diff --git a/.codespellrc b/.codespellrc
index a886554427d..e9be43f2160 100644
--- a/.codespellrc
+++ b/.codespellrc
@@ -1,4 +1,4 @@
 [codespell]
 skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb,components/wpa_supplicant/*,components/esp_wifi/*,*.pem
-ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane,assertIn,registr,oen
+ignore-words-list = ser,dout,rsource,fram,inout,shs,ans,aci,unstall,unstalling,hart,wheight,wel,ot,fane,assertIn,registr,oen,parms
 write-changes = true
diff --git a/.gitlab/CODEOWNERS b/.gitlab/CODEOWNERS
index b1ef4019e94..0ccfb93f8cf 100644
--- a/.gitlab/CODEOWNERS
+++ b/.gitlab/CODEOWNERS
@@ -159,8 +159,11 @@
 /components/xtensa/                   @esp-idf-codeowners/system
 
 /docs/                                      @esp-idf-codeowners/docs
+/docs/docs_not_updated/                     @esp-idf-codeowners/all-maintainers
 /docs/**/api-guides/tools/                  @esp-idf-codeowners/tools
 /docs/en/api-guides/core_dump.rst           @esp-idf-codeowners/debugging
+/docs/**/api-guides/wifi*                   @esp-idf-codeowners/wifi
+/docs/**/api-guides/esp-wifi-mesh.rst       @esp-idf-codeowners/wifi
 /docs/en/api-guides/jtag-debugging/         @esp-idf-codeowners/debugging
 /docs/**/api-reference/bluetooth/           @esp-idf-codeowners/bluetooth
 /docs/**/api-reference/network/             @esp-idf-codeowners/network @esp-idf-codeowners/wifi
diff --git a/.gitlab/ci/build.yml b/.gitlab/ci/build.yml
index ce6ccfd2764..ae3045175e2 100644
--- a/.gitlab/ci/build.yml
+++ b/.gitlab/ci/build.yml
@@ -1,7 +1,7 @@
 .build_template:
   stage: build
   extends:
-    - .after_script:build:ccache:upload-when-fail
+    - .after_script:build:ccache-show-stats:upload-failed-job-logs
   image: $ESP_ENV_IMAGE
   tags:
     - build
@@ -12,11 +12,11 @@
     IDF_CCACHE_ENABLE: "1"
   dependencies: []
 
-.build_cmake_template:
+.build_cmake_clang_template:
   extends:
     - .build_template
     - .before_script:build
-    - .after_script:build:ccache
+    - .after_script:build:ccache-show-stats
   dependencies: # set dependencies to null to avoid missing artifacts issue
   needs:
     - job: fast_template_app
@@ -34,29 +34,11 @@
       - "**/build*/size.json"
     expire_in: 1 week
     when: always
-  script:
-    # CI specific options start from "--parallel-count xxx". could ignore when running locally
-    - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v
-      -t $IDF_TARGET
-      --copy-sdkconfig
-      --parallel-count ${CI_NODE_TOTAL:-1}
-      --parallel-index ${CI_NODE_INDEX:-1}
-      --extra-preserve-dirs
-        examples/bluetooth/esp_ble_mesh/ble_mesh_console
-        examples/bluetooth/hci/controller_hci_uart_esp32
-        examples/wifi/iperf
-      --modified-components ${MR_MODIFIED_COMPONENTS}
-      --modified-files ${MR_MODIFIED_FILES}
-    # for detailed documents, please refer to .gitlab/ci/README.md#uploaddownload-artifacts-to-internal-minio-server
-    - python tools/ci/artifacts_handler.py upload
-
-.build_cmake_clang_template:
-  extends:
-    - .build_cmake_template
   variables:
     IDF_TOOLCHAIN: clang
     TEST_BUILD_OPTS_EXTRA: ""
     TEST_DIR: tools/test_apps/system/clang_build_test
+    PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
   script:
     # CI specific options start from "--parallel-count xxx". could ignore when running locally
     - run_cmd python tools/ci/ci_build_apps.py $TEST_DIR -v
@@ -126,7 +108,7 @@ gcc_static_analyzer:
     ANALYZING_APP: "examples/get-started/hello_world"
   script:
     - echo "CONFIG_COMPILER_STATIC_ANALYZER=y" >> ${ANALYZING_APP}/sdkconfig.defaults
-    - python -m idf_build_apps build -vv -p ${ANALYZING_APP} -t all
+    - python -m idf_build_apps build -v -p ${ANALYZING_APP} -t all
 
 ########################################
 # Clang Build Apps Without Tests Cases #
@@ -246,15 +228,16 @@ pytest_build_system_macos:
   extends:
     - .test_build_system_template
     - .before_script:build:macos
-    - .after_script:build:macos:upload-when-fail
+    - .after_script:build:macos:upload-failed-job-logs:ccache-show-stats
     - .rules:build:macos
   tags:
     - macos_shell
   parallel: 3
   variables:
-    PYENV_VERSION: "3.8"
-    CI_CCACHE_DISABLE: "1"  # ccache: error: Read-only file system
-
+    PYENV_VERSION: "3.9"
+    # CCACHE_DIR: "/cache/idf_ccache". On macOS, you cannot write to this folder due to insufficient permissions.
+    CCACHE_DIR: "" # ccache will use "$HOME/Library/Caches/ccache".
+    CCACHE_MAXSIZE: "5G" # To preserve the limited Macbook storage. CCACHE automatically prunes old caches to fit the set limit.
 build_docker:
   extends:
     - .before_script:minimal
@@ -309,7 +292,11 @@ generate_build_child_pipeline:
       - non_test_related_apps.txt
     expire_in: 1 week
     when: always
+  variables:
+    PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
   script:
+    # requires basic pytest dependencies
+    - run_cmd bash install.sh --enable-pytest
     - run_cmd python tools/ci/dynamic_pipelines/scripts/generate_build_child_pipeline.py
 
 build_child_pipeline:
diff --git a/.gitlab/ci/common.yml b/.gitlab/ci/common.yml
index 9708396b5fd..bfd4a700dcb 100644
--- a/.gitlab/ci/common.yml
+++ b/.gitlab/ci/common.yml
@@ -40,7 +40,7 @@ variables:
   GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags"
   # we're using .cache folder for caches
   GIT_CLEAN_FLAGS: -ffdx -e .cache/
-  LATEST_GIT_TAG: v5.4-dev
+  LATEST_GIT_TAG: v5.5-dev
 
   SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py"
   # by default we will fetch all submodules
@@ -55,15 +55,12 @@ variables:
   CHECKOUT_REF_SCRIPT: "$CI_PROJECT_DIR/tools/ci/checkout_project_ref.py"
 
   # Docker images
-  ESP_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-env-v5.4:1"
-  ESP_IDF_DOC_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-idf-doc-env-v5.4:1-1"
-  TARGET_TEST_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/target-test-env-v5.4:1"
+  ESP_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-env-v5.5:2"
+  ESP_IDF_DOC_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/esp-idf-doc-env-v5.5:2-1"
+  TARGET_TEST_ENV_IMAGE: "${CI_DOCKER_REGISTRY}/target-test-env-v5.5:2"
   SONARQUBE_SCANNER_IMAGE: "${CI_DOCKER_REGISTRY}/sonarqube-scanner:5"
   PRE_COMMIT_IMAGE: "${CI_DOCKER_REGISTRY}/esp-idf-pre-commit:1"
 
-  # target test repo parameters
-  TEST_ENV_CONFIG_REPO: "https://gitlab-ci-token:${BOT_TOKEN}@${CI_SERVER_HOST}:${CI_SERVER_PORT}/qa/ci-test-runner-configs.git"
-
   # cache python dependencies
   PIP_CACHE_DIR: "$CI_PROJECT_DIR/.cache/pip"
 
@@ -73,7 +70,7 @@ variables:
   CI_PYTHON_CONSTRAINT_BRANCH: ""
 
   # Update the filename for a specific ESP-IDF release. It is used only with CI_PYTHON_CONSTRAINT_BRANCH.
-  CI_PYTHON_CONSTRAINT_FILE: "espidf.constraints.v5.4.txt"
+  CI_PYTHON_CONSTRAINT_FILE: "espidf.constraints.v5.5.txt"
 
   # Set this variable to repository name of a Python tool you wish to install and test in the context of ESP-IDF CI.
   # Keep the variable empty when not used.
@@ -144,40 +141,48 @@ variables:
     export IDF_MIRROR_PREFIX_MAP=
   fi
 
-  # install latest python packages
-  # target test jobs
-  if [[ "${CI_JOB_STAGE}" == "target_test" ]]; then
-    run_cmd bash install.sh --enable-ci --enable-pytest --enable-test-specific
-  elif [[ "${CI_JOB_STAGE}" == "build_doc" ]]; then
-    run_cmd bash install.sh --enable-ci --enable-docs
-  elif [[ "${CI_JOB_STAGE}" == "build" ]]; then
-    run_cmd bash install.sh --enable-ci
-  else
-    if ! echo "${CI_JOB_NAME}" | egrep ".*pytest.*"; then
+  if [[ "${CI_JOB_STAGE}" != "target_test" ]]; then
+    section_start "running_install_sh" "Running install.sh"
+    if [[ "${CI_JOB_STAGE}" == "build_doc" ]]; then
+      run_cmd bash install.sh --enable-ci --enable-docs
+    elif [[ "${CI_JOB_STAGE}" == "build" ]]; then
       run_cmd bash install.sh --enable-ci
     else
-      run_cmd bash install.sh --enable-ci --enable-pytest --enable-test-specific
+      if ! echo "${CI_JOB_NAME}" | egrep ".*pytest.*"; then
+        run_cmd bash install.sh --enable-ci
+      else
+        run_cmd bash install.sh --enable-ci --enable-pytest --enable-test-specific
+      fi
     fi
+    section_end "running_install_sh"
+  else
+    section_start "install_python_env" "Install Python environment"
+    run_cmd python tools/idf_tools.py install-python-env --features ci,pytest,test-specific
+    section_end "install_python_env"
+  fi
+
+  if [[ ! -z "$INSTALL_EXTRA_TOOLS" ]]; then
+    section_start "installing_optional_tools" "Install optional tools ${INSTALL_EXTRA_TOOLS}"
+    $IDF_PATH/tools/idf_tools.py --non-interactive install $INSTALL_EXTRA_TOOLS
+    section_end "installing_optional_tools"
   fi
 
-  # Install esp-clang if necessary
+  # Install esp-clang if necessary (esp-clang is separately installed)
   if [[ "$IDF_TOOLCHAIN" == "clang" && -z "$CI_CLANG_DISTRO_URL" ]]; then
     $IDF_PATH/tools/idf_tools.py --non-interactive install esp-clang
   fi
 
-  # Install QEMU if necessary
-  if [[ ! -z "$INSTALL_QEMU" ]]; then
-    $IDF_PATH/tools/idf_tools.py --non-interactive install qemu-xtensa qemu-riscv32
+  if [[ "${CI_JOB_STAGE}" == "target_test" ]]; then
+    section_start "IDF_SKIP_TOOLS_CHECK" "Skip required tools check"
+    export IDF_SKIP_TOOLS_CHECK=1
+    section_end "IDF_SKIP_TOOLS_CHECK"
   fi
-
-  # Since the version 3.21 CMake passes source files and include dirs to ninja using absolute paths.
-  # Needed for pytest junit reports.
-  $IDF_PATH/tools/idf_tools.py --non-interactive install cmake
-
+  section_start "source_export" "Source export.sh"
   source ./export.sh
+  section_end "source_export"
 
   # Custom clang toolchain
-  if [[ ! -z "$CI_CLANG_DISTRO_URL" ]]; then
+  if [[ "$IDF_TOOLCHAIN" == "clang" && ! -z "$CI_CLANG_DISTRO_URL" ]]; then
     echo "Using custom clang from ${CI_CLANG_DISTRO_URL}"
     wget $CI_CLANG_DISTRO_URL
     ARCH_NAME=$(basename $CI_CLANG_DISTRO_URL)
@@ -201,6 +206,8 @@ variables:
     rm -rf ${CI_PYTHON_TOOL_REPO}
   fi
 
+  info "setup tools and python venv done"
+
 .show_ccache_statistics: &show_ccache_statistics |
   # Show ccache statistics if enabled globally
   test "$CI_CCACHE_STATS" == 1 && test -n "$(which ccache)" && ccache --show-stats -vv || true
@@ -225,18 +232,20 @@ variables:
     - export IDF_TOOLS_PATH="${HOME}/.espressif_runner_${CI_RUNNER_ID}_${CI_CONCURRENT_ID}"
     # remove idf-env.json, since it may contains enabled "features"
     - rm -f $IDF_TOOLS_PATH/idf-env.json
-    - $IDF_PATH/tools/idf_tools.py --non-interactive install cmake ninja
     # This adds tools (compilers) and the version-specific Python environment to PATH
     - *setup_tools_and_idf_python_venv
     - fetch_submodules
+  variables:
+    INSTALL_EXTRA_TOOLS: cmake ninja
 
-.after_script:build:macos:upload-when-fail:
+.after_script:build:macos:upload-failed-job-logs:ccache-show-stats:
   after_script:
     # macos is running shell executor, which means it would use
     # the system installed /usr/local/bin/python3 by default.
     # Ensure pyenv and PYENV_VERSION installed
     - eval "$(pyenv init -)"
     - *upload_failed_job_log_artifacts
+    - *show_ccache_statistics
 
 .before_script:build:
   before_script:
@@ -247,11 +256,11 @@ variables:
     - export EXTRA_CFLAGS=${PEDANTIC_CFLAGS}
     - export EXTRA_CXXFLAGS=${PEDANTIC_CXXFLAGS}
 
-.after_script:build:ccache:
+.after_script:build:ccache-show-stats:
   after_script:
     - *show_ccache_statistics
 
-.after_script:build:ccache:upload-when-fail:
+.after_script:build:ccache-show-stats:upload-failed-job-logs:
   after_script:
     - *show_ccache_statistics
     - *upload_failed_job_log_artifacts
diff --git a/.gitlab/ci/host-test.yml b/.gitlab/ci/host-test.yml
index b383c77b0a4..e1dc5f59a4c 100644
--- a/.gitlab/ci/host-test.yml
+++ b/.gitlab/ci/host-test.yml
@@ -195,7 +195,7 @@ test_tools:
       junit: ${IDF_PATH}/XUNIT_*.xml
   variables:
     LC_ALL: C.UTF-8
-    INSTALL_QEMU: 1  # for test_idf_qemu.py
+    INSTALL_EXTRA_TOOLS: "qemu-xtensa qemu-riscv32"  # for test_idf_qemu.py
   script:
     - stat=0
     - cd ${IDF_PATH}/tools/ci/test_autocomplete
@@ -282,9 +282,10 @@ test_pytest_qemu:
       junit: XUNIT_RESULT.xml
   parallel:
     matrix:
-      - IDF_TARGET: [esp32, esp32c3]
-  variables:
-    INSTALL_QEMU: 1
+      - IDF_TARGET: "esp32"
+        INSTALL_EXTRA_TOOLS: "qemu-xtensa"
+      - IDF_TARGET: "esp32c3"
+        INSTALL_EXTRA_TOOLS: "qemu-riscv32"
   script:
     - run_cmd python tools/ci/ci_build_apps.py . -v
       --target $IDF_TARGET
@@ -346,9 +347,10 @@ test_pytest_macos:
     reports:
       junit: XUNIT_RESULT.xml
   variables:
+    PYENV_VERSION: "3.9"
     PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
   script:
-    - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -vv
+    - run_cmd python tools/ci/ci_build_apps.py components examples tools/test_apps -v
       --target linux
       --pytest-apps
       -m \"host_test and macos_shell\"
diff --git a/.gitlab/ci/pre_check.yml b/.gitlab/ci/pre_check.yml
index 7bf24fb158f..5b1adf24297 100644
--- a/.gitlab/ci/pre_check.yml
+++ b/.gitlab/ci/pre_check.yml
@@ -44,6 +44,9 @@ check_blobs:
     - IDF_TARGET=esp32c2 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
     - IDF_TARGET=esp32c3 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
     - IDF_TARGET=esp32c6 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
+    - IDF_TARGET=esp32c5 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
+    - IDF_TARGET=esp32c61 $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
+    - IDF_TARGET=esp32_host $IDF_PATH/components/esp_wifi/test_md5/test_md5.sh
     # Check if Coexistence library header files match between IDF and the version used when compiling the libraries
     - IDF_TARGET=esp32 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
     - IDF_TARGET=esp32s2 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
@@ -52,6 +55,8 @@ check_blobs:
     - IDF_TARGET=esp32c3 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
     - IDF_TARGET=esp32c6 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
     - IDF_TARGET=esp32h2 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
+    - IDF_TARGET=esp32c5 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
+    - IDF_TARGET=esp32c61 $IDF_PATH/components/esp_coex/test_md5/test_md5.sh
     # Check if Wi-Fi, PHY, BT blobs contain references to specific symbols
     - bash $IDF_PATH/tools/ci/check_blobs.sh
 
@@ -112,8 +117,10 @@ check_test_scripts_build_test_rules:
   extends:
     - .pre_check_template
     - .before_script:build
+  variables:
+    PYTEST_IGNORE_COLLECT_IMPORT_ERROR: "1"
   script:
-    # required pytest related packages
+    # requires basic pytest dependencies
     - run_cmd bash install.sh --enable-pytest
     - python tools/ci/check_build_test_rules.py check-test-scripts examples/ tools/test_apps components
 
@@ -176,12 +183,24 @@ baseline_manifest_sha:
   tags: [fast_run, shiny]
   script:
     - |
-      if [ -n "$CI_MERGE_REQUEST_DIFF_BASE_SHA" ]; then
+      # merged results pipelines, by default
+      # diff between target-branch-head and merged-result-head
+      if [ -n "$CI_MERGE_REQUEST_TARGET_BRANCH_SHA" ]; then
+        git fetch origin $CI_MERGE_REQUEST_TARGET_BRANCH_SHA --depth=1
+        git checkout FETCH_HEAD
+        idf-build-apps dump-manifest-sha \
+          --manifest-files $(find . -name ".build-test-rules.yml" | xargs) \
+          --output .manifest_sha
+      # merge request pipelines, when the mr got conflicts
+      # diff between diff-base-sha and merge-request-head
+      elif [ -n "$CI_MERGE_REQUEST_DIFF_BASE_SHA" ]; then
         git fetch origin $CI_MERGE_REQUEST_DIFF_BASE_SHA --depth=1
         git checkout FETCH_HEAD
         idf-build-apps dump-manifest-sha \
           --manifest-files $(find . -name ".build-test-rules.yml" | xargs) \
           --output .manifest_sha
+      # other pipelines, like the protected branches pipelines
+      # not triggered in this job
       fi
   artifacts:
     paths:
diff --git a/.gitlab/ci/rules.yml b/.gitlab/ci/rules.yml
index cc386ac506b..7b348fbe095 100644
--- a/.gitlab/ci/rules.yml
+++ b/.gitlab/ci/rules.yml
@@ -261,14 +261,14 @@
     - <<: *if-dev-push
       changes: *patterns-python-files
 
-.rules:patterns:static-code-analysis-preview:
-  rules:
-    - <<: *if-dev-push
-      changes: *patterns-c-files
-    - <<: *if-dev-push
-      changes: *patterns-python-files
-    - <<: *if-dev-push
-      changes: *patterns-sonarqube-files
+#.rules:patterns:static-code-analysis-preview:
+#  rules:
+#    - <<: *if-dev-push
+#      changes: *patterns-c-files
+#    - <<: *if-dev-push
+#      changes: *patterns-python-files
+#    - <<: *if-dev-push
+#      changes: *patterns-sonarqube-files
 
 .rules:patterns:idf-pytest-plugin:
   rules:
diff --git a/.gitlab/ci/static-code-analysis.yml b/.gitlab/ci/static-code-analysis.yml
index d22f524d54a..2773d2cbf7f 100644
--- a/.gitlab/ci/static-code-analysis.yml
+++ b/.gitlab/ci/static-code-analysis.yml
@@ -38,84 +38,84 @@ check_pylint:
       fi
     - if [ -z "$files" ]; then echo "No python files found"; exit 0; fi
     - run_cmd pylint --exit-zero --load-plugins=pylint_gitlab --output-format=gitlab-codeclimate:pylint.json $files
-
-# build stage
-# Sonarqube related jobs put here for this reason:
-# Here we have two jobs. code_quality_check and code_quality_report.
 #
-# code_quality_check will analyze the code changes between your MR and
-# code repo stored in sonarqube server. The analysis result is only shown in
-# the comments under this MR and won't be transferred to the server.
+## build stage
+## Sonarqube related jobs put here for this reason:
+## Here we have two jobs. code_quality_check and code_quality_report.
+##
+## code_quality_check will analyze the code changes between your MR and
+## code repo stored in sonarqube server. The analysis result is only shown in
+## the comments under this MR and won't be transferred to the server.
+##
+## code_quality_report will analyze and transfer both of the newly added code
+## and the analysis result to the server.
+##
+## Put in the front to ensure that the newly merged code can be stored in
+## sonarqube server ASAP, in order to avoid reporting unrelated code issues
+#.sonar_scan_template:
+#  stage: build
+#  extends: .pre_check_template
+#  # full clone since this image does not support fetch --shallow-since-cutoff
+#  # shiny runners are used for full clone
+#  tags: [build, shiny]
+#  image: $SONARQUBE_SCANNER_IMAGE
+#  before_script:
+#    - source tools/ci/utils.sh
+#    - export PYTHONPATH="$CI_PROJECT_DIR/tools:$CI_PROJECT_DIR/tools/ci/python_packages:$PYTHONPATH"
+#    - fetch_submodules
+#    # Exclude the submodules, all paths ends with /**
+#    - submodules=$(get_all_submodules)
+#    # get all exclude paths specified in tools/ci/sonar_exclude_list.txt | ignore lines start with # | xargs | replace all <space> to <comma>
+#    - custom_excludes=$(cat $CI_PROJECT_DIR/tools/ci/sonar_exclude_list.txt | grep -v '^#' | xargs | sed -e 's/ /,/g')
+#    # Exclude the report dir as well
+#    - export EXCLUSIONS="$custom_excludes,$submodules"
+#    - export SONAR_SCANNER_OPTS="-Xmx2048m"
+#  variables:
+#    GIT_DEPTH: 0
+#    REPORT_PATTERN: clang_tidy_reports/**/*.txt
+#  artifacts:
+#    paths:
+#      - $REPORT_PATTERN
+#    expire_in: 1 week
+#    when: always
+#  dependencies:  # Here is not a hard dependency relationship, could be skipped when only python files changed. so we do not use "needs" here.
+#    - clang_tidy_check
 #
-# code_quality_report will analyze and transfer both of the newly added code
-# and the analysis result to the server.
+#code_quality_check:
+#  extends:
+#    - .sonar_scan_template
+#    - .rules:patterns:static-code-analysis-preview
+#  allow_failure: true  # it's using exit code to indicate the code analysis result,
+#                       # we don't want to block ci when critical issues founded
+#  script:
+#    - export CI_MERGE_REQUEST_COMMITS=$(python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py commits --src-branch ${CI_COMMIT_REF_NAME} | tr '\n' ',')
+#    # test if this branch have merge request, if not, exit 0
+#    - test -n "$CI_MERGE_REQUEST_IID" || exit 0
+#    - test -n "$CI_MERGE_REQUEST_COMMITS" || exit 0
+#    - sonar-scanner
+#      -Dsonar.analysis.mode=preview
+#      -Dsonar.branch.name=$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
+#      -Dsonar.cxx.clangtidy.reportPath=$REPORT_PATTERN
+#      -Dsonar.exclusions=$EXCLUSIONS
+#      -Dsonar.gitlab.ci_merge_request_iid=$CI_MERGE_REQUEST_IID
+#      -Dsonar.gitlab.commit_sha=$CI_MERGE_REQUEST_COMMITS
+#      -Dsonar.gitlab.merge_request_discussion=true
+#      -Dsonar.gitlab.ref_name=$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
+#      -Dsonar.host.url=$SONAR_HOST_URL
+#      -Dsonar.login=$SONAR_LOGIN
 #
-# Put in the front to ensure that the newly merged code can be stored in
-# sonarqube server ASAP, in order to avoid reporting unrelated code issues
-.sonar_scan_template:
-  stage: build
-  extends: .pre_check_template
-  # full clone since this image does not support fetch --shallow-since-cutoff
-  # shiny runners are used for full clone
-  tags: [build, shiny]
-  image: $SONARQUBE_SCANNER_IMAGE
-  before_script:
-    - source tools/ci/utils.sh
-    - export PYTHONPATH="$CI_PROJECT_DIR/tools:$CI_PROJECT_DIR/tools/ci/python_packages:$PYTHONPATH"
-    - fetch_submodules
-    # Exclude the submodules, all paths ends with /**
-    - submodules=$(get_all_submodules)
-    # get all exclude paths specified in tools/ci/sonar_exclude_list.txt | ignore lines start with # | xargs | replace all <space> to <comma>
-    - custom_excludes=$(cat $CI_PROJECT_DIR/tools/ci/sonar_exclude_list.txt | grep -v '^#' | xargs | sed -e 's/ /,/g')
-    # Exclude the report dir as well
-    - export EXCLUSIONS="$custom_excludes,$submodules"
-    - export SONAR_SCANNER_OPTS="-Xmx2048m"
-  variables:
-    GIT_DEPTH: 0
-    REPORT_PATTERN: clang_tidy_reports/**/*.txt
-  artifacts:
-    paths:
-      - $REPORT_PATTERN
-    expire_in: 1 week
-    when: always
-  dependencies:  # Here is not a hard dependency relationship, could be skipped when only python files changed. so we do not use "needs" here.
-    - clang_tidy_check
-
-code_quality_check:
-  extends:
-    - .sonar_scan_template
-    - .rules:patterns:static-code-analysis-preview
-  allow_failure: true  # it's using exit code to indicate the code analysis result,
-                       # we don't want to block ci when critical issues founded
-  script:
-    - export CI_MERGE_REQUEST_COMMITS=$(python ${CI_PROJECT_DIR}/tools/ci/ci_get_mr_info.py commits --src-branch ${CI_COMMIT_REF_NAME} | tr '\n' ',')
-    # test if this branch have merge request, if not, exit 0
-    - test -n "$CI_MERGE_REQUEST_IID" || exit 0
-    - test -n "$CI_MERGE_REQUEST_COMMITS" || exit 0
-    - sonar-scanner
-      -Dsonar.analysis.mode=preview
-      -Dsonar.branch.name=$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
-      -Dsonar.cxx.clangtidy.reportPath=$REPORT_PATTERN
-      -Dsonar.exclusions=$EXCLUSIONS
-      -Dsonar.gitlab.ci_merge_request_iid=$CI_MERGE_REQUEST_IID
-      -Dsonar.gitlab.commit_sha=$CI_MERGE_REQUEST_COMMITS
-      -Dsonar.gitlab.merge_request_discussion=true
-      -Dsonar.gitlab.ref_name=$CI_MERGE_REQUEST_SOURCE_BRANCH_NAME
-      -Dsonar.host.url=$SONAR_HOST_URL
-      -Dsonar.login=$SONAR_LOGIN
-
-code_quality_report:
-  extends:
-    - .sonar_scan_template
-    - .rules:protected
-  allow_failure: true  # it's using exit code to indicate the code analysis result,
-                       # we don't want to block ci when critical issues founded
-  script:
-    - sonar-scanner
-      -Dsonar.branch.name=$CI_COMMIT_REF_NAME
-      -Dsonar.cxx.clangtidy.reportPath=$REPORT_PATTERN
-      -Dsonar.exclusions=$EXCLUSIONS
-      -Dsonar.gitlab.commit_sha=$PIPELINE_COMMIT_SHA
-      -Dsonar.gitlab.ref_name=$CI_COMMIT_REF_NAME
-      -Dsonar.host.url=$SONAR_HOST_URL
-      -Dsonar.login=$SONAR_LOGIN
+#code_quality_report:
+#  extends:
+#    - .sonar_scan_template
+#    - .rules:protected
+#  allow_failure: true  # it's using exit code to indicate the code analysis result,
+#                       # we don't want to block ci when critical issues founded
+#  script:
+#    - sonar-scanner
+#      -Dsonar.branch.name=$CI_COMMIT_REF_NAME
+#      -Dsonar.cxx.clangtidy.reportPath=$REPORT_PATTERN
+#      -Dsonar.exclusions=$EXCLUSIONS
+#      -Dsonar.gitlab.commit_sha=$PIPELINE_COMMIT_SHA
+#      -Dsonar.gitlab.ref_name=$CI_COMMIT_REF_NAME
+#      -Dsonar.host.url=$SONAR_HOST_URL
+#      -Dsonar.login=$SONAR_LOGIN
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 20ef5b96896..b4dbce1bc23 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -251,7 +251,9 @@ if(CMAKE_C_COMPILER_ID MATCHES "GNU")
 endif()
 
 if(CMAKE_C_COMPILER_ID MATCHES "Clang")
-    list(APPEND compile_options "-fno-use-cxa-atexit")
+    list(APPEND compile_options "-fno-use-cxa-atexit")  # TODO IDF-10934
+else()
+    list(APPEND cxx_compile_options "-fuse-cxa-atexit")
 endif()
 
 if(COMPILER_RT_LIB_NAME)
diff --git a/README.md b/README.md
index ce807d91da8..d90e7e0eee9 100644
--- a/README.md
+++ b/README.md
@@ -15,17 +15,18 @@ ESP-IDF is the development framework for Espressif SoCs supported on Windows, Li
 
 The following table shows ESP-IDF support of Espressif SoCs where ![alt text][preview] and ![alt text][supported] denote preview status and support, respectively. The preview support is usually limited in time and intended for beta versions of chips. Please use an ESP-IDF release where the desired SoC is already supported.
 
-|Chip         |          v5.0          |         v5.1           |         v5.2           |         v5.3           |                                                            |
-|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------------------------------------------- |
-|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                            |
-|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_S3) |
-|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-C2) |
-|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_C6) |
-|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32_H2) |
-|ESP32-P4     |                        |                        |                        | ![alt text][supported] | [Announcement](https://www.espressif.com/en/news/ESP32-P4) |
-|ESP32-C5     |                        |                        |                        | ![alt text][preview]   | [Announcement](https://www.espressif.com/en/news/ESP32-C5) |
+|Chip         |          v5.0          |         v5.1           |         v5.2           |         v5.3           |          v5.4           |                                                                     |
+|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: |  :--------------------: |:------------------------------------------------------------------- |
+|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |                                                                     |
+|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |                                                                     |
+|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |                                                                     |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_S3)           |
+|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-C2)           |
+|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_C6)           |
+|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32_H2)           |
+|ESP32-P4     |                        |                        |                        | ![alt text][supported] |  ![alt text][supported] |[Announcement](https://www.espressif.com/en/news/ESP32-P4)           |
+|ESP32-C5     |                        |                        |                        |                        |  ![alt text][preview]   |[Announcement](https://www.espressif.com/en/news/ESP32-C5)           |
+|ESP32-C61    |                        |                        |                        |                        |  ![alt text][preview]   |[Announcement](https://www.espressif.com/en/products/socs/esp32-c61) |
 
 [supported]: https://img.shields.io/badge/-supported-green "supported"
 [preview]: https://img.shields.io/badge/-preview-orange "preview"
diff --git a/README_CN.md b/README_CN.md
index e8f21600d1d..6aeb55a5ac7 100644
--- a/README_CN.md
+++ b/README_CN.md
@@ -15,17 +15,18 @@ ESP-IDF 是乐鑫官方推出的物联网开发框架，支持 Windows、Linux 
 
 下表总结了乐鑫芯片在 ESP-IDF 各版本中的支持状态，其中 ![alt text][supported] 代表已支持，![alt text][preview] 代表目前处于预览支持状态。预览支持状态通常有时间限制，而且仅适用于测试版芯片。请确保使用与芯片相匹配的 ESP-IDF 版本。
 
-|芯片         |          v5.0          |          v5.1          |          v5.2          |          v5.3          |                                                                 |
-|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :-------------------------------------------------------------- |
-|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                 |
-|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3) |
-|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2) |
-|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6) |
-|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2) |
-|ESP32-P4     |                        |                        |                        | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4) |
-|ESP32-C5     |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5) |
+|芯片         |          v5.0          |          v5.1          |          v5.2          |          v5.3          |          v5.4          |                                                                           |
+|:----------- | :---------------------:| :--------------------: | :--------------------: | :--------------------: | :--------------------: | :------------------------------------------------------------------------ |
+|ESP32        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                           |
+|ESP32-S2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                           |
+|ESP32-C3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] |                                                                           |
+|ESP32-S3     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_S3)           |
+|ESP32-C2     | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C2)           |
+|ESP32-C6     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_C6)           |
+|ESP32-H2     |                        | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32_H2)           |
+|ESP32-P4     |                        |                        |                        | ![alt text][supported] | ![alt text][supported] | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-P4)           |
+|ESP32-C5     |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/news/ESP32-C5)           |
+|ESP32-C61    |                        |                        |                        |                        | ![alt text][preview]   | [芯片发布公告](https://www.espressif.com/zh-hans/products/socs/esp32-c61) |
 
 [supported]: https://img.shields.io/badge/-%E6%94%AF%E6%8C%81-green "supported"
 [preview]: https://img.shields.io/badge/-%E9%A2%84%E8%A7%88-orange "preview"
diff --git a/components/app_trace/port/port_uart.c b/components/app_trace/port/port_uart.c
index 053f235cdbf..c4146d09d3e 100644
--- a/components/app_trace/port/port_uart.c
+++ b/components/app_trace/port/port_uart.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -218,6 +218,13 @@ static esp_err_t esp_apptrace_uart_init(esp_apptrace_uart_data_t *hw_data)
         hw_data->message_buff_overflow = false;
         hw_data->circular_buff_overflow = false;
 
+        assert((hw_data->port_num <= SOC_UART_NUM) && "Not possible to configure UART. Please check selected UART port");
+
+        int source_clk = UART_SCLK_DEFAULT;
+#if SOC_UART_LP_NUM > 0
+        if (hw_data->port_num >= SOC_UART_HP_NUM)
+            source_clk = LP_UART_SCLK_DEFAULT;
+#endif
 
         const uart_config_t uart_config = {
             .baud_rate = CONFIG_APPTRACE_UART_BAUDRATE,
@@ -225,7 +232,7 @@ static esp_err_t esp_apptrace_uart_init(esp_apptrace_uart_data_t *hw_data)
             .parity = UART_PARITY_DISABLE,
             .stop_bits = UART_STOP_BITS_1,
             .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
-            .source_clk = UART_SCLK_DEFAULT,
+            .source_clk = source_clk,
         };
         ESP_LOGI(TAG, "UART baud rate: %i", CONFIG_APPTRACE_UART_BAUDRATE);
         // We won't use a buffer for sending data.
diff --git a/components/app_trace/port/riscv/port.c b/components/app_trace/port/riscv/port.c
index 3e5ceca966c..14fe223623c 100644
--- a/components/app_trace/port/riscv/port.c
+++ b/components/app_trace/port/riscv/port.c
@@ -57,7 +57,13 @@ static bool esp_apptrace_riscv_host_data_pending(void);
 
 const static char *TAG = "esp_apptrace";
 
-static esp_apptrace_riscv_ctrl_block_t s_tracing_ctrl[CONFIG_FREERTOS_NUMBER_OF_CORES];
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+#define APPTRACE_DRAM_ATTR TCM_DRAM_ATTR
+#else
+#define APPTRACE_DRAM_ATTR
+#endif
+
+static APPTRACE_DRAM_ATTR esp_apptrace_riscv_ctrl_block_t s_tracing_ctrl[CONFIG_FREERTOS_NUMBER_OF_CORES];
 
 esp_apptrace_hw_t *esp_apptrace_jtag_hw_get(void **data)
 {
@@ -92,7 +98,7 @@ esp_apptrace_hw_t *esp_apptrace_jtag_hw_get(void **data)
 }
 
 /* Advertises apptrace control block address to host.
-   This function can be overriden with custom implementation,
+   This function can be overridden with custom implementation,
    e.g. OpenOCD flasher stub use own implementation of it. */
 __attribute__((weak)) int esp_apptrace_advertise_ctrl_block(void *ctrl_block_addr)
 {
@@ -103,7 +109,7 @@ __attribute__((weak)) int esp_apptrace_advertise_ctrl_block(void *ctrl_block_add
 }
 
 /* Returns up buffers config.
-   This function can be overriden with custom implementation,
+   This function can be overridden with custom implementation,
    e.g. OpenOCD flasher stub use own implementation of it. */
 __attribute__((weak)) void esp_apptrace_get_up_buffers(esp_apptrace_mem_block_t mem_blocks_cfg[2])
 {
@@ -165,7 +171,7 @@ static esp_err_t esp_apptrace_riscv_init(esp_apptrace_riscv_data_t *hw_data)
     }
     // notify host about control block address
     int res = esp_apptrace_advertise_ctrl_block(&s_tracing_ctrl[core_id]);
-    assert(res == 0 && "Falied to send config to host!");
+    assert(res == 0 && "Failed to send config to host!");
 
     return ESP_OK;
 }
diff --git a/components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c b/components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c
index fcf33d365af..c01cbed67ea 100644
--- a/components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c
+++ b/components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: BSD-1-Clause
  *
- * SPDX-FileContributor: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2017-2024 Espressif Systems (Shanghai) CO LTD
  */
 /*********************************************************************
 *                    SEGGER Microcontroller GmbH                     *
@@ -58,6 +58,7 @@ File    : SEGGER_SYSVIEW_Config_FreeRTOS.c
 Purpose : Sample setup configuration of SystemView with FreeRTOS.
 Revision: $Rev: 7745 $
 */
+#include <string.h>
 #include "sdkconfig.h"
 #include "freertos/FreeRTOS.h"
 #include "SEGGER_SYSVIEW.h"
@@ -156,15 +157,16 @@ static esp_apptrace_lock_t s_sys_view_lock = {.mux = portMUX_INITIALIZER_UNLOCKE
 *    Sends SystemView description strings.
 */
 static void _cbSendSystemDesc(void) {
-    char irq_str[32];
+    char irq_str[32] = "I#";
     SEGGER_SYSVIEW_SendSysDesc("N="SYSVIEW_APP_NAME",D="SYSVIEW_DEVICE_NAME",C="SYSVIEW_CORE_NAME",O=FreeRTOS");
-    snprintf(irq_str, sizeof(irq_str), "I#%d=SysTick", SYSTICK_INTR_ID);
+    strcat(itoa(SYSTICK_INTR_ID, irq_str + 2, 10), "=SysTick");
     SEGGER_SYSVIEW_SendSysDesc(irq_str);
     size_t isr_count = sizeof(esp_isr_names)/sizeof(esp_isr_names[0]);
     for (size_t i = 0; i < isr_count; ++i) {
         if (esp_isr_names[i] == NULL || (ETS_INTERNAL_INTR_SOURCE_OFF + i) == SYSTICK_INTR_ID)
             continue;
-        snprintf(irq_str, sizeof(irq_str), "I#%d=%s", ETS_INTERNAL_INTR_SOURCE_OFF + i, esp_isr_names[i]);
+        strcat(itoa(ETS_INTERNAL_INTR_SOURCE_OFF + i, irq_str + 2, 10), "=");
+        strncat(irq_str, esp_isr_names[i], sizeof(irq_str) - strlen(irq_str) - 1);
         SEGGER_SYSVIEW_SendSysDesc(irq_str);
     }
 }
diff --git a/components/app_update/esp_ota_ops.c b/components/app_update/esp_ota_ops.c
index fdea76bddde..e4f70553454 100644
--- a/components/app_update/esp_ota_ops.c
+++ b/components/app_update/esp_ota_ops.c
@@ -31,13 +31,19 @@
 #include "esp_attr.h"
 #include "esp_bootloader_desc.h"
 #include "esp_flash.h"
+#include "esp_flash_internal.h"
 
 #define SUB_TYPE_ID(i) (i & 0x0F)
+#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
 
 /* Partial_data is word aligned so no reallocation is necessary for encrypted flash write */
 typedef struct ota_ops_entry_ {
     uint32_t handle;
-    const esp_partition_t *part;
+    struct {
+        const esp_partition_t *staging;      /*!< New image will be downloaded in this staging partition. */
+        const esp_partition_t *final;        /*!< Final destination partition which is intended to be updated. Its type/subtype shall be used for verification. */
+        bool finalize_with_copy;             /*!< Flag to copy the image from staging partition to the final partition at the end of OTA update */
+    } partition;
     bool need_erase;
     uint32_t wrote_size;
     uint8_t partial_bytes;
@@ -52,6 +58,8 @@ static uint32_t s_ota_ops_last_handle = 0;
 
 const static char *TAG = "esp_ota_ops";
 
+static ota_ops_entry_t *get_ota_ops_entry(esp_ota_handle_t handle);
+
 /* Return true if this is an OTA app partition */
 static bool is_ota_partition(const esp_partition_t *p)
 {
@@ -114,8 +122,6 @@ static esp_ota_img_states_t set_new_state_otadata(void)
 esp_err_t esp_ota_begin(const esp_partition_t *partition, size_t image_size, esp_ota_handle_t *out_handle)
 {
     ota_ops_entry_t *new_entry;
-    esp_err_t ret = ESP_OK;
-
     if ((partition == NULL) || (out_handle == NULL)) {
         return ESP_ERR_INVALID_ARG;
     }
@@ -125,36 +131,26 @@ esp_err_t esp_ota_begin(const esp_partition_t *partition, size_t image_size, esp
         return ESP_ERR_NOT_FOUND;
     }
 
-    if (!is_ota_partition(partition)) {
-        return ESP_ERR_INVALID_ARG;
-    }
+    if (partition->type == ESP_PARTITION_TYPE_APP) {
+        // The staging partition cannot be of type Factory, but the final partition can be.
+        if (!is_ota_partition(partition)) {
+           return ESP_ERR_INVALID_ARG;
+        }
 
-    const esp_partition_t* running_partition = esp_ota_get_running_partition();
-    if (partition == running_partition) {
-        return ESP_ERR_OTA_PARTITION_CONFLICT;
-    }
+        const esp_partition_t* running_partition = esp_ota_get_running_partition();
+        if (partition == running_partition) {
+            return ESP_ERR_OTA_PARTITION_CONFLICT;
+        }
 
 #ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
-    esp_ota_img_states_t ota_state_running_part;
-    if (esp_ota_get_state_partition(running_partition, &ota_state_running_part) == ESP_OK) {
-        if (ota_state_running_part == ESP_OTA_IMG_PENDING_VERIFY) {
-            ESP_LOGE(TAG, "Running app has not confirmed state (ESP_OTA_IMG_PENDING_VERIFY)");
-            return ESP_ERR_OTA_ROLLBACK_INVALID_STATE;
+        esp_ota_img_states_t ota_state_running_part;
+        if (esp_ota_get_state_partition(running_partition, &ota_state_running_part) == ESP_OK) {
+            if (ota_state_running_part == ESP_OTA_IMG_PENDING_VERIFY) {
+                ESP_LOGE(TAG, "Running app has not confirmed state (ESP_OTA_IMG_PENDING_VERIFY)");
+                return ESP_ERR_OTA_ROLLBACK_INVALID_STATE;
+            }
         }
-    }
 #endif
-
-    if (image_size != OTA_WITH_SEQUENTIAL_WRITES) {
-        // If input image size is 0 or OTA_SIZE_UNKNOWN, erase entire partition
-        if ((image_size == 0) || (image_size == OTA_SIZE_UNKNOWN)) {
-            ret = esp_partition_erase_range(partition, 0, partition->size);
-        } else {
-            const int aligned_erase_size = (image_size + partition->erase_size - 1) & ~(partition->erase_size - 1);
-            ret = esp_partition_erase_range(partition, 0, aligned_erase_size);
-        }
-        if (ret != ESP_OK) {
-            return ret;
-        }
     }
 
     new_entry = (ota_ops_entry_t *) calloc(1, sizeof(ota_ops_entry_t));
@@ -164,10 +160,60 @@ esp_err_t esp_ota_begin(const esp_partition_t *partition, size_t image_size, esp
 
     LIST_INSERT_HEAD(&s_ota_ops_entries_head, new_entry, entries);
 
-    new_entry->part = partition;
+    new_entry->partition.staging = partition;
+    new_entry->partition.final = partition;
+    new_entry->partition.finalize_with_copy = false;
     new_entry->handle = ++s_ota_ops_last_handle;
     new_entry->need_erase = (image_size == OTA_WITH_SEQUENTIAL_WRITES);
     *out_handle = new_entry->handle;
+
+    if (partition->type == ESP_PARTITION_TYPE_BOOTLOADER) {
+        esp_image_bootloader_offset_set(partition->address);
+    }
+    if (partition->type == ESP_PARTITION_TYPE_BOOTLOADER || partition->type == ESP_PARTITION_TYPE_PARTITION_TABLE) {
+        esp_flash_set_dangerous_write_protection(esp_flash_default_chip, false);
+    }
+
+    if (image_size != OTA_WITH_SEQUENTIAL_WRITES) {
+        // If input image size is 0 or OTA_SIZE_UNKNOWN, erase entire partition
+        size_t erase_size;
+        if ((image_size == 0) || (image_size == OTA_SIZE_UNKNOWN)) {
+            erase_size = partition->size;
+        } else {
+            erase_size = ALIGN_UP(image_size, partition->erase_size);
+        }
+        return esp_partition_erase_range(partition, 0, erase_size);
+    }
+    return ESP_OK;
+}
+
+esp_err_t esp_ota_set_final_partition(esp_ota_handle_t handle, const esp_partition_t *final, bool finalize_with_copy)
+{
+    ota_ops_entry_t *it = get_ota_ops_entry(handle);
+    if (final == NULL) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    if (it == NULL) {
+        return ESP_ERR_NOT_FOUND;
+    }
+    if (it->wrote_size != 0) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    if (it->partition.staging != final) {
+        const esp_partition_t* final_partition = esp_partition_verify(final);
+        if (final_partition == NULL) {
+            return ESP_ERR_NOT_FOUND;
+        }
+        ESP_LOGI(TAG,"Staging partition - <%s>. Final partition - <%s>.", it->partition.staging->label, final_partition->label);
+        it->partition.final = final_partition;
+        it->partition.finalize_with_copy = finalize_with_copy;
+        if (final_partition->type == ESP_PARTITION_TYPE_BOOTLOADER) {
+            esp_image_bootloader_offset_set(it->partition.staging->address);
+        }
+        if (final_partition->type == ESP_PARTITION_TYPE_BOOTLOADER || final_partition->type == ESP_PARTITION_TYPE_PARTITION_TABLE) {
+            esp_flash_set_dangerous_write_protection(esp_flash_default_chip, false);
+        }
+    }
     return ESP_OK;
 }
 
@@ -192,23 +238,33 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void *data, size_t size)
         if (it->handle == handle) {
             if (it->need_erase) {
                 // must erase the partition before writing to it
-                uint32_t first_sector = it->wrote_size / it->part->erase_size; // first affected sector
-                uint32_t last_sector = (it->wrote_size + size - 1) / it->part->erase_size; // last affected sector
+                uint32_t first_sector = it->wrote_size / it->partition.staging->erase_size; // first affected sector
+                uint32_t last_sector = (it->wrote_size + size - 1) / it->partition.staging->erase_size; // last affected sector
 
                 ret = ESP_OK;
-                if ((it->wrote_size % it->part->erase_size) == 0) {
-                    ret = esp_partition_erase_range(it->part, it->wrote_size, ((last_sector - first_sector) + 1) * it->part->erase_size);
+                if ((it->wrote_size % it->partition.staging->erase_size) == 0) {
+                    ret = esp_partition_erase_range(it->partition.staging, it->wrote_size, ((last_sector - first_sector) + 1) * it->partition.staging->erase_size);
                 } else if (first_sector != last_sector) {
-                    ret = esp_partition_erase_range(it->part, (first_sector + 1) * it->part->erase_size, (last_sector - first_sector) * it->part->erase_size);
+                    ret = esp_partition_erase_range(it->partition.staging, (first_sector + 1) * it->partition.staging->erase_size, (last_sector - first_sector) * it->partition.staging->erase_size);
                 }
                 if (ret != ESP_OK) {
                     return ret;
                 }
             }
 
-            if (it->wrote_size == 0 && it->partial_bytes == 0 && size > 0 && data_bytes[0] != ESP_IMAGE_HEADER_MAGIC) {
-                ESP_LOGE(TAG, "OTA image has invalid magic byte (expected 0xE9, saw 0x%02x)", data_bytes[0]);
-                return ESP_ERR_OTA_VALIDATE_FAILED;
+            if (it->wrote_size == 0 && it->partial_bytes == 0 && size > 0) {
+                if (it->partition.final->type == ESP_PARTITION_TYPE_APP || it->partition.final->type == ESP_PARTITION_TYPE_BOOTLOADER) {
+                    if (data_bytes[0] != ESP_IMAGE_HEADER_MAGIC) {
+                        ESP_LOGE(TAG, "OTA image has invalid magic byte (expected 0xE9, saw 0x%02x)", data_bytes[0]);
+                        return ESP_ERR_OTA_VALIDATE_FAILED;
+                    }
+
+                } else if (it->partition.final->type == ESP_PARTITION_TYPE_PARTITION_TABLE) {
+                    if (*(uint16_t*)data_bytes != (uint16_t)ESP_PARTITION_MAGIC) {
+                        ESP_LOGE(TAG, "Partition table image has invalid magic word (expected 0x50AA, saw 0x%04x)", *(uint16_t*)data_bytes);
+                        return ESP_ERR_OTA_VALIDATE_FAILED;
+                    }
+                }
             }
 
             if (esp_flash_encryption_enabled()) {
@@ -224,7 +280,7 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void *data, size_t size)
                         return ESP_OK; /* nothing to write yet, just filling buffer */
                     }
                     /* write 16 byte to partition */
-                    ret = esp_partition_write(it->part, it->wrote_size, it->partial_data, 16);
+                    ret = esp_partition_write(it->partition.staging, it->wrote_size, it->partial_data, 16);
                     if (ret != ESP_OK) {
                         return ret;
                     }
@@ -243,7 +299,7 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void *data, size_t size)
                 }
             }
 
-            ret = esp_partition_write(it->part, it->wrote_size, data_bytes, size);
+            ret = esp_partition_write(it->partition.staging, it->wrote_size, data_bytes, size);
             if(ret == ESP_OK){
                 it->wrote_size += size;
             }
@@ -280,7 +336,7 @@ esp_err_t esp_ota_write_with_offset(esp_ota_handle_t handle, const void *data, s
                 ESP_LOGE(TAG, "Size should be 16byte aligned for flash encryption case");
                 return ESP_ERR_INVALID_ARG;
             }
-            ret = esp_partition_write(it->part, offset, data_bytes, size);
+            ret = esp_partition_write(it->partition.staging, offset, data_bytes, size);
             if (ret == ESP_OK) {
                 it->wrote_size += size;
             }
@@ -316,6 +372,34 @@ esp_err_t esp_ota_abort(esp_ota_handle_t handle)
     return ESP_OK;
 }
 
+static esp_err_t ota_verify_partition(ota_ops_entry_t *ota_ops)
+{
+    esp_err_t ret = ESP_OK;
+    if (ota_ops->partition.final->type == ESP_PARTITION_TYPE_APP || ota_ops->partition.final->type == ESP_PARTITION_TYPE_BOOTLOADER) {
+        esp_image_metadata_t data;
+        const esp_partition_pos_t part_pos = {
+            .offset = ota_ops->partition.staging->address,
+            .size = ota_ops->partition.staging->size,
+        };
+        if (esp_image_verify(ESP_IMAGE_VERIFY, &part_pos, &data) != ESP_OK) {
+            return ESP_ERR_OTA_VALIDATE_FAILED;
+        }
+    } else if (ota_ops->partition.final->type == ESP_PARTITION_TYPE_PARTITION_TABLE) {
+        const esp_partition_info_t *partition_table = NULL;
+        esp_partition_mmap_handle_t partition_table_map;
+        ret = esp_partition_mmap(ota_ops->partition.staging, 0, ESP_PARTITION_TABLE_MAX_LEN, ESP_PARTITION_MMAP_DATA, (const void**)&partition_table, &partition_table_map);
+        if (ret == ESP_OK) {
+            int num_partitions;
+            if (esp_partition_table_verify(partition_table, true, &num_partitions) != ESP_OK) {
+                esp_partition_munmap(partition_table_map);
+                return ESP_ERR_OTA_VALIDATE_FAILED;
+            }
+            esp_partition_munmap(partition_table_map);
+        }
+    }
+    return ret;
+}
+
 esp_err_t esp_ota_end(esp_ota_handle_t handle)
 {
     ota_ops_entry_t *it = get_ota_ops_entry(handle);
@@ -335,7 +419,7 @@ esp_err_t esp_ota_end(esp_ota_handle_t handle)
 
     if (it->partial_bytes > 0) {
         /* Write out last 16 bytes, if necessary */
-        ret = esp_partition_write(it->part, it->wrote_size, it->partial_data, 16);
+        ret = esp_partition_write(it->partition.staging, it->wrote_size, it->partial_data, 16);
         if (ret != ESP_OK) {
             ret = ESP_ERR_INVALID_STATE;
             goto cleanup;
@@ -344,18 +428,21 @@ esp_err_t esp_ota_end(esp_ota_handle_t handle)
         it->partial_bytes = 0;
     }
 
-    esp_image_metadata_t data;
-    const esp_partition_pos_t part_pos = {
-      .offset = it->part->address,
-      .size = it->part->size,
-    };
-
-    if (esp_image_verify(ESP_IMAGE_VERIFY, &part_pos, &data) != ESP_OK) {
-        ret = ESP_ERR_OTA_VALIDATE_FAILED;
-        goto cleanup;
+    ret = ota_verify_partition(it);
+    if (ret != ESP_OK) {
+        ESP_LOGE(TAG, "New image failed verification");
+    } else {
+        if (it->partition.finalize_with_copy) {
+            ESP_LOGI(TAG, "Copy from <%s> staging partition to <%s>...", it->partition.staging->label, it->partition.final->label);
+            ret = esp_partition_copy(it->partition.final, 0, it->partition.staging, 0, it->partition.final->size);
+        }
     }
 
  cleanup:
+    if (it->partition.final->type == ESP_PARTITION_TYPE_BOOTLOADER) {
+        // In esp_ota_begin, bootloader offset was updated, here we return it to default.
+        esp_image_bootloader_offset_set(ESP_PRIMARY_BOOTLOADER_OFFSET);
+    }
     LIST_REMOVE(it, entries);
     free(it);
     return ret;
diff --git a/components/app_update/include/esp_ota_ops.h b/components/app_update/include/esp_ota_ops.h
index ec2c633d536..0916f1f8966 100644
--- a/components/app_update/include/esp_ota_ops.h
+++ b/components/app_update/include/esp_ota_ops.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -82,7 +82,11 @@ int esp_ota_get_app_elf_sha256(char* dst, size_t size) __attribute__((deprecated
  * it will lead to the ESP_ERR_OTA_ROLLBACK_INVALID_STATE error. Confirm the running app before to run download a new app,
  * use esp_ota_mark_app_valid_cancel_rollback() function for it (this should be done as early as possible when you first download a new application).
  *
- * @param partition Pointer to info for partition which will receive the OTA update. Required.
+ * Note: Rollback is applicable only for app type partitions.
+ *
+ * @param partition  Pointer to info for partition which will receive the OTA update. Required.
+ *                   This is considered as the staging partition (where OTA is downloaded), be default this also considered as the final partition which supposed to be updated.
+ *                   The final partition can be overwritten using esp_ota_set_final_partition() after calling esp_ota_begin() to relocate contents to the final destination partition.
  * @param image_size Size of new OTA app image. Partition will be erased in order to receive this size of image. If 0 or OTA_SIZE_UNKNOWN, the entire partition is erased.
  * @param out_handle On success, returns a handle which should be used for subsequent esp_ota_write() and esp_ota_end() calls.
 
@@ -99,6 +103,31 @@ int esp_ota_get_app_elf_sha256(char* dst, size_t size) __attribute__((deprecated
  */
 esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp_ota_handle_t* out_handle);
 
+/**
+ * @brief Set the final destination partition for OTA update
+ *
+ * This function configures the specified final partition as the destination for the OTA update.
+ * It also allows setting a flag to indicate if the image should be copied from the staging
+ * partition to the final partition after the OTA update completes. Otherwise, copying will need
+ * to be handled by custom code using esp_partition_copy().
+ *
+ * @note This can be called after esp_ota_begin() and before the OTA update has started (before esp_ota_write()).
+ *
+ * @param handle OTA update handle obtained from esp_ota_begin().
+ * @param final Pointer to the final destination partition where the new image will be verified and potentially finalized.
+ *              This partition must not be NULL.
+ * @param finalize_with_copy Boolean flag indicating if the downloaded image should be copied
+ *                           from the staging partition to the final partition upon completion.
+ *                           Set to False if you intend to perform the final copy process manually later.
+ *
+ * @return
+ *      - ESP_OK: final destination partition set successfully.
+ *      - ESP_ERR_INVALID_STATE: Once the OTA update has started, changing the final destination partition is prohibited.
+ *      - ESP_ERR_INVALID_ARG: Invalid arguments were passed (e.g., final partition is NULL).
+ *      - ESP_ERR_NOT_FOUND: OTA handle not found or final partition verification failed.
+ */
+esp_err_t esp_ota_set_final_partition(esp_ota_handle_t handle, const esp_partition_t *final, bool finalize_with_copy);
+
 /**
  * @brief   Write OTA update data to partition
  *
@@ -113,9 +142,8 @@ esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp
  * @return
  *    - ESP_OK: Data was written to flash successfully, or size = 0
  *    - ESP_ERR_INVALID_ARG: handle is invalid.
- *    - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte.
+ *    - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid image magic byte.
  *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
- *    - ESP_ERR_OTA_SELECT_INFO_INVALID: OTA data partition has invalid contents
  *    - ESP_ERR_INVALID_SIZE: if write would go out of bounds of the partition
  *    - or one of error codes from lower-level flash driver.
  */
@@ -138,9 +166,7 @@ esp_err_t esp_ota_write(esp_ota_handle_t handle, const void* data, size_t size);
  * @return
  *    - ESP_OK: Data was written to flash successfully.
  *    - ESP_ERR_INVALID_ARG: handle is invalid.
- *    - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte.
  *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
- *    - ESP_ERR_OTA_SELECT_INFO_INVALID: OTA data partition has invalid contents
  */
 esp_err_t esp_ota_write_with_offset(esp_ota_handle_t handle, const void *data, size_t size, uint32_t offset);
 
@@ -150,6 +176,11 @@ esp_err_t esp_ota_write_with_offset(esp_ota_handle_t handle, const void *data, s
  * @param handle  Handle obtained from esp_ota_begin().
  *
  * @note After calling esp_ota_end(), the handle is no longer valid and any memory associated with it is freed (regardless of result).
+ * @note If either the final or staging partitions were for the bootloader, then at the end of this function,
+ *       the bootloader is reset to its default offset: esp_image_bootloader_offset_set(ESP_PRIMARY_BOOTLOADER_OFFSET)
+ *
+ * If the finalize_with_copy option is set, the staging partition will be copied to the final partition at the end of this function.
+ * Otherwise, copying will need to be handled by custom code using esp_partition_copy().
  *
  * @return
  *    - ESP_OK: Newly written OTA app image is valid.
@@ -258,7 +289,7 @@ esp_err_t esp_ota_get_partition_description(const esp_partition_t *partition, es
  * @brief Returns the description structure of the bootloader.
  *
  * @param[in] bootloader_partition Pointer to bootloader partition.
- *                                 If NULL, then the current bootloader is used (the default location).
+ *                                 If NULL, then the PRIMARY bootloader is used (the default location).
  *                                 offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH,
  *                                 size = CONFIG_PARTITION_TABLE_OFFSET - CONFIG_BOOTLOADER_OFFSET_IN_FLASH,
  * @param[out] desc     Structure of info about bootloader.
diff --git a/components/app_update/test_apps/test_app_update/main/test_ota_partitions.c b/components/app_update/test_apps/test_app_update/main/test_ota_partitions.c
new file mode 100644
index 00000000000..6a7fbf9252e
--- /dev/null
+++ b/components/app_update/test_apps/test_app_update/main/test_ota_partitions.c
@@ -0,0 +1,256 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_ota_ops.h"
+#include "esp_partition.h"
+#include "esp_flash_partitions.h"
+#include "esp_flash_internal.h"
+#include "spi_flash_mmap.h"
+#include "esp_image_format.h"
+#include "esp_system.h"
+#include "esp_log.h"
+#include "unity.h"
+#include "nvs_flash.h"
+#include "sdkconfig.h"
+
+static const char *TAG = "test";
+
+static uint8_t buffer[SPI_FLASH_SEC_SIZE];
+
+// Find the unused offset after the last partition, checking that it is of the required size
+static uint32_t find_unused_space(size_t required_size)
+{
+    esp_partition_iterator_t it = esp_partition_find(ESP_PARTITION_TYPE_ANY, ESP_PARTITION_SUBTYPE_ANY, NULL);
+    TEST_ASSERT_NOT_NULL(it);
+    const esp_partition_t* latest_partition = esp_partition_get(it);
+    for (; it != NULL; it = esp_partition_next(it)) {
+        const esp_partition_t *p = esp_partition_get(it);
+        if (p->address > latest_partition->address) {
+            latest_partition = p;
+        }
+    }
+    esp_partition_iterator_release(it);
+    TEST_ASSERT_NOT_NULL(latest_partition);
+
+#if CONFIG_IDF_TARGET_LINUX
+    uint32_t flash_chip_size;
+    esp_flash_get_size(NULL, &flash_chip_size);
+#else
+    uint32_t flash_chip_size = esp_flash_default_chip->size;
+#endif // CONFIG_IDF_TARGET_LINUX
+    uint32_t unused_offset = latest_partition->address + latest_partition->size;
+    TEST_ASSERT_GREATER_OR_EQUAL_UINT32(required_size, flash_chip_size - unused_offset);
+    return unused_offset;
+}
+
+static void check_after_reboot(void)
+{
+    ESP_LOGI(TAG, "App runs");
+}
+
+static void download_new_image_from_partition(esp_ota_handle_t update_handle, const esp_partition_t *copy_from_part)
+{
+    uint32_t offset = 0;
+    ESP_LOGI(TAG, "Downloading image...");
+    do {
+        TEST_ESP_OK(esp_partition_read(copy_from_part, offset, buffer, sizeof(buffer)));
+        TEST_ESP_OK(esp_ota_write(update_handle, buffer, sizeof(buffer)));
+        offset += sizeof(buffer);
+    } while (offset < copy_from_part->size);
+}
+
+static void start_bootloader_ota_update_via_ota_bootloader_part(void)
+{
+    const esp_partition_t *primary_bootloader;
+    TEST_ESP_OK(esp_partition_register_external(NULL, ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader));
+
+    const esp_partition_t *ota_bootloader;
+    const uint32_t ota_bootloader_offset = find_unused_space(ESP_BOOTLOADER_SIZE);
+    TEST_ESP_OK(esp_partition_register_external(NULL, ota_bootloader_offset, ESP_BOOTLOADER_SIZE, "OtaBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_OTA, &ota_bootloader));
+
+    esp_ota_handle_t update_handle;
+    TEST_ESP_OK(esp_ota_begin(ota_bootloader, OTA_WITH_SEQUENTIAL_WRITES, &update_handle));
+    TEST_ESP_OK(esp_ota_set_final_partition(update_handle, primary_bootloader, true));
+    download_new_image_from_partition(update_handle, primary_bootloader);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+
+    TEST_ESP_OK(esp_partition_deregister_external(primary_bootloader));
+    TEST_ESP_OK(esp_partition_deregister_external(ota_bootloader));
+    esp_restart();
+}
+
+TEST_CASE_MULTIPLE_STAGES("OTA update of bootloader via temp partition", "[bootloader_ota][reset=SW_CPU_RESET]", start_bootloader_ota_update_via_ota_bootloader_part, check_after_reboot);
+
+static void start_bootloader_ota_update_via_primary_bootloader_part(void)
+{
+    const esp_partition_t *primary_bootloader;
+    TEST_ESP_OK(esp_partition_register_external(NULL, ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader));
+
+    esp_ota_handle_t update_handle;
+    TEST_ESP_OK(esp_ota_begin(primary_bootloader, OTA_WITH_SEQUENTIAL_WRITES, &update_handle));
+    download_new_image_from_partition(update_handle, primary_bootloader);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+
+    TEST_ESP_OK(esp_partition_deregister_external(primary_bootloader));
+    esp_restart();
+}
+
+TEST_CASE_MULTIPLE_STAGES("OTA update of bootloader via primary partition", "[bootloader_ota][reset=SW_CPU_RESET]", start_bootloader_ota_update_via_primary_bootloader_part, check_after_reboot);
+
+static void start_partition_table_ota_update_via_ota_part_table(void)
+{
+    const esp_partition_t *primary_partition_table;
+    const esp_partition_t *ota_partition_table;
+    TEST_ESP_OK(esp_partition_register_external(NULL, ESP_PRIMARY_PARTITION_TABLE_OFFSET, ESP_PARTITION_TABLE_SIZE, "PrimaryPrtTable", ESP_PARTITION_TYPE_PARTITION_TABLE, ESP_PARTITION_SUBTYPE_PARTITION_TABLE_PRIMARY, &primary_partition_table));
+
+    uint32_t ota_partition_table_offset = find_unused_space(ESP_PARTITION_TABLE_SIZE);
+    TEST_ESP_OK(esp_partition_register_external(NULL, ota_partition_table_offset, ESP_PARTITION_TABLE_SIZE, "OtaPrtTable", ESP_PARTITION_TYPE_PARTITION_TABLE, ESP_PARTITION_SUBTYPE_PARTITION_TABLE_OTA, &ota_partition_table));
+
+    esp_ota_handle_t update_handle;
+    TEST_ESP_OK(esp_ota_begin(ota_partition_table, OTA_WITH_SEQUENTIAL_WRITES, &update_handle));
+    TEST_ESP_OK(esp_ota_set_final_partition(update_handle, primary_partition_table, true));
+    download_new_image_from_partition(update_handle, primary_partition_table);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+
+    TEST_ESP_OK(esp_partition_deregister_external(primary_partition_table));
+    TEST_ESP_OK(esp_partition_deregister_external(ota_partition_table));
+    esp_restart();
+}
+
+TEST_CASE_MULTIPLE_STAGES("OTA update of partition_table via temp partition", "[partition_table_ota][reset=SW_CPU_RESET]", start_partition_table_ota_update_via_ota_part_table, check_after_reboot);
+
+static void start_partition_table_ota_update_via_primary_part_table(void)
+{
+    const esp_partition_t *primary_partition_table;
+    TEST_ESP_OK(esp_partition_register_external(NULL, ESP_PRIMARY_PARTITION_TABLE_OFFSET, ESP_PARTITION_TABLE_SIZE, "PrimaryPrtTable", ESP_PARTITION_TYPE_PARTITION_TABLE, ESP_PARTITION_SUBTYPE_PARTITION_TABLE_PRIMARY, &primary_partition_table));
+
+    esp_ota_handle_t update_handle;
+    TEST_ESP_OK(esp_ota_begin(primary_partition_table, OTA_WITH_SEQUENTIAL_WRITES, &update_handle));
+    download_new_image_from_partition(update_handle, primary_partition_table);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+
+    TEST_ESP_OK(esp_partition_deregister_external(primary_partition_table));
+    esp_restart();
+}
+
+TEST_CASE_MULTIPLE_STAGES("OTA update of partition_table via primary partition", "[partition_table_ota][reset=SW_CPU_RESET]", start_partition_table_ota_update_via_primary_part_table, check_after_reboot);
+
+TEST_CASE("OTA update of NVS partition", "[nvs_ota]")
+{
+    // intilaize "nvs" partition and define a var (magic_value).
+    TEST_ESP_OK(nvs_flash_erase());
+    TEST_ESP_OK(nvs_flash_init());
+    nvs_handle_t my_handle;
+    TEST_ESP_OK(nvs_open("namespace", NVS_READWRITE, &my_handle));
+    uint32_t magic_value = 0x0729FEED;
+    TEST_ESP_OK(nvs_set_u32(my_handle, "magic_value", magic_value));
+    TEST_ESP_OK(nvs_commit(my_handle));
+    magic_value = 0;
+    TEST_ESP_OK(nvs_get_u32(my_handle, "magic_value", &magic_value));
+    TEST_ASSERT_EQUAL_HEX(0x0729FEED, magic_value);
+    nvs_close(my_handle);
+    TEST_ESP_OK(nvs_flash_deinit());
+
+    // register a new "nvs2" partition
+    const esp_partition_t *nvs_part = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS, "nvs");
+    const esp_partition_t *nvs2_part;
+    TEST_ESP_OK(esp_partition_register_external(NULL, find_unused_space(nvs_part->size), nvs_part->size, "nvs2", ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS, &nvs2_part));
+    ESP_LOGI(TAG, "Use %s partition (0x%08" PRIx32 ") to load a new image", nvs2_part->label, nvs2_part->address);
+    TEST_ESP_OK(nvs_flash_erase_partition("nvs2"));
+
+    // OTA update of the new "nvs2" partition, taking "nvs" partition as source.
+    esp_ota_handle_t update_handle;
+    TEST_ESP_OK(esp_ota_begin(nvs2_part, OTA_WITH_SEQUENTIAL_WRITES, &update_handle));
+    download_new_image_from_partition(update_handle, nvs_part);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+
+    // init "nvs2" partition and check if the magic_value == 0x0729FEED
+    TEST_ESP_OK(nvs_flash_init_partition("nvs2"));
+    nvs_handle_t my_handle2;
+    TEST_ESP_OK(nvs_open_from_partition("nvs2", "namespace", NVS_READWRITE, &my_handle2));
+    magic_value = 0;
+    TEST_ESP_OK(nvs_get_u32(my_handle2, "magic_value", &magic_value));
+    TEST_ASSERT_EQUAL_HEX(0x0729FEED, magic_value);
+    nvs_close(my_handle2);
+    TEST_ESP_OK(nvs_flash_deinit_partition("nvs2"));
+
+    // deregister "nvs2"
+    TEST_ESP_OK(esp_partition_deregister_external(nvs2_part));
+
+    TEST_ESP_OK(nvs_flash_erase());
+}
+
+static void start_bootloader_ota_update_via_app_part(void)
+{
+    const esp_partition_t *primary_bootloader;
+    TEST_ESP_OK(esp_partition_register_external(NULL, ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader));
+
+    const esp_partition_t *free_app_ota_partition = esp_ota_get_next_update_partition(NULL);
+    esp_ota_handle_t update_handle;
+    TEST_ESP_OK(esp_ota_begin(free_app_ota_partition, OTA_WITH_SEQUENTIAL_WRITES, &update_handle));
+    TEST_ESP_OK(esp_ota_set_final_partition(update_handle, primary_bootloader, true));
+    download_new_image_from_partition(update_handle, primary_bootloader);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+
+    TEST_ESP_OK(esp_partition_deregister_external(primary_bootloader));
+    esp_restart();
+}
+
+TEST_CASE_MULTIPLE_STAGES("OTA update of bootloader via a free ota partition", "[bootloader_ota][reset=SW_CPU_RESET]", start_bootloader_ota_update_via_app_part, check_after_reboot);
+
+static void start_partition_table_ota_update_via_app_part(void)
+{
+    const esp_partition_t *primary_partition_table;
+    TEST_ESP_OK(esp_partition_register_external(NULL, ESP_PRIMARY_PARTITION_TABLE_OFFSET, ESP_PARTITION_TABLE_SIZE, "PrimaryPrtTable", ESP_PARTITION_TYPE_PARTITION_TABLE, ESP_PARTITION_SUBTYPE_PARTITION_TABLE_PRIMARY, &primary_partition_table));
+
+    const esp_partition_t *free_app_ota_partition = esp_ota_get_next_update_partition(NULL);
+    esp_ota_handle_t update_handle;
+    TEST_ESP_OK(esp_ota_begin(free_app_ota_partition, OTA_WITH_SEQUENTIAL_WRITES, &update_handle));
+    TEST_ESP_OK(esp_ota_set_final_partition(update_handle, primary_partition_table, true));
+    download_new_image_from_partition(update_handle, primary_partition_table);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+
+    TEST_ESP_OK(esp_partition_deregister_external(primary_partition_table));
+    esp_restart();
+}
+
+TEST_CASE_MULTIPLE_STAGES("OTA update of partition_table via a free ota partition", "[partition_table_ota][reset=SW_CPU_RESET]", start_partition_table_ota_update_via_app_part, check_after_reboot);
+
+TEST_CASE("OTA update of NVS partition via a free ota partition", "[nvs_ota]")
+{
+    // intilaize "nvs" partition and define a var (magic_value).
+    const esp_partition_t *nvs_part = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NVS, "nvs");
+    TEST_ESP_OK(nvs_flash_erase());
+    TEST_ESP_OK(nvs_flash_init());
+    nvs_handle_t my_handle;
+    TEST_ESP_OK(nvs_open("namespace", NVS_READWRITE, &my_handle));
+    uint32_t magic_value = 0x0729FEED;
+    TEST_ESP_OK(nvs_set_u32(my_handle, "magic_value", magic_value));
+    TEST_ESP_OK(nvs_commit(my_handle));
+    magic_value = 0;
+    TEST_ESP_OK(nvs_get_u32(my_handle, "magic_value", &magic_value));
+    TEST_ASSERT_EQUAL_HEX(0x0729FEED, magic_value);
+    nvs_close(my_handle);
+    TEST_ESP_OK(nvs_flash_deinit());
+
+    // 1. OTA update nvs partition into free_app_ota_partition
+    // 2. copy free_app_ota_partition into the original nvs partition (which was erased before coping)
+    const esp_partition_t *free_app_ota_partition = esp_ota_get_next_update_partition(NULL);
+    esp_ota_handle_t update_handle;
+    TEST_ESP_OK(esp_ota_begin(free_app_ota_partition, OTA_WITH_SEQUENTIAL_WRITES, &update_handle));
+    TEST_ESP_OK(esp_ota_set_final_partition(update_handle, nvs_part, true));
+    download_new_image_from_partition(update_handle, nvs_part);
+    TEST_ESP_OK(esp_ota_end(update_handle));
+
+    // Check if the magic_value == 0x0729FEED
+    TEST_ESP_OK(nvs_flash_init());
+    TEST_ESP_OK(nvs_open("namespace", NVS_READONLY, &my_handle));
+    magic_value = 0;
+    TEST_ESP_OK(nvs_get_u32(my_handle, "magic_value", &magic_value));
+    TEST_ASSERT_EQUAL_HEX(0x0729FEED, magic_value);
+    nvs_close(my_handle);
+    TEST_ESP_OK(nvs_flash_deinit());
+    TEST_ESP_OK(nvs_flash_erase());
+}
diff --git a/components/app_update/test_apps/test_app_update/main/test_switch_ota.c b/components/app_update/test_apps/test_app_update/main/test_switch_ota.c
index f38802b7aee..01368553818 100644
--- a/components/app_update/test_apps/test_app_update/main/test_switch_ota.c
+++ b/components/app_update/test_apps/test_app_update/main/test_switch_ota.c
@@ -43,7 +43,12 @@ static const char *TAG = "ota_test";
 static void set_boot_count_in_nvs(uint8_t boot_count)
 {
     nvs_handle_t boot_count_handle;
-    TEST_ESP_OK(nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle));
+    esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle);
+    if (err != ESP_OK) {
+        TEST_ESP_OK(nvs_flash_erase());
+        TEST_ESP_OK(nvs_flash_init());
+        TEST_ESP_OK(nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle));
+    }
     TEST_ESP_OK(nvs_set_u8(boot_count_handle, "boot_count", boot_count));
     TEST_ESP_OK(nvs_commit(boot_count_handle));
     nvs_close(boot_count_handle);
diff --git a/components/bootloader/Kconfig.app_rollback b/components/bootloader/Kconfig.app_rollback
new file mode 100644
index 00000000000..cfe0c279e63
--- /dev/null
+++ b/components/bootloader/Kconfig.app_rollback
@@ -0,0 +1,68 @@
+menu "Application Rollback"
+
+    config BOOTLOADER_APP_ROLLBACK_ENABLE
+        bool "Enable app rollback support"
+        default n
+        help
+            After updating the app, the bootloader runs a new app with the "ESP_OTA_IMG_PENDING_VERIFY" state set.
+            This state prevents the re-run of this app. After the first boot of the new app in the user code, the
+            function should be called to confirm the operability of the app or vice versa about its non-operability.
+            If the app is working, then it is marked as valid. Otherwise, it is marked as not valid and rolls back to
+            the previous working app. A reboot is performed, and the app is booted before the software update.
+            Note: If during the first boot a new app the power goes out or the WDT works, then roll back will happen.
+            Rollback is possible only between the apps with the same security versions.
+
+    config BOOTLOADER_APP_ANTI_ROLLBACK
+        bool "Enable app anti-rollback support"
+        depends on BOOTLOADER_APP_ROLLBACK_ENABLE
+        default n
+        help
+            This option prevents rollback to previous firmware/application image with lower security version.
+
+    config BOOTLOADER_APP_SECURE_VERSION
+        int "eFuse secure version of app"
+        depends on BOOTLOADER_APP_ANTI_ROLLBACK
+        default 0
+        help
+            The secure version is the sequence number stored in the header of each firmware.
+            The security version is set in the bootloader, version is recorded in the eFuse field
+            as the number of set ones. The allocated number of bits in the efuse field
+            for storing the security version is limited (see BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD option).
+
+            Bootloader: When bootloader selects an app to boot, an app is selected that has
+            a security version greater or equal that recorded in eFuse field.
+            The app is booted with a higher (or equal) secure version.
+
+            The security version is worth increasing if in previous versions there is
+            a significant vulnerability and their use is not acceptable.
+
+            Your partition table should has a scheme with ota_0 + ota_1 (without factory).
+
+    config BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD
+        int "Size of the efuse secure version field"
+        depends on BOOTLOADER_APP_ANTI_ROLLBACK
+        range 1 32 if IDF_TARGET_ESP32
+        default 32 if IDF_TARGET_ESP32
+        range 1 4 if IDF_TARGET_ESP32C2
+        default 4 if IDF_TARGET_ESP32C2
+        range 1 16
+        default 16
+        help
+            The size of the efuse secure version field.
+            Its length is limited to 32 bits for ESP32 and 16 bits for ESP32-S2.
+            This determines how many times the security version can be increased.
+
+    config BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
+        bool "Emulate operations with efuse secure version(only test)"
+        default n
+        depends on BOOTLOADER_APP_ANTI_ROLLBACK
+        select EFUSE_VIRTUAL
+        select EFUSE_VIRTUAL_KEEP_IN_FLASH
+        help
+            This option allows to emulate read/write operations with all eFuses and efuse secure version.
+            It allows to test anti-rollback implementation without permanent write eFuse bits.
+            There should be an entry in partition table with following details: `emul_efuse, data, efuse, , 0x2000`.
+
+            This option enables: EFUSE_VIRTUAL and EFUSE_VIRTUAL_KEEP_IN_FLASH.
+
+endmenu
diff --git a/components/bootloader/Kconfig.bootloader_rollback b/components/bootloader/Kconfig.bootloader_rollback
new file mode 100644
index 00000000000..f8c74dae15c
--- /dev/null
+++ b/components/bootloader/Kconfig.bootloader_rollback
@@ -0,0 +1,25 @@
+menu "Bootloader Rollback"
+
+    config BOOTLOADER_ANTI_ROLLBACK_ENABLE
+        bool "Enable bootloader rollback support"
+        depends on SOC_RECOVERY_BOOTLOADER_SUPPORTED
+        default n
+        help
+            This option prevents rollback to previous bootloader image with lower security version.
+
+    config BOOTLOADER_SECURE_VERSION
+        int "Secure version of bootloader"
+        depends on BOOTLOADER_ANTI_ROLLBACK_ENABLE
+        default 0
+        range 0 4
+        help
+            The secure version is the sequence number stored in the header of each bootloader.
+
+            The ROM Bootloader which runs the 2nd stage bootloader (PRIMARY or RECOVERY) checks that
+            the security version is greater or equal that recorded in the eFuse field.
+            Bootloaders that have a secure version in the image < secure version in efuse will not boot.
+
+            The security version is worth increasing if in previous versions there is
+            a significant vulnerability and their use is not acceptable.
+
+endmenu
diff --git a/components/bootloader/Kconfig.log.format b/components/bootloader/Kconfig.log.format
index b1b877b0a99..6d87bc56012 100644
--- a/components/bootloader/Kconfig.log.format
+++ b/components/bootloader/Kconfig.log.format
@@ -2,7 +2,7 @@ menu "Format"
 
     config BOOTLOADER_LOG_COLORS
         bool "Color"
-        default y
+        default n
         help
             Use ANSI terminal colors in log output
             Enable ANSI terminal color codes.
diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild
index b5dca09a205..c11c7b95a46 100644
--- a/components/bootloader/Kconfig.projbuild
+++ b/components/bootloader/Kconfig.projbuild
@@ -1,6 +1,8 @@
 menu "Bootloader config"
 
     orsource "../esp_bootloader_format/Kconfig.bootloader"
+    orsource "Kconfig.app_rollback"
+    orsource "Kconfig.bootloader_rollback"
 
     config BOOTLOADER_OFFSET_IN_FLASH
         hex
@@ -312,71 +314,6 @@ menu "Bootloader config"
             - these options can increase the execution time.
             Note: RTC_WDT will reset while encryption operations will be performed.
 
-    config BOOTLOADER_APP_ROLLBACK_ENABLE
-        bool "Enable app rollback support"
-        default n
-        help
-            After updating the app, the bootloader runs a new app with the "ESP_OTA_IMG_PENDING_VERIFY" state set.
-            This state prevents the re-run of this app. After the first boot of the new app in the user code, the
-            function should be called to confirm the operability of the app or vice versa about its non-operability.
-            If the app is working, then it is marked as valid. Otherwise, it is marked as not valid and rolls back to
-            the previous working app. A reboot is performed, and the app is booted before the software update.
-            Note: If during the first boot a new app the power goes out or the WDT works, then roll back will happen.
-            Rollback is possible only between the apps with the same security versions.
-
-    config BOOTLOADER_APP_ANTI_ROLLBACK
-        bool "Enable app anti-rollback support"
-        depends on BOOTLOADER_APP_ROLLBACK_ENABLE
-        default n
-        help
-            This option prevents rollback to previous firmware/application image with lower security version.
-
-    config BOOTLOADER_APP_SECURE_VERSION
-        int "eFuse secure version of app"
-        depends on BOOTLOADER_APP_ANTI_ROLLBACK
-        default 0
-        help
-            The secure version is the sequence number stored in the header of each firmware.
-            The security version is set in the bootloader, version is recorded in the eFuse field
-            as the number of set ones. The allocated number of bits in the efuse field
-            for storing the security version is limited (see BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD option).
-
-            Bootloader: When bootloader selects an app to boot, an app is selected that has
-            a security version greater or equal that recorded in eFuse field.
-            The app is booted with a higher (or equal) secure version.
-
-            The security version is worth increasing if in previous versions there is
-            a significant vulnerability and their use is not acceptable.
-
-            Your partition table should has a scheme with ota_0 + ota_1 (without factory).
-
-    config BOOTLOADER_APP_SEC_VER_SIZE_EFUSE_FIELD
-        int "Size of the efuse secure version field"
-        depends on BOOTLOADER_APP_ANTI_ROLLBACK
-        range 1 32 if IDF_TARGET_ESP32
-        default 32 if IDF_TARGET_ESP32
-        range 1 4 if IDF_TARGET_ESP32C2
-        default 4 if IDF_TARGET_ESP32C2
-        range 1 16
-        default 16
-        help
-            The size of the efuse secure version field.
-            Its length is limited to 32 bits for ESP32 and 16 bits for ESP32-S2.
-            This determines how many times the security version can be increased.
-
-    config BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE
-        bool "Emulate operations with efuse secure version(only test)"
-        default n
-        depends on BOOTLOADER_APP_ANTI_ROLLBACK
-        select EFUSE_VIRTUAL
-        select EFUSE_VIRTUAL_KEEP_IN_FLASH
-        help
-            This option allows to emulate read/write operations with all eFuses and efuse secure version.
-            It allows to test anti-rollback implementation without permanent write eFuse bits.
-            There should be an entry in partition table with following details: `emul_efuse, data, efuse, , 0x2000`.
-
-            This option enables: EFUSE_VIRTUAL and EFUSE_VIRTUAL_KEEP_IN_FLASH.
-
     config BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP
         bool "Skip image validation when exiting deep sleep"
         # note: dependencies for this config item are different to other "skip image validation"
diff --git a/components/bootloader/project_include.cmake b/components/bootloader/project_include.cmake
index 2afe2116d3b..12cf17dc70a 100644
--- a/components/bootloader/project_include.cmake
+++ b/components/bootloader/project_include.cmake
@@ -116,8 +116,13 @@ idf_build_get_property(sdkconfig SDKCONFIG)
 idf_build_get_property(python PYTHON)
 idf_build_get_property(extra_cmake_args EXTRA_CMAKE_ARGS)
 
-# We cannot pass lists are a parameter to the external project without modifying the ';' separator
+# BOOTLOADER_EXTRA_COMPONENT_DIRS may have been set by the `main` component, do not overwrite it
+idf_build_get_property(bootloader_extra_component_dirs BOOTLOADER_EXTRA_COMPONENT_DIRS)
+list(APPEND bootloader_extra_component_dirs "${CMAKE_CURRENT_LIST_DIR}")
+
+# We cannot pass lists as a parameter to the external project without modifying the ';' separator
 string(REPLACE ";" "|" BOOTLOADER_IGNORE_EXTRA_COMPONENT "${BOOTLOADER_IGNORE_EXTRA_COMPONENT}")
+string(REPLACE ";" "|" bootloader_extra_component_dirs "${bootloader_extra_component_dirs}")
 
 externalproject_add(bootloader
     SOURCE_DIR "${CMAKE_CURRENT_LIST_DIR}/subproject"
@@ -127,7 +132,7 @@ externalproject_add(bootloader
     LIST_SEPARATOR |
     CMAKE_ARGS  -DSDKCONFIG=${sdkconfig} -DIDF_PATH=${idf_path} -DIDF_TARGET=${idf_target}
                 -DPYTHON_DEPS_CHECKED=1 -DPYTHON=${python}
-                -DEXTRA_COMPONENT_DIRS=${CMAKE_CURRENT_LIST_DIR}
+                -DEXTRA_COMPONENT_DIRS=${bootloader_extra_component_dirs}
                 -DPROJECT_SOURCE_DIR=${PROJECT_SOURCE_DIR}
                 -DIGNORE_EXTRA_COMPONENT=${BOOTLOADER_IGNORE_EXTRA_COMPONENT}
                 ${sign_key_arg} ${ver_key_arg}
diff --git a/components/bootloader/subproject/CMakeLists.txt b/components/bootloader/subproject/CMakeLists.txt
index e4881b4bc55..34c7cded18a 100644
--- a/components/bootloader/subproject/CMakeLists.txt
+++ b/components/bootloader/subproject/CMakeLists.txt
@@ -34,8 +34,8 @@ set(COMPONENTS
     esp_system
     newlib)
 
-# Make EXTRA_COMPONENT_DIRS variable to point to the bootloader_components directory
-# of the project being compiled
+# EXTRA_COMPONENT_DIRS can be populated with directories containing one or several components.
+# Make sure this variable contains `bootloader_components` directory of the project being compiled.
 set(PROJECT_EXTRA_COMPONENTS "${PROJECT_SOURCE_DIR}/bootloader_components")
 if(EXISTS ${PROJECT_EXTRA_COMPONENTS})
     list(APPEND EXTRA_COMPONENT_DIRS "${PROJECT_EXTRA_COMPONENTS}")
@@ -58,6 +58,7 @@ foreach(component ${proj_components})
 endforeach()
 
 set(BOOTLOADER_BUILD 1)
+set(NON_OS_BUILD 1)
 include("${IDF_PATH}/tools/cmake/project.cmake")
 set(common_req log esp_rom esp_common esp_hw_support newlib)
 idf_build_set_property(EXTRA_COMPONENT_EXCLUDE_DIRS "${EXTRA_COMPONENT_EXCLUDE_DIRS}")
@@ -66,6 +67,7 @@ idf_build_set_property(__OUTPUT_SDKCONFIG 0)
 project(bootloader)
 
 idf_build_set_property(COMPILE_DEFINITIONS "BOOTLOADER_BUILD=1" APPEND)
+idf_build_set_property(COMPILE_DEFINITIONS "NON_OS_BUILD=1" APPEND)
 idf_build_set_property(COMPILE_OPTIONS "-fno-stack-protector" APPEND)
 
 idf_component_get_property(main_args esptool_py FLASH_ARGS)
@@ -207,7 +209,7 @@ elseif(CONFIG_SECURE_BOOTLOADER_REFLASHABLE)
         COMMAND ${CMAKE_COMMAND} -E echo
             "* After first boot, only re-flashes of this kind (with same key) will be accepted."
         COMMAND ${CMAKE_COMMAND} -E echo
-            "* Not recommended to re-use the same secure boot keyfile on multiple production devices."
+            "* Not recommended to reuse the same secure boot keyfile on multiple production devices."
         DEPENDS gen_secure_bootloader_key gen_bootloader_digest_bin
         VERBATIM)
 elseif(
diff --git a/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h b/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
index d8060476ae3..50f31caf2d4 100644
--- a/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
+++ b/components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +13,7 @@
 #include <spi_flash_mmap.h> /* including in bootloader for error values */
 #include "sdkconfig.h"
 #include "bootloader_flash.h"
+#include "soc/ext_mem_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -20,8 +21,11 @@ extern "C" {
 
 #define FLASH_SECTOR_SIZE 0x1000
 #define FLASH_BLOCK_SIZE 	0x10000
+
 #define MMAP_ALIGNED_MASK 	(SPI_FLASH_MMU_PAGE_SIZE - 1)
 #define MMU_FLASH_MASK    (~(SPI_FLASH_MMU_PAGE_SIZE - 1))
+#define MMU_FLASH_MASK_FROM_VAL(PAGE_SZ) (~((PAGE_SZ) - 1))
+#define MMU_DROM_END_ENTRY_VADDR_FROM_VAL(PAGE_SZ) (SOC_DRAM_FLASH_ADDRESS_HIGH - (PAGE_SZ))
 
 /**
  * MMU mapping must always be in the unit of a SPI_FLASH_MMU_PAGE_SIZE
@@ -89,7 +93,7 @@ uint32_t bootloader_mmap_get_free_pages(void);
  * @param length - Length of data to map.
  *
  * @return Pointer to mapped data memory (at src_addr), or NULL
- * if an allocation error occured.
+ * if an allocation error occurred.
  */
 const void *bootloader_mmap(uint32_t src_addr, uint32_t size);
 
diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
index ea105792215..adff675c260 100644
--- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c
@@ -670,7 +670,6 @@ void bootloader_spi_flash_reset(void)
 
 #define XMC_SUPPORT CONFIG_BOOTLOADER_FLASH_XMC_SUPPORT
 #define XMC_VENDOR_ID_1 0x20
-#define XMC_VENDOR_ID_2 0x46
 
 #if BOOTLOADER_BUILD
 #define BOOTLOADER_FLASH_LOG(level, ...)    ESP_EARLY_LOG##level(TAG, ##__VA_ARGS__)
@@ -687,7 +686,7 @@ static IRAM_ATTR bool is_xmc_chip_strict(uint32_t rdid)
     uint32_t mfid = BYTESHIFT(rdid, 1);
     uint32_t cpid = BYTESHIFT(rdid, 0);
 
-    if (vendor_id != XMC_VENDOR_ID_1 && vendor_id != XMC_VENDOR_ID_2) {
+    if (vendor_id != XMC_VENDOR_ID_1) {
         return false;
     }
 
@@ -720,7 +719,7 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
     // Check the Manufacturer ID in SFDP registers (JEDEC standard). If not XMC chip, no need to run the flow
     const int sfdp_mfid_addr = 0x10;
     uint8_t mf_id = (bootloader_flash_read_sfdp(sfdp_mfid_addr, 1) & 0xff);
-    if ((mf_id != XMC_VENDOR_ID_1) && (mf_id != XMC_VENDOR_ID_2)) {
+    if (mf_id != XMC_VENDOR_ID_1) {
         BOOTLOADER_FLASH_LOG(D, "non-XMC chip detected by SFDP Read (%02X), skip.", mf_id);
         return ESP_OK;
     }
@@ -752,7 +751,7 @@ esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
 static IRAM_ATTR bool is_xmc_chip(uint32_t rdid)
 {
     uint32_t vendor_id = (rdid >> 16) & 0xFF;
-    return ((vendor_id == XMC_VENDOR_ID_1) || (vendor_id == XMC_VENDOR_ID_2));
+    return (vendor_id == XMC_VENDOR_ID_1);
 }
 
 esp_err_t IRAM_ATTR bootloader_flash_xmc_startup(void)
diff --git a/components/bootloader_support/include/esp_flash_encrypt.h b/components/bootloader_support/include/esp_flash_encrypt.h
index e942d7f54d7..efc061edf50 100644
--- a/components/bootloader_support/include/esp_flash_encrypt.h
+++ b/components/bootloader_support/include/esp_flash_encrypt.h
@@ -184,12 +184,14 @@ void esp_flash_encryption_init_checks(void);
  */
 esp_err_t esp_flash_encryption_enable_secure_features(void);
 
+#if CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY
 /** @brief Enable the key manager for flash encryption
  *
  * @return
  *  - ESP_OK - On success
  */
 esp_err_t esp_flash_encryption_enable_key_mgr(void);
+#endif // CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY
 
 #endif /* BOOTLOADER_BUILD && CONFIG_SECURE_FLASH_ENC_ENABLED */
 
diff --git a/components/bootloader_support/include/esp_flash_partitions.h b/components/bootloader_support/include/esp_flash_partitions.h
index 47fe9759610..5a6da221b00 100644
--- a/components/bootloader_support/include/esp_flash_partitions.h
+++ b/components/bootloader_support/include/esp_flash_partitions.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +29,15 @@ extern "C" {
 #define PART_SUBTYPE_DATA_NVS_KEYS 0x04
 #define PART_SUBTYPE_DATA_EFUSE_EM 0x05
 
+#define PART_TYPE_BOOTLOADER 0x02
+#define PART_SUBTYPE_BOOTLOADER_PRIMARY 0x00
+#define PART_SUBTYPE_BOOTLOADER_OTA 0x01
+#define PART_SUBTYPE_BOOTLOADER_RECOVERY 0x02
+
+#define PART_TYPE_PARTITION_TABLE 0x03
+#define PART_SUBTYPE_PARTITION_TABLE_PRIMARY 0x00
+#define PART_SUBTYPE_PARTITION_TABLE_OTA 0x01
+
 #define PART_TYPE_END 0xff
 #define PART_SUBTYPE_END 0xff
 
@@ -41,7 +50,11 @@ extern "C" {
 /* Pre-partition table fixed flash offsets */
 #define ESP_BOOTLOADER_DIGEST_OFFSET 0x0
 #define ESP_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH  /* Offset of bootloader image. Has matching value in bootloader KConfig.projbuild file. */
+#define ESP_PRIMARY_BOOTLOADER_OFFSET CONFIG_BOOTLOADER_OFFSET_IN_FLASH  /* Offset of Primary bootloader image. */
 #define ESP_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. Backwards-compatible name.*/
+#define ESP_PRIMARY_PARTITION_TABLE_OFFSET CONFIG_PARTITION_TABLE_OFFSET /* Offset of partition table. */
+#define ESP_PARTITION_TABLE_SIZE (0x1000) /* The partition table occupies 1 sector of flash (SPI_FLASH_SEC_SIZE) */
+#define ESP_BOOTLOADER_SIZE (ESP_PARTITION_TABLE_OFFSET - ESP_BOOTLOADER_OFFSET)
 
 #define ESP_PARTITION_TABLE_MAX_LEN 0xC00 /* Maximum length of partition table data */
 #define ESP_PARTITION_TABLE_MAX_ENTRIES (ESP_PARTITION_TABLE_MAX_LEN / sizeof(esp_partition_info_t)) /* Maximum length of partition table data, including terminating entry */
diff --git a/components/bootloader_support/include/esp_image_format.h b/components/bootloader_support/include/esp_image_format.h
index f677b08fe50..77f0f231dd9 100644
--- a/components/bootloader_support/include/esp_image_format.h
+++ b/components/bootloader_support/include/esp_image_format.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,7 @@ typedef struct {
   uint32_t image_len; /* Length of image on flash, in bytes */
   uint8_t image_digest[32]; /* appended SHA-256 digest */
   uint32_t secure_version; /* secure version for anti-rollback, it is covered by sha256 (set if CONFIG_BOOTLOADER_APP_ANTI_ROLLBACK=y) */
+  uint32_t mmu_page_size; /* Flash MMU page size per binary header */
 } esp_image_metadata_t;
 
 typedef enum {
@@ -86,12 +87,12 @@ ESP_STATIC_ASSERT(sizeof(rtc_retain_mem_t) <= ESP_BOOTLOADER_RESERVE_RTC, "Reser
 #endif // CONFIG_BOOTLOADER_RESERVE_RTC_MEM
 
 /**
- * @brief Verify an app image.
+ * @brief Verify an app/bootloader image.
  *
  * If encryption is enabled, data will be transparently decrypted.
  *
  * @param mode Mode of operation (verify, silent verify, or load).
- * @param part Partition to load the app from.
+ * @param part Partition to load the app/bootloader from.
  * @param[inout] data Pointer to the image metadata structure which is be filled in by this function.
  *                    'start_addr' member should be set (to the start address of the image.)
  *                    Other fields will all be initialised by this function.
@@ -113,11 +114,11 @@ ESP_STATIC_ASSERT(sizeof(rtc_retain_mem_t) <= ESP_BOOTLOADER_RESERVE_RTC, "Reser
 esp_err_t esp_image_verify(esp_image_load_mode_t mode, const esp_partition_pos_t *part, esp_image_metadata_t *data);
 
 /**
- * @brief Get metadata of app
+ * @brief Get metadata of app/bootloader
  *
  * If encryption is enabled, data will be transparently decrypted.
  *
- * @param part Partition to load the app from.
+ * @param part Partition to load the app/bootloader from.
  * @param[out] metadata Pointer to the image metadata structure which is be filled in by this function.
  *                      Fields will all be initialised by this function.
  *
@@ -171,7 +172,7 @@ esp_err_t bootloader_load_image(const esp_partition_pos_t *part, esp_image_metad
 esp_err_t bootloader_load_image_no_verify(const esp_partition_pos_t *part, esp_image_metadata_t *data);
 
 /**
- * @brief Verify the bootloader image.
+ * @brief Verify the PRIMARY bootloader image.
  *
  * @param[out] If result is ESP_OK and this pointer is non-NULL, it
  * will be set to the length of the bootloader image.
@@ -181,7 +182,7 @@ esp_err_t bootloader_load_image_no_verify(const esp_partition_pos_t *part, esp_i
 esp_err_t esp_image_verify_bootloader(uint32_t *length);
 
 /**
- * @brief Verify the bootloader image.
+ * @brief Verify the PRIMARY bootloader image.
  *
  * @param[out] Metadata for the image. Only valid if result is ESP_OK.
  *
@@ -197,6 +198,25 @@ esp_err_t esp_image_verify_bootloader_data(esp_image_metadata_t *data);
  */
 int esp_image_get_flash_size(esp_image_flash_size_t app_flash_size);
 
+/**
+ * @brief Get the ota bootloader offset
+ *
+ * The esp_image_verify functions use the offset to distinguish between application and bootloader verifications.
+ * The application must set the OTA bootloader offset before running any verification functions for the OTA bootloader partition.
+ *
+ * @return ota Bootloader offset. UINT32_MAX - not set.
+ */
+uint32_t esp_image_bootloader_offset_get(void);
+
+/**
+ * @brief Set the ota bootloader offset
+ *
+ * The esp_image_verify functions use the offset to distinguish between application and bootloader verifications.
+ * The application must set the OTA bootloader offset before running any verification functions for the OTA bootloader partition.
+ *
+ * @param offset ota Bootloader offset
+ */
+void esp_image_bootloader_offset_set(const uint32_t offset);
 
 typedef struct {
     uint32_t drom_addr;
diff --git a/components/bootloader_support/private_include/bootloader_soc.h b/components/bootloader_support/private_include/bootloader_soc.h
index d854112f638..acce77cfb6c 100644
--- a/components/bootloader_support/private_include/bootloader_soc.h
+++ b/components/bootloader_support/private_include/bootloader_soc.h
@@ -24,6 +24,14 @@ void bootloader_ana_super_wdt_reset_config(bool enable);
  */
 void bootloader_ana_clock_glitch_reset_config(bool enable);
 
+/**
+ * @brief Configure analog power glitch reset & glitch reset dref
+ *
+ * @param enable Boolean to enable or disable power glitch reset
+ * @param dref voltage threshold
+ */
+void bootloader_power_glitch_reset_config(bool enable, uint8_t dref);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c
index 8099aa49553..e5e258a44e0 100644
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@@ -64,7 +64,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
         // RTC_FAST clock source will be switched to RC_FAST at application startup
         clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
         if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
-            clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV;
+            clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_DEFAULT;
         }
 
 #if CONFIG_IDF_TARGET_ESP32C6
diff --git a/components/bootloader_support/src/bootloader_common.c b/components/bootloader_support/src/bootloader_common.c
index e37a5b41c38..759263e1222 100644
--- a/components/bootloader_support/src/bootloader_common.c
+++ b/components/bootloader_support/src/bootloader_common.c
@@ -140,13 +140,13 @@ bool bootloader_common_erase_part_type_data(const char *list_erase, bool ota_dat
     return ret;
 }
 
-esp_err_t bootloader_common_get_sha256_of_partition (uint32_t address, uint32_t size, int type, uint8_t *out_sha_256)
+esp_err_t bootloader_common_get_sha256_of_partition(uint32_t address, uint32_t size, int type, uint8_t *out_sha_256)
 {
     if (out_sha_256 == NULL || size == 0) {
         return ESP_ERR_INVALID_ARG;
     }
 
-    if (type == PART_TYPE_APP) {
+    if (type == PART_TYPE_APP || type == PART_TYPE_BOOTLOADER) {
         const esp_partition_pos_t partition_pos = {
             .offset = address,
             .size = size,
diff --git a/components/bootloader_support/src/bootloader_random_esp32c5.c b/components/bootloader_support/src/bootloader_random_esp32c5.c
index 6541b8deb01..0aabb1d4a81 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c5.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c5.c
@@ -46,6 +46,9 @@ void bootloader_random_enable(void)
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     // Config ADC circuit (Analog part) with I2C (HOST ID 0X69) and choose internal voltage as sampling source
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 1);
@@ -94,6 +97,9 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0);
 
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 
diff --git a/components/bootloader_support/src/bootloader_random_esp32c6.c b/components/bootloader_support/src/bootloader_random_esp32c6.c
index fec85a6a404..41322592f25 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c6.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c6.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -40,6 +40,9 @@ void bootloader_random_enable(void)
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     // Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 2);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR   , 1);
@@ -88,6 +91,9 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
 
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 
diff --git a/components/bootloader_support/src/bootloader_random_esp32c61.c b/components/bootloader_support/src/bootloader_random_esp32c61.c
index bcc7d57f16c..a4b1da50700 100644
--- a/components/bootloader_support/src/bootloader_random_esp32c61.c
+++ b/components/bootloader_support/src/bootloader_random_esp32c61.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -45,6 +45,9 @@ void bootloader_random_enable(void)
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     // Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR   , 1);
@@ -93,6 +96,9 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
 
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 
diff --git a/components/bootloader_support/src/bootloader_random_esp32h2.c b/components/bootloader_support/src/bootloader_random_esp32h2.c
index 0b4e382025a..fc5036c8cc5 100644
--- a/components/bootloader_support/src/bootloader_random_esp32h2.c
+++ b/components/bootloader_support/src/bootloader_random_esp32h2.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,6 +35,9 @@ void bootloader_random_enable(void)
     // some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1);
@@ -80,6 +83,9 @@ void bootloader_random_disable(void)
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 0);
     REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 0);
 
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // disable ADC_CTRL_CLK (SAR ADC function clock)
     REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
 
diff --git a/components/bootloader_support/src/bootloader_random_esp32p4.c b/components/bootloader_support/src/bootloader_random_esp32p4.c
index df88e8d7b22..7cdc770a44a 100644
--- a/components/bootloader_support/src/bootloader_random_esp32p4.c
+++ b/components/bootloader_support/src/bootloader_random_esp32p4.c
@@ -62,6 +62,9 @@ void bootloader_random_enable(void)
 
     SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
 
+    // enable analog i2c master clock for RNG runtime
+    ANALOG_CLOCK_ENABLE();
+
     adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
 
     //  cfg pattern table
@@ -94,6 +97,9 @@ void bootloader_random_enable(void)
 
 void bootloader_random_disable(void)
 {
+    // disable analog i2c master clock
+    ANALOG_CLOCK_DISABLE();
+
     // No-op for now TODO IDF-6497
     // ADC should be set to defaults here, once ADC API is implemented
     // OR just keep this empty and let application continue to use RNG initialized by the bootloader
diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
index 30dd5049fc3..2d62c0b92c3 100644
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -20,6 +20,7 @@
 #include "esp_rom_spiflash.h"
 
 #include "soc/soc.h"
+#include "soc/soc_caps.h"
 #include "soc/rtc.h"
 #include "soc/efuse_periph.h"
 #include "soc/rtc_periph.h"
@@ -66,7 +67,7 @@ static void set_cache_and_start_app(uint32_t drom_addr,
                                     uint32_t irom_addr,
                                     uint32_t irom_load_addr,
                                     uint32_t irom_size,
-                                    uint32_t entry_addr);
+                                    const esp_image_metadata_t *data);
 
 esp_err_t bootloader_common_read_otadata(const esp_partition_pos_t *ota_info, esp_ota_select_entry_t *two_otadata)
 {
@@ -199,6 +200,29 @@ bool bootloader_utility_load_partition_table(bootloader_state_t *bs)
                 break;
             }
             break; /* PARTITION_USAGE_DATA */
+        case PART_TYPE_BOOTLOADER: /* Bootloader partition */
+            switch (partition->subtype) {
+            case PART_SUBTYPE_BOOTLOADER_PRIMARY:
+                partition_usage = "primary bootloader";
+                break;
+            case PART_SUBTYPE_BOOTLOADER_OTA:
+                partition_usage = "ota bootloader";
+                break;
+            case PART_SUBTYPE_BOOTLOADER_RECOVERY:
+                partition_usage = "recovery bootloader";
+                break;
+            }
+            break; /* PART_TYPE_BOOTLOADER */
+        case PART_TYPE_PARTITION_TABLE: /* Partition table partition */
+            switch (partition->subtype) {
+            case PART_SUBTYPE_PARTITION_TABLE_PRIMARY:
+                partition_usage = "primary partition_table";
+                break;
+            case PART_SUBTYPE_PARTITION_TABLE_OTA:
+                partition_usage = "ota partition_table";
+                break;
+            }
+            break; /* PART_TYPE_PARTITION_TABLE */
         default: /* other partition type */
             break;
         }
@@ -769,7 +793,7 @@ static void unpack_load_app(const esp_image_metadata_t *data)
                             rom_addr[1],
                             rom_load_addr[1],
                             rom_size[1],
-                            data->image.entry_addr);
+                            data);
 }
 
 #else  //!SOC_MMU_DI_VADDR_SHARED
@@ -814,7 +838,7 @@ static void unpack_load_app(const esp_image_metadata_t *data)
                             irom_addr,
                             irom_load_addr,
                             irom_size,
-                            data->image.entry_addr);
+                            data);
 }
 #endif  //#if SOC_MMU_DI_VADDR_SHARED
 
@@ -839,9 +863,11 @@ static void set_cache_and_start_app(
     uint32_t irom_addr,
     uint32_t irom_load_addr,
     uint32_t irom_size,
-    uint32_t entry_addr)
+    const esp_image_metadata_t *data)
 {
     int rc __attribute__((unused));
+    const uint32_t entry_addr = data->image.entry_addr;
+    const uint32_t mmu_page_size = data->mmu_page_size;
 
     ESP_EARLY_LOGD(TAG, "configure drom and irom and start");
     //-----------------------Disable Cache to do the mapping---------
@@ -851,12 +877,18 @@ static void set_cache_and_start_app(
 #else
     cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
 #endif
+
+#if SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    // re-configure MMU page size
+    mmu_ll_set_page_size(0, mmu_page_size);
+#endif //SOC_MMU_PAGE_SIZE_CONFIGURABLE
+
     //reset MMU table first
     mmu_hal_unmap_all();
 
     //-----------------------MAP DROM--------------------------
-    uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK;
-    uint32_t drom_addr_aligned = drom_addr & MMU_FLASH_MASK;
+    uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK_FROM_VAL(mmu_page_size);
+    uint32_t drom_addr_aligned = drom_addr & MMU_FLASH_MASK_FROM_VAL(mmu_page_size);
     ESP_EARLY_LOGV(TAG, "rodata starts from paddr=0x%08" PRIx32 ", vaddr=0x%08" PRIx32 ", size=0x%" PRIx32, drom_addr, drom_load_addr, drom_size);
     //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
     drom_size = (drom_load_addr - drom_load_addr_aligned) + drom_size;
@@ -874,13 +906,13 @@ static void set_cache_and_start_app(
         ESP_EARLY_LOGV(TAG, "after mapping rodata, starting from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, drom_load_addr_aligned, actual_mapped_len);
     }
     //we use the MMU_LL_END_DROM_ENTRY_ID mmu entry as a map page for app to find the boot partition
-    mmu_hal_map_region(0, MMU_TARGET_FLASH0, MMU_LL_END_DROM_ENTRY_VADDR, drom_addr_aligned, CONFIG_MMU_PAGE_SIZE, &actual_mapped_len);
+    mmu_hal_map_region(0, MMU_TARGET_FLASH0, MMU_DROM_END_ENTRY_VADDR_FROM_VAL(mmu_page_size), drom_addr_aligned, mmu_page_size, &actual_mapped_len);
     ESP_EARLY_LOGV(TAG, "mapped one page of the rodata, from paddr=0x%08" PRIx32 " and vaddr=0x%08" PRIx32 ", 0x%" PRIx32 " bytes are mapped", drom_addr_aligned, MMU_LL_END_DROM_ENTRY_VADDR, actual_mapped_len);
 #endif
 
     //-----------------------MAP IROM--------------------------
-    uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK;
-    uint32_t irom_addr_aligned = irom_addr & MMU_FLASH_MASK;
+    uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK_FROM_VAL(mmu_page_size);
+    uint32_t irom_addr_aligned = irom_addr & MMU_FLASH_MASK_FROM_VAL(mmu_page_size);
     ESP_EARLY_LOGV(TAG, "text starts from paddr=0x%08" PRIx32 ", vaddr=0x%08" PRIx32 ", size=0x%" PRIx32, irom_addr, irom_load_addr, irom_size);
     //The addr is aligned, so we add the mask off length to the size, to make sure the corresponding buses are enabled.
     irom_size = (irom_load_addr - irom_load_addr_aligned) + irom_size;
diff --git a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
index 0f53f259ad5..4d572e102ba 100644
--- a/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
+++ b/components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
@@ -85,18 +85,20 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }
 
 static inline void bootloader_ana_reset_config(void)
 {
-    // TODO: [ESP32C5] IDF-8650
-    //Enable super WDT reset.
-    // bootloader_ana_super_wdt_reset_config(true);
     //Enable BOD reset (mode1)
     brownout_ll_ana_reset_enable(true);
+    if (efuse_hal_chip_revision() == 0) {
+        // decrease power glitch reset voltage to avoid start the glitch reset
+        uint8_t power_glitch_dref = 0;
+        bootloader_power_glitch_reset_config(true, power_glitch_dref);
+    }
 }
 
 esp_err_t bootloader_init(void)
diff --git a/components/bootloader_support/src/esp32c5/bootloader_soc.c b/components/bootloader_support/src/esp32c5/bootloader_soc.c
index 95238f511e9..1e4335491b9 100644
--- a/components/bootloader_support/src/esp32c5/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32c5/bootloader_soc.c
@@ -7,18 +7,29 @@
 #include <assert.h>
 #include "soc/soc.h"
 #include "soc/lp_analog_peri_reg.h"
-// TODO: [ESP32C5] IDF-8667 remove esp_log.h
-#include "esp_log.h"
-
-void bootloader_ana_super_wdt_reset_config(bool enable)
-{
-    // TODO: [ESP32C5] IDF-8667
-    ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
-}
+#include "soc/pmu_reg.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
 
 //Not supported but common bootloader calls the function. Do nothing
 void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
-     // TODO: [ESP32C5] IDF-8667, PM-207
     (void)enable;
 }
+
+void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
+{
+    assert(dref < 8);
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    if (enable) {
+        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
+        REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
+    } else {
+        REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
+    }
+}
diff --git a/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c b/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c
index 03af18a1dbf..ad90f306c01 100644
--- a/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c
+++ b/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c
@@ -11,9 +11,8 @@
 #include "esp_efuse_table.h"
 #include "esp_log.h"
 #include "sdkconfig.h"
-#include "soc/keymng_reg.h"
-#include "soc/pcr_reg.h"
-#include "soc/pcr_struct.h"
+#include "hal/key_mgr_ll.h"
+#include "hal/mspi_timing_tuning_ll.h"
 
 static __attribute__((unused)) const char *TAG = "flash_encrypt";
 
@@ -62,30 +61,21 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
     return ESP_OK;
 }
 
-// TODO: Update to use LL APIs once key manager support added in IDF-8621
 esp_err_t esp_flash_encryption_enable_key_mgr(void)
 {
-    // Set the force power down bit to 0 to enable key manager
-    PCR.km_pd_ctrl.km_mem_force_pd = 0;
-    // Reset the key manager
-    PCR.km_conf.km_clk_en = 1;
-    PCR.km_conf.km_rst_en = 1;
-    PCR.km_conf.km_rst_en = 0;
+    // Enable and reset key manager
+    // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
+    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
+    key_mgr_ll_enable_bus_clock(true);
+    key_mgr_ll_enable_peripheral_clock(true);
+    key_mgr_ll_reset_register();
 
-    // Wait for key manager to be ready
-    while (!PCR.km_conf.km_ready) {
+    while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
     };
 
-    // Wait for key manager state machine to be idle
-    while (REG_READ(KEYMNG_STATE_REG) != 0) {
-    };
-
-    // Set the key manager to use efuse key
-    REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 2);
-
-    // Reset MSPI to re-load the flash encryption key
-    REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
-    REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
+    // Force Key Manager to use eFuse key for XTS-AES operation
+    key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
+    _mspi_timing_ll_reset_mspi();
 
     return ESP_OK;
 }
diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
index 2930188405c..f44372ae417 100644
--- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
+++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
@@ -96,7 +96,7 @@ static inline void bootloader_hardware_init(void)
     esp_rom_spiflash_fix_dummylen(1, 1);
 #endif
 
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_configure_clock();
 }
 
diff --git a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
index 8d62e4746e8..98b485857a7 100644
--- a/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
@@ -86,24 +86,24 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
     regi2c_ctrl_ll_master_configure_clock();
 }
 
 static inline void bootloader_ana_reset_config(void)
 {
-    //Enable super WDT reset.
-    bootloader_ana_super_wdt_reset_config(true);
     //Enable BOD reset (mode1)
     brownout_ll_ana_reset_enable(true);
+    uint8_t power_glitch_dref = 0;
+    bootloader_power_glitch_reset_config(true, power_glitch_dref);
 }
 
 esp_err_t bootloader_init(void)
 {
     esp_err_t ret = ESP_OK;
     bootloader_hardware_init();
-    // bootloader_ana_reset_config();   //TODO: [ESP32C61] IDF-9260
+    bootloader_ana_reset_config();
     bootloader_super_wdt_auto_feed();
 
 // In RAM_APP, memory will be initialized in `call_start_cpu0`
diff --git a/components/bootloader_support/src/esp32c61/bootloader_soc.c b/components/bootloader_support/src/esp32c61/bootloader_soc.c
index e2876607d66..ef415ace135 100644
--- a/components/bootloader_support/src/esp32c61/bootloader_soc.c
+++ b/components/bootloader_support/src/esp32c61/bootloader_soc.c
@@ -7,19 +7,29 @@
 #include <assert.h>
 #include "soc/soc.h"
 #include "soc/lp_analog_peri_reg.h"
+#include "soc/pmu_reg.h"
+#include "hal/regi2c_ctrl.h"
+#include "soc/regi2c_saradc.h"
 
-//TODO: [ESP32C61] IDF-9260, commented in verify code, check
-
-void bootloader_ana_super_wdt_reset_config(bool enable)
+void bootloader_ana_clock_glitch_reset_config(bool enable)
 {
-    //C61 doesn't support bypass super WDT reset
-    assert(enable);
-    // lp_analog_peri_reg.h updated, now following registers
-    // REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
+    // TODO: IDF-9274
+    (void)enable;
 }
 
-//Not supported but common bootloader calls the function. Do nothing
-void bootloader_ana_clock_glitch_reset_config(bool enable)
+void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
 {
-    (void)enable;
+    assert(dref < 8);
+    REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
+    if (enable) {
+        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
+        SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLLBB, dref);
+        REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
+        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
+    } else {
+        REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
+    }
 }
diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
index 74d88a20b70..0aa5bea4a36 100644
--- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
+++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
@@ -90,7 +90,7 @@ static inline void bootloader_hardware_init(void)
     CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
 
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_configure_clock();
 }
 
diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
index 7b0d9fd68d9..9780850c8cf 100644
--- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
@@ -95,8 +95,7 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_RC_ATOMIC_ENV
-    regi2c_ctrl_ll_master_enable_clock(true);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
     regi2c_ctrl_ll_master_configure_clock();
 
     unsigned chip_version = efuse_hal_chip_revision();
diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c
index 6b2f88a7ba5..bb57d9f698e 100644
--- a/components/bootloader_support/src/esp_image_format.c
+++ b/components/bootloader_support/src/esp_image_format.c
@@ -22,6 +22,7 @@
 #include "bootloader_memory_utils.h"
 #include "soc/soc_caps.h"
 #include "hal/cache_ll.h"
+#include "spi_flash_mmap.h"
 
 #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
 
@@ -77,7 +78,7 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
 static esp_err_t verify_image_header(uint32_t src_addr, const esp_image_header_t *image, bool silent);
 
 /* Verify a segment header */
-static esp_err_t verify_segment_header(int index, const esp_image_segment_header_t *segment, uint32_t segment_data_offs, bool silent);
+static esp_err_t verify_segment_header(int index, const esp_image_segment_header_t *segment, uint32_t segment_data_offs, esp_image_metadata_t *metadata, bool silent);
 
 /* Log-and-fail macro for use in esp_image_load */
 #define FAIL_LOAD(...) do {                         \
@@ -102,6 +103,24 @@ static esp_err_t process_checksum(bootloader_sha256_handle_t sha_handle, uint32_
 static esp_err_t __attribute__((unused)) verify_secure_boot_signature(bootloader_sha256_handle_t sha_handle, esp_image_metadata_t *data, uint8_t *image_digest, uint8_t *verified_digest);
 static esp_err_t __attribute__((unused)) verify_simple_hash(bootloader_sha256_handle_t sha_handle, esp_image_metadata_t *data);
 
+static uint32_t s_bootloader_partition_offset = ESP_PRIMARY_BOOTLOADER_OFFSET;
+
+uint32_t esp_image_bootloader_offset_get(void)
+{
+    return s_bootloader_partition_offset;
+}
+
+void esp_image_bootloader_offset_set(const uint32_t offset)
+{
+    s_bootloader_partition_offset = offset;
+    ESP_LOGI(TAG, "Bootloader offsets for PRIMARY: 0x%x, Secondary: 0x%" PRIx32, ESP_PRIMARY_BOOTLOADER_OFFSET, s_bootloader_partition_offset);
+}
+
+static bool is_bootloader(uint32_t offset)
+{
+    return ((offset == ESP_PRIMARY_BOOTLOADER_OFFSET) || (offset == s_bootloader_partition_offset));
+}
+
 static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_t *part, esp_image_metadata_t *data)
 {
 #ifdef BOOTLOADER_BUILD
@@ -135,7 +154,7 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
     // For secure boot V1 on ESP32, we don't calculate SHA or verify signature on bootloaders.
     // (For non-secure boot, we don't verify any SHA-256 hash appended to the bootloader because
     // esptool.py may have rewritten the header - rely on esptool.py having verified the bootloader at flashing time, instead.)
-    verify_sha = (part->offset != ESP_BOOTLOADER_OFFSET) && do_verify;
+    verify_sha = !is_bootloader(part->offset) && do_verify;
 #endif
 
     if (part->size > SIXTEEN_MB) {
@@ -199,7 +218,7 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
 #if CONFIG_SECURE_BOOT_V2_ENABLED
     ESP_FAULT_ASSERT(!esp_secure_boot_enabled() || memcmp(image_digest, verified_digest, HASH_LEN) == 0);
 #else // Secure Boot V1 on ESP32, only verify signatures for apps not bootloaders
-    ESP_FAULT_ASSERT(data->start_addr == ESP_BOOTLOADER_OFFSET || memcmp(image_digest, verified_digest, HASH_LEN) == 0);
+    ESP_FAULT_ASSERT(is_bootloader(data->start_addr) || memcmp(image_digest, verified_digest, HASH_LEN) == 0);
 #endif
 
 #endif // SECURE_BOOT_CHECK_SIGNATURE
@@ -332,7 +351,8 @@ static esp_err_t verify_image_header(uint32_t src_addr, const esp_image_header_t
     // Checking the chip revision header *will* print a bunch of other info
     // regardless of silent setting as this may be important, but don't bother checking it
     // if it looks like the app partition is erased or otherwise garbage
-    CHECK_ERR(bootloader_common_check_chip_validity(image, ESP_IMAGE_APPLICATION));
+    esp_image_type image_type = is_bootloader(src_addr) ? ESP_IMAGE_BOOTLOADER : ESP_IMAGE_APPLICATION;
+    CHECK_ERR(bootloader_common_check_chip_validity(image, image_type));
 
     if (image->segment_count > ESP_IMAGE_MAX_SEGMENTS) {
         FAIL_LOAD("image at 0x%"PRIx32" segment count %d exceeds max %d", src_addr, image->segment_count, ESP_IMAGE_MAX_SEGMENTS);
@@ -559,7 +579,7 @@ static esp_err_t process_segment(int index, uint32_t flash_addr, esp_image_segme
 
     ESP_LOGV(TAG, "segment data length 0x%"PRIx32" data starts 0x%"PRIx32, data_len, data_addr);
 
-    CHECK_ERR(verify_segment_header(index, header, data_addr, silent));
+    CHECK_ERR(verify_segment_header(index, header, data_addr, metadata, silent));
 
     if (data_len % 4 != 0) {
         FAIL_LOAD("unaligned segment length 0x%"PRIx32, data_len);
@@ -695,7 +715,7 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
     // Case II: Bootloader verifying bootloader
     // The esp_app_desc_t structure is located in DROM and is always in segment #0.
     // Anti-rollback check and efuse block version check should handle only Case I from above.
-    if (segment == 0 && metadata->start_addr != ESP_BOOTLOADER_OFFSET) {
+    if (segment == 0 && !is_bootloader(metadata->start_addr)) {
 /* ESP32 doesn't have more memory and more efuse bits for block major version. */
 #if !CONFIG_IDF_TARGET_ESP32
         const esp_app_desc_t *app_desc = (const esp_app_desc_t *)src;
@@ -748,7 +768,7 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
     return ESP_OK;
 }
 
-static esp_err_t verify_segment_header(int index, const esp_image_segment_header_t *segment, uint32_t segment_data_offs, bool silent)
+static esp_err_t verify_segment_header(int index, const esp_image_segment_header_t *segment, uint32_t segment_data_offs, esp_image_metadata_t *metadata, bool silent)
 {
     if ((segment->data_len & 3) != 0
             || segment->data_len >= SIXTEEN_MB) {
@@ -761,13 +781,39 @@ static esp_err_t verify_segment_header(int index, const esp_image_segment_header
     uint32_t load_addr = segment->load_addr;
     bool map_segment = should_map(load_addr);
 
+#if SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    /* ESP APP descriptor is present in the DROM segment #0 */
+    if (index == 0 && !is_bootloader(metadata->start_addr)) {
+        const esp_app_desc_t *app_desc = (const esp_app_desc_t *)bootloader_mmap(segment_data_offs, sizeof(esp_app_desc_t));
+        if (!app_desc || app_desc->magic_word != ESP_APP_DESC_MAGIC_WORD) {
+            ESP_LOGE(TAG, "Failed to fetch app description header!");
+            return ESP_FAIL;
+        }
+
+        // Convert from log base 2 number to actual size while handling legacy image case (value 0)
+        metadata->mmu_page_size = (app_desc->mmu_page_size > 0) ? (1UL << app_desc->mmu_page_size) : SPI_FLASH_MMU_PAGE_SIZE;
+        if (metadata->mmu_page_size != SPI_FLASH_MMU_PAGE_SIZE) {
+            ESP_LOGI(TAG, "MMU page size mismatch, configured: 0x%x, found: 0x%"PRIx32, SPI_FLASH_MMU_PAGE_SIZE, metadata->mmu_page_size);
+        }
+        bootloader_munmap(app_desc);
+    } else if (index == 0 && is_bootloader(metadata->start_addr)) {
+        // Bootloader always uses the default MMU page size
+        metadata->mmu_page_size = SPI_FLASH_MMU_PAGE_SIZE;
+    }
+#else // SOC_MMU_PAGE_SIZE_CONFIGURABLE
+    metadata->mmu_page_size = SPI_FLASH_MMU_PAGE_SIZE;
+#endif // !SOC_MMU_PAGE_SIZE_CONFIGURABLE
+
+    const int mmu_page_size = metadata->mmu_page_size;
+    ESP_LOGV(TAG, "MMU page size 0x%x", mmu_page_size);
+
     /* Check that flash cache mapped segment aligns correctly from flash to its mapped address,
-       relative to the 64KB page mapping size.
+       relative to the MMU page mapping size.
     */
     ESP_LOGV(TAG, "segment %d map_segment %d segment_data_offs 0x%"PRIx32" load_addr 0x%"PRIx32,
              index, map_segment, segment_data_offs, load_addr);
     if (map_segment
-            && ((segment_data_offs % SPI_FLASH_MMU_PAGE_SIZE) != (load_addr % SPI_FLASH_MMU_PAGE_SIZE))) {
+            && ((segment_data_offs % mmu_page_size) != (load_addr % mmu_page_size))) {
         if (!silent) {
             ESP_LOGE(TAG, "Segment %d load address 0x%08"PRIx32", doesn't match data 0x%08"PRIx32,
                      index, load_addr, segment_data_offs);
@@ -847,8 +893,8 @@ esp_err_t esp_image_verify_bootloader_data(esp_image_metadata_t *data)
         return ESP_ERR_INVALID_ARG;
     }
     const esp_partition_pos_t bootloader_part = {
-        .offset = ESP_BOOTLOADER_OFFSET,
-        .size = ESP_PARTITION_TABLE_OFFSET - ESP_BOOTLOADER_OFFSET,
+        .offset = ESP_PRIMARY_BOOTLOADER_OFFSET,
+        .size = ESP_BOOTLOADER_SIZE,
     };
     return esp_image_verify(ESP_IMAGE_VERIFY,
                             &bootloader_part,
@@ -871,7 +917,7 @@ static esp_err_t process_appended_hash_and_sig(esp_image_metadata_t *data, uint3
 #if CONFIG_SECURE_BOOT || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT
 
     // Case I: Bootloader part
-    if (part_offset == ESP_BOOTLOADER_OFFSET) {
+    if (is_bootloader(part_offset)) {
         // For bootloader with secure boot v1, signature stays in an independent flash
         // sector (offset 0x0)  and does not get appended to the image.
 #if CONFIG_SECURE_BOOT_V2_ENABLED
@@ -1005,7 +1051,7 @@ static esp_err_t verify_secure_boot_signature(bootloader_sha256_handle_t sha_han
 #if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME || CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME
     data->image_len = end - data->start_addr + sizeof(ets_secure_boot_signature_t);
 #elif defined(CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME)
-    if (data->start_addr != ESP_BOOTLOADER_OFFSET) {
+    if (!is_bootloader(data->start_addr)) {
         data->image_len = end - data->start_addr + sizeof(esp_secure_boot_sig_block_t);
     }
 #endif
diff --git a/components/bootloader_support/src/flash_encryption/flash_encrypt.c b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
index 92bc72b21f6..8a75cd2f111 100644
--- a/components/bootloader_support/src/flash_encryption/flash_encrypt.c
+++ b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
@@ -43,7 +43,7 @@ static const char *TAG = "flash_encrypt";
 
 /* Static functions for stages of flash encryption */
 static esp_err_t encrypt_bootloader(void);
-static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partition_table, int *num_partitions);
+static esp_err_t encrypt_and_load_partition_table(uint32_t offset, esp_partition_info_t *partition_table, int *num_partitions);
 static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partition);
 static size_t get_flash_encrypt_cnt_value(void);
 
@@ -258,17 +258,16 @@ esp_err_t esp_flash_encrypt_contents(void)
     REG_WRITE(SENSITIVE_XTS_AES_KEY_UPDATE_REG, 1);
 #endif
 
-// TODO: Remove C5 target config after key manager LL support- see IDF-8621
-#if CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY
     esp_flash_encryption_enable_key_mgr();
 #endif
 
-    err = encrypt_bootloader();
+    err = encrypt_bootloader(); // PART_SUBTYPE_BOOTLOADER_PRIMARY
     if (err != ESP_OK) {
         return err;
     }
 
-    err = encrypt_and_load_partition_table(partition_table, &num_partitions);
+    err = encrypt_and_load_partition_table(ESP_PRIMARY_PARTITION_TABLE_OFFSET, partition_table, &num_partitions);  // PART_SUBTYPE_PARTITION_TABLE_PRIMARY
     if (err != ESP_OK) {
         return err;
     }
@@ -278,6 +277,14 @@ esp_err_t esp_flash_encrypt_contents(void)
 
     /* Go through each partition and encrypt if necessary */
     for (int i = 0; i < num_partitions; i++) {
+        if ((partition_table[i].type == PART_TYPE_BOOTLOADER && partition_table[i].subtype == PART_SUBTYPE_BOOTLOADER_PRIMARY)
+             || (partition_table[i].type == PART_TYPE_PARTITION_TABLE && partition_table[i].subtype == PART_SUBTYPE_PARTITION_TABLE_PRIMARY)) {
+            /* Skip encryption of PRIMARY partitions for bootloader and partition table.
+             * PRIMARY partitions have already been encrypted above.
+             * We allow to encrypt partitions that are not PRIMARY.
+             */
+            continue;
+        }
         err = encrypt_partition(i, &partition_table[i]);
         if (err != ESP_OK) {
             return err;
@@ -338,13 +345,13 @@ static esp_err_t encrypt_bootloader(void)
 
 #if CONFIG_SECURE_BOOT_V2_ENABLED
         /* The image length obtained from esp_image_verify_bootloader includes the sector boundary padding and the signature block lengths */
-        if (ESP_BOOTLOADER_OFFSET + image_length > ESP_PARTITION_TABLE_OFFSET) {
-            ESP_LOGE(TAG, "Bootloader is too large to fit Secure Boot V2 signature sector and partition table (configured offset 0x%x)", ESP_PARTITION_TABLE_OFFSET);
+        if (image_length > ESP_BOOTLOADER_SIZE) {
+            ESP_LOGE(TAG, "Bootloader is too large to fit Secure Boot V2 signature sector and partition table (configured offset 0x%x)", ESP_PRIMARY_PARTITION_TABLE_OFFSET);
             return ESP_ERR_INVALID_SIZE;
         }
 #endif // CONFIG_SECURE_BOOT_V2_ENABLED
 
-        err = esp_flash_encrypt_region(ESP_BOOTLOADER_OFFSET, image_length);
+        err = esp_flash_encrypt_region(ESP_PRIMARY_BOOTLOADER_OFFSET, image_length);
         if (err != ESP_OK) {
             ESP_LOGE(TAG, "Failed to encrypt bootloader in place: 0x%x", err);
             return err;
@@ -369,53 +376,64 @@ static esp_err_t encrypt_bootloader(void)
     return ESP_OK;
 }
 
-static esp_err_t encrypt_and_load_partition_table(esp_partition_info_t *partition_table, int *num_partitions)
+static esp_err_t read_and_verify_partition_table(uint32_t offset, esp_partition_info_t *partition_table, int *num_partitions)
 {
     esp_err_t err;
     /* Check for plaintext partition table */
-    err = bootloader_flash_read(ESP_PARTITION_TABLE_OFFSET, partition_table, ESP_PARTITION_TABLE_MAX_LEN, false);
+    err = bootloader_flash_read(offset, partition_table, ESP_PARTITION_TABLE_MAX_LEN, false);
     if (err != ESP_OK) {
-        ESP_LOGE(TAG, "Failed to read partition table data");
+        ESP_LOGE(TAG, "Failed to read partition table data at 0x%" PRIx32, offset);
         return err;
     }
-    if (esp_partition_table_verify(partition_table, false, num_partitions) == ESP_OK) {
-        ESP_LOGD(TAG, "partition table is plaintext. Encrypting...");
-        esp_err_t err = esp_flash_encrypt_region(ESP_PARTITION_TABLE_OFFSET,
-                                                 FLASH_SECTOR_SIZE);
-        if (err != ESP_OK) {
-            ESP_LOGE(TAG, "Failed to encrypt partition table in place. %x", err);
-            return err;
-        }
-    } else {
-        ESP_LOGE(TAG, "Failed to read partition table data - not plaintext?");
-        return ESP_ERR_INVALID_STATE;
+    err = esp_partition_table_verify(partition_table, false, num_partitions);
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Failed to read partition table data - not plaintext or empty?");
     }
+    return err;
+}
 
-    /* Valid partition table loaded */
+static esp_err_t encrypt_and_load_partition_table(uint32_t offset, esp_partition_info_t *partition_table, int *num_partitions)
+{
+    esp_err_t err = read_and_verify_partition_table(offset, partition_table, num_partitions);
+    if (err != ESP_OK) {
+        return err;
+    }
+    ESP_LOGD(TAG, "partition table is plaintext. Encrypting...");
+    err = esp_flash_encrypt_region(offset, FLASH_SECTOR_SIZE);
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Failed to encrypt partition table in place. %x", err);
+        return err;
+    }
     ESP_LOGI(TAG, "partition table encrypted and loaded successfully");
-    return ESP_OK;
+    return err;
 }
 
-
 static esp_err_t encrypt_partition(int index, const esp_partition_info_t *partition)
 {
     esp_err_t err;
     bool should_encrypt = (partition->flags & PART_FLAG_ENCRYPTED);
     uint32_t size = partition->pos.size;
 
-    if (partition->type == PART_TYPE_APP) {
-        /* check if the partition holds a valid unencrypted app */
+    if (partition->type == PART_TYPE_APP || partition->type == PART_TYPE_BOOTLOADER) {
+        /* check if the partition holds a valid unencrypted app/bootloader */
         esp_image_metadata_t image_data = {};
-        err = esp_image_verify(ESP_IMAGE_VERIFY,
-                               &partition->pos,
-                               &image_data);
+        if (partition->type == PART_TYPE_BOOTLOADER) {
+            esp_image_bootloader_offset_set(partition->pos.offset);
+        }
+        err = esp_image_verify(ESP_IMAGE_VERIFY, &partition->pos, &image_data);
         should_encrypt = (err == ESP_OK);
 #ifdef CONFIG_SECURE_FLASH_ENCRYPT_ONLY_IMAGE_LEN_IN_APP_PART
-        if (should_encrypt) {
+        if (partition->type == PART_TYPE_APP && should_encrypt) {
             // Encrypt only the app image instead of encrypting the whole partition
             size = image_data.image_len;
         }
 #endif
+    } else if (partition->type == PART_TYPE_PARTITION_TABLE) {
+        /* check if the partition holds a valid unencrypted partition table */
+        esp_partition_info_t partition_table[ESP_PARTITION_TABLE_MAX_ENTRIES];
+        int num_partitions;
+        err = read_and_verify_partition_table(partition->pos.offset, partition_table, &num_partitions);
+        should_encrypt = (err == ESP_OK && num_partitions != 0);
     } else if ((partition->type == PART_TYPE_DATA && partition->subtype == PART_SUBTYPE_DATA_OTA)
                 || (partition->type == PART_TYPE_DATA && partition->subtype == PART_SUBTYPE_DATA_NVS_KEYS)) {
         /* check if we have ota data partition and the partition should be encrypted unconditionally */
diff --git a/components/bootloader_support/src/flash_partitions.c b/components/bootloader_support/src/flash_partitions.c
index 69cf92cbc08..8d0abd039d8 100644
--- a/components/bootloader_support/src/flash_partitions.c
+++ b/components/bootloader_support/src/flash_partitions.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -52,10 +52,11 @@ esp_err_t esp_partition_table_verify(const esp_partition_info_t *partition_table
                 }
                 return ESP_ERR_INVALID_STATE;
             }
-            //MD5 checksum matches and we continue with the next interation in
+            //MD5 checksum matches and we continue with the next iteration in
             //order to detect the end of the partition table
             md5_found = 1;
-        } else if (part->magic == 0xFFFF
+        } else if (num_parts != 0 // the first record cannot be empty, otherwise the whole table is empty
+                   && part->magic == 0xFFFF
                    && part->type == PART_TYPE_END
                    && part->subtype == PART_SUBTYPE_END) {
             ESP_LOGD(TAG, "partition table verified, %d entries", num_parts);
diff --git a/components/bootloader_support/test_apps/.build-test-rules.yml b/components/bootloader_support/test_apps/.build-test-rules.yml
index 859b46f7aa5..1dbe91f9132 100644
--- a/components/bootloader_support/test_apps/.build-test-rules.yml
+++ b/components/bootloader_support/test_apps/.build-test-rules.yml
@@ -4,7 +4,3 @@ components/bootloader_support/test_apps/rtc_custom_section:
   enable:
     - if: SOC_RTC_MEM_SUPPORTED == 1
       reason: this feature is supported on chips that have RTC memory
-  disable:
-    - if: IDF_TARGET == "esp32c61"
-      temporary: true
-      reason: IDF-9260
diff --git a/components/bt/CMakeLists.txt b/components/bt/CMakeLists.txt
index 70f8aacbbe1..143c8e3efb2 100644
--- a/components/bt/CMakeLists.txt
+++ b/components/bt/CMakeLists.txt
@@ -39,12 +39,20 @@ set(ble_mesh_include_dirs
     "esp_ble_mesh/api/core/include"
     "esp_ble_mesh/api/models/include"
     "esp_ble_mesh/api"
+)
+
+set(ble_mesh_v11_include_dirs
     "esp_ble_mesh/lib/include"
     "esp_ble_mesh/v1.1/api/core/include"
     "esp_ble_mesh/v1.1/api/models/include"
     "esp_ble_mesh/v1.1/btc/include"
 )
 
+if(CONFIG_IDF_DOC_BUILD)
+    list(APPEND ble_mesh_include_dirs
+                ${ble_mesh_v11_include_dirs})
+endif()
+
 set(bluedroid_include_dirs host/bluedroid/api/include/api)
 
 if(CONFIG_BT_CONTROLLER_ENABLED OR CONFIG_IDF_DOC_BUILD)
@@ -524,34 +532,41 @@ if(CONFIG_BT_ENABLED)
                     "esp_ble_mesh/models/server/server_common.c"
                     "esp_ble_mesh/models/server/state_binding.c"
                     "esp_ble_mesh/models/server/state_transition.c"
-                    "esp_ble_mesh/models/server/time_scene_server.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_agg_model_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_brc_model_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_cm_data_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_df_model_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_lcd_model_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_odp_model_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_prb_model_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_rpr_model_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_sar_model_api.c"
-                    "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_srpl_model_api.c"
-                    "esp_ble_mesh/v1.1/api/models/esp_ble_mesh_mbt_model_api.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_agg_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_brc_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_df_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_lcd_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_mbt_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_odp_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_prb_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_rpr_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_sar_model.c"
-                    "esp_ble_mesh/v1.1/btc/btc_ble_mesh_srpl_model.c"
-                    "esp_ble_mesh/lib/ext.c")
-
-        if(CONFIG_BLE_MESH_SAR_ENHANCEMENT)
-            list(APPEND srcs "esp_ble_mesh/core/transport.enh.c")
+                    "esp_ble_mesh/models/server/time_scene_server.c")
+        if(CONFIG_BLE_MESH_V11_SUPPORT)
+            list(APPEND include_dirs ${ble_mesh_v11_include_dirs})
+
+            list(APPEND srcs
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_agg_model_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_brc_model_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_cm_data_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_df_model_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_lcd_model_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_odp_model_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_prb_model_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_rpr_model_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_sar_model_api.c"
+                        "esp_ble_mesh/v1.1/api/core/esp_ble_mesh_srpl_model_api.c"
+                        "esp_ble_mesh/v1.1/api/models/esp_ble_mesh_mbt_model_api.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_agg_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_brc_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_df_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_lcd_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_mbt_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_odp_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_prb_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_rpr_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_sar_model.c"
+                        "esp_ble_mesh/v1.1/btc/btc_ble_mesh_srpl_model.c"
+                        "esp_ble_mesh/lib/ext.c")
+            if(CONFIG_BLE_MESH_SAR_ENHANCEMENT)
+                list(APPEND srcs "esp_ble_mesh/core/transport.enh.c")
+            else()
+                list(APPEND srcs "esp_ble_mesh/core/transport.c")
+            endif()
         else()
-            list(APPEND srcs "esp_ble_mesh/core/transport.c")
+            list(APPEND srcs
+                        "esp_ble_mesh/core/transport.c")
         endif()
     endif()
 
@@ -850,11 +865,19 @@ if(CONFIG_BT_ENABLED)
     elseif(CONFIG_IDF_TARGET_ESP32C3)
         target_link_directories(${COMPONENT_LIB} INTERFACE
                 "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32c3")
-        target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
+        if(CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+            target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app_flash)
+        else()
+            target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
+        endif()
     elseif(CONFIG_IDF_TARGET_ESP32S3)
         target_link_directories(${COMPONENT_LIB} INTERFACE
                 "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
-        target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
+        if(CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+            target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app_flash)
+        else()
+            target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
+        endif()
     elseif(CONFIG_BT_CONTROLLER_ENABLED)
         if(CONFIG_IDF_TARGET_ESP32C6)
             add_prebuilt_library(libble_app
@@ -879,7 +902,7 @@ if(CONFIG_BT_ENABLED)
     target_compile_options(${COMPONENT_LIB} PRIVATE "-Wno-format")
 endif()
 
-if(CONFIG_BLE_MESH)
+if(CONFIG_BLE_MESH_V11_SUPPORT)
     if(CONFIG_IDF_TARGET_ESP32)
         add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32/libble_mesh.a")
         target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh)
@@ -892,6 +915,9 @@ if(CONFIG_BLE_MESH)
     elseif(CONFIG_IDF_TARGET_ESP32C6)
         add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32c6/libble_mesh.a")
         target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh)
+    elseif(CONFIG_IDF_TARGET_ESP32C61)
+        add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32c61/libble_mesh.a")
+        target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh)
     elseif(CONFIG_IDF_TARGET_ESP32H2)
         add_prebuilt_library(ble_mesh "esp_ble_mesh/lib/lib/esp32h2/libble_mesh.a")
         target_link_libraries(${COMPONENT_LIB} PRIVATE ble_mesh)
diff --git a/components/bt/common/btc/core/btc_task.c b/components/bt/common/btc/core/btc_task.c
index 875f64b18a5..c3a0bd2bee9 100644
--- a/components/bt/common/btc/core/btc_task.c
+++ b/components/bt/common/btc/core/btc_task.c
@@ -69,6 +69,12 @@
 #include "btc_ble_mesh_prov.h"
 #include "btc_ble_mesh_health_model.h"
 #include "btc_ble_mesh_config_model.h"
+#include "btc_ble_mesh_generic_model.h"
+#include "btc_ble_mesh_lighting_model.h"
+#include "btc_ble_mesh_sensor_model.h"
+#include "btc_ble_mesh_time_scene_model.h"
+#if CONFIG_BLE_MESH_V11_SUPPORT
+#include "btc_ble_mesh_mbt_model.h"
 #include "btc_ble_mesh_agg_model.h"
 #include "btc_ble_mesh_brc_model.h"
 #include "btc_ble_mesh_df_model.h"
@@ -78,11 +84,7 @@
 #include "btc_ble_mesh_rpr_model.h"
 #include "btc_ble_mesh_sar_model.h"
 #include "btc_ble_mesh_srpl_model.h"
-#include "btc_ble_mesh_generic_model.h"
-#include "btc_ble_mesh_lighting_model.h"
-#include "btc_ble_mesh_sensor_model.h"
-#include "btc_ble_mesh_time_scene_model.h"
-#include "btc_ble_mesh_mbt_model.h"
+#endif /* CONFIG_BLE_MESH_V11_SUPPORT */
 #endif /* #if CONFIG_BLE_MESH */
 
 #define BTC_TASK_PINNED_TO_CORE         (TASK_PINNED_TO_CORE)
@@ -252,9 +254,9 @@ static const btc_func_t profile_tab[BTC_PID_NUM] = {
 #if CONFIG_BLE_MESH_MBT_SRV
     [BTC_PID_MBT_SERVER]        = {btc_ble_mesh_mbt_server_call_handler,        btc_ble_mesh_mbt_server_cb_handler       },
 #endif /* CONFIG_BLE_MESH_MBT_SRV */
-#if CONFIG_BLE_MESH_BLE_COEX_SUPPORT
+#if CONFIG_BLE_MESH_BLE_COEX_SUPPORT || CONFIG_BLE_MESH_USE_BLE_50
     [BTC_PID_BLE_MESH_BLE_COEX] = {btc_ble_mesh_ble_call_handler,               btc_ble_mesh_ble_cb_handler              },
-#endif /* CONFIG_BLE_MESH_BLE_COEX_SUPPORT */
+#endif /* CONFIG_BLE_MESH_BLE_COEX_SUPPORT || CONFIG_BLE_MESH_USE_BLE_50 */
 #endif /* #if CONFIG_BLE_MESH */
 };
 
@@ -380,7 +382,7 @@ static void btc_deinit_mem(void) {
         btc_profile_cb_tab = NULL;
     }
 
-#if (BLE_INCLUDED == TRUE)
+#if (BLE_42_FEATURE_SUPPORT == TRUE)
     if (gl_bta_adv_data_ptr) {
         osi_free(gl_bta_adv_data_ptr);
         gl_bta_adv_data_ptr = NULL;
@@ -390,7 +392,7 @@ static void btc_deinit_mem(void) {
         osi_free(gl_bta_scan_rsp_data_ptr);
         gl_bta_scan_rsp_data_ptr = NULL;
     }
-#endif  ///BLE_INCLUDED == TRUE
+#endif // BLE_42_FEATURE_SUPPORT
 
 #if GATTS_INCLUDED == TRUE && GATT_DYNAMIC_MEMORY == TRUE
     if (btc_creat_tab_env_ptr) {
@@ -442,7 +444,8 @@ static bt_status_t btc_init_mem(void) {
     }
     memset((void *)btc_profile_cb_tab, 0, sizeof(void *) * BTC_PID_NUM);
 
-#if (BLE_INCLUDED == TRUE)
+#if BTC_DYNAMIC_MEMORY == TRUE
+#if (BLE_42_FEATURE_SUPPORT == TRUE)
     if ((gl_bta_adv_data_ptr = (tBTA_BLE_ADV_DATA *)osi_malloc(sizeof(tBTA_BLE_ADV_DATA))) == NULL) {
         goto error_exit;
     }
@@ -452,7 +455,8 @@ static bt_status_t btc_init_mem(void) {
         goto error_exit;
     }
     memset((void *)gl_bta_scan_rsp_data_ptr, 0, sizeof(tBTA_BLE_ADV_DATA));
-#endif  ///BLE_INCLUDED == TRUE
+#endif // (BLE_42_FEATURE_SUPPORT == TRUE)
+#endif // BTC_DYNAMIC_MEMORY == TRUE
 
 #if GATTS_INCLUDED == TRUE && GATT_DYNAMIC_MEMORY == TRUE
     if ((btc_creat_tab_env_ptr = (esp_btc_creat_tab_t *)osi_malloc(sizeof(esp_btc_creat_tab_t))) == NULL) {
diff --git a/components/bt/common/hci_log/bt_hci_log.c b/components/bt/common/hci_log/bt_hci_log.c
index e35bf1a7a68..ac85179a707 100644
--- a/components/bt/common/hci_log/bt_hci_log.c
+++ b/components/bt/common/hci_log/bt_hci_log.c
@@ -305,19 +305,27 @@ void bt_hci_log_data_show(bt_hci_log_t *p_hci_log_ctl)
 
     osi_mutex_unlock(&mutex_lock);
 }
+static bool enable_hci_log_flag = true;
+void bt_hci_log_record_hci_enable(bool enable)
+{
+    enable_hci_log_flag = enable;
+}
 
 esp_err_t IRAM_ATTR bt_hci_log_record_hci_data(uint8_t data_type, uint8_t *data, uint8_t data_len)
 {
+    if (!enable_hci_log_flag) return ESP_OK;
     return bt_hci_log_record_data(&g_bt_hci_log_data_ctl, NULL, data_type, data, data_len);
 }
 
 esp_err_t IRAM_ATTR bt_hci_log_record_custom_data(char *string, uint8_t *data, uint8_t data_len)
 {
+    if (!enable_hci_log_flag) return ESP_OK;
     return bt_hci_log_record_data(&g_bt_hci_log_data_ctl, string, HCI_LOG_DATA_TYPE_SELF_DEFINE, data, data_len);
 }
 
 esp_err_t IRAM_ATTR bt_hci_log_record_hci_adv(uint8_t data_type, uint8_t *data, uint8_t data_len)
 {
+    if (!enable_hci_log_flag) return ESP_OK;
     return bt_hci_log_record_data(&g_bt_hci_log_adv_ctl, NULL, data_type, data, data_len);
 }
 
diff --git a/components/bt/common/osi/allocator.c b/components/bt/common/osi/allocator.c
index fba9cf0a9e0..86fb705b071 100644
--- a/components/bt/common/osi/allocator.c
+++ b/components/bt/common/osi/allocator.c
@@ -241,5 +241,8 @@ void *osi_calloc_func(size_t size)
 
 void osi_free_func(void *ptr)
 {
+#if HEAP_MEMORY_DEBUG
+    osi_mem_dbg_clean(ptr, __func__, __LINE__);
+#endif
     free(ptr);
 }
diff --git a/components/bt/common/osi/include/osi/allocator.h b/components/bt/common/osi/include/osi/allocator.h
index 25eca3431b1..d95040538d8 100644
--- a/components/bt/common/osi/include/osi/allocator.h
+++ b/components/bt/common/osi/include/osi/allocator.h
@@ -29,6 +29,15 @@ void *osi_malloc_func(size_t size);
 void *osi_calloc_func(size_t size);
 void osi_free_func(void *ptr);
 
+// Memory alloc function without print and assertion
+#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
+#define osi_malloc_base(size)             heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL)
+#define osi_calloc_base(size)             heap_caps_calloc_prefer(1, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL)
+#else
+#define osi_malloc_base(size)             malloc((size))
+#define osi_calloc_base(size)             calloc(1, (size))
+#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
+
 #if HEAP_MEMORY_DEBUG
 
 void osi_mem_dbg_init(void);
@@ -41,33 +50,10 @@ void osi_men_dbg_set_section_start(uint8_t index);
 void osi_men_dbg_set_section_end(uint8_t index);
 uint32_t osi_mem_dbg_get_max_size_section(uint8_t index);
 
-#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
-#define osi_malloc(size)                                \
-({                                                      \
-    void *p;                                            \
-    p = heap_caps_malloc_prefer(size, 2,                \
-        MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM,           \
-        MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);        \
-    osi_mem_dbg_record(p, size, __func__, __LINE__);    \
-    (void *)p;                                          \
-})
-
-#define osi_calloc(size)                                \
-({                                                      \
-    void *p;                                            \
-    p = heap_caps_calloc_prefer(1, size, 2,             \
-        MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM,           \
-        MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL);        \
-    osi_mem_dbg_record(p, size, __func__, __LINE__);    \
-    (void *)p;                                          \
-})
-
-#else
-
 #define osi_malloc(size)                                \
 ({                                                      \
     void *p;                                            \
-    p = malloc((size));                                 \
+    p = osi_malloc_base(size);                          \
     osi_mem_dbg_record(p, size, __func__, __LINE__);    \
     (void *)p;                                          \
 })
@@ -75,14 +61,11 @@ uint32_t osi_mem_dbg_get_max_size_section(uint8_t index);
 #define osi_calloc(size)                                \
 ({                                                      \
     void *p;                                            \
-    p = calloc(1, (size));                              \
+    p = osi_calloc_base(size);                          \
     osi_mem_dbg_record(p, size, __func__, __LINE__);    \
     (void *)p;                                          \
 })
 
-#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
-
-
 #if 0
 #define osi_malloc(size)                                \
 do {                                                    \
@@ -122,15 +105,6 @@ do {                                                    \
 
 #else
 
-// Memory alloc function without print and assertion
-#if HEAP_ALLOCATION_FROM_SPIRAM_FIRST
-#define osi_malloc_base(size)             heap_caps_malloc_prefer(size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL)
-#define osi_calloc_base(size)             heap_caps_calloc_prefer(1, size, 2, MALLOC_CAP_DEFAULT|MALLOC_CAP_SPIRAM, MALLOC_CAP_DEFAULT|MALLOC_CAP_INTERNAL)
-#else
-#define osi_malloc_base(size)             malloc((size))
-#define osi_calloc_base(size)             calloc(1, (size))
-#endif /* #if HEAP_ALLOCATION_FROM_SPIRAM_FIRST */
-
 // Memory alloc function with print and assertion when fails
 #define osi_malloc(size)                  osi_malloc_func((size))
 #define osi_calloc(size)                  osi_calloc_func((size))
diff --git a/components/bt/controller/esp32/Kconfig.in b/components/bt/controller/esp32/Kconfig.in
index 191738d0d22..80f8bb2d6e8 100644
--- a/components/bt/controller/esp32/Kconfig.in
+++ b/components/bt/controller/esp32/Kconfig.in
@@ -300,10 +300,10 @@ menu "MODEM SLEEP Options"
                 the bluetooth low power clock source.
 
         config BTDM_CTRL_LPCLK_SEL_EXT_32K_XTAL
-            bool "External 32kHz crystal"
-            depends on RTC_CLK_SRC_EXT_CRYS
+            bool "External 32kHz crystal/oscillator"
+            depends on RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
             help
-                External 32kHz crystal has a nominal frequency of 32.768kHz and provides good frequency
+                External 32kHz crystal/oscillator has a nominal frequency of 32.768kHz and provides good frequency
                 stability. If used as Bluetooth low power clock, External 32kHz can support Bluetooth
                 modem sleep to be used with both DFS and light sleep.
     endchoice
@@ -444,6 +444,15 @@ config BTDM_CTRL_SCAN_BACKOFF_UPPERLIMITMAX
         minimize collision of scan request PDUs from nultiple scanners. If scan backoff is disabled, in active
         scanning, scan request PDU will be sent every time when HW receives scannable ADV PDU.
 
+config BTDM_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS
+    bool "Enable enhanced Access Address check in CONNECT_IND"
+    default n
+    help
+        Enabling this option will add stricter verification of the Access Address in the CONNECT_IND PDU.
+        This improves security by ensuring that only connection requests with valid Access Addresses are accepted.
+        If disabled, only basic checks are applied, improving compatibility.
+
+
 config BTDM_BLE_ADV_REPORT_FLOW_CTRL_SUPP
     bool "BLE adv report flow control supported"
     depends on (BTDM_CTRL_MODE_BTDM || BTDM_CTRL_MODE_BLE_ONLY)
@@ -478,6 +487,23 @@ config BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD
         If you set `BTDM_BLE_ADV_REPORT_DISCARD_THRSHOLD` to a small value or printf every adv lost event, it
         may cause adv packets lost more.
 
+menu "BLE disconnect when instant passed"
+    config BTDM_BLE_LLCP_CONN_UPDATE
+        bool "BLE ACL connection update procedure"
+        depends on (BTDM_CTRL_MODE_BLE_ONLY || BTDM_CTRL_MODE_BTDM)
+        default n
+        help
+            If this option is enabled, Controller will terminate the connection
+            when instant passed during connection update procedure.
+
+    config BTDM_BLE_LLCP_CHAN_MAP_UPDATE
+        bool "BLE ACL channel map update procedure"
+        depends on (BTDM_CTRL_MODE_BLE_ONLY || BTDM_CTRL_MODE_BTDM)
+        default n
+        help
+            If this option is enabled, Controller will terminate the connection
+            when instant passed in channel map update procedure.
+endmenu
 
 config BTDM_RESERVE_DRAM
     hex
diff --git a/components/bt/controller/esp32c3/Kconfig.in b/components/bt/controller/esp32c3/Kconfig.in
index 5178ef86021..0121b3404a1 100644
--- a/components/bt/controller/esp32c3/Kconfig.in
+++ b/components/bt/controller/esp32c3/Kconfig.in
@@ -226,6 +226,7 @@ config BT_CTRL_DFT_TX_POWER_LEVEL_EFF
 
 config BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP
     bool "BLE adv report flow control supported"
+    depends on (!BT_CTRL_RUN_IN_FLASH_ONLY) || (BT_CTRL_RUN_IN_FLASH_ONLY && BT_CTRL_BLE_SCAN)
     default y
     help
         The function is mainly used to enable flow control for advertising reports. When it is enabled,
@@ -402,10 +403,10 @@ menu "MODEM SLEEP Options"
                 bluetooth can work under light sleep enabled. Main crystal has a relatively better performance
                 than other bluetooth low power clock sources.
         config BT_CTRL_LPCLK_SEL_EXT_32K_XTAL
-            bool "External 32kHz crystal"
-            depends on RTC_CLK_SRC_EXT_CRYS
+            bool "External 32kHz crystal/oscillator"
+            depends on RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
             help
-                External 32kHz crystal has a nominal frequency of 32.768kHz and provides good frequency
+                External 32kHz crystal/oscillator has a nominal frequency of 32.768kHz and provides good frequency
                 stability. If used as Bluetooth low power clock, External 32kHz can support Bluetooth
                 modem sleep to be used with both DFS and light sleep.
 
@@ -489,3 +490,61 @@ config BT_CTRL_LE_PING_EN
     help
         If this option is disabled, The Controller will not start the LE authenticated payload timer.
         This option is used for some compatibility problems related to LE ping procedure.
+
+menu "BLE disconnect when instant passed"
+    config BT_CTRL_BLE_LLCP_CONN_UPDATE
+        bool "BLE ACL connection update procedure"
+        default n
+        help
+            If this option is enabled, Controller will terminate the connection
+            when instant passed during connection update procedure.
+
+    config BT_CTRL_BLE_LLCP_CHAN_MAP_UPDATE
+        bool "BLE ACL channel map update procedure"
+        default n
+        help
+            If this option is enabled, Controller will terminate the connection
+            when instant passed in channel map update procedure.
+
+    config BT_CTRL_BLE_LLCP_PHY_UPDATE
+        bool "BLE ACL PHY update procedure"
+        default n
+        help
+            If this option is enabled, Controller will terminate the connection
+            when instant passed in PHY update procedure.
+endmenu
+config BT_CTRL_RUN_IN_FLASH_ONLY
+    bool "Put all BLE Controller code in flash"
+    default n
+    help
+        If this option is enabled, all code for the Bluetooth controller will be moved from ROM and IRAM
+        to flash, saving over 20K bytes of memory. However, it will require more flash resources and the
+        performance of Bluetooth will decrease If this option is enabled, Bluetooth may not work properly
+        during erasing flash. It is recommended to turn on the auto suspend function of flash. After auto
+        suspend is turned on, Bluetooth interrupts can be executed normally during erasing flash, with less
+        impact on Bluetooth performance.
+
+config BT_CTRL_DTM_ENABLE
+    depends on BT_CTRL_RUN_IN_FLASH_ONLY
+    bool "Enable direct test mode feature"
+    default n
+
+config BT_CTRL_BLE_MASTER
+    depends on BT_CTRL_RUN_IN_FLASH_ONLY
+    bool "Enable BLE master role feature"
+    default y
+
+config BT_CTRL_BLE_TEST
+    depends on BT_CTRL_RUN_IN_FLASH_ONLY
+    bool "Enable BLE QA test feature"
+    default n
+
+config BT_CTRL_BLE_SCAN
+    depends on BT_CTRL_RUN_IN_FLASH_ONLY
+    bool "Enable BLE scan feature"
+    default y
+
+config BT_CTRL_BLE_SECURITY_ENABLE
+    depends on BT_CTRL_RUN_IN_FLASH_ONLY && BT_CONTROLLER_ONLY
+    bool "Enable BLE security feature"
+    default y
diff --git a/components/bt/controller/esp32c3/bt.c b/components/bt/controller/esp32c3/bt.c
index 34c6ff9816d..c943fb92fad 100644
--- a/components/bt/controller/esp32c3/bt.c
+++ b/components/bt/controller/esp32c3/bt.c
@@ -499,7 +499,11 @@ static int interrupt_alloc_wrapper(int cpu_id, int source, intr_handler_t handle
 {
     btdm_isr_alloc_t p;
     p.source = source;
+#if CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
+    p.flags = ESP_INTR_FLAG_LEVEL3;
+#else
     p.flags = ESP_INTR_FLAG_LEVEL3 | ESP_INTR_FLAG_IRAM;
+#endif
     p.fn = handler;
     p.arg = arg;
     p.handle = (intr_handle_t *)ret_handle;
@@ -1426,6 +1430,10 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
 
     ESP_LOGI(BT_LOG_TAG, "BT controller compile version [%s]", btdm_controller_get_compile_version());
 
+#if (CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+    ESP_LOGI(BT_LOG_TAG,"Put all controller code in flash");
+#endif
+
     if ((err = btdm_low_power_mode_init(cfg)) != ESP_OK) {
         ESP_LOGE(BT_LOG_TAG, "Low power module initialization failed");
         goto error;
diff --git a/components/bt/controller/esp32c5/bt.c b/components/bt/controller/esp32c5/bt.c
index c0ed4fff553..de235b3fe02 100644
--- a/components/bt/controller/esp32c5/bt.c
+++ b/components/bt/controller/esp32c5/bt.c
@@ -184,7 +184,6 @@ const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG
 static bool s_ble_active = false;
 #ifdef CONFIG_PM_ENABLE
 static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
-#define BTDM_MIN_TIMER_UNCERTAINTY_US      (200)
 #endif // CONFIG_PM_ENABLE
 static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
 
@@ -404,7 +403,7 @@ static void sleep_modem_ble_mac_modem_state_deinit(void)
     }
 }
 
-void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
+void IRAM_ATTR sleep_modem_light_sleep_overhead_set(uint32_t overhead)
 {
     r_esp_ble_set_wakeup_overhead(overhead);
 }
@@ -424,16 +423,19 @@ esp_err_t controller_sleep_init(void)
                                 BLE_RTC_DELAY_US_MODEM_SLEEP);
 #endif /* FREERTOS_USE_TICKLESS_IDLE */
 #endif // CONFIG_BT_LE_SLEEP_ENABLE
-
 #ifdef CONFIG_PM_ENABLE
     rc = esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "bt", &s_pm_lock);
     if (rc != ESP_OK) {
         goto error;
     }
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+#endif // CONFIG_PM_ENABLE
+
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
     /* Create a new regdma link for BLE related register restoration */
     rc = sleep_modem_ble_mac_modem_state_init(0);
-    assert(rc == 0);
+    if (rc != ESP_OK) {
+        goto error;
+    }
     esp_sleep_enable_bt_wakeup();
     ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer");
 
@@ -446,19 +448,21 @@ esp_err_t controller_sleep_init(void)
     sleep_modem_register_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare,
                                                    sleep_modem_mac_bb_power_up_prepare);
 #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
-#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
     return rc;
 
+#ifdef CONFIG_PM_ENABLE
 error:
-
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+#endif // CONFIG_PM_ENABLE
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
     sleep_modem_unregister_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare,
                                                      sleep_modem_mac_bb_power_up_prepare);
 #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
     esp_sleep_disable_bt_wakeup();
     esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
-#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#ifdef CONFIG_PM_ENABLE
     /*lock should release first and then delete*/
     if (s_pm_lock != NULL) {
         esp_pm_lock_delete(s_pm_lock);
@@ -471,7 +475,7 @@ esp_err_t controller_sleep_init(void)
 
 void controller_sleep_deinit(void)
 {
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
     sleep_modem_unregister_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare,
                                                      sleep_modem_mac_bb_power_up_prepare);
diff --git a/components/bt/controller/esp32c6/bt.c b/components/bt/controller/esp32c6/bt.c
index 8bc3992e441..828efa09f6e 100644
--- a/components/bt/controller/esp32c6/bt.c
+++ b/components/bt/controller/esp32c6/bt.c
@@ -388,7 +388,6 @@ void esp_bt_read_ctrl_log_from_flash(bool output)
 static bool s_ble_active = false;
 #ifdef CONFIG_PM_ENABLE
 static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
-#define BTDM_MIN_TIMER_UNCERTAINTY_US      (200)
 #endif // CONFIG_PM_ENABLE
 static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
 
@@ -612,7 +611,7 @@ static void sleep_modem_ble_mac_modem_state_deinit(void)
     }
 }
 
-void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
+void IRAM_ATTR sleep_modem_light_sleep_overhead_set(uint32_t overhead)
 {
     r_esp_ble_set_wakeup_overhead(overhead);
 }
@@ -639,17 +638,20 @@ esp_err_t controller_sleep_init(void)
     if (rc != ESP_OK) {
         goto error;
     }
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
-#if CONFIG_BT_LE_SLEEP_ENABLE && SOC_PM_RETENTION_HAS_CLOCK_BUG && !CONFIG_MAC_BB_PD
+#endif // CONFIG_PM_ENABLE
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
+#if SOC_PM_RETENTION_HAS_CLOCK_BUG && !CONFIG_MAC_BB_PD
 #error "CONFIG_MAC_BB_PD required for BLE light sleep to run properly"
-#endif // CONFIG_BT_LE_SLEEP_ENABLE && SOC_PM_RETENTION_HAS_CLOCK_BUG && !CONFIG_MAC_BB_PD
+#endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && !CONFIG_MAC_BB_PD
     /* Create a new regdma link for BLE related register restoration */
 #if SOC_PM_RETENTION_HAS_CLOCK_BUG
     rc = sleep_modem_ble_mac_modem_state_init(1);
 #else
     rc = sleep_modem_ble_mac_modem_state_init(0);
 #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
-    assert(rc == 0);
+    if (rc != ESP_OK) {
+        goto error;
+    }
     esp_sleep_enable_bt_wakeup();
     ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer");
 
@@ -662,19 +664,21 @@ esp_err_t controller_sleep_init(void)
     sleep_modem_register_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare,
                                                    sleep_modem_mac_bb_power_up_prepare);
 #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
-#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
     return rc;
 
+#ifdef CONFIG_PM_ENABLE
 error:
-
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+#endif // CONFIG_PM_ENABLE
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
     sleep_modem_unregister_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare,
                                                      sleep_modem_mac_bb_power_up_prepare);
 #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
     esp_sleep_disable_bt_wakeup();
     esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
-#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#ifdef CONFIG_PM_ENABLE
     /*lock should release first and then delete*/
     if (s_pm_lock != NULL) {
         esp_pm_lock_delete(s_pm_lock);
@@ -687,7 +691,7 @@ esp_err_t controller_sleep_init(void)
 
 void controller_sleep_deinit(void)
 {
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
 #if SOC_PM_RETENTION_HAS_CLOCK_BUG && CONFIG_MAC_BB_PD
     sleep_modem_unregister_mac_bb_module_prepare_callback(sleep_modem_mac_bb_power_down_prepare,
                                                      sleep_modem_mac_bb_power_up_prepare);
@@ -696,7 +700,7 @@ void controller_sleep_deinit(void)
     esp_sleep_disable_bt_wakeup();
     sleep_modem_ble_mac_modem_state_deinit();
     esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
-#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
 #ifdef CONFIG_PM_ENABLE
     /* lock should be released first */
     esp_pm_lock_delete(s_pm_lock);
diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c
index 9a46b2ca6c2..8830a2018e7 100644
--- a/components/bt/controller/esp32h2/bt.c
+++ b/components/bt/controller/esp32h2/bt.c
@@ -385,7 +385,6 @@ void esp_bt_read_ctrl_log_from_flash(bool output)
 static bool s_ble_active = false;
 #ifdef CONFIG_PM_ENABLE
 static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
-#define BTDM_MIN_TIMER_UNCERTAINTY_US      (200)
 #endif // CONFIG_PM_ENABLE
 static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
 
@@ -604,7 +603,7 @@ static void sleep_modem_ble_mac_modem_state_deinit(void)
     }
 }
 
-void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
+void IRAM_ATTR sleep_modem_light_sleep_overhead_set(uint32_t overhead)
 {
     r_esp_ble_set_wakeup_overhead(overhead);
 }
@@ -631,13 +630,17 @@ esp_err_t controller_sleep_init(void)
     if (rc != ESP_OK) {
         goto error;
     }
-
     rc = esp_deep_sleep_register_hook(&r_esp_ble_stop_wakeup_timing);
-    assert(rc == 0);
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+    if (rc != ESP_OK) {
+        goto error;
+    }
+#endif //CONFIG_PM_ENABLE
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
     /* Create a new regdma link for BLE related register restoration */
     rc = sleep_modem_ble_mac_modem_state_init(0);
-    assert(rc == 0);
+    if (rc != ESP_OK) {
+        goto error;
+    }
     esp_sleep_enable_bt_wakeup();
     ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer");
 
@@ -645,15 +648,17 @@ esp_err_t controller_sleep_init(void)
     if (rc != ESP_OK) {
         goto error;
     }
-#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
     return rc;
 
+#ifdef CONFIG_PM_ENABLE
 error:
-
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+#endif // CONFIG_PM_ENABLE
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
     esp_sleep_disable_bt_wakeup();
     esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
-#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#ifdef CONFIG_PM_ENABLE
     esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing);
     /*lock should release first and then delete*/
     if (s_pm_lock != NULL) {
@@ -667,12 +672,12 @@ esp_err_t controller_sleep_init(void)
 
 void controller_sleep_deinit(void)
 {
-#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+#if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
     r_ble_rtc_wake_up_state_clr();
     esp_sleep_disable_bt_wakeup();
     sleep_modem_ble_mac_modem_state_deinit();
     esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
-#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
+#endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
 #ifdef CONFIG_PM_ENABLE
     esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing);
     /* lock should be released first */
diff --git a/components/bt/controller/lib_esp32 b/components/bt/controller/lib_esp32
index 22a4e62193e..4f9869a760c 160000
--- a/components/bt/controller/lib_esp32
+++ b/components/bt/controller/lib_esp32
@@ -1 +1 @@
-Subproject commit 22a4e62193eb8bf9c747c9ec826fece57b40c042
+Subproject commit 4f9869a760c7f6982d2d4d6b56ef46c1b2488611
diff --git a/components/bt/controller/lib_esp32c3_family b/components/bt/controller/lib_esp32c3_family
index 061e70c3195..6470c01165c 160000
--- a/components/bt/controller/lib_esp32c3_family
+++ b/components/bt/controller/lib_esp32c3_family
@@ -1 +1 @@
-Subproject commit 061e70c319576bf28b5695f5478dbe01ad18b18d
+Subproject commit 6470c01165cf4edeed5d826ce4082a90deb92efd
diff --git a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib
index 69f16a7a63a..b86a06d38cc 160000
--- a/components/bt/controller/lib_esp32c6/esp32c6-bt-lib
+++ b/components/bt/controller/lib_esp32c6/esp32c6-bt-lib
@@ -1 +1 @@
-Subproject commit 69f16a7a63a08032d81ee86649ca0e6f5d343f40
+Subproject commit b86a06d38cc3de4660b67d992259f727ba590296
diff --git a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib
index 50f567fff50..90f1ef76ab9 160000
--- a/components/bt/controller/lib_esp32h2/esp32h2-bt-lib
+++ b/components/bt/controller/lib_esp32h2/esp32h2-bt-lib
@@ -1 +1 @@
-Subproject commit 50f567fff506f63b4d06ebea80d0405fe9e39568
+Subproject commit 90f1ef76ab9021b123e3037e9df782549f386e30
diff --git a/components/bt/esp_ble_mesh/Kconfig.in b/components/bt/esp_ble_mesh/Kconfig.in
index 17d23ba94ec..d9c7fb85212 100644
--- a/components/bt/esp_ble_mesh/Kconfig.in
+++ b/components/bt/esp_ble_mesh/Kconfig.in
@@ -6,6 +6,12 @@ if BLE_MESH
         help
             It is a temporary solution and needs further modifications.
 
+    config BLE_MESH_V11_SUPPORT
+        bool "Support ESP BLE Mesh v1.1 features (Preview)"
+        default y
+        help
+            Support BLE Mesh v1.1 features
+
     config BLE_MESH_RANDOM_ADV_INTERVAL
         bool "Support using random adv interval for mesh packets"
         select BT_BLE_HIGH_DUTY_ADV_INTERVAL if BT_BLUEDROID_ENABLED
@@ -15,13 +21,25 @@ if BLE_MESH
             for mesh packets. And this could help avoid collision of
             advertising packets.
 
+    menuconfig BLE_MESH_USE_BLE_50
+        bool "Support using BLE 5.0 APIs for BLE Mesh"
+        depends on BLE_MESH_EXPERIMENTAL
+        depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
+        select BT_NIMBLE_50_FEATURE_SUPPORT if BT_NIMBLE_ENABLED
+        select BT_NIMBLE_EXT_ADV if BT_NIMBLE_ENABLED
+        select BT_BLE_50_FEATURES_SUPPORTED if BT_BLUEDROID_ENABLED
+        select BT_LE_50_FEATURE_SUPPORT if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
+        default n
+        help
+            This option to enable BLE Mesh using some BLE 5.0 APIs.
+
     config BLE_MESH_USE_DUPLICATE_SCAN
         bool "Support Duplicate Scan in BLE Mesh"
         select BTDM_BLE_SCAN_DUPL if IDF_TARGET_ESP32
         select BTDM_BLE_MESH_SCAN_DUPL_EN if IDF_TARGET_ESP32
         select BT_CTRL_BLE_SCAN_DUPL if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
         select BT_CTRL_BLE_MESH_SCAN_DUPL_EN if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
-        select BT_LE_SCAN_DUPL if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
+        select BT_LE_SCAN_DUPL if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32C5
         select BT_NIMBLE_VS_SUPPORT if BT_NIMBLE_ENABLED
         default y
         help
@@ -32,6 +50,7 @@ if BLE_MESH
 
     config BLE_MESH_ACTIVE_SCAN
         bool "Support Active Scan in BLE Mesh"
+        depends on BLE_MESH_V11_SUPPORT
         help
             Enable this option to allow using BLE Active Scan for BLE Mesh.
 
@@ -281,6 +300,7 @@ if BLE_MESH
     config BLE_MESH_PROV_EPA
         bool "BLE Mesh enhanced provisioning authentication"
         depends on BLE_MESH_PROV
+        depends on BLE_MESH_V11_SUPPORT
         default y
         help
             Enable this option to support BLE Mesh enhanced provisioning authentication
@@ -290,6 +310,7 @@ if BLE_MESH
     config BLE_MESH_CERT_BASED_PROV
         bool "Support Certificate-based provisioning"
         depends on BLE_MESH_PROV
+        depends on BLE_MESH_V11_SUPPORT
         default n
         help
             Enable this option to support BLE Mesh Certificate-Based Provisioning.
@@ -390,6 +411,7 @@ if BLE_MESH
     config BLE_MESH_PROXY_SOLIC_PDU_RX
         bool "Support receiving Proxy Solicitation PDU"
         depends on BLE_MESH_GATT_PROXY_SERVER
+        depends on BLE_MESH_V11_SUPPORT
         help
             Enable this option to support receiving Proxy Solicitation PDU.
 
@@ -417,6 +439,7 @@ if BLE_MESH
     config BLE_MESH_PROXY_SOLIC_PDU_TX
         bool "Support sending Proxy Solicitation PDU"
         depends on BLE_MESH_GATT_PROXY_CLIENT
+        depends on BLE_MESH_V11_SUPPORT
         help
             Enable this option to support sending Proxy Solicitation PDU.
 
@@ -703,6 +726,7 @@ if BLE_MESH
             to perform the IV index recovery procedure.
 
     config BLE_MESH_SAR_ENHANCEMENT
+        depends on BLE_MESH_V11_SUPPORT
         bool "Segmentation and reassembly enhancement"
         default n
         help
@@ -1102,253 +1126,257 @@ if BLE_MESH
             help
                 Enable support for Health Server model.
 
-        config BLE_MESH_BRC_CLI
-            bool "Bridge Configuration Client model"
-            help
-                Enable support for Bridge Configuration Client model.
-
-        config BLE_MESH_BRC_SRV
-            bool "Bridge Configuration Server model"
-            default n
-            help
-                Enable support for Bridge Configuration Server model.
+        if BLE_MESH_V11_SUPPORT
 
-        if BLE_MESH_BRC_SRV
-
-            config BLE_MESH_MAX_BRIDGING_TABLE_ENTRY_COUNT
-                int "Maximum number of Bridging Table entries"
-                range 16 65535
-                default 16
+            config BLE_MESH_BRC_CLI
+                bool "Bridge Configuration Client model"
                 help
-                    Maximum number of Bridging Table entries that the Bridge Configuration Server can support.
+                    Enable support for Bridge Configuration Client model.
 
-            config BLE_MESH_BRIDGE_CRPL
-                int "Maximum capacity of bridge replay protection list"
-                default 5
-                range 1 255
+            config BLE_MESH_BRC_SRV
+                bool "Bridge Configuration Server model"
+                default n
                 help
-                    This option specifies the maximum capacity of the bridge replay
-                    protection list. The bridge replay protection list is used to
-                    prevent a bridged subnet from replay attack, which will store the
-                    source address and sequence number of the received bridge messages.
+                    Enable support for Bridge Configuration Server model.
 
-        endif #BLE_MESH_BRC_SRV
+            if BLE_MESH_BRC_SRV
 
-        config BLE_MESH_PRB_CLI
-            bool "Mesh Private Beacon Client model"
-            help
-                Enable support for Mesh Private Beacon Client model.
+                config BLE_MESH_MAX_BRIDGING_TABLE_ENTRY_COUNT
+                    int "Maximum number of Bridging Table entries"
+                    range 16 65535
+                    default 16
+                    help
+                        Maximum number of Bridging Table entries that the Bridge Configuration Server can support.
 
-        config BLE_MESH_PRB_SRV
-            bool "Mesh Private Beacon Server model"
-            help
-                Enable support for Mesh Private Beacon Server model.
+                config BLE_MESH_BRIDGE_CRPL
+                    int "Maximum capacity of bridge replay protection list"
+                    default 5
+                    range 1 255
+                    help
+                        This option specifies the maximum capacity of the bridge replay
+                        protection list. The bridge replay protection list is used to
+                        prevent a bridged subnet from replay attack, which will store the
+                        source address and sequence number of the received bridge messages.
 
-        config BLE_MESH_ODP_CLI
-            bool "On-Demand Private Proxy Client model"
-            help
-                Enable support for On-Demand Private Proxy Client model.
+            endif #BLE_MESH_BRC_SRV
 
-        config BLE_MESH_ODP_SRV
-            bool "On-Demand Private Proxy Server model"
-            depends on BLE_MESH_PROXY_SOLIC_PDU_RX
-            select BLE_MESH_SRPL_SRV
-            help
-                Enable support for On-Demand Private Proxy Server model.
+            config BLE_MESH_PRB_CLI
+                bool "Mesh Private Beacon Client model"
+                help
+                    Enable support for Mesh Private Beacon Client model.
 
-        config BLE_MESH_SRPL_CLI
-            bool "Solicitation PDU RPL Configuration Client model"
-            help
-                Enable support for Solicitation PDU RPL Configuration Client model.
+            config BLE_MESH_PRB_SRV
+                bool "Mesh Private Beacon Server model"
+                help
+                    Enable support for Mesh Private Beacon Server model.
 
-        config BLE_MESH_SRPL_SRV
-            bool "Solicitation PDU RPL Configuration Server model"
-            depends on BLE_MESH_PROXY_SOLIC_PDU_RX
-            help
-                Enable support for Solicitation PDU RPL Configuration Server model.
-                Note:
-                This option depends on the functionality of receiving Solicitation
-                PDU. If the device doesn't support receiving Solicitation PDU, then
-                there is no need to enable this server model.
+            config BLE_MESH_ODP_CLI
+                bool "On-Demand Private Proxy Client model"
+                help
+                    Enable support for On-Demand Private Proxy Client model.
 
-        config BLE_MESH_AGG_CLI
-            bool "Opcodes Aggregator Client model"
-            help
-                Enable support for Opcodes Aggregator Client model.
+            config BLE_MESH_ODP_SRV
+                bool "On-Demand Private Proxy Server model"
+                depends on BLE_MESH_PROXY_SOLIC_PDU_RX
+                select BLE_MESH_SRPL_SRV
+                help
+                    Enable support for On-Demand Private Proxy Server model.
 
-        config BLE_MESH_AGG_SRV
-            bool "Opcodes Aggregator Server model"
-            help
-                Enable support for Opcodes Aggregator Server model.
+            config BLE_MESH_SRPL_CLI
+                bool "Solicitation PDU RPL Configuration Client model"
+                help
+                    Enable support for Solicitation PDU RPL Configuration Client model.
 
-        config BLE_MESH_SAR_CLI
-            bool "SAR Configuration Client model"
-            help
-                Enable support for SAR Configuration Client model.
+            config BLE_MESH_SRPL_SRV
+                bool "Solicitation PDU RPL Configuration Server model"
+                depends on BLE_MESH_PROXY_SOLIC_PDU_RX
+                help
+                    Enable support for Solicitation PDU RPL Configuration Server model.
+                    Note:
+                    This option depends on the functionality of receiving Solicitation
+                    PDU. If the device doesn't support receiving Solicitation PDU, then
+                    there is no need to enable this server model.
+
+            config BLE_MESH_AGG_CLI
+                bool "Opcodes Aggregator Client model"
+                help
+                    Enable support for Opcodes Aggregator Client model.
 
-        config BLE_MESH_SAR_SRV
-            bool "SAR Configuration Server model"
-            help
-                Enable support for SAR Configuration Server model.
+            config BLE_MESH_AGG_SRV
+                bool "Opcodes Aggregator Server model"
+                help
+                    Enable support for Opcodes Aggregator Server model.
 
-        config BLE_MESH_COMP_DATA_1
-            bool "Support Composition Data Page 1"
-            help
-                Composition Data Page 1 contains information about the relationships
-                among models.
-                Each model either can be a root model or can extend other models.
+            config BLE_MESH_SAR_CLI
+                bool "SAR Configuration Client model"
+                help
+                    Enable support for SAR Configuration Client model.
 
-        config BLE_MESH_COMP_DATA_128
-            bool "Support Composition Data Page 128"
-            help
-                Composition Data Page 128 is used to indicate the structure of
-                elements, features, and models of a node after the successful
-                execution of the Node Address Refresh procedure or the Node
-                Composition Refresh procedure, or after the execution of the
-                Node Removal procedure followed by the provisioning process.
-                Composition Data Page 128 shall be present if the node supports
-                the Remote Provisioning Server model; otherwise it is optional.
+            config BLE_MESH_SAR_SRV
+                bool "SAR Configuration Server model"
+                help
+                    Enable support for SAR Configuration Server model.
 
-        config BLE_MESH_MODELS_METADATA_0
-            bool "Support Models Metadata Page 0"
-            help
-                The Models Metadata state contains metadata of a node’s models.
-                The Models Metadata state is composed of a number of pages of
-                information.
-                Models Metadata Page 0 shall be present if the node supports
-                the Large Composition Data Server model.
+            config BLE_MESH_COMP_DATA_1
+                bool "Support Composition Data Page 1"
+                help
+                    Composition Data Page 1 contains information about the relationships
+                    among models.
+                    Each model either can be a root model or can extend other models.
 
-        config BLE_MESH_MODELS_METADATA_128
-            bool "Support Models Metadata Page 128"
-            depends on BLE_MESH_MODELS_METADATA_0
-            help
-                The Models Metadata state contains metadata of a node’s models.
-                The Models Metadata state is composed of a number of pages of
-                information.
-                Models Metadata Page 128 contains metadata for the node’s models
-                after the successful execution of the Node Address Refresh
-                procedure or the Node Composition Refresh procedure, or after
-                the execution of the Node Removal procedure followed by the
-                provisioning process.
-                Models Metadata Page 128 shall be present if the node supports
-                the Remote Provisioning Server model and the node supports the
-                Large Composition Data Server model.
+            config BLE_MESH_COMP_DATA_128
+                bool "Support Composition Data Page 128"
+                help
+                    Composition Data Page 128 is used to indicate the structure of
+                    elements, features, and models of a node after the successful
+                    execution of the Node Address Refresh procedure or the Node
+                    Composition Refresh procedure, or after the execution of the
+                    Node Removal procedure followed by the provisioning process.
+                    Composition Data Page 128 shall be present if the node supports
+                    the Remote Provisioning Server model; otherwise it is optional.
+
+            config BLE_MESH_MODELS_METADATA_0
+                bool "Support Models Metadata Page 0"
+                help
+                    The Models Metadata state contains metadata of a node’s models.
+                    The Models Metadata state is composed of a number of pages of
+                    information.
+                    Models Metadata Page 0 shall be present if the node supports
+                    the Large Composition Data Server model.
+
+            config BLE_MESH_MODELS_METADATA_128
+                bool "Support Models Metadata Page 128"
+                depends on BLE_MESH_MODELS_METADATA_0
+                help
+                    The Models Metadata state contains metadata of a node’s models.
+                    The Models Metadata state is composed of a number of pages of
+                    information.
+                    Models Metadata Page 128 contains metadata for the node’s models
+                    after the successful execution of the Node Address Refresh
+                    procedure or the Node Composition Refresh procedure, or after
+                    the execution of the Node Removal procedure followed by the
+                    provisioning process.
+                    Models Metadata Page 128 shall be present if the node supports
+                    the Remote Provisioning Server model and the node supports the
+                    Large Composition Data Server model.
+
+            config BLE_MESH_LCD_CLI
+                bool "Large Composition Data Client model"
+                help
+                    Enable support for Large Composition Data Client model.
 
-        config BLE_MESH_LCD_CLI
-            bool "Large Composition Data Client model"
-            help
-                Enable support for Large Composition Data Client model.
+            config BLE_MESH_LCD_SRV
+                bool "Large Composition Data Server model"
+                select BLE_MESH_MODELS_METADATA_0
+                help
+                    Enable support for Large Composition Data Server model.
 
-        config BLE_MESH_LCD_SRV
-            bool "Large Composition Data Server model"
-            select BLE_MESH_MODELS_METADATA_0
-            help
-                Enable support for Large Composition Data Server model.
+            config BLE_MESH_RPR_CLI
+                bool "Remote Provisioning Client model"
+                depends on BLE_MESH_PROVISIONER
+                select BLE_MESH_PROV
+                help
+                    Enable support for Remote Provisioning Client model
 
-        config BLE_MESH_RPR_CLI
-            bool "Remote Provisioning Client model"
-            depends on BLE_MESH_PROVISIONER
-            select BLE_MESH_PROV
-            help
-                Enable support for Remote Provisioning Client model
+            if BLE_MESH_RPR_CLI
 
-        if BLE_MESH_RPR_CLI
+                config BLE_MESH_RPR_CLI_PROV_SAME_TIME
+                    int "Maximum number of PB-Remote running at the same time by Provisioner"
+                    range 1 5
+                    default 2
+                    help
+                        This option specifies how many devices can be provisioned at the same time
+                        using PB-REMOTE. For example, if the value is 2, it means a Provisioner can
+                        provision two unprovisioned devices with PB-REMOTE at the same time.
 
-            config BLE_MESH_RPR_CLI_PROV_SAME_TIME
-                int "Maximum number of PB-Remote running at the same time by Provisioner"
-                range 1 5
-                default 2
+            endif # BLE_MESH_RPR_CLI
+
+            config BLE_MESH_RPR_SRV
+                bool "Remote Provisioning Server model"
+                depends on BLE_MESH_NODE
+                select BLE_MESH_PB_ADV
                 help
-                    This option specifies how many devices can be provisioned at the same time
-                    using PB-REMOTE. For example, if the value is 2, it means a Provisioner can
-                    provision two unprovisioned devices with PB-REMOTE at the same time.
+                    Enable support for Remote Provisioning Server model
 
-        endif # BLE_MESH_RPR_CLI
+            if BLE_MESH_RPR_SRV
 
-        config BLE_MESH_RPR_SRV
-            bool "Remote Provisioning Server model"
-            depends on BLE_MESH_NODE
-            select BLE_MESH_PB_ADV
-            help
-                Enable support for Remote Provisioning Server model
+                config BLE_MESH_RPR_SRV_MAX_SCANNED_ITEMS
+                    int "Maximum number of device information can be scanned"
+                    range 4 255
+                    default 10
+                    help
+                        This option specifies how many device information can a Remote
+                        Provisioning Server store each time while scanning.
 
-        if BLE_MESH_RPR_SRV
+                config BLE_MESH_RPR_SRV_ACTIVE_SCAN
+                    bool "Support Active Scan for remote provisioning"
+                    select BLE_MESH_ACTIVE_SCAN
+                    help
+                        Enable this option to support Active Scan for remote provisioning.
 
-            config BLE_MESH_RPR_SRV_MAX_SCANNED_ITEMS
-                int "Maximum number of device information can be scanned"
-                range 4 255
-                default 10
-                help
-                    This option specifies how many device information can a Remote
-                    Provisioning Server store each time while scanning.
+                config BLE_MESH_RPR_SRV_MAX_EXT_SCAN
+                    int "Maximum number of extended scan procedures"
+                    range 1 10
+                    default 1
+                    help
+                        This option specifies how many extended scan procedures can be
+                        started by the Remote Provisioning Server.
 
-            config BLE_MESH_RPR_SRV_ACTIVE_SCAN
-                bool "Support Active Scan for remote provisioning"
-                select BLE_MESH_ACTIVE_SCAN
-                help
-                    Enable this option to support Active Scan for remote provisioning.
+            endif # BLE_MESH_RPR_SRV
 
-            config BLE_MESH_RPR_SRV_MAX_EXT_SCAN
-                int "Maximum number of extended scan procedures"
-                range 1 10
-                default 1
+            config BLE_MESH_DF_CLI
+                bool "Directed Forwarding Configuration Client model"
                 help
-                    This option specifies how many extended scan procedures can be
-                    started by the Remote Provisioning Server.
+                    Enable support for Directed Forwarding Configuration Client model.
 
-        endif # BLE_MESH_RPR_SRV
+            config BLE_MESH_DF_SRV
+                bool "Directed Forwarding Configuration Server model"
+                help
+                    Enable support for Directed Forwarding Configuration Server model.
 
-        config BLE_MESH_DF_CLI
-            bool "Directed Forwarding Configuration Client model"
-            help
-                Enable support for Directed Forwarding Configuration Client model.
+            if BLE_MESH_DF_SRV
 
-        config BLE_MESH_DF_SRV
-            bool "Directed Forwarding Configuration Server model"
-            help
-                Enable support for Directed Forwarding Configuration Server model.
+                config BLE_MESH_MAX_DISC_TABLE_ENTRY_COUNT
+                    int "Maximum number of discovery table entries in a given subnet"
+                    range 2 255
+                    default 2
+                    help
+                        Maximum number of Discovery Table entries supported by the node in a given subnet.
 
-        if BLE_MESH_DF_SRV
+                config BLE_MESH_MAX_FORWARD_TABLE_ENTRY_COUNT
+                    int "Maximum number of forward table entries in a given subnet"
+                    range 2 64
+                    default 2
+                    help
+                        Maximum number of Forward Table entries supported by the node in a given subnet.
 
-            config BLE_MESH_MAX_DISC_TABLE_ENTRY_COUNT
-                int "Maximum number of discovery table entries in a given subnet"
-                range 2 255
-                default 2
-                help
-                    Maximum number of Discovery Table entries supported by the node in a given subnet.
+                config BLE_MESH_MAX_DEPS_NODES_PER_PATH
+                    int "Maximum number of dependent nodes per path"
+                    range 2 64
+                    default 2
+                    help
+                        Maximum size of dependent nodes list supported by each forward table entry.
 
-            config BLE_MESH_MAX_FORWARD_TABLE_ENTRY_COUNT
-                int "Maximum number of forward table entries in a given subnet"
-                range 2 64
-                default 2
-                help
-                    Maximum number of Forward Table entries supported by the node in a given subnet.
+                config BLE_MESH_PATH_MONITOR_TEST
+                    bool "Enable Path Monitoring test mode"
+                    default n
+                    help
+                        The option only removes the Path Use timer; all other behavior of the
+                        device is not changed.
+                        If Path Monitoring test mode is going to be used, this option should
+                        be enabled.
 
-            config BLE_MESH_MAX_DEPS_NODES_PER_PATH
-                int "Maximum number of dependent nodes per path"
-                range 2 64
-                default 2
-                help
-                    Maximum size of dependent nodes list supported by each forward table entry.
+                if BLE_MESH_GATT_PROXY_SERVER
+                    config BLE_MESH_SUPPORT_DIRECTED_PROXY
+                        bool "Enable Directed Proxy functionality"
+                        default y
+                        help
+                            Support Directed Proxy functionality.
+                endif
 
-            config BLE_MESH_PATH_MONITOR_TEST
-                bool "Enable Path Monitoring test mode"
-                default n
-                help
-                    The option only removes the Path Use timer; all other behavior of the
-                    device is not changed.
-                    If Path Monitoring test mode is going to be used, this option should
-                    be enabled.
-
-            if BLE_MESH_GATT_PROXY_SERVER
-                config BLE_MESH_SUPPORT_DIRECTED_PROXY
-                    bool "Enable Directed Proxy functionality"
-                    default y
-                    help
-                        Support Directed Proxy functionality.
-            endif
+            endif # BLE_MESH_DF_SRV
 
-        endif # BLE_MESH_DF_SRV
+        endif # BLE_MESH_V11_SUPPORT
 
     endmenu #Support for BLE Mesh Foundation models
 
@@ -1465,6 +1493,7 @@ if BLE_MESH
 
         config BLE_MESH_MBT_CLI
             bool "BLOB Transfer Client model"
+            depends on BLE_MESH_V11_SUPPORT
             default n
             help
                 Enable support for BLOB Transfer Client model.
@@ -1483,6 +1512,7 @@ if BLE_MESH
 
         config BLE_MESH_MBT_SRV
             bool "BLOB Transfer Server model"
+            depends on BLE_MESH_V11_SUPPORT
             default n
             help
                 Enable support for BLOB Transfer Server model.
@@ -1628,5 +1658,6 @@ if BLE_MESH
             Make BLE Mesh Experimental features visible.
             Experimental features list:
             - CONFIG_BLE_MESH_NOT_RELAY_REPLAY_MSG
+            - CONFIG_BLE_MESH_USE_BLE_50
 
 endif # BLE_MESH
diff --git a/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_ble_api.c b/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_ble_api.c
index 559528e8adf..fcba1f4b51a 100644
--- a/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_ble_api.c
+++ b/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_ble_api.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,14 +12,14 @@
 #include "btc_ble_mesh_ble.h"
 #include "esp_ble_mesh_ble_api.h"
 
-#if CONFIG_BLE_MESH_BLE_COEX_SUPPORT
+#if (CONFIG_BLE_MESH_BLE_COEX_SUPPORT || CONFIG_BLE_MESH_USE_BLE_50)
 esp_err_t esp_ble_mesh_register_ble_callback(esp_ble_mesh_ble_cb_t callback)
 {
     ESP_BLE_HOST_STATUS_CHECK(ESP_BLE_HOST_STATUS_ENABLED);
 
     return (btc_profile_cb_set(BTC_PID_BLE_MESH_BLE_COEX, callback) == 0 ? ESP_OK : ESP_FAIL);
 }
-#endif /* CONFIG_BLE_MESH_BLE_COEX_SUPPORT */
+#endif /* (CONFIG_BLE_MESH_BLE_COEX_SUPPORT || CONFIG_BLE_MESH_USE_BLE_50) */
 
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
 esp_err_t esp_ble_mesh_start_ble_advertising(const esp_ble_mesh_ble_adv_param_t *param,
@@ -100,3 +100,23 @@ esp_err_t esp_ble_mesh_stop_ble_scanning(void)
             == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
 }
 #endif /* CONFIG_BLE_MESH_SUPPORT_BLE_SCAN */
+
+esp_err_t esp_ble_mesh_scan_params_update(esp_ble_mesh_scan_param_t *scan_param)
+{
+    btc_ble_mesh_ble_args_t arg = {0};
+    btc_msg_t msg = {0};
+
+    if (!scan_param) {
+        return ESP_FAIL;
+    }
+
+    msg.sig = BTC_SIG_API_CALL;
+    msg.pid = BTC_PID_BLE_MESH_BLE_COEX;
+    msg.act = BTC_BLE_MESH_ACT_UPDATE_SCAN_PARAMS;
+
+    arg.scan_params.scan_interval = scan_param->scan_interval;
+    arg.scan_params.uncoded_scan_window = scan_param->uncoded_scan_window;
+
+    return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_mesh_ble_args_t), NULL, NULL)
+            == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
+}
diff --git a/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_common_api.c b/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_common_api.c
index 82128786085..eaa1868133f 100644
--- a/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_common_api.c
+++ b/components/bt/esp_ble_mesh/api/core/esp_ble_mesh_common_api.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_ble_api.h b/components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_ble_api.h
index 6818ba18aec..83d7e627606 100644
--- a/components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_ble_api.h
+++ b/components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_ble_api.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,10 @@
 
 #include "esp_ble_mesh_defs.h"
 
+#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BT_NIMBLE_ENABLED
+#include "host/ble_gap.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -20,9 +24,38 @@ typedef enum {
     ESP_BLE_MESH_START_BLE_SCANNING_COMP_EVT,    /*!< Start BLE scanning completion event */
     ESP_BLE_MESH_STOP_BLE_SCANNING_COMP_EVT,     /*!< Stop BLE scanning completion event */
     ESP_BLE_MESH_SCAN_BLE_ADVERTISING_PKT_EVT,   /*!< Scanning BLE advertising packets event */
+    ESP_BLE_MESH_SCAN_PARAMS_UPDATE_COMP_EVT,    /*!< Scan parameters update completion event */
+#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BT_NIMBLE_ENABLED
+    ESP_BLE_MESH_NIMBLE_GAP_EVENT_EVT,           /*!< NIMBLE GAP event */
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BT_NIMBLE_ENABLED */
     ESP_BLE_MESH_BLE_EVT_MAX,
 } esp_ble_mesh_ble_cb_event_t;
 
+/** Context of BLE advertising report. */
+typedef struct {
+    uint8_t   addr[6];                                /*!< Device address */
+    uint8_t   addr_type;                              /*!< Device address type */
+#if CONFIG_BLE_MESH_USE_BLE_50
+    uint8_t   adv_type __attribute__((deprecated("`event_type` should be used to determine the advertising type")));   /*!< advertising type  */
+#else
+    uint8_t   adv_type;                               /*!< Advertising type  */
+#endif
+    uint8_t   *data;                                  /*!< Advertising data */
+    uint16_t  length;                                 /*!< Advertising data length */
+    int8_t    rssi;                                   /*!< RSSI of the advertising packet */
+#if CONFIG_BLE_MESH_USE_BLE_50
+    uint8_t   event_type;                             /*!< Extended advertising event type */
+    uint8_t   primary_phy;                            /*!< Extended advertising primary PHY */
+    uint8_t   secondary_phy;                          /*!< Extended advertising secondary PHY */
+    uint8_t   sid;                                    /*!< Extended advertising set ID */
+    uint8_t   tx_power;                               /*!< Extended advertising TX power */
+    uint8_t   dir_addr_type;                          /*!< Direct address type */
+    uint8_t   dir_addr[6];                            /*!< Direct address */
+    uint8_t   data_status;                            /*!< Data type */
+    uint16_t  per_adv_interval;                       /*!< Periodic advertising interval */
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+} esp_ble_mesh_ble_adv_rpt_t;
+
 /** BLE operation callback parameters */
 typedef union {
     /**
@@ -52,16 +85,24 @@ typedef union {
         int err_code;     /*!< Indicate the result of stopping BLE scanning */
     } stop_ble_scan_comp; /*!< Event parameters of ESP_BLE_MESH_STOP_BLE_SCANNING_COMP_EVT */
     /**
-     * @brief ESP_BLE_MESH_SCAN_BLE_ADVERTISING_PKT_EVT
+     * @brief Event parameters of ESP_BLE_MESH_SCAN_BLE_ADVERTISING_PKT_EVT
      */
-    struct {
-        uint8_t  addr[6];   /*!< Device address */
-        uint8_t  addr_type; /*!< Device address type */
-        uint8_t  adv_type;  /*!< Advertising data type */
-        uint8_t *data;      /*!< Advertising data */
-        uint16_t length;    /*!< Advertising data length */
-        int8_t   rssi;      /*!< RSSI of the advertising packet */
-    } scan_ble_adv_pkt;     /*!< Event parameters of ESP_BLE_MESH_SCAN_BLE_ADVERTISING_PKT_EVT */
+    esp_ble_mesh_ble_adv_rpt_t scan_ble_adv_pkt;
+    /**
+     * @brief Event parameter of ESP_BLE_MESH_SCAN_PARAMS_UPDATE_COMP_EVT
+     */
+    struct ble_mesh_scan_params_update_comp_param {
+        int err_code;                           /*!< Indicates the result of updating scan parameters */
+    } scan_params_update_comp;                  /*!< Event parameter of ESP_BLE_MESH_SCAN_PARAMS_UPDATE_COMP_EVT */
+#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BT_NIMBLE_ENABLED
+    /**
+     * @brief Event parameters of ESP_BLE_MESH_NIMBLE_GAP_EVENT_EVT
+     */
+    struct ble_mesh_nimble_gap_event_evt_param {
+        struct ble_gap_event event;             /*!< GAP event parameters for NimBLE Host */
+        void *arg;                              /*!< User parameters */
+    } nimble_gap_evt;                           /*!< Event parameters of ESP_BLE_MESH_NIMBLE_GAP_EVENT_EVT */
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BT_NIMBLE_ENABLED */
 } esp_ble_mesh_ble_cb_param_t;
 
 /**
@@ -175,6 +216,33 @@ esp_err_t esp_ble_mesh_start_ble_scanning(esp_ble_mesh_ble_scan_param_t *param);
  */
 esp_err_t esp_ble_mesh_stop_ble_scanning(void);
 
+/**
+ * @brief           Update BLE Mesh scan parameters.
+ *
+ * @note
+ *                  1. This function shall be used after ESP BLE Mesh is initialized!
+ *                    Parameters `scan_interval` and `uncoded_scan_window` must both
+ *                    be multiples of 8.
+ *
+ *                  2. If the config BLE_MESH_USE_BLE_50 is enabled, within the scan_interval:
+ *                     - If uncoded_scan_window is not zero, the scan_interval is divided into
+ *                       two parts:
+ *                          - uncoded_scan_window: Used for performing uncoded scanning.
+ *                          - (scan_interval - uncoded_scan_window): The remaining time is
+ *                             used for coded scanning (coded_scan).
+ *                     - If uncoded_scan_window is set to 0, it means the entire scan_interval
+ *                      is used for coded scanning.
+ *                     - If uncoded_scan_window is equal to scan_interval, it means the entire
+ *                      scan_interval is used for uncoded scanning.
+ *
+ * @param[in]      scan_param: Scan parameters
+ *
+ * @return
+ *                 - ESP_OK: Success
+ *                 - ESP_FAIL: Invalid parameters or unable transfer this command to the stack
+*/
+esp_err_t esp_ble_mesh_scan_params_update(esp_ble_mesh_scan_param_t *scan_param);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/bt/esp_ble_mesh/api/esp_ble_mesh_defs.h b/components/bt/esp_ble_mesh/api/esp_ble_mesh_defs.h
index efbf2df5b79..188d6db22de 100644
--- a/components/bt/esp_ble_mesh/api/esp_ble_mesh_defs.h
+++ b/components/bt/esp_ble_mesh/api/esp_ble_mesh_defs.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -415,6 +415,29 @@ typedef struct {
     bool erase_flash;   /*!< Indicate if erasing flash when deinit mesh stack */
 } esp_ble_mesh_deinit_param_t;
 
+/** Scan parameters */
+typedef struct {
+    /**
+     * Scan interval.
+     *
+     * Range: 0x0004 to 0x4000.
+     *
+     * Time = N * 0.625 ms. Time Range: 2.5 ms to 10.24 s
+     */
+    uint16_t scan_interval;
+
+    /**
+     * Uncoded Scan window.
+     *
+     * Time scanned on uncoded PHY within a scan interval.
+     *
+     * Range: 0x0004 to 0x4000.
+     *
+     * Time = N * 0.625 ms. Time Range: 2.5 ms to 10.24 s
+     */
+    uint16_t uncoded_scan_window;
+} esp_ble_mesh_scan_param_t;
+
 /** Format of Unicast Address Range */
 typedef struct {
     uint16_t len_present:1,     /*!< Indicate the presence or absence of the RangeLength field */
diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c
index ead6c2cc022..27699600293 100644
--- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c
+++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_ble.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,8 +13,7 @@
 #include "mesh/adapter.h"
 #include "esp_ble_mesh_ble_api.h"
 
-#if CONFIG_BLE_MESH_BLE_COEX_SUPPORT
-
+#if (CONFIG_BLE_MESH_BLE_COEX_SUPPORT || CONFIG_BLE_MESH_USE_BLE_50)
 static void btc_ble_mesh_ble_copy_req_data(btc_msg_t *msg, void *p_dst, void *p_src)
 {
 #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
@@ -29,6 +28,7 @@ static void btc_ble_mesh_ble_copy_req_data(btc_msg_t *msg, void *p_dst, void *p_
     switch (msg->act) {
     case ESP_BLE_MESH_SCAN_BLE_ADVERTISING_PKT_EVT:
         if (p_src_data->scan_ble_adv_pkt.data && p_src_data->scan_ble_adv_pkt.length) {
+            memcpy(&p_dst_data->scan_ble_adv_pkt, &p_src_data->scan_ble_adv_pkt, sizeof(p_src_data->scan_ble_adv_pkt));
             p_dst_data->scan_ble_adv_pkt.length = p_src_data->scan_ble_adv_pkt.length;
             p_dst_data->scan_ble_adv_pkt.data = bt_mesh_calloc(p_src_data->scan_ble_adv_pkt.length);
             if (p_dst_data->scan_ble_adv_pkt.data) {
@@ -86,26 +86,34 @@ static void btc_ble_mesh_ble_callback(esp_ble_mesh_ble_cb_param_t *cb_params, ui
                          btc_ble_mesh_ble_copy_req_data, btc_ble_mesh_ble_free_req_data);
 }
 
-#if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
-void bt_mesh_ble_scan_cb_evt_to_btc(const bt_mesh_addr_t *addr,
-                                    uint8_t adv_type, uint8_t data[],
-                                    uint16_t length, int8_t rssi)
+#if CONFIG_BT_NIMBLE_ENABLED && CONFIG_BLE_MESH_USE_BLE_50
+void bt_mesh_ble_nimble_evt_to_btc(struct ble_gap_event *event, void *arg)
 {
     esp_ble_mesh_ble_cb_param_t param = {0};
 
-    if (addr == NULL) {
+    if (event == NULL) {
         BT_ERR("%s, Invalid parameter", __func__);
         return;
     }
 
-    memcpy(param.scan_ble_adv_pkt.addr, addr->val, sizeof(addr->val));
-    param.scan_ble_adv_pkt.addr_type = addr->type;
-    if (data && length) {
-        param.scan_ble_adv_pkt.data = data;
-        param.scan_ble_adv_pkt.length = length;
+    memcpy(&param.nimble_gap_evt.event, event, sizeof(struct ble_gap_event));
+    param.nimble_gap_evt.arg = arg;
+
+    btc_ble_mesh_ble_callback(&param, ESP_BLE_MESH_NIMBLE_GAP_EVENT_EVT);
+}
+#endif /* CONFIG_BT_NIMBLE_ENABLED && CONFIG_BLE_MESH_USE_BLE_50 */
+
+#if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
+void bt_mesh_ble_scan_cb_evt_to_btc(bt_mesh_ble_adv_report_t *adv_report)
+{
+    esp_ble_mesh_ble_cb_param_t param = {0};
+
+    if (adv_report == NULL) {
+        BT_ERR("%s, Invalid parameter", __func__);
+        return;
     }
-    param.scan_ble_adv_pkt.adv_type = adv_type;
-    param.scan_ble_adv_pkt.rssi = rssi;
+
+    memcpy(&param.scan_ble_adv_pkt, adv_report, sizeof(bt_mesh_ble_adv_report_t));
 
     btc_ble_mesh_ble_callback(&param, ESP_BLE_MESH_SCAN_BLE_ADVERTISING_PKT_EVT);
 }
@@ -157,6 +165,14 @@ void btc_ble_mesh_ble_call_handler(btc_msg_t *msg)
         btc_ble_mesh_ble_callback(&param, ESP_BLE_MESH_STOP_BLE_SCANNING_COMP_EVT);
         break;
 #endif /* CONFIG_BLE_MESH_SUPPORT_BLE_SCAN */
+    case BTC_BLE_MESH_ACT_UPDATE_SCAN_PARAMS:
+        struct bt_mesh_scan_param scan_param = {
+            .interval = arg->scan_params.scan_interval,
+            .window = arg->scan_params.uncoded_scan_window,
+        };
+        param.scan_params_update_comp.err_code = bt_mesh_scan_param_update(&scan_param);
+        btc_ble_mesh_ble_callback(&param, ESP_BLE_MESH_SCAN_PARAMS_UPDATE_COMP_EVT);
+        break;
     default:
         return;
     }
@@ -191,5 +207,4 @@ void btc_ble_mesh_ble_cb_handler(btc_msg_t *msg)
 
     btc_ble_mesh_ble_free_req_data(msg);
 }
-
-#endif /* CONFIG_BLE_MESH_BLE_COEX_SUPPORT */
+#endif /* (CONFIG_BLE_MESH_BLE_COEX_SUPPORT || CONFIG_BLE_MESH_USE_BLE_50) */
diff --git a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c
index 67d5353be8f..e8782500122 100644
--- a/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c
+++ b/components/bt/esp_ble_mesh/btc/btc_ble_mesh_prov.c
@@ -10,11 +10,13 @@
 #include "btc_ble_mesh_prov.h"
 #include "btc_ble_mesh_config_model.h"
 #include "btc_ble_mesh_health_model.h"
-#include "btc_ble_mesh_prb_model.h"
 #include "btc_ble_mesh_generic_model.h"
 #include "btc_ble_mesh_time_scene_model.h"
 #include "btc_ble_mesh_sensor_model.h"
 #include "btc_ble_mesh_lighting_model.h"
+
+#if CONFIG_BLE_MESH_V11_SUPPORT
+#include "btc_ble_mesh_prb_model.h"
 #include "btc_ble_mesh_brc_model.h"
 #include "btc_ble_mesh_odp_model.h"
 #include "btc_ble_mesh_srpl_model.h"
@@ -24,8 +26,11 @@
 #include "btc_ble_mesh_rpr_model.h"
 #include "btc_ble_mesh_df_model.h"
 #include "btc_ble_mesh_mbt_model.h"
+#include "mesh_v1.1/utils.h"
+#endif /* CONFIG_BLE_MESH_V11_SUPPORT */
 
 #include "adv.h"
+#include "scan.h"
 #include "mesh/kernel.h"
 #include "mesh/proxy.h"
 #include "mesh.h"
@@ -65,8 +70,6 @@
 #include "mesh/state_binding.h"
 #include "local.h"
 
-#include "mesh_v1.1/utils.h"
-
 #include "esp_ble_mesh_common_api.h"
 #include "esp_ble_mesh_provisioning_api.h"
 #include "esp_ble_mesh_networking_api.h"
@@ -2946,6 +2949,7 @@ void btc_ble_mesh_model_call_handler(btc_msg_t *msg)
             .ctx.send_tag   = arg->model_send.ctx->send_tag,
             .msg_timeout    = arg->model_send.msg_timeout,
         };
+
         err = bt_mesh_client_send_msg(&param, buf, arg->model_send.need_rsp,
                                       btc_ble_mesh_client_model_timeout_cb);
         bt_mesh_free_buf(buf);
diff --git a/components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_ble.h b/components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_ble.h
index 8c63002a2a9..e5d21df0d0a 100644
--- a/components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_ble.h
+++ b/components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_ble.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,6 +16,30 @@
 extern "C" {
 #endif
 
+typedef struct {
+    uint8_t   addr[6];                                /*!< Device address */
+    uint8_t   addr_type;                              /*!< Device address type */
+#if CONFIG_BLE_MESH_USE_BLE_50
+    uint8_t   adv_type __attribute__((deprecated("`event_type` should be used to determine the advertising type")));   /*!< advertising type  */
+#else
+    uint8_t   adv_type;                               /*!< Advertising type  */
+#endif
+    uint8_t   *data;                                  /*!< Advertising data */
+    uint16_t  length;                                 /*!< Advertising data length */
+    int8_t    rssi;                                   /*!< RSSI of the advertising packet */
+#if CONFIG_BLE_MESH_USE_BLE_50
+    uint8_t   event_type;                             /*!< Extended advertising event type */
+    uint8_t   primary_phy;                            /*!< Extended advertising primary PHY */
+    uint8_t   secondary_phy;                          /*!< Extended advertising secondary PHY */
+    uint8_t   sid;                                    /*!< Extended advertising set ID */
+    uint8_t   tx_power;                               /*!< Extended advertising TX power */
+    uint8_t   dir_addr_type;                          /*!< Direct address type */
+    uint8_t   dir_addr[6];                            /*!< Direct address */
+    uint8_t   data_status;                            /*!< Data type */
+    uint16_t  per_adv_interval;                       /*!< Periodic advertising interval */
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+} bt_mesh_ble_adv_report_t;
+
 typedef union {
     struct {
         esp_ble_mesh_ble_adv_param_t param;
@@ -30,6 +54,10 @@ typedef union {
     struct {
         /* RFU */
     } stop_ble_scan;
+    struct ble_mesh_scan_params {
+        uint16_t scan_interval;
+        uint16_t uncoded_scan_window;
+    } scan_params;
 } btc_ble_mesh_ble_args_t;
 
 typedef enum {
@@ -37,11 +65,14 @@ typedef enum {
     BTC_BLE_MESH_ACT_STOP_BLE_ADV,
     BTC_BLE_MESH_ACT_START_BLE_SCAN,
     BTC_BLE_MESH_ACT_STOP_BLE_SCAN,
+    BTC_BLE_MESH_ACT_UPDATE_SCAN_PARAMS,
 } btc_ble_mesh_ble_act_t;
 
-void bt_mesh_ble_scan_cb_evt_to_btc(const bt_mesh_addr_t *addr,
-                                    uint8_t adv_type, uint8_t data[],
-                                    uint16_t length, int8_t rssi);
+void bt_mesh_ble_scan_cb_evt_to_btc(bt_mesh_ble_adv_report_t *adv_report);
+
+#if CONFIG_BT_NIMBLE_ENABLED && CONFIG_BLE_MESH_USE_BLE_50
+void bt_mesh_ble_nimble_evt_to_btc(struct ble_gap_event *event, void *arg);
+#endif /* CONFIG_BT_NIMBLE_ENABLED && CONFIG_BLE_MESH_USE_BLE_50 */
 
 void btc_ble_mesh_ble_call_handler(btc_msg_t *msg);
 
diff --git a/components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_prov.h b/components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_prov.h
index f27779270f4..741a6b313d0 100644
--- a/components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_prov.h
+++ b/components/bt/esp_ble_mesh/btc/include/btc_ble_mesh_prov.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/bt/esp_ble_mesh/common/include/mesh/utils.h b/components/bt/esp_ble_mesh/common/include/mesh/utils.h
index 98243483c8e..967fed2e0c8 100644
--- a/components/bt/esp_ble_mesh/common/include/mesh/utils.h
+++ b/components/bt/esp_ble_mesh/common/include/mesh/utils.h
@@ -200,7 +200,7 @@ extern "C" {
  *    { MY_PWM0 , MY_PWM1 }
  *
  * @param LEN The length of the sequence. Must be an integer literal less
- *            than 255.
+ *            than 255 (ref: utils_loops.h).
  * @param F A macro function that accepts at least two arguments:
  *          <tt>F(i, ...)</tt>. @p F is called repeatedly in the expansion.
  *          Its first argument @p i is the index in the sequence, and
diff --git a/components/bt/esp_ble_mesh/core/access.c b/components/bt/esp_ble_mesh/core/access.c
index 9606581eb89..3791add9e34 100644
--- a/components/bt/esp_ble_mesh/core/access.c
+++ b/components/bt/esp_ble_mesh/core/access.c
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,7 @@
 #include <errno.h>
 
 #include "mesh.h"
+#include "tag.h"
 #include "adv.h"
 #include "lpn.h"
 #include "friend.h"
@@ -22,7 +23,9 @@
 #include "fast_prov.h"
 #include "pvnr_mgmt.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #define BLE_MESH_SDU_MAX_LEN    384
 
@@ -814,6 +817,135 @@ static bool ready_to_send(uint16_t dst)
     return false;
 }
 
+#if !CONFIG_BLE_MESH_V11_SUPPORT
+static bool use_friend_cred(uint16_t net_idx, uint16_t dst)
+{
+    /* Currently LPN only supports using NetKey in bt_mesh.sub[0] */
+    if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER) &&
+        net_idx == 0 &&
+        bt_mesh_lpn_match(dst)) {
+        return true;
+    }
+
+    if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) &&
+        bt_mesh_friend_match(net_idx, dst)) {
+        return true;
+    }
+
+    return false;
+}
+
+bool bt_mesh_valid_security_cred(struct bt_mesh_net_tx *tx)
+{
+    /* If the message is tagged with immutable-credentials,
+     * then the security credentials shall not be changed
+     * in lower layers.
+     * If not, later a better security credentials could be
+     * chosen for the message.
+     */
+    if (!bt_mesh_tag_immutable_cred(tx->ctx->send_tag)) {
+        return true;
+    }
+
+    if (tx->ctx->send_cred > BLE_MESH_FRIENDSHIP_CRED) {
+        return false;
+    }
+
+    if (tx->ctx->send_cred == BLE_MESH_FRIENDSHIP_CRED &&
+        !use_friend_cred(tx->ctx->net_idx, tx->ctx->addr)) {
+        return false;
+    }
+
+    return true;
+}
+
+void bt_mesh_choose_better_security_cred(struct bt_mesh_net_tx *tx)
+{
+    uint8_t send_cred = 0U;
+    uint8_t send_tag = 0U;
+    uint16_t net_idx = 0U;
+    uint16_t addr = 0U;
+
+    send_cred = tx->ctx->send_cred;
+    send_tag = tx->ctx->send_tag;
+    net_idx = tx->ctx->net_idx;
+    addr = tx->ctx->addr;
+
+    /* If the message is tagged with immutable-credentials,
+     * then the security credentials shall not be changed.
+     */
+    if (bt_mesh_tag_immutable_cred(send_tag)) {
+        return;
+    }
+
+    if (send_cred > BLE_MESH_FRIENDSHIP_CRED) {
+        BT_INFO("Use managed flooding security credentials");
+        tx->ctx->send_cred = BLE_MESH_FLOODING_CRED;
+        return;
+    }
+
+    if (send_cred == BLE_MESH_FRIENDSHIP_CRED) {
+        if (!use_friend_cred(net_idx, addr)) {
+            BT_INFO("Use managed flooding security credentials");
+            tx->ctx->send_cred = BLE_MESH_FLOODING_CRED;
+            tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED;
+        } else {
+            /* TODO:
+             * For LPN, do we need to change the friendship security
+             * credentials to managed flooding credentials?
+             * If changed, this could increase the possibility that
+             * the corresponding Friend node receives this message.
+             */
+        }
+        return;
+    }
+
+    /* If the message is destinated to a LPN, the following could be
+     * introduced to send the message with the friendship credentials.
+     *
+     * For LPN, this optimization should not be introduced, since it
+     * may cause the message failed to received by the Friend node,
+     * using friendship credentials will make the message can not be
+     * relayed by other mesh nodes.
+     */
+    if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) &&
+        BLE_MESH_ADDR_IS_UNICAST(addr) &&
+        bt_mesh_friend_match(net_idx, addr)) {
+        BT_INFO("Use friendship security credentials");
+        tx->ctx->send_cred = BLE_MESH_FRIENDSHIP_CRED;
+        tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED;
+        return;
+    }
+
+    /**
+     * Spec 3.7.3.1
+     * The Low power node in friendship should use friendship security
+     * material.
+     *
+     * But in Spec 3.6.6.2
+     * Depending on the value of the Publish Friendship Credentials Flag
+     * (see Section 4.2.3.4), the Low Power node model publishes messages
+     * using either the friendship security credentials or the managed
+     * flooding security credentials (see Section 3.9.6.3.1).
+     *
+     * So use the BLE_MESH_TAG_IMMUTABLE_CRED to indicate that the
+     * credentials of the message should not be changed when the
+     * message is sent by model publishing, even though the spec
+     * didn't require this flag to be set when model publishing.
+    */
+
+#if CONFIG_BLE_MESH_LOW_POWER
+    if (BLE_MESH_ADDR_IS_UNICAST(addr) &&
+        bt_mesh.lpn.frnd == addr &&
+        !bt_mesh_tag_immutable_cred(send_tag)) {
+        tx->ctx->send_cred = BLE_MESH_FRIENDSHIP_CRED;
+        tx->ctx->send_tag = send_tag | BLE_MESH_TAG_IMMUTABLE_CRED;
+        return;
+    }
+#endif
+}
+#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */
+
 static int model_send(struct bt_mesh_model *model,
                       struct bt_mesh_net_tx *tx, bool implicit_bind,
                       struct net_buf_simple *msg,
@@ -1108,11 +1240,13 @@ size_t bt_mesh_rx_devkey_size(void)
 #if CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER
     if (bt_mesh_is_provisioned()) {
         size = 1;
+#if CONFIG_BLE_MESH_RPR_SRV
         if (bt_mesh_dev_key_ca_valid()) {
             size += 1;
         }
+#endif /* CONFIG_BLE_MESH_RPR_SRV */
     }
-#endif
+#endif /* CONFIG_BLE_MESH_NODE && !CONFIG_BLE_MESH_PROVISIONER */
 
 #if !CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER
     if (bt_mesh_is_provisioner_en()) {
@@ -1122,9 +1256,11 @@ size_t bt_mesh_rx_devkey_size(void)
 
 #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER
     size = 1;
+#if CONFIG_BLE_MESH_RPR_SRV
     if (bt_mesh_dev_key_ca_valid()) {
         size += 1;
     }
+#endif /* CONFIG_BLE_MESH_RPR_SRV */
     if (bt_mesh_is_provisioner_en()) {
         size += 1;
     }
@@ -1156,7 +1292,9 @@ const uint8_t *bt_mesh_rx_devkey_get(size_t index, uint16_t src)
 #if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PROVISIONER
     if (index == 0) {
         key = bt_mesh.dev_key;
-    } else if (index == 1 && bt_mesh_dev_key_ca_valid()) {
+    } else
+#if CONFIG_BLE_MESH_RPR_SRV
+    if (index == 1 && bt_mesh_dev_key_ca_valid()) {
         /* If index == 1, there are two cases.
          *  1. bt_mesh_dev_key_ca_valid() is true, it should be return bt_mesh.dev_key_ca.
          *  2. bt_mesh_is_provisioner_en() is true, it should be return bt_mesh_provisioner_dev_key_get(src).
@@ -1166,7 +1304,9 @@ const uint8_t *bt_mesh_rx_devkey_get(size_t index, uint16_t src)
          * Then this round of function bt_mesh_rx_devkey_get(2, src) will return bt_mesh_provisioner_dev_key_get(src).
          */
         key = bt_mesh.dev_key_ca;
-    } else {
+    } else
+#endif
+    {
         key = bt_mesh_provisioner_dev_key_get(src);
     }
 #endif
diff --git a/components/bt/esp_ble_mesh/core/adv.c b/components/bt/esp_ble_mesh/core/adv.c
index 79932a05829..70341bbfa42 100644
--- a/components/bt/esp_ble_mesh/core/adv.c
+++ b/components/bt/esp_ble_mesh/core/adv.c
@@ -45,6 +45,14 @@ static const uint8_t adv_type[] = {
     [BLE_MESH_ADV_URI]    = BLE_MESH_DATA_URI,
 };
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+#define ESP_BLE_MESH_INST_UNUSED_ELT_(IDX, _) [IDX] = {.id = IDX}
+
+static struct bt_mesh_adv_inst adv_insts[BLE_MESH_ADV_INS_CNT] = {
+    LISTIFY(BLE_MESH_ADV_INS_CNT, ESP_BLE_MESH_INST_UNUSED_ELT_, (,)),
+};
+#endif
+
 NET_BUF_POOL_DEFINE(adv_buf_pool, CONFIG_BLE_MESH_ADV_BUF_COUNT,
                     BLE_MESH_ADV_DATA_SIZE, BLE_MESH_ADV_USER_DATA_SIZE, NULL);
 
@@ -122,11 +130,51 @@ struct bt_mesh_adv_task {
 
 static struct bt_mesh_adv_task adv_task;
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+bool bt_mesh_is_adv_inst_used(uint8_t adv_inst_id)
+{
+    uint8_t i;
+
+    for (i = 0; i < ARRAY_SIZE(adv_insts); i++) {
+        if (adv_insts[i].id == adv_inst_id) {
+            return true;
+        }
+    }
+    return false;
+}
+
+uint8_t bt_mesh_get_proxy_inst(void)
+{
+    return adv_insts[0].id;
+}
+
+void bt_mesh_adv_inst_deinit(void)
+{
+    uint8_t i;
+
+    for (i = 0; i < ARRAY_SIZE(adv_insts); i++) {
+        bt_le_ext_adv_stop(adv_insts[i].id);
+    }
+    return;
+}
+#endif
+
 static struct bt_mesh_adv *adv_alloc(int id)
 {
     return &adv_pool[id];
 }
 
+int ble_mesh_adv_task_wakeup(uint16_t adv_inst_id)
+{
+    xTaskNotify(adv_task.handle, BIT(adv_inst_id), eSetBits);
+    return 0;
+}
+
+static inline bool ble_mesh_adv_task_wait(uint32_t timeout, uint32_t *notify)
+{
+    return xTaskNotifyWait(UINT32_MAX, UINT32_MAX, notify, timeout) == pdTRUE;
+}
+
 static inline void adv_send_start(uint16_t duration, int err,
                                   const struct bt_mesh_send_cb *cb,
                                   void *cb_data)
@@ -155,8 +203,16 @@ uint16_t bt_mesh_pdu_duration(uint8_t xmit)
     return duration;
 }
 
+static inline TickType_t K_WAIT(int32_t val)
+{
+    return (val == K_FOREVER) ? portMAX_DELAY : (val / portTICK_PERIOD_MS);
+}
+
 static inline int adv_send(struct net_buf *buf)
 {
+#if CONFIG_BLE_MESH_USE_BLE_50
+    struct bt_mesh_adv_inst *adv_ins = &adv_insts[0];
+#endif
     const struct bt_mesh_send_cb *cb = BLE_MESH_ADV(buf)->cb;
     void *cb_data = BLE_MESH_ADV(buf)->cb_data;
     struct bt_mesh_adv_param param = {0};
@@ -187,6 +243,11 @@ static inline int adv_send(struct net_buf *buf)
         param.interval_min = ADV_SCAN_UNIT(adv_int);
         param.interval_max = param.interval_min;
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+        param.adv_duration = duration;
+        param.adv_count = BLE_MESH_TRANSMIT_COUNT(BLE_MESH_ADV(buf)->xmit) + 1;
+#endif
+
 #if CONFIG_BLE_MESH_PROXY_SOLIC_PDU_TX
         if (BLE_MESH_ADV(buf)->type == BLE_MESH_ADV_PROXY_SOLIC) {
             bt_mesh_adv_buf_ref_debug(__func__, buf, 3U, BLE_MESH_BUF_REF_SMALL);
@@ -195,12 +256,24 @@ static inline int adv_send(struct net_buf *buf)
                 BLE_MESH_ADV_DATA_BYTES(BLE_MESH_DATA_UUID16_ALL, 0x59, 0x18),
                 BLE_MESH_ADV_DATA(BLE_MESH_DATA_SVC_DATA16, buf->data, buf->len),
             };
-            err = bt_le_adv_start(&param, solic_ad, 3, NULL, 0);
+#if CONFIG_BLE_MESH_USE_BLE_50
+            param.primary_phy = BLE_MESH_ADV_PHY_1M;
+            param.secondary_phy = BLE_MESH_ADV_PHY_1M;
+            err = bt_le_ext_adv_start(adv_ins->id, &param, &ad, 3, NULL, 0);
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
+            err = bt_le_adv_start(&param, &ad, 3, NULL, 0);
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
         } else
 #endif
         {
             bt_mesh_adv_buf_ref_debug(__func__, buf, 4U, BLE_MESH_BUF_REF_SMALL);
+#if CONFIG_BLE_MESH_USE_BLE_50
+            param.primary_phy = BLE_MESH_ADV_PHY_1M;
+            param.secondary_phy = BLE_MESH_ADV_PHY_1M;
+            err = bt_le_ext_adv_start(adv_ins->id, &param, &ad, 1, NULL, 0);
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
             err = bt_le_adv_start(&param, &ad, 1, NULL, 0);
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
         }
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
     } else {
@@ -229,7 +302,11 @@ static inline int adv_send(struct net_buf *buf)
 
         bt_mesh_adv_buf_ref_debug(__func__, buf, 3U, BLE_MESH_BUF_REF_SMALL);
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+        err = bt_mesh_ble_ext_adv_start(adv_ins->id, &tx->param, &data);
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
         err = bt_mesh_ble_adv_start(&tx->param, &data);
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
     }
 #endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */
 
@@ -242,9 +319,19 @@ static inline int adv_send(struct net_buf *buf)
 
     BT_DBG("Advertising started. Sleeping %u ms", duration);
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    if (!ble_mesh_adv_task_wait(K_WAIT(K_FOREVER), NULL)) {
+        BT_WARN("Advertising didn't finish on time");
+        bt_le_ext_adv_stop(adv_ins->id);
+    }
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
     k_sleep(K_MSEC(duration));
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
+#if !CONFIG_BLE_MESH_USE_BLE_50
     err = bt_le_adv_stop();
+#endif
+
     adv_send_end(err, cb, cb_data);
     if (err) {
         BT_ERR("Stop advertising failed: err %d", err);
@@ -255,11 +342,6 @@ static inline int adv_send(struct net_buf *buf)
     return 0;
 }
 
-static inline TickType_t K_WAIT(int32_t val)
-{
-    return (val == K_FOREVER) ? portMAX_DELAY : (val / portTICK_PERIOD_MS);
-}
-
 static void adv_thread(void *p)
 {
 #if CONFIG_BLE_MESH_RELAY_ADV_BUF
@@ -679,6 +761,10 @@ void bt_mesh_adv_deinit(void)
         return;
     }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    bt_mesh_adv_inst_deinit();
+#endif
+
     vTaskDelete(adv_task.handle);
     adv_task.handle = NULL;
 #if (CONFIG_BLE_MESH_FREERTOS_STATIC_ALLOC_EXTERNAL && \
diff --git a/components/bt/esp_ble_mesh/core/adv.h b/components/bt/esp_ble_mesh/core/adv.h
index 33224d78b11..d2fb7baca39 100644
--- a/components/bt/esp_ble_mesh/core/adv.h
+++ b/components/bt/esp_ble_mesh/core/adv.h
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +13,7 @@
 #include "mesh/atomic.h"
 #include "mesh/access.h"
 #include "mesh/adapter.h"
+#include "mesh/utils.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -67,6 +68,19 @@ typedef enum {
     BLE_MESH_BUF_REF_MAX,
 } bt_mesh_buf_ref_flag_t;
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+
+#define BLE_MESH_ADV_INS_UNUSED 0xFF
+#define BLE_MESH_ADV_INS_CNT    1
+
+struct bt_mesh_adv_inst {
+    uint8_t id;
+};
+
+int ble_mesh_adv_task_wakeup(uint16_t adv_inst_id);
+bool bt_mesh_is_adv_inst_used(uint8_t adv_inst_id);
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+
 void bt_mesh_adv_buf_ref_debug(const char *func, struct net_buf *buf,
                                uint8_t ref_cmp, bt_mesh_buf_ref_flag_t flag);
 
@@ -81,6 +95,10 @@ void bt_mesh_adv_send(struct net_buf *buf, uint8_t xmit,
                       const struct bt_mesh_send_cb *cb,
                       void *cb_data);
 
+#if CONFIG_BLE_MESH_USE_BLE_50 && (CONFIG_BLE_MESH_GATT_PROXY_SERVER || CONFIG_BLE_MESH_PB_GATT)
+uint8_t bt_mesh_get_proxy_inst(void);
+#endif
+
 struct net_buf *bt_mesh_relay_adv_create(enum bt_mesh_adv_type type, int32_t timeout);
 
 void bt_mesh_relay_adv_send(struct net_buf *buf, uint8_t xmit,
diff --git a/components/bt/esp_ble_mesh/core/beacon.c b/components/bt/esp_ble_mesh/core/beacon.c
index 488a3c5f6d0..45e4a2d1a95 100644
--- a/components/bt/esp_ble_mesh/core/beacon.c
+++ b/components/bt/esp_ble_mesh/core/beacon.c
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,7 +25,9 @@
 #include "pvnr_mgmt.h"
 #include "mesh/common.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #if defined(CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL)
 #define UNPROV_BEACON_INTERVAL     K_SECONDS(CONFIG_BLE_MESH_UNPROVISIONED_BEACON_INTERVAL)
@@ -472,12 +474,13 @@ void bt_mesh_beacon_recv(struct net_buf_simple *buf, int8_t rssi)
             bt_mesh_provisioner_unprov_beacon_recv(buf, rssi);
         }
 
-        if (IS_ENABLED(CONFIG_BLE_MESH_RPR_SRV) &&
-            bt_mesh_is_provisioned()) {
+#if CONFIG_BLE_MESH_RPR_SRV
+        if (bt_mesh_is_provisioned()) {
             const bt_mesh_addr_t *addr = bt_mesh_get_unprov_dev_addr();
             bt_mesh_unprov_dev_fifo_enqueue(buf->data, addr->val, bt_mesh_get_adv_type());
             bt_mesh_rpr_srv_unprov_beacon_recv(buf, bt_mesh_get_adv_type(), addr, rssi);
         }
+#endif
         break;
     case BEACON_TYPE_SECURE:
         secure_beacon_recv(buf);
diff --git a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c
index e0fc33b4844..d72b83b2639 100644
--- a/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c
+++ b/components/bt/esp_ble_mesh/core/bluedroid_host/adapter.c
@@ -29,10 +29,14 @@
 #include "mesh/adapter.h"
 #include "mesh/common.h"
 #include "prov_pvnr.h"
+#include "scan.h"
 #include "net.h"
 #include "beacon.h"
+#include "btc_ble_mesh_ble.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 struct bt_mesh_dev bt_mesh_dev;
 
@@ -58,7 +62,10 @@ static uint8_t bt_mesh_private_key[32];
 
 /* Scan related functions */
 static bt_mesh_scan_cb_t *bt_mesh_scan_dev_found_cb;
+
+#if !CONFIG_BLE_MESH_USE_BLE_50
 static void bt_mesh_scan_result_callback(tBTA_DM_SEARCH_EVT event, tBTA_DM_SEARCH *p_data);
+#endif
 
 #if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_SERVER || \
@@ -102,6 +109,14 @@ static struct bt_mesh_prov_conn_cb *bt_mesh_gattc_conn_cb;
 static tBTA_GATTC_IF bt_mesh_gattc_if;
 #endif
 
+#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BLE_MESH_SUPPORT_BLE_ADV
+static inline void bt_mesh_set_ble_adv_running();
+
+static inline void bt_mesh_unset_ble_adv_running();
+
+static inline bool bt_mesh_is_ble_adv_running();
+#endif
+
 int bt_mesh_host_init(void)
 {
     return 0;
@@ -136,11 +151,18 @@ void bt_mesh_hci_init(void)
 
     const uint8_t *p = controller_get_interface()->get_ble_supported_states();
     uint64_t states_fh = 0, states_sh = 0;
-    STREAM_TO_UINT32(states_fh, p);
-    STREAM_TO_UINT32(states_sh, p);
+
+    /* macro STREAM_TO_UINT32 expansion */
+    states_fh = (((uint32_t)(*(p))) + ((((uint32_t)(*((p) + 1)))) << 8) + ((((uint32_t)(*((p) + 2)))) << 16) + ((((uint32_t)(*((p) + 3)))) << 24));
+    (p) += 4;
+
+    states_sh = (((uint32_t)(*(p))) + ((((uint32_t)(*((p) + 1)))) << 8) + ((((uint32_t)(*((p) + 2)))) << 16) + ((((uint32_t)(*((p) + 3)))) << 24));
+    (p) += 4;
+
     bt_mesh_dev.le.states = (states_sh << 32) | states_fh;
 }
 
+#if !CONFIG_BLE_MESH_USE_BLE_50
 static void bt_mesh_scan_results_change_2_bta(tBTM_INQ_RESULTS *p_inq, uint8_t *p_eir,
                                               tBTA_DM_SEARCH_CBACK *p_scan_cback)
 {
@@ -183,6 +205,189 @@ static void bt_mesh_scan_results_cb(tBTM_INQ_RESULTS *p_inq, uint8_t *p_eir)
 {
     bt_mesh_scan_results_change_2_bta(p_inq, p_eir, bt_mesh_scan_result_callback);
 }
+#endif
+
+#if CONFIG_BLE_MESH_USE_BLE_50
+extern void btc_ble_5_gap_callback(tBTA_DM_BLE_5_GAP_EVENT event,
+                                   tBTA_DM_BLE_5_GAP_CB_PARAMS *params);
+
+void bt_mesh_ble_ext_adv_report(tBTM_BLE_EXT_ADV_REPORT *ext_adv_report)
+{
+#if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
+    bt_mesh_ble_adv_report_t adv_rpt = {0};
+
+    if (bt_mesh_ble_scan_state_get()) {
+        memcpy(adv_rpt.addr, ext_adv_report->addr, BLE_MESH_ADDR_LEN);
+        memcpy(adv_rpt.dir_addr, ext_adv_report->dir_addr, BLE_MESH_ADDR_LEN);
+
+        adv_rpt.addr_type           = ext_adv_report->addr_type;
+        adv_rpt.data                = ext_adv_report->adv_data;
+        adv_rpt.length              = ext_adv_report->adv_data_len;
+        adv_rpt.rssi                = ext_adv_report->rssi;
+        adv_rpt.event_type          = ext_adv_report->event_type;
+        adv_rpt.primary_phy         = ext_adv_report->primary_phy;
+        adv_rpt.secondary_phy       = ext_adv_report->secondry_phy;
+        adv_rpt.sid                 = ext_adv_report->sid;
+        adv_rpt.tx_power            = ext_adv_report->tx_power;
+        adv_rpt.dir_addr_type       = ext_adv_report->dir_addr_type;
+        adv_rpt.data_status         = ext_adv_report->data_status;
+        adv_rpt.per_adv_interval    = ext_adv_report->per_adv_interval;
+
+        bt_mesh_ble_scan_cb_evt_to_btc(&adv_rpt);
+    }
+#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_SCAN */
+}
+
+static bool bt_mesh_scan_result_process(tBTM_BLE_EXT_ADV_REPORT *ext_adv_report)
+{
+    struct bt_mesh_adv_report adv_rpt = {0};
+
+    assert(ext_adv_report);
+
+    adv_rpt.addr.type = ext_adv_report->addr_type;
+    memcpy(adv_rpt.addr.val, ext_adv_report->addr, BLE_MESH_ADDR_LEN);
+    adv_rpt.primary_phy = ext_adv_report->primary_phy;
+    adv_rpt.secondary_phy = ext_adv_report->secondry_phy;
+    adv_rpt.rssi = ext_adv_report->rssi;
+
+    if (!(ext_adv_report->event_type & BTM_BLE_ADV_LEGACY_MASK)) {
+        return false;
+    }
+
+    if (!bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_SCANNING)) {
+        return false;
+    }
+
+    BT_DBG("Recv adv report type %04x", ext_adv_report->event_type);
+
+    switch (ext_adv_report->event_type) {
+    case BLE_MESH_ADV_IND:
+    case BLE_MESH_ADV_DIRECT_IND:
+    case BLE_MESH_ADV_SCAN_IND:
+    case BLE_MESH_ADV_NONCONN_IND:
+    case BLE_MESH_ADV_SCAN_RSP:
+        adv_rpt.adv_type = ext_adv_report->event_type;
+    break;
+    default:
+        return false;
+    break;
+    }
+
+    if (bt_mesh_scan_dev_found_cb) {
+        net_buf_simple_init_with_data(&adv_rpt.adv_data, ext_adv_report->adv_data, ext_adv_report->adv_data_len);
+        bt_mesh_scan_dev_found_cb(&adv_rpt);
+        if (adv_rpt.adv_data.len != ext_adv_report->adv_data_len) {
+            /* The advertising data has been processed by Mesh Protocol */
+            return true;
+        }
+    }
+    return false;
+}
+
+void ble_mesh_5_gap_callback(tBTA_DM_BLE_5_GAP_EVENT event,
+                             tBTA_DM_BLE_5_GAP_CB_PARAMS *params)
+{
+    BT_DBG("recv event %d", event);
+
+    switch (event) {
+    case BTA_DM_BLE_5_GAP_EXT_ADV_SET_PARAMS_COMPLETE_EVT:
+        if (!bt_mesh_is_adv_inst_used(params->set_params.instance)) {
+            goto transfer_to_user;
+        }
+        if (params->set_params.status != BTM_SUCCESS) {
+            BT_ERR("BTA_DM_BLE_5_GAP_EXT_ADV_SET_PARAMS_COMPLETE_EVT Failed");
+        }
+        break;
+    case BTA_DM_BLE_5_GAP_EXT_ADV_DATA_SET_COMPLETE_EVT:
+        if (!bt_mesh_is_adv_inst_used(params->adv_data_set.instance)) {
+            goto transfer_to_user;
+        }
+        if (params->adv_data_set.status != BTM_SUCCESS) {
+            BT_ERR("BTA_DM_BLE_5_GAP_EXT_ADV_DATA_SET_COMPLETE_EVT Failed");
+        }
+        break;
+    case BTA_DM_BLE_5_GAP_EXT_SCAN_RSP_DATA_SET_COMPLETE_EVT:
+        if (!bt_mesh_is_adv_inst_used(params->scan_rsp_data_set.instance)) {
+            goto transfer_to_user;
+        }
+        if (params->scan_rsp_data_set.status != BTM_SUCCESS) {
+            BT_ERR("BTA_DM_BLE_5_GAP_EXT_SCAN_RSP_DATA_SET_COMPLETE_EVT Failed");
+        }
+        break;
+    case BTA_DM_BLE_5_GAP_EXT_ADV_START_COMPLETE_EVT:
+        if (!bt_mesh_is_adv_inst_used(params->adv_start.instance[0])) {
+            goto transfer_to_user;
+        }
+        if (params->adv_start.status != BTM_SUCCESS) {
+            BT_ERR("BTA_DM_BLE_5_GAP_EXT_ADV_START_COMPLETE_EVT Failed");
+        }
+        break;
+    case BTA_DM_BLE_5_GAP_EXT_ADV_STOP_COMPLETE_EVT:
+        if (!bt_mesh_is_adv_inst_used(params->adv_start.instance[0])) {
+            goto transfer_to_user;
+        }
+        if (params->adv_start.status != BTM_SUCCESS) {
+            BT_ERR("BTA_DM_BLE_5_GAP_EXT_ADV_STOP_COMPLETE_EVT Failed");
+        }
+        break;
+    case BTA_DM_BLE_5_GAP_ADV_TERMINATED_EVT:
+        if (!bt_mesh_is_adv_inst_used(params->adv_term.adv_handle)) {
+            goto transfer_to_user;
+        }
+        if (params->adv_term.status == 0x43 ||  /* Limit reached */
+            params->adv_term.status == 0x3C) {  /* Advertising timeout */
+            ble_mesh_adv_task_wakeup(params->adv_term.adv_handle);
+        }
+#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
+        /**
+         * This judgment is to distinguish between the termination
+         * events of BLE connectable broadcasting and proxy connectable
+         * adv under the same instance ID, that is, when the status is 0.
+         *
+         * Since the host task and adv task are currently operated in
+         * series, there is no need to consider competition issues between
+         * tasks.
+         *
+         * @attention: once multiple adv instances are used, the adv task
+         * and host will be asynchronous, and it is necessary to consider
+         * the issue of resource competition.
+         */
+        if (bt_mesh_is_ble_adv_running() &&
+            params->adv_term.status == 0x00) {
+            /* The unset operation must be performed before waking up the
+                * adv task; performing the unset after waking up the adv task
+                * could lead to resource contention issues.
+                */
+            bt_mesh_unset_ble_adv_running();
+            ble_mesh_adv_task_wakeup(params->adv_term.adv_handle);
+        }
+#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */
+        break;
+    case BTA_DM_BLE_5_GAP_EXT_ADV_REPORT_EVT:
+        if (!bt_mesh_scan_result_process(&params->ext_adv_report)) {
+            bt_mesh_ble_ext_adv_report(&params->ext_adv_report);
+        }
+        break;
+    case BTA_DM_BLE_5_GAP_EXT_SCAN_START_COMPLETE_EVT:
+        if (params->scan_start.status != BTM_SUCCESS) {
+            BT_ERR("BTA_DM_BLE_5_GAP_EXT_SCAN_START_COMPLETE_EVT Failed");
+        }
+        break;
+    case BTA_DM_BLE_5_GAP_EXT_SCAN_STOP_COMPLETE_EVT:
+        if (params->scan_stop.status != BTM_SUCCESS) {
+            BT_ERR("BTM_BLE_5_GAP_EXT_SCAN_START_COMPLETE_EVT Failed");
+        }
+        break;
+    default:
+        goto transfer_to_user;
+    }
+
+    return;
+
+transfer_to_user:
+    btc_ble_5_gap_callback(event, params);
+}
+#endif
 
 static bool valid_adv_param(const struct bt_mesh_adv_param *param)
 {
@@ -203,7 +408,12 @@ static bool valid_adv_param(const struct bt_mesh_adv_param *param)
     return true;
 }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+static int set_adv_data(uint16_t hci_op, const uint8_t inst_id,
+                        const struct bt_mesh_adv_data *ad, size_t ad_len)
+#else
 static int set_adv_data(uint16_t hci_op, const struct bt_mesh_adv_data *ad, size_t ad_len)
+#endif
 {
     struct bt_mesh_hci_cp_set_adv_data param = {0};
     int i;
@@ -225,16 +435,22 @@ static int set_adv_data(uint16_t hci_op, const struct bt_mesh_adv_data *ad, size
         param.len += ad[i].data_len;
     }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+        BTA_DmBleGapConfigExtAdvDataRaw(hci_op == BLE_MESH_HCI_OP_SET_SCAN_RSP_DATA,
+                                        inst_id, param.len, param.data);
+#else
     /* Set adv data and scan rsp data. */
     if (hci_op == BLE_MESH_HCI_OP_SET_ADV_DATA) {
         BLE_MESH_BTM_CHECK_STATUS(BTM_BleWriteAdvDataRaw(param.data, param.len));
     } else if (hci_op == BLE_MESH_HCI_OP_SET_SCAN_RSP_DATA) {
         BLE_MESH_BTM_CHECK_STATUS(BTM_BleWriteScanRspRaw(param.data, param.len));
     }
+#endif
 
     return 0;
 }
 
+#if !CONFIG_BLE_MESH_USE_BLE_50
 static void start_adv_completed_cb(uint8_t status)
 {
 #if BLE_MESH_DEV
@@ -243,6 +459,7 @@ static void start_adv_completed_cb(uint8_t status)
     }
 #endif
 }
+#endif
 
 static bool valid_scan_param(const struct bt_mesh_scan_param *param)
 {
@@ -274,15 +491,54 @@ static bool valid_scan_param(const struct bt_mesh_scan_param *param)
 static int start_le_scan(uint8_t scan_type, uint16_t interval, uint16_t window,
                          uint8_t filter_dup, uint8_t scan_fil_policy)
 {
+#if !CONFIG_BLE_MESH_USE_BLE_50
     uint8_t addr_type_own = BLE_MESH_ADDR_PUBLIC;  /* Currently only support Public Address */
     tGATT_IF client_if = 0xFF; /* Default GATT interface id */
+#endif
+
+#if CONFIG_BLE_MESH_USE_BLE_50
+    tBTA_DM_BLE_EXT_SCAN_PARAMS ext_scan_params = {0};
+
+    if (interval == 0 ||
+        interval < window) {
+        BT_ERR("invalid scan param itvl %d win %d", interval, window);
+        return EINVAL;
+    }
+
+    ext_scan_params.own_addr_type = BLE_MESH_ADDR_PUBLIC;
+    ext_scan_params.filter_policy = scan_fil_policy;
+    ext_scan_params.scan_duplicate = filter_dup;
+
+    if (window == 0) {
+        ext_scan_params.cfg_mask = BTM_BLE_GAP_EXT_SCAN_CODE_MASK;
+    } else if (interval > window) {
+        ext_scan_params.cfg_mask = BTM_BLE_GAP_EXT_SCAN_UNCODE_MASK | BTM_BLE_GAP_EXT_SCAN_CODE_MASK;
+    } else {
+        // interval == window
+        ext_scan_params.cfg_mask = BTM_BLE_GAP_EXT_SCAN_UNCODE_MASK;
+    }
+
+    ext_scan_params.uncoded_cfg.scan_type = scan_type;
+    ext_scan_params.uncoded_cfg.scan_interval = interval;
+    ext_scan_params.uncoded_cfg.scan_window = window;
+
+    ext_scan_params.coded_cfg.scan_type = scan_type;
+    ext_scan_params.coded_cfg.scan_interval = interval;
+    ext_scan_params.coded_cfg.scan_window = interval - window;
+
+    BTA_DmBleGapSetExtScanParams(&ext_scan_params);
 
+    BTM_BleGapRegisterCallback(ble_mesh_5_gap_callback);
+
+    BTA_DmBleGapExtScan(true, 0, 0);
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
     BLE_MESH_BTM_CHECK_STATUS(
         BTM_BleSetScanFilterParams(client_if, interval, window, scan_type, addr_type_own,
                                    filter_dup, scan_fil_policy, NULL));
 
     /* BLE Mesh scan permanently, so no duration of scan here */
     BLE_MESH_BTM_CHECK_STATUS(BTM_BleScan(true, 0, bt_mesh_scan_results_cb, NULL, NULL));
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 #if BLE_MESH_DEV
     if (scan_type == BLE_MESH_SCAN_ACTIVE) {
@@ -295,22 +551,32 @@ static int start_le_scan(uint8_t scan_type, uint16_t interval, uint16_t window,
     return 0;
 }
 
+#if !CONFIG_BLE_MESH_USE_BLE_50
 static void bt_mesh_scan_result_callback(tBTA_DM_SEARCH_EVT event, tBTA_DM_SEARCH *p_data)
 {
-    struct net_buf_simple buf = {0};
-    bt_mesh_addr_t addr = {0};
+    struct bt_mesh_adv_report adv_rpt = {0};
 
     BT_DBG("%s, event %d", __func__, event);
 
     if (event == BTA_DM_INQ_RES_EVT) {
         /* TODO: How to process scan response here? PS: p_data->inq_res.scan_rsp_len */
-        addr.type = p_data->inq_res.ble_addr_type;
-        memcpy(addr.val, p_data->inq_res.bd_addr, BLE_MESH_ADDR_LEN);
 
-        net_buf_simple_init_with_data(&buf, p_data->inq_res.p_eir, p_data->inq_res.adv_data_len);
+        adv_rpt.addr.type = p_data->inq_res.ble_addr_type;
+        adv_rpt.rssi = p_data->inq_res.rssi;
+        adv_rpt.adv_type = p_data->inq_res.ble_evt_type;
+
+        memcpy(adv_rpt.addr.val, p_data->inq_res.bd_addr, BLE_MESH_ADDR_LEN);
+
+        net_buf_simple_init_with_data(&adv_rpt.adv_data, p_data->inq_res.p_eir, p_data->inq_res.adv_data_len);
 
         if (bt_mesh_scan_dev_found_cb) {
-            bt_mesh_scan_dev_found_cb(&addr, p_data->inq_res.rssi, p_data->inq_res.ble_evt_type, &buf, p_data->inq_res.scan_rsp_len);
+            bt_mesh_scan_dev_found_cb(&adv_rpt);
+
+            if (p_data->inq_res.scan_rsp_len) {
+                adv_rpt.adv_type = BLE_MESH_ADV_SCAN_RSP;
+                net_buf_simple_init_with_data(&adv_rpt.adv_data, p_data->inq_res.p_eir + p_data->inq_res.adv_data_len, p_data->inq_res.scan_rsp_len);
+                bt_mesh_scan_dev_found_cb(&adv_rpt);
+            }
         }
     } else if (event == BTA_DM_INQ_CMPL_EVT) {
         BT_INFO("Scan completed, number of scan response %d", p_data->inq_cmpl.num_resps);
@@ -318,7 +584,132 @@ static void bt_mesh_scan_result_callback(tBTA_DM_SEARCH_EVT event, tBTA_DM_SEARC
         BT_WARN("Unexpected scan result event %d", event);
     }
 }
+#endif
+
+#if CONFIG_BLE_MESH_USE_BLE_50
+int bt_le_ext_adv_start(const uint8_t inst_id,
+                        const struct bt_mesh_adv_param *param,
+                        const struct bt_mesh_adv_data *ad, size_t ad_len,
+                        const struct bt_mesh_adv_data *sd, size_t sd_len)
+{
+    tBTA_DM_BLE_GAP_EXT_ADV_PARAMS ext_adv_params = {0};
+    tBTA_DM_BLE_EXT_ADV ext_adv = {0};
+    uint16_t interval = 0U;
+    int err = 0;
+
+    assert(param);
+
+#if BLE_MESH_DEV
+    if (bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING)) {
+        return -EALREADY;
+    }
+#endif
+
+    if (!valid_adv_param(param)) {
+        BT_ERR("Invalid adv parameters");
+        return -EINVAL;
+    }
+
+    memset(&ext_adv_params, 0, sizeof(tBTA_DM_BLE_GAP_EXT_ADV_PARAMS));
+
+    if (param->options & BLE_MESH_ADV_OPT_CONNECTABLE) {
+        ext_adv_params.type = BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND;
+    } else if (sd != NULL) {
+        ext_adv_params.type = BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_SCAN;
+    } else {
+        if (param->primary_phy == BLE_MESH_ADV_PHY_1M &&
+            param->secondary_phy == BLE_MESH_ADV_PHY_1M) {
+            ext_adv_params.type = BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_NONCONN;
+        } else {
+            BT_ERR("Unsupported PHY: pri %d sec %d",param->primary_phy, param->secondary_phy);
+            return -EINVAL;
+        }
+    }
+
+#if CONFIG_BLE_MESH_PRB_SRV
+    /* NOTE: When a Mesh Private beacon is advertised, the Mesh Private beacon shall
+     * use a resolvable private address or a non-resolvable private address in the
+     * AdvA field of the advertising PDU.
+     */
+    if (ad->type == BLE_MESH_DATA_MESH_BEACON && ad->data[0] == BEACON_TYPE_PRIVATE) {
+        ext_adv_params.own_addr_type = BLE_MESH_ADDR_RANDOM;
+    } else {
+        ext_adv_params.own_addr_type = BLE_MESH_ADDR_PUBLIC;
+    }
+#else
+    ext_adv_params.own_addr_type = BLE_MESH_ADDR_PUBLIC;
+#endif
+
+    ext_adv_params.sid = inst_id;
+    ext_adv_params.max_skip = 0;
+    ext_adv_params.tx_power = 0x7F;
+    ext_adv_params.scan_req_notif = false;
+    ext_adv_params.primary_phy = param->primary_phy;
+    ext_adv_params.secondary_phy = param->secondary_phy;
+    ext_adv_params.filter_policy = BLE_MESH_AP_SCAN_CONN_ALL;
+    ext_adv_params.channel_map = BLE_MESH_ADV_CHNL_37 | BLE_MESH_ADV_CHNL_38 | BLE_MESH_ADV_CHNL_39;
+
+    interval = param->interval_min;
 
+#if CONFIG_BLE_MESH_RANDOM_ADV_INTERVAL
+    /* If non-connectable mesh packets are transmitted with an adv interval
+     * not smaller than 10ms, then we will use a random adv interval between
+     * [interval / 2, interval] for them.
+     */
+    if (adv_type == BLE_MESH_ADV_NONCONN_IND && interval >= 16) {
+        interval >>= 1;
+        interval += (bt_mesh_get_rand() % (interval + 1));
+
+        BT_INFO("%u->%u", param->interval_min, interval);
+    }
+#endif
+
+    ext_adv_params.interval_min = interval;
+    ext_adv_params.interval_max = interval;
+
+    /* Check if we can start adv using BTM_BleSetAdvParamsStartAdvCheck */
+    BTA_DmBleGapExtAdvSetParams(inst_id, &ext_adv_params);
+
+    err = set_adv_data(BLE_MESH_HCI_OP_SET_ADV_DATA, inst_id, ad, ad_len);
+    if (err) {
+        BT_ERR("Failed to set adv data, err %d", err);
+        return err;
+    }
+
+    /*
+     * We need to set SCAN_RSP when enabling advertising type that allows
+     * for Scan Requests.
+     *
+     * If sd was not provided but we enable connectable undirected
+     * advertising sd needs to be cleared from values set by previous calls.
+     * Clearing sd is done by calling set_adv_data() with NULL data and zero len.
+     * So following condition check is unusual but correct.
+     */
+    if (sd && (param->options & BLE_MESH_ADV_OPT_CONNECTABLE)) {
+        err = set_adv_data(BLE_MESH_HCI_OP_SET_SCAN_RSP_DATA, inst_id, sd, sd_len);
+        if (err) {
+            BT_ERR("Failed to set scan rsp data err %d", err);
+            return err;
+        }
+    }
+
+    ext_adv.instance = inst_id;
+    ext_adv.duration = param->adv_duration / 10;
+    ext_adv.max_events = param->adv_count;
+
+    BTA_DmBleGapExtAdvEnable(true, 1, &ext_adv);
+
+#if BLE_MESH_DEV
+    bt_mesh_atomic_set_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING);
+
+    if (!(param->options & BLE_MESH_ADV_OPT_ONE_TIME)) {
+        bt_mesh_atomic_set_bit(bt_mesh_dev.flags, BLE_MESH_DEV_KEEP_ADVERTISING);
+    }
+#endif
+
+    return 0;
+}
+#else  /* CONFIG_BLE_MESH_USE_BLE_50 */
 /* APIs functions */
 int bt_le_adv_start(const struct bt_mesh_adv_param *param,
                     const struct bt_mesh_adv_data *ad, size_t ad_len,
@@ -346,7 +737,7 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param,
 
     err = set_adv_data(BLE_MESH_HCI_OP_SET_ADV_DATA, ad, ad_len);
     if (err) {
-        BT_ERR("Failed to set adv data");
+        BT_ERR("Failed to set adv data, err %d", err);
         return err;
     }
 
@@ -362,7 +753,7 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param,
     if (sd && (param->options & BLE_MESH_ADV_OPT_CONNECTABLE)) {
         err = set_adv_data(BLE_MESH_HCI_OP_SET_SCAN_RSP_DATA, sd, sd_len);
         if (err) {
-            BT_ERR("Failed to set scan rsp data");
+            BT_ERR("Failed to set scan rsp data, err %d", err);
             return err;
         }
     }
@@ -425,8 +816,97 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param,
 
     return 0;
 }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
+#if CONFIG_BLE_MESH_USE_BLE_50
+
+static bool _ble_adv_running_flag;
+
+static inline void bt_mesh_set_ble_adv_running()
+{
+    _ble_adv_running_flag = true;
+}
+
+static inline void bt_mesh_unset_ble_adv_running()
+{
+    _ble_adv_running_flag = false;
+}
+
+static inline bool bt_mesh_is_ble_adv_running()
+{
+    return _ble_adv_running_flag == true;
+}
+
+int bt_mesh_ble_ext_adv_start(const uint8_t inst_id,
+                              const struct bt_mesh_ble_adv_param *param,
+                              const struct bt_mesh_ble_adv_data *data)
+{
+    tBTA_DM_BLE_GAP_EXT_ADV_PARAMS ext_adv_params = {0};
+    tBTA_DM_BLE_EXT_ADV ext_adv = {0};
+    struct bt_mesh_hci_cp_set_adv_data set = {0};
+
+    if (data && param->adv_type != BLE_MESH_ADV_DIRECT_IND &&
+        param->adv_type != BLE_MESH_ADV_DIRECT_IND_LOW_DUTY) {
+        if (data->adv_data_len) {
+            set.len = data->adv_data_len;
+            memcpy(set.data, data->adv_data, data->adv_data_len);
+                BTA_DmBleGapConfigExtAdvDataRaw(false, inst_id, set.len, set.data);
+        }
+        if (data->scan_rsp_data_len && param->adv_type != BLE_MESH_ADV_NONCONN_IND) {
+            set.len = data->scan_rsp_data_len;
+            memcpy(set.data, data->scan_rsp_data, data->scan_rsp_data_len);
+                BTA_DmBleGapConfigExtAdvDataRaw(true, inst_id, set.len, set.data);
+        }
+    }
+
+    switch (param->adv_type) {
+    case BLE_MESH_ADV_IND:
+    case BLE_MESH_ADV_DIRECT_IND:
+    case BLE_MESH_ADV_SCAN_IND:
+    case BLE_MESH_ADV_NONCONN_IND:
+    case BLE_MESH_ADV_SCAN_RSP:
+        ext_adv_params.type = param->adv_type;
+        break;
+    default:
+        BT_ERR("Unsupported adv type %d", param->adv_type);
+        return -EINVAL;
+    }
+
+    ext_adv_params.max_skip = 0;
+    ext_adv_params.tx_power = 0x7F;
+    ext_adv_params.sid = inst_id;
+    ext_adv_params.scan_req_notif = false;
+    ext_adv_params.own_addr_type = param->own_addr_type;
+    ext_adv_params.interval_min = param->interval;
+    ext_adv_params.interval_max = param->interval;
+    ext_adv_params.primary_phy = BLE_MESH_ADV_PHY_1M;
+    ext_adv_params.secondary_phy = BLE_MESH_ADV_PHY_1M;
+    ext_adv_params.filter_policy = BLE_MESH_AP_SCAN_CONN_ALL;
+    ext_adv_params.channel_map = BLE_MESH_ADV_CHNL_37 | BLE_MESH_ADV_CHNL_38 | BLE_MESH_ADV_CHNL_39;
+
+    if (param->own_addr_type == BLE_MESH_ADDR_PUBLIC_ID ||
+        param->own_addr_type == BLE_MESH_ADDR_RANDOM_ID ||
+        param->adv_type == BLE_MESH_ADV_DIRECT_IND ||
+        param->adv_type == BLE_MESH_ADV_DIRECT_IND_LOW_DUTY) {
+        ext_adv_params.peer_addr_type = param->peer_addr_type;
+        memcpy(ext_adv_params.peer_addr, param->peer_addr, BLE_MESH_ADDR_LEN);
+    }
+
+    ext_adv.instance = inst_id;
+    ext_adv.duration = param->duration;
+    ext_adv.max_events = param->count;
+
+    /* Check if we can start adv using BTM_BleSetAdvParamsStartAdvCheck */
+    BTA_DmBleGapExtAdvSetParams(inst_id, &ext_adv_params);
+
+    BTA_DmBleGapExtAdvEnable(true, 1, &ext_adv);
+
+    bt_mesh_set_ble_adv_running();
+
+    return 0;
+}
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
 int bt_mesh_ble_adv_start(const struct bt_mesh_ble_adv_param *param,
                           const struct bt_mesh_ble_adv_data *data)
 {
@@ -468,8 +948,32 @@ int bt_mesh_ble_adv_start(const struct bt_mesh_ble_adv_param *param,
 
     return 0;
 }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 #endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+int bt_le_ext_adv_stop(uint8_t inst_id)
+{
+    tBTA_DM_BLE_EXT_ADV ext_adv = {0};
+
+#if BLE_MESH_DEV
+    bt_mesh_atomic_clear_bit(bt_mesh_dev.flags, BLE_MESH_DEV_KEEP_ADVERTISING);
+    if (!bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING)) {
+        return 0;
+    }
+#endif
+
+    ext_adv.instance = inst_id;
+
+    BTA_DmBleGapExtAdvEnable(false, 1, &ext_adv);
+
+#if BLE_MESH_DEV
+    bt_mesh_atomic_clear_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING);
+#endif
+
+    return 0;
+}
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
 int bt_le_adv_stop(void)
 {
 #if BLE_MESH_DEV
@@ -487,6 +991,7 @@ int bt_le_adv_stop(void)
 
     return 0;
 }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 int bt_le_scan_start(const struct bt_mesh_scan_param *param, bt_mesh_scan_cb_t cb)
 {
@@ -528,7 +1033,11 @@ int bt_le_scan_stop(void)
         return -EALREADY;
     }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    BTA_DmBleGapExtScan(false, 0 ,0);
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
     BLE_MESH_BTM_CHECK_STATUS(BTM_BleScan(false, 0, NULL, NULL, NULL));
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
     bt_mesh_atomic_clear_bit(bt_mesh_dev.flags, BLE_MESH_DEV_SCANNING);
     bt_mesh_scan_dev_found_cb = NULL;
@@ -1196,6 +1705,9 @@ uint16_t bt_mesh_gattc_get_service_uuid(struct bt_mesh_conn *conn)
 
 int bt_mesh_gattc_conn_create(const bt_mesh_addr_t *addr, uint16_t service_uuid)
 {
+#if CONFIG_BLE_MESH_USE_BLE_50
+    tBTA_DM_BLE_CONN_PARAMS  conn_1m_param = {0};
+#endif
     uint8_t zero[6] = {0};
     int i;
 
@@ -1238,21 +1750,47 @@ int bt_mesh_gattc_conn_create(const bt_mesh_addr_t *addr, uint16_t service_uuid)
     }
 
     if (bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_SCANNING)) {
+#if CONFIG_BLE_MESH_USE_BLE_50
+        BTA_DmBleGapExtScan(false, 0 ,0);
+#else
         BLE_MESH_BTM_CHECK_STATUS(BTM_BleScan(false, 0, NULL, NULL, NULL));
+#endif
         bt_mesh_atomic_clear_bit(bt_mesh_dev.flags, BLE_MESH_DEV_SCANNING);
     }
 
     BT_DBG("Create conn with %s", bt_hex(addr->val, BLE_MESH_ADDR_LEN));
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    /* Min_interval: 15ms  0x18, 0x18, 0x00, 0x64
+     * Max_interval: 15ms
+     * Slave_latency: 0x0
+     * Supervision_timeout: 1s
+     */
+    conn_1m_param.scan_interval = 0x0020;
+    conn_1m_param.scan_window   = 0x0020;
+    conn_1m_param.interval_min  = 0x18;
+    conn_1m_param.interval_max  = 0x18;
+    conn_1m_param.latency       = 0;
+    conn_1m_param.supervision_timeout = 0x64;
+    conn_1m_param.min_ce_len = 0;
+    conn_1m_param.max_ce_len = 0;
+
+    BTA_DmBleGapPreferExtConnectParamsSet(bt_mesh_gattc_info[i].addr.val, 0x01, &conn_1m_param ,NULL, NULL);
+
+    BTA_GATTC_Open(bt_mesh_gattc_if, bt_mesh_gattc_info[i].addr.val,
+                   bt_mesh_gattc_info[i].addr.type, true, BTA_GATT_TRANSPORT_LE, TRUE);
+#else
     /* Min_interval: 15ms
      * Max_interval: 15ms
      * Slave_latency: 0x0
      * Supervision_timeout: 1s
      */
+
     BTA_DmSetBlePrefConnParams(bt_mesh_gattc_info[i].addr.val, 0x18, 0x18, 0x00, 0x64);
 
     BTA_GATTC_Open(bt_mesh_gattc_if, bt_mesh_gattc_info[i].addr.val,
                    bt_mesh_gattc_info[i].addr.type, true, BTA_GATT_TRANSPORT_LE, FALSE);
+#endif
 
     return 0;
 }
@@ -1653,11 +2191,15 @@ static void bt_mesh_bta_gattc_cb(tBTA_GATTC_EVT event, tBTA_GATTC *p_data)
          * use BTM_BleScan() to re-enable scan.
          */
         if (!bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_SCANNING)) {
+#if CONFIG_BLE_MESH_USE_BLE_50
+            BTA_DmBleGapExtScan(true, 0 ,0);
+#else
             tBTM_STATUS status = BTM_BleScan(true, 0, bt_mesh_scan_results_cb, NULL, NULL);
             if (status != BTM_SUCCESS && status != BTM_CMD_STARTED) {
                 BT_ERR("Invalid scan status %d", status);
                 break;
             }
+#endif
             bt_mesh_atomic_set_bit(bt_mesh_dev.flags, BLE_MESH_DEV_SCANNING);
         }
         break;
diff --git a/components/bt/esp_ble_mesh/core/cfg_srv.c b/components/bt/esp_ble_mesh/core/cfg_srv.c
index 9d91cb217b3..a8fe1af424d 100644
--- a/components/bt/esp_ble_mesh/core/cfg_srv.c
+++ b/components/bt/esp_ble_mesh/core/cfg_srv.c
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,7 +30,9 @@
 #include "mesh/common.h"
 #include "heartbeat.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #define DEFAULT_TTL         7
 
@@ -38,6 +40,158 @@ static struct bt_mesh_cfg_srv *conf;
 
 static struct label labels[CONFIG_BLE_MESH_LABEL_COUNT];
 
+#if !CONFIG_BLE_MESH_V11_SUPPORT
+const void *comp_0;
+
+static uint8_t bt_mesh_comp_page_check(uint8_t page, bool largest)
+{
+    /* If the page doesn't exist, TWO situations currently:
+     * 1. For Composition Data Get:
+     *    With the Page field set to the largest page number of
+     *    the Composition Data that the node supports and that is
+     *    less than the Page field value of the received Config
+     *    Composition Data Get message;
+     * 2. For Large Composition Data Get:
+     *    The Page field shall be set to the largest page number
+     *    of the Composition Data that the node supports.
+     */
+    ARG_UNUSED(largest);
+
+    if (page != 0) {
+        BT_WARN("Composition Data Page %d not exists", page);
+    }
+
+    return 0;
+}
+
+static inline uint16_t get_comp_elem_size(struct bt_mesh_elem *elem)
+{
+    return (4 + elem->model_count * 2 + elem->vnd_model_count * 4);
+}
+
+static uint16_t get_comp_data_size(const struct bt_mesh_comp *comp)
+{
+    uint16_t size = 10; /* CID + PID + VID + CRPL + Features */
+
+    for (int i = 0; i < comp->elem_count; i++) {
+        size += get_comp_elem_size(&(comp->elem[i]));
+    }
+
+    return size;
+}
+
+static void get_comp_data(struct net_buf_simple *buf,
+                          const struct bt_mesh_comp *comp,
+                          bool full_element)
+{
+    struct bt_mesh_model *model = NULL;
+    struct bt_mesh_elem *elem = NULL;
+    uint16_t feat = 0;
+
+    if (IS_ENABLED(CONFIG_BLE_MESH_RELAY)) {
+        feat |= BLE_MESH_FEAT_RELAY;
+    }
+
+    if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER)) {
+        feat |= BLE_MESH_FEAT_PROXY;
+    }
+
+    if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND)) {
+        feat |= BLE_MESH_FEAT_FRIEND;
+    }
+
+    if (IS_ENABLED(CONFIG_BLE_MESH_LOW_POWER)) {
+        feat |= BLE_MESH_FEAT_LOW_POWER;
+    }
+
+    net_buf_simple_add_le16(buf, comp->cid);
+    net_buf_simple_add_le16(buf, comp->pid);
+    net_buf_simple_add_le16(buf, comp->vid);
+    net_buf_simple_add_le16(buf, CONFIG_BLE_MESH_CRPL);
+    net_buf_simple_add_le16(buf, feat);
+
+    for (size_t i = 0; i < comp->elem_count; i++) {
+        elem = &(comp->elem[i]);
+
+        /* If "full_element" is true, which means the complete list
+         * of models within the element needs to fit in the data,
+         * otherwise the element shall not be reported.
+         */
+        if (full_element &&
+            net_buf_simple_tailroom(buf) < get_comp_elem_size(elem)) {
+            return;
+        }
+
+        net_buf_simple_add_le16(buf, elem->loc);
+        net_buf_simple_add_u8(buf, elem->model_count);
+        net_buf_simple_add_u8(buf, elem->vnd_model_count);
+
+        for (size_t j = 0; j < elem->model_count; j++) {
+            model = &(elem->models[j]);
+            net_buf_simple_add_le16(buf, model->id);
+        }
+
+        for (size_t j = 0; j < elem->vnd_model_count; j++) {
+            model = &(elem->vnd_models[j]);
+            net_buf_simple_add_le16(buf, model->vnd.company);
+            net_buf_simple_add_le16(buf, model->vnd.id);
+        }
+    }
+}
+
+static int fetch_comp_data(struct net_buf_simple *buf,
+                           const struct bt_mesh_comp *comp,
+                           uint8_t page, uint16_t offset,
+                           bool full_element)
+{
+    uint16_t size = get_comp_data_size(comp);
+
+    if (offset >= size) {
+        BT_WARN("Too large offset %d for comp data %d, size %d",
+                page, offset, size);
+        return 0;
+    }
+
+    if (net_buf_simple_tailroom(buf) < 10 ||
+        size - offset > net_buf_simple_tailroom(buf)) {
+        BT_ERR("Too small buffer for comp data %d, %d, expected %d",
+                page, buf->size, size - offset);
+        return -EINVAL;
+    }
+
+    if (offset) {
+        struct net_buf_simple *pdu = bt_mesh_alloc_buf(size);
+        if (pdu == NULL) {
+            BT_ERR("%s, Out of memory", __func__);
+            return -ENOMEM;
+        }
+
+        get_comp_data(pdu, comp, false);
+
+        /* Get part of Composition Data Page 0/128 */
+        net_buf_simple_add_mem(buf, pdu->data + offset, pdu->len - offset);
+
+        bt_mesh_free_buf(pdu);
+    } else {
+        get_comp_data(buf, comp, full_element);
+    }
+
+    return 0;
+}
+
+static int bt_mesh_get_comp_data(struct net_buf_simple *buf,
+                                 uint8_t page, uint16_t offset,
+                                 bool full_element)
+{
+    if (page == 0) {
+        return fetch_comp_data(buf, comp_0, page, offset, full_element);
+    }
+
+    BT_ERR("Invalid Composition Data Page %d", page);
+    return -EINVAL;
+}
+#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */
+
 static void comp_data_get(struct bt_mesh_model *model,
                           struct bt_mesh_msg_ctx *ctx,
                           struct net_buf_simple *buf)
@@ -2758,7 +2912,7 @@ static void node_reset(struct bt_mesh_model *model,
 
     bt_mesh_model_msg_init(&msg, OP_NODE_RESET_STATUS);
 
-    /* Send the response first since we wont have any keys left to
+    /* Send the response first since we won't have any keys left to
      * send it later.
      */
     if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) {
diff --git a/components/bt/esp_ble_mesh/core/crypto.c b/components/bt/esp_ble_mesh/core/crypto.c
index 9b762fb5ed3..2577c65efba 100644
--- a/components/bt/esp_ble_mesh/core/crypto.c
+++ b/components/bt/esp_ble_mesh/core/crypto.c
@@ -22,7 +22,9 @@
 #include "mesh/common.h"
 #include "mesh/adapter.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #define NET_MIC_LEN(pdu) (((pdu)[1] & 0x80) ? 8 : 4)
 #define APP_MIC_LEN(aszmic) ((aszmic) ? 8 : 4)
diff --git a/components/bt/esp_ble_mesh/core/friend.c b/components/bt/esp_ble_mesh/core/friend.c
index b1a298d5a97..aa9607492b2 100644
--- a/components/bt/esp_ble_mesh/core/friend.c
+++ b/components/bt/esp_ble_mesh/core/friend.c
@@ -21,7 +21,9 @@
 #include "mesh/common.h"
 #include "pvnr_mgmt.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #ifdef CONFIG_BLE_MESH_FRIEND
 
diff --git a/components/bt/esp_ble_mesh/core/include/mesh/access.h b/components/bt/esp_ble_mesh/core/include/mesh/access.h
index 86731036516..9d013baa0d4 100644
--- a/components/bt/esp_ble_mesh/core/include/mesh/access.h
+++ b/components/bt/esp_ble_mesh/core/include/mesh/access.h
@@ -4,7 +4,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/bt/esp_ble_mesh/core/include/mesh/adapter.h b/components/bt/esp_ble_mesh/core/include/mesh/adapter.h
index 1cb239a3cac..4f28c0d6844 100644
--- a/components/bt/esp_ble_mesh/core/include/mesh/adapter.h
+++ b/components/bt/esp_ble_mesh/core/include/mesh/adapter.h
@@ -1,7 +1,7 @@
 /*
  * SPDX-FileCopyrightText: 2017 Nordic Semiconductor ASA
  * SPDX-FileCopyrightText: 2015-2017 Intel Corporation
- * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,6 +33,18 @@ extern "C" {
 
 #define BLE_MESH_GATT_DEF_MTU_SIZE  23
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+#define BLE_MESH_ADV_PHY_UNASSIGNED                                 0
+#define BLE_MESH_ADV_PHY_1M                                         1
+#define BLE_MESH_ADV_PHY_2M                                         2
+#define BLE_MESH_ADV_PHY_CODED                                      3
+#define BLE_MESH_ADV_PHY_OPTION_NO_PREFER                           0
+#define BLE_MESH_ADV_PHY_OPTION_PREFER_S2                           1
+#define BLE_MESH_ADV_PHY_OPTION_PREFER_S8                           2
+#define BLE_MESH_ADV_PHY_OPTION_REQUIRE_S2                          3
+#define BLE_MESH_ADV_PHY_OPTION_REQUIRE_S8                          4
+#endif
+
 /* BD ADDR types */
 #define BLE_MESH_ADDR_PUBLIC         0x00
 #define BLE_MESH_ADDR_RANDOM         0x01
@@ -43,11 +55,22 @@ extern "C" {
 #define BLE_MESH_ADDR_LEN                   0x06
 
 /* Advertising types */
+#if !CONFIG_BLE_MESH_USE_BLE_50
 #define BLE_MESH_ADV_IND                    0x00
 #define BLE_MESH_ADV_DIRECT_IND             0x01
 #define BLE_MESH_ADV_SCAN_IND               0x02
 #define BLE_MESH_ADV_NONCONN_IND            0x03
 #define BLE_MESH_ADV_DIRECT_IND_LOW_DUTY    0x04
+#define BLE_MESH_ADV_SCAN_RSP               0x04
+#else
+/* Bluetooth Core Spec 6.0, Vol 4, Part E, 7.7.65.13 */
+#define BLE_MESH_ADV_IND                   (0x13)
+#define BLE_MESH_ADV_DIRECT_IND            (0x15)
+#define BLE_MESH_ADV_SCAN_IND              (0x12)
+#define BLE_MESH_ADV_NONCONN_IND           (0x10)
+#define BLE_MESH_ADV_DIRECT_IND_LOW_DUTY   (0x1b)
+#define BLE_MESH_ADV_SCAN_RSP              (0x1b)
+#endif
 
 /* advertising channel map */
 #define BLE_MESH_ADV_CHNL_37                BIT(0)
@@ -400,7 +423,31 @@ struct bt_mesh_adv_param {
 
     /** Maximum Advertising Interval (N * 0.625) */
     uint16_t interval_max;
+
+#if CONFIG_BLE_MESH_USE_BLE_50
+    /** Maximum Advertising Duration (N * 0.625) */
+    uint16_t adv_duration;
+
+    /** Advertising Packages Number */
+    uint16_t adv_count;
+
+    /** Advertising Primary PHY */
+    uint8_t primary_phy;
+
+    /** Advertising Secondary PHY */
+    uint8_t secondary_phy;
+#endif
+};
+
+#if CONFIG_BLE_MESH_USE_BLE_50
+enum bt_mesh_adv_inst_type {
+    BLE_MESH_ADV_PROXY_INS,
+    BLE_MESH_ADV_INS,
+    BLE_MESH_EXT_ADV_INS,
+    BLE_MESH_BLE_ADV_INS,
+    BLE_MESH_ADV_INS_TYPE_NUMS,
 };
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
 enum bt_mesh_ble_adv_priority {
@@ -441,7 +488,7 @@ struct bt_mesh_scan_param {
     /** Scan interval (N * 0.625 ms) */
     uint16_t interval;
 
-    /** Scan window (N * 0.625 ms) */
+    /** Uncoded phy Scan window (N * 0.625 ms) */
     uint16_t window;
 
     /** BLE scan filter policy */
@@ -453,21 +500,38 @@ struct bt_mesh_conn {
     bt_mesh_atomic_t ref;
 };
 
+/* BLE Mesh advertising report  */
+struct bt_mesh_adv_report {
+    /* Advertiser LE address and type. */
+    bt_mesh_addr_t addr;
+
+    /* Strength of advertiser signal. */
+    int8_t rssi;
+
+    /* Type of advertising response from advertiser. */
+    uint8_t adv_type;
+
+    /* Buffer containing advertiser data. */
+    struct net_buf_simple adv_data;
+
+#if CONFIG_BLE_MESH_USE_BLE_50
+    /* Primary advertising PHY */
+    uint8_t primary_phy;
+
+    /* Secondary advertising PHY */
+    uint8_t secondary_phy;
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+};
+
 /** @typedef bt_mesh_scan_cb_t
  *  @brief Callback type for reporting LE scan results.
  *
  *  A function of this type is given to the bt_le_scan_start() function
  *  and will be called for any discovered LE device.
  *
- *  @param addr Advertiser LE address and type.
- *  @param rssi Strength of advertiser signal.
- *  @param adv_type Type of advertising response from advertiser.
- *  @param data Buffer containing advertiser data.
- *  @param scan_rsp_len Scan Response data length.
+ *  @param adv_rpt: BLE Mesh advertising report.
  */
-typedef void bt_mesh_scan_cb_t(const bt_mesh_addr_t *addr, int8_t rssi,
-                               uint8_t adv_type, struct net_buf_simple *buf,
-                               uint8_t scan_rsp_len);
+typedef void bt_mesh_scan_cb_t(struct bt_mesh_adv_report *adv_rpt);
 
 /*  @typedef bt_mesh_dh_key_cb_t
  *  @brief Callback type for DH Key calculation.
@@ -553,7 +617,7 @@ struct bt_mesh_gatt_attr {
      *  @param len    Length of data to read
      *  @param offset Offset to start reading from
      *
-     *  @return Number fo bytes read, or in case of an error
+     *  @return Number of bytes read, or in case of an error
      *          BLE_MESH_GATT_ERR() with a specific ATT error code.
      */
     ssize_t (*read)(struct bt_mesh_conn *conn,
@@ -684,6 +748,21 @@ struct bt_mesh_gatt_attr {
 int bt_mesh_host_init(void);
 int bt_mesh_host_deinit(void);
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+int bt_le_ext_adv_start(const uint8_t inst_id,
+                        const struct bt_mesh_adv_param *param,
+                        const struct bt_mesh_adv_data *ad, size_t ad_len,
+                        const struct bt_mesh_adv_data *sd, size_t sd_len);
+
+#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
+int bt_mesh_ble_ext_adv_start(const uint8_t inst_id,
+                              const struct bt_mesh_ble_adv_param *param,
+                              const struct bt_mesh_ble_adv_data *adv_data);
+#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */
+
+int bt_le_ext_adv_stop(uint8_t inst_id);
+
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
 int bt_le_adv_start(const struct bt_mesh_adv_param *param,
                     const struct bt_mesh_adv_data *ad, size_t ad_len,
                     const struct bt_mesh_adv_data *sd, size_t sd_len);
@@ -691,9 +770,10 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param,
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
 int bt_mesh_ble_adv_start(const struct bt_mesh_ble_adv_param *param,
                           const struct bt_mesh_ble_adv_data *data);
-#endif
+#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */
 
 int bt_le_adv_stop(void);
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 int bt_le_scan_start(const struct bt_mesh_scan_param *param, bt_mesh_scan_cb_t cb);
 
diff --git a/components/bt/esp_ble_mesh/core/lpn.c b/components/bt/esp_ble_mesh/core/lpn.c
index f445be5632c..80f5b4321af 100644
--- a/components/bt/esp_ble_mesh/core/lpn.c
+++ b/components/bt/esp_ble_mesh/core/lpn.c
@@ -10,6 +10,7 @@
 #include <errno.h>
 
 #include "crypto.h"
+#include "tag.h"
 #include "adv.h"
 #include "scan.h"
 #include "mesh.h"
@@ -23,7 +24,9 @@
 #include "mesh/cfg_srv.h"
 #include "heartbeat.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #ifdef CONFIG_BLE_MESH_LOW_POWER
 
diff --git a/components/bt/esp_ble_mesh/core/main.c b/components/bt/esp_ble_mesh/core/main.c
index ad94e2c88b2..94a43c19b14 100644
--- a/components/bt/esp_ble_mesh/core/main.c
+++ b/components/bt/esp_ble_mesh/core/main.c
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,7 +30,9 @@
 #include "prov_pvnr.h"
 #include "pvnr_mgmt.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 static bool mesh_init = false;
 
@@ -161,9 +163,9 @@ void bt_mesh_node_reset(void)
         bt_mesh_clear_seq();
         bt_mesh_clear_dkca();
         bt_mesh_clear_role();
-        if (IS_ENABLED(CONFIG_BLE_MESH_DF_SRV)) {
-            bt_mesh_clear_all_directed_forwarding_table_data();
-        }
+#if CONFIG_BLE_MESH_DF_SRV
+        bt_mesh_clear_all_directed_forwarding_table_data();
+#endif
     }
 
     memset(bt_mesh.flags, 0, sizeof(bt_mesh.flags));
@@ -405,12 +407,14 @@ int bt_mesh_init(const struct bt_mesh_prov *prov,
         return -EALREADY;
     }
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
     extern int bt_mesh_v11_ext_init(void);
     err = bt_mesh_v11_ext_init();
     if (err) {
         BT_ERR("Bluetooth Mesh v1.1 init failed");
         return err;
     }
+#endif
 
     bt_mesh_mutex_init();
 
diff --git a/components/bt/esp_ble_mesh/core/mesh.h b/components/bt/esp_ble_mesh/core/mesh.h
index c9392240696..127844790fb 100644
--- a/components/bt/esp_ble_mesh/core/mesh.h
+++ b/components/bt/esp_ble_mesh/core/mesh.h
@@ -11,6 +11,7 @@
 #define _MESH_H_
 
 #include "net.h"
+#include "tag.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/bt/esp_ble_mesh/core/net.c b/components/bt/esp_ble_mesh/core/net.c
index d5b768c7d22..43f0af24875 100644
--- a/components/bt/esp_ble_mesh/core/net.c
+++ b/components/bt/esp_ble_mesh/core/net.c
@@ -13,6 +13,7 @@
 
 #include "crypto.h"
 #include "adv.h"
+#include "net.h"
 #include "scan.h"
 #include "mesh.h"
 #include "lpn.h"
@@ -31,7 +32,9 @@
 #include "proxy_server.h"
 #include "pvnr_mgmt.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 /* Minimum valid Mesh Network PDU length. The Network headers
  * themselves take up 9 bytes. After that there is a minimum of 1 byte
@@ -1019,6 +1022,33 @@ int bt_mesh_net_encode(struct bt_mesh_net_tx *tx, struct net_buf_simple *buf,
     return bt_mesh_net_obfuscate(buf->data, BLE_MESH_NET_IVI_TX, priv);
 }
 
+#if !CONFIG_BLE_MESH_V11_SUPPORT
+static void bt_mesh_net_adv_xmit_update(struct bt_mesh_net_tx *tx)
+{
+    /* When transmitting a Network PDU that is tagged as friendship,
+     * the Advertising Bearer Network Interface shall transmit the
+     * Network PDU over the advertising bearer only once.
+     *
+     * Note: Currently when transmitting a packet with the friendship
+     * credentials used, the message flow will not reach here. It
+     * will be enqueued into the friend queue in transport.c, and
+     * waited to be sent.
+     */
+    if (bt_mesh_tag_friendship(tx->ctx->send_tag)) {
+        tx->xmit = BLE_MESH_TRANSMIT(0, BLE_MESH_TRANSMIT_INT(bt_mesh_net_transmit_get()));
+        return;
+    }
+
+    if (bt_mesh_tag_relay(tx->ctx->send_tag)) {
+        tx->xmit = bt_mesh_relay_retransmit_get();
+    } else {
+        tx->xmit = bt_mesh_net_transmit_get();
+    }
+
+    return;
+}
+#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */
+
 int bt_mesh_net_send(struct bt_mesh_net_tx *tx, struct net_buf *buf,
                      const struct bt_mesh_send_cb *cb, void *cb_data)
 {
@@ -1094,6 +1124,15 @@ int bt_mesh_net_send(struct bt_mesh_net_tx *tx, struct net_buf *buf,
         tx->ctx->send_cred != BLE_MESH_FRIENDSHIP_CRED) {
         if (bt_mesh_proxy_server_relay(&buf->b, tx->ctx->addr) &&
             BLE_MESH_ADDR_IS_UNICAST(tx->ctx->addr)) {
+            /**
+             * When a message is sent to a proxy client, the message
+             * can be sent via GATT only, eliminating the need for
+             * an ADV bearer.
+             */
+            if (bt_mesh_proxy_server_find_client_by_addr(tx->ctx->addr)) {
+                bearer &= ~BLE_MESH_ADV_BEARER;
+            }
+
             /* Notify completion if this only went
              * through the Mesh Proxy.
              */
@@ -1418,13 +1457,94 @@ static bool relay_to_adv(enum bt_mesh_net_if net_if)
     case BLE_MESH_NET_IF_ADV:
         return (bt_mesh_relay_get() == BLE_MESH_RELAY_ENABLED);
     case BLE_MESH_NET_IF_PROXY:
-        return (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED ||
-                bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED);
+        return (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED
+#if CONFIG_BLE_MESH_PRB_SRV
+                || bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED
+#endif
+                );
     default:
         return false;
     }
 }
 
+#if !CONFIG_BLE_MESH_V11_SUPPORT
+static uint8_t net_retransmission_adv(struct bt_mesh_net_rx *rx,
+                                      uint8_t *cred, uint8_t *tag)
+{
+    if (rx->ctx.recv_cred == BLE_MESH_FLOODING_CRED) {
+        uint8_t bearer = BLE_MESH_NONE_BEARER;
+
+        /* Inbound bearer: ADV;
+         * Inbound Security Material: managed flooding;
+         */
+
+        /* Condition: Relay is enabled. */
+        if (IS_ENABLED(CONFIG_BLE_MESH_RELAY) &&
+            bt_mesh_relay_get() == BLE_MESH_RELAY_ENABLED) {
+            bearer |= BLE_MESH_ADV_BEARER;
+            *cred = BLE_MESH_FLOODING_CRED;
+            /* Additional action: Tag as relay */
+            *tag |= BLE_MESH_TAG_RELAY;
+        }
+
+        /* Condition: Proxy is enabled. */
+        if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) &&
+            bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED) {
+            bearer |= BLE_MESH_GATT_BEARER;
+            *cred = BLE_MESH_FLOODING_CRED;
+        }
+
+        return bearer;
+    }
+
+    if (rx->ctx.recv_cred == BLE_MESH_FRIENDSHIP_CRED &&
+        IS_ENABLED(CONFIG_BLE_MESH_FRIEND) &&
+        bt_mesh_friend_get() == BLE_MESH_FRIEND_ENABLED) {
+
+        /* Condition: Directed friend is disabled. */
+        *cred = BLE_MESH_FLOODING_CRED;
+        return BLE_MESH_ALL_BEARERS;
+    }
+
+    return BLE_MESH_NONE_BEARER;
+}
+
+static uint8_t net_retransmission_gatt(struct bt_mesh_net_rx *rx,
+                                       uint8_t *cred, uint8_t *tag)
+{
+    if (rx->ctx.recv_cred == BLE_MESH_FLOODING_CRED) {
+        /* Inbound bearer: GATT;
+         * Inbound Security Material: managed flooding;
+         * Condition: Proxy is enabled;
+         */
+        if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) &&
+            bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED) {
+            /* Condition: Directed proxy is disabled. */
+            *cred = BLE_MESH_FLOODING_CRED;
+            return BLE_MESH_ALL_BEARERS;
+        }
+
+        return BLE_MESH_NONE_BEARER;
+    }
+
+    return BLE_MESH_NONE_BEARER;
+}
+
+static uint8_t bt_mesh_net_retrans_match(struct bt_mesh_net_rx *rx,
+                                         uint8_t *cred, uint8_t *tag)
+{
+    if (rx->net_if == BLE_MESH_NET_IF_ADV) {
+        return net_retransmission_adv(rx, cred, tag);
+    }
+
+    if (rx->net_if == BLE_MESH_NET_IF_PROXY) {
+        return net_retransmission_gatt(rx, cred, tag);
+    }
+
+    return BLE_MESH_NONE_BEARER;
+}
+#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */
+
 static void bt_mesh_net_relay(struct net_buf_simple *sbuf,
                               struct bt_mesh_net_rx *rx)
 {
@@ -1621,7 +1741,9 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf,
         (bearer & BLE_MESH_GATT_BEARER) &&
         ((bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_ENABLED &&
           cred != BLE_MESH_FRIENDSHIP_CRED) ||
+#if CONFIG_BLE_MESH_PRB_SRV
          bt_mesh_private_gatt_proxy_state_get() == BLE_MESH_PRIVATE_GATT_PROXY_ENABLED ||
+#endif
          rx->net_if == BLE_MESH_NET_IF_LOCAL ||
          rx->ctx.recv_cred == BLE_MESH_FRIENDSHIP_CRED)) {
         if (bt_mesh_proxy_server_relay(&buf->b, rx->ctx.recv_dst) &&
@@ -1780,24 +1902,26 @@ static bool ignore_net_msg(uint16_t src, uint16_t dst)
     return false;
 }
 
-void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi,
-                      enum bt_mesh_net_if net_if)
+void bt_mesh_generic_net_recv(struct net_buf_simple *data,
+                              struct bt_mesh_net_rx *rx,
+                              enum bt_mesh_net_if net_if)
 {
     NET_BUF_SIMPLE_DEFINE(buf, 29);
-    struct bt_mesh_net_rx rx = { .ctx.recv_rssi = rssi };
     struct net_buf_simple_state state = {0};
 
-    BT_DBG("rssi %d net_if %u", rssi, net_if);
+    assert(rx);
+
+    BT_DBG("rssi %d net_if %u", rx->ctx.recv_rssi, net_if);
 
     if (!ready_to_recv()) {
         return;
     }
 
-    if (bt_mesh_net_decode(data, net_if, &rx, &buf)) {
+    if (bt_mesh_net_decode(data, net_if, rx, &buf)) {
         return;
     }
 
-    if (ignore_net_msg(rx.ctx.addr, rx.ctx.recv_dst)) {
+    if (ignore_net_msg(rx->ctx.addr, rx->ctx.recv_dst)) {
         return;
     }
 
@@ -1807,24 +1931,26 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi,
     BT_BQB(BLE_MESH_BQB_TEST_LOG_LEVEL_PRIMARY_ID_NODE | \
            BLE_MESH_BQB_TEST_LOG_LEVEL_SUB_ID_NET,
            "\nNetRecv: ctl: %d, src: %d, dst: %d, ttl: %d, data: 0x%s",
-           rx.ctl, rx.ctx.addr, rx.ctx.recv_dst, rx.ctx.recv_ttl,
+           rx->ctl, rx->ctx.addr, rx->ctx.recv_dst, rx->ctx.recv_ttl,
            bt_hex(buf.data + BLE_MESH_NET_HDR_LEN, buf.len - BLE_MESH_NET_HDR_LEN));
 
     /* If trying to handle a message with DST set to all-directed-forwarding-nodes,
      * we need to make sure the directed forwarding functionality is enabled in the
      * corresponding subnet.
      */
-    rx.local_match = (bt_mesh_fixed_group_match(rx.ctx.recv_dst) ||
-                      bt_mesh_fixed_direct_match(rx.sub, rx.ctx.recv_dst) ||
-                      bt_mesh_elem_find(rx.ctx.recv_dst));
+    rx->local_match = (bt_mesh_fixed_group_match(rx->ctx.recv_dst) ||
+                      bt_mesh_fixed_direct_match(rx->sub, rx->ctx.recv_dst) ||
+                      bt_mesh_elem_find(rx->ctx.recv_dst));
 
     if (IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) &&
+#if CONFIG_BLE_MESH_PRB_SRV
         bt_mesh_private_gatt_proxy_state_get() != BLE_MESH_PRIVATE_GATT_PROXY_ENABLED &&
+#endif
         net_if == BLE_MESH_NET_IF_PROXY) {
-        bt_mesh_proxy_server_addr_add(data, rx.ctx.addr);
+        bt_mesh_proxy_server_addr_add(data, rx->ctx.addr);
 
         if (bt_mesh_gatt_proxy_get() == BLE_MESH_GATT_PROXY_DISABLED &&
-            !rx.local_match) {
+            !rx->local_match) {
             BT_INFO("Proxy is disabled; ignoring message");
             return;
         }
@@ -1837,11 +1963,11 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi,
          * tag the Network PDU with the immutable-credentials tag.
          */
 #if CONFIG_BLE_MESH_DF_SRV
-        if (rx.sub->directed_proxy == BLE_MESH_DIRECTED_PROXY_ENABLED &&
-            rx.sub->use_directed == BLE_MESH_PROXY_USE_DIRECTED_ENABLED &&
-            !bt_mesh_addr_in_uar(&rx.sub->proxy_client_uar, rx.ctx.addr) &&
-            !bt_mesh_proxy_server_find_client_by_addr(rx.ctx.addr)) {
-            rx.ctx.recv_tag |= BLE_MESH_TAG_IMMUTABLE_CRED;
+        if (rx->sub->directed_proxy == BLE_MESH_DIRECTED_PROXY_ENABLED &&
+            rx->sub->use_directed == BLE_MESH_PROXY_USE_DIRECTED_ENABLED &&
+            !bt_mesh_addr_in_uar(&rx->sub->proxy_client_uar, rx->ctx.addr) &&
+            !bt_mesh_proxy_server_find_client_by_addr(rx->ctx.addr)) {
+            rx->ctx.recv_tag |= BLE_MESH_TAG_IMMUTABLE_CRED;
         }
 #endif /* CONFIG_BLE_MESH_DF_SRV */
     }
@@ -1853,24 +1979,24 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi,
     * credentials. Remove it from the message cache so that we accept
     * it again in the future.
     */
-    if (bt_mesh_trans_recv(&buf, &rx) == -EAGAIN) {
+    if (bt_mesh_trans_recv(&buf, rx) == -EAGAIN) {
         BT_WARN("Removing rejected message from Network Message Cache");
-        msg_cache[rx.msg_cache_idx].src = BLE_MESH_ADDR_UNASSIGNED;
+        msg_cache[rx->msg_cache_idx].src = BLE_MESH_ADDR_UNASSIGNED;
         /* Rewind the next index now that we're not using this entry */
-        msg_cache_next = rx.msg_cache_idx;
+        msg_cache_next = rx->msg_cache_idx;
     }
 
     /* Relay if this was a group/virtual address, or if the destination
      * was neither a local element nor an LPN we're Friends for.
      */
-    if (!BLE_MESH_ADDR_IS_UNICAST(rx.ctx.recv_dst) ||
-        (!rx.local_match && !rx.friend_match
+    if (!BLE_MESH_ADDR_IS_UNICAST(rx->ctx.recv_dst) ||
+        (!rx->local_match && !rx->friend_match
 #if CONFIG_BLE_MESH_NOT_RELAY_REPLAY_MSG
-        && !rx.replay_msg
+        && !rx->replay_msg
 #endif
         )) {
         net_buf_simple_restore(&buf, &state);
-        bt_mesh_net_relay(&buf, &rx);
+        bt_mesh_net_relay(&buf, rx);
     }
 }
 
diff --git a/components/bt/esp_ble_mesh/core/net.h b/components/bt/esp_ble_mesh/core/net.h
index 7da8c4a0782..94e07819170 100644
--- a/components/bt/esp_ble_mesh/core/net.h
+++ b/components/bt/esp_ble_mesh/core/net.h
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -465,8 +465,16 @@ int bt_mesh_net_resend(struct bt_mesh_subnet *sub, struct net_buf *buf,
 int bt_mesh_net_decode(struct net_buf_simple *data, enum bt_mesh_net_if net_if,
                        struct bt_mesh_net_rx *rx, struct net_buf_simple *buf);
 
-void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi,
-                      enum bt_mesh_net_if net_if);
+void bt_mesh_generic_net_recv(struct net_buf_simple *data,
+                              struct bt_mesh_net_rx *rx,
+                              enum bt_mesh_net_if net_if);
+
+static inline void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi,
+                                    enum bt_mesh_net_if net_if)
+{
+    struct bt_mesh_net_rx rx = { .ctx.recv_rssi = rssi };
+    bt_mesh_generic_net_recv(data, &rx, net_if);
+}
 
 bool bt_mesh_primary_subnet_exist(void);
 
diff --git a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c
index fcad7200599..2dd97770011 100644
--- a/components/bt/esp_ble_mesh/core/nimble_host/adapter.c
+++ b/components/bt/esp_ble_mesh/core/nimble_host/adapter.c
@@ -1,7 +1,7 @@
 /*
  * SPDX-FileCopyrightText: 2017 Nordic Semiconductor ASA
  * SPDX-FileCopyrightText: 2015-2016 Intel Corporation
- * SPDX-FileContributor: 2018-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,6 +27,8 @@
 #include "mesh/hci.h"
 #include "mesh/common.h"
 #include "prov_pvnr.h"
+#include "scan.h"
+#include "btc_ble_mesh_ble.h"
 
 /** @def BT_UUID_MESH_PROV
  *  @brief Mesh Provisioning Service
@@ -69,7 +71,6 @@ static uint8_t bt_mesh_private_key[32];
 
 /* Scan related functions */
 static bt_mesh_scan_cb_t *bt_mesh_scan_dev_found_cb;
-
 #if CONFIG_BLE_MESH_NODE
 /* the gatt database list to save the attribute table */
 static sys_slist_t bt_mesh_gatts_db;
@@ -79,10 +80,57 @@ static struct bt_mesh_conn bt_mesh_gatts_conn[BLE_MESH_MAX_CONN];
 static struct bt_mesh_conn_cb *bt_mesh_gatts_conn_cb;
 
 static uint8_t bt_mesh_gatts_addr[6];
+
+#if CONFIG_BLE_MESH_USE_BLE_50
+static bool g_gatts_svcs_add = false;
+#endif
 #endif /* CONFIG_BLE_MESH_NODE */
 
+#if CONFIG_BLE_MESH_USE_BLE_50 && CONFIG_BLE_MESH_SUPPORT_BLE_ADV
+static inline void bt_mesh_set_ble_adv_running();
+
+static inline void bt_mesh_unset_ble_adv_running();
+
+static inline bool bt_mesh_is_ble_adv_running();
+#endif
+
 static bool g_host_init = false;
 
+#if CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_USE_BLE_50
+
+#define BT_MESH_GATTS_CONN_UNUSED 0xFF
+
+static void bt_mesh_gatts_conn_init(void)
+{
+    int i;
+    for (i = 0; i < BLE_MESH_MAX_CONN; i++) {
+        bt_mesh_gatts_conn[i].handle = BT_MESH_GATTS_CONN_UNUSED;
+    }
+}
+
+static int bt_mesh_find_free_conn_idx(void)
+{
+    int i;
+    for (i = 0; i < BLE_MESH_MAX_CONN; i++) {
+        if (bt_mesh_gatts_conn[i].handle == BT_MESH_GATTS_CONN_UNUSED) {
+            return i;
+        }
+    }
+    return -ENOMEM;
+}
+
+static int bt_mesh_find_conn_idx(uint16_t conn_handle)
+{
+    int i;
+    for (i = 0; i < BLE_MESH_MAX_CONN; i++) {
+        if (bt_mesh_gatts_conn[i].handle == conn_handle) {
+            return i;
+        }
+    }
+    return -ENODEV;
+}
+#endif /* CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_USE_BLE_50 */
+
 int bt_mesh_host_init(void)
 {
     int rc;
@@ -145,7 +193,13 @@ void bt_mesh_hci_init(void)
 #endif
 }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+static struct ble_gap_ext_disc_params uncoded_disc_params;
+static struct ble_gap_ext_disc_params coded_disc_params;
+#else
 static struct ble_gap_disc_params scan_param;
+#endif
+
 #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_CLIENT
 static struct gattc_prov_info {
@@ -350,7 +404,7 @@ static int svc_disced(uint16_t conn_handle, const struct ble_gatt_error *error,
         }
 
         uuid = &service->uuid;
-        uuid_length = (uint8_t) (uuid->u.type == BLE_UUID_TYPE_16 ? 2 : 16);
+        uuid_length = (uint8_t)(uuid->u.type == BLE_UUID_TYPE_16 ? 2 : 16);
         if (uuid_length != 2) {
             return 0;
         }
@@ -398,9 +452,45 @@ static int svc_disced(uint16_t conn_handle, const struct ble_gatt_error *error,
 }
 #endif /* (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || CONFIG_BLE_MESH_GATT_PROXY_CLIENT */
 
-static int disc_cb(struct ble_gap_event *event, void *arg)
+#if CONFIG_BLE_MESH_USE_BLE_50
+void bt_mesh_ble_ext_adv_report(struct ble_gap_ext_disc_desc *desc)
+{
+#if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
+    bt_mesh_ble_adv_report_t adv_rpt = {0};
+    if (bt_mesh_ble_scan_state_get()) {
+        memcpy(adv_rpt.addr, desc->addr.val, BLE_MESH_ADDR_LEN);
+        memcpy(adv_rpt.dir_addr, desc->direct_addr.val, BLE_MESH_ADDR_LEN);
+
+        /* Here, only a shallow copy needs to be implemented;
+         * deep copying behavior occurs in btc_ble_mesh_ble_copy_req_data. */
+        adv_rpt.data                = desc->data;
+
+        adv_rpt.event_type          = desc->props;
+        adv_rpt.addr_type           = desc->addr.type;
+        adv_rpt.length              = desc->length_data;
+        adv_rpt.rssi                = desc->rssi;
+        adv_rpt.primary_phy         = desc->prim_phy;
+        adv_rpt.secondary_phy       = desc->sec_phy;
+        adv_rpt.sid                 = desc->sid;
+        adv_rpt.tx_power            = desc->tx_power;
+        adv_rpt.dir_addr_type       = desc->direct_addr.type;
+        adv_rpt.data_status         = desc->data_status;
+        adv_rpt.per_adv_interval    = desc->periodic_adv_itvl;
+
+        bt_mesh_ble_scan_cb_evt_to_btc(&adv_rpt);
+    }
+#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_SCAN */
+}
+#endif
+
+int disc_cb(struct ble_gap_event *event, void *arg)
 {
+#if CONFIG_BLE_MESH_USE_BLE_50
+    struct ble_gap_ext_disc_desc *desc;
+#else
     struct ble_gap_disc_desc *desc;
+#endif
+
 #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_CLIENT
     int rc, i;
@@ -412,21 +502,58 @@ static int disc_cb(struct ble_gap_event *event, void *arg)
 #endif
 
     switch (event->type) {
+#if CONFIG_BLE_MESH_USE_BLE_50
+    case BLE_GAP_EVENT_EXT_DISC: {
+        struct bt_mesh_adv_report adv_rpt = {0};
+
+        desc = &event->ext_disc;
+
+        memcpy(&adv_rpt.addr, &desc->addr, sizeof(bt_mesh_addr_t));
+        adv_rpt.rssi = desc->rssi;
+        adv_rpt.adv_type = desc->props;
+        adv_rpt.primary_phy = desc->prim_phy;
+        adv_rpt.secondary_phy = desc->sec_phy;
+
+        net_buf_simple_init_with_data(&adv_rpt.adv_data, (void *)desc->data, desc->length_data);
+
+        if (bt_mesh_scan_dev_found_cb) {
+            /* TODO: Support Scan Response data length for NimBLE host */
+            if (desc->props & BLE_HCI_ADV_LEGACY_MASK) {
+                bt_mesh_scan_dev_found_cb(&adv_rpt);
+            }
+        }
+
+        /* Mesh didn't process that data */
+        if (adv_rpt.adv_data.len == desc->length_data) {
+            bt_mesh_ble_ext_adv_report(desc);
+        }
+
+        break;
+    }
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
     case BLE_GAP_EVENT_DISC: {
-        struct net_buf_simple buf = {0};
+        struct bt_mesh_adv_report adv_rpt = {0};
 
         desc = &event->disc;
-        net_buf_simple_init_with_data(&buf, (void *)desc->data, desc->length_data);
+
+        adv_rpt.rssi = desc->rssi;
+        adv_rpt.adv_type = desc->event_type;
+
+        memcpy(&adv_rpt.addr, &desc->addr, sizeof(bt_mesh_addr_t));
+
+        net_buf_simple_init_with_data(&adv_rpt.adv_data, (void *)desc->data, desc->length_data);
 
         if (bt_mesh_scan_dev_found_cb) {
             /* TODO: Support Scan Response data length for NimBLE host */
-            bt_mesh_scan_dev_found_cb((bt_mesh_addr_t *)&desc->addr, desc->rssi, desc->event_type, &buf, 0);
+            bt_mesh_scan_dev_found_cb(&adv_rpt);
         }
         break;
     }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_CLIENT
     case BLE_GAP_EVENT_CONNECT:
+        /* @todo: process connect failed event */
         if (event->connect.status == 0) {
             /* Connection successfully established. */
             MODLOG_DFLT(INFO, "Connection established ");
@@ -442,10 +569,21 @@ static int disc_cb(struct ble_gap_event *event, void *arg)
                         break;
                     }
                 }
+                if (i == ARRAY_SIZE(bt_mesh_gattc_info)) {
+                    goto transfer_to_user;
+                }
+            } else {
+                goto transfer_to_user;
             }
         }
         if (!bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_SCANNING)) {
+#if CONFIG_BLE_MESH_USE_BLE_50
+            rc = ble_gap_ext_disc(BLE_OWN_ADDR_PUBLIC, 0, 0, 0, 0, 0,
+                                  uncoded_disc_params.itvl ? &uncoded_disc_params : NULL,
+                                  coded_disc_params.itvl ? &coded_disc_params : NULL, disc_cb, NULL);
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
             rc = ble_gap_disc(BLE_OWN_ADDR_PUBLIC, BLE_HS_FOREVER, &scan_param, disc_cb, NULL);
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
             if (rc != 0) {
                 BT_ERR("Invalid scan status %d", rc);
                 break;
@@ -494,7 +632,13 @@ static int disc_cb(struct ble_gap_event *event, void *arg)
                     bt_mesh_gattc_info[i].wr_desc_done = false;
                     break;
                 }
+
+                if (i == ARRAY_SIZE(bt_mesh_gattc_info)) {
+                    goto transfer_to_user;
+                }
             }
+        } else {
+                goto transfer_to_user;
         }
         break;
     case BLE_GAP_EVENT_MTU:
@@ -521,6 +665,8 @@ static int disc_cb(struct ble_gap_event *event, void *arg)
             }
             /* Search Mesh Provisioning Service or Mesh Proxy Service */
             ble_gattc_disc_all_svcs(bt_mesh_gattc_info[i].conn.handle, svc_disced, NULL);
+        } else {
+            goto transfer_to_user;
         }
         break;
     case BLE_GAP_EVENT_NOTIFY_RX:
@@ -531,8 +677,8 @@ static int disc_cb(struct ble_gap_event *event, void *arg)
         }
 
         if (i == ARRAY_SIZE(bt_mesh_gattc_info)) {
-            BT_ERR("Conn handle 0x%04x not found", event->notify_rx.conn_handle);
-            return 0;
+            BT_DBG("Conn handle 0x%04x not blonges to Mesh", event->notify_rx.conn_handle);
+            goto transfer_to_user;
         }
 
         conn = &bt_mesh_gattc_info[i].conn;
@@ -557,7 +703,7 @@ static int disc_cb(struct ble_gap_event *event, void *arg)
         if (bt_mesh_gattc_info[i].service_uuid == BLE_MESH_UUID_MESH_PROV_VAL) {
             if (bt_mesh_gattc_conn_cb != NULL && bt_mesh_gattc_conn_cb->prov_notify != NULL) {
                 len = bt_mesh_gattc_conn_cb->prov_notify(&bt_mesh_gattc_info[i].conn,
-                        notif_data, notif_len);
+                                                         notif_data, notif_len);
                 if (len < 0) {
                     BT_ERR("prov_notify failed");
                     bt_mesh_gattc_disconnect(conn);
@@ -568,7 +714,7 @@ static int disc_cb(struct ble_gap_event *event, void *arg)
             if (bt_mesh_gattc_conn_cb != NULL && bt_mesh_gattc_conn_cb->proxy_notify != NULL &&
                 bt_mesh_gattc_info[i].wr_desc_done) {
                 len = bt_mesh_gattc_conn_cb->proxy_notify(&bt_mesh_gattc_info[i].conn,
-                        notif_data, notif_len);
+                                                          notif_data, notif_len);
                 if (len < 0) {
                     BT_ERR("proxy_notify failed");
                     bt_mesh_gattc_disconnect(conn);
@@ -579,14 +725,53 @@ static int disc_cb(struct ble_gap_event *event, void *arg)
         break;
 #endif
     default:
+        goto transfer_to_user;
         break;
     }
 
     return 0;
+
+transfer_to_user:
+#if CONFIG_BLE_MESH_USE_BLE_50
+        bt_mesh_ble_nimble_evt_to_btc(event, arg);
+#endif
+    return 0;
 }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+/**
+ * @brief Get the gap callback function used by BLE Mesh
+ *
+ * @note  The user must get the mesh gap event handler function
+ *        through the bt_mesh_nimble_gap_cb_get function and pass
+ *        it in as a callback function when using the api:
+ *        ble_gap_ext_connect, ble_gap_ext_disc, ble_gap_connect,
+ *        and ble_gap_disc.
+ *
+ * @return void*
+ */
+void *bt_mesh_nimble_gap_cb_get(void)
+{
+    return (void*)disc_cb;
+}
+#endif
+
 static int start_le_scan(uint8_t scan_type, uint16_t interval, uint16_t window, uint8_t filter_dup)
 {
+#if CONFIG_BLE_MESH_USE_BLE_50
+    uncoded_disc_params.itvl = (window ? interval : 0);
+    uncoded_disc_params.window = window;
+
+    coded_disc_params.itvl = ((interval > window) ? interval : 0);
+    coded_disc_params.window = ((interval > window) ? interval - window : 0);
+
+    coded_disc_params.passive = (scan_type == BLE_MESH_SCAN_PASSIVE);
+    uncoded_disc_params.passive = (scan_type == BLE_MESH_SCAN_PASSIVE);
+
+    ble_gap_ext_disc(BLE_OWN_ADDR_PUBLIC, 0, 0, filter_dup, 0, 0,
+                     uncoded_disc_params.itvl ? &uncoded_disc_params : NULL,
+                     coded_disc_params.itvl ? &coded_disc_params : NULL, disc_cb, NULL);
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
     scan_param.filter_duplicates = filter_dup;
     scan_param.itvl = interval;
     scan_param.window = window;
@@ -597,6 +782,7 @@ static int start_le_scan(uint8_t scan_type, uint16_t interval, uint16_t window,
         scan_param.passive = 0;
     }
     ble_gap_disc(BLE_OWN_ADDR_PUBLIC, BLE_HS_FOREVER, &scan_param, disc_cb, NULL);
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 #if BLE_MESH_DEV
     if (scan_type == BLE_MESH_SCAN_ACTIVE) {
@@ -649,11 +835,23 @@ static int gap_event_cb(struct ble_gap_event *event, void *arg)
         bt_mesh_atomic_test_and_clear_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING);
 #endif
         if (bt_mesh_gatts_conn_cb != NULL && bt_mesh_gatts_conn_cb->connected != NULL) {
-            uint8_t index = BLE_MESH_GATT_GET_CONN_ID(event->connect.conn_handle);
+            int index = 0;
+#if CONFIG_BLE_MESH_USE_BLE_50
+            index = bt_mesh_find_free_conn_idx();
+            if (index != -ENOMEM) {
+                bt_mesh_gatts_conn[index].handle = BLE_MESH_GATT_GET_CONN_ID(event->connect.conn_handle);
+                (bt_mesh_gatts_conn_cb->connected)(&bt_mesh_gatts_conn[index], 0);
+            } else {
+                BT_ERR("No space for new connection");
+                ble_gap_terminate(event->connect.conn_handle, BLE_ERR_CONN_LIMIT);
+            }
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
+            index = BLE_MESH_GATT_GET_CONN_ID(event->connect.conn_handle);
             if (index < BLE_MESH_MAX_CONN) {
                 bt_mesh_gatts_conn[index].handle = BLE_MESH_GATT_GET_CONN_ID(event->connect.conn_handle);
                 (bt_mesh_gatts_conn_cb->connected)(&bt_mesh_gatts_conn[index], 0);
             }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
             memcpy(bt_mesh_gatts_addr, desc.peer_id_addr.val, BLE_MESH_ADDR_LEN);
             /* This is for EspBleMesh Android app. When it tries to connect with the
              * device at the first time and it fails due to some reason. And after
@@ -673,11 +871,23 @@ static int gap_event_cb(struct ble_gap_event *event, void *arg)
         bt_mesh_atomic_test_and_clear_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING);
 #endif
         if (bt_mesh_gatts_conn_cb != NULL && bt_mesh_gatts_conn_cb->disconnected != NULL) {
-            uint8_t index = BLE_MESH_GATT_GET_CONN_ID(event->disconnect.conn.conn_handle);
+            int index = 0;
+#if CONFIG_BLE_MESH_USE_BLE_50
+            index = bt_mesh_find_conn_idx(BLE_MESH_GATT_GET_CONN_ID(event->disconnect.conn.conn_handle));
+            if (index != -ENODEV) {
+                bt_mesh_gatts_conn[index].handle = BLE_MESH_GATT_GET_CONN_ID(event->disconnect.conn.conn_handle);
+                (bt_mesh_gatts_conn_cb->disconnected)(&bt_mesh_gatts_conn[index], event->disconnect.reason);
+            } else {
+                BT_ERR("No device");
+            }
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
+            index = BLE_MESH_GATT_GET_CONN_ID(event->disconnect.conn.conn_handle);
             if (index < BLE_MESH_MAX_CONN) {
                 bt_mesh_gatts_conn[index].handle = BLE_MESH_GATT_GET_CONN_ID(event->disconnect.conn.conn_handle);
                 (bt_mesh_gatts_conn_cb->disconnected)(&bt_mesh_gatts_conn[index], event->disconnect.reason);
             }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+            bt_mesh_gatts_conn[index].handle = 0;
             memset(bt_mesh_gatts_addr, 0x0, BLE_MESH_ADDR_LEN);
         }
 
@@ -693,8 +903,38 @@ static int gap_event_cb(struct ble_gap_event *event, void *arg)
         return 0;
 
     case BLE_GAP_EVENT_ADV_COMPLETE:
-        MODLOG_DFLT(INFO, "advertise complete; reason=%d",
-                    event->adv_complete.reason);
+        BT_DBG("advertise complete; reason=%d",
+               event->adv_complete.reason);
+        /* Limit Reached (0x43) and Advertising Timeout (0x3C) will cause BLE_HS_ETIMEOUT to be set. */
+#if CONFIG_BLE_MESH_USE_BLE_50
+        if (event->adv_complete.reason == BLE_HS_ETIMEOUT) {
+            ble_mesh_adv_task_wakeup(event->adv_complete.instance);
+        }
+#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
+        /**
+         * This judgment is to distinguish between the termination
+         * events of BLE connectable broadcasting and proxy connectable
+         * adv under the same instance ID, that is, when the status is 0.
+         *
+         * Since the host task and adv task are currently operated in
+         * series, there is no need to consider competition issues between
+         * tasks.
+         *
+         * @attention: once multiple adv instances are used, the adv task
+         * and host will be asynchronous, and it is necessary to consider
+         * the issue of resource competition.
+         */
+        if (bt_mesh_is_ble_adv_running() &&
+            event->adv_complete.reason == 0) {
+           /* The unset operation must be performed before waking up the
+            * adv task; performing the unset after waking up the adv task
+            * could lead to resource contention issues.
+            */
+            bt_mesh_unset_ble_adv_running();
+            ble_mesh_adv_task_wakeup(event->adv_complete.instance);
+        }
+#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
         return 0;
 
     case BLE_GAP_EVENT_ENC_CHANGE:
@@ -717,10 +957,20 @@ static int gap_event_cb(struct ble_gap_event *event, void *arg)
                     event->subscribe.prev_indicate,
                     event->subscribe.cur_indicate);
         struct bt_mesh_gatt_attr *attr = bt_mesh_gatts_find_attr_by_handle(event->subscribe.attr_handle + 1);
-        uint8_t index = BLE_MESH_GATT_GET_CONN_ID(event->subscribe.conn_handle);
+        int index = 0;
         uint16_t len = 0;
         uint16_t ccc_val = 0;
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+        index = bt_mesh_find_conn_idx(BLE_MESH_GATT_GET_CONN_ID(event->subscribe.conn_handle));
+        if (index == -ENODEV) {
+            BT_ERR("Couldn't find conn %d", event->subscribe.conn_handle);
+            return 0;
+        }
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
+        index = BLE_MESH_GATT_GET_CONN_ID(event->subscribe.conn_handle);
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+
         if (event->subscribe.prev_notify != event->subscribe.cur_notify) {
             ccc_val = event->subscribe.cur_notify;
         } else if (event->subscribe.prev_indicate != event->subscribe.cur_indicate) {
@@ -773,10 +1023,231 @@ static int gap_event_cb(struct ble_gap_event *event, void *arg)
 #else
 static int gap_event_cb(struct ble_gap_event *event, void *arg)
 {
+#if CONFIG_BLE_MESH_USE_BLE_50
+    switch (event->type) {
+    case BLE_GAP_EVENT_ADV_COMPLETE:
+        BT_DBG("Provisioner advertise complete; reason=%d",
+               event->adv_complete.reason);
+        /* Limit Reached (0x43) and Advertising Timeout (0x3C) will cause BLE_HS_ETIMEOUT to be set. */
+        if (event->adv_complete.reason == BLE_HS_ETIMEOUT) {
+            ble_mesh_adv_task_wakeup(event->adv_complete.instance);
+        }
+#if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
+        /**
+         * This judgment is to distinguish between the termination
+         * events of BLE connectable broadcasting and proxy connectable
+         * adv under the same instance ID, that is, when the status is 0.
+         *
+         * Since the host task and adv task are currently operated in
+         * series, there is no need to consider competition issues between
+         * tasks.
+         *
+         * @attention: once multiple adv instances are used, the adv task
+         * and host will be asynchronous, and it is necessary to consider
+         * the issue of resource competition.
+         */
+        if (bt_mesh_is_ble_adv_running() &&
+            event->adv_complete.reason == 0) {
+           /* The unset operation must be performed before waking up the
+            * adv task; performing the unset after waking up the adv task
+            * could lead to resource contention issues.
+            */
+            bt_mesh_unset_ble_adv_running();
+            ble_mesh_adv_task_wakeup(event->adv_complete.instance);
+        }
+#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */
+        break;
+    }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
     return 0;
 }
 #endif /* CONFIG_BLE_MESH_NODE */
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+int bt_le_ext_adv_start(const uint8_t inst_id,
+                        const struct bt_mesh_adv_param *param,
+                        const struct bt_mesh_adv_data *ad, size_t ad_len,
+                        const struct bt_mesh_adv_data *sd, size_t sd_len)
+{
+    struct ble_gap_ext_adv_params adv_params = {0};
+    struct os_mbuf *data = NULL;
+    struct os_mbuf *scan_rsp = NULL;
+    uint8_t *buf = NULL;
+    uint16_t interval = 0;
+    uint8_t buf_len = 0;
+    int err = 0;
+
+    err = ble_gap_ext_adv_active(inst_id);
+    if (err) {
+        BT_ERR("adv inst(%d) is running %d", inst_id, err);
+        return -EINVAL;
+    }
+
+#if BLE_MESH_DEV
+    if (bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING)) {
+        return -EALREADY;
+    }
+#endif
+    buf = bt_mesh_calloc(ad_len * BLE_HS_ADV_MAX_SZ);
+    if (!buf) {
+        BT_ERR("ad buffer alloc failed");
+        return -ENOMEM;
+    }
+
+    err = set_ad(ad, ad_len, buf, &buf_len);
+    if (err) {
+        bt_mesh_free(buf);
+        BT_ERR("set_ad failed: err %d", err);
+        return err;
+    }
+
+    data = os_msys_get_pkthdr(buf_len, 0);
+    if (!data) {
+        bt_mesh_free(buf);
+        BT_ERR("os buf get failed");
+        return -ENOBUFS;
+    }
+
+    err = os_mbuf_append(data, buf, buf_len);
+    if (err) {
+        bt_mesh_free(buf);
+        BT_ERR("Append ad data to os buf failed %d", err);
+        return -EINVAL;
+    }
+
+    bt_mesh_free(buf);
+
+    if (sd && (param->options & BLE_MESH_ADV_OPT_CONNECTABLE)) {
+        buf_len = 0;
+
+        buf = bt_mesh_calloc(sd_len * BLE_HS_ADV_MAX_SZ);
+        if (!buf) {
+            BT_ERR("ad buffer alloc failed");
+            return -ENOMEM;
+        }
+
+        err = set_ad(sd, sd_len, buf, &buf_len);
+        if (err) {
+            bt_mesh_free(buf);
+            BT_ERR("set_ad failed: err %d", err);
+            return err;
+        }
+
+        scan_rsp = os_msys_get_pkthdr(buf_len, 0);
+        if (!data) {
+            bt_mesh_free(buf);
+            BT_ERR("os buf get failed");
+            return -ENOBUFS;
+        }
+
+        err = os_mbuf_append(scan_rsp, buf, buf_len);
+        if (err) {
+            bt_mesh_free(buf);
+            BT_ERR("Append ad data to os buf failed %d", err);
+            return -EINVAL;
+        }
+
+        bt_mesh_free(buf);
+    }
+
+    memset(&adv_params, 0, sizeof adv_params);
+
+    assert(param);
+
+    if (param->options & BLE_MESH_ADV_OPT_CONNECTABLE) {
+        adv_params.connectable = true;
+        adv_params.scannable = true;
+        adv_params.legacy_pdu = true;
+    } else if (sd != NULL) {
+        adv_params.connectable = false;
+        adv_params.scannable = true;
+        adv_params.legacy_pdu = true;
+    } else {
+        if (param->primary_phy == BLE_MESH_ADV_PHY_1M &&
+            param->secondary_phy == BLE_MESH_ADV_PHY_1M) {
+            adv_params.legacy_pdu = true;
+        }
+    }
+
+    adv_params.sid = inst_id;
+    adv_params.primary_phy = param->primary_phy;
+    adv_params.secondary_phy = param->secondary_phy;
+    adv_params.tx_power = 0x7F; // tx power will be selected by controller
+    adv_params.own_addr_type = BLE_OWN_ADDR_PUBLIC;
+
+    interval = param->interval_min;
+
+#if CONFIG_BLE_MESH_RANDOM_ADV_INTERVAL
+    /* If non-connectable mesh packets are transmitted with an adv interval
+     * not smaller than 10ms, then we will use a random adv interval between
+     * [interval / 2, interval] for them.
+     */
+    if (adv_params.conn_mode == BLE_GAP_CONN_MODE_NON &&
+        adv_params.disc_mode == BLE_GAP_DISC_MODE_NON && interval >= 16) {
+        interval >>= 1;
+        interval += (bt_mesh_get_rand() % (interval + 1));
+
+        adv_params->high_duty_directed = true;
+
+        BT_INFO("%u->%u", param->interval_min, interval);
+    }
+#endif
+
+    adv_params.itvl_min = interval;
+    adv_params.itvl_max = interval;
+
+    err = ble_gap_ext_adv_configure(inst_id, &adv_params, NULL, gap_event_cb, NULL);
+    if (err != 0) {
+        BT_ERR("Advertising config failed: err %d", err);
+        return err;
+    }
+
+    err = ble_gap_ext_adv_set_data(inst_id, data);
+    if (err != 0) {
+        BT_ERR("Advertising set failed: err %d", err);
+        return err;
+    }
+
+    if (scan_rsp) {
+        err = ble_gap_ext_adv_rsp_set_data(inst_id, scan_rsp);
+        if (err != 0) {
+            BT_ERR("scan rsp set failed: err %d", err);
+            return err;
+        } else {
+            BT_INFO("scan rsp set succeed\n");
+        }
+    }
+
+again:
+
+    if (param->adv_duration < 10 &&
+        param->adv_duration != 0) {
+        BT_WARN("adv duration shall not be less than 10ms");
+    }
+
+    err = ble_gap_ext_adv_start(inst_id, param->adv_duration ?
+                                2 + param->adv_duration / 10 : 0, param->adv_count);
+    if (err) {
+        if (err == BLE_HS_EALREADY) {
+            ble_gap_ext_adv_stop(inst_id);
+            goto again;
+        }
+
+        BT_ERR("Advertising start failed: err %d", err);
+        return err;
+    }
+
+#if BLE_MESH_DEV
+    bt_mesh_atomic_set_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING);
+
+    if (!(param->options & BLE_MESH_ADV_OPT_ONE_TIME)) {
+        bt_mesh_atomic_set_bit(bt_mesh_dev.flags, BLE_MESH_DEV_KEEP_ADVERTISING);
+    }
+#endif
+
+    return 0;
+}
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
 /* APIs functions */
 int bt_le_adv_start(const struct bt_mesh_adv_param *param,
                     const struct bt_mesh_adv_data *ad, size_t ad_len,
@@ -877,8 +1348,146 @@ int bt_le_adv_start(const struct bt_mesh_adv_param *param,
 
     return 0;
 }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 #if CONFIG_BLE_MESH_SUPPORT_BLE_ADV
+#if CONFIG_BLE_MESH_USE_BLE_50
+
+static bool _ble_adv_running_flag;
+
+static inline void bt_mesh_set_ble_adv_running()
+{
+    _ble_adv_running_flag = true;
+}
+
+static inline void bt_mesh_unset_ble_adv_running()
+{
+    _ble_adv_running_flag = false;
+}
+
+static inline bool bt_mesh_is_ble_adv_running()
+{
+    return _ble_adv_running_flag == true;
+}
+
+int bt_mesh_ble_ext_adv_start(const uint8_t inst_id,
+                              const struct bt_mesh_ble_adv_param *param,
+                              const struct bt_mesh_ble_adv_data *adv_data)
+{
+    struct ble_gap_ext_adv_params adv_params = {0};
+    struct os_mbuf *data = NULL;
+    int err = 0;
+
+    assert(param);
+
+    switch (param->adv_type) {
+    case BLE_MESH_ADV_IND:
+        adv_params.connectable = true;
+        adv_params.scannable = true;
+        adv_params.legacy_pdu = true;
+        break;
+    case BLE_MESH_ADV_DIRECT_IND:
+        adv_params.connectable = true;
+        adv_params.scannable = false;
+        adv_params.directed = true;
+        adv_params.high_duty_directed = false;
+        adv_params.legacy_pdu = true;
+        break;
+    case BLE_MESH_ADV_SCAN_IND:
+        adv_params.connectable = false;
+        adv_params.scannable = true;
+        adv_params.directed = false;
+        adv_params.high_duty_directed = false;
+        adv_params.legacy_pdu = true;
+        break;
+    case BLE_MESH_ADV_NONCONN_IND:
+        adv_params.connectable = false;
+        adv_params.scannable = false;
+        adv_params.directed = false;
+        adv_params.high_duty_directed = false;
+        adv_params.legacy_pdu = true;
+        break;
+    case BLE_MESH_ADV_DIRECT_IND_LOW_DUTY:
+        adv_params.connectable = true;
+        adv_params.scannable = false;
+        adv_params.directed = true;
+        adv_params.high_duty_directed = true;
+        adv_params.legacy_pdu = true;
+        break;
+    }
+
+    adv_params.itvl_min = param->interval;
+    adv_params.itvl_max = param->interval;
+    adv_params.channel_map = BLE_MESH_ADV_CHNL_37 | BLE_MESH_ADV_CHNL_38 | BLE_MESH_ADV_CHNL_39;
+    adv_params.filter_policy = BLE_MESH_AP_SCAN_CONN_ALL;
+    adv_params.primary_phy = BLE_MESH_ADV_PHY_1M;
+    adv_params.secondary_phy = BLE_MESH_ADV_PHY_1M;
+
+    if (param->own_addr_type == BLE_MESH_ADDR_PUBLIC_ID ||
+        param->own_addr_type == BLE_MESH_ADDR_RANDOM_ID ||
+        param->adv_type == BLE_MESH_ADV_DIRECT_IND ||
+        param->adv_type == BLE_MESH_ADV_DIRECT_IND_LOW_DUTY) {
+        adv_params.peer.type = param->peer_addr_type;
+        memcpy(adv_params.peer.val, param->peer_addr, BLE_MESH_ADDR_LEN);
+    }
+
+
+    if (ble_gap_ext_adv_configure(inst_id, &adv_params, NULL,
+                                  gap_event_cb, NULL)) {
+        BT_ERR("ble adv configure failed\n");
+        return -EINVAL;
+    }
+
+    if (adv_data && param->adv_type != BLE_MESH_ADV_DIRECT_IND &&
+        param->adv_type != BLE_MESH_ADV_DIRECT_IND_LOW_DUTY) {
+        if (adv_data->adv_data_len) {
+            data = os_msys_get_pkthdr(adv_data->adv_data_len, 0);
+            if (!data) {
+                BT_ERR("Failed to alloc buffer for ble");
+                return -ENOMEM;
+            }
+
+            if (os_mbuf_append(data, adv_data->adv_data, adv_data->adv_data_len)) {
+                BT_ERR("Append data failed");
+                return -EINVAL;
+            }
+
+            err = ble_gap_ext_adv_set_data(inst_id, data);
+            if (err) {
+                BT_ERR("Failed to set advertising data, err %d", err);
+                return err;
+            }
+        }
+        if (adv_data->scan_rsp_data_len && param->adv_type != BLE_MESH_ADV_NONCONN_IND) {
+            data = os_msys_get_pkthdr(adv_data->scan_rsp_data_len, 0);
+            if (!data) {
+                BT_ERR("Failed to alloc buffer for ble");
+                return -ENOMEM;
+            }
+
+            if (os_mbuf_append(data, adv_data->scan_rsp_data, adv_data->scan_rsp_data_len)) {
+                BT_ERR("Append data failed");
+                return -EINVAL;
+            }
+            err = ble_gap_ext_adv_rsp_set_data(inst_id, data);
+            if (err) {
+                BT_ERR("Failed to set scan rsp data, err %d", err);
+                return err;
+            }
+        }
+    }
+
+    err = ble_gap_ext_adv_start(inst_id, 2 + param->duration / 10, param->count);
+    if (err) {
+        BT_ERR("Failed to start advertising, err %d", err);
+        return err;
+    }
+
+    bt_mesh_set_ble_adv_running();
+
+    return 0;
+}
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
 int bt_mesh_ble_adv_start(const struct bt_mesh_ble_adv_param *param,
                           const struct bt_mesh_ble_adv_data *data)
 {
@@ -949,8 +1558,27 @@ int bt_mesh_ble_adv_start(const struct bt_mesh_ble_adv_param *param,
 
     return 0;
 }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 #endif /* CONFIG_BLE_MESH_SUPPORT_BLE_ADV */
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+int bt_le_ext_adv_stop(uint8_t inst_id)
+{
+#if BLE_MESH_DEV
+    bt_mesh_atomic_clear_bit(bt_mesh_dev.flags, BLE_MESH_DEV_KEEP_ADVERTISING);
+    if (!bt_mesh_atomic_test_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING)) {
+        return 0;
+    }
+#endif
+    ble_gap_ext_adv_stop(inst_id);
+
+#if BLE_MESH_DEV
+    bt_mesh_atomic_clear_bit(bt_mesh_dev.flags, BLE_MESH_DEV_ADVERTISING);
+#endif
+
+    return 0;
+}
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
 int bt_le_adv_stop(void)
 {
 #if BLE_MESH_DEV
@@ -967,6 +1595,7 @@ int bt_le_adv_stop(void)
 
     return 0;
 }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 int bt_le_scan_start(const struct bt_mesh_scan_param *param, bt_mesh_scan_cb_t cb)
 {
@@ -987,6 +1616,7 @@ int bt_le_scan_start(const struct bt_mesh_scan_param *param, bt_mesh_scan_cb_t c
 
     err = start_le_scan(param->type, param->interval, param->window, param->filter_dup);
     if (err) {
+        BT_ERR("Failed to start advertising, err %d", err);
         return err;
     }
 
@@ -1554,6 +2184,7 @@ int bt_mesh_gattc_write_no_rsp(struct bt_mesh_conn *conn,
 
     om = ble_hs_mbuf_from_flat(data, len);
     if (om == NULL) {
+        BT_ERR("om buffer alloc failed");
         return -1;
     }
 
@@ -1622,9 +2253,19 @@ static int proxy_char_access_cb(uint16_t conn_handle, uint16_t attr_handle,
 {
     if (ctxt->op == BLE_GATT_ACCESS_OP_WRITE_CHR || ctxt->op == BLE_GATT_ACCESS_OP_WRITE_DSC) {
         struct bt_mesh_gatt_attr *attr = bt_mesh_gatts_find_attr_by_handle(attr_handle);
-        uint8_t index = BLE_MESH_GATT_GET_CONN_ID(conn_handle);
+        int index = 0;
         uint16_t len = 0;
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+        index =  bt_mesh_find_conn_idx(BLE_MESH_GATT_GET_CONN_ID(conn_handle));
+        if (index == -ENODEV) {
+            BT_ERR("Unknown conn handle");
+            return 0;
+        }
+#else
+        index = BLE_MESH_GATT_GET_CONN_ID(conn_handle);
+#endif
+
         BT_DBG("write, handle %d, len %d, data %s", attr_handle,
                ctxt->om->om_len,
                bt_hex(ctxt->om->om_data, ctxt->om->om_len));
@@ -1713,6 +2354,58 @@ void gatt_register_cb(struct ble_gatt_register_ctxt *ctxt,
     }
 }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+void bt_mesh_gatts_svcs_add(void)
+{
+    ble_hs_cfg.gatts_register_cb = gatt_register_cb;
+
+#if CONFIG_BLE_MESH_NODE
+    int rc = 0;
+
+    ble_svc_gap_init();
+    ble_svc_gatt_init();
+
+    rc = ble_gatts_count_cfg(svc_defs);
+    assert(rc == 0);
+
+    rc = ble_gatts_add_svcs(svc_defs);
+    assert(rc == 0);
+
+    g_gatts_svcs_add = true;
+#endif
+}
+
+void bt_mesh_gatt_init(void)
+{
+    ble_att_set_preferred_mtu(BLE_MESH_GATT_DEF_MTU_SIZE);
+
+#if CONFIG_BLE_MESH_NODE
+    static bool init = false;
+
+    if (init == false) {
+
+        __ASSERT(g_gatts_svcs_add, "func bt_mesh_gatts_svcs_add should be called before mesh init");
+
+        ble_gatts_svc_set_visibility(prov_svc_start_handle, 1);
+        ble_gatts_svc_set_visibility(proxy_svc_start_handle, 0);
+
+#if CONFIG_BLE_MESH_USE_BLE_50
+        bt_mesh_gatts_conn_init();
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+        init = true;
+    }
+#endif /* CONFIG_BLE_MESH_NODE */
+
+#if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \
+     CONFIG_BLE_MESH_GATT_PROXY_CLIENT
+    for (int i = 0; i < ARRAY_SIZE(bt_mesh_gattc_info); i++) {
+        bt_mesh_gattc_info[i].conn.handle = 0xFFFF;
+        bt_mesh_gattc_info[i].mtu = BLE_ATT_MTU_DFLT;
+        bt_mesh_gattc_info[i].wr_desc_done = false;
+    }
+#endif
+}
+#else
 void bt_mesh_gatt_init(void)
 {
     ble_att_set_preferred_mtu(BLE_ATT_MTU_DFLT);
@@ -1751,6 +2444,7 @@ void bt_mesh_gatt_init(void)
     }
 #endif
 }
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
 
 #if CONFIG_BLE_MESH_DEINIT
 void bt_mesh_gatt_deinit(void)
@@ -1981,12 +2675,12 @@ int bt_mesh_update_exceptional_list(uint8_t sub_code, uint32_t type, void *info)
 
     if ((sub_code > BLE_MESH_EXCEP_LIST_SUB_CODE_CLEAN) ||
         (sub_code < BLE_MESH_EXCEP_LIST_SUB_CODE_CLEAN &&
-         type > BLE_MESH_EXCEP_LIST_TYPE_MESH_PROXY_ADV) ||
+         type > BLE_MESH_EXCEP_LIST_TYPE_MAX) ||
         (sub_code == BLE_MESH_EXCEP_LIST_SUB_CODE_CLEAN &&
          !(type & BLE_MESH_EXCEP_LIST_CLEAN_ALL_LIST))) {
         BT_ERR("%s, Invalid parameter", __func__);
         return -EINVAL;
-   }
+    }
 
     if (type == BLE_MESH_EXCEP_LIST_TYPE_MESH_LINK_ID) {
         if (!info) {
diff --git a/components/bt/esp_ble_mesh/core/prov_common.h b/components/bt/esp_ble_mesh/core/prov_common.h
index 561712ef146..d2a8771bec8 100644
--- a/components/bt/esp_ble_mesh/core/prov_common.h
+++ b/components/bt/esp_ble_mesh/core/prov_common.h
@@ -17,7 +17,9 @@
 #include "mesh/timer.h"
 #include "mesh/adapter.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/bt/esp_ble_mesh/core/prov_node.c b/components/bt/esp_ble_mesh/core/prov_node.c
index 4871a1cb1eb..8053ac82018 100644
--- a/components/bt/esp_ble_mesh/core/prov_node.c
+++ b/components/bt/esp_ble_mesh/core/prov_node.c
@@ -22,7 +22,9 @@
 #include "prov_common.h"
 #include "prov_node.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #if CONFIG_BLE_MESH_NODE
 
diff --git a/components/bt/esp_ble_mesh/core/prov_pvnr.c b/components/bt/esp_ble_mesh/core/prov_pvnr.c
index e2e0fe5850d..9066597e876 100644
--- a/components/bt/esp_ble_mesh/core/prov_pvnr.c
+++ b/components/bt/esp_ble_mesh/core/prov_pvnr.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,7 +22,9 @@
 #include "prov_pvnr.h"
 #include "pvnr_mgmt.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #if CONFIG_BLE_MESH_PROVISIONER
 
@@ -1413,7 +1415,7 @@ static int prov_auth(struct bt_mesh_prov_link *link,
             return -EINVAL;
         }
 
-        /* Provisioner ouput number/string and wait for device's Provisioning Input Complete PDU */
+        /* Provisioner output number/string and wait for device's Provisioning Input Complete PDU */
         link->expect = PROV_INPUT_COMPLETE;
 
         /* NOTE: The Bluetooth SIG recommends that mesh implementations enforce a randomly
diff --git a/components/bt/esp_ble_mesh/core/proxy_client.c b/components/bt/esp_ble_mesh/core/proxy_client.c
index 9382cf61478..9e9a7354a25 100644
--- a/components/bt/esp_ble_mesh/core/proxy_client.c
+++ b/components/bt/esp_ble_mesh/core/proxy_client.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,7 +21,9 @@
 #include "pvnr_mgmt.h"
 #include "mesh/adapter.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_CLIENT
diff --git a/components/bt/esp_ble_mesh/core/proxy_client.h b/components/bt/esp_ble_mesh/core/proxy_client.h
index d2d85017019..ef8db32f6d2 100644
--- a/components/bt/esp_ble_mesh/core/proxy_client.h
+++ b/components/bt/esp_ble_mesh/core/proxy_client.h
@@ -11,7 +11,9 @@
 #include "mesh/adapter.h"
 #include "prov_common.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/bt/esp_ble_mesh/core/proxy_server.c b/components/bt/esp_ble_mesh/core/proxy_server.c
index 020793dc6e8..65b5dcba63b 100644
--- a/components/bt/esp_ble_mesh/core/proxy_server.c
+++ b/components/bt/esp_ble_mesh/core/proxy_server.c
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,7 +22,9 @@
 #include "prov_common.h"
 #include "prov_node.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #if (CONFIG_BLE_MESH_NODE && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_SERVER
@@ -33,6 +35,10 @@ _Static_assert(!(IS_ENABLED(CONFIG_BLE_MESH_GATT_PROXY_SERVER) && IS_ENABLED(CON
                "Not support Proxy Server and Proxy Client simultaneously");
 #endif
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+static uint8_t proxy_adv_inst = BLE_MESH_ADV_INS_UNUSED;
+#endif
+
 #define ADV_OPT     (BLE_MESH_ADV_OPT_CONNECTABLE | BLE_MESH_ADV_OPT_ONE_TIME)
 
 #if CONFIG_BLE_MESH_GATT_PROXY_SERVER && \
@@ -50,12 +56,24 @@ static const struct bt_mesh_adv_param slow_adv_param = {
     .options = ADV_OPT,
     .interval_min = BLE_MESH_GAP_ADV_SLOW_INT_MIN,
     .interval_max = BLE_MESH_GAP_ADV_SLOW_INT_MAX,
+#if CONFIG_BLE_MESH_USE_BLE_50
+    .primary_phy = BLE_MESH_ADV_PHY_1M,
+    .secondary_phy = BLE_MESH_ADV_PHY_1M,
+    .adv_duration = 0,
+    .adv_count = 0,
+#endif
 };
 
 static const struct bt_mesh_adv_param fast_adv_param = {
     .options = ADV_OPT,
     .interval_min = BLE_MESH_GAP_ADV_FAST_INT_MIN_0,
     .interval_max = BLE_MESH_GAP_ADV_FAST_INT_MAX_0,
+#if CONFIG_BLE_MESH_USE_BLE_50
+    .primary_phy = BLE_MESH_ADV_PHY_1M,
+    .secondary_phy = BLE_MESH_ADV_PHY_1M,
+    .adv_duration = 0,
+    .adv_count = 0,
+#endif
 };
 
 static bool proxy_adv_enabled;
@@ -1463,8 +1481,13 @@ static int node_id_adv(struct bt_mesh_subnet *sub)
     memcpy(proxy_svc_data + 3, tmp + 8, 8);
     proxy_sd_len = gatt_proxy_adv_create(&proxy_sd);
 
-    err = bt_le_adv_start(&fast_adv_param, node_id_ad,
-                          ARRAY_SIZE(node_id_ad), &proxy_sd, proxy_sd_len);
+#if CONFIG_BLE_MESH_USE_BLE_50
+    err = bt_le_ext_adv_start(proxy_adv_inst, &fast_adv_param, node_id_ad,
+                              ARRAY_SIZE(node_id_ad), &proxy_sd, proxy_sd_len);
+#else
+     err = bt_le_adv_start(&fast_adv_param, node_id_ad,
+                           ARRAY_SIZE(node_id_ad), &proxy_sd, proxy_sd_len);
+#endif
     if (err) {
         BT_WARN("Failed to advertise using Node ID (err %d)", err);
         return err;
@@ -1489,8 +1512,13 @@ static int net_id_adv(struct bt_mesh_subnet *sub)
     memcpy(proxy_svc_data + 3, sub->keys[sub->kr_flag].net_id, 8);
     proxy_sd_len = gatt_proxy_adv_create(&proxy_sd);
 
-    err = bt_le_adv_start(&slow_adv_param, net_id_ad,
-                          ARRAY_SIZE(net_id_ad), &proxy_sd, proxy_sd_len);
+#if CONFIG_BLE_MESH_USE_BLE_50
+    err = bt_le_ext_adv_start(proxy_adv_inst, &slow_adv_param, net_id_ad,
+                              ARRAY_SIZE(net_id_ad), &proxy_sd, proxy_sd_len);
+#else
+     err = bt_le_adv_start(&slow_adv_param, net_id_ad,
+                           ARRAY_SIZE(net_id_ad), &proxy_sd, proxy_sd_len);
+#endif
     if (err) {
         BT_WARN("Failed to advertise using Network ID (err %d)", err);
         return err;
@@ -1834,13 +1862,20 @@ int32_t bt_mesh_proxy_server_adv_start(void)
         return K_FOREVER;
     }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    if (proxy_adv_inst == BLE_MESH_ADV_INS_UNUSED) {
+        BT_ERR("Proxy adv inst is not initialized!");
+        return K_FOREVER;
+    }
+#endif
+
 #if CONFIG_BLE_MESH_PB_GATT
     if (prov_fast_adv) {
         prov_start_time = k_uptime_get_32();
     }
 
     if (!bt_mesh_is_provisioned()) {
-        const struct bt_mesh_adv_param *param;
+        const struct bt_mesh_adv_param *param = NULL;
         struct bt_mesh_adv_data prov_sd[2];
         size_t prov_sd_len;
 
@@ -1852,8 +1887,14 @@ int32_t bt_mesh_proxy_server_adv_start(void)
 
         prov_sd_len = gatt_prov_adv_create(prov_sd);
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+        if (bt_le_ext_adv_start(proxy_adv_inst, param, prov_ad, ARRAY_SIZE(prov_ad),
+                                prov_sd, prov_sd_len) == 0) {
+#else /* CONFIG_BLE_MESH_USE_BLE_50 */
         if (bt_le_adv_start(param, prov_ad, ARRAY_SIZE(prov_ad),
                             prov_sd, prov_sd_len) == 0) {
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+
             proxy_adv_enabled = true;
 
             /* Advertise 60 seconds using fast interval */
@@ -1897,7 +1938,16 @@ void bt_mesh_proxy_server_adv_stop(void)
         return;
     }
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    if (proxy_adv_inst == BLE_MESH_ADV_INS_UNUSED) {
+        BT_ERR("Proxy adv inst is not initialized!");
+        return;
+   }
+
+    err = bt_le_ext_adv_stop(proxy_adv_inst);
+#else
     err = bt_le_adv_stop();
+#endif
     if (err) {
         BT_ERR("Failed to stop advertising (err %d)", err);
     } else {
@@ -1914,6 +1964,10 @@ int bt_mesh_proxy_server_init(void)
 {
     int i;
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    proxy_adv_inst = bt_mesh_get_proxy_inst();
+#endif
+
 #if CONFIG_BLE_MESH_GATT_PROXY_SERVER
     bt_mesh_gatts_service_register(&proxy_svc);
 #endif
@@ -1952,6 +2006,10 @@ int bt_mesh_proxy_server_deinit(void)
 {
     int i;
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    proxy_adv_inst = BLE_MESH_ADV_INS_UNUSED;
+#endif
+
     proxy_adv_enabled = false;
     gatt_svc = MESH_GATT_NONE;
 
diff --git a/components/bt/esp_ble_mesh/core/proxy_server.h b/components/bt/esp_ble_mesh/core/proxy_server.h
index b98728910de..88eed8a7e96 100644
--- a/components/bt/esp_ble_mesh/core/proxy_server.h
+++ b/components/bt/esp_ble_mesh/core/proxy_server.h
@@ -12,6 +12,7 @@
 
 #include "net.h"
 #include "mesh/adapter.h"
+#include "adv.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/bt/esp_ble_mesh/core/pvnr_mgmt.c b/components/bt/esp_ble_mesh/core/pvnr_mgmt.c
index 2531a2d2fdb..96ad2feb324 100644
--- a/components/bt/esp_ble_mesh/core/pvnr_mgmt.c
+++ b/components/bt/esp_ble_mesh/core/pvnr_mgmt.c
@@ -22,7 +22,9 @@
 #include "prov_pvnr.h"
 #include "pvnr_mgmt.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #if CONFIG_BLE_MESH_PROVISIONER
 
diff --git a/components/bt/esp_ble_mesh/core/scan.c b/components/bt/esp_ble_mesh/core/scan.c
index e1b43dd2f63..4e021a7cbb3 100644
--- a/components/bt/esp_ble_mesh/core/scan.c
+++ b/components/bt/esp_ble_mesh/core/scan.c
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,7 +27,9 @@
 #include "prov_pvnr.h"
 #include "mesh/adapter.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 /* Scan Window and Interval are equal for continuous scanning */
 #define SCAN_INTERVAL   0x20
@@ -39,6 +41,22 @@
 #define PROXY_SVC_DATA_LEN_PRIVATE_NET_ID   0x11
 #define PROXY_SVC_DATA_LEN_PRIVATE_NODE_ID  0x11
 
+static struct bt_mesh_scan_param scan_param = {
+#if CONFIG_BLE_MESH_RPR_SRV_ACTIVE_SCAN
+        .type       = BLE_MESH_SCAN_ACTIVE,
+#else
+        .type       = BLE_MESH_SCAN_PASSIVE,
+#endif
+#if CONFIG_BLE_MESH_USE_DUPLICATE_SCAN
+        .filter_dup = BLE_MESH_SCAN_FILTER_DUP_ENABLE,
+#else
+        .filter_dup = BLE_MESH_SCAN_FILTER_DUP_DISABLE,
+#endif
+        .interval   = SCAN_INTERVAL,
+        .window     = SCAN_WINDOW,
+        .scan_fil_policy = BLE_MESH_SP_ADV_ALL,
+};
+
 #if (CONFIG_BLE_MESH_PROVISIONER || CONFIG_BLE_MESH_RPR_SRV)
 static const bt_mesh_addr_t *unprov_dev_addr;
 static uint8_t current_adv_type;
@@ -263,12 +281,13 @@ static void handle_adv_service_data(struct net_buf_simple *buf,
             bt_mesh_provisioner_prov_adv_recv(buf, addr, rssi);
         }
 
-        if (IS_ENABLED(CONFIG_BLE_MESH_RPR_SRV) &&
-            bt_mesh_is_provisioned()) {
+#if CONFIG_BLE_MESH_RPR_SRV
+        if (bt_mesh_is_provisioned()) {
             const bt_mesh_addr_t *addr = bt_mesh_get_unprov_dev_addr();
             bt_mesh_unprov_dev_fifo_enqueue(buf->data, addr->val, bt_mesh_get_adv_type());
             bt_mesh_rpr_srv_unprov_beacon_recv(buf, bt_mesh_get_adv_type(), addr, rssi);
         }
+#endif
         break;
 #endif
 #if CONFIG_BLE_MESH_GATT_PROXY_CLIENT
@@ -333,13 +352,27 @@ int bt_mesh_stop_ble_scan(void)
     return 0;
 }
 
+bool bt_mesh_ble_scan_state_get(void)
+{
+    return ble_scan_en;
+}
+
 static void inline callback_ble_adv_pkt(const bt_mesh_addr_t *addr,
                                         uint8_t adv_type, uint8_t data[],
                                         uint16_t length, int8_t rssi)
 {
+#if !CONFIG_BLE_MESH_USE_BLE_50
+    bt_mesh_ble_adv_report_t adv_rpt = {0};
     if (ble_scan_en) {
-        bt_mesh_ble_scan_cb_evt_to_btc(addr, adv_type, data, length, rssi);
+        memcpy(adv_rpt.addr, addr->val, BD_ADDR_LEN);
+        adv_rpt.addr_type = addr->type;
+        adv_rpt.adv_type = adv_type;
+        adv_rpt.length = length;
+        adv_rpt.data = data;
+        adv_rpt.rssi = rssi;
+        bt_mesh_ble_scan_cb_evt_to_btc(&adv_rpt);
     }
+#endif
 }
 #endif /* CONFIG_BLE_MESH_SUPPORT_BLE_SCAN */
 
@@ -361,11 +394,11 @@ static bool rpr_ext_scan_handle_adv_pkt(const bt_mesh_addr_t *addr,
 }
 #endif /* CONFIG_BLE_MESH_RPR_SRV */
 
-static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
-                            int8_t rssi, uint8_t adv_type,
-                            struct net_buf_simple *buf,
-                            uint8_t scan_rsp_len)
+static void bt_mesh_scan_cb(struct bt_mesh_adv_report *adv_rpt)
 {
+    struct net_buf_simple_state buf_state = {0};
+    struct net_buf_simple *buf = &adv_rpt->adv_data;
+
 #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_CLIENT || \
      CONFIG_BLE_MESH_PROXY_SOLIC_PDU_RX
@@ -376,19 +409,43 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
     uint16_t adv_len = buf->len;
 #endif
 
-    if (adv_type != BLE_MESH_ADV_NONCONN_IND && adv_type != BLE_MESH_ADV_IND) {
+    net_buf_simple_save(buf, &buf_state);
+
+    if (adv_rpt->adv_type != BLE_MESH_ADV_NONCONN_IND &&
+       adv_rpt->adv_type != BLE_MESH_ADV_IND
+#if CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_RPR_SRV_ACTIVE_SCAN
+       && adv_rpt->adv_type != BLE_MESH_ADV_SCAN_RSP
+#endif
+       ) {
 #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
-        callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi);
+        callback_ble_adv_pkt(&adv_rpt->addr, adv_rpt->adv_type, adv_data, adv_len, adv_rpt->rssi);
 #endif
+        net_buf_simple_restore(buf, &buf_state);
         return;
     }
 
     BT_DBG("scan, len %u: %s", buf->len, bt_hex(buf->data, buf->len));
 
 #if (CONFIG_BLE_MESH_PROVISIONER || CONFIG_BLE_MESH_RPR_SRV)
-    unprov_dev_addr = addr;
-    current_adv_type = adv_type;
+    unprov_dev_addr = &adv_rpt->addr;
+    current_adv_type = adv_rpt->adv_type;
+#endif
+
+#if CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_RPR_SRV_ACTIVE_SCAN
+    if (adv_rpt->adv_type == BLE_MESH_ADV_SCAN_RSP) {
+        /**
+         * scan response is only visible for remote provisioning extend scan.
+        */
+        if (rpr_ext_scan_handle_adv_pkt(&adv_rpt->addr, adv_data, adv_len)) {
+            return;
+        } else {
+#if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
+            callback_ble_adv_pkt(&adv_rpt->addr, adv_rpt->adv_type, adv_data, adv_len, adv_rpt->rssi);
 #endif
+            net_buf_simple_restore(buf, &buf_state);
+        }
+    }
+#endif /* CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_RPR_SRV_ACTIVE_SCAN */
 
     while (buf->len > 1) {
         struct net_buf_simple_state state;
@@ -398,16 +455,18 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
         /* Check for early termination */
         if (len == 0U) {
 #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
-            callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi);
+            callback_ble_adv_pkt(&adv_rpt->addr, adv_rpt->adv_type, adv_data, adv_len, adv_rpt->rssi);
 #endif
+            net_buf_simple_restore(buf, &buf_state);
             return;
         }
 
         if (len > buf->len) {
             BT_DBG("AD malformed");
 #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
-            callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi);
+            callback_ble_adv_pkt(&adv_rpt->addr, adv_rpt->adv_type, adv_data, adv_len, adv_rpt->rssi);
 #endif
+            net_buf_simple_restore(buf, &buf_state);
             return;
         }
 
@@ -418,14 +477,17 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
         buf->len = len - 1;
 
         if ((type == BLE_MESH_DATA_MESH_PROV || type == BLE_MESH_DATA_MESH_MESSAGE ||
-            type == BLE_MESH_DATA_MESH_BEACON) && (adv_type != BLE_MESH_ADV_NONCONN_IND)) {
-            BT_DBG("Ignore mesh packet (type 0x%02x) with adv_type 0x%02x", type, adv_type);
+            type == BLE_MESH_DATA_MESH_BEACON) && (adv_rpt->adv_type != BLE_MESH_ADV_NONCONN_IND)) {
+            BT_DBG("Ignore mesh packet (type 0x%02x) with adv_type 0x%02x", type, adv_rpt->adv_type);
             return;
         }
 
         switch (type) {
         case BLE_MESH_DATA_MESH_MESSAGE:
-            bt_mesh_net_recv(buf, rssi, BLE_MESH_NET_IF_ADV);
+            struct bt_mesh_net_rx rx = {
+                .ctx.recv_rssi = adv_rpt->rssi,
+            };
+            bt_mesh_generic_net_recv(buf, &rx, BLE_MESH_NET_IF_ADV);
             break;
 #if CONFIG_BLE_MESH_PB_ADV
         case BLE_MESH_DATA_MESH_PROV:
@@ -438,7 +500,7 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
             break;
 #endif /* CONFIG_BLE_MESH_PB_ADV */
         case BLE_MESH_DATA_MESH_BEACON:
-            bt_mesh_beacon_recv(buf, rssi);
+            bt_mesh_beacon_recv(buf, adv_rpt->rssi);
             break;
 #if (CONFIG_BLE_MESH_PROVISIONER && CONFIG_BLE_MESH_PB_GATT) || \
      CONFIG_BLE_MESH_GATT_PROXY_CLIENT || \
@@ -447,8 +509,9 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
             if (!adv_flags_valid(buf)) {
                 BT_DBG("Adv Flags mismatch, ignore this adv pkt");
 #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
-                callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi);
+                callback_ble_adv_pkt(&adv_rpt->addr, adv_rpt->adv_type, adv_data, adv_len, adv_rpt->rssi);
 #endif
+                net_buf_simple_restore(buf, &buf_state);
                 return;
             }
             break;
@@ -456,7 +519,7 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
             if (!adv_service_uuid_valid(buf, &uuid)) {
                 BT_DBG("Adv Service UUID mismatch, ignore this adv pkt");
 #if CONFIG_BLE_MESH_RPR_SRV
-                if (rpr_ext_scan_handle_adv_pkt(addr, adv_data, adv_len)) {
+                if (rpr_ext_scan_handle_adv_pkt(&adv_rpt->addr, adv_data, adv_len)) {
                     /* If handled as extended scan report successfully, then not
                      * notify to the application layer as normal BLE adv packet.
                      */
@@ -464,18 +527,19 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
                 }
 #endif
 #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
-                callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi);
+                callback_ble_adv_pkt(&adv_rpt->addr, adv_rpt->adv_type, adv_data, adv_len, adv_rpt->rssi);
 #endif
+                net_buf_simple_restore(buf, &buf_state);
                 return;
             }
             break;
         case BLE_MESH_DATA_SVC_DATA16:
-            handle_adv_service_data(buf, addr, uuid, rssi);
+            handle_adv_service_data(buf, &adv_rpt->addr, uuid, adv_rpt->rssi);
             break;
 #endif
         default:
 #if CONFIG_BLE_MESH_RPR_SRV
-            if (rpr_ext_scan_handle_adv_pkt(addr, adv_data, adv_len)) {
+            if (rpr_ext_scan_handle_adv_pkt(&adv_rpt->addr, adv_data, adv_len)) {
                 /* If handled as extended scan report successfully, then not
                  * notify to the application layer as normal BLE adv packet.
                  */
@@ -483,44 +547,21 @@ static void bt_mesh_scan_cb(const bt_mesh_addr_t *addr,
             }
 #endif
 #if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
-            callback_ble_adv_pkt(addr, adv_type, adv_data, adv_len, rssi);
+            callback_ble_adv_pkt(&adv_rpt->addr, adv_rpt->adv_type, adv_data, adv_len, adv_rpt->rssi);
 #endif
+            net_buf_simple_restore(buf, &buf_state);
             return;
         }
 
         net_buf_simple_restore(buf, &state);
         net_buf_simple_pull(buf, len);
     }
-#if CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_RPR_SRV_ACTIVE_SCAN
-    if (scan_rsp_len != 0) {
-        /**
-         * scan response is only visible for remote provisioning extend scan.
-        */
-        rpr_ext_scan_handle_adv_pkt(addr, adv_data + adv_len, scan_rsp_len);
-    }
-#endif /* CONFIG_BLE_MESH_RPR_SRV && CONFIG_BLE_MESH_RPR_SRV_ACTIVE_SCAN */
 }
 
 int bt_mesh_scan_enable(void)
 {
     int err = 0;
 
-    struct bt_mesh_scan_param scan_param = {
-#if CONFIG_BLE_MESH_RPR_SRV_ACTIVE_SCAN
-        .type       = BLE_MESH_SCAN_ACTIVE,
-#else
-        .type       = BLE_MESH_SCAN_PASSIVE,
-#endif
-#if CONFIG_BLE_MESH_USE_DUPLICATE_SCAN
-        .filter_dup = BLE_MESH_SCAN_FILTER_DUP_ENABLE,
-#else
-        .filter_dup = BLE_MESH_SCAN_FILTER_DUP_DISABLE,
-#endif
-        .interval   = SCAN_INTERVAL,
-        .window     = SCAN_WINDOW,
-        .scan_fil_policy = BLE_MESH_SP_ADV_ALL,
-    };
-
     err = bt_le_scan_start(&scan_param, bt_mesh_scan_cb);
     if (err && err != -EALREADY) {
         BT_ERR("starting scan failed (err %d)", err);
@@ -543,6 +584,49 @@ int bt_mesh_scan_disable(void)
     return 0;
 }
 
+int bt_mesh_scan_param_update(struct bt_mesh_scan_param *param)
+{
+    int err = 0;
+
+    if (param == NULL ||
+        param->interval == 0 ||
+        param->interval < param->window) {
+        return -EINVAL;
+    }
+
+    scan_param.interval = param->interval;
+    scan_param.window = param->window;
+
+    err = bt_le_scan_stop();
+    if (err) {
+        if (err == -EALREADY) {
+            BT_INFO("New scan parameters will take effect after scan starts");
+            return 0;
+        }
+        BT_ERR("Failed to stop scan (err %d)", err);
+        return err;
+    }
+
+    /**
+     * Since the user only needs to set the scan interval
+     * and scan window parameters, only the interval and
+     * window parameters in the `param` are correct.
+     *
+     * For the aforementioned reason, when updating the scan
+     * parameters, the other parameters also need to be set
+     * correctly, and these other parameters are saved in the
+     * `scan_param`. Therefore, `scan_param` must be used instead
+     * of `param` here.
+     */
+    err = bt_le_scan_start(&scan_param, bt_mesh_scan_cb);
+    if (err && err != -EALREADY) {
+        BT_ERR("Failed to start scan (err %d)", err);
+        return err;
+    }
+
+    return 0;
+}
+
 #if CONFIG_BLE_MESH_TEST_USE_WHITE_LIST
 int bt_mesh_scan_with_wl_enable(void)
 {
diff --git a/components/bt/esp_ble_mesh/core/scan.h b/components/bt/esp_ble_mesh/core/scan.h
index b7d0555c834..612751d3f20 100644
--- a/components/bt/esp_ble_mesh/core/scan.h
+++ b/components/bt/esp_ble_mesh/core/scan.h
@@ -2,7 +2,7 @@
 
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileContributor: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,16 +33,22 @@ int bt_mesh_scan_enable(void);
 
 int bt_mesh_scan_disable(void);
 
+int bt_mesh_scan_param_update(struct bt_mesh_scan_param *scan_param);
+
 int bt_mesh_scan_with_wl_enable(void);
 
 struct bt_mesh_ble_scan_param {
     uint32_t duration;
 };
 
+#if CONFIG_BLE_MESH_SUPPORT_BLE_SCAN
 int bt_mesh_start_ble_scan(struct bt_mesh_ble_scan_param *param);
 
 int bt_mesh_stop_ble_scan(void);
 
+bool bt_mesh_ble_scan_state_get(void);
+#endif /* CONFIG_BLE_MESH_SUPPORT_BLE_SCAN */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/bt/esp_ble_mesh/core/storage/settings.c b/components/bt/esp_ble_mesh/core/storage/settings.c
index 34a40d2d303..ad223201769 100644
--- a/components/bt/esp_ble_mesh/core/storage/settings.c
+++ b/components/bt/esp_ble_mesh/core/storage/settings.c
@@ -22,7 +22,9 @@
 #include "pvnr_mgmt.h"
 #include "prov_pvnr.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 /* BLE Mesh NVS Key and corresponding data struct.
  * Note: The length of nvs key must be <= 15.
diff --git a/components/bt/esp_ble_mesh/core/tag.h b/components/bt/esp_ble_mesh/core/tag.h
new file mode 100644
index 00000000000..d1b9831094a
--- /dev/null
+++ b/components/bt/esp_ble_mesh/core/tag.h
@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _BLE_MESH_v11_TAG_H_
+#define _BLE_MESH_v11_TAG_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "mesh.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !CONFIG_BLE_MESH_V11_SUPPORT
+
+/* TAG - additional metadata */
+#define BLE_MESH_TAG_SEND_SEGMENTED     BIT(0)
+#define BLE_MESH_TAG_IMMUTABLE_CRED     BIT(1)
+#define BLE_MESH_TAG_RELAY              BIT(3)
+#define BLE_MESH_TAG_FRIENDSHIP         BIT(4)
+
+static inline bool bt_mesh_tag_send_segmented(uint8_t tag)
+{
+    return (tag & BLE_MESH_TAG_SEND_SEGMENTED);
+}
+
+static inline bool bt_mesh_tag_immutable_cred(uint8_t tag)
+{
+    return (tag & BLE_MESH_TAG_IMMUTABLE_CRED);
+}
+
+static inline bool bt_mesh_tag_relay(uint8_t tag)
+{
+    return (tag & BLE_MESH_TAG_RELAY);
+}
+
+static inline bool bt_mesh_tag_friendship(uint8_t tag)
+{
+    return (tag & BLE_MESH_TAG_FRIENDSHIP);
+}
+
+#endif /* !CONFIG_BLE_MESH_V11_SUPPORT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BLE_MESH_v11_TAG_H_ */
diff --git a/components/bt/esp_ble_mesh/core/transport.c b/components/bt/esp_ble_mesh/core/transport.c
index 70589706dae..4f125b99df7 100644
--- a/components/bt/esp_ble_mesh/core/transport.c
+++ b/components/bt/esp_ble_mesh/core/transport.c
@@ -11,6 +11,7 @@
 #include <errno.h>
 
 #include "crypto.h"
+#include "tag.h"
 #include "adv.h"
 #include "mesh.h"
 #include "lpn.h"
@@ -26,7 +27,9 @@
 #include "mesh/cfg_srv.h"
 #include "heartbeat.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 /* The transport layer needs at least three buffers for itself to avoid
  * deadlocks. Ensure that there are a sufficient number of advertising
@@ -1039,18 +1042,18 @@ static int ctl_recv(struct bt_mesh_net_rx *rx, uint8_t hdr,
         return 0;
     }
 
-    if (IS_ENABLED(CONFIG_BLE_MESH_DF_SRV)) {
-        switch (ctl_op) {
-        case TRANS_CTL_OP_PATH_REQ:
-        case TRANS_CTL_OP_PATH_REPLY:
-        case TRANS_CTL_OP_PATH_CFM:
-        case TRANS_CTL_OP_PATH_ECHO_REQ:
-        case TRANS_CTL_OP_PATH_ECHO_REPLY:
-        case TRANS_CTL_OP_DEP_NODE_UPDATE:
-        case TRANS_CTL_OP_PATH_REQ_SOLIC:
-            return bt_mesh_directed_forwarding_ctl_recv(ctl_op, rx, buf);
-        }
+#if CONFIG_BLE_MESH_DF_SRV
+    switch (ctl_op) {
+    case TRANS_CTL_OP_PATH_REQ:
+    case TRANS_CTL_OP_PATH_REPLY:
+    case TRANS_CTL_OP_PATH_CFM:
+    case TRANS_CTL_OP_PATH_ECHO_REQ:
+    case TRANS_CTL_OP_PATH_ECHO_REPLY:
+    case TRANS_CTL_OP_DEP_NODE_UPDATE:
+    case TRANS_CTL_OP_PATH_REQ_SOLIC:
+        return bt_mesh_directed_forwarding_ctl_recv(ctl_op, rx, buf);
     }
+#endif
 
     if (IS_ENABLED(CONFIG_BLE_MESH_FRIEND) && !bt_mesh_lpn_established()) {
         switch (ctl_op) {
@@ -1759,8 +1762,6 @@ void bt_mesh_trans_init(void)
 {
     int i;
 
-    bt_mesh_sar_init();
-
     for (i = 0; i < ARRAY_SIZE(seg_tx); i++) {
         k_delayed_work_init(&seg_tx[i].rtx_timer, seg_retransmit);
     }
diff --git a/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h b/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h
index 71a02314c81..d8e80b196ff 100644
--- a/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h
+++ b/components/bt/esp_ble_mesh/lib/include/mesh_v1.1/utils.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/bt/esp_ble_mesh/lib/lib b/components/bt/esp_ble_mesh/lib/lib
index cba99c5a2e7..031cc5d3b8c 160000
--- a/components/bt/esp_ble_mesh/lib/lib
+++ b/components/bt/esp_ble_mesh/lib/lib
@@ -1 +1 @@
-Subproject commit cba99c5a2e7f5d4bccb04e8f3f968dc888bb5667
+Subproject commit 031cc5d3b8ca6ada831ae1419219fb2895c37907
diff --git a/components/bt/esp_ble_mesh/models/client/client_common.c b/components/bt/esp_ble_mesh/models/client/client_common.c
index db87851613d..7e5448707d9 100644
--- a/components/bt/esp_ble_mesh/models/client/client_common.c
+++ b/components/bt/esp_ble_mesh/models/client/client_common.c
@@ -14,7 +14,9 @@
 #include "mesh/client_common.h"
 #include "mesh/common.h"
 
+#if CONFIG_BLE_MESH_V11_SUPPORT
 #include "mesh_v1.1/utils.h"
+#endif
 
 #define HCI_TIME_FOR_START_ADV  K_MSEC(5)   /* Three adv related hci commands may take 4 ~ 5ms */
 
diff --git a/components/bt/host/bluedroid/api/esp_gap_ble_api.c b/components/bt/host/bluedroid/api/esp_gap_ble_api.c
index d37f3724be8..a4122529799 100644
--- a/components/bt/host/bluedroid/api/esp_gap_ble_api.c
+++ b/components/bt/host/bluedroid/api/esp_gap_ble_api.c
@@ -1049,6 +1049,23 @@ esp_err_t esp_ble_gap_set_privacy_mode(esp_ble_addr_type_t addr_type, esp_bd_add
             == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
 }
 
+esp_err_t esp_ble_gap_set_csa_support(uint8_t csa_select)
+{
+    btc_msg_t msg;
+    btc_ble_gap_args_t arg;
+
+    ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
+
+    msg.sig = BTC_SIG_API_CALL;
+    msg.pid = BTC_PID_GAP_BLE;
+    msg.act = BTC_GAP_BLE_SET_CSA_SUPPORT;
+
+    arg.set_csa_support.csa_select = csa_select;
+
+    return (btc_transfer_context(&msg, &arg, sizeof(btc_ble_gap_args_t), NULL, NULL)
+            == BT_STATUS_SUCCESS ? ESP_OK : ESP_FAIL);
+}
+
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
 
 esp_err_t esp_ble_gap_read_phy(esp_bd_addr_t bd_addr)
diff --git a/components/bt/host/bluedroid/api/esp_gattc_api.c b/components/bt/host/bluedroid/api/esp_gattc_api.c
index 5f078b28098..904fb32a0cc 100644
--- a/components/bt/host/bluedroid/api/esp_gattc_api.c
+++ b/components/bt/host/bluedroid/api/esp_gattc_api.c
@@ -363,10 +363,14 @@ esp_err_t esp_ble_gattc_read_char (esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
+    if (handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_READ_CHAR;
@@ -400,10 +404,14 @@ esp_err_t esp_ble_gattc_read_by_type (esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
+    if (start_handle == 0 || end_handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_READ_BY_TYPE;
@@ -432,7 +440,7 @@ esp_err_t esp_ble_gattc_read_multiple(esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
@@ -468,7 +476,7 @@ esp_err_t esp_ble_gattc_read_multiple_variable(esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
@@ -504,10 +512,14 @@ esp_err_t esp_ble_gattc_read_char_descr (esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
+    if (handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_READ_CHAR_DESCR;
@@ -537,10 +549,14 @@ esp_err_t esp_ble_gattc_write_char(esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
+    if (handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_WRITE_CHAR;
@@ -576,10 +592,14 @@ esp_err_t esp_ble_gattc_write_char_descr (esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
+    if (handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_WRITE_CHAR_DESCR;
@@ -615,10 +635,14 @@ esp_err_t esp_ble_gattc_prepare_write(esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
+    if (handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_PREPARE_WRITE;
@@ -652,10 +676,14 @@ esp_err_t esp_ble_gattc_prepare_write_char_descr(esp_gatt_if_t gattc_if,
     }
 
     if (L2CA_CheckIsCongest(L2CAP_ATT_CID, p_tcb->peer_bda)) {
-        LOG_DEBUG("%s, the l2cap chanel is congest.", __func__);
+        LOG_DEBUG("%s, the l2cap channel is congest.", __func__);
         return ESP_FAIL;
     }
 
+    if (handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_PREPARE_WRITE_CHAR_DESCR;
@@ -694,6 +722,10 @@ esp_err_t esp_ble_gattc_register_for_notify (esp_gatt_if_t gattc_if,
 
     ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
 
+    if (handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_REG_FOR_NOTIFY;
@@ -712,6 +744,10 @@ esp_err_t esp_ble_gattc_unregister_for_notify (esp_gatt_if_t gattc_if,
 
     ESP_BLUEDROID_STATUS_CHECK(ESP_BLUEDROID_STATUS_ENABLED);
 
+    if (handle == 0) {
+        return ESP_GATT_INVALID_HANDLE;
+    }
+
     msg.sig = BTC_SIG_API_CALL;
     msg.pid = BTC_PID_GATTC;
     msg.act = BTC_GATTC_ACT_UNREG_FOR_NOTIFY;
diff --git a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h
index 589945b3175..83fea16a99c 100644
--- a/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h
+++ b/components/bt/host/bluedroid/api/include/api/esp_gap_ble_api.h
@@ -229,6 +229,7 @@ typedef enum {
     ESP_GAP_BLE_ADD_DEV_TO_RESOLVING_LIST_COMPLETE_EVT,          /*!< when add a device to the resolving list completes, the event comes*/
     ESP_GAP_BLE_VENDOR_CMD_COMPLETE_EVT,                         /*!< When vendor hci command complete, the event comes */
     ESP_GAP_BLE_SET_PRIVACY_MODE_COMPLETE_EVT,                   /*!< When set privacy mode complete, the event comes */
+    ESP_GAP_BLE_SET_CSA_SUPPORT_COMPLETE_EVT,                    /*!< When set CSA support complete, the event comes */
     ESP_GAP_BLE_EVT_MAX,                                         /*!< when maximum advertising event complete, the event comes */
 } esp_gap_ble_cb_event_t;
 
@@ -1572,6 +1573,12 @@ typedef union {
     struct ble_set_privacy_mode_cmpl_evt_param {
         esp_bt_status_t status;                     /*!< Indicate privacy mode set operation success status */
     } set_privacy_mode_cmpl;                        /*!< Event parameter of ESP_GAP_BLE_SET_PRIVACY_MODE_COMPLETE_EVT */
+    /**
+     * @brief ESP_GAP_BLE_SET_CSA_SUPPORT_COMPLETE_EVT
+     */
+    struct ble_set_csa_support_cmpl_evt_param {
+        esp_bt_status_t status;                     /*!< Indicate CSA support set operation success status */
+    } set_csa_support_cmpl;                        /*!< Event parameter of ESP_GAP_BLE_SET_CSA_SUPPORT_COMPLETE_EVT */
 } esp_ble_gap_cb_param_t;
 
 /**
@@ -2744,6 +2751,23 @@ esp_err_t esp_ble_gap_vendor_command_send(esp_ble_vendor_cmd_params_t *vendor_cm
  */
 esp_err_t esp_ble_gap_set_privacy_mode(esp_ble_addr_type_t addr_type, esp_bd_addr_t addr, esp_ble_privacy_mode_t mode);
 
+/**
+ * @brief           This function is used to set which channel selection algorithm(CSA) is supported.
+ *
+ * @note            - This function should only be used when there are BLE compatibility issues about channel hopping after connected.
+ *                    For example, if the peer device only supports CSA#1, this function can be called to make the Controller use CSA#1.
+ *                  - This function is not supported on ESP32.
+ *
+ * @param[in]       csa_select: 0: Channel Selection Algorighm will be selected by Controller
+ *                              1: Select the LE Channel Selection Algorighm #1
+ *                              2: Select the LE Channel Selection Algorighm #2
+ *
+ * @return
+ *                  - ESP_OK : success
+ *                  - other  : failed
+ */
+esp_err_t esp_ble_gap_set_csa_support(uint8_t csa_select);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c
index 0ff6dc6c2ca..58d545d3b94 100644
--- a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c
+++ b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c
@@ -5859,6 +5859,12 @@ void bta_dm_ble_gap_set_privacy_mode(tBTA_DM_MSG *p_data)
                         p_data->ble_set_privacy_mode.privacy_mode, p_data->ble_set_privacy_mode.p_cback);
 }
 
+void bta_dm_ble_gap_set_csa_support(tBTA_DM_MSG *p_data)
+{
+    APPL_TRACE_API("%s, csa_select = %d", __func__, p_data->ble_set_csa_support.csa_select);
+    BTM_BleSetCsaSupport(p_data->ble_set_csa_support.csa_select, p_data->ble_set_csa_support.p_cback);
+}
+
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
 void bta_dm_ble_gap_dtm_enhance_tx_start(tBTA_DM_MSG *p_data)
 {
diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c
index 7ec61ee9994..71555246373 100644
--- a/components/bt/host/bluedroid/bta/dm/bta_dm_api.c
+++ b/components/bt/host/bluedroid/bta/dm/bta_dm_api.c
@@ -3025,6 +3025,19 @@ void BTA_DmClearRandAddress(void)
     }
 }
 
+void BTA_DmBleGapSetCsaSupport(uint8_t csa_select, tBTA_SET_CSA_SUPPORT_CMPL_CBACK *p_callback)
+{
+    tBTA_DM_API_BLE_SET_CSA_SUPPORT *p_msg;
+
+    if ((p_msg = (tBTA_DM_API_BLE_SET_CSA_SUPPORT *)osi_malloc(sizeof(tBTA_DM_API_BLE_SET_CSA_SUPPORT)))
+        != NULL) {
+        p_msg->hdr.event = BTA_DM_API_BLE_SET_CSA_SUPPORT_EVT;
+        p_msg->csa_select = csa_select;
+        p_msg->p_cback = p_callback;
+        bta_sys_sendmsg(p_msg);
+    }
+}
+
 /*******************************************************************************
 **
 ** Function         BTA_VendorInit
diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c b/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c
index a4792ce8469..81bbd4667f8 100644
--- a/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c
+++ b/components/bt/host/bluedroid/bta/dm/bta_dm_cfg.c
@@ -151,13 +151,13 @@ tBTA_DM_PM_TYPE_QUALIFIER tBTA_DM_PM_SPEC bta_dm_pm_spec[BTA_DM_NUM_PM_SPEC] = {
         (BTA_DM_PM_SSR2),                                              /* the SSR entry */
 #endif
         {
-            {{BTA_DM_PM_SNIFF_A2DP_IDX,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* conn open sniff  */
+            {{BTA_DM_PM_SNIFF_AG_OPEN_IDX,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* conn open sniff  */
             {{BTA_DM_PM_NO_PREF,   0},   {BTA_DM_PM_NO_ACTION, 0}},   /* conn close  */
             {{BTA_DM_PM_NO_ACTION, 0},   {BTA_DM_PM_NO_ACTION, 0}},   /* app open */
             {{BTA_DM_PM_NO_ACTION, 0},   {BTA_DM_PM_NO_ACTION, 0}},   /* app close */
             {{BTA_DM_PM_SNIFF_SCO_OPEN_IDX, 7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* sco open, active */
-            {{BTA_DM_PM_SNIFF_A2DP_IDX,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* sco close sniff  */
-            {{BTA_DM_PM_NO_ACTION, 0},   {BTA_DM_PM_NO_ACTION, 0}},   /* idle */
+            {{BTA_DM_PM_SNIFF_SCO_CLOSE_IDX,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* sco close sniff  */
+            {{BTA_DM_PM_SNIFF_AG_IDLE_IDX,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* idle */
             {{BTA_DM_PM_ACTIVE,    0},   {BTA_DM_PM_NO_ACTION, 0}},   /* busy */
             {{BTA_DM_PM_RETRY,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}}    /* mode change retry */
         }
@@ -231,9 +231,9 @@ tBTA_DM_PM_TYPE_QUALIFIER tBTA_DM_PM_SPEC bta_dm_pm_spec[BTA_DM_NUM_PM_SPEC] = {
             {{BTA_DM_PM_NO_PREF,   0},   {BTA_DM_PM_NO_ACTION, 0}},   /* conn close  */
             {{BTA_DM_PM_NO_ACTION, 0},   {BTA_DM_PM_NO_ACTION, 0}},   /* app open */
             {{BTA_DM_PM_NO_ACTION, 0},   {BTA_DM_PM_NO_ACTION, 0}},   /* app close */
-            {{BTA_DM_PM_NO_ACTION, 0},   {BTA_DM_PM_NO_ACTION, 0}},   /* sco open, active */
-            {{BTA_DM_PM_NO_ACTION, 0},   {BTA_DM_PM_NO_ACTION, 0}},   /* sco close sniff  */
-            {{BTA_DM_PM_NO_ACTION, 0},   {BTA_DM_PM_NO_ACTION, 0}},   /* idle */
+            {{BTA_DM_PM_SNIFF3, 7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* sco open, active */
+            {{BTA_DM_PM_SNIFF,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* sco close sniff  */
+            {{BTA_DM_PM_SNIFF,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}},   /* idle */
             {{BTA_DM_PM_ACTIVE,    0},   {BTA_DM_PM_NO_ACTION, 0}},   /* busy */
             {{BTA_DM_PM_RETRY,  7000 + BTA_DM_PM_SPEC_TO_OFFSET},   {BTA_DM_PM_NO_ACTION, 0}}    /* mode change retry */
         }
@@ -409,7 +409,7 @@ tBTA_DM_SSR_SPEC bta_dm_ssr_spec[] = {
     /*max_lat, min_rmt_to, min_loc_to*/
     {0,      0, 0},     /* BTA_DM_PM_SSR0 - do not use SSR */
     {0,      0, 2},     /* BTA_DM_PM_SSR1 - HH, can NOT share entry with any other profile,
-                           seting default max latency and min remote timeout as 0,
+                           setting default max latency and min remote timeout as 0,
                            and always read individual device preference from HH module */
     {1200,   2, 2},     /* BTA_DM_PM_SSR2 - others (as long as sniff is allowed)*/
     {360,  160, 1600}   /* BTA_DM_PM_SSR3 - HD */
@@ -466,7 +466,7 @@ tBTA_DM_EIR_CONF bta_dm_eir_cfg = {
     {   /* mask of UUID list in EIR */
         0xFFFFFFFF, /* LSB is the first UUID of the first 32 UUIDs in BTM_EIR_UUID_LKUP_TBL */
         0xFFFFFFFF  /* LSB is the first UUID of the next 32 UUIDs in BTM_EIR_UUID_LKUP_TBL */
-        /* BTM_EIR_UUID_LKUP_TBL can be overrided */
+        /* BTM_EIR_UUID_LKUP_TBL can be overridden */
     },
 #endif  // BTA_EIR_CANNED_UUID_LIST
     FALSE,  /* Not included TX power*/
diff --git a/components/bt/host/bluedroid/bta/dm/bta_dm_main.c b/components/bt/host/bluedroid/bta/dm/bta_dm_main.c
index 99736d8ecec..2d747f5b078 100644
--- a/components/bt/host/bluedroid/bta/dm/bta_dm_main.c
+++ b/components/bt/host/bluedroid/bta/dm/bta_dm_main.c
@@ -235,6 +235,7 @@ const tBTA_DM_ACTION bta_dm_action[BTA_DM_MAX_EVT] = {
     bta_dm_ble_gap_set_rpa_timeout, /* BTA_DM_API_SET_RPA_TIMEOUT_EVT */
     bta_dm_ble_gap_add_dev_to_resolving_list, /* BTA_DM_API_ADD_DEV_TO_RESOLVING_LIST_EVT */
     bta_dm_ble_gap_set_privacy_mode, /* BTA_DM_API_SET_PRIVACY_MODE_EVT */
+    bta_dm_ble_gap_set_csa_support, /* BTA_DM_API_BLE_SET_CSA_SUPPORT_EVT */
 #endif
 };
 
diff --git a/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h b/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h
index 862393fe8ab..29af35c6dc5 100644
--- a/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h
+++ b/components/bt/host/bluedroid/bta/dm/include/bta_dm_int.h
@@ -226,6 +226,7 @@ enum {
     BTA_DM_API_SET_RPA_TIMEOUT_EVT,
     BTA_DM_API_ADD_DEV_TO_RESOLVING_LIST_EVT,
     BTA_DM_API_SET_PRIVACY_MODE_EVT,
+    BTA_DM_API_BLE_SET_CSA_SUPPORT_EVT,
 #endif
     BTA_DM_MAX_EVT
 };
@@ -959,6 +960,12 @@ typedef struct {
     tBTA_SET_PRIVACY_MODE_CMPL_CBACK    *p_cback;
 } tBTA_DM_API_SET_PRIVACY_MODE;
 
+typedef struct {
+    BT_HDR                              hdr;
+    UINT8                               csa_select;
+    tBTA_SET_CSA_SUPPORT_CMPL_CBACK     *p_cback;
+} tBTA_DM_API_BLE_SET_CSA_SUPPORT;
+
 #endif /* BLE_INCLUDED */
 
 /* data type for BTA_DM_API_REMOVE_ACL_EVT */
@@ -1365,6 +1372,7 @@ typedef union {
     tBTA_DM_API_BLE_DTM_STOP        dtm_stop;
     tBTA_DM_API_CLEAR_ADV           ble_clear_adv;
     tBTA_DM_API_SET_PRIVACY_MODE    ble_set_privacy_mode;
+    tBTA_DM_API_BLE_SET_CSA_SUPPORT ble_set_csa_support;
 #endif
 
     tBTA_DM_API_REMOVE_ACL              remove_acl;
@@ -1817,6 +1825,7 @@ extern void bta_dm_ble_gap_clear_adv(tBTA_DM_MSG *p_data);
 extern void bta_dm_ble_gap_set_rpa_timeout(tBTA_DM_MSG *p_data);
 extern void bta_dm_ble_gap_add_dev_to_resolving_list(tBTA_DM_MSG *p_data);
 extern void bta_dm_ble_gap_set_privacy_mode(tBTA_DM_MSG *p_data);
+extern void bta_dm_ble_gap_set_csa_support(tBTA_DM_MSG *p_data);
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
 extern void bta_dm_ble_gap_dtm_enhance_tx_start(tBTA_DM_MSG *p_data);
 extern void bta_dm_ble_gap_dtm_enhance_rx_start(tBTA_DM_MSG *p_data);
diff --git a/components/bt/host/bluedroid/bta/gatt/bta_gattc_main.c b/components/bt/host/bluedroid/bta/gatt/bta_gattc_main.c
index 0cc55995a5f..47f210c8729 100644
--- a/components/bt/host/bluedroid/bta/gatt/bta_gattc_main.c
+++ b/components/bt/host/bluedroid/bta/gatt/bta_gattc_main.c
@@ -538,9 +538,14 @@ void bta_gattc_deinit(void)
 uint8_t bta_gattc_cl_rcb_active_count(void)
 {
     uint8_t count = 0;
+    uint8_t dm_gattc_uuid[16];
+
+    // When SDP is included, Bluedroid stack will register the DM GATTC application
+    memset(dm_gattc_uuid, 0x87, 16);
 
     for (uint8_t i = 0; i < BTA_GATTC_CL_MAX; i ++) {
-        if (bta_gattc_cb.cl_rcb[i].in_use) {
+        if (bta_gattc_cb.cl_rcb[i].in_use &&
+            memcmp(bta_gattc_cb.cl_rcb[i].app_uuid.uu.uuid128, dm_gattc_uuid, 16)) {
             count++;
         }
     }
diff --git a/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_act.c b/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_act.c
index 0e0c43addf6..930f30a57d4 100644
--- a/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_act.c
+++ b/components/bt/host/bluedroid/bta/hf_client/bta_hf_client_act.c
@@ -511,7 +511,9 @@ void bta_hf_client_rfc_data(tBTA_HF_CLIENT_DATA *p_data)
             break;
         }
 
+        bta_sys_busy(BTA_ID_HS, 1, bta_hf_client_cb.scb.peer_addr);
         bta_hf_client_at_parse(buf, len);
+        bta_sys_idle(BTA_ID_HS, 1, bta_hf_client_cb.scb.peer_addr);
 
         /* no more data to read, we're done */
         if (len < BTA_HF_CLIENT_RFC_READ_MAX) {
diff --git a/components/bt/host/bluedroid/bta/include/bta/bta_api.h b/components/bt/host/bluedroid/bta/include/bta/bta_api.h
index 32dc716bc65..62b0273f100 100644
--- a/components/bt/host/bluedroid/bta/include/bta/bta_api.h
+++ b/components/bt/host/bluedroid/bta/include/bta/bta_api.h
@@ -439,6 +439,8 @@ typedef tBTM_ADD_DEV_TO_RESOLVING_LIST_CMPL_CBACK tBTA_ADD_DEV_TO_RESOLVING_LIST
 
 typedef tBTM_SET_PRIVACY_MODE_CMPL_CBACK tBTA_SET_PRIVACY_MODE_CMPL_CBACK;
 
+typedef tBTM_SET_CSA_SUPPORT_CMPL_CBACK tBTA_SET_CSA_SUPPORT_CMPL_CBACK;
+
 typedef tBTM_CMPL_CB tBTA_CMPL_CB;
 
 typedef tBTM_VSC_CMPL tBTA_VSC_CMPL;
@@ -1351,10 +1353,22 @@ typedef UINT8 tBTA_DM_PM_ACTION;
 #define BTA_DM_PM_SNIFF_HD_IDLE_IDX     BTA_DM_PM_SNIFF4
 #endif
 
+#ifndef BTA_DM_PM_SNIFF_AG_OPEN_IDX
+#define BTA_DM_PM_SNIFF_AG_OPEN_IDX     BTA_DM_PM_SNIFF
+#endif
+
+#ifndef BTA_DM_PM_SNIFF_AG_IDLE_IDX
+#define BTA_DM_PM_SNIFF_AG_IDLE_IDX     BTA_DM_PM_SNIFF
+#endif
+
 #ifndef BTA_DM_PM_SNIFF_SCO_OPEN_IDX
 #define BTA_DM_PM_SNIFF_SCO_OPEN_IDX    BTA_DM_PM_SNIFF3
 #endif
 
+#ifndef BTA_DM_PM_SNIFF_SCO_CLOSE_IDX
+#define BTA_DM_PM_SNIFF_SCO_CLOSE_IDX   BTA_DM_PM_SNIFF
+#endif
+
 #ifndef BTA_DM_PM_SNIFF_HD_ACTIVE_IDX
 #define BTA_DM_PM_SNIFF_HD_ACTIVE_IDX   BTA_DM_PM_SNIFF5
 #endif
@@ -1498,18 +1512,18 @@ typedef UINT8 tBTA_DM_LINK_TYPE;
 #define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_INCLUDE_TX_PWR    (1 << 6)
 #define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_MASK              (0x7F)
 
-#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND        (ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY |\
-                                                        ESP_BLE_GAP_SET_EXT_ADV_PROP_CONNECTABLE |\
-                                                        ESP_BLE_GAP_SET_EXT_ADV_PROP_SCANNABLE)
-#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_LD_DIR     (ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY |\
-                                                        ESP_BLE_GAP_SET_EXT_ADV_PROP_CONNECTABLE |\
-                                                        ESP_BLE_GAP_SET_EXT_ADV_PROP_DIRECTED)
-#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_HD_DIR     (ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY |\
-                                                        ESP_BLE_GAP_SET_EXT_ADV_PROP_CONNECTABLE |\
-                                                        ESP_BLE_GAP_SET_EXT_ADV_PROP_HD_DIRECTED)
-#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_SCAN       (ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY |\
-                                                        ESP_BLE_GAP_SET_EXT_ADV_PROP_SCANNABLE)
-#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_NONCONN    (ESP_BLE_GAP_SET_EXT_ADV_PROP_LEGACY)
+#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_IND        (BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY |\
+                                                           BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_CONNECTABLE |\
+                                                           BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_SCANNABLE)
+#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_LD_DIR     (BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY |\
+                                                           BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_CONNECTABLE |\
+                                                           BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_DIRECTED)
+#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_HD_DIR     (BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY |\
+                                                           BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_CONNECTABLE |\
+                                                           BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_HD_DIRECTED)
+#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_SCAN       (BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY |\
+                                                           BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_SCANNABLE)
+#define BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY_NONCONN    (BTA_DM_BLE_GAP_SET_EXT_ADV_PROP_LEGACY)
 typedef UINT16 tBTA_DM_BLE_EXT_ADV_TYPE_MASK;
 
 
@@ -2909,6 +2923,8 @@ extern void BTA_DmBleDtmStop(tBTA_DTM_CMD_CMPL_CBACK *p_dtm_cmpl_cback);
 
 extern void BTA_DmBleSetPrivacyMode(uint8_t addr_type, BD_ADDR addr, uint8_t privacy_mode, tBTA_SET_PRIVACY_MODE_CMPL_CBACK *p_cback);
 
+extern void BTA_DmBleGapSetCsaSupport(uint8_t csa_select, tBTM_SET_CSA_SUPPORT_CMPL_CBACK *p_callback);
+
 /*******************************************************************************
 **
 ** Function         BTA_DmBleSetStorageParams
diff --git a/components/bt/host/bluedroid/btc/profile/std/avrc/btc_avrc.c b/components/bt/host/bluedroid/btc/profile/std/avrc/btc_avrc.c
index 159731e7837..a783d5e3504 100644
--- a/components/bt/host/bluedroid/btc/profile/std/avrc/btc_avrc.c
+++ b/components/bt/host/bluedroid/btc/profile/std/avrc/btc_avrc.c
@@ -175,8 +175,7 @@ bool btc_avrc_ct_init_p(void)
 bool btc_avrc_tg_connected_p(void)
 {
     return (s_rc_tg_init == BTC_RC_TG_INIT_MAGIC) &&
-           (btc_rc_cb.rc_connected == TRUE) &&
-           (btc_rc_cb.rc_features & BTA_AV_FEAT_RCCT);
+           (btc_rc_cb.rc_connected == TRUE);
 }
 
 bool btc_avrc_ct_connected_p(void)
@@ -507,7 +506,7 @@ static void handle_rc_connect (tBTA_AV_RC_OPEN *p_rc_open)
             btc_avrc_ct_cb_to_app(ESP_AVRC_CT_CONNECTION_STATE_EVT, &param);
         }
 
-        if (p_rc_open->peer_features & BTA_AV_FEAT_RCCT) {
+        if (btc_avrc_tg_init_p()) {
             esp_avrc_tg_cb_param_t param;
             memset(&param, 0, sizeof(esp_avrc_tg_cb_param_t));
             param.conn_stat.connected = true;
@@ -580,7 +579,7 @@ static void handle_rc_disconnect (tBTA_AV_RC_CLOSE *p_rc_close)
         btc_avrc_ct_cb_to_app(ESP_AVRC_CT_CONNECTION_STATE_EVT, &param);
     }
 
-    if (rc_features & BTA_AV_FEAT_RCCT) {
+    if (btc_avrc_tg_init_p()) {
         esp_avrc_tg_cb_param_t param;
         memset(&param, 0, sizeof(esp_avrc_ct_cb_param_t));
         param.conn_stat.connected = false;
@@ -1006,14 +1005,10 @@ void btc_rc_handler(tBTA_AV_EVT event, tBTA_AV *p_data)
                 memcpy(param.conn_stat.remote_bda, btc_rc_cb.rc_addr, sizeof(esp_bd_addr_t));
                 btc_avrc_ct_cb_to_app(ESP_AVRC_CT_CONNECTION_STATE_EVT, &param);
             }
-            if ((p_data->rc_feat.peer_features & BTA_AV_FEAT_RCCT) &&
-                !(old_feats & BTA_AV_FEAT_RCCT)) {
-                esp_avrc_tg_cb_param_t param;
-                memset(&param, 0, sizeof(esp_avrc_ct_cb_param_t));
-                param.conn_stat.connected = true;
-                memcpy(param.conn_stat.remote_bda, btc_rc_cb.rc_addr, sizeof(esp_bd_addr_t));
-                btc_avrc_tg_cb_to_app(ESP_AVRC_TG_CONNECTION_STATE_EVT, &param);
-            }
+            /**
+             * @note ESP_AVRC_TG_CONNECTION_STATE_EVT has been reported on rc connect/disconnect event,
+             * it doesn't rely on the SDP results.
+             */
         } while (0);
         btc_rc_cb.rc_features = p_data->rc_feat.peer_features;
         btc_rc_cb.rc_ct_features = p_data->rc_feat.peer_ct_features;
diff --git a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c
index 464f032417c..ecbea5124c0 100644
--- a/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c
+++ b/components/bt/host/bluedroid/btc/profile/std/gap/btc_gap_ble.c
@@ -958,7 +958,7 @@ static void btc_read_ble_rssi_cmpl_callback(void *p_data)
 }
 
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
-static void btc_ble_5_gap_callback(tBTA_DM_BLE_5_GAP_EVENT event,
+void btc_ble_5_gap_callback(tBTA_DM_BLE_5_GAP_EVENT event,
                                                 tBTA_DM_BLE_5_GAP_CB_PARAMS *params)
 {
     esp_ble_gap_cb_param_t param;
@@ -1363,6 +1363,25 @@ static void btc_ble_set_privacy_mode_callback(UINT8 status)
     }
 }
 
+static void btc_ble_set_csa_support_callback(UINT8 status)
+{
+    esp_ble_gap_cb_param_t param;
+    bt_status_t ret;
+    btc_msg_t msg = {0};
+
+    msg.sig = BTC_SIG_API_CB;
+    msg.pid = BTC_PID_GAP_BLE;
+    msg.act = ESP_GAP_BLE_SET_CSA_SUPPORT_COMPLETE_EVT;
+
+    param.set_csa_support_cmpl.status = btc_btm_status_to_esp_status(status);
+
+    ret = btc_transfer_context(&msg, &param, sizeof(esp_ble_gap_cb_param_t), NULL, NULL);
+
+    if (ret != BT_STATUS_SUCCESS) {
+        BTC_TRACE_ERROR("%s btc_transfer_context failed\n", __func__);
+    }
+}
+
 void btc_get_whitelist_size(uint16_t *length)
 {
     BTM_BleGetWhiteListSize(length);
@@ -2402,6 +2421,9 @@ void btc_gap_ble_call_handler(btc_msg_t *msg)
         btc_ble_set_privacy_mode(arg->set_privacy_mode.addr_type, arg->set_privacy_mode.addr,
             arg->set_privacy_mode.privacy_mode, btc_ble_set_privacy_mode_callback);
         break;
+    case BTC_GAP_BLE_SET_CSA_SUPPORT:
+        BTA_DmBleGapSetCsaSupport(arg->set_csa_support.csa_select, btc_ble_set_csa_support_callback);
+        break;
     default:
         break;
     }
diff --git a/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_ble.h b/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_ble.h
index e540116de19..3157c8c813c 100644
--- a/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_ble.h
+++ b/components/bt/host/bluedroid/btc/profile/std/include/btc_gap_ble.h
@@ -11,11 +11,13 @@
 #include "esp_gap_ble_api.h"
 
 #if BTC_DYNAMIC_MEMORY == TRUE
+#if (BLE_42_FEATURE_SUPPORT == TRUE)
 #include "bta/bta_api.h"
 extern tBTA_BLE_ADV_DATA *gl_bta_adv_data_ptr;
 extern tBTA_BLE_ADV_DATA *gl_bta_scan_rsp_data_ptr;
 #define gl_bta_adv_data     (*gl_bta_adv_data_ptr)
 #define gl_bta_scan_rsp_data    (*gl_bta_scan_rsp_data_ptr)
+#endif // BLE_42_FEATURE_SUPPORT
 #endif
 
 #define BLE_ISVALID_PARAM(x, min, max)  (((x) >= (min) && (x) <= (max)))
@@ -106,6 +108,7 @@ typedef enum {
     BTC_GAP_BLE_ACT_ADD_DEVICE_TO_RESOLVING_LIST,
     BTC_GAP_BLE_ACT_VENDOR_HCI_CMD_EVT,
     BTC_GAP_BLE_SET_PRIVACY_MODE,
+    BTC_GAP_BLE_SET_CSA_SUPPORT,
 } btc_gap_ble_act_t;
 
 /* btc_ble_gap_args_t */
@@ -274,6 +277,10 @@ typedef union {
         esp_bd_addr_t addr;
         uint8_t privacy_mode;
     } set_privacy_mode;
+    // BTC_GAP_BLE_SET_CSA_SUPPORT
+    struct set_csa_support_args {
+        uint8_t csa_select;
+    } set_csa_support;
 } btc_ble_gap_args_t;
 
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
diff --git a/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c b/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c
index 7c5157736a9..12e55c62184 100644
--- a/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c
+++ b/components/bt/host/bluedroid/btc/profile/std/l2cap/btc_l2cap.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -281,7 +281,7 @@ static void close_timeout_handler(void *arg)
     status = btc_transfer_context(&msg, slot->alarm_arg, sizeof(tBTA_JV), NULL, NULL);
 
     if (slot->alarm_arg) {
-        free(slot->alarm_arg);
+        osi_free(slot->alarm_arg);
         slot->alarm_arg = NULL;
     }
 
@@ -832,7 +832,7 @@ void btc_l2cap_cb_handler(btc_msg_t *msg)
             // if rx still has data, delay free slot
             if (slot->close_alarm == NULL && slot->rx.queue && fixed_queue_length(slot->rx.queue) > 0) {
                 tBTA_JV *p_arg = NULL;
-                if ((p_arg = malloc(sizeof(tBTA_JV))) == NULL) {
+                if ((p_arg = osi_malloc(sizeof(tBTA_JV))) == NULL) {
                     param.close.status = ESP_BT_L2CAP_NO_RESOURCE;
                     osi_mutex_unlock(&l2cap_local_param.l2cap_slot_mutex);
                     BTC_TRACE_ERROR("%s unable to malloc slot close_alarm arg!", __func__);
@@ -842,7 +842,7 @@ void btc_l2cap_cb_handler(btc_msg_t *msg)
                 slot->alarm_arg = (void *)p_arg;
                 if ((slot->close_alarm =
                             osi_alarm_new("slot", close_timeout_handler, (void *)slot, VFS_CLOSE_TIMEOUT)) == NULL) {
-                    free(p_arg);
+                    osi_free(p_arg);
                     slot->alarm_arg = NULL;
                     param.close.status = ESP_BT_L2CAP_NO_RESOURCE;
                     osi_mutex_unlock(&l2cap_local_param.l2cap_slot_mutex);
@@ -850,7 +850,7 @@ void btc_l2cap_cb_handler(btc_msg_t *msg)
                     break;
                 }
                 if (osi_alarm_set(slot->close_alarm, VFS_CLOSE_TIMEOUT) != OSI_ALARM_ERR_PASS) {
-                    free(p_arg);
+                    osi_free(p_arg);
                     slot->alarm_arg = NULL;
                     osi_alarm_free(slot->close_alarm);
                     param.close.status = ESP_BT_L2CAP_BUSY;
diff --git a/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c b/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c
index cf334494487..181f2014164 100644
--- a/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c
+++ b/components/bt/host/bluedroid/btc/profile/std/spp/btc_spp.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -1199,7 +1199,7 @@ void btc_spp_cb_handler(btc_msg_t *msg)
                     slot->alarm_arg = (void *)p_arg;
                     if ((slot->close_alarm =
                              osi_alarm_new("slot", close_timeout_handler, (void *)slot, VFS_CLOSE_TIMEOUT)) == NULL) {
-                        free(p_arg);
+                        osi_free(p_arg);
                         slot->alarm_arg = NULL;
                         param.close.status = ESP_SPP_NO_RESOURCE;
                         osi_mutex_unlock(&spp_local_param.spp_slot_mutex);
@@ -1207,7 +1207,7 @@ void btc_spp_cb_handler(btc_msg_t *msg)
                         break;
                     }
                     if (osi_alarm_set(slot->close_alarm, VFS_CLOSE_TIMEOUT) != OSI_ALARM_ERR_PASS) {
-                        free(p_arg);
+                        osi_free(p_arg);
                         slot->alarm_arg = NULL;
                         osi_alarm_free(slot->close_alarm);
                         param.close.status = ESP_SPP_BUSY;
@@ -1488,7 +1488,7 @@ static ssize_t spp_vfs_write(int fd, const void * data, size_t size)
             BTC_TRACE_DEBUG("%s items_waiting:%d, fd:%d\n", __func__, items_waiting, fd);
             osi_mutex_unlock(&spp_local_param.spp_slot_mutex);
 
-            // block untill under water level, be closed or time out
+            // block until under water level, be closed or time out
             tx_event_group_val =
                 xEventGroupWaitBits(spp_local_param.tx_event_group, SLOT_WRITE_BIT(serial) | SLOT_CLOSE_BIT(serial), pdTRUE,
                                     pdFALSE, VFS_WRITE_TIMEOUT / portTICK_PERIOD_MS);
diff --git a/components/bt/host/bluedroid/hci/hci_hal_h4.c b/components/bt/host/bluedroid/hci/hci_hal_h4.c
index da3be907074..f5b16385eb5 100644
--- a/components/bt/host/bluedroid/hci/hci_hal_h4.c
+++ b/components/bt/host/bluedroid/hci/hci_hal_h4.c
@@ -593,7 +593,11 @@ static int host_recv_pkt_cb(uint8_t *data, uint16_t len)
         }
 #endif
         pkt_size = BT_PKT_LINKED_HDR_SIZE + BT_HDR_SIZE + len;
+        #if HEAP_MEMORY_DEBUG
+        linked_pkt = (pkt_linked_item_t *) osi_calloc(pkt_size);
+        #else
         linked_pkt = (pkt_linked_item_t *) osi_calloc_base(pkt_size);
+        #endif
         if (!linked_pkt) {
 #if (BLE_ADV_REPORT_FLOW_CONTROL == TRUE)
             hci_adv_credits_consumed(1);
diff --git a/components/bt/host/bluedroid/hci/hci_packet_parser.c b/components/bt/host/bluedroid/hci/hci_packet_parser.c
index 1ee5033112f..d25caf3506e 100644
--- a/components/bt/host/bluedroid/hci/hci_packet_parser.c
+++ b/components/bt/host/bluedroid/hci/hci_packet_parser.c
@@ -219,7 +219,6 @@ static void parse_ble_read_adv_max_len_response(
         // Size: 2 Octets ; Value: 0x001F – 0x0672 ; Maximum supported advertising data length
         STREAM_TO_UINT16(*adv_max_len_ptr, stream);
     }
-
     osi_free(response);
 }
 #endif // #if (BLE_50_FEATURE_SUPPORT == TRUE)
diff --git a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c
index a85f6a16112..415805fe520 100644
--- a/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c
+++ b/components/bt/host/bluedroid/stack/btm/btm_ble_gap.c
@@ -4617,6 +4617,12 @@ void btm_ble_free (void)
 #endif
 }
 
+static bool enable_topology_check_flag = true;
+void esp_qa_enable_topology_check(bool enable)
+{
+    // This is a workaround: If the topology check is disabled, the 'Supported States' will not be checked.
+    enable_topology_check_flag = enable;
+}
 /*******************************************************************************
 **
 ** Function         btm_ble_topology_check
@@ -4629,6 +4635,7 @@ void btm_ble_free (void)
 *******************************************************************************/
 BOOLEAN btm_ble_topology_check(tBTM_BLE_STATE_MASK request_state_mask)
 {
+    if(!enable_topology_check_flag) return TRUE;
     BOOLEAN rt = FALSE;
 
     UINT8   state_offset = 0;
@@ -4761,6 +4768,17 @@ BOOLEAN BTM_BleSetPrivacyMode(UINT8 addr_type, BD_ADDR bd_addr, UINT8 privacy_mo
     return TRUE;
 }
 
+BOOLEAN BTM_BleSetCsaSupport(UINT8 csa_select, tBTM_SET_CSA_SUPPORT_CMPL_CBACK *p_callback)
+{
+    if (btsnd_hcic_ble_set_csa_support(csa_select) != TRUE) {
+        BTM_TRACE_ERROR("LE SetCsaSupport csa_select=%d: error", csa_select);
+        return FALSE;
+    }
+
+    btm_cb.ble_ctr_cb.set_csa_support_cmpl_cb = p_callback;
+    return TRUE;
+}
+
 bool btm_ble_adv_pkt_ready(void)
 {
     tBTM_BLE_CB *p_cb = &btm_cb.ble_ctr_cb;
diff --git a/components/bt/host/bluedroid/stack/btm/btm_devctl.c b/components/bt/host/bluedroid/stack/btm/btm_devctl.c
index bab88739a08..d3c4ac61da2 100644
--- a/components/bt/host/bluedroid/stack/btm/btm_devctl.c
+++ b/components/bt/host/bluedroid/stack/btm/btm_devctl.c
@@ -773,6 +773,14 @@ void btm_vsc_complete (UINT8 *p, UINT16 opcode, UINT16 evt_len,
             }
             break;
         }
+        case HCI_VENDOR_BLE_SET_CSA_SUPPORT: {
+            uint8_t status;
+            STREAM_TO_UINT8(status, p);
+            if (ble_cb && ble_cb->set_csa_support_cmpl_cb) {
+                ble_cb->set_csa_support_cmpl_cb(status);
+            }
+            break;
+        }
         default:
             break;
     }
diff --git a/components/bt/host/bluedroid/stack/btm/btm_main.c b/components/bt/host/bluedroid/stack/btm/btm_main.c
index e9e443380c8..1519ecb990a 100644
--- a/components/bt/host/bluedroid/stack/btm/btm_main.c
+++ b/components/bt/host/bluedroid/stack/btm/btm_main.c
@@ -110,6 +110,9 @@ void btm_free(void)
     fixed_queue_free(btm_cb.sec_pending_q, osi_free_func);
     btm_acl_free();
     btm_sec_dev_free();
+#if BTM_SCO_INCLUDED == TRUE
+    btm_sco_free();
+#endif
 #if BTM_DYNAMIC_MEMORY
     FREE_AND_RESET(btm_cb_ptr);
 #endif
diff --git a/components/bt/host/bluedroid/stack/btm/btm_sco.c b/components/bt/host/bluedroid/stack/btm/btm_sco.c
index 53a9768a1ae..7dede5d4d3f 100644
--- a/components/bt/host/bluedroid/stack/btm/btm_sco.c
+++ b/components/bt/host/bluedroid/stack/btm/btm_sco.c
@@ -123,6 +123,22 @@ void btm_sco_init (void)
     btm_cb.sco_cb.desired_sco_mode = BTM_DEFAULT_SCO_MODE;
 }
 
+/*******************************************************************************
+**
+** Function         btm_sco_free
+**
+** Description      Free sco specific fixed_queue from btm control block
+**
+*******************************************************************************/
+void btm_sco_free(void)
+{
+#if (BTM_SCO_HCI_INCLUDED == TRUE)
+    for (int i = 0; i < BTM_MAX_SCO_LINKS; i++) {
+        fixed_queue_free(btm_cb.sco_cb.sco_db[i].xmit_data_q, osi_free_func);
+    }
+#endif
+}
+
 /*******************************************************************************
 **
 ** Function         btm_esco_conn_rsp
@@ -233,7 +249,7 @@ void btm_sco_process_num_bufs (UINT16 num_lm_sco_bufs)
 **                               pointer is used, PCM parameter maintained in
 **                               the control block will be used; otherwise update
 **                               control block value.
-**                  err_data_rpt: Lisbon feature to enable the erronous data report
+**                  err_data_rpt: Lisbon feature to enable the erroneous data report
 **                                or not.
 **
 ** Returns          BTM_SUCCESS if the successful.
@@ -947,7 +963,7 @@ void btm_sco_conn_req (BD_ADDR bda,  DEV_CLASS dev_class, UINT8 link_type)
     for (xx = 0; xx < BTM_MAX_SCO_LINKS; xx++, p++) {
         /*
          * If the sco state is in the SCO_ST_CONNECTING state, we still need
-         * to return accept sco to avoid race conditon for sco creation
+         * to return accept sco to avoid race condition for sco creation
          */
         int rem_bd_matches = p->rem_bd_known &&
                              !memcmp (p->esco.data.bd_addr, bda, BD_ADDR_LEN);
diff --git a/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h b/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h
index 0f8888fb1bd..d81a03c0a92 100644
--- a/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h
+++ b/components/bt/host/bluedroid/stack/btm/include/btm_ble_int.h
@@ -377,6 +377,7 @@ typedef struct {
     tBTM_BLE_STATE_MASK cur_states; /* bit mask of tBTM_BLE_STATE */
     UINT8 link_count[2]; /* total link count master and slave*/
     tBTM_UPDATE_DUPLICATE_EXCEPTIONAL_LIST_CMPL_CBACK *update_exceptional_list_cmp_cb;
+    tBTM_SET_CSA_SUPPORT_CMPL_CBACK *set_csa_support_cmpl_cb;
 } tBTM_BLE_CB;
 
 #ifdef __cplusplus
diff --git a/components/bt/host/bluedroid/stack/btm/include/btm_int.h b/components/bt/host/bluedroid/stack/btm/include/btm_int.h
index 64bcc300cd2..df7e435db1a 100644
--- a/components/bt/host/bluedroid/stack/btm/include/btm_int.h
+++ b/components/bt/host/bluedroid/stack/btm/include/btm_int.h
@@ -1119,6 +1119,7 @@ void btm_ble_periodic_adv_sync_trans_complete(UINT16 op_code, UINT8 hci_status,
 ********************************************
 */
 void btm_sco_init (void);
+void btm_sco_free(void);
 void btm_sco_connected (UINT8 hci_status, BD_ADDR bda, UINT16 hci_handle,
                         tBTM_ESCO_DATA *p_esco_data);
 void btm_esco_proc_conn_chg (UINT8 status, UINT16 handle, UINT8 tx_interval,
diff --git a/components/bt/host/bluedroid/stack/gatt/gatt_db.c b/components/bt/host/bluedroid/stack/gatt/gatt_db.c
index efae6413ad2..8844ef5dc8e 100644
--- a/components/bt/host/bluedroid/stack/gatt/gatt_db.c
+++ b/components/bt/host/bluedroid/stack/gatt/gatt_db.c
@@ -60,7 +60,7 @@ static BOOLEAN gatts_add_char_desc_value_check (tGATT_ATTR_VAL *attr_val, tGATTS
 ** Parameter        p_db: database pointer.
 **                  len: size of the memory space.
 **
-** Returns          Status of te operation.
+** Returns          Status of the operation.
 **
 *******************************************************************************/
 BOOLEAN gatts_init_service_db (tGATT_SVC_DB *p_db, tBT_UUID *p_service,  BOOLEAN is_pri,
@@ -94,7 +94,7 @@ BOOLEAN gatts_init_service_db (tGATT_SVC_DB *p_db, tBT_UUID *p_service,  BOOLEAN
 ** Parameter        p_db: database pointer.
 **                  len: size of the memory space.
 **
-** Returns          Status of te operation.
+** Returns          Status of the operation.
 **
 *******************************************************************************/
 tBT_UUID *gatts_get_service_uuid (tGATT_SVC_DB *p_db)
@@ -497,14 +497,14 @@ UINT16 gatts_add_included_service (tGATT_SVC_DB *p_db, UINT16 s_handle, UINT16 e
 ** Function         gatts_add_characteristic
 **
 ** Description      This function add a characteristics and its descriptor into
-**                  a servce identified by the service database pointer.
+**                  a service identified by the service database pointer.
 **
 ** Parameter        p_db: database pointer.
 **                  perm: permission (authentication and key size requirements)
 **                  property: property of the characteristic.
 **                  p_char: characteristic value information.
 **
-** Returns          Status of te operation.
+** Returns          Status of the operation.
 **
 *******************************************************************************/
 UINT16 gatts_add_characteristic (tGATT_SVC_DB *p_db, tGATT_PERM perm,
@@ -1173,40 +1173,40 @@ tGATT_STATUS gatts_write_attr_perm_check (tGATT_SVC_DB *p_db, UINT8 op_code,
 
                 if ((op_code == GATT_SIGN_CMD_WRITE) && !(perm & GATT_WRITE_SIGNED_PERM)) {
                     status = GATT_WRITE_NOT_PERMIT;
-                    GATT_TRACE_DEBUG( "gatts_write_attr_perm_check - sign cmd write not allowed,handle:0x%04x",handle);
+                    GATT_TRACE_DEBUG( "gatts_write_attr_perm_check - sign cmd write not allowed,handle %04x,perm %04x", handle, perm);
                 }
                 if ((op_code == GATT_SIGN_CMD_WRITE) && (sec_flag & GATT_SEC_FLAG_ENCRYPTED)) {
                     status = GATT_INVALID_PDU;
-                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - Error!! sign cmd write sent on a encypted link,handle:0x%04x",handle);
+                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - Error!! sign cmd write sent on a encrypted link,handle %04x,perm %04x", handle, perm);
                 } else if (!(perm & GATT_WRITE_ALLOWED)) {
                     status = GATT_WRITE_NOT_PERMIT;
-                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_WRITE_NOT_PERMIT,handle:0x%04x",handle);
+                    GATT_TRACE_ERROR("gatts_write_attr_perm_check - GATT_WRITE_NOT_PERMIT,handle %04x, perm %04x", handle, perm);
                 }
                 /* require authentication, but not been authenticated */
                 else if ((perm & GATT_WRITE_AUTH_REQUIRED ) && !(sec_flag & GATT_SEC_FLAG_LKEY_UNAUTHED)) {
                     status = GATT_INSUF_AUTHENTICATION;
-                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION,handle:0x%04x",handle);
+                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION,handle %04x, perm %04x", handle, perm);
                 } else if ((perm & GATT_WRITE_MITM_REQUIRED ) && !(sec_flag & GATT_SEC_FLAG_LKEY_AUTHED)) {
                     status = GATT_INSUF_AUTHENTICATION;
-                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION: MITM required,handle:0x%04x",handle);
+                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION: MITM required,handle %04x,perm %04x", handle, perm);
                 } else if ((perm & GATT_WRITE_ENCRYPTED_PERM ) && !(sec_flag & GATT_SEC_FLAG_ENCRYPTED)) {
                     status = GATT_INSUF_ENCRYPTION;
-                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_ENCRYPTION,handle:0x%04x",handle);
+                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_ENCRYPTION,handle:0x%04x, perm:0x%04x", handle, perm);
                 } else if ((perm & GATT_WRITE_ENCRYPTED_PERM ) && (sec_flag & GATT_SEC_FLAG_ENCRYPTED) && (key_size < min_key_size)) {
                     status = GATT_INSUF_KEY_SIZE;
-                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_KEY_SIZE,handle:0x%04x",handle);
+                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_KEY_SIZE,handle %04x,perm %04x", handle, perm);
                 }
                 /* LE Authorization check*/
                 else if ((perm & GATT_WRITE_AUTHORIZATION) && (!(sec_flag & GATT_SEC_FLAG_LKEY_AUTHED) || !(sec_flag & GATT_SEC_FLAG_AUTHORIZATION))){
                     status = GATT_INSUF_AUTHORIZATION;
-                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHORIZATION,handle:0x%04x",handle);
+                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHORIZATION,handle %04x,perm %04x", handle, perm);
                 }
                 /* LE security mode 2 attribute  */
                 else if (perm & GATT_WRITE_SIGNED_PERM && op_code != GATT_SIGN_CMD_WRITE && !(sec_flag & GATT_SEC_FLAG_ENCRYPTED)
                          &&  (perm & GATT_WRITE_ALLOWED) == 0) {
                     status = GATT_INSUF_AUTHENTICATION;
-                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION: LE security mode 2 required,handle:0x%04x",handle);
-                } else { /* writable: must be char value declaration or char descritpors */
+                    GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INSUF_AUTHENTICATION: LE security mode 2 required,handle %04x,perm %04x", handle, perm);
+                } else { /* writable: must be char value declaration or char descriptors */
                     if (p_attr->uuid_type == GATT_ATTR_UUID_TYPE_16) {
                         switch (p_attr->uuid) {
                         case GATT_UUID_CHAR_PRESENT_FORMAT:/* should be readable only */
@@ -1215,13 +1215,19 @@ tGATT_STATUS gatts_write_attr_perm_check (tGATT_SVC_DB *p_db, UINT8 op_code,
                         case GATT_UUID_CHAR_VALID_RANGE:
                             status = GATT_WRITE_NOT_PERMIT;
                             break;
-
+                        case GATT_UUID_GAP_ICON:/* The Appearance characteristic value shall be 2 octets in length */
                         case GATT_UUID_CHAR_CLIENT_CONFIG:
                         /* coverity[MISSING_BREAK] */
                         /* intnended fall through, ignored */
                         /* fall through */
                         case GATT_UUID_CHAR_SRVR_CONFIG:
                             max_size = 2;
+                            status = GATT_SUCCESS;
+                            break;
+                        case GATT_UUID_CLIENT_SUP_FEAT:
+                            max_size = 1;
+                            status = GATT_SUCCESS;
+                            break;
                         case GATT_UUID_CHAR_DESCRIPTION:
                         default: /* any other must be character value declaration */
                             status = GATT_SUCCESS;
@@ -1242,17 +1248,17 @@ tGATT_STATUS gatts_write_attr_perm_check (tGATT_SVC_DB *p_db, UINT8 op_code,
                     else if ( (p_attr->uuid_type == GATT_ATTR_UUID_TYPE_16) &&
                               (p_attr->uuid == GATT_UUID_CHAR_CLIENT_CONFIG ||
                                p_attr->uuid == GATT_UUID_CHAR_SRVR_CONFIG   ||
-                               p_attr->uuid == GATT_UUID_CLIENT_SUP_FEAT    || 
+                               p_attr->uuid == GATT_UUID_CLIENT_SUP_FEAT    ||
                                p_attr->uuid == GATT_UUID_GAP_ICON
                                ) )
 // btla-specific --
                     {
                         if (op_code == GATT_REQ_PREPARE_WRITE) { /* does not allow write blob */
                             status = GATT_REQ_NOT_SUPPORTED;
-                            GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_REQ_NOT_SUPPORTED,handle:0x%04x",handle);
+                            GATT_TRACE_ERROR("gatts_write_attr_perm_check - GATT_REQ_NOT_SUPPORTED,handle %04x,opcode %4x", handle, op_code);
                         } else if (len != max_size) { /* data does not match the required format */
                             status = GATT_INVALID_ATTR_LEN;
-                            GATT_TRACE_ERROR( "gatts_write_attr_perm_check - GATT_INVALID_ATTR_LEN,handle:0x%04x",handle);
+                            GATT_TRACE_ERROR("gatts_write_attr_perm_check - GATT_INVALID_ATTR_LEN,handle %04x,op_code %04x,len %d,max_size %d", handle, op_code, len, max_size);
                         } else {
                             status = GATT_SUCCESS;
                         }
@@ -1554,7 +1560,7 @@ static BOOLEAN gatts_db_add_service_declaration(tGATT_SVC_DB *p_db, tBT_UUID *p_
         uuid.uu.uuid16 = GATT_UUID_SEC_SERVICE;
     }
 
-    /* add service declration record */
+    /* add service declaration record */
     if ((p_attr = (tGATT_ATTR16 *)(allocate_attr_in_db(p_db, &uuid, GATT_PERM_READ))) != NULL) {
         if (copy_extra_byte_in_db (p_db, (void **)&p_attr->p_value, sizeof(tBT_UUID))) {
             if (p_service->len == LEN_UUID_16) {
diff --git a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c
index 52a2b2dc09e..c51746b1aae 100644
--- a/components/bt/host/bluedroid/stack/hcic/hciblecmds.c
+++ b/components/bt/host/bluedroid/stack/hcic/hciblecmds.c
@@ -1910,7 +1910,7 @@ UINT8 btsnd_hcic_ble_set_default_periodic_adv_sync_trans_params(UINT8 mode, UINT
 }
 #endif // #if (BLE_FEAT_PERIODIC_ADV_SYNC_TRANSFER == TRUE)
 
-UINT8 btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 privacy_mode)
+BOOLEAN btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 privacy_mode)
 {
     BT_HDR *p;
     UINT8 *pp;
@@ -1933,4 +1933,26 @@ UINT8 btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 priva
     btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p);
     return (TRUE);
 }
+
+BOOLEAN btsnd_hcic_ble_set_csa_support (UINT8 csa_select)
+{
+    BT_HDR *p;
+    UINT8 *pp;
+
+    if ((p = HCI_GET_CMD_BUF (HCIC_PARAM_SIZE_BLE_SET_CSA_SUPPORT)) == NULL) {
+        return (FALSE);
+    }
+
+    pp = (UINT8 *)(p + 1);
+
+    p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_BLE_SET_CSA_SUPPORT;
+    p->offset = 0;
+
+    UINT16_TO_STREAM (pp, HCI_VENDOR_BLE_SET_CSA_SUPPORT);
+    UINT8_TO_STREAM (pp, HCIC_PARAM_SIZE_BLE_SET_CSA_SUPPORT);
+    UINT8_TO_STREAM (pp, csa_select);
+
+    btu_hcif_send_cmd (LOCAL_BR_EDR_CONTROLLER_ID, p);
+    return TRUE;
+}
 #endif
diff --git a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h
index 21d783dd2b1..3dc7dc8b331 100644
--- a/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h
+++ b/components/bt/host/bluedroid/stack/include/stack/btm_ble_api.h
@@ -1007,6 +1007,7 @@ typedef void (tBTM_START_STOP_ADV_CMPL_CBACK) (UINT8 status);
 typedef void (tBTM_UPDATE_DUPLICATE_EXCEPTIONAL_LIST_CMPL_CBACK) (tBTM_STATUS status, uint8_t subcode, uint32_t length, uint8_t *device_info);
 typedef void (tBTM_CLEAR_ADV_CMPL_CBACK) (UINT8 status);
 typedef void (tBTM_SET_PRIVACY_MODE_CMPL_CBACK) (tBTM_STATUS status);
+typedef void (tBTM_SET_CSA_SUPPORT_CMPL_CBACK) (tBTM_STATUS status);
 
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
 #define    BTM_BLE_5_GAP_READ_PHY_COMPLETE_EVT                     1
@@ -2724,6 +2725,20 @@ BOOLEAN BTM_BleSetPrivacyMode(UINT8 addr_type,
                               UINT8 privacy_mode,
                               tBTM_SET_PRIVACY_MODE_CMPL_CBACK *p_callback);
 
+/*******************************************************************************
+**
+** Function         BTM_BleSetCsaSupport
+**
+** Description      This function is called to set the ChSel field of Advertising or Initiating PDUs
+**
+** Parameters       csa_select - Select LE Channel Selection Algorithm.
+**                  p_callback - Callback function to be called when the operation is completed.
+**
+** Returns          TRUE if the operation was successful, otherwise FALSE.
+**
+*******************************************************************************/
+BOOLEAN BTM_BleSetCsaSupport (UINT8 csa_select, tBTM_SET_CSA_SUPPORT_CMPL_CBACK *p_callback);
+
 /*
 #ifdef __cplusplus
 }
diff --git a/components/bt/host/bluedroid/stack/include/stack/hcidefs.h b/components/bt/host/bluedroid/stack/include/stack/hcidefs.h
index b77e8854767..0943c624f92 100644
--- a/components/bt/host/bluedroid/stack/include/stack/hcidefs.h
+++ b/components/bt/host/bluedroid/stack/include/stack/hcidefs.h
@@ -422,6 +422,7 @@
 #define HCI_SUBCODE_BLE_ADV_REPORT_FLOW_CONTROL    0x0A
 #define HCI_SUBCODE_BLE_RD_STATIC_ADDR             0x0B
 #define HCI_SUBCODE_BLE_CLEAR_ADV                  0x0C
+#define HCI_SUBCODE_BLE_SET_CSA_SUPPORT            0x12
 #define HCI_SUBCODE_BLE_MAX                        0x7F
 
 //ESP BT subcode define
@@ -468,6 +469,8 @@
 #define HCI_VENDOR_BLE_ADV_REPORT_FLOW_CONTROL     HCI_ESP_VENDOR_OPCODE_BUILD(HCI_VENDOR_OGF, HCI_ESP_GROUP_BLE, HCI_SUBCODE_BLE_ADV_REPORT_FLOW_CONTROL)
 /* BLE clear legacy advertising */
 #define HCI_VENDOR_BLE_CLEAR_ADV          HCI_ESP_VENDOR_OPCODE_BUILD(HCI_VENDOR_OGF, HCI_ESP_GROUP_BLE, HCI_SUBCODE_BLE_CLEAR_ADV)
+/* BLE set CSA support */
+#define HCI_VENDOR_BLE_SET_CSA_SUPPORT    HCI_ESP_VENDOR_OPCODE_BUILD(HCI_VENDOR_OGF, HCI_ESP_GROUP_BLE, HCI_SUBCODE_BLE_SET_CSA_SUPPORT)
 //ESP BT HCI CMD
 #define HCI_VENDOR_BT_SET_MIN_ENC_KEY_SIZE         HCI_ESP_VENDOR_OPCODE_BUILD(HCI_VENDOR_OGF, HCI_ESP_GROUP_BT, HCI_SUBCODE_BT_SET_MIN_ENC_KEY_SIZE)
 
diff --git a/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h b/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h
index 951e5b703a7..252efa72191 100644
--- a/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h
+++ b/components/bt/host/bluedroid/stack/include/stack/hcimsgs.h
@@ -759,6 +759,7 @@ void btsnd_hcic_vendor_spec_cmd (BT_HDR *buffer, UINT16 opcode,
 #define HCIC_PARAM_SIZE_BLE_UPDATE_ADV_FLOW_CONTROL     2
 #define HCIC_PARAM_SIZE_BLE_CLEAR_ADV                   0
 #define HCIC_PARAM_SIZE_SET_PRIVACY_MODE                8
+#define HCIC_PARAM_SIZE_BLE_SET_CSA_SUPPORT             1
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
 #define HCIC_PARAM_SIZE_BLE_READ_PHY                   2
 #define HCIC_PARAM_SIZE_BLE_SET_DEF_PHY                3
@@ -914,7 +915,12 @@ BOOLEAN btsnd_hcic_ble_set_rand_priv_addr_timeout (UINT16 rpa_timout);
 
 BOOLEAN btsnd_hcic_ble_clear_adv(void);
 
+BOOLEAN btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 privacy_mode);
+
+BOOLEAN btsnd_hcic_ble_set_csa_support (UINT8 csa_select);
+
 #endif /* BLE_INCLUDED */
+
 #if (BLE_50_FEATURE_SUPPORT == TRUE)
 typedef struct {
     UINT8 scan_type;
@@ -1042,8 +1048,6 @@ UINT8 btsnd_hcic_ble_write_rf_path_compensation(UINT16 rf_tx_path, UINT16 rf_rx_
 
 #endif // #if (BLE_50_FEATURE_SUPPORT == TRUE)
 
-UINT8 btsnd_hcic_ble_set_privacy_mode(UINT8 addr_type, BD_ADDR addr, UINT8 privacy_mode);
-
 #define HCIC_PARAM_SIZE_WRITE_AUTHENT_PAYLOAD_TOUT  4
 
 #define HCI__WRITE_AUTHENT_PAYLOAD_TOUT_HANDLE_OFF  0
diff --git a/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c b/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c
index 01edf9caf53..36f91cfe087 100644
--- a/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c
+++ b/components/bt/host/bluedroid/stack/l2cap/l2c_ble.c
@@ -376,6 +376,7 @@ void l2cble_scanner_conn_comp (UINT16 handle, BD_ADDR bda, tBLE_ADDR_TYPE type,
     p_lcb->waiting_update_conn_latency = p_lcb->current_used_conn_latency = conn_latency;
     p_lcb->conn_update_mask = L2C_BLE_NOT_DEFAULT_PARAM;
     p_lcb->updating_param_flag = false;
+    p_lcb->ble_addr_type = type;
 
     /* If there are any preferred connection parameters, set them now */
     if ( (p_dev_rec->conn_params.min_conn_int     >= BTM_BLE_CONN_INT_MIN ) &&
@@ -476,6 +477,7 @@ void l2cble_advertiser_conn_comp (UINT16 handle, BD_ADDR bda, tBLE_ADDR_TYPE typ
     p_lcb->waiting_update_conn_latency      =  p_lcb->current_used_conn_latency = conn_latency;
     p_lcb->conn_update_mask = L2C_BLE_NOT_DEFAULT_PARAM;
     p_lcb->updating_param_flag = false;
+    p_lcb->ble_addr_type = type;
 
     /* Tell BTM Acl management about the link */
     p_dev_rec = btm_find_or_alloc_dev (bda);
diff --git a/components/bt/host/bluedroid/stack/smp/smp_utils.c b/components/bt/host/bluedroid/stack/smp/smp_utils.c
index 2e9fac77c9a..48ba6c0ae30 100644
--- a/components/bt/host/bluedroid/stack/smp/smp_utils.c
+++ b/components/bt/host/bluedroid/stack/smp/smp_utils.c
@@ -331,8 +331,7 @@ BOOLEAN  smp_send_msg_to_L2CAP(BD_ADDR rem_bda, BT_HDR *p_toL2CAP)
 
     if ((l2cap_ret = L2CA_SendFixedChnlData (fixed_cid, rem_bda, p_toL2CAP)) == L2CAP_DW_FAILED) {
         smp_cb.total_tx_unacked -= 1;
-        SMP_TRACE_ERROR("SMP   failed to pass msg:0x%0x to L2CAP",
-                        *((UINT8 *)(p_toL2CAP + 1) + p_toL2CAP->offset));
+        SMP_TRACE_ERROR("SMP failed to pass msg to L2CAP");
         return FALSE;
     } else {
         return TRUE;
@@ -1125,7 +1124,7 @@ BOOLEAN smp_pairing_request_response_parameters_are_valid(tSMP_CB *p_cb)
     SMP_TRACE_DEBUG("%s for cmd code 0x%02x\n", __func__, p_cb->rcvd_cmd_code);
 
     if (io_caps >= BTM_IO_CAP_MAX) {
-        SMP_TRACE_WARNING("Rcvd from the peer cmd 0x%02x with IO Capabilty \
+        SMP_TRACE_WARNING("Rcvd from the peer cmd 0x%02x with IO Capability \
             value (0x%02x) out of range).\n",
                           p_cb->rcvd_cmd_code, io_caps);
         return FALSE;
diff --git a/components/bt/host/nimble/Kconfig.in b/components/bt/host/nimble/Kconfig.in
index cfde045be4d..6984cc02923 100644
--- a/components/bt/host/nimble/Kconfig.in
+++ b/components/bt/host/nimble/Kconfig.in
@@ -648,7 +648,7 @@ config BT_NIMBLE_PERIODIC_ADV_ENH
 
 config BT_NIMBLE_AOA_AOD
     bool "Direction Finding"
-    depends on BT_NIMBLE_50_FEATURE_SUPPORT && SOC_BLE_CTE_SUPPORTED
+    depends on BT_NIMBLE_50_FEATURE_SUPPORT && (BT_CONTROLLER_DISABLED || SOC_BLE_CTE_SUPPORTED)
     default n
     help
         Enable support for Connectionless and Connection Oriented Direction Finding
diff --git a/components/bt/host/nimble/nimble b/components/bt/host/nimble/nimble
index 03462b6686c..32b2124f542 160000
--- a/components/bt/host/nimble/nimble
+++ b/components/bt/host/nimble/nimble
@@ -1 +1 @@
-Subproject commit 03462b6686cf49bb0bb026461300fec593c6f4c5
+Subproject commit 32b2124f54238e70ecd4c72a753698babdd939f7
diff --git a/components/bt/include/esp32/include/esp_bt.h b/components/bt/include/esp32/include/esp_bt.h
index 722da480de0..4aa60073d3e 100644
--- a/components/bt/include/esp32/include/esp_bt.h
+++ b/components/bt/include/esp32/include/esp_bt.h
@@ -55,7 +55,7 @@ extern "C" {
 *
 * @note Please do not modify this value
 */
-#define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL  0x20240722
+#define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL  0x20241015
 
 /**
  * @brief Bluetooth Controller mode
@@ -178,6 +178,27 @@ the advertising packet will be discarded until the memory is restored. */
 #else
 #define BTDM_CTRL_SCAN_BACKOFF_UPPERLIMITMAX  0
 #endif
+
+#ifdef CONFIG_BTDM_BLE_LLCP_CONN_UPDATE
+#define BTDM_BLE_LLCP_CONN_UPDATE (1<<0)
+#else
+#define BTDM_BLE_LLCP_CONN_UPDATE (0<<0)
+#endif
+
+#ifdef CONFIG_BTDM_BLE_LLCP_CHAN_MAP_UPDATE
+#define BTDM_BLE_LLCP_CHAN_MAP_UPDATE (1<<1)
+#else
+#define BTDM_BLE_LLCP_CHAN_MAP_UPDATE (0<<1)
+#endif
+
+#define BTDM_BLE_LLCP_DISC_FLAG (BTDM_BLE_LLCP_CONN_UPDATE | BTDM_BLE_LLCP_CHAN_MAP_UPDATE)
+
+#ifdef CONFIG_BTDM_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS
+#define BTDM_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED CONFIG_BTDM_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS
+#else
+#define BTDM_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED 0
+#endif
+
 /**
 * @brief  Default Bluetooth Controller configuration
 */
@@ -206,6 +227,8 @@ the advertising packet will be discarded until the memory is restored. */
     .hli = BTDM_CTRL_HLI,                                                  \
     .dup_list_refresh_period = SCAN_DUPL_CACHE_REFRESH_PERIOD,             \
     .ble_scan_backoff = BTDM_CTRL_SCAN_BACKOFF_UPPERLIMITMAX,              \
+    .ble_llcp_disc_flag = BTDM_BLE_LLCP_DISC_FLAG,                         \
+    .ble_aa_check = BTDM_CTRL_CHECK_CONNECT_IND_ACCESS_ADDRESS_ENABLED,    \
     .magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL,                           \
 }
 
@@ -258,6 +281,8 @@ typedef struct {
     bool hli;                               /*!< True if using high level interrupt; false otherwise. Configurable in menuconfig */
     uint16_t dup_list_refresh_period;       /*!< Scan duplicate filtering list refresh period in seconds. Configurable in menuconfig */
     bool ble_scan_backoff;                  /*!< True if BLE scan backoff is enabled; false otherwise. Configurable in menuconfig */
+    uint8_t ble_llcp_disc_flag;             /*!< BLE disconnect flag when instant passed. Configurable in menuconfig */
+    bool ble_aa_check;                      /*!< True if adds a verification step for the Access Address within the CONNECT_IND PDU; false otherwise. Configurable in menuconfig */
     uint32_t magic;                         /*!< Magic number */
 } esp_bt_controller_config_t;
 
diff --git a/components/bt/include/esp32c3/include/esp_bt.h b/components/bt/include/esp32c3/include/esp_bt.h
index d8ff356f9d9..1cd79be9021 100644
--- a/components/bt/include/esp32c3/include/esp_bt.h
+++ b/components/bt/include/esp32c3/include/esp_bt.h
@@ -19,7 +19,7 @@ extern "C" {
 #endif
 
 #define ESP_BT_CTRL_CONFIG_MAGIC_VAL    0x5A5AA5A5
-#define ESP_BT_CTRL_CONFIG_VERSION      0x02404010
+#define ESP_BT_CTRL_CONFIG_VERSION      0x02410230
 
 #define ESP_BT_HCI_TL_MAGIC_VALUE   0xfadebead
 #define ESP_BT_HCI_TL_VERSION       0x00010000
@@ -217,6 +217,80 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
 #define BLE_HW_TARGET_CODE_CHIP_ECO0                      (0x02010000)
 #endif
 
+#ifdef CONFIG_BT_CTRL_BLE_LLCP_CONN_UPDATE
+#define BT_CTRL_BLE_LLCP_CONN_UPDATE (1<<0)
+#else
+#define BT_CTRL_BLE_LLCP_CONN_UPDATE (0<<0)
+#endif
+
+#ifdef CONFIG_BT_CTRL_BLE_LLCP_CHAN_MAP_UPDATE
+#define BT_CTRL_BLE_LLCP_CHAN_MAP_UPDATE (1<<1)
+#else
+#define BT_CTRL_BLE_LLCP_CHAN_MAP_UPDATE (0<<1)
+#endif
+
+#ifdef CONFIG_BT_CTRL_BLE_LLCP_PHY_UPDATE
+#define BT_CTRL_BLE_LLCP_PHY_UPDATE (1<<2)
+#else
+#define BT_CTRL_BLE_LLCP_PHY_UPDATE (0<<2)
+#endif
+
+#define BT_CTRL_BLE_LLCP_DISC_FLAG (BT_CTRL_BLE_LLCP_CONN_UPDATE | BT_CTRL_BLE_LLCP_CHAN_MAP_UPDATE | BT_CTRL_BLE_LLCP_PHY_UPDATE)
+#if defined(CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+#define BT_CTRL_RUN_IN_FLASH_ONLY  CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY
+#else
+#define BT_CTRL_RUN_IN_FLASH_ONLY  (0)
+#endif
+
+#if (BT_CTRL_RUN_IN_FLASH_ONLY == 1)
+
+#if defined(CONFIG_BT_CTRL_DTM_ENABLE)
+#define BT_CTRL_DTM_ENABLE  CONFIG_BT_CTRL_DTM_ENABLE
+#else
+#define BT_CTRL_DTM_ENABLE  (0)
+#endif
+
+#if defined(CONFIG_BT_CTRL_BLE_MASTER)
+#define BT_CTRL_BLE_MASTER  CONFIG_BT_CTRL_BLE_MASTER
+#else
+#define BT_CTRL_BLE_MASTER  (0)
+#endif
+
+#if defined(CONFIG_BT_CTRL_BLE_TEST)
+#define BT_CTRL_BLE_TEST  CONFIG_BT_CTRL_BLE_TEST
+#else
+#define BT_CTRL_BLE_TEST  (0)
+#endif
+
+#if defined (CONFIG_BT_NIMBLE_SECURITY_ENABLE) || defined (CONFIG_BT_BLE_SMP_ENABLE)
+#ifdef CONFIG_BT_NIMBLE_SECURITY_ENABLE
+#define BLE_SECURITY_ENABLE  (CONFIG_BT_NIMBLE_SECURITY_ENABLE)
+#endif //CONFIG_BT_NIMBLE_SECURITY_ENABLE
+#ifdef CONFIG_BT_BLE_SMP_ENABLE
+#define BLE_SECURITY_ENABLE  (CONFIG_BT_BLE_SMP_ENABLE)
+#endif //CONFIG_BT_BLE_SMP_ENABLE
+#else
+#if defined (CONFIG_BT_CTRL_BLE_SECURITY_ENABLE)
+#define BLE_SECURITY_ENABLE  (CONFIG_BT_CTRL_BLE_SECURITY_ENABLE)
+#else
+#define BLE_SECURITY_ENABLE  (0)
+#endif
+#endif // (CONFIG_BT_NIMBLE_SECURITY_ENABLE) || (CONFIG_BT_BLE_SMP_ENABLE)
+
+#if defined (CONFIG_BT_CTRL_BLE_SCAN)
+#define BT_CTRL_BLE_SCAN    CONFIG_BT_CTRL_BLE_SCAN
+#else
+#define BT_CTRL_BLE_SCAN    (0)
+#endif
+
+#else
+#define BT_CTRL_BLE_MASTER   (1)
+#define BT_CTRL_DTM_ENABLE   (1)
+#define BT_CTRL_BLE_TEST     (1)
+#define BLE_SECURITY_ENABLE  (1)
+#define BT_CTRL_BLE_SCAN     (1)
+#endif // (BT_CTRL_RUN_IN_FLASH_ONLY == 1)
+
 #define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {                              \
     .magic = ESP_BT_CTRL_CONFIG_MAGIC_VAL,                                 \
     .version = ESP_BT_CTRL_CONFIG_VERSION,                                 \
@@ -255,6 +329,13 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
     .ble_data_lenth_zero_aux = BT_BLE_ADV_DATA_LENGTH_ZERO_AUX,            \
     .ble_chan_ass_en = BT_CTRL_CHAN_ASS_EN,                                \
     .ble_ping_en = BT_CTRL_LE_PING_EN,                                     \
+    .ble_llcp_disc_flag = BT_CTRL_BLE_LLCP_DISC_FLAG,                      \
+    .run_in_flash = BT_CTRL_RUN_IN_FLASH_ONLY,                             \
+    .dtm_en = BT_CTRL_DTM_ENABLE,                                          \
+    .enc_en = BLE_SECURITY_ENABLE,                                         \
+    .qa_test = BT_CTRL_BLE_TEST,                                           \
+    .master_en = BT_CTRL_BLE_MASTER,                                       \
+    .scan_en = BT_CTRL_BLE_SCAN,                                           \
 }
 
 #else
@@ -329,6 +410,13 @@ typedef struct {
     uint8_t ble_data_lenth_zero_aux;        /*!< Config ext adv aux option */
     uint8_t ble_chan_ass_en;                /*!< BLE channel assessment enable */
     uint8_t ble_ping_en;                    /*!< BLE ping procedure enable */
+    uint8_t ble_llcp_disc_flag;             /*!< BLE disconnect flag when instant passed */
+    bool run_in_flash;                      /*!< Check if controller code is in flash */
+    bool dtm_en;                            /*!< Controller DTM feature is enabled or not */
+    bool enc_en;                            /*!< Controller encryption feature is enabled or not */
+    bool qa_test;                           /*!< Controller QA test feature is enabled or not */
+    bool master_en;                         /*!< Controller master feature is enabled or not */
+    bool scan_en;                           /*!< Controller scan feature is enabled or not */
 } esp_bt_controller_config_t;
 
 /**
diff --git a/components/console/esp_console_common.c b/components/console/esp_console_common.c
index 416976dccbb..395aa272f7f 100644
--- a/components/console/esp_console_common.c
+++ b/components/console/esp_console_common.c
@@ -154,7 +154,7 @@ void esp_console_repl_task(void *args)
         printf("\r\n"
                "Your terminal application does not support escape sequences.\n\n"
                "Line editing and history features are disabled.\n\n"
-               "On Windows, try using Putty instead.\r\n");
+               "On Windows, try using Windows Terminal or Putty instead.\r\n");
     }
 
     linenoiseSetMaxLineLen(repl_com->max_cmdline_length);
diff --git a/components/cxx/cxx_guards.cpp b/components/cxx/cxx_guards.cpp
index 0a76173769e..e4f9f905a66 100644
--- a/components/cxx/cxx_guards.cpp
+++ b/components/cxx/cxx_guards.cpp
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -210,6 +210,12 @@ extern "C" void __cxa_guard_abort(__guard* pg) throw()
     }
 }
 
+/* Originally, this should come with crtbegin.o from the toolchain (if GCC is configured with --enable-__cxa_atexit).
+   Since we do not link with crtbegin.o and have not configured GCC with --enable-__cxa_atexit, it is declared here.
+   Note: It should have a unique value in every shared object; in the main program its value is zero. */
+extern "C" void *__dso_handle __attribute__((__visibility__("hidden")));
+void *__dso_handle = 0;
+
 /**
  * Dummy function used to force linking this file instead of the same one in libstdc++.
  * This works via -u __cxa_guard_dummy flag in component.mk
diff --git a/components/cxx/test_apps/general/main/test_cxx_general.cpp b/components/cxx/test_apps/general/main/test_cxx_general.cpp
index 0e483ab655a..858b16bc16a 100644
--- a/components/cxx/test_apps/general/main/test_cxx_general.cpp
+++ b/components/cxx/test_apps/general/main/test_cxx_general.cpp
@@ -197,7 +197,7 @@ struct PriorityInitTest {
 
 int PriorityInitTest::order = 0;
 
-// init_priority objects are initialized from the lowest to the heighest priority number
+// init_priority objects are initialized from the lowest to the highest priority number
 // Default init_priority is always the lowest (highest priority number)
 PriorityInitTest g_static_init_priority_test2;
 PriorityInitTest g_static_init_priority_test1 __attribute__((init_priority(1000)));
@@ -243,6 +243,36 @@ TEST_CASE("can use std::vector", "[misc]")
     TEST_ASSERT_EQUAL(51, std::accumulate(std::begin(v), std::end(v), 0));
 }
 
+static volatile bool is_tls_class_destructor_called;
+struct TestTLS {
+    TestTLS() { }
+    ~TestTLS()
+    {
+        is_tls_class_destructor_called = true;
+    }
+    void foo() { }
+};
+
+thread_local TestTLS s_testTLS;
+
+void test_thread_local_destructors(void * arg)
+{
+    s_testTLS.foo();
+    xSemaphoreGive(s_slow_init_sem);
+    vTaskDelete(NULL);
+}
+
+TEST_CASE("call destructors for thread_local classes CXX", "[misc]")
+{
+    is_tls_class_destructor_called = false;
+    s_slow_init_sem = xSemaphoreCreateCounting(1, 0);
+    xTaskCreate(test_thread_local_destructors, "test_thread_local_destructors", 2048, NULL, 10, NULL);
+    vTaskDelay(1); /* Triggers IDLE task to call prvCheckTasksWaitingTermination() which cleans task-specific data */
+    TEST_ASSERT_TRUE(xSemaphoreTake(s_slow_init_sem, 500 / portTICK_PERIOD_MS));
+    vSemaphoreDelete(s_slow_init_sem);
+    TEST_ASSERT_TRUE(is_tls_class_destructor_called);
+}
+
 /* These test cases pull a lot of code from libstdc++ and are disabled for now
  */
 #if 0
@@ -291,6 +321,7 @@ TEST_CASE("stack smashing protection CXX", "[stack_smash]")
 
 extern "C" void app_main(void)
 {
+    s_testTLS.foo(); /* allocates memory that will be reused */
     printf("CXX GENERAL TEST\n");
     unity_run_menu();
 }
diff --git a/components/driver/Kconfig b/components/driver/Kconfig
index 68634c78f92..2698ac746aa 100644
--- a/components/driver/Kconfig
+++ b/components/driver/Kconfig
@@ -152,4 +152,15 @@ menu "Driver Configurations"
                 and don't want to see related deprecation warnings, you can enable this option.
     endmenu # Legacy Temperature Sensor Driver Configurationss
 
+    menu "Legacy Touch Sensor Driver Configurations"
+        depends on SOC_TOUCH_SENSOR_SUPPORTED
+        config TOUCH_SUPPRESS_DEPRECATE_WARN
+            bool "Suppress legacy driver deprecated warning"
+            default n
+            help
+                whether to suppress the deprecation warnings when using legacy touch sensor driver
+                (driver/touch_sensor.h). If you want to continue using the legacy driver,
+                and don't want to see related deprecation warnings, you can enable this option.
+    endmenu # Legacy Touch Sensor Driver Configurationss
+
 endmenu  # Driver configurations
diff --git a/components/driver/deprecated/adc_dma_legacy.c b/components/driver/deprecated/adc_dma_legacy.c
index 7845b4bcc59..a85a043714d 100644
--- a/components/driver/deprecated/adc_dma_legacy.c
+++ b/components/driver/deprecated/adc_dma_legacy.c
@@ -27,6 +27,7 @@
 #include "hal/adc_hal.h"
 #include "hal/dma_types.h"
 #include "hal/adc_hal_common.h"
+#include "esp_private/regi2c_ctrl.h"
 
 #include "driver/gpio.h"
 #include "driver/adc_types_legacy.h"
@@ -212,6 +213,8 @@ esp_err_t adc_digi_deinitialize(void)
     }
 #endif  //CONFIG_PM_ENABLE
 
+    ANALOG_CLOCK_DISABLE();
+
     free(s_adc_digi_ctx->rx_dma_buf);
     free(s_adc_digi_ctx->hal.rx_desc);
     free(s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern);
@@ -355,6 +358,8 @@ esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
 
     adc_apb_periph_claim();
 
+    ANALOG_CLOCK_ENABLE();
+
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_hal_calibration_init(ADC_UNIT_1);
     adc_hal_calibration_init(ADC_UNIT_2);
diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c
index 239bb5ac40f..afca5a6d91e 100644
--- a/components/driver/deprecated/adc_legacy.c
+++ b/components/driver/deprecated/adc_legacy.c
@@ -28,6 +28,7 @@
 #include "hal/adc_ll.h"
 #include "hal/adc_hal_common.h"
 #include "esp_private/esp_clk_tree_common.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_private/periph_ctrl.h"
 #include "driver/adc_types_legacy.h"
 #include "esp_clk_tree.h"
@@ -292,10 +293,6 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
     adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten);
     SARADC1_EXIT();
 
-#if SOC_ADC_CALIBRATION_V1_SUPPORTED
-    adc_hal_calibration_init(ADC_UNIT_1);
-#endif
-
     return ESP_OK;
 }
 
@@ -385,11 +382,16 @@ int adc1_get_raw(adc1_channel_t channel)
     ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_UNIT_1), ESP_ERR_INVALID_ARG, ADC_TAG, "invalid channel");
     adc1_rtc_mode_acquire();
 
+    ANALOG_CLOCK_ENABLE();
+
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
+    adc_hal_calibration_init(ADC_UNIT_1);
     adc_atten_t atten = adc_ll_get_atten(ADC_UNIT_1, channel);
     adc_set_hw_calibration_code(ADC_UNIT_1, atten);
 #endif  //SOC_ADC_CALIBRATION_V1_SUPPORTED
 
+    ANALOG_CLOCK_DISABLE();
+
     SARADC1_ENTER();
 #ifdef CONFIG_IDF_TARGET_ESP32
     adc_ll_hall_disable(); //Disable other peripherals.
@@ -760,10 +762,6 @@ esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
     s_atten1_single[channel] = atten;
     ret = adc_digi_gpio_init(ADC_UNIT_1, BIT(channel));
 
-#if SOC_ADC_CALIBRATION_V1_SUPPORTED
-    adc_hal_calibration_init(ADC_UNIT_1);
-#endif
-
     return ret;
 }
 
@@ -781,10 +779,16 @@ int adc1_get_raw(adc1_channel_t channel)
     adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT);
 
     adc_atten_t atten = s_atten1_single[channel];
+
+    ANALOG_CLOCK_ENABLE();
+
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
+    adc_hal_calibration_init(ADC_UNIT_1);
     adc_set_hw_calibration_code(ADC_UNIT_1, atten);
 #endif
 
+    ANALOG_CLOCK_DISABLE();
+
     ADC_REG_LOCK_ENTER();
     adc_oneshot_ll_set_atten(ADC_UNIT_1, channel, atten);
     adc_hal_convert(ADC_UNIT_1, channel, clk_src_freq_hz, &raw_out);
@@ -838,8 +842,10 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
     esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, true);
     adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT);
 
+#if SOC_ADC_ARBITER_SUPPORTED
     adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
     adc_hal_arbiter_config(&config);
+#endif
 
     adc_atten_t atten = s_atten2_single[channel];
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
@@ -938,6 +944,7 @@ static void check_adc_oneshot_driver_conflict(void)
 ---------------------------------------------------------------*/
 static __attribute__((constructor)) void adc_hw_calibration(void)
 {
+    ANALOG_CLOCK_ENABLE();
     //Calculate all ICode
     for (int i = 0; i < SOC_ADC_PERIPH_NUM; i++) {
         adc_hal_calibration_init(i);
@@ -955,5 +962,6 @@ static __attribute__((constructor)) void adc_hw_calibration(void)
 #endif
         }
     }
+    ANALOG_CLOCK_DISABLE();
 }
 #endif  //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
diff --git a/components/driver/deprecated/driver/adc_types_legacy.h b/components/driver/deprecated/driver/adc_types_legacy.h
index 9186b9c2457..9888f03cba8 100644
--- a/components/driver/deprecated/driver/adc_types_legacy.h
+++ b/components/driver/deprecated/driver/adc_types_legacy.h
@@ -70,7 +70,7 @@ typedef enum {
     ADC1_CHANNEL_4,     /*!< ADC1 channel 4 is GPIO4 */
     ADC1_CHANNEL_MAX,
 } adc1_channel_t;
-#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
 typedef enum {
     ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
     ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO1 */
@@ -93,6 +93,14 @@ typedef enum {
     ADC1_CHANNEL_7,     /*!< ADC1 channel 7 is GPIO23 */
     ADC1_CHANNEL_MAX,
 } adc1_channel_t;
+#elif CONFIG_IDF_TARGET_ESP32C61
+typedef enum {
+    ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO1 */
+    ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO3 */
+    ADC1_CHANNEL_2,     /*!< ADC1 channel 2 is GPIO4 */
+    ADC1_CHANNEL_3,     /*!< ADC1 channel 3 is GPIO5 */
+    ADC1_CHANNEL_MAX,
+} adc1_channel_t;
 #endif // CONFIG_IDF_TARGET_*
 
 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
diff --git a/components/driver/deprecated/i2s_legacy.c b/components/driver/deprecated/i2s_legacy.c
index 36996697b28..5f4a033fcfc 100644
--- a/components/driver/deprecated/i2s_legacy.c
+++ b/components/driver/deprecated/i2s_legacy.c
@@ -1479,11 +1479,6 @@ static esp_err_t i2s_init_legacy(i2s_port_t i2s_num, int intr_alloc_flag)
     /* Create power management lock */
 #ifdef CONFIG_PM_ENABLE
     esp_pm_lock_type_t pm_lock = ESP_PM_APB_FREQ_MAX;
-#if SOC_I2S_SUPPORTS_APLL
-    if (p_i2s[i2s_num]->use_apll) {
-        pm_lock = ESP_PM_NO_LIGHT_SLEEP;
-    }
-#endif // SOC_I2S_SUPPORTS_APLL
     ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_lock, 0, "i2s_driver", &p_i2s[i2s_num]->pm_lock), TAG, "I2S pm lock error");
 #endif //CONFIG_PM_ENABLE
 
diff --git a/components/driver/deprecated/rtc_temperature_legacy.c b/components/driver/deprecated/rtc_temperature_legacy.c
index d0da188faab..7433867a019 100644
--- a/components/driver/deprecated/rtc_temperature_legacy.c
+++ b/components/driver/deprecated/rtc_temperature_legacy.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,7 +15,6 @@
 #include "freertos/FreeRTOS.h"
 #include "esp_private/regi2c_ctrl.h"
 #include "soc/regi2c_saradc.h"
-#include "esp_log.h"
 #include "esp_efuse_rtc_calib.h"
 #include "hal/temperature_sensor_ll.h"
 #include "driver/temp_sensor_types_legacy.h"
@@ -111,6 +110,10 @@ esp_err_t temp_sensor_stop(void)
 esp_err_t temp_sensor_read_raw(uint32_t *tsens_out)
 {
     ESP_RETURN_ON_FALSE(tsens_out != NULL, ESP_ERR_INVALID_ARG, TAG, "no tsens_out specified");
+    if (tsens_hw_state != TSENS_HW_STATE_STARTED) {
+        ESP_LOGE(TAG, "Has not been started");
+        return ESP_ERR_INVALID_STATE;
+    }
     ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-use-of-uninitialized-value") // False-positive detection. TODO GCC-366
     *tsens_out = temperature_sensor_ll_get_raw_value();
     ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-use-of-uninitialized-value")
diff --git a/components/driver/i2c/i2c.c b/components/driver/i2c/i2c.c
index 12f2a25d7b7..1450f9af1e8 100644
--- a/components/driver/i2c/i2c.c
+++ b/components/driver/i2c/i2c.c
@@ -280,7 +280,7 @@ static void i2c_hw_enable(i2c_port_t i2c_num)
 static esp_err_t i2c_sleep_retention_init(void *arg)
 {
     i2c_port_t i2c_num = *(i2c_port_t *)arg;
-    esp_err_t ret = sleep_retention_entries_create(i2c_regs_retention[i2c_num].link_list, i2c_regs_retention[i2c_num].link_num, REGDMA_LINK_PRI_I2C, I2C_SLEEP_RETENTION_MODULE(i2c_num));
+    esp_err_t ret = sleep_retention_entries_create(i2c_regs_retention[i2c_num].link_list, i2c_regs_retention[i2c_num].link_num, REGDMA_LINK_PRI_I2C, i2c_regs_retention[i2c_num].module_id);
     ESP_RETURN_ON_ERROR(ret, I2C_TAG, "failed to allocate mem for sleep retention");
     return ret;
 }
@@ -428,9 +428,9 @@ esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_
     sleep_retention_module_init_param_t init_param = {
         .cbs = { .create = { .handle = i2c_sleep_retention_init, .arg = &i2c_num } }
     };
-    ret = sleep_retention_module_init(I2C_SLEEP_RETENTION_MODULE(i2c_num), &init_param);
+    ret = sleep_retention_module_init(i2c_regs_retention[i2c_num].module_id, &init_param);
     if (ret == ESP_OK) {
-        sleep_retention_module_allocate(I2C_SLEEP_RETENTION_MODULE(i2c_num));
+        sleep_retention_module_allocate(i2c_regs_retention[i2c_num].module_id);
     }
 #endif
     return ESP_OK;
@@ -486,9 +486,9 @@ esp_err_t i2c_driver_delete(i2c_port_t i2c_num)
     p_i2c->intr_handle = NULL;
 
 #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
-    esp_err_t err = sleep_retention_module_free(I2C_SLEEP_RETENTION_MODULE(i2c_num));
+    esp_err_t err = sleep_retention_module_free(i2c_regs_retention[i2c_num].module_id);
     if (err == ESP_OK) {
-        err = sleep_retention_module_deinit(I2C_SLEEP_RETENTION_MODULE(i2c_num));
+        err = sleep_retention_module_deinit(i2c_regs_retention[i2c_num].module_id);
     }
 #endif
 
diff --git a/components/driver/test_apps/.build-test-rules.yml b/components/driver/test_apps/.build-test-rules.yml
index f78fff4f30e..5554901f8c0 100644
--- a/components/driver/test_apps/.build-test-rules.yml
+++ b/components/driver/test_apps/.build-test-rules.yml
@@ -21,6 +21,9 @@ components/driver/test_apps/legacy_adc_driver:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: lack of runners, TODO IDF-9573
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: lack of runners
   depends_components:
     - efuse
     - esp_driver_i2s
diff --git a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h
index 0fdcb27e493..6bcac2a72d9 100644
--- a/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h
+++ b/components/driver/test_apps/components/test_driver_utils/include/test_spi_utils.h
@@ -94,11 +94,6 @@
 #define WIRE_DELAY              12.5
 #endif  //CONFIG_IDF_TARGET_ESP32
 
-#define GET_DMA_CHAN(HOST)      (HOST)
-
-#define TEST_DMA_CHAN_MASTER    GET_DMA_CHAN(TEST_SPI_HOST)
-#define TEST_DMA_CHAN_SLAVE     GET_DMA_CHAN(TEST_SLAVE_HOST)
-
 #define FUNC_SPI    SPI2_FUNC_NUM
 #define FUNC_GPIO   PIN_FUNC_GPIO
 
diff --git a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c
index 124021167f7..8e23021d84b 100644
--- a/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c
+++ b/components/driver/test_apps/components/test_driver_utils/test_spi_utils.c
@@ -91,6 +91,7 @@ void spitest_slave_task(void* arg)
         t.length = txdata.len;
         t.tx_buffer = txdata.start;
         t.rx_buffer = recvbuf + 8;
+        t.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO;
         //loop until trans_len != 0 to skip glitches
         do {
             TEST_ESP_OK(spi_slave_transmit(context->spi, &t, portMAX_DELAY));
@@ -231,6 +232,7 @@ void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx)
     esp_rom_gpio_connect_in_signal(gpio_num, signal_idx, 0);
 }
 
+#if (TEST_SPI_PERIPH_NUM >= 2)
 //Note this cs_dev_id is the ID of the connected devices' ID, e.g. if 2 devices are connected to the bus,
 //then the cs_dev_id of the 1st and 2nd devices are 0 and 1 respectively.
 void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, uint8_t cs_dev_id)
@@ -247,3 +249,4 @@ void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev,
     spitest_gpio_output_sel(bus.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out);
     spitest_gpio_input_sel(bus.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in);
 }
+#endif  //(TEST_SPI_PERIPH_NUM >= 2)
diff --git a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/README.md b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/README.md
index 46d16c788ce..844e5ee973b 100644
--- a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/README.md
+++ b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
diff --git a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/pytest_legacy_i2s.py b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/pytest_legacy_i2s.py
index a5a9a9a1fff..bb70f8ee6a7 100644
--- a/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/pytest_legacy_i2s.py
+++ b/components/driver/test_apps/i2s_test_apps/legacy_i2s_driver/pytest_legacy_i2s.py
@@ -12,6 +12,7 @@
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
+@pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
diff --git a/components/driver/test_apps/legacy_adc_driver/README.md b/components/driver/test_apps/legacy_adc_driver/README.md
index 3a502b1f86f..7b96141437e 100644
--- a/components/driver/test_apps/legacy_adc_driver/README.md
+++ b/components/driver/test_apps/legacy_adc_driver/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
diff --git a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
index 7a22fa26dce..ba4918e24d1 100644
--- a/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
+++ b/components/driver/test_apps/legacy_adc_driver/main/test_legacy_adc.c
@@ -81,6 +81,13 @@
 #define ADC_TEST_HIGH_VAL        4095
 #define ADC_TEST_HIGH_THRESH     200
 
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define ADC_TEST_LOW_VAL         2140
+#define ADC_TEST_LOW_THRESH      200
+
+#define ADC_TEST_HIGH_VAL        4095
+#define ADC_TEST_HIGH_THRESH     200
+
 #endif
 
 //ADC Channels
diff --git a/components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c b/components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c
index 5e7096a399f..45bd9c3750f 100644
--- a/components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c
+++ b/components/driver/test_apps/touch_sensor_v1/main/test_touch_v1.c
@@ -10,20 +10,19 @@
 #include "sdkconfig.h"
 
 #include "esp_system.h"
-#include "driver/touch_pad.h"
 #include "unity.h"
 #include "esp_system.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "esp_log.h"
-#include "soc/rtc_cntl_reg.h"
-#include "soc/rtc_cntl_struct.h"
+#include "soc/soc_caps.h"
 #include "soc/sens_reg.h"
 #include "soc/sens_struct.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_io_reg.h"
 #include "soc/rtc_io_struct.h"
+#include "driver/touch_sensor.h"
 #include "esp_rom_sys.h"
 #if CONFIG_PM_ENABLE
 #include "esp_pm.h"
diff --git a/components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c b/components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c
index 78b1d78a74c..479ffe702f1 100644
--- a/components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c
+++ b/components/driver/test_apps/touch_sensor_v2/main/test_touch_v2.c
@@ -12,7 +12,6 @@
 #include <string.h>
 #include <inttypes.h>
 #include "esp_system.h"
-#include "driver/touch_pad.h"
 #include "unity.h"
 #include "esp_system.h"
 #include "freertos/FreeRTOS.h"
@@ -20,8 +19,7 @@
 #include "freertos/semphr.h"
 #include "freertos/queue.h"
 #include "esp_log.h"
-#include "soc/rtc_cntl_reg.h"
-#include "soc/rtc_cntl_struct.h"
+#include "soc/soc_caps.h"
 #include "soc/sens_reg.h"
 #include "soc/sens_struct.h"
 #include "soc/rtc_cntl_reg.h"
@@ -30,6 +28,7 @@
 #include "soc/rtc_io_struct.h"
 #include "soc/syscon_reg.h"
 #include "driver/rtc_io.h"
+#include "driver/touch_sensor_legacy.h"
 #include "esp_rom_sys.h"
 
 static const char *TAG = "test_touch";
diff --git a/components/driver/test_apps/twai/main/test_twai_loop_back.c b/components/driver/test_apps/twai/main/test_twai_loop_back.c
index 7fea86000bf..dccc9223054 100644
--- a/components/driver/test_apps/twai/main/test_twai_loop_back.c
+++ b/components/driver/test_apps/twai/main/test_twai_loop_back.c
@@ -12,6 +12,9 @@
 #include "driver/twai.h"
 #include "soc/soc_caps.h"
 #include "esp_attr.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/esp_pmu.h"
 
 TEST_CASE("driver_life_cycle", "[twai-loop-back]")
 {
@@ -130,3 +133,90 @@ TEST_CASE("twai_mode_ext_no_ack_250kbps", "[twai-loop-back]")
         TEST_ESP_OK(twai_driver_uninstall_v2(twai_buses[i]));
     }
 }
+
+static void s_test_sleep_retention(bool allow_pd)
+{
+    // Prepare a TOP PD sleep
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+
+    twai_handle_t twai_buses[SOC_TWAI_CONTROLLER_NUM] = {0};
+    twai_timing_config_t t_config = TWAI_TIMING_CONFIG_250KBITS();
+    twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL();
+    // bind the TX and RX to the same GPIO to act like a loopback
+    twai_general_config_t g_config = TWAI_GENERAL_CONFIG_DEFAULT(0, 0, TWAI_MODE_NO_ACK);
+    g_config.general_flags.sleep_allow_pd = allow_pd;
+    twai_message_t tx_msg = {
+        .identifier = 0x12345,
+        .data_length_code = 6,
+        .data = {0x11, 0x22, 0x33, 0x44, 0x55, 0x66},
+        .self = true, // Transmitted message will also received by the same node
+        .extd = true, // Extended Frame Format (29bit ID)
+    };
+
+    for (int i = 0; i < SOC_TWAI_CONTROLLER_NUM; i++) {
+        g_config.controller_id = i;
+        g_config.tx_io = i;
+        g_config.rx_io = i;
+        printf("install twai driver %d\r\n", g_config.controller_id);
+        TEST_ESP_OK(twai_driver_install_v2(&g_config, &t_config, &f_config, &twai_buses[i]));
+    }
+
+    printf("Going into sleep...\n");
+    TEST_ESP_OK(esp_light_sleep_start());
+    printf("Waked up!\n");
+
+    // check if the sleep happened as expected
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_TWAI_SUPPORT_SLEEP_RETENTION
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL(allow_pd ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+
+    for (int i = 0; i < SOC_TWAI_CONTROLLER_NUM; i++) {
+        TEST_ESP_OK(twai_start_v2(twai_buses[i]));
+    }
+
+    for (int i = 0; i < SOC_TWAI_CONTROLLER_NUM; i++) {
+        printf("transmit message from %d\r\n", i);
+        tx_msg.data[5] = SOC_TWAI_CONTROLLER_NUM - i;
+        TEST_ESP_OK(twai_transmit_v2(twai_buses[i], &tx_msg, pdMS_TO_TICKS(1000)));
+    }
+
+    twai_message_t rx_msg;
+    for (int i = 0; i < SOC_TWAI_CONTROLLER_NUM; i++) {
+        printf("receive message from %d\r\n", i);
+        TEST_ESP_OK(twai_receive_v2(twai_buses[i], &rx_msg, pdMS_TO_TICKS(1000)));
+        TEST_ASSERT_TRUE(rx_msg.data_length_code == 6);
+        tx_msg.data[5] = SOC_TWAI_CONTROLLER_NUM - i;
+        for (int i = 0; i < 6; i++) {
+            TEST_ASSERT_EQUAL(tx_msg.data[i], rx_msg.data[i]);
+        }
+    }
+
+    for (int i = 0; i < SOC_TWAI_CONTROLLER_NUM; i++) {
+        TEST_ESP_OK(twai_stop_v2(twai_buses[i]));
+        TEST_ESP_OK(twai_driver_uninstall_v2(twai_buses[i]));
+    }
+
+    esp_sleep_set_sleep_context(NULL);
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+}
+
+#if SOC_TWAI_SUPPORT_SLEEP_RETENTION
+TEST_CASE("twai_mode_ext_no_ack_250kbps with sleep retention (allow pd)", "[twai-loop-back]")
+{
+    s_test_sleep_retention(true);
+}
+#endif
+
+TEST_CASE("twai_mode_ext_no_ack_250kbps with sleep retention (no pd)", "[twai-loop-back]")
+{
+    s_test_sleep_retention(false);
+}
diff --git a/components/driver/test_apps/twai/sdkconfig.ci.release b/components/driver/test_apps/twai/sdkconfig.ci.release
index 91d93f163e6..29ef87d9695 100644
--- a/components/driver/test_apps/twai/sdkconfig.ci.release
+++ b/components/driver/test_apps/twai/sdkconfig.ci.release
@@ -3,3 +3,5 @@ CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
 CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
+
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
diff --git a/components/driver/test_apps/twai/sdkconfig.defaults b/components/driver/test_apps/twai/sdkconfig.defaults
index b308cb2ddda..feceba725e2 100644
--- a/components/driver/test_apps/twai/sdkconfig.defaults
+++ b/components/driver/test_apps/twai/sdkconfig.defaults
@@ -1,2 +1,4 @@
 CONFIG_FREERTOS_HZ=1000
 CONFIG_ESP_TASK_WDT=n
+# primitives for checking sleep internal state
+CONFIG_ESP_SLEEP_DEBUG=y
diff --git a/components/driver/touch_sensor/esp32/include/driver/touch_sensor.h b/components/driver/touch_sensor/esp32/include/driver/touch_sensor.h
index 737faf02490..c1a6f759f27 100644
--- a/components/driver/touch_sensor/esp32/include/driver/touch_sensor.h
+++ b/components/driver/touch_sensor/esp32/include/driver/touch_sensor.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/driver/touch_sensor/esp32/touch_sensor.c b/components/driver/touch_sensor/esp32/touch_sensor.c
index e73d6dc6a12..fd54c452a03 100644
--- a/components/driver/touch_sensor/esp32/touch_sensor.c
+++ b/components/driver/touch_sensor/esp32/touch_sensor.c
@@ -27,7 +27,7 @@
 #define INVARIANTS
 #endif
 #include "sys/queue.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 #include "hal/touch_sensor_hal.h"
 
 typedef struct {
diff --git a/components/driver/touch_sensor/esp32s2/include/driver/touch_sensor.h b/components/driver/touch_sensor/esp32s2/include/driver/touch_sensor.h
index 06f835879f0..adb40726ae3 100644
--- a/components/driver/touch_sensor/esp32s2/include/driver/touch_sensor.h
+++ b/components/driver/touch_sensor/esp32s2/include/driver/touch_sensor.h
@@ -1,646 +1,17 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
-#include "driver/touch_sensor_common.h"
+#include "sdkconfig.h"
+#include "driver/touch_sensor_legacy.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Set touch sensor FSM start
- * @note  Start FSM after the touch sensor FSM mode is set.
- * @note  Call this function will reset benchmark of all touch channels.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_fsm_start(void);
-
-/**
- * @brief Stop touch sensor FSM.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_fsm_stop(void);
-
-/**
- * @brief Trigger a touch sensor measurement, only support in SW mode of FSM
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_sw_start(void);
-
-/**
- * @brief Set charge and discharge times of each measurement
- * @note  This function will specify the charge and discharge times in each measurement period
- *        The clock is sourced from SOC_MOD_CLK_RTC_FAST, and its default frequency is SOC_CLK_RC_FAST_FREQ_APPROX
- *        The touch sensor will record the total clock cycles of all the charge and discharge cycles as the final result (raw value)
- * @note  If the charge and discharge times is too small, it may lead to inaccurate results.
- *
- * @param charge_discharge_times    Charge and discharge times, range: 0 ~ 0xffff.
- *                                  No exact typical value can be recommended because the capacity is influenced by the hardware design and how finger touches,
- *                                  but suggest adjusting this value to make the measurement time around 1 ms.
- * @return
- *      - ESP_OK    Set charge and discharge times success
- */
-esp_err_t touch_pad_set_charge_discharge_times(uint16_t charge_discharge_times);
-
-/**
- * @brief Get charge and discharge times of each measurement
- *
- * @param charge_discharge_times    Charge and discharge times
- * @return
- *      - ESP_OK    Get charge_discharge_times success
- *      - ESP_ERR_INVALID_ARG   The input parameter is NULL
- */
-esp_err_t touch_pad_get_charge_discharge_times(uint16_t *charge_discharge_times);
-
-/**
- * @brief Set the interval between two measurements
- * @note  The touch sensor will sleep between two measurements
- *        This function is to set the interval cycle
- *        And the interval is clocked from SOC_MOD_CLK_RTC_SLOW, its default frequency is SOC_CLK_RC_SLOW_FREQ_APPROX
- *
- * @param interval_cycle    The interval between two measurements
- *                          sleep_time = interval_cycle / SOC_CLK_RC_SLOW_FREQ_APPROX.
- *                          The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
- * @return
- *      - ESP_OK    Set interval cycle success
- */
-esp_err_t touch_pad_set_measurement_interval(uint16_t interval_cycle);
-
-/**
- * @brief Get the interval between two measurements
- *
- * @param interval_cycle    The interval between two measurements
- * @return
- *      - ESP_OK    Get interval cycle success
- *      - ESP_ERR_INVALID_ARG   The input parameter is NULL
- */
-esp_err_t touch_pad_get_measurement_interval(uint16_t *interval_cycle);
-
-/**
- * @brief Set touch sensor times of charge and discharge and sleep time.
- *        Excessive total time will slow down the touch response.
- *        Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
- * @note  The touch sensor will measure time of a fixed number of charge/discharge cycles (specified as the second parameter).
- *        That means the time (raw value) will increase as the capacity of the touch pad is increasing.
- *        The time (raw value) here is the number of clock cycles which is sourced from SOC_MOD_CLK_RTC_FAST and at (SOC_CLK_RC_FAST_FREQ_APPROX) Hz as default
- * @note The greater the duty cycle of the measurement time, the more system power is consumed.
- *
- * @param sleep_cycle The touch sensor will sleep after each measurement.
- *                    sleep_cycle decide the interval between each measurement.
- *                    t_sleep = sleep_cycle / SOC_CLK_RC_SLOW_FREQ_APPROX.
- *                    The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
- * @param meas_times The times of charge and discharge in each measurement of touch channels.  Range: 0 ~ 0xffff.
- *                   Recommended typical value: Modify this value to make the measurement time around 1 ms.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_times)
-__attribute__((deprecated("please use 'touch_pad_set_charge_discharge_times' and 'touch_pad_set_measurement_interval' instead")));
-
-/**
- * @brief Get touch sensor times of charge and discharge and sleep time
- * @param sleep_cycle  Pointer to accept sleep cycle number
- * @param meas_times Pointer to accept measurement times count.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_times)
-__attribute__((deprecated("please use 'touch_pad_get_charge_discharge_times' and 'touch_pad_get_measurement_interval' instead")));
-
-/**
- * @brief Set the connection type of touch channels in idle status.
- *        When a channel is in measurement mode, other initialized channels are in idle mode.
- *        The touch channel is generally adjacent to the trace, so the connection state of the idle channel
- *        affects the stability and sensitivity of the test channel.
- *        The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels.
- *        The `CONN_GND`(grounding) setting increases the stability of touch channels.
- * @param type  Select idle channel connect to high resistance state or ground.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_idle_channel_connect(touch_pad_conn_type_t type);
-
-/**
- * @brief Get the connection type of touch channels in idle status.
- *        When a channel is in measurement mode, other initialized channels are in idle mode.
- *        The touch channel is generally adjacent to the trace, so the connection state of the idle channel
- *        affects the stability and sensitivity of the test channel.
- *        The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels.
- *        The `CONN_GND`(grounding) setting increases the stability of touch channels.
- * @param type  Pointer to connection type.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_idle_channel_connect(touch_pad_conn_type_t *type);
-
-/**
- * @brief Set the trigger threshold of touch sensor.
- *        The threshold determines the sensitivity of the touch sensor.
- *        The threshold is the original value of the trigger state minus the benchmark value.
- * @note  If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered.
- * @param touch_num touch pad index
- * @param threshold threshold of touch sensor. Should be less than the max change value of touch.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold);
-
-/**
- * @brief Get touch sensor trigger threshold
- * @param touch_num touch pad index
- * @param threshold pointer to accept threshold
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold);
-
-/**
- * @brief Register touch channel into touch sensor scan group.
- *        The working mode of the touch sensor is cyclically scanned.
- *        This function will set the scan bits according to the given bitmask.
- * @note  If set this mask, the FSM timer should be stop firsty.
- * @note  The touch sensor that in scan map, should be deinit GPIO function firstly by `touch_pad_io_init`.
- * @param enable_mask bitmask of touch sensor scan group.
- *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_channel_mask(uint16_t enable_mask);
-
-/**
- * @brief Get the touch sensor scan group bit mask.
- * @param enable_mask Pointer to bitmask of touch sensor scan group.
- *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_channel_mask(uint16_t *enable_mask);
-
-/**
- * @brief Clear touch channel from touch sensor scan group.
- *        The working mode of the touch sensor is cyclically scanned.
- *        This function will clear the scan bits according to the given bitmask.
- * @note  If clear all mask, the FSM timer should be stop firsty.
- * @param enable_mask bitmask of touch sensor scan group.
- *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_clear_channel_mask(uint16_t enable_mask);
-
-/**
- * @brief Configure parameter for each touch channel.
- * @note  Touch num 0 is denoise channel, please use `touch_pad_denoise_enable` to set denoise function
- * @param touch_num touch pad index
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG if argument wrong
- *     - ESP_FAIL if touch pad not initialized
- */
-esp_err_t touch_pad_config(touch_pad_t touch_num);
-
-/**
- * @brief Reset the FSM of touch module.
- * @note  Call this function after `touch_pad_fsm_stop`.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_reset(void);
-
-/**
- * @brief Get the current measure channel.
- * @note  Should be called when touch sensor measurement is in cyclic scan mode.
- * @return
- *      - touch channel number
- */
-touch_pad_t touch_pad_get_current_meas_channel(void);
-
-/**
- * @brief Get the touch sensor interrupt status mask.
- * @return
- *      - touch interrupt bit
- */
-uint32_t touch_pad_read_intr_status_mask(void);
-
-/**
- * @brief Enable touch sensor interrupt by bitmask.
- * @note  This API can be called in ISR handler.
- * @param int_mask Pad mask to enable interrupts
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_intr_enable(touch_pad_intr_mask_t int_mask);
-
-/**
- * @brief Disable touch sensor interrupt by bitmask.
- * @note  This API can be called in ISR handler.
- * @param int_mask Pad mask to disable interrupts
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_intr_disable(touch_pad_intr_mask_t int_mask);
-
-/**
- * @brief Clear touch sensor interrupt by bitmask.
- * @param int_mask Pad mask to clear interrupts
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_intr_clear(touch_pad_intr_mask_t int_mask);
-
-/**
- * @brief   Register touch-pad ISR.
- *          The handler will be attached to the same CPU core that this function is running on.
- * @param fn  Pointer to ISR handler
- * @param arg  Parameter for ISR
- * @param intr_mask Enable touch sensor interrupt handler by bitmask.
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Arguments error
- *     - ESP_ERR_NO_MEM No memory
- */
-esp_err_t touch_pad_isr_register(intr_handler_t fn, void *arg, touch_pad_intr_mask_t intr_mask);
-
-/**
- * @brief Enable/disable the timeout check and set timeout threshold for all touch sensor channels measurements.
- *        If enable: When the touch reading of a touch channel exceeds the measurement threshold, a timeout interrupt will be generated.
- *        If disable: the FSM does not check if the channel under measurement times out.
- *
- * @note The threshold compared with touch readings.
- * @note In order to avoid abnormal short circuit of some touch channels. This function should be turned on.
- *       Ensure the normal operation of other touch channels.
- *
- * @param enable true(default): Enable the timeout check; false: Disable the timeout check.
- * @param threshold For all channels, the maximum value that will not be exceeded during normal operation.
- *
-* @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_timeout_set(bool enable, uint32_t threshold);
-
-/**
- * @brief Call this interface after timeout to make the touch channel resume normal work. Point on the next channel to measure.
- *        If this API is not called, the touch FSM will stop the measurement after timeout interrupt.
- *
- * @note  Call this API after finishes the exception handling by user.
- *
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_timeout_resume(void);
-
-/**
- * @brief get raw data of touch sensor.
- * @note After the initialization is complete, the "raw_data" is max value. You need to wait for a measurement
- *       cycle before you can read the correct touch value.
- * @param touch_num touch pad index
- * @param raw_data pointer to accept touch sensor value
- * @return
- *     - ESP_OK Success
- *     - ESP_FAIL Touch channel 0 haven't this parameter.
- */
-
-esp_err_t touch_pad_read_raw_data(touch_pad_t touch_num, uint32_t *raw_data);
-
-/**
- * @brief get benchmark of touch sensor.
- * @note After initialization, the benchmark value is the maximum during the first measurement period.
- * @param touch_num touch pad index
- * @param benchmark pointer to accept touch sensor benchmark value
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Touch channel 0 haven't this parameter.
- */
-esp_err_t touch_pad_read_benchmark(touch_pad_t touch_num, uint32_t *benchmark);
-
-/**
- * @brief Get smoothed data that obtained by filtering the raw data.
- *
- * @param touch_num touch pad index
- * @param smooth pointer to smoothed data
- */
-esp_err_t touch_pad_filter_read_smooth(touch_pad_t touch_num, uint32_t *smooth);
-
-/**
- * @brief Force reset benchmark to raw data of touch sensor.
- * @param touch_num touch pad index
- *                  - TOUCH_PAD_MAX Reset basaline of all channels
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_reset_benchmark(touch_pad_t touch_num);
-
-/**
- * @brief set parameter of touch sensor filter and detection algorithm.
- *        For more details on the detection algorithm, please refer to the application documentation.
- * @param filter_info select filter type and threshold of detection algorithm
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_filter_set_config(const touch_filter_config_t *filter_info);
-
-/**
- * @brief get parameter of touch sensor filter and detection algorithm.
- *        For more details on the detection algorithm, please refer to the application documentation.
- * @param filter_info select filter type and threshold of detection algorithm
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info);
-
-/**
- * @brief enable touch sensor filter for detection algorithm.
- *        For more details on the detection algorithm, please refer to the application documentation.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_filter_enable(void);
-
-/**
- * @brief disable touch sensor filter for detection algorithm.
- *        For more details on the detection algorithm, please refer to the application documentation.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_filter_disable(void);
-
-/**
- * @brief set parameter of denoise pad (TOUCH_PAD_NUM0).
- *        T0 is an internal channel that does not have a corresponding external GPIO.
- *        T0 will work simultaneously with the measured channel Tn. Finally, the actual
- *        measured value of Tn is the value after subtracting lower bits of T0.
- *        The noise reduction function filters out interference introduced simultaneously on all channels,
- *        such as noise introduced by power supplies and external EMI.
- * @param denoise parameter of denoise
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_set_config(const touch_pad_denoise_t *denoise);
-
-/**
- * @brief get parameter of denoise pad (TOUCH_PAD_NUM0).
- * @param denoise Pointer to parameter of denoise
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise);
-
-/**
- * @brief enable denoise function.
- *        T0 is an internal channel that does not have a corresponding external GPIO.
- *        T0 will work simultaneously with the measured channel Tn. Finally, the actual
- *        measured value of Tn is the value after subtracting lower bits of T0.
- *        The noise reduction function filters out interference introduced simultaneously on all channels,
- *        such as noise introduced by power supplies and external EMI.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_enable(void);
-
-/**
- * @brief disable denoise function.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_disable(void);
-
-/**
- * @brief Get denoise measure value (TOUCH_PAD_NUM0).
- * @param data Pointer to receive denoise value
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_read_data(uint32_t *data);
-
-/**
- * @brief set parameter of waterproof function.
- *
- *        The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel.
- *        Guard pad is used to detect the large area of water covering the touch panel.
- *        Shield pad is used to shield the influence of water droplets covering the touch panel.
- *        It is generally designed as a grid and is placed around the touch buttons.
- *
- * @param waterproof parameter of waterproof
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_waterproof_set_config(const touch_pad_waterproof_t *waterproof);
-
-/**
- * @brief get parameter of waterproof function.
- * @param waterproof parameter of waterproof
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof);
-
-/**
- * @brief Enable parameter of waterproof function.
- *        Should be called after function ``touch_pad_waterproof_set_config``.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_waterproof_enable(void);
-
-/**
- * @brief Disable parameter of waterproof function.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_waterproof_disable(void);
-
-/**
- * @brief Enable/disable proximity function of touch channels.
- *        The proximity sensor measurement is the accumulation of touch channel measurements.
- *
- * @note Supports up to three touch channels configured as proximity sensors.
- * @param touch_num touch pad index
- * @param enabled true: enable the proximity function; false:  disable the proximity function
- * @return
- *     - ESP_OK: Configured correctly.
- *     - ESP_ERR_INVALID_ARG: Touch channel number error.
- *     - ESP_ERR_NOT_SUPPORTED: Don't support configured.
- */
-esp_err_t touch_pad_proximity_enable(touch_pad_t touch_num, bool enabled);
-
-/**
- * @brief Set measure count of proximity channel.
- *        The proximity sensor measurement is the accumulation of touch channel measurements.
- *
- * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`.
- * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`.
- * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255.
- * @return
- *     - ESP_OK: Configured correctly.
- *     - ESP_ERR_INVALID_ARG: Touch channel number error.
- */
-esp_err_t touch_pad_proximity_set_count(touch_pad_t touch_num, uint32_t count);
-
-/**
- * @brief Get measure count of proximity channel.
- *        The proximity sensor measurement is the accumulation of touch channel measurements.
- *
- * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`.
- * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`.
- * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255.
- * @return
- *     - ESP_OK: Configured correctly.
- *     - ESP_ERR_INVALID_ARG: Touch channel number error.
- */
-esp_err_t touch_pad_proximity_get_count(touch_pad_t touch_num, uint32_t *count);
-
-/**
- * @brief Get the accumulated measurement of the proximity sensor.
- *        The proximity sensor measurement is the accumulation of touch channel measurements.
- * @param touch_num touch pad index
- * @param measure_out If the accumulation process does not end, the `measure_out` is the process value.
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Touch num is not proximity
- */
-esp_err_t touch_pad_proximity_get_data(touch_pad_t touch_num, uint32_t *measure_out);
-
-/**
- * @brief Get parameter of touch sensor sleep channel.
- *        The touch sensor can works in sleep mode to wake up sleep.
- *
- * @note  After the sleep channel is configured, Please use special functions for sleep channel.
- *        e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading.
- *
- * @param slp_config touch sleep pad config.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_get_info(touch_pad_sleep_channel_t *slp_config);
-
-/**
- * @brief Enable/Disable sleep channel function for touch sensor.
- *        The touch sensor can works in sleep mode to wake up sleep.
- *
- * @note  ESP32S2 only support one sleep channel.
- * @note  After the sleep channel is configured, Please use special functions for sleep channel.
- *        e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading.
- *
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param enable true: enable sleep pad for touch sensor; false: disable sleep pad for touch sensor;
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_enable(touch_pad_t pad_num, bool enable);
-
-/**
- * @brief Enable/Disable proximity function for sleep channel.
- *        The touch sensor can works in sleep mode to wake up sleep.
- *
- * @note  ESP32S2 only support one sleep channel.
- *
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param enable true: enable proximity for sleep channel; false: disable proximity for sleep channel;
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_enable_proximity(touch_pad_t pad_num, bool enable);
-
-/**
- * @brief Set the trigger threshold of touch sensor in deep sleep.
- *        The threshold determines the sensitivity of the touch sensor.
- *
- * @note  In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
- *
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param touch_thres touch sleep pad threshold
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_set_threshold(touch_pad_t pad_num, uint32_t touch_thres);
-
-/**
- * @brief Get the trigger threshold of touch sensor in deep sleep.
- *        The threshold determines the sensitivity of the touch sensor.
- *
- * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
- *
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param touch_thres touch sleep pad threshold
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_get_threshold(touch_pad_t pad_num, uint32_t *touch_thres);
-
-/**
- * @brief Read benchmark of touch sensor sleep channel.
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param benchmark pointer to accept touch sensor benchmark value
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG parameter is NULL
- */
-esp_err_t touch_pad_sleep_channel_read_benchmark(touch_pad_t pad_num, uint32_t *benchmark);
-
-/**
- * @brief Read smoothed data of touch sensor sleep channel.
- *        Smoothed data is filtered from the raw data.
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param smooth_data pointer to accept touch sensor smoothed data
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG parameter is NULL
- */
-esp_err_t touch_pad_sleep_channel_read_smooth(touch_pad_t pad_num, uint32_t *smooth_data);
-
-/**
- * @brief Read raw data of touch sensor sleep channel.
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param raw_data pointer to accept touch sensor raw data
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG parameter is NULL
- */
-esp_err_t touch_pad_sleep_channel_read_data(touch_pad_t pad_num, uint32_t *raw_data);
-
-/**
- * @brief Reset benchmark of touch sensor sleep channel.
- *
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_reset_benchmark(void);
-
-/**
- * @brief Read proximity count of touch sensor sleep channel.
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param proximity_cnt pointer to accept touch sensor proximity count value
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG parameter is NULL
- */
-esp_err_t touch_pad_sleep_channel_read_proximity_cnt(touch_pad_t pad_num, uint32_t *proximity_cnt);
-
-/**
- * @brief Change the operating frequency of touch pad in deep sleep state. Reducing the operating frequency can effectively reduce power consumption.
- *        If this function is not called, the working frequency of touch in the deep sleep state is the same as that in the wake-up state.
- *
- * @param sleep_cycle The touch sensor will sleep after each measurement.
- *                    sleep_cycle decide the interval between each measurement.
- *                    t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency).
- *                    The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
- * @param meas_times The times of charge and discharge in each measure process of touch channels.
- *                  The timer frequency is 8Mhz. Range: 0 ~ 0xffff.
- *                  Recommended typical value: Modify this value to make the measurement time around 1ms.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_set_work_time(uint16_t sleep_cycle, uint16_t meas_times);
-
-#ifdef __cplusplus
-}
+#if !CONFIG_TOUCH_SUPPRESS_DEPRECATE_WARN
+#warning "This set of Touch APIs has been deprecated, \
+please include 'driver/touch_sens.h' instead. \
+if you want to keep using the old APIs and ignore this warning, \
+you can enable 'Suppress legacy driver deprecated warning' option under 'Touch Configuration' menu in Kconfig"
 #endif
diff --git a/components/driver/touch_sensor/esp32s2/include/driver/touch_sensor_legacy.h b/components/driver/touch_sensor/esp32s2/include/driver/touch_sensor_legacy.h
new file mode 100644
index 00000000000..96ce7130674
--- /dev/null
+++ b/components/driver/touch_sensor/esp32s2/include/driver/touch_sensor_legacy.h
@@ -0,0 +1,646 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "driver/touch_sensor_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set touch sensor FSM start
+ * @note  Start FSM after the touch sensor FSM mode is set.
+ * @note  Call this function will reset benchmark of all touch channels.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_fsm_start(void);
+
+/**
+ * @brief Stop touch sensor FSM.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_fsm_stop(void);
+
+/**
+ * @brief Trigger a touch sensor measurement, only support in SW mode of FSM
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_sw_start(void);
+
+/**
+ * @brief Set charge and discharge times of each measurement
+ * @note  This function will specify the charge and discharge times in each measurement period
+ *        The clock is sourced from SOC_MOD_CLK_RTC_FAST, and its default frequency is SOC_CLK_RC_FAST_FREQ_APPROX
+ *        The touch sensor will record the total clock cycles of all the charge and discharge cycles as the final result (raw value)
+ * @note  If the charge and discharge times is too small, it may lead to inaccurate results.
+ *
+ * @param charge_discharge_times    Charge and discharge times, range: 0 ~ 0xffff.
+ *                                  No exact typical value can be recommended because the capacity is influenced by the hardware design and how finger touches,
+ *                                  but suggest adjusting this value to make the measurement time around 1 ms.
+ * @return
+ *      - ESP_OK    Set charge and discharge times success
+ */
+esp_err_t touch_pad_set_charge_discharge_times(uint16_t charge_discharge_times);
+
+/**
+ * @brief Get charge and discharge times of each measurement
+ *
+ * @param charge_discharge_times    Charge and discharge times
+ * @return
+ *      - ESP_OK    Get charge_discharge_times success
+ *      - ESP_ERR_INVALID_ARG   The input parameter is NULL
+ */
+esp_err_t touch_pad_get_charge_discharge_times(uint16_t *charge_discharge_times);
+
+/**
+ * @brief Set the interval between two measurements
+ * @note  The touch sensor will sleep between two measurements
+ *        This function is to set the interval cycle
+ *        And the interval is clocked from SOC_MOD_CLK_RTC_SLOW, its default frequency is SOC_CLK_RC_SLOW_FREQ_APPROX
+ *
+ * @param interval_cycle    The interval between two measurements
+ *                          sleep_time = interval_cycle / SOC_CLK_RC_SLOW_FREQ_APPROX.
+ *                          The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ * @return
+ *      - ESP_OK    Set interval cycle success
+ */
+esp_err_t touch_pad_set_measurement_interval(uint16_t interval_cycle);
+
+/**
+ * @brief Get the interval between two measurements
+ *
+ * @param interval_cycle    The interval between two measurements
+ * @return
+ *      - ESP_OK    Get interval cycle success
+ *      - ESP_ERR_INVALID_ARG   The input parameter is NULL
+ */
+esp_err_t touch_pad_get_measurement_interval(uint16_t *interval_cycle);
+
+/**
+ * @brief Set touch sensor times of charge and discharge and sleep time.
+ *        Excessive total time will slow down the touch response.
+ *        Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
+ * @note  The touch sensor will measure time of a fixed number of charge/discharge cycles (specified as the second parameter).
+ *        That means the time (raw value) will increase as the capacity of the touch pad is increasing.
+ *        The time (raw value) here is the number of clock cycles which is sourced from SOC_MOD_CLK_RTC_FAST and at (SOC_CLK_RC_FAST_FREQ_APPROX) Hz as default
+ * @note The greater the duty cycle of the measurement time, the more system power is consumed.
+ *
+ * @param sleep_cycle The touch sensor will sleep after each measurement.
+ *                    sleep_cycle decide the interval between each measurement.
+ *                    t_sleep = sleep_cycle / SOC_CLK_RC_SLOW_FREQ_APPROX.
+ *                    The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ * @param meas_times The times of charge and discharge in each measurement of touch channels.  Range: 0 ~ 0xffff.
+ *                   Recommended typical value: Modify this value to make the measurement time around 1 ms.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_times)
+__attribute__((deprecated("please use 'touch_pad_set_charge_discharge_times' and 'touch_pad_set_measurement_interval' instead")));
+
+/**
+ * @brief Get touch sensor times of charge and discharge and sleep time
+ * @param sleep_cycle  Pointer to accept sleep cycle number
+ * @param meas_times Pointer to accept measurement times count.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_times)
+__attribute__((deprecated("please use 'touch_pad_get_charge_discharge_times' and 'touch_pad_get_measurement_interval' instead")));
+
+/**
+ * @brief Set the connection type of touch channels in idle status.
+ *        When a channel is in measurement mode, other initialized channels are in idle mode.
+ *        The touch channel is generally adjacent to the trace, so the connection state of the idle channel
+ *        affects the stability and sensitivity of the test channel.
+ *        The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels.
+ *        The `CONN_GND`(grounding) setting increases the stability of touch channels.
+ * @param type  Select idle channel connect to high resistance state or ground.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_idle_channel_connect(touch_pad_conn_type_t type);
+
+/**
+ * @brief Get the connection type of touch channels in idle status.
+ *        When a channel is in measurement mode, other initialized channels are in idle mode.
+ *        The touch channel is generally adjacent to the trace, so the connection state of the idle channel
+ *        affects the stability and sensitivity of the test channel.
+ *        The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels.
+ *        The `CONN_GND`(grounding) setting increases the stability of touch channels.
+ * @param type  Pointer to connection type.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_idle_channel_connect(touch_pad_conn_type_t *type);
+
+/**
+ * @brief Set the trigger threshold of touch sensor.
+ *        The threshold determines the sensitivity of the touch sensor.
+ *        The threshold is the original value of the trigger state minus the benchmark value.
+ * @note  If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered.
+ * @param touch_num touch pad index
+ * @param threshold threshold of touch sensor. Should be less than the max change value of touch.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold);
+
+/**
+ * @brief Get touch sensor trigger threshold
+ * @param touch_num touch pad index
+ * @param threshold pointer to accept threshold
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold);
+
+/**
+ * @brief Register touch channel into touch sensor scan group.
+ *        The working mode of the touch sensor is cyclically scanned.
+ *        This function will set the scan bits according to the given bitmask.
+ * @note  If set this mask, the FSM timer should be stop firsty.
+ * @note  The touch sensor that in scan map, should be deinit GPIO function firstly by `touch_pad_io_init`.
+ * @param enable_mask bitmask of touch sensor scan group.
+ *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_channel_mask(uint16_t enable_mask);
+
+/**
+ * @brief Get the touch sensor scan group bit mask.
+ * @param enable_mask Pointer to bitmask of touch sensor scan group.
+ *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_channel_mask(uint16_t *enable_mask);
+
+/**
+ * @brief Clear touch channel from touch sensor scan group.
+ *        The working mode of the touch sensor is cyclically scanned.
+ *        This function will clear the scan bits according to the given bitmask.
+ * @note  If clear all mask, the FSM timer should be stop firsty.
+ * @param enable_mask bitmask of touch sensor scan group.
+ *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_clear_channel_mask(uint16_t enable_mask);
+
+/**
+ * @brief Configure parameter for each touch channel.
+ * @note  Touch num 0 is denoise channel, please use `touch_pad_denoise_enable` to set denoise function
+ * @param touch_num touch pad index
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG if argument wrong
+ *     - ESP_FAIL if touch pad not initialized
+ */
+esp_err_t touch_pad_config(touch_pad_t touch_num);
+
+/**
+ * @brief Reset the FSM of touch module.
+ * @note  Call this function after `touch_pad_fsm_stop`.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_reset(void);
+
+/**
+ * @brief Get the current measure channel.
+ * @note  Should be called when touch sensor measurement is in cyclic scan mode.
+ * @return
+ *      - touch channel number
+ */
+touch_pad_t touch_pad_get_current_meas_channel(void);
+
+/**
+ * @brief Get the touch sensor interrupt status mask.
+ * @return
+ *      - touch interrupt bit
+ */
+uint32_t touch_pad_read_intr_status_mask(void);
+
+/**
+ * @brief Enable touch sensor interrupt by bitmask.
+ * @note  This API can be called in ISR handler.
+ * @param int_mask Pad mask to enable interrupts
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_intr_enable(touch_pad_intr_mask_t int_mask);
+
+/**
+ * @brief Disable touch sensor interrupt by bitmask.
+ * @note  This API can be called in ISR handler.
+ * @param int_mask Pad mask to disable interrupts
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_intr_disable(touch_pad_intr_mask_t int_mask);
+
+/**
+ * @brief Clear touch sensor interrupt by bitmask.
+ * @param int_mask Pad mask to clear interrupts
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_intr_clear(touch_pad_intr_mask_t int_mask);
+
+/**
+ * @brief   Register touch-pad ISR.
+ *          The handler will be attached to the same CPU core that this function is running on.
+ * @param fn  Pointer to ISR handler
+ * @param arg  Parameter for ISR
+ * @param intr_mask Enable touch sensor interrupt handler by bitmask.
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Arguments error
+ *     - ESP_ERR_NO_MEM No memory
+ */
+esp_err_t touch_pad_isr_register(intr_handler_t fn, void *arg, touch_pad_intr_mask_t intr_mask);
+
+/**
+ * @brief Enable/disable the timeout check and set timeout threshold for all touch sensor channels measurements.
+ *        If enable: When the touch reading of a touch channel exceeds the measurement threshold, a timeout interrupt will be generated.
+ *        If disable: the FSM does not check if the channel under measurement times out.
+ *
+ * @note The threshold compared with touch readings.
+ * @note In order to avoid abnormal short circuit of some touch channels. This function should be turned on.
+ *       Ensure the normal operation of other touch channels.
+ *
+ * @param enable true(default): Enable the timeout check; false: Disable the timeout check.
+ * @param threshold For all channels, the maximum value that will not be exceeded during normal operation.
+ *
+* @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_timeout_set(bool enable, uint32_t threshold);
+
+/**
+ * @brief Call this interface after timeout to make the touch channel resume normal work. Point on the next channel to measure.
+ *        If this API is not called, the touch FSM will stop the measurement after timeout interrupt.
+ *
+ * @note  Call this API after finishes the exception handling by user.
+ *
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_timeout_resume(void);
+
+/**
+ * @brief get raw data of touch sensor.
+ * @note After the initialization is complete, the "raw_data" is max value. You need to wait for a measurement
+ *       cycle before you can read the correct touch value.
+ * @param touch_num touch pad index
+ * @param raw_data pointer to accept touch sensor value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_FAIL Touch channel 0 haven't this parameter.
+ */
+
+esp_err_t touch_pad_read_raw_data(touch_pad_t touch_num, uint32_t *raw_data);
+
+/**
+ * @brief get benchmark of touch sensor.
+ * @note After initialization, the benchmark value is the maximum during the first measurement period.
+ * @param touch_num touch pad index
+ * @param benchmark pointer to accept touch sensor benchmark value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Touch channel 0 haven't this parameter.
+ */
+esp_err_t touch_pad_read_benchmark(touch_pad_t touch_num, uint32_t *benchmark);
+
+/**
+ * @brief Get smoothed data that obtained by filtering the raw data.
+ *
+ * @param touch_num touch pad index
+ * @param smooth pointer to smoothed data
+ */
+esp_err_t touch_pad_filter_read_smooth(touch_pad_t touch_num, uint32_t *smooth);
+
+/**
+ * @brief Force reset benchmark to raw data of touch sensor.
+ * @param touch_num touch pad index
+ *                  - TOUCH_PAD_MAX Reset basaline of all channels
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_reset_benchmark(touch_pad_t touch_num);
+
+/**
+ * @brief set parameter of touch sensor filter and detection algorithm.
+ *        For more details on the detection algorithm, please refer to the application documentation.
+ * @param filter_info select filter type and threshold of detection algorithm
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_filter_set_config(const touch_filter_config_t *filter_info);
+
+/**
+ * @brief get parameter of touch sensor filter and detection algorithm.
+ *        For more details on the detection algorithm, please refer to the application documentation.
+ * @param filter_info select filter type and threshold of detection algorithm
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info);
+
+/**
+ * @brief enable touch sensor filter for detection algorithm.
+ *        For more details on the detection algorithm, please refer to the application documentation.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_filter_enable(void);
+
+/**
+ * @brief disable touch sensor filter for detection algorithm.
+ *        For more details on the detection algorithm, please refer to the application documentation.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_filter_disable(void);
+
+/**
+ * @brief set parameter of denoise pad (TOUCH_PAD_NUM0).
+ *        T0 is an internal channel that does not have a corresponding external GPIO.
+ *        T0 will work simultaneously with the measured channel Tn. Finally, the actual
+ *        measured value of Tn is the value after subtracting lower bits of T0.
+ *        The noise reduction function filters out interference introduced simultaneously on all channels,
+ *        such as noise introduced by power supplies and external EMI.
+ * @param denoise parameter of denoise
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_set_config(const touch_pad_denoise_t *denoise);
+
+/**
+ * @brief get parameter of denoise pad (TOUCH_PAD_NUM0).
+ * @param denoise Pointer to parameter of denoise
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise);
+
+/**
+ * @brief enable denoise function.
+ *        T0 is an internal channel that does not have a corresponding external GPIO.
+ *        T0 will work simultaneously with the measured channel Tn. Finally, the actual
+ *        measured value of Tn is the value after subtracting lower bits of T0.
+ *        The noise reduction function filters out interference introduced simultaneously on all channels,
+ *        such as noise introduced by power supplies and external EMI.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_enable(void);
+
+/**
+ * @brief disable denoise function.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_disable(void);
+
+/**
+ * @brief Get denoise measure value (TOUCH_PAD_NUM0).
+ * @param data Pointer to receive denoise value
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_read_data(uint32_t *data);
+
+/**
+ * @brief set parameter of waterproof function.
+ *
+ *        The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel.
+ *        Guard pad is used to detect the large area of water covering the touch panel.
+ *        Shield pad is used to shield the influence of water droplets covering the touch panel.
+ *        It is generally designed as a grid and is placed around the touch buttons.
+ *
+ * @param waterproof parameter of waterproof
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_waterproof_set_config(const touch_pad_waterproof_t *waterproof);
+
+/**
+ * @brief get parameter of waterproof function.
+ * @param waterproof parameter of waterproof
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof);
+
+/**
+ * @brief Enable parameter of waterproof function.
+ *        Should be called after function ``touch_pad_waterproof_set_config``.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_waterproof_enable(void);
+
+/**
+ * @brief Disable parameter of waterproof function.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_waterproof_disable(void);
+
+/**
+ * @brief Enable/disable proximity function of touch channels.
+ *        The proximity sensor measurement is the accumulation of touch channel measurements.
+ *
+ * @note Supports up to three touch channels configured as proximity sensors.
+ * @param touch_num touch pad index
+ * @param enabled true: enable the proximity function; false:  disable the proximity function
+ * @return
+ *     - ESP_OK: Configured correctly.
+ *     - ESP_ERR_INVALID_ARG: Touch channel number error.
+ *     - ESP_ERR_NOT_SUPPORTED: Don't support configured.
+ */
+esp_err_t touch_pad_proximity_enable(touch_pad_t touch_num, bool enabled);
+
+/**
+ * @brief Set measure count of proximity channel.
+ *        The proximity sensor measurement is the accumulation of touch channel measurements.
+ *
+ * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`.
+ * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`.
+ * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255.
+ * @return
+ *     - ESP_OK: Configured correctly.
+ *     - ESP_ERR_INVALID_ARG: Touch channel number error.
+ */
+esp_err_t touch_pad_proximity_set_count(touch_pad_t touch_num, uint32_t count);
+
+/**
+ * @brief Get measure count of proximity channel.
+ *        The proximity sensor measurement is the accumulation of touch channel measurements.
+ *
+ * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`.
+ * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`.
+ * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255.
+ * @return
+ *     - ESP_OK: Configured correctly.
+ *     - ESP_ERR_INVALID_ARG: Touch channel number error.
+ */
+esp_err_t touch_pad_proximity_get_count(touch_pad_t touch_num, uint32_t *count);
+
+/**
+ * @brief Get the accumulated measurement of the proximity sensor.
+ *        The proximity sensor measurement is the accumulation of touch channel measurements.
+ * @param touch_num touch pad index
+ * @param measure_out If the accumulation process does not end, the `measure_out` is the process value.
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Touch num is not proximity
+ */
+esp_err_t touch_pad_proximity_get_data(touch_pad_t touch_num, uint32_t *measure_out);
+
+/**
+ * @brief Get parameter of touch sensor sleep channel.
+ *        The touch sensor can works in sleep mode to wake up sleep.
+ *
+ * @note  After the sleep channel is configured, Please use special functions for sleep channel.
+ *        e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading.
+ *
+ * @param slp_config touch sleep pad config.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_get_info(touch_pad_sleep_channel_t *slp_config);
+
+/**
+ * @brief Enable/Disable sleep channel function for touch sensor.
+ *        The touch sensor can works in sleep mode to wake up sleep.
+ *
+ * @note  ESP32S2 only support one sleep channel.
+ * @note  After the sleep channel is configured, Please use special functions for sleep channel.
+ *        e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading.
+ *
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param enable true: enable sleep pad for touch sensor; false: disable sleep pad for touch sensor;
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_enable(touch_pad_t pad_num, bool enable);
+
+/**
+ * @brief Enable/Disable proximity function for sleep channel.
+ *        The touch sensor can works in sleep mode to wake up sleep.
+ *
+ * @note  ESP32S2 only support one sleep channel.
+ *
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param enable true: enable proximity for sleep channel; false: disable proximity for sleep channel;
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_enable_proximity(touch_pad_t pad_num, bool enable);
+
+/**
+ * @brief Set the trigger threshold of touch sensor in deep sleep.
+ *        The threshold determines the sensitivity of the touch sensor.
+ *
+ * @note  In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
+ *
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param touch_thres touch sleep pad threshold
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_set_threshold(touch_pad_t pad_num, uint32_t touch_thres);
+
+/**
+ * @brief Get the trigger threshold of touch sensor in deep sleep.
+ *        The threshold determines the sensitivity of the touch sensor.
+ *
+ * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
+ *
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param touch_thres touch sleep pad threshold
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_get_threshold(touch_pad_t pad_num, uint32_t *touch_thres);
+
+/**
+ * @brief Read benchmark of touch sensor sleep channel.
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param benchmark pointer to accept touch sensor benchmark value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG parameter is NULL
+ */
+esp_err_t touch_pad_sleep_channel_read_benchmark(touch_pad_t pad_num, uint32_t *benchmark);
+
+/**
+ * @brief Read smoothed data of touch sensor sleep channel.
+ *        Smoothed data is filtered from the raw data.
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param smooth_data pointer to accept touch sensor smoothed data
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG parameter is NULL
+ */
+esp_err_t touch_pad_sleep_channel_read_smooth(touch_pad_t pad_num, uint32_t *smooth_data);
+
+/**
+ * @brief Read raw data of touch sensor sleep channel.
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param raw_data pointer to accept touch sensor raw data
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG parameter is NULL
+ */
+esp_err_t touch_pad_sleep_channel_read_data(touch_pad_t pad_num, uint32_t *raw_data);
+
+/**
+ * @brief Reset benchmark of touch sensor sleep channel.
+ *
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_reset_benchmark(void);
+
+/**
+ * @brief Read proximity count of touch sensor sleep channel.
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param proximity_cnt pointer to accept touch sensor proximity count value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG parameter is NULL
+ */
+esp_err_t touch_pad_sleep_channel_read_proximity_cnt(touch_pad_t pad_num, uint32_t *proximity_cnt);
+
+/**
+ * @brief Change the operating frequency of touch pad in deep sleep state. Reducing the operating frequency can effectively reduce power consumption.
+ *        If this function is not called, the working frequency of touch in the deep sleep state is the same as that in the wake-up state.
+ *
+ * @param sleep_cycle The touch sensor will sleep after each measurement.
+ *                    sleep_cycle decide the interval between each measurement.
+ *                    t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency).
+ *                    The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ * @param meas_times The times of charge and discharge in each measure process of touch channels.
+ *                  The timer frequency is 8Mhz. Range: 0 ~ 0xffff.
+ *                  Recommended typical value: Modify this value to make the measurement time around 1ms.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_set_work_time(uint16_t sleep_cycle, uint16_t meas_times);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/driver/touch_sensor/esp32s2/touch_sensor.c b/components/driver/touch_sensor/esp32s2/touch_sensor.c
index 42ed7c6291d..2c46fa1eb3c 100644
--- a/components/driver/touch_sensor/esp32s2/touch_sensor.c
+++ b/components/driver/touch_sensor/esp32s2/touch_sensor.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,13 +16,13 @@
 #include "freertos/timers.h"
 #include "esp_intr_alloc.h"
 #include "driver/rtc_io.h"
-#include "driver/touch_pad.h"
+#include "driver/touch_sensor_common.h"
 #include "esp_private/rtc_ctrl.h"
 #include "driver/gpio.h"
 #include "sdkconfig.h"
 #include "esp_check.h"
 
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 #include "hal/touch_sensor_hal.h"
 
 #ifndef NDEBUG
@@ -405,7 +405,7 @@ esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info)
 esp_err_t touch_pad_filter_enable(void)
 {
     TOUCH_ENTER_CRITICAL();
-    touch_hal_filter_enable();
+    touch_hal_filter_enable(true);
     TOUCH_EXIT_CRITICAL();
     return ESP_OK;
 }
@@ -413,7 +413,7 @@ esp_err_t touch_pad_filter_enable(void)
 esp_err_t touch_pad_filter_disable(void)
 {
     TOUCH_ENTER_CRITICAL();
-    touch_hal_filter_disable();
+    touch_hal_filter_enable(false);
     TOUCH_EXIT_CRITICAL();
     return ESP_OK;
 }
@@ -596,9 +596,9 @@ esp_err_t touch_pad_sleep_channel_enable_proximity(touch_pad_t pad_num, bool ena
 
     TOUCH_ENTER_CRITICAL();
     if (enable) {
-        touch_hal_sleep_enable_approach();
+        touch_hal_sleep_enable_approach(true);
     } else {
-        touch_hal_sleep_disable_approach();
+        touch_hal_sleep_enable_approach(false);
     }
     TOUCH_EXIT_CRITICAL();
     return ESP_OK;
@@ -684,3 +684,17 @@ esp_err_t touch_pad_sleep_channel_set_work_time(uint16_t sleep_cycle, uint16_t m
     touch_hal_sleep_channel_set_work_time(sleep_cycle, meas_times);
     return ESP_OK;
 }
+
+/**
+ * @brief This function will be called during start up, to check that the new touch driver is not running along with the legacy touch driver
+ */
+static __attribute__((constructor)) void check_touch_driver_conflict(void)
+{
+    extern __attribute__((weak)) esp_err_t touch_sensor_new_controller(const void*, void *);
+    /* If the new Touch driver is linked, the weak function will point to the actual function in the new driver, otherwise it is NULL*/
+    if ((void *)touch_sensor_new_controller != NULL) {
+        ESP_EARLY_LOGE("legacy_touch_driver", "CONFLICT! The new touch driver can't work along with the legacy touch driver");
+        abort();
+    }
+    ESP_EARLY_LOGW("legacy_touch_driver", "legacy touch driver is deprecated, please migrate to use driver/touch_sens.h");
+}
diff --git a/components/driver/touch_sensor/esp32s3/include/driver/touch_sensor.h b/components/driver/touch_sensor/esp32s3/include/driver/touch_sensor.h
index 06f835879f0..adb40726ae3 100644
--- a/components/driver/touch_sensor/esp32s3/include/driver/touch_sensor.h
+++ b/components/driver/touch_sensor/esp32s3/include/driver/touch_sensor.h
@@ -1,646 +1,17 @@
 /*
- * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
-#include "driver/touch_sensor_common.h"
+#include "sdkconfig.h"
+#include "driver/touch_sensor_legacy.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Set touch sensor FSM start
- * @note  Start FSM after the touch sensor FSM mode is set.
- * @note  Call this function will reset benchmark of all touch channels.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_fsm_start(void);
-
-/**
- * @brief Stop touch sensor FSM.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_fsm_stop(void);
-
-/**
- * @brief Trigger a touch sensor measurement, only support in SW mode of FSM
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_sw_start(void);
-
-/**
- * @brief Set charge and discharge times of each measurement
- * @note  This function will specify the charge and discharge times in each measurement period
- *        The clock is sourced from SOC_MOD_CLK_RTC_FAST, and its default frequency is SOC_CLK_RC_FAST_FREQ_APPROX
- *        The touch sensor will record the total clock cycles of all the charge and discharge cycles as the final result (raw value)
- * @note  If the charge and discharge times is too small, it may lead to inaccurate results.
- *
- * @param charge_discharge_times    Charge and discharge times, range: 0 ~ 0xffff.
- *                                  No exact typical value can be recommended because the capacity is influenced by the hardware design and how finger touches,
- *                                  but suggest adjusting this value to make the measurement time around 1 ms.
- * @return
- *      - ESP_OK    Set charge and discharge times success
- */
-esp_err_t touch_pad_set_charge_discharge_times(uint16_t charge_discharge_times);
-
-/**
- * @brief Get charge and discharge times of each measurement
- *
- * @param charge_discharge_times    Charge and discharge times
- * @return
- *      - ESP_OK    Get charge_discharge_times success
- *      - ESP_ERR_INVALID_ARG   The input parameter is NULL
- */
-esp_err_t touch_pad_get_charge_discharge_times(uint16_t *charge_discharge_times);
-
-/**
- * @brief Set the interval between two measurements
- * @note  The touch sensor will sleep between two measurements
- *        This function is to set the interval cycle
- *        And the interval is clocked from SOC_MOD_CLK_RTC_SLOW, its default frequency is SOC_CLK_RC_SLOW_FREQ_APPROX
- *
- * @param interval_cycle    The interval between two measurements
- *                          sleep_time = interval_cycle / SOC_CLK_RC_SLOW_FREQ_APPROX.
- *                          The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
- * @return
- *      - ESP_OK    Set interval cycle success
- */
-esp_err_t touch_pad_set_measurement_interval(uint16_t interval_cycle);
-
-/**
- * @brief Get the interval between two measurements
- *
- * @param interval_cycle    The interval between two measurements
- * @return
- *      - ESP_OK    Get interval cycle success
- *      - ESP_ERR_INVALID_ARG   The input parameter is NULL
- */
-esp_err_t touch_pad_get_measurement_interval(uint16_t *interval_cycle);
-
-/**
- * @brief Set touch sensor times of charge and discharge and sleep time.
- *        Excessive total time will slow down the touch response.
- *        Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
- * @note  The touch sensor will measure time of a fixed number of charge/discharge cycles (specified as the second parameter).
- *        That means the time (raw value) will increase as the capacity of the touch pad is increasing.
- *        The time (raw value) here is the number of clock cycles which is sourced from SOC_MOD_CLK_RTC_FAST and at (SOC_CLK_RC_FAST_FREQ_APPROX) Hz as default
- * @note The greater the duty cycle of the measurement time, the more system power is consumed.
- *
- * @param sleep_cycle The touch sensor will sleep after each measurement.
- *                    sleep_cycle decide the interval between each measurement.
- *                    t_sleep = sleep_cycle / SOC_CLK_RC_SLOW_FREQ_APPROX.
- *                    The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
- * @param meas_times The times of charge and discharge in each measurement of touch channels.  Range: 0 ~ 0xffff.
- *                   Recommended typical value: Modify this value to make the measurement time around 1 ms.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_times)
-__attribute__((deprecated("please use 'touch_pad_set_charge_discharge_times' and 'touch_pad_set_measurement_interval' instead")));
-
-/**
- * @brief Get touch sensor times of charge and discharge and sleep time
- * @param sleep_cycle  Pointer to accept sleep cycle number
- * @param meas_times Pointer to accept measurement times count.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_times)
-__attribute__((deprecated("please use 'touch_pad_get_charge_discharge_times' and 'touch_pad_get_measurement_interval' instead")));
-
-/**
- * @brief Set the connection type of touch channels in idle status.
- *        When a channel is in measurement mode, other initialized channels are in idle mode.
- *        The touch channel is generally adjacent to the trace, so the connection state of the idle channel
- *        affects the stability and sensitivity of the test channel.
- *        The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels.
- *        The `CONN_GND`(grounding) setting increases the stability of touch channels.
- * @param type  Select idle channel connect to high resistance state or ground.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_idle_channel_connect(touch_pad_conn_type_t type);
-
-/**
- * @brief Get the connection type of touch channels in idle status.
- *        When a channel is in measurement mode, other initialized channels are in idle mode.
- *        The touch channel is generally adjacent to the trace, so the connection state of the idle channel
- *        affects the stability and sensitivity of the test channel.
- *        The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels.
- *        The `CONN_GND`(grounding) setting increases the stability of touch channels.
- * @param type  Pointer to connection type.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_idle_channel_connect(touch_pad_conn_type_t *type);
-
-/**
- * @brief Set the trigger threshold of touch sensor.
- *        The threshold determines the sensitivity of the touch sensor.
- *        The threshold is the original value of the trigger state minus the benchmark value.
- * @note  If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered.
- * @param touch_num touch pad index
- * @param threshold threshold of touch sensor. Should be less than the max change value of touch.
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold);
-
-/**
- * @brief Get touch sensor trigger threshold
- * @param touch_num touch pad index
- * @param threshold pointer to accept threshold
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_INVALID_ARG if argument is wrong
- */
-esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold);
-
-/**
- * @brief Register touch channel into touch sensor scan group.
- *        The working mode of the touch sensor is cyclically scanned.
- *        This function will set the scan bits according to the given bitmask.
- * @note  If set this mask, the FSM timer should be stop firsty.
- * @note  The touch sensor that in scan map, should be deinit GPIO function firstly by `touch_pad_io_init`.
- * @param enable_mask bitmask of touch sensor scan group.
- *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_set_channel_mask(uint16_t enable_mask);
-
-/**
- * @brief Get the touch sensor scan group bit mask.
- * @param enable_mask Pointer to bitmask of touch sensor scan group.
- *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_get_channel_mask(uint16_t *enable_mask);
-
-/**
- * @brief Clear touch channel from touch sensor scan group.
- *        The working mode of the touch sensor is cyclically scanned.
- *        This function will clear the scan bits according to the given bitmask.
- * @note  If clear all mask, the FSM timer should be stop firsty.
- * @param enable_mask bitmask of touch sensor scan group.
- *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_clear_channel_mask(uint16_t enable_mask);
-
-/**
- * @brief Configure parameter for each touch channel.
- * @note  Touch num 0 is denoise channel, please use `touch_pad_denoise_enable` to set denoise function
- * @param touch_num touch pad index
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG if argument wrong
- *     - ESP_FAIL if touch pad not initialized
- */
-esp_err_t touch_pad_config(touch_pad_t touch_num);
-
-/**
- * @brief Reset the FSM of touch module.
- * @note  Call this function after `touch_pad_fsm_stop`.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_reset(void);
-
-/**
- * @brief Get the current measure channel.
- * @note  Should be called when touch sensor measurement is in cyclic scan mode.
- * @return
- *      - touch channel number
- */
-touch_pad_t touch_pad_get_current_meas_channel(void);
-
-/**
- * @brief Get the touch sensor interrupt status mask.
- * @return
- *      - touch interrupt bit
- */
-uint32_t touch_pad_read_intr_status_mask(void);
-
-/**
- * @brief Enable touch sensor interrupt by bitmask.
- * @note  This API can be called in ISR handler.
- * @param int_mask Pad mask to enable interrupts
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_intr_enable(touch_pad_intr_mask_t int_mask);
-
-/**
- * @brief Disable touch sensor interrupt by bitmask.
- * @note  This API can be called in ISR handler.
- * @param int_mask Pad mask to disable interrupts
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_intr_disable(touch_pad_intr_mask_t int_mask);
-
-/**
- * @brief Clear touch sensor interrupt by bitmask.
- * @param int_mask Pad mask to clear interrupts
- * @return
- *      - ESP_OK on success
- */
-esp_err_t touch_pad_intr_clear(touch_pad_intr_mask_t int_mask);
-
-/**
- * @brief   Register touch-pad ISR.
- *          The handler will be attached to the same CPU core that this function is running on.
- * @param fn  Pointer to ISR handler
- * @param arg  Parameter for ISR
- * @param intr_mask Enable touch sensor interrupt handler by bitmask.
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Arguments error
- *     - ESP_ERR_NO_MEM No memory
- */
-esp_err_t touch_pad_isr_register(intr_handler_t fn, void *arg, touch_pad_intr_mask_t intr_mask);
-
-/**
- * @brief Enable/disable the timeout check and set timeout threshold for all touch sensor channels measurements.
- *        If enable: When the touch reading of a touch channel exceeds the measurement threshold, a timeout interrupt will be generated.
- *        If disable: the FSM does not check if the channel under measurement times out.
- *
- * @note The threshold compared with touch readings.
- * @note In order to avoid abnormal short circuit of some touch channels. This function should be turned on.
- *       Ensure the normal operation of other touch channels.
- *
- * @param enable true(default): Enable the timeout check; false: Disable the timeout check.
- * @param threshold For all channels, the maximum value that will not be exceeded during normal operation.
- *
-* @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_timeout_set(bool enable, uint32_t threshold);
-
-/**
- * @brief Call this interface after timeout to make the touch channel resume normal work. Point on the next channel to measure.
- *        If this API is not called, the touch FSM will stop the measurement after timeout interrupt.
- *
- * @note  Call this API after finishes the exception handling by user.
- *
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_timeout_resume(void);
-
-/**
- * @brief get raw data of touch sensor.
- * @note After the initialization is complete, the "raw_data" is max value. You need to wait for a measurement
- *       cycle before you can read the correct touch value.
- * @param touch_num touch pad index
- * @param raw_data pointer to accept touch sensor value
- * @return
- *     - ESP_OK Success
- *     - ESP_FAIL Touch channel 0 haven't this parameter.
- */
-
-esp_err_t touch_pad_read_raw_data(touch_pad_t touch_num, uint32_t *raw_data);
-
-/**
- * @brief get benchmark of touch sensor.
- * @note After initialization, the benchmark value is the maximum during the first measurement period.
- * @param touch_num touch pad index
- * @param benchmark pointer to accept touch sensor benchmark value
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Touch channel 0 haven't this parameter.
- */
-esp_err_t touch_pad_read_benchmark(touch_pad_t touch_num, uint32_t *benchmark);
-
-/**
- * @brief Get smoothed data that obtained by filtering the raw data.
- *
- * @param touch_num touch pad index
- * @param smooth pointer to smoothed data
- */
-esp_err_t touch_pad_filter_read_smooth(touch_pad_t touch_num, uint32_t *smooth);
-
-/**
- * @brief Force reset benchmark to raw data of touch sensor.
- * @param touch_num touch pad index
- *                  - TOUCH_PAD_MAX Reset basaline of all channels
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_reset_benchmark(touch_pad_t touch_num);
-
-/**
- * @brief set parameter of touch sensor filter and detection algorithm.
- *        For more details on the detection algorithm, please refer to the application documentation.
- * @param filter_info select filter type and threshold of detection algorithm
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_filter_set_config(const touch_filter_config_t *filter_info);
-
-/**
- * @brief get parameter of touch sensor filter and detection algorithm.
- *        For more details on the detection algorithm, please refer to the application documentation.
- * @param filter_info select filter type and threshold of detection algorithm
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info);
-
-/**
- * @brief enable touch sensor filter for detection algorithm.
- *        For more details on the detection algorithm, please refer to the application documentation.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_filter_enable(void);
-
-/**
- * @brief disable touch sensor filter for detection algorithm.
- *        For more details on the detection algorithm, please refer to the application documentation.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_filter_disable(void);
-
-/**
- * @brief set parameter of denoise pad (TOUCH_PAD_NUM0).
- *        T0 is an internal channel that does not have a corresponding external GPIO.
- *        T0 will work simultaneously with the measured channel Tn. Finally, the actual
- *        measured value of Tn is the value after subtracting lower bits of T0.
- *        The noise reduction function filters out interference introduced simultaneously on all channels,
- *        such as noise introduced by power supplies and external EMI.
- * @param denoise parameter of denoise
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_set_config(const touch_pad_denoise_t *denoise);
-
-/**
- * @brief get parameter of denoise pad (TOUCH_PAD_NUM0).
- * @param denoise Pointer to parameter of denoise
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise);
-
-/**
- * @brief enable denoise function.
- *        T0 is an internal channel that does not have a corresponding external GPIO.
- *        T0 will work simultaneously with the measured channel Tn. Finally, the actual
- *        measured value of Tn is the value after subtracting lower bits of T0.
- *        The noise reduction function filters out interference introduced simultaneously on all channels,
- *        such as noise introduced by power supplies and external EMI.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_enable(void);
-
-/**
- * @brief disable denoise function.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_disable(void);
-
-/**
- * @brief Get denoise measure value (TOUCH_PAD_NUM0).
- * @param data Pointer to receive denoise value
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_denoise_read_data(uint32_t *data);
-
-/**
- * @brief set parameter of waterproof function.
- *
- *        The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel.
- *        Guard pad is used to detect the large area of water covering the touch panel.
- *        Shield pad is used to shield the influence of water droplets covering the touch panel.
- *        It is generally designed as a grid and is placed around the touch buttons.
- *
- * @param waterproof parameter of waterproof
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_waterproof_set_config(const touch_pad_waterproof_t *waterproof);
-
-/**
- * @brief get parameter of waterproof function.
- * @param waterproof parameter of waterproof
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof);
-
-/**
- * @brief Enable parameter of waterproof function.
- *        Should be called after function ``touch_pad_waterproof_set_config``.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_waterproof_enable(void);
-
-/**
- * @brief Disable parameter of waterproof function.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_waterproof_disable(void);
-
-/**
- * @brief Enable/disable proximity function of touch channels.
- *        The proximity sensor measurement is the accumulation of touch channel measurements.
- *
- * @note Supports up to three touch channels configured as proximity sensors.
- * @param touch_num touch pad index
- * @param enabled true: enable the proximity function; false:  disable the proximity function
- * @return
- *     - ESP_OK: Configured correctly.
- *     - ESP_ERR_INVALID_ARG: Touch channel number error.
- *     - ESP_ERR_NOT_SUPPORTED: Don't support configured.
- */
-esp_err_t touch_pad_proximity_enable(touch_pad_t touch_num, bool enabled);
-
-/**
- * @brief Set measure count of proximity channel.
- *        The proximity sensor measurement is the accumulation of touch channel measurements.
- *
- * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`.
- * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`.
- * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255.
- * @return
- *     - ESP_OK: Configured correctly.
- *     - ESP_ERR_INVALID_ARG: Touch channel number error.
- */
-esp_err_t touch_pad_proximity_set_count(touch_pad_t touch_num, uint32_t count);
-
-/**
- * @brief Get measure count of proximity channel.
- *        The proximity sensor measurement is the accumulation of touch channel measurements.
- *
- * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`.
- * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`.
- * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255.
- * @return
- *     - ESP_OK: Configured correctly.
- *     - ESP_ERR_INVALID_ARG: Touch channel number error.
- */
-esp_err_t touch_pad_proximity_get_count(touch_pad_t touch_num, uint32_t *count);
-
-/**
- * @brief Get the accumulated measurement of the proximity sensor.
- *        The proximity sensor measurement is the accumulation of touch channel measurements.
- * @param touch_num touch pad index
- * @param measure_out If the accumulation process does not end, the `measure_out` is the process value.
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG Touch num is not proximity
- */
-esp_err_t touch_pad_proximity_get_data(touch_pad_t touch_num, uint32_t *measure_out);
-
-/**
- * @brief Get parameter of touch sensor sleep channel.
- *        The touch sensor can works in sleep mode to wake up sleep.
- *
- * @note  After the sleep channel is configured, Please use special functions for sleep channel.
- *        e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading.
- *
- * @param slp_config touch sleep pad config.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_get_info(touch_pad_sleep_channel_t *slp_config);
-
-/**
- * @brief Enable/Disable sleep channel function for touch sensor.
- *        The touch sensor can works in sleep mode to wake up sleep.
- *
- * @note  ESP32S2 only support one sleep channel.
- * @note  After the sleep channel is configured, Please use special functions for sleep channel.
- *        e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading.
- *
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param enable true: enable sleep pad for touch sensor; false: disable sleep pad for touch sensor;
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_enable(touch_pad_t pad_num, bool enable);
-
-/**
- * @brief Enable/Disable proximity function for sleep channel.
- *        The touch sensor can works in sleep mode to wake up sleep.
- *
- * @note  ESP32S2 only support one sleep channel.
- *
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param enable true: enable proximity for sleep channel; false: disable proximity for sleep channel;
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_enable_proximity(touch_pad_t pad_num, bool enable);
-
-/**
- * @brief Set the trigger threshold of touch sensor in deep sleep.
- *        The threshold determines the sensitivity of the touch sensor.
- *
- * @note  In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
- *
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param touch_thres touch sleep pad threshold
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_set_threshold(touch_pad_t pad_num, uint32_t touch_thres);
-
-/**
- * @brief Get the trigger threshold of touch sensor in deep sleep.
- *        The threshold determines the sensitivity of the touch sensor.
- *
- * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
- *
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param touch_thres touch sleep pad threshold
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_get_threshold(touch_pad_t pad_num, uint32_t *touch_thres);
-
-/**
- * @brief Read benchmark of touch sensor sleep channel.
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param benchmark pointer to accept touch sensor benchmark value
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG parameter is NULL
- */
-esp_err_t touch_pad_sleep_channel_read_benchmark(touch_pad_t pad_num, uint32_t *benchmark);
-
-/**
- * @brief Read smoothed data of touch sensor sleep channel.
- *        Smoothed data is filtered from the raw data.
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param smooth_data pointer to accept touch sensor smoothed data
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG parameter is NULL
- */
-esp_err_t touch_pad_sleep_channel_read_smooth(touch_pad_t pad_num, uint32_t *smooth_data);
-
-/**
- * @brief Read raw data of touch sensor sleep channel.
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param raw_data pointer to accept touch sensor raw data
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG parameter is NULL
- */
-esp_err_t touch_pad_sleep_channel_read_data(touch_pad_t pad_num, uint32_t *raw_data);
-
-/**
- * @brief Reset benchmark of touch sensor sleep channel.
- *
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_reset_benchmark(void);
-
-/**
- * @brief Read proximity count of touch sensor sleep channel.
- * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
- * @param proximity_cnt pointer to accept touch sensor proximity count value
- * @return
- *     - ESP_OK Success
- *     - ESP_ERR_INVALID_ARG parameter is NULL
- */
-esp_err_t touch_pad_sleep_channel_read_proximity_cnt(touch_pad_t pad_num, uint32_t *proximity_cnt);
-
-/**
- * @brief Change the operating frequency of touch pad in deep sleep state. Reducing the operating frequency can effectively reduce power consumption.
- *        If this function is not called, the working frequency of touch in the deep sleep state is the same as that in the wake-up state.
- *
- * @param sleep_cycle The touch sensor will sleep after each measurement.
- *                    sleep_cycle decide the interval between each measurement.
- *                    t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency).
- *                    The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
- * @param meas_times The times of charge and discharge in each measure process of touch channels.
- *                  The timer frequency is 8Mhz. Range: 0 ~ 0xffff.
- *                  Recommended typical value: Modify this value to make the measurement time around 1ms.
- * @return
- *     - ESP_OK Success
- */
-esp_err_t touch_pad_sleep_channel_set_work_time(uint16_t sleep_cycle, uint16_t meas_times);
-
-#ifdef __cplusplus
-}
+#if !CONFIG_TOUCH_SUPPRESS_DEPRECATE_WARN
+#warning "This set of Touch APIs has been deprecated, \
+please include 'driver/touch_sens.h' instead. \
+if you want to keep using the old APIs and ignore this warning, \
+you can enable 'Suppress legacy driver deprecated warning' option under 'Touch Configuration' menu in Kconfig"
 #endif
diff --git a/components/driver/touch_sensor/esp32s3/include/driver/touch_sensor_legacy.h b/components/driver/touch_sensor/esp32s3/include/driver/touch_sensor_legacy.h
new file mode 100644
index 00000000000..96ce7130674
--- /dev/null
+++ b/components/driver/touch_sensor/esp32s3/include/driver/touch_sensor_legacy.h
@@ -0,0 +1,646 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "driver/touch_sensor_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set touch sensor FSM start
+ * @note  Start FSM after the touch sensor FSM mode is set.
+ * @note  Call this function will reset benchmark of all touch channels.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_fsm_start(void);
+
+/**
+ * @brief Stop touch sensor FSM.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_fsm_stop(void);
+
+/**
+ * @brief Trigger a touch sensor measurement, only support in SW mode of FSM
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_sw_start(void);
+
+/**
+ * @brief Set charge and discharge times of each measurement
+ * @note  This function will specify the charge and discharge times in each measurement period
+ *        The clock is sourced from SOC_MOD_CLK_RTC_FAST, and its default frequency is SOC_CLK_RC_FAST_FREQ_APPROX
+ *        The touch sensor will record the total clock cycles of all the charge and discharge cycles as the final result (raw value)
+ * @note  If the charge and discharge times is too small, it may lead to inaccurate results.
+ *
+ * @param charge_discharge_times    Charge and discharge times, range: 0 ~ 0xffff.
+ *                                  No exact typical value can be recommended because the capacity is influenced by the hardware design and how finger touches,
+ *                                  but suggest adjusting this value to make the measurement time around 1 ms.
+ * @return
+ *      - ESP_OK    Set charge and discharge times success
+ */
+esp_err_t touch_pad_set_charge_discharge_times(uint16_t charge_discharge_times);
+
+/**
+ * @brief Get charge and discharge times of each measurement
+ *
+ * @param charge_discharge_times    Charge and discharge times
+ * @return
+ *      - ESP_OK    Get charge_discharge_times success
+ *      - ESP_ERR_INVALID_ARG   The input parameter is NULL
+ */
+esp_err_t touch_pad_get_charge_discharge_times(uint16_t *charge_discharge_times);
+
+/**
+ * @brief Set the interval between two measurements
+ * @note  The touch sensor will sleep between two measurements
+ *        This function is to set the interval cycle
+ *        And the interval is clocked from SOC_MOD_CLK_RTC_SLOW, its default frequency is SOC_CLK_RC_SLOW_FREQ_APPROX
+ *
+ * @param interval_cycle    The interval between two measurements
+ *                          sleep_time = interval_cycle / SOC_CLK_RC_SLOW_FREQ_APPROX.
+ *                          The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ * @return
+ *      - ESP_OK    Set interval cycle success
+ */
+esp_err_t touch_pad_set_measurement_interval(uint16_t interval_cycle);
+
+/**
+ * @brief Get the interval between two measurements
+ *
+ * @param interval_cycle    The interval between two measurements
+ * @return
+ *      - ESP_OK    Get interval cycle success
+ *      - ESP_ERR_INVALID_ARG   The input parameter is NULL
+ */
+esp_err_t touch_pad_get_measurement_interval(uint16_t *interval_cycle);
+
+/**
+ * @brief Set touch sensor times of charge and discharge and sleep time.
+ *        Excessive total time will slow down the touch response.
+ *        Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
+ * @note  The touch sensor will measure time of a fixed number of charge/discharge cycles (specified as the second parameter).
+ *        That means the time (raw value) will increase as the capacity of the touch pad is increasing.
+ *        The time (raw value) here is the number of clock cycles which is sourced from SOC_MOD_CLK_RTC_FAST and at (SOC_CLK_RC_FAST_FREQ_APPROX) Hz as default
+ * @note The greater the duty cycle of the measurement time, the more system power is consumed.
+ *
+ * @param sleep_cycle The touch sensor will sleep after each measurement.
+ *                    sleep_cycle decide the interval between each measurement.
+ *                    t_sleep = sleep_cycle / SOC_CLK_RC_SLOW_FREQ_APPROX.
+ *                    The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ * @param meas_times The times of charge and discharge in each measurement of touch channels.  Range: 0 ~ 0xffff.
+ *                   Recommended typical value: Modify this value to make the measurement time around 1 ms.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_times)
+__attribute__((deprecated("please use 'touch_pad_set_charge_discharge_times' and 'touch_pad_set_measurement_interval' instead")));
+
+/**
+ * @brief Get touch sensor times of charge and discharge and sleep time
+ * @param sleep_cycle  Pointer to accept sleep cycle number
+ * @param meas_times Pointer to accept measurement times count.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_times)
+__attribute__((deprecated("please use 'touch_pad_get_charge_discharge_times' and 'touch_pad_get_measurement_interval' instead")));
+
+/**
+ * @brief Set the connection type of touch channels in idle status.
+ *        When a channel is in measurement mode, other initialized channels are in idle mode.
+ *        The touch channel is generally adjacent to the trace, so the connection state of the idle channel
+ *        affects the stability and sensitivity of the test channel.
+ *        The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels.
+ *        The `CONN_GND`(grounding) setting increases the stability of touch channels.
+ * @param type  Select idle channel connect to high resistance state or ground.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_idle_channel_connect(touch_pad_conn_type_t type);
+
+/**
+ * @brief Get the connection type of touch channels in idle status.
+ *        When a channel is in measurement mode, other initialized channels are in idle mode.
+ *        The touch channel is generally adjacent to the trace, so the connection state of the idle channel
+ *        affects the stability and sensitivity of the test channel.
+ *        The `CONN_HIGHZ`(high resistance) setting increases the sensitivity of touch channels.
+ *        The `CONN_GND`(grounding) setting increases the stability of touch channels.
+ * @param type  Pointer to connection type.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_idle_channel_connect(touch_pad_conn_type_t *type);
+
+/**
+ * @brief Set the trigger threshold of touch sensor.
+ *        The threshold determines the sensitivity of the touch sensor.
+ *        The threshold is the original value of the trigger state minus the benchmark value.
+ * @note  If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered.
+ * @param touch_num touch pad index
+ * @param threshold threshold of touch sensor. Should be less than the max change value of touch.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold);
+
+/**
+ * @brief Get touch sensor trigger threshold
+ * @param touch_num touch pad index
+ * @param threshold pointer to accept threshold
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold);
+
+/**
+ * @brief Register touch channel into touch sensor scan group.
+ *        The working mode of the touch sensor is cyclically scanned.
+ *        This function will set the scan bits according to the given bitmask.
+ * @note  If set this mask, the FSM timer should be stop firsty.
+ * @note  The touch sensor that in scan map, should be deinit GPIO function firstly by `touch_pad_io_init`.
+ * @param enable_mask bitmask of touch sensor scan group.
+ *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_channel_mask(uint16_t enable_mask);
+
+/**
+ * @brief Get the touch sensor scan group bit mask.
+ * @param enable_mask Pointer to bitmask of touch sensor scan group.
+ *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_channel_mask(uint16_t *enable_mask);
+
+/**
+ * @brief Clear touch channel from touch sensor scan group.
+ *        The working mode of the touch sensor is cyclically scanned.
+ *        This function will clear the scan bits according to the given bitmask.
+ * @note  If clear all mask, the FSM timer should be stop firsty.
+ * @param enable_mask bitmask of touch sensor scan group.
+ *        e.g. TOUCH_PAD_NUM14 -> BIT(14)
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_clear_channel_mask(uint16_t enable_mask);
+
+/**
+ * @brief Configure parameter for each touch channel.
+ * @note  Touch num 0 is denoise channel, please use `touch_pad_denoise_enable` to set denoise function
+ * @param touch_num touch pad index
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG if argument wrong
+ *     - ESP_FAIL if touch pad not initialized
+ */
+esp_err_t touch_pad_config(touch_pad_t touch_num);
+
+/**
+ * @brief Reset the FSM of touch module.
+ * @note  Call this function after `touch_pad_fsm_stop`.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_reset(void);
+
+/**
+ * @brief Get the current measure channel.
+ * @note  Should be called when touch sensor measurement is in cyclic scan mode.
+ * @return
+ *      - touch channel number
+ */
+touch_pad_t touch_pad_get_current_meas_channel(void);
+
+/**
+ * @brief Get the touch sensor interrupt status mask.
+ * @return
+ *      - touch interrupt bit
+ */
+uint32_t touch_pad_read_intr_status_mask(void);
+
+/**
+ * @brief Enable touch sensor interrupt by bitmask.
+ * @note  This API can be called in ISR handler.
+ * @param int_mask Pad mask to enable interrupts
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_intr_enable(touch_pad_intr_mask_t int_mask);
+
+/**
+ * @brief Disable touch sensor interrupt by bitmask.
+ * @note  This API can be called in ISR handler.
+ * @param int_mask Pad mask to disable interrupts
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_intr_disable(touch_pad_intr_mask_t int_mask);
+
+/**
+ * @brief Clear touch sensor interrupt by bitmask.
+ * @param int_mask Pad mask to clear interrupts
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_intr_clear(touch_pad_intr_mask_t int_mask);
+
+/**
+ * @brief   Register touch-pad ISR.
+ *          The handler will be attached to the same CPU core that this function is running on.
+ * @param fn  Pointer to ISR handler
+ * @param arg  Parameter for ISR
+ * @param intr_mask Enable touch sensor interrupt handler by bitmask.
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Arguments error
+ *     - ESP_ERR_NO_MEM No memory
+ */
+esp_err_t touch_pad_isr_register(intr_handler_t fn, void *arg, touch_pad_intr_mask_t intr_mask);
+
+/**
+ * @brief Enable/disable the timeout check and set timeout threshold for all touch sensor channels measurements.
+ *        If enable: When the touch reading of a touch channel exceeds the measurement threshold, a timeout interrupt will be generated.
+ *        If disable: the FSM does not check if the channel under measurement times out.
+ *
+ * @note The threshold compared with touch readings.
+ * @note In order to avoid abnormal short circuit of some touch channels. This function should be turned on.
+ *       Ensure the normal operation of other touch channels.
+ *
+ * @param enable true(default): Enable the timeout check; false: Disable the timeout check.
+ * @param threshold For all channels, the maximum value that will not be exceeded during normal operation.
+ *
+* @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_timeout_set(bool enable, uint32_t threshold);
+
+/**
+ * @brief Call this interface after timeout to make the touch channel resume normal work. Point on the next channel to measure.
+ *        If this API is not called, the touch FSM will stop the measurement after timeout interrupt.
+ *
+ * @note  Call this API after finishes the exception handling by user.
+ *
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_timeout_resume(void);
+
+/**
+ * @brief get raw data of touch sensor.
+ * @note After the initialization is complete, the "raw_data" is max value. You need to wait for a measurement
+ *       cycle before you can read the correct touch value.
+ * @param touch_num touch pad index
+ * @param raw_data pointer to accept touch sensor value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_FAIL Touch channel 0 haven't this parameter.
+ */
+
+esp_err_t touch_pad_read_raw_data(touch_pad_t touch_num, uint32_t *raw_data);
+
+/**
+ * @brief get benchmark of touch sensor.
+ * @note After initialization, the benchmark value is the maximum during the first measurement period.
+ * @param touch_num touch pad index
+ * @param benchmark pointer to accept touch sensor benchmark value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Touch channel 0 haven't this parameter.
+ */
+esp_err_t touch_pad_read_benchmark(touch_pad_t touch_num, uint32_t *benchmark);
+
+/**
+ * @brief Get smoothed data that obtained by filtering the raw data.
+ *
+ * @param touch_num touch pad index
+ * @param smooth pointer to smoothed data
+ */
+esp_err_t touch_pad_filter_read_smooth(touch_pad_t touch_num, uint32_t *smooth);
+
+/**
+ * @brief Force reset benchmark to raw data of touch sensor.
+ * @param touch_num touch pad index
+ *                  - TOUCH_PAD_MAX Reset basaline of all channels
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_reset_benchmark(touch_pad_t touch_num);
+
+/**
+ * @brief set parameter of touch sensor filter and detection algorithm.
+ *        For more details on the detection algorithm, please refer to the application documentation.
+ * @param filter_info select filter type and threshold of detection algorithm
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_filter_set_config(const touch_filter_config_t *filter_info);
+
+/**
+ * @brief get parameter of touch sensor filter and detection algorithm.
+ *        For more details on the detection algorithm, please refer to the application documentation.
+ * @param filter_info select filter type and threshold of detection algorithm
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info);
+
+/**
+ * @brief enable touch sensor filter for detection algorithm.
+ *        For more details on the detection algorithm, please refer to the application documentation.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_filter_enable(void);
+
+/**
+ * @brief disable touch sensor filter for detection algorithm.
+ *        For more details on the detection algorithm, please refer to the application documentation.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_filter_disable(void);
+
+/**
+ * @brief set parameter of denoise pad (TOUCH_PAD_NUM0).
+ *        T0 is an internal channel that does not have a corresponding external GPIO.
+ *        T0 will work simultaneously with the measured channel Tn. Finally, the actual
+ *        measured value of Tn is the value after subtracting lower bits of T0.
+ *        The noise reduction function filters out interference introduced simultaneously on all channels,
+ *        such as noise introduced by power supplies and external EMI.
+ * @param denoise parameter of denoise
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_set_config(const touch_pad_denoise_t *denoise);
+
+/**
+ * @brief get parameter of denoise pad (TOUCH_PAD_NUM0).
+ * @param denoise Pointer to parameter of denoise
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_get_config(touch_pad_denoise_t *denoise);
+
+/**
+ * @brief enable denoise function.
+ *        T0 is an internal channel that does not have a corresponding external GPIO.
+ *        T0 will work simultaneously with the measured channel Tn. Finally, the actual
+ *        measured value of Tn is the value after subtracting lower bits of T0.
+ *        The noise reduction function filters out interference introduced simultaneously on all channels,
+ *        such as noise introduced by power supplies and external EMI.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_enable(void);
+
+/**
+ * @brief disable denoise function.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_disable(void);
+
+/**
+ * @brief Get denoise measure value (TOUCH_PAD_NUM0).
+ * @param data Pointer to receive denoise value
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_denoise_read_data(uint32_t *data);
+
+/**
+ * @brief set parameter of waterproof function.
+ *
+ *        The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel.
+ *        Guard pad is used to detect the large area of water covering the touch panel.
+ *        Shield pad is used to shield the influence of water droplets covering the touch panel.
+ *        It is generally designed as a grid and is placed around the touch buttons.
+ *
+ * @param waterproof parameter of waterproof
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_waterproof_set_config(const touch_pad_waterproof_t *waterproof);
+
+/**
+ * @brief get parameter of waterproof function.
+ * @param waterproof parameter of waterproof
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof);
+
+/**
+ * @brief Enable parameter of waterproof function.
+ *        Should be called after function ``touch_pad_waterproof_set_config``.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_waterproof_enable(void);
+
+/**
+ * @brief Disable parameter of waterproof function.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_waterproof_disable(void);
+
+/**
+ * @brief Enable/disable proximity function of touch channels.
+ *        The proximity sensor measurement is the accumulation of touch channel measurements.
+ *
+ * @note Supports up to three touch channels configured as proximity sensors.
+ * @param touch_num touch pad index
+ * @param enabled true: enable the proximity function; false:  disable the proximity function
+ * @return
+ *     - ESP_OK: Configured correctly.
+ *     - ESP_ERR_INVALID_ARG: Touch channel number error.
+ *     - ESP_ERR_NOT_SUPPORTED: Don't support configured.
+ */
+esp_err_t touch_pad_proximity_enable(touch_pad_t touch_num, bool enabled);
+
+/**
+ * @brief Set measure count of proximity channel.
+ *        The proximity sensor measurement is the accumulation of touch channel measurements.
+ *
+ * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`.
+ * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`.
+ * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255.
+ * @return
+ *     - ESP_OK: Configured correctly.
+ *     - ESP_ERR_INVALID_ARG: Touch channel number error.
+ */
+esp_err_t touch_pad_proximity_set_count(touch_pad_t touch_num, uint32_t count);
+
+/**
+ * @brief Get measure count of proximity channel.
+ *        The proximity sensor measurement is the accumulation of touch channel measurements.
+ *
+ * @note All proximity channels use the same `count` value. So please pass the parameter `TOUCH_PAD_MAX`.
+ * @param touch_num Touch pad index. In this version, pass the parameter `TOUCH_PAD_MAX`.
+ * @param count The cumulative times of measurements for proximity pad. Range: 0 ~ 255.
+ * @return
+ *     - ESP_OK: Configured correctly.
+ *     - ESP_ERR_INVALID_ARG: Touch channel number error.
+ */
+esp_err_t touch_pad_proximity_get_count(touch_pad_t touch_num, uint32_t *count);
+
+/**
+ * @brief Get the accumulated measurement of the proximity sensor.
+ *        The proximity sensor measurement is the accumulation of touch channel measurements.
+ * @param touch_num touch pad index
+ * @param measure_out If the accumulation process does not end, the `measure_out` is the process value.
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Touch num is not proximity
+ */
+esp_err_t touch_pad_proximity_get_data(touch_pad_t touch_num, uint32_t *measure_out);
+
+/**
+ * @brief Get parameter of touch sensor sleep channel.
+ *        The touch sensor can works in sleep mode to wake up sleep.
+ *
+ * @note  After the sleep channel is configured, Please use special functions for sleep channel.
+ *        e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading.
+ *
+ * @param slp_config touch sleep pad config.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_get_info(touch_pad_sleep_channel_t *slp_config);
+
+/**
+ * @brief Enable/Disable sleep channel function for touch sensor.
+ *        The touch sensor can works in sleep mode to wake up sleep.
+ *
+ * @note  ESP32S2 only support one sleep channel.
+ * @note  After the sleep channel is configured, Please use special functions for sleep channel.
+ *        e.g. The user should uses `touch_pad_sleep_channel_read_data` instead of `touch_pad_read_raw_data` to obtain the sleep channel reading.
+ *
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param enable true: enable sleep pad for touch sensor; false: disable sleep pad for touch sensor;
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_enable(touch_pad_t pad_num, bool enable);
+
+/**
+ * @brief Enable/Disable proximity function for sleep channel.
+ *        The touch sensor can works in sleep mode to wake up sleep.
+ *
+ * @note  ESP32S2 only support one sleep channel.
+ *
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param enable true: enable proximity for sleep channel; false: disable proximity for sleep channel;
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_enable_proximity(touch_pad_t pad_num, bool enable);
+
+/**
+ * @brief Set the trigger threshold of touch sensor in deep sleep.
+ *        The threshold determines the sensitivity of the touch sensor.
+ *
+ * @note  In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
+ *
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param touch_thres touch sleep pad threshold
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_set_threshold(touch_pad_t pad_num, uint32_t touch_thres);
+
+/**
+ * @brief Get the trigger threshold of touch sensor in deep sleep.
+ *        The threshold determines the sensitivity of the touch sensor.
+ *
+ * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
+ *
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param touch_thres touch sleep pad threshold
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_get_threshold(touch_pad_t pad_num, uint32_t *touch_thres);
+
+/**
+ * @brief Read benchmark of touch sensor sleep channel.
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param benchmark pointer to accept touch sensor benchmark value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG parameter is NULL
+ */
+esp_err_t touch_pad_sleep_channel_read_benchmark(touch_pad_t pad_num, uint32_t *benchmark);
+
+/**
+ * @brief Read smoothed data of touch sensor sleep channel.
+ *        Smoothed data is filtered from the raw data.
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param smooth_data pointer to accept touch sensor smoothed data
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG parameter is NULL
+ */
+esp_err_t touch_pad_sleep_channel_read_smooth(touch_pad_t pad_num, uint32_t *smooth_data);
+
+/**
+ * @brief Read raw data of touch sensor sleep channel.
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param raw_data pointer to accept touch sensor raw data
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG parameter is NULL
+ */
+esp_err_t touch_pad_sleep_channel_read_data(touch_pad_t pad_num, uint32_t *raw_data);
+
+/**
+ * @brief Reset benchmark of touch sensor sleep channel.
+ *
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_reset_benchmark(void);
+
+/**
+ * @brief Read proximity count of touch sensor sleep channel.
+ * @param pad_num Set touch channel number for sleep pad. Only one touch sensor channel is supported in deep sleep mode.
+ * @param proximity_cnt pointer to accept touch sensor proximity count value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG parameter is NULL
+ */
+esp_err_t touch_pad_sleep_channel_read_proximity_cnt(touch_pad_t pad_num, uint32_t *proximity_cnt);
+
+/**
+ * @brief Change the operating frequency of touch pad in deep sleep state. Reducing the operating frequency can effectively reduce power consumption.
+ *        If this function is not called, the working frequency of touch in the deep sleep state is the same as that in the wake-up state.
+ *
+ * @param sleep_cycle The touch sensor will sleep after each measurement.
+ *                    sleep_cycle decide the interval between each measurement.
+ *                    t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency).
+ *                    The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ * @param meas_times The times of charge and discharge in each measure process of touch channels.
+ *                  The timer frequency is 8Mhz. Range: 0 ~ 0xffff.
+ *                  Recommended typical value: Modify this value to make the measurement time around 1ms.
+ * @return
+ *     - ESP_OK Success
+ */
+esp_err_t touch_pad_sleep_channel_set_work_time(uint16_t sleep_cycle, uint16_t meas_times);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/driver/touch_sensor/esp32s3/touch_sensor.c b/components/driver/touch_sensor/esp32s3/touch_sensor.c
index d749996017b..e29091618e3 100644
--- a/components/driver/touch_sensor/esp32s3/touch_sensor.c
+++ b/components/driver/touch_sensor/esp32s3/touch_sensor.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,13 +16,13 @@
 #include "freertos/timers.h"
 #include "esp_intr_alloc.h"
 #include "driver/rtc_io.h"
-#include "driver/touch_pad.h"
+#include "driver/touch_sensor_common.h"
 #include "esp_private/rtc_ctrl.h"
 #include "driver/gpio.h"
 #include "sdkconfig.h"
 #include "esp_check.h"
 
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 #include "hal/touch_sensor_hal.h"
 
 #ifndef NDEBUG
@@ -379,7 +379,7 @@ esp_err_t touch_pad_filter_get_config(touch_filter_config_t *filter_info)
 esp_err_t touch_pad_filter_enable(void)
 {
     TOUCH_ENTER_CRITICAL();
-    touch_hal_filter_enable();
+    touch_hal_filter_enable(true);
     TOUCH_EXIT_CRITICAL();
     return ESP_OK;
 }
@@ -387,7 +387,7 @@ esp_err_t touch_pad_filter_enable(void)
 esp_err_t touch_pad_filter_disable(void)
 {
     TOUCH_ENTER_CRITICAL();
-    touch_hal_filter_disable();
+    touch_hal_filter_enable(false);
     TOUCH_EXIT_CRITICAL();
     return ESP_OK;
 }
@@ -569,9 +569,9 @@ esp_err_t touch_pad_sleep_channel_enable_proximity(touch_pad_t pad_num, bool ena
 
     TOUCH_ENTER_CRITICAL();
     if (enable) {
-        touch_hal_sleep_enable_approach();
+        touch_hal_sleep_enable_approach(true);
     } else {
-        touch_hal_sleep_disable_approach();
+        touch_hal_sleep_enable_approach(false);
     }
     TOUCH_EXIT_CRITICAL();
     return ESP_OK;
@@ -656,3 +656,17 @@ esp_err_t touch_pad_sleep_channel_set_work_time(uint16_t sleep_cycle, uint16_t m
     touch_hal_sleep_channel_set_work_time(sleep_cycle, meas_times);
     return ESP_OK;
 }
+
+/**
+ * @brief This function will be called during start up, to check that the new touch driver is not running along with the legacy touch driver
+ */
+static __attribute__((constructor)) void check_touch_driver_conflict(void)
+{
+    extern __attribute__((weak)) esp_err_t touch_sensor_new_controller(const void*, void *);
+    /* If the new Touch driver is linked, the weak function will point to the actual function in the new driver, otherwise it is NULL*/
+    if ((void *)touch_sensor_new_controller != NULL) {
+        ESP_EARLY_LOGE("legacy_touch_driver", "CONFLICT! The new touch driver can't work along with the legacy touch driver");
+        abort();
+    }
+    ESP_EARLY_LOGW("legacy_touch_driver", "legacy touch driver is deprecated, please migrate to use driver/touch_sens.h");
+}
diff --git a/components/driver/touch_sensor/include/driver/touch_sensor_common.h b/components/driver/touch_sensor/include/driver/touch_sensor_common.h
index af02b2a2fc1..848b4c2149e 100644
--- a/components/driver/touch_sensor/include/driver/touch_sensor_common.h
+++ b/components/driver/touch_sensor/include/driver/touch_sensor_common.h
@@ -8,7 +8,7 @@
 
 #include "esp_err.h"
 #include "esp_intr_alloc.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/driver/touch_sensor/touch_sensor_common.c b/components/driver/touch_sensor/touch_sensor_common.c
index cbe1d4dced8..1c901dc0be3 100644
--- a/components/driver/touch_sensor/touch_sensor_common.c
+++ b/components/driver/touch_sensor/touch_sensor_common.c
@@ -16,10 +16,9 @@
 #include "freertos/timers.h"
 #include "esp_intr_alloc.h"
 #include "driver/rtc_io.h"
-#include "driver/touch_pad.h"
 #include "esp_private/rtc_ctrl.h"
 #include "driver/gpio.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 #include "hal/touch_sensor_hal.h"
 
 static const char *TOUCH_TAG = "TOUCH_SENSOR";
diff --git a/components/driver/twai/include/driver/twai.h b/components/driver/twai/include/driver/twai.h
index 78bc71106a7..6cde097f0cd 100644
--- a/components/driver/twai/include/driver/twai.h
+++ b/components/driver/twai/include/driver/twai.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -114,6 +114,11 @@ typedef struct {
     uint32_t alerts_enabled;        /**< Bit field of alerts to enable (see documentation) */
     uint32_t clkout_divider;        /**< CLKOUT divider. Can be 1 or any even number from 2 to 14 (optional, set to 0 if unused) */
     int intr_flags;                 /**< Interrupt flags to set the priority of the driver's ISR. Note that to use the ESP_INTR_FLAG_IRAM, the CONFIG_TWAI_ISR_IN_IRAM option should be enabled first. */
+    struct {
+        uint32_t sleep_allow_pd;    /**< Set to allow power down. When this flag set, the driver will backup/restore the TWAI registers before/after entering/exist sleep mode.
+                                         By this approach, the system can power off TWAI's power domain.
+                                         This can save power, but at the expense of more RAM being consumed. */
+    } general_flags;                /**< General flags */
 } twai_general_config_t;
 
 /**
diff --git a/components/driver/twai/twai.c b/components/driver/twai/twai.c
index b6e0e982b5c..274a785133c 100644
--- a/components/driver/twai/twai.c
+++ b/components/driver/twai/twai.c
@@ -18,19 +18,24 @@
 #include "esp_heap_caps.h"
 #include "esp_clk_tree.h"
 #include "clk_ctrl_os.h"
-#include "driver/gpio.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_clk.h"
+#include "esp_private/gpio.h"
+#include "esp_private/esp_gpio_reserve.h"
 #include "driver/twai.h"
 #include "soc/soc_caps.h"
 #include "soc/soc.h"
+#include "soc/io_mux_reg.h"
 #include "soc/twai_periph.h"
-#include "soc/gpio_sig_map.h"
 #include "hal/twai_hal.h"
 #include "esp_rom_gpio.h"
+#if SOC_TWAI_SUPPORT_SLEEP_RETENTION
+#include "esp_private/sleep_retention.h"
+#endif
 
 /* ---------------------------- Definitions --------------------------------- */
 //Internal Macros
+#define TWAI_TAG "TWAI"
 #define TWAI_CHECK(cond, ret_val) ({                                        \
             if (!(cond)) {                                                  \
                 return (ret_val);                                           \
@@ -43,7 +48,6 @@
 #ifdef CONFIG_TWAI_ISR_IN_IRAM
 #define TWAI_MALLOC_CAPS    (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
 #else
-#define TWAI_TAG "TWAI"
 #define TWAI_MALLOC_CAPS    MALLOC_CAP_DEFAULT
 #endif  //CONFIG_TWAI_ISR_IN_IRAM
 
@@ -64,11 +68,17 @@
 #define TWAI_PERI_ATOMIC()
 #endif
 
+#define TWAI_USE_RETENTION_LINK  (SOC_TWAI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+
 /* ------------------ Typedefs, structures, and variables ------------------- */
 
 //Control structure for TWAI driver
 typedef struct twai_obj_t {
     int controller_id;
+    gpio_num_t tx_io;
+    gpio_num_t rx_io;
+    gpio_num_t clkout_io;
+    gpio_num_t bus_off_io;
     twai_hal_context_t hal;  // hal context
     //Control and status members
     twai_state_t state;
@@ -96,6 +106,11 @@ typedef struct twai_obj_t {
 static twai_handle_t g_twai_objs[SOC_TWAI_CONTROLLER_NUM];
 static portMUX_TYPE g_spinlock = portMUX_INITIALIZER_UNLOCKED;
 
+/* -------------------- Sleep Retention ------------------------ */
+#if TWAI_USE_RETENTION_LINK
+static esp_err_t s_twai_create_sleep_retention_link_cb(void *obj);
+#endif
+
 /* -------------------- Interrupt and Alert Handlers ------------------------ */
 
 static void twai_alert_handler(twai_obj_t *p_twai_obj, uint32_t alert_code, int *alert_req)
@@ -275,44 +290,61 @@ static void twai_intr_handler_main(void *arg)
 
 /* -------------------------- Helper functions  ----------------------------- */
 
-static void twai_configure_gpio(int controller_id, gpio_num_t tx, gpio_num_t rx, gpio_num_t clkout, gpio_num_t bus_status)
+static void twai_configure_gpio(twai_obj_t *p_obj)
 {
-    // assert the GPIO number is not a negative number (shift operation on a negative number is undefined)
-    assert(tx >= 0 && rx >= 0);
-    // if TX and RX set to the same GPIO, which means we want to create a loop-back in the GPIO matrix
-    bool io_loop_back = (tx == rx);
-    gpio_config_t gpio_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        .pull_down_en = false,
-        .pull_up_en = false,
-    };
+    uint8_t controller_id = p_obj->controller_id;
+    uint64_t gpio_mask = BIT64(p_obj->tx_io);
+
     //Set RX pin
-    gpio_conf.mode = GPIO_MODE_INPUT | (io_loop_back ? GPIO_MODE_OUTPUT : 0);
-    gpio_conf.pin_bit_mask = 1ULL << rx;
-    gpio_config(&gpio_conf);
-    esp_rom_gpio_connect_in_signal(rx, twai_controller_periph_signals.controllers[controller_id].rx_sig, false);
+    gpio_func_sel(p_obj->rx_io, PIN_FUNC_GPIO);
+    gpio_input_enable(p_obj->rx_io);
+    esp_rom_gpio_connect_in_signal(p_obj->rx_io, twai_controller_periph_signals.controllers[controller_id].rx_sig, false);
 
     //Set TX pin
-    gpio_conf.mode = GPIO_MODE_OUTPUT | (io_loop_back ? GPIO_MODE_INPUT : 0);
-    gpio_conf.pin_bit_mask = 1ULL << tx;
-    gpio_config(&gpio_conf);
-    esp_rom_gpio_connect_out_signal(tx, twai_controller_periph_signals.controllers[controller_id].tx_sig, false, false);
+    gpio_func_sel(p_obj->tx_io, PIN_FUNC_GPIO);
+    esp_rom_gpio_connect_out_signal(p_obj->tx_io, twai_controller_periph_signals.controllers[controller_id].tx_sig, false, false);
 
     //Configure output clock pin (Optional)
-    if (clkout >= 0 && clkout < GPIO_NUM_MAX) {
-        gpio_set_pull_mode(clkout, GPIO_FLOATING);
-        esp_rom_gpio_connect_out_signal(clkout, twai_controller_periph_signals.controllers[controller_id].clk_out_sig, false, false);
-        esp_rom_gpio_pad_select_gpio(clkout);
+    if (GPIO_IS_VALID_OUTPUT_GPIO(p_obj->clkout_io)) {
+        gpio_mask |= BIT64(p_obj->clkout_io);
+        gpio_func_sel(p_obj->clkout_io, PIN_FUNC_GPIO);
+        esp_rom_gpio_connect_out_signal(p_obj->clkout_io, twai_controller_periph_signals.controllers[controller_id].clk_out_sig, false, false);
     }
 
     //Configure bus status pin (Optional)
-    if (bus_status >= 0 && bus_status < GPIO_NUM_MAX) {
-        gpio_set_pull_mode(bus_status, GPIO_FLOATING);
-        esp_rom_gpio_connect_out_signal(bus_status, twai_controller_periph_signals.controllers[controller_id].bus_off_sig, false, false);
-        esp_rom_gpio_pad_select_gpio(bus_status);
+    if (GPIO_IS_VALID_OUTPUT_GPIO(p_obj->bus_off_io)) {
+        gpio_mask |= BIT64(p_obj->bus_off_io);
+        gpio_func_sel(p_obj->bus_off_io, PIN_FUNC_GPIO);
+        esp_rom_gpio_connect_out_signal(p_obj->bus_off_io, twai_controller_periph_signals.controllers[controller_id].bus_off_sig, false, false);
+    }
+
+    uint64_t busy_mask = esp_gpio_reserve(gpio_mask);
+    uint64_t conflict_mask = busy_mask & gpio_mask;
+    for (; conflict_mask > 0;) {
+        uint8_t pos = __builtin_ctz(conflict_mask);
+        conflict_mask &= ~(1 << pos);
+        ESP_LOGW(TWAI_TAG, "GPIO %d is not usable, maybe used by others", pos);
     }
 }
 
+static void twai_release_gpio(twai_obj_t *p_obj)
+{
+    assert(p_obj);
+    uint64_t gpio_mask = BIT64(p_obj->tx_io);
+
+    esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, twai_controller_periph_signals.controllers[p_obj->controller_id].rx_sig, false);
+    gpio_output_disable(p_obj->tx_io);
+    if (GPIO_IS_VALID_OUTPUT_GPIO(p_obj->clkout_io)) {
+        gpio_mask |= BIT64(p_obj->clkout_io);
+        gpio_output_disable(p_obj->clkout_io);
+    }
+    if (GPIO_IS_VALID_OUTPUT_GPIO(p_obj->bus_off_io)) {
+        gpio_mask |= BIT64(p_obj->bus_off_io);
+        gpio_output_disable(p_obj->bus_off_io);
+    }
+    esp_gpio_revoke(gpio_mask);
+}
+
 static void twai_free_driver_obj(twai_obj_t *p_obj)
 {
     //Free driver object and any dependent SW resources it uses (queues, semaphores, interrupts, PM locks etc)
@@ -334,6 +366,19 @@ static void twai_free_driver_obj(twai_obj_t *p_obj)
     if (p_obj->alert_semphr != NULL) {
         vSemaphoreDeleteWithCaps(p_obj->alert_semphr);
     }
+
+#if TWAI_USE_RETENTION_LINK
+    const periph_retention_module_t retention_id = twai_reg_retention_info[p_obj->controller_id].module_id;
+    if (sleep_retention_get_created_modules() & BIT(retention_id)) {
+        assert(sleep_retention_get_inited_modules() & BIT(retention_id));
+        sleep_retention_module_free(retention_id);
+    }
+    if (sleep_retention_get_inited_modules() & BIT(retention_id)) {
+        sleep_retention_module_deinit(retention_id);
+    }
+
+#endif
+
     heap_caps_free(p_obj);
 }
 
@@ -365,6 +410,9 @@ static esp_err_t twai_alloc_driver_obj(const twai_general_config_t *g_config, tw
     if (ret != ESP_OK) {
         goto err;
     }
+
+    p_obj->controller_id = controller_id;
+
 #if CONFIG_PM_ENABLE
 #if SOC_TWAI_CLK_SUPPORT_APB
     // DFS can change APB frequency. So add lock to prevent sleep and APB freq from changing
@@ -384,6 +432,28 @@ static esp_err_t twai_alloc_driver_obj(const twai_general_config_t *g_config, tw
 #endif //SOC_TWAI_CLK_SUPPORT_APB
 #endif //CONFIG_PM_ENABLE
 
+#if TWAI_USE_RETENTION_LINK
+    sleep_retention_module_t module = twai_reg_retention_info[controller_id].module_id;
+    sleep_retention_module_init_param_t init_param = {
+        .cbs = {
+            .create = {
+                .handle = s_twai_create_sleep_retention_link_cb,
+                .arg = p_obj,
+            },
+        },
+        .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM)
+    };
+    if (sleep_retention_module_init(module, &init_param) != ESP_OK) {
+        ESP_LOGW(TWAI_TAG, "init sleep retention failed for TWAI%d, power domain may be turned off during sleep", controller_id);
+    }
+
+    if (g_config->general_flags.sleep_allow_pd) {
+        if (sleep_retention_module_allocate(module) != ESP_OK) {
+            ESP_LOGW(TWAI_TAG, "create retention module failed, power domain can't turn off");
+        }
+    }
+#endif
+
     *p_twai_obj_ret = p_obj;
     return ESP_OK;
 
@@ -401,6 +471,7 @@ esp_err_t twai_driver_install_v2(const twai_general_config_t *g_config, const tw
     TWAI_CHECK(f_config != NULL, ESP_ERR_INVALID_ARG);
     TWAI_CHECK(g_config->controller_id < SOC_TWAI_CONTROLLER_NUM, ESP_ERR_INVALID_ARG);
     TWAI_CHECK(g_config->rx_queue_len > 0, ESP_ERR_INVALID_ARG);
+    // assert the GPIO number is not a negative number (shift operation on a negative number is undefined)
     TWAI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(g_config->tx_io), ESP_ERR_INVALID_ARG);
     TWAI_CHECK(GPIO_IS_VALID_GPIO(g_config->rx_io), ESP_ERR_INVALID_ARG);
 #ifndef CONFIG_TWAI_ISR_IN_IRAM
@@ -408,6 +479,9 @@ esp_err_t twai_driver_install_v2(const twai_general_config_t *g_config, const tw
 #endif
     int controller_id = g_config->controller_id;
     TWAI_CHECK(g_twai_objs[controller_id] == NULL, ESP_ERR_INVALID_STATE);
+#if !SOC_TWAI_SUPPORT_SLEEP_RETENTION
+    TWAI_CHECK(!g_config->general_flags.sleep_allow_pd, ESP_ERR_INVALID_ARG);
+#endif
 
     //Get clock source resolution
     uint32_t clock_source_hz = 0;
@@ -437,10 +511,13 @@ esp_err_t twai_driver_install_v2(const twai_general_config_t *g_config, const tw
 
     //Initialize flags and variables. All other members are already set to zero by twai_alloc_driver_obj()
     portMUX_INITIALIZE(&p_twai_obj->spinlock);
-    p_twai_obj->controller_id = controller_id;
     p_twai_obj->state = TWAI_STATE_STOPPED;
     p_twai_obj->mode = g_config->mode;
     p_twai_obj->alerts_enabled = g_config->alerts_enabled;
+    p_twai_obj->tx_io = g_config->tx_io;
+    p_twai_obj->rx_io = g_config->rx_io;
+    p_twai_obj->clkout_io = g_config->clkout_io;
+    p_twai_obj->bus_off_io = g_config->bus_off_io;
 
     //Assign the TWAI object
     portENTER_CRITICAL(&g_spinlock);
@@ -475,7 +552,7 @@ esp_err_t twai_driver_install_v2(const twai_general_config_t *g_config, const tw
     twai_hal_configure(&p_twai_obj->hal, t_config, f_config, DRIVER_DEFAULT_INTERRUPTS, g_config->clkout_divider);
 
     //Assign GPIO and Interrupts
-    twai_configure_gpio(controller_id, g_config->tx_io, g_config->rx_io, g_config->clkout_io, g_config->bus_off_io);
+    twai_configure_gpio(p_twai_obj);
 
 #if CONFIG_PM_ENABLE
     //Acquire PM lock
@@ -523,6 +600,9 @@ esp_err_t twai_driver_uninstall_v2(twai_handle_t handle)
     g_twai_objs[controller_id] = NULL;
     portEXIT_CRITICAL(&g_spinlock);
 
+    //Disable interrupt
+    ESP_ERROR_CHECK(esp_intr_disable(p_twai_obj->isr_handle));
+
     //Clear registers by reading
     twai_hal_deinit(&p_twai_obj->hal);
     TWAI_PERI_ATOMIC() {
@@ -539,8 +619,7 @@ esp_err_t twai_driver_uninstall_v2(twai_handle_t handle)
     }
 #endif //CONFIG_PM_ENABLE
 
-    //Disable interrupt
-    ESP_ERROR_CHECK(esp_intr_disable(p_twai_obj->isr_handle));
+    twai_release_gpio(p_twai_obj);
     //Free twai driver object
     twai_free_driver_obj(p_twai_obj);
     return ESP_OK;
@@ -874,3 +953,14 @@ esp_err_t twai_clear_receive_queue(void)
     // the handle-less driver API only support one TWAI controller, i.e. the g_twai_objs[0]
     return twai_clear_receive_queue_v2(g_twai_objs[0]);
 }
+
+#if TWAI_USE_RETENTION_LINK
+static esp_err_t s_twai_create_sleep_retention_link_cb(void *obj)
+{
+    twai_obj_t *host = (twai_obj_t *)obj;
+    return sleep_retention_entries_create(twai_reg_retention_info[host->controller_id].entry_array,
+                                          twai_reg_retention_info[host->controller_id].array_size,
+                                          REGDMA_LINK_PRI_TWAI,
+                                          twai_reg_retention_info[host->controller_id].module_id);
+}
+#endif
diff --git a/components/efuse/CMakeLists.txt b/components/efuse/CMakeLists.txt
index e0f57b1d343..8b5d587213e 100644
--- a/components/efuse/CMakeLists.txt
+++ b/components/efuse/CMakeLists.txt
@@ -1,4 +1,5 @@
 idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(non_os_build NON_OS_BUILD)
 
 if(CONFIG_EFUSE_VIRTUAL)
     message(STATUS "Efuse virtual mode is enabled. If Secure boot or Flash encryption is on"
@@ -28,7 +29,7 @@ list(APPEND srcs "src/esp_efuse_api.c"
                  "src/esp_efuse_utility.c"
                  "src/efuse_controller/keys/${type}/esp_efuse_api_key.c")
 
-if(BOOTLOADER_BUILD)
+if(non_os_build)
     idf_component_register(SRCS "${srcs}"
                     PRIV_REQUIRES bootloader_support soc spi_flash
                     INCLUDE_DIRS "${include_dirs}"
diff --git a/components/efuse/esp32c2/esp_efuse_rtc_calib.c b/components/efuse/esp32c2/esp_efuse_rtc_calib.c
index 79d91b23192..467b2048e70 100644
--- a/components/efuse/esp32c2/esp_efuse_rtc_calib.c
+++ b/components/efuse/esp32c2/esp_efuse_rtc_calib.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -111,7 +111,18 @@ esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, in
 
 esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
 {
-    // Currently calibration is not supported on ESP32-C2, IDF-5236
-    *tsens_cal = 0.0;
+    const esp_efuse_desc_t** cal_temp_efuse;
+    cal_temp_efuse = ESP_EFUSE_TEMP_CALIB;
+    int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
+    assert(cal_temp_size == 9);
+
+    uint32_t cal_temp = 0;
+    esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
+    if (err != ESP_OK) {
+        *tsens_cal = 0.0;
+        return err;
+    }
+    // BIT(8) stands for sign: 1: negative, 0: positive
+    *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
     return ESP_OK;
 }
diff --git a/components/efuse/esp32c5/esp_efuse_rtc_calib.c b/components/efuse/esp32c5/esp_efuse_rtc_calib.c
index 4e59366f55a..98b6e836f3f 100644
--- a/components/efuse/esp32c5/esp_efuse_rtc_calib.c
+++ b/components/efuse/esp32c5/esp_efuse_rtc_calib.c
@@ -49,8 +49,18 @@ esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, in
 
 esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
 {
-    // Currently calibration is not supported on ESP32-C5, IDF-5236
-    // Allow no calibration
-    *tsens_cal = 0;
+    const esp_efuse_desc_t** cal_temp_efuse;
+    cal_temp_efuse = ESP_EFUSE_TEMPERATURE_SENSOR;
+    int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
+    assert(cal_temp_size == 9);
+
+    uint32_t cal_temp = 0;
+    esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
+    if (err != ESP_OK) {
+        *tsens_cal = 0.0;
+        return err;
+    }
+    // BIT(8) stands for sign: 1: negative, 0: positive
+    *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
     return ESP_OK;
 }
diff --git a/components/efuse/esp32c5/esp_efuse_table.c b/components/efuse/esp32c5/esp_efuse_table.c
index 7c0837a52d0..54279b76a40 100644
--- a/components/efuse/esp32c5/esp_efuse_table.c
+++ b/components/efuse/esp32c5/esp_efuse_table.c
@@ -9,7 +9,7 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f
+// md5_digest_table b26e7466c400977081a142076ef1a5bb
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -287,14 +287,102 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of BLOCK2,
 };
 
+static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_HP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_LP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LSLP_HP_DBG,
+};
+
+static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LSLP_HP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_LP_DBG,
+};
+
+static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_LP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LP_HP_DBIAS_VOL_GAP,
+};
+
 static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OPTIONAL_UNIQUE_ID,
 };
 
+static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of TEMPERATURE_SENSOR,
+};
+
 static const esp_efuse_desc_t WR_DIS_OCODE[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OCODE,
 };
 
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF,
+};
+
 static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
     {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
 };
@@ -648,14 +736,102 @@ static const esp_efuse_desc_t TRIM_P_BIAS[] = {
     {EFUSE_BLK1, 101, 5}, 	 // [] PADC CAL P bias,
 };
 
+static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = {
+    {EFUSE_BLK1, 106, 4}, 	 // [] Active HP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = {
+    {EFUSE_BLK1, 110, 4}, 	 // [] Active LP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t LSLP_HP_DBG[] = {
+    {EFUSE_BLK1, 114, 2}, 	 // [] LSLP HP DBG of fixed voltage,
+};
+
+static const esp_efuse_desc_t LSLP_HP_DBIAS[] = {
+    {EFUSE_BLK1, 116, 4}, 	 // [] LSLP HP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t DSLP_LP_DBG[] = {
+    {EFUSE_BLK1, 120, 4}, 	 // [] DSLP LP DBG of fixed voltage,
+};
+
+static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
+    {EFUSE_BLK1, 124, 5}, 	 // [] DSLP LP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = {
+    {EFUSE_BLK1, 129, 5}, 	 // [] DBIAS gap between LP and HP,
+};
+
 static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
     {EFUSE_BLK2, 0, 128}, 	 // [] Optional unique 128-bit ID,
 };
 
+static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK2, 128, 9}, 	 // [] Temperature calibration data,
+};
+
 static const esp_efuse_desc_t OCODE[] = {
     {EFUSE_BLK2, 137, 8}, 	 // [] ADC OCode,
 };
 
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK2, 145, 10}, 	 // [] Average initcode of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK2, 155, 10}, 	 // [] Average initcode of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK2, 165, 10}, 	 // [] Average initcode of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK2, 175, 10}, 	 // [] Average initcode of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK2, 185, 10}, 	 // [] HI DOUT of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK2, 195, 10}, 	 // [] HI DOUT of ADC1 atten1,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK2, 205, 10}, 	 // [] HI DOUT of ADC1 atten2,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK2, 215, 10}, 	 // [] HI DOUT of ADC1 atten3,
+};
+
+static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 225, 4}, 	 // [] Gap between ADC1 CH0 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 229, 4}, 	 // [] Gap between ADC1 CH1 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 233, 4}, 	 // [] Gap between ADC1 CH2 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 237, 4}, 	 // [] Gap between ADC1 CH3 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 241, 4}, 	 // [] Gap between ADC1 CH4 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 245, 4}, 	 // [] Gap between ADC1 CH5 and average initcode,
+};
+
 static const esp_efuse_desc_t USER_DATA[] = {
     {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
 };
@@ -1036,16 +1212,126 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = {
+    &WR_DIS_ACTIVE_HP_DBIAS[0],    		// [] wr_dis of ACTIVE_HP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = {
+    &WR_DIS_ACTIVE_LP_DBIAS[0],    		// [] wr_dis of ACTIVE_LP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = {
+    &WR_DIS_LSLP_HP_DBG[0],    		// [] wr_dis of LSLP_HP_DBG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = {
+    &WR_DIS_LSLP_HP_DBIAS[0],    		// [] wr_dis of LSLP_HP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = {
+    &WR_DIS_DSLP_LP_DBG[0],    		// [] wr_dis of DSLP_LP_DBG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
+    &WR_DIS_DSLP_LP_DBIAS[0],    		// [] wr_dis of DSLP_LP_DBIAS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
+    &WR_DIS_LP_HP_DBIAS_VOL_GAP[0],    		// [] wr_dis of LP_HP_DBIAS_VOL_GAP
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
     &WR_DIS_OPTIONAL_UNIQUE_ID[0],    		// [] wr_dis of OPTIONAL_UNIQUE_ID
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = {
+    &WR_DIS_TEMPERATURE_SENSOR[0],    		// [] wr_dis of TEMPERATURE_SENSOR
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
     &WR_DIS_OCODE[0],    		// [] wr_dis of OCODE
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN0[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN1[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN2[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN3[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
     &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
     NULL
@@ -1486,16 +1772,126 @@ const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = {
+    &ACTIVE_HP_DBIAS[0],    		// [] Active HP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = {
+    &ACTIVE_LP_DBIAS[0],    		// [] Active LP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = {
+    &LSLP_HP_DBG[0],    		// [] LSLP HP DBG of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = {
+    &LSLP_HP_DBIAS[0],    		// [] LSLP HP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = {
+    &DSLP_LP_DBG[0],    		// [] DSLP LP DBG of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
+    &DSLP_LP_DBIAS[0],    		// [] DSLP LP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = {
+    &LP_HP_DBIAS_VOL_GAP[0],    		// [] DBIAS gap between LP and HP
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
     &OPTIONAL_UNIQUE_ID[0],    		// [] Optional unique 128-bit ID
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = {
+    &TEMPERATURE_SENSOR[0],    		// [] Temperature calibration data
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
     &OCODE[0],    		// [] ADC OCode
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
+    &ADC1_AVE_INITCODE_ATTEN0[0],    		// [] Average initcode of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
+    &ADC1_AVE_INITCODE_ATTEN1[0],    		// [] Average initcode of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
+    &ADC1_AVE_INITCODE_ATTEN2[0],    		// [] Average initcode of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
+    &ADC1_AVE_INITCODE_ATTEN3[0],    		// [] Average initcode of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
+    &ADC1_HI_DOUT_ATTEN0[0],    		// [] HI DOUT of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
+    &ADC1_HI_DOUT_ATTEN1[0],    		// [] HI DOUT of ADC1 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
+    &ADC1_HI_DOUT_ATTEN2[0],    		// [] HI DOUT of ADC1 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
+    &ADC1_HI_DOUT_ATTEN3[0],    		// [] HI DOUT of ADC1 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH0 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH1 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH2 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH3 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH4 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH5 and average initcode
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
     &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
     NULL
diff --git a/components/efuse/esp32c5/esp_efuse_table.csv b/components/efuse/esp32c5/esp_efuse_table.csv
index 29fc4e1f5c2..3ba2839da4e 100644
--- a/components/efuse/esp32c5/esp_efuse_table.csv
+++ b/components/efuse/esp32c5/esp_efuse_table.csv
@@ -9,7 +9,7 @@
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# This file was generated by regtools.py based on the efuses.yaml file with the version: b09fa417de505238a601eddce188b696
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 287a0ed4951aba84b9571a5f31000275
 
 WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
 WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
@@ -79,8 +79,30 @@ WR_DIS.PA_TRIM_VERSION,                          EFUSE_BLK0,  20,   1, [] wr_dis
 WR_DIS.TRIM_N_BIAS,                              EFUSE_BLK0,  20,   1, [] wr_dis of TRIM_N_BIAS
 WR_DIS.TRIM_P_BIAS,                              EFUSE_BLK0,  20,   1, [] wr_dis of TRIM_P_BIAS
 WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
+WR_DIS.ACTIVE_HP_DBIAS,                          EFUSE_BLK0,  20,   1, [] wr_dis of ACTIVE_HP_DBIAS
+WR_DIS.ACTIVE_LP_DBIAS,                          EFUSE_BLK0,  20,   1, [] wr_dis of ACTIVE_LP_DBIAS
+WR_DIS.LSLP_HP_DBG,                              EFUSE_BLK0,  20,   1, [] wr_dis of LSLP_HP_DBG
+WR_DIS.LSLP_HP_DBIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of LSLP_HP_DBIAS
+WR_DIS.DSLP_LP_DBG,                              EFUSE_BLK0,  20,   1, [] wr_dis of DSLP_LP_DBG
+WR_DIS.DSLP_LP_DBIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of DSLP_LP_DBIAS
+WR_DIS.LP_HP_DBIAS_VOL_GAP,                      EFUSE_BLK0,  20,   1, [] wr_dis of LP_HP_DBIAS_VOL_GAP
 WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
+WR_DIS.TEMPERATURE_SENSOR,                       EFUSE_BLK0,  21,   1, [] wr_dis of TEMPERATURE_SENSOR
 WR_DIS.OCODE,                                    EFUSE_BLK0,  21,   1, [] wr_dis of OCODE
+WR_DIS.ADC1_AVE_INITCODE_ATTEN0,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
+WR_DIS.ADC1_AVE_INITCODE_ATTEN1,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
+WR_DIS.ADC1_AVE_INITCODE_ATTEN2,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
+WR_DIS.ADC1_AVE_INITCODE_ATTEN3,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
+WR_DIS.ADC1_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
+WR_DIS.ADC1_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
+WR_DIS.ADC1_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
+WR_DIS.ADC1_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
+WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
 WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
 WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
 WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -173,8 +195,30 @@ PKG_VERSION,                                     EFUSE_BLK1,  90,   3, [] Packag
 PA_TRIM_VERSION,                                 EFUSE_BLK1,  93,   3, [] PADC CAL PA trim version
 TRIM_N_BIAS,                                     EFUSE_BLK1,  96,   5, [] PADC CAL N bias
 TRIM_P_BIAS,                                     EFUSE_BLK1, 101,   5, [] PADC CAL P bias
+ACTIVE_HP_DBIAS,                                 EFUSE_BLK1, 106,   4, [] Active HP DBIAS of fixed voltage
+ACTIVE_LP_DBIAS,                                 EFUSE_BLK1, 110,   4, [] Active LP DBIAS of fixed voltage
+LSLP_HP_DBG,                                     EFUSE_BLK1, 114,   2, [] LSLP HP DBG of fixed voltage
+LSLP_HP_DBIAS,                                   EFUSE_BLK1, 116,   4, [] LSLP HP DBIAS of fixed voltage
+DSLP_LP_DBG,                                     EFUSE_BLK1, 120,   4, [] DSLP LP DBG of fixed voltage
+DSLP_LP_DBIAS,                                   EFUSE_BLK1, 124,   5, [] DSLP LP DBIAS of fixed voltage
+LP_HP_DBIAS_VOL_GAP,                             EFUSE_BLK1, 129,   5, [] DBIAS gap between LP and HP
 OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
+TEMPERATURE_SENSOR,                              EFUSE_BLK2, 128,   9, [] Temperature calibration data
 OCODE,                                           EFUSE_BLK2, 137,   8, [] ADC OCode
+ADC1_AVE_INITCODE_ATTEN0,                        EFUSE_BLK2, 145,  10, [] Average initcode of ADC1 atten0
+ADC1_AVE_INITCODE_ATTEN1,                        EFUSE_BLK2, 155,  10, [] Average initcode of ADC1 atten0
+ADC1_AVE_INITCODE_ATTEN2,                        EFUSE_BLK2, 165,  10, [] Average initcode of ADC1 atten0
+ADC1_AVE_INITCODE_ATTEN3,                        EFUSE_BLK2, 175,  10, [] Average initcode of ADC1 atten0
+ADC1_HI_DOUT_ATTEN0,                             EFUSE_BLK2, 185,  10, [] HI DOUT of ADC1 atten0
+ADC1_HI_DOUT_ATTEN1,                             EFUSE_BLK2, 195,  10, [] HI DOUT of ADC1 atten1
+ADC1_HI_DOUT_ATTEN2,                             EFUSE_BLK2, 205,  10, [] HI DOUT of ADC1 atten2
+ADC1_HI_DOUT_ATTEN3,                             EFUSE_BLK2, 215,  10, [] HI DOUT of ADC1 atten3
+ADC1_CH0_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 225,   4, [] Gap between ADC1 CH0 and average initcode
+ADC1_CH1_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 229,   4, [] Gap between ADC1 CH1 and average initcode
+ADC1_CH2_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 233,   4, [] Gap between ADC1 CH2 and average initcode
+ADC1_CH3_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 237,   4, [] Gap between ADC1 CH3 and average initcode
+ADC1_CH4_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 241,   4, [] Gap between ADC1 CH4 and average initcode
+ADC1_CH5_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 245,   4, [] Gap between ADC1 CH5 and average initcode
 USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
 USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
 KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
diff --git a/components/efuse/esp32c5/include/esp_efuse_table.h b/components/efuse/esp32c5/include/esp_efuse_table.h
index 5cc46273545..7bcd93b66aa 100644
--- a/components/efuse/esp32c5/include/esp_efuse_table.h
+++ b/components/efuse/esp32c5/include/esp_efuse_table.h
@@ -10,7 +10,7 @@ extern "C" {
 
 #include "esp_efuse.h"
 
-// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f
+// md5_digest_table b26e7466c400977081a142076ef1a5bb
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -92,8 +92,30 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
 #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -205,8 +227,30 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
 #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
diff --git a/components/efuse/esp32c6/esp_efuse_rtc_calib.c b/components/efuse/esp32c6/esp_efuse_rtc_calib.c
index 5477b095a49..3a3573d93ac 100644
--- a/components/efuse/esp32c6/esp_efuse_rtc_calib.c
+++ b/components/efuse/esp32c6/esp_efuse_rtc_calib.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -132,7 +132,18 @@ esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, in
 
 esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
 {
-    // Currently calibration is not supported on ESP32-C6, IDF-5236
-    *tsens_cal = 0;
+    const esp_efuse_desc_t** cal_temp_efuse;
+    cal_temp_efuse = ESP_EFUSE_TEMP_CALIB;
+    int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
+    assert(cal_temp_size == 9);
+
+    uint32_t cal_temp = 0;
+    esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
+    if (err != ESP_OK) {
+        *tsens_cal = 0.0;
+        return err;
+    }
+    // BIT(8) stands for sign: 1: negative, 0: positive
+    *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
     return ESP_OK;
 }
diff --git a/components/efuse/esp32c61/esp_efuse_table.c b/components/efuse/esp32c61/esp_efuse_table.c
index 07784d930ee..4ff8c7c62fc 100644
--- a/components/efuse/esp32c61/esp_efuse_table.c
+++ b/components/efuse/esp32c61/esp_efuse_table.c
@@ -9,7 +9,7 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table 52aee23d9256003919a3d01945678355
+// md5_digest_table af9aaa79feb0970d90f35360a5113f03
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -235,6 +235,62 @@ static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OPTIONAL_UNIQUE_ID,
 };
 
+static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of TEMPERATURE_SENSOR,
+};
+
+static const esp_efuse_desc_t WR_DIS_OCODE[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OCODE,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
+};
+
 static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
     {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
 };
@@ -528,6 +584,62 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
     {EFUSE_BLK2, 0, 128}, 	 // [] Optional unique 128-bit ID,
 };
 
+static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK2, 128, 9}, 	 // [] Temperature calibration data,
+};
+
+static const esp_efuse_desc_t OCODE[] = {
+    {EFUSE_BLK2, 137, 8}, 	 // [] ADC OCode calibration,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN0[] = {
+    {EFUSE_BLK2, 145, 10}, 	 // [] Average initcode of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN1[] = {
+    {EFUSE_BLK2, 155, 10}, 	 // [] Average initcode of ADC1 atten1,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN2[] = {
+    {EFUSE_BLK2, 165, 10}, 	 // [] Average initcode of ADC1 atten2,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN3[] = {
+    {EFUSE_BLK2, 175, 10}, 	 // [] Average initcode of ADC1 atten3,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK2, 185, 10}, 	 // [] HI_DOUT of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK2, 195, 10}, 	 // [] HI_DOUT of ADC1 atten1,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK2, 205, 10}, 	 // [] HI_DOUT of ADC1 atten2,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK2, 215, 10}, 	 // [] HI_DOUT of ADC1 atten3,
+};
+
+static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 225, 4}, 	 // [] Gap between ADC1 CH0 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 229, 4}, 	 // [] Gap between ADC1 CH1 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 233, 4}, 	 // [] Gap between ADC1 CH2 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK2, 237, 4}, 	 // [] Gap between ADC1 CH3 and average initcode,
+};
+
 static const esp_efuse_desc_t USER_DATA[] = {
     {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
 };
@@ -843,6 +955,76 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = {
+    &WR_DIS_TEMPERATURE_SENSOR[0],    		// [] wr_dis of TEMPERATURE_SENSOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
+    &WR_DIS_OCODE[0],    		// [] wr_dis of OCODE
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[] = {
+    &WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[0],    		// [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[] = {
+    &WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[0],    		// [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[] = {
+    &WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[0],    		// [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[] = {
+    &WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[0],    		// [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN0[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN1[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN2[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN3[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
     &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
     NULL
@@ -1208,6 +1390,76 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = {
+    &TEMPERATURE_SENSOR[0],    		// [] Temperature calibration data
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
+    &OCODE[0],    		// [] ADC OCode calibration
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN0[] = {
+    &ADC1_AVE_INIT_CODE_ATTEN0[0],    		// [] Average initcode of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN1[] = {
+    &ADC1_AVE_INIT_CODE_ATTEN1[0],    		// [] Average initcode of ADC1 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN2[] = {
+    &ADC1_AVE_INIT_CODE_ATTEN2[0],    		// [] Average initcode of ADC1 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN3[] = {
+    &ADC1_AVE_INIT_CODE_ATTEN3[0],    		// [] Average initcode of ADC1 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
+    &ADC1_HI_DOUT_ATTEN0[0],    		// [] HI_DOUT of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
+    &ADC1_HI_DOUT_ATTEN1[0],    		// [] HI_DOUT of ADC1 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
+    &ADC1_HI_DOUT_ATTEN2[0],    		// [] HI_DOUT of ADC1 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
+    &ADC1_HI_DOUT_ATTEN3[0],    		// [] HI_DOUT of ADC1 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH0 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH1 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH2 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1 CH3 and average initcode
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
     &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
     NULL
diff --git a/components/efuse/esp32c61/esp_efuse_table.csv b/components/efuse/esp32c61/esp_efuse_table.csv
index 271c86df89c..2a82ff95b51 100644
--- a/components/efuse/esp32c61/esp_efuse_table.csv
+++ b/components/efuse/esp32c61/esp_efuse_table.csv
@@ -9,7 +9,7 @@
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# This file was generated by regtools.py based on the efuses.yaml file with the version: e564f8042b56a475a7714bb28ecdadfa
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 8f05ff9d292b10d2360200fae1d15e8d
 
 WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
 WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
@@ -66,6 +66,20 @@ WR_DIS.TEMP,                                     EFUSE_BLK0,  20,   1, [] wr_dis
 WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
 WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
 WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
+WR_DIS.TEMPERATURE_SENSOR,                       EFUSE_BLK0,  21,   1, [] wr_dis of TEMPERATURE_SENSOR
+WR_DIS.OCODE,                                    EFUSE_BLK0,  21,   1, [] wr_dis of OCODE
+WR_DIS.ADC1_AVE_INIT_CODE_ATTEN0,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0
+WR_DIS.ADC1_AVE_INIT_CODE_ATTEN1,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1
+WR_DIS.ADC1_AVE_INIT_CODE_ATTEN2,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2
+WR_DIS.ADC1_AVE_INIT_CODE_ATTEN3,                EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3
+WR_DIS.ADC1_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
+WR_DIS.ADC1_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
+WR_DIS.ADC1_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
+WR_DIS.ADC1_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
+WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
 WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
 WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
 WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -143,6 +157,20 @@ PSRAM_VENDOR,                                    EFUSE_BLK1,  86,   2, [] PSRAM
 TEMP,                                            EFUSE_BLK1,  88,   2, [] Temperature
 PKG_VERSION,                                     EFUSE_BLK1,  90,   3, [] Package version
 OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
+TEMPERATURE_SENSOR,                              EFUSE_BLK2, 128,   9, [] Temperature calibration data
+OCODE,                                           EFUSE_BLK2, 137,   8, [] ADC OCode calibration
+ADC1_AVE_INIT_CODE_ATTEN0,                       EFUSE_BLK2, 145,  10, [] Average initcode of ADC1 atten0
+ADC1_AVE_INIT_CODE_ATTEN1,                       EFUSE_BLK2, 155,  10, [] Average initcode of ADC1 atten1
+ADC1_AVE_INIT_CODE_ATTEN2,                       EFUSE_BLK2, 165,  10, [] Average initcode of ADC1 atten2
+ADC1_AVE_INIT_CODE_ATTEN3,                       EFUSE_BLK2, 175,  10, [] Average initcode of ADC1 atten3
+ADC1_HI_DOUT_ATTEN0,                             EFUSE_BLK2, 185,  10, [] HI_DOUT of ADC1 atten0
+ADC1_HI_DOUT_ATTEN1,                             EFUSE_BLK2, 195,  10, [] HI_DOUT of ADC1 atten1
+ADC1_HI_DOUT_ATTEN2,                             EFUSE_BLK2, 205,  10, [] HI_DOUT of ADC1 atten2
+ADC1_HI_DOUT_ATTEN3,                             EFUSE_BLK2, 215,  10, [] HI_DOUT of ADC1 atten3
+ADC1_CH0_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 225,   4, [] Gap between ADC1 CH0 and average initcode
+ADC1_CH1_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 229,   4, [] Gap between ADC1 CH1 and average initcode
+ADC1_CH2_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 233,   4, [] Gap between ADC1 CH2 and average initcode
+ADC1_CH3_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK2, 237,   4, [] Gap between ADC1 CH3 and average initcode
 USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
 USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
 KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
diff --git a/components/efuse/esp32c61/include/esp_efuse_table.h b/components/efuse/esp32c61/include/esp_efuse_table.h
index 085c9223e28..40844a05810 100644
--- a/components/efuse/esp32c61/include/esp_efuse_table.h
+++ b/components/efuse/esp32c61/include/esp_efuse_table.h
@@ -10,7 +10,7 @@ extern "C" {
 
 #include "esp_efuse.h"
 
-// md5_digest_table 52aee23d9256003919a3d01945678355
+// md5_digest_table af9aaa79feb0970d90f35360a5113f03
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -79,6 +79,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
 #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -175,6 +189,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
+extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
 #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
diff --git a/components/efuse/esp32h2/esp_efuse_rtc_calib.c b/components/efuse/esp32h2/esp_efuse_rtc_calib.c
index 2ff20ea3a3c..9d782c89542 100644
--- a/components/efuse/esp32h2/esp_efuse_rtc_calib.c
+++ b/components/efuse/esp32h2/esp_efuse_rtc_calib.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -124,7 +124,18 @@ esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, uint32_t adc_unit, in
 
 esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
 {
-    // Currently calibration is not supported on ESP32-H2, IDF-5236
-    *tsens_cal = 0;
+    const esp_efuse_desc_t** cal_temp_efuse;
+    cal_temp_efuse = ESP_EFUSE_TEMP_CALIB;
+    int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
+    assert(cal_temp_size == 9);
+
+    uint32_t cal_temp = 0;
+    esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
+    if (err != ESP_OK) {
+        *tsens_cal = 0.0;
+        return err;
+    }
+    // BIT(8) stands for sign: 1: negative, 0: positive
+    *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
     return ESP_OK;
 }
diff --git a/components/efuse/esp32p4/esp_efuse_rtc_calib.c b/components/efuse/esp32p4/esp_efuse_rtc_calib.c
index 47ac9117d79..db583af99ec 100644
--- a/components/efuse/esp32p4/esp_efuse_rtc_calib.c
+++ b/components/efuse/esp32p4/esp_efuse_rtc_calib.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,7 @@
 #include <esp_bit_defs.h>
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
+#include "esp_efuse_rtc_calib.h"
 
 int esp_efuse_rtc_calib_get_ver(void)
 {
@@ -35,7 +36,18 @@ esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t*
 
 esp_err_t esp_efuse_rtc_calib_get_tsens_val(float* tsens_cal)
 {
-    //TODO: IDF-7482
-    *tsens_cal = 0;
-    return ESP_ERR_NOT_SUPPORTED;
+    const esp_efuse_desc_t** cal_temp_efuse;
+    cal_temp_efuse = ESP_EFUSE_TEMPERATURE_SENSOR;
+    int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse);
+    assert(cal_temp_size == 9);
+
+    uint32_t cal_temp = 0;
+    esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size);
+    if (err != ESP_OK) {
+        *tsens_cal = 0.0;
+        return err;
+    }
+    // BIT(8) stands for sign: 1: negative, 0: positive
+    *tsens_cal = ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp;
+    return ESP_OK;
 }
diff --git a/components/efuse/esp32p4/esp_efuse_table.c b/components/efuse/esp32p4/esp_efuse_table.c
index 990c984365d..049cd56f113 100644
--- a/components/efuse/esp32p4/esp_efuse_table.c
+++ b/components/efuse/esp32p4/esp_efuse_table.c
@@ -9,7 +9,7 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b
+// md5_digest_table c56ed98dde7a08c8f70d57a01faba96a
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -287,10 +287,122 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of BLOCK2,
 };
 
+static const esp_efuse_desc_t WR_DIS_LDO_VO1_DREF[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO1_DREF,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO2_DREF[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO2_DREF,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO1_MUL[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO1_MUL,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO2_MUL[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO2_MUL,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO3_K[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO3_K,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO3_VOS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO3_VOS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO3_C[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO3_C,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO4_K[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO4_K,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO4_VOS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO4_VOS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LDO_VO4_C[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LDO_VO4_C,
+};
+
+static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_HP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of ACTIVE_LP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LSLP_HP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_DSLP_DBG[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_DBG,
+};
+
+static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of DSLP_LP_DBIAS,
+};
+
+static const esp_efuse_desc_t WR_DIS_LP_DCDC_DBIAS_VOL_GAP[] = {
+    {EFUSE_BLK0, 20, 1}, 	 // [] wr_dis of LP_DCDC_DBIAS_VOL_GAP,
+};
+
 static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
     {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of OPTIONAL_UNIQUE_ID,
 };
 
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC2_AVE_INITCODE_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC2_AVE_INITCODE_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC2_AVE_INITCODE_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC2_AVE_INITCODE_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 21, 1}, 	 // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
+};
+
 static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
     {EFUSE_BLK0, 22, 1}, 	 // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
 };
@@ -327,6 +439,82 @@ static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = {
     {EFUSE_BLK0, 29, 1}, 	 // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
 };
 
+static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_HI_DOUT_ATTEN3,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK0, 29, 1}, 	 // [] wr_dis of TEMPERATURE_SENSOR,
+};
+
 static const esp_efuse_desc_t WR_DIS_USB_DEVICE_EXCHG_PINS[] = {
     {EFUSE_BLK0, 30, 1}, 	 // [] wr_dis of USB_DEVICE_EXCHG_PINS,
 };
@@ -375,6 +563,82 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
     {EFUSE_BLK0, 38, 1}, 	 // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
 };
 
+static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_HI_DOUT_ATTEN0,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_HI_DOUT_ATTEN1,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_HI_DOUT_ATTEN2,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_HI_DOUT_ATTEN3,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF,
+};
+
+static const esp_efuse_desc_t RD_DIS_TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK0, 38, 1}, 	 // [] rd_dis of TEMPERATURE_SENSOR,
+};
+
 static const esp_efuse_desc_t USB_DEVICE_EXCHG_PINS[] = {
     {EFUSE_BLK0, 39, 1}, 	 // [] Enable usb device exchange pins of D+ and D-,
 };
@@ -664,10 +928,122 @@ static const esp_efuse_desc_t PKG_VERSION[] = {
     {EFUSE_BLK1, 84, 3}, 	 // [] Package version,
 };
 
+static const esp_efuse_desc_t LDO_VO1_DREF[] = {
+    {EFUSE_BLK1, 88, 4}, 	 // [] Output VO1 parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO2_DREF[] = {
+    {EFUSE_BLK1, 92, 4}, 	 // [] Output VO2 parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO1_MUL[] = {
+    {EFUSE_BLK1, 96, 3}, 	 // [] Output VO1 parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO2_MUL[] = {
+    {EFUSE_BLK1, 99, 3}, 	 // [] Output VO2 parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO3_K[] = {
+    {EFUSE_BLK1, 102, 8}, 	 // [] Output VO3 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO3_VOS[] = {
+    {EFUSE_BLK1, 110, 6}, 	 // [] Output VO3 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO3_C[] = {
+    {EFUSE_BLK1, 116, 6}, 	 // [] Output VO3 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO4_K[] = {
+    {EFUSE_BLK1, 122, 8}, 	 // [] Output VO4 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO4_VOS[] = {
+    {EFUSE_BLK1, 130, 6}, 	 // [] Output VO4 calibration parameter,
+};
+
+static const esp_efuse_desc_t LDO_VO4_C[] = {
+    {EFUSE_BLK1, 136, 6}, 	 // [] Output VO4 calibration parameter,
+};
+
+static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = {
+    {EFUSE_BLK1, 144, 4}, 	 // [] Active HP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = {
+    {EFUSE_BLK1, 148, 4}, 	 // [] Active LP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t LSLP_HP_DBIAS[] = {
+    {EFUSE_BLK1, 152, 4}, 	 // [] LSLP HP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t DSLP_DBG[] = {
+    {EFUSE_BLK1, 156, 4}, 	 // [] DSLP BDG of fixed voltage,
+};
+
+static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
+    {EFUSE_BLK1, 160, 5}, 	 // [] DSLP LP DBIAS of fixed voltage,
+};
+
+static const esp_efuse_desc_t LP_DCDC_DBIAS_VOL_GAP[] = {
+    {EFUSE_BLK1, 165, 5}, 	 // [] DBIAS gap between LP and DCDC,
+};
+
 static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
     {EFUSE_BLK2, 0, 128}, 	 // [] Optional unique 128-bit ID,
 };
 
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK2, 128, 10}, 	 // [] Average initcode of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK2, 138, 10}, 	 // [] Average initcode of ADC1 atten1,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK2, 148, 10}, 	 // [] Average initcode of ADC1 atten2,
+};
+
+static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK2, 158, 10}, 	 // [] Average initcode of ADC1 atten3,
+};
+
+static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN0[] = {
+    {EFUSE_BLK2, 168, 10}, 	 // [] Average initcode of ADC2 atten0,
+};
+
+static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN1[] = {
+    {EFUSE_BLK2, 178, 10}, 	 // [] Average initcode of ADC2 atten1,
+};
+
+static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN2[] = {
+    {EFUSE_BLK2, 188, 10}, 	 // [] Average initcode of ADC2 atten2,
+};
+
+static const esp_efuse_desc_t ADC2_AVE_INITCODE_ATTEN3[] = {
+    {EFUSE_BLK2, 198, 10}, 	 // [] Average initcode of ADC2 atten3,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK2, 208, 10}, 	 // [] HI_DOUT of ADC1 atten0,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK2, 218, 10}, 	 // [] HI_DOUT of ADC1 atten1,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK2, 228, 10}, 	 // [] HI_DOUT of ADC1 atten2,
+};
+
+static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK2, 238, 10}, 	 // [] HI_DOUT of ADC1 atten3,
+};
+
 static const esp_efuse_desc_t USER_DATA[] = {
     {EFUSE_BLK3, 0, 256}, 	 // [BLOCK_USR_DATA] User data,
 };
@@ -700,8 +1076,80 @@ static const esp_efuse_desc_t KEY5[] = {
     {EFUSE_BLK9, 0, 256}, 	 // [BLOCK_KEY5] Key5 or user data,
 };
 
-static const esp_efuse_desc_t SYS_DATA_PART2[] = {
-    {EFUSE_BLK10, 0, 256}, 	 // [BLOCK_SYS_DATA2] System data part 2 (reserved),
+static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN0[] = {
+    {EFUSE_BLK10, 0, 10}, 	 // [] HI_DOUT of ADC2 atten0,
+};
+
+static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN1[] = {
+    {EFUSE_BLK10, 10, 10}, 	 // [] HI_DOUT of ADC2 atten1,
+};
+
+static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN2[] = {
+    {EFUSE_BLK10, 20, 10}, 	 // [] HI_DOUT of ADC2 atten2,
+};
+
+static const esp_efuse_desc_t ADC2_HI_DOUT_ATTEN3[] = {
+    {EFUSE_BLK10, 30, 10}, 	 // [] HI_DOUT of ADC2 atten3,
+};
+
+static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 40, 4}, 	 // [] Gap between ADC1_ch0 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 44, 4}, 	 // [] Gap between ADC1_ch1 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 48, 4}, 	 // [] Gap between ADC1_ch2 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 52, 4}, 	 // [] Gap between ADC1_ch3 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 56, 4}, 	 // [] Gap between ADC1_ch4 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 60, 4}, 	 // [] Gap between ADC1_ch5 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 64, 4}, 	 // [] Gap between ADC1_ch6 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 68, 4}, 	 // [] Gap between ADC1_ch7 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 72, 4}, 	 // [] Gap between ADC2_ch0 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 76, 4}, 	 // [] Gap between ADC2_ch1 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 80, 4}, 	 // [] Gap between ADC2_ch2 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 84, 4}, 	 // [] Gap between ADC2_ch3 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 88, 4}, 	 // [] Gap between ADC2_ch4 and average initcode,
+};
+
+static const esp_efuse_desc_t ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    {EFUSE_BLK10, 92, 4}, 	 // [] Gap between ADC2_ch5 and average initcode,
+};
+
+static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = {
+    {EFUSE_BLK10, 96, 9}, 	 // [] Temperature calibration data,
 };
 
 
@@ -1048,83 +1496,318 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
-    &WR_DIS_OPTIONAL_UNIQUE_ID[0],    		// [] wr_dis of OPTIONAL_UNIQUE_ID
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[] = {
+    &WR_DIS_LDO_VO1_DREF[0],    		// [] wr_dis of LDO_VO1_DREF
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
-    &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[] = {
+    &WR_DIS_LDO_VO2_DREF[0],    		// [] wr_dis of LDO_VO2_DREF
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = {
-    &WR_DIS_CUSTOM_MAC[0],    		// [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[] = {
+    &WR_DIS_LDO_VO1_MUL[0],    		// [] wr_dis of LDO_VO1_MUL
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = {
-    &WR_DIS_BLOCK_KEY0[0],    		// [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[] = {
+    &WR_DIS_LDO_VO2_MUL[0],    		// [] wr_dis of LDO_VO2_MUL
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = {
-    &WR_DIS_BLOCK_KEY1[0],    		// [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[] = {
+    &WR_DIS_LDO_VO3_K[0],    		// [] wr_dis of LDO_VO3_K
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = {
-    &WR_DIS_BLOCK_KEY2[0],    		// [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[] = {
+    &WR_DIS_LDO_VO3_VOS[0],    		// [] wr_dis of LDO_VO3_VOS
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = {
-    &WR_DIS_BLOCK_KEY3[0],    		// [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[] = {
+    &WR_DIS_LDO_VO3_C[0],    		// [] wr_dis of LDO_VO3_C
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = {
-    &WR_DIS_BLOCK_KEY4[0],    		// [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[] = {
+    &WR_DIS_LDO_VO4_K[0],    		// [] wr_dis of LDO_VO4_K
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = {
-    &WR_DIS_BLOCK_KEY5[0],    		// [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[] = {
+    &WR_DIS_LDO_VO4_VOS[0],    		// [] wr_dis of LDO_VO4_VOS
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
-    &WR_DIS_BLOCK_SYS_DATA2[0],    		// [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[] = {
+    &WR_DIS_LDO_VO4_C[0],    		// [] wr_dis of LDO_VO4_C
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[] = {
-    &WR_DIS_USB_DEVICE_EXCHG_PINS[0],    		// [] wr_dis of USB_DEVICE_EXCHG_PINS
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = {
+    &WR_DIS_ACTIVE_HP_DBIAS[0],    		// [] wr_dis of ACTIVE_HP_DBIAS
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[] = {
-    &WR_DIS_USB_OTG11_EXCHG_PINS[0],    		// [] wr_dis of USB_OTG11_EXCHG_PINS
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = {
+    &WR_DIS_ACTIVE_LP_DBIAS[0],    		// [] wr_dis of ACTIVE_LP_DBIAS
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = {
-    &WR_DIS_USB_PHY_SEL[0],    		// [] wr_dis of USB_PHY_SEL
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = {
+    &WR_DIS_LSLP_HP_DBIAS[0],    		// [] wr_dis of LSLP_HP_DBIAS
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
-    &WR_DIS_SOFT_DIS_JTAG[0],    		// [] wr_dis of SOFT_DIS_JTAG
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[] = {
+    &WR_DIS_DSLP_DBG[0],    		// [] wr_dis of DSLP_DBG
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
-    &RD_DIS[0],    		// [] Disable reading from BlOCK4-10
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
+    &WR_DIS_DSLP_LP_DBIAS[0],    		// [] wr_dis of DSLP_LP_DBIAS
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = {
-    &RD_DIS_BLOCK_KEY0[0],    		// [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[] = {
+    &WR_DIS_LP_DCDC_DBIAS_VOL_GAP[0],    		// [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
+    &WR_DIS_OPTIONAL_UNIQUE_ID[0],    		// [] wr_dis of OPTIONAL_UNIQUE_ID
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
+    &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0],    		// [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[] = {
+    &WR_DIS_ADC2_AVE_INITCODE_ATTEN0[0],    		// [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[] = {
+    &WR_DIS_ADC2_AVE_INITCODE_ATTEN1[0],    		// [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[] = {
+    &WR_DIS_ADC2_AVE_INITCODE_ATTEN2[0],    		// [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[] = {
+    &WR_DIS_ADC2_AVE_INITCODE_ATTEN3[0],    		// [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN0[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN1[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN2[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
+    &WR_DIS_ADC1_HI_DOUT_ATTEN3[0],    		// [] wr_dis of ADC1_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
+    &WR_DIS_BLOCK_USR_DATA[0],    		// [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = {
+    &WR_DIS_CUSTOM_MAC[0],    		// [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = {
+    &WR_DIS_BLOCK_KEY0[0],    		// [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = {
+    &WR_DIS_BLOCK_KEY1[0],    		// [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = {
+    &WR_DIS_BLOCK_KEY2[0],    		// [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = {
+    &WR_DIS_BLOCK_KEY3[0],    		// [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = {
+    &WR_DIS_BLOCK_KEY4[0],    		// [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = {
+    &WR_DIS_BLOCK_KEY5[0],    		// [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
+    &WR_DIS_BLOCK_SYS_DATA2[0],    		// [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[] = {
+    &WR_DIS_ADC2_HI_DOUT_ATTEN0[0],    		// [] wr_dis of ADC2_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[] = {
+    &WR_DIS_ADC2_HI_DOUT_ATTEN1[0],    		// [] wr_dis of ADC2_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[] = {
+    &WR_DIS_ADC2_HI_DOUT_ATTEN2[0],    		// [] wr_dis of ADC2_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[] = {
+    &WR_DIS_ADC2_HI_DOUT_ATTEN3[0],    		// [] wr_dis of ADC2_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = {
+    &WR_DIS_TEMPERATURE_SENSOR[0],    		// [] wr_dis of TEMPERATURE_SENSOR
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[] = {
+    &WR_DIS_USB_DEVICE_EXCHG_PINS[0],    		// [] wr_dis of USB_DEVICE_EXCHG_PINS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[] = {
+    &WR_DIS_USB_OTG11_EXCHG_PINS[0],    		// [] wr_dis of USB_OTG11_EXCHG_PINS
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = {
+    &WR_DIS_USB_PHY_SEL[0],    		// [] wr_dis of USB_PHY_SEL
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
+    &WR_DIS_SOFT_DIS_JTAG[0],    		// [] wr_dis of SOFT_DIS_JTAG
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
+    &RD_DIS[0],    		// [] Disable reading from BlOCK4-10
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = {
+    &RD_DIS_BLOCK_KEY0[0],    		// [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
     NULL
 };
 
@@ -1158,6 +1841,101 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[] = {
+    &RD_DIS_ADC2_HI_DOUT_ATTEN0[0],    		// [] rd_dis of ADC2_HI_DOUT_ATTEN0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[] = {
+    &RD_DIS_ADC2_HI_DOUT_ATTEN1[0],    		// [] rd_dis of ADC2_HI_DOUT_ATTEN1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[] = {
+    &RD_DIS_ADC2_HI_DOUT_ATTEN2[0],    		// [] rd_dis of ADC2_HI_DOUT_ATTEN2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[] = {
+    &RD_DIS_ADC2_HI_DOUT_ATTEN3[0],    		// [] rd_dis of ADC2_HI_DOUT_ATTEN3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[] = {
+    &RD_DIS_TEMPERATURE_SENSOR[0],    		// [] rd_dis of TEMPERATURE_SENSOR
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[] = {
     &USB_DEVICE_EXCHG_PINS[0],    		// [] Enable usb device exchange pins of D+ and D-
     NULL
@@ -1518,11 +2296,151 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[] = {
+    &LDO_VO1_DREF[0],    		// [] Output VO1 parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[] = {
+    &LDO_VO2_DREF[0],    		// [] Output VO2 parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[] = {
+    &LDO_VO1_MUL[0],    		// [] Output VO1 parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[] = {
+    &LDO_VO2_MUL[0],    		// [] Output VO2 parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[] = {
+    &LDO_VO3_K[0],    		// [] Output VO3 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[] = {
+    &LDO_VO3_VOS[0],    		// [] Output VO3 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[] = {
+    &LDO_VO3_C[0],    		// [] Output VO3 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[] = {
+    &LDO_VO4_K[0],    		// [] Output VO4 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[] = {
+    &LDO_VO4_VOS[0],    		// [] Output VO4 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[] = {
+    &LDO_VO4_C[0],    		// [] Output VO4 calibration parameter
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = {
+    &ACTIVE_HP_DBIAS[0],    		// [] Active HP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = {
+    &ACTIVE_LP_DBIAS[0],    		// [] Active LP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = {
+    &LSLP_HP_DBIAS[0],    		// [] LSLP HP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[] = {
+    &DSLP_DBG[0],    		// [] DSLP BDG of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
+    &DSLP_LP_DBIAS[0],    		// [] DSLP LP DBIAS of fixed voltage
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[] = {
+    &LP_DCDC_DBIAS_VOL_GAP[0],    		// [] DBIAS gap between LP and DCDC
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
     &OPTIONAL_UNIQUE_ID[0],    		// [] Optional unique 128-bit ID
     NULL
 };
 
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
+    &ADC1_AVE_INITCODE_ATTEN0[0],    		// [] Average initcode of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
+    &ADC1_AVE_INITCODE_ATTEN1[0],    		// [] Average initcode of ADC1 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
+    &ADC1_AVE_INITCODE_ATTEN2[0],    		// [] Average initcode of ADC1 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
+    &ADC1_AVE_INITCODE_ATTEN3[0],    		// [] Average initcode of ADC1 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[] = {
+    &ADC2_AVE_INITCODE_ATTEN0[0],    		// [] Average initcode of ADC2 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[] = {
+    &ADC2_AVE_INITCODE_ATTEN1[0],    		// [] Average initcode of ADC2 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[] = {
+    &ADC2_AVE_INITCODE_ATTEN2[0],    		// [] Average initcode of ADC2 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[] = {
+    &ADC2_AVE_INITCODE_ATTEN3[0],    		// [] Average initcode of ADC2 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
+    &ADC1_HI_DOUT_ATTEN0[0],    		// [] HI_DOUT of ADC1 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
+    &ADC1_HI_DOUT_ATTEN1[0],    		// [] HI_DOUT of ADC1 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
+    &ADC1_HI_DOUT_ATTEN2[0],    		// [] HI_DOUT of ADC1 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
+    &ADC1_HI_DOUT_ATTEN3[0],    		// [] HI_DOUT of ADC1 atten3
+    NULL
+};
+
 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
     &USER_DATA[0],    		// [BLOCK_USR_DATA] User data
     NULL
@@ -1563,7 +2481,97 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
-    &SYS_DATA_PART2[0],    		// [BLOCK_SYS_DATA2] System data part 2 (reserved)
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[] = {
+    &ADC2_HI_DOUT_ATTEN0[0],    		// [] HI_DOUT of ADC2 atten0
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[] = {
+    &ADC2_HI_DOUT_ATTEN1[0],    		// [] HI_DOUT of ADC2 atten1
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[] = {
+    &ADC2_HI_DOUT_ATTEN2[0],    		// [] HI_DOUT of ADC2 atten2
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[] = {
+    &ADC2_HI_DOUT_ATTEN3[0],    		// [] HI_DOUT of ADC2 atten3
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch0 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch1 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch2 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch3 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch4 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch5 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH6_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch6 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[] = {
+    &ADC1_CH7_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC1_ch7 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH0_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch0 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH1_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch1 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH2_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch2 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH3_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch3 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH4_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch4 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[] = {
+    &ADC2_CH5_ATTEN0_INITCODE_DIFF[0],    		// [] Gap between ADC2_ch5 and average initcode
+    NULL
+};
+
+const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = {
+    &TEMPERATURE_SENSOR[0],    		// [] Temperature calibration data
     NULL
 };
diff --git a/components/efuse/esp32p4/esp_efuse_table.csv b/components/efuse/esp32p4/esp_efuse_table.csv
index 7cd373599cb..e07ef0bd628 100644
--- a/components/efuse/esp32p4/esp_efuse_table.csv
+++ b/components/efuse/esp32p4/esp_efuse_table.csv
@@ -9,7 +9,7 @@
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# This file was generated by regtools.py based on the efuses.yaml file with the version: d4a48929387e281bd05db8cfb3a85f60
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 73787d3f5ae45b80abca925a7562120b
 
 WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
 WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
@@ -79,7 +79,35 @@ WR_DIS.TEMP,                                     EFUSE_BLK0,  20,   1, [] wr_dis
 WR_DIS.PSRAM_VENDOR,                             EFUSE_BLK0,  20,   1, [] wr_dis of PSRAM_VENDOR
 WR_DIS.PKG_VERSION,                              EFUSE_BLK0,  20,   1, [] wr_dis of PKG_VERSION
 WR_DIS.SYS_DATA_PART1,                           EFUSE_BLK0,  21,   1, [] wr_dis of BLOCK2
+WR_DIS.LDO_VO1_DREF,                             EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO1_DREF
+WR_DIS.LDO_VO2_DREF,                             EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO2_DREF
+WR_DIS.LDO_VO1_MUL,                              EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO1_MUL
+WR_DIS.LDO_VO2_MUL,                              EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO2_MUL
+WR_DIS.LDO_VO3_K,                                EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO3_K
+WR_DIS.LDO_VO3_VOS,                              EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO3_VOS
+WR_DIS.LDO_VO3_C,                                EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO3_C
+WR_DIS.LDO_VO4_K,                                EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO4_K
+WR_DIS.LDO_VO4_VOS,                              EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO4_VOS
+WR_DIS.LDO_VO4_C,                                EFUSE_BLK0,  20,   1, [] wr_dis of LDO_VO4_C
+WR_DIS.ACTIVE_HP_DBIAS,                          EFUSE_BLK0,  20,   1, [] wr_dis of ACTIVE_HP_DBIAS
+WR_DIS.ACTIVE_LP_DBIAS,                          EFUSE_BLK0,  20,   1, [] wr_dis of ACTIVE_LP_DBIAS
+WR_DIS.LSLP_HP_DBIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of LSLP_HP_DBIAS
+WR_DIS.DSLP_DBG,                                 EFUSE_BLK0,  20,   1, [] wr_dis of DSLP_DBG
+WR_DIS.DSLP_LP_DBIAS,                            EFUSE_BLK0,  20,   1, [] wr_dis of DSLP_LP_DBIAS
+WR_DIS.LP_DCDC_DBIAS_VOL_GAP,                    EFUSE_BLK0,  20,   1, [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
 WR_DIS.OPTIONAL_UNIQUE_ID,                       EFUSE_BLK0,  21,   1, [] wr_dis of OPTIONAL_UNIQUE_ID
+WR_DIS.ADC1_AVE_INITCODE_ATTEN0,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
+WR_DIS.ADC1_AVE_INITCODE_ATTEN1,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
+WR_DIS.ADC1_AVE_INITCODE_ATTEN2,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
+WR_DIS.ADC1_AVE_INITCODE_ATTEN3,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
+WR_DIS.ADC2_AVE_INITCODE_ATTEN0,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
+WR_DIS.ADC2_AVE_INITCODE_ATTEN1,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
+WR_DIS.ADC2_AVE_INITCODE_ATTEN2,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
+WR_DIS.ADC2_AVE_INITCODE_ATTEN3,                 EFUSE_BLK0,  21,   1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
+WR_DIS.ADC1_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
+WR_DIS.ADC1_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
+WR_DIS.ADC1_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
+WR_DIS.ADC1_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  21,   1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
 WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
 WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
 WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -89,6 +117,25 @@ WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.K
 WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
 WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
 WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+WR_DIS.ADC2_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_HI_DOUT_ATTEN0
+WR_DIS.ADC2_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_HI_DOUT_ATTEN1
+WR_DIS.ADC2_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_HI_DOUT_ATTEN2
+WR_DIS.ADC2_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_HI_DOUT_ATTEN3
+WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
+WR_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  29,   1, [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
+WR_DIS.TEMPERATURE_SENSOR,                       EFUSE_BLK0,  29,   1, [] wr_dis of TEMPERATURE_SENSOR
 WR_DIS.USB_DEVICE_EXCHG_PINS,                    EFUSE_BLK0,  30,   1, [] wr_dis of USB_DEVICE_EXCHG_PINS
 WR_DIS.USB_OTG11_EXCHG_PINS,                     EFUSE_BLK0,  30,   1, [] wr_dis of USB_OTG11_EXCHG_PINS
 WR_DIS.USB_PHY_SEL,                              EFUSE_BLK0,  30,   1, [] wr_dis of USB_PHY_SEL
@@ -101,6 +148,25 @@ RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.K
 RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
 RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
 RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
+RD_DIS.ADC2_HI_DOUT_ATTEN0,                      EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_HI_DOUT_ATTEN0
+RD_DIS.ADC2_HI_DOUT_ATTEN1,                      EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_HI_DOUT_ATTEN1
+RD_DIS.ADC2_HI_DOUT_ATTEN2,                      EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_HI_DOUT_ATTEN2
+RD_DIS.ADC2_HI_DOUT_ATTEN3,                      EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_HI_DOUT_ATTEN3
+RD_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
+RD_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF,            EFUSE_BLK0,  38,   1, [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
+RD_DIS.TEMPERATURE_SENSOR,                       EFUSE_BLK0,  38,   1, [] rd_dis of TEMPERATURE_SENSOR
 USB_DEVICE_EXCHG_PINS,                           EFUSE_BLK0,  39,   1, [] Enable usb device exchange pins of D+ and D-
 USB_OTG11_EXCHG_PINS,                            EFUSE_BLK0,  40,   1, [] Enable usb otg11 exchange pins of D+ and D-
 DIS_USB_JTAG,                                    EFUSE_BLK0,  41,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
@@ -177,7 +243,35 @@ PSRAM_CAP,                                       EFUSE_BLK1,  77,   3, [] PSRAM
 TEMP,                                            EFUSE_BLK1,  80,   2, [] Operating temperature of the ESP chip
 PSRAM_VENDOR,                                    EFUSE_BLK1,  82,   2, [] PSRAM vendor
 PKG_VERSION,                                     EFUSE_BLK1,  84,   3, [] Package version
+LDO_VO1_DREF,                                    EFUSE_BLK1,  88,   4, [] Output VO1 parameter
+LDO_VO2_DREF,                                    EFUSE_BLK1,  92,   4, [] Output VO2 parameter
+LDO_VO1_MUL,                                     EFUSE_BLK1,  96,   3, [] Output VO1 parameter
+LDO_VO2_MUL,                                     EFUSE_BLK1,  99,   3, [] Output VO2 parameter
+LDO_VO3_K,                                       EFUSE_BLK1, 102,   8, [] Output VO3 calibration parameter
+LDO_VO3_VOS,                                     EFUSE_BLK1, 110,   6, [] Output VO3 calibration parameter
+LDO_VO3_C,                                       EFUSE_BLK1, 116,   6, [] Output VO3 calibration parameter
+LDO_VO4_K,                                       EFUSE_BLK1, 122,   8, [] Output VO4 calibration parameter
+LDO_VO4_VOS,                                     EFUSE_BLK1, 130,   6, [] Output VO4 calibration parameter
+LDO_VO4_C,                                       EFUSE_BLK1, 136,   6, [] Output VO4 calibration parameter
+ACTIVE_HP_DBIAS,                                 EFUSE_BLK1, 144,   4, [] Active HP DBIAS of fixed voltage
+ACTIVE_LP_DBIAS,                                 EFUSE_BLK1, 148,   4, [] Active LP DBIAS of fixed voltage
+LSLP_HP_DBIAS,                                   EFUSE_BLK1, 152,   4, [] LSLP HP DBIAS of fixed voltage
+DSLP_DBG,                                        EFUSE_BLK1, 156,   4, [] DSLP BDG of fixed voltage
+DSLP_LP_DBIAS,                                   EFUSE_BLK1, 160,   5, [] DSLP LP DBIAS of fixed voltage
+LP_DCDC_DBIAS_VOL_GAP,                           EFUSE_BLK1, 165,   5, [] DBIAS gap between LP and DCDC
 OPTIONAL_UNIQUE_ID,                              EFUSE_BLK2,   0, 128, [] Optional unique 128-bit ID
+ADC1_AVE_INITCODE_ATTEN0,                        EFUSE_BLK2, 128,  10, [] Average initcode of ADC1 atten0
+ADC1_AVE_INITCODE_ATTEN1,                        EFUSE_BLK2, 138,  10, [] Average initcode of ADC1 atten1
+ADC1_AVE_INITCODE_ATTEN2,                        EFUSE_BLK2, 148,  10, [] Average initcode of ADC1 atten2
+ADC1_AVE_INITCODE_ATTEN3,                        EFUSE_BLK2, 158,  10, [] Average initcode of ADC1 atten3
+ADC2_AVE_INITCODE_ATTEN0,                        EFUSE_BLK2, 168,  10, [] Average initcode of ADC2 atten0
+ADC2_AVE_INITCODE_ATTEN1,                        EFUSE_BLK2, 178,  10, [] Average initcode of ADC2 atten1
+ADC2_AVE_INITCODE_ATTEN2,                        EFUSE_BLK2, 188,  10, [] Average initcode of ADC2 atten2
+ADC2_AVE_INITCODE_ATTEN3,                        EFUSE_BLK2, 198,  10, [] Average initcode of ADC2 atten3
+ADC1_HI_DOUT_ATTEN0,                             EFUSE_BLK2, 208,  10, [] HI_DOUT of ADC1 atten0
+ADC1_HI_DOUT_ATTEN1,                             EFUSE_BLK2, 218,  10, [] HI_DOUT of ADC1 atten1
+ADC1_HI_DOUT_ATTEN2,                             EFUSE_BLK2, 228,  10, [] HI_DOUT of ADC1 atten2
+ADC1_HI_DOUT_ATTEN3,                             EFUSE_BLK2, 238,  10, [] HI_DOUT of ADC1 atten3
 USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
 USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
 KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
@@ -186,4 +280,22 @@ KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KE
 KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
 KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
 KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
-SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
+ADC2_HI_DOUT_ATTEN0,                             EFUSE_BLK10,   0,  10, [] HI_DOUT of ADC2 atten0
+ADC2_HI_DOUT_ATTEN1,                             EFUSE_BLK10,  10,  10, [] HI_DOUT of ADC2 atten1
+ADC2_HI_DOUT_ATTEN2,                             EFUSE_BLK10,  20,  10, [] HI_DOUT of ADC2 atten2
+ADC2_HI_DOUT_ATTEN3,                             EFUSE_BLK10,  30,  10, [] HI_DOUT of ADC2 atten3
+ADC1_CH0_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  40,   4, [] Gap between ADC1_ch0 and average initcode
+ADC1_CH1_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  44,   4, [] Gap between ADC1_ch1 and average initcode
+ADC1_CH2_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  48,   4, [] Gap between ADC1_ch2 and average initcode
+ADC1_CH3_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  52,   4, [] Gap between ADC1_ch3 and average initcode
+ADC1_CH4_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  56,   4, [] Gap between ADC1_ch4 and average initcode
+ADC1_CH5_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  60,   4, [] Gap between ADC1_ch5 and average initcode
+ADC1_CH6_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  64,   4, [] Gap between ADC1_ch6 and average initcode
+ADC1_CH7_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  68,   4, [] Gap between ADC1_ch7 and average initcode
+ADC2_CH0_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  72,   4, [] Gap between ADC2_ch0 and average initcode
+ADC2_CH1_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  76,   4, [] Gap between ADC2_ch1 and average initcode
+ADC2_CH2_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  80,   4, [] Gap between ADC2_ch2 and average initcode
+ADC2_CH3_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  84,   4, [] Gap between ADC2_ch3 and average initcode
+ADC2_CH4_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  88,   4, [] Gap between ADC2_ch4 and average initcode
+ADC2_CH5_ATTEN0_INITCODE_DIFF,                   EFUSE_BLK10,  92,   4, [] Gap between ADC2_ch5 and average initcode
+TEMPERATURE_SENSOR,                              EFUSE_BLK10,  96,   9, [] Temperature calibration data
diff --git a/components/efuse/esp32p4/include/esp_efuse_table.h b/components/efuse/esp32p4/include/esp_efuse_table.h
index 9e82ad86301..8ccdd797109 100644
--- a/components/efuse/esp32p4/include/esp_efuse_table.h
+++ b/components/efuse/esp32p4/include/esp_efuse_table.h
@@ -10,7 +10,7 @@ extern "C" {
 
 #include "esp_efuse.h"
 
-// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b
+// md5_digest_table c56ed98dde7a08c8f70d57a01faba96a
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -92,7 +92,35 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
 #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -112,6 +140,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
 #define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
 #define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
@@ -131,6 +178,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
 #define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
 extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
 #define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
@@ -209,7 +275,35 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
 extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
 extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
 #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
 extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
@@ -227,8 +321,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
 #define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
 extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
 #define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
-extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
-#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
+extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
 
 #ifdef __cplusplus
 }
diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c
index b48f6b2010a..fb906cd4e71 100644
--- a/components/efuse/esp32s3/esp_efuse_table.c
+++ b/components/efuse/esp32s3/esp_efuse_table.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,7 +9,7 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table e0674ff40a1e124670c6eecf33410e76
+// md5_digest_table f8f32987a955792b4fe4534ea428268f
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -769,7 +769,8 @@ static const esp_efuse_desc_t FLASH_VENDOR[] = {
 };
 
 static const esp_efuse_desc_t PSRAM_CAP[] = {
-    {EFUSE_BLK1, 131, 2}, 	 // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"},
+    {EFUSE_BLK1, 131, 2}, 	 // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"},
+    {EFUSE_BLK1, 179, 1}, 	 // [] PSRAM capacity bit 3,
 };
 
 static const esp_efuse_desc_t PSRAM_TEMP[] = {
@@ -1869,7 +1870,8 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
-    &PSRAM_CAP[0],    		// [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}
+    &PSRAM_CAP[0],    		// [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"}
+    &PSRAM_CAP[1],    		// [] PSRAM capacity bit 3
     NULL
 };
 
diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv
index a55cfa2d595..a10c75587b9 100644
--- a/components/efuse/esp32s3/esp_efuse_table.csv
+++ b/components/efuse/esp32s3/esp_efuse_table.csv
@@ -9,7 +9,7 @@
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #
 
-# This file was generated by regtools.py based on the efuses.yaml file with the version: f75f74727101326a187188a23f4a6c70
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 7127dd097e72bb90d0b790d460993126
 
 WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
 WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
@@ -203,7 +203,8 @@ BLK_VERSION_MINOR,                               EFUSE_BLK1, 120,   3, [] BLK_VE
 FLASH_CAP,                                       EFUSE_BLK1, 123,   3, [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"}
 FLASH_TEMP,                                      EFUSE_BLK1, 126,   2, [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"}
 FLASH_VENDOR,                                    EFUSE_BLK1, 128,   3, [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"}
-PSRAM_CAP,                                       EFUSE_BLK1, 131,   2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}
+PSRAM_CAP,                                       EFUSE_BLK1, 131,   2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"}
+,                                                EFUSE_BLK1, 179,   1, [] PSRAM capacity bit 3
 PSRAM_TEMP,                                      EFUSE_BLK1, 133,   2, [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"}
 PSRAM_VENDOR,                                    EFUSE_BLK1, 135,   2, [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"}
 K_RTC_LDO,                                       EFUSE_BLK1, 141,   7, [] BLOCK1 K_RTC_LDO
diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h
index 5fb75b6872d..d43fba24026 100644
--- a/components/efuse/esp32s3/include/esp_efuse_table.h
+++ b/components/efuse/esp32s3/include/esp_efuse_table.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,7 @@ extern "C" {
 
 #include "esp_efuse.h"
 
-// md5_digest_table e0674ff40a1e124670c6eecf33410e76
+// md5_digest_table f8f32987a955792b4fe4534ea428268f
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
diff --git a/components/efuse/src/esp_efuse_api.c b/components/efuse/src/esp_efuse_api.c
index 64059f72a10..36c555435c5 100644
--- a/components/efuse/src/esp_efuse_api.c
+++ b/components/efuse/src/esp_efuse_api.c
@@ -13,7 +13,7 @@
 
 const static char *TAG = "efuse";
 
-#if defined(BOOTLOADER_BUILD)
+#ifdef NON_OS_BUILD
 #define EFUSE_LOCK_ACQUIRE_RECURSIVE()
 #define EFUSE_LOCK_RELEASE_RECURSIVE()
 #else
@@ -39,11 +39,11 @@ esp_err_t esp_efuse_read_field_blob(const esp_efuse_desc_t* field[], void* dst,
         do {
             memset((uint8_t *)dst, 0, esp_efuse_utility_get_number_of_items(dst_size_bits, 8));
             err = esp_efuse_utility_process(field, dst, dst_size_bits, esp_efuse_utility_fill_buff);
-#ifndef BOOTLOADER_BUILD
+#ifndef NON_OS_BUILD
             if (err == ESP_ERR_DAMAGED_READING) {
                 vTaskDelay(1);
             }
-#endif // BOOTLOADER_BUILD
+#endif // NON_OS_BUILD
         } while (err == ESP_ERR_DAMAGED_READING);
     }
     return err;
@@ -67,11 +67,11 @@ esp_err_t esp_efuse_read_field_cnt(const esp_efuse_desc_t* field[], size_t* out_
         do {
             *out_cnt = 0;
             err = esp_efuse_utility_process(field, out_cnt, 0, esp_efuse_utility_count_once);
-#ifndef BOOTLOADER_BUILD
+#ifndef NON_OS_BUILD
             if (err == ESP_ERR_DAMAGED_READING) {
                 vTaskDelay(1);
             }
-#endif // BOOTLOADER_BUILD
+#endif // NON_OS_BUILD
         } while (err == ESP_ERR_DAMAGED_READING);
     }
     return err;
diff --git a/components/efuse/src/esp_efuse_startup.c b/components/efuse/src/esp_efuse_startup.c
index 8a3a746b34e..488e6b37e56 100644
--- a/components/efuse/src/esp_efuse_startup.c
+++ b/components/efuse/src/esp_efuse_startup.c
@@ -63,7 +63,20 @@ static void init_efuse_virtual(void)
     // esp_flash must be initialized in advance because here we read the efuse partition.
     const esp_partition_t *efuse_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_EFUSE_EM, NULL);
     if (efuse_partition) {
+        /*
+         * esp_partition_find_first triggers the reading of partitions from the partition table.
+         * However, since the efuses have not yet been read from the 'efuse_em' partition,
+         * the encryption flag for these partitions is set to false.
+         *
+         * Unloading all partitions ensures that the next time the esp_partition API is called,
+         * the efuses will have been read, and the correct encryption flags will be applied.
+         */
         esp_efuse_init_virtual_mode_in_flash(efuse_partition->address, efuse_partition->size);
+        esp_partition_unload_all();
+
+        // Use volatile to ensure this function call is not optimized out and the partition table will be loaded again.
+        volatile const esp_partition_t *dummy_partition = esp_partition_find_first(ESP_PARTITION_TYPE_ANY, ESP_PARTITION_SUBTYPE_ANY, NULL);
+        (void) dummy_partition;
     }
 #else // !CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
     // For efuse virtual mode we need to seed virtual efuses from efuse_regs.
diff --git a/components/esp_adc/adc_common.c b/components/esp_adc/adc_common.c
index d760a1cff85..1b5a8d599e0 100644
--- a/components/esp_adc/adc_common.c
+++ b/components/esp_adc/adc_common.c
@@ -15,6 +15,7 @@
 #include "driver/gpio.h"
 #include "hal/adc_hal.h"
 #include "hal/adc_hal_common.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "soc/adc_periph.h"
 
 static const char *TAG = "adc_common";
@@ -57,6 +58,7 @@ esp_err_t adc_channel_to_io(adc_unit_t unit_id, adc_channel_t channel, int * con
 static __attribute__((constructor)) void adc_hw_calibration(void)
 {
     adc_apb_periph_claim();
+    ANALOG_CLOCK_ENABLE();
     //Calculate all ICode
     for (int i = 0; i < SOC_ADC_PERIPH_NUM; i++) {
         adc_hal_calibration_init(i);
@@ -74,5 +76,6 @@ static __attribute__((constructor)) void adc_hw_calibration(void)
 #endif
         }
     }
+    ANALOG_CLOCK_DISABLE();
 }
 #endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
diff --git a/components/esp_adc/adc_continuous.c b/components/esp_adc/adc_continuous.c
index 8ef8bef9171..1a92568ff53 100644
--- a/components/esp_adc/adc_continuous.c
+++ b/components/esp_adc/adc_continuous.c
@@ -24,6 +24,7 @@
 #include "freertos/timers.h"
 #include "freertos/ringbuf.h"
 #include "esp_private/esp_clk_tree_common.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/adc_private.h"
 #include "esp_private/adc_share_hw_ctrl.h"
@@ -242,11 +243,6 @@ esp_err_t adc_continuous_new_handle(const adc_continuous_handle_cfg_t *hdl_confi
 
     adc_apb_periph_claim();
 
-#if SOC_ADC_CALIBRATION_V1_SUPPORTED
-    adc_hal_calibration_init(ADC_UNIT_1);
-    adc_hal_calibration_init(ADC_UNIT_2);
-#endif  //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
-
     return ret;
 
 cleanup:
@@ -259,6 +255,12 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
     ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_STATE, ADC_TAG, "The driver isn't initialised");
     ESP_RETURN_ON_FALSE(handle->fsm == ADC_FSM_INIT, ESP_ERR_INVALID_STATE, ADC_TAG, "ADC continuous mode isn't in the init state, it's started already");
 
+    ANALOG_CLOCK_ENABLE();
+#if SOC_ADC_CALIBRATION_V1_SUPPORTED
+    adc_hal_calibration_init(ADC_UNIT_1);
+    adc_hal_calibration_init(ADC_UNIT_2);
+#endif  //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
+
     //reset ADC digital part to reset ADC sampling EOF counter
     ADC_BUS_CLK_ATOMIC() {
         adc_ll_reset_register();
@@ -294,6 +296,22 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle)
     }
 #endif  //#if SOC_ADC_ARBITER_SUPPORTED
 
+#if SOC_ADC_MONITOR_SUPPORTED
+    adc_ll_digi_monitor_clear_intr();
+    for (int i = 0; i < SOC_ADC_DIGI_MONITOR_NUM; i++) {
+        adc_monitor_t *monitor_ctx = handle->adc_monitor[i];
+        if (monitor_ctx) {
+            // config monitor hardware
+            adc_hal_digi_monitor_set_thres(monitor_ctx->monitor_id, monitor_ctx->config.adc_unit, monitor_ctx->config.channel, monitor_ctx->config.h_threshold, monitor_ctx->config.l_threshold);
+            // if monitor not enabled now, just using monitor api later
+            if (monitor_ctx->fsm == ADC_MONITOR_FSM_ENABLED) {
+                // restore the started FSM
+                adc_ll_digi_monitor_user_start(monitor_ctx->monitor_id, ((monitor_ctx->config.h_threshold >= 0) || (monitor_ctx->config.l_threshold >= 0)));
+            }
+        }
+    }
+#endif  //#if SOC_ADC_MONITOR_SUPPORTED
+
     if (handle->use_adc1) {
         adc_hal_set_controller(ADC_UNIT_1, ADC_HAL_CONTINUOUS_READ_MODE);
     }
@@ -356,6 +374,8 @@ esp_err_t adc_continuous_stop(adc_continuous_handle_t handle)
         ESP_RETURN_ON_ERROR(esp_pm_lock_release(handle->pm_lock), ADC_TAG, "release pm_lock failed");
     }
 
+    ANALOG_CLOCK_DISABLE();
+
     return ESP_OK;
 }
 
diff --git a/components/esp_adc/adc_monitor.c b/components/esp_adc/adc_monitor.c
index 768b46fac5f..025f13e9799 100644
--- a/components/esp_adc/adc_monitor.c
+++ b/components/esp_adc/adc_monitor.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -173,10 +173,6 @@ esp_err_t adc_new_continuous_monitor(adc_continuous_handle_t handle, const adc_m
         ESP_GOTO_ON_ERROR(adc_monitor_intr_alloc(), intr_err, MNTOR_TAG, "esp intr alloc failed");
     }
 
-    // config hardware
-    adc_ll_digi_monitor_clear_intr();
-    adc_ll_digi_monitor_set_thres(monitor_ctx->monitor_id, monitor_ctx->config.adc_unit, monitor_ctx->config.channel, monitor_ctx->config.h_threshold, monitor_ctx->config.l_threshold);
-
     *ret_handle = monitor_ctx;
     return ESP_OK;
 
@@ -191,7 +187,6 @@ esp_err_t adc_continuous_monitor_register_event_callbacks(adc_monitor_handle_t m
 {
     ESP_RETURN_ON_FALSE(monitor_handle && cbs, ESP_ERR_INVALID_ARG, MNTOR_TAG, "invalid argument: null pointer");
     ESP_RETURN_ON_FALSE(monitor_handle->fsm == ADC_MONITOR_FSM_INIT, ESP_ERR_INVALID_STATE, MNTOR_TAG, "monitor should be in init state");
-    ESP_RETURN_ON_FALSE(!(monitor_handle->cbs.on_over_high_thresh || monitor_handle->cbs.on_below_low_thresh), ESP_ERR_INVALID_STATE, MNTOR_TAG, "callbacks had been registered");
 #if CONFIG_IDF_TARGET_ESP32S2
     ESP_RETURN_ON_FALSE(!(cbs->on_below_low_thresh && cbs->on_over_high_thresh), ESP_ERR_NOT_SUPPORTED, MNTOR_TAG, "ESP32S2 support only one threshold");
 #endif
@@ -216,45 +211,31 @@ esp_err_t adc_continuous_monitor_register_event_callbacks(adc_monitor_handle_t m
 
 esp_err_t adc_continuous_monitor_enable(adc_monitor_handle_t monitor_handle)
 {
-    ESP_RETURN_ON_FALSE(monitor_handle, ESP_ERR_INVALID_ARG, MNTOR_TAG, "invalid argument: null pointer");
-    ESP_RETURN_ON_FALSE(monitor_handle->fsm == ADC_MONITOR_FSM_INIT, ESP_ERR_INVALID_STATE, MNTOR_TAG, "monitor should be in init state");
-
-    // enable peripheral intr_ena
-    if ((monitor_handle->config.h_threshold >= 0)) {
-        adc_ll_digi_monitor_enable_intr(monitor_handle->monitor_id, ADC_MONITOR_MODE_HIGH, true);
-    }
-    if ((monitor_handle->config.l_threshold >= 0)) {
-        adc_ll_digi_monitor_enable_intr(monitor_handle->monitor_id, ADC_MONITOR_MODE_LOW, true);
-    }
+    ESP_RETURN_ON_FALSE_ISR(monitor_handle, ESP_ERR_INVALID_ARG, MNTOR_TAG, "invalid argument: null pointer");
+    ESP_RETURN_ON_FALSE_ISR(monitor_handle->fsm == ADC_MONITOR_FSM_INIT, ESP_ERR_INVALID_STATE, MNTOR_TAG, "monitor should be in init state");
 
-    adc_ll_digi_monitor_user_start(monitor_handle->monitor_id, true);
+    // start monitor
+    adc_ll_digi_monitor_user_start(monitor_handle->monitor_id, ((monitor_handle->config.h_threshold >= 0) || (monitor_handle->config.l_threshold >= 0)));
     monitor_handle->fsm = ADC_MONITOR_FSM_ENABLED;
-    return esp_intr_enable(s_adc_monitor_platform.monitor_intr_handle);
+    return ESP_OK;
 }
 
 esp_err_t adc_continuous_monitor_disable(adc_monitor_handle_t monitor_handle)
 {
-    ESP_RETURN_ON_FALSE(monitor_handle, ESP_ERR_INVALID_ARG, MNTOR_TAG, "invalid argument: null pointer");
-    ESP_RETURN_ON_FALSE(monitor_handle->fsm == ADC_MONITOR_FSM_ENABLED, ESP_ERR_INVALID_STATE, MNTOR_TAG, "monitor not in running");
-
-    // disable peripheral intr_ena
-    if ((monitor_handle->config.h_threshold >= 0)) {
-        adc_ll_digi_monitor_enable_intr(monitor_handle->monitor_id, ADC_MONITOR_MODE_HIGH, false);
-    }
-    if ((monitor_handle->config.l_threshold >= 0)) {
-        adc_ll_digi_monitor_enable_intr(monitor_handle->monitor_id, ADC_MONITOR_MODE_LOW, false);
-    }
+    ESP_RETURN_ON_FALSE_ISR(monitor_handle, ESP_ERR_INVALID_ARG, MNTOR_TAG, "invalid argument: null pointer");
+    ESP_RETURN_ON_FALSE_ISR(monitor_handle->fsm == ADC_MONITOR_FSM_ENABLED, ESP_ERR_INVALID_STATE, MNTOR_TAG, "monitor not in running");
 
+    // stop monitor
     adc_ll_digi_monitor_user_start(monitor_handle->monitor_id, false);
     monitor_handle->fsm = ADC_MONITOR_FSM_INIT;
-    return esp_intr_disable(s_adc_monitor_platform.monitor_intr_handle);
+    return ESP_OK;
 }
 
 esp_err_t adc_del_continuous_monitor(adc_monitor_handle_t monitor_handle)
 {
     ESP_RETURN_ON_FALSE(monitor_handle, ESP_ERR_INVALID_ARG, MNTOR_TAG, "invalid argument: null pointer");
     ESP_RETURN_ON_FALSE((monitor_handle->fsm == ADC_MONITOR_FSM_INIT) && (s_adc_monitor_platform.continuous_ctx->fsm == ADC_FSM_INIT), \
-                        ESP_ERR_INVALID_STATE, MNTOR_TAG, "monitor and ADC continuous driver should all be in init state");
+                        ESP_ERR_INVALID_STATE, MNTOR_TAG, "monitor and ADC continuous driver should all stopped");
     ESP_RETURN_ON_ERROR(s_adc_monitor_release(monitor_handle), MNTOR_TAG, "monitor not find or isn't in use");
 
     for (int i = 0; i < SOC_ADC_DIGI_MONITOR_NUM; i++) {
@@ -265,7 +246,7 @@ esp_err_t adc_del_continuous_monitor(adc_monitor_handle_t monitor_handle)
         }
     }
 
-    // If no monitor is using, the release intr handle as well
+    // If no monitor is using, then release intr handle as well
     ESP_RETURN_ON_ERROR(esp_intr_free(s_adc_monitor_platform.monitor_intr_handle), MNTOR_TAG, "esp intr release failed\n");
     s_adc_monitor_platform.monitor_intr_handle = NULL;
     free(monitor_handle);
diff --git a/components/esp_adc/adc_oneshot.c b/components/esp_adc/adc_oneshot.c
index 782a1c5338b..4c3f2d17c0d 100644
--- a/components/esp_adc/adc_oneshot.c
+++ b/components/esp_adc/adc_oneshot.c
@@ -23,6 +23,7 @@
 #include "esp_clk_tree.h"
 #include "esp_private/adc_private.h"
 #include "esp_private/adc_share_hw_ctrl.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_private/sar_periph_ctrl.h"
 #include "esp_private/esp_clk_tree_common.h"
 #include "esp_private/esp_sleep_internal.h"
@@ -192,6 +193,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan,
 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
     esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true);
 #endif
+    ANALOG_CLOCK_ENABLE();
     adc_oneshot_hal_setup(&(handle->hal), chan);
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_atten_t atten = adc_ll_get_atten(handle->unit_id, chan);
@@ -200,6 +202,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan,
 #endif  // SOC_ADC_CALIBRATION_V1_SUPPORTED
     bool valid = false;
     valid = adc_oneshot_hal_convert(&(handle->hal), out_raw);
+    ANALOG_CLOCK_DISABLE();
 
     portEXIT_CRITICAL(&rtc_spinlock);
     adc_lock_release(handle->unit_id);
@@ -218,6 +221,7 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c
 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
     esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true);
 #endif
+    ANALOG_CLOCK_ENABLE();
     adc_oneshot_hal_setup(&(handle->hal), chan);
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_atten_t atten = adc_ll_get_atten(handle->unit_id, chan);
@@ -225,6 +229,7 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c
     adc_set_hw_calibration_code(handle->unit_id, atten);
 #endif
     adc_oneshot_hal_convert(&(handle->hal), out_raw);
+    ANALOG_CLOCK_DISABLE();
 
     portEXIT_CRITICAL_SAFE(&rtc_spinlock);
 
diff --git a/components/esp_adc/include/esp_adc/adc_monitor.h b/components/esp_adc/include/esp_adc/adc_monitor.h
index 8066771a2e7..946967e2712 100644
--- a/components/esp_adc/include/esp_adc/adc_monitor.h
+++ b/components/esp_adc/include/esp_adc/adc_monitor.h
@@ -65,7 +65,8 @@ typedef struct {
 esp_err_t adc_new_continuous_monitor(adc_continuous_handle_t handle, const adc_monitor_config_t *monitor_cfg, adc_monitor_handle_t *ret_handle);
 
 /**
- * @brief Register threshold interrupt callbacks for allocated monitor.
+ * @brief Register/Unregister threshold interrupt callbacks for allocated monitor.
+ *        Passing `cbs` contain the NULL `over_high/below_low` will unregister relative callbacks.
  *
  * @param[in]  monitor_handle       Monitor handle
  * @param[in]  cbs                  Pointer to a adc_monitor_evt_cbs_t struct
diff --git a/components/esp_adc/test_apps/.build-test-rules.yml b/components/esp_adc/test_apps/.build-test-rules.yml
index 6a284fa6d2c..83598edd3a0 100644
--- a/components/esp_adc/test_apps/.build-test-rules.yml
+++ b/components/esp_adc/test_apps/.build-test-rules.yml
@@ -8,6 +8,9 @@ components/esp_adc/test_apps/adc:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: not runners for ESP32P4 ADC # TODO: IDF-9573
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: not runners for ESP32C61 ADC
   depends_components:
     - esp_adc
     - esp_driver_gpio
diff --git a/components/esp_adc/test_apps/adc/README.md b/components/esp_adc/test_apps/adc/README.md
index 3a502b1f86f..7b96141437e 100644
--- a/components/esp_adc/test_apps/adc/README.md
+++ b/components/esp_adc/test_apps/adc/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
diff --git a/components/esp_adc/test_apps/adc/main/test_adc.c b/components/esp_adc/test_apps/adc/main/test_adc.c
index 19d1c836b0a..0180710d0e2 100644
--- a/components/esp_adc/test_apps/adc/main/test_adc.c
+++ b/components/esp_adc/test_apps/adc/main/test_adc.c
@@ -382,9 +382,6 @@ TEST_CASE("ADC continuous monitor init_deinit", "[adc]")
     TEST_ESP_OK(adc_del_continuous_monitor(monitor_handle_2));
     TEST_ESP_ERR(ESP_ERR_INVALID_ARG, adc_del_continuous_monitor(monitor_handle_3));
 
-    //try register cbs again
-    TEST_ESP_ERR(ESP_ERR_INVALID_STATE, adc_continuous_monitor_register_event_callbacks(monitor_handle, &monitor_cb, &monitor_cb));
-
     //try delete it when adc is running but monitor not running
     TEST_ESP_OK(adc_continuous_start(handle));
     TEST_ESP_ERR(ESP_ERR_INVALID_STATE, adc_del_continuous_monitor(monitor_handle));
@@ -400,23 +397,7 @@ TEST_CASE("ADC continuous monitor init_deinit", "[adc]")
     TEST_ESP_OK(adc_continuous_deinit(handle));
 }
 
-/**
- * NOTE: To run this special feature test case, you need wire ADC channel pin you want to monit
- *       to a wave output pin defined below.
- *
- *       +---------+
- *       |         |
- *       |    (adc)|------------+
- *       |         |            |
- *       |   (wave)|------------+
- *       |         |
- *       |  ESP32  |
- *       +---------+
- *
- *       or you can connect your signals from signal generator to ESP32 pin which you monitoring
- **/
-#define TEST_ADC_CHANNEL    ADC_CHANNEL_0   //GPIO_1
-#define TEST_WAVE_OUT_PIN   GPIO_NUM_2      //GPIO_2
+#define TEST_ADC_CHANNEL    ADC_CHANNEL_0
 static uint32_t m1h_cnt, m1l_cnt;
 
 bool IRAM_ATTR m1h_cb(adc_monitor_handle_t monitor_handle, const adc_monitor_evt_data_t *event_data, void *user_data)
@@ -429,7 +410,7 @@ bool IRAM_ATTR m1l_cb(adc_monitor_handle_t monitor_handle, const adc_monitor_evt
     m1l_cnt ++;
     return false;
 }
-TEST_CASE("ADC continuous monitor functionary", "[adc][manual][ignore]")
+TEST_CASE("ADC continuous monitor functionary", "[adc]")
 {
     adc_continuous_handle_t handle = NULL;
     adc_continuous_handle_cfg_t adc_config = {
@@ -474,35 +455,40 @@ TEST_CASE("ADC continuous monitor functionary", "[adc][manual][ignore]")
     };
     TEST_ESP_OK(adc_new_continuous_monitor(handle, &adc_monitor_cfg, &monitor_handle));
     TEST_ESP_OK(adc_continuous_monitor_register_event_callbacks(monitor_handle, &monitor_cb, NULL));
-
-    //config a pin to generate wave
-    gpio_config_t gpio_cfg = {
-        .pin_bit_mask = (1ULL << TEST_WAVE_OUT_PIN),
-        .mode = GPIO_MODE_INPUT_OUTPUT,
-        .pull_up_en = GPIO_PULLDOWN_ENABLE,
-    };
-    TEST_ESP_OK(gpio_config(&gpio_cfg));
-
     TEST_ESP_OK(adc_continuous_monitor_enable(monitor_handle));
     TEST_ESP_OK(adc_continuous_start(handle));
 
-    for (uint8_t i = 0; i < 8; i++) {
-        vTaskDelay(1000);
+    int adc_io;
+    adc_continuous_channel_to_io(ADC_UNIT_1, TEST_ADC_CHANNEL, &adc_io);
+    printf("Using ADC_CHANNEL_%d on GPIO%d\n", TEST_ADC_CHANNEL, adc_io);
 
-        // check monitor cb
-        printf("%d\t high_cnt %4ld\tlow_cnt %4ld\n", i, m1h_cnt, m1l_cnt);
-        if (gpio_get_level(TEST_WAVE_OUT_PIN)) {
+    // Test with internal gpio pull up/down, detail and order refer to `gpio_pull_mode_t`
+    // pull_up + pull_down to get half ADC convert
+    for (uint8_t i = 0; i < 8; i++) {
+        int pull_mode = i % GPIO_FLOATING;
+        gpio_set_pull_mode(adc_io, pull_mode);
+        vTaskDelay(10); // wait some time for GPIO level be stable
+        m1h_cnt = 0;
+        m1l_cnt = 0;
+        vTaskDelay(1000);   //time to count monitor interrupt
+        printf("%d\t %s\t high_cnt %4ld\tlow_cnt %4ld\n", i, (pull_mode == 0) ? "up  " : (pull_mode == 1) ? "down" : "mid ", m1h_cnt, m1l_cnt);
+
+        switch (pull_mode) {
+        case GPIO_PULLUP_ONLY:
 #if !CONFIG_IDF_TARGET_ESP32S2
-            // TEST_ASSERT_UINT32_WITHIN(SOC_ADC_SAMPLE_FREQ_THRES_LOW*0.1, SOC_ADC_SAMPLE_FREQ_THRES_LOW, m1h_cnt);
-            // TEST_ASSERT_LESS_THAN_UINT32(5, m1l_cnt);   //Actually, it will still encountered 1~2 times because hardware run very quickly
+            TEST_ASSERT_UINT32_WITHIN(SOC_ADC_SAMPLE_FREQ_THRES_LOW * 0.1, SOC_ADC_SAMPLE_FREQ_THRES_LOW, m1h_cnt);
+            TEST_ASSERT_EQUAL(0, m1l_cnt);  //low limit should NOT triggrted when pull_up
 #endif
-            m1h_cnt = 0;
-            gpio_set_level(TEST_WAVE_OUT_PIN, 0);
-        } else {
+            break;
+        case GPIO_PULLDOWN_ONLY:
             TEST_ASSERT_UINT32_WITHIN(SOC_ADC_SAMPLE_FREQ_THRES_LOW * 0.1, SOC_ADC_SAMPLE_FREQ_THRES_LOW, m1l_cnt);
-            TEST_ASSERT_LESS_THAN_UINT32(5, m1h_cnt);   //Actually, it will still encountered 1~2 times because hardware run very quickly
-            m1l_cnt = 0;
-            gpio_set_level(TEST_WAVE_OUT_PIN, 1);
+            TEST_ASSERT_EQUAL(0, m1h_cnt);
+            break;
+        case GPIO_PULLUP_PULLDOWN:
+            TEST_ASSERT_EQUAL(0, m1h_cnt);  //half votage, both limit should NOT triggered
+            TEST_ASSERT_EQUAL(0, m1l_cnt);
+            break;
+        default: printf("unknown gpio pull mode !!!\n");
         }
     }
     TEST_ESP_OK(adc_continuous_stop(handle));
diff --git a/components/esp_adc/test_apps/adc/main/test_adc_wifi.c b/components/esp_adc/test_apps/adc/main/test_adc_wifi.c
index b236f8ea2db..e9380a825b2 100644
--- a/components/esp_adc/test_apps/adc/main/test_adc_wifi.c
+++ b/components/esp_adc/test_apps/adc/main/test_adc_wifi.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,7 +43,7 @@ static const char* TAG = "test_adc_wifi";
 static int read_raw;
 static int target_value;
 static int test_adc_io;
-static bool test_list[TEST_NUM] = {1, 1, 0, 0, 1, 0, 1, 0};
+static bool test_list[TEST_NUM] = {0, 1, 0, 0, 1, 0, 1, 0};
 
 static void wifi_event_handler(void* arg, esp_event_base_t event_base,
                                int32_t event_id, void* event_data)
@@ -215,14 +215,14 @@ __attribute__((unused)) static void adc_work_with_wifi(adc_unit_t unit_id, adc_c
     TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop.");
 }
 
-#if CONFIG_IDF_TARGET_ESP32C6
-// On ESP32C6, ADC need to call two modem clocks: modem_syscon_ll_enable_fe_80m_clock and modem_syscon_ll_enable_fe_apb_clock.
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61
+// ADC need to call two modem clocks: modem_syscon_ll_enable_fe_80m_clock and modem_syscon_ll_enable_fe_apb_clock.
 // Without calling these two clocks, PWDET mode will not take into effect, so ADC readings will be wrong.
 TEST_CASE("ADC1 work with WiFi", "[adc]")
 {
     adc_work_with_wifi(ADC_UNIT_1, ADC1_WIFI_TEST_CHAN0);
 }
-#endif  // CONFIG_IDF_TARGET_ESP32C6
+#endif
 
 #if (SOC_ADC_PERIPH_NUM >= 2) && !CONFIG_IDF_TARGET_ESP32C3
 // On ESP32C3, ADC2 is no longer supported, due to its HW limitation.
diff --git a/components/esp_adc/test_apps/adc/main/test_common_adc.h b/components/esp_adc/test_apps/adc/main/test_common_adc.h
index c2bd4cd1989..89e3477b4c3 100644
--- a/components/esp_adc/test_apps/adc/main/test_common_adc.h
+++ b/components/esp_adc/test_apps/adc/main/test_common_adc.h
@@ -103,6 +103,14 @@ extern "C" {
 #define ADC_TEST_HIGH_VAL_DMA    4095
 #define ADC_TEST_HIGH_THRESH     200
 
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define ADC_TEST_LOW_VAL         2140
+#define ADC_TEST_LOW_THRESH      200
+
+#define ADC_TEST_HIGH_VAL        4095
+#define ADC_TEST_HIGH_VAL_DMA    4095
+#define ADC_TEST_HIGH_THRESH     200
+
 #endif
 
 /*---------------------------------------------------------------
diff --git a/components/esp_app_format/esp_app_desc.c b/components/esp_app_format/esp_app_desc.c
index 27b821256d7..302250b1792 100644
--- a/components/esp_app_format/esp_app_desc.c
+++ b/components/esp_app_format/esp_app_desc.c
@@ -59,6 +59,7 @@ const __attribute__((weak)) __attribute__((section(".rodata_desc")))  esp_app_de
 #endif
     .min_efuse_blk_rev_full = CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL,
     .max_efuse_blk_rev_full = CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL,
+    .mmu_page_size = 31 - __builtin_clz(CONFIG_MMU_PAGE_SIZE),
 };
 
 #ifndef CONFIG_APP_EXCLUDE_PROJECT_VER_VAR
diff --git a/components/esp_app_format/include/esp_app_desc.h b/components/esp_app_format/include/esp_app_desc.h
index b4201a4d057..6cb73e3676e 100644
--- a/components/esp_app_format/include/esp_app_desc.h
+++ b/components/esp_app_format/include/esp_app_desc.h
@@ -35,7 +35,9 @@ typedef struct {
     uint8_t app_elf_sha256[32]; /*!< sha256 of elf file */
     uint16_t min_efuse_blk_rev_full; /*!< Minimal eFuse block revision supported by image, in format: major * 100 + minor */
     uint16_t max_efuse_blk_rev_full; /*!< Maximal eFuse block revision supported by image, in format: major * 100 + minor */
-    uint32_t reserv2[19];       /*!< reserv2 */
+    uint8_t mmu_page_size;      /*!< MMU page size in log base 2 format */
+    uint8_t reserv3[3];         /*!< reserv3 */
+    uint32_t reserv2[18];       /*!< reserv2 */
 } esp_app_desc_t;
 
 /** @cond */
diff --git a/components/esp_bootloader_format/esp_bootloader_desc.c b/components/esp_bootloader_format/esp_bootloader_desc.c
index fdcc2049ba3..6c4c3caa94e 100644
--- a/components/esp_bootloader_format/esp_bootloader_desc.c
+++ b/components/esp_bootloader_format/esp_bootloader_desc.c
@@ -17,6 +17,11 @@ __attribute__((weak))
 const esp_bootloader_desc_t esp_bootloader_desc = {
     .magic_byte = ESP_BOOTLOADER_DESC_MAGIC_BYTE,
     .reserved = { 0 },
+#if CONFIG_BOOTLOADER_ANTI_ROLLBACK_ENABLE
+    .secure_version = CONFIG_BOOTLOADER_SECURE_VERSION,
+#else
+    .secure_version = 0,
+#endif // CONFIG_BOOTLOADER_ANTI_ROLLBACK_ENABLE
     .version = CONFIG_BOOTLOADER_PROJECT_VER,
     .idf_ver = IDF_VER,
 #ifdef CONFIG_BOOTLOADER_COMPILE_TIME_DATE
diff --git a/components/esp_bootloader_format/include/esp_bootloader_desc.h b/components/esp_bootloader_format/include/esp_bootloader_desc.h
index 868fb9c7354..5bee2f4d0a7 100644
--- a/components/esp_bootloader_format/include/esp_bootloader_desc.h
+++ b/components/esp_bootloader_format/include/esp_bootloader_desc.h
@@ -24,7 +24,8 @@ extern "C"
  */
 typedef struct {
     uint8_t magic_byte;         /*!< Magic byte ESP_BOOTLOADER_DESC_MAGIC_BYTE */
-    uint8_t reserved[3];        /*!< reserved for IDF */
+    uint8_t reserved[2];        /*!< reserved for IDF */
+    uint8_t secure_version;     /*!< The version used by bootloader anti-rollback feature */
     uint32_t version;           /*!< Bootloader version */
     char idf_ver[32];           /*!< Version IDF */
     char date_time[24];         /*!< Compile date and time*/
diff --git a/components/esp_coex/Kconfig b/components/esp_coex/Kconfig
index 5fb0eac973a..bc37b3820b2 100644
--- a/components/esp_coex/Kconfig
+++ b/components/esp_coex/Kconfig
@@ -217,7 +217,7 @@ menu "Wireless Coexistence"
             default 12 if IDF_TARGET_ESP32S3
             default 3 if IDF_TARGET_ESP32C2
             default 22 if IDF_TARGET_ESP32C6
-            default 16 if IDF_TARGET_ESP32C5
+            default 10 if IDF_TARGET_ESP32C5
             default 13 if IDF_TARGET_ESP32C61
             default 11
 
@@ -231,7 +231,7 @@ menu "Wireless Coexistence"
             default 13 if IDF_TARGET_ESP32S3
             default 2 if IDF_TARGET_ESP32C2
             default 21 if IDF_TARGET_ESP32C6
-            default 0 if IDF_TARGET_ESP32C5
+            default 9 if IDF_TARGET_ESP32C5
             default 12 if IDF_TARGET_ESP32C61
             default 12
 
diff --git a/components/esp_coex/esp32c2/esp_coex_adapter.c b/components/esp_coex/esp32c2/esp_coex_adapter.c
index 4954fb9f850..b98c9c94742 100644
--- a/components/esp_coex/esp32c2/esp_coex_adapter.c
+++ b/components/esp_coex/esp32c2/esp_coex_adapter.c
@@ -152,6 +152,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
 #endif
 }
 
+static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void)
+{
+    return rtc_clk_xtal_freq_get();
+}
+
 coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._version = COEX_ADAPTER_VERSION,
     ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@@ -172,5 +177,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._timer_setfn = esp_coex_common_timer_setfn_wrapper,
     ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
     ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
+    ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper,
     ._magic = COEX_ADAPTER_MAGIC,
 };
diff --git a/components/esp_coex/esp32c5/esp_coex_adapter.c b/components/esp_coex/esp32c5/esp_coex_adapter.c
index b5e761ffbd9..8588b7348d1 100644
--- a/components/esp_coex/esp32c5/esp_coex_adapter.c
+++ b/components/esp_coex/esp32c5/esp_coex_adapter.c
@@ -151,6 +151,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
 #endif
 }
 
+static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void)
+{
+    return rtc_clk_xtal_freq_get();
+}
+
 coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._version = COEX_ADAPTER_VERSION,
     ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@@ -170,5 +175,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._timer_setfn = esp_coex_common_timer_setfn_wrapper,
     ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
     ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
+    ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper,
     ._magic = COEX_ADAPTER_MAGIC,
 };
diff --git a/components/esp_coex/esp32c6/esp_coex_adapter.c b/components/esp_coex/esp32c6/esp_coex_adapter.c
index 81b4eef2b1e..4b920ce1595 100644
--- a/components/esp_coex/esp32c6/esp_coex_adapter.c
+++ b/components/esp_coex/esp32c6/esp_coex_adapter.c
@@ -152,6 +152,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
 #endif
 }
 
+static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void)
+{
+    return rtc_clk_xtal_freq_get();
+}
+
 coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._version = COEX_ADAPTER_VERSION,
     ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@@ -171,5 +176,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._timer_setfn = esp_coex_common_timer_setfn_wrapper,
     ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
     ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
+    ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper,
     ._magic = COEX_ADAPTER_MAGIC,
 };
diff --git a/components/esp_coex/esp32c61/esp_coex_adapter.c b/components/esp_coex/esp32c61/esp_coex_adapter.c
index 547e1dbd363..059160f7bab 100644
--- a/components/esp_coex/esp32c61/esp_coex_adapter.c
+++ b/components/esp_coex/esp32c61/esp_coex_adapter.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -152,6 +152,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
 #endif
 }
 
+static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void)
+{
+    return rtc_clk_xtal_freq_get();
+}
+
 coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._version = COEX_ADAPTER_VERSION,
     ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@@ -171,5 +176,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._timer_setfn = esp_coex_common_timer_setfn_wrapper,
     ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
     ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
+    ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper,
     ._magic = COEX_ADAPTER_MAGIC,
 };
diff --git a/components/esp_coex/esp32h2/esp_coex_adapter.c b/components/esp_coex/esp32h2/esp_coex_adapter.c
index f00cade6f6b..1fa2243ae9a 100644
--- a/components/esp_coex/esp32h2/esp_coex_adapter.c
+++ b/components/esp_coex/esp32h2/esp_coex_adapter.c
@@ -144,6 +144,11 @@ static int esp_coexist_debug_matrix_init_wrapper(int evt, int sig, bool rev)
 #endif
 }
 
+static IRAM_ATTR int esp_coex_common_xtal_freq_get_wrapper(void)
+{
+    return rtc_clk_xtal_freq_get();
+}
+
 coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._version = COEX_ADAPTER_VERSION,
     ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper,
@@ -163,5 +168,6 @@ coex_adapter_funcs_t g_coex_adapter_funcs = {
     ._timer_setfn = esp_coex_common_timer_setfn_wrapper,
     ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper,
     ._debug_matrix_init = esp_coexist_debug_matrix_init_wrapper,
+    ._xtal_freq_get = esp_coex_common_xtal_freq_get_wrapper,
     ._magic = COEX_ADAPTER_MAGIC,
 };
diff --git a/components/esp_coex/include/esp_coex_i154.h b/components/esp_coex/include/esp_coex_i154.h
index 942de356139..b8cb8171e68 100644
--- a/components/esp_coex/include/esp_coex_i154.h
+++ b/components/esp_coex/include/esp_coex_i154.h
@@ -18,6 +18,8 @@ typedef enum {
 void esp_coex_ieee802154_txrx_pti_set(ieee802154_coex_event_t event);
 void esp_coex_ieee802154_ack_pti_set(ieee802154_coex_event_t event);
 void esp_coex_ieee802154_coex_break_notify(void);
+void esp_coex_ieee802154_extcoex_tx_stage(void);
+void esp_coex_ieee802154_extcoex_rx_stage(void);
 #endif
 
 #endif
diff --git a/components/esp_coex/include/private/esp_coexist_adapter.h b/components/esp_coex/include/private/esp_coexist_adapter.h
index aca50a6161a..15e8ef7114f 100644
--- a/components/esp_coex/include/private/esp_coexist_adapter.h
+++ b/components/esp_coex/include/private/esp_coexist_adapter.h
@@ -47,6 +47,7 @@ typedef struct {
     void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg);
     void (* _timer_arm_us)(void *ptimer, uint32_t us, bool repeat);
     int (* _debug_matrix_init)(int event, int signal, bool rev);
+    int (* _xtal_freq_get)(void);
     int32_t _magic;
 } coex_adapter_funcs_t;
 
diff --git a/components/esp_coex/include/private/esp_coexist_debug.h b/components/esp_coex/include/private/esp_coexist_debug.h
index 26147262c75..80bfbbd5aa6 100644
--- a/components/esp_coex/include/private/esp_coexist_debug.h
+++ b/components/esp_coex/include/private/esp_coexist_debug.h
@@ -108,7 +108,7 @@ typedef enum {
 #endif
 
 /* wifi callback -> debug */
-void wifi_set_gpio_debug_cb(void (* cb)(int, int));
+void wifi_set_gpio_debug_cb(void (* cb)(int, coex_gpio_debug_sig_t));
 int wifi_gpio_debug_max_event_get(void);
 
 /* functions to check if in ROM */
@@ -128,9 +128,10 @@ void pm_check_state(void);
 void pm_tx_null_data_done_process(void);
 void pm_start(void);
 void pm_stop(void);
+void pm_disconnected_wake(void);
 
 /* coex callback -> debug */
-void coex_set_gpio_debug_cb(void (*cb)(int, int));
+void coex_set_gpio_debug_cb(void (*cb)(int, coex_gpio_debug_sig_t));
 int coex_gpio_debug_max_event_get(void);
 esp_err_t coex_gpio_debug_matrix_init(void);
 
@@ -142,4 +143,10 @@ void wifi_bind_io_to_evt(uint8_t io_idx, uint8_t evt);
 void coex_bind_io_to_evt(uint8_t io_idx, uint8_t evt);
 void diagram_bind_io_to_evt(void);
 
+/* coex -> debug
+ * configure single gpio debug event */
+esp_err_t coex_gpio_debug_matrix_config(int event);
+/* debug -> internal use */
+esp_err_t esp_coexist_gpio_debug_matrix_config(int event);
+
 #endif
diff --git a/components/esp_coex/lib b/components/esp_coex/lib
index e15e7a161fc..ad30777643c 160000
--- a/components/esp_coex/lib
+++ b/components/esp_coex/lib
@@ -1 +1 @@
-Subproject commit e15e7a161fc1a48e8fb4fd0b3da74623c30ba1cb
+Subproject commit ad30777643ca4c97fbce790f01aebd474ae4946f
diff --git a/components/esp_coex/src/coexist_debug.c b/components/esp_coex/src/coexist_debug.c
index 7c38eea8e51..8ef1eb6de16 100644
--- a/components/esp_coex/src/coexist_debug.c
+++ b/components/esp_coex/src/coexist_debug.c
@@ -13,37 +13,20 @@
 #include "esp_attr.h"
 #include "esp_log.h"
 
-#if CONFIG_IDF_TARGET_ESP32
-#include "esp32/rom/gpio.h"
-#include "esp32/rom/ets_sys.h"
-#elif defined(CONFIG_IDF_TARGET_ESP32S2)
-#include "esp32s2/rom/gpio.h"
-#include "esp32s2/rom/ets_sys.h"
-#elif defined(CONFIG_IDF_TARGET_ESP32C3)
-#include "esp32c3/rom/gpio.h"
-#include "esp32c3/rom/ets_sys.h"
-#elif defined(CONFIG_IDF_TARGET_ESP32C2)
-#include "esp32c2/rom/gpio.h"
-#include "esp32c2/rom/ets_sys.h"
-#elif defined(CONFIG_IDF_TARGET_ESP32C6)
-#include "esp32c6/rom/gpio.h"
-#include "esp32c6/rom/ets_sys.h"
-#elif defined(CONFIG_IDF_TARGET_ESP32C5)
-#include "esp32c5/rom/gpio.h"
-#include "esp32c5/rom/ets_sys.h"
-#elif defined(CONFIG_IDF_TARGET_ESP32C61)
-#include "esp32c61/rom/gpio.h"
-#include "esp32c61/rom/ets_sys.h"
-#endif
+#include "rom/gpio.h"
+#include "rom/ets_sys.h"
 #include "driver/gpio.h"
 #include "soc/gpio_sig_map.h"
 #include "esp_rom_gpio.h"
 #include "soc/soc.h"
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+#include "esp_private/esp_modem_clock.h"
+#endif
 
 #if CONFIG_ESP_COEX_GPIO_DEBUG
 static char* TAG = "coexist debug";
 
-__attribute__((weak)) void wifi_set_gpio_debug_cb(void (* cb)(int, int))
+__attribute__((weak)) void wifi_set_gpio_debug_cb(void (* cb)(int, coex_gpio_debug_sig_t))
 {
     ESP_LOGW(TAG, "Not support: %s", __FUNCTION__);
 }
@@ -53,7 +36,7 @@ __attribute__((weak)) int wifi_gpio_debug_max_event_get(void)
     return 0;
 }
 
-__attribute__((weak)) void coex_set_gpio_debug_cb(void (*cb)(int, int))
+__attribute__((weak)) void coex_set_gpio_debug_cb(void (*cb)(int, coex_gpio_debug_sig_t))
 {
     ESP_LOGW(TAG, "Not support: %s", __FUNCTION__);
 }
@@ -89,6 +72,7 @@ static const void* rom_funcs[] = {
     pm_tx_null_data_done_process,
     pm_start,
     pm_stop,
+    pm_disconnected_wake,
 #endif
 };
 static const char* rom_funcs_name[] = {
@@ -109,6 +93,7 @@ static const char* rom_funcs_name[] = {
     "pm_tx_null_data_done_process",
     "pm_start",
     "pm_stop",
+    "pm_disconnected_wake",
 #endif
 };
 
@@ -205,6 +190,18 @@ esp_err_t esp_coexist_debug_matrix_init(int evt, int sig, bool rev)
     return ESP_OK;
 }
 
+esp_err_t esp_coexist_gpio_debug_matrix_config(int event)
+{
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+    modem_clock_module_enable(PERIPH_COEX_MODULE);
+#endif
+    esp_err_t ret = coex_gpio_debug_matrix_config(event);
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+    modem_clock_module_disable(PERIPH_COEX_MODULE);
+#endif
+    return ret;
+}
+
 esp_err_t esp_coexist_debug_init(void)
 {
     if (check_funcs_in_rom()) {
@@ -268,8 +265,14 @@ esp_err_t esp_coexist_debug_init(void)
         gpio_set_level(s_io_nums[i], false);
     }
 
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+    modem_clock_module_enable(PERIPH_COEX_MODULE);
+#endif
     /* Init coexist hardware signal */
     ESP_ERROR_CHECK(coex_gpio_debug_matrix_init());
+#if SOC_MODEM_CLOCK_IS_INDEPENDENT
+    modem_clock_module_disable(PERIPH_COEX_MODULE);
+#endif
 
     return ESP_OK;
 }
diff --git a/components/esp_coex/test_md5/test_md5.sh b/components/esp_coex/test_md5/test_md5.sh
index 24f80b76e3b..429796bdfa7 100755
--- a/components/esp_coex/test_md5/test_md5.sh
+++ b/components/esp_coex/test_md5/test_md5.sh
@@ -32,40 +32,74 @@ case $IDF_TARGET in
 esac
 LIB_DIR=${IDF_TARGET}
 
-ELF_FILE=test.elf
+COEX_ELF_FILE=coex.elf
+TEST_ELF_FILE=test.elf
 
 FAILURES=0
 
 function check_md5()
+{
+    if [ "$1" != "$2" ]; then
+        echo "  error: MD5 mismatch!"
+        FAILURES=$(($FAILURES+1))
+    fi
+}
+
+function check_md5_file_lib()
 {
     FILENAME=$1
     SYMBOL=$2
 
-    ${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${ELF_FILE} \
+    ${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${COEX_ELF_FILE} \
         -u ${SYMBOL} \
     ${IDF_PATH}/components/esp_coex/lib/${LIB_DIR}/*.a
     GDB_COMMAND="printf \"%s\\n\", (const char*) ${SYMBOL}"
-    MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${ELF_FILE} -ex "${GDB_COMMAND}")
+    MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${COEX_ELF_FILE} -ex "${GDB_COMMAND}")
     MD5_FROM_HEADER=$(md5sum ${FILENAME} | cut -c 1-7)
-
     echo "Checking ${FILENAME}:"
     echo "  ${MD5_FROM_HEADER} - from header file"
     echo "  ${MD5_FROM_LIB} - from library"
-    if [ "${MD5_FROM_LIB}" != "${MD5_FROM_HEADER}" ]; then
-        echo "  error: MD5 mismatch!"
-        FAILURES=$(($FAILURES+1))
-    fi
+    check_md5 ${MD5_FROM_HEADER} ${MD5_FROM_LIB}
+}
+
+function check_md5_libs()
+{
+    COEX_SYMBOL=$1
+    TEST_SYMBOL=$2
+    TEST_PATH=$3
+
+    ${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${COEX_ELF_FILE} \
+        -u ${COEX_SYMBOL} \
+    ${IDF_PATH}/components/esp_coex/lib/${LIB_DIR}/*.a
+
+    ${PREFIX}ld --unresolved-symbols=ignore-all --entry 0 -o ${TEST_ELF_FILE} \
+        -u ${TEST_SYMBOL} \
+    ${TEST_PATH}/*.a
+
+    COEX_GDB_COMMAND="printf \"%s\\n\", (const char*) ${COEX_SYMBOL}"
+    TEST_GDB_COMMAND="printf \"%s\\n\", (const char*) ${TEST_SYMBOL}"
+    COEX_MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${COEX_ELF_FILE} -ex "${COEX_GDB_COMMAND}")
+    TEST_MD5_FROM_LIB=$(${PREFIX}gdb -n -batch ${TEST_ELF_FILE} -ex "${TEST_GDB_COMMAND}")
+
+    echo "Checking ${TEST_PATH}/${TEST_SYMBOL} "
+    echo "  ${COEX_MD5_FROM_LIB} - from coexist library"
+    echo "  ${TEST_MD5_FROM_LIB} - from test library"
+    check_md5 ${COEX_MD5_FROM_LIB} ${TEST_MD5_FROM_LIB}
 }
 
 echo "Checking libraries for target ${IDF_TARGET}..."
-check_md5 ${IDF_PATH}/components/esp_coex/include/private/esp_coexist_adapter.h g_coex_adapter_funcs_md5
+check_md5_file_lib ${IDF_PATH}/components/esp_coex/include/private/esp_coexist_adapter.h g_coex_adapter_funcs_md5
 
 case $IDF_TARGET in
     esp32c6|esp32h2|esp32c5)
-    check_md5 ${IDF_PATH}/components/esp_coex/include/esp_coex_i154.h g_coex_i154_funcs_md5
+    check_md5_file_lib ${IDF_PATH}/components/esp_coex/include/esp_coex_i154.h g_coex_i154_funcs_md5
     ;;
 esac
 
+if [[ ! "$IDF_TARGET" =~ ^(esp32h2)$ ]]; then
+    check_md5_libs g_coex_basic_md5 g_wifi_coex_basic_md5 ${IDF_PATH}/components/esp_wifi/lib/${LIB_DIR}
+fi
+
 if [ $FAILURES -gt 0 ]; then
     exit 1
 fi
diff --git a/components/esp_common/include/esp_idf_version.h b/components/esp_common/include/esp_idf_version.h
index 74aea26b783..d5051726975 100644
--- a/components/esp_common/include/esp_idf_version.h
+++ b/components/esp_common/include/esp_idf_version.h
@@ -13,7 +13,7 @@ extern "C" {
 /** Major version number (X.x.x) */
 #define ESP_IDF_VERSION_MAJOR   5
 /** Minor version number (x.X.x) */
-#define ESP_IDF_VERSION_MINOR   4
+#define ESP_IDF_VERSION_MINOR   5
 /** Patch version number (x.x.X) */
 #define ESP_IDF_VERSION_PATCH   0
 
diff --git a/components/esp_common/include/esp_macros.h b/components/esp_common/include/esp_macros.h
index 183c947a44f..0893878e7eb 100644
--- a/components/esp_common/include/esp_macros.h
+++ b/components/esp_common/include/esp_macros.h
@@ -50,15 +50,15 @@ extern "C" {
 /* Count number of arguments of __VA_ARGS__
  * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s
  * - __GET_NTH_ARG__() takes args >= N (64) but only expand to Nth one (64th)
- * - __RSEQ_N__() is reverse sequential to N to add padding to have Nth
+ * - ESP_RSEQ_N() is reverse sequential to N to add padding to have Nth
  *   position is the same as the number of arguments
  * - ##__VA_ARGS__ is used to deal with 0 parameter (swallows comma)
  */
-#ifndef __VA_NARG__
-# define __VA_NARG__(...)   __NARG__(_0, ##__VA_ARGS__, __RSEQ_N__())
+#ifndef ESP_VA_NARG
+# define ESP_VA_NARG(...)   ESP_NARG(_0, ##__VA_ARGS__, ESP_RSEQ_N())
 
-# define __NARG__(...)      __GET_NTH_ARG__(__VA_ARGS__)
-# define __GET_NTH_ARG__( \
+# define ESP_NARG(...)      ESP_GET_NTH_ARG(__VA_ARGS__)
+# define ESP_GET_NTH_ARG( \
         _01,_02,_03,_04,_05,_06,_07,_08,_09,_10, \
         _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
         _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
@@ -66,7 +66,7 @@ extern "C" {
         _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
         _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
         _61,_62,_63,N,...) N
-# define __RSEQ_N__() \
+# define ESP_RSEQ_N() \
         62,61,60,                      \
         59,58,57,56,55,54,53,52,51,50, \
         49,48,47,46,45,44,43,42,41,40, \
@@ -80,25 +80,6 @@ extern "C" {
 #define ESP_UNUSED(x) ((void)(x))
 #endif
 
-/* test macros */
-#define foo_args(...) 1
-#define foo_no_args() 2
-#if defined(__cplusplus) && (__cplusplus >  201703L)
-#define foo(...) CHOOSE_MACRO_VA_ARG(foo_args, foo_no_args __VA_OPT__(,) __VA_ARGS__)(__VA_ARGS__)
-#else
-#define foo(...) CHOOSE_MACRO_VA_ARG(foo_args, foo_no_args, ##__VA_ARGS__)(__VA_ARGS__)
-#endif
-
-ESP_STATIC_ASSERT(foo() == 2, "CHOOSE_MACRO_VA_ARG() result does not match for 0 arguments");
-ESP_STATIC_ASSERT(foo(42) == 1, "CHOOSE_MACRO_VA_ARG() result does not match for 1 argument");
-#if defined(__cplusplus) && (__cplusplus >  201703L)
-ESP_STATIC_ASSERT(foo(42, 87) == 1, "CHOOSE_MACRO_VA_ARG() result does not match for n arguments");
-#endif
-
-#undef foo
-#undef foo_args
-#undef foo_no_args
-
 #define ESP_INFINITE_LOOP() \
     do { \
         ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-infinite-loop") \
diff --git a/components/esp_common/test_apps/esp_common/main/CMakeLists.txt b/components/esp_common/test_apps/esp_common/main/CMakeLists.txt
index d1e953e6382..f45ce0708cd 100644
--- a/components/esp_common/test_apps/esp_common/main/CMakeLists.txt
+++ b/components/esp_common/test_apps/esp_common/main/CMakeLists.txt
@@ -1,4 +1,4 @@
-idf_component_register(SRCS "test_app_main.c" "test_attr.c"
+idf_component_register(SRCS "test_app_main.c" "test_attr.c" "test_esp_macro.c"
                        INCLUDE_DIRS "."
                        PRIV_REQUIRES unity esp_mm esp_psram
                        WHOLE_ARCHIVE)
diff --git a/components/esp_common/test_apps/esp_common/main/test_esp_macro.c b/components/esp_common/test_apps/esp_common/main/test_esp_macro.c
new file mode 100644
index 00000000000..334fa980672
--- /dev/null
+++ b/components/esp_common/test_apps/esp_common/main/test_esp_macro.c
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include "esp_macros.h"
+
+/* test macros */
+#define foo_args(...) 1
+#define foo_no_args() 2
+#if defined(__cplusplus) && (__cplusplus >  201703L)
+#define foo(...) CHOOSE_MACRO_VA_ARG(foo_args, foo_no_args __VA_OPT__(,) __VA_ARGS__)(__VA_ARGS__)
+#else
+#define foo(...) CHOOSE_MACRO_VA_ARG(foo_args, foo_no_args, ##__VA_ARGS__)(__VA_ARGS__)
+#endif
+
+ESP_STATIC_ASSERT(foo() == 2, "CHOOSE_MACRO_VA_ARG() result does not match for 0 arguments");
+ESP_STATIC_ASSERT(foo(42) == 1, "CHOOSE_MACRO_VA_ARG() result does not match for 1 argument");
+#if defined(__cplusplus) && (__cplusplus >  201703L)
+ESP_STATIC_ASSERT(foo(42, 87) == 1, "CHOOSE_MACRO_VA_ARG() result does not match for n arguments");
+#endif
diff --git a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4 b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4
index 0d33cfbf8f4..5470efa1208 100644
--- a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4
+++ b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32p4
@@ -5,4 +5,4 @@ CONFIG_SPIRAM=y
 CONFIG_SPIRAM_XIP_FROM_PSRAM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
diff --git a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2 b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2
index fd9b7e865c3..3c7418b55d9 100644
--- a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2
+++ b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s2
@@ -5,4 +5,4 @@ CONFIG_SPIRAM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_RODATA=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
diff --git a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3 b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3
index 3b1db1f233f..53125cb9b8b 100644
--- a/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3
+++ b/components/esp_common/test_apps/esp_common/sdkconfig.ci.xip_psram_esp32s3
@@ -5,4 +5,4 @@ CONFIG_SPIRAM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_RODATA=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
diff --git a/components/esp_driver_dac/dac_continuous.c b/components/esp_driver_dac/dac_continuous.c
index b3f8f9c25e0..c7e4ffb5eae 100644
--- a/components/esp_driver_dac/dac_continuous.c
+++ b/components/esp_driver_dac/dac_continuous.c
@@ -228,7 +228,7 @@ esp_err_t dac_continuous_new_channels(const dac_continuous_config_t *cont_cfg, d
 
     /* Create PM lock */
 #if CONFIG_PM_ENABLE
-    esp_pm_lock_type_t pm_lock_type = cont_cfg->clk_src == DAC_DIGI_CLK_SRC_APLL ? ESP_PM_NO_LIGHT_SLEEP : ESP_PM_APB_FREQ_MAX;
+    esp_pm_lock_type_t pm_lock_type = ESP_PM_APB_FREQ_MAX;
     ESP_GOTO_ON_ERROR(esp_pm_lock_create(pm_lock_type, 0, "dac_driver", &handle->pm_lock), err3, TAG, "Failed to create DAC pm lock");
 #endif
     handle->chan_cnt = __builtin_popcount(cont_cfg->chan_mask);
diff --git a/components/esp_driver_gpio/include/esp_private/gpio.h b/components/esp_driver_gpio/include/esp_private/gpio.h
index b2186295c0a..2e06192f633 100644
--- a/components/esp_driver_gpio/include/esp_private/gpio.h
+++ b/components/esp_driver_gpio/include/esp_private/gpio.h
@@ -52,6 +52,17 @@ esp_err_t gpio_sleep_pupd_config_unapply(gpio_num_t gpio_num);
   */
 esp_err_t gpio_func_sel(gpio_num_t gpio_num, uint32_t func);
 
+/**
+ * @brief Enable output for an IO
+ *
+ * @param gpio_num GPIO number
+ *
+ * @return
+ *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_ARG GPIO number error
+ */
+esp_err_t gpio_output_enable(gpio_num_t gpio_num);
+
 /**
  * @brief Disable output for an IO
  *
diff --git a/components/esp_driver_gpio/src/dedic_gpio.c b/components/esp_driver_gpio/src/dedic_gpio.c
index bbc66995b2c..3faf0d9de7e 100644
--- a/components/esp_driver_gpio/src/dedic_gpio.c
+++ b/components/esp_driver_gpio/src/dedic_gpio.c
@@ -269,6 +269,7 @@ esp_err_t dedic_gpio_new_bundle(const dedic_gpio_bundle_config_t *config, dedic_
     if (config->flags.in_en) {
         for (size_t i = 0; i < config->array_size; i++) {
             gpio_func_sel(config->gpio_array[i], PIN_FUNC_GPIO);
+            gpio_input_enable(config->gpio_array[i]);
             esp_rom_gpio_connect_in_signal(config->gpio_array[i], dedic_gpio_periph_signals.cores[core_id].in_sig_per_channel[in_offset + i], config->flags.in_invert);
         }
     }
@@ -325,6 +326,17 @@ esp_err_t dedic_gpio_del_bundle(dedic_gpio_bundle_handle_t bundle)
     }
     portEXIT_CRITICAL(&s_platform[core_id]->spinlock);
 
+    if (bundle->in_mask > 0) {
+        for (size_t i = 0; i < bundle->nr_gpio; i++) {
+            esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, dedic_gpio_periph_signals.cores[core_id].in_sig_per_channel[bundle->in_offset + i], 0);
+        }
+    }
+    if (bundle->out_mask > 0) {
+        for (size_t i = 0; i < bundle->nr_gpio; i++) {
+            gpio_output_disable(bundle->gpio_array[i]);
+        }
+    }
+
     free(bundle);
 
     if (recycle_all) {
diff --git a/components/esp_driver_gpio/src/gpio.c b/components/esp_driver_gpio/src/gpio.c
index cffca8e8e83..a63ab11375a 100644
--- a/components/esp_driver_gpio/src/gpio.c
+++ b/components/esp_driver_gpio/src/gpio.c
@@ -211,7 +211,7 @@ esp_err_t gpio_output_disable(gpio_num_t gpio_num)
     return ESP_OK;
 }
 
-static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
+esp_err_t gpio_output_enable(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
     gpio_hal_matrix_out_default(gpio_context.gpio_hal, gpio_num); // No peripheral output signal routed to the pin, just as a simple GPIO output
diff --git a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
index d528c9bdd8f..a6c1549c518 100644
--- a/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
+++ b/components/esp_driver_gpio/test_apps/gpio/main/test_gpio.c
@@ -83,16 +83,16 @@ TEST_CASE("GPIO_config_parameters_test", "[gpio]")
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
 
     // test a non-exist pin
-    io_config.pin_bit_mask = ((uint64_t)1 << GPIO_NUM_MAX);
+    io_config.pin_bit_mask = BIT64(GPIO_NUM_MAX);
     TEST_ASSERT(gpio_config(&io_config) == ESP_ERR_INVALID_ARG);
 
     // test an available pin
-    io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_EXT_OUT_IO);
+    io_config.pin_bit_mask = BIT64(TEST_GPIO_EXT_OUT_IO);
     TEST_ESP_OK(gpio_config(&io_config));
 
     //This IO is just used for input, C3 and S3 doesn't have input only pin.
 #if SOC_HAS_INPUT_ONLY_PIN
-    io_config.pin_bit_mask = ((uint64_t)1 << TEST_GPIO_INPUT_ONLY_PIN);
+    io_config.pin_bit_mask = BIT64(TEST_GPIO_INPUT_ONLY_PIN);
     io_config.mode = GPIO_MODE_INPUT;
     TEST_ESP_OK(gpio_config(&io_config));
     io_config.mode = GPIO_MODE_OUTPUT;
diff --git a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c
index fb306b523ee..9b3f73635e6 100644
--- a/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c
+++ b/components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c
@@ -70,16 +70,8 @@ static void test_dedic_gpio_on_specific_core(void *args)
     uint32_t value = 0;
     dedic_gpio_cpu_ll_write_all(0x0); // clear all out channels
 
-    // configure a group of GPIOs, output only
-    const int bundleA_gpios[] = {ctx->gpios[0], ctx->gpios[1]};
-    gpio_config_t io_conf = {
-        .mode = GPIO_MODE_OUTPUT,
-    };
-    for (int i = 0; i < sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]); i++) {
-        io_conf.pin_bit_mask = 1ULL << bundleA_gpios[i];
-        gpio_config(&io_conf);
-    }
     // Create bundleA, output only
+    const int bundleA_gpios[] = {ctx->gpios[0], ctx->gpios[1]};
     dedic_gpio_bundle_handle_t bundleA = NULL;
     dedic_gpio_bundle_config_t bundleA_config = {
         .gpio_array = bundleA_gpios,
@@ -90,15 +82,8 @@ static void test_dedic_gpio_on_specific_core(void *args)
     };
     TEST_ESP_OK(dedic_gpio_new_bundle(&bundleA_config, &bundleA));
 
-    // configure another group of GPIOs, input and output
-    const int bundleB_gpios[] = {ctx->gpios[2], ctx->gpios[3]};
-    io_conf.mode = GPIO_MODE_INPUT_OUTPUT;
-    for (int i = 0; i < sizeof(bundleB_gpios) / sizeof(bundleB_gpios[0]); i++) {
-        io_conf.pin_bit_mask = 1ULL << bundleB_gpios[i];
-        gpio_config(&io_conf);
-    }
-
     // GPIO bundleB, input and output
+    const int bundleB_gpios[] = {ctx->gpios[2], ctx->gpios[3]};
     dedic_gpio_bundle_handle_t bundleB = NULL;
     dedic_gpio_bundle_config_t bundleB_config = {
         .gpio_array = bundleB_gpios,
@@ -192,13 +177,6 @@ TEST_CASE("Dedicated_GPIO_interrupt_and_callback", "[dedic_gpio]")
 #else
     const int bundle_gpios[] = {0, 1};
 #endif
-    gpio_config_t io_conf = {
-        .mode = GPIO_MODE_INPUT_OUTPUT,
-    };
-    for (int i = 0; i < sizeof(bundle_gpios) / sizeof(bundle_gpios[0]); i++) {
-        io_conf.pin_bit_mask = 1ULL << bundle_gpios[i];
-        gpio_config(&io_conf);
-    }
     dedic_gpio_bundle_handle_t bundle = NULL;
     dedic_gpio_bundle_config_t bundle_config = {
         .gpio_array = bundle_gpios,
diff --git a/components/esp_driver_gptimer/src/gptimer_common.c b/components/esp_driver_gptimer/src/gptimer_common.c
index 928ce3c84ad..8338ebb2f49 100644
--- a/components/esp_driver_gptimer/src/gptimer_common.c
+++ b/components/esp_driver_gptimer/src/gptimer_common.c
@@ -27,24 +27,21 @@ static esp_err_t gptimer_create_sleep_retention_link_cb(void *arg)
 {
     gptimer_group_t *group = (gptimer_group_t *)arg;
     int group_id = group->group_id;
-    sleep_retention_module_t module = group->sleep_retention_module;
     esp_err_t err = sleep_retention_entries_create(tg_timer_reg_retention_info[group_id].regdma_entry_array,
                                                    tg_timer_reg_retention_info[group_id].array_size,
-                                                   REGDMA_LINK_PRI_GPTIMER, module);
-    ESP_RETURN_ON_ERROR(err, TAG, "create retention link failed");
-    return ESP_OK;
+                                                   REGDMA_LINK_PRI_GPTIMER, tg_timer_reg_retention_info[group_id].module);
+    return err;
 }
 
 void gptimer_create_retention_module(gptimer_group_t *group)
 {
-    sleep_retention_module_t module = group->sleep_retention_module;
+    int group_id = group->group_id;
+    sleep_retention_module_t module = tg_timer_reg_retention_info[group_id].module;
     _lock_acquire(&s_platform.mutex);
-    if (group->retention_link_created == false) {
+    if ((sleep_retention_get_inited_modules() & BIT(module)) && !(sleep_retention_get_created_modules() & BIT(module))) {
         if (sleep_retention_module_allocate(module) != ESP_OK) {
             // even though the sleep retention module create failed, GPTimer driver should still work, so just warning here
-            ESP_LOGW(TAG, "create retention module for group %d retention, power domain can't turn off", group->group_id);
-        } else {
-            group->retention_link_created = true;
+            ESP_LOGW(TAG, "create retention link failed %d, power domain won't be turned off during sleep", group_id);
         }
     }
     _lock_release(&s_platform.mutex);
@@ -97,9 +94,7 @@ gptimer_group_t *gptimer_acquire_group_handle(int group_id)
             },
             .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM)
         };
-        if (sleep_retention_module_init(module, &init_param) == ESP_OK) {
-            group->sleep_retention_module = module;
-        } else {
+        if (sleep_retention_module_init(module, &init_param) != ESP_OK) {
             // even though the sleep retention module init failed, RMT driver should still work, so just warning here
             ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id);
         }
@@ -132,11 +127,12 @@ void gptimer_release_group_handle(gptimer_group_t *group)
             }
         }
 #if GPTIMER_USE_RETENTION_LINK
-        if (group->sleep_retention_module) {
-            if (group->retention_link_created) {
-                sleep_retention_module_free(group->sleep_retention_module);
-            }
-            sleep_retention_module_deinit(group->sleep_retention_module);
+        sleep_retention_module_t module = tg_timer_reg_retention_info[group_id].module;
+        if (sleep_retention_get_created_modules() & BIT(module)) {
+            sleep_retention_module_free(module);
+        }
+        if (sleep_retention_get_inited_modules() & BIT(module)) {
+            sleep_retention_module_deinit(module);
         }
 #endif
         free(group);
diff --git a/components/esp_driver_gptimer/src/gptimer_priv.h b/components/esp_driver_gptimer/src/gptimer_priv.h
index 3c117af44f9..b5d4d1c0e66 100644
--- a/components/esp_driver_gptimer/src/gptimer_priv.h
+++ b/components/esp_driver_gptimer/src/gptimer_priv.h
@@ -59,10 +59,6 @@ typedef struct gptimer_group_t {
     int group_id;
     portMUX_TYPE spinlock; // to protect per-group register level concurrent access
     gptimer_t *timers[SOC_TIMER_GROUP_TIMERS_PER_GROUP];
-#if GPTIMER_USE_RETENTION_LINK
-    sleep_retention_module_t sleep_retention_module; // sleep retention module
-    bool retention_link_created;       // mark if the retention link is created
-#endif
 } gptimer_group_t;
 
 typedef enum {
diff --git a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c
index 34a43715989..5b7e5879d57 100644
--- a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c
+++ b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c
@@ -10,6 +10,8 @@
 #include "freertos/task.h"
 #include "unity.h"
 #include "driver/gptimer.h"
+#include "driver/gpio_etm.h"
+#include "driver/gpio.h"
 #include "soc/soc_caps.h"
 #include "esp_sleep.h"
 #include "esp_private/sleep_cpu.h"
@@ -117,3 +119,135 @@ TEST_CASE("gptimer can work after light sleep", "[gptimer]")
     test_gptimer_sleep_retention(true);
 #endif
 }
+
+#if SOC_TIMER_SUPPORT_ETM
+/**
+ * @brief Test the GPTimer and ETM subsystem can still work after light sleep
+ *
+ * @param back_up_before_sleep Whether to back up GPTimer registers before sleep
+ */
+static void test_gptimer_etm_sleep_retention(bool back_up_before_sleep)
+{
+    const uint32_t output_gpio = 1;
+    // GPTimer alarm ---> ETM channel A ---> GPTimer alarm re-enable
+    // GPTimer alarm ---> ETM channel B ---> GPIO toggle
+    printf("allocate etm channel\r\n");
+    esp_etm_channel_config_t etm_config = {
+        .flags.allow_pd = back_up_before_sleep,
+    };
+    esp_etm_channel_handle_t etm_channel_a, etm_channel_b;
+    TEST_ESP_OK(esp_etm_new_channel(&etm_config, &etm_channel_a));
+    TEST_ESP_OK(esp_etm_new_channel(&etm_config, &etm_channel_b));
+
+    printf("initialize gpio\r\n");
+    gpio_config_t task_gpio_config = {
+        .intr_type = GPIO_INTR_DISABLE,
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = 1ULL << output_gpio,
+    };
+    TEST_ESP_OK(gpio_config(&task_gpio_config));
+
+    printf("create a gptimer\r\n");
+    gptimer_handle_t gptimer = NULL;
+    gptimer_config_t timer_config = {
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
+        .direction = GPTIMER_COUNT_UP,
+        .resolution_hz = 1 * 1000 * 1000, // 1MHz, 1 tick = 1us
+        .flags.backup_before_sleep = back_up_before_sleep,
+    };
+    TEST_ESP_OK(gptimer_new_timer(&timer_config, &gptimer));
+
+    printf("get gptimer etm event and task handle\r\n");
+    esp_etm_event_handle_t gptimer_event = NULL;
+    gptimer_etm_event_config_t gptimer_etm_event_conf = {
+        .event_type = GPTIMER_ETM_EVENT_ALARM_MATCH,
+    };
+    TEST_ESP_OK(gptimer_new_etm_event(gptimer, &gptimer_etm_event_conf, &gptimer_event));
+    esp_etm_task_handle_t gptimer_task = NULL;
+    gptimer_etm_task_config_t gptimer_etm_task_conf = {
+        .task_type = GPTIMER_ETM_TASK_EN_ALARM,
+    };
+    TEST_ESP_OK(gptimer_new_etm_task(gptimer, &gptimer_etm_task_conf, & gptimer_task));
+
+    printf("connect event and task to the channel a\r\n");
+    TEST_ESP_OK(esp_etm_channel_connect(etm_channel_a, gptimer_event, gptimer_task));
+
+    printf("enable etm channels\r\n");
+    TEST_ESP_OK(esp_etm_channel_enable(etm_channel_a));
+    TEST_ESP_OK(esp_etm_channel_enable(etm_channel_b));
+
+    printf("set timer alarm action\r\n");
+    gptimer_alarm_config_t alarm_config = {
+        .reload_count = 0,
+        .alarm_count = 100, // 100us per alarm event
+        .flags.auto_reload_on_alarm = true,
+    };
+    TEST_ESP_OK(gptimer_set_alarm_action(gptimer, &alarm_config));
+
+    // before going to sleep, ensure the gptimer is not enabled yet, otherwise it will acquire power management lock
+
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+    printf("go to light sleep for 2 seconds\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
+    TEST_ESP_OK(esp_light_sleep_start());
+
+    printf("Waked up! Let's see if GPTimer and ETM can still work...\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+
+    printf("check if the sleep happened as expected\r\n");
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_RMT_SUPPORT_SLEEP_RETENTION
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL(back_up_before_sleep ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+    esp_sleep_set_sleep_context(NULL);
+
+    printf("enable and start timer\r\n");
+    TEST_ESP_OK(gptimer_enable(gptimer));
+    TEST_ESP_OK(gptimer_start(gptimer));
+
+    printf("allocate GPIO etm task\r\n");
+    esp_etm_task_handle_t gpio_task = NULL;
+    gpio_etm_task_config_t gpio_task_config = {
+        .action = GPIO_ETM_TASK_ACTION_TOG,
+    };
+    TEST_ESP_OK(gpio_new_etm_task(&gpio_task_config, &gpio_task));
+    // set gpio number for the gpio etm primitives
+    TEST_ESP_OK(gpio_etm_task_add_gpio(gpio_task, output_gpio));
+    printf("connect event and task to the channel b\r\n");
+    TEST_ESP_OK(esp_etm_channel_connect(etm_channel_b, gptimer_event, gpio_task));
+
+    // delay sometime for us to view the waveform, should see a 5KHz square waveform
+    vTaskDelay(pdMS_TO_TICKS(1000));
+
+    // delete gptimer
+    TEST_ESP_OK(gptimer_stop(gptimer));
+    TEST_ESP_OK(gptimer_disable(gptimer));
+    TEST_ESP_OK(gptimer_del_timer(gptimer));
+
+    // delete etm primitives
+    TEST_ESP_OK(gpio_etm_task_rm_gpio(gpio_task, output_gpio));
+    TEST_ESP_OK(esp_etm_del_task(gpio_task));
+    TEST_ESP_OK(esp_etm_del_task(gptimer_task));
+    TEST_ESP_OK(esp_etm_del_event(gptimer_event));
+    TEST_ESP_OK(esp_etm_channel_disable(etm_channel_a));
+    TEST_ESP_OK(esp_etm_channel_disable(etm_channel_b));
+    TEST_ESP_OK(esp_etm_del_channel(etm_channel_a));
+    TEST_ESP_OK(esp_etm_del_channel(etm_channel_b));
+}
+
+TEST_CASE("gptimer and ETM can work after light sleep", "[gptimer]")
+{
+    test_gptimer_etm_sleep_retention(false);
+#if SOC_TIMER_SUPPORT_SLEEP_RETENTION && SOC_ETM_SUPPORT_SLEEP_RETENTION
+    test_gptimer_etm_sleep_retention(true);
+#endif
+}
+
+#endif // SOC_TIMER_SUPPORT_ETM
diff --git a/components/esp_driver_i2c/CMakeLists.txt b/components/esp_driver_i2c/CMakeLists.txt
index 699cf0b5d32..0a6f42a8f3b 100644
--- a/components/esp_driver_i2c/CMakeLists.txt
+++ b/components/esp_driver_i2c/CMakeLists.txt
@@ -10,7 +10,11 @@ if(CONFIG_SOC_I2C_SUPPORTED)
                      "i2c_common.c"
         )
     if(CONFIG_SOC_I2C_SUPPORT_SLAVE)
-        list(APPEND srcs "i2c_slave.c")
+        if(CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2)
+            list(APPEND srcs "i2c_slave_v2.c")
+        else()
+            list(APPEND srcs "i2c_slave.c")
+        endif()
     endif()
 
 endif()
diff --git a/components/esp_driver_i2c/Kconfig b/components/esp_driver_i2c/Kconfig
index d8156fddf3a..294aa05977d 100644
--- a/components/esp_driver_i2c/Kconfig
+++ b/components/esp_driver_i2c/Kconfig
@@ -17,4 +17,10 @@ menu "ESP-Driver:I2C Configurations"
 
             note: This cannot be used in the I2C legacy driver.
 
+    config I2C_ENABLE_SLAVE_DRIVER_VERSION_2
+        bool "Enable I2C slave driver version 2"
+        default n
+        help
+            I2C slave version 2 solves some existing known issues. Such as write/read workflow, stretch handling, etc.
+
 endmenu # I2C Configurations
diff --git a/components/esp_driver_i2c/i2c_common.c b/components/esp_driver_i2c/i2c_common.c
index 87bad063b03..87042b404ae 100644
--- a/components/esp_driver_i2c/i2c_common.c
+++ b/components/esp_driver_i2c/i2c_common.c
@@ -33,7 +33,7 @@
 #include "soc/rtc_io_channel.h"
 #include "driver/lp_io.h"
 #endif
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+#if I2C_USE_RETENTION_LINK
 #include "esp_private/sleep_retention.h"
 #endif
 
@@ -47,15 +47,31 @@ typedef struct i2c_platform_t {
 
 static i2c_platform_t s_i2c_platform = {}; // singleton platform
 
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
+#if I2C_USE_RETENTION_LINK
 static esp_err_t s_i2c_sleep_retention_init(void *arg)
 {
     i2c_bus_t *bus = (i2c_bus_t *)arg;
     i2c_port_num_t port_num = bus->port_num;
-    esp_err_t ret = sleep_retention_entries_create(i2c_regs_retention[port_num].link_list, i2c_regs_retention[port_num].link_num, REGDMA_LINK_PRI_I2C, I2C_SLEEP_RETENTION_MODULE(port_num));
+    esp_err_t ret = sleep_retention_entries_create(i2c_regs_retention[port_num].link_list, i2c_regs_retention[port_num].link_num, REGDMA_LINK_PRI_I2C, i2c_regs_retention[port_num].module_id);
     ESP_RETURN_ON_ERROR(ret, TAG, "failed to allocate mem for sleep retention");
     return ret;
 }
+
+void i2c_create_retention_module(i2c_bus_handle_t handle)
+{
+    i2c_port_num_t port_num = handle->port_num;
+    _lock_acquire(&s_i2c_platform.mutex);
+    if (handle->retention_link_created == false) {
+        if (sleep_retention_module_allocate(i2c_regs_retention[port_num].module_id) != ESP_OK) {
+            // even though the sleep retention module create failed, I2C driver should still work, so just warning here
+            ESP_LOGW(TAG, "create retention module failed, power domain can't turn off");
+        } else {
+            handle->retention_link_created = true;
+        }
+    }
+    _lock_release(&s_i2c_platform.mutex);
+
+}
 #endif
 
 static esp_err_t s_i2c_bus_handle_acquire(i2c_port_num_t port_num, i2c_bus_handle_t *i2c_new_bus, i2c_bus_mode_t mode)
@@ -77,14 +93,14 @@ static esp_err_t s_i2c_bus_handle_acquire(i2c_port_num_t port_num, i2c_bus_handl
             bus->bus_mode = mode;
             bus->is_lp_i2c = (bus->port_num < SOC_HP_I2C_NUM) ? false : true;
 
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
+#if I2C_USE_RETENTION_LINK
             if (bus->is_lp_i2c == false) {
                 sleep_retention_module_init_param_t init_param = {
                     .cbs = { .create = { .handle = s_i2c_sleep_retention_init, .arg = (void *)bus } }
                 };
-                ret = sleep_retention_module_init(I2C_SLEEP_RETENTION_MODULE(port_num), &init_param);
-                if (ret == ESP_OK) {
-                    sleep_retention_module_allocate(I2C_SLEEP_RETENTION_MODULE(port_num));
+                esp_err_t err = sleep_retention_module_init(i2c_regs_retention[port_num].module_id, &init_param);
+                if (err != ESP_OK) {
+                    ESP_LOGW(TAG, "init sleep retention failed on bus %d, power domain may be turned off during sleep", port_num);
                 }
             } else {
                 ESP_LOGW(TAG, "Detected PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP is enabled while LP_I2C is used. Sleep retention is not supported on LP I2C. Please use it properly");
@@ -175,12 +191,12 @@ esp_err_t i2c_release_bus_handle(i2c_bus_handle_t i2c_bus)
         if (s_i2c_platform.count[port_num] == 0) {
             do_deinitialize = true;
             s_i2c_platform.buses[port_num] = NULL;
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_I2C_SUPPORT_SLEEP_RETENTION
+#if I2C_USE_RETENTION_LINK
             if (i2c_bus->is_lp_i2c == false) {
-                esp_err_t err = sleep_retention_module_free(I2C_SLEEP_RETENTION_MODULE(port_num));
-                if (err == ESP_OK) {
-                    err = sleep_retention_module_deinit(I2C_SLEEP_RETENTION_MODULE(port_num));
+                if (i2c_bus->retention_link_created) {
+                    sleep_retention_module_free(i2c_regs_retention[port_num].module_id);
                 }
+                sleep_retention_module_deinit(i2c_regs_retention[port_num].module_id);
             }
 #endif
             if (i2c_bus->intr_handle) {
@@ -296,29 +312,27 @@ static esp_err_t s_hp_i2c_pins_config(i2c_bus_handle_t handle)
     int port_id = handle->port_num;
 
     // SDA pin configurations
-    gpio_config_t sda_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        .mode = GPIO_MODE_INPUT_OUTPUT_OD,
-        .pull_down_en = false,
-        .pull_up_en = handle->pull_up_enable ? GPIO_PULLUP_ENABLE : GPIO_PULLUP_DISABLE,
-        .pin_bit_mask = 1ULL << handle->sda_num,
-    };
     ESP_RETURN_ON_ERROR(gpio_set_level(handle->sda_num, 1), TAG, "i2c sda pin set level failed");
-    ESP_RETURN_ON_ERROR(gpio_config(&sda_conf), TAG, "config GPIO failed");
+    gpio_input_enable(handle->sda_num);
+    gpio_od_enable(handle->sda_num);
+    if (handle->pull_up_enable) {
+        gpio_pullup_en(handle->sda_num);
+    } else {
+        gpio_pullup_dis(handle->sda_num);
+    }
     gpio_func_sel(handle->sda_num, PIN_FUNC_GPIO);
     esp_rom_gpio_connect_out_signal(handle->sda_num, i2c_periph_signal[port_id].sda_out_sig, 0, 0);
     esp_rom_gpio_connect_in_signal(handle->sda_num, i2c_periph_signal[port_id].sda_in_sig, 0);
 
     // SCL pin configurations
-    gpio_config_t scl_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        .mode = GPIO_MODE_INPUT_OUTPUT_OD,
-        .pull_down_en = false,
-        .pull_up_en = handle->pull_up_enable ? GPIO_PULLUP_ENABLE : GPIO_PULLUP_DISABLE,
-        .pin_bit_mask = 1ULL << handle->scl_num,
-    };
     ESP_RETURN_ON_ERROR(gpio_set_level(handle->scl_num, 1), TAG, "i2c scl pin set level failed");
-    ESP_RETURN_ON_ERROR(gpio_config(&scl_conf), TAG, "config GPIO failed");
+    gpio_input_enable(handle->scl_num);
+    gpio_od_enable(handle->scl_num);
+    if (handle->pull_up_enable) {
+        gpio_pullup_en(handle->scl_num);
+    } else {
+        gpio_pullup_dis(handle->scl_num);
+    }
     gpio_func_sel(handle->scl_num, PIN_FUNC_GPIO);
     esp_rom_gpio_connect_out_signal(handle->scl_num, i2c_periph_signal[port_id].scl_out_sig, 0, 0);
     esp_rom_gpio_connect_in_signal(handle->scl_num, i2c_periph_signal[port_id].scl_in_sig, 0);
@@ -390,3 +404,28 @@ esp_err_t i2c_common_set_pins(i2c_bus_handle_t handle)
 
     return ret;
 }
+
+esp_err_t i2c_common_deinit_pins(i2c_bus_handle_t handle)
+{
+    int port_id = handle->port_num;
+
+    if (handle->is_lp_i2c == false) {
+        ESP_RETURN_ON_ERROR(gpio_output_disable(handle->sda_num), TAG, "disable i2c pins failed");
+        esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].sda_in_sig, 0);
+
+        ESP_RETURN_ON_ERROR(gpio_output_disable(handle->scl_num), TAG, "disable i2c pins failed");
+        esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].scl_in_sig, 0);
+    }
+#if SOC_LP_I2C_SUPPORTED
+    else {
+        ESP_RETURN_ON_ERROR(rtc_gpio_deinit(handle->sda_num), TAG, "deinit rtc gpio failed");
+        ESP_RETURN_ON_ERROR(rtc_gpio_deinit(handle->scl_num), TAG, "deinit rtc gpio failed");
+#if SOC_LP_GPIO_MATRIX_SUPPORTED
+        lp_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].scl_in_sig, 0);
+        lp_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, i2c_periph_signal[port_id].sda_in_sig, 0);
+#endif
+    }
+#endif
+
+    return ESP_OK;
+}
diff --git a/components/esp_driver_i2c/i2c_master.c b/components/esp_driver_i2c/i2c_master.c
index ad18d2806d3..44a6cff3885 100644
--- a/components/esp_driver_i2c/i2c_master.c
+++ b/components/esp_driver_i2c/i2c_master.c
@@ -784,7 +784,12 @@ static esp_err_t i2c_master_bus_destroy(i2c_master_bus_handle_t bus_handle)
 {
     ESP_RETURN_ON_FALSE(bus_handle, ESP_ERR_INVALID_ARG, TAG, "no memory for i2c master bus");
     i2c_master_bus_handle_t i2c_master = bus_handle;
-    if (i2c_release_bus_handle(i2c_master->base) == ESP_OK) {
+    esp_err_t err = ESP_OK;
+    if (i2c_master->base) {
+        i2c_common_deinit_pins(i2c_master->base);
+        err = i2c_release_bus_handle(i2c_master->base);
+    }
+    if (err == ESP_OK) {
         if (i2c_master) {
             if (i2c_master->bus_lock_mux) {
                 vSemaphoreDeleteWithCaps(i2c_master->bus_lock_mux);
@@ -932,6 +937,10 @@ esp_err_t i2c_new_master_bus(const i2c_master_bus_config_t *bus_config, i2c_mast
     ESP_RETURN_ON_FALSE((bus_config->i2c_port < SOC_I2C_NUM || bus_config->i2c_port == -1), ESP_ERR_INVALID_ARG, TAG, "invalid i2c port number");
     ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(bus_config->sda_io_num) && GPIO_IS_VALID_GPIO(bus_config->scl_io_num), ESP_ERR_INVALID_ARG, TAG, "invalid SDA/SCL pin number");
 
+#if !SOC_I2C_SUPPORT_SLEEP_RETENTION
+    ESP_RETURN_ON_FALSE(bus_config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep");
+#endif // SOC_I2C_SUPPORT_SLEEP_RETENTION
+
     i2c_master = heap_caps_calloc(1, sizeof(i2c_master_bus_t) + 20 * sizeof(i2c_transaction_t), I2C_MEM_ALLOC_CAPS);
 
     ESP_RETURN_ON_FALSE(i2c_master, ESP_ERR_NO_MEM, TAG, "no memory for i2c master bus");
@@ -980,6 +989,12 @@ esp_err_t i2c_new_master_bus(const i2c_master_bus_config_t *bus_config, i2c_mast
         ESP_RETURN_ON_FALSE(1 << (bus_config->intr_priority) & I2C_ALLOW_INTR_PRIORITY_MASK, ESP_ERR_INVALID_ARG, TAG, "invalid interrupt priority:%d", bus_config->intr_priority);
     }
 
+#if I2C_USE_RETENTION_LINK
+    if (bus_config->flags.allow_pd != 0) {
+        i2c_create_retention_module(i2c_master->base);
+    }
+#endif // I2C_USE_RETENTION_LINK
+
     xSemaphoreTake(i2c_master->bus_lock_mux, portMAX_DELAY);
     SLIST_INIT(&i2c_master->device_list);
     xSemaphoreGive(i2c_master->bus_lock_mux);
diff --git a/components/esp_driver_i2c/i2c_private.h b/components/esp_driver_i2c/i2c_private.h
index a78dfdd0674..5dd06fa259a 100644
--- a/components/esp_driver_i2c/i2c_private.h
+++ b/components/esp_driver_i2c/i2c_private.h
@@ -19,6 +19,7 @@
 #include "driver/i2c_slave.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_pm.h"
+#include "sdkconfig.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -54,6 +55,9 @@ extern "C" {
 #define I2C_INTR_ALLOC_FLAG     (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED)
 #endif
 
+// Use retention link only when the target supports sleep retention and PM is enabled
+#define I2C_USE_RETENTION_LINK  (SOC_I2C_SUPPORT_SLEEP_RETENTION && CONFIG_PM_ENABLE && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+
 #define I2C_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED
 
 #define I2C_PM_LOCK_NAME_LEN_MAX 16
@@ -119,6 +123,9 @@ struct i2c_bus_t {
     char pm_lock_name[I2C_PM_LOCK_NAME_LEN_MAX]; // pm lock name
 #endif
     i2c_bus_mode_t bus_mode; // I2C bus mode
+#if SOC_I2C_SUPPORT_SLEEP_RETENTION
+    bool retention_link_created;     // mark if the retention link is created.
+#endif
 };
 
 typedef struct i2c_master_device_list {
@@ -190,6 +197,8 @@ typedef struct {
     uint32_t rcv_fifo_cnt;      // receive fifo count.
 } i2c_slave_receive_t;
 
+#if !CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2
+
 struct i2c_slave_dev_t {
     i2c_bus_t *base;                            // bus base class
     SemaphoreHandle_t slv_rx_mux;               // Mutex for slave rx direction
@@ -207,6 +216,22 @@ struct i2c_slave_dev_t {
     uint32_t already_receive_len;               // Data length already received in ISR.
 };
 
+#else // CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2
+
+struct i2c_slave_dev_t {
+    i2c_bus_t *base;                                  // bus base class
+    SemaphoreHandle_t operation_mux;                  // Mux for i2c slave operation
+    i2c_slave_request_callback_t request_callback;    // i2c slave request callback
+    i2c_slave_received_callback_t receive_callback;   // i2c_slave receive callback
+    void *user_ctx;                                   // Callback user context
+    RingbufHandle_t rx_ring_buf;                      // receive ringbuffer
+    RingbufHandle_t tx_ring_buf;                      // transmit ringbuffer
+    uint32_t rx_data_count;                           // receive data count
+    i2c_slave_receive_t receive_desc;                 // slave receive descriptor
+};
+
+#endif // CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2
+
 /**
  * @brief Acquire I2C bus handle
  *
@@ -252,6 +277,17 @@ esp_err_t i2c_select_periph_clock(i2c_bus_handle_t handle, soc_module_clk_t clk_
  */
 esp_err_t i2c_common_set_pins(i2c_bus_handle_t handle);
 
+/**
+ * @brief Deinit I2C SCL/SDA pins
+ *
+ * @param handle I2C bus handle
+ * @return
+ *      - ESP_OK: I2C set SCL/SDA pins successfully.
+ *      - ESP_ERR_INVALID_ARG: Argument error.
+ *      - Otherwise: Set SCL/SDA IOs error.
+ */
+esp_err_t i2c_common_deinit_pins(i2c_bus_handle_t handle);
+
 /**
  * @brief Check whether bus is acquired
  *
@@ -260,6 +296,13 @@ esp_err_t i2c_common_set_pins(i2c_bus_handle_t handle);
 */
 bool i2c_bus_occupied(i2c_port_num_t port_num);
 
+/**
+ * @brief Create sleep retention link
+ *
+ * @param handle I2C bus handle
+ */
+void i2c_create_retention_module(i2c_bus_handle_t handle);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_i2c/i2c_slave.c b/components/esp_driver_i2c/i2c_slave.c
index 6b000ef66ed..b5f16fb9fc0 100644
--- a/components/esp_driver_i2c/i2c_slave.c
+++ b/components/esp_driver_i2c/i2c_slave.c
@@ -235,6 +235,12 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
     ret = esp_intr_alloc_intrstatus(i2c_periph_signal[i2c_port_num].irq, isr_flags, (uint32_t)i2c_ll_get_interrupt_status_reg(hal->dev), I2C_LL_SLAVE_EVENT_INTR, s_slave_isr_handle_default, i2c_slave, &i2c_slave->base->intr_handle);
     ESP_GOTO_ON_ERROR(ret, err, TAG, "install i2c slave interrupt failed");
 
+#if I2C_USE_RETENTION_LINK
+    if (slave_config->flags.allow_pd != 0) {
+        i2c_create_retention_module(i2c_slave->base);
+    }
+#endif // I2C_USE_RETENTION_LINK
+
     portENTER_CRITICAL(&i2c_slave->base->spinlock);
     i2c_ll_clear_intr_mask(hal->dev, I2C_LL_SLAVE_EVENT_INTR);
     i2c_hal_slave_init(hal);
@@ -288,6 +294,7 @@ static esp_err_t i2c_slave_bus_destroy(i2c_slave_dev_handle_t i2c_slave)
 {
     if (i2c_slave) {
         i2c_ll_disable_intr_mask(i2c_slave->base->hal.dev, I2C_LL_SLAVE_EVENT_INTR);
+        i2c_common_deinit_pins(i2c_slave->base);
         if (i2c_slave->slv_rx_mux) {
             vSemaphoreDeleteWithCaps(i2c_slave->slv_rx_mux);
             i2c_slave->slv_rx_mux = NULL;
diff --git a/components/esp_driver_i2c/i2c_slave_v2.c b/components/esp_driver_i2c/i2c_slave_v2.c
new file mode 100644
index 00000000000..773a468c031
--- /dev/null
+++ b/components/esp_driver_i2c/i2c_slave_v2.c
@@ -0,0 +1,433 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
+#include "esp_attr.h"
+#include "esp_rom_gpio.h"
+#include "driver/gpio.h"
+#include "hal/gpio_ll.h"
+#include "esp_err.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "freertos/ringbuf.h"
+#include "esp_intr_alloc.h"
+#include "hal/i2c_ll.h"
+#include "i2c_private.h"
+#include "driver/i2c_slave.h"
+#include "esp_memory_utils.h"
+#if CONFIG_I2C_ENABLE_DEBUG_LOG
+// The local log level must be defined before including esp_log.h
+// Set the maximum log level for this source file
+#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
+#endif
+#include "esp_log.h"
+#include "esp_check.h"
+
+static const char *TAG = "i2c.slave";
+
+IRAM_ATTR static bool i2c_slave_read_rx(i2c_slave_dev_t *i2c_slave, uint8_t *data, size_t len, size_t *read_len)
+{
+    BaseType_t xTaskWoken = pdFALSE;
+    size_t read_size = len;
+    size_t actual_size = 0;
+    size_t available_size = 0;
+    size_t get_size = 0;
+    uint8_t *rx_data = NULL;
+
+    vRingbufferGetInfo(i2c_slave->rx_ring_buf, NULL, NULL, NULL, NULL, &available_size);
+    if (available_size < read_size) {
+        read_size = available_size;
+    }
+
+    while (read_size) {
+        actual_size = 0;
+        rx_data = (uint8_t *)xRingbufferReceiveUpToFromISR(i2c_slave->rx_ring_buf, &actual_size, read_size);
+        if (rx_data != NULL && actual_size != 0) {
+            memcpy(data + get_size, rx_data, actual_size);
+            vRingbufferReturnItemFromISR(i2c_slave->rx_ring_buf, rx_data, &xTaskWoken);
+            get_size += actual_size;
+            read_size -= actual_size;
+        } else {
+            break;
+        }
+    }
+    *read_len = get_size;
+    return xTaskWoken;
+}
+
+IRAM_ATTR static bool i2c_slave_handle_tx_fifo(i2c_slave_dev_t *i2c_slave)
+{
+    BaseType_t xTaskWoken = pdFALSE;
+    i2c_hal_context_t *hal = &i2c_slave->base->hal;
+    uint8_t *data;
+    uint32_t fifo_len = 0;
+    xSemaphoreTakeFromISR(i2c_slave->operation_mux, &xTaskWoken);
+    i2c_ll_get_txfifo_len(hal->dev, &fifo_len);
+    size_t actual_get_len = 0;
+    while (fifo_len > 0) {
+        data = xRingbufferReceiveUpToFromISR(i2c_slave->tx_ring_buf, &actual_get_len, fifo_len);
+        if (data) {
+            portENTER_CRITICAL_ISR(&i2c_slave->base->spinlock);
+            i2c_ll_write_txfifo(hal->dev, data, actual_get_len);
+            fifo_len -= actual_get_len;
+            portEXIT_CRITICAL_ISR(&i2c_slave->base->spinlock);
+            vRingbufferReturnItemFromISR(i2c_slave->tx_ring_buf, data, &xTaskWoken);
+        } else {
+            // No data in ringbuffer, so disable the tx interrupt.
+            i2c_ll_slave_disable_tx_it(hal->dev);
+            break;
+        }
+    }
+    xSemaphoreGiveFromISR(i2c_slave->operation_mux, &xTaskWoken);
+    return xTaskWoken;
+}
+
+IRAM_ATTR static bool i2c_slave_handle_rx_fifo(i2c_slave_dev_t *i2c_slave, uint32_t len)
+{
+    i2c_hal_context_t *hal = &i2c_slave->base->hal;
+    uint8_t data[SOC_I2C_FIFO_LEN];
+    BaseType_t xTaskWoken = pdFALSE;
+    xSemaphoreTakeFromISR(i2c_slave->operation_mux, &xTaskWoken);
+    if (len) {
+        portENTER_CRITICAL_ISR(&i2c_slave->base->spinlock);
+        i2c_ll_read_rxfifo(hal->dev, data, len);
+        portEXIT_CRITICAL_ISR(&i2c_slave->base->spinlock);
+        BaseType_t res = xRingbufferSendFromISR(i2c_slave->rx_ring_buf, (void *)data, len, &xTaskWoken);
+        if (res == pdTRUE) {
+            i2c_slave->rx_data_count += len;
+        }
+    }
+    xSemaphoreTakeFromISR(i2c_slave->operation_mux, &xTaskWoken);
+    return xTaskWoken;
+}
+
+#if SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+IRAM_ATTR static bool i2c_slave_handle_stretch_event(i2c_slave_dev_t *i2c_slave, uint32_t rx_fifo_exist_len)
+{
+    i2c_slave_stretch_cause_t cause;
+    BaseType_t xTaskWoken = pdFALSE;
+    i2c_hal_context_t *hal = &i2c_slave->base->hal;
+    i2c_ll_slave_get_stretch_cause(hal->dev, &cause);
+    if (cause == I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH) {
+        if (rx_fifo_exist_len) {
+            xTaskWoken |= i2c_slave_handle_rx_fifo(i2c_slave, rx_fifo_exist_len);
+        }
+        if (i2c_slave->rx_data_count) {
+            uint32_t len = i2c_slave->rx_data_count;
+            size_t read_len;
+            xTaskWoken |= i2c_slave_read_rx(i2c_slave, i2c_slave->receive_desc.buffer, len, &read_len);
+            i2c_slave_rx_done_event_data_t edata = {};
+            edata.buffer = i2c_slave->receive_desc.buffer;
+            edata.length = read_len;
+            if (i2c_slave->receive_callback) {
+                xTaskWoken |= i2c_slave->receive_callback(i2c_slave, &edata, i2c_slave->user_ctx);
+            }
+            i2c_slave->rx_data_count = 0;
+        }
+        i2c_slave_request_event_data_t evt_data = {};
+        if (i2c_slave->request_callback) {
+            xTaskWoken |= i2c_slave->request_callback(i2c_slave, &evt_data, i2c_slave->user_ctx);
+        }
+        //will clear after request callback
+    } else if (cause == I2C_SLAVE_STRETCH_CAUSE_TX_EMPTY) {
+        xTaskWoken |= i2c_slave_handle_tx_fifo(i2c_slave);
+        i2c_ll_slave_clear_stretch(hal->dev);
+    } else if (cause == I2C_SLAVE_STRETCH_CAUSE_RX_FULL) {
+        xTaskWoken |= i2c_slave_handle_rx_fifo(i2c_slave, rx_fifo_exist_len);
+        i2c_ll_slave_clear_stretch(hal->dev);
+    }
+    return xTaskWoken;
+}
+#endif
+
+IRAM_ATTR static void i2c_slave_isr_handler(void *arg)
+{
+    BaseType_t pxHigherPriorityTaskWoken = false;
+    i2c_slave_dev_t *i2c_slave = (i2c_slave_dev_t *)arg;
+
+    i2c_hal_context_t *hal = &i2c_slave->base->hal;
+    uint32_t int_mask = 0;
+    i2c_ll_get_intr_mask(hal->dev, &int_mask);
+    i2c_ll_clear_intr_mask(hal->dev, int_mask);
+    uint32_t rx_fifo_exist_len = 0;
+    i2c_ll_get_rxfifo_cnt(hal->dev, &rx_fifo_exist_len);
+    i2c_slave_read_write_status_t slave_rw = i2c_ll_slave_get_read_write_status(hal->dev);
+
+    if (int_mask & I2C_INTR_SLV_RXFIFO_WM) {
+        pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo(i2c_slave, rx_fifo_exist_len);
+    }
+
+    if (int_mask & I2C_INTR_SLV_COMPLETE) {
+        if (rx_fifo_exist_len) {
+            pxHigherPriorityTaskWoken |= i2c_slave_handle_rx_fifo(i2c_slave, rx_fifo_exist_len);
+        }
+        if (i2c_slave->rx_data_count) {
+            uint32_t len = i2c_slave->rx_data_count;
+            size_t read_len;
+            pxHigherPriorityTaskWoken |= i2c_slave_read_rx(i2c_slave, i2c_slave->receive_desc.buffer, len, &read_len);
+            i2c_slave_rx_done_event_data_t edata = {};
+            edata.buffer = i2c_slave->receive_desc.buffer;
+            edata.length = read_len;
+            if (i2c_slave->receive_callback) {
+                pxHigherPriorityTaskWoken |= i2c_slave->receive_callback(i2c_slave, &edata, i2c_slave->user_ctx);
+            }
+            i2c_slave->rx_data_count = 0;
+        }
+        if (slave_rw == I2C_SLAVE_READ_BY_MASTER) {
+#if !SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+            i2c_slave_request_event_data_t evt_data = {};
+            if (i2c_slave->request_callback) {
+                pxHigherPriorityTaskWoken |= i2c_slave->request_callback(i2c_slave, &evt_data, i2c_slave->user_ctx);
+            }
+#endif
+        }
+    }
+
+#if SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+    if (int_mask & I2C_INTR_STRETCH) {  // STRETCH
+        pxHigherPriorityTaskWoken |= i2c_slave_handle_stretch_event(i2c_slave, rx_fifo_exist_len);
+    }
+#endif
+
+    if (int_mask & I2C_INTR_SLV_TXFIFO_WM) {  // TX FiFo Empty
+        pxHigherPriorityTaskWoken |= i2c_slave_handle_tx_fifo(i2c_slave);
+    }
+
+    if (pxHigherPriorityTaskWoken) {
+        portYIELD_FROM_ISR();
+    }
+}
+
+static esp_err_t i2c_slave_device_destroy(i2c_slave_dev_handle_t i2c_slave)
+{
+    i2c_ll_disable_intr_mask(i2c_slave->base->hal.dev, I2C_LL_SLAVE_EVENT_INTR);
+    if (i2c_slave->rx_ring_buf) {
+        vRingbufferDeleteWithCaps(i2c_slave->rx_ring_buf);
+        i2c_slave->rx_ring_buf = NULL;
+    }
+    if (i2c_slave->tx_ring_buf) {
+        vRingbufferDeleteWithCaps(i2c_slave->tx_ring_buf);
+        i2c_slave->tx_ring_buf = NULL;
+    }
+    if (i2c_slave->operation_mux) {
+        vSemaphoreDeleteWithCaps(i2c_slave->operation_mux);
+        i2c_slave->operation_mux = NULL;
+    }
+    if (i2c_slave->receive_desc.buffer) {
+        free(i2c_slave->receive_desc.buffer);
+    }
+    esp_err_t ret = i2c_release_bus_handle(i2c_slave->base);
+
+    free(i2c_slave);
+    return ret;
+}
+
+esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave_dev_handle_t *ret_handle)
+{
+#if CONFIG_I2C_ENABLE_DEBUG_LOG
+    esp_log_level_set(TAG, ESP_LOG_DEBUG);
+#endif
+    esp_err_t ret = ESP_OK;
+    i2c_slave_dev_t *i2c_slave = NULL;
+    ESP_RETURN_ON_FALSE(slave_config && ret_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    ESP_RETURN_ON_FALSE(GPIO_IS_VALID_GPIO(slave_config->sda_io_num) && GPIO_IS_VALID_GPIO(slave_config->scl_io_num), ESP_ERR_INVALID_ARG, TAG, "invalid SDA/SCL pin number");
+#if SOC_LP_I2C_SUPPORTED
+    ESP_RETURN_ON_FALSE(slave_config->i2c_port != (SOC_I2C_NUM - 1), ESP_ERR_NOT_SUPPORTED, TAG, "LP i2c is not supported in I2C slave");
+#endif
+    ESP_RETURN_ON_FALSE(slave_config->i2c_port < SOC_HP_I2C_NUM || slave_config->i2c_port == -1, ESP_ERR_INVALID_ARG, TAG, "invalid i2c port number");
+#if SOC_I2C_SLAVE_SUPPORT_BROADCAST
+    ESP_RETURN_ON_FALSE(((slave_config->addr_bit_len != I2C_ADDR_BIT_LEN_10) || (!slave_config->flags.broadcast_en)), ESP_ERR_INVALID_STATE, TAG, "10bits address cannot used together with broadcast");
+#endif
+
+    i2c_slave = heap_caps_calloc(1, sizeof(i2c_slave_dev_t), I2C_MEM_ALLOC_CAPS);
+    ESP_RETURN_ON_FALSE(i2c_slave, ESP_ERR_NO_MEM, TAG, "no memory for i2c slave bus");
+
+    ESP_GOTO_ON_ERROR(i2c_acquire_bus_handle(slave_config->i2c_port, &i2c_slave->base, I2C_BUS_MODE_SLAVE), err, TAG, "I2C bus acquire failed");
+
+    i2c_hal_context_t *hal = &i2c_slave->base->hal;
+    i2c_slave->base->scl_num = slave_config->scl_io_num;
+    i2c_slave->base->sda_num = slave_config->sda_io_num;
+    i2c_slave->base->pull_up_enable = slave_config->flags.enable_internal_pullup;
+    i2c_slave->rx_data_count = 0;
+    int i2c_port_num = slave_config->i2c_port;
+    ESP_GOTO_ON_ERROR(i2c_common_set_pins(i2c_slave->base), err, TAG, "i2c slave set pins failed");
+
+    i2c_slave->rx_ring_buf = xRingbufferCreateWithCaps(slave_config->receive_buf_depth, RINGBUF_TYPE_BYTEBUF, I2C_MEM_ALLOC_CAPS);
+    ESP_GOTO_ON_FALSE(i2c_slave->rx_ring_buf != NULL, ESP_ERR_INVALID_STATE, err, TAG, "ringbuffer create failed");
+
+    i2c_slave->operation_mux = xSemaphoreCreateBinaryWithCaps(I2C_MEM_ALLOC_CAPS);
+    ESP_GOTO_ON_FALSE(i2c_slave->operation_mux, ESP_ERR_NO_MEM, err, TAG, "No memory for binary semaphore");
+    xSemaphoreGive(i2c_slave->operation_mux);
+
+    uint8_t *rcv_buffer = heap_caps_calloc(1, slave_config->receive_buf_depth, I2C_MEM_ALLOC_CAPS);
+    ESP_RETURN_ON_FALSE(rcv_buffer, ESP_ERR_NO_MEM, TAG, "no memory for i2c slave receive internal buffer");
+
+    i2c_slave->receive_desc.buffer = rcv_buffer;
+    i2c_slave->receive_desc.rcv_fifo_cnt = slave_config->receive_buf_depth;
+
+    i2c_slave->tx_ring_buf = xRingbufferCreateWithCaps(slave_config->send_buf_depth, RINGBUF_TYPE_BYTEBUF, I2C_MEM_ALLOC_CAPS);
+    ESP_RETURN_ON_FALSE(i2c_slave->tx_ring_buf, ESP_ERR_NO_MEM, TAG, "no memory for i2c slave transmit ringbuffer");
+
+#if I2C_USE_RETENTION_LINK
+    if (slave_config->flags.allow_pd != 0) {
+        i2c_create_retention_module(i2c_slave->base);
+    }
+#endif // I2C_USE_RETENTION_LINK
+
+    int isr_flags = I2C_INTR_ALLOC_FLAG;
+    if (slave_config->intr_priority) {
+        isr_flags |= 1 << (slave_config->intr_priority);
+    }
+    ret = esp_intr_alloc_intrstatus(i2c_periph_signal[i2c_port_num].irq, isr_flags, (uint32_t)i2c_ll_get_interrupt_status_reg(hal->dev), I2C_LL_SLAVE_EVENT_INTR, i2c_slave_isr_handler, i2c_slave, &i2c_slave->base->intr_handle);
+    ESP_GOTO_ON_ERROR(ret, err, TAG, "install i2c slave interrupt failed");
+
+    portENTER_CRITICAL(&i2c_slave->base->spinlock);
+    i2c_hal_slave_init(hal);
+    i2c_ll_slave_set_fifo_mode(hal->dev, true);
+    i2c_ll_set_slave_addr(hal->dev, slave_config->slave_addr, false);
+    i2c_ll_set_tout(hal->dev, I2C_LL_MAX_TIMEOUT);
+
+    I2C_CLOCK_SRC_ATOMIC() {
+        i2c_ll_set_source_clk(hal->dev, slave_config->clk_source);
+    }
+    bool addr_10bit_en = slave_config->addr_bit_len != I2C_ADDR_BIT_LEN_7;
+    i2c_ll_set_slave_addr(hal->dev, slave_config->slave_addr, addr_10bit_en);
+
+#if SOC_I2C_SLAVE_SUPPORT_BROADCAST
+    i2c_ll_slave_broadcast_enable(hal->dev, slave_config->flags.broadcast_en);
+#endif
+
+    i2c_ll_set_txfifo_empty_thr(hal->dev, SOC_I2C_FIFO_LEN / 2);
+    i2c_ll_set_rxfifo_full_thr(hal->dev, SOC_I2C_FIFO_LEN / 2);
+    i2c_ll_set_sda_timing(hal->dev, 10, 10);
+
+    i2c_ll_disable_intr_mask(hal->dev, I2C_LL_INTR_MASK);
+    i2c_ll_clear_intr_mask(hal->dev, I2C_LL_INTR_MASK);
+
+    i2c_ll_enable_intr_mask(hal->dev, I2C_LL_SLAVE_RX_EVENT_INTR);
+
+    // Configure stretch
+    i2c_ll_slave_set_stretch_protect_num(hal->dev, I2C_LL_STRETCH_PROTECT_TIME);
+    i2c_ll_slave_enable_scl_stretch(hal->dev, true);
+    i2c_ll_slave_clear_stretch(hal->dev);
+
+    i2c_ll_update(hal->dev);
+    portEXIT_CRITICAL(&i2c_slave->base->spinlock);
+
+    *ret_handle = i2c_slave;
+    return ret;
+
+err:
+    if (i2c_slave) {
+        i2c_slave_device_destroy(i2c_slave);
+    }
+    return ret;
+}
+
+esp_err_t i2c_del_slave_device(i2c_slave_dev_handle_t i2c_slave)
+{
+    ESP_RETURN_ON_FALSE(i2c_slave, ESP_ERR_INVALID_ARG, TAG, "i2c slave not initialized");
+    int port_id = i2c_slave->base->port_num;
+    ESP_LOGD(TAG, "del i2c bus(%d)", port_id);
+    ESP_RETURN_ON_ERROR(i2c_slave_device_destroy(i2c_slave), TAG, "destroy i2c bus failed");
+    return ESP_OK;
+}
+
+esp_err_t i2c_slave_write(i2c_slave_dev_handle_t i2c_slave, const uint8_t *data, uint32_t len, uint32_t *write_len, int timeout_ms)
+{
+    ESP_RETURN_ON_FALSE(i2c_slave, ESP_ERR_INVALID_ARG, TAG, "i2c slave not initialized");
+    ESP_RETURN_ON_FALSE(data, ESP_ERR_INVALID_ARG, TAG, "invalid data buffer");
+    ESP_RETURN_ON_FALSE(write_len, ESP_ERR_INVALID_ARG, TAG, "invalid write length pointer");
+    uint32_t free_fifo_len = 0;
+    uint32_t write_ringbuffer_len = 0;
+    uint32_t actual_write_fifo_size = 0;
+    uint8_t *existing_data = NULL;
+    size_t existing_size = 0;
+    i2c_hal_context_t *hal = &i2c_slave->base->hal;
+    TickType_t wait_ticks = (timeout_ms == -1) ? portMAX_DELAY : pdMS_TO_TICKS(timeout_ms);
+
+    xSemaphoreTake(i2c_slave->operation_mux, wait_ticks);
+
+    portENTER_CRITICAL(&i2c_slave->base->spinlock);
+#if !SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+    i2c_ll_slave_disable_tx_it(hal->dev);
+    uint32_t txfifo_len = 0;
+    i2c_ll_get_txfifo_len(hal->dev, &txfifo_len);
+    if (txfifo_len < SOC_I2C_FIFO_LEN) {
+        // For the target (esp32) cannot stretch, reset the fifo when there is any dirty data in fifo.
+        i2c_ll_txfifo_rst(hal->dev);
+    }
+#endif
+    i2c_ll_get_txfifo_len(hal->dev, &free_fifo_len);
+    portEXIT_CRITICAL(&i2c_slave->base->spinlock);
+
+    // Check if there is any data in the ringbuffer in last transaction
+    existing_data = xRingbufferReceiveUpTo(i2c_slave->tx_ring_buf, &existing_size, 0, free_fifo_len);
+    if (existing_data) {
+        // has data, fill to the fifo
+        i2c_ll_write_txfifo(hal->dev, existing_data, existing_size);
+        free_fifo_len -= existing_size;
+        vRingbufferReturnItem(i2c_slave->tx_ring_buf, existing_data);
+    }
+
+    // Write data.
+    if (free_fifo_len) {
+        portENTER_CRITICAL(&i2c_slave->base->spinlock);
+        if (len < free_fifo_len) {
+            actual_write_fifo_size = len;
+        }
+        i2c_ll_write_txfifo(hal->dev, (uint8_t *)data, actual_write_fifo_size);
+        data += actual_write_fifo_size;
+        len -= actual_write_fifo_size;
+        portEXIT_CRITICAL(&i2c_slave->base->spinlock);
+        //write the rest of the bytes to the ringbuffer
+    }
+
+    if (len) {
+        write_ringbuffer_len = xRingbufferGetCurFreeSize(i2c_slave->tx_ring_buf);
+        if (len < write_ringbuffer_len) {
+            write_ringbuffer_len = len;
+        }
+
+        if (xRingbufferSend(i2c_slave->tx_ring_buf, data, write_ringbuffer_len, wait_ticks) != pdTRUE) {
+            write_ringbuffer_len = 0;
+        }
+    }
+
+    *write_len = write_ringbuffer_len + actual_write_fifo_size;
+    i2c_ll_slave_enable_tx_it(hal->dev);
+    i2c_ll_slave_clear_stretch(hal->dev);
+
+    xSemaphoreGive(i2c_slave->operation_mux);
+
+    return ESP_OK;
+}
+
+esp_err_t i2c_slave_register_event_callbacks(i2c_slave_dev_handle_t i2c_slave, const i2c_slave_event_callbacks_t *cbs, void *user_data)
+{
+    ESP_RETURN_ON_FALSE(i2c_slave != NULL, ESP_ERR_INVALID_ARG, TAG, "i2c slave handle not initialized");
+    ESP_RETURN_ON_FALSE(cbs, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+#if CONFIG_I2C_ISR_IRAM_SAFE
+    if (cbs->on_request) {
+        ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_request), ESP_ERR_INVALID_ARG, TAG, "i2c request occur callback not in IRAM");
+    }
+    if (cbs->on_receive) {
+        ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_receive), ESP_ERR_INVALID_ARG, TAG, "i2c receive occur callback not in IRAM");
+    }
+    if (user_data) {
+        ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM");
+    }
+#endif
+
+    i2c_slave->user_ctx = user_data;
+    i2c_slave->request_callback = cbs->on_request;
+    i2c_slave->receive_callback = cbs->on_receive;
+    return ESP_OK;
+}
diff --git a/components/esp_driver_i2c/include/driver/i2c_master.h b/components/esp_driver_i2c/include/driver/i2c_master.h
index a7b1a0d4c72..8518a45d0cd 100644
--- a/components/esp_driver_i2c/include/driver/i2c_master.h
+++ b/components/esp_driver_i2c/include/driver/i2c_master.h
@@ -33,6 +33,9 @@ typedef struct {
     size_t trans_queue_depth;             /*!< Depth of internal transfer queue, increase this value can support more transfers pending in the background, only valid in asynchronous transaction. (Typically max_device_num * per_transaction)*/
     struct {
         uint32_t enable_internal_pullup: 1;  /*!< Enable internal pullups. Note: This is not strong enough to pullup buses under high-speed frequency. Recommend proper external pull-up if possible */
+        uint32_t allow_pd:               1;  /*!< If set, the driver will backup/restore the I2C registers before/after entering/exist sleep mode.
+                                              By this approach, the system can power off I2C's power domain.
+                                              This can save power, but at the expense of more RAM being consumed */
     } flags;                              /*!< I2C master config flags */
 } i2c_master_bus_config_t;
 
@@ -257,6 +260,22 @@ esp_err_t i2c_master_bus_reset(i2c_master_bus_handle_t bus_handle);
  */
 esp_err_t i2c_master_bus_wait_all_done(i2c_master_bus_handle_t bus_handle, int timeout_ms);
 
+/**
+ * @brief Retrieves the I2C master bus handle for a specified I2C port number.
+ *
+ * This function retrieves the I2C master bus handle for the
+ * given I2C port number. Please make sure the handle has already been initialized, and this
+ * function would simply returns the existing handle. Note that the returned handle still can't be used concurrently
+ *
+ * @param port_num I2C port number for which the handle is to be retrieved.
+ * @param ret_handle Pointer to a variable where the retrieved handle will be stored.
+ * @return
+ *     - ESP_OK: Success. The handle is retrieved successfully.
+ *     - ESP_ERR_INVALID_ARG: Invalid argument, such as invalid port number
+ *     - ESP_ERR_INVALID_STATE: Invalid state, such as the I2C port is not initialized.
+ */
+esp_err_t i2c_master_get_bus_handle(i2c_port_num_t port_num, i2c_master_bus_handle_t *ret_handle);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_i2c/include/driver/i2c_slave.h b/components/esp_driver_i2c/include/driver/i2c_slave.h
index 897b9899ed0..17d26dabd1b 100644
--- a/components/esp_driver_i2c/include/driver/i2c_slave.h
+++ b/components/esp_driver_i2c/include/driver/i2c_slave.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,11 +10,14 @@
 #include "driver/i2c_types.h"
 #include "hal/gpio_types.h"
 #include "soc/soc_caps.h"
+#include "sdkconfig.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#if !CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2
+
 /**
  * @brief I2C slave specific configurations
  */
@@ -40,6 +43,9 @@ typedef struct {
 #if SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
         uint32_t slave_unmatch_en: 1;        /*!< Can trigger unmatch interrupt when slave address does not match what master sends*/
 #endif
+        uint32_t allow_pd:    1;  /*!< If set, the driver will backup/restore the I2C registers before/after entering/exist sleep mode.
+                                              By this approach, the system can power off I2C's power domain.
+                                              This can save power, but at the expense of more RAM being consumed */
     } flags;                                 /*!< I2C slave config flags */
 } i2c_slave_config_t;
 
@@ -56,28 +62,6 @@ typedef struct {
     i2c_slave_received_callback_t on_recv_done;   /*!< I2C slave receive done callback */
 } i2c_slave_event_callbacks_t;
 
-/**
- * @brief Initialize an I2C slave device
- *
- * @param[in] slave_config I2C slave device configurations
- * @param[out] ret_handle Return a generic I2C device handle
- * @return
- *      - ESP_OK: I2C slave device initialized successfully
- *      - ESP_ERR_INVALID_ARG: I2C device initialization failed because of invalid argument.
- *      - ESP_ERR_NO_MEM: Create I2C device failed because of out of memory.
- */
-esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave_dev_handle_t *ret_handle);
-
-/**
- * @brief Deinitialize the I2C slave device
- *
- * @param[in] i2c_slave I2C slave device handle that created by `i2c_new_slave_device`.
- * @return
- *      - ESP_OK: Delete I2C device successfully.
- *      - ESP_ERR_INVALID_ARG: I2C device initialization failed because of invalid argument.
- */
-esp_err_t i2c_del_slave_device(i2c_slave_dev_handle_t i2c_slave);
-
 /**
  * @brief Read bytes from I2C internal buffer. Start a job to receive I2C data.
  *
@@ -113,23 +97,6 @@ esp_err_t i2c_slave_receive(i2c_slave_dev_handle_t i2c_slave, uint8_t *data, siz
  */
 esp_err_t i2c_slave_transmit(i2c_slave_dev_handle_t i2c_slave, const uint8_t *data, int size, int xfer_timeout_ms);
 
-/**
- * @brief Set I2C slave event callbacks for I2C slave channel.
- *
- * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL.
- * @note When CONFIG_I2C_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
- *       The variables used in the function should be in the SRAM as well. The `user_data` should also reside in SRAM.
- *
- * @param[in] i2c_slave I2C slave device handle that created by `i2c_new_slave_device`.
- * @param[in] cbs Group of callback functions
- * @param[in] user_data User data, which will be passed to callback functions directly
- * @return
- *      - ESP_OK: Set I2C transaction callbacks successfully
- *      - ESP_ERR_INVALID_ARG: Set I2C transaction callbacks failed because of invalid argument
- *      - ESP_FAIL: Set I2C transaction callbacks failed because of other error
- */
-esp_err_t i2c_slave_register_event_callbacks(i2c_slave_dev_handle_t i2c_slave, const i2c_slave_event_callbacks_t *cbs, void *user_data);
-
 #if SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
 /**
  * @brief Read bytes from I2C internal ram. This can be only used when `access_ram_en` in configuration structure set to true.
@@ -161,6 +128,103 @@ esp_err_t i2c_slave_read_ram(i2c_slave_dev_handle_t i2c_slave, uint8_t ram_addre
 esp_err_t i2c_slave_write_ram(i2c_slave_dev_handle_t i2c_slave, uint8_t ram_address, const uint8_t *data, size_t size);
 
 #endif
+
+#else // CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+////////////////////////////////// I2C SLAVE VERSION TWO /////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief I2C slave specific configurations
+ */
+typedef struct {
+    i2c_port_num_t i2c_port;                 /*!< I2C port number, `-1` for auto selecting */
+    gpio_num_t sda_io_num;                   /*!< SDA IO number used by I2C bus */
+    gpio_num_t scl_io_num;                   /*!< SCL IO number used by I2C bus */
+    i2c_clock_source_t clk_source;           /*!< Clock source of I2C bus. */
+    uint32_t send_buf_depth;                 /*!< Depth of internal transfer ringbuffer */
+    uint32_t receive_buf_depth;              /*!< Depth of receive internal software buffer */
+    uint16_t slave_addr;                     /*!< I2C slave address */
+    i2c_addr_bit_len_t addr_bit_len;         /*!< I2C slave address in bit length */
+    int intr_priority;                       /*!< I2C interrupt priority, if set to 0, driver will select the default priority (1,2,3). */
+    struct {
+        uint32_t allow_pd:    1;  /*!< If set, the driver will backup/restore the I2C registers before/after entering/exist sleep mode.
+                                              By this approach, the system can power off I2C's power domain.
+                                              This can save power, but at the expense of more RAM being consumed */
+        uint32_t enable_internal_pullup: 1;  /*!< Enable internal pullups. Note: This is not strong enough to pullup buses under high-speed frequency. Recommend proper external pull-up if possible */
+#if SOC_I2C_SLAVE_SUPPORT_BROADCAST
+        uint32_t broadcast_en: 1;            /*!< I2C slave enable broadcast, able to respond to broadcast address */
+#endif
+    } flags;                                 /*!< I2C slave config flags */
+} i2c_slave_config_t;
+
+/**
+ * @brief Group of I2C slave callbacks. Take care of potential concurrency issues.
+ * @note The callbacks are all running under ISR context
+ * @note When CONFIG_I2C_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
+ *       The variables used in the function should be in the SRAM as well.
+ */
+typedef struct {
+    i2c_slave_request_callback_t on_request;         /*!< Callback for when a master requests data from the slave */
+    i2c_slave_received_callback_t on_receive;         /*!< Callback for when the slave receives data from the master */
+} i2c_slave_event_callbacks_t;
+
+/**
+ * @brief Write buffer to hardware fifo. If write length is larger than hardware fifo, then restore in software buffer.
+ *
+ * @param[in] i2c_slave I2C slave device handle that created by `i2c_new_slave_device`.
+ * @param[in] data Buffer to write to slave fifo, can pickup by master.
+ * @param[in] len In bytes, of `data` buffer.
+ * @param[out] write_len In bytes, actually write length.
+ * @param[in] timeout_ms Wait timeout, in ms. Note: -1 means wait forever.
+ * @return
+ *      - ESP_OK: I2C slave write success.
+ *      - ESP_ERR_INVALID_ARG: I2C slave write parameter invalid.
+ *      - ESP_ERR_TIMEOUT: Operation timeout(larger than xfer_timeout_ms) because the device is busy or hardware crash.
+ */
+esp_err_t i2c_slave_write(i2c_slave_dev_handle_t i2c_slave, const uint8_t *data, uint32_t len, uint32_t *write_len, int timeout_ms);
+
+#endif // CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2
+
+/**
+ * @brief Initialize an I2C slave device
+ *
+ * @param[in] slave_config I2C slave device configurations
+ * @param[out] ret_handle Return a generic I2C device handle
+ * @return
+ *      - ESP_OK: I2C slave device initialized successfully
+ *      - ESP_ERR_INVALID_ARG: I2C device initialization failed because of invalid argument.
+ *      - ESP_ERR_NO_MEM: Create I2C device failed because of out of memory.
+ */
+esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave_dev_handle_t *ret_handle);
+
+/**
+ * @brief Set I2C slave event callbacks for I2C slave channel.
+ *
+ * @note User can deregister a previously registered callback by calling this function and setting the callback member in the `cbs` structure to NULL.
+ * @note When CONFIG_I2C_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
+ *       The variables used in the function should be in the SRAM as well. The `user_data` should also reside in SRAM.
+ *
+ * @param[in] i2c_slave I2C slave device handle that created by `i2c_new_slave_device`.
+ * @param[in] cbs Group of callback functions
+ * @param[in] user_data User data, which will be passed to callback functions directly
+ * @return
+ *      - ESP_OK: Set I2C transaction callbacks successfully
+ *      - ESP_ERR_INVALID_ARG: Set I2C transaction callbacks failed because of invalid argument
+ *      - ESP_FAIL: Set I2C transaction callbacks failed because of other error
+ */
+esp_err_t i2c_slave_register_event_callbacks(i2c_slave_dev_handle_t i2c_slave, const i2c_slave_event_callbacks_t *cbs, void *user_data);
+
+/**
+ * @brief Deinitialize the I2C slave device
+ *
+ * @param[in] i2c_slave I2C slave device handle that created by `i2c_new_slave_device`.
+ * @return
+ *      - ESP_OK: Delete I2C device successfully.
+ *      - ESP_ERR_INVALID_ARG: I2C device initialization failed because of invalid argument.
+ */
+esp_err_t i2c_del_slave_device(i2c_slave_dev_handle_t i2c_slave);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_i2c/include/driver/i2c_types.h b/components/esp_driver_i2c/include/driver/i2c_types.h
index 1dffb25ceab..aa80a840afd 100644
--- a/components/esp_driver_i2c/include/driver/i2c_types.h
+++ b/components/esp_driver_i2c/include/driver/i2c_types.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,6 +10,7 @@
 #include <stdbool.h>
 #include "hal/i2c_types.h"
 #include "soc/soc_caps.h"
+#include "sdkconfig.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -82,6 +83,9 @@ typedef bool (*i2c_master_callback_t)(i2c_master_dev_handle_t i2c_dev, const i2c
  */
 typedef struct {
     uint8_t *buffer;  /**< Pointer for buffer received in callback. */
+#if CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2
+    uint32_t length;      /**< Length for buffer received in callback. */
+#endif
 } i2c_slave_rx_done_event_data_t;
 
 /**
@@ -117,6 +121,25 @@ typedef bool (*i2c_slave_stretch_callback_t)(i2c_slave_dev_handle_t i2c_slave, c
 
 #endif
 
+/**
+ * @brief Event structure used in I2C slave request.
+ */
+typedef struct {
+
+} i2c_slave_request_event_data_t;
+
+/**
+ * @brief Callback signature for I2C slave request event. When this callback is triggered that means master want to read data
+ * from slave while there is no data in slave fifo. So user should write data to fifo via `i2c_slave_write`
+ *
+ * @param[in]  i2c_slave Handle for I2C slave.
+ * @param[out] evt_data I2C receive event data, fed by driver
+ * @param[in]  arg User data, set in `i2c_slave_register_event_callbacks()`
+ *
+ * @return Whether a high priority task has been waken up by this function
+ */
+typedef bool (*i2c_slave_request_callback_t)(i2c_slave_dev_handle_t i2c_slave, const i2c_slave_request_event_data_t *evt_data, void *arg);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_i2c/include/esp_private/i2c_platform.h b/components/esp_driver_i2c/include/esp_private/i2c_platform.h
index f18cf53c99c..3b8bee7b252 100644
--- a/components/esp_driver_i2c/include/esp_private/i2c_platform.h
+++ b/components/esp_driver_i2c/include/esp_private/i2c_platform.h
@@ -15,21 +15,7 @@
 extern "C" {
 #endif
 
-/**
- * @brief Retrieves the I2C master bus handle for a specified I2C port number.
- *
- * This function retrieves the I2C master bus handle for the
- * given I2C port number. Please make sure the handle has already been initialized, and this
- * function would simply returns the existing handle. Note that the returned handle still can't be used concurrently
- *
- * @param port_num I2C port number for which the handle is to be retrieved.
- * @param ret_handle Pointer to a variable where the retrieved handle will be stored.
- * @return
- *     - ESP_OK: Success. The handle is retrieved successfully.
- *     - ESP_ERR_INVALID_ARG: Invalid argument, such as invalid port number
- *     - ESP_ERR_INVALID_STATE: Invalid state, such as the I2C port is not initialized.
- */
-esp_err_t i2c_master_get_bus_handle(i2c_port_num_t port_num, i2c_master_bus_handle_t *ret_handle);
+// Empty file in order not cause breaking change. Should be removed in next version.
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_driver_i2c/test_apps/.build-test-rules.yml b/components/esp_driver_i2c/test_apps/.build-test-rules.yml
index b363f05a991..5436c0467ea 100644
--- a/components/esp_driver_i2c/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_i2c/test_apps/.build-test-rules.yml
@@ -5,8 +5,3 @@ components/esp_driver_i2c/test_apps/i2c_test_apps:
     - if: SOC_I2C_SUPPORTED != 1
   depends_components:
     - esp_driver_i2c
-    # Following dependency is needed because they might increase lazy installed memory
-    # that can cause sleep retention memory leak check failed.
-    - components/ieee802154/**
-    - components/esp_coex/**
-    - components/esp_phy/**
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt
index 2f653da9aeb..7187dd3907f 100644
--- a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt
+++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/CMakeLists.txt
@@ -3,35 +3,37 @@ set(srcs "test_app_main.c"
     )
 
 if(CONFIG_SOC_I2C_SUPPORT_SLAVE)
-    list(APPEND srcs "test_i2c_multi.c")
-    if(CONFIG_I2C_ISR_IRAM_SAFE)
-        list(APPEND srcs "test_i2c_iram.c")
-    endif()
-endif()
+    if(CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2)
+        list(APPEND srcs "test_i2c_slave_v2.c")
+    else()
+        list(APPEND srcs "test_i2c_multi.c")
 
-if(CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST)
-    list(APPEND srcs "test_i2c_broadcast.c")
-endif()
+        if(CONFIG_SOC_I2C_SLAVE_SUPPORT_BROADCAST)
+            list(APPEND srcs "test_i2c_broadcast.c")
+        endif()
 
-if(CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS)
-    list(APPEND srcs "test_i2c_ram.c")
-endif()
+        if(CONFIG_SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS)
+            list(APPEND srcs "test_i2c_ram.c")
+        endif()
 
-if(CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR AND CONFIG_SOC_I2C_SUPPORT_SLAVE)
-    list(APPEND srcs "test_i2c_10bit.c")
-endif()
+        if(CONFIG_SOC_I2C_SUPPORT_10BIT_ADDR AND CONFIG_SOC_I2C_SUPPORT_SLAVE)
+            list(APPEND srcs "test_i2c_10bit.c")
+        endif()
 
-if(CONFIG_SOC_LP_I2C_SUPPORTED)
-    list(APPEND srcs "test_lp_i2c.c")
-endif()
+        if(CONFIG_SOC_LP_I2C_SUPPORTED)
+            list(APPEND srcs "test_lp_i2c.c")
+        endif()
 
-# Only build this file with `CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP` and `CONFIG_IEEE802154_ENABLED` enabled
-# Enable `CONFIG_IEEE802154_ENABLED` is for modem domain really power down.
-# This reliable can be removed if the sleep retention got finished.
-if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP AND CONFIG_IEEE802154_ENABLED)
-    list(APPEND srcs "test_i2c_sleep_retention.c")
+        if(CONFIG_SOC_I2C_SUPPORT_SLEEP_RETENTION)
+            list(APPEND srcs "test_i2c_sleep_retention.c")
+        endif()
+
+        if(CONFIG_I2C_ISR_IRAM_SAFE)
+            list(APPEND srcs "test_i2c_iram.c")
+        endif()
+    endif()
 endif()
 
 idf_component_register(SRCS ${srcs}
-                       PRIV_REQUIRES unity driver test_utils ieee802154
+                       PRIV_REQUIRES unity driver test_utils
                        WHOLE_ARCHIVE)
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_common.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_common.c
index 91296a6eedd..55d7064b86f 100644
--- a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_common.c
+++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_common.c
@@ -19,7 +19,6 @@
 #include "esp_private/periph_ctrl.h"
 #include "driver/gpio.h"
 #include "driver/i2c_master.h"
-#include "esp_private/i2c_platform.h"
 #include "esp_rom_gpio.h"
 #include "esp_log.h"
 #include "test_utils.h"
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_slave_v2.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_slave_v2.c
new file mode 100644
index 00000000000..e1282824d0c
--- /dev/null
+++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_slave_v2.c
@@ -0,0 +1,238 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include <stdio.h>
+#include <string.h>
+#include "sdkconfig.h"
+#include "unity.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/queue.h"
+#include "esp_err.h"
+#include "driver/i2c_master.h"
+#include "driver/i2c_slave.h"
+#include "esp_rom_gpio.h"
+#include "esp_log.h"
+#include "test_utils.h"
+#include "test_board.h"
+
+#if SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+
+static QueueHandle_t event_queue;
+static uint8_t *temp_data;
+static size_t temp_len = 0;
+
+typedef enum {
+    I2C_SLAVE_EVT_RX,
+    I2C_SLAVE_EVT_TX
+} i2c_slave_event_t;
+
+void disp_buf(uint8_t *buf, int len)
+{
+    int i;
+    for (i = 0; i < len; i++) {
+        printf("%02x ", buf[i]);
+        if ((i + 1) % 16 == 0) {
+            printf("\n");
+        }
+    }
+    printf("\n");
+}
+
+static bool i2c_slave_request_cb(i2c_slave_dev_handle_t i2c_slave, const i2c_slave_request_event_data_t *evt_data, void *arg)
+{
+    BaseType_t xTaskWoken;
+    i2c_slave_event_t evt = I2C_SLAVE_EVT_TX;
+    xQueueSendFromISR(event_queue, &evt, &xTaskWoken);
+    return xTaskWoken;
+}
+
+static bool i2c_slave_receive_cb(i2c_slave_dev_handle_t i2c_slave, const i2c_slave_rx_done_event_data_t *evt_data, void *arg)
+{
+    BaseType_t xTaskWoken;
+    i2c_slave_event_t evt = I2C_SLAVE_EVT_RX;
+    memcpy(temp_data, evt_data->buffer, evt_data->length);
+    temp_len = evt_data->length;
+    xQueueSendFromISR(event_queue, &evt, &xTaskWoken);
+    return xTaskWoken;
+}
+
+static void i2c_slave_read_test_v2(void)
+{
+    i2c_slave_dev_handle_t handle;
+    event_queue = xQueueCreate(2, sizeof(i2c_slave_event_t));
+    assert(event_queue);
+    temp_data = malloc(DATA_LENGTH);
+    assert(temp_data);
+
+    i2c_slave_config_t i2c_slv_config = {
+        .i2c_port = TEST_I2C_PORT,
+        .clk_source = I2C_CLK_SRC_DEFAULT,
+        .scl_io_num = I2C_SLAVE_SCL_IO,
+        .sda_io_num = I2C_SLAVE_SDA_IO,
+        .slave_addr = ESP_SLAVE_ADDR,
+        .send_buf_depth = DATA_LENGTH,
+        .receive_buf_depth = DATA_LENGTH,
+    };
+
+    TEST_ESP_OK(i2c_new_slave_device(&i2c_slv_config, &handle));
+
+    i2c_slave_event_callbacks_t cbs = {
+        .on_receive = i2c_slave_receive_cb,
+        .on_request = i2c_slave_request_cb,
+    };
+
+    TEST_ESP_OK(i2c_slave_register_event_callbacks(handle, &cbs, NULL));
+
+    unity_send_signal("i2c slave init finish");
+
+    unity_wait_for_signal("master write");
+
+    i2c_slave_event_t evt;
+    if (xQueueReceive(event_queue, &evt, 1) == pdTRUE) {
+        if (evt == I2C_SLAVE_EVT_RX) {
+            disp_buf(temp_data, temp_len);
+            printf("length is %x\n", temp_len);
+            for (int i = 0; i < temp_len; i++) {
+                TEST_ASSERT(temp_data[i] == i);
+            }
+        }
+    }
+
+    unity_send_signal("ready to delete");
+    free(temp_data);
+    vQueueDelete(event_queue);
+    TEST_ESP_OK(i2c_del_slave_device(handle));
+}
+
+static void i2c_master_write_test_v2(void)
+{
+    uint8_t data_wr[DATA_LENGTH] = { 0 };
+    int i;
+
+    i2c_master_bus_config_t i2c_mst_config = {
+        .clk_source = I2C_CLK_SRC_DEFAULT,
+        .i2c_port = TEST_I2C_PORT,
+        .scl_io_num = I2C_MASTER_SCL_IO,
+        .sda_io_num = I2C_MASTER_SDA_IO,
+        .flags.enable_internal_pullup = true,
+    };
+    i2c_master_bus_handle_t bus_handle;
+
+    TEST_ESP_OK(i2c_new_master_bus(&i2c_mst_config, &bus_handle));
+
+    i2c_device_config_t dev_cfg = {
+        .dev_addr_length = I2C_ADDR_BIT_LEN_7,
+        .device_address = ESP_SLAVE_ADDR,
+        .scl_speed_hz = 100000,
+    };
+
+    i2c_master_dev_handle_t dev_handle;
+    TEST_ESP_OK(i2c_master_bus_add_device(bus_handle, &dev_cfg, &dev_handle));
+
+    unity_wait_for_signal("i2c slave init finish");
+
+    unity_send_signal("master write");
+    for (i = 0; i < DATA_LENGTH; i++) {
+        data_wr[i] = i;
+    }
+
+    disp_buf(data_wr, i);
+    TEST_ESP_OK(i2c_master_transmit(dev_handle, data_wr, DATA_LENGTH, -1));
+    unity_wait_for_signal("ready to delete");
+    TEST_ESP_OK(i2c_master_bus_rm_device(dev_handle));
+
+    TEST_ESP_OK(i2c_del_master_bus(bus_handle));
+}
+
+TEST_CASE_MULTIPLE_DEVICES("I2C master write slave v2 test", "[i2c][test_env=generic_multi_device][timeout=150]", i2c_master_write_test_v2, i2c_slave_read_test_v2);
+
+static void master_read_slave_test_v2(void)
+{
+    uint8_t data_rd[DATA_LENGTH] = {0};
+    i2c_master_bus_config_t i2c_mst_config = {
+        .clk_source = I2C_CLK_SRC_DEFAULT,
+        .i2c_port = TEST_I2C_PORT,
+        .scl_io_num = I2C_MASTER_SCL_IO,
+        .sda_io_num = I2C_MASTER_SDA_IO,
+        .flags.enable_internal_pullup = true,
+    };
+    i2c_master_bus_handle_t bus_handle;
+    TEST_ESP_OK(i2c_new_master_bus(&i2c_mst_config, &bus_handle));
+
+    i2c_device_config_t dev_cfg = {
+        .dev_addr_length = I2C_ADDR_BIT_LEN_7,
+        .device_address = ESP_SLAVE_ADDR,
+        .scl_speed_hz = 100000,
+        .scl_wait_us = 20000,
+    };
+
+    i2c_master_dev_handle_t dev_handle;
+    TEST_ESP_OK(i2c_master_bus_add_device(bus_handle, &dev_cfg, &dev_handle));
+
+    unity_wait_for_signal("i2c slave init finish");
+
+    TEST_ESP_OK(i2c_master_receive(dev_handle, data_rd, DATA_LENGTH, -1));
+    vTaskDelay(100 / portTICK_PERIOD_MS);
+    for (int i = 0; i < DATA_LENGTH; i++) {
+        printf("%x\n", data_rd[i]);
+        TEST_ASSERT(data_rd[i] == i);
+    }
+    unity_send_signal("ready to delete master read test");
+
+    TEST_ESP_OK(i2c_master_bus_rm_device(dev_handle));
+    TEST_ESP_OK(i2c_del_master_bus(bus_handle));
+}
+
+static void slave_write_buffer_test_v2(void)
+{
+    i2c_slave_dev_handle_t handle;
+    uint8_t data_wr[DATA_LENGTH];
+    event_queue = xQueueCreate(2, sizeof(i2c_slave_event_t));
+    assert(event_queue);
+
+    i2c_slave_config_t i2c_slv_config = {
+        .i2c_port = TEST_I2C_PORT,
+        .clk_source = I2C_CLK_SRC_DEFAULT,
+        .scl_io_num = I2C_SLAVE_SCL_IO,
+        .sda_io_num = I2C_SLAVE_SDA_IO,
+        .slave_addr = ESP_SLAVE_ADDR,
+        .send_buf_depth = DATA_LENGTH,
+        .receive_buf_depth = DATA_LENGTH,
+    };
+
+    TEST_ESP_OK(i2c_new_slave_device(&i2c_slv_config, &handle));
+
+    i2c_slave_event_callbacks_t cbs = {
+        .on_receive = i2c_slave_receive_cb,
+        .on_request = i2c_slave_request_cb,
+    };
+
+    TEST_ESP_OK(i2c_slave_register_event_callbacks(handle, &cbs, NULL));
+
+    unity_send_signal("i2c slave init finish");
+
+    for (int i = 0; i < DATA_LENGTH; i++) {
+        data_wr[i] = i;
+    }
+
+    i2c_slave_event_t evt;
+    uint32_t write_len;
+    while (true) {
+        if (xQueueReceive(event_queue, &evt, portMAX_DELAY) == pdTRUE) {
+            if (evt == I2C_SLAVE_EVT_TX) {
+                TEST_ESP_OK(i2c_slave_write(handle, data_wr, DATA_LENGTH, &write_len, 1000));
+                break;
+            }
+        }
+    }
+
+    unity_wait_for_signal("ready to delete master read test");
+    vQueueDelete(event_queue);
+    TEST_ESP_OK(i2c_del_slave_device(handle));
+}
+
+TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=generic_multi_device][timeout=150]", master_read_slave_test_v2, slave_write_buffer_test_v2);
+
+#endif // SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.c b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.c
index 8f1ca39d8e8..845791cfed7 100644
--- a/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.c
+++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.c
@@ -43,6 +43,7 @@ static void i2c_master_write_sleep_retention_test(void)
         .scl_io_num = I2C_MASTER_SCL_IO,
         .sda_io_num = I2C_MASTER_SDA_IO,
         .flags.enable_internal_pullup = true,
+        .flags.allow_pd = true,
     };
     i2c_master_bus_handle_t bus_handle;
 
@@ -68,7 +69,9 @@ static void i2c_master_write_sleep_retention_test(void)
     TEST_ESP_OK(i2c_master_transmit(dev_handle, data_wr, DATA_LENGTH, -1));
     unity_wait_for_signal("i2c slave receive once, master to sleep");
 
+#if ESP_SLEEP_POWER_DOWN_CPU
     TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
     TEST_ESP_OK(esp_sleep_enable_timer_wakeup(3 * 1000 * 1000));
     TEST_ESP_OK(esp_light_sleep_start());
 
@@ -84,7 +87,9 @@ static void i2c_master_write_sleep_retention_test(void)
     unity_send_signal("master write again");
 
     unity_wait_for_signal("ready to delete");
+#if ESP_SLEEP_POWER_DOWN_CPU
     TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
     TEST_ESP_OK(i2c_master_bus_rm_device(dev_handle));
 
     TEST_ESP_OK(i2c_del_master_bus(bus_handle));
@@ -103,6 +108,7 @@ static void i2c_slave_read_sleep_retention_test(void)
         .scl_io_num = I2C_SLAVE_SCL_IO,
         .sda_io_num = I2C_SLAVE_SDA_IO,
         .slave_addr = 0x58,
+        .flags.allow_pd = true,
     };
 
     i2c_slave_dev_handle_t slave_handle;
@@ -128,7 +134,9 @@ static void i2c_slave_read_sleep_retention_test(void)
 
     unity_send_signal("i2c slave receive once, master to sleep");
     // Slave sleep as well..
+#if ESP_SLEEP_POWER_DOWN_CPU
     TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
     TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
     TEST_ESP_OK(esp_light_sleep_start());
 
@@ -147,7 +155,9 @@ static void i2c_slave_read_sleep_retention_test(void)
 
     vQueueDelete(s_receive_queue);
     unity_send_signal("ready to delete");
+#if ESP_SLEEP_POWER_DOWN_CPU
     TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
     TEST_ESP_OK(i2c_del_slave_device(slave_handle));
 }
 
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py
index 56a8eb0bf89..7840f8d32e5 100644
--- a/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py
+++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/pytest_i2c.py
@@ -31,6 +31,9 @@ def test_i2c(dut: Dut) -> None:
     'count, config',
     [
         (2, 'defaults',),
+        (2, 'release',),
+        (2, 'iram_safe',),
+        (2, 'slave_v2',),
     ],
     indirect=True
 )
@@ -38,19 +41,3 @@ def test_i2c_multi_device(case_tester) -> None:        # type: ignore
     for case in case_tester.test_menu:
         if case.attributes.get('test_env', 'generic_multi_device') == 'generic_multi_device':
             case_tester.run_multi_dev_case(case=case, reset=True)
-
-
-@pytest.mark.esp32c6
-@pytest.mark.esp32h2
-@pytest.mark.generic_multi_device
-@pytest.mark.parametrize(
-    'count, config',
-    [
-        (2, 'sleep_retention',),
-    ],
-    indirect=True
-)
-def test_i2c_sleep_retention(case_tester) -> None:        # type: ignore
-    for case in case_tester.test_menu:
-        if case.attributes.get('test_env', 'generic_multi_device') == 'generic_multi_device':
-            case_tester.run_multi_dev_case(case=case, reset=True, timeout=250)
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe
index 3d824868635..05c3f1a8d13 100644
--- a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe
+++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.iram_safe
@@ -2,5 +2,6 @@ CONFIG_PM_ENABLE=y
 CONFIG_COMPILER_DUMP_RTL_FILES=y
 CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
 CONFIG_COMPILER_OPTIMIZATION_NONE=y
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
 CONFIG_I2C_ISR_IRAM_SAFE=y
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release
index 91d93f163e6..eb643d4d06b 100644
--- a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release
+++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.release
@@ -1,4 +1,5 @@
 CONFIG_PM_ENABLE=y
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
 CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
 CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.slave_v2 b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.slave_v2
new file mode 100644
index 00000000000..e0e63260b96
--- /dev/null
+++ b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.slave_v2
@@ -0,0 +1 @@
+CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2=y
diff --git a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.sleep_retention b/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.sleep_retention
deleted file mode 100644
index 219e27e6b93..00000000000
--- a/components/esp_driver_i2c/test_apps/i2c_test_apps/sdkconfig.ci.sleep_retention
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_PM_ENABLE=y
-CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
-CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
-CONFIG_IEEE802154_ENABLED=y
-CONFIG_IEEE802154_SLEEP_ENABLE=y
diff --git a/components/esp_driver_i2s/CMakeLists.txt b/components/esp_driver_i2s/CMakeLists.txt
index cc39943ae66..2498fa6126a 100644
--- a/components/esp_driver_i2s/CMakeLists.txt
+++ b/components/esp_driver_i2s/CMakeLists.txt
@@ -30,6 +30,10 @@ if(CONFIG_SOC_LP_I2S_SUPPORTED)
     list(APPEND srcs "lp_i2s.c" "lp_i2s_std.c" "lp_i2s_pdm.c")
 endif()
 
+if(CONFIG_SOC_LP_I2S_SUPPORT_VAD)
+    list(APPEND srcs "lp_i2s_vad.c")
+endif()
+
 idf_component_register(SRCS ${srcs}
                     INCLUDE_DIRS ${include}
                     PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm
diff --git a/components/esp_driver_i2s/i2s_pdm.c b/components/esp_driver_i2s/i2s_pdm.c
index 9d10058af49..86d899a933f 100644
--- a/components/esp_driver_i2s/i2s_pdm.c
+++ b/components/esp_driver_i2s/i2s_pdm.c
@@ -199,11 +199,6 @@ esp_err_t i2s_channel_init_pdm_tx_mode(i2s_chan_handle_t handle, const i2s_pdm_t
 
 #ifdef CONFIG_PM_ENABLE
     esp_pm_lock_type_t pm_type = ESP_PM_APB_FREQ_MAX;
-#if SOC_I2S_SUPPORTS_APLL
-    if (pdm_tx_cfg->clk_cfg.clk_src == I2S_CLK_SRC_APLL) {
-        pm_type = ESP_PM_NO_LIGHT_SLEEP;
-    }
-#endif // SOC_I2S_SUPPORTS_APLL
     ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_type, 0, "i2s_driver", &handle->pm_lock), TAG, "I2S pm lock create failed");
 #endif
 
diff --git a/components/esp_driver_i2s/i2s_std.c b/components/esp_driver_i2s/i2s_std.c
index 109aaa0bc51..564f2cd4f71 100644
--- a/components/esp_driver_i2s/i2s_std.c
+++ b/components/esp_driver_i2s/i2s_std.c
@@ -240,11 +240,6 @@ esp_err_t i2s_channel_init_std_mode(i2s_chan_handle_t handle, const i2s_std_conf
 
 #ifdef CONFIG_PM_ENABLE
     esp_pm_lock_type_t pm_type = ESP_PM_APB_FREQ_MAX;
-#if SOC_I2S_SUPPORTS_APLL
-    if (std_cfg->clk_cfg.clk_src == I2S_CLK_SRC_APLL) {
-        pm_type = ESP_PM_NO_LIGHT_SLEEP;
-    }
-#endif // SOC_I2S_SUPPORTS_APLL
     ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_type, 0, "i2s_driver", &handle->pm_lock), TAG, "I2S pm lock create failed");
 #endif
 
diff --git a/components/esp_driver_i2s/i2s_tdm.c b/components/esp_driver_i2s/i2s_tdm.c
index 6d579105ed5..f0dce4d55a1 100644
--- a/components/esp_driver_i2s/i2s_tdm.c
+++ b/components/esp_driver_i2s/i2s_tdm.c
@@ -246,11 +246,6 @@ esp_err_t i2s_channel_init_tdm_mode(i2s_chan_handle_t handle, const i2s_tdm_conf
 #endif
 #ifdef CONFIG_PM_ENABLE
     esp_pm_lock_type_t pm_type = ESP_PM_APB_FREQ_MAX;
-#if SOC_I2S_SUPPORTS_APLL
-    if (tdm_cfg->clk_cfg.clk_src == I2S_CLK_SRC_APLL) {
-        pm_type = ESP_PM_NO_LIGHT_SLEEP;
-    }
-#endif // SOC_I2S_SUPPORTS_APLL
     ESP_RETURN_ON_ERROR(esp_pm_lock_create(pm_type, 0, "i2s_driver", &handle->pm_lock), TAG, "I2S pm lock create failed");
 #endif
 
diff --git a/components/esp_driver_i2s/include/driver/lp_i2s_vad.h b/components/esp_driver_i2s/include/driver/lp_i2s_vad.h
new file mode 100644
index 00000000000..ce52370cde6
--- /dev/null
+++ b/components/esp_driver_i2s/include/driver/lp_i2s_vad.h
@@ -0,0 +1,153 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "esp_err.h"
+#include "driver/i2s_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief State Machine
+                                           ┌──────────────────────────────────┐
+                                           │                                  │
+                             ┌─────────────┤  speak-activity-listening-state  │ ◄───────────────┐
+                             │             │                                  │                 │
+                             │             └──────────────────────────────────┘                 │
+                             │                          ▲                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+detected speak activity      │                          │  detected speak activity              │   detected speak activity
+        >=                   │                          │          >=                           │           >=
+'speak_activity_thresh'      │                          │  'min_speak_activity_thresh'          │   'max_speak_activity_thresh'
+                             │                          │                                       │
+                             │                          │          &&                           │
+                             │                          │                                       │
+                             │                          │  detected non-speak activity          │
+                             │                          │           <                           │
+                             │                          │  'non_speak_activity_thresh'          │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │              ┌───────────┴─────────────────────┐                 │
+                             │              │                                 │                 │
+                             └───────────►  │ speak-activity-detected-state   ├─────────────────┘
+                                            │                                 │
+                                            └─┬───────────────────────────────┘
+                                              │
+                                              │                     ▲
+                                              │                     │
+                                              │                     │
+                                              │                     │  detected speak activity
+                                              │                     │          >=
+                                              │                     │  'min_speak_activity_thresh'
+                                              │                     │
+                                              │                     │          &&
+                                              │                     │
+                                              │                     │  detected non-speak activity
+                                              │                     │           <
+                                              └─────────────────────┘  'non_speak_activity_thresh'
+*/
+
+/**
+ * @brief LP VAD peripheral
+ */
+typedef uint32_t lp_vad_t;
+
+/**
+ * @brief Type of VAD unit handle
+ */
+typedef struct vad_unit_ctx_t *vad_unit_handle_t;
+
+/**
+ * @brief LP VAD configurations
+ */
+typedef struct {
+    int init_frame_num;               /**< Number of init frames that are used for VAD to denoise, this helps the VAD to decrease the accidental trigger ratio.
+                                           Note too big values may lead to voice activity miss */
+    int min_energy_thresh;            ///< Min energy threshold.
+    bool skip_band_energy_thresh;     ///< Skip band energy threshold or not
+
+    int speak_activity_thresh;        /**< When in speak-activity-listening-state, if number of the detected speak activity is higher than this value, VAD runs into speak-activity-detected-state */
+
+    int non_speak_activity_thresh;    /**< When in speak-activity-detected-state, if the number of the detected speak activity is higher than this value, but lower than `max_speak_activity_thresh`:
+                                           - if the number of the detected non-speak activity is higher than this value, VAD runs into speak-activity-listening-state
+                                           - if the number of the detected non-speak activity is lower than this value, VAD keeps in speak-activity-detected-state */
+
+    int min_speak_activity_thresh;    /**< When in speak-activity-detected-state, if the number of the detected speak activity is higher than this value, but lower than `max_speak_activity_thresh`,
+                                           then the VAD state machine will depends on the value of `non_speak_activity_thresh` */
+
+    int max_speak_activity_thresh;    /**< When in speak-activity-detected-state, if the number of the detected speak activity is higher than this value, VAD runs into speak-activity-listening-state */
+} lp_vad_config_t;
+
+typedef struct {
+    lp_i2s_chan_handle_t    lp_i2s_chan;  ///< LP I2S channel handle
+    lp_vad_config_t         vad_config;   ///< LP VAD config
+} lp_vad_init_config_t;
+
+/**
+ * @brief New LP VAD unit
+ * @param[in]  vad_id        VAD id
+ * @param[in]  init_config   Initial configurations
+ * @param[out] ret_unit      Unit handle
+ *
+ * @return
+ *        - ESP_OK:                 On success
+ *        - ESP_ERR_INVALID_ARG:    Invalid argument
+ *        - ESP_ERR_INVALID_STATE:  Driver state is invalid, you shouldn't call this API at this moment
+ */
+esp_err_t lp_i2s_vad_new_unit(lp_vad_t vad_id, const lp_vad_init_config_t *init_config, vad_unit_handle_t *ret_unit);
+
+/**
+ * @brief Enable LP VAD
+ *
+ * @param[in] unit          VAD handle
+ * @param[in] init_config   Initial configurations
+ *
+ * @return
+ *        - ESP_OK:                 On success
+ *        - ESP_ERR_INVALID_ARG:    Invalid argument
+ *        - ESP_ERR_INVALID_STATE:  Driver state is invalid, you shouldn't call this API at this moment
+ */
+esp_err_t lp_i2s_vad_enable(vad_unit_handle_t unit);
+
+/**
+ * @brief Disable LP VAD
+ *
+ * @param[in] unit          VAD handle
+ * @param[in] init_config   Initial configurations
+ *
+ * @return
+ *        - ESP_OK:                 On success
+ *        - ESP_ERR_INVALID_ARG:    Invalid argument
+ *        - ESP_ERR_INVALID_STATE:  Driver state is invalid, you shouldn't call this API at this moment
+ */
+esp_err_t lp_i2s_vad_disable(vad_unit_handle_t unit);
+
+/**
+ * @brief Delete LP VAD unit
+ * @param[in] unit          VAD handle
+ *
+ * @return
+ *        - ESP_OK:                 On success
+ *        - ESP_ERR_INVALID_ARG:    Invalid argument
+ *        - ESP_ERR_INVALID_STATE:  Driver state is invalid, you shouldn't call this API at this moment
+ */
+esp_err_t lp_i2s_vad_del_unit(vad_unit_handle_t unit);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_driver_i2s/include/esp_private/lp_i2s_private.h b/components/esp_driver_i2s/include/esp_private/lp_i2s_private.h
new file mode 100644
index 00000000000..2785ca02633
--- /dev/null
+++ b/components/esp_driver_i2s/include/esp_private/lp_i2s_private.h
@@ -0,0 +1,27 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "hal/lp_i2s_hal.h"
+#include "driver/i2s_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get LP I2S soc handle
+ *
+ * @param[in] chan  LP I2S channel handle
+ *
+ * @return LP I2S soc handle
+ */
+lp_i2s_soc_handle_t lp_i2s_get_soc_handle(lp_i2s_chan_handle_t chan);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_driver_i2s/lp_i2s.c b/components/esp_driver_i2s/lp_i2s.c
index 7084fc8947e..0d5e43dd8d0 100644
--- a/components/esp_driver_i2s/lp_i2s.c
+++ b/components/esp_driver_i2s/lp_i2s.c
@@ -25,6 +25,7 @@
 #include "driver/lp_i2s.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/i2s_platform.h"
+#include "esp_private/lp_i2s_private.h"
 #include "i2s_private.h"
 #include "soc/i2s_periph.h"
 
@@ -329,3 +330,15 @@ static void IRAM_ATTR s_i2s_default_isr(void *arg)
         portYIELD_FROM_ISR();
     }
 }
+
+/*---------------------------------------------------------------
+                      HELPERS
+---------------------------------------------------------------*/
+lp_i2s_soc_handle_t lp_i2s_get_soc_handle(lp_i2s_chan_handle_t chan)
+{
+    if (!chan) {
+        return NULL;
+    }
+
+    return chan->ctlr->hal.dev;
+}
diff --git a/components/esp_driver_i2s/lp_i2s_vad.c b/components/esp_driver_i2s/lp_i2s_vad.c
new file mode 100644
index 00000000000..f1cc63559ec
--- /dev/null
+++ b/components/esp_driver_i2s/lp_i2s_vad.c
@@ -0,0 +1,112 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <inttypes.h>
+#include "soc/soc_caps.h"
+#include "stdatomic.h"
+#if SOC_LP_VAD_SUPPORTED
+#include "esp_check.h"
+#include "esp_err.h"
+#include "driver/lp_i2s_vad.h"
+#include "esp_heap_caps.h"
+#include "hal/lp_i2s_ll.h"
+#include "hal/lp_i2s_hal.h"
+#include "esp_private/lp_i2s_private.h"
+
+#define LP_VAD_MEM_ALLOC_CAPS      (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
+
+static const char *LP_VAD_TAG = "LP_VAD";
+
+typedef enum {
+    VAD_FSM_INIT,
+    VAD_FSM_ENABLE,
+} vad_fsm_t;
+
+typedef struct vad_unit_ctx_t {
+    lp_i2s_soc_handle_t hw;
+    lp_vad_t vad_id;
+    vad_fsm_t fsm;
+} vad_unit_ctx_t;
+
+static atomic_bool s_vad_id_claimed[SOC_ADC_PERIPH_NUM] = {ATOMIC_VAR_INIT(false)};
+
+static bool s_vad_claim(lp_vad_t vad_id)
+{
+    bool false_var = false;
+    return atomic_compare_exchange_strong(&s_vad_id_claimed[vad_id], &false_var, true);
+}
+
+static bool s_vad_free(lp_vad_t vad_id)
+{
+    bool true_var = true;
+    return atomic_compare_exchange_strong(&s_vad_id_claimed[vad_id], &true_var, false);
+}
+
+esp_err_t lp_i2s_vad_new_unit(lp_vad_t vad_id, const lp_vad_init_config_t *init_config, vad_unit_handle_t *ret_unit)
+{
+    esp_err_t ret = ESP_OK;
+    ESP_RETURN_ON_FALSE(init_config, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid arg");
+    ESP_RETURN_ON_FALSE(init_config->lp_i2s_chan, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "LP I2S not initialised");
+    ESP_RETURN_ON_FALSE(init_config->vad_config.init_frame_num >= LP_VAD_LL_INIT_FRAME_MIN && init_config->vad_config.init_frame_num <= LP_VAD_LL_INIT_FRAME_MAX, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid init frame num");
+
+    bool success_claim = s_vad_claim(vad_id);
+    ESP_RETURN_ON_FALSE(success_claim, ESP_ERR_NOT_FOUND, LP_VAD_TAG, "vad%"PRId32" is already in use", vad_id);
+
+    vad_unit_ctx_t *unit = heap_caps_calloc(1, sizeof(vad_unit_ctx_t), LP_VAD_MEM_ALLOC_CAPS);
+    ESP_GOTO_ON_FALSE(unit, ESP_ERR_NO_MEM, err, LP_VAD_TAG, "no mem for unit");
+
+    unit->hw = lp_i2s_get_soc_handle(init_config->lp_i2s_chan);
+    ESP_LOGD(LP_VAD_TAG, "unit->hw: %p", unit->hw);
+    lp_vad_ll_set_init_frame_num(unit->hw, init_config->vad_config.init_frame_num);
+    lp_vad_ll_set_init_min_energy(unit->hw, init_config->vad_config.min_energy_thresh);
+    lp_vad_ll_set_speak_activity_thresh(unit->hw, init_config->vad_config.speak_activity_thresh);
+    lp_vad_ll_set_non_speak_activity_thresh(unit->hw, init_config->vad_config.non_speak_activity_thresh);
+    lp_vad_ll_set_min_speak_activity_thresh(unit->hw, init_config->vad_config.min_speak_activity_thresh);
+    lp_vad_ll_set_max_speak_activity_thresh(unit->hw, init_config->vad_config.max_speak_activity_thresh);
+    lp_vad_ll_skip_band_energy(unit->hw, init_config->vad_config.skip_band_energy_thresh);
+    unit->fsm = VAD_FSM_INIT;
+    *ret_unit = unit;
+
+    return ESP_OK;
+err:
+    bool success_free = s_vad_free(vad_id);
+    assert(success_free);
+
+    return ret;
+}
+
+esp_err_t lp_i2s_vad_enable(vad_unit_handle_t unit)
+{
+    ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid arg");
+    ESP_RETURN_ON_FALSE(unit->fsm == VAD_FSM_INIT, ESP_ERR_INVALID_STATE, LP_VAD_TAG, "The driver is enabled already");
+
+    lp_vad_ll_enable(unit->hw, true);
+    unit->fsm = VAD_FSM_ENABLE;
+    return ESP_OK;
+}
+
+esp_err_t lp_i2s_vad_disable(vad_unit_handle_t unit)
+{
+    ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid arg");
+    ESP_RETURN_ON_FALSE(unit->fsm == VAD_FSM_ENABLE, ESP_ERR_INVALID_STATE, LP_VAD_TAG, "The driver is not enabled yet");
+
+    lp_vad_ll_enable(unit->hw, false);
+    unit->fsm = VAD_FSM_INIT;
+    return ESP_OK;
+}
+
+esp_err_t lp_i2s_vad_del_unit(vad_unit_handle_t unit)
+{
+    ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, LP_VAD_TAG, "invalid arg");
+    ESP_RETURN_ON_FALSE(unit->fsm == VAD_FSM_INIT, ESP_ERR_INVALID_STATE, LP_VAD_TAG, "The driver is still in enabled state");
+
+    bool success_free = s_vad_free(unit->vad_id);
+    ESP_RETURN_ON_FALSE(success_free, ESP_ERR_NOT_FOUND, LP_VAD_TAG, "vad%"PRId32" isn't in use", unit->vad_id);
+
+    free(unit);
+    return ESP_OK;
+}
+#endif /* SOC_LP_VAD_SUPPORTED */
diff --git a/components/esp_driver_i2s/test_apps/.build-test-rules.yml b/components/esp_driver_i2s/test_apps/.build-test-rules.yml
index 8ecfb0daeb2..78e2a417f16 100644
--- a/components/esp_driver_i2s/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_i2s/test_apps/.build-test-rules.yml
@@ -12,7 +12,7 @@ components/esp_driver_i2s/test_apps/i2s_multi_dev:
     - if: SOC_I2S_SUPPORTED != 1
     - if: SOC_I2S_HW_VERSION_2 != 1
   disable_test:
-    - if: IDF_TARGET in ["esp32p4", "esp32c5"]  # TODO: [ESP32C5] IDF- 10321
+    - if: IDF_TARGET in ["esp32c61"]  # TODO: [ESP32C61] IDF-11442
       temporary: true
       reason: lack of runners
   depends_components:
diff --git a/components/esp_driver_i2s/test_apps/i2s/README.md b/components/esp_driver_i2s/test_apps/i2s/README.md
index 46d16c788ce..844e5ee973b 100644
--- a/components/esp_driver_i2s/test_apps/i2s/README.md
+++ b/components/esp_driver_i2s/test_apps/i2s/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
diff --git a/components/esp_driver_i2s/test_apps/i2s/pytest_i2s.py b/components/esp_driver_i2s/test_apps/i2s/pytest_i2s.py
index a2fa85533b3..138769c5948 100644
--- a/components/esp_driver_i2s/test_apps/i2s/pytest_i2s.py
+++ b/components/esp_driver_i2s/test_apps/i2s/pytest_i2s.py
@@ -12,6 +12,7 @@
 @pytest.mark.esp32s3
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
+@pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
diff --git a/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.release b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.release
index 998cfb51f82..7c7f2a2efa6 100644
--- a/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.release
+++ b/components/esp_driver_i2s/test_apps/i2s/sdkconfig.ci.release
@@ -4,3 +4,4 @@ CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
 CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
+CONFIG_PM_DFS_INIT_AUTO=y
diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md b/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md
index 61d1e027920..c91eb572ca8 100644
--- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md
+++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/README.md
@@ -1,3 +1,3 @@
-| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
 
diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c
index 3f2737b0b35..35b1b237602 100644
--- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c
+++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/main/test_i2s_multi_dev.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -161,6 +161,9 @@ static void test_i2s_tdm_slave(uint32_t sample_rate, i2s_data_bit_width_t bit_wi
     if (sample_rate >= 96000) {
         i2s_tdm_config.clk_cfg.bclk_div = 12;
     }
+#if SOC_I2S_SUPPORTS_APLL
+    i2s_tdm_config.clk_cfg.clk_src = I2S_CLK_SRC_APLL;
+#endif
     TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_tx_handle, &i2s_tdm_config));
     TEST_ESP_OK(i2s_channel_init_tdm_mode(i2s_tdm_rx_handle, &i2s_tdm_config));
 
@@ -237,8 +240,9 @@ TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_48k_8bits_4slots", "[I2S
                            test_i2s_tdm_master_48k_8bits_4slots, test_i2s_tdm_slave_48k_8bits_4slots);
 
 /* The I2S source clock can only reach 96Mhz on ESP32H2,
+   and the max clock source APLL on P4 is 125M,
    which can't satisfy the following configurations in slave mode */
-#if !CONFIG_IDF_TARGET_ESP32H2
+#if !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4
 static void test_i2s_tdm_master_48k_16bits_8slots(void)
 {
     test_i2s_tdm_master(48000, I2S_DATA_BIT_WIDTH_16BIT, I2S_TDM_SLOT0 | I2S_TDM_SLOT1 | I2S_TDM_SLOT2 | I2S_TDM_SLOT3 |
@@ -266,7 +270,7 @@ static void test_i2s_tdm_slave_96k_16bits_4slots(void)
 
 TEST_CASE_MULTIPLE_DEVICES("I2S_TDM_full_duplex_test_in_96k_16bits_4slots", "[I2S_TDM]",
                            test_i2s_tdm_master_96k_16bits_4slots, test_i2s_tdm_slave_96k_16bits_4slots);
-#endif  // !CONFIG_IDF_TARGET_ESP32H2
+#endif  // !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4
 
 static void test_i2s_external_clk_src(bool is_master, bool is_external)
 {
@@ -279,22 +283,15 @@ static void test_i2s_external_clk_src(bool is_master, bool is_external)
         .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(16, I2S_SLOT_MODE_STEREO),
         .gpio_cfg = TEST_I2S_DEFAULT_GPIO(TEST_I2S_MCK_IO, is_master),
     };
+    std_cfg.clk_cfg.mclk_multiple = I2S_MCLK_MULTIPLE_512;
     if (is_external) {
         std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_EXTERNAL;
-        std_cfg.clk_cfg.ext_clk_freq_hz = 11289600;
+        std_cfg.clk_cfg.ext_clk_freq_hz = 22579200;
     }
     TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &std_cfg));
-    if (is_master && !is_external) {
-        i2s_std_slot_config_t slot_cfg = I2S_STD_PHILIPS_SLOT_DEFAULT_CONFIG(16, I2S_SLOT_MODE_STEREO);
-        memcpy(&std_cfg.slot_cfg, &slot_cfg, sizeof(i2s_std_slot_config_t));
-    }
     TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
 
     if (is_master) {
-        if (!is_external) {
-            // Delay bclk to get compensate the data delay
-            I2S0.rx_timing.rx_bck_out_dm = 1;
-        }
         uint8_t mst_tx_data[4] = {0x12, 0x34, 0x56, 0x78};
         size_t w_bytes = 4;
         while (w_bytes == 4) {
diff --git a/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py
index 3d53063d50e..000bb65e399 100644
--- a/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py
+++ b/components/esp_driver_i2s/test_apps/i2s_multi_dev/pytest_i2s_multi_dev.py
@@ -5,9 +5,10 @@
 
 @pytest.mark.esp32s3
 @pytest.mark.esp32c3
-# @pytest.mark.esp32c5  # TODO: [ESP32C5] IDF- 10321
+@pytest.mark.esp32c5
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
+@pytest.mark.esp32p4
 @pytest.mark.generic_multi_device
 @pytest.mark.parametrize('count', [
     2,
diff --git a/components/esp_driver_i2s/test_apps/lp_i2s/sdkconfig.ci.defaults b/components/esp_driver_i2s/test_apps/lp_i2s/sdkconfig.ci.defaults
index 5e9f8e25bd8..e69de29bb2d 100644
--- a/components/esp_driver_i2s/test_apps/lp_i2s/sdkconfig.ci.defaults
+++ b/components/esp_driver_i2s/test_apps/lp_i2s/sdkconfig.ci.defaults
@@ -1 +0,0 @@
-CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
diff --git a/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h b/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h
index cbf25114cea..0be715c450b 100644
--- a/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h
+++ b/components/esp_driver_i2s/test_apps/test_inc/test_i2s.h
@@ -22,23 +22,7 @@ extern "C" {
 #define SLAVE_WS_IO 22
 #define DATA_IN_IO 19
 #define DATA_OUT_IO 18
-#elif CONFIG_IDF_TARGET_ESP32S2
-#define MASTER_MCK_IO 0
-#define MASTER_BCK_IO 4
-#define MASTER_WS_IO 5
-#define SLAVE_BCK_IO 14
-#define SLAVE_WS_IO 15
-#define DATA_IN_IO 19
-#define DATA_OUT_IO 18
-#elif CONFIG_IDF_TARGET_ESP32C3
-#define MASTER_MCK_IO 0
-#define MASTER_BCK_IO 4
-#define MASTER_WS_IO 5
-#define SLAVE_BCK_IO 14
-#define SLAVE_WS_IO 15
-#define DATA_IN_IO 19
-#define DATA_OUT_IO 18
-#elif CONFIG_IDF_TARGET_ESP32S3
+#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
 #define MASTER_MCK_IO 0
 #define MASTER_BCK_IO 4
 #define MASTER_WS_IO 5
@@ -50,8 +34,8 @@ extern "C" {
 #define MASTER_MCK_IO 51
 #define MASTER_BCK_IO 45
 #define MASTER_WS_IO 46
-#define SLAVE_BCK_IO 22
-#define SLAVE_WS_IO 23
+#define SLAVE_BCK_IO 49
+#define SLAVE_WS_IO 50
 #define DATA_IN_IO 47
 #define DATA_OUT_IO 48
 #elif CONFIG_IDF_TARGET_ESP32C5
diff --git a/components/esp_driver_isp/CMakeLists.txt b/components/esp_driver_isp/CMakeLists.txt
index 3cffb62c4c0..ab7761edb65 100644
--- a/components/esp_driver_isp/CMakeLists.txt
+++ b/components/esp_driver_isp/CMakeLists.txt
@@ -34,6 +34,10 @@ if(CONFIG_SOC_ISP_COLOR_SUPPORTED)
     list(APPEND srcs "src/isp_color.c")
 endif()
 
+if(CONFIG_SOC_ISP_LSC_SUPPORTED)
+    list(APPEND srcs "src/isp_lsc.c")
+endif()
+
 if(NOT ${target} STREQUAL "linux")
     list(APPEND requires esp_mm)
 endif()
diff --git a/components/esp_driver_isp/include/driver/isp.h b/components/esp_driver_isp/include/driver/isp.h
index 92370fb4279..235aca350ef 100644
--- a/components/esp_driver_isp/include/driver/isp.h
+++ b/components/esp_driver_isp/include/driver/isp.h
@@ -22,3 +22,4 @@
 #include "driver/isp_hist.h"
 #include "driver/isp_sharpen.h"
 #include "driver/isp_color.h"
+#include "driver/isp_lsc.h"
diff --git a/components/esp_driver_isp/include/driver/isp_core.h b/components/esp_driver_isp/include/driver/isp_core.h
index ef8307645c7..c1f61928bf1 100644
--- a/components/esp_driver_isp/include/driver/isp_core.h
+++ b/components/esp_driver_isp/include/driver/isp_core.h
@@ -10,6 +10,7 @@
 #include <stdbool.h>
 #include "esp_err.h"
 #include "driver/isp_types.h"
+#include "hal/color_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -30,6 +31,7 @@ typedef struct {
     bool has_line_end_packet;                     ///< Enable line end packet
     uint32_t h_res;                               ///< Input horizontal resolution, i.e. the number of pixels in a line
     uint32_t v_res;                               ///< Input vertical resolution, i.e. the number of lines in a frame
+    color_raw_element_order_t bayer_order;        ///< Bayer order
     int intr_priority;                            ///< The interrupt priority, range 0~3, if set to 0, the driver will try to allocate an interrupt with a relative low priority (1,2,3)
 } esp_isp_processor_cfg_t;
 
diff --git a/components/esp_driver_isp/include/driver/isp_lsc.h b/components/esp_driver_isp/include/driver/isp_lsc.h
new file mode 100644
index 00000000000..db32c74ff1a
--- /dev/null
+++ b/components/esp_driver_isp/include/driver/isp_lsc.h
@@ -0,0 +1,91 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/isp_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LSC Gain array
+ */
+typedef struct {
+    isp_lsc_gain_t *gain_r;     ///< Gain for R channel
+    isp_lsc_gain_t *gain_gr;    ///< Gain for GR channel
+    isp_lsc_gain_t *gain_gb;    ///< Gain for GB channel
+    isp_lsc_gain_t *gain_b;     ///< Gain for B channel
+} esp_isp_lsc_gain_array_t;
+
+/**
+ * @brief ISP LSC configurations
+ */
+typedef struct {
+    esp_isp_lsc_gain_array_t *gain_array;    ///< Gain array
+} esp_isp_lsc_config_t;
+
+/**
+ * @brief Helper function to allocate gain array for LSC
+ *
+ * @param[in] proc                         Processor handle
+ * @param[in] gain_array                   Gain array to be allocated
+ * @param[out] out_array_size_per_channel  Array size
+ *
+ * @return
+ *        - ESP_OK                 On success
+ *        - ESP_ERR_INVALID_STATE  Not allowed to be called under current state
+ *        - ESP_ERR_INVALID_ARG    If the combination of arguments is invalid
+ *        - ESP_ERR_NO_MEM         Out of memory
+ */
+esp_err_t esp_isp_lsc_allocate_gain_array(isp_proc_handle_t isp_proc, esp_isp_lsc_gain_array_t *gain_array, size_t *out_array_size_per_channel);
+
+/**
+ * @brief ISP LSC configuration
+ *
+ * @note After calling this API, LSC doesn't take into effect until `esp_isp_lsc_enable` is called
+ *
+ * @param[in] proc    Processor handle
+ * @param[in] config  LSC configurations
+ *
+ * @return
+ *        - ESP_OK                 On success
+ *        - ESP_ERR_INVALID_STATE  Not allowed to be called under current state
+ *        - ESP_ERR_INVALID_ARG    If the combination of arguments is invalid
+ *        - ESP_ERR_NOT_SUPPORTED  Not supported
+ */
+esp_err_t esp_isp_lsc_configure(isp_proc_handle_t isp_proc, const esp_isp_lsc_config_t *config);
+
+/**
+ * @brief Enable ISP LSC function
+ *
+ * @param[in] proc  Processor handle
+ *
+ * @return
+ *         - ESP_OK                On success
+ *         - ESP_ERR_INVALID_ARG   If the combination of arguments is invalid.
+ *         - ESP_ERR_INVALID_STATE Driver state is invalid.
+ */
+esp_err_t esp_isp_lsc_enable(isp_proc_handle_t isp_proc);
+
+/**
+ * @brief Disable ISP LSC function
+ *
+ * @param[in] proc  Processor handle
+ *
+ * @return
+ *         - ESP_OK                On success
+ *         - ESP_ERR_INVALID_ARG   If the combination of arguments is invalid.
+ *         - ESP_ERR_INVALID_STATE Driver state is invalid.
+ */
+esp_err_t esp_isp_lsc_disable(isp_proc_handle_t isp_proc);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_driver_isp/include/esp_private/isp_private.h b/components/esp_driver_isp/include/esp_private/isp_private.h
index 1f96bea135c..a0e6913ca59 100644
--- a/components/esp_driver_isp/include/esp_private/isp_private.h
+++ b/components/esp_driver_isp/include/esp_private/isp_private.h
@@ -64,6 +64,7 @@ typedef struct isp_processor_t {
     color_space_pixel_format_t  out_color_format;
     uint32_t                    h_res;
     uint32_t                    v_res;
+    color_raw_element_order_t   bayer_order;
     /* sub module contexts */
     isp_af_ctlr_t               af_ctlr[SOC_ISP_AF_CTLR_NUMS];
     isp_awb_ctlr_t              awb_ctlr;
@@ -73,6 +74,7 @@ typedef struct isp_processor_t {
     isp_fsm_t                   demosaic_fsm;
     isp_fsm_t                   sharpen_fsm;
     isp_fsm_t                   color_fsm;
+    isp_fsm_t                   lsc_fsm;
     esp_isp_evt_cbs_t           cbs;
     void                        *user_data;
 
@@ -85,7 +87,7 @@ typedef struct isp_processor_t {
         uint32_t                ae_isr_added:    1;
         uint32_t                awb_isr_added:   1;
         uint32_t                sharp_isr_added: 1;
-        uint32_t                hist_isr_added: 1;
+        uint32_t                hist_isr_added:  1;
     } isr_users;
 
 } isp_processor_t;
diff --git a/components/esp_driver_isp/src/isp_core.c b/components/esp_driver_isp/src/isp_core.c
index f3ff71e625f..f964aaa1ccb 100644
--- a/components/esp_driver_isp/src/isp_core.c
+++ b/components/esp_driver_isp/src/isp_core.c
@@ -139,6 +139,7 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_
     isp_ll_enable_line_end_packet_exist(proc->hal.hw, proc_config->has_line_end_packet);
     isp_ll_set_intput_data_h_pixel_num(proc->hal.hw, proc_config->h_res);
     isp_ll_set_intput_data_v_row_num(proc->hal.hw, proc_config->v_res);
+    isp_ll_set_bayer_mode(proc->hal.hw, proc_config->bayer_order);
     isp_ll_yuv_set_std(proc->hal.hw, proc_config->yuv_std);
     if (out_color_format.color_space == COLOR_SPACE_YUV) {
         isp_ll_yuv_set_range(proc->hal.hw, proc_config->yuv_range);
@@ -148,6 +149,7 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_
     proc->out_color_format = out_color_format;
     proc->h_res = proc_config->h_res;
     proc->v_res = proc_config->v_res;
+    proc->bayer_order = proc_config->bayer_order;
 
     *ret_proc = proc;
 
diff --git a/components/esp_driver_isp/src/isp_lsc.c b/components/esp_driver_isp/src/isp_lsc.c
new file mode 100644
index 00000000000..d8996e29059
--- /dev/null
+++ b/components/esp_driver_isp/src/isp_lsc.c
@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdatomic.h>
+#include "sdkconfig.h"
+#include "esp_log.h"
+#include "esp_check.h"
+#include "freertos/FreeRTOS.h"
+#include "driver/isp_core.h"
+#include "driver/isp_bf.h"
+#include "driver/isp_lsc.h"
+#include "esp_private/isp_private.h"
+#include "hal/efuse_hal.h"
+#include "soc/chip_revision.h"
+
+/*---------------------------------------------------------------
+                      LSC
+---------------------------------------------------------------*/
+#define ISP_LSC_GET_GRIDS(res)    (((res) - 1) / 2 / ISP_LL_LSC_GRID_HEIGHT + 2)
+
+static const char *TAG = "ISP_LSC";
+
+esp_err_t esp_isp_lsc_allocate_gain_array(isp_proc_handle_t isp_proc, esp_isp_lsc_gain_array_t *gain_array, size_t *out_array_size_per_channel)
+{
+    ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
+    ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already");
+
+    int num_grids_x_max = ISP_LSC_GET_GRIDS(ISP_LL_HSIZE_MAX);
+    int num_grids_y_max = ISP_LSC_GET_GRIDS(ISP_LL_VSIZE_MAX);
+    int num_grids_x = ISP_LSC_GET_GRIDS(isp_proc->h_res);
+    int num_grids_y = ISP_LSC_GET_GRIDS(isp_proc->v_res);
+    ESP_LOGD(TAG, "num_grids_x_max: %d, num_grids_x: %d, num_grids_y_max: %d, num_grids_y: %d", num_grids_x_max, num_grids_y_max, num_grids_x, num_grids_y);
+    ESP_RETURN_ON_FALSE(num_grids_x <= num_grids_x_max && num_grids_y <= num_grids_y_max, ESP_ERR_INVALID_ARG, TAG, "invalid h_res or v_res");
+
+    gain_array->gain_r = (isp_lsc_gain_t *)heap_caps_calloc(1, num_grids_x * num_grids_y * sizeof(isp_lsc_gain_t), ISP_MEM_ALLOC_CAPS);
+    gain_array->gain_gr = (isp_lsc_gain_t *)heap_caps_calloc(1, num_grids_x * num_grids_y * sizeof(isp_lsc_gain_t), ISP_MEM_ALLOC_CAPS);
+    gain_array->gain_gb = (isp_lsc_gain_t *)heap_caps_calloc(1, num_grids_x * num_grids_y * sizeof(isp_lsc_gain_t), ISP_MEM_ALLOC_CAPS);
+    gain_array->gain_b = (isp_lsc_gain_t *)heap_caps_calloc(1, num_grids_x * num_grids_y * sizeof(isp_lsc_gain_t), ISP_MEM_ALLOC_CAPS);
+
+    if (!gain_array->gain_r || !gain_array->gain_gr || !gain_array->gain_gb || !gain_array->gain_b) {
+        ESP_LOGE(TAG, "no enough mem for gain arrays");
+        return ESP_ERR_NO_MEM;
+    }
+    ESP_LOGD(TAG, "gain_array->gain_r: %p, gain_array->gain_gr: %p, gain_array->gain_gb: %p, gain_array->gain_b: %p", gain_array->gain_r, gain_array->gain_gr, gain_array->gain_gb, gain_array->gain_b);
+    *out_array_size_per_channel = num_grids_x * num_grids_y;
+    return ESP_OK;
+}
+
+esp_err_t esp_isp_lsc_configure(isp_proc_handle_t isp_proc, const esp_isp_lsc_config_t *config)
+{
+#if CONFIG_IDF_TARGET_ESP32P4
+    unsigned chip_version = efuse_hal_chip_revision();
+    if (!ESP_CHIP_REV_ABOVE(chip_version, 100)) {
+        ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "LSC is not supported on ESP32P4 chips prior than ECO2");
+    }
+#endif
+
+    ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
+
+    int num_grids_x_max = ISP_LSC_GET_GRIDS(ISP_LL_HSIZE_MAX);
+    int num_grids_y_max = ISP_LSC_GET_GRIDS(ISP_LL_VSIZE_MAX);
+    int num_grids_x = ISP_LSC_GET_GRIDS(isp_proc->h_res);
+    int num_grids_y = ISP_LSC_GET_GRIDS(isp_proc->v_res);
+    ESP_LOGD(TAG, "num_grids_x_max: %d, num_grids_x: %d, num_grids_y_max: %d, num_grids_y: %d", num_grids_x_max, num_grids_y_max, num_grids_x, num_grids_y);
+    ESP_RETURN_ON_FALSE(num_grids_x <= num_grids_x_max && num_grids_y <= num_grids_y_max, ESP_ERR_INVALID_ARG, TAG, "invalid h_res or v_res");
+    ESP_RETURN_ON_FALSE(config->gain_array->gain_r && config->gain_array->gain_gr && config->gain_array->gain_gb && config->gain_array->gain_b, ESP_ERR_INVALID_ARG, TAG, "null pointer to gain arrays");
+
+    isp_ll_lsc_set_xtablesize(isp_proc->hal.hw, num_grids_x);
+
+    for (int y = 0; y < num_grids_y; y++) {
+        for (int x = 0; x < num_grids_x; x++) {
+            int i = y * num_grids_x + x;
+            isp_ll_lut_set_wdata_r_gr(isp_proc->hal.hw, config->gain_array->gain_r[i], config->gain_array->gain_gr[i]);
+            isp_ll_lut_set_cmd(isp_proc->hal.hw, true, false, i, ISP_LL_LUT_LSC);
+            isp_ll_lut_set_wdata_gb_b(isp_proc->hal.hw, config->gain_array->gain_gb[i], config->gain_array->gain_b[i]);
+            isp_ll_lut_set_cmd(isp_proc->hal.hw, true, true, i, ISP_LL_LUT_LSC);
+        }
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t esp_isp_lsc_enable(isp_proc_handle_t isp_proc)
+{
+    ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
+    ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "lsc is enabled already");
+
+    isp_ll_lsc_clk_enable(isp_proc->hal.hw, true);
+    isp_ll_lsc_enable(isp_proc->hal.hw, true);
+    isp_proc->lsc_fsm = ISP_FSM_ENABLE;
+
+    return ESP_OK;
+}
+
+esp_err_t esp_isp_lsc_disable(isp_proc_handle_t isp_proc)
+{
+    ESP_RETURN_ON_FALSE(isp_proc, ESP_ERR_INVALID_ARG, TAG, "invalid argument: null pointer");
+    ESP_RETURN_ON_FALSE(isp_proc->lsc_fsm == ISP_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "lsc isn't enabled yet");
+
+    isp_ll_lsc_enable(isp_proc->hal.hw, false);
+    isp_ll_lsc_clk_enable(isp_proc->hal.hw, false);
+    isp_proc->lsc_fsm = ISP_FSM_INIT;
+
+    return ESP_OK;
+}
diff --git a/components/esp_driver_jpeg/jpeg_emit_marker.c b/components/esp_driver_jpeg/jpeg_emit_marker.c
index cc6b2be117f..10baa354b55 100644
--- a/components/esp_driver_jpeg/jpeg_emit_marker.c
+++ b/components/esp_driver_jpeg/jpeg_emit_marker.c
@@ -235,7 +235,7 @@ esp_err_t emit_com_marker(jpeg_enc_header_info_t *header_info)
         compensate_size += cache_align;
     }
     emit_marker(header_info, JPEG_M_COM & 0xff);
-    emit_word(header_info, compensate_size);
+    emit_word(header_info, compensate_size + 2);
     for (int i = 0; i < compensate_size; i++) {
         emit_byte(header_info, 0);
     }
diff --git a/components/esp_driver_ledc/include/driver/ledc.h b/components/esp_driver_ledc/include/driver/ledc.h
index bd644e1d681..4245ae83da0 100644
--- a/components/esp_driver_ledc/include/driver/ledc.h
+++ b/components/esp_driver_ledc/include/driver/ledc.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,6 +33,18 @@ extern "C" {
 #define LEDC_ERR_DUTY           (0xFFFFFFFF)
 #define LEDC_ERR_VAL            (-1)
 
+/**
+ * @brief Strategies to be applied to the LEDC channel during system Light-sleep period
+ */
+typedef enum {
+    LEDC_SLEEP_MODE_NO_ALIVE_NO_PD = 0,  /*!< The default mode: no LEDC output, and no power off the LEDC power domain. */
+    LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD,   /*!< The low-power-consumption mode: no LEDC output, and allow to power off the LEDC power domain.
+                                              This can save power, but at the expense of more RAM being consumed to save register context.
+                                              This option is only available on targets that support TOP domain to be powered down. */
+    LEDC_SLEEP_MODE_KEEP_ALIVE,          /*!< The high-power-consumption mode: keep LEDC output when the system enters Light-sleep. */
+    LEDC_SLEEP_MODE_INVALID,             /*!< Invalid LEDC sleep mode strategy */
+} ledc_sleep_mode_t;
+
 /**
  * @brief Configuration parameters of LEDC channel for ledc_channel_config function
  */
@@ -44,6 +56,7 @@ typedef struct {
     ledc_timer_t timer_sel;         /*!< Select the timer source of channel (0 - LEDC_TIMER_MAX-1) */
     uint32_t duty;                  /*!< LEDC channel duty, the range of duty setting is [0, (2**duty_resolution)] */
     int hpoint;                     /*!< LEDC channel hpoint value, the range is [0, (2**duty_resolution)-1] */
+    ledc_sleep_mode_t sleep_mode;   /*!< choose the desired behavior for the LEDC channel in Light-sleep */
     struct {
         unsigned int output_invert: 1;/*!< Enable (1) or disable (0) gpio output invert */
     } flags;                        /*!< LEDC flags */
diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c
index 9e9be008e2c..b3495e3c063 100644
--- a/components/esp_driver_ledc/src/ledc.c
+++ b/components/esp_driver_ledc/src/ledc.c
@@ -25,6 +25,12 @@
 #include "esp_private/esp_clk_tree_common.h"
 #include "esp_private/esp_gpio_reserve.h"
 #include "esp_memory_utils.h"
+#include "esp_private/sleep_retention.h"
+#if SOC_PMU_SUPPORTED // TODO: replace when icg API available IDF-7595
+#include "soc/pmu_struct.h"
+#include "hal/pmu_types.h"
+#include "soc/pmu_icg_mapping.h"
+#endif
 
 static __attribute__((unused)) const char *LEDC_TAG = "ledc";
 
@@ -58,6 +64,8 @@ static __attribute__((unused)) const char *LEDC_TAG = "ledc";
 #define LEDC_FUNC_CLOCK_ATOMIC()
 #endif
 
+#define LEDC_USE_RETENTION_LINK  (SOC_LEDC_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+
 typedef enum {
     LEDC_FSM_IDLE,
     LEDC_FSM_HW_FADE,
@@ -87,6 +95,10 @@ typedef struct {
 #if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
     ledc_clk_src_t timer_specific_clk[LEDC_TIMER_MAX];  /*!< Tracks the timer-specific clock selection for each timer */
 #endif
+    ledc_sleep_mode_t sleep_mode;                       /*!< Records the sleep strategy to be applied to the LEDC module */
+    bool channel_keep_alive[LEDC_CHANNEL_MAX];          /*!< Records whether each channel needs to keep output during sleep */
+    uint8_t timer_xpd_ref_cnt[LEDC_TIMER_MAX];          /*!< Records the timer (glb_clk) not power down during sleep requirement */
+    bool glb_clk_xpd;                                   /*!< Records the power strategy applied to the global clock */
 } ledc_obj_t;
 
 static ledc_obj_t *p_ledc_obj[LEDC_SPEED_MODE_MAX] = {
@@ -118,6 +130,37 @@ static const ledc_slow_clk_sel_t s_glb_clks[] = LEDC_LL_GLOBAL_CLOCKS;
 static const ledc_clk_src_t s_timer_specific_clks[] = LEDC_LL_TIMER_SPECIFIC_CLOCKS;
 #endif
 
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+static esp_err_t ledc_create_sleep_retention_link_cb(void *arg)
+{
+#if SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    sleep_retention_module_t module = ledc_reg_retention_info.module_id;
+
+    esp_err_t err = sleep_retention_entries_create(ledc_reg_retention_info.common.regdma_entry_array,
+                                                   ledc_reg_retention_info.common.array_size,
+                                                   REGDMA_LINK_PRI_LEDC, module);
+    bool slp_retention_create_failed = (err != ESP_OK);
+
+    for (int i = 0; i < SOC_LEDC_TIMER_NUM && !slp_retention_create_failed; i++) {
+        err = sleep_retention_entries_create(ledc_reg_retention_info.timer[i].regdma_entry_array,
+                                             ledc_reg_retention_info.timer[i].array_size,
+                                             REGDMA_LINK_PRI_LEDC, module);
+        slp_retention_create_failed |= (err != ESP_OK);
+    }
+
+    for (int j = 0; j < SOC_LEDC_CHANNEL_NUM && !slp_retention_create_failed; j++) {
+        err = sleep_retention_entries_create(ledc_reg_retention_info.channel[j].regdma_entry_array,
+                                             ledc_reg_retention_info.channel[j].array_size,
+                                             REGDMA_LINK_PRI_LEDC, module);
+        slp_retention_create_failed |= (err != ESP_OK);
+    }
+
+    ESP_RETURN_ON_FALSE(!slp_retention_create_failed, err, LEDC_TAG, "create retention link failed");
+#endif
+    return ESP_OK;
+}
+#endif
+
 static void ledc_ls_timer_update(ledc_mode_t speed_mode, ledc_timer_t timer_sel)
 {
     if (speed_mode == LEDC_LOW_SPEED_MODE) {
@@ -240,15 +283,78 @@ static IRAM_ATTR esp_err_t ledc_duty_config(ledc_mode_t speed_mode, ledc_channel
     return ESP_OK;
 }
 
+/**
+ * return 1 if the global clock cannot keep alive in sleep, as an error raised
+ */
+static bool ledc_glb_clk_set_sleep_mode(ledc_mode_t speed_mode, bool xpd)
+{
+    bool glb_clk_xpd_err = false;
+    if (p_ledc_obj[speed_mode]->glb_clk == LEDC_SLOW_CLK_RC_FAST) {
+        esp_sleep_sub_mode_config(ESP_SLEEP_DIG_USE_RC_FAST_MODE, xpd);
+        p_ledc_obj[speed_mode]->glb_clk_xpd = xpd;
+    }
+#if SOC_LEDC_SUPPORT_XTAL_CLOCK
+    else if (p_ledc_obj[speed_mode]->glb_clk == LEDC_SLOW_CLK_XTAL) {
+        esp_sleep_sub_mode_config(ESP_SLEEP_DIG_USE_XTAL_MODE, xpd);
+        p_ledc_obj[speed_mode]->glb_clk_xpd = xpd;
+    }
+#endif
+    else {
+        if (xpd) {
+            glb_clk_xpd_err = true;
+        }
+    }
+    return glb_clk_xpd_err;
+}
+
+/**
+ * spinlock should wrap outside
+ * return 1 if the timer cannot keep alive in sleep, as an error raised
+ */
+static bool ledc_timer_clk_src_set_xpd_in_sleep(ledc_mode_t speed_mode, ledc_timer_t timer_sel)
+{
+    p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[timer_sel]++;
+    bool timer_clock_xpd_err = false;
+    // if the timer has not been configured yet, leave the xpd configuration to ledc_timer_config
+    if (p_ledc_obj[speed_mode]->glb_clk_is_acquired[timer_sel] && p_ledc_obj[speed_mode]->glb_clk != LEDC_SLOW_CLK_UNINIT && !p_ledc_obj[speed_mode]->glb_clk_xpd) {
+        timer_clock_xpd_err = ledc_glb_clk_set_sleep_mode(speed_mode, true);
+    }
+#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
+    else if (p_ledc_obj[speed_mode]->timer_specific_clk[timer_sel] != LEDC_TIMER_SPECIFIC_CLK_UNINIT) {
+        timer_clock_xpd_err = true;
+    }
+#endif
+    if (timer_clock_xpd_err) {
+        p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[timer_sel]--;
+    }
+    return timer_clock_xpd_err;
+}
+
 esp_err_t ledc_bind_channel_timer(ledc_mode_t speed_mode, ledc_channel_t channel, ledc_timer_t timer_sel)
 {
     LEDC_ARG_CHECK(speed_mode < LEDC_SPEED_MODE_MAX, "speed_mode");
     LEDC_ARG_CHECK(timer_sel < LEDC_TIMER_MAX, "timer_select");
     LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
+
+    bool timer_xpd_err = false;
+    ledc_timer_t old_timer_sel;
+    ledc_hal_get_channel_timer(&(p_ledc_obj[speed_mode]->ledc_hal), channel, &old_timer_sel);
+
     portENTER_CRITICAL(&ledc_spinlock);
     ledc_hal_bind_channel_timer(&(p_ledc_obj[speed_mode]->ledc_hal), channel, timer_sel);
     ledc_ls_channel_update(speed_mode, channel);
+
+    if (p_ledc_obj[speed_mode]->channel_keep_alive[channel] && old_timer_sel != timer_sel) {
+        if (p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[old_timer_sel] > 0) {
+            p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[old_timer_sel]--;
+        }
+        // timer clock source should not be powered down during sleep
+        timer_xpd_err = ledc_timer_clk_src_set_xpd_in_sleep(speed_mode, timer_sel);
+    }
     portEXIT_CRITICAL(&ledc_spinlock);
+    if (timer_xpd_err) {
+        ESP_LOGW(LEDC_TAG, "the binded timer can't keep alive in sleep");
+    }
     return ESP_OK;
 }
 
@@ -316,6 +422,24 @@ static bool ledc_speed_mode_ctx_create(ledc_mode_t speed_mode)
 #if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
             memset(ledc_new_mode_obj->timer_specific_clk, LEDC_TIMER_SPECIFIC_CLK_UNINIT, sizeof(ledc_clk_src_t) * LEDC_TIMER_MAX);
 #endif
+
+            ledc_new_mode_obj->sleep_mode = LEDC_SLEEP_MODE_INVALID;
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP // for targets that is !SOC_LEDC_SUPPORT_SLEEP_RETENTION, retention module should still be inited to avoid TOP PD
+            // Initialize sleep retention module for LEDC
+            sleep_retention_module_t module = ledc_reg_retention_info.module_id;
+            sleep_retention_module_init_param_t init_param = {
+                .cbs = {
+                    .create = {
+                        .handle = ledc_create_sleep_retention_link_cb,
+                        .arg = NULL,
+                    },
+                },
+                .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
+            };
+            if (sleep_retention_module_init(module, &init_param) != ESP_OK) {
+                ESP_LOGW(LEDC_TAG, "init sleep retention failed for ledc, power domain may be turned off during sleep");
+            }
+#endif
             p_ledc_obj[speed_mode] = ledc_new_mode_obj;
         }
     }
@@ -530,6 +654,8 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
     ESP_LOGD(LEDC_TAG, "Using clock source %d (in %s mode), divisor: 0x%"PRIx32,
              timer_clk_src, (speed_mode == LEDC_LOW_SPEED_MODE ? "slow" : "fast"), div_param);
 
+    bool timer_clk_xpd_err = false;
+
     /* The following block configures the global clock.
      * Thus, in theory, this only makes sense when configuring the LOW_SPEED timer and the source clock is LEDC_SCLK (as
      * HIGH_SPEED timers won't be clocked by the global clock). However, there are some limitations due to HW design.
@@ -563,16 +689,6 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
         }
         p_ledc_obj[speed_mode]->glb_clk_is_acquired[timer_num] = true;
         if (p_ledc_obj[speed_mode]->glb_clk != glb_clk) {
-#if SOC_LIGHT_SLEEP_SUPPORTED
-            /* keep ESP_PD_DOMAIN_RC_FAST on during light sleep */
-            if (glb_clk == LEDC_SLOW_CLK_RC_FAST) {
-                /* Keep ESP_PD_DOMAIN_RC_FAST on during light sleep */
-                esp_sleep_sub_mode_config(ESP_SLEEP_DIG_USE_RC_FAST_MODE, true);
-            } else if (p_ledc_obj[speed_mode]->glb_clk == LEDC_SLOW_CLK_RC_FAST) {
-                /* No need to keep ESP_PD_DOMAIN_RC_FAST on during light sleep anymore */
-                esp_sleep_sub_mode_config(ESP_SLEEP_DIG_USE_RC_FAST_MODE, false);
-            }
-#endif
             // TODO: release old glb_clk (if not UNINIT), and acquire new glb_clk [clk_tree]
             p_ledc_obj[speed_mode]->glb_clk = glb_clk;
             esp_clk_tree_enable_src((soc_module_clk_t)glb_clk, true);
@@ -581,6 +697,13 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
                 ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk);
             }
         }
+        // acquire power domain for the timer clock source if desired and possible
+        if (p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[timer_num] > 0 && !p_ledc_obj[speed_mode]->glb_clk_xpd) {
+            timer_clk_xpd_err = ledc_glb_clk_set_sleep_mode(speed_mode, true);
+            if (timer_clk_xpd_err) {
+                p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[timer_num] = 0;
+            }
+        }
         portEXIT_CRITICAL(&ledc_spinlock);
 
         ESP_LOGD(LEDC_TAG, "In slow speed mode, global clk set: %d", glb_clk);
@@ -588,6 +711,19 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
 
     /* The divisor is correct, we can write in the hardware. */
     ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src);
+
+    portENTER_CRITICAL(&ledc_spinlock);
+    if (p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[timer_num] > 0 && !p_ledc_obj[speed_mode]->glb_clk_xpd) {
+        // if still get into here, it means the speed mode is high speed mode
+        assert(speed_mode != LEDC_LOW_SPEED_MODE);
+        timer_clk_xpd_err = true;
+        p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[timer_num] = 0;
+    }
+    portEXIT_CRITICAL(&ledc_spinlock);
+    if (timer_clk_xpd_err) {
+        ESP_LOGW(LEDC_TAG, "the timer can't keep alive in sleep");
+    }
+
     return ESP_OK;
 
 error:
@@ -612,6 +748,20 @@ static esp_err_t ledc_timer_del(ledc_mode_t speed_mode, ledc_timer_t timer_sel)
         is_deleted = true;
         p_ledc_obj[speed_mode]->glb_clk_is_acquired[timer_sel] = false;
         // TODO: release timer specific clk and global clk if possible [clk_tree]
+
+        // check if the acquired power domain for the timer clock source can be released
+        if (p_ledc_obj[speed_mode]->glb_clk_xpd) {
+            bool timer_clk_allow_pd = true;
+            for (int i = 0; i < LEDC_TIMER_MAX; i++) {
+                if (p_ledc_obj[speed_mode]->glb_clk_is_acquired[timer_sel] && p_ledc_obj[speed_mode]->timer_xpd_ref_cnt[i] > 0) {
+                    timer_clk_allow_pd = false;
+                    break;
+                }
+            }
+            if (timer_clk_allow_pd) {
+                ledc_glb_clk_set_sleep_mode(speed_mode, false);
+            }
+        }
     }
     portEXIT_CRITICAL(&ledc_spinlock);
     ESP_RETURN_ON_FALSE(is_configured && is_deleted, ESP_ERR_INVALID_STATE, LEDC_TAG, "timer hasn't been configured, or it is still running, please stop it with ledc_timer_pause first");
@@ -687,6 +837,10 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
     LEDC_ARG_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "gpio_num");
     LEDC_ARG_CHECK(timer_select < LEDC_TIMER_MAX, "timer_select");
     LEDC_ARG_CHECK(intr_type < LEDC_INTR_MAX, "intr_type");
+    LEDC_ARG_CHECK(ledc_conf->sleep_mode < LEDC_SLEEP_MODE_INVALID, "sleep_mode");
+#if !SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    ESP_RETURN_ON_FALSE(ledc_conf->sleep_mode != LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD, ESP_ERR_NOT_SUPPORTED, LEDC_TAG, "register back up is not supported");
+#endif
 
     esp_err_t ret = ESP_OK;
 
@@ -732,6 +886,86 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
     /*set LEDC signal in gpio matrix*/
     _ledc_set_pin(gpio_num, output_invert, speed_mode, ledc_channel);
 
+    // apply desired sleep strategy
+    bool slp_mode_conflict = false;
+    bool slp_retention_alloc __attribute__((unused)) = false;
+    bool slp_retention_free __attribute__((unused)) = false;
+    portENTER_CRITICAL(&ledc_spinlock);
+    if (ledc_conf->sleep_mode == LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD) {
+#if LEDC_USE_RETENTION_LINK
+        if (p_ledc_obj[speed_mode]->sleep_mode == LEDC_SLEEP_MODE_NO_ALIVE_NO_PD || p_ledc_obj[speed_mode]->sleep_mode == LEDC_SLEEP_MODE_KEEP_ALIVE) {
+            // conflict sleep strategy with other LEDC channels, power domain cannot be turned off
+            slp_mode_conflict = true;
+        } else {
+            p_ledc_obj[speed_mode]->sleep_mode = LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD;
+            slp_retention_alloc = true;
+        }
+#endif
+    } else if (ledc_conf->sleep_mode == LEDC_SLEEP_MODE_NO_ALIVE_NO_PD) {
+        if (p_ledc_obj[speed_mode]->sleep_mode == LEDC_SLEEP_MODE_INVALID) {
+            p_ledc_obj[speed_mode]->sleep_mode = LEDC_SLEEP_MODE_NO_ALIVE_NO_PD;
+        }
+#if LEDC_USE_RETENTION_LINK
+        else if (p_ledc_obj[speed_mode]->sleep_mode == LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD) {
+            // conflict sleep strategy with other LEDC channels, power domain might still be turned off
+            slp_mode_conflict = true;
+        }
+#endif
+    } else if (ledc_conf->sleep_mode == LEDC_SLEEP_MODE_KEEP_ALIVE) {
+        p_ledc_obj[speed_mode]->channel_keep_alive[ledc_channel] = true;
+#if LEDC_USE_RETENTION_LINK
+        if (p_ledc_obj[speed_mode]->sleep_mode == LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD) {
+            // conflict sleep strategy with other LEDC channels, power domain won't be turned off
+            slp_mode_conflict = true;
+            slp_retention_free = true;
+        }
+#endif
+        p_ledc_obj[speed_mode]->sleep_mode = LEDC_SLEEP_MODE_KEEP_ALIVE;
+    }
+    portEXIT_CRITICAL(&ledc_spinlock);
+    if (slp_mode_conflict) {
+        ESP_LOGW(LEDC_TAG, "conflict sleep strategy with other LEDC channels, power domain may not be on/off as desired in sleep");
+    }
+#if LEDC_USE_RETENTION_LINK
+    if (slp_retention_alloc) {
+        if (sleep_retention_module_allocate(ledc_reg_retention_info.module_id) != ESP_OK) {
+            ESP_LOGW(LEDC_TAG, "create retention module failed, power domain can't turn off");
+        }
+    }
+    if (slp_retention_free) {
+        sleep_retention_module_free(ledc_reg_retention_info.module_id);
+    }
+#endif
+
+    if (ledc_conf->sleep_mode == LEDC_SLEEP_MODE_KEEP_ALIVE) {
+        // 1. timer clock source should not be powered down during sleep
+        bool timer_xpd_err = false;
+        portENTER_CRITICAL(&ledc_spinlock);
+        timer_xpd_err = ledc_timer_clk_src_set_xpd_in_sleep(speed_mode, timer_select);
+        portEXIT_CRITICAL(&ledc_spinlock);
+        if (timer_xpd_err) {
+            ESP_LOGW(LEDC_TAG, "the binded timer can't keep alive in sleep");
+        }
+
+        // 2. keep IO output during sleep
+        gpio_sleep_sel_dis(gpio_num);
+#if CONFIG_IDF_TARGET_ESP32P4
+        // To workaround DIG-399, all LP IOs are held when LP_PERIPH is powered off to ensure EXT wakeup functionality
+        // But holding LP IOs will cause LEDC signal cannot output on the pad during sleep
+        // Therefore, we will force LP periph xpd in such case
+        if ((1ULL << gpio_num) & SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK) {
+            esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+        }
+#endif
+
+        // 3. keep related module integrated clock gating on during sleep
+// TODO: use proper icg API IDF-7595
+#if SOC_PMU_SUPPORTED && !CONFIG_IDF_TARGET_ESP32P4 // P4 does not have peripheral icg
+        uint32_t val = PMU.hp_sys[PMU_MODE_HP_SLEEP].icg_func;
+        PMU.hp_sys[PMU_MODE_HP_SLEEP].icg_func = (val | BIT(PMU_ICG_FUNC_ENA_LEDC) | BIT(PMU_ICG_FUNC_ENA_IOMUX));
+#endif
+    }
+
     return ret;
 }
 
diff --git a/components/esp_driver_ledc/test_apps/ledc/main/CMakeLists.txt b/components/esp_driver_ledc/test_apps/ledc/main/CMakeLists.txt
index 63794907bf1..8aeea8c40d0 100644
--- a/components/esp_driver_ledc/test_apps/ledc/main/CMakeLists.txt
+++ b/components/esp_driver_ledc/test_apps/ledc/main/CMakeLists.txt
@@ -1,5 +1,10 @@
 set(srcs "test_app_main.c"
-         "test_ledc.c")
+         "test_ledc.c"
+         "test_ledc_utils.c")
+
+if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED)
+    list(APPEND srcs "test_ledc_sleep.c")
+endif()
 
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
diff --git a/components/esp_driver_ledc/test_apps/ledc/main/idf_component.yml b/components/esp_driver_ledc/test_apps/ledc/main/idf_component.yml
new file mode 100644
index 00000000000..f5001494e21
--- /dev/null
+++ b/components/esp_driver_ledc/test_apps/ledc/main/idf_component.yml
@@ -0,0 +1,3 @@
+dependencies:
+  test_utils:
+    path: ${IDF_PATH}/tools/unit-test-app/components/test_utils
diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_app_main.c b/components/esp_driver_ledc/test_apps/ledc/main/test_app_main.c
index 5beebdc5157..dabba32336a 100644
--- a/components/esp_driver_ledc/test_apps/ledc/main/test_app_main.c
+++ b/components/esp_driver_ledc/test_apps/ledc/main/test_app_main.c
@@ -9,7 +9,8 @@
 #include "esp_heap_caps.h"
 
 // Some resources are lazy allocated in LEDC driver, the threshold is left for that case
-#define TEST_MEMORY_LEAK_THRESHOLD (400)
+// This leak is large since LEDC driver does not provide channel delete mechanism
+#define TEST_MEMORY_LEAK_THRESHOLD (500)
 
 void setUp(void)
 {
diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c
index df27ae3e19d..fb180423eed 100644
--- a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c
+++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c
@@ -22,54 +22,7 @@
 #include "driver/ledc.h"
 #include "soc/ledc_struct.h"
 #include "esp_clk_tree.h"
-
-#define PULSE_IO      5
-
-#define TEST_PWM_FREQ 2000
-
-#if SOC_LEDC_SUPPORT_HS_MODE
-#define TEST_SPEED_MODE LEDC_HIGH_SPEED_MODE
-#define SPEED_MODE_LIST {LEDC_HIGH_SPEED_MODE, LEDC_LOW_SPEED_MODE}
-#else
-#define TEST_SPEED_MODE LEDC_LOW_SPEED_MODE
-#define SPEED_MODE_LIST {LEDC_LOW_SPEED_MODE}
-#endif
-
-#if SOC_LEDC_SUPPORT_APB_CLOCK
-#define TEST_DEFAULT_CLK_CFG LEDC_USE_APB_CLK
-#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
-#if SOC_CLK_TREE_SUPPORTED
-#define TEST_DEFAULT_CLK_CFG LEDC_USE_PLL_DIV_CLK
-#else
-#define TEST_DEFAULT_CLK_CFG LEDC_USE_XTAL_CLK
-#endif
-#endif
-
-static ledc_channel_config_t initialize_channel_config(void)
-{
-    ledc_channel_config_t config;
-    memset(&config, 0, sizeof(ledc_channel_config_t));
-    config.gpio_num = PULSE_IO;
-    config.speed_mode = TEST_SPEED_MODE;
-    config.channel  = LEDC_CHANNEL_0;
-    config.intr_type = LEDC_INTR_DISABLE;
-    config.timer_sel = LEDC_TIMER_0;
-    config.duty = 4000;
-    config.hpoint = 0;
-    return config;
-}
-
-static ledc_timer_config_t create_default_timer_config(void)
-{
-    ledc_timer_config_t ledc_time_config;
-    memset(&ledc_time_config, 0, sizeof(ledc_timer_config_t));
-    ledc_time_config.speed_mode = TEST_SPEED_MODE;
-    ledc_time_config.duty_resolution = LEDC_TIMER_13_BIT;
-    ledc_time_config.timer_num = LEDC_TIMER_0;
-    ledc_time_config.freq_hz = TEST_PWM_FREQ;
-    ledc_time_config.clk_cfg = TEST_DEFAULT_CLK_CFG;
-    return ledc_time_config;
-}
+#include "test_ledc_utils.h"
 
 static void fade_setup(void)
 {
@@ -474,52 +427,6 @@ TEST_CASE("LEDC multi fade test", "[ledc]")
 
 #if SOC_PCNT_SUPPORTED // Note. C61, C3, C2 do not have PCNT peripheral, the following test cases cannot be tested
 
-#include "driver/pulse_cnt.h"
-
-#define HIGHEST_LIMIT 10000
-#define LOWEST_LIMIT -10000
-
-static pcnt_unit_handle_t pcnt_unit;
-static pcnt_channel_handle_t pcnt_chan;
-
-static void setup_testbench(void)
-{
-    pcnt_unit_config_t unit_config = {
-        .high_limit = HIGHEST_LIMIT,
-        .low_limit = LOWEST_LIMIT,
-    };
-    TEST_ESP_OK(pcnt_new_unit(&unit_config, &pcnt_unit));
-    pcnt_chan_config_t chan_config = {
-        .edge_gpio_num = PULSE_IO,
-        .level_gpio_num = -1,
-    };
-    TEST_ESP_OK(pcnt_new_channel(pcnt_unit, &chan_config, &pcnt_chan));
-    TEST_ESP_OK(pcnt_channel_set_level_action(pcnt_chan, PCNT_CHANNEL_LEVEL_ACTION_KEEP, PCNT_CHANNEL_LEVEL_ACTION_KEEP));
-    TEST_ESP_OK(pcnt_channel_set_edge_action(pcnt_chan, PCNT_CHANNEL_EDGE_ACTION_INCREASE, PCNT_CHANNEL_EDGE_ACTION_HOLD));
-    TEST_ESP_OK(pcnt_unit_enable(pcnt_unit));
-}
-
-static void tear_testbench(void)
-{
-    TEST_ESP_OK(pcnt_unit_disable(pcnt_unit));
-    TEST_ESP_OK(pcnt_del_channel(pcnt_chan));
-    TEST_ESP_OK(pcnt_del_unit(pcnt_unit));
-}
-
-// use PCNT to test the waveform of LEDC
-static int wave_count(int last_time)
-{
-    // The input ability of PULSE_IO is disabled after ledc driver install, so we need to re-enable it again
-    gpio_ll_input_enable(&GPIO, PULSE_IO);
-    int test_counter = 0;
-    TEST_ESP_OK(pcnt_unit_clear_count(pcnt_unit));
-    TEST_ESP_OK(pcnt_unit_start(pcnt_unit));
-    vTaskDelay(pdMS_TO_TICKS(last_time));
-    TEST_ESP_OK(pcnt_unit_stop(pcnt_unit));
-    TEST_ESP_OK(pcnt_unit_get_count(pcnt_unit, &test_counter));
-    return test_counter;
-}
-
 // the PCNT will count the frequency of it
 static void frequency_set_get(ledc_mode_t speed_mode, ledc_timer_t timer, uint32_t desired_freq, int16_t theoretical_freq, int16_t error)
 {
@@ -731,8 +638,6 @@ static void ledc_cpu_reset_test_second_stage(void)
     int count;
     TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
     setup_testbench();
-    // reconfigure the GPIO again, as the GPIO output ability has been disabled during initialize pcnt peripheral
-    ledc_set_pin(PULSE_IO, TEST_SPEED_MODE, LEDC_CHANNEL_0);
     count = wave_count(1000);
     TEST_ASSERT_UINT32_WITHIN(5, TEST_PWM_FREQ, count);
     tear_testbench();
diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.c b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.c
new file mode 100644
index 00000000000..c3c57a4e032
--- /dev/null
+++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.c
@@ -0,0 +1,159 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "test_utils.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "driver/ledc.h"
+#include "test_ledc_utils.h"
+#include "esp_sleep.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/esp_pmu.h"
+#include "soc/ledc_periph.h"
+#include "esp_private/sleep_retention.h"
+#include "esp_rom_uart.h"
+
+// Note. Test cases in this file cannot run one after another without reset
+
+/**
+ * @brief Test LEDC can still output PWM signal after light sleep
+ *
+ * @param allow_pd Whether to allow powering down the peripheral in light sleep
+ */
+static void test_ledc_sleep_retention(bool allow_pd)
+{
+    int pulse_count __attribute__((unused)) = 0;
+
+    ledc_timer_config_t ledc_time_config = create_default_timer_config();
+    TEST_ESP_OK(ledc_timer_config(&ledc_time_config));
+
+    ledc_channel_config_t ledc_ch_config = initialize_channel_config();
+    ledc_ch_config.sleep_mode = (allow_pd ? LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD : LEDC_SLEEP_MODE_NO_ALIVE_NO_PD);
+    TEST_ESP_OK(ledc_channel_config(&ledc_ch_config));
+
+    vTaskDelay(50 / portTICK_PERIOD_MS);
+
+#if SOC_PCNT_SUPPORTED
+    setup_testbench();
+    pulse_count = wave_count(1000);
+    TEST_ASSERT_UINT32_WITHIN(5, TEST_PWM_FREQ, pulse_count);
+    tear_testbench(); // tear down so that PCNT won't affect TOP PD
+#endif
+
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
+
+    printf("Go to light sleep for 2 seconds\n");
+    TEST_ESP_OK(esp_light_sleep_start());
+    printf("Waked up! Let's see if LEDC peripheral can still work...\n");
+
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+
+    printf("Check if the sleep happened as expected\r\n");
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_PMU_SUPPORTED
+    // check if the TOP power domain on/off as desired
+    TEST_ASSERT_EQUAL(allow_pd ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+    esp_sleep_set_sleep_context(NULL);
+
+    if (allow_pd) {
+        // check if the RO duty_r register field get synced back
+        TEST_ASSERT_EQUAL(4000, ledc_get_duty(TEST_SPEED_MODE, LEDC_CHANNEL_0));
+    }
+
+#if SOC_PCNT_SUPPORTED
+    setup_testbench();
+    pulse_count = wave_count(1000);
+    TEST_ASSERT_UINT32_WITHIN(5, TEST_PWM_FREQ, pulse_count);
+    tear_testbench();
+#endif
+}
+
+TEST_CASE("ledc can output after light sleep (LEDC power domain xpd)", "[ledc]")
+{
+    test_ledc_sleep_retention(false);
+}
+
+#if SOC_LEDC_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+TEST_CASE("ledc can output after light sleep (LEDC power domain pd)", "[ledc]")
+{
+    // test retention feature
+    test_ledc_sleep_retention(true);
+
+    // ledc driver does not have channel release, we will do retention release here to avoid memory leak
+    sleep_retention_module_t module = ledc_reg_retention_info.module_id;
+    sleep_retention_module_free(module);
+    sleep_retention_module_deinit(module);
+}
+#endif
+
+#if SOC_PCNT_SUPPORTED
+static const ledc_clk_src_t test_ledc_clk_in_slp[] = {
+    LEDC_USE_RC_FAST_CLK,
+#if SOC_LEDC_SUPPORT_XTAL_CLOCK
+    LEDC_USE_XTAL_CLK,
+#endif
+};
+
+static const int test_clks_num = sizeof(test_ledc_clk_in_slp) / sizeof(test_ledc_clk_in_slp[0]);
+
+static void ledc_output_monitor(void)
+{
+    setup_testbench();
+
+    for (int i = 0; i < test_clks_num; i++) {
+        unity_wait_for_signal("Go to light sleep for 3 seconds");
+        vTaskDelay(500 / portTICK_PERIOD_MS);
+        int pulse_count = wave_count(1000);
+        uint32_t acceptable_delta = (test_ledc_clk_in_slp[i] == (ledc_clk_src_t)LEDC_USE_RC_FAST_CLK) ? 20 : 5; // RC_FAST as the clk src has a bigger error range is reasonable
+        TEST_ASSERT_UINT32_WITHIN(acceptable_delta, TEST_PWM_LOW_FREQ, pulse_count);
+        unity_wait_for_signal("Waked up!");
+    }
+
+    tear_testbench();
+}
+
+static void ledc_output_in_sleep(void)
+{
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(3 * 1000 * 1000));
+
+    ledc_channel_config_t ledc_ch_config = initialize_channel_config();
+    ledc_ch_config.speed_mode = LEDC_LOW_SPEED_MODE;
+    ledc_ch_config.sleep_mode = LEDC_SLEEP_MODE_KEEP_ALIVE;
+    TEST_ESP_OK(ledc_channel_config(&ledc_ch_config));
+
+    for (int i = 0; i < test_clks_num; i++) {
+        ledc_timer_config_t ledc_time_config = create_default_timer_config();
+        ledc_time_config.speed_mode = LEDC_LOW_SPEED_MODE;
+        ledc_time_config.clk_cfg = test_ledc_clk_in_slp[i];
+        ledc_time_config.freq_hz = TEST_PWM_LOW_FREQ;
+        TEST_ESP_OK(ledc_timer_config(&ledc_time_config));
+
+        TEST_ESP_OK(ledc_update_duty(ledc_ch_config.speed_mode, ledc_ch_config.channel));
+
+        unity_send_signal("Go to light sleep for 3 seconds");
+        esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM); // wait until the signal sent
+        TEST_ESP_OK(esp_light_sleep_start());
+        unity_send_signal("Waked up!");
+
+        TEST_ESP_OK(ledc_timer_pause(ledc_time_config.speed_mode, ledc_time_config.timer_num));
+        ledc_time_config.deconfigure = 1;
+        TEST_ESP_OK(ledc_timer_config(&ledc_time_config));
+    }
+}
+
+TEST_CASE_MULTIPLE_DEVICES("ledc can output during light sleep", "[ledc][test_env=generic_multi_device]", ledc_output_in_sleep, ledc_output_monitor);
+#endif // SOC_PCNT_SUPPORTED
diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.c b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.c
new file mode 100644
index 00000000000..5fce63fddd5
--- /dev/null
+++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.c
@@ -0,0 +1,84 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include "unity.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "test_ledc_utils.h"
+#include "soc/soc_caps.h"
+
+ledc_channel_config_t initialize_channel_config(void)
+{
+    ledc_channel_config_t config;
+    memset(&config, 0, sizeof(ledc_channel_config_t));
+    config.gpio_num = PULSE_IO;
+    config.speed_mode = TEST_SPEED_MODE;
+    config.channel  = LEDC_CHANNEL_0;
+    config.intr_type = LEDC_INTR_DISABLE;
+    config.timer_sel = LEDC_TIMER_0;
+    config.duty = 4000;
+    config.hpoint = 0;
+    return config;
+}
+
+ledc_timer_config_t create_default_timer_config(void)
+{
+    ledc_timer_config_t ledc_time_config;
+    memset(&ledc_time_config, 0, sizeof(ledc_timer_config_t));
+    ledc_time_config.speed_mode = TEST_SPEED_MODE;
+    ledc_time_config.duty_resolution = LEDC_TIMER_13_BIT;
+    ledc_time_config.timer_num = LEDC_TIMER_0;
+    ledc_time_config.freq_hz = TEST_PWM_FREQ;
+    ledc_time_config.clk_cfg = TEST_DEFAULT_CLK_CFG;
+    return ledc_time_config;
+}
+
+// use PCNT to test the waveform of LEDC
+#if SOC_PCNT_SUPPORTED
+#include "driver/pulse_cnt.h"
+
+#define HIGHEST_LIMIT 10000
+#define LOWEST_LIMIT -10000
+
+static pcnt_unit_handle_t pcnt_unit;
+static pcnt_channel_handle_t pcnt_chan;
+
+void setup_testbench(void)
+{
+    pcnt_unit_config_t unit_config = {
+        .high_limit = HIGHEST_LIMIT,
+        .low_limit = LOWEST_LIMIT,
+    };
+    TEST_ESP_OK(pcnt_new_unit(&unit_config, &pcnt_unit));
+    pcnt_chan_config_t chan_config = {
+        .edge_gpio_num = PULSE_IO,
+        .level_gpio_num = -1,
+    };
+    TEST_ESP_OK(pcnt_new_channel(pcnt_unit, &chan_config, &pcnt_chan));
+    TEST_ESP_OK(pcnt_channel_set_level_action(pcnt_chan, PCNT_CHANNEL_LEVEL_ACTION_KEEP, PCNT_CHANNEL_LEVEL_ACTION_KEEP));
+    TEST_ESP_OK(pcnt_channel_set_edge_action(pcnt_chan, PCNT_CHANNEL_EDGE_ACTION_INCREASE, PCNT_CHANNEL_EDGE_ACTION_HOLD));
+    TEST_ESP_OK(pcnt_unit_enable(pcnt_unit));
+}
+
+void tear_testbench(void)
+{
+    TEST_ESP_OK(pcnt_unit_disable(pcnt_unit));
+    TEST_ESP_OK(pcnt_del_channel(pcnt_chan));
+    TEST_ESP_OK(pcnt_del_unit(pcnt_unit));
+}
+
+int wave_count(int last_time)
+{
+    int test_counter = 0;
+    TEST_ESP_OK(pcnt_unit_clear_count(pcnt_unit));
+    TEST_ESP_OK(pcnt_unit_start(pcnt_unit));
+    vTaskDelay(pdMS_TO_TICKS(last_time));
+    TEST_ESP_OK(pcnt_unit_stop(pcnt_unit));
+    TEST_ESP_OK(pcnt_unit_get_count(pcnt_unit, &test_counter));
+    return test_counter;
+}
+#endif
diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.h b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.h
new file mode 100644
index 00000000000..d3c3c7e6436
--- /dev/null
+++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc_utils.h
@@ -0,0 +1,61 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include "soc/soc_caps.h"
+#include "driver/ledc.h"
+
+#define PULSE_IO      5
+
+#define TEST_PWM_FREQ       2000
+#define TEST_PWM_LOW_FREQ   200
+
+#if SOC_LEDC_SUPPORT_HS_MODE
+#define TEST_SPEED_MODE LEDC_HIGH_SPEED_MODE
+#define SPEED_MODE_LIST {LEDC_HIGH_SPEED_MODE, LEDC_LOW_SPEED_MODE}
+#else
+#define TEST_SPEED_MODE LEDC_LOW_SPEED_MODE
+#define SPEED_MODE_LIST {LEDC_LOW_SPEED_MODE}
+#endif
+
+#if SOC_LEDC_SUPPORT_APB_CLOCK
+#define TEST_DEFAULT_CLK_CFG LEDC_USE_APB_CLK
+#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
+#if SOC_CLK_TREE_SUPPORTED
+#define TEST_DEFAULT_CLK_CFG LEDC_USE_PLL_DIV_CLK
+#else
+#define TEST_DEFAULT_CLK_CFG LEDC_USE_XTAL_CLK
+#endif
+#endif
+
+/**
+ * Initialize a LEDC channel config structure
+ */
+ledc_channel_config_t initialize_channel_config(void);
+
+/**
+ * Initialize a LEDC timer config structure
+ */
+ledc_timer_config_t create_default_timer_config(void);
+
+#if SOC_PCNT_SUPPORTED
+/**
+ * Setup PCNT test bench
+ */
+void setup_testbench(void);
+
+/**
+ * Tear down PCNT test bench
+ */
+void tear_testbench(void);
+
+/**
+ * Use PCNT to count pulse
+ *
+ * @param last_time Duration time in ms
+ * @return Pulse count
+ */
+int wave_count(int last_time);
+#endif
diff --git a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py
index 0b7ae925e90..22687a67fc9 100644
--- a/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py
+++ b/components/esp_driver_ledc/test_apps/ledc/pytest_ledc.py
@@ -32,3 +32,19 @@ def test_ledc(dut: IdfDut) -> None:
 )
 def test_ledc_psram(dut: IdfDut) -> None:
     dut.run_all_single_board_cases(reset=True)
+
+
+@pytest.mark.supported_targets
+@pytest.mark.temp_skip_ci(targets=['esp32s3', 'esp32c61'],
+                          reason='s3 multi device runner has no psram, c61 lack of runner IDF-10949')
+@pytest.mark.generic_multi_device
+@pytest.mark.parametrize(
+    'count, config',
+    [
+        (2, 'iram_safe',),
+        (2, 'release',),
+    ],
+    indirect=True
+)
+def test_ledc_multi_device(case_tester) -> None:        # type: ignore
+    case_tester.run_all_multi_dev_cases(reset=True)
diff --git a/components/esp_driver_ledc/test_apps/ledc/sdkconfig.ci.release b/components/esp_driver_ledc/test_apps/ledc/sdkconfig.ci.release
index 91d93f163e6..17aaee1e8ec 100644
--- a/components/esp_driver_ledc/test_apps/ledc/sdkconfig.ci.release
+++ b/components/esp_driver_ledc/test_apps/ledc/sdkconfig.ci.release
@@ -1,5 +1,6 @@
 CONFIG_PM_ENABLE=y
 CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
 CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
diff --git a/components/esp_driver_ledc/test_apps/ledc/sdkconfig.defaults b/components/esp_driver_ledc/test_apps/ledc/sdkconfig.defaults
index 568a2ae79fc..cbdb4160e28 100644
--- a/components/esp_driver_ledc/test_apps/ledc/sdkconfig.defaults
+++ b/components/esp_driver_ledc/test_apps/ledc/sdkconfig.defaults
@@ -2,3 +2,5 @@ CONFIG_FREERTOS_HZ=1000
 CONFIG_ESP_TASK_WDT_INIT=n
 # Disable memory protection, because "LEDC continue work after software reset" test case requires a cpu reset
 CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n
+# primitives for checking sleep internal state
+CONFIG_ESP_SLEEP_DEBUG=y
diff --git a/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h b/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h
index 6e280860876..a56d903bc37 100644
--- a/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h
+++ b/components/esp_driver_mcpwm/include/driver/mcpwm_cap.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,6 +22,11 @@ typedef struct {
     int group_id;                         /*!< Specify from which group to allocate the capture timer */
     mcpwm_capture_clock_source_t clk_src; /*!< MCPWM capture timer clock source */
     uint32_t resolution_hz;               /*!< Resolution of capture timer */
+    struct {
+        uint32_t allow_pd: 1;       /*!< Set to allow power down. When this flag set, the driver will backup/restore the MCPWM registers before/after entering/exist sleep mode.
+                                      By this approach, the system can power off MCPWM's power domain.
+                                      This can save power, but at the expense of more RAM being consumed.*/
+    } flags;                        /*!< Extra configuration flags for timer */
 } mcpwm_capture_timer_config_t;
 
 /**
@@ -145,8 +150,7 @@ typedef struct {
         uint32_t pull_down: 1;         /*!< Whether to pull down internally */
         uint32_t invert_cap_signal: 1; /*!< Invert the input capture signal */
         uint32_t io_loop_back: 1;      /*!< For debug/test, the signal output from the GPIO will be fed to the input path as well */
-        uint32_t keep_io_conf_at_exit: 1; /*!< For debug/test, whether to keep the GPIO configuration when capture channel is deleted.
-                                            By default, driver will reset the GPIO pin at exit. */
+        uint32_t keep_io_conf_at_exit: 1 __attribute__((deprecated)); /*!< Deprecated. Driver won't change the GPIO configuration in deinilization. */
     } flags;                           /*!< Extra configuration flags for capture channel */
 } mcpwm_capture_channel_config_t;
 
diff --git a/components/esp_driver_mcpwm/include/driver/mcpwm_timer.h b/components/esp_driver_mcpwm/include/driver/mcpwm_timer.h
index dcf6b96e835..69a8b7a3b66 100644
--- a/components/esp_driver_mcpwm/include/driver/mcpwm_timer.h
+++ b/components/esp_driver_mcpwm/include/driver/mcpwm_timer.h
@@ -40,6 +40,9 @@ typedef struct {
     struct {
         uint32_t update_period_on_empty: 1; /*!< Whether to update period when timer counts to zero */
         uint32_t update_period_on_sync: 1;  /*!< Whether to update period on sync event */
+        uint32_t allow_pd: 1;               /*!< Set to allow power down. When this flag set, the driver will backup/restore the MCPWM registers before/after entering/exist sleep mode.
+                                              By this approach, the system can power off MCPWM's power domain.
+                                              This can save power, but at the expense of more RAM being consumed. */
     } flags;                                /*!< Extra configuration flags for timer */
 } mcpwm_timer_config_t;
 
diff --git a/components/esp_driver_mcpwm/src/mcpwm_cap.c b/components/esp_driver_mcpwm/src/mcpwm_cap.c
index 0baf6b090cb..7d68cf74fc2 100644
--- a/components/esp_driver_mcpwm/src/mcpwm_cap.c
+++ b/components/esp_driver_mcpwm/src/mcpwm_cap.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,9 +24,11 @@
 #include "soc/soc_caps.h"
 #include "soc/mcpwm_periph.h"
 #include "hal/mcpwm_ll.h"
+#include "hal/gpio_hal.h"
 #include "driver/mcpwm_cap.h"
 #include "driver/gpio.h"
 #include "mcpwm_private.h"
+#include "esp_private/gpio.h"
 
 static const char *TAG = "mcpwm";
 
@@ -92,6 +94,10 @@ esp_err_t mcpwm_new_capture_timer(const mcpwm_capture_timer_config_t *config, mc
     ESP_GOTO_ON_FALSE(config->group_id < SOC_MCPWM_GROUPS && config->group_id >= 0, ESP_ERR_INVALID_ARG,
                       err, TAG, "invalid group ID:%d", config->group_id);
 
+#if !SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "register back up is not supported");
+#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+
     cap_timer = heap_caps_calloc(1, sizeof(mcpwm_cap_timer_t), MCPWM_MEM_ALLOC_CAPS);
     ESP_GOTO_ON_FALSE(cap_timer, ESP_ERR_NO_MEM, err, TAG, "no mem for capture timer");
 
@@ -137,6 +143,13 @@ esp_err_t mcpwm_new_capture_timer(const mcpwm_capture_timer_config_t *config, mc
     cap_timer->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
     cap_timer->fsm = MCPWM_CAP_TIMER_FSM_INIT;
     *ret_cap_timer = cap_timer;
+
+#if MCPWM_USE_RETENTION_LINK
+    if (config->flags.allow_pd != 0) {
+        mcpwm_create_retention_module(group);
+    }
+#endif // MCPWM_USE_RETENTION_LINK
+
     ESP_LOGD(TAG, "new capture timer at %p, in group (%d), resolution %"PRIu32, cap_timer, group_id, cap_timer->resolution_hz);
     return ESP_OK;
 
@@ -289,20 +302,25 @@ esp_err_t mcpwm_new_capture_channel(mcpwm_cap_timer_handle_t cap_timer, const mc
 
     if (config->gpio_num >= 0) {
         // GPIO configuration
-        gpio_config_t gpio_conf = {
-            .intr_type = GPIO_INTR_DISABLE,
-            .mode = GPIO_MODE_INPUT | (config->flags.io_loop_back ? GPIO_MODE_OUTPUT : 0), // also enable the output path if `io_loop_back` is enabled
-            .pin_bit_mask = (1ULL << config->gpio_num),
-            .pull_down_en = config->flags.pull_down,
-            .pull_up_en = config->flags.pull_up,
-        };
-        ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config capture GPIO failed");
+        gpio_func_sel(config->gpio_num, PIN_FUNC_GPIO);
+        gpio_input_enable(config->gpio_num);
         esp_rom_gpio_connect_in_signal(config->gpio_num, mcpwm_periph_signals.groups[group->group_id].captures[cap_chan_id].cap_sig, 0);
+        if (config->flags.pull_down) {
+            gpio_pulldown_en(config->gpio_num);
+        }
+        if (config->flags.pull_up) {
+            gpio_pullup_en(config->gpio_num);
+        }
+
+        // deprecated, to be removed in in esp-idf v6.0
+        if (config->flags.io_loop_back) {
+            gpio_ll_output_enable(&GPIO, config->gpio_num);
+        }
     }
 
     cap_chan->gpio_num = config->gpio_num;
     cap_chan->fsm = MCPWM_CAP_CHAN_FSM_INIT;
-    cap_chan->flags.reset_io_at_exit = !config->flags.keep_io_conf_at_exit && config->gpio_num >= 0;
+
     *ret_cap_channel = cap_chan;
     ESP_LOGD(TAG, "new capture channel (%d,%d) at %p", group->group_id, cap_chan_id, cap_chan);
     return ESP_OK;
@@ -323,15 +341,16 @@ esp_err_t mcpwm_del_capture_channel(mcpwm_cap_channel_handle_t cap_channel)
     int cap_chan_id = cap_channel->cap_chan_id;
 
     ESP_LOGD(TAG, "del capture channel (%d,%d)", group->group_id, cap_channel->cap_chan_id);
-    if (cap_channel->flags.reset_io_at_exit) {
-        gpio_reset_pin(cap_channel->gpio_num);
-    }
 
     portENTER_CRITICAL(&group->spinlock);
     mcpwm_ll_intr_enable(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_chan_id), false);
     mcpwm_ll_intr_clear_status(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_chan_id));
     portEXIT_CRITICAL(&group->spinlock);
 
+    // disconnect signal from the GPIO pin
+    esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT,
+                                   mcpwm_periph_signals.groups[group->group_id].captures[cap_chan_id].cap_sig, 0);
+
     // recycle memory resource
     ESP_RETURN_ON_ERROR(mcpwm_capture_channel_destroy(cap_channel), TAG, "destroy capture channel failed");
     return ESP_OK;
diff --git a/components/esp_driver_mcpwm/src/mcpwm_com.c b/components/esp_driver_mcpwm/src/mcpwm_com.c
index a3bdd38269c..ae57a8510a4 100644
--- a/components/esp_driver_mcpwm/src/mcpwm_com.c
+++ b/components/esp_driver_mcpwm/src/mcpwm_com.c
@@ -21,6 +21,7 @@
 #include "soc/soc_caps.h"
 #include "hal/mcpwm_ll.h"
 #include "mcpwm_private.h"
+#include "esp_private/rtc_clk.h"
 
 #if SOC_PERIPH_CLK_CTRL_SHARED
 #define MCPWM_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
@@ -34,6 +35,10 @@
 #define MCPWM_RCC_ATOMIC()
 #endif
 
+#if MCPWM_USE_RETENTION_LINK
+static esp_err_t mcpwm_create_sleep_retention_link_cb(void *arg);
+#endif
+
 static const char *TAG = "mcpwm";
 
 typedef struct {
@@ -59,6 +64,23 @@ mcpwm_group_t *mcpwm_acquire_group_handle(int group_id)
             group->group_id = group_id;
             group->intr_priority = -1;
             group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
+#if MCPWM_USE_RETENTION_LINK
+            sleep_retention_module_t module = mcpwm_reg_retention_info[group_id].retention_module;
+            sleep_retention_module_init_param_t init_param = {
+                .cbs = {
+                    .create = {
+                        .handle = mcpwm_create_sleep_retention_link_cb,
+                        .arg = group,
+                    },
+                },
+                .depends = SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM
+            };
+            // we only do retention init here. Allocate retention module in the unit initialization
+            if (sleep_retention_module_init(module, &init_param) != ESP_OK) {
+                // even though the sleep retention module init failed, MCPWM driver should still work, so just warning here
+                ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id);
+            }
+#endif // MCPWM_USE_RETENTION_LINK
             // enable APB to access MCPWM registers
             MCPWM_RCC_ATOMIC() {
                 mcpwm_ll_enable_bus_clock(group_id, true);
@@ -116,6 +138,15 @@ void mcpwm_release_group_handle(mcpwm_group_t *group)
         if (group->pm_lock) {
             esp_pm_lock_delete(group->pm_lock);
         }
+#if MCPWM_USE_RETENTION_LINK
+        const periph_retention_module_t module_id = mcpwm_reg_retention_info[group_id].retention_module;
+        if (sleep_retention_get_created_modules() & BIT(module_id)) {
+            sleep_retention_module_free(module_id);
+        }
+        if (sleep_retention_get_inited_modules() & BIT(module_id)) {
+            sleep_retention_module_deinit(module_id);
+        }
+#endif // MCPWM_USE_RETENTION_LINK
         free(group);
     }
     _lock_release(&s_platform.mutex);
@@ -257,3 +288,29 @@ esp_err_t mcpwm_set_prescale(mcpwm_group_t *group, uint32_t expect_module_resolu
 
     return ESP_OK;
 }
+
+#if MCPWM_USE_RETENTION_LINK
+static esp_err_t mcpwm_create_sleep_retention_link_cb(void *arg)
+{
+    mcpwm_group_t *group = (mcpwm_group_t *)arg;
+    int group_id = group->group_id;
+    sleep_retention_module_t module_id = mcpwm_reg_retention_info[group_id].retention_module;
+    esp_err_t err = sleep_retention_entries_create(mcpwm_reg_retention_info[group_id].regdma_entry_array,
+                                                   mcpwm_reg_retention_info[group_id].array_size,
+                                                   REGDMA_LINK_PRI_MCPWM, module_id);
+    return err;
+}
+void mcpwm_create_retention_module(mcpwm_group_t *group)
+{
+    int group_id = group->group_id;
+    sleep_retention_module_t module_id = mcpwm_reg_retention_info[group_id].retention_module;
+    _lock_acquire(&s_platform.mutex);
+    if ((sleep_retention_get_inited_modules() & BIT(module_id)) && !(sleep_retention_get_created_modules() & BIT(module_id))) {
+        if (sleep_retention_module_allocate(module_id) != ESP_OK) {
+            // even though the sleep retention module create failed, MCPWM driver should still work, so just warning here
+            ESP_LOGW(TAG, "create retention module failed, power domain can't turn off");
+        }
+    }
+    _lock_release(&s_platform.mutex);
+}
+#endif // MCPWM_USE_RETENTION_LINK
diff --git a/components/esp_driver_mcpwm/src/mcpwm_fault.c b/components/esp_driver_mcpwm/src/mcpwm_fault.c
index b2539e2048f..d1ccde6912d 100644
--- a/components/esp_driver_mcpwm/src/mcpwm_fault.c
+++ b/components/esp_driver_mcpwm/src/mcpwm_fault.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,9 +22,11 @@
 #include "soc/soc_caps.h"
 #include "soc/mcpwm_periph.h"
 #include "hal/mcpwm_ll.h"
+#include "hal/gpio_hal.h"
 #include "driver/mcpwm_fault.h"
 #include "driver/gpio.h"
 #include "mcpwm_private.h"
+#include "esp_private/gpio.h"
 
 static const char *TAG = "mcpwm";
 
@@ -112,16 +114,22 @@ esp_err_t mcpwm_new_gpio_fault(const mcpwm_gpio_fault_config_t *config, mcpwm_fa
     ESP_GOTO_ON_ERROR(mcpwm_check_intr_priority(group, config->intr_priority), err, TAG, "set group interrupt priority failed");
 
     // GPIO configuration
-    gpio_config_t gpio_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        .mode = GPIO_MODE_INPUT | (config->flags.io_loop_back ? GPIO_MODE_OUTPUT : 0), // also enable the output path if `io_loop_back` is enabled
-        .pin_bit_mask = (1ULL << config->gpio_num),
-        .pull_down_en = config->flags.pull_down,
-        .pull_up_en = config->flags.pull_up,
-    };
-    ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config fault GPIO failed");
+    gpio_func_sel(config->gpio_num, PIN_FUNC_GPIO);
+    gpio_input_enable(config->gpio_num);
     esp_rom_gpio_connect_in_signal(config->gpio_num, mcpwm_periph_signals.groups[group_id].gpio_faults[fault_id].fault_sig, 0);
 
+    if (config->flags.pull_down) {
+        gpio_pulldown_en(config->gpio_num);
+    }
+    if (config->flags.pull_up) {
+        gpio_pullup_en(config->gpio_num);
+    }
+
+    // deprecated, to be removed in in esp-idf v6.0
+    if (config->flags.io_loop_back) {
+        gpio_ll_output_enable(&GPIO, config->gpio_num);
+    }
+
     // set fault detection polarity
     // different gpio faults share the same config register, using a group level spin lock
     portENTER_CRITICAL(&group->spinlock);
@@ -151,10 +159,10 @@ static esp_err_t mcpwm_del_gpio_fault(mcpwm_fault_handle_t fault)
     mcpwm_gpio_fault_t *gpio_fault = __containerof(fault, mcpwm_gpio_fault_t, base);
     mcpwm_group_t *group = fault->group;
     mcpwm_hal_context_t *hal = &group->hal;
+    int group_id = group->group_id;
     int fault_id = gpio_fault->fault_id;
 
     ESP_LOGD(TAG, "del GPIO fault (%d,%d)", group->group_id, fault_id);
-    gpio_reset_pin(gpio_fault->gpio_num);
 
     portENTER_CRITICAL(&group->spinlock);
     mcpwm_ll_intr_enable(hal->dev, MCPWM_LL_EVENT_FAULT_MASK(fault_id), false);
@@ -164,6 +172,10 @@ static esp_err_t mcpwm_del_gpio_fault(mcpwm_fault_handle_t fault)
     // disable fault detection
     mcpwm_ll_fault_enable_detection(hal->dev, fault_id, false);
 
+    // disconnect signal from the GPIO pin
+    esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT,
+                                   mcpwm_periph_signals.groups[group_id].gpio_faults[fault_id].fault_sig, 0);
+
     // recycle memory resource
     ESP_RETURN_ON_ERROR(mcpwm_gpio_fault_destroy(gpio_fault), TAG, "destroy GPIO fault failed");
     return ESP_OK;
diff --git a/components/esp_driver_mcpwm/src/mcpwm_gen.c b/components/esp_driver_mcpwm/src/mcpwm_gen.c
index 0851f744c61..85ca5cb8f2b 100644
--- a/components/esp_driver_mcpwm/src/mcpwm_gen.c
+++ b/components/esp_driver_mcpwm/src/mcpwm_gen.c
@@ -21,10 +21,12 @@
 #include "soc/soc_caps.h"
 #include "soc/mcpwm_periph.h"
 #include "hal/mcpwm_ll.h"
+#include "hal/gpio_hal.h"
 #include "driver/gpio.h"
 #include "driver/mcpwm_gen.h"
 #include "mcpwm_private.h"
 #include "esp_private/esp_gpio_reserve.h"
+#include "esp_private/gpio.h"
 
 static const char *TAG = "mcpwm";
 
@@ -84,27 +86,29 @@ esp_err_t mcpwm_new_generator(mcpwm_oper_handle_t oper, const mcpwm_generator_co
     // reset generator
     mcpwm_hal_generator_reset(hal, oper_id, gen_id);
 
-    // GPIO configuration
     gen->gen_gpio_num = -1; // gpio not initialized yet
-    gpio_config_t gpio_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        // also enable the input path if `io_loop_back` is enabled
-        .mode = (config->flags.io_od_mode ? GPIO_MODE_OUTPUT_OD : GPIO_MODE_OUTPUT) | (config->flags.io_loop_back ? GPIO_MODE_INPUT : 0),
-        .pin_bit_mask = (1ULL << config->gen_gpio_num),
-        .pull_down_en = config->flags.pull_down,
-        .pull_up_en = config->flags.pull_up,
-    };
-    ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config gen GPIO failed");
     // reserve the GPIO output path, because we don't expect another peripheral to signal to the same GPIO
     uint64_t old_gpio_rsv_mask = esp_gpio_reserve(BIT64(config->gen_gpio_num));
     // check if the GPIO is already used by others
     if (old_gpio_rsv_mask & BIT64(config->gen_gpio_num)) {
         ESP_LOGW(TAG, "GPIO %d is not usable, maybe conflict with others", config->gen_gpio_num);
     }
+
+    // GPIO Matrix/MUX configuration
+    gpio_func_sel(config->gen_gpio_num, PIN_FUNC_GPIO);
+    // connect the signal to the GPIO by matrix, it will also enable the output path properly
     esp_rom_gpio_connect_out_signal(config->gen_gpio_num,
                                     mcpwm_periph_signals.groups[group->group_id].operators[oper_id].generators[gen_id].pwm_sig,
                                     config->flags.invert_pwm, 0);
 
+    // deprecated, to be removed in in esp-idf v6.0
+    if (config->flags.io_loop_back) {
+        gpio_ll_input_enable(&GPIO, config->gen_gpio_num);
+    }
+    if (config->flags.io_od_mode) {
+        gpio_ll_od_enable(&GPIO, config->gen_gpio_num);
+    }
+
     // fill in other generator members
     gen->gen_gpio_num = config->gen_gpio_num;
     gen->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
@@ -126,9 +130,9 @@ esp_err_t mcpwm_del_generator(mcpwm_gen_handle_t gen)
     mcpwm_group_t *group = oper->group;
 
     ESP_LOGD(TAG, "del generator (%d,%d,%d)", group->group_id, oper->oper_id, gen->gen_id);
-    // reset GPIO
+    // disable GPIO output
     if (gen->gen_gpio_num >= 0) {
-        gpio_reset_pin(gen->gen_gpio_num);
+        gpio_output_disable(gen->gen_gpio_num);
         esp_gpio_revoke(BIT64(gen->gen_gpio_num));
     }
     // recycle memory resource
@@ -401,6 +405,10 @@ esp_err_t mcpwm_generator_set_dead_time(mcpwm_gen_handle_t in_generator, mcpwm_g
         mcpwm_ll_deadtime_set_falling_delay(hal->dev, oper_id, config->negedge_delay_ticks);
     }
 
+    if (delay_on_both_edge && in_generator->gen_id == 0 && oper->generators[1]) {
+        ESP_LOGW(TAG, "generator B will not function correctly. To set deadtime on both edges for one generator while bypassing the deadtime for the other, please set the deadtime for generator B only.");
+    }
+
     ESP_LOGD(TAG, "operator (%d,%d) dead time (R:%"PRIu32",F:%"PRIu32"), topology code:%"PRIx32, group->group_id, oper_id,
              config->posedge_delay_ticks, config->negedge_delay_ticks, mcpwm_ll_deadtime_get_switch_topology(hal->dev, oper_id));
     return ESP_OK;
diff --git a/components/esp_driver_mcpwm/src/mcpwm_private.h b/components/esp_driver_mcpwm/src/mcpwm_private.h
index cc3e2fcd490..0a51d6e0701 100644
--- a/components/esp_driver_mcpwm/src/mcpwm_private.h
+++ b/components/esp_driver_mcpwm/src/mcpwm_private.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,7 @@
 #include "hal/mcpwm_hal.h"
 #include "hal/mcpwm_types.h"
 #include "driver/mcpwm_types.h"
+#include "esp_private/sleep_retention.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -34,6 +35,9 @@ extern "C" {
 #define MCPWM_INTR_ALLOC_FLAG     (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED)
 #endif
 
+// Use retention link only when the target supports sleep retention is enabled
+#define MCPWM_USE_RETENTION_LINK  (SOC_MCPWM_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+
 #define MCPWM_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED
 
 #define MCPWM_GROUP_CLOCK_DEFAULT_PRESCALE 2
@@ -250,9 +254,6 @@ struct mcpwm_cap_channel_t {
     intr_handle_t intr;               // Interrupt handle
     mcpwm_capture_event_cb_t on_cap;  // Callback function which would be invoked in capture interrupt routine
     void *user_data;                  // user data which would be passed to the capture callback
-    struct {
-        uint32_t reset_io_at_exit: 1; // Whether to reset the GPIO configuration when capture channel is deleted
-    } flags;
 };
 
 mcpwm_group_t *mcpwm_acquire_group_handle(int group_id);
@@ -262,6 +263,10 @@ int mcpwm_get_intr_priority_flag(mcpwm_group_t *group);
 esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_src);
 esp_err_t mcpwm_set_prescale(mcpwm_group_t *group, uint32_t expect_module_resolution_hz, uint32_t module_prescale_max, uint32_t *ret_module_prescale);
 
+#if MCPWM_USE_RETENTION_LINK
+void mcpwm_create_retention_module(mcpwm_group_t *group);
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_mcpwm/src/mcpwm_sync.c b/components/esp_driver_mcpwm/src/mcpwm_sync.c
index dede456adc3..3fe84b5fb26 100644
--- a/components/esp_driver_mcpwm/src/mcpwm_sync.c
+++ b/components/esp_driver_mcpwm/src/mcpwm_sync.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,9 +22,11 @@
 #include "soc/soc_caps.h"
 #include "soc/mcpwm_periph.h"
 #include "hal/mcpwm_ll.h"
+#include "hal/gpio_hal.h"
 #include "driver/mcpwm_sync.h"
 #include "driver/gpio.h"
 #include "mcpwm_private.h"
+#include "esp_private/gpio.h"
 
 static const char *TAG = "mcpwm";
 
@@ -192,16 +194,23 @@ esp_err_t mcpwm_new_gpio_sync_src(const mcpwm_gpio_sync_src_config_t *config, mc
     int sync_id = gpio_sync_src->sync_id;
 
     // GPIO configuration
-    gpio_config_t gpio_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        .mode = GPIO_MODE_INPUT | (config->flags.io_loop_back ? GPIO_MODE_OUTPUT : 0), // also enable the output path if `io_loop_back` is enabled
-        .pin_bit_mask = (1ULL << config->gpio_num),
-        .pull_down_en = config->flags.pull_down,
-        .pull_up_en = config->flags.pull_up,
-    };
-    ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config sync GPIO failed");
+    gpio_func_sel(config->gpio_num, PIN_FUNC_GPIO);
+    gpio_input_enable(config->gpio_num);
+
     esp_rom_gpio_connect_in_signal(config->gpio_num, mcpwm_periph_signals.groups[group_id].gpio_synchros[sync_id].sync_sig, 0);
 
+    if (config->flags.pull_down) {
+        gpio_pulldown_en(config->gpio_num);
+    }
+    if (config->flags.pull_up) {
+        gpio_pullup_en(config->gpio_num);
+    }
+
+    // deprecated, to be removed in in esp-idf v6.0
+    if (config->flags.io_loop_back) {
+        gpio_ll_output_enable(&GPIO, config->gpio_num);
+    }
+
     // different ext sync share the same config register, using a group level spin lock
     portENTER_CRITICAL(&group->spinlock);
     mcpwm_ll_invert_gpio_sync_input(group->hal.dev, sync_id, config->flags.active_neg);
@@ -226,9 +235,11 @@ static esp_err_t mcpwm_del_gpio_sync_src(mcpwm_sync_t *sync_src)
 {
     mcpwm_gpio_sync_src_t *gpio_sync_src = __containerof(sync_src, mcpwm_gpio_sync_src_t, base);
     mcpwm_group_t *group = sync_src->group;
+    int group_id = group->group_id;
+    int sync_id = gpio_sync_src->sync_id;
 
     ESP_LOGD(TAG, "del gpio sync_src (%d,%d)", group->group_id, gpio_sync_src->sync_id);
-    gpio_reset_pin(gpio_sync_src->gpio_num);
+    esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, mcpwm_periph_signals.groups[group_id].gpio_synchros[sync_id].sync_sig, 0);
 
     // recycle memory resource
     ESP_RETURN_ON_ERROR(mcpwm_gpio_sync_src_destroy(gpio_sync_src), TAG, "destroy GPIO sync_src failed");
diff --git a/components/esp_driver_mcpwm/src/mcpwm_timer.c b/components/esp_driver_mcpwm/src/mcpwm_timer.c
index 19dc756af14..8acedf36abc 100644
--- a/components/esp_driver_mcpwm/src/mcpwm_timer.c
+++ b/components/esp_driver_mcpwm/src/mcpwm_timer.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -102,6 +102,10 @@ esp_err_t mcpwm_new_timer(const mcpwm_timer_config_t *config, mcpwm_timer_handle
     }
     ESP_GOTO_ON_FALSE(peak_ticks > 0 && peak_ticks < MCPWM_LL_MAX_COUNT_VALUE, ESP_ERR_INVALID_ARG, err, TAG, "invalid period ticks");
 
+#if !SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "register back up is not supported");
+#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+
     timer = heap_caps_calloc(1, sizeof(mcpwm_timer_t), MCPWM_MEM_ALLOC_CAPS);
     ESP_GOTO_ON_FALSE(timer, ESP_ERR_NO_MEM, err, TAG, "no mem for timer");
 
@@ -143,6 +147,13 @@ esp_err_t mcpwm_new_timer(const mcpwm_timer_config_t *config, mcpwm_timer_handle
     timer->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
     timer->fsm = MCPWM_TIMER_FSM_INIT;
     *ret_timer = timer;
+
+#if MCPWM_USE_RETENTION_LINK
+    if (config->flags.allow_pd != 0) {
+        mcpwm_create_retention_module(group);
+    }
+#endif // MCPWM_USE_RETENTION_LINK
+
     ESP_LOGD(TAG, "new timer(%d,%d) at %p, resolution:%"PRIu32"Hz, peak:%"PRIu32", count_mod:%c",
              group_id, timer_id, timer, timer->resolution_hz, timer->peak_ticks, "SUDB"[timer->count_mode]);
     return ESP_OK;
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/CMakeLists.txt b/components/esp_driver_mcpwm/test_apps/mcpwm/main/CMakeLists.txt
index d4f59e540d5..42208fabf38 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/CMakeLists.txt
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/CMakeLists.txt
@@ -17,6 +17,11 @@ if(CONFIG_SOC_ETM_SUPPORTED AND CONFIG_SOC_MCPWM_SUPPORT_ETM)
     list(APPEND srcs "test_mcpwm_etm.c")
 endif()
 
+# TODO: IDF-9928 support ESP32P4
+if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED AND CONFIG_PM_ENABLE AND NOT CONFIG_IDF_TARGET_ESP32P4)
+    list(APPEND srcs "test_mcpwm_sleep.c")
+endif()
+
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c
index 228d0648cf7..8c01654f4f8 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_cap.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -71,6 +71,14 @@ static bool test_capture_callback(mcpwm_cap_channel_handle_t cap_channel, const
 
 TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]")
 {
+    printf("init a gpio to simulate the external capture signal\r\n");
+    const int cap_gpio = TEST_CAP_GPIO;
+    gpio_config_t ext_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT(cap_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&ext_gpio_conf));
+
     printf("install mcpwm capture timer\r\n");
     mcpwm_cap_timer_handle_t cap_timer = NULL;
     mcpwm_capture_timer_config_t cap_timer_config = {
@@ -80,7 +88,6 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]")
     };
     TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer));
 
-    const int cap_gpio = TEST_CAP_GPIO;
     // put the GPIO into a preset state
     gpio_set_level(cap_gpio, 0);
 
@@ -91,7 +98,6 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]")
         .prescale = 1,
         .flags.pos_edge = true,
         .flags.neg_edge = true,
-        .flags.io_loop_back = true, // so we can use GPIO functions to simulate the external capture signal
         .flags.pull_up = true,
     };
     TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &pps_channel));
@@ -127,6 +133,7 @@ TEST_CASE("mcpwm_capture_ext_gpio", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_capture_channel(pps_channel));
     TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer));
     TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer));
+    TEST_ESP_OK(gpio_reset_pin(cap_gpio));
 }
 
 typedef struct {
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c
index 38a852c06f8..2dc14b34d39 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_fault.c
@@ -58,15 +58,21 @@ static bool IRAM_ATTR test_fault_exit_callback(mcpwm_fault_handle_t detector, co
 
 TEST_CASE("mcpwm_gpio_fault_event_callbacks", "[mcpwm]")
 {
-    printf("create gpio fault\r\n");
+    printf("init a gpio to simulate the fault signal\r\n");
     const int fault_gpio = TEST_FAULT_GPIO;
+    gpio_config_t fault_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT(fault_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&fault_gpio_conf));
+
+    printf("create gpio fault\r\n");
     mcpwm_fault_handle_t fault = NULL;
     mcpwm_gpio_fault_config_t gpio_fault_config = {
         .group_id = 0,
         .gpio_num = fault_gpio,
         .flags.active_level = true, // active on high level
         .flags.pull_down = true,
-        .flags.io_loop_back = true, // for debug, so that we can use gpio_set_level to mimic a fault source
     };
     TEST_ESP_OK(mcpwm_new_gpio_fault(&gpio_fault_config, &fault));
 
@@ -80,7 +86,7 @@ TEST_CASE("mcpwm_gpio_fault_event_callbacks", "[mcpwm]")
     };
     TaskHandle_t task_to_notify = xTaskGetCurrentTaskHandle();
     TEST_ESP_OK(mcpwm_fault_register_event_callbacks(fault, &cbs, task_to_notify));
-    TEST_ASSERT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000)));
+    TEST_ASSERT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(100)));
 
     printf("trigget a fault event\r\n");
     gpio_set_level(fault_gpio, 1);
@@ -91,4 +97,5 @@ TEST_CASE("mcpwm_gpio_fault_event_callbacks", "[mcpwm]")
     TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(10)));
 
     TEST_ESP_OK(mcpwm_del_fault(fault));
+    TEST_ESP_OK(gpio_reset_pin(fault_gpio));
 }
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c
index a00bed33090..1182f74e7df 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c
@@ -7,6 +7,7 @@
 #include "freertos/task.h"
 #include "unity.h"
 #include "soc/soc_caps.h"
+#include "driver/mcpwm_cap.h"
 #include "driver/mcpwm_timer.h"
 #include "driver/mcpwm_oper.h"
 #include "driver/mcpwm_cmpr.h"
@@ -15,6 +16,7 @@
 #include "driver/mcpwm_sync.h"
 #include "driver/gpio.h"
 #include "test_mcpwm_utils.h"
+#include "esp_clk_tree.h"
 
 TEST_CASE("mcpwm_generator_install_uninstall", "[mcpwm]")
 {
@@ -46,6 +48,14 @@ TEST_CASE("mcpwm_generator_install_uninstall", "[mcpwm]")
 
 TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]")
 {
+    const int gen_gpio = TEST_PWMA_GPIO;
+    printf("init a gpio to read generator output\r\n");
+    gpio_config_t gen_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(gen_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&gen_gpio_conf));
+
     // The operator can even work without the timer
     printf("create operator and generator\r\n");
     mcpwm_oper_handle_t oper = NULL;
@@ -55,10 +65,8 @@ TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]")
     TEST_ESP_OK(mcpwm_new_operator(&operator_config, &oper));
 
     mcpwm_gen_handle_t generator = NULL;
-    const int gen_gpio = TEST_PWMA_GPIO;
     mcpwm_generator_config_t generator_config = {
         .gen_gpio_num = gen_gpio,
-        .flags.io_loop_back = true, // loop back for test
     };
     TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator));
 
@@ -78,12 +86,22 @@ TEST_CASE("mcpwm_generator_force_level_hold_on", "[mcpwm]")
     printf("delete generator and operator\r\n");
     TEST_ESP_OK(mcpwm_del_generator(generator));
     TEST_ESP_OK(mcpwm_del_operator(oper));
+    TEST_ESP_OK(gpio_reset_pin(gen_gpio));
 }
 
 // mcpwm_generator_set_force_level acts before the dead time module
 // so the value output on the generator is a combined result
 TEST_CASE("mcpwm_force_level_and_dead_time", "[mcpwm]")
 {
+    const int gen_a_gpio = TEST_PWMA_GPIO;
+    const int gen_b_gpio = TEST_PWMB_GPIO;
+    printf("init gpios to read generator output\r\n");
+    gpio_config_t gen_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(gen_a_gpio) | BIT(gen_b_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&gen_gpio_conf));
+
     printf("create operator and generators\r\n");
     mcpwm_oper_handle_t oper = NULL;
     mcpwm_operator_config_t operator_config = {
@@ -93,11 +111,8 @@ TEST_CASE("mcpwm_force_level_and_dead_time", "[mcpwm]")
 
     mcpwm_gen_handle_t gen_a = NULL;
     mcpwm_gen_handle_t gen_b = NULL;
-    const int gen_a_gpio = TEST_PWMA_GPIO;
-    const int gen_b_gpio = TEST_PWMB_GPIO;
     mcpwm_generator_config_t generator_config = {
         .gen_gpio_num = gen_a_gpio,
-        .flags.io_loop_back = true, // loop back for test
     };
     TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_a));
     generator_config.gen_gpio_num = gen_b_gpio;
@@ -128,10 +143,20 @@ TEST_CASE("mcpwm_force_level_and_dead_time", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(gen_a));
     TEST_ESP_OK(mcpwm_del_generator(gen_b));
     TEST_ESP_OK(mcpwm_del_operator(oper));
+    TEST_ESP_OK(gpio_reset_pin(gen_a_gpio));
+    TEST_ESP_OK(gpio_reset_pin(gen_b_gpio));
 }
 
 TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]")
 {
+    const int gen_gpio = TEST_PWMA_GPIO;
+    printf("init a gpio to read generator output\r\n");
+    gpio_config_t gen_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(gen_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&gen_gpio_conf));
+
     printf("create mcpwm timer\r\n");
     mcpwm_timer_config_t timer_config = {
         .group_id = 0,
@@ -155,10 +180,8 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]")
 
     printf("create generator\r\n");
     mcpwm_gen_handle_t generator = NULL;
-    const int gen_gpio = TEST_PWMA_GPIO;
     mcpwm_generator_config_t generator_config = {
         .gen_gpio_num = gen_gpio,
-        .flags.io_loop_back = true, // loop back for test
     };
     TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &generator));
 
@@ -195,11 +218,19 @@ TEST_CASE("mcpwm_generator_force_level_recovery", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(generator));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(gen_gpio));
 }
 
 TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]")
 {
     const int generator_gpio = TEST_PWMA_GPIO;
+    printf("init a gpio to read generator output\r\n");
+    gpio_config_t gen_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(generator_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&gen_gpio_conf));
+
     printf("create timer and operator\r\n");
     mcpwm_timer_config_t timer_config = {
         .group_id = 0,
@@ -224,7 +255,6 @@ TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]")
     printf("create generator\r\n");
     mcpwm_generator_config_t gen_config = {
         .gen_gpio_num = generator_gpio,
-        .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver
     };
     mcpwm_gen_handle_t gen = NULL;
     TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen));
@@ -258,12 +288,26 @@ TEST_CASE("mcpwm_generator_action_on_timer_event", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(gen));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(generator_gpio));
+}
+
+TEST_MCPWM_CALLBACK_ATTR
+static bool test_capture_callback(mcpwm_cap_channel_handle_t cap_channel, const mcpwm_capture_event_data_t *edata, void *user_data)
+{
+    uint32_t *cap_value = (uint32_t *)user_data;
+    if (edata->cap_edge == MCPWM_CAP_EDGE_NEG) {
+        cap_value[1] = edata->cap_value;
+    } else {
+        cap_value[0] = edata->cap_value;
+    }
+    return false;
 }
 
 typedef void (*set_gen_actions_cb_t)(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb);
 
 static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t period, mcpwm_timer_count_mode_t count_mode,
-                                           uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob, set_gen_actions_cb_t set_generator_actions)
+                                           uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob, set_gen_actions_cb_t set_generator_actions,
+                                           uint32_t *ret_capa, uint32_t *ret_capb)
 {
     mcpwm_timer_config_t timer_config = {
         .group_id = 0,
@@ -305,10 +349,72 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p
 
     set_generator_actions(generator_a, generator_b, comparator_a, comparator_b);
 
+    // install mcpwm capture timer
+    mcpwm_cap_timer_handle_t cap_timer = NULL;
+    uint32_t clk_src_freq_hz;
+    esp_clk_tree_src_get_freq_hz(MCPWM_CAPTURE_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
+    mcpwm_capture_timer_config_t cap_timer_config = {
+        .clk_src = MCPWM_CAPTURE_CLK_SRC_DEFAULT,
+        .group_id = 0,
+        .resolution_hz = clk_src_freq_hz / 2,
+    };
+    TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer));
+
+    // install mcpwm capture channel
+    mcpwm_cap_channel_handle_t cap_channel_a;
+    mcpwm_cap_channel_handle_t cap_channel_b;
+    mcpwm_capture_channel_config_t cap_chan_config = {
+        .gpio_num = gpioa,
+        .prescale = 1,
+        .flags.pos_edge = true,
+        .flags.neg_edge = true,
+    };
+    TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel_a));
+    cap_chan_config.gpio_num = gpiob;
+    TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel_b));
+
+    // install callback for capture channel
+    mcpwm_capture_event_callbacks_t cbs = {
+        .on_cap = test_capture_callback,
+    };
+    uint32_t cap_value_a[2] = {0};
+    uint32_t cap_value_b[2] = {0};
+    TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel_a, &cbs, cap_value_a));
+    TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel_b, &cbs, cap_value_b));
+
+    // enable capture channel and timer
+    TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel_a));
+    TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel_b));
+    TEST_ESP_OK(mcpwm_capture_timer_enable(cap_timer));
+
+    // start timer and capture timer
     TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP));
+    TEST_ESP_OK(mcpwm_capture_timer_start(cap_timer));
     vTaskDelay(pdMS_TO_TICKS(100));
     TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY));
     vTaskDelay(pdMS_TO_TICKS(10));
+    TEST_ESP_OK(mcpwm_capture_timer_stop(cap_timer));
+
+    // calculate the actual capture time
+    uint32_t clk_src_res;
+    TEST_ESP_OK(mcpwm_capture_timer_get_resolution(cap_timer, &clk_src_res));
+    clk_src_res /= 1000; // convert to kHz
+
+    if (cap_value_a[1] > cap_value_a[0]) {
+        // generator end with low level, calculate the high level time
+        *ret_capa = (cap_value_a[1] - cap_value_a[0]) * 1000 / clk_src_res;
+    } else {
+        // generator end with high level, calculate the low level time
+        *ret_capa = (cap_value_a[0] - cap_value_a[1]) * 1000 / clk_src_res;
+    }
+
+    if (cap_value_b[1] > cap_value_b[0]) {
+        // generator end with low level, calculate the high level time
+        *ret_capb = (cap_value_b[1] - cap_value_b[0]) * 1000 / clk_src_res;
+    } else {
+        // generator end with high level, calculate the low level time
+        *ret_capb = (cap_value_b[0] - cap_value_b[1]) * 1000 / clk_src_res;
+    }
 
     TEST_ESP_OK(mcpwm_timer_disable(timer));
     TEST_ESP_OK(mcpwm_del_generator(generator_a));
@@ -317,6 +423,12 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p
     TEST_ESP_OK(mcpwm_del_comparator(comparator_b));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_a));
+    TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_a));
+    TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_b));
+    TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_b));
+    TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer));
+    TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer));
 }
 
 static void single_edge_active_high(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb)
@@ -392,41 +504,55 @@ static void dual_edge_complementary(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t
 
 TEST_CASE("mcpwm_generator_action_on_compare_event", "[mcpwm]")
 {
+    uint32_t capa, capb;
     printf("[Asymmetric, SingleEdge, ActiveHigh]\r\n");
     // PWMA: high = [1->350], low = [351->499,0]
     // PWMB: high = [1->200], low = [201->499,0]
-    mcpwm_gen_action_test_template(1000000, 500, MCPWM_TIMER_COUNT_MODE_UP, 350, 200, TEST_PWMA_GPIO, TEST_PWMB_GPIO, single_edge_active_high);
+    mcpwm_gen_action_test_template(1000000, 500, MCPWM_TIMER_COUNT_MODE_UP, 350, 200, TEST_PWMA_GPIO, TEST_PWMB_GPIO, single_edge_active_high, &capa, &capb);
+    TEST_ASSERT_UINT_WITHIN(2, 150, capa);
+    TEST_ASSERT_UINT_WITHIN(2, 300, capb);
 
     printf("[Asymmetric, SingleEdge, ActiveLow]\r\n");
     // PWMA: low = [0->300], high = [301->499]
     // PWMB: low = [0->150], high = [151->499]
-    mcpwm_gen_action_test_template(1000000, 500, MCPWM_TIMER_COUNT_MODE_UP, 300, 150, TEST_PWMA_GPIO, TEST_PWMB_GPIO, single_edge_active_low);
+    mcpwm_gen_action_test_template(1000000, 500, MCPWM_TIMER_COUNT_MODE_UP, 300, 150, TEST_PWMA_GPIO, TEST_PWMB_GPIO, single_edge_active_low, &capa, &capb);
+    TEST_ASSERT_UINT_WITHIN(2, 200, capa);
+    TEST_ASSERT_UINT_WITHIN(2, 350, capb);
 
     printf("[Asymmetric, PulsePlacement]\r\n");
     // PWMA: low = [0->200], high = [201->400], low = [401->599]
     // PWMB: high = [0->599], low = [0->599]
-    mcpwm_gen_action_test_template(1000000, 600, MCPWM_TIMER_COUNT_MODE_UP, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, pulse_placement);
+    mcpwm_gen_action_test_template(1000000, 600, MCPWM_TIMER_COUNT_MODE_UP, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, pulse_placement, &capa, &capb);
+    TEST_ASSERT_UINT_WITHIN(2, 200, capa);
+    TEST_ASSERT_UINT_WITHIN(2, 600, capb);
 
     printf("[Asymmetric, DualEdge, ActiveLow]\r\n");
     // PWMA: low = [0->250], high = [251->599, 600->450], low = [451->1]
     // PWMB: low = [0->599], low = [600->1]
-    mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 250, 450, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_active_low_asym);
+    mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 250, 450, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_active_low_asym, &capa, &capb);
+    TEST_ASSERT_UINT_WITHIN(2, 500, capa);
+    TEST_ASSERT_UINT_WITHIN(2, 600, capb);
 
     printf("[Symmetric, DualEdge, ActiveLow]\r\n");
     // PWMA: low = [0->400], high = [401->599, 600->400], low = [399->1]
     // PWMB: low = [0->500], high = [501->599, 600->500], low = [499->1]
-    mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 400, 500, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_active_low_sym);
+    mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 400, 500, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_active_low_sym, &capa, &capb);
+    TEST_ASSERT_UINT_WITHIN(2, 400, capa);
+    TEST_ASSERT_UINT_WITHIN(2, 200, capb);
 
     printf("[Symmetric, DualEdge, Complementary]\r\n");
     // PWMA: low = [0->350], high = [351->599, 600->350], low = [349->1]
     // PWMB: low = [0->400], high = [401->599, 600->400], low = [399->1]
-    mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 350, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_complementary);
+    mcpwm_gen_action_test_template(1000000, 1200, MCPWM_TIMER_COUNT_MODE_UP_DOWN, 350, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, dual_edge_complementary, &capa, &capb);
+    TEST_ASSERT_UINT_WITHIN(2, 500, capa);
+    TEST_ASSERT_UINT_WITHIN(2, 400, capb);
 }
 
 typedef void (*set_dead_time_cb_t)(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb);
 
 static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t period, uint32_t cmpa, uint32_t cmpb, int gpioa, int gpiob,
-                                         set_gen_actions_cb_t set_generator_actions, set_dead_time_cb_t set_dead_time)
+                                         set_gen_actions_cb_t set_generator_actions, set_dead_time_cb_t set_dead_time,
+                                         uint32_t ret_capa[2], uint32_t ret_capb[2])
 {
     mcpwm_timer_config_t timer_config = {
         .group_id = 0,
@@ -469,10 +595,61 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per
     set_generator_actions(generator_a, generator_b, comparator_a, comparator_b);
     set_dead_time(generator_a, generator_b);
 
+    // install mcpwm capture timer
+    mcpwm_cap_timer_handle_t cap_timer = NULL;
+    uint32_t clk_src_freq_hz;
+    esp_clk_tree_src_get_freq_hz(MCPWM_CAPTURE_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
+    mcpwm_capture_timer_config_t cap_timer_config = {
+        .clk_src = MCPWM_CAPTURE_CLK_SRC_DEFAULT,
+        .group_id = 0,
+        .resolution_hz = clk_src_freq_hz / 2,
+    };
+    TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer));
+
+    // install mcpwm capture channel
+    mcpwm_cap_channel_handle_t cap_channel_a;
+    mcpwm_cap_channel_handle_t cap_channel_b;
+    mcpwm_capture_channel_config_t cap_chan_config = {
+        .gpio_num = gpioa,
+        .prescale = 1,
+        .flags.pos_edge = true,
+        .flags.neg_edge = true,
+    };
+    TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel_a));
+    cap_chan_config.gpio_num = gpiob;
+    TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel_b));
+
+    // install callback for capture channel
+    mcpwm_capture_event_callbacks_t cbs = {
+        .on_cap = test_capture_callback,
+    };
+    uint32_t cap_value_a[2] = {0};
+    uint32_t cap_value_b[2] = {0};
+    TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel_a, &cbs, cap_value_a));
+    TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel_b, &cbs, cap_value_b));
+
+    // enable capture channel and timer
+    TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel_a));
+    TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel_b));
+    TEST_ESP_OK(mcpwm_capture_timer_enable(cap_timer));
+
+    // start timer and capture timer
     TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP));
+    TEST_ESP_OK(mcpwm_capture_timer_start(cap_timer));
     vTaskDelay(pdMS_TO_TICKS(100));
-    TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_EMPTY));
+    TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_FULL));
     vTaskDelay(pdMS_TO_TICKS(10));
+    TEST_ESP_OK(mcpwm_capture_timer_stop(cap_timer));
+
+    // calculate the actual capture time
+    uint32_t clk_src_res;
+    TEST_ESP_OK(mcpwm_capture_timer_get_resolution(cap_timer, &clk_src_res));
+    clk_src_res /= 1000; // convert to kHz
+
+    ret_capa[0] = cap_value_a[0] * 1000 / clk_src_res;
+    ret_capa[1] = cap_value_a[1] * 1000 / clk_src_res;
+    ret_capb[0] = cap_value_b[0] * 1000 / clk_src_res;
+    ret_capb[1] = cap_value_b[1] * 1000 / clk_src_res;
 
     TEST_ESP_OK(mcpwm_timer_disable(timer));
     TEST_ESP_OK(mcpwm_del_generator(generator_a));
@@ -481,6 +658,12 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per
     TEST_ESP_OK(mcpwm_del_comparator(comparator_b));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_a));
+    TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_a));
+    TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_b));
+    TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_b));
+    TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer));
+    TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer));
 }
 
 static void ahc_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb)
@@ -663,34 +846,58 @@ static void invalid_reda_redb_set_dead_time(mcpwm_gen_handle_t gena, mcpwm_gen_h
 
 TEST_CASE("mcpwm_generator_deadtime_classical_configuration", "[mcpwm]")
 {
+    uint32_t capa[2], capb[2];
     printf("Active High Complementary\r\n");
-    mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, ahc_set_generator_actions, ahc_set_dead_time);
+    mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, ahc_set_generator_actions, ahc_set_dead_time, capa, capb);
+    TEST_ASSERT_UINT_WITHIN(2, 50, capa[0] - capb[1]);
+    TEST_ASSERT_UINT_WITHIN(2, 100, capb[0] - capa[1]);
 
     printf("Active Low Complementary\r\n");
-    mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, alc_set_generator_actions, alc_set_dead_time);
+    mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, alc_set_generator_actions, alc_set_dead_time, capa, capb);
+    TEST_ASSERT_UINT_WITHIN(2, 50, capa[1] - capb[0]);
+    TEST_ASSERT_UINT_WITHIN(2, 100, capb[1] - capa[0]);
 
     printf("Active High\r\n");
-    mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, ah_set_generator_actions, ah_set_dead_time);
+    mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, ah_set_generator_actions, ah_set_dead_time, capa, capb);
+    TEST_ASSERT_UINT_WITHIN(2, 50, capa[0] - capb[0]);
+    TEST_ASSERT_UINT_WITHIN(2, 100, capb[1] - capa[1]);
 
     printf("Active Low\r\n");
-    mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, al_set_generator_actions, al_set_dead_time);
+    mcpwm_deadtime_test_template(1000000, 600, 200, 400, TEST_PWMA_GPIO, TEST_PWMB_GPIO, al_set_generator_actions, al_set_dead_time, capa, capb);
+    TEST_ASSERT_UINT_WITHIN(2, 50, capa[1] - capb[1]);
+    TEST_ASSERT_UINT_WITHIN(2, 100, capb[0] - capa[0]);
 
     printf("RED on A, Bypass B\r\n");
-    mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, reda_only_set_generator_actions, reda_only_set_dead_time);
+    mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, reda_only_set_generator_actions, reda_only_set_dead_time, capa, capb);
+    TEST_ASSERT_UINT_WITHIN(2, 50, capa[0] - capb[0]);
+    TEST_ASSERT_UINT_WITHIN(2, 0, capb[1] - capa[1]);
 
     printf("Bypass A, FED on B\r\n");
-    mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, fedb_only_set_generator_actions, fedb_only_set_dead_time);
+    mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, fedb_only_set_generator_actions, fedb_only_set_dead_time, capa, capb);
+    TEST_ASSERT_UINT_WITHIN(2, 50, capb[1] - capa[1]);
+    TEST_ASSERT_UINT_WITHIN(2, 0, capb[0] - capa[0]);
 
     printf("Bypass A, RED + FED on B\r\n");
-    mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, redfedb_only_set_generator_actions, redfedb_only_set_dead_time);
+    mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, redfedb_only_set_generator_actions, redfedb_only_set_dead_time, capa, capb);
+    TEST_ASSERT_UINT_WITHIN(2, 50, capb[0] - capa[0]);
+    TEST_ASSERT_UINT_WITHIN(2, 50, capb[1] - capa[1]);
 
     printf("Can't apply one delay module to multiple generators\r\n");
-    mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, redfedb_only_set_generator_actions, invalid_reda_redb_set_dead_time);
+    mcpwm_deadtime_test_template(1000000, 500, 350, 350, TEST_PWMA_GPIO, TEST_PWMB_GPIO, redfedb_only_set_generator_actions, invalid_reda_redb_set_dead_time, capa, capb);
+    TEST_ASSERT_UINT_WITHIN(2, 0, capa[0] - capb[0]);
+    TEST_ASSERT_UINT_WITHIN(2, 0, capa[1] - capb[1]);
 }
 
 TEST_CASE("mcpwm_duty_empty_full", "[mcpwm]")
 {
     const int gen_gpio_num = TEST_PWMA_GPIO;
+    printf("init a gpio to read generator output\r\n");
+    gpio_config_t gen_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(gen_gpio_num),
+    };
+    TEST_ESP_OK(gpio_config(&gen_gpio_conf));
+
     mcpwm_timer_handle_t timer;
     mcpwm_oper_handle_t oper;
     mcpwm_cmpr_handle_t comparator;
@@ -722,7 +929,6 @@ TEST_CASE("mcpwm_duty_empty_full", "[mcpwm]")
     printf("install MCPWM generator\r\n");
     mcpwm_generator_config_t gen_config = {
         .gen_gpio_num = gen_gpio_num,
-        .flags.io_loop_back = true, // we want to read the output level as well
     };
     TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen));
 
@@ -763,12 +969,30 @@ TEST_CASE("mcpwm_duty_empty_full", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_comparator(comparator));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(gen_gpio_num));
 }
 
 TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]")
 {
     const int generator_gpio = TEST_PWMA_GPIO;
     const int fault_gpio_num[3] = {TEST_FAULT_GPIO0, TEST_FAULT_GPIO1, TEST_FAULT_GPIO2};
+
+    printf("init a gpio to read generator output and simulate fault signal\r\n");
+    gpio_config_t generator_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(generator_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&generator_gpio_conf));
+
+    gpio_config_t fault_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = 0,
+    };
+    for (int i = 0; i < 3; i++) {
+        fault_gpio_conf.pin_bit_mask |= BIT(fault_gpio_num[i]);
+    }
+    TEST_ESP_OK(gpio_config(&fault_gpio_conf));
+
     printf("create timer and operator\r\n");
     mcpwm_timer_config_t timer_config = {
         .group_id = 0,
@@ -796,7 +1020,6 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]")
         .flags.active_level = 1,
         .flags.pull_down = 1,
         .flags.pull_up = 0,
-        .flags.io_loop_back = 1, // so that we can write the GPIO value by GPIO driver
     };
     for (int i = 0 ; i < 3; i++) {
         gpio_trigger_config.gpio_num = fault_gpio_num[i];
@@ -806,7 +1029,6 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]")
     printf("create generator\r\n");
     mcpwm_generator_config_t gen_config = {
         .gen_gpio_num = generator_gpio,
-        .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver
     };
     mcpwm_gen_handle_t gen = NULL;
     TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen));
@@ -839,11 +1061,22 @@ TEST_CASE("mcpwm_generator_action_on_fault_trigger_event", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(gen));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(generator_gpio));
+    for (int i = 0; i < 3; i++) {
+        TEST_ESP_OK(gpio_reset_pin(fault_gpio_num[i]));
+    }
 }
 
 TEST_CASE("mcpwm_generator_action_on_soft_sync_trigger_event", "[mcpwm]")
 {
     const int generator_gpio = TEST_PWMA_GPIO;
+    printf("init a gpio to read generator output\r\n");
+    gpio_config_t generator_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(generator_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&generator_gpio_conf));
+
     printf("create timer and operator\r\n");
     mcpwm_timer_config_t timer_config = {
         .group_id = 0,
@@ -879,7 +1112,6 @@ TEST_CASE("mcpwm_generator_action_on_soft_sync_trigger_event", "[mcpwm]")
     printf("create generator\r\n");
     mcpwm_generator_config_t gen_config = {
         .gen_gpio_num = generator_gpio,
-        .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver
     };
     mcpwm_gen_handle_t gen = NULL;
     TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen));
@@ -905,11 +1137,19 @@ TEST_CASE("mcpwm_generator_action_on_soft_sync_trigger_event", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(gen));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(generator_gpio));
 }
 
 TEST_CASE("mcpwm_generator_action_on_timer_sync_trigger_event", "[mcpwm]")
 {
     const int generator_gpio = TEST_PWMA_GPIO;
+    printf("init a gpio to read generator output\r\n");
+    gpio_config_t generator_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(generator_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&generator_gpio_conf));
+
     printf("create timer and operator\r\n");
     mcpwm_timer_config_t timer_config = {
         .group_id = 0,
@@ -948,7 +1188,6 @@ TEST_CASE("mcpwm_generator_action_on_timer_sync_trigger_event", "[mcpwm]")
     printf("create generator\r\n");
     mcpwm_generator_config_t gen_config = {
         .gen_gpio_num = generator_gpio,
-        .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver
     };
     mcpwm_gen_handle_t gen = NULL;
     TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen));
@@ -970,11 +1209,25 @@ TEST_CASE("mcpwm_generator_action_on_timer_sync_trigger_event", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(gen));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(generator_gpio));
 }
 
 TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]")
 {
     const int generator_gpio = TEST_PWMA_GPIO;
+    const int sync_gpio = TEST_SYNC_GPIO;
+    printf("init a gpio to read generator output and simulate sync signal\r\n");
+    gpio_config_t generator_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(generator_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&generator_gpio_conf));
+    gpio_config_t sync_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT(sync_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&sync_gpio_conf));
+
     printf("create timer and operator\r\n");
     mcpwm_timer_config_t timer_config = {
         .group_id = 0,
@@ -999,14 +1252,13 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]")
     mcpwm_sync_handle_t gpio_sync = NULL;
     mcpwm_gpio_sync_src_config_t gpio_sync_config = {
         .group_id = 0,
-        .gpio_num = TEST_SYNC_GPIO,
-        .flags.io_loop_back = true, // so that we can use gpio driver to simulate the sync signal
+        .gpio_num = sync_gpio,
         .flags.pull_down = true, // internally pull down
     };
     TEST_ESP_OK(mcpwm_new_gpio_sync_src(&gpio_sync_config, &gpio_sync));
 
     // put the GPIO into initial state
-    gpio_set_level(gpio_sync_config.gpio_num, 0);
+    gpio_set_level(sync_gpio, 0);
 
     mcpwm_timer_sync_phase_config_t sync_phase_config = {
         .count_value = 0,
@@ -1018,7 +1270,6 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]")
     printf("create generator\r\n");
     mcpwm_generator_config_t gen_config = {
         .gen_gpio_num = generator_gpio,
-        .flags.io_loop_back = 1, // so that we can read the GPIO value by GPIO driver
     };
     mcpwm_gen_handle_t gen = NULL;
     TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen));
@@ -1028,8 +1279,8 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]")
                                                          MCPWM_GEN_SYNC_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, gpio_sync, MCPWM_GEN_ACTION_HIGH)));
 
     TEST_ASSERT_EQUAL(0, gpio_get_level(generator_gpio));
-    gpio_set_level(gpio_sync_config.gpio_num, 1);
-    gpio_set_level(gpio_sync_config.gpio_num, 0);
+    gpio_set_level(sync_gpio, 1);
+    gpio_set_level(sync_gpio, 0);
     TEST_ASSERT_EQUAL(1, gpio_get_level(generator_gpio));
     vTaskDelay(pdMS_TO_TICKS(10));
 
@@ -1038,4 +1289,6 @@ TEST_CASE("mcpwm_generator_action_on_gpio_sync_trigger_event", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(gen));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(generator_gpio));
+    TEST_ESP_OK(gpio_reset_pin(sync_gpio));
 }
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c
index fa53482c569..24744463bab 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_iram.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -46,6 +46,13 @@ TEST_CASE("mcpwm_capture_iram_safe", "[mcpwm]")
     TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer));
 
     const int cap_gpio = TEST_CAP_GPIO;
+    printf("init a gpio to simulate the external capture signal\r\n");
+    gpio_config_t cap_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT(cap_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&cap_gpio_conf));
+
     // put the GPIO into a preset state
     gpio_set_level(cap_gpio, 0);
 
@@ -56,7 +63,6 @@ TEST_CASE("mcpwm_capture_iram_safe", "[mcpwm]")
         .prescale = 1,
         .flags.pos_edge = true,
         .flags.neg_edge = true,
-        .flags.io_loop_back = true, // so we can use GPIO functions to simulate the external capture signal
         .flags.pull_up = true,
     };
     TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &pps_channel));
@@ -89,6 +95,7 @@ TEST_CASE("mcpwm_capture_iram_safe", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_capture_channel(pps_channel));
     TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer));
     TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer));
+    TEST_ESP_OK(gpio_reset_pin(cap_gpio));
 }
 
 static bool IRAM_ATTR test_compare_on_reach(mcpwm_cmpr_handle_t cmpr, const mcpwm_compare_event_data_t *ev_data, void *user_data)
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c
index 76f977a268c..ce2523d7fbe 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_oper.c
@@ -121,6 +121,22 @@ static bool IRAM_ATTR test_ost_brake_on_gpio_fault_callback(mcpwm_oper_handle_t
 
 TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]")
 {
+    const int cbc_fault_gpio = TEST_FAULT_GPIO1;
+    const int ost_fault_gpio = TEST_FAULT_GPIO2;
+    const int gen_a_gpio = TEST_PWMA_GPIO;
+    const int gen_b_gpio = TEST_PWMB_GPIO;
+    printf("init gpios to read generator output and simulate fault signal\r\n");
+    gpio_config_t fault_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT(cbc_fault_gpio) | BIT(ost_fault_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&fault_gpio_conf));
+    gpio_config_t gen_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(gen_a_gpio) | BIT(gen_b_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&gen_gpio_conf));
+
     printf("install timer\r\n");
     mcpwm_timer_config_t timer_config = {
         .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT,
@@ -151,13 +167,10 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]")
     mcpwm_gpio_fault_config_t gpio_fault_config = {
         .group_id = 0,
         .flags.active_level = 1,
-        .flags.io_loop_back = true,
         .flags.pull_down = true,
     };
     mcpwm_fault_handle_t gpio_cbc_fault = NULL;
     mcpwm_fault_handle_t gpio_ost_fault = NULL;
-    const int cbc_fault_gpio = TEST_FAULT_GPIO1;
-    const int ost_fault_gpio = TEST_FAULT_GPIO2;
 
     gpio_fault_config.gpio_num = cbc_fault_gpio;
     TEST_ESP_OK(mcpwm_new_gpio_fault(&gpio_fault_config, &gpio_cbc_fault));
@@ -180,14 +193,12 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]")
     TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(oper, &brake_config));
 
     printf("create generators\r\n");
-    const int gen_a_gpio = TEST_PWMA_GPIO;
-    const int gen_b_gpio = TEST_PWMB_GPIO;
+
     mcpwm_gen_handle_t gen_a = NULL;
     mcpwm_gen_handle_t gen_b = NULL;
     mcpwm_generator_config_t generator_config = {
-        .flags.io_loop_back = true,
+        .gen_gpio_num = gen_a_gpio,
     };
-    generator_config.gen_gpio_num = gen_a_gpio;
     TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_a));
     generator_config.gen_gpio_num = gen_b_gpio;
     TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_b));
@@ -249,10 +260,23 @@ TEST_CASE("mcpwm_operator_brake_on_gpio_fault", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(gen_b));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(cbc_fault_gpio));
+    TEST_ESP_OK(gpio_reset_pin(ost_fault_gpio));
+    TEST_ESP_OK(gpio_reset_pin(gen_a_gpio));
+    TEST_ESP_OK(gpio_reset_pin(gen_b_gpio));
 }
 
 TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]")
 {
+    const int gen_a_gpio = TEST_PWMA_GPIO;
+    const int gen_b_gpio = TEST_PWMB_GPIO;
+    printf("init gpios to read generator output\r\n");
+    gpio_config_t gen_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(gen_a_gpio) | BIT(gen_b_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&gen_gpio_conf));
+
     printf("install timer\r\n");
     mcpwm_timer_config_t timer_config = {
         .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT,
@@ -286,14 +310,11 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]")
     TEST_ESP_OK(mcpwm_operator_set_brake_on_fault(oper, &brake_config));
 
     printf("create generators\r\n");
-    const int gen_a_gpio = TEST_PWMA_GPIO;
-    const int gen_b_gpio = TEST_PWMB_GPIO;
     mcpwm_gen_handle_t gen_a = NULL;
     mcpwm_gen_handle_t gen_b = NULL;
     mcpwm_generator_config_t generator_config = {
-        .flags.io_loop_back = true,
+        .gen_gpio_num = gen_a_gpio,
     };
-    generator_config.gen_gpio_num = gen_a_gpio;
     TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_a));
     generator_config.gen_gpio_num = gen_b_gpio;
     TEST_ESP_OK(mcpwm_new_generator(oper, &generator_config, &gen_b));
@@ -360,4 +381,6 @@ TEST_CASE("mcpwm_operator_brake_on_soft_fault", "[mcpwm]")
     TEST_ESP_OK(mcpwm_del_generator(gen_b));
     TEST_ESP_OK(mcpwm_del_operator(oper));
     TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(gen_a_gpio));
+    TEST_ESP_OK(gpio_reset_pin(gen_b_gpio));
 }
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sleep.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sleep.c
new file mode 100644
index 00000000000..e1b0840eb1d
--- /dev/null
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sleep.c
@@ -0,0 +1,229 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include "unity.h"
+#include "unity_test_utils.h"
+#include "esp_attr.h"
+#include "esp_clk_tree.h"
+#include "driver/gpio.h"
+#include "driver/mcpwm_prelude.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/sleep_retention.h"
+#include "esp_private/esp_pmu.h"
+#include "test_mcpwm_utils.h"
+
+/**
+ * @brief Test the MCPWM timer can still work after light sleep
+ *
+ * @param allow_pd Whether to allow power down the peripheral in light sleep
+ */
+static void test_mcpwm_timer_sleep_retention(bool allow_pd)
+{
+    const int generator_gpio = TEST_PWMA_GPIO;
+    printf("init a gpio to read generator output\r\n");
+    gpio_config_t gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT(generator_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&gpio_conf));
+
+    printf("create timer and operator\r\n");
+    mcpwm_timer_config_t timer_config = {
+        .group_id = 0,
+        .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT,
+        .resolution_hz = 1000000,
+        .count_mode = MCPWM_TIMER_COUNT_MODE_UP,
+        .period_ticks = 1000,
+        .flags.allow_pd = allow_pd,
+    };
+    mcpwm_timer_handle_t timer = NULL;
+    TEST_ESP_OK(mcpwm_new_timer(&timer_config, &timer));
+
+    mcpwm_operator_config_t oper_config = {
+        .group_id = 0,
+    };
+    mcpwm_oper_handle_t oper = NULL;
+    TEST_ESP_OK(mcpwm_new_operator(&oper_config, &oper));
+
+    printf("connect timer and operator\r\n");
+    TEST_ESP_OK(mcpwm_operator_connect_timer(oper, timer));
+
+    printf("create generator\r\n");
+    mcpwm_generator_config_t gen_config = {
+        .gen_gpio_num = generator_gpio,
+        .flags.io_loop_back = true,
+    };
+    mcpwm_gen_handle_t gen = NULL;
+    TEST_ESP_OK(mcpwm_new_generator(oper, &gen_config, &gen));
+
+    printf("set generator to output high on timer full\r\n");
+    TEST_ESP_OK(mcpwm_generator_set_actions_on_timer_event(gen,
+                                                           MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_FULL, MCPWM_GEN_ACTION_HIGH),
+                                                           MCPWM_GEN_TIMER_EVENT_ACTION(MCPWM_TIMER_DIRECTION_UP, MCPWM_TIMER_EVENT_EMPTY, MCPWM_GEN_ACTION_KEEP),
+                                                           MCPWM_GEN_TIMER_EVENT_ACTION_END()));
+
+    // go to sleep
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+    printf("go to light sleep for 1 seconds\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
+    TEST_ESP_OK(esp_light_sleep_start());
+
+    printf("Waked up! Let's see if MCPWM driver can still work...\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+
+    printf("check if the sleep happened as expected\r\n");
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL(allow_pd ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+    esp_sleep_set_sleep_context(NULL);
+
+    printf("enable timer\r\n");
+    TEST_ESP_OK(mcpwm_timer_enable(timer));
+    printf("start timer\r\n");
+    TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_START_NO_STOP));
+    vTaskDelay(pdMS_TO_TICKS(100));
+    printf("stop timer on full\r\n");
+    TEST_ESP_OK(mcpwm_timer_start_stop(timer, MCPWM_TIMER_STOP_FULL));
+    vTaskDelay(pdMS_TO_TICKS(100));
+    TEST_ASSERT_EQUAL(1, gpio_get_level(generator_gpio));
+
+    printf("delete timer, operator, generator\r\n");
+    TEST_ESP_OK(mcpwm_timer_disable(timer));
+    TEST_ESP_OK(mcpwm_del_generator(gen));
+    TEST_ESP_OK(mcpwm_del_operator(oper));
+    TEST_ESP_OK(mcpwm_del_timer(timer));
+    TEST_ESP_OK(gpio_reset_pin(generator_gpio));
+}
+
+TEST_CASE("mcpwm_timer_sleep_retention", "[mcpwm]")
+{
+    test_mcpwm_timer_sleep_retention(false);
+#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    test_mcpwm_timer_sleep_retention(true);
+#endif
+}
+
+TEST_MCPWM_CALLBACK_ATTR
+static bool test_capture_callback(mcpwm_cap_channel_handle_t cap_channel, const mcpwm_capture_event_data_t *edata, void *user_data)
+{
+    uint32_t *cap_value = (uint32_t *)user_data;
+    if (edata->cap_edge == MCPWM_CAP_EDGE_NEG) {
+        cap_value[1] = edata->cap_value;
+    } else {
+        cap_value[0] = edata->cap_value;
+    }
+    return false;
+}
+
+/**
+ * @brief Test the MCPWM capture timer can still work after light sleep
+ *
+ * @param allow_pd Whether to allow power down the peripheral in light sleep
+ */
+static void test_mcpwm_capture_timer_sleep_retention(bool allow_pd)
+{
+    const int cap_gpio = TEST_CAP_GPIO;
+    printf("init a gpio to simulate the external capture signal\r\n");
+    gpio_config_t gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT(cap_gpio),
+    };
+    TEST_ESP_OK(gpio_config(&gpio_conf));
+    // reset the gpio
+    TEST_ESP_OK(gpio_set_level(cap_gpio, 0));
+    // install mcpwm capture timer
+    mcpwm_cap_timer_handle_t cap_timer = NULL;
+    uint32_t clk_src_freq_hz;
+    esp_clk_tree_src_get_freq_hz(MCPWM_CAPTURE_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
+    mcpwm_capture_timer_config_t cap_timer_config = {
+        .clk_src = MCPWM_CAPTURE_CLK_SRC_DEFAULT,
+        .group_id = 0,
+        .resolution_hz = clk_src_freq_hz / 2,
+        .flags.allow_pd = allow_pd,
+    };
+    TEST_ESP_OK(mcpwm_new_capture_timer(&cap_timer_config, &cap_timer));
+    // install mcpwm capture channel
+    mcpwm_cap_channel_handle_t cap_channel;
+    mcpwm_capture_channel_config_t cap_chan_config = {
+        .gpio_num = cap_gpio,
+        .prescale = 1,
+        .flags.pos_edge = true,
+        .flags.neg_edge = true,
+    };
+    TEST_ESP_OK(mcpwm_new_capture_channel(cap_timer, &cap_chan_config, &cap_channel));
+
+    // install callback for capture channel
+    mcpwm_capture_event_callbacks_t cbs = {
+        .on_cap = test_capture_callback,
+    };
+    uint32_t cap_value[2] = {0};
+    TEST_ESP_OK(mcpwm_capture_channel_register_event_callbacks(cap_channel, &cbs, cap_value));
+
+    // go to sleep
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+    printf("go to light sleep for 1 seconds\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
+    TEST_ESP_OK(esp_light_sleep_start());
+
+    printf("Waked up! Let's see if MCPWM driver can still work...\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+
+    printf("check if the sleep happened as expected\r\n");
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL(allow_pd ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+    esp_sleep_set_sleep_context(NULL);
+
+    printf("enable capture\r\n");
+    TEST_ESP_OK(mcpwm_capture_channel_enable(cap_channel));
+    TEST_ESP_OK(mcpwm_capture_timer_enable(cap_timer));
+
+    printf("simulate GPIO capture signal\r\n");
+    TEST_ESP_OK(mcpwm_capture_timer_start(cap_timer));
+    TEST_ESP_OK(gpio_set_level(cap_gpio, 1));
+    esp_rom_delay_us(10 * 1000);
+    TEST_ESP_OK(gpio_set_level(cap_gpio, 0));
+
+    uint32_t clk_src_res;
+    TEST_ESP_OK(mcpwm_capture_timer_get_resolution(cap_timer, &clk_src_res));
+    clk_src_res /= 1000; // convert to kHz
+    uint32_t capture_value = (cap_value[1] - cap_value[0]) * 1000 / clk_src_res;
+    TEST_ASSERT_UINT_WITHIN(1000, 10000, capture_value);
+
+    printf("delete timer, operator, generator\r\n");
+    TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel));
+    TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel));
+    TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer));
+    TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer));
+    TEST_ESP_OK(gpio_reset_pin(cap_gpio));
+}
+
+TEST_CASE("mcpwm_capture_timer_sleep_retention", "[mcpwm]")
+{
+    test_mcpwm_capture_timer_sleep_retention(false);
+#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    test_mcpwm_capture_timer_sleep_retention(true);
+#endif
+}
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c
index 7fb5328cfad..d8bc8e4aaf7 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sync.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -106,6 +106,13 @@ TEST_CASE("mcpwm_gpio_sync_timer_phase_lock", "[mcpwm]")
     //   |
     //   v
     // timer0-->timer1-->timer2
+    const int gpio_num = TEST_SYNC_GPIO;
+    gpio_config_t sync_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT(gpio_num),
+    };
+    TEST_ESP_OK(gpio_config(&sync_gpio_conf));
+
     mcpwm_timer_config_t timer_config = {
         .clk_src = MCPWM_TIMER_CLK_SRC_DEFAULT,
         .group_id = 0,
@@ -127,11 +134,9 @@ TEST_CASE("mcpwm_gpio_sync_timer_phase_lock", "[mcpwm]")
         .direction = MCPWM_TIMER_DIRECTION_UP,
     };
     mcpwm_sync_handle_t gpio_sync_src;
-    const int gpio_num = TEST_SYNC_GPIO;
     mcpwm_gpio_sync_src_config_t gpio_sync_config = {
         .group_id = 0,
         .gpio_num = gpio_num,
-        .flags.io_loop_back = true, // so that we can use gpio driver to simulate the sync signal
         .flags.pull_down = true, // internally pull down
     };
     TEST_ESP_OK(mcpwm_new_gpio_sync_src(&gpio_sync_config, &gpio_sync_src));
@@ -154,6 +159,7 @@ TEST_CASE("mcpwm_gpio_sync_timer_phase_lock", "[mcpwm]")
         TEST_ESP_OK(mcpwm_del_sync_src(sync_srcs[i]));
         TEST_ESP_OK(mcpwm_del_timer(timers[i]));
     }
+    TEST_ESP_OK(gpio_reset_pin(gpio_num));
 }
 
 TEST_CASE("mcpwm_timer_sync_timer_phase_lock", "[mcpwm]")
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.ci.release b/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.ci.release
index 91d93f163e6..17aaee1e8ec 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.ci.release
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.ci.release
@@ -1,5 +1,6 @@
 CONFIG_PM_ENABLE=y
 CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
 CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
diff --git a/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.defaults b/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.defaults
index 8e326e32e18..d7d65b16651 100644
--- a/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.defaults
+++ b/components/esp_driver_mcpwm/test_apps/mcpwm/sdkconfig.defaults
@@ -1,2 +1,5 @@
 CONFIG_FREERTOS_HZ=1000
 CONFIG_ESP_TASK_WDT_INIT=n
+
+# primitives for checking sleep internal state
+CONFIG_ESP_SLEEP_DEBUG=y
diff --git a/components/esp_driver_parlio/include/driver/parlio_rx.h b/components/esp_driver_parlio/include/driver/parlio_rx.h
index 400b10beabe..9774d871b40 100644
--- a/components/esp_driver_parlio/include/driver/parlio_rx.h
+++ b/components/esp_driver_parlio/include/driver/parlio_rx.h
@@ -40,8 +40,10 @@ typedef struct {
                                                          the output clock will be controlled by the valid gpio,
                                                          i.e. high level of valid gpio to enable the clock output, low to disable */
         uint32_t            io_loop_back: 1;        /*!< For debug/test, the signal output from the GPIO will be fed to the input path as well */
-        uint32_t            io_no_init: 1;          /*!< Set to skip initializing the GPIO, but only attach the pralio rx signals to those GPIOs via IO Matrix.
-                                                         So that the signals that have attached to those GPIO won't be overwritten. Mainly used for self communication or self monitoring */
+        uint32_t            io_no_init: 1 __attribute__((deprecated)); /*!< Deprecated. Driver won't change the GPIO configuration in inilization. */
+        uint32_t            allow_pd: 1;             /*!< Set to allow power down. When this flag set, the driver will backup/restore the PARLIO registers before/after entering/exist sleep mode.
+                                                         By this approach, the system can power off PARLIO's power domain.
+                                                         This can save power, but at the expense of more RAM being consumed. */
     } flags;                                        /*!< RX driver flags */
 } parlio_rx_unit_config_t;
 
diff --git a/components/esp_driver_parlio/include/driver/parlio_tx.h b/components/esp_driver_parlio/include/driver/parlio_tx.h
index b2cb66a2436..0bd9442ced6 100644
--- a/components/esp_driver_parlio/include/driver/parlio_tx.h
+++ b/components/esp_driver_parlio/include/driver/parlio_tx.h
@@ -40,6 +40,9 @@ typedef struct {
                                        the output clock will be controlled by the MSB bit of the data bus,
                                        i.e. by data_gpio_nums[PARLIO_TX_UNIT_MAX_DATA_WIDTH-1]. High level to enable the clock output, low to disable */
         uint32_t io_loop_back: 1; /*!< For debug/test, the signal output from the GPIO will be fed to the input path as well */
+        uint32_t allow_pd: 1;      /*!< Set to allow power down. When this flag set, the driver will backup/restore the PARLIO registers before/after entering/exist sleep mode.
+                                       By this approach, the system can power off PARLIO's power domain.
+                                       This can save power, but at the expense of more RAM being consumed. */
     } flags;                      /*!< Extra configuration flags */
 } parlio_tx_unit_config_t;
 
diff --git a/components/esp_driver_parlio/src/parlio_common.c b/components/esp_driver_parlio/src/parlio_common.c
index 48518ddb0cc..585cea006f5 100644
--- a/components/esp_driver_parlio/src/parlio_common.c
+++ b/components/esp_driver_parlio/src/parlio_common.c
@@ -18,6 +18,7 @@
 #include "soc/parlio_periph.h"
 #include "hal/parlio_ll.h"
 #include "esp_private/esp_clk.h"
+#include "esp_private/sleep_retention.h"
 #include "parlio_private.h"
 
 static const char *TAG = "parlio";
@@ -46,6 +47,23 @@ parlio_group_t *parlio_acquire_group_handle(int group_id)
                 parlio_ll_enable_bus_clock(group_id, true);
                 parlio_ll_reset_register(group_id);
             }
+#if PARLIO_USE_RETENTION_LINK
+            sleep_retention_module_t module_id = parlio_reg_retention_info[group_id].retention_module;
+            sleep_retention_module_init_param_t init_param = {
+                .cbs = {
+                    .create = {
+                        .handle = parlio_create_sleep_retention_link_cb,
+                        .arg = group,
+                    },
+                },
+                .depends = SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM
+            };
+            // we only do retention init here. Allocate retention module in the unit initialization
+            if (sleep_retention_module_init(module_id, &init_param) != ESP_OK) {
+                // even though the sleep retention module init failed, PARLIO driver should still work, so just warning here
+                ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id);
+            }
+#endif // PARLIO_USE_RETENTION_LINK
             // hal layer initialize
             parlio_hal_init(&group->hal);
             group->dma_align = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
@@ -87,6 +105,16 @@ void parlio_release_group_handle(parlio_group_t *group)
     _lock_release(&s_platform.mutex);
 
     if (do_deinitialize) {
+#if PARLIO_USE_RETENTION_LINK
+        const periph_retention_module_t module_id = parlio_reg_retention_info[group_id].retention_module;
+        if (sleep_retention_get_created_modules() & BIT(module_id)) {
+            assert(sleep_retention_get_inited_modules() & BIT(module_id));
+            sleep_retention_module_free(module_id);
+        }
+        if (sleep_retention_get_inited_modules() & BIT(module_id)) {
+            sleep_retention_module_deinit(module_id);
+        }
+#endif // PARLIO_USE_RETENTION_LINK
         free(group);
         ESP_LOGD(TAG, "del group(%d)", group_id);
     }
@@ -147,3 +175,32 @@ void parlio_unregister_unit_from_group(parlio_unit_base_handle_t unit)
     /* the parlio unit has a reference of the group, release it now */
     parlio_release_group_handle(group);
 }
+
+#if PARLIO_USE_RETENTION_LINK
+esp_err_t parlio_create_sleep_retention_link_cb(void *arg)
+{
+    parlio_group_t *group = (parlio_group_t *)arg;
+    int group_id = group->group_id;
+    sleep_retention_module_t module_id = parlio_reg_retention_info[group_id].retention_module;
+    esp_err_t err = sleep_retention_entries_create(parlio_reg_retention_info[group_id].regdma_entry_array,
+                                                   parlio_reg_retention_info[group_id].array_size,
+                                                   REGDMA_LINK_PRI_PARLIO, module_id);
+    ESP_RETURN_ON_ERROR(err, TAG, "create retention link failed");
+    return ESP_OK;
+}
+
+void parlio_create_retention_module(parlio_group_t *group)
+{
+    int group_id = group->group_id;
+    sleep_retention_module_t module_id = parlio_reg_retention_info[group_id].retention_module;
+
+    _lock_acquire(&s_platform.mutex);
+    if ((sleep_retention_get_inited_modules() & BIT(module_id)) && !(sleep_retention_get_created_modules() & BIT(module_id))) {
+        if (sleep_retention_module_allocate(module_id) != ESP_OK) {
+            // even though the sleep retention module create failed, PARLIO driver should still work, so just warning here
+            ESP_LOGW(TAG, "create retention module failed, power domain can't turn off");
+        }
+    }
+    _lock_release(&s_platform.mutex);
+}
+#endif // PARLIO_USE_RETENTION_LINK
diff --git a/components/esp_driver_parlio/src/parlio_private.h b/components/esp_driver_parlio/src/parlio_private.h
index d728359b09e..b76ec8ba834 100644
--- a/components/esp_driver_parlio/src/parlio_private.h
+++ b/components/esp_driver_parlio/src/parlio_private.h
@@ -24,6 +24,7 @@
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/esp_gpio_reserve.h"
 #include "esp_private/gpio.h"
+#include "esp_private/sleep_retention.h"
 
 #if CONFIG_PARLIO_ISR_IRAM_SAFE
 #define PARLIO_MEM_ALLOC_CAPS    (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
@@ -44,6 +45,9 @@
 #define PARLIO_INTR_ALLOC_FLAG   (ESP_INTR_FLAG_LOWMED | PARLIO_INTR_ALLOC_FLAG_SHARED)
 #endif
 
+// Use retention link only when the target supports sleep retention is enabled
+#define PARLIO_USE_RETENTION_LINK  (SOC_PARLIO_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+
 #if defined(SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS) // Parlio uses GDMA
 #if defined(SOC_GDMA_BUS_AHB) && (SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS == SOC_GDMA_BUS_AHB)
 typedef dma_descriptor_align4_t     parlio_dma_desc_t;
@@ -149,6 +153,11 @@ esp_err_t parlio_register_unit_to_group(parlio_unit_base_handle_t unit);
  */
 void parlio_unregister_unit_from_group(parlio_unit_base_handle_t unit);
 
+#if PARLIO_USE_RETENTION_LINK
+esp_err_t parlio_create_sleep_retention_link_cb(void *arg);
+void parlio_create_retention_module(parlio_group_t *group);
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_parlio/src/parlio_rx.c b/components/esp_driver_parlio/src/parlio_rx.c
index 411ed2aea0d..97acef19734 100644
--- a/components/esp_driver_parlio/src/parlio_rx.c
+++ b/components/esp_driver_parlio/src/parlio_rx.c
@@ -25,7 +25,6 @@
 #include "soc/parlio_periph.h"
 #include "soc/soc_caps.h"
 #include "hal/parlio_ll.h"
-#include "hal/gpio_hal.h"
 #include "hal/dma_types.h"
 #include "hal/hal_utils.h"
 #include "driver/gpio.h"
@@ -252,24 +251,19 @@ static esp_err_t s_parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, cons
 {
     int group_id = rx_unit->base.group->group_id;
     int unit_id = rx_unit->base.unit_id;
-    /* Default GPIO configuration */
-    gpio_config_t gpio_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        .pull_down_en = false,
-        .pull_up_en = true,
-    };
 
     /* When the source clock comes from external, enable the gpio input direction and connect to the clock input signal */
     if (config->clk_src == PARLIO_CLK_SRC_EXTERNAL) {
         ESP_RETURN_ON_FALSE(config->clk_in_gpio_num >= 0, ESP_ERR_INVALID_ARG, TAG, "clk_in_gpio_num must be set while the clock input from external");
         /* Connect the clock in signal to the GPIO matrix if it is set */
-        if (!config->flags.io_no_init) {
-            gpio_conf.mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_INPUT;
-            gpio_conf.pin_bit_mask = BIT64(config->clk_in_gpio_num);
-            ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config clk in GPIO failed");
-        } else {
-            gpio_ll_input_enable(&GPIO, config->clk_in_gpio_num);
+        gpio_func_sel(config->clk_in_gpio_num, PIN_FUNC_GPIO);
+        gpio_input_enable(config->clk_in_gpio_num);
+
+        // deprecated, to be removed in in esp-idf v6.0
+        if (config->flags.io_loop_back) {
+            gpio_output_enable(config->clk_in_gpio_num);
         }
+
         esp_rom_gpio_connect_in_signal(config->clk_in_gpio_num,
                                        parlio_periph_signals.groups[group_id].rx_units[unit_id].clk_in_sig, false);
     }
@@ -277,9 +271,14 @@ static esp_err_t s_parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, cons
      * enable the gpio output direction and connect to the clock output signal */
     if (config->clk_out_gpio_num >= 0) {
 #if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
-        gpio_conf.mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_OUTPUT;
-        gpio_conf.pin_bit_mask = BIT64(config->clk_out_gpio_num);
-        ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config clk out GPIO failed");
+        gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO);
+
+        // deprecated, to be removed in in esp-idf v6.0
+        if (config->flags.io_loop_back) {
+            gpio_input_enable(config->clk_out_gpio_num);
+        }
+
+        // connect the signal to the GPIO by matrix, it will also enable the output path properly
         esp_rom_gpio_connect_out_signal(config->clk_out_gpio_num,
                                         parlio_periph_signals.groups[group_id].rx_units[unit_id].clk_out_sig, false, false);
 #else
@@ -287,15 +286,16 @@ static esp_err_t s_parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, cons
 #endif // SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
     }
 
-    gpio_conf.mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_INPUT;
     /* Initialize the valid GPIO as input */
     if (config->valid_gpio_num >= 0) {
-        if (!config->flags.io_no_init) {
-            gpio_conf.pin_bit_mask = BIT64(config->valid_gpio_num);
-            ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config data GPIO failed");
-        } else {
-            gpio_ll_input_enable(&GPIO, config->valid_gpio_num);
+        gpio_func_sel(config->valid_gpio_num, PIN_FUNC_GPIO);
+        gpio_input_enable(config->valid_gpio_num);
+
+        // deprecated, to be removed in in esp-idf v6.0
+        if (config->flags.io_loop_back) {
+            gpio_output_enable(config->valid_gpio_num);
         }
+
         /* Not connect the signal here, the signal is lazy connected until the delimiter takes effect */
     }
 
@@ -303,12 +303,14 @@ static esp_err_t s_parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, cons
     for (int i = 0; i < config->data_width; i++) {
         /* Loop the data_gpio_nums to connect data and valid signals via GPIO matrix */
         if (config->data_gpio_nums[i] >= 0) {
-            if (!config->flags.io_no_init) {
-                gpio_conf.pin_bit_mask = BIT64(config->data_gpio_nums[i]);
-                ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config data GPIO failed");
-            } else {
-                gpio_ll_input_enable(&GPIO, config->data_gpio_nums[i]);
+            gpio_func_sel(config->data_gpio_nums[i], PIN_FUNC_GPIO);
+            gpio_input_enable(config->data_gpio_nums[i]);
+
+            // deprecated, to be removed in in esp-idf v6.0
+            if (config->flags.io_loop_back) {
+                gpio_output_enable(config->data_gpio_nums[i]);
             }
+
             esp_rom_gpio_connect_in_signal(config->data_gpio_nums[i],
                                            parlio_periph_signals.groups[group_id].rx_units[unit_id].data_sigs[i], false);
         } else {
@@ -618,6 +620,10 @@ esp_err_t parlio_new_rx_unit(const parlio_rx_unit_config_t *config, parlio_rx_un
     esp_err_t ret = ESP_OK;
     parlio_rx_unit_handle_t unit = NULL;
 
+#if !SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "register back up is not supported");
+#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+
     /* Allocate unit memory */
     unit = heap_caps_calloc(1, sizeof(parlio_rx_unit_t), PARLIO_MEM_ALLOC_CAPS);
     ESP_GOTO_ON_FALSE(unit, ESP_ERR_NO_MEM, err, TAG, "no memory for rx unit");
@@ -674,6 +680,12 @@ esp_err_t parlio_new_rx_unit(const parlio_rx_unit_config_t *config, parlio_rx_un
     }
 #endif  // SOC_PARLIO_RX_CLK_SUPPORT_GATING
 
+#if PARLIO_USE_RETENTION_LINK
+    if (config->flags.allow_pd != 0) {
+        parlio_create_retention_module(group);
+    }
+#endif // PARLIO_USE_RETENTION_LINK
+
     /* return RX unit handle */
     *ret_unit = unit;
 
diff --git a/components/esp_driver_parlio/src/parlio_tx.c b/components/esp_driver_parlio/src/parlio_tx.c
index dcf073ed264..b7493b73cb8 100644
--- a/components/esp_driver_parlio/src/parlio_tx.c
+++ b/components/esp_driver_parlio/src/parlio_tx.c
@@ -138,46 +138,59 @@ static esp_err_t parlio_tx_unit_configure_gpio(parlio_tx_unit_t *tx_unit, const
 {
     int group_id = tx_unit->base.group->group_id;
     int unit_id = tx_unit->base.unit_id;
-    gpio_config_t gpio_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        .mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_OUTPUT,
-        .pull_down_en = false,
-        .pull_up_en = true,
-    };
 
     // connect peripheral signals via GPIO matrix
     for (size_t i = 0; i < config->data_width; i++) {
         if (config->data_gpio_nums[i] >= 0) {
-            gpio_conf.pin_bit_mask = BIT64(config->data_gpio_nums[i]);
-            ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config data GPIO failed");
+            gpio_func_sel(config->data_gpio_nums[i], PIN_FUNC_GPIO);
+
+            // deprecated, to be removed in in esp-idf v6.0
+            if (config->flags.io_loop_back) {
+                gpio_input_enable(config->data_gpio_nums[i]);
+            }
+
+            // connect the signal to the GPIO by matrix, it will also enable the output path properly
             esp_rom_gpio_connect_out_signal(config->data_gpio_nums[i],
                                             parlio_periph_signals.groups[group_id].tx_units[unit_id].data_sigs[i], false, false);
-            gpio_func_sel(config->data_gpio_nums[i], PIN_FUNC_GPIO);
         }
     }
     // Note: the valid signal will override TXD[PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG]
     if (config->valid_gpio_num >= 0) {
-        gpio_conf.pin_bit_mask = BIT64(config->valid_gpio_num);
-        ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config valid GPIO failed");
+        gpio_func_sel(config->valid_gpio_num, PIN_FUNC_GPIO);
+
+        // deprecated, to be removed in in esp-idf v6.0
+        if (config->flags.io_loop_back) {
+            gpio_input_enable(config->valid_gpio_num);
+        }
+
+        // connect the signal to the GPIO by matrix, it will also enable the output path properly
         esp_rom_gpio_connect_out_signal(config->valid_gpio_num,
                                         parlio_periph_signals.groups[group_id].tx_units[unit_id].data_sigs[PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG],
                                         false, false);
-        gpio_func_sel(config->valid_gpio_num, PIN_FUNC_GPIO);
     }
     if (config->clk_out_gpio_num >= 0) {
-        gpio_conf.pin_bit_mask = BIT64(config->clk_out_gpio_num);
-        ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config clk out GPIO failed");
+        gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO);
+
+        // deprecated, to be removed in in esp-idf v6.0
+        if (config->flags.io_loop_back) {
+            gpio_input_enable(config->clk_out_gpio_num);
+        }
+
+        // connect the signal to the GPIO by matrix, it will also enable the output path properly
         esp_rom_gpio_connect_out_signal(config->clk_out_gpio_num,
                                         parlio_periph_signals.groups[group_id].tx_units[unit_id].clk_out_sig, false, false);
-        gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO);
     }
     if (config->clk_in_gpio_num >= 0) {
-        gpio_conf.mode = config->flags.io_loop_back ? GPIO_MODE_INPUT_OUTPUT : GPIO_MODE_INPUT;
-        gpio_conf.pin_bit_mask = BIT64(config->clk_in_gpio_num);
-        ESP_RETURN_ON_ERROR(gpio_config(&gpio_conf), TAG, "config clk in GPIO failed");
+        gpio_func_sel(config->clk_in_gpio_num, PIN_FUNC_GPIO);
+        gpio_input_enable(config->clk_in_gpio_num);
+
+        // deprecated, to be removed in in esp-idf v6.0
+        if (config->flags.io_loop_back) {
+            gpio_output_enable(config->clk_in_gpio_num);
+        }
+
         esp_rom_gpio_connect_in_signal(config->clk_in_gpio_num,
                                        parlio_periph_signals.groups[group_id].tx_units[unit_id].clk_in_sig, false);
-        gpio_func_sel(config->clk_in_gpio_num, PIN_FUNC_GPIO);
     }
     return ESP_OK;
 }
@@ -257,7 +270,7 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par
 #endif
     esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
     PARLIO_CLOCK_SRC_ATOMIC() {
-        // turn on the tx module clock to sync the register configuration to the module
+        // turn on the tx module clock to sync the clock divider configuration because of the CDC (Cross Domain Crossing)
         parlio_ll_tx_enable_clock(hal->regs, true);
         parlio_ll_tx_set_clock_source(hal->regs, clk_src);
         // set clock division
@@ -296,6 +309,10 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
     ESP_RETURN_ON_FALSE(config->flags.clk_gate_en == 0, ESP_ERR_NOT_SUPPORTED, TAG, "clock gating is not supported");
 #endif // SOC_PARLIO_TX_CLK_SUPPORT_GATING
 
+#if !SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "register back up is not supported");
+#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+
     // malloc unit memory
     uint32_t mem_caps = PARLIO_MEM_ALLOC_CAPS;
     unit = heap_caps_calloc(1, sizeof(parlio_tx_unit_t) + sizeof(parlio_tx_trans_desc_t) * config->trans_queue_depth, mem_caps);
@@ -368,6 +385,12 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un
     // GPIO Matrix/MUX configuration
     ESP_GOTO_ON_ERROR(parlio_tx_unit_configure_gpio(unit, config), err, TAG, "configure gpio failed");
 
+#if PARLIO_USE_RETENTION_LINK
+    if (config->flags.allow_pd != 0) {
+        parlio_create_retention_module(group);
+    }
+#endif // PARLIO_USE_RETENTION_LINK
+
     portMUX_INITIALIZE(&unit->spinlock);
     atomic_init(&unit->fsm, PARLIO_TX_FSM_INIT);
     // return TX unit handle
@@ -455,13 +478,11 @@ static void IRAM_ATTR parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio
     while (parlio_ll_tx_is_ready(hal->regs) == false);
     // turn on the core clock after we start the TX unit
     parlio_ll_tx_start(hal->regs, true);
-    PARLIO_CLOCK_SRC_ATOMIC() {
-        parlio_ll_tx_enable_clock(hal->regs, true);
-    }
 }
 
 esp_err_t parlio_tx_unit_enable(parlio_tx_unit_handle_t tx_unit)
 {
+    parlio_hal_context_t *hal = &tx_unit->base.group->hal;
     ESP_RETURN_ON_FALSE(tx_unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     parlio_tx_fsm_t expected_fsm = PARLIO_TX_FSM_INIT;
     if (atomic_compare_exchange_strong(&tx_unit->fsm, &expected_fsm, PARLIO_TX_FSM_ENABLE_WAIT)) {
@@ -476,6 +497,11 @@ esp_err_t parlio_tx_unit_enable(parlio_tx_unit_handle_t tx_unit)
         ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_STATE, TAG, "unit not in init state");
     }
 
+    // enable clock output
+    PARLIO_CLOCK_SRC_ATOMIC() {
+        parlio_ll_tx_enable_clock(hal->regs, true);
+    }
+
     // check if we need to start one pending transaction
     parlio_tx_trans_desc_t *t = NULL;
     expected_fsm = PARLIO_TX_FSM_ENABLE;
@@ -518,6 +544,10 @@ esp_err_t parlio_tx_unit_disable(parlio_tx_unit_handle_t tx_unit)
 
     // stop the TX engine
     parlio_hal_context_t *hal = &tx_unit->base.group->hal;
+    // disable clock output
+    PARLIO_CLOCK_SRC_ATOMIC() {
+        parlio_ll_tx_enable_clock(hal->regs, false);
+    }
     gdma_stop(tx_unit->dma_chan);
     parlio_ll_tx_start(hal->regs, false);
     parlio_ll_enable_interrupt(hal->regs, PARLIO_LL_EVENT_TX_EOF, false);
@@ -608,9 +638,6 @@ static void IRAM_ATTR parlio_tx_default_isr(void *args)
 
     if (status & PARLIO_LL_EVENT_TX_EOF) {
         parlio_ll_clear_interrupt_status(hal->regs, PARLIO_LL_EVENT_TX_EOF);
-        PARLIO_CLOCK_SRC_ATOMIC() {
-            parlio_ll_tx_enable_clock(hal->regs, false);
-        }
         parlio_ll_tx_start(hal->regs, false);
 
         parlio_tx_trans_desc_t *trans_desc = NULL;
diff --git a/components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt b/components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt
index 3ee6db54cec..6d465c10d47 100644
--- a/components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt
+++ b/components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt
@@ -7,6 +7,10 @@ if(CONFIG_PARLIO_ISR_IRAM_SAFE)
     list(REMOVE_ITEM srcs "test_parlio_rx.c")
 endif()
 
+if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED AND CONFIG_PM_ENABLE)
+    list(APPEND srcs "test_parlio_sleep.c")
+endif()
+
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_board.h b/components/esp_driver_parlio/test_apps/parlio/main/test_board.h
index da22296e39d..36c4931acb9 100644
--- a/components/esp_driver_parlio/test_apps/parlio/main/test_board.h
+++ b/components/esp_driver_parlio/test_apps/parlio/main/test_board.h
@@ -56,14 +56,14 @@ extern "C" {
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define TEST_CLK_GPIO       33
 #define TEST_VALID_GPIO     36
-#define TEST_DATA0_GPIO     20
-#define TEST_DATA1_GPIO     21
-#define TEST_DATA2_GPIO     22
-#define TEST_DATA3_GPIO     23
-#define TEST_DATA4_GPIO     45
-#define TEST_DATA5_GPIO     46
-#define TEST_DATA6_GPIO     47
-#define TEST_DATA7_GPIO     48
+#define TEST_DATA0_GPIO     0
+#define TEST_DATA1_GPIO     1
+#define TEST_DATA2_GPIO     2
+#define TEST_DATA3_GPIO     3
+#define TEST_DATA4_GPIO     4
+#define TEST_DATA5_GPIO     5
+#define TEST_DATA6_GPIO     6
+#define TEST_DATA7_GPIO     7
 #else
 #error "Unsupported target"
 #endif
diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
index cf5f0befcb2..cc454aa7b44 100644
--- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
+++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
@@ -52,7 +52,6 @@
     },  \
     .flags = {  \
         .clk_gate_en = false,  \
-        .io_loop_back = true,  \
     } \
 }
 
@@ -369,7 +368,7 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
 {
     parlio_rx_pulse_delimiter_config_t pls_deli_cfg = {
         .valid_sig_line_id = TEST_VALID_SIG,
-        .sample_edge = PARLIO_SAMPLE_EDGE_POS,
+        .sample_edge = PARLIO_SAMPLE_EDGE_NEG,
         .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
         .eof_data_len = TEST_EOF_DATA_LEN,
         .timeout_ticks = 0,
@@ -528,6 +527,13 @@ TEST_CASE("parallel_rx_unit_receive_transaction_test", "[parlio_rx]")
 
 TEST_CASE("parallel_rx_unit_receive_timeout_test", "[parlio_rx]")
 {
+    printf("init a gpio to simulate valid signal\r\n");
+    gpio_config_t test_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT64(TEST_VALID_GPIO),
+    };
+    TEST_ESP_OK(gpio_config(&test_gpio_conf));
+
     parlio_rx_unit_handle_t rx_unit = NULL;
     parlio_rx_delimiter_handle_t timeout_deli = NULL;
 
@@ -583,5 +589,6 @@ TEST_CASE("parallel_rx_unit_receive_timeout_test", "[parlio_rx]")
     TEST_ESP_OK(parlio_rx_unit_disable(rx_unit));
     TEST_ESP_OK(parlio_del_rx_delimiter(timeout_deli));
     TEST_ESP_OK(parlio_del_rx_unit(rx_unit));
+    TEST_ESP_OK(gpio_reset_pin(TEST_VALID_GPIO));
     free(payload);
 }
diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c
new file mode 100644
index 00000000000..047a19ca4c7
--- /dev/null
+++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c
@@ -0,0 +1,168 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "unity.h"
+#include "driver/parlio_tx.h"
+#include "driver/parlio_rx.h"
+#include "driver/gpio.h"
+#include "soc/soc_caps.h"
+#include "soc/parl_io_struct.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/esp_pmu.h"
+#include "esp_attr.h"
+#include "test_board.h"
+
+TEST_PARLIO_CALLBACK_ATTR
+static bool test_parlio_rx_done_callback(parlio_rx_unit_handle_t rx_unit, const parlio_rx_event_data_t *edata, void *user_ctx)
+{
+    BaseType_t high_task_wakeup = pdFALSE;
+    TaskHandle_t task = (TaskHandle_t)user_ctx;
+    vTaskNotifyGiveFromISR(task, &high_task_wakeup);
+    return high_task_wakeup == pdTRUE;
+}
+
+#define TEST_PAYLOAD_SIZE  64
+static void test_parlio_sleep_retention(bool allow_pd)
+{
+    printf("install parlio tx unit\r\n");
+    parlio_tx_unit_handle_t tx_unit = NULL;
+    parlio_tx_unit_config_t tx_config = {
+        .clk_src = PARLIO_CLK_SRC_DEFAULT,
+        .data_width = 4,
+        .clk_in_gpio_num = -1,  // use internal clock source
+        .valid_gpio_num = TEST_VALID_GPIO,
+        .clk_out_gpio_num = TEST_CLK_GPIO,
+        .data_gpio_nums = {
+            TEST_DATA0_GPIO,
+            TEST_DATA1_GPIO,
+            TEST_DATA2_GPIO,
+            TEST_DATA3_GPIO,
+        },
+        .output_clk_freq_hz = 1 * 1000 * 1000,
+        .trans_queue_depth = 8,
+        .max_transfer_size = 128,
+        .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
+        .sample_edge = PARLIO_SAMPLE_EDGE_POS,
+        .flags.allow_pd = allow_pd,
+    };
+    TEST_ESP_OK(parlio_new_tx_unit(&tx_config, &tx_unit));
+
+    printf("send packets and check event is fired\r\n");
+    parlio_transmit_config_t transmit_config = {
+        .idle_value = 0x00,
+    };
+    uint8_t tx_payload[TEST_PAYLOAD_SIZE] = {0};
+    for (int i = 0; i < TEST_PAYLOAD_SIZE; i++) {
+        tx_payload[i] = i;
+    }
+
+    printf("install parlio rx unit\r\n");
+    parlio_rx_unit_handle_t rx_unit = NULL;
+    parlio_rx_delimiter_handle_t deli = NULL;
+
+    parlio_rx_unit_config_t rx_config = {
+        .trans_queue_depth = 10,
+        .max_recv_size = 1024,
+        .data_width = 4,
+        .clk_src = PARLIO_CLK_SRC_DEFAULT,
+        .ext_clk_freq_hz =  0,
+        .clk_in_gpio_num =  -1,
+        .exp_clk_freq_hz = 1 * 1000 * 1000,
+        .clk_out_gpio_num = -1,
+        .valid_gpio_num = TEST_VALID_GPIO,
+        .data_gpio_nums = {
+            TEST_DATA0_GPIO,
+            TEST_DATA1_GPIO,
+            TEST_DATA2_GPIO,
+            TEST_DATA3_GPIO,
+        },
+        .flags = {
+            .clk_gate_en = false,
+            .allow_pd = allow_pd,
+        }
+    };
+    rx_config.flags.free_clk = 1;
+    TEST_ESP_OK(parlio_new_rx_unit(&rx_config, &rx_unit));
+
+    parlio_rx_level_delimiter_config_t lvl_deli_cfg = {
+        .valid_sig_line_id = PARLIO_RX_UNIT_MAX_DATA_WIDTH - 1,
+        .sample_edge = PARLIO_SAMPLE_EDGE_POS,
+        .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
+        .eof_data_len = TEST_PAYLOAD_SIZE,
+        .timeout_ticks = 0,
+        .flags = {
+            .active_low_en = 0,
+        },
+    };
+    TEST_ESP_OK(parlio_new_rx_level_delimiter(&lvl_deli_cfg, &deli));
+
+    printf("register receive_done event callback\r\n");
+    parlio_rx_event_callbacks_t rx_cbs = {
+        .on_receive_done = test_parlio_rx_done_callback,
+    };
+    TEST_ESP_OK(parlio_rx_unit_register_event_callbacks(rx_unit, &rx_cbs, xTaskGetCurrentTaskHandle()));
+
+    parlio_receive_config_t recv_config = {
+        .delimiter = deli,
+        .flags.partial_rx_en = false,
+    };
+    __attribute__((aligned(TEST_PAYLOAD_SIZE))) uint8_t rx_payload[TEST_PAYLOAD_SIZE] = {0};
+
+    // go to sleep
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+    printf("go to light sleep for 2 seconds\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
+    TEST_ESP_OK(esp_light_sleep_start());
+
+    printf("Waked up! Let's see if PARLIO driver can still work...\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+
+    printf("check if the sleep happened as expected\r\n");
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL(allow_pd ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+    esp_sleep_set_sleep_context(NULL);
+
+    printf("Testing tx and rx after sleep...\n");
+    TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
+    TEST_ESP_OK(parlio_rx_unit_enable(rx_unit, 1));
+    TEST_ESP_OK(parlio_rx_unit_receive(rx_unit, rx_payload, TEST_PAYLOAD_SIZE, &recv_config));
+    TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, tx_payload, TEST_PAYLOAD_SIZE * sizeof(uint8_t) * 8, &transmit_config));
+    TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000)));
+    for (int i = 0; i < TEST_PAYLOAD_SIZE; i++) {
+        printf("%.2d ", (rx_payload[i]));
+        TEST_ASSERT_EQUAL(tx_payload[i], rx_payload[i]);
+        if ((i + 1) % 16 == 0) {
+            printf("\n");
+        }
+    }
+    TEST_ESP_OK(parlio_tx_unit_disable(tx_unit));
+    TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
+    TEST_ESP_OK(parlio_rx_unit_disable(rx_unit));
+    TEST_ESP_OK(parlio_del_rx_delimiter(deli));
+    TEST_ESP_OK(parlio_del_rx_unit(rx_unit));
+}
+
+TEST_CASE("parlio light sleep", "[parlio]")
+{
+    test_parlio_sleep_retention(false);
+#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    test_parlio_sleep_retention(true);
+#endif
+}
diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c
index a1fd71d8883..a556c8a407a 100644
--- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c
+++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c
@@ -178,6 +178,13 @@ TEST_CASE("parallel_tx_unit_enable_disable", "[parlio_tx]")
 
 TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]")
 {
+    printf("init a gpio to read parlio_tx output\r\n");
+    gpio_config_t test_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT64(TEST_DATA0_GPIO),
+    };
+    TEST_ESP_OK(gpio_config(&test_gpio_conf));
+
     printf("install parlio tx unit\r\n");
     parlio_tx_unit_handle_t tx_unit = NULL;
     parlio_tx_unit_config_t config = {
@@ -201,7 +208,6 @@ TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]")
         .max_transfer_size = 64,
         .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
         .sample_edge = PARLIO_SAMPLE_EDGE_POS,
-        .flags.io_loop_back = 1,   // enable loop back by GPIO matrix, so that we can read the level of the data line by gpio driver
     };
     TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
     TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -224,11 +230,19 @@ TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]")
 
     TEST_ESP_OK(parlio_tx_unit_disable(tx_unit));
     TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
+    TEST_ESP_OK(gpio_reset_pin(TEST_DATA0_GPIO));
 }
 
 #if SOC_PARLIO_TX_CLK_SUPPORT_GATING
 TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]")
 {
+    printf("init a gpio to read parlio_tx clk output\r\n");
+    gpio_config_t test_gpio_conf = {
+        .mode = GPIO_MODE_INPUT,
+        .pin_bit_mask = BIT64(TEST_CLK_GPIO),
+    };
+    TEST_ESP_OK(gpio_config(&test_gpio_conf));
+
     printf("install parlio tx unit\r\n");
     parlio_tx_unit_handle_t tx_unit = NULL;
     parlio_tx_unit_config_t config = {
@@ -247,7 +261,6 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]")
         .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
         .sample_edge = PARLIO_SAMPLE_EDGE_POS,
         .flags.clk_gate_en = true, // enable clock gating, controlled by the level of TEST_DATA7_GPIO
-        .flags.io_loop_back = true, // for reading the level of the clock line in IDLE state
     };
     TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
     TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
@@ -272,5 +285,6 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]")
 
     TEST_ESP_OK(parlio_tx_unit_disable(tx_unit));
     TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
+    TEST_ESP_OK(gpio_reset_pin(TEST_CLK_GPIO));
 }
 #endif // SOC_PARLIO_TX_CLK_SUPPORT_GATING
diff --git a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release
index 91d93f163e6..17aaee1e8ec 100644
--- a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release
+++ b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.ci.release
@@ -1,5 +1,6 @@
 CONFIG_PM_ENABLE=y
 CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
 CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
diff --git a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults
index 448bb50f824..e8b3e421f0a 100644
--- a/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults
+++ b/components/esp_driver_parlio/test_apps/parlio/sdkconfig.defaults
@@ -3,3 +3,6 @@
 #
 CONFIG_ESP_TASK_WDT_INIT=n
 CONFIG_FREERTOS_HZ=1000
+
+# primitives for checking sleep internal state
+CONFIG_ESP_SLEEP_DEBUG=y
diff --git a/components/esp_driver_pcnt/src/pulse_cnt.c b/components/esp_driver_pcnt/src/pulse_cnt.c
index 5f50e39acff..6be76876c19 100644
--- a/components/esp_driver_pcnt/src/pulse_cnt.c
+++ b/components/esp_driver_pcnt/src/pulse_cnt.c
@@ -28,6 +28,7 @@
 #include "hal/gpio_hal.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/sleep_retention.h"
 #include "driver/gpio.h"
 #include "esp_private/gpio.h"
 #include "hal/gpio_ll.h" // for io_loop_back flag only
@@ -65,6 +66,13 @@ typedef struct pcnt_group_t pcnt_group_t;
 typedef struct pcnt_unit_t pcnt_unit_t;
 typedef struct pcnt_chan_t pcnt_chan_t;
 
+// Use retention link only when the target supports sleep retention
+#define PCNT_USE_RETENTION_LINK  (SOC_PCNT_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+
+#if PCNT_USE_RETENTION_LINK
+static esp_err_t pcnt_create_sleep_retention_link_cb(void *arg);
+#endif
+
 struct pcnt_platform_t {
     _lock_t mutex;                         // platform level mutex lock
     pcnt_group_t *groups[SOC_PCNT_GROUPS]; // pcnt group pool
@@ -246,6 +254,14 @@ esp_err_t pcnt_new_unit(const pcnt_unit_config_t *config, pcnt_unit_handle_t *re
                           TAG, "install interrupt service failed");
     }
 
+    // PCNT uses the APB as its function clock,
+    // and its filter module is sensitive to the clock frequency
+#if CONFIG_PM_ENABLE
+    sprintf(unit->pm_lock_name, "pcnt_%d_%d", group_id, unit_id); // e.g. pcnt_0_0
+    ESP_GOTO_ON_ERROR(esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, unit->pm_lock_name, &unit->pm_lock), err, TAG, "install pm lock failed");
+    ESP_LOGD(TAG, "install APB_FREQ_MAX lock for unit (%d,%d)", group_id, unit_id);
+#endif
+
     // some events are enabled by default, disable them all
     pcnt_ll_disable_all_events(group->hal.dev, unit_id);
     // disable filter by default
@@ -375,15 +391,6 @@ esp_err_t pcnt_unit_set_glitch_filter(pcnt_unit_handle_t unit, const pcnt_glitch
     if (config) {
         glitch_filter_thres = esp_clk_apb_freq() / 1000000 * config->max_glitch_ns / 1000;
         ESP_RETURN_ON_FALSE(glitch_filter_thres <= PCNT_LL_MAX_GLITCH_WIDTH, ESP_ERR_INVALID_ARG, TAG, "glitch width out of range");
-
-        // The filter module is working against APB clock, so lazy install PM lock
-#if CONFIG_PM_ENABLE
-        if (!unit->pm_lock) {
-            sprintf(unit->pm_lock_name, "pcnt_%d_%d", group->group_id, unit->unit_id); // e.g. pcnt_0_0
-            ESP_RETURN_ON_ERROR(esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, unit->pm_lock_name, &unit->pm_lock), TAG, "install pm lock failed");
-            ESP_LOGD(TAG, "install APB_FREQ_MAX lock for unit (%d,%d)", group->group_id, unit->unit_id);
-        }
-#endif
     }
 
     // filter control bit is mixed with other PCNT control bits in the same register
@@ -865,6 +872,23 @@ static pcnt_group_t *pcnt_acquire_group_handle(int group_id)
                 pcnt_ll_enable_bus_clock(group_id, true);
                 pcnt_ll_reset_register(group_id);
             }
+#if PCNT_USE_RETENTION_LINK
+            sleep_retention_module_t module_id = pcnt_reg_retention_info[group_id].retention_module;
+            sleep_retention_module_init_param_t init_param = {
+                .cbs = {
+                    .create = {
+                        .handle = pcnt_create_sleep_retention_link_cb,
+                        .arg = group,
+                    },
+                },
+                .depends = SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM
+            };
+            // we only do retention init here. Allocate retention module in the unit initialization
+            if (sleep_retention_module_init(module_id, &init_param) != ESP_OK) {
+                // even though the sleep retention module init failed, PCNT driver should still work, so just warning here
+                ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id);
+            }
+#endif // PCNT_USE_RETENTION_LINK
             // initialize HAL context
             pcnt_hal_init(&group->hal, group_id);
         }
@@ -902,6 +926,12 @@ static void pcnt_release_group_handle(pcnt_group_t *group)
     _lock_release(&s_platform.mutex);
 
     if (do_deinitialize) {
+#if PCNT_USE_RETENTION_LINK
+        const periph_retention_module_t module_id = pcnt_reg_retention_info[group_id].retention_module;
+        if (sleep_retention_get_inited_modules() & BIT(module_id)) {
+            sleep_retention_module_deinit(module_id);
+        }
+#endif // PCNT_USE_RETENTION_LINK
         free(group);
         ESP_LOGD(TAG, "del group (%d)", group_id);
     }
@@ -999,3 +1029,17 @@ IRAM_ATTR static void pcnt_default_isr(void *args)
         portYIELD_FROM_ISR();
     }
 }
+
+#if PCNT_USE_RETENTION_LINK
+static esp_err_t pcnt_create_sleep_retention_link_cb(void *arg)
+{
+    pcnt_group_t *group = (pcnt_group_t *)arg;
+    int group_id = group->group_id;
+    sleep_retention_module_t module_id = pcnt_reg_retention_info[group_id].retention_module;
+    esp_err_t err = sleep_retention_entries_create(pcnt_reg_retention_info[group_id].regdma_entry_array,
+                                                   pcnt_reg_retention_info[group_id].array_size,
+                                                   REGDMA_LINK_PRI_PCNT, module_id);
+    ESP_RETURN_ON_ERROR(err, TAG, "create retention link failed");
+    return ESP_OK;
+}
+#endif // PCNT_USE_RETENTION_LINK
diff --git a/components/esp_driver_pcnt/test_apps/pulse_cnt/main/CMakeLists.txt b/components/esp_driver_pcnt/test_apps/pulse_cnt/main/CMakeLists.txt
index 67bb690c46b..1fc04aa4b80 100644
--- a/components/esp_driver_pcnt/test_apps/pulse_cnt/main/CMakeLists.txt
+++ b/components/esp_driver_pcnt/test_apps/pulse_cnt/main/CMakeLists.txt
@@ -6,6 +6,11 @@ if(CONFIG_PCNT_ISR_IRAM_SAFE)
     list(APPEND srcs "test_pulse_cnt_iram.c")
 endif()
 
+# TODO: IDF-9907 support ESP32P4
+if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED AND CONFIG_PM_ENABLE AND NOT CONFIG_IDF_TARGET_ESP32P4)
+    list(APPEND srcs "test_pulse_cnt_sleep.c")
+endif()
+
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
diff --git a/components/esp_driver_pcnt/test_apps/pulse_cnt/main/test_pulse_cnt_sleep.c b/components/esp_driver_pcnt/test_apps/pulse_cnt/main/test_pulse_cnt_sleep.c
new file mode 100644
index 00000000000..2ac2dc40628
--- /dev/null
+++ b/components/esp_driver_pcnt/test_apps/pulse_cnt/main/test_pulse_cnt_sleep.c
@@ -0,0 +1,141 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "unity.h"
+#include "unity_test_utils.h"
+#include "driver/pulse_cnt.h"
+#include "driver/gpio.h"
+#include "spi_flash_mmap.h"
+#include "esp_attr.h"
+#include "esp_sleep.h"
+#include "soc/soc_caps.h"
+#include "soc/pcnt_struct.h"
+#include "hal/pcnt_ll.h"
+#include "test_pulse_cnt_board.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/esp_pmu.h"
+
+/**
+ * @brief Test the PCNT driver can still work after light sleep
+ */
+static void test_pcnt_sleep_retention(void)
+{
+    test_gpio_init_for_simulation(TEST_PCNT_GPIO_A);
+    test_gpio_init_for_simulation(TEST_PCNT_GPIO_B);
+
+    printf("install pcnt units\r\n");
+    pcnt_unit_config_t unit_config = {
+        .low_limit = -100,
+        .high_limit = 100,
+    };
+    pcnt_unit_handle_t units[2];
+    for (int i = 0; i < 2; i++) {
+        TEST_ESP_OK(pcnt_new_unit(&unit_config, &units[i]));
+    }
+
+    printf("install pcnt channels\r\n");
+    const int channel_gpios[] = {TEST_PCNT_GPIO_A, TEST_PCNT_GPIO_B};
+    pcnt_chan_config_t chan_config = {
+        .level_gpio_num = -1,
+    };
+    pcnt_channel_handle_t chans[2];
+    for (int i = 0; i < 2; i++) {
+        chan_config.edge_gpio_num = channel_gpios[i];
+        TEST_ESP_OK(pcnt_new_channel(units[i], &chan_config, &chans[i]));
+        TEST_ESP_OK(pcnt_channel_set_edge_action(chans[i], PCNT_CHANNEL_EDGE_ACTION_INCREASE, PCNT_CHANNEL_EDGE_ACTION_HOLD));
+        TEST_ESP_OK(pcnt_channel_set_level_action(chans[i], PCNT_CHANNEL_LEVEL_ACTION_KEEP, PCNT_CHANNEL_LEVEL_ACTION_KEEP));
+    }
+
+    printf("enable and start unit\r\n");
+    for (int i = 0; i < 2; i++) {
+        TEST_ESP_OK(pcnt_unit_enable(units[i]));
+        TEST_ESP_OK(pcnt_unit_start(units[i]));
+    }
+
+    // trigger 10 rising edge on GPIO
+    test_gpio_simulate_rising_edge(TEST_PCNT_GPIO_A, 10);
+    test_gpio_simulate_rising_edge(TEST_PCNT_GPIO_B, 10);
+
+    int count_value = 0;
+    for (int i = 0; i < 2; i++) {
+        TEST_ESP_OK(pcnt_unit_get_count(units[i], &count_value));
+        TEST_ASSERT_EQUAL(10, count_value);
+    }
+
+    // hold GPIO to avoid trigger PCNT counter during GPIO power down
+    gpio_hold_en(TEST_PCNT_GPIO_A);
+    gpio_hold_en(TEST_PCNT_GPIO_B);
+
+    printf("stop and disable unit before sleep\r\n");
+    for (int i = 0; i < 2; i++) {
+        TEST_ESP_OK(pcnt_unit_stop(units[i]));
+        TEST_ESP_OK(pcnt_unit_disable(units[i]));
+    }
+
+    // go to sleep
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+    printf("go to light sleep for 1 seconds\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
+    TEST_ESP_OK(esp_light_sleep_start());
+
+    printf("Waked up! Let's see if PCNT driver can still work...\r\n");
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+
+    printf("check if the sleep happened as expected\r\n");
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_PCNT_SUPPORT_SLEEP_RETENTION
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL(0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+    esp_sleep_set_sleep_context(NULL);
+
+    gpio_hold_dis(TEST_PCNT_GPIO_A);
+    gpio_hold_dis(TEST_PCNT_GPIO_B);
+
+    printf("enable and start unit after sleep\r\n");
+    for (int i = 0; i < 2; i++) {
+        TEST_ESP_OK(pcnt_unit_enable(units[i]));
+        TEST_ESP_OK(pcnt_unit_start(units[i]));
+    }
+
+    // Verify the counter still holds the value
+    test_gpio_simulate_rising_edge(TEST_PCNT_GPIO_A, 10);
+    test_gpio_simulate_rising_edge(TEST_PCNT_GPIO_B, 10);
+
+    int reg_value = 0;
+    for (int i = 0; i < 2; i++) {
+        // check the counter value (include accum value and register value)
+        TEST_ESP_OK(pcnt_unit_get_count(units[i], &count_value));
+        TEST_ASSERT_EQUAL(20, count_value);
+        // check the register value
+        reg_value = pcnt_ll_get_count(&PCNT, i);
+        TEST_ASSERT_EQUAL(20, reg_value);
+    }
+
+    for (int i = 0; i < 2; i++) {
+        TEST_ESP_OK(pcnt_unit_stop(units[i]));
+        TEST_ESP_OK(pcnt_unit_disable(units[i]));
+        TEST_ESP_OK(pcnt_del_channel(chans[i]));
+        TEST_ESP_OK(pcnt_del_unit(units[i]));
+    }
+}
+
+TEST_CASE("pcnt light sleep", "[pcnt]")
+{
+    test_pcnt_sleep_retention();
+}
diff --git a/components/esp_driver_pcnt/test_apps/pulse_cnt/sdkconfig.ci.release b/components/esp_driver_pcnt/test_apps/pulse_cnt/sdkconfig.ci.release
index 91d93f163e6..17aaee1e8ec 100644
--- a/components/esp_driver_pcnt/test_apps/pulse_cnt/sdkconfig.ci.release
+++ b/components/esp_driver_pcnt/test_apps/pulse_cnt/sdkconfig.ci.release
@@ -1,5 +1,6 @@
 CONFIG_PM_ENABLE=y
 CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
 CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
diff --git a/components/esp_driver_pcnt/test_apps/pulse_cnt/sdkconfig.defaults b/components/esp_driver_pcnt/test_apps/pulse_cnt/sdkconfig.defaults
index fa8ac618b94..488ad46859a 100644
--- a/components/esp_driver_pcnt/test_apps/pulse_cnt/sdkconfig.defaults
+++ b/components/esp_driver_pcnt/test_apps/pulse_cnt/sdkconfig.defaults
@@ -1,2 +1,5 @@
 CONFIG_FREERTOS_HZ=1000
 CONFIG_ESP_TASK_WDT_EN=n
+
+# primitives for checking sleep internal state
+CONFIG_ESP_SLEEP_DEBUG=y
diff --git a/components/esp_driver_ppa/src/ppa_blend.c b/components/esp_driver_ppa/src/ppa_blend.c
index b5ebaa7f692..f8ffab01ee5 100644
--- a/components/esp_driver_ppa/src/ppa_blend.c
+++ b/components/esp_driver_ppa/src/ppa_blend.c
@@ -234,16 +234,22 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf
         .color_type_id = config->in_bg.blend_cm,
     };
     uint32_t in_bg_pixel_depth = color_hal_pixel_format_get_bit_depth(in_bg_pixel_format); // bits
+    // Usually C2M can let the msync do alignment internally, however, it only do L1-cacheline-size alignment for L1->L2, and then L2-cacheline-size alignment for L2->mem
+    // While M2C direction manual alignment is L2-cacheline-size alignment for mem->L2->L1
+    // Mismatching writeback and invalidate data size could cause synchronization error if in_bg/fg_buffer and out_buffer are the same one
     uint32_t in_bg_ext_window = (uint32_t)config->in_bg.buffer + config->in_bg.block_offset_y * config->in_bg.pic_w * in_bg_pixel_depth / 8;
+    uint32_t in_bg_ext_window_aligned = PPA_ALIGN_DOWN(in_bg_ext_window, buf_alignment_size);
     uint32_t in_bg_ext_window_len = config->in_bg.pic_w * config->in_bg.block_h * in_bg_pixel_depth / 8;
-    esp_cache_msync((void *)in_bg_ext_window, in_bg_ext_window_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
+    esp_cache_msync((void *)in_bg_ext_window_aligned, PPA_ALIGN_UP(in_bg_ext_window_len + (in_bg_ext_window - in_bg_ext_window_aligned), buf_alignment_size), ESP_CACHE_MSYNC_FLAG_DIR_C2M);
     color_space_pixel_format_t in_fg_pixel_format = {
         .color_type_id = config->in_fg.blend_cm,
     };
     uint32_t in_fg_pixel_depth = color_hal_pixel_format_get_bit_depth(in_fg_pixel_format); // bits
     uint32_t in_fg_ext_window = (uint32_t)config->in_fg.buffer + config->in_fg.block_offset_y * config->in_fg.pic_w * in_fg_pixel_depth / 8;
+    // Same for fg_buffer msync, do manual alignment
+    uint32_t in_fg_ext_window_aligned = PPA_ALIGN_DOWN(in_fg_ext_window, buf_alignment_size);
     uint32_t in_fg_ext_window_len = config->in_fg.pic_w * config->in_fg.block_h * in_fg_pixel_depth / 8;
-    esp_cache_msync((void *)in_fg_ext_window, in_fg_ext_window_len, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
+    esp_cache_msync((void *)in_fg_ext_window_aligned, PPA_ALIGN_UP(in_fg_ext_window_len + (in_fg_ext_window - in_fg_ext_window_aligned), buf_alignment_size), ESP_CACHE_MSYNC_FLAG_DIR_C2M);
     // Invalidate out_buffer extended window (alignment strict on M2C direction)
     uint32_t out_ext_window = (uint32_t)config->out.buffer + config->out.block_offset_y * config->out.pic_w * out_pixel_depth / 8;
     uint32_t out_ext_window_aligned = PPA_ALIGN_DOWN(out_ext_window, buf_alignment_size);
diff --git a/components/esp_driver_ppa/src/ppa_srm.c b/components/esp_driver_ppa/src/ppa_srm.c
index f59746e8662..0242ef37eed 100644
--- a/components/esp_driver_ppa/src/ppa_srm.c
+++ b/components/esp_driver_ppa/src/ppa_srm.c
@@ -194,14 +194,17 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s
                             config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0,
                             ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y");
     }
+    ESP_RETURN_ON_FALSE(config->in.block_w <= (config->in.pic_w - config->in.block_offset_x) &&
+                        config->in.block_h <= (config->in.pic_h - config->in.block_offset_y),
+                        ESP_ERR_INVALID_ARG, TAG, "in.block_w/h + in.block_offset_x/y does not fit in the in pic");
     color_space_pixel_format_t out_pixel_format = {
         .color_type_id = config->out.srm_cm,
     };
     uint32_t out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); // bits
     uint32_t out_pic_len = config->out.pic_w * config->out.pic_h * out_pixel_depth / 8;
     ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size");
-    ESP_RETURN_ON_FALSE(config->scale_x < (PPA_LL_SRM_SCALING_INT_MAX + 1) && config->scale_x >= (1.0 / PPA_LL_SRM_SCALING_FRAG_MAX) &&
-                        config->scale_y < (PPA_LL_SRM_SCALING_INT_MAX + 1) && config->scale_y >= (1.0 / PPA_LL_SRM_SCALING_FRAG_MAX),
+    ESP_RETURN_ON_FALSE(config->scale_x < PPA_LL_SRM_SCALING_INT_MAX && config->scale_x >= (1.0 / PPA_LL_SRM_SCALING_FRAG_MAX) &&
+                        config->scale_y < PPA_LL_SRM_SCALING_INT_MAX && config->scale_y >= (1.0 / PPA_LL_SRM_SCALING_FRAG_MAX),
                         ESP_ERR_INVALID_ARG, TAG, "invalid scale");
     uint32_t new_block_w = 0;
     uint32_t new_block_h = 0;
@@ -243,7 +246,8 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s
     // Invalidate out_buffer extended window (alignment strict on M2C direction)
     uint32_t out_ext_window = (uint32_t)config->out.buffer + config->out.block_offset_y * config->out.pic_w * out_pixel_depth / 8;
     uint32_t out_ext_window_aligned = PPA_ALIGN_DOWN(out_ext_window, buf_alignment_size);
-    uint32_t out_ext_window_len = config->out.pic_w * config->in.block_h * out_pixel_depth / 8;
+    uint32_t out_ext_window_len = config->out.pic_w * new_block_h * out_pixel_depth / 8; // actual ext_window_len must be less than or equal to this, since actual block_h <= new_block_h (may round down)
+    assert(out_ext_window + out_ext_window_len <= (uint32_t)config->out.buffer + config->out.buffer_size);
     esp_cache_msync((void *)out_ext_window_aligned, PPA_ALIGN_UP(out_ext_window_len + (out_ext_window - out_ext_window_aligned), buf_alignment_size), ESP_CACHE_MSYNC_FLAG_DIR_M2C);
 
     esp_err_t ret = ESP_OK;
@@ -256,9 +260,9 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s
         ppa_srm_oper_t *srm_trans_desc = (ppa_srm_oper_t *)trans_on_picked_desc->srm_desc;
         memcpy(srm_trans_desc, config, sizeof(ppa_srm_oper_config_t));
         srm_trans_desc->scale_x_int = (uint32_t)srm_trans_desc->scale_x;
-        srm_trans_desc->scale_x_frag = (uint32_t)(srm_trans_desc->scale_x * (PPA_LL_SRM_SCALING_FRAG_MAX + 1)) & PPA_LL_SRM_SCALING_FRAG_MAX;
+        srm_trans_desc->scale_x_frag = (uint32_t)(srm_trans_desc->scale_x * PPA_LL_SRM_SCALING_FRAG_MAX) & (PPA_LL_SRM_SCALING_FRAG_MAX - 1);
         srm_trans_desc->scale_y_int = (uint32_t)srm_trans_desc->scale_y;
-        srm_trans_desc->scale_y_frag = (uint32_t)(srm_trans_desc->scale_y * (PPA_LL_SRM_SCALING_FRAG_MAX + 1)) & PPA_LL_SRM_SCALING_FRAG_MAX;
+        srm_trans_desc->scale_y_frag = (uint32_t)(srm_trans_desc->scale_y * PPA_LL_SRM_SCALING_FRAG_MAX) & (PPA_LL_SRM_SCALING_FRAG_MAX - 1);
         srm_trans_desc->alpha_value = new_alpha_value;
         srm_trans_desc->data_burst_length = ppa_client->data_burst_length;
 
diff --git a/components/esp_driver_rmt/src/rmt_common.c b/components/esp_driver_rmt/src/rmt_common.c
index d2b6f856f6f..7a3cf11ca3d 100644
--- a/components/esp_driver_rmt/src/rmt_common.c
+++ b/components/esp_driver_rmt/src/rmt_common.c
@@ -75,7 +75,7 @@ rmt_group_t *rmt_acquire_group_handle(int group_id)
                 rmt_ll_reset_register(group_id);
             }
 #if RMT_USE_RETENTION_LINK
-            sleep_retention_module_t module = RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id);
+            sleep_retention_module_t module = rmt_reg_retention_info[group_id].module;
             sleep_retention_module_init_param_t init_param = {
                 .cbs = {
                     .create = {
@@ -85,9 +85,7 @@ rmt_group_t *rmt_acquire_group_handle(int group_id)
                 },
                 .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM)
             };
-            if (sleep_retention_module_init(module, &init_param) == ESP_OK) {
-                group->sleep_retention_module = module;
-            } else {
+            if (sleep_retention_module_init(module, &init_param) != ESP_OK) {
                 // even though the sleep retention module init failed, RMT driver should still work, so just warning here
                 ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id);
             }
@@ -147,11 +145,12 @@ void rmt_release_group_handle(rmt_group_t *group)
 
     if (do_deinitialize) {
 #if RMT_USE_RETENTION_LINK
-        if (group->sleep_retention_module) {
-            if (group->retention_link_created) {
-                sleep_retention_module_free(group->sleep_retention_module);
-            }
-            sleep_retention_module_deinit(group->sleep_retention_module);
+        sleep_retention_module_t module = rmt_reg_retention_info[group_id].module;
+        if (sleep_retention_get_created_modules() & BIT(module)) {
+            sleep_retention_module_free(module);
+        }
+        if (sleep_retention_get_inited_modules() & BIT(module)) {
+            sleep_retention_module_deinit(module);
         }
 #endif
         free(group);
@@ -303,24 +302,21 @@ static esp_err_t rmt_create_sleep_retention_link_cb(void *arg)
 {
     rmt_group_t *group = (rmt_group_t *)arg;
     int group_id = group->group_id;
-    sleep_retention_module_t module = group->sleep_retention_module;
     esp_err_t err = sleep_retention_entries_create(rmt_reg_retention_info[group_id].regdma_entry_array,
                                                    rmt_reg_retention_info[group_id].array_size,
-                                                   REGDMA_LINK_PRI_RMT, module);
+                                                   REGDMA_LINK_PRI_RMT, rmt_reg_retention_info[group_id].module);
     return err;
 }
 
 void rmt_create_retention_module(rmt_group_t *group)
 {
-    sleep_retention_module_t module = group->sleep_retention_module;
-
+    int group_id = group->group_id;
+    sleep_retention_module_t module = rmt_reg_retention_info[group_id].module;
     _lock_acquire(&s_platform.mutex);
-    if (group->retention_link_created == false) {
+    if ((sleep_retention_get_inited_modules() & BIT(module)) && !(sleep_retention_get_created_modules() & BIT(module))) {
         if (sleep_retention_module_allocate(module) != ESP_OK) {
             // even though the sleep retention module create failed, RMT driver should still work, so just warning here
-            ESP_LOGW(TAG, "create retention link failed, power domain can't be turned off");
-        } else {
-            group->retention_link_created = true;
+            ESP_LOGW(TAG, "create retention link failed, power domain won't be turned off during sleep");
         }
     }
     _lock_release(&s_platform.mutex);
diff --git a/components/esp_driver_rmt/src/rmt_private.h b/components/esp_driver_rmt/src/rmt_private.h
index 017ed9d9ab6..16efc8ca9eb 100644
--- a/components/esp_driver_rmt/src/rmt_private.h
+++ b/components/esp_driver_rmt/src/rmt_private.h
@@ -119,10 +119,6 @@ struct rmt_group_t {
     rmt_rx_channel_t *rx_channels[SOC_RMT_RX_CANDIDATES_PER_GROUP]; // array of RMT RX channels
     rmt_sync_manager_t *sync_manager; // sync manager, this can be extended into an array if there're more sync controllers in one RMT group
     int intr_priority;     // RMT interrupt priority
-#if RMT_USE_RETENTION_LINK
-    sleep_retention_module_t sleep_retention_module; // sleep retention module
-    bool retention_link_created;       // mark if the retention link is created
-#endif
 };
 
 struct rmt_channel_t {
diff --git a/components/esp_driver_sdio/src/sdio_slave.c b/components/esp_driver_sdio/src/sdio_slave.c
index ccc56d9ae93..71b6084645b 100644
--- a/components/esp_driver_sdio/src/sdio_slave.c
+++ b/components/esp_driver_sdio/src/sdio_slave.c
@@ -76,20 +76,24 @@ The driver of FIFOs works as below:
 */
 
 #include <string.h>
-#include "driver/sdio_slave.h"
-#include "soc/sdio_slave_periph.h"
-#include "esp_log.h"
-#include "esp_intr_alloc.h"
-#include "freertos/FreeRTOS.h"
+
 #include "soc/soc_memory_layout.h"
 #include "soc/gpio_periph.h"
 #include "soc/soc_caps.h"
+#include "soc/sdio_slave_periph.h"
 #include "esp_cpu.h"
+#include "esp_intr_alloc.h"
+#include "esp_log.h"
+#include "hal/sdio_slave_hal.h"
+#include "hal/gpio_hal.h"
+#include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "esp_private/periph_ctrl.h"
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+#include "esp_private/sleep_retention.h"
+#endif
 #include "driver/gpio.h"
-#include "hal/sdio_slave_hal.h"
-#include "hal/gpio_hal.h"
+#include "driver/sdio_slave.h"
 
 #define SDIO_SLAVE_CHECK(res, str, ret_val) do { if(!(res)){\
     SDIO_SLAVE_LOGE("%s", str);\
@@ -365,6 +369,13 @@ esp_err_t sdio_slave_initialize(sdio_slave_config_t *config)
     }
     context.intr_handle = intr_handle;
 
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+    r = sleep_retention_power_lock_acquire();
+    if (r != ESP_OK) {
+        return r;
+    }
+#endif
+
     r = sdio_slave_hw_init(config);
     if (r != ESP_OK) {
         return r;
@@ -378,6 +389,11 @@ void sdio_slave_deinit(void)
 {
     sdio_slave_hw_deinit();
 
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+    esp_err_t r = sleep_retention_power_lock_release();
+    assert(r == ESP_OK);
+#endif
+
     //unregister all buffers registered but returned (not loaded)
     recv_desc_t *temp_desc;
     recv_desc_t *desc;
diff --git a/components/esp_driver_sdio/test_apps/.build-test-rules.yml b/components/esp_driver_sdio/test_apps/.build-test-rules.yml
index df1d2c4828f..25d6c046aec 100644
--- a/components/esp_driver_sdio/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_sdio/test_apps/.build-test-rules.yml
@@ -1,7 +1,6 @@
 components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc:
   enable:
     - if: IDF_TARGET == "esp32"
-      temporary: false
       reason: always use ESP32 SDMMC as host
   depends_components:
     - sdmmc
@@ -9,6 +8,10 @@ components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc:
     - esp_driver_sdio
 
 components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio:
+  enable:
+  # There is no retention support for SDIO slave, just build and test if driver can forbid from auto light sleep.
+    - if: CONFIG_NAME == "sleep_retention" and SOC_PAU_SUPPORTED == 1
+    - if: CONFIG_NAME != "sleep_retention"
   disable:
     - if: SOC_SDIO_SLAVE_SUPPORTED != 1
   depends_components:
diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c
index 8a63f2b9b6a..c358a2d8a7b 100644
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/host_sdmmc/main/test_sdio_sdhost.c
@@ -418,6 +418,20 @@ TEST_CASE("SDIO_SDMMC: test to host", "[sdio]")
     test_to_host(true);
 }
 
+TEST_CASE("SDIO_SDMMC: test sleep retention", "[sdio_retention]")
+{
+    essl_handle_t handle = NULL;
+    test_sdio_param_t test_param = {
+        .host_flags = SDMMC_HOST_FLAG_4BIT | SDMMC_HOST_FLAG_ALLOC_ALIGNED_BUF,
+        .max_freq_khz = SDMMC_FREQ_HIGHSPEED,
+    };
+    //essl init and sdmmc init
+    s_master_init(&test_param, &handle, NULL);
+
+    s_send_finish_test(handle);
+    s_master_deinit();
+}
+
 TEST_CASE("SDIO_SDMMC: test to host (Performance)", "[sdio_speed]")
 {
     test_to_host(false);
diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py
index e0e6f3ebf73..1e123bd929a 100644
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/pytest_sdio.py
@@ -1,13 +1,30 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import os.path
+from typing import List
 from typing import Tuple
 
 import pytest
 from pytest_embedded_idf import IdfDut
 
 
+def parameter_expand(existing_parameters: List[List[str]], value_list: List[str]) -> List[List[str]]:
+    ret = []
+    for param in existing_parameters:
+        ret.extend([param + [value] for value in value_list])
+
+    return ret
+
+
+esp32_32_param = [[f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}', 'esp32|esp32']]
+esp32_c6_param = [[f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}', 'esp32|esp32c6']]
+
+esp32_param_default = [pytest.param(*param) for param in parameter_expand(esp32_32_param, ['default|default'])]
+c6_param_default = [pytest.param(*param) for param in parameter_expand(esp32_c6_param, ['default|default'])]
+
+c6_param_retention = [pytest.param(*param) for param in parameter_expand(esp32_c6_param, ['default|sleep_retention'])]
+
+
 # Normal tests
 def test_sdio_flow(dut:Tuple[IdfDut, IdfDut]) -> None:
     dut[1].expect('Press ENTER to see the list of tests')
@@ -24,11 +41,7 @@ def test_sdio_flow(dut:Tuple[IdfDut, IdfDut]) -> None:
 @pytest.mark.esp32c6
 @pytest.mark.sdio_multidev_32_c6
 @pytest.mark.parametrize('count', [2,], indirect=True)
-@pytest.mark.parametrize('app_path, target', [
-    pytest.param(
-        f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}',
-        'esp32|esp32c6'),
-], indirect=True)
+@pytest.mark.parametrize('app_path, target, config', c6_param_default, indirect=True)
 def test_sdio_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None:
     test_sdio_flow(dut)
 
@@ -36,11 +49,7 @@ def test_sdio_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None:
 @pytest.mark.esp32
 @pytest.mark.sdio_master_slave
 @pytest.mark.parametrize('count', [2,], indirect=True)
-@pytest.mark.parametrize('app_path, target', [
-    pytest.param(
-        f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}',
-        'esp32|esp32'),
-], indirect=True)
+@pytest.mark.parametrize('app_path, target, config', esp32_param_default, indirect=True)
 def test_sdio_esp32_esp32(dut:Tuple[IdfDut, IdfDut]) -> None:
     test_sdio_flow(dut)
 
@@ -68,11 +77,7 @@ def test_sdio_speed_frhost_flow(dut:Tuple[IdfDut, IdfDut], expected_4b_speed:int
 @pytest.mark.esp32c6
 @pytest.mark.sdio_multidev_32_c6
 @pytest.mark.parametrize('count', [2,], indirect=True)
-@pytest.mark.parametrize('app_path, target', [
-    pytest.param(
-        f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}',
-        'esp32|esp32c6'),
-], indirect=True)
+@pytest.mark.parametrize('app_path, target, config', c6_param_default, indirect=True)
 def test_sdio_speed_frhost_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None:
     test_sdio_speed_frhost_flow(dut, 10000, 4000)
 
@@ -80,11 +85,7 @@ def test_sdio_speed_frhost_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None:
 @pytest.mark.esp32
 @pytest.mark.sdio_master_slave
 @pytest.mark.parametrize('count', [2,], indirect=True)
-@pytest.mark.parametrize('app_path, target', [
-    pytest.param(
-        f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}',
-        'esp32|esp32'),
-], indirect=True)
+@pytest.mark.parametrize('app_path, target, config', esp32_param_default, indirect=True)
 def test_sdio_speed_frhost_esp32_esp32(dut:Tuple[IdfDut, IdfDut]) -> None:
     test_sdio_speed_frhost_flow(dut, 12200, 4000)
 
@@ -112,11 +113,7 @@ def test_sdio_speed_tohost_flow(dut:Tuple[IdfDut, IdfDut], expected_4b_speed:int
 @pytest.mark.esp32c6
 @pytest.mark.sdio_multidev_32_c6
 @pytest.mark.parametrize('count', [2,], indirect=True)
-@pytest.mark.parametrize('app_path, target', [
-    pytest.param(
-        f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}',
-        'esp32|esp32c6'),
-], indirect=True)
+@pytest.mark.parametrize('app_path, target, config', c6_param_default, indirect=True)
 def test_sdio_speed_tohost_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None:
     test_sdio_speed_tohost_flow(dut, 9000, 4000)
 
@@ -124,10 +121,27 @@ def test_sdio_speed_tohost_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None:
 @pytest.mark.esp32
 @pytest.mark.sdio_master_slave
 @pytest.mark.parametrize('count', [2,], indirect=True)
-@pytest.mark.parametrize('app_path, target', [
-    pytest.param(
-        f'{os.path.join(os.path.dirname(__file__), "host_sdmmc")}|{os.path.join(os.path.dirname(__file__), "sdio")}',
-        'esp32|esp32'),
-], indirect=True)
+@pytest.mark.parametrize('app_path, target, config', esp32_param_default, indirect=True)
 def test_sdio_speed_tohost_esp32_esp32(dut:Tuple[IdfDut, IdfDut]) -> None:
     test_sdio_speed_tohost_flow(dut, 12200, 4000)
+
+
+# Retention tests
+def test_sdio_retention(dut:Tuple[IdfDut, IdfDut]) -> None:
+    dut[1].expect('Press ENTER to see the list of tests')
+    dut[1].write('[sdio_retention]')
+    dut[1].expect('test_sdio: slave ready')
+
+    dut[0].expect('Press ENTER to see the list of tests')
+    dut[0].write('[sdio_retention]')
+
+    dut[1].expect_unity_test_output()
+    dut[0].expect_unity_test_output()
+
+
+@pytest.mark.esp32c6
+@pytest.mark.sdio_multidev_32_c6
+@pytest.mark.parametrize('count', [2,], indirect=True)
+@pytest.mark.parametrize('app_path, target, config', c6_param_retention, indirect=True)
+def test_sdio_retention_esp32_esp32c6(dut:Tuple[IdfDut, IdfDut]) -> None:
+    test_sdio_retention(dut)
diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/CMakeLists.txt b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/CMakeLists.txt
index 94e0034a58b..0822f3336ae 100644
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/CMakeLists.txt
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/CMakeLists.txt
@@ -2,5 +2,5 @@ set(srcs "test_app_main.c"
          "test_sdio_slave.c")
 
 idf_component_register(SRCS ${srcs}
-                       PRIV_REQUIRES test_driver_utils driver
+                       PRIV_REQUIRES test_driver_utils driver esp_hw_support
                        WHOLE_ARCHIVE)
diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c
index d91e19dd7ce..6be681697dc 100644
--- a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/main/test_sdio_slave.c
@@ -305,6 +305,31 @@ TEST_CASE("SDIO_Slave: test to host", "[sdio]")
     test_to_host();
 }
 
+#if SOC_PAU_SUPPORTED
+#include "esp_private/sleep_sys_periph.h"
+#include "esp_private/sleep_retention.h"
+
+TEST_CASE("SDIO_Slave: test sleep retention", "[sdio_retention]")
+{
+    TEST_ASSERT_EQUAL_INT32(true, peripheral_domain_pd_allowed());
+    sleep_retention_dump_modules(stdout);
+
+    s_slave_init(SDIO_SLAVE_SEND_STREAM);
+    TEST_ESP_OK(sdio_slave_start());
+    ESP_LOGI(TAG, "slave ready");
+
+    TEST_ASSERT_EQUAL_INT32(false, peripheral_domain_pd_allowed());
+    sleep_retention_dump_modules(stdout);
+
+    wait_for_finish(&s_test_slv_ctx);
+
+    sdio_slave_stop();
+    sdio_slave_deinit();
+
+    TEST_ASSERT_EQUAL_INT32(true, peripheral_domain_pd_allowed());
+}
+#endif
+
 TEST_CASE("SDIO_Slave: test to host (Performance)", "[sdio_speed]")
 {
     test_to_host();
diff --git a/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.ci.sleep_retention b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.ci.sleep_retention
new file mode 100644
index 00000000000..b9e39a38336
--- /dev/null
+++ b/components/esp_driver_sdio/test_apps/sdio/sdio_common_tests/sdio/sdkconfig.ci.sleep_retention
@@ -0,0 +1,4 @@
+CONFIG_PM_ENABLE=y
+CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
+CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
diff --git a/components/esp_driver_sdm/src/sdm.c b/components/esp_driver_sdm/src/sdm.c
index d5300a48ece..9675e504b61 100644
--- a/components/esp_driver_sdm/src/sdm.c
+++ b/components/esp_driver_sdm/src/sdm.c
@@ -29,6 +29,7 @@
 #include "soc/sdm_periph.h"
 #include "esp_private/esp_clk.h"
 #include "esp_private/io_mux.h"
+#include "esp_private/gpio.h"
 
 #if CONFIG_SDM_CTRL_FUNC_IN_IRAM
 #define SDM_MEM_ALLOC_CAPS      (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
@@ -229,16 +230,12 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_
     // SDM clock comes from IO MUX, but IO MUX clock might be shared with other submodules as well
     ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(group->clk_src)), err, TAG, "set IO MUX clock source failed");
 
-    // GPIO configuration
-    gpio_config_t gpio_conf = {
-        .intr_type = GPIO_INTR_DISABLE,
-        // also enable the input path is `io_loop_back` is on, this is useful for debug
-        .mode = GPIO_MODE_OUTPUT | (config->flags.io_loop_back ? GPIO_MODE_INPUT : 0),
-        .pull_down_en = false,
-        .pull_up_en = true,
-        .pin_bit_mask = 1ULL << config->gpio_num,
-    };
-    ESP_GOTO_ON_ERROR(gpio_config(&gpio_conf), err, TAG, "config GPIO failed");
+    gpio_func_sel(config->gpio_num, PIN_FUNC_GPIO);
+    // deprecated, to be removed in in esp-idf v6.0
+    if (config->flags.io_loop_back) {
+        gpio_input_enable(config->gpio_num);
+    }
+    // connect the signal to the GPIO by matrix, it will also enable the output path properly
     esp_rom_gpio_connect_out_signal(config->gpio_num, sigma_delta_periph_signals.channels[chan_id].sd_sig, config->flags.invert_out, false);
     chan->gpio_num = config->gpio_num;
 
@@ -283,6 +280,7 @@ esp_err_t sdm_del_channel(sdm_channel_handle_t chan)
     sdm_group_t *group = chan->group;
     int group_id = group->group_id;
     int chan_id = chan->chan_id;
+    gpio_output_disable(chan->gpio_num);
     ESP_LOGD(TAG, "del channel (%d,%d)", group_id, chan_id);
     // recycle memory resource
     ESP_RETURN_ON_ERROR(sdm_destroy(chan), TAG, "destroy channel failed");
diff --git a/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h b/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h
index 7b72fdb201f..5b0bc07f0ff 100644
--- a/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h
+++ b/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h
@@ -31,6 +31,8 @@ extern "C" {
     .slot = SDMMC_HOST_SLOT_1, \
     .max_freq_khz = SDMMC_FREQ_DEFAULT, \
     .io_voltage = 3.3f, \
+    .driver_strength = SDMMC_DRIVER_STRENGTH_B, \
+    .current_limit = SDMMC_CURRENT_LIMIT_200MA, \
     .init = &sdmmc_host_init, \
     .set_bus_width = &sdmmc_host_set_bus_width, \
     .get_bus_width = &sdmmc_host_get_slot_width, \
@@ -48,29 +50,35 @@ extern "C" {
     .dma_aligned_buffer = NULL, \
     .pwr_ctrl_handle = NULL, \
     .get_dma_info = &sdmmc_host_get_dma_info, \
+    .is_slot_set_to_uhs1 = &sdmmc_host_is_slot_set_to_uhs1, \
 }
 
 #define SDMMC_SLOT_NO_CD      GPIO_NUM_NC     ///< indicates that card detect line is not used
 #define SDMMC_SLOT_NO_WP      GPIO_NUM_NC     ///< indicates that write protect line is not used
 #define SDMMC_SLOT_WIDTH_DEFAULT 0 ///< use the maximum possible width for the slot
 
-#if SOC_SDMMC_USE_IOMUX && !SOC_SDMMC_USE_GPIO_MATRIX
 /**
  * Macro defining default configuration of SDMMC host slot
  */
+#if CONFIG_IDF_TARGET_ESP32
 #define SDMMC_SLOT_CONFIG_DEFAULT() {\
+    .clk = GPIO_NUM_6, \
+    .cmd = GPIO_NUM_11, \
+    .d0 = GPIO_NUM_7, \
+    .d1 = GPIO_NUM_8, \
+    .d2 = GPIO_NUM_9, \
+    .d3 = GPIO_NUM_10, \
+    .d4 = GPIO_NUM_16, \
+    .d5 = GPIO_NUM_17, \
+    .d6 = GPIO_NUM_5, \
+    .d7 = GPIO_NUM_18, \
     .cd = SDMMC_SLOT_NO_CD, \
     .wp = SDMMC_SLOT_NO_WP, \
     .width   = SDMMC_SLOT_WIDTH_DEFAULT, \
     .flags = 0, \
 }
 
-#else
-
-/**
- * Macro defining default configuration of SDMMC host slot
- */
-#if CONFIG_IDF_TARGET_ESP32P4
+#elif CONFIG_IDF_TARGET_ESP32P4
 #define SDMMC_SLOT_CONFIG_DEFAULT() {\
     .clk = GPIO_NUM_43, \
     .cmd = GPIO_NUM_44, \
@@ -107,8 +115,6 @@ extern "C" {
 }
 #endif  // GPIO Matrix chips
 
-#endif
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_sdmmc/include/driver/sdmmc_host.h b/components/esp_driver_sdmmc/include/driver/sdmmc_host.h
index 9457eaf5c14..037dbe83cf8 100644
--- a/components/esp_driver_sdmmc/include/driver/sdmmc_host.h
+++ b/components/esp_driver_sdmmc/include/driver/sdmmc_host.h
@@ -24,7 +24,6 @@ extern "C" {
  * Extra configuration for SDMMC peripheral slot
  */
 typedef struct {
-#ifdef SOC_SDMMC_USE_GPIO_MATRIX
     gpio_num_t clk;         ///< GPIO number of CLK signal.
     gpio_num_t cmd;         ///< GPIO number of CMD signal.
     gpio_num_t d0;          ///< GPIO number of D0 signal.
@@ -35,7 +34,6 @@ typedef struct {
     gpio_num_t d5;          ///< GPIO number of D5 signal. Ignored in 1- or 4- line mode.
     gpio_num_t d6;          ///< GPIO number of D6 signal. Ignored in 1- or 4- line mode.
     gpio_num_t d7;          ///< GPIO number of D7 signal. Ignored in 1- or 4- line mode.
-#endif // SOC_SDMMC_USE_GPIO_MATRIX
     union {
         gpio_num_t gpio_cd;     ///< GPIO number of card detect signal
         gpio_num_t cd;          ///< GPIO number of card detect signal; shorter name.
@@ -56,6 +54,8 @@ typedef struct {
      * 0 means "active low", i.e. card is protected when the GPIO is low;
      * 1 means "active high", i.e. card is protected when GPIO is high.
      */
+#define SDMMC_SLOT_FLAG_UHS1             BIT(2)
+    /**< Enable UHS-I mode for this slot */
 } sdmmc_slot_config_t;
 
 /**
@@ -284,6 +284,18 @@ esp_err_t sdmmc_host_set_input_delay(int slot, sdmmc_delay_phase_t delay_phase);
  */
 esp_err_t sdmmc_host_get_dma_info(int slot, esp_dma_mem_info_t *dma_mem_info);
 
+/**
+ * @brief Check if the slot is set to uhs1 or not
+ *
+ * @param[in]  slot     Slot id
+ * @param[out] is_uhs1  Is uhs1 or not
+ *
+ * @return
+ *        - ESP_OK:                on success
+ *        - ESP_ERR_INVALID_STATE: driver not in correct state
+ */
+esp_err_t sdmmc_host_is_slot_set_to_uhs1(int slot, bool *is_uhs1);
+
 /**
  * @brief Get the state of SDMMC host
  *
diff --git a/components/esp_driver_sdmmc/src/sdmmc_host.c b/components/esp_driver_sdmmc/src/sdmmc_host.c
index f322f8316f4..fad7045ece6 100644
--- a/components/esp_driver_sdmmc/src/sdmmc_host.c
+++ b/components/esp_driver_sdmmc/src/sdmmc_host.c
@@ -20,7 +20,7 @@
 #include "driver/sdmmc_host.h"
 #include "esp_private/esp_clk_tree_common.h"
 #include "esp_private/periph_ctrl.h"
-#include "sdmmc_private.h"
+#include "sdmmc_internal.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "esp_clk_tree.h"
@@ -33,6 +33,8 @@
 
 #define SDMMC_EVENT_QUEUE_LENGTH    32
 
+#define SDMMC_FREQ_SDR104           208000      /*!< MMC 208MHz speed */
+
 #if !SOC_RCC_IS_INDEPENDENT
 // Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
 #define SDMMC_RCC_ATOMIC()          PERIPH_RCC_ATOMIC()
@@ -65,9 +67,11 @@ if (!GPIO_IS_VALID_GPIO(_gpio_num)) { \
  * Slot contexts
  */
 typedef struct slot_ctx_t {
+    int slot_id;
     size_t slot_width;
     sdmmc_slot_io_info_t slot_gpio_num;
     bool use_gpio_matrix;
+    bool is_uhs1;
 #if SOC_SDMMC_NUM_SLOTS >= 2
     int slot_host_div;
     uint32_t slot_freq_khz;
@@ -79,14 +83,15 @@ typedef struct slot_ctx_t {
  * Host contexts
  */
 typedef struct host_ctx_t {
-    intr_handle_t        intr_handle;
-    QueueHandle_t        event_queue;
-    SemaphoreHandle_t    io_intr_event;
-    sdmmc_hal_context_t  hal;
-    slot_ctx_t           slot_ctx[SOC_SDMMC_NUM_SLOTS];
+    intr_handle_t              intr_handle;
+    QueueHandle_t              event_queue;
+    SemaphoreHandle_t          io_intr_event;
+    sdmmc_hal_context_t        hal;
+    soc_periph_sdmmc_clk_src_t clk_src;
+    slot_ctx_t                 slot_ctx[SOC_SDMMC_NUM_SLOTS];
 #if SOC_SDMMC_NUM_SLOTS >= 2
-    uint8_t              num_of_init_slots;
-    int8_t               active_slot_num;
+    uint8_t                    num_of_init_slots;
+    int8_t                     active_slot_num;
 #endif
 } host_ctx_t;
 
@@ -163,20 +168,25 @@ esp_err_t sdmmc_host_reset(void)
  * Of the second stage dividers, div0 is used for card 0, and div1 is used
  * for card 1.
  */
-static void sdmmc_host_set_clk_div(int div)
+static void sdmmc_host_set_clk_div(soc_periph_sdmmc_clk_src_t src, int div)
 {
-    esp_clk_tree_enable_src((soc_module_clk_t)SDMMC_CLK_SRC_DEFAULT, true);
+    esp_clk_tree_enable_src((soc_module_clk_t)src, true);
     SDMMC_CLK_SRC_ATOMIC() {
         sdmmc_ll_set_clock_div(s_host_ctx.hal.dev, div);
-        sdmmc_ll_select_clk_source(s_host_ctx.hal.dev, SDMMC_CLK_SRC_DEFAULT);
+        sdmmc_ll_select_clk_source(s_host_ctx.hal.dev, src);
         sdmmc_ll_init_phase_delay(s_host_ctx.hal.dev);
+#if SOC_CLK_SDIO_PLL_SUPPORTED
+        if (src == SDMMC_CLK_SRC_SDIO_200M) {
+            sdmmc_ll_enable_sdio_pll(s_host_ctx.hal.dev, true);
+        }
+#endif
     }
 
     // Wait for the clock to propagate
     esp_rom_delay_us(10);
 }
 
-static esp_err_t sdmmc_host_clock_update_command(int slot)
+static esp_err_t sdmmc_host_clock_update_command(int slot, bool is_cmd11)
 {
     // Clock update command (not a real command; just updates CIU registers)
     sdmmc_hw_cmd_t cmd_val = {
@@ -184,47 +194,31 @@ static esp_err_t sdmmc_host_clock_update_command(int slot)
         .update_clk_reg = 1,
         .wait_complete = 1
     };
-    bool repeat = true;
-    while (repeat) {
-
-        ESP_RETURN_ON_ERROR(sdmmc_host_start_command(slot, cmd_val, 0), TAG, "sdmmc_host_start_command returned 0x%x", err_rc_);
-
-        int64_t yield_delay_us = 100 * 1000; // initially 100ms
-        int64_t t0 = esp_timer_get_time();
-        int64_t t1 = 0;
-        while (true) {
-            t1 = esp_timer_get_time();
-            if (t1 - t0  > SDMMC_HOST_CLOCK_UPDATE_CMD_TIMEOUT_US) {
-                return ESP_ERR_TIMEOUT;
-            }
-            // Sending clock update command to the CIU can generate HLE error.
-            // According to the manual, this is okay and we must retry the command.
-            if (sdmmc_ll_get_interrupt_raw(s_host_ctx.hal.dev) & SDMMC_LL_EVENT_HLE) {
-                sdmmc_ll_clear_interrupt(s_host_ctx.hal.dev, SDMMC_LL_EVENT_HLE);
-                repeat = true;
-                break;
-            }
-            // When the command is accepted by CIU, start_command bit will be
-            // cleared in SDMMC.cmd register.
-            if (sdmmc_ll_is_command_taken(s_host_ctx.hal.dev)) {
-                repeat = false;
-                break;
-            }
-            if (t1 - t0 > yield_delay_us) {
-                yield_delay_us *= 2;
-                vTaskDelay(1);
-            }
-        }
+    if (is_cmd11) {
+        cmd_val.volt_switch = 1;
     }
+    ESP_RETURN_ON_ERROR(sdmmc_host_start_command(slot, cmd_val, 0), TAG, "sdmmc_host_start_command returned 0x%x", err_rc_);
 
     return ESP_OK;
 }
 
-void sdmmc_host_get_clk_dividers(uint32_t freq_khz, int *host_div, int *card_div)
+void sdmmc_host_get_clk_dividers(uint32_t freq_khz, int *host_div, int *card_div, soc_periph_sdmmc_clk_src_t *src)
 {
     uint32_t clk_src_freq_hz = 0;
-    esp_clk_tree_src_get_freq_hz(SDMMC_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
-    assert(clk_src_freq_hz == (160 * 1000 * 1000));
+    soc_periph_sdmmc_clk_src_t clk_src = 0;
+#if SOC_SDMMC_UHS_I_SUPPORTED
+    if (freq_khz > SDMMC_FREQ_HIGHSPEED) {
+        clk_src = SDMMC_CLK_SRC_SDIO_200M;
+    } else
+#endif
+    {
+        clk_src = SDMMC_CLK_SRC_DEFAULT;
+    }
+    s_host_ctx.clk_src = clk_src;
+
+    esp_err_t ret = esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
+    assert(ret == ESP_OK);
+    ESP_LOGD(TAG, "clk_src_freq_hz: %"PRId32" hz", clk_src_freq_hz);
 
 #if SDMMC_LL_MAX_FREQ_KHZ_FPGA
     if (freq_khz >= SDMMC_LL_MAX_FREQ_KHZ_FPGA) {
@@ -232,40 +226,53 @@ void sdmmc_host_get_clk_dividers(uint32_t freq_khz, int *host_div, int *card_div
         freq_khz = SDMMC_LL_MAX_FREQ_KHZ_FPGA;
     }
 #endif
+
     // Calculate new dividers
-    if (freq_khz >= SDMMC_FREQ_HIGHSPEED) {
-        *host_div = 4;       // 160 MHz / 4 = 40 MHz
+#if SOC_SDMMC_UHS_I_SUPPORTED
+    if (freq_khz == SDMMC_FREQ_SDR104) {
+        *host_div = 1;       // 200 MHz / 1 = 200 MHz
         *card_div = 0;
-    } else if (freq_khz == SDMMC_FREQ_DEFAULT) {
-        *host_div = 8;       // 160 MHz / 8 = 20 MHz
+    } else if (freq_khz == SDMMC_FREQ_SDR50) {
+        *host_div = 2;       // 200 MHz / 2 = 100 MHz
         *card_div = 0;
-    } else if (freq_khz == SDMMC_FREQ_PROBING) {
-        *host_div = 10;      // 160 MHz / 10 / (20 * 2) = 400 kHz
-        *card_div = 20;
-    } else {
-        /*
-         * for custom frequencies use maximum range of host divider (1-16), find the closest <= div. combination
-         * if exceeded, combine with the card divider to keep reasonable precision (applies mainly to low frequencies)
-         * effective frequency range: 400 kHz - 32 MHz (32.1 - 39.9 MHz cannot be covered with given divider scheme)
-         */
-        *host_div = (clk_src_freq_hz) / (freq_khz * 1000);
-        if (*host_div > 15) {
-            *host_div = 2;
-            *card_div = (clk_src_freq_hz / 2) / (2 * freq_khz * 1000);
-            if (((clk_src_freq_hz / 2) % (2 * freq_khz * 1000)) > 0) {
-                (*card_div)++;
+    } else
+#endif
+        if (freq_khz >= SDMMC_FREQ_HIGHSPEED) {
+            *host_div = 4;       // 160 MHz / 4 = 40 MHz
+            *card_div = 0;
+        } else if (freq_khz == SDMMC_FREQ_DEFAULT) {
+            *host_div = 8;       // 160 MHz / 8 = 20 MHz
+            *card_div = 0;
+        } else if (freq_khz == SDMMC_FREQ_PROBING) {
+            *host_div = 10;      // 160 MHz / 10 / (20 * 2) = 400 kHz
+            *card_div = 20;
+        } else {
+            /*
+             * for custom frequencies use maximum range of host divider (1-16), find the closest <= div. combination
+             * if exceeded, combine with the card divider to keep reasonable precision (applies mainly to low frequencies)
+             * effective frequency range: 400 kHz - 32 MHz (32.1 - 39.9 MHz cannot be covered with given divider scheme)
+             */
+            *host_div = (clk_src_freq_hz) / (freq_khz * 1000);
+            if (*host_div > 15) {
+                *host_div = 2;
+                *card_div = (clk_src_freq_hz / 2) / (2 * freq_khz * 1000);
+                if (((clk_src_freq_hz / 2) % (2 * freq_khz * 1000)) > 0) {
+                    (*card_div)++;
+                }
+            } else if ((clk_src_freq_hz % (freq_khz * 1000)) > 0) {
+                (*host_div)++;
             }
-        } else if ((clk_src_freq_hz % (freq_khz * 1000)) > 0) {
-            (*host_div)++;
         }
-    }
+
+    *src = clk_src;
 }
 
-static int sdmmc_host_calc_freq(const int host_div, const int card_div)
+static int sdmmc_host_calc_freq(soc_periph_sdmmc_clk_src_t src, const int host_div, const int card_div)
 {
     uint32_t clk_src_freq_hz = 0;
-    esp_clk_tree_src_get_freq_hz(SDMMC_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
-    assert(clk_src_freq_hz == (160 * 1000 * 1000));
+    esp_err_t ret = esp_clk_tree_src_get_freq_hz(src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz);
+    assert(ret == ESP_OK);
+
     return clk_src_freq_hz / host_div / ((card_div == 0) ? 1 : card_div * 2) / 1000;
 }
 
@@ -282,24 +289,25 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz)
 
     // Disable clock first
     sdmmc_ll_enable_card_clock(s_host_ctx.hal.dev, slot, false);
-    esp_err_t err = sdmmc_host_clock_update_command(slot);
+    esp_err_t err = sdmmc_host_clock_update_command(slot, false);
     if (err != ESP_OK) {
         ESP_LOGE(TAG, "disabling clk failed");
         ESP_LOGE(TAG, "%s: sdmmc_host_clock_update_command returned 0x%x", __func__, err);
         return err;
     }
 
+    soc_periph_sdmmc_clk_src_t clk_src = 0;
     int host_div = 0;   /* clock divider of the host (SDMMC.clock) */
     int card_div = 0;   /* 1/2 of card clock divider (SDMMC.clkdiv) */
-    sdmmc_host_get_clk_dividers(freq_khz, &host_div, &card_div);
+    sdmmc_host_get_clk_dividers(freq_khz, &host_div, &card_div, &clk_src);
 
-    int real_freq = sdmmc_host_calc_freq(host_div, card_div);
-    ESP_LOGD(TAG, "slot=%d host_div=%d card_div=%d freq=%dkHz (max %" PRIu32 "kHz)", slot, host_div, card_div, real_freq, freq_khz);
+    int real_freq = sdmmc_host_calc_freq(clk_src, host_div, card_div);
+    ESP_LOGD(TAG, "slot=%d clk_src=%d host_div=%d card_div=%d freq=%dkHz (max %" PRIu32 "kHz)", slot, clk_src, host_div, card_div, real_freq, freq_khz);
 
     // Program card clock settings, send them to the CIU
     sdmmc_ll_set_card_clock_div(s_host_ctx.hal.dev, slot, card_div);
-    sdmmc_host_set_clk_div(host_div);
-    err = sdmmc_host_clock_update_command(slot);
+    sdmmc_host_set_clk_div(clk_src, host_div);
+    err = sdmmc_host_clock_update_command(slot, false);
     if (err != ESP_OK) {
         ESP_LOGE(TAG, "setting clk div failed");
         ESP_LOGE(TAG, "%s: sdmmc_host_clock_update_command returned 0x%x", __func__, err);
@@ -309,7 +317,7 @@ esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz)
     // Re-enable clocks
     sdmmc_ll_enable_card_clock(s_host_ctx.hal.dev, slot, true);
     sdmmc_ll_enable_card_clock_low_power(s_host_ctx.hal.dev, slot, true);
-    err = sdmmc_host_clock_update_command(slot);
+    err = sdmmc_host_clock_update_command(slot, false);
     if (err != ESP_OK) {
         ESP_LOGE(TAG, "re-enabling clk failed");
         ESP_LOGE(TAG, "%s: sdmmc_host_clock_update_command returned 0x%x", __func__, err);
@@ -338,7 +346,7 @@ esp_err_t sdmmc_host_get_real_freq(int slot, int *real_freq_khz)
 
     int host_div = sdmmc_ll_get_clock_div(s_host_ctx.hal.dev);
     int card_div = sdmmc_ll_get_card_clock_div(s_host_ctx.hal.dev, slot);
-    *real_freq_khz = sdmmc_host_calc_freq(host_div, card_div);
+    *real_freq_khz = sdmmc_host_calc_freq(s_host_ctx.clk_src, host_div, card_div);
 
     return ESP_OK;
 }
@@ -354,7 +362,7 @@ esp_err_t sdmmc_host_set_input_delay(int slot, sdmmc_delay_phase_t delay_phase)
     ESP_RETURN_ON_FALSE(delay_phase < SOC_SDMMC_DELAY_PHASE_NUM, ESP_ERR_INVALID_ARG, TAG, "invalid delay phase");
 
     uint32_t clk_src_freq_hz = 0;
-    ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(SDMMC_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz),
+    ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(s_host_ctx.clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_src_freq_hz),
                         TAG, "get source clock frequency failed");
 
     //Now we're in high speed. Note ESP SDMMC Host HW only supports integer divider.
@@ -425,7 +433,25 @@ esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg)
     int64_t yield_delay_us = 100 * 1000; // initially 100ms
     int64_t t0 = esp_timer_get_time();
     int64_t t1 = 0;
-    while (!sdmmc_ll_is_command_taken(s_host_ctx.hal.dev)) {
+    bool skip_wait = (cmd.volt_switch && cmd.update_clk_reg);
+    if (!skip_wait) {
+        while (!(sdmmc_ll_is_command_taken(s_host_ctx.hal.dev))) {
+            t1 = esp_timer_get_time();
+            if (t1 - t0 > SDMMC_HOST_START_CMD_TIMEOUT_US) {
+                return ESP_ERR_TIMEOUT;
+            }
+            if (t1 - t0 > yield_delay_us) {
+                yield_delay_us *= 2;
+                vTaskDelay(1);
+            }
+        }
+    }
+    sdmmc_ll_set_command_arg(s_host_ctx.hal.dev, arg);
+    cmd.card_num = slot;
+    cmd.start_command = 1;
+    sdmmc_ll_set_command(s_host_ctx.hal.dev, cmd);
+
+    while (!(sdmmc_ll_is_command_taken(s_host_ctx.hal.dev))) {
         t1 = esp_timer_get_time();
         if (t1 - t0 > SDMMC_HOST_START_CMD_TIMEOUT_US) {
             return ESP_ERR_TIMEOUT;
@@ -435,10 +461,6 @@ esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg)
             vTaskDelay(1);
         }
     }
-    sdmmc_ll_set_command_arg(s_host_ctx.hal.dev, arg);
-    cmd.card_num = slot;
-    cmd.start_command = 1;
-    sdmmc_ll_set_command(s_host_ctx.hal.dev, cmd);
     return ESP_OK;
 }
 
@@ -473,7 +495,7 @@ esp_err_t sdmmc_host_init(void)
     sdmmc_hal_init(&s_host_ctx.hal);
 
     // Enable clock to peripheral. Use smallest divider first.
-    sdmmc_host_set_clk_div(2);
+    sdmmc_host_set_clk_div(SDMMC_CLK_SRC_DEFAULT, 2);
 
     // Reset
     esp_err_t err = sdmmc_host_reset();
@@ -581,6 +603,18 @@ static bool s_check_pin_not_set(const sdmmc_slot_config_t *slot_config)
 #endif
 }
 
+esp_err_t sdmmc_host_is_slot_set_to_uhs1(int slot, bool *is_uhs1)
+{
+    if (s_host_ctx.slot_ctx[slot].slot_id != slot) {
+        ESP_LOGE(TAG, "%s: slot %d isn't initialized", __func__, slot);
+        return ESP_ERR_INVALID_STATE;
+    }
+
+    *is_uhs1 = s_host_ctx.slot_ctx[slot].is_uhs1;
+
+    return ESP_OK;
+}
+
 esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
 {
     if (!s_host_ctx.intr_handle) {
@@ -592,6 +626,11 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
     if (slot_config == NULL) {
         return ESP_ERR_INVALID_ARG;
     }
+
+    if (slot_config->flags & SDMMC_SLOT_FLAG_UHS1) {
+        s_host_ctx.slot_ctx[slot].is_uhs1 = true;
+    }
+
     int gpio_cd = slot_config->cd;
     int gpio_wp = slot_config->wp;
     bool gpio_wp_polarity = slot_config->flags & SDMMC_SLOT_FLAG_WP_ACTIVE_HIGH;
@@ -616,7 +655,17 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
 
     if (slot == 0) {
 #if !SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(0)
-        ESP_RETURN_ON_FALSE(!use_gpio_matrix, ESP_ERR_INVALID_ARG, TAG, "doesn't support routing from GPIO matrix, driver uses dedicated IOs");
+        if (use_gpio_matrix &&
+                SDMMC_SLOT0_IOMUX_PIN_NUM_CLK == slot_config->clk &&
+                SDMMC_SLOT0_IOMUX_PIN_NUM_CMD == slot_config->cmd &&
+                SDMMC_SLOT0_IOMUX_PIN_NUM_D0 == slot_config->d0 &&
+                SDMMC_SLOT0_IOMUX_PIN_NUM_D1 == slot_config->d1 &&
+                SDMMC_SLOT0_IOMUX_PIN_NUM_D2 == slot_config->d2 &&
+                SDMMC_SLOT0_IOMUX_PIN_NUM_D3 == slot_config->d3) {
+            use_gpio_matrix = false;
+        } else {
+            ESP_RETURN_ON_FALSE(!use_gpio_matrix, ESP_ERR_INVALID_ARG, TAG, "doesn't support routing from GPIO matrix, driver uses dedicated IOs");
+        }
 #endif
     } else {
 #if !SDMMC_LL_SLOT_SUPPORT_GPIO_MATRIX(1)
@@ -689,18 +738,22 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
     if (slot_width >= 4) {
         configure_pin(slot_gpio->d1, sdmmc_slot_gpio_sig[slot].d1, GPIO_MODE_INPUT_OUTPUT, "d1", use_gpio_matrix);
         configure_pin(slot_gpio->d2, sdmmc_slot_gpio_sig[slot].d2, GPIO_MODE_INPUT_OUTPUT, "d2", use_gpio_matrix);
-        // Force D3 high to make slave enter SD mode.
-        // Connect to peripheral after width configuration.
-        if (slot_gpio->d3 > GPIO_NUM_NC) {
-            gpio_config_t gpio_conf = {
-                .pin_bit_mask = BIT64(slot_gpio->d3),
-                .mode = GPIO_MODE_OUTPUT,
-                .pull_up_en = 0,
-                .pull_down_en = 0,
-                .intr_type = GPIO_INTR_DISABLE,
-            };
-            gpio_config(&gpio_conf);
-            gpio_set_level(slot_gpio->d3, 1);
+        if (s_host_ctx.slot_ctx[slot].is_uhs1) {
+            configure_pin(slot_gpio->d3, sdmmc_slot_gpio_sig[slot].d3, GPIO_MODE_INPUT_OUTPUT, "d3", use_gpio_matrix);
+        } else {
+            // Force D3 high to make slave enter SD mode.
+            // Connect to peripheral after width configuration.
+            if (slot_gpio->d3 > GPIO_NUM_NC) {
+                gpio_config_t gpio_conf = {
+                    .pin_bit_mask = BIT64(slot_gpio->d3),
+                    .mode = GPIO_MODE_OUTPUT,
+                    .pull_up_en = 0,
+                    .pull_down_en = 0,
+                    .intr_type = GPIO_INTR_DISABLE,
+                };
+                gpio_config(&gpio_conf);
+                gpio_set_level(slot_gpio->d3, 1);
+            }
         }
     }
     if (slot_width == 8) {
@@ -755,6 +808,8 @@ esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t *slot_config)
         return ret;
     }
 
+    s_host_ctx.slot_ctx[slot].slot_id = slot;
+
 #if SOC_SDMMC_NUM_SLOTS >= 2
     if (s_host_ctx.num_of_init_slots < SOC_SDMMC_NUM_SLOTS && s_host_ctx.active_slot_num != slot) {
         s_host_ctx.num_of_init_slots += 1;
@@ -940,10 +995,21 @@ esp_err_t sdmmc_host_set_cclk_always_on(int slot, bool cclk_always_on)
     } else {
         sdmmc_ll_enable_card_clock_low_power(s_host_ctx.hal.dev, slot, true);
     }
-    sdmmc_host_clock_update_command(slot);
+    sdmmc_host_clock_update_command(slot, false);
     return ESP_OK;
 }
 
+void sdmmc_host_enable_clk_cmd11(int slot, bool enable)
+{
+    sdmmc_ll_enable_card_clock(s_host_ctx.hal.dev, slot, enable);
+    sdmmc_host_clock_update_command(slot, true);
+    if (enable) {
+        sdmmc_ll_enable_1v8_mode(s_host_ctx.hal.dev, slot, true);
+    } else {
+        sdmmc_ll_enable_1v8_mode(s_host_ctx.hal.dev, slot, false);
+    }
+}
+
 void sdmmc_host_dma_stop(void)
 {
     sdmmc_ll_stop_dma(s_host_ctx.hal.dev);
diff --git a/components/esp_driver_sdmmc/src/sdmmc_internal.h b/components/esp_driver_sdmmc/src/sdmmc_internal.h
new file mode 100644
index 00000000000..20ad83289a5
--- /dev/null
+++ b/components/esp_driver_sdmmc/src/sdmmc_internal.h
@@ -0,0 +1,43 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+#include "esp_err.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/queue.h"
+#include "soc/sdmmc_periph.h"
+
+typedef struct {
+    uint32_t sdmmc_status;      ///< masked SDMMC interrupt status
+    uint32_t dma_status;        ///< masked DMA interrupt status
+} sdmmc_event_t;
+
+#define SDMMC_HOST_CLOCK_UPDATE_CMD_TIMEOUT_US           1000 * 1000
+#define SDMMC_HOST_START_CMD_TIMEOUT_US                  1000 * 1000
+#define SDMMC_HOST_RESET_TIMEOUT_US                      5000 * 1000
+
+esp_err_t sdmmc_host_reset(void);
+
+esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg);
+
+esp_err_t sdmmc_host_wait_for_event(int tick_count, sdmmc_event_t* out_event);
+
+void sdmmc_host_dma_prepare(sdmmc_desc_t* desc, size_t block_size, size_t data_size);
+
+void sdmmc_host_dma_stop(void);
+
+void sdmmc_host_dma_resume(void);
+
+bool sdmmc_host_card_busy(void);
+
+void sdmmc_host_enable_clk_cmd11(int slot, bool enable);
+
+esp_err_t sdmmc_host_transaction_handler_init(void);
+
+void sdmmc_host_transaction_handler_deinit(void);
diff --git a/components/esp_driver_sdmmc/src/sdmmc_private.h b/components/esp_driver_sdmmc/src/sdmmc_private.h
deleted file mode 100644
index 529fa6b823b..00000000000
--- a/components/esp_driver_sdmmc/src/sdmmc_private.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include <stddef.h>
-#include "esp_err.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/queue.h"
-#include "soc/sdmmc_periph.h"
-
-typedef struct {
-    uint32_t sdmmc_status;      ///< masked SDMMC interrupt status
-    uint32_t dma_status;        ///< masked DMA interrupt status
-} sdmmc_event_t;
-
-#define SDMMC_HOST_CLOCK_UPDATE_CMD_TIMEOUT_US           1000 * 1000
-#define SDMMC_HOST_START_CMD_TIMEOUT_US                  1000 * 1000
-#define SDMMC_HOST_RESET_TIMEOUT_US                      5000 * 1000
-
-esp_err_t sdmmc_host_reset(void);
-
-esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg);
-
-esp_err_t sdmmc_host_wait_for_event(int tick_count, sdmmc_event_t* out_event);
-
-void sdmmc_host_dma_prepare(sdmmc_desc_t* desc, size_t block_size, size_t data_size);
-
-void sdmmc_host_dma_stop(void);
-
-void sdmmc_host_dma_resume(void);
-
-bool sdmmc_host_card_busy(void);
-
-esp_err_t sdmmc_host_transaction_handler_init(void);
-
-void sdmmc_host_transaction_handler_deinit(void);
diff --git a/components/esp_driver_sdmmc/src/sdmmc_transaction.c b/components/esp_driver_sdmmc/src/sdmmc_transaction.c
index c6a360b8d1e..55cf55a4029 100644
--- a/components/esp_driver_sdmmc/src/sdmmc_transaction.c
+++ b/components/esp_driver_sdmmc/src/sdmmc_transaction.c
@@ -5,6 +5,7 @@
  */
 
 #include <string.h>
+#include <unistd.h>
 #include "esp_err.h"
 #include "esp_log.h"
 #include "esp_check.h"
@@ -19,8 +20,9 @@
 #include "driver/sdmmc_host.h"
 #include "esp_cache.h"
 #include "esp_private/esp_cache_private.h"
-#include "sdmmc_private.h"
+#include "sdmmc_internal.h"
 #include "soc/soc_caps.h"
+#include "hal/sdmmc_ll.h"
 
 /* Number of DMA descriptors used for transfer.
  * Increasing this value above 4 doesn't improve performance for the usual case
@@ -37,6 +39,8 @@ typedef enum {
     SDMMC_SENDING_CMD,
     SDMMC_SENDING_DATA,
     SDMMC_BUSY,
+    SDMMC_SENDING_VOLTAGE_SWITCH,
+    SDMMC_WAITING_VOLTAGE_SWITCH,
 } sdmmc_req_state_t;
 
 typedef struct {
@@ -70,14 +74,17 @@ static esp_pm_lock_handle_t s_pm_lock;
 
 static esp_err_t handle_idle_state_events(void);
 static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd);
-static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state,
+static esp_err_t handle_event(int slot, sdmmc_command_t* cmd, sdmmc_req_state_t* state,
                               sdmmc_event_t* unhandled_events);
-static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd,
+static esp_err_t process_events(int slot, sdmmc_event_t evt, sdmmc_command_t* cmd,
                                 sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events);
 static void process_command_response(uint32_t status, sdmmc_command_t* cmd);
 static void fill_dma_descriptors(size_t num_desc);
 static size_t get_free_descriptors_count(void);
 static bool wait_for_busy_cleared(uint32_t timeout_ms);
+static void handle_voltage_switch_stage1(int slot, sdmmc_command_t* cmd);
+static void handle_voltage_switch_stage2(int slot, sdmmc_command_t* cmd);
+static void handle_voltage_switch_stage3(int slot, sdmmc_command_t* cmd);
 
 esp_err_t sdmmc_host_transaction_handler_init(void)
 {
@@ -124,6 +131,12 @@ esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo)
 
     // dispose of any events which happened asynchronously
     handle_idle_state_events();
+
+    // special handling for voltage switch command
+    if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) {
+        handle_voltage_switch_stage1(slot, cmdinfo);
+    }
+
     // convert cmdinfo to hardware register value
     sdmmc_hw_cmd_t hw_cmd = make_hw_cmd(cmdinfo);
     if (cmdinfo->data) {
@@ -174,9 +187,12 @@ esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo)
     // process events until transfer is complete
     cmdinfo->error = ESP_OK;
     sdmmc_req_state_t state = SDMMC_SENDING_CMD;
+    if (cmdinfo->opcode == SD_SWITCH_VOLTAGE) {
+        state = SDMMC_SENDING_VOLTAGE_SWITCH;
+    }
     sdmmc_event_t unhandled_events = { 0 };
     while (state != SDMMC_IDLE) {
-        ret = handle_event(cmdinfo, &state, &unhandled_events);
+        ret = handle_event(slot, cmdinfo, &state, &unhandled_events);
         if (ret != ESP_OK) {
             break;
         }
@@ -286,7 +302,7 @@ static esp_err_t handle_idle_state_events(void)
     return ESP_OK;
 }
 
-static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state,
+static esp_err_t handle_event(int slot, sdmmc_command_t* cmd, sdmmc_req_state_t* state,
                               sdmmc_event_t* unhandled_events)
 {
     sdmmc_event_t event;
@@ -298,13 +314,13 @@ static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state,
         }
         return err;
     }
-    ESP_LOGV(TAG, "sdmmc_handle_event: event %08"PRIx32" %08"PRIx32", unhandled %08"PRIx32" %08"PRIx32,
-             event.sdmmc_status, event.dma_status,
+    ESP_LOGV(TAG, "sdmmc_handle_event: slot %d event %08"PRIx32" %08"PRIx32", unhandled %08"PRIx32" %08"PRIx32,
+             slot, event.sdmmc_status, event.dma_status,
              unhandled_events->sdmmc_status, unhandled_events->dma_status);
     event.sdmmc_status |= unhandled_events->sdmmc_status;
     event.dma_status |= unhandled_events->dma_status;
-    process_events(event, cmd, state, unhandled_events);
-    ESP_LOGV(TAG, "sdmmc_handle_event: events unhandled: %08"PRIx32" %08"PRIx32, unhandled_events->sdmmc_status, unhandled_events->dma_status);
+    process_events(slot, event, cmd, state, unhandled_events);
+    ESP_LOGV(TAG, "sdmmc_handle_event: slot %d events unhandled: %08"PRIx32" %08"PRIx32, slot, unhandled_events->sdmmc_status, unhandled_events->dma_status);
     return ESP_OK;
 }
 
@@ -327,12 +343,15 @@ static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd)
         res.stop_abort_cmd = 1;
     } else if (cmd->opcode == MMC_GO_IDLE_STATE) {
         res.send_init = 1;
+    } else if (cmd->opcode == SD_SWITCH_VOLTAGE) {
+        res.volt_switch = 1;
     } else {
         res.wait_complete = 1;
     }
     if (cmd->opcode == MMC_GO_IDLE_STATE) {
         res.send_init = 1;
     }
+
     if (cmd->flags & SCF_RSP_PRESENT) {
         res.response_expect = 1;
         if (cmd->flags & SCF_RSP_136) {
@@ -419,18 +438,20 @@ static inline bool mask_check_and_clear(uint32_t* state, uint32_t mask)
     return ret;
 }
 
-static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd,
+static esp_err_t process_events(int slot, sdmmc_event_t evt, sdmmc_command_t* cmd,
                                 sdmmc_req_state_t* pstate, sdmmc_event_t* unhandled_events)
 {
     const char* const s_state_names[] __attribute__((unused)) = {
         "IDLE",
         "SENDING_CMD",
         "SENDIND_DATA",
-        "BUSY"
+        "BUSY",
+        "SENDING_VOLTAGE_SWITCH",
+        "WAITING_VOLTAGE_SWITCH",
     };
     sdmmc_event_t orig_evt = evt;
-    ESP_LOGV(TAG, "%s: state=%s evt=%"PRIx32" dma=%"PRIx32, __func__, s_state_names[*pstate],
-             evt.sdmmc_status, evt.dma_status);
+    ESP_LOGV(TAG, "%s: slot=%d state=%s evt=%"PRIx32" dma=%"PRIx32, __func__, slot,
+             s_state_names[*pstate], evt.sdmmc_status, evt.dma_status);
     sdmmc_req_state_t next_state = *pstate;
     sdmmc_req_state_t state = (sdmmc_req_state_t) -1;
     while (next_state != state) {
@@ -461,6 +482,32 @@ static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd,
             }
             break;
 
+        case SDMMC_SENDING_VOLTAGE_SWITCH:
+            if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) {
+                process_command_response(orig_evt.sdmmc_status, cmd);
+                next_state = SDMMC_IDLE;
+            }
+            if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) {
+                handle_voltage_switch_stage2(slot, cmd);
+                if (cmd->error != ESP_OK) {
+                    next_state = SDMMC_IDLE;
+                } else {
+                    next_state = SDMMC_WAITING_VOLTAGE_SWITCH;
+                }
+            }
+            break;
+
+        case SDMMC_WAITING_VOLTAGE_SWITCH:
+            if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) {
+                process_command_response(orig_evt.sdmmc_status, cmd);
+                next_state = SDMMC_IDLE;
+            }
+            if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_VOLT_SW)) {
+                handle_voltage_switch_stage3(slot, cmd);
+                next_state = SDMMC_IDLE;
+            }
+            break;
+
         case SDMMC_SENDING_DATA:
             if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_DATA_ERR_MASK)) {
                 process_data_status(orig_evt.sdmmc_status, cmd);
@@ -518,3 +565,32 @@ static bool wait_for_busy_cleared(uint32_t timeout_ms)
     }
     return false;
 }
+
+static void handle_voltage_switch_stage1(int slot, sdmmc_command_t* cmd)
+{
+    ESP_LOGV(TAG, "%s: enabling clock", __func__);
+    sdmmc_host_set_cclk_always_on(slot, true);
+}
+
+static void handle_voltage_switch_stage2(int slot, sdmmc_command_t* cmd)
+{
+    ESP_LOGV(TAG, "%s: disabling clock", __func__);
+    sdmmc_host_enable_clk_cmd11(slot, false);
+    usleep(100);
+    ESP_LOGV(TAG, "%s: switching voltage", __func__);
+    esp_err_t err = cmd->volt_switch_cb(cmd->volt_switch_cb_arg, 1800);
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "failed to switch voltage (0x%x)", err);
+        cmd->error = err;
+    }
+    ESP_LOGV(TAG, "%s: waiting 10ms", __func__);
+    usleep(10000);
+    ESP_LOGV(TAG, "%s: enabling clock", __func__);
+    sdmmc_host_enable_clk_cmd11(slot, true);
+}
+
+static void handle_voltage_switch_stage3(int slot, sdmmc_command_t* cmd)
+{
+    ESP_LOGV(TAG, "%s: voltage switch complete, clock back to low-power mode", __func__);
+    sdmmc_host_set_cclk_always_on(slot, false);
+}
diff --git a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/include/sdmmc_test_board.h b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/include/sdmmc_test_board.h
index 3e1424f35d8..cb220f07b96 100644
--- a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/include/sdmmc_test_board.h
+++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/include/sdmmc_test_board.h
@@ -33,6 +33,7 @@ typedef struct {
     bool is_emmc;       /*< True if this slot is connected to eMMC */
     int  bus_width;     /*< SD interface width (1, 4 or 8) */
     int  max_freq_khz;  /*< Max frequency (kHz) of SD interface, supported by the board */
+    bool uhs1_supported; /*< Whether UHS-I mode is supported */
     gpio_num_t clk;     /*< CLK pin number */
     gpio_num_t cmd_mosi;    /*< CMD pin number (SD mode) or MOSI (SPI mode) */
     gpio_num_t d0_miso; /*< D0 pin number (SD mode) or MISO (SPI mode) */
diff --git a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board.c b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board.c
index 5a2831e299a..08f37abe667 100644
--- a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board.c
+++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board.c
@@ -34,6 +34,9 @@ void sdmmc_test_board_get_config_sdmmc(int slot_index, sdmmc_host_t *out_host_co
     if (slot->max_freq_khz > 0) {
         out_host_config->max_freq_khz = slot->max_freq_khz;
     }
+    if (slot->uhs1_supported) {
+        out_slot_config->flags |= SDMMC_SLOT_FLAG_UHS1;
+    }
 
 #if SOC_SDMMC_USE_GPIO_MATRIX
     out_slot_config->clk = slot->clk;
diff --git a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board_defs.c b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board_defs.c
index 229902ff6f0..533cbde8e26 100644
--- a/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board_defs.c
+++ b/components/esp_driver_sdmmc/test_apps/sd_test_utils/components/sdmmc_test_boards/sdmmc_test_board_defs.c
@@ -323,12 +323,10 @@ static const sdmmc_test_board_info_t s_board_info = {
 static const sdmmc_test_board_info_t s_board_info = {
     .name = "ESP32-P4 Function EV Board",
     .slot = {
-        {
-            .slot_exists = false
-        },
         {
             .slot_exists = true,
             .bus_width = 4,
+            .uhs1_supported = true,
             .clk = 43,
             .cmd_mosi = 44,
             .d0_miso = 39,
@@ -342,6 +340,9 @@ static const sdmmc_test_board_info_t s_board_info = {
             .cd = GPIO_NUM_NC,
             .wp = GPIO_NUM_NC,
             .unused_pin = 54,
+        },
+        {
+            .slot_exists = false,
         }
     },
 };
diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/CMakeLists.txt b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/CMakeLists.txt
index 599b9ffba34..96fe18ea964 100644
--- a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/CMakeLists.txt
+++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/CMakeLists.txt
@@ -9,7 +9,8 @@ if(CONFIG_SOC_SDMMC_HOST_SUPPORTED)
                      "sdmmc_test_erase_sd.c"
                      "sdmmc_test_trim_sd.c"
                      "sdmmc_test_discard_sd.c"
-                     "sdmmc_test_sanitize_sd.c")
+                     "sdmmc_test_sanitize_sd.c"
+                     "sdmmc_test_various_cmds.c")
 endif()
 
 set(priv_requires "sdmmc"
diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.c
index 804bd203b04..cd37a753640 100644
--- a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.c
+++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_begin_end_sd.c
@@ -58,6 +58,7 @@ void sdmmc_test_sd_begin(int slot, int width, int freq_khz, int ddr, sdmmc_card_
     }
 
     config.max_freq_khz = freq_khz;
+    bool slot_is_uhs1 = slot_config.flags & SDMMC_SLOT_FLAG_UHS1;
 
     if (width == 1) {
         config.flags = SDMMC_HOST_FLAG_1BIT;
@@ -78,6 +79,10 @@ void sdmmc_test_sd_begin(int slot, int width, int freq_khz, int ddr, sdmmc_card_
         config.flags |= SDMMC_HOST_FLAG_DDR;
     }
 
+    if (slot_is_uhs1) {
+        slot_config.flags |= SDMMC_SLOT_FLAG_UHS1;
+    }
+
 #if SOC_SDMMC_IO_POWER_EXTERNAL
 #define SDMMC_PWR_LDO_CHANNEL   4
     sd_pwr_ctrl_ldo_config_t ldo_config = {
diff --git a/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_various_cmds.c b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_various_cmds.c
new file mode 100644
index 00000000000..2f05d0ceca2
--- /dev/null
+++ b/components/esp_driver_sdmmc/test_apps/sdmmc/components/sdmmc_tests/sdmmc_test_various_cmds.c
@@ -0,0 +1,73 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+#include <stdlib.h>
+#include <string.h>
+#include "unity.h"
+#include "esp_log.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "driver/sdmmc_defs.h"
+#include "driver/sdmmc_host.h"
+#include "sdmmc_cmd.h"
+#include "esp_private/sdmmc_common.h"
+#include "sdmmc_test_begin_end_sd.h"
+
+#if !SOC_SDMMC_HOST_SUPPORTED
+#error "Targets with SDMMC host supported only"
+#endif // !SOC_SDMMC_HOST_SUPPORTED
+
+static const char* TAG = "sdmmc_test_various_cmds";
+
+static void sdmmc_write_sectors_cmd25_error_test_acmd22(sdmmc_card_t* card, uint32_t write_size)
+{
+    esp_err_t err = ESP_OK;
+    size_t block_size = (size_t)card->csd.sector_size;
+    size_t block_count = write_size / block_size;
+    void* buf = heap_caps_calloc(1, write_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT | MALLOC_CAP_DMA);
+    TEST_ASSERT_NOT_NULL(buf);
+
+    if (!host_is_spi(card)) {
+        err = sdmmc_wait_for_idle(card, 0); // wait for the card to be idle (in transfer state)
+        if (err != ESP_OK) {
+            free(buf);
+        }
+        TEST_ESP_OK(err);
+    }
+
+    // Try to write to the card
+    err = sdmmc_write_sectors(card, buf, 0, block_count);
+    free(buf);
+    TEST_ESP_OK(err);
+
+    // Check if the number of written blocks is equal to the number ACMD22 returns
+    // ACMD22 is usually only called if CMD25 fails but here we call it anyway to test it
+    size_t sucessfully_written_blocks;
+    err = sdmmc_send_cmd_num_of_written_blocks(card, &sucessfully_written_blocks);
+    TEST_ESP_OK(err);
+    TEST_ASSERT_EQUAL_size_t(sucessfully_written_blocks, block_count);
+    ESP_LOGI(TAG, "%s: ACMD22 successfully written %zu blocks out of %zu", __func__, sucessfully_written_blocks, block_count);
+}
+
+static void do_one_mmc_acmd22_test(int slot, int width, int freq_khz, int ddr)
+{
+    sdmmc_card_t card;
+    sdmmc_test_sd_skip_if_board_incompatible(slot, width, freq_khz, ddr);
+    sdmmc_test_sd_begin(slot, width, freq_khz, ddr, &card);
+    sdmmc_card_print_info(stdout, &card);
+    sdmmc_write_sectors_cmd25_error_test_acmd22(&card, 4096 * 4);
+    sdmmc_test_sd_end(&card);
+}
+
+TEST_CASE("send ACMD22 after writing multiple blocks to check real number of successfully written blocks, slot 0, 1-bit", "[sdmmc]")
+{
+    do_one_mmc_acmd22_test(SLOT_0, 1, SDMMC_FREQ_HIGHSPEED, NO_DDR);
+}
+
+TEST_CASE("send ACMD22 after writing multiple blocks to check real number of successfully written blocks, slot 1, 1-bit", "[sdmmc]")
+{
+    do_one_mmc_acmd22_test(SLOT_1, 1, SDMMC_FREQ_HIGHSPEED, NO_DDR);
+}
diff --git a/components/esp_driver_sdspi/include/driver/sdspi_host.h b/components/esp_driver_sdspi/include/driver/sdspi_host.h
index a614d9185cc..091757b5647 100644
--- a/components/esp_driver_sdspi/include/driver/sdspi_host.h
+++ b/components/esp_driver_sdspi/include/driver/sdspi_host.h
@@ -40,6 +40,8 @@ typedef int sdspi_dev_handle_t;
     .slot = SDSPI_DEFAULT_HOST, \
     .max_freq_khz = SDMMC_FREQ_DEFAULT, \
     .io_voltage = 3.3f, \
+    .driver_strength = SDMMC_DRIVER_STRENGTH_B, \
+    .current_limit = SDMMC_CURRENT_LIMIT_200MA, \
     .init = &sdspi_host_init, \
     .set_bus_width = NULL, \
     .get_bus_width = NULL, \
@@ -57,6 +59,7 @@ typedef int sdspi_dev_handle_t;
     .dma_aligned_buffer = NULL, \
     .pwr_ctrl_handle = NULL, \
     .get_dma_info = &sdspi_host_get_dma_info, \
+    .is_slot_set_to_uhs1 = NULL, \
 }
 
 /**
diff --git a/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py b/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py
index a9b13fcfbb2..723b9b08abe 100644
--- a/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py
+++ b/components/esp_driver_sdspi/test_apps/sdspi/pytest_sdspi.py
@@ -4,6 +4,7 @@
 from pytest_embedded_idf import IdfDut
 
 
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C5 C61 GPSPI same, so testing on C5 is enough')
 @pytest.mark.esp32
 @pytest.mark.esp32s3
 @pytest.mark.esp32c3
diff --git a/components/esp_driver_spi/include/driver/spi_common.h b/components/esp_driver_spi/include/driver/spi_common.h
index c0c1918afdb..2f4de6a121a 100644
--- a/components/esp_driver_spi/include/driver/spi_common.h
+++ b/components/esp_driver_spi/include/driver/spi_common.h
@@ -64,6 +64,7 @@ extern "C"
 #define SPICOMMON_BUSFLAG_IO4_IO7       (1<<8)     ///< Check existing of IO4~IO7 pins. Or indicates IO4~IO7 pins initialized.
 #define SPICOMMON_BUSFLAG_OCTAL         (SPICOMMON_BUSFLAG_QUAD|SPICOMMON_BUSFLAG_IO4_IO7)  ///< Check existing of MOSI/MISO/WP/HD/SPIIO4/SPIIO5/SPIIO6/SPIIO7 pins as output. Or indicates bus able to work under octal mode.
 #define SPICOMMON_BUSFLAG_NATIVE_PINS   SPICOMMON_BUSFLAG_IOMUX_PINS
+#define SPICOMMON_BUSFLAG_SLP_ALLOW_PD  (1<<9)     ///< Allow to power down the peripheral during light sleep, and auto recover then.
 
 /**
  * @brief SPI DMA channels
diff --git a/components/esp_driver_spi/src/gpspi/spi_common.c b/components/esp_driver_spi/src/gpspi/spi_common.c
index 7724af5a1cf..1b51593d572 100644
--- a/components/esp_driver_spi/src/gpspi/spi_common.c
+++ b/components/esp_driver_spi/src/gpspi/spi_common.c
@@ -21,6 +21,7 @@
 #include "esp_private/spi_common_internal.h"
 #include "esp_private/spi_share_hw_ctrl.h"
 #include "esp_private/esp_cache_private.h"
+#include "esp_private/sleep_retention.h"
 #include "esp_dma_utils.h"
 #include "hal/spi_hal.h"
 #include "hal/gpio_hal.h"
@@ -49,6 +50,7 @@ static const char *SPI_TAG = "spi";
 
 typedef struct {
     int host_id;
+    _lock_t mutex;      // mutex for controller
     spi_destroy_func_t destroy_func;
     void* destroy_arg;
     spi_bus_attr_t bus_attr;
@@ -587,7 +589,8 @@ esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_conf
     }
 
     uint32_t missing_flag = flags & ~temp_flag;
-    missing_flag &= ~SPICOMMON_BUSFLAG_MASTER;//don't check this flag
+    missing_flag &= ~SPICOMMON_BUSFLAG_MASTER;  //don't check this flag
+    missing_flag &= ~SPICOMMON_BUSFLAG_SLP_ALLOW_PD;
 
     if (missing_flag != 0) {
         //check pins existence
@@ -778,6 +781,16 @@ spi_bus_lock_handle_t spi_bus_lock_get_by_id(spi_host_device_t host_id)
     return bus_ctx[host_id]->bus_attr.lock;
 }
 
+#if SOC_SPI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+static esp_err_t s_bus_create_sleep_retention_cb(void *arg)
+{
+    spicommon_bus_context_t *ctx = arg;
+    return sleep_retention_entries_create(spi_reg_retention_info[ctx->host_id - 1].entry_array,
+                                          spi_reg_retention_info[ctx->host_id - 1].array_size,
+                                          REGDMA_LINK_PRI_GPSPI,
+                                          spi_reg_retention_info[ctx->host_id - 1].module_id);
+}
+#endif  // SOC_SPI_SUPPORT_SLEEP_RETENTION
 //----------------------------------------------------------master bus init-------------------------------------------------------//
 esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *bus_config, spi_dma_chan_t dma_chan)
 {
@@ -846,6 +859,34 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *
         goto cleanup;
     }
 
+#if SOC_SPI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+    sleep_retention_module_init_param_t init_param = {
+        .cbs = {
+            .create = {
+                .handle = s_bus_create_sleep_retention_cb,
+                .arg = ctx,
+            },
+        },
+        .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
+    };
+
+    _lock_acquire(&ctx->mutex);
+    if (sleep_retention_module_init(spi_reg_retention_info[host_id - 1].module_id, &init_param) == ESP_OK) {
+        if ((bus_attr->bus_cfg.flags & SPICOMMON_BUSFLAG_SLP_ALLOW_PD) && (sleep_retention_module_allocate(spi_reg_retention_info[host_id - 1].module_id) != ESP_OK)) {
+            // even though the sleep retention create failed, SPI driver should still work, so just warning here
+            ESP_LOGW(SPI_TAG, "alloc sleep recover failed, peripherals may hold power on");
+        }
+    } else {
+        // even the sleep retention init failed, SPI driver should still work, so just warning here
+        ESP_LOGW(SPI_TAG, "init sleep recover failed, spi may offline after sleep");
+    }
+    _lock_release(&ctx->mutex);
+#else
+    if (bus_attr->bus_cfg.flags & SPICOMMON_BUSFLAG_SLP_ALLOW_PD) {
+        ESP_LOGE(SPI_TAG, "power down peripheral in sleep is not enabled or not supported on your target");
+    }
+#endif  // SOC_SPI_SUPPORT_SLEEP_RETENTION
+
 #ifdef CONFIG_PM_ENABLE
     err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "spi_master",
                              &bus_attr->pm_lock);
@@ -927,9 +968,24 @@ esp_err_t spi_bus_free(spi_host_device_t host_id)
     }
     spicommon_bus_free_io_cfg(&bus_attr->bus_cfg);
 
+#if SOC_SPI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+    const periph_retention_module_t retention_id = spi_reg_retention_info[host_id - 1].module_id;
+    _lock_acquire(&ctx->mutex);
+    if (sleep_retention_get_created_modules() & BIT(retention_id)) {
+        assert(sleep_retention_get_inited_modules() & BIT(retention_id));
+        sleep_retention_module_free(retention_id);
+    }
+    if (sleep_retention_get_inited_modules() & BIT(retention_id)) {
+        sleep_retention_module_deinit(retention_id);
+    }
+    _lock_release(&ctx->mutex);
+    _lock_close(&ctx->mutex);
+#endif
+
 #ifdef CONFIG_PM_ENABLE
     esp_pm_lock_delete(bus_attr->pm_lock);
 #endif
+
     spi_bus_deinit_lock(bus_attr->lock);
     if (ctx->dma_ctx) {
         free(ctx->dma_ctx->dmadesc_tx);
diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c
index bc2ce1967f5..b447b40a5f0 100644
--- a/components/esp_driver_spi/src/gpspi/spi_master.c
+++ b/components/esp_driver_spi/src/gpspi/spi_master.c
@@ -345,8 +345,7 @@ static esp_err_t spi_master_deinit_driver(void* arg)
     int host_id = host->id;
     SPI_CHECK(is_valid_host(host_id), "invalid host_id", ESP_ERR_INVALID_ARG);
 
-    int x;
-    for (x = 0; x < DEV_NUM_MAX; x++) {
+    for (int x = 0; x < DEV_NUM_MAX; x++) {
         SPI_CHECK(host->device[x] == NULL, "not all CSses freed", ESP_ERR_INVALID_STATE);
     }
 
@@ -1416,7 +1415,7 @@ esp_err_t SPI_MASTER_ISR_ATTR spi_device_polling_end(spi_device_handle_t handle,
 
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE   //invalidate here to let user access rx data in post_cb if possible
     const spi_bus_attr_t *bus_attr = host->bus_attr;
-    if (host->cur_trans_buf.buffer_to_rcv) {
+    if (bus_attr->dma_enabled && host->cur_trans_buf.buffer_to_rcv) {
         uint16_t alignment = bus_attr->internal_mem_align_size;
         uint32_t buffer_byte_len = (host->cur_trans_buf.trans->rxlength + 7) / 8;
         buffer_byte_len = (buffer_byte_len + alignment - 1) & (~(alignment - 1));
diff --git a/components/esp_driver_spi/test_apps/.build-test-rules.yml b/components/esp_driver_spi/test_apps/.build-test-rules.yml
index 81f1c69c5cf..9b605ff8552 100644
--- a/components/esp_driver_spi/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_spi/test_apps/.build-test-rules.yml
@@ -9,19 +9,11 @@
 components/esp_driver_spi/test_apps/master:
   disable:
     - if: SOC_GPSPI_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: no multi-dev runner  # TODO: [ESP32C61] IDF-10949
   <<: *spi_depends_default
 
 components/esp_driver_spi/test_apps/param:
   disable:
     - if: SOC_GPSPI_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: no multi-dev runner  # TODO: [ESP32P4] IDF-9517
   <<: *spi_depends_default
 
 components/esp_driver_spi/test_apps/slave:
diff --git a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
index 5dcb6f690f3..2b68f9d0406 100644
--- a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
+++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h
@@ -84,7 +84,7 @@
 #elif CONFIG_IDF_TARGET_ESP32C61
 #define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ                            40*1000*1000
 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING                32
-#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   17
+#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING                   19
 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA         29
 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA            14
 
diff --git a/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt b/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt
index 6af72ca6623..cc99e1467af 100644
--- a/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt
+++ b/components/esp_driver_spi/test_apps/master/main/CMakeLists.txt
@@ -8,7 +8,7 @@ set(srcs
 
 # sct test using slave hd APIs, need slave hd support
 # tmp skip sct test under iram_safe, both sct and slave hd are not cleaned
-if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 AND NOT CONFIG_COMPILER_DUMP_RTL_FILES)
+if(CONFIG_SOC_SPI_SUPPORT_SLAVE_HD_VER2 AND CONFIG_SOC_SPI_SCT_SUPPORTED AND NOT CONFIG_COMPILER_DUMP_RTL_FILES)
     list(APPEND srcs "test_spi_master_sct.c")
 endif()
 
diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
index 4298dcdd222..f3d284d69e7 100644
--- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
+++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c
@@ -19,6 +19,9 @@
 #include "esp_private/cache_utils.h"
 #include "esp_private/spi_common_internal.h"
 #include "esp_private/esp_clk.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/esp_pmu.h"
 #include "esp_heap_caps.h"
 #include "esp_clk_tree.h"
 #include "esp_timer.h"
@@ -1251,6 +1254,7 @@ static void slave_only_tx_trans(uint8_t *slv_send_buf, uint32_t length)
 {
     ESP_LOGI(SLAVE_TAG, "FD DMA, Only TX");
     spi_slave_transaction_t trans = {0};
+    trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO;
     trans.tx_buffer = slv_send_buf;
     trans.length = length * 8;
     unity_send_signal("Slave ready");
@@ -1262,6 +1266,7 @@ static void slave_only_rx_trans(uint8_t *slv_recv_buf, uint8_t *mst_send_buf, ui
 {
     ESP_LOGI(SLAVE_TAG, "FD DMA, Only RX");
     spi_slave_transaction_t trans = {};
+    trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO;
     trans.tx_buffer = NULL;
     trans.rx_buffer = slv_recv_buf;
     trans.length = length * 8;
@@ -1276,6 +1281,7 @@ static void slave_both_trans(uint8_t *slv_send_buf, uint8_t *slv_recv_buf, uint8
 {
     ESP_LOGI(SLAVE_TAG, "FD DMA, Both TX and RX:");
     spi_slave_transaction_t trans = {0};
+    trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO;
     trans.tx_buffer = slv_send_buf;
     trans.rx_buffer = slv_recv_buf;
     trans.length = length * 8;
@@ -1492,6 +1498,8 @@ TEST_CASE("spi_speed", "[spi]")
 #define DUMMY_CS_PINS() {25, 26, 27}
 #elif CONFIG_IDF_TARGET_ESP32H2
 #define DUMMY_CS_PINS() {9, 10, 11, 12, 22, 25}
+#elif CONFIG_IDF_TARGET_ESP32P4
+#define DUMMY_CS_PINS() {20, 21, 22, 23, 24, 25}
 #else
 #define DUMMY_CS_PINS() {0, 1, 4, 5, 8, 9}
 #endif //CONFIG_IDF_TARGET_ESP32
@@ -1575,6 +1583,7 @@ void test_add_device_slave(void)
     slave_trans.length = sizeof(slave_sendbuf) * 8;
     slave_trans.tx_buffer = slave_sendbuf;
     slave_trans.rx_buffer = slave_recvbuf;
+    slave_trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO;
 
     for (uint8_t i = 0; i < SOC_SPI_MAX_CS_NUM; i++) {
         memset(slave_recvbuf, 0, sizeof(slave_recvbuf));
@@ -1697,7 +1706,6 @@ static IRAM_ATTR void test_master_iram(void)
     spi_flash_enable_interrupts_caches_and_other_cpu();
 
     ESP_LOG_BUFFER_HEX("master tx", ret_trans->tx_buffer, TEST_MASTER_IRAM_TRANS_LEN);
-    ESP_LOG_BUFFER_HEX("master rx", ret_trans->rx_buffer, TEST_MASTER_IRAM_TRANS_LEN);
     spitest_cmp_or_dump(master_exp, trans_cfg.rx_buffer, TEST_MASTER_IRAM_TRANS_LEN);
 
     // Test polling trans api once -------------------------------
@@ -1709,13 +1717,12 @@ static IRAM_ATTR void test_master_iram(void)
     spi_flash_enable_interrupts_caches_and_other_cpu();
 
     ESP_LOG_BUFFER_HEX("master tx", ret_trans->tx_buffer, TEST_MASTER_IRAM_TRANS_LEN);
-    ESP_LOG_BUFFER_HEX("master rx", ret_trans->rx_buffer, TEST_MASTER_IRAM_TRANS_LEN);
     spitest_cmp_or_dump(master_exp, trans_cfg.rx_buffer, TEST_MASTER_IRAM_TRANS_LEN);
 
     free(master_send);
     free(master_recv);
     free(master_exp);
-    spi_bus_remove_device(dev_handle);
+    TEST_ESP_OK(spi_bus_remove_device(dev_handle));
     spi_bus_free(TEST_SPI_HOST);
 }
 
@@ -1733,20 +1740,19 @@ static void test_iram_slave_normal(void)
     slave_trans.length = TEST_MASTER_IRAM_TRANS_LEN * 8;
     slave_trans.tx_buffer = slave_sendbuf;
     slave_trans.rx_buffer = slave_recvbuf;
+    slave_trans.flags |= SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO;
     test_fill_random_to_buffers_dualboard(211, slave_expect, slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN);
 
     unity_wait_for_signal("Master ready");
     unity_send_signal("Slave ready");
-    spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY);
+    TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY));
     ESP_LOG_BUFFER_HEX("slave tx", slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN);
-    ESP_LOG_BUFFER_HEX("slave rx", slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN);
     spitest_cmp_or_dump(slave_expect, slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN);
 
     unity_send_signal("Slave ready");
     test_fill_random_to_buffers_dualboard(119, slave_expect, slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN);
-    spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY);
+    TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &slave_trans, portMAX_DELAY));
     ESP_LOG_BUFFER_HEX("slave tx", slave_sendbuf, TEST_MASTER_IRAM_TRANS_LEN);
-    ESP_LOG_BUFFER_HEX("slave rx", slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN);
     spitest_cmp_or_dump(slave_expect, slave_recvbuf, TEST_MASTER_IRAM_TRANS_LEN);
 
     free(slave_sendbuf);
@@ -1785,3 +1791,133 @@ TEST_CASE("test_bus_free_safty_to_remain_devices", "[spi]")
     TEST_ESP_OK(spi_bus_remove_device(dev1));
     TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
 }
+
+TEST_CASE("test_spi_master_sleep_retention", "[spi]")
+{
+    // Prepare a TOP PD sleep
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+
+    spi_device_handle_t dev_handle;
+    spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
+    spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
+    buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS;
+    buscfg.flags |= SPICOMMON_BUSFLAG_SLP_ALLOW_PD;
+    uint8_t send[16] = "hello spi x\n";
+    uint8_t recv[16];
+    spi_transaction_t trans_cfg = {
+        .length = 8 * sizeof(send),
+        .tx_buffer = send,
+        .rx_buffer = recv,
+    };
+
+    for (int periph = SPI2_HOST; periph < SPI_HOST_MAX; periph ++) {
+        for (int test_dma = 0; test_dma <= 1; test_dma ++) {
+            int use_dma = SPI_DMA_DISABLED;
+#if SOC_GDMA_SUPPORT_SLEEP_RETENTION    // TODO: IDF-11317 test dma on esp32 and s2
+            use_dma = test_dma ? SPI_DMA_CH_AUTO : SPI_DMA_DISABLED;
+#endif
+            printf("Retention on GPSPI%d with dma: %d\n", periph + 1, use_dma);
+            TEST_ESP_OK(spi_bus_initialize(periph, &buscfg, use_dma));
+            // set spi "self-loop" after bus initialized
+            spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[periph].spid_out);
+            TEST_ESP_OK(spi_bus_add_device(periph, &devcfg, &dev_handle));
+
+            for (uint8_t cnt = 0; cnt < 3; cnt ++) {
+                printf("Going into sleep...\n");
+                TEST_ESP_OK(esp_light_sleep_start());
+                printf("Waked up!\n");
+
+                // check if the sleep happened as expected
+                TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_SPI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+                // check if the power domain also is powered down
+                TEST_ASSERT_EQUAL((buscfg.flags & SPICOMMON_BUSFLAG_SLP_ALLOW_PD) ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+                memset(recv, 0, sizeof(recv));
+                send[10] = cnt + 'A';
+                TEST_ESP_OK(spi_device_transmit(dev_handle, &trans_cfg));
+                printf("%s", recv);
+                spitest_cmp_or_dump(trans_cfg.tx_buffer, trans_cfg.rx_buffer, sizeof(send));
+            }
+
+            TEST_ESP_OK(spi_bus_remove_device(dev_handle));
+            TEST_ESP_OK(spi_bus_free(periph));
+        }
+    }
+
+    esp_sleep_set_sleep_context(NULL);
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+}
+
+#if CONFIG_PM_ENABLE
+TEST_CASE("test_spi_master_auto_sleep_retention", "[spi]")
+{
+    // Configure dynamic frequency scaling:
+    // maximum and minimum frequencies are set in sdkconfig,
+    // automatic light sleep is enabled if tickless idle support is enabled.
+    uint32_t xtal_hz = 0;
+    esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_XTAL, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &xtal_hz);
+    esp_pm_config_t pm_config = {
+        .max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
+        .min_freq_mhz = xtal_hz / 1000000,
+#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
+        .light_sleep_enable = true,
+#endif
+    };
+    TEST_ESP_OK(esp_pm_configure(&pm_config));
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+
+    for (uint8_t allow_pd = 0; allow_pd < 2; allow_pd ++) {
+        spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
+        buscfg.flags = (allow_pd) ? SPICOMMON_BUSFLAG_SLP_ALLOW_PD : 0;
+        buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS;
+        TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_DISABLED));
+        // set spi "self-loop" after bus initialized
+        spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
+
+        spi_device_handle_t dev_handle;
+        spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
+        TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg, &dev_handle));
+
+        uint8_t send[13] = "hello spi 0\n";
+        uint8_t recv[13];
+        spi_transaction_t trans_cfg = {
+            .length = 8 * sizeof(send),
+            .tx_buffer = send,
+            .rx_buffer = recv,
+        };
+
+        for (uint8_t cnt = 0; cnt < 3; cnt ++) {
+            printf("Going into Auto sleep with power %s ...\n", (buscfg.flags & SPICOMMON_BUSFLAG_SLP_ALLOW_PD) ? "down" : "hold");
+            vTaskDelay(1000);   //auto light sleep here
+            printf("Waked up!\n");
+
+            // check if the sleep happened as expected
+            TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_SPI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+            // check if the power domain also is powered down
+            TEST_ASSERT_EQUAL((buscfg.flags & SPICOMMON_BUSFLAG_SLP_ALLOW_PD) ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+            memset(recv, 0, sizeof(recv));
+            send[10] = cnt + '0';
+            TEST_ESP_OK(spi_device_polling_transmit(dev_handle, &trans_cfg));
+            printf("%s", recv);
+            spitest_cmp_or_dump(trans_cfg.tx_buffer, trans_cfg.rx_buffer, sizeof(send));
+        }
+
+        TEST_ESP_OK(spi_bus_remove_device(dev_handle));
+        TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
+    }
+    esp_sleep_set_sleep_context(NULL);
+    pm_config.light_sleep_enable = false;
+    TEST_ESP_OK(esp_pm_configure(&pm_config));
+}
+#endif  //CONFIG_PM_ENABLE
diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c
index 2efb4184d91..d0e203704d3 100644
--- a/components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c
+++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c
@@ -15,6 +15,9 @@
 #include "esp_heap_caps.h"
 #include "driver/spi_master.h"
 #include "esp_private/spi_master_internal.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/esp_pmu.h"
 #include "driver/spi_slave_hd.h"
 #include "driver/spi_slave.h"
 #include "soc/spi_pins.h"
@@ -22,7 +25,6 @@
 
 __attribute__((unused)) static const char *TAG = "SCT";
 
-#if (SOC_SPI_SUPPORT_SLAVE_HD_VER2 && SOC_SPI_SCT_SUPPORTED)
 /*-----------------------------------------------------------
  * HD SCT Functional Test
  *-----------------------------------------------------------*/
@@ -230,7 +232,6 @@ TEST_CASE_MULTIPLE_DEVICES("SPI_Master_SCT_HD_Functional", "[spi_ms]", hd_master
 TEST_CASE("spi_master: test_sct_dma_desc_oob_on_tail", "[spi]")
 {
     spi_device_handle_t handle;
-
     spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
     buscfg.max_transfer_sz = 4092 * 8;
 
@@ -291,4 +292,127 @@ TEST_CASE("spi_master: test_sct_dma_desc_oob_on_tail", "[spi]")
     TEST_ESP_OK(spi_bus_free(SPI2_HOST));
 }
 
-#endif  //#if (SOC_SPI_SUPPORT_SLAVE_HD_VER2 && SOC_SPI_SCT_SUPPORTED)
+/*-----------------------------------------------------------
+ * Sleep Retention Test
+ *-----------------------------------------------------------*/
+#define TEST_SLP_DATA_LEN               64
+//Master write, slave read, wrt slave reg
+#define TEST_SLP_BUF_ID                 12
+#define TEST_SLP_BUF_VAL                0x11223344
+
+static void sleep_master(void)
+{
+    // Prepare a TOP PD sleep
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
+#if ESP_SLEEP_POWER_DOWN_CPU
+    sleep_cpu_configure(true);
+#endif
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+
+    spi_device_handle_t handle;
+    spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
+    buscfg.max_transfer_sz = 4092 * 10;
+#if SOC_SPI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+    buscfg.flags |= SPICOMMON_BUSFLAG_SLP_ALLOW_PD;
+#endif
+    spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
+    devcfg.command_bits = 8;
+    devcfg.address_bits = 8;
+    devcfg.dummy_bits = 8;
+    devcfg.flags = SPI_DEVICE_HALFDUPLEX;
+    TEST_ESP_OK(spi_bus_initialize(SPI2_HOST, &buscfg, SPI_DMA_CH_AUTO));
+    TEST_ESP_OK(spi_bus_add_device(SPI2_HOST, &devcfg, &handle));
+    TEST_ESP_OK(spi_bus_multi_trans_mode_enable(handle, true));
+    unity_send_signal("Master ready");
+
+    //Test data preparation
+    uint32_t master_tx_val = TEST_SLP_BUF_VAL;
+    uint8_t *master_tx_buf = heap_caps_calloc(1, TEST_SLP_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+    test_fill_random_to_buffers_dualboard(199, master_tx_buf, master_tx_buf, TEST_SLP_DATA_LEN);
+    //---------------------Master TX---------------------------//
+    spi_multi_transaction_t *ret_seg_trans = NULL;
+    spi_multi_transaction_t tx_seg_trans[3] = {
+        {
+            .base = {
+                .cmd = 0x1,
+                .addr = TEST_SLP_BUF_ID,
+                .length = 4 * 8,
+                .tx_buffer = (uint8_t *) &master_tx_val,
+            },
+        },
+        {
+            .base = {
+                .cmd = 0x3,
+                .addr = 0xf2,
+                .length = TEST_SLP_DATA_LEN * 8,
+                .tx_buffer = master_tx_buf,
+            },
+            .dummy_bits = 8,
+        },
+        {
+            .base = {
+                .cmd = 0x7,
+            },
+        },
+    };
+
+    unity_wait_for_signal("Slave ready");
+    printf("Going into sleep with power down ...\n");
+    TEST_ESP_OK(esp_light_sleep_start());
+    printf("Waked up!\n");
+    // check if the sleep happened as expected
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_SPI_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL((buscfg.flags & SPICOMMON_BUSFLAG_SLP_ALLOW_PD) ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+    TEST_ESP_OK(spi_device_queue_multi_trans(handle, tx_seg_trans, 3, portMAX_DELAY));
+    TEST_ESP_OK(spi_device_get_multi_trans_result(handle, &ret_seg_trans, portMAX_DELAY));
+    TEST_ASSERT(ret_seg_trans == tx_seg_trans);
+    ESP_LOG_BUFFER_HEX("Master tx", master_tx_buf, TEST_SLP_DATA_LEN);
+
+    free(master_tx_buf);
+    TEST_ESP_OK(spi_bus_multi_trans_mode_enable(handle, false));
+    TEST_ESP_OK(spi_bus_remove_device(handle));
+    TEST_ESP_OK(spi_bus_free(SPI2_HOST));
+    esp_sleep_set_sleep_context(NULL);
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+}
+
+static void sleep_slave(void)
+{
+    spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
+    spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG();
+    slave_hd_cfg.dma_chan = SPI_DMA_CH_AUTO,
+    TEST_ESP_OK(spi_slave_hd_init(SPI2_HOST, &buscfg, &slave_hd_cfg));
+
+    //Test data preparation
+    uint32_t slave_rx_val = 0;
+    uint8_t *slave_rx_buf = heap_caps_calloc(1, TEST_SLP_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+    uint8_t *master_tx_buf = heap_caps_calloc(1, TEST_SLP_DATA_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+    test_fill_random_to_buffers_dualboard(199, master_tx_buf, master_tx_buf, TEST_SLP_DATA_LEN);
+    //---------------------Slave RX---------------------------//
+    spi_slave_hd_data_t *ret_trans = NULL;
+    spi_slave_hd_data_t slave_rx_trans = {
+        .data = slave_rx_buf,
+        .len = TEST_SLP_DATA_LEN,
+    };
+    unity_wait_for_signal("Master ready");
+    TEST_ESP_OK(spi_slave_hd_queue_trans(SPI2_HOST, SPI_SLAVE_CHAN_RX, &slave_rx_trans, portMAX_DELAY));
+    unity_send_signal("Slave ready");
+    TEST_ESP_OK(spi_slave_hd_get_trans_res(SPI2_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
+    TEST_ASSERT(ret_trans == &slave_rx_trans);
+
+    spitest_cmp_or_dump(master_tx_buf, slave_rx_buf, TEST_SLP_DATA_LEN);
+    spi_slave_hd_read_buffer(SPI2_HOST, TEST_SLP_BUF_ID, (uint8_t *)&slave_rx_val, 4);
+    ESP_LOGI("Slave", "Slave Reg[%d] value is: 0x%" PRIx32, TEST_SLP_BUF_ID, slave_rx_val);
+    TEST_ASSERT(slave_rx_val == TEST_SLP_BUF_VAL);
+
+    free(master_tx_buf);
+    free(slave_rx_buf);
+    TEST_ESP_OK(spi_slave_hd_deinit(SPI2_HOST));
+}
+TEST_CASE_MULTIPLE_DEVICES("test_spi_master_sct_sleep_retention", "[spi_ms]", sleep_master, sleep_slave);
diff --git a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py
index 1ac833a84de..691929a135a 100644
--- a/components/esp_driver_spi/test_apps/master/pytest_spi_master.py
+++ b/components/esp_driver_spi/test_apps/master/pytest_spi_master.py
@@ -5,7 +5,6 @@
 
 # If `test_env` is define, should not run on generic runner
 @pytest.mark.supported_targets
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='test case fail')    # TODO: [ESP32C61] IDF-10949
 @pytest.mark.generic
 @pytest.mark.parametrize('config', ['defaults', 'release', 'freertos_compliance', 'freertos_flash',], indirect=True)
 def test_master_single_dev(case_tester) -> None:       # type: ignore
@@ -27,8 +26,8 @@ def test_master_esp_flash(case_tester) -> None:        # type: ignore
 
 
 # if `test_env` not defined, will run on `generic_multi_device` by default
-# TODO: [ESP32P4] IDF-9517 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949
-@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner')
+# TODO: [ESP32C61] IDF-10949
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='no multi-dev runner')
 @pytest.mark.supported_targets
 @pytest.mark.generic_multi_device
 @pytest.mark.parametrize(
diff --git a/components/esp_driver_spi/test_apps/master/sdkconfig.ci.defaults b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.defaults
deleted file mode 100644
index 250a29bc45b..00000000000
--- a/components/esp_driver_spi/test_apps/master/sdkconfig.ci.defaults
+++ /dev/null
@@ -1,2 +0,0 @@
-# don't delete.
-# used for CI to compile a default config when 'sdkconfig.ci.xxxx' is exist
diff --git a/components/esp_driver_spi/test_apps/master/sdkconfig.ci.freertos_compliance b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.freertos_compliance
index c3eaa50fa4b..272fdd42852 100644
--- a/components/esp_driver_spi/test_apps/master/sdkconfig.ci.freertos_compliance
+++ b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.freertos_compliance
@@ -1 +1,3 @@
+CONFIG_PM_ENABLE=y
+CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
 CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE=y
diff --git a/components/esp_driver_spi/test_apps/master/sdkconfig.ci.release b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.release
index 3cff15d49e2..ee9acb0df40 100644
--- a/components/esp_driver_spi/test_apps/master/sdkconfig.ci.release
+++ b/components/esp_driver_spi/test_apps/master/sdkconfig.ci.release
@@ -1,3 +1,4 @@
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
 CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
diff --git a/components/esp_driver_spi/test_apps/master/sdkconfig.defaults b/components/esp_driver_spi/test_apps/master/sdkconfig.defaults
index b308cb2ddda..fff8c78591b 100644
--- a/components/esp_driver_spi/test_apps/master/sdkconfig.defaults
+++ b/components/esp_driver_spi/test_apps/master/sdkconfig.defaults
@@ -1,2 +1,4 @@
 CONFIG_FREERTOS_HZ=1000
-CONFIG_ESP_TASK_WDT=n
+CONFIG_ESP_TASK_WDT_INIT=n
+# primitives for checking sleep internal state
+CONFIG_ESP_SLEEP_DEBUG=y
diff --git a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
index 627f4ad492a..7f507a549b9 100644
--- a/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
+++ b/components/esp_driver_spi/test_apps/param/main/test_spi_param.c
@@ -109,6 +109,10 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p
         devcfg.flags |= SPI_DEVICE_NO_DUMMY;
     }
 
+#if CONFIG_IDF_TARGET_ESP32P4      //TODO: IDF-8313, update P4 defaulte clock source
+    devcfg.clock_source = SPI_CLK_SRC_SPLL;
+#endif
+
     //slave config
     slvcfg.mode = pset->mode;
     slave_pull_up(&buscfg, slvcfg.spics_io_num);
@@ -192,6 +196,7 @@ static void local_test_loop(const void *arg1, void *arg2)
                 .tx_buffer = txdata->start,
                 .rx_buffer = recvbuf,
                 .length = txdata->len,
+                .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO,
             };
             esp_err_t err = spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_trans, portMAX_DELAY);
             TEST_ESP_OK(err);
@@ -247,8 +252,7 @@ static void local_test_loop(const void *arg1, void *arg2)
 /************ Timing Test ***********************************************/
 //TODO: esp32s2 has better timing performance
 static spitest_param_set_t timing_pgroup[] = {
-//signals are not fed to peripherals through iomux if the functions are not selected to iomux
-#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
+#if (SLAVE_IOMUX_PIN_MISO != -1)    //SPI3 slave has iomux pin
     {
         .pset_name = "FULL_DUP, MASTER IOMUX",
         .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
@@ -277,8 +281,7 @@ static spitest_param_set_t timing_pgroup[] = {
         .slave_iomux = false,
         .slave_tv_ns = TV_INT_CONNECT_GPIO,
     },
-//signals are not fed to peripherals through iomux if the functions are not selected to iomux
-#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
+#if (SLAVE_IOMUX_PIN_MISO != -1)    //SPI3 slave has iomux pin
     {
         .pset_name = "MISO_DUP, MASTER IOMUX",
         .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
@@ -307,8 +310,7 @@ static spitest_param_set_t timing_pgroup[] = {
         .slave_iomux = false,
         .slave_tv_ns = TV_INT_CONNECT_GPIO,
     },
-//signals are not fed to peripherals through iomux if the functions are not selected to iomux
-#if !DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
+#if (SLAVE_IOMUX_PIN_MISO != -1)    //SPI3 slave has iomux pin
     {
         .pset_name = "MOSI_DUP, MASTER IOMUX",
         .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
@@ -616,7 +618,8 @@ TEST_CASE("Slave receive correct data", "[spi]")
                 spi_slave_transaction_t slave_trans = {
                     .length = slave_trans_len * 8,
                     .tx_buffer = slave_sendbuf,
-                    .rx_buffer = slave_recvbuf
+                    .rx_buffer = slave_recvbuf,
+                    .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO,
                 };
                 esp_err_t ret = spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_trans, portMAX_DELAY);
                 TEST_ESP_OK(ret);
@@ -1270,7 +1273,9 @@ static int s_spi_bus_freq[] = {
     IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 7,
     IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 4,
     IDF_PERFORMANCE_MAX_SPI_CLK_FREQ / 2,
+#if !CONFIG_IDF_TARGET_ESP32P4      //TODO: IDF-8313, update P4 defaulte clock source
     IDF_PERFORMANCE_MAX_SPI_CLK_FREQ,
+#endif
 };
 
 //------------------------------------------- Full Duplex with DMA Freq test --------------------------------------
@@ -1433,7 +1438,7 @@ static void test_master_fd_no_dma(void)
                         .length = test_trans_len * 8,
                     };
                     unity_wait_for_signal("Slave ready");
-                    TEST_ESP_OK(spi_device_transmit(dev0, &trans_cfg));
+                    TEST_ESP_OK(spi_device_polling_transmit(dev0, &trans_cfg));
 
                     ESP_LOG_BUFFER_HEX("master tx", master_send, test_trans_len);
                     ESP_LOG_BUFFER_HEX_LEVEL("master rx", master_receive, test_trans_len, ESP_LOG_DEBUG);
@@ -1483,6 +1488,7 @@ static void test_slave_fd_no_dma(void)
                         .tx_buffer = slave_send,
                         .rx_buffer = slave_receive,
                         .length = test_trans_len * 8,
+                        .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO,
                     };
                     unity_send_signal("Slave ready");
                     TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans_cfg, portMAX_DELAY));
@@ -1587,6 +1593,7 @@ static void test_slave_hd_dma(void)
                     TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_trans, portMAX_DELAY));
                     slave_trans.data = slave_receive;
                     TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_trans, portMAX_DELAY));
+                    TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));
                     TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
 
                     ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len);
@@ -1688,6 +1695,7 @@ static void test_slave_hd_no_dma(void)
                     TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_trans, portMAX_DELAY));
                     slave_trans.data = slave_receive;
                     TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_trans, portMAX_DELAY));
+                    TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));
                     TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
 
                     ESP_LOG_BUFFER_HEX("slave tx", slave_send, test_trans_len);
@@ -1951,6 +1959,7 @@ static void test_slave_sio_no_dma(void)
                         .length = SOC_SPI_MAXIMUM_BUFFER_SIZE * 8,
                         .tx_buffer = slave_send,
                         .rx_buffer = slave_receive,
+                        .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO,
                     };
                     unity_send_signal("Slave ready");
                     TEST_ESP_OK(spi_slave_transmit(TEST_SPI_HOST, &trans, portMAX_DELAY));
diff --git a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py
index d565235e9c8..d7df6964106 100644
--- a/components/esp_driver_spi/test_apps/param/pytest_spi_param.py
+++ b/components/esp_driver_spi/test_apps/param/pytest_spi_param.py
@@ -4,9 +4,7 @@
 
 
 # If `test_env` is define, should not run on generic runner
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 support TBD')  # TODO: IDF-8942
 @pytest.mark.supported_targets
-@pytest.mark.esp32h2
 @pytest.mark.generic
 def test_param_single_dev(case_tester) -> None:       # type: ignore
     for case in case_tester.test_menu:
@@ -16,10 +14,9 @@ def test_param_single_dev(case_tester) -> None:       # type: ignore
 
 
 # if `test_env` not defined, will run on `generic_multi_device` by default
-# TODO: [ESP32P4] IDF-8942 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949
-@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner')
+# TODO: [ESP32C61] IDF-10949
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='no multi-dev runner')
 @pytest.mark.supported_targets
-@pytest.mark.esp32h2
 @pytest.mark.generic_multi_device
 @pytest.mark.parametrize('count', [2,], indirect=True)
 def test_param_multi_dev(case_tester) -> None:        # type: ignore
diff --git a/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c b/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
index 8a27902e716..f5634dbba91 100644
--- a/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
+++ b/components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
@@ -162,7 +162,7 @@ TEST_CASE("Test slave rx no_dma overwrite when length below/over config", "[spi]
         .length = 8 * 7,
         .tx_buffer = master_tx,
     };
-    spi_device_transmit(spidev0, &master_tans);
+    spi_device_polling_transmit(spidev0, &master_tans);
 
     TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &slave_out, portMAX_DELAY));
 
@@ -181,7 +181,7 @@ TEST_CASE("Test slave rx no_dma overwrite when length below/over config", "[spi]
     TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_tans, portMAX_DELAY));
 
     master_tans.length = 8 * 11,
-    spi_device_transmit(spidev0, &master_tans);
+    spi_device_polling_transmit(spidev0, &master_tans);
 
     TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &slave_out, portMAX_DELAY));
 
@@ -562,6 +562,7 @@ static IRAM_ATTR void test_slave_isr_iram(void)
 }
 TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_ISR_IRAM_disable_cache", "[spi_ms]", test_slave_iram_master_normal, test_slave_isr_iram);
 
+#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE //isr option is not supported in this condition
 static uint32_t isr_trans_cnt, isr_trans_test_fail;
 static IRAM_ATTR void test_trans_in_isr_post_trans_cbk(spi_slave_transaction_t *curr_trans)
 {
@@ -725,6 +726,7 @@ static IRAM_ATTR void spi_queue_reset_in_isr(void)
     spi_slave_free(TEST_SPI_HOST);
 }
 TEST_CASE_MULTIPLE_DEVICES("SPI_Slave: Test_Queue_Reset_in_ISR", "[spi_ms]", test_slave_iram_master_normal, spi_queue_reset_in_isr);
+#endif  // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
 #endif  // CONFIG_SPI_SLAVE_ISR_IN_IRAM
 
 #if (SOC_CPU_CORES_NUM > 1) && (!CONFIG_FREERTOS_UNICORE)
diff --git a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py
index b39e7f94847..5b9f8823dc2 100644
--- a/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py
+++ b/components/esp_driver_spi/test_apps/slave/pytest_spi_slave.py
@@ -15,8 +15,8 @@ def test_slave_single_dev(case_tester) -> None:       # type: ignore
 
 
 # if `test_env` not defined, will run on `generic_multi_device` by default
-# TODO: [ESP32P4] IDF-9517 [ESP32C5] IDF-10322 [ESP32C61] IDF-10949
-@pytest.mark.temp_skip_ci(targets=['esp32p4', 'esp32c5', 'esp32c61'], reason='no multi-dev runner')
+# TODO: [ESP32C61] IDF-10949
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='no multi-dev runner')
 @pytest.mark.supported_targets
 @pytest.mark.generic_multi_device
 @pytest.mark.parametrize('count, config', [(2, 'defaults'), (2, 'iram_safe')], indirect=True)
diff --git a/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c b/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
index 397a30f4a1a..eea77e52c33 100644
--- a/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
+++ b/components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -855,19 +855,23 @@ static void hd_slave_quad(void)
         {
             .data = slave_recv_buf,
             .len = (trans_len + 3) & (~3),
+            .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO,
         },
         {
             .data = slave_recv_buf + BUF_SIZE / 2,
             .len = (trans_len + 3) & (~3),
+            .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO,
         },
         //send
         {
             .data = slave_send_buf,
             .len = (trans_len + 3) & (~3),
+            .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO,
         },
         {
             .data = slave_send_buf + BUF_SIZE / 2,
             .len = (trans_len + 3) & (~3),
+            .flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO,
         },
     };
 
@@ -901,7 +905,7 @@ static void hd_slave_quad(void)
     spi_slave_hd_deinit(TEST_SLAVE_HOST);
 }
 
-TEST_CASE_MULTIPLE_DEVICES("SPI quad hd test ", "[spi_ms][test_env=generic_multi_device]", hd_master_quad, hd_slave_quad);
+TEST_CASE_MULTIPLE_DEVICES("SPI quad hd test", "[spi_ms][test_env=generic_multi_device]", hd_master_quad, hd_slave_quad);
 
 #endif  // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
 
@@ -941,6 +945,7 @@ void slave_run_append(void)
         slave_rx_trans[append_idx].data = heap_caps_aligned_calloc(4, 1, TEST_TRANS_LEN, MALLOC_CAP_DMA);
         TEST_ASSERT_NOT_NULL(slave_rx_trans[append_idx].data);
         slave_rx_trans[append_idx].len = trans_len;
+        slave_rx_trans[append_idx].flags |= SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO;
         TEST_ESP_OK(spi_slave_hd_append_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_RX, &slave_rx_trans[append_idx], portMAX_DELAY));
     }
 
@@ -982,6 +987,7 @@ void slave_run_append(void)
         }
         slave_tx_trans[append_idx].data = slave_rx_trans[append_idx].data;
         slave_tx_trans[append_idx].len = trans_len;
+        slave_tx_trans[append_idx].flags |= SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO;
         prepare_data(slave_tx_trans[append_idx].data, trans_len, -3);
         TEST_ESP_OK(spi_slave_hd_append_trans(TEST_SPI_HOST, SPI_SLAVE_CHAN_TX, &slave_tx_trans[append_idx], portMAX_DELAY));
     }
diff --git a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py
index d8470588460..5d09b75f069 100644
--- a/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py
+++ b/components/esp_driver_spi/test_apps/slave_hd/pytest_spi_slave_hd.py
@@ -26,8 +26,10 @@ def test_slave_hd_single_dev(case_tester) -> None:       # type: ignore
 @pytest.mark.esp32s3
 @pytest.mark.esp32c2
 @pytest.mark.esp32c3
+@pytest.mark.esp32c5
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
+@pytest.mark.esp32p4
 @pytest.mark.generic_multi_device
 @pytest.mark.parametrize('count', [2,], indirect=True)
 def test_slave_hd_multi_dev(case_tester) -> None:        # type: ignore
diff --git a/components/esp_driver_touch_sens/CMakeLists.txt b/components/esp_driver_touch_sens/CMakeLists.txt
index e2a0c6040f8..d7f47492ad3 100644
--- a/components/esp_driver_touch_sens/CMakeLists.txt
+++ b/components/esp_driver_touch_sens/CMakeLists.txt
@@ -8,10 +8,11 @@ set(srcs)
 set(public_inc)
 
 if(CONFIG_SOC_TOUCH_SENSOR_SUPPORTED)
-    if(CONFIG_SOC_TOUCH_SENSOR_VERSION EQUAL 3)
-        list(APPEND srcs "hw_ver3/touch_version_specific.c"
-                         "common/touch_sens_common.c")
-        list(APPEND public_inc  "include" "hw_ver3/include")
+    set(version_folder "hw_ver${CONFIG_SOC_TOUCH_SENSOR_VERSION}")
+    if(CONFIG_SOC_TOUCH_SENSOR_VERSION GREATER 1)
+        list(APPEND srcs "common/touch_sens_common.c"
+                         "${version_folder}/touch_version_specific.c")
+        list(APPEND public_inc  "include" "${version_folder}/include")
     endif()
 endif()
 
diff --git a/components/esp_driver_touch_sens/common/touch_sens_common.c b/components/esp_driver_touch_sens/common/touch_sens_common.c
index f5119c72372..f13f47848d3 100644
--- a/components/esp_driver_touch_sens/common/touch_sens_common.c
+++ b/components/esp_driver_touch_sens/common/touch_sens_common.c
@@ -21,12 +21,14 @@
 #include "soc/interrupts.h"
 #include "esp_intr_alloc.h"
 #endif
+#include "esp_private/touch_sens_helper.h"
 
 #if CONFIG_TOUCH_ENABLE_DEBUG_LOG
 // The local log level must be defined before including esp_log.h
 // Set the maximum log level for this source file
 #define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
 #endif
+#include "esp_log.h"
 #include "esp_check.h"
 #include "touch_sens_private.h"
 
@@ -72,7 +74,7 @@ esp_err_t touch_sensor_new_controller(const touch_sensor_config_t *sens_cfg, tou
     g_touch = (touch_sensor_handle_t)heap_caps_calloc(1, sizeof(struct touch_sensor_s), TOUCH_MEM_ALLOC_CAPS);
     ESP_RETURN_ON_FALSE(g_touch, ESP_ERR_NO_MEM, TAG, "No memory for touch sensor struct");
 
-    g_touch->mutex = xSemaphoreCreateMutexWithCaps(TOUCH_MEM_ALLOC_CAPS);
+    g_touch->mutex = xSemaphoreCreateRecursiveMutexWithCaps(TOUCH_MEM_ALLOC_CAPS);
     ESP_GOTO_ON_FALSE(g_touch->mutex, ESP_ERR_NO_MEM, err, TAG, "No memory for mutex semaphore");
 
     touch_priv_enable_module(true);
@@ -99,7 +101,7 @@ esp_err_t touch_sensor_del_controller(touch_sensor_handle_t sens_handle)
 
     esp_err_t ret = ESP_OK;
     // Take the semaphore to make sure the touch has stopped
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Touch sensor has not disabled");
     FOR_EACH_TOUCH_CHANNEL(i) {
         ESP_GOTO_ON_FALSE(!sens_handle->ch[i], ESP_ERR_INVALID_STATE, err, TAG, "There are still some touch channels not deleted");
@@ -112,7 +114,7 @@ esp_err_t touch_sensor_del_controller(touch_sensor_handle_t sens_handle)
     ESP_GOTO_ON_ERROR(esp_intr_free(sens_handle->intr_handle), err, TAG, "Failed to deregister the interrupt handler");
 #endif
     TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
-    touch_ll_intr_disable(TOUCH_LL_INTR_MASK_ALL);
+    touch_ll_interrupt_disable(TOUCH_LL_INTR_MASK_ALL);
     touch_ll_clear_active_channel_status();
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
 
@@ -120,7 +122,7 @@ esp_err_t touch_sensor_del_controller(touch_sensor_handle_t sens_handle)
     s_touch_free_resource(sens_handle);
 err:
     if (g_touch && g_touch->mutex) {
-        xSemaphoreGive(g_touch->mutex);
+        xSemaphoreGiveRecursive(g_touch->mutex);
     }
     return ret;
 }
@@ -133,10 +135,11 @@ esp_err_t touch_sensor_new_channel(touch_sensor_handle_t sens_handle, int chan_i
     TOUCH_NULL_POINTER_CHECK(chan_cfg);
     TOUCH_NULL_POINTER_CHECK(ret_chan_handle);
     TOUCH_CHANNEL_CHECK(chan_id);
+
     ESP_RETURN_ON_FALSE(g_touch == sens_handle, ESP_ERR_INVALID_ARG, TAG, "The input touch sensor handle is unmatched");
 
     esp_err_t ret = ESP_OK;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
 
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err2, TAG, "Please disable the touch sensor first");
     ESP_GOTO_ON_FALSE(!sens_handle->ch[chan_id], ESP_ERR_INVALID_STATE, err2, TAG, "The channel %d has been registered", chan_id);
@@ -145,29 +148,29 @@ esp_err_t touch_sensor_new_channel(touch_sensor_handle_t sens_handle, int chan_i
     ESP_GOTO_ON_FALSE(sens_handle->ch[chan_id], ESP_ERR_NO_MEM, err2, TAG, "No memory for touch channel");
     sens_handle->ch[chan_id]->id = chan_id;
     sens_handle->ch[chan_id]->base = sens_handle;
-    sens_handle->ch[chan_id]->is_prox_chan = false;
+    sens_handle->ch[chan_id]->prox_id = 0;
 
     /* Init the channel */
     ESP_GOTO_ON_ERROR(touch_priv_config_channel(sens_handle->ch[chan_id], chan_cfg),
                       err1, TAG, "Failed to configure the touch channel %d", chan_id);
     touch_channel_pin_init(chan_id);
+
+    touch_chan_benchmark_config_t bm_cfg = {.do_reset = true};
     TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
-#if SOC_TOUCH_SENSOR_VERSION == 2
-    touch_ll_reset_chan_benchmark(1 << chan_id);
-#endif
     sens_handle->chan_mask |= 1 << chan_id;
-    touch_ll_set_channel_mask(sens_handle->chan_mask);
+    /* Reset the benchmark to overwrite the legacy benchmark during the deep sleep */
+    touch_priv_config_benchmark(sens_handle->ch[chan_id], &bm_cfg);
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
 
     *ret_chan_handle = sens_handle->ch[chan_id];
 
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 err1:
     free(sens_handle->ch[chan_id]);
     sens_handle->ch[chan_id] = NULL;
 err2:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -177,27 +180,41 @@ esp_err_t touch_sensor_del_channel(touch_channel_handle_t chan_handle)
 
     esp_err_t ret = ESP_OK;
     touch_sensor_handle_t sens_handle = chan_handle->base;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
 
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
-#if SOC_TOUCH_SENSOR_VERSION == 2
-    if (sens_handle->guard_chan == chan_handle || (BIT(chan_handle->id) & sens_handle->shield_chan_mask)) {
+#if SOC_TOUCH_SUPPORT_WATERPROOF
+    if (sens_handle->shield_chan == chan_handle) {
         ESP_GOTO_ON_ERROR(touch_sensor_config_waterproof(sens_handle, NULL), err, TAG, "Failed to disable waterproof on this channel");
+    } else if (sens_handle->guard_chan == chan_handle) {
+        TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+        touch_ll_waterproof_set_guard_chan(TOUCH_LL_NULL_CHANNEL);
+        sens_handle->guard_chan = NULL;
+        TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
     }
-    if (sens_handle->sleep_chan == chan_handle) {
-        ESP_GOTO_ON_ERROR(touch_sensor_config_sleep_channel(sens_handle, NULL), err, TAG, "Failed to disable sleep function on this channel");
+#endif  // SOC_TOUCH_SUPPORT_WATERPROOF
+#if SOC_TOUCH_SUPPORT_SLEEP_WAKEUP
+    if (sens_handle->deep_slp_chan == chan_handle) {
+        ESP_GOTO_ON_ERROR(touch_sensor_config_sleep_wakeup(sens_handle, NULL), err, TAG, "Failed to disable sleep function on this channel");
+    }
+#endif
+#if SOC_TOUCH_SUPPORT_PROX_SENSING
+    if (chan_handle->prox_id > 0) {
+        TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+        chan_handle->prox_id = 0;
+        touch_ll_set_proximity_sensing_channel(chan_handle->prox_id - 1, TOUCH_LL_NULL_CHANNEL);
+        TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
     }
 #endif
     int id = chan_handle->id;
     TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
     sens_handle->chan_mask &= ~(1UL << id);
-    touch_ll_set_channel_mask(sens_handle->chan_mask);
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
 
     free(g_touch->ch[id]);
     g_touch->ch[id] = NULL;
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -208,13 +225,13 @@ esp_err_t touch_sensor_reconfig_controller(touch_sensor_handle_t sens_handle, co
     ESP_RETURN_ON_FALSE(sens_cfg->meas_interval_us >= 0, ESP_ERR_INVALID_ARG, TAG, "interval_us should be a positive value");
 
     esp_err_t ret = ESP_OK;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
 
     ESP_GOTO_ON_ERROR(touch_priv_config_controller(sens_handle, sens_cfg), err, TAG, "Configure touch controller failed");
 
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -230,13 +247,14 @@ esp_err_t touch_sensor_enable(touch_sensor_handle_t sens_handle)
 
     sens_handle->is_enabled = true;
     TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
-    touch_ll_intr_clear(TOUCH_LL_INTR_MASK_ALL);
-    touch_ll_intr_enable(TOUCH_LL_INTR_MASK_ALL);
+    touch_ll_enable_channel_mask(sens_handle->chan_mask);
+    touch_ll_interrupt_clear(TOUCH_LL_INTR_MASK_ALL);
+    touch_ll_interrupt_enable(TOUCH_LL_INTR_MASK_ALL);
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
 #if SOC_TOUCH_SUPPORT_PROX_SENSING
     /* Reset the cached data of proximity channel */
     FOR_EACH_TOUCH_CHANNEL(i) {
-        if (sens_handle->ch[i] && sens_handle->ch[i]->is_prox_chan) {
+        if (sens_handle->ch[i] && sens_handle->ch[i]->prox_id > 0) {
             sens_handle->ch[i]->prox_cnt = 0;
             memset(sens_handle->ch[i]->prox_val, 0, sizeof(sens_handle->ch[i]->prox_val[0]) * TOUCH_SAMPLE_CFG_NUM);
         }
@@ -253,16 +271,17 @@ esp_err_t touch_sensor_disable(touch_sensor_handle_t sens_handle)
     TOUCH_NULL_POINTER_CHECK(sens_handle);
 
     esp_err_t ret = ESP_OK;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
     ESP_GOTO_ON_FALSE(sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Touch sensor has not enabled");
 
     TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
-    touch_ll_intr_disable(TOUCH_LL_INTR_MASK_ALL);
+    touch_ll_interrupt_disable(TOUCH_LL_INTR_MASK_ALL);
+    touch_ll_enable_channel_mask(0);
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
     sens_handle->is_enabled = false;
 
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -273,13 +292,13 @@ esp_err_t touch_sensor_reconfig_channel(touch_channel_handle_t chan_handle, cons
 
     esp_err_t ret = ESP_OK;
     touch_sensor_handle_t sens_handle = chan_handle->base;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
 
     ESP_GOTO_ON_ERROR(touch_priv_config_channel(chan_handle, chan_cfg), err, TAG, "Configure touch channel failed");
 
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -294,13 +313,8 @@ esp_err_t touch_sensor_start_continuous_scanning(touch_sensor_handle_t sens_hand
 
     TOUCH_ENTER_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
     sens_handle->is_started = true;
-#if SOC_TOUCH_SENSOR_VERSION <= 2
-    touch_ll_set_fsm_mode(TOUCH_FSM_MODE_TIMER);
-    touch_ll_start_fsm();
-#else
     touch_ll_enable_fsm_timer(true);
-    touch_ll_start_fsm_repeated_timer(false);
-#endif
+    touch_ll_start_fsm_repeated_timer();
     TOUCH_EXIT_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
 
 err:
@@ -316,13 +330,8 @@ esp_err_t touch_sensor_stop_continuous_scanning(touch_sensor_handle_t sens_handl
     ESP_GOTO_ON_FALSE_ISR(sens_handle->is_started, ESP_ERR_INVALID_STATE, err, TAG, "Continuous scanning not started yet");
 
     TOUCH_ENTER_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
-#if SOC_TOUCH_SENSOR_VERSION <= 2
-    touch_ll_stop_fsm();
-    touch_ll_set_fsm_mode(TOUCH_FSM_MODE_SW);
-#else
-    touch_ll_stop_fsm_repeated_timer(false);
+    touch_ll_stop_fsm_repeated_timer();
     touch_ll_enable_fsm_timer(false);
-#endif
     sens_handle->is_started = false;
     TOUCH_EXIT_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
 
@@ -349,9 +358,8 @@ esp_err_t touch_sensor_trigger_oneshot_scanning(touch_sensor_handle_t sens_handl
             ticks = 1;
         }
     }
-    xSemaphoreTake(sens_handle->mutex, ticks);
+    xSemaphoreTakeRecursive(sens_handle->mutex, ticks);
     TickType_t end_tick = xTaskGetTickCount() + ticks;
-    // TODO: extract the following implementation into version specific source file when supporting other targets
     TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
     touch_ll_enable_fsm_timer(false);
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
@@ -379,7 +387,7 @@ esp_err_t touch_sensor_trigger_oneshot_scanning(touch_sensor_handle_t sens_handl
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
 
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
     sens_handle->is_started = false;
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
@@ -400,7 +408,7 @@ esp_err_t touch_sensor_register_callbacks(touch_sensor_handle_t sens_handle, con
 #endif
 
     esp_err_t ret = ESP_OK;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
 
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
 
@@ -408,7 +416,7 @@ esp_err_t touch_sensor_register_callbacks(touch_sensor_handle_t sens_handle, con
     sens_handle->user_ctx = user_ctx;
 
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -426,3 +434,21 @@ esp_err_t touch_channel_config_benchmark(touch_channel_handle_t chan_handle, con
     touch_priv_config_benchmark(chan_handle, benchmark_cfg);
     return ESP_OK;
 }
+
+/******************************************************************************/
+/*                            Scope: Private APIs                             */
+/******************************************************************************/
+esp_err_t touch_sensor_get_channel_info(touch_channel_handle_t chan_handle, touch_chan_info_t *chan_info)
+{
+    TOUCH_NULL_POINTER_CHECK(chan_handle);
+    TOUCH_NULL_POINTER_CHECK(chan_info);
+    xSemaphoreTakeRecursive(chan_handle->base->mutex, portMAX_DELAY);
+    chan_info->chan_id = chan_handle->id;
+    chan_info->chan_gpio = touch_sensor_channel_io_map[chan_handle->id];
+    chan_info->flags.can_wake_dp_slp = chan_handle == chan_handle->base->deep_slp_chan;
+    chan_info->flags.is_proxi = chan_handle->prox_id > 0;
+    chan_info->flags.is_guard = chan_handle == chan_handle->base->guard_chan;
+    chan_info->flags.is_shield = chan_handle == chan_handle->base->shield_chan;
+    xSemaphoreGiveRecursive(chan_handle->base->mutex);
+    return ESP_OK;
+}
diff --git a/components/esp_driver_touch_sens/common/touch_sens_private.h b/components/esp_driver_touch_sens/common/touch_sens_private.h
index 325acb775e5..895af66991b 100644
--- a/components/esp_driver_touch_sens/common/touch_sens_private.h
+++ b/components/esp_driver_touch_sens/common/touch_sens_private.h
@@ -14,7 +14,7 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "soc/soc_caps.h"
-#include "hal/touch_sensor_hal.h"
+#include "hal/touch_sens_hal.h"
 #include "driver/touch_sens_types.h"
 #include "esp_memory_utils.h"
 #include "esp_check.h"
@@ -32,13 +32,19 @@ extern "C" {
 
 /* IRAM safe caps */
 #if CONFIG_TOUCH_ISR_IRAM_SAFE || CONFIG_TOUCH_CTRL_FUNC_IN_IRAM
-#define TOUCH_INTR_ALLOC_FLAGS    (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED)
-#define TOUCH_MEM_ALLOC_CAPS      (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
+#define _TOUCH_INTR_ALLOC_FLAGS     (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_LOWMED)
+#define TOUCH_MEM_ALLOC_CAPS        (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
 #else
-#define TOUCH_INTR_ALLOC_FLAGS    (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED)
+#define _TOUCH_INTR_ALLOC_FLAGS    (ESP_INTR_FLAG_LOWMED)
 #define TOUCH_MEM_ALLOC_CAPS      MALLOC_CAP_DEFAULT
 #endif //CONFIG_TOUCH_ISR_IRAM_SAFE
 
+#if SOC_TOUCH_SENSOR_VERSION == 3
+#define TOUCH_INTR_ALLOC_FLAGS      (_TOUCH_INTR_ALLOC_FLAGS)
+#else
+#define TOUCH_INTR_ALLOC_FLAGS      (_TOUCH_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED)
+#endif
+
 /* DMA caps */
 #define TOUCH_DMA_ALLOC_CAPS      (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA)
 
@@ -85,6 +91,7 @@ struct touch_sensor_s {
     bool                    immersion_proof;            /*!< Flag to indicate whether to disable scanning when the guard ring is triggered */
     bool                    proximity_en;               /*!< Flag to indicate whether the proximity sensing feature is enabled */
     bool                    timeout_en;                 /*!< Flag to indicate whether the measurement timeout feature (hardware timeout) is enabled */
+    bool                    denoise_en;                 /*!< Flag to indicate whether the denoise channel feature is enabled */
 };
 
 /**
@@ -94,7 +101,7 @@ struct touch_sensor_s {
 struct touch_channel_s {
     touch_sensor_handle_t   base;                       /*!< The touch sensor controller handle */
     int                     id;                         /*!< Touch channel id, the range is target-specific */
-    bool                    is_prox_chan;               /*!< Flag to indicate whether this is a proximity channel */
+    int                     prox_id;                    /*!< The proximity channel id + 1. It is 0 if not a proximity channel */
     uint32_t                prox_cnt;                   /*!< Cache the proximity measurement count, only takes effect when the channel is a proximity channel.
                                                          *   When this count reaches `touch_proximity_config_t::scan_times`,
                                                          *   this field will be cleared and call the `on_proximity_meas_done` callback.
diff --git a/components/esp_driver_touch_sens/hw_ver2/include/driver/touch_version_types.h b/components/esp_driver_touch_sens/hw_ver2/include/driver/touch_version_types.h
index 3eb0d2167e9..fddd88857e9 100644
--- a/components/esp_driver_touch_sens/hw_ver2/include/driver/touch_version_types.h
+++ b/components/esp_driver_touch_sens/hw_ver2/include/driver/touch_version_types.h
@@ -9,4 +9,375 @@
  *        Version 2 includes ESP32-S2 and ESP32-S3
  */
 
-#error "'esp_driver_touch_sens' does not support for ESP32-S2 and ESP32-S3 yet"
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "driver/touch_sens_types.h"
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define TOUCH_MIN_CHAN_ID           1           /*!< The minimum available channel id of the touch pad */
+#define TOUCH_MAX_CHAN_ID           14          /*!< The maximum available channel id of the touch pad */
+
+#define TOUCH_SHIELD_CHAN_ID        14          /*!< The touch channel that can be used as the shield channel */
+
+/**
+ * @brief Helper macro to the default configurations of the touch sensor controller
+ *
+ * @param[in] sample_cfg_number     The number of the sample configurations, which can only be 1 here because there is only one sample configuration
+ * @param[in] sample_cfg_ptr        The pointer to the sample configurations
+ */
+#define TOUCH_SENSOR_DEFAULT_BASIC_CONFIG(sample_cfg_number, sample_cfg_ptr) { \
+    .power_on_wait_us = 256, \
+    .meas_interval_us = 32.0, \
+    .max_meas_time_us = 0, \
+    .sample_cfg_num = sample_cfg_number,  \
+    .sample_cfg = sample_cfg_ptr,  \
+}
+
+/**
+ * @brief Helper macro to the default sample configurations
+ * @note  This default configuration uses `sample frequency = clock frequency / 1`
+ *
+ * @param[in] chg_times     The charge times of the touch channel
+ * @param[in] volt_low      The low voltage limit of the touch channel
+ * @param[in] volt_high     The high voltage limit of the touch channel
+ */
+#define TOUCH_SENSOR_V2_DEFAULT_SAMPLE_CONFIG(chg_times, volt_low, volt_high) {  \
+    .charge_times = chg_times,  \
+    .charge_volt_lim_h = volt_high,  \
+    .charge_volt_lim_l = volt_low,  \
+    .idle_conn = TOUCH_IDLE_CONN_GND,  \
+    .bias_type = TOUCH_BIAS_TYPE_SELF,  \
+}
+
+/**
+ * @brief Helper macro to the default filter configurations
+ *
+ */
+#define TOUCH_SENSOR_DEFAULT_FILTER_CONFIG() { \
+    .benchmark = { \
+        .filter_mode = TOUCH_BM_IIR_FILTER_4, \
+        .jitter_step = 4, \
+        .denoise_lvl = 1, \
+    }, \
+    .data = { \
+        .smooth_filter = TOUCH_SMOOTH_IIR_FILTER_2, \
+        .active_hysteresis = 2, \
+        .debounce_cnt = 2, \
+    }, \
+}
+
+/**
+ * @brief The data type of the touch channel
+ *
+ */
+typedef enum {
+    TOUCH_CHAN_DATA_TYPE_RAW,                   /*!< The raw data of the touch channel */
+    TOUCH_CHAN_DATA_TYPE_SMOOTH,                /*!< The smooth data of the touch channel */
+    TOUCH_CHAN_DATA_TYPE_BENCHMARK,             /*!< The benchmark of the touch channel */
+    TOUCH_CHAN_DATA_TYPE_PROXIMITY,             /*!< The proximity data of the proximity channel */
+} touch_chan_data_type_t;
+
+/**
+ * @brief Sample configurations of the touch sensor
+ *
+ */
+typedef struct {
+    uint32_t                        charge_times;       /*!< The charge and discharge times of this sample configuration, the read data are positive correlation to the charge_times */
+    touch_volt_lim_h_t              charge_volt_lim_h;  /*!< The upper voltage limit while charging a touch pad. i.e., the touch controller won't charge the touch pad higher than this high voltage limitation. */
+    touch_volt_lim_l_t              charge_volt_lim_l;  /*!< The lower voltage limit while discharging a touch pad. i.e., the touch controller won't discharge the touch pad lower than this low voltage limitation. */
+    touch_idle_conn_t               idle_conn;          /*!< The connection of the idle touch channels.
+                                                         *   The idle touch channel is a channel which is enabled and power-on but not under measuring.
+                                                         */
+    touch_bias_type_t               bias_type;          /*!< The type of the touch sensor bias. Which affects the charge/discharge stability and power consumption */
+} touch_sensor_sample_config_t;
+
+/**
+ * @brief Configurations of the touch sensor controller
+ *
+ */
+typedef struct {
+    uint32_t                        power_on_wait_us;   /*!< The waiting time between the channels power on and able to measure, to ensure the data stability */
+    float                           meas_interval_us;   /*!< Measurement interval of each channels */
+    uint32_t                        max_meas_time_us;   /*!< The maximum time of measuring one channel, if the time exceeds this value, the timeout interrupt will be triggered.
+                                                         *   Set to '0' to ignore the measurement time limitation, otherwise please set a proper time considering the configurations
+                                                         *   of this sample configurations below.
+                                                         */
+    /* Touch sensor sample configuration */
+    uint32_t                        sample_cfg_num;     /*!< The sample configuration number that used for sampling, CANNOT exceed TOUCH_SAMPLE_CFG_NUM */
+    touch_sensor_sample_config_t    *sample_cfg;        /*!< The array of this sample configuration configurations, the length should be specified in `touch_sensor_config_t::sample_cfg_num` */
+} touch_sensor_config_t;
+
+/**
+ * @brief Configurations of the touch sensor channel
+ *
+ */
+typedef struct {
+    uint32_t                        active_thresh[TOUCH_SAMPLE_CFG_NUM];      /*!< The active threshold of each sample configuration,
+                                                                               *   while the touch channel smooth value minus benchmark value exceed this threshold,
+                                                                               *   will be regarded as activated
+                                                                               */
+    touch_charge_speed_t            charge_speed;       /*!< The speed of charging and discharging the touch pad, the higher the speed, the faster charging and discharging */
+    touch_init_charge_volt_t        init_charge_volt;   /*!< The initial voltage before charging/discharging a touch pad */
+} touch_channel_config_t;
+
+/**
+ * @brief Configurations of the touch sensor filter
+ *
+ */
+typedef struct {
+    /**
+     * @brief Benchmark configuration
+     */
+    struct {
+        touch_benchmark_filter_mode_t   filter_mode;        /*!< Benchmark filter mode. IIR filter and Jitter filter can be selected,
+                                                             *   TOUCH_BM_IIR_FILTER_16 is recommended
+                                                             */
+        uint32_t                        jitter_step;        /*!< Jitter filter step size, only takes effect when the `filter_mode` is TOUCH_BM_JITTER_FILTER. Range: [0 ~ 15] */
+        int                             denoise_lvl;        /*!< The denoise level, which determines the noise bouncing range that won't trigger benchmark update.
+                                                             *   Range: [0 ~ 4]. The greater the denoise_lvl is, more noise resistance will be. Specially, `0` stands for no denoise
+                                                             *   Typically, recommend to set this field to 1.
+                                                             */
+    } benchmark;                                            /*!< Benchmark filter */
+    /**
+     * @brief Data configuration
+     */
+    struct {
+        touch_smooth_filter_mode_t      smooth_filter;      /*!< Smooth data IIR filter mode */
+        uint32_t                        active_hysteresis;  /*!< The hysteresis threshold to judge whether the touch channel is active
+                                                             *   If the channel data exceed the 'touch_channel_config_t::active_thresh + active_hysteresis'
+                                                             *   The channel will be activated. If the channel data is below to
+                                                             *   'touch_channel_config_t::active_thresh - active_hysteresis' the channel will be inactivated.
+                                                             */
+        uint32_t                        debounce_cnt;       /*!< The debounce count of the touch channel.
+                                                             *   Only when the channel data exceed the `touch_channel_config_t::active_thresh + active_hysteresis` for `debounce_cnt` times
+                                                             *   The channel will be activated. And only if the channel data is below to the `touch_channel_config_t::active_thresh - active_hysteresis`
+                                                             *   for `debounce_cnt` times, the channel will be inactivated.
+                                                             *   (The unit of `debounce_cnt` is the tick of the slow clock source)
+                                                             */
+    } data;                                                 /*!< Channel data filter */
+} touch_sensor_filter_config_t;
+
+/**
+ * @brief Touch sensor configuration during the deep sleep
+ * @note  Currently it is the same as the normal controller configuration.
+ *        The deep sleep configuration only takes effect when the chip entered sleep,
+ *        so that to update a more power efficient configuration.
+ *
+ */
+typedef touch_sensor_config_t touch_sensor_config_dslp_t;
+
+/**
+ * @brief Configuration of the touch sensor sleep function
+ *
+ */
+typedef struct {
+    touch_sleep_wakeup_level_t      slp_wakeup_lvl;     /*!< The sleep level that can be woke up by touch sensor. */
+    touch_channel_handle_t          deep_slp_chan;      /*!< The touch channel handle that supposed to work in the deep sleep. It can wake up the chip
+                                                         *   from deep sleep when this channel is activated.
+                                                         *   Only effective when the `touch_sleep_config_t::slp_wakeup_lvl` is `TOUCH_DEEP_SLEEP_WAKEUP`
+                                                         */
+    uint32_t                        deep_slp_thresh[TOUCH_SAMPLE_CFG_NUM];    /*!< The active threshold of the deep sleep channel during deep sleep,
+                                                         *   while the sleep channel exceed this threshold, it will be regarded as activated
+                                                         *   Only effective when the `touch_sleep_config_t::slp_wakeup_lvl` is `TOUCH_DEEP_SLEEP_WAKEUP`
+                                                         */
+    touch_sensor_config_dslp_t      *deep_slp_sens_cfg; /*!< Specify the touch sensor configuration during the deep sleep.
+                                                         *   Note that these configurations will no take effect immediately,
+                                                         *   they will be set automatically while the chip prepare to enter sleep.
+                                                         *   Set NULL to not change the configurations before entering sleep.
+                                                         *   The sleep configuration mainly aims at lower down the charging and measuring times,
+                                                         *   so that to save power consumption during the sleep.
+                                                         *   Only effective when the `touch_sleep_config_t::slp_wakeup_lvl` is `TOUCH_DEEP_SLEEP_WAKEUP`
+                                                         */
+} touch_sleep_config_t;
+
+/**
+ * @brief Configuration of the touch sensor waterproof function
+ *
+ */
+typedef struct {
+    touch_channel_handle_t          guard_chan;         /*!< The guard channel of that used for immersion detect. Set NULL if you don't need the guard channel.
+                                                         *   Typically, the guard channel is a ring that surrounds the touch panels,
+                                                         *   it is used to detect the large area that covered by water.
+                                                         *   While large area of water covers the touch panel, the guard channel will be activated.
+                                                         */
+    touch_channel_handle_t          shield_chan;        /*!< The shield channel that used for water droplets shield, can't be NULL.
+                                                         *   The shield channel can only be the No.14 channel on touch version 2.
+                                                         *   Typically, the shield channel uses grid layout which covers the touch area,
+                                                         *   it is used to shield the influence of water droplets covering both the touch panel and the shield channel.
+                                                         *   The shield channel will be paralleled to the current measuring channel (except the guard channel) to reduce the influence of water droplets.
+                                                         */
+    uint32_t                        shield_drv;         /*!< The shield channel driver, which controls the drive capability of shield channel, range: 0 ~ 7
+                                                         *   The larger the parasitic capacitance on the shielding channel, the higher the drive capability needs to be set.
+                                                         */
+    struct {
+        uint32_t                    immersion_proof: 1; /*!< Enable to protect the touch sensor pad when immersion detected.
+                                                         *   It will temporary disable the touch scanning if the guard channel triggered, and enable again if guard channel released.
+                                                         *   So that to avoid the fake touch when the touch panel is immersed in water.
+                                                         */
+    } flags;                                            /*!< Flags of the water proof function */
+} touch_waterproof_config_t;
+
+/**
+ * @brief Configuration of the touch sensor proximity function
+ *
+ */
+typedef struct {
+    touch_channel_handle_t          proximity_chan[TOUCH_PROXIMITY_CHAN_NUM]; /*!< The touch channel handles that will be configured as proximity sensing channels */
+    uint32_t                        scan_times;                               /*!< The total scan times of EACH sample configuration, all sample configurations share a same `scan_times`.
+                                                                               *   The measurement result of each scanning will be accumulated together to get the final result.
+                                                                               */
+} touch_proximity_config_t;
+
+/**
+ * @brief Configuration of denoise channel
+ *
+ */
+typedef struct {
+    touch_charge_speed_t            charge_speed;       /*!< The speed of charging and discharging the denoise touch channel, the higher the speed, the faster charging and discharging */
+    touch_init_charge_volt_t        init_charge_volt;   /*!< The initial voltage before starting charging/discharging the denoise channel */
+    touch_denoise_chan_cap_t        ref_cap;            /*!< The reference capacitance of the denoise channel. */
+    touch_denoise_chan_resolution_t resolution;         /*!< The noise suppression resolution of the denoise channel.
+                                                         *   The higher the resolution, the better the suppression effect,
+                                                         *   but at the same time, the attenuation of other touch channel sampling values also increases.
+                                                         */
+} touch_denoise_chan_config_t;
+
+/**
+ * @brief Base event structure used in touch event queue
+ */
+typedef struct {
+    touch_channel_handle_t          chan;           /*!< the current triggered touch channel handle */
+    int                             chan_id;        /*!< the current triggered touch channel number */
+    uint32_t                        status_mask;    /*!< the current channel triggered status.
+                                                     *   For the bits in the status mask,
+                                                     *   if the bit is set, the corresponding channel is active
+                                                     *   if the bit is cleared, the corresponding channel is inactive
+                                                     */
+} touch_base_event_data_t;
+
+/**
+ * @brief Measure done event data
+ * @note  Currently same as base event data
+ *
+ */
+typedef touch_base_event_data_t touch_meas_done_event_data_t;
+
+/**
+ * @brief Scan done event data
+ * @note  Currently same as base event data
+ *
+ */
+typedef touch_base_event_data_t touch_scan_done_event_data_t;
+
+/**
+ * @brief Active event data
+ * @note  Currently same as base event data
+ *
+ */
+typedef touch_base_event_data_t touch_active_event_data_t;
+
+/**
+ * @brief Inactive event data
+ * @note  Currently same as base event data
+ *
+ */
+typedef touch_base_event_data_t touch_inactive_event_data_t;
+
+/**
+ * @brief Proximity sensing measure done event data
+ * @note  Currently same as base event data
+ *
+ */
+typedef touch_base_event_data_t touch_prox_done_event_data_t;
+
+/**
+ * @brief Timeout event data
+ * @note  Currently same as base event data
+ *
+ */
+typedef touch_base_event_data_t touch_timeout_event_data_t;
+
+/**
+ * @brief Touch sensor callbacks
+ * @note  Set NULL for the used callbacks.
+ *
+ */
+typedef struct {
+    /**
+     * @brief Touch sensor on active event callback.
+     *        Callback when any touch channel is activated.
+     * @param[in] sens_handle    Touch sensor controller handle, created from `touch_sensor_new_controller()`
+     * @param[in] event     Touch sensor active event data
+     * @param[in] user_ctx  User registered context, passed from `touch_sensor_register_callbacks()`
+     *
+     * @return Whether a high priority task has been waken up by this callback function
+     */
+    bool (*on_active)(touch_sensor_handle_t sens_handle, const touch_active_event_data_t *event, void *user_ctx);
+    /**
+     * @brief Touch sensor on inactive event callback.
+     *        Callback when any touch channel is inactivated.
+     * @param[in] sens_handle    Touch sensor controller handle, created from `touch_sensor_new_controller()`
+     * @param[in] event     Touch sensor inactive event data
+     * @param[in] user_ctx  User registered context, passed from `touch_sensor_register_callbacks()`
+     *
+     * @return Whether a high priority task has been waken up by this callback function
+     */
+    bool (*on_inactive)(touch_sensor_handle_t sens_handle, const touch_inactive_event_data_t *event, void *user_ctx);
+    /**
+     * @brief Touch sensor on measure done event callback.
+     *        Callback when the measurement of all the sample configurations on the current touch channel is done.
+     * @param[in] sens_handle    Touch sensor controller handle, created from `touch_sensor_new_controller()`
+     * @param[in] event     Touch sensor measure done event data
+     * @param[in] user_ctx  User registered context, passed from `touch_sensor_register_callbacks()`
+     *
+     * @return Whether a high priority task has been waken up by this callback function
+     */
+    bool (*on_measure_done)(touch_sensor_handle_t sens_handle, const touch_meas_done_event_data_t *event, void *user_ctx);
+    /**
+     * @brief Touch sensor on scan done event callback.
+     *        Callback when finished scanning all the registered touch channels.
+     * @param[in] sens_handle    Touch sensor controller handle, created from `touch_sensor_new_controller()`
+     * @param[in] event     Touch sensor scan done event data
+     * @param[in] user_ctx  User registered context, passed from `touch_sensor_register_callbacks()`
+     *
+     * @return Whether a high priority task has been waken up by this callback function
+     */
+    bool (*on_scan_done)(touch_sensor_handle_t sens_handle, const touch_scan_done_event_data_t *event, void *user_ctx);
+    /**
+     * @brief Touch sensor on measurement timeout event callback.
+     *        Callback when measure the current touch channel timeout.
+     * @param[in] sens_handle    Touch sensor controller handle, created from `touch_sensor_new_controller()`
+     * @param[in] event     Touch sensor timeout event data
+     * @param[in] user_ctx  User registered context, passed from `touch_sensor_register_callbacks()`
+     *
+     * @return Whether a high priority task has been waken up by this callback function
+     */
+    bool (*on_timeout)(touch_sensor_handle_t sens_handle, const touch_timeout_event_data_t *event, void *user_ctx);
+    /**
+     * @brief Touch sensor on proximity sensing measurement done event callback.
+     *        Callback when proximity sensing measurement of the current channel is done.
+     * @param[in] sens_handle    Touch sensor controller handle, created from `touch_sensor_new_controller()`
+     * @param[in] event     Touch sensor proximity sensing measure done event data
+     * @param[in] user_ctx  User registered context, passed from `touch_sensor_register_callbacks()`
+     *
+     * @return Whether a high priority task has been waken up by this callback function
+     */
+    bool (*on_proximity_meas_done)(touch_sensor_handle_t sens_handle, const touch_prox_done_event_data_t *event, void *user_ctx);
+} touch_event_callbacks_t;
+
+/**
+ * @brief Touch sensor benchmark configurations, to set or reset the benchmark of the channel
+ *
+ */
+typedef struct {
+    bool                            do_reset;                /*!< Whether to reset the benchmark to the channel's latest smooth data */
+} touch_chan_benchmark_config_t;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_driver_touch_sens/hw_ver2/touch_version_specific.c b/components/esp_driver_touch_sens/hw_ver2/touch_version_specific.c
new file mode 100644
index 00000000000..e7dcc63fe02
--- /dev/null
+++ b/components/esp_driver_touch_sens/hw_ver2/touch_version_specific.c
@@ -0,0 +1,471 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief This file is only applicable to the touch hardware version2
+ *        Version 2 includes ESP32-S2 and ESP32-S3
+ */
+
+#include <inttypes.h>
+#include <string.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "soc/soc_caps.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/touch_sensor_periph.h"
+#include "soc/rtc.h"
+#include "hal/hal_utils.h"
+#include "driver/touch_sens.h"
+#include "esp_private/rtc_ctrl.h"
+#include "esp_private/periph_ctrl.h"
+#include "esp_clk_tree.h"
+#include "esp_sleep.h"
+#include "../../common/touch_sens_private.h"
+#if CONFIG_TOUCH_ENABLE_DEBUG_LOG
+// The local log level must be defined before including esp_log.h
+// Set the maximum log level for this source file
+#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
+#endif
+#include "esp_log.h"
+#include "esp_check.h"
+
+#define TOUCH_DENOISE_CHAN_ID       0           /*!< The touch channel that can be used as the denoise channel */
+
+static const char *TAG = "touch";
+
+portMUX_TYPE g_touch_spinlock = portMUX_INITIALIZER_UNLOCKED;
+
+/******************************************************************************
+ *                       Scope: touch driver private                          *
+ ******************************************************************************/
+
+void touch_priv_enable_module(bool enable)
+{
+    TOUCH_ENTER_CRITICAL(TOUCH_RTC_LOCK);
+    touch_ll_enable_clock_gate(enable);
+    // Reset the benchmark after finished the scanning
+    touch_ll_reset_chan_benchmark(TOUCH_LL_FULL_CHANNEL_MASK);
+    TOUCH_EXIT_CRITICAL(TOUCH_RTC_LOCK);
+}
+
+void IRAM_ATTR touch_priv_default_intr_handler(void *arg)
+{
+    /* If the touch controller object has not been allocated, return directly */
+    if (!g_touch) {
+        return;
+    }
+    bool need_yield = false;
+    uint32_t status = touch_ll_get_intr_status_mask();
+    g_touch->is_meas_timeout = false;
+    touch_ll_interrupt_clear(status);
+    touch_base_event_data_t data;
+    touch_ll_get_active_channel_mask(&data.status_mask);
+    data.chan = g_touch->ch[touch_ll_get_current_meas_channel()];
+    /* If the channel is not registered, return directly */
+    if (!data.chan) {
+        return;
+    }
+    data.chan_id = data.chan->id;
+
+    if (status & TOUCH_LL_INTR_MASK_DONE) {
+#if !SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED
+        /* For the target like ESP32-S2 that don't support proximity done interrupt,
+           Simulate the interrupt by software by judge the scan times. */
+        if (data.chan->prox_id > 0 &&
+                touch_ll_proximity_get_total_scan_times() == touch_ll_proximity_get_curr_scan_cnt(data.chan_id)) {
+            /* Set the proximity scan done flag to simulate a proximity done interrupt */
+            status |= TOUCH_LL_INTR_MASK_PROX_DONE;
+        }
+#endif
+        if (g_touch->cbs.on_measure_done) {
+            need_yield |= g_touch->cbs.on_measure_done(g_touch, &data, g_touch->user_ctx);
+        }
+    }
+    if (status & TOUCH_LL_INTR_MASK_SCAN_DONE) {
+#if CONFIG_IDF_TARGET_ESP32S2
+        /* Workaround for the fake scan done interrupt.
+           (Only happens when both channel 13 and 14 are enabled)
+           The scan done interrupt will be triggered twice for channel 13 and 14,
+           but we only hope it be triggered after channel 14 measurement done. */
+        bool fake_scan_done = data.chan_id == 13 && (g_touch->chan_mask >> 13 == 0x03);
+        if (g_touch->cbs.on_scan_done && !fake_scan_done)
+#else
+        if (g_touch->cbs.on_scan_done)
+#endif
+        {
+            need_yield |= g_touch->cbs.on_scan_done(g_touch, &data, g_touch->user_ctx);
+        }
+    }
+    if (status & TOUCH_LL_INTR_MASK_PROX_DONE) {
+        /* Accumulated proximity sensing data is stored in the benchmark data register.
+           Read it out to latch the last proximity sensing data. */
+        touch_ll_read_chan_data(data.chan_id, TOUCH_LL_READ_BENCHMARK, &data.chan->prox_val[0]);
+        // TODO: support to judge by software if the proximity channel triggered
+        if (g_touch->cbs.on_proximity_meas_done) {
+            need_yield |= g_touch->cbs.on_proximity_meas_done(g_touch, &data, g_touch->user_ctx);
+        }
+    }
+    if (status & TOUCH_LL_INTR_MASK_ACTIVE) {
+        /* When the guard ring activated, disable the scanning of other channels to avoid fake touch */
+        TOUCH_ENTER_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
+        if (g_touch->waterproof_en && data.chan == g_touch->guard_chan) {
+            touch_ll_enable_scan_mask(~BIT(data.chan->id), false);
+        }
+        TOUCH_EXIT_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
+        if (g_touch->cbs.on_active) {
+            need_yield |= g_touch->cbs.on_active(g_touch, &data, g_touch->user_ctx);
+        }
+    }
+    if (status & TOUCH_LL_INTR_MASK_INACTIVE) {
+        /* When the guard ring inactivated, enable the scanning of other channels again */
+        TOUCH_ENTER_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
+        if (g_touch->waterproof_en && data.chan == g_touch->guard_chan) {
+            touch_ll_enable_scan_mask(g_touch->chan_mask & (~BIT(g_touch->shield_chan->id)), true);
+        }
+        TOUCH_EXIT_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
+        if (g_touch->cbs.on_inactive) {
+            need_yield |= g_touch->cbs.on_inactive(g_touch, &data, g_touch->user_ctx);
+        }
+    }
+    if (status & TOUCH_LL_INTR_MASK_TIMEOUT) {
+        g_touch->is_meas_timeout = true;
+        touch_ll_force_done_curr_measurement();
+        if ((g_touch->cbs.on_timeout)) {
+            need_yield |= g_touch->cbs.on_timeout(g_touch, &data, g_touch->user_ctx);
+        }
+    }
+
+    if (need_yield) {
+        portYIELD_FROM_ISR();
+    }
+}
+
+static esp_err_t s_touch_convert_to_hal_config(touch_sensor_handle_t sens_handle, const touch_sensor_config_t *sens_cfg, touch_hal_config_t *hal_cfg)
+{
+    TOUCH_NULL_POINTER_CHECK(sens_cfg);
+    TOUCH_NULL_POINTER_CHECK(hal_cfg);
+
+    ESP_RETURN_ON_FALSE(sens_cfg->sample_cfg_num && sens_cfg->sample_cfg, ESP_ERR_INVALID_ARG, TAG,
+                        "at least one sample configuration required");
+    ESP_RETURN_ON_FALSE(sens_cfg->sample_cfg_num <= TOUCH_SAMPLE_CFG_NUM, ESP_ERR_INVALID_ARG, TAG,
+                        "at most %d sample configurations supported", (int)(TOUCH_SAMPLE_CFG_NUM));
+
+    /* Get the source clock frequency for the first time */
+    if (!sens_handle->src_freq_hz) {
+        /* Touch sensor actually uses dynamic fast clock LP_DYN_FAST_CLK, but it will only switch to the slow clock during sleep,
+        * This driver only designed for wakeup case (sleep case should use ULP driver), so we only need to consider RTC_FAST here */
+        esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_RTC_FAST, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sens_handle->src_freq_hz);
+        ESP_LOGD(TAG, "touch rtc clock source: RTC_FAST, frequency: %"PRIu32" Hz", sens_handle->src_freq_hz);
+    }
+
+    uint32_t src_freq_mhz = sens_handle->src_freq_hz / 1000000;
+    hal_cfg->power_on_wait_ticks = (uint32_t)sens_cfg->power_on_wait_us * src_freq_mhz;
+    hal_cfg->power_on_wait_ticks = hal_cfg->power_on_wait_ticks > TOUCH_LL_PAD_MEASURE_WAIT_MAX ?
+                                   TOUCH_LL_PAD_MEASURE_WAIT_MAX : hal_cfg->power_on_wait_ticks;
+    hal_cfg->meas_interval_ticks = (uint32_t)(sens_cfg->meas_interval_us * src_freq_mhz);
+    hal_cfg->timeout_ticks = (uint32_t)sens_cfg->max_meas_time_us * src_freq_mhz;
+    ESP_RETURN_ON_FALSE(hal_cfg->timeout_ticks <= TOUCH_LL_TIMEOUT_MAX, ESP_ERR_INVALID_ARG, TAG,
+                        "max_meas_time_ms should within %"PRIu32, TOUCH_LL_TIMEOUT_MAX / src_freq_mhz);
+    hal_cfg->sample_cfg_num = sens_cfg->sample_cfg_num;  // Only one sample cfg
+    hal_cfg->sample_cfg = (touch_hal_sample_config_t *)sens_cfg->sample_cfg;
+    return ESP_OK;
+}
+
+esp_err_t touch_priv_config_controller(touch_sensor_handle_t sens_handle, const touch_sensor_config_t *sens_cfg)
+{
+#if CONFIG_TOUCH_ENABLE_DEBUG_LOG
+    esp_log_level_set(TAG, ESP_LOG_DEBUG);
+#endif
+    /* Check and convert the configuration to hal configurations */
+    touch_hal_config_t hal_cfg = {};
+    ESP_RETURN_ON_ERROR(s_touch_convert_to_hal_config(sens_handle, sens_cfg, &hal_cfg),
+                        TAG, "parse the configuration failed due to the invalid configuration");
+    sens_handle->sample_cfg_num = 1;  // Only have one set of sampling configuration
+
+    /* Configure the hardware */
+    TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+    touch_hal_config_controller(&hal_cfg);
+    TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+
+    return ESP_OK;
+}
+
+esp_err_t touch_priv_config_channel(touch_channel_handle_t chan_handle, const touch_channel_config_t *chan_cfg)
+{
+    // Check the validation of the channel active threshold
+    ESP_RETURN_ON_FALSE(chan_cfg->active_thresh[0] <= TOUCH_LL_ACTIVE_THRESH_MAX, ESP_ERR_INVALID_ARG,
+                        TAG, "the active threshold out of range 0~%d", TOUCH_LL_ACTIVE_THRESH_MAX);
+    TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+    touch_ll_set_chan_active_threshold(chan_handle->id, chan_cfg->active_thresh[0]);
+    touch_ll_set_charge_speed(chan_handle->id, chan_cfg->charge_speed);
+    touch_ll_set_init_charge_voltage(chan_handle->id, chan_cfg->init_charge_volt);
+    TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+    return ESP_OK;
+}
+
+esp_err_t touch_priv_deinit_controller(touch_sensor_handle_t sens_handle)
+{
+    /* Disable the additional functions */
+    if (sens_handle->proximity_en) {
+        touch_sensor_config_proximity_sensing(sens_handle, NULL);
+    }
+    if (sens_handle->sleep_en) {
+        touch_sensor_config_sleep_wakeup(sens_handle, NULL);
+    }
+    if (sens_handle->waterproof_en) {
+        touch_sensor_config_waterproof(sens_handle, NULL);
+    }
+    if (sens_handle->denoise_en) {
+        touch_sensor_config_denoise_channel(sens_handle, NULL);
+    }
+    return ESP_OK;
+}
+
+esp_err_t touch_priv_channel_read_data(touch_channel_handle_t chan_handle, touch_chan_data_type_t type, uint32_t *data)
+{
+    ESP_RETURN_ON_FALSE_ISR(type >= TOUCH_CHAN_DATA_TYPE_RAW && type <= TOUCH_CHAN_DATA_TYPE_PROXIMITY,
+                            ESP_ERR_INVALID_ARG, TAG, "The channel data type is invalid");
+    ESP_RETURN_ON_FALSE_ISR(type != TOUCH_CHAN_DATA_TYPE_PROXIMITY || chan_handle->prox_id > 0, ESP_ERR_INVALID_ARG, TAG, "This is not a proximity sensing channel");
+    TOUCH_ENTER_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
+    switch (type) {
+    default: // fall through
+    case TOUCH_CHAN_DATA_TYPE_RAW:
+        touch_ll_read_chan_data(chan_handle->id, TOUCH_LL_READ_RAW, data);
+        break;
+    case TOUCH_CHAN_DATA_TYPE_SMOOTH:
+        touch_ll_read_chan_data(chan_handle->id, TOUCH_LL_READ_SMOOTH, data);
+        break;
+    case TOUCH_CHAN_DATA_TYPE_BENCHMARK:
+        touch_ll_read_chan_data(chan_handle->id, TOUCH_LL_READ_BENCHMARK, data);
+        break;
+    case TOUCH_CHAN_DATA_TYPE_PROXIMITY:
+        /* Get the proximity value from the stored data.
+        * The proximity value are updated in the isr when proximity scanning is done */
+        *data = chan_handle->prox_val[0];
+        break;
+    }
+    TOUCH_EXIT_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
+    return ESP_OK;
+}
+
+void touch_priv_config_benchmark(touch_channel_handle_t chan_handle, const touch_chan_benchmark_config_t *benchmark_cfg)
+{
+    if (benchmark_cfg->do_reset) {
+        touch_ll_reset_chan_benchmark(BIT(chan_handle->id));
+    }
+}
+
+/******************************************************************************
+ *                              Scope: public APIs                            *
+ ******************************************************************************/
+
+esp_err_t touch_sensor_config_filter(touch_sensor_handle_t sens_handle, const touch_sensor_filter_config_t *filter_cfg)
+{
+    TOUCH_NULL_POINTER_CHECK(sens_handle);
+    if (filter_cfg) {
+        ESP_RETURN_ON_FALSE(filter_cfg->benchmark.denoise_lvl >= 0 && filter_cfg->benchmark.denoise_lvl <= 4,
+                            ESP_ERR_INVALID_ARG, TAG, "denoise_lvl is out of range");
+    }
+
+    esp_err_t ret = ESP_OK;
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
+    TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+
+    if (filter_cfg) {
+        touch_ll_filter_enable(true);
+        /* Configure the benchmark filter and update strategy */
+        touch_ll_filter_set_filter_mode(filter_cfg->benchmark.filter_mode);
+        if (filter_cfg->benchmark.filter_mode == TOUCH_BM_JITTER_FILTER) {
+            touch_ll_filter_set_jitter_step(filter_cfg->benchmark.jitter_step);
+        }
+        touch_ll_filter_set_denoise_level(filter_cfg->benchmark.denoise_lvl);
+        /* Configure the touch data filter */
+        touch_ll_filter_set_smooth_mode(filter_cfg->data.smooth_filter);
+        touch_ll_filter_set_active_hysteresis(filter_cfg->data.active_hysteresis);
+        touch_ll_filter_set_debounce(filter_cfg->data.debounce_cnt);
+    } else {
+        touch_ll_filter_enable(false);
+    }
+
+    TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
+    return ret;
+}
+
+esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, const touch_sleep_config_t *sleep_cfg)
+{
+    TOUCH_NULL_POINTER_CHECK(sens_handle);
+
+    esp_err_t ret = ESP_OK;
+    int dp_slp_chan_id = -1;
+    touch_hal_config_t hal_cfg = {};
+    touch_hal_config_t *hal_cfg_ptr = NULL;
+
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
+    ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
+
+    if (sleep_cfg) {
+        ESP_GOTO_ON_FALSE(sleep_cfg->slp_wakeup_lvl == TOUCH_LIGHT_SLEEP_WAKEUP || sleep_cfg->slp_wakeup_lvl == TOUCH_DEEP_SLEEP_WAKEUP,
+                          ESP_ERR_INVALID_ARG, err, TAG, "Invalid sleep level");
+        /* Enabled touch sensor as wake-up source */
+        esp_sleep_enable_touchpad_wakeup();
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+        // Keep ESP_PD_DOMAIN_RTC_PERIPH power domain on during the light/deep sleep, so that to keep the touch sensor working
+        esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
+#endif  // SOC_PM_SUPPORT_RC_FAST_PD
+
+        /* If set the deep sleep channel (i.e., enable deep sleep wake-up),
+           configure the deep sleep related settings. */
+        if (sleep_cfg->slp_wakeup_lvl == TOUCH_DEEP_SLEEP_WAKEUP) {
+            ESP_GOTO_ON_FALSE(sleep_cfg->deep_slp_chan, ESP_ERR_INVALID_ARG, err, TAG, "deep sleep waken channel can't be NULL");
+            dp_slp_chan_id = sleep_cfg->deep_slp_chan->id;
+
+            /* Check and convert the configuration to hal configurations */
+            if (sleep_cfg->deep_slp_sens_cfg) {
+                hal_cfg_ptr = &hal_cfg;
+                ESP_GOTO_ON_ERROR(s_touch_convert_to_hal_config(sens_handle, sleep_cfg->deep_slp_sens_cfg, hal_cfg_ptr),
+                                  err, TAG, "parse the configuration failed due to the invalid configuration");
+            }
+            sens_handle->sleep_en = true;
+            sens_handle->deep_slp_chan = sleep_cfg->deep_slp_chan;
+            TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+            touch_ll_sleep_set_threshold(sleep_cfg->deep_slp_thresh[0]);
+            TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+        }
+
+    } else {
+        /* Disable the touch sensor as wake-up source */
+        esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TOUCHPAD);
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+        esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_AUTO);
+#endif  // SOC_PM_SUPPORT_RC_FAST_PD
+        sens_handle->deep_slp_chan = NULL;
+        sens_handle->sleep_en = false;
+    }
+
+    /* Save or update the sleep config */
+    TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+    touch_hal_save_sleep_config(dp_slp_chan_id, hal_cfg_ptr);
+    TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+
+err:
+    xSemaphoreGiveRecursive(sens_handle->mutex);
+    return ret;
+}
+
+// Water proof can be enabled separately
+esp_err_t touch_sensor_config_waterproof(touch_sensor_handle_t sens_handle, const touch_waterproof_config_t *wp_cfg)
+{
+    TOUCH_NULL_POINTER_CHECK(sens_handle);
+
+    esp_err_t ret = ESP_OK;
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
+
+    ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
+
+    if (wp_cfg) {
+        ESP_GOTO_ON_FALSE(wp_cfg->shield_chan && wp_cfg->shield_chan->id == 14, ESP_ERR_INVALID_ARG, err, TAG, "Shield channel must be channel 14");
+        // Check the validation of the waterproof configuration
+        TOUCH_NULL_POINTER_CHECK(wp_cfg->shield_chan);
+        TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+        sens_handle->waterproof_en = true;
+        sens_handle->guard_chan = wp_cfg->guard_chan;
+        sens_handle->shield_chan = wp_cfg->shield_chan;
+        touch_ll_waterproof_set_guard_chan(wp_cfg->guard_chan ? wp_cfg->guard_chan->id : TOUCH_LL_NULL_CHANNEL);
+        // need to disable the scanning of the shield channel
+        touch_ll_enable_scan_mask(BIT(wp_cfg->shield_chan->id), false);
+        touch_ll_waterproof_set_shield_driver(wp_cfg->shield_drv);
+        touch_ll_waterproof_enable(true);
+        TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+    } else {
+        TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+        touch_ll_waterproof_enable(false);
+        touch_ll_waterproof_set_guard_chan(TOUCH_LL_NULL_CHANNEL);
+        touch_ll_enable_scan_mask(BIT(sens_handle->shield_chan->id), true);
+        touch_ll_waterproof_set_shield_driver(0);
+        sens_handle->guard_chan = NULL;
+        sens_handle->shield_chan = NULL;
+        sens_handle->waterproof_en = false;
+        TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+    }
+err:
+    xSemaphoreGiveRecursive(sens_handle->mutex);
+    return ret;
+}
+
+esp_err_t touch_sensor_config_proximity_sensing(touch_sensor_handle_t sens_handle, const touch_proximity_config_t *prox_cfg)
+{
+    TOUCH_NULL_POINTER_CHECK(sens_handle);
+
+    esp_err_t ret = ESP_OK;
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
+
+    ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
+
+    TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+
+    /* Reset proximity sensing part of all channels */
+    FOR_EACH_TOUCH_CHANNEL(i) {
+        if (sens_handle->ch[i]) {
+            sens_handle->ch[i]->prox_id = 0;
+            sens_handle->ch[i]->prox_cnt = 0;
+            memset(sens_handle->ch[i]->prox_val, 0, sizeof(sens_handle->ch[i]->prox_val[0]) * TOUCH_SAMPLE_CFG_NUM);
+        }
+    }
+
+    if (prox_cfg) {
+        sens_handle->proximity_en = true;
+        for (int i = 0; i < TOUCH_PROXIMITY_CHAN_NUM; i++) {
+            if (prox_cfg->proximity_chan[i]) {
+                prox_cfg->proximity_chan[i]->prox_id = i + 1;
+                touch_ll_set_proximity_sensing_channel(i, prox_cfg->proximity_chan[i]->id);
+            } else {
+                touch_ll_set_proximity_sensing_channel(i, TOUCH_LL_NULL_CHANNEL);
+            }
+        }
+        touch_ll_proximity_set_total_scan_times(prox_cfg->scan_times);
+    } else {
+        for (int i = 0; i < TOUCH_PROXIMITY_CHAN_NUM; i++) {
+            touch_ll_set_proximity_sensing_channel(i, TOUCH_LL_NULL_CHANNEL);
+        }
+        sens_handle->proximity_en = false;
+    }
+    TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+
+err:
+    xSemaphoreGiveRecursive(sens_handle->mutex);
+    return ret;
+}
+
+esp_err_t touch_sensor_config_denoise_channel(touch_sensor_handle_t sens_handle, const touch_denoise_chan_config_t *denoise_cfg)
+{
+    TOUCH_NULL_POINTER_CHECK(sens_handle);
+    esp_err_t ret = ESP_OK;
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
+
+    ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
+
+    if (denoise_cfg) {
+        TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+        sens_handle->denoise_en = true;
+        sens_handle->chan_mask |= BIT(TOUCH_DENOISE_CHAN_ID);
+        touch_ll_set_charge_speed(TOUCH_DENOISE_CHAN_ID, denoise_cfg->charge_speed);
+        touch_ll_set_init_charge_voltage(TOUCH_DENOISE_CHAN_ID, denoise_cfg->init_charge_volt);
+        touch_ll_denoise_set_reference_cap(denoise_cfg->ref_cap);
+        touch_ll_denoise_set_resolution(denoise_cfg->resolution);
+        touch_ll_denoise_enable(true);
+        TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+    } else {
+        TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
+        sens_handle->denoise_en = false;
+        sens_handle->chan_mask &= ~BIT(TOUCH_DENOISE_CHAN_ID);
+        touch_ll_denoise_enable(false);
+        TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
+    }
+err:
+    xSemaphoreGiveRecursive(sens_handle->mutex);
+    return ret;
+}
diff --git a/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h b/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h
index cf15c14be8a..00f185337e2 100644
--- a/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h
+++ b/components/esp_driver_touch_sens/hw_ver3/include/driver/touch_version_types.h
@@ -25,6 +25,9 @@ extern "C" {
 /**
  * @brief Helper macro to the default configurations of the touch sensor controller
  *
+ * @param[in] sample_cfg_number The number of sample configurations, which should be less than or equal to `SOC_TOUCH_SAMPLE_CFG_NUM`
+ *                          Given multiple sample configurations to enable the frequency hopping
+ * @param[in] sample_cfg_array  The pointer to the sample configurations array
  */
 #define TOUCH_SENSOR_DEFAULT_BASIC_CONFIG(sample_cfg_number, sample_cfg_array) { \
     .power_on_wait_us = 256, \
@@ -39,6 +42,9 @@ extern "C" {
  * @brief Helper macro to the default sample configurations
  * @note  This default configuration uses `sample frequency = clock frequency / 1`
  *
+ * @param[in] _div_num              The division of the final data, used to scaling the final data
+ * @param[in] coarse_freq_tune      The coarse frequency tuning value
+ * @param[in] fine_freq_tune        The fine frequency tuning value
  */
 #define TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(_div_num, coarse_freq_tune, fine_freq_tune) { \
     .div_num = _div_num, \
@@ -51,6 +57,10 @@ extern "C" {
     .bypass_shield_output = false, \
 }
 
+/**
+ * @brief Helper macro to the default filter configurations
+ *
+ */
 #define TOUCH_SENSOR_DEFAULT_FILTER_CONFIG() { \
     .benchmark = { \
         .filter_mode = TOUCH_BM_IIR_FILTER_4, \
@@ -60,6 +70,7 @@ extern "C" {
     .data = { \
         .smooth_filter = TOUCH_SMOOTH_IIR_FILTER_2, \
         .active_hysteresis = 2, \
+        .debounce_cnt = 2, \
     }, \
 }
 
@@ -73,74 +84,14 @@ typedef enum {
     TOUCH_CHAN_DATA_TYPE_PROXIMITY,             /*!< The proximity data of the proximity channel */
 } touch_chan_data_type_t;
 
-/**
- * @brief The chip sleep level that allows the touch sensor to wake-up
- *
- */
-typedef enum {
-    TOUCH_LIGHT_SLEEP_WAKEUP,                /*!< Only enable the touch sensor to wake up the chip from light sleep */
-    TOUCH_DEEP_SLEEP_WAKEUP,                 /*!< Enable the touch sensor to wake up the chip from deep sleep or light sleep */
-} touch_sleep_wakeup_level_t;
-
-/**
- * @brief Touch sensor shield channel drive capability level
- *
- */
-typedef enum {
-    TOUCH_SHIELD_CAP_40PF,                  /*!< The max equivalent capacitance in shield channel is 40pf */
-    TOUCH_SHIELD_CAP_80PF,                  /*!< The max equivalent capacitance in shield channel is 80pf */
-    TOUCH_SHIELD_CAP_120PF,                 /*!< The max equivalent capacitance in shield channel is 120pf */
-    TOUCH_SHIELD_CAP_160PF,                 /*!< The max equivalent capacitance in shield channel is 160pf */
-    TOUCH_SHIELD_CAP_200PF,                 /*!< The max equivalent capacitance in shield channel is 200pf */
-    TOUCH_SHIELD_CAP_240PF,                 /*!< The max equivalent capacitance in shield channel is 240pf */
-    TOUCH_SHIELD_CAP_280PF,                 /*!< The max equivalent capacitance in shield channel is 280pf */
-    TOUCH_SHIELD_CAP_320PF,                 /*!< The max equivalent capacitance in shield channel is 320pf */
-} touch_chan_shield_cap_t;
-
-/**
- * @brief Touch channel Infinite Impulse Response (IIR) filter or Jitter filter for benchmark
- * @note Recommended filter coefficient selection is `IIR_16`.
- */
-typedef enum {
-    TOUCH_BM_IIR_FILTER_4,                  /*!< IIR Filter for benchmark, 1/4 raw_value + 3/4 benchmark */
-    TOUCH_BM_IIR_FILTER_8,                  /*!< IIR Filter for benchmark, 1/8 raw_value + 7/8 benchmark */
-    TOUCH_BM_IIR_FILTER_16,                 /*!< IIR Filter for benchmark, 1/16 raw_value + 15/16 benchmark (typical) */
-    TOUCH_BM_IIR_FILTER_32,                 /*!< IIR Filter for benchmark, 1/32 raw_value + 31/32 benchmark */
-    TOUCH_BM_IIR_FILTER_64,                 /*!< IIR Filter for benchmark, 1/64 raw_value + 63/64 benchmark */
-    TOUCH_BM_IIR_FILTER_128,                /*!< IIR Filter for benchmark, 1/128 raw_value + 127/128 benchmark */
-    TOUCH_BM_JITTER_FILTER,                 /*!< Jitter Filter for benchmark, raw value +/- jitter_step */
-} touch_benchmark_filter_mode_t;
-
-/**
- * @brief Touch channel Infinite Impulse Response (IIR) filter for smooth data
- *
- */
-typedef enum {
-    TOUCH_SMOOTH_NO_FILTER,                 /*!< No filter adopted for smooth data, smooth data equals raw data */
-    TOUCH_SMOOTH_IIR_FILTER_2,              /*!< IIR filter adopted for smooth data, smooth data equals 1/2 raw data + 1/2 last smooth data (typical) */
-    TOUCH_SMOOTH_IIR_FILTER_4,              /*!< IIR filter adopted for smooth data, smooth data equals 1/4 raw data + 3/4 last smooth data */
-    TOUCH_SMOOTH_IIR_FILTER_8,              /*!< IIR filter adopted for smooth data, smooth data equals 1/8 raw data + 7/8 last smooth data */
-} touch_smooth_filter_mode_t;
-
-/**
- * @brief Interrupt events
- *
- */
-typedef enum {
-    TOUCH_INTR_EVENT_ACTIVE,                /*!< Touch channel active event */
-    TOUCH_INTR_EVENT_INACTIVE,              /*!< Touch channel inactive event */
-    TOUCH_INTR_EVENT_MEASURE_DONE,          /*!< Touch channel measure done event */
-    TOUCH_INTR_EVENT_SCAN_DONE,             /*!< All touch channels scan done event */
-    TOUCH_INTR_EVENT_TIMEOUT,               /*!< Touch channel measurement timeout event */
-    TOUCH_INTR_EVENT_PROXIMITY_DONE,        /*!< Proximity channel measurement done event */
-} touch_intr_event_t;
-
 /**
  * @brief Sample configurations of the touch sensor
  *
  */
 typedef struct {
-    uint32_t                        div_num;            /*!< Division of the touch output pulse, `touch_out_pulse / div_num = charge_times` */
+    uint32_t                        div_num;            /*!< Division of the touch output pulse.
+                                                         *   It is proportional to the gain of the read data, the greater the div_num, the higher gain of the read data.
+                                                         *   If the read data is exceeded the maximum range, please reduce the div_num. */
     uint32_t                        charge_times;       /*!< The charge and discharge times of this sample configuration, the read data are positive correlation to the charge_times */
     uint8_t                         rc_filter_res;      /*!< The resistance of the RC filter of this sample configuration, range [0, 3], while 0 = 0K, 1 = 1.5K, 2 = 3K, 3 = 4.5K */
     uint8_t                         rc_filter_cap;      /*!< The capacitance of the RC filter of this sample configuration, range [0, 127], while 0 = 0pF, 1 = 20fF, ..., 127 = 2.54pF */
@@ -162,7 +113,7 @@ typedef struct {
                                                          *   of this sample configurations below.
                                                          */
     touch_out_mode_t                output_mode;        /*!< Touch channel counting mode of the binarized touch output */
-    uint32_t                        sample_cfg_num;     /*!< The sample configuration number that used for sampling */
+    uint32_t                        sample_cfg_num;     /*!< The sample configuration number that used for sampling, CANNOT exceed TOUCH_SAMPLE_CFG_NUM */
     touch_sensor_sample_config_t    *sample_cfg;        /*!< The array of this sample configuration configurations, the length should be specified in `touch_sensor_config_t::sample_cfg_num` */
 } touch_sensor_config_t;
 
@@ -224,7 +175,7 @@ typedef struct {
 typedef touch_sensor_config_t touch_sensor_config_dslp_t;
 
 /**
- * @brief Configure the touch sensor sleep function
+ * @brief Configuration of the touch sensor sleep function
  *
  */
 typedef struct {
@@ -248,7 +199,7 @@ typedef struct {
 } touch_sleep_config_t;
 
 /**
- * @brief Configure the touch sensor waterproof function
+ * @brief Configuration of the touch sensor waterproof function
  *
  */
 typedef struct {
@@ -274,7 +225,7 @@ typedef struct {
 } touch_waterproof_config_t;
 
 /**
- * @brief Configure the touch sensor proximity function
+ * @brief Configuration of the touch sensor proximity function
  *
  */
 typedef struct {
@@ -292,13 +243,13 @@ typedef struct {
  * @brief Base event structure used in touch event queue
  */
 typedef struct {
-    touch_channel_handle_t  chan;           /*!< the current triggered touch channel handle */
-    int                     chan_id;        /*!< the current triggered touch channel number */
-    uint32_t                status_mask;    /*!< the current channel triggered status.
-                                             *   For the bits in the status mask,
-                                             *   if the bit is set, the corresponding channel is active
-                                             *   if the bit is cleared, the corresponding channel is inactive
-                                             */
+    touch_channel_handle_t          chan;           /*!< the current triggered touch channel handle */
+    int                             chan_id;        /*!< the current triggered touch channel number */
+    uint32_t                        status_mask;    /*!< the current channel triggered status.
+                                                     *   For the bits in the status mask,
+                                                     *   if the bit is set, the corresponding channel is active
+                                                     *   if the bit is cleared, the corresponding channel is inactive
+                                                     */
 } touch_base_event_data_t;
 
 /**
diff --git a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c
index ebf9acecdd6..bf2ca48f38d 100644
--- a/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c
+++ b/components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c
@@ -29,6 +29,7 @@
 // Set the maximum log level for this source file
 #define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
 #endif
+#include "esp_log.h"
 #include "esp_check.h"
 
 static const char *TAG = "touch";
@@ -44,10 +45,6 @@ void touch_priv_enable_module(bool enable)
     TOUCH_ENTER_CRITICAL(TOUCH_RTC_LOCK);
     touch_ll_enable_module_clock(enable);
     touch_ll_enable_out_gate(enable);
-#if SOC_TOUCH_SENSOR_VERSION >= 2
-    // Reset the benchmark after finished the scanning
-    touch_ll_reset_chan_benchmark(TOUCH_LL_FULL_CHANNEL_MASK);
-#endif
     TOUCH_EXIT_CRITICAL(TOUCH_RTC_LOCK);
 }
 
@@ -60,7 +57,7 @@ void IRAM_ATTR touch_priv_default_intr_handler(void *arg)
     bool need_yield = false;
     uint32_t status = touch_ll_get_intr_status_mask();
     g_touch->is_meas_timeout = false;
-    touch_ll_intr_clear(status);
+    touch_ll_interrupt_clear(status);
     touch_base_event_data_t data;
     touch_ll_get_active_channel_mask(&data.status_mask);
     data.chan = g_touch->ch[touch_ll_get_current_meas_channel()];
@@ -253,7 +250,7 @@ esp_err_t touch_priv_channel_read_data(touch_channel_handle_t chan_handle, touch
             TOUCH_EXIT_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
         }
     } else {
-        if (!chan_handle->is_prox_chan) {
+        if (!chan_handle->prox_id) {
             ESP_EARLY_LOGW(TAG, "This is not a proximity sensing channel");
         }
         TOUCH_ENTER_CRITICAL_SAFE(TOUCH_PERIPH_LOCK);
@@ -287,7 +284,7 @@ esp_err_t touch_sensor_config_filter(touch_sensor_handle_t sens_handle, const to
     }
 
     esp_err_t ret = ESP_OK;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
     TOUCH_ENTER_CRITICAL(TOUCH_PERIPH_LOCK);
 
     if (filter_cfg) {
@@ -307,7 +304,7 @@ esp_err_t touch_sensor_config_filter(touch_sensor_handle_t sens_handle, const to
     }
 
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -323,7 +320,7 @@ esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, co
     };
     touch_hal_config_t *hal_cfg_ptr = NULL;
 
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
 
     if (sleep_cfg) {
@@ -331,8 +328,9 @@ esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, co
                           ESP_ERR_INVALID_ARG, err, TAG, "Invalid sleep level");
         /* Enabled touch sensor as wake-up source */
         ESP_GOTO_ON_ERROR(esp_sleep_enable_touchpad_wakeup(), err, TAG, "Failed to enable touch sensor wakeup");
-#if SOC_PM_SUPPORT_RC_FAST_PD
-        ESP_GOTO_ON_ERROR(esp_sleep_pd_config(ESP_PD_DOMAIN_RC_FAST, ESP_PD_OPTION_ON), err, TAG, "Failed to keep touch sensor module clock during the sleep");
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+        // Keep ESP_PD_DOMAIN_RTC_PERIPH power domain on during the light/deep sleep, so that to keep the touch sensor working
+        ESP_GOTO_ON_ERROR(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON), err, TAG, "Failed to keep touch sensor module clock during the sleep");
 #endif
 
         /* If set the deep sleep channel (i.e., enable deep sleep wake-up),
@@ -360,10 +358,10 @@ esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, co
     } else {
         /* Disable the touch sensor as wake-up source */
         esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TOUCHPAD);
-#if SOC_PM_SUPPORT_RC_FAST_PD
-        esp_sleep_pd_config(ESP_PD_DOMAIN_RC_FAST, ESP_PD_OPTION_AUTO);
+#if SOC_PM_SUPPORT_RTC_PERIPH_PD
+        esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_AUTO);
 #endif
-
+        sens_handle->deep_slp_chan = NULL;
         sens_handle->sleep_en = false;
     }
 
@@ -373,7 +371,7 @@ esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, co
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
 
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -383,7 +381,7 @@ esp_err_t touch_sensor_config_waterproof(touch_sensor_handle_t sens_handle, cons
     TOUCH_NULL_POINTER_CHECK(sens_handle);
 
     esp_err_t ret = ESP_OK;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
 
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
 
@@ -418,7 +416,7 @@ esp_err_t touch_sensor_config_waterproof(touch_sensor_handle_t sens_handle, cons
         TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
     }
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
 
@@ -427,7 +425,7 @@ esp_err_t touch_sensor_config_proximity_sensing(touch_sensor_handle_t sens_handl
     TOUCH_NULL_POINTER_CHECK(sens_handle);
 
     esp_err_t ret = ESP_OK;
-    xSemaphoreTake(sens_handle->mutex, portMAX_DELAY);
+    xSemaphoreTakeRecursive(sens_handle->mutex, portMAX_DELAY);
 
     ESP_GOTO_ON_FALSE(!sens_handle->is_enabled, ESP_ERR_INVALID_STATE, err, TAG, "Please disable the touch sensor first");
 
@@ -435,8 +433,8 @@ esp_err_t touch_sensor_config_proximity_sensing(touch_sensor_handle_t sens_handl
 
     /* Reset proximity sensing part of all channels */
     FOR_EACH_TOUCH_CHANNEL(i) {
-        if (sens_handle->ch[i] && sens_handle->ch[i]->is_prox_chan) {
-            sens_handle->ch[i]->is_prox_chan = false;
+        if (sens_handle->ch[i] && sens_handle->ch[i]->prox_id > 0) {
+            sens_handle->ch[i]->prox_id = 0;
             sens_handle->ch[i]->prox_cnt = 0;
             for (int i = 0; i < TOUCH_SAMPLE_CFG_NUM; i++) {
                 sens_handle->ch[i]->prox_val[i] = 0;
@@ -449,7 +447,7 @@ esp_err_t touch_sensor_config_proximity_sensing(touch_sensor_handle_t sens_handl
         uint8_t sample_cfg_num = sens_handle->sample_cfg_num;
         for (int i = 0; i < TOUCH_PROXIMITY_CHAN_NUM; i++) {
             if (prox_cfg->proximity_chan[i]) {
-                prox_cfg->proximity_chan[i]->is_prox_chan = true;
+                prox_cfg->proximity_chan[i]->prox_id = i + 1;
                 touch_ll_set_proximity_sensing_channel(i, prox_cfg->proximity_chan[i]->id);
             } else {
                 touch_ll_set_proximity_sensing_channel(i, TOUCH_LL_NULL_CHANNEL);
@@ -468,6 +466,6 @@ esp_err_t touch_sensor_config_proximity_sensing(touch_sensor_handle_t sens_handl
     TOUCH_EXIT_CRITICAL(TOUCH_PERIPH_LOCK);
 
 err:
-    xSemaphoreGive(sens_handle->mutex);
+    xSemaphoreGiveRecursive(sens_handle->mutex);
     return ret;
 }
diff --git a/components/esp_driver_touch_sens/include/driver/touch_sens.h b/components/esp_driver_touch_sens/include/driver/touch_sens.h
index cba510baef9..c1e22d57137 100644
--- a/components/esp_driver_touch_sens/include/driver/touch_sens.h
+++ b/components/esp_driver_touch_sens/include/driver/touch_sens.h
@@ -61,6 +61,8 @@ esp_err_t touch_sensor_new_channel(touch_sensor_handle_t sens_handle, int chan_i
 /**
  * @brief Delete the touch channel
  * @note  This function can be called when the touch sensor controller is NOT enabled (i.e. INIT state).
+ * @note  If the channel has been enabled other sub-features like proximity sensing, sleep wakeup, waterproof, denoise.
+ *        The attached sub-features will be disabled while deleting the channel.
  *
  * @param[in]  chan_handle      Touch channel handle
  * @return
@@ -289,6 +291,24 @@ esp_err_t touch_sensor_config_proximity_sensing(touch_sensor_handle_t sens_handl
 esp_err_t touch_sensor_config_sleep_wakeup(touch_sensor_handle_t sens_handle, const touch_sleep_config_t *sleep_cfg);
 #endif
 
+#if SOC_TOUCH_SUPPORT_DENOISE_CHAN
+/**
+ * @brief Configure the touch denoise channel
+ * @note  The denoise channel is used to suppress the internal background noise.
+ *        Once the denoise channel enabled, the measured data of the other touch channels
+ *        will minus the data of the denoise channel automatically.
+ *        So the channel data will be attenuated after enabling the denoise channel.
+ *
+ * @param[in]  sens_handle      Touch sensor controller handle
+ * @param[in]  denoise_cfg      Denoise channel configurations, set NULL to disable the touch channel
+ * @return
+ *      - ESP_OK:                   Configure the denoise channel success
+ *      - ESP_ERR_INVALID_ARG:      The sensor handle is NULL or invalid denoise configuration
+ *      - ESP_ERR_INVALID_STATE:    The touch sensor is enabled
+ */
+esp_err_t touch_sensor_config_denoise_channel(touch_sensor_handle_t sens_handle, const touch_denoise_chan_config_t *denoise_cfg);
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_driver_touch_sens/include/driver/touch_sens_types.h b/components/esp_driver_touch_sens/include/driver/touch_sens_types.h
index 3b802cc6ccd..50ee1ae0c33 100644
--- a/components/esp_driver_touch_sens/include/driver/touch_sens_types.h
+++ b/components/esp_driver_touch_sens/include/driver/touch_sens_types.h
@@ -10,7 +10,7 @@
 #include <stdbool.h>
 #include <stddef.h>
 #include "soc/soc_caps.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sens_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -22,6 +22,15 @@ extern "C" {
 #define TOUCH_PROXIMITY_CHAN_NUM    SOC_TOUCH_PROXIMITY_CHANNEL_NUM     /*!< The supported proximity channel number in proximity sensing mode */
 #endif
 
+/**
+ * @brief The chip sleep level that allows the touch sensor to wake-up
+ *
+ */
+typedef enum {
+    TOUCH_LIGHT_SLEEP_WAKEUP,                /*!< Only enable the touch sensor to wake up the chip from light sleep */
+    TOUCH_DEEP_SLEEP_WAKEUP,                 /*!< Enable the touch sensor to wake up the chip from deep sleep or light sleep */
+} touch_sleep_wakeup_level_t;
+
 typedef struct touch_sensor_s       *touch_sensor_handle_t;     /*!< The handle of touch sensor controller */
 typedef struct touch_channel_s      *touch_channel_handle_t;    /*!< The handle of touch channel */
 
diff --git a/components/esp_driver_touch_sens/include/esp_private/touch_sens_helper.h b/components/esp_driver_touch_sens/include/esp_private/touch_sens_helper.h
new file mode 100644
index 00000000000..637a90336a1
--- /dev/null
+++ b/components/esp_driver_touch_sens/include/esp_private/touch_sens_helper.h
@@ -0,0 +1,45 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/touch_sens_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Touch channel information
+ *
+ */
+typedef struct {
+    int chan_id;                    /*!< Touch channel number */
+    int chan_gpio;                  /*!< Corresponding GPIO of this channel */
+    struct {
+        uint32_t can_wake_dp_slp: 1;/*!< Whether this channel can wakeup from deep sleep */
+        uint32_t is_proxi: 1;       /*!< Whether this channel is used for proximity sensing */
+        uint32_t is_guard: 1;       /*!< Whether this channel is used for waterproof guard channel */
+        uint32_t is_shield: 1;      /*!< Whether this channel is used for waterproof shield channel */
+    } flags;                        /*!< Channel sub-feature flags */
+} touch_chan_info_t;
+
+/**
+ * @brief Get the touch channel information by the channel handle
+ *
+ * @param[in]  chan_handle  Touch channel handle
+ * @param[out] chan_info    Touch channel information
+ * @return
+ *      - ESP_OK:               Success to get the channel information
+ *      - ESP_ERR_INVALID_ARG:  NULL pointer
+ */
+esp_err_t touch_sensor_get_channel_info(touch_channel_handle_t chan_handle, touch_chan_info_t *chan_info);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_driver_touch_sens/test_apps/.build-test-rules.yml b/components/esp_driver_touch_sens/test_apps/.build-test-rules.yml
index 16e6ca03696..142c609d4bc 100644
--- a/components/esp_driver_touch_sens/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_touch_sens/test_apps/.build-test-rules.yml
@@ -1,6 +1,8 @@
 components/esp_driver_touch_sens/test_apps/touch_sens:
   disable:
-    - if: SOC_TOUCH_SENSOR_VERSION != 3
-      temporary: currently driver ng only support version 3
+    - if: SOC_TOUCH_SENSOR_SUPPORTED != 1
+    - if: SOC_TOUCH_SENSOR_VERSION == 1
+      temporary: true
+      reason: currently driver ng does not support version 1
   depends_components:
     - esp_driver_touch_sens
diff --git a/components/esp_driver_touch_sens/test_apps/touch_sens/README.md b/components/esp_driver_touch_sens/test_apps/touch_sens/README.md
index f8ea707124d..9b5055b84a8 100644
--- a/components/esp_driver_touch_sens/test_apps/touch_sens/README.md
+++ b/components/esp_driver_touch_sens/test_apps/touch_sens/README.md
@@ -1,3 +1,3 @@
-| Supported Targets | ESP32-P4 |
-| ----------------- | -------- |
+| Supported Targets | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- |
 
diff --git a/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c b/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c
index 226b8549fa2..64481e69729 100644
--- a/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c
+++ b/components/esp_driver_touch_sens/test_apps/touch_sens/main/test_touch_sens_common.c
@@ -10,29 +10,36 @@
 #include "unity.h"
 #include "driver/touch_sens.h"
 #include "hal/touch_sensor_ll.h"
+#include "esp_private/touch_sens_helper.h"
 #include "esp_log.h"
 #include "esp_attr.h"
 
 static touch_sensor_sample_config_t s_sample_cfg[TOUCH_SAMPLE_CFG_NUM] = {
+#if SOC_TOUCH_SENSOR_VERSION == 2
+    TOUCH_SENSOR_V2_DEFAULT_SAMPLE_CONFIG(500, TOUCH_VOLT_LIM_L_0V5, TOUCH_VOLT_LIM_H_2V2),
+#elif SOC_TOUCH_SENSOR_VERSION == 3
     TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(1, 1, 1),
-#if TOUCH_SAMPLE_CFG_NUM > 1
     TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(2, 1, 1),
-#endif
-#if TOUCH_SAMPLE_CFG_NUM > 2
     TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(4, 1, 1),
+#else
+#error "Target not support"
 #endif
 };
 
 static touch_channel_config_t s_chan_cfg = {
+#if SOC_TOUCH_SENSOR_VERSION == 2
+    .active_thresh = {
+        2000,
+    },
+    .charge_speed = TOUCH_CHARGE_SPEED_7,
+    .init_charge_volt = TOUCH_INIT_CHARGE_VOLT_LOW,
+#elif SOC_TOUCH_SENSOR_VERSION == 3
     .active_thresh = {
         5000,
-#if TOUCH_SAMPLE_CFG_NUM > 1
         2500,
-#endif
-#if TOUCH_SAMPLE_CFG_NUM > 2
         1000,
-#endif
     },
+#endif
 };
 
 TEST_CASE("touch_sens_install_uninstall_test", "[touch]")
@@ -48,20 +55,20 @@ TEST_CASE("touch_sens_install_uninstall_test", "[touch]")
     touch_sensor_filter_config_t filter_cfg = TOUCH_SENSOR_DEFAULT_FILTER_CONFIG();
     TEST_ESP_OK(touch_sensor_config_filter(touch, &filter_cfg));
 
-    for (int i = 0; i < TOUCH_TOTAL_CHAN_NUM; i++) {
+    for (int i = TOUCH_MIN_CHAN_ID; i <= TOUCH_MAX_CHAN_ID; i++) {
         TEST_ESP_OK(touch_sensor_new_channel(touch, i, &s_chan_cfg, &touch_chan[i]));
     }
     touch_channel_handle_t fault_chan = NULL;
     TEST_ASSERT(touch_sensor_new_channel(touch, TOUCH_TOTAL_CHAN_NUM, &s_chan_cfg, &fault_chan) == ESP_ERR_INVALID_ARG);
-    TEST_ASSERT(touch_sensor_new_channel(touch, 0, &s_chan_cfg, &fault_chan) == ESP_ERR_INVALID_STATE);
+    TEST_ASSERT(touch_sensor_new_channel(touch, TOUCH_MIN_CHAN_ID, &s_chan_cfg, &fault_chan) == ESP_ERR_INVALID_STATE);
 
     TEST_ESP_OK(touch_sensor_enable(touch));
-    TEST_ASSERT(touch_sensor_del_channel(touch_chan[0]) == ESP_ERR_INVALID_STATE);
+    TEST_ASSERT(touch_sensor_del_channel(touch_chan[TOUCH_MIN_CHAN_ID]) == ESP_ERR_INVALID_STATE);
     TEST_ESP_OK(touch_sensor_disable(touch));
 
     TEST_ASSERT(touch_sensor_del_controller(touch) == ESP_ERR_INVALID_STATE);
 
-    for (int i = 0; i < TOUCH_TOTAL_CHAN_NUM; i++) {
+    for (int i = TOUCH_MIN_CHAN_ID; i <= TOUCH_MAX_CHAN_ID; i++) {
         TEST_ESP_OK(touch_sensor_del_channel(touch_chan[i]));
     }
     TEST_ESP_OK(touch_sensor_del_controller(touch));
@@ -119,7 +126,13 @@ static bool TEST_TCH_IRAM_ATTR s_test_touch_on_inactive_callback(touch_sensor_ha
 
 static void s_test_touch_simulate_touch(touch_sensor_handle_t touch, touch_channel_handle_t touch_chan, bool active)
 {
+#if SOC_TOUCH_SENSOR_VERSION == 2
+    touch_chan_info_t chan_info = {};
+    touch_sensor_get_channel_info(touch_chan, &chan_info);
+    touch_ll_set_charge_speed(chan_info.chan_id, active ? TOUCH_CHARGE_SPEED_4 : TOUCH_CHARGE_SPEED_7);
+#elif SOC_TOUCH_SENSOR_VERSION == 3
     touch_ll_set_internal_capacitor(active ? 0x7f : 0);
+#endif
 }
 
 static void s_test_touch_log_data(touch_channel_handle_t touch_chan, uint32_t sample_cfg_num, const char *tag)
@@ -146,15 +159,21 @@ TEST_CASE("touch_sens_active_inactive_test", "[touch]")
     /* Configuring the filter */
     touch_sensor_filter_config_t filter_cfg = TOUCH_SENSOR_DEFAULT_FILTER_CONFIG();
     TEST_ESP_OK(touch_sensor_config_filter(touch, &filter_cfg));
-    TEST_ESP_OK(touch_sensor_new_channel(touch, 0, &s_chan_cfg, &touch_chan));
+    TEST_ESP_OK(touch_sensor_new_channel(touch, TOUCH_MIN_CHAN_ID, &s_chan_cfg, &touch_chan));
+#if SOC_TOUCH_SENSOR_VERSION == 3
     /* Connect the touch channels to the internal capacitor */
     touch_ll_enable_internal_capacitor(true);
+#endif  // SOC_TOUCH_SENSOR_VERSION == 3
 
     s_test_touch_do_initial_scanning(touch, 3);
 
     /* Read benchmark */
     uint32_t benchmark[TOUCH_SAMPLE_CFG_NUM] = {0};
     TEST_ESP_OK(touch_channel_read_data(touch_chan, TOUCH_CHAN_DATA_TYPE_BENCHMARK, benchmark));
+    /* Test whether success to finish the initial scanning */
+    for (int i = 0; i < TOUCH_SAMPLE_CFG_NUM; i++) {
+        TEST_ASSERT_GREATER_THAN(0, benchmark[i]);
+    }
     /* Re-configure the threshold according to the benchmark */
     touch_channel_config_t chan_cfg = s_test_get_chan_cfg_by_benchmark(benchmark, TOUCH_SAMPLE_CFG_NUM, TEST_ACTIVE_THRESH_RATIO);
     TEST_ESP_OK(touch_sensor_reconfig_channel(touch_chan, &chan_cfg));
diff --git a/components/esp_driver_touch_sens/test_apps/touch_sens/pytest_touch_sens.py b/components/esp_driver_touch_sens/test_apps/touch_sens/pytest_touch_sens.py
index 871cdb6baf0..c1205a91175 100644
--- a/components/esp_driver_touch_sens/test_apps/touch_sens/pytest_touch_sens.py
+++ b/components/esp_driver_touch_sens/test_apps/touch_sens/pytest_touch_sens.py
@@ -4,8 +4,9 @@
 from pytest_embedded import Dut
 
 
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
 @pytest.mark.esp32p4
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 runners do not support touch pins')
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
diff --git a/components/esp_driver_tsens/include/driver/temperature_sensor.h b/components/esp_driver_tsens/include/driver/temperature_sensor.h
index 3c2c18dc1c5..fc968dfb0fa 100644
--- a/components/esp_driver_tsens/include/driver/temperature_sensor.h
+++ b/components/esp_driver_tsens/include/driver/temperature_sensor.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,6 +30,12 @@ typedef struct {
     int range_min;   /**< the minimum value of the temperature you want to test */
     int range_max;   /**< the maximum value of the temperature you want to test */
     temperature_sensor_clk_src_t clk_src;  /**< the clock source of the temperature sensor. */
+    struct {
+        uint32_t allow_pd;  /**< If set, the driver will backup/restore the temperature sensor registers before/after entering/exist sleep mode.
+                                 By this approach, the system can power off temperature sensor's power domain.
+                                 This can save power, but at the expense of more RAM being consumed */
+    } flags;                /**< Temperature sensor config flags */
+
 } temperature_sensor_config_t;
 
 /**
diff --git a/components/esp_driver_tsens/src/temperature_sensor.c b/components/esp_driver_tsens/src/temperature_sensor.c
index 2bf39ca9bf2..39e44afb9b5 100644
--- a/components/esp_driver_tsens/src/temperature_sensor.c
+++ b/components/esp_driver_tsens/src/temperature_sensor.c
@@ -29,6 +29,9 @@
 #include "soc/temperature_sensor_periph.h"
 #include "esp_memory_utils.h"
 #include "esp_private/sar_periph_ctrl.h"
+#if TEMPERATURE_SENSOR_USE_RETENTION_LINK
+#include "esp_private/sleep_retention.h"
+#endif
 
 static const char *TAG = "temperature_sensor";
 
@@ -93,6 +96,26 @@ static void IRAM_ATTR temperature_sensor_isr(void *arg)
 }
 #endif // SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
 
+#if TEMPERATURE_SENSOR_USE_RETENTION_LINK
+static esp_err_t s_temperature_sensor_sleep_retention_init(void *arg)
+{
+    esp_err_t ret = sleep_retention_entries_create(temperature_sensor_regs_retention.link_list, temperature_sensor_regs_retention.link_num, REGDMA_LINK_PRI_TEMPERATURE_SENSOR, temperature_sensor_regs_retention.module_id);
+    ESP_RETURN_ON_ERROR(ret, TAG, "failed to allocate mem for sleep retention");
+    return ret;
+}
+
+void temperature_sensor_create_retention_module(temperature_sensor_handle_t tsens)
+{
+    sleep_retention_module_t module_id = temperature_sensor_regs_retention.module_id;
+    if ((sleep_retention_get_inited_modules() & BIT(module_id)) && !(sleep_retention_get_created_modules() & BIT(module_id))) {
+        if (sleep_retention_module_allocate(module_id) != ESP_OK) {
+            // even though the sleep retention module_id create failed, temperature sensor driver should still work, so just warning here
+            ESP_LOGW(TAG, "create retention link failed, power domain won't be turned off during sleep");
+        }
+    }
+}
+#endif // TEMPERATURE_SENSOR_USE_RETENTION_LINK
+
 esp_err_t temperature_sensor_install(const temperature_sensor_config_t *tsens_config, temperature_sensor_handle_t *ret_tsens)
 {
 #if CONFIG_TEMP_SENSOR_ENABLE_DEBUG_LOG
@@ -110,6 +133,24 @@ esp_err_t temperature_sensor_install(const temperature_sensor_config_t *tsens_co
         tsens->clk_src = tsens_config->clk_src;
     }
 
+#if !SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+    ESP_RETURN_ON_FALSE(tsens_config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep");
+#endif // SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+
+#if TEMPERATURE_SENSOR_USE_RETENTION_LINK
+    sleep_retention_module_init_param_t init_param = {
+        .cbs = { .create = { .handle = s_temperature_sensor_sleep_retention_init, .arg = (void *)tsens } }
+    };
+    ret = sleep_retention_module_init(temperature_sensor_regs_retention.module_id, &init_param);
+    if (ret != ESP_OK) {
+        ESP_LOGW(TAG, "init sleep retention failed, power domain may be turned off during sleep");
+    }
+
+    if (tsens_config->flags.allow_pd != 0) {
+        temperature_sensor_create_retention_module(tsens);
+    }
+#endif // TEMPERATURE_SENSOR_USE_RETENTION_LINK
+
     temperature_sensor_power_acquire();
     temperature_sensor_ll_clk_sel(tsens->clk_src);
 
@@ -147,6 +188,17 @@ esp_err_t temperature_sensor_uninstall(temperature_sensor_handle_t tsens)
         ESP_RETURN_ON_ERROR(esp_intr_free(tsens->temp_sensor_isr_handle), TAG, "uninstall interrupt service failed");
     }
 #endif // SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
+
+#if TEMPERATURE_SENSOR_USE_RETENTION_LINK
+    sleep_retention_module_t module_id = temperature_sensor_regs_retention.module_id;
+    if (sleep_retention_get_created_modules() & BIT(module_id)) {
+        sleep_retention_module_free(temperature_sensor_regs_retention.module_id);
+    }
+    if (sleep_retention_get_inited_modules() & BIT(module_id)) {
+        sleep_retention_module_deinit(temperature_sensor_regs_retention.module_id);
+    }
+#endif // TEMPERATURE_SENSOR_USE_RETENTION_LINK
+
     temperature_sensor_power_release();
 
     free(tsens);
diff --git a/components/esp_driver_tsens/src/temperature_sensor_private.h b/components/esp_driver_tsens/src/temperature_sensor_private.h
index b511505ffba..28b84be5f8e 100644
--- a/components/esp_driver_tsens/src/temperature_sensor_private.h
+++ b/components/esp_driver_tsens/src/temperature_sensor_private.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,6 +30,9 @@ typedef enum {
 #define TEMPERATURE_SENSOR_MEM_ALLOC_CAPS      (MALLOC_CAP_DEFAULT)
 #endif
 
+// Use retention link only when the target supports sleep retention and PM is enabled
+#define TEMPERATURE_SENSOR_USE_RETENTION_LINK  (SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN)
+
 typedef struct temperature_sensor_obj_t temperature_sensor_obj_t;
 
 struct temperature_sensor_obj_t {
diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt b/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt
index 5d45e0615ad..57b6fd425c6 100644
--- a/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt
+++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/CMakeLists.txt
@@ -9,5 +9,5 @@ endif()
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
-                       PRIV_REQUIRES unity esp_wifi test_utils nvs_flash esp_driver_tsens esp_driver_gpio
+                       PRIV_REQUIRES unity esp_wifi test_utils nvs_flash esp_driver_tsens esp_driver_gpio esp_pm
                        WHOLE_ARCHIVE)
diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c
index 6bc7fe4e86e..15b38613c8b 100644
--- a/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c
+++ b/components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +13,11 @@
 #include "freertos/task.h"
 #include "soc/soc_caps.h"
 #include "unity_test_utils_cache.h"
+#include "esp_sleep.h"
+#include "esp_private/sleep_cpu.h"
+#include "esp_pm.h"
+#include "esp_private/esp_sleep_internal.h"
+#include "esp_private/esp_pmu.h"
 
 TEST_CASE("Temperature_sensor_driver_workflow_test", "[temperature_sensor]")
 {
@@ -146,3 +151,59 @@ TEST_CASE("Temperature sensor callback test", "[temperature_sensor]")
 }
 
 #endif // SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
+
+#if SOC_LIGHT_SLEEP_SUPPORTED && CONFIG_PM_ENABLE
+static void test_temperature_sensor_sleep_retention(bool allow_pd)
+{
+    printf("Initializing Temperature sensor\n");
+    float tsens_result0;
+    float tsens_result1;
+    temperature_sensor_config_t temp_sensor = {
+        .range_min = 10,
+        .range_max = 50,
+        .clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT,
+        .flags.allow_pd = allow_pd,
+    };
+    temperature_sensor_handle_t temp_handle = NULL;
+    TEST_ESP_OK(temperature_sensor_install(&temp_sensor, &temp_handle));
+    TEST_ESP_OK(temperature_sensor_enable(temp_handle));
+    printf("Temperature sensor started\n");
+    TEST_ESP_OK(temperature_sensor_get_celsius(temp_handle, &tsens_result0));
+    printf("Temperature out celsius %f°C\n", tsens_result0);
+
+    esp_sleep_context_t sleep_ctx;
+    esp_sleep_set_sleep_context(&sleep_ctx);
+
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(true));
+#endif
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
+    TEST_ESP_OK(esp_light_sleep_start());
+#if ESP_SLEEP_POWER_DOWN_CPU
+    TEST_ESP_OK(sleep_cpu_configure(false));
+#endif
+    printf("check if the sleep happened as expected\r\n");
+    TEST_ASSERT_EQUAL(0, sleep_ctx.sleep_request_result);
+#if SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN
+    // check if the power domain also is powered down
+    TEST_ASSERT_EQUAL(allow_pd ? PMU_SLEEP_PD_TOP : 0, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#elif CONFIG_IDF_TARGET_ESP32P4
+    TEST_ASSERT_EQUAL(PMU_SLEEP_PD_TOP, (sleep_ctx.sleep_flags) & PMU_SLEEP_PD_TOP);
+#endif
+
+    TEST_ESP_OK(temperature_sensor_get_celsius(temp_handle, &tsens_result1));
+    printf("Temperature out celsius %f°C\n", tsens_result1);
+    TEST_ASSERT_FLOAT_WITHIN(6.0, tsens_result0, tsens_result1);
+
+    TEST_ESP_OK(temperature_sensor_disable(temp_handle));
+    TEST_ESP_OK(temperature_sensor_uninstall(temp_handle));
+}
+
+TEST_CASE("temperature sensor sleep retention test", "[temperature_sensor]")
+{
+    test_temperature_sensor_sleep_retention(false);
+#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+    test_temperature_sensor_sleep_retention(true);
+#endif
+}
+#endif
diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release
index 91d93f163e6..eb643d4d06b 100644
--- a/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release
+++ b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.ci.release
@@ -1,4 +1,5 @@
 CONFIG_PM_ENABLE=y
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
 CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
 CONFIG_COMPILER_OPTIMIZATION_SIZE=y
 CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
diff --git a/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults
index e4bfc208a55..a89cab2af3b 100644
--- a/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults
+++ b/components/esp_driver_tsens/test_apps/temperature_sensor/sdkconfig.defaults
@@ -1 +1,3 @@
 CONFIG_ESP_TASK_WDT_EN=n
+# primitives for checking sleep internal state
+CONFIG_ESP_SLEEP_DEBUG=y
diff --git a/components/esp_driver_uart/include/driver/uart.h b/components/esp_driver_uart/include/driver/uart.h
index aeb0176bfd1..42600a7b851 100644
--- a/components/esp_driver_uart/include/driver/uart.h
+++ b/components/esp_driver_uart/include/driver/uart.h
@@ -47,9 +47,9 @@ typedef struct {
 #endif
     };
     struct {
-        uint32_t backup_before_sleep: 1;    /*!< If set, the driver will backup/restore the HP UART registers before entering/after exiting sleep mode.
-                                                 By this approach, the system can power off HP UART's power domain.
-                                                 This can save power, but at the expense of more RAM being consumed */
+        uint32_t allow_pd: 1;               /*!< If set, driver allows the power domain to be powered off when system enters sleep mode.
+                                                 This can save power, but at the expense of more RAM being consumed to save register context. */
+        uint32_t backup_before_sleep: 1;    /*!< @deprecated, same meaning as allow_pd */
     } flags;                                /*!< Configuration flags */
 } uart_config_t;
 
@@ -67,18 +67,20 @@ typedef struct {
  * @brief UART event types used in the ring buffer
  */
 typedef enum {
-    UART_DATA,              /*!< UART data event*/
-    UART_BREAK,             /*!< UART break event*/
-    UART_BUFFER_FULL,       /*!< UART RX buffer full event*/
-    UART_FIFO_OVF,          /*!< UART FIFO overflow event*/
-    UART_FRAME_ERR,         /*!< UART RX frame error event*/
-    UART_PARITY_ERR,        /*!< UART RX parity event*/
-    UART_DATA_BREAK,        /*!< UART TX data and break event*/
-    UART_PATTERN_DET,       /*!< UART pattern detected */
+    UART_DATA,              /*!< Triggered when the receiver either takes longer than rx_timeout_thresh
+                                 to receive a byte, or when more data is received than what rxfifo_full_thresh
+                                 specifies*/
+    UART_BREAK,             /*!< Triggered when the receiver detects a NULL character*/
+    UART_BUFFER_FULL,       /*!< Triggered when RX ring buffer is full*/
+    UART_FIFO_OVF,          /*!< Triggered when the received data exceeds the capacity of the RX FIFO*/
+    UART_FRAME_ERR,         /*!< Triggered when the receiver detects a data frame error*/
+    UART_PARITY_ERR,        /*!< Triggered when a parity error is detected in the received data*/
+    UART_DATA_BREAK,        /*!< Internal event triggered to signal a break afte data transmission*/
+    UART_PATTERN_DET,       /*!< Triggered when a specified pattern  is detected in the incoming data*/
 #if SOC_UART_SUPPORT_WAKEUP_INT
-    UART_WAKEUP,            /*!< UART wakeup event */
+    UART_WAKEUP,            /*!< Triggered when a wakeup signal is detected*/
 #endif
-    UART_EVENT_MAX,         /*!< UART event max index*/
+    UART_EVENT_MAX,         /*!< Maximum index for UART events*/
 } uart_event_type_t;
 
 /**
diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c
index c8f5436ad2d..0008bdbc96b 100644
--- a/components/esp_driver_uart/src/uart.c
+++ b/components/esp_driver_uart/src/uart.c
@@ -221,7 +221,7 @@ static void uart_module_enable(uart_port_t uart_num)
             // Initialize sleep retention module for HP UART
             if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { // Console uart retention has been taken care in sleep_sys_periph_stdout_console_uart_retention_init
                 assert(!uart_context[uart_num].retention_link_inited);
-                sleep_retention_module_t module = UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num);
+                sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
                 sleep_retention_module_init_param_t init_param = {
                     .cbs = {
                         .create = {
@@ -260,7 +260,7 @@ static void uart_module_disable(uart_port_t uart_num)
         if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
 #if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
             // Uninitialize sleep retention module for HP UART
-            sleep_retention_module_t module = UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num);
+            sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
             assert(!uart_context[uart_num].retention_link_created); // HP UART sleep retention should have been freed at this moment
             if (uart_context[uart_num].retention_link_inited) {
                 sleep_retention_module_deinit(module);
@@ -856,8 +856,9 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
     ESP_RETURN_ON_FALSE((uart_config->flow_ctrl < UART_HW_FLOWCTRL_MAX), ESP_FAIL, UART_TAG, "hw_flowctrl mode error");
     ESP_RETURN_ON_FALSE((uart_config->data_bits < UART_DATA_BITS_MAX), ESP_FAIL, UART_TAG, "data bit error");
 
+    bool allow_pd __attribute__((unused)) = (uart_config->flags.allow_pd || uart_config->flags.backup_before_sleep);
 #if !SOC_UART_SUPPORT_SLEEP_RETENTION
-    ESP_RETURN_ON_FALSE(uart_config->flags.backup_before_sleep == 0, ESP_ERR_NOT_SUPPORTED, UART_TAG, "register back up is not supported");
+    ESP_RETURN_ON_FALSE(allow_pd == 0, ESP_ERR_NOT_SUPPORTED, UART_TAG, "not able to power down in light sleep");
 #endif
 
     uart_module_enable(uart_num);
@@ -866,8 +867,8 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
     // Create sleep retention link if desired
     if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
         _lock_acquire(&(uart_context[uart_num].mutex));
-        sleep_retention_module_t module = UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num);
-        if (uart_config->flags.backup_before_sleep && !uart_context[uart_num].retention_link_created) {
+        sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
+        if (allow_pd && !uart_context[uart_num].retention_link_created) {
             if (uart_context[uart_num].retention_link_inited) {
                 if (sleep_retention_module_allocate(module) == ESP_OK) {
                     uart_context[uart_num].retention_link_created = true;
@@ -878,7 +879,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
             } else {
                 ESP_LOGW(UART_TAG, "retention module not initialized first, unable to create retention module");
             }
-        } else if (!uart_config->flags.backup_before_sleep && uart_context[uart_num].retention_link_created) {
+        } else if (!allow_pd && uart_context[uart_num].retention_link_created) {
             assert(uart_context[uart_num].retention_link_inited);
             sleep_retention_module_free(module);
             uart_context[uart_num].retention_link_created = false;
@@ -1805,7 +1806,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
 #if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
     // Free sleep retention link for HP UART
     if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) {
-        sleep_retention_module_t module = UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num);
+        sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
         _lock_acquire(&(uart_context[uart_num].mutex));
         if (uart_context[uart_num].retention_link_created) {
             assert(uart_context[uart_num].retention_link_inited);
@@ -1979,7 +1980,7 @@ static esp_err_t uart_create_sleep_retention_link_cb(void *arg)
 {
     uart_context_t *group = (uart_context_t *)arg;
     uart_port_t uart_num = group->port_id;
-    sleep_retention_module_t module = UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num);
+    sleep_retention_module_t module = uart_reg_retention_info[uart_num].module;
     esp_err_t err = sleep_retention_entries_create(uart_reg_retention_info[uart_num].regdma_entry_array,
                                                    uart_reg_retention_info[uart_num].array_size,
                                                    REGDMA_LINK_PRI_UART, module);
diff --git a/components/esp_driver_uart/src/uart_vfs.c b/components/esp_driver_uart/src/uart_vfs.c
index 6e5a0dbfaf7..8d00ab43382 100644
--- a/components/esp_driver_uart/src/uart_vfs.c
+++ b/components/esp_driver_uart/src/uart_vfs.c
@@ -53,14 +53,18 @@
 typedef void (*tx_func_t)(int, int);
 // UART read bytes function type
 typedef int (*rx_func_t)(int);
+// UART get available received bytes function type
+typedef size_t (*get_available_data_len_func_t)(int);
 
-// Basic functions for sending and receiving bytes over UART
+// Basic functions for sending, receiving bytes, and get available data length over UART
 static void uart_tx_char(int fd, int c);
 static int uart_rx_char(int fd);
+static size_t uart_get_avail_data_len(int fd);
 
-// Functions for sending and receiving bytes which use UART driver
+// Functions for sending, receiving bytes, and get available data length which use UART driver
 static void uart_tx_char_via_driver(int fd, int c);
 static int uart_rx_char_via_driver(int fd);
+static size_t uart_get_avail_data_len_via_driver(int fd);
 
 typedef struct {
     // Pointers to UART peripherals
@@ -82,6 +86,8 @@ typedef struct {
     tx_func_t tx_func;
     // Functions used to read bytes from UART. Default to "basic" functions.
     rx_func_t rx_func;
+    // Function used to get available data bytes from UART. Default to "basic" functions.
+    get_available_data_len_func_t get_avail_data_len_func;
 } uart_vfs_context_t;
 
 #define VFS_CTX_DEFAULT_VAL(uart_dev) (uart_vfs_context_t) {\
@@ -91,6 +97,7 @@ typedef struct {
     .rx_mode = DEFAULT_RX_MODE,\
     .tx_func = uart_tx_char,\
     .rx_func = uart_rx_char,\
+    .get_avail_data_len_func = uart_get_avail_data_len,\
 }
 
 //If the context should be dynamically initialized, remove this structure
@@ -162,6 +169,19 @@ static int uart_open(const char *path, int flags, int mode)
     return fd;
 }
 
+size_t uart_get_avail_data_len(int fd)
+{
+    uart_dev_t* uart = s_ctx[fd]->uart;
+    return uart_ll_get_rxfifo_len(uart);
+}
+
+size_t uart_get_avail_data_len_via_driver(int fd)
+{
+    size_t buffered_size = 0;
+    uart_get_buffered_data_len(fd, &buffered_size);
+    return buffered_size;
+}
+
 static void uart_tx_char(int fd, int c)
 {
     uart_dev_t* uart = s_ctx[fd]->uart;
@@ -253,38 +273,65 @@ static ssize_t uart_read(int fd, void* data, size_t size)
     assert(fd >= 0 && fd < 3);
     char *data_c = (char *) data;
     size_t received = 0;
+    size_t available_size = 0;
+    int c = NONE; // store the read char
     _lock_acquire_recursive(&s_ctx[fd]->read_lock);
-    while (received < size) {
-        int c = uart_read_char(fd);
-        if (c == '\r') {
-            if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CR) {
-                c = '\n';
-            } else if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CRLF) {
-                /* look ahead */
-                int c2 = uart_read_char(fd);
-                if (c2 == NONE) {
-                    /* could not look ahead, put the current character back */
-                    uart_return_char(fd, c);
-                    break;
-                }
-                if (c2 == '\n') {
-                    /* this was \r\n sequence. discard \r, return \n */
+
+    if (!s_ctx[fd]->non_blocking) {
+        c = uart_read_char(fd); // blocking until data available for non-O_NONBLOCK mode
+    }
+
+    // find the actual fetch size
+    available_size += s_ctx[fd]->get_avail_data_len_func(fd);
+    if (c != NONE) {
+        available_size++;
+    }
+    if (s_ctx[fd]->peek_char != NONE) {
+        available_size++;
+    }
+    size_t fetch_size = MIN(available_size, size);
+
+    if (fetch_size > 0) {
+        do {
+            if (c == NONE) { // for non-O_NONBLOCK mode, there is already a pre-fetched char
+                c = uart_read_char(fd);
+            }
+            assert(c != NONE);
+
+            if (c == '\r') {
+                if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CR) {
                     c = '\n';
-                } else {
-                    /* \r followed by something else. put the second char back,
-                     * it will be processed on next iteration. return \r now.
-                     */
-                    uart_return_char(fd, c2);
+                } else if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CRLF) {
+                    /* look ahead */
+                    int c2 = uart_read_char(fd);
+                    fetch_size--;
+                    if (c2 == NONE) {
+                        /* could not look ahead, put the current character back */
+                        uart_return_char(fd, c);
+                        c = NONE;
+                        break;
+                    }
+                    if (c2 == '\n') {
+                        /* this was \r\n sequence. discard \r, return \n */
+                        c = '\n';
+                    } else {
+                        /* \r followed by something else. put the second char back,
+                         * it will be processed on next iteration. return \r now.
+                         */
+                        uart_return_char(fd, c2);
+                        fetch_size++;
+                    }
                 }
             }
-        } else if (c == NONE) {
-            break;
-        }
-        data_c[received] = (char) c;
-        ++received;
-        if (c == '\n') {
-            break;
-        }
+
+            data_c[received] = (char) c;
+            ++received;
+            c = NONE;
+        } while (received < fetch_size);
+    }
+
+    if (c != NONE) { // fetched, but not used
+        uart_return_char(fd, c);
     }
     _lock_release_recursive(&s_ctx[fd]->read_lock);
     if (received > 0) {
@@ -1061,6 +1108,7 @@ void uart_vfs_dev_use_nonblocking(int uart_num)
     _lock_acquire_recursive(&s_ctx[uart_num]->write_lock);
     s_ctx[uart_num]->tx_func = uart_tx_char;
     s_ctx[uart_num]->rx_func = uart_rx_char;
+    s_ctx[uart_num]->get_avail_data_len_func = uart_get_avail_data_len;
     _lock_release_recursive(&s_ctx[uart_num]->write_lock);
     _lock_release_recursive(&s_ctx[uart_num]->read_lock);
 }
@@ -1071,6 +1119,7 @@ void uart_vfs_dev_use_driver(int uart_num)
     _lock_acquire_recursive(&s_ctx[uart_num]->write_lock);
     s_ctx[uart_num]->tx_func = uart_tx_char_via_driver;
     s_ctx[uart_num]->rx_func = uart_rx_char_via_driver;
+    s_ctx[uart_num]->get_avail_data_len_func = uart_get_avail_data_len_via_driver;
     _lock_release_recursive(&s_ctx[uart_num]->write_lock);
     _lock_release_recursive(&s_ctx[uart_num]->read_lock);
 }
diff --git a/components/esp_driver_uart/test_apps/uart/CMakeLists.txt b/components/esp_driver_uart/test_apps/uart/CMakeLists.txt
index a79832e8c84..35ec00faba4 100644
--- a/components/esp_driver_uart/test_apps/uart/CMakeLists.txt
+++ b/components/esp_driver_uart/test_apps/uart/CMakeLists.txt
@@ -21,3 +21,8 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
                       DEPENDS ${elf}
                       )
 endif()
+
+message(STATUS "Checking uart registers are not read-write by half-word")
+include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
+check_register_rw_half_word(SOC_MODULES "uart" "pcr" "hp_sys_clkrst" "lp_clkrst" "lpperi"
+                            HAL_MODULES "uart")
diff --git a/components/esp_driver_uart/test_apps/uart/main/test_uart_retention.c b/components/esp_driver_uart/test_apps/uart/main/test_uart_retention.c
index 692d24f72f8..d230a84987a 100644
--- a/components/esp_driver_uart/test_apps/uart/main/test_uart_retention.c
+++ b/components/esp_driver_uart/test_apps/uart/main/test_uart_retention.c
@@ -17,7 +17,7 @@
 
 static const uart_port_t uart_num = UART_NUM_1;
 
-static void uart_init(bool backup_before_sleep)
+static void uart_init(bool allow_pd)
 {
     uart_config_t uart_config = {
         .baud_rate = 115200,
@@ -26,7 +26,7 @@ static void uart_init(bool backup_before_sleep)
         .stop_bits = UART_STOP_BITS_1,
         .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
         .source_clk = UART_SCLK_DEFAULT,
-        .flags.backup_before_sleep = backup_before_sleep,
+        .flags.allow_pd = allow_pd,
     };
 
     TEST_ESP_OK(uart_driver_install(uart_num, 256, 0, 20, NULL, 0));
@@ -120,7 +120,7 @@ TEST_CASE("uart won't be powered down in light sleep if retention not created",
     TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
     sleep_cpu_configure(true);
 
-    uart_init(false); // backup_before_sleep set to false, sleep retention module will be inited, but not created
+    uart_init(false); // allow_pd set to false, sleep retention module will be inited, but not created
 
     // Ensure UART is fully idle before starting loopback RX/TX test
     TEST_ESP_OK(uart_wait_tx_done(uart_num, portMAX_DELAY));
diff --git a/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c b/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c
index 5cf95429d32..b3266a625d9 100644
--- a/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c
+++ b/components/esp_driver_uart/test_apps/uart_vfs/main/test_vfs_uart.c
@@ -74,6 +74,12 @@ TEST_CASE("CRs are removed from the stdin correctly", "[vfs_uart]")
     uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF);
 
     flush_stdin_stdout();
+
+    // A test case with no use of uart driver
+    // For non-uart-driver-involved uart vfs, all reads are non-blocking
+    // If no data at the moment, read() returns directly;
+    // If there is data available at the moment, read() also returns directly with the currently available size
+
     const char* send_str = "1234567890\n\r123\r\n4\n";
     /* with CONFIG_NEWLIB_STDOUT_ADDCR, the following will be sent on the wire.
      * (last character of each part is marked with a hat)
@@ -133,30 +139,46 @@ struct read_task_arg_t {
 
 struct write_task_arg_t {
     const char* str;
+    size_t str_len;
     SemaphoreHandle_t done;
 };
 
-static void read_task_fn(void* varg)
+static void read_blocking_task_fn(void* varg)
 {
     struct read_task_arg_t* parg = (struct read_task_arg_t*) varg;
-    parg->out_buffer[0] = 0;
+    memset(parg->out_buffer, 0, parg->out_buffer_len);
 
     fgets(parg->out_buffer, parg->out_buffer_len, stdin);
     xSemaphoreGive(parg->done);
     vTaskDelete(NULL);
 }
 
+static void read_non_blocking_task_fn(void* varg)
+{
+    struct read_task_arg_t* parg = (struct read_task_arg_t*) varg;
+    memset(parg->out_buffer, 0, parg->out_buffer_len);
+    char *ptr = parg->out_buffer;
+
+    while (fgets(ptr, parg->out_buffer_len, stdin) != NULL) {
+        while (*ptr != 0) {
+            ptr++;
+        }
+    }
+    xSemaphoreGive(parg->done);
+    vTaskDelete(NULL);
+}
+
 static void write_task_fn(void* varg)
 {
     struct write_task_arg_t* parg = (struct write_task_arg_t*) varg;
-    fwrite_str_loopback(parg->str, strlen(parg->str));
+    fwrite_str_loopback(parg->str, parg->str_len);
     xSemaphoreGive(parg->done);
     vTaskDelete(NULL);
 }
 
-TEST_CASE("can write to UART while another task is reading", "[vfs_uart]")
+TEST_CASE("read with uart driver (blocking)", "[vfs_uart]")
 {
-    char out_buffer[32];
+    char out_buffer[32] = {};
     size_t out_buffer_len = sizeof(out_buffer);
 
     struct read_task_arg_t read_arg = {
@@ -165,8 +187,12 @@ TEST_CASE("can write to UART while another task is reading", "[vfs_uart]")
         .done = xSemaphoreCreateBinary()
     };
 
+    // Send a string with length less than the read requested length
+    const char in_buffer[] = "!(@*#&(!*@&#((SDasdkjhadsl\n";
+    size_t in_buffer_len = sizeof(in_buffer);
     struct write_task_arg_t write_arg = {
-        .str = "!(@*#&(!*@&#((SDasdkjhadsl\n",
+        .str = in_buffer,
+        .str_len = in_buffer_len,
         .done = xSemaphoreCreateBinary()
     };
 
@@ -176,14 +202,18 @@ TEST_CASE("can write to UART while another task is reading", "[vfs_uart]")
                                         256, 0, 0, NULL, 0));
     uart_vfs_dev_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
 
-    xTaskCreate(&read_task_fn, "vfs_read", 4096, &read_arg, 5, NULL);
-    vTaskDelay(10);
+    // Start the read task first, it will block until data incoming
+    xTaskCreate(&read_blocking_task_fn, "vfs_read", 4096, &read_arg, 5, NULL);
+
+    int res = xSemaphoreTake(read_arg.done, 100 / portTICK_PERIOD_MS);
+    TEST_ASSERT_FALSE(res);
+
     xTaskCreate(&write_task_fn, "vfs_write", 4096, &write_arg, 6, NULL);
 
-    int res = xSemaphoreTake(write_arg.done, 100 / portTICK_PERIOD_MS);
+    res = xSemaphoreTake(write_arg.done, 100 / portTICK_PERIOD_MS);
     TEST_ASSERT(res);
 
-    res = xSemaphoreTake(read_arg.done, 100 / portTICK_PERIOD_MS);
+    res = xSemaphoreTake(read_arg.done, 100 / portTICK_PERIOD_MS); // read() returns with currently available size
     TEST_ASSERT(res);
 
     TEST_ASSERT_EQUAL(0, strcmp(write_arg.str, read_arg.out_buffer));
@@ -195,6 +225,69 @@ TEST_CASE("can write to UART while another task is reading", "[vfs_uart]")
     vTaskDelay(2);  // wait for tasks to exit
 }
 
+TEST_CASE("read with uart driver (non-blocking)", "[vfs_uart]")
+{
+    char out_buffer[32] = {};
+    size_t out_buffer_len = sizeof(out_buffer);
+
+    struct read_task_arg_t read_arg = {
+        .out_buffer = out_buffer,
+        .out_buffer_len = out_buffer_len,
+        .done = xSemaphoreCreateBinary()
+    };
+
+    // Send a string with length less than the read requested length
+    const char in_buffer[] = "!(@*#&(!*@&#((SDasdkjhad\nce"; // read should not early return on \n
+    size_t in_buffer_len = sizeof(in_buffer);
+    struct write_task_arg_t write_arg = {
+        .str = in_buffer,
+        .str_len = in_buffer_len,
+        .done = xSemaphoreCreateBinary()
+    };
+
+    flush_stdin_stdout();
+
+    ESP_ERROR_CHECK(uart_driver_install(CONFIG_ESP_CONSOLE_UART_NUM,
+                                        256, 0, 0, NULL, 0));
+    uart_vfs_dev_use_driver(CONFIG_ESP_CONSOLE_UART_NUM);
+
+    uart_vfs_dev_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_LF);
+    uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_LF);
+
+    int flags = fcntl(STDIN_FILENO, F_GETFL, 0);
+    fcntl(STDIN_FILENO, F_SETFL, flags | O_NONBLOCK);
+
+    // If start the read task first, it will return immediately
+    xTaskCreate(&read_non_blocking_task_fn, "vfs_read", 4096, &read_arg, 5, NULL);
+
+    int res = xSemaphoreTake(read_arg.done, 100 / portTICK_PERIOD_MS);
+    TEST_ASSERT(res);
+
+    xTaskCreate(&write_task_fn, "vfs_write", 4096, &write_arg, 6, NULL);
+    vTaskDelay(10);
+    xTaskCreate(&read_non_blocking_task_fn, "vfs_read", 4096, &read_arg, 5, NULL);
+
+    res = xSemaphoreTake(write_arg.done, 100 / portTICK_PERIOD_MS);
+    TEST_ASSERT(res);
+
+    res = xSemaphoreTake(read_arg.done, 1000 / portTICK_PERIOD_MS); // read() returns with currently available size
+    TEST_ASSERT(res);
+
+    // string compare
+    for (int i = 0; i < in_buffer_len; i++) {
+        TEST_ASSERT_EQUAL(in_buffer[i], out_buffer[i]);
+    }
+
+    uart_vfs_dev_use_nonblocking(CONFIG_ESP_CONSOLE_UART_NUM);
+    fcntl(STDIN_FILENO, F_SETFL, flags);
+    uart_vfs_dev_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF);
+    uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF);
+    uart_driver_delete(CONFIG_ESP_CONSOLE_UART_NUM);
+    vSemaphoreDelete(read_arg.done);
+    vSemaphoreDelete(write_arg.done);
+    vTaskDelay(2);  // wait for tasks to exit
+}
+
 TEST_CASE("fcntl supported in UART VFS", "[vfs_uart]")
 {
     int flags = fcntl(STDIN_FILENO, F_GETFL, 0);
diff --git a/components/esp_eth/CMakeLists.txt b/components/esp_eth/CMakeLists.txt
index 132f01a3011..6a6941397d6 100644
--- a/components/esp_eth/CMakeLists.txt
+++ b/components/esp_eth/CMakeLists.txt
@@ -30,6 +30,7 @@ if(CONFIG_ETH_ENABLED)
         list(APPEND srcs "src/mac/esp_eth_mac_esp.c"
                          "src/mac/esp_eth_mac_esp_dma.c"
                          "src/mac/esp_eth_mac_esp_gpio.c"
+                         "src/phy/esp_eth_phy_generic.c"
                          "src/phy/esp_eth_phy_dp83848.c"
                          "src/phy/esp_eth_phy_ip101.c"
                          "src/phy/esp_eth_phy_ksz80xx.c"
diff --git a/components/esp_eth/include/esp_eth_com.h b/components/esp_eth/include/esp_eth_com.h
index a2c49459438..5435fddb32b 100644
--- a/components/esp_eth/include/esp_eth_com.h
+++ b/components/esp_eth/include/esp_eth_com.h
@@ -92,6 +92,20 @@ struct esp_eth_mediator_s {
     */
     esp_err_t (*stack_input)(esp_eth_mediator_t *eth, uint8_t *buffer, uint32_t length);
 
+    /**
+    * @brief Deliver packet to upper stack with additional information about reception
+    *
+    * @param[in] eth: mediator of Ethernet driver
+    * @param[in] buffer: packet buffer
+    * @param[in] length: length of the packet
+    * @param[in] info: info associated with reception (e.g. time stamp)
+    *
+    * @return
+    *       - ESP_OK: deliver packet to upper stack successfully
+    *       - ESP_FAIL: deliver packet failed because some error occurred
+    */
+    esp_err_t (*stack_input_info)(esp_eth_mediator_t *eth, uint8_t *buffer, uint32_t length, void *info);
+
     /**
     * @brief Callback on Ethernet state changed
     *
diff --git a/components/esp_eth/include/esp_eth_driver.h b/components/esp_eth/include/esp_eth_driver.h
index 3a253f71c45..0c5f183caca 100644
--- a/components/esp_eth/include/esp_eth_driver.h
+++ b/components/esp_eth/include/esp_eth_driver.h
@@ -56,6 +56,7 @@ typedef struct {
     * @param[in] eth_handle: handle of Ethernet driver
     * @param[in] buffer: frame buffer that will get input to upper stack
     * @param[in] length: length of the frame buffer
+    * @param[in] priv pointer to private resource, defined when registering the input function
     *
     * @return
     *      - ESP_OK: input frame buffer to upper stack successfully
@@ -64,6 +65,22 @@ typedef struct {
     */
     esp_err_t (*stack_input)(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv);
 
+    /**
+    * @brief Input frame buffer to user's stack with additional information about received frame
+    *
+    * @param[in] eth_handle: handle of Ethernet driver
+    * @param[in] buffer: frame buffer that will get input to upper stack
+    * @param[in] length: length of the frame buffer
+    * @param[in] priv pointer to private resource, defined when registering the input function
+    * @param[in] info: extra information about received Ethernet frame (may be timestamp, CRC offload check result, etc.)
+    *
+    * @return
+    *      - ESP_OK: input frame buffer to upper stack successfully
+    *      - ESP_FAIL: error occurred when inputting buffer to upper stack
+    *
+    */
+    esp_err_t (*stack_input_info)(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv, void *info);
+
     /**
     * @brief Callback function invoked when lowlevel initialization is finished
     *
@@ -173,6 +190,7 @@ typedef enum {
         .phy = ephy,                     \
         .check_link_period_ms = 2000,    \
         .stack_input = NULL,             \
+        .stack_input_info = NULL,        \
         .on_lowlevel_init_done = NULL,   \
         .on_lowlevel_deinit_done = NULL, \
         .read_phy_reg = NULL,            \
@@ -257,6 +275,31 @@ esp_err_t esp_eth_update_input_path(
     esp_err_t (*stack_input)(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t length, void *priv),
     void *priv);
 
+/**
+* @brief Update Ethernet data input path with input function which consumes extra info about received frame.
+*
+* @note Extra information may include but is not limited to such info like Time Stamp, CRC check offload result, etc.
+*       The MAC layer of the Ethernet driver of the particular device must provide extra information using
+*       `stack_input_info()` function. Otherwise, input path function registered by this API is not invoked. If this
+*       is the case, register `stack_input` function by `esp_eth_update_input_path()` instead.
+*
+* @note After install driver, Ethernet still don't know where to deliver the input buffer.
+*       In fact, this API registers a callback function which get invoked when Ethernet received new packets.
+*
+* @param[in] hdl handle of Ethernet driver
+* @param[in] stack_input_info function pointer, which does the actual process on incoming packets
+* @param[in] priv private resource, which gets passed to `stack_input_info` callback without any modification
+*
+* @return
+*       - ESP_OK: update input path successfully
+*       - ESP_ERR_INVALID_ARG: update input path failed because of some invalid argument
+*       - ESP_FAIL: update input path failed because some other error occurred
+*/
+esp_err_t esp_eth_update_input_path_info(
+    esp_eth_handle_t hdl,
+    esp_err_t (*stack_input_info)(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t length, void *priv, void *info),
+    void *priv);
+
 /**
 * @brief General Transmit
 *
@@ -267,25 +310,45 @@ esp_err_t esp_eth_update_input_path(
 * @return
 *       - ESP_OK: transmit frame buffer successfully
 *       - ESP_ERR_INVALID_ARG: transmit frame buffer failed because of some invalid argument
-*       - ESP_ERR_INVALID_STATE: invalid driver state (e.i. driver is not started)
+*       - ESP_ERR_INVALID_STATE: invalid driver state (e.i., driver is not started)
 *       - ESP_ERR_TIMEOUT: transmit frame buffer failed because HW was not get available in predefined period
 *       - ESP_FAIL: transmit frame buffer failed because some other error occurred
 */
 esp_err_t esp_eth_transmit(esp_eth_handle_t hdl, void *buf, size_t length);
 
 /**
-* @brief Special Transmit with variable number of arguments
+ * @brief Extended Transmit with variable number of arguments
+ *
+ * @note Typical intended use case of this function is to assemble Ethernet frame from multiple input buffers
+ *       at lower layer of the driver (MAC layer) to avoid unnecessary buffer reallocation and copy.
+ *
+ * @param hdl handle of Ethernet driver
+ * @param ctrl optional transmit control structure (MAC specific), set to NULL when not required
+ * @param argc number variable arguments
+ * @param ... variable arguments
+ * @return
+ *       - ESP_OK: transmit successful
+ *       - ESP_ERR_INVALID_STATE: invalid driver state (e.i., driver is not started)
+ *       - ESP_ERR_TIMEOUT: transmit frame buffer failed because HW was not get available in predefined period
+ *       - ESP_FAIL: transmit frame buffer failed because some other error occurred
+ */
+esp_err_t esp_eth_transmit_ctrl_vargs(esp_eth_handle_t hdl, void *ctrl, uint32_t argc, ...);
+
+/**
+* @brief Wrapper over Extended Transmit function to ensure backward compatibility.
 *
-* @param[in] hdl handle of Ethernet driver
+* @note For new implementations, it is recommended to use `esp_eth_transmit_ctrl_vargs()` directly.
+*
+* @param[in] eth_hdl handle of Ethernet driver
 * @param[in] argc number variable arguments
 * @param ... variable arguments
 * @return
 *       - ESP_OK: transmit successful
-*       - ESP_ERR_INVALID_STATE: invalid driver state (e.i. driver is not started)
+*       - ESP_ERR_INVALID_STATE: invalid driver state (e.i., driver is not started)
 *       - ESP_ERR_TIMEOUT: transmit frame buffer failed because HW was not get available in predefined period
 *       - ESP_FAIL: transmit frame buffer failed because some other error occurred
 */
-esp_err_t esp_eth_transmit_vargs(esp_eth_handle_t hdl, uint32_t argc, ...);
+#define esp_eth_transmit_vargs(eth_hdl, argc, ...) esp_eth_transmit_ctrl_vargs(eth_hdl, NULL, (argc) * 2, ##__VA_ARGS__)
 
 /**
 * @brief Misc IO function of Ethernet driver
diff --git a/components/esp_eth/include/esp_eth_mac.h b/components/esp_eth/include/esp_eth_mac.h
index cabfb127239..740442dcbb8 100644
--- a/components/esp_eth/include/esp_eth_mac.h
+++ b/components/esp_eth/include/esp_eth_mac.h
@@ -104,9 +104,32 @@ struct esp_eth_mac_s {
     */
     esp_err_t (*transmit)(esp_eth_mac_t *mac, uint8_t *buf, uint32_t length);
 
+    /**
+    * @brief Transmit packet with extended control from Ethernet MAC and constructed with special parameters at Layer2.
+    *
+    * @param[in] mac: Ethernet MAC instance
+    * @param[in] ctrl: optional transmit control structure (chip specific), set to NULL when not required
+    * @param[in] argc: number variable arguments
+    * @param[in] args: variable arguments
+    *
+    * @note Typical intended use case is to make possible to construct a frame from multiple higher layer
+    *       buffers without a need of buffer reallocations. However, other use cases are not limited.
+    *
+    * @return
+    *      - ESP_OK: transmit packet successfully
+    *      - ESP_ERR_INVALID_SIZE: number of actually sent bytes differs to expected
+    *      - ESP_FAIL: transmit packet failed because some other error occurred
+    *
+    * @note Returned error codes may differ for each specific MAC chip.
+    *
+    */
+    esp_err_t (*transmit_ctrl_vargs)(esp_eth_mac_t *mac, void *ctrl, uint32_t argc, va_list args);
+
     /**
     * @brief Transmit packet from Ethernet MAC constructed with special parameters at Layer2.
     *
+    * @warning Deprecated, use `transmit_ctrl_vargs()` function instead.
+    *
     * @param[in] mac: Ethernet MAC instance
     * @param[in] argc: number variable arguments
     * @param[in] args: variable arguments
@@ -122,7 +145,7 @@ struct esp_eth_mac_s {
     * @note Returned error codes may differ for each specific MAC chip.
     *
     */
-    esp_err_t (*transmit_vargs)(esp_eth_mac_t *mac, uint32_t argc, va_list args);
+    esp_err_t (*transmit_vargs)(esp_eth_mac_t *mac, uint32_t argc, va_list args) __attribute__((deprecated("Use transmit_ctrl_vargs instead")));
 
     /**
     * @brief Receive packet from Ethernet MAC
@@ -318,6 +341,15 @@ struct esp_eth_mac_s {
     esp_err_t (*del)(esp_eth_mac_t *mac);
 };
 
+/**
+ * @brief Ethernet MAC Time Stamp
+ *
+ */
+typedef struct {
+    uint32_t seconds;       /*!< Seconds */
+    uint32_t nanoseconds;   /*!< Nanoseconds */
+} eth_mac_time_t;
+
 /**
 * @brief Configuration of Ethernet MAC object
 *
diff --git a/components/esp_eth/include/esp_eth_mac_esp.h b/components/esp_eth/include/esp_eth_mac_esp.h
index f18bf4d75c5..bb62cf7719f 100644
--- a/components/esp_eth/include/esp_eth_mac_esp.h
+++ b/components/esp_eth/include/esp_eth_mac_esp.h
@@ -192,8 +192,30 @@ typedef enum {
     ETH_MAC_ESP_CMD_SET_TDES0_CFG_BITS = ETH_CMD_CUSTOM_MAC_CMDS_OFFSET,    /*!< Set Transmit Descriptor Word 0 control bit mask (debug option)*/
     ETH_MAC_ESP_CMD_CLEAR_TDES0_CFG_BITS,                                   /*!< Clear Transmit Descriptor Word 0 control bit mask (debug option)*/
     ETH_MAC_ESP_CMD_PTP_ENABLE,                                             /*!< Enable IEEE1588 Time stamping */
+    ETH_MAC_ESP_CMD_S_PTP_TIME,                                             /*!< Set PTP time in the module */
+    ETH_MAC_ESP_CMD_G_PTP_TIME,                                             /*!< Get PTP time from the module */
+    ETH_MAC_ESP_CMD_ADJ_PTP_FREQ,                                           /*!< Adjust current PTP time frequency increment by scale factor */
+    ETH_MAC_ESP_CMD_ADJ_PTP_TIME,                                           /*!< Adjust base PTP time frequency increment by PPS */
+    ETH_MAC_ESP_CMD_S_TARGET_TIME,                                          /*!< Set Target Time at which interrupt is invoked when PTP time exceeds this value*/
+    ETH_MAC_ESP_CMD_S_TARGET_CB                                             /*!< Set pointer to a callback function invoked when PTP time exceeds Target Time */
 } eth_mac_esp_io_cmd_t;
 
+#ifdef SOC_EMAC_IEEE1588V2_SUPPORTED
+/**
+ * @brief Type of callback function invoked under Time Stamp target time exceeded interrupt
+ *
+ * @warning Time stamping is currently Experimental Feature! Be aware that API may change.
+ *
+ * @param eth: mediator of Ethernet driver
+ * @param user_args user specific arguments (placeholder - IDF-11429)
+ *
+ * @return
+ *          - TRUE when high priority task has been woken by this function
+ *          - FALSE no high priority task was woken by this function
+ */
+typedef bool (*ts_target_exceed_cb_from_isr_t)(esp_eth_mediator_t *eth, void *user_args);
+#endif // SOC_EMAC_IEEE1588V2_SUPPORTED
+
 /**
  * @brief Default ESP32's EMAC specific configuration
  *
@@ -242,7 +264,7 @@ typedef enum {
         .smi_gpio =                                                           \
         {                                                                     \
             .mdc_num = 31,                                                    \
-            .mdio_num = 27                                                    \
+            .mdio_num = 52                                                    \
         },                                                                    \
         .interface = EMAC_DATA_INTERFACE_RMII,                                \
         .clock_config =                                                       \
diff --git a/components/esp_eth/include/esp_eth_phy.h b/components/esp_eth/include/esp_eth_phy.h
index 82c16aef41d..109a8014dc4 100644
--- a/components/esp_eth/include/esp_eth_phy.h
+++ b/components/esp_eth/include/esp_eth_phy.h
@@ -13,7 +13,8 @@
 extern "C" {
 #endif
 
-#define ESP_ETH_PHY_ADDR_AUTO (-1)
+#define ESP_ETH_PHY_ADDR_AUTO           (-1)
+#define ESP_ETH_NO_POST_HW_RESET_DELAY  (-1)
 
 /**
  * @brief Auto-negotiation control commands
@@ -273,24 +274,45 @@ struct esp_eth_phy_s {
 *
 */
 typedef struct {
-    int32_t phy_addr;             /*!< PHY address, set -1 to enable PHY address detection at initialization stage */
-    uint32_t reset_timeout_ms;    /*!< Reset timeout value (Unit: ms) */
-    uint32_t autonego_timeout_ms; /*!< Auto-negotiation timeout value (Unit: ms) */
-    int reset_gpio_num;           /*!< Reset GPIO number, -1 means no hardware reset */
+    int32_t phy_addr;                 /*!< PHY address, set -1 to enable PHY address detection at initialization stage */
+    uint32_t reset_timeout_ms;        /*!< Reset timeout value (Unit: ms) */
+    uint32_t autonego_timeout_ms;     /*!< Auto-negotiation timeout value (Unit: ms) */
+    int reset_gpio_num;               /*!< Reset GPIO number, -1 means no hardware reset */
+    int32_t hw_reset_assert_time_us;  /*!< Time the reset pin is asserted (Unit: us), 0 to use chip specific default */
+    int32_t post_hw_reset_delay_ms;   /*!< Time to wait after the HW reset (Unit: ms), 0 to use chip specific default, -1 means no wait */
 } eth_phy_config_t;
 
 /**
  * @brief Default configuration for Ethernet PHY object
  *
  */
-#define ETH_PHY_DEFAULT_CONFIG()           \
-    {                                      \
-        .phy_addr = ESP_ETH_PHY_ADDR_AUTO, \
-        .reset_timeout_ms = 100,           \
-        .autonego_timeout_ms = 4000,       \
-        .reset_gpio_num = 5,               \
+#define ETH_PHY_DEFAULT_CONFIG()               \
+    {                                          \
+        .phy_addr = ESP_ETH_PHY_ADDR_AUTO,     \
+        .reset_timeout_ms = 100,               \
+        .autonego_timeout_ms = 4000,           \
+        .reset_gpio_num = 5,                   \
+        .hw_reset_assert_time_us = 0,         \
+        .post_hw_reset_delay_ms = 0           \
     }
 
+/**
+* @brief Create a PHY instance of generic chip which conforms with IEEE 802.3
+*
+* @note Default reset timing configuration is set conservatively( @c DEFAULT_PHY_RESET_ASSERTION_TIME_US ).
+*       If you need faster response and your chip supports it, configure it via @c config parameter.
+*
+* @warning While basic functionality should always work, some specific features might be limited,
+*          even if the PHY meets IEEE 802.3 standard. A typical example is loopback functionality,
+*          where certain PHYs may require setting a specific speed mode to operate correctly.
+*
+* @param[in] config configuration of PHY
+* @return
+*      - instance: create PHY instance successfully
+*      - NULL: create PHY instance failed because some error occurred
+ */
+esp_eth_phy_t *esp_eth_phy_new_generic(const eth_phy_config_t *config);
+
 /**
 * @brief Create a PHY instance of IP101
 *
diff --git a/components/esp_eth/include/esp_eth_phy_802_3.h b/components/esp_eth/include/esp_eth_phy_802_3.h
index 0cc83ed1390..e90646bd37d 100644
--- a/components/esp_eth/include/esp_eth_phy_802_3.h
+++ b/components/esp_eth/include/esp_eth_phy_802_3.h
@@ -19,13 +19,15 @@ extern "C" {
  *
  */
 typedef struct {
-    esp_eth_phy_t parent;           /*!< Parent Ethernet PHY instance */
-    esp_eth_mediator_t *eth;        /*!< Mediator of Ethernet driver */
-    int addr;                       /*!< PHY address */
-    uint32_t reset_timeout_ms;      /*!< Reset timeout value (Unit: ms) */
-    uint32_t autonego_timeout_ms;   /*!< Auto-negotiation timeout value (Unit: ms) */
-    eth_link_t link_status;         /*!< Current Link status */
-    int reset_gpio_num;             /*!< Reset GPIO number, -1 means no hardware reset */
+    esp_eth_phy_t parent;              /*!< Parent Ethernet PHY instance */
+    esp_eth_mediator_t *eth;           /*!< Mediator of Ethernet driver */
+    int addr;                          /*!< PHY address */
+    uint32_t reset_timeout_ms;         /*!< Reset timeout value (Unit: ms) */
+    uint32_t autonego_timeout_ms;      /*!< Auto-negotiation timeout value (Unit: ms) */
+    eth_link_t link_status;            /*!< Current Link status */
+    int reset_gpio_num;                /*!< Reset GPIO number, -1 means no hardware reset */
+    int32_t hw_reset_assert_time_us;   /*!< Time the reset pin is asserted (Unit: us) */
+    int32_t post_hw_reset_delay_ms;    /*!< Time to wait after the HW reset (Unit: ms) */
 } phy_802_3_t;
 
 /**
@@ -73,6 +75,16 @@ esp_err_t esp_eth_phy_802_3_reset(phy_802_3_t *phy_802_3);
  */
 esp_err_t esp_eth_phy_802_3_autonego_ctrl(phy_802_3_t *phy_802_3, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat);
 
+/**
+ * @brief Retrieve link status and propagate the status to higher layers if the status changed
+ *
+ * @param phy_802_3 IEEE 802.3 PHY object infostructure
+ * @return
+ *      - ESP_OK: Ethernet PHY link status retrieved successfully
+ *      - ESP_FAIL: Error occurred during reading registry
+ */
+esp_err_t esp_eth_phy_802_3_updt_link_dup_spd(phy_802_3_t *phy_802_3);
+
 /**
  * @brief Power control of Ethernet PHY
  *
@@ -183,7 +195,7 @@ esp_err_t esp_eth_phy_802_3_deinit(phy_802_3_t *phy_802_3);
  *
  * @param phy_802_3 IEEE 802.3 PHY object infostructure
  * @return
- *      - ESP_OK: Ethrnet PHY infostructure deleted
+ *      - ESP_OK: Ethernet PHY infostructure deleted
  */
 esp_err_t esp_eth_phy_802_3_del(phy_802_3_t *phy_802_3);
 
@@ -194,6 +206,7 @@ esp_err_t esp_eth_phy_802_3_del(phy_802_3_t *phy_802_3);
  * @param reset_assert_us Hardware reset pin assertion time
  * @return
  *      - ESP_OK: reset Ethernet PHY successfully
+ *      - ESP_ERR_NOT_ALLOWED: reset GPIO not defined
  */
 esp_err_t esp_eth_phy_802_3_reset_hw(phy_802_3_t *phy_802_3, uint32_t reset_assert_us);
 
diff --git a/components/esp_eth/include/esp_private/eth_mac_esp_dma.h b/components/esp_eth/include/esp_private/eth_mac_esp_dma.h
index 3fc496534cc..2445379a8e3 100644
--- a/components/esp_eth/include/esp_private/eth_mac_esp_dma.h
+++ b/components/esp_eth/include/esp_private/eth_mac_esp_dma.h
@@ -9,7 +9,9 @@
 extern "C" {
 #endif
 
+#include <stdbool.h>
 #include "esp_err.h"
+#include "esp_eth_mac.h"
 
 /**
  * @brief Indicate to ::emac_esp_dma_receive_frame that receive frame buffer was allocated by ::emac_esp_dma_alloc_recv_buf
@@ -31,6 +33,15 @@ typedef struct emac_esp_dma_t *emac_esp_dma_handle_t;
  */
 typedef struct emac_esp_dma_config_t emac_esp_dma_config_t;
 
+/**
+ * @brief Supplementary properties for the ESP EMAC DMA transmit buffer
+ *
+ */
+typedef struct {
+    uint8_t* buf;
+    uint32_t size;
+} emac_esp_dma_transmit_buff_t;
+
 /**
  * @brief Reset DMA
  * @note This function should be called prior each EMAC start
@@ -49,22 +60,23 @@ void emac_esp_dma_reset(emac_esp_dma_handle_t emac_esp_dma);
  *         zero on fail
  */
 uint32_t emac_esp_dma_transmit_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t *buf, uint32_t length);
-
 /**
- * @brief Transmit data from multiple buffers over EMAC in single Ethernet frame. Data will be joint into
- *        single frame in order in which the buffers are stored in input array.
+ * @brief Extended version of Transmit data function. It is capable to transmit from multiple buffers to appear as single Ethernet frame.
+ *        The function also provides hardware time stamp of the transmission on supported targets.
+ *
+ * @note Data is joint into single frame in order in which the buffers are stored in input array.
  *
  * @param[in] emac_esp_dma EMAC DMA handle
- * @param[in] buffs array of pointers to buffers to be transmitted
- * @param[in] lengths array of lengths of the buffers
- * @param[in] inbuffs_cnt number of buffers (i.e. input arrays size)
+ * @param[in] buffs_array array of buffers to be transmitted
+ * @param[in] buffs_cnt number of buffers (i.e. buffs array sizes can be 1 to n)
+ * @param[out] ts time stamp at which the frame was transmitted by EMAC. Valid time stamp returned only on supported targets. Pass NULL
+ *                if time stamp is not required.
+ *
  * @return number of transmitted bytes on success
  *         zero on fail
  *
- * @pre @p lengths array must have the same size as @p buffs array and their elements need to be stored in the same
- *      order, i.e. lengths[1] is a length associated with data buffer referenced at buffs[1] position.
  */
-uint32_t emac_esp_dma_transmit_multiple_buf_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t **buffs, uint32_t *lengths, uint32_t buffs_cnt);
+uint32_t emac_esp_dma_transmit_frame_ext(emac_esp_dma_handle_t emac_esp_dma, emac_esp_dma_transmit_buff_t *buffs_array, uint32_t buffs_cnt, eth_mac_time_t *ts);
 
 /**
  * @brief Allocate buffer with size equal to actually received Ethernet frame size.
@@ -89,6 +101,8 @@ uint8_t *emac_esp_dma_alloc_recv_buf(emac_esp_dma_handle_t emac_esp_dma, uint32_
  * @param[in] buf buffer into which the Ethernet frame is to be copied
  * @param[in] size buffer size. When buffer was allocated by ::emac_esp_dma_alloc_recv_buf, this parameter needs to be set
  *                 to @c EMAC_DMA_BUF_SIZE_AUTO
+ * @param[out] ts time stamp at which the frame was received by EMAC. Only available on supported targets. Can be NULL
+ *                when time stamp is not required.
  *
  * @return - number of copied bytes when success
  *         - number of bytes of received Ethernet frame when maximum allowed buffer @p size is less than actual size of
@@ -101,7 +115,7 @@ uint8_t *emac_esp_dma_alloc_recv_buf(emac_esp_dma_handle_t emac_esp_dma, uint32_
  *       is less than actual size of received Ethernet frame, the frame will be truncated.
  * @note FCS field is never copied
  */
-uint32_t emac_esp_dma_receive_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t *buf, uint32_t size);
+uint32_t emac_esp_dma_receive_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t *buf, uint32_t size, eth_mac_time_t *ts);
 
 /**
  * @brief Flush frame stored in Rx DMA
@@ -135,6 +149,14 @@ void emac_esp_dma_set_tdes0_ctrl_bits(emac_esp_dma_handle_t emac_esp_dma, uint32
  */
 void emac_esp_dma_clear_tdes0_ctrl_bits(emac_esp_dma_handle_t emac_esp_dma, uint32_t bit_mask);
 
+/**
+ * @brief Enables DMA time stamping feature
+ *
+ * @param[in] emac_esp_dma EMAC DMA handle
+ * @param[in] enable enable when true
+ */
+void emac_esp_dma_ts_enable(emac_esp_dma_handle_t emac_esp_dma, bool enable);
+
 /**
  * @brief Creates a new instance of the ESP EMAC DMA
  *
diff --git a/components/esp_eth/linker.lf b/components/esp_eth/linker.lf
index 3bb1d9c54cb..8dcdca709f0 100644
--- a/components/esp_eth/linker.lf
+++ b/components/esp_eth/linker.lf
@@ -3,12 +3,12 @@ archive: libesp_eth.a
 entries:
   if ETH_IRAM_OPTIMIZATION = y:
     esp_eth:esp_eth_transmit (noflash_text)
-    esp_eth:esp_eth_transmit_vargs (noflash_text)
+    esp_eth:esp_eth_transmit_ctrl_vargs (noflash_text)
     esp_eth_mac_esp:emac_esp32_transmit (noflash_text)
-    esp_eth_mac_esp:emac_esp32_transmit_multiple_bufs (noflash_text)
+    esp_eth_mac_esp:emac_esp32_transmit_ctrl_vargs (noflash_text)
     esp_eth_mac_esp:emac_esp32_receive (noflash_text)
     esp_eth_mac_esp:emac_esp32_rx_task (noflash_text)
     esp_eth_mac_esp_dma:emac_esp_dma_transmit_frame (noflash_text)
-    esp_eth_mac_esp_dma:emac_esp_dma_transmit_multiple_buf_frame (noflash_text)
+    esp_eth_mac_esp_dma:emac_esp_dma_transmit_frame_ext (noflash_text)
     esp_eth_mac_esp_dma:emac_esp_dma_alloc_recv_buf (noflash_text)
     esp_eth_mac_esp_dma:emac_esp_dma_receive_frame (noflash_text)
diff --git a/components/esp_eth/src/esp_eth.c b/components/esp_eth/src/esp_eth.c
index d9439ca316b..3f9b63a0671 100644
--- a/components/esp_eth/src/esp_eth.c
+++ b/components/esp_eth/src/esp_eth.c
@@ -58,6 +58,7 @@ typedef struct {
     SemaphoreHandle_t transmit_mutex;
 #endif // CONFIG_ETH_TRANSMIT_MUTEX
     esp_err_t (*stack_input)(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv);
+    esp_err_t (*stack_input_info)(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv, void *info);
     esp_err_t (*on_lowlevel_init_done)(esp_eth_handle_t eth_handle);
     esp_err_t (*on_lowlevel_deinit_done)(esp_eth_handle_t eth_handle);
     esp_err_t (*customized_read_phy_reg)(esp_eth_handle_t eth_handle, uint32_t phy_addr, uint32_t phy_reg, uint32_t *reg_value);
@@ -102,9 +103,28 @@ static esp_err_t eth_stack_input(esp_eth_mediator_t *eth, uint8_t *buffer, uint3
     esp_eth_driver_t *eth_driver = __containerof(eth, esp_eth_driver_t, mediator);
     if (eth_driver->stack_input) {
         return eth_driver->stack_input((esp_eth_handle_t)eth_driver, buffer, length, eth_driver->priv);
+    // try to pass traffic using extended `stack_input_info`. It's for compatibility reasons since older MAC drivers may
+    // still use `stack_input` but higher level API registered extended version.
+    } else if (eth_driver->stack_input_info) {
+        return eth_driver->stack_input_info((esp_eth_handle_t)eth_driver, buffer, length, eth_driver->priv, NULL);
     }
     // No stack input path has been installed, just drop the incoming packets
-    free(buffer);
+    free(buffer); // IDF-11444
+    return ESP_OK;
+}
+
+static esp_err_t eth_stack_input_info(esp_eth_mediator_t *eth, uint8_t *buffer, uint32_t length, void *info)
+{
+    esp_eth_driver_t *eth_driver = __containerof(eth, esp_eth_driver_t, mediator);
+    if (eth_driver->stack_input_info) {
+        return eth_driver->stack_input_info((esp_eth_handle_t)eth_driver, buffer, length, eth_driver->priv, info);
+    // try using simple `stack_input`. It's for compatibility reasons since higher level API may still register original `stack_input`.
+    // Additional frame info is silently lost of course.
+    } else if (eth_driver->stack_input) {
+        return eth_driver->stack_input((esp_eth_handle_t)eth_driver, buffer, length, eth_driver->priv);
+    }
+    // No stack input path has been installed, just drop the incoming packets
+    free(buffer); // IDF-11444
     return ESP_OK;
 }
 
@@ -209,6 +229,7 @@ esp_err_t esp_eth_driver_install(const esp_eth_config_t *config, esp_eth_handle_
     eth_driver->duplex = ETH_DUPLEX_HALF;
     eth_driver->speed = ETH_SPEED_10M;
     eth_driver->stack_input = config->stack_input;
+    eth_driver->stack_input_info = config->stack_input_info;
     eth_driver->on_lowlevel_init_done = config->on_lowlevel_init_done;
     eth_driver->on_lowlevel_deinit_done = config->on_lowlevel_deinit_done;
     eth_driver->check_link_period_ms = config->check_link_period_ms;
@@ -217,6 +238,7 @@ esp_err_t esp_eth_driver_install(const esp_eth_config_t *config, esp_eth_handle_
     eth_driver->mediator.phy_reg_read = eth_phy_reg_read;
     eth_driver->mediator.phy_reg_write = eth_phy_reg_write;
     eth_driver->mediator.stack_input = eth_stack_input;
+    eth_driver->mediator.stack_input_info = eth_stack_input_info;
     eth_driver->mediator.on_state_changed = eth_on_state_changed;
     // set mediator for both mac and phy object, so that mac and phy are connected to each other via mediator
     mac->set_mediator(mac, &eth_driver->mediator);
@@ -331,11 +353,27 @@ esp_err_t esp_eth_update_input_path(
     esp_eth_driver_t *eth_driver = (esp_eth_driver_t *)hdl;
     ESP_GOTO_ON_FALSE(eth_driver, ESP_ERR_INVALID_ARG, err, TAG, "ethernet driver handle can't be null");
     eth_driver->priv = priv;
+    eth_driver->stack_input_info = NULL;
     eth_driver->stack_input = stack_input;
 err:
     return ret;
 }
 
+esp_err_t esp_eth_update_input_path_info(
+    esp_eth_handle_t hdl,
+    esp_err_t (*stack_input_info)(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t length, void *priv, void *info),
+    void *priv)
+{
+    esp_err_t ret = ESP_OK;
+    esp_eth_driver_t *eth_driver = (esp_eth_driver_t *)hdl;
+    ESP_GOTO_ON_FALSE(eth_driver, ESP_ERR_INVALID_ARG, err, TAG, "ethernet driver handle can't be null");
+    eth_driver->priv = priv;
+    eth_driver->stack_input = NULL;
+    eth_driver->stack_input_info = stack_input_info;
+err:
+    return ret;
+}
+
 esp_err_t esp_eth_transmit(esp_eth_handle_t hdl, void *buf, size_t length)
 {
     esp_err_t ret = ESP_OK;
@@ -365,7 +403,7 @@ esp_err_t esp_eth_transmit(esp_eth_handle_t hdl, void *buf, size_t length)
     return ret;
 }
 
-esp_err_t esp_eth_transmit_vargs(esp_eth_handle_t hdl, uint32_t argc, ...)
+esp_err_t esp_eth_transmit_ctrl_vargs(esp_eth_handle_t hdl, void *ctrl, uint32_t argc, ...)
 {
     esp_err_t ret = ESP_OK;
     esp_eth_driver_t *eth_driver = (esp_eth_driver_t *)hdl;
@@ -384,7 +422,7 @@ esp_err_t esp_eth_transmit_vargs(esp_eth_handle_t hdl, uint32_t argc, ...)
     }
 #endif // CONFIG_ETH_TRANSMIT_MUTEX
     va_start(args, argc);
-    ret = mac->transmit_vargs(mac, argc, args);
+    ret = mac->transmit_ctrl_vargs(mac, ctrl, argc, args);
 #if CONFIG_ETH_TRANSMIT_MUTEX
     xSemaphoreGive(eth_driver->transmit_mutex);
 #endif // CONFIG_ETH_TRANSMIT_MUTEX
diff --git a/components/esp_eth/src/esp_eth_netif_glue.c b/components/esp_eth/src/esp_eth_netif_glue.c
index f3bc3600505..7fa38b29c49 100644
--- a/components/esp_eth/src/esp_eth_netif_glue.c
+++ b/components/esp_eth/src/esp_eth_netif_glue.c
@@ -29,11 +29,11 @@ struct esp_eth_netif_glue_t {
     esp_event_handler_instance_t get_ip_ctx_handler;
 };
 
-static esp_err_t eth_input_to_netif(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv)
+static esp_err_t eth_input_to_netif(esp_eth_handle_t eth_handle, uint8_t *buffer, uint32_t length, void *priv, void *info)
 {
 #if CONFIG_ESP_NETIF_L2_TAP
     esp_err_t ret = ESP_OK;
-    ret = esp_vfs_l2tap_eth_filter(eth_handle, buffer, (size_t *)&length);
+    ret = esp_vfs_l2tap_eth_filter_frame(eth_handle, buffer, (size_t *)&length, info);
     if (length == 0) {
         return ret;
     }
@@ -52,7 +52,7 @@ static esp_err_t esp_eth_post_attach(esp_netif_t *esp_netif, void *args)
     esp_eth_netif_glue_t *netif_glue = (esp_eth_netif_glue_t *)args;
     netif_glue->base.netif = esp_netif;
 
-    esp_eth_update_input_path(netif_glue->eth_driver, eth_input_to_netif, esp_netif);
+    esp_eth_update_input_path_info(netif_glue->eth_driver, eth_input_to_netif, esp_netif);
 
     // set driver related config to esp-netif
     esp_netif_driver_ifconfig_t driver_ifconfig = {
diff --git a/components/esp_eth/src/mac/esp_eth_mac_esp.c b/components/esp_eth/src/mac/esp_eth_mac_esp.c
index 14bfec2f63f..f2ecfdedf4d 100644
--- a/components/esp_eth/src/mac/esp_eth_mac_esp.c
+++ b/components/esp_eth/src/mac/esp_eth_mac_esp.c
@@ -66,7 +66,6 @@ typedef struct {
     uint32_t flow_control_high_water_mark;
     uint32_t flow_control_low_water_mark;
     uint8_t addr[ETH_ADDR_LEN];
-    bool isr_need_yield;
     bool flow_ctrl_enabled; // indicates whether the user want to do flow control
     bool do_flow_ctrl;  // indicates whether we need to do software flow control
     bool use_pll;  // Only use (A/M)PLL in EMAC_DATA_INTERFACE_RMII && EMAC_CLK_OUT
@@ -79,6 +78,9 @@ typedef struct {
 #ifdef CONFIG_IDF_TARGET_ESP32
     esp_clock_output_mapping_handle_t rmii_clk_hdl; // we use the esp_clock_output driver to output a pre-configured APLL clock as the RMII reference clock
 #endif
+#ifdef SOC_EMAC_IEEE1588V2_SUPPORTED
+    ts_target_exceed_cb_from_isr_t ts_target_exceed_cb_from_isr;
+#endif
 } emac_esp32_t;
 
 static esp_err_t emac_esp_alloc_driver_obj(const eth_mac_config_t *config, emac_esp32_t **emac_out_hdl);
@@ -167,15 +169,12 @@ static esp_err_t emac_esp32_get_addr(esp_eth_mac_t *mac, uint8_t *addr)
 static esp_err_t emac_esp32_set_link(esp_eth_mac_t *mac, eth_link_t link)
 {
     esp_err_t ret = ESP_OK;
-    emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
     switch (link) {
     case ETH_LINK_UP:
-        ESP_GOTO_ON_ERROR(esp_intr_enable(emac->intr_hdl), err, TAG, "enable interrupt failed");
         emac_esp32_start(mac);
         ESP_LOGD(TAG, "emac started");
         break;
     case ETH_LINK_DOWN:
-        ESP_GOTO_ON_ERROR(esp_intr_disable(emac->intr_hdl), err, TAG, "disable interrupt failed");
         emac_esp32_stop(mac);
         ESP_LOGD(TAG, "emac stopped");
         break;
@@ -260,9 +259,78 @@ esp_err_t emac_esp_custom_ioctl(esp_eth_mac_t *mac, int cmd, void *data)
 {
     emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
 
-    switch (cmd) {
+    switch (cmd)
+    {
+#ifdef SOC_EMAC_IEEE1588V2_SUPPORTED
+    case ETH_MAC_ESP_CMD_PTP_ENABLE: {
+        ESP_RETURN_ON_FALSE(data, ESP_ERR_INVALID_ARG, TAG, "PTP enable invalid argument, cant' be NULL");
+        bool enable = *((bool *)data);
+        if (enable) {
+            EMAC_IF_RCC_ATOMIC() {
+                emac_hal_clock_enable_ptp(&emac->hal, EMAC_PTP_CLK_SRC_XTAL, true);
+            }
+            emac_hal_ptp_config_t ptp_config = {
+                .upd_method = ETH_PTP_UPDATE_METHOD_FINE,
+                .roll = ETH_PTP_DIGITAL_ROLLOVER,
+                .ptp_clk_src_period_ns = 25,  // = 1 / 40MHz
+                .ptp_req_accuracy_ns = 40     // required accuracy (must be worse than ptp_ref_clk)
+            };
+            ESP_RETURN_ON_ERROR(emac_hal_ptp_start(&emac->hal, &ptp_config), TAG, "failed to start PTP module");
+            emac_esp_dma_ts_enable(emac->emac_dma_hndl, true);
+        } else {
+            ESP_RETURN_ON_ERROR(emac_hal_ptp_stop(&emac->hal), TAG, "failed to stop PTP module");
+            emac_esp_dma_ts_enable(emac->emac_dma_hndl, false);
+            EMAC_IF_RCC_ATOMIC() {
+                emac_hal_clock_enable_ptp(&emac->hal, 0, false);
+            }
+        }
+        break;
+    }
+    case ETH_MAC_ESP_CMD_S_PTP_TIME: {
+        ESP_RETURN_ON_FALSE(data, ESP_ERR_INVALID_ARG, TAG, "PTP set time invalid argument, cant' be NULL");
+        eth_mac_time_t *time = (eth_mac_time_t *)data;
+        ESP_RETURN_ON_ERROR(emac_hal_ptp_set_sys_time(&emac->hal, time->seconds, time->nanoseconds), TAG, "failed to set PTP time");
+        break;
+    }
+    case ETH_MAC_ESP_CMD_G_PTP_TIME: {
+        ESP_RETURN_ON_FALSE(data, ESP_ERR_INVALID_ARG, TAG, "PTP get time invalid argument, cant' be NULL");
+        eth_mac_time_t *time = (eth_mac_time_t *)data;
+        ESP_RETURN_ON_ERROR(emac_hal_ptp_get_sys_time(&emac->hal, &time->seconds, &time->nanoseconds), TAG, "failed to get PTP time");
+        break;
+    }
+    case ETH_MAC_ESP_CMD_ADJ_PTP_TIME: {
+        ESP_RETURN_ON_FALSE(data, ESP_ERR_INVALID_ARG, TAG, "PTP adjust time invalid argument, cant' be NULL");
+        int32_t adj_ppb = *((int32_t *)data);
+        ESP_RETURN_ON_ERROR(emac_hal_ptp_adj_inc(&emac->hal, adj_ppb), TAG, "failed to adjust PTP time base");
+        break;
+    }
+    case ETH_MAC_ESP_CMD_ADJ_PTP_FREQ: {
+        ESP_RETURN_ON_FALSE(data, ESP_ERR_INVALID_ARG, TAG, "PTP adjust frequency invalid argument, cant' be NULL");
+        double scale_factor = *((double *)data);
+        ESP_RETURN_ON_ERROR(emac_hal_adj_freq_factor(&emac->hal, scale_factor), TAG, "failed to aject PTP time base by scale factor");
+        break;
+    }
+    case ETH_MAC_ESP_CMD_S_TARGET_CB:
+        ESP_RETURN_ON_FALSE(data, ESP_ERR_INVALID_ARG, TAG, "PTP set target callback function invalid argument, cant' be NULL");
+        emac->ts_target_exceed_cb_from_isr = (ts_target_exceed_cb_from_isr_t)data;
+        break;
+    case ETH_MAC_ESP_CMD_S_TARGET_TIME: {
+        ESP_RETURN_ON_FALSE(data, ESP_ERR_INVALID_ARG, TAG, "PTP set target time invalid argument, cant' be NULL");
+        eth_mac_time_t *start_time = (eth_mac_time_t *)data;
+        ESP_RETURN_ON_ERROR(emac_hal_ptp_set_target_time(&emac->hal, start_time->seconds, start_time->nanoseconds), TAG,
+                            "failed to set PTP target time");
+        break;
+    }
+#else
     case ETH_MAC_ESP_CMD_PTP_ENABLE:
+    case ETH_MAC_ESP_CMD_S_PTP_TIME:
+    case ETH_MAC_ESP_CMD_G_PTP_TIME:
+    case ETH_MAC_ESP_CMD_ADJ_PTP_TIME:
+    case ETH_MAC_ESP_CMD_ADJ_PTP_FREQ:
+    case ETH_MAC_ESP_CMD_S_TARGET_CB:
+    case ETH_MAC_ESP_CMD_S_TARGET_TIME:
         return ESP_ERR_NOT_SUPPORTED;
+#endif
     case ETH_MAC_ESP_CMD_SET_TDES0_CFG_BITS:
         ESP_RETURN_ON_FALSE(data != NULL, ESP_ERR_INVALID_ARG, TAG, "cannot set DMA tx desc flag to null");
         emac_esp_dma_set_tdes0_ctrl_bits(emac->emac_dma_hndl, *(uint32_t *)data);
@@ -288,23 +356,28 @@ static esp_err_t emac_esp32_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t
     return ESP_OK;
 }
 
-static esp_err_t emac_esp32_transmit_multiple_bufs(esp_eth_mac_t *mac, uint32_t argc, va_list args)
+static esp_err_t emac_esp32_transmit_ctrl_vargs(esp_eth_mac_t *mac, void *ctrl, uint32_t argc, va_list args)
 {
-    esp_err_t ret = ESP_OK;
     emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
-    uint8_t *bufs[argc];
-    uint32_t len[argc];
+    uint32_t buf_num = argc / 2;
+
+    emac_esp_dma_transmit_buff_t buff_array[buf_num];
+
     uint32_t exp_len = 0;
-    for (int i = 0; i < argc; i++) {
-        bufs[i] = va_arg(args, uint8_t *);
-        len[i] = va_arg(args, uint32_t);
-        exp_len += len[i];
+    for (int i = 0; i < buf_num; i++) {
+        buff_array[i].buf = va_arg(args, uint8_t *);
+        buff_array[i].size = va_arg(args, uint32_t);
+        exp_len += buff_array[i].size;
+    }
+
+    eth_mac_time_t *ts = (eth_mac_time_t *)ctrl;
+    uint32_t sent_len = emac_esp_dma_transmit_frame_ext(emac->emac_dma_hndl, buff_array, buf_num, ts);
+
+    if(sent_len != exp_len) {
+        ESP_LOGD(TAG, "insufficient TX buffer size");
+        return ESP_ERR_NO_MEM;
     }
-    uint32_t sent_len = emac_esp_dma_transmit_multiple_buf_frame(emac->emac_dma_hndl, bufs, len, argc);
-    ESP_GOTO_ON_FALSE(sent_len == exp_len, ESP_ERR_INVALID_SIZE, err, TAG, "insufficient TX buffer size");
     return ESP_OK;
-err:
-    return ret;
 }
 
 static esp_err_t emac_esp32_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t *length)
@@ -313,7 +386,7 @@ static esp_err_t emac_esp32_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t *
     uint32_t expected_len = *length;
     emac_esp32_t *emac = __containerof(mac, emac_esp32_t, parent);
     ESP_GOTO_ON_FALSE(buf && length, ESP_ERR_INVALID_ARG, err, TAG, "can't set buf and length to null");
-    uint32_t receive_len = emac_esp_dma_receive_frame(emac->emac_dma_hndl, buf, expected_len);
+    uint32_t receive_len = emac_esp_dma_receive_frame(emac->emac_dma_hndl, buf, expected_len, NULL);
     emac_esp_dma_get_remain_frames(emac->emac_dma_hndl, &emac->frames_remain, &emac->free_rx_descriptor);
     /* we need to check the return value in case the buffer size is not enough */
     ESP_GOTO_ON_FALSE(expected_len >= receive_len, ESP_ERR_INVALID_SIZE, err, TAG, "received buffer longer than expected");
@@ -337,23 +410,29 @@ static void emac_esp32_rx_task(void *arg)
             buffer = emac_esp_dma_alloc_recv_buf(emac->emac_dma_hndl, &frame_len);
             /* we have memory to receive the frame of maximal size previously defined */
             if (buffer != NULL) {
-                uint32_t recv_len = emac_esp_dma_receive_frame(emac->emac_dma_hndl, buffer, EMAC_DMA_BUF_SIZE_AUTO);
+#ifdef SOC_EMAC_IEEE1588V2_SUPPORTED
+                eth_mac_time_t ts;
+                eth_mac_time_t *p_ts = &ts;
+#else
+                eth_mac_time_t *p_ts = NULL;
+#endif
+                uint32_t recv_len = emac_esp_dma_receive_frame(emac->emac_dma_hndl, buffer, EMAC_DMA_BUF_SIZE_AUTO, p_ts);
                 if (recv_len == 0) {
                     ESP_LOGE(TAG, "frame copy error");
                     free(buffer);
-                    /* ensure that interface to EMAC does not get stuck with unprocessed frames */
+                    /* ensures that interface to EMAC does not get stuck with unprocessed frames */
                     emac_esp_dma_flush_recv_frame(emac->emac_dma_hndl);
                 } else if (frame_len > recv_len) {
                     ESP_LOGE(TAG, "received frame was truncated");
                     free(buffer);
                 } else {
                     ESP_LOGD(TAG, "receive len= %" PRIu32, recv_len);
-                    emac->eth->stack_input(emac->eth, buffer, recv_len);
+                    emac->eth->stack_input_info(emac->eth, buffer, recv_len, (void *)p_ts);
                 }
-                /* if allocation failed and there is a waiting frame */
+            /* if allocation failed and there is a waiting frame */
             } else if (frame_len) {
                 ESP_LOGE(TAG, "no mem for receive buffer");
-                /* ensure that interface to EMAC does not get stuck with unprocessed frames */
+                /* ensures that interface to EMAC does not get stuck with unprocessed frames */
                 emac_esp_dma_flush_recv_frame(emac->emac_dma_hndl);
             }
             emac_esp_dma_get_remain_frames(emac->emac_dma_hndl, &emac->frames_remain, &emac->free_rx_descriptor);
@@ -498,18 +577,33 @@ IRAM_ATTR void emac_isr_default_handler(void *args)
     emac_hal_context_t *hal = (emac_hal_context_t *)args;
     uint32_t intr_stat = emac_hal_get_intr_status(hal);
     emac_hal_clear_corresponding_intr(hal, intr_stat);
+    emac_esp32_t *emac = __containerof(hal, emac_esp32_t, hal);
+    bool high_task_woken = false;
+
+#if SOC_EMAC_IEEE1588V2_SUPPORTED && EMAC_LL_CONFIG_ENABLE_MAC_INTR_MASK & EMAC_LL_MAC_INTR_TIME_STAMP_ENABLE
+    if (intr_stat & EMAC_LL_DMA_TIMESTAMP_TRIGGER_INTR) {
+        uint32_t ts_stat = emac_hal_get_ts_status(hal);
+        if (ts_stat & EMAC_LL_TS_TARGET_TIME_REACHED) {
+            if (emac->ts_target_exceed_cb_from_isr) {
+                bool ts_high_task_woken = emac->ts_target_exceed_cb_from_isr(emac->eth, NULL);
+                high_task_woken |= ts_high_task_woken;
+            }
+        }
+    }
+#endif // SOC_EMAC_IEEE1588V2_SUPPORTED
 
 #if EMAC_LL_CONFIG_ENABLE_INTR_MASK & EMAC_LL_INTR_RECEIVE_ENABLE
     if (intr_stat & EMAC_LL_DMA_RECEIVE_FINISH_INTR) {
-        emac_esp32_t *emac = __containerof(hal, emac_esp32_t, hal);
-        BaseType_t high_task_wakeup = pdFALSE;
+        BaseType_t rx_high_task_woken = pdFALSE;
         /* notify receive task */
-        vTaskNotifyGiveFromISR(emac->rx_task_hdl, &high_task_wakeup);
-        if (high_task_wakeup == pdTRUE) {
-            portYIELD_FROM_ISR();
-        }
+        vTaskNotifyGiveFromISR(emac->rx_task_hdl, &rx_high_task_woken);
+        high_task_woken |= (bool)rx_high_task_woken;
+    }
+#endif // EMAC_LL_CONFIG_ENABLE_INTR_MASK & EMAC_LL_INTR_RECEIVE_ENABLE
+
+    if (high_task_woken) {
+        portYIELD_FROM_ISR();
     }
-#endif
 }
 
 static void emac_esp_free_driver_obj(emac_esp32_t *emac)
@@ -684,6 +778,8 @@ esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_esp32_emac_config_t *esp32_config
     ret_code = esp_intr_alloc(ETS_ETH_MAC_INTR_SOURCE, isr_flags,
                               emac_isr_default_handler, &emac->hal, &(emac->intr_hdl));
     ESP_GOTO_ON_FALSE(ret_code == ESP_OK, NULL, err, TAG, "alloc emac interrupt failed");
+    ret_code = esp_intr_enable(emac->intr_hdl);
+    ESP_GOTO_ON_FALSE(ret_code == ESP_OK, NULL, err, TAG, "enable interrupt failed");
 
     /* init GPIO used by SMI interface */
     ret_code = emac_esp_gpio_init_smi(&esp32_config->smi_gpio);
@@ -714,9 +810,12 @@ esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_esp32_emac_config_t *esp32_config
     emac->parent.set_peer_pause_ability = emac_esp32_set_peer_pause_ability;
     emac->parent.enable_flow_ctrl = emac_esp32_enable_flow_ctrl;
     emac->parent.transmit = emac_esp32_transmit;
-    emac->parent.transmit_vargs = emac_esp32_transmit_multiple_bufs;
+    emac->parent.transmit_ctrl_vargs = emac_esp32_transmit_ctrl_vargs;
     emac->parent.receive = emac_esp32_receive;
     emac->parent.custom_ioctl = emac_esp_custom_ioctl;
+#ifdef SOC_EMAC_IEEE1588V2_SUPPORTED
+    emac->ts_target_exceed_cb_from_isr = NULL;
+#endif // SOC_EMAC_IEEE1588V2_SUPPORTED
     return &(emac->parent);
 
 err:
diff --git a/components/esp_eth/src/mac/esp_eth_mac_esp_dma.c b/components/esp_eth/src/mac/esp_eth_mac_esp_dma.c
index 73f5ee40c7c..f8901d6a5a4 100644
--- a/components/esp_eth/src/mac/esp_eth_mac_esp_dma.c
+++ b/components/esp_eth/src/mac/esp_eth_mac_esp_dma.c
@@ -19,6 +19,8 @@
 #define EMAC_TDES0_FS_CTRL_FLAGS_MASK 0x0FCC0000 // modifiable bits mask associated with the First Segment
 #define EMAC_TDES0_LS_CTRL_FLAGS_MASK 0x40000000 // modifiable bits mask associated with the Last Segment
 
+#define PTP_TX_TIMESTAMP_TO 50 //  maximum loops observed on P4 was 31 @ETH frame 1500B
+
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
 #define DMA_CACHE_WB(addr, size) do {                                                           \
     esp_err_t msync_ret = esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_DIR_C2M);    \
@@ -116,6 +118,15 @@ void emac_esp_dma_clear_tdes0_ctrl_bits(emac_esp_dma_handle_t emac_esp_dma, uint
     emac_esp_dma->tx_desc_flags &= ~flag;
 }
 
+void emac_esp_dma_ts_enable(emac_esp_dma_handle_t emac_esp_dma, bool enable)
+{
+    if (enable) {
+        emac_esp_dma_set_tdes0_ctrl_bits(emac_esp_dma, EMAC_HAL_TDES0_TX_TS_ENABLE);
+    } else {
+        emac_esp_dma_clear_tdes0_ctrl_bits(emac_esp_dma, EMAC_HAL_TDES0_TX_TS_ENABLE);
+    }
+}
+
 uint32_t emac_esp_dma_transmit_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t *buf, uint32_t length)
 {
     /* Get the number of Tx buffers to use for the frame */
@@ -183,16 +194,19 @@ uint32_t emac_esp_dma_transmit_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t
     return 0;
 }
 
-uint32_t emac_esp_dma_transmit_multiple_buf_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t **buffs, uint32_t *lengths, uint32_t buffs_cnt)
+uint32_t emac_esp_dma_transmit_frame_ext(emac_esp_dma_handle_t emac_esp_dma, emac_esp_dma_transmit_buff_t *buffs_array, uint32_t buffs_cnt, eth_mac_time_t *ts)
 {
     /* Get the number of Tx buffers to use for the frame */
     uint32_t dma_bufcount = 0;
     uint32_t sentout = 0;
-    uint8_t *ptr = buffs[0];
-    uint32_t lastlen = lengths[0];
     uint32_t avail_len = CONFIG_ETH_DMA_BUFFER_SIZE;
+    uint8_t *ptr = buffs_array->buf;
+    uint32_t lastlen = buffs_array->size;
 
     eth_dma_tx_descriptor_t *desc_iter = emac_esp_dma->tx_desc;
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+    eth_dma_tx_descriptor_t *desc_last = desc_iter;
+#endif
     /* A frame is transmitted in multiple descriptor */
     while (dma_bufcount < CONFIG_ETH_DMA_TX_BUFFER_NUM) {
         DMA_CACHE_INVALIDATE(desc_iter, EMAC_HAL_DMA_DESC_SIZE);
@@ -222,8 +236,9 @@ uint32_t emac_esp_dma_transmit_multiple_buf_frame(emac_esp_dma_handle_t emac_esp
 
                 /* Update processed input buffers info */
                 buffs_cnt--;
-                ptr = *(++buffs);
-                lastlen = *(++lengths);
+                buffs_array++;
+                ptr = buffs_array->buf;
+                lastlen = buffs_array->size;
                 /* There is only limited available space in the current descriptor, use it all */
             } else {
                 /* copy data from uplayer stack buffer */
@@ -237,8 +252,9 @@ uint32_t emac_esp_dma_transmit_multiple_buf_frame(emac_esp_dma_handle_t emac_esp
                 } else {
                     /* Update processed input buffers info */
                     buffs_cnt--;
-                    ptr = *(++buffs);
-                    lastlen = *(++lengths);
+                    buffs_array++;
+                    ptr = buffs_array->buf;
+                    lastlen = buffs_array->size;
                 }
                 avail_len = CONFIG_ETH_DMA_BUFFER_SIZE;
                 desc_iter->TDES1.TransmitBuffer1Size = CONFIG_ETH_DMA_BUFFER_SIZE;
@@ -255,6 +271,9 @@ uint32_t emac_esp_dma_transmit_multiple_buf_frame(emac_esp_dma_handle_t emac_esp
             /* Setting the last segment bit */
             desc_iter->TDES0.LastSegment = 1;
             desc_iter->TDES0.Value |= emac_esp_dma->tx_desc_flags & EMAC_TDES0_LS_CTRL_FLAGS_MASK;
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+            desc_last = desc_iter;
+#endif
             break;
         }
 
@@ -270,6 +289,23 @@ uint32_t emac_esp_dma_transmit_multiple_buf_frame(emac_esp_dma_handle_t emac_esp
     }
 
     emac_hal_transmit_poll_demand(&emac_esp_dma->hal);
+
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+    if (ts != NULL) {
+        uint32_t timeout = 0;
+        do {
+            timeout++;
+            DMA_CACHE_INVALIDATE(desc_last, EMAC_HAL_DMA_DESC_SIZE);
+        } while (emac_hal_get_txdesc_timestamp(&emac_esp_dma->hal, desc_last, &ts->seconds, &ts->nanoseconds) == ESP_ERR_INVALID_STATE &&
+                 timeout < PTP_TX_TIMESTAMP_TO);
+        if (timeout >= PTP_TX_TIMESTAMP_TO) {
+            /* zeros indicate invalid time stamp since it is not possible to ever get "zero time" under normal conditions */
+            ts->seconds = 0;
+            ts->nanoseconds = 0;
+        }
+    }
+#endif
+
     return sentout;
 err:
     return 0;
@@ -360,7 +396,7 @@ uint8_t *emac_esp_dma_alloc_recv_buf(emac_esp_dma_handle_t emac_esp_dma, uint32_
     return buf;
 }
 
-uint32_t emac_esp_dma_receive_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t *buf, uint32_t size)
+uint32_t emac_esp_dma_receive_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t *buf, uint32_t size, eth_mac_time_t *ts)
 {
     uint32_t ret_len = 0;
     uint32_t copy_len = 0;
@@ -395,14 +431,25 @@ uint32_t emac_esp_dma_receive_frame(emac_esp_dma_handle_t emac_esp_dma, uint8_t
         }
         DMA_CACHE_INVALIDATE(desc_iter->Buffer1Addr, CONFIG_ETH_DMA_BUFFER_SIZE);
         memcpy(buf, (void *)(desc_iter->Buffer1Addr), copy_len);
-        desc_iter->RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
-        DMA_CACHE_WB(desc_iter, EMAC_HAL_DMA_DESC_SIZE);
         /* `copy_len` does not include CRC (which may be stored in separate buffer), hence check if we reached the last descriptor */
         while (!desc_iter->RDES0.LastDescriptor) {
-            desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
             desc_iter->RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
             DMA_CACHE_WB(desc_iter, EMAC_HAL_DMA_DESC_SIZE);
+            desc_iter = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
         }
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+        if (ts != NULL) {
+            if (emac_hal_get_rxdesc_timestamp(&emac_esp_dma->hal, desc_iter, &ts->seconds, &ts->nanoseconds) != ESP_OK) {
+                /* zeros indicate invalid time stamp since it is not possible to ever get "zero time" under normal conditions */
+                ts->seconds = 0;
+                ts->nanoseconds = 0;
+            }
+        }
+#endif
+        /* return last descriptor to DMA */
+        desc_iter->RDES0.Own = EMAC_LL_DMADESC_OWNER_DMA;
+        DMA_CACHE_WB(desc_iter, EMAC_HAL_DMA_DESC_SIZE);
+
         /* update rxdesc */
         emac_esp_dma->rx_desc = (eth_dma_rx_descriptor_t *)(desc_iter->Buffer2NextDescAddr);
         /* poll rx demand */
diff --git a/components/esp_eth/src/phy/esp_eth_phy_802_3.c b/components/esp_eth/src/phy/esp_eth_phy_802_3.c
index f120821187f..b0c22cb53f4 100644
--- a/components/esp_eth/src/phy/esp_eth_phy_802_3.c
+++ b/components/esp_eth/src/phy/esp_eth_phy_802_3.c
@@ -16,11 +16,14 @@
 #include "esp_rom_sys.h"
 #include "esp_eth_phy_802_3.h"
 
-// Default reset assertion time is selected to be 100us as it is most commonly used value among PHY chips.
+// Default reset assertion time is selected to be 100us as it is most commonly used value among ESP-IDF supported PHY chips.
 #define PHY_RESET_ASSERTION_TIME_US 100
 
 static const char *TAG = "eth_phy_802_3";
 
+// TODO: IDF-11362 (should be renamed to esp_eth_phy_802_3_reset_hw with the next major release)
+static esp_err_t esp_eth_phy_802_3_reset_hw_internal(phy_802_3_t *phy_802_3);
+
 static esp_err_t set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
 {
     phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
@@ -33,10 +36,10 @@ static esp_err_t reset(esp_eth_phy_t *phy)
     return esp_eth_phy_802_3_reset(phy_802_3);
 }
 
-static esp_err_t reset_hw_default(esp_eth_phy_t *phy)
+static esp_err_t reset_hw(esp_eth_phy_t *phy)
 {
     phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
-    return esp_eth_phy_802_3_reset_hw(phy_802_3, PHY_RESET_ASSERTION_TIME_US);
+    return esp_eth_phy_802_3_reset_hw_internal(phy_802_3);
 }
 
 static esp_err_t autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
@@ -93,6 +96,14 @@ static esp_err_t set_link(esp_eth_phy_t *phy, eth_link_t link)
     return esp_eth_phy_802_3_set_link(phy_802_3, link);
 }
 
+static esp_err_t get_link(esp_eth_phy_t *phy)
+{
+    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
+
+    /* Update information about link, speed, duplex */
+    return esp_eth_phy_802_3_updt_link_dup_spd(phy_802_3);
+}
+
 static esp_err_t init(esp_eth_phy_t *phy)
 {
     phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
@@ -143,21 +154,6 @@ esp_err_t esp_eth_phy_802_3_reset(phy_802_3_t *phy_802_3)
     return ret;
 }
 
-/**
- * @brief PHY hardware reset with default assert time
- *
- * @note Default reset assertion time is selected to be 100us as it is most commonly used value among PHY chips.
- *       If your PHY chip requires different value, redefine the `reset_hw` function in derived PHY specific driver structure.
- *
- * @param phy Ethernet PHY instance
- * @return
- *         - ESP_OK on success
- */
-esp_err_t esp_eth_phy_802_3_reset_hw_default(phy_802_3_t *phy_802_3)
-{
-    return esp_eth_phy_802_3_reset_hw(phy_802_3, PHY_RESET_ASSERTION_TIME_US);
-}
-
 esp_err_t esp_eth_phy_802_3_autonego_ctrl(phy_802_3_t *phy_802_3, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
 {
     esp_err_t ret = ESP_OK;
@@ -220,6 +216,67 @@ esp_err_t esp_eth_phy_802_3_autonego_ctrl(phy_802_3_t *phy_802_3, eth_phy_autone
     return ret;
 }
 
+esp_err_t esp_eth_phy_802_3_updt_link_dup_spd(phy_802_3_t *phy_802_3)
+{
+    esp_err_t ret = ESP_OK;
+    esp_eth_mediator_t *eth = phy_802_3->eth;
+    uint32_t addr = phy_802_3->addr;
+    eth_speed_t speed = ETH_SPEED_10M;
+    eth_duplex_t duplex = ETH_DUPLEX_HALF;
+    uint32_t peer_pause_ability = false;
+    bmcr_reg_t bmcr;
+    bmsr_reg_t bmsr;
+    anar_reg_t anar;
+    anlpar_reg_t anlpar;
+
+    ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
+    eth_link_t link = bmsr.link_status ? ETH_LINK_UP : ETH_LINK_DOWN;
+    /* check if link status changed */
+    if (phy_802_3->link_status != link) {
+        /* when link up, read negotiation result */
+        if (link == ETH_LINK_UP) {
+            ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
+            ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANAR_REG_ADDR, &(anar.val)), err, TAG, "read ANAR failed");
+            ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
+            if (bmcr.en_auto_nego) {
+                if (anar.base100_tx_fd && anlpar.base100_tx_fd) {
+                    speed = ETH_SPEED_100M;
+                    duplex = ETH_DUPLEX_FULL;
+                } else if (anar.base100_tx && anlpar.base100_tx) {
+                    speed = ETH_SPEED_100M;
+                    duplex = ETH_DUPLEX_HALF;
+                } else if (anar.base10_t_fd && anlpar.base10_t_fd) {
+                    speed = ETH_SPEED_10M;
+                    duplex = ETH_DUPLEX_FULL;
+                } else if (anar.base10_t && anlpar.base10_t) {
+                    speed = ETH_SPEED_10M;
+                    duplex = ETH_DUPLEX_HALF;
+                } else {
+                    ESP_GOTO_ON_FALSE(false, ESP_FAIL, err, TAG, "invalid auto-nego speed/duplex advertising");
+                }
+            } else {
+                speed = bmcr.speed_select ? ETH_SPEED_100M : ETH_SPEED_10M;
+                duplex = bmcr.duplex_mode ? ETH_DUPLEX_FULL : ETH_DUPLEX_HALF;
+            }
+
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
+            /* if we're in duplex mode, and peer has the flow control ability */
+            if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
+                peer_pause_ability = 1;
+            } else {
+                peer_pause_ability = 0;
+            }
+            ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
+        }
+        ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "change link failed");
+        phy_802_3->link_status = link;
+    }
+    return ESP_OK;
+err:
+    return ret;
+}
+
 esp_err_t esp_eth_phy_802_3_pwrctl(phy_802_3_t *phy_802_3, bool enable)
 {
     esp_err_t ret = ESP_OK;
@@ -392,8 +449,28 @@ esp_err_t esp_eth_phy_802_3_reset_hw(phy_802_3_t *phy_802_3, uint32_t reset_asse
             vTaskDelay(pdMS_TO_TICKS(reset_assert_us/1000));
         }
         gpio_set_level(phy_802_3->reset_gpio_num, 1);
+        return ESP_OK;
     }
-    return ESP_OK;
+    return ESP_ERR_NOT_ALLOWED;
+}
+
+/**
+ * @brief Hardware reset with internal timing configuration defined during initialization
+ *
+ * @param phy_802_3 IEEE 802.3 PHY object infostructure
+ * @return
+ *      - ESP_OK: reset Ethernet PHY successfully
+ *      - ESP_ERR_NOT_ALLOWED: reset GPIO not defined
+ */
+static esp_err_t esp_eth_phy_802_3_reset_hw_internal(phy_802_3_t *phy_802_3)
+{
+    esp_err_t ret = ESP_OK;
+    if ((ret = esp_eth_phy_802_3_reset_hw(phy_802_3, phy_802_3->hw_reset_assert_time_us)) == ESP_OK) {
+        if (phy_802_3->post_hw_reset_delay_ms > 0) {
+            vTaskDelay(pdMS_TO_TICKS(phy_802_3->post_hw_reset_delay_ms));
+        }
+    }
+    return ret;
 }
 
 esp_err_t esp_eth_phy_802_3_detect_phy_addr(esp_eth_mediator_t *eth, int *detected_addr)
@@ -601,9 +678,19 @@ esp_err_t esp_eth_phy_802_3_obj_config_init(phy_802_3_t *phy_802_3, const eth_ph
     phy_802_3->reset_timeout_ms = config->reset_timeout_ms;
     phy_802_3->reset_gpio_num = config->reset_gpio_num;
     phy_802_3->autonego_timeout_ms = config->autonego_timeout_ms;
+    if (config->hw_reset_assert_time_us > 0) {
+        phy_802_3->hw_reset_assert_time_us = config->hw_reset_assert_time_us;
+    } else {
+        phy_802_3->hw_reset_assert_time_us = PHY_RESET_ASSERTION_TIME_US;
+    }
+    if (config->post_hw_reset_delay_ms > 0) {
+        phy_802_3->post_hw_reset_delay_ms = config->post_hw_reset_delay_ms;
+    } else {
+        phy_802_3->post_hw_reset_delay_ms = ESP_ETH_NO_POST_HW_RESET_DELAY;
+    }
 
     phy_802_3->parent.reset = reset;
-    phy_802_3->parent.reset_hw = reset_hw_default;
+    phy_802_3->parent.reset_hw = reset_hw;
     phy_802_3->parent.init = init;
     phy_802_3->parent.deinit = deinit;
     phy_802_3->parent.set_mediator = set_mediator;
@@ -617,7 +704,7 @@ esp_err_t esp_eth_phy_802_3_obj_config_init(phy_802_3_t *phy_802_3, const eth_ph
     phy_802_3->parent.set_duplex = set_duplex;
     phy_802_3->parent.del = del;
     phy_802_3->parent.set_link = set_link;
-    phy_802_3->parent.get_link = NULL;
+    phy_802_3->parent.get_link = get_link;
     phy_802_3->parent.custom_ioctl = NULL;
 
 err:
diff --git a/components/esp_eth/src/phy/esp_eth_phy_generic.c b/components/esp_eth/src/phy/esp_eth_phy_generic.c
new file mode 100644
index 00000000000..0003758bf86
--- /dev/null
+++ b/components/esp_eth/src/phy/esp_eth_phy_generic.c
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include "esp_log.h"
+#include "esp_check.h"
+#include "esp_eth.h"
+#include "esp_eth_phy_802_3.h"
+
+static const char *TAG = "eth_phy_generic";
+
+// Default reset timing is intentionally conservative
+#define DEFAULT_PHY_GENERIC_RESET_ASSERTION_TIME_US 10000
+#define DEFAULT_PHY_GENERIC_POST_RESET_DELAY_MS     500
+
+esp_eth_phy_t *esp_eth_phy_new_generic(const eth_phy_config_t *config)
+{
+    esp_eth_phy_t *ret = NULL;
+    phy_802_3_t *phy_802_3 = calloc(1, sizeof(phy_802_3_t));
+    eth_phy_config_t phy_802_3_config = *config;
+    // default chip specific configuration if not defined by user
+    if (config->hw_reset_assert_time_us == 0) {
+        phy_802_3_config.hw_reset_assert_time_us = DEFAULT_PHY_GENERIC_RESET_ASSERTION_TIME_US;
+    }
+    if (config->post_hw_reset_delay_ms == 0) {
+        phy_802_3_config.post_hw_reset_delay_ms = DEFAULT_PHY_GENERIC_POST_RESET_DELAY_MS;
+    }
+    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(phy_802_3, &phy_802_3_config) == ESP_OK,
+                        NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
+
+    return &phy_802_3->parent;
+err:
+    return ret;
+}
diff --git a/components/esp_eth/src/phy/esp_eth_phy_ip101.c b/components/esp_eth/src/phy/esp_eth_phy_ip101.c
index e66fb78b93e..42fce95b317 100644
--- a/components/esp_eth/src/phy/esp_eth_phy_ip101.c
+++ b/components/esp_eth/src/phy/esp_eth_phy_ip101.c
@@ -173,14 +173,6 @@ static esp_err_t ip101_get_link(esp_eth_phy_t *phy)
     return ret;
 }
 
-static esp_err_t ip101_reset_hw(esp_eth_phy_t *phy)
-{
-    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
-    esp_err_t ret = esp_eth_phy_802_3_reset_hw(phy_802_3, IP101_PHY_RESET_ASSERTION_TIME_US);
-    vTaskDelay(pdMS_TO_TICKS(IP101_PHY_POST_RESET_INIT_TIME_MS));
-    return ret;
-}
-
 static esp_err_t ip101_init(esp_eth_phy_t *phy)
 {
     esp_err_t ret = ESP_OK;
@@ -206,13 +198,20 @@ esp_eth_phy_t *esp_eth_phy_new_ip101(const eth_phy_config_t *config)
     esp_eth_phy_t *ret = NULL;
     phy_ip101_t *ip101 = calloc(1, sizeof(phy_ip101_t));
     ESP_GOTO_ON_FALSE(ip101, NULL, err, TAG, "calloc ip101 failed");
-    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&ip101->phy_802_3, config) == ESP_OK,
+    eth_phy_config_t ip101_config = *config;
+    // default chip specific configuration
+    if (config->hw_reset_assert_time_us == 0) {
+        ip101_config.hw_reset_assert_time_us = IP101_PHY_RESET_ASSERTION_TIME_US;
+    }
+    if (config->post_hw_reset_delay_ms == 0) {
+        ip101_config.post_hw_reset_delay_ms = IP101_PHY_POST_RESET_INIT_TIME_MS;
+    }
+    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&ip101->phy_802_3, &ip101_config) == ESP_OK,
                         NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
 
     // redefine functions which need to be customized for sake of IP101
     ip101->phy_802_3.parent.init = ip101_init;
     ip101->phy_802_3.parent.get_link = ip101_get_link;
-    ip101->phy_802_3.parent.reset_hw = ip101_reset_hw;
 
     return &ip101->phy_802_3.parent;
 err:
diff --git a/components/esp_eth/src/phy/esp_eth_phy_lan87xx.c b/components/esp_eth/src/phy/esp_eth_phy_lan87xx.c
index d6f8e148fd1..1d9f666f9a7 100644
--- a/components/esp_eth/src/phy/esp_eth_phy_lan87xx.c
+++ b/components/esp_eth/src/phy/esp_eth_phy_lan87xx.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,6 +14,9 @@
 
 static const char *TAG = "lan87xx";
 
+/* It was observed that assert nRST signal on LAN87xx needs to be a little longer than the minimum specified in datasheet */
+#define LAN87XX_PHY_RESET_ASSERTION_TIME_US 150
+
 /***************List of Supported Models***************/
 
 // See Microchip's Application Note AN25.3 summarizing differences among below models
@@ -287,12 +290,6 @@ static esp_err_t lan87xx_get_link(esp_eth_phy_t *phy)
     return ret;
 }
 
-static esp_err_t lan87xx_reset_hw(esp_eth_phy_t *phy)
-{
-    /* It was observed that assert nRST signal on LAN87xx needs to be a little longer than the minimum specified in datasheet */
-    return esp_eth_phy_802_3_reset_hw(esp_eth_phy_into_phy_802_3(phy), 150);
-}
-
 static esp_err_t lan87xx_autonego_ctrl(esp_eth_phy_t *phy, eth_phy_autoneg_cmd_t cmd, bool *autonego_en_stat)
 {
     esp_err_t ret = ESP_OK;
@@ -366,11 +363,18 @@ esp_eth_phy_t *esp_eth_phy_new_lan87xx(const eth_phy_config_t *config)
     esp_eth_phy_t *ret = NULL;
     phy_lan87xx_t *lan87xx = calloc(1, sizeof(phy_lan87xx_t));
     ESP_GOTO_ON_FALSE(lan87xx, NULL, err, TAG, "calloc lan87xx failed");
-    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&lan87xx->phy_802_3, config) == ESP_OK,
+    eth_phy_config_t lan87xx_config = *config;
+    // default chip specific configuration
+    if (config->hw_reset_assert_time_us == 0) {
+        lan87xx_config.hw_reset_assert_time_us = LAN87XX_PHY_RESET_ASSERTION_TIME_US;
+    }
+    if (config->post_hw_reset_delay_ms == 0) {
+        lan87xx_config.post_hw_reset_delay_ms = ESP_ETH_NO_POST_HW_RESET_DELAY;
+    }
+    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&lan87xx->phy_802_3, &lan87xx_config) == ESP_OK,
                         NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
 
     // redefine functions which need to be customized for sake of LAN87xx
-    lan87xx->phy_802_3.parent.reset_hw = lan87xx_reset_hw;
     lan87xx->phy_802_3.parent.init = lan87xx_init;
     lan87xx->phy_802_3.parent.get_link = lan87xx_get_link;
     lan87xx->phy_802_3.parent.autonego_ctrl = lan87xx_autonego_ctrl;
diff --git a/components/esp_eth/src/phy/esp_eth_phy_rtl8201.c b/components/esp_eth/src/phy/esp_eth_phy_rtl8201.c
index 4f3a9337b4f..c2bf0900e3a 100644
--- a/components/esp_eth/src/phy/esp_eth_phy_rtl8201.c
+++ b/components/esp_eth/src/phy/esp_eth_phy_rtl8201.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -149,15 +149,6 @@ static esp_err_t rtl8201_loopback(esp_eth_phy_t *phy, bool enable)
     return ret;
 }
 
-static esp_err_t rtl8201_reset_hw(esp_eth_phy_t *phy)
-{
-    phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
-    esp_err_t ret = esp_eth_phy_802_3_reset_hw(phy_802_3, RTL8201_PHY_RESET_ASSERTION_TIME_US);
-    vTaskDelay(pdMS_TO_TICKS(RTL8201_PHY_POST_RESET_INIT_TIME_MS));
-    return ret;
-}
-
-
 static esp_err_t rtl8201_init(esp_eth_phy_t *phy)
 {
     esp_err_t ret = ESP_OK;
@@ -183,7 +174,15 @@ esp_eth_phy_t *esp_eth_phy_new_rtl8201(const eth_phy_config_t *config)
     esp_eth_phy_t *ret = NULL;
     phy_rtl8201_t *rtl8201 = calloc(1, sizeof(phy_rtl8201_t));
     ESP_GOTO_ON_FALSE(rtl8201, NULL, err, TAG, "calloc rtl8201 failed");
-    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&rtl8201->phy_802_3, config) == ESP_OK,
+    eth_phy_config_t rtl8201_config = *config;
+    // default chip specific configuration
+    if (config->hw_reset_assert_time_us == 0) {
+        rtl8201_config.hw_reset_assert_time_us = RTL8201_PHY_RESET_ASSERTION_TIME_US;
+    }
+    if (config->post_hw_reset_delay_ms == 0) {
+        rtl8201_config.post_hw_reset_delay_ms = RTL8201_PHY_POST_RESET_INIT_TIME_MS;
+    }
+    ESP_GOTO_ON_FALSE(esp_eth_phy_802_3_obj_config_init(&rtl8201->phy_802_3, &rtl8201_config) == ESP_OK,
                         NULL, err, TAG, "configuration initialization of PHY 802.3 failed");
 
     // redefine functions which need to be customized for sake of RTL8201
@@ -191,7 +190,6 @@ esp_eth_phy_t *esp_eth_phy_new_rtl8201(const eth_phy_config_t *config)
     rtl8201->phy_802_3.parent.get_link = rtl8201_get_link;
     rtl8201->phy_802_3.parent.autonego_ctrl = rtl8201_autonego_ctrl;
     rtl8201->phy_802_3.parent.loopback = rtl8201_loopback;
-    rtl8201->phy_802_3.parent.reset_hw = rtl8201_reset_hw;
 
     return &rtl8201->phy_802_3.parent;
 err:
diff --git a/components/esp_eth/test_apps/main/esp_eth_test_esp_emac.c b/components/esp_eth/test_apps/main/esp_eth_test_esp_emac.c
index 5056c864825..518efe06024 100644
--- a/components/esp_eth/test_apps/main/esp_eth_test_esp_emac.c
+++ b/components/esp_eth/test_apps/main/esp_eth_test_esp_emac.c
@@ -5,6 +5,7 @@
  */
 #include <string.h>
 #include <inttypes.h>
+#include "time.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/event_groups.h"
 #include "esp_log.h"
@@ -29,7 +30,7 @@ typedef struct
     uint16_t expected_size_3;
 } recv_esp_emac_check_info_t;
 
-static esp_err_t eth_recv_esp_emac_check_cb(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t length, void *priv)
+static esp_err_t eth_recv_esp_emac_check_cb(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t length, void *priv, void *info)
 {
     emac_frame_t *pkt = (emac_frame_t *)buffer;
     recv_esp_emac_check_info_t *recv_info = (recv_esp_emac_check_info_t *)priv;
@@ -107,7 +108,7 @@ TEST_CASE("internal emac receive/transmit", "[esp_emac]")
     bool loopback_en = true;
     esp_eth_ioctl(eth_handle, ETH_CMD_S_PHY_LOOPBACK, &loopback_en);
 
-    TEST_ESP_OK(esp_eth_update_input_path(eth_handle, eth_recv_esp_emac_check_cb, &recv_info));
+    TEST_ESP_OK(esp_eth_update_input_path_info(eth_handle, eth_recv_esp_emac_check_cb, &recv_info));
 
     // start the driver
     TEST_ESP_OK(esp_eth_start(eth_handle));
@@ -191,7 +192,46 @@ TEST_CASE("internal emac receive/transmit", "[esp_emac]")
     TEST_ESP_OK(esp_eth_transmit(eth_handle, test_pkt, transmit_size));
     TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
 
-    ESP_LOGI(TAG, "-- Verify transmission from multiple buffers --");
+    ESP_LOGI(TAG, "-- Verify transmission using extended Tx fnc using one buffer--");
+    transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE;
+    ESP_LOGI(TAG, "transmit frame size: %" PRIu16, transmit_size);
+    recv_info.expected_size = transmit_size;
+    eth_mac_time_t ts;
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, &ts, 2, test_pkt, transmit_size));
+    printf("test %lu.%lu sec\n", ts.seconds, ts.nanoseconds); // TODO finish the test
+    TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
+
+    transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE - 1;
+    ESP_LOGI(TAG, "transmit frame size: %" PRIu16, transmit_size);
+    recv_info.expected_size = transmit_size;
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 2, test_pkt, transmit_size));
+    TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
+
+    transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE + 1;
+    ESP_LOGI(TAG, "transmit frame size: %" PRIu16, transmit_size);
+    recv_info.expected_size = transmit_size;
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 2, test_pkt, transmit_size));
+    TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
+
+    transmit_size = 2 * CONFIG_ETH_DMA_BUFFER_SIZE;
+    ESP_LOGI(TAG, "transmit frame size: %" PRIu16, transmit_size);
+    recv_info.expected_size = transmit_size;
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 2, test_pkt, transmit_size));
+    TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
+
+    transmit_size = 2 * CONFIG_ETH_DMA_BUFFER_SIZE - 1;
+    ESP_LOGI(TAG, "transmit frame size: %" PRIu16, transmit_size);
+    recv_info.expected_size = transmit_size;
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 2, test_pkt, transmit_size));
+    TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
+
+    transmit_size = 2 * CONFIG_ETH_DMA_BUFFER_SIZE + 1;
+    ESP_LOGI(TAG, "transmit frame size: %" PRIu16, transmit_size);
+    recv_info.expected_size = transmit_size;
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 2, test_pkt, transmit_size));
+    TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
+
+    ESP_LOGI(TAG, "-- Verify transmission using extended Tx func with multiple buffers --");
     uint16_t transmit_size_2;
     // allocated the second buffer
     uint8_t *pkt_data_2 = malloc(ETH_MAX_PAYLOAD_LEN);
@@ -211,11 +251,11 @@ TEST_CASE("internal emac receive/transmit", "[esp_emac]")
     recv_info.expected_size_2 = transmit_size_2;
     for (int32_t i = 0; i < config_eth_dma_max_buffer_num*2; i++) {
         ESP_LOGI(TAG, "transmit joint frame size: %" PRIu16 ", i = %" PRIi32, transmit_size + transmit_size_2, i);
-        TEST_ESP_OK(esp_eth_transmit_vargs(eth_handle, 2, test_pkt, transmit_size, pkt_data_2, transmit_size_2));
+        TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 4, test_pkt, transmit_size, pkt_data_2, transmit_size_2));
         TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
     }
 
-    ESP_LOGI(TAG, "Verify boundary conditions");
+    ESP_LOGI(TAG, "Verify backwards compatibility");
     transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE;
     transmit_size_2 = CONFIG_ETH_DMA_BUFFER_SIZE;
     recv_info.expected_size = transmit_size;
@@ -224,12 +264,21 @@ TEST_CASE("internal emac receive/transmit", "[esp_emac]")
     TEST_ESP_OK(esp_eth_transmit_vargs(eth_handle, 2, test_pkt, transmit_size, pkt_data_2, transmit_size_2));
     TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
 
+    ESP_LOGI(TAG, "Verify boundary conditions");
+    transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE;
+    transmit_size_2 = CONFIG_ETH_DMA_BUFFER_SIZE;
+    recv_info.expected_size = transmit_size;
+    recv_info.expected_size_2 = transmit_size_2;
+    ESP_LOGI(TAG, "transmit joint frame size: %" PRIu16, transmit_size + transmit_size_2);
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 4, test_pkt, transmit_size, pkt_data_2, transmit_size_2));
+    TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
+
     transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE - 1;
     transmit_size_2 = CONFIG_ETH_DMA_BUFFER_SIZE;
     recv_info.expected_size = transmit_size;
     recv_info.expected_size_2 = transmit_size_2;
     ESP_LOGI(TAG, "transmit joint frame size: %" PRIu16, transmit_size + transmit_size_2);
-    TEST_ESP_OK(esp_eth_transmit_vargs(eth_handle, 2, test_pkt, transmit_size, pkt_data_2, transmit_size_2));
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 4, test_pkt, transmit_size, pkt_data_2, transmit_size_2));
     TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
 
     transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE + 1;
@@ -237,7 +286,7 @@ TEST_CASE("internal emac receive/transmit", "[esp_emac]")
     recv_info.expected_size = transmit_size;
     recv_info.expected_size_2 = transmit_size_2;
     ESP_LOGI(TAG, "transmit joint frame size: %" PRIu16, transmit_size + transmit_size_2);
-    TEST_ESP_OK(esp_eth_transmit_vargs(eth_handle, 2, test_pkt, transmit_size, pkt_data_2, transmit_size_2));
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 4, test_pkt, transmit_size, pkt_data_2, transmit_size_2));
     TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
 
     uint16_t transmit_size_3 = 256;
@@ -256,7 +305,7 @@ TEST_CASE("internal emac receive/transmit", "[esp_emac]")
     recv_info.expected_size_2 = transmit_size_2;
     recv_info.expected_size_3 = transmit_size_3;
     ESP_LOGI(TAG, "transmit joint frame size (3 buffs): %" PRIu16, transmit_size + transmit_size_2 + transmit_size_3);
-    TEST_ESP_OK(esp_eth_transmit_vargs(eth_handle, 3, test_pkt, transmit_size, pkt_data_2, transmit_size_2, pkt_data_3, transmit_size_3));
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 6, test_pkt, transmit_size, pkt_data_2, transmit_size_2, pkt_data_3, transmit_size_3));
     TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
 
     transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE - 1;
@@ -266,7 +315,7 @@ TEST_CASE("internal emac receive/transmit", "[esp_emac]")
     recv_info.expected_size_2 = transmit_size_2;
     recv_info.expected_size_3 = transmit_size_3;
     ESP_LOGI(TAG, "transmit joint frame size (3 buffs): %" PRIu16, transmit_size + transmit_size_2 + transmit_size_3);
-    TEST_ESP_OK(esp_eth_transmit_vargs(eth_handle, 3, test_pkt, transmit_size, pkt_data_2, transmit_size_2, pkt_data_3, transmit_size_3));
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 6, test_pkt, transmit_size, pkt_data_2, transmit_size_2, pkt_data_3, transmit_size_3));
     TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
 
     transmit_size = CONFIG_ETH_DMA_BUFFER_SIZE + 1;
@@ -276,7 +325,7 @@ TEST_CASE("internal emac receive/transmit", "[esp_emac]")
     recv_info.expected_size_2 = transmit_size_2;
     recv_info.expected_size_3 = transmit_size_3;
     ESP_LOGI(TAG, "transmit joint frame size (3 buffs): %" PRIu16, transmit_size + transmit_size_2 + transmit_size_3);
-    TEST_ESP_OK(esp_eth_transmit_vargs(eth_handle, 3, test_pkt, transmit_size, pkt_data_2, transmit_size_2, pkt_data_3, transmit_size_3));
+    TEST_ESP_OK(esp_eth_transmit_ctrl_vargs(eth_handle, NULL, 6, test_pkt, transmit_size, pkt_data_2, transmit_size_2, pkt_data_3, transmit_size_3));
     TEST_ASSERT(xSemaphoreTake(recv_info.mutex, pdMS_TO_TICKS(500)));
 
     free(test_pkt);
@@ -363,7 +412,7 @@ TEST_CASE("internal emac interrupt priority", "[esp_emac]")
 static uint8_t *s_recv_frames[TEST_FRAMES_NUM];
 static uint8_t s_recv_frames_cnt = 0;
 
-static esp_err_t eth_recv_esp_emac_err_check_cb(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t length, void *priv)
+static esp_err_t eth_recv_esp_emac_err_check_cb(esp_eth_handle_t hdl, uint8_t *buffer, uint32_t length, void *priv, void *info)
 {
     SemaphoreHandle_t mutex = (SemaphoreHandle_t)priv;
     s_recv_frames[s_recv_frames_cnt++] = buffer;
@@ -397,7 +446,7 @@ TEST_CASE("internal emac erroneous frames", "[esp_emac]")
     bool loopback_en = true;
     esp_eth_ioctl(eth_handle, ETH_CMD_S_PHY_LOOPBACK, &loopback_en);
 
-    TEST_ESP_OK(esp_eth_update_input_path(eth_handle, eth_recv_esp_emac_err_check_cb, mutex));
+    TEST_ESP_OK(esp_eth_update_input_path_info(eth_handle, eth_recv_esp_emac_err_check_cb, mutex));
 
     // start the driver
     TEST_ESP_OK(esp_eth_start(eth_handle));
diff --git a/components/esp_http_client/esp_http_client.c b/components/esp_http_client/esp_http_client.c
index 1e642d63dac..c7d2c28ffaf 100644
--- a/components/esp_http_client/esp_http_client.c
+++ b/components/esp_http_client/esp_http_client.c
@@ -1247,15 +1247,15 @@ int esp_http_client_read(esp_http_client_handle_t client, char *buffer, int len)
         ESP_LOGD(TAG, "need_read=%d, byte_to_read=%d, rlen=%d, ridx=%d", need_read, byte_to_read, rlen, ridx);
 
         if (rlen <= 0) {
+            esp_log_level_t sev = ESP_LOG_WARN;
+            /* Check for cleanly closed connection */
+            if (rlen == ERR_TCP_TRANSPORT_CONNECTION_CLOSED_BY_FIN && client->response->is_chunked) {
+                /* Explicit call to parser for invoking `message_complete` callback */
+                http_parser_execute(client->parser, client->parser_settings, res_buffer->data, 0);
+                /* ...and lowering the message severity, as closed connection from server side is expected in chunked transport */
+                sev = ESP_LOG_DEBUG;
+            }
             if (errno != 0) {
-                esp_log_level_t sev = ESP_LOG_WARN;
-                /* Check for cleanly closed connection */
-                if (rlen == ERR_TCP_TRANSPORT_CONNECTION_CLOSED_BY_FIN && client->response->is_chunked) {
-                    /* Explicit call to parser for invoking `message_complete` callback */
-                    http_parser_execute(client->parser, client->parser_settings, res_buffer->data, 0);
-                    /* ...and lowering the message severity, as closed connection from server side is expected in chunked transport */
-                    sev = ESP_LOG_DEBUG;
-                }
                 ESP_LOG_LEVEL(sev, TAG, "esp_transport_read returned:%d and errno:%d ", rlen, errno);
             }
 
diff --git a/components/esp_http_server/include/esp_http_server.h b/components/esp_http_server/include/esp_http_server.h
index 759eadf85f6..d6b6e7709aa 100644
--- a/components/esp_http_server/include/esp_http_server.h
+++ b/components/esp_http_server/include/esp_http_server.h
@@ -487,7 +487,7 @@ typedef struct httpd_uri {
  * // URI handler structure
  * httpd_uri_t my_uri {
  *     .uri      = "/my_uri/path/xyz",
- *     .method   = HTTPD_GET,
+ *     .method   = HTTP_GET,
  *     .handler  = my_uri_handler,
  *     .user_ctx = NULL
  * };
diff --git a/components/esp_http_server/src/httpd_parse.c b/components/esp_http_server/src/httpd_parse.c
index 3d76380a8b4..2fbc37f3eb8 100644
--- a/components/esp_http_server/src/httpd_parse.c
+++ b/components/esp_http_server/src/httpd_parse.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -86,7 +86,7 @@ static esp_err_t verify_url (http_parser *parser)
     ESP_LOGD(TAG, LOG_FMT("received URI = %s"), r->uri);
 
     /* Make sure version is HTTP/1.1 */
-    if ((parser->http_major != 1) && (parser->http_minor != 1)) {
+    if (!((parser->http_major == 1) && (parser->http_minor == 1))) {
         ESP_LOGW(TAG, LOG_FMT("unsupported HTTP version = %d.%d"),
                  parser->http_major, parser->http_minor);
         parser_data->error = HTTPD_505_VERSION_NOT_SUPPORTED;
@@ -106,7 +106,7 @@ static esp_err_t verify_url (http_parser *parser)
 }
 
 /* http_parser callback on finding url in HTTP request
- * Will be invoked ATLEAST once every packet
+ * Will be invoked AT LEAST once every packet
  */
 static esp_err_t cb_url(http_parser *parser,
                         const char *at, size_t length)
@@ -191,7 +191,7 @@ static size_t continue_parsing(http_parser *parser, size_t length)
 }
 
 /* http_parser callback on header field in HTTP request
- * May be invoked ATLEAST once every header field
+ * May be invoked AT LEAST once every header field
  */
 static esp_err_t cb_header_field(http_parser *parser, const char *at, size_t length)
 {
@@ -250,7 +250,7 @@ static esp_err_t cb_header_field(http_parser *parser, const char *at, size_t len
 }
 
 /* http_parser callback on header value in HTTP request.
- * May be invoked ATLEAST once every header value
+ * May be invoked AT LEAST once every header value
  */
 static esp_err_t cb_header_value(http_parser *parser, const char *at, size_t length)
 {
diff --git a/components/esp_https_ota/include/esp_https_ota.h b/components/esp_https_ota/include/esp_https_ota.h
index 850d329a05f..aeb06865afc 100644
--- a/components/esp_https_ota/include/esp_https_ota.h
+++ b/components/esp_https_ota/include/esp_https_ota.h
@@ -9,6 +9,7 @@
 #include <esp_http_client.h>
 #include <bootloader_common.h>
 #include "esp_app_desc.h"
+#include "esp_bootloader_desc.h"
 #include <sdkconfig.h>
 
 #include "esp_event.h"
@@ -26,7 +27,7 @@ ESP_EVENT_DECLARE_BASE(ESP_HTTPS_OTA_EVENT);
 typedef enum {
     ESP_HTTPS_OTA_START,                    /*!< OTA started */
     ESP_HTTPS_OTA_CONNECTED,                /*!< Connected to server */
-    ESP_HTTPS_OTA_GET_IMG_DESC,             /*!< Read app description from image header */
+    ESP_HTTPS_OTA_GET_IMG_DESC,             /*!< Read app/bootloader description from image header */
     ESP_HTTPS_OTA_VERIFY_CHIP_ID,           /*!< Verify chip id of new image */
     ESP_HTTPS_OTA_DECRYPT_CB,               /*!< Callback to decrypt function */
     ESP_HTTPS_OTA_WRITE_FLASH,              /*!< Flash write operation */
@@ -68,6 +69,11 @@ typedef struct {
     void *decrypt_user_ctx;                        /*!< User context for external decryption layer */
     uint16_t enc_img_header_size;                  /*!< Header size of pre-encrypted ota image header */
 #endif
+    struct {                                        /*!< Details of staging and final partitions for OTA update */
+        const esp_partition_t *staging;             /*!< New image will be downloaded in this staging partition. If NULL then a free app partition (passive app partition) is selected as the staging partition. */
+        const esp_partition_t *final;               /*!< Final destination partition. Its type/subtype will be used for verification. If set to NULL, staging partition shall be set as the final partition. */
+        bool finalize_with_copy;                    /*!< Flag to copy the staging image to the final partition at the end of OTA update */
+    } partition;                                    /*!< Struct containing details about the staging and final partitions for OTA update. */
 } esp_https_ota_config_t;
 
 #define ESP_ERR_HTTPS_OTA_BASE            (0x9000)
@@ -223,6 +229,23 @@ esp_err_t esp_https_ota_abort(esp_https_ota_handle_t https_ota_handle);
  */
 esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, esp_app_desc_t *new_app_info);
 
+/**
+ * @brief   Reads bootloader description from image header. The bootloader description provides information
+ *          like the "Bootloader version" of the image.
+ *
+ * @note    This API can be called only after esp_https_ota_begin() and before esp_https_ota_perform().
+ *          Calling this API is not mandatory.
+ *
+ * @param[in]   https_ota_handle   pointer to esp_https_ota_handle_t structure
+ * @param[out]  new_img_info       pointer to an allocated esp_bootloader_desc_t structure
+ *
+ * @return
+ *    - ESP_ERR_INVALID_ARG: Invalid arguments
+ *    - ESP_ERR_INVALID_STATE: Invalid state to call this API. esp_https_ota_begin() not called yet.
+ *    - ESP_FAIL: Failed to read image descriptor
+ *    - ESP_OK: Successfully read image descriptor
+ */
+esp_err_t esp_https_ota_get_bootloader_img_desc(esp_https_ota_handle_t https_ota_handle, esp_bootloader_desc_t *new_img_info);
 
 /**
 * @brief  This function returns OTA image data read so far.
diff --git a/components/esp_https_ota/src/esp_https_ota.c b/components/esp_https_ota/src/esp_https_ota.c
index 96459fa7fe1..faf2d4e187d 100644
--- a/components/esp_https_ota/src/esp_https_ota.c
+++ b/components/esp_https_ota/src/esp_https_ota.c
@@ -39,7 +39,11 @@ typedef enum {
 
 struct esp_https_ota_handle {
     esp_ota_handle_t update_handle;
-    const esp_partition_t *update_partition;
+    struct {                                  /*!< Details of staging and final partitions for OTA update */
+        const esp_partition_t *staging;       /*!< New image will be downloaded in this staging partition. If NULL then a free app partition (passive app partition) is selected as the staging partition. */
+        const esp_partition_t *final;         /*!< Final destination partition which is intended to be updated. Its type/subtype shall be used for verification. If NULL, staging partition is considered as the final partition. */
+        bool finalize_with_copy;              /*!< Flag to copy the staging image to the final at the end of OTA update */
+    } partition;
     esp_http_client_handle_t http_client;
     char *ota_upgrade_buf;
     size_t ota_upgrade_buf_size;
@@ -368,16 +372,35 @@ esp_err_t esp_https_ota_begin(const esp_https_ota_config_t *ota_config, esp_http
 #endif
     }
 
-    https_ota_handle->update_partition = NULL;
+    https_ota_handle->partition.staging = NULL;
     ESP_LOGI(TAG, "Starting OTA...");
-    https_ota_handle->update_partition = esp_ota_get_next_update_partition(NULL);
-    if (https_ota_handle->update_partition == NULL) {
-        ESP_LOGE(TAG, "Passive OTA partition not found");
+    if (ota_config->partition.staging != NULL) {
+        https_ota_handle->partition.staging = esp_partition_verify(ota_config->partition.staging);
+    } else {
+        https_ota_handle->partition.staging = esp_ota_get_next_update_partition(NULL);
+    }
+    if (https_ota_handle->partition.staging == NULL) {
+        ESP_LOGE(TAG, "Given staging partition or another suitable Passive OTA partition could not be found");
         err = ESP_FAIL;
         goto http_cleanup;
     }
     ESP_LOGI(TAG, "Writing to <%s> partition at offset 0x%" PRIx32,
-        https_ota_handle->update_partition->label, https_ota_handle->update_partition->address);
+        https_ota_handle->partition.staging->label, https_ota_handle->partition.staging->address);
+
+    if (ota_config->partition.final == NULL) {
+        https_ota_handle->partition.final = https_ota_handle->partition.staging;
+    } else {
+        if (ota_config->partition.staging != ota_config->partition.final) {
+            const esp_partition_t *final = esp_partition_verify(ota_config->partition.final);
+            if (final == NULL) {
+                ESP_LOGE(TAG, "Given final partition not found");
+                err = ESP_FAIL;
+                goto http_cleanup;
+            }
+            https_ota_handle->partition.final = final;
+            https_ota_handle->partition.finalize_with_copy = ota_config->partition.finalize_with_copy;
+        }
+    }
 
     const int alloc_size = MAX(ota_config->http_config->buffer_size, DEFAULT_OTA_BUF_SIZE);
     if (ota_config->buffer_caps != 0) {
@@ -449,7 +472,7 @@ static esp_err_t read_header(esp_https_ota_t *handle)
     return ESP_OK;
 }
 
-esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, esp_app_desc_t *new_app_info)
+static esp_err_t get_description_from_image(esp_https_ota_handle_t https_ota_handle, void *new_img_info)
 {
     esp_https_ota_dispatch_event(ESP_HTTPS_OTA_GET_IMG_DESC, NULL, 0);
 
@@ -460,7 +483,7 @@ esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, es
 #endif
 
     esp_https_ota_t *handle = (esp_https_ota_t *)https_ota_handle;
-    if (handle == NULL || new_app_info == NULL)  {
+    if (handle == NULL || new_img_info == NULL)  {
         ESP_LOGE(TAG, "esp_https_ota_get_img_desc: Invalid argument");
         return ESP_ERR_INVALID_ARG;
     }
@@ -472,17 +495,41 @@ esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, es
         return ESP_FAIL;
     }
 
-    const int app_desc_offset = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t);
-    esp_app_desc_t *app_info = (esp_app_desc_t *) &handle->ota_upgrade_buf[app_desc_offset];
-    if (app_info->magic_word != ESP_APP_DESC_MAGIC_WORD) {
-        ESP_LOGE(TAG, "Incorrect app descriptor magic");
+    void *img_info = (void *)&handle->ota_upgrade_buf[sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t)];
+    unsigned img_info_len;
+    if (handle->partition.final->type == ESP_PARTITION_TYPE_APP) {
+        img_info_len = sizeof(esp_app_desc_t);
+        esp_app_desc_t *app_info = (esp_app_desc_t *)img_info;
+        if (app_info->magic_word != ESP_APP_DESC_MAGIC_WORD) {
+            ESP_LOGE(TAG, "Incorrect app descriptor magic");
+            return ESP_FAIL;
+        }
+    } else if (handle->partition.final->type == ESP_PARTITION_TYPE_BOOTLOADER) {
+        img_info_len = sizeof(esp_bootloader_desc_t);
+        esp_bootloader_desc_t *bootloader_info = (esp_bootloader_desc_t *)img_info;
+        if (bootloader_info->magic_byte != ESP_BOOTLOADER_DESC_MAGIC_BYTE) {
+            ESP_LOGE(TAG, "Incorrect bootloader descriptor magic");
+            return ESP_FAIL;
+        }
+    } else {
+        ESP_LOGE(TAG, "This partition type (%d) is not supported", handle->partition.final->type);
         return ESP_FAIL;
     }
 
-    memcpy(new_app_info, app_info, sizeof(esp_app_desc_t));
+    memcpy(new_img_info, img_info, img_info_len);
     return ESP_OK;
 }
 
+esp_err_t esp_https_ota_get_img_desc(esp_https_ota_handle_t https_ota_handle, esp_app_desc_t *new_app_info)
+{
+    return get_description_from_image(https_ota_handle, new_app_info);
+}
+
+esp_err_t esp_https_ota_get_bootloader_img_desc(esp_https_ota_handle_t https_ota_handle, esp_bootloader_desc_t *new_img_info)
+{
+    return get_description_from_image(https_ota_handle, new_img_info);
+}
+
 static esp_err_t esp_ota_verify_chip_id(const void *arg)
 {
     esp_image_header_t *data = (esp_image_header_t *)(arg);
@@ -512,11 +559,12 @@ esp_err_t esp_https_ota_perform(esp_https_ota_handle_t https_ota_handle)
     const int erase_size = handle->bulk_flash_erase ? (handle->image_length > 0 ? handle->image_length : OTA_SIZE_UNKNOWN) : OTA_WITH_SEQUENTIAL_WRITES;
     switch (handle->state) {
         case ESP_HTTPS_OTA_BEGIN:
-            err = esp_ota_begin(handle->update_partition, erase_size, &handle->update_handle);
+            err = esp_ota_begin(handle->partition.staging, erase_size, &handle->update_handle);
             if (err != ESP_OK) {
                 ESP_LOGE(TAG, "esp_ota_begin failed (%s)", esp_err_to_name(err));
                 return err;
             }
+            esp_ota_set_final_partition(handle->update_handle, handle->partition.final, handle->partition.finalize_with_copy);
             handle->state = ESP_HTTPS_OTA_IN_PROGRESS;
             /* In case `esp_https_ota_get_img_desc` was invoked first,
                then the image data read there should be written to OTA partition
@@ -550,9 +598,11 @@ esp_err_t esp_https_ota_perform(esp_https_ota_handle_t https_ota_handle)
                 return ESP_FAIL;
             }
 #endif // CONFIG_ESP_HTTPS_OTA_DECRYPT_CB
-            err = esp_ota_verify_chip_id(data_buf);
-            if (err != ESP_OK) {
-                return err;
+            if (handle->partition.final->type == ESP_PARTITION_TYPE_APP || handle->partition.final->type == ESP_PARTITION_TYPE_BOOTLOADER) {
+                err = esp_ota_verify_chip_id(data_buf);
+                if (err != ESP_OK) {
+                    return err;
+                }
             }
             return _ota_write(handle, data_buf, binary_file_len);
         case ESP_HTTPS_OTA_IN_PROGRESS:
@@ -674,12 +724,16 @@ esp_err_t esp_https_ota_finish(esp_https_ota_handle_t https_ota_handle)
             break;
     }
 
-    if ((err == ESP_OK) && (handle->state == ESP_HTTPS_OTA_SUCCESS)) {
-        err = esp_ota_set_boot_partition(handle->update_partition);
+    if ((handle->partition.final->type == ESP_PARTITION_TYPE_APP) && (err == ESP_OK) && (handle->state == ESP_HTTPS_OTA_SUCCESS)) {
+        if (handle->partition.final->subtype >= ESP_PARTITION_SUBTYPE_APP_OTA_0 && handle->partition.final->subtype < ESP_PARTITION_SUBTYPE_APP_OTA_MAX) {
+            // Do not allow the boot partition to be set as the Factory partition, because ota_data will be erased in this case.
+            // The user can call it afterward if needed.
+            err = esp_ota_set_boot_partition(handle->partition.staging);
+        }
         if (err != ESP_OK) {
             ESP_LOGE(TAG, "esp_ota_set_boot_partition failed! err=0x%x", err);
         } else {
-            esp_https_ota_dispatch_event(ESP_HTTPS_OTA_UPDATE_BOOT_PARTITION, (void *)(&handle->update_partition->subtype), sizeof(esp_partition_subtype_t));
+            esp_https_ota_dispatch_event(ESP_HTTPS_OTA_UPDATE_BOOT_PARTITION, (void *)(&handle->partition.final->subtype), sizeof(esp_partition_subtype_t));
         }
     }
     free(handle);
diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt
index e1b6efc00db..1d3585ac91a 100644
--- a/components/esp_hw_support/CMakeLists.txt
+++ b/components/esp_hw_support/CMakeLists.txt
@@ -1,4 +1,5 @@
 idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(non_os_build NON_OS_BUILD)
 
 # On Linux, we only support a few features, hence this simple component registration
 if(${target} STREQUAL "linux")
@@ -22,7 +23,7 @@ if(CONFIG_RTC_CLK_SRC_INT_RC32K)
 endif()
 
 set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c")
-if(NOT BOOTLOADER_BUILD)
+if(NOT non_os_build)
     list(APPEND srcs "esp_clk.c"
                      "clk_ctrl_os.c"
                      "hw_random.c"
@@ -163,15 +164,11 @@ idf_build_get_property(target IDF_TARGET)
 add_subdirectory(port/${target})
 add_subdirectory(lowpower)
 
-if(CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10229
-    target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer")
-endif()
-
 if(CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND OR CONFIG_PM_SLP_DISABLE_GPIO)
     target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_sleep_gpio_include")
 endif()
 
-if(NOT BOOTLOADER_BUILD)
+if(NOT non_os_build)
     if(CONFIG_SPIRAM)
         idf_component_optional_requires(PRIVATE esp_psram)
     endif()
diff --git a/components/esp_hw_support/Kconfig b/components/esp_hw_support/Kconfig
index 167d828de28..e29c37b2422 100644
--- a/components/esp_hw_support/Kconfig
+++ b/components/esp_hw_support/Kconfig
@@ -69,8 +69,9 @@ menu "Hardware Settings"
         # This is here since this option affect behavior of esp_light_sleep_start
         # regardless of power management configuration.
         config ESP_SLEEP_POWER_DOWN_FLASH
-            bool "Power down flash in light sleep when there is no SPIRAM"
-            depends on !SPIRAM
+            bool "Power down flash in light sleep when there is no SPIRAM or SPIRAM has independent power supply"
+            depends on !SPIRAM || ESP_LDO_RESERVE_PSRAM
+            depends on !(IDF_TARGET_ESP32P4 && (ESP32P4_REV_MIN_FULL < 100))
             default n
             help
                 If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs
diff --git a/components/esp_hw_support/dma/Kconfig.dma b/components/esp_hw_support/dma/Kconfig.dma
index fa43dd6ea8e..5620926e3ee 100644
--- a/components/esp_hw_support/dma/Kconfig.dma
+++ b/components/esp_hw_support/dma/Kconfig.dma
@@ -29,6 +29,7 @@ menu "DW_GDMA Configurations"
     config DW_GDMA_CTRL_FUNC_IN_IRAM
         bool
         default n
+        select DW_GDMA_OBJ_DRAM_SAFE
         help
             Place DW_GDMA control functions (e.g. dw_gdma_channel_continue) into IRAM,
             so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
@@ -36,6 +37,7 @@ menu "DW_GDMA Configurations"
     config DW_GDMA_SETTER_FUNC_IN_IRAM
         bool
         default n
+        select DW_GDMA_OBJ_DRAM_SAFE
         help
             Place DW_GDMA setter functions (e.g. dw_gdma_channel_set_block_markers) into IRAM,
             so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
@@ -43,6 +45,7 @@ menu "DW_GDMA Configurations"
     config DW_GDMA_GETTER_FUNC_IN_IRAM
         bool
         default n
+        select DW_GDMA_OBJ_DRAM_SAFE
         help
             Place DW_GDMA getter functions (e.g. dw_gdma_link_list_get_item) into IRAM,
             so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
@@ -50,11 +53,19 @@ menu "DW_GDMA Configurations"
     config DW_GDMA_ISR_IRAM_SAFE
         bool
         default n
+        select DW_GDMA_OBJ_DRAM_SAFE
         help
             This will ensure the DW_GDMA interrupt handler is IRAM-Safe, allow to avoid flash
             cache misses, and also be able to run whilst the cache is disabled.
             (e.g. SPI Flash write).
 
+    config DW_GDMA_OBJ_DRAM_SAFE
+        bool
+        default n
+        help
+            This will ensure the DW_GDMA object is DRAM-Safe, allow to avoid external memory
+            cache misses, and also be accessible whilst the cache is disabled.
+
     config DW_GDMA_ENABLE_DEBUG_LOG
         bool "Enable debug log"
         default n
diff --git a/components/esp_hw_support/dma/dw_gdma.c b/components/esp_hw_support/dma/dw_gdma.c
index f76f1245eb5..fc4aaf4078e 100644
--- a/components/esp_hw_support/dma/dw_gdma.c
+++ b/components/esp_hw_support/dma/dw_gdma.c
@@ -48,7 +48,7 @@ static const char *TAG = "dw-gdma";
 #define DW_GDMA_GET_CACHE_ADDRESS(nc_addr) (nc_addr)
 #endif
 
-#if CONFIG_DW_GDMA_ISR_IRAM_SAFE || CONFIG_DW_GDMA_CTRL_FUNC_IN_IRAM || DW_GDMA_SETTER_FUNC_IN_IRAM
+#if CONFIG_DW_GDMA_OBJ_DRAM_SAFE
 #define DW_GDMA_MEM_ALLOC_CAPS    (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
 #else
 #define DW_GDMA_MEM_ALLOC_CAPS    MALLOC_CAP_DEFAULT
diff --git a/components/esp_hw_support/dma/gdma_link.c b/components/esp_hw_support/dma/gdma_link.c
index d13b62e64d2..45923f57a95 100644
--- a/components/esp_hw_support/dma/gdma_link.c
+++ b/components/esp_hw_support/dma/gdma_link.c
@@ -13,6 +13,7 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "soc/soc_caps.h"
+#include "soc/ext_mem_defs.h"
 #include "esp_log.h"
 #include "esp_check.h"
 #include "esp_memory_utils.h"
@@ -227,11 +228,20 @@ uintptr_t gdma_link_get_head_addr(gdma_link_list_handle_t list)
     return (uintptr_t)(list->items);
 }
 
+esp_err_t gdma_link_concat(gdma_link_list_handle_t first_link, int first_link_item_index, gdma_link_list_handle_t second_link, int second_link_item_index)
+{
+    ESP_RETURN_ON_FALSE(first_link && second_link, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    gdma_link_list_item_t *lli_nc = NULL;
+    lli_nc = (gdma_link_list_item_t *)(first_link->items_nc + (first_link->num_items + first_link_item_index) % first_link->num_items * first_link->item_size);
+    lli_nc->next = (gdma_link_list_item_t *)(second_link->items + (second_link->num_items + second_link_item_index) % second_link->num_items * second_link->item_size);
+    return ESP_OK;
+}
+
 esp_err_t gdma_link_set_owner(gdma_link_list_handle_t list, int item_index, gdma_lli_owner_t owner)
 {
     ESP_RETURN_ON_FALSE_ISR(list, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     ESP_RETURN_ON_FALSE_ISR(item_index < list->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid item index");
-    gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + item_index * list->item_size);
+    gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + (list->num_items + item_index) % list->num_items * list->item_size);
     lli->dw0.owner = owner;
     return ESP_OK;
 }
@@ -240,7 +250,7 @@ esp_err_t gdma_link_get_owner(gdma_link_list_handle_t list, int item_index, gdma
 {
     ESP_RETURN_ON_FALSE_ISR(list && owner, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     ESP_RETURN_ON_FALSE_ISR(item_index < list->num_items, ESP_ERR_INVALID_ARG, TAG, "invalid item index");
-    gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + item_index * list->item_size);
+    gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + (list->num_items + item_index) % list->num_items * list->item_size);
     *owner = lli->dw0.owner;
     return ESP_OK;
 }
diff --git a/components/esp_hw_support/dma/include/esp_private/gdma_link.h b/components/esp_hw_support/dma/include/esp_private/gdma_link.h
index 94a13651c4e..fa350e792a6 100644
--- a/components/esp_hw_support/dma/include/esp_private/gdma_link.h
+++ b/components/esp_hw_support/dma/include/esp_private/gdma_link.h
@@ -71,7 +71,7 @@ typedef struct {
         uint32_t mark_final: 1; /*!< Whether to terminate the DMA link list at this item.
                                      Note, DMA engine will stop at this item and trigger an interrupt.
                                      If `mark_final` is not set, this list item will point to the next item, and
-                                     wrap around to the head item if it's the one in the list. */
+                                     wrap around to the head item if it's the last one in the list. */
     } flags; //!< Flags for buffer mount configurations
 } gdma_buffer_mount_config_t;
 
@@ -105,6 +105,31 @@ esp_err_t gdma_link_mount_buffers(gdma_link_list_handle_t list, uint32_t start_i
  */
 uintptr_t gdma_link_get_head_addr(gdma_link_list_handle_t list);
 
+/**
+ * @brief Concatenate two link lists as follows:
+ *
+ *        Link A: A1 --> A2 --> A3 --> A4
+ *                    | item_index
+ *                    +-----+
+ *                          |
+ *                          v item_index
+ *        Link B: B1 --> B2 --> B3 --> B4
+ *
+ *      After concatenation:
+ *       Link A: A1 --> B3 --> B4
+ *       Link B: B1 --> B2 --> B3 --> B4
+ *
+ * @param[in] first_link First link list handle, allocated by `gdma_new_link_list`
+ * @param[in] first_link_item_index Index of the item in the first link list (-1 means the last item)
+ * @param[in] second_link Second link list handle, allocated by `gdma_new_link_list`
+ * @param[in] second_link_item_index Index of the item in the second link list (-1 means the last item)
+ * @return
+ *      - ESP_OK: Concatenate the link lists successfully
+ *      - ESP_ERR_INVALID_ARG: Concatenate the link lists failed because of invalid argument
+ *      - ESP_FAIL: Concatenate the link lists failed because of other error
+ */
+esp_err_t gdma_link_concat(gdma_link_list_handle_t first_link, int first_link_item_index, gdma_link_list_handle_t second_link, int second_link_item_index);
+
 /**
  * @brief GDMA link list item owner
  */
@@ -117,7 +142,7 @@ typedef enum {
  * @brief Set the ownership for a DMA link list item
  *
  * @param[in] list Link list handle, allocated by `gdma_new_link_list`
- * @param[in] item_index Index of the link list item
+ * @param[in] item_index Index of the link list item (-1 means the last item)
  * @param[in] owner Ownership
  * @return
  *      - ESP_OK: Set the ownership successfully
@@ -130,7 +155,7 @@ esp_err_t gdma_link_set_owner(gdma_link_list_handle_t list, int item_index, gdma
  * @brief Get the ownership of a DMA link list item
  *
  * @param[in] list Link list handle, allocated by `gdma_new_link_list`
- * @param[in] item_index Index of the link list item
+ * @param[in] item_index Index of the link list item (-1 means the last item)
  * @param[out] owner Ownership
  * @return
  *      - ESP_OK: Get the ownership successfully
diff --git a/components/esp_hw_support/esp_etm.c b/components/esp_hw_support/esp_etm.c
index 9dfbfc6cb40..b8ae6349b7c 100644
--- a/components/esp_hw_support/esp_etm.c
+++ b/components/esp_hw_support/esp_etm.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,7 +16,7 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "soc/soc_caps.h"
-#include "soc/periph_defs.h"
+#include "soc/etm_periph.h"
 #include "esp_log.h"
 #include "esp_check.h"
 #include "esp_heap_caps.h"
@@ -25,10 +25,13 @@
 #include "hal/etm_ll.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/etm_interface.h"
+#include "esp_private/sleep_retention.h"
 
 #define ETM_MEM_ALLOC_CAPS   MALLOC_CAP_DEFAULT
 
-#if CONFIG_IDF_TARGET_ESP32P4
+#define ETM_USE_RETENTION_LINK  (SOC_ETM_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
+
+#if !SOC_RCC_IS_INDEPENDENT
 // Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
 #define ETM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
 #else
@@ -70,6 +73,32 @@ struct esp_etm_channel_t {
 // ETM driver platform, it's always a singleton
 static etm_platform_t s_platform;
 
+#if ETM_USE_RETENTION_LINK
+static esp_err_t etm_create_sleep_retention_link_cb(void *arg)
+{
+    etm_group_t *group = (etm_group_t *)arg;
+    int group_id = group->group_id;
+    esp_err_t err = sleep_retention_entries_create(etm_reg_retention_info[group_id].regdma_entry_array,
+                                                   etm_reg_retention_info[group_id].array_size,
+                                                   REGDMA_LINK_PRI_ETM, etm_reg_retention_info[group_id].module);
+    return err;
+}
+
+static void etm_create_retention_module(etm_group_t *group)
+{
+    int group_id = group->group_id;
+    sleep_retention_module_t module = etm_reg_retention_info[group_id].module;
+    _lock_acquire(&s_platform.mutex);
+    if ((sleep_retention_get_inited_modules() & BIT(module)) && !(sleep_retention_get_created_modules() & BIT(module))) {
+        if (sleep_retention_module_allocate(module) != ESP_OK) {
+            // even though the sleep retention module create failed, ETM driver should still work, so just warning here
+            ESP_LOGW(TAG, "create retention link failed %d, power domain won't be turned off during sleep", group_id);
+        }
+    }
+    _lock_release(&s_platform.mutex);
+}
+#endif // ETM_USE_RETENTION_LINK
+
 static etm_group_t *etm_acquire_group_handle(int group_id)
 {
     bool new_group = false;
@@ -90,7 +119,22 @@ static etm_group_t *etm_acquire_group_handle(int group_id)
                 etm_ll_enable_bus_clock(group_id, true);
                 etm_ll_reset_register(group_id);
             }
-
+#if ETM_USE_RETENTION_LINK
+            sleep_retention_module_t module = etm_reg_retention_info[group_id].module;
+            sleep_retention_module_init_param_t init_param = {
+                .cbs = {
+                    .create = {
+                        .handle = etm_create_sleep_retention_link_cb,
+                        .arg = group,
+                    },
+                },
+                .depends = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM)
+            };
+            if (sleep_retention_module_init(module, &init_param) != ESP_OK) {
+                // even though the sleep retention module init failed, ETM driver may still work, so just warning here
+                ESP_LOGW(TAG, "init sleep retention failed %d, power domain may be turned off during sleep", group_id);
+            }
+#endif // ETM_USE_RETENTION_LINK
             // initialize HAL context
             etm_hal_init(&group->hal);
         }
@@ -129,6 +173,15 @@ static void etm_release_group_handle(etm_group_t *group)
     _lock_release(&s_platform.mutex);
 
     if (do_deinitialize) {
+#if ETM_USE_RETENTION_LINK
+        sleep_retention_module_t module = etm_reg_retention_info[group_id].module;
+        if (sleep_retention_get_created_modules() & BIT(module)) {
+            sleep_retention_module_free(module);
+        }
+        if (sleep_retention_get_inited_modules() & BIT(module)) {
+            sleep_retention_module_deinit(module);
+        }
+#endif
         free(group);
         ESP_LOGD(TAG, "del group (%d)", group_id);
     }
@@ -192,6 +245,9 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch
     esp_err_t ret = ESP_OK;
     esp_etm_channel_t *chan = NULL;
     ESP_GOTO_ON_FALSE(config && ret_chan, ESP_ERR_INVALID_ARG, err, TAG, "invalid args");
+#if !SOC_ETM_SUPPORT_SLEEP_RETENTION
+    ESP_RETURN_ON_FALSE(config->flags.allow_pd == 0, ESP_ERR_NOT_SUPPORTED, TAG, "not able to power down in light sleep");
+#endif // SOC_ETM_SUPPORT_SLEEP_RETENTION
 
     chan = heap_caps_calloc(1, sizeof(esp_etm_channel_t), ETM_MEM_ALLOC_CAPS);
     ESP_GOTO_ON_FALSE(chan, ESP_ERR_NO_MEM, err, TAG, "no mem for channel");
@@ -201,6 +257,12 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch
     int group_id = group->group_id;
     int chan_id = chan->chan_id;
 
+#if ETM_USE_RETENTION_LINK
+    if (config->flags.allow_pd != 0) {
+        etm_create_retention_module(group);
+    }
+#endif // ETM_USE_RETENTION_LINK
+
     chan->fsm = ETM_CHAN_FSM_INIT;
     ESP_LOGD(TAG, "new etm channel (%d,%d) at %p", group_id, chan_id, chan);
     *ret_chan = chan;
diff --git a/components/esp_hw_support/esp_memory_utils.c b/components/esp_hw_support/esp_memory_utils.c
index 766ca5a2c18..62627cbcb97 100644
--- a/components/esp_hw_support/esp_memory_utils.c
+++ b/components/esp_hw_support/esp_memory_utils.c
@@ -67,7 +67,7 @@ bool esp_ptr_external_ram(const void *p)
 #endif  //CONFIG_SPIRAM
 }
 
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
 bool esp_stack_ptr_in_extram(uint32_t sp)
 {
     //Check if stack ptr is on PSRAM, and 16 byte aligned.
diff --git a/components/esp_hw_support/include/esp_etm.h b/components/esp_hw_support/include/esp_etm.h
index c0757abf8ab..daa97d76c32 100644
--- a/components/esp_hw_support/include/esp_etm.h
+++ b/components/esp_hw_support/include/esp_etm.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -32,7 +32,11 @@ typedef struct esp_etm_task_t *esp_etm_task_handle_t;
  * @brief ETM channel configuration
  */
 typedef struct {
-
+    /// Extra configuration flags for ETM channel
+    struct etm_chan_flags {
+        uint32_t allow_pd : 1; /*!< If set, driver allows the power domain to be powered off when system enters sleep mode.
+                                    This can save power, but at the expense of more RAM being consumed to save register context. */
+    } flags; /*!< ETM channel flags */
 } esp_etm_channel_config_t;
 
 /**
diff --git a/components/esp_hw_support/include/esp_memory_utils.h b/components/esp_hw_support/include/esp_memory_utils.h
index 427dc4912ea..d17d6f26965 100644
--- a/components/esp_hw_support/include/esp_memory_utils.h
+++ b/components/esp_hw_support/include/esp_memory_utils.h
@@ -352,7 +352,7 @@ inline static bool esp_stack_ptr_in_dram(uint32_t sp)
     return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0));
 }
 
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
 /**
  * @brief Check if the stack pointer is in external ram
  *
@@ -374,7 +374,7 @@ __attribute__((always_inline))
 inline static bool esp_stack_ptr_is_sane(uint32_t sp)
 {
     return esp_stack_ptr_in_dram(sp)
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
         || esp_stack_ptr_in_extram(sp)
 #endif
 #if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h
index 5b481946074..6d347788a24 100644
--- a/components/esp_hw_support/include/esp_private/esp_pmu.h
+++ b/components/esp_hw_support/include/esp_private/esp_pmu.h
@@ -50,6 +50,7 @@ typedef enum {
 #define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17)
 #define RTC_SLEEP_NO_ULTRA_LOW          BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature
 #define RTC_SLEEP_XTAL_AS_RTC_FAST      BIT(19)
+#define RTC_SLEEP_LP_PERIPH_USE_XTAL    BIT(20)
 
 #if SOC_PM_SUPPORT_EXT0_WAKEUP
 #define RTC_EXT0_TRIG_EN            PMU_EXT0_WAKEUP_EN      //!< EXT0 wakeup
@@ -109,6 +110,12 @@ typedef enum {
 #define RTC_LP_CORE_TRIG_EN         0
 #endif //SOC_LP_CORE_SUPPORTED
 
+#if SOC_LP_VAD_SUPPORTED
+#define RTC_LP_VAD_TRIG_EN          PMU_LP_I2S_WAKEUP_EN   //!< LP VAD wakeup
+#else
+#define RTC_LP_VAD_TRIG_EN          0
+#endif //SOC_LP_VAD_SUPPORTED
+
 #define RTC_XTAL32K_DEAD_TRIG_EN    0 // TODO
 #define RTC_BROWNOUT_DET_TRIG_EN    0 // TODO
 
@@ -127,6 +134,7 @@ typedef enum {
                                RTC_TOUCH_TRIG_EN        | \
                                RTC_XTAL32K_DEAD_TRIG_EN | \
                                RTC_USB_TRIG_EN          | \
+                               RTC_LP_VAD_TRIG_EN       | \
                                RTC_BROWNOUT_DET_TRIG_EN)
 
 
diff --git a/components/esp_hw_support/include/esp_private/esp_regdma.h b/components/esp_hw_support/include/esp_private/esp_regdma.h
index 9e904997f70..1a082408fd7 100644
--- a/components/esp_hw_support/include/esp_private/esp_regdma.h
+++ b/components/esp_hw_support/include/esp_private/esp_regdma.h
@@ -396,9 +396,9 @@ void *regdma_find_prev_module_link_tail(void *link, void *tail, int entry, uint3
  */
 void *regdma_find_next_module_link_head(void *link, void *tail, int entry, uint32_t module);
 
-#define regdma_link_init_safe(pcfg, branch, module, ...)    regdma_link_init((pcfg), (branch), (module), __VA_NARG__(__VA_ARGS__), ##__VA_ARGS__)
+#define regdma_link_init_safe(pcfg, branch, module, ...)    regdma_link_init((pcfg), (branch), (module), ESP_VA_NARG(__VA_ARGS__), ##__VA_ARGS__)
 
-#define regdma_link_update_next_safe(link, ...)             regdma_link_update_next((link), __VA_NARG__(__VA_ARGS__), ##__VA_ARGS__)
+#define regdma_link_update_next_safe(link, ...)             regdma_link_update_next((link), ESP_VA_NARG(__VA_ARGS__), ##__VA_ARGS__)
 
 #endif // SOC_PAU_SUPPORTED
 
diff --git a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h
index df9c2a79e29..747d426cd9c 100644
--- a/components/esp_hw_support/include/esp_private/esp_sleep_internal.h
+++ b/components/esp_hw_support/include/esp_private/esp_sleep_internal.h
@@ -38,6 +38,7 @@ typedef enum {
     ESP_SLEEP_ULTRA_LOW_MODE,             //!< In ultra low mode, 2uA is saved, but RTC memory can't use at high temperature, and RTCIO can't be used as INPUT.
     ESP_SLEEP_RTC_FAST_USE_XTAL_MODE,     //!< The mode in which the crystal is used as the RTC_FAST clock source, need keep XTAL on in HP_SLEEP mode when ULP is working.
     ESP_SLEEP_DIG_USE_XTAL_MODE,          //!< The mode requested by digital peripherals to keep XTAL clock on during sleep (both HP_SLEEP and LP_SLEEP mode). (!!! Only valid for lightsleep, will override the XTAL domain config by esp_sleep_pd_config)
+    ESP_SLEEP_LP_USE_XTAL_MODE,           //!< The mode requested by lp peripherals to keep XTAL clock on during sleep. Only valid for lightsleep.
     ESP_SLEEP_MODE_MAX,
 } esp_sleep_sub_mode_t;
 
@@ -107,6 +108,22 @@ esp_err_t esp_deep_sleep_register_phy_hook(esp_deep_sleep_cb_t new_dslp_cb);
 void esp_deep_sleep_deregister_phy_hook(esp_deep_sleep_cb_t old_dslp_cb);
 #endif
 
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
+/**
+ * @brief Backup or restore the MMU when the top domain is powered down.
+ * @param backup_or_restore decide to backup mmu or restore mmu
+ */
+void esp_sleep_mmu_retention(bool backup_or_restore);
+
+/**
+ * @brief Whether to allow the top domain to be powered off due to mmu domain requiring retention.
+ *
+ * In light sleep mode, only when the system can provide enough memory
+ * for mmu retention, the top power domain can be powered off.
+ */
+bool mmu_domain_pd_allowed(void);
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h
index def755d8156..4be8502eaf1 100644
--- a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h
+++ b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,11 +10,50 @@
 #include "sdkconfig.h"
 #include "esp_rom_regi2c.h"
 #include "soc/regi2c_defs.h"
+#include "soc/soc_caps.h"
+#include "esp_private/periph_ctrl.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#ifdef BOOTLOADER_BUILD
+
+// For bootloader, the strategy is to keep the analog i2c master clock always enabled if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (in bootloader_hardware_init())
+#define ANALOG_CLOCK_ENABLE()
+#define ANALOG_CLOCK_DISABLE()
+
+#else // !BOOTLOADER_BUILD
+
+#if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+// This clock needs to be enabled for regi2c write/read, pll calibaration, PHY, RNG, ADC, etc.
+// Use reference count to manage the analog i2c master clock
+#define ANALOG_CLOCK_ENABLE() \
+      PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_ANA_I2C_MASTER_MODULE, ref_count) { \
+            if (ref_count == 0) { \
+                  regi2c_ctrl_ll_master_enable_clock(true); \
+            } \
+      }
+
+#define ANALOG_CLOCK_DISABLE() \
+      PERIPH_RCC_RELEASE_ATOMIC(PERIPH_ANA_I2C_MASTER_MODULE, ref_count) { \
+            if (ref_count == 0) { \
+                  regi2c_ctrl_ll_master_enable_clock(false); \
+            } \
+      }
+
+#else
+#define ANALOG_CLOCK_ENABLE()
+#define ANALOG_CLOCK_DISABLE()
+#endif
+
+#endif // BOOTLOADER_BUILD
+
+// regi2c write/read requires analog i2c master clock enabled
+#define REGI2C_CLOCK_ENABLE()      ANALOG_CLOCK_ENABLE()
+#define REGI2C_CLOCK_DISABLE()     ANALOG_CLOCK_DISABLE()
+
 
 #define regi2c_read_reg_raw        esp_rom_regi2c_read
 #define regi2c_read_reg_mask_raw   esp_rom_regi2c_read_mask
@@ -70,6 +109,13 @@ void regi2c_analog_cali_reg_read(void);
 void regi2c_analog_cali_reg_write(void);
 #endif   //#if ADC_CALI_PD_WORKAROUND
 
+#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+// regi2c would be powered down in light sleep, but measure range is recorded
+// in regi2c, so this function is used for record.
+void regi2c_tsens_reg_read(void);
+void regi2c_tsens_reg_write(void);
+#endif
+
 /* Enable/Disable regi2c_saradc with calling these two functions.
    With reference count protection inside.
    Internal use only.
diff --git a/components/esp_hw_support/include/esp_private/rtc_clk.h b/components/esp_hw_support/include/esp_private/rtc_clk.h
index 52610fa0d1c..4480780217f 100644
--- a/components/esp_hw_support/include/esp_private/rtc_clk.h
+++ b/components/esp_hw_support/include/esp_private/rtc_clk.h
@@ -18,11 +18,12 @@ extern "C" {
  * @brief Switch CPU clock source to XTAL, and let cpu frequency equal to main XTAL frequency.
  *
  * This function does not disable CPU's source PLL. If the PLL requires to be disabled to save power, please call
- * `rtc_clk_cpu_freq_set_xtal` instead. It does one extra check (if necessary) to see whether can disable the
- * corresponding PLL after switching the CPU clock source to XTAL.
+ * `rtc_clk_cpu_freq_set_xtal` instead. It will always disable the corresponding PLL after switching the CPU clock
+ * source to XTAL (except for S2).
  *
- * Currently, this function should only be called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
- * clock source back to XTAL (by default) before reset.
+ * Currently, this function is only called in `esp_restart_noos` and `esp_restart_noos_dig` to switch the CPU
+ * clock source back to XTAL (by default) before reset, and in `esp_sleep_start` to switch CPU clock source to XTAL
+ * before entering sleep for PMU supported chips.
  */
 void rtc_clk_cpu_set_to_default_config(void);
 
@@ -32,12 +33,6 @@ void rtc_clk_cpu_set_to_default_config(void);
  * Currently, this function is only used for tracking whether USB Serial/JTAG is using the 48MHz PHY clock
  *
  * Note: Calling this function only helps to not disable the BBPLL clock in `rtc_clk_cpu_freq_set_config`.
- *       For light and deep sleep, whether to disable the BBPLL in the internal call to `rtc_clk_cpu_freq_set_xtal`
- *       varies for targets.
- *       On ESP32C3/S3, USB CDC device can not function properly during sleep due to the lack of APB clock. Therefore.
- *       `rtc_clk_cpu_freq_set_xtal` will always disable BBPLL, no matter whether BBPLL has any consumer.
- *       On ESP32C6/H2, USB CDC device can maintain the minimum connection with the host during sleep, so
- *       `rtc_clk_cpu_freq_set_xtal` will check for BBPLL consumers, and keep BBPLL if USB Serial/JTAG is in use.
  */
 void rtc_clk_bbpll_add_consumer(void);
 
diff --git a/components/esp_hw_support/include/esp_private/sleep_retention.h b/components/esp_hw_support/include/esp_private/sleep_retention.h
index 076373c8f4f..5b4e95e3382 100644
--- a/components/esp_hw_support/include/esp_private/sleep_retention.h
+++ b/components/esp_hw_support/include/esp_private/sleep_retention.h
@@ -59,6 +59,11 @@ typedef enum {
  */
 esp_err_t sleep_retention_entries_create(const sleep_retention_entries_config_t retent[], int num, regdma_link_priority_t priority, sleep_retention_module_t module);
 
+/**
+ * @brief Dump the initialization status of all modules.
+*/
+void sleep_retention_dump_modules(FILE *out);
+
 /**
  * @brief Dump all runtime sleep retention linked lists
  */
@@ -139,6 +144,23 @@ esp_err_t sleep_retention_module_allocate(sleep_retention_module_t module);
  */
 esp_err_t sleep_retention_module_free(sleep_retention_module_t module);
 
+/**
+ * @brief Force take the power lock so that during sleep the power domain won't be powered off.
+ *
+ * @return
+ *      - ESP_OK if success
+ *      - other value when the internal `sleep_retention_module_init` fails.
+*/
+esp_err_t sleep_retention_power_lock_acquire(void);
+
+/**
+ * @brief Release the power lock so that the peripherals' power domain can be powered off.
+ *        Please note that there is an internal reference counter and the power domain will be kept on until same number
+ *        of `sleep_retention_power_lock_release` is called as `sleep_retention_power_lock_acquire`.
+ * @return always ESP_OK
+*/
+esp_err_t sleep_retention_power_lock_release(void);
+
 /**
  * @brief Get all initialized modules that require sleep retention
  *
diff --git a/components/esp_hw_support/include/esp_sleep.h b/components/esp_hw_support/include/esp_sleep.h
index de25aeb2683..8efa3d78bf5 100644
--- a/components/esp_hw_support/include/esp_sleep.h
+++ b/components/esp_hw_support/include/esp_sleep.h
@@ -9,7 +9,7 @@
 #include <stdint.h>
 #include "esp_err.h"
 
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 #include "hal/gpio_types.h"
 
 #include "soc/soc_caps.h"
@@ -118,6 +118,7 @@ typedef enum {
     ESP_SLEEP_WAKEUP_COCPU,             //!< Wakeup caused by COCPU int
     ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG,   //!< Wakeup caused by COCPU crash
     ESP_SLEEP_WAKEUP_BT,           //!< Wakeup caused by BT (light sleep only)
+    ESP_SLEEP_WAKEUP_VAD,          //!< Wakeup caused by VAD
 } esp_sleep_source_t;
 
 /**
@@ -179,6 +180,16 @@ esp_err_t esp_sleep_enable_ulp_wakeup(void);
  */
 esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
 
+#if SOC_LP_VAD_SUPPORTED
+/**
+ * @brief Enable wakeup by VAD
+ *
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t esp_sleep_enable_vad_wakeup(void);
+#endif
+
 #if SOC_TOUCH_SENSOR_SUPPORTED
 /**
  * @brief Enable wakeup by touch sensor
@@ -759,41 +770,6 @@ esp_err_t esp_sleep_cpu_retention_init(void);
 esp_err_t esp_sleep_cpu_retention_deinit(void);
 #endif // ESP_SLEEP_POWER_DOWN_CPU
 
-#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
-/**
- * @brief Backup or restore the MMU when the top domain is powered down.
- * @param backup_or_restore decide to backup mmu or restore mmu
- */
-void esp_sleep_mmu_retention(bool backup_or_restore);
-
-/**
- * @brief Mmu backup initialize when power down TOP domain
- *
- * @return
- *      - ESP_OK on success
- *      - ESP_ERR_NO_MEM not enough retention memory
- */
-esp_err_t esp_sleep_mmu_retention_init(void);
-
-/**
- * @brief Mmu backup de-initialize when power down TOP domain
- *
- * @return
- *      - ESP_OK on success
- *
- * Release system retention memory.
- */
-esp_err_t esp_sleep_mmu_retention_deinit(void);
-
-/**
- * @brief Whether to allow the top domain to be powered off due to mmu domain requiring retention.
- *
- * In light sleep mode, only when the system can provide enough memory
- * for mmu retention, the top power domain can be powered off.
- */
-bool mmu_domain_pd_allowed(void);
-#endif
-
 /**
  * @brief Configure to isolate all GPIO pins in sleep state
  */
diff --git a/components/esp_hw_support/ldo/esp_ldo_regulator.c b/components/esp_hw_support/ldo/esp_ldo_regulator.c
index 2a59dd6de57..63595dbbf2f 100644
--- a/components/esp_hw_support/ldo/esp_ldo_regulator.c
+++ b/components/esp_hw_support/ldo/esp_ldo_regulator.c
@@ -24,6 +24,7 @@ typedef struct ldo_regulator_channel_t {
     int ref_cnt;
     struct {
         uint32_t adjustable : 1;
+        uint32_t bypass : 1;
     } flags;
 } ldo_regulator_channel_t;
 
@@ -83,7 +84,7 @@ esp_err_t esp_ldo_acquire_channel(const esp_ldo_channel_config_t *config, esp_ld
             uint8_t mul = 0;
             // calculate the dref and mul
             ldo_ll_voltage_to_dref_mul(unit_id, config->voltage_mv, &dref, &mul);
-            ldo_ll_adjust_voltage(unit_id, dref, mul);
+            ldo_ll_adjust_voltage(unit_id, dref, mul, config->flags.bypass);
             // set the ldo unit owner ship
             ldo_ll_set_owner(unit_id, config->flags.owned_by_hw ? LDO_LL_UNIT_OWNER_HW : LDO_LL_UNIT_OWNER_SW);
             // suppress voltage ripple
@@ -94,6 +95,7 @@ esp_err_t esp_ldo_acquire_channel(const esp_ldo_channel_config_t *config, esp_ld
         channel->ref_cnt++;
         channel->voltage_mv = config->voltage_mv;
         channel->flags.adjustable = config->flags.adjustable;
+        channel->flags.bypass = config->flags.bypass;
         channel->chan_id = config->chan_id;
     }
     portEXIT_CRITICAL(&s_spinlock);
@@ -155,7 +157,7 @@ esp_err_t esp_ldo_channel_adjust_voltage(esp_ldo_channel_handle_t chan, int volt
     uint8_t mul = 0;
     // calculate the dref and mul
     ldo_ll_voltage_to_dref_mul(unit_id, voltage_mv, &dref, &mul);
-    ldo_ll_adjust_voltage(unit_id, dref, mul);
+    ldo_ll_adjust_voltage(unit_id, dref, mul, chan->flags.bypass);
 
     return ESP_OK;
 }
diff --git a/components/esp_hw_support/ldo/include/esp_ldo_regulator.h b/components/esp_hw_support/ldo/include/esp_ldo_regulator.h
index 868166acd5c..3bf31507cd1 100644
--- a/components/esp_hw_support/ldo/include/esp_ldo_regulator.h
+++ b/components/esp_hw_support/ldo/include/esp_ldo_regulator.h
@@ -30,7 +30,8 @@ typedef struct {
     /// Extra flags of a LDO channel
     struct ldo_extra_flags {
         uint32_t adjustable : 1; /*!< Whether the LDO channel is adjustable, and the voltage can be updated by `esp_ldo_channel_adjust_voltage` */
-        uint32_t owned_by_hw: 1; /*!< If the LDO channel is owned by hardware, then software configurations will be overridden by hardware */
+        uint32_t owned_by_hw: 1; /*!< If the LDO channel is owned by hardware, then software configurations can be overridden by hardware (e.g. eFuse) */
+        uint32_t bypass: 1;      /*!< Whether to bypass the regulator, i.e., the input voltage is sourced directly to the output */
     } flags; /*!< Flags for the LDO channel */
 } esp_ldo_channel_config_t;
 
diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
index d4a682ea3ef..7802c57ffeb 100644
--- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
+++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
@@ -10,6 +10,8 @@
 #include "modem/modem_syscon_reg.h"
 #include "modem/modem_lpcon_reg.h"
 #include "soc/i2c_ana_mst_reg.h"
+#include "soc/chip_revision.h"
+#include "hal/efuse_hal.h"
 
 static const char *TAG = "sleep_clock";
 
@@ -35,7 +37,6 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
 #if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
     uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
     if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
-
         /* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
          * the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
          * command memory */
@@ -52,6 +53,21 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
     }
 #endif
 
+#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
+        /* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG (it's
+         * located in TOP domain) is used to fix the issue where the modem
+         * module fails to transmit and receive packets due to the loss of The
+         * modem root clock caused by automatic clock gating during soc root
+         * clock source switching. For detailed information, refer to IDF-11064 */
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
+        const static sleep_retention_entries_config_t rootclk_workaround[] = {
+            [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(9), PCR_FPGA_DEBUG_REG, PCR_FPGA_DEBUG_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1) }
+        };
+        err = sleep_retention_entries_create(rootclk_workaround, ARRAY_SIZE(rootclk_workaround), 1, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
+        ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem root clock workaround, 1 level priority");
+    }
+#endif
+
     ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
     return ESP_OK;
 }
diff --git a/components/esp_hw_support/lowpower/port/esp32c5/sleep_mmu.c b/components/esp_hw_support/lowpower/port/esp32c5/sleep_mmu.c
index ac2f45da7ba..3a1cad17284 100644
--- a/components/esp_hw_support/lowpower/port/esp32c5/sleep_mmu.c
+++ b/components/esp_hw_support/lowpower/port/esp32c5/sleep_mmu.c
@@ -112,7 +112,7 @@ IRAM_ATTR void esp_sleep_mmu_retention(bool backup_or_restore)
     }
 }
 
-static esp_err_t esp_sleep_mmu_retention_deinit_impl(void)
+static esp_err_t esp_sleep_mmu_retention_deinit(void)
 {
     if (s_mmu_retention.retent.mmu_table_frame) {
         heap_caps_free((void *)s_mmu_retention.retent.mmu_table_frame);
@@ -121,7 +121,7 @@ static esp_err_t esp_sleep_mmu_retention_deinit_impl(void)
     return ESP_OK;
 }
 
-static esp_err_t esp_sleep_mmu_retention_init_impl(void)
+static esp_err_t esp_sleep_mmu_retention_init(void)
 {
     if (s_mmu_retention.retent.mmu_table_frame == NULL) {
         void *frame = mmu_domain_mmu_table_sleep_frame_alloc_and_init();
@@ -136,16 +136,6 @@ static esp_err_t esp_sleep_mmu_retention_init_impl(void)
     return ESP_ERR_NO_MEM;
 }
 
-esp_err_t esp_sleep_mmu_retention_init(void)
-{
-    return esp_sleep_mmu_retention_init_impl();
-}
-
-esp_err_t esp_sleep_mmu_retention_deinit(void)
-{
-    return esp_sleep_mmu_retention_deinit_impl();
-}
-
 bool mmu_domain_pd_allowed(void)
 {
     return (s_mmu_retention.retent.mmu_table_frame != NULL);
diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c
index ac2f45da7ba..3a1cad17284 100644
--- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c
+++ b/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c
@@ -112,7 +112,7 @@ IRAM_ATTR void esp_sleep_mmu_retention(bool backup_or_restore)
     }
 }
 
-static esp_err_t esp_sleep_mmu_retention_deinit_impl(void)
+static esp_err_t esp_sleep_mmu_retention_deinit(void)
 {
     if (s_mmu_retention.retent.mmu_table_frame) {
         heap_caps_free((void *)s_mmu_retention.retent.mmu_table_frame);
@@ -121,7 +121,7 @@ static esp_err_t esp_sleep_mmu_retention_deinit_impl(void)
     return ESP_OK;
 }
 
-static esp_err_t esp_sleep_mmu_retention_init_impl(void)
+static esp_err_t esp_sleep_mmu_retention_init(void)
 {
     if (s_mmu_retention.retent.mmu_table_frame == NULL) {
         void *frame = mmu_domain_mmu_table_sleep_frame_alloc_and_init();
@@ -136,16 +136,6 @@ static esp_err_t esp_sleep_mmu_retention_init_impl(void)
     return ESP_ERR_NO_MEM;
 }
 
-esp_err_t esp_sleep_mmu_retention_init(void)
-{
-    return esp_sleep_mmu_retention_init_impl();
-}
-
-esp_err_t esp_sleep_mmu_retention_deinit(void)
-{
-    return esp_sleep_mmu_retention_deinit_impl();
-}
-
 bool mmu_domain_pd_allowed(void)
 {
     return (s_mmu_retention.retent.mmu_table_frame != NULL);
diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c
index 63066d6302f..285e88a0151 100644
--- a/components/esp_hw_support/modem_clock.c
+++ b/components/esp_hw_support/modem_clock.c
@@ -18,6 +18,7 @@
 #include "hal/efuse_hal.h"
 #include "hal/clk_tree_ll.h"
 #include "hal/regi2c_ctrl_ll.h"
+#include "esp_private/regi2c_ctrl.h"
 
 // Please define the frequently called modules in the low bit,
 // which will improve the execution efficiency
@@ -108,7 +109,7 @@ static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, boo
 
 static void IRAM_ATTR modem_clock_modem_adc_common_fe_configure(modem_clock_context_t *ctx, bool enable)
 {
-    modem_clock_hal_enable_modem_adc_common_fe_clock(ctx->hal, enable);
+    modem_clock_hal_enable_modem_common_fe_clock(ctx->hal, enable);
 }
 
 static void IRAM_ATTR modem_clock_modem_private_fe_configure(modem_clock_context_t *ctx, bool enable)
@@ -118,7 +119,11 @@ static void IRAM_ATTR modem_clock_modem_private_fe_configure(modem_clock_context
 
 static void IRAM_ATTR modem_clock_i2c_master_configure(modem_clock_context_t *ctx, bool enable)
 {
-    regi2c_ctrl_ll_master_enable_clock(enable);
+    if (enable) {
+        ANALOG_CLOCK_ENABLE();
+    } else {
+        ANALOG_CLOCK_DISABLE();
+    }
 }
 
 static void IRAM_ATTR modem_clock_etm_configure(modem_clock_context_t *ctx, bool enable)
diff --git a/components/esp_hw_support/periph_ctrl.c b/components/esp_hw_support/periph_ctrl.c
index 0ce975e3081..29152555d9a 100644
--- a/components/esp_hw_support/periph_ctrl.c
+++ b/components/esp_hw_support/periph_ctrl.c
@@ -31,25 +31,25 @@ IRAM_ATTR void periph_rcc_exit(void)
     portEXIT_CRITICAL_SAFE(&periph_spinlock);
 }
 
-uint8_t periph_rcc_acquire_enter(periph_module_t periph)
+IRAM_ATTR uint8_t periph_rcc_acquire_enter(periph_module_t periph)
 {
     periph_rcc_enter();
     return ref_counts[periph];
 }
 
-void periph_rcc_acquire_exit(periph_module_t periph, uint8_t ref_count)
+IRAM_ATTR void periph_rcc_acquire_exit(periph_module_t periph, uint8_t ref_count)
 {
     ref_counts[periph] = ++ref_count;
     periph_rcc_exit();
 }
 
-uint8_t periph_rcc_release_enter(periph_module_t periph)
+IRAM_ATTR uint8_t periph_rcc_release_enter(periph_module_t periph)
 {
     periph_rcc_enter();
     return ref_counts[periph] - 1;
 }
 
-void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count)
+IRAM_ATTR void periph_rcc_release_exit(periph_module_t periph, uint8_t ref_count)
 {
     ref_counts[periph] = ref_count;
     periph_rcc_exit();
diff --git a/components/esp_hw_support/port/esp32/include/soc/rtc.h b/components/esp_hw_support/port/esp32/include/soc/rtc.h
index 22f7cfe1574..0c0afc20dd5 100644
--- a/components/esp_hw_support/port/esp32/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32/include/soc/rtc.h
@@ -726,7 +726,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 4
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D4  //!< Main XTAL, divided by 4
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 8 MHz RC oscillator
 
 /**
diff --git a/components/esp_hw_support/port/esp32c2/include/soc/rtc.h b/components/esp_hw_support/port/esp32c2/include/soc/rtc.h
index 9f8d412f59f..40f1c8a6372 100644
--- a/components/esp_hw_support/port/esp32c2/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c2/include/soc/rtc.h
@@ -715,7 +715,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
 
 /**
diff --git a/components/esp_hw_support/port/esp32c3/include/soc/rtc.h b/components/esp_hw_support/port/esp32c3/include/soc/rtc.h
index 58a26dd41e4..e18fda176eb 100644
--- a/components/esp_hw_support/port/esp32c3/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c3/include/soc/rtc.h
@@ -784,7 +784,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
 
 /**
diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
index 92a2c4f5c25..a11d201f20c 100644
--- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h
@@ -307,8 +307,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
  * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
  * Assumes that XTAL frequency has been determined — don't call in startup code.
  *
- * @note On ESP32C5, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
- * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
+ * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose.
+ * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use,
+ * if so, then BBPLL will not be turned off.
  */
 void rtc_clk_cpu_freq_set_xtal(void);
 
diff --git a/components/esp_hw_support/port/esp32c5/pmu_param.c b/components/esp_hw_support/port/esp32c5/pmu_param.c
index e676f8c478d..19888d4828a 100644
--- a/components/esp_hw_support/port/esp32c5/pmu_param.c
+++ b/components/esp_hw_support/port/esp32c5/pmu_param.c
@@ -291,18 +291,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2active_backup_en      = 0, \
         .hp_modem2active_backup_en      = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_GDMA)      | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() {   \
@@ -314,17 +303,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2modem_backup_mode     = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
         .hp_sleep2modem_backup_en       = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() {   \
@@ -341,17 +320,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_modem2sleep_backup_en       = 0, \
         .hp_active2sleep_backup_en      = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
@@ -367,23 +336,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
 
 
 /** LP system default parameter */
-
-#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (1)
-#else
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (0)
-#endif
-
-#define PMU_LP_DEFAULT_XPD_RC32K (0)
-
 #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
     .dig_power = {              \
         .mem_dslp       = 0,    \
         .peri_pd_en     = 0,    \
     }, \
     .clk_power = {              \
-        .xpd_xtal32k    = PMU_SLOW_CLK_USE_EXT_XTAL,    \
-        .xpd_rc32k      = PMU_LP_DEFAULT_XPD_RC32K,    \
+        .xpd_xtal32k    = 1,    \
+        .xpd_rc32k      = 0,    \
         .xpd_fosc       = 1,    \
         .pd_osc         = 0     \
     } \
diff --git a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
index 8e9909749b8..bbcc0c8e70f 100644
--- a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
@@ -87,7 +87,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo
 
 typedef struct {
     pmu_hp_backup_reg_t     retention;
-    uint32_t                backup_clk;
+    uint32_t                backup_clk; // icg_func
 } pmu_hp_system_retention_param_t;
 
 const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c
index e3d1052c4b0..31c1452130c 100644
--- a/components/esp_hw_support/port/esp32c5/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c
@@ -22,10 +22,7 @@
 #include "esp_private/sleep_event.h"
 #include "hal/efuse_hal.h"
 #include "soc/chip_revision.h"
-
-#if SOC_MODEM_CLOCK_SUPPORTED
-#include "esp_private/esp_modem_clock.h"
-#endif
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -133,27 +130,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#if SOC_MODEM_CLOCK_SUPPORTED
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -162,7 +145,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 
@@ -268,7 +252,8 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
     } else if (freq_mhz == 80) {
         real_freq_mhz = freq_mhz;
         if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
-            // ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M
+            /* ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M
+             * For detailed information, refer to IDF-11064 */
             source = SOC_CPU_CLK_SRC_PLL_F240M;
             source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
             divider = 3;
@@ -383,10 +368,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
 void rtc_clk_cpu_freq_set_xtal(void)
 {
     rtc_clk_cpu_set_to_default_config();
-    // We don't turn off the bbpll if some consumers depend on bbpll
-    if (!s_bbpll_digi_consumers_ref_count) {
-        rtc_clk_bbpll_disable();
-    }
+    rtc_clk_bbpll_disable();
 }
 
 void rtc_clk_cpu_set_to_default_config(void)
@@ -394,6 +376,7 @@ void rtc_clk_cpu_set_to_default_config(void)
     int freq_mhz = (int)rtc_clk_xtal_freq_get();
 
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
+    s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c
index 8d5c33800b2..18cb9a28309 100644
--- a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c
@@ -79,6 +79,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
+
     uint32_t hp_cali_dbias = get_act_hp_dbias();
     uint32_t lp_cali_dbias = get_act_lp_dbias();
 
diff --git a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
index 8d508d5df39..ae0a4ea43b3 100644
--- a/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c6/include/soc/rtc.h
@@ -338,8 +338,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
  * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
  * Assumes that XTAL frequency has been determined — don't call in startup code.
  *
- * @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
- * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
+ * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose.
+ * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use,
+ * if so, then BBPLL will not be turned off.
  */
 void rtc_clk_cpu_freq_set_xtal(void);
 
@@ -464,7 +465,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
 
 /**
diff --git a/components/esp_hw_support/port/esp32c6/ocode_init.c b/components/esp_hw_support/port/esp32c6/ocode_init.c
index 04743d7d6a7..dd26da07c05 100644
--- a/components/esp_hw_support/port/esp32c6/ocode_init.c
+++ b/components/esp_hw_support/port/esp32c6/ocode_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,10 +11,9 @@
 #include "soc/regi2c_lp_bias.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
-#include "regi2c_ctrl.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_hw_log.h"
 
-
 static const char *TAG = "ocode_init";
 
 static void set_ocode_by_efuse(int ocode_scheme_ver)
@@ -57,6 +56,7 @@ static void calibrate_ocode(void)
     rtc_clk_cpu_freq_get_config(&old_config);
     rtc_clk_cpu_freq_set_xtal();
 
+    ANALOG_CLOCK_ENABLE();
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
     bool odone_flag = 0;
@@ -73,6 +73,8 @@ static void calibrate_ocode(void)
             break;
         }
     }
+    ANALOG_CLOCK_DISABLE();
+
     rtc_clk_cpu_freq_set_config(&old_config);
 }
 
diff --git a/components/esp_hw_support/port/esp32c6/pmu_init.c b/components/esp_hw_support/port/esp32c6/pmu_init.c
index e64111e19b3..d961d995938 100644
--- a/components/esp_hw_support/port/esp32c6/pmu_init.c
+++ b/components/esp_hw_support/port/esp32c6/pmu_init.c
@@ -211,6 +211,7 @@ void pmu_init(void)
     /* Peripheral reg i2c power up */
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
+
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_RTC_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_ENIF_DIG_DREG, 1);
     REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
diff --git a/components/esp_hw_support/port/esp32c6/pmu_param.c b/components/esp_hw_support/port/esp32c6/pmu_param.c
index 044c300688e..6b24a4c4d90 100644
--- a/components/esp_hw_support/port/esp32c6/pmu_param.c
+++ b/components/esp_hw_support/port/esp32c6/pmu_param.c
@@ -291,18 +291,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2active_backup_en      = 0, \
         .hp_modem2active_backup_en      = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_GDMA)      | \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() {   \
@@ -314,17 +303,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2modem_backup_mode     = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
         .hp_sleep2modem_backup_en       = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() {   \
@@ -341,18 +320,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_modem2sleep_backup_en       = 0, \
         .hp_active2sleep_backup_en      = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_GDMA)      | \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
@@ -368,21 +336,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
 
 
 /** LP system default parameter */
-
-#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (1)
-#else
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (0)
-#endif
-
 #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
     .dig_power = {              \
         .mem_dslp       = 0,    \
         .peri_pd_en     = 0,    \
     }, \
     .clk_power = {              \
-        .xpd_xtal32k    = PMU_SLOW_CLK_USE_EXT_XTAL,    \
-        .xpd_rc32k      = 0,    \
+        .xpd_xtal32k    = 1,    \
+        .xpd_rc32k      = 1,    \
         .xpd_fosc       = 1,    \
         .pd_osc         = 0     \
     } \
diff --git a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
index fdef78b3300..155c3e810f4 100644
--- a/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
@@ -92,7 +92,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo
 
 typedef struct {
     pmu_hp_backup_reg_t     retention;
-    uint32_t                backup_clk;
+    uint32_t                backup_clk; // icg_func
 } pmu_hp_system_retention_param_t;
 
 const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
diff --git a/components/esp_hw_support/port/esp32c6/rtc_clk.c b/components/esp_hw_support/port/esp32c6/rtc_clk.c
index 521e2fd03f5..93aa57d9407 100644
--- a/components/esp_hw_support/port/esp32c6/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c6/rtc_clk.c
@@ -20,7 +20,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-#include "esp_private/esp_modem_clock.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -139,25 +139,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -166,7 +154,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 
@@ -333,10 +322,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
 void rtc_clk_cpu_freq_set_xtal(void)
 {
     rtc_clk_cpu_set_to_default_config();
-    // We don't turn off the bbpll if some consumers depend on bbpll
-    if (!s_bbpll_digi_consumers_ref_count) {
-        rtc_clk_bbpll_disable();
-    }
+    rtc_clk_bbpll_disable();
 }
 
 void rtc_clk_cpu_set_to_default_config(void)
@@ -344,6 +330,7 @@ void rtc_clk_cpu_set_to_default_config(void)
     int freq_mhz = (int)rtc_clk_xtal_freq_get();
 
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
+    s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
diff --git a/components/esp_hw_support/port/esp32c61/CMakeLists.txt b/components/esp_hw_support/port/esp32c61/CMakeLists.txt
index 0e720dc0291..ea0e988a9d0 100644
--- a/components/esp_hw_support/port/esp32c61/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32c61/CMakeLists.txt
@@ -17,13 +17,6 @@ if(NOT BOOTLOADER_BUILD)
 
 endif()
 
-# TODO: [ESP32C61] IDF-9304
-if(CONFIG_IDF_TARGET_ESP32C61)
-    list(REMOVE_ITEM srcs
-        "sar_periph_ctrl.c"
-    )
-endif()
-
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
diff --git a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c
index 78352f59f3e..7915de98ec5 100644
--- a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c
@@ -33,6 +33,9 @@ uint32_t *freq_value)
     case SOC_MOD_CLK_PLL_F80M:
         clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;
         break;
+    case SOC_MOD_CLK_PLL_F120M:
+        clk_src_freq = CLK_LL_PLL_120M_FREQ_MHZ * MHZ;
+        break;
     case SOC_MOD_CLK_PLL_F160M:
         clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
         break;
diff --git a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
index 12c15bc101d..b0413273398 100644
--- a/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32c61/include/soc/rtc.h
@@ -307,8 +307,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
  * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
  * Assumes that XTAL frequency has been determined — don't call in startup code.
  *
- * @note On ESP32C61, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
- * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
+ * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose.
+ * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use,
+ * if so, then BBPLL will not be turned off.
  */
 void rtc_clk_cpu_freq_set_xtal(void);
 
diff --git a/components/esp_hw_support/port/esp32c61/ocode_init.c b/components/esp_hw_support/port/esp32c61/ocode_init.c
index bb25cce95cb..3ccc5077076 100644
--- a/components/esp_hw_support/port/esp32c61/ocode_init.c
+++ b/components/esp_hw_support/port/esp32c61/ocode_init.c
@@ -11,7 +11,7 @@
 #include "soc/regi2c_lp_bias.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
-#include "regi2c_ctrl.h"
+#include "esp_private/regi2c_ctrl.h"
 #include "esp_hw_log.h"
 
 // TODO: IDF-9303
@@ -58,6 +58,7 @@ static void calibrate_ocode(void)
     rtc_clk_cpu_freq_get_config(&old_config);
     rtc_clk_cpu_freq_set_xtal();
 
+    ANALOG_CLOCK_ENABLE();
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
     REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
     bool odone_flag = 0;
@@ -74,6 +75,8 @@ static void calibrate_ocode(void)
             break;
         }
     }
+    ANALOG_CLOCK_DISABLE();
+
     rtc_clk_cpu_freq_set_config(&old_config);
 }
 
diff --git a/components/esp_hw_support/port/esp32c61/pmu_param.c b/components/esp_hw_support/port/esp32c61/pmu_param.c
index 37105bef538..33af14a9f2e 100644
--- a/components/esp_hw_support/port/esp32c61/pmu_param.c
+++ b/components/esp_hw_support/port/esp32c61/pmu_param.c
@@ -290,18 +290,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2active_backup_en      = 0, \
         .hp_modem2active_backup_en      = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_GDMA)      | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() {   \
@@ -313,17 +302,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2modem_backup_mode     = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
         .hp_sleep2modem_backup_en       = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() {   \
@@ -340,17 +319,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_modem2sleep_backup_en       = 0, \
         .hp_active2sleep_backup_en      = 0, \
     }, \
-    .backup_clk = (                       \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
-        BIT(PMU_ICG_FUNC_ENA_TG0)       | \
-        BIT(PMU_ICG_FUNC_ENA_TG1)       | \
-        BIT(PMU_ICG_FUNC_ENA_HPBUS)     | \
-        BIT(PMU_ICG_FUNC_ENA_MSPI)      | \
-        BIT(PMU_ICG_FUNC_ENA_IOMUX)     | \
-        BIT(PMU_ICG_FUNC_ENA_SPI2)      | \
-        BIT(PMU_ICG_FUNC_ENA_UART0)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSTIMER)    \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
@@ -366,23 +335,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
 
 
 /** LP system default parameter */
-
-#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (1)
-#else
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (0)
-#endif
-
-#define PMU_LP_DEFAULT_XPD_RC32K (0)
-
 #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
     .dig_power = {              \
         .mem_dslp       = 0,    \
         .peri_pd_en     = 0,    \
     }, \
     .clk_power = {              \
-        .xpd_xtal32k    = PMU_SLOW_CLK_USE_EXT_XTAL,    \
-        .xpd_rc32k      = PMU_LP_DEFAULT_XPD_RC32K,    \
+        .xpd_xtal32k    = 1,    \
+        .xpd_rc32k      = 0,    \
         .xpd_fosc       = 1,    \
         .pd_osc         = 0     \
     } \
diff --git a/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
index 80aaac61ee9..4a7516a4f93 100644
--- a/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
@@ -90,7 +90,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo
 
 typedef struct {
     pmu_hp_backup_reg_t     retention;
-    uint32_t                backup_clk;
+    uint32_t                backup_clk; // icg_func
 } pmu_hp_system_retention_param_t;
 
 const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
diff --git a/components/esp_hw_support/port/esp32c61/rtc_clk.c b/components/esp_hw_support/port/esp32c61/rtc_clk.c
index e46cdbe1c48..8a97e4d5317 100644
--- a/components/esp_hw_support/port/esp32c61/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32c61/rtc_clk.c
@@ -20,10 +20,7 @@
 #include "hal/gpio_ll.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-
-#if SOC_MODEM_CLOCK_SUPPORTED
-#include "esp_private/esp_modem_clock.h"
-#endif
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -131,27 +128,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#if SOC_MODEM_CLOCK_SUPPORTED
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-#endif  //SOC_MODEM_CLOCK_SUPPORTED
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -160,7 +143,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 
@@ -327,10 +311,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
 void rtc_clk_cpu_freq_set_xtal(void)
 {
     rtc_clk_cpu_set_to_default_config();
-    // We don't turn off the bbpll if some consumers depend on bbpll
-    if (!s_bbpll_digi_consumers_ref_count) {
-        rtc_clk_bbpll_disable();
-    }
+    rtc_clk_bbpll_disable();
 }
 
 void rtc_clk_cpu_set_to_default_config(void)
@@ -338,6 +319,7 @@ void rtc_clk_cpu_set_to_default_config(void)
     int freq_mhz = (int)rtc_clk_xtal_freq_get();
 
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
+    s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
diff --git a/components/esp_hw_support/port/esp32c61/sar_periph_ctrl.c b/components/esp_hw_support/port/esp32c61/sar_periph_ctrl.c
new file mode 100644
index 00000000000..ffdd973ed5e
--- /dev/null
+++ b/components/esp_hw_support/port/esp32c61/sar_periph_ctrl.c
@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent. This file
+ * provides a united control to these registers, as multiple
+ * components require these controls.
+ *
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ */
+
+#include "sdkconfig.h"
+#include "esp_log.h"
+#include "freertos/FreeRTOS.h"
+#include "esp_private/sar_periph_ctrl.h"
+#include "esp_private/esp_modem_clock.h"
+#include "hal/sar_ctrl_ll.h"
+
+static const char *TAG = "sar_periph_ctrl";
+extern portMUX_TYPE rtc_spinlock;
+
+void sar_periph_ctrl_init(void)
+{
+    sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
+
+    //Add other periph power control initialisation here
+}
+
+void sar_periph_ctrl_power_enable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_force_power_ctrl_from_pwdet(true);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+void sar_periph_ctrl_power_disable(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    sar_ctrl_ll_force_power_ctrl_from_pwdet(false);
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+/**
+ * This gets incremented when s_sar_power_acquire() is called,
+ * and decremented when s_sar_power_release() is called.
+ * PWDET is powered down when the value reaches zero.
+ * Should be modified within critical section.
+ */
+static int s_pwdet_power_on_cnt;
+
+static void s_sar_power_acquire(void)
+{
+    modem_clock_module_enable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt++;
+    if (s_pwdet_power_on_cnt == 1) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_ON);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+}
+
+static void s_sar_power_release(void)
+{
+    portENTER_CRITICAL_SAFE(&rtc_spinlock);
+    s_pwdet_power_on_cnt--;
+    if (s_pwdet_power_on_cnt < 0) {
+        portEXIT_CRITICAL(&rtc_spinlock);
+        ESP_LOGE(TAG, "%s called, but s_pwdet_power_on_cnt == 0", __func__);
+        abort();
+    } else if (s_pwdet_power_on_cnt == 0) {
+        sar_ctrl_ll_set_power_mode_from_pwdet(SAR_CTRL_LL_POWER_FSM);
+    }
+    portEXIT_CRITICAL_SAFE(&rtc_spinlock);
+    modem_clock_module_disable(PERIPH_MODEM_ADC_COMMON_FE_MODULE);
+}
+
+
+/*------------------------------------------------------------------------------
+* PWDET Power
+*----------------------------------------------------------------------------*/
+void sar_periph_ctrl_pwdet_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_pwdet_power_release(void)
+{
+    s_sar_power_release();
+}
+
+
+/*------------------------------------------------------------------------------
+* ADC Power
+*----------------------------------------------------------------------------*/
+void sar_periph_ctrl_adc_oneshot_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_adc_oneshot_power_release(void)
+{
+    s_sar_power_release();
+}
+
+void sar_periph_ctrl_adc_continuous_power_acquire(void)
+{
+    s_sar_power_acquire();
+}
+
+void sar_periph_ctrl_adc_continuous_power_release(void)
+{
+    s_sar_power_release();
+}
diff --git a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
index dfd1f96f019..9934431037b 100644
--- a/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32h2/include/soc/rtc.h
@@ -354,8 +354,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
  * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
  * Assumes that XTAL frequency has been determined — don't call in startup code.
  *
- * @note On ESP32H2, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
- * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
+ * @note This function always disables BBPLL after switching the CPU clock source to XTAL for power saving purpose.
+ * If this is unwanted, please use rtc_clk_cpu_freq_set_config. It helps to check whether USB Serial JTAG is in use,
+ * if so, then BBPLL will not be turned off.
  */
 void rtc_clk_cpu_freq_set_xtal(void);
 
@@ -461,7 +462,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 8 MHz RC oscillator
 
 /**
diff --git a/components/esp_hw_support/port/esp32h2/pmu_param.c b/components/esp_hw_support/port/esp32h2/pmu_param.c
index 036792a6faa..f9de2ca5aeb 100644
--- a/components/esp_hw_support/port/esp32h2/pmu_param.c
+++ b/components/esp_hw_support/port/esp32h2/pmu_param.c
@@ -290,18 +290,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2active_backup_en      = 0, \
         .hp_modem2active_backup_en      = 0, \
     }, \
-    .backup_clk = (                             \
-        BIT(PMU_ICG_FUNC_ENA_GDMA)              \
-        | BIT(PMU_ICG_FUNC_ENA_REGDMA)          \
-        | BIT(PMU_ICG_FUNC_ENA_TG0)             \
-        | BIT(PMU_ICG_FUNC_ENA_HPBUS)           \
-        | BIT(PMU_ICG_FUNC_ENA_MSPI)            \
-        | BIT(PMU_ICG_FUNC_ENA_IOMUX)           \
-        | BIT(PMU_ICG_FUNC_ENA_SPI2)            \
-        | BIT(PMU_ICG_FUNC_ENA_SEC)             \
-        | BIT(PMU_ICG_FUNC_ENA_PWM)             \
-        | BIT(PMU_ICG_FUNC_ENA_SYSTIMER)        \
-        | BIT(PMU_ICG_FUNC_ENA_UART0)),         \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() {   \
@@ -313,16 +302,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2modem_backup_mode     = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
         .hp_sleep2modem_backup_en       = 0, \
     }, \
-    .backup_clk = (BIT(PMU_ICG_FUNC_ENA_REGDMA) \
-        | BIT(PMU_ICG_FUNC_ENA_TG0)             \
-        | BIT(PMU_ICG_FUNC_ENA_HPBUS)           \
-        | BIT(PMU_ICG_FUNC_ENA_MSPI)            \
-        | BIT(PMU_ICG_FUNC_ENA_IOMUX)           \
-        | BIT(PMU_ICG_FUNC_ENA_SPI2)            \
-        | BIT(PMU_ICG_FUNC_ENA_SEC)            \
-        | BIT(PMU_ICG_FUNC_ENA_PWM)            \
-        | BIT(PMU_ICG_FUNC_ENA_SYSTIMER)        \
-        | BIT(PMU_ICG_FUNC_ENA_UART0)),         \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() {   \
@@ -339,18 +319,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_modem2sleep_backup_en       = 0, \
         .hp_active2sleep_backup_en      = 0, \
     }, \
-    .backup_clk = (                             \
-        BIT(PMU_ICG_FUNC_ENA_GDMA)              \
-        | BIT(PMU_ICG_FUNC_ENA_REGDMA)          \
-        | BIT(PMU_ICG_FUNC_ENA_TG0)             \
-        | BIT(PMU_ICG_FUNC_ENA_HPBUS)           \
-        | BIT(PMU_ICG_FUNC_ENA_MSPI)            \
-        | BIT(PMU_ICG_FUNC_ENA_IOMUX)           \
-        | BIT(PMU_ICG_FUNC_ENA_SPI2)            \
-        | BIT(PMU_ICG_FUNC_ENA_SEC)             \
-        | BIT(PMU_ICG_FUNC_ENA_PWM)             \
-        | BIT(PMU_ICG_FUNC_ENA_SYSTIMER)        \
-        | BIT(PMU_ICG_FUNC_ENA_UART0)),         \
+    .backup_clk = 0xffffffff,   \
 }
 
 const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
@@ -366,21 +335,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
 
 
 /** LP system default parameter */
-
-#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (1)
-#else
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (0)
-#endif
-
 #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
     .dig_power = {              \
         .mem_dslp       = 0,    \
         .peri_pd_en     = 0,    \
     }, \
     .clk_power = {              \
-        .xpd_xtal32k    = PMU_SLOW_CLK_USE_EXT_XTAL,    \
-        .xpd_rc32k      = 0,    \
+        .xpd_xtal32k    = 1,    \
+        .xpd_rc32k      = 1,    \
         .xpd_fosc       = 1,    \
         .pd_osc         = 0     \
     } \
diff --git a/components/esp_hw_support/port/esp32h2/pmu_sleep.c b/components/esp_hw_support/port/esp32h2/pmu_sleep.c
index ab32613ab59..60492aa4de1 100644
--- a/components/esp_hw_support/port/esp32h2/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32h2/pmu_sleep.c
@@ -20,6 +20,8 @@
 #include "hal/efuse_ll.h"
 #include "hal/efuse_hal.h"
 #include "esp_hw_log.h"
+#include "soc/regi2c_bias.h"
+#include "regi2c_ctrl.h"
 
 static __attribute__((unused)) const char *TAG = "pmu_sleep";
 
@@ -264,6 +266,8 @@ uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp
 bool pmu_sleep_finish(bool dslp)
 {
     (void)dslp;
+    // Restore registers lost during sleep
+    REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_0P8, 8);  // fix low temp issue, need to increase this internal voltage
     return pmu_ll_hp_is_sleep_reject(PMU_instance()->hal->dev);
 }
 
diff --git a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
index 58fbf97ff48..bb89da8b001 100644
--- a/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
@@ -85,7 +85,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
 
 typedef struct {
     pmu_hp_backup_reg_t     retention;
-    uint32_t                backup_clk;
+    uint32_t                backup_clk; // icg_func
 } pmu_hp_system_retention_param_t;
 
 const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
@@ -340,7 +340,7 @@ typedef struct {
     },                                                      \
     .lp_sys[PMU_MODE_LP_SLEEP] = {                          \
         .analog = {                                         \
-            .drv_b         = PMU_LP_DRVB_DEEPSLEEP,         \
+            .drv_b         = PMU_LP_DRVB_LIGHTSLEEP,        \
             .pd_cur        = PMU_PD_CUR_SLEEP_DEFAULT,      \
             .bias_sleep    = PMU_BIASSLP_SLEEP_DEFAULT,     \
             .slp_xpd       = PMU_LP_SLP_XPD_SLEEP_DEFAULT,  \
@@ -407,7 +407,7 @@ typedef struct {
 
 typedef struct pmu_sleep_machine_constant {
     struct {
-        uint16_t    min_slp_time_us;            /* Mininum sleep protection time (unit: microsecond) */
+        uint16_t    min_slp_time_us;            /* Minimum sleep protection time (unit: microsecond) */
         uint8_t     reserved0;
         uint16_t    reserved1;
         uint16_t    analog_wait_time_us;        /* LP LDO power up wait time (unit: microsecond) */
@@ -418,7 +418,7 @@ typedef struct pmu_sleep_machine_constant {
         uint16_t    power_up_wait_time_us;      /* (unit: microsecond) */
     } lp;
     struct {
-        uint16_t    min_slp_time_us;            /* Mininum sleep protection time (unit: microsecond) */
+        uint16_t    min_slp_time_us;            /* Minimum sleep protection time (unit: microsecond) */
         uint16_t    analog_wait_time_us;        /* HP LDO power up wait time (unit: microsecond) */
         uint16_t    power_supply_wait_time_us;  /* (unit: microsecond) */
         uint16_t    power_up_wait_time_us;      /* (unit: microsecond) */
diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c
index 0c6664fdce8..305dec5b1e4 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c
@@ -20,7 +20,7 @@
 #include "soc/io_mux_reg.h"
 #include "soc/lp_aon_reg.h"
 #include "esp_private/sleep_event.h"
-#include "esp_private/esp_modem_clock.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -155,25 +155,13 @@ static void rtc_clk_bbpll_enable(void)
     clk_ll_bbpll_enable();
 }
 
-static void rtc_clk_enable_i2c_ana_master_clock(bool enable)
-{
-#ifdef BOOTLOADER_BUILD
-    regi2c_ctrl_ll_master_enable_clock(enable);
-#else
-    if (enable) {
-        modem_clock_module_enable(PERIPH_ANA_I2C_MASTER_MODULE);
-    } else {
-        modem_clock_module_disable(PERIPH_ANA_I2C_MASTER_MODULE);
-    }
-#endif
-}
-
 static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
 {
     /* Digital part */
     clk_ll_bbpll_set_freq_mhz(pll_freq);
+
     /* Analog part */
-    rtc_clk_enable_i2c_ana_master_clock(true);
+    ANALOG_CLOCK_ENABLE();
     /* BBPLL CALIBRATION START */
     regi2c_ctrl_ll_bbpll_calibration_start();
     clk_ll_bbpll_set_config(pll_freq, xtal_freq);
@@ -182,7 +170,8 @@ static void rtc_clk_bbpll_configure(soc_xtal_freq_t xtal_freq, int pll_freq)
     esp_rom_delay_us(10);
     /* BBPLL CALIBRATION STOP */
     regi2c_ctrl_ll_bbpll_calibration_stop();
-    rtc_clk_enable_i2c_ana_master_clock(false);
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_pll_freq = pll_freq;
 }
 
@@ -393,10 +382,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
 void rtc_clk_cpu_freq_set_xtal(void)
 {
     rtc_clk_cpu_set_to_default_config();
-    // We don't turn off the bbpll if some consumers only depends on bbpll
-    if (!s_bbpll_digi_consumers_ref_count) {
-        rtc_clk_bbpll_disable();
-    }
+    rtc_clk_bbpll_disable();
 }
 
 void rtc_clk_cpu_set_to_default_config(void)
@@ -404,6 +390,7 @@ void rtc_clk_cpu_set_to_default_config(void)
     int freq_mhz = (int)rtc_clk_xtal_freq_get();
 
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
+    s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
 soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support
index fe31a3aebef..46f9a88f302 100644
--- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support
+++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support
@@ -13,12 +13,15 @@ choice ESP32P4_REV_MIN
         bool "Rev v0.0"
     config ESP32P4_REV_MIN_1
         bool "Rev v0.1"
+    config ESP32P4_REV_MIN_100
+        bool "Rev v1.0"
 endchoice
 
 config ESP32P4_REV_MIN_FULL
     int
     default 0 if ESP32P4_REV_MIN_0
     default 1 if ESP32P4_REV_MIN_1
+    default 100 if ESP32P4_REV_MIN_100
 
 config ESP_REV_MIN_FULL
     int
@@ -28,7 +31,7 @@ config ESP_REV_MIN_FULL
     # MAX Revision
     #
 
-    comment "Maximum Supported ESP32-P4 Revision (Rev v0.99)"
+    comment "Maximum Supported ESP32-P4 Revision (Rev v1.99)"
     # Maximum revision that IDF supports.
     # It can not be changed by user.
     # Only Espressif can change it when a new version will be supported in IDF.
@@ -36,7 +39,7 @@ config ESP_REV_MIN_FULL
 
 config ESP32P4_REV_MAX_FULL
     int
-    default 99
+    default 199
     # keep in sync the "Maximum Supported Revision" description with this value
 
 config ESP_REV_MAX_FULL
diff --git a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
index 880dff56f94..03b6377107d 100644
--- a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c
@@ -56,8 +56,9 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr
     case SOC_MOD_CLK_APLL:
         clk_src_freq = clk_hal_apll_get_freq_hz();
         break;
-    // case SOC_MOD_CLK_SDIO_PLL: TODO: IDF-8886
-    //     break;
+    case SOC_MOD_CLK_SDIO_PLL:
+        clk_src_freq = CLK_LL_PLL_SDIO_FREQ_MHZ * MHZ;
+        break;
     case SOC_MOD_CLK_RTC_SLOW:
         clk_src_freq = esp_clk_tree_lp_slow_get_freq_hz(precision);
         break;
diff --git a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
index 183f8a79fe6..43acaa253fa 100644
--- a/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32p4/include/soc/rtc.h
@@ -350,8 +350,8 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
  * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
  * Assumes that XTAL frequency has been determined — don't call in startup code.
  *
- * @note On ESP32C6, this function will check whether BBPLL can be disabled. If there is no consumer, then BBPLL will be
- * turned off. The behaviour is the same as using rtc_clk_cpu_freq_set_config to switch cpu clock source to XTAL.
+ * @note On ESP32P4, this function always disables CPLL after switching the CPU clock source to XTAL,
+ * since there is no peripheral relies on CPLL clock (except Flash/PSRAM if their clock source selects CPLL).
  */
 void rtc_clk_cpu_freq_set_xtal(void);
 
diff --git a/components/esp_hw_support/port/esp32p4/pmu_init.c b/components/esp_hw_support/port/esp32p4/pmu_init.c
index 92d67002fdf..ffebc6a0e22 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_init.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_init.c
@@ -9,8 +9,10 @@
 #include <esp_types.h>
 #include "sdkconfig.h"
 #include "esp_attr.h"
+#include "soc/chip_revision.h"
 #include "soc/soc.h"
 #include "soc/pmu_struct.h"
+#include "hal/efuse_hal.h"
 #include "hal/pmu_hal.h"
 #include "pmu_param.h"
 #include "esp_private/esp_pmu.h"
@@ -84,7 +86,9 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_pa
     pmu_ll_hp_set_bias_sleep_enable           (ctx->hal->dev, mode, anlg->bias.bias_sleep);
     pmu_ll_hp_set_regulator_sleep_memory_xpd  (ctx->hal->dev, mode, anlg->regulator0.slp_mem_xpd);
     pmu_ll_hp_set_regulator_sleep_logic_xpd   (ctx->hal->dev, mode, anlg->regulator0.slp_logic_xpd);
-    pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_mem_dbias);
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100) && (mode == PMU_MODE_HP_SLEEP)) {
+        pmu_ll_hp_enable_sleep_flash_ldo_channel(ctx->hal->dev, anlg->regulator0.xpd_0p1a);
+    }
     pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_logic_dbias);
     pmu_ll_hp_set_regulator_driver_bar        (ctx->hal->dev, mode, anlg->regulator1.drv_b);
 
diff --git a/components/esp_hw_support/port/esp32p4/pmu_param.c b/components/esp_hw_support/port/esp32p4/pmu_param.c
index 0905a1268a4..f9a410ec464 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_param.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_param.c
@@ -153,8 +153,8 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
         .dbias_init      = 1,   \
         .slp_mem_xpd     = 0,   \
         .slp_logic_xpd   = 0,   \
-        .slp_mem_dbias   = 0, \
-        .slp_logic_dbias = 0, \
+        .slp_mem_dbias   = 1, /* slp_mem_dbias bit[3] controls ext_ldo_1 xpd for rev1.0*/ \
+        .slp_logic_dbias = 0,   \
     }, \
     .regulator1 = {             \
         .drv_b           = 0x0 \
@@ -173,8 +173,8 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
     .regulator0 = {             \
         .slp_mem_xpd     = 0,   \
         .slp_logic_xpd   = 0,   \
-        .slp_mem_dbias   = 0, \
-        .slp_logic_dbias = 0, \
+        .slp_mem_dbias   = 1, /* slp_mem_dbias bit[3] controls ext_ldo_1 xpd for rev1.0*/ \
+        .slp_logic_dbias = 0,   \
     }, \
     .regulator1 = {             \
         .drv_b           = 0x0 \
@@ -208,18 +208,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2active_backup_en      = 0, \
         .hp_modem2active_backup_en      = 0, \
     }, \
-    .backup_clk = ( \
-        BIT(PMU_ICG_FUNC_ENA_L2MEM_MEM)     | \
-        BIT(PMU_ICG_FUNC_ENA_L2MEM_SYS)     | \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)        | \
-        BIT(PMU_ICG_FUNC_ENA_HP_CLKRST)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSREG_APB)    | \
-        BIT(PMU_ICG_FUNC_ENA_ICM_CPU)       | \
-        BIT(PMU_ICG_FUNC_ENA_ICM_APB)       | \
-        BIT(PMU_ICG_FUNC_ENA_ICM_SYS)       | \
-        BIT(PMU_ICG_FUNC_ENA_ICM_MEM)       | \
-        BIT(PMU_ICG_FUNC_ENA_INTRMTX_APB) \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 #define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() {   \
@@ -236,18 +225,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_modem2sleep_backup_en       = 0, \
         .hp_active2sleep_backup_en      = 0, \
     }, \
-    .backup_clk = ( \
-        BIT(PMU_ICG_FUNC_ENA_L2MEM_MEM)     | \
-        BIT(PMU_ICG_FUNC_ENA_L2MEM_SYS)     | \
-        BIT(PMU_ICG_FUNC_ENA_REGDMA)        | \
-        BIT(PMU_ICG_FUNC_ENA_HP_CLKRST)     | \
-        BIT(PMU_ICG_FUNC_ENA_SYSREG_APB)    | \
-        BIT(PMU_ICG_FUNC_ENA_ICM_CPU)       | \
-        BIT(PMU_ICG_FUNC_ENA_ICM_APB)       | \
-        BIT(PMU_ICG_FUNC_ENA_ICM_SYS)       | \
-        BIT(PMU_ICG_FUNC_ENA_ICM_MEM)       | \
-        BIT(PMU_ICG_FUNC_ENA_INTRMTX_APB) \
-    ) \
+    .backup_clk = 0xffffffff,   \
 }
 
 const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
@@ -263,13 +241,6 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
 
 
 /** LP system default parameter */
-
-#if CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (1)
-#else
-# define PMU_SLOW_CLK_USE_EXT_XTAL  (0)
-#endif
-
 #define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
     .dig_power = {              \
         .lp_pad_slp_sel = 0,    \
@@ -280,8 +251,8 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
     }, \
     .clk_power = {              \
         .xpd_lppll      = 0,    \
-        .xpd_xtal32k    = PMU_SLOW_CLK_USE_EXT_XTAL,    \
-        .xpd_rc32k      = 0,    \
+        .xpd_xtal32k    = 1,    \
+        .xpd_rc32k      = 1,    \
         .xpd_fosc       = 1,    \
         .pd_osc         = 0     \
     } \
diff --git a/components/esp_hw_support/port/esp32p4/pmu_sleep.c b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
index 97c112aa6b5..64ea630d323 100644
--- a/components/esp_hw_support/port/esp32p4/pmu_sleep.c
+++ b/components/esp_hw_support/port/esp32p4/pmu_sleep.c
@@ -29,11 +29,15 @@
 #include "hal/pmu_hal.h"
 #include "hal/psram_ctrlr_ll.h"
 #include "hal/lp_sys_ll.h"
+#include "hal/clk_gate_ll.h"
 #include "esp_private/esp_pmu.h"
 #include "pmu_param.h"
 #include "esp_rom_sys.h"
 #include "esp_rom_uart.h"
 #include "hal/efuse_hal.h"
+#if CONFIG_SPIRAM
+#include "hal/ldo_ll.h"
+#endif
 
 #define HP(state)   (PMU_MODE_HP_ ## state)
 #define LP(state)   (PMU_MODE_LP_ ## state)
@@ -154,6 +158,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         config->digital = digital_default;
 
         pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
+        analog_default.hp_sys.analog.xpd_0p1a = 0;
         config->analog = analog_default;
     } else {
         // Get light sleep digital_default
@@ -164,6 +169,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
 
 #if CONFIG_SPIRAM
+        // Adjust analog parameters to keep EXT_LDO PSRAM channel volt outputting during light-sleep.
         analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
         analog_default.lp_sys[PMU_MODE_LP_SLEEP].analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
 #endif
@@ -190,6 +196,11 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         analog_default.hp_sys.analog.dcm_vset = CONFIG_ESP_SLEEP_DCM_VSET_VAL_IN_SLEEP;
         analog_default.hp_sys.analog.dcm_mode = 1;
 #endif
+        if (sleep_flags & PMU_SLEEP_PD_VDDSDIO) {
+            analog_default.hp_sys.analog.xpd_0p1a = 0;
+        } else {
+            analog_default.hp_sys.analog.xpd_0p1a = 1;
+        }
         config->analog = analog_default;
     }
 
@@ -202,6 +213,10 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
         config->analog.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
     }
 
+    if (sleep_flags & RTC_SLEEP_LP_PERIPH_USE_XTAL) {
+        _clk_gate_ll_xtal_to_lp_periph_en(true);
+    }
+
     config->power = power_default;
     pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
     config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
@@ -239,7 +254,9 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con
     pmu_ll_hp_set_regulator_sleep_memory_xpd  (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_xpd);
     pmu_ll_hp_set_regulator_sleep_logic_xpd   (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_xpd);
     pmu_ll_hp_set_regulator_xpd               (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
-    pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_dbias);
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
+        pmu_ll_hp_enable_sleep_flash_ldo_channel(ctx->hal->dev, analog->hp_sys.analog.xpd_0p1a);
+    }
     pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_dbias);
     pmu_ll_hp_set_dbg_atten                   (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbg_atten);
     pmu_ll_hp_set_regulator_dbias             (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
@@ -351,6 +368,14 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
         rtc_clk_mpll_disable();
     }
 
+
+#if CONFIG_SPIRAM && CONFIG_ESP_LDO_RESERVE_PSRAM
+    // Disable PSRAM chip power supply
+    if (dslp) {
+        ldo_ll_enable(LDO_ID2UNIT(CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN), false);
+    }
+#endif
+
     /* Start entry into sleep mode */
     pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
 
@@ -359,6 +384,13 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
         ;
     }
 
+#if CONFIG_SPIRAM && CONFIG_ESP_LDO_RESERVE_PSRAM
+    // Enable PSRAM chip power supply after deepsleep request rejected
+    if (dslp) {
+        ldo_ll_enable(LDO_ID2UNIT(CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN), true);
+    }
+#endif
+
     return pmu_sleep_finish(dslp);
 }
 
diff --git a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
index 9c8be63ac55..4ad678bd334 100644
--- a/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
+++ b/components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
@@ -86,7 +86,7 @@ const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mo
 
 typedef struct {
     pmu_hp_backup_reg_t     retention;
-    uint32_t                backup_clk;
+    uint32_t                backup_clk; // icg_func
 } pmu_hp_system_retention_param_t;
 
 const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
@@ -173,7 +173,7 @@ typedef struct {
         uint32_t slp_mem_xpd    : 1;
         uint32_t slp_logic_xpd  : 1;
         uint32_t xpd            : 1;
-        uint32_t slp_mem_dbias  : 4;
+        uint32_t xpd_0p1a       : 1; // Should map to slp_mem_dbias bit[3] on hardware.
         uint32_t slp_logic_dbias: 4;
         uint32_t dbias          : 5;
     };
diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk.c b/components/esp_hw_support/port/esp32p4/rtc_clk.c
index aa3bfd96750..951beac9480 100644
--- a/components/esp_hw_support/port/esp32p4/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32p4/rtc_clk.c
@@ -21,6 +21,7 @@
 #include "hal/gpio_ll.h"
 #include "soc/io_mux_reg.h"
 #include "esp_private/sleep_event.h"
+#include "esp_private/regi2c_ctrl.h"
 
 static const char *TAG = "rtc_clk";
 
@@ -141,7 +142,9 @@ static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
 {
     /* Digital part */
     clk_ll_cpll_set_freq_mhz(cpll_freq);
+
     /* Analog part */
+    ANALOG_CLOCK_ENABLE();
     /* CPLL CALIBRATION START */
     regi2c_ctrl_ll_cpll_calibration_start();
     clk_ll_cpll_set_config(cpll_freq, xtal_freq);
@@ -150,6 +153,7 @@ static void rtc_clk_cpll_configure(soc_xtal_freq_t xtal_freq, int cpll_freq)
     esp_rom_delay_us(10); // wait for true stop
     /* CPLL CALIBRATION STOP */
     regi2c_ctrl_ll_cpll_calibration_stop();
+    ANALOG_CLOCK_DISABLE();
 
     s_cur_cpll_freq = cpll_freq;
 }
@@ -362,34 +366,42 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
     }
 }
 
-void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
+static uint32_t rtc_clk_hp_root_get_freq_mhz(soc_cpu_clk_src_t clk_src)
 {
-    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
-    uint32_t source_freq_mhz;
-    hal_utils_clk_div_t div = {0}; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
-    uint32_t freq_mhz;
-    clk_ll_cpu_get_divider(&div.integer, &div.numerator, &div.denominator);
-    if (div.denominator == 0) {
-        div.denominator = 1;
-        div.numerator = 0;
-    }
-    switch (source) {
-    case SOC_CPU_CLK_SRC_XTAL: {
+    uint32_t source_freq_mhz = 0;
+    switch (clk_src) {
+    case SOC_CPU_CLK_SRC_XTAL:
         source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
         break;
-    }
-    case SOC_CPU_CLK_SRC_CPLL: {
+    case SOC_CPU_CLK_SRC_CPLL:
         source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
         break;
-    }
     case SOC_CPU_CLK_SRC_RC_FAST:
         source_freq_mhz = 20;
         break;
     default:
-        ESP_HW_LOGE(TAG, "unsupported frequency configuration");
+        // Unknown HP_ROOT clock source
+        ESP_HW_LOGE(TAG, "Invalid HP_ROOT_CLK");
+        break;
+    }
+    return source_freq_mhz;
+}
+
+void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
+{
+    soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
+    uint32_t source_freq_mhz = rtc_clk_hp_root_get_freq_mhz(source);
+    if (source_freq_mhz == 0) {
+        // unsupported frequency configuration
         abort();
     }
-    freq_mhz = source_freq_mhz * div.denominator / (div.integer * div.denominator + div.numerator);
+    hal_utils_clk_div_t div = {0}; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
+    clk_ll_cpu_get_divider(&div.integer, &div.numerator, &div.denominator);
+    if (div.denominator == 0) {
+        div.denominator = 1;
+        div.numerator = 0;
+    }
+    uint32_t freq_mhz = source_freq_mhz * div.denominator / (div.integer * div.denominator + div.numerator);
     *out_config = (rtc_cpu_freq_config_t) {
         .source = source,
         .source_freq_mhz = source_freq_mhz,
@@ -426,6 +438,7 @@ void rtc_clk_cpu_set_to_default_config(void)
     int freq_mhz = (int)rtc_clk_xtal_freq_get();
 
     rtc_clk_cpu_freq_to_xtal(freq_mhz, 1, true);
+    s_cur_cpll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep
 }
 
 soc_xtal_freq_t rtc_clk_xtal_freq_get(void)
@@ -446,23 +459,7 @@ void rtc_clk_xtal_freq_update(soc_xtal_freq_t xtal_freq)
 uint32_t rtc_clk_apb_freq_get(void)
 {
     soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
-    uint32_t source_freq_mhz;
-    switch (source) {
-    case SOC_CPU_CLK_SRC_XTAL:
-        source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
-        break;
-    case SOC_CPU_CLK_SRC_CPLL:
-        source_freq_mhz = clk_ll_cpll_get_freq_mhz((uint32_t)rtc_clk_xtal_freq_get());
-        break;
-    case SOC_CPU_CLK_SRC_RC_FAST:
-        source_freq_mhz = 20;
-        break;
-    default:
-        // Unknown HP_ROOT clock source
-        source_freq_mhz = 0;
-        ESP_HW_LOGE(TAG, "Invalid HP_ROOT_CLK");
-        break;
-    }
+    uint32_t source_freq_mhz = rtc_clk_hp_root_get_freq_mhz(source);
     uint32_t integer, numerator, denominator;
     clk_ll_cpu_get_divider(&integer, &numerator, &denominator);
     if (denominator == 0) {
@@ -548,6 +545,7 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32
     clk_ll_apll_set_config(o_div, sdm0, sdm1, sdm2);
 
     /* calibration */
+    ANALOG_CLOCK_ENABLE();
     clk_ll_apll_set_calibration();
 
     /* wait for calibration end */
@@ -555,6 +553,7 @@ void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32
         /* use esp_rom_delay_us so the RTC bus doesn't get flooded */
         esp_rom_delay_us(1);
     }
+    ANALOG_CLOCK_DISABLE();
 }
 
 void rtc_dig_clk8m_enable(void)
@@ -589,6 +588,7 @@ TCM_IRAM_ATTR void rtc_clk_mpll_enable(void)
 void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
 {
     /* Analog part */
+    ANALOG_CLOCK_ENABLE();
     /* MPLL calibration start */
     regi2c_ctrl_ll_mpll_calibration_start();
     clk_ll_mpll_set_config(mpll_freq, xtal_freq);
@@ -596,6 +596,8 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq)
     while(!regi2c_ctrl_ll_mpll_calibration_is_done());
     /* MPLL calibration stop */
     regi2c_ctrl_ll_mpll_calibration_stop();
+    ANALOG_CLOCK_DISABLE();
+
     s_cur_mpll_freq = mpll_freq;
 }
 
diff --git a/components/esp_hw_support/port/esp32s2/include/soc/rtc.h b/components/esp_hw_support/port/esp32s2/include/soc/rtc.h
index 5a3dda48448..ca648bc7825 100644
--- a/components/esp_hw_support/port/esp32s2/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32s2/include/soc/rtc.h
@@ -864,7 +864,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 4
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D4  //!< Main XTAL, divided by 4
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 8 MHz RC oscillator
 
 /**
diff --git a/components/esp_hw_support/port/esp32s3/include/soc/rtc.h b/components/esp_hw_support/port/esp32s3/include/soc/rtc.h
index 27a4845f5f9..4f914d6e88f 100644
--- a/components/esp_hw_support/port/esp32s3/include/soc/rtc.h
+++ b/components/esp_hw_support/port/esp32s3/include/soc/rtc.h
@@ -842,7 +842,7 @@ typedef soc_rtc_slow_clk_src_t rtc_slow_freq_t;
  * @brief RTC FAST_CLK frequency values
  */
 typedef soc_rtc_fast_clk_src_t rtc_fast_freq_t;
-#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_DIV  //!< Main XTAL, divided by 2
+#define RTC_FAST_FREQ_XTALD4 SOC_RTC_FAST_CLK_SRC_XTAL_D2  //!< Main XTAL, divided by 2
 #define RTC_FAST_FREQ_8M SOC_RTC_FAST_CLK_SRC_RC_FAST       //!< Internal 17.5 MHz RC oscillator
 
 /**
diff --git a/components/esp_hw_support/port/esp_clk_tree_common.c b/components/esp_hw_support/port/esp_clk_tree_common.c
index 6a971e2468b..20012d49301 100644
--- a/components/esp_hw_support/port/esp_clk_tree_common.c
+++ b/components/esp_hw_support/port/esp_clk_tree_common.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -177,23 +177,23 @@ uint32_t esp_clk_tree_rc_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
 uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision)
 {
     switch (clk_ll_rtc_fast_get_src()) {
-    case SOC_RTC_FAST_CLK_SRC_XTAL_DIV:
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 //SOC_RTC_FAST_CLK_SRC_XTAL_D4
-        return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
-#elif CONFIG_IDF_TARGET_ESP32P4 //SOC_RTC_FAST_CLK_SRC_XTAL
-        return clk_hal_xtal_get_freq_mhz() * MHZ;
-#else //SOC_RTC_FAST_CLK_SRC_XTAL_D2
-        return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
-#endif
     case SOC_RTC_FAST_CLK_SRC_RC_FAST:
         return esp_clk_tree_rc_fast_get_freq_hz(precision) / clk_ll_rc_fast_get_divider();
 #if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
     case SOC_RTC_FAST_CLK_SRC_LP_PLL:
         return clk_ll_lp_pll_get_freq_mhz() * MHZ;
 #endif
-#if SOC_CLK_LP_FAST_SUPPORT_XTAL && !CONFIG_IDF_TARGET_ESP32P4 // On P4 SOC_RTC_FAST_CLK_SRC_XTAL is an alias for SOC_RTC_FAST_CLK_SRC_XTAL_DIV
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL
     case SOC_RTC_FAST_CLK_SRC_XTAL:
         return clk_hal_xtal_get_freq_mhz() * MHZ;
+#endif
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    case SOC_RTC_FAST_CLK_SRC_XTAL_D2:
+        return clk_hal_xtal_get_freq_mhz() * MHZ >> 1;
+#endif
+#if SOC_CLK_LP_FAST_SUPPORT_XTAL_D4
+    case SOC_RTC_FAST_CLK_SRC_XTAL_D4:
+        return clk_hal_xtal_get_freq_mhz() * MHZ >> 2;
 #endif
     default:
         // Invalid clock source
diff --git a/components/esp_hw_support/port/regdma_link.c b/components/esp_hw_support/port/regdma_link.c
index a090ea0b25d..69db06f5e08 100644
--- a/components/esp_hw_support/port/regdma_link.c
+++ b/components/esp_hw_support/port/regdma_link.c
@@ -15,6 +15,7 @@
 #include "esp_heap_caps.h"
 #include "esp_log.h"
 #include "esp_regdma.h"
+#include "esp_compiler.h"
 
 
 
@@ -419,6 +420,7 @@ static void * regdma_link_get_instance(void *link)
 
     return container_memaddr[it];
 }
+ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-null-dereference") // TODO IDF-11384
 static regdma_link_stats_t * regdma_link_get_stats(void *link)
 {
     const static size_t stats_offset[] = {
@@ -437,6 +439,7 @@ static regdma_link_stats_t * regdma_link_get_stats(void *link)
 
     return (regdma_link_stats_t *)(regdma_link_get_instance(link) + stats_offset[it]);
 }
+ESP_COMPILER_DIAGNOSTIC_POP("-Wanalyzer-null-dereference")
 
 static void regdma_link_update_stats_wrapper(void *link, int entry, int depth)
 {
diff --git a/components/esp_hw_support/regi2c_ctrl.c b/components/esp_hw_support/regi2c_ctrl.c
index 1d63f666864..38ad924d45d 100644
--- a/components/esp_hw_support/regi2c_ctrl.c
+++ b/components/esp_hw_support/regi2c_ctrl.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "hal/regi2c_ctrl.h"
 #include "hal/regi2c_ctrl_ll.h"
 #include "esp_hw_log.h"
+#include "soc/soc_caps.h"
 
 static portMUX_TYPE mux = portMUX_INITIALIZER_UNLOCKED;
 
@@ -19,32 +20,40 @@ static DRAM_ATTR __attribute__((unused)) const char *TAG = "REGI2C";
 
 uint8_t IRAM_ATTR regi2c_ctrl_read_reg(uint8_t block, uint8_t host_id, uint8_t reg_add)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     uint8_t value = regi2c_read_reg_raw(block, host_id, reg_add);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
     return value;
 }
 
 uint8_t IRAM_ATTR regi2c_ctrl_read_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     uint8_t value = regi2c_read_reg_mask_raw(block, host_id, reg_add, msb, lsb);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
     return value;
 }
 
 void IRAM_ATTR regi2c_ctrl_write_reg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     regi2c_write_reg_raw(block, host_id, reg_add, data);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
 }
 
 void IRAM_ATTR regi2c_ctrl_write_reg_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
 {
+    REGI2C_CLOCK_ENABLE();
     portENTER_CRITICAL_SAFE(&mux);
     regi2c_write_reg_mask_raw(block, host_id, reg_add, msb, lsb, data);
     portEXIT_CRITICAL_SAFE(&mux);
+    REGI2C_CLOCK_DISABLE();
 }
 
 void IRAM_ATTR regi2c_enter_critical(void)
@@ -109,3 +118,21 @@ void regi2c_saradc_disable(void)
     regi2c_exit_critical();
 
 }
+
+#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+
+#include "soc/regi2c_saradc.h"
+
+static DRAM_ATTR uint8_t dac_offset_regi2c;
+
+void IRAM_ATTR regi2c_tsens_reg_read(void)
+{
+    dac_offset_regi2c = REGI2C_READ_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC);
+}
+
+void IRAM_ATTR regi2c_tsens_reg_write(void)
+{
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_TSENS_DAC, dac_offset_regi2c);
+}
+
+#endif
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index ed81134542d..a5efcd2dc63 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -12,6 +12,7 @@
 
 #include "esp_attr.h"
 #include "esp_rom_caps.h"
+#include "esp_macros.h"
 #include "esp_memory_utils.h"
 #include "esp_sleep.h"
 #include "esp_private/esp_sleep_internal.h"
@@ -61,6 +62,7 @@
 #include "hal/uart_hal.h"
 #if SOC_TOUCH_SENSOR_SUPPORTED
 #include "hal/touch_sensor_hal.h"
+#include "hal/touch_sens_hal.h"
 #endif
 
 #include "sdkconfig.h"
@@ -222,7 +224,7 @@ typedef struct {
     } domain[ESP_PD_DOMAIN_MAX];
     portMUX_TYPE lock;
     uint64_t sleep_duration;
-    uint32_t wakeup_triggers : 15;
+    uint32_t wakeup_triggers : 20;
 #if SOC_PM_SUPPORT_EXT1_WAKEUP
     uint32_t ext1_trigger_mode : 22;  // 22 is the maximum RTCIO number in all chips
     uint32_t ext1_rtc_gpio_mask : 22;
@@ -296,7 +298,7 @@ static void ext0_wakeup_prepare(void);
 static void ext1_wakeup_prepare(void);
 #endif
 static esp_err_t timer_wakeup_prepare(int64_t sleep_duration);
-#if SOC_TOUCH_SENSOR_SUPPORTED && SOC_TOUCH_SENSOR_VERSION != 1
+#if SOC_TOUCH_SENSOR_VERSION >= 2
 static void touch_wakeup_prepare(void);
 #endif
 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_DEEP_SLEEP_SUPPORTED
@@ -679,15 +681,16 @@ FORCE_INLINE_ATTR void misc_modules_sleep_prepare(uint32_t pd_flags, bool deep_s
 #endif
 #if REGI2C_ANA_CALI_PD_WORKAROUND
         regi2c_analog_cali_reg_read();
+#endif
+#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+        regi2c_tsens_reg_read();
 #endif
     }
 
-#if !CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_IDF_TARGET_ESP32C61
-    // TODO: IDF-7370
     if (!(deep_sleep && (s_sleep_sub_mode_ref_cnt[ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE] != 0))){
+        // TODO: IDF-7370
         sar_periph_ctrl_power_disable();
     }
-#endif
 }
 
 /**
@@ -709,9 +712,7 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
 #if SOC_USB_SERIAL_JTAG_SUPPORTED && !SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP
     sleep_console_usj_pad_restore();
 #endif
-#if !CONFIG_IDF_TARGET_ESP32C61 // TODO: IDF-9304
     sar_periph_ctrl_power_enable();
-#endif
 #if CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && SOC_PM_CPU_RETENTION_BY_RTCCNTL
     sleep_disable_cpu_retention();
 #endif
@@ -724,6 +725,9 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
 #if REGI2C_ANA_CALI_PD_WORKAROUND
     regi2c_analog_cali_reg_write();
 #endif
+#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+    regi2c_tsens_reg_write();
+#endif
 }
 
 static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
@@ -803,7 +807,16 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
     // Save current frequency and switch to XTAL
     rtc_cpu_freq_config_t cpu_freq_config;
     rtc_clk_cpu_freq_get_config(&cpu_freq_config);
+#if SOC_PMU_SUPPORTED
+    // For PMU supported chips, CPU's PLL power can be turned off by PMU, so no need to disable the PLL at here.
+    // Leaving PLL on at this stage also helps USJ keep connection and retention operation (if they rely on this PLL).
+    rtc_clk_cpu_set_to_default_config();
+#else
+    // For earlier chips, there is no PMU module that can turn off the CPU's PLL, so it has to be disabled at here to save the power consumption.
+    // Though ESP32C3/S3 has USB CDC device, it can not function properly during sleep due to the lack of APB clock (before C6, USJ relies on APB clock to work).
+    // Therefore, we will always disable CPU's PLL (i.e. BBPLL).
     rtc_clk_cpu_freq_set_xtal();
+#endif
 
 #if SOC_PM_SUPPORT_EXT0_WAKEUP
     // Configure pins for external wakeup
@@ -861,11 +874,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
         /* In light sleep, the RTC_PERIPH power domain should be in the power-on state (Power on the touch circuit in light sleep),
          * otherwise the touch sensor FSM will be cleared, causing touch sensor false triggering.
          */
-#if SOC_TOUCH_SENSOR_VERSION == 3
         bool keep_rtc_power_on = touch_ll_is_fsm_repeated_timer_enabled();
-#else
-        bool keep_rtc_power_on = touch_ll_get_fsm_state();
-#endif
         if (keep_rtc_power_on) { // Check if the touch sensor is working properly.
             pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
         }
@@ -901,7 +910,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
     uint32_t sleep_flags = pd_flags;
 
     if (s_sleep_sub_mode_ref_cnt[ESP_SLEEP_DIG_USE_RC_FAST_MODE] && !deep_sleep) {
-        pd_flags &= ~RTC_SLEEP_PD_INT_8M;
+        sleep_flags &= ~RTC_SLEEP_PD_INT_8M;
         sleep_flags |= RTC_SLEEP_DIG_USE_8M;
     }
 
@@ -917,6 +926,12 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
         sleep_flags |= RTC_SLEEP_XTAL_AS_RTC_FAST;
     }
 
+#if SOC_LP_VAD_SUPPORTED
+    if (s_sleep_sub_mode_ref_cnt[ESP_SLEEP_LP_USE_XTAL_MODE] && !deep_sleep) {
+        sleep_flags |= RTC_SLEEP_LP_PERIPH_USE_XTAL;
+    }
+#endif
+
 #if CONFIG_ESP_SLEEP_DEBUG
     if (s_sleep_ctx != NULL) {
         s_sleep_ctx->sleep_flags = sleep_flags;
@@ -1106,12 +1121,14 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t m
     esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CLK_READY, (void *)0);
 
     if (!deep_sleep) {
-        s_config.ccount_ticks_record = esp_cpu_get_cycle_count();
+        if (result == ESP_OK) {
+            s_config.ccount_ticks_record = esp_cpu_get_cycle_count();
 #if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
-        if (pd_flags & PMU_SLEEP_PD_TOP) {
-            sleep_retention_do_system_retention(false);
-        }
+            if (pd_flags & PMU_SLEEP_PD_TOP) {
+                sleep_retention_do_system_retention(false);
+            }
 #endif
+        }
         misc_modules_wake_prepare(pd_flags);
     }
 
@@ -1215,9 +1232,7 @@ static esp_err_t IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection)
     } else {
         // Because RTC is in a slower clock domain than the CPU, it
         // can take several CPU cycles for the sleep mode to start.
-        while (1) {
-            ;
-        }
+        ESP_INFINITE_LOOP();
     }
     // Never returns here, except that the sleep is rejected.
     esp_ipc_isr_stall_resume();
@@ -1266,7 +1281,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
 #endif
 
     // If SPI flash was powered down, wait for it to become ready
-    if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
+    if (!reject && (pd_flags & RTC_SLEEP_PD_VDDSDIO)) {
 #if SOC_PM_SUPPORT_TOP_PD
         if (pd_flags & PMU_SLEEP_PD_TOP) {
             uint32_t flash_ready_hw_waited_time_us = pmu_sleep_get_wakup_retention_cost();
@@ -1492,33 +1507,28 @@ esp_err_t esp_light_sleep_start(void)
         // Enter sleep, then wait for flash to be ready on wakeup
         err = esp_light_sleep_inner(pd_flags, flash_enable_time_us);
     }
-#if !CONFIG_FREERTOS_UNICORE && ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
-        if (err != ESP_OK) {
-            esp_sleep_cpu_skip_retention();
-        }
-#endif
 
     // light sleep wakeup flag only makes sense after a successful light sleep
     s_light_sleep_wakeup = (err == ESP_OK);
 
     // System timer has been stopped for the duration of the sleep, correct for that.
     uint64_t rtc_ticks_at_end = rtc_time_get();
-    uint64_t rtc_time_diff = rtc_time_slowclk_to_us(rtc_ticks_at_end - s_config.rtc_ticks_at_sleep_start, s_config.rtc_clk_cal_period);
 
-#if CONFIG_ESP_SLEEP_DEBUG
-    if (s_sleep_ctx != NULL) {
-        s_sleep_ctx->sleep_out_rtc_time_stamp = rtc_ticks_at_end;
-    }
+    if (s_light_sleep_wakeup) {
+        uint64_t rtc_time_diff = rtc_time_slowclk_to_us(rtc_ticks_at_end - s_config.rtc_ticks_at_sleep_start, s_config.rtc_clk_cal_period);
+        /**
+         * If sleep duration is too small(less than 1 rtc_slow_clk cycle), rtc_time_diff will be zero.
+         * In this case, just ignore the time compensation and keep esp_timer monotonic.
+         */
+        if (rtc_time_diff > 0) {
+            esp_timer_private_set(high_res_time_at_start + rtc_time_diff);
+        }
+        esp_set_time_from_rtc();
+    } else {
+#if !CONFIG_FREERTOS_UNICORE && ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
+        esp_sleep_cpu_skip_retention();
 #endif
-
-    /**
-     * If sleep duration is too small(less than 1 rtc_slow_clk cycle), rtc_time_diff will be zero.
-     * In this case, just ignore the time compensation and keep esp_timer monotonic.
-     */
-    if (rtc_time_diff > 0) {
-        esp_timer_private_set(high_res_time_at_start + rtc_time_diff);
     }
-    esp_set_time_from_rtc();
 
     esp_clk_private_unlock();
     esp_timer_private_unlock();
@@ -1553,14 +1563,18 @@ esp_err_t esp_light_sleep_start(void)
 #endif // CONFIG_ESP_TASK_WDT_USE_ESP_TIMER
 
     esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_EXIT_SLEEP, (void *)0);
-    s_config.sleep_time_overhead_out = (esp_cpu_get_cycle_count() - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL);
 
 #if CONFIG_ESP_SLEEP_DEBUG
     if (s_sleep_ctx != NULL) {
+        s_sleep_ctx->sleep_out_rtc_time_stamp = rtc_ticks_at_end;
         s_sleep_ctx->sleep_request_result = err;
     }
 #endif
 
+    if (s_light_sleep_wakeup) {
+        s_config.sleep_time_overhead_out = (esp_cpu_get_cycle_count() - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL);
+    }
+
     portEXIT_CRITICAL(&s_config.lock);
     return err;
 }
@@ -1645,6 +1659,14 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
     return ESP_OK;
 }
 
+#if SOC_LP_VAD_SUPPORTED
+esp_err_t esp_sleep_enable_vad_wakeup(void)
+{
+    s_config.wakeup_triggers |= RTC_LP_VAD_TRIG_EN;
+    return esp_sleep_sub_mode_config(ESP_SLEEP_LP_USE_XTAL_MODE, true);
+}
+#endif
+
 static esp_err_t timer_wakeup_prepare(int64_t sleep_duration)
 {
     if (sleep_duration < 0) {
@@ -1671,26 +1693,7 @@ static esp_err_t timer_wakeup_prepare(int64_t sleep_duration)
     return ESP_OK;
 }
 
-#if SOC_TOUCH_SENSOR_VERSION == 2
-/* In deep sleep mode, only the sleep channel is supported, and other touch channels should be turned off. */
-static void touch_wakeup_prepare(void)
-{
-    uint16_t sleep_cycle = 0;
-    uint16_t meas_times = 0;
-    touch_pad_t touch_num = TOUCH_PAD_NUM0;
-    touch_ll_sleep_get_channel_num(&touch_num); // Check if the sleep pad is enabled.
-    if ((touch_num > TOUCH_PAD_NUM0) && (touch_num < TOUCH_PAD_MAX) && touch_ll_get_fsm_state()) {
-        touch_ll_stop_fsm();
-        touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
-        touch_ll_intr_clear(TOUCH_PAD_INTR_MASK_ALL); // Clear state from previous wakeup
-        touch_hal_sleep_channel_get_work_time(&sleep_cycle, &meas_times);
-        touch_ll_set_meas_times(meas_times);
-        touch_ll_set_sleep_time(sleep_cycle);
-        touch_ll_set_channel_mask(BIT(touch_num));
-        touch_ll_start_fsm();
-    }
-}
-#elif SOC_TOUCH_SENSOR_VERSION == 3
+#if SOC_TOUCH_SENSOR_VERSION >= 2
 static void touch_wakeup_prepare(void)
 {
     touch_hal_prepare_deep_sleep();
@@ -2165,6 +2168,10 @@ esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
 #if SOC_LP_CORE_SUPPORTED
     } else if (wakeup_cause & RTC_LP_CORE_TRIG_EN) {
         return ESP_SLEEP_WAKEUP_ULP;
+#endif
+#if SOC_LP_VAD_SUPPORTED
+    } else if (wakeup_cause & RTC_LP_VAD_TRIG_EN) {
+        return ESP_SLEEP_WAKEUP_VAD;
 #endif
     } else {
         return ESP_SLEEP_WAKEUP_UNDEFINED;
@@ -2229,6 +2236,7 @@ int32_t* esp_sleep_sub_mode_dump_config(FILE *stream) {
                                 [ESP_SLEEP_ULTRA_LOW_MODE]              = "ESP_SLEEP_ULTRA_LOW_MODE",
                                 [ESP_SLEEP_RTC_FAST_USE_XTAL_MODE]      = "ESP_SLEEP_RTC_FAST_USE_XTAL_MODE",
                                 [ESP_SLEEP_DIG_USE_XTAL_MODE]           = "ESP_SLEEP_DIG_USE_XTAL_MODE",
+                                [ESP_SLEEP_LP_USE_XTAL_MODE]            = "ESP_SLEEP_LP_USE_XTAL_MODE",
                             }[mode],
                             s_sleep_sub_mode_ref_cnt[mode] ? "ENABLED" : "DISABLED",
                             s_sleep_sub_mode_ref_cnt[mode]);
@@ -2339,6 +2347,11 @@ static uint32_t get_power_down_flags(void)
     if (s_config.domain[ESP_PD_DOMAIN_VDDSDIO].pd_option == ESP_PD_OPTION_AUTO) {
 #ifndef CONFIG_ESP_SLEEP_POWER_DOWN_FLASH
         s_config.domain[ESP_PD_DOMAIN_VDDSDIO].pd_option = ESP_PD_OPTION_ON;
+#endif
+#if CONFIG_IDF_TARGET_ESP32P4
+        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
+            s_config.domain[ESP_PD_DOMAIN_VDDSDIO].pd_option = ESP_PD_OPTION_ON;
+        }
 #endif
     }
 #endif
@@ -2427,6 +2440,13 @@ static uint32_t get_power_down_flags(void)
     }
 #endif
 
+#if CONFIG_IDF_TARGET_ESP32P4
+    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
+        if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
+            ESP_LOGE(TAG, "ESP32P4 chips lower than v1.0 are not allowed to power down the Flash");
+        }
+    }
+#endif
     return pd_flags;
 }
 
diff --git a/components/esp_hw_support/sleep_retention.c b/components/esp_hw_support/sleep_retention.c
index e437a6fe581..7e01204a6ed 100644
--- a/components/esp_hw_support/sleep_retention.c
+++ b/components/esp_hw_support/sleep_retention.c
@@ -29,6 +29,8 @@
 #endif
 
 static __attribute__((unused)) const char *TAG = "sleep";
+static int acquire_cnt; //for the force acquire lock
+
 
 struct sleep_retention_module_object {
     sleep_retention_module_callbacks_t cbs;         /* A callback list that can extend more sleep retention event callbacks */
@@ -319,6 +321,23 @@ static void sleep_retention_entries_stats(void)
     _lock_release_recursive(&s_retention.lock);
 }
 
+void sleep_retention_dump_modules(FILE *out)
+{
+    uint32_t inited_modules = sleep_retention_get_inited_modules();
+    uint32_t created_modules = sleep_retention_get_created_modules();
+    for (int i = SLEEP_RETENTION_MODULE_MIN; i <= SLEEP_RETENTION_MODULE_MAX; i++) {
+        bool inited = (inited_modules & BIT(i)) != 0;
+        bool created = (created_modules & BIT(i)) != 0;
+        bool is_top = (TOP_DOMAIN_PERIPHERALS_BM & BIT(i)) != 0;
+
+        const char* status = !inited? "-":
+                        created? "CREATED":
+                                "INITED";
+        const char* domain = is_top? "TOP": "-";
+        fprintf(out, "%2d: %4s %8s\n", i, domain, status);
+    }
+}
+
 void sleep_retention_dump_entries(FILE *out)
 {
     _lock_acquire_recursive(&s_retention.lock);
@@ -820,6 +839,42 @@ esp_err_t sleep_retention_module_free(sleep_retention_module_t module)
     return err;
 }
 
+static esp_err_t empty_create(void *args)
+{
+    return ESP_OK;
+}
+
+esp_err_t sleep_retention_power_lock_acquire(void)
+{
+    _lock_acquire_recursive(&s_retention.lock);
+    if (acquire_cnt == 0) {
+        sleep_retention_module_init_param_t init_param = {
+            .cbs = { .create = {.handle = empty_create},},
+        };
+        esp_err_t ret = sleep_retention_module_init(SLEEP_RETENTION_MODULE_NULL, &init_param);
+        if (ret != ESP_OK) {
+            _lock_release_recursive(&s_retention.lock);
+            return ret;
+        }
+    }
+    acquire_cnt++;
+    _lock_release_recursive(&s_retention.lock);
+    return ESP_OK;
+}
+
+esp_err_t sleep_retention_power_lock_release(void)
+{
+    esp_err_t ret = ESP_OK;
+    _lock_acquire_recursive(&s_retention.lock);
+    acquire_cnt--;
+    assert(acquire_cnt >= 0);
+    if (acquire_cnt == 0) {
+        ret = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_NULL);
+    }
+    _lock_release_recursive(&s_retention.lock);
+    return ret;
+}
+
 void IRAM_ATTR sleep_retention_do_extra_retention(bool backup_or_restore)
 {
     if (s_retention.highpri < SLEEP_RETENTION_REGDMA_LINK_HIGHEST_PRIORITY ||
diff --git a/components/esp_hw_support/test_apps/.build-test-rules.yml b/components/esp_hw_support/test_apps/.build-test-rules.yml
index b61d8878c6c..0585429ebae 100644
--- a/components/esp_hw_support/test_apps/.build-test-rules.yml
+++ b/components/esp_hw_support/test_apps/.build-test-rules.yml
@@ -42,6 +42,15 @@ components/esp_hw_support/test_apps/rtc_power_modes:
       temporary: true
       reason: the other targets are not tested yet
 
+components/esp_hw_support/test_apps/sleep_retention:
+  enable:
+    - if: SOC_PAU_SUPPORTED == 1 and CONFIG_NAME != "xip_psram"
+    - if: SOC_PAU_SUPPORTED == 1 and (SOC_SPIRAM_XIP_SUPPORTED == 1 and CONFIG_NAME == "xip_psram")
+
+components/esp_hw_support/test_apps/vad_wakeup:
+  disable:
+    - if: SOC_LP_VAD_SUPPORTED != 1
+
 components/esp_hw_support/test_apps/wakeup_tests:
   disable:
     - if: IDF_TARGET in ["esp32c5", "esp32p4", "linux", "esp32c61"]
diff --git a/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c b/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c
index eb927a04b6a..45eeb11c320 100644
--- a/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c
+++ b/components/esp_hw_support/test_apps/dma/main/test_dw_gdma.c
@@ -380,6 +380,7 @@ static bool test_dw_gdma_list_mode_invalid_block_cb(dw_gdma_channel_handle_t cha
     udata->count++;
     // clear the destination buffer
     memset(udata->dst_buffer_addr, 0, udata->dst_buffer_size);
+    esp_cache_msync(udata->dst_buffer_addr, udata->dst_buffer_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
     dw_gdma_block_markers_t markers = {
         .is_last = true,  // mark the next block as the last one
         .is_valid = true, // mark the block as valid so that the DMA can continue the transfer
diff --git a/components/esp_hw_support/test_apps/dma/pytest_dma.py b/components/esp_hw_support/test_apps/dma/pytest_dma.py
index 3d78de4a849..1d741f14fb1 100644
--- a/components/esp_hw_support/test_apps/dma/pytest_dma.py
+++ b/components/esp_hw_support/test_apps/dma/pytest_dma.py
@@ -21,7 +21,7 @@
     indirect=True,
 )
 def test_dma(dut: Dut) -> None:
-    dut.run_all_single_board_cases()
+    dut.run_all_single_board_cases(reset=True)
 
 
 @pytest.mark.esp32s3
@@ -34,4 +34,4 @@ def test_dma(dut: Dut) -> None:
     indirect=True,
 )
 def test_dma_psram(dut: Dut) -> None:
-    dut.run_all_single_board_cases()
+    dut.run_all_single_board_cases(reset=True)
diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c
index 39f57f1b5c4..f2231dc509d 100644
--- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c
+++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_ldo.c
@@ -25,7 +25,7 @@ TEST_CASE("LDO channel acquire and release (no adjustable)", "[LDO]")
     TEST_ASSERT_EQUAL(success_ldo_chans[0], success_ldo_chans[1]);
     TEST_ASSERT_EQUAL(success_ldo_chans[0], success_ldo_chans[2]);
     // can't acquire with a different voltage
-    ldo_chan_config.voltage_mv = 3300;
+    ldo_chan_config.voltage_mv = 2500;
     TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_ldo_acquire_channel(&ldo_chan_config, &fail_ldo_chan));
     // the channel has been acquired as "not adjustable" before, so we can't acquire it as "adjustable" again
     ldo_chan_config = (esp_ldo_channel_config_t) {
@@ -36,7 +36,7 @@ TEST_CASE("LDO channel acquire and release (no adjustable)", "[LDO]")
     TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_ldo_acquire_channel(&ldo_chan_config, &fail_ldo_chan));
 
     // can't change the voltage for a non-adjustable channel
-    TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_ldo_channel_adjust_voltage(success_ldo_chans[0], 3300));
+    TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_ldo_channel_adjust_voltage(success_ldo_chans[0], 1900));
 
     for (int i = 0; i < 3; i++) {
         TEST_ESP_OK(esp_ldo_release_channel(success_ldo_chans[i]));
@@ -62,7 +62,7 @@ TEST_CASE("LDO channel acquire and release (adjustable)", "[LDO]")
     TEST_ESP_ERR(ESP_ERR_INVALID_ARG, esp_ldo_acquire_channel(&ldo_chan_config, &fail_ldo_chan));
 
     // can change voltage for an adjustable channel
-    TEST_ESP_OK(esp_ldo_channel_adjust_voltage(success_ldo_chan, 3300));
+    TEST_ESP_OK(esp_ldo_channel_adjust_voltage(success_ldo_chan, 2500));
     TEST_ESP_OK(esp_ldo_release_channel(success_ldo_chan));
 }
 
@@ -71,7 +71,7 @@ TEST_CASE("LDO channel state dump", "[LDO][manual][ignore]")
     esp_ldo_channel_handle_t success_ldo_chans[3] = {};
     esp_ldo_channel_config_t ldo_chan_config = {
         .chan_id = 2,
-        .voltage_mv = 1800,
+        .voltage_mv = 1900,
     };
     TEST_ESP_OK(esp_ldo_acquire_channel(&ldo_chan_config, &success_ldo_chans[0]));
 
diff --git a/components/esp_hw_support/test_apps/sleep_retention/CMakeLists.txt b/components/esp_hw_support/test_apps/sleep_retention/CMakeLists.txt
new file mode 100644
index 00000000000..47e7d817bd3
--- /dev/null
+++ b/components/esp_hw_support/test_apps/sleep_retention/CMakeLists.txt
@@ -0,0 +1,10 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+# "Trim" the build. Include the minimal set of components, main, and anything it depends on. We also depend on esp_psram
+# as we set CONFIG_SPIRAM_... options.
+set(COMPONENTS main esp_psram)
+
+project(test_retention)
diff --git a/components/esp_hw_support/test_apps/sleep_retention/README.md b/components/esp_hw_support/test_apps/sleep_retention/README.md
new file mode 100644
index 00000000000..77eda1867c0
--- /dev/null
+++ b/components/esp_hw_support/test_apps/sleep_retention/README.md
@@ -0,0 +1,2 @@
+| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
+| ----------------- | -------- | -------- | --------- | -------- | -------- |
diff --git a/components/esp_hw_support/test_apps/sleep_retention/main/CMakeLists.txt b/components/esp_hw_support/test_apps/sleep_retention/main/CMakeLists.txt
new file mode 100644
index 00000000000..d285f1b5525
--- /dev/null
+++ b/components/esp_hw_support/test_apps/sleep_retention/main/CMakeLists.txt
@@ -0,0 +1,7 @@
+set(srcs "test_app_main.c" "test_retention.c")
+
+# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
+# the component can be registered as WHOLE_ARCHIVE
+idf_component_register(SRCS ${srcs}
+                       PRIV_REQUIRES unity esp_mm esp_psram
+                       WHOLE_ARCHIVE)
diff --git a/components/esp_hw_support/test_apps/sleep_retention/main/test_app_main.c b/components/esp_hw_support/test_apps/sleep_retention/main/test_app_main.c
new file mode 100644
index 00000000000..027d2b69c05
--- /dev/null
+++ b/components/esp_hw_support/test_apps/sleep_retention/main/test_app_main.c
@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "esp_heap_caps.h"
+
+#define TEST_MEMORY_LEAK_THRESHOLD (-300)
+
+static size_t before_free_8bit;
+static size_t before_free_32bit;
+
+static void check_leak(size_t before_free, size_t after_free, const char *type)
+{
+    ssize_t delta = after_free - before_free;
+    printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
+    TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
+}
+
+void setUp(void)
+{
+    before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+}
+
+void tearDown(void)
+{
+    size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+    check_leak(before_free_8bit, after_free_8bit, "8BIT");
+    check_leak(before_free_32bit, after_free_32bit, "32BIT");
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}
diff --git a/components/esp_hw_support/test_apps/sleep_retention/main/test_retention.c b/components/esp_hw_support/test_apps/sleep_retention/main/test_retention.c
new file mode 100644
index 00000000000..72a4e5b3e80
--- /dev/null
+++ b/components/esp_hw_support/test_apps/sleep_retention/main/test_retention.c
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+#include "unity.h"
+#include "esp_private/sleep_sys_periph.h"
+#include "esp_private/sleep_retention.h"
+#include "esp_sleep.h"
+#include "esp_private/sleep_cpu.h"
+
+const char TAG[] = "retention";
+
+TEST_CASE("retention: can go to retention", "[retention]")
+{
+    // Prepare a TOP PD sleep
+    TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
+    sleep_cpu_configure(true);
+
+    TEST_ASSERT_EQUAL_INT32(true, peripheral_domain_pd_allowed());
+    sleep_retention_dump_modules(stdout);
+    vTaskDelay(1000/portTICK_PERIOD_MS);
+
+    ESP_LOGI(TAG, "Going to sleep...");
+    esp_light_sleep_start();
+
+    ESP_LOGI(TAG, "After wakeup");
+    TEST_ASSERT_EQUAL_INT32(true, peripheral_domain_pd_allowed());
+    sleep_retention_dump_modules(stdout);
+
+    sleep_cpu_configure(false);
+}
diff --git a/components/esp_hw_support/test_apps/sleep_retention/pytest_retention.py b/components/esp_hw_support/test_apps/sleep_retention/pytest_retention.py
new file mode 100644
index 00000000000..3a4ca50f1ee
--- /dev/null
+++ b/components/esp_hw_support/test_apps/sleep_retention/pytest_retention.py
@@ -0,0 +1,35 @@
+# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import functools
+from typing import Callable
+from typing import Dict
+from typing import List
+
+import pytest
+from pytest_embedded import Dut
+
+
+def target_list(targets: List[str]) -> Callable:
+
+    def decorator(func: Callable) -> Callable:
+
+        @functools.wraps(func)
+        def wrapper(*args: List, **kwargs: Dict) -> Callable:
+            return func(*args, **kwargs)  # type: ignore
+
+        for target in targets:
+            wrapper = pytest.mark.__getattr__(target)(wrapper)
+
+        return wrapper
+
+    return decorator
+
+
+# SOC_PAU_SUPPORTED == 1
+retention_targets = ['esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61']
+
+
+@target_list(retention_targets)
+@pytest.mark.generic
+def test_sleep_retention(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
diff --git a/components/soc/esp32c2/register/soc/.gitkeep b/components/esp_hw_support/test_apps/sleep_retention/sdkconfig.ci.defaults
similarity index 100%
rename from components/soc/esp32c2/register/soc/.gitkeep
rename to components/esp_hw_support/test_apps/sleep_retention/sdkconfig.ci.defaults
diff --git a/components/esp_hw_support/test_apps/sleep_retention/sdkconfig.ci.xip_psram b/components/esp_hw_support/test_apps/sleep_retention/sdkconfig.ci.xip_psram
new file mode 100644
index 00000000000..358f51460be
--- /dev/null
+++ b/components/esp_hw_support/test_apps/sleep_retention/sdkconfig.ci.xip_psram
@@ -0,0 +1,2 @@
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_XIP_FROM_PSRAM=y
diff --git a/components/esp_hw_support/test_apps/sleep_retention/sdkconfig.defaults b/components/esp_hw_support/test_apps/sleep_retention/sdkconfig.defaults
new file mode 100644
index 00000000000..6cefbfaaf53
--- /dev/null
+++ b/components/esp_hw_support/test_apps/sleep_retention/sdkconfig.defaults
@@ -0,0 +1,6 @@
+CONFIG_FREERTOS_HZ=1000
+CONFIG_ESP_TASK_WDT=n
+
+CONFIG_PM_ENABLE=y
+CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
+CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
diff --git a/components/esp_hw_support/test_apps/vad_wakeup/CMakeLists.txt b/components/esp_hw_support/test_apps/vad_wakeup/CMakeLists.txt
new file mode 100644
index 00000000000..50365600115
--- /dev/null
+++ b/components/esp_hw_support/test_apps/vad_wakeup/CMakeLists.txt
@@ -0,0 +1,8 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.16)
+
+# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
+set(COMPONENTS main)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(vad_wakeup)
diff --git a/components/esp_hw_support/test_apps/vad_wakeup/README.md b/components/esp_hw_support/test_apps/vad_wakeup/README.md
new file mode 100644
index 00000000000..f8ea707124d
--- /dev/null
+++ b/components/esp_hw_support/test_apps/vad_wakeup/README.md
@@ -0,0 +1,3 @@
+| Supported Targets | ESP32-P4 |
+| ----------------- | -------- |
+
diff --git a/components/esp_hw_support/test_apps/vad_wakeup/main/CMakeLists.txt b/components/esp_hw_support/test_apps/vad_wakeup/main/CMakeLists.txt
new file mode 100644
index 00000000000..3a92a5d2bd7
--- /dev/null
+++ b/components/esp_hw_support/test_apps/vad_wakeup/main/CMakeLists.txt
@@ -0,0 +1,7 @@
+set(srcs "test_app_main.c"
+         "test_vad_wakeup.c")
+
+idf_component_register(SRCS ${srcs}
+                       REQUIRES unity esp_driver_i2s esp_driver_uart ulp esp_timer
+                       WHOLE_ARCHIVE
+                       EMBED_FILES "test_vad_8k.pcm")
diff --git a/components/esp_hw_support/test_apps/vad_wakeup/main/test_app_main.c b/components/esp_hw_support/test_apps/vad_wakeup/main/test_app_main.c
new file mode 100644
index 00000000000..1d34b63e446
--- /dev/null
+++ b/components/esp_hw_support/test_apps/vad_wakeup/main/test_app_main.c
@@ -0,0 +1,27 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "unity_test_utils.h"
+
+#define LEAKS (400)
+
+
+void setUp(void)
+{
+    unity_utils_record_free_mem();
+}
+
+void tearDown(void)
+{
+    unity_utils_evaluate_leaks_direct(LEAKS);
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}
diff --git a/components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_8k.pcm b/components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_8k.pcm
new file mode 100644
index 00000000000..5b6c32a0373
Binary files /dev/null and b/components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_8k.pcm differ
diff --git a/components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_wakeup.c b/components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_wakeup.c
new file mode 100644
index 00000000000..2a245bfc6f3
--- /dev/null
+++ b/components/esp_hw_support/test_apps/vad_wakeup/main/test_vad_wakeup.c
@@ -0,0 +1,162 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_sleep.h"
+#include "esp_log.h"
+#include "driver/uart.h"
+#include "driver/lp_i2s.h"
+#include "driver/lp_i2s_std.h"
+#include "driver/i2s_std.h"
+#include "ulp_lp_core_lp_vad_shared.h"
+#include "unity.h"
+#include "esp_timer.h"
+
+#define TEST_I2S_FRAME_SIZE            (128)       // Frame numbers in every writing / reading
+#define TEST_I2S_TRANS_SIZE            (4096)      // Trans size
+#define TEST_LP_I2S_PIN_BCK            4
+#define TEST_LP_I2S_PIN_WS             5
+#define TEST_LP_I2S_PIN_DIN            6
+
+
+extern const uint8_t test_vad_pcm_start[]            asm("_binary_test_vad_8k_pcm_start");
+extern const uint8_t test_vad_pcm_end[]              asm("_binary_test_vad_8k_pcm_end");
+static const char *TAG = "TEST_VAD";
+
+static void s_hp_i2s_config(void)
+{
+    esp_err_t ret = ESP_FAIL;
+    int pcm_size = test_vad_pcm_end - test_vad_pcm_start;
+    printf("pcm_size: %d\n", pcm_size);
+
+    i2s_chan_handle_t tx_handle = NULL;
+    i2s_chan_config_t i2s_channel_config = {
+        .id = I2S_NUM_0,
+        .role = I2S_ROLE_MASTER,
+        .dma_desc_num = 16,
+        .dma_frame_num = TEST_I2S_FRAME_SIZE,
+        .auto_clear = false,
+    };
+    TEST_ESP_OK(i2s_new_channel(&i2s_channel_config, &tx_handle, NULL));
+
+
+    i2s_std_config_t i2s_std_config = {
+        .gpio_cfg = {
+            .mclk = I2S_GPIO_UNUSED,
+            .bclk = GPIO_NUM_7,
+            .ws   = GPIO_NUM_8,
+            .dout = GPIO_NUM_21,
+            .din  = -1,
+            .invert_flags = {
+                .mclk_inv = false,
+                .bclk_inv = false,
+                .ws_inv   = false,
+            },
+        },
+    };
+    i2s_std_config.clk_cfg = (i2s_std_clk_config_t)I2S_STD_CLK_DEFAULT_CONFIG(16000);
+    i2s_std_config.slot_cfg = (i2s_std_slot_config_t)I2S_STD_PCM_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO);
+    TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &i2s_std_config));
+
+
+    uint8_t *txbuf = (uint8_t *)heap_caps_calloc(1, TEST_I2S_TRANS_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+    TEST_ASSERT(txbuf);
+
+    uint8_t *prebuf = (uint8_t *)heap_caps_calloc(1, TEST_I2S_TRANS_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+    TEST_ASSERT(prebuf);
+
+    memcpy(prebuf, test_vad_pcm_start, TEST_I2S_TRANS_SIZE);
+    memcpy(txbuf, test_vad_pcm_start, TEST_I2S_TRANS_SIZE);
+
+    for (int i = 0; i < TEST_I2S_TRANS_SIZE; i++) {
+        ESP_LOGD(TAG, "prebuf[%d]: %d", i, prebuf[i]);
+        ESP_LOGD(TAG, "txbuf[%d]: %d", i, txbuf[i]);
+    }
+
+    size_t bytes_written = 0;
+    TEST_ESP_OK(i2s_channel_preload_data(tx_handle, prebuf, TEST_I2S_TRANS_SIZE, &bytes_written));
+
+    TEST_ESP_OK(i2s_channel_enable(tx_handle));
+
+    while (1) {
+        ret = i2s_channel_write(tx_handle, txbuf, TEST_I2S_TRANS_SIZE, &bytes_written, 0);
+        if (ret != ESP_OK && ret != ESP_ERR_TIMEOUT) {
+            TEST_ESP_OK(ret);
+        }
+        ESP_LOGD(TAG, "bytes_written: %d", bytes_written);
+        vTaskDelay(1);
+    }
+}
+
+static void s_lp_vad_config(void)
+{
+    ESP_ERROR_CHECK(esp_sleep_enable_vad_wakeup());
+    ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON));
+    ESP_ERROR_CHECK(esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON));
+
+    lp_i2s_chan_handle_t rx_handle = NULL;
+    lp_i2s_chan_config_t config = {
+        .id = 0,
+        .role = I2S_ROLE_SLAVE,
+        .threshold = 512,
+    };
+    TEST_ESP_OK(lp_i2s_new_channel(&config, NULL, &rx_handle));
+
+    lp_i2s_std_config_t lp_std_cfg = {
+        .pin_cfg = {
+            .bck = TEST_LP_I2S_PIN_BCK,
+            .ws = TEST_LP_I2S_PIN_WS,
+            .din = TEST_LP_I2S_PIN_DIN,
+        },
+    };
+    lp_std_cfg.slot_cfg = (lp_i2s_std_slot_config_t)LP_I2S_STD_PCM_SHORT_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO);
+    TEST_ESP_OK(lp_i2s_channel_init_std_mode(rx_handle, &lp_std_cfg));
+
+    // LP VAD Init
+    lp_vad_init_config_t init_config = {
+        .lp_i2s_chan = rx_handle,
+        .vad_config = {
+            .init_frame_num = 100,
+            .min_energy_thresh = 100,
+            .speak_activity_thresh = 10,
+            .non_speak_activity_thresh = 30,
+            .min_speak_activity_thresh = 3,
+            .max_speak_activity_thresh = 100,
+        },
+    };
+    TEST_ESP_OK(lp_core_lp_vad_init(0, &init_config));
+    TEST_ESP_OK(lp_i2s_channel_enable(rx_handle));
+    TEST_ESP_OK(lp_core_lp_vad_enable(0));
+
+    printf("Entering light sleep\n");
+    /* To make sure the complete line is printed before entering sleep mode,
+        * need to wait until UART TX FIFO is empty:
+        */
+    uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM);
+
+    /* Enter sleep mode */
+    esp_light_sleep_start();
+
+    /* Determine wake up reason */
+    const char* wakeup_reason;
+    switch (esp_sleep_get_wakeup_cause()) {
+        case ESP_SLEEP_WAKEUP_VAD:
+            wakeup_reason = "vad";
+            break;
+        default:
+            wakeup_reason = "other";
+            TEST_ASSERT(false);
+            break;
+    }
+
+    ESP_LOGI(TAG, "wakeup, reason: %s", wakeup_reason);
+}
+
+TEST_CASE_MULTIPLE_DEVICES("test LP VAD wakeup", "[vad][ignore][manual]", s_hp_i2s_config, s_lp_vad_config);
diff --git a/components/esp_hw_support/test_apps/vad_wakeup/pytest_wakeup_vad.py b/components/esp_hw_support/test_apps/vad_wakeup/pytest_wakeup_vad.py
new file mode 100644
index 00000000000..b4d9f85affd
--- /dev/null
+++ b/components/esp_hw_support/test_apps/vad_wakeup/pytest_wakeup_vad.py
@@ -0,0 +1,11 @@
+# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32p4
+@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='lack of runners for now')
+@pytest.mark.lp_i2s
+def test_efuse(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
diff --git a/components/esp_hw_support/test_apps/vad_wakeup/sdkconfig.defaults b/components/esp_hw_support/test_apps/vad_wakeup/sdkconfig.defaults
new file mode 100644
index 00000000000..cac3f9a01f9
--- /dev/null
+++ b/components/esp_hw_support/test_apps/vad_wakeup/sdkconfig.defaults
@@ -0,0 +1,8 @@
+CONFIG_ESP_TASK_WDT_INIT=n
+
+CONFIG_ULP_COPROC_ENABLED=y
+CONFIG_ULP_COPROC_TYPE_LP_CORE=y
+CONFIG_ULP_COPROC_RESERVE_MEM=12000
+CONFIG_ULP_PANIC_OUTPUT_ENABLE=y
+
+CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y
diff --git a/components/esp_lcd/Kconfig b/components/esp_lcd/Kconfig
index 1e6ee9407cb..c247c58637e 100644
--- a/components/esp_lcd/Kconfig
+++ b/components/esp_lcd/Kconfig
@@ -1,47 +1,40 @@
-menu "LCD and Touch Panel"
-    comment "LCD Touch Drivers are maintained in the ESP Component Registry"
+menu "ESP-Driver:LCD Controller Configurations"
+    config LCD_ENABLE_DEBUG_LOG
+        bool "Enable debug log"
+        default n
+        help
+            whether to enable the debug log message for LCD driver.
+            Note that, this option only controls the LCD driver log, won't affect other drivers.
 
-    menu "LCD Peripheral Configuration"
-        config LCD_ENABLE_DEBUG_LOG
-            bool "Enable debug log"
+    if SOC_LCD_RGB_SUPPORTED
+        config LCD_RGB_ISR_IRAM_SAFE
+            bool "RGB LCD ISR IRAM-Safe"
+            select GDMA_ISR_IRAM_SAFE # bounce buffer mode relies on GDMA EOF interrupt
             default n
             help
-                whether to enable the debug log message for LCD driver.
-                Note that, this option only controls the LCD driver log, won't affect other drivers.
+                Ensure the LCD interrupt is IRAM-Safe by allowing the interrupt handler to be
+                executable when the cache is disabled (e.g. SPI Flash write).
+                If you want the LCD driver to keep flushing the screen even when cache ops disabled,
+                you can enable this option. Note, this will also increase the IRAM usage.
 
-        if SOC_LCD_RGB_SUPPORTED
-            config LCD_RGB_ISR_IRAM_SAFE
-                bool "RGB LCD ISR IRAM-Safe"
-                default n
-                help
-                    Ensure the LCD interrupt is IRAM-Safe by allowing the interrupt handler to be
-                    executable when the cache is disabled (e.g. SPI Flash write).
-                    If you want the LCD driver to keep flushing the screen even when cache ops disabled,
-                    you can enable this option. Note, this will also increase the IRAM usage.
-
-            config LCD_RGB_RESTART_IN_VSYNC
-                bool "Restart transmission in VSYNC"
-                default n
-                select GDMA_CTRL_FUNC_IN_IRAM # need to restart GDMA in the LCD ISR
-                help
-                    Reset the GDMA channel every VBlank to stop permanent desyncs from happening.
-                    Only need to enable it when in your application, the DMA can't deliver data
-                    as fast as the LCD consumes it.
-        endif # SOC_LCD_RGB_SUPPORTED
+        config LCD_RGB_RESTART_IN_VSYNC
+            bool "Always restart RGB LCD transmission in VSYNC"
+            default n
+            help
+                Reset the GDMA channel every VBlank to stop permanent desyncs from happening.
+                Only need to enable it when in your application, the DMA can't deliver data
+                as fast as the LCD consumes it.
+    endif # SOC_LCD_RGB_SUPPORTED
 
-        if SOC_MIPI_DSI_SUPPORTED
-            config LCD_DSI_ISR_IRAM_SAFE
-                bool "DSI LCD ISR IRAM-Safe"
-                default n
-                select DW_GDMA_ISR_IRAM_SAFE
-                select DW_GDMA_CTRL_FUNC_IN_IRAM
-                select DW_GDMA_SETTER_FUNC_IN_IRAM
-                select DW_GDMA_GETTER_FUNC_IN_IRAM
-                help
-                    Ensure the LCD interrupt is IRAM-Safe by allowing the interrupt handler to be
-                    executable when the cache is disabled (e.g. SPI Flash write).
-                    If you want the LCD driver to keep flushing the screen even when cache ops disabled,
-                    you can enable this option. Note, this will also increase the IRAM usage.
-        endif # SOC_MIPI_DSI_SUPPORTED
-    endmenu
+    if SOC_MIPI_DSI_SUPPORTED
+        config LCD_DSI_ISR_IRAM_SAFE
+            bool "DSI LCD ISR IRAM-Safe"
+            default n
+            select DW_GDMA_ISR_IRAM_SAFE # relies on DW_GDMA Full trans done interrupt
+            help
+                Ensure the LCD interrupt is IRAM-Safe by allowing the interrupt handler to be
+                executable when the cache is disabled (e.g. SPI Flash write).
+                If you want the LCD driver to keep flushing the screen even when cache ops disabled,
+                you can enable this option. Note, this will also increase the IRAM usage.
+    endif # SOC_MIPI_DSI_SUPPORTED
 endmenu
diff --git a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c
index 49933e01608..8fa35c55dc0 100644
--- a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c
+++ b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c
@@ -16,7 +16,7 @@ static const char *TAG = "lcd.dsi.bus";
 
 #define MIPI_DSI_DEFAULT_TIMEOUT_CLOCK_FREQ_MHZ 10
 // TxClkEsc frequency must be configured between 2 and 20 MHz
-#define MIPI_DSI_DEFAULT_ESCAPE_CLOCK_FREQ_MHZ  10
+#define MIPI_DSI_DEFAULT_ESCAPE_CLOCK_FREQ_MHZ  18
 
 esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lcd_dsi_bus_handle_t *ret_bus)
 {
diff --git a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c
index c41a8d7d6f9..5a74f4376c2 100644
--- a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c
+++ b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c
@@ -20,6 +20,7 @@
 #include "esp_private/esp_clk_tree_common.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
+#include "hal/color_hal.h"
 
 static const char *TAG = "lcd.dsi.dpi";
 
@@ -40,7 +41,8 @@ struct esp_lcd_dpi_panel_t {
     uint32_t v_pixels;            // Vertical pixels
     size_t fb_size;               // Frame buffer size, in bytes
     size_t bits_per_pixel;        // Bits per pixel
-    lcd_color_rgb_pixel_format_t pixel_format; // RGB Pixel format
+    lcd_color_format_t in_color_format;  // Input color format
+    lcd_color_format_t out_color_format; // Output color format
     dw_gdma_channel_handle_t dma_chan;    // DMA channel
     dw_gdma_link_list_handle_t link_lists[DPI_PANEL_MAX_FB_NUM]; // DMA link list
     esp_async_fbcpy_handle_t fbcpy_handle; // Use DMA2D to do frame buffer copy
@@ -175,6 +177,19 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_
         bits_per_pixel = 24;
         break;
     }
+    lcd_color_format_t in_color_format = COLOR_TYPE_ID(COLOR_SPACE_RGB, panel_config->pixel_format);
+    // if user sets the in_color_format, it can override the pixel format setting
+    if (panel_config->in_color_format) {
+        color_space_pixel_format_t in_color_id = {
+            .color_type_id = panel_config->in_color_format,
+        };
+        bits_per_pixel = color_hal_pixel_format_get_bit_depth(in_color_id);
+        in_color_format = panel_config->in_color_format;
+    }
+    lcd_color_format_t out_color_format = in_color_format;
+    if (panel_config->out_color_format) {
+        out_color_format = panel_config->out_color_format;
+    }
     ESP_RETURN_ON_FALSE(panel_config->video_timing.h_size * panel_config->video_timing.v_size * bits_per_pixel % 8 == 0,
                         ESP_ERR_INVALID_ARG, TAG, "frame buffer size not aligned to byte boundary");
 
@@ -184,7 +199,8 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_
     dpi_panel = heap_caps_calloc(1, sizeof(esp_lcd_dpi_panel_t), DSI_MEM_ALLOC_CAPS);
     ESP_GOTO_ON_FALSE(dpi_panel, ESP_ERR_NO_MEM, err, TAG, "no memory for DPI panel");
     dpi_panel->virtual_channel = panel_config->virtual_channel;
-    dpi_panel->pixel_format = panel_config->pixel_format;
+    dpi_panel->in_color_format = in_color_format;
+    dpi_panel->out_color_format = out_color_format;
     dpi_panel->bus = bus;
     dpi_panel->num_fbs = num_fbs;
 
@@ -253,16 +269,25 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_
     ESP_GOTO_ON_ERROR(dpi_panel_create_dma_link(dpi_panel), err, TAG, "initialize DMA link failed");
 
     mipi_dsi_host_ll_dpi_set_vcid(hal->host, panel_config->virtual_channel);
-    mipi_dsi_hal_host_dpi_set_color_coding(hal, panel_config->pixel_format, 0);
+    mipi_dsi_hal_host_dpi_set_color_coding(hal, out_color_format, 0);
     // these signals define how the DPI interface interacts with the controller
     mipi_dsi_host_ll_dpi_set_timing_polarity(hal->host, false, false, false, false, false);
-    // configure the low-power transitions: defines the video periods which are permitted to goto low-power if the time available to do so
-    mipi_dsi_host_ll_dpi_enable_lp_horizontal_timing(hal->host, true, true);
-    mipi_dsi_host_ll_dpi_enable_lp_vertical_timing(hal->host, true, true, true, true);
+
+    if (panel_config->flags.disable_lp) {
+        // configure the low-power transitions: defines the video periods which are NOT permitted to goto low-power
+        mipi_dsi_host_ll_dpi_enable_lp_horizontal_timing(hal->host, false, false);
+        mipi_dsi_host_ll_dpi_enable_lp_vertical_timing(hal->host, false, false, false, false);
+        // commands are NOT transmitted in low-power mode
+        mipi_dsi_host_ll_dpi_enable_lp_command(hal->host, false);
+    } else {
+        // configure the low-power transitions: defines the video periods which are permitted to goto low-power if the time available to do so
+        mipi_dsi_host_ll_dpi_enable_lp_horizontal_timing(hal->host, true, true);
+        mipi_dsi_host_ll_dpi_enable_lp_vertical_timing(hal->host, true, true, true, true);
+        // commands are transmitted in low-power mode
+        mipi_dsi_host_ll_dpi_enable_lp_command(hal->host, true);
+    }
     // after sending a frame, the DSI device should return an ack
     mipi_dsi_host_ll_dpi_enable_frame_ack(hal->host, true);
-    // commands are transmitted in low-power mode
-    mipi_dsi_host_ll_dpi_enable_lp_command(hal->host, true);
     // using the burst mode because it's energy-efficient
     mipi_dsi_host_ll_dpi_set_video_burst_type(hal->host, MIPI_DSI_LL_VIDEO_BURST_WITH_SYNC_PULSES);
     // configure the size of the active lin period, measured in pixels
@@ -282,6 +307,8 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_
                                               panel_config->video_timing.vsync_front_porch);
     mipi_dsi_brg_ll_set_num_pixel_bits(hal->bridge, panel_config->video_timing.h_size * panel_config->video_timing.v_size * bits_per_pixel);
     mipi_dsi_brg_ll_set_underrun_discard_count(hal->bridge, panel_config->video_timing.h_size);
+    // set input color space
+    mipi_dsi_brg_ll_set_input_color_space(hal->bridge, COLOR_SPACE_TYPE(in_color_format));
     // use the DW_GDMA as the flow controller
     mipi_dsi_brg_ll_set_flow_controller(hal->bridge, MIPI_DSI_LL_FLOW_CONTROLLER_DMA);
     mipi_dsi_brg_ll_set_multi_block_number(hal->bridge, DPI_PANEL_MIN_DMA_NODES_PER_LINK);
@@ -334,7 +361,7 @@ static esp_err_t dpi_panel_del(esp_lcd_panel_t *panel)
         esp_async_fbcpy_uninstall(dpi_panel->fbcpy_handle);
     }
     if (dpi_panel->draw_sem) {
-        vSemaphoreDelete(dpi_panel->draw_sem);
+        vSemaphoreDeleteWithCaps(dpi_panel->draw_sem);
     }
     if (dpi_panel->pm_lock) {
         esp_pm_lock_release(dpi_panel->pm_lock);
@@ -506,9 +533,8 @@ static esp_err_t dpi_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int
             .copy_size_x = x_end - x_start,
             .copy_size_y = y_end - y_start,
             .pixel_format_unique_id = {
-                .color_space = COLOR_SPACE_RGB,
-                .pixel_format = dpi_panel->pixel_format,
-            },
+                .color_type_id = dpi_panel->in_color_format,
+            }
         };
         ESP_RETURN_ON_ERROR(esp_async_fbcpy(dpi_panel->fbcpy_handle, &fbcpy_trans_config, async_fbcpy_done_cb, dpi_panel), TAG, "async memcpy failed");
     }
@@ -516,6 +542,24 @@ static esp_err_t dpi_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int
     return ESP_OK;
 }
 
+esp_err_t esp_lcd_dpi_panel_set_color_conversion(esp_lcd_panel_handle_t panel, const esp_lcd_color_conv_config_t *config)
+{
+    ESP_RETURN_ON_FALSE(panel, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    esp_lcd_dpi_panel_t *dpi_panel = __containerof(panel, esp_lcd_dpi_panel_t, base);
+    esp_lcd_dsi_bus_handle_t bus = dpi_panel->bus;
+    mipi_dsi_hal_context_t *hal = &bus->hal;
+
+    if (dpi_panel->in_color_format == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422)
+            && COLOR_SPACE_TYPE(dpi_panel->out_color_format) == LCD_COLOR_SPACE_RGB) {
+        // YUV422->RGB
+        mipi_dsi_brg_ll_set_yuv_convert_std(hal->bridge, config->spec.yuv.conv_std);
+        mipi_dsi_brg_ll_set_yuv422_pack_order(hal->bridge, config->spec.yuv.yuv422.in_pack_order);
+    } else {
+        ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "unsupported conversion mode");
+    }
+    return ESP_OK;
+}
+
 esp_err_t esp_lcd_dpi_panel_set_pattern(esp_lcd_panel_handle_t panel, mipi_dsi_pattern_type_t pattern)
 {
     ESP_RETURN_ON_FALSE(panel, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
diff --git a/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h b/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h
index 657f71583db..497b4329bb0 100644
--- a/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h
+++ b/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h
@@ -84,12 +84,17 @@ typedef struct {
     mipi_dsi_dpi_clock_source_t dpi_clk_src;   /*!< MIPI DSI DPI clock source */
     uint32_t dpi_clock_freq_mhz;               /*!< DPI clock frequency in MHz */
     lcd_color_rgb_pixel_format_t pixel_format; /*!< Pixel format that used by the MIPI LCD device */
+    lcd_color_format_t in_color_format;        /*!< Format of the input data (color space and pixel format),
+                                                    which is the format stored in the frame buffer */
+    lcd_color_format_t out_color_format;       /*!< Format of the output data (color space and pixel format),
+                                                    which is the format that the panel can accept */
     uint8_t num_fbs;                           /*!< Number of screen-sized frame buffers that allocated by the driver
                                                     By default (set to either 0 or 1) only one frame buffer will be created */
     esp_lcd_video_timing_t video_timing;       /*!< Video timing */
     /// Extra configuration flags for MIPI DSI DPI panel
     struct extra_dpi_panel_flags {
         uint32_t use_dma2d: 1; /*!< Use DMA2D to copy user buffer to the frame buffer when necessary */
+        uint32_t disable_lp: 1;/*!< Disable low-power for DPI */
     } flags;                   /*!< Extra configuration flags */
 } esp_lcd_dpi_panel_config_t;
 
@@ -133,6 +138,18 @@ esp_err_t esp_lcd_dpi_panel_get_frame_buffer(esp_lcd_panel_handle_t dpi_panel, u
  */
 esp_err_t esp_lcd_dpi_panel_set_pattern(esp_lcd_panel_handle_t dpi_panel, mipi_dsi_pattern_type_t pattern);
 
+/**
+ * @brief Set color conversion configuration for DPI panel
+ *
+ * @param[in] dpi_panel MIPI DPI panel handle, returned from esp_lcd_new_panel_dpi()
+ * @param[in] config Color conversion configuration
+ * @return
+ *      - ESP_OK: Set color conversion configuration successfully
+ *      - ESP_ERR_INVALID_ARG: Set color conversion configuration failed because of invalid argument
+ *      - ESP_FAIL: Set color conversion configuration failed because of other error
+ */
+esp_err_t esp_lcd_dpi_panel_set_color_conversion(esp_lcd_panel_handle_t dpi_panel, const esp_lcd_color_conv_config_t *config);
+
 /**
  * @brief Type of LCD DPI panel event data
  */
diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c b/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c
index 0851381033e..4c30053ced9 100644
--- a/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c
+++ b/components/esp_lcd/i80/esp_lcd_panel_io_i2s.c
@@ -39,14 +39,12 @@
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/i2s_platform.h"
 #include "esp_private/gdma_link.h"
+#include "esp_private/gpio.h"
 #include "soc/lcd_periph.h"
 #include "hal/i2s_hal.h"
 #include "hal/i2s_ll.h"
 #include "hal/i2s_types.h"
 
-// the DMA descriptor used by esp32 and esp32s2, each descriptor can carry 4095 bytes at most
-#define LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095
-
 static const char *TAG = "lcd_panel.io.i80";
 
 typedef struct esp_lcd_i80_bus_t esp_lcd_i80_bus_t;
@@ -61,7 +59,7 @@ static esp_err_t i2s_lcd_init_dma_link(esp_lcd_i80_bus_handle_t bus);
 static esp_err_t i2s_lcd_configure_gpio(esp_lcd_i80_bus_handle_t bus, const esp_lcd_i80_bus_config_t *bus_config);
 static void i2s_lcd_trigger_quick_trans_done_event(esp_lcd_i80_bus_handle_t bus);
 static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_i80_t *next_device);
-static void lcd_default_isr_handler(void *args);
+static void i2s_lcd_default_isr_handler(void *args);
 static esp_err_t panel_io_i80_register_event_callbacks(esp_lcd_panel_io_handle_t io, const esp_lcd_panel_io_callbacks_t *cbs, void *user_ctx);
 
 struct esp_lcd_i80_bus_t {
@@ -188,7 +186,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc
     int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED;
     ret = esp_intr_alloc_intrstatus(lcd_periph_i2s_signals.buses[bus->bus_id].irq_id, isr_flags,
                                     (uint32_t)i2s_ll_get_intr_status_reg(bus->hal.dev),
-                                    I2S_LL_EVENT_TX_EOF, lcd_default_isr_handler, bus, &bus->intr);
+                                    I2S_LL_EVENT_TX_EOF, i2s_lcd_default_isr_handler, bus, &bus->intr);
     ESP_GOTO_ON_ERROR(ret, err, TAG, "install interrupt failed");
     i2s_ll_enable_intr(bus->hal.dev, I2S_LL_EVENT_TX_EOF, false); // disable interrupt temporarily
     i2s_ll_clear_intr_status(bus->hal.dev, I2S_LL_EVENT_TX_EOF);  // clear pending interrupt
@@ -317,8 +315,8 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p
     if (io_config->cs_gpio_num >= 0) {
         // CS signal is controlled by software
         gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high); // de-assert by default
-        gpio_set_direction(io_config->cs_gpio_num, GPIO_MODE_OUTPUT);
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_config->cs_gpio_num], PIN_FUNC_GPIO);
+        gpio_func_sel(io_config->cs_gpio_num, PIN_FUNC_GPIO);
+        gpio_output_enable(io_config->cs_gpio_num);
     }
     *ret_io = &(i80_device->base);
     ESP_LOGD(TAG, "new i80 lcd panel io @%p on bus(%d), pclk=%"PRIu32"Hz", i80_device, bus->bus_id, i80_device->pclk_hz);
@@ -362,9 +360,8 @@ static esp_err_t panel_io_i80_del(esp_lcd_panel_io_t *io)
     LIST_REMOVE(i80_device, device_list_entry);
     portEXIT_CRITICAL(&bus->spinlock);
 
-    // reset CS GPIO
     if (i80_device->cs_gpio_num >= 0) {
-        gpio_reset_pin(i80_device->cs_gpio_num);
+        gpio_output_disable(i80_device->cs_gpio_num);
     }
 
     ESP_LOGD(TAG, "del i80 lcd panel io @%p", i80_device);
@@ -648,7 +645,7 @@ static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons
     xQueueSend(next_device->trans_queue, &trans_desc, portMAX_DELAY);
     next_device->num_trans_inflight++;
     // enable interrupt and go into isr handler, where we fetch the transactions from trans_queue and start it
-    // we will go into `lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment
+    // we will go into `i2s_lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment
     esp_intr_enable(bus->intr);
     return ESP_OK;
 }
@@ -669,7 +666,7 @@ static esp_err_t i2s_lcd_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c
     // create pm lock based on different clock source
     // clock sources like PLL and XTAL will be turned off in light sleep
 #if CONFIG_PM_ENABLE
-    ESP_RETURN_ON_ERROR(esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "i80_bus_lcd", &bus->pm_lock), TAG, "create pm lock failed");
+    ESP_RETURN_ON_ERROR(esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "i80_bus_lcd", &bus->pm_lock), TAG, "create pm lock failed");
 #endif
     return ESP_OK;
 }
@@ -698,21 +695,20 @@ static esp_err_t i2s_lcd_configure_gpio(esp_lcd_i80_bus_handle_t bus, const esp_
     // connect peripheral signals via GPIO matrix
     // data line
     for (size_t i = 0; i < bus_config->bus_width; i++) {
-        gpio_set_direction(bus_config->data_gpio_nums[i], GPIO_MODE_OUTPUT);
+        gpio_func_sel(bus_config->data_gpio_nums[i], PIN_FUNC_GPIO);
+        // the esp_rom_gpio_connect_out_signal function will also help enable the output path properly
 #if SOC_I2S_TRANS_SIZE_ALIGN_WORD
         esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_i2s_signals.buses[bus_id].data_sigs[i + 8], false, false);
 #else
         esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_i2s_signals.buses[bus_id].data_sigs[i + SOC_I2S_MAX_DATA_WIDTH - bus_config->bus_width], false, false);
 #endif
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->data_gpio_nums[i]], PIN_FUNC_GPIO);
     }
     // WR signal (pclk)
-    gpio_set_direction(bus_config->wr_gpio_num, GPIO_MODE_OUTPUT);
+    gpio_func_sel(bus_config->wr_gpio_num, PIN_FUNC_GPIO);
     esp_rom_gpio_connect_out_signal(bus_config->wr_gpio_num, lcd_periph_i2s_signals.buses[bus_id].wr_sig, true, false);
-    gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->wr_gpio_num], PIN_FUNC_GPIO);
     // DC signal is controlled by software, set as general purpose IO
-    gpio_set_direction(bus_config->dc_gpio_num, GPIO_MODE_OUTPUT);
-    gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[bus_config->dc_gpio_num], PIN_FUNC_GPIO);
+    gpio_func_sel(bus_config->dc_gpio_num, PIN_FUNC_GPIO);
+    gpio_output_enable(bus_config->dc_gpio_num);
     return ESP_OK;
 }
 
@@ -756,7 +752,7 @@ static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_
     bus->cur_device = next_device;
 }
 
-static IRAM_ATTR void lcd_default_isr_handler(void *args)
+static IRAM_ATTR void i2s_lcd_default_isr_handler(void *args)
 {
     esp_lcd_i80_bus_t *bus = (esp_lcd_i80_bus_t *)args;
     lcd_i80_trans_descriptor_t *trans_desc = NULL;
diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c
index 96b8fb4ca8b..d7a29f44504 100644
--- a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c
+++ b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c
@@ -43,8 +43,6 @@
 #include "hal/cache_ll.h"
 #include "hal/cache_hal.h"
 
-#define LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095
-
 #if defined(SOC_GDMA_TRIG_PERIPH_LCD0_BUS) && (SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AHB)
 #define LCD_GDMA_NEW_CHANNEL gdma_new_ahb_channel
 #define LCD_GDMA_DESCRIPTOR_ALIGN 4
@@ -76,7 +74,7 @@ static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c
 static esp_err_t lcd_i80_bus_configure_gpio(esp_lcd_i80_bus_handle_t bus, const esp_lcd_i80_bus_config_t *bus_config);
 static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_i80_t *next_device);
 static void lcd_start_transaction(esp_lcd_i80_bus_t *bus, lcd_i80_trans_descriptor_t *trans_desc);
-static void lcd_default_isr_handler(void *args);
+static void i80_lcd_default_isr_handler(void *args);
 static esp_err_t panel_io_i80_register_event_callbacks(esp_lcd_panel_io_handle_t io, const esp_lcd_panel_io_callbacks_t *cbs, void *user_ctx);
 
 struct esp_lcd_i80_bus_t {
@@ -157,18 +155,6 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc
     // allocate i80 bus memory
     bus = heap_caps_calloc(1, sizeof(esp_lcd_i80_bus_t), LCD_I80_MEM_ALLOC_CAPS);
     ESP_GOTO_ON_FALSE(bus, ESP_ERR_NO_MEM, err, TAG, "no mem for i80 bus");
-    size_t num_dma_nodes = bus_config->max_transfer_bytes / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1;
-    // create DMA link list
-    gdma_link_list_config_t dma_link_config = {
-        .buffer_alignment = 1, // no special buffer alignment for LCD TX buffer
-        .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN,
-        .num_items = num_dma_nodes,
-        .flags = {
-            .check_owner = true,
-        },
-    };
-    ESP_GOTO_ON_ERROR(gdma_new_link_list(&dma_link_config, &bus->dma_link), err, TAG, "create DMA link list failed");
-    bus->num_dma_nodes = num_dma_nodes;
     bus->bus_width = bus_config->bus_width;
     bus->bus_id = -1;
     // allocate the format buffer from internal memory, with DMA capability
@@ -208,7 +194,7 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc
     int isr_flags = LCD_I80_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED;
     ret = esp_intr_alloc_intrstatus(lcd_periph_i80_signals.buses[bus_id].irq_id, isr_flags,
                                     (uint32_t)lcd_ll_get_interrupt_status_reg(bus->hal.dev),
-                                    LCD_LL_EVENT_TRANS_DONE, lcd_default_isr_handler, bus, &bus->intr);
+                                    LCD_LL_EVENT_TRANS_DONE, i80_lcd_default_isr_handler, bus, &bus->intr);
     ESP_GOTO_ON_ERROR(ret, err, TAG, "install interrupt failed");
     lcd_ll_enable_interrupt(bus->hal.dev, LCD_LL_EVENT_TRANS_DONE, false); // disable all interrupts
     lcd_ll_clear_interrupt_status(bus->hal.dev, UINT32_MAX); // clear pending interrupt
@@ -355,9 +341,10 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p
     // we only configure the CS GPIO as output, don't connect to the peripheral signal at the moment
     // we will connect the CS GPIO to peripheral signal when switching devices in lcd_i80_switch_devices()
     if (io_config->cs_gpio_num >= 0) {
-        gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high);
-        gpio_set_direction(io_config->cs_gpio_num, GPIO_MODE_OUTPUT);
+        // CS signal is controlled by software
+        gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high); // de-assert by default
         gpio_func_sel(io_config->cs_gpio_num, PIN_FUNC_GPIO);
+        gpio_output_enable(io_config->cs_gpio_num);
     }
     *ret_io = &(i80_device->base);
     ESP_LOGD(TAG, "new i80 lcd panel io @%p on bus(%d)", i80_device, bus->bus_id);
@@ -393,9 +380,8 @@ static esp_err_t panel_io_i80_del(esp_lcd_panel_io_t *io)
     LIST_REMOVE(i80_device, device_list_entry);
     portEXIT_CRITICAL(&bus->spinlock);
 
-    // reset CS to normal GPIO
     if (i80_device->cs_gpio_num >= 0) {
-        gpio_reset_pin(i80_device->cs_gpio_num);
+        gpio_output_disable(i80_device->cs_gpio_num);
     }
 
     ESP_LOGD(TAG, "del i80 lcd panel io @%p", i80_device);
@@ -572,7 +558,7 @@ static esp_err_t panel_io_i80_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons
     xQueueSend(i80_device->trans_queue, &trans_desc, portMAX_DELAY);
     i80_device->num_trans_inflight++;
     // enable interrupt and go into isr handler, where we fetch the transactions from trans_queue and start it
-    // we will go into `lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment
+    // we will go into `i80_lcd_default_isr_handler` almost at once, because the "trans done" event is active at the moment
     esp_intr_enable(bus->intr);
     return ESP_OK;
 }
@@ -609,7 +595,7 @@ static esp_err_t lcd_i80_init_dma_link(esp_lcd_i80_bus_handle_t bus, const esp_l
         .direction = GDMA_CHANNEL_DIRECTION_TX,
     };
     ret = LCD_GDMA_NEW_CHANNEL(&dma_chan_config, &bus->dma_chan);
-    ESP_GOTO_ON_ERROR(ret, err, TAG, "alloc DMA channel failed");
+    ESP_RETURN_ON_ERROR(ret, TAG, "alloc DMA channel failed");
     gdma_connect(bus->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0));
     gdma_strategy_config_t strategy_config = {
         .auto_update_desc = true,
@@ -621,14 +607,23 @@ static esp_err_t lcd_i80_init_dma_link(esp_lcd_i80_bus_handle_t bus, const esp_l
         .max_data_burst_size = bus_config->dma_burst_size ? bus_config->dma_burst_size : 16, // Enable DMA burst transfer for better performance
         .access_ext_mem = true, // the LCD can carry pixel buffer from the external memory
     };
-    ESP_GOTO_ON_ERROR(gdma_config_transfer(bus->dma_chan, &trans_cfg), err, TAG, "config DMA transfer failed");
+    ESP_RETURN_ON_ERROR(gdma_config_transfer(bus->dma_chan, &trans_cfg), TAG, "config DMA transfer failed");
     gdma_get_alignment_constraints(bus->dma_chan, &bus->int_mem_align, &bus->ext_mem_align);
+
+    size_t num_dma_nodes = bus_config->max_transfer_bytes / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE + 1;
+    // create DMA link list
+    gdma_link_list_config_t dma_link_config = {
+        .buffer_alignment = MAX(bus->int_mem_align, bus->ext_mem_align),
+        .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN,
+        .num_items = num_dma_nodes,
+        .flags = {
+            .check_owner = true,
+        },
+    };
+    ESP_RETURN_ON_ERROR(gdma_new_link_list(&dma_link_config, &bus->dma_link), TAG, "create DMA link list failed");
+    bus->num_dma_nodes = num_dma_nodes;
+
     return ESP_OK;
-err:
-    if (bus->dma_chan) {
-        gdma_del_channel(bus->dma_chan);
-    }
-    return ret;
 }
 
 void *esp_lcd_i80_alloc_draw_buffer(esp_lcd_panel_io_handle_t io, size_t size, uint32_t caps)
@@ -660,17 +655,18 @@ static esp_err_t lcd_i80_bus_configure_gpio(esp_lcd_i80_bus_handle_t bus, const
     // Set the number of output data lines
     lcd_ll_set_data_wire_width(bus->hal.dev, bus_config->bus_width);
     // connect peripheral signals via GPIO matrix
+    // data lines
     for (size_t i = 0; i < bus_config->bus_width; i++) {
-        gpio_set_direction(bus_config->data_gpio_nums[i], GPIO_MODE_OUTPUT);
-        esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_i80_signals.buses[bus_id].data_sigs[i], false, false);
         gpio_func_sel(bus_config->data_gpio_nums[i], PIN_FUNC_GPIO);
+        // the esp_rom_gpio_connect_out_signal function will also help enable the output path properly
+        esp_rom_gpio_connect_out_signal(bus_config->data_gpio_nums[i], lcd_periph_i80_signals.buses[bus_id].data_sigs[i], false, false);
     }
-    gpio_set_direction(bus_config->dc_gpio_num, GPIO_MODE_OUTPUT);
-    esp_rom_gpio_connect_out_signal(bus_config->dc_gpio_num, lcd_periph_i80_signals.buses[bus_id].dc_sig, false, false);
+    // D/C signal
     gpio_func_sel(bus_config->dc_gpio_num, PIN_FUNC_GPIO);
-    gpio_set_direction(bus_config->wr_gpio_num, GPIO_MODE_OUTPUT);
-    esp_rom_gpio_connect_out_signal(bus_config->wr_gpio_num, lcd_periph_i80_signals.buses[bus_id].wr_sig, false, false);
+    esp_rom_gpio_connect_out_signal(bus_config->dc_gpio_num, lcd_periph_i80_signals.buses[bus_id].dc_sig, false, false);
+    // WR signal (PCLK)
     gpio_func_sel(bus_config->wr_gpio_num, PIN_FUNC_GPIO);
+    esp_rom_gpio_connect_out_signal(bus_config->wr_gpio_num, lcd_periph_i80_signals.buses[bus_id].wr_sig, false, false);
     return ESP_OK;
 }
 
@@ -722,8 +718,7 @@ static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_
         lcd_ll_set_dc_level(bus->hal.dev, next_device->dc_levels.dc_idle_level, next_device->dc_levels.dc_cmd_level,
                             next_device->dc_levels.dc_dummy_level, next_device->dc_levels.dc_data_level);
         if (cur_device && cur_device->cs_gpio_num >= 0) {
-            // disconnect current CS GPIO from peripheral signal
-            esp_rom_gpio_connect_out_signal(cur_device->cs_gpio_num, SIG_GPIO_OUT_IDX, false, false);
+            gpio_output_disable(cur_device->cs_gpio_num);
         }
         if (next_device->cs_gpio_num >= 0) {
             // connect CS signal to the new device
@@ -733,7 +728,7 @@ static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_
     }
 }
 
-IRAM_ATTR static void lcd_default_isr_handler(void *args)
+IRAM_ATTR static void i80_lcd_default_isr_handler(void *args)
 {
     esp_lcd_i80_bus_t *bus = (esp_lcd_i80_bus_t *)args;
     lcd_i80_trans_descriptor_t *trans_desc = NULL;
diff --git a/components/esp_lcd/include/esp_lcd_io_i2c.h b/components/esp_lcd/include/esp_lcd_io_i2c.h
index 7d1b0fc02c9..e98f18acbd7 100644
--- a/components/esp_lcd/include/esp_lcd_io_i2c.h
+++ b/components/esp_lcd/include/esp_lcd_io_i2c.h
@@ -83,9 +83,9 @@ esp_err_t esp_lcd_new_panel_io_i2c_v2(i2c_master_bus_handle_t bus, const esp_lcd
  *          - ESP_ERR_NO_MEM        if out of memory
  *          - ESP_OK                on success
  */
-static inline void esp_lcd_new_panel_io_i2c(uint32_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io)
+static inline esp_err_t esp_lcd_new_panel_io_i2c(uint32_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io)
 {
-    esp_lcd_new_panel_io_i2c_v1(bus, io_config, ret_io);
+    return esp_lcd_new_panel_io_i2c_v1(bus, io_config, ret_io);
 }
 
 /**
@@ -99,9 +99,9 @@ static inline void esp_lcd_new_panel_io_i2c(uint32_t bus, const esp_lcd_panel_io
  *          - ESP_ERR_NO_MEM        if out of memory
  *          - ESP_OK                on success
  */
-static inline void esp_lcd_new_panel_io_i2c(i2c_master_bus_handle_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io)
+static inline esp_err_t esp_lcd_new_panel_io_i2c(i2c_master_bus_handle_t bus, const esp_lcd_panel_io_i2c_config_t *io_config, esp_lcd_panel_io_handle_t *ret_io)
 {
-    esp_lcd_new_panel_io_i2c_v2(bus, io_config, ret_io);
+    return esp_lcd_new_panel_io_i2c_v2(bus, io_config, ret_io);
 }
 #else
 /**
diff --git a/components/esp_lcd/include/esp_lcd_io_i80.h b/components/esp_lcd/include/esp_lcd_io_i80.h
index 7b6bd90422f..f2885390f5f 100644
--- a/components/esp_lcd/include/esp_lcd_io_i80.h
+++ b/components/esp_lcd/include/esp_lcd_io_i80.h
@@ -30,7 +30,7 @@ typedef struct {
     size_t bus_width;          /*!< Number of data lines, 8 or 16 */
     size_t max_transfer_bytes; /*!< Maximum transfer size, this determines the length of internal DMA link */
     union {
-        size_t psram_trans_align;  /*!< DMA transfer alignment for data allocated from PSRAM */
+        size_t psram_trans_align __attribute__((deprecated)); /*!< DMA transfer alignment for data allocated from PSRAM */
         size_t dma_burst_size;     /*!< DMA burst size, in bytes */
     };
     size_t sram_trans_align __attribute__((deprecated)); /*!< DMA transfer alignment for data allocated from SRAM */
diff --git a/components/esp_lcd/include/esp_lcd_types.h b/components/esp_lcd/include/esp_lcd_types.h
index ca15370b93d..2de4306ba2a 100644
--- a/components/esp_lcd/include/esp_lcd_types.h
+++ b/components/esp_lcd/include/esp_lcd_types.h
@@ -75,6 +75,22 @@ typedef struct {
     esp_lcd_panel_io_color_trans_done_cb_t on_color_trans_done; /*!< Callback invoked when color data transfer has finished */
 } esp_lcd_panel_io_callbacks_t;
 
+/**
+ * @brief Configuration of LCD color conversion
+ */
+typedef struct {
+    lcd_color_range_t in_color_range;    /*!< Color range of the input color */
+    lcd_color_range_t out_color_range;   /*!< Color range of the output color */
+    union {
+        struct {
+            lcd_yuv_conv_std_t conv_std; /*!< YUV conversion standard: BT601, BT709 */
+            struct {
+                lcd_yuv422_pack_order_t in_pack_order; /*!< YUV422 packing order of the input color */
+            } yuv422; /*!< YUV422 specific */
+        } yuv; /*!< YUV specific */
+    } spec; /*!< Extra configuration for specific color conversion */
+} esp_lcd_color_conv_config_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_lcd/interface/esp_lcd_panel_io_interface.h b/components/esp_lcd/interface/esp_lcd_panel_io_interface.h
index 781eb1dd3f4..0a4334f6fad 100644
--- a/components/esp_lcd/interface/esp_lcd_panel_io_interface.h
+++ b/components/esp_lcd/interface/esp_lcd_panel_io_interface.h
@@ -7,7 +7,7 @@
 
 #include <stdbool.h>
 #include "esp_err.h"
-#include "esp_lcd_panel_io.h"
+#include "esp_lcd_types.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/esp_lcd/linker.lf b/components/esp_lcd/linker.lf
index 6e3aa0d3cda..f66d088f22d 100644
--- a/components/esp_lcd/linker.lf
+++ b/components/esp_lcd/linker.lf
@@ -1,8 +1,15 @@
-[mapping:esp_lcd_driver]
-archive: libesp_lcd.a
+[mapping:esp_lcd_gdma]
+archive: libesp_hw_support.a
 entries:
     if LCD_RGB_ISR_IRAM_SAFE = y:
-        esp_lcd_common: lcd_com_mount_dma_data (noflash)
+        gdma: gdma_reset (noflash)
+        gdma: gdma_start (noflash)
+        gdma_link: gdma_link_get_head_addr (noflash)
+    if LCD_DSI_ISR_IRAM_SAFE = y:
+        dw_gdma: dw_gdma_link_list_get_item (noflash)
+        dw_gdma: dw_gdma_lli_set_block_markers (noflash)
+        dw_gdma: dw_gdma_channel_use_link_list (noflash)
+        dw_gdma: dw_gdma_channel_enable_ctrl (noflash)
 
 [mapping:esp_lcd_hal]
 archive: libhal.a
diff --git a/components/esp_lcd/priv_include/esp_lcd_common.h b/components/esp_lcd/priv_include/esp_lcd_common.h
index a7b8ae6161e..64546727ef3 100644
--- a/components/esp_lcd/priv_include/esp_lcd_common.h
+++ b/components/esp_lcd/priv_include/esp_lcd_common.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,6 +33,8 @@ extern "C" {
 #define LCD_CLOCK_SRC_ATOMIC()
 #endif
 
+#define LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095
+
 #if SOC_LCDCAM_SUPPORTED
 
 typedef enum {
@@ -58,15 +60,6 @@ int lcd_com_register_device(lcd_com_device_type_t device_type, void *device_obj)
 void lcd_com_remove_device(lcd_com_device_type_t device_type, int member_id);
 #endif // SOC_LCDCAM_SUPPORTED
 
-/**
- * @brief Mount data to DMA descriptors
- *
- * @param desc_head Point to the head of DMA descriptor chain
- * @param buffer Data buffer
- * @param len Size of the data buffer, in bytes
- */
-void lcd_com_mount_dma_data(dma_descriptor_t *desc_head, const void *buffer, size_t len);
-
 /**
  * @brief Reverse the bytes in the buffer
  *
diff --git a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c
index 60165fc1c53..25cb52db289 100644
--- a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c
+++ b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c
@@ -17,7 +17,6 @@
 #endif
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
-#include "freertos/semphr.h"
 #include "esp_attr.h"
 #include "esp_check.h"
 #include "esp_pm.h"
@@ -28,43 +27,50 @@
 #include "soc/soc_caps.h"
 #include "esp_clk_tree.h"
 #include "hal/dma_types.h"
-#include "hal/gpio_hal.h"
-#include "esp_private/gdma.h"
 #include "driver/gpio.h"
 #include "esp_bit_defs.h"
 #include "esp_private/esp_clk_tree_common.h"
+#include "esp_private/gdma.h"
+#include "esp_private/gdma_link.h"
 #include "esp_private/periph_ctrl.h"
+#include "esp_private/gpio.h"
 #include "esp_psram.h"
 #include "esp_lcd_common.h"
+#include "esp_cache.h"
 #include "esp_memory_utils.h"
 #include "soc/lcd_periph.h"
-#include "soc/soc_caps.h"
+#include "soc/io_mux_reg.h"
 #include "hal/lcd_hal.h"
 #include "hal/lcd_ll.h"
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
-#include "rom/cache.h"
-#include "esp_cache.h"
+#include "rgb_lcd_rotation_sw.h"
+
+// hardware issue workaround
+#if CONFIG_IDF_TARGET_ESP32S3
+#define RGB_LCD_NEEDS_SEPARATE_RESTART_LINK 1
+#endif
 
 #if CONFIG_LCD_RGB_ISR_IRAM_SAFE
 #define LCD_RGB_INTR_ALLOC_FLAGS     (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED)
+#define LCD_RGB_MEM_ALLOC_CAPS       (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
 #else
 #define LCD_RGB_INTR_ALLOC_FLAGS     ESP_INTR_FLAG_INTRDISABLED
+#define LCD_RGB_MEM_ALLOC_CAPS       MALLOC_CAP_DEFAULT
+#endif
+
+#if defined(SOC_GDMA_TRIG_PERIPH_LCD0_BUS) && (SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AHB)
+#define LCD_GDMA_NEW_CHANNEL gdma_new_ahb_channel
+#define LCD_GDMA_DESCRIPTOR_ALIGN 4
+#elif defined(SOC_GDMA_TRIG_PERIPH_LCD0_BUS) && (SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AXI)
+#define LCD_GDMA_NEW_CHANNEL gdma_new_axi_channel
+#define LCD_GDMA_DESCRIPTOR_ALIGN 8
+#else
+#error "Unsupported GDMA bus type for RGB LCD"
 #endif
 
 #define RGB_LCD_PANEL_MAX_FB_NUM         3 // maximum supported frame buffer number
 #define RGB_LCD_PANEL_BOUNCE_BUF_NUM     2 // bounce buffer number
-#define RGB_LCD_PANEL_DMA_LINKS_REPLICA  MAX(RGB_LCD_PANEL_MAX_FB_NUM, RGB_LCD_PANEL_BOUNCE_BUF_NUM)
-
-#define RGB_PANEL_SWAP_XY  0
-#define RGB_PANEL_MIRROR_Y 1
-#define RGB_PANEL_MIRROR_X 2
-
-typedef enum {
-    ROTATE_MASK_SWAP_XY = BIT(RGB_PANEL_SWAP_XY),
-    ROTATE_MASK_MIRROR_Y = BIT(RGB_PANEL_MIRROR_Y),
-    ROTATE_MASK_MIRROR_X = BIT(RGB_PANEL_MIRROR_X),
-} panel_rotate_mask_t;
 
 static const char *TAG = "lcd_panel.rgb";
 
@@ -79,12 +85,12 @@ static esp_err_t rgb_panel_mirror(esp_lcd_panel_t *panel, bool mirror_x, bool mi
 static esp_err_t rgb_panel_swap_xy(esp_lcd_panel_t *panel, bool swap_axes);
 static esp_err_t rgb_panel_set_gap(esp_lcd_panel_t *panel, int x_gap, int y_gap);
 static esp_err_t rgb_panel_disp_on_off(esp_lcd_panel_t *panel, bool off);
-static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_clock_source_t clk_src);
-static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *panel);
-static void lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *panel);
-static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_lcd_rgb_panel_config_t *panel_config);
+static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *rgb_panel, lcd_clock_source_t clk_src);
+static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *rgb_panel);
+static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel);
+static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *rgb_panel, const esp_lcd_rgb_panel_config_t *panel_config);
 static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel);
-static void lcd_default_isr_handler(void *args);
+static void rgb_lcd_default_isr_handler(void *args);
 
 struct esp_rgb_panel_t {
     esp_lcd_panel_t base;  // Base class of generic lcd panel
@@ -99,22 +105,30 @@ struct esp_rgb_panel_t {
     intr_handle_t intr;    // LCD peripheral interrupt handle
     esp_pm_lock_handle_t pm_lock; // Power management lock
     size_t num_dma_nodes;  // Number of DMA descriptors that used to carry the frame buffer
+    gdma_channel_handle_t dma_chan; // DMA channel handle
+    gdma_link_list_handle_t dma_fb_links[RGB_LCD_PANEL_MAX_FB_NUM]; // DMA link lists for multiple frame buffers
+    gdma_link_list_handle_t dma_bb_link; // DMA link list for bounce buffer
+#if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK
+    gdma_link_list_handle_t dma_restart_link; // DMA link list for restarting the DMA
+#endif
     uint8_t *fbs[RGB_LCD_PANEL_MAX_FB_NUM]; // Frame buffers
+    uint8_t *bounce_buffer[RGB_LCD_PANEL_BOUNCE_BUF_NUM]; // Pointer to the bounce buffers
+    size_t fb_size;        // Size of frame buffer, in bytes
+    size_t bb_size;        // Size of the bounce buffer, in bytes. If not-zero, the driver uses two bounce buffers allocated from internal memory
     uint8_t cur_fb_index;  // Current frame buffer index
     uint8_t bb_fb_index;  // Current frame buffer index which used by bounce buffer
-    size_t fb_size;        // Size of frame buffer, in bytes
-    int data_gpio_nums[SOC_LCD_RGB_DATA_WIDTH]; // GPIOs used for data lines, we keep these GPIOs for action like "invert_color"
+    size_t int_mem_align;  // DMA buffer alignment for internal memory
+    size_t ext_mem_align;  // DMA buffer alignment for external memory
+    int data_gpio_nums[SOC_LCDCAM_RGB_DATA_WIDTH]; // GPIOs used for data lines, we keep these GPIOs for action like "invert_color"
     uint32_t src_clk_hz;   // Peripheral source clock resolution
     esp_lcd_rgb_timing_t timings;   // RGB timing parameters (e.g. pclk, sync pulse, porch width)
-    size_t bb_size;                 // Size of the bounce buffer, in bytes. If not-zero, the driver uses two bounce buffers allocated from internal memory
     int bounce_pos_px;              // Position in whatever source material is used for the bounce buffer, in pixels
-    uint8_t *bounce_buffer[RGB_LCD_PANEL_BOUNCE_BUF_NUM]; // Pointer to the bounce buffers
     size_t bb_eof_count;            // record the number we received the DMA EOF event, compare with `expect_eof_count` in the VSYNC_END ISR
     size_t expect_eof_count;        // record the number of DMA EOF event we expected to receive
-    gdma_channel_handle_t dma_chan; // DMA channel handle
+    esp_lcd_rgb_panel_draw_buf_complete_cb_t on_color_trans_done; // draw buffer completes
+    esp_lcd_rgb_panel_frame_buf_complete_cb_t on_frame_buf_complete; // callback used to notify when the bounce buffer finish copying the entire frame
     esp_lcd_rgb_panel_vsync_cb_t on_vsync; // VSYNC event callback
     esp_lcd_rgb_panel_bounce_buf_fill_cb_t on_bounce_empty; // callback used to fill a bounce buffer rather than copying from the frame buffer
-    esp_lcd_rgb_panel_bounce_buf_finish_cb_t on_bounce_frame_finish; // callback used to notify when the bounce buffer finish copying the entire frame
     void *user_ctx;                 // Reserved user's data of callback functions
     int x_gap;                      // Extra gap in x coordinate, it's used when calculate the flush window
     int y_gap;                      // Extra gap in y coordinate, it's used when calculate the flush window
@@ -127,67 +141,55 @@ struct esp_rgb_panel_t {
         uint32_t fb_in_psram: 1;         // Whether the frame buffer is in PSRAM
         uint32_t need_update_pclk: 1;    // Whether to update the PCLK before start a new transaction
         uint32_t need_restart: 1;        // Whether to restart the LCD controller and the DMA
-        uint32_t bb_invalidate_cache: 1; // Whether to do cache invalidation in bounce buffer mode
+        uint32_t fb_behind_cache: 1;     // Whether the frame buffer is behind the cache
+        uint32_t bb_behind_cache: 1;     // Whether the bounce buffer is behind the cache
     } flags;
-    dma_descriptor_t *dma_links[RGB_LCD_PANEL_DMA_LINKS_REPLICA]; // fbs[0] <-> dma_links[0], fbs[1] <-> dma_links[1], etc
-    dma_descriptor_t dma_restart_node; // DMA descriptor used to restart the transfer
-    dma_descriptor_t dma_nodes[];      // DMA descriptors pool
 };
 
-static esp_err_t lcd_rgb_panel_alloc_frame_buffers(const esp_lcd_rgb_panel_config_t *rgb_panel_config, esp_rgb_panel_t *rgb_panel)
+static esp_err_t lcd_rgb_panel_alloc_frame_buffers(esp_rgb_panel_t *rgb_panel)
 {
-    bool fb_in_psram = false;
-    size_t ext_mem_align = 0;
-    size_t int_mem_align = 0;
-    gdma_get_alignment_constraints(rgb_panel->dma_chan, &int_mem_align, &ext_mem_align);
+    bool fb_in_psram = rgb_panel->flags.fb_in_psram;
 
-    // also take the cache line size into account when allocating the frame buffer
-    uint32_t ext_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
+    // read the cache line size of internal and external memory, we use this information to check if the allocated memory is behind the cache
     uint32_t int_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
-    // The buffer must be aligned to the cache line size
-    if (ext_mem_cache_line_size) {
-        ext_mem_align = MAX(ext_mem_align, ext_mem_cache_line_size);
-    }
-    if (int_mem_cache_line_size) {
-        int_mem_align = MAX(int_mem_align, int_mem_cache_line_size);
-    }
+    uint32_t ext_mem_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_DATA);
 
     // alloc frame buffer
-    if (rgb_panel->num_fbs > 0) {
-        // fb_in_psram is only an option, if there's no PSRAM on board, we fallback to alloc from SRAM
-        if (rgb_panel_config->flags.fb_in_psram) {
-#if CONFIG_SPIRAM_USE_MALLOC || CONFIG_SPIRAM_USE_CAPS_ALLOC
-            if (esp_psram_is_initialized()) {
-                fb_in_psram = true;
-            }
-#endif
+    for (int i = 0; i < rgb_panel->num_fbs; i++) {
+        if (fb_in_psram) {
+            // the allocated buffer is also aligned to the cache line size
+            rgb_panel->fbs[i] = heap_caps_aligned_calloc(rgb_panel->ext_mem_align, 1, rgb_panel->fb_size,
+                                                         MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
+            ESP_RETURN_ON_FALSE(rgb_panel->fbs[i], ESP_ERR_NO_MEM, TAG, "no mem for frame buffer");
+            rgb_panel->flags.fb_behind_cache = ext_mem_cache_line_size > 0;
+        } else {
+            rgb_panel->fbs[i] = heap_caps_aligned_calloc(rgb_panel->int_mem_align, 1, rgb_panel->fb_size,
+                                                         MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
+            ESP_RETURN_ON_FALSE(rgb_panel->fbs[i], ESP_ERR_NO_MEM, TAG, "no mem for frame buffer");
+            rgb_panel->flags.fb_behind_cache = int_mem_cache_line_size > 0;
         }
-        for (int i = 0; i < rgb_panel->num_fbs; i++) {
-            if (fb_in_psram) {
-                // the low level malloc function will help check the validation of alignment
-                rgb_panel->fbs[i] = heap_caps_aligned_calloc(ext_mem_align, 1, rgb_panel->fb_size, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
-                ESP_RETURN_ON_FALSE(rgb_panel->fbs[i], ESP_ERR_NO_MEM, TAG, "no mem for frame buffer");
-                // calloc not only allocates but also zero's the buffer. We have to make sure this is
-                // properly committed to the PSRAM, otherwise all sorts of visual corruption will happen.
-                ESP_RETURN_ON_ERROR(esp_cache_msync(rgb_panel->fbs[i], rgb_panel->fb_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M), TAG, "cache write back failed");
-            } else {
-                rgb_panel->fbs[i] = heap_caps_aligned_calloc(int_mem_align, 1, rgb_panel->fb_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
-                ESP_RETURN_ON_FALSE(rgb_panel->fbs[i], ESP_ERR_NO_MEM, TAG, "no mem for frame buffer");
-            }
+        // flush data from cache to the physical memory
+        if (rgb_panel->flags.fb_behind_cache) {
+            esp_cache_msync(rgb_panel->fbs[i], rgb_panel->fb_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
         }
     }
 
     // alloc bounce buffer
     if (rgb_panel->bb_size) {
         for (int i = 0; i < RGB_LCD_PANEL_BOUNCE_BUF_NUM; i++) {
-            // bounce buffer must come from SRAM
-            rgb_panel->bounce_buffer[i] = heap_caps_aligned_calloc(int_mem_align, 1, rgb_panel->bb_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
+            // bounce buffer must be allocated from internal memory for performance
+            rgb_panel->bounce_buffer[i] = heap_caps_aligned_calloc(rgb_panel->int_mem_align, 1, rgb_panel->bb_size,
+                                                                   MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
             ESP_RETURN_ON_FALSE(rgb_panel->bounce_buffer[i], ESP_ERR_NO_MEM, TAG, "no mem for bounce buffer");
+            if (int_mem_cache_line_size > 0) {
+                // flush data from cache to the physical memory
+                esp_cache_msync(rgb_panel->bounce_buffer[i], rgb_panel->bb_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
+                rgb_panel->flags.bb_behind_cache = true;
+            }
         }
     }
     rgb_panel->cur_fb_index = 0;
     rgb_panel->bb_fb_index = 0;
-    rgb_panel->flags.fb_in_psram = fb_in_psram;
 
     return ESP_OK;
 }
@@ -205,21 +207,31 @@ static esp_err_t lcd_rgb_panel_destroy(esp_rgb_panel_t *rgb_panel)
         }
         lcd_com_remove_device(LCD_COM_DEVICE_TYPE_RGB, rgb_panel->panel_id);
     }
-    for (size_t i = 0; i < rgb_panel->num_fbs; i++) {
+    if (rgb_panel->dma_chan) {
+        gdma_disconnect(rgb_panel->dma_chan);
+        gdma_del_channel(rgb_panel->dma_chan);
+    }
+    for (size_t i = 0; i < RGB_LCD_PANEL_MAX_FB_NUM; i++) {
         if (rgb_panel->fbs[i]) {
             free(rgb_panel->fbs[i]);
         }
+        if (rgb_panel->dma_fb_links[i]) {
+            gdma_del_link_list(rgb_panel->dma_fb_links[i]);
+        }
     }
-    if (rgb_panel->bounce_buffer[0]) {
-        free(rgb_panel->bounce_buffer[0]);
+    for (int i = 0; i < RGB_LCD_PANEL_BOUNCE_BUF_NUM; i++) {
+        if (rgb_panel->bounce_buffer[i]) {
+            free(rgb_panel->bounce_buffer[i]);
+        }
     }
-    if (rgb_panel->bounce_buffer[1]) {
-        free(rgb_panel->bounce_buffer[1]);
+    if (rgb_panel->dma_bb_link) {
+        gdma_del_link_list(rgb_panel->dma_bb_link);
     }
-    if (rgb_panel->dma_chan) {
-        gdma_disconnect(rgb_panel->dma_chan);
-        gdma_del_channel(rgb_panel->dma_chan);
+#if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK
+    if (rgb_panel->dma_restart_link) {
+        gdma_del_link_list(rgb_panel->dma_restart_link);
     }
+#endif
     if (rgb_panel->intr) {
         esp_intr_free(rgb_panel->intr);
     }
@@ -240,7 +252,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
     esp_rgb_panel_t *rgb_panel = NULL;
     ESP_RETURN_ON_FALSE(rgb_panel_config && ret_panel, ESP_ERR_INVALID_ARG, TAG, "invalid parameter");
     size_t data_width = rgb_panel_config->data_width;
-    ESP_RETURN_ON_FALSE((data_width >= 8) && (data_width <= SOC_LCD_RGB_DATA_WIDTH) && ((data_width & (data_width - 1)) == 0), ESP_ERR_INVALID_ARG,
+    ESP_RETURN_ON_FALSE((data_width > 0) && (data_width <= SOC_LCDCAM_RGB_DATA_WIDTH) && ((data_width % 8) == 0), ESP_ERR_INVALID_ARG,
                         TAG, "unsupported data width %d", data_width);
     ESP_RETURN_ON_FALSE(!(rgb_panel_config->flags.double_fb && rgb_panel_config->flags.no_fb),
                         ESP_ERR_INVALID_ARG, TAG, "double_fb conflicts with no_fb");
@@ -250,8 +262,6 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
                         ESP_ERR_INVALID_ARG, TAG, "num_fbs conflicts with no_fb");
     ESP_RETURN_ON_FALSE(!(rgb_panel_config->flags.no_fb && rgb_panel_config->bounce_buffer_size_px == 0),
                         ESP_ERR_INVALID_ARG, TAG, "must set bounce buffer if there's no frame buffer");
-    ESP_RETURN_ON_FALSE(!(rgb_panel_config->flags.refresh_on_demand && rgb_panel_config->bounce_buffer_size_px),
-                        ESP_ERR_INVALID_ARG, TAG, "refresh on demand is not supported under bounce buffer mode");
 
     // determine number of framebuffers
     size_t num_fbs = 1;
@@ -275,33 +285,22 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
     size_t bb_size = rgb_panel_config->bounce_buffer_size_px * fb_bits_per_pixel / 8;
     size_t expect_bb_eof_count = 0;
     if (bb_size) {
-        // we want the bounce can always end in the second buffer
-        ESP_RETURN_ON_FALSE(fb_size % (2 * bb_size) == 0, ESP_ERR_INVALID_ARG, TAG,
-                            "fb size must be even multiple of bounce buffer size");
+        ESP_RETURN_ON_FALSE(fb_size % bb_size == 0, ESP_ERR_INVALID_ARG, TAG, "frame buffer size must be multiple of bounce buffer size");
         expect_bb_eof_count = fb_size / bb_size;
     }
 
     // calculate the number of DMA descriptors
     size_t num_dma_nodes = 0;
-    if (bb_size) {
-        // in bounce buffer mode, DMA is used to convey the bounce buffer, not the frame buffer.
-        // frame buffer is copied to bounce buffer by CPU
-        num_dma_nodes = (bb_size + DMA_DESCRIPTOR_BUFFER_MAX_SIZE - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
-    } else {
-        // Not bounce buffer mode, DMA descriptors need to fit the entire frame buffer
-        num_dma_nodes = (fb_size + DMA_DESCRIPTOR_BUFFER_MAX_SIZE - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
-    }
-
-    // DMA descriptors must be placed in internal SRAM (requested by DMA)
-    rgb_panel = heap_caps_calloc(1, sizeof(esp_rgb_panel_t) + num_dma_nodes * sizeof(dma_descriptor_t) * RGB_LCD_PANEL_DMA_LINKS_REPLICA,
-                                 MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+    // allocate memory for rgb panel
+    rgb_panel = heap_caps_calloc(1, sizeof(esp_rgb_panel_t), LCD_RGB_MEM_ALLOC_CAPS);
     ESP_GOTO_ON_FALSE(rgb_panel, ESP_ERR_NO_MEM, err, TAG, "no mem for rgb panel");
+    rgb_panel->panel_id = -1;
     rgb_panel->num_dma_nodes = num_dma_nodes;
     rgb_panel->num_fbs = num_fbs;
     rgb_panel->fb_size = fb_size;
     rgb_panel->bb_size = bb_size;
+    rgb_panel->fb_bits_per_pixel = fb_bits_per_pixel;
     rgb_panel->expect_eof_count = expect_bb_eof_count;
-    rgb_panel->panel_id = -1;
     // register to platform
     int panel_id = lcd_com_register_device(LCD_COM_DEVICE_TYPE_RGB, rgb_panel);
     ESP_GOTO_ON_FALSE(panel_id >= 0, ESP_ERR_NOT_FOUND, err, TAG, "no free rgb panel slot");
@@ -336,20 +335,20 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
     int isr_flags = LCD_RGB_INTR_ALLOC_FLAGS | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_LOWMED;
     ret = esp_intr_alloc_intrstatus(lcd_periph_rgb_signals.panels[panel_id].irq_id, isr_flags,
                                     (uint32_t)lcd_ll_get_interrupt_status_reg(rgb_panel->hal.dev),
-                                    LCD_LL_EVENT_VSYNC_END, lcd_default_isr_handler, rgb_panel, &rgb_panel->intr);
+                                    LCD_LL_EVENT_VSYNC_END, rgb_lcd_default_isr_handler, rgb_panel, &rgb_panel->intr);
     ESP_GOTO_ON_ERROR(ret, err, TAG, "install interrupt failed");
     lcd_ll_enable_interrupt(rgb_panel->hal.dev, LCD_LL_EVENT_VSYNC_END, false); // disable all interrupts
     lcd_ll_clear_interrupt_status(rgb_panel->hal.dev, UINT32_MAX); // clear pending interrupt
 
     // install DMA service
     rgb_panel->flags.stream_mode = !rgb_panel_config->flags.refresh_on_demand;
-    rgb_panel->fb_bits_per_pixel = fb_bits_per_pixel;
     rgb_panel->dma_burst_size = rgb_panel_config->dma_burst_size ? rgb_panel_config->dma_burst_size : 64;
+    rgb_panel->flags.fb_in_psram = rgb_panel_config->flags.fb_in_psram;
     ESP_GOTO_ON_ERROR(lcd_rgb_create_dma_channel(rgb_panel), err, TAG, "install DMA failed");
     // allocate frame buffers + bounce buffers
-    ESP_GOTO_ON_ERROR(lcd_rgb_panel_alloc_frame_buffers(rgb_panel_config, rgb_panel), err, TAG, "alloc frame buffers failed");
+    ESP_GOTO_ON_ERROR(lcd_rgb_panel_alloc_frame_buffers(rgb_panel), err, TAG, "alloc frame buffers failed");
     // initialize DMA descriptor link
-    lcd_rgb_panel_init_trans_link(rgb_panel);
+    ESP_GOTO_ON_ERROR(lcd_rgb_panel_init_trans_link(rgb_panel), err, TAG, "init DMA link failed");
 
     // configure GPIO
     ret = lcd_rgb_panel_configure_gpio(rgb_panel, rgb_panel_config);
@@ -361,7 +360,6 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
     rgb_panel->output_bits_per_pixel = fb_bits_per_pixel; // by default, the output bpp is the same as the frame buffer bpp
     rgb_panel->disp_gpio_num = rgb_panel_config->disp_gpio_num;
     rgb_panel->flags.disp_en_level = !rgb_panel_config->flags.disp_active_low;
-    rgb_panel->flags.bb_invalidate_cache = rgb_panel_config->flags.bb_invalidate_cache;
     rgb_panel->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
     // fill function table
     rgb_panel->base.del = rgb_panel_del;
@@ -398,19 +396,23 @@ esp_err_t esp_lcd_rgb_panel_register_event_callbacks(esp_lcd_panel_handle_t pane
     if (callbacks->on_vsync) {
         ESP_RETURN_ON_FALSE(esp_ptr_in_iram(callbacks->on_vsync), ESP_ERR_INVALID_ARG, TAG, "on_vsync callback not in IRAM");
     }
+    if (callbacks->on_color_trans_done) {
+        ESP_RETURN_ON_FALSE(esp_ptr_in_iram(callbacks->on_color_trans_done), ESP_ERR_INVALID_ARG, TAG, "on_color_trans_done callback not in IRAM");
+    }
+    if (callbacks->on_frame_buf_complete) {
+        ESP_RETURN_ON_FALSE(esp_ptr_in_iram(callbacks->on_frame_buf_complete), ESP_ERR_INVALID_ARG, TAG, "on_frame_buf_complete callback not in IRAM");
+    }
     if (callbacks->on_bounce_empty) {
         ESP_RETURN_ON_FALSE(esp_ptr_in_iram(callbacks->on_bounce_empty), ESP_ERR_INVALID_ARG, TAG, "on_bounce_empty callback not in IRAM");
     }
-    if (callbacks->on_bounce_frame_finish) {
-        ESP_RETURN_ON_FALSE(esp_ptr_in_iram(callbacks->on_bounce_frame_finish), ESP_ERR_INVALID_ARG, TAG, "on_bounce_frame_finish callback not in IRAM");
-    }
     if (user_ctx) {
         ESP_RETURN_ON_FALSE(esp_ptr_internal(user_ctx), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM");
     }
 #endif // CONFIG_LCD_RGB_ISR_IRAM_SAFE
     rgb_panel->on_vsync = callbacks->on_vsync;
+    rgb_panel->on_color_trans_done = callbacks->on_color_trans_done;
+    rgb_panel->on_frame_buf_complete = callbacks->on_frame_buf_complete;
     rgb_panel->on_bounce_empty = callbacks->on_bounce_empty;
-    rgb_panel->on_bounce_frame_finish = callbacks->on_bounce_frame_finish;
     rgb_panel->user_ctx = user_ctx;
     return ESP_OK;
 }
@@ -488,8 +490,7 @@ esp_err_t esp_lcd_rgb_panel_set_yuv_conversion(esp_lcd_panel_handle_t panel, con
 
         if (config->src.color_space == LCD_COLOR_SPACE_YUV && config->dst.color_space == LCD_COLOR_SPACE_RGB) { // YUV->RGB
             lcd_ll_set_convert_mode_yuv_to_rgb(hal->dev, config->src.yuv_sample);
-            // Note, the RGB->YUV conversion only support RGB565
-            rgb_panel->output_bits_per_pixel = 16;
+            rgb_panel->output_bits_per_pixel = rgb_panel->fb_bits_per_pixel;
         } else if (config->src.color_space == LCD_COLOR_SPACE_RGB && config->dst.color_space == LCD_COLOR_SPACE_YUV) { // RGB->YUV
             lcd_ll_set_convert_mode_rgb_to_yuv(hal->dev, config->dst.yuv_sample);
             rgb_panel->output_bits_per_pixel = bpp_yuv[config->dst.yuv_sample];
@@ -551,7 +552,8 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
     // enable RGB mode and set data width
     lcd_ll_enable_rgb_mode(rgb_panel->hal.dev, true);
     lcd_ll_set_dma_read_stride(rgb_panel->hal.dev, rgb_panel->data_width);
-    lcd_ll_set_phase_cycles(rgb_panel->hal.dev, 0, 0, 1); // enable data phase only
+    // enable data phase only
+    lcd_ll_set_phase_cycles(rgb_panel->hal.dev, 0, 0, 1);
     // number of data cycles is controlled by DMA buffer size
     lcd_ll_enable_output_always_on(rgb_panel->hal.dev, true);
     // configure HSYNC, VSYNC, DE signal idle state level
@@ -569,7 +571,8 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
     lcd_ll_enable_output_hsync_in_porch_region(rgb_panel->hal.dev, true);
     // generate the hsync at the very beginning of line
     lcd_ll_set_hsync_position(rgb_panel->hal.dev, 0);
-    // send next frame automatically in stream mode
+    // in stream mode, after finish one frame, the LCD controller will ask for data automatically from the DMA
+    // DMA should prepare the next frame data within porch region
     lcd_ll_enable_auto_next_frame(rgb_panel->hal.dev, rgb_panel->flags.stream_mode);
     // trigger interrupt on the end of frame
     lcd_ll_enable_interrupt(rgb_panel->hal.dev, LCD_LL_EVENT_VSYNC_END, true);
@@ -583,157 +586,18 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
     return ret;
 }
 
-__attribute__((always_inline))
-static inline void copy_pixel_8bpp(uint8_t *to, const uint8_t *from)
-{
-    *to++ = *from++;
-}
-
-__attribute__((always_inline))
-static inline void copy_pixel_16bpp(uint8_t *to, const uint8_t *from)
-{
-    *to++ = *from++;
-    *to++ = *from++;
-}
-
-__attribute__((always_inline))
-static inline void copy_pixel_24bpp(uint8_t *to, const uint8_t *from)
-{
-    *to++ = *from++;
-    *to++ = *from++;
-    *to++ = *from++;
-}
-
-#define COPY_PIXEL_CODE_BLOCK(_bpp)                                                               \
-    switch (rgb_panel->rotate_mask)                                                               \
-    {                                                                                             \
-    case 0:                                                                                       \
-    {                                                                                             \
-        uint8_t *to = fb + (y_start * h_res + x_start) * bytes_per_pixel;                         \
-        for (int y = y_start; y < y_end; y++)                                                     \
-        {                                                                                         \
-            memcpy(to, from, copy_bytes_per_line);                                                \
-            to += bytes_per_line;                                                                 \
-            from += copy_bytes_per_line;                                                          \
-        }                                                                                         \
-        bytes_to_flush = (y_end - y_start) * bytes_per_line;                                      \
-        flush_ptr = fb + y_start * bytes_per_line;                                                \
-    }                                                                                             \
-    break;                                                                                        \
-    case ROTATE_MASK_MIRROR_X:                                                                    \
-        for (int y = y_start; y < y_end; y++)                                                     \
-        {                                                                                         \
-            uint32_t index = (y * h_res + (h_res - 1 - x_start)) * bytes_per_pixel;               \
-            for (size_t x = x_start; x < x_end; x++)                                              \
-            {                                                                                     \
-                copy_pixel_##_bpp##bpp(to + index, from);                                         \
-                index -= bytes_per_pixel;                                                         \
-                from += bytes_per_pixel;                                                          \
-            }                                                                                     \
-        }                                                                                         \
-        bytes_to_flush = (y_end - y_start) * bytes_per_line;                                      \
-        flush_ptr = fb + y_start * bytes_per_line;                                                \
-        break;                                                                                    \
-    case ROTATE_MASK_MIRROR_Y:                                                                    \
-    {                                                                                             \
-        uint8_t *to = fb + ((v_res - 1 - y_start) * h_res + x_start) * bytes_per_pixel;           \
-        for (int y = y_start; y < y_end; y++)                                                     \
-        {                                                                                         \
-            memcpy(to, from, copy_bytes_per_line);                                                \
-            to -= bytes_per_line;                                                                 \
-            from += copy_bytes_per_line;                                                          \
-        }                                                                                         \
-        bytes_to_flush = (y_end - y_start) * bytes_per_line;                                      \
-        flush_ptr = fb + (v_res - y_end) * bytes_per_line;                                        \
-    }                                                                                             \
-    break;                                                                                        \
-    case ROTATE_MASK_MIRROR_X | ROTATE_MASK_MIRROR_Y:                                             \
-        for (int y = y_start; y < y_end; y++)                                                     \
-        {                                                                                         \
-            uint32_t index = ((v_res - 1 - y) * h_res + (h_res - 1 - x_start)) * bytes_per_pixel; \
-            for (size_t x = x_start; x < x_end; x++)                                              \
-            {                                                                                     \
-                copy_pixel_##_bpp##bpp(to + index, from);                                         \
-                index -= bytes_per_pixel;                                                         \
-                from += bytes_per_pixel;                                                          \
-            }                                                                                     \
-        }                                                                                         \
-        bytes_to_flush = (y_end - y_start) * bytes_per_line;                                      \
-        flush_ptr = fb + (v_res - y_end) * bytes_per_line;                                        \
-        break;                                                                                    \
-    case ROTATE_MASK_SWAP_XY:                                                                     \
-        for (int y = y_start; y < y_end; y++)                                                     \
-        {                                                                                         \
-            for (int x = x_start; x < x_end; x++)                                                 \
-            {                                                                                     \
-                uint32_t j = y * copy_bytes_per_line + x * bytes_per_pixel - offset;              \
-                uint32_t i = (x * h_res + y) * bytes_per_pixel;                                   \
-                copy_pixel_##_bpp##bpp(to + i, from + j);                                         \
-            }                                                                                     \
-        }                                                                                         \
-        bytes_to_flush = (x_end - x_start) * bytes_per_line;                                      \
-        flush_ptr = fb + x_start * bytes_per_line;                                                \
-        break;                                                                                    \
-    case ROTATE_MASK_SWAP_XY | ROTATE_MASK_MIRROR_X:                                              \
-        for (int y = y_start; y < y_end; y++)                                                     \
-        {                                                                                         \
-            for (int x = x_start; x < x_end; x++)                                                 \
-            {                                                                                     \
-                uint32_t j = y * copy_bytes_per_line + x * bytes_per_pixel - offset;              \
-                uint32_t i = (x * h_res + h_res - 1 - y) * bytes_per_pixel;                       \
-                copy_pixel_##_bpp##bpp(to + i, from + j);                                         \
-            }                                                                                     \
-        }                                                                                         \
-        bytes_to_flush = (x_end - x_start) * bytes_per_line;                                      \
-        flush_ptr = fb + x_start * bytes_per_line;                                                \
-        break;                                                                                    \
-    case ROTATE_MASK_SWAP_XY | ROTATE_MASK_MIRROR_Y:                                              \
-        for (int y = y_start; y < y_end; y++)                                                     \
-        {                                                                                         \
-            for (int x = x_start; x < x_end; x++)                                                 \
-            {                                                                                     \
-                uint32_t j = y * copy_bytes_per_line + x * bytes_per_pixel - offset;              \
-                uint32_t i = ((v_res - 1 - x) * h_res + y) * bytes_per_pixel;                     \
-                copy_pixel_##_bpp##bpp(to + i, from + j);                                         \
-            }                                                                                     \
-        }                                                                                         \
-        bytes_to_flush = (x_end - x_start) * bytes_per_line;                                      \
-        flush_ptr = fb + (v_res - x_end) * bytes_per_line;                                        \
-        break;                                                                                    \
-    case ROTATE_MASK_SWAP_XY | ROTATE_MASK_MIRROR_X | ROTATE_MASK_MIRROR_Y:                       \
-        for (int y = y_start; y < y_end; y++)                                                     \
-        {                                                                                         \
-            for (int x = x_start; x < x_end; x++)                                                 \
-            {                                                                                     \
-                uint32_t j = y * copy_bytes_per_line + x * bytes_per_pixel - offset;              \
-                uint32_t i = ((v_res - 1 - x) * h_res + h_res - 1 - y) * bytes_per_pixel;         \
-                copy_pixel_##_bpp##bpp(to + i, from + j);                                         \
-            }                                                                                     \
-        }                                                                                         \
-        bytes_to_flush = (x_end - x_start) * bytes_per_line;                                      \
-        flush_ptr = fb + (v_res - x_end) * bytes_per_line;                                        \
-        break;                                                                                    \
-    default:                                                                                      \
-        break;                                                                                    \
-    }
-
 static esp_err_t rgb_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int y_start, int x_end, int y_end, const void *color_data)
 {
     esp_rgb_panel_t *rgb_panel = __containerof(panel, esp_rgb_panel_t, base);
     ESP_RETURN_ON_FALSE(rgb_panel->num_fbs > 0, ESP_ERR_NOT_SUPPORTED, TAG, "no frame buffer installed");
+    esp_lcd_rgb_panel_draw_buf_complete_cb_t cb = rgb_panel->on_color_trans_done;
 
-    // check if we need to copy the draw buffer (pointed by the color_data) to the driver's frame buffer
-    bool do_copy = false;
-    if (color_data == rgb_panel->fbs[0]) {
-        rgb_panel->cur_fb_index = 0;
-    } else if (color_data == rgb_panel->fbs[1]) {
-        rgb_panel->cur_fb_index = 1;
-    } else if (color_data == rgb_panel->fbs[2]) {
-        rgb_panel->cur_fb_index = 2;
-    } else {
-        // we do the copy only if the color_data is different from either frame buffer
-        do_copy = true;
-    }
+    uint8_t *draw_buffer = (uint8_t *)color_data;
+    size_t fb_size = rgb_panel->fb_size;
+    int h_res = rgb_panel->timings.h_res;
+    int v_res = rgb_panel->timings.v_res;
+    int bytes_per_pixel = rgb_panel->fb_bits_per_pixel / 8;
+    uint32_t bytes_per_line = bytes_per_pixel * h_res;
 
     // adjust the flush window by adding extra gap
     x_start += rgb_panel->x_gap;
@@ -742,8 +606,6 @@ static esp_err_t rgb_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int
     y_end += rgb_panel->y_gap;
 
     // clip to boundaries
-    int h_res = rgb_panel->timings.h_res;
-    int v_res = rgb_panel->timings.v_res;
     if (rgb_panel->rotate_mask & ROTATE_MASK_SWAP_XY) {
         x_start = MAX(x_start, 0);
         x_end = MIN(x_end, v_res);
@@ -756,15 +618,24 @@ static esp_err_t rgb_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int
         y_end = MIN(y_end, v_res);
     }
 
-    int bytes_per_pixel = rgb_panel->fb_bits_per_pixel / 8;
-    int pixels_per_line = rgb_panel->timings.h_res;
-    uint32_t bytes_per_line = bytes_per_pixel * pixels_per_line;
-    uint8_t *fb = rgb_panel->fbs[rgb_panel->cur_fb_index];
-    size_t bytes_to_flush = v_res * h_res * bytes_per_pixel;
-    uint8_t *flush_ptr = fb;
-
-    if (do_copy) {
-        // copy the UI draw buffer into internal frame buffer
+    // check if we want to copy the draw buffer to the internal frame buffer
+    bool draw_buf_copy_to_fb = true;
+    uint8_t draw_buf_fb_index = 0;
+    for (int i = 0; i < rgb_panel->num_fbs; i++) {
+        if (draw_buffer >= rgb_panel->fbs[i] && draw_buffer < rgb_panel->fbs[i] + fb_size) {
+            draw_buf_fb_index = i;
+            draw_buf_copy_to_fb = false;
+            break;
+        }
+    }
+
+    if (draw_buf_copy_to_fb) {
+        // sync the draw buffer with the frame buffer by CPU copy
+        ESP_LOGV(TAG, "copy draw buffer to frame buffer by CPU");
+        uint8_t *fb = rgb_panel->fbs[rgb_panel->cur_fb_index];
+        size_t bytes_to_flush = v_res * bytes_per_line;
+        uint8_t *flush_ptr = fb;
+
         const uint8_t *from = (const uint8_t *)color_data;
         uint32_t copy_bytes_per_line = (x_end - x_start) * bytes_per_pixel;
         size_t offset = y_start * copy_bytes_per_line + x_start * bytes_per_pixel;
@@ -776,23 +647,41 @@ static esp_err_t rgb_panel_draw_bitmap(esp_lcd_panel_t *panel, int x_start, int
         } else if (3 == bytes_per_pixel) {
             COPY_PIXEL_CODE_BLOCK(24)
         }
-    }
-
-    // Note that if we use a bounce buffer, the data gets read by the CPU as well so no need to write back
-    if (rgb_panel->flags.fb_in_psram && !rgb_panel->bb_size) {
-        // CPU writes data to PSRAM through DCache, data in PSRAM might not get updated, so write back
-        ESP_RETURN_ON_ERROR(esp_cache_msync(flush_ptr, bytes_to_flush, 0), TAG, "flush cache buffer failed");
+        // do memory sync only when the frame buffer is mounted to the DMA link list and behind the cache
+        if (!rgb_panel->bb_size && rgb_panel->flags.fb_behind_cache) {
+            esp_cache_msync(flush_ptr, bytes_to_flush, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
+        }
+        // after the draw buffer finished copying, notify the user to recycle the draw buffer
+        if (cb) {
+            cb(&rgb_panel->base, NULL, rgb_panel->user_ctx);
+        }
+    } else {
+        ESP_LOGV(TAG, "draw buffer is part of the frame buffer");
+        // the new frame buffer index is changed
+        rgb_panel->cur_fb_index = draw_buf_fb_index;
+        // when this function is called, the frame buffer already reflects the draw buffer changes
+        // if the frame buffer is also mounted to the DMA, we need to do the sync between them
+        if (!rgb_panel->bb_size && rgb_panel->flags.fb_behind_cache) {
+            uint8_t *cache_sync_start = rgb_panel->fbs[draw_buf_fb_index] + (y_start * h_res) * bytes_per_pixel;
+            size_t cache_sync_size = (y_end - y_start) * bytes_per_line;
+            esp_cache_msync(cache_sync_start, cache_sync_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
+        }
+        // after the draw buffer finished copying, notify the user to recycle the draw buffer
+        if (cb) {
+            cb(&rgb_panel->base, NULL, rgb_panel->user_ctx);
+        }
     }
 
     if (!rgb_panel->bb_size) {
         if (rgb_panel->flags.stream_mode) {
-            // the DMA will convey the new frame buffer next time
-            for (int i = 0; i < RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) {
-                rgb_panel->dma_nodes[rgb_panel->num_dma_nodes * (i + 1) - 1].next = rgb_panel->dma_links[rgb_panel->cur_fb_index];
+            for (int i = 0; i < rgb_panel->num_fbs; i++) {
+                // Note, because of DMA prefetch, there's possibility that the old frame buffer might be sent out again
+                // it's hard to know the time when the new frame buffer starts
+                gdma_link_concat(rgb_panel->dma_fb_links[i], -1, rgb_panel->dma_fb_links[rgb_panel->cur_fb_index], 0);
             }
+
         }
     }
-
     return ESP_OK;
 }
 
@@ -848,73 +737,67 @@ static esp_err_t rgb_panel_disp_on_off(esp_lcd_panel_t *panel, bool on_off)
     return ESP_OK;
 }
 
-static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_lcd_rgb_panel_config_t *panel_config)
+static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *rgb_panel, const esp_lcd_rgb_panel_config_t *panel_config)
 {
-    int panel_id = panel->panel_id;
+    int panel_id = rgb_panel->panel_id;
     // Set the number of output data lines
-    lcd_ll_set_data_wire_width(panel->hal.dev, panel_config->data_width);
+    lcd_ll_set_data_wire_width(rgb_panel->hal.dev, panel_config->data_width);
     // connect peripheral signals via GPIO matrix
     for (size_t i = 0; i < panel_config->data_width; i++) {
         if (panel_config->data_gpio_nums[i] >= 0) {
-            gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->data_gpio_nums[i]], PIN_FUNC_GPIO);
-            gpio_set_direction(panel_config->data_gpio_nums[i], GPIO_MODE_OUTPUT);
+            gpio_func_sel(panel_config->data_gpio_nums[i], PIN_FUNC_GPIO);
             esp_rom_gpio_connect_out_signal(panel_config->data_gpio_nums[i],
                                             lcd_periph_rgb_signals.panels[panel_id].data_sigs[i], false, false);
         }
     }
     if (panel_config->hsync_gpio_num >= 0) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->hsync_gpio_num], PIN_FUNC_GPIO);
-        gpio_set_direction(panel_config->hsync_gpio_num, GPIO_MODE_OUTPUT);
+        gpio_func_sel(panel_config->hsync_gpio_num, PIN_FUNC_GPIO);
         esp_rom_gpio_connect_out_signal(panel_config->hsync_gpio_num,
                                         lcd_periph_rgb_signals.panels[panel_id].hsync_sig, false, false);
     }
     if (panel_config->vsync_gpio_num >= 0) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->vsync_gpio_num], PIN_FUNC_GPIO);
-        gpio_set_direction(panel_config->vsync_gpio_num, GPIO_MODE_OUTPUT);
+        gpio_func_sel(panel_config->vsync_gpio_num, PIN_FUNC_GPIO);
         esp_rom_gpio_connect_out_signal(panel_config->vsync_gpio_num,
                                         lcd_periph_rgb_signals.panels[panel_id].vsync_sig, false, false);
     }
     // PCLK may not be necessary in some cases (i.e. VGA output)
     if (panel_config->pclk_gpio_num >= 0) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->pclk_gpio_num], PIN_FUNC_GPIO);
-        gpio_set_direction(panel_config->pclk_gpio_num, GPIO_MODE_OUTPUT);
+        gpio_func_sel(panel_config->pclk_gpio_num, PIN_FUNC_GPIO);
         esp_rom_gpio_connect_out_signal(panel_config->pclk_gpio_num,
                                         lcd_periph_rgb_signals.panels[panel_id].pclk_sig, false, false);
     }
     // DE signal might not be necessary for some RGB LCD
     if (panel_config->de_gpio_num >= 0) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->de_gpio_num], PIN_FUNC_GPIO);
-        gpio_set_direction(panel_config->de_gpio_num, GPIO_MODE_OUTPUT);
+        gpio_func_sel(panel_config->de_gpio_num, PIN_FUNC_GPIO);
         esp_rom_gpio_connect_out_signal(panel_config->de_gpio_num,
                                         lcd_periph_rgb_signals.panels[panel_id].de_sig, false, false);
     }
-    // disp enable GPIO is optional
+    // disp enable GPIO is optional, it is a general purpose output GPIO
     if (panel_config->disp_gpio_num >= 0) {
-        gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->disp_gpio_num], PIN_FUNC_GPIO);
-        gpio_set_direction(panel_config->disp_gpio_num, GPIO_MODE_OUTPUT);
-        esp_rom_gpio_connect_out_signal(panel_config->disp_gpio_num, SIG_GPIO_OUT_IDX, false, false);
+        gpio_func_sel(panel_config->disp_gpio_num, PIN_FUNC_GPIO);
+        gpio_output_enable(panel_config->disp_gpio_num);
     }
     return ESP_OK;
 }
 
-static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_clock_source_t clk_src)
+static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *rgb_panel, lcd_clock_source_t clk_src)
 {
     // get clock source frequency
     uint32_t src_clk_hz = 0;
     ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz),
                         TAG, "get clock source frequency failed");
-    panel->src_clk_hz = src_clk_hz;
+    rgb_panel->src_clk_hz = src_clk_hz;
     esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true);
     LCD_CLOCK_SRC_ATOMIC() {
-        lcd_ll_select_clk_src(panel->hal.dev, clk_src);
+        lcd_ll_select_clk_src(rgb_panel->hal.dev, clk_src);
     }
 
     // create pm lock based on different clock source
     // clock sources like PLL and XTAL will be turned off in light sleep
 #if CONFIG_PM_ENABLE
-    ESP_RETURN_ON_ERROR(esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "rgb_panel", &panel->pm_lock), TAG, "create pm lock failed");
+    ESP_RETURN_ON_ERROR(esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "rgb_panel", &rgb_panel->pm_lock), TAG, "create pm lock failed");
     // hold the lock during the whole lifecycle of RGB panel
-    esp_pm_lock_acquire(panel->pm_lock);
+    esp_pm_lock_acquire(rgb_panel->pm_lock);
     ESP_LOGD(TAG, "installed pm lock and hold the lock during the whole panel lifecycle");
 #endif
 
@@ -925,135 +808,211 @@ static IRAM_ATTR bool lcd_rgb_panel_fill_bounce_buffer(esp_rgb_panel_t *panel, u
 {
     bool need_yield = false;
     int bytes_per_pixel = panel->fb_bits_per_pixel / 8;
-    if (panel->num_fbs == 0) {
+    if (unlikely(panel->num_fbs == 0)) {
+        // driver doesn't maintain a frame buffer, so ask the user to fill the bounce buffer
         if (panel->on_bounce_empty) {
-            // We don't have a frame buffer here; we need to call a callback to refill the bounce buffer
             if (panel->on_bounce_empty(&panel->base, buffer, panel->bounce_pos_px, panel->bb_size, panel->user_ctx)) {
                 need_yield = true;
             }
         }
     } else {
-        // We do have frame buffer; copy from there.
-        // Note: if the cache is disabled, and accessing the PSRAM by DCACHE will crash.
+        // copy partial frame buffer to the bounce buffer
+        // Note: if the frame buffer is behind a cache, and the cache is disabled, crash would happen here when auto write back happens
         memcpy(buffer, &panel->fbs[panel->bb_fb_index][panel->bounce_pos_px * bytes_per_pixel], panel->bb_size);
-        if (panel->flags.bb_invalidate_cache) {
-            // We don't need the bytes we copied from the psram anymore
-            // Make sure that if anything happened to have changed (because the line already was in cache) we write the data back.
-            esp_cache_msync(&panel->fbs[panel->bb_fb_index][panel->bounce_pos_px * bytes_per_pixel], (size_t)panel->bb_size, ESP_CACHE_MSYNC_FLAG_INVALIDATE);
-        }
     }
+    // do memory sync if the bounce buffer is behind the cache
+    if (panel->flags.bb_behind_cache) {
+        esp_cache_msync(buffer, panel->bb_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED);
+    }
+
     panel->bounce_pos_px += panel->bb_size / bytes_per_pixel;
     // If the bounce pos is larger than the frame buffer size, wrap around so the next isr starts pre-loading the next frame.
     if (panel->bounce_pos_px >= panel->fb_size / bytes_per_pixel) {
         panel->bounce_pos_px = 0;
         panel->bb_fb_index = panel->cur_fb_index;
-        if (panel->on_bounce_frame_finish) {
-            if (panel->on_bounce_frame_finish(&panel->base, NULL, panel->user_ctx)) {
+        esp_lcd_rgb_panel_frame_buf_complete_cb_t cb = panel->on_frame_buf_complete;
+        if (cb) {
+            if (cb(&panel->base, NULL, panel->user_ctx)) {
                 need_yield = true;
             }
         }
     }
-    if (panel->num_fbs > 0) {
-        // Preload the next bit of buffer from psram
+
+    // Preload the next bit of buffer to the cache memory, this can improve the performance
+    if (panel->num_fbs > 0 && panel->flags.fb_behind_cache) {
+#if CONFIG_IDF_TARGET_ESP32S3
         Cache_Start_DCache_Preload((uint32_t)&panel->fbs[panel->bb_fb_index][panel->bounce_pos_px * bytes_per_pixel],
                                    panel->bb_size, 0);
+#elif CONFIG_IDF_TARGET_ESP32P4
+        Cache_Start_L2_Cache_Preload((uint32_t)&panel->fbs[panel->bb_fb_index][panel->bounce_pos_px * bytes_per_pixel],
+                                     panel->bb_size, 0);
+#else
+#error "Unsupported target"
+#endif
     }
     return need_yield;
 }
 
-// This is called in bounce buffer mode, when one bounce buffer has been fully sent to the LCD peripheral.
 static IRAM_ATTR bool lcd_rgb_panel_eof_handler(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
 {
-    esp_rgb_panel_t *panel = (esp_rgb_panel_t *)user_data;
-    dma_descriptor_t *desc = (dma_descriptor_t *)event_data->tx_eof_desc_addr;
-    // Figure out which bounce buffer to write to.
-    // Note: what we receive is the *last* descriptor of this bounce buffer.
-    int bb = (desc == &panel->dma_nodes[panel->num_dma_nodes - 1]) ? 0 : 1;
-    portENTER_CRITICAL_ISR(&panel->spinlock);
-    panel->bb_eof_count++;
-    portEXIT_CRITICAL_ISR(&panel->spinlock);
-    return lcd_rgb_panel_fill_bounce_buffer(panel, panel->bounce_buffer[bb]);
+    bool need_yield = false;
+    esp_rgb_panel_t *rgb_panel = (esp_rgb_panel_t *)user_data;
+
+    if (rgb_panel->bb_size) {
+        // in bounce buffer mode, the DMA EOF means time to fill the finished bounce buffer
+        // Figure out which bounce buffer to write to
+        portENTER_CRITICAL_ISR(&rgb_panel->spinlock);
+        int bb = rgb_panel->bb_eof_count % RGB_LCD_PANEL_BOUNCE_BUF_NUM;
+        rgb_panel->bb_eof_count++;
+        portEXIT_CRITICAL_ISR(&rgb_panel->spinlock);
+        need_yield = lcd_rgb_panel_fill_bounce_buffer(rgb_panel, rgb_panel->bounce_buffer[bb]);
+    } else {
+        // if not bounce buffer, the DMA EOF event means the end of a frame has been sent out to the LCD controller
+        if (rgb_panel->on_frame_buf_complete) {
+            if (rgb_panel->on_frame_buf_complete(&rgb_panel->base, NULL, rgb_panel->user_ctx)) {
+                need_yield = true;
+            }
+        }
+    }
+    return need_yield;
 }
 
-static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *panel)
+static esp_err_t lcd_rgb_create_dma_channel(esp_rgb_panel_t *rgb_panel)
 {
     // alloc DMA channel and connect to LCD peripheral
     gdma_channel_alloc_config_t dma_chan_config = {
         .direction = GDMA_CHANNEL_DIRECTION_TX,
     };
-#if SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AHB
-    ESP_RETURN_ON_ERROR(gdma_new_ahb_channel(&dma_chan_config, &panel->dma_chan), TAG, "alloc DMA channel failed");
-#elif SOC_GDMA_TRIG_PERIPH_LCD0_BUS == SOC_GDMA_BUS_AXI
-    ESP_RETURN_ON_ERROR(gdma_new_axi_channel(&dma_chan_config, &panel->dma_chan), TAG, "alloc DMA channel failed");
-#endif
-    gdma_connect(panel->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0));
+    ESP_RETURN_ON_ERROR(LCD_GDMA_NEW_CHANNEL(&dma_chan_config, &rgb_panel->dma_chan), TAG, "alloc DMA channel failed");
+    gdma_connect(rgb_panel->dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0));
 
-    // configure DMA transfer parameters
+    // configure DMA strategy
+    gdma_strategy_config_t dma_strategy = {
+        .eof_till_data_popped = false,
+    };
+    gdma_apply_strategy(rgb_panel->dma_chan, &dma_strategy);
+
+    // configure DMA transfer
     gdma_transfer_config_t trans_cfg = {
-        .max_data_burst_size = panel->dma_burst_size,
-        .access_ext_mem = true, // frame buffer was allocated from external memory
+        .max_data_burst_size = rgb_panel->dma_burst_size,
+        .access_ext_mem = rgb_panel->flags.fb_in_psram,
     };
-    ESP_RETURN_ON_ERROR(gdma_config_transfer(panel->dma_chan, &trans_cfg), TAG, "config DMA transfer failed");
+    ESP_RETURN_ON_ERROR(gdma_config_transfer(rgb_panel->dma_chan, &trans_cfg), TAG, "config DMA transfer failed");
+    // get the memory alignment required by the DMA
+    gdma_get_alignment_constraints(rgb_panel->dma_chan, &rgb_panel->int_mem_align, &rgb_panel->ext_mem_align);
 
-    // we need to refill the bounce buffer in the DMA EOF interrupt, so only register the callback for bounce buffer mode
-    if (panel->bb_size) {
-        gdma_tx_event_callbacks_t cbs = {
-            .on_trans_eof = lcd_rgb_panel_eof_handler,
-        };
-        gdma_register_tx_event_callbacks(panel->dma_chan, &cbs, panel);
-    }
+    // register DMA EOF callback
+    gdma_tx_event_callbacks_t cbs = {
+        .on_trans_eof = lcd_rgb_panel_eof_handler,
+    };
+    ESP_RETURN_ON_ERROR(gdma_register_tx_event_callbacks(rgb_panel->dma_chan, &cbs, rgb_panel), TAG, "register DMA EOF callback failed");
 
     return ESP_OK;
 }
 
-// If we restart GDMA, many pixels already have been transferred to the LCD peripheral.
-// Looks like that has 16 pixels of FIFO plus one holding register.
+#if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK
+// If we restart GDMA, the data sent to the LCD peripheral needs to start LCD_FIFO_PRESERVE_SIZE_PX pixels after the FB start
+// so we use a dedicated DMA link (called restart link) to restart the transaction
 #define LCD_FIFO_PRESERVE_SIZE_PX (LCD_LL_FIFO_DEPTH + 1)
+#endif
 
-static void lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *panel)
+static esp_err_t lcd_rgb_panel_init_trans_link(esp_rgb_panel_t *rgb_panel)
 {
-    for (int i = 0; i < RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) {
-        panel->dma_links[i] = &panel->dma_nodes[panel->num_dma_nodes * i];
-    }
-    // chain DMA descriptors
-    for (int i = 0; i < panel->num_dma_nodes * RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) {
-        panel->dma_nodes[i].dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU;
-        panel->dma_nodes[i].next = &panel->dma_nodes[i + 1];
-    }
-
-    if (panel->bb_size) {
-        // loop end back to start
-        panel->dma_nodes[panel->num_dma_nodes * RGB_LCD_PANEL_BOUNCE_BUF_NUM - 1].next = &panel->dma_nodes[0];
-        // mount the bounce buffers to the DMA descriptors
-        lcd_com_mount_dma_data(panel->dma_links[0], panel->bounce_buffer[0], panel->bb_size);
-        lcd_com_mount_dma_data(panel->dma_links[1], panel->bounce_buffer[1], panel->bb_size);
-    } else {
-        if (panel->flags.stream_mode) {
-            // circle DMA descriptors chain for each frame buffer
-            for (int i = 0; i < RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) {
-                panel->dma_nodes[panel->num_dma_nodes * (i + 1) - 1].next = &panel->dma_nodes[panel->num_dma_nodes * i];
-            }
-        } else {
-            // one-off DMA descriptors chain
-            for (int i = 0; i < RGB_LCD_PANEL_DMA_LINKS_REPLICA; i++) {
-                panel->dma_nodes[panel->num_dma_nodes * (i + 1) - 1].next = NULL;
+#if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK
+    // the restart link shares the same buffer with the frame/bounce buffer but start from a different offset
+    int restart_skip_bytes = LCD_FIFO_PRESERVE_SIZE_PX * (rgb_panel->fb_bits_per_pixel / 8);
+#endif
+    if (rgb_panel->bb_size) {
+        // DMA is used to convey the bounce buffer
+        size_t num_dma_nodes_per_bounce_buffer = (rgb_panel->bb_size + LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE - 1) / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
+        gdma_link_list_config_t link_cfg = {
+            .buffer_alignment = rgb_panel->int_mem_align,
+            .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN,
+            .num_items = num_dma_nodes_per_bounce_buffer * RGB_LCD_PANEL_BOUNCE_BUF_NUM,
+            .flags = {
+                .check_owner = true,
             }
+        };
+        ESP_RETURN_ON_ERROR(gdma_new_link_list(&link_cfg, &rgb_panel->dma_bb_link), TAG, "create bounce buffer DMA link failed");
+        // mount bounce buffers to the DMA link list
+        gdma_buffer_mount_config_t mount_cfgs[RGB_LCD_PANEL_BOUNCE_BUF_NUM] = {0};
+        for (int i = 0; i < RGB_LCD_PANEL_BOUNCE_BUF_NUM; i++) {
+            mount_cfgs[i].buffer = rgb_panel->bounce_buffer[i];
+            mount_cfgs[i].length = rgb_panel->bb_size;
+            mount_cfgs[i].flags.mark_eof = true; // we use the DMA EOF interrupt to copy the frame buffer (partially) to the bounce buffer
         }
-        // mount the frame buffer to the DMA descriptors
-        for (size_t i = 0; i < panel->num_fbs; i++) {
-            lcd_com_mount_dma_data(panel->dma_links[i], panel->fbs[i], panel->fb_size);
+        ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_bb_link, 0, mount_cfgs, RGB_LCD_PANEL_BOUNCE_BUF_NUM, NULL),
+                            TAG, "mount DMA bounce buffers failed");
+#if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK
+        // create restart link
+        gdma_link_list_config_t restart_link_cfg = {
+            .buffer_alignment = rgb_panel->int_mem_align,
+            .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN,
+            .num_items = 1, // the restart link only contains one node
+            .flags = {
+                .check_owner = true,
+            }
+        };
+        ESP_RETURN_ON_ERROR(gdma_new_link_list(&restart_link_cfg, &rgb_panel->dma_restart_link), TAG, "create DMA restart link list failed");
+        gdma_buffer_mount_config_t restart_buffer_mount_cfg = {
+            .buffer = rgb_panel->bounce_buffer[0] + restart_skip_bytes,
+            .length = MIN(LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE, rgb_panel->bb_size) - restart_skip_bytes,
+        };
+        ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_restart_link, 0, &restart_buffer_mount_cfg, 1, NULL),
+                            TAG, "mount DMA restart buffer failed");
+
+        // Magic here: we use the restart link to restart the bounce buffer link list, so concat them
+        gdma_link_concat(rgb_panel->dma_restart_link, 0, rgb_panel->dma_bb_link, 1);
+#endif
+    } else {
+        // DMA is used to convey the frame buffer
+        size_t num_dma_nodes = (rgb_panel->fb_size + LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE - 1) / LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
+        gdma_link_list_config_t link_cfg = {
+            .buffer_alignment = rgb_panel->flags.fb_in_psram ? rgb_panel->ext_mem_align : rgb_panel->int_mem_align,
+            .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN,
+            .num_items = num_dma_nodes,
+            .flags = {
+                .check_owner = true,
+            },
+        };
+        gdma_buffer_mount_config_t mount_cfg = {
+            .length = rgb_panel->fb_size,
+            .flags = {
+                .mark_final = rgb_panel->flags.stream_mode ? false : true,
+                .mark_eof = true,
+            },
+        };
+        for (size_t i = 0; i < rgb_panel->num_fbs; i++) {
+            ESP_RETURN_ON_ERROR(gdma_new_link_list(&link_cfg, &rgb_panel->dma_fb_links[i]), TAG, "create frame buffer DMA link failed");
+            // mount bounce buffers to the DMA link list
+            mount_cfg.buffer = rgb_panel->fbs[i];
+            ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_fb_links[i], 0, &mount_cfg, 1, NULL),
+                                TAG, "mount DMA frame buffer failed");
         }
+#if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK
+        // create restart link
+        gdma_link_list_config_t restart_link_cfg = {
+            .buffer_alignment = rgb_panel->flags.fb_in_psram ? rgb_panel->ext_mem_align : rgb_panel->int_mem_align,
+            .item_alignment = LCD_GDMA_DESCRIPTOR_ALIGN,
+            .num_items = 1, // the restart link only contains one node
+            .flags = {
+                .check_owner = true,
+            }
+        };
+        ESP_RETURN_ON_ERROR(gdma_new_link_list(&restart_link_cfg, &rgb_panel->dma_restart_link), TAG, "create DMA restart link list failed");
+        gdma_buffer_mount_config_t restart_buffer_mount_cfg = {
+            .buffer = rgb_panel->fbs[0] + restart_skip_bytes,
+            .length = MIN(LCD_DMA_DESCRIPTOR_BUFFER_MAX_SIZE, rgb_panel->fb_size) - restart_skip_bytes,
+        };
+        ESP_RETURN_ON_ERROR(gdma_link_mount_buffers(rgb_panel->dma_restart_link, 0, &restart_buffer_mount_cfg, 1, NULL),
+                            TAG, "mount DMA restart buffer failed");
+
+        // Magic here: we use the restart link to restart the frame buffer link list, so concat them
+        gdma_link_concat(rgb_panel->dma_restart_link, 0, rgb_panel->dma_fb_links[0], 1);
+#endif
     }
 
-    // On restart, the data sent to the LCD peripheral needs to start LCD_FIFO_PRESERVE_SIZE_PX pixels after the FB start
-    // so we use a dedicated DMA node to restart the DMA transaction
-    // see also `lcd_rgb_panel_try_restart_transmission`
-    memcpy(&panel->dma_restart_node, &panel->dma_nodes[0], sizeof(panel->dma_restart_node));
-    int restart_skip_bytes = LCD_FIFO_PRESERVE_SIZE_PX * (panel->fb_bits_per_pixel / 8);
-    uint8_t *p = (uint8_t *)panel->dma_restart_node.buffer;
-    panel->dma_restart_node.buffer = &p[restart_skip_bytes];
-    panel->dma_restart_node.dw0.length -= restart_skip_bytes;
-    panel->dma_restart_node.dw0.size -= restart_skip_bytes;
+    return ESP_OK;
 }
 
 // reset the GDMA channel every VBlank to stop permanent desyncs from happening.
@@ -1098,8 +1057,17 @@ static IRAM_ATTR void lcd_rgb_panel_try_restart_transmission(esp_rgb_panel_t *pa
     }
 
     gdma_reset(panel->dma_chan);
+    lcd_ll_fifo_reset(panel->hal.dev);
+#if RGB_LCD_NEEDS_SEPARATE_RESTART_LINK
     // restart the DMA by a special DMA node
-    gdma_start(panel->dma_chan, (intptr_t)&panel->dma_restart_node);
+    gdma_start(panel->dma_chan, gdma_link_get_head_addr(panel->dma_restart_link));
+#else
+    if (panel->bb_size) {
+        gdma_start(panel->dma_chan, gdma_link_get_head_addr(panel->dma_bb_link));
+    } else {
+        gdma_start(panel->dma_chan, gdma_link_get_head_addr(panel->dma_fb_links[panel->cur_fb_index]));
+    }
+#endif
 
     if (panel->bb_size) {
         // Fill 2nd bounce buffer while 1st is being sent out, if needed.
@@ -1115,6 +1083,7 @@ static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel)
     // reset FIFO of DMA and LCD, in case there remains old frame data
     gdma_reset(rgb_panel->dma_chan);
     lcd_ll_stop(rgb_panel->hal.dev);
+    lcd_ll_reset(rgb_panel->hal.dev);
     lcd_ll_fifo_reset(rgb_panel->hal.dev);
 
     // pre-fill bounce buffers if needed
@@ -1125,7 +1094,11 @@ static void lcd_rgb_panel_start_transmission(esp_rgb_panel_t *rgb_panel)
     }
 
     // the start of DMA should be prior to the start of LCD engine
-    gdma_start(rgb_panel->dma_chan, (intptr_t)rgb_panel->dma_links[rgb_panel->cur_fb_index]);
+    if (rgb_panel->bb_size) {
+        gdma_start(rgb_panel->dma_chan, gdma_link_get_head_addr(rgb_panel->dma_bb_link));
+    } else {
+        gdma_start(rgb_panel->dma_chan, gdma_link_get_head_addr(rgb_panel->dma_fb_links[rgb_panel->cur_fb_index]));
+    }
     // delay 1us is sufficient for DMA to pass data to LCD FIFO
     // in fact, this is only needed when LCD pixel clock is set too high
     esp_rom_delay_us(1);
@@ -1147,13 +1120,16 @@ IRAM_ATTR static void lcd_rgb_panel_try_update_pclk(esp_rgb_panel_t *rgb_panel)
     portEXIT_CRITICAL_ISR(&rgb_panel->spinlock);
 }
 
-IRAM_ATTR static void lcd_default_isr_handler(void *args)
+IRAM_ATTR static void rgb_lcd_default_isr_handler(void *args)
 {
     esp_rgb_panel_t *rgb_panel = (esp_rgb_panel_t *)args;
     bool need_yield = false;
 
+    // clear the interrupt status
     uint32_t intr_status = lcd_ll_get_interrupt_status(rgb_panel->hal.dev);
     lcd_ll_clear_interrupt_status(rgb_panel->hal.dev, intr_status);
+
+    // VSYNC event happened
     if (intr_status & LCD_LL_EVENT_VSYNC_END) {
         // call user registered callback
         if (rgb_panel->on_vsync) {
@@ -1171,6 +1147,7 @@ IRAM_ATTR static void lcd_default_isr_handler(void *args)
         }
 
     }
+    // yield if needed
     if (need_yield) {
         portYIELD_FROM_ISR();
     }
diff --git a/components/esp_lcd/rgb/include/esp_lcd_panel_rgb.h b/components/esp_lcd/rgb/include/esp_lcd_panel_rgb.h
index 2e9e5a95a6e..389d49ef2f8 100644
--- a/components/esp_lcd/rgb/include/esp_lcd_panel_rgb.h
+++ b/components/esp_lcd/rgb/include/esp_lcd_panel_rgb.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -77,14 +77,32 @@ typedef struct {
 } esp_lcd_rgb_panel_event_data_t;
 
 /**
- * @brief RGB LCD VSYNC event callback prototype
+ * @brief A general function callback prototype for RGB panel driver
  *
- * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel`
- * @param[in] edata Panel event data, fed by driver
+ * @param[in] panel LCD panel handle, which is created by factory API like `esp_lcd_new_rgb_panel`
+ * @param[in] edata RGB panel event data, provided by driver
  * @param[in] user_ctx User data, passed from `esp_lcd_rgb_panel_register_event_callbacks()`
  * @return Whether a high priority task has been waken up by this function
  */
-typedef bool (*esp_lcd_rgb_panel_vsync_cb_t)(esp_lcd_panel_handle_t panel, const esp_lcd_rgb_panel_event_data_t *edata, void *user_ctx);
+typedef bool (*esp_lcd_rgb_panel_general_cb_t)(esp_lcd_panel_handle_t panel, const esp_lcd_rgb_panel_event_data_t *edata, void *user_ctx);
+
+/**
+ * @brief Declare the prototype of the function that will be invoked when the user draw buffer is complete.
+ *        The draw buffer can be recycled after this event.
+ */
+typedef esp_lcd_rgb_panel_general_cb_t esp_lcd_rgb_panel_draw_buf_complete_cb_t;
+
+/**
+ * @brief Declare the prototype of the function that will be invoked when a whole frame buffer is sent to the LCD DMA.
+ *        The LCD hardware may still need some blank time to finish the refresh.
+ */
+typedef esp_lcd_rgb_panel_general_cb_t esp_lcd_rgb_panel_frame_buf_complete_cb_t;
+
+/**
+ * @brief Declare the prototype of the function that will be invoked when the LCD controller sends the VSYNC signal.
+ *        It means, the LCD hardware should be ready, and after some blank time, the next frame will be flushed to the LCD controller.
+ */
+typedef esp_lcd_rgb_panel_general_cb_t esp_lcd_rgb_panel_vsync_cb_t;
 
 /**
  * @brief Prototype for function to re-fill a bounce buffer, rather than copying from the frame buffer
@@ -99,15 +117,10 @@ typedef bool (*esp_lcd_rgb_panel_vsync_cb_t)(esp_lcd_panel_handle_t panel, const
  */
 typedef bool (*esp_lcd_rgb_panel_bounce_buf_fill_cb_t)(esp_lcd_panel_handle_t panel, void *bounce_buf, int pos_px, int len_bytes, void *user_ctx);
 
-/**
- * @brief Prototype for the function to be called when the bounce buffer finish copying the entire frame.
- *
- * @param[in] panel LCD panel handle, returned from `esp_lcd_new_rgb_panel`
- * @param[in] edata Panel event data, fed by driver
- * @param[in] user_ctx User data, passed from `esp_lcd_rgb_panel_register_event_callbacks()`
- * @return Whether a high priority task has been waken up by this function
- */
-typedef bool (*esp_lcd_rgb_panel_bounce_buf_finish_cb_t)(esp_lcd_panel_handle_t panel, const esp_lcd_rgb_panel_event_data_t *edata, void *user_ctx);
+/** @cond */
+/// for backward compatible
+typedef esp_lcd_rgb_panel_frame_buf_complete_cb_t esp_lcd_rgb_panel_bounce_buf_finish_cb_t __attribute__((deprecated("esp_lcd_rgb_panel_bounce_buf_finish_cb_t is deprecated, use esp_lcd_rgb_panel_frame_buf_complete_cb_t instead")));
+/** @endcond */
 
 /**
  * @brief Group of supported RGB LCD panel callbacks
@@ -115,9 +128,15 @@ typedef bool (*esp_lcd_rgb_panel_bounce_buf_finish_cb_t)(esp_lcd_panel_handle_t
  * @note When CONFIG_LCD_RGB_ISR_IRAM_SAFE is enabled, the callback itself and functions called by it should be placed in IRAM.
  */
 typedef struct {
-    esp_lcd_rgb_panel_vsync_cb_t on_vsync;                      /*!< VSYNC event callback */
-    esp_lcd_rgb_panel_bounce_buf_fill_cb_t on_bounce_empty;     /*!< Bounce buffer empty callback. */
-    esp_lcd_rgb_panel_bounce_buf_finish_cb_t on_bounce_frame_finish;  /*!< Bounce buffer finish callback. */
+    esp_lcd_rgb_panel_draw_buf_complete_cb_t on_color_trans_done;  /*!< Invoked when user's color buffer copied to the internal frame buffer.
+                                                                      This is an indicator that the draw buffer can be recycled safely.
+                                                                      But doesn't mean the draw buffer finishes the refreshing to the screen. */
+    esp_lcd_rgb_panel_vsync_cb_t on_vsync;                         /*!< VSYNC event callback */
+    esp_lcd_rgb_panel_bounce_buf_fill_cb_t on_bounce_empty;        /*!< Bounce buffer empty callback. */
+    union {
+        esp_lcd_rgb_panel_frame_buf_complete_cb_t on_bounce_frame_finish __attribute__((deprecated)); /*!< Bounce buffer finish callback. */
+        esp_lcd_rgb_panel_frame_buf_complete_cb_t on_frame_buf_complete;  /*!< A whole frame buffer was just sent to the LCD DMA */
+    };
 } esp_lcd_rgb_panel_event_callbacks_t;
 
 /**
@@ -134,7 +153,7 @@ typedef struct {
                                        DMA fetching from DRAM bounce buffer is much faster than PSRAM frame buffer. */
     size_t sram_trans_align __attribute__((deprecated)); /*!< Alignment of buffers (frame buffer or bounce buffer) that allocated in SRAM */
     union {
-        size_t psram_trans_align; /*!< Alignment of buffers (frame buffer) that allocated in PSRAM */
+        size_t psram_trans_align __attribute__((deprecated)); /*!< Alignment of buffers (frame buffer) that allocated in PSRAM */
         size_t dma_burst_size;    /*!< DMA burst size, in bytes */
     };
     int hsync_gpio_num;           /*!< GPIO used for HSYNC signal */
@@ -142,11 +161,10 @@ typedef struct {
     int de_gpio_num;              /*!< GPIO used for DE signal, set to -1 if it's not used */
     int pclk_gpio_num;            /*!< GPIO used for PCLK signal, set to -1 if it's not used */
     int disp_gpio_num;            /*!< GPIO used for display control signal, set to -1 if it's not used */
-    int data_gpio_nums[SOC_LCD_RGB_DATA_WIDTH]; /*!< GPIOs used for data lines */
+    int data_gpio_nums[SOC_LCDCAM_RGB_DATA_WIDTH]; /*!< GPIOs used for data lines */
     struct {
         uint32_t disp_active_low: 1;     /*!< If this flag is enabled, a low level of display control signal can turn the screen on; vice versa */
-        uint32_t refresh_on_demand: 1;   /*!< If this flag is enabled, the host only refresh the frame buffer when `esp_lcd_panel_draw_bitmap` is called.
-                                              This is useful when the LCD screen has a GRAM and can refresh the LCD by itself. */
+        uint32_t refresh_on_demand: 1;   /*!< If this flag is enabled, the host only refresh the frame buffer in `esp_lcd_panel_draw_bitmap` and `esp_lcd_rgb_panel_refresh`. */
         uint32_t fb_in_psram: 1;         /*!< If this flag is enabled, the frame buffer will be allocated from PSRAM, preferentially */
         uint32_t double_fb: 1;           /*!< If this flag is enabled, the driver will allocate two screen sized frame buffer, same as num_fbs=2 */
         uint32_t no_fb: 1;               /*!< If this flag is enabled, the driver won't allocate frame buffer.
diff --git a/components/esp_lcd/rgb/rgb_lcd_rotation_sw.h b/components/esp_lcd/rgb/rgb_lcd_rotation_sw.h
new file mode 100644
index 00000000000..401786cbcbd
--- /dev/null
+++ b/components/esp_lcd/rgb/rgb_lcd_rotation_sw.h
@@ -0,0 +1,162 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stddef.h>
+#include <stdint.h>
+#include "esp_bit_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RGB_PANEL_SWAP_XY  0
+#define RGB_PANEL_MIRROR_Y 1
+#define RGB_PANEL_MIRROR_X 2
+
+typedef enum {
+    ROTATE_MASK_SWAP_XY = BIT(RGB_PANEL_SWAP_XY),
+    ROTATE_MASK_MIRROR_Y = BIT(RGB_PANEL_MIRROR_Y),
+    ROTATE_MASK_MIRROR_X = BIT(RGB_PANEL_MIRROR_X),
+} panel_rotate_mask_t;
+
+__attribute__((always_inline))
+static inline void copy_pixel_8bpp(uint8_t *to, const uint8_t *from)
+{
+    *to++ = *from++;
+}
+
+__attribute__((always_inline))
+static inline void copy_pixel_16bpp(uint8_t *to, const uint8_t *from)
+{
+    *to++ = *from++;
+    *to++ = *from++;
+}
+
+__attribute__((always_inline))
+static inline void copy_pixel_24bpp(uint8_t *to, const uint8_t *from)
+{
+    *to++ = *from++;
+    *to++ = *from++;
+    *to++ = *from++;
+}
+
+#define COPY_PIXEL_CODE_BLOCK(_bpp)                                                               \
+    switch (rgb_panel->rotate_mask)                                                               \
+    {                                                                                             \
+    case 0:                                                                                       \
+    {                                                                                             \
+        uint8_t *to = fb + (y_start * h_res + x_start) * bytes_per_pixel;                         \
+        for (int y = y_start; y < y_end; y++)                                                     \
+        {                                                                                         \
+            memcpy(to, from, copy_bytes_per_line);                                                \
+            to += bytes_per_line;                                                                 \
+            from += copy_bytes_per_line;                                                          \
+        }                                                                                         \
+        bytes_to_flush = (y_end - y_start) * bytes_per_line;                                      \
+        flush_ptr = fb + y_start * bytes_per_line;                                                \
+    }                                                                                             \
+    break;                                                                                        \
+    case ROTATE_MASK_MIRROR_X:                                                                    \
+        for (int y = y_start; y < y_end; y++)                                                     \
+        {                                                                                         \
+            uint32_t index = (y * h_res + (h_res - 1 - x_start)) * bytes_per_pixel;               \
+            for (size_t x = x_start; x < x_end; x++)                                              \
+            {                                                                                     \
+                copy_pixel_##_bpp##bpp(to + index, from);                                         \
+                index -= bytes_per_pixel;                                                         \
+                from += bytes_per_pixel;                                                          \
+            }                                                                                     \
+        }                                                                                         \
+        bytes_to_flush = (y_end - y_start) * bytes_per_line;                                      \
+        flush_ptr = fb + y_start * bytes_per_line;                                                \
+        break;                                                                                    \
+    case ROTATE_MASK_MIRROR_Y:                                                                    \
+    {                                                                                             \
+        uint8_t *to = fb + ((v_res - 1 - y_start) * h_res + x_start) * bytes_per_pixel;           \
+        for (int y = y_start; y < y_end; y++)                                                     \
+        {                                                                                         \
+            memcpy(to, from, copy_bytes_per_line);                                                \
+            to -= bytes_per_line;                                                                 \
+            from += copy_bytes_per_line;                                                          \
+        }                                                                                         \
+        bytes_to_flush = (y_end - y_start) * bytes_per_line;                                      \
+        flush_ptr = fb + (v_res - y_end) * bytes_per_line;                                        \
+    }                                                                                             \
+    break;                                                                                        \
+    case ROTATE_MASK_MIRROR_X | ROTATE_MASK_MIRROR_Y:                                             \
+        for (int y = y_start; y < y_end; y++)                                                     \
+        {                                                                                         \
+            uint32_t index = ((v_res - 1 - y) * h_res + (h_res - 1 - x_start)) * bytes_per_pixel; \
+            for (size_t x = x_start; x < x_end; x++)                                              \
+            {                                                                                     \
+                copy_pixel_##_bpp##bpp(to + index, from);                                         \
+                index -= bytes_per_pixel;                                                         \
+                from += bytes_per_pixel;                                                          \
+            }                                                                                     \
+        }                                                                                         \
+        bytes_to_flush = (y_end - y_start) * bytes_per_line;                                      \
+        flush_ptr = fb + (v_res - y_end) * bytes_per_line;                                        \
+        break;                                                                                    \
+    case ROTATE_MASK_SWAP_XY:                                                                     \
+        for (int y = y_start; y < y_end; y++)                                                     \
+        {                                                                                         \
+            for (int x = x_start; x < x_end; x++)                                                 \
+            {                                                                                     \
+                uint32_t j = y * copy_bytes_per_line + x * bytes_per_pixel - offset;              \
+                uint32_t i = (x * h_res + y) * bytes_per_pixel;                                   \
+                copy_pixel_##_bpp##bpp(to + i, from + j);                                         \
+            }                                                                                     \
+        }                                                                                         \
+        bytes_to_flush = (x_end - x_start) * bytes_per_line;                                      \
+        flush_ptr = fb + x_start * bytes_per_line;                                                \
+        break;                                                                                    \
+    case ROTATE_MASK_SWAP_XY | ROTATE_MASK_MIRROR_X:                                              \
+        for (int y = y_start; y < y_end; y++)                                                     \
+        {                                                                                         \
+            for (int x = x_start; x < x_end; x++)                                                 \
+            {                                                                                     \
+                uint32_t j = y * copy_bytes_per_line + x * bytes_per_pixel - offset;              \
+                uint32_t i = (x * h_res + h_res - 1 - y) * bytes_per_pixel;                       \
+                copy_pixel_##_bpp##bpp(to + i, from + j);                                         \
+            }                                                                                     \
+        }                                                                                         \
+        bytes_to_flush = (x_end - x_start) * bytes_per_line;                                      \
+        flush_ptr = fb + x_start * bytes_per_line;                                                \
+        break;                                                                                    \
+    case ROTATE_MASK_SWAP_XY | ROTATE_MASK_MIRROR_Y:                                              \
+        for (int y = y_start; y < y_end; y++)                                                     \
+        {                                                                                         \
+            for (int x = x_start; x < x_end; x++)                                                 \
+            {                                                                                     \
+                uint32_t j = y * copy_bytes_per_line + x * bytes_per_pixel - offset;              \
+                uint32_t i = ((v_res - 1 - x) * h_res + y) * bytes_per_pixel;                     \
+                copy_pixel_##_bpp##bpp(to + i, from + j);                                         \
+            }                                                                                     \
+        }                                                                                         \
+        bytes_to_flush = (x_end - x_start) * bytes_per_line;                                      \
+        flush_ptr = fb + (v_res - x_end) * bytes_per_line;                                        \
+        break;                                                                                    \
+    case ROTATE_MASK_SWAP_XY | ROTATE_MASK_MIRROR_X | ROTATE_MASK_MIRROR_Y:                       \
+        for (int y = y_start; y < y_end; y++)                                                     \
+        {                                                                                         \
+            for (int x = x_start; x < x_end; x++)                                                 \
+            {                                                                                     \
+                uint32_t j = y * copy_bytes_per_line + x * bytes_per_pixel - offset;              \
+                uint32_t i = ((v_res - 1 - x) * h_res + h_res - 1 - y) * bytes_per_pixel;         \
+                copy_pixel_##_bpp##bpp(to + i, from + j);                                         \
+            }                                                                                     \
+        }                                                                                         \
+        bytes_to_flush = (x_end - x_start) * bytes_per_line;                                      \
+        flush_ptr = fb + (v_res - x_end) * bytes_per_line;                                        \
+        break;                                                                                    \
+    default:                                                                                      \
+        break;                                                                                    \
+    }
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_lcd/src/esp_lcd_common.c b/components/esp_lcd/src/esp_lcd_common.c
index 07ee21a98e2..7b739188bba 100644
--- a/components/esp_lcd/src/esp_lcd_common.c
+++ b/components/esp_lcd/src/esp_lcd_common.c
@@ -78,29 +78,3 @@ void lcd_com_remove_device(lcd_com_device_type_t device_type, int member_id)
     }
 }
 #endif // SOC_LCDCAM_SUPPORTED
-
-void lcd_com_mount_dma_data(dma_descriptor_t *desc_head, const void *buffer, size_t len)
-{
-    size_t prepared_length = 0;
-    uint8_t *data = (uint8_t *)buffer;
-    dma_descriptor_t *desc = desc_head;
-    while (len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE) {
-        desc->dw0.suc_eof = 0; // not the end of the transaction
-        desc->dw0.size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
-        desc->dw0.length = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
-        desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-        desc->buffer = &data[prepared_length];
-        desc = desc->next; // move to next descriptor
-        prepared_length += DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
-        len -= DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
-    }
-    if (len) {
-        desc->dw0.suc_eof = 1; // end of the transaction
-        desc->dw0.size = len;
-        desc->dw0.length = len;
-        desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-        desc->buffer = &data[prepared_length];
-        desc = desc->next; // move to next descriptor
-        prepared_length += len;
-    }
-}
diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt b/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt
index 30d912b096c..e895a0deeda 100644
--- a/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt
+++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/CMakeLists.txt
@@ -7,6 +7,9 @@ set(COMPONENTS main)
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(mipi_dsi_lcd_panel_test)
 
+target_add_binary_data(mipi_dsi_lcd_panel_test.elf "resources/pictures/hello.yuv" BINARY)
+target_add_binary_data(mipi_dsi_lcd_panel_test.elf "resources/pictures/world.yuv" BINARY)
+
 if(CONFIG_COMPILER_DUMP_RTL_FILES)
     add_custom_target(check_test_app_sections ALL
                       COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/idf_component.yml b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/idf_component.yml
index 27d4953b96c..2187eb1048b 100644
--- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/idf_component.yml
+++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/idf_component.yml
@@ -1,2 +1,2 @@
 dependencies:
-  esp_lcd_ili9881c: "~0.2.0"
+  esp_lcd_ek79007: "^1.0.0"
diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_board.h b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_board.h
index d1e57d9a47f..069e4369842 100644
--- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_board.h
+++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_board.h
@@ -9,16 +9,16 @@
 extern "C" {
 #endif
 
-// FPS = 80000000/(40+140+40+800)/(4+16+16+1280) = 60Hz
-#define MIPI_DSI_DPI_CLK_MHZ  80
-#define MIPI_DSI_LCD_H_RES    800
-#define MIPI_DSI_LCD_V_RES    1280
-#define MIPI_DSI_LCD_HSYNC    40
-#define MIPI_DSI_LCD_HBP      140
-#define MIPI_DSI_LCD_HFP      40
-#define MIPI_DSI_LCD_VSYNC    4
-#define MIPI_DSI_LCD_VBP      16
-#define MIPI_DSI_LCD_VFP      16
+// Refresh Rate = 48000000/(10+120+120+1024)/(1+20+10+600) = 60Hz
+#define MIPI_DSI_DPI_CLK_MHZ  48
+#define MIPI_DSI_LCD_H_RES    1024
+#define MIPI_DSI_LCD_V_RES    600
+#define MIPI_DSI_LCD_HSYNC    10
+#define MIPI_DSI_LCD_HBP      120
+#define MIPI_DSI_LCD_HFP      120
+#define MIPI_DSI_LCD_VSYNC    1
+#define MIPI_DSI_LCD_VBP      20
+#define MIPI_DSI_LCD_VFP      20
 
 #define TEST_MIPI_DSI_PHY_PWR_LDO_CHAN 3
 #define TEST_MIPI_DSI_PHY_PWR_LDO_VOLTAGE_MV 2500
diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c
index 85cef15288f..51299acb8c9 100644
--- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c
+++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_iram.c
@@ -16,7 +16,7 @@
 #include "esp_random.h"
 #include "esp_attr.h"
 #include "test_mipi_dsi_board.h"
-#include "esp_lcd_ili9881c.h"
+#include "esp_lcd_ek79007.h"
 
 IRAM_ATTR static bool test_rgb_panel_count_in_callback(esp_lcd_panel_handle_t panel, esp_lcd_dpi_panel_event_data_t *edata, void *user_ctx)
 {
@@ -32,12 +32,11 @@ static void IRAM_ATTR test_delay_post_cache_disable(void *args)
 
 #define TEST_IMG_SIZE (100 * 100 * sizeof(uint16_t))
 
-TEST_CASE("MIPI DSI draw bitmap (ILI9881C) IRAM Safe", "[mipi_dsi]")
+TEST_CASE("MIPI DSI draw bitmap (EK79007) IRAM Safe", "[mipi_dsi]")
 {
     esp_lcd_dsi_bus_handle_t mipi_dsi_bus;
     esp_lcd_panel_io_handle_t mipi_dbi_io;
     esp_lcd_panel_handle_t mipi_dpi_panel;
-    esp_lcd_panel_handle_t ili9881c_ctrl_panel;
 
     test_bsp_enable_dsi_phy_power();
 
@@ -59,22 +58,11 @@ TEST_CASE("MIPI DSI draw bitmap (ILI9881C) IRAM Safe", "[mipi_dsi]")
     };
     TEST_ESP_OK(esp_lcd_new_panel_io_dbi(mipi_dsi_bus, &dbi_config, &mipi_dbi_io));
 
-    esp_lcd_panel_dev_config_t lcd_dev_config = {
-        .bits_per_pixel = 16,
-        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
-        .reset_gpio_num = -1,
-    };
-    TEST_ESP_OK(esp_lcd_new_panel_ili9881c(mipi_dbi_io, &lcd_dev_config, &ili9881c_ctrl_panel));
-    TEST_ESP_OK(esp_lcd_panel_reset(ili9881c_ctrl_panel));
-    TEST_ESP_OK(esp_lcd_panel_init(ili9881c_ctrl_panel));
-    // turn on display
-    TEST_ESP_OK(esp_lcd_panel_disp_on_off(ili9881c_ctrl_panel, true));
-
     esp_lcd_dpi_panel_config_t dpi_config = {
         .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
         .dpi_clock_freq_mhz = MIPI_DSI_DPI_CLK_MHZ,
         .virtual_channel = 0,
-        .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB565,
+        .in_color_format = LCD_COLOR_FMT_RGB565,
         .video_timing = {
             .h_size = MIPI_DSI_LCD_H_RES,
             .v_size = MIPI_DSI_LCD_V_RES,
@@ -86,8 +74,22 @@ TEST_CASE("MIPI DSI draw bitmap (ILI9881C) IRAM Safe", "[mipi_dsi]")
             .vsync_front_porch = MIPI_DSI_LCD_VFP,
         },
     };
-    TEST_ESP_OK(esp_lcd_new_panel_dpi(mipi_dsi_bus, &dpi_config, &mipi_dpi_panel));
+    ek79007_vendor_config_t vendor_config = {
+        .mipi_config = {
+            .dsi_bus = mipi_dsi_bus,
+            .dpi_config = &dpi_config,
+        },
+    };
+    esp_lcd_panel_dev_config_t lcd_dev_config = {
+        .reset_gpio_num = -1,
+        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
+        .bits_per_pixel = 16,
+        .vendor_config = &vendor_config,
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_ek79007(mipi_dbi_io, &lcd_dev_config, &mipi_dpi_panel));
+    TEST_ESP_OK(esp_lcd_panel_reset(mipi_dpi_panel));
     TEST_ESP_OK(esp_lcd_panel_init(mipi_dpi_panel));
+
     uint32_t callback_calls = 0;
     esp_lcd_dpi_panel_event_callbacks_t cbs = {
         .on_refresh_done = test_rgb_panel_count_in_callback,
@@ -110,7 +112,6 @@ TEST_CASE("MIPI DSI draw bitmap (ILI9881C) IRAM Safe", "[mipi_dsi]")
     TEST_ASSERT(callback_calls > 2);
 
     TEST_ESP_OK(esp_lcd_panel_del(mipi_dpi_panel));
-    TEST_ESP_OK(esp_lcd_panel_del(ili9881c_ctrl_panel));
     TEST_ESP_OK(esp_lcd_panel_io_del(mipi_dbi_io));
     TEST_ESP_OK(esp_lcd_del_dsi_bus(mipi_dsi_bus));
     free(img);
diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c
index a31d26e01fd..aa5579c0d34 100644
--- a/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c
+++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c
@@ -15,14 +15,13 @@
 #include "esp_random.h"
 #include "esp_attr.h"
 #include "test_mipi_dsi_board.h"
-#include "esp_lcd_ili9881c.h"
+#include "esp_lcd_ek79007.h"
 
-TEST_CASE("MIPI DSI Pattern Generator (ILI9881C)", "[mipi_dsi]")
+TEST_CASE("MIPI DSI Pattern Generator (EK79007)", "[mipi_dsi]")
 {
     esp_lcd_dsi_bus_handle_t mipi_dsi_bus;
     esp_lcd_panel_io_handle_t mipi_dbi_io;
     esp_lcd_panel_handle_t mipi_dpi_panel;
-    esp_lcd_panel_handle_t ili9881c_ctrl_panel;
 
     test_bsp_enable_dsi_phy_power();
 
@@ -41,22 +40,11 @@ TEST_CASE("MIPI DSI Pattern Generator (ILI9881C)", "[mipi_dsi]")
     };
     TEST_ESP_OK(esp_lcd_new_panel_io_dbi(mipi_dsi_bus, &dbi_config, &mipi_dbi_io));
 
-    esp_lcd_panel_dev_config_t lcd_dev_config = {
-        .bits_per_pixel = 16,
-        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
-        .reset_gpio_num = -1,
-    };
-    TEST_ESP_OK(esp_lcd_new_panel_ili9881c(mipi_dbi_io, &lcd_dev_config, &ili9881c_ctrl_panel));
-    TEST_ESP_OK(esp_lcd_panel_reset(ili9881c_ctrl_panel));
-    TEST_ESP_OK(esp_lcd_panel_init(ili9881c_ctrl_panel));
-    // turn on display
-    TEST_ESP_OK(esp_lcd_panel_disp_on_off(ili9881c_ctrl_panel, true));
-
     esp_lcd_dpi_panel_config_t dpi_config = {
         .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
         .dpi_clock_freq_mhz = MIPI_DSI_DPI_CLK_MHZ,
         .virtual_channel = 0,
-        .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB565,
+        .in_color_format = LCD_COLOR_FMT_RGB888,
         .video_timing = {
             .h_size = MIPI_DSI_LCD_H_RES,
             .v_size = MIPI_DSI_LCD_V_RES,
@@ -68,7 +56,20 @@ TEST_CASE("MIPI DSI Pattern Generator (ILI9881C)", "[mipi_dsi]")
             .vsync_front_porch = MIPI_DSI_LCD_VFP,
         },
     };
-    TEST_ESP_OK(esp_lcd_new_panel_dpi(mipi_dsi_bus, &dpi_config, &mipi_dpi_panel));
+    ek79007_vendor_config_t vendor_config = {
+        .mipi_config = {
+            .dsi_bus = mipi_dsi_bus,
+            .dpi_config = &dpi_config,
+        },
+    };
+    esp_lcd_panel_dev_config_t lcd_dev_config = {
+        .reset_gpio_num = -1,
+        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
+        .bits_per_pixel = 24,
+        .vendor_config = &vendor_config,
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_ek79007(mipi_dbi_io, &lcd_dev_config, &mipi_dpi_panel));
+    TEST_ESP_OK(esp_lcd_panel_reset(mipi_dpi_panel));
     TEST_ESP_OK(esp_lcd_panel_init(mipi_dpi_panel));
 
     TEST_ESP_OK(esp_lcd_dpi_panel_set_pattern(mipi_dpi_panel, MIPI_DSI_PATTERN_BAR_HORIZONTAL));
@@ -80,7 +81,6 @@ TEST_CASE("MIPI DSI Pattern Generator (ILI9881C)", "[mipi_dsi]")
     TEST_ESP_OK(esp_lcd_dpi_panel_set_pattern(mipi_dpi_panel, MIPI_DSI_PATTERN_NONE));
 
     TEST_ESP_OK(esp_lcd_panel_del(mipi_dpi_panel));
-    TEST_ESP_OK(esp_lcd_panel_del(ili9881c_ctrl_panel));
     TEST_ESP_OK(esp_lcd_panel_io_del(mipi_dbi_io));
     TEST_ESP_OK(esp_lcd_del_dsi_bus(mipi_dsi_bus));
 
@@ -89,12 +89,11 @@ TEST_CASE("MIPI DSI Pattern Generator (ILI9881C)", "[mipi_dsi]")
 
 #define TEST_IMG_SIZE (100 * 100 * sizeof(uint16_t))
 
-TEST_CASE("MIPI DSI draw bitmap (ILI9881C)", "[mipi_dsi]")
+TEST_CASE("MIPI DSI draw bitmap (EK79007)", "[mipi_dsi]")
 {
     esp_lcd_dsi_bus_handle_t mipi_dsi_bus;
     esp_lcd_panel_io_handle_t mipi_dbi_io;
     esp_lcd_panel_handle_t mipi_dpi_panel;
-    esp_lcd_panel_handle_t ili9881c_ctrl_panel;
 
     test_bsp_enable_dsi_phy_power();
 
@@ -116,22 +115,11 @@ TEST_CASE("MIPI DSI draw bitmap (ILI9881C)", "[mipi_dsi]")
     };
     TEST_ESP_OK(esp_lcd_new_panel_io_dbi(mipi_dsi_bus, &dbi_config, &mipi_dbi_io));
 
-    esp_lcd_panel_dev_config_t lcd_dev_config = {
-        .bits_per_pixel = 16,
-        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
-        .reset_gpio_num = -1,
-    };
-    TEST_ESP_OK(esp_lcd_new_panel_ili9881c(mipi_dbi_io, &lcd_dev_config, &ili9881c_ctrl_panel));
-    TEST_ESP_OK(esp_lcd_panel_reset(ili9881c_ctrl_panel));
-    TEST_ESP_OK(esp_lcd_panel_init(ili9881c_ctrl_panel));
-    // turn on display
-    TEST_ESP_OK(esp_lcd_panel_disp_on_off(ili9881c_ctrl_panel, true));
-
     esp_lcd_dpi_panel_config_t dpi_config = {
         .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
         .dpi_clock_freq_mhz = MIPI_DSI_DPI_CLK_MHZ,
         .virtual_channel = 0,
-        .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB565,
+        .in_color_format = LCD_COLOR_FMT_RGB565,
         .video_timing = {
             .h_size = MIPI_DSI_LCD_H_RES,
             .v_size = MIPI_DSI_LCD_V_RES,
@@ -143,7 +131,20 @@ TEST_CASE("MIPI DSI draw bitmap (ILI9881C)", "[mipi_dsi]")
             .vsync_front_porch = MIPI_DSI_LCD_VFP,
         },
     };
-    TEST_ESP_OK(esp_lcd_new_panel_dpi(mipi_dsi_bus, &dpi_config, &mipi_dpi_panel));
+    ek79007_vendor_config_t vendor_config = {
+        .mipi_config = {
+            .dsi_bus = mipi_dsi_bus,
+            .dpi_config = &dpi_config,
+        },
+    };
+    esp_lcd_panel_dev_config_t lcd_dev_config = {
+        .reset_gpio_num = -1,
+        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
+        .bits_per_pixel = 16,
+        .vendor_config = &vendor_config,
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_ek79007(mipi_dbi_io, &lcd_dev_config, &mipi_dpi_panel));
+    TEST_ESP_OK(esp_lcd_panel_reset(mipi_dpi_panel));
     TEST_ESP_OK(esp_lcd_panel_init(mipi_dpi_panel));
 
     for (int i = 0; i < 100; i++) {
@@ -156,7 +157,6 @@ TEST_CASE("MIPI DSI draw bitmap (ILI9881C)", "[mipi_dsi]")
     }
 
     TEST_ESP_OK(esp_lcd_panel_del(mipi_dpi_panel));
-    TEST_ESP_OK(esp_lcd_panel_del(ili9881c_ctrl_panel));
     TEST_ESP_OK(esp_lcd_panel_io_del(mipi_dbi_io));
     TEST_ESP_OK(esp_lcd_del_dsi_bus(mipi_dsi_bus));
     free(img);
@@ -164,12 +164,11 @@ TEST_CASE("MIPI DSI draw bitmap (ILI9881C)", "[mipi_dsi]")
     test_bsp_disable_dsi_phy_power();
 }
 
-TEST_CASE("MIPI DSI with multiple frame buffers (ILI9881C)", "[mipi_dsi]")
+TEST_CASE("MIPI DSI with multiple frame buffers (EK79007)", "[mipi_dsi]")
 {
     esp_lcd_dsi_bus_handle_t mipi_dsi_bus;
     esp_lcd_panel_io_handle_t mipi_dbi_io;
     esp_lcd_panel_handle_t mipi_dpi_panel;
-    esp_lcd_panel_handle_t ili9881c_ctrl_panel;
 
     test_bsp_enable_dsi_phy_power();
 
@@ -188,22 +187,11 @@ TEST_CASE("MIPI DSI with multiple frame buffers (ILI9881C)", "[mipi_dsi]")
     };
     TEST_ESP_OK(esp_lcd_new_panel_io_dbi(mipi_dsi_bus, &dbi_config, &mipi_dbi_io));
 
-    esp_lcd_panel_dev_config_t lcd_dev_config = {
-        .bits_per_pixel = 16,
-        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
-        .reset_gpio_num = -1,
-    };
-    TEST_ESP_OK(esp_lcd_new_panel_ili9881c(mipi_dbi_io, &lcd_dev_config, &ili9881c_ctrl_panel));
-    TEST_ESP_OK(esp_lcd_panel_reset(ili9881c_ctrl_panel));
-    TEST_ESP_OK(esp_lcd_panel_init(ili9881c_ctrl_panel));
-    // turn on display
-    TEST_ESP_OK(esp_lcd_panel_disp_on_off(ili9881c_ctrl_panel, true));
-
     esp_lcd_dpi_panel_config_t dpi_config = {
         .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
         .dpi_clock_freq_mhz = MIPI_DSI_DPI_CLK_MHZ,
         .virtual_channel = 0,
-        .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB565,
+        .in_color_format = LCD_COLOR_FMT_RGB565,
         .num_fbs = 3, // the driver will allocate and maintain 3 frame buffers
         .video_timing = {
             .h_size = MIPI_DSI_LCD_H_RES,
@@ -216,7 +204,21 @@ TEST_CASE("MIPI DSI with multiple frame buffers (ILI9881C)", "[mipi_dsi]")
             .vsync_front_porch = MIPI_DSI_LCD_VFP,
         },
     };
-    TEST_ESP_OK(esp_lcd_new_panel_dpi(mipi_dsi_bus, &dpi_config, &mipi_dpi_panel));
+
+    ek79007_vendor_config_t vendor_config = {
+        .mipi_config = {
+            .dsi_bus = mipi_dsi_bus,
+            .dpi_config = &dpi_config,
+        },
+    };
+    esp_lcd_panel_dev_config_t lcd_dev_config = {
+        .reset_gpio_num = -1,
+        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
+        .bits_per_pixel = 16,
+        .vendor_config = &vendor_config,
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_ek79007(mipi_dbi_io, &lcd_dev_config, &mipi_dpi_panel));
+    TEST_ESP_OK(esp_lcd_panel_reset(mipi_dpi_panel));
     TEST_ESP_OK(esp_lcd_panel_init(mipi_dpi_panel));
 
     uint16_t *fbs[3];
@@ -236,9 +238,106 @@ TEST_CASE("MIPI DSI with multiple frame buffers (ILI9881C)", "[mipi_dsi]")
     }
 
     TEST_ESP_OK(esp_lcd_panel_del(mipi_dpi_panel));
-    TEST_ESP_OK(esp_lcd_panel_del(ili9881c_ctrl_panel));
     TEST_ESP_OK(esp_lcd_panel_io_del(mipi_dbi_io));
     TEST_ESP_OK(esp_lcd_del_dsi_bus(mipi_dsi_bus));
 
     test_bsp_disable_dsi_phy_power();
 }
+
+TEST_CASE("MIPI DSI draw YUV422 (EK79007)", "[mipi_dsi]")
+{
+    esp_lcd_dsi_bus_handle_t mipi_dsi_bus;
+    esp_lcd_panel_io_handle_t mipi_dbi_io;
+    esp_lcd_panel_handle_t mipi_dpi_panel;
+
+    test_bsp_enable_dsi_phy_power();
+
+    uint8_t *img = malloc(TEST_IMG_SIZE);
+    TEST_ASSERT_NOT_NULL(img);
+
+    esp_lcd_dsi_bus_config_t bus_config = {
+        .bus_id = 0,
+        .num_data_lanes = 2,
+        .phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT,
+        .lane_bit_rate_mbps = 1000, // 1000 Mbps
+    };
+    TEST_ESP_OK(esp_lcd_new_dsi_bus(&bus_config, &mipi_dsi_bus));
+
+    esp_lcd_dbi_io_config_t dbi_config = {
+        .virtual_channel = 0,
+        .lcd_cmd_bits = 8,
+        .lcd_param_bits = 8,
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_io_dbi(mipi_dsi_bus, &dbi_config, &mipi_dbi_io));
+
+    esp_lcd_dpi_panel_config_t dpi_config = {
+        .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
+        .dpi_clock_freq_mhz = MIPI_DSI_DPI_CLK_MHZ,
+        .virtual_channel = 0,
+
+        // YUV422 -> RGB888
+        .in_color_format = LCD_COLOR_FMT_YUV422,
+        .out_color_format = LCD_COLOR_FMT_RGB888,
+
+        .video_timing = {
+            .h_size = MIPI_DSI_LCD_H_RES,
+            .v_size = MIPI_DSI_LCD_V_RES,
+            .hsync_back_porch = MIPI_DSI_LCD_HBP,
+            .hsync_pulse_width = MIPI_DSI_LCD_HSYNC,
+            .hsync_front_porch = MIPI_DSI_LCD_HFP,
+            .vsync_back_porch = MIPI_DSI_LCD_VBP,
+            .vsync_pulse_width = MIPI_DSI_LCD_VSYNC,
+            .vsync_front_porch = MIPI_DSI_LCD_VFP,
+        },
+
+        .flags = {
+            .use_dma2d = true,
+        }
+    };
+    ek79007_vendor_config_t vendor_config = {
+        .mipi_config = {
+            .dsi_bus = mipi_dsi_bus,
+            .dpi_config = &dpi_config,
+        },
+    };
+    esp_lcd_panel_dev_config_t lcd_dev_config = {
+        .reset_gpio_num = -1,
+        .rgb_ele_order = LCD_RGB_ELEMENT_ORDER_RGB,
+        .bits_per_pixel = 24,
+        .vendor_config = &vendor_config,
+    };
+    TEST_ESP_OK(esp_lcd_new_panel_ek79007(mipi_dbi_io, &lcd_dev_config, &mipi_dpi_panel));
+
+    // Set color conversion configuration
+    esp_lcd_color_conv_config_t convert_config = {
+        .in_color_range = LCD_COLOR_RANGE_FULL,
+        .out_color_range = LCD_COLOR_RANGE_FULL,
+        .spec.yuv = {
+            .conv_std = LCD_YUV_CONV_STD_BT601,
+            .yuv422.in_pack_order = LCD_YUV422_PACK_ORDER_YUYV,
+        }
+    };
+    TEST_ESP_OK(esp_lcd_dpi_panel_set_color_conversion(mipi_dpi_panel, &convert_config));
+
+    TEST_ESP_OK(esp_lcd_panel_reset(mipi_dpi_panel));
+    TEST_ESP_OK(esp_lcd_panel_init(mipi_dpi_panel));
+
+    // YUV images are embedded in the firmware binary
+    extern const uint8_t image_hello_yuv_start[] asm("_binary_hello_yuv_start");
+    extern const uint8_t image_world_yuv_start[] asm("_binary_world_yuv_start");
+
+    printf("Draw YUV images\r\n");
+    for (int i = 0; i < 4; i++) {
+        TEST_ESP_OK(esp_lcd_panel_draw_bitmap(mipi_dpi_panel, 0, 0, 320, 320, image_hello_yuv_start));
+        vTaskDelay(pdMS_TO_TICKS(1000));
+        TEST_ESP_OK(esp_lcd_panel_draw_bitmap(mipi_dpi_panel, 0, 0, 320, 320, image_world_yuv_start));
+        vTaskDelay(pdMS_TO_TICKS(1000));
+    }
+
+    TEST_ESP_OK(esp_lcd_panel_del(mipi_dpi_panel));
+    TEST_ESP_OK(esp_lcd_panel_io_del(mipi_dbi_io));
+    TEST_ESP_OK(esp_lcd_del_dsi_bus(mipi_dsi_bus));
+    free(img);
+
+    test_bsp_disable_dsi_phy_power();
+}
diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/README.md b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/README.md
new file mode 100644
index 00000000000..5822bbd7732
--- /dev/null
+++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/README.md
@@ -0,0 +1,13 @@
+# How to generate the YUV image from the PNG image
+
+```bash
+ffmpeg -i hello.png -pix_fmt yuyv422 hello.yuv
+```
+
+## Supported YUV422 packing order
+
+| NAME     | NB_COMPONENTS  | BITS_PER_PIXEL | BIT_DEPTHS |
+|----------|----------------|----------------|------------|
+| yuyv422  | 3              | 16             | 8-8-8      |
+| yvyu422  | 3              | 16             | 8-8-8      |
+| uyvy422  | 3              | 16             | 8-8-8      |
diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.png b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.png
new file mode 100644
index 00000000000..b1172c410a8
Binary files /dev/null and b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.png differ
diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.yuv b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.yuv
new file mode 100644
index 00000000000..5dd8b5fd94e
--- /dev/null
+++ b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/hello.yuv
@@ -0,0 +1 @@
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diff --git a/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/world.yuv b/components/esp_lcd/test_apps/mipi_dsi_lcd/resources/pictures/world.yuv
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\ No newline at end of file
diff --git a/components/esp_lcd/test_apps/rgb_lcd/README.md b/components/esp_lcd/test_apps/rgb_lcd/README.md
index 47ecb029fc4..c9ab66b2b9b 100644
--- a/components/esp_lcd/test_apps/rgb_lcd/README.md
+++ b/components/esp_lcd/test_apps/rgb_lcd/README.md
@@ -1,4 +1,4 @@
-| Supported Targets | ESP32-S3 |
-| ----------------- | -------- |
+| Supported Targets | ESP32-P4 | ESP32-S3 |
+| ----------------- | -------- | -------- |
 
 This test app is used to test RGB565 interfaced LCDs.
diff --git a/components/esp_lcd/test_apps/rgb_lcd/main/test_app_main.c b/components/esp_lcd/test_apps/rgb_lcd/main/test_app_main.c
index 7b7ff5c8687..59989d90b11 100644
--- a/components/esp_lcd/test_apps/rgb_lcd/main/test_app_main.c
+++ b/components/esp_lcd/test_apps/rgb_lcd/main/test_app_main.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: CC0-1.0
  */
diff --git a/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_board.h b/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_board.h
index 180c519e561..3e65925a153 100644
--- a/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_board.h
+++ b/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_board.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,16 @@ extern "C" {
 
 #define TEST_LCD_H_RES         800
 #define TEST_LCD_V_RES         480
+#define TEST_LCD_HSYNC         1
+#define TEST_LCD_HBP           40
+#define TEST_LCD_HFP           20
+#define TEST_LCD_VSYNC         1
+#define TEST_LCD_VBP           10
+#define TEST_LCD_VFP           5
+
+#define TEST_LCD_PIXEL_CLOCK_HZ (18 * 1000 * 1000)
+
+#if CONFIG_IDF_TARGET_ESP32S3
 
 #define TEST_LCD_VSYNC_GPIO    3
 #define TEST_LCD_HSYNC_GPIO    46
@@ -34,7 +44,33 @@ extern "C" {
 #define TEST_LCD_DATA15_GPIO   40 // R4
 #define TEST_LCD_DISP_EN_GPIO  -1
 
-#define TEST_LCD_PIXEL_CLOCK_HZ (10 * 1000 * 1000)
+#elif CONFIG_IDF_TARGET_ESP32P4
+
+#define TEST_LCD_VSYNC_GPIO    41
+#define TEST_LCD_HSYNC_GPIO    39
+#define TEST_LCD_DE_GPIO       43
+#define TEST_LCD_PCLK_GPIO     33
+#define TEST_LCD_DATA0_GPIO    40 // B0
+#define TEST_LCD_DATA1_GPIO    42 // B1
+#define TEST_LCD_DATA2_GPIO    27 // B2
+#define TEST_LCD_DATA3_GPIO    29 // B3
+#define TEST_LCD_DATA4_GPIO    31 // B4
+#define TEST_LCD_DATA5_GPIO    21 // G0
+#define TEST_LCD_DATA6_GPIO    23 // G1
+#define TEST_LCD_DATA7_GPIO    26 // G2
+#define TEST_LCD_DATA8_GPIO    28 // G3
+#define TEST_LCD_DATA9_GPIO    30 // G4
+#define TEST_LCD_DATA10_GPIO   32 // G5
+#define TEST_LCD_DATA11_GPIO   6  // R0
+#define TEST_LCD_DATA12_GPIO   0  // R1
+#define TEST_LCD_DATA13_GPIO   15 // R2
+#define TEST_LCD_DATA14_GPIO   17 // R3
+#define TEST_LCD_DATA15_GPIO   19 // R4
+#define TEST_LCD_DISP_EN_GPIO  -1
+
+#else
+#error "Unsupported target"
+#endif
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c b/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c
index 8c39c32121f..0de40e884cc 100644
--- a/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c
+++ b/components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -62,12 +62,12 @@ static esp_lcd_panel_handle_t test_rgb_panel_initialization(size_t data_width, s
             .pclk_hz = TEST_LCD_PIXEL_CLOCK_HZ,
             .h_res = TEST_LCD_H_RES,
             .v_res = TEST_LCD_V_RES,
-            .hsync_back_porch = 68,
-            .hsync_front_porch = 20,
-            .hsync_pulse_width = 5,
-            .vsync_back_porch = 18,
-            .vsync_front_porch = 4,
-            .vsync_pulse_width = 1,
+            .hsync_back_porch = TEST_LCD_HBP,
+            .hsync_front_porch = TEST_LCD_HFP,
+            .hsync_pulse_width = TEST_LCD_HSYNC,
+            .vsync_back_porch = TEST_LCD_VBP,
+            .vsync_front_porch = TEST_LCD_VFP,
+            .vsync_pulse_width = TEST_LCD_VSYNC,
         },
         .flags.fb_in_psram = 1, // allocate frame buffer in PSRAM
         .flags.refresh_on_demand = refresh_on_demand,
@@ -99,6 +99,7 @@ TEST_CASE("lcd_rgb_panel_stream_mode", "[lcd]")
         int y_start = esp_random() % (TEST_LCD_V_RES - 100);
         memset(img, color_byte, TEST_IMG_SIZE);
         esp_lcd_panel_draw_bitmap(panel_handle, x_start, y_start, x_start + 100, y_start + 100, img);
+        vTaskDelay(pdMS_TO_TICKS(10));
     }
     printf("delete RGB panel\r\n");
     TEST_ESP_OK(esp_lcd_panel_del(panel_handle));
diff --git a/components/esp_lcd/test_apps/rgb_lcd/pytest_rgb_lcd.py b/components/esp_lcd/test_apps/rgb_lcd/pytest_rgb_lcd.py
index 497ca91e4d2..a9d77166a45 100644
--- a/components/esp_lcd/test_apps/rgb_lcd/pytest_rgb_lcd.py
+++ b/components/esp_lcd/test_apps/rgb_lcd/pytest_rgb_lcd.py
@@ -1,6 +1,5 @@
-# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import pytest
 from pytest_embedded import Dut
 
@@ -15,5 +14,19 @@
     ],
     indirect=True,
 )
-def test_rgb_lcd(dut: Dut) -> None:
+def test_rgb_lcd_esp32s3(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
+
+
+@pytest.mark.esp32p4
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'iram_safe',
+        'release',
+    ],
+    indirect=True,
+)
+def test_rgb_lcd_esp32p4(dut: Dut) -> None:
     dut.run_all_single_board_cases()
diff --git a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe
index 0643ce8884a..a0efad79df1 100644
--- a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe
+++ b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.ci.iram_safe
@@ -1,8 +1,5 @@
 CONFIG_COMPILER_DUMP_RTL_FILES=y
 CONFIG_LCD_RGB_ISR_IRAM_SAFE=y
-CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y
-# bounce buffer mode relies on GDMA EOF interrupt to be service-able
-CONFIG_GDMA_ISR_IRAM_SAFE=y
 CONFIG_COMPILER_OPTIMIZATION_NONE=y
 # silent the error check, as the error string are stored in rodata, causing RTL check failure
 CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
diff --git a/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.defaults.esp32p4 b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.defaults.esp32p4
new file mode 100644
index 00000000000..a27acf6f087
--- /dev/null
+++ b/components/esp_lcd/test_apps/rgb_lcd/sdkconfig.defaults.esp32p4
@@ -0,0 +1,5 @@
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_HEX=y
+CONFIG_SPIRAM_SPEED_200M=y
diff --git a/components/esp_netif/README.md b/components/esp_netif/README.md
deleted file mode 100644
index c2000c8cb45..00000000000
--- a/components/esp_netif/README.md
+++ /dev/null
@@ -1,107 +0,0 @@
-# ESP-NETIF architecture
-     
-                           |          (A) USER CODE                 |
-                           |                                        |
-          .................| init          settings      events     |
-          .                +----------------------------------------+
-          .                   .                |           *
-          .                   .                |           *
-      --------+            +===========================+   *     +-----------------------+
-              |            | new/config     get/set    |   *     |                       |
-              |            |                           |...*.....| init                  |
-              |            |---------------------------|   *     |                       |
-        init  |            |                           |****     |                       |
-        start |************|  event handler            |*********|  DHCP                 |
-        stop  |            |                           |         |                       |
-              |            |---------------------------|         |                       |
-              |            |                           |         |    NETIF              |
-        +-----|            |                           |         +-----------------+     |
-        | glue|---<----|---|  esp_netif_transmit       |--<------| netif_output    |     |
-        |     |        |   |                           |         |                 |     |
-        |     |--->----|---|  esp_netif_receive        |-->------| netif_input     |     |
-        |     |        |   |                           |         + ----------------+     |
-        |     |...<....|...|  esp_netif_free_rx_buffer |...<.....| packet buffer         |
-        +-----|     |  |   |                           |         |                       |
-              |     |  |   |                           |         |         (D)           |
-        (B)   |     |  |   |          (C)              |         +-----------------------+
-      --------+     |  |   +===========================+
-    communication   |  |                                               NETWORK STACK
-    DRIVER          |  |           ESP-NETIF
-                    |  |                                         +------------------+
-                    |  |   +---------------------------+.........| open/close       |
-                    |  |   |                           |         |                  |
-                    |  -<--|  l2tap_write              |-----<---|  write           |
-                    |      |                           |         |                  |
-                    ---->--|  esp_vfs_l2tap_eth_filter |----->---|  read            |
-                           |                           |         |                  |
-                           |            (E)            |         +------------------+
-                           +---------------------------+
-                                                                      USER CODE
-                                ESP-NETIF L2 TAP
-
-##  Data/event flow:
-
-* `........`     Initialization line from user code to esp-netif and comm driver
-
-* `--<--->--`    Data packets going from communication media to TCP/IP stack and back
-
-* `********`     Events agregated in ESP-NETIP propagates to driver, user code and network stack
-
-*  `|`           User settings and runtime configuration
-
-##  Components:
-
-###  A) User code, boiler plate
-Overall application interaction with communication media and network stack
-  
-  * initialization code
-      - create a new instance of ESP-NETIF
-      - configure the object with
-          1) netif specific options (flags, behaviour, name)
-          2) network stack options (netif init and input functions, not publicly available)
-          3) IO driver specific options (transmit, tx_free functions, IO driver handle)
-    - setup event handlers
-    - use default handlers for common interfaces defined in IO drivers; or define a specific handlers
-                        for customised behaviour/new interfaces
-    - register handlers for app related events (such as IP lost/acquired)
-  - interact with network interfaces using ESP-NETIF API
-
-###  B) Communication driver, IO driver, media driver
-  * event handler
-      - define behaviour patterns of interaction with ESP-NETIF (example: ehternet link-up -> turn netif on)
-  * glue IO layer: adapt the input/output functions to use esp-netif transmit/input/free_rx
-      - install driver_transmit to appropriate ESP-NETIF object, so that outgoing packets from
-                network stack are passed to the IO driver
-      - calls esp_netif_receive to pass incoming data to network stack
-
-###  C) ESP-NETIF
-* init API (new, configure)
-* IO API: for passing data between IO driver and network stack
-* event/action API (esp-netif lifecycle management)
-  - building blocks for designing event handlers
-* setters, getters
-* network stack abstraction: enabling user interaction with TCP/IP stack
-  - netif up/down
-  - DHCP server, client
-  - DNS API
-* driver conversion utilities
-
-###  D) Network stack: no public interaction with user code (wrtt interfaces)
-
-###  E) ESP-NETIF L2 TAP Interface
-The ESP-NETIF L2 TAP interface is ESP-IDF mechanism utilized to access Data Link Layer (L2 per OSI/ISO) for frame reception and
-transmission from user application. Its typical usage in embedded world might be implementation of non-IP related protocols
-such as PTP, Wake on LAN and others. Note that only Ethernet (IEEE 802.3)
-is currently supported. 
-
-From user perspective, the ESP-NETIF L2 TAP interface is accessed using file descriptors of VFS which provides a file-like interfacing
-(using functions like ``open()``, ``read()``, ``write()``, etc).
- 
-There is only one ESP-NETIF L2 TAP interface device (path name) available. However multiple file descriptors with different configuration
-can be opened at a time since the ESP-NETIF L2 TAP interface can be understood as generic entry point to the NETIF internal structure.
-Important is then specific configuration of particular file descriptor. It can be configured to give an access to specific Network Interface
-identified by ``if_key`` (e.g. `ETH_DEF`) and to filter only specific frames based on their type (e.g. Ethernet type in case of IEEE 802.3).
-Filtering only specific frames is crucial since the ESP-NETIF L2 TAP needs to work along with IP stack and so the IP related traffic
-(IP, ARP, etc.) should not be passed directly to the user application. Even though such option is still configurable, it is not recommended in
-standard use cases. Filtering is also advantageous from a perspective the user’s application gets access only to frame types it is interested
-in and the remaining traffic is either passed to other L2 TAP file descriptors or to IP stack.
diff --git a/components/esp_netif/include/esp_vfs_l2tap.h b/components/esp_netif/include/esp_vfs_l2tap.h
index 27c807beff4..8c76c6fbcae 100644
--- a/components/esp_netif/include/esp_vfs_l2tap.h
+++ b/components/esp_netif/include/esp_vfs_l2tap.h
@@ -1,13 +1,15 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+#include <stdalign.h>
 #include "esp_err.h"
 
+
 #define L2TAP_VFS_DEFAULT_PATH "/dev/net/tap"
 #define L2TAP_VFS_CONFIG_DEFAULT()                  \
     {                                               \
@@ -29,20 +31,76 @@ typedef struct {
 } l2tap_vfs_config_t;
 
 typedef enum {
-    L2TAP_S_RCV_FILTER,
-    L2TAP_G_RCV_FILTER,
-    L2TAP_S_INTF_DEVICE,
-    L2TAP_G_INTF_DEVICE,
-    L2TAP_S_DEVICE_DRV_HNDL,
-    L2TAP_G_DEVICE_DRV_HNDL
+    L2TAP_S_RCV_FILTER,         /*!< Set Ethertype filter, frames with this type to be passed to the file descriptor. */
+    L2TAP_G_RCV_FILTER,         /*!< Get current Ethertype filter. */
+    L2TAP_S_INTF_DEVICE,        /*!< Bound the file descriptor to a specific Network Interface is identified by its ``if_key``. */
+    L2TAP_G_INTF_DEVICE,        /*!< Get the Network Interface ``if_key`` the file descriptor is bound to. */
+    L2TAP_S_DEVICE_DRV_HNDL,    /*!< Bound the file descriptor to a specific Network Interface identified by IO Driver handle. */
+    L2TAP_G_DEVICE_DRV_HNDL,    /*!< Get the Network Interface IO Driver handle the file descriptor is bound to. */
+    L2TAP_S_TIMESTAMP_EN,       /*!< Enables the hardware Time Stamping (TS) processing by the file descriptor. TS needs to be supported by hardware and enabled in the IO driver. */
 } l2tap_ioctl_opt_t;
 
+/**
+ * @brief Information Record (IREC) Header Type indicates expected type of Header Data
+ *
+ */
+typedef enum {
+    L2TAP_IREC_INVALID      = -1,   /*!< Indicate invalid IREC (data is not valid)*/
+    L2TAP_IREC_TIME_STAMP   = 1     /*!< To retrieve time stamp in `struct timespec` format */
+} l2tap_irec_type_t;
+
+
+/**
+ * @brief Information Record (IREC)
+ *
+ */
+typedef struct
+{
+    size_t len;                         /*!< Length of the record including header and data*/
+    l2tap_irec_type_t type;             /*!< Type of the record */
+    alignas(long long) uint8_t data[];  /*!< Records Data aligned to double word */
+} l2tap_irec_hdr_t;
+
+/**
+ * @brief Extended Buffer
+ *
+ * @attention Use macros when allocating buffer for Information Records and when manipulating with data in the records
+ *            to ensure proper memory alignment
+ *
+ */
+typedef struct {
+    size_t info_recs_len;       /*!< Length of Information Records buffer */
+    void *info_recs_buff;       /*!< Buffer holding extended information (IRECs) related to IO frames */
+    size_t buff_len;            /*!< Length of the actual IO Frame buffer */
+    void *buff;                 /*!< Pointer to the IO Frame buffer */
+} l2tap_extended_buff_t;
+
+
+/**
+ * @brief Macros for operations with Information Records
+ *
+ * Align to double word size to each info record starts aligned in memory even if not aligned
+ * info data size is used by previous record. Double word alignment (at 32-bit arch) is needed when accessing
+ * double word variables or structs containing double word variables.
+ *
+ */
+#define L2TAP_ALIGN(size) (((size) + sizeof(long long) - 1U) & ~(sizeof(long long) - 1U))
+
+#define L2TAP_IREC_LEN(size)                    (sizeof(l2tap_irec_hdr_t) + size)
+#define L2TAP_IREC_SPACE(size)                  (L2TAP_ALIGN(L2TAP_IREC_LEN(size)))
+#define L2TAP_IREC_FIRST(ext_buff)              (ext_buff)->info_recs_len >= sizeof(l2tap_irec_hdr_t) ? (l2tap_irec_hdr_t *)(ext_buff)->info_recs_buff : NULL
+#define L2TAP_IREC_NEXT(ext_buff, curr_rec)     (((curr_rec) == NULL) ? L2TAP_IREC_FIRST(ext_buff) : \
+                                                (uint8_t *)(curr_rec) + L2TAP_ALIGN((curr_rec)->len) + L2TAP_ALIGN(sizeof(l2tap_irec_hdr_t)) > \
+                                                    (uint8_t *)(ext_buff)->info_recs_buff + (ext_buff)->info_recs_len ? \
+                                                        NULL : \
+                                                        (l2tap_irec_hdr_t *)(void *)(((uint8_t *)(curr_rec) + L2TAP_ALIGN((curr_rec)->len))))
+
 /**
  * @brief Add L2 TAP virtual filesystem driver
  *
  * This function must be called prior usage of ESP-NETIF L2 TAP Interface
  *
- * @param config L2 TAP virtual filesystem driver configuration. Default base path /dev/net/tap is used when this paramenter is NULL.
+ * @param config L2 TAP virtual filesystem driver configuration. Default base path /dev/net/tap is used when this parameter is NULL.
  * @return esp_err_t
  *          - ESP_OK on success
  */
@@ -51,7 +109,7 @@ esp_err_t esp_vfs_l2tap_intf_register(l2tap_vfs_config_t *config);
 /**
  * @brief Removes L2 TAP virtual filesystem driver
  *
- * @param base_path Base path to the L2 TAP virtual filesystem driver. Default path /dev/net/tap is used when this paramenter is NULL.
+ * @param base_path Base path to the L2 TAP virtual filesystem driver. Default path /dev/net/tap is used when this parameter is NULL.
  * @return esp_err_t
  *          - ESP_OK on success
  */
@@ -63,10 +121,25 @@ esp_err_t esp_vfs_l2tap_intf_unregister(const char *base_path);
  * @param driver_handle handle of driver at which the frame was received
  * @param buff received L2 frame
  * @param size input length of the L2 frame which is set to 0 when frame is filtered into L2 TAP
+ * @param info extra information about received Ethernet frame
  * @return esp_err_t
  *                  - ESP_OK is always returned
  */
-esp_err_t esp_vfs_l2tap_eth_filter(l2tap_iodriver_handle driver_handle, void *buff, size_t *size);
+esp_err_t esp_vfs_l2tap_eth_filter_frame(l2tap_iodriver_handle driver_handle, void *buff, size_t *size, void *info);
+
+/**
+ * @brief Wrapper over L2 TAP filter function to ensure backward compatibility.
+ *
+ * This macro is provided for backward compatibility with the original `esp_vfs_l2tap_eth_filter` function.
+ * It calls `esp_vfs_l2tap_eth_filter_frame()` with the `info` parameter set to `NULL`, which means
+ * L2 TAP features that depend on extra information about the received Ethernet frame (e.g., timestamps)
+ * will not work as expected.
+ *
+ * @note For new implementations, it is recommended to use `esp_vfs_l2tap_eth_filter_frame()` directly to
+ *       take advantage of the extended functionality.
+ */
+#define esp_vfs_l2tap_eth_filter(drv_hndl, buf, size) esp_vfs_l2tap_eth_filter_frame(drv_hndl, buf, size, NULL)
+
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_netif/test_apps/.build-test-rules.yml b/components/esp_netif/test_apps/.build-test-rules.yml
index d6bcee11b8f..7baad883016 100644
--- a/components/esp_netif/test_apps/.build-test-rules.yml
+++ b/components/esp_netif/test_apps/.build-test-rules.yml
@@ -13,9 +13,9 @@ components/esp_netif/test_apps/test_app_esp_netif:
 
 components/esp_netif/test_apps/test_app_vfs_l2tap:
   disable:
-    - if: IDF_TARGET not in ["esp32"]
+    - if: IDF_TARGET not in ["esp32", "esp32p4"]
       temporary: true
-      reason: Ethernet runners currently use only ESP32
+      reason: Not needed to test on all targets (chosen two, one for each architecture plus P4 tests time stamping)
   depends_components:
     - esp_netif
     - lwip
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md b/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md
index f708a1985a3..4873c15b15b 100644
--- a/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md
+++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 |
-| ----------------- | ----- |
+| Supported Targets | ESP32 | ESP32-P4 |
+| ----------------- | ----- | -------- |
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c b/components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c
index 074112bbe8a..ff766f309ba 100644
--- a/components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c
+++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/main/test_vfs_l2tap.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,6 +24,7 @@
 #include "sdkconfig.h"
 #include "arpa/inet.h" // for ntohs, etc.
 #include "lwip/prot/ethernet.h" // Ethernet headers
+#include "soc/soc_caps.h"
 
 #include "unity.h"
 #include "test_utils.h"
@@ -32,6 +33,7 @@
 
 #define ETH_FILTER_LE 0x7A05
 #define ETH_FILTER_BE 0x057A
+#define ETH_TYPE_PTP  0x88F7
 
 #define ETH_START_BIT BIT(0)
 #define ETH_STOP_BIT BIT(1)
@@ -68,6 +70,33 @@ typedef struct {
     };
 } test_vfs_eth_tap_msg_t;
 
+// PTPv2 header
+typedef struct {
+    uint8_t message_type;           // 4 bits: Message Type
+    uint8_t version;                // 4 bits: PTP version
+    uint16_t message_length;        // 16 bits: Total length of the PTP message
+    uint8_t domain_number;          // 8 bits: Domain number
+    uint8_t reserved1;              // Reserved (8 bits)
+    uint16_t flags;                 // 16 bits: Flags field
+    int64_t correction_field;       // 64 bits: Correction field
+    uint32_t reserved2;             // Reserved (32 bits)
+    uint64_t clock_identity;    // 64 bits: Clock identity
+    uint16_t port_number;       // 16 bits: Port number
+    uint16_t sequence_id;           // 16 bits: Sequence ID
+    uint8_t control_field;          // 8 bits: Control field (deprecated)
+    int8_t log_message_interval;    // 8 bits: Log message interval
+} __attribute__((packed)) ptpv2_hdr_t;
+
+typedef struct {
+    ptpv2_hdr_t ptp_hdr;
+    uint64_t timestamp;
+} __attribute__((packed)) ptp_msg_t;
+
+typedef struct {
+    struct eth_hdr eth_hdr;
+    ptp_msg_t ptp_msg;
+} __attribute__((packed)) test_eth_ptp_msg_t;
+
 /* =============================================================================
  *                              Common Routines
  * ============================================================================= */
@@ -163,6 +192,9 @@ static void ethernet_init(test_vfs_eth_network_t *network_hndls)
     eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG();
     network_hndls->mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config);
     eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG();
+#ifdef CONFIG_IDF_TARGET_ESP32P4
+    phy_config.reset_gpio_num = 51;
+#endif // CONFIG_IDF_TARGET_ESP32P4
     network_hndls->phy = esp_eth_phy_new_ip101(&phy_config);
     esp_eth_config_t eth_config = ETH_DEFAULT_CONFIG(network_hndls->mac, network_hndls->phy);
     network_hndls->eth_handle = NULL;
@@ -205,7 +237,7 @@ static void ethernet_deinit(test_vfs_eth_network_t *network_hndls)
     TEST_ESP_OK(esp_event_loop_delete_default());
 }
 
-// Global test message send by "send_task"
+// Global test message
 static test_vfs_eth_tap_msg_t s_test_msg = {
     .header = {
         .src.addr = {0},
@@ -297,6 +329,7 @@ typedef struct {
     int eth_tap_fd;
     SemaphoreHandle_t sem;
     bool on_select;
+    int queue_frames_num;
 } open_close_task_ctrl_t;
 
 static void open_read_task(void *task_param)
@@ -318,30 +351,35 @@ static void open_read_task(void *task_param)
     uint16_t eth_type_filter = ETH_FILTER_LE;
     TEST_ASSERT_NOT_EQUAL(-1, ioctl(task_control->eth_tap_fd, L2TAP_S_RCV_FILTER, &eth_type_filter));
 
-    xSemaphoreGive(task_control->sem);
-
-    if (task_control->on_select == true) {
-        ESP_LOGI(TAG, "task1: going to block on select...");
-        struct timeval tv;
-        tv.tv_sec = 1;
-        tv.tv_usec = 0;
+    if (task_control->queue_frames_num > 0) {
+        for (int i = 0; i < task_control->queue_frames_num; i++) {
+            TEST_ASSERT_NOT_EQUAL(-1, write(task_control->eth_tap_fd, &s_test_msg, sizeof(s_test_msg)));
+        }
+    } else {
+        xSemaphoreGive(task_control->sem);
+        if (task_control->on_select == true) {
+            ESP_LOGI(TAG, "task1: going to block on select...");
+            struct timeval tv;
+            tv.tv_sec = 1;
+            tv.tv_usec = 0;
 
-        fd_set rfds;
-        FD_ZERO(&rfds);
-        FD_SET(task_control->eth_tap_fd, &rfds);
+            fd_set rfds;
+            FD_ZERO(&rfds);
+            FD_SET(task_control->eth_tap_fd, &rfds);
 
-        // it is expected that blocking select is not unblocked by close and it timeouts (the fd number may be reused later
-        // though and so select released but that's not tested here)
-        TEST_ASSERT_EQUAL(0, select(task_control->eth_tap_fd + 1, &rfds, NULL, NULL, &tv));
-        ESP_LOGI(TAG, "task1: select timeout");
+            // it is expected that blocking select is not unblocked by close and it timeouts (the fd number may be reused later
+            // though and so select released but that's not tested here)
+            TEST_ASSERT_EQUAL(0, select(task_control->eth_tap_fd + 1, &rfds, NULL, NULL, &tv));
+            ESP_LOGI(TAG, "task1: select timeout");
 
-        // get an error when try to use closed fd
-        TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, in_buf_size));
-    } else {
-        ESP_LOGI(TAG, "task1: going to block on read...");
-        // it is expected that blocking read is unblocked by close
-        TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, in_buf_size));
-        ESP_LOGI(TAG, "task1: unblocked");
+            // get an error when try to use closed fd
+            TEST_ASSERT_EQUAL(-1, read(task_control->eth_tap_fd, in_buffer, in_buf_size));
+        } else {
+            ESP_LOGI(TAG, "task1: going to block on read...");
+            // it is expected that blocking read is unblocked by close and we read zero bytes
+            TEST_ASSERT_EQUAL(0, read(task_control->eth_tap_fd, in_buffer, in_buf_size));
+            ESP_LOGI(TAG, "task1: unblocked");
+        }
     }
     xSemaphoreGive(task_control->sem);
 
@@ -355,6 +393,10 @@ static void close_task(void *task_param)
     ESP_LOGI(TAG, "task2: closing...");
     TEST_ASSERT_EQUAL(0, close(task_control->eth_tap_fd));
 
+    if (task_control->queue_frames_num > 0) {
+        // since there is no blocking "read" task in this scenario, we need to signal that close finished
+        xSemaphoreGive(task_control->sem);
+    }
     vTaskDelete(NULL);
 }
 
@@ -368,6 +410,7 @@ TEST_CASE("esp32 l2tap - open/close", "[ethernet]")
     open_close_task_ctrl_t task_control;
     task_control.sem = xSemaphoreCreateBinary();
     task_control.on_select = false;
+    task_control.queue_frames_num = 0;
 
     // ==========================================================
     // Close when blocking on read
@@ -381,7 +424,6 @@ TEST_CASE("esp32 l2tap - open/close", "[ethernet]")
     ESP_LOGI(TAG, "Verify closing blocking read from lower priority task...");
     xTaskCreate(open_read_task, "open_read_task", 4096, &task_control, 10, NULL);
     TEST_ASSERT_NOT_EQUAL(pdFALSE, xSemaphoreTake(task_control.sem, pdMS_TO_TICKS(1000)));
-    // Close blocking read from lower priority task
     xTaskCreate(close_task, "close_task", 4096, &task_control, 5, NULL);
     TEST_ASSERT_NOT_EQUAL(pdFALSE, xSemaphoreTake(task_control.sem, pdMS_TO_TICKS(1000)));
 
@@ -398,7 +440,23 @@ TEST_CASE("esp32 l2tap - open/close", "[ethernet]")
     ESP_LOGI(TAG, "Verify closing blocking select from lower priority task...");
     xTaskCreate(open_read_task, "open_read_task", 4096, &task_control, 10, NULL);
     TEST_ASSERT_NOT_EQUAL(pdFALSE, xSemaphoreTake(task_control.sem, pdMS_TO_TICKS(2000)));
-    // Close blocking read from lower priority task
+    xTaskCreate(close_task, "close_task", 4096, &task_control, 5, NULL);
+    TEST_ASSERT_NOT_EQUAL(pdFALSE, xSemaphoreTake(task_control.sem, pdMS_TO_TICKS(2000)));
+
+    // ==========================================================
+    // Close when buffered frames pending in L2 TAP
+    // ==========================================================
+    // indicate to queue frames
+    task_control.queue_frames_num = 3;
+    ESP_LOGI(TAG, "Verify closing from higher priority task when when buffered frames pending...");
+    xTaskCreate(open_read_task, "open_read_task", 4096, &task_control, 5, NULL);
+    TEST_ASSERT_NOT_EQUAL(pdFALSE, xSemaphoreTake(task_control.sem, pdMS_TO_TICKS(2000)));
+    xTaskCreate(close_task, "close_task", 4096, &task_control, 10, NULL);
+    TEST_ASSERT_NOT_EQUAL(pdFALSE, xSemaphoreTake(task_control.sem, pdMS_TO_TICKS(2000)));
+
+    ESP_LOGI(TAG, "Verify closing from lower priority task when when buffered frames pending...");
+    xTaskCreate(open_read_task, "open_read_task", 4096, &task_control, 10, NULL);
+    TEST_ASSERT_NOT_EQUAL(pdFALSE, xSemaphoreTake(task_control.sem, pdMS_TO_TICKS(2000)));
     xTaskCreate(close_task, "close_task", 4096, &task_control, 5, NULL);
     TEST_ASSERT_NOT_EQUAL(pdFALSE, xSemaphoreTake(task_control.sem, pdMS_TO_TICKS(2000)));
 
@@ -759,6 +817,227 @@ TEST_CASE("esp32 l2tap - read/write multiple fd's used by multiple tasks", "[eth
     ethernet_deinit(&eth_network_hndls);
 }
 
+/* ============================================================================= */
+/**
+ * @brief Verifies time stamping feature
+ *
+ */
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+TEST_CASE("esp32 l2tap - time stamping", "[ethernet]")
+{
+    test_vfs_eth_network_t eth_network_hndls;
+
+    TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_register(NULL));
+    ethernet_init(&eth_network_hndls);
+
+    int eth_tap_fd = open("/dev/net/tap", 0);
+    TEST_ASSERT_NOT_EQUAL(-1, eth_tap_fd);
+
+    // Set Ethernet interface on which to get raw frames
+    TEST_ASSERT_NOT_EQUAL(-1, ioctl(eth_tap_fd, L2TAP_S_INTF_DEVICE, "ETH_DEF"));
+    // Check the Ethernet interface was assigned
+    char *if_key_str;
+    TEST_ASSERT_NOT_EQUAL(-1, ioctl(eth_tap_fd, L2TAP_G_INTF_DEVICE, &if_key_str));
+    TEST_ASSERT_EQUAL_STRING("ETH_DEF", if_key_str);
+
+    // Set the Ethertype filter (frames with this type will be available through the eth_tap_fd)
+    uint16_t eth_type_filter = ETH_TYPE_PTP;
+    TEST_ASSERT_NOT_EQUAL(-1, ioctl(eth_tap_fd, L2TAP_S_RCV_FILTER, &eth_type_filter));
+
+    // Enable time stamping in driver
+    bool ts_enable = true;
+    TEST_ESP_OK(esp_eth_ioctl(eth_network_hndls.eth_handle, ETH_MAC_ESP_CMD_PTP_ENABLE, &ts_enable));
+
+    test_eth_ptp_msg_t test_ptp_msg = {
+        .eth_hdr = {
+            // Note that PTPv2 MAC 01:80:C2:00:00:0E is reserved for "Peer delay messages" which are currently not
+            // enabled to be snapped by internal EMAC, hence not tested
+            .dest.addr = {0x01, 0x1b, 0x19, 0x0, 0x0, 0x0},
+            .type = htons(ETH_TYPE_PTP)
+        },
+        .ptp_msg = {
+            .ptp_hdr = {
+                .message_type = 1,
+                .version = 2,
+                .message_length = htons(sizeof(ptp_msg_t)),
+                .sequence_id = 0
+            },
+            .timestamp = 0,
+        }
+    };
+    uint16_t exp_sequence_id = test_ptp_msg.ptp_msg.ptp_hdr.sequence_id;
+    TEST_ESP_OK(esp_eth_ioctl(eth_network_hndls.eth_handle, ETH_CMD_G_MAC_ADDR, &test_ptp_msg.eth_hdr.src.addr));
+
+    // wrap "Info Records Buffer" into union to ensure proper alignment of data (this is typically needed when
+    // accessing double word variables or structs containing double word variables)
+    union {
+        uint8_t info_recs_buff[L2TAP_IREC_SPACE(sizeof(struct timespec))];
+        l2tap_irec_hdr_t align;
+    } u;
+
+    l2tap_extended_buff_t ptp_msg_ext_buff;
+    ptp_msg_ext_buff.info_recs_len = sizeof(u.info_recs_buff);
+    ptp_msg_ext_buff.info_recs_buff = u.info_recs_buff;
+
+    l2tap_irec_hdr_t *ts_info = L2TAP_IREC_FIRST(&ptp_msg_ext_buff);
+    ts_info->len = L2TAP_IREC_LEN(sizeof(struct timespec));
+    ts_info->type = L2TAP_IREC_TIME_STAMP;
+
+    ESP_LOGI(TAG, "Verify response to read TS when not enabled in TAP");
+    test_ptp_msg.ptp_msg.ptp_hdr.sequence_id++;
+    exp_sequence_id++;
+    ptp_msg_ext_buff.buff = &test_ptp_msg;
+    ptp_msg_ext_buff.buff_len = sizeof(test_ptp_msg);
+    int n = write(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    // when input len is 0 and no special function of tap => expected standard behavior, i.e. nothing was written
+    TEST_ASSERT_EQUAL(0, n);
+    ptp_msg_ext_buff.buff = in_buffer;
+    ptp_msg_ext_buff.buff_len = IN_BUFFER_SIZE;
+    n = read(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    // when input len is 0 and no special function of tap => expected standard behavior, i.e. nothing was read
+    TEST_ASSERT_EQUAL(0, n);
+
+    // Enable time stamping in L2TAP, since now we can read TS
+    TEST_ASSERT_NOT_EQUAL(-1, ioctl(eth_tap_fd, L2TAP_S_TIMESTAMP_EN));
+
+    ESP_LOGI(TAG, "Verify response when trying to write/read in standard way (input len > 0) but tap configured as TS enabled");
+    test_ptp_msg.ptp_msg.ptp_hdr.sequence_id++;
+    exp_sequence_id++;
+    n = write(eth_tap_fd, &test_ptp_msg, sizeof(test_ptp_msg));
+    TEST_ASSERT_EQUAL(-1, n);
+    TEST_ASSERT_EQUAL(EINVAL, errno);
+    n = read(eth_tap_fd, &in_buffer, sizeof(test_ptp_msg));
+    TEST_ASSERT_EQUAL(-1, n);
+    TEST_ASSERT_EQUAL(EINVAL, errno);
+
+    ESP_LOGI(TAG, "Verify response to invalid info record type for write");
+    ts_info->type = 0xFF;
+    test_ptp_msg.ptp_msg.ptp_hdr.sequence_id++;
+    exp_sequence_id++;
+    ptp_msg_ext_buff.buff = &test_ptp_msg;
+    ptp_msg_ext_buff.buff_len = sizeof(test_ptp_msg);
+    n = write(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    TEST_ASSERT_EQUAL(sizeof(test_ptp_msg), n); // invalid info record is ignored and write is successful
+    // since write was successful, empty L2 TAP queue
+    ptp_msg_ext_buff.buff = in_buffer;
+    ptp_msg_ext_buff.buff_len = IN_BUFFER_SIZE;
+    n = read(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    int exp_n = sizeof(test_ptp_msg) < 60 ? 60 : sizeof(test_ptp_msg);
+    TEST_ASSERT_EQUAL(exp_n, n);
+    TEST_ASSERT_EQUAL(exp_sequence_id, ((test_eth_ptp_msg_t *)in_buffer)->ptp_msg.ptp_hdr.sequence_id);
+
+
+    ESP_LOGI(TAG, "Verify response to invalid record type for read (first need to write correctly)");
+    ts_info->type = L2TAP_IREC_TIME_STAMP;
+    test_ptp_msg.ptp_msg.ptp_hdr.sequence_id++;
+    exp_sequence_id++;
+    ptp_msg_ext_buff.buff = &test_ptp_msg;
+    ptp_msg_ext_buff.buff_len = sizeof(test_ptp_msg);
+    n = write(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    TEST_ASSERT_EQUAL(sizeof(test_ptp_msg), n);
+    ts_info->type = 0xFF;
+    ptp_msg_ext_buff.buff = in_buffer;
+    ptp_msg_ext_buff.buff_len = IN_BUFFER_SIZE;
+    n = read(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    exp_n = sizeof(test_ptp_msg) < 60 ? 60 : sizeof(test_ptp_msg); // minimum Ethernet frame has size of 60B
+    TEST_ASSERT_EQUAL(exp_n, n); // invalid info record is ignored and read is successful
+
+    ESP_LOGI(TAG, "Verify response to invalid record len for write");
+    ts_info->type = L2TAP_IREC_TIME_STAMP;
+    ts_info->len = L2TAP_IREC_LEN(1);
+    test_ptp_msg.ptp_msg.ptp_hdr.sequence_id++;
+    exp_sequence_id++;
+    ptp_msg_ext_buff.buff = &test_ptp_msg;
+    ptp_msg_ext_buff.buff_len = sizeof(test_ptp_msg);
+    n = write(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    TEST_ASSERT_EQUAL(sizeof(test_ptp_msg), n); // write is successful
+    TEST_ASSERT_EQUAL(L2TAP_IREC_INVALID, ts_info->type); // but the TS record is marked invalid
+    // since write was successful, empty L2 TAP queue
+    ptp_msg_ext_buff.buff = in_buffer;
+    ptp_msg_ext_buff.buff_len = IN_BUFFER_SIZE;
+    n = read(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    exp_n = sizeof(test_ptp_msg) < 60 ? 60 : sizeof(test_ptp_msg);
+    TEST_ASSERT_EQUAL(exp_n, n);
+    TEST_ASSERT_EQUAL(exp_sequence_id, ((test_eth_ptp_msg_t *)in_buffer)->ptp_msg.ptp_hdr.sequence_id);
+
+
+    ESP_LOGI(TAG, "Verify response to invalid record len for read (first we need write correctly)");
+    ts_info->type = L2TAP_IREC_TIME_STAMP;
+    ts_info->len = L2TAP_IREC_LEN(sizeof(struct timespec));
+    test_ptp_msg.ptp_msg.ptp_hdr.sequence_id++;
+    exp_sequence_id++;
+    ptp_msg_ext_buff.buff = &test_ptp_msg;
+    ptp_msg_ext_buff.buff_len = sizeof(test_ptp_msg);
+    n = write(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    TEST_ASSERT_EQUAL(sizeof(test_ptp_msg), n);
+    ts_info->type = L2TAP_IREC_TIME_STAMP;
+    ts_info->len = L2TAP_IREC_LEN(1);
+    ptp_msg_ext_buff.buff = in_buffer;
+    ptp_msg_ext_buff.buff_len = IN_BUFFER_SIZE;
+    n = read(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    exp_n = sizeof(test_ptp_msg) < 60 ? 60 : sizeof(test_ptp_msg);
+    TEST_ASSERT_EQUAL(exp_n, n); // read is successful
+    TEST_ASSERT_EQUAL(L2TAP_IREC_INVALID, ts_info->type); // but the TS record is marked invalid
+
+    ESP_LOGI(TAG, "Verify response to Info Record buffer is NULL for write");
+    ts_info->type = L2TAP_IREC_TIME_STAMP;
+    ts_info->len = L2TAP_IREC_LEN(sizeof(struct timespec));
+    ptp_msg_ext_buff.buff = NULL;
+    ptp_msg_ext_buff.buff_len = sizeof(test_ptp_msg);
+    n = write(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    TEST_ASSERT_EQUAL(-1, n);
+    TEST_ASSERT_EQUAL(EFAULT, errno);
+    ESP_LOGI(TAG, "Verify response to Info Record buffer is NULL for read");
+    ts_info->type = L2TAP_IREC_TIME_STAMP;
+    ts_info->len = L2TAP_IREC_LEN(1);
+    ptp_msg_ext_buff.buff = NULL;
+    ptp_msg_ext_buff.buff_len = IN_BUFFER_SIZE;
+    n = read(eth_tap_fd, &ptp_msg_ext_buff, 0);
+    TEST_ASSERT_EQUAL(-1, n);
+    TEST_ASSERT_EQUAL(EFAULT, errno);
+
+    eth_mac_time_t ptp_time = {
+        .seconds = 10,
+        .nanoseconds = 412000
+    };
+    esp_eth_ioctl(eth_network_hndls.eth_handle, ETH_MAC_ESP_CMD_S_PTP_TIME, &ptp_time);
+
+    ESP_LOGI(TAG, "Verify retrieval of Tx and Rx time stamps");
+    for (int i = 0; i < 4; i++) {
+        ts_info->type = L2TAP_IREC_TIME_STAMP;
+        ts_info->len = L2TAP_IREC_LEN(sizeof(struct timespec));
+        test_ptp_msg.ptp_msg.ptp_hdr.sequence_id++;
+        exp_sequence_id++;
+        ptp_msg_ext_buff.buff = &test_ptp_msg;
+        ptp_msg_ext_buff.buff_len = sizeof(test_ptp_msg);
+        n = write(eth_tap_fd, &ptp_msg_ext_buff, 0);
+        TEST_ASSERT_EQUAL(sizeof(test_ptp_msg), n);
+        TEST_ASSERT_EQUAL(L2TAP_IREC_TIME_STAMP, ts_info->type);
+        struct timespec *ts = (struct timespec *)ts_info->data;
+        printf("tap tx TS: %lli.%09li\n", ts->tv_sec, ts->tv_nsec);
+        TEST_ASSERT_NOT_EQUAL(0, ts->tv_sec);
+        TEST_ASSERT_NOT_EQUAL(0, ts->tv_nsec);
+
+        ptp_msg_ext_buff.buff = in_buffer;
+        ptp_msg_ext_buff.buff_len = IN_BUFFER_SIZE;
+        n = read(eth_tap_fd, &ptp_msg_ext_buff, 0);
+        exp_n = sizeof(test_ptp_msg) < 60 ? 60 : sizeof(test_ptp_msg);
+        TEST_ASSERT_EQUAL(exp_n, n);
+        TEST_ASSERT_EQUAL(exp_sequence_id, ((test_eth_ptp_msg_t *)in_buffer)->ptp_msg.ptp_hdr.sequence_id);
+        TEST_ASSERT_EQUAL(exp_n, ptp_msg_ext_buff.buff_len);
+        TEST_ASSERT_EQUAL(L2TAP_IREC_TIME_STAMP, ts_info->type);
+        printf("tap rx TS: %lli.%09li\n", ts->tv_sec, ts->tv_nsec);
+        TEST_ASSERT_NOT_EQUAL(0, ts->tv_sec);
+        TEST_ASSERT_NOT_EQUAL(0, ts->tv_nsec);
+        vTaskDelay(pdMS_TO_TICKS(100));
+    }
+
+    TEST_ASSERT_EQUAL(0, close(eth_tap_fd));
+    TEST_ASSERT_EQUAL(ESP_OK, esp_vfs_l2tap_intf_unregister(NULL));
+    ethernet_deinit(&eth_network_hndls);
+}
+#endif // SOC_EMAC_IEEE1588V2_SUPPORTED
+
 /* ============================================================================= */
 /**
  * @brief Verifies proper functionality of ioctl RCV_FILTER option
@@ -1063,10 +1342,18 @@ TEST_CASE("esp32 l2tap - fcntl", "[ethernet]")
     TEST_ASSERT_EQUAL(0, loop_cnt);
 
     // Try to use unsupported operation
-    int new_fd = fcntl(eth_tap_fd, F_DUPFD, 0);
-    TEST_ASSERT_EQUAL(-1, new_fd);
+    flags = fcntl(eth_tap_fd, F_DUPFD, 0);
+    TEST_ASSERT_EQUAL(-1, flags);
     TEST_ASSERT_EQUAL(ENOSYS, errno);
 
+    // Try to set unsupported flag
+    flags = fcntl(eth_tap_fd, F_SETFL, O_TRUNC);
+    TEST_ASSERT_EQUAL(-1, flags);
+    TEST_ASSERT_EQUAL(EINVAL, errno);
+    flags = fcntl(eth_tap_fd, F_SETFL, O_TRUNC | O_NONBLOCK);
+    TEST_ASSERT_EQUAL(-1, flags);
+    TEST_ASSERT_EQUAL(EINVAL, errno);
+
     TEST_ASSERT_EQUAL(0, close(eth_tap_fd));
 
     vTaskDelay(pdMS_TO_TICKS(50)); // just for sure to give some time to send task close fd
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py b/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py
index 966483b5174..a93a9a9e348 100644
--- a/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py
+++ b/components/esp_netif/test_apps/test_app_vfs_l2tap/pytest_esp_vfs_l2tap.py
@@ -6,5 +6,17 @@
 
 @pytest.mark.esp32
 @pytest.mark.ethernet
+@pytest.mark.parametrize('config', [
+    'defaults',
+], indirect=True)
 def test_esp_netif_vfs_l2tp(dut: Dut) -> None:
     dut.run_all_single_board_cases()
+
+
+@pytest.mark.esp32p4
+@pytest.mark.eth_ip101
+@pytest.mark.parametrize('config', [
+    'defaults',
+], indirect=True)
+def test_esp_netif_vfs_l2tp_p4(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
diff --git a/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.defaults b/components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.defaults
similarity index 100%
rename from components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.defaults
rename to components/esp_netif/test_apps/test_app_vfs_l2tap/sdkconfig.ci.defaults
diff --git a/components/esp_netif/vfs_l2tap/esp_vfs_l2tap.c b/components/esp_netif/vfs_l2tap/esp_vfs_l2tap.c
index 69b1959f41c..e6081e38aee 100644
--- a/components/esp_netif/vfs_l2tap/esp_vfs_l2tap.c
+++ b/components/esp_netif/vfs_l2tap/esp_vfs_l2tap.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,7 @@
 #include <sys/fcntl.h>
 #include <sys/param.h>
 #include <sys/queue.h>
+#include <time.h>
 #include "arpa/inet.h" // for ntohs, etc.
 #include "errno.h"
 
@@ -25,7 +26,6 @@
 #include "freertos/semphr.h"
 #include "freertos/queue.h"
 
-
 #define INVALID_FD          (-1)
 
 #define L2TAP_MAX_FDS       CONFIG_ESP_NETIF_L2_TAP_MAX_FDS
@@ -33,25 +33,35 @@
 
 typedef enum {
     L2TAP_SOCK_STATE_READY,
+    L2TAP_SOCK_STATE_OPENING,
     L2TAP_SOCK_STATE_OPENED,
     L2TAP_SOCK_STATE_CLOSING
 } l2tap_socket_state_t;
 
+typedef enum {
+    L2TAP_FLAG_NON_BLOCK = BIT(0),
+    L2TAP_FLAG_TS        = BIT(1)
+} l2tap_socket_flags_t;
+
 typedef struct {
     _Atomic l2tap_socket_state_t state;
-    bool non_blocking;
+    l2tap_socket_flags_t flags;
     l2tap_iodriver_handle driver_handle;
     uint16_t ethtype_filter;
     QueueHandle_t rx_queue;
-    SemaphoreHandle_t close_done_sem;
 
-    esp_err_t (*driver_transmit)(l2tap_iodriver_handle io_handle, void *buffer, size_t len);
+    SemaphoreHandle_t close_done_sem;
+    union {
+        esp_err_t (*driver_transmit)(l2tap_iodriver_handle io_handle, void *buffer, size_t len);
+        esp_err_t (*driver_transmit_ctrl_vargs)(l2tap_iodriver_handle io_handle, void *ctrl, uint32_t argc, ...);
+    };
     void (*driver_free_rx_buffer)(l2tap_iodriver_handle io_handle, void* buffer);
 } l2tap_context_t;
 
 typedef struct {
     void *buff;
     size_t len;
+    eth_mac_time_t ts;
 } frame_queue_entry_t;
 
 typedef struct {
@@ -87,51 +97,90 @@ static void l2tap_select_notify(int fd, l2tap_select_notif_e select_notif);
 static esp_err_t init_rx_queue(l2tap_context_t *l2tap_socket)
 {
     l2tap_socket->rx_queue = xQueueCreate(RX_QUEUE_MAX_SIZE, sizeof(frame_queue_entry_t));
-    ESP_RETURN_ON_FALSE(l2tap_socket->rx_queue, ESP_ERR_NO_MEM, TAG, "create work queue failed");
+    ESP_RETURN_ON_FALSE(l2tap_socket->rx_queue, ESP_ERR_NO_MEM, TAG, "create Rx queue failed");
     return ESP_OK;
 }
 
-static esp_err_t push_rx_queue(l2tap_context_t *l2tap_socket, void *buff, size_t len)
+static esp_err_t push_rx_queue(l2tap_context_t *l2tap_socket, void *buff, size_t len, eth_mac_time_t *ts)
 {
-    frame_queue_entry_t frame_info;
+    frame_queue_entry_t rx_frame_info;
 
-    frame_info.buff = buff;
-    frame_info.len = len;
+    rx_frame_info.buff = buff;
+    rx_frame_info.len = len;
+    if (ts) {
+        rx_frame_info.ts = *ts;
+    }
     // try send to queue and check if the queue is full
-    if (xQueueSend(l2tap_socket->rx_queue, &frame_info, 0) != pdTRUE) {
+    if (xQueueSend(l2tap_socket->rx_queue, &rx_frame_info, 0) != pdTRUE) {
         return ESP_ERR_NO_MEM;
     }
     return ESP_OK;
 }
 
-static ssize_t pop_rx_queue(l2tap_context_t *l2tap_socket, void *buff, size_t len)
+static esp_err_t pop_rx_queue(l2tap_context_t *l2tap_socket, void *buff, size_t len, ssize_t *copy_len)
 {
+    uint8_t *copy_buff;
     TickType_t timeout = portMAX_DELAY;
-    if (l2tap_socket->non_blocking) {
+    if (l2tap_socket->flags & L2TAP_FLAG_NON_BLOCK) {
         timeout = 0;
     }
+    *copy_len = -1;
 
-    frame_queue_entry_t frame_info;
-    if (xQueueReceive(l2tap_socket->rx_queue, &frame_info, timeout) == pdTRUE) {
+    frame_queue_entry_t rx_frame_info;
+    if (xQueueReceive(l2tap_socket->rx_queue, &rx_frame_info, timeout) == pdTRUE) {
         // empty queue was issued indicating the fd is going to be closed
-        if (frame_info.len == 0) {
+        if (rx_frame_info.len == 0) {
             // indicate to "clean_task" that task waiting for queue was unblocked
-            push_rx_queue(l2tap_socket, NULL, 0);
-            goto err;
+            push_rx_queue(l2tap_socket, NULL, 0, NULL);
+            *copy_len = 0;
+            return ESP_OK;
         }
 
-        if (len > frame_info.len) {
-            len = frame_info.len;
+        // when len == 0, extended buffer is going to be used
+        if (len == 0) {
+            l2tap_extended_buff_t *ext_buff = (l2tap_extended_buff_t *)buff;
+            copy_buff = ext_buff->buff;
+            if (ext_buff->buff_len > rx_frame_info.len) {
+                *copy_len = rx_frame_info.len;
+            } else {
+                *copy_len = ext_buff->buff_len;
+            }
+            ext_buff->buff_len = *copy_len;
+            // check if fd has TS enabled
+            if (l2tap_socket->flags & L2TAP_FLAG_TS) {
+                // find the record allocated for the time stamp info
+                l2tap_irec_hdr_t *info_rec = L2TAP_IREC_FIRST(ext_buff);
+                while(info_rec != NULL) {
+                    if (info_rec->type == L2TAP_IREC_TIME_STAMP) {
+                        break;
+                    }
+                    info_rec = L2TAP_IREC_NEXT(ext_buff, info_rec);
+                }
+                if (info_rec != NULL) {
+                    // check if there is enough space to store TS
+                    if (info_rec->len - sizeof(l2tap_irec_hdr_t) >= sizeof(struct timespec)) {
+                        struct timespec *ts = (struct timespec *)info_rec->data;
+                        ts->tv_sec = rx_frame_info.ts.seconds;
+                        ts->tv_nsec = rx_frame_info.ts.nanoseconds;
+                    } else {
+                        info_rec->type = L2TAP_IREC_INVALID;
+                    }
+                }
+            }
+        } else {
+            copy_buff = buff;
+            if (len > rx_frame_info.len) {
+                *copy_len = rx_frame_info.len;
+            } else {
+                *copy_len = len;
+            }
         }
-        memcpy(buff, frame_info.buff, len);
-        l2tap_socket->driver_free_rx_buffer(l2tap_socket->driver_handle, frame_info.buff);
+        memcpy(copy_buff, rx_frame_info.buff, *copy_len);
+        l2tap_socket->driver_free_rx_buffer(l2tap_socket->driver_handle, rx_frame_info.buff);
     } else {
-        goto err;
+        return ESP_ERR_TIMEOUT;
     }
-
-    return len;
-err:
-    return -1;
+    return ESP_OK;
 }
 
 static bool rx_queue_empty(l2tap_context_t *l2tap_socket)
@@ -141,10 +190,10 @@ static bool rx_queue_empty(l2tap_context_t *l2tap_socket)
 
 static void flush_rx_queue(l2tap_context_t *l2tap_socket)
 {
-    frame_queue_entry_t frame_info;
-    while (xQueueReceive(l2tap_socket->rx_queue, &frame_info, 0) == pdTRUE) {
-        if (frame_info.len > 0) {
-            free(frame_info.buff);
+    frame_queue_entry_t rx_frame_info;
+    while (xQueueReceive(l2tap_socket->rx_queue, &rx_frame_info, 0) == pdTRUE) {
+        if (rx_frame_info.len > 0) {
+            free(rx_frame_info.buff);
         }
     }
 }
@@ -155,12 +204,12 @@ static void delete_rx_queue(l2tap_context_t *l2tap_socket)
     l2tap_socket->rx_queue = NULL;
 }
 
-static inline void l2tap_lock(void)
+static inline void l2tap_enter_critical(void)
 {
     portENTER_CRITICAL(&s_critical_section_lock);
 }
 
-static inline void l2tap_unlock(void)
+static inline void l2tap_exit_critical(void)
 {
     portEXIT_CRITICAL(&s_critical_section_lock);
 }
@@ -171,32 +220,38 @@ static inline void default_free_rx_buffer(l2tap_iodriver_handle io_handle, void*
 }
 
 /* ================== ESP NETIF L2 TAP intf ====================== */
-esp_err_t esp_vfs_l2tap_eth_filter(l2tap_iodriver_handle driver_handle, void *buff, size_t *size)
+esp_err_t esp_vfs_l2tap_eth_filter_frame(l2tap_iodriver_handle driver_handle, void *buff, size_t *size, void *info)
 {
     struct eth_hdr *eth_header = buff;
     uint16_t eth_type = ntohs(eth_header->type);
 
     for (int i = 0; i < L2TAP_MAX_FDS; i++) {
         if (atomic_load(&s_l2tap_sockets[i].state) == L2TAP_SOCK_STATE_OPENED) {
-            l2tap_lock(); // read of socket config needs to be atomic since it can be manipulated from other task
+            l2tap_enter_critical(); // read of socket config needs to be atomic since it can be manipulated from other task
             if (s_l2tap_sockets[i].driver_handle == driver_handle && (s_l2tap_sockets[i].ethtype_filter == eth_type ||
                     // IEEE 802.2 Frame is identified based on its length which is less than IEEE802.3 max length (Ethernet II Types IDs start over this value)
                     // Note that IEEE 802.2 LLC resolution is expected to be performed by upper stream app
                     (s_l2tap_sockets[i].ethtype_filter <= ETH_IEEE802_3_MAX_LEN && eth_type <= ETH_IEEE802_3_MAX_LEN))) {
-                l2tap_unlock();
-                if (push_rx_queue(&s_l2tap_sockets[i], buff, *size) != ESP_OK) {
+                l2tap_exit_critical();
+                eth_mac_time_t *ts;
+                if (s_l2tap_sockets[i].flags & L2TAP_FLAG_TS) {
+                    ts = (eth_mac_time_t *)info;
+                } else {
+                    ts = NULL;
+                }
+                if (push_rx_queue(&s_l2tap_sockets[i], buff, *size, ts) != ESP_OK) {
                     // just tail drop when queue is full
                     s_l2tap_sockets[i].driver_free_rx_buffer(s_l2tap_sockets[i].driver_handle, buff);
                     ESP_LOGD(TAG, "fd %d rx queue is full", i);
                 }
-                l2tap_lock();
+                l2tap_enter_critical();
                 if (s_registered_select_cnt) {
                     l2tap_select_notify(i, L2TAP_SELECT_READ_NOTIF);
                 }
-                l2tap_unlock();
+                l2tap_exit_critical();
                 *size = 0; // the frame is not passed to IP stack when size set to 0
             } else {
-                l2tap_unlock();
+                l2tap_exit_critical();
             }
         }
     }
@@ -212,44 +267,118 @@ static int l2tap_open(const char *path, int flags, int mode)
     for (fd = 0; fd < L2TAP_MAX_FDS; fd++) {
         l2tap_socket_state_t exp_state = L2TAP_SOCK_STATE_READY;
         if (atomic_compare_exchange_strong(&s_l2tap_sockets[fd].state, &exp_state,
-                                           L2TAP_SOCK_STATE_OPENED)) {
+                                           L2TAP_SOCK_STATE_OPENING)) {
             if (init_rx_queue(&s_l2tap_sockets[fd]) != ESP_OK) {
-                atomic_store(&s_l2tap_sockets[fd].state, L2TAP_SOCK_STATE_READY);
                 goto err;
             }
             s_l2tap_sockets[fd].ethtype_filter = 0x0;
+            s_l2tap_sockets[fd].flags = 0;
             s_l2tap_sockets[fd].driver_handle = NULL;
-            s_l2tap_sockets[fd].non_blocking = ((flags & O_NONBLOCK) == O_NONBLOCK);
+            s_l2tap_sockets[fd].flags |= ((flags & O_NONBLOCK) == O_NONBLOCK) ? L2TAP_FLAG_NON_BLOCK : 0;
             s_l2tap_sockets[fd].driver_transmit = esp_eth_transmit;
             s_l2tap_sockets[fd].driver_free_rx_buffer = default_free_rx_buffer;
+            atomic_store(&s_l2tap_sockets[fd].state, L2TAP_SOCK_STATE_OPENED);
             return fd;
         }
     }
 err:
+    if (fd < L2TAP_MAX_FDS) {
+        if (s_l2tap_sockets[fd].rx_queue) {
+            delete_rx_queue(&s_l2tap_sockets[fd]);
+        }
+        atomic_store(&s_l2tap_sockets[fd].state, L2TAP_SOCK_STATE_READY);
+    }
     return INVALID_FD;
 }
 
+static int l2tap_tx_esp_err_to_errno(esp_err_t esp_err)
+{
+    switch(esp_err) {
+        case ESP_ERR_INVALID_ARG:
+            return EINVAL;
+        case ESP_ERR_TIMEOUT:
+            return EBUSY;
+        case ESP_ERR_NO_MEM:
+            return ENOBUFS;
+        case ESP_ERR_INVALID_STATE:
+        // fall through
+        default:
+            return EIO;
+    }
+}
+
 static ssize_t l2tap_write(int fd, const void *data, size_t size)
 {
+    void *eth_buff;
+    l2tap_extended_buff_t *ext_buff;
     ssize_t ret = -1;
+    esp_err_t esp_ret;
+
+    // for certain fd modes, size 0 indicates to use a size from extended buffer header
+    int flags_set = s_l2tap_sockets[fd].flags & L2TAP_FLAG_TS;
+    if ((flags_set && size != 0) || (!flags_set && size == 0)) {
+        if (flags_set) {
+            // Invalid argument
+            errno = EINVAL;
+            return -1;
+        } else {
+            return 0;
+        }
+    }
 
     if (size == 0) {
-        return 0;
+        ext_buff = (l2tap_extended_buff_t *)data;
+        // check if extended buffer holds pointer to valid IO frame buffer
+        if (ext_buff->buff == NULL) {
+            errno = EFAULT;
+            goto err;
+        }
+        eth_buff = ext_buff->buff;
+        size = ext_buff->buff_len;
+    } else {
+        eth_buff = (void *)data;
+        ext_buff = NULL;
     }
 
     if (atomic_load(&s_l2tap_sockets[fd].state) == L2TAP_SOCK_STATE_OPENED) {
         if (s_l2tap_sockets[fd].ethtype_filter > ETH_IEEE802_3_MAX_LEN &&
-                ((struct eth_hdr *)data)->type != htons(s_l2tap_sockets[fd].ethtype_filter)) {
+                ((struct eth_hdr *)eth_buff)->type != htons(s_l2tap_sockets[fd].ethtype_filter)) {
             // bad message
             errno = EBADMSG;
             goto err;
         }
 
-        if (s_l2tap_sockets[fd].driver_transmit(s_l2tap_sockets[fd].driver_handle, (void *)data, size) == ESP_OK) {
-            ret = size;
+        if (s_l2tap_sockets[fd].flags & L2TAP_FLAG_TS) {
+            eth_mac_time_t eth_ts;
+            if ((esp_ret = s_l2tap_sockets[fd].driver_transmit_ctrl_vargs(s_l2tap_sockets[fd].driver_handle, &eth_ts, 2, eth_buff, size)) == ESP_OK){
+                // find the record allocated for the time stamp info
+                l2tap_irec_hdr_t *info_rec = L2TAP_IREC_FIRST(ext_buff);
+                while(info_rec != NULL) {
+                    if (info_rec->type == L2TAP_IREC_TIME_STAMP) {
+                        break;
+                    }
+                    info_rec = L2TAP_IREC_NEXT(ext_buff, info_rec);
+                }
+                // if there is a record to retrieve time stamp
+                if (info_rec != NULL) {
+                    if (info_rec->len - sizeof(l2tap_irec_hdr_t) >= sizeof(struct timespec)) {
+                        struct timespec *ts = (struct timespec *)info_rec->data;
+                        ts->tv_sec = eth_ts.seconds;
+                        ts->tv_nsec = eth_ts.nanoseconds;
+                    } else {
+                        info_rec->type = L2TAP_IREC_INVALID;
+                    }
+                }
+                ret = size;
+            } else {
+                errno = l2tap_tx_esp_err_to_errno(esp_ret);
+            }
         } else {
-            // I/O error
-            errno = EIO;
+            if ((esp_ret = s_l2tap_sockets[fd].driver_transmit(s_l2tap_sockets[fd].driver_handle, eth_buff, size)) == ESP_OK) {
+                ret = size;
+            } else {
+                errno = l2tap_tx_esp_err_to_errno(esp_ret);
+            }
         }
     } else {
         // bad file desc
@@ -259,22 +388,54 @@ static ssize_t l2tap_write(int fd, const void *data, size_t size)
     return ret;
 }
 
+static int l2tap_rx_esp_err_to_errno(esp_err_t esp_err)
+{
+    switch(esp_err) {
+        case ESP_ERR_INVALID_ARG:
+            return EINVAL;
+        case ESP_ERR_TIMEOUT:
+            return EAGAIN;
+        case ESP_ERR_INVALID_STATE:
+            return EPERM;
+        default:
+            return EIO;
+    }
+}
+
 static ssize_t l2tap_read(int fd, void *data, size_t size)
 {
-    // fd might be in process of closing (close was already called but preempted)
+    // fd might be in process of opening/closing (close was already called but preempted)
     if (atomic_load(&s_l2tap_sockets[fd].state) != L2TAP_SOCK_STATE_OPENED) {
         // bad file desc
         errno = EBADF;
         return -1;
     }
 
+    // for certain fd modes, size 0 indicates to use a size from extended buffer header
+    int flags_set = s_l2tap_sockets[fd].flags & L2TAP_FLAG_TS;
+    if ((flags_set && size != 0) || (!flags_set && size == 0)) {
+        if (flags_set) {
+            // Invalid argument
+            errno = EINVAL;
+            return -1;
+        } else {
+            return 0;
+        }
+    }
+
     if (size == 0) {
-        return 0;
+        l2tap_extended_buff_t *ext_buff = (l2tap_extended_buff_t *)data;
+        // check if extended buffer holds pointer to valid IO frame buffer
+        if (ext_buff->buff == NULL) {
+            errno = EFAULT;
+            return -1;
+        }
     }
 
-    ssize_t actual_size = -1;
-    if ((actual_size = pop_rx_queue(&s_l2tap_sockets[fd], data, size)) < 0) {
-        errno = EAGAIN;
+    esp_err_t esp_ret;
+    ssize_t actual_size;
+    if ((esp_ret = pop_rx_queue(&s_l2tap_sockets[fd], data, size, &actual_size)) != ESP_OK) {
+        errno = l2tap_rx_esp_err_to_errno(esp_ret);
     }
 
     return actual_size;
@@ -284,14 +445,17 @@ void l2tap_clean_task(void *task_param)
 {
     l2tap_context_t *l2tap_socket = (l2tap_context_t *)task_param;
 
+    // flush queued frames to not affect "empty queue" signalling below
+    flush_rx_queue(l2tap_socket);
+
     // push empty queue to unblock possibly blocking task
-    push_rx_queue(l2tap_socket, NULL, 0);
+    push_rx_queue(l2tap_socket, NULL, 0, NULL);
     // wait for the indication that blocking task was executed (unblocked)
-    pop_rx_queue(l2tap_socket, NULL, 0);
+    ssize_t actual_size;
+    pop_rx_queue(l2tap_socket, NULL, 0, &actual_size);
 
-    // now, all higher priority tasks should finished their execution and new accesses to the queue were prevended
+    // now, all higher priority tasks should finished their execution and new accesses to the queue were prevented
     // by L2TAP_SOCK_STATE_CLOSING => we are free to free queue resources
-    flush_rx_queue(l2tap_socket);
     delete_rx_queue(l2tap_socket);
 
     // unblock task which originally called close
@@ -343,14 +507,14 @@ static int l2tap_ioctl(int fd, int cmd, va_list args)
 {
     esp_netif_t *esp_netif;
     switch (cmd) {
-    case L2TAP_S_RCV_FILTER: ;
+    case L2TAP_S_RCV_FILTER:{
         uint16_t *new_ethtype_filter = va_arg(args, uint16_t *);
-        l2tap_lock();
+        l2tap_enter_critical();
         // socket needs to be assigned to interface at first
         if (s_l2tap_sockets[fd].driver_handle == NULL) {
             // Permission denied (filter change is denied at this state)
             errno = EACCES;
-            l2tap_unlock();
+            l2tap_exit_critical();
             goto err;
         }
         // do nothing when same filter is to be set
@@ -362,19 +526,21 @@ static int l2tap_ioctl(int fd, int cmd, va_list args)
                         s_l2tap_sockets[i].ethtype_filter == *new_ethtype_filter) {
                     // invalid argument
                     errno = EINVAL;
-                    l2tap_unlock();
+                    l2tap_exit_critical();
                     goto err;
                 }
             }
             s_l2tap_sockets[fd].ethtype_filter = *new_ethtype_filter;
         }
-        l2tap_unlock();
+        l2tap_exit_critical();
         break;
-    case L2TAP_G_RCV_FILTER: ;
+    }
+    case L2TAP_G_RCV_FILTER:{
         uint16_t *ethtype_filter_dest = va_arg(args, uint16_t *);
         *ethtype_filter_dest = s_l2tap_sockets[fd].ethtype_filter;
         break;
-    case L2TAP_S_INTF_DEVICE: ;
+    }
+    case L2TAP_S_INTF_DEVICE:{
         const char *str = va_arg(args, const char *);
         esp_netif = esp_netif_get_handle_from_ifkey(str);
         if (esp_netif == NULL) {
@@ -382,32 +548,42 @@ static int l2tap_ioctl(int fd, int cmd, va_list args)
             errno = ENODEV;
             goto err;
         }
-        l2tap_lock();
+        l2tap_enter_critical();
         s_l2tap_sockets[fd].driver_handle = esp_netif_get_io_driver(esp_netif);
-        l2tap_unlock();
+        l2tap_exit_critical();
         break;
-    case L2TAP_G_INTF_DEVICE: ;
+    }
+    case L2TAP_G_INTF_DEVICE:{
         const char **str_p = va_arg(args, const char **);
         *str_p = NULL;
         if ((esp_netif = esp_netif_find_if(netif_driver_matches, s_l2tap_sockets[fd].driver_handle)) != NULL) {
             *str_p = esp_netif_get_ifkey(esp_netif);
         }
         break;
-    case L2TAP_S_DEVICE_DRV_HNDL: ;
+    }
+    case L2TAP_S_DEVICE_DRV_HNDL:{
         l2tap_iodriver_handle set_driver_hdl = va_arg(args, l2tap_iodriver_handle);
         if (set_driver_hdl == NULL) {
             // No such device (not valid driver handle)
             errno = ENODEV;
             goto err;
         }
-        l2tap_lock();
+        l2tap_enter_critical();
         s_l2tap_sockets[fd].driver_handle = set_driver_hdl;
-        l2tap_unlock();
+        l2tap_exit_critical();
         break;
-    case L2TAP_G_DEVICE_DRV_HNDL: ;
+    }
+    case L2TAP_G_DEVICE_DRV_HNDL:{
         l2tap_iodriver_handle *get_driver_hdl = va_arg(args, l2tap_iodriver_handle*);
         *get_driver_hdl = s_l2tap_sockets[fd].driver_handle;
         break;
+    }
+    case L2TAP_S_TIMESTAMP_EN:
+        l2tap_enter_critical();
+        s_l2tap_sockets[fd].flags |= L2TAP_FLAG_TS;
+        s_l2tap_sockets[fd].driver_transmit_ctrl_vargs = esp_eth_transmit_ctrl_vargs;
+        l2tap_exit_critical();
+        break;
     default:
         // unsupported operation
         errno = ENOSYS;
@@ -421,15 +597,32 @@ static int l2tap_ioctl(int fd, int cmd, va_list args)
     return -1;
 }
 
+static void l2tap_set_nonblocking(l2tap_context_t *l2tap_socket, bool nonblock)
+{
+    l2tap_enter_critical();
+    if (nonblock) {
+        l2tap_socket->flags |= L2TAP_FLAG_NON_BLOCK;
+    } else {
+        l2tap_socket->flags &= ~L2TAP_FLAG_NON_BLOCK;
+    }
+    l2tap_exit_critical();
+}
+
 static int l2tap_fcntl(int fd, int cmd, int arg)
 {
     int result = 0;
     if (cmd == F_GETFL) {
-        if (s_l2tap_sockets[fd].non_blocking) {
+        if (s_l2tap_sockets[fd].flags & L2TAP_FLAG_NON_BLOCK) {
             result |= O_NONBLOCK;
         }
     } else if (cmd == F_SETFL) {
-        s_l2tap_sockets[fd].non_blocking = (arg & O_NONBLOCK) != 0;
+        // only O_NONBLOCK is supported
+        if ((arg & ~O_NONBLOCK) == 0) {
+            l2tap_set_nonblocking(&s_l2tap_sockets[fd], (arg & O_NONBLOCK) == O_NONBLOCK);
+        } else {
+            result = -1;
+            errno = EINVAL;
+        }
     } else {
         // unsupported operation
         result = -1;
@@ -537,7 +730,7 @@ static esp_err_t l2tap_start_select(int nfds, fd_set *readfds, fd_set *writefds,
     FD_ZERO(writefds);
     FD_ZERO(exceptfds);
 
-    l2tap_lock();
+    l2tap_enter_critical();
 
     for (int i = 0; i < max_fds; i++) {
         if (FD_ISSET(i, &args->readfds_orig)) {
@@ -551,12 +744,12 @@ static esp_err_t l2tap_start_select(int nfds, fd_set *readfds, fd_set *writefds,
 
     esp_err_t ret = register_select(args);
     if (ret != ESP_OK) {
-        l2tap_unlock();
+        l2tap_exit_critical();
         free(args);
         return ret;
     }
 
-    l2tap_unlock();
+    l2tap_exit_critical();
 
     *end_select_args = args;
 
@@ -570,9 +763,9 @@ static esp_err_t l2tap_end_select(void *end_select_args)
         return ESP_OK;
     }
 
-    l2tap_lock();
+    l2tap_enter_critical();
     esp_err_t ret = unregister_select(args);
-    l2tap_unlock();
+    l2tap_exit_critical();
 
     if (args) {
         free(args);
diff --git a/components/esp_partition/include/esp_partition.h b/components/esp_partition/include/esp_partition.h
index ea0c42dde13..d53d0cbaac2 100644
--- a/components/esp_partition/include/esp_partition.h
+++ b/components/esp_partition/include/esp_partition.h
@@ -67,6 +67,13 @@ typedef enum {
  * @internal Keep this enum in sync with PartitionDefinition class gen_esp32part.py @endinternal
  */
 typedef enum {
+    ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY = 0x00,                          //!< Primary Bootloader
+    ESP_PARTITION_SUBTYPE_BOOTLOADER_OTA = 0x01,                              //!< Temporary OTA storage for Bootloader, where the OTA uploads a new Bootloader image
+    ESP_PARTITION_SUBTYPE_BOOTLOADER_RECOVERY = 0x02,                         //!< Recovery Bootloader
+
+    ESP_PARTITION_SUBTYPE_PARTITION_TABLE_PRIMARY = 0x00,                     //!< Primary Partition table
+    ESP_PARTITION_SUBTYPE_PARTITION_TABLE_OTA = 0x01,                         //!< Temporary OTA storage for Partition table, where the OTA uploads a new Partition table image
+
     ESP_PARTITION_SUBTYPE_APP_FACTORY = 0x00,                                 //!< Factory application partition
     ESP_PARTITION_SUBTYPE_APP_OTA_MIN = 0x10,                                 //!< Base for OTA partition subtypes
     ESP_PARTITION_SUBTYPE_APP_OTA_0 = ESP_PARTITION_SUBTYPE_APP_OTA_MIN + 0,  //!< OTA partition 0
diff --git a/components/esp_partition/partition.c b/components/esp_partition/partition.c
index d1ab54c0863..b4d17bec4c4 100644
--- a/components/esp_partition/partition.c
+++ b/components/esp_partition/partition.c
@@ -33,6 +33,7 @@
 #include "esp_log.h"
 #include "esp_rom_md5.h"
 #include "bootloader_util.h"
+#include "hal/efuse_hal.h"
 
 #if CONFIG_IDF_TARGET_LINUX
 #include "esp_private/partition_linux.h"
@@ -92,6 +93,10 @@ static bool is_partition_encrypted(bool encryption_config, esp_partition_type_t
             are always encrypted */
         ret_encrypted = true;
     }
+#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    // FE can be enabled in virt eFuses but not in real eFuses.
+    ret_encrypted &= efuse_hal_flash_encryption_enabled();
+#endif
     return ret_encrypted;
 #endif
 }
diff --git a/components/esp_partition/partition_linux.c b/components/esp_partition/partition_linux.c
index c85ac0ced8e..53010027608 100644
--- a/components/esp_partition/partition_linux.c
+++ b/components/esp_partition/partition_linux.c
@@ -67,6 +67,8 @@ const char *esp_partition_type_to_str(const uint32_t type)
     switch (type) {
     case PART_TYPE_APP: return "app";
     case PART_TYPE_DATA: return "data";
+    case PART_TYPE_BOOTLOADER: return "bootloader";
+    case PART_TYPE_PARTITION_TABLE: return "partition_table";
     default: return "unknown";
     }
 }
@@ -74,6 +76,19 @@ const char *esp_partition_type_to_str(const uint32_t type)
 const char *esp_partition_subtype_to_str(const uint32_t type, const uint32_t subtype)
 {
     switch (type) {
+    case PART_TYPE_BOOTLOADER:
+        switch (subtype) {
+        case PART_SUBTYPE_BOOTLOADER_PRIMARY: return "primary";
+        case PART_SUBTYPE_BOOTLOADER_OTA: return "ota";
+        case PART_SUBTYPE_BOOTLOADER_RECOVERY: return "recovery";
+        default: return "unknown";
+        }
+    case PART_TYPE_PARTITION_TABLE:
+        switch (subtype) {
+        case PART_SUBTYPE_PARTITION_TABLE_PRIMARY: return "primary";
+        case PART_SUBTYPE_PARTITION_TABLE_OTA: return "ota";
+        default: return "unknown";
+        }
     case PART_TYPE_APP:
         switch (subtype) {
         case PART_SUBTYPE_FACTORY: return "factory";
diff --git a/components/esp_phy/Kconfig b/components/esp_phy/Kconfig
index c0837398e2a..75b5be45cd4 100644
--- a/components/esp_phy/Kconfig
+++ b/components/esp_phy/Kconfig
@@ -172,5 +172,10 @@ menu "PHY"
             help
                 If enabled, there will be some logs while pll tracking
 
+        config ESP_PHY_RECORD_USED_TIME
+            bool "Record PHY used time"
+            default n
+            help
+                Select to support record and query phy used time.
     endif
 endmenu  # PHY
diff --git a/components/esp_phy/esp32c6/phy_init_data.c b/components/esp_phy/esp32c6/phy_init_data.c
index f60ba8f7e39..499b60d6609 100644
--- a/components/esp_phy/esp32c6/phy_init_data.c
+++ b/components/esp_phy/esp32c6/phy_init_data.c
@@ -13,8 +13,8 @@ const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_M
  * @brief Structure containing default recommended PHY initialization parameters.
  */
 const esp_phy_init_data_t phy_init_data= { {
-        0x01,
-        0x00,
+        0xa,
+        0x0,
         LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54),
         LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54),
         LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
@@ -29,62 +29,62 @@ const esp_phy_init_data_t phy_init_data= { {
         LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C),
         LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C),
         LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48),
+        0x0,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
+        0x00,
         0x00,
         0x00,
         0x00,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0xff,
-        0,
-        0,
         0,
         0,
         0,
@@ -140,7 +140,7 @@ const esp_phy_init_data_t phy_init_data= { {
         0,
         0,
         0,
-        0x70
+        0x51
 } };
 
 const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;
diff --git a/components/esp_phy/include/esp_phy_init.h b/components/esp_phy/include/esp_phy_init.h
index 95756568b48..2e194f707b3 100644
--- a/components/esp_phy/include/esp_phy_init.h
+++ b/components/esp_phy/include/esp_phy_init.h
@@ -38,6 +38,7 @@ typedef enum {
     PHY_MODEM_WIFI       = 1,       /*!< PHY modem WIFI       */
     PHY_MODEM_BT         = 2,       /*!< PHY modem BT         */
     PHY_MODEM_IEEE802154 = 4,       /*!< PHY modem IEEE802154 */
+    PHY_MODEM_MAX,                  /*!< Don't use it. Used by ESP_PHY_MODEM_COUNT_MAX */
 } esp_phy_modem_t;
 
 /**
@@ -286,6 +287,23 @@ void phy_init_param_set(uint8_t param);
  */
 void phy_wifi_enable_set(uint8_t enable);
 
+#if CONFIG_ESP_PHY_RECORD_USED_TIME
+/**
+ * @brief Get phy used time from different modem
+ * @param used_time pointer of variable to get used time, in microseconds
+ * @param modem modem type
+ * @return ESP_ERR_INVALID_ARG on incorrect modem type.
+ */
+esp_err_t phy_query_used_time(uint64_t *used_time, esp_phy_modem_t modem);
+
+/**
+ * @brief Clear phy used time for different modem
+ * @param modem modem type
+ * @return ESP_ERR_INVALID_ARG on incorrect modem type.
+ */
+esp_err_t phy_clear_used_time(esp_phy_modem_t modem);
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_phy/lib b/components/esp_phy/lib
index 6bd4ea98abf..f5f852b53c9 160000
--- a/components/esp_phy/lib
+++ b/components/esp_phy/lib
@@ -1 +1 @@
-Subproject commit 6bd4ea98abf865ee8ee3598f58d7260bf06ff03e
+Subproject commit f5f852b53c90c2a23bfbd6b9c4897c25f0ae6155
diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c
index bc495b30316..86f1cbb5e00 100644
--- a/components/esp_phy/src/phy_init.c
+++ b/components/esp_phy/src/phy_init.c
@@ -161,6 +161,60 @@ static phy_country_to_bin_type_t s_country_code_map_type_table[] = {
     {"US",  ESP_PHY_INIT_DATA_TYPE_FCC},
 };
 #endif
+
+#if CONFIG_ESP_PHY_RECORD_USED_TIME
+#define ESP_PHY_MODEM_COUNT_MAX         (__builtin_ffs(PHY_MODEM_MAX - 1))
+#define ESP_PHY_IS_VALID_MODEM(modem)   (__builtin_popcount(modem) == 1 && __builtin_ctz(modem) < ESP_PHY_MODEM_COUNT_MAX)
+
+static DRAM_ATTR struct {
+    uint64_t used_time;
+    uint64_t enabled_time;
+    uint64_t disabled_time;
+} s_phy_rf_used_info[ESP_PHY_MODEM_COUNT_MAX];
+
+static IRAM_ATTR void phy_record_time(bool enabled, esp_phy_modem_t modem) {
+    uint8_t index = __builtin_ctz(modem);
+    if (enabled) {
+        s_phy_rf_used_info[index].enabled_time = esp_timer_get_time();
+    } else {
+        s_phy_rf_used_info[index].disabled_time = esp_timer_get_time();
+        s_phy_rf_used_info[index].used_time += s_phy_rf_used_info[index].disabled_time - s_phy_rf_used_info[index].enabled_time;
+    }
+}
+
+esp_err_t phy_query_used_time(uint64_t *used_time, esp_phy_modem_t modem) {
+    if (!ESP_PHY_IS_VALID_MODEM(modem)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    uint8_t index = __builtin_ctz(modem);
+    _lock_acquire(&s_phy_access_lock);
+    *used_time = s_phy_rf_used_info[index].used_time;
+    if (s_phy_rf_used_info[index].disabled_time < s_phy_rf_used_info[index].enabled_time) {
+        // phy is being used
+        *used_time += esp_timer_get_time() - s_phy_rf_used_info[index].enabled_time;
+    }
+    _lock_release(&s_phy_access_lock);
+    return ESP_OK;
+}
+
+esp_err_t phy_clear_used_time(esp_phy_modem_t modem) {
+    if (!ESP_PHY_IS_VALID_MODEM(modem)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    uint8_t index = __builtin_ctz(modem);
+    _lock_acquire(&s_phy_access_lock);
+    if (s_phy_rf_used_info[index].enabled_time > s_phy_rf_used_info[index].disabled_time) {
+        // phy is being used
+        s_phy_rf_used_info[index].enabled_time = esp_timer_get_time();
+    } else {
+        s_phy_rf_used_info[index].enabled_time = s_phy_rf_used_info[index].disabled_time;
+    }
+    s_phy_rf_used_info[index].used_time = 0;
+    _lock_release(&s_phy_access_lock);
+    return ESP_OK;
+}
+#endif
+
 uint32_t IRAM_ATTR phy_enter_critical(void)
 {
     if (xPortInIsrContext()) {
@@ -293,13 +347,18 @@ void esp_phy_enable(esp_phy_modem_t modem)
     phy_track_pll();
 #endif
 
+#if CONFIG_ESP_PHY_RECORD_USED_TIME
+    phy_record_time(true, modem);
+#endif
     _lock_release(&s_phy_access_lock);
 }
 
 void esp_phy_disable(esp_phy_modem_t modem)
 {
     _lock_acquire(&s_phy_access_lock);
-
+#if CONFIG_ESP_PHY_RECORD_USED_TIME
+    phy_record_time(false, modem);
+#endif
     phy_clr_modem_flag(modem);
     if (phy_get_modem_flag() == 0) {
 // ESP32 will track pll in the wifi/BT modem interrupt handler.
diff --git a/components/esp_phy/src/phy_init_esp32hxx.c b/components/esp_phy/src/phy_init_esp32hxx.c
index d0d3e2a20b9..9ff88d452fe 100644
--- a/components/esp_phy/src/phy_init_esp32hxx.c
+++ b/components/esp_phy/src/phy_init_esp32hxx.c
@@ -8,6 +8,7 @@
 #include "freertos/portmacro.h"
 #include "esp_phy_init.h"
 #include "esp_private/phy.h"
+#include "esp_timer.h"
 
 #if SOC_MODEM_CLOCK_IS_INDEPENDENT
 #include "esp_private/esp_modem_clock.h"
@@ -23,6 +24,59 @@ static _lock_t s_phy_access_lock;
 /* Reference count of enabling PHY */
 static bool s_phy_is_enabled = false;
 
+#if CONFIG_ESP_PHY_RECORD_USED_TIME
+#define ESP_PHY_MODEM_COUNT_MAX         (__builtin_ffs(PHY_MODEM_MAX - 1))
+#define ESP_PHY_IS_VALID_MODEM(modem)   (__builtin_popcount(modem) == 1 && __builtin_ctz(modem) < ESP_PHY_MODEM_COUNT_MAX)
+
+static DRAM_ATTR struct {
+    uint64_t used_time;
+    uint64_t enabled_time;
+    uint64_t disabled_time;
+} s_phy_rf_used_info[ESP_PHY_MODEM_COUNT_MAX];
+
+static IRAM_ATTR void phy_record_time(bool enabled, esp_phy_modem_t modem) {
+    uint8_t index = __builtin_ctz(modem);
+    if (enabled) {
+        s_phy_rf_used_info[index].enabled_time = esp_timer_get_time();
+    } else {
+        s_phy_rf_used_info[index].disabled_time = esp_timer_get_time();
+        s_phy_rf_used_info[index].used_time += s_phy_rf_used_info[index].disabled_time - s_phy_rf_used_info[index].enabled_time;
+    }
+}
+
+esp_err_t phy_query_used_time(uint64_t *used_time, esp_phy_modem_t modem) {
+    if (!ESP_PHY_IS_VALID_MODEM(modem)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    uint8_t index = __builtin_ctz(modem);
+    _lock_acquire(&s_phy_access_lock);
+    *used_time = s_phy_rf_used_info[index].used_time;
+    if (s_phy_rf_used_info[index].disabled_time < s_phy_rf_used_info[index].enabled_time) {
+        // phy is being used
+        *used_time += esp_timer_get_time() - s_phy_rf_used_info[index].enabled_time;
+    }
+    _lock_release(&s_phy_access_lock);
+    return ESP_OK;
+}
+
+esp_err_t phy_clear_used_time(esp_phy_modem_t modem) {
+    if (!ESP_PHY_IS_VALID_MODEM(modem)) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    uint8_t index = __builtin_ctz(modem);
+    _lock_acquire(&s_phy_access_lock);
+    if (s_phy_rf_used_info[index].enabled_time > s_phy_rf_used_info[index].disabled_time) {
+        // phy is being used
+        s_phy_rf_used_info[index].enabled_time = esp_timer_get_time();
+    } else {
+        s_phy_rf_used_info[index].enabled_time = s_phy_rf_used_info[index].disabled_time;
+    }
+    s_phy_rf_used_info[index].used_time = 0;
+    _lock_release(&s_phy_access_lock);
+    return ESP_OK;
+}
+#endif
+
 uint32_t IRAM_ATTR phy_enter_critical(void)
 {
     if (xPortInIsrContext()) {
@@ -64,13 +118,18 @@ void esp_phy_enable(esp_phy_modem_t modem)
     phy_set_modem_flag(modem);
     // Immediately track pll when phy enabled.
     phy_track_pll();
+#if CONFIG_ESP_PHY_RECORD_USED_TIME
+    phy_record_time(true, modem);
+#endif
     _lock_release(&s_phy_access_lock);
 }
 
 void esp_phy_disable(esp_phy_modem_t modem)
 {
     _lock_acquire(&s_phy_access_lock);
-
+#if CONFIG_ESP_PHY_RECORD_USED_TIME
+    phy_record_time(false, modem);
+#endif
     phy_clr_modem_flag(modem);
     if (phy_get_modem_flag() == 0) {
 
diff --git a/components/esp_pm/linker.lf b/components/esp_pm/linker.lf
index 6fe90c1ff36..a5d95c06b4e 100644
--- a/components/esp_pm/linker.lf
+++ b/components/esp_pm/linker.lf
@@ -34,10 +34,11 @@ entries:
         if SOC_PM_SUPPORT_TOP_PD = y:
             sleep_clock:clock_domain_pd_allowed (noflash)
             sleep_system_peripheral:peripheral_domain_pd_allowed (noflash)
+        if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP = y:
+            sleep_mmu:mmu_domain_pd_allowed (noflash)
         sleep_modem:modem_domain_pd_allowed (noflash)
         sleep_modem:periph_inform_out_light_sleep_overhead (noflash)
-        if IDF_TARGET_ESP32P4 = n && IDF_TARGET_ESP32C61 = n : # TODO: IDF-6496, IDF-9304
-            sar_periph_ctrl:sar_periph_ctrl_power_disable (noflash)
+        sar_periph_ctrl:sar_periph_ctrl_power_disable (noflash)
 
 [mapping:esp_system_pm]
 archive: libesp_system.a
diff --git a/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2 b/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2
index 51f7a5a0451..8345d72b95f 100644
--- a/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2
+++ b/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s2
@@ -1,6 +1,6 @@
 CONFIG_IDF_TARGET="esp32s2"
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y
 CONFIG_SPIRAM_RODATA=y
diff --git a/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3 b/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3
index 31f93b58766..7669b3050c8 100644
--- a/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3
+++ b/components/esp_pm/test_apps/esp_pm/sdkconfig.ci.pm_xip_psram_esp32s3
@@ -1,6 +1,6 @@
 CONFIG_IDF_TARGET="esp32s3"
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
 CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y
 CONFIG_SPIRAM_RODATA=y
diff --git a/components/esp_psram/Kconfig.spiram.common b/components/esp_psram/Kconfig.spiram.common
index cbff587ffc1..2832f1e6778 100644
--- a/components/esp_psram/Kconfig.spiram.common
+++ b/components/esp_psram/Kconfig.spiram.common
@@ -17,16 +17,12 @@ config SPIRAM_IGNORE_NOTFOUND
     help
         Normally, if psram initialization is enabled during compile time but not found at runtime, it
         is seen as an error making the CPU panic. If this is enabled, booting will complete
-        but no PSRAM will be available. If PSRAM failed to initialize, the following configs may be affected
-        and may need to be corrected manually. SPIRAM_TRY_ALLOCATE_WIFI_LWIP will affect some LWIP and WiFi buffer
-        default values and range values. Enable SPIRAM_TRY_ALLOCATE_WIFI_LWIP, ESP_WIFI_AMSDU_TX_ENABLED,
-        ESP_WIFI_CACHE_TX_BUFFER_NUM and use static WiFi Tx buffer may cause potential memory exhaustion issues.
-        Suggest disable SPIRAM_TRY_ALLOCATE_WIFI_LWIP.
-        Suggest disable ESP_WIFI_AMSDU_TX_ENABLED.
-        Suggest disable ESP_WIFI_CACHE_TX_BUFFER_NUM,
-        need clear CONFIG_FEATURE_CACHE_TX_BUF_BIT of config->feature_caps.
-        Suggest change ESP_WIFI_TX_BUFFER from static to dynamic. Also suggest to adjust some buffer numbers to the
-        values used without PSRAM case. Such as, ESP_WIFI_STATIC_TX_BUFFER_NUM, ESP_WIFI_DYNAMIC_TX_BUFFER_NUM.
+        but no PSRAM will be available. In particular, it is important to note that when SPIRAM_IGNORE_NOTFOUND
+        is enabled, some WIFI related configs will be set to the default value used when SPIRAM is disabled.
+        It can be assumed that by enabling this config, WIFI and LWIP will assume that the current chip does not
+        have SPIRAM. SPIRAM_TRY_ALLOCATE_WIFI_LWIP will not work, buffers in WIFI and LWIP will be set to smaller
+        ranges and default values. WIFI_CACHE_TX_BUFFER_NUM and ESP_WIFI_AMSDU_TX_ENABLED will be disabled,
+        ESP_WIFI_TX_BUFFER will be set to ESP_WIFI_DYNAMIC_TX_BUFFER.
 
 choice SPIRAM_USE
     prompt "SPI RAM access method"
diff --git a/components/esp_psram/esp32/Kconfig.spiram b/components/esp_psram/esp32/Kconfig.spiram
index f7eb1725a45..04c32ff5faf 100644
--- a/components/esp_psram/esp32/Kconfig.spiram
+++ b/components/esp_psram/esp32/Kconfig.spiram
@@ -259,19 +259,6 @@ menu "SPI RAM config"
             any himem calls, the reservation is not done and the original amount of memory will be available
             to malloc/esp_heap_alloc_caps.
 
-    config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-        bool "Allow external memory as an argument to xTaskCreateStatic"
-        default n
-        depends on SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC
-        help
-            Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround,
-            normally tasks cannot be safely run with their stack residing in external memory; for this reason
-            xTaskCreate (and related task creaton functions) always allocate stack in internal memory and
-            xTaskCreateStatic will check if the memory passed to it is in internal memory. If you have a task that
-            needs a large amount of stack and does not call on ROM code in any way (no direct calls, but also no
-            Bluetooth/WiFi), you can try enable this to cause xTaskCreateStatic to allow tasks stack in external
-            memory.
-
     choice SPIRAM_OCCUPY_SPI_HOST
         prompt "SPI host to use for 32MBit PSRAM"
         default SPIRAM_OCCUPY_VSPI_HOST
diff --git a/components/esp_psram/esp32c5/Kconfig.spiram b/components/esp_psram/esp32c5/Kconfig.spiram
index 75e0ec8da9d..ca941e8f1d5 100644
--- a/components/esp_psram/esp32c5/Kconfig.spiram
+++ b/components/esp_psram/esp32c5/Kconfig.spiram
@@ -17,16 +17,6 @@ menu "SPI RAM config"
 
     endchoice
 
-    config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-        bool "Allow external memory as an argument to xTaskCreateStatic"
-        default y
-        help
-            Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate
-            are by default allocated from internal RAM.
-
-            This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic.
-            This should only be used for tasks where the stack is never accessed while the cache is disabled.
-
     choice SPIRAM_SPEED
         prompt "Set RAM clock speed"
         default SPIRAM_SPEED_40M
diff --git a/components/esp_psram/esp32c61/Kconfig.spiram b/components/esp_psram/esp32c61/Kconfig.spiram
index 0ef577983fd..fefbd96463c 100644
--- a/components/esp_psram/esp32c61/Kconfig.spiram
+++ b/components/esp_psram/esp32c61/Kconfig.spiram
@@ -17,16 +17,6 @@ menu "SPI RAM config"
 
     endchoice
 
-    config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-        bool "Allow external memory as an argument to xTaskCreateStatic"
-        default y
-        help
-            Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate
-            are by default allocated from internal RAM.
-
-            This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic.
-            This should only be used for tasks where the stack is never accessed while the cache is disabled.
-
     choice SPIRAM_SPEED
         prompt "Set RAM clock speed"
         default SPIRAM_SPEED_40M
diff --git a/components/esp_psram/esp32p4/Kconfig.spiram b/components/esp_psram/esp32p4/Kconfig.spiram
index f17fb795eec..821188d2f3f 100644
--- a/components/esp_psram/esp32p4/Kconfig.spiram
+++ b/components/esp_psram/esp32p4/Kconfig.spiram
@@ -91,17 +91,6 @@ menu "PSRAM config"
 
             If enabled, 1/8 of the PSRAM total size will be reserved for error-correcting code.
 
-    config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-        bool "Allow external memory as an argument to xTaskCreateStatic"
-        default y
-        help
-            Accessing memory in PSRAM has certain restrictions, so task stacks allocated by xTaskCreate
-            are by default allocated from internal RAM.
-
-            This option allows for passing memory allocated from PSRAM to be passed to xTaskCreateStatic.
-            This should only be used for tasks where the stack is never accessed while the L2Cache is
-            disabled, e.g. during SPI Flash operations
-
     source "$IDF_PATH/components/esp_psram/Kconfig.spiram.common"    # insert non-chip-specific items here
 
 endmenu
diff --git a/components/esp_psram/esp32s2/Kconfig.spiram b/components/esp_psram/esp32s2/Kconfig.spiram
index 1af865756aa..6135222a5af 100644
--- a/components/esp_psram/esp32s2/Kconfig.spiram
+++ b/components/esp_psram/esp32s2/Kconfig.spiram
@@ -29,16 +29,6 @@ menu "SPI RAM config"
             bool "ESP-PSRAM64 or LY68L6400"
     endchoice
 
-    config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-        bool "Allow external memory as an argument to xTaskCreateStatic"
-        default y
-        help
-            Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate
-            are by default allocated from internal RAM.
-
-            This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic.
-            This should only be used for tasks where the stack is never accessed while the cache is disabled.
-
     config SPIRAM_CLK_IO
         int
         default 30
diff --git a/components/esp_psram/esp32s3/Kconfig.spiram b/components/esp_psram/esp32s3/Kconfig.spiram
index 46634376297..1bf74912d0c 100644
--- a/components/esp_psram/esp32s3/Kconfig.spiram
+++ b/components/esp_psram/esp32s3/Kconfig.spiram
@@ -38,16 +38,6 @@ menu "SPI RAM config"
             bool "ESP-PSRAM64 , LY68L6400 or APS6408"
     endchoice
 
-    config SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-        bool "Allow external memory as an argument to xTaskCreateStatic"
-        default y
-        help
-            Accessing memory in SPIRAM has certain restrictions, so task stacks allocated by xTaskCreate
-            are by default allocated from internal RAM.
-
-            This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic.
-            This should only be used for tasks where the stack is never accessed while the cache is disabled.
-
     config SPIRAM_CLK_IO
         int
         default 30
diff --git a/components/esp_psram/esp_psram.c b/components/esp_psram/esp_psram.c
index 59176e7c74e..80a9cdeb5f4 100644
--- a/components/esp_psram/esp_psram.c
+++ b/components/esp_psram/esp_psram.c
@@ -325,6 +325,7 @@ static void s_psram_mapping(uint32_t psram_available_size, uint32_t start_page)
 
 #if CONFIG_IDF_TARGET_ESP32
     s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].size -= esp_himem_reserved_area_size() - 1;
+    s_psram_ctx.regions_to_heap[PSRAM_MEM_8BIT_ALIGNED].vaddr_end -= esp_himem_reserved_area_size();
 #endif
 }
 
diff --git a/components/esp_psram/test_apps/.build-test-rules.yml b/components/esp_psram/test_apps/.build-test-rules.yml
index 88e27087346..c9b865f3012 100644
--- a/components/esp_psram/test_apps/.build-test-rules.yml
+++ b/components/esp_psram/test_apps/.build-test-rules.yml
@@ -9,11 +9,3 @@ components/esp_psram/test_apps/psram:
     - esp_driver_gpio
     - esp_driver_spi
     - spi_flash
-
-
-components/esp_psram/test_apps/psram_no_malloc_task_stack:
-  enable:
-    - if: IDF_TARGET in ["esp32", "esp32p4"]
-  depends_components:
-    - esp_psram
-    - freertos
diff --git a/components/esp_psram/test_apps/psram/main/test_himem.c b/components/esp_psram/test_apps/psram/main/test_himem.c
index cfb4372d201..7e048c3af34 100644
--- a/components/esp_psram/test_apps/psram/main/test_himem.c
+++ b/components/esp_psram/test_apps/psram/main/test_himem.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,7 @@
 #include <stdio.h>
 #include <stdbool.h>
 #include <stdint.h>
+#include <string.h>
 #include "inttypes.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
@@ -106,6 +107,60 @@ TEST_CASE("high psram memory test", "[himem]")
     vTaskDelay(100);
 }
 
+#define CACHE_BLOCKSIZE     (32*1024)
+#define ALLOCATIONS_SIZE    (CACHE_BLOCKSIZE / 2)
+#define MAX_ALLOCATIONS     ((4*1024*1024) / ALLOCATIONS_SIZE)
+
+TEST_CASE("psram heap doesn't affect himem", "[himem]")
+{
+    esp_himem_handle_t mh;
+    esp_himem_rangehandle_t rh;
+    uint32_t *ptr = NULL;
+    /* Array containing all the areas from the heap */
+    void* allocs[MAX_ALLOCATIONS] = { 0 };
+    int allocs_idx = 0;
+
+    /* Allocate a physical block from the PSRAM */
+    ESP_ERROR_CHECK(esp_himem_alloc(CACHE_BLOCKSIZE, &mh));
+    /* Allocate a range of virtual memory where we can map the allocated block */
+    ESP_ERROR_CHECK(esp_himem_alloc_map_range(ESP_HIMEM_BLKSZ, &rh));
+    /* Map that physical block in the allocated virtual memory */
+    ESP_ERROR_CHECK(esp_himem_map(mh, rh, 0, 0, ESP_HIMEM_BLKSZ, 0, (void**)&ptr));
+    /* Memset that part of the memory with an arbitrary pattern */
+    memset(ptr, 0x42, CACHE_BLOCKSIZE);
+
+    /* Allocate heap memory in PSRAM until there is no more memory */
+    while (1) {
+        uint8_t* data = heap_caps_malloc(ALLOCATIONS_SIZE, MALLOC_CAP_SPIRAM);
+        /* If the allocation failed, there is no more memory, we can break */
+        if (data == NULL) {
+            break;
+        }
+        assert(allocs_idx < MAX_ALLOCATIONS);
+        allocs[allocs_idx++] = data;
+        /* Set the allocated memory to another pattern */
+        memset(data, 0xAB, ALLOCATIONS_SIZE);
+    }
+
+    /* Make sure we allocated more than 127 blocks */
+    printf("Allocated %d blocks\n", allocs_idx);
+    TEST_ASSERT_GREATER_THAN_INT(127, allocs_idx);
+
+    /* Check if the himem block has been altered by the heap */
+    TEST_ASSERT_EACH_EQUAL_INT8(0x42, ptr, CACHE_BLOCKSIZE);
+
+    /* Free all the allocated memories */
+    for (int i = 0; i < allocs_idx; i++) {
+        heap_caps_free(allocs[i]);
+    }
+
+    ESP_ERROR_CHECK(esp_himem_unmap(rh, ptr, ESP_HIMEM_BLKSZ));
+    ESP_ERROR_CHECK(esp_himem_free(mh));
+    ESP_ERROR_CHECK(esp_himem_free_map_range(rh));
+
+    printf("Success!\n");
+}
+
 #endif
 
 #endif // CONFIG_IDF_TARGET_ESP32
diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/CMakeLists.txt b/components/esp_psram/test_apps/psram_no_malloc_task_stack/CMakeLists.txt
deleted file mode 100644
index 9debb1681bd..00000000000
--- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# The following five lines of boilerplate have to be in your project's
-# CMakeLists in this exact order for cmake to work correctly
-cmake_minimum_required(VERSION 3.16)
-
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-set(COMPONENTS main)
-project(psram_no_malloc_task_stack)
diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/README.md b/components/esp_psram/test_apps/psram_no_malloc_task_stack/README.md
deleted file mode 100644
index 4873c15b15b..00000000000
--- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/README.md
+++ /dev/null
@@ -1,2 +0,0 @@
-| Supported Targets | ESP32 | ESP32-P4 |
-| ----------------- | ----- | -------- |
diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/CMakeLists.txt b/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/CMakeLists.txt
deleted file mode 100644
index 90939ebf279..00000000000
--- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/CMakeLists.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-idf_component_register(SRCS "test_psram_no_malloc_task_stack.c"
-                       INCLUDE_DIRS "."
-                       PRIV_REQUIRES unity esp_psram freertos heap)
diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/test_psram_no_malloc_task_stack.c b/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/test_psram_no_malloc_task_stack.c
deleted file mode 100644
index d0c48c608d2..00000000000
--- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/main/test_psram_no_malloc_task_stack.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Unlicense OR CC0-1.0
- */
-#include <stdio.h>
-#include "esp_log.h"
-#include "unity.h"
-#include "unity_test_runner.h"
-#include "unity_test_utils_memory.h"
-#include "unity_test_utils.h"
-#include "esp_heap_caps.h"
-#include "esp_memory_utils.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-
-static const char* TAG = "psram_no_malloc_task_stack_test";
-
-#define STACK_SIZE 4096
-#define WAIT_TICKS 2
-#define TEST_TASK_PRIORITY 6 // relatively high priority to let task finish quickly
-
-void setUp(void)
-{
-    unity_utils_set_leak_level(0);
-    unity_utils_record_free_mem();
-}
-
-void tearDown(void)
-{
-    unity_utils_evaluate_leaks();
-}
-
-static uint8_t *stack_memory;
-static StaticTask_t *tcb_memory;
-static bool is_external;
-static SemaphoreHandle_t task_waiter;
-
-static void test_task(void *arg)
-{
-    int dummy = 47;
-    is_external = esp_ptr_external_ram(&dummy);
-    xSemaphoreGive(task_waiter);
-    vTaskDelay(portMAX_DELAY);
-}
-
-TEST_CASE("FreeRTOS task with stack on SPIRAM works", "[psram]")
-{
-    stack_memory = heap_caps_malloc(STACK_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM);
-    TEST_ASSERT_NOT_NULL(stack_memory);
-    tcb_memory = heap_caps_malloc(sizeof(StaticTask_t), MALLOC_CAP_8BIT);
-    TEST_ASSERT_NOT_NULL(tcb_memory);
-    task_waiter = xSemaphoreCreateBinary();
-    TEST_ASSERT_NOT_NULL(task_waiter);
-
-    TaskHandle_t task = xTaskCreateStatic(test_task,
-                                          "heap caps static",
-                                          STACK_SIZE,
-                                          NULL,
-                                          TEST_TASK_PRIORITY,
-                                          stack_memory,
-                                          tcb_memory);
-    TEST_ASSERT_NOT_NULL(task);
-
-    TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(task_waiter, WAIT_TICKS));
-
-    TEST_ASSERT_EQUAL(true, is_external);
-
-    // use unity_utils_task_delete() to avoid deleting stack of a still running task
-    unity_utils_task_delete(task);
-
-    vSemaphoreDelete(task_waiter);
-    heap_caps_free(tcb_memory);
-    heap_caps_free(stack_memory);
-}
-
-void app_main(void)
-{
-    ESP_LOGI(TAG, "Running PSRAM task stack test app with SPIRAM_USE_CAPS_ALLOC");
-
-    unity_run_menu();
-}
diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/pytest_psram_no_malloc_task_stack.py b/components/esp_psram/test_apps/psram_no_malloc_task_stack/pytest_psram_no_malloc_task_stack.py
deleted file mode 100644
index 298f6f93c87..00000000000
--- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/pytest_psram_no_malloc_task_stack.py
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
-# SPDX-License-Identifier: CC0-1.0
-import pytest
-from pytest_embedded import Dut
-
-
-@pytest.mark.esp32
-@pytest.mark.esp32p4
-@pytest.mark.generic
-def test_psram_no_malloc_task_stack(dut: Dut) -> None:
-    dut.run_all_single_board_cases()
diff --git a/components/esp_psram/test_apps/psram_no_malloc_task_stack/sdkconfig.defaults b/components/esp_psram/test_apps/psram_no_malloc_task_stack/sdkconfig.defaults
deleted file mode 100644
index 5e67e04b0c4..00000000000
--- a/components/esp_psram/test_apps/psram_no_malloc_task_stack/sdkconfig.defaults
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_ESP_TASK_WDT_EN=n
-CONFIG_SPIRAM=y
-CONFIG_SPIRAM_USE_CAPS_ALLOC=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index e344d4dffcf..a2a86ed786d 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -99,6 +99,11 @@ if(target STREQUAL "linux")
 else()
     target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld")
     rom_linker_script("api")
+    if(NOT CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+        if(target STREQUAL "esp32s3" OR target STREQUAL "esp32c3")
+            rom_linker_script("bt_funcs")
+        endif()
+    endif()
 
     if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB)
         rom_linker_script("libgcc")
@@ -176,15 +181,67 @@ else() # Regular app build
         endif()
 
     elseif(target STREQUAL "esp32c3")
+        if(CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+            if(NOT CONFIG_BT_CTRL_BLE_MASTER)
+                rom_linker_script("ble_master")
+            endif()
+            if(NOT CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT AND NOT CONFIG_BT_BLE_50_FEATURES_SUPPORTED)
+                rom_linker_script("ble_50")
+            endif()
+            if(CONFIG_BT_BLE_CCA_MODE_NONE)
+                rom_linker_script("ble_cca")
+            endif()
+            if(NOT CONFIG_BT_NIMBLE_SECURITY_ENABLE AND NOT CONFIG_BT_BLE_SMP_ENABLE)
+                rom_linker_script("ble_smp")
+            endif()
+            if(NOT CONFIG_BT_CTRL_DTM_ENABLE)
+                rom_linker_script("ble_dtm")
+            endif()
+            if(NOT CONFIG_BT_CTRL_BLE_TEST)
+                rom_linker_script("ble_test")
+            endif()
+            if(NOT CONFIG_BT_CTRL_BLE_SCAN)
+                rom_linker_script("ble_scan")
+            endif()
+        endif()
 
         if(CONFIG_ESP32C3_REV_MIN_FULL GREATER_EQUAL 3)
             rom_linker_script("eco3")
+            if(NOT CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+                rom_linker_script("eco3_bt_funcs")
+            endif()
         endif()
 
         if(CONFIG_ESP32C3_REV_MIN_FULL GREATER_EQUAL 101)
             rom_linker_script("eco7")
+            if(NOT CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+                rom_linker_script("eco7_bt_funcs")
+            endif()
+        endif()
+    elseif(target STREQUAL "esp32s3")
+        if(CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
+            if(NOT CONFIG_BT_CTRL_BLE_MASTER)
+                rom_linker_script("ble_master")
+            endif()
+            if(NOT CONFIG_BT_NIMBLE_50_FEATURE_SUPPORT AND NOT CONFIG_BT_BLE_50_FEATURES_SUPPORTED)
+                rom_linker_script("ble_50")
+            endif()
+            if(CONFIG_BT_BLE_CCA_MODE_NONE)
+                rom_linker_script("ble_cca")
+            endif()
+            if(NOT CONFIG_BT_NIMBLE_SECURITY_ENABLE AND NOT CONFIG_BT_BLE_SMP_ENABLE)
+                rom_linker_script("ble_smp")
+            endif()
+            if(NOT CONFIG_BT_CTRL_DTM_ENABLE)
+                rom_linker_script("ble_dtm")
+            endif()
+            if(NOT CONFIG_BT_CTRL_BLE_TEST)
+                rom_linker_script("ble_test")
+            endif()
+            if(NOT CONFIG_BT_CTRL_BLE_SCAN)
+                rom_linker_script("ble_scan")
+            endif()
         endif()
-
     elseif(target STREQUAL "esp32c6")
         # esp32c6.rom.api.ld has been split to several lds by components.
         # esp32c6.rom.api.ld is still reserved to map the APIs
diff --git a/components/esp_rom/esp32/include/esp32/rom/cache.h b/components/esp_rom/esp32/include/esp32/rom/cache.h
index 5b56d7e046a..d9017615e6d 100644
--- a/components/esp_rom/esp32/include/esp32/rom/cache.h
+++ b/components/esp_rom/esp32/include/esp32/rom/cache.h
@@ -44,7 +44,7 @@ void mmu_init(int cpu_no);
   *
   * @param  int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
   *
-  * @param  int pod : process identifier. Range 0~7.
+  * @param  int pid : process identifier. Range 0~7.
   *
   * @param  unsigned int vaddr : virtual address in CPU address space.
   *                              Can be IRam0, IRam1, IRom0 and DRom0 memory address.
@@ -87,7 +87,7 @@ static inline __attribute__((always_inline)) unsigned int IRAM_ATTR cache_flash_
   *
   * @param  int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
   *
-  * @param  int pod : process identifier. Range 0~7.
+  * @param  int pid : process identifier. Range 0~7.
   *
   * @param  unsigned int vaddr : virtual address in CPU address space.
   *                              Can be IRam0, IRam1, IRom0 and DRom0 memory address.
diff --git a/components/esp_rom/esp32/ld/esp32.rom.ld b/components/esp_rom/esp32/ld/esp32.rom.ld
index b47c3140b89..c6abfb4559b 100644
--- a/components/esp_rom/esp32/ld/esp32.rom.ld
+++ b/components/esp_rom/esp32/ld/esp32.rom.ld
@@ -663,6 +663,7 @@ PROVIDE ( ld_acl_rsw_frm_cbk = 0x40033bb0 );
 PROVIDE ( ld_sco_modify = 0x40031778 );
 PROVIDE ( lm_cmd_cmp_send = 0x40051838 );
 PROVIDE ( ld_sco_frm_cbk = 0x400349dc );
+PROVIDE ( ld_sco_evt_stop_cbk = 0x40031d78 );
 PROVIDE ( ld_acl_sco_rsvd_check = 0x4002fa94 );
 PROVIDE ( ld_acl_sniff_frm_cbk = 0x4003482c );
 PROVIDE ( ld_inq_end = 0x4003ab48 );
@@ -1368,6 +1369,7 @@ PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 );
 PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );
 PROVIDE ( SPI_write_enable = 0x40062320 );
 PROVIDE ( hci_le_rd_rem_used_feats_cmd_handler = 0x400417b4 );
+PROVIDE ( hci_per_inq_mode_cmd_handler = 0x400519b0 );
 PROVIDE ( llcp_length_req_handler = 0x40043808 );
 PROVIDE ( llcp_unknown_rsp_handler = 0x40043ba8 );
 PROVIDE ( llcp_channel_map_req_handler = 0x4004291c );
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
index 22130d601e4..4f35bfd10b8 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.eco4.ld
@@ -1194,14 +1194,14 @@ ieee80211_output_process = 0x40001fc4;
 sta_input = 0x40001fcc;
 ieee80211_classify = 0x40001fe0;
 ieee80211_crypto_decap = 0x40001ff8;
-ieee80211_ccmp_decrypt = 0x4000200c;
-ieee80211_ccmp_encrypt = 0x40002010;
+//ieee80211_ccmp_decrypt = 0x4000200c;
+//ieee80211_ccmp_encrypt = 0x40002010;
 //ieee80211_send_action_vendor_spec = 0x40002034;
 ieee80211_send_mgmt = 0x40002038;
 //ieee80211_auth_construct = 0x4000203c;
 ieee80211_deauth_construct = 0x40002040;
 ieee80211_disassoc_construct = 0x40002044;
-ieee80211_add_xrates = 0x40002058;
+//ieee80211_add_xrates = 0x40002058;
 //ieee80211_assoc_req_construct = 0x40002060;
 ieee80211_assoc_resp_construct = 0x40002064;
 ieee80211_timer_process = 0x4000208c;
@@ -1214,7 +1214,7 @@ cnx_coexist_timeout_process = 0x400020ac;
 ieee80211_add_extcap = 0x400020cc;
 //ieee80211_alloc_proberesp = 0x400020d8;
 esp_wifi_80211_tx = 0x400020f8;
-ieee80211_crypto_aes_128_cmac_decrypt = 0x40002104;
+/* ieee80211_crypto_aes_128_cmac_decrypt = 0x40002104; */
 ieee80211_output_do = 0x4000210c;
 ieee80211_send_nulldata = 0x40002110;
 //ieee80211_setup_robust_mgmtframe = 0x40002114;
@@ -1222,11 +1222,11 @@ ieee80211_send_nulldata = 0x40002110;
 ieee80211_send_deauth = 0x40002120;
 //ieee80211_tx_mgt_cb = 0x4000212c;
 sta_rx_csa = 0x40002134;
-sta_send_sa_query_req = 0x40002138;
+/*sta_send_sa_query_req = 0x40002138;
 sta_send_sa_query_resp = 0x4000213c;
 sta_recv_sa_query_req = 0x40002140;
-sta_recv_sa_query_resp = 0x40002144;
-ieee80211_parse_beacon = 0x40002148;
+sta_recv_sa_query_resp = 0x40002144;*/
+//ieee80211_parse_beacon = 0x40002148;
 ieee80211_match_security = 0x40002154;
 //ieee80211_parse_rsn = 0x4000215c;
 /* Data (.data, .bss, .rodata) */
diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
index 5aad6135888..3dbbb8aacd1 100644
--- a/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
+++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.ld
@@ -361,8 +361,8 @@ ets_get_xtal_freq = 0x40000784;
 gpio_input_get = 0x40000788;
 gpio_matrix_in = 0x4000078c;
 gpio_matrix_out = 0x40000790;
-gpio_output_disable = 0x40000794;
-gpio_output_enable = 0x40000798;
+/* gpio_output_disable = 0x40000794; */
+/* gpio_output_enable = 0x40000798; */
 gpio_output_set = 0x4000079c;
 gpio_pad_hold = 0x400007a0;
 gpio_pad_input_disable = 0x400007a4;
@@ -1623,7 +1623,7 @@ dbg_lmac_rxtx_statis_dump = 0x40001e90;
 dbg_lmac_hw_statis_dump = 0x40001e94;
 dbg_lmac_diag_statis_dump = 0x40001e98;
 dbg_lmac_ps_statis_dump = 0x40001e9c;
-pp_timer_do_process = 0x40001ea0;
+/*pp_timer_do_process = 0x40001ea0;*/
 rcUpdateAMPDUParam = 0x40001ea4;
 rcUpdatePhyMode = 0x40001ea8;
 rcGetHighestRateIdx = 0x40001eac;
@@ -1834,7 +1834,7 @@ ieee80211_amsdu_length_check = 0x400020ec;
 ieee80211_encap_amsdu = 0x400020f0;
 ieee80211_output_raw_process = 0x400020f4;
 ieee80211_raw_frame_sanity_check = 0x400020fc;
-ieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;
+//ieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;
 ieee80211_alloc_tx_buf = 0x40002108;
 /* ieee80211_output_do = 0x4000210c; */
 /* ieee80211_send_nulldata = 0x40002110; */
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_50.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_50.ld
new file mode 100644
index 00000000000..cf9e0c3e127
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_50.ld
@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c3.rom.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* extend adv */
+f_hci_le_set_ext_adv_param_cmd_handler = 0;
+f_hci_le_set_adv_set_rand_addr_cmd_handler = 0;
+f_hci_le_set_ext_adv_data_cmd_handler = 0;
+f_hci_le_set_ext_scan_rsp_data_cmd_handler = 0;
+f_hci_le_set_ext_adv_en_cmd_handler = 0;
+f_hci_le_rd_max_adv_data_len_cmd_handler = 0;
+f_hci_le_rd_nb_supp_adv_sets_cmd_handler = 0;
+f_hci_le_rmv_adv_set_cmd_handler = 0;
+f_hci_le_clear_adv_sets_cmd_handler = 0;
+r_lld_adv_sync_info_set = 0;
+
+r_lld_ext_adv_dynamic_pti_process = 0;
+r_lld_adv_ext_chain_construct = 0;
+r_lld_adv_aux_evt_canceled_cbk = 0;
+r_lld_adv_aux_evt_start_cbk = 0;
+r_lld_adv_aux_ch_idx_set = 0;
+
+/* periodic adv */
+f_hci_le_set_per_adv_param_cmd_handler = 0;
+f_hci_le_set_per_adv_data_cmd_handler = 0;
+f_hci_le_set_per_adv_en_cmd_handler = 0;
+r_lld_per_adv_ch_map_update = 0;
+r_lld_per_adv_init = 0;
+
+/* PA list */
+f_hci_le_add_dev_to_per_adv_list_cmd_handler = 0;
+f_hci_le_rmv_dev_from_per_adv_list_cmd_handler = 0;
+f_hci_le_clear_per_adv_list_cmd_handler = 0;
+f_hci_le_rd_per_adv_list_size_cmd_handler = 0;
+
+/* extend scan */
+f_hci_le_set_ext_scan_param_cmd_handler = 0;
+f_hci_le_set_ext_scan_en_cmd_handler = 0;
+r_lld_scan_process_pkt_rx_ext_adv = 0;
+r_lld_scan_trunc_ind = 0;
+
+/* extend con */
+f_hci_le_ext_create_con_cmd_handler = 0;
+r_lld_init_process_pkt_rx_adv_ext_ind = 0;
+r_lld_init_process_pkt_rx_aux_connect_rsp = 0;
+
+/* PA sync */
+f_hci_le_per_adv_create_sync_cmd_handler = 0;
+f_hci_le_per_adv_create_sync_cancel_cmd_handler = 0;
+f_hci_le_per_adv_term_sync_cmd_handler = 0;
+f_lld_per_adv_rx_end_ind_handler_hack = 0;
+f_lld_sync_start_req_handler = 0;
+f_lld_per_adv_rep_ind_handler = 0;
+r_lld_sync_init = 0;
+
+/* phy update*/
+r_phy_upd_proc_start = 0;
+f_llc_op_phy_upd_ind_handler = 0;
+f_ll_phy_req_handler = 0;
+f_ll_phy_rsp_handler = 0;
+f_ll_phy_update_ind_handler = 0;
+f_lld_phy_upd_cfm_handler = 0;
+f_hci_le_set_phy_cmd_handler = 0;
+llc_llcp_phy_update_ind_ack = 0;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_cca.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_cca.ld
new file mode 100644
index 00000000000..3bb14764722
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_cca.ld
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c3.rom.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* SW CCA */
+r_lld_cca_con_evt_start_handle = 0;
+r_lld_hw_cca_end_isr = 0;
+r_lld_hw_cca_isr_eco = 0;
+r_lld_cca_bb_sync_found_handle = 0;
+r_lld_cca_data_reset = 0;
+r_lld_cca_sw_init = 0;
+r_lld_cca_con_evt_end_handle  = 0;
+r_lld_cca_alloc = 0;
+r_lld_cca_sw_alloc = 0;
+r_lld_cca_sw_free = 0;
+r_lld_cca_free = 0;
+r_cca_init = 0;
+r_lld_hw_cca_evt_handler = 0;
+r_lld_sw_cca_evt_handler = 0;
+r_ble_sw_cca_check_isr = 0;
+bt_bb_tx_cca_set = 0;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_dtm.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_dtm.ld
new file mode 100644
index 00000000000..aeede90250d
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_dtm.ld
@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c3.rom.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* DTM */
+f_hci_le_rx_test_cmd_handler = 0;
+f_hci_le_tx_test_cmd_handler = 0;
+f_hci_le_enh_rx_test_cmd_handler = 0;
+f_hci_le_enh_tx_test_cmd_handler = 0;
+f_hci_le_test_end_cmd_handler = 0;
+r_lld_test_init = 0;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_master.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_master.ld
new file mode 100644
index 00000000000..e7d2db0cbff
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_master.ld
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c3.rom.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* master */
+f_hci_le_create_con_cmd_handler = 0;
+f_hci_le_create_con_cancel_cmd_handler = 0;
+lld_init_end_ind_handler = 0;
+r_lld_init_init = 0;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_scan.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_scan.ld
new file mode 100644
index 00000000000..eda6c721a1b
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_scan.ld
@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c3.rom.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+
+/* BLE scan */
+f_hci_le_set_scan_param_cmd_handler = 0;
+f_hci_le_set_scan_en_cmd_handler = 0;
+f_llm_scan_period_to_handler_hack = 0;
+f_lld_adv_rep_ind_handler_hack = 0;
+r_lld_scan_init = 0;
+r_lld_scan_restart = 0;
+f_lld_scan_end_ind_handler_hack = 0;
+r_llm_env_adv_dup_filt_deinit_eco = 0;
+llm_exception_list_init = 0;
+llm_duplicate_list_init = 0;
+f_hci_vendor_ble_update_duplicate_exceptional_list_cmd_handler = 0;
+f_hci_vendor_ble_init_adv_flow_control_cmd_handler = 0;
+f_hci_vendor_ble_update_adv_report_flow_control_cmd_handler = 0;
+coex_schm_ble_scan_stop = 0;
+
+f_hci_le_set_ext_scan_param_cmd_handler = 0;
+f_hci_le_set_ext_scan_en_cmd_handler = 0;
+r_lld_scan_process_pkt_rx_ext_adv = 0;
+r_lld_scan_trunc_ind = 0;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_smp.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_smp.ld
new file mode 100644
index 00000000000..15436088d77
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_smp.ld
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c3.rom.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* SMP */
+f_ll_pause_enc_req_handler = 0;
+f_ll_pause_enc_rsp_handler = 0;
+f_ll_enc_req_handler = 0;
+f_ll_enc_rsp_handler = 0;
+f_ll_start_enc_req_handler = 0;
+f_ll_start_enc_rsp_handler = 0;
+f_hci_le_start_enc_cmd_handler = 0;
+f_hci_le_ltk_req_reply_cmd_handler = 0;
+f_hci_le_ltk_req_neg_reply_cmd_handler = 0;
+f_llc_encrypt_ind_handler = 0;
+f_llc_op_encrypt_ind_handler = 0;
+f_hci_le_rd_local_p256_public_key_cmd_handler = 0;
+f_hci_le_generate_dhkey_cmd_handler = 0;
+f_hci_le_enc_cmd_handler = 0;
+r_rwip_crypt_evt_handler = 0;
+
+/* LE ping */
+f_ll_ping_req_handler = 0;
+f_ll_ping_rsp_handler = 0;
+r_llc_le_ping_set = 0;
+r_llc_le_ping_restart = 0;
+f_llc_op_le_ping_ind_handler = 0;
+f_llc_auth_payl_nearly_op_handler = 0;
+f_llc_auth_payl_real_to_handler = 0;
+f_llc_auth_payl_nearly_to_handler = 0;
+
+/* ecc */
+r_ecc_init = 0;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_test.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_test.ld
new file mode 100644
index 00000000000..0c821cf5ba8
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ble_test.ld
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c3.rom.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+
+/* overwrite */
+lld_acl_rx_ind_handler = 0;
+lld_con_estab_ind_handler = 0;
+lld_adv_rep_ind_handler = 0;
+llm_rpa_renew_to_handler = 0;
+lld_scan_end_ind_handler = 0;
+llm_scan_period_to_handler = 0;
+
+/* nvds */
+r_nvds_init = 0;
+f_nvds_get = 0;
+f_nvds_del = 0;
+f_nvds_put = 0;
+
+/* controller flash */
+r_flash_init = 0;
+r_flash_env_init = 0;
+r_flash_env_deinit = 0;
+
+/* QA test */
+f_hci_vendor_ble_qa_test_cmd_handler = 0;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.bt_funcs.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.bt_funcs.ld
new file mode 100644
index 00000000000..89ea7c532ce
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.bt_funcs.ld
@@ -0,0 +1,844 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32c3.rom.ld for esp32c3
+ *
+ *
+ * Generated from ./interface-esp32c3.yml md5sum 93b28a9e1fe42d212018eb4336849208
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group bluetooth
+ ***************************************/
+
+/* Functions */
+bt_rf_coex_get_dft_cfg = 0x400008dc;
+bt_rf_coex_hooks_p_set = 0x400008e0;
+btdm_con_maxevtime_cal_impl = 0x400008e4;
+btdm_controller_get_compile_version_impl = 0x400008e8;
+btdm_controller_rom_data_init = 0x400008ec;
+btdm_dis_privacy_err_report_impl = 0x400008f0;
+btdm_disable_adv_delay_impl = 0x400008f4;
+btdm_enable_scan_continue_impl = 0x400008f8;
+btdm_enable_scan_forever_impl = 0x400008fc;
+btdm_get_power_state_impl = 0x40000900;
+btdm_get_prevent_sleep_flag_impl = 0x40000904;
+btdm_power_state_active_impl = 0x40000908;
+btdm_switch_phy_coded_impl = 0x4000090c;
+hci_acl_data_handler = 0x40000910;
+hci_disconnect_cmd_handler = 0x40000914;
+hci_le_con_upd_cmd_handler = 0x40000918;
+hci_le_ltk_req_neg_reply_cmd_handler = 0x4000091c;
+hci_le_ltk_req_reply_cmd_handler = 0x40000920;
+hci_le_rd_chnl_map_cmd_handler = 0x40000924;
+hci_le_rd_phy_cmd_handler = 0x40000928;
+hci_le_rd_rem_feats_cmd_handler = 0x4000092c;
+hci_le_rem_con_param_req_neg_reply_cmd_handler = 0x40000930;
+hci_le_rem_con_param_req_reply_cmd_handler = 0x40000934;
+hci_le_set_data_len_cmd_handler = 0x40000938;
+hci_le_set_phy_cmd_handler = 0x4000093c;
+hci_le_start_enc_cmd_handler = 0x40000940;
+hci_rd_auth_payl_to_cmd_handler = 0x40000944;
+hci_rd_rem_ver_info_cmd_handler = 0x40000948;
+hci_rd_rssi_cmd_handler = 0x4000094c;
+hci_rd_tx_pwr_lvl_cmd_handler = 0x40000950;
+hci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40000954;
+hci_vs_set_pref_slave_latency_cmd_handler = 0x40000958;
+hci_wr_auth_payl_to_cmd_handler = 0x4000095c;
+ll_channel_map_ind_handler = 0x40000960;
+ll_connection_param_req_handler = 0x40000964;
+ll_connection_param_rsp_handler = 0x40000968;
+ll_connection_update_ind_handler = 0x4000096c;
+ll_enc_req_handler = 0x40000970;
+ll_enc_rsp_handler = 0x40000974;
+ll_feature_req_handler = 0x40000978;
+ll_feature_rsp_handler = 0x4000097c;
+ll_length_req_handler = 0x40000980;
+ll_length_rsp_handler = 0x40000984;
+ll_min_used_channels_ind_handler = 0x40000988;
+ll_pause_enc_req_handler = 0x4000098c;
+ll_pause_enc_rsp_handler = 0x40000990;
+ll_phy_req_handler = 0x40000994;
+ll_phy_rsp_handler = 0x40000998;
+ll_phy_update_ind_handler = 0x4000099c;
+ll_ping_req_handler = 0x400009a0;
+ll_ping_rsp_handler = 0x400009a4;
+ll_slave_feature_req_handler = 0x400009a8;
+ll_start_enc_req_handler = 0x400009ac;
+ll_start_enc_rsp_handler = 0x400009b0;
+ll_terminate_ind_handler = 0x400009b4;
+ll_version_ind_handler = 0x400009b8;
+llc_auth_payl_nearly_to_handler = 0x400009bc;
+llc_auth_payl_real_to_handler = 0x400009c0;
+llc_encrypt_ind_handler = 0x400009c4;
+llc_hci_command_handler_wrapper = 0x400009c8;
+llc_ll_connection_param_req_pdu_send = 0x400009cc;
+llc_ll_connection_param_rsp_pdu_send = 0x400009d0;
+llc_ll_connection_update_ind_pdu_send = 0x400009d4;
+llc_ll_enc_req_pdu_send = 0x400009d8;
+llc_ll_enc_rsp_pdu_send = 0x400009dc;
+llc_ll_feature_req_pdu_send = 0x400009e0;
+llc_ll_feature_rsp_pdu_send = 0x400009e4;
+llc_ll_length_req_pdu_send = 0x400009e8;
+llc_ll_length_rsp_pdu_send = 0x400009ec;
+llc_ll_pause_enc_req_pdu_send = 0x400009f0;
+llc_ll_pause_enc_rsp_pdu_send = 0x400009f4;
+llc_ll_phy_req_pdu_send = 0x400009f8;
+llc_ll_phy_rsp_pdu_send = 0x400009fc;
+llc_ll_ping_req_pdu_send = 0x40000a00;
+llc_ll_ping_rsp_pdu_send = 0x40000a04;
+llc_ll_start_enc_req_pdu_send = 0x40000a08;
+llc_ll_start_enc_rsp_pdu_send = 0x40000a0c;
+llc_ll_terminate_ind_pdu_send = 0x40000a10;
+llc_ll_unknown_rsp_pdu_send = 0x40000a14;
+llc_llcp_ch_map_update_ind_pdu_send = 0x40000a18;
+llc_llcp_phy_upd_ind_pdu_send = 0x40000a1c;
+llc_llcp_version_ind_pdu_send = 0x40000a20;
+llc_op_ch_map_upd_ind_handler = 0x40000a24;
+llc_op_con_upd_ind_handler = 0x40000a28;
+llc_op_disconnect_ind_handler = 0x40000a2c;
+llc_op_dl_upd_ind_handler = 0x40000a30;
+llc_op_encrypt_ind_handler = 0x40000a34;
+llc_op_feats_exch_ind_handler = 0x40000a38;
+llc_op_le_ping_ind_handler = 0x40000a3c;
+llc_op_phy_upd_ind_handler = 0x40000a40;
+llc_op_ver_exch_ind_handler = 0x40000a44;
+llc_stopped_ind_handler = 0x40000a48;
+lld_acl_rx_ind_handler = 0x40000a4c;
+lld_acl_tx_cfm_handler = 0x40000a50;
+lld_adv_end_ind_handler = 0x40000a54;
+lld_adv_rep_ind_handler = 0x40000a58;
+lld_ch_map_upd_cfm_handler = 0x40000a5c;
+lld_con_estab_ind_handler = 0x40000a60;
+lld_con_evt_sd_evt_time_set = 0x40000a64;
+lld_con_offset_upd_ind_handler = 0x40000a68;
+lld_con_param_upd_cfm_handler = 0x40000a6c;
+lld_disc_ind_handler = 0x40000a70;
+lld_init_end_ind_handler = 0x40000a74;
+lld_llcp_rx_ind_handler_wrapper = 0x40000a78;
+lld_llcp_tx_cfm_handler = 0x40000a7c;
+lld_per_adv_end_ind_handler = 0x40000a80;
+lld_per_adv_rep_ind_handler = 0x40000a84;
+lld_per_adv_rx_end_ind_handler = 0x40000a88;
+lld_phy_coded_500k_get = 0x40000a8c;
+lld_phy_upd_cfm_handler = 0x40000a90;
+lld_scan_end_ind_handler = 0x40000a94;
+lld_scan_req_ind_handler = 0x40000a98;
+lld_sync_start_req_handler = 0x40000a9c;
+lld_test_end_ind_handler = 0x40000aa0;
+lld_update_rxbuf_handler = 0x40000aa4;
+llm_ch_map_update_ind_handler = 0x40000aa8;
+llm_hci_command_handler_wrapper = 0x40000aac;
+llm_scan_period_to_handler = 0x40000ab0;
+r_Add2SelfBigHex256 = 0x40000ab4;
+r_AddBigHex256 = 0x40000ab8;
+r_AddBigHexModP256 = 0x40000abc;
+r_AddP256 = 0x40000ac0;
+r_AddPdiv2_256 = 0x40000ac4;
+r_GF_Jacobian_Point_Addition256 = 0x40000ac8;
+r_GF_Jacobian_Point_Double256 = 0x40000acc;
+r_GF_Point_Jacobian_To_Affine256 = 0x40000ad0;
+r_MultiplyBigHexByUint32_256 = 0x40000ad4;
+r_MultiplyBigHexModP256 = 0x40000ad8;
+r_MultiplyByU16ModP256 = 0x40000adc;
+r_SubtractBigHex256 = 0x40000ae0;
+r_SubtractBigHexMod256 = 0x40000ae4;
+r_SubtractBigHexUint32_256 = 0x40000ae8;
+r_SubtractFromSelfBigHex256 = 0x40000aec;
+r_SubtractFromSelfBigHexSign256 = 0x40000af0;
+r_aes_alloc = 0x40000af4;
+r_aes_ccm_continue = 0x40000af8;
+r_aes_ccm_process_e = 0x40000afc;
+r_aes_ccm_xor_128_lsb = 0x40000b00;
+r_aes_ccm_xor_128_msb = 0x40000b04;
+r_aes_cmac_continue = 0x40000b08;
+r_aes_cmac_start = 0x40000b0c;
+r_aes_k1_continue = 0x40000b10;
+r_aes_k2_continue = 0x40000b14;
+r_aes_k3_continue = 0x40000b18;
+r_aes_k4_continue = 0x40000b1c;
+r_aes_shift_left_128 = 0x40000b20;
+r_aes_start = 0x40000b24;
+r_aes_xor_128 = 0x40000b28;
+r_assert_err = 0x40000b2c;
+r_assert_param = 0x40000b30;
+r_assert_warn = 0x40000b34;
+r_bigHexInversion256 = 0x40000b38;
+r_ble_sw_cca_check_isr = 0x40000b3c;
+r_ble_util_buf_acl_tx_alloc = 0x40000b40;
+r_ble_util_buf_acl_tx_elt_get = 0x40000b44;
+r_ble_util_buf_acl_tx_free = 0x40000b48;
+r_ble_util_buf_acl_tx_free_in_isr = 0x40000b4c;
+r_ble_util_buf_adv_tx_alloc = 0x40000b50;
+r_ble_util_buf_adv_tx_free = 0x40000b54;
+r_ble_util_buf_adv_tx_free_in_isr = 0x40000b58;
+r_ble_util_buf_env_deinit = 0x40000b5c;
+r_ble_util_buf_env_init = 0x40000b60;
+r_ble_util_buf_get_rx_buf_nb = 0x40000b64;
+r_ble_util_buf_get_rx_buf_size = 0x40000b68;
+r_ble_util_buf_llcp_tx_alloc = 0x40000b6c;
+r_ble_util_buf_llcp_tx_free = 0x40000b70;
+r_ble_util_buf_rx_alloc = 0x40000b74;
+r_ble_util_buf_rx_alloc_in_isr = 0x40000b78;
+r_ble_util_buf_rx_free = 0x40000b7c;
+r_ble_util_buf_rx_free_in_isr = 0x40000b80;
+r_ble_util_buf_set_rx_buf_nb = 0x40000b84;
+r_ble_util_buf_set_rx_buf_size = 0x40000b88;
+r_ble_util_data_rx_buf_reset = 0x40000b8c;
+r_bt_bb_get_intr_mask = 0x40000b90;
+r_bt_bb_intr_clear = 0x40000b94;
+r_bt_bb_intr_mask_set = 0x40000b98;
+r_bt_rf_coex_cfg_set = 0x40000ba0;
+r_bt_rf_coex_conn_dynamic_pti_en_get = 0x40000ba4;
+r_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x40000bac;
+r_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x40000bb0;
+r_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40000bb4;
+r_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x40000bb8;
+r_bt_rf_coex_pti_table_get = 0x40000bbc;
+r_bt_rf_coex_st_param_get = 0x40000bc0;
+r_bt_rf_coex_st_param_set = 0x40000bc4;
+r_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x40000bc8;
+r_bt_rma_apply_rule_cs_fmt = 0x40000bcc;
+r_bt_rma_apply_rule_cs_idx = 0x40000bd0;
+r_bt_rma_configure = 0x40000bd4;
+r_bt_rma_deregister_rule_cs_fmt = 0x40000bd8;
+r_bt_rma_deregister_rule_cs_idx = 0x40000bdc;
+r_bt_rma_get_ant_by_act = 0x40000be0;
+r_bt_rma_init = 0x40000be4;
+r_bt_rma_register_rule_cs_fmt = 0x40000be8;
+r_bt_rma_register_rule_cs_idx = 0x40000bec;
+r_bt_rtp_apply_rule_cs_fmt = 0x40000bf0;
+r_bt_rtp_apply_rule_cs_idx = 0x40000bf4;
+r_bt_rtp_deregister_rule_cs_fmt = 0x40000bf8;
+r_bt_rtp_deregister_rule_cs_idx = 0x40000bfc;
+r_bt_rtp_init = 0x40000c04;
+r_bt_rtp_register_rule_cs_fmt = 0x40000c08;
+r_bt_rtp_register_rule_cs_idx = 0x40000c0c;
+r_btdm_isr = 0x40000c10;
+r_cali_phase_match_p = 0x40000c20;
+r_cmp_abs_time = 0x40000c24;
+r_cmp_dest_id = 0x40000c28;
+r_cmp_timer_id = 0x40000c2c;
+r_co_bdaddr_compare = 0x40000c30;
+r_co_ble_pkt_dur_in_us = 0x40000c34;
+r_co_list_extract = 0x40000c38;
+r_co_list_extract_after = 0x40000c3c;
+r_co_list_extract_sublist = 0x40000c40;
+r_co_list_find = 0x40000c44;
+r_co_list_init = 0x40000c48;
+r_co_list_insert_after = 0x40000c4c;
+r_co_list_insert_before = 0x40000c50;
+r_co_list_merge = 0x40000c54;
+r_co_list_pool_init = 0x40000c58;
+r_co_list_pop_front = 0x40000c5c;
+r_co_list_push_back = 0x40000c60;
+r_co_list_push_back_sublist = 0x40000c64;
+r_co_list_push_front = 0x40000c68;
+r_co_list_size = 0x40000c6c;
+r_co_nb_good_le_channels = 0x40000c70;
+r_co_util_pack = 0x40000c74;
+r_co_util_read_array_size = 0x40000c78;
+r_co_util_unpack = 0x40000c7c;
+r_dbg_env_deinit = 0x40000c80;
+r_dbg_env_init = 0x40000c84;
+r_dbg_platform_reset_complete = 0x40000c88;
+r_dl_upd_proc_start = 0x40000c8c;
+r_dump_data = 0x40000c90;
+r_ecc_abort_key256_generation = 0x40000c94;
+r_ecc_gen_new_public_key = 0x40000c98;
+r_ecc_gen_new_secret_key = 0x40000c9c;
+r_ecc_generate_key256 = 0x40000ca0;
+r_ecc_get_debug_Keys = 0x40000ca4;
+r_ecc_init = 0x40000ca8;
+r_ecc_is_valid_point = 0x40000cac;
+r_ecc_multiplication_event_handler = 0x40000cb0;
+r_ecc_point_multiplication_win_256 = 0x40000cb4;
+r_emi_alloc_em_mapping_by_offset = 0x40000cb8;
+r_emi_base_reg_lut_show = 0x40000cbc;
+r_emi_em_base_reg_show = 0x40000cc0;
+r_emi_free_em_mapping_by_offset = 0x40000cc4;
+r_emi_get_em_mapping_idx_by_offset = 0x40000cc8;
+r_emi_get_mem_addr_by_offset = 0x40000ccc;
+r_emi_overwrite_em_mapping_by_offset = 0x40000cd0;
+r_esp_vendor_hci_command_handler = 0x40000cd4;
+r_get_stack_usage = 0x40000cd8;
+r_h4tl_acl_hdr_rx_evt_handler = 0x40000cdc;
+r_h4tl_cmd_hdr_rx_evt_handler = 0x40000ce0;
+r_h4tl_cmd_pld_rx_evt_handler = 0x40000ce4;
+r_h4tl_eif_io_event_post = 0x40000ce8;
+r_h4tl_eif_register = 0x40000cec;
+r_h4tl_init = 0x40000cf0;
+r_h4tl_out_of_sync = 0x40000cf4;
+r_h4tl_out_of_sync_check = 0x40000cf8;
+r_h4tl_read_hdr = 0x40000cfc;
+r_h4tl_read_next_out_of_sync = 0x40000d00;
+r_h4tl_read_payl = 0x40000d04;
+r_h4tl_read_start = 0x40000d08;
+r_h4tl_rx_acl_hdr_extract = 0x40000d0c;
+r_h4tl_rx_cmd_hdr_extract = 0x40000d10;
+r_h4tl_rx_done = 0x40000d14;
+r_h4tl_start = 0x40000d18;
+r_h4tl_stop = 0x40000d1c;
+r_h4tl_tx_done = 0x40000d20;
+r_h4tl_tx_evt_handler = 0x40000d24;
+r_h4tl_write = 0x40000d28;
+r_hci_acl_tx_data_alloc = 0x40000d2c;
+r_hci_acl_tx_data_received = 0x40000d30;
+r_hci_basic_cmd_send_2_controller = 0x40000d34;
+r_hci_ble_adv_report_filter_check = 0x40000d38;
+r_hci_ble_adv_report_tx_check = 0x40000d3c;
+r_hci_ble_conhdl_register = 0x40000d40;
+r_hci_ble_conhdl_unregister = 0x40000d44;
+r_hci_build_acl_data = 0x40000d48;
+r_hci_build_cc_evt = 0x40000d4c;
+r_hci_build_cs_evt = 0x40000d50;
+r_hci_build_evt = 0x40000d54;
+r_hci_build_le_evt = 0x40000d58;
+r_hci_cmd_get_max_param_size = 0x40000d5c;
+r_hci_cmd_received = 0x40000d60;
+r_hci_cmd_reject = 0x40000d64;
+r_hci_evt_mask_check = 0x40000d68;
+r_hci_evt_mask_set = 0x40000d6c;
+r_hci_fc_acl_buf_size_set = 0x40000d70;
+r_hci_fc_acl_en = 0x40000d74;
+r_hci_fc_acl_packet_sent = 0x40000d78;
+r_hci_fc_check_host_available_nb_acl_packets = 0x40000d7c;
+r_hci_fc_host_nb_acl_pkts_complete = 0x40000d80;
+r_hci_fc_init = 0x40000d84;
+r_hci_look_for_cmd_desc = 0x40000d88;
+r_hci_look_for_evt_desc = 0x40000d8c;
+r_hci_look_for_le_evt_desc = 0x40000d90;
+r_hci_look_for_le_evt_desc_esp = 0x40000d94;
+r_hci_pack_bytes = 0x40000d98;
+r_hci_send_2_controller = 0x40000da0;
+r_hci_send_2_host = 0x40000da4;
+r_hci_tl_c2h_data_flow_on = 0x40000da8;
+r_hci_tl_cmd_hdr_rx_evt_handler = 0x40000dac;
+r_hci_tl_cmd_pld_rx_evt_handler = 0x40000db0;
+r_hci_tl_get_pkt = 0x40000db4;
+r_hci_tl_hci_pkt_handler = 0x40000db8;
+r_hci_tl_hci_tx_done_evt_handler = 0x40000dbc;
+r_hci_tl_inc_nb_h2c_cmd_pkts = 0x40000dc0;
+r_hci_tl_save_pkt = 0x40000dc4;
+r_hci_tl_send = 0x40000dc8;
+r_hci_tx_done = 0x40000dcc;
+r_hci_tx_start = 0x40000dd0;
+r_hci_tx_trigger = 0x40000dd4;
+r_isValidSecretKey_256 = 0x40000dd8;
+r_ke_check_malloc = 0x40000ddc;
+r_ke_event_callback_set = 0x40000de0;
+r_ke_event_clear = 0x40000de4;
+r_ke_event_flush = 0x40000de8;
+r_ke_event_get = 0x40000dec;
+r_ke_event_get_all = 0x40000df0;
+r_ke_event_init = 0x40000df4;
+r_ke_event_schedule = 0x40000df8;
+r_ke_event_set = 0x40000dfc;
+r_ke_flush = 0x40000e00;
+r_ke_free = 0x40000e04;
+r_ke_handler_search = 0x40000e08;
+r_ke_init = 0x40000e0c;
+r_ke_is_free = 0x40000e10;
+r_ke_malloc = 0x40000e14;
+r_ke_mem_init = 0x40000e18;
+r_ke_mem_is_empty = 0x40000e1c;
+r_ke_mem_is_in_heap = 0x40000e20;
+r_ke_msg_alloc = 0x40000e24;
+r_ke_msg_dest_id_get = 0x40000e28;
+r_ke_msg_discard = 0x40000e2c;
+r_ke_msg_forward = 0x40000e30;
+r_ke_msg_forward_new_id = 0x40000e34;
+r_ke_msg_free = 0x40000e38;
+r_ke_msg_in_queue = 0x40000e3c;
+r_ke_msg_save = 0x40000e40;
+r_ke_msg_send = 0x40000e44;
+r_ke_msg_send_basic = 0x40000e48;
+r_ke_msg_src_id_get = 0x40000e4c;
+r_ke_queue_extract = 0x40000e50;
+r_ke_queue_insert = 0x40000e54;
+r_ke_sleep_check = 0x40000e58;
+r_ke_state_get = 0x40000e5c;
+r_ke_state_set = 0x40000e60;
+r_ke_task_check = 0x40000e64;
+r_ke_task_create = 0x40000e68;
+r_ke_task_delete = 0x40000e6c;
+r_ke_task_handler_get = 0x40000e70;
+r_ke_task_init = 0x40000e74;
+r_ke_task_msg_flush = 0x40000e78;
+r_ke_task_saved_update = 0x40000e7c;
+r_ke_time = 0x40000e84;
+r_ke_time_cmp = 0x40000e88;
+r_ke_time_past = 0x40000e8c;
+r_ke_timer_active = 0x40000e90;
+r_ke_timer_adjust_all = 0x40000e94;
+r_ke_timer_clear = 0x40000e98;
+r_ke_timer_init = 0x40000e9c;
+r_ke_timer_schedule = 0x40000ea0;
+r_ke_timer_set = 0x40000ea4;
+r_led_init = 0x40000ea8;
+r_led_set_all = 0x40000eac;
+r_llc_aes_res_cb = 0x40000eb0;
+r_llc_ch_map_up_proc_err_cb = 0x40000eb4;
+r_llc_cleanup = 0x40000eb8;
+r_llc_cmd_cmp_send = 0x40000ebc;
+r_llc_cmd_stat_send = 0x40000ec0;
+r_llc_con_move_cbk = 0x40000ec4;
+r_llc_con_plan_set_update = 0x40000ec8;
+r_llc_con_upd_param_in_range = 0x40000ecc;
+r_llc_disconnect = 0x40000ed0;
+r_llc_disconnect_end = 0x40000ed4;
+r_llc_disconnect_proc_continue = 0x40000ed8;
+r_llc_disconnect_proc_err_cb = 0x40000edc;
+r_llc_dl_chg_check = 0x40000ee0;
+r_llc_dle_proc_err_cb = 0x40000ee4;
+r_llc_feats_exch_proc_err_cb = 0x40000ee8;
+r_llc_hci_cmd_handler_tab_p_get = 0x40000eec;
+r_llc_hci_con_param_req_evt_send = 0x40000ef4;
+r_llc_hci_con_upd_info_send = 0x40000ef8;
+r_llc_hci_disconnected_dis = 0x40000efc;
+r_llc_hci_dl_upd_info_send = 0x40000f00;
+r_llc_hci_enc_evt_send = 0x40000f04;
+r_llc_hci_feats_info_send = 0x40000f08;
+r_llc_hci_le_phy_upd_cmp_evt_send = 0x40000f0c;
+r_llc_hci_ltk_request_evt_send = 0x40000f10;
+r_llc_hci_nb_cmp_pkts_evt_send = 0x40000f14;
+r_llc_hci_version_info_send = 0x40000f18;
+r_llc_init_term_proc = 0x40000f1c;
+r_llc_iv_skd_rand_gen = 0x40000f20;
+r_llc_le_ping_proc_continue = 0x40000f24;
+r_llc_le_ping_proc_err_cb = 0x40000f28;
+/* r_llc_le_ping_restart = 0x40000f2c; */
+r_llc_le_ping_set = 0x40000f30;
+r_llc_ll_pause_enc_rsp_ack_handler = 0x40000f34;
+r_llc_ll_reject_ind_ack_handler = 0x40000f38;
+r_llc_ll_reject_ind_pdu_send = 0x40000f3c;
+r_llc_ll_start_enc_rsp_ack_handler = 0x40000f40;
+r_llc_ll_terminate_ind_ack = 0x40000f44;
+r_llc_ll_unknown_ind_handler = 0x40000f48;
+r_llc_llcp_send = 0x40000f4c;
+r_llc_llcp_state_set = 0x40000f50;
+r_llc_llcp_trans_timer_set = 0x40000f54;
+r_llc_llcp_tx_check = 0x40000f58;
+r_llc_loc_con_upd_proc_err_cb = 0x40000f64;
+r_llc_loc_dl_upd_proc_continue = 0x40000f68;
+r_llc_loc_encrypt_proc_continue = 0x40000f6c;
+r_llc_loc_encrypt_proc_err_cb = 0x40000f70;
+r_llc_loc_feats_exch_proc_continue = 0x40000f74;
+r_llc_loc_phy_upd_proc_err_cb = 0x40000f7c;
+r_llc_msg_handler_tab_p_get = 0x40000f80;
+r_llc_pref_param_compute = 0x40000f84;
+r_llc_proc_collision_check = 0x40000f88;
+r_llc_proc_err_ind = 0x40000f8c;
+r_llc_proc_get = 0x40000f90;
+r_llc_proc_id_get = 0x40000f94;
+r_llc_proc_reg = 0x40000f98;
+r_llc_proc_state_get = 0x40000f9c;
+r_llc_proc_state_set = 0x40000fa0;
+r_llc_proc_timer_pause_set = 0x40000fa4;
+r_llc_proc_timer_set = 0x40000fa8;
+r_llc_proc_unreg = 0x40000fac;
+r_llc_rem_ch_map_proc_continue = 0x40000fb0;
+r_llc_rem_con_upd_proc_err_cb = 0x40000fb8;
+r_llc_rem_dl_upd_proc = 0x40000fbc;
+r_llc_rem_encrypt_proc_continue = 0x40000fc0;
+r_llc_rem_encrypt_proc_err_cb = 0x40000fc4;
+r_llc_rem_phy_upd_proc_continue = 0x40000fc8;
+r_llc_rem_phy_upd_proc_err_cb = 0x40000fcc;
+r_llc_role_get = 0x40000fd0;
+r_llc_sk_gen = 0x40000fd4;
+r_llc_start = 0x40000fd8;
+r_llc_stop = 0x40000fdc;
+r_llc_ver_exch_loc_proc_continue = 0x40000fe0;
+r_llc_ver_proc_err_cb = 0x40000fe4;
+r_llcp_pdu_handler_tab_p_get = 0x40000fe8;
+r_lld_aa_gen = 0x40000fec;
+r_lld_adv_adv_data_set = 0x40000ff0;
+r_lld_adv_adv_data_update = 0x40000ff4;
+r_lld_adv_aux_ch_idx_set = 0x40000ff8;
+r_lld_adv_aux_evt_canceled_cbk = 0x40000ffc;
+r_lld_adv_aux_evt_start_cbk = 0x40001000;
+r_lld_adv_coex_check_ext_adv_synced = 0x40001004;
+r_lld_adv_coex_env_reset = 0x40001008;
+r_lld_adv_duration_update = 0x4000100c;
+r_lld_adv_dynamic_pti_process = 0x40001010;
+r_lld_adv_end = 0x40001014;
+r_lld_adv_evt_canceled_cbk = 0x40001018;
+r_lld_adv_evt_start_cbk = 0x4000101c;
+r_lld_adv_ext_chain_construct = 0x40001020;
+r_lld_adv_ext_pkt_prepare = 0x40001024;
+r_lld_adv_frm_cbk = 0x40001028;
+r_lld_adv_frm_isr = 0x4000102c;
+r_lld_adv_frm_skip_isr = 0x40001030;
+r_lld_adv_init = 0x40001034;
+r_lld_adv_pkt_rx = 0x40001038;
+r_lld_adv_pkt_rx_connect_ind = 0x4000103c;
+r_lld_adv_pkt_rx_send_scan_req_evt = 0x40001040;
+r_lld_adv_rand_addr_update = 0x40001044;
+r_lld_adv_restart = 0x40001048;
+r_lld_adv_scan_rsp_data_set = 0x4000104c;
+r_lld_adv_scan_rsp_data_update = 0x40001050;
+r_lld_adv_set_tx_power = 0x40001054;
+r_lld_adv_start = 0x40001058;
+r_lld_adv_stop = 0x4000105c;
+r_lld_adv_sync_info_set = 0x40001060;
+r_lld_adv_sync_info_update = 0x40001064;
+r_lld_calc_aux_rx = 0x40001068;
+r_lld_cca_alloc = 0x4000106c;
+r_lld_cca_data_reset = 0x40001070;
+r_lld_cca_free = 0x40001074;
+r_lld_ch_assess_data_get = 0x40001078;
+r_lld_ch_idx_get = 0x4000107c;
+r_lld_ch_map_set = 0x40001080;
+r_lld_channel_assess = 0x40001084;
+r_lld_con_activity_act_offset_compute = 0x40001088;
+r_lld_con_activity_offset_compute = 0x4000108c;
+r_lld_con_ch_map_update = 0x40001090;
+r_lld_con_cleanup = 0x40001094;
+r_lld_con_current_tx_power_get = 0x40001098;
+r_lld_con_data_flow_set = 0x4000109c;
+r_lld_con_data_len_update = 0x400010a0;
+r_lld_con_data_tx = 0x400010a4;
+r_lld_con_enc_key_load = 0x400010a8;
+r_lld_con_event_counter_get = 0x400010ac;
+r_lld_con_evt_canceled_cbk = 0x400010b0;
+r_lld_con_evt_duration_min_get = 0x400010b4;
+r_lld_con_evt_max_eff_time_cal = 0x400010b8;
+r_lld_con_evt_sd_evt_time_get = 0x400010bc;
+r_lld_con_evt_start_cbk = 0x400010c0;
+r_lld_con_evt_time_update = 0x400010c4;
+r_lld_con_free_all_tx_buf = 0x400010c8;
+r_lld_con_frm_cbk = 0x400010cc;
+r_lld_con_frm_isr = 0x400010d0;
+r_lld_con_frm_skip_isr = 0x400010d4;
+r_lld_con_init = 0x400010d8;
+r_lld_con_llcp_tx = 0x400010dc;
+r_lld_con_max_lat_calc = 0x400010e0;
+r_lld_con_offset_get = 0x400010e4;
+r_lld_con_param_update = 0x400010e8;
+r_lld_con_phys_update = 0x400010ec;
+r_lld_con_pref_slave_evt_dur_set = 0x400010f0;
+r_lld_con_pref_slave_latency_set = 0x400010f4;
+r_lld_con_rssi_get = 0x400010f8;
+r_lld_con_rx = 0x400010fc;
+/* r_lld_con_rx_channel_assess = 0x40001100; */
+r_lld_con_rx_enc = 0x40001104;
+r_lld_con_rx_isr = 0x40001108;
+r_lld_con_rx_link_info_check = 0x4000110c;
+r_lld_con_rx_llcp_check = 0x40001110;
+r_lld_con_rx_sync_time_update = 0x40001114;
+r_lld_con_set_tx_power = 0x4000111c;
+r_lld_con_start = 0x40001120;
+r_lld_con_tx = 0x40001128;
+r_lld_con_tx_enc = 0x4000112c;
+r_lld_con_tx_isr = 0x40001130;
+r_lld_con_tx_len_update = 0x40001134;
+r_lld_con_tx_len_update_for_intv = 0x40001138;
+r_lld_con_tx_len_update_for_rate = 0x4000113c;
+r_lld_con_tx_prog = 0x40001140;
+r_lld_conn_dynamic_pti_process = 0x40001144;
+r_lld_continue_scan_rx_isr_end_process = 0x40001148;
+r_lld_ext_scan_dynamic_pti_process = 0x4000114c;
+r_lld_hw_cca_end_isr = 0x40001150;
+r_lld_hw_cca_evt_handler = 0x40001154;
+r_lld_hw_cca_isr = 0x40001158;
+r_lld_init_cal_anchor_point = 0x4000115c;
+r_lld_init_compute_winoffset = 0x40001160;
+r_lld_init_connect_req_pack = 0x40001164;
+r_lld_init_end = 0x40001168;
+r_lld_init_evt_canceled_cbk = 0x4000116c;
+r_lld_init_evt_start_cbk = 0x40001170;
+r_lld_init_frm_cbk = 0x40001174;
+r_lld_init_frm_eof_isr = 0x40001178;
+r_lld_init_frm_skip_isr = 0x4000117c;
+r_lld_init_init = 0x40001180;
+r_lld_init_process_pkt_rx = 0x40001184;
+r_lld_init_process_pkt_rx_adv_ext_ind = 0x40001188;
+r_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x4000118c;
+r_lld_init_process_pkt_rx_aux_connect_rsp = 0x40001190;
+r_lld_init_process_pkt_tx = 0x40001194;
+r_lld_init_process_pkt_tx_cal_con_timestamp = 0x40001198;
+r_lld_init_sched = 0x4000119c;
+r_lld_init_set_tx_power = 0x400011a0;
+r_lld_init_start = 0x400011a4;
+r_lld_init_stop = 0x400011a8;
+r_lld_instant_proc_end = 0x400011ac;
+r_lld_per_adv_ch_map_update = 0x400011b4;
+r_lld_per_adv_chain_construct = 0x400011b8;
+r_lld_per_adv_cleanup = 0x400011bc;
+r_lld_per_adv_coex_env_reset = 0x400011c0;
+r_lld_per_adv_data_set = 0x400011c4;
+r_lld_per_adv_data_update = 0x400011c8;
+r_lld_per_adv_dynamic_pti_process = 0x400011cc;
+r_lld_per_adv_evt_canceled_cbk = 0x400011d0;
+r_lld_per_adv_evt_start_cbk = 0x400011d4;
+r_lld_per_adv_ext_pkt_prepare = 0x400011d8;
+r_lld_per_adv_frm_cbk = 0x400011dc;
+r_lld_per_adv_frm_isr = 0x400011e0;
+r_lld_per_adv_frm_skip_isr = 0x400011e4;
+r_lld_per_adv_init = 0x400011e8;
+r_lld_per_adv_init_info_get = 0x400011ec;
+r_lld_per_adv_list_add = 0x400011f0;
+r_lld_per_adv_list_rem = 0x400011f4;
+r_lld_per_adv_set_tx_power = 0x400011fc;
+r_lld_per_adv_start = 0x40001200;
+r_lld_per_adv_stop = 0x40001204;
+r_lld_per_adv_sync_info_get = 0x40001208;
+r_lld_process_cca_data = 0x4000120c;
+r_lld_ral_search = 0x40001210;
+r_lld_read_clock = 0x40001214;
+r_lld_res_list_add = 0x40001218;
+r_lld_res_list_is_empty = 0x40001220;
+r_lld_res_list_local_rpa_get = 0x40001224;
+r_lld_res_list_peer_rpa_get = 0x40001228;
+r_lld_res_list_peer_update = 0x4000122c;
+/* r_lld_res_list_priv_mode_update = 0x40001230; */
+r_lld_reset_reg = 0x40001238;
+r_lld_rpa_renew = 0x4000123c;
+r_lld_rpa_renew_evt_canceled_cbk = 0x40001240;
+r_lld_rpa_renew_evt_start_cbk = 0x40001244;
+r_lld_rpa_renew_instant_cbk = 0x40001248;
+r_lld_rxdesc_check = 0x4000124c;
+r_lld_rxdesc_free = 0x40001250;
+r_lld_scan_create_sync = 0x40001254;
+r_lld_scan_create_sync_cancel = 0x40001258;
+r_lld_scan_end = 0x4000125c;
+r_lld_scan_evt_canceled_cbk = 0x40001260;
+r_lld_scan_evt_start_cbk = 0x40001264;
+r_lld_scan_frm_cbk = 0x40001268;
+r_lld_scan_frm_eof_isr = 0x4000126c;
+r_lld_scan_frm_rx_isr = 0x40001270;
+r_lld_scan_frm_skip_isr = 0x40001274;
+r_lld_scan_init = 0x40001278;
+r_lld_scan_params_update = 0x4000127c;
+r_lld_scan_process_pkt_rx_aux_adv_ind = 0x40001288;
+r_lld_scan_process_pkt_rx_aux_chain_ind = 0x4000128c;
+r_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40001290;
+r_lld_scan_process_pkt_rx_ext_adv = 0x40001294;
+r_lld_scan_process_pkt_rx_ext_adv_ind = 0x40001298;
+r_lld_scan_process_pkt_rx_legacy_adv = 0x4000129c;
+r_lld_scan_restart = 0x400012a0;
+r_lld_scan_sched = 0x400012a4;
+r_lld_scan_set_tx_power = 0x400012a8;
+r_lld_scan_start = 0x400012ac;
+r_lld_scan_stop = 0x400012b0;
+r_lld_scan_sync_accept = 0x400012b4;
+r_lld_scan_sync_info_unpack = 0x400012b8;
+r_lld_scan_trunc_ind = 0x400012bc;
+r_lld_sw_cca_evt_handler = 0x400012c0;
+r_lld_sw_cca_isr = 0x400012c4;
+r_lld_sync_ch_map_update = 0x400012c8;
+r_lld_sync_cleanup = 0x400012cc;
+r_lld_sync_evt_canceled_cbk = 0x400012d0;
+r_lld_sync_evt_start_cbk = 0x400012d4;
+r_lld_sync_frm_cbk = 0x400012d8;
+r_lld_sync_frm_eof_isr = 0x400012dc;
+r_lld_sync_frm_rx_isr = 0x400012e0;
+r_lld_sync_frm_skip_isr = 0x400012e4;
+r_lld_sync_init = 0x400012e8;
+r_lld_sync_process_pkt_rx = 0x400012ec;
+r_lld_sync_process_pkt_rx_aux_sync_ind = 0x400012f0;
+r_lld_sync_process_pkt_rx_pkt_check = 0x400012f4;
+r_lld_sync_scan_dynamic_pti_process = 0x400012f8;
+r_lld_sync_sched = 0x400012fc;
+r_lld_sync_start = 0x40001300;
+r_lld_sync_stop = 0x40001304;
+r_lld_sync_trunc_ind = 0x40001308;
+r_lld_test_cleanup = 0x4000130c;
+r_lld_test_evt_canceled_cbk = 0x40001310;
+r_lld_test_evt_start_cbk = 0x40001314;
+r_lld_test_freq2chnl = 0x40001318;
+r_lld_test_frm_cbk = 0x4000131c;
+r_lld_test_frm_isr = 0x40001320;
+r_lld_test_init = 0x40001324;
+r_lld_test_rx_isr = 0x40001328;
+r_lld_test_set_tx_power = 0x4000132c;
+r_lld_test_start = 0x40001330;
+/* r_lld_test_stop = 0x40001334; */
+r_lld_update_rxbuf = 0x40001338;
+r_lld_update_rxbuf_isr = 0x4000133c;
+r_lld_white_list_add = 0x40001340;
+r_lld_white_list_rem = 0x40001344;
+r_llm_activity_free_get = 0x40001348;
+r_llm_activity_free_set = 0x4000134c;
+r_llm_activity_syncing_get = 0x40001350;
+r_llm_adv_con_len_check = 0x40001354;
+r_llm_adv_hdl_to_id = 0x40001358;
+r_llm_adv_rep_flow_control_check = 0x4000135c;
+r_llm_adv_rep_flow_control_update = 0x40001360;
+r_llm_adv_reports_list_check = 0x40001364;
+r_llm_adv_set_all_release = 0x40001368;
+r_llm_adv_set_dft_params = 0x4000136c;
+r_llm_adv_set_release = 0x40001370;
+r_llm_aes_res_cb = 0x40001374;
+r_llm_ble_update_adv_flow_control = 0x40001378;
+r_llm_ch_map_update = 0x4000137c;
+r_llm_cmd_cmp_send = 0x40001380;
+r_llm_cmd_stat_send = 0x40001384;
+r_llm_dev_list_empty_entry = 0x40001388;
+r_llm_dev_list_search = 0x4000138c;
+r_llm_env_adv_dup_filt_deinit = 0x40001390;
+r_llm_env_adv_dup_filt_init = 0x40001394;
+r_llm_init_ble_adv_report_flow_contol = 0x40001398;
+r_llm_is_dev_connected = 0x4000139c;
+r_llm_is_dev_synced = 0x400013a0;
+r_llm_is_non_con_act_ongoing_check = 0x400013a4;
+r_llm_is_wl_accessible = 0x400013a8;
+r_llm_le_evt_mask_check = 0x400013ac;
+r_llm_link_disc = 0x400013b4;
+r_llm_master_ch_map_get = 0x400013b8;
+r_llm_msg_handler_tab_p_get = 0x400013bc;
+r_llm_no_activity = 0x400013c0;
+r_llm_per_adv_slot_dur = 0x400013c4;
+r_llm_plan_elt_get = 0x400013c8;
+r_llm_rx_path_comp_get = 0x400013cc;
+r_llm_scan_start = 0x400013d0;
+r_llm_scan_sync_acad_attach = 0x400013d4;
+r_llm_scan_sync_acad_detach = 0x400013d8;
+r_llm_send_adv_lost_event_to_host = 0x400013dc;
+r_llm_tx_path_comp_get = 0x400013e0;
+r_misc_deinit = 0x400013e4;
+r_misc_free_em_buf_in_isr = 0x400013e8;
+r_misc_init = 0x400013ec;
+r_misc_msg_handler_tab_p_get = 0x400013f0;
+r_notEqual256 = 0x400013f4;
+r_phy_upd_proc_start = 0x400013f8;
+r_platform_reset = 0x400013fc;
+r_rf_em_init = 0x40001404;
+r_rf_force_agc_enable = 0x40001408;
+r_rf_reg_rd = 0x4000140c;
+r_rf_reg_wr = 0x40001410;
+r_rf_reset = 0x40001414;
+r_rf_rssi_convert = 0x40001418;
+r_rf_rw_v9_le_disable = 0x4000141c;
+r_rf_rw_v9_le_enable = 0x40001420;
+r_rf_sleep = 0x40001424;
+r_rf_util_cs_fmt_convert = 0x40001430;
+r_rw_crypto_aes_ccm = 0x40001434;
+r_rw_crypto_aes_encrypt = 0x40001438;
+r_rw_crypto_aes_init = 0x4000143c;
+r_rw_crypto_aes_k1 = 0x40001440;
+r_rw_crypto_aes_k2 = 0x40001444;
+r_rw_crypto_aes_k3 = 0x40001448;
+r_rw_crypto_aes_k4 = 0x4000144c;
+r_rw_crypto_aes_rand = 0x40001450;
+r_rw_crypto_aes_result_handler = 0x40001454;
+r_rw_crypto_aes_s1 = 0x40001458;
+r_rw_cryto_aes_cmac = 0x4000145c;
+r_rw_v9_init_em_radio_table = 0x40001460;
+r_rwble_sleep_enter = 0x40001468;
+r_rwble_sleep_wakeup_end = 0x4000146c;
+/* r_rwbtdm_isr_wrapper = 0x40001470; */
+r_rwip_active_check = 0x40001474;
+r_rwip_aes_encrypt = 0x40001478;
+/* r_rwip_assert = 0x4000147c; */
+r_rwip_crypt_evt_handler = 0x40001480;
+r_rwip_crypt_isr_handler = 0x40001484;
+r_rwip_eif_get = 0x40001488;
+r_rwip_half_slot_2_lpcycles = 0x4000148c;
+r_rwip_hus_2_lpcycles = 0x40001490;
+r_rwip_isr = 0x40001494;
+r_rwip_lpcycles_2_hus = 0x40001498;
+r_rwip_prevent_sleep_clear = 0x4000149c;
+r_rwip_prevent_sleep_set = 0x400014a0;
+r_rwip_schedule = 0x400014a4;
+r_rwip_sleep = 0x400014a8;
+r_rwip_sw_int_handler = 0x400014ac;
+r_rwip_sw_int_req = 0x400014b0;
+r_rwip_time_get = 0x400014b4;
+r_rwip_timer_10ms_handler = 0x400014b8;
+r_rwip_timer_10ms_set = 0x400014bc;
+r_rwip_timer_hs_handler = 0x400014c0;
+r_rwip_timer_hs_set = 0x400014c4;
+r_rwip_timer_hus_handler = 0x400014c8;
+r_rwip_timer_hus_set = 0x400014cc;
+r_rwip_wakeup = 0x400014d0;
+/* r_rwip_wakeup_end = 0x400014d4; */
+r_rwip_wlcoex_set = 0x400014d8;
+r_sch_alarm_clear = 0x400014dc;
+r_sch_alarm_init = 0x400014e0;
+r_sch_alarm_prog = 0x400014e4;
+r_sch_alarm_set = 0x400014e8;
+r_sch_alarm_timer_isr = 0x400014ec;
+r_sch_arb_conflict_check = 0x400014f0;
+r_sch_arb_elt_cancel = 0x400014f4;
+r_sch_arb_init = 0x400014fc;
+r_sch_arb_insert = 0x40001500;
+r_sch_arb_prog_timer = 0x40001504;
+r_sch_arb_remove = 0x40001508;
+r_sch_arb_sw_isr = 0x4000150c;
+r_sch_plan_chk = 0x40001510;
+r_sch_plan_clock_wrap_offset_update = 0x40001514;
+r_sch_plan_init = 0x40001518;
+r_sch_plan_interval_req = 0x4000151c;
+r_sch_plan_offset_max_calc = 0x40001520;
+r_sch_plan_offset_req = 0x40001524;
+r_sch_plan_position_range_compute = 0x40001528;
+r_sch_plan_rem = 0x4000152c;
+r_sch_plan_req = 0x40001530;
+r_sch_prog_init = 0x4000153c;
+r_sch_prog_push = 0x40001540;
+r_sch_prog_rx_isr = 0x40001544;
+r_sch_prog_skip_isr = 0x40001548;
+r_sch_prog_tx_isr = 0x4000154c;
+r_sch_slice_bg_add = 0x40001550;
+r_sch_slice_bg_remove = 0x40001554;
+r_sch_slice_compute = 0x40001558;
+r_sch_slice_fg_add = 0x4000155c;
+r_sch_slice_fg_remove = 0x40001560;
+r_sch_slice_init = 0x40001564;
+r_sch_slice_per_add = 0x40001568;
+r_sch_slice_per_remove = 0x4000156c;
+r_sdk_config_get_bt_sleep_enable = 0x40001570;
+r_sdk_config_get_hl_derived_opts = 0x40001574;
+r_sdk_config_get_opts = 0x40001578;
+r_sdk_config_get_priv_opts = 0x4000157c;
+r_sdk_config_set_bt_sleep_enable = 0x40001580;
+r_sdk_config_set_hl_derived_opts = 0x40001584;
+r_sdk_config_set_opts = 0x40001588;
+r_specialModP256 = 0x4000158c;
+r_unloaded_area_init = 0x40001590;
+r_vhci_flow_off = 0x40001594;
+r_vhci_flow_on = 0x40001598;
+r_vhci_notify_host_send_available = 0x4000159c;
+r_vhci_send_to_host = 0x400015a0;
+r_vnd_hci_command_handler = 0x400015a4;
+r_vshci_init = 0x400015a8;
+vnd_hci_command_handler_wrapper = 0x400015ac;
+
+/* bluetooth hook funcs */
+r_llc_loc_encrypt_proc_continue_hook = 0x40001c60;
+r_llc_loc_phy_upd_proc_continue_hook = 0x40001c64;
+r_llc_rem_phy_upd_proc_continue_hook = 0x40001c68;
+r_lld_scan_frm_eof_isr_hook = 0x40001c6c;
+r_lld_scan_evt_start_cbk_hook = 0x40001c70;
+r_lld_scan_process_pkt_rx_ext_adv_hook = 0x40001c78;
+r_lld_scan_sched_hook = 0x40001c7c;
+r_lld_adv_evt_start_cbk_hook = 0x40001c84;
+r_lld_adv_aux_evt_start_cbk_hook = 0x40001c88;
+r_lld_adv_frm_isr_hook = 0x40001c8c;
+r_lld_adv_start_init_evt_param_hook = 0x40001c90;
+r_lld_con_evt_canceled_cbk_hook = 0x40001c94;
+r_lld_con_frm_isr_hook = 0x40001c98;
+r_lld_con_tx_hook = 0x40001c9c;
+r_lld_con_rx_hook = 0x40001ca0;
+r_lld_con_evt_start_cbk_hook = 0x40001ca4;
+r_lld_con_tx_prog_new_packet_hook = 0x40001cac;
+r_lld_init_frm_eof_isr_hook = 0x40001cb0;
+r_lld_init_evt_start_cbk_hook = 0x40001cb4;
+r_lld_init_sched_hook = 0x40001cbc;
+r_lld_init_process_pkt_tx_hook = 0x40001cc0;
+r_lld_per_adv_evt_start_cbk_hook = 0x40001cc4;
+r_lld_per_adv_frm_isr_hook = 0x40001cc8;
+r_lld_per_adv_start_hook = 0x40001ccc;
+r_lld_sync_frm_eof_isr_hook = 0x40001cd0;
+r_lld_sync_evt_start_cbk_hook = 0x40001cd4;
+r_lld_sync_start_hook = 0x40001cd8;
+r_lld_sync_process_pkt_rx_pkt_check_hook = 0x40001cdc;
+r_sch_arb_insert_hook = 0x40001ce0;
+r_sch_plan_offset_req_hook = 0x40001ce4;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco3.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco3.ld
index 3568b2d6e8d..edad2237dc7 100644
--- a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco3.ld
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco3.ld
@@ -44,38 +44,6 @@ ppProcTxCallback = 0x40001b30;
 ieee80211_gettid = 0x40001b34;
 
 
-/***************************************
-   Group eco3_bluetooth
- ***************************************/
-
-/* Functions */
-r_lld_legacy_adv_dynamic_pti_get = 0x40001b38;
-r_lld_legacy_adv_dynamic_pti_process = 0x40001b3c;
-r_lld_ext_adv_dynamic_pti_get = 0x40001b40;
-r_lld_ext_adv_dynamic_aux_pti_process = 0x40001b44;
-r_lld_ext_adv_dynamic_pti_process = 0x40001b48;
-r_lld_adv_ext_pkt_prepare_set = 0x40001b4c;
-r_lld_adv_ext_chain_connectable_construct = 0x40001b54;
-r_lld_adv_pkt_rx_connect_post = 0x40001b5c;
-r_lld_adv_start_init_evt_param = 0x40001b60;
-r_lld_adv_start_set_cs = 0x40001b64;
-/* r_lld_adv_start_update_filter_policy = 0x40001b68; */
-r_lld_adv_start_schedule_asap = 0x40001b6c;
-r_lld_con_tx_prog_new_packet_coex = 0x40001b70;
-r_lld_per_adv_dynamic_pti_get = 0x40001b78;
-r_lld_per_adv_evt_start_chm_upd = 0x40001b7c;
-r_lld_ext_scan_dynamic_pti_get = 0x40001b80;
-r_lld_sync_insert = 0x40001b88;
-r_sch_prog_ble_push = 0x40001b8c;
-r_sch_prog_bt_push = 0x40001b90;
-r_lld_init_evt_end_type_set = 0x40001b94;
-r_lld_init_evt_end_type_get = 0x40001b98;
-r_lld_adv_direct_adv_use_rpa_addr_state_set = 0x40001b9c;
-r_lld_adv_direct_adv_use_rpa_addr_state_get = 0x40001ba0;
-r_lld_init_evt_end_type_check_state_set = 0x40001ba4;
-r_lld_init_evt_end_type_check_state_get = 0x40001ba8;
-
-
 /***************************************
    Group eco3_phy
  ***************************************/
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco3_bt_funcs.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco3_bt_funcs.ld
new file mode 100644
index 00000000000..6f67b8ddc33
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco3_bt_funcs.ld
@@ -0,0 +1,45 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ESP32C3 ECO3 ROM address table
+Version 3 API's imported from the ROM
+*/
+
+
+/***************************************
+   Group eco3_bluetooth
+ ***************************************/
+
+/* Functions */
+r_lld_legacy_adv_dynamic_pti_get = 0x40001b38;
+r_lld_legacy_adv_dynamic_pti_process = 0x40001b3c;
+r_lld_ext_adv_dynamic_pti_get = 0x40001b40;
+r_lld_ext_adv_dynamic_aux_pti_process = 0x40001b44;
+r_lld_ext_adv_dynamic_pti_process = 0x40001b48;
+/*
+r_lld_adv_ext_pkt_prepare_set = 0x40001b4c;
+*/
+r_lld_adv_ext_chain_connectable_construct = 0x40001b54;
+r_lld_adv_pkt_rx_connect_post = 0x40001b5c;
+r_lld_adv_start_init_evt_param = 0x40001b60;
+r_lld_adv_start_set_cs = 0x40001b64;
+/* r_lld_adv_start_update_filter_policy = 0x40001b68; */
+r_lld_adv_start_schedule_asap = 0x40001b6c;
+r_lld_con_tx_prog_new_packet_coex = 0x40001b70;
+r_lld_per_adv_dynamic_pti_get = 0x40001b78;
+r_lld_per_adv_evt_start_chm_upd = 0x40001b7c;
+r_lld_ext_scan_dynamic_pti_get = 0x40001b80;
+r_lld_sync_insert = 0x40001b88;
+/*
+r_sch_prog_ble_push = 0x40001b8c;
+*/
+r_sch_prog_bt_push = 0x40001b90;
+r_lld_init_evt_end_type_set = 0x40001b94;
+r_lld_init_evt_end_type_get = 0x40001b98;
+r_lld_adv_direct_adv_use_rpa_addr_state_set = 0x40001b9c;
+r_lld_adv_direct_adv_use_rpa_addr_state_get = 0x40001ba0;
+r_lld_init_evt_end_type_check_state_set = 0x40001ba4;
+r_lld_init_evt_end_type_check_state_get = 0x40001ba8;
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
index 69df558be7e..41445a1b543 100644
--- a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7.ld
@@ -93,132 +93,6 @@ rom1_phy_close_rf = 0x40001c18;
 uart_tx_switch = 0x40001c44;
 
 
-/***************************************
- Group eco7_bluetooth
- ***************************************/
-
-/* Functions */
-r_lld_con_count_get = 0x40001c48;
-r_lld_update_con_offset = 0x40001c4c;
-r_lld_con_update_last_clock = 0x40001c50;
-r_lld_con_llcp_ind_info_clear = 0x40001c54;
-r_lld_con_update_terminte_info_init = 0x40001c58;
-r_lld_con_terminate_max_evt_update = 0x40001c5c;
-r_llc_pref_param_compute_eco = 0x40001ce8;
-r_llc_hci_con_upd_info_send_eco = 0x40001cec;
-r_llc_rem_encrypt_proc_continue_eco = 0x40001cf0;
-r_llc_start_eco = 0x40001cf8;
-r_lld_ext_adv_dynamic_aux_pti_process_eco = 0x40001cfc;
-r_lld_adv_start_eco = 0x40001d04;
-r_lld_con_evt_canceled_cbk_eco = 0x40001d08;
-r_lld_con_evt_time_update_eco = 0x40001d0c;
-r_lld_con_start_eco = 0x40001d10;
-r_lld_con_frm_isr_eco = 0x40001d14;
-r_lld_con_tx_eco = 0x40001d18;
-r_lld_ext_scan_dynamic_pti_process_eco = 0x40001d28;
-r_lld_scan_frm_eof_isr_eco = 0x40001d2c;
-r_lld_sync_start_eco = 0x40001d30;
-r_lld_sync_insert_eco = 0x40001d34;
-r_llm_adv_rep_flow_control_update_eco = 0x40001d38;
-r_llm_env_adv_dup_filt_init_eco = 0x40001d3c;
-r_llm_env_adv_dup_filt_deinit_eco = 0x40001d40;
-r_llm_adv_rep_flow_control_check_eco = 0x40001d44;
-r_llm_scan_start_eco = 0x40001d48;
-r_llm_update_duplicate_scan_count = 0x40001d4c;
-r_llc_hci_command_handler_pre = 0x40001d50;
-r_llc_hci_command_handler_get = 0x40001d54;
-r_llc_hci_command_handler_search = 0x40001d58;
-r_llc_llcp_pdu_handler_get_overwrite = 0x40001d5c;
-r_llc_llcp_pdu_handler_pre = 0x40001d60;
-r_llc_llcp_pdu_handler_end = 0x40001d64;
-r_llc_con_conflict_check = 0x40001d6c;
-r_sch_prog_hw_reset_try = 0x40001d70;
-r_sch_prog_et_state_reset = 0x40001d74;
-r_sch_prog_end_isr_handler = 0x40001d78;
-r_sch_plan_conflict_check = 0x40001d7c;
-r_rwble_isr_hw_fixed = 0x40001d80;
-r_bt_bb_recorrect_is_dead = 0x40001d84;
-r_bt_bb_restart_hw_recorrect = 0x40001d88;
-r_ke_task_handler_pre = 0x40001da0;
-r_ke_task_handler_end = 0x40001da4;
-r_lld_scan_frm_skip_isr_eco = 0x40001db0;
-r_lld_ext_scan_dynamic_pti_reset = 0x40001db4;
-r_llc_rem_phy_upd_proc_continue_eco = 0x40001db8;
-r_llm_get_preferred_phys = 0x40001dbc;
-r_lld_hw_cca_isr_eco = 0x40001dc0;
-r_lld_sw_cca_isr_eco = 0x40001dc4;
-r_lld_cca_chan_prn_e = 0x40001dc8;
-r_lld_cca_chan_prn_s = 0x40001dcc;
-r_lld_cca_chan_sel_remap = 0x40001dd0;
-r_lld_cca_chan_sel_1 = 0x40001dd4;
-r_lld_cca_chan_sel_2 = 0x40001dd8;
-r_lld_cca_set_thresh = 0x40001ddc;
-r_lld_cca_con_start = 0x40001de0;
-r_lld_cca_con_end = 0x40001de4;
-r_lld_cca_chm_restore = 0x40001de8;
-r_lld_cca_chan_unused_check = 0x40001dec;
-r_lld_cca_chm_update_check = 0x40001df0;
-r_lld_cca_busy_mode_handle = 0x40001df4;
-r_lld_cca_lbt_handle = 0x40001df8;
-r_lld_cca_scst_timeout_check = 0x40001dfc;
-r_lld_cca_chan_avl_timeout_check = 0x40001e00;
-
-r_lld_con_start_hook = 0x40001ca8;
-
-/* ble Functions eco */
-r_bt_bb_isr = 0x40000b9c;
-r_bt_rf_coex_conn_phy_coded_data_time_limit_en_get = 0x40000ba8;
-r_bt_rtp_get_txpwr_idx_by_act = 0x40000c00;
-r_btdm_task_post = 0x40000c14;
-r_btdm_task_post_from_isr = 0x40000c18;
-r_btdm_task_recycle = 0x40000c1c;
-r_hci_register_vendor_desc_tab = 0x40000d9c;
-r_ke_task_schedule = 0x40000e80;
-r_llc_hci_command_handler = 0x40000ef0;
-r_llc_loc_ch_map_proc_continue = 0x40000f5c;
-r_llc_loc_con_upd_proc_continue = 0x40000f60;
-r_llc_loc_phy_upd_proc_continue = 0x40000f78;
-r_llc_rem_con_upd_proc_continue = 0x40000fb4;
-r_lld_con_sched = 0x40001118;
-r_lld_con_stop = 0x40001124;
-r_lld_llcp_rx_ind_handler = 0x400011b0;
-r_lld_per_adv_sched = 0x400011f8;
-r_lld_scan_process_pkt_rx_adv_rep = 0x40001284;
-r_register_esp_vendor_cmd_handler = 0x40001400;
-r_rf_txpwr_cs_get = 0x40001428;
-r_rf_txpwr_dbm_get = 0x4000142c;
-r_sch_arb_event_start_isr = 0x400014f8;
-r_sch_plan_set = 0x40001534;
-r_sch_prog_end_isr = 0x40001538;
-r_lld_adv_ext_chain_scannable_construct = 0x40001b58;
-
-r_lld_scan_process_pkt_rx = 0x40001280;
-r_llm_le_features_get = 0x400013b0;
-
-/* ble functions rename */
-r_lld_init_start_hack = 0x400011a4;
-
-/* ble functions disable */
-/*
-r_lld_adv_frm_isr_eco = 0x40001d00;
-r_lld_res_list_clear = 0x40004638;
-r_lld_res_list_rem = 0x40004680;
-r_lld_adv_start_hook = 0x40001c80;
-r_lld_con_evt_start_cbk_eco = 0x40001d1c;
-r_lld_con_tx_prog_new_packet = 0x40001b74;
-r_lld_adv_ext_chain_none_construct = 0x40001b50;
-r_llc_llcp_send_eco = 0x40001cf4;
-r_llc_llcp_channel_map_ind_ack = 0x40001d68;
-r_rwble_isr = 0x40001464;
-r_lld_scan_start_eco = 0x40001d24;
-r_lld_scan_try_sched_eco = 0x40001dac;
-r_lld_scan_start_hook = 0x40001c74;
-r_lld_init_start_hook = 0x40001cb8;
-r_lld_scan_evt_start_cbk_eco = 0x40001d20;
-r_ke_task_handler_get_overwrite = 0x40001da8;
-*/
-
-
 /***************************************
  Group eco7_phy
  ***************************************/
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7_bt_funcs.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7_bt_funcs.ld
new file mode 100644
index 00000000000..33b0ed595d6
--- /dev/null
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.eco7_bt_funcs.ld
@@ -0,0 +1,130 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/***************************************
+ Group eco7_bluetooth
+ ***************************************/
+
+/* Functions */
+r_lld_con_count_get = 0x40001c48;
+r_lld_update_con_offset = 0x40001c4c;
+r_lld_con_update_last_clock = 0x40001c50;
+r_lld_con_llcp_ind_info_clear = 0x40001c54;
+r_lld_con_update_terminte_info_init = 0x40001c58;
+r_lld_con_terminate_max_evt_update = 0x40001c5c;
+r_llc_pref_param_compute_eco = 0x40001ce8;
+r_llc_hci_con_upd_info_send_eco = 0x40001cec;
+r_llc_rem_encrypt_proc_continue_eco = 0x40001cf0;
+r_llc_start_eco = 0x40001cf8;
+r_lld_ext_adv_dynamic_aux_pti_process_eco = 0x40001cfc;
+r_lld_adv_start_eco = 0x40001d04;
+r_lld_con_evt_canceled_cbk_eco = 0x40001d08;
+r_lld_con_evt_time_update_eco = 0x40001d0c;
+r_lld_con_start_eco = 0x40001d10;
+r_lld_con_frm_isr_eco = 0x40001d14;
+r_lld_con_tx_eco = 0x40001d18;
+r_lld_ext_scan_dynamic_pti_process_eco = 0x40001d28;
+r_lld_scan_frm_eof_isr_eco = 0x40001d2c;
+r_lld_sync_start_eco = 0x40001d30;
+r_lld_sync_insert_eco = 0x40001d34;
+r_llm_adv_rep_flow_control_update_eco = 0x40001d38;
+r_llm_env_adv_dup_filt_init_eco = 0x40001d3c;
+r_llm_env_adv_dup_filt_deinit_eco = 0x40001d40;
+r_llm_adv_rep_flow_control_check_eco = 0x40001d44;
+r_llm_scan_start_eco = 0x40001d48;
+r_llm_update_duplicate_scan_count = 0x40001d4c;
+r_llc_hci_command_handler_pre = 0x40001d50;
+r_llc_hci_command_handler_get = 0x40001d54;
+r_llc_hci_command_handler_search = 0x40001d58;
+r_llc_llcp_pdu_handler_pre = 0x40001d60;
+r_llc_llcp_pdu_handler_end = 0x40001d64;
+r_llc_con_conflict_check = 0x40001d6c;
+r_sch_prog_hw_reset_try = 0x40001d70;
+r_sch_prog_et_state_reset = 0x40001d74;
+r_sch_prog_end_isr_handler = 0x40001d78;
+r_sch_plan_conflict_check = 0x40001d7c;
+r_rwble_isr_hw_fixed = 0x40001d80;
+r_bt_bb_recorrect_is_dead = 0x40001d84;
+r_bt_bb_restart_hw_recorrect = 0x40001d88;
+r_ke_task_handler_pre = 0x40001da0;
+r_ke_task_handler_end = 0x40001da4;
+r_lld_scan_frm_skip_isr_eco = 0x40001db0;
+r_lld_ext_scan_dynamic_pti_reset = 0x40001db4;
+r_llc_rem_phy_upd_proc_continue_eco = 0x40001db8;
+r_llm_get_preferred_phys = 0x40001dbc;
+r_lld_hw_cca_isr_eco = 0x40001dc0;
+r_lld_sw_cca_isr_eco = 0x40001dc4;
+r_lld_cca_chan_prn_e = 0x40001dc8;
+r_lld_cca_chan_prn_s = 0x40001dcc;
+r_lld_cca_chan_sel_remap = 0x40001dd0;
+r_lld_cca_chan_sel_1 = 0x40001dd4;
+r_lld_cca_chan_sel_2 = 0x40001dd8;
+r_lld_cca_set_thresh = 0x40001ddc;
+r_lld_cca_con_start = 0x40001de0;
+r_lld_cca_con_end = 0x40001de4;
+r_lld_cca_chm_restore = 0x40001de8;
+r_lld_cca_chan_unused_check = 0x40001dec;
+r_lld_cca_chm_update_check = 0x40001df0;
+r_lld_cca_busy_mode_handle = 0x40001df4;
+r_lld_cca_lbt_handle = 0x40001df8;
+r_lld_cca_scst_timeout_check = 0x40001dfc;
+r_lld_cca_chan_avl_timeout_check = 0x40001e00;
+
+r_lld_con_start_hook = 0x40001ca8;
+
+/* ble Functions eco */
+r_bt_bb_isr = 0x40000b9c;
+r_bt_rf_coex_conn_phy_coded_data_time_limit_en_get = 0x40000ba8;
+r_bt_rtp_get_txpwr_idx_by_act = 0x40000c00;
+r_btdm_task_post = 0x40000c14;
+r_btdm_task_post_from_isr = 0x40000c18;
+r_btdm_task_recycle = 0x40000c1c;
+r_ke_task_schedule = 0x40000e80;
+r_llc_hci_command_handler = 0x40000ef0;
+r_llc_loc_ch_map_proc_continue = 0x40000f5c;
+r_llc_loc_con_upd_proc_continue = 0x40000f60;
+r_llc_loc_phy_upd_proc_continue = 0x40000f78;
+r_llc_rem_con_upd_proc_continue = 0x40000fb4;
+r_lld_con_sched = 0x40001118;
+r_lld_con_stop = 0x40001124;
+r_lld_llcp_rx_ind_handler = 0x400011b0;
+r_lld_per_adv_sched = 0x400011f8;
+r_rf_txpwr_cs_get = 0x40001428;
+r_rf_txpwr_dbm_get = 0x4000142c;
+r_sch_arb_event_start_isr = 0x400014f8;
+r_sch_plan_set = 0x40001534;
+r_sch_prog_end_isr = 0x40001538;
+r_lld_adv_ext_chain_scannable_construct = 0x40001b58;
+
+r_lld_scan_process_pkt_rx = 0x40001280;
+r_llm_le_features_get = 0x400013b0;
+
+/* ble functions rename */
+r_lld_init_start_hack = 0x400011a4;
+
+/* ble functions disable */
+/*
+r_lld_adv_frm_isr_eco = 0x40001d00;
+r_lld_res_list_clear = 0x40004638;
+r_lld_res_list_rem = 0x40004680;
+r_lld_adv_start_hook = 0x40001c80;
+r_lld_con_evt_start_cbk_eco = 0x40001d1c;
+r_lld_con_tx_prog_new_packet = 0x40001b74;
+r_lld_adv_ext_chain_none_construct = 0x40001b50;
+r_llc_llcp_send_eco = 0x40001cf4;
+r_llc_llcp_channel_map_ind_ack = 0x40001d68;
+r_rwble_isr = 0x40001464;
+r_lld_scan_start_eco = 0x40001d24;
+r_lld_scan_try_sched_eco = 0x40001dac;
+r_lld_scan_start_hook = 0x40001c74;
+r_lld_init_start_hook = 0x40001cb8;
+r_lld_scan_evt_start_cbk_eco = 0x40001d20;
+r_ke_task_handler_get_overwrite = 0x40001da8;
+r_hci_register_vendor_desc_tab = 0x40000d9c;
+r_lld_scan_process_pkt_rx_adv_rep = 0x40001284;
+r_register_esp_vendor_cmd_handler = 0x40001400;
+r_llc_llcp_pdu_handler_get_overwrite = 0x40001d5c;
+*/
diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld
index 559f5cade6e..33944248095 100644
--- a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld
@@ -366,8 +366,8 @@ ets_get_xtal_freq = 0x40000598;
 gpio_input_get = 0x4000059c;
 gpio_matrix_in = 0x400005a0;
 gpio_matrix_out = 0x400005a4;
-gpio_output_disable = 0x400005a8;
-gpio_output_enable = 0x400005ac;
+/* gpio_output_disable = 0x400005a8; */
+/* gpio_output_enable = 0x400005ac; */
 gpio_output_set = 0x400005b0;
 gpio_pad_hold = 0x400005b4;
 gpio_pad_input_disable = 0x400005b8;
@@ -525,800 +525,6 @@ PROVIDE( g_usb_print = 0x3fcdffd0 );
 /***************************************
  Group bluetooth
  ***************************************/
-
-/* Functions */
-bt_rf_coex_get_dft_cfg = 0x400008dc;
-bt_rf_coex_hooks_p_set = 0x400008e0;
-btdm_con_maxevtime_cal_impl = 0x400008e4;
-btdm_controller_get_compile_version_impl = 0x400008e8;
-btdm_controller_rom_data_init = 0x400008ec;
-btdm_dis_privacy_err_report_impl = 0x400008f0;
-btdm_disable_adv_delay_impl = 0x400008f4;
-btdm_enable_scan_continue_impl = 0x400008f8;
-btdm_enable_scan_forever_impl = 0x400008fc;
-btdm_get_power_state_impl = 0x40000900;
-btdm_get_prevent_sleep_flag_impl = 0x40000904;
-btdm_power_state_active_impl = 0x40000908;
-btdm_switch_phy_coded_impl = 0x4000090c;
-hci_acl_data_handler = 0x40000910;
-hci_disconnect_cmd_handler = 0x40000914;
-hci_le_con_upd_cmd_handler = 0x40000918;
-hci_le_ltk_req_neg_reply_cmd_handler = 0x4000091c;
-hci_le_ltk_req_reply_cmd_handler = 0x40000920;
-hci_le_rd_chnl_map_cmd_handler = 0x40000924;
-hci_le_rd_phy_cmd_handler = 0x40000928;
-hci_le_rd_rem_feats_cmd_handler = 0x4000092c;
-hci_le_rem_con_param_req_neg_reply_cmd_handler = 0x40000930;
-hci_le_rem_con_param_req_reply_cmd_handler = 0x40000934;
-hci_le_set_data_len_cmd_handler = 0x40000938;
-hci_le_set_phy_cmd_handler = 0x4000093c;
-hci_le_start_enc_cmd_handler = 0x40000940;
-hci_rd_auth_payl_to_cmd_handler = 0x40000944;
-hci_rd_rem_ver_info_cmd_handler = 0x40000948;
-hci_rd_rssi_cmd_handler = 0x4000094c;
-hci_rd_tx_pwr_lvl_cmd_handler = 0x40000950;
-hci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40000954;
-hci_vs_set_pref_slave_latency_cmd_handler = 0x40000958;
-hci_wr_auth_payl_to_cmd_handler = 0x4000095c;
-ll_channel_map_ind_handler = 0x40000960;
-ll_connection_param_req_handler = 0x40000964;
-ll_connection_param_rsp_handler = 0x40000968;
-ll_connection_update_ind_handler = 0x4000096c;
-ll_enc_req_handler = 0x40000970;
-ll_enc_rsp_handler = 0x40000974;
-ll_feature_req_handler = 0x40000978;
-ll_feature_rsp_handler = 0x4000097c;
-ll_length_req_handler = 0x40000980;
-ll_length_rsp_handler = 0x40000984;
-ll_min_used_channels_ind_handler = 0x40000988;
-ll_pause_enc_req_handler = 0x4000098c;
-ll_pause_enc_rsp_handler = 0x40000990;
-ll_phy_req_handler = 0x40000994;
-ll_phy_rsp_handler = 0x40000998;
-ll_phy_update_ind_handler = 0x4000099c;
-ll_ping_req_handler = 0x400009a0;
-ll_ping_rsp_handler = 0x400009a4;
-ll_slave_feature_req_handler = 0x400009a8;
-ll_start_enc_req_handler = 0x400009ac;
-ll_start_enc_rsp_handler = 0x400009b0;
-ll_terminate_ind_handler = 0x400009b4;
-ll_version_ind_handler = 0x400009b8;
-llc_auth_payl_nearly_to_handler = 0x400009bc;
-llc_auth_payl_real_to_handler = 0x400009c0;
-llc_encrypt_ind_handler = 0x400009c4;
-llc_hci_command_handler_wrapper = 0x400009c8;
-llc_ll_connection_param_req_pdu_send = 0x400009cc;
-llc_ll_connection_param_rsp_pdu_send = 0x400009d0;
-llc_ll_connection_update_ind_pdu_send = 0x400009d4;
-llc_ll_enc_req_pdu_send = 0x400009d8;
-llc_ll_enc_rsp_pdu_send = 0x400009dc;
-llc_ll_feature_req_pdu_send = 0x400009e0;
-llc_ll_feature_rsp_pdu_send = 0x400009e4;
-llc_ll_length_req_pdu_send = 0x400009e8;
-llc_ll_length_rsp_pdu_send = 0x400009ec;
-llc_ll_pause_enc_req_pdu_send = 0x400009f0;
-llc_ll_pause_enc_rsp_pdu_send = 0x400009f4;
-llc_ll_phy_req_pdu_send = 0x400009f8;
-llc_ll_phy_rsp_pdu_send = 0x400009fc;
-llc_ll_ping_req_pdu_send = 0x40000a00;
-llc_ll_ping_rsp_pdu_send = 0x40000a04;
-llc_ll_start_enc_req_pdu_send = 0x40000a08;
-llc_ll_start_enc_rsp_pdu_send = 0x40000a0c;
-llc_ll_terminate_ind_pdu_send = 0x40000a10;
-llc_ll_unknown_rsp_pdu_send = 0x40000a14;
-llc_llcp_ch_map_update_ind_pdu_send = 0x40000a18;
-llc_llcp_phy_upd_ind_pdu_send = 0x40000a1c;
-llc_llcp_version_ind_pdu_send = 0x40000a20;
-llc_op_ch_map_upd_ind_handler = 0x40000a24;
-llc_op_con_upd_ind_handler = 0x40000a28;
-llc_op_disconnect_ind_handler = 0x40000a2c;
-llc_op_dl_upd_ind_handler = 0x40000a30;
-llc_op_encrypt_ind_handler = 0x40000a34;
-llc_op_feats_exch_ind_handler = 0x40000a38;
-llc_op_le_ping_ind_handler = 0x40000a3c;
-llc_op_phy_upd_ind_handler = 0x40000a40;
-llc_op_ver_exch_ind_handler = 0x40000a44;
-llc_stopped_ind_handler = 0x40000a48;
-lld_acl_rx_ind_handler = 0x40000a4c;
-lld_acl_tx_cfm_handler = 0x40000a50;
-lld_adv_end_ind_handler = 0x40000a54;
-lld_adv_rep_ind_handler = 0x40000a58;
-lld_ch_map_upd_cfm_handler = 0x40000a5c;
-lld_con_estab_ind_handler = 0x40000a60;
-lld_con_evt_sd_evt_time_set = 0x40000a64;
-lld_con_offset_upd_ind_handler = 0x40000a68;
-lld_con_param_upd_cfm_handler = 0x40000a6c;
-lld_disc_ind_handler = 0x40000a70;
-lld_init_end_ind_handler = 0x40000a74;
-lld_llcp_rx_ind_handler_wrapper = 0x40000a78;
-lld_llcp_tx_cfm_handler = 0x40000a7c;
-lld_per_adv_end_ind_handler = 0x40000a80;
-lld_per_adv_rep_ind_handler = 0x40000a84;
-lld_per_adv_rx_end_ind_handler = 0x40000a88;
-lld_phy_coded_500k_get = 0x40000a8c;
-lld_phy_upd_cfm_handler = 0x40000a90;
-lld_scan_end_ind_handler = 0x40000a94;
-lld_scan_req_ind_handler = 0x40000a98;
-lld_sync_start_req_handler = 0x40000a9c;
-lld_test_end_ind_handler = 0x40000aa0;
-lld_update_rxbuf_handler = 0x40000aa4;
-llm_ch_map_update_ind_handler = 0x40000aa8;
-llm_hci_command_handler_wrapper = 0x40000aac;
-llm_scan_period_to_handler = 0x40000ab0;
-r_Add2SelfBigHex256 = 0x40000ab4;
-r_AddBigHex256 = 0x40000ab8;
-r_AddBigHexModP256 = 0x40000abc;
-r_AddP256 = 0x40000ac0;
-r_AddPdiv2_256 = 0x40000ac4;
-r_GF_Jacobian_Point_Addition256 = 0x40000ac8;
-r_GF_Jacobian_Point_Double256 = 0x40000acc;
-r_GF_Point_Jacobian_To_Affine256 = 0x40000ad0;
-r_MultiplyBigHexByUint32_256 = 0x40000ad4;
-r_MultiplyBigHexModP256 = 0x40000ad8;
-r_MultiplyByU16ModP256 = 0x40000adc;
-r_SubtractBigHex256 = 0x40000ae0;
-r_SubtractBigHexMod256 = 0x40000ae4;
-r_SubtractBigHexUint32_256 = 0x40000ae8;
-r_SubtractFromSelfBigHex256 = 0x40000aec;
-r_SubtractFromSelfBigHexSign256 = 0x40000af0;
-r_aes_alloc = 0x40000af4;
-r_aes_ccm_continue = 0x40000af8;
-r_aes_ccm_process_e = 0x40000afc;
-r_aes_ccm_xor_128_lsb = 0x40000b00;
-r_aes_ccm_xor_128_msb = 0x40000b04;
-r_aes_cmac_continue = 0x40000b08;
-r_aes_cmac_start = 0x40000b0c;
-r_aes_k1_continue = 0x40000b10;
-r_aes_k2_continue = 0x40000b14;
-r_aes_k3_continue = 0x40000b18;
-r_aes_k4_continue = 0x40000b1c;
-r_aes_shift_left_128 = 0x40000b20;
-r_aes_start = 0x40000b24;
-r_aes_xor_128 = 0x40000b28;
-r_assert_err = 0x40000b2c;
-r_assert_param = 0x40000b30;
-r_assert_warn = 0x40000b34;
-r_bigHexInversion256 = 0x40000b38;
-r_ble_sw_cca_check_isr = 0x40000b3c;
-r_ble_util_buf_acl_tx_alloc = 0x40000b40;
-r_ble_util_buf_acl_tx_elt_get = 0x40000b44;
-r_ble_util_buf_acl_tx_free = 0x40000b48;
-r_ble_util_buf_acl_tx_free_in_isr = 0x40000b4c;
-r_ble_util_buf_adv_tx_alloc = 0x40000b50;
-r_ble_util_buf_adv_tx_free = 0x40000b54;
-r_ble_util_buf_adv_tx_free_in_isr = 0x40000b58;
-r_ble_util_buf_env_deinit = 0x40000b5c;
-r_ble_util_buf_env_init = 0x40000b60;
-r_ble_util_buf_get_rx_buf_nb = 0x40000b64;
-r_ble_util_buf_get_rx_buf_size = 0x40000b68;
-r_ble_util_buf_llcp_tx_alloc = 0x40000b6c;
-r_ble_util_buf_llcp_tx_free = 0x40000b70;
-r_ble_util_buf_rx_alloc = 0x40000b74;
-r_ble_util_buf_rx_alloc_in_isr = 0x40000b78;
-r_ble_util_buf_rx_free = 0x40000b7c;
-r_ble_util_buf_rx_free_in_isr = 0x40000b80;
-r_ble_util_buf_set_rx_buf_nb = 0x40000b84;
-r_ble_util_buf_set_rx_buf_size = 0x40000b88;
-r_ble_util_data_rx_buf_reset = 0x40000b8c;
-r_bt_bb_get_intr_mask = 0x40000b90;
-r_bt_bb_intr_clear = 0x40000b94;
-r_bt_bb_intr_mask_set = 0x40000b98;
-r_bt_rf_coex_cfg_set = 0x40000ba0;
-r_bt_rf_coex_conn_dynamic_pti_en_get = 0x40000ba4;
-r_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x40000bac;
-r_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x40000bb0;
-r_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40000bb4;
-r_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x40000bb8;
-r_bt_rf_coex_pti_table_get = 0x40000bbc;
-r_bt_rf_coex_st_param_get = 0x40000bc0;
-r_bt_rf_coex_st_param_set = 0x40000bc4;
-r_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x40000bc8;
-r_bt_rma_apply_rule_cs_fmt = 0x40000bcc;
-r_bt_rma_apply_rule_cs_idx = 0x40000bd0;
-r_bt_rma_configure = 0x40000bd4;
-r_bt_rma_deregister_rule_cs_fmt = 0x40000bd8;
-r_bt_rma_deregister_rule_cs_idx = 0x40000bdc;
-r_bt_rma_get_ant_by_act = 0x40000be0;
-r_bt_rma_init = 0x40000be4;
-r_bt_rma_register_rule_cs_fmt = 0x40000be8;
-r_bt_rma_register_rule_cs_idx = 0x40000bec;
-r_bt_rtp_apply_rule_cs_fmt = 0x40000bf0;
-r_bt_rtp_apply_rule_cs_idx = 0x40000bf4;
-r_bt_rtp_deregister_rule_cs_fmt = 0x40000bf8;
-r_bt_rtp_deregister_rule_cs_idx = 0x40000bfc;
-r_bt_rtp_init = 0x40000c04;
-r_bt_rtp_register_rule_cs_fmt = 0x40000c08;
-r_bt_rtp_register_rule_cs_idx = 0x40000c0c;
-r_btdm_isr = 0x40000c10;
-r_cali_phase_match_p = 0x40000c20;
-r_cmp_abs_time = 0x40000c24;
-r_cmp_dest_id = 0x40000c28;
-r_cmp_timer_id = 0x40000c2c;
-r_co_bdaddr_compare = 0x40000c30;
-r_co_ble_pkt_dur_in_us = 0x40000c34;
-r_co_list_extract = 0x40000c38;
-r_co_list_extract_after = 0x40000c3c;
-r_co_list_extract_sublist = 0x40000c40;
-r_co_list_find = 0x40000c44;
-r_co_list_init = 0x40000c48;
-r_co_list_insert_after = 0x40000c4c;
-r_co_list_insert_before = 0x40000c50;
-r_co_list_merge = 0x40000c54;
-r_co_list_pool_init = 0x40000c58;
-r_co_list_pop_front = 0x40000c5c;
-r_co_list_push_back = 0x40000c60;
-r_co_list_push_back_sublist = 0x40000c64;
-r_co_list_push_front = 0x40000c68;
-r_co_list_size = 0x40000c6c;
-r_co_nb_good_le_channels = 0x40000c70;
-r_co_util_pack = 0x40000c74;
-r_co_util_read_array_size = 0x40000c78;
-r_co_util_unpack = 0x40000c7c;
-r_dbg_env_deinit = 0x40000c80;
-r_dbg_env_init = 0x40000c84;
-r_dbg_platform_reset_complete = 0x40000c88;
-r_dl_upd_proc_start = 0x40000c8c;
-r_dump_data = 0x40000c90;
-r_ecc_abort_key256_generation = 0x40000c94;
-r_ecc_gen_new_public_key = 0x40000c98;
-r_ecc_gen_new_secret_key = 0x40000c9c;
-r_ecc_generate_key256 = 0x40000ca0;
-r_ecc_get_debug_Keys = 0x40000ca4;
-r_ecc_init = 0x40000ca8;
-r_ecc_is_valid_point = 0x40000cac;
-r_ecc_multiplication_event_handler = 0x40000cb0;
-r_ecc_point_multiplication_win_256 = 0x40000cb4;
-r_emi_alloc_em_mapping_by_offset = 0x40000cb8;
-r_emi_base_reg_lut_show = 0x40000cbc;
-r_emi_em_base_reg_show = 0x40000cc0;
-r_emi_free_em_mapping_by_offset = 0x40000cc4;
-r_emi_get_em_mapping_idx_by_offset = 0x40000cc8;
-r_emi_get_mem_addr_by_offset = 0x40000ccc;
-r_emi_overwrite_em_mapping_by_offset = 0x40000cd0;
-r_esp_vendor_hci_command_handler = 0x40000cd4;
-r_get_stack_usage = 0x40000cd8;
-r_h4tl_acl_hdr_rx_evt_handler = 0x40000cdc;
-r_h4tl_cmd_hdr_rx_evt_handler = 0x40000ce0;
-r_h4tl_cmd_pld_rx_evt_handler = 0x40000ce4;
-r_h4tl_eif_io_event_post = 0x40000ce8;
-r_h4tl_eif_register = 0x40000cec;
-r_h4tl_init = 0x40000cf0;
-r_h4tl_out_of_sync = 0x40000cf4;
-r_h4tl_out_of_sync_check = 0x40000cf8;
-r_h4tl_read_hdr = 0x40000cfc;
-r_h4tl_read_next_out_of_sync = 0x40000d00;
-r_h4tl_read_payl = 0x40000d04;
-r_h4tl_read_start = 0x40000d08;
-r_h4tl_rx_acl_hdr_extract = 0x40000d0c;
-r_h4tl_rx_cmd_hdr_extract = 0x40000d10;
-r_h4tl_rx_done = 0x40000d14;
-r_h4tl_start = 0x40000d18;
-r_h4tl_stop = 0x40000d1c;
-r_h4tl_tx_done = 0x40000d20;
-r_h4tl_tx_evt_handler = 0x40000d24;
-r_h4tl_write = 0x40000d28;
-r_hci_acl_tx_data_alloc = 0x40000d2c;
-r_hci_acl_tx_data_received = 0x40000d30;
-r_hci_basic_cmd_send_2_controller = 0x40000d34;
-r_hci_ble_adv_report_filter_check = 0x40000d38;
-r_hci_ble_adv_report_tx_check = 0x40000d3c;
-r_hci_ble_conhdl_register = 0x40000d40;
-r_hci_ble_conhdl_unregister = 0x40000d44;
-r_hci_build_acl_data = 0x40000d48;
-r_hci_build_cc_evt = 0x40000d4c;
-r_hci_build_cs_evt = 0x40000d50;
-r_hci_build_evt = 0x40000d54;
-r_hci_build_le_evt = 0x40000d58;
-r_hci_cmd_get_max_param_size = 0x40000d5c;
-r_hci_cmd_received = 0x40000d60;
-r_hci_cmd_reject = 0x40000d64;
-r_hci_evt_mask_check = 0x40000d68;
-r_hci_evt_mask_set = 0x40000d6c;
-r_hci_fc_acl_buf_size_set = 0x40000d70;
-r_hci_fc_acl_en = 0x40000d74;
-r_hci_fc_acl_packet_sent = 0x40000d78;
-r_hci_fc_check_host_available_nb_acl_packets = 0x40000d7c;
-r_hci_fc_host_nb_acl_pkts_complete = 0x40000d80;
-r_hci_fc_init = 0x40000d84;
-r_hci_look_for_cmd_desc = 0x40000d88;
-r_hci_look_for_evt_desc = 0x40000d8c;
-r_hci_look_for_le_evt_desc = 0x40000d90;
-r_hci_look_for_le_evt_desc_esp = 0x40000d94;
-r_hci_pack_bytes = 0x40000d98;
-r_hci_send_2_controller = 0x40000da0;
-r_hci_send_2_host = 0x40000da4;
-r_hci_tl_c2h_data_flow_on = 0x40000da8;
-r_hci_tl_cmd_hdr_rx_evt_handler = 0x40000dac;
-r_hci_tl_cmd_pld_rx_evt_handler = 0x40000db0;
-r_hci_tl_get_pkt = 0x40000db4;
-r_hci_tl_hci_pkt_handler = 0x40000db8;
-r_hci_tl_hci_tx_done_evt_handler = 0x40000dbc;
-r_hci_tl_inc_nb_h2c_cmd_pkts = 0x40000dc0;
-r_hci_tl_save_pkt = 0x40000dc4;
-r_hci_tl_send = 0x40000dc8;
-r_hci_tx_done = 0x40000dcc;
-r_hci_tx_start = 0x40000dd0;
-r_hci_tx_trigger = 0x40000dd4;
-r_isValidSecretKey_256 = 0x40000dd8;
-r_ke_check_malloc = 0x40000ddc;
-r_ke_event_callback_set = 0x40000de0;
-r_ke_event_clear = 0x40000de4;
-r_ke_event_flush = 0x40000de8;
-r_ke_event_get = 0x40000dec;
-r_ke_event_get_all = 0x40000df0;
-r_ke_event_init = 0x40000df4;
-r_ke_event_schedule = 0x40000df8;
-r_ke_event_set = 0x40000dfc;
-r_ke_flush = 0x40000e00;
-r_ke_free = 0x40000e04;
-r_ke_handler_search = 0x40000e08;
-r_ke_init = 0x40000e0c;
-r_ke_is_free = 0x40000e10;
-r_ke_malloc = 0x40000e14;
-r_ke_mem_init = 0x40000e18;
-r_ke_mem_is_empty = 0x40000e1c;
-r_ke_mem_is_in_heap = 0x40000e20;
-r_ke_msg_alloc = 0x40000e24;
-r_ke_msg_dest_id_get = 0x40000e28;
-r_ke_msg_discard = 0x40000e2c;
-r_ke_msg_forward = 0x40000e30;
-r_ke_msg_forward_new_id = 0x40000e34;
-r_ke_msg_free = 0x40000e38;
-r_ke_msg_in_queue = 0x40000e3c;
-r_ke_msg_save = 0x40000e40;
-r_ke_msg_send = 0x40000e44;
-r_ke_msg_send_basic = 0x40000e48;
-r_ke_msg_src_id_get = 0x40000e4c;
-r_ke_queue_extract = 0x40000e50;
-r_ke_queue_insert = 0x40000e54;
-r_ke_sleep_check = 0x40000e58;
-r_ke_state_get = 0x40000e5c;
-r_ke_state_set = 0x40000e60;
-r_ke_task_check = 0x40000e64;
-r_ke_task_create = 0x40000e68;
-r_ke_task_delete = 0x40000e6c;
-r_ke_task_handler_get = 0x40000e70;
-r_ke_task_init = 0x40000e74;
-r_ke_task_msg_flush = 0x40000e78;
-r_ke_task_saved_update = 0x40000e7c;
-r_ke_time = 0x40000e84;
-r_ke_time_cmp = 0x40000e88;
-r_ke_time_past = 0x40000e8c;
-r_ke_timer_active = 0x40000e90;
-r_ke_timer_adjust_all = 0x40000e94;
-r_ke_timer_clear = 0x40000e98;
-r_ke_timer_init = 0x40000e9c;
-r_ke_timer_schedule = 0x40000ea0;
-r_ke_timer_set = 0x40000ea4;
-r_led_init = 0x40000ea8;
-r_led_set_all = 0x40000eac;
-r_llc_aes_res_cb = 0x40000eb0;
-r_llc_ch_map_up_proc_err_cb = 0x40000eb4;
-r_llc_cleanup = 0x40000eb8;
-r_llc_cmd_cmp_send = 0x40000ebc;
-r_llc_cmd_stat_send = 0x40000ec0;
-r_llc_con_move_cbk = 0x40000ec4;
-r_llc_con_plan_set_update = 0x40000ec8;
-r_llc_con_upd_param_in_range = 0x40000ecc;
-r_llc_disconnect = 0x40000ed0;
-r_llc_disconnect_end = 0x40000ed4;
-r_llc_disconnect_proc_continue = 0x40000ed8;
-r_llc_disconnect_proc_err_cb = 0x40000edc;
-r_llc_dl_chg_check = 0x40000ee0;
-r_llc_dle_proc_err_cb = 0x40000ee4;
-r_llc_feats_exch_proc_err_cb = 0x40000ee8;
-r_llc_hci_cmd_handler_tab_p_get = 0x40000eec;
-r_llc_hci_con_param_req_evt_send = 0x40000ef4;
-r_llc_hci_con_upd_info_send = 0x40000ef8;
-r_llc_hci_disconnected_dis = 0x40000efc;
-r_llc_hci_dl_upd_info_send = 0x40000f00;
-r_llc_hci_enc_evt_send = 0x40000f04;
-r_llc_hci_feats_info_send = 0x40000f08;
-r_llc_hci_le_phy_upd_cmp_evt_send = 0x40000f0c;
-r_llc_hci_ltk_request_evt_send = 0x40000f10;
-r_llc_hci_nb_cmp_pkts_evt_send = 0x40000f14;
-r_llc_hci_version_info_send = 0x40000f18;
-r_llc_init_term_proc = 0x40000f1c;
-r_llc_iv_skd_rand_gen = 0x40000f20;
-r_llc_le_ping_proc_continue = 0x40000f24;
-r_llc_le_ping_proc_err_cb = 0x40000f28;
-/* r_llc_le_ping_restart = 0x40000f2c; */
-r_llc_le_ping_set = 0x40000f30;
-r_llc_ll_pause_enc_rsp_ack_handler = 0x40000f34;
-r_llc_ll_reject_ind_ack_handler = 0x40000f38;
-r_llc_ll_reject_ind_pdu_send = 0x40000f3c;
-r_llc_ll_start_enc_rsp_ack_handler = 0x40000f40;
-r_llc_ll_terminate_ind_ack = 0x40000f44;
-r_llc_ll_unknown_ind_handler = 0x40000f48;
-r_llc_llcp_send = 0x40000f4c;
-r_llc_llcp_state_set = 0x40000f50;
-r_llc_llcp_trans_timer_set = 0x40000f54;
-r_llc_llcp_tx_check = 0x40000f58;
-r_llc_loc_con_upd_proc_err_cb = 0x40000f64;
-r_llc_loc_dl_upd_proc_continue = 0x40000f68;
-r_llc_loc_encrypt_proc_continue = 0x40000f6c;
-r_llc_loc_encrypt_proc_err_cb = 0x40000f70;
-r_llc_loc_feats_exch_proc_continue = 0x40000f74;
-r_llc_loc_phy_upd_proc_err_cb = 0x40000f7c;
-r_llc_msg_handler_tab_p_get = 0x40000f80;
-r_llc_pref_param_compute = 0x40000f84;
-r_llc_proc_collision_check = 0x40000f88;
-r_llc_proc_err_ind = 0x40000f8c;
-r_llc_proc_get = 0x40000f90;
-r_llc_proc_id_get = 0x40000f94;
-r_llc_proc_reg = 0x40000f98;
-r_llc_proc_state_get = 0x40000f9c;
-r_llc_proc_state_set = 0x40000fa0;
-r_llc_proc_timer_pause_set = 0x40000fa4;
-r_llc_proc_timer_set = 0x40000fa8;
-r_llc_proc_unreg = 0x40000fac;
-r_llc_rem_ch_map_proc_continue = 0x40000fb0;
-r_llc_rem_con_upd_proc_err_cb = 0x40000fb8;
-r_llc_rem_dl_upd_proc = 0x40000fbc;
-r_llc_rem_encrypt_proc_continue = 0x40000fc0;
-r_llc_rem_encrypt_proc_err_cb = 0x40000fc4;
-r_llc_rem_phy_upd_proc_continue = 0x40000fc8;
-r_llc_rem_phy_upd_proc_err_cb = 0x40000fcc;
-r_llc_role_get = 0x40000fd0;
-r_llc_sk_gen = 0x40000fd4;
-r_llc_start = 0x40000fd8;
-r_llc_stop = 0x40000fdc;
-r_llc_ver_exch_loc_proc_continue = 0x40000fe0;
-r_llc_ver_proc_err_cb = 0x40000fe4;
-r_llcp_pdu_handler_tab_p_get = 0x40000fe8;
-r_lld_aa_gen = 0x40000fec;
-r_lld_adv_adv_data_set = 0x40000ff0;
-r_lld_adv_adv_data_update = 0x40000ff4;
-r_lld_adv_aux_ch_idx_set = 0x40000ff8;
-r_lld_adv_aux_evt_canceled_cbk = 0x40000ffc;
-r_lld_adv_aux_evt_start_cbk = 0x40001000;
-r_lld_adv_coex_check_ext_adv_synced = 0x40001004;
-r_lld_adv_coex_env_reset = 0x40001008;
-r_lld_adv_duration_update = 0x4000100c;
-r_lld_adv_dynamic_pti_process = 0x40001010;
-r_lld_adv_end = 0x40001014;
-r_lld_adv_evt_canceled_cbk = 0x40001018;
-r_lld_adv_evt_start_cbk = 0x4000101c;
-r_lld_adv_ext_chain_construct = 0x40001020;
-r_lld_adv_ext_pkt_prepare = 0x40001024;
-r_lld_adv_frm_cbk = 0x40001028;
-r_lld_adv_frm_isr = 0x4000102c;
-r_lld_adv_frm_skip_isr = 0x40001030;
-r_lld_adv_init = 0x40001034;
-r_lld_adv_pkt_rx = 0x40001038;
-r_lld_adv_pkt_rx_connect_ind = 0x4000103c;
-r_lld_adv_pkt_rx_send_scan_req_evt = 0x40001040;
-r_lld_adv_rand_addr_update = 0x40001044;
-r_lld_adv_restart = 0x40001048;
-r_lld_adv_scan_rsp_data_set = 0x4000104c;
-r_lld_adv_scan_rsp_data_update = 0x40001050;
-r_lld_adv_set_tx_power = 0x40001054;
-r_lld_adv_start = 0x40001058;
-r_lld_adv_stop = 0x4000105c;
-r_lld_adv_sync_info_set = 0x40001060;
-r_lld_adv_sync_info_update = 0x40001064;
-r_lld_calc_aux_rx = 0x40001068;
-r_lld_cca_alloc = 0x4000106c;
-r_lld_cca_data_reset = 0x40001070;
-r_lld_cca_free = 0x40001074;
-r_lld_ch_assess_data_get = 0x40001078;
-r_lld_ch_idx_get = 0x4000107c;
-r_lld_ch_map_set = 0x40001080;
-r_lld_channel_assess = 0x40001084;
-r_lld_con_activity_act_offset_compute = 0x40001088;
-r_lld_con_activity_offset_compute = 0x4000108c;
-r_lld_con_ch_map_update = 0x40001090;
-r_lld_con_cleanup = 0x40001094;
-r_lld_con_current_tx_power_get = 0x40001098;
-r_lld_con_data_flow_set = 0x4000109c;
-r_lld_con_data_len_update = 0x400010a0;
-r_lld_con_data_tx = 0x400010a4;
-r_lld_con_enc_key_load = 0x400010a8;
-r_lld_con_event_counter_get = 0x400010ac;
-r_lld_con_evt_canceled_cbk = 0x400010b0;
-r_lld_con_evt_duration_min_get = 0x400010b4;
-r_lld_con_evt_max_eff_time_cal = 0x400010b8;
-r_lld_con_evt_sd_evt_time_get = 0x400010bc;
-r_lld_con_evt_start_cbk = 0x400010c0;
-r_lld_con_evt_time_update = 0x400010c4;
-r_lld_con_free_all_tx_buf = 0x400010c8;
-r_lld_con_frm_cbk = 0x400010cc;
-r_lld_con_frm_isr = 0x400010d0;
-r_lld_con_frm_skip_isr = 0x400010d4;
-r_lld_con_init = 0x400010d8;
-r_lld_con_llcp_tx = 0x400010dc;
-r_lld_con_max_lat_calc = 0x400010e0;
-r_lld_con_offset_get = 0x400010e4;
-r_lld_con_param_update = 0x400010e8;
-r_lld_con_phys_update = 0x400010ec;
-r_lld_con_pref_slave_evt_dur_set = 0x400010f0;
-r_lld_con_pref_slave_latency_set = 0x400010f4;
-r_lld_con_rssi_get = 0x400010f8;
-r_lld_con_rx = 0x400010fc;
-/* r_lld_con_rx_channel_assess = 0x40001100; */
-r_lld_con_rx_enc = 0x40001104;
-r_lld_con_rx_isr = 0x40001108;
-r_lld_con_rx_link_info_check = 0x4000110c;
-r_lld_con_rx_llcp_check = 0x40001110;
-r_lld_con_rx_sync_time_update = 0x40001114;
-r_lld_con_set_tx_power = 0x4000111c;
-r_lld_con_start = 0x40001120;
-r_lld_con_tx = 0x40001128;
-r_lld_con_tx_enc = 0x4000112c;
-r_lld_con_tx_isr = 0x40001130;
-r_lld_con_tx_len_update = 0x40001134;
-r_lld_con_tx_len_update_for_intv = 0x40001138;
-r_lld_con_tx_len_update_for_rate = 0x4000113c;
-r_lld_con_tx_prog = 0x40001140;
-r_lld_conn_dynamic_pti_process = 0x40001144;
-r_lld_continue_scan_rx_isr_end_process = 0x40001148;
-r_lld_ext_scan_dynamic_pti_process = 0x4000114c;
-r_lld_hw_cca_end_isr = 0x40001150;
-r_lld_hw_cca_evt_handler = 0x40001154;
-r_lld_hw_cca_isr = 0x40001158;
-r_lld_init_cal_anchor_point = 0x4000115c;
-r_lld_init_compute_winoffset = 0x40001160;
-r_lld_init_connect_req_pack = 0x40001164;
-r_lld_init_end = 0x40001168;
-r_lld_init_evt_canceled_cbk = 0x4000116c;
-r_lld_init_evt_start_cbk = 0x40001170;
-r_lld_init_frm_cbk = 0x40001174;
-r_lld_init_frm_eof_isr = 0x40001178;
-r_lld_init_frm_skip_isr = 0x4000117c;
-r_lld_init_init = 0x40001180;
-r_lld_init_process_pkt_rx = 0x40001184;
-r_lld_init_process_pkt_rx_adv_ext_ind = 0x40001188;
-r_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x4000118c;
-r_lld_init_process_pkt_rx_aux_connect_rsp = 0x40001190;
-r_lld_init_process_pkt_tx = 0x40001194;
-r_lld_init_process_pkt_tx_cal_con_timestamp = 0x40001198;
-r_lld_init_sched = 0x4000119c;
-r_lld_init_set_tx_power = 0x400011a0;
-r_lld_init_start = 0x400011a4;
-r_lld_init_stop = 0x400011a8;
-r_lld_instant_proc_end = 0x400011ac;
-r_lld_per_adv_ch_map_update = 0x400011b4;
-r_lld_per_adv_chain_construct = 0x400011b8;
-r_lld_per_adv_cleanup = 0x400011bc;
-r_lld_per_adv_coex_env_reset = 0x400011c0;
-r_lld_per_adv_data_set = 0x400011c4;
-r_lld_per_adv_data_update = 0x400011c8;
-r_lld_per_adv_dynamic_pti_process = 0x400011cc;
-r_lld_per_adv_evt_canceled_cbk = 0x400011d0;
-r_lld_per_adv_evt_start_cbk = 0x400011d4;
-r_lld_per_adv_ext_pkt_prepare = 0x400011d8;
-r_lld_per_adv_frm_cbk = 0x400011dc;
-r_lld_per_adv_frm_isr = 0x400011e0;
-r_lld_per_adv_frm_skip_isr = 0x400011e4;
-r_lld_per_adv_init = 0x400011e8;
-r_lld_per_adv_init_info_get = 0x400011ec;
-r_lld_per_adv_list_add = 0x400011f0;
-r_lld_per_adv_list_rem = 0x400011f4;
-r_lld_per_adv_set_tx_power = 0x400011fc;
-r_lld_per_adv_start = 0x40001200;
-r_lld_per_adv_stop = 0x40001204;
-r_lld_per_adv_sync_info_get = 0x40001208;
-r_lld_process_cca_data = 0x4000120c;
-r_lld_ral_search = 0x40001210;
-r_lld_read_clock = 0x40001214;
-r_lld_res_list_add = 0x40001218;
-r_lld_res_list_is_empty = 0x40001220;
-r_lld_res_list_local_rpa_get = 0x40001224;
-r_lld_res_list_peer_rpa_get = 0x40001228;
-r_lld_res_list_peer_update = 0x4000122c;
-/* r_lld_res_list_priv_mode_update = 0x40001230; */
-r_lld_reset_reg = 0x40001238;
-r_lld_rpa_renew = 0x4000123c;
-r_lld_rpa_renew_evt_canceled_cbk = 0x40001240;
-r_lld_rpa_renew_evt_start_cbk = 0x40001244;
-r_lld_rpa_renew_instant_cbk = 0x40001248;
-r_lld_rxdesc_check = 0x4000124c;
-r_lld_rxdesc_free = 0x40001250;
-r_lld_scan_create_sync = 0x40001254;
-r_lld_scan_create_sync_cancel = 0x40001258;
-r_lld_scan_end = 0x4000125c;
-r_lld_scan_evt_canceled_cbk = 0x40001260;
-r_lld_scan_evt_start_cbk = 0x40001264;
-r_lld_scan_frm_cbk = 0x40001268;
-r_lld_scan_frm_eof_isr = 0x4000126c;
-r_lld_scan_frm_rx_isr = 0x40001270;
-r_lld_scan_frm_skip_isr = 0x40001274;
-r_lld_scan_init = 0x40001278;
-r_lld_scan_params_update = 0x4000127c;
-r_lld_scan_process_pkt_rx_aux_adv_ind = 0x40001288;
-r_lld_scan_process_pkt_rx_aux_chain_ind = 0x4000128c;
-r_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40001290;
-r_lld_scan_process_pkt_rx_ext_adv = 0x40001294;
-r_lld_scan_process_pkt_rx_ext_adv_ind = 0x40001298;
-r_lld_scan_process_pkt_rx_legacy_adv = 0x4000129c;
-r_lld_scan_restart = 0x400012a0;
-r_lld_scan_sched = 0x400012a4;
-r_lld_scan_set_tx_power = 0x400012a8;
-r_lld_scan_start = 0x400012ac;
-r_lld_scan_stop = 0x400012b0;
-r_lld_scan_sync_accept = 0x400012b4;
-r_lld_scan_sync_info_unpack = 0x400012b8;
-r_lld_scan_trunc_ind = 0x400012bc;
-r_lld_sw_cca_evt_handler = 0x400012c0;
-r_lld_sw_cca_isr = 0x400012c4;
-r_lld_sync_ch_map_update = 0x400012c8;
-r_lld_sync_cleanup = 0x400012cc;
-r_lld_sync_evt_canceled_cbk = 0x400012d0;
-r_lld_sync_evt_start_cbk = 0x400012d4;
-r_lld_sync_frm_cbk = 0x400012d8;
-r_lld_sync_frm_eof_isr = 0x400012dc;
-r_lld_sync_frm_rx_isr = 0x400012e0;
-r_lld_sync_frm_skip_isr = 0x400012e4;
-r_lld_sync_init = 0x400012e8;
-r_lld_sync_process_pkt_rx = 0x400012ec;
-r_lld_sync_process_pkt_rx_aux_sync_ind = 0x400012f0;
-r_lld_sync_process_pkt_rx_pkt_check = 0x400012f4;
-r_lld_sync_scan_dynamic_pti_process = 0x400012f8;
-r_lld_sync_sched = 0x400012fc;
-r_lld_sync_start = 0x40001300;
-r_lld_sync_stop = 0x40001304;
-r_lld_sync_trunc_ind = 0x40001308;
-r_lld_test_cleanup = 0x4000130c;
-r_lld_test_evt_canceled_cbk = 0x40001310;
-r_lld_test_evt_start_cbk = 0x40001314;
-r_lld_test_freq2chnl = 0x40001318;
-r_lld_test_frm_cbk = 0x4000131c;
-r_lld_test_frm_isr = 0x40001320;
-r_lld_test_init = 0x40001324;
-r_lld_test_rx_isr = 0x40001328;
-r_lld_test_set_tx_power = 0x4000132c;
-r_lld_test_start = 0x40001330;
-/* r_lld_test_stop = 0x40001334; */
-r_lld_update_rxbuf = 0x40001338;
-r_lld_update_rxbuf_isr = 0x4000133c;
-r_lld_white_list_add = 0x40001340;
-r_lld_white_list_rem = 0x40001344;
-r_llm_activity_free_get = 0x40001348;
-r_llm_activity_free_set = 0x4000134c;
-r_llm_activity_syncing_get = 0x40001350;
-r_llm_adv_con_len_check = 0x40001354;
-r_llm_adv_hdl_to_id = 0x40001358;
-r_llm_adv_rep_flow_control_check = 0x4000135c;
-r_llm_adv_rep_flow_control_update = 0x40001360;
-r_llm_adv_reports_list_check = 0x40001364;
-r_llm_adv_set_all_release = 0x40001368;
-r_llm_adv_set_dft_params = 0x4000136c;
-r_llm_adv_set_release = 0x40001370;
-r_llm_aes_res_cb = 0x40001374;
-r_llm_ble_update_adv_flow_control = 0x40001378;
-r_llm_ch_map_update = 0x4000137c;
-r_llm_cmd_cmp_send = 0x40001380;
-r_llm_cmd_stat_send = 0x40001384;
-r_llm_dev_list_empty_entry = 0x40001388;
-r_llm_dev_list_search = 0x4000138c;
-r_llm_env_adv_dup_filt_deinit = 0x40001390;
-r_llm_env_adv_dup_filt_init = 0x40001394;
-r_llm_init_ble_adv_report_flow_contol = 0x40001398;
-r_llm_is_dev_connected = 0x4000139c;
-r_llm_is_dev_synced = 0x400013a0;
-r_llm_is_non_con_act_ongoing_check = 0x400013a4;
-r_llm_is_wl_accessible = 0x400013a8;
-r_llm_le_evt_mask_check = 0x400013ac;
-r_llm_link_disc = 0x400013b4;
-r_llm_master_ch_map_get = 0x400013b8;
-r_llm_msg_handler_tab_p_get = 0x400013bc;
-r_llm_no_activity = 0x400013c0;
-r_llm_per_adv_slot_dur = 0x400013c4;
-r_llm_plan_elt_get = 0x400013c8;
-r_llm_rx_path_comp_get = 0x400013cc;
-r_llm_scan_start = 0x400013d0;
-r_llm_scan_sync_acad_attach = 0x400013d4;
-r_llm_scan_sync_acad_detach = 0x400013d8;
-r_llm_send_adv_lost_event_to_host = 0x400013dc;
-r_llm_tx_path_comp_get = 0x400013e0;
-r_misc_deinit = 0x400013e4;
-r_misc_free_em_buf_in_isr = 0x400013e8;
-r_misc_init = 0x400013ec;
-r_misc_msg_handler_tab_p_get = 0x400013f0;
-r_notEqual256 = 0x400013f4;
-r_phy_upd_proc_start = 0x400013f8;
-r_platform_reset = 0x400013fc;
-r_rf_em_init = 0x40001404;
-r_rf_force_agc_enable = 0x40001408;
-r_rf_reg_rd = 0x4000140c;
-r_rf_reg_wr = 0x40001410;
-r_rf_reset = 0x40001414;
-r_rf_rssi_convert = 0x40001418;
-r_rf_rw_v9_le_disable = 0x4000141c;
-r_rf_rw_v9_le_enable = 0x40001420;
-r_rf_sleep = 0x40001424;
-r_rf_util_cs_fmt_convert = 0x40001430;
-r_rw_crypto_aes_ccm = 0x40001434;
-r_rw_crypto_aes_encrypt = 0x40001438;
-r_rw_crypto_aes_init = 0x4000143c;
-r_rw_crypto_aes_k1 = 0x40001440;
-r_rw_crypto_aes_k2 = 0x40001444;
-r_rw_crypto_aes_k3 = 0x40001448;
-r_rw_crypto_aes_k4 = 0x4000144c;
-r_rw_crypto_aes_rand = 0x40001450;
-r_rw_crypto_aes_result_handler = 0x40001454;
-r_rw_crypto_aes_s1 = 0x40001458;
-r_rw_cryto_aes_cmac = 0x4000145c;
-r_rw_v9_init_em_radio_table = 0x40001460;
-r_rwble_sleep_enter = 0x40001468;
-r_rwble_sleep_wakeup_end = 0x4000146c;
-/* r_rwbtdm_isr_wrapper = 0x40001470; */
-r_rwip_active_check = 0x40001474;
-r_rwip_aes_encrypt = 0x40001478;
-/* r_rwip_assert = 0x4000147c; */
-r_rwip_crypt_evt_handler = 0x40001480;
-r_rwip_crypt_isr_handler = 0x40001484;
-r_rwip_eif_get = 0x40001488;
-r_rwip_half_slot_2_lpcycles = 0x4000148c;
-r_rwip_hus_2_lpcycles = 0x40001490;
-r_rwip_isr = 0x40001494;
-r_rwip_lpcycles_2_hus = 0x40001498;
-r_rwip_prevent_sleep_clear = 0x4000149c;
-r_rwip_prevent_sleep_set = 0x400014a0;
-r_rwip_schedule = 0x400014a4;
-r_rwip_sleep = 0x400014a8;
-r_rwip_sw_int_handler = 0x400014ac;
-r_rwip_sw_int_req = 0x400014b0;
-r_rwip_time_get = 0x400014b4;
-r_rwip_timer_10ms_handler = 0x400014b8;
-r_rwip_timer_10ms_set = 0x400014bc;
-r_rwip_timer_hs_handler = 0x400014c0;
-r_rwip_timer_hs_set = 0x400014c4;
-r_rwip_timer_hus_handler = 0x400014c8;
-r_rwip_timer_hus_set = 0x400014cc;
-r_rwip_wakeup = 0x400014d0;
-/* r_rwip_wakeup_end = 0x400014d4; */
-r_rwip_wlcoex_set = 0x400014d8;
-r_sch_alarm_clear = 0x400014dc;
-r_sch_alarm_init = 0x400014e0;
-r_sch_alarm_prog = 0x400014e4;
-r_sch_alarm_set = 0x400014e8;
-r_sch_alarm_timer_isr = 0x400014ec;
-r_sch_arb_conflict_check = 0x400014f0;
-r_sch_arb_elt_cancel = 0x400014f4;
-r_sch_arb_init = 0x400014fc;
-r_sch_arb_insert = 0x40001500;
-r_sch_arb_prog_timer = 0x40001504;
-r_sch_arb_remove = 0x40001508;
-r_sch_arb_sw_isr = 0x4000150c;
-r_sch_plan_chk = 0x40001510;
-r_sch_plan_clock_wrap_offset_update = 0x40001514;
-r_sch_plan_init = 0x40001518;
-r_sch_plan_interval_req = 0x4000151c;
-r_sch_plan_offset_max_calc = 0x40001520;
-r_sch_plan_offset_req = 0x40001524;
-r_sch_plan_position_range_compute = 0x40001528;
-r_sch_plan_rem = 0x4000152c;
-r_sch_plan_req = 0x40001530;
-r_sch_prog_init = 0x4000153c;
-r_sch_prog_push = 0x40001540;
-r_sch_prog_rx_isr = 0x40001544;
-r_sch_prog_skip_isr = 0x40001548;
-r_sch_prog_tx_isr = 0x4000154c;
-r_sch_slice_bg_add = 0x40001550;
-r_sch_slice_bg_remove = 0x40001554;
-r_sch_slice_compute = 0x40001558;
-r_sch_slice_fg_add = 0x4000155c;
-r_sch_slice_fg_remove = 0x40001560;
-r_sch_slice_init = 0x40001564;
-r_sch_slice_per_add = 0x40001568;
-r_sch_slice_per_remove = 0x4000156c;
-r_sdk_config_get_bt_sleep_enable = 0x40001570;
-r_sdk_config_get_hl_derived_opts = 0x40001574;
-r_sdk_config_get_opts = 0x40001578;
-r_sdk_config_get_priv_opts = 0x4000157c;
-r_sdk_config_set_bt_sleep_enable = 0x40001580;
-r_sdk_config_set_hl_derived_opts = 0x40001584;
-r_sdk_config_set_opts = 0x40001588;
-r_specialModP256 = 0x4000158c;
-r_unloaded_area_init = 0x40001590;
-r_vhci_flow_off = 0x40001594;
-r_vhci_flow_on = 0x40001598;
-r_vhci_notify_host_send_available = 0x4000159c;
-r_vhci_send_to_host = 0x400015a0;
-r_vnd_hci_command_handler = 0x400015a4;
-r_vshci_init = 0x400015a8;
-vnd_hci_command_handler_wrapper = 0x400015ac;
 /* Data (.data, .bss, .rodata) */
 bt_rf_coex_cfg_p = 0x3fcdffcc;
 bt_rf_coex_hooks_p = 0x3fcdffc8;
@@ -1462,38 +668,6 @@ rwip_coex_cfg = 0x3ff1eeac;
 rwip_priority = 0x3ff1ee94;
 veryBigHexP256 = 0x3ff1ee48;
 
-/* bluetooth hook funcs */
-r_llc_loc_encrypt_proc_continue_hook = 0x40001c60;
-r_llc_loc_phy_upd_proc_continue_hook = 0x40001c64;
-r_llc_rem_phy_upd_proc_continue_hook = 0x40001c68;
-r_lld_scan_frm_eof_isr_hook = 0x40001c6c;
-r_lld_scan_evt_start_cbk_hook = 0x40001c70;
-r_lld_scan_process_pkt_rx_ext_adv_hook = 0x40001c78;
-r_lld_scan_sched_hook = 0x40001c7c;
-r_lld_adv_evt_start_cbk_hook = 0x40001c84;
-r_lld_adv_aux_evt_start_cbk_hook = 0x40001c88;
-r_lld_adv_frm_isr_hook = 0x40001c8c;
-r_lld_adv_start_init_evt_param_hook = 0x40001c90;
-r_lld_con_evt_canceled_cbk_hook = 0x40001c94;
-r_lld_con_frm_isr_hook = 0x40001c98;
-r_lld_con_tx_hook = 0x40001c9c;
-r_lld_con_rx_hook = 0x40001ca0;
-r_lld_con_evt_start_cbk_hook = 0x40001ca4;
-r_lld_con_tx_prog_new_packet_hook = 0x40001cac;
-r_lld_init_frm_eof_isr_hook = 0x40001cb0;
-r_lld_init_evt_start_cbk_hook = 0x40001cb4;
-r_lld_init_sched_hook = 0x40001cbc;
-r_lld_init_process_pkt_tx_hook = 0x40001cc0;
-r_lld_per_adv_evt_start_cbk_hook = 0x40001cc4;
-r_lld_per_adv_frm_isr_hook = 0x40001cc8;
-r_lld_per_adv_start_hook = 0x40001ccc;
-r_lld_sync_frm_eof_isr_hook = 0x40001cd0;
-r_lld_sync_evt_start_cbk_hook = 0x40001cd4;
-r_lld_sync_start_hook = 0x40001cd8;
-r_lld_sync_process_pkt_rx_pkt_check_hook = 0x40001cdc;
-r_sch_arb_insert_hook = 0x40001ce0;
-r_sch_plan_offset_req_hook = 0x40001ce4;
-
 /***************************************
  Group rom_pp
  ***************************************/
diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/gpio.h b/components/esp_rom/esp32c5/include/esp32c5/rom/gpio.h
index 1153de59bf3..7a9c1590b54 100644
--- a/components/esp_rom/esp32c5/include/esp32c5/rom/gpio.h
+++ b/components/esp_rom/esp32c5/include/esp32c5/rom/gpio.h
@@ -44,7 +44,7 @@ typedef enum {
 
 
 /**
-  * @brief Change GPIO(0-30) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
+  * @brief Change GPIO(0-28) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
   *         There is no particular ordering guaranteed; so if the order of writes is significant,
   *         calling code should divide a single call into multiple calls.
   *
@@ -61,7 +61,7 @@ typedef enum {
 void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
 
 /**
-  * @brief Sample the value of GPIO input pins(0-30) and returns a bitmask.
+  * @brief Sample the value of GPIO input pins(0-28) and returns a bitmask.
   * @param None
   *
   * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
@@ -69,7 +69,7 @@ void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mas
 uint32_t gpio_input_get(void);
 
 /**
-  * @brief Set GPIO to wakeup the ESP32.
+  * @brief Set GPIO to wakeup.
   *        Please do not call this function in SDK.
   *
   * @param uint32_t i: gpio number.
@@ -81,7 +81,7 @@ uint32_t gpio_input_get(void);
 void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
 
 /**
-  * @brief disable GPIOs to wakeup the ESP32.
+  * @brief disable GPIOs to wakeup.
   *        Please do not call this function in SDK.
   *
   * @param None
@@ -93,10 +93,9 @@ void gpio_pin_wakeup_disable(void);
 /**
   * @brief set gpio input to a signal, one gpio can input to several signals.
   *
-  * @param uint32_t gpio : gpio number, 0~30
-  *                        gpio == 0x3C, input 0 to signal
-  *                        gpio == 0x3A, input nothing to signal
-  *                        gpio == 0x38, input 1 to signal
+  * @param uint32_t gpio : gpio number, 0~28
+  *                        gpio == 0x60, input 0 to signal
+  *                        gpio == 0x40, input 1 to signal
   *
   * @param uint32_t signal_idx : signal index.
   *
@@ -109,7 +108,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
 /**
   * @brief set signal output to gpio, one signal can output to several gpios.
   *
-  * @param uint32_t gpio : gpio number, 0~30
+  * @param uint32_t gpio : gpio number, 0~28
   *
   * @param uint32_t signal_idx : signal index.
   *                        signal_idx == 0x80, cancel output put to the gpio
@@ -125,7 +124,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
 /**
   * @brief Select pad as a gpio function from IOMUX.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~28
   *
   * @return None
   */
@@ -134,7 +133,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
 /**
   * @brief Set pad driver capability.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~28
   *
   * @param uint32_t drv : 0-3
   *
@@ -145,7 +144,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
 /**
   * @brief Pull up the pad from gpio number.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~28
   *
   * @return None
   */
@@ -154,7 +153,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
 /**
   * @brief Pull down the pad from gpio number.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~28
   *
   * @return None
   */
@@ -163,7 +162,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
 /**
   * @brief Unhold the pad from gpio number.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~28
   *
   * @return None
   */
@@ -172,7 +171,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
 /**
   * @brief Hold the pad from gpio number.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~28
   *
   * @return None
   */
@@ -181,7 +180,7 @@ void gpio_pad_hold(uint32_t gpio_num);
 /**
   * @brief enable gpio pad input.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~28
   *
   * @return None
   */
@@ -190,7 +189,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
 /**
   * @brief disable gpio pad input.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~28
   *
   * @return None
   */
diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/km.h b/components/esp_rom/esp32c5/include/esp32c5/rom/km.h
new file mode 100644
index 00000000000..2fe74e77a56
--- /dev/null
+++ b/components/esp_rom/esp32c5/include/esp32c5/rom/km.h
@@ -0,0 +1,63 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _KM_H
+#define _KM_H
+
+#include "soc/soc_caps.h"
+#if SOC_KEY_MANAGER_SUPPORTED
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "ets_sys.h"
+
+#if __cplusplus
+extern "C" {
+#endif
+
+/* huk mode type */
+typedef enum {
+    HUK_MODE_RECOVER = 0,
+    HUK_MODE_GEN = 1,
+} huk_mode_t;
+
+/**
+  * @brief Recover efuse key or key manager key if flash encryption is enabled
+  *
+  * @param do_log : if km process print log
+  *
+  * @return ETS_OK when key is recovered, ETS_FAILED when key not recovered
+  */
+ETS_STATUS esp_rom_check_recover_key(int do_log);
+
+/**
+  * @brief Configure huk mode
+  *
+  * @param mode : HUK_MODE_RECOVER or HUK_MODE_GEN
+  *
+  * @param huk_info : uint8_t pointer to the buffer which will feed the huk info or
+  *                   gain the huk info
+  *
+  * @return ETS_OK when huk configuration is done, else ETS_FAILED
+  */
+ETS_STATUS esp_rom_km_huk_conf(huk_mode_t mode, uint8_t *huk_info);
+
+/**
+  * @brief Get huk risk. The risk level of HUK is 0-6: the higher the risk level is,
+  *        the more error bits there are in the PUF SRAM. 7: Error level, HUK is invalid
+  *
+  * @param None
+  *
+  * @return The huk risk
+  */
+int esp_rom_km_huk_risk(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* SOC_KEY_MANAGER_SUPPORTED */
+
+#endif /* _KM_H */
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.ld
index 3f5b833a297..7f5148d682f 100644
--- a/components/esp_rom/esp32c5/ld/esp32c5.rom.ld
+++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.ld
@@ -258,8 +258,8 @@ gpio_get_input_level = 0x4000070c;
 gpio_matrix_in = 0x40000710;
 gpio_matrix_out = 0x40000714;
 gpio_bypass_matrix_in = 0x40000718;
-gpio_output_disable = 0x4000071c;
-gpio_output_enable = 0x40000720;
+/* gpio_output_disable = 0x4000071c; */
+/* gpio_output_enable = 0x40000720; */
 gpio_pad_input_disable = 0x40000724;
 gpio_pad_input_enable = 0x40000728;
 gpio_pad_pulldown = 0x4000072c;
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
index bd55f3bb3cb..1d87aafcb38 100644
--- a/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
+++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
@@ -60,7 +60,7 @@ ieee80211_find_ext_elem = 0x40000bb0;
 ieee80211_find_ie = 0x40000bb4;
 ieee80211_find_ext_ie = 0x40000bb8;
 ieee80211_merge_mbssid_profile = 0x40000bbc;
-ieee80211_encap_esfbuf_htc = 0x40000bc0;
+/*ieee80211_encap_esfbuf_htc = 0x40000bc0;*/
 /*wifi_get_macaddr = 0x40000bc4;*/
 /*wifi_rf_phy_disable = 0x40000bc8;*/
 /*wifi_rf_phy_enable = 0x40000bcc;*/
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.phy.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.phy.ld
index 9bd20793bee..3c61a264b03 100644
--- a/components/esp_rom/esp32c5/ld/esp32c5.rom.phy.ld
+++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.phy.ld
@@ -284,10 +284,14 @@ phy_wifi_set_tx_gain = 0x400014f4;
 phy_bt_get_tx_tab_ = 0x400014f8;
 phy_bt_set_tx_gain = 0x400014fc;
 phy_bt_tx_gain_init = 0x40001500;
-phy_pbus_xpd_rx_off = 0x40002518;
-phy_i2c_writeReg_Mask = 0x4000787e;
-phy_pbus_xpd_rx_on = 0x40002628;
-phy_pbus_xpd_tx_on = 0x4000274c;
+phy_pbus_xpd_rx_off = 0x40001528;
+phy_i2c_writeReg_Mask = 0x4000152c;
+phy_pbus_xpd_rx_on = 0x40001530;
+phy_pbus_xpd_tx_on = 0x40001534;
+phy_get_romfuncs = 0x40001538;
+phy_chip_set_chan_ana_ = 0x4000153c;
+phy_pbus_xpd_tx_off = 0x40001540;
 /* Data (.data, .bss, .rodata) */
 phy_rom_phyFuns = 0x4085fb80;
 phy_param_rom = 0x4085fc70;
+phy_rom_phyFuns_eco1 = 0x4085fc6c;
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
index 605063d1c68..dbe5ab1adf9 100644
--- a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
+++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
@@ -27,14 +27,14 @@ esf_buf_recycle = 0x40000bfc;
 GetAccess = 0x40000c00;
 hal_mac_is_low_rate_enabled = 0x40000c04;
 hal_mac_tx_get_blockack = 0x40000c08;
-hal_mac_tx_set_ppdu = 0x40000c0c;
+/*hal_mac_tx_set_ppdu = 0x40000c0c;*/
 hal_mac_tx_clr_mplen = 0x40000c10;
 hal_mac_get_txq_state = 0x40000c14;
 hal_mac_clr_txq_state = 0x40000c18;
 hal_mac_get_txq_complete = 0x40000c1c;
-/*hal_mac_deinit_twt_tx = 0x40000c20;*/
+hal_mac_deinit_twt_tx = 0x40000c20;
 hal_mac_is_dma_enable = 0x40000c24;
-hal_he_get_bss_color = 0x40000c28;
+/*hal_he_get_bss_color = 0x40000c28;*/
 hal_he_set_ersu = 0x40000c2c;
 hal_he_get_mplen_addr_start = 0x40000c30;
 hal_he_get_mplen_addr_end = 0x40000c34;
@@ -62,7 +62,7 @@ ic_get_he_rts_threshold_bytes = 0x40000c88;
 lmacAdjustTimestamp = 0x40000c8c;
 lmacDiscardAgedMSDU = 0x40000c90;
 lmacDiscardMSDU = 0x40000c94;
-/*lmacEndFrameExchangeSequence = 0x40000c98;*/
+lmacEndFrameExchangeSequence = 0x40000c98;
 lmacIsIdle = 0x40000c9c;
 lmacIsLongFrame = 0x40000ca0;
 lmacMSDUAged = 0x40000ca4;
@@ -74,19 +74,19 @@ lmacReachLongLimit = 0x40000cb8;
 lmacReachShortLimit = 0x40000cbc;
 lmacRecycleMPDU = 0x40000cc0;
 lmacRxDone = 0x40000cc4;
-/*lmacSetTxFrame = 0x40000cc8;*/
+lmacSetTxFrame = 0x40000cc8;
 lmacTxDone = 0x40000ccc;
 lmacTxFrame = 0x40000cd0;
 lmacDisableTransmit = 0x40000cd4;
 lmacDiscardFrameExchangeSequence = 0x40000cd8;
 lmacProcessCollision = 0x40000cdc;
 lmacProcessAckTimeout = 0x40000ce0;
-/*lmacProcessShortRetryFail = 0x40000ce4;*/
+lmacProcessShortRetryFail = 0x40000ce4;
 lmacProcessCollisions_task = 0x40000ce8;
 lmacProcessTxRtsError = 0x40000cec;
 lmacProcessTxError = 0x40000cf0;
 lmacProcessCtsTimeout = 0x40000cf4;
-/*lmacProcessLongRetryFail = 0x40000cf8;*/
+lmacProcessLongRetryFail = 0x40000cf8;
 lmacRetryTxFrame = 0x40000cfc;
 lmacEndRetryAMPDUFail = 0x40000d00;
 lmacProcessTxSuccess = 0x40000d04;
@@ -112,7 +112,7 @@ pm_disable_sleep_delay_timer = 0x40000d50;
 /*pm_dream = 0x40000d54;*/
 pm_mac_wakeup = 0x40000d58;
 pm_mac_sleep = 0x40000d5c;
-pm_enable_active_timer = 0x40000d60;
+/*pm_enable_active_timer = 0x40000d60;*/
 pm_enable_sleep_delay_timer = 0x40000d64;
 pm_local_tsf_process = 0x40000d68;
 pm_set_beacon_filter = 0x40000d6c;
@@ -145,13 +145,13 @@ pm_disconnected_wake = 0x40000dd4;
 /*pm_tx_data_process = 0x40000dd8;*/
 pm_is_twt_awake = 0x40000ddc;
 pm_enable_twt_keep_alive = 0x40000de0;
-/*pm_twt_on_tsf_timer = 0x40000de4;*/
+pm_twt_on_tsf_timer = 0x40000de4;
 pm_twt_process = 0x40000de8;
 pm_is_twt_start = 0x40000dec;
 pm_twt_set_target_wdev_time = 0x40000df0;
 pm_twt_set_target_tsf = 0x40000df4;
 pm_enable_twt_keep_alive_timer = 0x40000df8;
-/*pm_mac_try_enable_modem_state = 0x40000dfc;*/
+pm_mac_try_enable_modem_state = 0x40000dfc;
 pm_beacon_monitor_tbtt_timeout_process = 0x40000e00;
 /*pm_update_next_tbtt = 0x40000e04;*/
 pm_twt_disallow_tx = 0x40000e08;
@@ -209,11 +209,11 @@ ppDisableQueue = 0x40000ed4;
 ppCalVHTDeliNum = 0x40000ed8;
 ppCalTxVHTSMPDULength = 0x40000edc;
 ppCheckTxRTS = 0x40000ee0;
-/*ppProcessLifeTime = 0x40000ee4;*/
+ppProcessLifeTime = 0x40000ee4;
 ppProcTxCallback = 0x40000ee8;
 ppCalPreFecPaddingFactor = 0x40000eec;
 ppCalDeliNum = 0x40000ef0;
-/*ppRemoveHTC = 0x40000ef4;*/
+ppRemoveHTC = 0x40000ef4;
 ppCheckTxHEAMPDUlength = 0x40000ef8;
 ppCertSetRate = 0x40000efc;
 ppSelectTxFormat = 0x40000f00;
@@ -222,7 +222,7 @@ pp_coex_tx_release = 0x40000f08;
 ppAdd2AMPDUTail = 0x40000f0c;
 ppDirectRecycleAmpdu = 0x40000f10;
 ppRegressAmpdu = 0x40000f14;
-pp_timer_do_process = 0x40000f18;
+/*pp_timer_do_process = 0x40000f18;*/
 rcGetAmpduSched = 0x40000f1c;
 rcUpdateRxDone = 0x40000f20;
 rc_get_trc = 0x40000f24;
@@ -260,7 +260,7 @@ trcAmpduSetState = 0x40000fa0;
 trc_set_bf_report_rate = 0x40000fa4;
 trc_onPPTxDone = 0x40000fa8;
 wDevCheckBlockError = 0x40000fac;
-/*wDev_AppendRxBlocks = 0x40000fb0;*/
+wDev_AppendRxBlocks = 0x40000fb0;
 wDev_DiscardFrame = 0x40000fb4;
 wDev_GetNoiseFloor = 0x40000fb8;
 wDev_IndicateAmpdu = 0x40000fbc;
@@ -335,6 +335,12 @@ is_use_muedca = 0x400010cc;
 pwr_hal_clear_mac_modem_state_wakeup_protect_signal = 0x400010d0;
 get_estimated_batime = 0x400010d4;
 get_sublen_offset = 0x400010d8;
+pm_coex_schm_overall_period_get = 0x40001504;
+ppRemoveHEAMPDUflags = 0x4000150c;
+tsf_hal_get_tbtt_interval = 0x40001510;
+pm_get_tbtt_count = 0x4000151c;
+tsf_hal_get_time = 0x40001520;
+tsf_hal_get_counter_value = 0x40001524;
 /* Data (.data, .bss, .rodata) */
 our_instances_ptr = 0x4004ffe0;
 pTxRx = 0x4085ff74;
diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.ld
index f8ea9d4d3e4..2af963d5087 100644
--- a/components/esp_rom/esp32c6/ld/esp32c6.rom.ld
+++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.ld
@@ -238,8 +238,8 @@ ets_clk_mspi_apb_wait_ready = 0x400006d0;
 gpio_input_get = 0x400006d4;
 gpio_matrix_in = 0x400006d8;
 gpio_matrix_out = 0x400006dc;
-gpio_output_disable = 0x400006e0;
-gpio_output_enable = 0x400006e4;
+/* gpio_output_disable = 0x400006e0; */
+/* gpio_output_enable = 0x400006e4; */
 gpio_output_set = 0x400006e8;
 gpio_pad_hold = 0x400006ec;
 gpio_pad_input_disable = 0x400006f0;
diff --git a/components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h b/components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h
index 80bfe79334e..f4272ea6e36 100644
--- a/components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h
+++ b/components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h
@@ -44,7 +44,7 @@ typedef enum {
 
 
 /**
-  * @brief Change GPIO(0-30) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
+  * @brief Change GPIO(0-24) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
   *         There is no particular ordering guaranteed; so if the order of writes is significant,
   *         calling code should divide a single call into multiple calls.
   *
@@ -61,7 +61,7 @@ typedef enum {
 void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
 
 /**
-  * @brief Sample the value of GPIO input pins(0-30) and returns a bitmask.
+  * @brief Sample the value of GPIO input pins(0-24) and returns a bitmask.
   * @param None
   *
   * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
@@ -69,7 +69,7 @@ void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mas
 uint32_t gpio_input_get(void);
 
 /**
-  * @brief Set GPIO to wakeup the ESP32.
+  * @brief Set GPIO to wakeup.
   *        Please do not call this function in SDK.
   *
   * @param uint32_t i: gpio number.
@@ -81,7 +81,7 @@ uint32_t gpio_input_get(void);
 void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
 
 /**
-  * @brief disable GPIOs to wakeup the ESP32.
+  * @brief disable GPIOs to wakeup.
   *        Please do not call this function in SDK.
   *
   * @param None
@@ -93,10 +93,9 @@ void gpio_pin_wakeup_disable(void);
 /**
   * @brief set gpio input to a signal, one gpio can input to several signals.
   *
-  * @param uint32_t gpio : gpio number, 0~30
-  *                        gpio == 0x3C, input 0 to signal
-  *                        gpio == 0x3A, input nothing to signal
-  *                        gpio == 0x38, input 1 to signal
+  * @param uint32_t gpio : gpio number, 0~24
+  *                        gpio == 0x30, input 0 to signal
+  *                        gpio == 0x20, input 1 to signal
   *
   * @param uint32_t signal_idx : signal index.
   *
@@ -109,7 +108,7 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
 /**
   * @brief set signal output to gpio, one signal can output to several gpios.
   *
-  * @param uint32_t gpio : gpio number, 0~30
+  * @param uint32_t gpio : gpio number, 0~24
   *
   * @param uint32_t signal_idx : signal index.
   *                        signal_idx == 0x80, cancel output put to the gpio
@@ -125,7 +124,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_
 /**
   * @brief Select pad as a gpio function from IOMUX.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~24
   *
   * @return None
   */
@@ -134,7 +133,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num);
 /**
   * @brief Set pad driver capability.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~24
   *
   * @param uint32_t drv : 0-3
   *
@@ -145,7 +144,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
 /**
   * @brief Pull up the pad from gpio number.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~24
   *
   * @return None
   */
@@ -154,7 +153,7 @@ void gpio_pad_pullup(uint32_t gpio_num);
 /**
   * @brief Pull down the pad from gpio number.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~24
   *
   * @return None
   */
@@ -163,7 +162,7 @@ void gpio_pad_pulldown(uint32_t gpio_num);
 /**
   * @brief Unhold the pad from gpio number.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~24
   *
   * @return None
   */
@@ -172,7 +171,7 @@ void gpio_pad_unhold(uint32_t gpio_num);
 /**
   * @brief Hold the pad from gpio number.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~24
   *
   * @return None
   */
@@ -181,7 +180,7 @@ void gpio_pad_hold(uint32_t gpio_num);
 /**
   * @brief enable gpio pad input.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~24
   *
   * @return None
   */
@@ -190,7 +189,7 @@ void gpio_pad_input_enable(uint32_t gpio_num);
 /**
   * @brief disable gpio pad input.
   *
-  * @param uint32_t gpio_num : gpio number, 0~30
+  * @param uint32_t gpio_num : gpio number, 0~24
   *
   * @return None
   */
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld
index 7ef283388df..645b536924c 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld
@@ -260,8 +260,8 @@ gpio_get_input_level = 0x400006f0;
 gpio_matrix_in = 0x400006f4;
 gpio_matrix_out = 0x400006f8;
 gpio_bypass_matrix_in = 0x400006fc;
-gpio_output_disable = 0x40000700;
-gpio_output_enable = 0x40000704;
+/* gpio_output_disable = 0x40000700; */
+/* gpio_output_enable = 0x40000704; */
 gpio_pad_input_disable = 0x40000708;
 gpio_pad_input_enable = 0x4000070c;
 gpio_pad_pulldown = 0x40000710;
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
index 82727daf241..230c560b3df 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
@@ -60,7 +60,7 @@ ieee80211_find_ext_elem = 0x40000b18;
 ieee80211_find_ie = 0x40000b1c;
 ieee80211_find_ext_ie = 0x40000b20;
 ieee80211_merge_mbssid_profile = 0x40000b24;
-ieee80211_encap_esfbuf_htc = 0x40000b28;
+/*ieee80211_encap_esfbuf_htc = 0x40000b28;*/
 wifi_get_macaddr = 0x40000b2c;
 wifi_rf_phy_disable = 0x40000b30;
 wifi_rf_phy_enable = 0x40000b34;
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
index 54f0a48c42b..2bdc202eb75 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld
@@ -27,14 +27,14 @@ esf_buf_recycle = 0x40000b64;
 GetAccess = 0x40000b68;
 hal_mac_is_low_rate_enabled = 0x40000b6c;
 hal_mac_tx_get_blockack = 0x40000b70;
-hal_mac_tx_set_ppdu = 0x40000b74;
+/*hal_mac_tx_set_ppdu = 0x40000b74;*/
 hal_mac_tx_clr_mplen = 0x40000b78;
 hal_mac_get_txq_state = 0x40000b7c;
 hal_mac_clr_txq_state = 0x40000b80;
 hal_mac_get_txq_complete = 0x40000b84;
 hal_mac_deinit_twt_tx = 0x40000b88;
 hal_mac_is_dma_enable = 0x40000b8c;
-hal_he_get_bss_color = 0x40000b90;
+/*hal_he_get_bss_color = 0x40000b90;*/
 hal_he_set_ersu = 0x40000b94;
 hal_he_get_mplen_addr_start = 0x40000b98;
 hal_he_get_mplen_addr_end = 0x40000b9c;
@@ -113,7 +113,7 @@ pm_disable_sleep_delay_timer = 0x40000cbc;
 pm_dream = 0x40000cc0;
 pm_mac_wakeup = 0x40000cc4;
 pm_mac_sleep = 0x40000cc8;
-pm_enable_active_timer = 0x40000ccc;
+/*pm_enable_active_timer = 0x40000ccc;*/
 pm_enable_sleep_delay_timer = 0x40000cd0;
 pm_local_tsf_process = 0x40000cd4;
 pm_set_beacon_filter = 0x40000cd8;
@@ -225,7 +225,7 @@ pp_coex_tx_release = 0x40000e7c;
 ppAdd2AMPDUTail = 0x40000e80;
 ppDirectRecycleAmpdu = 0x40000e84;
 ppRegressAmpdu = 0x40000e88;
-pp_timer_do_process = 0x40000e8c;
+/*pp_timer_do_process = 0x40000e8c;*/
 rcGetAmpduSched = 0x40000e90;
 rcUpdateRxDone = 0x40000e94;
 rc_get_trc = 0x40000e98;
diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld
index 7be47b11105..9f260f5ecd4 100644
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld
@@ -9,8 +9,9 @@
  ***************************************/
 
 /* Functions */
-systimer_hal_init = 0x400003d0;
-systimer_hal_deinit = 0x400003d4;
+/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* systimer_hal_init = 0x400003d0; */
+/* systimer_hal_deinit = 0x400003d4; */
 systimer_hal_set_tick_rate_ops = 0x400003d8;
 systimer_hal_get_counter_value = 0x400003dc;
 systimer_hal_get_time = 0x400003e0;
diff --git a/components/esp_rom/esp32h2/ld/esp32h2.rom.ld b/components/esp_rom/esp32h2/ld/esp32h2.rom.ld
index 8000e80f1c2..b7b8775614e 100644
--- a/components/esp_rom/esp32h2/ld/esp32h2.rom.ld
+++ b/components/esp_rom/esp32h2/ld/esp32h2.rom.ld
@@ -226,8 +226,8 @@ ets_clk_get_cpu_freq = 0x4000069c;
 gpio_input_get = 0x400006a0;
 gpio_matrix_in = 0x400006a4;
 gpio_matrix_out = 0x400006a8;
-gpio_output_disable = 0x400006ac;
-gpio_output_enable = 0x400006b0;
+/* gpio_output_disable = 0x400006ac; */
+/* gpio_output_enable = 0x400006b0; */
 gpio_output_set = 0x400006b4;
 gpio_pad_hold = 0x400006b8;
 gpio_pad_input_disable = 0x400006bc;
diff --git a/components/esp_rom/esp32p4/ld/esp32p4.rom.ld b/components/esp_rom/esp32p4/ld/esp32p4.rom.ld
index 6b8f14bf60e..1ddf2b79451 100644
--- a/components/esp_rom/esp32p4/ld/esp32p4.rom.ld
+++ b/components/esp_rom/esp32p4/ld/esp32p4.rom.ld
@@ -301,8 +301,8 @@ gpio_get_input_level = 0x4fc00568;
 gpio_matrix_in = 0x4fc0056c;
 gpio_matrix_out = 0x4fc00570;
 gpio_bypass_matrix_in = 0x4fc00574;
-gpio_output_disable = 0x4fc00578;
-gpio_output_enable = 0x4fc0057c;
+/* gpio_output_disable = 0x4fc00578; */
+/* gpio_output_enable = 0x4fc0057c; */
 gpio_pad_input_disable = 0x4fc00580;
 gpio_pad_input_enable = 0x4fc00584;
 gpio_pad_pulldown = 0x4fc00588;
diff --git a/components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld b/components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld
index ad9dbf3971b..7fba13bd4bd 100644
--- a/components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld
+++ b/components/esp_rom/esp32p4/ld/esp32p4lp.rom.ld
@@ -44,8 +44,8 @@ gpio_matrix_in = 0x501000d4;
 gpio_matrix_out = 0x501000d8;
 gpio_bypass_matrix_in = 0x501000dc;
 gpio_output_disable = 0x501000e0;
-gpio_output_enable = 0x501000e4;
-gpio_pad_input_disable = 0x501000e8;
+/* gpio_output_enable = 0x501000e4; */
+/* gpio_pad_input_disable = 0x501000e8; */
 gpio_pad_input_enable = 0x501000ec;
 gpio_pad_pulldown = 0x501000f0;
 gpio_pad_pullup = 0x501000f4;
diff --git a/components/esp_rom/esp32p4/ld/esp32p4lp.rom.newlib.ld b/components/esp_rom/esp32p4/ld/esp32p4lp.rom.newlib.ld
index d4936c7833c..ab46640b20b 100644
--- a/components/esp_rom/esp32p4/ld/esp32p4lp.rom.newlib.ld
+++ b/components/esp_rom/esp32p4/ld/esp32p4lp.rom.newlib.ld
@@ -1,12 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 /* ROM function interface esp32p4lp.rom.newlib.ld for esp32p4lp
  *
  *
- * Generated from ./target/esp32p4lp/interface-esp32p4lp.yml md5sum 0751c805e21bd23f11b74dcc1f7e8007
+ * Generated from ./target/esp32p4lp/interface-esp32p4lp.yml md5sum f827caf806e9f4faec384ffbde44b380
  *
  * Compatible with ROM where ECO version equal or greater to 0.
  *
@@ -18,60 +18,60 @@
  ***************************************/
 
 /* Functions */
-memset = 0x501000f0;
-memcpy = 0x501000f4;
-memmove = 0x501000f8;
-memcmp = 0x501000fc;
-strcpy = 0x50100100;
-strncpy = 0x50100104;
-strcmp = 0x50100108;
-strncmp = 0x5010010c;
-strlen = 0x50100110;
-strstr = 0x50100114;
-bzero = 0x50100118;
-isalnum = 0x5010011c;
-isalpha = 0x50100120;
-isascii = 0x50100124;
-isblank = 0x50100128;
-iscntrl = 0x5010012c;
-isdigit = 0x50100130;
-islower = 0x50100134;
-isgraph = 0x50100138;
-isprint = 0x5010013c;
-ispunct = 0x50100140;
-isspace = 0x50100144;
-isupper = 0x50100148;
-toupper = 0x5010014c;
-tolower = 0x50100150;
-toascii = 0x50100154;
-memccpy = 0x50100158;
-memchr = 0x5010015c;
-memrchr = 0x50100160;
-strcasecmp = 0x50100164;
-strcasestr = 0x50100168;
-strcat = 0x5010016c;
-strchr = 0x50100170;
-strcspn = 0x50100174;
-strcoll = 0x50100178;
-strlcat = 0x5010017c;
-strlcpy = 0x50100180;
-strlwr = 0x50100184;
-strncasecmp = 0x50100188;
-strncat = 0x5010018c;
-strnlen = 0x50100190;
-strrchr = 0x50100194;
-strsep = 0x50100198;
-strspn = 0x5010019c;
-strtok_r = 0x501001a0;
-strupr = 0x501001a4;
-longjmp = 0x501001a8;
-setjmp = 0x501001ac;
-abs = 0x501001b0;
-div = 0x501001b4;
-labs = 0x501001b8;
-ldiv = 0x501001bc;
-qsort = 0x501001c0;
-atoi = 0x501001c4;
-atol = 0x501001c8;
-itoa = 0x501001cc;
-utoa = 0x501001d0;
+memset = 0x50100134;
+memcpy = 0x50100138;
+memmove = 0x5010013c;
+memcmp = 0x50100140;
+strcpy = 0x50100144;
+strncpy = 0x50100148;
+strcmp = 0x5010014c;
+strncmp = 0x50100150;
+strlen = 0x50100154;
+strstr = 0x50100158;
+bzero = 0x5010015c;
+isalnum = 0x50100160;
+isalpha = 0x50100164;
+isascii = 0x50100168;
+isblank = 0x5010016c;
+iscntrl = 0x50100170;
+isdigit = 0x50100174;
+islower = 0x50100178;
+isgraph = 0x5010017c;
+isprint = 0x50100180;
+ispunct = 0x50100184;
+isspace = 0x50100188;
+isupper = 0x5010018c;
+toupper = 0x50100190;
+tolower = 0x50100194;
+toascii = 0x50100198;
+memccpy = 0x5010019c;
+memchr = 0x501001a0;
+memrchr = 0x501001a4;
+strcasecmp = 0x501001a8;
+strcasestr = 0x501001ac;
+strcat = 0x501001b0;
+strchr = 0x501001b4;
+strcspn = 0x501001b8;
+strcoll = 0x501001bc;
+strlcat = 0x501001c0;
+strlcpy = 0x501001c4;
+strlwr = 0x501001c8;
+strncasecmp = 0x501001cc;
+strncat = 0x501001d0;
+strnlen = 0x501001d4;
+strrchr = 0x501001d8;
+strsep = 0x501001dc;
+strspn = 0x501001e0;
+strtok_r = 0x501001e4;
+strupr = 0x501001e8;
+longjmp = 0x501001ec;
+setjmp = 0x501001f0;
+abs = 0x501001f4;
+div = 0x501001f8;
+labs = 0x501001fc;
+ldiv = 0x50100200;
+qsort = 0x50100204;
+atoi = 0x50100208;
+atol = 0x5010020c;
+itoa = 0x50100210;
+utoa = 0x50100214;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_50.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_50.ld
new file mode 100644
index 00000000000..10cc038cc3b
--- /dev/null
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_50.ld
@@ -0,0 +1,75 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32s3.rom.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* extend adv */
+f_hci_le_set_ext_adv_param_cmd_handler = 0x40000000;
+f_hci_le_set_adv_set_rand_addr_cmd_handler = 0x40000000;
+f_hci_le_set_ext_adv_data_cmd_handler = 0x40000000;
+f_hci_le_set_ext_scan_rsp_data_cmd_handler = 0x40000000;
+f_hci_le_set_ext_adv_en_cmd_handler = 0x40000000;
+f_hci_le_rd_max_adv_data_len_cmd_handler = 0x40000000;
+f_hci_le_rd_nb_supp_adv_sets_cmd_handler = 0x40000000;
+f_hci_le_rmv_adv_set_cmd_handler = 0x40000000;
+f_hci_le_clear_adv_sets_cmd_handler = 0x40000000;
+r_lld_adv_sync_info_set = 0x40000000;
+
+r_lld_ext_adv_dynamic_pti_process = 0x40000000;
+r_lld_adv_ext_chain_construct = 0x40000000;
+r_lld_adv_aux_evt_canceled_cbk = 0x40000000;
+r_lld_adv_aux_evt_start_cbk = 0x40000000;
+r_lld_adv_aux_ch_idx_set = 0x40000000;
+
+/* periodic adv */
+f_hci_le_set_per_adv_param_cmd_handler = 0x40000000;
+f_hci_le_set_per_adv_data_cmd_handler = 0x40000000;
+f_hci_le_set_per_adv_en_cmd_handler = 0x40000000;
+r_lld_per_adv_ch_map_update = 0x40000000;
+r_lld_per_adv_init = 0x40000000;
+
+/* PA list */
+f_hci_le_add_dev_to_per_adv_list_cmd_handler = 0x40000000;
+f_hci_le_rmv_dev_from_per_adv_list_cmd_handler = 0x40000000;
+f_hci_le_clear_per_adv_list_cmd_handler = 0x40000000;
+f_hci_le_rd_per_adv_list_size_cmd_handler = 0x40000000;
+
+/* extend scan */
+f_hci_le_set_ext_scan_param_cmd_handler = 0x40000000;
+f_hci_le_set_ext_scan_en_cmd_handler = 0x40000000;
+r_lld_scan_process_pkt_rx_ext_adv = 0x40000000;
+r_lld_scan_trunc_ind = 0x40000000;
+
+/* extend con */
+f_hci_le_ext_create_con_cmd_handler = 0x40000000;
+r_lld_init_process_pkt_rx_adv_ext_ind = 0x40000000;
+r_lld_init_process_pkt_rx_aux_connect_rsp = 0x40000000;
+
+/* PA sync */
+f_hci_le_per_adv_create_sync_cmd_handler = 0x40000000;
+f_hci_le_per_adv_create_sync_cancel_cmd_handler = 0x40000000;
+f_hci_le_per_adv_term_sync_cmd_handler = 0x40000000;
+f_lld_per_adv_rx_end_ind_handler_hack = 0x40000000;
+f_lld_sync_start_req_handler = 0x40000000;
+f_lld_per_adv_rep_ind_handler = 0x40000000;
+r_lld_sync_init = 0x40000000;
+
+/* phy update*/
+r_phy_upd_proc_start = 0x40000000;
+f_llc_op_phy_upd_ind_handler = 0x40000000;
+f_ll_phy_req_handler = 0x40000000;
+f_ll_phy_rsp_handler = 0x40000000;
+f_ll_phy_update_ind_handler = 0x40000000;
+f_lld_phy_upd_cfm_handler = 0x40000000;
+f_hci_le_set_phy_cmd_handler = 0x40000000;
+llc_llcp_phy_update_ind_ack = 0x40000000;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_cca.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_cca.ld
new file mode 100644
index 00000000000..74d2dca0e30
--- /dev/null
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_cca.ld
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32s3.rom.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* SW CCA */
+r_lld_cca_con_evt_start_handle = 0x40000000;
+r_lld_hw_cca_end_isr = 0x40000000;
+r_lld_hw_cca_isr_eco = 0x40000000;
+r_lld_cca_bb_sync_found_handle = 0x40000000;
+r_lld_cca_data_reset = 0x40000000;
+r_lld_cca_sw_init = 0x40000000;
+r_lld_cca_con_evt_end_handle  = 0x40000000;
+r_lld_cca_alloc = 0x40000000;
+r_lld_cca_sw_alloc = 0x40000000;
+r_lld_cca_sw_free = 0x40000000;
+r_lld_cca_free = 0x40000000;
+r_cca_init = 0x40000000;
+r_lld_hw_cca_evt_handler = 0x40000000;
+r_lld_sw_cca_evt_handler = 0x40000000;
+r_ble_sw_cca_check_isr = 0x40000000;
+bt_bb_tx_cca_set = 0x40000000;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_dtm.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_dtm.ld
new file mode 100644
index 00000000000..e08545c7179
--- /dev/null
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_dtm.ld
@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32s3.rom.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* DTM */
+f_hci_le_rx_test_cmd_handler = 0x40000000;
+f_hci_le_tx_test_cmd_handler = 0x40000000;
+f_hci_le_enh_rx_test_cmd_handler = 0x40000000;
+f_hci_le_enh_tx_test_cmd_handler = 0x40000000;
+f_hci_le_test_end_cmd_handler = 0x40000000;
+r_lld_test_init = 0x40000000;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_master.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_master.ld
new file mode 100644
index 00000000000..498330a6804
--- /dev/null
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_master.ld
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32s3.rom.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* master */
+f_hci_le_create_con_cmd_handler = 0x40000000;
+f_hci_le_create_con_cancel_cmd_handler = 0x40000000;
+lld_init_end_ind_handler = 0x40000000;
+r_lld_init_init = 0x40000000;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_scan.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_scan.ld
new file mode 100644
index 00000000000..c3c8414e516
--- /dev/null
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_scan.ld
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32s3.rom.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+
+/* BLE scan */
+
+f_hci_le_set_scan_param_cmd_handler = 0x40000000;
+f_hci_le_set_scan_en_cmd_handler = 0x40000000;
+f_llm_scan_period_to_handler_hack = 0x40000000;
+f_lld_adv_rep_ind_handler_hack = 0x40000000;
+r_lld_scan_init = 0x40000000;
+r_lld_scan_restart = 0x40000000;
+f_lld_scan_end_ind_handler_hack = 0x40000000;
+r_llm_env_adv_dup_filt_deinit_eco = 0x40000000;
+llm_exception_list_init = 0x40000000;
+llm_duplicate_list_init = 0x40000000;
+f_hci_vendor_ble_update_duplicate_exceptional_list_cmd_handler = 0x40000000;
+f_hci_vendor_ble_init_adv_flow_control_cmd_handler = 0x40000000;
+f_hci_vendor_ble_update_adv_report_flow_control_cmd_handler = 0x40000000;
+coex_schm_ble_scan_stop = 0x40000000;
+
+f_hci_le_set_ext_scan_param_cmd_handler = 0x40000000;
+f_hci_le_set_ext_scan_en_cmd_handler = 0x40000000;
+r_lld_scan_process_pkt_rx_ext_adv = 0x40000000;
+r_lld_scan_trunc_ind = 0x40000000;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_smp.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_smp.ld
new file mode 100644
index 00000000000..78d1fb9784a
--- /dev/null
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_smp.ld
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32s3.rom.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/* SMP */
+f_ll_pause_enc_req_handler = 0x40000000;
+f_ll_pause_enc_rsp_handler = 0x40000000;
+f_ll_enc_req_handler = 0x40000000;
+f_ll_enc_rsp_handler = 0x40000000;
+f_ll_start_enc_req_handler = 0x40000000;
+f_ll_start_enc_rsp_handler = 0x40000000;
+f_hci_le_start_enc_cmd_handler = 0x40000000;
+f_hci_le_ltk_req_reply_cmd_handler = 0x40000000;
+f_hci_le_ltk_req_neg_reply_cmd_handler = 0x40000000;
+f_llc_encrypt_ind_handler = 0x40000000;
+f_llc_op_encrypt_ind_handler = 0x40000000;
+f_hci_le_rd_local_p256_public_key_cmd_handler = 0x40000000;
+f_hci_le_generate_dhkey_cmd_handler = 0x40000000;
+f_hci_le_enc_cmd_handler = 0x40000000;
+r_rwip_crypt_evt_handler = 0x40000000;
+
+/* LE ping */
+f_ll_ping_req_handler = 0x40000000;
+f_ll_ping_rsp_handler = 0x40000000;
+r_llc_le_ping_set = 0x40000000;
+r_llc_le_ping_restart = 0x40000000;
+f_llc_op_le_ping_ind_handler = 0x40000000;
+f_llc_auth_payl_nearly_op_handler = 0x40000000;
+f_llc_auth_payl_real_to_handler = 0x40000000;
+f_llc_auth_payl_nearly_to_handler = 0x40000000;
+
+/* ecc */
+r_ecc_init = 0x40000000;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_test.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_test.ld
new file mode 100644
index 00000000000..1c0a6b59f0a
--- /dev/null
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ble_test.ld
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32s3.rom.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+
+/* overwrite */
+lld_acl_rx_ind_handler = 0x40000000;
+lld_con_estab_ind_handler = 0x40000000;
+lld_adv_rep_ind_handler = 0x40000000;
+llm_rpa_renew_to_handler = 0x40000000;
+lld_scan_end_ind_handler = 0x40000000;
+llm_scan_period_to_handler = 0x40000000;
+
+/* nvds */
+r_nvds_init = 0x40000000;
+f_nvds_get = 0x40000000;
+f_nvds_del = 0x40000000;
+f_nvds_put = 0x40000000;
+
+/* controller flash */
+r_flash_init = 0x40000000;
+r_flash_env_init = 0x40000000;
+r_flash_env_deinit = 0x40000000;
+
+/* QA test */
+f_hci_vendor_ble_qa_test_cmd_handler = 0x40000000;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.bt_funcs.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.bt_funcs.ld
new file mode 100644
index 00000000000..de1ad187533
--- /dev/null
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.bt_funcs.ld
@@ -0,0 +1,874 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32s3.rom.ld for esp32s3
+ *
+ *
+ * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group bluetooth
+ ***************************************/
+
+/* Functions */
+bt_rf_coex_get_dft_cfg = 0x40002a78;
+bt_rf_coex_hooks_p_set = 0x40002a84;
+btdm_con_maxevtime_cal_impl = 0x40002a90;
+btdm_controller_get_compile_version_impl = 0x40002a9c;
+btdm_controller_rom_data_init = 0x40002aa8;
+btdm_dis_privacy_err_report_impl = 0x40002ab4;
+btdm_disable_adv_delay_impl = 0x40002ac0;
+btdm_enable_scan_continue_impl = 0x40002acc;
+btdm_enable_scan_forever_impl = 0x40002ad8;
+btdm_get_power_state_impl = 0x40002ae4;
+btdm_get_prevent_sleep_flag_impl = 0x40002af0;
+btdm_power_state_active_impl = 0x40002afc;
+btdm_switch_phy_coded_impl = 0x40002b08;
+hci_acl_data_handler = 0x40002b14;
+hci_disconnect_cmd_handler = 0x40002b20;
+hci_le_con_upd_cmd_handler = 0x40002b2c;
+hci_le_ltk_req_neg_reply_cmd_handler = 0x40002b38;
+hci_le_ltk_req_reply_cmd_handler = 0x40002b44;
+hci_le_rd_chnl_map_cmd_handler = 0x40002b50;
+hci_le_rd_phy_cmd_handler = 0x40002b5c;
+hci_le_rd_rem_feats_cmd_handler = 0x40002b68;
+hci_le_rem_con_param_req_neg_reply_cmd_handler = 0x40002b74;
+hci_le_rem_con_param_req_reply_cmd_handler = 0x40002b80;
+hci_le_set_data_len_cmd_handler = 0x40002b8c;
+hci_le_set_phy_cmd_handler = 0x40002b98;
+hci_le_start_enc_cmd_handler = 0x40002ba4;
+hci_rd_auth_payl_to_cmd_handler = 0x40002bb0;
+hci_rd_rem_ver_info_cmd_handler = 0x40002bbc;
+hci_rd_rssi_cmd_handler = 0x40002bc8;
+hci_rd_tx_pwr_lvl_cmd_handler = 0x40002bd4;
+hci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40002be0;
+hci_vs_set_pref_slave_latency_cmd_handler = 0x40002bec;
+hci_wr_auth_payl_to_cmd_handler = 0x40002bf8;
+ll_channel_map_ind_handler = 0x40002c04;
+ll_connection_param_req_handler = 0x40002c10;
+ll_connection_param_rsp_handler = 0x40002c1c;
+ll_connection_update_ind_handler = 0x40002c28;
+ll_enc_req_handler = 0x40002c34;
+ll_enc_rsp_handler = 0x40002c40;
+ll_feature_req_handler = 0x40002c4c;
+ll_feature_rsp_handler = 0x40002c58;
+ll_length_req_handler = 0x40002c64;
+ll_length_rsp_handler = 0x40002c70;
+ll_min_used_channels_ind_handler = 0x40002c7c;
+ll_pause_enc_req_handler = 0x40002c88;
+ll_pause_enc_rsp_handler = 0x40002c94;
+ll_phy_req_handler = 0x40002ca0;
+ll_phy_rsp_handler = 0x40002cac;
+ll_phy_update_ind_handler = 0x40002cb8;
+ll_ping_req_handler = 0x40002cc4;
+ll_ping_rsp_handler = 0x40002cd0;
+ll_slave_feature_req_handler = 0x40002cdc;
+ll_start_enc_req_handler = 0x40002ce8;
+ll_start_enc_rsp_handler = 0x40002cf4;
+ll_terminate_ind_handler = 0x40002d00;
+ll_version_ind_handler = 0x40002d0c;
+llc_auth_payl_nearly_to_handler = 0x40002d18;
+llc_auth_payl_real_to_handler = 0x40002d24;
+llc_encrypt_ind_handler = 0x40002d30;
+llc_hci_command_handler_wrapper = 0x40002d3c;
+llc_ll_connection_param_req_pdu_send = 0x40002d48;
+llc_ll_connection_param_rsp_pdu_send = 0x40002d54;
+llc_ll_connection_update_ind_pdu_send = 0x40002d60;
+llc_ll_enc_req_pdu_send = 0x40002d6c;
+llc_ll_enc_rsp_pdu_send = 0x40002d78;
+llc_ll_feature_req_pdu_send = 0x40002d84;
+llc_ll_feature_rsp_pdu_send = 0x40002d90;
+llc_ll_length_req_pdu_send = 0x40002d9c;
+llc_ll_length_rsp_pdu_send = 0x40002da8;
+llc_ll_pause_enc_req_pdu_send = 0x40002db4;
+llc_ll_pause_enc_rsp_pdu_send = 0x40002dc0;
+llc_ll_phy_req_pdu_send = 0x40002dcc;
+llc_ll_phy_rsp_pdu_send = 0x40002dd8;
+llc_ll_ping_req_pdu_send = 0x40002de4;
+llc_ll_ping_rsp_pdu_send = 0x40002df0;
+llc_ll_start_enc_req_pdu_send = 0x40002dfc;
+llc_ll_start_enc_rsp_pdu_send = 0x40002e08;
+llc_ll_terminate_ind_pdu_send = 0x40002e14;
+llc_ll_unknown_rsp_pdu_send = 0x40002e20;
+llc_llcp_ch_map_update_ind_pdu_send = 0x40002e2c;
+llc_llcp_phy_upd_ind_pdu_send = 0x40002e38;
+llc_llcp_version_ind_pdu_send = 0x40002e44;
+llc_op_ch_map_upd_ind_handler = 0x40002e50;
+llc_op_con_upd_ind_handler = 0x40002e5c;
+llc_op_disconnect_ind_handler = 0x40002e68;
+llc_op_dl_upd_ind_handler = 0x40002e74;
+llc_op_encrypt_ind_handler = 0x40002e80;
+llc_op_feats_exch_ind_handler = 0x40002e8c;
+llc_op_le_ping_ind_handler = 0x40002e98;
+llc_op_phy_upd_ind_handler = 0x40002ea4;
+llc_op_ver_exch_ind_handler = 0x40002eb0;
+llc_stopped_ind_handler = 0x40002ebc;
+lld_acl_rx_ind_handler = 0x40002ec8;
+lld_acl_tx_cfm_handler = 0x40002ed4;
+lld_adv_end_ind_handler = 0x40002ee0;
+lld_adv_rep_ind_handler = 0x40002eec;
+lld_ch_map_upd_cfm_handler = 0x40002ef8;
+lld_con_estab_ind_handler = 0x40002f04;
+lld_con_evt_sd_evt_time_set = 0x40002f10;
+lld_con_offset_upd_ind_handler = 0x40002f1c;
+lld_con_param_upd_cfm_handler = 0x40002f28;
+lld_disc_ind_handler = 0x40002f34;
+lld_init_end_ind_handler = 0x40002f40;
+lld_llcp_rx_ind_handler_wrapper = 0x40002f4c;
+lld_llcp_tx_cfm_handler = 0x40002f58;
+lld_per_adv_end_ind_handler = 0x40002f64;
+lld_per_adv_rep_ind_handler = 0x40002f70;
+lld_per_adv_rx_end_ind_handler = 0x40002f7c;
+lld_phy_coded_500k_get = 0x40002f88;
+lld_phy_upd_cfm_handler = 0x40002f94;
+lld_scan_end_ind_handler = 0x40002fa0;
+lld_scan_req_ind_handler = 0x40002fac;
+lld_sync_start_req_handler = 0x40002fb8;
+lld_test_end_ind_handler = 0x40002fc4;
+lld_update_rxbuf_handler = 0x40002fd0;
+llm_ch_map_update_ind_handler = 0x40002fdc;
+llm_hci_command_handler_wrapper = 0x40002fe8;
+llm_scan_period_to_handler = 0x40002ff4;
+r_Add2SelfBigHex256 = 0x40003000;
+r_AddBigHex256 = 0x4000300c;
+r_AddBigHexModP256 = 0x40003018;
+r_AddP256 = 0x40003024;
+r_AddPdiv2_256 = 0x40003030;
+r_GF_Jacobian_Point_Addition256 = 0x4000303c;
+r_GF_Jacobian_Point_Double256 = 0x40003048;
+r_GF_Point_Jacobian_To_Affine256 = 0x40003054;
+r_MultiplyBigHexByUint32_256 = 0x40003060;
+r_MultiplyBigHexModP256 = 0x4000306c;
+r_MultiplyByU16ModP256 = 0x40003078;
+r_SubtractBigHex256 = 0x40003084;
+r_SubtractBigHexMod256 = 0x40003090;
+r_SubtractBigHexUint32_256 = 0x4000309c;
+r_SubtractFromSelfBigHex256 = 0x400030a8;
+r_SubtractFromSelfBigHexSign256 = 0x400030b4;
+r_aes_alloc = 0x400030c0;
+r_aes_ccm_continue = 0x400030cc;
+r_aes_ccm_process_e = 0x400030d8;
+r_aes_ccm_xor_128_lsb = 0x400030e4;
+r_aes_ccm_xor_128_msb = 0x400030f0;
+r_aes_cmac_continue = 0x400030fc;
+r_aes_cmac_start = 0x40003108;
+r_aes_k1_continue = 0x40003114;
+r_aes_k2_continue = 0x40003120;
+r_aes_k3_continue = 0x4000312c;
+r_aes_k4_continue = 0x40003138;
+r_aes_shift_left_128 = 0x40003144;
+r_aes_start = 0x40003150;
+r_aes_xor_128 = 0x4000315c;
+r_assert_err = 0x40003168;
+r_assert_param = 0x40003174;
+r_assert_warn = 0x40003180;
+r_bigHexInversion256 = 0x4000318c;
+r_ble_sw_cca_check_isr = 0x40003198;
+r_ble_util_buf_acl_tx_alloc = 0x400031a4;
+r_ble_util_buf_acl_tx_elt_get = 0x400031b0;
+r_ble_util_buf_acl_tx_free = 0x400031bc;
+r_ble_util_buf_acl_tx_free_in_isr = 0x400031c8;
+r_ble_util_buf_adv_tx_alloc = 0x400031d4;
+r_ble_util_buf_adv_tx_free = 0x400031e0;
+r_ble_util_buf_adv_tx_free_in_isr = 0x400031ec;
+r_ble_util_buf_env_deinit = 0x400031f8;
+r_ble_util_buf_env_init = 0x40003204;
+r_ble_util_buf_get_rx_buf_nb = 0x40003210;
+r_ble_util_buf_get_rx_buf_size = 0x4000321c;
+r_ble_util_buf_llcp_tx_alloc = 0x40003228;
+r_ble_util_buf_llcp_tx_free = 0x40003234;
+r_ble_util_buf_rx_alloc = 0x40003240;
+r_ble_util_buf_rx_alloc_in_isr = 0x4000324c;
+r_ble_util_buf_rx_free = 0x40003258;
+r_ble_util_buf_rx_free_in_isr = 0x40003264;
+r_ble_util_buf_set_rx_buf_nb = 0x40003270;
+r_ble_util_buf_set_rx_buf_size = 0x4000327c;
+r_ble_util_data_rx_buf_reset = 0x40003288;
+r_bt_bb_get_intr_mask = 0x40003294;
+r_bt_bb_intr_clear = 0x400032a0;
+r_bt_bb_intr_mask_set = 0x400032ac;
+r_bt_rf_coex_cfg_set = 0x400032c4;
+r_bt_rf_coex_conn_dynamic_pti_en_get = 0x400032d0;
+r_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x400032e8;
+r_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x400032f4;
+r_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40003300;
+r_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x4000330c;
+r_bt_rf_coex_pti_table_get = 0x40003318;
+r_bt_rf_coex_st_param_get = 0x40003324;
+r_bt_rf_coex_st_param_set = 0x40003330;
+r_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x4000333c;
+r_bt_rma_apply_rule_cs_fmt = 0x40003348;
+r_bt_rma_apply_rule_cs_idx = 0x40003354;
+r_bt_rma_configure = 0x40003360;
+r_bt_rma_deregister_rule_cs_fmt = 0x4000336c;
+r_bt_rma_deregister_rule_cs_idx = 0x40003378;
+r_bt_rma_get_ant_by_act = 0x40003384;
+r_bt_rma_init = 0x40003390;
+r_bt_rma_register_rule_cs_fmt = 0x4000339c;
+r_bt_rma_register_rule_cs_idx = 0x400033a8;
+r_bt_rtp_apply_rule_cs_fmt = 0x400033b4;
+r_bt_rtp_apply_rule_cs_idx = 0x400033c0;
+r_bt_rtp_deregister_rule_cs_fmt = 0x400033cc;
+r_bt_rtp_deregister_rule_cs_idx = 0x400033d8;
+r_bt_rtp_init = 0x400033f0;
+r_bt_rtp_register_rule_cs_fmt = 0x400033fc;
+r_bt_rtp_register_rule_cs_idx = 0x40003408;
+r_btdm_isr = 0x40003414;
+r_cali_phase_match_p = 0x40003444;
+r_cmp_abs_time = 0x40003450;
+r_cmp_dest_id = 0x4000345c;
+r_cmp_timer_id = 0x40003468;
+r_co_bdaddr_compare = 0x40003474;
+r_co_ble_pkt_dur_in_us = 0x40003480;
+r_co_list_extract = 0x4000348c;
+r_co_list_extract_after = 0x40003498;
+r_co_list_extract_sublist = 0x400034a4;
+r_co_list_find = 0x400034b0;
+r_co_list_init = 0x400034bc;
+r_co_list_insert_after = 0x400034c8;
+r_co_list_insert_before = 0x400034d4;
+r_co_list_merge = 0x400034e0;
+r_co_list_pool_init = 0x400034ec;
+r_co_list_pop_front = 0x400034f8;
+r_co_list_push_back = 0x40003504;
+r_co_list_push_back_sublist = 0x40003510;
+r_co_list_push_front = 0x4000351c;
+r_co_list_size = 0x40003528;
+r_co_nb_good_le_channels = 0x40003534;
+r_co_util_pack = 0x40003540;
+r_co_util_read_array_size = 0x4000354c;
+r_co_util_unpack = 0x40003558;
+r_dbg_env_deinit = 0x40003564;
+r_dbg_env_init = 0x40003570;
+r_dbg_platform_reset_complete = 0x4000357c;
+r_dl_upd_proc_start = 0x40003588;
+r_dump_data = 0x40003594;
+r_ecc_abort_key256_generation = 0x400035a0;
+r_ecc_gen_new_public_key = 0x400035ac;
+r_ecc_gen_new_secret_key = 0x400035b8;
+r_ecc_generate_key256 = 0x400035c4;
+r_ecc_get_debug_Keys = 0x400035d0;
+r_ecc_init = 0x400035dc;
+r_ecc_is_valid_point = 0x400035e8;
+r_ecc_multiplication_event_handler = 0x400035f4;
+r_ecc_point_multiplication_win_256 = 0x40003600;
+r_emi_alloc_em_mapping_by_offset = 0x4000360c;
+r_emi_base_reg_lut_show = 0x40003618;
+r_emi_em_base_reg_show = 0x40003624;
+r_emi_free_em_mapping_by_offset = 0x40003630;
+r_emi_get_em_mapping_idx_by_offset = 0x4000363c;
+r_emi_get_mem_addr_by_offset = 0x40003648;
+r_emi_overwrite_em_mapping_by_offset = 0x40003654;
+r_esp_vendor_hci_command_handler = 0x40003660;
+r_get_stack_usage = 0x4000366c;
+r_h4tl_acl_hdr_rx_evt_handler = 0x40003678;
+r_h4tl_cmd_hdr_rx_evt_handler = 0x40003684;
+r_h4tl_cmd_pld_rx_evt_handler = 0x40003690;
+r_h4tl_eif_io_event_post = 0x4000369c;
+r_h4tl_eif_register = 0x400036a8;
+r_h4tl_init = 0x400036b4;
+r_h4tl_out_of_sync = 0x400036c0;
+r_h4tl_out_of_sync_check = 0x400036cc;
+r_h4tl_read_hdr = 0x400036d8;
+r_h4tl_read_next_out_of_sync = 0x400036e4;
+r_h4tl_read_payl = 0x400036f0;
+r_h4tl_read_start = 0x400036fc;
+r_h4tl_rx_acl_hdr_extract = 0x40003708;
+r_h4tl_rx_cmd_hdr_extract = 0x40003714;
+r_h4tl_rx_done = 0x40003720;
+r_h4tl_start = 0x4000372c;
+r_h4tl_stop = 0x40003738;
+r_h4tl_tx_done = 0x40003744;
+r_h4tl_tx_evt_handler = 0x40003750;
+r_h4tl_write = 0x4000375c;
+r_hci_acl_tx_data_alloc = 0x40003768;
+r_hci_acl_tx_data_received = 0x40003774;
+r_hci_basic_cmd_send_2_controller = 0x40003780;
+r_hci_ble_adv_report_filter_check = 0x4000378c;
+r_hci_ble_adv_report_tx_check = 0x40003798;
+r_hci_ble_conhdl_register = 0x400037a4;
+r_hci_ble_conhdl_unregister = 0x400037b0;
+r_hci_build_acl_data = 0x400037bc;
+r_hci_build_cc_evt = 0x400037c8;
+r_hci_build_cs_evt = 0x400037d4;
+r_hci_build_evt = 0x400037e0;
+r_hci_build_le_evt = 0x400037ec;
+r_hci_cmd_get_max_param_size = 0x400037f8;
+r_hci_cmd_received = 0x40003804;
+r_hci_cmd_reject = 0x40003810;
+r_hci_evt_mask_check = 0x4000381c;
+r_hci_evt_mask_set = 0x40003828;
+r_hci_fc_acl_buf_size_set = 0x40003834;
+r_hci_fc_acl_en = 0x40003840;
+r_hci_fc_acl_packet_sent = 0x4000384c;
+r_hci_fc_check_host_available_nb_acl_packets = 0x40003858;
+r_hci_fc_host_nb_acl_pkts_complete = 0x40003864;
+r_hci_fc_init = 0x40003870;
+r_hci_look_for_cmd_desc = 0x4000387c;
+r_hci_look_for_evt_desc = 0x40003888;
+r_hci_look_for_le_evt_desc = 0x40003894;
+r_hci_look_for_le_evt_desc_esp = 0x400038a0;
+r_hci_pack_bytes = 0x400038ac;
+r_hci_send_2_controller = 0x400038c4;
+r_hci_send_2_host = 0x400038d0;
+r_hci_tl_c2h_data_flow_on = 0x400038dc;
+r_hci_tl_cmd_hdr_rx_evt_handler = 0x400038e8;
+r_hci_tl_cmd_pld_rx_evt_handler = 0x400038f4;
+r_hci_tl_get_pkt = 0x40003900;
+r_hci_tl_hci_pkt_handler = 0x4000390c;
+r_hci_tl_hci_tx_done_evt_handler = 0x40003918;
+r_hci_tl_inc_nb_h2c_cmd_pkts = 0x40003924;
+r_hci_tl_save_pkt = 0x40003930;
+r_hci_tl_send = 0x4000393c;
+r_hci_tx_done = 0x40003948;
+r_hci_tx_start = 0x40003954;
+r_hci_tx_trigger = 0x40003960;
+r_isValidSecretKey_256 = 0x4000396c;
+r_ke_check_malloc = 0x40003978;
+r_ke_event_callback_set = 0x40003984;
+r_ke_event_clear = 0x40003990;
+r_ke_event_flush = 0x4000399c;
+r_ke_event_get = 0x400039a8;
+r_ke_event_get_all = 0x400039b4;
+r_ke_event_init = 0x400039c0;
+r_ke_event_schedule = 0x400039cc;
+r_ke_event_set = 0x400039d8;
+r_ke_flush = 0x400039e4;
+r_ke_free = 0x400039f0;
+r_ke_handler_search = 0x400039fc;
+r_ke_init = 0x40003a08;
+r_ke_is_free = 0x40003a14;
+r_ke_malloc = 0x40003a20;
+r_ke_mem_init = 0x40003a2c;
+r_ke_mem_is_empty = 0x40003a38;
+r_ke_mem_is_in_heap = 0x40003a44;
+r_ke_msg_alloc = 0x40003a50;
+r_ke_msg_dest_id_get = 0x40003a5c;
+r_ke_msg_discard = 0x40003a68;
+r_ke_msg_forward = 0x40003a74;
+r_ke_msg_forward_new_id = 0x40003a80;
+r_ke_msg_free = 0x40003a8c;
+r_ke_msg_in_queue = 0x40003a98;
+r_ke_msg_save = 0x40003aa4;
+r_ke_msg_send = 0x40003ab0;
+r_ke_msg_send_basic = 0x40003abc;
+r_ke_msg_src_id_get = 0x40003ac8;
+r_ke_queue_extract = 0x40003ad4;
+r_ke_queue_insert = 0x40003ae0;
+r_ke_sleep_check = 0x40003aec;
+r_ke_state_get = 0x40003af8;
+r_ke_state_set = 0x40003b04;
+r_ke_task_check = 0x40003b10;
+r_ke_task_create = 0x40003b1c;
+r_ke_task_delete = 0x40003b28;
+r_ke_task_handler_get = 0x40003b34;
+r_ke_task_init = 0x40003b40;
+r_ke_task_msg_flush = 0x40003b4c;
+r_ke_task_saved_update = 0x40003b58;
+r_ke_time = 0x40003b70;
+r_ke_time_cmp = 0x40003b7c;
+r_ke_time_past = 0x40003b88;
+r_ke_timer_active = 0x40003b94;
+r_ke_timer_adjust_all = 0x40003ba0;
+r_ke_timer_clear = 0x40003bac;
+r_ke_timer_init = 0x40003bb8;
+r_ke_timer_schedule = 0x40003bc4;
+r_ke_timer_set = 0x40003bd0;
+r_led_init = 0x40003bdc;
+r_led_set_all = 0x40003be8;
+r_llc_aes_res_cb = 0x40003bf4;
+r_llc_ch_map_up_proc_err_cb = 0x40003c00;
+r_llc_cleanup = 0x40003c0c;
+r_llc_cmd_cmp_send = 0x40003c18;
+r_llc_cmd_stat_send = 0x40003c24;
+r_llc_con_move_cbk = 0x40003c30;
+r_llc_con_plan_set_update = 0x40003c3c;
+r_llc_con_upd_param_in_range = 0x40003c48;
+r_llc_disconnect = 0x40003c54;
+r_llc_disconnect_end = 0x40003c60;
+r_llc_disconnect_proc_continue = 0x40003c6c;
+r_llc_disconnect_proc_err_cb = 0x40003c78;
+r_llc_dl_chg_check = 0x40003c84;
+r_llc_dle_proc_err_cb = 0x40003c90;
+r_llc_feats_exch_proc_err_cb = 0x40003c9c;
+r_llc_hci_cmd_handler_tab_p_get = 0x40003ca8;
+r_llc_hci_con_param_req_evt_send = 0x40003cc0;
+r_llc_hci_con_upd_info_send = 0x40003ccc;
+r_llc_hci_disconnected_dis = 0x40003cd8;
+r_llc_hci_dl_upd_info_send = 0x40003ce4;
+r_llc_hci_enc_evt_send = 0x40003cf0;
+r_llc_hci_feats_info_send = 0x40003cfc;
+r_llc_hci_le_phy_upd_cmp_evt_send = 0x40003d08;
+r_llc_hci_ltk_request_evt_send = 0x40003d14;
+r_llc_hci_nb_cmp_pkts_evt_send = 0x40003d20;
+r_llc_hci_version_info_send = 0x40003d2c;
+r_llc_init_term_proc = 0x40003d38;
+r_llc_iv_skd_rand_gen = 0x40003d44;
+r_llc_le_ping_proc_continue = 0x40003d50;
+r_llc_le_ping_proc_err_cb = 0x40003d5c;
+/* r_llc_le_ping_restart = 0x40003d68; */
+r_llc_le_ping_set = 0x40003d74;
+r_llc_ll_pause_enc_rsp_ack_handler = 0x40003d80;
+r_llc_ll_reject_ind_ack_handler = 0x40003d8c;
+r_llc_ll_reject_ind_pdu_send = 0x40003d98;
+r_llc_ll_start_enc_rsp_ack_handler = 0x40003da4;
+r_llc_ll_terminate_ind_ack = 0x40003db0;
+r_llc_ll_unknown_ind_handler = 0x40003dbc;
+r_llc_llcp_send = 0x40003dc8;
+r_llc_llcp_state_set = 0x40003dd4;
+r_llc_llcp_trans_timer_set = 0x40003de0;
+r_llc_llcp_tx_check = 0x40003dec;
+/* r_llc_loc_ch_map_proc_continue = 0x40003df8; */
+r_llc_loc_con_upd_proc_err_cb = 0x40003e10;
+r_llc_loc_dl_upd_proc_continue = 0x40003e1c;
+r_llc_loc_encrypt_proc_continue = 0x40003e28;
+r_llc_loc_encrypt_proc_err_cb = 0x40003e34;
+r_llc_loc_feats_exch_proc_continue = 0x40003e40;
+r_llc_loc_phy_upd_proc_err_cb = 0x40003e58;
+r_llc_msg_handler_tab_p_get = 0x40003e64;
+r_llc_pref_param_compute = 0x40003e70;
+r_llc_proc_collision_check = 0x40003e7c;
+r_llc_proc_err_ind = 0x40003e88;
+r_llc_proc_get = 0x40003e94;
+r_llc_proc_id_get = 0x40003ea0;
+r_llc_proc_reg = 0x40003eac;
+r_llc_proc_state_get = 0x40003eb8;
+r_llc_proc_state_set = 0x40003ec4;
+r_llc_proc_timer_pause_set = 0x40003ed0;
+r_llc_proc_timer_set = 0x40003edc;
+r_llc_proc_unreg = 0x40003ee8;
+r_llc_rem_ch_map_proc_continue = 0x40003ef4;
+r_llc_rem_con_upd_proc_err_cb = 0x40003f0c;
+r_llc_rem_dl_upd_proc = 0x40003f18;
+r_llc_rem_encrypt_proc_continue = 0x40003f24;
+r_llc_rem_encrypt_proc_err_cb = 0x40003f30;
+r_llc_rem_phy_upd_proc_continue = 0x40003f3c;
+r_llc_rem_phy_upd_proc_err_cb = 0x40003f48;
+r_llc_role_get = 0x40003f54;
+r_llc_sk_gen = 0x40003f60;
+r_llc_start = 0x40003f6c;
+r_llc_stop = 0x40003f78;
+r_llc_ver_exch_loc_proc_continue = 0x40003f84;
+r_llc_ver_proc_err_cb = 0x40003f90;
+r_llcp_pdu_handler_tab_p_get = 0x40003f9c;
+r_lld_aa_gen = 0x40003fa8;
+r_lld_adv_adv_data_set = 0x40003fb4;
+r_lld_adv_adv_data_update = 0x40003fc0;
+r_lld_adv_aux_ch_idx_set = 0x40003fcc;
+r_lld_adv_aux_evt_canceled_cbk = 0x40003fd8;
+r_lld_adv_aux_evt_start_cbk = 0x40003fe4;
+r_lld_adv_coex_check_ext_adv_synced = 0x40003ff0;
+r_lld_adv_coex_env_reset = 0x40003ffc;
+r_lld_adv_duration_update = 0x40004008;
+r_lld_adv_dynamic_pti_process = 0x40004014;
+r_lld_adv_end = 0x40004020;
+r_lld_adv_evt_canceled_cbk = 0x4000402c;
+r_lld_adv_evt_start_cbk = 0x40004038;
+r_lld_adv_ext_chain_construct = 0x40004044;
+r_lld_adv_ext_pkt_prepare = 0x40004050;
+r_lld_adv_frm_cbk = 0x4000405c;
+r_lld_adv_frm_isr = 0x40004068;
+r_lld_adv_frm_skip_isr = 0x40004074;
+r_lld_adv_init = 0x40004080;
+r_lld_adv_pkt_rx = 0x4000408c;
+r_lld_adv_pkt_rx_connect_ind = 0x40004098;
+r_lld_adv_pkt_rx_send_scan_req_evt = 0x400040a4;
+r_lld_adv_rand_addr_update = 0x400040b0;
+r_lld_adv_restart = 0x400040bc;
+r_lld_adv_scan_rsp_data_set = 0x400040c8;
+r_lld_adv_scan_rsp_data_update = 0x400040d4;
+r_lld_adv_set_tx_power = 0x400040e0;
+r_lld_adv_start = 0x400040ec;
+r_lld_adv_stop = 0x400040f8;
+r_lld_adv_sync_info_set = 0x40004104;
+r_lld_adv_sync_info_update = 0x40004110;
+r_lld_calc_aux_rx = 0x4000411c;
+r_lld_cca_alloc = 0x40004128;
+r_lld_cca_data_reset = 0x40004134;
+r_lld_cca_free = 0x40004140;
+r_lld_ch_assess_data_get = 0x4000414c;
+r_lld_ch_idx_get = 0x40004158;
+r_lld_ch_map_set = 0x40004164;
+r_lld_channel_assess = 0x40004170;
+r_lld_con_activity_act_offset_compute = 0x4000417c;
+r_lld_con_activity_offset_compute = 0x40004188;
+r_lld_con_ch_map_update = 0x40004194;
+r_lld_con_cleanup = 0x400041a0;
+r_lld_con_current_tx_power_get = 0x400041ac;
+r_lld_con_data_flow_set = 0x400041b8;
+r_lld_con_data_len_update = 0x400041c4;
+r_lld_con_data_tx = 0x400041d0;
+r_lld_con_enc_key_load = 0x400041dc;
+r_lld_con_event_counter_get = 0x400041e8;
+r_lld_con_evt_canceled_cbk = 0x400041f4;
+r_lld_con_evt_duration_min_get = 0x40004200;
+r_lld_con_evt_max_eff_time_cal = 0x4000420c;
+r_lld_con_evt_sd_evt_time_get = 0x40004218;
+r_lld_con_evt_start_cbk = 0x40004224;
+r_lld_con_evt_time_update = 0x40004230;
+r_lld_con_free_all_tx_buf = 0x4000423c;
+r_lld_con_frm_cbk = 0x40004248;
+r_lld_con_frm_isr = 0x40004254;
+r_lld_con_frm_skip_isr = 0x40004260;
+r_lld_con_init = 0x4000426c;
+r_lld_con_llcp_tx = 0x40004278;
+r_lld_con_max_lat_calc = 0x40004284;
+r_lld_con_offset_get = 0x40004290;
+r_lld_con_param_update = 0x4000429c;
+r_lld_con_phys_update = 0x400042a8;
+r_lld_con_pref_slave_evt_dur_set = 0x400042b4;
+r_lld_con_pref_slave_latency_set = 0x400042c0;
+r_lld_con_rssi_get = 0x400042cc;
+r_lld_con_rx = 0x400042d8;
+/* r_lld_con_rx_channel_assess = 0x400042e4; */
+r_lld_con_rx_enc = 0x400042f0;
+r_lld_con_rx_isr = 0x400042fc;
+r_lld_con_rx_link_info_check = 0x40004308;
+r_lld_con_rx_llcp_check = 0x40004314;
+r_lld_con_rx_sync_time_update = 0x40004320;
+r_lld_con_set_tx_power = 0x40004338;
+r_lld_con_start = 0x40004344;
+r_lld_con_tx = 0x4000435c;
+r_lld_con_tx_enc = 0x40004368;
+r_lld_con_tx_isr = 0x40004374;
+r_lld_con_tx_len_update = 0x40004380;
+r_lld_con_tx_len_update_for_intv = 0x4000438c;
+r_lld_con_tx_len_update_for_rate = 0x40004398;
+r_lld_con_tx_prog = 0x400043a4;
+r_lld_conn_dynamic_pti_process = 0x400043b0;
+r_lld_continue_scan_rx_isr_end_process = 0x400043bc;
+r_lld_ext_scan_dynamic_pti_process = 0x400043c8;
+r_lld_hw_cca_end_isr = 0x400043d4;
+r_lld_hw_cca_evt_handler = 0x400043e0;
+r_lld_hw_cca_isr = 0x400043ec;
+r_lld_init_cal_anchor_point = 0x400043f8;
+r_lld_init_compute_winoffset = 0x40004404;
+r_lld_init_connect_req_pack = 0x40004410;
+r_lld_init_end = 0x4000441c;
+r_lld_init_evt_canceled_cbk = 0x40004428;
+r_lld_init_evt_start_cbk = 0x40004434;
+r_lld_init_frm_cbk = 0x40004440;
+r_lld_init_frm_eof_isr = 0x4000444c;
+r_lld_init_frm_skip_isr = 0x40004458;
+r_lld_init_init = 0x40004464;
+r_lld_init_process_pkt_rx = 0x40004470;
+r_lld_init_process_pkt_rx_adv_ext_ind = 0x4000447c;
+r_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x40004488;
+r_lld_init_process_pkt_rx_aux_connect_rsp = 0x40004494;
+r_lld_init_process_pkt_tx = 0x400044a0;
+r_lld_init_process_pkt_tx_cal_con_timestamp = 0x400044ac;
+r_lld_init_sched = 0x400044b8;
+r_lld_init_set_tx_power = 0x400044c4;
+r_lld_init_start = 0x400044d0;
+r_lld_init_stop = 0x400044dc;
+r_lld_instant_proc_end = 0x400044e8;
+r_lld_per_adv_ch_map_update = 0x40004500;
+r_lld_per_adv_chain_construct = 0x4000450c;
+r_lld_per_adv_cleanup = 0x40004518;
+r_lld_per_adv_coex_env_reset = 0x40004524;
+r_lld_per_adv_data_set = 0x40004530;
+r_lld_per_adv_data_update = 0x4000453c;
+r_lld_per_adv_dynamic_pti_process = 0x40004548;
+r_lld_per_adv_evt_canceled_cbk = 0x40004554;
+r_lld_per_adv_evt_start_cbk = 0x40004560;
+r_lld_per_adv_ext_pkt_prepare = 0x4000456c;
+r_lld_per_adv_frm_cbk = 0x40004578;
+r_lld_per_adv_frm_isr = 0x40004584;
+r_lld_per_adv_frm_skip_isr = 0x40004590;
+r_lld_per_adv_init = 0x4000459c;
+r_lld_per_adv_init_info_get = 0x400045a8;
+r_lld_per_adv_list_add = 0x400045b4;
+r_lld_per_adv_list_rem = 0x400045c0;
+r_lld_per_adv_set_tx_power = 0x400045d8;
+r_lld_per_adv_start = 0x400045e4;
+r_lld_per_adv_stop = 0x400045f0;
+r_lld_per_adv_sync_info_get = 0x400045fc;
+r_lld_process_cca_data = 0x40004608;
+r_lld_ral_search = 0x40004614;
+r_lld_read_clock = 0x40004620;
+r_lld_res_list_add = 0x4000462c;
+r_lld_res_list_is_empty = 0x40004644;
+r_lld_res_list_local_rpa_get = 0x40004650;
+r_lld_res_list_peer_rpa_get = 0x4000465c;
+r_lld_res_list_peer_update = 0x40004668;
+/* r_lld_res_list_priv_mode_update = 0x40004674; */
+r_lld_reset_reg = 0x4000468c;
+r_lld_rpa_renew = 0x40004698;
+r_lld_rpa_renew_evt_canceled_cbk = 0x400046a4;
+r_lld_rpa_renew_evt_start_cbk = 0x400046b0;
+r_lld_rpa_renew_instant_cbk = 0x400046bc;
+r_lld_rxdesc_check = 0x400046c8;
+r_lld_rxdesc_free = 0x400046d4;
+r_lld_scan_create_sync = 0x400046e0;
+r_lld_scan_create_sync_cancel = 0x400046ec;
+r_lld_scan_end = 0x400046f8;
+r_lld_scan_evt_canceled_cbk = 0x40004704;
+r_lld_scan_evt_start_cbk = 0x40004710;
+r_lld_scan_frm_cbk = 0x4000471c;
+r_lld_scan_frm_eof_isr = 0x40004728;
+r_lld_scan_frm_rx_isr = 0x40004734;
+r_lld_scan_frm_skip_isr = 0x40004740;
+r_lld_scan_init = 0x4000474c;
+r_lld_scan_params_update = 0x40004758;
+r_lld_scan_process_pkt_rx_aux_adv_ind = 0x4000477c;
+r_lld_scan_process_pkt_rx_aux_chain_ind = 0x40004788;
+r_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40004794;
+r_lld_scan_process_pkt_rx_ext_adv = 0x400047a0;
+r_lld_scan_process_pkt_rx_ext_adv_ind = 0x400047ac;
+r_lld_scan_process_pkt_rx_legacy_adv = 0x400047b8;
+r_lld_scan_restart = 0x400047c4;
+r_lld_scan_sched = 0x400047d0;
+r_lld_scan_set_tx_power = 0x400047dc;
+r_lld_scan_start = 0x400047e8;
+r_lld_scan_stop = 0x400047f4;
+r_lld_scan_sync_accept = 0x40004800;
+r_lld_scan_sync_info_unpack = 0x4000480c;
+r_lld_scan_trunc_ind = 0x40004818;
+r_lld_sw_cca_evt_handler = 0x40004824;
+r_lld_sw_cca_isr = 0x40004830;
+r_lld_sync_ch_map_update = 0x4000483c;
+r_lld_sync_cleanup = 0x40004848;
+r_lld_sync_evt_canceled_cbk = 0x40004854;
+r_lld_sync_evt_start_cbk = 0x40004860;
+r_lld_sync_frm_cbk = 0x4000486c;
+r_lld_sync_frm_eof_isr = 0x40004878;
+r_lld_sync_frm_rx_isr = 0x40004884;
+r_lld_sync_frm_skip_isr = 0x40004890;
+r_lld_sync_init = 0x4000489c;
+r_lld_sync_process_pkt_rx = 0x400048a8;
+r_lld_sync_process_pkt_rx_aux_sync_ind = 0x400048b4;
+r_lld_sync_process_pkt_rx_pkt_check = 0x400048c0;
+r_lld_sync_scan_dynamic_pti_process = 0x400048cc;
+r_lld_sync_sched = 0x400048d8;
+r_lld_sync_start = 0x400048e4;
+r_lld_sync_stop = 0x400048f0;
+r_lld_sync_trunc_ind = 0x400048fc;
+r_lld_test_cleanup = 0x40004908;
+r_lld_test_evt_canceled_cbk = 0x40004914;
+r_lld_test_evt_start_cbk = 0x40004920;
+r_lld_test_freq2chnl = 0x4000492c;
+r_lld_test_frm_cbk = 0x40004938;
+r_lld_test_frm_isr = 0x40004944;
+r_lld_test_init = 0x40004950;
+r_lld_test_rx_isr = 0x4000495c;
+r_lld_test_set_tx_power = 0x40004968;
+r_lld_test_start = 0x40004974;
+/* r_lld_test_stop = 0x40004980;*/
+r_lld_update_rxbuf = 0x4000498c;
+r_lld_update_rxbuf_isr = 0x40004998;
+r_lld_white_list_add = 0x400049a4;
+r_lld_white_list_rem = 0x400049b0;
+r_llm_activity_free_get = 0x400049bc;
+r_llm_activity_free_set = 0x400049c8;
+r_llm_activity_syncing_get = 0x400049d4;
+r_llm_adv_con_len_check = 0x400049e0;
+r_llm_adv_hdl_to_id = 0x400049ec;
+r_llm_adv_rep_flow_control_check = 0x400049f8;
+r_llm_adv_rep_flow_control_update = 0x40004a04;
+r_llm_adv_reports_list_check = 0x40004a10;
+r_llm_adv_set_all_release = 0x40004a1c;
+r_llm_adv_set_dft_params = 0x40004a28;
+r_llm_adv_set_release = 0x40004a34;
+r_llm_aes_res_cb = 0x40004a40;
+r_llm_ble_update_adv_flow_control = 0x40004a4c;
+r_llm_ch_map_update = 0x40004a58;
+r_llm_cmd_cmp_send = 0x40004a64;
+r_llm_cmd_stat_send = 0x40004a70;
+r_llm_dev_list_empty_entry = 0x40004a7c;
+r_llm_dev_list_search = 0x40004a88;
+r_llm_env_adv_dup_filt_deinit = 0x40004a94;
+r_llm_env_adv_dup_filt_init = 0x40004aa0;
+r_llm_init_ble_adv_report_flow_contol = 0x40004aac;
+r_llm_is_dev_connected = 0x40004ab8;
+r_llm_is_dev_synced = 0x40004ac4;
+r_llm_is_non_con_act_ongoing_check = 0x40004ad0;
+r_llm_is_wl_accessible = 0x40004adc;
+r_llm_le_evt_mask_check = 0x40004ae8;
+r_llm_link_disc = 0x40004b00;
+r_llm_master_ch_map_get = 0x40004b0c;
+r_llm_msg_handler_tab_p_get = 0x40004b18;
+r_llm_no_activity = 0x40004b24;
+r_llm_per_adv_slot_dur = 0x40004b30;
+r_llm_plan_elt_get = 0x40004b3c;
+r_llm_rx_path_comp_get = 0x40004b48;
+r_llm_scan_start = 0x40004b54;
+r_llm_scan_sync_acad_attach = 0x40004b60;
+r_llm_scan_sync_acad_detach = 0x40004b6c;
+r_llm_send_adv_lost_event_to_host = 0x40004b78;
+r_llm_tx_path_comp_get = 0x40004b84;
+r_misc_deinit = 0x40004b90;
+r_misc_free_em_buf_in_isr = 0x40004b9c;
+r_misc_init = 0x40004ba8;
+r_misc_msg_handler_tab_p_get = 0x40004bb4;
+r_notEqual256 = 0x40004bc0;
+r_phy_upd_proc_start = 0x40004bcc;
+r_platform_reset = 0x40004bd8;
+r_rf_em_init = 0x40004bf0;
+r_rf_force_agc_enable = 0x40004bfc;
+r_rf_reg_rd = 0x40004c08;
+r_rf_reg_wr = 0x40004c14;
+r_rf_reset = 0x40004c20;
+r_rf_rssi_convert = 0x40004c2c;
+r_rf_rw_v9_le_disable = 0x40004c38;
+r_rf_rw_v9_le_enable = 0x40004c44;
+r_rf_sleep = 0x40004c50;
+r_rf_util_cs_fmt_convert = 0x40004c74;
+r_rw_crypto_aes_ccm = 0x40004c80;
+r_rw_crypto_aes_encrypt = 0x40004c8c;
+r_rw_crypto_aes_init = 0x40004c98;
+r_rw_crypto_aes_k1 = 0x40004ca4;
+r_rw_crypto_aes_k2 = 0x40004cb0;
+r_rw_crypto_aes_k3 = 0x40004cbc;
+r_rw_crypto_aes_k4 = 0x40004cc8;
+r_rw_crypto_aes_rand = 0x40004cd4;
+r_rw_crypto_aes_result_handler = 0x40004ce0;
+r_rw_crypto_aes_s1 = 0x40004cec;
+r_rw_cryto_aes_cmac = 0x40004cf8;
+r_rw_v9_init_em_radio_table = 0x40004d04;
+r_rwble_sleep_enter = 0x40004d1c;
+r_rwble_sleep_wakeup_end = 0x40004d28;
+/* r_rwbtdm_isr_wrapper = 0x40004d34; */
+r_rwip_active_check = 0x40004d40;
+r_rwip_aes_encrypt = 0x40004d4c;
+/* r_rwip_assert = 0x40004d58; */
+r_rwip_crypt_evt_handler = 0x40004d64;
+r_rwip_crypt_isr_handler = 0x40004d70;
+r_rwip_eif_get = 0x40004d7c;
+r_rwip_half_slot_2_lpcycles = 0x40004d88;
+r_rwip_hus_2_lpcycles = 0x40004d94;
+r_rwip_isr = 0x40004da0;
+r_rwip_lpcycles_2_hus = 0x40004dac;
+r_rwip_prevent_sleep_clear = 0x40004db8;
+r_rwip_prevent_sleep_set = 0x40004dc4;
+r_rwip_schedule = 0x40004dd0;
+r_rwip_sleep = 0x40004ddc;
+r_rwip_sw_int_handler = 0x40004de8;
+r_rwip_sw_int_req = 0x40004df4;
+r_rwip_time_get = 0x40004e00;
+r_rwip_timer_10ms_handler = 0x40004e0c;
+r_rwip_timer_10ms_set = 0x40004e18;
+r_rwip_timer_hs_handler = 0x40004e24;
+r_rwip_timer_hs_set = 0x40004e30;
+r_rwip_timer_hus_handler = 0x40004e3c;
+r_rwip_timer_hus_set = 0x40004e48;
+r_rwip_wakeup = 0x40004e54;
+/* r_rwip_wakeup_end = 0x40004e60; */
+r_rwip_wlcoex_set = 0x40004e6c;
+r_sch_alarm_clear = 0x40004e78;
+r_sch_alarm_init = 0x40004e84;
+r_sch_alarm_prog = 0x40004e90;
+r_sch_alarm_set = 0x40004e9c;
+r_sch_alarm_timer_isr = 0x40004ea8;
+r_sch_arb_conflict_check = 0x40004eb4;
+r_sch_arb_elt_cancel = 0x40004ec0;
+r_sch_arb_init = 0x40004ed8;
+r_sch_arb_insert = 0x40004ee4;
+r_sch_arb_prog_timer = 0x40004ef0;
+r_sch_arb_remove = 0x40004efc;
+r_sch_arb_sw_isr = 0x40004f08;
+r_sch_plan_chk = 0x40004f14;
+r_sch_plan_clock_wrap_offset_update = 0x40004f20;
+r_sch_plan_init = 0x40004f2c;
+r_sch_plan_interval_req = 0x40004f38;
+r_sch_plan_offset_max_calc = 0x40004f44;
+r_sch_plan_offset_req = 0x40004f50;
+r_sch_plan_position_range_compute = 0x40004f5c;
+r_sch_plan_rem = 0x40004f68;
+r_sch_plan_req = 0x40004f74;
+r_sch_prog_init = 0x40004f98;
+r_sch_prog_push = 0x40004fa4;
+r_sch_prog_rx_isr = 0x40004fb0;
+r_sch_prog_skip_isr = 0x40004fbc;
+r_sch_prog_tx_isr = 0x40004fc8;
+r_sch_slice_bg_add = 0x40004fd4;
+r_sch_slice_bg_remove = 0x40004fe0;
+r_sch_slice_compute = 0x40004fec;
+r_sch_slice_fg_add = 0x40004ff8;
+r_sch_slice_fg_remove = 0x40005004;
+r_sch_slice_init = 0x40005010;
+r_sch_slice_per_add = 0x4000501c;
+r_sch_slice_per_remove = 0x40005028;
+r_sdk_config_get_bt_sleep_enable = 0x40005034;
+r_sdk_config_get_hl_derived_opts = 0x40005040;
+r_sdk_config_get_opts = 0x4000504c;
+r_sdk_config_get_priv_opts = 0x40005058;
+r_sdk_config_set_bt_sleep_enable = 0x40005064;
+r_sdk_config_set_hl_derived_opts = 0x40005070;
+r_sdk_config_set_opts = 0x4000507c;
+r_specialModP256 = 0x40005088;
+r_unloaded_area_init = 0x40005094;
+r_vhci_flow_off = 0x400050a0;
+r_vhci_flow_on = 0x400050ac;
+r_vhci_notify_host_send_available = 0x400050b8;
+r_vhci_send_to_host = 0x400050c4;
+r_vnd_hci_command_handler = 0x400050d0;
+r_vshci_init = 0x400050dc;
+vnd_hci_command_handler_wrapper = 0x400050e8;
+r_lld_legacy_adv_dynamic_pti_get = 0x400050f4;
+r_lld_legacy_adv_dynamic_pti_process = 0x40005100;
+r_lld_ext_adv_dynamic_pti_get = 0x4000510c;
+r_lld_ext_adv_dynamic_aux_pti_process = 0x40005118;
+r_lld_ext_adv_dynamic_pti_process = 0x40005124;
+/*
+r_lld_adv_ext_pkt_prepare_set = 0x40005130;
+*/
+r_lld_adv_ext_chain_connectable_construct = 0x40005148;
+r_lld_adv_pkt_rx_connect_post = 0x40005160;
+r_lld_adv_start_init_evt_param = 0x4000516c;
+r_lld_adv_start_set_cs = 0x40005178;
+/* r_lld_adv_start_update_filter_policy = 0x40005184; */
+r_lld_adv_start_schedule_asap = 0x40005190;
+r_lld_con_tx_prog_new_packet_coex = 0x4000519c;
+r_lld_per_adv_dynamic_pti_get = 0x400051b4;
+r_lld_per_adv_evt_start_chm_upd = 0x400051c0;
+r_lld_ext_scan_dynamic_pti_get = 0x400051cc;
+r_lld_sync_insert = 0x400051e4;
+/*
+r_sch_prog_ble_push = 0x400051f0;
+*/
+r_sch_prog_bt_push = 0x400051fc;
+r_lld_init_evt_end_type_set = 0x40005208;
+r_lld_init_evt_end_type_get = 0x40005214;
+r_lld_adv_direct_adv_use_rpa_addr_state_set = 0x40005220;
+r_lld_adv_direct_adv_use_rpa_addr_state_get = 0x4000522c;
+r_lld_init_evt_end_type_check_state_set = 0x40005238;
+r_lld_init_evt_end_type_check_state_get = 0x40005244;
+
+/* bluetooth hook funcs */
+r_llc_loc_encrypt_proc_continue_hook = 0x40001c60;
+r_llc_loc_phy_upd_proc_continue_hook = 0x40001c64;
+r_llc_rem_phy_upd_proc_continue_hook = 0x40001c68;
+r_lld_scan_frm_eof_isr_hook = 0x40001c6c;
+r_lld_scan_evt_start_cbk_hook = 0x40001c70;
+r_lld_scan_process_pkt_rx_ext_adv_hook = 0x40001c78;
+r_lld_scan_sched_hook = 0x40001c7c;
+r_lld_adv_evt_start_cbk_hook = 0x40001c84;
+r_lld_adv_aux_evt_start_cbk_hook = 0x40001c88;
+r_lld_adv_frm_isr_hook = 0x40001c8c;
+r_lld_adv_start_init_evt_param_hook = 0x40001c90;
+r_lld_con_evt_canceled_cbk_hook = 0x40001c94;
+r_lld_con_frm_isr_hook = 0x40001c98;
+r_lld_con_tx_hook = 0x40001c9c;
+r_lld_con_rx_hook = 0x40001ca0;
+r_lld_con_evt_start_cbk_hook = 0x40001ca4;
+r_lld_con_tx_prog_new_packet_hook = 0x40001cac;
+r_lld_init_frm_eof_isr_hook = 0x40001cb0;
+r_lld_init_evt_start_cbk_hook = 0x40001cb4;
+r_lld_init_sched_hook = 0x40001cbc;
+r_lld_init_process_pkt_tx_hook = 0x40001cc0;
+r_lld_per_adv_evt_start_cbk_hook = 0x40001cc4;
+r_lld_per_adv_frm_isr_hook = 0x40001cc8;
+r_lld_per_adv_start_hook = 0x40001ccc;
+r_lld_sync_frm_eof_isr_hook = 0x40001cd0;
+r_lld_sync_evt_start_cbk_hook = 0x40001cd4;
+r_lld_sync_start_hook = 0x40001cd8;
+r_lld_sync_process_pkt_rx_pkt_check_hook = 0x40001cdc;
+r_sch_arb_insert_hook = 0x40001ce0;
+r_sch_plan_offset_req_hook = 0x40001ce4;
diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
index a8818575a66..a883ee04162 100644
--- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
@@ -458,8 +458,8 @@ ets_get_xtal_freq = 0x40001a7c;
 gpio_input_get = 0x40001a88;
 gpio_matrix_in = 0x40001a94;
 gpio_matrix_out = 0x40001aa0;
-gpio_output_disable = 0x40001aac;
-gpio_output_enable = 0x40001ab8;
+/* gpio_output_disable = 0x40001aac; */
+/* gpio_output_enable = 0x40001ab8; */
 gpio_output_set = 0x40001ac4;
 gpio_pad_hold = 0x40001ad0;
 gpio_pad_input_disable = 0x40001adc;
@@ -776,825 +776,6 @@ rom_usb_osglue = 0x3fceffac;
  Group bluetooth
  ***************************************/
 
-/* Functions */
-bt_rf_coex_get_dft_cfg = 0x40002a78;
-bt_rf_coex_hooks_p_set = 0x40002a84;
-btdm_con_maxevtime_cal_impl = 0x40002a90;
-btdm_controller_get_compile_version_impl = 0x40002a9c;
-btdm_controller_rom_data_init = 0x40002aa8;
-btdm_dis_privacy_err_report_impl = 0x40002ab4;
-btdm_disable_adv_delay_impl = 0x40002ac0;
-btdm_enable_scan_continue_impl = 0x40002acc;
-btdm_enable_scan_forever_impl = 0x40002ad8;
-btdm_get_power_state_impl = 0x40002ae4;
-btdm_get_prevent_sleep_flag_impl = 0x40002af0;
-btdm_power_state_active_impl = 0x40002afc;
-btdm_switch_phy_coded_impl = 0x40002b08;
-hci_acl_data_handler = 0x40002b14;
-hci_disconnect_cmd_handler = 0x40002b20;
-hci_le_con_upd_cmd_handler = 0x40002b2c;
-hci_le_ltk_req_neg_reply_cmd_handler = 0x40002b38;
-hci_le_ltk_req_reply_cmd_handler = 0x40002b44;
-hci_le_rd_chnl_map_cmd_handler = 0x40002b50;
-hci_le_rd_phy_cmd_handler = 0x40002b5c;
-hci_le_rd_rem_feats_cmd_handler = 0x40002b68;
-hci_le_rem_con_param_req_neg_reply_cmd_handler = 0x40002b74;
-hci_le_rem_con_param_req_reply_cmd_handler = 0x40002b80;
-hci_le_set_data_len_cmd_handler = 0x40002b8c;
-hci_le_set_phy_cmd_handler = 0x40002b98;
-hci_le_start_enc_cmd_handler = 0x40002ba4;
-hci_rd_auth_payl_to_cmd_handler = 0x40002bb0;
-hci_rd_rem_ver_info_cmd_handler = 0x40002bbc;
-hci_rd_rssi_cmd_handler = 0x40002bc8;
-hci_rd_tx_pwr_lvl_cmd_handler = 0x40002bd4;
-hci_vs_set_pref_slave_evt_dur_cmd_handler = 0x40002be0;
-hci_vs_set_pref_slave_latency_cmd_handler = 0x40002bec;
-hci_wr_auth_payl_to_cmd_handler = 0x40002bf8;
-ll_channel_map_ind_handler = 0x40002c04;
-ll_connection_param_req_handler = 0x40002c10;
-ll_connection_param_rsp_handler = 0x40002c1c;
-ll_connection_update_ind_handler = 0x40002c28;
-ll_enc_req_handler = 0x40002c34;
-ll_enc_rsp_handler = 0x40002c40;
-ll_feature_req_handler = 0x40002c4c;
-ll_feature_rsp_handler = 0x40002c58;
-ll_length_req_handler = 0x40002c64;
-ll_length_rsp_handler = 0x40002c70;
-ll_min_used_channels_ind_handler = 0x40002c7c;
-ll_pause_enc_req_handler = 0x40002c88;
-ll_pause_enc_rsp_handler = 0x40002c94;
-ll_phy_req_handler = 0x40002ca0;
-ll_phy_rsp_handler = 0x40002cac;
-ll_phy_update_ind_handler = 0x40002cb8;
-ll_ping_req_handler = 0x40002cc4;
-ll_ping_rsp_handler = 0x40002cd0;
-ll_slave_feature_req_handler = 0x40002cdc;
-ll_start_enc_req_handler = 0x40002ce8;
-ll_start_enc_rsp_handler = 0x40002cf4;
-ll_terminate_ind_handler = 0x40002d00;
-ll_version_ind_handler = 0x40002d0c;
-llc_auth_payl_nearly_to_handler = 0x40002d18;
-llc_auth_payl_real_to_handler = 0x40002d24;
-llc_encrypt_ind_handler = 0x40002d30;
-llc_hci_command_handler_wrapper = 0x40002d3c;
-llc_ll_connection_param_req_pdu_send = 0x40002d48;
-llc_ll_connection_param_rsp_pdu_send = 0x40002d54;
-llc_ll_connection_update_ind_pdu_send = 0x40002d60;
-llc_ll_enc_req_pdu_send = 0x40002d6c;
-llc_ll_enc_rsp_pdu_send = 0x40002d78;
-llc_ll_feature_req_pdu_send = 0x40002d84;
-llc_ll_feature_rsp_pdu_send = 0x40002d90;
-llc_ll_length_req_pdu_send = 0x40002d9c;
-llc_ll_length_rsp_pdu_send = 0x40002da8;
-llc_ll_pause_enc_req_pdu_send = 0x40002db4;
-llc_ll_pause_enc_rsp_pdu_send = 0x40002dc0;
-llc_ll_phy_req_pdu_send = 0x40002dcc;
-llc_ll_phy_rsp_pdu_send = 0x40002dd8;
-llc_ll_ping_req_pdu_send = 0x40002de4;
-llc_ll_ping_rsp_pdu_send = 0x40002df0;
-llc_ll_start_enc_req_pdu_send = 0x40002dfc;
-llc_ll_start_enc_rsp_pdu_send = 0x40002e08;
-llc_ll_terminate_ind_pdu_send = 0x40002e14;
-llc_ll_unknown_rsp_pdu_send = 0x40002e20;
-llc_llcp_ch_map_update_ind_pdu_send = 0x40002e2c;
-llc_llcp_phy_upd_ind_pdu_send = 0x40002e38;
-llc_llcp_version_ind_pdu_send = 0x40002e44;
-llc_op_ch_map_upd_ind_handler = 0x40002e50;
-llc_op_con_upd_ind_handler = 0x40002e5c;
-llc_op_disconnect_ind_handler = 0x40002e68;
-llc_op_dl_upd_ind_handler = 0x40002e74;
-llc_op_encrypt_ind_handler = 0x40002e80;
-llc_op_feats_exch_ind_handler = 0x40002e8c;
-llc_op_le_ping_ind_handler = 0x40002e98;
-llc_op_phy_upd_ind_handler = 0x40002ea4;
-llc_op_ver_exch_ind_handler = 0x40002eb0;
-llc_stopped_ind_handler = 0x40002ebc;
-lld_acl_rx_ind_handler = 0x40002ec8;
-lld_acl_tx_cfm_handler = 0x40002ed4;
-lld_adv_end_ind_handler = 0x40002ee0;
-lld_adv_rep_ind_handler = 0x40002eec;
-lld_ch_map_upd_cfm_handler = 0x40002ef8;
-lld_con_estab_ind_handler = 0x40002f04;
-lld_con_evt_sd_evt_time_set = 0x40002f10;
-lld_con_offset_upd_ind_handler = 0x40002f1c;
-lld_con_param_upd_cfm_handler = 0x40002f28;
-lld_disc_ind_handler = 0x40002f34;
-lld_init_end_ind_handler = 0x40002f40;
-lld_llcp_rx_ind_handler_wrapper = 0x40002f4c;
-lld_llcp_tx_cfm_handler = 0x40002f58;
-lld_per_adv_end_ind_handler = 0x40002f64;
-lld_per_adv_rep_ind_handler = 0x40002f70;
-lld_per_adv_rx_end_ind_handler = 0x40002f7c;
-lld_phy_coded_500k_get = 0x40002f88;
-lld_phy_upd_cfm_handler = 0x40002f94;
-lld_scan_end_ind_handler = 0x40002fa0;
-lld_scan_req_ind_handler = 0x40002fac;
-lld_sync_start_req_handler = 0x40002fb8;
-lld_test_end_ind_handler = 0x40002fc4;
-lld_update_rxbuf_handler = 0x40002fd0;
-llm_ch_map_update_ind_handler = 0x40002fdc;
-llm_hci_command_handler_wrapper = 0x40002fe8;
-llm_scan_period_to_handler = 0x40002ff4;
-r_Add2SelfBigHex256 = 0x40003000;
-r_AddBigHex256 = 0x4000300c;
-r_AddBigHexModP256 = 0x40003018;
-r_AddP256 = 0x40003024;
-r_AddPdiv2_256 = 0x40003030;
-r_GF_Jacobian_Point_Addition256 = 0x4000303c;
-r_GF_Jacobian_Point_Double256 = 0x40003048;
-r_GF_Point_Jacobian_To_Affine256 = 0x40003054;
-r_MultiplyBigHexByUint32_256 = 0x40003060;
-r_MultiplyBigHexModP256 = 0x4000306c;
-r_MultiplyByU16ModP256 = 0x40003078;
-r_SubtractBigHex256 = 0x40003084;
-r_SubtractBigHexMod256 = 0x40003090;
-r_SubtractBigHexUint32_256 = 0x4000309c;
-r_SubtractFromSelfBigHex256 = 0x400030a8;
-r_SubtractFromSelfBigHexSign256 = 0x400030b4;
-r_aes_alloc = 0x400030c0;
-r_aes_ccm_continue = 0x400030cc;
-r_aes_ccm_process_e = 0x400030d8;
-r_aes_ccm_xor_128_lsb = 0x400030e4;
-r_aes_ccm_xor_128_msb = 0x400030f0;
-r_aes_cmac_continue = 0x400030fc;
-r_aes_cmac_start = 0x40003108;
-r_aes_k1_continue = 0x40003114;
-r_aes_k2_continue = 0x40003120;
-r_aes_k3_continue = 0x4000312c;
-r_aes_k4_continue = 0x40003138;
-r_aes_shift_left_128 = 0x40003144;
-r_aes_start = 0x40003150;
-r_aes_xor_128 = 0x4000315c;
-r_assert_err = 0x40003168;
-r_assert_param = 0x40003174;
-r_assert_warn = 0x40003180;
-r_bigHexInversion256 = 0x4000318c;
-r_ble_sw_cca_check_isr = 0x40003198;
-r_ble_util_buf_acl_tx_alloc = 0x400031a4;
-r_ble_util_buf_acl_tx_elt_get = 0x400031b0;
-r_ble_util_buf_acl_tx_free = 0x400031bc;
-r_ble_util_buf_acl_tx_free_in_isr = 0x400031c8;
-r_ble_util_buf_adv_tx_alloc = 0x400031d4;
-r_ble_util_buf_adv_tx_free = 0x400031e0;
-r_ble_util_buf_adv_tx_free_in_isr = 0x400031ec;
-r_ble_util_buf_env_deinit = 0x400031f8;
-r_ble_util_buf_env_init = 0x40003204;
-r_ble_util_buf_get_rx_buf_nb = 0x40003210;
-r_ble_util_buf_get_rx_buf_size = 0x4000321c;
-r_ble_util_buf_llcp_tx_alloc = 0x40003228;
-r_ble_util_buf_llcp_tx_free = 0x40003234;
-r_ble_util_buf_rx_alloc = 0x40003240;
-r_ble_util_buf_rx_alloc_in_isr = 0x4000324c;
-r_ble_util_buf_rx_free = 0x40003258;
-r_ble_util_buf_rx_free_in_isr = 0x40003264;
-r_ble_util_buf_set_rx_buf_nb = 0x40003270;
-r_ble_util_buf_set_rx_buf_size = 0x4000327c;
-r_ble_util_data_rx_buf_reset = 0x40003288;
-r_bt_bb_get_intr_mask = 0x40003294;
-r_bt_bb_intr_clear = 0x400032a0;
-r_bt_bb_intr_mask_set = 0x400032ac;
-r_bt_rf_coex_cfg_set = 0x400032c4;
-r_bt_rf_coex_conn_dynamic_pti_en_get = 0x400032d0;
-r_bt_rf_coex_ext_adv_dynamic_pti_en_get = 0x400032e8;
-r_bt_rf_coex_ext_scan_dynamic_pti_en_get = 0x400032f4;
-r_bt_rf_coex_legacy_adv_dynamic_pti_en_get = 0x40003300;
-r_bt_rf_coex_per_adv_dynamic_pti_en_get = 0x4000330c;
-r_bt_rf_coex_pti_table_get = 0x40003318;
-r_bt_rf_coex_st_param_get = 0x40003324;
-r_bt_rf_coex_st_param_set = 0x40003330;
-r_bt_rf_coex_sync_scan_dynamic_pti_en_get = 0x4000333c;
-r_bt_rma_apply_rule_cs_fmt = 0x40003348;
-r_bt_rma_apply_rule_cs_idx = 0x40003354;
-r_bt_rma_configure = 0x40003360;
-r_bt_rma_deregister_rule_cs_fmt = 0x4000336c;
-r_bt_rma_deregister_rule_cs_idx = 0x40003378;
-r_bt_rma_get_ant_by_act = 0x40003384;
-r_bt_rma_init = 0x40003390;
-r_bt_rma_register_rule_cs_fmt = 0x4000339c;
-r_bt_rma_register_rule_cs_idx = 0x400033a8;
-r_bt_rtp_apply_rule_cs_fmt = 0x400033b4;
-r_bt_rtp_apply_rule_cs_idx = 0x400033c0;
-r_bt_rtp_deregister_rule_cs_fmt = 0x400033cc;
-r_bt_rtp_deregister_rule_cs_idx = 0x400033d8;
-r_bt_rtp_init = 0x400033f0;
-r_bt_rtp_register_rule_cs_fmt = 0x400033fc;
-r_bt_rtp_register_rule_cs_idx = 0x40003408;
-r_btdm_isr = 0x40003414;
-r_cali_phase_match_p = 0x40003444;
-r_cmp_abs_time = 0x40003450;
-r_cmp_dest_id = 0x4000345c;
-r_cmp_timer_id = 0x40003468;
-r_co_bdaddr_compare = 0x40003474;
-r_co_ble_pkt_dur_in_us = 0x40003480;
-r_co_list_extract = 0x4000348c;
-r_co_list_extract_after = 0x40003498;
-r_co_list_extract_sublist = 0x400034a4;
-r_co_list_find = 0x400034b0;
-r_co_list_init = 0x400034bc;
-r_co_list_insert_after = 0x400034c8;
-r_co_list_insert_before = 0x400034d4;
-r_co_list_merge = 0x400034e0;
-r_co_list_pool_init = 0x400034ec;
-r_co_list_pop_front = 0x400034f8;
-r_co_list_push_back = 0x40003504;
-r_co_list_push_back_sublist = 0x40003510;
-r_co_list_push_front = 0x4000351c;
-r_co_list_size = 0x40003528;
-r_co_nb_good_le_channels = 0x40003534;
-r_co_util_pack = 0x40003540;
-r_co_util_read_array_size = 0x4000354c;
-r_co_util_unpack = 0x40003558;
-r_dbg_env_deinit = 0x40003564;
-r_dbg_env_init = 0x40003570;
-r_dbg_platform_reset_complete = 0x4000357c;
-r_dl_upd_proc_start = 0x40003588;
-r_dump_data = 0x40003594;
-r_ecc_abort_key256_generation = 0x400035a0;
-r_ecc_gen_new_public_key = 0x400035ac;
-r_ecc_gen_new_secret_key = 0x400035b8;
-r_ecc_generate_key256 = 0x400035c4;
-r_ecc_get_debug_Keys = 0x400035d0;
-r_ecc_init = 0x400035dc;
-r_ecc_is_valid_point = 0x400035e8;
-r_ecc_multiplication_event_handler = 0x400035f4;
-r_ecc_point_multiplication_win_256 = 0x40003600;
-r_emi_alloc_em_mapping_by_offset = 0x4000360c;
-r_emi_base_reg_lut_show = 0x40003618;
-r_emi_em_base_reg_show = 0x40003624;
-r_emi_free_em_mapping_by_offset = 0x40003630;
-r_emi_get_em_mapping_idx_by_offset = 0x4000363c;
-r_emi_get_mem_addr_by_offset = 0x40003648;
-r_emi_overwrite_em_mapping_by_offset = 0x40003654;
-r_esp_vendor_hci_command_handler = 0x40003660;
-r_get_stack_usage = 0x4000366c;
-r_h4tl_acl_hdr_rx_evt_handler = 0x40003678;
-r_h4tl_cmd_hdr_rx_evt_handler = 0x40003684;
-r_h4tl_cmd_pld_rx_evt_handler = 0x40003690;
-r_h4tl_eif_io_event_post = 0x4000369c;
-r_h4tl_eif_register = 0x400036a8;
-r_h4tl_init = 0x400036b4;
-r_h4tl_out_of_sync = 0x400036c0;
-r_h4tl_out_of_sync_check = 0x400036cc;
-r_h4tl_read_hdr = 0x400036d8;
-r_h4tl_read_next_out_of_sync = 0x400036e4;
-r_h4tl_read_payl = 0x400036f0;
-r_h4tl_read_start = 0x400036fc;
-r_h4tl_rx_acl_hdr_extract = 0x40003708;
-r_h4tl_rx_cmd_hdr_extract = 0x40003714;
-r_h4tl_rx_done = 0x40003720;
-r_h4tl_start = 0x4000372c;
-r_h4tl_stop = 0x40003738;
-r_h4tl_tx_done = 0x40003744;
-r_h4tl_tx_evt_handler = 0x40003750;
-r_h4tl_write = 0x4000375c;
-r_hci_acl_tx_data_alloc = 0x40003768;
-r_hci_acl_tx_data_received = 0x40003774;
-r_hci_basic_cmd_send_2_controller = 0x40003780;
-r_hci_ble_adv_report_filter_check = 0x4000378c;
-r_hci_ble_adv_report_tx_check = 0x40003798;
-r_hci_ble_conhdl_register = 0x400037a4;
-r_hci_ble_conhdl_unregister = 0x400037b0;
-r_hci_build_acl_data = 0x400037bc;
-r_hci_build_cc_evt = 0x400037c8;
-r_hci_build_cs_evt = 0x400037d4;
-r_hci_build_evt = 0x400037e0;
-r_hci_build_le_evt = 0x400037ec;
-r_hci_cmd_get_max_param_size = 0x400037f8;
-r_hci_cmd_received = 0x40003804;
-r_hci_cmd_reject = 0x40003810;
-r_hci_evt_mask_check = 0x4000381c;
-r_hci_evt_mask_set = 0x40003828;
-r_hci_fc_acl_buf_size_set = 0x40003834;
-r_hci_fc_acl_en = 0x40003840;
-r_hci_fc_acl_packet_sent = 0x4000384c;
-r_hci_fc_check_host_available_nb_acl_packets = 0x40003858;
-r_hci_fc_host_nb_acl_pkts_complete = 0x40003864;
-r_hci_fc_init = 0x40003870;
-r_hci_look_for_cmd_desc = 0x4000387c;
-r_hci_look_for_evt_desc = 0x40003888;
-r_hci_look_for_le_evt_desc = 0x40003894;
-r_hci_look_for_le_evt_desc_esp = 0x400038a0;
-r_hci_pack_bytes = 0x400038ac;
-r_hci_send_2_controller = 0x400038c4;
-r_hci_send_2_host = 0x400038d0;
-r_hci_tl_c2h_data_flow_on = 0x400038dc;
-r_hci_tl_cmd_hdr_rx_evt_handler = 0x400038e8;
-r_hci_tl_cmd_pld_rx_evt_handler = 0x400038f4;
-r_hci_tl_get_pkt = 0x40003900;
-r_hci_tl_hci_pkt_handler = 0x4000390c;
-r_hci_tl_hci_tx_done_evt_handler = 0x40003918;
-r_hci_tl_inc_nb_h2c_cmd_pkts = 0x40003924;
-r_hci_tl_save_pkt = 0x40003930;
-r_hci_tl_send = 0x4000393c;
-r_hci_tx_done = 0x40003948;
-r_hci_tx_start = 0x40003954;
-r_hci_tx_trigger = 0x40003960;
-r_isValidSecretKey_256 = 0x4000396c;
-r_ke_check_malloc = 0x40003978;
-r_ke_event_callback_set = 0x40003984;
-r_ke_event_clear = 0x40003990;
-r_ke_event_flush = 0x4000399c;
-r_ke_event_get = 0x400039a8;
-r_ke_event_get_all = 0x400039b4;
-r_ke_event_init = 0x400039c0;
-r_ke_event_schedule = 0x400039cc;
-r_ke_event_set = 0x400039d8;
-r_ke_flush = 0x400039e4;
-r_ke_free = 0x400039f0;
-r_ke_handler_search = 0x400039fc;
-r_ke_init = 0x40003a08;
-r_ke_is_free = 0x40003a14;
-r_ke_malloc = 0x40003a20;
-r_ke_mem_init = 0x40003a2c;
-r_ke_mem_is_empty = 0x40003a38;
-r_ke_mem_is_in_heap = 0x40003a44;
-r_ke_msg_alloc = 0x40003a50;
-r_ke_msg_dest_id_get = 0x40003a5c;
-r_ke_msg_discard = 0x40003a68;
-r_ke_msg_forward = 0x40003a74;
-r_ke_msg_forward_new_id = 0x40003a80;
-r_ke_msg_free = 0x40003a8c;
-r_ke_msg_in_queue = 0x40003a98;
-r_ke_msg_save = 0x40003aa4;
-r_ke_msg_send = 0x40003ab0;
-r_ke_msg_send_basic = 0x40003abc;
-r_ke_msg_src_id_get = 0x40003ac8;
-r_ke_queue_extract = 0x40003ad4;
-r_ke_queue_insert = 0x40003ae0;
-r_ke_sleep_check = 0x40003aec;
-r_ke_state_get = 0x40003af8;
-r_ke_state_set = 0x40003b04;
-r_ke_task_check = 0x40003b10;
-r_ke_task_create = 0x40003b1c;
-r_ke_task_delete = 0x40003b28;
-r_ke_task_handler_get = 0x40003b34;
-r_ke_task_init = 0x40003b40;
-r_ke_task_msg_flush = 0x40003b4c;
-r_ke_task_saved_update = 0x40003b58;
-r_ke_time = 0x40003b70;
-r_ke_time_cmp = 0x40003b7c;
-r_ke_time_past = 0x40003b88;
-r_ke_timer_active = 0x40003b94;
-r_ke_timer_adjust_all = 0x40003ba0;
-r_ke_timer_clear = 0x40003bac;
-r_ke_timer_init = 0x40003bb8;
-r_ke_timer_schedule = 0x40003bc4;
-r_ke_timer_set = 0x40003bd0;
-r_led_init = 0x40003bdc;
-r_led_set_all = 0x40003be8;
-r_llc_aes_res_cb = 0x40003bf4;
-r_llc_ch_map_up_proc_err_cb = 0x40003c00;
-r_llc_cleanup = 0x40003c0c;
-r_llc_cmd_cmp_send = 0x40003c18;
-r_llc_cmd_stat_send = 0x40003c24;
-r_llc_con_move_cbk = 0x40003c30;
-r_llc_con_plan_set_update = 0x40003c3c;
-r_llc_con_upd_param_in_range = 0x40003c48;
-r_llc_disconnect = 0x40003c54;
-r_llc_disconnect_end = 0x40003c60;
-r_llc_disconnect_proc_continue = 0x40003c6c;
-r_llc_disconnect_proc_err_cb = 0x40003c78;
-r_llc_dl_chg_check = 0x40003c84;
-r_llc_dle_proc_err_cb = 0x40003c90;
-r_llc_feats_exch_proc_err_cb = 0x40003c9c;
-r_llc_hci_cmd_handler_tab_p_get = 0x40003ca8;
-r_llc_hci_con_param_req_evt_send = 0x40003cc0;
-r_llc_hci_con_upd_info_send = 0x40003ccc;
-r_llc_hci_disconnected_dis = 0x40003cd8;
-r_llc_hci_dl_upd_info_send = 0x40003ce4;
-r_llc_hci_enc_evt_send = 0x40003cf0;
-r_llc_hci_feats_info_send = 0x40003cfc;
-r_llc_hci_le_phy_upd_cmp_evt_send = 0x40003d08;
-r_llc_hci_ltk_request_evt_send = 0x40003d14;
-r_llc_hci_nb_cmp_pkts_evt_send = 0x40003d20;
-r_llc_hci_version_info_send = 0x40003d2c;
-r_llc_init_term_proc = 0x40003d38;
-r_llc_iv_skd_rand_gen = 0x40003d44;
-r_llc_le_ping_proc_continue = 0x40003d50;
-r_llc_le_ping_proc_err_cb = 0x40003d5c;
-/* r_llc_le_ping_restart = 0x40003d68; */
-r_llc_le_ping_set = 0x40003d74;
-r_llc_ll_pause_enc_rsp_ack_handler = 0x40003d80;
-r_llc_ll_reject_ind_ack_handler = 0x40003d8c;
-r_llc_ll_reject_ind_pdu_send = 0x40003d98;
-r_llc_ll_start_enc_rsp_ack_handler = 0x40003da4;
-r_llc_ll_terminate_ind_ack = 0x40003db0;
-r_llc_ll_unknown_ind_handler = 0x40003dbc;
-r_llc_llcp_send = 0x40003dc8;
-r_llc_llcp_state_set = 0x40003dd4;
-r_llc_llcp_trans_timer_set = 0x40003de0;
-r_llc_llcp_tx_check = 0x40003dec;
-/* r_llc_loc_ch_map_proc_continue = 0x40003df8; */
-r_llc_loc_con_upd_proc_err_cb = 0x40003e10;
-r_llc_loc_dl_upd_proc_continue = 0x40003e1c;
-r_llc_loc_encrypt_proc_continue = 0x40003e28;
-r_llc_loc_encrypt_proc_err_cb = 0x40003e34;
-r_llc_loc_feats_exch_proc_continue = 0x40003e40;
-r_llc_loc_phy_upd_proc_err_cb = 0x40003e58;
-r_llc_msg_handler_tab_p_get = 0x40003e64;
-r_llc_pref_param_compute = 0x40003e70;
-r_llc_proc_collision_check = 0x40003e7c;
-r_llc_proc_err_ind = 0x40003e88;
-r_llc_proc_get = 0x40003e94;
-r_llc_proc_id_get = 0x40003ea0;
-r_llc_proc_reg = 0x40003eac;
-r_llc_proc_state_get = 0x40003eb8;
-r_llc_proc_state_set = 0x40003ec4;
-r_llc_proc_timer_pause_set = 0x40003ed0;
-r_llc_proc_timer_set = 0x40003edc;
-r_llc_proc_unreg = 0x40003ee8;
-r_llc_rem_ch_map_proc_continue = 0x40003ef4;
-r_llc_rem_con_upd_proc_err_cb = 0x40003f0c;
-r_llc_rem_dl_upd_proc = 0x40003f18;
-r_llc_rem_encrypt_proc_continue = 0x40003f24;
-r_llc_rem_encrypt_proc_err_cb = 0x40003f30;
-r_llc_rem_phy_upd_proc_continue = 0x40003f3c;
-r_llc_rem_phy_upd_proc_err_cb = 0x40003f48;
-r_llc_role_get = 0x40003f54;
-r_llc_sk_gen = 0x40003f60;
-r_llc_start = 0x40003f6c;
-r_llc_stop = 0x40003f78;
-r_llc_ver_exch_loc_proc_continue = 0x40003f84;
-r_llc_ver_proc_err_cb = 0x40003f90;
-r_llcp_pdu_handler_tab_p_get = 0x40003f9c;
-r_lld_aa_gen = 0x40003fa8;
-r_lld_adv_adv_data_set = 0x40003fb4;
-r_lld_adv_adv_data_update = 0x40003fc0;
-r_lld_adv_aux_ch_idx_set = 0x40003fcc;
-r_lld_adv_aux_evt_canceled_cbk = 0x40003fd8;
-r_lld_adv_aux_evt_start_cbk = 0x40003fe4;
-r_lld_adv_coex_check_ext_adv_synced = 0x40003ff0;
-r_lld_adv_coex_env_reset = 0x40003ffc;
-r_lld_adv_duration_update = 0x40004008;
-r_lld_adv_dynamic_pti_process = 0x40004014;
-r_lld_adv_end = 0x40004020;
-r_lld_adv_evt_canceled_cbk = 0x4000402c;
-r_lld_adv_evt_start_cbk = 0x40004038;
-r_lld_adv_ext_chain_construct = 0x40004044;
-r_lld_adv_ext_pkt_prepare = 0x40004050;
-r_lld_adv_frm_cbk = 0x4000405c;
-r_lld_adv_frm_isr = 0x40004068;
-r_lld_adv_frm_skip_isr = 0x40004074;
-r_lld_adv_init = 0x40004080;
-r_lld_adv_pkt_rx = 0x4000408c;
-r_lld_adv_pkt_rx_connect_ind = 0x40004098;
-r_lld_adv_pkt_rx_send_scan_req_evt = 0x400040a4;
-r_lld_adv_rand_addr_update = 0x400040b0;
-r_lld_adv_restart = 0x400040bc;
-r_lld_adv_scan_rsp_data_set = 0x400040c8;
-r_lld_adv_scan_rsp_data_update = 0x400040d4;
-r_lld_adv_set_tx_power = 0x400040e0;
-r_lld_adv_start = 0x400040ec;
-r_lld_adv_stop = 0x400040f8;
-r_lld_adv_sync_info_set = 0x40004104;
-r_lld_adv_sync_info_update = 0x40004110;
-r_lld_calc_aux_rx = 0x4000411c;
-r_lld_cca_alloc = 0x40004128;
-r_lld_cca_data_reset = 0x40004134;
-r_lld_cca_free = 0x40004140;
-r_lld_ch_assess_data_get = 0x4000414c;
-r_lld_ch_idx_get = 0x40004158;
-r_lld_ch_map_set = 0x40004164;
-r_lld_channel_assess = 0x40004170;
-r_lld_con_activity_act_offset_compute = 0x4000417c;
-r_lld_con_activity_offset_compute = 0x40004188;
-r_lld_con_ch_map_update = 0x40004194;
-r_lld_con_cleanup = 0x400041a0;
-r_lld_con_current_tx_power_get = 0x400041ac;
-r_lld_con_data_flow_set = 0x400041b8;
-r_lld_con_data_len_update = 0x400041c4;
-r_lld_con_data_tx = 0x400041d0;
-r_lld_con_enc_key_load = 0x400041dc;
-r_lld_con_event_counter_get = 0x400041e8;
-r_lld_con_evt_canceled_cbk = 0x400041f4;
-r_lld_con_evt_duration_min_get = 0x40004200;
-r_lld_con_evt_max_eff_time_cal = 0x4000420c;
-r_lld_con_evt_sd_evt_time_get = 0x40004218;
-r_lld_con_evt_start_cbk = 0x40004224;
-r_lld_con_evt_time_update = 0x40004230;
-r_lld_con_free_all_tx_buf = 0x4000423c;
-r_lld_con_frm_cbk = 0x40004248;
-r_lld_con_frm_isr = 0x40004254;
-r_lld_con_frm_skip_isr = 0x40004260;
-r_lld_con_init = 0x4000426c;
-r_lld_con_llcp_tx = 0x40004278;
-r_lld_con_max_lat_calc = 0x40004284;
-r_lld_con_offset_get = 0x40004290;
-r_lld_con_param_update = 0x4000429c;
-r_lld_con_phys_update = 0x400042a8;
-r_lld_con_pref_slave_evt_dur_set = 0x400042b4;
-r_lld_con_pref_slave_latency_set = 0x400042c0;
-r_lld_con_rssi_get = 0x400042cc;
-r_lld_con_rx = 0x400042d8;
-/* r_lld_con_rx_channel_assess = 0x400042e4; */
-r_lld_con_rx_enc = 0x400042f0;
-r_lld_con_rx_isr = 0x400042fc;
-r_lld_con_rx_link_info_check = 0x40004308;
-r_lld_con_rx_llcp_check = 0x40004314;
-r_lld_con_rx_sync_time_update = 0x40004320;
-r_lld_con_set_tx_power = 0x40004338;
-r_lld_con_start = 0x40004344;
-r_lld_con_tx = 0x4000435c;
-r_lld_con_tx_enc = 0x40004368;
-r_lld_con_tx_isr = 0x40004374;
-r_lld_con_tx_len_update = 0x40004380;
-r_lld_con_tx_len_update_for_intv = 0x4000438c;
-r_lld_con_tx_len_update_for_rate = 0x40004398;
-r_lld_con_tx_prog = 0x400043a4;
-r_lld_conn_dynamic_pti_process = 0x400043b0;
-r_lld_continue_scan_rx_isr_end_process = 0x400043bc;
-r_lld_ext_scan_dynamic_pti_process = 0x400043c8;
-r_lld_hw_cca_end_isr = 0x400043d4;
-r_lld_hw_cca_evt_handler = 0x400043e0;
-r_lld_hw_cca_isr = 0x400043ec;
-r_lld_init_cal_anchor_point = 0x400043f8;
-r_lld_init_compute_winoffset = 0x40004404;
-r_lld_init_connect_req_pack = 0x40004410;
-r_lld_init_end = 0x4000441c;
-r_lld_init_evt_canceled_cbk = 0x40004428;
-r_lld_init_evt_start_cbk = 0x40004434;
-r_lld_init_frm_cbk = 0x40004440;
-r_lld_init_frm_eof_isr = 0x4000444c;
-r_lld_init_frm_skip_isr = 0x40004458;
-r_lld_init_init = 0x40004464;
-r_lld_init_process_pkt_rx = 0x40004470;
-r_lld_init_process_pkt_rx_adv_ext_ind = 0x4000447c;
-r_lld_init_process_pkt_rx_adv_ind_or_direct_ind = 0x40004488;
-r_lld_init_process_pkt_rx_aux_connect_rsp = 0x40004494;
-r_lld_init_process_pkt_tx = 0x400044a0;
-r_lld_init_process_pkt_tx_cal_con_timestamp = 0x400044ac;
-r_lld_init_sched = 0x400044b8;
-r_lld_init_set_tx_power = 0x400044c4;
-r_lld_init_start = 0x400044d0;
-r_lld_init_stop = 0x400044dc;
-r_lld_instant_proc_end = 0x400044e8;
-r_lld_per_adv_ch_map_update = 0x40004500;
-r_lld_per_adv_chain_construct = 0x4000450c;
-r_lld_per_adv_cleanup = 0x40004518;
-r_lld_per_adv_coex_env_reset = 0x40004524;
-r_lld_per_adv_data_set = 0x40004530;
-r_lld_per_adv_data_update = 0x4000453c;
-r_lld_per_adv_dynamic_pti_process = 0x40004548;
-r_lld_per_adv_evt_canceled_cbk = 0x40004554;
-r_lld_per_adv_evt_start_cbk = 0x40004560;
-r_lld_per_adv_ext_pkt_prepare = 0x4000456c;
-r_lld_per_adv_frm_cbk = 0x40004578;
-r_lld_per_adv_frm_isr = 0x40004584;
-r_lld_per_adv_frm_skip_isr = 0x40004590;
-r_lld_per_adv_init = 0x4000459c;
-r_lld_per_adv_init_info_get = 0x400045a8;
-r_lld_per_adv_list_add = 0x400045b4;
-r_lld_per_adv_list_rem = 0x400045c0;
-r_lld_per_adv_set_tx_power = 0x400045d8;
-r_lld_per_adv_start = 0x400045e4;
-r_lld_per_adv_stop = 0x400045f0;
-r_lld_per_adv_sync_info_get = 0x400045fc;
-r_lld_process_cca_data = 0x40004608;
-r_lld_ral_search = 0x40004614;
-r_lld_read_clock = 0x40004620;
-r_lld_res_list_add = 0x4000462c;
-r_lld_res_list_is_empty = 0x40004644;
-r_lld_res_list_local_rpa_get = 0x40004650;
-r_lld_res_list_peer_rpa_get = 0x4000465c;
-r_lld_res_list_peer_update = 0x40004668;
-/* r_lld_res_list_priv_mode_update = 0x40004674; */
-r_lld_reset_reg = 0x4000468c;
-r_lld_rpa_renew = 0x40004698;
-r_lld_rpa_renew_evt_canceled_cbk = 0x400046a4;
-r_lld_rpa_renew_evt_start_cbk = 0x400046b0;
-r_lld_rpa_renew_instant_cbk = 0x400046bc;
-r_lld_rxdesc_check = 0x400046c8;
-r_lld_rxdesc_free = 0x400046d4;
-r_lld_scan_create_sync = 0x400046e0;
-r_lld_scan_create_sync_cancel = 0x400046ec;
-r_lld_scan_end = 0x400046f8;
-r_lld_scan_evt_canceled_cbk = 0x40004704;
-r_lld_scan_evt_start_cbk = 0x40004710;
-r_lld_scan_frm_cbk = 0x4000471c;
-r_lld_scan_frm_eof_isr = 0x40004728;
-r_lld_scan_frm_rx_isr = 0x40004734;
-r_lld_scan_frm_skip_isr = 0x40004740;
-r_lld_scan_init = 0x4000474c;
-r_lld_scan_params_update = 0x40004758;
-r_lld_scan_process_pkt_rx_aux_adv_ind = 0x4000477c;
-r_lld_scan_process_pkt_rx_aux_chain_ind = 0x40004788;
-r_lld_scan_process_pkt_rx_aux_scan_rsp = 0x40004794;
-r_lld_scan_process_pkt_rx_ext_adv = 0x400047a0;
-r_lld_scan_process_pkt_rx_ext_adv_ind = 0x400047ac;
-r_lld_scan_process_pkt_rx_legacy_adv = 0x400047b8;
-r_lld_scan_restart = 0x400047c4;
-r_lld_scan_sched = 0x400047d0;
-r_lld_scan_set_tx_power = 0x400047dc;
-r_lld_scan_start = 0x400047e8;
-r_lld_scan_stop = 0x400047f4;
-r_lld_scan_sync_accept = 0x40004800;
-r_lld_scan_sync_info_unpack = 0x4000480c;
-r_lld_scan_trunc_ind = 0x40004818;
-r_lld_sw_cca_evt_handler = 0x40004824;
-r_lld_sw_cca_isr = 0x40004830;
-r_lld_sync_ch_map_update = 0x4000483c;
-r_lld_sync_cleanup = 0x40004848;
-r_lld_sync_evt_canceled_cbk = 0x40004854;
-r_lld_sync_evt_start_cbk = 0x40004860;
-r_lld_sync_frm_cbk = 0x4000486c;
-r_lld_sync_frm_eof_isr = 0x40004878;
-r_lld_sync_frm_rx_isr = 0x40004884;
-r_lld_sync_frm_skip_isr = 0x40004890;
-r_lld_sync_init = 0x4000489c;
-r_lld_sync_process_pkt_rx = 0x400048a8;
-r_lld_sync_process_pkt_rx_aux_sync_ind = 0x400048b4;
-r_lld_sync_process_pkt_rx_pkt_check = 0x400048c0;
-r_lld_sync_scan_dynamic_pti_process = 0x400048cc;
-r_lld_sync_sched = 0x400048d8;
-r_lld_sync_start = 0x400048e4;
-r_lld_sync_stop = 0x400048f0;
-r_lld_sync_trunc_ind = 0x400048fc;
-r_lld_test_cleanup = 0x40004908;
-r_lld_test_evt_canceled_cbk = 0x40004914;
-r_lld_test_evt_start_cbk = 0x40004920;
-r_lld_test_freq2chnl = 0x4000492c;
-r_lld_test_frm_cbk = 0x40004938;
-r_lld_test_frm_isr = 0x40004944;
-r_lld_test_init = 0x40004950;
-r_lld_test_rx_isr = 0x4000495c;
-r_lld_test_set_tx_power = 0x40004968;
-r_lld_test_start = 0x40004974;
-/* r_lld_test_stop = 0x40004980;*/
-r_lld_update_rxbuf = 0x4000498c;
-r_lld_update_rxbuf_isr = 0x40004998;
-r_lld_white_list_add = 0x400049a4;
-r_lld_white_list_rem = 0x400049b0;
-r_llm_activity_free_get = 0x400049bc;
-r_llm_activity_free_set = 0x400049c8;
-r_llm_activity_syncing_get = 0x400049d4;
-r_llm_adv_con_len_check = 0x400049e0;
-r_llm_adv_hdl_to_id = 0x400049ec;
-r_llm_adv_rep_flow_control_check = 0x400049f8;
-r_llm_adv_rep_flow_control_update = 0x40004a04;
-r_llm_adv_reports_list_check = 0x40004a10;
-r_llm_adv_set_all_release = 0x40004a1c;
-r_llm_adv_set_dft_params = 0x40004a28;
-r_llm_adv_set_release = 0x40004a34;
-r_llm_aes_res_cb = 0x40004a40;
-r_llm_ble_update_adv_flow_control = 0x40004a4c;
-r_llm_ch_map_update = 0x40004a58;
-r_llm_cmd_cmp_send = 0x40004a64;
-r_llm_cmd_stat_send = 0x40004a70;
-r_llm_dev_list_empty_entry = 0x40004a7c;
-r_llm_dev_list_search = 0x40004a88;
-r_llm_env_adv_dup_filt_deinit = 0x40004a94;
-r_llm_env_adv_dup_filt_init = 0x40004aa0;
-r_llm_init_ble_adv_report_flow_contol = 0x40004aac;
-r_llm_is_dev_connected = 0x40004ab8;
-r_llm_is_dev_synced = 0x40004ac4;
-r_llm_is_non_con_act_ongoing_check = 0x40004ad0;
-r_llm_is_wl_accessible = 0x40004adc;
-r_llm_le_evt_mask_check = 0x40004ae8;
-r_llm_link_disc = 0x40004b00;
-r_llm_master_ch_map_get = 0x40004b0c;
-r_llm_msg_handler_tab_p_get = 0x40004b18;
-r_llm_no_activity = 0x40004b24;
-r_llm_per_adv_slot_dur = 0x40004b30;
-r_llm_plan_elt_get = 0x40004b3c;
-r_llm_rx_path_comp_get = 0x40004b48;
-r_llm_scan_start = 0x40004b54;
-r_llm_scan_sync_acad_attach = 0x40004b60;
-r_llm_scan_sync_acad_detach = 0x40004b6c;
-r_llm_send_adv_lost_event_to_host = 0x40004b78;
-r_llm_tx_path_comp_get = 0x40004b84;
-r_misc_deinit = 0x40004b90;
-r_misc_free_em_buf_in_isr = 0x40004b9c;
-r_misc_init = 0x40004ba8;
-r_misc_msg_handler_tab_p_get = 0x40004bb4;
-r_notEqual256 = 0x40004bc0;
-r_phy_upd_proc_start = 0x40004bcc;
-r_platform_reset = 0x40004bd8;
-r_rf_em_init = 0x40004bf0;
-r_rf_force_agc_enable = 0x40004bfc;
-r_rf_reg_rd = 0x40004c08;
-r_rf_reg_wr = 0x40004c14;
-r_rf_reset = 0x40004c20;
-r_rf_rssi_convert = 0x40004c2c;
-r_rf_rw_v9_le_disable = 0x40004c38;
-r_rf_rw_v9_le_enable = 0x40004c44;
-r_rf_sleep = 0x40004c50;
-r_rf_util_cs_fmt_convert = 0x40004c74;
-r_rw_crypto_aes_ccm = 0x40004c80;
-r_rw_crypto_aes_encrypt = 0x40004c8c;
-r_rw_crypto_aes_init = 0x40004c98;
-r_rw_crypto_aes_k1 = 0x40004ca4;
-r_rw_crypto_aes_k2 = 0x40004cb0;
-r_rw_crypto_aes_k3 = 0x40004cbc;
-r_rw_crypto_aes_k4 = 0x40004cc8;
-r_rw_crypto_aes_rand = 0x40004cd4;
-r_rw_crypto_aes_result_handler = 0x40004ce0;
-r_rw_crypto_aes_s1 = 0x40004cec;
-r_rw_cryto_aes_cmac = 0x40004cf8;
-r_rw_v9_init_em_radio_table = 0x40004d04;
-r_rwble_sleep_enter = 0x40004d1c;
-r_rwble_sleep_wakeup_end = 0x40004d28;
-/* r_rwbtdm_isr_wrapper = 0x40004d34; */
-r_rwip_active_check = 0x40004d40;
-r_rwip_aes_encrypt = 0x40004d4c;
-/* r_rwip_assert = 0x40004d58; */
-r_rwip_crypt_evt_handler = 0x40004d64;
-r_rwip_crypt_isr_handler = 0x40004d70;
-r_rwip_eif_get = 0x40004d7c;
-r_rwip_half_slot_2_lpcycles = 0x40004d88;
-r_rwip_hus_2_lpcycles = 0x40004d94;
-r_rwip_isr = 0x40004da0;
-r_rwip_lpcycles_2_hus = 0x40004dac;
-r_rwip_prevent_sleep_clear = 0x40004db8;
-r_rwip_prevent_sleep_set = 0x40004dc4;
-r_rwip_schedule = 0x40004dd0;
-r_rwip_sleep = 0x40004ddc;
-r_rwip_sw_int_handler = 0x40004de8;
-r_rwip_sw_int_req = 0x40004df4;
-r_rwip_time_get = 0x40004e00;
-r_rwip_timer_10ms_handler = 0x40004e0c;
-r_rwip_timer_10ms_set = 0x40004e18;
-r_rwip_timer_hs_handler = 0x40004e24;
-r_rwip_timer_hs_set = 0x40004e30;
-r_rwip_timer_hus_handler = 0x40004e3c;
-r_rwip_timer_hus_set = 0x40004e48;
-r_rwip_wakeup = 0x40004e54;
-/* r_rwip_wakeup_end = 0x40004e60; */
-r_rwip_wlcoex_set = 0x40004e6c;
-r_sch_alarm_clear = 0x40004e78;
-r_sch_alarm_init = 0x40004e84;
-r_sch_alarm_prog = 0x40004e90;
-r_sch_alarm_set = 0x40004e9c;
-r_sch_alarm_timer_isr = 0x40004ea8;
-r_sch_arb_conflict_check = 0x40004eb4;
-r_sch_arb_elt_cancel = 0x40004ec0;
-r_sch_arb_init = 0x40004ed8;
-r_sch_arb_insert = 0x40004ee4;
-r_sch_arb_prog_timer = 0x40004ef0;
-r_sch_arb_remove = 0x40004efc;
-r_sch_arb_sw_isr = 0x40004f08;
-r_sch_plan_chk = 0x40004f14;
-r_sch_plan_clock_wrap_offset_update = 0x40004f20;
-r_sch_plan_init = 0x40004f2c;
-r_sch_plan_interval_req = 0x40004f38;
-r_sch_plan_offset_max_calc = 0x40004f44;
-r_sch_plan_offset_req = 0x40004f50;
-r_sch_plan_position_range_compute = 0x40004f5c;
-r_sch_plan_rem = 0x40004f68;
-r_sch_plan_req = 0x40004f74;
-r_sch_prog_init = 0x40004f98;
-r_sch_prog_push = 0x40004fa4;
-r_sch_prog_rx_isr = 0x40004fb0;
-r_sch_prog_skip_isr = 0x40004fbc;
-r_sch_prog_tx_isr = 0x40004fc8;
-r_sch_slice_bg_add = 0x40004fd4;
-r_sch_slice_bg_remove = 0x40004fe0;
-r_sch_slice_compute = 0x40004fec;
-r_sch_slice_fg_add = 0x40004ff8;
-r_sch_slice_fg_remove = 0x40005004;
-r_sch_slice_init = 0x40005010;
-r_sch_slice_per_add = 0x4000501c;
-r_sch_slice_per_remove = 0x40005028;
-r_sdk_config_get_bt_sleep_enable = 0x40005034;
-r_sdk_config_get_hl_derived_opts = 0x40005040;
-r_sdk_config_get_opts = 0x4000504c;
-r_sdk_config_get_priv_opts = 0x40005058;
-r_sdk_config_set_bt_sleep_enable = 0x40005064;
-r_sdk_config_set_hl_derived_opts = 0x40005070;
-r_sdk_config_set_opts = 0x4000507c;
-r_specialModP256 = 0x40005088;
-r_unloaded_area_init = 0x40005094;
-r_vhci_flow_off = 0x400050a0;
-r_vhci_flow_on = 0x400050ac;
-r_vhci_notify_host_send_available = 0x400050b8;
-r_vhci_send_to_host = 0x400050c4;
-r_vnd_hci_command_handler = 0x400050d0;
-r_vshci_init = 0x400050dc;
-vnd_hci_command_handler_wrapper = 0x400050e8;
-r_lld_legacy_adv_dynamic_pti_get = 0x400050f4;
-r_lld_legacy_adv_dynamic_pti_process = 0x40005100;
-r_lld_ext_adv_dynamic_pti_get = 0x4000510c;
-r_lld_ext_adv_dynamic_aux_pti_process = 0x40005118;
-r_lld_ext_adv_dynamic_pti_process = 0x40005124;
-r_lld_adv_ext_pkt_prepare_set = 0x40005130;
-r_lld_adv_ext_chain_connectable_construct = 0x40005148;
-r_lld_adv_pkt_rx_connect_post = 0x40005160;
-r_lld_adv_start_init_evt_param = 0x4000516c;
-r_lld_adv_start_set_cs = 0x40005178;
-/* r_lld_adv_start_update_filter_policy = 0x40005184; */
-r_lld_adv_start_schedule_asap = 0x40005190;
-r_lld_con_tx_prog_new_packet_coex = 0x4000519c;
-r_lld_per_adv_dynamic_pti_get = 0x400051b4;
-r_lld_per_adv_evt_start_chm_upd = 0x400051c0;
-r_lld_ext_scan_dynamic_pti_get = 0x400051cc;
-r_lld_sync_insert = 0x400051e4;
-r_sch_prog_ble_push = 0x400051f0;
-r_sch_prog_bt_push = 0x400051fc;
-r_lld_init_evt_end_type_set = 0x40005208;
-r_lld_init_evt_end_type_get = 0x40005214;
-r_lld_adv_direct_adv_use_rpa_addr_state_set = 0x40005220;
-r_lld_adv_direct_adv_use_rpa_addr_state_get = 0x4000522c;
-r_lld_init_evt_end_type_check_state_set = 0x40005238;
-r_lld_init_evt_end_type_check_state_get = 0x40005244;
 /* Data (.data, .bss, .rodata) */
 bt_rf_coex_cfg_p = 0x3fceffa8;
 bt_rf_coex_hooks_p = 0x3fceffa4;
@@ -1738,38 +919,6 @@ rwip_coex_cfg = 0x3ff1eebe;
 rwip_priority = 0x3ff1eea8;
 veryBigHexP256 = 0x3ff1ee5c;
 
-/* bluetooth hook funcs */
-r_llc_loc_encrypt_proc_continue_hook = 0x40001c60;
-r_llc_loc_phy_upd_proc_continue_hook = 0x40001c64;
-r_llc_rem_phy_upd_proc_continue_hook = 0x40001c68;
-r_lld_scan_frm_eof_isr_hook = 0x40001c6c;
-r_lld_scan_evt_start_cbk_hook = 0x40001c70;
-r_lld_scan_process_pkt_rx_ext_adv_hook = 0x40001c78;
-r_lld_scan_sched_hook = 0x40001c7c;
-r_lld_adv_evt_start_cbk_hook = 0x40001c84;
-r_lld_adv_aux_evt_start_cbk_hook = 0x40001c88;
-r_lld_adv_frm_isr_hook = 0x40001c8c;
-r_lld_adv_start_init_evt_param_hook = 0x40001c90;
-r_lld_con_evt_canceled_cbk_hook = 0x40001c94;
-r_lld_con_frm_isr_hook = 0x40001c98;
-r_lld_con_tx_hook = 0x40001c9c;
-r_lld_con_rx_hook = 0x40001ca0;
-r_lld_con_evt_start_cbk_hook = 0x40001ca4;
-r_lld_con_tx_prog_new_packet_hook = 0x40001cac;
-r_lld_init_frm_eof_isr_hook = 0x40001cb0;
-r_lld_init_evt_start_cbk_hook = 0x40001cb4;
-r_lld_init_sched_hook = 0x40001cbc;
-r_lld_init_process_pkt_tx_hook = 0x40001cc0;
-r_lld_per_adv_evt_start_cbk_hook = 0x40001cc4;
-r_lld_per_adv_frm_isr_hook = 0x40001cc8;
-r_lld_per_adv_start_hook = 0x40001ccc;
-r_lld_sync_frm_eof_isr_hook = 0x40001cd0;
-r_lld_sync_evt_start_cbk_hook = 0x40001cd4;
-r_lld_sync_start_hook = 0x40001cd8;
-r_lld_sync_process_pkt_rx_pkt_check_hook = 0x40001cdc;
-r_sch_arb_insert_hook = 0x40001ce0;
-r_sch_plan_offset_req_hook = 0x40001ce4;
-
 /***************************************
  Group rom_pp
  ***************************************/
diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c
index 4f75c8adff7..868caeb1974 100644
--- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c
+++ b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c5.c
@@ -74,8 +74,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-
-    regi2c_ctrl_ll_master_enable_clock(true);
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {
diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c
index 2ae4b905d57..cf8479d8bc9 100644
--- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c
+++ b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c
@@ -85,8 +85,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-
-    regi2c_ctrl_ll_master_enable_clock(true);
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {
diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c
index 4f75c8adff7..868caeb1974 100644
--- a/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c
+++ b/components/esp_rom/patches/esp_rom_regi2c_esp32c61.c
@@ -74,8 +74,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-
-    regi2c_ctrl_ll_master_enable_clock(true);
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {
diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c b/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c
index 58815d15bca..e42c3493a65 100644
--- a/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c
+++ b/components/esp_rom/patches/esp_rom_regi2c_esp32h2.c
@@ -86,7 +86,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
     uint32_t i2c_sel = 0;
-    regi2c_ctrl_ll_master_enable_clock(true);
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
 
     /* Before config I2C register, enable corresponding slave. */
     switch (block) {
diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c b/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c
index 5de1ba2827e..6175540bbb1 100644
--- a/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c
+++ b/components/esp_rom/patches/esp_rom_regi2c_esp32p4.c
@@ -87,8 +87,7 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
 
 static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
 {
-    int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // Right now this patch in rom can not depend on esp_hw_support, after IDF-10110 is done, this should be removed, should have spinlock protection
-    regi2c_ctrl_ll_master_enable_clock(true);
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
     REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0);
     REG_SET_FIELD(I2C_ANA_MST_ANA_CONF1_REG, I2C_ANA_MST_ANA_CONF1, 0);
 
diff --git a/components/esp_rom/patches/esp_rom_systimer.c b/components/esp_rom/patches/esp_rom_systimer.c
index 0b8b20e180d..7de32f09e6a 100644
--- a/components/esp_rom/patches/esp_rom_systimer.c
+++ b/components/esp_rom/patches/esp_rom_systimer.c
@@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co
 }
 #endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200)
 
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 void systimer_hal_init(systimer_hal_context_t *hal)
 {
     hal->dev = &SYSTIMER;
@@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal)
     systimer_ll_enable_clock(hal->dev, false);
     hal->dev = NULL;
 }
-#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 
 #endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
diff --git a/components/esp_rom/patches/esp_rom_uart.c b/components/esp_rom/patches/esp_rom_uart.c
index 0740c9022ea..6aa0988c16d 100644
--- a/components/esp_rom/patches/esp_rom_uart.c
+++ b/components/esp_rom/patches/esp_rom_uart.c
@@ -25,9 +25,9 @@ IRAM_ATTR void esp_rom_output_tx_wait_idle(uint8_t uart_no)
 
 #if CONFIG_IDF_TARGET_ESP32C3
 /**
- * The ESP32-C3 ROM has released two versions, one is the ECO3 version,
- * and the other is the version before ECO3 (include ECO0 ECO1 ECO2).
- * These two versions of the ROM code do not list uart_tx_switch wrap
+ * The ESP32-C3 ROM has released three versions, ECO7 (v1.1), ECO3, and
+ * the version before ECO3 (include ECO0 ECO1 ECO2).
+ * These three versions of the ROM code do not list uart_tx_switch wrap
  * function in the ROM interface, so here use the uart_tx_switch direct
  * address instead.
  */
@@ -38,6 +38,8 @@ IRAM_ATTR void esp_rom_output_set_as_console(uint8_t uart_no)
 
     if (efuse_hal_chip_revision() < 3) {
         uart_tx_switch = (rom_func_t)0x4004b8ca;
+    } else if (efuse_hal_chip_revision() >= 101) {
+        uart_tx_switch = (rom_func_t)0x40001c44;
     } else {
         uart_tx_switch = (rom_func_t)0x4004c166;
     }
diff --git a/components/esp_security/CMakeLists.txt b/components/esp_security/CMakeLists.txt
index d9c054b15ec..da2fb0125bb 100644
--- a/components/esp_security/CMakeLists.txt
+++ b/components/esp_security/CMakeLists.txt
@@ -1,4 +1,5 @@
 idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(non_os_build NON_OS_BUILD)
 
 if(${target} STREQUAL "linux")
     return() # This component is not supported by the POSIX/Linux simulator
@@ -8,7 +9,7 @@ set(srcs "")
 set(priv_requires "")
 set(priv_includes "")
 
-if(NOT BOOTLOADER_BUILD)
+if(NOT non_os_build)
     list(APPEND srcs "src/init.c")
     list(APPEND priv_includes "src/${IDF_TARGET}")
 
@@ -37,6 +38,6 @@ idf_component_register(SRCS ${srcs}
                     PRIV_INCLUDE_DIRS ${priv_includes}
                     PRIV_REQUIRES ${priv_requires})
 
-if(NOT BOOTLOADER_BUILD)
+if(NOT non_os_build)
     target_link_libraries(${COMPONENT_LIB} PRIVATE "-u esp_security_init_include_impl")
 endif()
diff --git a/components/esp_security/src/init.c b/components/esp_security/src/init.c
index d00d0e9647f..d12e1fe3265 100644
--- a/components/esp_security/src/init.c
+++ b/components/esp_security/src/init.c
@@ -20,23 +20,15 @@ __attribute__((unused)) static const char *TAG = "esp_security";
 
 static void esp_key_mgr_init(void)
 {
-    // The following operation makes the Key Manager to use eFuse key for ECDSA and XTS-AES operation by default
-    // This is to keep the default behavior same as the other chips
-    // If the Key Manager configuration is already locked then following operation does not have any effect
+    // The following code initializes the key manager.
 #if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
     // Enable key manager clock
     // Using ll APIs which do not require critical section
     _key_mgr_ll_enable_bus_clock(true);
     _key_mgr_ll_enable_peripheral_clock(true);
-
+    _key_mgr_ll_reset_register();
     while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
     };
-#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
-    key_mgr_ll_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
-#endif
-#if SOC_KEY_MANAGER_FE_KEY_DEPLOY
-    key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
-#endif
 #endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY */
 }
 
diff --git a/components/esp_security/test_apps/.build-test-rules.yml b/components/esp_security/test_apps/.build-test-rules.yml
index abfc86a2c5d..6802faf7539 100644
--- a/components/esp_security/test_apps/.build-test-rules.yml
+++ b/components/esp_security/test_apps/.build-test-rules.yml
@@ -1,7 +1,7 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
 
 components/esp_security/test_apps/crypto_drivers:
-  disable:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: Support for ESP32C61 is yet to be added.
+  enable:
+    - if: ((SOC_HMAC_SUPPORTED == 1) or (SOC_DIG_SIGN_SUPPORTED == 1)) or (SOC_KEY_MANAGER_SUPPORTED == 1)
+  depends_components:
+    - esp_security
diff --git a/components/esp_security/test_apps/crypto_drivers/README.md b/components/esp_security/test_apps/crypto_drivers/README.md
index 351f5fdebc7..1dfe1331b41 100644
--- a/components/esp_security/test_apps/crypto_drivers/README.md
+++ b/components/esp_security/test_apps/crypto_drivers/README.md
@@ -1,3 +1,3 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
 
diff --git a/components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt b/components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt
index 67485675547..b6ae16ae0a9 100644
--- a/components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt
+++ b/components/esp_security/test_apps/crypto_drivers/main/CMakeLists.txt
@@ -1,7 +1,16 @@
-set(srcs "test_app_main.c"
-          "test_ds.c"
-          "test_hmac.c"
-          "test_key_mgr.c")
+set(srcs "test_app_main.c")
+
+if(CONFIG_SOC_HMAC_SUPPORTED)
+    list(APPEND srcs "test_hmac.c")
+endif()
+
+if(CONFIG_SOC_DIG_SIGN_SUPPORTED)
+    list(APPEND srcs "test_ds.c")
+endif()
+
+if(CONFIG_SOC_KEY_MANAGER_SUPPORTED)
+    list(APPEND srcs "test_key_mgr.c")
+endif()
 
 idf_component_register(SRCS ${srcs}
                        REQUIRES unity efuse test_utils spi_flash esp_security
diff --git a/components/esp_security/test_apps/crypto_drivers/main/Kconfig.projbuild b/components/esp_security/test_apps/crypto_drivers/main/Kconfig.projbuild
new file mode 100644
index 00000000000..7cdf8c00fa6
--- /dev/null
+++ b/components/esp_security/test_apps/crypto_drivers/main/Kconfig.projbuild
@@ -0,0 +1,9 @@
+menu "ESP Security Tests"
+    config ESP_SECURITY_ENABLE_FPGA_TESTS
+        bool "Allow enabling the esp_security tests that require burning efuses"
+        default y if IDF_ENV_FPGA
+        default n
+        help
+            This includes the esp_security tests that actually require burning some efuses.
+            It is better to run these tests on an FPGA to avoid mistakenly burning eFuses.
+endmenu
diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_ds.c b/components/esp_security/test_apps/crypto_drivers/main/test_ds.c
index d631c7dd358..13d53308be6 100644
--- a/components/esp_security/test_apps/crypto_drivers/main/test_ds.c
+++ b/components/esp_security/test_apps/crypto_drivers/main/test_ds.c
@@ -8,8 +8,6 @@
 #include "unity.h"
 
 #include "soc/soc_caps.h"
-
-#if SOC_DIG_SIGN_SUPPORTED
 #include "rom/efuse.h"
 #if CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rom/digital_signature.h"
@@ -257,7 +255,7 @@ TEST_CASE("Digital Signature Blocking HMAC key out of range", "[hw_crypto] [ds]"
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY0 - 1, signature_data));
 }
 
-#if CONFIG_IDF_ENV_FPGA
+#if CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS
 
 static void burn_hmac_keys(void)
 {
@@ -437,5 +435,4 @@ TEST_CASE("Digital Signature Invalid Data (FPGA only)", "[hw_crypto] [ds]")
     }
 }
 
-#endif // CONFIG_IDF_ENV_FPGA
-#endif // SOC_DIG_SIGN_SUPPORTED
+#endif // CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS
diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c b/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c
index 9c20debc529..8f8ccf39ef4 100644
--- a/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c
+++ b/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c
@@ -8,11 +8,9 @@
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
 #include "esp_log.h"
-
-#if SOC_HMAC_SUPPORTED
 #include "esp_hmac.h"
 
-#if CONFIG_IDF_ENV_FPGA
+#if CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS
 
 /* Allow testing varying message lengths (truncating the same message)
    for various results */
@@ -1299,7 +1297,7 @@ TEST_CASE("HMAC 'upstream' wait lock", "[hw_crypto]")
     }
 }
 
-#endif // CONFIG_IDF_ENV_FPGA
+#endif // CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS
 
 /**
  * This test is just a parameter test and does not write any keys to efuse.
@@ -1315,5 +1313,3 @@ TEST_CASE("HMAC key out of range", "[hw_crypto]")
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_hmac_calculate(HMAC_KEY0 - 1, message, 47, hmac));
     TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_hmac_calculate(HMAC_KEY5 + 1, message, 47, hmac));
 }
-
-#endif // SOC_HMAC_SUPPORTED
diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c b/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c
index 4484a9fde5e..1fdb5b28f19 100644
--- a/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c
+++ b/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c
@@ -7,7 +7,6 @@
 #include "unity.h"
 
 #include "soc/soc_caps.h"
-#if SOC_KEY_MANAGER_SUPPORTED
 #include "esp_partition.h"
 #include "esp_flash.h"
 #include "esp_log.h"
@@ -143,4 +142,3 @@ TEST_CASE("Key Manager random mode: ECDSA key deployment", "[hw_crypto] [key_mgr
     esp_ret = esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_info);
     TEST_ASSERT_EQUAL(ESP_OK, esp_ret);
 }
-#endif
diff --git a/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py b/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py
index e0709970c50..44435595f06 100644
--- a/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py
+++ b/components/esp_security/test_apps/crypto_drivers/pytest_crypto_drivers.py
@@ -1,17 +1,16 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
 import pytest
 from pytest_embedded import Dut
 
 
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.esp32p4
+@pytest.mark.esp32c5
 @pytest.mark.generic
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='Support for ESP32C61 is yet to be added.')  # TODO: [ESP32C61] IDF-10987
-@pytest.mark.parametrize(
-    'config',
-    [
-        pytest.param('default', marks=[pytest.mark.supported_targets]),
-    ],
-    indirect=True,
-)
 def test_crypto_drivers(dut: Dut) -> None:
     dut.run_all_single_board_cases(timeout=180)
diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt
index d2f97850ece..1443e619d4b 100644
--- a/components/esp_system/CMakeLists.txt
+++ b/components/esp_system/CMakeLists.txt
@@ -147,3 +147,7 @@ endif()
 if(CONFIG_SOC_MEM_NON_CONTIGUOUS_SRAM)
     target_link_options(${COMPONENT_LIB} INTERFACE "-Wl,--enable-non-contiguous-regions")
 endif()
+
+if(CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS)
+    add_subdirectory(openocd_stub_bins)
+endif()
diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
index e597eac88fa..504981640b1 100644
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@@ -92,14 +92,8 @@ menu "ESP System Settings"
 
     config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
         bool
-        default y if IDF_TARGET_ESP32 && ESP_SYSTEM_SINGLE_CORE_MODE
-        default y if IDF_TARGET_ESP32S2
-        default y if IDF_TARGET_ESP32C3
-        default y if IDF_TARGET_ESP32S3
-        default y if IDF_TARGET_ESP32C6
-        default n if IDF_TARGET_ESP32H2 # IDF-5667
-        default y if IDF_TARGET_ESP32P4
-        default y if IDF_TARGET_ESP32C5
+        default n if IDF_TARGET_ESP32 && !ESP_SYSTEM_SINGLE_CORE_MODE
+        default y
         depends on SOC_RTC_FAST_MEM_SUPPORTED
 
     config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
@@ -108,9 +102,8 @@ menu "ESP System Settings"
         depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
         help
             This config option allows to add RTC fast memory region to system heap with capability
-            similar to that of DRAM region but without DMA. This memory will be consumed first per
-            heap initialization order by early startup services and scheduler related code. Speed
-            wise RTC fast memory operates on APB clock and hence does not have much performance impact.
+            similar to that of DRAM region but without DMA. Speed wise RTC fast memory operates on
+            APB clock and hence does not have much performance impact.
 
     config ESP_SYSTEM_USE_EH_FRAME
         bool "Generate and use eh_frame for backtracing"
@@ -542,6 +535,19 @@ menu "ESP System Settings"
             Debug stubs are used by OpenOCD to execute pre-compiled onboard code
             which does some useful debugging stuff, e.g. GCOV data dump.
 
+    config ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+        bool "Preload OpenOCD stub binaries to speed up debugging. 8K memory will be reserved"
+        default n
+        depends on SOC_DEBUG_HAVE_OCD_STUB_BINS
+        help
+            OpenOCD uses stub code to access flash during programming or when inserting and removing
+            SW flash breakpoints.
+            To execute stub code, OpenOCD allocates memory on the target device, backs up the existing memory,
+            loads the stub binary, runs the binary, and then restores the original memory.
+            This process can be time-consuming, especially when using USB serial JTAG.
+            By enabling this option, 8K of memory in RAM will be preallocated with the stub code,
+            eliminating the need to back up and restore the memory region.
+
     config ESP_DEBUG_OCDAWARE
         bool "Make exception and panic handlers JTAG/OCD aware"
         default y
diff --git a/components/esp_system/ld/esp32c6/sections.ld.in b/components/esp_system/ld/esp32c6/sections.ld.in
index 98b23613d32..da8a695be4a 100644
--- a/components/esp_system/ld/esp32c6/sections.ld.in
+++ b/components/esp_system/ld/esp32c6/sections.ld.in
@@ -156,6 +156,21 @@ SECTIONS
   .iram0.text :
   {
     _iram_start = ABSOLUTE(.);
+
+#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+    /* Do not move this block! OpenOCD expects this to be at the beginning of IRAM. */
+    KEEP(*(.ocd_stub.code));
+    KEEP(*(.ocd_stub.tramp));
+    . = ALIGN(0x800);
+    KEEP(*(.ocd_stub.data));
+    KEEP(*(.ocd_stub.bss));
+    KEEP(*(.ocd_stub.stack));
+    KEEP(*(.ocd_stub.params));
+    . = ALIGN(0x1000);
+    KEEP(*(.ocd_stub.scratchmem));
+    ASSERT(ABSOLUTE(.) == _iram_start + 0x2000, "openocd stub memory must be ended at _iram_start + 0x2000");
+#endif
+
     /* Vectors go to start of IRAM */
     ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
     KEEP(*(.exception_vectors_table.text));
diff --git a/components/esp_system/ld/esp32h2/sections.ld.in b/components/esp_system/ld/esp32h2/sections.ld.in
index 5ffe1de81d6..5fb84f6b3b0 100644
--- a/components/esp_system/ld/esp32h2/sections.ld.in
+++ b/components/esp_system/ld/esp32h2/sections.ld.in
@@ -156,6 +156,21 @@ SECTIONS
   .iram0.text :
   {
     _iram_start = ABSOLUTE(.);
+
+#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+    /* Do not move this block! OpenOCD expects this to be at the beginning of IRAM. */
+    KEEP(*(.ocd_stub.code));
+    KEEP(*(.ocd_stub.tramp));
+    . = ALIGN(0x800);
+    KEEP(*(.ocd_stub.data));
+    KEEP(*(.ocd_stub.bss));
+    KEEP(*(.ocd_stub.stack));
+    KEEP(*(.ocd_stub.params));
+    . = ALIGN(0x1000);
+    KEEP(*(.ocd_stub.scratchmem));
+    ASSERT(ABSOLUTE(.) == _iram_start + 0x2000, "openocd stub memory must be ended at _iram_start + 0x2000");
+#endif
+
     /* Vectors go to start of IRAM */
     ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
     KEEP(*(.exception_vectors_table.text));
diff --git a/components/esp_system/openocd_stub_bins/CMakeLists.txt b/components/esp_system/openocd_stub_bins/CMakeLists.txt
new file mode 100644
index 00000000000..ebd73f430aa
--- /dev/null
+++ b/components/esp_system/openocd_stub_bins/CMakeLists.txt
@@ -0,0 +1,48 @@
+idf_build_get_property(target IDF_TARGET)
+
+# Function to add custom commands for copying stub files
+function(add_copy_command src dest)
+    add_custom_command(
+        OUTPUT ${dest}
+        COMMAND ${CMAKE_COMMAND} -E copy_if_different ${src} ${dest}
+        DEPENDS ${src}
+        COMMENT "Copying ${src} to ${dest}"
+        VERBATIM
+    )
+endfunction()
+
+set(openocd_path $ENV{OPENOCD_SCRIPTS})
+
+if(openocd_path)
+    set(stub_bin_path ${openocd_path}/../espressif/stub_bins)
+    if(IS_DIRECTORY ${stub_bin_path} AND IS_DIRECTORY ${stub_bin_path}/${target})
+        set(code_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_code.inc")
+        set(data_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_data.inc")
+        set(img_header "${stub_bin_path}/${target}/stub_flash_idf_image.h")
+        if(EXISTS ${code_bin} AND EXISTS ${data_bin} AND EXISTS ${img_header})
+            set(dest_dir "${CMAKE_BINARY_DIR}/openocd_stub_bins")
+            set(output_code_bin "${dest_dir}/stub_flash_idf_binary_code.inc")
+            set(output_data_bin "${dest_dir}/stub_flash_idf_binary_data.inc")
+            set(output_img_header "${dest_dir}/stub_flash_idf_image.h")
+            add_copy_command(${code_bin} ${output_code_bin})
+            add_copy_command(${data_bin} ${output_data_bin})
+            add_copy_command(${img_header} ${output_img_header})
+            add_custom_target(copy_stub_bins ALL
+                DEPENDS ${output_code_bin} ${output_data_bin} ${output_img_header}
+                COMMENT "Copying OpenOCD stub binaries and image header"
+            )
+            add_dependencies(${COMPONENT_LIB} copy_stub_bins)
+        endif()
+    else()
+        message(FATAL_ERROR
+            "OpenOCD stub binary files couldn't be found! "
+            "To bypass this error, disable the CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS option")
+    endif()
+
+    set(srcs "openocd_stub_flasher.c")
+    add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
+    target_sources(${COMPONENT_LIB} PRIVATE ${srcs})
+    target_include_directories(${COMPONENT_LIB} PRIVATE ${dest_dir})
+    target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_system_include_openocd_stub_binaries")
+
+endif()
diff --git a/components/esp_system/openocd_stub_bins/esp_riscv_stub_tramp.inc b/components/esp_system/openocd_stub_bins/esp_riscv_stub_tramp.inc
new file mode 100644
index 00000000000..22c0b530f60
--- /dev/null
+++ b/components/esp_system/openocd_stub_bins/esp_riscv_stub_tramp.inc
@@ -0,0 +1 @@
+  0x82, 0x98, 0x02, 0x90
diff --git a/components/esp_system/openocd_stub_bins/openocd_stub_flasher.c b/components/esp_system/openocd_stub_bins/openocd_stub_flasher.c
new file mode 100644
index 00000000000..52331ec67c1
--- /dev/null
+++ b/components/esp_system/openocd_stub_bins/openocd_stub_flasher.c
@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+
+#include "stub_flash_idf_image.h"
+
+/* Copied from openocd-esp32/contrib/loaders/flash/espressif/${target}/inc/stub_flash_idf_binary_code.inc */
+static const uint8_t s_flasher_stub_code[]  __attribute__((used, section(".ocd_stub.code"))) = {
+#include "stub_flash_idf_binary_code.inc"
+};
+
+/* Copied from openocd-esp32/src/target/espressif/esp_riscv_stub_tramp.inc */
+static const uint8_t s_flasher_stub_tramp[] __attribute__((used, section(".ocd_stub.tramp"))) = {
+#include "esp_riscv_stub_tramp.inc"
+};
+
+/* Copied from openocd-esp32/contrib/loaders/flash/espressif/${target}/inc/stub_flash_idf_binary_data.inc */
+static const uint8_t s_flasher_stub_data[] __attribute__((used, section(".ocd_stub.data"))) = {
+#include "stub_flash_idf_binary_data.inc"
+};
+
+static uint8_t s_flasher_stub_bss[OPENOCD_STUB_BSS_SIZE] __attribute__((used, section(".ocd_stub.bss")));
+static uint8_t s_flasher_stub_stack[OPENOCD_STUB_STACK_SIZE] __attribute__((used, section(".ocd_stub.stack")));
+static uint8_t s_flasher_stub_params[OPENOCD_STUB_PARAM_SIZE] __attribute__((used, section(".ocd_stub.params")));
+static uint8_t s_flasher_stub_bp_sectors[OPENOCD_STUB_BP_SECTOR_SIZE] __attribute__((used, section(".ocd_stub.scratchmem")));
+
+// Hook to force the linker to include this file
+void esp_system_include_openocd_stub_binaries(void)
+{
+}
diff --git a/components/esp_system/port/arch/riscv/panic_arch.c b/components/esp_system/port/arch/riscv/panic_arch.c
index 52fb63dd37e..1f4dd57b540 100644
--- a/components/esp_system/port/arch/riscv/panic_arch.c
+++ b/components/esp_system/port/arch/riscv/panic_arch.c
@@ -39,9 +39,11 @@
  */
 static inline void print_cache_err_details(const void *frame)
 {
-    const char* cache_err_msg = esp_cache_err_panic_string();
-    if (cache_err_msg) {
-        panic_print_str(cache_err_msg);
+    esp_cache_err_info_t err_info = {};
+    esp_cache_err_get_panic_info(&err_info);
+
+    if (err_info.err_str) {
+        panic_print_str(err_info.err_str);
     } else {
         panic_print_str("Cache error active, but failed to find a corresponding error message");
     }
diff --git a/components/esp_system/port/arch/xtensa/panic_arch.c b/components/esp_system/port/arch/xtensa/panic_arch.c
index 484774ecb19..610a4a04680 100644
--- a/components/esp_system/port/arch/xtensa/panic_arch.c
+++ b/components/esp_system/port/arch/xtensa/panic_arch.c
@@ -19,8 +19,6 @@
 #include "sdkconfig.h"
 
 #if !CONFIG_IDF_TARGET_ESP32
-#include "soc/extmem_reg.h"
-#include "soc/ext_mem_defs.h"
 #include "soc/rtc_cntl_reg.h"
 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 #ifdef CONFIG_IDF_TARGET_ESP32S2
@@ -167,95 +165,7 @@ static void print_debug_exception_details(const void *f)
     }
 }
 
-#if CONFIG_IDF_TARGET_ESP32S2
-static inline void print_cache_err_details(const void *f)
-{
-    uint32_t vaddr = 0, size = 0;
-    uint32_t status[2];
-    status[0] = REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
-    status[1] = REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
-    for (int i = 0; i < 32; i++) {
-        switch (status[0] & BIT(i)) {
-        case EXTMEM_IC_SYNC_SIZE_FAULT_ST:
-            vaddr = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC0_REG);
-            size = REG_READ(EXTMEM_PRO_ICACHE_MEM_SYNC1_REG);
-            panic_print_str("Icache sync parameter configuration error, the error address and size is 0x");
-            panic_print_hex(vaddr);
-            panic_print_str("(0x");
-            panic_print_hex(size);
-            panic_print_str(")\r\n");
-            break;
-        case EXTMEM_IC_PRELOAD_SIZE_FAULT_ST:
-            vaddr = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG);
-            size = REG_READ(EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG);
-            panic_print_str("Icache preload parameter configuration error, the error address and size is 0x");
-            panic_print_hex(vaddr);
-            panic_print_str("(0x");
-            panic_print_hex(size);
-            panic_print_str(")\r\n");
-            break;
-        case EXTMEM_ICACHE_REJECT_ST:
-            vaddr = REG_READ(EXTMEM_PRO_ICACHE_REJECT_VADDR_REG);
-            panic_print_str("Icache reject error occurred while accessing the address 0x");
-            panic_print_hex(vaddr);
-
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
-                panic_print_str(" (invalid mmu entry)");
-            }
-            panic_print_str("\r\n");
-            break;
-        default:
-            break;
-        }
-        switch (status[1] & BIT(i)) {
-        case EXTMEM_DC_SYNC_SIZE_FAULT_ST:
-            vaddr = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC0_REG);
-            size = REG_READ(EXTMEM_PRO_DCACHE_MEM_SYNC1_REG);
-            panic_print_str("Dcache sync parameter configuration error, the error address and size is 0x");
-            panic_print_hex(vaddr);
-            panic_print_str("(0x");
-            panic_print_hex(size);
-            panic_print_str(")\r\n");
-            break;
-        case EXTMEM_DC_PRELOAD_SIZE_FAULT_ST:
-            vaddr = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG);
-            size = REG_READ(EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG);
-            panic_print_str("Dcache preload parameter configuration error, the error address and size is 0x");
-            panic_print_hex(vaddr);
-            panic_print_str("(0x");
-            panic_print_hex(size);
-            panic_print_str(")\r\n");
-            break;
-        case EXTMEM_DCACHE_WRITE_FLASH_ST:
-            panic_print_str("Write back error occurred while dcache tries to write back to flash\r\n");
-            break;
-        case EXTMEM_DCACHE_REJECT_ST:
-            vaddr = REG_READ(EXTMEM_PRO_DCACHE_REJECT_VADDR_REG);
-            panic_print_str("Dcache reject error occurred while accessing the address 0x");
-            panic_print_hex(vaddr);
-
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
-                panic_print_str(" (invalid mmu entry)");
-            }
-            panic_print_str("\r\n");
-            break;
-        case EXTMEM_MMU_ENTRY_FAULT_ST:
-            vaddr = REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG);
-            panic_print_str("MMU entry fault error occurred while accessing the address 0x");
-            panic_print_hex(vaddr);
-
-            if (REG_READ(EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
-                panic_print_str(" (invalid mmu entry)");
-            }
-            panic_print_str("\r\n");
-            break;
-        default:
-            break;
-        }
-    }
-}
-
-#if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
+#if CONFIG_IDF_TARGET_ESP32S2 && CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 #define MEMPROT_OP_INVALID 0xFFFFFFFF
 static inline void print_memprot_err_details(const void *f)
 {
@@ -290,75 +200,27 @@ static inline void print_memprot_err_details(const void *f)
 }
 #endif
 
-#elif CONFIG_IDF_TARGET_ESP32S3
 static inline void print_cache_err_details(const void *f)
 {
-    uint32_t vaddr = 0, size = 0;
-    uint32_t status;
-    status = REG_READ(EXTMEM_CACHE_ILG_INT_ST_REG);
-    for (int i = 0; i < 32; i++) {
-        switch (status & BIT(i)) {
-        case EXTMEM_ICACHE_SYNC_OP_FAULT_ST:
-            //TODO, which size should fetch
-            //vaddr = REG_READ(EXTMEM_ICACHE_MEM_SYNC0_REG);
-            //size = REG_READ(EXTMEM_ICACHE_MEM_SYNC1_REG);
-            panic_print_str("Icache sync parameter configuration error, the error address and size is 0x");
-            panic_print_hex(vaddr);
-            panic_print_str("(0x");
-            panic_print_hex(size);
-            panic_print_str(")\r\n");
-            break;
-        case EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST:
-            //TODO, which size should fetch
-            vaddr = REG_READ(EXTMEM_ICACHE_PRELOAD_ADDR_REG);
-            size = REG_READ(EXTMEM_ICACHE_PRELOAD_SIZE_REG);
-            panic_print_str("Icache preload parameter configuration error, the error address and size is 0x");
-            panic_print_hex(vaddr);
-            panic_print_str("(0x");
-            panic_print_hex(size);
-            panic_print_str(")\r\n");
-            break;
-        case EXTMEM_DCACHE_SYNC_OP_FAULT_ST:
-            //TODO, which size should fetch
-            //vaddr = REG_READ(EXTMEM_DCACHE_MEM_SYNC0_REG);
-            //size = REG_READ(EXTMEM_DCACHE_MEM_SYNC1_REG);
-            panic_print_str("Dcache sync parameter configuration error, the error address and size is 0x");
-            panic_print_hex(vaddr);
-            panic_print_str("(0x");
-            panic_print_hex(size);
-            panic_print_str(")\r\n");
-            break;
-        case EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST:
-            //TODO, which size should fetch
-            vaddr = REG_READ(EXTMEM_DCACHE_PRELOAD_ADDR_REG);
-            size = REG_READ(EXTMEM_DCACHE_PRELOAD_SIZE_REG);
-            panic_print_str("Dcache preload parameter configuration error, the error address and size is 0x");
-            panic_print_hex(vaddr);
-            panic_print_str("(0x");
-            panic_print_hex(size);
-            panic_print_str(")\r\n");
-            break;
-        case EXTMEM_DCACHE_WRITE_FLASH_ST:
-            panic_print_str("Write back error occurred while dcache tries to write back to flash\r\n");
-            panic_print_str("The following backtrace may not indicate the code that caused Cache invalid access\r\n");
-            break;
-        case EXTMEM_MMU_ENTRY_FAULT_ST:
-            vaddr = REG_READ(EXTMEM_CACHE_MMU_FAULT_VADDR_REG);
-            panic_print_str("MMU entry fault error occurred while accessing the address 0x");
-            panic_print_hex(vaddr);
-
-            if (REG_READ(EXTMEM_CACHE_MMU_FAULT_CONTENT_REG) & SOC_MMU_INVALID) {
-                panic_print_str(" (invalid mmu entry)");
-            }
-            panic_print_str("\r\n");
-            break;
-        default:
-            break;
+    esp_cache_err_info_t err = {};
+    esp_cache_err_get_panic_info(&err);
+
+    if (err.err_str) {
+        panic_print_str(err.err_str);
+        if (err.vaddr) {
+            panic_print_str(", error address: 0x");
+            panic_print_hex(err.vaddr);
         }
+        if (err.size) {
+            panic_print_str(", error size: 0x");
+            panic_print_hex(err.vaddr);
+        }
+    } else {
+        // Default to cache disabled message if no specific error is found
+        panic_print_str("Cache disabled but cached memory region accessed");
     }
     panic_print_str("\r\n");
 }
-#endif
 
 void panic_arch_fill_info(void *f, panic_info_t *info)
 {
@@ -383,7 +245,6 @@ void panic_arch_fill_info(void *f, panic_info_t *info)
     }
 
     info->description = "Exception was unhandled.";
-
     if (frame->exccause == EXCCAUSE_ILLEGAL) {
         info->details = print_illegal_instruction_details;
     }
@@ -426,7 +287,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
         "Coprocessor exception",
         "Interrupt wdt timeout on CPU0",
         "Interrupt wdt timeout on CPU1",
-        "Cache disabled but cached memory region accessed",
+        "Cache error",
     };
 
     info->reason = pseudo_reason[0];
@@ -442,8 +303,6 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
     }
 
     //MV note: ESP32S3 PMS handling?
-
-#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
     if (frame->exccause == PANIC_RSN_CACHEERR) {
 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE && CONFIG_IDF_TARGET_ESP32S2
         if (esp_memprot_is_intr_ena_any()) {
@@ -455,7 +314,6 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
             info->details = print_cache_err_details;
         }
     }
-#endif
 }
 
 uint32_t panic_get_address(const void *f)
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index 0911e8abd55..6e1a0ceda77 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -13,6 +13,7 @@
 
 #include "esp_log.h"
 #include "esp_chip_info.h"
+#include "esp_app_format.h"
 
 #include "esp_private/cache_err_int.h"
 #include "esp_clk_internal.h"
@@ -629,6 +630,9 @@ void IRAM_ATTR call_start_cpu0(void)
     REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
     REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
 #endif
+#elif CONFIG_IDF_TARGET_ESP32P4
+    REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
+    REG_SET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_CORE1_GLOBAL);
 #endif // CONFIG_IDF_TARGET_ESP32
 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 #endif // SOC_CPU_CORES_NUM > 1
@@ -787,9 +791,13 @@ void IRAM_ATTR call_start_cpu0(void)
     // Read the application binary image header. This will also decrypt the header if the image is encrypted.
     __attribute__((unused)) esp_image_header_t fhdr = {0};
 
-    // This assumes that DROM is the first segment in the application binary, i.e. that we can read
-    // the binary header through cache by accessing SOC_DROM_LOW address.
-    hal_memcpy(&fhdr, (void *) SOC_DROM_LOW, sizeof(fhdr));
+    // We can access the image header through the cache by reading from the memory-mapped virtual DROM start offset
+    uint32_t fhdr_src_addr = (uint32_t)(&_rodata_reserved_start) - sizeof(esp_image_header_t) - sizeof(esp_image_segment_header_t);
+    hal_memcpy(&fhdr, (void *) fhdr_src_addr, sizeof(fhdr));
+    if (fhdr.magic != ESP_IMAGE_HEADER_MAGIC) {
+        ESP_EARLY_LOGE(TAG, "Invalid app image header");
+        abort();
+    }
 
 #if CONFIG_IDF_TARGET_ESP32
 #if !CONFIG_SPIRAM_BOOT_INIT
diff --git a/components/esp_system/port/include/private/esp_private/cache_err_int.h b/components/esp_system/port/include/private/esp_private/cache_err_int.h
index 3d911bca5c7..369257358cf 100644
--- a/components/esp_system/port/include/private/esp_private/cache_err_int.h
+++ b/components/esp_system/port/include/private/esp_private/cache_err_int.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,11 +7,21 @@
 #pragma once
 
 #include <stdbool.h>
+#include <stdint.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/**
+ * @brief Cache error information
+ */
+typedef struct {
+    const char* err_str;    /*!< Error message for the current panic */
+    uint32_t vaddr;     /*!< Virtual address that caused the error */
+    uint32_t size;      /*!< Size of the access which caused the error */
+} esp_cache_err_info_t;
+
 /**
  * @brief initialize cache invalid access interrupt
  *
@@ -34,11 +44,11 @@ void esp_cache_err_int_init(void);
 int esp_cache_err_get_cpuid(void);
 
 /**
- * @brief Returns a pointer to the cache error message
+ * @brief Get error info for the current cache exception
  *
- * @return const char* Pointer to the error message
+ * @err_info struct containing the information of the current error
  */
-const char *esp_cache_err_panic_string(void);
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info);
 
 /**
  * @brief Checks if any cache errors are active
diff --git a/components/esp_system/port/soc/esp32/cache_err_int.c b/components/esp_system/port/soc/esp32/cache_err_int.c
index 491d122b9ad..61d0e9d36e5 100644
--- a/components/esp_system/port/soc/esp32/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32/cache_err_int.c
@@ -26,6 +26,15 @@
 #include "esp_rom_sys.h"
 
 #include "sdkconfig.h"
+#include "esp_private/cache_err_int.h"
+
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
+{
+    if (err_info == NULL) {
+        return;
+    }
+    (void)err_info;
+}
 
 void esp_cache_err_int_init(void)
 {
diff --git a/components/esp_system/port/soc/esp32/system_internal.c b/components/esp_system/port/soc/esp32/system_internal.c
index 75cae925114..da76aa90d1a 100644
--- a/components/esp_system/port/soc/esp32/system_internal.c
+++ b/components/esp_system/port/soc/esp32/system_internal.c
@@ -97,9 +97,9 @@ void IRAM_ATTR esp_restart_noos(void)
     wdt_hal_disable(&wdt1_context);
     wdt_hal_write_protect_enable(&wdt1_context);
 
-#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
     if (esp_ptr_external_ram(esp_cpu_get_sp())) {
-        // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
+        // If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used)
         // then need to switch SP to Internal Memory otherwise
         // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
         uint32_t new_sp = SOC_DRAM_LOW + (SOC_DRAM_HIGH - SOC_DRAM_LOW) / 2;
diff --git a/components/esp_system/port/soc/esp32c2/cache_err_int.c b/components/esp_system/port/soc/esp32c2/cache_err_int.c
index ff2a4312693..3807aa12eb6 100644
--- a/components/esp_system/port/soc/esp32c2/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32c2/cache_err_int.c
@@ -17,6 +17,7 @@
 #include "soc/periph_defs.h"
 #include "riscv/interrupt.h"
 #include "hal/cache_ll.h"
+#include "esp_private/cache_err_int.h"
 
 static const char *TAG = "CACHE_ERR";
 
@@ -106,25 +107,26 @@ static inline const char* test_and_print_register_bits(const uint32_t status,
     return NULL;
 }
 
-const char *esp_cache_err_panic_string(void)
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
 {
+    if (err_info == NULL) {
+        return;
+    }
     /* Read the status register EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. This status
-     * register is not equal to 0 when a cache access error occured. */
+     * register is not equal to 0 when a cache access error occurred. */
     const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
 
     /* If the panic is due to a cache access error, one of the bit of the
      * register is set. Thus, this function will return an error string. */
-    const char* err_str = test_and_print_register_bits(access_err_status, core0_acs_bits, DIM(core0_acs_bits));
+    err_info->err_str = test_and_print_register_bits(access_err_status, core0_acs_bits, DIM(core0_acs_bits));
 
     /* If the panic was due to a cache illegal error, the previous call returned NULL and this
      * EXTMEM_CACHE_ILG_INT_ST_REG register should not be equal to 0.
      * Check each bit of it and print the message associated if found. */
-    if (err_str == NULL) {
+    if (err_info->err_str == NULL) {
         const uint32_t cache_ilg_status = cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK);
-        err_str = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits));
+        err_info->err_str = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits));
     }
-
-    return err_str;
 }
 
 bool esp_cache_err_has_active_err(void)
@@ -169,7 +171,7 @@ void esp_cache_err_int_init(void)
     esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
-    /* On the hardware side, start by clearing all the bits reponsible for cache access error */
+    /* On the hardware side, start by clearing all the bits responsible for cache access error */
     cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* Then enable cache access error interrupts. */
     cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
diff --git a/components/esp_system/port/soc/esp32c3/cache_err_int.c b/components/esp_system/port/soc/esp32c3/cache_err_int.c
index dce1427e4fc..8f9d2765dab 100644
--- a/components/esp_system/port/soc/esp32c3/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32c3/cache_err_int.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,7 @@
 #include "soc/periph_defs.h"
 #include "riscv/interrupt.h"
 #include "hal/cache_ll.h"
+#include "esp_private/cache_err_int.h"
 
 static const char *TAG = "CACHE_ERR";
 
@@ -106,25 +107,26 @@ static inline const char* test_and_print_register_bits(const uint32_t status,
     return NULL;
 }
 
-const char *esp_cache_err_panic_string(void)
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
 {
+    if (err_info == NULL) {
+        return;
+    }
     /* Read the status register EXTMEM_CORE0_ACS_CACHE_INT_ST_REG. This status
-     * register is not equal to 0 when a cache access error occured. */
+     * register is not equal to 0 when a cache access error occurred. */
     const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
 
     /* If the panic is due to a cache access error, one of the bit of the
      * register is set. Thus, this function will return an error string. */
-    const char* err_str = test_and_print_register_bits(access_err_status, core0_acs_bits, DIM(core0_acs_bits));
+    err_info->err_str = test_and_print_register_bits(access_err_status, core0_acs_bits, DIM(core0_acs_bits));
 
     /* If the panic was due to a cache illegal error, the previous call returned NULL and this
      * EXTMEM_CACHE_ILG_INT_ST_REG register should not be equal to 0.
      * Check each bit of it and return the message associated if found. */
-    if (err_str == NULL) {
+    if (err_info->err_str == NULL) {
         const uint32_t cache_ilg_status = cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK);
-        err_str = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits));
+        err_info->err_str = test_and_print_register_bits(cache_ilg_status, cache_ilg_bits, DIM(cache_ilg_bits));
     }
-
-    return err_str;
 }
 
 bool esp_cache_err_has_active_err(void)
@@ -169,7 +171,7 @@ void esp_cache_err_int_init(void)
     esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
-    /* On the hardware side, start by clearing all the bits reponsible for cache access error */
+    /* On the hardware side, start by clearing all the bits responsible for cache access error */
     cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* Then enable cache access error interrupts. */
     cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
diff --git a/components/esp_system/port/soc/esp32c3/clk.c b/components/esp_system/port/soc/esp32c3/clk.c
index ece3d4c732f..ecb5d083856 100644
--- a/components/esp_system/port/soc/esp32c3/clk.c
+++ b/components/esp_system/port/soc/esp32c3/clk.c
@@ -235,7 +235,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                            SYSTEM_SPI3_CLK_EN |
                            SYSTEM_SPI4_CLK_EN |
                            SYSTEM_TWAI_CLK_EN |
-                           SYSTEM_I2S1_CLK_EN |
+                           SYSTEM_I2S0_CLK_EN |
                            SYSTEM_SPI2_DMA_CLK_EN |
                            SYSTEM_SPI3_DMA_CLK_EN;
 
@@ -274,7 +274,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                         SYSTEM_SPI3_CLK_EN |
                         SYSTEM_SPI4_CLK_EN |
                         SYSTEM_I2C_EXT1_CLK_EN |
-                        SYSTEM_I2S1_CLK_EN |
+                        SYSTEM_I2S0_CLK_EN |
                         SYSTEM_SPI2_DMA_CLK_EN |
                         SYSTEM_SPI3_DMA_CLK_EN;
     common_perip_clk1 = 0;
diff --git a/components/esp_system/port/soc/esp32c5/cache_err_int.c b/components/esp_system/port/soc/esp32c5/cache_err_int.c
index 0a86015545f..d4c1cae619b 100644
--- a/components/esp_system/port/soc/esp32c5/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32c5/cache_err_int.c
@@ -18,19 +18,21 @@
 #include "soc/soc.h"
 #include "riscv/interrupt.h"
 #include "hal/cache_ll.h"
+#include "esp_private/cache_err_int.h"
 
 static const char *TAG = "CACHE_ERR";
 
 const char cache_error_msg[] = "Cache access error";
 
-const char *esp_cache_err_panic_string(void)
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
 {
+    if (err_info == NULL) {
+        return;
+    }
     const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
 
     /* Return the error string if a cache error is active */
-    const char* err_str = access_err_status ? cache_error_msg : NULL;
-
-    return err_str;
+    err_info->err_str = access_err_status ? cache_error_msg : NULL;
 }
 
 bool esp_cache_err_has_active_err(void)
diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c
index 7bf484cab4e..4cec699c81a 100644
--- a/components/esp_system/port/soc/esp32c5/clk.c
+++ b/components/esp_system/port/soc/esp32c5/clk.c
@@ -19,7 +19,9 @@
 #include "soc/rtc.h"
 #include "soc/rtc_periph.h"
 #include "soc/i2s_reg.h"
+#include "soc/chip_revision.h"
 #include "esp_cpu.h"
+#include "hal/efuse_hal.h"
 #include "hal/wdt_hal.h"
 #if SOC_MODEM_CLOCK_SUPPORTED
 #include "hal/modem_lpcon_ll.h"
@@ -164,6 +166,12 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         }
         rtc_clk_slow_src_set(rtc_slow_clk_src);
 
+        // Disable unused clock sources after clock source switching is complete.
+        // Regardless of the clock source selection, the internal 136K clock source will always keep on.
+        if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+            rtc_clk_32k_enable(false);
+        }
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.
@@ -209,6 +217,15 @@ __attribute__((weak)) void esp_perip_clk_init(void)
     modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
 #endif
 
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
+        /* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix
+         * the issue where the modem module fails to transmit and receive packets
+         * due to the loss of the modem root clock caused by automatic clock gating
+         * during soc root clock source switching. For detailed information, refer
+         * to IDF-11064. */
+        REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
+    }
+
     ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
 #if 0  // TODO: [ESP32C5] IDF-8844
     uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
@@ -242,7 +259,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                            SYSTEM_SPI3_CLK_EN |
                            SYSTEM_SPI4_CLK_EN |
                            SYSTEM_TWAI_CLK_EN |
-                           SYSTEM_I2S1_CLK_EN |
+                           SYSTEM_I2S0_CLK_EN |
                            SYSTEM_SPI2_DMA_CLK_EN |
                            SYSTEM_SPI3_DMA_CLK_EN;
 
@@ -272,7 +289,7 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                         SYSTEM_SPI3_CLK_EN |
                         SYSTEM_SPI4_CLK_EN |
                         SYSTEM_I2C_EXT1_CLK_EN |
-                        SYSTEM_I2S1_CLK_EN |
+                        SYSTEM_I2S0_CLK_EN |
                         SYSTEM_SPI2_DMA_CLK_EN |
                         SYSTEM_SPI3_DMA_CLK_EN;
     common_perip_clk1 = 0;
diff --git a/components/esp_system/port/soc/esp32c6/cache_err_int.c b/components/esp_system/port/soc/esp32c6/cache_err_int.c
index c272b217f9e..9034f72ed90 100644
--- a/components/esp_system/port/soc/esp32c6/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32c6/cache_err_int.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,19 +17,21 @@
 #include "soc/periph_defs.h"
 #include "riscv/interrupt.h"
 #include "hal/cache_ll.h"
+#include "esp_private/cache_err_int.h"
 
 static const char *TAG = "CACHE_ERR";
 
 const char cache_error_msg[] = "Cache access error";
 
-const char *esp_cache_err_panic_string(void)
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
 {
+    if (err_info == NULL) {
+        return;
+    }
     const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
 
     /* Return the error string if a cache error is active */
-    const char* err_str = access_err_status ? cache_error_msg : NULL;
-
-    return err_str;
+    err_info->err_str = access_err_status ? cache_error_msg : NULL;
 }
 
 bool esp_cache_err_has_active_err(void)
@@ -60,7 +62,7 @@ void esp_cache_err_int_init(void)
     esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
-    /* On the hardware side, start by clearing all the bits reponsible for cache access error */
+    /* On the hardware side, start by clearing all the bits responsible for cache access error */
     cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* Then enable cache access error interrupts. */
     cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c
index 23a8ddab32f..36e023cd561 100644
--- a/components/esp_system/port/soc/esp32c6/clk.c
+++ b/components/esp_system/port/soc/esp32c6/clk.c
@@ -185,6 +185,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         }
         rtc_clk_slow_src_set(rtc_slow_clk_src);
 
+        // Disable unused clock sources after clock source switching is complete.
+        // Regardless of the clock source selection, the internal 136K clock source will always keep on.
+        if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+            rtc_clk_32k_enable(false);
+        }
+        if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
+            rtc_clk_rc32k_enable(false);
+        }
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.
diff --git a/components/esp_system/port/soc/esp32c61/cache_err_int.c b/components/esp_system/port/soc/esp32c61/cache_err_int.c
index e17c32f49dc..141b52382d0 100644
--- a/components/esp_system/port/soc/esp32c61/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32c61/cache_err_int.c
@@ -17,19 +17,21 @@
 #include "soc/periph_defs.h"
 #include "riscv/interrupt.h"
 #include "hal/cache_ll.h"
+#include "esp_private/cache_err_int.h"
 
 static const char *TAG = "CACHE_ERR";
 
 const char cache_error_msg[] = "Cache access error";
 
-const char *esp_cache_err_panic_string(void)
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
 {
+    if (err_info == NULL) {
+        return;
+    }
     const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
 
     /* Return the error string if a cache error is active */
-    const char* err_str = access_err_status ? cache_error_msg : NULL;
-
-    return err_str;
+    err_info->err_str = access_err_status ? cache_error_msg : NULL;
 }
 
 bool esp_cache_err_has_active_err(void)
diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c
index 035cc1c87f3..7e865037ab6 100644
--- a/components/esp_system/port/soc/esp32c61/clk.c
+++ b/components/esp_system/port/soc/esp32c61/clk.c
@@ -148,6 +148,12 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         }
         rtc_clk_slow_src_set(rtc_slow_clk_src);
 
+        // Disable unused clock sources after clock source switching is complete.
+        // Regardless of the clock source selection, the internal 136K clock source will always keep on.
+        if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+            rtc_clk_32k_enable(false);
+        }
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.
diff --git a/components/esp_system/port/soc/esp32h2/cache_err_int.c b/components/esp_system/port/soc/esp32h2/cache_err_int.c
index 770b4119481..bad10facb93 100644
--- a/components/esp_system/port/soc/esp32h2/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32h2/cache_err_int.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,19 +17,21 @@
 #include "soc/periph_defs.h"
 #include "riscv/interrupt.h"
 #include "hal/cache_ll.h"
+#include "esp_private/cache_err_int.h"
 
 static const char *TAG = "CACHE_ERR";
 
 const char cache_error_msg[] = "Cache access error";
 
-const char *esp_cache_err_panic_string(void)
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
 {
+    if (err_info == NULL) {
+        return;
+    }
     const uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
 
     /* Return the error string if a cache error is active */
-    const char* err_str = access_err_status ? cache_error_msg : NULL;
-
-    return err_str;
+    err_info->err_str = access_err_status ? cache_error_msg : NULL;
 }
 
 bool esp_cache_err_has_active_err(void)
@@ -60,7 +62,7 @@ void esp_cache_err_int_init(void)
     esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 
     ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
-    /* On the hardware side, start by clearing all the bits reponsible for cache access error */
+    /* On the hardware side, start by clearing all the bits responsible for cache access error */
     cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
     /* Then enable cache access error interrupts. */
     cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c
index 02aa13411a0..026fd5c19ea 100644
--- a/components/esp_system/port/soc/esp32h2/clk.c
+++ b/components/esp_system/port/soc/esp32h2/clk.c
@@ -184,6 +184,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         }
         rtc_clk_slow_src_set(rtc_slow_clk_src);
 
+        // Disable unused clock sources after clock source switching is complete.
+        // Regardless of the clock source selection, the internal 136K clock source will always keep on.
+        if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K && rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_OSC_SLOW) {
+            rtc_clk_32k_enable(false);
+        }
+        if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
+            rtc_clk_rc32k_enable(false);
+        }
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.
diff --git a/components/esp_system/port/soc/esp32p4/Kconfig.system b/components/esp_system/port/soc/esp32p4/Kconfig.system
index 5ffec7fe769..02a1c4acd11 100644
--- a/components/esp_system/port/soc/esp32p4/Kconfig.system
+++ b/components/esp_system/port/soc/esp32p4/Kconfig.system
@@ -10,34 +10,28 @@ menu "Brownout Detector"
 
     choice ESP_BROWNOUT_DET_LVL_SEL
         prompt "Brownout voltage level"
-        depends on ESP_BROWNOUT_DET
         default ESP_BROWNOUT_DET_LVL_SEL_7
+        depends on ESP_BROWNOUT_DET
         help
             The brownout detector will reset the chip when the supply voltage is approximately
             below this level. Note that there may be some variation of brownout voltage level
             between each chip.
 
+            Please note that this config is only valid when P4 SOC version is above v1.0. When you are using a
+            earlier P4 SOC version (v0.x), the brownout value should be fixed around 2.52V and not configurable.
+
             #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
             #of the brownout threshold levels.
         config ESP_BROWNOUT_DET_LVL_SEL_7
-            bool "2.51V"
+            bool "2.6V"
         config ESP_BROWNOUT_DET_LVL_SEL_6
-            bool "2.64V"
+            bool "2.52V"
         config ESP_BROWNOUT_DET_LVL_SEL_5
-            bool "2.76V"
-        config ESP_BROWNOUT_DET_LVL_SEL_4
-            bool "2.92V"
-        config ESP_BROWNOUT_DET_LVL_SEL_3
-            bool "3.10V"
-        config ESP_BROWNOUT_DET_LVL_SEL_2
-            bool "3.27V"
+            bool "2.42V"
     endchoice
 
     config ESP_BROWNOUT_DET_LVL
         int
-        default 2 if ESP_BROWNOUT_DET_LVL_SEL_2
-        default 3 if ESP_BROWNOUT_DET_LVL_SEL_3
-        default 4 if ESP_BROWNOUT_DET_LVL_SEL_4
         default 5 if ESP_BROWNOUT_DET_LVL_SEL_5
         default 6 if ESP_BROWNOUT_DET_LVL_SEL_6
         default 7 if ESP_BROWNOUT_DET_LVL_SEL_7
diff --git a/components/esp_system/port/soc/esp32p4/cache_err_int.c b/components/esp_system/port/soc/esp32p4/cache_err_int.c
index 24904c2d5a8..86e5b8da07d 100644
--- a/components/esp_system/port/soc/esp32p4/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32p4/cache_err_int.c
@@ -17,19 +17,22 @@
 #include "soc/periph_defs.h"
 #include "riscv/interrupt.h"
 #include "hal/cache_ll.h"
+#include "esp_private/cache_err_int.h"
 
 static const char *TAG = "CACHE_ERR";
 
 const char cache_error_msg[] = "Cache access error";
 
-const char *esp_cache_err_panic_string(void)
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
 {
+    if (err_info == NULL) {
+        return;
+    }
     uint32_t access_err_status = cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK) | cache_ll_l2_get_access_error_intr_status(0, CACHE_LL_L2_ACCESS_EVENT_MASK);
 
     /* Return the error string if a cache error is active */
-    const char* err_str = access_err_status ? cache_error_msg : NULL;
+    err_info->err_str = access_err_status ? cache_error_msg : NULL;
 
-    return err_str;
 }
 
 bool esp_cache_err_has_active_err(void)
diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c
index fabbfe22ed0..bb9a6e0aa51 100644
--- a/components/esp_system/port/soc/esp32p4/clk.c
+++ b/components/esp_system/port/soc/esp32p4/clk.c
@@ -189,6 +189,15 @@ static void select_rtc_slow_clk(soc_rtc_slow_clk_src_t rtc_slow_clk_src)
         }
         rtc_clk_slow_src_set(rtc_slow_clk_src);
 
+        // Disable unused clock sources after clock source switching is complete.
+        // Regardless of the clock source selection, the internal 136K clock source will always keep on.
+        if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
+            rtc_clk_32k_enable(false);
+        }
+        if (rtc_slow_clk_src != SOC_RTC_SLOW_CLK_SRC_RC32K) {
+            rtc_clk_rc32k_enable(false);
+        }
+
         if (SLOW_CLK_CAL_CYCLES > 0) {
             /* TODO: 32k XTAL oscillator has some frequency drift at startup.
              * Improve calibration routine to wait until the frequency is stable.
diff --git a/components/esp_system/port/soc/esp32p4/system_internal.c b/components/esp_system/port/soc/esp32p4/system_internal.c
index 79f5d23011d..86981428ea5 100644
--- a/components/esp_system/port/soc/esp32p4/system_internal.c
+++ b/components/esp_system/port/soc/esp32p4/system_internal.c
@@ -127,6 +127,9 @@ void IRAM_ATTR esp_restart_noos(void)
     wdt_hal_write_protect_enable(&wdt1_context);
 
     // Disable cache
+#if CONFIG_SPIRAM
+    Cache_WriteBack_All(CACHE_MAP_L1_DCACHE);
+#endif
     Cache_Disable_L2_Cache();
 
     esp_system_reset_modules_on_exit();
diff --git a/components/esp_system/port/soc/esp32s2/cache_err_int.c b/components/esp_system/port/soc/esp32s2/cache_err_int.c
index 0c969d79bc2..424fb49130a 100644
--- a/components/esp_system/port/soc/esp32s2/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32s2/cache_err_int.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,10 +25,133 @@
 #include "soc/extmem_reg.h"
 #include "soc/dport_reg.h"
 #include "soc/periph_defs.h"
+#include "hal/cache_ll.h"
 
 #include "esp_rom_sys.h"
 
 #include "sdkconfig.h"
+#include "esp_private/cache_err_int.h"
+
+#define DIM(array) (sizeof(array)/sizeof(*array))
+
+/**
+ * Structure used to define a flag/bit to test in case of cache error.
+ * The message describes the cause of the error when the bit is set in
+ * a given status register.
+ */
+typedef struct {
+    const uint32_t bit;
+    const char *msg;
+    const uint32_t fault_addr_reg;
+    const uint32_t fault_size_reg;
+} register_bit_t;
+
+/* Define the array that contains the status (bits) to test on the register
+ * EXTMEM_CACHE_DBG_STATUS0_REG. each bit is accompanied by a small
+ * message.
+ * The messages have been pulled from the header file where the status bit
+ * are defined.
+*/
+const register_bit_t dbg_status0_bits[] = {
+    {
+        .bit = EXTMEM_IC_SYNC_SIZE_FAULT_ST,
+        .msg = "Icache sync parameter configuration error",
+        .fault_addr_reg = EXTMEM_PRO_ICACHE_MEM_SYNC0_REG,
+        .fault_size_reg = EXTMEM_PRO_ICACHE_MEM_SYNC1_REG,
+    },
+    {
+        .bit = EXTMEM_IC_PRELOAD_SIZE_FAULT_ST,
+        .msg = "Icache preload parameter configuration error",
+        .fault_addr_reg = EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG,
+        .fault_size_reg = EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG,
+    },
+    {
+        .bit = EXTMEM_ICACHE_REJECT_ST,
+        .msg = "Icache reject error",
+        .fault_addr_reg = EXTMEM_PRO_ICACHE_REJECT_VADDR_REG,
+        .fault_size_reg = 0,
+    },
+};
+
+/* Define the array that contains the status (bits) to test on the register
+    * EXTMEM_CACHE_DBG_STATUS1_REG. each bit is accompanied by a small
+    * message.
+    * The messages have been pulled from the header file where the status bit
+    * are defined. */
+const register_bit_t dbg_status1_bits[] = {
+    {
+        .bit = EXTMEM_DC_SYNC_SIZE_FAULT_ST,
+        .msg = "Dcache sync parameter configuration error",
+        .fault_addr_reg = EXTMEM_PRO_DCACHE_MEM_SYNC0_REG,
+        .fault_size_reg = EXTMEM_PRO_DCACHE_MEM_SYNC1_REG,
+    },
+    {
+        .bit = EXTMEM_DC_PRELOAD_SIZE_FAULT_ST,
+        .msg = "Dcache preload parameter configuration error",
+        .fault_addr_reg = EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG,
+        .fault_size_reg = EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG,
+    },
+    {
+        .bit = EXTMEM_DCACHE_REJECT_ST,
+        .msg = "Dcache reject error",
+        .fault_addr_reg = EXTMEM_PRO_DCACHE_REJECT_VADDR_REG,
+        .fault_size_reg = 0,
+    },
+    {
+        .bit = EXTMEM_DCACHE_WRITE_FLASH_ST,
+        .msg = "Write back error occurred while dcache tries to write back to flash",
+        .fault_addr_reg = 0,
+        .fault_size_reg = 0,
+    },
+    {
+        .bit = EXTMEM_MMU_ENTRY_FAULT_ST,
+        .msg = "MMU entry fault error",
+        .fault_addr_reg = 0,
+        .fault_size_reg = 0,
+    },
+};
+/**
+ * Function to check each bits defined in the array reg_bits in the given
+ * status register. The first bit from the array to be set in the status
+ * register will have its associated message printed. This function returns
+ * true. If not bit was set in the register, it returns false.
+ * The order of the bits in the array is important as only the first bit to
+ * be set in the register will have its associated message printed.
+ */
+static inline void get_cache_error(const uint32_t status, const register_bit_t *reg_bits,
+                                   const uint32_t size, esp_cache_err_info_t *err_info)
+{
+    /* Browse the flag/bit array and test each one with the given status
+     * register. */
+    for (int i = 0; i < size; i++) {
+        const uint32_t bit = reg_bits[i].bit;
+        if ((status & bit) == bit) {
+            /* Reason of the panic found, print the reason. */
+            err_info->err_str = reg_bits[i].msg;
+            err_info->vaddr = reg_bits[i].fault_addr_reg ? REG_READ(reg_bits[i].fault_addr_reg) : 0;
+            err_info->size = reg_bits[i].fault_size_reg ? REG_READ(reg_bits[i].fault_size_reg) : 0;
+
+            return;
+        }
+    }
+}
+
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
+{
+    if (err_info == NULL) {
+        return;
+    }
+    /* Read the status register EXTMEM_CACHE_ILG_INT_ST_REG. This status
+     * register is not equal to 0 when a cache access error occurred. */
+    const uint32_t dbg_status0 = cache_ll_get_dbg_status0();
+    const uint32_t dbg_status1 = cache_ll_get_dbg_status1();
+
+    get_cache_error(dbg_status0, dbg_status0_bits, DIM(dbg_status0_bits), err_info);
+
+    if (err_info->err_str == NULL) {
+        get_cache_error(dbg_status1, dbg_status1_bits, DIM(dbg_status1_bits), err_info);
+    }
+}
 
 void esp_cache_err_int_init(void)
 {
diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c
index 45d932ba520..2b786b62f9a 100644
--- a/components/esp_system/port/soc/esp32s2/clk.c
+++ b/components/esp_system/port/soc/esp32s2/clk.c
@@ -240,7 +240,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                            DPORT_PWM0_CLK_EN |
                            DPORT_TWAI_CLK_EN |
                            DPORT_PWM1_CLK_EN |
-                           DPORT_I2S1_CLK_EN |
                            DPORT_SPI2_DMA_CLK_EN |
                            DPORT_SPI3_DMA_CLK_EN |
                            DPORT_PWM2_CLK_EN |
@@ -276,7 +275,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
                         DPORT_UHCI1_CLK_EN |
                         DPORT_SPI3_CLK_EN |
                         DPORT_I2C_EXT1_CLK_EN |
-                        DPORT_I2S1_CLK_EN |
                         DPORT_SPI2_DMA_CLK_EN |
                         DPORT_SPI3_DMA_CLK_EN;
     common_perip_clk1 = 0;
diff --git a/components/esp_system/port/soc/esp32s2/system_internal.c b/components/esp_system/port/soc/esp32s2/system_internal.c
index 3de3bafdf18..8eb6c0325c2 100644
--- a/components/esp_system/port/soc/esp32s2/system_internal.c
+++ b/components/esp_system/port/soc/esp32s2/system_internal.c
@@ -85,9 +85,9 @@ void IRAM_ATTR esp_restart_noos(void)
     wdt_hal_disable(&wdt1_context);
     wdt_hal_write_protect_enable(&wdt1_context);
 
-#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
     if (esp_ptr_external_ram(esp_cpu_get_sp())) {
-        // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
+        // If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used)
         // then need to switch SP to Internal Memory otherwise
         // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
         uint32_t new_sp = ALIGN_DOWN(_bss_end, 16);
diff --git a/components/esp_system/port/soc/esp32s3/cache_err_int.c b/components/esp_system/port/soc/esp32s3/cache_err_int.c
index d87d1ea3678..9e6499b86a7 100644
--- a/components/esp_system/port/soc/esp32s3/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32s3/cache_err_int.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,9 +23,109 @@
 #include "soc/periph_defs.h"
 #include "esp_rom_sys.h"
 #include "hal/cache_ll.h"
+#include "soc/syscon_struct.h"
+#include "esp_private/cache_err_int.h"
 
 static const char *TAG = "CACHE_ERR";
 
+#define DIM(array) (sizeof(array)/sizeof(*array))
+
+/**
+ * Structure used to define a flag/bit to test in case of cache error.
+ * The message describes the cause of the error when the bit is set in
+ * a given status register.
+ */
+typedef struct {
+    const uint32_t bit;
+    const char *msg;
+    const uint32_t fault_addr_reg;
+    const uint32_t fault_size_reg;
+} register_bit_t;
+
+/* Define the array that contains the status (bits) to test on the register
+ * EXTMEM_CACHE_ILG_INT_ST_REG. each bit is accompanied by a small
+ * message.
+ * The messages have been pulled from the header file where the status bit
+ * are defined.
+*/
+const register_bit_t ilg_int_st_bits[] = {
+    {
+        .bit = EXTMEM_ICACHE_SYNC_OP_FAULT_ST,
+        .msg = "Icache sync parameter configuration error",
+        .fault_addr_reg = 0,
+        .fault_size_reg = 0,
+    },
+    {
+        .bit = EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST,
+        .msg = "Icache preload parameter configuration error",
+        .fault_addr_reg = 0,
+        .fault_size_reg = 0,
+    },
+    {
+        .bit = EXTMEM_DCACHE_SYNC_OP_FAULT_ST,
+        .msg = "Dcache sync parameter configuration error",
+        .fault_addr_reg = 0,
+        .fault_size_reg = 0,
+    },
+    {
+        .bit = EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST,
+        .msg = "Dcache preload parameter configuration error",
+        .fault_addr_reg = 0,
+        .fault_size_reg = 0,
+    },
+    {
+        .bit = EXTMEM_DCACHE_WRITE_FLASH_ST,
+        .msg = "Write back error occurred while dcache tries to write back to flash\r\nThe following backtrace may not indicate the code that caused Cache invalid access",
+        .fault_addr_reg = 0,
+        .fault_size_reg = 0,
+    },
+    {
+        .bit = EXTMEM_MMU_ENTRY_FAULT_ST,
+        .msg = "MMU entry fault error",
+        .fault_addr_reg = 0,
+        .fault_size_reg = 0,
+    },
+};
+
+/**
+ * Function to check each bits defined in the array reg_bits in the given
+ * status register. The first bit from the array to be set in the status
+ * register will have its associated message printed. This function returns
+ * true. If not bit was set in the register, it returns false.
+ * The order of the bits in the array is important as only the first bit to
+ * be set in the register will have its associated message printed.
+ */
+static inline void get_cache_error(const uint32_t status, const register_bit_t *reg_bits,
+                                   const uint32_t size, esp_cache_err_info_t *err_info)
+{
+    /* Browse the flag/bit array and test each one with the given status
+     * register. */
+    for (int i = 0; i < size; i++) {
+        const uint32_t bit = reg_bits[i].bit;
+        if ((status & bit) == bit) {
+            /* Reason of the panic found, print the reason. */
+            err_info->err_str = reg_bits[i].msg;
+            err_info->vaddr = reg_bits[i].fault_addr_reg ? REG_READ(reg_bits[i].fault_addr_reg) : 0;
+            err_info->size = reg_bits[i].fault_size_reg ? REG_READ(reg_bits[i].fault_size_reg) : 0;
+
+            return;
+        }
+    }
+}
+
+void esp_cache_err_get_panic_info(esp_cache_err_info_t *err_info)
+{
+    if (err_info == NULL) {
+        return;
+    }
+    /* Read the status register EXTMEM_CACHE_ILG_INT_ST_REG. This status
+     * register is not equal to 0 when a cache access error occurred. */
+    const uint32_t illegal_intr_status = cache_ll_l1_get_illegal_error_intr_status(0, CACHE_LL_L1_ILG_EVENT_MASK);
+
+    get_cache_error(illegal_intr_status, ilg_int_st_bits, DIM(ilg_int_st_bits), err_info);
+
+}
+
 void esp_cache_err_int_init(void)
 {
     uint32_t core_id = esp_cpu_get_core_id();
@@ -52,7 +152,7 @@ void esp_cache_err_int_init(void)
     if (core_id == PRO_CPU_NUM) {
         esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
 
-        /* On the hardware side, stat by clearing all the bits reponsible for
+        /* On the hardware side, stat by clearing all the bits responsible for
          * enabling cache access error interrupts.  */
         ESP_DRAM_LOGV(TAG, "core 0 access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
         cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
@@ -60,7 +160,7 @@ void esp_cache_err_int_init(void)
     } else {
         esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
 
-        /* On the hardware side, stat by clearing all the bits reponsible for
+        /* On the hardware side, stat by clearing all the bits responsible for
          * enabling cache access error interrupts.  */
         ESP_DRAM_LOGV(TAG, "core 1 access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
         cache_ll_l1_clear_access_error_intr(1, CACHE_LL_L1_ACCESS_EVENT_MASK);
diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c
index ebdaccbcb25..f0edae876cb 100644
--- a/components/esp_system/port/soc/esp32s3/system_internal.c
+++ b/components/esp_system/port/soc/esp32s3/system_internal.c
@@ -92,9 +92,9 @@ void IRAM_ATTR esp_restart_noos(void)
     wdt_hal_disable(&wdt1_context);
     wdt_hal_write_protect_enable(&wdt1_context);
 
-#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
     if (esp_ptr_external_ram(esp_cpu_get_sp())) {
-        // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
+        // If stack_addr is from External Memory (CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM is used)
         // then need to switch SP to Internal Memory otherwise
         // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
         uint32_t new_sp = ALIGN_DOWN(_bss_end, 16);
diff --git a/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c b/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c
index 6dfc11af787..a95ae8369a5 100644
--- a/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c
+++ b/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c
@@ -96,7 +96,7 @@ static void IRAM_ATTR cache_access_test_func(void* arg)
 #endif
 
 // These tests works properly if they resets the chip with the
-// "Cache disabled but cached memory region accessed" reason and the correct CPU is logged.
+// "Cache Error" reason and the correct CPU is logged.
 static void invalid_access_to_cache_pro_cpu(void)
 {
     xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0);
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
index 3008f15b62c..491c3299b45 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
+++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_reset_reason.c
@@ -318,7 +318,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event",
                           do_brownout,
                           check_reset_reason_brownout);
 
-#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
 #ifndef CONFIG_FREERTOS_UNICORE
 #if CONFIG_IDF_TARGET_ARCH_XTENSA
 #include "xt_instr_macros.h"
@@ -402,6 +402,6 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after an exception in a ta
 
 #endif //CONFIG_IDF_TARGET_ARCH_XTENSA
 #endif // CONFIG_FREERTOS_UNICORE
-#endif // CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#endif // CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
 
 /* Not tested here: ESP_RST_SDIO */
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c
index d82cf13d625..58793d18249 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c
+++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c
@@ -51,7 +51,7 @@ TEST_CASE("rtos_systick_etm_event", "[etm]")
 
     TEST_ESP_OK(esp_etm_channel_enable(etm_channel_a));
 
-    // should see a 500Hz square wave on the GPIO (if RTOS systick is set to 1000Hz)
+    // should see a 50Hz square wave on the GPIO (if RTOS systick is set to 100Hz)
     vTaskDelay(pdMS_TO_TICKS(1000));
 
     // delete etm primitives
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram
index 482bcd8baa5..f29df53fffe 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram
+++ b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram
@@ -1,2 +1,2 @@
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
diff --git a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram_with_pd_top b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram_with_pd_top
index 440009beb18..d1b0d302443 100644
--- a/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram_with_pd_top
+++ b/components/esp_system/test_apps/esp_system_unity_tests/sdkconfig.ci.psram_with_pd_top
@@ -1,4 +1,4 @@
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP=y
 CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
diff --git a/components/esp_timer/src/esp_timer_impl_lac.c b/components/esp_timer/src/esp_timer_impl_lac.c
index d557716e659..79503303af5 100644
--- a/components/esp_timer/src/esp_timer_impl_lac.c
+++ b/components/esp_timer/src/esp_timer_impl_lac.c
@@ -222,11 +222,11 @@ static void IRAM_ATTR timer_alarm_isr(void *arg)
 
 void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us)
 {
-    portENTER_CRITICAL(&s_time_update_lock);
+    portENTER_CRITICAL_SAFE(&s_time_update_lock);
     assert(apb_ticks_per_us >= 3 && "divider value too low");
     assert(apb_ticks_per_us % TICKS_PER_US == 0 && "APB frequency (in MHz) should be divisible by TICK_PER_US");
     REG_SET_FIELD(CONFIG_REG, TIMG_LACT_DIVIDER, apb_ticks_per_us / TICKS_PER_US);
-    portEXIT_CRITICAL(&s_time_update_lock);
+    portEXIT_CRITICAL_SAFE(&s_time_update_lock);
 }
 
 void esp_timer_impl_set(uint64_t new_us)
diff --git a/components/esp_wifi/Kconfig b/components/esp_wifi/Kconfig
index eb69f2056ce..f105c83ff3f 100644
--- a/components/esp_wifi/Kconfig
+++ b/components/esp_wifi/Kconfig
@@ -28,8 +28,8 @@ menu "Wi-Fi"
             int "Max number of WiFi static RX buffers"
             range 2 25 if !SOC_WIFI_HE_SUPPORT
             range 2 128 if SOC_WIFI_HE_SUPPORT
-            default 10 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
-            default 16 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+            default 10 if !(SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
+            default 16 if (SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
             help
                 Set the number of WiFi static RX buffers. Each buffer takes approximately 1.6KB of RAM.
                 The static rx buffers are allocated when esp_wifi_init is called, they are not freed
@@ -80,7 +80,7 @@ menu "Wi-Fi"
                 bool "Static"
             config ESP_WIFI_DYNAMIC_TX_BUFFER
                 bool "Dynamic"
-                depends on !SPIRAM_USE_MALLOC
+                depends on !(SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
         endchoice
 
         config ESP_WIFI_TX_BUFFER_TYPE
@@ -105,8 +105,8 @@ menu "Wi-Fi"
 
         config ESP_WIFI_CACHE_TX_BUFFER_NUM
             int "Max number of WiFi cache TX buffers"
-            depends on SPIRAM
-            range 16 128
+            depends on (SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
+            range 0 128
             default 32
             help
                 Set the number of WiFi cache TX buffer number.
@@ -203,8 +203,8 @@ menu "Wi-Fi"
             depends on ESP_WIFI_AMPDU_RX_ENABLED
             range 2 32 if !SOC_WIFI_HE_SUPPORT
             range 2 64 if SOC_WIFI_HE_SUPPORT
-            default 6 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
-            default 16 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+            default 6 if !(SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
+            default 16 if (SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
             help
                 Set the size of WiFi Block Ack RX window. Generally a bigger value means higher throughput and better
                 compatibility but more memory. Most of time we should NOT change the default value unless special
@@ -215,7 +215,7 @@ menu "Wi-Fi"
 
         config ESP_WIFI_AMSDU_TX_ENABLED
             bool "WiFi AMSDU TX"
-            depends on SPIRAM
+            depends on (ESP_WIFI_CACHE_TX_BUFFER_NUM >= 2)
             default n
             help
                 Select this option to enable AMSDU TX feature
diff --git a/components/esp_wifi/include/esp_mesh.h b/components/esp_wifi/include/esp_mesh.h
index 18e55c2dfdb..7a7e85cf893 100644
--- a/components/esp_wifi/include/esp_mesh.h
+++ b/components/esp_wifi/include/esp_mesh.h
@@ -637,7 +637,8 @@ esp_err_t esp_mesh_stop(void);
  * @param[in]  to  the address of the final destination of the packet
  *             - If the packet is to the root, set this parameter to NULL.
  *             - If the packet is to an external IP network, set this parameter to the IPv4:PORT combination.
- *               This packet will be delivered to the root firstly, then the root will forward this packet to the final IP server address.
+ *               This packet will be delivered to the root firstly, then users need to call esp_mesh_recv_toDS() on the root node to forward this
+ *               packet to the final IP server address.
  * @param[in]  data  pointer to a sending mesh packet
  *             - Field size should not exceed MESH_MPS. Note that the size of one mesh packet should not exceed MESH_MTU.
  *             - Field proto should be set to data protocol in use (default is MESH_PROTO_BIN for binary).
diff --git a/components/esp_wifi/include/esp_now.h b/components/esp_wifi/include/esp_now.h
index 734fbcf8bf9..af7695e2587 100644
--- a/components/esp_wifi/include/esp_now.h
+++ b/components/esp_wifi/include/esp_now.h
@@ -98,9 +98,10 @@ typedef struct esp_now_recv_info {
  */
 typedef struct esp_now_rate_config {
     wifi_phy_mode_t phymode;                 /**< ESPNOW phymode of specified interface */
-    wifi_phy_rate_t rate;                    /**< ESPNOW rate of specified interface*/
-    bool ersu;                               /**< ESPNOW using ersu send frame*/
-    bool dcm;                                /**< ESPNOW using dcm rate to send frame*/
+    wifi_phy_rate_t rate;                    /**< ESPNOW rate of specified interface */
+    bool ersu;                               /**< ESPNOW using ERSU to send frame, ERSU is a transmission mode related to 802.11 ax.
+                                                  ERSU is always used in long distance transmission, and its frame has lower rate compared with SU mode */
+    bool dcm;                                /**< ESPNOW using dcm rate to send frame */
 } esp_now_rate_config_t;
 
 /**
diff --git a/components/esp_wifi/include/esp_wifi.h b/components/esp_wifi/include/esp_wifi.h
index ce08ecb7484..fc321d20367 100644
--- a/components/esp_wifi/include/esp_wifi.h
+++ b/components/esp_wifi/include/esp_wifi.h
@@ -129,7 +129,7 @@ typedef struct {
 #define WIFI_STATIC_TX_BUFFER_NUM 0
 #endif
 
-#if CONFIG_SPIRAM
+#ifdef CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM
 #define WIFI_CACHE_TX_BUFFER_NUM  CONFIG_ESP_WIFI_CACHE_TX_BUFFER_NUM
 #else
 #define WIFI_CACHE_TX_BUFFER_NUM  0
@@ -224,10 +224,10 @@ extern wifi_osi_funcs_t g_wifi_osi_funcs;
 #define WIFI_ENABLE_WPA3_SAE 0
 #endif
 
-#if CONFIG_SPIRAM
-#define WIFI_ENABLE_SPIRAM (1<<1)
+#if WIFI_CACHE_TX_BUFFER_NUM > 0
+#define WIFI_ENABLE_CACHE_TX_BUFFER (1<<1)
 #else
-#define WIFI_ENABLE_SPIRAM 0
+#define WIFI_ENABLE_CACHE_TX_BUFFER 0
 #endif
 
 #if CONFIG_ESP_WIFI_FTM_INITIATOR_SUPPORT
@@ -289,7 +289,7 @@ extern wifi_osi_funcs_t g_wifi_osi_funcs;
 
 /* Set additional WiFi features and capabilities */
 #define WIFI_FEATURE_CAPS (WIFI_ENABLE_WPA3_SAE | \
-                           WIFI_ENABLE_SPIRAM  | \
+                           WIFI_ENABLE_CACHE_TX_BUFFER  | \
                            WIFI_FTM_INITIATOR | \
                            WIFI_FTM_RESPONDER | \
                            WIFI_ENABLE_GCMP | \
diff --git a/components/esp_wifi/include/esp_wifi_he.h b/components/esp_wifi/include/esp_wifi_he.h
index 99a3be564b2..619c7b3fa6c 100644
--- a/components/esp_wifi/include/esp_wifi_he.h
+++ b/components/esp_wifi/include/esp_wifi_he.h
@@ -9,6 +9,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include "esp_err.h"
+#include "esp_wifi_types.h"
 #include "esp_wifi_he_types.h"
 
 #ifdef __cplusplus
@@ -219,15 +220,18 @@ esp_err_t esp_wifi_sta_twt_config(wifi_twt_config_t *config);
 /**
   * @brief     Enable bss color collision detection.
   *
-  * @param[in] enable If true, when the station detects a BSS color collision, it will report the BSS color collision event to the access point (AP).
+  * @attention Currently, only STA BSS color collision detection is supported.
+  *
+  * @param     ifx interface to be configured
+  * @param     enable If true, when the STA detects a BSS color collision, it will report the BSS color collision event to the access point (AP).
   *
   * @return
   *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_IF: Invalid interface
   *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
   *    - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
-  *    - ESP_ERR_NOT_SUPPORTED: This API is not supported in AP mode yet
   */
-esp_err_t esp_wifi_sta_enable_bsscolor_collision_detection(bool enable);
+esp_err_t esp_wifi_enable_bsscolor_collision_detection(wifi_interface_t ifx, bool enable);
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_wifi/include/esp_wifi_he_types.h b/components/esp_wifi/include/esp_wifi_he_types.h
index e9dc2e17a4d..e2fe9c9f755 100644
--- a/components/esp_wifi/include/esp_wifi_he_types.h
+++ b/components/esp_wifi/include/esp_wifi_he_types.h
@@ -406,6 +406,7 @@ typedef enum {
 /** Argument structure for twt configuration */
 typedef struct {
     bool post_wakeup_event;              /**< post twt wakeup event */
+    bool twt_enable_keep_alive;          /**< twt enable send qos null to keep alive */
 } wifi_twt_config_t;
 
 /** Argument structure for WIFI_EVENT_TWT_WAKEUP event */
diff --git a/components/esp_wifi/include/esp_wifi_types_generic.h b/components/esp_wifi/include/esp_wifi_types_generic.h
index 3e49682df5a..a232069fa47 100644
--- a/components/esp_wifi/include/esp_wifi_types_generic.h
+++ b/components/esp_wifi/include/esp_wifi_types_generic.h
@@ -17,145 +17,173 @@
 extern "C" {
 #endif
 
+/**
+  * @brief Wi-Fi mode type
+  */
 typedef enum {
-    WIFI_MODE_NULL = 0,  /**< null mode */
-    WIFI_MODE_STA,       /**< WiFi station mode */
-    WIFI_MODE_AP,        /**< WiFi soft-AP mode */
-    WIFI_MODE_APSTA,     /**< WiFi station + soft-AP mode */
-    WIFI_MODE_NAN,       /**< WiFi NAN mode */
+    WIFI_MODE_NULL = 0,  /**< Null mode */
+    WIFI_MODE_STA,       /**< Wi-Fi station mode */
+    WIFI_MODE_AP,        /**< Wi-Fi soft-AP mode */
+    WIFI_MODE_APSTA,     /**< Wi-Fi station + soft-AP mode */
+    WIFI_MODE_NAN,       /**< Wi-Fi NAN mode */
     WIFI_MODE_MAX
 } wifi_mode_t;
 
+/**
+  * @brief Wi-Fi interface type
+  */
 typedef enum {
-    WIFI_IF_STA = ESP_IF_WIFI_STA,
-    WIFI_IF_AP  = ESP_IF_WIFI_AP,
+    WIFI_IF_STA = ESP_IF_WIFI_STA,    /**< Station interface */
+    WIFI_IF_AP  = ESP_IF_WIFI_AP,     /**< Soft-AP interface */
 #if CONFIG_SOC_WIFI_NAN_SUPPORT || !CONFIG_SOC_WIFI_ENABLED
-    WIFI_IF_NAN = ESP_IF_WIFI_NAN,
+    WIFI_IF_NAN = ESP_IF_WIFI_NAN,    /**< NAN interface */
 #endif
-    WIFI_IF_MAX
+    WIFI_IF_MAX                       /**< Maximum number of interfaces */
 } wifi_interface_t;
 
-#define WIFI_OFFCHAN_TX_REQ      1
-#define WIFI_OFFCHAN_TX_CANCEL   0
+#define WIFI_OFFCHAN_TX_REQ      1    /**< Request off-channel transmission */
+#define WIFI_OFFCHAN_TX_CANCEL   0    /**< Cancel off-channel transmission */
 
-#define WIFI_ROC_REQ     1
-#define WIFI_ROC_CANCEL  0
+#define WIFI_ROC_REQ     1    /**< Request remain on channel */
+#define WIFI_ROC_CANCEL  0    /**< Cancel remain on channel */
 
+/**
+  * @brief Wi-Fi country policy
+  */
 typedef enum {
     WIFI_COUNTRY_POLICY_AUTO,   /**< Country policy is auto, use the country info of AP to which the station is connected */
     WIFI_COUNTRY_POLICY_MANUAL, /**< Country policy is manual, always use the configured country info */
 } wifi_country_policy_t;
 
-/** @brief Structure describing WiFi country-based regional restrictions. */
+/**
+  * @brief Structure describing Wi-Fi country-based regional restrictions.
+  */
 typedef struct {
-    char                  cc[3];   /**< country code string */
-    uint8_t               schan;   /**< start channel of the allowed 2.4GHz WiFi channels */
-    uint8_t               nchan;   /**< total channel number of the allowed 2.4GHz WiFi channels */
-    int8_t                max_tx_power;   /**< This field is used for getting WiFi maximum transmitting power, call esp_wifi_set_max_tx_power to set the maximum transmitting power. */
-    wifi_country_policy_t policy;  /**< country policy */
+    char                  cc[3];   /**< Country code string */
+    uint8_t               schan;   /**< Start channel of the allowed 2.4GHz Wi-Fi channels */
+    uint8_t               nchan;   /**< Total channel number of the allowed 2.4GHz Wi-Fi channels */
+    int8_t                max_tx_power;   /**< This field is used for getting Wi-Fi maximum transmitting power, call esp_wifi_set_max_tx_power to set the maximum transmitting power. */
+    wifi_country_policy_t policy;  /**< Country policy */
 #if CONFIG_SOC_WIFI_SUPPORT_5G
-    uint32_t              wifi_5g_channel_mask;  /**< A bitmask representing the allowed 5GHz WiFi channels.
+    uint32_t              wifi_5g_channel_mask;  /**< A bitmask representing the allowed 5GHz Wi-Fi channels.
                                                       Each bit in the mask corresponds to a specific channel as wifi_5g_channel_bit_t shown.
                                                       Bitmask set to 0 indicates 5GHz channels are allowed according to local regulatory rules.
                                                       Please note that configured bitmask takes effect only when policy is manual. */
 #endif
 } wifi_country_t;
 
-/* Strength of authmodes */
-/* OPEN < WEP < WPA_PSK < OWE < WPA2_PSK = WPA_WPA2_PSK < WAPI_PSK < WPA3_PSK = WPA2_WPA3_PSK = DPP */
+/**
+  * @brief Wi-Fi authmode type
+  * Strength of authmodes
+  * Personal Networks   : OPEN < WEP < WPA_PSK < OWE < WPA2_PSK = WPA_WPA2_PSK < WAPI_PSK < WPA3_PSK = WPA2_WPA3_PSK = DPP
+  * Enterprise Networks : WIFI_AUTH_WPA2_ENTERPRISE < WIFI_AUTH_WPA3_ENTERPRISE = WIFI_AUTH_WPA2_WPA3_ENTERPRISE < WIFI_AUTH_WPA3_ENT_192
+  */
 typedef enum {
-    WIFI_AUTH_OPEN = 0,         /**< authenticate mode : open */
-    WIFI_AUTH_WEP,              /**< authenticate mode : WEP */
-    WIFI_AUTH_WPA_PSK,          /**< authenticate mode : WPA_PSK */
-    WIFI_AUTH_WPA2_PSK,         /**< authenticate mode : WPA2_PSK */
-    WIFI_AUTH_WPA_WPA2_PSK,     /**< authenticate mode : WPA_WPA2_PSK */
-    WIFI_AUTH_ENTERPRISE,       /**< authenticate mode : WiFi EAP security */
-    WIFI_AUTH_WPA2_ENTERPRISE = WIFI_AUTH_ENTERPRISE,  /**< authenticate mode : WiFi EAP security */
-    WIFI_AUTH_WPA3_PSK,         /**< authenticate mode : WPA3_PSK */
-    WIFI_AUTH_WPA2_WPA3_PSK,    /**< authenticate mode : WPA2_WPA3_PSK */
-    WIFI_AUTH_WAPI_PSK,         /**< authenticate mode : WAPI_PSK */
-    WIFI_AUTH_OWE,              /**< authenticate mode : OWE */
-    WIFI_AUTH_WPA3_ENT_192,     /**< authenticate mode : WPA3_ENT_SUITE_B_192_BIT */
-    WIFI_AUTH_WPA3_EXT_PSK,     /**< this authentication mode will yield same result as WIFI_AUTH_WPA3_PSK and not recommended to be used. It will be deprecated in future, please use WIFI_AUTH_WPA3_PSK instead. */
-    WIFI_AUTH_WPA3_EXT_PSK_MIXED_MODE, /**< this authentication mode will yield same result as WIFI_AUTH_WPA3_PSK and not recommended to be used. It will be deprecated in future, please use WIFI_AUTH_WPA3_PSK instead.*/
-    WIFI_AUTH_DPP,              /**< authenticate mode : DPP */
+    WIFI_AUTH_OPEN = 0,         /**< Authenticate mode : open */
+    WIFI_AUTH_WEP,              /**< Authenticate mode : WEP */
+    WIFI_AUTH_WPA_PSK,          /**< Authenticate mode : WPA_PSK */
+    WIFI_AUTH_WPA2_PSK,         /**< Authenticate mode : WPA2_PSK */
+    WIFI_AUTH_WPA_WPA2_PSK,     /**< Authenticate mode : WPA_WPA2_PSK */
+    WIFI_AUTH_ENTERPRISE,       /**< Authenticate mode : Wi-Fi EAP security */
+    WIFI_AUTH_WPA2_ENTERPRISE = WIFI_AUTH_ENTERPRISE,  /**< Authenticate mode : Wi-Fi EAP security */
+    WIFI_AUTH_WPA3_PSK,         /**< Authenticate mode : WPA3_PSK */
+    WIFI_AUTH_WPA2_WPA3_PSK,    /**< Authenticate mode : WPA2_WPA3_PSK */
+    WIFI_AUTH_WAPI_PSK,         /**< Authenticate mode : WAPI_PSK */
+    WIFI_AUTH_OWE,              /**< Authenticate mode : OWE */
+    WIFI_AUTH_WPA3_ENT_192,     /**< Authenticate mode : WPA3_ENT_SUITE_B_192_BIT */
+    WIFI_AUTH_WPA3_EXT_PSK,     /**< This authentication mode will yield same result as WIFI_AUTH_WPA3_PSK and not recommended to be used. It will be deprecated in future, please use WIFI_AUTH_WPA3_PSK instead. */
+    WIFI_AUTH_WPA3_EXT_PSK_MIXED_MODE, /**< This authentication mode will yield same result as WIFI_AUTH_WPA3_PSK and not recommended to be used. It will be deprecated in future, please use WIFI_AUTH_WPA3_PSK instead.*/
+    WIFI_AUTH_DPP,              /**< Authenticate mode : DPP */
+    WIFI_AUTH_WPA3_ENTERPRISE,  /**< Authenticate mode : WPA3-Enterprise Only Mode */
+    WIFI_AUTH_WPA2_WPA3_ENTERPRISE, /**< Authenticate mode : WPA3-Enterprise Transition Mode */
     WIFI_AUTH_MAX
 } wifi_auth_mode_t;
 
+/**
+  * @brief Wi-Fi disconnection reason codes
+  *
+  * These reason codes are used to indicate the cause of disconnection.
+  */
 typedef enum {
-    WIFI_REASON_UNSPECIFIED                        = 1,
-    WIFI_REASON_AUTH_EXPIRE                        = 2,
-    WIFI_REASON_AUTH_LEAVE                         = 3,
-    WIFI_REASON_ASSOC_EXPIRE                       = 4,
-    WIFI_REASON_ASSOC_TOOMANY                      = 5,
-    WIFI_REASON_NOT_AUTHED                         = 6,
-    WIFI_REASON_NOT_ASSOCED                        = 7,
-    WIFI_REASON_ASSOC_LEAVE                        = 8,
-    WIFI_REASON_ASSOC_NOT_AUTHED                   = 9,
-    WIFI_REASON_DISASSOC_PWRCAP_BAD                = 10,
-    WIFI_REASON_DISASSOC_SUPCHAN_BAD               = 11,
-    WIFI_REASON_BSS_TRANSITION_DISASSOC            = 12,
-    WIFI_REASON_IE_INVALID                         = 13,
-    WIFI_REASON_MIC_FAILURE                        = 14,
-    WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT             = 15,
-    WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT           = 16,
-    WIFI_REASON_IE_IN_4WAY_DIFFERS                 = 17,
-    WIFI_REASON_GROUP_CIPHER_INVALID               = 18,
-    WIFI_REASON_PAIRWISE_CIPHER_INVALID            = 19,
-    WIFI_REASON_AKMP_INVALID                       = 20,
-    WIFI_REASON_UNSUPP_RSN_IE_VERSION              = 21,
-    WIFI_REASON_INVALID_RSN_IE_CAP                 = 22,
-    WIFI_REASON_802_1X_AUTH_FAILED                 = 23,
-    WIFI_REASON_CIPHER_SUITE_REJECTED              = 24,
-    WIFI_REASON_TDLS_PEER_UNREACHABLE              = 25,
-    WIFI_REASON_TDLS_UNSPECIFIED                   = 26,
-    WIFI_REASON_SSP_REQUESTED_DISASSOC             = 27,
-    WIFI_REASON_NO_SSP_ROAMING_AGREEMENT           = 28,
-    WIFI_REASON_BAD_CIPHER_OR_AKM                  = 29,
-    WIFI_REASON_NOT_AUTHORIZED_THIS_LOCATION       = 30,
-    WIFI_REASON_SERVICE_CHANGE_PERCLUDES_TS        = 31,
-    WIFI_REASON_UNSPECIFIED_QOS                    = 32,
-    WIFI_REASON_NOT_ENOUGH_BANDWIDTH               = 33,
-    WIFI_REASON_MISSING_ACKS                       = 34,
-    WIFI_REASON_EXCEEDED_TXOP                      = 35,
-    WIFI_REASON_STA_LEAVING                        = 36,
-    WIFI_REASON_END_BA                             = 37,
-    WIFI_REASON_UNKNOWN_BA                         = 38,
-    WIFI_REASON_TIMEOUT                            = 39,
-    WIFI_REASON_PEER_INITIATED                     = 46,
-    WIFI_REASON_AP_INITIATED                       = 47,
-    WIFI_REASON_INVALID_FT_ACTION_FRAME_COUNT      = 48,
-    WIFI_REASON_INVALID_PMKID                      = 49,
-    WIFI_REASON_INVALID_MDE                        = 50,
-    WIFI_REASON_INVALID_FTE                        = 51,
-    WIFI_REASON_TRANSMISSION_LINK_ESTABLISH_FAILED = 67,
-    WIFI_REASON_ALTERATIVE_CHANNEL_OCCUPIED        = 68,
-
-    WIFI_REASON_BEACON_TIMEOUT                     = 200,
-    WIFI_REASON_NO_AP_FOUND                        = 201,
-    WIFI_REASON_AUTH_FAIL                          = 202,
-    WIFI_REASON_ASSOC_FAIL                         = 203,
-    WIFI_REASON_HANDSHAKE_TIMEOUT                  = 204,
-    WIFI_REASON_CONNECTION_FAIL                    = 205,
-    WIFI_REASON_AP_TSF_RESET                       = 206,
-    WIFI_REASON_ROAMING                            = 207,
-    WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG       = 208,
-    WIFI_REASON_SA_QUERY_TIMEOUT                   = 209,
-    WIFI_REASON_NO_AP_FOUND_W_COMPATIBLE_SECURITY  = 210,
-    WIFI_REASON_NO_AP_FOUND_IN_AUTHMODE_THRESHOLD  = 211,
-    WIFI_REASON_NO_AP_FOUND_IN_RSSI_THRESHOLD      = 212,
+    WIFI_REASON_UNSPECIFIED                        = 1,     /**< Unspecified reason */
+    WIFI_REASON_AUTH_EXPIRE                        = 2,     /**< Authentication expired */
+    WIFI_REASON_AUTH_LEAVE                         = 3,     /**< Deauthentication due to leaving */
+    WIFI_REASON_ASSOC_EXPIRE                       = 4,     /**< Deprecated, will be removed in next IDF major release */
+    WIFI_REASON_DISASSOC_DUE_TO_INACTIVITY         = 4,     /**< Disassociated due to inactivity */
+    WIFI_REASON_ASSOC_TOOMANY                      = 5,     /**< Too many associated stations */
+    WIFI_REASON_NOT_AUTHED                         = 6,     /**< Deprecated, will be removed in next IDF major release */
+    WIFI_REASON_CLASS2_FRAME_FROM_NONAUTH_STA      = 6,     /**< Class 2 frame received from nonauthenticated STA */
+    WIFI_REASON_NOT_ASSOCED                        = 7,     /**< Deprecated, will be removed in next IDF major release */
+    WIFI_REASON_CLASS3_FRAME_FROM_NONASSOC_STA     = 7,     /**< Class 3 frame received from nonassociated STA */
+    WIFI_REASON_ASSOC_LEAVE                        = 8,     /**< Deassociated due to leaving */
+    WIFI_REASON_ASSOC_NOT_AUTHED                   = 9,     /**< Association but not authenticated */
+    WIFI_REASON_DISASSOC_PWRCAP_BAD                = 10,    /**< Disassociated due to poor power capability */
+    WIFI_REASON_DISASSOC_SUPCHAN_BAD               = 11,    /**< Disassociated due to unsupported channel */
+    WIFI_REASON_BSS_TRANSITION_DISASSOC            = 12,    /**< Disassociated due to BSS transition */
+    WIFI_REASON_IE_INVALID                         = 13,    /**< Invalid Information Element (IE) */
+    WIFI_REASON_MIC_FAILURE                        = 14,    /**< MIC failure */
+    WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT             = 15,    /**< 4-way handshake timeout */
+    WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT           = 16,    /**< Group key update timeout */
+    WIFI_REASON_IE_IN_4WAY_DIFFERS                 = 17,    /**< IE differs in 4-way handshake */
+    WIFI_REASON_GROUP_CIPHER_INVALID               = 18,    /**< Invalid group cipher */
+    WIFI_REASON_PAIRWISE_CIPHER_INVALID            = 19,    /**< Invalid pairwise cipher */
+    WIFI_REASON_AKMP_INVALID                       = 20,    /**< Invalid AKMP */
+    WIFI_REASON_UNSUPP_RSN_IE_VERSION              = 21,    /**< Unsupported RSN IE version */
+    WIFI_REASON_INVALID_RSN_IE_CAP                 = 22,    /**< Invalid RSN IE capabilities */
+    WIFI_REASON_802_1X_AUTH_FAILED                 = 23,    /**< 802.1X authentication failed */
+    WIFI_REASON_CIPHER_SUITE_REJECTED              = 24,    /**< Cipher suite rejected */
+    WIFI_REASON_TDLS_PEER_UNREACHABLE              = 25,    /**< TDLS peer unreachable */
+    WIFI_REASON_TDLS_UNSPECIFIED                   = 26,    /**< TDLS unspecified */
+    WIFI_REASON_SSP_REQUESTED_DISASSOC             = 27,    /**< SSP requested disassociation */
+    WIFI_REASON_NO_SSP_ROAMING_AGREEMENT           = 28,    /**< No SSP roaming agreement */
+    WIFI_REASON_BAD_CIPHER_OR_AKM                  = 29,    /**< Bad cipher or AKM */
+    WIFI_REASON_NOT_AUTHORIZED_THIS_LOCATION       = 30,    /**< Not authorized in this location */
+    WIFI_REASON_SERVICE_CHANGE_PERCLUDES_TS        = 31,    /**< Service change precludes TS */
+    WIFI_REASON_UNSPECIFIED_QOS                    = 32,    /**< Unspecified QoS reason */
+    WIFI_REASON_NOT_ENOUGH_BANDWIDTH               = 33,    /**< Not enough bandwidth */
+    WIFI_REASON_MISSING_ACKS                       = 34,    /**< Missing ACKs */
+    WIFI_REASON_EXCEEDED_TXOP                      = 35,    /**< Exceeded TXOP */
+    WIFI_REASON_STA_LEAVING                        = 36,    /**< Station leaving */
+    WIFI_REASON_END_BA                             = 37,    /**< End of Block Ack (BA) */
+    WIFI_REASON_UNKNOWN_BA                         = 38,    /**< Unknown Block Ack (BA) */
+    WIFI_REASON_TIMEOUT                            = 39,    /**< Timeout */
+    WIFI_REASON_PEER_INITIATED                     = 46,    /**< Peer initiated disassociation */
+    WIFI_REASON_AP_INITIATED                       = 47,    /**< AP initiated disassociation */
+    WIFI_REASON_INVALID_FT_ACTION_FRAME_COUNT      = 48,    /**< Invalid FT action frame count */
+    WIFI_REASON_INVALID_PMKID                      = 49,    /**< Invalid PMKID */
+    WIFI_REASON_INVALID_MDE                        = 50,    /**< Invalid MDE */
+    WIFI_REASON_INVALID_FTE                        = 51,    /**< Invalid FTE */
+    WIFI_REASON_TRANSMISSION_LINK_ESTABLISH_FAILED = 67,    /**< Transmission link establishment failed */
+    WIFI_REASON_ALTERATIVE_CHANNEL_OCCUPIED        = 68,    /**< Alternative channel occupied */
+
+    WIFI_REASON_BEACON_TIMEOUT                     = 200,    /**< Beacon timeout */
+    WIFI_REASON_NO_AP_FOUND                        = 201,    /**< No AP found */
+    WIFI_REASON_AUTH_FAIL                          = 202,    /**< Authentication failed */
+    WIFI_REASON_ASSOC_FAIL                         = 203,    /**< Association failed */
+    WIFI_REASON_HANDSHAKE_TIMEOUT                  = 204,    /**< Handshake timeout */
+    WIFI_REASON_CONNECTION_FAIL                    = 205,    /**< Connection failed */
+    WIFI_REASON_AP_TSF_RESET                       = 206,    /**< AP TSF reset */
+    WIFI_REASON_ROAMING                            = 207,    /**< Roaming */
+    WIFI_REASON_ASSOC_COMEBACK_TIME_TOO_LONG       = 208,    /**< Association comeback time too long */
+    WIFI_REASON_SA_QUERY_TIMEOUT                   = 209,    /**< SA query timeout */
+    WIFI_REASON_NO_AP_FOUND_W_COMPATIBLE_SECURITY  = 210,    /**< No AP found with compatible security */
+    WIFI_REASON_NO_AP_FOUND_IN_AUTHMODE_THRESHOLD  = 211,    /**< No AP found in auth mode threshold */
+    WIFI_REASON_NO_AP_FOUND_IN_RSSI_THRESHOLD      = 212,    /**< No AP found in RSSI threshold */
 } wifi_err_reason_t;
 
+/**
+  * @brief Wi-Fi second channel type
+  */
 typedef enum {
-    WIFI_SECOND_CHAN_NONE = 0,  /**< the channel width is HT20 */
-    WIFI_SECOND_CHAN_ABOVE,     /**< the channel width is HT40 and the secondary channel is above the primary channel */
-    WIFI_SECOND_CHAN_BELOW,     /**< the channel width is HT40 and the secondary channel is below the primary channel */
+    WIFI_SECOND_CHAN_NONE = 0,  /**< The channel width is HT20 */
+    WIFI_SECOND_CHAN_ABOVE,     /**< The channel width is HT40 and the secondary channel is above the primary channel */
+    WIFI_SECOND_CHAN_BELOW,     /**< The channel width is HT40 and the secondary channel is below the primary channel */
 } wifi_second_chan_t;
 
-#define WIFI_ACTIVE_SCAN_MIN_DEFAULT_TIME 0
-#define WIFI_ACTIVE_SCAN_MAX_DEFAULT_TIME 120
-#define WIFI_PASSIVE_SCAN_DEFAULT_TIME 360
-#define WIFI_SCAN_HOME_CHANNEL_DWELL_DEFAULT_TIME 30
+#define WIFI_ACTIVE_SCAN_MIN_DEFAULT_TIME 0             /**< Default minimum active scan time per channel */
+#define WIFI_ACTIVE_SCAN_MAX_DEFAULT_TIME 120           /**< Default maximum active scan time per channel */
+#define WIFI_PASSIVE_SCAN_DEFAULT_TIME 360              /**< Default passive scan time per channel */
+#define WIFI_SCAN_HOME_CHANNEL_DWELL_DEFAULT_TIME 30    /**< Default time spent at home channel between scanning consecutive channels */
 
 #define WIFI_SCAN_PARAMS_DEFAULT_CONFIG() { \
     .scan_time.active.min = WIFI_ACTIVE_SCAN_MIN_DEFAULT_TIME, \
@@ -164,153 +192,199 @@ typedef enum {
     .home_chan_dwell_time = WIFI_SCAN_HOME_CHANNEL_DWELL_DEFAULT_TIME\
 }
 
+/**
+  * @brief Wi-Fi scan type
+  */
 typedef enum {
-    WIFI_SCAN_TYPE_ACTIVE = 0,  /**< active scan */
-    WIFI_SCAN_TYPE_PASSIVE,     /**< passive scan */
+    WIFI_SCAN_TYPE_ACTIVE = 0,  /**< Active scan */
+    WIFI_SCAN_TYPE_PASSIVE,     /**< Passive scan */
 } wifi_scan_type_t;
 
-/** @brief Range of active scan times per channel */
+/**
+  * @brief Range of active scan times per channel
+  */
 typedef struct {
-    uint32_t min;  /**< minimum active scan time per channel, units: millisecond */
-    uint32_t max;  /**< maximum active scan time per channel, units: millisecond, values above 1500ms may
+    uint32_t min;  /**< Minimum active scan time per channel, units: millisecond */
+    uint32_t max;  /**< Maximum active scan time per channel, units: millisecond, values above 1500 ms may
                                           cause station to disconnect from AP and are not recommended.  */
 } wifi_active_scan_time_t;
 
-/** @brief Aggregate of active & passive scan time per channel */
+/**
+  * @brief Aggregate of active & passive scan time per channel
+  */
 typedef struct {
-    wifi_active_scan_time_t active;  /**< active scan time per channel, units: millisecond. */
-    uint32_t passive;                /**< passive scan time per channel, units: millisecond, values above 1500ms may
+    wifi_active_scan_time_t active;  /**< Active scan time per channel, units: millisecond. */
+    uint32_t passive;                /**< Passive scan time per channel, units: millisecond, values above 1500 ms may
                                           cause station to disconnect from AP and are not recommended. */
 } wifi_scan_time_t;
 
+/**
+  * @brief Channel bitmap for setting specific channels to be scanned
+  */
 typedef struct {
     uint16_t ghz_2_channels;     /**< Represents 2.4 GHz channels, that bits can be set as wifi_2g_channel_bit_t shown. */
     uint32_t ghz_5_channels;     /**< Represents 5 GHz channels, that bits can be set as wifi_5g_channel_bit_t shown. */
 } wifi_scan_channel_bitmap_t;
 
-/** @brief Parameters for an SSID scan. */
+/**
+  * @brief Parameters for an SSID scan
+  */
 typedef struct {
     uint8_t *ssid;                                     /**< SSID of AP */
     uint8_t *bssid;                                    /**< MAC address of AP */
-    uint8_t channel;                                   /**< channel, scan the specific channel */
-    bool show_hidden;                                  /**< enable to scan AP whose SSID is hidden */
-    wifi_scan_type_t scan_type;                        /**< scan type, active or passive */
-    wifi_scan_time_t scan_time;                        /**< scan time per channel */
-    uint8_t home_chan_dwell_time;                      /**< time spent at home channel between scanning consecutive channels. */
+    uint8_t channel;                                   /**< Channel, scan the specific channel */
+    bool show_hidden;                                  /**< Enable it to scan AP whose SSID is hidden */
+    wifi_scan_type_t scan_type;                        /**< Scan type, active or passive */
+    wifi_scan_time_t scan_time;                        /**< Scan time per channel */
+    uint8_t home_chan_dwell_time;                      /**< Time spent at home channel between scanning consecutive channels. */
     wifi_scan_channel_bitmap_t channel_bitmap;         /**< Channel bitmap for setting specific channels to be scanned.
                                                             Please note that the 'channel' parameter above needs to be set to 0 to allow scanning by bitmap.
-                                                            Also, note that only allowed channels configured by wifi_country_t can be scaned. */
+                                                            Also, note that only allowed channels configured by wifi_country_t can be scanned. */
 } wifi_scan_config_t;
 
-/** @brief Parameters default scan configurations. */
+/**
+  * @brief Parameters default scan configurations
+  */
 typedef struct {
-    wifi_scan_time_t scan_time;  /**< scan time per channel */
-    uint8_t home_chan_dwell_time;/**< time spent at home channel between scanning consecutive channels.*/
+    wifi_scan_time_t scan_time;  /**< Scan time per channel */
+    uint8_t home_chan_dwell_time;/**< Time spent at home channel between scanning consecutive channels.*/
 } wifi_scan_default_params_t;
 
+/**
+  * @brief Wi-Fi cipher type
+  */
 typedef enum {
-    WIFI_CIPHER_TYPE_NONE = 0,   /**< the cipher type is none */
-    WIFI_CIPHER_TYPE_WEP40,      /**< the cipher type is WEP40 */
-    WIFI_CIPHER_TYPE_WEP104,     /**< the cipher type is WEP104 */
-    WIFI_CIPHER_TYPE_TKIP,       /**< the cipher type is TKIP */
-    WIFI_CIPHER_TYPE_CCMP,       /**< the cipher type is CCMP */
-    WIFI_CIPHER_TYPE_TKIP_CCMP,  /**< the cipher type is TKIP and CCMP */
-    WIFI_CIPHER_TYPE_AES_CMAC128,/**< the cipher type is AES-CMAC-128 */
-    WIFI_CIPHER_TYPE_SMS4,       /**< the cipher type is SMS4 */
-    WIFI_CIPHER_TYPE_GCMP,       /**< the cipher type is GCMP */
-    WIFI_CIPHER_TYPE_GCMP256,    /**< the cipher type is GCMP-256 */
-    WIFI_CIPHER_TYPE_AES_GMAC128,/**< the cipher type is AES-GMAC-128 */
-    WIFI_CIPHER_TYPE_AES_GMAC256,/**< the cipher type is AES-GMAC-256 */
-    WIFI_CIPHER_TYPE_UNKNOWN,    /**< the cipher type is unknown */
+    WIFI_CIPHER_TYPE_NONE = 0,   /**< The cipher type is none */
+    WIFI_CIPHER_TYPE_WEP40,      /**< The cipher type is WEP40 */
+    WIFI_CIPHER_TYPE_WEP104,     /**< The cipher type is WEP104 */
+    WIFI_CIPHER_TYPE_TKIP,       /**< The cipher type is TKIP */
+    WIFI_CIPHER_TYPE_CCMP,       /**< The cipher type is CCMP */
+    WIFI_CIPHER_TYPE_TKIP_CCMP,  /**< The cipher type is TKIP and CCMP */
+    WIFI_CIPHER_TYPE_AES_CMAC128,/**< The cipher type is AES-CMAC-128 */
+    WIFI_CIPHER_TYPE_SMS4,       /**< The cipher type is SMS4 */
+    WIFI_CIPHER_TYPE_GCMP,       /**< The cipher type is GCMP */
+    WIFI_CIPHER_TYPE_GCMP256,    /**< The cipher type is GCMP-256 */
+    WIFI_CIPHER_TYPE_AES_GMAC128,/**< The cipher type is AES-GMAC-128 */
+    WIFI_CIPHER_TYPE_AES_GMAC256,/**< The cipher type is AES-GMAC-256 */
+    WIFI_CIPHER_TYPE_UNKNOWN,    /**< The cipher type is unknown */
 } wifi_cipher_type_t;
 
 /**
-  * @brief WiFi antenna
-  *
+  * @brief Wi-Fi bandwidth type
   */
 typedef enum {
-    WIFI_ANT_ANT0,          /**< WiFi antenna 0 */
-    WIFI_ANT_ANT1,          /**< WiFi antenna 1 */
-    WIFI_ANT_MAX,           /**< Invalid WiFi antenna */
+    WIFI_BW_HT20   = 1,       /**< Bandwidth is HT20      */
+    WIFI_BW20 = WIFI_BW_HT20, /**< Bandwidth is 20 MHz    */
+    WIFI_BW_HT40   = 2,       /**< Bandwidth is HT40      */
+    WIFI_BW40 = WIFI_BW_HT40, /**< Bandwidth is 40 MHz    */
+    WIFI_BW80      = 3,       /**< Bandwidth is 80 MHz    */
+    WIFI_BW160     = 4,       /**< Bandwidth is 160 MHz   */
+    WIFI_BW80_BW80 = 5,       /**< Bandwidth is 80 + 80 MHz */
+} wifi_bandwidth_t;
+
+/**
+  * @brief Wi-Fi antenna
+  */
+typedef enum {
+    WIFI_ANT_ANT0,          /**< Wi-Fi antenna 0 */
+    WIFI_ANT_ANT1,          /**< Wi-Fi antenna 1 */
+    WIFI_ANT_MAX,           /**< Invalid Wi-Fi antenna */
 } wifi_ant_t;
 
-/** @brief Description of a WiFi AP HE Info */
+/**
+  * @brief Description of a Wi-Fi AP HE Info
+  */
 typedef struct {
-    uint8_t bss_color: 6;                 /**< an unsigned integer whose value is the BSS Color of the BSS corresponding to the AP */
-    uint8_t partial_bss_color: 1;         /**< indicate if an AID assignment rule based on the BSS color */
-    uint8_t bss_color_disabled: 1;        /**< indicate if the use of BSS color is disabled */
-    uint8_t bssid_index;                  /**< in M-BSSID set, identifies the nontransmitted BSSID */
+    uint8_t bss_color: 6;                 /**< The BSS Color value associated with the AP's corresponding BSS */
+    uint8_t partial_bss_color: 1;         /**< Indicates whether an AID assignment rule is based on the BSS color */
+    uint8_t bss_color_disabled: 1;        /**< Indicates whether the BSS color usage is disabled */
+    uint8_t bssid_index;                  /**< In a M-BSSID set, identifies the non-transmitted BSSID */
 } wifi_he_ap_info_t;
 
-/** @brief Description of a WiFi AP */
+/**
+  * @brief Description of a Wi-Fi AP
+  */
 typedef struct {
     uint8_t bssid[6];                     /**< MAC address of AP */
     uint8_t ssid[33];                     /**< SSID of AP */
-    uint8_t primary;                      /**< channel of AP */
-    wifi_second_chan_t second;            /**< secondary channel of AP */
-    int8_t  rssi;                         /**< signal strength of AP. Note that in some rare cases where signal strength is very strong, rssi values can be slightly positive */
-    wifi_auth_mode_t authmode;            /**< authmode of AP */
-    wifi_cipher_type_t pairwise_cipher;   /**< pairwise cipher of AP */
-    wifi_cipher_type_t group_cipher;      /**< group cipher of AP */
-    wifi_ant_t ant;                       /**< antenna used to receive beacon from AP */
-    uint32_t phy_11b: 1;                  /**< bit: 0 flag to identify if 11b mode is enabled or not */
-    uint32_t phy_11g: 1;                  /**< bit: 1 flag to identify if 11g mode is enabled or not */
-    uint32_t phy_11n: 1;                  /**< bit: 2 flag to identify if 11n mode is enabled or not */
-    uint32_t phy_lr: 1;                   /**< bit: 3 flag to identify if low rate is enabled or not */
-    uint32_t phy_11a: 1;                  /**< bit: 4 flag to identify if 11ax mode is enabled or not */
-    uint32_t phy_11ac: 1;                 /**< bit: 5 flag to identify if 11ax mode is enabled or not */
-    uint32_t phy_11ax: 1;                 /**< bit: 6 flag to identify if 11ax mode is enabled or not */
-    uint32_t wps: 1;                      /**< bit: 7 flag to identify if WPS is supported or not */
-    uint32_t ftm_responder: 1;            /**< bit: 8 flag to identify if FTM is supported in responder mode */
-    uint32_t ftm_initiator: 1;            /**< bit: 9 flag to identify if FTM is supported in initiator mode */
-    uint32_t reserved: 22;                /**< bit: 10..31 reserved */
-    wifi_country_t country;               /**< country information of AP */
+    uint8_t primary;                      /**< Channel of AP */
+    wifi_second_chan_t second;            /**< Secondary channel of AP */
+    int8_t  rssi;                         /**< Signal strength of AP. Note that in some rare cases where signal strength is very strong, RSSI values can be slightly positive */
+    wifi_auth_mode_t authmode;            /**< Auth mode of AP */
+    wifi_cipher_type_t pairwise_cipher;   /**< Pairwise cipher of AP */
+    wifi_cipher_type_t group_cipher;      /**< Group cipher of AP */
+    wifi_ant_t ant;                       /**< Antenna used to receive beacon from AP */
+    uint32_t phy_11b: 1;                  /**< Bit: 0 flag to identify if 11b mode is enabled or not */
+    uint32_t phy_11g: 1;                  /**< Bit: 1 flag to identify if 11g mode is enabled or not */
+    uint32_t phy_11n: 1;                  /**< Bit: 2 flag to identify if 11n mode is enabled or not */
+    uint32_t phy_lr: 1;                   /**< Bit: 3 flag to identify if low rate is enabled or not */
+    uint32_t phy_11a: 1;                  /**< Bit: 4 flag to identify if 11ax mode is enabled or not */
+    uint32_t phy_11ac: 1;                 /**< Bit: 5 flag to identify if 11ax mode is enabled or not */
+    uint32_t phy_11ax: 1;                 /**< Bit: 6 flag to identify if 11ax mode is enabled or not */
+    uint32_t wps: 1;                      /**< Bit: 7 flag to identify if WPS is supported or not */
+    uint32_t ftm_responder: 1;            /**< Bit: 8 flag to identify if FTM is supported in responder mode */
+    uint32_t ftm_initiator: 1;            /**< Bit: 9 flag to identify if FTM is supported in initiator mode */
+    uint32_t reserved: 22;                /**< Bit: 10..31 reserved */
+    wifi_country_t country;               /**< Country information of AP */
     wifi_he_ap_info_t he_ap;              /**< HE AP info */
-    uint8_t bandwidth;                    /**< For either 20 MHz or 40 MHz operation, the Channel Width field is set to 0.
-                                               For AP 80 MHz this value is set to 1. For AP 160MHz sets this value is set to 2.
-                                               For AP 80+80MHz this value is set to 3*/
-    uint8_t vht_ch_freq1;                 /**< this fields are used only AP bandwidth is 80 and 160 MHz, to transmit the center channel
-                                               frequency of the BSS. For AP bandwidth is 80+80MHz, it is the center channel frequency
+    wifi_bandwidth_t bandwidth;           /**< Bandwidth of AP */
+    uint8_t vht_ch_freq1;                 /**< This fields are used only AP bandwidth is 80 and 160 MHz, to transmit the center channel
+                                               frequency of the BSS. For AP bandwidth is 80 + 80 MHz, it is the center channel frequency
                                                of the lower frequency segment.*/
-    uint8_t vht_ch_freq2;                 /**< this fields are used only AP bandwidth is 80+80MHz, and is used to transmit the center
+    uint8_t vht_ch_freq2;                 /**< this fields are used only AP bandwidth is 80 + 80 MHz, and is used to transmit the center
                                                channel frequency of the second segment. */
 } wifi_ap_record_t;
 
+/**
+  * @brief Wi-Fi scan method
+  */
 typedef enum {
     WIFI_FAST_SCAN = 0,                   /**< Do fast scan, scan will end after find SSID match AP */
     WIFI_ALL_CHANNEL_SCAN,                /**< All channel scan, scan will end after scan all the channel */
 } wifi_scan_method_t;
 
+/**
+  * @brief Wi-Fi sort AP method
+  */
 typedef enum {
     WIFI_CONNECT_AP_BY_SIGNAL = 0,        /**< Sort match AP in scan list by RSSI */
     WIFI_CONNECT_AP_BY_SECURITY,          /**< Sort match AP in scan list by security mode */
 } wifi_sort_method_t;
 
-/** @brief Structure describing parameters for a WiFi fast scan */
+/**
+  * @brief Structure describing parameters for a Wi-Fi fast scan
+  */
 typedef struct {
-    int8_t              rssi;               /**< The minimum rssi to accept in the fast scan mode */
-    wifi_auth_mode_t    authmode;           /**< The weakest authmode to accept in the fast scan mode
-                                               Note: In case this value is not set and password is set as per WPA2 standards(password len >= 8), it will be defaulted to WPA2 and device won't connect to deprecated WEP/WPA networks. Please set authmode threshold as WIFI_AUTH_WEP/WIFI_AUTH_WPA_PSK to connect to WEP/WPA networks */
+    int8_t              rssi;             /**< The minimum rssi to accept in the fast scan mode */
+    wifi_auth_mode_t    authmode;         /**< The weakest auth mode to accept in the fast scan mode
+                                               Note: In case this value is not set and password is set as per WPA2 standards(password len >= 8), it will be defaulted to WPA2 and device won't connect to deprecated WEP/WPA networks. Please set auth mode threshold as WIFI_AUTH_WEP/WIFI_AUTH_WPA_PSK to connect to WEP/WPA networks */
     uint8_t             rssi_5g_adjustment; /**< The RSSI value of the 5G AP is within the rssi_5g_adjustment range compared to the 2G AP, the 5G AP will be given priority for connection. */
 } wifi_scan_threshold_t;
 
+/**
+  * @brief Wi-Fi power save type
+  */
 typedef enum {
     WIFI_PS_NONE,        /**< No power save */
     WIFI_PS_MIN_MODEM,   /**< Minimum modem power saving. In this mode, station wakes up to receive beacon every DTIM period */
     WIFI_PS_MAX_MODEM,   /**< Maximum modem power saving. In this mode, interval to receive beacons is determined by the listen_interval parameter in wifi_sta_config_t */
 } wifi_ps_type_t;
 
-/** Argument structure for WiFi band */
+/**
+  * @brief Argument structure for Wi-Fi band
+  */
 typedef enum {
-    WIFI_BAND_2G = 1,                   /* Band is 2.4G */
-    WIFI_BAND_5G = 2,                   /* Band is 5G */
+    WIFI_BAND_2G = 1,                   /**< Band is 2.4 GHz */
+    WIFI_BAND_5G = 2,                   /**< Band is 5 GHz */
 } wifi_band_t;
 
-/** Argument structure for WiFi band mode */
+/**
+  * @brief Argument structure for Wi-Fi band mode
+  */
 typedef enum {
-    WIFI_BAND_MODE_2G_ONLY = 1,         /* WiFi band mode is 2.4G only */
-    WIFI_BAND_MODE_5G_ONLY = 2,         /* WiFi band mode is 5G only */
-    WIFI_BAND_MODE_AUTO = 3,            /* WiFi band mode is 2.4G + 5G */
+    WIFI_BAND_MODE_2G_ONLY = 1,         /**< Wi-Fi band mode is 2.4 GHz only */
+    WIFI_BAND_MODE_5G_ONLY = 2,         /**< Wi-Fi band mode is 5 GHz only */
+    WIFI_BAND_MODE_AUTO = 3,            /**< Wi-Fi band mode is 2.4 GHz + 5 GHz */
 } wifi_band_mode_t;
 
 #ifndef BIT
@@ -331,91 +405,89 @@ typedef enum {
 
 /** Argument structure for 2.4G channels */
 typedef enum {
-    WIFI_CHANNEL_1 = BIT(1),   /**< wifi channel 1 */
-    WIFI_CHANNEL_2 = BIT(2),   /**< wifi channel 2 */
-    WIFI_CHANNEL_3 = BIT(3),   /**< wifi channel 3 */
-    WIFI_CHANNEL_4 = BIT(4),   /**< wifi channel 4 */
-    WIFI_CHANNEL_5 = BIT(5),   /**< wifi channel 5 */
-    WIFI_CHANNEL_6 = BIT(6),   /**< wifi channel 6 */
-    WIFI_CHANNEL_7 = BIT(7),   /**< wifi channel 7 */
-    WIFI_CHANNEL_8 = BIT(8),   /**< wifi channel 8 */
-    WIFI_CHANNEL_9 = BIT(9),   /**< wifi channel 9 */
-    WIFI_CHANNEL_10 = BIT(10), /**< wifi channel 10 */
-    WIFI_CHANNEL_11 = BIT(11), /**< wifi channel 11 */
-    WIFI_CHANNEL_12 = BIT(12), /**< wifi channel 12 */
-    WIFI_CHANNEL_13 = BIT(13), /**< wifi channel 13 */
-    WIFI_CHANNEL_14 = BIT(14), /**< wifi channel 14 */
+    WIFI_CHANNEL_1 = BIT(1),   /**< Wi-Fi channel 1 */
+    WIFI_CHANNEL_2 = BIT(2),   /**< Wi-Fi channel 2 */
+    WIFI_CHANNEL_3 = BIT(3),   /**< Wi-Fi channel 3 */
+    WIFI_CHANNEL_4 = BIT(4),   /**< Wi-Fi channel 4 */
+    WIFI_CHANNEL_5 = BIT(5),   /**< Wi-Fi channel 5 */
+    WIFI_CHANNEL_6 = BIT(6),   /**< Wi-Fi channel 6 */
+    WIFI_CHANNEL_7 = BIT(7),   /**< Wi-Fi channel 7 */
+    WIFI_CHANNEL_8 = BIT(8),   /**< Wi-Fi channel 8 */
+    WIFI_CHANNEL_9 = BIT(9),   /**< Wi-Fi channel 9 */
+    WIFI_CHANNEL_10 = BIT(10), /**< Wi-Fi channel 10 */
+    WIFI_CHANNEL_11 = BIT(11), /**< Wi-Fi channel 11 */
+    WIFI_CHANNEL_12 = BIT(12), /**< Wi-Fi channel 12 */
+    WIFI_CHANNEL_13 = BIT(13), /**< Wi-Fi channel 13 */
+    WIFI_CHANNEL_14 = BIT(14), /**< Wi-Fi channel 14 */
 } wifi_2g_channel_bit_t;
 
 /** Argument structure for 5G channels */
 typedef enum {
-    WIFI_CHANNEL_36 = BIT(1),   /**< wifi channel 36 */
-    WIFI_CHANNEL_40 = BIT(2),   /**< wifi channel 40 */
-    WIFI_CHANNEL_44 = BIT(3),   /**< wifi channel 44 */
-    WIFI_CHANNEL_48 = BIT(4),   /**< wifi channel 48 */
-    WIFI_CHANNEL_52 = BIT(5),   /**< wifi channel 52 */
-    WIFI_CHANNEL_56 = BIT(6),   /**< wifi channel 56 */
-    WIFI_CHANNEL_60 = BIT(7),   /**< wifi channel 60 */
-    WIFI_CHANNEL_64 = BIT(8),   /**< wifi channel 64 */
-    WIFI_CHANNEL_100 = BIT(9),  /**< wifi channel 100 */
-    WIFI_CHANNEL_104 = BIT(10), /**< wifi channel 104 */
-    WIFI_CHANNEL_108 = BIT(11), /**< wifi channel 108 */
-    WIFI_CHANNEL_112 = BIT(12), /**< wifi channel 112 */
-    WIFI_CHANNEL_116 = BIT(13), /**< wifi channel 116 */
-    WIFI_CHANNEL_120 = BIT(14), /**< wifi channel 120 */
-    WIFI_CHANNEL_124 = BIT(15), /**< wifi channel 124 */
-    WIFI_CHANNEL_128 = BIT(16), /**< wifi channel 128 */
-    WIFI_CHANNEL_132 = BIT(17), /**< wifi channel 132 */
-    WIFI_CHANNEL_136 = BIT(18), /**< wifi channel 136 */
-    WIFI_CHANNEL_140 = BIT(19), /**< wifi channel 140 */
-    WIFI_CHANNEL_144 = BIT(20), /**< wifi channel 144 */
-    WIFI_CHANNEL_149 = BIT(21), /**< wifi channel 149 */
-    WIFI_CHANNEL_153 = BIT(22), /**< wifi channel 153 */
-    WIFI_CHANNEL_157 = BIT(23), /**< wifi channel 157 */
-    WIFI_CHANNEL_161 = BIT(24), /**< wifi channel 161 */
-    WIFI_CHANNEL_165 = BIT(25), /**< wifi channel 165 */
-    WIFI_CHANNEL_169 = BIT(26), /**< wifi channel 169 */
-    WIFI_CHANNEL_173 = BIT(27), /**< wifi channel 173 */
-    WIFI_CHANNEL_177 = BIT(28), /**< wifi channel 177 */
+    WIFI_CHANNEL_36 = BIT(1),   /**< Wi-Fi channel 36 */
+    WIFI_CHANNEL_40 = BIT(2),   /**< Wi-Fi channel 40 */
+    WIFI_CHANNEL_44 = BIT(3),   /**< Wi-Fi channel 44 */
+    WIFI_CHANNEL_48 = BIT(4),   /**< Wi-Fi channel 48 */
+    WIFI_CHANNEL_52 = BIT(5),   /**< Wi-Fi channel 52 */
+    WIFI_CHANNEL_56 = BIT(6),   /**< Wi-Fi channel 56 */
+    WIFI_CHANNEL_60 = BIT(7),   /**< Wi-Fi channel 60 */
+    WIFI_CHANNEL_64 = BIT(8),   /**< Wi-Fi channel 64 */
+    WIFI_CHANNEL_100 = BIT(9),  /**< Wi-Fi channel 100 */
+    WIFI_CHANNEL_104 = BIT(10), /**< Wi-Fi channel 104 */
+    WIFI_CHANNEL_108 = BIT(11), /**< Wi-Fi channel 108 */
+    WIFI_CHANNEL_112 = BIT(12), /**< Wi-Fi channel 112 */
+    WIFI_CHANNEL_116 = BIT(13), /**< Wi-Fi channel 116 */
+    WIFI_CHANNEL_120 = BIT(14), /**< Wi-Fi channel 120 */
+    WIFI_CHANNEL_124 = BIT(15), /**< Wi-Fi channel 124 */
+    WIFI_CHANNEL_128 = BIT(16), /**< Wi-Fi channel 128 */
+    WIFI_CHANNEL_132 = BIT(17), /**< Wi-Fi channel 132 */
+    WIFI_CHANNEL_136 = BIT(18), /**< Wi-Fi channel 136 */
+    WIFI_CHANNEL_140 = BIT(19), /**< Wi-Fi channel 140 */
+    WIFI_CHANNEL_144 = BIT(20), /**< Wi-Fi channel 144 */
+    WIFI_CHANNEL_149 = BIT(21), /**< Wi-Fi channel 149 */
+    WIFI_CHANNEL_153 = BIT(22), /**< Wi-Fi channel 153 */
+    WIFI_CHANNEL_157 = BIT(23), /**< Wi-Fi channel 157 */
+    WIFI_CHANNEL_161 = BIT(24), /**< Wi-Fi channel 161 */
+    WIFI_CHANNEL_165 = BIT(25), /**< Wi-Fi channel 165 */
+    WIFI_CHANNEL_169 = BIT(26), /**< Wi-Fi channel 169 */
+    WIFI_CHANNEL_173 = BIT(27), /**< Wi-Fi channel 173 */
+    WIFI_CHANNEL_177 = BIT(28), /**< Wi-Fi channel 177 */
 } wifi_5g_channel_bit_t;
 
-#define WIFI_PROTOCOL_11B         0x1
-#define WIFI_PROTOCOL_11G         0x2
-#define WIFI_PROTOCOL_11N         0x4
-#define WIFI_PROTOCOL_LR          0x8
-#define WIFI_PROTOCOL_11A         0x10
-#define WIFI_PROTOCOL_11AC        0x20
-#define WIFI_PROTOCOL_11AX        0x40
+#define WIFI_PROTOCOL_11B         0x1     /**< 802.11b protocol */
+#define WIFI_PROTOCOL_11G         0x2     /**< 802.11g protocol */
+#define WIFI_PROTOCOL_11N         0x4     /**< 802.11n protocol */
+#define WIFI_PROTOCOL_LR          0x8     /**< Low Rate protocol */
+#define WIFI_PROTOCOL_11A         0x10    /**< 802.11a protocol */
+#define WIFI_PROTOCOL_11AC        0x20    /**< 802.11ac protocol */
+#define WIFI_PROTOCOL_11AX        0x40    /**< 802.11ax protocol */
 
-/** @brief Description of a WiFi protocols */
+/**
+  * @brief Description of a Wi-Fi protocols
+  */
 typedef struct {
     uint16_t ghz_2g;            /**< Represents 2.4 GHz protocol, support 802.11b or 802.11g or 802.11n or 802.11ax or LR mode */
     uint16_t ghz_5g;            /**< Represents 5 GHz protocol, support 802.11a or 802.11n or 802.11ac or 802.11ax */
 } wifi_protocols_t;
 
-typedef enum {
-    WIFI_BW_HT20   = 1,       /* Bandwidth is HT20      */
-    WIFI_BW20 = WIFI_BW_HT20, /* Bandwidth is 20 MHz    */
-    WIFI_BW_HT40   = 2,       /* Bandwidth is HT40      */
-    WIFI_BW40 = WIFI_BW_HT40, /* Bandwidth is 40 MHz    */
-    WIFI_BW80      = 3,       /* Bandwidth is 80 MHz    */
-    WIFI_BW160     = 4,       /* Bandwidth is 160 MHz   */
-    WIFI_BW80_BW80 = 5,       /* Bandwidth is 80+80 MHz */
-} wifi_bandwidth_t;
-
-/** @brief Description of a WiFi band bandwidths */
+/**
+  * @brief Description of a Wi-Fi band bandwidths
+  */
 typedef struct {
-    wifi_bandwidth_t ghz_2g;       /* Represents 2.4 GHz bandwidth */
-    wifi_bandwidth_t ghz_5g;       /* Represents 5 GHz bandwidth */
+    wifi_bandwidth_t ghz_2g;       /**< Represents 2.4 GHz bandwidth */
+    wifi_bandwidth_t ghz_5g;       /**< Represents 5 GHz bandwidth */
 } wifi_bandwidths_t;
 
-/** Configuration structure for Protected Management Frame */
+/**
+  * @brief Configuration structure for Protected Management Frame
+  */
 typedef struct {
     bool capable;            /**< Deprecated variable. Device will always connect in PMF mode if other device also advertises PMF capability. */
     bool required;           /**< Advertises that Protected Management Frame is required. Device will not associate to non-PMF capable devices. */
 } wifi_pmf_config_t;
 
-/** Configuration for SAE PWE derivation */
+/**
+  * @brief Configuration for SAE PWE derivation
+  */
 typedef enum {
     WPA3_SAE_PWE_UNSPECIFIED,
     WPA3_SAE_PWE_HUNT_AND_PECK,
@@ -423,14 +495,18 @@ typedef enum {
     WPA3_SAE_PWE_BOTH,
 } wifi_sae_pwe_method_t;
 
-/** Configuration for SAE-PK  */
+/**
+  * @brief Configuration for SAE-PK
+  */
 typedef enum {
     WPA3_SAE_PK_MODE_AUTOMATIC = 0,
     WPA3_SAE_PK_MODE_ONLY = 1,
     WPA3_SAE_PK_MODE_DISABLED = 2,
 } wifi_sae_pk_mode_t;
 
-/** @brief Soft-AP configuration settings for the device */
+/**
+  * @brief Soft-AP configuration settings for the device
+  */
 typedef struct {
     uint8_t ssid[32];           /**< SSID of soft-AP. If ssid_len field is 0, this must be a Null terminated string. Otherwise, length is set according to ssid_len. */
     uint8_t password[64];       /**< Password of soft-AP. */
@@ -440,25 +516,28 @@ typedef struct {
     uint8_t ssid_hidden;        /**< Broadcast SSID or not, default 0, broadcast the SSID */
     uint8_t max_connection;     /**< Max number of stations allowed to connect in */
     uint16_t beacon_interval;   /**< Beacon interval which should be multiples of 100. Unit: TU(time unit, 1 TU = 1024 us). Range: 100 ~ 60000. Default value: 100 */
-    uint8_t csa_count;          /**< Channel Switch Announcement Count. Notify the station that the channel will switch after the csa_count beacon intervals. Default value: 3 */
-    uint8_t dtim_period;        /**< Dtim period of soft-AP. Default value: 2 */
+    uint8_t csa_count;          /**< Channel Switch Announcement Count. Notify the station that the channel will switch after the csa_count beacon intervals. Range: 1 ~ 30. Default value: 3 */
+    uint8_t dtim_period;        /**< Dtim period of soft-AP. Range: 1 ~ 10. Default value: 1 */
     wifi_cipher_type_t pairwise_cipher;   /**< Pairwise cipher of SoftAP, group cipher will be derived using this. Cipher values are valid starting from WIFI_CIPHER_TYPE_TKIP, enum values before that will be considered as invalid and default cipher suites(TKIP+CCMP) will be used. Valid cipher suites in softAP mode are WIFI_CIPHER_TYPE_TKIP, WIFI_CIPHER_TYPE_CCMP and WIFI_CIPHER_TYPE_TKIP_CCMP. */
     bool ftm_responder;         /**< Enable FTM Responder mode */
     wifi_pmf_config_t pmf_cfg;  /**< Configuration for Protected Management Frame */
     wifi_sae_pwe_method_t sae_pwe_h2e;  /**< Configuration for SAE PWE derivation method */
 } wifi_ap_config_t;
 
-#define SAE_H2E_IDENTIFIER_LEN 32
-/** @brief STA configuration settings for the device */
+#define SAE_H2E_IDENTIFIER_LEN 32    /**< Length of the password identifier for H2E */
+
+/**
+  * @brief STA configuration settings for the device
+  */
 typedef struct {
     uint8_t ssid[32];                         /**< SSID of target AP. */
     uint8_t password[64];                     /**< Password of target AP. */
-    wifi_scan_method_t scan_method;           /**< do all channel scan or fast scan */
-    bool bssid_set;                           /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
+    wifi_scan_method_t scan_method;           /**< Do all channel scan or fast scan */
+    bool bssid_set;                           /**< Whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
     uint8_t bssid[6];                         /**< MAC address of target AP*/
-    uint8_t channel;                          /**< channel of target AP. For 2.4G AP, set to 1~13 to scan starting from the specified channel before connecting to AP. For 5G AP, set to 36~177 (36, 40, 44 ... 177) to scan starting from the specified channel before connecting to AP. If the channel of AP is unknown, set it to 0.*/
+    uint8_t channel;                          /**< Channel of target AP. For 2.4G AP, set to 1~13 to scan starting from the specified channel before connecting to AP. For 5G AP, set to 36~177 (36, 40, 44 ... 177) to scan starting from the specified channel before connecting to AP. If the channel of AP is unknown, set it to 0.*/
     uint16_t listen_interval;                 /**< Listen interval for ESP32 station to receive beacon when WIFI_PS_MAX_MODEM is set. Units: AP beacon intervals. Defaults to 3 if set to 0. */
-    wifi_sort_method_t sort_method;           /**< sort the connect AP in the list by rssi or security mode */
+    wifi_sort_method_t sort_method;           /**< Sort the connect AP in the list by rssi or security mode */
     wifi_scan_threshold_t  threshold;         /**< When scan_threshold is set, only APs which have an auth mode that is more secure than the selected auth mode and a signal stronger than the minimum RSSI will be used. */
     wifi_pmf_config_t pmf_cfg;                /**< Configuration for Protected Management Frame. Will be advertised in RSN Capabilities in RSN IE. */
     uint32_t rm_enabled: 1;                   /**< Whether Radio Measurements are enabled for the connection */
@@ -486,7 +565,6 @@ typedef struct {
 
 /**
   * @brief NAN Discovery start configuration
-  *
   */
 typedef struct {
     uint8_t op_channel;    /**< NAN Discovery operating channel */
@@ -495,36 +573,42 @@ typedef struct {
     uint16_t warm_up_sec;  /**< Warm up time before assuming NAN Anchor Master role */
 } wifi_nan_config_t;
 
-/** @brief Configuration data for device's AP or STA or NAN.
- *
- * The usage of this union (for ap, sta or nan configuration) is determined by the accompanying
- * interface argument passed to esp_wifi_set_config() or esp_wifi_get_config()
- *
- */
+/**
+  * @brief Configuration data for device's AP or STA or NAN.
+  *
+  * The usage of this union (for ap, sta or nan configuration) is determined by the accompanying
+  * interface argument passed to esp_wifi_set_config() or esp_wifi_get_config()
+  *
+  */
 typedef union {
-    wifi_ap_config_t  ap;  /**< configuration of AP */
-    wifi_sta_config_t sta; /**< configuration of STA */
-    wifi_nan_config_t nan; /**< configuration of NAN */
+    wifi_ap_config_t  ap;  /**< Configuration of AP */
+    wifi_sta_config_t sta; /**< Configuration of STA */
+    wifi_nan_config_t nan; /**< Configuration of NAN */
 } wifi_config_t;
 
-/** @brief Description of STA associated with AP */
+/**
+  * @brief Description of STA associated with AP
+  */
 typedef struct {
-    uint8_t mac[6];          /**< mac address */
-    int8_t  rssi;            /**< current average rssi of sta connected */
-    uint32_t phy_11b: 1;     /**< bit: 0 flag to identify if 11b mode is enabled or not */
-    uint32_t phy_11g: 1;     /**< bit: 1 flag to identify if 11g mode is enabled or not */
-    uint32_t phy_11n: 1;     /**< bit: 2 flag to identify if 11n mode is enabled or not */
-    uint32_t phy_lr: 1;      /**< bit: 3 flag to identify if low rate is enabled or not */
-    uint32_t phy_11a: 1;     /**< bit: 4 flag to identify if 11ax mode is enabled or not */
-    uint32_t phy_11ac: 1;    /**< bit: 5 flag to identify if 11ax mode is enabled or not */
-    uint32_t phy_11ax: 1;    /**< bit: 6 flag to identify if 11ax mode is enabled or not */
-    uint32_t is_mesh_child: 1; /**< bit: 7 flag to identify mesh child */
-    uint32_t reserved: 24;   /**< bit: 8..31 reserved */
+    uint8_t mac[6];          /**< MAC address */
+    int8_t  rssi;            /**< Current average rssi of sta connected */
+    uint32_t phy_11b: 1;     /**< Bit: 0 flag to identify if 11b mode is enabled or not */
+    uint32_t phy_11g: 1;     /**< Bit: 1 flag to identify if 11g mode is enabled or not */
+    uint32_t phy_11n: 1;     /**< Bit: 2 flag to identify if 11n mode is enabled or not */
+    uint32_t phy_lr: 1;      /**< Bit: 3 flag to identify if low rate is enabled or not */
+    uint32_t phy_11a: 1;     /**< Bit: 4 flag to identify if 11ax mode is enabled or not */
+    uint32_t phy_11ac: 1;    /**< Bit: 5 flag to identify if 11ax mode is enabled or not */
+    uint32_t phy_11ax: 1;    /**< Bit: 6 flag to identify if 11ax mode is enabled or not */
+    uint32_t is_mesh_child: 1; /**< Bit: 7 flag to identify mesh child */
+    uint32_t reserved: 24;   /**< Bit: 8..31 reserved */
 } wifi_sta_info_t;
 
+/**
+  * @brief Wi-Fi storage type
+  */
 typedef enum {
-    WIFI_STORAGE_FLASH,  /**< all configuration will store in both memory and flash */
-    WIFI_STORAGE_RAM,    /**< all configuration will only store in the memory */
+    WIFI_STORAGE_FLASH,  /**< All configuration will store in both memory and flash */
+    WIFI_STORAGE_RAM,    /**< All configuration will only store in the memory */
 } wifi_storage_t;
 
 /**
@@ -533,11 +617,11 @@ typedef enum {
   * Determines the frame type that the IE will be associated with.
   */
 typedef enum {
-    WIFI_VND_IE_TYPE_BEACON,
-    WIFI_VND_IE_TYPE_PROBE_REQ,
-    WIFI_VND_IE_TYPE_PROBE_RESP,
-    WIFI_VND_IE_TYPE_ASSOC_REQ,
-    WIFI_VND_IE_TYPE_ASSOC_RESP,
+    WIFI_VND_IE_TYPE_BEACON,        /**< Beacon frame */
+    WIFI_VND_IE_TYPE_PROBE_REQ,     /**< Probe request frame */
+    WIFI_VND_IE_TYPE_PROBE_RESP,    /**< Probe response frame */
+    WIFI_VND_IE_TYPE_ASSOC_REQ,     /**< Association request frame */
+    WIFI_VND_IE_TYPE_ASSOC_RESP,    /**< Association response frame */
 } wifi_vendor_ie_type_t;
 
 /**
@@ -546,14 +630,14 @@ typedef enum {
   * Each IE type can have up to two associated vendor ID elements.
   */
 typedef enum {
-    WIFI_VND_IE_ID_0,
-    WIFI_VND_IE_ID_1,
+    WIFI_VND_IE_ID_0,    /**< Vendor ID element 0 */
+    WIFI_VND_IE_ID_1,    /**< Vendor ID element 1 */
 } wifi_vendor_ie_id_t;
 
-#define WIFI_VENDOR_IE_ELEMENT_ID 0xDD
+#define WIFI_VENDOR_IE_ELEMENT_ID 0xDD    /**< Vendor Information Element ID */
 
 /**
-  * @brief     Operation Phymode
+  * @brief     Operation PHY mode
   */
 typedef enum {
     WIFI_PHY_MODE_LR,   /**< PHY mode for Low Rate */
@@ -567,10 +651,10 @@ typedef enum {
 } wifi_phy_mode_t;
 
 /**
- * @brief Vendor Information Element header
- *
- * The first bytes of the Information Element will match this header. Payload follows.
- */
+  * @brief Vendor Information Element header
+  *
+  * The first bytes of the Information Element will match this header. Payload follows.
+  */
 typedef struct {
     uint8_t element_id;      /**< Should be set to WIFI_VENDOR_IE_ELEMENT_ID (0xDD) */
     uint8_t length;          /**< Length of all bytes in the element data following this field. Minimum 4. */
@@ -592,34 +676,36 @@ typedef enum {
     WIFI_PKT_MISC,  /**< Other type, such as MIMO etc. 'buf' argument is wifi_promiscuous_pkt_t but the payload is zero length. */
 } wifi_promiscuous_pkt_type_t;
 
-#define WIFI_PROMIS_FILTER_MASK_ALL         (0xFFFFFFFF)  /**< filter all packets */
-#define WIFI_PROMIS_FILTER_MASK_MGMT        (1)           /**< filter the packets with type of WIFI_PKT_MGMT */
-#define WIFI_PROMIS_FILTER_MASK_CTRL        (1<<1)        /**< filter the packets with type of WIFI_PKT_CTRL */
-#define WIFI_PROMIS_FILTER_MASK_DATA        (1<<2)        /**< filter the packets with type of WIFI_PKT_DATA */
-#define WIFI_PROMIS_FILTER_MASK_MISC        (1<<3)        /**< filter the packets with type of WIFI_PKT_MISC */
-#define WIFI_PROMIS_FILTER_MASK_DATA_MPDU   (1<<4)        /**< filter the MPDU which is a kind of WIFI_PKT_DATA */
-#define WIFI_PROMIS_FILTER_MASK_DATA_AMPDU  (1<<5)        /**< filter the AMPDU which is a kind of WIFI_PKT_DATA */
-#define WIFI_PROMIS_FILTER_MASK_FCSFAIL     (1<<6)        /**< filter the FCS failed packets, do not open it in general */
-
-#define WIFI_PROMIS_CTRL_FILTER_MASK_ALL         (0xFF800000)  /**< filter all control packets */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_WRAPPER     (1<<23)       /**< filter the control packets with subtype of Control Wrapper */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_BAR         (1<<24)       /**< filter the control packets with subtype of Block Ack Request */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_BA          (1<<25)       /**< filter the control packets with subtype of Block Ack */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_PSPOLL      (1<<26)       /**< filter the control packets with subtype of PS-Poll */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_RTS         (1<<27)       /**< filter the control packets with subtype of RTS */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_CTS         (1<<28)       /**< filter the control packets with subtype of CTS */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_ACK         (1<<29)       /**< filter the control packets with subtype of ACK */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_CFEND       (1<<30)       /**< filter the control packets with subtype of CF-END */
-#define WIFI_PROMIS_CTRL_FILTER_MASK_CFENDACK    (1<<31)       /**< filter the control packets with subtype of CF-END+CF-ACK */
-
-/** @brief Mask for filtering different packet types in promiscuous mode. */
+#define WIFI_PROMIS_FILTER_MASK_ALL         (0xFFFFFFFF)  /**< Filter all packets */
+#define WIFI_PROMIS_FILTER_MASK_MGMT        (1)           /**< Filter the packets with type of WIFI_PKT_MGMT */
+#define WIFI_PROMIS_FILTER_MASK_CTRL        (1<<1)        /**< Filter the packets with type of WIFI_PKT_CTRL */
+#define WIFI_PROMIS_FILTER_MASK_DATA        (1<<2)        /**< Filter the packets with type of WIFI_PKT_DATA */
+#define WIFI_PROMIS_FILTER_MASK_MISC        (1<<3)        /**< Filter the packets with type of WIFI_PKT_MISC */
+#define WIFI_PROMIS_FILTER_MASK_DATA_MPDU   (1<<4)        /**< Filter the MPDU which is a kind of WIFI_PKT_DATA */
+#define WIFI_PROMIS_FILTER_MASK_DATA_AMPDU  (1<<5)        /**< Filter the AMPDU which is a kind of WIFI_PKT_DATA */
+#define WIFI_PROMIS_FILTER_MASK_FCSFAIL     (1<<6)        /**< Filter the FCS failed packets, do not open it in general */
+
+#define WIFI_PROMIS_CTRL_FILTER_MASK_ALL         (0xFF800000)  /**< Filter all control packets */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_WRAPPER     (1<<23)       /**< Filter the control packets with subtype of Control Wrapper */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_BAR         (1<<24)       /**< Filter the control packets with subtype of Block Ack Request */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_BA          (1<<25)       /**< Filter the control packets with subtype of Block Ack */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_PSPOLL      (1<<26)       /**< Filter the control packets with subtype of PS-Poll */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_RTS         (1<<27)       /**< Filter the control packets with subtype of RTS */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_CTS         (1<<28)       /**< Filter the control packets with subtype of CTS */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_ACK         (1<<29)       /**< Filter the control packets with subtype of ACK */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_CFEND       (1<<30)       /**< Filter the control packets with subtype of CF-END */
+#define WIFI_PROMIS_CTRL_FILTER_MASK_CFENDACK    (1<<31)       /**< Filter the control packets with subtype of CF-END+CF-ACK */
+
+/**
+  * @brief Mask for filtering different packet types in promiscuous mode
+  */
 typedef struct {
     uint32_t filter_mask; /**< OR of one or more filter values WIFI_PROMIS_FILTER_* */
 } wifi_promiscuous_filter_t;
 
-#define WIFI_EVENT_MASK_ALL                 (0xFFFFFFFF)  /**< mask all WiFi events */
-#define WIFI_EVENT_MASK_NONE                (0)           /**< mask none of the WiFi events */
-#define WIFI_EVENT_MASK_AP_PROBEREQRECVED   (BIT(0))      /**< mask SYSTEM_EVENT_AP_PROBEREQRECVED event */
+#define WIFI_EVENT_MASK_ALL                 (0xFFFFFFFF)  /**< Mask all Wi-Fi events */
+#define WIFI_EVENT_MASK_NONE                (0)           /**< Mask none of the Wi-Fi events */
+#define WIFI_EVENT_MASK_AP_PROBEREQRECVED   (BIT(0))      /**< Mask SYSTEM_EVENT_AP_PROBEREQRECVED event */
 
 /**
   * @brief CSI data type
@@ -628,7 +714,7 @@ typedef struct {
 typedef struct wifi_csi_info_t wifi_csi_info_t;
 
 /**
-  * @brief WiFi GPIO configuration for antenna selection
+  * @brief Wi-Fi GPIO configuration for antenna selection
   *
   */
 typedef struct {
@@ -637,7 +723,7 @@ typedef struct {
 } wifi_ant_gpio_t;
 
 /**
-  * @brief WiFi GPIOs configuration for antenna selection
+  * @brief Wi-Fi GPIOs configuration for antenna selection
   *
   */
 typedef struct {
@@ -645,24 +731,24 @@ typedef struct {
 } wifi_ant_gpio_config_t;
 
 /**
-  * @brief WiFi antenna mode
+  * @brief Wi-Fi antenna mode
   *
   */
 typedef enum {
-    WIFI_ANT_MODE_ANT0,          /**< Enable WiFi antenna 0 only */
-    WIFI_ANT_MODE_ANT1,          /**< Enable WiFi antenna 1 only */
-    WIFI_ANT_MODE_AUTO,          /**< Enable WiFi antenna 0 and 1, automatically select an antenna */
-    WIFI_ANT_MODE_MAX,           /**< Invalid WiFi enabled antenna */
+    WIFI_ANT_MODE_ANT0,          /**< Enable Wi-Fi antenna 0 only */
+    WIFI_ANT_MODE_ANT1,          /**< Enable Wi-Fi antenna 1 only */
+    WIFI_ANT_MODE_AUTO,          /**< Enable Wi-Fi antenna 0 and 1, automatically select an antenna */
+    WIFI_ANT_MODE_MAX,           /**< Invalid Wi-Fi enabled antenna */
 } wifi_ant_mode_t;
 
 /**
-  * @brief WiFi antenna configuration
+  * @brief Wi-Fi antenna configuration
   *
   */
 typedef struct {
-    wifi_ant_mode_t rx_ant_mode;          /**< WiFi antenna mode for receiving */
+    wifi_ant_mode_t rx_ant_mode;          /**< Wi-Fi antenna mode for receiving */
     wifi_ant_t      rx_ant_default;       /**< Default antenna mode for receiving, it's ignored if rx_ant_mode is not WIFI_ANT_MODE_AUTO */
-    wifi_ant_mode_t tx_ant_mode;          /**< WiFi antenna mode for transmission, it can be set to WIFI_ANT_MODE_AUTO only if rx_ant_mode is set to WIFI_ANT_MODE_AUTO */
+    wifi_ant_mode_t tx_ant_mode;          /**< Wi-Fi antenna mode for transmission, it can be set to WIFI_ANT_MODE_AUTO only if rx_ant_mode is set to WIFI_ANT_MODE_AUTO */
     uint8_t         enabled_ant0: 4,      /**< Index (in antenna GPIO configuration) of enabled WIFI_ANT_MODE_ANT0 */
                     enabled_ant1: 4;      /**< Index (in antenna GPIO configuration) of enabled WIFI_ANT_MODE_ANT1 */
 } wifi_ant_config_t;
@@ -670,21 +756,19 @@ typedef struct {
 /**
   * @brief     The Rx callback function of Action Tx operations
   *
-  * @param     hdr pointer to the IEEE 802.11 Header structure
-  * @param     payload pointer to the Payload following 802.11 Header
-  * @param     len length of the Payload
-  * @param     channel channel number the frame is received on
+  * @param     hdr Pointer to the IEEE 802.11 Header structure
+  * @param     payload Pointer to the Payload following 802.11 Header
+  * @param     len Length of the Payload
+  * @param     channel Channel number the frame is received on
   *
   */
 typedef int (* wifi_action_rx_cb_t)(uint8_t *hdr, uint8_t *payload,
                                     size_t len, uint8_t channel);
 /**
- * @brief Action Frame Tx Request
- *
- *
- */
+  * @brief Action Frame Tx Request
+  */
 typedef struct {
-    wifi_interface_t ifx;       /**< WiFi interface to send request to */
+    wifi_interface_t ifx;       /**< Wi-Fi interface to send request to */
     uint8_t dest_mac[6];        /**< Destination MAC address */
     bool no_ack;                /**< Indicates no ack required */
     wifi_action_rx_cb_t rx_cb;  /**< Rx Callback to receive any response */
@@ -705,16 +789,17 @@ typedef struct {
                                      WIFI_EVENT_FTM_REPORT to get FTM report */
 } wifi_ftm_initiator_cfg_t;
 
-#define ESP_WIFI_NAN_MAX_SVC_SUPPORTED  2
-#define ESP_WIFI_NAN_DATAPATH_MAX_PEERS 2
+#define ESP_WIFI_NAN_MAX_SVC_SUPPORTED  2      /**< Maximum number of NAN services supported */
+#define ESP_WIFI_NAN_DATAPATH_MAX_PEERS 2      /**< Maximum number of NAN datapath peers supported */
 
-#define ESP_WIFI_NDP_ROLE_INITIATOR     1
-#define ESP_WIFI_NDP_ROLE_RESPONDER     2
+#define ESP_WIFI_NDP_ROLE_INITIATOR     1      /**< Initiator role for NAN Data Path */
+#define ESP_WIFI_NDP_ROLE_RESPONDER     2      /**< Responder role for NAN Data Path */
+
+#define ESP_WIFI_MAX_SVC_NAME_LEN       256    /**< Maximum length of NAN service name */
+#define ESP_WIFI_MAX_FILTER_LEN         256    /**< Maximum length of NAN service filter */
+#define ESP_WIFI_MAX_SVC_INFO_LEN       64     /**< Maximum length of NAN service info */
+#define ESP_WIFI_MAX_NEIGHBOR_REP_LEN   64     /**< Maximum length of NAN Neighbor Report */
 
-#define ESP_WIFI_MAX_SVC_NAME_LEN       256
-#define ESP_WIFI_MAX_FILTER_LEN         256
-#define ESP_WIFI_MAX_SVC_INFO_LEN       64
-#define ESP_WIFI_MAX_NEIGHBOR_REP_LEN   64
 /**
   * @brief NAN Services types
   *
@@ -794,7 +879,35 @@ typedef struct {
 } wifi_nan_datapath_end_req_t;
 
 /**
-  * @brief WiFi PHY rate encodings
+  * @brief Wi-Fi PHY rate encodings
+  *
+  * @note Rate Table: MCS Rate and Guard Interval Information
+  * |       MCS RATE              |          HT20           |          HT40           |          HE20           |         VHT20           |
+  * |-----------------------------|-------------------------|-------------------------|-------------------------|-------------------------|
+  * | WIFI_PHY_RATE_MCS0_LGI      |     6.5 Mbps (800 ns)   |    13.5 Mbps (800 ns)   |     8.1 Mbps (1600 ns)  |     6.5 Mbps (800 ns)   |
+  * | WIFI_PHY_RATE_MCS1_LGI      |      13 Mbps (800 ns)   |      27 Mbps (800 ns)   |    16.3 Mbps (1600 ns)  |      13 Mbps (800 ns)   |
+  * | WIFI_PHY_RATE_MCS2_LGI      |    19.5 Mbps (800 ns)   |    40.5 Mbps (800 ns)   |    24.4 Mbps (1600 ns)  |    19.5 Mbps (800 ns)   |
+  * | WIFI_PHY_RATE_MCS3_LGI      |      26 Mbps (800 ns)   |      54 Mbps (800 ns)   |    32.5 Mbps (1600 ns)  |      26 Mbps (800 ns)   |
+  * | WIFI_PHY_RATE_MCS4_LGI      |      39 Mbps (800 ns)   |      81 Mbps (800 ns)   |    48.8 Mbps (1600 ns)  |      39 Mbps (800 ns)   |
+  * | WIFI_PHY_RATE_MCS5_LGI      |      52 Mbps (800 ns)   |     108 Mbps (800 ns)   |      65 Mbps (1600 ns)  |      52 Mbps (800 ns)   |
+  * | WIFI_PHY_RATE_MCS6_LGI      |    58.5 Mbps (800 ns)   |   121.5 Mbps (800 ns)   |    73.1 Mbps (1600 ns)  |    58.5 Mbps (800 ns)   |
+  * | WIFI_PHY_RATE_MCS7_LGI      |      65 Mbps (800 ns)   |     135 Mbps (800 ns)   |    81.3 Mbps (1600 ns)  |      65 Mbps (800 ns)   |
+  * | WIFI_PHY_RATE_MCS8_LGI      |                         |                         |    97.5 Mbps (1600 ns)  |                         |
+  * | WIFI_PHY_RATE_MCS9_LGI      |                         |                         |   108.3 Mbps (1600 ns)  |                         |
+  *
+  * @note
+  * |       MCS RATE              |          HT20           |          HT40           |          HE20           |         VHT20           |
+  * |-----------------------------|-------------------------|-------------------------|-------------------------|-------------------------|
+  * | WIFI_PHY_RATE_MCS0_SGI      |     7.2 Mbps (400 ns)   |      15 Mbps (400 ns)   |      8.6 Mbps (800 ns)  |     7.2 Mbps (400 ns)   |
+  * | WIFI_PHY_RATE_MCS1_SGI      |    14.4 Mbps (400 ns)   |      30 Mbps (400 ns)   |     17.2 Mbps (800 ns)  |    14.4 Mbps (400 ns)   |
+  * | WIFI_PHY_RATE_MCS2_SGI      |    21.7 Mbps (400 ns)   |      45 Mbps (400 ns)   |     25.8 Mbps (800 ns)  |    21.7 Mbps (400 ns)   |
+  * | WIFI_PHY_RATE_MCS3_SGI      |    28.9 Mbps (400 ns)   |      60 Mbps (400 ns)   |     34.4 Mbps (800 ns)  |    28.9 Mbps (400 ns)   |
+  * | WIFI_PHY_RATE_MCS4_SGI      |    43.3 Mbps (400 ns)   |      90 Mbps (400 ns)   |     51.6 Mbps (800 ns)  |    43.3 Mbps (400 ns)   |
+  * | WIFI_PHY_RATE_MCS5_SGI      |    57.8 Mbps (400 ns)   |     120 Mbps (400 ns)   |     68.8 Mbps (800 ns)  |    57.8 Mbps (400 ns)   |
+  * | WIFI_PHY_RATE_MCS6_SGI      |      65 Mbps (400 ns)   |     135 Mbps (400 ns)   |     77.4 Mbps (800 ns)  |      65 Mbps (400 ns)   |
+  * | WIFI_PHY_RATE_MCS7_SGI      |    72.2 Mbps (400 ns)   |     150 Mbps (400 ns)   |       86 Mbps (800 ns)  |    72.2 Mbps (400 ns)   |
+  * | WIFI_PHY_RATE_MCS8_SGI      |                         |                         |    103.2 Mbps (800 ns)  |                         |
+  * | WIFI_PHY_RATE_MCS9_SGI      |                         |                         |    114.7 Mbps (800 ns)  |                         |
   *
   */
 typedef enum {
@@ -813,22 +926,7 @@ typedef enum {
     WIFI_PHY_RATE_36M       = 0x0D, /**< 36 Mbps */
     WIFI_PHY_RATE_18M       = 0x0E, /**< 18 Mbps */
     WIFI_PHY_RATE_9M        = 0x0F, /**< 9 Mbps */
-    /**< rate table and guard interval information for each MCS rate*/
-    /*
-     -------------------------------------------------------------------------------------------------------------------------------------
-            MCS RATE             |          HT20           |          HT40           |          HE20           |         VHT20           |
-     WIFI_PHY_RATE_MCS0_LGI      |     6.5 Mbps (800ns)    |    13.5 Mbps (800ns)    |     8.1 Mbps (1600ns)   |     6.5 Mbps (800ns)    |
-     WIFI_PHY_RATE_MCS1_LGI      |      13 Mbps (800ns)    |      27 Mbps (800ns)    |    16.3 Mbps (1600ns)   |      13 Mbps (800ns)    |
-     WIFI_PHY_RATE_MCS2_LGI      |    19.5 Mbps (800ns)    |    40.5 Mbps (800ns)    |    24.4 Mbps (1600ns)   |    19.5 Mbps (800ns)    |
-     WIFI_PHY_RATE_MCS3_LGI      |      26 Mbps (800ns)    |      54 Mbps (800ns)    |    32.5 Mbps (1600ns)   |      26 Mbps (800ns)    |
-     WIFI_PHY_RATE_MCS4_LGI      |      39 Mbps (800ns)    |      81 Mbps (800ns)    |    48.8 Mbps (1600ns)   |      39 Mbps (800ns)    |
-     WIFI_PHY_RATE_MCS5_LGI      |      52 Mbps (800ns)    |     108 Mbps (800ns)    |      65 Mbps (1600ns)   |      52 Mbps (800ns)    |
-     WIFI_PHY_RATE_MCS6_LGI      |    58.5 Mbps (800ns)    |   121.5 Mbps (800ns)    |    73.1 Mbps (1600ns)   |    58.5 Mbps (800ns)    |
-     WIFI_PHY_RATE_MCS7_LGI      |      65 Mbps (800ns)    |     135 Mbps (800ns)    |    81.3 Mbps (1600ns)   |      65 Mbps (800ns)    |
-     WIFI_PHY_RATE_MCS8_LGI      |          -----          |          -----          |    97.5 Mbps (1600ns)   |          -----          |
-     WIFI_PHY_RATE_MCS9_LGI      |          -----          |          -----          |   108.3 Mbps (1600ns)   |          -----          |
-     -------------------------------------------------------------------------------------------------------------------------------------
-    */
+
     WIFI_PHY_RATE_MCS0_LGI  = 0x10, /**< MCS0 with long GI */
     WIFI_PHY_RATE_MCS1_LGI  = 0x11, /**< MCS1 with long GI */
     WIFI_PHY_RATE_MCS2_LGI  = 0x12, /**< MCS2 with long GI */
@@ -841,21 +939,7 @@ typedef enum {
     WIFI_PHY_RATE_MCS8_LGI,         /**< MCS8 with long GI */
     WIFI_PHY_RATE_MCS9_LGI,         /**< MCS9 with long GI */
 #endif
-    /*
-     -------------------------------------------------------------------------------------------------------------------------------------
-            MCS RATE             |          HT20           |          HT40           |          HE20           |         VHT20           |
-     WIFI_PHY_RATE_MCS0_SGI      |     7.2 Mbps (400ns)    |      15 Mbps (400ns)    |      8.6 Mbps (800ns)   |     7.2 Mbps (400ns)    |
-     WIFI_PHY_RATE_MCS1_SGI      |    14.4 Mbps (400ns)    |      30 Mbps (400ns)    |     17.2 Mbps (800ns)   |    14.4 Mbps (400ns)    |
-     WIFI_PHY_RATE_MCS2_SGI      |    21.7 Mbps (400ns)    |      45 Mbps (400ns)    |     25.8 Mbps (800ns)   |    21.7 Mbps (400ns)    |
-     WIFI_PHY_RATE_MCS3_SGI      |    28.9 Mbps (400ns)    |      60 Mbps (400ns)    |     34.4 Mbps (800ns)   |    28.9 Mbps (400ns)    |
-     WIFI_PHY_RATE_MCS4_SGI      |    43.3 Mbps (400ns)    |      90 Mbps (400ns)    |     51.6 Mbps (800ns)   |    43.3 Mbps (400ns)    |
-     WIFI_PHY_RATE_MCS5_SGI      |    57.8 Mbps (400ns)    |     120 Mbps (400ns)    |     68.8 Mbps (800ns)   |    57.8 Mbps (400ns)    |
-     WIFI_PHY_RATE_MCS6_SGI      |      65 Mbps (400ns)    |     135 Mbps (400ns)    |     77.4 Mbps (800ns)   |      65 Mbps (400ns)    |
-     WIFI_PHY_RATE_MCS7_SGI      |    72.2 Mbps (400ns)    |     150 Mbps (400ns)    |       86 Mbps (800ns)   |    72.2 Mbps (400ns)    |
-     WIFI_PHY_RATE_MCS8_SGI      |          -----          |          -----          |    103.2 Mbps (800ns)   |          -----          |
-     WIFI_PHY_RATE_MCS9_SGI      |          -----          |          -----          |    114.7 Mbps (800ns)   |          -----          |
-     -------------------------------------------------------------------------------------------------------------------------------------
-    */
+
     WIFI_PHY_RATE_MCS0_SGI,         /**< MCS0 with short GI */
     WIFI_PHY_RATE_MCS1_SGI,         /**< MCS1 with short GI */
     WIFI_PHY_RATE_MCS2_SGI,         /**< MCS2 with short GI */
@@ -868,31 +952,33 @@ typedef enum {
     WIFI_PHY_RATE_MCS8_SGI,         /**< MCS8 with short GI */
     WIFI_PHY_RATE_MCS9_SGI,         /**< MCS9 with short GI */
 #endif
-    WIFI_PHY_RATE_LORA_250K = 0x29, /**< 250 Kbps */
-    WIFI_PHY_RATE_LORA_500K = 0x2A, /**< 500 Kbps */
+    WIFI_PHY_RATE_LORA_250K = 0x29, /**< Espressif-specific Long Range mode rate, 250 Kbps */
+    WIFI_PHY_RATE_LORA_500K = 0x2A, /**< Espressif-specific Long Range mode rate, 500 Kbps */
     WIFI_PHY_RATE_MAX,
 } wifi_phy_rate_t;
 
-/** WiFi event declarations */
+/**
+  * @brief Wi-Fi event declarations
+  */
 typedef enum {
-    WIFI_EVENT_WIFI_READY = 0,           /**< WiFi ready */
+    WIFI_EVENT_WIFI_READY = 0,           /**< Wi-Fi ready */
     WIFI_EVENT_SCAN_DONE,                /**< Finished scanning AP */
     WIFI_EVENT_STA_START,                /**< Station start */
     WIFI_EVENT_STA_STOP,                 /**< Station stop */
     WIFI_EVENT_STA_CONNECTED,            /**< Station connected to AP */
     WIFI_EVENT_STA_DISCONNECTED,         /**< Station disconnected from AP */
-    WIFI_EVENT_STA_AUTHMODE_CHANGE,      /**< the auth mode of AP connected by device's station changed */
+    WIFI_EVENT_STA_AUTHMODE_CHANGE,      /**< The auth mode of AP connected by device's station changed */
 
-    WIFI_EVENT_STA_WPS_ER_SUCCESS,       /**< Station wps succeeds in enrollee mode */
-    WIFI_EVENT_STA_WPS_ER_FAILED,        /**< Station wps fails in enrollee mode */
-    WIFI_EVENT_STA_WPS_ER_TIMEOUT,       /**< Station wps timeout in enrollee mode */
-    WIFI_EVENT_STA_WPS_ER_PIN,           /**< Station wps pin code in enrollee mode */
-    WIFI_EVENT_STA_WPS_ER_PBC_OVERLAP,   /**< Station wps overlap in enrollee mode */
+    WIFI_EVENT_STA_WPS_ER_SUCCESS,       /**< Station WPS succeeds in enrollee mode */
+    WIFI_EVENT_STA_WPS_ER_FAILED,        /**< Station WPS fails in enrollee mode */
+    WIFI_EVENT_STA_WPS_ER_TIMEOUT,       /**< Station WPS timeout in enrollee mode */
+    WIFI_EVENT_STA_WPS_ER_PIN,           /**< Station WPS pin code in enrollee mode */
+    WIFI_EVENT_STA_WPS_ER_PBC_OVERLAP,   /**< Station WPS overlap in enrollee mode */
 
     WIFI_EVENT_AP_START,                 /**< Soft-AP start */
     WIFI_EVENT_AP_STOP,                  /**< Soft-AP stop */
-    WIFI_EVENT_AP_STACONNECTED,          /**< a station connected to Soft-AP */
-    WIFI_EVENT_AP_STADISCONNECTED,       /**< a station disconnected from Soft-AP */
+    WIFI_EVENT_AP_STACONNECTED,          /**< A station connected to Soft-AP */
+    WIFI_EVENT_AP_STADISCONNECTED,       /**< A station disconnected from Soft-AP */
     WIFI_EVENT_AP_PROBEREQRECVED,        /**< Receive probe request packet in soft-AP interface */
 
     WIFI_EVENT_FTM_REPORT,               /**< Receive report of FTM procedure */
@@ -929,68 +1015,82 @@ typedef enum {
     WIFI_EVENT_NDP_INDICATION,           /**< Received NDP Request from a NAN Peer */
     WIFI_EVENT_NDP_CONFIRM,              /**< NDP Confirm Indication */
     WIFI_EVENT_NDP_TERMINATED,           /**< NAN Datapath terminated indication */
-    WIFI_EVENT_HOME_CHANNEL_CHANGE,      /**< WiFi home channel change，doesn't occur when scanning */
+    WIFI_EVENT_HOME_CHANNEL_CHANGE,      /**< Wi-Fi home channel change，doesn't occur when scanning */
 
     WIFI_EVENT_STA_NEIGHBOR_REP,         /**< Received Neighbor Report response */
 
-    WIFI_EVENT_MAX,                      /**< Invalid WiFi event ID */
+    WIFI_EVENT_MAX,                      /**< Invalid Wi-Fi event ID */
 } wifi_event_t;
 
 /** @cond **/
-/** @brief WiFi event base declaration */
+/** @brief Wi-Fi event base declaration */
 ESP_EVENT_DECLARE_BASE(WIFI_EVENT);
 /** @endcond **/
 
-/** Argument structure for WIFI_EVENT_SCAN_DONE event */
+/**
+  * @brief Argument structure for WIFI_EVENT_SCAN_DONE event
+  */
 typedef struct {
-    uint32_t status;          /**< status of scanning APs: 0 — success, 1 - failure */
-    uint8_t  number;          /**< number of scan results */
-    uint8_t  scan_id;         /**< scan sequence number, used for block scan */
+    uint32_t status;          /**< Status of scanning APs: 0 — success, 1 - failure */
+    uint8_t  number;          /**< Number of scan results */
+    uint8_t  scan_id;         /**< Scan sequence number, used for block scan */
 } wifi_event_sta_scan_done_t;
 
-/** Argument structure for WIFI_EVENT_STA_CONNECTED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_STA_CONNECTED event
+  */
 typedef struct {
     uint8_t ssid[32];         /**< SSID of connected AP */
     uint8_t ssid_len;         /**< SSID length of connected AP */
     uint8_t bssid[6];         /**< BSSID of connected AP*/
-    uint8_t channel;          /**< channel of connected AP*/
-    wifi_auth_mode_t authmode;/**< authentication mode used by AP*/
-    uint16_t aid;             /**< authentication id assigned by the connected AP */
+    uint8_t channel;          /**< Channel of connected AP*/
+    wifi_auth_mode_t authmode;/**< Authentication mode used by AP*/
+    uint16_t aid;             /**< Authentication id assigned by the connected AP */
 } wifi_event_sta_connected_t;
 
-/** Argument structure for WIFI_EVENT_STA_DISCONNECTED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_STA_DISCONNECTED event
+  */
 typedef struct {
     uint8_t ssid[32];         /**< SSID of disconnected AP */
     uint8_t ssid_len;         /**< SSID length of disconnected AP */
     uint8_t bssid[6];         /**< BSSID of disconnected AP */
-    uint8_t reason;           /**< reason of disconnection */
-    int8_t  rssi;             /**< rssi of disconnection */
+    uint8_t reason;           /**< Disconnection reason */
+    int8_t  rssi;             /**< Disconnection RSSI */
 } wifi_event_sta_disconnected_t;
 
-/** Argument structure for WIFI_EVENT_STA_AUTHMODE_CHANGE event */
+/**
+  * @brief Argument structure for WIFI_EVENT_STA_AUTHMODE_CHANGE event
+  */
 typedef struct {
-    wifi_auth_mode_t old_mode;         /**< the old auth mode of AP */
-    wifi_auth_mode_t new_mode;         /**< the new auth mode of AP */
+    wifi_auth_mode_t old_mode;         /**< Old auth mode of AP */
+    wifi_auth_mode_t new_mode;         /**< New auth mode of AP */
 } wifi_event_sta_authmode_change_t;
 
-/** Argument structure for WIFI_EVENT_STA_WPS_ER_PIN event */
+/**
+  * @brief Argument structure for WIFI_EVENT_STA_WPS_ER_PIN event
+  */
 typedef struct {
     uint8_t pin_code[8];         /**< PIN code of station in enrollee mode */
 } wifi_event_sta_wps_er_pin_t;
 
-/** Argument structure for WIFI_EVENT_STA_WPS_ER_FAILED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_STA_WPS_ER_FAILED event
+  */
 typedef enum {
     WPS_FAIL_REASON_NORMAL = 0,     /**< WPS normal fail reason */
     WPS_FAIL_REASON_RECV_M2D,       /**< WPS receive M2D frame */
     WPS_FAIL_REASON_RECV_DEAUTH,    /**< Recv deauth from AP while wps handshake */
-    WPS_FAIL_REASON_MAX
+    WPS_FAIL_REASON_MAX             /**< Max WPS fail reason */
 } wifi_event_sta_wps_fail_reason_t;
 
-#define MAX_SSID_LEN        32
-#define MAX_PASSPHRASE_LEN  64
-#define MAX_WPS_AP_CRED     3
+#define MAX_SSID_LEN        32    /**< Maximum length of SSID */
+#define MAX_PASSPHRASE_LEN  64    /**< Maximum length of passphrase */
+#define MAX_WPS_AP_CRED     3     /**< Maximum number of AP credentials received from WPS handshake */
 
-/** Argument structure for WIFI_EVENT_STA_WPS_ER_SUCCESS event */
+/**
+  * @brief Argument structure for WIFI_EVENT_STA_WPS_ER_SUCCESS event
+  */
 typedef struct {
     uint8_t ap_cred_cnt;                        /**< Number of AP credentials received */
     struct {
@@ -999,38 +1099,48 @@ typedef struct {
     } ap_cred[MAX_WPS_AP_CRED];                 /**< All AP credentials received from WPS handshake */
 } wifi_event_sta_wps_er_success_t;
 
-/** Argument structure for WIFI_EVENT_AP_STACONNECTED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_AP_STACONNECTED event
+  */
 typedef struct {
     uint8_t mac[6];           /**< MAC address of the station connected to Soft-AP */
-    uint8_t aid;              /**< the aid that soft-AP gives to the station connected to  */
-    bool is_mesh_child;       /**< flag to identify mesh child */
+    uint8_t aid;              /**< AID assigned by the Soft-AP to the connected station  */
+    bool is_mesh_child;       /**< Flag indicating whether the connected station is a mesh child */
 } wifi_event_ap_staconnected_t;
 
-/** Argument structure for WIFI_EVENT_AP_STADISCONNECTED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_AP_STADISCONNECTED event
+  */
 typedef struct {
-    uint8_t mac[6];           /**< MAC address of the station disconnects to soft-AP */
-    uint8_t aid;              /**< the aid that soft-AP gave to the station disconnects to  */
-    bool is_mesh_child;       /**< flag to identify mesh child */
-    uint16_t reason;           /**< reason of disconnection */
+    uint8_t mac[6];           /**< MAC address of the station disconnects from the soft-AP */
+    uint8_t aid;              /**< AID that the Soft-AP assigned to the disconnected station  */
+    bool is_mesh_child;       /**< Flag indicating whether the disconnected station is a mesh child */
+    uint16_t reason;           /**< Disconnection reason */
 } wifi_event_ap_stadisconnected_t;
 
-/** Argument structure for WIFI_EVENT_AP_PROBEREQRECVED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_AP_PROBEREQRECVED event
+  */
 typedef struct {
     int rssi;                 /**< Received probe request signal strength */
     uint8_t mac[6];           /**< MAC address of the station which send probe request */
 } wifi_event_ap_probe_req_rx_t;
 
-/** Argument structure for WIFI_EVENT_STA_BSS_RSSI_LOW event */
+/**
+  * @brief Argument structure for WIFI_EVENT_STA_BSS_RSSI_LOW event
+  */
 typedef struct {
     int32_t rssi;                 /**< RSSI value of bss */
 } wifi_event_bss_rssi_low_t;
 
-/** Argument structure for WIFI_EVENT_HOME_CHANNEL_CHANGE event */
+/**
+  * @brief Argument structure for WIFI_EVENT_HOME_CHANNEL_CHANGE event
+  */
 typedef struct {
-    uint8_t            old_chan;   /**< old home channel of the device */
-    wifi_second_chan_t old_snd;    /**< old second channel of the device */
-    uint8_t            new_chan;   /**< new home channel of the device */
-    wifi_second_chan_t new_snd;    /**< new second channel of the device */
+    uint8_t            old_chan;   /**< Old home channel of the device */
+    wifi_second_chan_t old_snd;    /**< Old second channel of the device */
+    uint8_t            new_chan;   /**< New home channel of the device */
+    wifi_second_chan_t new_snd;    /**< New second channel of the device */
 } wifi_event_home_channel_change_t;
 
 /**
@@ -1047,7 +1157,13 @@ typedef enum {
     FTM_STATUS_USER_TERM,       /**< User triggered termination */
 } wifi_ftm_status_t;
 
-/** Argument structure for */
+/**
+  * @brief Structure representing a report entry for Fine Timing Measurement (FTM) in Wi-Fi.
+  *
+  * This structure holds the information related to the FTM process between a Wi-Fi FTM Initiator
+  * and a Wi-Fi FTM Responder. FTM is used for precise distance measurement by timing the exchange
+  * of frames between devices.
+  */
 typedef struct {
     uint8_t dlog_token;     /**< Dialog Token of the FTM frame */
     int8_t rssi;            /**< RSSI of the FTM frame received */
@@ -1058,7 +1174,9 @@ typedef struct {
     uint64_t t4;            /**< Time of arrival of ACK at FTM Responder in pSec */
 } wifi_ftm_report_entry_t;
 
-/** Argument structure for WIFI_EVENT_FTM_REPORT event */
+/**
+  * @brief Argument structure for WIFI_EVENT_FTM_REPORT event
+  */
 typedef struct {
     uint8_t peer_mac[6];                        /**< MAC address of the FTM Peer */
     wifi_ftm_status_t status;                   /**< Status of the FTM operation */
@@ -1070,50 +1188,65 @@ typedef struct {
     uint8_t ftm_report_num_entries;             /**< Number of entries in the FTM Report data */
 } wifi_event_ftm_report_t;
 
-#define WIFI_STATIS_BUFFER    (1<<0)
-#define WIFI_STATIS_RXTX      (1<<1)
-#define WIFI_STATIS_HW        (1<<2)
-#define WIFI_STATIS_DIAG      (1<<3)
-#define WIFI_STATIS_PS        (1<<4)
-#define WIFI_STATIS_ALL       (-1)
+#define WIFI_STATIS_BUFFER    (1<<0)    /**< Buffer status */
+#define WIFI_STATIS_RXTX      (1<<1)    /**< RX/TX status */
+#define WIFI_STATIS_HW        (1<<2)    /**< Hardware status */
+#define WIFI_STATIS_DIAG      (1<<3)    /**< Diagnostic status */
+#define WIFI_STATIS_PS        (1<<4)    /**< Power save status */
+#define WIFI_STATIS_ALL       (-1)      /**< All status */
 
-/** Argument structure for WIFI_EVENT_ACTION_TX_STATUS event */
+/**
+  * @brief Argument structure for WIFI_EVENT_ACTION_TX_STATUS event
+  */
 typedef struct {
-    wifi_interface_t ifx;     /**< WiFi interface to send request to */
+    wifi_interface_t ifx;     /**< Wi-Fi interface to send request to */
     uint32_t context;         /**< Context to identify the request */
     uint8_t da[6];            /**< Destination MAC address */
     uint8_t status;           /**< Status of the operation */
 } wifi_event_action_tx_status_t;
 
-/** Argument structure for WIFI_EVENT_ROC_DONE event */
+/**
+  * @brief Argument structure for WIFI_EVENT_ROC_DONE event
+  */
 typedef struct {
     uint32_t context;         /**< Context to identify the request */
 } wifi_event_roc_done_t;
 
-/** Argument structure for WIFI_EVENT_AP_WPS_RG_PIN event */
+/**
+  * @brief Argument structure for WIFI_EVENT_AP_WPS_RG_PIN event
+  */
 typedef struct {
     uint8_t pin_code[8];         /**< PIN code of station in enrollee mode */
 } wifi_event_ap_wps_rg_pin_t;
 
+/**
+  * @brief WPS fail reason
+  */
 typedef enum {
     WPS_AP_FAIL_REASON_NORMAL = 0,     /**< WPS normal fail reason */
     WPS_AP_FAIL_REASON_CONFIG,         /**< WPS failed due to incorrect config */
     WPS_AP_FAIL_REASON_AUTH,           /**< WPS failed during auth */
-    WPS_AP_FAIL_REASON_MAX,
+    WPS_AP_FAIL_REASON_MAX,            /**< Max WPS fail reason */
 } wps_fail_reason_t;
 
-/** Argument structure for WIFI_EVENT_AP_WPS_RG_FAILED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_AP_WPS_RG_FAILED event
+  */
 typedef struct {
     wps_fail_reason_t reason;          /**< WPS failure reason wps_fail_reason_t */
     uint8_t peer_macaddr[6];           /**< Enrollee mac address */
 } wifi_event_ap_wps_rg_fail_reason_t;
 
-/** Argument structure for WIFI_EVENT_AP_WPS_RG_SUCCESS event */
+/**
+  * @brief Argument structure for WIFI_EVENT_AP_WPS_RG_SUCCESS event
+  */
 typedef struct {
     uint8_t peer_macaddr[6];           /**< Enrollee mac address */
 } wifi_event_ap_wps_rg_success_t;
 
-/** Argument structure for WIFI_EVENT_NAN_SVC_MATCH event */
+/**
+  * @brief Argument structure for WIFI_EVENT_NAN_SVC_MATCH event
+  */
 typedef struct {
     uint8_t subscribe_id;       /**< Subscribe Service Identifier */
     uint8_t publish_id;         /**< Publish Service Identifier */
@@ -1121,14 +1254,18 @@ typedef struct {
     bool update_pub_id;         /**< Indicates whether publisher's service ID needs to be updated */
 } wifi_event_nan_svc_match_t;
 
-/** Argument structure for WIFI_EVENT_NAN_REPLIED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_NAN_REPLIED event
+  */
 typedef struct {
     uint8_t publish_id;         /**< Publish Service Identifier */
     uint8_t subscribe_id;       /**< Subscribe Service Identifier */
     uint8_t sub_if_mac[6];      /**< NAN Interface MAC of the Subscriber */
 } wifi_event_nan_replied_t;
 
-/** Argument structure for WIFI_EVENT_NAN_RECEIVE event */
+/**
+  * @brief Argument structure for WIFI_EVENT_NAN_RECEIVE event
+  */
 typedef struct {
     uint8_t inst_id;                                 /**< Our Service Identifier */
     uint8_t peer_inst_id;                            /**< Peer's Service Identifier */
@@ -1136,7 +1273,9 @@ typedef struct {
     uint8_t peer_svc_info[ESP_WIFI_MAX_SVC_INFO_LEN];/**< Peer Service Info */
 } wifi_event_nan_receive_t;
 
-/** Argument structure for WIFI_EVENT_NDP_INDICATION event */
+/**
+  * @brief Argument structure for WIFI_EVENT_NDP_INDICATION event
+  */
 typedef struct {
     uint8_t publish_id;                         /**< Publish Id for NAN Service */
     uint8_t ndp_id;                             /**< NDP instance id */
@@ -1145,7 +1284,9 @@ typedef struct {
     uint8_t svc_info[ESP_WIFI_MAX_SVC_INFO_LEN];/**< Service Specific Info */
 } wifi_event_ndp_indication_t;
 
-/** Argument structure for WIFI_EVENT_NDP_CONFIRM event */
+/**
+  * @brief Argument structure for WIFI_EVENT_NDP_CONFIRM event
+  */
 typedef struct {
     uint8_t status;                             /**< NDP status code */
     uint8_t ndp_id;                             /**< NDP instance id */
@@ -1155,14 +1296,18 @@ typedef struct {
     uint8_t svc_info[ESP_WIFI_MAX_SVC_INFO_LEN];/**< Service Specific Info */
 } wifi_event_ndp_confirm_t;
 
-/** Argument structure for WIFI_EVENT_NDP_TERMINATED event */
+/**
+  * @brief Argument structure for WIFI_EVENT_NDP_TERMINATED event
+  */
 typedef struct {
     uint8_t reason;                             /**< Termination reason code */
     uint8_t ndp_id;                             /**< NDP instance id */
     uint8_t init_ndi[6];                        /**< Initiator's NAN Data Interface MAC */
 } wifi_event_ndp_terminated_t;
 
-/** Argument structure for WIFI_EVENT_STA_NEIGHBOR_REP event */
+/**
+  * @brief Argument structure for WIFI_EVENT_STA_NEIGHBOR_REP event
+  */
 typedef struct {
     uint8_t report[ESP_WIFI_MAX_NEIGHBOR_REP_LEN];  /**< Neighbor Report received from the AP*/
     uint16_t report_len;                            /**< Length of the report*/
diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib
index dde71a69c52..ede55ea6fdf 160000
--- a/components/esp_wifi/lib
+++ b/components/esp_wifi/lib
@@ -1 +1 @@
-Subproject commit dde71a69c525d0a69989eca620557536b2773231
+Subproject commit ede55ea6fdfc67953b5d5f3caf8f37a15d39237d
diff --git a/components/esp_wifi/src/wifi_netif.c b/components/esp_wifi/src/wifi_netif.c
index 9b6183bcd6d..f42ff6bd52e 100644
--- a/components/esp_wifi/src/wifi_netif.c
+++ b/components/esp_wifi/src/wifi_netif.c
@@ -69,7 +69,7 @@ static esp_err_t wifi_transmit(void *h, void *buffer, size_t len)
 static esp_err_t wifi_transmit_wrap(void *h, void *buffer, size_t len, void *netstack_buf)
 {
     wifi_netif_driver_t driver = h;
-#if CONFIG_SPIRAM
+#if CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !CONFIG_SPIRAM_IGNORE_NOTFOUND
     return esp_wifi_internal_tx_by_ref(driver->wifi_if, buffer, len, netstack_buf);
 #else
     return esp_wifi_internal_tx(driver->wifi_if, buffer, len);
diff --git a/components/esp_wifi/test_md5/test_md5.sh b/components/esp_wifi/test_md5/test_md5.sh
index 98c29f77322..788a8744b7e 100755
--- a/components/esp_wifi/test_md5/test_md5.sh
+++ b/components/esp_wifi/test_md5/test_md5.sh
@@ -22,7 +22,7 @@ case $IDF_TARGET in
     esp32s3)
         PREFIX=xtensa-esp32s3-elf-
         ;;
-    esp32c2|esp32c3|esp32c6)
+    esp32c2|esp32c3|esp32c6|esp32c5|esp32_host|esp32c61)
         PREFIX=riscv32-esp-elf-
         ;;
     *)
diff --git a/components/espcoredump/Kconfig b/components/espcoredump/Kconfig
index c19b0eabbae..90b806d96aa 100644
--- a/components/espcoredump/Kconfig
+++ b/components/espcoredump/Kconfig
@@ -108,7 +108,7 @@ menu "Core dump"
 
     config ESP_COREDUMP_USE_STACK_SIZE
         bool
-        default y if ESP_COREDUMP_ENABLE_TO_FLASH && SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+        default y if ESP_COREDUMP_ENABLE_TO_FLASH && FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
         default n
         help
             Force the use of a custom DRAM stack for coredump when Task stacks can be in PSRAM.
diff --git a/components/espcoredump/src/port/riscv/core_dump_port.c b/components/espcoredump/src/port/riscv/core_dump_port.c
index 60a2ac39546..7d872ce62e5 100644
--- a/components/espcoredump/src/port/riscv/core_dump_port.c
+++ b/components/espcoredump/src/port/riscv/core_dump_port.c
@@ -37,7 +37,7 @@ const static char TAG[] __attribute__((unused)) = "esp_core_dump_port";
 /**
  * Union representing the registers of the CPU as they will be written
  * in the core dump.
- * Registers can be adressed with their names thanks to the structure, or as
+ * Registers can be addressed with their names thanks to the structure, or as
  * an array of 32 words.
  */
 #define RISCV_GP_REGS_COUNT 32
@@ -222,7 +222,7 @@ uint32_t esp_core_dump_get_isr_stack_end(void)
 static inline bool esp_core_dump_task_stack_end_is_sane(uint32_t sp)
 {
     return esp_ptr_in_dram((void *)sp)
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
            || esp_stack_ptr_in_extram(sp)
 #endif
 #if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
@@ -315,7 +315,7 @@ bool esp_core_dump_mem_seg_is_sane(uint32_t addr, uint32_t sz)
 }
 
 /**
- * Get the task's registers dump when the panic occured.
+ * Get the task's registers dump when the panic occurred.
  * Returns the size, in bytes, of the data pointed by reg_dumps.
  * The data pointed by reg_dump are allocated statically, thus, they must be
  * used (or copied) before calling this function again.
diff --git a/components/espcoredump/src/port/xtensa/core_dump_port.c b/components/espcoredump/src/port/xtensa/core_dump_port.c
index cee4c1ebc1e..8efae60d576 100644
--- a/components/espcoredump/src/port/xtensa/core_dump_port.c
+++ b/components/espcoredump/src/port/xtensa/core_dump_port.c
@@ -299,7 +299,7 @@ uint32_t esp_core_dump_get_isr_stack_end(void)
 static inline bool esp_core_dump_task_stack_end_is_sane(uint32_t sp)
 {
     return esp_ptr_in_dram((void *)sp)
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
            || esp_stack_ptr_in_extram(sp)
 #endif
 #if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake
index 9f051b2359c..de0efe407cc 100644
--- a/components/esptool_py/project_include.cmake
+++ b/components/esptool_py/project_include.cmake
@@ -5,6 +5,7 @@ idf_build_get_property(target IDF_TARGET)
 idf_build_get_property(python PYTHON)
 idf_build_get_property(idf_path IDF_PATH)
 
+idf_build_get_property(non_os_build NON_OS_BUILD)
 
 set(chip_model ${target})
 
@@ -151,7 +152,7 @@ elseif(CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME OR CONFIG_SECURE_SIGNED_APPS_ECDSA_V
     set(secure_boot_version "2")
 endif()
 
-if(NOT BOOTLOADER_BUILD AND CONFIG_SECURE_SIGNED_APPS)
+if(NOT non_os_build AND CONFIG_SECURE_SIGNED_APPS)
     if(CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES)
         # for locally signed secure boot image, add a signing step to get from unsigned app to signed app
         get_filename_component(secure_boot_signing_key "${CONFIG_SECURE_BOOT_SIGNING_KEY}"
@@ -526,7 +527,7 @@ function(esptool_py_custom_target target_name flasher_filename dependencies)
     endif()
 endfunction()
 
-if(NOT BOOTLOADER_BUILD)
+if(NOT non_os_build)
     set(flash_deps "")
 
     if(CONFIG_APP_BUILD_TYPE_APP_2NDBOOT)
diff --git a/components/fatfs/fatfsgen.py b/components/fatfs/fatfsgen.py
index 4ab13020015..30d274f5260 100755
--- a/components/fatfs/fatfsgen.py
+++ b/components/fatfs/fatfsgen.py
@@ -1,10 +1,11 @@
 #!/usr/bin/env python
 # SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
-
 import os
 from datetime import datetime
-from typing import Any, List, Optional
+from typing import Any
+from typing import List
+from typing import Optional
 
 from fatfs_utils.boot_sector import BootSector
 from fatfs_utils.exceptions import NoFreeClusterException
@@ -12,10 +13,16 @@
 from fatfs_utils.fatfs_state import FATFSState
 from fatfs_utils.fs_object import Directory
 from fatfs_utils.long_filename_utils import get_required_lfn_entries_count
-from fatfs_utils.utils import (BYTES_PER_DIRECTORY_ENTRY, FATFS_INCEPTION, FATFS_MIN_ALLOC_UNIT,
-                               RESERVED_CLUSTERS_COUNT, FATDefaults, get_args_for_partition_generator,
-                               get_fat_sectors_count, get_non_data_sectors_cnt, read_filesystem,
-                               required_clusters_count)
+from fatfs_utils.utils import BYTES_PER_DIRECTORY_ENTRY
+from fatfs_utils.utils import FATDefaults
+from fatfs_utils.utils import FATFS_INCEPTION
+from fatfs_utils.utils import FATFS_MIN_ALLOC_UNIT
+from fatfs_utils.utils import get_args_for_partition_generator
+from fatfs_utils.utils import get_fat_sectors_count
+from fatfs_utils.utils import get_non_data_sectors_cnt
+from fatfs_utils.utils import read_filesystem
+from fatfs_utils.utils import required_clusters_count
+from fatfs_utils.utils import RESERVED_CLUSTERS_COUNT
 
 
 def duplicate_fat_decorator(func):  # type: ignore
@@ -48,14 +55,15 @@ def __init__(self,
                  volume_label: str = FATDefaults.VOLUME_LABEL,
                  file_sys_type: str = FATDefaults.FILE_SYS_TYPE,
                  root_entry_count: int = FATDefaults.ROOT_ENTRIES_COUNT,
-                 explicit_fat_type: int = None,
+                 explicit_fat_type: Optional[int] = None,
                  media_type: int = FATDefaults.MEDIA_TYPE) -> None:
         # root directory bytes should be aligned by sector size
-        assert (root_entry_count * BYTES_PER_DIRECTORY_ENTRY) % sector_size == 0
+        assert (int(root_entry_count) * BYTES_PER_DIRECTORY_ENTRY) % sector_size == 0
         # number of bytes in the root dir must be even multiple of BPB_BytsPerSec
-        assert ((root_entry_count * BYTES_PER_DIRECTORY_ENTRY) // sector_size) % 2 == 0
+        if (int(root_entry_count) > 128):
+            assert ((int(root_entry_count) * BYTES_PER_DIRECTORY_ENTRY) // sector_size) % 2 == 0
 
-        root_dir_sectors_cnt: int = (root_entry_count * BYTES_PER_DIRECTORY_ENTRY) // sector_size
+        root_dir_sectors_cnt: int = (int(root_entry_count) * BYTES_PER_DIRECTORY_ENTRY) // sector_size
 
         self.state: FATFSState = FATFSState(sector_size=sector_size,
                                             explicit_fat_type=explicit_fat_type,
diff --git a/components/fatfs/host_test/main/test_fatfs.cpp b/components/fatfs/host_test/main/test_fatfs.cpp
index a948822eef8..88aa16e1c49 100644
--- a/components/fatfs/host_test/main/test_fatfs.cpp
+++ b/components/fatfs/host_test/main/test_fatfs.cpp
@@ -44,7 +44,10 @@ TEST_CASE("Create volume, open file, write and read back data", "[fatfs]")
 
     fr_result = f_fdisk(pdrv, part_list, work_area);
     REQUIRE(fr_result == FR_OK);
-    const MKFS_PARM opt = {(BYTE)FM_ANY, 0, 0, 0, 0};
+
+    // For host tests, include FM_SFD flag when formatting partitions smaller than 128KB.
+    // if n_root field of MKFS_PARM is set to 128 => 1 root directory sec and if set to 0(default 512) => 4 root directory sectors.
+    const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 128, 0};
     fr_result = f_mkfs("", &opt, work_area, sizeof(work_area)); // Use default volume
 
     // Mount the volume
@@ -56,7 +59,7 @@ TEST_CASE("Create volume, open file, write and read back data", "[fatfs]")
     REQUIRE(fr_result == FR_OK);
 
     // Generate data
-    uint32_t data_size = 100000;
+    uint32_t data_size = 1000;
 
     char *data = (char*) malloc(data_size);
     char *read = (char*) malloc(data_size);
@@ -130,7 +133,7 @@ static void prepare_fatfs(const char* partition_label, const esp_partition_t** p
 
     fr_result = f_fdisk(_pdrv, part_list, work_area);
     REQUIRE(fr_result == FR_OK);
-    const MKFS_PARM opt = {(BYTE)FM_ANY, 0, 0, 0, 0};
+    const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 128, 0};
     fr_result = f_mkfs(drv, &opt, work_area, sizeof(work_area)); // Use default volume
     REQUIRE(fr_result == FR_OK);
 }
@@ -222,7 +225,7 @@ TEST_CASE("Test mounting 2 volumes, writing data and formatting the 2nd one, rea
     const size_t workbuf_size = 4096;
     void *workbuf = ff_memalloc(workbuf_size);
     REQUIRE(workbuf != NULL);
-    const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 0, CONFIG_WL_SECTOR_SIZE};
+    const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), 0, 0, 128, CONFIG_WL_SECTOR_SIZE};
     fr_result = f_mkfs(drv1, &opt, workbuf, workbuf_size);
     free(workbuf);
     workbuf = NULL;
diff --git a/components/fatfs/host_test/partition_table.csv b/components/fatfs/host_test/partition_table.csv
index 30d2d909258..777a3e67e9f 100644
--- a/components/fatfs/host_test/partition_table.csv
+++ b/components/fatfs/host_test/partition_table.csv
@@ -3,5 +3,5 @@
 nvs,      data, nvs,     0x9000,  0x6000,
 phy_init, data, phy,     0xf000,  0x1000,
 factory,  app,  factory, 0x10000, 1M,
-storage,  data, fat,     ,        1M,
-storage2, data, fat,     ,        1M,
+storage,  data, fat,     ,        32k,
+storage2, data, fat,     ,        32k,
diff --git a/components/fatfs/src/ff.c b/components/fatfs/src/ff.c
index 49b8d89620f..3c3f1ace61d 100644
--- a/components/fatfs/src/ff.c
+++ b/components/fatfs/src/ff.c
@@ -34,7 +34,6 @@
 #error Wrong include file (ff.h).
 #endif
 
-
 /* Limits and boundaries */
 #define MAX_DIR		0x200000		/* Max size of FAT directory */
 #define MAX_DIR_EX	0x10000000		/* Max size of exFAT directory */
@@ -43,6 +42,10 @@
 #define MAX_FAT32	0x0FFFFFF5		/* Max FAT32 clusters (not specified, practical limit) */
 #define MAX_EXFAT	0x7FFFFFFD		/* Max exFAT clusters (differs from specs, implementation limit) */
 
+#define MIN_FAT12_SEC_VOL         4  /* Min size of the FAT sector volume
+                                        1 FAT, 1 root dir, 1 reserved, 1 data sector */
+#define MIN_FAT12_DATA_SEC        1  /* Min FAT data sectors */
+
 
 /* Character code support macros */
 #define IsUpper(c)		((c) >= 'A' && (c) <= 'Z')
@@ -3318,7 +3321,7 @@ static UINT check_fs (	/* 0:FAT/FAT32 VBR, 1:exFAT VBR, 2:Not FAT and valid BS,
 			&& ld_word(fs->win + BPB_RsvdSecCnt) != 0	/* Properness of reserved sectors (MNBZ) */
 			&& (UINT)fs->win[BPB_NumFATs] - 1 <= 1		/* Properness of FATs (1 or 2) */
 			&& ld_word(fs->win + BPB_RootEntCnt) != 0	/* Properness of root dir entries (MNBZ) */
-			&& (ld_word(fs->win + BPB_TotSec16) >= 128 || ld_dword(fs->win + BPB_TotSec32) >= 0x10000)	/* Properness of volume sectors (>=128) */
+			&& (ld_word(fs->win + BPB_TotSec16) >= MIN_FAT12_SEC_VOL || ld_dword(fs->win + BPB_TotSec32) >= 0x10000)	/* Properness of volume sectors (>=MIN_FAT12_SEC_VOL) */
 			&& ld_word(fs->win + BPB_FATSz16) != 0) {	/* Properness of FAT size (MNBZ) */
 				return 0;	/* It can be presumed an FAT VBR */
 		}
@@ -6034,7 +6037,11 @@ FRESULT f_mkfs (
 			}
 		}
 	}
-	if (sz_vol < 128) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Check if volume size is >=128s */
+	if (n_fat == 1) {
+			if (sz_vol < MIN_FAT12_SEC_VOL) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >= MIN_FAT12_SEC_VOLs */
+	} else {
+			if (sz_vol < (MIN_FAT12_SEC_VOL + 1)) LEAVE_MKFS(FR_MKFS_ABORTED); /* Check if volume size is >= (MIN_FAT12_SEC_VOL+1)s */
+	}
 
 	/* Now start to create an FAT volume at b_vol and sz_vol */
 
@@ -6265,7 +6272,7 @@ FRESULT f_mkfs (
 			}
 
 			/* Determine number of clusters and final check of validity of the FAT sub-type */
-			if (sz_vol < b_data + pau * 16 - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too small volume? */
+			if (sz_vol < b_data + pau * MIN_FAT12_DATA_SEC - b_vol) LEAVE_MKFS(FR_MKFS_ABORTED);	/* Too small volume? */
 			n_clst = ((DWORD)sz_vol - sz_rsv - sz_fat * n_fat - sz_dir) / pau;
 			if (fsty == FS_FAT32) {
 				if (n_clst <= MAX_FAT16) {	/* Too few clusters for FAT32? */
diff --git a/components/fatfs/test_apps/.build-test-rules.yml b/components/fatfs/test_apps/.build-test-rules.yml
index 5aae749df65..2fb48788ccc 100644
--- a/components/fatfs/test_apps/.build-test-rules.yml
+++ b/components/fatfs/test_apps/.build-test-rules.yml
@@ -23,10 +23,6 @@ components/fatfs/test_apps/flash_wl:
     - wear_leveling
 
 components/fatfs/test_apps/sdcard:
-  disable:
-    - if: IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"]
-      temporary: true
-      reason: target esp32p4, esp32c5 is not supported yet # TODO: [ESP32P4] IDF-7501 [ESP32C5] IDF-8704, [esp32c61] IDF-9305
   disable_test:
     - if: IDF_TARGET not in ["esp32", "esp32c3"]
       temporary: true
diff --git a/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt b/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt
index 20b600fca29..f6501bda48f 100644
--- a/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt
+++ b/components/fatfs/test_apps/flash_wl/main/CMakeLists.txt
@@ -1,4 +1,4 @@
-idf_component_register(SRCS "test_fatfs_flash_wl.c"
+idf_component_register(SRCS "test_fatfs_flash_wl.c" "test_fatfs_small_partition.c"
                        INCLUDE_DIRS "."
                        PRIV_REQUIRES unity spi_flash fatfs vfs test_fatfs_common
                        WHOLE_ARCHIVE)
diff --git a/components/fatfs/test_apps/flash_wl/main/test_fatfs_small_partition.c b/components/fatfs/test_apps/flash_wl/main/test_fatfs_small_partition.c
new file mode 100644
index 00000000000..fd65a4db811
--- /dev/null
+++ b/components/fatfs/test_apps/flash_wl/main/test_fatfs_small_partition.c
@@ -0,0 +1,76 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <fcntl.h>
+#include <sys/unistd.h>
+#include "unity.h"
+#include "esp_vfs_fat.h"
+
+static wl_handle_t s_test_wl_handle;
+static void test_setup(void)
+{
+  // With this configuration, for 32k partition size,
+  // 4 sectors will be used for WL and 4 sectors for FATFS
+  // (1 FAT,  1 root directory, 1 reserved and 1 data sector)
+    esp_vfs_fat_mount_config_t mount_config = {
+        .format_if_mount_failed = true,
+        .max_files = 5,
+        .use_one_fat = true,
+    };
+
+    TEST_ESP_OK(esp_vfs_fat_spiflash_format_cfg_rw_wl("/spiflash", "storage1", &mount_config));
+    TEST_ESP_OK(esp_vfs_fat_spiflash_mount_rw_wl("/spiflash", "storage1", &mount_config, &s_test_wl_handle));
+}
+
+static void test_teardown(void)
+{
+    TEST_ESP_OK(esp_vfs_fat_spiflash_unmount_rw_wl("/spiflash", s_test_wl_handle));
+}
+
+static void test_write_data_sec(int num_data_sec)
+{
+    int fd = open("/spiflash/test.txt", O_CREAT | O_WRONLY);
+    TEST_ASSERT_NOT_EQUAL(-1, fd);
+
+    // Generate data
+    uint32_t data_size = 4096*num_data_sec;
+
+    char *data = (char*) malloc(data_size);
+    char *read_data = (char*) malloc(data_size);
+
+    for(uint32_t i = 0; i < (data_size); i += sizeof(i))
+    {
+        *((uint32_t*)(data + i)) = i;
+    }
+    ssize_t wr = write(fd, data, data_size);
+    if (num_data_sec == 1) {
+        TEST_ASSERT_EQUAL(data_size, wr);
+    } else {
+        TEST_ASSERT_NOT_EQUAL(data_size, wr);
+    }
+    TEST_ASSERT_EQUAL(0, close(fd));
+
+    fd = open("/spiflash/test.txt", O_RDONLY);
+    int r = read(fd, read_data, data_size);
+    if (num_data_sec == 1) {
+        TEST_ASSERT_EQUAL(data_size, r);
+    } else {
+        TEST_ASSERT_NOT_EQUAL(data_size, r);
+    }
+    TEST_ASSERT_EQUAL(0, strcmp(data, read_data));
+    TEST_ASSERT_EQUAL(0, close(fd));
+}
+
+TEST_CASE("(WL) can format small partition and read-write data", "[fatfs][wear_levelling][timeout=120]")
+{
+    test_setup();
+    test_write_data_sec(1); //for 1 data sectors, write and read func should work
+    test_write_data_sec(2); //for 2 data sectors, write and read func should fail
+    test_teardown();
+}
diff --git a/components/fatfs/test_apps/flash_wl/partitions.csv b/components/fatfs/test_apps/flash_wl/partitions.csv
index d1dcbae61db..d68a9de0115 100644
--- a/components/fatfs/test_apps/flash_wl/partitions.csv
+++ b/components/fatfs/test_apps/flash_wl/partitions.csv
@@ -2,3 +2,4 @@
 factory,  app,  factory, 0x10000, 768k,
 storage,  data, fat,     ,        528k,
 storage2, data, fat,     ,        528k,
+storage1, data, fat,     ,        32k,
diff --git a/components/fatfs/test_apps/sdcard/README.md b/components/fatfs/test_apps/sdcard/README.md
index 639f1d386dc..381b38a983b 100644
--- a/components/fatfs/test_apps/sdcard/README.md
+++ b/components/fatfs/test_apps/sdcard/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 This test app runs a few FATFS test cases in a FAT-formatted SD card.
 
diff --git a/components/fatfs/test_apps/sdcard/main/test_fatfs_sdspi.c b/components/fatfs/test_apps/sdcard/main/test_fatfs_sdspi.c
index 7ff45e3caa4..a3247bd2456 100644
--- a/components/fatfs/test_apps/sdcard/main/test_fatfs_sdspi.c
+++ b/components/fatfs/test_apps/sdcard/main/test_fatfs_sdspi.c
@@ -35,13 +35,13 @@
 #define SDSPI_MOSI_PIN 35
 #define SDSPI_CLK_PIN  36
 #define SDSPI_CS_PIN   34
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C61
 #define SDSPI_MISO_PIN 6
 #define SDSPI_MOSI_PIN 4
 #define SDSPI_CLK_PIN  5
 #define SDSPI_CS_PIN   1
 #define SPI_DMA_CHAN   SPI_DMA_CH_AUTO
-#elif CONFIG_IDF_TARGET_ESP32H2
+#elif CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32P4
 #define SDSPI_MISO_PIN 0
 #define SDSPI_MOSI_PIN 5
 #define SDSPI_CLK_PIN  4
diff --git a/components/fatfs/vfs/vfs_fat_spiflash.c b/components/fatfs/vfs/vfs_fat_spiflash.c
index dffd7ec1bb8..7144f165f6a 100644
--- a/components/fatfs/vfs/vfs_fat_spiflash.c
+++ b/components/fatfs/vfs/vfs_fat_spiflash.c
@@ -15,6 +15,10 @@
 #include "wear_levelling.h"
 #include "diskio_wl.h"
 
+// If the available sectors based on partition size are less than 128,
+// the root directory sector should be set to 1.
+#define MIN_REQ_SEC    128
+
 static const char* TAG = "vfs_fat_spiflash";
 
 static vfs_fat_spiflash_ctx_t *s_ctx[FF_VOLUMES] = {};
@@ -74,7 +78,7 @@ vfs_fat_spiflash_ctx_t* get_vfs_fat_spiflash_ctx(wl_handle_t wlhandle)
     return NULL;
 }
 
-static esp_err_t s_f_mount_rw(FATFS *fs, const char *drv, const esp_vfs_fat_mount_config_t *mount_config, vfs_fat_x_ctx_flags_t *out_flags)
+static esp_err_t s_f_mount_rw(FATFS *fs, const char *drv, const esp_vfs_fat_mount_config_t *mount_config, vfs_fat_x_ctx_flags_t *out_flags, size_t sec_num)
 {
     FRESULT fresult = f_mount(fs, drv, 1);
     if (fresult != FR_OK) {
@@ -93,7 +97,13 @@ static esp_err_t s_f_mount_rw(FATFS *fs, const char *drv, const esp_vfs_fat_moun
 
         size_t alloc_unit_size = esp_vfs_fat_get_allocation_unit_size(CONFIG_WL_SECTOR_SIZE, mount_config->allocation_unit_size);
         ESP_LOGI(TAG, "Formatting FATFS partition, allocation unit size=%d", alloc_unit_size);
-        const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), (mount_config->use_one_fat ? 1 : 2), 0, 0, alloc_unit_size};
+        UINT root_dir_entries;
+        if (CONFIG_WL_SECTOR_SIZE == 512) {
+            root_dir_entries = 16;
+        } else {
+            root_dir_entries = 128;
+        }
+        const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), (mount_config->use_one_fat ? 1 : 2), 0, (sec_num <= MIN_REQ_SEC ? root_dir_entries : 0), alloc_unit_size};
         fresult = f_mkfs(drv, &opt, workbuf, workbuf_size);
         free(workbuf);
         workbuf = NULL;
@@ -157,8 +167,9 @@ esp_err_t esp_vfs_fat_spiflash_mount_rw_wl(const char* base_path,
 
     vfs_fat_x_ctx_flags_t flags = 0;
 
+    size_t sec_num = wl_size(*wl_handle) / wl_sector_size(*wl_handle);
     // Try to mount partition
-    ret = s_f_mount_rw(fs, drv, mount_config, &flags);
+    ret = s_f_mount_rw(fs, drv, mount_config, &flags, sec_num);
     if (ret != ESP_OK) {
         goto fail;
     }
@@ -224,6 +235,7 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha
 
     wl_handle_t temp_handle = WL_INVALID_HANDLE;
     uint32_t id = FF_VOLUMES;
+    size_t sec_num = 0;
 
     bool found = s_get_context_id_by_label(partition_label, &id);
     if (!found) {
@@ -239,6 +251,7 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha
         }
         ESP_RETURN_ON_ERROR(esp_vfs_fat_spiflash_mount_rw_wl(base_path, partition_label, mount_cfg, &temp_handle), TAG, "Failed to mount");
         found = s_get_context_id_by_label(partition_label, &id);
+        sec_num = wl_size(temp_handle) / wl_sector_size(temp_handle);
         assert(found);
         if (s_ctx[id]->flags & FORMATTED_DURING_LAST_MOUNT) {
             ESP_LOGD(TAG, "partition was formatted during mounting, skipping another format");
@@ -250,6 +263,8 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha
         if (cfg) {
             s_ctx[id]->mount_config = *cfg;
         }
+        temp_handle = s_ctx[id]->wlhandle;
+        sec_num = wl_size(temp_handle) / wl_sector_size(temp_handle);
     }
 
     //unmount
@@ -266,7 +281,13 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha
     }
     size_t alloc_unit_size = esp_vfs_fat_get_allocation_unit_size(CONFIG_WL_SECTOR_SIZE, s_ctx[id]->mount_config.allocation_unit_size);
     ESP_LOGI(TAG, "Formatting FATFS partition, allocation unit size=%d", alloc_unit_size);
-    const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), (s_ctx[id]->mount_config.use_one_fat ? 1 : 2), 0, 0, alloc_unit_size};
+    UINT root_dir_entries;
+    if (CONFIG_WL_SECTOR_SIZE == 512) {
+        root_dir_entries = 16;
+    } else {
+        root_dir_entries = 128;
+    }
+    const MKFS_PARM opt = {(BYTE)(FM_ANY | FM_SFD), (s_ctx[id]->mount_config.use_one_fat ? 1 : 2), 0, (sec_num <= MIN_REQ_SEC ? root_dir_entries : 0), alloc_unit_size};
     fresult = f_mkfs(drv, &opt, workbuf, workbuf_size);
     free(workbuf);
     workbuf = NULL;
@@ -274,7 +295,7 @@ esp_err_t esp_vfs_fat_spiflash_format_cfg_rw_wl(const char* base_path, const cha
 
 mount_back:
     if (partition_was_mounted) {
-        esp_err_t err = s_f_mount_rw(s_ctx[id]->fs, drv, &s_ctx[id]->mount_config, NULL);
+        esp_err_t err = s_f_mount_rw(s_ctx[id]->fs, drv, &s_ctx[id]->mount_config, NULL, sec_num);
         if (err != ESP_OK) {
             ESP_LOGE(TAG, "failed to mount back, go to recycle");
             goto recycle;
diff --git a/components/freertos/CMakeLists.txt b/components/freertos/CMakeLists.txt
index 5776b7f3783..87798ab7885 100644
--- a/components/freertos/CMakeLists.txt
+++ b/components/freertos/CMakeLists.txt
@@ -20,7 +20,9 @@
 #       - Files common across all kernel implementations and all ports
 
 # Bootloader builds only needs FreeRTOS for config, not for anything else
-if(BOOTLOADER_BUILD)
+idf_build_get_property(non_os_build NON_OS_BUILD)
+
+if(non_os_build)
     idf_component_register()
     return()
 endif()
diff --git a/components/freertos/FreeRTOS-Kernel/idf_changes.md b/components/freertos/FreeRTOS-Kernel/idf_changes.md
index a3ef8454601..7bf620e6e41 100644
--- a/components/freertos/FreeRTOS-Kernel/idf_changes.md
+++ b/components/freertos/FreeRTOS-Kernel/idf_changes.md
@@ -123,6 +123,10 @@ The following functions were modified to accommodate SMP behavior:
   - In SMP, the function now disables interrupts to ensure that the calling task does not switch cores while checking its own copy of `uxSchedulerSuspended`.
 - `prvAddCurrentTaskToDelayedList()`
   - Added extra check to see if current blocking task has already been deleted by the other core.
+- `xStreamBufferReceive()`
+  - Added a critical section for setting `xTaskWaitingToReceive` to `NULL` so that the write is SMP safe.
+- `xStreamBufferSend()`
+  - Added a critical section for setting `xTaskWaitingToSend` to `NULL` so that the write is SMP safe.
 
 ### Critical Section Changes
 
diff --git a/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h
index 179265b778e..583c568d888 100644
--- a/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h
+++ b/components/freertos/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h
@@ -94,8 +94,8 @@ extern void vPortEnableInterrupts( void );
 extern BaseType_t xPortSetInterruptMask( void );
 extern void vPortClearInterruptMask( BaseType_t xMask );
 
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
 #define portSET_INTERRUPT_MASK_FROM_ISR()       xPortSetInterruptMask()
 #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortClearInterruptMask(x)
 #define portDISABLE_INTERRUPTS()                portSET_INTERRUPT_MASK()
diff --git a/components/freertos/FreeRTOS-Kernel/stream_buffer.c b/components/freertos/FreeRTOS-Kernel/stream_buffer.c
index 50c2fb13cae..04d67a20056 100644
--- a/components/freertos/FreeRTOS-Kernel/stream_buffer.c
+++ b/components/freertos/FreeRTOS-Kernel/stream_buffer.c
@@ -6,7 +6,7 @@
  *
  * SPDX-License-Identifier: MIT
  *
- * SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -774,7 +774,18 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
 
             traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
             ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
-            pxStreamBuffer->xTaskWaitingToSend = NULL;
+            /* In SMP mode, the task may have been woken and scheduled on
+             * another core. Hence, we must clear the xTaskWaitingToSend
+             * handle in a critical section. */
+            #if ( configNUMBER_OF_CORES > 1 )
+                taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) );
+            #endif /* configNUMBER_OF_CORES > 1 */
+            {
+                pxStreamBuffer->xTaskWaitingToSend = NULL;
+            }
+            #if ( configNUMBER_OF_CORES > 1 )
+                taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) );
+            #endif /* configNUMBER_OF_CORES > 1 */
         } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
     }
     else
@@ -977,7 +988,19 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
             /* Wait for data to be available. */
             traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
             ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
-            pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+            /* In SMP mode, the task may have been woken and scheduled on
+             * another core. Hence, we must clear the xTaskWaitingToReceive
+             * handle in a critical section. */
+            #if ( configNUMBER_OF_CORES > 1 )
+                taskENTER_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) );
+            #endif /* configNUMBER_OF_CORES > 1 */
+            {
+                pxStreamBuffer->xTaskWaitingToReceive = NULL;
+            }
+            #if ( configNUMBER_OF_CORES > 1 )
+                taskEXIT_CRITICAL( &( pxStreamBuffer->xStreamBufferLock ) );
+            #endif /* configNUMBER_OF_CORES > 1 */
 
             /* Recheck the data available after blocking. */
             xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
@@ -1421,7 +1444,7 @@ static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
          * result in confusion as to what is actually being observed. */
         const BaseType_t xWriteValue = 0x55;
         configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
-        (void)xWriteValue;
+        ( void ) xWriteValue;
     } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
     #endif
 
diff --git a/components/freertos/FreeRTOS-Kernel/tasks.c b/components/freertos/FreeRTOS-Kernel/tasks.c
index 8d06ea30b0d..368a20599fd 100644
--- a/components/freertos/FreeRTOS-Kernel/tasks.c
+++ b/components/freertos/FreeRTOS-Kernel/tasks.c
@@ -4123,10 +4123,19 @@ void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
         if( taskIS_YIELD_REQUIRED( pxUnblockedTCB, pdFALSE ) == pdTRUE )
         {
             /* The unblocked task has a priority above that of the calling task, so
-             * a context switch is required.  This function is called with the
-             * scheduler suspended so xYieldPending is set so the context switch
-             * occurs immediately that the scheduler is resumed (unsuspended). */
-            xYieldPending[ xCurCoreID ] = pdTRUE;
+             * a context switch is required. */
+            #if ( configNUM_CORES > 1 )
+
+                /* In SMP mode, this function is called from a critical section, so we
+                 * yield the current core to schedule the unblocked task. */
+                portYIELD_WITHIN_API();
+            #else /* configNUM_CORES > 1 */
+
+                /* In single-core mode, this function is called with the scheduler suspended
+                 * so xYieldPending is set so the context switch occurs immediately once the
+                 * scheduler is resumed (unsuspended). */
+                xYieldPending[ xCurCoreID ] = pdTRUE;
+            #endif /* configNUM_CORES > 1 */
         }
     }
 }
diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig
index ba0bb786f48..dec261a93c8 100644
--- a/components/freertos/Kconfig
+++ b/components/freertos/Kconfig
@@ -573,6 +573,33 @@ menu "FreeRTOS"
 
     endmenu # Port
 
+    menu "Extra"
+
+        config FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
+            depends on SPIRAM
+            depends on FREERTOS_SUPPORT_STATIC_ALLOCATION
+            bool "Allow external memory as an argument to xTaskCreateStatic (READ HELP)"
+            default n if IDF_TARGET_ESP32
+            default y
+            help
+                Accessing memory in PSRAM has certain restrictions, so task stacks allocated by xTaskCreate
+                are by default allocated from internal RAM.
+
+                This option allows for passing memory allocated from SPIRAM to be passed to xTaskCreateStatic.
+                This should only be used for tasks where the stack is never accessed while the cache is disabled.
+
+                Extra notes for ESP32:
+
+                Because some bits of the ESP32 code environment cannot be recompiled with the cache workaround,
+                normally tasks cannot be safely run with their stack residing in external memory; for this reason
+                xTaskCreate (and related task creation functions) always allocate stack in internal memory and
+                xTaskCreateStatic will check if the memory passed to it is in internal memory.
+                If you have a task that needs a large amount of stack and does not call on ROM code in any way
+                (no direct calls, but also no Bluetooth/WiFi), you can try enable this to
+                cause xTaskCreateStatic to allow tasks stack in external memory.
+
+    endmenu  # Extra
+
     # Hidden or compatibility options
 
     config FREERTOS_PORT
diff --git a/components/freertos/heap_idf.c b/components/freertos/heap_idf.c
index 57ff845f742..60974047097 100644
--- a/components/freertos/heap_idf.c
+++ b/components/freertos/heap_idf.c
@@ -99,7 +99,7 @@ bool xPortcheckValidStackMem(const void * ptr)
 #if CONFIG_IDF_TARGET_LINUX
     return true;
 #else /* CONFIG_IDF_TARGET_LINUX */
-#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#ifdef CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
     return esp_ptr_byte_accessible(ptr);
 #else
     return esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr);
diff --git a/components/freertos/sdkconfig.rename b/components/freertos/sdkconfig.rename
index 5720544d0e7..da4c466482a 100644
--- a/components/freertos/sdkconfig.rename
+++ b/components/freertos/sdkconfig.rename
@@ -5,3 +5,4 @@ CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK     CONFIG_FREERTOS_ENABLE_STATIC_TASK_C
 CONFIG_TIMER_TASK_PRIORITY                  CONFIG_FREERTOS_TIMER_TASK_PRIORITY
 CONFIG_TIMER_TASK_STACK_DEPTH               CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH
 CONFIG_TIMER_QUEUE_LENGTH                   CONFIG_FREERTOS_TIMER_QUEUE_LENGTH
+CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY   CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
diff --git a/components/freertos/test_apps/freertos/kernel/event_groups/test_freertos_eventgroups.c b/components/freertos/test_apps/freertos/kernel/event_groups/test_freertos_eventgroups.c
index b14f1ea1ca2..00ff6980c9e 100644
--- a/components/freertos/test_apps/freertos/kernel/event_groups/test_freertos_eventgroups.c
+++ b/components/freertos/test_apps/freertos/kernel/event_groups/test_freertos_eventgroups.c
@@ -132,6 +132,57 @@ TEST_CASE("FreeRTOS Event Group Sync", "[freertos]")
     vEventGroupDelete(eg);
 }
 
+static TaskHandle_t run_order[2];
+static uint32_t run_order_index = 0;
+
+void task_test_eg_prio(void *arg)
+{
+    TaskHandle_t main_task_hdl = (TaskHandle_t)arg;
+
+    /* Notify the main task that this task has been created */
+    xTaskNotifyGive(main_task_hdl);
+
+    /* Wait for the event group bits to be set */
+    TEST_ASSERT_EQUAL(1, xEventGroupWaitBits(eg, 1, pdTRUE, pdTRUE, portMAX_DELAY));
+
+    /* Record the task handle in the run order array */
+    run_order[run_order_index++] = xTaskGetCurrentTaskHandle();
+
+    /* Suspend the task */
+    vTaskSuspend(NULL);
+}
+
+TEST_CASE("FreeRTOS Event Groups do not cause priority inversion when higher priority task is unblocked", "[freertos]")
+{
+    run_order[0] = NULL;
+    run_order[1] = NULL;
+    run_order_index = 0;
+
+    /* Initialize the event group */
+    eg = xEventGroupCreate();
+
+    /* Create a task with higher priority than the task that will set the event group bits */
+    TaskHandle_t higher_prio_hdl;
+    TEST_ASSERT_EQUAL(pdTRUE, xTaskCreatePinnedToCore(task_test_eg_prio, "task_test_eg_prio", 2048, (void *)xTaskGetCurrentTaskHandle(), CONFIG_UNITY_FREERTOS_PRIORITY + 1, &higher_prio_hdl, CONFIG_UNITY_FREERTOS_CPU));
+
+    /* Wait for the task to be created */
+    ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
+
+    /* Set the event group bits */
+    xEventGroupSetBits(eg, 1);
+
+    /* Record the task handle in the run order array */
+    run_order[run_order_index++] = xTaskGetCurrentTaskHandle();
+
+    /* Verify that the higher priority task was unblocked and immediately scheduled and the lower priority task was preempted */
+    TEST_ASSERT_EQUAL(higher_prio_hdl, run_order[0]);
+    TEST_ASSERT_EQUAL(xTaskGetCurrentTaskHandle(), run_order[1]);
+
+    /* Clean up */
+    vEventGroupDelete(eg);
+    vTaskDelete(higher_prio_hdl);
+}
+
 /*-----------------Test case for event group trace facilities-----------------*/
 #ifdef  CONFIG_FREERTOS_USE_TRACE_FACILITY
 /*
diff --git a/components/freertos/test_apps/freertos/misc/test_idf_additions.c b/components/freertos/test_apps/freertos/misc/test_idf_additions.c
index 2f4d4a1fb76..5c5c3d69add 100644
--- a/components/freertos/test_apps/freertos/misc/test_idf_additions.c
+++ b/components/freertos/test_apps/freertos/misc/test_idf_additions.c
@@ -89,7 +89,7 @@ TEST_CASE("IDF additions: Task creation with memory caps and self deletion", "[f
     xTaskNotifyGive(task_handle);
 }
 
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
 
 TEST_CASE("IDF additions: Task creation with SPIRAM memory caps and self deletion stress test", "[freertos]")
 {
@@ -115,7 +115,7 @@ TEST_CASE("IDF additions: Task creation with SPIRAM memory caps and self deletio
     }
 }
 
-#endif /* CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY */
+#endif /* CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM */
 
 #if ( CONFIG_FREERTOS_NUMBER_OF_CORES > 1 )
 
diff --git a/components/freertos/test_apps/freertos/pytest_freertos.py b/components/freertos/test_apps/freertos/pytest_freertos.py
index ff27e9bc354..e2cdb05bd2c 100644
--- a/components/freertos/test_apps/freertos/pytest_freertos.py
+++ b/components/freertos/test_apps/freertos/pytest_freertos.py
@@ -7,7 +7,7 @@
 CONFIGS = [
     pytest.param('default', marks=[pytest.mark.supported_targets,]),
     pytest.param('freertos_options', marks=[pytest.mark.supported_targets]),
-    pytest.param('psram', marks=[pytest.mark.esp32]),
+    pytest.param('psram', marks=[pytest.mark.esp32, pytest.mark.esp32s3, pytest.mark.esp32p4, pytest.mark.esp32c5]),
     pytest.param('single_core', marks=[pytest.mark.esp32, pytest.mark.esp32p4]),
     # TODO: [ESP32C5] IDF-10335
     # TODO: [ESP32C61] IDF-11146
diff --git a/components/freertos/test_apps/freertos/sdkconfig.ci.psram b/components/freertos/test_apps/freertos/sdkconfig.ci.psram
index 1e330983154..776e127a2aa 100644
--- a/components/freertos/test_apps/freertos/sdkconfig.ci.psram
+++ b/components/freertos/test_apps/freertos/sdkconfig.ci.psram
@@ -5,7 +5,7 @@ CONFIG_IDF_TARGET="esp32"
 # Enable SPIRAM
 CONFIG_SPIRAM=y
 CONFIG_SPIRAM_OCCUPY_NO_HOST=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 
 # Disable encrypted flash reads/writes to save IRAM in this build configuration
 CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=n
diff --git a/components/hal/.build-test-rules.yml b/components/hal/.build-test-rules.yml
index 2577a357be2..161bbc1df3b 100644
--- a/components/hal/.build-test-rules.yml
+++ b/components/hal/.build-test-rules.yml
@@ -1,6 +1,8 @@
 components/hal/test_apps/crypto:
   depends_components:
     - efuse
+    - mbedtls
+    - esp_security
 
 components/hal/test_apps/hal_i2c:
   disable:
diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt
index 35ca479f78f..698bd8adffb 100644
--- a/components/hal/CMakeLists.txt
+++ b/components/hal/CMakeLists.txt
@@ -271,6 +271,10 @@ if(NOT BOOTLOADER_BUILD)
         list(APPEND srcs "usb_serial_jtag_hal.c")
     endif()
 
+    if(CONFIG_SOC_USB_UTMI_PHY_NUM GREATER 0)
+        list(APPEND srcs "usb_utmi_hal.c")
+    endif()
+
     if(CONFIG_SOC_USB_OTG_SUPPORTED)
         list(APPEND srcs
                     "usb_dwc_hal.c"
@@ -278,10 +282,15 @@ if(NOT BOOTLOADER_BUILD)
     endif()
 
     if(CONFIG_SOC_TOUCH_SENSOR_SUPPORTED)
-        list(APPEND srcs "${target}/touch_sensor_hal.c")
+        # Source files for legacy touch driver
         if(CONFIG_SOC_TOUCH_SENSOR_VERSION LESS 3)
+            list(APPEND srcs "${target}/touch_sensor_hal.c")
             list(APPEND srcs "touch_sensor_hal.c")
         endif()
+        # Source files for touch driver-ng (currently only support ver2 & ver3)
+        if(CONFIG_SOC_TOUCH_SENSOR_VERSION GREATER 1)
+            list(APPEND srcs "touch_sens_hal.c")
+        endif()
     endif()
 
     if(${target} STREQUAL "esp32")
@@ -330,8 +339,3 @@ if(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL EQUAL 1)
 elseif(CONFIG_HAL_DEFAULT_ASSERTION_LEVEL EQUAL 2)
     target_link_libraries(${COMPONENT_LIB} INTERFACE "-u __assert_func")
 endif()
-
-if((CONFIG_IDF_TARGET_ESP32H2 OR CONFIG_IDF_TARGET_ESP32S2 OR CONFIG_IDF_TARGET_ESP32S3) AND
-   CONFIG_COMPILER_STATIC_ANALYZER AND CMAKE_C_COMPILER_ID STREQUAL "GNU") # TODO IDF-10234
-    target_compile_options(${COMPONENT_LIB} PRIVATE "-fno-analyzer")
-endif()
diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c
index 1688491f2db..e71c70f1de0 100644
--- a/components/hal/adc_hal.c
+++ b/components/hal/adc_hal.c
@@ -300,3 +300,14 @@ void adc_hal_digi_clr_eof(void)
     adc_ll_digi_dma_clr_eof();
 }
 #endif
+
+#if SOC_ADC_MONITOR_SUPPORTED
+void adc_hal_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t adc_ch, int32_t h_thres, int32_t l_thres)
+{
+    adc_ll_digi_monitor_set_thres(monitor_id, adc_n, adc_ch, h_thres, l_thres);
+
+    // enable peripheral intr_ena accordingly
+    adc_ll_digi_monitor_enable_intr(monitor_id, ADC_MONITOR_MODE_HIGH, (h_thres >= 0));
+    adc_ll_digi_monitor_enable_intr(monitor_id, ADC_MONITOR_MODE_LOW, (l_thres >= 0));
+}
+#endif  //SOC_ADC_MONITOR_SUPPORTED
diff --git a/components/hal/ecdsa_hal.c b/components/hal/ecdsa_hal.c
index 237a461f6d7..bec830e3914 100644
--- a/components/hal/ecdsa_hal.c
+++ b/components/hal/ecdsa_hal.c
@@ -14,13 +14,8 @@
 #include "esp_random.h"
 #endif
 
-// Need to remove in IDF-8621
-#if CONFIG_IDF_TARGET_ESP32C5
-#include "soc/keymng_reg.h"
-#endif
-
 #ifdef SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
-#include "hal/key_mgr_hal.h"
+#include "hal/key_mgr_ll.h"
 #endif
 
 #define ECDSA_HAL_P192_COMPONENT_LEN        24
@@ -32,11 +27,6 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf)
     if (conf->use_km_key == 0) {
         efuse_hal_set_ecdsa_key(conf->efuse_key_blk);
 
-// Need to remove in IDF-8621
-#if CONFIG_IDF_TARGET_ESP32C5
-        REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 1);
-#endif
-
 #if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
         // Force Key Manager to use eFuse key for XTS-AES operation
         key_mgr_ll_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
diff --git a/components/hal/emac_hal.c b/components/hal/emac_hal.c
index 427809f939a..a8ee895ffc7 100644
--- a/components/hal/emac_hal.c
+++ b/components/hal/emac_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,10 @@
 #include "esp_attr.h"
 #include "hal/emac_hal.h"
 #include "hal/emac_ll.h"
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+#include "esp_rom_sys.h"
+#define EMAC_PTP_INIT_TIMEOUT_US (10)
+#endif // SOC_EMAC_IEEE1588V2_SUPPORTED
 
 static esp_err_t emac_hal_flush_trans_fifo(emac_hal_context_t *hal)
 {
@@ -27,6 +31,11 @@ void emac_hal_init(emac_hal_context_t *hal)
     hal->mac_regs = &EMAC_MAC;
 #if CONFIG_IDF_TARGET_ESP32
     hal->ext_regs = &EMAC_EXT;
+#else
+    hal->ext_regs = NULL;
+#endif
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+    hal->ptp_regs = &EMAC_PTP;
 #endif
 }
 
@@ -75,11 +84,11 @@ void emac_hal_init_mac_default(emac_hal_context_t *hal)
     emac_ll_set_duplex(hal->mac_regs, ETH_DUPLEX_FULL);
     /* Select the checksum mode for received frame payload's TCP/UDP/ICMP headers */
     emac_ll_checksum_offload_mode(hal->mac_regs, ETH_CHECKSUM_HW);
-    /* Enable MAC retry transmission when a colision occurs in half duplex mode */
+    /* Enable MAC retry transmission when a collision occurs in half duplex mode */
     emac_ll_retry_enable(hal->mac_regs, true);
     /* MAC passes all incoming frames to host, without modifying them */
     emac_ll_auto_pad_crc_strip_enable(hal->mac_regs, false);
-    /* Set Back-Off limit time before retry a transmittion after a collision */
+    /* Set Back-Off limit time before retry a transmission after a collision */
     emac_ll_set_back_off_limit(hal->mac_regs, EMAC_LL_BACKOFF_LIMIT_10);
     /* Disable deferral check, MAC defers until the CRS signal goes inactive */
     emac_ll_deferral_check_enable(hal->mac_regs, false);
@@ -193,6 +202,249 @@ void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr)
     }
 }
 
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+static inline uint32_t subsecond2nanosecond(emac_hal_context_t *hal, uint32_t subsecond)
+{
+    if (emac_ll_is_ts_digital_roll_set(hal->ptp_regs)) {
+        return subsecond;
+    }
+    uint64_t val = subsecond * 1000000000ll; // 1 s = 10e9 ns
+    val >>= 31; // Sub-Second register is 31 bit
+    return (uint32_t)val;
+}
+
+static inline uint32_t nanosecond2subsecond(emac_hal_context_t *hal, uint32_t nanosecond)
+{
+    if (emac_ll_is_ts_digital_roll_set(hal->ptp_regs)) {
+        return nanosecond;
+    }
+    uint64_t val = (uint64_t)nanosecond << 31;
+    val /= 1000000000ll;
+    return (uint32_t)val;
+}
+
+esp_err_t emac_hal_get_rxdesc_timestamp(emac_hal_context_t *hal, eth_dma_rx_descriptor_t *rxdesc, uint32_t *seconds, uint32_t *nano_seconds)
+{
+    if (!rxdesc->RDES0.TSAvailIPChecksumErrGiantFrame) {
+        return ESP_ERR_INVALID_STATE;
+    }
+
+    if (seconds) {
+        *seconds = rxdesc->TimeStampHigh;
+    }
+    if (nano_seconds) {
+        *nano_seconds = subsecond2nanosecond(hal, rxdesc->TimeStampLow);
+    }
+    rxdesc->RDES0.TSAvailIPChecksumErrGiantFrame = 0;
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_get_txdesc_timestamp(emac_hal_context_t *hal, eth_dma_tx_descriptor_t *txdesc, uint32_t *seconds, uint32_t *nano_seconds)
+{
+    if (txdesc->TDES0.Own == EMAC_LL_DMADESC_OWNER_DMA || !txdesc->TDES0.TxTimestampStatus) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    if (seconds) {
+        *seconds = txdesc->TimeStampHigh;
+    }
+    if (nano_seconds) {
+        *nano_seconds = subsecond2nanosecond(hal, txdesc->TimeStampLow);
+    }
+    txdesc->TDES0.TxTimestampStatus = 0;
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_ptp_start(emac_hal_context_t *hal, const emac_hal_ptp_config_t *config)
+{
+    uint8_t base_increment;
+
+    // Enable time stamping frame filtering (applicable to receive)
+    emac_ll_ts_ptp_ether_enable(hal->ptp_regs, true);
+    // Process frames with v2 format
+    emac_ll_ptp_v2_proc_enable(hal->ptp_regs, true);
+
+    /* Un-mask the Time stamp trigger interrupt */
+    emac_ll_enable_corresponding_emac_intr(hal->mac_regs, EMAC_LL_CONFIG_ENABLE_MAC_INTR_MASK);
+
+    /* Enable the timestamp feature */
+    emac_ll_ts_enable(hal->ptp_regs, true);
+    /* Set digital or binary rollover */
+    if (config->roll == ETH_PTP_DIGITAL_ROLLOVER) {
+        emac_ll_ts_digital_roll_enable(hal->ptp_regs, true);
+    } else {
+        emac_ll_ts_digital_roll_enable(hal->ptp_regs, false);
+    }
+    /* Set sub second increment based on the required PTP accuracy */
+    if (emac_ll_is_ts_digital_roll_set(hal->ptp_regs)) {
+        /**
+         *   tick(ns)         10^9
+         * ———————————— = ————————————— ==> Increment = tick
+         *   Increment        10^9
+         */
+        base_increment = config->ptp_req_accuracy_ns;
+    } else {
+        /**
+         *   tick(ns)         10^9                       tick * 2^31      tick
+         * ———————————— = ————————————— ==> Increment = ————————————— ≈ —————————
+         *   Increment        2^31                           10^9         0.465
+         */
+        base_increment = config->ptp_req_accuracy_ns / 0.465;
+    }
+    emac_ll_set_ts_sub_second_incre_val(hal->ptp_regs, base_increment);
+    /* Set Update Mode */
+    emac_ll_set_ts_update_method(hal->ptp_regs, config->upd_method);
+    int32_t to = 0;
+    /* If you are using the Fine correction method */
+    if (config->upd_method == ETH_PTP_UPDATE_METHOD_FINE) {
+        /**
+         *           2^32                 2^32                      TsysClk(ns)
+         * Addend = ——————— = —————————————————————————— = 2^32 * ——————————————
+         *           ratio     SysClk(MHz)/PTPaccur(MHz)            Taccur(ns)
+         */
+        uint32_t base_addend = (1ll << 32) * config->ptp_clk_src_period_ns / config->ptp_req_accuracy_ns;
+        emac_ll_set_ts_addend_val(hal->ptp_regs, base_addend);
+        emac_ll_ts_addend_do_update(hal->ptp_regs);
+        while (!emac_ll_is_ts_addend_update_done(hal->ptp_regs) && to < EMAC_PTP_INIT_TIMEOUT_US) {
+            esp_rom_delay_us(1);
+            to++;
+        }
+        if (to >= EMAC_PTP_INIT_TIMEOUT_US) {
+            return ESP_ERR_TIMEOUT;
+        }
+    }
+    /* Initialize timestamp */
+    emac_ll_set_ts_update_second_val(hal->ptp_regs, 0);
+    emac_ll_set_ts_update_sub_second_val(hal->ptp_regs, 0);
+    emac_ll_ts_init_do(hal->ptp_regs);
+    to = 0;
+    while (!emac_ll_is_ts_init_done(hal->ptp_regs) && to < EMAC_PTP_INIT_TIMEOUT_US) {
+        esp_rom_delay_us(1);
+        to++;
+    }
+    if (to >= EMAC_PTP_INIT_TIMEOUT_US) {
+        return ESP_ERR_TIMEOUT;
+    }
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_ptp_stop(emac_hal_context_t *hal)
+{
+    /* Disable the timestamp feature */
+    emac_ll_ts_enable(hal->ptp_regs, false);
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_ptp_adj_inc(emac_hal_context_t *hal, int32_t adj_ppb)
+{
+    if (emac_ll_get_ts_update_method(hal->ptp_regs) != ETH_PTP_UPDATE_METHOD_FINE ||
+        !emac_ll_is_ts_addend_update_done(hal->ptp_regs)) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    /**
+     *       Sysclk(MHz) * ppb    Sysclk * ppb
+     * var = ————————————————— = ———————————————
+     *            10^9                10^9
+     *
+     *          2^32 * PTPClk(MHz)                    2^32 * PTPClk(MHz)
+     * old = —————————————————————————  =>  SysClk = ——————————————————————
+     *             SysClk(MHz)                             old
+     *
+     *        2^32 * PTPClk(MHz)        2^32 * PTPClk(MHz)           2^32 * PTPClk(MHz)
+     * new = ———————————————————— = —————————————————————————— = ———————————————————————————————————— =
+     *        SysClk(MHz) - var                Sysclk * ppb       2^32 * PTPClk(MHz)    (     ppb  )
+     *                               SysClk - ———————————————    ———————————————————— - (1 - ——————)
+     *                                             10^9                old              (     10^9 )
+     *
+     *      old           old * 10^9
+     * = ————————————— = —————————————
+     *        ppb         10^9 - ppb
+     *   1 - ——————
+     *        10^9
+     */
+    static uint32_t addend_base = 0;
+    if (addend_base == 0) {
+        addend_base = emac_ll_get_ts_addend_val(hal->ptp_regs);
+    }
+
+    if (adj_ppb > 5120000) {
+        adj_ppb = 5120000;
+    }
+    if (adj_ppb < -5120000) {
+        adj_ppb = -5120000;
+    }
+    /* calculate the rate by which you want to speed up or slow down the system time increments */
+    int64_t addend_new = (int64_t)addend_base * 1000000000ll;
+    addend_new /= 1000000000ll - adj_ppb;
+
+    emac_ll_set_ts_addend_val(hal->ptp_regs, addend_new);
+    emac_ll_ts_addend_do_update(hal->ptp_regs);
+
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_adj_freq_factor(emac_hal_context_t *hal, double scale_factor)
+{
+    if (emac_ll_get_ts_update_method(hal->ptp_regs) != ETH_PTP_UPDATE_METHOD_FINE ||
+        !emac_ll_is_ts_addend_update_done(hal->ptp_regs)) {
+        return ESP_ERR_INVALID_STATE;
+    }
+
+    uint32_t addend_new = (emac_ll_get_ts_addend_val(hal->ptp_regs) * scale_factor);
+    emac_ll_set_ts_addend_val(hal->ptp_regs, addend_new);
+    emac_ll_ts_addend_do_update(hal->ptp_regs);
+
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_ptp_time_add(emac_hal_context_t *hal, uint32_t off_sec, uint32_t off_nsec, bool sign)
+{
+    emac_ll_set_ts_update_second_val(hal->ptp_regs, off_sec);
+    emac_ll_set_ts_update_sub_second_val(hal->ptp_regs, nanosecond2subsecond(hal, off_nsec));
+    if (sign) {
+        emac_ll_ts_update_time_add(hal->ptp_regs);
+    } else {
+        emac_ll_ts_update_time_sub(hal->ptp_regs);
+    }
+    if (!emac_ll_is_ts_update_time_done(hal->ptp_regs)) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    emac_ll_ts_update_time_do(hal->ptp_regs);
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_ptp_set_sys_time(emac_hal_context_t *hal, uint32_t seconds, uint32_t nano_seconds)
+{
+    emac_ll_set_ts_update_second_val(hal->ptp_regs, seconds);
+    emac_ll_set_ts_update_sub_second_val(hal->ptp_regs, nanosecond2subsecond(hal, nano_seconds));
+
+    if (!emac_ll_is_ts_init_done(hal->ptp_regs)) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    emac_ll_ts_init_do(hal->ptp_regs);
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_ptp_get_sys_time(emac_hal_context_t *hal, uint32_t *seconds, uint32_t *nano_seconds)
+{
+    if (seconds == NULL || nano_seconds == NULL) {
+        return ESP_ERR_INVALID_ARG;
+    }
+    *seconds = emac_ll_get_ts_seconds_val(hal->ptp_regs);
+    *nano_seconds = subsecond2nanosecond(hal, emac_ll_get_ts_sub_seconds_val(hal->ptp_regs));
+    return ESP_OK;
+}
+
+esp_err_t emac_hal_ptp_set_target_time(emac_hal_context_t *hal, uint32_t seconds, uint32_t nano_seconds)
+{
+    emac_ll_set_ts_target_second_val(hal->ptp_regs, seconds);
+    emac_ll_set_ts_target_sub_second_val(hal->ptp_regs, nanosecond2subsecond(hal, nano_seconds));
+    /*  Enable the PTP Time Stamp interrupt trigger */
+    emac_ll_ts_target_int_trig_enable(hal->ptp_regs);
+    return ESP_OK;
+}
+#endif // SOC_EMAC_IEEE1588V2_SUPPORTED
+
+
 void emac_hal_start(emac_hal_context_t *hal)
 {
     /* Enable Ethernet MAC and DMA Interrupt */
diff --git a/components/hal/esp32/include/hal/emac_ll.h b/components/hal/esp32/include/hal/emac_ll.h
index c858552fb27..b6d8b983f81 100644
--- a/components/hal/esp32/include/hal/emac_ll.h
+++ b/components/hal/esp32/include/hal/emac_ll.h
@@ -88,19 +88,6 @@ extern "C" {
 #define EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_3_1 (2)
 #define EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_4_1 (3)
 
-/* PTP register bits */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U                      /* SYNC message (all clock types) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U                  /* FollowUp message (all clock types) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U                  /* DelayReq message (all clock types) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U                 /* DelayResp message (all clock types) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U        /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U          /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
-
-#define EMAC_LL_DMAPTPRXDESC_IPPT_UDP 0x00000001U  /* UDP payload encapsulated in the IP datagram */
-#define EMAC_LL_DMAPTPRXDESC_IPPT_TCP 0x00000002U  /* TCP payload encapsulated in the IP datagram */
-#define EMAC_LL_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
-
 #define EMAC_LL_DMADESC_OWNER_CPU  (0)
 #define EMAC_LL_DMADESC_OWNER_DMA  (1)
 
diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h
index a6f62de1c5b..3f5f64a4dba 100644
--- a/components/hal/esp32/include/hal/gpio_ll.h
+++ b/components/hal/esp32/include/hal/gpio_ll.h
@@ -498,15 +498,15 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t
 {
     if (level) {
         if (gpio_num < 32) {
-            hw->out_w1ts = (1 << gpio_num);
+            hw->out_w1ts = 1 << gpio_num;
         } else {
-            HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1ts, data, (1 << (gpio_num - 32)));
+            hw->out1_w1ts.val = 1 << (gpio_num - 32);
         }
     } else {
         if (gpio_num < 32) {
-            hw->out_w1tc = (1 << gpio_num);
+            hw->out_w1tc = 1 << gpio_num;
         } else {
-            HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1tc, data, (1 << (gpio_num - 32)));
+            hw->out1_w1tc.val = 1 << (gpio_num - 32);
         }
     }
 }
diff --git a/components/hal/esp32/include/hal/i2c_ll.h b/components/hal/esp32/include/hal/i2c_ll.h
index 7e5d3523375..cc47434dee4 100644
--- a/components/hal/esp32/include/hal/i2c_ll.h
+++ b/components/hal/esp32/include/hal/i2c_ll.h
@@ -67,11 +67,13 @@ typedef enum {
 // Get the I2C hardware instance
 #define I2C_LL_GET_HW(i2c_num)        (((i2c_num) == 0) ? &I2C0 : &I2C1)
 #define I2C_LL_MASTER_EVENT_INTR    (I2C_ACK_ERR_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
-#define I2C_LL_SLAVE_EVENT_INTR     (I2C_TRANS_COMPLETE_INT_ENA_M|I2C_TXFIFO_EMPTY_INT_ENA_M|I2C_RX_REC_FULL_INT_ST_M)
+#define I2C_LL_SLAVE_EVENT_INTR     (I2C_TRANS_COMPLETE_INT_ENA_M|I2C_TXFIFO_EMPTY_INT_ENA_M|I2C_RX_REC_FULL_INT_ST_M|I2C_RXFIFO_FULL_INT_ENA)
 #define I2C_LL_SLAVE_RX_EVENT_INTR  (I2C_TRANS_COMPLETE_INT_ENA_M|I2C_RX_REC_FULL_INT_ST_M)
 #define I2C_LL_SLAVE_TX_EVENT_INTR  (I2C_TXFIFO_EMPTY_INT_ENA_M)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2000)  // 2000 is not default value on esp32, but 0 is not good to be default
 
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff) // Not supported on esp32, keep consistent with other chips.
+
 /**
  * @brief  Calculate I2C bus frequency
  *
@@ -808,6 +810,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     // Not supported on esp32
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    // Not supported on esp32
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -835,6 +847,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return clk_cycle_num_per_us * timeout_us;
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->status_reg.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32/include/hal/sdmmc_ll.h b/components/hal/esp32/include/hal/sdmmc_ll.h
index c9ccf8ffe49..0f5a62ea376 100644
--- a/components/hal/esp32/include/hal/sdmmc_ll.h
+++ b/components/hal/esp32/include/hal/sdmmc_ll.h
@@ -408,6 +408,18 @@ static inline bool sdmmc_ll_is_card_write_protected(sdmmc_dev_t *hw, uint32_t sl
     return is_protected;
 }
 
+/**
+ * @brief Switch between 3.3V and 1.8V mode
+ *
+ * @param hw    hardware instance address
+ * @param slot  slot
+ * @param en    enable / disable 1.8V (3.3V on disable)
+ */
+static inline void sdmmc_ll_enable_1v8_mode(sdmmc_dev_t *hw, uint32_t slot, bool en)
+{
+    //for compatibility
+}
+
 /**
  * @brief Enable DDR mode
  *
diff --git a/components/hal/esp32/include/hal/touch_sensor_hal.h b/components/hal/esp32/include/hal/touch_sensor_hal.h
index 5cd1688df12..dd91614088f 100644
--- a/components/hal/esp32/include/hal/touch_sensor_hal.h
+++ b/components/hal/esp32/include/hal/touch_sensor_hal.h
@@ -15,7 +15,7 @@
 #pragma once
 
 #include "hal/touch_sensor_ll.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 
 #include_next "hal/touch_sensor_hal.h"
 
diff --git a/components/hal/esp32/include/hal/touch_sensor_ll.h b/components/hal/esp32/include/hal/touch_sensor_ll.h
index 8d1c945024b..f154f16b0e7 100644
--- a/components/hal/esp32/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32/include/hal/touch_sensor_ll.h
@@ -21,7 +21,7 @@
 #include "soc/sens_struct.h"
 #include "soc/rtc_io_struct.h"
 #include "soc/rtc_cntl_struct.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 
 
 #ifdef __cplusplus
diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h
index 4c66c7bc49d..bb1d1006e34 100644
--- a/components/hal/esp32/include/hal/uart_ll.h
+++ b/components/hal/esp32/include/hal/uart_ll.h
@@ -632,8 +632,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
         hw->flow_conf.sw_flow_con_en = 1;
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_threshold, flow_ctrl->xon_thrd);
         HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_threshold, flow_ctrl->xoff_thrd);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -656,7 +656,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, at_char_num, cmd_char->char_num);
     hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
     hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
     hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
@@ -857,7 +857,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, at_char_num);
 }
 
 /**
@@ -896,7 +896,7 @@ FORCE_INLINE_ATTR IRAM_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
 {
     typeof(hw->status) status;
     status.val = hw->status.val;
-    return ((status.txfifo_cnt == 0) && (status.st_utx_out == 0));
+    return ((HAL_FORCE_READ_U32_REG_FIELD(status, txfifo_cnt) == 0) && (status.st_utx_out == 0));
 }
 
 /**
diff --git a/components/hal/esp32/touch_sensor_hal.c b/components/hal/esp32/touch_sensor_hal.c
index d74a6686ddc..b663dedaa07 100644
--- a/components/hal/esp32/touch_sensor_hal.c
+++ b/components/hal/esp32/touch_sensor_hal.c
@@ -7,7 +7,7 @@
 // The HAL layer for Touch sensor (common part)
 
 #include "hal/touch_sensor_hal.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 
 void touch_hal_init(void)
 {
diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h
index 6906faa7db4..80301ddf706 100644
--- a/components/hal/esp32c2/include/hal/gpio_ll.h
+++ b/components/hal/esp32c2/include/hal/gpio_ll.h
@@ -330,9 +330,9 @@ __attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
-        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+        hw->out_w1ts.val = 1 << gpio_num;
     } else {
-        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+        hw->out_w1tc.val = 1 << gpio_num;
     }
 }
 
diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h
index 157d2e2cb37..2ef71b907f6 100644
--- a/components/hal/esp32c2/include/hal/uart_ll.h
+++ b/components/hal/esp32c2/include/hal/uart_ll.h
@@ -595,8 +595,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
         hw->flow_conf.sw_flow_con_en = 1;
         hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
         hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -619,7 +619,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
@@ -826,7 +826,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, at_char_num);
 }
 
 /**
diff --git a/components/hal/esp32c3/include/hal/clk_gate_ll.h b/components/hal/esp32c3/include/hal/clk_gate_ll.h
index 5765a5e57e1..daf544184b7 100644
--- a/components/hal/esp32c3/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32c3/include/hal/clk_gate_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,8 +35,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
         return SYSTEM_UART1_CLK_EN;
     case PERIPH_I2C0_MODULE:
         return SYSTEM_I2C_EXT0_CLK_EN;
-    case PERIPH_I2S1_MODULE:
-        return SYSTEM_I2S1_CLK_EN;
+    case PERIPH_I2S0_MODULE:
+        return SYSTEM_I2S0_CLK_EN;
     case PERIPH_TIMG0_MODULE:
         return SYSTEM_TIMERGROUP_CLK_EN;
     case PERIPH_TIMG1_MODULE:
@@ -106,8 +106,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         return SYSTEM_UART1_RST;
     case PERIPH_I2C0_MODULE:
         return SYSTEM_I2C_EXT0_RST;
-    case PERIPH_I2S1_MODULE:
-        return SYSTEM_I2S1_RST;
+    case PERIPH_I2S0_MODULE:
+        return SYSTEM_I2S0_RST;
     case PERIPH_TIMG0_MODULE:
         return SYSTEM_TIMERGROUP_RST;
     case PERIPH_TIMG1_MODULE:
diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h
index 798d190970f..cd96a95d93b 100644
--- a/components/hal/esp32c3/include/hal/gpio_ll.h
+++ b/components/hal/esp32c3/include/hal/gpio_ll.h
@@ -339,9 +339,9 @@ __attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
-        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+        hw->out_w1ts.val = 1 << gpio_num;
     } else {
-        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+        hw->out_w1tc.val = 1 << gpio_num;
     }
 }
 
diff --git a/components/hal/esp32c3/include/hal/i2c_ll.h b/components/hal/esp32c3/include/hal/i2c_ll.h
index c74f591c015..326ab5471e4 100644
--- a/components/hal/esp32c3/include/hal/i2c_ll.h
+++ b/components/hal/esp32c3/include/hal/i2c_ll.h
@@ -76,6 +76,8 @@ typedef enum {
 #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT   (9)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2000)  // Approximate value for SCL timeout regs (in us).
 
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff)
+
 /**
  * @brief  Calculate I2C bus frequency
  *         Note that the clock accuracy is affected by the external pull-up resistor,
@@ -916,6 +918,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    dev->scl_stretch_conf.stretch_protect_num = protect_num;
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -944,6 +956,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->sr.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h
index 907324fdd0f..3eecccacd24 100644
--- a/components/hal/esp32c3/include/hal/i2s_ll.h
+++ b/components/hal/esp32c3/include/hal/i2s_ll.h
@@ -47,7 +47,7 @@ extern "C" {
 static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
 {
     (void)i2s_id;
-    SYSTEM.perip_clk_en0.reg_i2s1_clk_en = enable;
+    SYSTEM.perip_clk_en0.reg_i2s0_clk_en = enable;
 }
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
@@ -63,8 +63,8 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
 static inline void i2s_ll_reset_register(int i2s_id)
 {
     (void)i2s_id;
-    SYSTEM.perip_rst_en0.reg_i2s1_rst = 1;
-    SYSTEM.perip_rst_en0.reg_i2s1_rst = 0;
+    SYSTEM.perip_rst_en0.reg_i2s0_rst = 1;
+    SYSTEM.perip_rst_en0.reg_i2s0_rst = 0;
 }
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
@@ -366,7 +366,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 
 /**
  * @brief Configure I2S RX module clock divider
- * @note mclk on ESP32 is shared by both TX and RX channel
+ * @note mclk on ESP32C3 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
  * @param mclk_div The mclk division coefficients
diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h
index fd7aa05de03..b2741137e98 100644
--- a/components/hal/esp32c3/include/hal/uart_ll.h
+++ b/components/hal/esp32c3/include/hal/uart_ll.h
@@ -598,8 +598,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
         hw->flow_conf.sw_flow_con_en = 1;
         hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
         hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -622,7 +622,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
@@ -829,7 +829,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, at_char_num);
 }
 
 /**
diff --git a/components/hal/esp32c5/include/hal/adc_ll.h b/components/hal/esp32c5/include/hal/adc_ll.h
index 7c491440b42..e32a879fffe 100644
--- a/components/hal/esp32c5/include/hal/adc_ll.h
+++ b/components/hal/esp32c5/include/hal/adc_ll.h
@@ -129,7 +129,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 
@@ -566,7 +566,6 @@ static inline void adc_ll_enable_bus_clock(bool enable)
     PCR.saradc_conf.saradc_reg_clk_en = enable;
 }
 
-#if SOC_RCC_IS_INDEPENDENT
 /**
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
@@ -575,7 +574,6 @@ static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
 }
-#endif
 
 /**
  * @brief Reset ADC module
diff --git a/components/hal/esp32c5/include/hal/brownout_ll.h b/components/hal/esp32c5/include/hal/brownout_ll.h
index 09dcb3cb5e9..e103d2639c9 100644
--- a/components/hal/esp32c5/include/hal/brownout_ll.h
+++ b/components/hal/esp32c5/include/hal/brownout_ll.h
@@ -113,8 +113,6 @@ static inline void brownout_ll_ana_reset_enable(bool enable)
     LP_ANA_PERI.fib_enable.val &= ~BROWNOUT_DETECTOR_LL_FIB_ENABLE;
     // then we can enable or disable if we want the BOD mode1 to reset the system
     LP_ANA_PERI.bod_mode1_cntl.bod_mode1_reset_ena = enable;
-    // Disable the power glitch detect.
-    LP_ANA_PERI.fib_enable.val &= ~(BIT2|BIT3|BIT4|BIT5);
 }
 
 /**
diff --git a/components/hal/esp32c5/include/hal/etm_ll.h b/components/hal/esp32c5/include/hal/etm_ll.h
index fa76af9f99b..ebed4861b56 100644
--- a/components/hal/esp32c5/include/hal/etm_ll.h
+++ b/components/hal/esp32c5/include/hal/etm_ll.h
@@ -11,7 +11,6 @@
 #include <stdbool.h>
 #include "hal/assert.h"
 #include "hal/misc.h"
-#include "hal/lp_aon_ll.h"
 #include "soc/soc_etm_struct.h"
 #include "soc/pcr_struct.h"
 
diff --git a/components/hal/esp32c5/include/hal/gpio_ll.h b/components/hal/esp32c5/include/hal/gpio_ll.h
index 0f17f99f069..31894abc028 100644
--- a/components/hal/esp32c5/include/hal/gpio_ll.h
+++ b/components/hal/esp32c5/include/hal/gpio_ll.h
@@ -360,9 +360,9 @@ __attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
-        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+        hw->out_w1ts.val = 1 << gpio_num;
     } else {
-        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+        hw->out_w1tc.val = 1 << gpio_num;
     }
 }
 
diff --git a/components/hal/esp32c5/include/hal/huk_ll.h b/components/hal/esp32c5/include/hal/huk_ll.h
new file mode 100644
index 00000000000..37215ae35ea
--- /dev/null
+++ b/components/hal/esp32c5/include/hal/huk_ll.h
@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use it in application code.
+ ******************************************************************************/
+
+#pragma once
+
+#include "soc/soc_caps.h"
+
+#if SOC_KEY_MANAGER_SUPPORTED
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include "hal/huk_types.h"
+#include "soc/huk_reg.h"
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* @brief Configure the HUK mode */
+static inline void huk_ll_configure_mode(const esp_huk_mode_t huk_mode)
+{
+    REG_SET_FIELD(HUK_CONF_REG, HUK_MODE, huk_mode);
+}
+
+static inline void huk_ll_write_info(const uint8_t *buffer, const size_t size)
+{
+    memcpy((uint8_t *)HUK_INFO_MEM, buffer, size);
+}
+
+static inline void huk_ll_read_info(uint8_t *buffer, const size_t size)
+{
+    memcpy(buffer, (uint8_t *)HUK_INFO_MEM, size);
+}
+
+/* @brief Start the HUK at IDLE state */
+static inline void huk_ll_start(void)
+{
+    REG_SET_FIELD(HUK_START_REG, HUK_START, 1);
+}
+
+/* @brief Continue HUK operation at LOAD/GAIN state */
+static inline void huk_ll_continue(void)
+{
+    REG_SET_FIELD(HUK_START_REG, HUK_CONTINUE, 1);
+}
+
+/* @bried Enable or Disable the HUK interrupts */
+static inline void huk_ll_configure_interrupt(const esp_huk_interrupt_type_t intr, const bool en)
+{
+    switch(intr) {
+        case ESP_HUK_INT_PREP_DONE:
+                REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PREP_DONE_INT_ENA, en);
+        case ESP_HUK_INT_PROC_DONE:
+                REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PROC_DONE_INT_ENA, en);
+        case ESP_HUK_INT_POST_DONE:
+                REG_SET_FIELD(HUK_INT_ENA_REG, HUK_POST_DONE_INT_ENA, en);
+        default:
+            return;
+    }
+}
+
+/* @bried Clear the HUK interrupts */
+static inline void huk_ll_clear_int(const esp_huk_interrupt_type_t intr)
+{
+    switch(intr) {
+        case ESP_HUK_INT_PREP_DONE:
+            REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PREP_DONE_INT_CLR, 1);
+        case ESP_HUK_INT_PROC_DONE:
+            REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PROC_DONE_INT_CLR, 1);
+        case ESP_HUK_INT_POST_DONE:
+            REG_SET_FIELD(HUK_INT_CLR_REG, HUK_POST_DONE_INT_CLR, 1);
+        default:
+            return;
+    }
+}
+
+/**
+ * @brief Read state of Hardware Unique Key Generator
+ *
+ * @return esp_huk_state_t
+ */
+static inline esp_huk_state_t huk_ll_get_state(void)
+{
+    return (esp_huk_state_t) REG_GET_FIELD(HUK_STATE_REG, HUK_STATE);
+}
+
+/**
+ * @brief Get the HUK generation status
+ */
+static inline esp_huk_gen_status_t huk_ll_get_gen_status(void)
+{
+    return (esp_huk_gen_status_t) REG_GET_FIELD(HUK_STATUS_REG, HUK_STATUS);
+}
+
+/**
+ * @brief Read the HUK date information
+ */
+static inline uint32_t huk_ll_get_date_info(void)
+{
+    // Only the least significant 28 bits have desired information
+    return (uint32_t)(0x0FFFFFFF & REG_READ(HUK_DATE_REG));
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/components/hal/esp32c5/include/hal/i2c_ll.h b/components/hal/esp32c5/include/hal/i2c_ll.h
index ba2dd6610c6..1d86684dbe0 100644
--- a/components/hal/esp32c5/include/hal/i2c_ll.h
+++ b/components/hal/esp32c5/include/hal/i2c_ll.h
@@ -78,6 +78,8 @@ typedef enum {
 #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT   (9)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2500)  // Approximate value for SCL timeout regs (in us).
 
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff)
+
 // Record for Pins usage logs
 
 #define LP_I2C_SCL_PIN_ERR_LOG   "SCL pin can only be configured as GPIO#7"
@@ -954,6 +956,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    dev->scl_stretch_conf.stretch_protect_num = protect_num;
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -982,6 +994,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->sr.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32c5/include/hal/i2s_ll.h b/components/hal/esp32c5/include/hal/i2s_ll.h
index 47e096b3538..59c2f96ed6e 100644
--- a/components/hal/esp32c5/include/hal/i2s_ll.h
+++ b/components/hal/esp32c5/include/hal/i2s_ll.h
@@ -13,7 +13,6 @@
 
 #pragma once
 #include <stdbool.h>
-#include "sdkconfig.h"
 #include "hal/misc.h"
 #include "hal/assert.h"
 #include "soc/i2s_periph.h"
@@ -154,7 +153,7 @@ static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw)
 static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw)
 {
     (void)hw;
-    PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0;  // TODO: need check
+    PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0;
 }
 
 /**
@@ -398,7 +397,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 
 /**
  * @brief Configure I2S RX module clock divider
- * @note mclk on ESP32 is shared by both TX and RX channel
+ * @note mclk on ESP32C5 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
  * @param mclk_div The mclk division coefficients
@@ -945,7 +944,7 @@ static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
  */
 static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm_enable)
 {
-    // Due to the lack of `PDM to PCM` module on ESP32-H2, PDM RX is not available
+    // Due to the lack of `PDM to PCM` module on ESP32-C5, PDM RX is not available
     HAL_ASSERT(!pdm_enable);
     hw->rx_conf.rx_pdm_en = 0;
     hw->rx_conf.rx_tdm_en = 1;
diff --git a/components/hal/esp32c5/include/hal/key_mgr_ll.h b/components/hal/esp32c5/include/hal/key_mgr_ll.h
new file mode 100644
index 00000000000..f46c7c2e4cd
--- /dev/null
+++ b/components/hal/esp32c5/include/hal/key_mgr_ll.h
@@ -0,0 +1,359 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use it in application code.
+ ******************************************************************************/
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include "hal/assert.h"
+#include "hal/key_mgr_types.h"
+#include "soc/keymng_reg.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Read state of Key Manager
+ *
+ * @return esp_key_mgr_state_t
+ */
+static inline esp_key_mgr_state_t key_mgr_ll_get_state(void)
+{
+    return (esp_key_mgr_state_t) REG_GET_FIELD(KEYMNG_STATE_REG, KEYMNG_STATE);
+}
+
+/**
+ * @brief Enable the bus clock for Key Manager peripheral
+ * Note: Please use key_mgr_ll_enable_bus_clock which requires the critical section
+ *       and do not use _key_mgr_ll_enable_bus_clock
+ * @param true to enable, false to disable
+ */
+static inline void _key_mgr_ll_enable_bus_clock(bool enable)
+{
+    // Set the force power down bit to 0 to enable key manager
+    PCR.km_pd_ctrl.km_mem_force_pd = 0;
+    // Enable key manager clock
+    PCR.km_conf.km_clk_en = 1;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define key_mgr_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Enable the peripheral clock for Key Manager
+ *
+ * Note: Please use key_mgr_ll_enable_peripheral_clock which requires the critical section
+ *       and do not use _key_mgr_ll_enable_peripheral_clock
+ * @param true to enable, false to disable
+ */
+static inline void _key_mgr_ll_enable_peripheral_clock(bool enable)
+{
+    ;    /* Nothing to do here, Kept for compatibility with other SoC */
+}
+
+#define key_mgr_ll_enable_peripheral_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_enable_peripheral_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the Key Manager peripheral
+ * Note: Please use key_mgr_ll_reset_register which requires the critical section
+ *       and do not use _key_mgr_ll_reset_register
+ */
+static inline void _key_mgr_ll_reset_register(void)
+{
+    PCR.km_conf.km_rst_en = 1;
+    PCR.km_conf.km_rst_en = 0;
+    // Wait for key manager to be ready
+    while (!PCR.km_conf.km_ready) {
+    };
+
+    while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
+    };
+
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define key_mgr_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_reset_register(__VA_ARGS__)
+
+/* @brief Start the key manager at IDLE state */
+static inline void key_mgr_ll_start(void)
+{
+    REG_SET_BIT(KEYMNG_START_REG, KEYMNG_START);
+}
+
+/* @brief Continue key manager operation at LOAD/GAIN state */
+static inline void key_mgr_ll_continue(void)
+{
+    REG_SET_BIT(KEYMNG_START_REG, KEYMNG_CONTINUE);
+}
+
+/* @brief Enable or Disable the KEY_MGR interrupts */
+static inline void key_mgr_ll_configure_interrupt(const esp_key_mgr_interrupt_type_t intr, bool en)
+{
+    switch(intr) {
+        case ESP_KEY_MGR_INT_PREP_DONE:
+            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PREP_DONE_INT_ENA, en);
+            break;
+        case ESP_KEY_MGR_INT_PROC_DONE:
+            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PROC_DONE_INT_ENA, en);
+            break;
+        case ESP_KEY_MGR_INT_POST_DONE:
+            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_POST_DONE_INT_ENA, en);
+            break;
+        default:
+            return;
+    }
+}
+
+/* @brief Clear the KEY_MGR interrupts */
+static inline void key_mgr_ll_clear_int(const esp_key_mgr_interrupt_type_t intr)
+{
+    switch(intr) {
+        case ESP_KEY_MGR_INT_PREP_DONE:
+            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PREP_DONE_INT_CLR, 1);
+            break;
+        case ESP_KEY_MGR_INT_PROC_DONE:
+            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PROC_DONE_INT_CLR, 1);
+            break;
+        case ESP_KEY_MGR_INT_POST_DONE:
+            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_POST_DONE_INT_CLR, 1);
+            break;
+        default:
+            return;
+    }
+}
+
+/**
+ * @brief Set the key manager to use the software provided init key
+ */
+static inline void key_mgr_ll_use_sw_init_key(void)
+{
+    REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_SW_INIT_KEY);
+}
+
+/**
+ * @brief Configure the key manager key usage policy for a particular key type
+ *
+ */
+static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_usage_t key_usage)
+{
+    switch (key_type) {
+        case ESP_KEY_MGR_ECDSA_KEY:
+            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
+            } else {
+                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
+            }
+            break;
+        case ESP_KEY_MGR_XTS_AES_128_KEY:
+        case ESP_KEY_MGR_XTS_AES_256_KEY:
+            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+            } else {
+                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+            }
+            break;
+
+        default:
+            HAL_ASSERT(false && "Unsupported mode");
+            return;
+    }
+}
+
+static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_type_t key_type)
+{
+    switch (key_type) {
+        case ESP_KEY_MGR_ECDSA_KEY:
+            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
+            break;
+
+        case ESP_KEY_MGR_XTS_AES_128_KEY:
+        case ESP_KEY_MGR_XTS_AES_256_KEY:
+            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
+            break;
+
+        default:
+            HAL_ASSERT(false && "Unsupported mode");
+            return ESP_KEY_MGR_USAGE_INVALID;
+    }
+    return ESP_KEY_MGR_USAGE_INVALID;
+}
+
+/**
+ * @brief Set the lock for the use_sw_init_key_reg
+ *        After this lock has been set,
+ *        The Key manager configuration about the use of software init key cannot be changed
+ */
+static inline void key_mgr_ll_lock_use_sw_init_key_reg(void)
+{
+    REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_SW_INIT_KEY_LOCK);
+}
+
+/**
+ * @brief Set the lock for the use_sw_init_key_reg
+ *        After this lock has been set,
+ *        The Key manager configuration about whether to use a particular key from efuse or key manager cannot be changed.
+ */
+static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_type)
+{
+    switch(key_type) {
+        case ESP_KEY_MGR_ECDSA_KEY:
+            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
+            break;
+        case ESP_KEY_MGR_XTS_AES_128_KEY:
+        case ESP_KEY_MGR_XTS_AES_256_KEY:
+            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
+            break;
+        default:
+            HAL_ASSERT(false && "Unsupported mode");
+            return;
+    }
+}
+
+/* @brief Configure the key purpose to be used by the Key Manager for key generator operation */
+static inline void key_mgr_ll_set_key_purpose(const esp_key_mgr_key_purpose_t key_purpose)
+{
+    REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, key_purpose);
+}
+
+/**
+ * @brief Configure the mode which is used by the Key Manager for the generator key deployment process
+ */
+static inline void key_mgr_ll_set_key_generator_mode(const esp_key_mgr_key_generator_mode_t mode)
+{
+    REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KGEN_MODE, mode);
+}
+
+/**
+ * @brief Read the key manager process result
+ * @return  1 for Success
+ *          0 for failure
+ */
+static inline bool key_mgr_ll_is_result_success(void)
+{
+    return REG_GET_FIELD(KEYMNG_RESULT_REG, KEYMNG_PROC_RESULT);
+}
+
+/**
+ * @brief Check if the deployed key is valid or not
+ * @return  1 for Success
+ *          0 for failure
+ */
+static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type)
+{
+    switch (key_type) {
+
+        case ESP_KEY_MGR_ECDSA_KEY:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_VLD);
+            break;
+
+        case ESP_KEY_MGR_XTS_AES_128_KEY:
+        case ESP_KEY_MGR_XTS_AES_256_KEY:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
+            break;
+
+        default:
+            HAL_ASSERT(false && "Unsupported mode");
+            return 0;
+    }
+}
+
+/*
+ * @brief Write the SW init key in the key manager registers
+ *
+ * @input
+ * sw_init_key_buf      Init key buffer, this should be a readable buffer of data_len size which should contain the sw init key. The buffer must be 32 bit aligned
+ * data_len             Length of the init key buffer
+ */
+static inline void key_mgr_ll_write_sw_init_key(const uint8_t *sw_init_key_buf, const size_t data_len)
+{
+    memcpy((uint8_t *)KEYMNG_SW_INIT_KEY_MEM, sw_init_key_buf, data_len);
+}
+
+/*
+ * @brief Write the Assist info in the key manager registers
+ *
+ * @input
+ * assist_info_buf      Assist info buffer, this should be a readable buffer of data_len size which should contain the assist info.  The buffer must be 32 bit aligned
+ * data_len             Length of the assist info buffer
+ */
+static inline void key_mgr_ll_write_assist_info(const uint8_t *assist_info_buf, const size_t data_len)
+{
+    memcpy((uint8_t *)KEYMNG_ASSIST_INFO_MEM, assist_info_buf, data_len);
+}
+
+/*
+ * @brief Read the Assist info from the key manager registers
+ *
+ * @input
+ * assist_info_buf      Assist info buffer, this should be a writable buffer of size KEY_MGR_ASSIST_INFO_LEN. The buffer must be 32 bit aligned
+ */
+static inline void key_mgr_ll_read_assist_info( uint8_t *assist_info_buf)
+{
+    memcpy(assist_info_buf, (uint8_t *)KEYMNG_ASSIST_INFO_MEM, KEY_MGR_ASSIST_INFO_LEN);
+}
+
+/*
+ * @brief Write the Public info in the key manager registers
+ * @input
+ * public_info_buf      Public info buffer, this should be a readable buffer of data_len size which should contain the public info.  The buffer must be 32 bit aligned
+ * data_len             Length of the public info buffer
+ */
+static inline void key_mgr_ll_write_public_info(const uint8_t *public_info_buf, const size_t data_len)
+{
+    memcpy((uint8_t *)KEYMNG_PUBLIC_INFO_MEM, public_info_buf, data_len);
+}
+
+/*
+ * @brief Read the Public info in the key manager registers
+ * @input
+ * public_info_buf      Public info buffer, this should be a writable buffer of read_len,  The buffer must be 32 bit aligned
+ * read_len             Length of the public info buffer
+ */
+static inline void key_mgr_ll_read_public_info(uint8_t *public_info_buf, const size_t read_len)
+{
+    memcpy(public_info_buf, (uint8_t *)KEYMNG_PUBLIC_INFO_MEM, read_len);
+}
+
+static inline bool key_mgr_ll_is_huk_valid(void)
+{
+    return REG_GET_FIELD(KEYMNG_HUK_VLD_REG, KEYMNG_HUK_VALID);
+}
+
+/* @brief Set the XTS-AES (Flash Encryption) key length for the Key Manager */
+static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_xts_aes_key_len_t key_len)
+{
+    REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN, key_len);
+}
+
+/* @brief Get the XTS-AES (Flash Encryption) key length for the Key Manager */
+static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(void)
+{
+    return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN);
+}
+
+/**
+ * @brief Read the Key Manager date information
+ */
+static inline uint32_t key_mgr_ll_get_date_info(void)
+{
+    // Only the least significant 28 bits have desired information
+    return (uint32_t)(0x0FFFFFFF & REG_READ(KEYMNG_DATE_REG));
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h
index 9a01d99830e..2d4416657fb 100644
--- a/components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h
+++ b/components/hal/esp32c5/include/hal/mspi_timing_tuning_ll.h
@@ -63,6 +63,17 @@ static inline __attribute__((always_inline)) void mspi_ll_enable_bus_clock(bool
     PCR.mspi_conf.mspi_clk_en = enable;
 }
 
+/**
+ * Reset the MSPI clock
+ */
+static inline __attribute__((always_inline)) void _mspi_timing_ll_reset_mspi(void)
+{
+    PCR.mspi_clk_conf.mspi_axi_rst_en = 1;
+    PCR.mspi_clk_conf.mspi_axi_rst_en = 0;
+    // Wait for mspi to be ready
+    while (!PCR.mspi_conf.mspi_ready) {
+    };
+}
 
 #ifdef __cplusplus
 }
diff --git a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h
index 81db4b07fc1..98d65aed033 100644
--- a/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h
+++ b/components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h
@@ -21,20 +21,36 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
     MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
 /**
  * @brief Force enable analog I2C master clock
  */
diff --git a/components/hal/esp32c5/include/hal/rmt_ll.h b/components/hal/esp32c5/include/hal/rmt_ll.h
index 053e27d0e9b..0e54a0b3786 100644
--- a/components/hal/esp32c5/include/hal/rmt_ll.h
+++ b/components/hal/esp32c5/include/hal/rmt_ll.h
@@ -38,8 +38,6 @@ extern "C" {
 #define RMT_LL_MAX_FILTER_VALUE           255
 #define RMT_LL_MAX_IDLE_VALUE             32767
 
-#define RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id) (SLEEP_RETENTION_MODULE_RMT0)
-
 typedef enum {
     RMT_LL_MEM_OWNER_SW = 0,
     RMT_LL_MEM_OWNER_HW = 1,
diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h
index 7bc6606bc98..2b06e0fe47d 100644
--- a/components/hal/esp32c5/include/hal/uart_ll.h
+++ b/components/hal/esp32c5/include/hal/uart_ll.h
@@ -61,10 +61,6 @@ extern "C" {
 #define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix)  \
     (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
 
-// UART sleep retention module
-#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
-                                                     (uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : -1)
-
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1 << 0),
@@ -615,7 +611,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 {
-    return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
 }
 
 /**
@@ -628,7 +624,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 {
     uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN;
-    uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    uint32_t txfifo_len = HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
     return (total_fifo_len - txfifo_len);
 }
 
@@ -704,7 +700,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_
  */
 FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
 {
-    hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw));
 }
 
 /**
@@ -718,7 +714,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full
  */
 FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
 {
-    hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw));
 }
 
 /**
@@ -782,7 +778,7 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
 {
     //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
     if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
-        hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw));
         hw->hwfc_conf_sync.rx_flow_en = 1;
     } else {
         hw->hwfc_conf_sync.rx_flow_en = 0;
@@ -828,10 +824,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
     if (sw_flow_ctrl_en) {
         hw->swfc_conf0_sync.xonoff_del = 1;
         hw->swfc_conf0_sync.sw_flow_con_en = 1;
-        hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
-        hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->swfc_conf0_sync.sw_flow_con_en = 0;
         hw->swfc_conf0_sync.xonoff_del = 0;
@@ -855,7 +851,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
@@ -1092,7 +1088,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num);
 }
 
 /**
@@ -1129,7 +1125,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length
  */
 FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
 {
-    return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
+    return (((HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
 }
 
 /**
diff --git a/components/hal/esp32c5/modem_clock_hal.c b/components/hal/esp32c5/modem_clock_hal.c
index 0c6370faa08..554aaa94735 100644
--- a/components/hal/esp32c5/modem_clock_hal.c
+++ b/components/hal/esp32c5/modem_clock_hal.c
@@ -101,12 +101,9 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c
     return bitmap;
 }
 
-void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
 {
     if (enable) {
-        modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
-        modem_syscon_ll_enable_fe_dac_clock(hal->syscon_dev, enable);
-        modem_syscon_ll_enable_fe_pwdet_clock(hal->syscon_dev, enable);
         modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
         modem_syscon_ll_enable_fe_80m_clock(hal->syscon_dev, enable);
     }
@@ -116,6 +113,9 @@ void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_con
 {
     if (enable) {
         modem_syscon_ll_enable_fe_160m_clock(hal->syscon_dev, enable);
+        modem_syscon_ll_enable_fe_dac_clock(hal->syscon_dev, enable);
+        modem_syscon_ll_enable_fe_pwdet_clock(hal->syscon_dev, enable);
+        modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
     }
 }
 
diff --git a/components/hal/esp32c6/include/hal/adc_ll.h b/components/hal/esp32c6/include/hal/adc_ll.h
index 439f4c0514b..0b09c3cd867 100644
--- a/components/hal/esp32c6/include/hal/adc_ll.h
+++ b/components/hal/esp32c6/include/hal/adc_ll.h
@@ -128,7 +128,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 
@@ -565,7 +565,6 @@ static inline void adc_ll_enable_bus_clock(bool enable)
     PCR.saradc_conf.saradc_reg_clk_en = enable;
 }
 
-#if SOC_RCC_IS_INDEPENDENT
 /**
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
@@ -574,7 +573,6 @@ static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
 }
-#endif
 
 /**
  * @brief Reset ADC module
diff --git a/components/hal/esp32c6/include/hal/clk_gate_ll.h b/components/hal/esp32c6/include/hal/clk_gate_ll.h
index ecac26fd457..eaff2e37760 100644
--- a/components/hal/esp32c6/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32c6/include/hal/clk_gate_ll.h
@@ -36,7 +36,7 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
             return PCR_UART1_CLK_EN;
         case PERIPH_I2C0_MODULE:
             return PCR_I2C_CLK_EN;
-        case PERIPH_I2S1_MODULE:
+        case PERIPH_I2S0_MODULE:
             return PCR_I2S_CLK_EN;
         case PERIPH_TIMG0_MODULE:
             return PCR_TG0_CLK_EN;
@@ -104,7 +104,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
             return PCR_UART1_RST_EN;
         case PERIPH_I2C0_MODULE:
             return PCR_I2C_RST_EN;
-        case PERIPH_I2S1_MODULE:
+        case PERIPH_I2S0_MODULE:
             return PCR_I2S_RST_EN;
         case PERIPH_TIMG0_MODULE:
             return PCR_TG0_RST_EN;
@@ -183,7 +183,7 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
             return PCR_UART1_CONF_REG;
         case PERIPH_I2C0_MODULE:
             return PCR_I2C_CONF_REG;
-        case PERIPH_I2S1_MODULE:
+        case PERIPH_I2S0_MODULE:
             return PCR_I2S_CONF_REG;
         case PERIPH_TIMG0_MODULE:
             return PCR_TIMERGROUP0_CONF_REG;
@@ -249,7 +249,7 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
             return PCR_UART1_CONF_REG;
         case PERIPH_I2C0_MODULE:
             return PCR_I2C_CONF_REG;
-        case PERIPH_I2S1_MODULE:
+        case PERIPH_I2S0_MODULE:
             return PCR_I2S_CONF_REG;
         case PERIPH_TIMG0_MODULE:
             return PCR_TIMERGROUP0_CONF_REG;
diff --git a/components/hal/esp32c6/include/hal/etm_ll.h b/components/hal/esp32c6/include/hal/etm_ll.h
index 9d7079619d0..e77bfeec5f9 100644
--- a/components/hal/esp32c6/include/hal/etm_ll.h
+++ b/components/hal/esp32c6/include/hal/etm_ll.h
@@ -11,7 +11,6 @@
 #include <stdbool.h>
 #include "hal/assert.h"
 #include "hal/misc.h"
-#include "hal/lp_aon_ll.h"
 #include "soc/soc_etm_struct.h"
 #include "soc/pcr_struct.h"
 
diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/hal/esp32c6/include/hal/gpio_ll.h
index 7871b705120..2409c412e06 100644
--- a/components/hal/esp32c6/include/hal/gpio_ll.h
+++ b/components/hal/esp32c6/include/hal/gpio_ll.h
@@ -332,9 +332,9 @@ __attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
-        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+        hw->out_w1ts.val = 1 << gpio_num;
     } else {
-        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+        hw->out_w1tc.val = 1 << gpio_num;
     }
 }
 
diff --git a/components/hal/esp32c6/include/hal/i2c_ll.h b/components/hal/esp32c6/include/hal/i2c_ll.h
index e8aaa77828d..393909065fd 100644
--- a/components/hal/esp32c6/include/hal/i2c_ll.h
+++ b/components/hal/esp32c6/include/hal/i2c_ll.h
@@ -77,6 +77,8 @@ typedef enum {
 #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT   (9)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2000)  // Approximate value for SCL timeout regs (in us).
 
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff)
+
 // Record for Pins usage logs
 
 #define LP_I2C_SCL_PIN_ERR_LOG   "SCL pin can only be configured as GPIO#7"
@@ -85,9 +87,6 @@ typedef enum {
 #define LP_I2C_SDA_IOMUX_PAD 6
 #define LP_I2C_SCL_IOMUX_PAD 7
 
-// I2C sleep retention module
-#define I2C_SLEEP_RETENTION_MODULE(i2c_num) (SLEEP_RETENTION_MODULE_I2C0)
-
 /**
  * @brief  Calculate I2C bus frequency
  *         Note that the clock accuracy is affected by the external pull-up resistor,
@@ -959,6 +958,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    dev->scl_stretch_conf.stretch_protect_num = protect_num;
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -987,6 +996,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->sr.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32c6/include/hal/i2s_ll.h b/components/hal/esp32c6/include/hal/i2s_ll.h
index 0c0a99a852b..f38ec506c39 100644
--- a/components/hal/esp32c6/include/hal/i2s_ll.h
+++ b/components/hal/esp32c6/include/hal/i2s_ll.h
@@ -388,7 +388,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 
 /**
  * @brief Configure I2S RX module clock divider
- * @note mclk on ESP32 is shared by both TX and RX channel
+ * @note mclk on ESP32C6 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
  * @param mclk_div The mclk division coefficients
diff --git a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h
index 984ef041261..975fa89577d 100644
--- a/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h
+++ b/components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h
@@ -19,20 +19,36 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
     MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
 /**
  * @brief Force enable analog I2C master clock
  */
diff --git a/components/hal/esp32c6/include/hal/rmt_ll.h b/components/hal/esp32c6/include/hal/rmt_ll.h
index 247d63e5fe8..9fdc75764e0 100644
--- a/components/hal/esp32c6/include/hal/rmt_ll.h
+++ b/components/hal/esp32c6/include/hal/rmt_ll.h
@@ -38,8 +38,6 @@ extern "C" {
 #define RMT_LL_MAX_FILTER_VALUE           255
 #define RMT_LL_MAX_IDLE_VALUE             32767
 
-#define RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id) (SLEEP_RETENTION_MODULE_RMT0)
-
 typedef enum {
     RMT_LL_MEM_OWNER_SW = 0,
     RMT_LL_MEM_OWNER_HW = 1,
diff --git a/components/hal/esp32c6/include/hal/rtc_io_ll.h b/components/hal/esp32c6/include/hal/rtc_io_ll.h
index 0cd64df36d5..6fcac4cd406 100644
--- a/components/hal/esp32c6/include/hal/rtc_io_ll.h
+++ b/components/hal/esp32c6/include/hal/rtc_io_ll.h
@@ -309,6 +309,14 @@ static inline void rtcio_ll_wakeup_enable(int rtcio_num, rtcio_ll_wake_type_t ty
 {
     LP_IO.pin[rtcio_num].wakeup_enable = 1;
     LP_IO.pin[rtcio_num].int_type = type;
+
+    /* Work around for HW issue,
+       need to also enable this clk, otherwise it will
+       not trigger a wake-up on the ULP. This is not needed
+       for triggering a wakeup on HP CPU, but always setting this
+       has no side-effects.
+    */
+    LP_IO.date.clk_en = 1;
 }
 
 /**
diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h
index 653fb37bbc1..f382ff6bb3b 100644
--- a/components/hal/esp32c6/include/hal/uart_ll.h
+++ b/components/hal/esp32c6/include/hal/uart_ll.h
@@ -61,10 +61,6 @@ extern "C" {
 #define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix)  \
     (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
 
-// UART sleep retention module
-#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
-                                                     (uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : -1)
-
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1 << 0),
@@ -596,7 +592,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 {
-    return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
 }
 
 /**
@@ -609,7 +605,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 {
     uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN;
-    uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    uint32_t txfifo_len = HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
     return (total_fifo_len - txfifo_len);
 }
 
@@ -685,7 +681,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_
  */
 FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
 {
-    hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw));
 }
 
 /**
@@ -699,7 +695,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full
  */
 FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
 {
-    hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw));
 }
 
 /**
@@ -763,7 +759,7 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
 {
     //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
     if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
-        hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw));
         hw->hwfc_conf_sync.rx_flow_en = 1;
     } else {
         hw->hwfc_conf_sync.rx_flow_en = 0;
@@ -809,10 +805,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
     if (sw_flow_ctrl_en) {
         hw->swfc_conf0_sync.xonoff_del = 1;
         hw->swfc_conf0_sync.sw_flow_con_en = 1;
-        hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
-        hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_character, flow_ctrl->xoff_char);
     } else {
         hw->swfc_conf0_sync.sw_flow_con_en = 0;
         hw->swfc_conf0_sync.xonoff_del = 0;
@@ -836,7 +832,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
@@ -1073,7 +1069,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num);
 }
 
 /**
@@ -1110,7 +1106,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length
  */
 FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
 {
-    return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
+    return (((HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
 }
 
 /**
diff --git a/components/hal/esp32c6/modem_clock_hal.c b/components/hal/esp32c6/modem_clock_hal.c
index ed242febec4..7901b829dab 100644
--- a/components/hal/esp32c6/modem_clock_hal.c
+++ b/components/hal/esp32c6/modem_clock_hal.c
@@ -101,7 +101,7 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c
     return bitmap;
 }
 
-void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
 {
     if (enable) {
         modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
diff --git a/components/hal/esp32c61/include/hal/adc_ll.h b/components/hal/esp32c61/include/hal/adc_ll.h
new file mode 100644
index 00000000000..5a57f347ad1
--- /dev/null
+++ b/components/hal/esp32c61/include/hal/adc_ll.h
@@ -0,0 +1,800 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include "esp_attr.h"
+
+#include "soc/adc_periph.h"
+#include "soc/apb_saradc_struct.h"
+#include "soc/apb_saradc_reg.h"
+#include "soc/pmu_reg.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/pcr_struct.h"
+#include "hal/misc.h"
+#include "hal/assert.h"
+#include "hal/adc_types.h"
+#include "hal/adc_types_private.h"
+#include "hal/regi2c_ctrl.h"
+#include "hal/sar_ctrl_ll.h"
+
+#include "soc/regi2c_saradc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ADC_LL_EVENT_ADC1_ONESHOT_DONE    BIT(31)
+#define ADC_LL_EVENT_ADC2_ONESHOT_DONE    BIT(30)
+
+#define ADC_LL_THRES_ALL_INTR_ST_M  (SARADC_THRES0_HIGH_INT_ST_M | \
+                                     SARADC_THRES1_HIGH_INT_ST_M | \
+                                     SARADC_THRES0_LOW_INT_ST_M  | \
+                                     SARADC_THRES1_LOW_INT_ST_M)
+
+#define ADC_LL_GET_HIGH_THRES_MASK(monitor_id)    ((monitor_id == 0) ? SARADC_THRES0_HIGH_INT_ST_M : SARADC_THRES1_HIGH_INT_ST_M)
+#define ADC_LL_GET_LOW_THRES_MASK(monitor_id)     ((monitor_id == 0) ? SARADC_THRES0_LOW_INT_ST_M : SARADC_THRES1_LOW_INT_ST_M)
+
+/*---------------------------------------------------------------
+                    Oneshot
+---------------------------------------------------------------*/
+#define ADC_LL_DATA_INVERT_DEFAULT(PERIPH_NUM)         (0)
+#define ADC_LL_DELAY_CYCLE_AFTER_DONE_SIGNAL           (0)
+
+/*---------------------------------------------------------------
+                    DMA
+---------------------------------------------------------------*/
+#define ADC_LL_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM)    (0)
+#define ADC_LL_FSM_RSTB_WAIT_DEFAULT                   (8)
+#define ADC_LL_FSM_START_WAIT_DEFAULT                  (5)
+#define ADC_LL_FSM_STANDBY_WAIT_DEFAULT                (100)
+#define ADC_LL_SAMPLE_CYCLE_DEFAULT                    (2)
+#define ADC_LL_DIGI_SAR_CLK_DIV_DEFAULT                (1)
+#define ADC_LL_CLKM_DIV_NUM_DEFAULT       15
+#define ADC_LL_CLKM_DIV_B_DEFAULT         1
+#define ADC_LL_CLKM_DIV_A_DEFAULT         0
+#define ADC_LL_DEFAULT_CONV_LIMIT_EN      0
+#define ADC_LL_DEFAULT_CONV_LIMIT_NUM     10
+
+#define ADC_LL_POWER_MANAGE_SUPPORTED     1 //ESP32C61 supported to manage power mode
+/*---------------------------------------------------------------
+                    PWDET (Power Detect)
+---------------------------------------------------------------*/
+#define ADC_LL_PWDET_CCT_DEFAULT                       (4)
+
+typedef enum {
+    ADC_LL_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM,   /*!< ADC XPD controlled by FSM. Used for polling mode */
+    ADC_LL_POWER_SW_ON = SAR_CTRL_LL_POWER_ON,    /*!< ADC XPD controlled by SW. power on. Used for DMA mode */
+    ADC_LL_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF,   /*!< ADC XPD controlled by SW. power off. */
+} adc_ll_power_t;
+
+typedef enum {
+    ADC_LL_CTRL_DIG = 0,    ///< ADC digital controller
+} adc_ll_controller_t;
+
+/**
+ * @brief ADC digital controller (DMA mode) work mode.
+ *
+ * @note  The conversion mode affects the sampling frequency:
+ *        ESP32C61 only support ONLY_ADC1 mode
+ *        SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
+ */
+typedef enum {
+    ADC_LL_DIGI_CONV_ONLY_ADC1 = 0,     // Only use ADC1 for conversion
+} adc_ll_digi_convert_mode_t;
+
+typedef struct  {
+    union {
+        struct {
+            uint8_t atten:      2;
+            uint8_t channel:    3;
+            uint8_t unit:       1;
+            uint8_t reserved:   2;
+        };
+        uint8_t val;
+    };
+} __attribute__((packed)) adc_ll_digi_pattern_table_t;
+
+/*---------------------------------------------------------------
+                    Digital controller setting
+---------------------------------------------------------------*/
+
+/**
+ * Set adc fsm interval parameter for digital controller. These values are fixed for same platforms.
+ *
+ * @param rst_wait cycles between DIG ADC controller reset ADC sensor and start ADC sensor.
+ * @param start_wait Delay time after open xpd.
+ * @param standby_wait Delay time to close xpd.
+ */
+static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
+{
+    // Internal FSM reset wait time
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_fsm_wait, saradc_rstb_wait, rst_wait);
+    // Internal FSM start wait time
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_fsm_wait, saradc_xpd_wait, start_wait);
+    // Internal FSM standby wait time
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_fsm_wait, saradc_standby_wait, standby_wait);
+}
+
+/**
+ * Set adc sample cycle for digital controller.
+ *
+ * @note Normally, please use default value.
+ * @param sample_cycle Cycles between DIG ADC controller start ADC sensor and beginning to receive data from sensor.
+ *                     Range: 2 ~ 0xFF.
+ */
+static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
+{
+    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
+}
+
+/**
+ * Set SAR ADC module clock division factor.
+ * SAR ADC clock divided from digital controller clock.
+ *
+ * @param div Division factor.
+ */
+static inline void adc_ll_digi_set_clk_div(uint32_t div)
+{
+    /* ADC clock divided from digital controller clock clk */
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_ctrl, saradc_sar_clk_div, div);
+}
+
+/**
+ * Set adc max conversion number for digital controller.
+ * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
+ *
+ * @param meas_num Max conversion number. Range: 0 ~ 255.
+ */
+static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_ctrl2, saradc_max_meas_num, meas_num);
+}
+
+/**
+ * Enable max conversion number detection for digital controller.
+ * If the number of ADC conversion is equal to the maximum, the conversion is stopped.
+ *
+ * @param enable  true: enable; false: disable
+ */
+static inline void adc_ll_digi_convert_limit_enable(bool enable)
+{
+    ADC.saradc_ctrl2.saradc_meas_num_limit = enable;
+}
+
+/**
+ * Set adc conversion mode for digital controller.
+ *
+ * @note ESP32C61 only support ADC1 single mode.
+ *
+ * @param mode Conversion mode select.
+ */
+static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
+{
+    //ESP32C61 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode
+}
+
+/**
+ * Set pattern table length for digital controller.
+ * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection,
+ * and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
+ * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself.
+ *
+ * @param adc_n ADC unit.
+ * @param patt_len Items range: 1 ~ 8.
+ */
+static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
+{
+    ADC.saradc_ctrl.saradc_sar_patt_len = patt_len - 1;
+}
+
+/**
+ * Set pattern table for digital controller.
+ * The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection,
+ * resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
+ * pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself.
+ *
+ * @param adc_n ADC unit.
+ * @param pattern_index Items index. Range: 0 ~ 7.
+ * @param pattern Stored conversion rules.
+ */
+static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
+{
+    uint32_t tab;
+    uint8_t index = pattern_index / 4;
+    uint8_t offset = (pattern_index % 4) * 6;
+    adc_ll_digi_pattern_table_t pattern = {0};
+
+    pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5);
+    if (index == 0) {
+        tab = ADC.saradc_sar_patt_tab1.saradc_sar_patt_tab1;         // Read old register value
+        tab &= (~(0xFC0000 >> offset));                             // Clear old data
+        tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset;    // Fill in the new data
+        ADC.saradc_sar_patt_tab1.saradc_sar_patt_tab1 = tab;         // Write back
+    } else {
+        tab = ADC.saradc_sar_patt_tab2.saradc_sar_patt_tab2;         // Read old register value
+        tab &= (~(0xFC0000 >> offset));                             // Clear old data
+        tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset;    // Fill in the new data
+        ADC.saradc_sar_patt_tab2.saradc_sar_patt_tab2 = tab;         // Write back
+    }
+}
+
+/**
+ * Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
+ *
+ * @param adc_n ADC unit.
+ */
+static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
+{
+    ADC.saradc_ctrl.saradc_sar_patt_p_clear = 1;
+    ADC.saradc_ctrl.saradc_sar_patt_p_clear = 0;
+}
+
+/**
+ * Sets the number of cycles required for the conversion to complete and wait for the arbiter to stabilize.
+ *
+ * @note Only ADC2 have arbiter function.
+ * @param cycle range: 0 ~ 4.
+ */
+static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
+{
+    ADC.saradc_ctrl.saradc_wait_arb_cycle = cycle;
+}
+
+/**
+ * ADC Digital controller output data invert or not.
+ *
+ * @param adc_n ADC unit.
+ * @param inv_en data invert or not.
+ */
+static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
+{
+    if (adc_n == ADC_UNIT_1) {
+        ADC.saradc_ctrl2.saradc_sar1_inv = inv_en;   // Enable / Disable ADC data invert
+    } else { // adc_n == ADC_UNIT_2
+        ADC.saradc_ctrl2.saradc_sar2_inv = inv_en;   // Enable / Disable ADC data invert
+    }
+}
+
+/**
+ * Set the interval clock cycle for the digital controller to trigger the measurement.
+ * Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval.
+ *
+ * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
+ * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
+ */
+static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
+{
+    ADC.saradc_ctrl2.saradc_timer_target = cycle;
+}
+
+/**
+ * Enable digital controller timer to trigger the measurement.
+ */
+static inline void adc_ll_digi_trigger_enable(void)
+{
+    ADC.saradc_ctrl2.saradc_timer_en = 1;
+}
+
+/**
+ * Disable digital controller timer to trigger the measurement.
+ */
+static inline void adc_ll_digi_trigger_disable(void)
+{
+    ADC.saradc_ctrl2.saradc_timer_en = 0;
+}
+
+/**
+ * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock.
+ * Expression: controller_clk = (APLL or APB) / (div_num + div_a / div_b + 1).
+ *
+ * @param div_num Division factor. Range: 0 ~ 255.
+ * @param div_b Division factor. Range: 1 ~ 63.
+ * @param div_a Division factor. Range: 0 ~ 63.
+ */
+static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
+    PCR.saradc_clkm_conf.saradc_clkm_div_b = div_b;
+    PCR.saradc_clkm_conf.saradc_clkm_div_a = div_a;
+}
+
+/**
+ * Enable clock and select clock source for ADC digital controller.
+ *
+ * @param clk_src clock source for ADC digital controller.
+ */
+static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
+{
+    switch (clk_src) {
+        case ADC_DIGI_CLK_SRC_XTAL:
+            PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
+            break;
+        case ADC_DIGI_CLK_SRC_RC_FAST:
+            PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
+            break;
+        case ADC_DIGI_CLK_SRC_PLL_F80M:
+            PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
+            break;
+        default:
+            HAL_ASSERT(false && "unsupported clock");
+    }
+    // Enable ADC_CTRL_CLK (i.e. digital domain clock)
+    ADC.saradc_ctrl.saradc_sar_clk_gated = 1;
+}
+
+/**
+ * Disable clock for ADC digital controller.
+ */
+static inline void adc_ll_digi_controller_clk_disable(void)
+{
+    ADC.saradc_ctrl.saradc_sar_clk_gated = 0;
+}
+
+/**
+ * Reset adc digital controller filter.
+ *
+ * @param idx   Filter index
+ * @param adc_n ADC unit.
+ */
+static inline void adc_ll_digi_filter_reset(adc_digi_iir_filter_t idx, adc_unit_t adc_n)
+{
+    (void)adc_n;
+    ADC.saradc_filter_ctrl0.saradc_adc_filter_reset = 1;
+    ADC.saradc_filter_ctrl0.saradc_adc_filter_reset = 0;
+}
+
+/**
+ * Set adc digital controller filter coeff.
+ *
+ * @param idx      filter index
+ * @param adc_n    adc unit
+ * @param channel  adc channel
+ * @param coeff    filter coeff
+ */
+static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_unit_t adc_n, adc_channel_t channel, adc_digi_iir_filter_coeff_t coeff)
+{
+    uint32_t factor_reg_val = 0;
+    switch (coeff) {
+        case ADC_DIGI_IIR_FILTER_COEFF_2:
+            factor_reg_val = 1;
+            break;
+        case ADC_DIGI_IIR_FILTER_COEFF_4:
+            factor_reg_val = 2;
+            break;
+        case ADC_DIGI_IIR_FILTER_COEFF_8:
+            factor_reg_val = 3;
+            break;
+        case ADC_DIGI_IIR_FILTER_COEFF_16:
+            factor_reg_val = 4;
+            break;
+        case ADC_DIGI_IIR_FILTER_COEFF_64:
+            factor_reg_val = 6;
+            break;
+        default:
+            HAL_ASSERT(false);
+    }
+
+    if (idx == ADC_DIGI_IIR_FILTER_0) {
+        ADC.saradc_filter_ctrl0.saradc_adc_filter_channel0 = ((adc_n + 1) << 3) | (channel & 0x7);
+        ADC.saradc_filter_ctrl1.saradc_adc_filter_factor0 = factor_reg_val;
+    } else if (idx == ADC_DIGI_IIR_FILTER_1) {
+        ADC.saradc_filter_ctrl0.saradc_adc_filter_channel1 = ((adc_n + 1) << 3) | (channel & 0x7);
+        ADC.saradc_filter_ctrl1.saradc_adc_filter_factor1 = factor_reg_val;
+    }
+}
+
+/**
+ * Enable adc digital controller filter.
+ * Filtering the ADC data to obtain smooth data at higher sampling rates.
+ *
+ * @param idx      filter index
+ * @param adc_n    ADC unit
+ * @param enable   Enable / Disable
+ */
+static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit_t adc_n, bool enable)
+{
+    (void)adc_n;
+    if (!enable) {
+        if (idx == ADC_DIGI_IIR_FILTER_0) {
+            ADC.saradc_filter_ctrl0.saradc_adc_filter_channel0 = 0xF;
+            ADC.saradc_filter_ctrl1.saradc_adc_filter_factor0 = 0;
+        } else if (idx == ADC_DIGI_IIR_FILTER_1) {
+            ADC.saradc_filter_ctrl0.saradc_adc_filter_channel1 = 0xF;
+            ADC.saradc_filter_ctrl1.saradc_adc_filter_factor1 = 0;
+        }
+    }
+    //nothing to do to enable, after adc_ll_digi_filter_set_factor, it's enabled.
+}
+
+/**
+ * Set monitor threshold of adc digital controller on specific channel.
+ *
+ * @param monitor_id ADC digi monitor unit index.
+ * @param adc_n      Which adc unit the channel belong to.
+ * @param channel    Which channel of adc want to be monitored.
+ * @param h_thresh   High threshold of this monitor.
+ * @param l_thresh   Low threshold of this monitor.
+ */
+static inline void adc_ll_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t channel, int32_t h_thresh, int32_t l_thresh)
+{
+    if (monitor_id == ADC_MONITOR_0) {
+        ADC.saradc_thres0_ctrl.saradc_adc_thres0_channel = (adc_n << 3) | (channel & 0x7);
+        ADC.saradc_thres0_ctrl.saradc_adc_thres0_high = h_thresh;
+        ADC.saradc_thres0_ctrl.saradc_adc_thres0_low = l_thresh;
+    } else { // ADC_MONITOR_1
+        ADC.saradc_thres1_ctrl.saradc_adc_thres1_channel = (adc_n << 3) | (channel & 0x7);
+        ADC.saradc_thres1_ctrl.saradc_adc_thres1_high = h_thresh;
+        ADC.saradc_thres1_ctrl.saradc_adc_thres1_low = l_thresh;
+    }
+}
+
+/**
+ * Start/Stop monitor of adc digital controller.
+ *
+ * @param monitor_id ADC digi monitor unit index.
+ * @param start 1 for start, 0 for stop
+ */
+static inline void adc_ll_digi_monitor_user_start(adc_monitor_id_t monitor_id, bool start)
+{
+    if (monitor_id == ADC_MONITOR_0) {
+        ADC.saradc_thres_ctrl.saradc_adc_thres0_en = start;
+    } else {
+        ADC.saradc_thres_ctrl.saradc_adc_thres1_en = start;
+    }
+}
+
+/**
+ * Enable/disable a intr of adc digital monitor.
+ *
+ * @param monitor_id ADC digi monitor unit index.
+ * @param mode monit mode to enable/disable intr.
+ * @param enable enable or disable.
+ */
+static inline void adc_ll_digi_monitor_enable_intr(adc_monitor_id_t monitor_id, adc_monitor_mode_t mode, bool enable)
+{
+    if (monitor_id == ADC_MONITOR_0) {
+        if (mode == ADC_MONITOR_MODE_HIGH) {
+            ADC.saradc_int_ena.saradc_adc_thres0_high_int_ena = enable;
+        } else {
+            ADC.saradc_int_ena.saradc_adc_thres0_low_int_ena = enable;
+        }
+    }
+    if (monitor_id == ADC_MONITOR_1) {
+        if (mode == ADC_MONITOR_MODE_HIGH) {
+            ADC.saradc_int_ena.saradc_adc_thres1_high_int_ena = enable;
+        } else {
+            ADC.saradc_int_ena.saradc_adc_thres1_low_int_ena = enable;
+        }
+    }
+}
+
+/**
+ * Clear intr raw for adc digi monitors.
+ */
+__attribute__((always_inline))
+static inline void adc_ll_digi_monitor_clear_intr(void)
+{
+    ADC.saradc_int_clr.val |= ADC_LL_THRES_ALL_INTR_ST_M;
+}
+
+/**
+ * Get the address of digi monitor intr statue register.
+ *
+ * @return address of register.
+ */
+__attribute__((always_inline))
+static inline volatile const void *adc_ll_digi_monitor_get_intr_status_addr(void)
+{
+    return &ADC.saradc_int_st.val;
+}
+
+/**
+ * Set DMA eof num of adc digital controller.
+ * If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated.
+ *
+ * @param num eof num of DMA.
+ */
+static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ADC.saradc_dma_conf, saradc_apb_adc_eof_num, num);
+}
+
+/**
+ * Enable output data to DMA from adc digital controller.
+ */
+static inline void adc_ll_digi_dma_enable(void)
+{
+    ADC.saradc_dma_conf.saradc_apb_adc_trans = 1;
+}
+
+/**
+ * Disable output data to DMA from adc digital controller.
+ */
+static inline void adc_ll_digi_dma_disable(void)
+{
+    ADC.saradc_dma_conf.saradc_apb_adc_trans = 0;
+}
+
+/**
+ * Reset adc digital controller.
+ */
+static inline void adc_ll_digi_reset(void)
+{
+    ADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 1;
+    ADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 0;
+}
+
+/*---------------------------------------------------------------
+                    PWDET(Power detect) controller setting
+---------------------------------------------------------------*/
+/**
+ * Set adc cct for PWDET controller.
+ *
+ * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
+ * @param cct Range: 0 ~ 7.
+ */
+static inline void adc_ll_pwdet_set_cct(uint32_t cct)
+{
+    (void)cct;
+}
+
+/**
+ * Get adc cct for PWDET controller.
+ *
+ * @note Capacitor tuning of the PA power monitor. cct set to the same value with PHY.
+ * @return cct Range: 0 ~ 7.
+ */
+static inline uint32_t adc_ll_pwdet_get_cct(void)
+{
+    return 0;
+}
+
+/*---------------------------------------------------------------
+                    Common setting
+---------------------------------------------------------------*/
+
+/**
+ * @brief Enable the ADC APB clock
+ * @param enable true to enable, false to disable
+ */
+static inline void adc_ll_enable_bus_clock(bool enable)
+{
+    PCR.saradc_conf.saradc_reg_clk_en = enable;
+}
+
+/**
+ * @brief Enable the ADC function clock
+ * @param enable true to enable, false to disable
+ */
+static inline void adc_ll_enable_func_clock(bool enable)
+{
+    PCR.saradc_clkm_conf.saradc_clkm_en = enable;
+}
+
+/**
+ * @brief Reset ADC module
+ */
+static inline void adc_ll_reset_register(void)
+{
+    PCR.saradc_conf.saradc_reg_rst_en = 1;
+    PCR.saradc_conf.saradc_reg_rst_en = 0;
+}
+
+/**
+ * Set ADC module power management.
+ *
+ * @param manage Set ADC power status.
+ */
+static inline void adc_ll_set_power_manage(adc_unit_t adc_n, adc_ll_power_t manage)
+{
+    (void) adc_n;
+    /* Bit1  0:Fsm  1: SW mode
+       Bit0  0:SW mode power down  1: SW mode power on */
+    if (manage == ADC_LL_POWER_SW_ON) {
+        ADC.saradc_ctrl.saradc_sar_clk_gated = 1;
+        ADC.saradc_ctrl.saradc_xpd_sar_force = 3;
+    } else if (manage == ADC_LL_POWER_BY_FSM) {
+        ADC.saradc_ctrl.saradc_sar_clk_gated = 1;
+        ADC.saradc_ctrl.saradc_xpd_sar_force = 0;
+    } else if (manage == ADC_LL_POWER_SW_OFF) {
+        ADC.saradc_ctrl.saradc_sar_clk_gated = 0;
+        ADC.saradc_ctrl.saradc_xpd_sar_force = 2;
+    }
+}
+
+__attribute__((always_inline))
+static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
+{
+    //Not used on ESP32C61
+}
+
+/*---------------------------------------------------------------
+                    Oneshot Read
+---------------------------------------------------------------*/
+/**
+ * Set adc output data format for oneshot mode
+ *
+ * @note ESP32C61 Oneshot mode only supports 12bit.
+ * @param adc_n ADC unit.
+ * @param bits  Output data bits width option.
+ */
+static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits)
+{
+    (void) adc_n;
+    //ESP32C61 only supports 12bit, leave here for compatibility
+    HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT);
+}
+
+/**
+ * Enable adc channel to start convert.
+ *
+ * @note Only one channel can be selected for measurement.
+ *
+ * @param adc_n   ADC unit.
+ * @param channel ADC channel number for each ADCn.
+ */
+static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel)
+{
+    ADC.saradc_onetime_sample.saradc_onetime_channel = ((adc_n << 3) | channel);
+}
+
+/**
+ * Disable adc channel to start convert.
+ *
+ * @note Only one channel can be selected in once measurement.
+ *
+ * @param adc_n ADC unit.
+ */
+static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n)
+{
+    ADC.saradc_onetime_sample.saradc_onetime_channel = ((adc_n << 3) | 0xF);
+}
+
+/**
+ * Start oneshot conversion by software
+ *
+ * @param val Usage: set to 1 to start the ADC conversion. The step signal should at least keep 3 ADC digital controller clock cycle,
+ *            otherwise the step signal may not be captured by the ADC digital controller when its frequency is slow.
+ *            This hardware limitation will be removed in future versions.
+ */
+static inline void adc_oneshot_ll_start(bool val)
+{
+    ADC.saradc_onetime_sample.saradc_onetime_start = val;
+}
+
+/**
+ * Clear the event for each ADCn for Oneshot mode
+ *
+ * @param event ADC event
+ */
+static inline void adc_oneshot_ll_clear_event(uint32_t event_mask)
+{
+    ADC.saradc_int_clr.val |= event_mask;
+}
+
+/**
+ * Check the event for each ADCn for Oneshot mode
+ *
+ * @param event ADC event
+ *
+ * @return
+ *      -true  : The conversion process is finish.
+ *      -false : The conversion process is not finish.
+ */
+static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
+{
+    return (ADC.saradc_int_raw.val & event_mask);
+}
+
+/**
+ * Get the converted value for each ADCn for controller.
+ *
+ * @param adc_n ADC unit.
+ * @return
+ *      - Converted value.
+ */
+static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
+{
+    uint32_t ret_val = 0;
+    if (adc_n == ADC_UNIT_1) {
+        ret_val = ADC.saradc_sar1data_status.saradc_adc1_data & 0xfff;
+    } else { // adc_n == ADC_UNIT_2
+        ret_val = ADC.saradc_sar2data_status.saradc_adc2_data & 0xfff;
+    }
+    return ret_val;
+}
+
+
+/**
+ * Analyze whether the obtained raw data is correct.
+ * ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
+ *
+ * @param adc_n    ADC unit.
+ * @param raw_data ADC raw data input (convert value).
+ * @return
+ *        - 1: The data is correct to use.
+ *        - 0: The data is invalid.
+ */
+static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data)
+{
+    (void)adc_n;
+    return true;
+}
+
+/**
+ * ADC module RTC output data invert or not.
+ *
+ * @param adc_n ADC unit.
+ * @param inv_en data invert or not.
+ */
+static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en)
+{
+    (void)adc_n;
+    (void)inv_en;
+    //For compatibility
+}
+
+/**
+ * Enable oneshot conversion trigger
+ *
+ * @param adc_n  ADC unit
+ */
+static inline void adc_oneshot_ll_enable(adc_unit_t adc_n)
+{
+    if (adc_n == ADC_UNIT_1) {
+        ADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1;
+    } else {
+        ADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 1;
+    }
+}
+
+/**
+ * Disable oneshot conversion trigger for all the ADC units
+ */
+static inline void adc_oneshot_ll_disable_all_unit(void)
+{
+    ADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0;
+    ADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0;
+}
+
+/**
+ * Set attenuation
+ *
+ * @note Attenuation is for all channels
+ *
+ * @param adc_n   ADC unit
+ * @param channel ADC channel
+ * @param atten   ADC attenuation
+ */
+static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
+{
+    (void)adc_n;
+    (void)channel;
+    // Attenuation is for all channels, unit and channel are for compatibility
+    ADC.saradc_onetime_sample.saradc_onetime_atten = atten;
+}
+
+/**
+ * Get the attenuation of a particular channel on ADCn.
+ *
+ * @param adc_n ADC unit.
+ * @param channel ADCn channel number.
+ * @return atten The attenuation option.
+ */
+__attribute__((always_inline))
+static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
+{
+    (void)adc_n;
+    (void)channel;
+    return (adc_atten_t)ADC.saradc_onetime_sample.saradc_onetime_atten;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c61/include/hal/brownout_ll.h b/components/hal/esp32c61/include/hal/brownout_ll.h
index 7a4bb9e1841..ac3b966d56a 100644
--- a/components/hal/esp32c61/include/hal/brownout_ll.h
+++ b/components/hal/esp32c61/include/hal/brownout_ll.h
@@ -113,8 +113,6 @@ static inline void brownout_ll_ana_reset_enable(bool enable)
     LP_ANA.fib_enable.val &= ~BROWNOUT_DETECTOR_LL_FIB_ENABLE;
     // then we can enable or disable if we want the BOD mode1 to reset the system
     LP_ANA.bod_mode1_cntl.bod_mode1_reset_ena = enable;
-    // Disable the power glitch detect.
-    LP_ANA.fib_enable.val &= ~(BIT2|BIT3|BIT4|BIT5);
 }
 
 /**
diff --git a/components/hal/esp32c61/include/hal/etm_ll.h b/components/hal/esp32c61/include/hal/etm_ll.h
new file mode 100644
index 00000000000..ebed4861b56
--- /dev/null
+++ b/components/hal/esp32c61/include/hal/etm_ll.h
@@ -0,0 +1,119 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "soc/soc_etm_struct.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ETM_LL_SUPPORT_STATUS          1   // Support to get and clear the status of the ETM event and task
+
+/**
+ * @brief Enable the clock for ETM register
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    PCR.etm_conf.etm_clk_en = enable;
+}
+
+/**
+ * @brief Reset the ETM register
+ *
+ * @param group_id Group ID
+ */
+static inline void etm_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    PCR.etm_conf.etm_rst_en = 1;
+    PCR.etm_conf.etm_rst_en = 0;
+}
+
+/**
+ * @brief Enable ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ */
+static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        hw->ch_ena_ad0_set.val = 1 << chan;
+    } else {
+        hw->ch_ena_ad1_set.val = 1 << (chan - 32);
+    }
+}
+
+/**
+ * @brief Disable ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ */
+static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        hw->ch_ena_ad0_clr.val = 1 << chan;
+    } else {
+        hw->ch_ena_ad1_clr.val = 1 << (chan - 32);
+    }
+}
+
+/**
+ * @brief Check whether the ETM channel is enabled or not
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @return true if the channel is enabled, false otherwise
+ */
+static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        return hw->ch_ena_ad0.val & (1 << chan);
+    } else {
+        return hw->ch_ena_ad1.val & (1 << (chan - 32));
+    }
+}
+
+/**
+ * @brief Set the input event for the ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @param event Event ID
+ */
+static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, chn_evt_id, event);
+}
+
+/**
+ * @brief Set the output task for the ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @param task Task ID
+ */
+static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, chn_task_id, task);
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c61/include/hal/gpio_etm_ll.h b/components/hal/esp32c61/include/hal/gpio_etm_ll.h
new file mode 100644
index 00000000000..52a06e7fc3e
--- /dev/null
+++ b/components/hal/esp32c61/include/hal/gpio_etm_ll.h
@@ -0,0 +1,136 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "soc/gpio_ext_struct.h"
+#include "soc/soc_etm_source.h"
+
+#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch))
+#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch))
+#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch))
+
+#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch))
+#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
+#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
+
+#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP    8
+#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP     8
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set which GPIO to be bound to the event channel
+ *
+ * @note Different channels can be bound to one GPIO
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Event channel number
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
+{
+    dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num;
+}
+
+/**
+ * @brief Whether to enable the event channel
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Event channel number
+ * @param enable True to enable, false to disable
+ */
+static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
+{
+    dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable;
+}
+
+/**
+ * @brief Get which GPIO is bound to the event channel
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Event channel number
+ * @return GPIO number
+ */
+static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan)
+{
+    return dev->etm_event_chn_cfg[chan].etm_chn_event_sel;
+}
+
+/**
+ * @brief Set which GPIO to be bound to the task channel
+ *
+ * @note One channel can be bound to multiple different GPIOs
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Task channel number
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
+{
+    int g_p = gpio_num / 5;
+    int g_idx = gpio_num % 5;
+    uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
+    reg_val &= ~(0x07 << (g_idx * 6));
+    reg_val |= ((chan & 0x07) << (g_idx * 6));
+    dev->etm_task_pn_cfg[g_p].val = reg_val;
+}
+
+/**
+ * @brief Whether to enable the GPIO to be managed by the task channel
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @param enable True to enable, false to disable
+ */
+static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable)
+{
+    int g_p = gpio_num / 5;
+    int g_idx = gpio_num % 5;
+    uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
+    reg_val &= ~(0x01 << (g_idx * 6 + 5));
+    reg_val |= ((enable & 0x01) << (g_idx * 6 + 5));
+    dev->etm_task_pn_cfg[g_p].val = reg_val;
+}
+
+/**
+ * @brief Check whether a GPIO has been enabled and managed by a task channel
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @return True if enabled, false otherwise
+ */
+static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num)
+{
+    int g_p = gpio_num / 5;
+    int g_idx = gpio_num % 5;
+    return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5));
+}
+
+/**
+ * @brief Get the channel number that the GPIO is bound to
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @return GPIO ETM Task channel number
+ */
+static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num)
+{
+    int g_p = gpio_num / 5;
+    int g_idx = gpio_num % 5;
+    return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c61/include/hal/gpio_ll.h b/components/hal/esp32c61/include/hal/gpio_ll.h
index 1f1670aff83..a04c6ce2e5c 100644
--- a/components/hal/esp32c61/include/hal/gpio_ll.h
+++ b/components/hal/esp32c61/include/hal/gpio_ll.h
@@ -356,9 +356,9 @@ __attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t level)
 {
     if (level) {
-        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+        hw->out_w1ts.val = 1 << gpio_num;
     } else {
-        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+        hw->out_w1tc.val = 1 << gpio_num;
     }
 }
 
diff --git a/components/hal/esp32c61/include/hal/i2c_ll.h b/components/hal/esp32c61/include/hal/i2c_ll.h
index c5dc44348db..7393fe83434 100644
--- a/components/hal/esp32c61/include/hal/i2c_ll.h
+++ b/components/hal/esp32c61/include/hal/i2c_ll.h
@@ -78,6 +78,8 @@ typedef enum {
 #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT   (9)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2500)  // Approximate value for SCL timeout regs (in us).
 
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff)
+
 /**
  * @brief  Calculate I2C bus frequency
  *         Note that the clock accuracy is affected by the external pull-up resistor,
@@ -880,6 +882,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    dev->scl_stretch_conf.stretch_protect_num = protect_num;
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -908,6 +920,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->sr.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32c61/include/hal/i2s_ll.h b/components/hal/esp32c61/include/hal/i2s_ll.h
new file mode 100644
index 00000000000..209bf67219f
--- /dev/null
+++ b/components/hal/esp32c61/include/hal/i2s_ll.h
@@ -0,0 +1,1323 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for I2S register operations
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+#pragma once
+#include <stdbool.h>
+#include "hal/misc.h"
+#include "hal/assert.h"
+#include "soc/i2s_periph.h"
+#include "soc/i2s_struct.h"
+#include "soc/pcr_struct.h"
+#include "soc/soc_etm_struct.h"
+#include "soc/soc_etm_source.h"
+#include "hal/i2s_types.h"
+#include "hal/hal_utils.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define I2S_LL_GET_HW(num)             (((num) == 0)? (&I2S0) : NULL)
+#define I2S_LL_GET_ID(hw)              (((hw) == &I2S0)? 0 : -1)
+
+#define I2S_LL_TDM_CH_MASK             (0xffff)
+#define I2S_LL_PDM_BCK_FACTOR          (64)
+
+#define I2S_LL_CLK_FRAC_DIV_N_MAX      256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width
+#define I2S_LL_CLK_FRAC_DIV_AB_MAX     512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
+
+#define I2S_LL_PLL_F160M_CLK_FREQ      (160 * 1000000) // PLL_F160M_CLK: 160MHz
+#define I2S_LL_DEFAULT_CLK_FREQ        I2S_LL_PLL_F160M_CLK_FREQ    // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
+
+#define I2S_LL_ETM_EVENT_TABLE(i2s_port, chan_dir, event)  \
+    (uint32_t[SOC_I2S_NUM][2][I2S_ETM_EVENT_MAX]){{  \
+                                          [I2S_DIR_RX - 1] = {  \
+                                              [I2S_ETM_EVENT_DONE] = I2S0_EVT_RX_DONE, \
+                                              [I2S_ETM_EVENT_REACH_THRESH] = I2S0_EVT_X_WORDS_RECEIVED,  \
+                                          },  \
+                                          [I2S_DIR_TX - 1] = {  \
+                                              [I2S_ETM_EVENT_DONE] = I2S0_EVT_TX_DONE,  \
+                                              [I2S_ETM_EVENT_REACH_THRESH] = I2S0_EVT_X_WORDS_SENT, \
+                                          }}}[i2s_port][(chan_dir) - 1][event]
+
+
+#define I2S_LL_ETM_TASK_TABLE(i2s_port, chan_dir, task)  \
+    (uint32_t[SOC_I2S_NUM][2][I2S_ETM_TASK_MAX]){{  \
+                                         [I2S_DIR_RX - 1] = {  \
+                                             [I2S_ETM_TASK_START] = I2S0_TASK_START_RX, \
+                                             [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_RX, \
+                                         },  \
+                                         [I2S_DIR_TX - 1] = {  \
+                                             [I2S_ETM_TASK_START] = I2S0_TASK_START_TX, \
+                                             [I2S_ETM_TASK_STOP] = I2S0_TASK_STOP_TX, \
+                                         }}}[i2s_port][(chan_dir) - 1][task]
+#define I2S_LL_ETM_MAX_THRESH_NUM       (0x3FFUL)
+
+/**
+ * @brief Enable the bus clock for I2S module
+ *
+ * @param i2s_id The port id of I2S
+ * @param enable Set true to enable the buf clock
+ */
+static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
+{
+    (void)i2s_id;
+    PCR.i2s_conf.i2s_clk_en = enable;
+}
+
+/**
+ * @brief Reset the I2S module
+ *
+ * @param i2s_id The port id of I2S
+ */
+static inline void i2s_ll_reset_register(int i2s_id)
+{
+    (void)i2s_id;
+    PCR.i2s_conf.i2s_rst_en = 1;
+    PCR.i2s_conf.i2s_rst_en = 0;
+}
+
+/**
+ * @brief I2S module general init, enable I2S clock.
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param enable set true to enable the core clock
+ */
+static inline void i2s_ll_enable_core_clock(i2s_dev_t *hw, bool enable)
+{
+    (void)hw;
+    (void)enable;
+    // No need to do anything
+}
+
+/**
+ * @brief Enable I2S tx module clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw)
+{
+    (void)hw;
+    PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 1;
+}
+
+/**
+ * @brief Enable I2S rx module clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw)
+{
+    (void)hw;
+    PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 1;
+}
+
+/**
+ * @brief Disable I2S tx module clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw)
+{
+    (void)hw;
+    PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 0;
+}
+
+/**
+ * @brief Disable I2S rx module clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw)
+{
+    (void)hw;
+    PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 0;
+}
+
+/**
+ * @brief I2S mclk use tx module clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw)
+{
+    (void)hw;
+    PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0;
+}
+
+/**
+ * @brief I2S mclk use rx module clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_mclk_bind_to_rx_clk(i2s_dev_t *hw)
+{
+    (void)hw;
+    PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 1;
+}
+
+/**
+ * @brief Enable I2S TX slave mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param slave_en Set true to enable slave mode
+ */
+static inline void i2s_ll_tx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
+{
+    hw->tx_conf.tx_slave_mod = slave_en;
+}
+
+/**
+ * @brief Enable I2S RX slave mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param slave_en Set true to enable slave mode
+ */
+static inline void i2s_ll_rx_set_slave_mod(i2s_dev_t *hw, bool slave_en)
+{
+    hw->rx_conf.rx_slave_mod = slave_en;
+}
+
+/**
+ * @brief Reset I2S TX module
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_reset(i2s_dev_t *hw)
+{
+    hw->tx_conf.tx_reset = 1;
+    hw->tx_conf.tx_reset = 0;
+}
+
+/**
+ * @brief Reset I2S RX module
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_rx_reset(i2s_dev_t *hw)
+{
+    hw->rx_conf.rx_reset = 1;
+    hw->rx_conf.rx_reset = 0;
+}
+
+/**
+ * @brief Reset I2S TX FIFO
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_reset_fifo(i2s_dev_t *hw)
+{
+    hw->tx_conf.tx_fifo_reset = 1;
+    hw->tx_conf.tx_fifo_reset = 0;
+}
+
+/**
+ * @brief Reset I2S RX FIFO
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
+{
+    hw->rx_conf.rx_fifo_reset = 1;
+    hw->rx_conf.rx_fifo_reset = 0;
+}
+
+/**
+ * @brief Set TX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param src I2S source clock.
+ */
+static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
+{
+    (void)hw;
+    switch (src)
+    {
+    case I2S_CLK_SRC_XTAL:
+        PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0;
+        break;
+    case I2S_CLK_SRC_PLL_120M:
+        PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 1;
+        break;
+    case I2S_CLK_SRC_PLL_160M:
+        PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 2;
+        break;
+    case I2S_CLK_SRC_EXTERNAL:
+        PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 3;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
+}
+
+/**
+ * @brief Set RX source clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param src I2S source clock
+ */
+static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
+{
+    (void)hw;
+    switch (src)
+    {
+    case I2S_CLK_SRC_XTAL:
+        PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0;
+        break;
+    case I2S_CLK_SRC_PLL_120M:
+        PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 1;
+        break;
+    case I2S_CLK_SRC_PLL_160M:
+        PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 2;
+        break;
+    case I2S_CLK_SRC_EXTERNAL:
+        PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 3;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
+}
+
+/**
+ * @brief Set I2S tx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set tx bck div num
+ */
+static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->tx_conf.tx_bck_div_num = val - 1;
+}
+
+/**
+ * @brief Set I2S tx raw clock division
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
+ * @param x  div x
+ * @param y  div y
+ * @param z  div z
+ * @param yn1 yn1
+ */
+static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+{
+    (void)hw;
+    /* Workaround for the double division issue.
+     * The division coefficients must be set in particular sequence.
+     * And it has to switch to a small division first before setting the target division. */
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, 2);
+    PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = 0;
+    PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = 1;
+    PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = 0;
+    PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = 0;
+
+    /* Set the target mclk division coefficients */
+    PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_yn1 = yn1;
+    PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = z;
+    PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = y;
+    PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = x;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_tx_clkm_conf, i2s_tx_clkm_div_num, div_int);
+}
+
+/**
+ * @brief Set I2S rx raw clock division
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param div_int  Integer part of division
+ * @param x  div x
+ * @param y  div y
+ * @param z  div z
+ * @param yn1 yn1
+ */
+static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
+{
+    (void)hw;
+    /* Workaround for the double division issue.
+     * The division coefficients must be set in particular sequence.
+     * And it has to switch to a small division first before setting the target division. */
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, 2);
+    PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = 0;
+    PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = 1;
+    PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = 0;
+    PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = 0;
+
+    /* Set the target mclk division coefficients */
+    PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_yn1 = yn1;
+    PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = z;
+    PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = y;
+    PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = x;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2s_rx_clkm_conf, i2s_rx_clkm_div_num, div_int);
+}
+
+/**
+ * @brief Configure I2S TX module clock divider
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param mclk_div The mclk division coefficients
+ */
+static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
+{
+    uint32_t div_x = 0;
+    uint32_t div_y = 0;
+    uint32_t div_z = 0;
+    uint32_t div_yn1 = 0;
+    /* If any of denominator and numerator is 0, set all the coefficients to 0 */
+    if (mclk_div->denominator && mclk_div->numerator) {
+        div_yn1 = mclk_div->numerator * 2 > mclk_div->denominator;
+        div_z = div_yn1 ? mclk_div->denominator - mclk_div->numerator : mclk_div->numerator;
+        div_x = mclk_div->denominator / div_z - 1;
+        div_y = mclk_div->denominator % div_z;
+    }
+    i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integer, div_x, div_y, div_z, div_yn1);
+}
+
+/**
+ * @brief Set I2S rx bck div num
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param val value to set rx bck div num
+ */
+static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
+{
+    hw->rx_conf.rx_bck_div_num = val - 1;
+}
+
+/**
+ * @brief Configure I2S RX module clock divider
+ * @note mclk on ESP32C61 is shared by both TX and RX channel
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param mclk_div The mclk division coefficients
+ */
+static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const hal_utils_clk_div_t *mclk_div)
+{
+    uint32_t div_x = 0;
+    uint32_t div_y = 0;
+    uint32_t div_z = 0;
+    uint32_t div_yn1 = 0;
+    /* If any of denominator and numerator is 0, set all the coefficients to 0 */
+    if (mclk_div->denominator && mclk_div->numerator) {
+        div_yn1 = mclk_div->numerator * 2 > mclk_div->denominator;
+        div_z = div_yn1 ? mclk_div->denominator - mclk_div->numerator : mclk_div->numerator;
+        div_x = mclk_div->denominator / div_z - 1;
+        div_y = mclk_div->denominator % div_z;
+    }
+    i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integer, div_x, div_y, div_z, div_yn1);
+}
+
+/**
+ * @brief Start I2S TX
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_start(i2s_dev_t *hw)
+{
+    // Have to update registers before start
+    hw->tx_conf.tx_update = 1;
+    while (hw->tx_conf.tx_update);
+    hw->tx_conf.tx_start = 1;
+}
+
+/**
+ * @brief Start I2S RX
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_rx_start(i2s_dev_t *hw)
+{
+    // Have to update registers before start
+    hw->rx_conf.rx_update = 1;
+    while (hw->rx_conf.rx_update);
+    hw->rx_conf.rx_start = 1;
+}
+
+/**
+ * @brief Stop I2S TX
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_stop(i2s_dev_t *hw)
+{
+    hw->tx_conf.tx_start = 0;
+}
+
+/**
+ * @brief Stop I2S RX
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_rx_stop(i2s_dev_t *hw)
+{
+    hw->rx_conf.rx_start = 0;
+}
+
+/**
+ * @brief Configure TX WS signal width
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param width WS width in BCK cycle
+ */
+static inline void i2s_ll_tx_set_ws_width(i2s_dev_t *hw, int width)
+{
+    hw->tx_conf1.tx_tdm_ws_width = width - 1;
+}
+
+/**
+ * @brief Configure RX WS signal width
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param width WS width in BCK cycle
+ */
+static inline void i2s_ll_rx_set_ws_width(i2s_dev_t *hw, int width)
+{
+    hw->rx_conf1.rx_tdm_ws_width = width - 1;
+}
+
+/**
+ * @brief Configure the received length to trigger in_suc_eof interrupt
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param eof_num the byte length to trigger in_suc_eof interrupt
+ */
+static inline void i2s_ll_rx_set_eof_num(i2s_dev_t *hw, int eof_num)
+{
+    hw->rx_eof_num.rx_eof_num = eof_num;
+}
+
+/**
+ * @brief Configure TX chan bit and audio data bit
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param chan_bit The chan bit width
+ * @param data_bit The audio data bit width
+ */
+static inline void i2s_ll_tx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit)
+{
+    hw->tx_conf1.tx_bits_mod = data_bit - 1;
+    hw->tx_conf1.tx_tdm_chan_bits = chan_bit - 1;
+}
+
+/**
+ * @brief Configure RX chan bit and audio data bit
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param chan_bit The chan bit width
+ * @param data_bit The audio data bit width
+ */
+static inline void i2s_ll_rx_set_sample_bit(i2s_dev_t *hw, uint8_t chan_bit, int data_bit)
+{
+    hw->rx_conf1.rx_bits_mod = data_bit - 1;
+    hw->rx_conf1.rx_tdm_chan_bits = chan_bit - 1;
+}
+
+/**
+ * @brief Configure RX half_sample_bit
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param half_sample_bits half sample bit width
+ */
+static inline void i2s_ll_tx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_conf1, tx_half_sample_bits,  half_sample_bits - 1);
+}
+
+/**
+ * @brief Configure RX half_sample_bit
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param half_sample_bits half sample bit width
+ */
+static inline void i2s_ll_rx_set_half_sample_bit(i2s_dev_t *hw, int half_sample_bits)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_conf1, rx_half_sample_bits,  half_sample_bits - 1);
+}
+
+/**
+ * @brief Enable TX MSB shift, the data will be launch at the first BCK clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param msb_shift_enable Set true to enable MSB shift
+ */
+static inline void i2s_ll_tx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable)
+{
+    hw->tx_conf.tx_msb_shift = msb_shift_enable;
+}
+
+/**
+ * @brief Enable RX MSB shift, the data will be launch at the first BCK clock
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param msb_shift_enable Set true to enable MSB shift
+ */
+static inline void i2s_ll_rx_enable_msb_shift(i2s_dev_t *hw, bool msb_shift_enable)
+{
+    hw->rx_conf.rx_msb_shift = msb_shift_enable;
+}
+
+/**
+ * @brief Configure TX total chan number
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param total_num Total chan number
+ */
+static inline void i2s_ll_tx_set_chan_num(i2s_dev_t *hw, int total_num)
+{
+    hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = total_num - 1;
+}
+
+/**
+ * @brief Configure RX total chan number
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param total_num Total chan number
+ */
+static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
+{
+    hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = total_num - 1;
+}
+
+/**
+ * @brief Set the bimap of the active TX chan, only the active chan can launch audio data.
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param chan_mask mask of tx active chan
+ */
+static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
+{
+    uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->tx_tdm_ctrl.val = tdm_ctrl;
+}
+
+/**
+ * @brief Set the bimap of the active RX chan, only the active chan can receive audio data.
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param chan_mask mask of rx active chan
+ */
+static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
+{
+    uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
+    tdm_ctrl &= 0xFFFF0000;
+    tdm_ctrl |= chan_mask;
+    hw->rx_tdm_ctrl.val = tdm_ctrl;
+}
+
+/**
+ * @brief Set I2S tx chan mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param slot_mask select slot to send data
+ */
+static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask)
+{
+    /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
+     * Otherwise always enable the first two slots */
+    hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1;  // tx_tdm_tot_chan_num = 2 slots - 1 = 1
+    uint32_t chan_mask = 0;
+    switch (slot_mask)
+    {
+    case I2S_STD_SLOT_LEFT:
+        chan_mask |= 0x01;
+        break;
+    case I2S_STD_SLOT_RIGHT:
+        chan_mask |= 0x02;
+        break;
+    case I2S_STD_SLOT_BOTH:
+        chan_mask |= 0x03;
+        break;
+    default:
+        break;
+    }
+    i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
+}
+
+/**
+ * @brief Set I2S rx chan mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param slot_mask select slot to receive data
+ */
+static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t slot_mask)
+{
+    /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
+     * Otherwise always enable the first two slots */
+    hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1;  // rx_tdm_tot_chan_num = 2 slots - 1 = 1
+    uint32_t chan_mask = 0;
+    switch (slot_mask)
+    {
+    case I2S_STD_SLOT_LEFT:
+        chan_mask |= 0x01;
+        break;
+    case I2S_STD_SLOT_RIGHT:
+        chan_mask |= 0x02;
+        break;
+    case I2S_STD_SLOT_BOTH:
+        chan_mask |= 0x03;
+        break;
+    default:
+        break;
+    }
+    i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
+}
+
+/**
+ * @brief PDM slot mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param mod Channel mode
+ *            while tx_ws_idle_pol = 0:
+ *            0: stereo
+ *            1: Both slots transmit left
+ *            2: Both slots transmit right
+ *            3: Left transmits `conf_single_data` right transmits data
+ *            4: Right transmits `conf_single_data` left transmits data
+ *            while tx_ws_idle_pol = 1:
+              0: stereo
+ *            1: Both slots transmit right
+ *            2: Both slots transmit left
+ *            3: Right transmits `conf_single_data` left transmits data
+ *            4: Left transmits `conf_single_data` right transmits data
+ */
+static inline void i2s_ll_tx_set_pdm_chan_mod(i2s_dev_t *hw, uint32_t mod)
+{
+    hw->tx_conf.tx_chan_mod = mod;
+}
+
+/**
+ * @brief Set TX WS signal pol level
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param ws_pol_level pin level of WS(output) when receiving left channel data
+ */
+static inline void i2s_ll_tx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
+{
+    hw->tx_conf.tx_ws_idle_pol = ws_pol_level;
+}
+
+/**
+ * @brief Set RX WS signal pol level
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param ws_pol_level pin level of WS(input) when receiving left channel data
+ */
+static inline void i2s_ll_rx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
+{
+    hw->rx_conf.rx_ws_idle_pol = ws_pol_level;
+}
+
+/**
+ * @brief Enable I2S TX TDM mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_enable_tdm(i2s_dev_t *hw)
+{
+    hw->tx_conf.tx_pdm_en = false;
+    hw->tx_conf.tx_tdm_en = true;
+    hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = false;
+}
+
+/**
+ * @brief Enable I2S RX TDM mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_rx_enable_tdm(i2s_dev_t *hw)
+{
+    hw->rx_conf.rx_pdm_en = false;
+    hw->rx_conf.rx_tdm_en = true;
+}
+
+/**
+ * @brief Enable I2S TX STD mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_enable_std(i2s_dev_t *hw)
+{
+    i2s_ll_tx_enable_tdm(hw);
+}
+
+/**
+ * @brief Enable I2S RX STD mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_rx_enable_std(i2s_dev_t *hw)
+{
+    i2s_ll_rx_enable_tdm(hw);
+}
+
+/**
+ * @brief Enable TX PDM mode.
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ */
+static inline void i2s_ll_tx_enable_pdm(i2s_dev_t *hw)
+{
+    hw->tx_conf.tx_pdm_en = true;
+    hw->tx_conf.tx_tdm_en = false;
+    hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = true;
+}
+
+/**
+ * @brief Set I2S TX PDM prescale
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param prescale I2S TX PDM prescale
+ */
+static inline void i2s_ll_tx_set_pdm_prescale(i2s_dev_t *hw, bool prescale)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_pcm2pdm_conf, tx_pdm_prescale, prescale);
+}
+
+/**
+ * @brief Set I2S TX PDM high pass filter scaling
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param sig_scale I2S TX PDM signal scaling before transmit to the filter
+ */
+static inline void i2s_ll_tx_set_pdm_hp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_hp_in_shift = sig_scale;
+}
+
+/**
+ * @brief Set I2S TX PDM low pass filter scaling
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param sig_scale I2S TX PDM signal scaling before transmit to the filter
+ */
+static inline void i2s_ll_tx_set_pdm_lp_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_lp_in_shift = sig_scale;
+}
+
+/**
+ * @brief Set I2S TX PDM sinc filter scaling
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param sig_scale I2S TX PDM signal scaling before transmit to the filter
+ */
+static inline void i2s_ll_tx_set_pdm_sinc_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_sinc_in_shift = sig_scale;
+}
+
+/**
+ * @brief Set I2S TX PDM sigma-delta filter scaling
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param sig_scale I2S TX PDM signal scaling before transmit to the filter
+ */
+static inline void i2s_ll_tx_set_pdm_sd_scale(i2s_dev_t *hw, i2s_pdm_sig_scale_t sig_scale)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_in_shift = sig_scale;
+}
+
+/**
+ * @brief Set I2S TX PDM high pass filter param0
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param param The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])
+ */
+static inline void i2s_ll_tx_set_pdm_hp_filter_param0(i2s_dev_t *hw, uint32_t param)
+{
+    hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_0 = param;
+}
+
+/**
+ * @brief Set I2S TX PDM high pass filter param5
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param param The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])
+ */
+static inline void i2s_ll_tx_set_pdm_hp_filter_param5(i2s_dev_t *hw, uint32_t param)
+{
+    hw->tx_pcm2pdm_conf1.tx_iir_hp_mult12_5 = param;
+}
+
+/**
+ * @brief Enable I2S TX PDM high pass filter
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param enable Set true to enable I2S TX PDM high pass filter, set false to bypass it
+ */
+static inline void i2s_ll_tx_enable_pdm_hp_filter(i2s_dev_t *hw, bool enable)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_hp_bypass = !enable;
+}
+
+/**
+ * @brief Set I2S TX PDM sigma-delta codec dither
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param dither I2S TX PDM sigmadelta dither value
+ */
+static inline void i2s_ll_tx_set_pdm_sd_dither(i2s_dev_t *hw, uint32_t dither)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither = dither;
+}
+
+/**
+ * @brief Set I2S TX PDM sigma-delta codec dither
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param dither2 I2S TX PDM sigmadelta dither2 value
+ */
+static inline void i2s_ll_tx_set_pdm_sd_dither2(i2s_dev_t *hw, uint32_t dither2)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_sigmadelta_dither2 = dither2;
+}
+
+/**
+ * @brief Set the PDM TX over sampling ratio
+ *
+ * @param hw  Peripheral I2S hardware instance address.
+ * @param ovr Over sampling ratio
+ */
+static inline void i2s_ll_tx_set_pdm_over_sample_ratio(i2s_dev_t *hw, uint32_t ovr)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_sinc_osr2 = ovr;
+}
+
+/**
+ * @brief Configure I2S TX PDM sample rate
+ *        Fpdm = 64*Fpcm*fp/fs
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param fp The fp value of TX PDM filter module group0.
+ * @param fs The fs value of TX PDM filter module group0.
+ */
+static inline void i2s_ll_tx_set_pdm_fpfs(i2s_dev_t *hw, uint32_t fp, uint32_t fs)
+{
+    hw->tx_pcm2pdm_conf1.tx_pdm_fp = fp;
+    hw->tx_pcm2pdm_conf1.tx_pdm_fs = fs;
+}
+
+/**
+ * @brief Get I2S TX PDM fp configuration parameter
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return
+ *        - fp configuration parameter
+ */
+static inline uint32_t i2s_ll_tx_get_pdm_fp(i2s_dev_t *hw)
+{
+    return hw->tx_pcm2pdm_conf1.tx_pdm_fp;
+}
+
+/**
+ * @brief Get I2S TX PDM fs configuration parameter
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return
+ *        - fs configuration parameter
+ */
+static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
+{
+    return hw->tx_pcm2pdm_conf1.tx_pdm_fs;
+}
+
+/**
+ * @brief Enable RX PDM mode.
+ * @note  ESP32-C61 doesn't support pdm in rx mode, disable anyway
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param pdm_enable Set true to RX enable PDM mode (ignored)
+ */
+static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm_enable)
+{
+    // Due to the lack of `PDM to PCM` module on ESP32-C61, PDM RX is not available
+    HAL_ASSERT(!pdm_enable);
+    hw->rx_conf.rx_pdm_en = 0;
+    hw->rx_conf.rx_tdm_en = 1;
+}
+
+/**
+ * @brief Configura TX a/u-law decompress or compress
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param pcm_cfg PCM configuration parameter
+ */
+static inline void i2s_ll_tx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg)
+{
+    hw->tx_conf.tx_pcm_conf = pcm_cfg;
+    hw->tx_conf.tx_pcm_bypass = !pcm_cfg;
+}
+
+/**
+ * @brief Configure RX a/u-law decompress or compress
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param pcm_cfg PCM configuration parameter
+ */
+static inline void i2s_ll_rx_set_pcm_type(i2s_dev_t *hw, i2s_pcm_compress_t pcm_cfg)
+{
+    hw->rx_conf.rx_pcm_conf = pcm_cfg;
+    hw->rx_conf.rx_pcm_bypass = !pcm_cfg;
+}
+
+/**
+ * @brief Enable TX audio data left alignment
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param ena Set true to enable left alignment
+ */
+static inline void i2s_ll_tx_enable_left_align(i2s_dev_t *hw, bool ena)
+{
+    hw->tx_conf.tx_left_align = ena;
+}
+
+/**
+ * @brief Enable RX audio data left alignment
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param ena Set true to enable left alignment
+ */
+static inline void i2s_ll_rx_enable_left_align(i2s_dev_t *hw, bool ena)
+{
+    hw->rx_conf.rx_left_align = ena;
+}
+
+/**
+ * @brief Enable TX big endian mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param ena Set true to enable big endian mode
+ */
+static inline void i2s_ll_rx_enable_big_endian(i2s_dev_t *hw, bool ena)
+{
+    hw->rx_conf.rx_big_endian = ena;
+}
+
+/**
+ * @brief Enable RX big endian mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param ena Set true to enable big endian mode
+ */
+static inline void i2s_ll_tx_enable_big_endian(i2s_dev_t *hw, bool ena)
+{
+    hw->tx_conf.tx_big_endian = ena;
+}
+
+/**
+ * @brief Configure TX bit order
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param lsb_order_ena Set true to enable LSB bit order
+ */
+static inline void i2s_ll_tx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena)
+{
+    hw->tx_conf.tx_bit_order = lsb_order_ena;
+}
+
+/**
+ * @brief Configure RX bit order
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param lsb_order_ena Set true to enable LSB bit order
+ */
+static inline void i2s_ll_rx_set_bit_order(i2s_dev_t *hw, bool lsb_order_ena)
+{
+    hw->rx_conf.rx_bit_order = lsb_order_ena;
+}
+
+/**
+ * @brief Configure TX skip mask enable
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param skip_mask_ena Set true to skip inactive channels.
+ */
+static inline void i2s_ll_tx_set_skip_mask(i2s_dev_t *hw, bool skip_mask_ena)
+{
+    hw->tx_tdm_ctrl.tx_tdm_skip_msk_en = skip_mask_ena;
+}
+
+
+/**
+ * @brief Configure single data
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param data Single data to be set
+ */
+static inline void i2s_ll_set_single_data(i2s_dev_t *hw, uint32_t data)
+{
+    hw->conf_single_data.val = data;
+}
+
+/**
+ * @brief Enable TX mono mode
+ * @note MONO in hardware means only one channel got data, but another doesn't
+ *       MONO in software means two channel share same data
+ *       This function aims to use MONO in software meaning
+ *       so 'tx_mono' and 'tx_chan_equal' should be enabled at the same time
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param mono_ena Set true to enable mono mde.
+ */
+static inline void i2s_ll_tx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena)
+{
+    hw->tx_conf.tx_mono = mono_ena;
+    hw->tx_conf.tx_chan_equal = mono_ena;
+}
+
+/**
+ * @brief Enable RX mono mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param mono_ena Set true to enable mono mde.
+ */
+static inline void i2s_ll_rx_enable_mono_mode(i2s_dev_t *hw, bool mono_ena)
+{
+    hw->rx_conf.rx_mono = mono_ena;
+    hw->rx_conf.rx_mono_fst_vld = mono_ena;
+}
+
+/**
+ * @brief Enable loopback mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param ena Set true to share BCK and WS signal for tx module and rx module.
+ */
+static inline void i2s_ll_share_bck_ws(i2s_dev_t *hw, bool ena)
+{
+    hw->tx_conf.sig_loopback = ena;
+}
+
+/**
+ * @brief PDM TX DMA data take mode
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param is_mono   The DMA data only has one slot (mono) or contains two slots (stereo)
+ * @param is_fst_valid  Whether take the DMA data at the first half period
+ *                      Only take effet when 'is_mono' is true
+ */
+static inline void i2s_ll_tx_pdm_dma_take_mode(i2s_dev_t *hw, bool is_mono, bool is_fst_valid)
+{
+    hw->tx_conf.tx_mono = is_mono;
+    hw->tx_conf.tx_mono_fst_vld = is_fst_valid;
+}
+
+/**
+ * @brief PDM TX slot mode
+ * @note     Mode     Left Slot       Right Slot      Chan Mode       WS Pol
+ *          -----------------------------------------------------------------
+ *           Stereo   Left            Right           0               x
+ *          -----------------------------------------------------------------
+ *           Mono     Left            Left            1               0
+ *           Mono     Right           Right           2               0
+ *           Mono     Single          Right           3               0
+ *           Mono     Left            Single          4               0
+ *          -----------------------------------------------------------------
+ *           Mono     Right           Right           1               1
+ *           Mono     Left            Left            2               1
+ *           Mono     Left            Single          3               1
+ *           Mono     Single          Right           4               1
+ * @note  The 'Single' above means always sending the value of `conf_single_data` reg
+ *        The default value of `conf_single_data` reg is '0', it is not public for now
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param is_mono   The DMA data only has one slot (mono) or contains two slots (stereo)
+ * @param is_copy   Whether the un-selected slot copies the data from the selected one
+ *                  If not, the un-selected slot will transmit the data from 'conf_single_data'
+ * @param mask      The slot mask to select the slot
+ */
+static inline void i2s_ll_tx_pdm_slot_mode(i2s_dev_t *hw, bool is_mono, bool is_copy, i2s_pdm_slot_mask_t mask)
+{
+    if (is_mono) {
+        /* The default tx_ws_idle_pol is false */
+        if (is_copy) {
+            hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 1 : 2;
+        } else {
+            hw->tx_conf.tx_chan_mod = mask == I2S_PDM_SLOT_LEFT ? 4 : 3;
+        }
+    } else {
+        hw->tx_conf.tx_chan_mod = 0;
+    }
+}
+
+/**
+ * @brief PDM TX line mode
+ * @note    Mode         DAC Mode        2 lines output
+ *          -------------------------------------------
+ *          PDM codec    0               1
+ *          DAC 1-line   1               0
+ *          DAC 2-line   1               1
+ *
+ * @param hw    Peripheral I2S hardware instance address.
+ * @param line_mode    PDM TX line mode
+ */
+static inline void i2s_ll_tx_pdm_line_mode(i2s_dev_t *hw, i2s_pdm_tx_line_mode_t line_mode)
+{
+    hw->tx_pcm2pdm_conf.tx_pdm_dac_mode_en = line_mode > I2S_PDM_TX_ONE_LINE_CODEC;
+    hw->tx_pcm2pdm_conf.tx_pdm_dac_2out_en = line_mode != I2S_PDM_TX_ONE_LINE_DAC;
+}
+
+/**
+ * @brief  Reset TX FIFO synchronization counter
+ *
+ * @param hw    Peripheral I2S hardware instance address.
+ */
+__attribute__((always_inline))
+static inline void i2s_ll_tx_reset_fifo_sync_counter(i2s_dev_t *hw)
+{
+    hw->fifo_cnt.tx_fifo_cnt_rst = 1;
+    hw->fifo_cnt.tx_fifo_cnt_rst = 0;
+}
+
+/**
+ * @brief Get TX FIFO synchronization count value
+ *
+ * @param hw    Peripheral I2S hardware instance address.
+ * @return
+ *      bclk count value
+ */
+__attribute__((always_inline))
+static inline uint32_t i2s_ll_tx_get_fifo_sync_count(i2s_dev_t *hw)
+{
+    return hw->fifo_cnt.tx_fifo_cnt;
+}
+
+/**
+ * @brief  Reset TX bclk synchronization counter
+ *
+ * @param hw    Peripheral I2S hardware instance address.
+ */
+__attribute__((always_inline))
+static inline void i2s_ll_tx_reset_bclk_sync_counter(i2s_dev_t *hw)
+{
+    hw->bck_cnt.tx_bck_cnt_rst = 1;
+    hw->bck_cnt.tx_bck_cnt_rst = 0;
+}
+
+/**
+ * @brief Get TX bclk synchronization count value
+ *
+ * @param hw    Peripheral I2S hardware instance address.
+ * @return
+ *      fifo count value
+ */
+__attribute__((always_inline))
+static inline uint32_t i2s_ll_tx_get_bclk_sync_count(i2s_dev_t *hw)
+{
+    return hw->bck_cnt.tx_bck_cnt;
+}
+
+/**
+ * @brief Set the TX ETM threshold of REACH_THRESH event
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param thresh The threshold that send, in words (4 bytes)
+ */
+static inline void i2s_ll_tx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
+{
+    hw->etm_conf.etm_tx_send_word_num = thresh;
+}
+
+/**
+ * @brief Set the RX ETM threshold of REACH_THRESH event
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @param thresh The threshold that received, in words (4 bytes)
+ */
+static inline void i2s_ll_rx_set_etm_threshold(i2s_dev_t *hw, uint32_t thresh)
+{
+    hw->etm_conf.etm_rx_receive_word_num = thresh;
+}
+
+/**
+ * @brief Get I2S ETM TX done event status
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return
+ *      - true  TX done event triggered
+ *      - false TX done event not triggered
+ */
+static inline bool i2s_ll_get_etm_tx_done_event_status(i2s_dev_t *hw)
+{
+    uint32_t i2s_id = I2S_LL_GET_ID(hw);
+    switch (i2s_id) {
+        case 0:
+            return SOC_ETM.evt_st2.i2s0_evt_tx_done_st;
+        default:
+            HAL_ASSERT(false);
+    }
+}
+
+/**
+ * @brief Get I2S ETM TX done event status
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return
+ *      - true  TX done event triggered
+ *      - false TX done event not triggered
+ */
+static inline bool i2s_ll_get_etm_rx_done_event_status(i2s_dev_t *hw)
+{
+    uint32_t i2s_id = I2S_LL_GET_ID(hw);
+    switch (i2s_id) {
+        case 0:
+            return SOC_ETM.evt_st2.i2s0_evt_rx_done_st;
+        default:
+            HAL_ASSERT(false);
+    }
+}
+
+/**
+ * @brief Get I2S ETM TX done event status
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return
+ *      - true  TX done event triggered
+ *      - false TX done event not triggered
+ */
+static inline bool i2s_ll_get_etm_tx_threshold_event_status(i2s_dev_t *hw)
+{
+    uint32_t i2s_id = I2S_LL_GET_ID(hw);
+    switch (i2s_id) {
+        case 0:
+            return SOC_ETM.evt_st2.i2s0_evt_x_words_sent_st;
+        default:
+            HAL_ASSERT(false);
+    }
+}
+
+/**
+ * @brief Get I2S ETM TX done event status
+ *
+ * @param hw Peripheral I2S hardware instance address.
+ * @return
+ *      - true  TX done event triggered
+ *      - false TX done event not triggered
+ */
+static inline bool i2s_ll_get_etm_rx_threshold_event_status(i2s_dev_t *hw)
+{
+    uint32_t i2s_id = I2S_LL_GET_ID(hw);
+    switch (i2s_id) {
+        case 0:
+            return SOC_ETM.evt_st2.i2s0_evt_x_words_received_st;
+        default:
+            HAL_ASSERT(false);
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h
index 9e94417baa8..1c17305864f 100644
--- a/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h
+++ b/components/hal/esp32c61/include/hal/regi2c_ctrl_ll.h
@@ -21,20 +21,36 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
     MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
 /**
  * @brief Force enable analog I2C master clock
  */
diff --git a/components/hal/esp32c61/include/hal/sar_ctrl_ll.h b/components/hal/esp32c61/include/hal/sar_ctrl_ll.h
new file mode 100644
index 00000000000..48d511dd3c0
--- /dev/null
+++ b/components/hal/esp32c61/include/hal/sar_ctrl_ll.h
@@ -0,0 +1,73 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * SAR related peripherals are interdependent.
+ * Related peripherals are:
+ * - ADC
+ * - PWDET
+ *
+ * All of above peripherals require SAR to work correctly.
+ * As SAR has some registers that will influence above mentioned peripherals.
+ * This file gives an abstraction for such registers
+ */
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "soc/apb_saradc_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PWDET_LL_SAR_POWER_FORCE_BIT BIT(24)
+#define PWDET_LL_SAR_POWER_CNTL_BIT  BIT(23)
+
+
+typedef enum {
+    SAR_CTRL_LL_POWER_FSM,     //SAR power controlled by FSM
+    SAR_CTRL_LL_POWER_ON,      //SAR power on
+    SAR_CTRL_LL_POWER_OFF,     //SAR power off
+} sar_ctrl_ll_power_t;
+
+/*---------------------------------------------------------------
+                    SAR power control
+---------------------------------------------------------------*/
+/**
+ * @brief Set SAR power mode when controlled by PWDET
+ *
+ * @param[in] mode  See `sar_ctrl_ll_power_t`
+ */
+__attribute__((always_inline))
+static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
+{
+    if (mode == SAR_CTRL_LL_POWER_FSM) {
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
+    } else if (mode == SAR_CTRL_LL_POWER_ON) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
+    } else if (mode == SAR_CTRL_LL_POWER_OFF) {
+        REG_SET_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_FORCE_BIT);
+        REG_CLR_BIT(PWDET_CONF_REG, PWDET_LL_SAR_POWER_CNTL_BIT);
+    }
+}
+
+/**
+ * @brief Set SAR power ctrl source
+ *
+ * @param[in] force  set PWDET as SAR power ctrl source when force is true
+ */
+static inline void sar_ctrl_ll_force_power_ctrl_from_pwdet(bool force)
+{
+    ADC.saradc_ctrl.saradc_saradc2_pwdet_drv = force;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32c61/include/hal/uart_ll.h b/components/hal/esp32c61/include/hal/uart_ll.h
index 2a6a014108f..5910cad8afe 100644
--- a/components/hal/esp32c61/include/hal/uart_ll.h
+++ b/components/hal/esp32c61/include/hal/uart_ll.h
@@ -64,10 +64,6 @@ extern "C" {
     ((hw) == &UART1) ? PCR.uart1_##reg_suffix.uart1_##field_suffix : \
     PCR.uart2_##reg_suffix.uart2_##field_suffix)
 
-// UART sleep retention module
-#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
-                                                     (uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : -1)
-
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1 << 0),
@@ -445,7 +441,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 {
-    return hw->status.rxfifo_cnt;
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
 }
 
 /**
@@ -457,7 +453,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 {
-    return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
+    return UART_LL_FIFO_DEF_LEN - HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt);
 }
 
 /**
@@ -532,7 +528,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_
  */
 FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
 {
-    hw->conf1.rxfifo_full_thrhd = full_thrhd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd);
 }
 
 /**
@@ -546,7 +542,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full
  */
 FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
 {
-    hw->conf1.txfifo_empty_thrhd = empty_thrhd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd);
 }
 
 /**
@@ -610,7 +606,7 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
 {
     //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
     if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
-        hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs);
         hw->hwfc_conf_sync.rx_flow_en = 1;
     } else {
         hw->hwfc_conf_sync.rx_flow_en = 0;
@@ -656,10 +652,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
     if (sw_flow_ctrl_en) {
         hw->swfc_conf0_sync.xonoff_del = 1;
         hw->swfc_conf0_sync.sw_flow_con_en = 1;
-        hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
-        hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd;
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, flow_ctrl->xon_thrd);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, flow_ctrl->xoff_thrd);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->swfc_conf0_sync.sw_flow_con_en = 0;
         hw->swfc_conf0_sync.xonoff_del = 0;
@@ -683,7 +679,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
@@ -895,7 +891,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num);
 }
 
 /**
@@ -932,7 +928,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length
  */
 FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
 {
-    return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0));
+    return ((HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) == 0) && (hw->fsm_status.st_utx_out == 0));
 }
 
 /**
diff --git a/components/hal/esp32c61/modem_clock_hal.c b/components/hal/esp32c61/modem_clock_hal.c
index fe84dcfb850..3af99192403 100644
--- a/components/hal/esp32c61/modem_clock_hal.c
+++ b/components/hal/esp32c61/modem_clock_hal.c
@@ -101,12 +101,9 @@ uint32_t IRAM_ATTR modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_c
     return bitmap;
 }
 
-void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
 {
     if (enable) {
-        modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
-        modem_syscon_ll_enable_fe_dac_clock(hal->syscon_dev, enable);
-        modem_syscon_ll_enable_fe_pwdet_clock(hal->syscon_dev, enable);
         modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
         modem_syscon_ll_enable_fe_80m_clock(hal->syscon_dev, enable);
     }
@@ -116,6 +113,9 @@ void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_con
 {
     if (enable) {
         modem_syscon_ll_enable_fe_160m_clock(hal->syscon_dev, enable);
+        modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
+        modem_syscon_ll_enable_fe_dac_clock(hal->syscon_dev, enable);
+        modem_syscon_ll_enable_fe_pwdet_clock(hal->syscon_dev, enable);
     }
 }
 
diff --git a/components/hal/esp32h2/include/hal/adc_ll.h b/components/hal/esp32h2/include/hal/adc_ll.h
index ab7f8fa58f6..9b0210a341d 100644
--- a/components/hal/esp32h2/include/hal/adc_ll.h
+++ b/components/hal/esp32h2/include/hal/adc_ll.h
@@ -129,7 +129,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 
@@ -566,7 +566,6 @@ static inline void adc_ll_enable_bus_clock(bool enable)
     PCR.saradc_conf.saradc_reg_clk_en = enable;
 }
 
-#if SOC_RCC_IS_INDEPENDENT
 /**
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
@@ -575,7 +574,6 @@ static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
 }
-#endif
 
 /**
  * @brief Reset ADC module
diff --git a/components/hal/esp32h2/include/hal/brownout_ll.h b/components/hal/esp32h2/include/hal/brownout_ll.h
index 6553c8bd141..9dce284ac8b 100644
--- a/components/hal/esp32h2/include/hal/brownout_ll.h
+++ b/components/hal/esp32h2/include/hal/brownout_ll.h
@@ -69,7 +69,8 @@ static inline void brownout_ll_reset_config(bool reset_ena, uint32_t reset_wait,
  */
 static inline void brownout_ll_set_threshold(uint8_t threshold)
 {
-    REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD, threshold);
+    REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD_L, threshold);
+    REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD_H, threshold);
 }
 
 /**
diff --git a/components/hal/esp32h2/include/hal/clk_gate_ll.h b/components/hal/esp32h2/include/hal/clk_gate_ll.h
index 3eef499230d..7ac7b7d7fcd 100644
--- a/components/hal/esp32h2/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32h2/include/hal/clk_gate_ll.h
@@ -38,7 +38,7 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
             return PCR_I2C0_CLK_EN;
         case PERIPH_I2C1_MODULE:
             return PCR_I2C1_CLK_EN;
-        case PERIPH_I2S1_MODULE:
+        case PERIPH_I2S0_MODULE:
             return PCR_I2S_CLK_EN;
         case PERIPH_TIMG0_MODULE:
             return PCR_TG0_CLK_EN;
@@ -119,7 +119,7 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
             return PCR_I2C0_RST_EN;
         case PERIPH_I2C1_MODULE:
             return PCR_I2C1_RST_EN;
-        case PERIPH_I2S1_MODULE:
+        case PERIPH_I2S0_MODULE:
             return PCR_I2S_RST_EN;
         case PERIPH_TIMG0_MODULE:
             return PCR_TG0_RST_EN;
@@ -224,7 +224,7 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
             return PCR_I2C0_CONF_REG;
         case PERIPH_I2C1_MODULE:
             return PCR_I2C1_CONF_REG;
-        case PERIPH_I2S1_MODULE:
+        case PERIPH_I2S0_MODULE:
             return PCR_I2S_CONF_REG;
         case PERIPH_TIMG0_MODULE:
             return PCR_TIMERGROUP0_CONF_REG;
@@ -291,7 +291,7 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
             return PCR_I2C0_CONF_REG;
         case PERIPH_I2C1_MODULE:
             return PCR_I2C1_CONF_REG;
-        case PERIPH_I2S1_MODULE:
+        case PERIPH_I2S0_MODULE:
             return PCR_I2S_CONF_REG;
         case PERIPH_TIMG0_MODULE:
             return PCR_TIMERGROUP0_CONF_REG;
diff --git a/components/hal/esp32h2/include/hal/gpio_ll.h b/components/hal/esp32h2/include/hal/gpio_ll.h
index be799df2146..8a7cfd448bd 100644
--- a/components/hal/esp32h2/include/hal/gpio_ll.h
+++ b/components/hal/esp32h2/include/hal/gpio_ll.h
@@ -377,9 +377,9 @@ __attribute__((always_inline))
 static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level)
 {
     if (level) {
-        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+        hw->out_w1ts.val = 1 << gpio_num;
     } else {
-        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+        hw->out_w1tc.val = 1 << gpio_num;
     }
 }
 
diff --git a/components/hal/esp32h2/include/hal/i2c_ll.h b/components/hal/esp32h2/include/hal/i2c_ll.h
index d636cc0c719..3a625302ce4 100644
--- a/components/hal/esp32h2/include/hal/i2c_ll.h
+++ b/components/hal/esp32h2/include/hal/i2c_ll.h
@@ -76,8 +76,7 @@ typedef enum {
 #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT   (9)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2500)  // Approximate value for SCL timeout regs (in us).
 
-// I2C sleep retention module
-#define I2C_SLEEP_RETENTION_MODULE(i2c_num) ((i2c_num == 0) ? SLEEP_RETENTION_MODULE_I2C0 : SLEEP_RETENTION_MODULE_I2C1)
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff)
 
 /**
  * @brief  Calculate I2C bus frequency
@@ -866,6 +865,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    dev->scl_stretch_conf.stretch_protect_num = protect_num;
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -894,6 +903,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->sr.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32h2/include/hal/i2s_ll.h b/components/hal/esp32h2/include/hal/i2s_ll.h
index 15de741213a..e640c8d5f49 100644
--- a/components/hal/esp32h2/include/hal/i2s_ll.h
+++ b/components/hal/esp32h2/include/hal/i2s_ll.h
@@ -395,7 +395,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 
 /**
  * @brief Configure I2S RX module clock divider
- * @note mclk on ESP32 is shared by both TX and RX channel
+ * @note mclk on ESP32H2 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
  * @param mclk_div The mclk division coefficients
diff --git a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h
index 179fd2db3ed..7c35b6eafcf 100644
--- a/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h
+++ b/components/hal/esp32h2/include/hal/regi2c_ctrl_ll.h
@@ -20,20 +20,36 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
     MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
 /**
  * @brief Force enable analog I2C master clock
  */
diff --git a/components/hal/esp32h2/include/hal/rmt_ll.h b/components/hal/esp32h2/include/hal/rmt_ll.h
index a3179addba5..4ebb3a1e062 100644
--- a/components/hal/esp32h2/include/hal/rmt_ll.h
+++ b/components/hal/esp32h2/include/hal/rmt_ll.h
@@ -38,8 +38,6 @@ extern "C" {
 #define RMT_LL_MAX_FILTER_VALUE           255
 #define RMT_LL_MAX_IDLE_VALUE             32767
 
-#define RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id) (SLEEP_RETENTION_MODULE_RMT0)
-
 typedef enum {
     RMT_LL_MEM_OWNER_SW = 0,
     RMT_LL_MEM_OWNER_HW = 1,
diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h
index 4fa29d216f3..f9abd2c260a 100644
--- a/components/hal/esp32h2/include/hal/uart_ll.h
+++ b/components/hal/esp32h2/include/hal/uart_ll.h
@@ -57,10 +57,6 @@ extern "C" {
 #define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix)  \
     (((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
 
-// UART sleep retention module
-#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
-                                                     (uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : -1)
-
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1 << 0),
@@ -94,14 +90,14 @@ typedef enum {
  */
 FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
 {
-    uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
-                                    (uart_num == 1) ? PCR_UART1_CONF_REG : 0);
-    uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
-                            (uart_num == 1) ? PCR_UART1_RST_EN : 0);
-    uint32_t uart_en_bit  = ((uart_num == 0) ? PCR_UART0_CLK_EN :
-                            (uart_num == 1) ? PCR_UART1_CLK_EN : 0);
-    return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
-        REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
+    switch (uart_num) {
+    case 0:
+        return PCR.uart0_conf.uart0_clk_en && !PCR.uart0_conf.uart0_rst_en;
+    case 1:
+        return PCR.uart1_conf.uart1_clk_en && !PCR.uart1_conf.uart1_rst_en;
+    default:
+        return false;
+    }
 }
 
 /**
@@ -194,18 +190,18 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
 FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
 {
     switch (source_clk) {
-        case UART_SCLK_PLL_F48M:
-            UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
-            break;
-        case UART_SCLK_RTC:
-            UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2);
-            break;
-        case UART_SCLK_XTAL:
-            UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3);
-            break;
-        default:
-            // Invalid UART clock source
-            abort();
+    case UART_SCLK_PLL_F48M:
+        UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
+        break;
+    case UART_SCLK_RTC:
+        UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2);
+        break;
+    case UART_SCLK_XTAL:
+        UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3);
+        break;
+    default:
+        // Invalid UART clock source
+        abort();
     }
 }
 
@@ -220,16 +216,16 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
 FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
 {
     switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
-        default:
-        case 1:
-            *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M;
-            break;
-        case 2:
-            *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
-            break;
-        case 3:
-            *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
-            break;
+    default:
+    case 1:
+        *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M;
+        break;
+    case 2:
+        *source_clk = (soc_module_clk_t)UART_SCLK_RTC;
+        break;
+    case 3:
+        *source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
+        break;
     }
 }
 
@@ -248,7 +244,9 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
     const uint32_t max_div = BIT(12) - 1;   // UART divider integer part only has 12 bits
     uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
 
-    if (sclk_div == 0) abort();
+    if (sclk_div == 0) {
+        abort();
+    }
 
     uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
     // The baud rate configuration register is divided into
@@ -424,7 +422,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 {
-    return hw->status.rxfifo_cnt;
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
 }
 
 /**
@@ -436,7 +434,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 {
-    return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
+    return UART_LL_FIFO_DEF_LEN - HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt);
 }
 
 /**
@@ -511,7 +509,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_
  */
 FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
 {
-    hw->conf1.rxfifo_full_thrhd = full_thrhd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd);
 }
 
 /**
@@ -525,7 +523,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full
  */
 FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
 {
-    hw->conf1.txfifo_empty_thrhd = empty_thrhd;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd);
 }
 
 /**
@@ -589,7 +587,7 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
 {
     //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
     if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
-        hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs;
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs);
         hw->hwfc_conf_sync.rx_flow_en = 1;
     } else {
         hw->hwfc_conf_sync.rx_flow_en = 0;
@@ -635,10 +633,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
     if (sw_flow_ctrl_en) {
         hw->swfc_conf0_sync.xonoff_del = 1;
         hw->swfc_conf0_sync.sw_flow_con_en = 1;
-        hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
-        hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd;
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, flow_ctrl->xon_thrd);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, flow_ctrl->xoff_thrd);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->swfc_conf0_sync.sw_flow_con_en = 0;
         hw->swfc_conf0_sync.xonoff_del = 0;
@@ -662,7 +660,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
@@ -844,22 +842,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
 FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 {
     switch (mode) {
-        default:
-        case UART_MODE_UART:
-            uart_ll_set_mode_normal(hw);
-            break;
-        case UART_MODE_RS485_COLLISION_DETECT:
-            uart_ll_set_mode_collision_detect(hw);
-            break;
-        case UART_MODE_RS485_APP_CTRL:
-            uart_ll_set_mode_rs485_app_ctrl(hw);
-            break;
-        case UART_MODE_RS485_HALF_DUPLEX:
-            uart_ll_set_mode_rs485_half_duplex(hw);
-            break;
-        case UART_MODE_IRDA:
-            uart_ll_set_mode_irda(hw);
-            break;
+    default:
+    case UART_MODE_UART:
+        uart_ll_set_mode_normal(hw);
+        break;
+    case UART_MODE_RS485_COLLISION_DETECT:
+        uart_ll_set_mode_collision_detect(hw);
+        break;
+    case UART_MODE_RS485_APP_CTRL:
+        uart_ll_set_mode_rs485_app_ctrl(hw);
+        break;
+    case UART_MODE_RS485_HALF_DUPLEX:
+        uart_ll_set_mode_rs485_half_duplex(hw);
+        break;
+    case UART_MODE_IRDA:
+        uart_ll_set_mode_irda(hw);
+        break;
     }
 }
 
@@ -875,7 +873,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num);
 }
 
 /**
@@ -912,7 +910,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length
  */
 FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
 {
-    return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0));
+    return ((HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) == 0) && (hw->fsm_status.st_utx_out == 0));
 }
 
 /**
@@ -957,7 +955,7 @@ FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
 {
     hw->swfc_conf0_sync.force_xon = 1;
     uart_ll_update(hw);
-    if(!always_on) {
+    if (!always_on) {
         hw->swfc_conf0_sync.force_xon = 0;
         uart_ll_update(hw);
     }
@@ -1003,7 +1001,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
 FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
 {
     uint16_t tout_val = tout_thrd;
-    if(tout_thrd > 0) {
+    if (tout_thrd > 0) {
         hw->tout_conf_sync.rx_tout_thrhd = tout_val;
         hw->tout_conf_sync.rx_tout_en = 1;
     } else {
@@ -1022,7 +1020,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
 FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
 {
     uint16_t tout_thrd = 0;
-    if(hw->tout_conf_sync.rx_tout_en > 0) {
+    if (hw->tout_conf_sync.rx_tout_en > 0) {
         tout_thrd = hw->tout_conf_sync.rx_tout_thrhd;
     }
     return tout_thrd;
diff --git a/components/hal/esp32h2/modem_clock_hal.c b/components/hal/esp32h2/modem_clock_hal.c
index 879e694d2a4..851e0c01ffc 100644
--- a/components/hal/esp32h2/modem_clock_hal.c
+++ b/components/hal/esp32h2/modem_clock_hal.c
@@ -19,7 +19,7 @@ typedef enum {
     MODEM_CLOCK_EXT32K_CODE  = 2
 } modem_clock_32k_clk_src_code_t;
 
-void IRAM_ATTR modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
 {
     modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
     modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable);
diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h
index 17745bb07ad..b8308260393 100644
--- a/components/hal/esp32p4/include/hal/adc_ll.h
+++ b/components/hal/esp32p4/include/hal/adc_ll.h
@@ -135,7 +135,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
  */
 static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
 {
-    /* Peripheral reg i2c has powered up in rtc_init, write directly */
+    /* Analog i2c master clock needs to be enabled for regi2c operations (done inside REGI2C_WRITE_MASK) */
     REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
 }
 
diff --git a/components/hal/esp32p4/include/hal/brownout_ll.h b/components/hal/esp32p4/include/hal/brownout_ll.h
index 8327f9f8901..96224c63adb 100644
--- a/components/hal/esp32p4/include/hal/brownout_ll.h
+++ b/components/hal/esp32p4/include/hal/brownout_ll.h
@@ -17,6 +17,8 @@
 #include "hal/regi2c_ctrl.h"
 #include "hal/psdet_types.h"
 #include "soc/regi2c_brownout.h"
+#include "hal/efuse_hal.h"
+#include "soc/chip_revision.h"
 
 #define BROWNOUT_DETECTOR_LL_FIB_ENABLE       (BIT(1))
 
@@ -68,7 +70,11 @@ static inline void brownout_ll_reset_config(bool reset_ena, uint32_t reset_wait,
  */
 static inline void brownout_ll_set_threshold(uint8_t threshold)
 {
-    REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD, threshold);
+    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
+        threshold = 0; // Fix this level as 0 so that on v0.x brownout value will be fixed around 2.52v.
+    }
+    REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD_L, threshold);
+    REGI2C_WRITE_MASK(I2C_BOD, I2C_BOD_THRESHOLD_H, threshold);
 }
 
 /**
diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h
index 8c5fc05cfbf..9a49fd41e01 100644
--- a/components/hal/esp32p4/include/hal/clk_gate_ll.h
+++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h
@@ -14,6 +14,7 @@ extern "C" {
 #include <stdbool.h>
 #include "esp_attr.h"
 #include "soc/hp_sys_clkrst_struct.h"
+#include "soc/lp_clkrst_struct.h"
 
 /**
  * Enable or disable the clock gate for ref_20m.
@@ -75,6 +76,18 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_240m_clk_en(bool enable)
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
 #define clk_gate_ll_ref_240m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_240m_clk_en(__VA_ARGS__)
 
+/**
+ * Enable or disable the clock gate for xtal to lp periph
+ * @param  enable Enable / disable
+ */
+FORCE_INLINE_ATTR void _clk_gate_ll_xtal_to_lp_periph_en(bool enable)
+{
+    LP_AON_CLKRST.lp_clk_en.xtal_clk_force_on = enable;
+}
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define clk_gate_ll_xtal_to_lp_periph_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_xtal_to_lp_periph_en(__VA_ARGS__)
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h
index 3a6ad120240..3a15c02e4f7 100644
--- a/components/hal/esp32p4/include/hal/clk_tree_ll.h
+++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h
@@ -40,6 +40,7 @@ extern "C" {
 #define CLK_LL_PLL_80M_FREQ_MHZ    (80)
 #define CLK_LL_PLL_160M_FREQ_MHZ   (160)
 #define CLK_LL_PLL_240M_FREQ_MHZ   (240)
+#define CLK_LL_PLL_SDIO_FREQ_MHZ   (200)
 
 #define CLK_LL_PLL_360M_FREQ_MHZ   (360)
 #define CLK_LL_PLL_400M_FREQ_MHZ   (400)
@@ -347,7 +348,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_cpll_get_freq_mhz(u
     unsigned chip_version = efuse_hal_chip_revision();
     if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
         return xtal_freq_mhz * (div + 4) / (ref_div + 1);
-    } else
+    }
     return xtal_freq_mhz * div / (ref_div + 1);
 }
 
diff --git a/components/hal/esp32p4/include/hal/efuse_ll.h b/components/hal/esp32p4/include/hal/efuse_ll.h
index c287b964dc6..11fd66c61d0 100644
--- a/components/hal/esp32p4/include/hal/efuse_ll.h
+++ b/components/hal/esp32p4/include/hal/efuse_ll.h
@@ -73,7 +73,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
 {
-    return EFUSE.rd_mac_sys_2.disable_blk_version_major;
+    return EFUSE.rd_mac_sys_2.blk_version_major;
 }
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
@@ -83,7 +83,7 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_m
 
 __attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
 {
-    return EFUSE.rd_mac_sys_2.blk_version_major;
+    return EFUSE.rd_mac_sys_2.disable_blk_version_major;
 }
 
 __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
diff --git a/components/hal/esp32p4/include/hal/emac_ll.h b/components/hal/esp32p4/include/hal/emac_ll.h
index 33a5ed8a5c9..2dfca8d166c 100644
--- a/components/hal/esp32p4/include/hal/emac_ll.h
+++ b/components/hal/esp32p4/include/hal/emac_ll.h
@@ -20,6 +20,8 @@
 #include "hal/eth_types.h"
 #include "soc/emac_dma_struct.h"
 #include "soc/emac_mac_struct.h"
+#include "soc/emac_ptp_struct.h"
+#include "soc/clk_tree_defs.h"
 
 #include "soc/hp_system_struct.h"
 #include "soc/hp_sys_clkrst_struct.h"
@@ -90,22 +92,14 @@ extern "C" {
 #define EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_3_1 (2)
 #define EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_4_1 (3)
 
-/* PTP register bits */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U                      /* SYNC message (all clock types) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U                  /* FollowUp message (all clock types) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U                  /* DelayReq message (all clock types) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U                 /* DelayResp message (all clock types) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U        /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U          /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock)  */
-#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
-
-#define EMAC_LL_DMAPTPRXDESC_IPPT_UDP 0x00000001U  /* UDP payload encapsulated in the IP datagram */
-#define EMAC_LL_DMAPTPRXDESC_IPPT_TCP 0x00000002U  /* TCP payload encapsulated in the IP datagram */
-#define EMAC_LL_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
-
 #define EMAC_LL_DMADESC_OWNER_CPU  (0)
 #define EMAC_LL_DMADESC_OWNER_DMA  (1)
 
+/* Time stamp status flags */
+#define EMAC_LL_TS_SECONDS_OVERFLOW                    0x00000001U
+#define EMAC_LL_TS_TARGET_TIME_REACHED                 0x00000002U
+#define EMAC_LL_TS_TARGET_TIME_ERROR                   0x00000008U
+
 /* Interrupt flags (referring to dmastatus register in emac_dma_struct.h) */
 #define EMAC_LL_DMA_TRANSMIT_FINISH_INTR               0x00000001U
 #define EMAC_LL_DMA_TRANSMIT_STOP_INTR                 0x00000002U
@@ -125,7 +119,7 @@ extern "C" {
 #define EMAC_LL_DMA_POWER_MANAGE_INTR                  0x10000000U
 #define EMAC_LL_DMA_TIMESTAMP_TRIGGER_INTR             0x20000000U
 
-/* Interrupt enable (referring to dmain_en register in emac_dma_struct.h) */
+/* DMA Interrupt enable (referring to dmain_en register in emac_dma_struct.h) */
 #define EMAC_LL_INTR_TRANSMIT_ENABLE                    0x00000001U
 #define EMAC_LL_INTR_TRANSMIT_STOP_ENABLE               0x00000002U
 #define EMAC_LL_INTR_TRANSMIT_BUFF_UNAVAILABLE_ENABLE   0x00000004U
@@ -142,9 +136,17 @@ extern "C" {
 #define EMAC_LL_INTR_ABNORMAL_SUMMARY_ENABLE            0x00008000U
 #define EMAC_LL_INTR_NORMAL_SUMMARY_ENABLE              0x00010000U
 
-/* Enable needed interrupts (recv/recv_buf_unavailabal/normal must be enabled to make eth work) */
+/* EMAC interrupt enable (referring to emacintmask register in emac_mac_struct.h)*/
+#define EMAC_LL_MAC_INTR_LOW_POWER_IDLE_ENABLE         0x00000400U
+#define EMAC_LL_MAC_INTR_TIME_STAMP_ENABLE             0x00000200U
+#define EMAC_LL_MAC_INTR_POWER_MANAGEMENT_MOD_ENABLE   0x00000008U
+
+/* Enable needed DMA interrupts (recv/recv_buf_unavailabal/normal must be enabled to make eth work) */
 #define EMAC_LL_CONFIG_ENABLE_INTR_MASK    (EMAC_LL_INTR_RECEIVE_ENABLE | EMAC_LL_INTR_NORMAL_SUMMARY_ENABLE)
 
+/* Enable needed MAC interrupts */
+#define EMAC_LL_CONFIG_ENABLE_MAC_INTR_MASK  (EMAC_LL_MAC_INTR_TIME_STAMP_ENABLE)
+
 /************** Start of mac regs operation ********************/
 /* emacgmiiaddr */
 static inline void emac_ll_set_csr_clock_division(emac_mac_dev_t *mac_regs, uint32_t div_mode)
@@ -373,6 +375,22 @@ static inline void emac_ll_set_addr(emac_mac_dev_t *mac_regs, const uint8_t *add
     HAL_FORCE_MODIFY_U32_REG_FIELD(mac_regs->emacaddr0high, address0_hi, (addr[5] << 8) | addr[4]);
     mac_regs->emacaddr0low = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | (addr[0]);
 }
+
+/* emacintmask */
+static inline void emac_ll_enable_corresponding_emac_intr(emac_mac_dev_t *mac_regs, uint32_t mask)
+{
+    uint32_t temp_mask = mac_regs->emacintmask.val;
+    temp_mask &= ~mask;
+    mac_regs->emacintmask.val = temp_mask;
+}
+
+static inline void emac_ll_disable_corresponding_emac_intr(emac_mac_dev_t *mac_regs, uint32_t mask)
+{
+    uint32_t temp_mask = mac_regs->emacintmask.val;
+    temp_mask |= mask;
+    mac_regs->emacintmask.val = temp_mask;
+}
+
 /*************** End of mac regs operation *********************/
 
 
@@ -535,12 +553,17 @@ static inline void emac_ll_disable_all_intr(emac_dma_dev_t *dma_regs)
 
 static inline void emac_ll_enable_corresponding_intr(emac_dma_dev_t *dma_regs, uint32_t mask)
 {
-    dma_regs->dmain_en.val |= mask;
+    uint32_t temp_mask = dma_regs->dmain_en.val;
+    temp_mask |= mask;
+    dma_regs->dmain_en.val = temp_mask;
+
 }
 
 static inline void emac_ll_disable_corresponding_intr(emac_dma_dev_t *dma_regs, uint32_t mask)
 {
-    dma_regs->dmain_en.val &= ~mask;
+    uint32_t temp_mask = dma_regs->dmain_en.val;
+    temp_mask &= ~mask;
+    dma_regs->dmain_en.val = temp_mask;
 }
 
 static inline uint32_t emac_ll_get_intr_enable_status(emac_dma_dev_t *dma_regs)
@@ -577,6 +600,175 @@ static inline void emac_ll_receive_poll_demand(emac_dma_dev_t *dma_regs, uint32_
 
 /*************** End of dma regs operation *********************/
 
+/************** Start of ptp regs operation ********************/
+static inline uint32_t emac_ll_get_ts_status(emac_ptp_dev_t *ptp_regs)
+{
+    return ptp_regs->status.val;
+}
+
+/* basic control and setting */
+static inline void emac_ll_ts_enable(emac_ptp_dev_t *ptp_regs, bool enable)
+{
+    ptp_regs->timestamp_ctrl.en_timestamp = enable;
+}
+
+static inline void emac_ll_ts_ptp_ip4_enable(emac_ptp_dev_t *ptp_regs, bool enable)
+{
+    ptp_regs->timestamp_ctrl.en_proc_ptp_ipv4_udp = enable;
+}
+
+static inline void emac_ll_ts_ptp_ether_enable(emac_ptp_dev_t *ptp_regs, bool enable)
+{
+    ptp_regs->timestamp_ctrl.en_proc_ptp_ether_frm = enable;
+}
+
+static inline void emac_ll_ts_ptp_snap_type_sel(emac_ptp_dev_t *ptp_regs, uint8_t sel)
+{
+    ptp_regs->timestamp_ctrl.sel_snap_type = sel;
+}
+
+static inline void emac_ll_ts_ptp_snap_master_only_enable(emac_ptp_dev_t *ptp_regs, bool enable)
+{
+    ptp_regs->timestamp_ctrl.en_snap_msg_relevant_master = enable;
+}
+
+static inline void emac_ll_ts_ptp_snap_event_only_enable(emac_ptp_dev_t *ptp_regs, bool enable)
+{
+    ptp_regs->timestamp_ctrl.en_ts_snap_event_msg = enable;
+}
+
+static inline void emac_ll_ts_all_enable(emac_ptp_dev_t *ptp_regs, bool enable)
+{
+    ptp_regs->timestamp_ctrl.en_ts4all = enable;
+}
+
+static inline void emac_ll_ptp_v2_proc_enable(emac_ptp_dev_t *ptp_regs, bool enable) {
+    ptp_regs->timestamp_ctrl.en_ptp_pkg_proc_ver2_fmt = enable;
+}
+
+static inline void emac_ll_ts_digital_roll_enable(emac_ptp_dev_t *ptp_regs, bool enable)
+{
+    ptp_regs->timestamp_ctrl.ts_digit_bin_roll_ctrl = enable;
+}
+
+static inline bool emac_ll_is_ts_digital_roll_set(emac_ptp_dev_t *ptp_regs)
+{
+    return ptp_regs->timestamp_ctrl.ts_digit_bin_roll_ctrl;
+}
+
+static inline void emac_ll_set_ts_update_method(emac_ptp_dev_t *ptp_regs, eth_mac_ptp_update_method_t method)
+{
+    if (method == ETH_PTP_UPDATE_METHOD_COARSE) {
+        ptp_regs->timestamp_ctrl.ts_fine_coarse_update = 0;
+    } else {
+        ptp_regs->timestamp_ctrl.ts_fine_coarse_update = 1;
+    }
+}
+
+static inline eth_mac_ptp_update_method_t emac_ll_get_ts_update_method(emac_ptp_dev_t *ptp_regs)
+{
+    if (ptp_regs->timestamp_ctrl.ts_fine_coarse_update == 0) {
+        return ETH_PTP_UPDATE_METHOD_COARSE;
+    }
+    return ETH_PTP_UPDATE_METHOD_FINE;
+}
+
+static inline void emac_ll_ts_init_do(emac_ptp_dev_t *ptp_regs)
+{
+    ptp_regs->timestamp_ctrl.ts_initialize = 1;
+}
+
+static inline bool emac_ll_is_ts_init_done(emac_ptp_dev_t *ptp_regs)
+{
+    return !ptp_regs->timestamp_ctrl.ts_initialize;
+}
+
+/* increment value */
+static inline void emac_ll_set_ts_sub_second_incre_val(emac_ptp_dev_t *ptp_regs, uint8_t increment)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(ptp_regs->sub_sec_incre, sub_second_incre_value, increment);
+}
+
+/* addend control */
+static inline void emac_ll_set_ts_addend_val(emac_ptp_dev_t *ptp_regs, uint32_t val)
+{
+    ptp_regs->timestamp_addend.ts_addend_val = val;
+}
+
+static inline uint32_t emac_ll_get_ts_addend_val(emac_ptp_dev_t *ptp_regs)
+{
+    return ptp_regs->timestamp_addend.ts_addend_val;
+}
+
+static inline void emac_ll_ts_addend_do_update(emac_ptp_dev_t *ptp_regs)
+{
+    ptp_regs->timestamp_ctrl.addend_reg_update = 1;
+}
+
+static inline bool emac_ll_is_ts_addend_update_done(emac_ptp_dev_t *ptp_regs)
+{
+    return !ptp_regs->timestamp_ctrl.addend_reg_update;
+}
+
+/* time update */
+static inline void emac_ll_set_ts_update_second_val(emac_ptp_dev_t *ptp_regs, uint32_t val)
+{
+    ptp_regs->sys_seconds_update.ts_second = val;
+}
+
+static inline void emac_ll_set_ts_update_sub_second_val(emac_ptp_dev_t *ptp_regs, uint32_t val)
+{
+    ptp_regs->sys_nanosec_update.ts_sub_seconds = val;
+}
+
+static inline void emac_ll_ts_update_time_add(emac_ptp_dev_t *ptp_regs)
+{
+    ptp_regs->sys_nanosec_update.add_sub = 0;
+}
+
+static inline void emac_ll_ts_update_time_sub(emac_ptp_dev_t *ptp_regs)
+{
+    ptp_regs->sys_nanosec_update.add_sub = 1;
+}
+
+static inline void emac_ll_ts_update_time_do(emac_ptp_dev_t *ptp_regs)
+{
+    ptp_regs->timestamp_ctrl.ts_update = 1;
+}
+
+static inline bool emac_ll_is_ts_update_time_done(emac_ptp_dev_t *ptp_regs)
+{
+    return !ptp_regs->timestamp_ctrl.ts_update;
+}
+
+/* get time */
+static inline uint32_t emac_ll_get_ts_seconds_val(emac_ptp_dev_t *ptp_regs)
+{
+    return ptp_regs->sys_seconds.ts_second;
+}
+
+static inline uint32_t emac_ll_get_ts_sub_seconds_val(emac_ptp_dev_t *ptp_regs)
+{
+    return ptp_regs->sys_nanosec.ts_sub_seconds;
+}
+
+/* target time control */
+static inline void emac_ll_set_ts_target_second_val(emac_ptp_dev_t *ptp_regs, uint32_t val)
+{
+    ptp_regs->tgt_seconds.tgt_time_second_val = val;
+}
+
+static inline void emac_ll_set_ts_target_sub_second_val(emac_ptp_dev_t *ptp_regs, uint32_t val)
+{
+    ptp_regs->tgt_nanosec.tgt_ts_low_reg = val;
+}
+
+static inline void emac_ll_ts_target_int_trig_enable(emac_ptp_dev_t *ptp_regs)
+{
+    ptp_regs->timestamp_ctrl.en_ts_int_trig = 1;
+}
+
+/************** End of ptp regs operation ********************/
 
 /**
  * @brief Enable the bus clock for the EMAC module
@@ -655,7 +847,7 @@ static inline void emac_ll_clock_enable_rmii_input(void *ext_regs)
     HP_SYS_CLKRST.peri_clk_ctrl00.reg_emac_rx_clk_src_sel = 0; // 0-pad_emac_txrx_clk, 1-pad_emac_rx_clk
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_rx_clk_div_num, 1); // set default divider
 
-    HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_en = 1;
+    HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_en  = 1;
     HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_tx_clk_src_sel = 0; // 0-pad_emac_txrx_clk, 1-pad_emac_tx_clk
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl01, reg_emac_tx_clk_div_num, 1); // set default divider
 
@@ -689,6 +881,30 @@ static inline void emac_ll_clock_enable_rmii_output(void *ext_regs)
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
 #define emac_ll_clock_enable_rmii_output(...) (void)__DECLARE_RCC_ATOMIC_ENV; emac_ll_clock_enable_rmii_output(__VA_ARGS__)
 
+static inline void emac_ll_clock_enable_ptp(void *ext_regs, soc_periph_emac_ptp_clk_src_t clk_src, bool enable)
+{
+    uint8_t clk_src_val;
+
+    switch (clk_src)
+    {
+    case EMAC_PTP_CLK_SRC_XTAL:
+        clk_src_val = 0;
+        break;
+    case EMAC_PTP_CLK_SRC_PLL_F80M:
+        clk_src_val = 1;
+        break;
+    default:
+        clk_src_val = 0;
+        break;
+    }
+    HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_ptp_ref_clk_src_sel = clk_src_val;
+    HP_SYS_CLKRST.peri_clk_ctrl01.reg_emac_ptp_ref_clk_en = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define emac_ll_clock_enable_ptp(...) (void)__DECLARE_RCC_ATOMIC_ENV; emac_ll_clock_enable_ptp(__VA_ARGS__)
+
 static inline void emac_ll_pause_frame_enable(void *ext_regs, bool enable)
 {
     HP_SYSTEM.sys_gmac_ctrl0.sys_phy_intf_sel = enable;
diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h
index b152f9f863e..7fb9bec340d 100644
--- a/components/hal/esp32p4/include/hal/gpio_ll.h
+++ b/components/hal/esp32p4/include/hal/gpio_ll.h
@@ -400,15 +400,15 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t
 {
     if (level) {
         if (gpio_num < 32) {
-            hw->out_w1ts.out_w1ts = (1 << gpio_num);
+            hw->out_w1ts.val = 1 << gpio_num;
         } else {
-            hw->out1_w1ts.out1_w1ts = (1 << (gpio_num - 32));
+            hw->out1_w1ts.val = 1 << (gpio_num - 32);
         }
     } else {
         if (gpio_num < 32) {
-            hw->out_w1tc.out_w1tc = (1 << gpio_num);
+            hw->out_w1tc.val = 1 << gpio_num;
         } else {
-            hw->out1_w1tc.out1_w1tc = (1 << (gpio_num - 32));
+            hw->out1_w1tc.val = 1 << (gpio_num - 32);
         }
     }
 }
diff --git a/components/hal/esp32p4/include/hal/i2c_ll.h b/components/hal/esp32p4/include/hal/i2c_ll.h
index 7471583274a..1de981b3478 100644
--- a/components/hal/esp32p4/include/hal/i2c_ll.h
+++ b/components/hal/esp32p4/include/hal/i2c_ll.h
@@ -82,6 +82,8 @@ typedef enum {
 #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT   (9)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2000)  // Approximate value for SCL timeout regs (in us).
 
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff)
+
 /**
  * @brief  Calculate I2C bus frequency
  *         Note that the clock accuracy is affected by the external pull-up resistor,
@@ -353,6 +355,36 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e
     hw->ctr.addr_broadcasting_en = broadcast_en;
 }
 
+/**
+ * @brief Get the cause of SCL clock stretching in slave mode
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @param stretch_cause Pointer to stretch cause in the slave mode.
+ *
+ * @return None
+ */
+__attribute__((always_inline))
+static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
+{
+    switch (hw->sr.stretch_cause) {
+    case 0:
+        *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
+        break;
+    case 1:
+        *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_TX_EMPTY;
+        break;
+    case 2:
+        *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_RX_FULL;
+        break;
+    case 3:
+        *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_SENDING_ACK;
+        break;
+    default:
+        HAL_ASSERT(false);
+        break;
+    }
+}
+
 /**
  * @brief  Configure I2C slave address
  *
@@ -963,6 +995,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    dev->scl_stretch_conf.stretch_protect_num = protect_num;
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -991,6 +1033,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->sr.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32p4/include/hal/i2s_ll.h b/components/hal/esp32p4/include/hal/i2s_ll.h
index 817491f126f..6cee5068a3b 100644
--- a/components/hal/esp32p4/include/hal/i2s_ll.h
+++ b/components/hal/esp32p4/include/hal/i2s_ll.h
@@ -652,7 +652,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 
 /**
  * @brief Configure I2S RX module clock divider
- * @note mclk on ESP32 is shared by both TX and RX channel
+ * @note mclk on ESP32P4 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
  * @param mclk_div The mclk division coefficients
diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h
index 9deb1b87811..00712b12564 100644
--- a/components/hal/esp32p4/include/hal/isp_ll.h
+++ b/components/hal/esp32p4/include/hal/isp_ll.h
@@ -22,7 +22,10 @@ extern "C" {
 #endif
 
 
-#define ISP_LL_GET_HW(num)            (((num) == 0) ? (&ISP) : NULL)
+#define ISP_LL_GET_HW(num)                    (((num) == 0) ? (&ISP) : NULL)
+
+#define ISP_LL_HSIZE_MAX                      1920
+#define ISP_LL_VSIZE_MAX                      1080
 
 /*---------------------------------------------------------------
                       Clock
@@ -81,6 +84,14 @@ extern "C" {
 ---------------------------------------------------------------*/
 #define ISP_LL_AE_WINDOW_MAX_RANGE            ((1<<12) - 1)
 
+/*---------------------------------------------------------------
+                      AWB
+---------------------------------------------------------------*/
+#define ISP_LL_AWB_WINDOW_MAX_RANGE    ((1<<12) - 1)
+#define ISP_LL_AWB_LUM_MAX_RANGE       ((1<<10) - 1)
+#define ISP_LL_AWB_RGB_RATIO_INT_BITS  (2)
+#define ISP_LL_AWB_RGB_RATIO_FRAC_BITS (8)
+
 /*---------------------------------------------------------------
                       BF
 ---------------------------------------------------------------*/
@@ -103,20 +114,10 @@ extern "C" {
 #define ISP_LL_COLOR_BRIGNTNESS_MAX     127
 
 /*---------------------------------------------------------------
-                      AWB
+                      LSC
 ---------------------------------------------------------------*/
-#define ISP_LL_AWB_WINDOW_MAX_RANGE    ((1<<12) - 1)
-#define ISP_LL_AWB_LUM_MAX_RANGE       ((1<<10) - 1)
-#define ISP_LL_AWB_RGB_RATIO_INT_BITS  (2)
-#define ISP_LL_AWB_RGB_RATIO_FRAC_BITS (8)
-
-typedef union {
-    struct {
-        uint32_t fraction: ISP_LL_AWB_RGB_RATIO_FRAC_BITS;
-        uint32_t integer: ISP_LL_AWB_RGB_RATIO_INT_BITS;
-    };
-    uint32_t val;
-} isp_ll_awb_rgb_ratio_t;
+#define ISP_LL_LSC_GRID_HEIGHT        32
+#define ISP_LL_LSC_GRID_WIDTH         32
 
 /*---------------------------------------------------------------
                       CCM
@@ -150,6 +151,22 @@ typedef enum {
     ISP_LL_AF_EDGE_DETECTOR_MODE_MANUAL,    ///< Manual set threshold
 } isp_ll_af_edge_detector_mode_t;
 
+typedef union {
+    struct {
+        uint32_t fraction: ISP_LL_AWB_RGB_RATIO_FRAC_BITS;
+        uint32_t integer: ISP_LL_AWB_RGB_RATIO_INT_BITS;
+    };
+    uint32_t val;
+} isp_ll_awb_rgb_ratio_t;
+
+/**
+ * @brief ISP LUT
+ */
+typedef enum {
+    ISP_LL_LUT_LSC,    ///< LUT for LSC
+    ISP_LL_LUT_DPC,    ///< LUT for DPC
+} isp_ll_lut_t;
+
 
 /*---------------------------------------------------------------
                       Clock
@@ -463,6 +480,17 @@ static inline bool isp_ll_is_rgb2yuv_enabled(isp_dev_t *hw)
     return hw->cntl.rgb2yuv_en;
 }
 
+/**
+ * @brief Set bayer mode
+ *
+ * @param[in] hw           Hardware instance address
+ * @param[in] bayer_order  Bayer order
+ */
+static inline void isp_ll_set_bayer_mode(isp_dev_t *hw, color_raw_element_order_t bayer_order)
+{
+    hw->frame_cfg.bayer_mode = bayer_order;
+}
+
 /*---------------------------------------------------------------
                       AF
 ---------------------------------------------------------------*/
@@ -1153,6 +1181,88 @@ static inline void isp_ll_ae_env_detector_set_period(isp_dev_t *hw, uint32_t per
     hw->ae_monitor.ae_monitor_period = period;
 }
 
+/*---------------------------------------------------------------
+                      LSC
+---------------------------------------------------------------*/
+/**
+ * @brief Enable / Disable LSC clock
+ *
+ * @param[in] hw      Hardware instance address
+ * @param[in] enable  Enable / Disable
+ */
+static inline void isp_ll_lsc_clk_enable(isp_dev_t *hw, bool enable)
+{
+    hw->clk_en.clk_lsc_force_on = enable;
+}
+
+/**
+ * @brief Enable / Disable Color
+ *
+ * @param[in] hw      Hardware instance address
+ * @param[in] enable  Enable / Disable
+ */
+static inline void isp_ll_lsc_enable(isp_dev_t *hw, bool enable)
+{
+    hw->cntl.lsc_en = enable;
+}
+
+/**
+ * @brief Set xtable size
+ *
+ * @param[in] hw          Hardware instance address
+ * @param[in] xtablesize  xtablesize
+ */
+static inline void isp_ll_lsc_set_xtablesize(isp_dev_t *hw, uint8_t xtablesize)
+{
+    hw->lsc_tablesize.lsc_xtablesize = xtablesize;
+}
+
+/*---------------------------------------------------------------
+                      LUT
+---------------------------------------------------------------*/
+/**
+ * @brief Select ISP LUT
+ *
+ * @param[in] hw        Hardware instance address
+ * @param[in] is_write  Is write or not
+ * @param[in] is_gb_b   Is gb_b or not
+ * @param[in] addr      LUT addr
+ * @param[in] lut       ISP LUT
+ */
+static inline void isp_ll_lut_set_cmd(isp_dev_t *hw, bool is_write, bool is_gb_b, uint32_t addr, isp_ll_lut_t lut)
+{
+    uint32_t val = 0;
+    val |= is_write ? (1 << 16) : 0;
+    val |= is_gb_b ? 0 : (1 << 10);
+    val |= addr & ((1 << 10) - 1);
+    val |= lut << 12;
+    hw->lut_cmd.val = val;
+}
+
+/**
+ * @brief Set lut gb and b gain
+ *
+ * @param[in] hw        Hardware instance address
+ * @param[in] gb_gain   gb gain
+ * @param[in] b_gain    b gain
+ */
+static inline void isp_ll_lut_set_wdata_gb_b(isp_dev_t *hw, isp_lsc_gain_t gb_gain, isp_lsc_gain_t b_gain)
+{
+    hw->lut_wdata.lut_wdata = (gb_gain.val & 0x3ff) << 10 | (b_gain.val & 0x3ff);
+}
+
+/**
+ * @brief Set lut r and gr gain
+ *
+ * @param[in] hw        Hardware instance address
+ * @param[in] r_gain   r gain
+ * @param[in] gr_gain    gr gain
+ */
+static inline void isp_ll_lut_set_wdata_r_gr(isp_dev_t *hw, isp_lsc_gain_t r_gain, isp_lsc_gain_t gr_gain)
+{
+    hw->lut_wdata.lut_wdata = (r_gain.val & 0x3ff) << 10 | (gr_gain.val & 0x3ff);
+}
+
 /*---------------------------------------------------------------
                       INTR
 ---------------------------------------------------------------*/
diff --git a/components/hal/esp32p4/include/hal/key_mgr_ll.h b/components/hal/esp32p4/include/hal/key_mgr_ll.h
index 15923a67ffa..3aa13bc3631 100644
--- a/components/hal/esp32p4/include/hal/key_mgr_ll.h
+++ b/components/hal/esp32p4/include/hal/key_mgr_ll.h
@@ -54,19 +54,35 @@ static inline void _key_mgr_ll_enable_peripheral_clock(bool enable)
 #define key_mgr_ll_enable_peripheral_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_enable_peripheral_clock(__VA_ARGS__)
 
 /**
- * @brief Reset the Key Manager peripheral */
-static inline void key_mgr_ll_reset_register(void)
+ * @brief Read state of Key Manager
+ *
+ * @return esp_key_mgr_state_t
+ */
+static inline esp_key_mgr_state_t key_mgr_ll_get_state(void)
+{
+    return (esp_key_mgr_state_t) REG_GET_FIELD(KEYMNG_STATE_REG, KEYMNG_STATE);
+}
+
+/**
+ * @brief Reset the Key Manager peripheral
+ * Note: Please use key_mgr_ll_reset_register which requires the critical section
+ *       and do not use _key_mgr_ll_reset_register
+ */
+static inline void _key_mgr_ll_reset_register(void)
 {
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_km = 1;
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_km = 0;
 
     // Clear reset on parent crypto, otherwise Key Manager is held in reset
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_crypto = 0;
+
+    while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
+    };
 }
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
-#define key_mgr_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; key_mgr_ll_reset_register(__VA_ARGS__)
+#define key_mgr_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_reset_register(__VA_ARGS__)
 
 /* @brief Start the key manager at IDLE state */
 static inline void key_mgr_ll_start(void)
@@ -323,16 +339,6 @@ static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(void)
     return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_XTS_AES_KEY_LEN);
 }
 
-/**
- * @brief Read state of Key Manager
- *
- * @return esp_key_mgr_state_t
- */
-static inline esp_key_mgr_state_t key_mgr_ll_get_state(void)
-{
-    return (esp_key_mgr_state_t) REG_GET_FIELD(KEYMNG_STATE_REG, KEYMNG_STATE);
-}
-
 /**
  * @brief Read the Key Manager date information
  */
diff --git a/components/hal/esp32p4/include/hal/ldo_ll.h b/components/hal/esp32p4/include/hal/ldo_ll.h
index 6e707890adb..abfd44e0126 100644
--- a/components/hal/esp32p4/include/hal/ldo_ll.h
+++ b/components/hal/esp32p4/include/hal/ldo_ll.h
@@ -8,34 +8,29 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "soc/chip_revision.h"
 #include "esp_bit_defs.h"
 #include "hal/misc.h"
+#include "hal/efuse_hal.h"
+#include "hal/pmu_types.h"
 #include "soc/pmu_struct.h"
+#include "soc/efuse_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define LDO_LL_NUM_UNITS            4    // NUmber of LDO units
-#define LDO_LL_ADJUSTABLE_CHAN_MASK 0x0F // all the 4 channels can be adjustable
+#define LDO_LL_NUM_UNITS            4    // Number of LDO units
+#define LDO_LL_ADJUSTABLE_CHAN_MASK 0x0F // all the 4 channels are adjustable by setting "mul" and "dref" registers
 
 #define LDO_LL_MAX_VOLTAGE_MV 3300
 #define LDO_LL_MIN_VOLTAGE_MV 500
 
 /**
- * LDO LL macros, these macros are in the unit of mV
+ * @brief In the analog design, the LDO output "channel" is index from 1, i.e., VO1, VO2, VO3, VO4.
+ *        But in software, we mapped them to "LDO unit", which is index from 0, i.e., 0, 1, 2, 3.
  */
-#define LDO_LL_EXT_LDO_DREF_VOL_H_BASE 1000
-#define LDO_LL_EXT_LDO_DREF_VOL_H_STEP 100
-#define LDO_LL_EXT_LDO_DREF_VOL_L_BASE 500
-#define LDO_LL_EXT_LDO_DREF_VOL_L_STEP 50
-#define LDO_LL_EXT_LDO_MUL_VOL_BASE    1000
-#define LDO_LL_EXT_LDO_MUL_VOL_STEP    250
-
-/**
- * LDO ID to real unit ID
- */
-#define LDO_ID2UNIT(ldo_id)    ((ldo_id) - 1)
+#define LDO_ID2UNIT(ldo_id)  ((ldo_id) - 1)
 
 /**
  * @brief LDO unit owner
@@ -48,6 +43,7 @@ typedef enum {
 /**
  * @brief Check if a LDO channel is valid
  *
+ * @param ldo_chan LDO channel ID, note, this is indexed from 1
  * @return True for valid, false for invalid
  */
 __attribute__((always_inline))
@@ -70,26 +66,76 @@ static inline bool ldo_ll_is_valid_ldo_channel(int ldo_chan)
 __attribute__((always_inline))
 static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint8_t *dref, uint8_t *mul)
 {
-    // TODO [IDF-10754]: also take the calibration parameters into account
-    if (voltage_mv <= 500) {
-        *dref = 0;
-        *mul = 0;
-    } else if (voltage_mv <= 900) {
-        *mul = 0;
-        *dref = (voltage_mv - LDO_LL_EXT_LDO_DREF_VOL_L_BASE) / LDO_LL_EXT_LDO_DREF_VOL_L_STEP;
-    } else if (voltage_mv <= 1600) {
-        *mul = 1;
-        *dref = 6 + (voltage_mv - LDO_LL_EXT_LDO_DREF_VOL_H_BASE) / LDO_LL_EXT_LDO_DREF_VOL_H_STEP;
-    } else if (voltage_mv <= 2000) {
-        *mul = 4;
-        *dref = (voltage_mv / 2 - LDO_LL_EXT_LDO_DREF_VOL_L_BASE) / LDO_LL_EXT_LDO_DREF_VOL_L_STEP;
-    } else if (voltage_mv <= 3200) {
-        *mul = 4;
-        *dref = 9 + (voltage_mv / 2 - LDO_LL_EXT_LDO_DREF_VOL_H_BASE) / LDO_LL_EXT_LDO_DREF_VOL_H_STEP;
-    } else {
-        *mul = 7;
-        *dref = 15;
+    uint8_t efuse_k = 0;
+    uint8_t efuse_vos = 0;
+    uint8_t efuse_c = 0;
+    // to avoid using FPU, enlarge the constants by 1000 as fixed point
+    int K_1000 = 1000;
+    int Vos_1000 = 0;
+    int C_1000 = 1000;
+
+    if (efuse_hal_blk_version() >= 1) {
+        // load the calibration values from the eFuse
+        if (ldo_unit == 2) {
+            efuse_k = EFUSE.rd_mac_sys_3.ldo_vo3_k;
+            efuse_vos = EFUSE.rd_mac_sys_3.ldo_vo3_vos;
+            efuse_c = EFUSE.rd_mac_sys_3.ldo_vo3_c;
+        }
+        if (ldo_unit == 3) {
+            efuse_k = (EFUSE.rd_mac_sys_4.ldo_vo4_k_1 << 6) + EFUSE.rd_mac_sys_3.ldo_vo4_k;
+            efuse_vos = EFUSE.rd_mac_sys_4.ldo_vo4_vos;
+            efuse_c = EFUSE.rd_mac_sys_4.ldo_vo4_c;
+        }
+        // convert the eFuse calibration values to fixed point, note these values are signed
+        if (efuse_k) {
+            K_1000 = efuse_k & 0x80 ? -1 * (efuse_k & 0x7F) + 975 : efuse_k + 975;
+        }
+        if (efuse_vos) {
+            Vos_1000 = efuse_vos & 0x20 ? -1 * (efuse_vos & 0x1F) - 3 : efuse_vos - 3;
+        }
+        if (efuse_c) {
+            C_1000 = efuse_c & 0x20 ? -1 * (efuse_c & 0x1F) + 990 : efuse_c + 990;
+        }
+    }
+
+    // iterate all the possible dref and mul values to find the best match
+    int min_voltage_diff = 400000000;
+    uint8_t matched_dref = 0;
+    uint8_t matched_mul = 0;
+    for (uint8_t dref_val = 0; dref_val < 16; dref_val++) {
+        int vref_20 = (dref_val < 9) ? (10 + dref_val) : (20 + (dref_val - 9) * 2);
+        for (uint8_t mul_val = 0; mul_val < 8; mul_val++) {
+            int vout_80000000 = (vref_20 * K_1000 + 20 * Vos_1000) * (4000 + mul_val * C_1000);
+            int diff = voltage_mv * 80000 - vout_80000000;
+            if (diff < 0) {
+                diff = -diff;
+            }
+            if (diff < min_voltage_diff) {
+                min_voltage_diff = diff;
+                matched_dref = dref_val;
+                matched_mul = mul_val;
+            }
+        }
+    }
+
+    if (efuse_hal_blk_version() >= 1) {
+        // For unit0 and unit1, the mul and dref value are calibrated and saved in the efuse, load them when available
+        if (ldo_unit == 0 && voltage_mv == 1800) {
+            if (EFUSE.rd_mac_sys_2.ldo_vo1_dref && EFUSE.rd_mac_sys_3.ldo_vo1_mul) {
+                matched_mul = EFUSE.rd_mac_sys_3.ldo_vo1_mul;
+                matched_dref = EFUSE.rd_mac_sys_2.ldo_vo1_dref;
+            }
+        }
+        if (ldo_unit == 1 && voltage_mv == 1900) {
+            if (EFUSE.rd_mac_sys_2.ldo_vo2_dref && EFUSE.rd_mac_sys_3.ldo_vo2_mul) {
+                matched_mul = EFUSE.rd_mac_sys_3.ldo_vo2_mul;
+                matched_dref = EFUSE.rd_mac_sys_2.ldo_vo2_dref;
+            }
+        }
     }
+
+    *dref = matched_dref;
+    *mul = matched_mul;
 }
 
 /**
@@ -110,47 +156,56 @@ static inline void ldo_ll_set_owner(int ldo_unit, ldo_ll_unit_owner_t owner)
      *  - 1: tieh_sel, i.e. by software
      */
     PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.force_tieh_sel = owner;
+    /**
+     * tieh_sel:
+     *  - 0: tieh;
+     *  - 1: sdmmc0_tieh;
+     *  - 2: 3.3V;
+     *  - 3: sdmmc1_tieh;
+     */
+    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.tieh_sel = 0;
 }
 
 /**
- * @brief Enable a LDO unit
+ * @brief Adjust voltage of a LDO unit
+ *
+ * @note When bypass is enabled, the input voltage is sourced directly to the output.
+ *       The dref and mul values will be ignored.
  *
  * @param ldo_unit LDO unit
- * @param enable  True: enable; False: disable
+ * @param dref A parameter which controls the internal reference voltage
+ * @param mul Multiply factor
+ * @param bypass True: bypass; False: not bypass.
  */
 __attribute__((always_inline))
-static inline void ldo_ll_enable(int ldo_unit, bool enable)
+static inline void ldo_ll_adjust_voltage(int ldo_unit, uint8_t dref, uint8_t mul, bool bypass)
 {
     uint8_t index_array[LDO_LL_NUM_UNITS] = {0, 3, 1, 4};
-    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.xpd = enable;
+    /**
+     * tieh:
+     *  - 0: Vref * Mul
+     *  - 1: 3.3V
+     */
+    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.tieh = bypass;
+    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo_ana.dref = dref;
+    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo_ana.mul = mul;
 }
 
 /**
- * @brief Adjust voltage of a LDO unit
+ * @brief Enable a LDO unit
  *
  * @param ldo_unit LDO unit
- * @param dref A parameter which controls the internal reference voltage
- * @param mul Multiply factor
+ * @param enable  True: enable; False: disable
  */
 __attribute__((always_inline))
-static inline void ldo_ll_adjust_voltage(int ldo_unit, uint8_t dref, uint8_t mul)
+static inline void ldo_ll_enable(int ldo_unit, bool enable)
 {
     uint8_t index_array[LDO_LL_NUM_UNITS] = {0, 3, 1, 4};
-    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo_ana.dref = dref;
-    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo_ana.mul = mul;
-    /**
-     * tieh:
-     *  - 0: Vref * Mul
-     *  - 1: 3.3V
-     *
-     * tieh_sel:
-     *  - 0: tieh;
-     *  - 1: sdmmc0_tieh;
-     *  - 2: 3.3V;
-     *  - 3: sdmmc1_tieh;
-     */
-    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.tieh_sel = 0;
-    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.tieh = 0;
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100) && (ldo_unit == 0)) {
+        // If chip_rev >= v1.0, slp_mem_dbias[3] is used to control the volt output of VO1.
+        PMU.hp_sys[PMU_MODE_HP_ACTIVE].regulator0.xpd_0p1a = (enable ? 8 : 0);
+    }
+    PMU.ext_ldo[index_array[ldo_unit]].pmu_ext_ldo.xpd = enable;
 }
 
 /**
diff --git a/components/hal/esp32p4/include/hal/lp_core_ll.h b/components/hal/esp32p4/include/hal/lp_core_ll.h
index 27a9a0997fa..eb2c57be317 100644
--- a/components/hal/esp32p4/include/hal/lp_core_ll.h
+++ b/components/hal/esp32p4/include/hal/lp_core_ll.h
@@ -28,7 +28,7 @@ extern "C" {
 #define LP_CORE_LL_WAKEUP_SOURCE_LP_BOD     BIT(14)
 #define LP_CORE_LL_WAKEUP_SOURCE_ETM        BIT(17)
 #define LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER_1 BIT(18)
-#define LP_CORE_LL_WAKEUP_SOURCE_LP_I2S     BIT(19)
+#define LP_CORE_LL_WAKEUP_SOURCE_LP_VAD     BIT(19)
 #define LP_CORE_LL_WAKEUP_SOURCE_HP_CPU     BIT(22)
 
 /* Use lp timer 1 as the normal wakeup timer, timer 0 is used by deep sleep */
diff --git a/components/hal/esp32p4/include/hal/lp_i2s_ll.h b/components/hal/esp32p4/include/hal/lp_i2s_ll.h
index c9f0d5611bd..23e81cd2a5f 100644
--- a/components/hal/esp32p4/include/hal/lp_i2s_ll.h
+++ b/components/hal/esp32p4/include/hal/lp_i2s_ll.h
@@ -32,6 +32,8 @@ extern "C" {
 #define LP_I2S_LL_EVENT_RX_DONE_INT             (1<<0)
 #define LP_I2S_LL_EVENT_RX_HUNG_INT_INT         (1<<1)
 #define LP_I2S_LL_EVENT_RX_FIFOMEM_UDF_INT      (1<<2)
+#define LP_I2S_LL_EVENT_VAD_DONE_INT            (1<<3)
+#define LP_I2S_LL_EVENT_VAD_RESET_DONE_INT      (1<<4)
 #define LP_I2S_LL_EVENT_RX_MEM_THRESHOLD_INT    (1<<5)
 #define LP_I2S_LL_TDM_CH_MASK                   (0x03UL)
 
@@ -709,9 +711,9 @@ static inline uint32_t lp_i2s_ll_get_intr_status_reg_addr(lp_i2s_dev_t *hw)
 /**
  * @brief Enable LP I2S RX channel interrupt
  *
- * @param hw         LP I2S hardware instance
- * @param mask       mask
- * @param enable     enable or disable
+ * @param[in] hw         LP I2S hardware instance
+ * @param[in] mask       mask
+ * @param[in] enable     enable or disable
  */
 static inline void lp_i2s_ll_rx_enable_interrupt(lp_i2s_dev_t *hw, uint32_t mask, bool enable)
 {
@@ -727,8 +729,8 @@ static inline void lp_i2s_ll_rx_enable_interrupt(lp_i2s_dev_t *hw, uint32_t mask
 /**
  * @brief Clear LP I2S RX channel interrupt
  *
- * @param hw         LP I2S hardware instance
- * @param mask       mask
+ * @param[in] hw         LP I2S hardware instance
+ * @param[in] mask       mask
  */
 __attribute__((always_inline))
 static inline void lp_i2s_ll_rx_clear_interrupt_status(lp_i2s_dev_t *hw, uint32_t mask)
@@ -736,6 +738,100 @@ static inline void lp_i2s_ll_rx_clear_interrupt_status(lp_i2s_dev_t *hw, uint32_
     hw->int_clr.val = mask;
 }
 
+/*---------------------------------------------------------------
+                      VAD
+---------------------------------------------------------------*/
+#define LP_VAD_LL_INIT_FRAME_MIN    100
+#define LP_VAD_LL_INIT_FRAME_MAX    200
+
+/**
+ * @brief Set VAD init frame number
+ *
+ * @param[in] hw         LP I2S hardware instance
+ * @param[in] frame_num  Frame number
+ */
+static inline void lp_vad_ll_set_init_frame_num(lp_i2s_dev_t *hw, int frame_num)
+{
+    hw->vad_param0.param_init_frame_num = frame_num;
+}
+
+/**
+ * @brief Set VAD min energy
+ *
+ * @param[in] hw          LP I2S hardware instance
+ * @param[in] min_energy  Min energy
+ */
+static inline void lp_vad_ll_set_init_min_energy(lp_i2s_dev_t *hw, int min_energy)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->vad_param0, param_min_energy, min_energy);
+}
+
+/**
+ * @brief Set VAD speak activity thresh
+ *
+ * @param[in] hw          LP I2S hardware instance
+ * @param[in] thresh      Threshold
+ */
+static inline void lp_vad_ll_set_speak_activity_thresh(lp_i2s_dev_t *hw, int thresh)
+{
+    hw->vad_param1.param_hangover_speech = thresh;
+}
+
+/**
+ * @brief Set VAD non speak activity thresh
+ *
+ * @param[in] hw          LP I2S hardware instance
+ * @param[in] thresh      Threshold
+ */
+static inline void lp_vad_ll_set_non_speak_activity_thresh(lp_i2s_dev_t *hw, int thresh)
+{
+    hw->vad_param1.param_hangover_silent = thresh;
+}
+
+/**
+ * @brief Set VAD min speak activity thresh
+ *
+ * @param[in] hw          LP I2S hardware instance
+ * @param[in] thresh      Threshold
+ */
+static inline void lp_vad_ll_set_min_speak_activity_thresh(lp_i2s_dev_t *hw, int thresh)
+{
+    hw->vad_param1.param_min_speech_count = thresh;
+}
+
+/**
+ * @brief Set VAD max speak activity thresh
+ *
+ * @param[in] hw          LP I2S hardware instance
+ * @param[in] thresh      Threshold
+ */
+static inline void lp_vad_ll_set_max_speak_activity_thresh(lp_i2s_dev_t *hw, int thresh)
+{
+    hw->vad_param1.param_max_speech_count = thresh;
+}
+
+/**
+ * @brief Skip band energy check
+ *
+ * @param[in] hw          LP I2S hardware instance
+ * @param[in] skip        1: skip; 0: not skip
+ */
+static inline void lp_vad_ll_skip_band_energy(lp_i2s_dev_t *hw, bool skip)
+{
+    hw->vad_param1.param_skip_band_energy = skip;
+}
+
+/**
+ * @brief Enable LP I2S 24 fill
+ *
+ * @param[in] hw         LP I2S hardware instance
+ * @param[in] en         enable or disable
+ */
+static inline void lp_vad_ll_enable(lp_i2s_dev_t *hw, bool en)
+{
+    hw->vad_conf.vad_en = en;
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h
index f9cfe4e6855..78979e8453a 100644
--- a/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h
+++ b/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h
@@ -170,23 +170,25 @@ static inline void mipi_dsi_brg_ll_credit_reset(dsi_brg_dev_t *dev)
  * @brief Set the color coding for the bridge controller
  *
  * @param dev Pointer to the DSI bridge controller register base address
- * @param pixel_format Color coding
+ * @param color_coding Color coding value
  * @param sub_config Sub configuration
  */
-static inline void mipi_dsi_brg_ll_set_pixel_format(dsi_brg_dev_t *dev, lcd_color_rgb_pixel_format_t pixel_format, uint32_t sub_config)
+static inline void mipi_dsi_brg_ll_set_pixel_format(dsi_brg_dev_t *dev, lcd_color_format_t color_coding, uint32_t sub_config)
 {
-    switch (pixel_format) {
-    case LCD_COLOR_PIXEL_FORMAT_RGB565:
+    switch (color_coding) {
+    case LCD_COLOR_FMT_RGB565:
         dev->pixel_type.raw_type = 2;
         break;
-    case LCD_COLOR_PIXEL_FORMAT_RGB666:
+    case LCD_COLOR_FMT_RGB666:
         dev->pixel_type.raw_type = 1;
         break;
-    case LCD_COLOR_PIXEL_FORMAT_RGB888:
+    case LCD_COLOR_FMT_RGB888:
         dev->pixel_type.raw_type = 0;
         break;
     default:
-        abort();
+        // MIPI DSI host can only accept RGB data, no YUV data
+        HAL_ASSERT(false);
+        break;
     }
     dev->pixel_type.dpi_config = sub_config;
 }
@@ -344,6 +346,36 @@ static inline void mipi_dsi_brg_ll_set_yuv_convert_std(dsi_brg_dev_t *dev, lcd_y
     }
 }
 
+/**
+ * @brief Set the YUV422 packing order
+ *
+ * @param dev Pointer to the DSI bridge controller register base address
+ * @param order YUV422 packing order
+ */
+static inline void mipi_dsi_brg_ll_set_yuv422_pack_order(dsi_brg_dev_t *dev, lcd_yuv422_pack_order_t order)
+{
+    switch (order) {
+    case LCD_YUV422_PACK_ORDER_UYVY:
+        dev->yuv_cfg.yuv422_format = 0;
+        dev->yuv_cfg.yuv_pix_endian = 1;
+        break;
+    case LCD_YUV422_PACK_ORDER_VYUY:
+        dev->yuv_cfg.yuv422_format = 1;
+        dev->yuv_cfg.yuv_pix_endian = 1;
+        break;
+    case LCD_YUV422_PACK_ORDER_YUYV:
+        dev->yuv_cfg.yuv422_format = 2;
+        dev->yuv_cfg.yuv_pix_endian = 1;
+        break;
+    case LCD_YUV422_PACK_ORDER_YVYU:
+        dev->yuv_cfg.yuv422_format = 3;
+        dev->yuv_cfg.yuv_pix_endian = 1;
+        break;
+    default:
+        abort();
+    }
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h
index e88ea9e7a51..c1a29595991 100644
--- a/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h
+++ b/components/hal/esp32p4/include/hal/mipi_dsi_host_ll.h
@@ -181,19 +181,20 @@ static inline void mipi_dsi_host_ll_dpi_set_vcid(dsi_host_dev_t *dev, uint32_t v
  * @param color_coding Color coding value
  * @param sub_config Sub configuration value
  */
-static inline void mipi_dsi_host_ll_dpi_set_color_coding(dsi_host_dev_t *dev, lcd_color_rgb_pixel_format_t color_coding, uint32_t sub_config)
+static inline void mipi_dsi_host_ll_dpi_set_color_coding(dsi_host_dev_t *dev, lcd_color_format_t color_coding, uint32_t sub_config)
 {
     switch (color_coding) {
-    case LCD_COLOR_PIXEL_FORMAT_RGB565:
+    case LCD_COLOR_FMT_RGB565:
         dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_16BIT_CONFIG1 + sub_config;
         break;
-    case LCD_COLOR_PIXEL_FORMAT_RGB666:
+    case LCD_COLOR_FMT_RGB666:
         dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_18BIT_CONFIG1 + sub_config;
         break;
-    case LCD_COLOR_PIXEL_FORMAT_RGB888:
+    case LCD_COLOR_FMT_RGB888:
         dev->dpi_color_coding.dpi_color_coding = MIPI_DSI_LL_COLOR_CODE_24BIT;
         break;
     default:
+        // MIPI DSI bridge can only write RGB data to the DSI host controller, no YUV data
         HAL_ASSERT(false);
         break;
     }
diff --git a/components/hal/esp32p4/include/hal/pmu_ll.h b/components/hal/esp32p4/include/hal/pmu_ll.h
index 0378fbaf421..f64b60cccda 100644
--- a/components/hal/esp32p4/include/hal/pmu_ll.h
+++ b/components/hal/esp32p4/include/hal/pmu_ll.h
@@ -216,9 +216,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw,
     hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
 }
 
-FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
+FORCE_INLINE_ATTR void pmu_ll_hp_enable_sleep_flash_ldo_channel(pmu_dev_t *hw, bool enable)
 {
-    hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
+    // slp_mem_dbias[3] is used to control the volt output of VO1 for chip_revision >= 100,
+    // and this field is not used for chip_revision < 100.
+    hw->hp_sys[PMU_MODE_HP_SLEEP].regulator0.xpd_0p1a = (enable ? 8 : 0);
 }
 
 FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
diff --git a/components/hal/esp32p4/include/hal/ppa_ll.h b/components/hal/esp32p4/include/hal/ppa_ll.h
index 60facd94fec..1d82fdce92a 100644
--- a/components/hal/esp32p4/include/hal/ppa_ll.h
+++ b/components/hal/esp32p4/include/hal/ppa_ll.h
@@ -24,8 +24,8 @@ extern "C" {
 #define PPA_LL_BLEND0_CLUT_MEM_ADDR_OFFSET  0x400
 #define PPA_LL_BLEND1_CLUT_MEM_ADDR_OFFSET  0x800
 
-#define PPA_LL_SRM_SCALING_INT_MAX   PPA_SR_SCAL_X_INT_V
-#define PPA_LL_SRM_SCALING_FRAG_MAX  PPA_SR_SCAL_X_FRAG_V
+#define PPA_LL_SRM_SCALING_INT_MAX   (PPA_SR_SCAL_X_INT_V + 1)
+#define PPA_LL_SRM_SCALING_FRAG_MAX  (PPA_SR_SCAL_X_FRAG_V + 1)
 
 // TODO: On P4 ECO2, SRM block size needs update
 #define PPA_LL_SRM_DEFAULT_BLOCK_SIZE   18 // 18 x 18 block size
diff --git a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h
index 75744b44d42..efb93b30570 100644
--- a/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h
+++ b/components/hal/esp32p4/include/hal/regi2c_ctrl_ll.h
@@ -21,25 +21,33 @@ extern "C" {
 /**
  * @brief Enable analog I2C master clock
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
 {
     LPPERI.clk_en.ck_en_lp_i2cmst = en;
 }
 
 // LPPERI.clk_en is a shared register, so this function must be used in an atomic way
-#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return LPPERI.clk_en.ck_en_lp_i2cmst;
+}
 
 /**
  * @brief Reset analog I2C master
  */
-static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
 {
     LPPERI.reset_en.rst_en_lp_i2cmst = 1;
     LPPERI.reset_en.rst_en_lp_i2cmst = 0;
 }
 
 // LPPERI.reset_en is a shared register, so this function must be used in an atomic way
-#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
 
 /**
  * @brief Configure analog I2C master clock
diff --git a/components/hal/esp32p4/include/hal/rmt_ll.h b/components/hal/esp32p4/include/hal/rmt_ll.h
index affcc3eeacd..105aa426925 100644
--- a/components/hal/esp32p4/include/hal/rmt_ll.h
+++ b/components/hal/esp32p4/include/hal/rmt_ll.h
@@ -33,8 +33,6 @@ extern "C" {
 #define RMT_LL_EVENT_TX_MASK(channel)     (RMT_LL_EVENT_TX_DONE(channel) | RMT_LL_EVENT_TX_THRES(channel) | RMT_LL_EVENT_TX_LOOP_END(channel))
 #define RMT_LL_EVENT_RX_MASK(channel)     (RMT_LL_EVENT_RX_DONE(channel) | RMT_LL_EVENT_RX_THRES(channel))
 
-#define RMT_LL_SLEEP_RETENTION_MODULE_ID(group_id) (SLEEP_RETENTION_MODULE_RMT0)
-
 #define RMT_LL_MAX_LOOP_COUNT_PER_BATCH   1023
 #define RMT_LL_MAX_FILTER_VALUE           255
 #define RMT_LL_MAX_IDLE_VALUE             32767
diff --git a/components/hal/esp32p4/include/hal/sdmmc_ll.h b/components/hal/esp32p4/include/hal/sdmmc_ll.h
index 1141854f5ca..9f168b2620a 100644
--- a/components/hal/esp32p4/include/hal/sdmmc_ll.h
+++ b/components/hal/esp32p4/include/hal/sdmmc_ll.h
@@ -24,6 +24,7 @@
 #include "soc/sdmmc_reg.h"
 #include "soc/hp_sys_clkrst_struct.h"
 #include "soc/lp_clkrst_struct.h"
+#include "soc/pmu_reg.h"
 
 
 #ifdef __cplusplus
@@ -124,6 +125,37 @@ static inline void sdmmc_ll_reset_register(sdmmc_dev_t *hw)
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
 #define sdmmc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_reset_register(__VA_ARGS__)
 
+/**
+ * @brief Enable the bus clock for SDIO PLL
+ *
+ * @param hw    hardware instance address
+ * @param en    enable / disable
+ */
+static inline void sdmmc_ll_enable_sdio_pll(sdmmc_dev_t *hw, bool en)
+{
+    if (en) {
+        REG_SET_BIT(PMU_RF_PWC_REG, PMU_SDIO_PLL_XPD);
+        REG_SET_BIT(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_SDIOPLL_I2C);
+        REG_SET_BIT(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_SDIOPLL);
+        REG_SET_BIT(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG);
+        LP_AON_CLKRST.hp_clk_ctrl.hp_sdio_pll0_clk_en = 1;
+        LP_AON_CLKRST.hp_clk_ctrl.hp_sdio_pll1_clk_en = 1;
+        LP_AON_CLKRST.hp_clk_ctrl.hp_sdio_pll2_clk_en = 1;
+    } else {
+        REG_CLR_BIT(PMU_RF_PWC_REG, PMU_SDIO_PLL_XPD);
+        REG_CLR_BIT(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_SDIOPLL_I2C);
+        REG_CLR_BIT(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_SDIOPLL);
+        REG_CLR_BIT(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_SDIOPLL_ICG);
+        LP_AON_CLKRST.hp_clk_ctrl.hp_sdio_pll0_clk_en = 0;
+        LP_AON_CLKRST.hp_clk_ctrl.hp_sdio_pll0_clk_en = 0;
+        LP_AON_CLKRST.hp_clk_ctrl.hp_sdio_pll2_clk_en = 0;
+    }
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define sdmmc_ll_enable_sdio_pll(...) (void)__DECLARE_RCC_ATOMIC_ENV; sdmmc_ll_enable_sdio_pll(__VA_ARGS__)
+
 /**
  * @brief Select SDMMC clock source
  *
@@ -137,9 +169,9 @@ static inline void sdmmc_ll_select_clk_source(sdmmc_dev_t *hw, soc_periph_sdmmc_
     case SDMMC_CLK_SRC_PLL160M:
         clk_val = 0;
         break;
-    // case SDMMC_CLK_SRC_PLL200M: // TODO: IDF-8886
-    //     clk_val = 1;
-    //     break;
+    case SDMMC_CLK_SRC_SDIO_200M:
+        clk_val = 1;
+        break;
     default:
         HAL_ASSERT(false);
         break;
@@ -161,12 +193,18 @@ static inline void sdmmc_ll_select_clk_source(sdmmc_dev_t *hw, soc_periph_sdmmc_
  */
 static inline void sdmmc_ll_set_clock_div(sdmmc_dev_t *hw, uint32_t div)
 {
-    HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_h = div / 2 - 1;
-    HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_n = div - 1;
-    HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_l = div - 1;
-
-    HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_cfg_update = 1;
-    HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_cfg_update = 0;
+    if (div > 1) {
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_h = div / 2 - 1;
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_n = div - 1;
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_l = div - 1;
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_cfg_update = 1;
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_cfg_update = 0;
+    } else {
+        HP_SYS_CLKRST.peri_clk_ctrl01.reg_sdio_hs_mode = 1;
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_h = 0;
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_n = 0;
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_l = 0;
+    }
 }
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
@@ -192,7 +230,16 @@ static inline void sdmmc_ll_deinit_clk(sdmmc_dev_t *hw)
  */
 static inline uint32_t sdmmc_ll_get_clock_div(sdmmc_dev_t *hw)
 {
-    return HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_l + 1;
+    uint32_t div = 0;
+    if (HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_h == 0 &&
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_n == 0 &&
+        HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_l == 0) {
+        div = 1;
+    } else {
+        div = HP_SYS_CLKRST.peri_clk_ctrl02.reg_sdio_ls_clk_edge_l + 1;
+    }
+
+    return div;
 }
 
 /**
@@ -451,6 +498,22 @@ static inline bool sdmmc_ll_is_card_write_protected(sdmmc_dev_t *hw, uint32_t sl
     return is_protected;
 }
 
+/**
+ * @brief Switch between 3.3V and 1.8V mode
+ *
+ * @param hw    hardware instance address
+ * @param slot  slot
+ * @param en    enable / disable 1.8V (3.3V on disable)
+ */
+static inline void sdmmc_ll_enable_1v8_mode(sdmmc_dev_t *hw, uint32_t slot, bool en)
+{
+    if (en) {
+        hw->uhs.volt |= BIT(slot);
+    } else {
+        hw->uhs.volt &= ~BIT(slot);
+    }
+}
+
 /**
  * @brief Enable DDR mode
  *
diff --git a/components/hal/esp32p4/include/hal/touch_sensor_hal.h b/components/hal/esp32p4/include/hal/touch_sensor_hal.h
deleted file mode 100644
index bc6d03f503b..00000000000
--- a/components/hal/esp32p4/include/hal/touch_sensor_hal.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*******************************************************************************
- * NOTICE
- * The hal is not public api, don't use in application code.
- * See readme.md in hal/include/hal/readme.md
- ******************************************************************************/
-
-// The HAL layer for touch sensor (ESP32-P4 specific part)
-
-#pragma once
-
-#include "hal/touch_sensor_ll.h"
-#include "hal/touch_sensor_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief Sample configurations of the touch sensor
- *
- */
-typedef struct {
-    uint32_t                        div_num;            /*!< The division from the source clock to the sampling frequency */
-    uint32_t                        charge_times;       /*!< The charge and discharge times of the sample configuration, the read data are positive correlation to the charge_times */
-    uint8_t                         rc_filter_res;      /*!< The resistance of the RC filter of the sample configuration, range [0, 3], while 0 = 0K, 1 = 1.5K, 2 = 3K, 3 = 4.5K */
-    uint8_t                         rc_filter_cap;      /*!< The capacitance of the RC filter of the sample configuration, range [0, 127], while 0 = 0pF, 1 = 20fF, ..., 127 = 2.54pF */
-    uint8_t                         low_drv;            /*!< Low speed touch driver, only effective when high speed driver is disabled */
-    uint8_t                         high_drv;           /*!< High speed touch driver */
-    uint8_t                         bias_volt;          /*!< The Internal LDO voltage, which decide the bias voltage of the sample wave, range [0,15] */
-    bool                            bypass_shield_output; /*!< Whether to bypass the shield output */
-} touch_hal_sample_config_t;
-
-/**
- * @brief Configurations of the touch sensor controller
- *
- */
-typedef struct {
-    uint32_t                        power_on_wait_ticks;    /*!< The waiting time between the channels power on and able to measure, to ensure the data stability */
-    uint32_t                        meas_interval_ticks;    /*!< Measurement interval of each channels */ // TODO: Test the supported range
-    uint32_t                        timeout_ticks;          /*!< The maximum time of measuring one channel, if the time exceeds this value, the timeout interrupt will be triggered.
-                                                             *   Set to '0' to ignore the measurement time limitation, otherwise please set a proper time considering the configurations
-                                                             *   of the sample configurations below.
-                                                             */
-    touch_out_mode_t                output_mode;            /*!< Touch channel counting mode of the binarized touch output */
-    uint32_t                        sample_cfg_num;         /*!< The sample configuration number that used for sampling */
-    touch_hal_sample_config_t       *sample_cfg;            /*!< The array of the sample configuration configurations, the length should be specified in `touch_hal_sample_config_t::sample_cfg_num` */
-} touch_hal_config_t;
-
-/**
- * @brief Configure the touch sensor hardware with the configuration
- *
- * @param[in]  cfg  Touch sensor hardware configuration
- */
-void touch_hal_config_controller(const touch_hal_config_t *cfg);
-
-/**
- * @brief Save the touch sensor hardware configuration
- * @note  The saved configurations will be applied before entering deep sleep
- *
- * @param[in]  deep_slp_chan    The touch sensor channel that can wake-up the chip from deep sleep
- * @param[in]  deep_slp_cfg     The hardware configuration that takes effect during the deep sleep
- */
-void touch_hal_save_sleep_config(int deep_slp_chan, const touch_hal_config_t *deep_slp_cfg);
-
-/**
- * @brief Prepare for the deep sleep
- * @note  Including apply the deep sleep configuration, clear interrupts, resetting benchmark
- */
-void touch_hal_prepare_deep_sleep(void);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/hal/esp32p4/include/hal/touch_sensor_ll.h b/components/hal/esp32p4/include/hal/touch_sensor_ll.h
index 37280c3b5d2..d2e99b03f16 100644
--- a/components/hal/esp32p4/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32p4/include/hal/touch_sensor_ll.h
@@ -24,7 +24,7 @@
 #include "soc/touch_struct.h"
 #include "soc/pmu_struct.h"
 #include "soc/soc_caps.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sens_types.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -173,17 +173,6 @@ static inline void touch_ll_enable_fsm_timer(bool enable)
     LP_ANA_PERI.touch_mux0.touch_start_force = !enable;
 }
 
-/**
- * Get touch sensor FSM mode.
- *        The measurement action can be triggered by the hardware timer, as well as by the software instruction.
- *
- * @param mode FSM mode.
- */
-static inline void touch_ll_get_fsm_mode(touch_fsm_mode_t *mode)
-{
-    *mode = (touch_fsm_mode_t)LP_ANA_PERI.touch_mux0.touch_fsm_en;
-}
-
 /**
  * Is touch sensor FSM using hardware timer to trigger scanning.
  *        The measurement action can be triggered by the hardware timer, as well as by the software instruction.
@@ -222,10 +211,9 @@ static inline void touch_ll_force_done_curr_measurement(void)
  * The measurement action can be triggered by the hardware timer, as well as by the software instruction.
  * @note
  *      The timer should be triggered
- * @param is_sleep   Whether in sleep state
  */
 __attribute__((always_inline))
-static inline void touch_ll_start_fsm_repeated_timer(bool is_sleep)
+static inline void touch_ll_start_fsm_repeated_timer(void)
 {
     /**
      * Touch timer trigger measurement and always wait measurement done.
@@ -238,10 +226,9 @@ static inline void touch_ll_start_fsm_repeated_timer(bool is_sleep)
 /**
  * Stop touch sensor FSM timer.
  *        The measurement action can be triggered by the hardware timer, as well as by the software instruction.
- * @param is_sleep   Whether in sleep state
  */
 __attribute__((always_inline))
-static inline void touch_ll_stop_fsm_repeated_timer(bool is_sleep)
+static inline void touch_ll_stop_fsm_repeated_timer(void)
 {
     PMU.touch_pwr_cntl.sleep_timer_en = 0;
     touch_ll_force_done_curr_measurement();
@@ -255,6 +242,7 @@ static inline void touch_ll_stop_fsm_repeated_timer(bool is_sleep)
  *      - true: enabled
  *      - true: disabled
  */
+__attribute__((always_inline))
 static inline bool touch_ll_is_fsm_repeated_timer_enabled(void)
 {
     return (bool)(PMU.touch_pwr_cntl.sleep_timer_en);
@@ -305,7 +293,7 @@ __attribute__((always_inline))
 static inline void touch_ll_enable_scan_mask(uint16_t chan_mask, bool enable)
 {
     // Channel shift workaround: the lowest bit takes no effect
-    uint16_t mask = (chan_mask << 1) & TOUCH_PAD_BIT_MASK_ALL;
+    uint16_t mask = (chan_mask << 1) & TOUCH_LL_FULL_CHANNEL_MASK;
     uint16_t prev_mask = LP_ANA_PERI.touch_scan_ctrl1.touch_scan_pad_map;
     if (enable) {
         LP_ANA_PERI.touch_scan_ctrl1.touch_scan_pad_map = prev_mask | mask;
@@ -326,10 +314,10 @@ static inline void touch_ll_enable_scan_mask(uint16_t chan_mask, bool enable)
  * @return
  *      - ESP_OK on success
  */
-static inline void touch_ll_set_channel_mask(uint16_t enable_mask)
+static inline void touch_ll_enable_channel_mask(uint16_t enable_mask)
 {
     // Channel shift workaround: the lowest bit takes no effect
-    uint16_t mask = (enable_mask << 1) & TOUCH_PAD_BIT_MASK_ALL;
+    uint16_t mask = (enable_mask << 1) & TOUCH_LL_FULL_CHANNEL_MASK;
     LP_ANA_PERI.touch_scan_ctrl1.touch_scan_pad_map = mask;
     LP_ANA_PERI.touch_filter2.touch_outen = mask;
 }
@@ -479,7 +467,7 @@ static inline void touch_ll_set_clock_div(uint8_t sample_cfg_id, uint32_t div_nu
  *
  * @param type  Select idle channel connect to high resistance state or ground. (No effect)
  */
-static inline void touch_ll_set_idle_channel_connect(touch_pad_conn_type_t type)
+static inline void touch_ll_set_idle_channel_connect(touch_idle_conn_t type)
 {
     (void)type;
 }
@@ -502,7 +490,7 @@ static inline uint32_t touch_ll_get_current_meas_channel(void)
  *
  * @param int_mask interrupt mask
  */
-static inline void touch_ll_intr_enable(uint32_t int_mask)
+static inline void touch_ll_interrupt_enable(uint32_t int_mask)
 {
     uint32_t mask = LP_TOUCH.int_ena.val;
     mask |= (int_mask & TOUCH_LL_INTR_MASK_ALL);
@@ -514,7 +502,7 @@ static inline void touch_ll_intr_enable(uint32_t int_mask)
  *
  * @param int_mask interrupt mask
  */
-static inline void touch_ll_intr_disable(uint32_t int_mask)
+static inline void touch_ll_interrupt_disable(uint32_t int_mask)
 {
     uint32_t mask = LP_TOUCH.int_ena.val;
     mask &= ~(int_mask & TOUCH_LL_INTR_MASK_ALL);
@@ -527,7 +515,7 @@ static inline void touch_ll_intr_disable(uint32_t int_mask)
  * @param int_mask Pad mask to clear interrupts
  */
 __attribute__((always_inline))
-static inline void touch_ll_intr_clear(touch_pad_intr_mask_t int_mask)
+static inline void touch_ll_interrupt_clear(uint32_t int_mask)
 {
     LP_TOUCH.int_clr.val = int_mask;
 }
@@ -545,28 +533,23 @@ static inline uint32_t touch_ll_get_intr_status_mask(void)
 }
 
 /**
- * Enable the timeout check for all touch sensor channels measurements.
+ * Set the timeout to enable or disable the check for all touch sensor channels measurements.
  * When the touch reading of a touch channel exceeds the measurement threshold,
  * If enable: a timeout interrupt will be generated and it will go to the next channel measurement.
  * If disable: the FSM is always on the channel, until the measurement of this channel is over.
  *
  * @param timeout_cycles The maximum time cycles of the measurement on one channel.
+ *                       Set to 0 to disable the timeout.
+ *                       Set to non-zero to enable the timeout and set the timeout cycles.
  */
-static inline void touch_ll_timeout_enable(uint32_t timeout_cycles)
-{
-    LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_num = timeout_cycles;
-    LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_en = 1;
-}
-
-/**
- * Disable the timeout check for all touch sensor channels measurements.
- * When the touch reading of a touch channel exceeds the measurement threshold,
- * If enable: a timeout interrupt will be generated and it will go to the next channel measurement.
- * If disable: the FSM is always on the channel, until the measurement of this channel is over.
- */
-static inline void touch_ll_timeout_disable(void)
+static inline void touch_ll_set_timeout(uint32_t timeout_cycles)
 {
-    LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_en = 0;
+    if (timeout_cycles) {
+        LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_num = timeout_cycles;
+        LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_en = 1;
+    } else {
+        LP_ANA_PERI.touch_scan_ctrl2.touch_timeout_en = 0;
+    }
 }
 
 /**
@@ -665,9 +648,9 @@ static inline void touch_ll_reset_chan_benchmark(uint32_t chan_mask)
  * Set filter mode. The input of the filter is the raw value of touch reading,
  * and the output of the filter is involved in the judgment of the touch state.
  *
- * @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
+ * @param mode Filter mode type. Refer to ``touch_benchmark_filter_mode_t``.
  */
-static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
+static inline void touch_ll_filter_set_filter_mode(touch_benchmark_filter_mode_t mode)
 {
     LP_ANA_PERI.touch_filter1.touch_filter_mode = mode;
 }
@@ -676,9 +659,9 @@ static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
  * Set filter mode. The input to the filter is raw data and the output is the smooth data.
  * The smooth data is used to determine the touch status.
  *
- * @param mode Filter mode type. Refer to ``touch_smooth_mode_t``.
+ * @param mode Filter mode type. Refer to ``touch_smooth_filter_mode_t``.
  */
-static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
+static inline void touch_ll_filter_set_smooth_mode(touch_smooth_filter_mode_t mode)
 {
     LP_ANA_PERI.touch_filter1.touch_smooth_lvl = mode;
 }
@@ -803,7 +786,7 @@ static inline void touch_ll_waterproof_set_shield_chan_mask(uint32_t mask)
  *
  * @param driver_level The driver level of the touch buff
  */
-static inline void touch_ll_waterproof_set_shield_driver(touch_pad_shield_driver_t driver_level)
+static inline void touch_ll_waterproof_set_shield_driver(touch_chan_shield_cap_t driver_level)
 {
     LP_ANA_PERI.touch_ana_para.touch_touch_buf_drv = driver_level;
 }
diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h
index 9b62cea267d..e50d181af69 100644
--- a/components/hal/esp32p4/include/hal/uart_ll.h
+++ b/components/hal/esp32p4/include/hal/uart_ll.h
@@ -45,13 +45,6 @@ extern "C" {
 #define UART_LL_FSM_IDLE                       (0x0)
 #define UART_LL_FSM_TX_WAIT_SEND               (0xf)
 
-// UART sleep retention module
-#define UART_LL_SLEEP_RETENTION_MODULE_ID(uart_num) ((uart_num == UART_NUM_0) ? SLEEP_RETENTION_MODULE_UART0 : \
-                                                     (uart_num == UART_NUM_1) ? SLEEP_RETENTION_MODULE_UART1 : \
-                                                     (uart_num == UART_NUM_2) ? SLEEP_RETENTION_MODULE_UART2 : \
-                                                     (uart_num == UART_NUM_3) ? SLEEP_RETENTION_MODULE_UART3 : \
-                                                     (uart_num == UART_NUM_4) ? SLEEP_RETENTION_MODULE_UART4 : -1)
-
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1 << 0),
@@ -716,7 +709,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
  */
 FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 {
-    return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
 }
 
 /**
@@ -729,7 +722,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
 FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
 {
     uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN;
-    uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    uint32_t txfifo_len = HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
     return (total_fifo_len - txfifo_len);
 }
 
@@ -805,7 +798,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_
  */
 FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
 {
-    hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw));
 }
 
 /**
@@ -819,7 +812,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full
  */
 FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
 {
-    hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw));
 }
 
 /**
@@ -883,7 +876,7 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
 {
     //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
     if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
-        hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs << UART_LL_REG_FIELD_BIT_SHIFT(hw));
         hw->hwfc_conf_sync.rx_flow_en = 1;
     } else {
         hw->hwfc_conf_sync.rx_flow_en = 0;
@@ -929,10 +922,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
     if (sw_flow_ctrl_en) {
         hw->swfc_conf0_sync.xonoff_del = 1;
         hw->swfc_conf0_sync.sw_flow_con_en = 1;
-        hw->swfc_conf1.xon_threshold = (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
-        hw->swfc_conf1.xoff_threshold = (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, (flow_ctrl->xon_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, (flow_ctrl->xoff_thrd) << UART_LL_REG_FIELD_BIT_SHIFT(hw));
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->swfc_conf0_sync.sw_flow_con_en = 0;
         hw->swfc_conf0_sync.xonoff_del = 0;
@@ -956,7 +949,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt_sync, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt_sync, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout_sync, rx_gap_tout, cmd_char->gap_tout);
@@ -1206,7 +1199,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_cmd_char);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, at_char_num);
 }
 
 /**
@@ -1243,7 +1236,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length
  */
 FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
 {
-    return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
+    return (((HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
 }
 
 /**
diff --git a/components/hal/esp32p4/include/hal/usb_dwc_ll.h b/components/hal/esp32p4/include/hal/usb_dwc_ll.h
new file mode 100644
index 00000000000..fd0685a50dd
--- /dev/null
+++ b/components/hal/esp32p4/include/hal/usb_dwc_ll.h
@@ -0,0 +1,982 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/usb_dwc_struct.h"
+#include "hal/usb_dwc_types.h"
+#include "hal/misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ----------------------------- Helper Macros ------------------------------ */
+
+// Get USB hardware instance
+#define USB_DWC_LL_GET_HW(num) (((num) == 1) ? &USB_DWC_FS : &USB_DWC_HS)
+
+/* -----------------------------------------------------------------------------
+--------------------------------- DWC Constants --------------------------------
+----------------------------------------------------------------------------- */
+
+#define USB_DWC_QTD_LIST_MEM_ALIGN              512
+#define USB_DWC_FRAME_LIST_MEM_ALIGN            512     // The frame list needs to be 512 bytes aligned (contrary to the databook)
+
+/* -----------------------------------------------------------------------------
+------------------------------- Global Registers -------------------------------
+----------------------------------------------------------------------------- */
+
+/*
+ * Interrupt bit masks of the GINTSTS and GINTMSK registers
+ */
+#define USB_DWC_LL_INTR_CORE_WKUPINT        (1 << 31)
+#define USB_DWC_LL_INTR_CORE_SESSREQINT     (1 << 30)
+#define USB_DWC_LL_INTR_CORE_DISCONNINT     (1 << 29)
+#define USB_DWC_LL_INTR_CORE_CONIDSTSCHNG   (1 << 28)
+#define USB_DWC_LL_INTR_CORE_PTXFEMP        (1 << 26)
+#define USB_DWC_LL_INTR_CORE_HCHINT         (1 << 25)
+#define USB_DWC_LL_INTR_CORE_PRTINT         (1 << 24)
+#define USB_DWC_LL_INTR_CORE_RESETDET       (1 << 23)
+#define USB_DWC_LL_INTR_CORE_FETSUSP        (1 << 22)
+#define USB_DWC_LL_INTR_CORE_INCOMPIP       (1 << 21)
+#define USB_DWC_LL_INTR_CORE_INCOMPISOIN    (1 << 20)
+#define USB_DWC_LL_INTR_CORE_OEPINT         (1 << 19)
+#define USB_DWC_LL_INTR_CORE_IEPINT         (1 << 18)
+#define USB_DWC_LL_INTR_CORE_EPMIS          (1 << 17)
+#define USB_DWC_LL_INTR_CORE_EOPF           (1 << 15)
+#define USB_DWC_LL_INTR_CORE_ISOOUTDROP     (1 << 14)
+#define USB_DWC_LL_INTR_CORE_ENUMDONE       (1 << 13)
+#define USB_DWC_LL_INTR_CORE_USBRST         (1 << 12)
+#define USB_DWC_LL_INTR_CORE_USBSUSP        (1 << 11)
+#define USB_DWC_LL_INTR_CORE_ERLYSUSP       (1 << 10)
+#define USB_DWC_LL_INTR_CORE_GOUTNAKEFF     (1 << 7)
+#define USB_DWC_LL_INTR_CORE_GINNAKEFF      (1 << 6)
+#define USB_DWC_LL_INTR_CORE_NPTXFEMP       (1 << 5)
+#define USB_DWC_LL_INTR_CORE_RXFLVL         (1 << 4)
+#define USB_DWC_LL_INTR_CORE_SOF            (1 << 3)
+#define USB_DWC_LL_INTR_CORE_OTGINT         (1 << 2)
+#define USB_DWC_LL_INTR_CORE_MODEMIS        (1 << 1)
+#define USB_DWC_LL_INTR_CORE_CURMOD         (1 << 0)
+
+/*
+ * Bit mask of interrupt generating bits of the the HPRT register. These bits
+ * are ORd into the USB_DWC_LL_INTR_CORE_PRTINT interrupt.
+ *
+ * Note: Some fields of the HPRT are W1C (write 1 clear), this we cannot do a
+ * simple read and write-back to clear the HPRT interrupt bits. Instead we need
+ * a W1C mask the non-interrupt related bits
+ */
+#define USB_DWC_LL_HPRT_W1C_MSK             (0x2E)
+#define USB_DWC_LL_HPRT_ENA_MSK             (0x04)
+#define USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG (1 << 5)
+#define USB_DWC_LL_INTR_HPRT_PRTENCHNG      (1 << 3)
+#define USB_DWC_LL_INTR_HPRT_PRTCONNDET     (1 << 1)
+
+/*
+ * Bit mask of channel interrupts (HCINTi and HCINTMSKi registers)
+ *
+ * Note: Under Scatter/Gather DMA mode, only the following interrupts can be unmasked
+ * - DESC_LS_ROLL
+ * - XCS_XACT_ERR (always unmasked)
+ * - BNAINTR
+ * - CHHLTD
+ * - XFERCOMPL
+ * The remaining interrupt bits will still be set (when the corresponding event occurs)
+ * but will not generate an interrupt. Therefore we must proxy through the
+ * USB_DWC_LL_INTR_CHAN_CHHLTD interrupt to check the other interrupt bits.
+ */
+#define USB_DWC_LL_INTR_CHAN_DESC_LS_ROLL   (1 << 13)
+#define USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR   (1 << 12)
+#define USB_DWC_LL_INTR_CHAN_BNAINTR        (1 << 11)
+#define USB_DWC_LL_INTR_CHAN_DATATGLERR     (1 << 10)
+#define USB_DWC_LL_INTR_CHAN_FRMOVRUN       (1 << 9)
+#define USB_DWC_LL_INTR_CHAN_BBLEER         (1 << 8)
+#define USB_DWC_LL_INTR_CHAN_XACTERR        (1 << 7)
+#define USB_DWC_LL_INTR_CHAN_NYET           (1 << 6)
+#define USB_DWC_LL_INTR_CHAN_ACK            (1 << 5)
+#define USB_DWC_LL_INTR_CHAN_NAK            (1 << 4)
+#define USB_DWC_LL_INTR_CHAN_STALL          (1 << 3)
+#define USB_DWC_LL_INTR_CHAN_AHBERR         (1 << 2)
+#define USB_DWC_LL_INTR_CHAN_CHHLTD         (1 << 1)
+#define USB_DWC_LL_INTR_CHAN_XFERCOMPL      (1 << 0)
+
+/*
+ * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
+ * Each QTD describes one transfer. Scatter gather mode will automatically split
+ * a transfer into multiple MPS packets. Each QTD is 64bits in size
+ *
+ * Note: The status information part of the QTD is interpreted differently depending
+ * on IN or OUT, and ISO or non-ISO
+ */
+typedef struct {
+    union {
+        struct {
+            uint32_t xfer_size: 17;
+            uint32_t aqtd_offset: 6;
+            uint32_t aqtd_valid: 1;
+            uint32_t reserved_24: 1;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t rx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } in_non_iso;
+        struct {
+            uint32_t xfer_size: 12;
+            uint32_t reserved_12_24: 13;
+            uint32_t intr_cplt: 1;
+            uint32_t reserved_26_27: 2;
+            uint32_t rx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } in_iso;
+        struct {
+            uint32_t xfer_size: 17;
+            uint32_t reserved_17_23: 7;
+            uint32_t is_setup: 1;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t tx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } out_non_iso;
+        struct {
+            uint32_t xfer_size: 12;
+            uint32_t reserved_12_24: 13;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t tx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } out_iso;
+        uint32_t buffer_status_val;
+    };
+    uint8_t *buffer;
+} usb_dwc_ll_dma_qtd_t;
+
+
+/* -----------------------------------------------------------------------------
+------------------------------- Global Registers -------------------------------
+----------------------------------------------------------------------------- */
+
+// --------------------------- GAHBCFG Register --------------------------------
+
+static inline void usb_dwc_ll_gahbcfg_en_dma_mode(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.dmaen = 1;
+}
+
+static inline void usb_dwc_ll_gahbcfg_en_slave_mode(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.dmaen = 0;
+}
+
+static inline void usb_dwc_ll_gahbcfg_set_hbstlen(usb_dwc_dev_t *hw, uint32_t burst_len)
+{
+    hw->gahbcfg_reg.hbstlen = burst_len;
+}
+
+static inline void usb_dwc_ll_gahbcfg_en_global_intr(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.glbllntrmsk = 1;
+}
+
+static inline void usb_dwc_ll_gahbcfg_dis_global_intr(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.glbllntrmsk = 0;
+}
+
+// --------------------------- GUSBCFG Register --------------------------------
+
+static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.forcehstmode = 1;
+}
+
+static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.hnpcap = 0;
+}
+
+static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.srpcap = 0;
+}
+
+static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
+{
+    hw->gusbcfg_reg.toutcal = tout_cal;
+}
+
+static inline void usb_dwc_ll_gusbcfg_set_utmi_phy(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.phyif = 1;       // 16 bits interface
+    hw->gusbcfg_reg.ulpiutmisel = 0; // UTMI+
+    hw->gusbcfg_reg.physel = 0;      // HS PHY
+}
+
+// --------------------------- GRSTCTL Register --------------------------------
+
+static inline bool usb_dwc_ll_grstctl_is_ahb_idle(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.ahbidle;
+}
+
+static inline bool usb_dwc_ll_grstctl_is_dma_req_in_progress(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.dmareq;
+}
+
+static inline void usb_dwc_ll_grstctl_flush_nptx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.txfnum = 0;     //Set the TX FIFO number to 0 to select the non-periodic TX FIFO
+    hw->grstctl_reg.txfflsh = 1;    //Flush the selected TX FIFO
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.txfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_flush_ptx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.txfnum = 1;     //Set the TX FIFO number to 1 to select the periodic TX FIFO
+    hw->grstctl_reg.txfflsh = 1;    //FLush the select TX FIFO
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.txfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_flush_rx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.rxfflsh = 1;
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.rxfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.frmcntrrst = 1;
+}
+
+static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.csftrst = 1;
+}
+
+static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.csftrst;
+}
+
+// --------------------------- GINTSTS Register --------------------------------
+
+/**
+ * @brief Reads and clears the global interrupt register
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @return uint32_t Mask of interrupts
+ */
+static inline uint32_t usb_dwc_ll_gintsts_read_and_clear_intrs(usb_dwc_dev_t *hw)
+{
+    usb_dwc_gintsts_reg_t gintsts;
+    gintsts.val = hw->gintsts_reg.val;
+    hw->gintsts_reg.val = gintsts.val;  //Write back to clear
+    return gintsts.val;
+}
+
+/**
+ * @brief Clear specific interrupts
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @param intr_msk Mask of interrupts to clear
+ */
+static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t intr_msk)
+{
+    //All GINTSTS fields are either W1C or read only. So safe to write directly
+    hw->gintsts_reg.val = intr_msk;
+}
+
+// --------------------------- GINTMSK Register --------------------------------
+
+static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    hw->gintmsk_reg.val |= intr_mask;
+}
+
+static inline void usb_dwc_ll_gintmsk_dis_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    hw->gintmsk_reg.val &= ~intr_mask;
+}
+
+// --------------------------- GRXFSIZ Register --------------------------------
+
+static inline void usb_dwc_ll_grxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t num_lines)
+{
+    //Set size in words
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->grxfsiz_reg, rxfdep, num_lines);
+}
+
+// -------------------------- GNPTXFSIZ Register -------------------------------
+
+static inline void usb_dwc_ll_gnptxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
+{
+    usb_dwc_gnptxfsiz_reg_t gnptxfsiz;
+    gnptxfsiz.val = hw->gnptxfsiz_reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfstaddr, addr);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfdep, num_lines);
+    hw->gnptxfsiz_reg.val = gnptxfsiz.val;
+}
+
+// --------------------------- GSNPSID Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
+{
+    return hw->gsnpsid_reg.val;
+}
+
+// --------------------------- GHWCFGx Register --------------------------------
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.dfifodepth;
+}
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg2_reg.hsphytype;
+}
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg2_reg.numhstchnl;
+}
+
+// --------------------------- HPTXFSIZ Register -------------------------------
+
+static inline void usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
+{
+    usb_dwc_hptxfsiz_reg_t hptxfsiz;
+    hptxfsiz.val = hw->hptxfsiz_reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfstaddr, addr);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfsize, num_lines);
+    hw->hptxfsiz_reg.val = hptxfsiz.val;
+}
+
+/* -----------------------------------------------------------------------------
+-------------------------------- Host Registers --------------------------------
+----------------------------------------------------------------------------- */
+
+// ----------------------------- HCFG Register ---------------------------------
+
+static inline void usb_dwc_ll_hcfg_en_perio_sched(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.perschedena = 1;
+}
+
+static inline void usb_dwc_ll_hcfg_dis_perio_sched(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.perschedena = 0;
+}
+
+/**
+ * Sets the length of the frame list
+ *
+ * @param num_entires Number of entries in the frame list
+ */
+static inline void usb_dwc_ll_hcfg_set_num_frame_list_entries(usb_dwc_dev_t *hw, usb_hal_frame_list_len_t num_entries)
+{
+    uint32_t frlisten;
+    switch (num_entries) {
+        case USB_HAL_FRAME_LIST_LEN_8:
+            frlisten = 0;
+            break;
+        case USB_HAL_FRAME_LIST_LEN_16:
+            frlisten = 1;
+            break;
+        case USB_HAL_FRAME_LIST_LEN_32:
+            frlisten = 2;
+            break;
+        default: //USB_HAL_FRAME_LIST_LEN_64
+            frlisten = 3;
+            break;
+    }
+    hw->hcfg_reg.frlisten = frlisten;
+}
+
+static inline void usb_dwc_ll_hcfg_en_scatt_gatt_dma(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.descdma = 1;
+}
+
+static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.fslssupp = 1;
+}
+
+/**
+ * @brief Set FSLS PHY clock
+ *
+ * @attention This function should only be called if FSLS PHY is selected
+ * @param[in] hw    Start address of the DWC_OTG registers
+ */
+static inline void usb_dwc_ll_hcfg_set_fsls_phy_clock(usb_dwc_dev_t *hw)
+{
+    /*
+    Indicate to the OTG core what speed the PHY clock is at
+    Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
+          so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
+    */
+    usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+    hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2;
+}
+
+// ----------------------------- HFIR Register ---------------------------------
+
+/**
+ * @brief Set Frame Interval
+ *
+ * @attention This function should only be called if FSLS PHY is selected
+ * @param[in] hw    Start address of the DWC_OTG registers
+ */
+static inline void usb_dwc_ll_hfir_set_frame_interval(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hfir_reg_t hfir;
+    hfir.val = hw->hfir_reg.val;
+    hfir.hfirrldctrl = 0;       // Disable dynamic loading
+    /*
+    Set frame interval to be equal to 1ms
+    Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
+          so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
+    */
+    usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+    hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000;
+    hw->hfir_reg.val = hfir.val;
+}
+
+// ----------------------------- HFNUM Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_hfnum_get_frame_time_rem(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hfnum_reg, frrem);
+}
+
+static inline uint32_t usb_dwc_ll_hfnum_get_frame_num(usb_dwc_dev_t *hw)
+{
+    return hw->hfnum_reg.frnum;
+}
+
+// ---------------------------- HPTXSTS Register -------------------------------
+
+static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_top(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxqtop);
+}
+
+static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_space_avail(usb_dwc_dev_t *hw)
+{
+    return hw->hptxsts_reg.ptxqspcavail;
+}
+
+static inline uint32_t usb_dwc_ll_ptxsts_get_ptxf_space_avail(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxfspcavail);
+}
+
+// ----------------------------- HAINT Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_haint_get_chan_intrs(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->haint_reg, haint);
+}
+
+// --------------------------- HAINTMSK Register -------------------------------
+
+static inline void usb_dwc_ll_haintmsk_en_chan_intr(usb_dwc_dev_t *hw, uint32_t mask)
+{
+
+    hw->haintmsk_reg.val |= mask;
+}
+
+static inline void usb_dwc_ll_haintmsk_dis_chan_intr(usb_dwc_dev_t *hw, uint32_t mask)
+{
+    hw->haintmsk_reg.val &= ~mask;
+}
+
+// --------------------------- HFLBAddr Register -------------------------------
+
+/**
+ * @brief Set the base address of the scheduling frame list
+ *
+ * @note For some reason, this address must be 512 bytes aligned or else a bunch of frames will not be scheduled when
+ *       the frame list rolls over. However, according to the databook, there is no mention of the HFLBAddr needing to
+ *       be aligned.
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @param addr Base address of the scheduling frame list
+ */
+static inline void usb_dwc_ll_hflbaddr_set_base_addr(usb_dwc_dev_t *hw, uint32_t addr)
+{
+    hw->hflbaddr_reg.hflbaddr = addr;
+}
+
+/**
+ * @brief Get the base address of the scheduling frame list
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @return uint32_t Base address of the scheduling frame list
+ */
+static inline uint32_t usb_dwc_ll_hflbaddr_get_base_addr(usb_dwc_dev_t *hw)
+{
+    return hw->hflbaddr_reg.hflbaddr;
+}
+
+// ----------------------------- HPRT Register ---------------------------------
+
+static inline usb_dwc_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw)
+{
+    return (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+}
+
+static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prttstctl;
+}
+
+static inline void usb_dwc_ll_hprt_set_test_ctl(usb_dwc_dev_t *hw, uint32_t test_mode)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prttstctl = test_mode;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_en_pwr(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtpwr = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_dis_pwr(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtpwr = 0;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline uint32_t usb_dwc_ll_hprt_get_pwr_line_status(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtlnsts;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_reset(usb_dwc_dev_t *hw, bool reset)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtrst = reset;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_reset(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtrst;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_suspend(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtsusp = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_suspend(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtsusp;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_resume(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtres = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_clr_port_resume(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtres = 0;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_resume(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtres;
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_overcur(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtovrcurract;
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_en(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtena;
+}
+
+static inline void usb_dwc_ll_hprt_port_dis(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtena = 1;        //W1C to disable
+    //we want to W1C ENA but not W1C the interrupt bits
+    hw->hprt_reg.val = hprt.val & ((~USB_DWC_LL_HPRT_W1C_MSK) | USB_DWC_LL_HPRT_ENA_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_conn_status(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtconnsts;
+}
+
+static inline uint32_t usb_dwc_ll_hprt_intr_read_and_clear(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    //We want to W1C the interrupt bits but not that ENA
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_ENA_MSK);
+    //Return only the interrupt bits
+    return (hprt.val & (USB_DWC_LL_HPRT_W1C_MSK & ~(USB_DWC_LL_HPRT_ENA_MSK)));
+}
+
+static inline void usb_dwc_ll_hprt_intr_clear(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hw->hprt_reg.val = ((hprt.val & ~USB_DWC_LL_HPRT_ENA_MSK) & ~USB_DWC_LL_HPRT_W1C_MSK) | intr_mask;
+}
+
+//Per Channel registers
+
+// --------------------------- HCCHARi Register --------------------------------
+
+static inline void usb_dwc_ll_hcchar_enable_chan(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.chena = 1;
+}
+
+static inline bool usb_dwc_ll_hcchar_chan_is_enabled(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    return chan->hcchar_reg.chena;
+}
+
+static inline void usb_dwc_ll_hcchar_disable_chan(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.chdis = 1;
+}
+
+static inline void usb_dwc_ll_hcchar_set_odd_frame(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.oddfrm = 1;
+}
+
+static inline void usb_dwc_ll_hcchar_set_even_frame(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.oddfrm = 0;
+}
+
+static inline void usb_dwc_ll_hcchar_set_dev_addr(volatile usb_dwc_host_chan_regs_t *chan, uint32_t addr)
+{
+    chan->hcchar_reg.devaddr = addr;
+}
+
+static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_dwc_xfer_type_t type)
+{
+    chan->hcchar_reg.eptype = (uint32_t)type;
+}
+
+//Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause
+//each packet to be preceded by a PREamble packet
+static inline void usb_dwc_ll_hcchar_set_lspddev(volatile usb_dwc_host_chan_regs_t *chan, bool is_ls)
+{
+    chan->hcchar_reg.lspddev = is_ls;
+}
+
+static inline void usb_dwc_ll_hcchar_set_dir(volatile usb_dwc_host_chan_regs_t *chan, bool is_in)
+{
+    chan->hcchar_reg.epdir = is_in;
+}
+
+static inline void usb_dwc_ll_hcchar_set_ep_num(volatile usb_dwc_host_chan_regs_t *chan, uint32_t num)
+{
+    chan->hcchar_reg.epnum = num;
+}
+
+static inline void usb_dwc_ll_hcchar_set_mps(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mps)
+{
+    chan->hcchar_reg.mps = mps;
+}
+
+static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_dwc_xfer_type_t type, bool is_in, bool is_ls)
+{
+    //Sets all persistent fields of the channel over its lifetimez
+    usb_dwc_ll_hcchar_set_dev_addr(chan, dev_addr);
+    usb_dwc_ll_hcchar_set_ep_type(chan, type);
+    usb_dwc_ll_hcchar_set_lspddev(chan, is_ls);
+    usb_dwc_ll_hcchar_set_dir(chan, is_in);
+    usb_dwc_ll_hcchar_set_ep_num(chan, ep_num);
+    usb_dwc_ll_hcchar_set_mps(chan, mps);
+}
+
+// ---------------------------- HCINTi Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_hcint_read_and_clear_intrs(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    usb_dwc_hcint_reg_t hcint;
+    hcint.val = chan->hcint_reg.val;
+    chan->hcint_reg.val = hcint.val;
+    return hcint.val;
+}
+
+// --------------------------- HCINTMSKi Register ------------------------------
+
+static inline void usb_dwc_ll_hcintmsk_set_intr_mask(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mask)
+{
+    chan->hcintmsk_reg.val = mask;
+}
+
+// ---------------------------- HCTSIZi Register -------------------------------
+
+static inline void usb_dwc_ll_hctsiz_set_pid(volatile usb_dwc_host_chan_regs_t *chan, uint32_t data_pid)
+{
+    if (data_pid == 0) {
+        chan->hctsiz_reg.pid = 0;
+    } else {
+        chan->hctsiz_reg.pid = 2;
+    }
+}
+
+static inline uint32_t usb_dwc_ll_hctsiz_get_pid(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    if (chan->hctsiz_reg.pid == 0) {
+        return 0;   //DATA0
+    } else {
+        return 1;   //DATA1
+    }
+}
+
+static inline void usb_dwc_ll_hctsiz_set_qtd_list_len(volatile usb_dwc_host_chan_regs_t *chan, int qtd_list_len)
+{
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    //Set the length of the descriptor list. NTD occupies xfersize[15:8]
+    hctsiz.xfersize &= ~(0xFF << 8);
+    hctsiz.xfersize |= ((qtd_list_len - 1) & 0xFF) << 8;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    hctsiz.dopng = 0;         //Don't do ping
+    /*
+    Set SCHED_INFO which occupies xfersize[7:0]
+    It is always set to 0xFF for full speed and not used in Bulk/Ctrl channels
+    */
+    hctsiz.xfersize |= 0xFF;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+static inline void usb_dwc_ll_hctsiz_set_sched_info(volatile usb_dwc_host_chan_regs_t *chan, int tokens_per_frame, int offset)
+{
+    // @see USB-OTG databook: Table 5-47
+    // This function is relevant only for HS
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    uint8_t sched_info_val;
+    switch (tokens_per_frame) {
+        case 1:
+            offset %= 8; // If the required offset > 8, we must wrap around to SCHED_INFO size = 8
+            sched_info_val = 0b00000001;
+            break;
+        case 2:
+            offset %= 4;
+            sched_info_val = 0b00010001;
+            break;
+        case 4:
+            offset %= 2;
+            sched_info_val = 0b01010101;
+            break;
+        case 8:
+            offset = 0;
+            sched_info_val = 0b11111111;
+            break;
+        default:
+            abort();
+            break;
+    }
+    sched_info_val <<= offset;
+    hctsiz.xfersize &= ~(0xFF);
+    hctsiz.xfersize |= sched_info_val;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+// ---------------------------- HCDMAi Register --------------------------------
+
+static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx)
+{
+    usb_dwc_hcdma_reg_t hcdma;
+    /*
+    Set the base address portion of the field which is dmaaddr[31:9]. This is
+    the based address of the QTD list and must be 512 bytes aligned
+    */
+    hcdma.dmaaddr = ((uint32_t)dmaaddr) & 0xFFFFFE00;
+    //Set the current QTD index in the QTD list which is dmaaddr[8:3]
+    hcdma.dmaaddr |= (qtd_idx & 0x3F) << 3;
+    //dmaaddr[2:0] is reserved thus doesn't not need to be set
+
+    chan->hcdma_reg.val = hcdma.val;
+}
+
+static inline int usb_dwc_ll_hcdam_get_cur_qtd_idx(usb_dwc_host_chan_regs_t *chan)
+{
+    //The current QTD index is dmaaddr[8:3]
+    return (chan->hcdma_reg.dmaaddr >> 3) & 0x3F;
+}
+
+// ---------------------------- HCDMABi Register -------------------------------
+
+static inline void *usb_dwc_ll_hcdmab_get_buff_addr(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    return (void *)chan->hcdmab_reg.hcdmab;
+}
+
+/* -----------------------------------------------------------------------------
+---------------------------- Scatter/Gather DMA QTDs ---------------------------
+----------------------------------------------------------------------------- */
+
+// ---------------------------- Helper Functions -------------------------------
+
+/**
+ * @brief Get the base address of a channel's register based on the channel's index
+ *
+ * @param dev Start address of the DWC_OTG registers
+ * @param chan_idx The channel's index
+ * @return usb_dwc_host_chan_regs_t* Pointer to channel's registers
+ */
+static inline usb_dwc_host_chan_regs_t *usb_dwc_ll_chan_get_regs(usb_dwc_dev_t *dev, int chan_idx)
+{
+    return &dev->host_chans[chan_idx];
+}
+
+// ------------------------------ QTD related ----------------------------------
+
+#define USB_DWC_LL_QTD_STATUS_SUCCESS      0x0     //If QTD was processed, it indicates the data was transmitted/received successfully
+#define USB_DWC_LL_QTD_STATUS_PKTERR       0x1     //Data transmitted/received with errors (CRC/Timeout/Stuff/False EOP/Excessive NAK).
+//Note: 0x2 is reserved
+#define USB_DWC_LL_QTD_STATUS_BUFFER       0x3     //AHB error occurred.
+#define USB_DWC_LL_QTD_STATUS_NOT_EXECUTED 0x4     //QTD as never processed
+
+/**
+ * @brief Set a QTD for a non isochronous IN transfer
+ *
+ * @param qtd Pointer to the QTD
+ * @param data_buff Pointer to buffer containing the data to transfer
+ * @param xfer_len Number of bytes in transfer. Setting 0 will do a zero length IN transfer.
+ *                 Non zero length must be multiple of the endpoint's MPS.
+ * @param hoc Halt on complete (will generate an interrupt and halt the channel)
+ */
+static inline void usb_dwc_ll_qtd_set_in(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc)
+{
+    qtd->buffer = data_buff;        //Set pointer to data buffer
+    qtd->buffer_status_val = 0;     //Reset all flags to zero
+    qtd->in_non_iso.xfer_size = xfer_len;
+    if (hoc) {
+        qtd->in_non_iso.intr_cplt = 1;  //We need to set this to distinguish between a halt due to a QTD
+        qtd->in_non_iso.eol = 1;        //Used to halt the channel at this qtd
+    }
+    qtd->in_non_iso.active = 1;
+}
+
+/**
+ * @brief Set a QTD for a non isochronous OUT transfer
+ *
+ * @param qtd Pointer to the QTD
+ * @param data_buff Pointer to buffer containing the data to transfer
+ * @param xfer_len Number of bytes to transfer. Setting 0 will do a zero length transfer.
+ *                 For ctrl setup packets, this should be set to 8.
+ * @param hoc Halt on complete (will generate an interrupt)
+ * @param is_setup Indicates whether this is a control transfer setup packet or a normal OUT Data transfer.
+ *                 (As per the USB protocol, setup packets cannot be STALLd or NAKd by the device)
+ */
+static inline void usb_dwc_ll_qtd_set_out(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc, bool is_setup)
+{
+    qtd->buffer = data_buff;        //Set pointer to data buffer
+    qtd->buffer_status_val = 0;     //Reset all flags to zero
+    qtd->out_non_iso.xfer_size = xfer_len;
+    if (is_setup) {
+        qtd->out_non_iso.is_setup = 1;
+    }
+    if (hoc) {
+        qtd->in_non_iso.intr_cplt = 1;  //We need to set this to distinguish between a halt due to a QTD
+        qtd->in_non_iso.eol = 1;        //Used to halt the channel at this qtd
+    }
+    qtd->out_non_iso.active = 1;
+}
+
+/**
+ * @brief Set a QTD as NULL
+ *
+ * This sets the QTD to a value of 0. This is only useful when you need to insert
+ * blank QTDs into a list of QTDs
+ *
+ * @param qtd Pointer to the QTD
+ */
+static inline void usb_dwc_ll_qtd_set_null(usb_dwc_ll_dma_qtd_t *qtd)
+{
+    qtd->buffer = NULL;
+    qtd->buffer_status_val = 0;     //Disable qtd by clearing it to zero. Used by interrupt/isoc as an unscheudled frame
+}
+
+/**
+ * @brief Get the status of a QTD
+ *
+ * When a channel gets halted, call this to check whether each QTD was executed successfully
+ *
+ * @param qtd Pointer to the QTD
+ * @param[out] rem_len Number of bytes ramining in the QTD
+ * @param[out] status Status of the QTD
+ */
+static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem_len, int *status)
+{
+    //Status is the same regardless of IN or OUT
+    if (qtd->in_non_iso.active) {
+        //QTD was never processed
+        *status = USB_DWC_LL_QTD_STATUS_NOT_EXECUTED;
+    } else {
+        *status = qtd->in_non_iso.rx_status;
+    }
+    *rem_len = qtd->in_non_iso.xfer_size;
+    //Clear the QTD just for safety
+    qtd->buffer_status_val = 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32p4/include/hal/usb_utmi_ll.h b/components/hal/esp32p4/include/hal/usb_utmi_ll.h
index 14eb8fd1766..f2ea99d8b6b 100644
--- a/components/hal/esp32p4/include/hal/usb_utmi_ll.h
+++ b/components/hal/esp32p4/include/hal/usb_utmi_ll.h
@@ -53,7 +53,7 @@ FORCE_INLINE_ATTR void _usb_utmi_ll_enable_bus_clock(bool clk_en)
 /**
  * @brief Reset the USB UTMI PHY and USB_DWC_HS controller
  */
-FORCE_INLINE_ATTR void usb_utmi_ll_reset_register(void)
+FORCE_INLINE_ATTR void _usb_utmi_ll_reset_register(void)
 {
     // Reset the USB_UTMI and USB_DWC_HS
     LP_AON_CLKRST.hp_usb_clkrst_ctrl1.rst_en_usb_otg20 = 1;
@@ -63,7 +63,7 @@ FORCE_INLINE_ATTR void usb_utmi_ll_reset_register(void)
 }
 
 // P_AON_CLKRST.hp_usb_clkrst_ctrlx is shared register, so this function must be used in an atomic way
-#define usb_utmi_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_utmi_ll_reset_register(__VA_ARGS__)
+#define usb_utmi_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_utmi_ll_reset_register(__VA_ARGS__)
 
 /**
  * @brief Enable precise detection of VBUS
diff --git a/components/hal/esp32p4/touch_sensor_hal.c b/components/hal/esp32p4/touch_sensor_hal.c
deleted file mode 100644
index 450e3ab89ba..00000000000
--- a/components/hal/esp32p4/touch_sensor_hal.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <string.h>
-#include "soc/soc_pins.h"
-#include "hal/touch_sensor_ll.h"
-#include "hal/touch_sensor_hal.h"
-#include "hal/touch_sensor_types.h"
-#include "soc/soc_caps.h"
-
-typedef struct {
-    int deep_slp_chan;
-    touch_hal_config_t slp_cfg;
-    bool apply_slp_cfg;
-} touch_hal_deep_sleep_obj_t;
-
-static touch_hal_deep_sleep_obj_t s_touch_slp_obj = {
-    .deep_slp_chan = -1,
-    .apply_slp_cfg = false,
-};
-
-void touch_hal_config_controller(const touch_hal_config_t *cfg)
-{
-    HAL_ASSERT(cfg);
-    touch_ll_sleep_set_channel_num(TOUCH_LL_NULL_CHANNEL);
-    touch_ll_set_out_mode(cfg->output_mode);
-    touch_ll_set_power_on_wait_cycle(cfg->power_on_wait_ticks);
-    touch_ll_set_measure_interval_ticks(cfg->meas_interval_ticks);
-    if (cfg->timeout_ticks) {
-        touch_ll_timeout_enable(cfg->timeout_ticks);
-    } else {
-        touch_ll_timeout_disable();
-    }
-
-    touch_ll_sample_cfg_set_engaged_num(cfg->sample_cfg_num);
-    for (int i = 0; i < cfg->sample_cfg_num; i++) {
-        touch_ll_set_clock_div(i, cfg->sample_cfg[i].div_num);
-        touch_ll_set_charge_times(i, cfg->sample_cfg[i].charge_times);
-        touch_ll_sample_cfg_set_rc_filter(i, cfg->sample_cfg[i].rc_filter_cap, cfg->sample_cfg[i].rc_filter_res);
-        touch_ll_sample_cfg_set_driver(i, cfg->sample_cfg[i].low_drv, cfg->sample_cfg[i].high_drv);
-        touch_ll_sample_cfg_bypass_shield_output(i, cfg->sample_cfg[i].bypass_shield_output);
-        touch_ll_sample_cfg_set_bias_voltage(i, cfg->sample_cfg[i].bias_volt);
-    }
-}
-
-void touch_hal_save_sleep_config(int deep_slp_chan, const touch_hal_config_t *deep_slp_cfg)
-{
-    s_touch_slp_obj.deep_slp_chan = deep_slp_chan;
-    /* If particular deep sleep configuration is given, save it and apply it before entering the deep sleep */
-    if (deep_slp_chan >= 0 && deep_slp_cfg) {
-        s_touch_slp_obj.apply_slp_cfg = true;
-        memcpy(&s_touch_slp_obj.slp_cfg, deep_slp_cfg, sizeof(touch_hal_config_t));
-    } else {
-        s_touch_slp_obj.apply_slp_cfg = false;
-    }
-}
-
-//This function will only be called when the chip is going to deep sleep.
-static void s_touch_hal_apply_sleep_config(void)
-{
-    /* Apply the particular configuration for deep sleep */
-    if (s_touch_slp_obj.apply_slp_cfg) {
-        touch_hal_config_controller(&s_touch_slp_obj.slp_cfg);
-    }
-    /* Whether to enable touch sensor wake-up the chip from deep sleep */
-    if (s_touch_slp_obj.deep_slp_chan >= 0) {
-        touch_ll_sleep_set_channel_num(s_touch_slp_obj.deep_slp_chan);
-        touch_ll_set_channel_mask(BIT(s_touch_slp_obj.deep_slp_chan));
-    } else {
-        touch_ll_sleep_set_channel_num(TOUCH_LL_NULL_CHANNEL);
-    }
-}
-
-void touch_hal_prepare_deep_sleep(void)
-{
-    s_touch_hal_apply_sleep_config();
-    touch_ll_sleep_reset_benchmark();
-    touch_ll_intr_clear(TOUCH_LL_INTR_MASK_ALL);
-}
diff --git a/components/hal/esp32s2/include/hal/cache_ll.h b/components/hal/esp32s2/include/hal/cache_ll.h
index 0a2ecbde7a0..16f7a7fe900 100644
--- a/components/hal/esp32s2/include/hal/cache_ll.h
+++ b/components/hal/esp32s2/include/hal/cache_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -551,6 +551,26 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
     return valid;
 }
 
+/**
+ * @brief Get cache debug status 0
+ *
+ */
+__attribute__((always_inline))
+static inline uint32_t cache_ll_get_dbg_status0(void)
+{
+    return REG_READ(EXTMEM_CACHE_DBG_STATUS0_REG);
+}
+
+/**
+ * @brief Get cache debug status 1
+ *
+ */
+__attribute__((always_inline))
+static inline uint32_t cache_ll_get_dbg_status1(void)
+{
+    return REG_READ(EXTMEM_CACHE_DBG_STATUS1_REG);
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32s2/include/hal/gpio_ll.h b/components/hal/esp32s2/include/hal/gpio_ll.h
index 382cc455ad5..233b86c3677 100644
--- a/components/hal/esp32s2/include/hal/gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/gpio_ll.h
@@ -338,15 +338,15 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t
 {
     if (level) {
         if (gpio_num < 32) {
-            hw->out_w1ts = (1 << gpio_num);
+            hw->out_w1ts = 1 << gpio_num;
         } else {
-            hw->out1_w1ts.data = (1 << (gpio_num - 32));
+            hw->out1_w1ts.val = 1 << (gpio_num - 32);
         }
     } else {
         if (gpio_num < 32) {
-            hw->out_w1tc = (1 << gpio_num);
+            hw->out_w1tc = 1 << gpio_num;
         } else {
-            hw->out1_w1tc.data = (1 << (gpio_num - 32));
+            hw->out1_w1tc.val = 1 << (gpio_num - 32);
         }
     }
 }
diff --git a/components/hal/esp32s2/include/hal/i2c_ll.h b/components/hal/esp32s2/include/hal/i2c_ll.h
index 9391b32b270..840937e4e8d 100644
--- a/components/hal/esp32s2/include/hal/i2c_ll.h
+++ b/components/hal/esp32s2/include/hal/i2c_ll.h
@@ -15,6 +15,7 @@
 #include "hal/i2c_types.h"
 #include "esp_attr.h"
 #include "hal/misc.h"
+#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -72,6 +73,8 @@ typedef enum {
 #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT   (9)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2000)  // 2000 is not default value on esp32s2, but 0 is not good to be default
 
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff)
+
 /**
  * @brief  Calculate I2C bus frequency
  *
@@ -309,7 +312,23 @@ static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_e
 __attribute__((always_inline))
 static inline void i2c_ll_slave_get_stretch_cause(i2c_dev_t *hw, i2c_slave_stretch_cause_t *stretch_cause)
 {
-    // Not supported on esp32s2
+    switch (hw->status_reg.stretch_cause) {
+    case 0:
+        *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_ADDRESS_MATCH;
+        break;
+    case 1:
+        *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_TX_EMPTY;
+        break;
+    case 2:
+        *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_RX_FULL;
+        break;
+    case 3:
+        *stretch_cause = I2C_SLAVE_STRETCH_CAUSE_SENDING_ACK;
+        break;
+    default:
+        HAL_ASSERT(false);
+        break;
+    }
 }
 
 /**
@@ -858,6 +877,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    dev->scl_stretch_conf.stretch_protect_num = protect_num;
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -885,6 +914,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return clk_cycle_num_per_us * timeout_us;
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->status_reg.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32s2/include/hal/i2s_ll.h b/components/hal/esp32s2/include/hal/i2s_ll.h
index 4399631e1ee..a5221fbc5c3 100644
--- a/components/hal/esp32s2/include/hal/i2s_ll.h
+++ b/components/hal/esp32s2/include/hal/i2s_ll.h
@@ -90,18 +90,11 @@ static inline void i2s_ll_dma_enable_eof_on_fifo_empty(i2s_dev_t *hw, bool en)
  */
 static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
 {
+    (void) i2s_id;
     if (enable) {
-        if (i2s_id == 0) {
-            DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
-        } else {
-            DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN);
-        }
+        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
     } else {
-        if (i2s_id == 0) {
-            DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
-        } else {
-            DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S1_CLK_EN);
-        }
+        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
     }
 }
 
@@ -116,13 +109,9 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable)
  */
 static inline void i2s_ll_reset_register(int i2s_id)
 {
-    if (i2s_id == 0) {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
-    } else {
-        DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST);
-        DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S1_RST);
-    }
+    (void) i2s_id;
+    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
+    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
 }
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
@@ -357,7 +346,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 
 /**
  * @brief Configure I2S RX module clock divider
- * @note mclk on ESP32 is shared by both TX and RX channel
+ * @note mclk on ESP32S2 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
  * @param mclk_div The mclk division coefficients
diff --git a/components/hal/esp32s2/include/hal/touch_sensor_hal.h b/components/hal/esp32s2/include/hal/touch_sensor_hal.h
index b42532c78f9..6d2770d4ee2 100644
--- a/components/hal/esp32s2/include/hal/touch_sensor_hal.h
+++ b/components/hal/esp32s2/include/hal/touch_sensor_hal.h
@@ -15,7 +15,7 @@
 #pragma once
 
 #include "hal/touch_sensor_ll.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 
 #include_next "hal/touch_sensor_hal.h"
 
@@ -278,14 +278,10 @@ void touch_hal_filter_get_config(touch_filter_config_t *filter_info);
 /**
  * Enable touch sensor filter and detection algorithm.
  * For more details on the detection algorithm, please refer to the application documentation.
+ *
+ * @param enable set true to enable the filter
  */
-#define touch_hal_filter_enable() touch_ll_filter_enable()
-
-/**
- * Disable touch sensor filter and detection algorithm.
- * For more details on the detection algorithm, please refer to the application documentation.
- */
-#define touch_hal_filter_disable() touch_ll_filter_disable()
+#define touch_hal_filter_enable(enable) touch_ll_filter_enable(enable)
 
 /************************ Denoise register setting ************************/
 
@@ -326,7 +322,7 @@ void touch_hal_denoise_enable(void);
  * This denoise function filters out interference introduced on all channels,
  * such as noise introduced by the power supply and external EMI.
  */
-#define touch_hal_denoise_disable() touch_ll_denoise_disable()
+#define touch_hal_denoise_disable() touch_ll_denoise_enable(false)
 
 /**
  * Set internal reference capacitance of denoise channel.
@@ -391,7 +387,7 @@ void touch_hal_denoise_enable(void);
  *
  * @param pad_num Touch sensor channel number.
  */
-#define touch_hal_waterproof_set_sheild_driver(driver_level) touch_ll_waterproof_set_sheild_driver(driver_level)
+#define touch_hal_waterproof_set_sheild_driver(driver_level) touch_ll_waterproof_set_shield_driver(driver_level)
 
 /**
  * Get max equivalent capacitance for shield channel.
@@ -400,7 +396,7 @@ void touch_hal_denoise_enable(void);
  *
  * @param pad_num Touch sensor channel number.
  */
-#define touch_hal_waterproof_get_sheild_driver(driver_level) touch_ll_waterproof_get_sheild_driver(driver_level)
+#define touch_hal_waterproof_get_sheild_driver(driver_level) touch_ll_waterproof_get_shield_driver(driver_level)
 
 /**
  * Set parameter of waterproof function.
@@ -430,7 +426,7 @@ void touch_hal_waterproof_enable(void);
 /**
  * Disable parameter of waterproof function.
  */
-#define touch_hal_waterproof_disable() touch_ll_waterproof_disable()
+#define touch_hal_waterproof_disable() touch_ll_waterproof_enable(false)
 
 /************************ Proximity register setting ************************/
 
@@ -550,13 +546,9 @@ void touch_hal_sleep_channel_enable(touch_pad_t pad_num, bool enable);
 
 /**
  * Enable proximity function for sleep pad.
+ * @param enable the proximity sensing
  */
-#define touch_hal_sleep_enable_approach() touch_ll_sleep_enable_proximity_sensing()
-
-/**
- * Disable proximity function for sleep pad.
- */
-#define touch_hal_sleep_disable_approach() touch_ll_sleep_disable_proximity_sensing()
+#define touch_hal_sleep_enable_approach(enable) touch_ll_sleep_enable_proximity_sensing(enable)
 
 /**
  * Read benchmark of touch sensor for sleep pad.
diff --git a/components/hal/esp32s2/include/hal/touch_sensor_ll.h b/components/hal/esp32s2/include/hal/touch_sensor_ll.h
index 0cc5069d2f2..1b2bda597e8 100644
--- a/components/hal/esp32s2/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32s2/include/hal/touch_sensor_ll.h
@@ -16,26 +16,754 @@
 
 #include <stdlib.h>
 #include <stdbool.h>
+#include "esp_bit_defs.h"
 #include "hal/misc.h"
+#include "hal/assert.h"
 #include "soc/touch_sensor_periph.h"
 #include "soc/soc_caps.h"
 #include "soc/sens_struct.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_io_struct.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sens_types.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 #define TOUCH_LL_READ_RAW           0x0
-#define TOUCH_LL_READ_BENCHMARK      0x2
+#define TOUCH_LL_READ_BENCHMARK     0x2
 #define TOUCH_LL_READ_SMOOTH        0x3
+
 #define TOUCH_LL_TIMER_FORCE_DONE   0x3
 #define TOUCH_LL_TIMER_DONE         0x0
 
-#define TOUCH_LL_PAD_MEASURE_WAIT_MAX      (0xFF)  /*!<The timer frequency is 8Mhz, the max value is 0xff */
+// Interrupt mask
+#define TOUCH_LL_INTR_MASK_SCAN_DONE        BIT(4)
+#define TOUCH_LL_INTR_MASK_DONE             BIT(6)
+#define TOUCH_LL_INTR_MASK_ACTIVE           BIT(7)
+#define TOUCH_LL_INTR_MASK_INACTIVE         BIT(8)
+#define TOUCH_LL_INTR_MASK_TIMEOUT          BIT(18)
+/* S2 does NOT really have the prox done interrupt,
+   the TOUCH_LL_INTR_MASK_PROX_DONE signal is used for software simulation
+   So it is not included in the TOUCH_LL_INTR_MASK_ALL */
+#define TOUCH_LL_INTR_MASK_PROX_DONE        BIT(31)
+#define TOUCH_LL_INTR_MASK_ALL              (TOUCH_LL_INTR_MASK_SCAN_DONE | \
+                                             TOUCH_LL_INTR_MASK_DONE | \
+                                             TOUCH_LL_INTR_MASK_ACTIVE | \
+                                             TOUCH_LL_INTR_MASK_INACTIVE | \
+                                             TOUCH_LL_INTR_MASK_TIMEOUT)
+
+#define TOUCH_LL_FULL_CHANNEL_MASK          ((uint16_t)((1U << SOC_TOUCH_SENSOR_NUM) - 1))
+#define TOUCH_LL_NULL_CHANNEL               (0)  // Null Channel id. Used for disabling some functions like sleep/proximity/waterproof
+
+#define TOUCH_LL_PAD_MEASURE_WAIT_MAX      (0xFF)      // The timer frequency is 8Mhz, the max value is 0xff
+#define TOUCH_LL_ACTIVE_THRESH_MAX         (0x3FFFFF)  // Max channel active threshold
+#define TOUCH_LL_TIMEOUT_MAX               (0x3FFFFF)  // Max timeout value
+
+/**
+ * Enable/disable clock gate of touch sensor.
+ *
+ * @param enable true/false.
+ */
+static inline void touch_ll_enable_clock_gate(bool enable)
+{
+    RTCCNTL.touch_ctrl2.touch_clkgate_en = enable; //enable touch clock for FSM. or force enable.
+}
+
+/**
+ * Enable/disable clock gate of touch sensor.
+ *
+ * @param enable true/false.
+ */
+static inline void touch_ll_reset_module(void)
+{
+    RTCCNTL.touch_ctrl2.touch_reset = 1;
+    RTCCNTL.touch_ctrl2.touch_reset = 0;    // Should be set 0.
+}
+
+/*********************************** Interrupts *******************************/
+/**
+ * Enable touch sensor interrupt by bitmask.
+ *
+ * @param int_mask interrupt mask
+ */
+static inline void touch_ll_interrupt_enable(uint32_t int_mask)
+{
+    uint32_t mask = RTCCNTL.int_ena.val;
+    mask |= (int_mask & TOUCH_LL_INTR_MASK_ALL);
+    RTCCNTL.int_ena.val = mask;
+}
+
+/**
+ * Disable touch sensor interrupt by bitmask.
+ *
+ * @param int_mask interrupt mask
+ */
+static inline void touch_ll_interrupt_disable(uint32_t int_mask)
+{
+    uint32_t mask = RTCCNTL.int_ena.val;
+    mask &= ~(int_mask & TOUCH_LL_INTR_MASK_ALL);
+    RTCCNTL.int_ena.val = mask;
+}
+
+/**
+ * Clear touch sensor interrupt by bitmask.
+ *
+ * @param int_mask Pad mask to clear interrupts
+ */
+__attribute__((always_inline))
+static inline void touch_ll_interrupt_clear(uint32_t int_mask)
+{
+    RTCCNTL.int_clr.val = int_mask & TOUCH_LL_INTR_MASK_ALL;
+}
+
+/**
+ * Get the bitmask of touch sensor interrupt status.
+ *
+ * @return type interrupt type
+ */
+__attribute__((always_inline))
+static inline uint32_t touch_ll_get_intr_status_mask(void)
+{
+    uint32_t intr_st = RTCCNTL.int_st.val;
+    return intr_st & TOUCH_LL_INTR_MASK_ALL;
+}
+
+/********************************* Status Info ********************************/
+/**
+ * Get the current measure channel. Touch sensor measurement is cyclic scan mode.
+ *
+ * @return
+ *      - touch channel number
+ */
+__attribute__((always_inline))
+static inline uint32_t touch_ll_get_current_meas_channel(void)
+{
+    return SENS.sar_touch_status0.touch_scan_curr;
+}
+
+/**
+ * Get touch sensor measure status. No block.
+ *
+ * @return
+ *      - If touch sensors measure done.
+ */
+__attribute__((always_inline))
+static inline bool touch_ll_is_measure_done(void)
+{
+    return (bool)SENS.sar_touch_chn_st.touch_meas_done;
+}
+
+/**
+ * Get the touch sensor active channel mask, usually used in ISR to decide which channels are 'touched'.
+ *
+ * @param active_mask The touch channel status. e.g. Touch1 trigger status is `status_mask & (BIT1)`.
+ */
+__attribute__((always_inline))
+static inline void touch_ll_get_active_channel_mask(uint32_t *active_mask)
+{
+    *active_mask = SENS.sar_touch_chn_st.touch_pad_active;
+}
+
+/**************************** Measurement Configuration ***********************/
+/**
+ * @brief Enable or disable the channel that will be scanned.
+ * @note  The shield channel should not be enabled to scan here
+ *
+ * @param chan_mask The channel mask to be enabled or disabled
+ * @param enable Enable or disable the channel mask
+ */
+__attribute__((always_inline))
+static inline void touch_ll_enable_scan_mask(uint16_t chan_mask, bool enable)
+{
+    uint16_t mask = chan_mask & TOUCH_LL_FULL_CHANNEL_MASK;
+    uint16_t prev_mask = RTCCNTL.touch_scan_ctrl.touch_scan_pad_map;
+    if (enable) {
+        RTCCNTL.touch_scan_ctrl.touch_scan_pad_map = prev_mask | mask;
+    } else {
+        RTCCNTL.touch_scan_ctrl.touch_scan_pad_map = prev_mask & (~mask);
+    }
+}
+
+/**
+ * Set touch sensor threshold of charge cycles that triggers pad active state.
+ * The threshold determines the sensitivity of the touch sensor.
+ * The threshold is the original value of the trigger state minus the benchmark value.
+ *
+ * @note  If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered.
+ * @param touch_num The touch pad id
+ * @param thresh    The threshold of charge cycles
+ */
+static inline void touch_ll_set_chan_active_threshold(uint32_t touch_num, uint32_t thresh)
+{
+    HAL_ASSERT(touch_num > 0);
+    SENS.touch_thresh[touch_num - 1].thresh = thresh;
+}
+
+/**
+ * Set the power on wait cycle
+ *
+ * @param wait_cycles
+ */
+static inline void touch_ll_set_power_on_wait_cycle(uint32_t wait_cycles)
+{
+    //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl2, touch_xpd_wait, wait_cycles); //wait volt stable
+}
+
+/**
+ * Set touch sensor touch sensor charge and discharge times of every measurement on a pad.
+ *
+ * @param charge_times The times of charge and discharge in each measure process of touch channels.
+ *                     The timer frequency is RTC_FAST (about 16M). Range: 0 ~ 0xffff.
+ */
+static inline void touch_ll_set_charge_times( uint16_t charge_times)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num, charge_times);
+}
+
+/**
+ * Set touch sensor sleep time.
+ *
+ * @param interval_ticks    The touch sensor will sleep for some cycles after each measurement.
+ *                          interval_ticks decide the interval between each measurement.
+ *                          t_sleep = interval_ticks / (RTC_SLOW_CLK frequency).
+ *                          The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ */
+static inline void touch_ll_set_measure_interval_ticks(uint16_t interval_ticks)
+{
+    // touch sensor sleep cycle Time = interval_ticks / RTC_SLOW_CLK
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles, interval_ticks);
+}
+
+/**
+ * Set the Touch pad charge speed.
+ *
+ * @param touch_num     Touch channel number
+ * @param charge_speed  Charge speed of this touch channel
+ */
+static inline void touch_ll_set_charge_speed(uint32_t touch_num, touch_charge_speed_t charge_speed)
+{
+    RTCIO.touch_pad[touch_num].dac = charge_speed;
+}
+
+/**
+ * Set the upper limitation of the touch channel voltage while charging
+ *
+ * @param high_lim      The high(upper) limitation of charge
+ */
+static inline void touch_ll_set_charge_voltage_high_limit(touch_volt_lim_h_t high_lim)
+{
+    RTCCNTL.touch_ctrl2.touch_drefh = (uint32_t)high_lim & 0x3;
+    RTCCNTL.touch_ctrl2.touch_drange = (uint32_t)high_lim >> 2;
+}
+
+/**
+ * Set the lower limitation of the touch channel voltage while discharging
+ *
+ * @param low_lim      The lower limitation of discharge
+ */
+static inline void touch_ll_set_charge_voltage_low_limit(touch_volt_lim_l_t low_lim)
+{
+    RTCCNTL.touch_ctrl2.touch_drefl = low_lim;
+}
+
+/**
+ * Set the initial charge voltage of touch channel
+ * i.e., the touch pad measurement start from a low voltage or a high voltage
+ *
+ * @param touch_num         Touch channel number
+ * @param init_charge_volt  The initial charge voltage
+ */
+static inline void touch_ll_set_init_charge_voltage(uint32_t touch_num, touch_init_charge_volt_t init_charge_volt)
+{
+    RTCIO.touch_pad[touch_num].tie_opt = init_charge_volt;
+}
+
+/**
+ * Set the connection of the idle channel
+ * The idle channel is the channel that is enabled and powered on but not under measurement.
+ *
+ * @param idle_conn
+ */
+static inline void touch_ll_set_idle_channel_connection(touch_idle_conn_t idle_conn)
+{
+    RTCCNTL.touch_scan_ctrl.touch_inactive_connection = idle_conn;
+}
+
+/**
+ * Enable touch sensor channel. Register touch channel into touch sensor measurement group.
+ * The working mode of the touch sensor is simultaneous measurement.
+ * This function will set the measure bits according to the given bitmask.
+ *
+ * @note  If set this mask, the FSM timer should be stop firstly.
+ * @note  The touch sensor that in scan map, should be deinit GPIO function firstly.
+ * @param enable_mask bitmask of touch sensor scan group.
+ *        e.g. TOUCH_PAD_NUM1 -> BIT(1)
+ * @return
+ *      - ESP_OK on success
+ */
+static inline void touch_ll_enable_channel_mask(uint16_t enable_mask)
+{
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  = enable_mask;
+    SENS.sar_touch_conf.touch_outen = enable_mask;
+}
+
+/**
+ * Set the timeout to enable or disable the check for all touch sensor channels measurements.
+ * When the touch reading of a touch channel exceeds the measurement threshold,
+ * If enable: a timeout interrupt will be generated and it will go to the next channel measurement.
+ * If disable: the FSM is always on the channel, until the measurement of this channel is over.
+ *
+ * @param timeout_cycles The maximum time cycles of the measurement on one channel.
+ *                       Set to 0 to disable the timeout.
+ *                       Set to non-zero to enable the timeout and set the timeout cycles.
+ */
+static inline void touch_ll_set_timeout(uint32_t timeout_cycles)
+{
+    if (timeout_cycles) {
+        RTCCNTL.touch_timeout_ctrl.touch_timeout_num = timeout_cycles;
+        RTCCNTL.touch_timeout_ctrl.touch_timeout_en = 1;
+    } else {
+        RTCCNTL.touch_timeout_ctrl.touch_timeout_en = 0;
+    }
+}
+
+/**
+ * Clear all touch sensor channels active status.
+ *
+ * @note Generally no manual removal is required.
+ */
+static inline void touch_ll_clear_active_channel_status(void)
+{
+    SENS.sar_touch_conf.touch_status_clr = 1;
+}
+
+/**
+ * Select touch sensor dbias to save power in sleep mode.
+ *
+ * @note If change the dbias, the reading of touch sensor will changed. Users should make sure the threshold.
+ */
+static inline void touch_ll_set_bias_type(touch_bias_type_t bias_type)
+{
+    RTCCNTL.touch_ctrl2.touch_dbias = bias_type;
+}
+
+/********************************* FSM Operation ******************************/
+/**
+ * Touch timer trigger measurement and always wait measurement done.
+ * Force done for touch timer ensures that the timer always can get the measurement done signal.
+ * @note The `force done` signal should last as least one slow clock tick
+ */
+__attribute__((always_inline))
+static inline void touch_ll_force_done_curr_measurement(void)
+{
+    RTCCNTL.touch_ctrl2.touch_timer_force_done = TOUCH_LL_TIMER_FORCE_DONE;
+    RTCCNTL.touch_ctrl2.touch_timer_force_done = TOUCH_LL_TIMER_DONE;
+}
+
+/**
+ * Enable touch sensor FSM timer trigger (continuous) mode or software trigger (oneshot) mode.
+ *
+ * @param enable Enable FSM timer mode.
+ *        True: the FSM will trigger scanning repeatedly under the control of the hardware timer (continuous mode)
+ *        False: the FSM will trigger scanning once under the control of the software (continuous mode)
+ */
+__attribute__((always_inline))
+static inline void touch_ll_enable_fsm_timer(bool enable)
+{
+    touch_ll_force_done_curr_measurement();
+    // Set 0 to start by timer, otherwise by software
+    RTCCNTL.touch_ctrl2.touch_start_force = !enable;
+}
+
+/**
+ * Start touch sensor FSM timer to run FSM repeatedly
+ * The measurement action can be triggered by the hardware timer, as well as by the software instruction.
+ * @note
+ *      The timer should be triggered
+ */
+__attribute__((always_inline))
+static inline void touch_ll_start_fsm_repeated_timer(void)
+{
+    /**
+     * Touch timer trigger measurement and always wait measurement done.
+     * Force done for touch timer ensures that the timer always can get the measurement done signal.
+     */
+    touch_ll_force_done_curr_measurement();
+    RTCCNTL.touch_ctrl2.touch_slp_timer_en = 1;
+}
+
+/**
+ * Stop touch sensor FSM timer.
+ *        The measurement action can be triggered by the hardware timer, as well as by the software instruction.
+ */
+__attribute__((always_inline))
+static inline void touch_ll_stop_fsm_repeated_timer(void)
+{
+    RTCCNTL.touch_ctrl2.touch_slp_timer_en = 0;
+    touch_ll_force_done_curr_measurement();
+}
+
+/**
+ * Is the FSM repeated timer enabled.
+ * @note when the timer is enabled, RTC clock should not be power down
+ *
+ * @return
+ *      - true: enabled
+ *      - false: disabled
+ */
+__attribute__((always_inline))
+static inline bool touch_ll_is_fsm_repeated_timer_enabled(void)
+{
+    return (bool)RTCCNTL.touch_ctrl2.touch_slp_timer_en;
+}
+
+
+/**
+ * Enable the touch sensor FSM start signal from software
+ */
+__attribute__((always_inline))
+static inline void touch_ll_trigger_oneshot_measurement(void)
+{
+    RTCCNTL.touch_ctrl2.touch_start_en = 1;
+    RTCCNTL.touch_ctrl2.touch_start_en = 0;
+}
+
+/**
+ * @brief Power on the channel by mask
+ *
+ * @param chan_mask The channel mask that needs to power on
+ */
+__attribute__((always_inline))
+static inline void touch_ll_channel_sw_measure_mask(uint16_t chan_mask)
+{
+    (void) chan_mask;
+    // Only for compatibility
+}
+
+/****************************** Benchmark Operation ***************************/
+/**
+ * Force reset benchmark to raw data of touch sensor.
+ *
+ * @note If call this API, make sure enable clock gate(`touch_ll_clkgate`) first.
+ * @param chan_mask touch channel mask
+ */
+__attribute__((always_inline))
+static inline void touch_ll_reset_chan_benchmark(uint32_t chan_mask)
+{
+    SENS.sar_touch_chn_st.touch_channel_clr = chan_mask;
+}
+
+static inline void touch_ll_sleep_reset_benchmark(void)
+{
+    RTCCNTL.touch_approach.touch_slp_channel_clr = 1;
+}
+
+/************************************** Data **********************************/
+/**
+ * Get the data of the touch channel according to the types
+ *
+ * @param touch_num touch pad index
+ * @param type  data type
+ *              0/1: TOUCH_LL_READ_RAW, raw data of touch channel
+ *              2:   TOUCH_LL_READ_BENCHMARK, benchmark value of touch channel,
+ *                   the benchmark value is the maximum during the first measurement period
+ *              3:   TOUCH_LL_READ_SMOOTH, the smoothed data that obtained by filtering the raw data.
+ * @param data pointer to the data
+ */
+__attribute__((always_inline))
+static inline void touch_ll_read_chan_data(uint32_t touch_num, uint8_t type, uint32_t *data)
+{
+    HAL_ASSERT(type <= TOUCH_LL_READ_SMOOTH);
+    HAL_ASSERT(touch_num > 0);
+    SENS.sar_touch_conf.touch_data_sel = type;
+    *data = SENS.sar_touch_status[touch_num - 1].touch_pad_data;
+}
+
+/****************************** Filter Configuration **************************/
+
+/**
+ * Enable or disable touch sensor filter and detection algorithm.
+ * For more details on the detection algorithm, please refer to the application documentation.
+ */
+static inline void touch_ll_filter_enable(bool enable)
+{
+    RTCCNTL.touch_filter_ctrl.touch_filter_en = enable;
+}
+
+/**
+ * Set filter mode. The input of the filter is the raw value of touch reading,
+ * and the output of the filter is involved in the judgment of the touch state.
+ *
+ * @param mode Filter mode type. Refer to ``touch_benchmark_filter_mode_t``.
+ */
+static inline void touch_ll_filter_set_filter_mode(touch_benchmark_filter_mode_t mode)
+{
+    RTCCNTL.touch_filter_ctrl.touch_filter_mode = mode;
+}
+
+/**
+ * Set jitter filter step size.
+ * If filter mode is jitter, should set filter step for jitter.
+ * Range: 0 ~ 15
+ *
+ * @param step The step size of the data change.
+ */
+static inline void touch_ll_filter_set_jitter_step(uint32_t step)
+{
+    RTCCNTL.touch_filter_ctrl.touch_jitter_step = step;
+}
+
+/**
+ * Set the denoise coefficient regarding the denoise level.
+ *
+ * @param denoise_lvl   Range [0 ~ 4]. 0 = no noise resistance, otherwise higher denoise_lvl means more noise resistance.
+ *                      0 = no noise resistance
+ *                      1 = noise resistance is 1/4 benchmark
+ *                      2 = noise resistance is 3/8 benchmark
+ *                      3 = noise resistance is 1/2 benchmark
+ *                      4 = noise resistance is 1 benchmark
+ */
+static inline void touch_ll_filter_set_denoise_level(int denoise_lvl)
+{
+    HAL_ASSERT(denoise_lvl >= 0 && denoise_lvl <= 4);
+    bool always_update = denoise_lvl == 0;
+    /* Map denoise level to actual noise threshold coefficients
+       denoise_lvl=1 -> noise_thresh=2, 1/4 benchmark
+       denoise_lvl=2 -> noise_thresh=1, 3/8 benchmark
+       denoise_lvl=3 -> noise_thresh=0, 1/2 benchmark
+       denoise_lvl=4 -> noise_thresh=3, 1   benchmark */
+    uint32_t noise_thresh = denoise_lvl == 4 ? 3 : 3 - denoise_lvl;
+
+    RTCCNTL.touch_filter_ctrl.touch_noise_thres = always_update ? 0 : noise_thresh;
+    RTCCNTL.touch_filter_ctrl.config2 = always_update ? 0 : noise_thresh;
+    RTCCNTL.touch_filter_ctrl.config1 = 0xF;
+}
+
+/**
+ * Set the hysteresis value of the active threshold
+ * While the touch data is greater than active_threshold + hysteresis and last for several ticks, the channel is activated,
+ * and while the touch data is smaller than active_threshold - hysteresis and last for several ticks, the channel is inactivated
+ *
+ * @param hysteresis The hysteresis value of active threshold
+ */
+static inline void touch_ll_filter_set_active_hysteresis(uint32_t hysteresis)
+{
+    RTCCNTL.touch_filter_ctrl.config3 = hysteresis;
+}
+
+/**
+ * Set filter mode. The input to the filter is raw data and the output is the smooth data.
+ * The smooth data is used to determine the touch status.
+ *
+ * @param mode Filter mode type. Refer to ``touch_smooth_filter_mode_t``.
+ */
+static inline void touch_ll_filter_set_smooth_mode(touch_smooth_filter_mode_t mode)
+{
+    RTCCNTL.touch_filter_ctrl.touch_smooth_lvl = mode;
+}
+
+/**
+ * Set debounce count, such as `n`. If the measured values continue to exceed
+ * the threshold for `n+1` times, it is determined that the touch sensor state changes.
+ *
+ * @param dbc_cnt Debounce count value.
+ */
+static inline void touch_ll_filter_set_debounce(uint32_t dbc_cnt)
+{
+    RTCCNTL.touch_filter_ctrl.touch_debounce = dbc_cnt;
+}
+
+/**************************** Sleep Configurations ****************************/
+/**
+ * Set the trigger threshold of touch sensor in deep sleep.
+ * The threshold determines the sensitivity of the touch sensor.
+ * The threshold is the original value of the trigger state minus the benchmark value.
+ *
+ * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
+ */
+static inline void touch_ll_sleep_set_threshold(uint32_t touch_thres)
+{
+    RTCCNTL.touch_slp_thres.touch_slp_th = touch_thres;
+}
+
+/**
+ * Set touch channel number for sleep channel.
+ *
+ * @note Only one touch sensor channel is supported in deep sleep mode.
+ * @param touch_num Touch sensor channel number.
+ */
+static inline void touch_ll_sleep_set_channel_num(uint32_t touch_num)
+{
+    RTCCNTL.touch_slp_thres.touch_slp_pad = touch_num;
+}
+
+/**
+ * Enable proximity sensing function for sleep channel.
+ */
+static inline void touch_ll_sleep_enable_proximity_sensing(bool enable)
+{
+    RTCCNTL.touch_slp_thres.touch_slp_approach_en = enable;
+}
+
+/************************* Waterproof Configurations **************************/
+/**
+ * Enable parameter of waterproof function.
+ *
+ * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel.
+ * Guard pad is used to detect the large area of water covering the touch panel.
+ * Shield pad is used to shield the influence of water droplets covering the touch panel.
+ * It is generally designed as a grid and is placed around the touch buttons.
+ * @param enable Enable or disable waterproof function.
+ */
+static inline void touch_ll_waterproof_enable(bool enable)
+{
+    RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = enable;
+}
+
+/**
+ * Set touch channel use for guard channel.
+ *
+ * @param pad_num Touch sensor channel number.
+ */
+static inline void touch_ll_waterproof_set_guard_chan(uint32_t pad_num)
+{
+    RTCCNTL.touch_scan_ctrl.touch_out_ring = pad_num;
+}
+
+/**
+ * Set max equivalent capacitance for shield channel.
+ * The equivalent capacitance of the shielded channel can be calculated
+ * from the reading of denoise channel.
+ *
+ * @param pad_num Touch sensor channel number. Refer to ``touch_chan_shield_cap_t``
+ */
+static inline void touch_ll_waterproof_set_shield_driver(touch_chan_shield_cap_t driver_level)
+{
+    RTCCNTL.touch_scan_ctrl.touch_bufdrv = driver_level;
+}
+
+/****************************** Proximity Sensing *****************************/
+/**
+ * Set the proximity sensing channel to the specific touch channel
+ * To disable the proximity channel, point this pad to `TOUCH_LL_NULL_CHANNEL`
+ *
+ * @param prox_chan  proximity sensing channel.
+ * @param touch_num  The touch channel that supposed to be used as proximity sensing channel
+ */
+static inline void touch_ll_set_proximity_sensing_channel(uint8_t prox_chan, uint32_t touch_num)
+{
+    switch (prox_chan) {
+        case 0:
+            SENS.sar_touch_conf.touch_approach_pad0 = touch_num;
+            break;
+        case 1:
+            SENS.sar_touch_conf.touch_approach_pad1 = touch_num;
+            break;
+        case 2:
+            SENS.sar_touch_conf.touch_approach_pad2 = touch_num;
+            break;
+        default:
+            // invalid proximity channel
+            abort();
+    }
+}
+
+/**
+ * Set the total scan times of the proximity sensing channel.
+ *
+ * @param scan_times The total scan times of the proximity sensing channel
+ */
+static inline void touch_ll_proximity_set_total_scan_times(uint32_t scan_times)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time, scan_times);
+}
+
+/**
+ * Get the total scan times of the proximity sensing channel.
+ *
+ * @return
+ *      - The total scan times of the proximity sensing channel
+ */
+__attribute__((always_inline))
+static inline uint32_t touch_ll_proximity_get_total_scan_times(void)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time);
+}
+
+/**
+ * Get the current scan count for proximity channel.
+ *
+ * @param touch_num Touch channel number.
+ * @return
+ *      - Current scan count for proximity channel
+ */
+__attribute__((always_inline))
+static inline uint32_t touch_ll_proximity_get_curr_scan_cnt(uint32_t touch_num)
+{
+    if (SENS.sar_touch_conf.touch_approach_pad0 == touch_num) {
+        return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad0_cnt);
+    } else if (SENS.sar_touch_conf.touch_approach_pad1 == touch_num) {
+        return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad1_cnt);
+    } else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) {
+        return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad2_cnt);
+    }
+    return 0;
+}
+
+/******************************* Denoise Channel ******************************/
+/**
+ * Enable denoise function.
+ * T0 is an internal channel that does not have a corresponding external GPIO.
+ * T0 will work simultaneously with the measured channel Tn. Finally, the actual
+ * measured value of Tn is the value after subtracting lower bits of T0.
+ * This denoise function filters out interference introduced on all channels,
+ * such as noise introduced by the power supply and external EMI.
+ * @param enable  enable the denoise channel
+ */
+static inline void touch_ll_denoise_enable(bool enable)
+{
+    RTCCNTL.touch_scan_ctrl.touch_denoise_en = enable;
+}
+
+/**
+ * Set internal reference capacitance of denoise channel.
+ * Select the appropriate internal reference capacitance value so that
+ * the reading of denoise channel is closest to the reading of the channel being measured.
+ *
+ * @param capacitance   Reference capacitance level.
+ */
+static inline void touch_ll_denoise_set_reference_cap(touch_denoise_chan_cap_t capacitance)
+{
+    RTCCNTL.touch_ctrl2.touch_refc = capacitance;
+}
+
+/**
+ * Set denoise resolution of denoise channel.
+ * Determined by measuring the noise amplitude of the denoise channel.
+ *
+ * @param resolution Denoise resolution of denoise channel.
+ */
+static inline void touch_ll_denoise_set_resolution(touch_denoise_chan_resolution_t resolution)
+{
+    RTCCNTL.touch_scan_ctrl.touch_denoise_res = resolution;
+}
+
+/**
+ * Read denoise measure value (TOUCH_PAD_NUM0).
+ *
+ * @param denoise value of denoise.
+ */
+static inline void touch_ll_denoise_read_data(uint32_t *data)
+{
+    *data =  SENS.sar_touch_status0.touch_denoise_data;
+}
 
+/******************************************************************************/
+/*                   Legacy APIs (to be removed in esp-idf v6.0)              */
+/******************************************************************************/
+#include "hal/touch_sensor_legacy_types.h"
 /**
  * Set touch sensor touch sensor times of charge and discharge.
  *
@@ -85,11 +813,11 @@ static inline void touch_ll_get_sleep_time(uint16_t *sleep_time)
 }
 
 /**
- * Set touch sensor high voltage threshold of chanrge.
+ * Set touch sensor high voltage threshold of charge.
  * The touch sensor measures the channel capacitance value by charging and discharging the channel.
  * So the high threshold should be less than the supply voltage.
  *
- * @param refh The high voltage threshold of chanrge.
+ * @param refh The high voltage threshold of charge.
  */
 static inline void touch_ll_set_voltage_high(touch_high_volt_t refh)
 {
@@ -97,11 +825,11 @@ static inline void touch_ll_set_voltage_high(touch_high_volt_t refh)
 }
 
 /**
- * Get touch sensor high voltage threshold of chanrge.
+ * Get touch sensor high voltage threshold of charge.
  * The touch sensor measures the channel capacitance value by charging and discharging the channel.
  * So the high threshold should be less than the supply voltage.
  *
- * @param refh The high voltage threshold of chanrge.
+ * @param refh The high voltage threshold of charge.
  */
 static inline void touch_ll_get_voltage_high(touch_high_volt_t *refh)
 {
@@ -131,11 +859,11 @@ static inline void touch_ll_get_voltage_low(touch_low_volt_t *refl)
 }
 
 /**
- * Set touch sensor high voltage attenuation of chanrge. The actual charge threshold is high voltage threshold minus attenuation value.
+ * Set touch sensor high voltage attenuation of charge. The actual charge threshold is high voltage threshold minus attenuation value.
  * The touch sensor measures the channel capacitance value by charging and discharging the channel.
  * So the high threshold should be less than the supply voltage.
  *
- * @param refh The high voltage threshold of chanrge.
+ * @param refh The high voltage threshold of charge.
  */
 static inline void touch_ll_set_voltage_attenuation(touch_volt_atten_t atten)
 {
@@ -143,11 +871,11 @@ static inline void touch_ll_set_voltage_attenuation(touch_volt_atten_t atten)
 }
 
 /**
- * Get touch sensor high voltage attenuation of chanrge. The actual charge threshold is high voltage threshold minus attenuation value.
+ * Get touch sensor high voltage attenuation of charge. The actual charge threshold is high voltage threshold minus attenuation value.
  * The touch sensor measures the channel capacitance value by charging and discharging the channel.
  * So the high threshold should be less than the supply voltage.
  *
- * @param refh The high voltage threshold of chanrge.
+ * @param refh The high voltage threshold of charge.
  */
 static inline void touch_ll_get_voltage_attenuation(touch_volt_atten_t *atten)
 {
@@ -412,20 +1140,6 @@ static inline uint32_t IRAM_ATTR touch_ll_read_raw_data(touch_pad_t touch_num)
     return SENS.sar_touch_status[touch_num - 1].touch_pad_data;
 }
 
-/**
- * Get touch sensor measure status. No block.
- *
- * @return
- *      - If touch sensors measure done.
- */
-__attribute__((always_inline))
-static inline bool touch_ll_is_measure_done(void)
-{
-    return (bool)SENS.sar_touch_chn_st.touch_meas_done;
-}
-
-/************************* esp32s2 only *************************/
-
 /**
  * Reset the whole of touch module.
  *
@@ -468,17 +1182,6 @@ static inline void touch_ll_get_idle_channel_connect(touch_pad_conn_type_t *type
     *type = (touch_pad_conn_type_t)(RTCCNTL.touch_scan_ctrl.touch_inactive_connection);
 }
 
-/**
- * Get the current measure channel. Touch sensor measurement is cyclic scan mode.
- *
- * @return
- *      - touch channel number
- */
-static inline touch_pad_t IRAM_ATTR touch_ll_get_current_meas_channel(void)
-{
-    return (touch_pad_t)(SENS.sar_touch_status0.touch_scan_curr);
-}
-
 /**
  * Enable touch sensor interrupt by bitmask.
  *
@@ -673,17 +1376,6 @@ static inline void touch_ll_reset_benchmark(touch_pad_t touch_num)
     }
 }
 
-/**
- * Set filter mode. The input of the filter is the raw value of touch reading,
- * and the output of the filter is involved in the judgment of the touch state.
- *
- * @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
- */
-static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
-{
-    RTCCNTL.touch_filter_ctrl.touch_filter_mode = mode;
-}
-
 /**
  * Get filter mode. The input of the filter is the raw value of touch reading,
  * and the output of the filter is involved in the judgment of the touch state.
@@ -695,17 +1387,6 @@ static inline void touch_ll_filter_get_filter_mode(touch_filter_mode_t *mode)
     *mode = (touch_filter_mode_t)RTCCNTL.touch_filter_ctrl.touch_filter_mode;
 }
 
-/**
- * Set filter mode. The input to the filter is raw data and the output is the smooth data.
- * The smooth data is used to determine the touch status.
- *
- * @param mode Filter mode type. Refer to `touch_smooth_mode_t`.
- */
-static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
-{
-    RTCCNTL.touch_filter_ctrl.touch_smooth_lvl = mode;
-}
-
 /**
  * Get filter mode. The smooth data is used to determine the touch status.
  *
@@ -716,17 +1397,6 @@ static inline void touch_ll_filter_get_smooth_mode(touch_smooth_mode_t *mode)
     *mode = (touch_smooth_mode_t)(RTCCNTL.touch_filter_ctrl.touch_smooth_lvl);
 }
 
-/**
- * Set debounce count, such as `n`. If the measured values continue to exceed
- * the threshold for `n+1` times, it is determined that the touch sensor state changes.
- *
- * @param dbc_cnt Debounce count value.
- */
-static inline void touch_ll_filter_set_debounce(uint32_t dbc_cnt)
-{
-    RTCCNTL.touch_filter_ctrl.touch_debounce = dbc_cnt;
-}
-
 /**
  * Get debounce count.
  *
@@ -764,18 +1434,6 @@ static inline void touch_ll_filter_get_noise_thres(uint32_t *noise_thr)
     *noise_thr = RTCCNTL.touch_filter_ctrl.touch_noise_thres;
 }
 
-/**
- * Set jitter filter step size.
- * If filter mode is jitter, should set filter step for jitter.
- * Range: 0 ~ 15
- *
- * @param step The step size of the data change.
- */
-static inline void touch_ll_filter_set_jitter_step(uint32_t step)
-{
-    RTCCNTL.touch_filter_ctrl.touch_jitter_step = step;
-}
-
 /**
  * Get jitter filter step size.
  * If filter mode is jitter, should set filter step for jitter.
@@ -788,52 +1446,8 @@ static inline void touch_ll_filter_get_jitter_step(uint32_t *step)
     *step = RTCCNTL.touch_filter_ctrl.touch_jitter_step;
 }
 
-/**
- * Enable touch sensor filter and detection algorithm.
- * For more details on the detection algorithm, please refer to the application documentation.
- */
-static inline void touch_ll_filter_enable(void)
-{
-    RTCCNTL.touch_filter_ctrl.touch_filter_en = 1;
-}
-
-/**
- * Disable touch sensor filter and detection algorithm.
- * For more details on the detection algorithm, please refer to the application documentation.
- */
-static inline void touch_ll_filter_disable(void)
-{
-    RTCCNTL.touch_filter_ctrl.touch_filter_en = 0;
-}
-
 /************************ Denoise register setting ************************/
 
-/**
- * Enable denoise function.
- * T0 is an internal channel that does not have a corresponding external GPIO.
- * T0 will work simultaneously with the measured channel Tn. Finally, the actual
- * measured value of Tn is the value after subtracting lower bits of T0.
- * This denoise function filters out interference introduced on all channels,
- * such as noise introduced by the power supply and external EMI.
- */
-static inline void touch_ll_denoise_enable(void)
-{
-    RTCCNTL.touch_scan_ctrl.touch_denoise_en = 1;
-}
-
-/**
- * Enable denoise function.
- * T0 is an internal channel that does not have a corresponding external GPIO.
- * T0 will work simultaneously with the measured channel Tn. Finally, the actual
- * measured value of Tn is the value after subtracting lower bits of T0.
- * This denoise function filters out interference introduced on all channels,
- * such as noise introduced by the power supply and external EMI.
- */
-static inline void touch_ll_denoise_disable(void)
-{
-    RTCCNTL.touch_scan_ctrl.touch_denoise_en = 0;
-}
-
 /**
  * Set internal reference capacitance of denoise channel.
  * Select the appropriate internal reference capacitance value so that
@@ -880,16 +1494,6 @@ static inline void touch_ll_denoise_get_grade(touch_pad_denoise_grade_t *grade)
     *grade = (touch_pad_denoise_grade_t)(RTCCNTL.touch_scan_ctrl.touch_denoise_res);
 }
 
-/**
- * Read denoise measure value (TOUCH_PAD_NUM0).
- *
- * @param denoise value of denoise.
- */
-static inline void touch_ll_denoise_read_data(uint32_t *data)
-{
-    *data = SENS.sar_touch_status0.touch_denoise_data;
-}
-
 /************************ Waterproof register setting ************************/
 
 /**
@@ -912,18 +1516,6 @@ static inline void touch_ll_waterproof_get_guard_pad(touch_pad_t *pad_num)
     *pad_num = (touch_pad_t)(RTCCNTL.touch_scan_ctrl.touch_out_ring);
 }
 
-/**
- * Set max equivalent capacitance for shield channel.
- * The equivalent capacitance of the shielded channel can be calculated
- * from the reading of denoise channel.
- *
- * @param pad_num Touch sensor channel number.
- */
-static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver_t driver_level)
-{
-    RTCCNTL.touch_scan_ctrl.touch_bufdrv = driver_level;
-}
-
 /**
  * Get max equivalent capacitance for shield channel.
  * The equivalent capacitance of the shielded channel can be calculated
@@ -931,32 +1523,11 @@ static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver
  *
  * @param pad_num Touch sensor channel number.
  */
-static inline void touch_ll_waterproof_get_sheild_driver(touch_pad_shield_driver_t *driver_level)
+static inline void touch_ll_waterproof_get_shield_driver(touch_pad_shield_driver_t *driver_level)
 {
     *driver_level = (touch_pad_shield_driver_t)(RTCCNTL.touch_scan_ctrl.touch_bufdrv);
 }
 
-/**
- * Enable parameter of waterproof function.
- *
- * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel.
- * Guard pad is used to detect the large area of water covering the touch panel.
- * Shield pad is used to shield the influence of water droplets covering the touch panel.
- * It is generally designed as a grid and is placed around the touch buttons.
- */
-static inline void touch_ll_waterproof_enable(void)
-{
-    RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 1;
-}
-
-/**
- * Disable parameter of waterproof function.
- */
-static inline void touch_ll_waterproof_disable(void)
-{
-    RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 0;
-}
-
 /************************ Proximity register setting ************************/
 
 /**
@@ -1038,18 +1609,6 @@ static inline bool touch_ll_proximity_pad_check(touch_pad_t touch_num)
 }
 
 /************** sleep pad setting ***********************/
-
-/**
- * Set touch channel number for sleep pad.
- *
- * @note Only one touch sensor channel is supported in deep sleep mode.
- * @param touch_num Touch sensor channel number.
- */
-static inline void touch_ll_sleep_set_channel_num(touch_pad_t touch_num)
-{
-    RTCCNTL.touch_slp_thres.touch_slp_pad = touch_num;
-}
-
 /**
  * Get touch channel number for sleep pad.
  *
@@ -1061,18 +1620,6 @@ static inline void touch_ll_sleep_get_channel_num(touch_pad_t *touch_num)
     *touch_num = (touch_pad_t)(RTCCNTL.touch_slp_thres.touch_slp_pad);
 }
 
-/**
- * Set the trigger threshold of touch sensor in deep sleep.
- * The threshold determines the sensitivity of the touch sensor.
- * The threshold is the original value of the trigger state minus the benchmark value.
- *
- * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
- */
-static inline void touch_ll_sleep_set_threshold(uint32_t touch_thres)
-{
-    RTCCNTL.touch_slp_thres.touch_slp_th = touch_thres;
-}
-
 /**
  * Get the trigger threshold of touch sensor in deep sleep.
  * The threshold determines the sensitivity of the touch sensor.
@@ -1085,22 +1632,6 @@ static inline void touch_ll_sleep_get_threshold(uint32_t *touch_thres)
     *touch_thres = RTCCNTL.touch_slp_thres.touch_slp_th;
 }
 
-/**
- * Enable proximity function for sleep pad.
- */
-static inline void touch_ll_sleep_enable_proximity_sensing(void)
-{
-    RTCCNTL.touch_slp_thres.touch_slp_approach_en = 1;
-}
-
-/**
- * Disable proximity function for sleep pad.
- */
-static inline void touch_ll_sleep_disable_proximity_sensing(void)
-{
-    RTCCNTL.touch_slp_thres.touch_slp_approach_en = 0;
-}
-
 /**
  * Get proximity function status for sleep pad.
  */
@@ -1134,11 +1665,6 @@ static inline void touch_ll_sleep_read_data(uint32_t *raw_data)
     *raw_data = SENS.sar_touch_status[touch_num - 1].touch_pad_data;
 }
 
-static inline void touch_ll_sleep_reset_benchmark(void)
-{
-    RTCCNTL.touch_approach.touch_slp_channel_clr = 1;
-}
-
 /**
  * Select touch sensor dbias to save power in sleep mode.
  *
diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h
index e044addcc76..a5aeeaa3166 100644
--- a/components/hal/esp32s2/include/hal/uart_ll.h
+++ b/components/hal/esp32s2/include/hal/uart_ll.h
@@ -573,8 +573,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
         hw->flow_conf.sw_flow_con_en = 1;
         hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
         hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -597,7 +597,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
@@ -797,7 +797,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
     *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, at_char_num);
 }
 
 /**
diff --git a/components/hal/esp32s2/include/hal/usb_dwc_ll.h b/components/hal/esp32s2/include/hal/usb_dwc_ll.h
new file mode 100644
index 00000000000..7426be2efa7
--- /dev/null
+++ b/components/hal/esp32s2/include/hal/usb_dwc_ll.h
@@ -0,0 +1,983 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/usb_dwc_struct.h"
+#include "soc/usb_dwc_cfg.h"
+#include "hal/usb_dwc_types.h"
+#include "hal/misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ----------------------------- Helper Macros ------------------------------ */
+
+// Get USB hardware instance
+#define USB_DWC_LL_GET_HW(num) (&USB_DWC)
+
+/* -----------------------------------------------------------------------------
+--------------------------------- DWC Constants --------------------------------
+----------------------------------------------------------------------------- */
+
+#define USB_DWC_QTD_LIST_MEM_ALIGN              512
+#define USB_DWC_FRAME_LIST_MEM_ALIGN            512     // The frame list needs to be 512 bytes aligned (contrary to the databook)
+
+/* -----------------------------------------------------------------------------
+------------------------------- Global Registers -------------------------------
+----------------------------------------------------------------------------- */
+
+/*
+ * Interrupt bit masks of the GINTSTS and GINTMSK registers
+ */
+#define USB_DWC_LL_INTR_CORE_WKUPINT        (1 << 31)
+#define USB_DWC_LL_INTR_CORE_SESSREQINT     (1 << 30)
+#define USB_DWC_LL_INTR_CORE_DISCONNINT     (1 << 29)
+#define USB_DWC_LL_INTR_CORE_CONIDSTSCHNG   (1 << 28)
+#define USB_DWC_LL_INTR_CORE_PTXFEMP        (1 << 26)
+#define USB_DWC_LL_INTR_CORE_HCHINT         (1 << 25)
+#define USB_DWC_LL_INTR_CORE_PRTINT         (1 << 24)
+#define USB_DWC_LL_INTR_CORE_RESETDET       (1 << 23)
+#define USB_DWC_LL_INTR_CORE_FETSUSP        (1 << 22)
+#define USB_DWC_LL_INTR_CORE_INCOMPIP       (1 << 21)
+#define USB_DWC_LL_INTR_CORE_INCOMPISOIN    (1 << 20)
+#define USB_DWC_LL_INTR_CORE_OEPINT         (1 << 19)
+#define USB_DWC_LL_INTR_CORE_IEPINT         (1 << 18)
+#define USB_DWC_LL_INTR_CORE_EPMIS          (1 << 17)
+#define USB_DWC_LL_INTR_CORE_EOPF           (1 << 15)
+#define USB_DWC_LL_INTR_CORE_ISOOUTDROP     (1 << 14)
+#define USB_DWC_LL_INTR_CORE_ENUMDONE       (1 << 13)
+#define USB_DWC_LL_INTR_CORE_USBRST         (1 << 12)
+#define USB_DWC_LL_INTR_CORE_USBSUSP        (1 << 11)
+#define USB_DWC_LL_INTR_CORE_ERLYSUSP       (1 << 10)
+#define USB_DWC_LL_INTR_CORE_GOUTNAKEFF     (1 << 7)
+#define USB_DWC_LL_INTR_CORE_GINNAKEFF      (1 << 6)
+#define USB_DWC_LL_INTR_CORE_NPTXFEMP       (1 << 5)
+#define USB_DWC_LL_INTR_CORE_RXFLVL         (1 << 4)
+#define USB_DWC_LL_INTR_CORE_SOF            (1 << 3)
+#define USB_DWC_LL_INTR_CORE_OTGINT         (1 << 2)
+#define USB_DWC_LL_INTR_CORE_MODEMIS        (1 << 1)
+#define USB_DWC_LL_INTR_CORE_CURMOD         (1 << 0)
+
+/*
+ * Bit mask of interrupt generating bits of the the HPRT register. These bits
+ * are ORd into the USB_DWC_LL_INTR_CORE_PRTINT interrupt.
+ *
+ * Note: Some fields of the HPRT are W1C (write 1 clear), this we cannot do a
+ * simple read and write-back to clear the HPRT interrupt bits. Instead we need
+ * a W1C mask the non-interrupt related bits
+ */
+#define USB_DWC_LL_HPRT_W1C_MSK             (0x2E)
+#define USB_DWC_LL_HPRT_ENA_MSK             (0x04)
+#define USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG (1 << 5)
+#define USB_DWC_LL_INTR_HPRT_PRTENCHNG      (1 << 3)
+#define USB_DWC_LL_INTR_HPRT_PRTCONNDET     (1 << 1)
+
+/*
+ * Bit mask of channel interrupts (HCINTi and HCINTMSKi registers)
+ *
+ * Note: Under Scatter/Gather DMA mode, only the following interrupts can be unmasked
+ * - DESC_LS_ROLL
+ * - XCS_XACT_ERR (always unmasked)
+ * - BNAINTR
+ * - CHHLTD
+ * - XFERCOMPL
+ * The remaining interrupt bits will still be set (when the corresponding event occurs)
+ * but will not generate an interrupt. Therefore we must proxy through the
+ * USB_DWC_LL_INTR_CHAN_CHHLTD interrupt to check the other interrupt bits.
+ */
+#define USB_DWC_LL_INTR_CHAN_DESC_LS_ROLL   (1 << 13)
+#define USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR   (1 << 12)
+#define USB_DWC_LL_INTR_CHAN_BNAINTR        (1 << 11)
+#define USB_DWC_LL_INTR_CHAN_DATATGLERR     (1 << 10)
+#define USB_DWC_LL_INTR_CHAN_FRMOVRUN       (1 << 9)
+#define USB_DWC_LL_INTR_CHAN_BBLEER         (1 << 8)
+#define USB_DWC_LL_INTR_CHAN_XACTERR        (1 << 7)
+#define USB_DWC_LL_INTR_CHAN_NYET           (1 << 6)
+#define USB_DWC_LL_INTR_CHAN_ACK            (1 << 5)
+#define USB_DWC_LL_INTR_CHAN_NAK            (1 << 4)
+#define USB_DWC_LL_INTR_CHAN_STALL          (1 << 3)
+#define USB_DWC_LL_INTR_CHAN_AHBERR         (1 << 2)
+#define USB_DWC_LL_INTR_CHAN_CHHLTD         (1 << 1)
+#define USB_DWC_LL_INTR_CHAN_XFERCOMPL      (1 << 0)
+
+/*
+ * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
+ * Each QTD describes one transfer. Scatter gather mode will automatically split
+ * a transfer into multiple MPS packets. Each QTD is 64bits in size
+ *
+ * Note: The status information part of the QTD is interpreted differently depending
+ * on IN or OUT, and ISO or non-ISO
+ */
+typedef struct {
+    union {
+        struct {
+            uint32_t xfer_size: 17;
+            uint32_t aqtd_offset: 6;
+            uint32_t aqtd_valid: 1;
+            uint32_t reserved_24: 1;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t rx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } in_non_iso;
+        struct {
+            uint32_t xfer_size: 12;
+            uint32_t reserved_12_24: 13;
+            uint32_t intr_cplt: 1;
+            uint32_t reserved_26_27: 2;
+            uint32_t rx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } in_iso;
+        struct {
+            uint32_t xfer_size: 17;
+            uint32_t reserved_17_23: 7;
+            uint32_t is_setup: 1;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t tx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } out_non_iso;
+        struct {
+            uint32_t xfer_size: 12;
+            uint32_t reserved_12_24: 13;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t tx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } out_iso;
+        uint32_t buffer_status_val;
+    };
+    uint8_t *buffer;
+} usb_dwc_ll_dma_qtd_t;
+
+
+/* -----------------------------------------------------------------------------
+------------------------------- Global Registers -------------------------------
+----------------------------------------------------------------------------- */
+
+// --------------------------- GAHBCFG Register --------------------------------
+
+static inline void usb_dwc_ll_gahbcfg_en_dma_mode(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.dmaen = 1;
+}
+
+static inline void usb_dwc_ll_gahbcfg_en_slave_mode(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.dmaen = 0;
+}
+
+static inline void usb_dwc_ll_gahbcfg_set_hbstlen(usb_dwc_dev_t *hw, uint32_t burst_len)
+{
+    hw->gahbcfg_reg.hbstlen = burst_len;
+}
+
+static inline void usb_dwc_ll_gahbcfg_en_global_intr(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.glbllntrmsk = 1;
+}
+
+static inline void usb_dwc_ll_gahbcfg_dis_global_intr(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.glbllntrmsk = 0;
+}
+
+// --------------------------- GUSBCFG Register --------------------------------
+
+static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.forcehstmode = 1;
+}
+
+static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.hnpcap = 0;
+}
+
+static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.srpcap = 0;
+}
+
+static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
+{
+    hw->gusbcfg_reg.toutcal = tout_cal;
+}
+
+static inline void usb_dwc_ll_gusbcfg_set_utmi_phy(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.phyif = 1;       // 16 bits interface
+    hw->gusbcfg_reg.ulpiutmisel = 0; // UTMI+
+    hw->gusbcfg_reg.physel = 0;      // HS PHY
+}
+
+// --------------------------- GRSTCTL Register --------------------------------
+
+static inline bool usb_dwc_ll_grstctl_is_ahb_idle(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.ahbidle;
+}
+
+static inline bool usb_dwc_ll_grstctl_is_dma_req_in_progress(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.dmareq;
+}
+
+static inline void usb_dwc_ll_grstctl_flush_nptx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.txfnum = 0;     //Set the TX FIFO number to 0 to select the non-periodic TX FIFO
+    hw->grstctl_reg.txfflsh = 1;    //Flush the selected TX FIFO
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.txfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_flush_ptx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.txfnum = 1;     //Set the TX FIFO number to 1 to select the periodic TX FIFO
+    hw->grstctl_reg.txfflsh = 1;    //FLush the select TX FIFO
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.txfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_flush_rx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.rxfflsh = 1;
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.rxfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.frmcntrrst = 1;
+}
+
+static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.csftrst = 1;
+}
+
+static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.csftrst;
+}
+
+// --------------------------- GINTSTS Register --------------------------------
+
+/**
+ * @brief Reads and clears the global interrupt register
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @return uint32_t Mask of interrupts
+ */
+static inline uint32_t usb_dwc_ll_gintsts_read_and_clear_intrs(usb_dwc_dev_t *hw)
+{
+    usb_dwc_gintsts_reg_t gintsts;
+    gintsts.val = hw->gintsts_reg.val;
+    hw->gintsts_reg.val = gintsts.val;  //Write back to clear
+    return gintsts.val;
+}
+
+/**
+ * @brief Clear specific interrupts
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @param intr_msk Mask of interrupts to clear
+ */
+static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t intr_msk)
+{
+    //All GINTSTS fields are either W1C or read only. So safe to write directly
+    hw->gintsts_reg.val = intr_msk;
+}
+
+// --------------------------- GINTMSK Register --------------------------------
+
+static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    hw->gintmsk_reg.val |= intr_mask;
+}
+
+static inline void usb_dwc_ll_gintmsk_dis_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    hw->gintmsk_reg.val &= ~intr_mask;
+}
+
+// --------------------------- GRXFSIZ Register --------------------------------
+
+static inline void usb_dwc_ll_grxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t num_lines)
+{
+    //Set size in words
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->grxfsiz_reg, rxfdep, num_lines);
+}
+
+// -------------------------- GNPTXFSIZ Register -------------------------------
+
+static inline void usb_dwc_ll_gnptxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
+{
+    usb_dwc_gnptxfsiz_reg_t gnptxfsiz;
+    gnptxfsiz.val = hw->gnptxfsiz_reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfstaddr, addr);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfdep, num_lines);
+    hw->gnptxfsiz_reg.val = gnptxfsiz.val;
+}
+
+// --------------------------- GSNPSID Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
+{
+    return hw->gsnpsid_reg.val;
+}
+
+// --------------------------- GHWCFGx Register --------------------------------
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.dfifodepth;
+}
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg2_reg.hsphytype;
+}
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg2_reg.numhstchnl;
+}
+
+// --------------------------- HPTXFSIZ Register -------------------------------
+
+static inline void usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
+{
+    usb_dwc_hptxfsiz_reg_t hptxfsiz;
+    hptxfsiz.val = hw->hptxfsiz_reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfstaddr, addr);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfsize, num_lines);
+    hw->hptxfsiz_reg.val = hptxfsiz.val;
+}
+
+/* -----------------------------------------------------------------------------
+-------------------------------- Host Registers --------------------------------
+----------------------------------------------------------------------------- */
+
+// ----------------------------- HCFG Register ---------------------------------
+
+static inline void usb_dwc_ll_hcfg_en_perio_sched(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.perschedena = 1;
+}
+
+static inline void usb_dwc_ll_hcfg_dis_perio_sched(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.perschedena = 0;
+}
+
+/**
+ * Sets the length of the frame list
+ *
+ * @param num_entires Number of entries in the frame list
+ */
+static inline void usb_dwc_ll_hcfg_set_num_frame_list_entries(usb_dwc_dev_t *hw, usb_hal_frame_list_len_t num_entries)
+{
+    uint32_t frlisten;
+    switch (num_entries) {
+        case USB_HAL_FRAME_LIST_LEN_8:
+            frlisten = 0;
+            break;
+        case USB_HAL_FRAME_LIST_LEN_16:
+            frlisten = 1;
+            break;
+        case USB_HAL_FRAME_LIST_LEN_32:
+            frlisten = 2;
+            break;
+        default: //USB_HAL_FRAME_LIST_LEN_64
+            frlisten = 3;
+            break;
+    }
+    hw->hcfg_reg.frlisten = frlisten;
+}
+
+static inline void usb_dwc_ll_hcfg_en_scatt_gatt_dma(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.descdma = 1;
+}
+
+static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.fslssupp = 1;
+}
+
+/**
+ * @brief Set FSLS PHY clock
+ *
+ * @attention This function should only be called if FSLS PHY is selected
+ * @param[in] hw    Start address of the DWC_OTG registers
+ */
+static inline void usb_dwc_ll_hcfg_set_fsls_phy_clock(usb_dwc_dev_t *hw)
+{
+    /*
+    Indicate to the OTG core what speed the PHY clock is at
+    Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
+          so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
+    */
+    usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+    hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2;
+}
+
+// ----------------------------- HFIR Register ---------------------------------
+
+/**
+ * @brief Set Frame Interval
+ *
+ * @attention This function should only be called if FSLS PHY is selected
+ * @param[in] hw    Start address of the DWC_OTG registers
+ */
+static inline void usb_dwc_ll_hfir_set_frame_interval(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hfir_reg_t hfir;
+    hfir.val = hw->hfir_reg.val;
+    hfir.hfirrldctrl = 0;       // Disable dynamic loading
+    /*
+    Set frame interval to be equal to 1ms
+    Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
+          so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
+    */
+    usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+    hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000;
+    hw->hfir_reg.val = hfir.val;
+}
+
+// ----------------------------- HFNUM Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_hfnum_get_frame_time_rem(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hfnum_reg, frrem);
+}
+
+static inline uint32_t usb_dwc_ll_hfnum_get_frame_num(usb_dwc_dev_t *hw)
+{
+    return hw->hfnum_reg.frnum;
+}
+
+// ---------------------------- HPTXSTS Register -------------------------------
+
+static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_top(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxqtop);
+}
+
+static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_space_avail(usb_dwc_dev_t *hw)
+{
+    return hw->hptxsts_reg.ptxqspcavail;
+}
+
+static inline uint32_t usb_dwc_ll_ptxsts_get_ptxf_space_avail(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxfspcavail);
+}
+
+// ----------------------------- HAINT Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_haint_get_chan_intrs(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->haint_reg, haint);
+}
+
+// --------------------------- HAINTMSK Register -------------------------------
+
+static inline void usb_dwc_ll_haintmsk_en_chan_intr(usb_dwc_dev_t *hw, uint32_t mask)
+{
+
+    hw->haintmsk_reg.val |= mask;
+}
+
+static inline void usb_dwc_ll_haintmsk_dis_chan_intr(usb_dwc_dev_t *hw, uint32_t mask)
+{
+    hw->haintmsk_reg.val &= ~mask;
+}
+
+// --------------------------- HFLBAddr Register -------------------------------
+
+/**
+ * @brief Set the base address of the scheduling frame list
+ *
+ * @note For some reason, this address must be 512 bytes aligned or else a bunch of frames will not be scheduled when
+ *       the frame list rolls over. However, according to the databook, there is no mention of the HFLBAddr needing to
+ *       be aligned.
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @param addr Base address of the scheduling frame list
+ */
+static inline void usb_dwc_ll_hflbaddr_set_base_addr(usb_dwc_dev_t *hw, uint32_t addr)
+{
+    hw->hflbaddr_reg.hflbaddr = addr;
+}
+
+/**
+ * @brief Get the base address of the scheduling frame list
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @return uint32_t Base address of the scheduling frame list
+ */
+static inline uint32_t usb_dwc_ll_hflbaddr_get_base_addr(usb_dwc_dev_t *hw)
+{
+    return hw->hflbaddr_reg.hflbaddr;
+}
+
+// ----------------------------- HPRT Register ---------------------------------
+
+static inline usb_dwc_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw)
+{
+    return (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+}
+
+static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prttstctl;
+}
+
+static inline void usb_dwc_ll_hprt_set_test_ctl(usb_dwc_dev_t *hw, uint32_t test_mode)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prttstctl = test_mode;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_en_pwr(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtpwr = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_dis_pwr(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtpwr = 0;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline uint32_t usb_dwc_ll_hprt_get_pwr_line_status(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtlnsts;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_reset(usb_dwc_dev_t *hw, bool reset)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtrst = reset;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_reset(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtrst;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_suspend(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtsusp = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_suspend(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtsusp;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_resume(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtres = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_clr_port_resume(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtres = 0;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_resume(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtres;
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_overcur(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtovrcurract;
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_en(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtena;
+}
+
+static inline void usb_dwc_ll_hprt_port_dis(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtena = 1;        //W1C to disable
+    //we want to W1C ENA but not W1C the interrupt bits
+    hw->hprt_reg.val = hprt.val & ((~USB_DWC_LL_HPRT_W1C_MSK) | USB_DWC_LL_HPRT_ENA_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_conn_status(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtconnsts;
+}
+
+static inline uint32_t usb_dwc_ll_hprt_intr_read_and_clear(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    //We want to W1C the interrupt bits but not that ENA
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_ENA_MSK);
+    //Return only the interrupt bits
+    return (hprt.val & (USB_DWC_LL_HPRT_W1C_MSK & ~(USB_DWC_LL_HPRT_ENA_MSK)));
+}
+
+static inline void usb_dwc_ll_hprt_intr_clear(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hw->hprt_reg.val = ((hprt.val & ~USB_DWC_LL_HPRT_ENA_MSK) & ~USB_DWC_LL_HPRT_W1C_MSK) | intr_mask;
+}
+
+//Per Channel registers
+
+// --------------------------- HCCHARi Register --------------------------------
+
+static inline void usb_dwc_ll_hcchar_enable_chan(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.chena = 1;
+}
+
+static inline bool usb_dwc_ll_hcchar_chan_is_enabled(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    return chan->hcchar_reg.chena;
+}
+
+static inline void usb_dwc_ll_hcchar_disable_chan(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.chdis = 1;
+}
+
+static inline void usb_dwc_ll_hcchar_set_odd_frame(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.oddfrm = 1;
+}
+
+static inline void usb_dwc_ll_hcchar_set_even_frame(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.oddfrm = 0;
+}
+
+static inline void usb_dwc_ll_hcchar_set_dev_addr(volatile usb_dwc_host_chan_regs_t *chan, uint32_t addr)
+{
+    chan->hcchar_reg.devaddr = addr;
+}
+
+static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_dwc_xfer_type_t type)
+{
+    chan->hcchar_reg.eptype = (uint32_t)type;
+}
+
+//Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause
+//each packet to be preceded by a PREamble packet
+static inline void usb_dwc_ll_hcchar_set_lspddev(volatile usb_dwc_host_chan_regs_t *chan, bool is_ls)
+{
+    chan->hcchar_reg.lspddev = is_ls;
+}
+
+static inline void usb_dwc_ll_hcchar_set_dir(volatile usb_dwc_host_chan_regs_t *chan, bool is_in)
+{
+    chan->hcchar_reg.epdir = is_in;
+}
+
+static inline void usb_dwc_ll_hcchar_set_ep_num(volatile usb_dwc_host_chan_regs_t *chan, uint32_t num)
+{
+    chan->hcchar_reg.epnum = num;
+}
+
+static inline void usb_dwc_ll_hcchar_set_mps(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mps)
+{
+    chan->hcchar_reg.mps = mps;
+}
+
+static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_dwc_xfer_type_t type, bool is_in, bool is_ls)
+{
+    //Sets all persistent fields of the channel over its lifetimez
+    usb_dwc_ll_hcchar_set_dev_addr(chan, dev_addr);
+    usb_dwc_ll_hcchar_set_ep_type(chan, type);
+    usb_dwc_ll_hcchar_set_lspddev(chan, is_ls);
+    usb_dwc_ll_hcchar_set_dir(chan, is_in);
+    usb_dwc_ll_hcchar_set_ep_num(chan, ep_num);
+    usb_dwc_ll_hcchar_set_mps(chan, mps);
+}
+
+// ---------------------------- HCINTi Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_hcint_read_and_clear_intrs(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    usb_dwc_hcint_reg_t hcint;
+    hcint.val = chan->hcint_reg.val;
+    chan->hcint_reg.val = hcint.val;
+    return hcint.val;
+}
+
+// --------------------------- HCINTMSKi Register ------------------------------
+
+static inline void usb_dwc_ll_hcintmsk_set_intr_mask(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mask)
+{
+    chan->hcintmsk_reg.val = mask;
+}
+
+// ---------------------------- HCTSIZi Register -------------------------------
+
+static inline void usb_dwc_ll_hctsiz_set_pid(volatile usb_dwc_host_chan_regs_t *chan, uint32_t data_pid)
+{
+    if (data_pid == 0) {
+        chan->hctsiz_reg.pid = 0;
+    } else {
+        chan->hctsiz_reg.pid = 2;
+    }
+}
+
+static inline uint32_t usb_dwc_ll_hctsiz_get_pid(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    if (chan->hctsiz_reg.pid == 0) {
+        return 0;   //DATA0
+    } else {
+        return 1;   //DATA1
+    }
+}
+
+static inline void usb_dwc_ll_hctsiz_set_qtd_list_len(volatile usb_dwc_host_chan_regs_t *chan, int qtd_list_len)
+{
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    //Set the length of the descriptor list. NTD occupies xfersize[15:8]
+    hctsiz.xfersize &= ~(0xFF << 8);
+    hctsiz.xfersize |= ((qtd_list_len - 1) & 0xFF) << 8;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    hctsiz.dopng = 0;         //Don't do ping
+    /*
+    Set SCHED_INFO which occupies xfersize[7:0]
+    It is always set to 0xFF for full speed and not used in Bulk/Ctrl channels
+    */
+    hctsiz.xfersize |= 0xFF;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+static inline void usb_dwc_ll_hctsiz_set_sched_info(volatile usb_dwc_host_chan_regs_t *chan, int tokens_per_frame, int offset)
+{
+    // @see USB-OTG databook: Table 5-47
+    // This function is relevant only for HS
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    uint8_t sched_info_val;
+    switch (tokens_per_frame) {
+        case 1:
+            offset %= 8; // If the required offset > 8, we must wrap around to SCHED_INFO size = 8
+            sched_info_val = 0b00000001;
+            break;
+        case 2:
+            offset %= 4;
+            sched_info_val = 0b00010001;
+            break;
+        case 4:
+            offset %= 2;
+            sched_info_val = 0b01010101;
+            break;
+        case 8:
+            offset = 0;
+            sched_info_val = 0b11111111;
+            break;
+        default:
+            abort();
+            break;
+    }
+    sched_info_val <<= offset;
+    hctsiz.xfersize &= ~(0xFF);
+    hctsiz.xfersize |= sched_info_val;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+// ---------------------------- HCDMAi Register --------------------------------
+
+static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx)
+{
+    usb_dwc_hcdma_reg_t hcdma;
+    /*
+    Set the base address portion of the field which is dmaaddr[31:9]. This is
+    the based address of the QTD list and must be 512 bytes aligned
+    */
+    hcdma.dmaaddr = ((uint32_t)dmaaddr) & 0xFFFFFE00;
+    //Set the current QTD index in the QTD list which is dmaaddr[8:3]
+    hcdma.dmaaddr |= (qtd_idx & 0x3F) << 3;
+    //dmaaddr[2:0] is reserved thus doesn't not need to be set
+
+    chan->hcdma_reg.val = hcdma.val;
+}
+
+static inline int usb_dwc_ll_hcdam_get_cur_qtd_idx(usb_dwc_host_chan_regs_t *chan)
+{
+    //The current QTD index is dmaaddr[8:3]
+    return (chan->hcdma_reg.dmaaddr >> 3) & 0x3F;
+}
+
+// ---------------------------- HCDMABi Register -------------------------------
+
+static inline void *usb_dwc_ll_hcdmab_get_buff_addr(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    return (void *)chan->hcdmab_reg.hcdmab;
+}
+
+/* -----------------------------------------------------------------------------
+---------------------------- Scatter/Gather DMA QTDs ---------------------------
+----------------------------------------------------------------------------- */
+
+// ---------------------------- Helper Functions -------------------------------
+
+/**
+ * @brief Get the base address of a channel's register based on the channel's index
+ *
+ * @param dev Start address of the DWC_OTG registers
+ * @param chan_idx The channel's index
+ * @return usb_dwc_host_chan_regs_t* Pointer to channel's registers
+ */
+static inline usb_dwc_host_chan_regs_t *usb_dwc_ll_chan_get_regs(usb_dwc_dev_t *dev, int chan_idx)
+{
+    return &dev->host_chans[chan_idx];
+}
+
+// ------------------------------ QTD related ----------------------------------
+
+#define USB_DWC_LL_QTD_STATUS_SUCCESS      0x0     //If QTD was processed, it indicates the data was transmitted/received successfully
+#define USB_DWC_LL_QTD_STATUS_PKTERR       0x1     //Data transmitted/received with errors (CRC/Timeout/Stuff/False EOP/Excessive NAK).
+//Note: 0x2 is reserved
+#define USB_DWC_LL_QTD_STATUS_BUFFER       0x3     //AHB error occurred.
+#define USB_DWC_LL_QTD_STATUS_NOT_EXECUTED 0x4     //QTD as never processed
+
+/**
+ * @brief Set a QTD for a non isochronous IN transfer
+ *
+ * @param qtd Pointer to the QTD
+ * @param data_buff Pointer to buffer containing the data to transfer
+ * @param xfer_len Number of bytes in transfer. Setting 0 will do a zero length IN transfer.
+ *                 Non zero length must be multiple of the endpoint's MPS.
+ * @param hoc Halt on complete (will generate an interrupt and halt the channel)
+ */
+static inline void usb_dwc_ll_qtd_set_in(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc)
+{
+    qtd->buffer = data_buff;        //Set pointer to data buffer
+    qtd->buffer_status_val = 0;     //Reset all flags to zero
+    qtd->in_non_iso.xfer_size = xfer_len;
+    if (hoc) {
+        qtd->in_non_iso.intr_cplt = 1;  //We need to set this to distinguish between a halt due to a QTD
+        qtd->in_non_iso.eol = 1;        //Used to halt the channel at this qtd
+    }
+    qtd->in_non_iso.active = 1;
+}
+
+/**
+ * @brief Set a QTD for a non isochronous OUT transfer
+ *
+ * @param qtd Pointer to the QTD
+ * @param data_buff Pointer to buffer containing the data to transfer
+ * @param xfer_len Number of bytes to transfer. Setting 0 will do a zero length transfer.
+ *                 For ctrl setup packets, this should be set to 8.
+ * @param hoc Halt on complete (will generate an interrupt)
+ * @param is_setup Indicates whether this is a control transfer setup packet or a normal OUT Data transfer.
+ *                 (As per the USB protocol, setup packets cannot be STALLd or NAKd by the device)
+ */
+static inline void usb_dwc_ll_qtd_set_out(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc, bool is_setup)
+{
+    qtd->buffer = data_buff;        //Set pointer to data buffer
+    qtd->buffer_status_val = 0;     //Reset all flags to zero
+    qtd->out_non_iso.xfer_size = xfer_len;
+    if (is_setup) {
+        qtd->out_non_iso.is_setup = 1;
+    }
+    if (hoc) {
+        qtd->in_non_iso.intr_cplt = 1;  //We need to set this to distinguish between a halt due to a QTD
+        qtd->in_non_iso.eol = 1;        //Used to halt the channel at this qtd
+    }
+    qtd->out_non_iso.active = 1;
+}
+
+/**
+ * @brief Set a QTD as NULL
+ *
+ * This sets the QTD to a value of 0. This is only useful when you need to insert
+ * blank QTDs into a list of QTDs
+ *
+ * @param qtd Pointer to the QTD
+ */
+static inline void usb_dwc_ll_qtd_set_null(usb_dwc_ll_dma_qtd_t *qtd)
+{
+    qtd->buffer = NULL;
+    qtd->buffer_status_val = 0;     //Disable qtd by clearing it to zero. Used by interrupt/isoc as an unscheudled frame
+}
+
+/**
+ * @brief Get the status of a QTD
+ *
+ * When a channel gets halted, call this to check whether each QTD was executed successfully
+ *
+ * @param qtd Pointer to the QTD
+ * @param[out] rem_len Number of bytes ramining in the QTD
+ * @param[out] status Status of the QTD
+ */
+static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem_len, int *status)
+{
+    //Status is the same regardless of IN or OUT
+    if (qtd->in_non_iso.active) {
+        //QTD was never processed
+        *status = USB_DWC_LL_QTD_STATUS_NOT_EXECUTED;
+    } else {
+        *status = qtd->in_non_iso.rx_status;
+    }
+    *rem_len = qtd->in_non_iso.xfer_size;
+    //Clear the QTD just for safety
+    qtd->buffer_status_val = 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32s2/touch_sensor_hal.c b/components/hal/esp32s2/touch_sensor_hal.c
index 78bc17819e0..c8f3789c8ae 100644
--- a/components/hal/esp32s2/touch_sensor_hal.c
+++ b/components/hal/esp32s2/touch_sensor_hal.c
@@ -9,7 +9,7 @@
 #include "soc/soc_pins.h"
 #include "soc/touch_sensor_pins.h"
 #include "hal/touch_sensor_hal.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 
 static int s_sleep_cycle = -1;
 static int s_meas_times = -1;
@@ -48,12 +48,12 @@ void touch_hal_deinit(void)
     touch_ll_clear_trigger_status_mask();
     touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
     touch_ll_timeout_disable();
-    touch_ll_waterproof_disable();
-    touch_ll_denoise_disable();
+    touch_ll_waterproof_enable(false);
+    touch_ll_denoise_enable(false);
     touch_pad_t prox_pad[SOC_TOUCH_PROXIMITY_CHANNEL_NUM] = {[0 ... (SOC_TOUCH_PROXIMITY_CHANNEL_NUM - 1)] = 0};
     touch_ll_proximity_set_channel_num((const touch_pad_t *)prox_pad);
     touch_ll_sleep_set_channel_num(0);
-    touch_ll_sleep_disable_proximity_sensing();
+    touch_ll_sleep_enable_proximity_sensing(false);
     touch_ll_reset();   // Reset the touch sensor FSM.
 }
 
@@ -90,25 +90,25 @@ void touch_hal_denoise_get_config(touch_pad_denoise_t *denoise)
 void touch_hal_denoise_enable(void)
 {
     touch_ll_clear_channel_mask(1U << SOC_TOUCH_DENOISE_CHANNEL);
-    touch_ll_denoise_enable();
+    touch_ll_denoise_enable(true);
 }
 
 void touch_hal_waterproof_set_config(const touch_pad_waterproof_t *waterproof)
 {
     touch_ll_waterproof_set_guard_pad(waterproof->guard_ring_pad);
-    touch_ll_waterproof_set_sheild_driver(waterproof->shield_driver);
+    touch_ll_waterproof_set_shield_driver(waterproof->shield_driver);
 }
 
 void touch_hal_waterproof_get_config(touch_pad_waterproof_t *waterproof)
 {
     touch_ll_waterproof_get_guard_pad(&waterproof->guard_ring_pad);
-    touch_ll_waterproof_get_sheild_driver(&waterproof->shield_driver);
+    touch_ll_waterproof_get_shield_driver(&waterproof->shield_driver);
 }
 
 void touch_hal_waterproof_enable(void)
 {
     touch_ll_clear_channel_mask(1U << SOC_TOUCH_SHIELD_CHANNEL);
-    touch_ll_waterproof_enable();
+    touch_ll_waterproof_enable(true);
 }
 
 bool touch_hal_enable_proximity(touch_pad_t touch_num, bool enabled)
diff --git a/components/hal/esp32s3/include/hal/cache_ll.h b/components/hal/esp32s3/include/hal/cache_ll.h
index 215473731e6..9ab5b7f5ff6 100644
--- a/components/hal/esp32s3/include/hal/cache_ll.h
+++ b/components/hal/esp32s3/include/hal/cache_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/hal/esp32s3/include/hal/gpio_ll.h b/components/hal/esp32s3/include/hal/gpio_ll.h
index 9a27591e8e5..3410e4f973b 100644
--- a/components/hal/esp32s3/include/hal/gpio_ll.h
+++ b/components/hal/esp32s3/include/hal/gpio_ll.h
@@ -354,15 +354,15 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, uint32_t gpio_num, uint32_t
 {
     if (level) {
         if (gpio_num < 32) {
-            hw->out_w1ts = (1 << gpio_num);
+            hw->out_w1ts = 1 << gpio_num;
         } else {
-            hw->out1_w1ts.data = (1 << (gpio_num - 32));
+            hw->out1_w1ts.val = 1 << (gpio_num - 32);
         }
     } else {
         if (gpio_num < 32) {
-            hw->out_w1tc = (1 << gpio_num);
+            hw->out_w1tc = 1 << gpio_num;
         } else {
-            hw->out1_w1tc.data = (1 << (gpio_num - 32));
+            hw->out1_w1tc.val = 1 << (gpio_num - 32);
         }
     }
 }
diff --git a/components/hal/esp32s3/include/hal/i2c_ll.h b/components/hal/esp32s3/include/hal/i2c_ll.h
index 50dfb6eaf74..9883b92488a 100644
--- a/components/hal/esp32s3/include/hal/i2c_ll.h
+++ b/components/hal/esp32s3/include/hal/i2c_ll.h
@@ -76,6 +76,8 @@ typedef enum {
 #define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT   (9)
 #define I2C_LL_SCL_WAIT_US_VAL_DEFAULT   (2000)  // Approximate value for SCL timeout regs (in us).
 
+#define I2C_LL_STRETCH_PROTECT_TIME  (0x3ff)
+
 /**
  * @brief  Calculate I2C bus frequency
  *         Note that the clock accuracy is affected by the external pull-up resistor,
@@ -920,6 +922,16 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
     dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
 }
 
+/**
+ * @brief Set I2C clock stretch protect num
+ *
+ * @param dev Beginning address of the peripheral registers
+ */
+static inline void i2c_ll_slave_set_stretch_protect_num(i2c_dev_t *dev, uint32_t protect_num)
+{
+    dev->scl_stretch_conf.stretch_protect_num = protect_num;
+}
+
 /**
  * @brief Check if i2c command is done.
  *
@@ -948,6 +960,18 @@ static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_h
     return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
 }
 
+/**
+ * @brief Get status of i2c slave
+ *
+ * @param Beginning address of the peripheral registers
+ * @return i2c slave working status
+ */
+__attribute__((always_inline))
+static inline i2c_slave_read_write_status_t i2c_ll_slave_get_read_write_status(i2c_dev_t *hw)
+{
+    return (hw->sr.slave_rw == 0) ? I2C_SLAVE_WRITE_BY_MASTER : I2C_SLAVE_READ_BY_MASTER;
+}
+
 //////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
 /////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
 /////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
diff --git a/components/hal/esp32s3/include/hal/i2s_ll.h b/components/hal/esp32s3/include/hal/i2s_ll.h
index 9f0ff7ec5af..c2ae3b9beda 100644
--- a/components/hal/esp32s3/include/hal/i2s_ll.h
+++ b/components/hal/esp32s3/include/hal/i2s_ll.h
@@ -372,7 +372,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
 
 /**
  * @brief Configure I2S RX module clock divider
- * @note mclk on ESP32 is shared by both TX and RX channel
+ * @note mclk on ESP32S3 is shared by both TX and RX channel
  *
  * @param hw Peripheral I2S hardware instance address.
  * @param mclk_div The mclk division coefficients
diff --git a/components/hal/esp32s3/include/hal/sdmmc_ll.h b/components/hal/esp32s3/include/hal/sdmmc_ll.h
index 89aa2a85290..27479059312 100644
--- a/components/hal/esp32s3/include/hal/sdmmc_ll.h
+++ b/components/hal/esp32s3/include/hal/sdmmc_ll.h
@@ -444,6 +444,18 @@ static inline bool sdmmc_ll_is_card_write_protected(sdmmc_dev_t *hw, uint32_t sl
     return is_protected;
 }
 
+/**
+ * @brief Switch between 3.3V and 1.8V mode
+ *
+ * @param hw    hardware instance address
+ * @param slot  slot
+ * @param en    enable / disable 1.8V (3.3V on disable)
+ */
+static inline void sdmmc_ll_enable_1v8_mode(sdmmc_dev_t *hw, uint32_t slot, bool en)
+{
+    //for compatibility
+}
+
 /**
  * @brief Enable DDR mode
  *
diff --git a/components/hal/esp32s3/include/hal/touch_sensor_hal.h b/components/hal/esp32s3/include/hal/touch_sensor_hal.h
index c80f624fde1..dc8f6fefdc1 100644
--- a/components/hal/esp32s3/include/hal/touch_sensor_hal.h
+++ b/components/hal/esp32s3/include/hal/touch_sensor_hal.h
@@ -15,7 +15,7 @@
 #pragma once
 
 #include "hal/touch_sensor_ll.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 
 #include_next "hal/touch_sensor_hal.h"
 
@@ -278,14 +278,10 @@ void touch_hal_filter_get_config(touch_filter_config_t *filter_info);
 /**
  * Enable touch sensor filter and detection algorithm.
  * For more details on the detection algorithm, please refer to the application documentation.
+ *
+ * @param enable set true to enable the filter
  */
-#define touch_hal_filter_enable() touch_ll_filter_enable()
-
-/**
- * Disable touch sensor filter and detection algorithm.
- * For more details on the detection algorithm, please refer to the application documentation.
- */
-#define touch_hal_filter_disable() touch_ll_filter_disable()
+#define touch_hal_filter_enable(enable) touch_ll_filter_enable(enable)
 
 /************************ Denoise register setting ************************/
 
@@ -326,7 +322,7 @@ void touch_hal_denoise_enable(void);
  * This denoise function filters out interference introduced on all channels,
  * such as noise introduced by the power supply and external EMI.
  */
-#define touch_hal_denoise_disable() touch_ll_denoise_disable()
+#define touch_hal_denoise_disable() touch_ll_denoise_enable(false)
 
 /**
  * Set internal reference capacitance of denoise channel.
@@ -391,7 +387,7 @@ void touch_hal_denoise_enable(void);
  *
  * @param pad_num Touch sensor channel number.
  */
-#define touch_hal_waterproof_set_sheild_driver(driver_level) touch_ll_waterproof_set_sheild_driver(driver_level)
+#define touch_hal_waterproof_set_sheild_driver(driver_level) touch_ll_waterproof_set_shield_driver(driver_level)
 
 /**
  * Get max equivalent capacitance for shield channel.
@@ -400,7 +396,7 @@ void touch_hal_denoise_enable(void);
  *
  * @param pad_num Touch sensor channel number.
  */
-#define touch_hal_waterproof_get_sheild_driver(driver_level) touch_ll_waterproof_get_sheild_driver(driver_level)
+#define touch_hal_waterproof_get_sheild_driver(driver_level) touch_ll_waterproof_get_shield_driver(driver_level)
 
 /**
  * Set parameter of waterproof function.
@@ -430,7 +426,7 @@ void touch_hal_waterproof_enable(void);
 /**
  * Disable parameter of waterproof function.
  */
-#define touch_hal_waterproof_disable() touch_ll_waterproof_disable()
+#define touch_hal_waterproof_disable() touch_ll_waterproof_enable(false)
 
 /************************ Proximity register setting ************************/
 
@@ -550,13 +546,9 @@ void touch_hal_sleep_channel_enable(touch_pad_t pad_num, bool enable);
 
 /**
  * Enable proximity function for sleep pad.
+ * @param enable the proximity sensing
  */
-#define touch_hal_sleep_enable_approach() touch_ll_sleep_enable_proximity_sensing()
-
-/**
- * Disable proximity function for sleep pad.
- */
-#define touch_hal_sleep_disable_approach() touch_ll_sleep_disable_proximity_sensing()
+#define touch_hal_sleep_enable_approach(enable) touch_ll_sleep_enable_proximity_sensing(enable)
 
 /**
  * Read benchmark of touch sensor for sleep pad.
diff --git a/components/hal/esp32s3/include/hal/touch_sensor_ll.h b/components/hal/esp32s3/include/hal/touch_sensor_ll.h
index d3dde4edd35..b42083a1f21 100644
--- a/components/hal/esp32s3/include/hal/touch_sensor_ll.h
+++ b/components/hal/esp32s3/include/hal/touch_sensor_ll.h
@@ -16,26 +16,764 @@
 
 #include <stdlib.h>
 #include <stdbool.h>
+#include "esp_bit_defs.h"
 #include "hal/misc.h"
+#include "hal/assert.h"
 #include "soc/touch_sensor_periph.h"
 #include "soc/rtc_cntl_struct.h"
 #include "soc/rtc_io_struct.h"
 #include "soc/sens_struct.h"
 #include "soc/soc_caps.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sens_types.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
+#define TOUCH_LL_READ_RAW           0x0
+#define TOUCH_LL_READ_BENCHMARK     0x2
+#define TOUCH_LL_READ_SMOOTH        0x3
+
+#define TOUCH_LL_TIMER_FORCE_DONE   0x3
+#define TOUCH_LL_TIMER_DONE         0x0
+
+#define TOUCH_LL_INTR_MASK_SCAN_DONE        BIT(4)
+#define TOUCH_LL_INTR_MASK_DONE             BIT(6)
+#define TOUCH_LL_INTR_MASK_ACTIVE           BIT(7)
+#define TOUCH_LL_INTR_MASK_INACTIVE         BIT(8)
+#define TOUCH_LL_INTR_MASK_TIMEOUT          BIT(18)
+#define TOUCH_LL_INTR_MASK_PROX_DONE        BIT(20)
+#define TOUCH_LL_INTR_MASK_ALL              (TOUCH_LL_INTR_MASK_SCAN_DONE | \
+                                             TOUCH_LL_INTR_MASK_DONE | \
+                                             TOUCH_LL_INTR_MASK_ACTIVE | \
+                                             TOUCH_LL_INTR_MASK_INACTIVE | \
+                                             TOUCH_LL_INTR_MASK_TIMEOUT | \
+                                             TOUCH_LL_INTR_MASK_PROX_DONE)
+
+#define TOUCH_LL_FULL_CHANNEL_MASK          ((uint16_t)((1U << SOC_TOUCH_SENSOR_NUM) - 1))
+#define TOUCH_LL_NULL_CHANNEL               (0)  // Null Channel id. Used for disabling some functions like sleep/proximity/waterproof
+
+#define TOUCH_LL_PAD_MEASURE_WAIT_MAX      (0xFF)      // The timer frequency is 8Mhz, the max value is 0xff
+#define TOUCH_LL_ACTIVE_THRESH_MAX         (0x3FFFFF)  // Max channel active threshold
+#define TOUCH_LL_TIMEOUT_MAX               (0x3FFFFF)  // Max timeout value
+
+/**
+ * Enable/disable clock gate of touch sensor.
+ *
+ * @param enable true/false.
+ */
+static inline void touch_ll_enable_clock_gate(bool enable)
+{
+    RTCCNTL.touch_ctrl2.touch_clkgate_en = enable; //enable touch clock for FSM. or force enable.
+}
+
+/**
+ * Enable/disable clock gate of touch sensor.
+ *
+ * @param enable true/false.
+ */
+static inline void touch_ll_reset_module(void)
+{
+    RTCCNTL.touch_ctrl2.touch_reset = 1;
+    RTCCNTL.touch_ctrl2.touch_reset = 0;    // Should be set 0.
+}
+
+/*********************************** Interrupts *******************************/
+/**
+ * Enable touch sensor interrupt by bitmask.
+ *
+ * @param int_mask interrupt mask
+ */
+static inline void touch_ll_interrupt_enable(uint32_t int_mask)
+{
+    uint32_t mask = RTCCNTL.int_ena_w1ts.val;
+    mask |= (int_mask & TOUCH_LL_INTR_MASK_ALL);
+    RTCCNTL.int_ena_w1ts.val = mask;
+}
+
+/**
+ * Disable touch sensor interrupt by bitmask.
+ *
+ * @param int_mask interrupt mask
+ */
+static inline void touch_ll_interrupt_disable(uint32_t int_mask)
+{
+    uint32_t mask = int_mask & TOUCH_LL_INTR_MASK_ALL;
+    RTCCNTL.int_ena_w1tc.val = mask;
+}
+
+/**
+ * Clear touch sensor interrupt by bitmask.
+ *
+ * @param int_mask Pad mask to clear interrupts
+ */
+__attribute__((always_inline))
+static inline void touch_ll_interrupt_clear(uint32_t int_mask)
+{
+    RTCCNTL.int_clr.val = int_mask & TOUCH_LL_INTR_MASK_ALL;
+}
+
+/**
+ * Get the bitmask of touch sensor interrupt status.
+ *
+ * @return type interrupt type
+ */
+__attribute__((always_inline))
+static inline uint32_t touch_ll_get_intr_status_mask(void)
+{
+    uint32_t intr_st = RTCCNTL.int_st.val;
+    return intr_st & TOUCH_LL_INTR_MASK_ALL;
+}
+
+/********************************* Status Info ********************************/
+/**
+ * Get the current measure channel. Touch sensor measurement is cyclic scan mode.
+ *
+ * @return
+ *      - touch channel number
+ */
+__attribute__((always_inline))
+static inline uint32_t touch_ll_get_current_meas_channel(void)
+{
+    return SENS.sar_touch_status0.touch_scan_curr;
+}
+
+/**
+ * Get touch sensor measure status. No block.
+ *
+ * @return
+ *      - If touch sensors measure done.
+ */
+__attribute__((always_inline))
+static inline bool touch_ll_is_measure_done(void)
+{
+    return (bool)SENS.sar_touch_chn_st.touch_meas_done;
+}
+
+/**
+ * Get the touch sensor active channel mask, usually used in ISR to decide which channels are 'touched'.
+ *
+ * @param active_mask The touch channel status. e.g. Touch1 trigger status is `status_mask & (BIT1)`.
+ */
+__attribute__((always_inline))
+static inline void touch_ll_get_active_channel_mask(uint32_t *active_mask)
+{
+    *active_mask = SENS.sar_touch_chn_st.touch_pad_active;
+}
+
+/**************************** Measurement Configuration ***********************/
+/**
+ * @brief Enable or disable the channel that will be scanned.
+ * @note  The shield channel should not be enabled to scan here
+ *
+ * @param chan_mask The channel mask to be enabled or disabled
+ * @param enable Enable or disable the channel mask
+ */
+__attribute__((always_inline))
+static inline void touch_ll_enable_scan_mask(uint16_t chan_mask, bool enable)
+{
+    uint16_t mask = chan_mask & TOUCH_LL_FULL_CHANNEL_MASK;
+    uint16_t prev_mask = RTCCNTL.touch_scan_ctrl.touch_scan_pad_map;
+    if (enable) {
+        RTCCNTL.touch_scan_ctrl.touch_scan_pad_map = prev_mask | mask;
+    } else {
+        RTCCNTL.touch_scan_ctrl.touch_scan_pad_map = prev_mask & (~mask);
+    }
+}
+
+/**
+ * Set touch sensor threshold of charge cycles that triggers pad active state.
+ * The threshold determines the sensitivity of the touch sensor.
+ * The threshold is the original value of the trigger state minus the benchmark value.
+ *
+ * @note  If set "TOUCH_PAD_THRESHOLD_MAX", the touch is never be triggered.
+ * @param touch_num The touch pad id
+ * @param thresh    The threshold of charge cycles
+ */
+static inline void touch_ll_set_chan_active_threshold(uint32_t touch_num, uint32_t thresh)
+{
+    HAL_ASSERT(touch_num > 0);
+    SENS.touch_thresh[touch_num - 1].thresh = thresh;
+}
+
+/**
+ * Set the power on wait cycle
+ *
+ * @param wait_cycles
+ */
+static inline void touch_ll_set_power_on_wait_cycle(uint32_t wait_cycles)
+{
+    //the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl2, touch_xpd_wait, wait_cycles); //wait volt stable
+}
+
+/**
+ * Set touch sensor touch sensor charge and discharge times of every measurement on a pad.
+ *
+ * @param charge_times The times of charge and discharge in each measure process of touch channels.
+ *                     The timer frequency is RTC_FAST (about 16M). Range: 0 ~ 0xffff.
+ */
+static inline void touch_ll_set_charge_times( uint16_t charge_times)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_meas_num, charge_times);
+}
+
+/**
+ * Set touch sensor sleep time.
+ *
+ * @param interval_ticks    The touch sensor will sleep for some cycles after each measurement.
+ *                          interval_ticks decide the interval between each measurement.
+ *                          t_sleep = interval_ticks / (RTC_SLOW_CLK frequency).
+ *                          The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ */
+static inline void touch_ll_set_measure_interval_ticks(uint16_t interval_ticks)
+{
+    // touch sensor sleep cycle Time = interval_ticks / RTC_SLOW_CLK
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_ctrl1, touch_sleep_cycles, interval_ticks);
+}
+
+/**
+ * Set the Touch pad charge speed.
+ *
+ * @param touch_num     Touch channel number
+ * @param charge_speed  Charge speed of this touch channel
+ */
+static inline void touch_ll_set_charge_speed(uint32_t touch_num, touch_charge_speed_t charge_speed)
+{
+#define CHARGE_SPEED_MASK(val, num) ((val) << (29 - (num) * 3))
+    uint32_t speed_mask = 0;
+    if (touch_num < 10) {
+        speed_mask = RTCCNTL.touch_dac.val;
+        speed_mask &= ~CHARGE_SPEED_MASK(0x07, touch_num);  // clear the old value
+        RTCCNTL.touch_dac.val = speed_mask | CHARGE_SPEED_MASK(charge_speed, touch_num);
+    } else {
+        speed_mask = RTCCNTL.touch_dac1.val;
+        speed_mask &= ~CHARGE_SPEED_MASK(0x07, touch_num - 10);  // clear the old value
+        RTCCNTL.touch_dac1.val = speed_mask | CHARGE_SPEED_MASK(charge_speed, touch_num - 10);
+    }
+#undef CHARGE_SPEED_MASK
+}
+
+/**
+ * Set the upper limitation of the touch channel voltage while charging
+ *
+ * @param high_lim      The high(upper) limitation of charge
+ */
+static inline void touch_ll_set_charge_voltage_high_limit(touch_volt_lim_h_t high_lim)
+{
+    RTCCNTL.touch_ctrl2.touch_drefh = (uint32_t)high_lim & 0x3;
+    RTCCNTL.touch_ctrl2.touch_drange = (uint32_t)high_lim >> 2;
+}
+
+/**
+ * Set the lower limitation of the touch channel voltage while discharging
+ *
+ * @param low_lim      The lower limitation of discharge
+ */
+static inline void touch_ll_set_charge_voltage_low_limit(touch_volt_lim_l_t low_lim)
+{
+    RTCCNTL.touch_ctrl2.touch_drefl = low_lim;
+}
+
+/**
+ * Set the initial charge voltage of touch channel
+ * i.e., the touch pad measurement start from a low voltage or a high voltage
+ *
+ * @param touch_num         Touch channel number
+ * @param init_charge_volt  The initial charge voltage
+ */
+static inline void touch_ll_set_init_charge_voltage(uint32_t touch_num, touch_init_charge_volt_t init_charge_volt)
+{
+    RTCIO.touch_pad[touch_num].tie_opt = init_charge_volt;
+}
+
+/**
+ * Set the connection of the idle channel
+ * The idle channel is the channel that is enabled and powered on but not under measurement.
+ *
+ * @param idle_conn
+ */
+static inline void touch_ll_set_idle_channel_connection(touch_idle_conn_t idle_conn)
+{
+    RTCCNTL.touch_scan_ctrl.touch_inactive_connection = idle_conn;
+}
+
+/**
+ * Enable touch sensor channel. Register touch channel into touch sensor measurement group.
+ * The working mode of the touch sensor is simultaneous measurement.
+ * This function will set the measure bits according to the given bitmask.
+ *
+ * @note  If set this mask, the FSM timer should be stop firstly.
+ * @note  The touch sensor that in scan map, should be deinit GPIO function firstly.
+ * @param enable_mask bitmask of touch sensor scan group.
+ *        e.g. TOUCH_PAD_NUM1 -> BIT(1)
+ * @return
+ *      - ESP_OK on success
+ */
+static inline void touch_ll_enable_channel_mask(uint16_t enable_mask)
+{
+    RTCCNTL.touch_scan_ctrl.touch_scan_pad_map  = enable_mask;
+    SENS.sar_touch_conf.touch_outen = enable_mask;
+}
+
+/**
+ * Set the timeout to enable or disable the check for all touch sensor channels measurements.
+ * When the touch reading of a touch channel exceeds the measurement threshold,
+ * If enable: a timeout interrupt will be generated and it will go to the next channel measurement.
+ * If disable: the FSM is always on the channel, until the measurement of this channel is over.
+ *
+ * @param timeout_cycles The maximum time cycles of the measurement on one channel.
+ *                       Set to 0 to disable the timeout.
+ *                       Set to non-zero to enable the timeout and set the timeout cycles.
+ */
+static inline void touch_ll_set_timeout(uint32_t timeout_cycles)
+{
+    if (timeout_cycles) {
+        RTCCNTL.touch_timeout_ctrl.touch_timeout_num = timeout_cycles;
+        RTCCNTL.touch_timeout_ctrl.touch_timeout_en = 1;
+    } else {
+        RTCCNTL.touch_timeout_ctrl.touch_timeout_en = 0;
+    }
+}
+
+/**
+ * Clear all touch sensor channels active status.
+ *
+ * @note Generally no manual removal is required.
+ */
+static inline void touch_ll_clear_active_channel_status(void)
+{
+    SENS.sar_touch_conf.touch_status_clr = 1;
+}
+
+
+/**
+ * Select touch sensor dbias to save power in sleep mode.
+ *
+ * @note If change the dbias, the reading of touch sensor will changed. Users should make sure the threshold.
+ */
+static inline void touch_ll_set_bias_type(touch_bias_type_t bias_type)
+{
+    RTCCNTL.touch_ctrl2.touch_dbias = bias_type;
+}
+
+/********************************* FSM Operation ******************************/
+/**
+ * Touch timer trigger measurement and always wait measurement done.
+ * Force done for touch timer ensures that the timer always can get the measurement done signal.
+ * @note The `force done` signal should last as least one slow clock tick
+ */
+__attribute__((always_inline))
+static inline void touch_ll_force_done_curr_measurement(void)
+{
+    RTCCNTL.touch_ctrl2.touch_timer_force_done = TOUCH_LL_TIMER_FORCE_DONE;
+    RTCCNTL.touch_ctrl2.touch_timer_force_done = TOUCH_LL_TIMER_DONE;
+}
+
+/**
+ * Enable touch sensor FSM timer trigger (continuous) mode or software trigger (oneshot) mode.
+ *
+ * @param enable Enable FSM timer mode.
+ *        True: the FSM will trigger scanning repeatedly under the control of the hardware timer (continuous mode)
+ *        False: the FSM will trigger scanning once under the control of the software (continuous mode)
+ */
+__attribute__((always_inline))
+static inline void touch_ll_enable_fsm_timer(bool enable)
+{
+    touch_ll_force_done_curr_measurement();
+    // Set 0 to start by timer, otherwise by software
+    RTCCNTL.touch_ctrl2.touch_start_force = !enable;
+}
+
+/**
+ * Start touch sensor FSM timer to run FSM repeatedly
+ * The measurement action can be triggered by the hardware timer, as well as by the software instruction.
+ * @note
+ *      The timer should be triggered
+ */
+__attribute__((always_inline))
+static inline void touch_ll_start_fsm_repeated_timer(void)
+{
+    /**
+     * Touch timer trigger measurement and always wait measurement done.
+     * Force done for touch timer ensures that the timer always can get the measurement done signal.
+     */
+    touch_ll_force_done_curr_measurement();
+    RTCCNTL.touch_ctrl2.touch_slp_timer_en = 1;
+}
+
+/**
+ * Stop touch sensor FSM timer.
+ *        The measurement action can be triggered by the hardware timer, as well as by the software instruction.
+ */
+__attribute__((always_inline))
+static inline void touch_ll_stop_fsm_repeated_timer(void)
+{
+    RTCCNTL.touch_ctrl2.touch_slp_timer_en = 0;
+    touch_ll_force_done_curr_measurement();
+}
+
+/**
+ * Is the FSM repeated timer enabled.
+ * @note when the timer is enabled, RTC clock should not be power down
+ *
+ * @return
+ *      - true: enabled
+ *      - false: disabled
+ */
+__attribute__((always_inline))
+static inline bool touch_ll_is_fsm_repeated_timer_enabled(void)
+{
+    return (bool)RTCCNTL.touch_ctrl2.touch_slp_timer_en;
+}
+
+/**
+ * Enable the touch sensor FSM start signal from software
+ */
+__attribute__((always_inline))
+static inline void touch_ll_trigger_oneshot_measurement(void)
+{
+    RTCCNTL.touch_ctrl2.touch_start_en = 1;
+    RTCCNTL.touch_ctrl2.touch_start_en = 0;
+}
+
+/**
+ * @brief Power on the channel by mask
+ *
+ * @param chan_mask The channel mask that needs to power on
+ */
+__attribute__((always_inline))
+static inline void touch_ll_channel_sw_measure_mask(uint16_t chan_mask)
+{
+    (void) chan_mask;
+    // Only for compatibility
+}
+
+/****************************** Benchmark Operation ***************************/
+/**
+ * Force reset benchmark to raw data of touch sensor.
+ *
+ * @note If call this API, make sure enable clock gate(`touch_ll_clkgate`) first.
+ * @param chan_mask touch channel mask
+ */
+__attribute__((always_inline))
+static inline void touch_ll_reset_chan_benchmark(uint32_t chan_mask)
+{
+    SENS.sar_touch_chn_st.touch_channel_clr = chan_mask;
+}
+
+static inline void touch_ll_sleep_reset_benchmark(void)
+{
+    RTCCNTL.touch_approach.touch_slp_channel_clr = 1;
+}
+
+/************************************** Data **********************************/
+/**
+ * Get the data of the touch channel according to the types
+ *
+ * @param touch_num touch pad index
+ * @param type  data type
+ *              0/1: TOUCH_LL_READ_RAW, raw data of touch channel
+ *              2:   TOUCH_LL_READ_BENCHMARK, benchmark value of touch channel,
+ *                   the benchmark value is the maximum during the first measurement period
+ *              3:   TOUCH_LL_READ_SMOOTH, the smoothed data that obtained by filtering the raw data.
+ * @param data pointer to the data
+ */
+__attribute__((always_inline))
+static inline void touch_ll_read_chan_data(uint32_t touch_num, uint8_t type, uint32_t *data)
+{
+    HAL_ASSERT(type <= TOUCH_LL_READ_SMOOTH);
+    HAL_ASSERT(touch_num > 0);
+    SENS.sar_touch_conf.touch_data_sel = type;
+    *data = SENS.sar_touch_status[touch_num - 1].touch_pad_data;
+}
+
+/****************************** Filter Configuration **************************/
+
+/**
+ * Enable or disable touch sensor filter and detection algorithm.
+ * For more details on the detection algorithm, please refer to the application documentation.
+ */
+static inline void touch_ll_filter_enable(bool enable)
+{
+    RTCCNTL.touch_filter_ctrl.touch_filter_en = enable;
+}
+
+
+/**
+ * Set filter mode. The input of the filter is the raw value of touch reading,
+ * and the output of the filter is involved in the judgment of the touch state.
+ *
+ * @param mode Filter mode type. Refer to ``touch_benchmark_filter_mode_t``.
+ */
+static inline void touch_ll_filter_set_filter_mode(touch_benchmark_filter_mode_t mode)
+{
+    RTCCNTL.touch_filter_ctrl.touch_filter_mode = mode;
+}
+
+/**
+ * Set jitter filter step size.
+ * If filter mode is jitter, should set filter step for jitter.
+ * Range: 0 ~ 15
+ *
+ * @param step The step size of the data change.
+ */
+static inline void touch_ll_filter_set_jitter_step(uint32_t step)
+{
+    RTCCNTL.touch_filter_ctrl.touch_jitter_step = step;
+}
+
+/**
+ * Set the denoise coefficient regarding the denoise level.
+ *
+ * @param denoise_lvl   Range [0 ~ 4]. 0 = no noise resistance, otherwise higher denoise_lvl means more noise resistance.
+ *                      0 = no noise resistance
+ *                      1 = noise resistance is 1/4 benchmark
+ *                      2 = noise resistance is 3/8 benchmark
+ *                      3 = noise resistance is 1/2 benchmark
+ *                      4 = noise resistance is 1 benchmark
+ */
+static inline void touch_ll_filter_set_denoise_level(int denoise_lvl)
+{
+    HAL_ASSERT(denoise_lvl >= 0 && denoise_lvl <= 4);
+    bool always_update = denoise_lvl == 0;
+    /* Map denoise level to actual noise threshold coefficients
+       denoise_lvl=1 -> noise_thresh=2, 1/4 benchmark
+       denoise_lvl=2 -> noise_thresh=1, 3/8 benchmark
+       denoise_lvl=3 -> noise_thresh=0, 1/2 benchmark
+       denoise_lvl=4 -> noise_thresh=3, 1   benchmark */
+    uint32_t noise_thresh = denoise_lvl == 4 ? 3 : 3 - denoise_lvl;
+
+    RTCCNTL.touch_filter_ctrl.touch_bypass_noise_thres = always_update;
+    RTCCNTL.touch_filter_ctrl.touch_noise_thres = always_update ? 0 : noise_thresh;
+
+    RTCCNTL.touch_filter_ctrl.touch_bypass_nn_thres = always_update;
+    RTCCNTL.touch_filter_ctrl.config2 = always_update ? 0 : noise_thresh;
+    RTCCNTL.touch_filter_ctrl.config1 = 0xF;
+}
+
+/**
+ * Set the hysteresis value of the active threshold
+ * While the touch data is greater than active_threshold + hysteresis and last for several ticks, the channel is activated,
+ * and while the touch data is smaller than active_threshold - hysteresis and last for several ticks, the channel is inactivated
+ *
+ * @param hysteresis The hysteresis value of active threshold
+ */
+static inline void touch_ll_filter_set_active_hysteresis(uint32_t hysteresis)
+{
+    RTCCNTL.touch_filter_ctrl.config3 = hysteresis;
+}
+
+/**
+ * Set filter mode. The input to the filter is raw data and the output is the smooth data.
+ * The smooth data is used to determine the touch status.
+ *
+ * @param mode Filter mode type. Refer to ``touch_smooth_filter_mode_t``.
+ */
+static inline void touch_ll_filter_set_smooth_mode(touch_smooth_filter_mode_t mode)
+{
+    RTCCNTL.touch_filter_ctrl.touch_smooth_lvl = mode;
+}
+
+/**
+ * Set debounce count, such as `n`. If the measured values continue to exceed
+ * the threshold for `n+1` times, it is determined that the touch sensor state changes.
+ *
+ * @param dbc_cnt Debounce count value.
+ */
+static inline void touch_ll_filter_set_debounce(uint32_t dbc_cnt)
+{
+    RTCCNTL.touch_filter_ctrl.touch_debounce = dbc_cnt;
+}
+
+/**************************** Sleep Configurations ****************************/
+/**
+ * Set the trigger threshold of touch sensor in deep sleep.
+ * The threshold determines the sensitivity of the touch sensor.
+ * The threshold is the original value of the trigger state minus the benchmark value.
+ *
+ * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
+ */
+static inline void touch_ll_sleep_set_threshold(uint32_t touch_thres)
+{
+    RTCCNTL.touch_slp_thres.touch_slp_th = touch_thres;
+}
+
+/**
+ * Set touch channel number for sleep channel.
+ *
+ * @note Only one touch sensor channel is supported in deep sleep mode.
+ * @param touch_num Touch sensor channel number.
+ */
+static inline void touch_ll_sleep_set_channel_num(uint32_t touch_num)
+{
+    RTCCNTL.touch_slp_thres.touch_slp_pad = touch_num;
+}
+
+/**
+ * Enable proximity sensing function for sleep channel.
+ */
+static inline void touch_ll_sleep_enable_proximity_sensing(bool enable)
+{
+    RTCCNTL.touch_slp_thres.touch_slp_approach_en = enable;
+}
+
+/************************* Waterproof Configurations **************************/
+/**
+ * Enable parameter of waterproof function.
+ *
+ * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel.
+ * Guard pad is used to detect the large area of water covering the touch panel.
+ * Shield pad is used to shield the influence of water droplets covering the touch panel.
+ * It is generally designed as a grid and is placed around the touch buttons.
+ * @param enable Enable or disable waterproof function.
+ */
+static inline void touch_ll_waterproof_enable(bool enable)
+{
+    RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = enable;
+}
+
+/**
+ * Set touch channel use for guard channel.
+ *
+ * @param pad_num Touch sensor channel number.
+ */
+static inline void touch_ll_waterproof_set_guard_chan(uint32_t pad_num)
+{
+    RTCCNTL.touch_scan_ctrl.touch_out_ring = pad_num;
+}
 
-#define TOUCH_LL_READ_RAW           0x0
-#define TOUCH_LL_READ_BENCHMARK     0x2
-#define TOUCH_LL_READ_SMOOTH        0x3
-#define TOUCH_LL_TIMER_FORCE_DONE   0x3
-#define TOUCH_LL_TIMER_DONE         0x0
+/**
+ * Set max equivalent capacitance for shield channel.
+ * The equivalent capacitance of the shielded channel can be calculated
+ * from the reading of denoise channel.
+ *
+ * @param pad_num Touch sensor channel number. Refer to ``touch_chan_shield_cap_t``
+ */
+static inline void touch_ll_waterproof_set_shield_driver(touch_chan_shield_cap_t driver_level)
+{
+    RTCCNTL.touch_scan_ctrl.touch_bufdrv = driver_level;
+}
+
+/****************************** Proximity Sensing *****************************/
+/**
+ * Set the proximity sensing channel to the specific touch channel
+ * To disable the proximity channel, point this pad to `TOUCH_LL_NULL_CHANNEL`
+ *
+ * @param prox_chan  proximity sensing channel.
+ * @param touch_num  The touch channel that supposed to be used as proximity sensing channel
+ */
+static inline void touch_ll_set_proximity_sensing_channel(uint8_t prox_chan, uint32_t touch_num)
+{
+    switch (prox_chan) {
+        case 0:
+            SENS.sar_touch_conf.touch_approach_pad0 = touch_num;
+            break;
+        case 1:
+            SENS.sar_touch_conf.touch_approach_pad1 = touch_num;
+            break;
+        case 2:
+            SENS.sar_touch_conf.touch_approach_pad2 = touch_num;
+            break;
+        default:
+            // invalid proximity channel
+            abort();
+    }
+}
+
+/**
+ * Set the total scan times of the proximity sensing channel.
+ *
+ * @param scan_times The total scan times of the proximity sensing channel
+ */
+static inline void touch_ll_proximity_set_total_scan_times(uint32_t scan_times)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time, scan_times);
+}
+
+/**
+ * Get the total scan times of the proximity sensing channel.
+ *
+ * @return
+ *      - The total scan times of the proximity sensing channel
+ */
+__attribute__((always_inline))
+static inline uint32_t touch_ll_proximity_get_total_scan_times(void)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(RTCCNTL.touch_approach, touch_approach_meas_time);
+}
+
+/**
+ * Get the current scan count for proximity channel.
+ *
+ * @param touch_num Touch channel number.
+ * @return
+ *      - Current scan count for proximity channel
+ */
+__attribute__((always_inline))
+static inline uint32_t touch_ll_proximity_get_curr_scan_cnt(uint32_t touch_num)
+{
+    if (SENS.sar_touch_conf.touch_approach_pad0 == touch_num) {
+        return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad0_cnt);
+    } else if (SENS.sar_touch_conf.touch_approach_pad1 == touch_num) {
+        return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad1_cnt);
+    } else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) {
+        return HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad2_cnt);
+    }
+    return 0;
+}
+
+/******************************* Denoise Channel ******************************/
+/**
+ * Enable denoise function.
+ * T0 is an internal channel that does not have a corresponding external GPIO.
+ * T0 will work simultaneously with the measured channel Tn. Finally, the actual
+ * measured value of Tn is the value after subtracting lower bits of T0.
+ * This denoise function filters out interference introduced on all channels,
+ * such as noise introduced by the power supply and external EMI.
+ * @param enable  enable the denoise channel
+ */
+static inline void touch_ll_denoise_enable(bool enable)
+{
+    RTCCNTL.touch_scan_ctrl.touch_denoise_en = enable;
+}
+
+/**
+ * Set internal reference capacitance of denoise channel.
+ * Select the appropriate internal reference capacitance value so that
+ * the reading of denoise channel is closest to the reading of the channel being measured.
+ *
+ * @param capacitance   Reference capacitance level.
+ */
+static inline void touch_ll_denoise_set_reference_cap(touch_denoise_chan_cap_t capacitance)
+{
+    RTCCNTL.touch_ctrl2.touch_refc = capacitance;
+}
+
+/**
+ * Set denoise resolution of denoise channel.
+ * Determined by measuring the noise amplitude of the denoise channel.
+ *
+ * @param resolution Denoise resolution of denoise channel.
+ */
+static inline void touch_ll_denoise_set_resolution(touch_denoise_chan_resolution_t resolution)
+{
+    RTCCNTL.touch_scan_ctrl.touch_denoise_res = resolution;
+}
 
-#define TOUCH_LL_PAD_MEASURE_WAIT_MAX      (0xFF)  /*!<The timer frequency is 8Mhz, the max value is 0xff */
+/**
+ * Read denoise measure value (TOUCH_PAD_NUM0).
+ *
+ * @param denoise value of denoise.
+ */
+static inline void touch_ll_denoise_read_data(uint32_t *data)
+{
+    *data =  SENS.sar_touch_denoise.touch_denoise_data;
+}
 
+/******************************************************************************/
+/*                   Legacy APIs (to be removed in esp-idf v6.0)              */
+/******************************************************************************/
+#include "hal/touch_sensor_legacy_types.h"
 /**
  * Set touch sensor touch sensor times of charge and discharge.
  *
@@ -85,11 +823,11 @@ static inline void touch_ll_get_sleep_time(uint16_t *sleep_time)
 }
 
 /**
- * Set touch sensor high voltage threshold of chanrge.
+ * Set touch sensor high voltage threshold of charge.
  * The touch sensor measures the channel capacitance value by charging and discharging the channel.
  * So the high threshold should be less than the supply voltage.
  *
- * @param refh The high voltage threshold of chanrge.
+ * @param refh The high voltage threshold of charge.
  */
 static inline void touch_ll_set_voltage_high(touch_high_volt_t refh)
 {
@@ -97,11 +835,11 @@ static inline void touch_ll_set_voltage_high(touch_high_volt_t refh)
 }
 
 /**
- * Get touch sensor high voltage threshold of chanrge.
+ * Get touch sensor high voltage threshold of charge.
  * The touch sensor measures the channel capacitance value by charging and discharging the channel.
  * So the high threshold should be less than the supply voltage.
  *
- * @param refh The high voltage threshold of chanrge.
+ * @param refh The high voltage threshold of charge.
  */
 static inline void touch_ll_get_voltage_high(touch_high_volt_t *refh)
 {
@@ -131,11 +869,11 @@ static inline void touch_ll_get_voltage_low(touch_low_volt_t *refl)
 }
 
 /**
- * Set touch sensor high voltage attenuation of chanrge. The actual charge threshold is high voltage threshold minus attenuation value.
+ * Set touch sensor high voltage attenuation of charge. The actual charge threshold is high voltage threshold minus attenuation value.
  * The touch sensor measures the channel capacitance value by charging and discharging the channel.
  * So the high threshold should be less than the supply voltage.
  *
- * @param refh The high voltage threshold of chanrge.
+ * @param refh The high voltage threshold of charge.
  */
 static inline void touch_ll_set_voltage_attenuation(touch_volt_atten_t atten)
 {
@@ -143,11 +881,11 @@ static inline void touch_ll_set_voltage_attenuation(touch_volt_atten_t atten)
 }
 
 /**
- * Get touch sensor high voltage attenuation of chanrge. The actual charge threshold is high voltage threshold minus attenuation value.
+ * Get touch sensor high voltage attenuation of charge. The actual charge threshold is high voltage threshold minus attenuation value.
  * The touch sensor measures the channel capacitance value by charging and discharging the channel.
  * So the high threshold should be less than the supply voltage.
  *
- * @param refh The high voltage threshold of chanrge.
+ * @param refh The high voltage threshold of charge.
  */
 static inline void touch_ll_get_voltage_attenuation(touch_volt_atten_t *atten)
 {
@@ -427,20 +1165,6 @@ static inline uint32_t IRAM_ATTR touch_ll_read_raw_data(touch_pad_t touch_num)
     return SENS.sar_touch_status[touch_num - 1].touch_pad_data;
 }
 
-/**
- * Get touch sensor measure status. No block.
- *
- * @return
- *      - If touch sensors measure done.
- */
-__attribute__((always_inline))
-static inline bool touch_ll_is_measure_done(void)
-{
-    return (bool)SENS.sar_touch_chn_st.touch_meas_done;
-}
-
-/************************* esp32s2 only *************************/
-
 /**
  * Reset the whole of touch module.
  *
@@ -483,17 +1207,6 @@ static inline void touch_ll_get_idle_channel_connect(touch_pad_conn_type_t *type
     *type = (touch_pad_conn_type_t)(RTCCNTL.touch_scan_ctrl.touch_inactive_connection);
 }
 
-/**
- * Get the current measure channel. Touch sensor measurement is cyclic scan mode.
- *
- * @return
- *      - touch channel number
- */
-static inline touch_pad_t IRAM_ATTR touch_ll_get_current_meas_channel(void)
-{
-    return (touch_pad_t)(SENS.sar_touch_status0.touch_scan_curr);
-}
-
 /**
  * Enable touch sensor interrupt by bitmask.
  *
@@ -700,17 +1413,6 @@ static inline void touch_ll_reset_benchmark(touch_pad_t touch_num)
     }
 }
 
-/**
- * Set filter mode. The input of the filter is the raw value of touch reading,
- * and the output of the filter is involved in the judgment of the touch state.
- *
- * @param mode Filter mode type. Refer to ``touch_filter_mode_t``.
- */
-static inline void touch_ll_filter_set_filter_mode(touch_filter_mode_t mode)
-{
-    RTCCNTL.touch_filter_ctrl.touch_filter_mode = mode;
-}
-
 /**
  * Get filter mode. The input of the filter is the raw value of touch reading,
  * and the output of the filter is involved in the judgment of the touch state.
@@ -722,17 +1424,6 @@ static inline void touch_ll_filter_get_filter_mode(touch_filter_mode_t *mode)
     *mode = (touch_filter_mode_t)RTCCNTL.touch_filter_ctrl.touch_filter_mode;
 }
 
-/**
- * Set filter mode. The input to the filter is raw data and the output is the smooth data.
- * The smooth data is used to determine the touch status.
- *
- * @param mode Filter mode type. Refer to ``touch_smooth_mode_t``.
- */
-static inline void touch_ll_filter_set_smooth_mode(touch_smooth_mode_t mode)
-{
-    RTCCNTL.touch_filter_ctrl.touch_smooth_lvl = mode;
-}
-
 /**
  * Get filter mode. The smooth data is used to determine the touch status.
  *
@@ -743,17 +1434,6 @@ static inline void touch_ll_filter_get_smooth_mode(touch_smooth_mode_t *mode)
     *mode = (touch_smooth_mode_t)(RTCCNTL.touch_filter_ctrl.touch_smooth_lvl);
 }
 
-/**
- * Set debounce count, such as `n`. If the measured values continue to exceed
- * the threshold for `n+1` times, it is determined that the touch sensor state changes.
- *
- * @param dbc_cnt Debounce count value.
- */
-static inline void touch_ll_filter_set_debounce(uint32_t dbc_cnt)
-{
-    RTCCNTL.touch_filter_ctrl.touch_debounce = dbc_cnt;
-}
-
 /**
  * Get debounce count.
  *
@@ -791,18 +1471,6 @@ static inline void touch_ll_filter_get_noise_thres(uint32_t *noise_thr)
     *noise_thr = RTCCNTL.touch_filter_ctrl.touch_noise_thres;
 }
 
-/**
- * Set jitter filter step size.
- * If filter mode is jitter, should set filter step for jitter.
- * Range: 0 ~ 15
- *
- * @param step The step size of the data change.
- */
-static inline void touch_ll_filter_set_jitter_step(uint32_t step)
-{
-    RTCCNTL.touch_filter_ctrl.touch_jitter_step = step;
-}
-
 /**
  * Get jitter filter step size.
  * If filter mode is jitter, should set filter step for jitter.
@@ -815,52 +1483,8 @@ static inline void touch_ll_filter_get_jitter_step(uint32_t *step)
     *step = RTCCNTL.touch_filter_ctrl.touch_jitter_step;
 }
 
-/**
- * Enable touch sensor filter and detection algorithm.
- * For more details on the detection algorithm, please refer to the application documentation.
- */
-static inline void touch_ll_filter_enable(void)
-{
-    RTCCNTL.touch_filter_ctrl.touch_filter_en = 1;
-}
-
-/**
- * Disable touch sensor filter and detection algorithm.
- * For more details on the detection algorithm, please refer to the application documentation.
- */
-static inline void touch_ll_filter_disable(void)
-{
-    RTCCNTL.touch_filter_ctrl.touch_filter_en = 0;
-}
-
 /************************ Denoise register setting ************************/
 
-/**
- * Enable denoise function.
- * T0 is an internal channel that does not have a corresponding external GPIO.
- * T0 will work simultaneously with the measured channel Tn. Finally, the actual
- * measured value of Tn is the value after subtracting lower bits of T0.
- * This denoise function filters out interference introduced on all channels,
- * such as noise introduced by the power supply and external EMI.
- */
-static inline void touch_ll_denoise_enable(void)
-{
-    RTCCNTL.touch_scan_ctrl.touch_denoise_en = 1;
-}
-
-/**
- * Enable denoise function.
- * T0 is an internal channel that does not have a corresponding external GPIO.
- * T0 will work simultaneously with the measured channel Tn. Finally, the actual
- * measured value of Tn is the value after subtracting lower bits of T0.
- * This denoise function filters out interference introduced on all channels,
- * such as noise introduced by the power supply and external EMI.
- */
-static inline void touch_ll_denoise_disable(void)
-{
-    RTCCNTL.touch_scan_ctrl.touch_denoise_en = 0;
-}
-
 /**
  * Set internal reference capacitance of denoise channel.
  * Select the appropriate internal reference capacitance value so that
@@ -907,16 +1531,6 @@ static inline void touch_ll_denoise_get_grade(touch_pad_denoise_grade_t *grade)
     *grade = (touch_pad_denoise_grade_t)(RTCCNTL.touch_scan_ctrl.touch_denoise_res);
 }
 
-/**
- * Read denoise measure value (TOUCH_PAD_NUM0).
- *
- * @param denoise value of denoise.
- */
-static inline void touch_ll_denoise_read_data(uint32_t *data)
-{
-    *data =  SENS.sar_touch_denoise.touch_denoise_data;
-}
-
 /************************ Waterproof register setting ************************/
 
 /**
@@ -939,18 +1553,6 @@ static inline void touch_ll_waterproof_get_guard_pad(touch_pad_t *pad_num)
     *pad_num = (touch_pad_t)(RTCCNTL.touch_scan_ctrl.touch_out_ring);
 }
 
-/**
- * Set max equivalent capacitance for shield channel.
- * The equivalent capacitance of the shielded channel can be calculated
- * from the reading of denoise channel.
- *
- * @param pad_num Touch sensor channel number.
- */
-static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver_t driver_level)
-{
-    RTCCNTL.touch_scan_ctrl.touch_bufdrv = driver_level;
-}
-
 /**
  * Get max equivalent capacitance for shield channel.
  * The equivalent capacitance of the shielded channel can be calculated
@@ -958,32 +1560,11 @@ static inline void touch_ll_waterproof_set_sheild_driver(touch_pad_shield_driver
  *
  * @param pad_num Touch sensor channel number.
  */
-static inline void touch_ll_waterproof_get_sheild_driver(touch_pad_shield_driver_t *driver_level)
+static inline void touch_ll_waterproof_get_shield_driver(touch_pad_shield_driver_t *driver_level)
 {
     *driver_level = (touch_pad_shield_driver_t)(RTCCNTL.touch_scan_ctrl.touch_bufdrv);
 }
 
-/**
- * Enable parameter of waterproof function.
- *
- * The waterproof function includes a shielded channel (TOUCH_PAD_NUM14) and a guard channel.
- * Guard pad is used to detect the large area of water covering the touch panel.
- * Shield pad is used to shield the influence of water droplets covering the touch panel.
- * It is generally designed as a grid and is placed around the touch buttons.
- */
-static inline void touch_ll_waterproof_enable(void)
-{
-    RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 1;
-}
-
-/**
- * Disable parameter of waterproof function.
- */
-static inline void touch_ll_waterproof_disable(void)
-{
-    RTCCNTL.touch_scan_ctrl.touch_shield_pad_en = 0;
-}
-
 /************************ Proximity register setting ************************/
 
 /**
@@ -1040,11 +1621,11 @@ static inline void touch_ll_proximity_get_meas_times(uint32_t *times)
 static inline void touch_ll_proximity_read_meas_cnt(touch_pad_t touch_num, uint32_t *cnt)
 {
     if (SENS.sar_touch_conf.touch_approach_pad0 == touch_num) {
-        *cnt = SENS.sar_touch_appr_status.touch_approach_pad0_cnt;
+        *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad0_cnt);
     } else if (SENS.sar_touch_conf.touch_approach_pad1 == touch_num) {
-        *cnt = SENS.sar_touch_appr_status.touch_approach_pad1_cnt;
+        *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad1_cnt);
     } else if (SENS.sar_touch_conf.touch_approach_pad2 == touch_num) {
-        *cnt = SENS.sar_touch_appr_status.touch_approach_pad2_cnt;
+        *cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_approach_pad2_cnt);
     }
 }
 
@@ -1065,18 +1646,6 @@ static inline bool touch_ll_proximity_pad_check(touch_pad_t touch_num)
 }
 
 /************** sleep pad setting ***********************/
-
-/**
- * Set touch channel number for sleep pad.
- *
- * @note Only one touch sensor channel is supported in deep sleep mode.
- * @param touch_num Touch sensor channel number.
- */
-static inline void touch_ll_sleep_set_channel_num(touch_pad_t touch_num)
-{
-    RTCCNTL.touch_slp_thres.touch_slp_pad = touch_num;
-}
-
 /**
  * Get touch channel number for sleep pad.
  *
@@ -1088,18 +1657,6 @@ static inline void touch_ll_sleep_get_channel_num(touch_pad_t *touch_num)
     *touch_num = (touch_pad_t)(RTCCNTL.touch_slp_thres.touch_slp_pad);
 }
 
-/**
- * Set the trigger threshold of touch sensor in deep sleep.
- * The threshold determines the sensitivity of the touch sensor.
- * The threshold is the original value of the trigger state minus the benchmark value.
- *
- * @note In general, the touch threshold during sleep can use the threshold parameter parameters before sleep.
- */
-static inline void touch_ll_sleep_set_threshold(uint32_t touch_thres)
-{
-    RTCCNTL.touch_slp_thres.touch_slp_th = touch_thres;
-}
-
 /**
  * Get the trigger threshold of touch sensor in deep sleep.
  * The threshold determines the sensitivity of the touch sensor.
@@ -1112,22 +1669,6 @@ static inline void touch_ll_sleep_get_threshold(uint32_t *touch_thres)
     *touch_thres = RTCCNTL.touch_slp_thres.touch_slp_th;
 }
 
-/**
- * Enable proximity function for sleep pad.
- */
-static inline void touch_ll_sleep_enable_proximity_sensing(void)
-{
-    RTCCNTL.touch_slp_thres.touch_slp_approach_en = 1;
-}
-
-/**
- * Disable proximity function for sleep pad.
- */
-static inline void touch_ll_sleep_disable_proximity_sensing(void)
-{
-    RTCCNTL.touch_slp_thres.touch_slp_approach_en = 0;
-}
-
 /**
  * Get proximity function status for sleep pad.
  */
@@ -1161,10 +1702,6 @@ static inline void touch_ll_sleep_read_data(uint32_t *raw_data)
     *raw_data = SENS.sar_touch_status[touch_num - 1].touch_pad_data;
 }
 
-static inline void touch_ll_sleep_reset_benchmark(void)
-{
-    RTCCNTL.touch_approach.touch_slp_channel_clr = 1;
-}
 
 /**
  * Select touch sensor dbias to save power in sleep mode.
@@ -1192,7 +1729,7 @@ static inline void touch_ll_sleep_read_debounce(uint32_t *debounce)
  */
 static inline void touch_ll_sleep_read_proximity_cnt(uint32_t *prox_cnt)
 {
-    *prox_cnt = SENS.sar_touch_appr_status.touch_slp_approach_cnt;
+    *prox_cnt = HAL_FORCE_READ_U32_REG_FIELD(SENS.sar_touch_appr_status, touch_slp_approach_cnt);
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h
index ceaa3e246f9..91cebea9a42 100644
--- a/components/hal/esp32s3/include/hal/uart_ll.h
+++ b/components/hal/esp32s3/include/hal/uart_ll.h
@@ -601,8 +601,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
         hw->flow_conf.sw_flow_con_en = 1;
         hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
         hw->swfc_conf0.xoff_threshold = flow_ctrl->xoff_thrd;
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_char, flow_ctrl->xon_char);
-        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_char, flow_ctrl->xoff_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_character, flow_ctrl->xon_char);
+        HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0, xoff_character, flow_ctrl->xoff_char);
     } else {
         hw->flow_conf.sw_flow_con_en = 0;
         hw->flow_conf.xonoff_del = 0;
@@ -624,8 +624,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
  */
 FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, at_cmd_char, cmd_char->cmd_char);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, at_char_num, cmd_char->char_num);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_postcnt, post_idle_num, cmd_char->post_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_precnt, pre_idle_num, cmd_char->pre_idle);
     HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_gaptout, rx_gap_tout, cmd_char->gap_tout);
@@ -824,8 +824,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
  */
 FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
 {
-    *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, at_cmd_char);
-    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
+    *cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
+    *char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, at_char_num);
 }
 
 /**
diff --git a/components/hal/esp32s3/include/hal/usb_dwc_ll.h b/components/hal/esp32s3/include/hal/usb_dwc_ll.h
new file mode 100644
index 00000000000..7426be2efa7
--- /dev/null
+++ b/components/hal/esp32s3/include/hal/usb_dwc_ll.h
@@ -0,0 +1,983 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/usb_dwc_struct.h"
+#include "soc/usb_dwc_cfg.h"
+#include "hal/usb_dwc_types.h"
+#include "hal/misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ----------------------------- Helper Macros ------------------------------ */
+
+// Get USB hardware instance
+#define USB_DWC_LL_GET_HW(num) (&USB_DWC)
+
+/* -----------------------------------------------------------------------------
+--------------------------------- DWC Constants --------------------------------
+----------------------------------------------------------------------------- */
+
+#define USB_DWC_QTD_LIST_MEM_ALIGN              512
+#define USB_DWC_FRAME_LIST_MEM_ALIGN            512     // The frame list needs to be 512 bytes aligned (contrary to the databook)
+
+/* -----------------------------------------------------------------------------
+------------------------------- Global Registers -------------------------------
+----------------------------------------------------------------------------- */
+
+/*
+ * Interrupt bit masks of the GINTSTS and GINTMSK registers
+ */
+#define USB_DWC_LL_INTR_CORE_WKUPINT        (1 << 31)
+#define USB_DWC_LL_INTR_CORE_SESSREQINT     (1 << 30)
+#define USB_DWC_LL_INTR_CORE_DISCONNINT     (1 << 29)
+#define USB_DWC_LL_INTR_CORE_CONIDSTSCHNG   (1 << 28)
+#define USB_DWC_LL_INTR_CORE_PTXFEMP        (1 << 26)
+#define USB_DWC_LL_INTR_CORE_HCHINT         (1 << 25)
+#define USB_DWC_LL_INTR_CORE_PRTINT         (1 << 24)
+#define USB_DWC_LL_INTR_CORE_RESETDET       (1 << 23)
+#define USB_DWC_LL_INTR_CORE_FETSUSP        (1 << 22)
+#define USB_DWC_LL_INTR_CORE_INCOMPIP       (1 << 21)
+#define USB_DWC_LL_INTR_CORE_INCOMPISOIN    (1 << 20)
+#define USB_DWC_LL_INTR_CORE_OEPINT         (1 << 19)
+#define USB_DWC_LL_INTR_CORE_IEPINT         (1 << 18)
+#define USB_DWC_LL_INTR_CORE_EPMIS          (1 << 17)
+#define USB_DWC_LL_INTR_CORE_EOPF           (1 << 15)
+#define USB_DWC_LL_INTR_CORE_ISOOUTDROP     (1 << 14)
+#define USB_DWC_LL_INTR_CORE_ENUMDONE       (1 << 13)
+#define USB_DWC_LL_INTR_CORE_USBRST         (1 << 12)
+#define USB_DWC_LL_INTR_CORE_USBSUSP        (1 << 11)
+#define USB_DWC_LL_INTR_CORE_ERLYSUSP       (1 << 10)
+#define USB_DWC_LL_INTR_CORE_GOUTNAKEFF     (1 << 7)
+#define USB_DWC_LL_INTR_CORE_GINNAKEFF      (1 << 6)
+#define USB_DWC_LL_INTR_CORE_NPTXFEMP       (1 << 5)
+#define USB_DWC_LL_INTR_CORE_RXFLVL         (1 << 4)
+#define USB_DWC_LL_INTR_CORE_SOF            (1 << 3)
+#define USB_DWC_LL_INTR_CORE_OTGINT         (1 << 2)
+#define USB_DWC_LL_INTR_CORE_MODEMIS        (1 << 1)
+#define USB_DWC_LL_INTR_CORE_CURMOD         (1 << 0)
+
+/*
+ * Bit mask of interrupt generating bits of the the HPRT register. These bits
+ * are ORd into the USB_DWC_LL_INTR_CORE_PRTINT interrupt.
+ *
+ * Note: Some fields of the HPRT are W1C (write 1 clear), this we cannot do a
+ * simple read and write-back to clear the HPRT interrupt bits. Instead we need
+ * a W1C mask the non-interrupt related bits
+ */
+#define USB_DWC_LL_HPRT_W1C_MSK             (0x2E)
+#define USB_DWC_LL_HPRT_ENA_MSK             (0x04)
+#define USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG (1 << 5)
+#define USB_DWC_LL_INTR_HPRT_PRTENCHNG      (1 << 3)
+#define USB_DWC_LL_INTR_HPRT_PRTCONNDET     (1 << 1)
+
+/*
+ * Bit mask of channel interrupts (HCINTi and HCINTMSKi registers)
+ *
+ * Note: Under Scatter/Gather DMA mode, only the following interrupts can be unmasked
+ * - DESC_LS_ROLL
+ * - XCS_XACT_ERR (always unmasked)
+ * - BNAINTR
+ * - CHHLTD
+ * - XFERCOMPL
+ * The remaining interrupt bits will still be set (when the corresponding event occurs)
+ * but will not generate an interrupt. Therefore we must proxy through the
+ * USB_DWC_LL_INTR_CHAN_CHHLTD interrupt to check the other interrupt bits.
+ */
+#define USB_DWC_LL_INTR_CHAN_DESC_LS_ROLL   (1 << 13)
+#define USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR   (1 << 12)
+#define USB_DWC_LL_INTR_CHAN_BNAINTR        (1 << 11)
+#define USB_DWC_LL_INTR_CHAN_DATATGLERR     (1 << 10)
+#define USB_DWC_LL_INTR_CHAN_FRMOVRUN       (1 << 9)
+#define USB_DWC_LL_INTR_CHAN_BBLEER         (1 << 8)
+#define USB_DWC_LL_INTR_CHAN_XACTERR        (1 << 7)
+#define USB_DWC_LL_INTR_CHAN_NYET           (1 << 6)
+#define USB_DWC_LL_INTR_CHAN_ACK            (1 << 5)
+#define USB_DWC_LL_INTR_CHAN_NAK            (1 << 4)
+#define USB_DWC_LL_INTR_CHAN_STALL          (1 << 3)
+#define USB_DWC_LL_INTR_CHAN_AHBERR         (1 << 2)
+#define USB_DWC_LL_INTR_CHAN_CHHLTD         (1 << 1)
+#define USB_DWC_LL_INTR_CHAN_XFERCOMPL      (1 << 0)
+
+/*
+ * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
+ * Each QTD describes one transfer. Scatter gather mode will automatically split
+ * a transfer into multiple MPS packets. Each QTD is 64bits in size
+ *
+ * Note: The status information part of the QTD is interpreted differently depending
+ * on IN or OUT, and ISO or non-ISO
+ */
+typedef struct {
+    union {
+        struct {
+            uint32_t xfer_size: 17;
+            uint32_t aqtd_offset: 6;
+            uint32_t aqtd_valid: 1;
+            uint32_t reserved_24: 1;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t rx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } in_non_iso;
+        struct {
+            uint32_t xfer_size: 12;
+            uint32_t reserved_12_24: 13;
+            uint32_t intr_cplt: 1;
+            uint32_t reserved_26_27: 2;
+            uint32_t rx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } in_iso;
+        struct {
+            uint32_t xfer_size: 17;
+            uint32_t reserved_17_23: 7;
+            uint32_t is_setup: 1;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t tx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } out_non_iso;
+        struct {
+            uint32_t xfer_size: 12;
+            uint32_t reserved_12_24: 13;
+            uint32_t intr_cplt: 1;
+            uint32_t eol: 1;
+            uint32_t reserved_27: 1;
+            uint32_t tx_status: 2;
+            uint32_t reserved_30: 1;
+            uint32_t active: 1;
+        } out_iso;
+        uint32_t buffer_status_val;
+    };
+    uint8_t *buffer;
+} usb_dwc_ll_dma_qtd_t;
+
+
+/* -----------------------------------------------------------------------------
+------------------------------- Global Registers -------------------------------
+----------------------------------------------------------------------------- */
+
+// --------------------------- GAHBCFG Register --------------------------------
+
+static inline void usb_dwc_ll_gahbcfg_en_dma_mode(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.dmaen = 1;
+}
+
+static inline void usb_dwc_ll_gahbcfg_en_slave_mode(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.dmaen = 0;
+}
+
+static inline void usb_dwc_ll_gahbcfg_set_hbstlen(usb_dwc_dev_t *hw, uint32_t burst_len)
+{
+    hw->gahbcfg_reg.hbstlen = burst_len;
+}
+
+static inline void usb_dwc_ll_gahbcfg_en_global_intr(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.glbllntrmsk = 1;
+}
+
+static inline void usb_dwc_ll_gahbcfg_dis_global_intr(usb_dwc_dev_t *hw)
+{
+    hw->gahbcfg_reg.glbllntrmsk = 0;
+}
+
+// --------------------------- GUSBCFG Register --------------------------------
+
+static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.forcehstmode = 1;
+}
+
+static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.hnpcap = 0;
+}
+
+static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.srpcap = 0;
+}
+
+static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
+{
+    hw->gusbcfg_reg.toutcal = tout_cal;
+}
+
+static inline void usb_dwc_ll_gusbcfg_set_utmi_phy(usb_dwc_dev_t *hw)
+{
+    hw->gusbcfg_reg.phyif = 1;       // 16 bits interface
+    hw->gusbcfg_reg.ulpiutmisel = 0; // UTMI+
+    hw->gusbcfg_reg.physel = 0;      // HS PHY
+}
+
+// --------------------------- GRSTCTL Register --------------------------------
+
+static inline bool usb_dwc_ll_grstctl_is_ahb_idle(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.ahbidle;
+}
+
+static inline bool usb_dwc_ll_grstctl_is_dma_req_in_progress(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.dmareq;
+}
+
+static inline void usb_dwc_ll_grstctl_flush_nptx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.txfnum = 0;     //Set the TX FIFO number to 0 to select the non-periodic TX FIFO
+    hw->grstctl_reg.txfflsh = 1;    //Flush the selected TX FIFO
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.txfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_flush_ptx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.txfnum = 1;     //Set the TX FIFO number to 1 to select the periodic TX FIFO
+    hw->grstctl_reg.txfflsh = 1;    //FLush the select TX FIFO
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.txfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_flush_rx_fifo(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.rxfflsh = 1;
+    //Wait for the flushing to complete
+    while (hw->grstctl_reg.rxfflsh) {
+        ;
+    }
+}
+
+static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.frmcntrrst = 1;
+}
+
+static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw)
+{
+    hw->grstctl_reg.csftrst = 1;
+}
+
+static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw)
+{
+    return hw->grstctl_reg.csftrst;
+}
+
+// --------------------------- GINTSTS Register --------------------------------
+
+/**
+ * @brief Reads and clears the global interrupt register
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @return uint32_t Mask of interrupts
+ */
+static inline uint32_t usb_dwc_ll_gintsts_read_and_clear_intrs(usb_dwc_dev_t *hw)
+{
+    usb_dwc_gintsts_reg_t gintsts;
+    gintsts.val = hw->gintsts_reg.val;
+    hw->gintsts_reg.val = gintsts.val;  //Write back to clear
+    return gintsts.val;
+}
+
+/**
+ * @brief Clear specific interrupts
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @param intr_msk Mask of interrupts to clear
+ */
+static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t intr_msk)
+{
+    //All GINTSTS fields are either W1C or read only. So safe to write directly
+    hw->gintsts_reg.val = intr_msk;
+}
+
+// --------------------------- GINTMSK Register --------------------------------
+
+static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    hw->gintmsk_reg.val |= intr_mask;
+}
+
+static inline void usb_dwc_ll_gintmsk_dis_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    hw->gintmsk_reg.val &= ~intr_mask;
+}
+
+// --------------------------- GRXFSIZ Register --------------------------------
+
+static inline void usb_dwc_ll_grxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t num_lines)
+{
+    //Set size in words
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->grxfsiz_reg, rxfdep, num_lines);
+}
+
+// -------------------------- GNPTXFSIZ Register -------------------------------
+
+static inline void usb_dwc_ll_gnptxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
+{
+    usb_dwc_gnptxfsiz_reg_t gnptxfsiz;
+    gnptxfsiz.val = hw->gnptxfsiz_reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfstaddr, addr);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfdep, num_lines);
+    hw->gnptxfsiz_reg.val = gnptxfsiz.val;
+}
+
+// --------------------------- GSNPSID Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
+{
+    return hw->gsnpsid_reg.val;
+}
+
+// --------------------------- GHWCFGx Register --------------------------------
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg3_reg.dfifodepth;
+}
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg2_reg.hsphytype;
+}
+
+static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
+{
+    return hw->ghwcfg2_reg.numhstchnl;
+}
+
+// --------------------------- HPTXFSIZ Register -------------------------------
+
+static inline void usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
+{
+    usb_dwc_hptxfsiz_reg_t hptxfsiz;
+    hptxfsiz.val = hw->hptxfsiz_reg.val;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfstaddr, addr);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfsize, num_lines);
+    hw->hptxfsiz_reg.val = hptxfsiz.val;
+}
+
+/* -----------------------------------------------------------------------------
+-------------------------------- Host Registers --------------------------------
+----------------------------------------------------------------------------- */
+
+// ----------------------------- HCFG Register ---------------------------------
+
+static inline void usb_dwc_ll_hcfg_en_perio_sched(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.perschedena = 1;
+}
+
+static inline void usb_dwc_ll_hcfg_dis_perio_sched(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.perschedena = 0;
+}
+
+/**
+ * Sets the length of the frame list
+ *
+ * @param num_entires Number of entries in the frame list
+ */
+static inline void usb_dwc_ll_hcfg_set_num_frame_list_entries(usb_dwc_dev_t *hw, usb_hal_frame_list_len_t num_entries)
+{
+    uint32_t frlisten;
+    switch (num_entries) {
+        case USB_HAL_FRAME_LIST_LEN_8:
+            frlisten = 0;
+            break;
+        case USB_HAL_FRAME_LIST_LEN_16:
+            frlisten = 1;
+            break;
+        case USB_HAL_FRAME_LIST_LEN_32:
+            frlisten = 2;
+            break;
+        default: //USB_HAL_FRAME_LIST_LEN_64
+            frlisten = 3;
+            break;
+    }
+    hw->hcfg_reg.frlisten = frlisten;
+}
+
+static inline void usb_dwc_ll_hcfg_en_scatt_gatt_dma(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.descdma = 1;
+}
+
+static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw)
+{
+    hw->hcfg_reg.fslssupp = 1;
+}
+
+/**
+ * @brief Set FSLS PHY clock
+ *
+ * @attention This function should only be called if FSLS PHY is selected
+ * @param[in] hw    Start address of the DWC_OTG registers
+ */
+static inline void usb_dwc_ll_hcfg_set_fsls_phy_clock(usb_dwc_dev_t *hw)
+{
+    /*
+    Indicate to the OTG core what speed the PHY clock is at
+    Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
+          so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
+    */
+    usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+    hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2;
+}
+
+// ----------------------------- HFIR Register ---------------------------------
+
+/**
+ * @brief Set Frame Interval
+ *
+ * @attention This function should only be called if FSLS PHY is selected
+ * @param[in] hw    Start address of the DWC_OTG registers
+ */
+static inline void usb_dwc_ll_hfir_set_frame_interval(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hfir_reg_t hfir;
+    hfir.val = hw->hfir_reg.val;
+    hfir.hfirrldctrl = 0;       // Disable dynamic loading
+    /*
+    Set frame interval to be equal to 1ms
+    Note: FSLS PHY has an implicit 8 divider applied when in LS mode,
+          so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
+    */
+    usb_dwc_speed_t speed = (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+    hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000;
+    hw->hfir_reg.val = hfir.val;
+}
+
+// ----------------------------- HFNUM Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_hfnum_get_frame_time_rem(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hfnum_reg, frrem);
+}
+
+static inline uint32_t usb_dwc_ll_hfnum_get_frame_num(usb_dwc_dev_t *hw)
+{
+    return hw->hfnum_reg.frnum;
+}
+
+// ---------------------------- HPTXSTS Register -------------------------------
+
+static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_top(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxqtop);
+}
+
+static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_space_avail(usb_dwc_dev_t *hw)
+{
+    return hw->hptxsts_reg.ptxqspcavail;
+}
+
+static inline uint32_t usb_dwc_ll_ptxsts_get_ptxf_space_avail(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxfspcavail);
+}
+
+// ----------------------------- HAINT Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_haint_get_chan_intrs(usb_dwc_dev_t *hw)
+{
+    return HAL_FORCE_READ_U32_REG_FIELD(hw->haint_reg, haint);
+}
+
+// --------------------------- HAINTMSK Register -------------------------------
+
+static inline void usb_dwc_ll_haintmsk_en_chan_intr(usb_dwc_dev_t *hw, uint32_t mask)
+{
+
+    hw->haintmsk_reg.val |= mask;
+}
+
+static inline void usb_dwc_ll_haintmsk_dis_chan_intr(usb_dwc_dev_t *hw, uint32_t mask)
+{
+    hw->haintmsk_reg.val &= ~mask;
+}
+
+// --------------------------- HFLBAddr Register -------------------------------
+
+/**
+ * @brief Set the base address of the scheduling frame list
+ *
+ * @note For some reason, this address must be 512 bytes aligned or else a bunch of frames will not be scheduled when
+ *       the frame list rolls over. However, according to the databook, there is no mention of the HFLBAddr needing to
+ *       be aligned.
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @param addr Base address of the scheduling frame list
+ */
+static inline void usb_dwc_ll_hflbaddr_set_base_addr(usb_dwc_dev_t *hw, uint32_t addr)
+{
+    hw->hflbaddr_reg.hflbaddr = addr;
+}
+
+/**
+ * @brief Get the base address of the scheduling frame list
+ *
+ * @param hw Start address of the DWC_OTG registers
+ * @return uint32_t Base address of the scheduling frame list
+ */
+static inline uint32_t usb_dwc_ll_hflbaddr_get_base_addr(usb_dwc_dev_t *hw)
+{
+    return hw->hflbaddr_reg.hflbaddr;
+}
+
+// ----------------------------- HPRT Register ---------------------------------
+
+static inline usb_dwc_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw)
+{
+    return (usb_dwc_speed_t)hw->hprt_reg.prtspd;
+}
+
+static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prttstctl;
+}
+
+static inline void usb_dwc_ll_hprt_set_test_ctl(usb_dwc_dev_t *hw, uint32_t test_mode)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prttstctl = test_mode;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_en_pwr(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtpwr = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_dis_pwr(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtpwr = 0;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline uint32_t usb_dwc_ll_hprt_get_pwr_line_status(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtlnsts;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_reset(usb_dwc_dev_t *hw, bool reset)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtrst = reset;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_reset(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtrst;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_suspend(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtsusp = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_suspend(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtsusp;
+}
+
+static inline void usb_dwc_ll_hprt_set_port_resume(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtres = 1;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline void usb_dwc_ll_hprt_clr_port_resume(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtres = 0;
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_resume(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtres;
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_overcur(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtovrcurract;
+}
+
+static inline bool usb_dwc_ll_hprt_get_port_en(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtena;
+}
+
+static inline void usb_dwc_ll_hprt_port_dis(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hprt.prtena = 1;        //W1C to disable
+    //we want to W1C ENA but not W1C the interrupt bits
+    hw->hprt_reg.val = hprt.val & ((~USB_DWC_LL_HPRT_W1C_MSK) | USB_DWC_LL_HPRT_ENA_MSK);
+}
+
+static inline bool usb_dwc_ll_hprt_get_conn_status(usb_dwc_dev_t *hw)
+{
+    return hw->hprt_reg.prtconnsts;
+}
+
+static inline uint32_t usb_dwc_ll_hprt_intr_read_and_clear(usb_dwc_dev_t *hw)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    //We want to W1C the interrupt bits but not that ENA
+    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_ENA_MSK);
+    //Return only the interrupt bits
+    return (hprt.val & (USB_DWC_LL_HPRT_W1C_MSK & ~(USB_DWC_LL_HPRT_ENA_MSK)));
+}
+
+static inline void usb_dwc_ll_hprt_intr_clear(usb_dwc_dev_t *hw, uint32_t intr_mask)
+{
+    usb_dwc_hprt_reg_t hprt;
+    hprt.val = hw->hprt_reg.val;
+    hw->hprt_reg.val = ((hprt.val & ~USB_DWC_LL_HPRT_ENA_MSK) & ~USB_DWC_LL_HPRT_W1C_MSK) | intr_mask;
+}
+
+//Per Channel registers
+
+// --------------------------- HCCHARi Register --------------------------------
+
+static inline void usb_dwc_ll_hcchar_enable_chan(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.chena = 1;
+}
+
+static inline bool usb_dwc_ll_hcchar_chan_is_enabled(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    return chan->hcchar_reg.chena;
+}
+
+static inline void usb_dwc_ll_hcchar_disable_chan(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.chdis = 1;
+}
+
+static inline void usb_dwc_ll_hcchar_set_odd_frame(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.oddfrm = 1;
+}
+
+static inline void usb_dwc_ll_hcchar_set_even_frame(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    chan->hcchar_reg.oddfrm = 0;
+}
+
+static inline void usb_dwc_ll_hcchar_set_dev_addr(volatile usb_dwc_host_chan_regs_t *chan, uint32_t addr)
+{
+    chan->hcchar_reg.devaddr = addr;
+}
+
+static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_dwc_xfer_type_t type)
+{
+    chan->hcchar_reg.eptype = (uint32_t)type;
+}
+
+//Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause
+//each packet to be preceded by a PREamble packet
+static inline void usb_dwc_ll_hcchar_set_lspddev(volatile usb_dwc_host_chan_regs_t *chan, bool is_ls)
+{
+    chan->hcchar_reg.lspddev = is_ls;
+}
+
+static inline void usb_dwc_ll_hcchar_set_dir(volatile usb_dwc_host_chan_regs_t *chan, bool is_in)
+{
+    chan->hcchar_reg.epdir = is_in;
+}
+
+static inline void usb_dwc_ll_hcchar_set_ep_num(volatile usb_dwc_host_chan_regs_t *chan, uint32_t num)
+{
+    chan->hcchar_reg.epnum = num;
+}
+
+static inline void usb_dwc_ll_hcchar_set_mps(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mps)
+{
+    chan->hcchar_reg.mps = mps;
+}
+
+static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_dwc_xfer_type_t type, bool is_in, bool is_ls)
+{
+    //Sets all persistent fields of the channel over its lifetimez
+    usb_dwc_ll_hcchar_set_dev_addr(chan, dev_addr);
+    usb_dwc_ll_hcchar_set_ep_type(chan, type);
+    usb_dwc_ll_hcchar_set_lspddev(chan, is_ls);
+    usb_dwc_ll_hcchar_set_dir(chan, is_in);
+    usb_dwc_ll_hcchar_set_ep_num(chan, ep_num);
+    usb_dwc_ll_hcchar_set_mps(chan, mps);
+}
+
+// ---------------------------- HCINTi Register --------------------------------
+
+static inline uint32_t usb_dwc_ll_hcint_read_and_clear_intrs(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    usb_dwc_hcint_reg_t hcint;
+    hcint.val = chan->hcint_reg.val;
+    chan->hcint_reg.val = hcint.val;
+    return hcint.val;
+}
+
+// --------------------------- HCINTMSKi Register ------------------------------
+
+static inline void usb_dwc_ll_hcintmsk_set_intr_mask(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mask)
+{
+    chan->hcintmsk_reg.val = mask;
+}
+
+// ---------------------------- HCTSIZi Register -------------------------------
+
+static inline void usb_dwc_ll_hctsiz_set_pid(volatile usb_dwc_host_chan_regs_t *chan, uint32_t data_pid)
+{
+    if (data_pid == 0) {
+        chan->hctsiz_reg.pid = 0;
+    } else {
+        chan->hctsiz_reg.pid = 2;
+    }
+}
+
+static inline uint32_t usb_dwc_ll_hctsiz_get_pid(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    if (chan->hctsiz_reg.pid == 0) {
+        return 0;   //DATA0
+    } else {
+        return 1;   //DATA1
+    }
+}
+
+static inline void usb_dwc_ll_hctsiz_set_qtd_list_len(volatile usb_dwc_host_chan_regs_t *chan, int qtd_list_len)
+{
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    //Set the length of the descriptor list. NTD occupies xfersize[15:8]
+    hctsiz.xfersize &= ~(0xFF << 8);
+    hctsiz.xfersize |= ((qtd_list_len - 1) & 0xFF) << 8;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    hctsiz.dopng = 0;         //Don't do ping
+    /*
+    Set SCHED_INFO which occupies xfersize[7:0]
+    It is always set to 0xFF for full speed and not used in Bulk/Ctrl channels
+    */
+    hctsiz.xfersize |= 0xFF;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+static inline void usb_dwc_ll_hctsiz_set_sched_info(volatile usb_dwc_host_chan_regs_t *chan, int tokens_per_frame, int offset)
+{
+    // @see USB-OTG databook: Table 5-47
+    // This function is relevant only for HS
+    usb_dwc_hctsiz_reg_t hctsiz;
+    hctsiz.val = chan->hctsiz_reg.val;
+    uint8_t sched_info_val;
+    switch (tokens_per_frame) {
+        case 1:
+            offset %= 8; // If the required offset > 8, we must wrap around to SCHED_INFO size = 8
+            sched_info_val = 0b00000001;
+            break;
+        case 2:
+            offset %= 4;
+            sched_info_val = 0b00010001;
+            break;
+        case 4:
+            offset %= 2;
+            sched_info_val = 0b01010101;
+            break;
+        case 8:
+            offset = 0;
+            sched_info_val = 0b11111111;
+            break;
+        default:
+            abort();
+            break;
+    }
+    sched_info_val <<= offset;
+    hctsiz.xfersize &= ~(0xFF);
+    hctsiz.xfersize |= sched_info_val;
+    chan->hctsiz_reg.val = hctsiz.val;
+}
+
+// ---------------------------- HCDMAi Register --------------------------------
+
+static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx)
+{
+    usb_dwc_hcdma_reg_t hcdma;
+    /*
+    Set the base address portion of the field which is dmaaddr[31:9]. This is
+    the based address of the QTD list and must be 512 bytes aligned
+    */
+    hcdma.dmaaddr = ((uint32_t)dmaaddr) & 0xFFFFFE00;
+    //Set the current QTD index in the QTD list which is dmaaddr[8:3]
+    hcdma.dmaaddr |= (qtd_idx & 0x3F) << 3;
+    //dmaaddr[2:0] is reserved thus doesn't not need to be set
+
+    chan->hcdma_reg.val = hcdma.val;
+}
+
+static inline int usb_dwc_ll_hcdam_get_cur_qtd_idx(usb_dwc_host_chan_regs_t *chan)
+{
+    //The current QTD index is dmaaddr[8:3]
+    return (chan->hcdma_reg.dmaaddr >> 3) & 0x3F;
+}
+
+// ---------------------------- HCDMABi Register -------------------------------
+
+static inline void *usb_dwc_ll_hcdmab_get_buff_addr(volatile usb_dwc_host_chan_regs_t *chan)
+{
+    return (void *)chan->hcdmab_reg.hcdmab;
+}
+
+/* -----------------------------------------------------------------------------
+---------------------------- Scatter/Gather DMA QTDs ---------------------------
+----------------------------------------------------------------------------- */
+
+// ---------------------------- Helper Functions -------------------------------
+
+/**
+ * @brief Get the base address of a channel's register based on the channel's index
+ *
+ * @param dev Start address of the DWC_OTG registers
+ * @param chan_idx The channel's index
+ * @return usb_dwc_host_chan_regs_t* Pointer to channel's registers
+ */
+static inline usb_dwc_host_chan_regs_t *usb_dwc_ll_chan_get_regs(usb_dwc_dev_t *dev, int chan_idx)
+{
+    return &dev->host_chans[chan_idx];
+}
+
+// ------------------------------ QTD related ----------------------------------
+
+#define USB_DWC_LL_QTD_STATUS_SUCCESS      0x0     //If QTD was processed, it indicates the data was transmitted/received successfully
+#define USB_DWC_LL_QTD_STATUS_PKTERR       0x1     //Data transmitted/received with errors (CRC/Timeout/Stuff/False EOP/Excessive NAK).
+//Note: 0x2 is reserved
+#define USB_DWC_LL_QTD_STATUS_BUFFER       0x3     //AHB error occurred.
+#define USB_DWC_LL_QTD_STATUS_NOT_EXECUTED 0x4     //QTD as never processed
+
+/**
+ * @brief Set a QTD for a non isochronous IN transfer
+ *
+ * @param qtd Pointer to the QTD
+ * @param data_buff Pointer to buffer containing the data to transfer
+ * @param xfer_len Number of bytes in transfer. Setting 0 will do a zero length IN transfer.
+ *                 Non zero length must be multiple of the endpoint's MPS.
+ * @param hoc Halt on complete (will generate an interrupt and halt the channel)
+ */
+static inline void usb_dwc_ll_qtd_set_in(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc)
+{
+    qtd->buffer = data_buff;        //Set pointer to data buffer
+    qtd->buffer_status_val = 0;     //Reset all flags to zero
+    qtd->in_non_iso.xfer_size = xfer_len;
+    if (hoc) {
+        qtd->in_non_iso.intr_cplt = 1;  //We need to set this to distinguish between a halt due to a QTD
+        qtd->in_non_iso.eol = 1;        //Used to halt the channel at this qtd
+    }
+    qtd->in_non_iso.active = 1;
+}
+
+/**
+ * @brief Set a QTD for a non isochronous OUT transfer
+ *
+ * @param qtd Pointer to the QTD
+ * @param data_buff Pointer to buffer containing the data to transfer
+ * @param xfer_len Number of bytes to transfer. Setting 0 will do a zero length transfer.
+ *                 For ctrl setup packets, this should be set to 8.
+ * @param hoc Halt on complete (will generate an interrupt)
+ * @param is_setup Indicates whether this is a control transfer setup packet or a normal OUT Data transfer.
+ *                 (As per the USB protocol, setup packets cannot be STALLd or NAKd by the device)
+ */
+static inline void usb_dwc_ll_qtd_set_out(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc, bool is_setup)
+{
+    qtd->buffer = data_buff;        //Set pointer to data buffer
+    qtd->buffer_status_val = 0;     //Reset all flags to zero
+    qtd->out_non_iso.xfer_size = xfer_len;
+    if (is_setup) {
+        qtd->out_non_iso.is_setup = 1;
+    }
+    if (hoc) {
+        qtd->in_non_iso.intr_cplt = 1;  //We need to set this to distinguish between a halt due to a QTD
+        qtd->in_non_iso.eol = 1;        //Used to halt the channel at this qtd
+    }
+    qtd->out_non_iso.active = 1;
+}
+
+/**
+ * @brief Set a QTD as NULL
+ *
+ * This sets the QTD to a value of 0. This is only useful when you need to insert
+ * blank QTDs into a list of QTDs
+ *
+ * @param qtd Pointer to the QTD
+ */
+static inline void usb_dwc_ll_qtd_set_null(usb_dwc_ll_dma_qtd_t *qtd)
+{
+    qtd->buffer = NULL;
+    qtd->buffer_status_val = 0;     //Disable qtd by clearing it to zero. Used by interrupt/isoc as an unscheudled frame
+}
+
+/**
+ * @brief Get the status of a QTD
+ *
+ * When a channel gets halted, call this to check whether each QTD was executed successfully
+ *
+ * @param qtd Pointer to the QTD
+ * @param[out] rem_len Number of bytes ramining in the QTD
+ * @param[out] status Status of the QTD
+ */
+static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem_len, int *status)
+{
+    //Status is the same regardless of IN or OUT
+    if (qtd->in_non_iso.active) {
+        //QTD was never processed
+        *status = USB_DWC_LL_QTD_STATUS_NOT_EXECUTED;
+    } else {
+        *status = qtd->in_non_iso.rx_status;
+    }
+    *rem_len = qtd->in_non_iso.xfer_size;
+    //Clear the QTD just for safety
+    qtd->buffer_status_val = 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/esp32s3/touch_sensor_hal.c b/components/hal/esp32s3/touch_sensor_hal.c
index 83dcc05cd56..4ae025a5b0d 100644
--- a/components/hal/esp32s3/touch_sensor_hal.c
+++ b/components/hal/esp32s3/touch_sensor_hal.c
@@ -8,7 +8,8 @@
 
 #include "soc/soc_pins.h"
 #include "hal/touch_sensor_hal.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_ll.h"
+#include "hal/touch_sensor_legacy_types.h"
 #include "soc/soc_caps.h"
 
 static int s_sleep_cycle = -1;
@@ -48,12 +49,12 @@ void touch_hal_deinit(void)
     touch_ll_clear_trigger_status_mask();
     touch_ll_intr_disable(TOUCH_PAD_INTR_MASK_ALL);
     touch_ll_timeout_disable();
-    touch_ll_waterproof_disable();
-    touch_ll_denoise_disable();
+    touch_ll_waterproof_enable(false);
+    touch_ll_denoise_enable(false);
     touch_pad_t prox_pad[SOC_TOUCH_PROXIMITY_CHANNEL_NUM] = {[0 ... (SOC_TOUCH_PROXIMITY_CHANNEL_NUM - 1)] = 0};
     touch_ll_proximity_set_channel_num((const touch_pad_t *)prox_pad);
     touch_ll_sleep_set_channel_num(0);
-    touch_ll_sleep_disable_proximity_sensing();
+    touch_ll_sleep_enable_proximity_sensing(false);
     touch_ll_reset();   // Reset the touch sensor FSM.
 }
 
@@ -90,25 +91,25 @@ void touch_hal_denoise_get_config(touch_pad_denoise_t *denoise)
 void touch_hal_denoise_enable(void)
 {
     touch_ll_clear_channel_mask(1U << SOC_TOUCH_DENOISE_CHANNEL);
-    touch_ll_denoise_enable();
+    touch_ll_denoise_enable(true);
 }
 
 void touch_hal_waterproof_set_config(const touch_pad_waterproof_t *waterproof)
 {
     touch_ll_waterproof_set_guard_pad(waterproof->guard_ring_pad);
-    touch_ll_waterproof_set_sheild_driver(waterproof->shield_driver);
+    touch_ll_waterproof_set_shield_driver(waterproof->shield_driver);
 }
 
 void touch_hal_waterproof_get_config(touch_pad_waterproof_t *waterproof)
 {
     touch_ll_waterproof_get_guard_pad(&waterproof->guard_ring_pad);
-    touch_ll_waterproof_get_sheild_driver(&waterproof->shield_driver);
+    touch_ll_waterproof_get_shield_driver(&waterproof->shield_driver);
 }
 
 void touch_hal_waterproof_enable(void)
 {
     touch_ll_clear_channel_mask(1U << SOC_TOUCH_SHIELD_CHANNEL);
-    touch_ll_waterproof_enable();
+    touch_ll_waterproof_enable(true);
 }
 
 bool touch_hal_enable_proximity(touch_pad_t touch_num, bool enabled)
diff --git a/components/hal/include/hal/adc_hal.h b/components/hal/include/hal/adc_hal.h
index f237613327f..1953b317090 100644
--- a/components/hal/include/hal/adc_hal.h
+++ b/components/hal/include/hal/adc_hal.h
@@ -130,7 +130,7 @@ void adc_hal_dma_ctx_config(adc_hal_dma_ctx_t *hal, const adc_hal_dma_config_t *
  * Setting the digital controller.
  *
  * @param hal    Context of the HAL
- * @param cfg    Pointer to digital controller paramter.
+ * @param cfg    Pointer to digital controller parameter.
  */
 void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_ctrlr_cfg_t *cfg);
 
@@ -180,6 +180,17 @@ void adc_hal_digi_reset(void);
 void adc_hal_digi_clr_eof(void);
 #endif
 
+/**
+ * @brief Set ADC monitor with high and low thresholds, and will enable the interrupts accordingly
+ *
+ * @param monitor_id Monitor to configure
+ * @param adc_n Which ADC unit will be monitored
+ * @param adc_ch Which ADC channel will be monitored
+ * @param h_thres High threshold (disable if < 0)
+ * @param l_thres Low threshold (disable if < 0)
+ */
+void adc_hal_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t adc_ch, int32_t h_thres, int32_t l_thres);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/include/hal/adc_types.h b/components/hal/include/hal/adc_types.h
index 86600475799..a96fe36f855 100644
--- a/components/hal/include/hal/adc_types.h
+++ b/components/hal/include/hal/adc_types.h
@@ -214,7 +214,7 @@ typedef struct {
     };
 } adc_digi_output_data_t;
 
-#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5
+#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 /**
  * @brief ADC digital controller (DMA mode) output data format.
  *        Used to analyze the acquired ADC (DMA) data.
diff --git a/components/hal/include/hal/color_types.h b/components/hal/include/hal/color_types.h
index 2cdd7d33104..93c69b323d7 100644
--- a/components/hal/include/hal/color_types.h
+++ b/components/hal/include/hal/color_types.h
@@ -141,6 +141,15 @@ typedef enum {
 /*---------------------------------------------------------------
                       Color Endian
 ---------------------------------------------------------------*/
+/**
+ * @brief RAW element order
+ */
+typedef enum {
+    COLOR_RAW_ELEMENT_ORDER_BGGR,    ///< BGGR order
+    COLOR_RAW_ELEMENT_ORDER_GBRG,    ///< GBRG order
+    COLOR_RAW_ELEMENT_ORDER_GRBG,    ///< GRBG order
+    COLOR_RAW_ELEMENT_ORDER_RGGB,    ///< RGGB order
+} color_raw_element_order_t;
 
 /**
  * @brief RGB element order
@@ -202,6 +211,16 @@ typedef enum {
     COLOR_COMPONENT_INVALID,    /*!< Invalid color component */
 } color_component_t;
 
+/**
+ * @brief The order of the components per pack in the YUV422 format
+ */
+typedef enum {
+    COLOR_YUV422_PACK_ORDER_YUYV, /*!< YUYV */
+    COLOR_YUV422_PACK_ORDER_YVYU, /*!< YVYU */
+    COLOR_YUV422_PACK_ORDER_UYVY, /*!< UYVY */
+    COLOR_YUV422_PACK_ORDER_VYUY, /*!< VYUY */
+} color_yuv422_pack_order_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/include/hal/emac_hal.h b/components/hal/include/hal/emac_hal.h
index 70b5e86478b..953adb36d85 100644
--- a/components/hal/include/hal/emac_hal.h
+++ b/components/hal/include/hal/emac_hal.h
@@ -188,6 +188,7 @@ typedef struct {
 
 ASSERT_TYPE_SIZE(eth_dma_rx_descriptor_t, EMAC_HAL_DMA_DESC_SIZE);
 
+
 typedef struct emac_mac_dev_s *emac_mac_soc_regs_t;
 typedef struct emac_dma_dev_s *emac_dma_soc_regs_t;
 #if CONFIG_IDF_TARGET_ESP32
@@ -195,11 +196,17 @@ typedef struct emac_ext_dev_s *emac_ext_soc_regs_t;
 #else
 typedef void *emac_ext_soc_regs_t;
 #endif
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+typedef struct emac_ptp_dev_s *emac_ptp_soc_regs_t;
+#endif
 
 typedef struct {
     emac_mac_soc_regs_t mac_regs;
     emac_dma_soc_regs_t dma_regs;
     emac_ext_soc_regs_t ext_regs;
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+    emac_ptp_soc_regs_t ptp_regs;
+#endif
 } emac_hal_context_t;
 
 /**
@@ -209,6 +216,18 @@ typedef struct {
     eth_mac_dma_burst_len_t dma_burst_len;  /*!< eth-type enum of chosen dma burst-len */
 } emac_hal_dma_config_t;
 
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+/**
+ * @brief EMAC PTP configuration parameters
+ */
+typedef struct {
+    eth_mac_ptp_update_method_t upd_method;
+    eth_mac_ptp_roll_type_t roll;
+    uint32_t ptp_clk_src_period_ns;         /*!< 1/ptp_ref_clk */
+    uint32_t ptp_req_accuracy_ns;           /*!< required PTP accuracy in ns, must be greater than clk_src period */
+} emac_hal_ptp_config_t;
+#endif
+
 void emac_hal_init(emac_hal_context_t *hal);
 
 #define emac_hal_get_phy_intf(hal) emac_ll_get_phy_intf((hal)->ext_regs)
@@ -288,6 +307,130 @@ void emac_hal_set_rx_tx_desc_addr(emac_hal_context_t *hal, eth_dma_rx_descriptor
 
 #define emac_hal_transmit_poll_demand(hal) emac_ll_transmit_poll_demand((hal)->dma_regs, 0)
 
+#if SOC_EMAC_IEEE1588V2_SUPPORTED
+#define emac_hal_get_ts_status(hal) emac_ll_get_ts_status((hal)->ptp_regs);
+
+#define emac_hal_clock_enable_ptp(hal, clk_src, enable) emac_ll_clock_enable_ptp((hal)->ext_regs, clk_src, enable);
+
+/**
+ * @brief Start Ethernet PTP timestamp for transmit and receive frames
+ *
+ * @param hal EMAC HAL context infostructure
+ * @return
+ *         - ESP_OK: on success
+ *         - ESP_ERR_TIMEOUT: on PTP block is busy
+ */
+esp_err_t emac_hal_ptp_start(emac_hal_context_t *hal, const emac_hal_ptp_config_t *config);
+
+/**
+ * @brief Stop Ethernet PTP timestamp
+ *
+ * @param hal EMAC HAL context infostructure
+ * @return
+ *          Always return ESP_OK
+ */
+esp_err_t emac_hal_ptp_stop(emac_hal_context_t *hal);
+
+/**
+ * @brief Updates time stamp addend register relatively to the base value
+ *
+ * @param hal EMAC HAL context infostructure
+ * @param adj_ppb Correction value in ppb(parts per billion) (adj*10^9).
+ *            For example, if the crystal used is 5 Hz off, then this value should be 5000.
+ * @return
+ *         - ESP_OK: on success
+ *         - ESP_ERR_INVALID_STATE: on PTP block is busy
+ */
+esp_err_t emac_hal_ptp_adj_inc(emac_hal_context_t *hal, int32_t adj_ppb);
+
+/**
+ * @brief Updates time stamp addend register relatively to the previous value
+ *
+ * @param hal EMAC HAL context infostructure
+ * @param scale_factor scale factor with which the addend register value is updated
+ * @return
+ *         - ESP_OK: on success
+ *         - ESP_ERR_INVALID_STATE: on PTP block is busy
+ */
+esp_err_t emac_hal_adj_freq_factor(emac_hal_context_t *hal, double ratio);
+
+/**
+ * @brief Adds or subtracts to the PTP system time.
+ *
+ * @param hal EMAC HAL context infostructure
+ * @param off_sec the PTP Time update second value
+ * @param off_nsec the PTP Time update nano-second value
+ * @param sign specifies the PTP Time update value sign(true means positive, false means negative)
+ * @return
+ *        - ESP_OK: on success
+ *        - ESP_ERR_INVALID_STATE: on waiting for previous update to end
+ */
+esp_err_t emac_hal_ptp_time_add(emac_hal_context_t *hal, uint32_t off_sec, uint32_t off_nsec, bool sign);
+
+/**
+ * @brief Initialize the PTP time base
+ *
+ * @param hal EMAC HAL context infostructure
+ * @param seconds specifies the PTP Time init second value
+ * @param nano_seconds specifies the PTP Time init nano-second value
+ * @return
+ *         - ESP_OK: on success,
+ *         - ESP_ERR_INVALID_STATE: on waiting for previous init to end
+ */
+esp_err_t emac_hal_ptp_set_sys_time(emac_hal_context_t *hal, uint32_t seconds, uint32_t nano_seconds);
+
+/**
+ * @brief Get the current value of the system time maintained by the MAC
+ *
+ * @param hal EMAC HAL context infostructure
+ * @param seconds get the PTP system time second value
+ * @param nano_seconds get the PTP system time nano-second value
+ * @return
+ *          - ESP_OK: on success
+ *          - ESP_ERR_INVALID_ARG: on invalid argument
+ */
+esp_err_t emac_hal_ptp_get_sys_time(emac_hal_context_t *hal, uint32_t *seconds, uint32_t *nano_seconds);
+
+/**
+ * @brief Set target time to trigger event when the system time exceeds the target time
+ *
+ * @param hal EMAC HAL context infostructure
+ * @param seconds specifies the PTP target time second value
+ * @param nano_seconds specifies the PTP target Time nano-second value
+ * @return
+ *          - ESP_OK on success, ESP_ERR_TIMEOUT on busy
+ */
+esp_err_t emac_hal_ptp_set_target_time(emac_hal_context_t *hal, uint32_t seconds, uint32_t nano_seconds);
+
+/**
+ * @brief Get timestamp from receive descriptor
+ *
+ * @param hal EMAC HAL context infostructure
+ * @param rxdesc Pointer to receive descriptor
+ * @param seconds Pointer to store seconds part of timestamp
+ * @param nano_seconds Pointer to store nanoseconds part of timestamp
+ *
+ * @return
+ *     - ESP_OK: On success
+ *     - ESP_ERR_INVALID_STATE: Descriptor does not contain time stamp information (frame might be filtered)
+ */
+esp_err_t emac_hal_get_rxdesc_timestamp(emac_hal_context_t *hal, eth_dma_rx_descriptor_t *rxdesc, uint32_t *seconds, uint32_t *nano_seconds);
+
+/**
+ * @brief Get timestamp from transmit descriptor
+ *
+ * @param hal EMAC HAL context infostructure
+ * @param txdesc Pointer to transmit descriptor
+ * @param seconds Pointer to store seconds part of timestamp
+ * @param nano_seconds Pointer to store nanoseconds part of timestamp
+ *
+ * @return
+ *     - ESP_OK: On success
+ *     - ESP_ERR_INVALID_STATE: descriptor is still owned by DMA or time stamp is not ready yet
+ */
+esp_err_t emac_hal_get_txdesc_timestamp(emac_hal_context_t *hal, eth_dma_tx_descriptor_t *txdesc, uint32_t *seconds, uint32_t *nano_seconds);
+
+#endif // SOC_EMAC_IEEE1588V2_SUPPORTED
 #endif  // SOC_EMAC_SUPPORTED
 
 #ifdef __cplusplus
diff --git a/components/hal/include/hal/eth_types.h b/components/hal/include/hal/eth_types.h
index 018d958f15c..42ad5de57b1 100644
--- a/components/hal/include/hal/eth_types.h
+++ b/components/hal/include/hal/eth_types.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -66,6 +66,24 @@ typedef enum {
     ETH_DMA_BURST_LEN_1,
 } eth_mac_dma_burst_len_t;
 
+/**
+ * @brief EMAC System timestamp update update method
+ *
+ */
+typedef enum {
+    ETH_PTP_UPDATE_METHOD_COARSE,   /*!< EMAC System timestamp update using the Coarse method */
+    ETH_PTP_UPDATE_METHOD_FINE      /*!< EMAC System timestamp update using the Fine method */
+} eth_mac_ptp_update_method_t;
+
+/**
+ * @brief EMAC System Timestamp Rollover
+ *
+ */
+typedef enum {
+    ETH_PTP_DIGITAL_ROLLOVER,       /*!< Digital - subseconds register rolls over after 999999999 value (1 nanosecond accuracy) */
+    ETH_PTP_BINARY_ROLLOVER         /*!< Binary - subseconds register rolls over after 0x7FFFFFFF value  */
+} eth_mac_ptp_roll_type_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/huk_hal.h b/components/hal/include/hal/huk_hal.h
similarity index 96%
rename from components/hal/esp32p4/include/hal/huk_hal.h
rename to components/hal/include/hal/huk_hal.h
index 796f2b8f943..e158f1fc664 100644
--- a/components/hal/esp32p4/include/hal/huk_hal.h
+++ b/components/hal/include/hal/huk_hal.h
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-// The HAL layer for Hardware Unique Key (HUK) Genarator
+// The HAL layer for Hardware Unique Key (HUK) Generator
 
 #pragma once
 
diff --git a/components/hal/include/hal/i2c_types.h b/components/hal/include/hal/i2c_types.h
index 6a0d685ac74..57cf5a6b9fe 100644
--- a/components/hal/include/hal/i2c_types.h
+++ b/components/hal/include/hal/i2c_types.h
@@ -98,6 +98,11 @@ typedef enum {
     I2C_SLAVE_STRETCH_CAUSE_SENDING_ACK = 3,     /*!< Stretching SCL low when slave sending ACK */
 } i2c_slave_stretch_cause_t;
 
+typedef enum {
+    I2C_SLAVE_WRITE_BY_MASTER = 0,
+    I2C_SLAVE_READ_BY_MASTER = 1,
+} i2c_slave_read_write_status_t;
+
 #if SOC_I2C_SUPPORTED
 /**
  * @brief I2C group clock source
diff --git a/components/hal/include/hal/isp_types.h b/components/hal/include/hal/isp_types.h
index ae7d001f5b3..974c5a3d354 100644
--- a/components/hal/include/hal/isp_types.h
+++ b/components/hal/include/hal/isp_types.h
@@ -393,6 +393,31 @@ typedef union {
     uint32_t val;       ///< 32-bit color saturation value
 } isp_color_saturation_t;
 
+/*---------------------------------------------------------------
+                      LSC
+---------------------------------------------------------------*/
+#if SOC_ISP_LSC_SUPPORTED
+#define ISP_LSC_GRAD_RATIO_INT_BITS    SOC_ISP_LSC_GRAD_RATIO_INT_BITS
+#define ISP_LSC_GRAD_RATIO_DEC_BITS    SOC_ISP_LSC_GRAD_RATIO_DEC_BITS
+#define ISP_LSC_GRAD_RATIO_RES_BITS    SOC_ISP_LSC_GRAD_RATIO_RES_BITS
+#else
+#define ISP_LSC_GRAD_RATIO_INT_BITS    2
+#define ISP_LSC_GRAD_RATIO_DEC_BITS    8
+#define ISP_LSC_GRAD_RATIO_RES_BITS    22
+#endif
+
+/**
+ * @brief LSC gain
+ */
+typedef union {
+    struct {
+        uint32_t decimal:8;    ///< Integer part
+        uint32_t integer:2;    ///< Decimal part
+        uint32_t reserved:ISP_LSC_GRAD_RATIO_RES_BITS;   ///< Reserved
+    };
+    uint32_t val;    ///< 32-bit gradient ratio value
+} isp_lsc_gain_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32p4/include/hal/key_mgr_hal.h b/components/hal/include/hal/key_mgr_hal.h
similarity index 94%
rename from components/hal/esp32p4/include/hal/key_mgr_hal.h
rename to components/hal/include/hal/key_mgr_hal.h
index 3bed3fa3fd1..8a3ca092dca 100644
--- a/components/hal/esp32p4/include/hal/key_mgr_hal.h
+++ b/components/hal/include/hal/key_mgr_hal.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -37,11 +37,11 @@ void key_mgr_hal_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_
  */
 esp_key_mgr_key_usage_t key_mgr_hal_get_key_usage(const esp_key_mgr_key_type_t key_type);
 
-/* @brief Configure the key purpose to be used by the Key Manager for key generator opearation */
+/* @brief Configure the key purpose to be used by the Key Manager for key generator operation */
 void key_mgr_hal_set_key_purpose(const esp_key_mgr_key_purpose_t key_purpose);
 
 /**
- * @bfief Configure the mode which is used by the Key Manager for the generator key deployement process
+ * @bfief Configure the mode which is used by the Key Manager for the generator key deployment process
  */
 void key_mgr_hal_set_key_generator_mode(const esp_key_mgr_key_generator_mode_t mode);
 
@@ -131,11 +131,11 @@ uint32_t key_mgr_hal_get_date_info(void);
 
 /**
  * @brief Set the Key Manager date information
- *        Only the least siginificant 28 bits shall be considered
+ *        Only the least significant 28 bits shall be considered
  */
 void key_mgr_hal_set_date_info(const uint32_t date_info);
 
 #ifdef __cplusplus
 }
 #endif
-#endif
+#endif /* SOC_KEY_MANAGER_SUPPORTED */
diff --git a/components/hal/include/hal/lcd_types.h b/components/hal/include/hal/lcd_types.h
index 1bff0f6472d..5fbdb1aea27 100644
--- a/components/hal/include/hal/lcd_types.h
+++ b/components/hal/include/hal/lcd_types.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -48,6 +48,16 @@ typedef enum {
     LCD_COLOR_PIXEL_FORMAT_RGB888 = COLOR_PIXEL_RGB888, /*!< 24 bits, 8 bits per R/G/B value */
 } lcd_color_rgb_pixel_format_t;
 
+/**
+ * @brief LCD color format
+ */
+typedef enum {
+    LCD_COLOR_FMT_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), ///< RGB565
+    LCD_COLOR_FMT_RGB666 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB666), ///< RGB666
+    LCD_COLOR_FMT_RGB888 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888), ///< RGB888
+    LCD_COLOR_FMT_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), ///< YUV422
+} lcd_color_format_t;
+
 /**
  * @brief LCD color range
  */
@@ -73,6 +83,17 @@ typedef enum {
     LCD_YUV_CONV_STD_BT709 = COLOR_CONV_STD_RGB_YUV_BT709, /*!< YUV<->RGB conversion standard: BT.709 */
 } lcd_yuv_conv_std_t;
 
+
+/**
+ * @brief YUV422 packing order
+ */
+typedef enum {
+    LCD_YUV422_PACK_ORDER_YUYV = COLOR_YUV422_PACK_ORDER_YUYV, /*!< YUYV */
+    LCD_YUV422_PACK_ORDER_YVYU = COLOR_YUV422_PACK_ORDER_YVYU, /*!< YVYU */
+    LCD_YUV422_PACK_ORDER_UYVY = COLOR_YUV422_PACK_ORDER_UYVY, /*!< UYVY */
+    LCD_YUV422_PACK_ORDER_VYUY = COLOR_YUV422_PACK_ORDER_VYUY, /*!< VYUY */
+} lcd_yuv422_pack_order_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/include/hal/mipi_dsi_hal.h b/components/hal/include/hal/mipi_dsi_hal.h
index 7ec69da23ee..e3e43b2b3bb 100644
--- a/components/hal/include/hal/mipi_dsi_hal.h
+++ b/components/hal/include/hal/mipi_dsi_hal.h
@@ -150,7 +150,7 @@ void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_
  * @param color_coding Color coding
  * @param sub_config Sub configuration
  */
-void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_rgb_pixel_format_t color_coding, uint32_t sub_config);
+void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_format_t color_coding, uint32_t sub_config);
 
 /**
  * @brief Set horizontal timing parameters for DPI
diff --git a/components/hal/include/hal/modem_clock_hal.h b/components/hal/include/hal/modem_clock_hal.h
index dfc5009741b..ec04d18d718 100644
--- a/components/hal/include/hal/modem_clock_hal.h
+++ b/components/hal/include/hal/modem_clock_hal.h
@@ -29,7 +29,7 @@ void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal,
 uint32_t modem_clock_hal_get_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain);
 #endif
 
-void modem_clock_hal_enable_modem_adc_common_fe_clock(modem_clock_hal_context_t *hal, bool enable);
+void modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable);
 void modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable);
 
 #if SOC_BT_SUPPORTED
diff --git a/components/hal/include/hal/touch_sens_hal.h b/components/hal/include/hal/touch_sens_hal.h
new file mode 100644
index 00000000000..f10992363a9
--- /dev/null
+++ b/components/hal/include/hal/touch_sens_hal.h
@@ -0,0 +1,117 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*******************************************************************************
+ * NOTICE
+ * The hal is not public api, don't use in application code.
+ * See readme.md in hal/include/hal/readme.md
+ ******************************************************************************/
+
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if SOC_TOUCH_SENSOR_VERSION > 1
+#include "hal/touch_sensor_ll.h"
+#include "hal/touch_sens_types.h"
+#endif  // SOC_TOUCH_SENSOR_SUPPORTED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_TOUCH_SENSOR_VERSION > 1
+
+#if SOC_TOUCH_SENSOR_VERSION == 2
+
+/**
+ * @brief Sample configurations of the touch sensor V2
+ */
+typedef struct {
+    uint32_t                        charge_times;       /*!< The charge and discharge times of this sample configuration, the read data are positive correlation to the charge_times */
+    touch_volt_lim_h_t              charge_volt_lim_h;  /*!< The upper voltage limit while charging a touch pad. i.e., the touch controller won't charge the touch pad higher than this high voltage limitation. */
+    touch_volt_lim_l_t              charge_volt_lim_l;  /*!< The lower voltage limit while discharging a touch pad. i.e., the touch controller won't discharge the touch pad lower than this low voltage limitation. */
+    touch_idle_conn_t               idle_conn;          /*!< The connection of the idle touch channels.
+                                                         *   The idle touch channel is a channel which is enabled and power-on but not under measuring.
+                                                         */
+    touch_bias_type_t               bias_type;          /*!< The type of the touch sensor bias. Which affects the charge/discharge stability and power consumption */
+} touch_hal_sample_config_v2_t;
+
+/**
+ * @brief Alias of touch_hal_sample_config_v2_t for compatibility
+ */
+typedef touch_hal_sample_config_v2_t    touch_hal_sample_config_t;
+
+#elif SOC_TOUCH_SENSOR_VERSION == 3
+
+/**
+ * @brief Sample configurations of the touch sensor V3
+ */
+typedef struct {
+    uint32_t                        div_num;            /*!< The division of the touch output signal. It is proportional to the gain of the read data */
+    uint32_t                        charge_times;       /*!< The charge and discharge times of the sample configuration, the read data are positive correlation to the charge_times */
+    uint8_t                         rc_filter_res;      /*!< The resistance of the RC filter of the sample configuration, range [0, 3], while 0 = 0K, 1 = 1.5K, 2 = 3K, 3 = 4.5K */
+    uint8_t                         rc_filter_cap;      /*!< The capacitance of the RC filter of the sample configuration, range [0, 127], while 0 = 0pF, 1 = 20fF, ..., 127 = 2.54pF */
+    uint8_t                         low_drv;            /*!< Low speed touch driver, only effective when high speed driver is disabled */
+    uint8_t                         high_drv;           /*!< High speed touch driver */
+    uint8_t                         bias_volt;          /*!< The Internal LDO voltage, which decide the bias voltage of the sample wave, range [0,15] */
+    bool                            bypass_shield_output; /*!< Whether to bypass the shield output */
+} touch_hal_sample_config_v3_t;
+
+/**
+ * @brief Alias of touch_hal_sample_config_v3_t for compatibility
+ */
+typedef touch_hal_sample_config_v3_t    touch_hal_sample_config_t;
+
+#else
+#error "Unsupported touch sensor version"
+#endif
+
+/**
+ * @brief Configurations of the touch sensor controller
+ *
+ */
+typedef struct {
+    uint32_t                        power_on_wait_ticks;    /*!< The waiting time between the channels power on and able to measure, to ensure the data stability */
+    uint32_t                        meas_interval_ticks;    /*!< Measurement interval of each channels */ // TODO: Test the supported range
+    uint32_t                        timeout_ticks;          /*!< The maximum time of measuring one channel, if the time exceeds this value, the timeout interrupt will be triggered.
+                                                             *   Set to '0' to ignore the measurement time limitation, otherwise please set a proper time considering the configurations
+                                                             *   of the sample configurations below.
+                                                             */
+#if SOC_TOUCH_SENSOR_VERSION == 3
+    touch_out_mode_t                output_mode;            /*!< Touch channel counting mode of the binarized touch output */
+#endif  // SOC_TOUCH_SENSOR_VERSION == 3
+    uint32_t                        sample_cfg_num;         /*!< The sample configuration number that used for sampling */
+    touch_hal_sample_config_t       *sample_cfg;            /*!< The array of the sample configuration configurations, the length should be specified in `touch_hal_sample_config_t::sample_cfg_num` */
+} touch_hal_config_t;
+
+/**
+ * @brief Configure the touch sensor hardware with the configuration
+ *
+ * @param[in]  cfg  Touch sensor hardware configuration
+ */
+void touch_hal_config_controller(const touch_hal_config_t *cfg);
+
+/**
+ * @brief Save the touch sensor hardware configuration
+ * @note  The saved configurations will be applied before entering deep sleep
+ *
+ * @param[in]  deep_slp_chan    The touch sensor channel that can wake-up the chip from deep sleep
+ * @param[in]  deep_slp_cfg     The hardware configuration that takes effect during the deep sleep
+ */
+void touch_hal_save_sleep_config(int deep_slp_chan, const touch_hal_config_t *deep_slp_cfg);
+
+/**
+ * @brief Prepare for the deep sleep
+ * @note  Including apply the deep sleep configuration, clear interrupts, resetting benchmark
+ */
+void touch_hal_prepare_deep_sleep(void);
+
+#endif  // SOC_TOUCH_SENSOR_SUPPORTED
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/include/hal/touch_sens_types.h b/components/hal/include/hal/touch_sens_types.h
new file mode 100644
index 00000000000..65c3b92d6d2
--- /dev/null
+++ b/components/hal/include/hal/touch_sens_types.h
@@ -0,0 +1,171 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Touch sensor shield channel drive capability level
+ *
+ */
+typedef enum {
+    TOUCH_SHIELD_CAP_40PF,                  /*!< The max equivalent capacitance in shield channel is 40pf */
+    TOUCH_SHIELD_CAP_80PF,                  /*!< The max equivalent capacitance in shield channel is 80pf */
+    TOUCH_SHIELD_CAP_120PF,                 /*!< The max equivalent capacitance in shield channel is 120pf */
+    TOUCH_SHIELD_CAP_160PF,                 /*!< The max equivalent capacitance in shield channel is 160pf */
+    TOUCH_SHIELD_CAP_200PF,                 /*!< The max equivalent capacitance in shield channel is 200pf */
+    TOUCH_SHIELD_CAP_240PF,                 /*!< The max equivalent capacitance in shield channel is 240pf */
+    TOUCH_SHIELD_CAP_280PF,                 /*!< The max equivalent capacitance in shield channel is 280pf */
+    TOUCH_SHIELD_CAP_320PF,                 /*!< The max equivalent capacitance in shield channel is 320pf */
+} touch_chan_shield_cap_t;
+
+/**
+ * @brief Touch channel Infinite Impulse Response (IIR) filter or Jitter filter for benchmark
+ * @note Recommended filter coefficient selection is `IIR_16`.
+ */
+typedef enum {
+    TOUCH_BM_IIR_FILTER_4,                  /*!< IIR Filter for benchmark, 1/4 raw_value + 3/4 benchmark */
+    TOUCH_BM_IIR_FILTER_8,                  /*!< IIR Filter for benchmark, 1/8 raw_value + 7/8 benchmark */
+    TOUCH_BM_IIR_FILTER_16,                 /*!< IIR Filter for benchmark, 1/16 raw_value + 15/16 benchmark (typical) */
+    TOUCH_BM_IIR_FILTER_32,                 /*!< IIR Filter for benchmark, 1/32 raw_value + 31/32 benchmark */
+    TOUCH_BM_IIR_FILTER_64,                 /*!< IIR Filter for benchmark, 1/64 raw_value + 63/64 benchmark */
+    TOUCH_BM_IIR_FILTER_128,                /*!< IIR Filter for benchmark, 1/128 raw_value + 127/128 benchmark */
+#if SOC_TOUCH_SENSOR_VERSION == 2
+    TOUCH_BM_IIR_FILTER_256,                /*!< IIR Filter for benchmark, 1/256 raw_value + 255/256 benchmark */
+#endif
+    TOUCH_BM_JITTER_FILTER,                 /*!< Jitter Filter for benchmark, raw value +/- jitter_step */
+} touch_benchmark_filter_mode_t;
+
+/**
+ * @brief Touch channel Infinite Impulse Response (IIR) filter for smooth data
+ *
+ */
+typedef enum {
+    TOUCH_SMOOTH_NO_FILTER,                 /*!< No filter adopted for smooth data, smooth data equals raw data */
+    TOUCH_SMOOTH_IIR_FILTER_2,              /*!< IIR filter adopted for smooth data, smooth data equals 1/2 raw data + 1/2 last smooth data (typical) */
+    TOUCH_SMOOTH_IIR_FILTER_4,              /*!< IIR filter adopted for smooth data, smooth data equals 1/4 raw data + 3/4 last smooth data */
+    TOUCH_SMOOTH_IIR_FILTER_8,              /*!< IIR filter adopted for smooth data, smooth data equals 1/8 raw data + 7/8 last smooth data */
+} touch_smooth_filter_mode_t;
+
+/**
+ * @brief Touch sensor upper charging voltage limit
+ */
+typedef enum {
+    TOUCH_VOLT_LIM_H_0V9,         /*!< Touch sensor upper voltage limit is 0.9V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_1V0,         /*!< Touch sensor upper voltage limit is 1.0V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_1V1,         /*!< Touch sensor upper voltage limit is 1.1V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_1V2,         /*!< Touch sensor upper voltage limit is 1.2V while charging a touch pad */
+    // No 1V3
+    TOUCH_VOLT_LIM_H_1V4,         /*!< Touch sensor upper voltage limit is 1.4V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_1V5,         /*!< Touch sensor upper voltage limit is 1.5V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_1V6,         /*!< Touch sensor upper voltage limit is 1.6V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_1V7,         /*!< Touch sensor upper voltage limit is 1.7V while charging a touch pad */
+    // No 1V8
+    TOUCH_VOLT_LIM_H_1V9,         /*!< Touch sensor upper voltage limit is 1.9V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_2V0,         /*!< Touch sensor upper voltage limit is 2.0V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_2V1,         /*!< Touch sensor upper voltage limit is 2.1V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_2V2,         /*!< Touch sensor upper voltage limit is 2.2V while charging a touch pad */
+    // No 2V3
+    TOUCH_VOLT_LIM_H_2V4,         /*!< Touch sensor upper voltage limit is 2.4V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_2V5,         /*!< Touch sensor upper voltage limit is 2.5V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_2V6,         /*!< Touch sensor upper voltage limit is 2.6V while charging a touch pad */
+    TOUCH_VOLT_LIM_H_2V7,         /*!< Touch sensor upper voltage limit is 2.7V while charging a touch pad */
+} touch_volt_lim_h_t;
+
+/**
+ * @brief Touch sensor lower discharging voltage limit
+ */
+typedef enum {
+    TOUCH_VOLT_LIM_L_0V5,         /*!< Touch sensor lower voltage limit is 0.5V while discharging a touch pad */
+    TOUCH_VOLT_LIM_L_0V6,         /*!< Touch sensor lower voltage limit is 0.6V while discharging a touch pad */
+    TOUCH_VOLT_LIM_L_0V7,         /*!< Touch sensor lower voltage limit is 0.7V while discharging a touch pad */
+    TOUCH_VOLT_LIM_L_0V8,         /*!< Touch sensor lower voltage limit is 0.8V while discharging a touch pad */
+} touch_volt_lim_l_t;
+
+/**
+ * @brief Touch sensor charge and discharge speed
+ */
+typedef enum {
+    TOUCH_CHARGE_SPEED_0 = 0,     /*!< Touch sensor charge and discharge speed, no charge, always zero  */
+    TOUCH_CHARGE_SPEED_1 = 1,     /*!< Touch sensor charge and discharge speed, slowest  */
+    TOUCH_CHARGE_SPEED_2 = 2,     /*!< Touch sensor charge and discharge speed */
+    TOUCH_CHARGE_SPEED_3 = 3,     /*!< Touch sensor charge and discharge speed */
+    TOUCH_CHARGE_SPEED_4 = 4,     /*!< Touch sensor charge and discharge speed */
+    TOUCH_CHARGE_SPEED_5 = 5,     /*!< Touch sensor charge and discharge speed */
+    TOUCH_CHARGE_SPEED_6 = 6,     /*!< Touch sensor charge and discharge speed */
+    TOUCH_CHARGE_SPEED_7 = 7,     /*!< Touch sensor charge and discharge speed, fastest  */
+} touch_charge_speed_t;
+
+/**
+ * @brief Touch sensor initial voltage before charging
+ */
+typedef enum {
+    TOUCH_INIT_CHARGE_VOLT_LOW = 0, /*!< Tie the initial charge voltage to low */
+    TOUCH_INIT_CHARGE_VOLT_HIGH = 1,/*!< Tie the initial charge voltage to high */
+} touch_init_charge_volt_t;
+
+/**
+ *  @brief Touch channel idle state configuration
+ */
+typedef enum {
+    TOUCH_IDLE_CONN_HIGHZ = 0,      /*!< The idle (enabled but not measuring) touch channel is at high resistance state */
+    TOUCH_IDLE_CONN_GND = 1,        /*!< The idle (enabled but not measuring) touch channel is connected to the ground */
+} touch_idle_conn_t;
+
+/**
+ * @brief Touch sensor denoise channel internal reference capacitance
+ */
+typedef enum {
+    TOUCH_DENOISE_CHAN_CAP_5PF   = 0,   /*!< Denoise channel internal reference capacitance is 5.0pf */
+    TOUCH_DENOISE_CHAN_CAP_6PF   = 1,   /*!< Denoise channel internal reference capacitance is 6.4pf */
+    TOUCH_DENOISE_CHAN_CAP_7PF   = 2,   /*!< Denoise channel internal reference capacitance is 7.8pf */
+    TOUCH_DENOISE_CHAN_CAP_9PF   = 3,   /*!< Denoise channel internal reference capacitance is 9.2pf */
+    TOUCH_DENOISE_CHAN_CAP_10PF  = 4,   /*!< Denoise channel internal reference capacitance is 10.6pf */
+    TOUCH_DENOISE_CHAN_CAP_12PF  = 5,   /*!< Denoise channel internal reference capacitance is 12.0pf */
+    TOUCH_DENOISE_CHAN_CAP_13PF  = 6,   /*!< Denoise channel internal reference capacitance is 13.4pf */
+    TOUCH_DENOISE_CHAN_CAP_14PF  = 7,   /*!< Denoise channel internal reference capacitance is 14.8pf */
+} touch_denoise_chan_cap_t;
+
+/**
+ * @brief Touch sensor denoise channel noise suppression resolution
+ */
+typedef enum {
+    TOUCH_DENOISE_CHAN_RESOLUTION_BIT12 = 0,    /*!< Denoise channel noise suppression resolution is 12bit */
+    TOUCH_DENOISE_CHAN_RESOLUTION_BIT10 = 1,    /*!< Denoise channel noise suppression resolution is 10bit */
+    TOUCH_DENOISE_CHAN_RESOLUTION_BIT8 = 2,     /*!< Denoise channel noise suppression resolution is 8bit */
+    TOUCH_DENOISE_CHAN_RESOLUTION_BIT4 = 3,     /*!< Denoise channel noise suppression resolution is 4bit */
+} touch_denoise_chan_resolution_t;
+
+/**
+ * @brief Touch sensor bias type
+ */
+typedef enum {
+    TOUCH_BIAS_TYPE_BANDGAP,            /*!< Use bandgap-bias to charge/discharge the touch channel, which is more stable but power-consuming */
+    TOUCH_BIAS_TYPE_SELF,               /*!< Use self-bias to charge/discharge the touch channel, which is less stable but power-saving */
+} touch_bias_type_t;
+
+/**
+ * @brief Touch channel binarized output counting mode
+ */
+typedef enum {
+    TOUCH_PAD_OUT_AS_DATA,      /*!< Counting the output of touch channel as data.
+                                 *   The value will be smaller than actual value but more sensitive when the frequency of touch_out is close to the source clock
+                                 *   Normally we treat the output as data when it is lower than the sample clock
+                                 */
+    TOUCH_PAD_OUT_AS_CLOCK,     /*!< Counting the output of touch channel as clock.
+                                 *   The value is accurate but less sensitive when the frequency of touch_out is close to the source clock
+                                 *   Normally we treat the output as clock when it is higher than the sample clock
+                                 */
+} touch_out_mode_t;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/include/hal/touch_sensor_hal.h b/components/hal/include/hal/touch_sensor_hal.h
index be45ca89ab6..23f9ba863a0 100644
--- a/components/hal/include/hal/touch_sensor_hal.h
+++ b/components/hal/include/hal/touch_sensor_hal.h
@@ -10,13 +10,14 @@
  * See readme.md in hal/include/hal/readme.md
  ******************************************************************************/
 
-// The HAL layer for touch sensor (common part)
+// The legacy HAL layer for touch sensor (common part)
 
 #pragma once
 
+#include "soc/soc_caps.h"
 #if SOC_TOUCH_SENSOR_SUPPORTED
 #include "hal/touch_sensor_ll.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/components/hal/include/hal/touch_sensor_legacy_types.h b/components/hal/include/hal/touch_sensor_legacy_types.h
new file mode 100644
index 00000000000..c5428372c94
--- /dev/null
+++ b/components/hal/include/hal/touch_sensor_legacy_types.h
@@ -0,0 +1,307 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_bit_defs.h"
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Touch pad channel */
+typedef enum {
+    TOUCH_PAD_NUM0 = 0, /*!< Touch pad channel 0 is GPIO4(ESP32) */
+    TOUCH_PAD_NUM1,     /*!< Touch pad channel 1 is GPIO0(ESP32) / GPIO1(ESP32-S2) */
+    TOUCH_PAD_NUM2,     /*!< Touch pad channel 2 is GPIO2(ESP32) / GPIO2(ESP32-S2) */
+    TOUCH_PAD_NUM3,     /*!< Touch pad channel 3 is GPIO15(ESP32) / GPIO3(ESP32-S2) */
+    TOUCH_PAD_NUM4,     /*!< Touch pad channel 4 is GPIO13(ESP32) / GPIO4(ESP32-S2) */
+    TOUCH_PAD_NUM5,     /*!< Touch pad channel 5 is GPIO12(ESP32) / GPIO5(ESP32-S2) */
+    TOUCH_PAD_NUM6,     /*!< Touch pad channel 6 is GPIO14(ESP32) / GPIO6(ESP32-S2) */
+    TOUCH_PAD_NUM7,     /*!< Touch pad channel 7 is GPIO27(ESP32) / GPIO7(ESP32-S2) */
+    TOUCH_PAD_NUM8,     /*!< Touch pad channel 8 is GPIO33(ESP32) / GPIO8(ESP32-S2) */
+    TOUCH_PAD_NUM9,     /*!< Touch pad channel 9 is GPIO32(ESP32) / GPIO9(ESP32-S2) */
+#if SOC_TOUCH_SENSOR_NUM > 10
+    TOUCH_PAD_NUM10,    /*!< Touch channel 10 is GPIO10(ESP32-S2) */
+    TOUCH_PAD_NUM11,    /*!< Touch channel 11 is GPIO11(ESP32-S2) */
+    TOUCH_PAD_NUM12,    /*!< Touch channel 12 is GPIO12(ESP32-S2) */
+    TOUCH_PAD_NUM13,    /*!< Touch channel 13 is GPIO13(ESP32-S2) */
+    TOUCH_PAD_NUM14,    /*!< Touch channel 14 is GPIO14(ESP32-S2) */
+#endif
+    TOUCH_PAD_MAX,
+} touch_pad_t;
+
+/** Touch sensor high reference voltage */
+typedef enum {
+    TOUCH_HVOLT_KEEP = -1, /*!<Touch sensor high reference voltage, no change  */
+    TOUCH_HVOLT_2V4 = 0,   /*!<Touch sensor high reference voltage, 2.4V  */
+    TOUCH_HVOLT_2V5,       /*!<Touch sensor high reference voltage, 2.5V  */
+    TOUCH_HVOLT_2V6,       /*!<Touch sensor high reference voltage, 2.6V  */
+    TOUCH_HVOLT_2V7,       /*!<Touch sensor high reference voltage, 2.7V  */
+    TOUCH_HVOLT_MAX,
+} touch_high_volt_t;
+
+/** Touch sensor low reference voltage */
+typedef enum {
+    TOUCH_LVOLT_KEEP = -1, /*!<Touch sensor low reference voltage, no change  */
+    TOUCH_LVOLT_0V5 = 0,   /*!<Touch sensor low reference voltage, 0.5V  */
+    TOUCH_LVOLT_0V6,       /*!<Touch sensor low reference voltage, 0.6V  */
+    TOUCH_LVOLT_0V7,       /*!<Touch sensor low reference voltage, 0.7V  */
+    TOUCH_LVOLT_0V8,       /*!<Touch sensor low reference voltage, 0.8V  */
+    TOUCH_LVOLT_MAX,
+} touch_low_volt_t;
+
+/** Touch sensor high reference voltage attenuation */
+typedef enum {
+    TOUCH_HVOLT_ATTEN_KEEP = -1,  /*!<Touch sensor high reference voltage attenuation, no change  */
+    TOUCH_HVOLT_ATTEN_1V5 = 0,    /*!<Touch sensor high reference voltage attenuation, 1.5V attenuation  */
+    TOUCH_HVOLT_ATTEN_1V,         /*!<Touch sensor high reference voltage attenuation, 1.0V attenuation  */
+    TOUCH_HVOLT_ATTEN_0V5,        /*!<Touch sensor high reference voltage attenuation, 0.5V attenuation  */
+    TOUCH_HVOLT_ATTEN_0V,         /*!<Touch sensor high reference voltage attenuation,   0V attenuation  */
+    TOUCH_HVOLT_ATTEN_MAX,
+} touch_volt_atten_t;
+
+/** Touch sensor charge/discharge speed */
+typedef enum {
+    TOUCH_PAD_SLOPE_0 = 0,       /*!<Touch sensor charge / discharge speed, always zero  */
+    TOUCH_PAD_SLOPE_1 = 1,       /*!<Touch sensor charge / discharge speed, slowest  */
+    TOUCH_PAD_SLOPE_2 = 2,       /*!<Touch sensor charge / discharge speed */
+    TOUCH_PAD_SLOPE_3 = 3,       /*!<Touch sensor charge / discharge speed  */
+    TOUCH_PAD_SLOPE_4 = 4,       /*!<Touch sensor charge / discharge speed  */
+    TOUCH_PAD_SLOPE_5 = 5,       /*!<Touch sensor charge / discharge speed  */
+    TOUCH_PAD_SLOPE_6 = 6,       /*!<Touch sensor charge / discharge speed  */
+    TOUCH_PAD_SLOPE_7 = 7,       /*!<Touch sensor charge / discharge speed, fast  */
+    TOUCH_PAD_SLOPE_MAX,
+} touch_cnt_slope_t;
+
+/** Touch sensor initial charge level */
+typedef enum {
+    TOUCH_PAD_TIE_OPT_LOW = 0,    /*!<Initial level of charging voltage, low level */
+    TOUCH_PAD_TIE_OPT_HIGH = 1,   /*!<Initial level of charging voltage, high level */
+    TOUCH_PAD_TIE_OPT_MAX,
+} touch_tie_opt_t;
+
+/** Touch sensor FSM mode */
+typedef enum {
+    TOUCH_FSM_MODE_TIMER = 0,   /*!<To start touch FSM by timer */
+    TOUCH_FSM_MODE_SW,          /*!<To start touch FSM by software trigger */
+    TOUCH_FSM_MODE_MAX,
+} touch_fsm_mode_t;
+
+/**** ESP32 Only *****/
+
+typedef enum {
+    TOUCH_TRIGGER_BELOW = 0,   /*!<Touch interrupt will happen if counter value is less than threshold.*/
+    TOUCH_TRIGGER_ABOVE = 1,   /*!<Touch interrupt will happen if counter value is larger than threshold.*/
+    TOUCH_TRIGGER_MAX,
+} touch_trigger_mode_t;
+
+typedef enum {
+    TOUCH_TRIGGER_SOURCE_BOTH = 0,  /*!< wakeup interrupt is generated if both SET1 and SET2 are "touched"*/
+    TOUCH_TRIGGER_SOURCE_SET1 = 1,  /*!< wakeup interrupt is generated if SET1 is "touched"*/
+    TOUCH_TRIGGER_SOURCE_MAX,
+} touch_trigger_src_t;
+
+/********************************/
+#define TOUCH_PAD_BIT_MASK_ALL              ((1<<SOC_TOUCH_SENSOR_NUM)-1)
+#define TOUCH_PAD_SLOPE_DEFAULT             (TOUCH_PAD_SLOPE_7)
+#define TOUCH_PAD_TIE_OPT_DEFAULT           (TOUCH_PAD_TIE_OPT_LOW)
+#define TOUCH_PAD_BIT_MASK_MAX              (TOUCH_PAD_BIT_MASK_ALL)
+#define TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD    (TOUCH_HVOLT_2V7)
+#define TOUCH_PAD_LOW_VOLTAGE_THRESHOLD     (TOUCH_LVOLT_0V5)
+#define TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD   (TOUCH_HVOLT_ATTEN_0V5)
+#define TOUCH_PAD_IDLE_CH_CONNECT_DEFAULT   (TOUCH_PAD_CONN_GND)
+#if SOC_TOUCH_SENSOR_VERSION == 1
+#define TOUCH_PAD_THRESHOLD_MAX             (0)         /*!< If set touch threshold max value, The touch sensor can't be in touched status */
+#elif SOC_TOUCH_SENSOR_VERSION == 2
+#define TOUCH_PAD_THRESHOLD_MAX             (0x1FFFFF)  /*!< If set touch threshold max value, The touch sensor can't be in touched status */
+#elif SOC_TOUCH_SENSOR_VERSION == 3
+#define TOUCH_PAD_THRESHOLD_MAX             (0xFFFF)    /*!< If set touch threshold max value, The touch sensor can't be in touched status */
+#endif
+
+#ifdef CONFIG_IDF_TARGET_ESP32
+
+#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT   (0x1000)  /*!<The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options), max value is 0xffff */
+#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (0x7fff)  /*!<The timer frequency is 8Mhz, the max value is 0x7fff */
+#define TOUCH_FSM_MODE_DEFAULT          (TOUCH_FSM_MODE_SW)  /*!<The touch FSM my be started by the software or timer */
+#define TOUCH_TRIGGER_MODE_DEFAULT      (TOUCH_TRIGGER_BELOW)   /*!<Interrupts can be triggered if sensor value gets below or above threshold */
+#define TOUCH_TRIGGER_SOURCE_DEFAULT    (TOUCH_TRIGGER_SOURCE_SET1)  /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */
+
+#endif // CONFIG_IDF_TARGET ESP32
+
+#if !CONFIG_IDF_TARGET_ESP32
+/**
+ * Excessive total time will slow down the touch response.
+ * Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
+ *
+ * @note The greater the duty cycle of the measurement time, the more system power is consumed.
+ */
+#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT   (0xf)   /*!<The number of sleep cycle in each measure process of touch channels.
+                                                    The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options).
+                                                    Range: 0 ~ 0xffff */
+#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (500)   /*!<The times of charge and discharge in each measure process of touch channels.
+                                                    The timer frequency is 8Mhz.
+                                                    Recommended typical value: Modify this value to make the measurement time around 1ms.
+                                                    Range: 0 ~ 0xffff */
+
+// TODO: replace by ll macro
+typedef enum {
+    TOUCH_PAD_INTR_MASK_DONE = BIT(0),      /*!<Measurement done for one of the enabled channels. */
+    TOUCH_PAD_INTR_MASK_ACTIVE = BIT(1),    /*!<Active for one of the enabled channels. */
+    TOUCH_PAD_INTR_MASK_INACTIVE = BIT(2),  /*!<Inactive for one of the enabled channels. */
+    TOUCH_PAD_INTR_MASK_SCAN_DONE = BIT(3), /*!<Measurement done for all the enabled channels. */
+    TOUCH_PAD_INTR_MASK_TIMEOUT = BIT(4),   /*!<Timeout for one of the enabled channels. */
+#if SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED
+    TOUCH_PAD_INTR_MASK_PROXI_MEAS_DONE = BIT(5),   /*!<For proximity sensor, when the number of measurements reaches the set count of measurements, an interrupt will be generated. */
+    TOUCH_PAD_INTR_MASK_MAX
+#define TOUCH_PAD_INTR_MASK_ALL (TOUCH_PAD_INTR_MASK_TIMEOUT    \
+                                | TOUCH_PAD_INTR_MASK_SCAN_DONE \
+                                | TOUCH_PAD_INTR_MASK_INACTIVE  \
+                                | TOUCH_PAD_INTR_MASK_ACTIVE    \
+                                | TOUCH_PAD_INTR_MASK_DONE      \
+                                | TOUCH_PAD_INTR_MASK_PROXI_MEAS_DONE) /*!<All touch interrupt type enable. */
+#else
+    TOUCH_PAD_INTR_MASK_MAX
+#define TOUCH_PAD_INTR_MASK_ALL (TOUCH_PAD_INTR_MASK_TIMEOUT    \
+                                | TOUCH_PAD_INTR_MASK_SCAN_DONE \
+                                | TOUCH_PAD_INTR_MASK_INACTIVE  \
+                                | TOUCH_PAD_INTR_MASK_ACTIVE    \
+                                | TOUCH_PAD_INTR_MASK_DONE) /*!<All touch interrupt type enable. */
+#endif
+} touch_pad_intr_mask_t;
+
+typedef enum {
+    TOUCH_PAD_DENOISE_BIT12 = 0,    /*!<Denoise range is 12bit */
+    TOUCH_PAD_DENOISE_BIT10 = 1,    /*!<Denoise range is 10bit */
+    TOUCH_PAD_DENOISE_BIT8 = 2,     /*!<Denoise range is 8bit */
+    TOUCH_PAD_DENOISE_BIT4 = 3,     /*!<Denoise range is 4bit */
+    TOUCH_PAD_DENOISE_MAX
+} touch_pad_denoise_grade_t;
+
+typedef enum {
+    TOUCH_PAD_DENOISE_CAP_L0 = 0,   /*!<Denoise channel internal reference capacitance is 5pf */
+    TOUCH_PAD_DENOISE_CAP_L1 = 1,   /*!<Denoise channel internal reference capacitance is 6.4pf */
+    TOUCH_PAD_DENOISE_CAP_L2 = 2,   /*!<Denoise channel internal reference capacitance is 7.8pf */
+    TOUCH_PAD_DENOISE_CAP_L3 = 3,   /*!<Denoise channel internal reference capacitance is 9.2pf */
+    TOUCH_PAD_DENOISE_CAP_L4 = 4,   /*!<Denoise channel internal reference capacitance is 10.6pf */
+    TOUCH_PAD_DENOISE_CAP_L5 = 5,   /*!<Denoise channel internal reference capacitance is 12.0pf */
+    TOUCH_PAD_DENOISE_CAP_L6 = 6,   /*!<Denoise channel internal reference capacitance is 13.4pf */
+    TOUCH_PAD_DENOISE_CAP_L7 = 7,   /*!<Denoise channel internal reference capacitance is 14.8pf */
+    TOUCH_PAD_DENOISE_CAP_MAX = 8
+} touch_pad_denoise_cap_t;
+
+/** Touch sensor denoise configuration */
+typedef struct touch_pad_denoise {
+    touch_pad_denoise_grade_t grade;    /*!<Select denoise range of denoise channel.
+                                            Determined by measuring the noise amplitude of the denoise channel. */
+    touch_pad_denoise_cap_t cap_level;  /*!<Select internal reference capacitance of denoise channel.
+                                            Ensure that the denoise readings are closest to the readings of the channel being measured.
+                                            Use `touch_pad_denoise_read_data` to get the reading of denoise channel.
+                                            The equivalent capacitance of the shielded channel can be calculated
+                                            from the reading of denoise channel. */
+} touch_pad_denoise_t;
+
+/** Touch sensor shield channel drive capability level */
+typedef enum {
+    TOUCH_PAD_SHIELD_DRV_L0 = 0,/*!<The max equivalent capacitance in shield channel is 40pf */
+    TOUCH_PAD_SHIELD_DRV_L1,    /*!<The max equivalent capacitance in shield channel is 80pf */
+    TOUCH_PAD_SHIELD_DRV_L2,    /*!<The max equivalent capacitance in shield channel is 120pf */
+    TOUCH_PAD_SHIELD_DRV_L3,    /*!<The max equivalent capacitance in shield channel is 160pf */
+    TOUCH_PAD_SHIELD_DRV_L4,    /*!<The max equivalent capacitance in shield channel is 200pf */
+    TOUCH_PAD_SHIELD_DRV_L5,    /*!<The max equivalent capacitance in shield channel is 240pf */
+    TOUCH_PAD_SHIELD_DRV_L6,    /*!<The max equivalent capacitance in shield channel is 280pf */
+    TOUCH_PAD_SHIELD_DRV_L7,    /*!<The max equivalent capacitance in shield channel is 320pf */
+    TOUCH_PAD_SHIELD_DRV_MAX
+} touch_pad_shield_driver_t;
+
+/** Touch sensor waterproof configuration */
+typedef struct touch_pad_waterproof {
+    touch_pad_t guard_ring_pad;             /*!<Waterproof. Select touch channel use for guard pad.
+                                                Guard pad is used to detect the large area of water covering the touch panel. */
+    touch_pad_shield_driver_t shield_driver;/*!<Waterproof. Shield channel drive capability configuration.
+                                                Shield pad is used to shield the influence of water droplets covering the touch panel.
+                                                When the waterproof function is enabled, Touch14 is set as shield channel by default.
+                                                The larger the parasitic capacitance on the shielding channel, the higher the drive capability needs to be set.
+                                                The equivalent capacitance of the shield channel can be estimated through the reading value of the denoise channel(Touch0).*/
+} touch_pad_waterproof_t;
+
+/** Touch sensor proximity detection configuration */
+#define TOUCH_PROXIMITY_MEAS_NUM_MAX (0xFF)
+
+/** Touch channel idle state configuration */
+typedef enum {
+    TOUCH_PAD_CONN_HIGHZ = 0,   /*!<Idle status of touch channel is high resistance state */
+    TOUCH_PAD_CONN_GND = 1,     /*!<Idle status of touch channel is ground connection */
+    TOUCH_PAD_CONN_MAX
+} touch_pad_conn_type_t;
+
+/**
+ * @brief Touch channel IIR filter coefficient configuration.
+ * @note On ESP32S2. There is an error in the IIR calculation. The magnitude of the error is twice the filter coefficient.
+ *       So please select a smaller filter coefficient on the basis of meeting the filtering requirements.
+ *       Recommended filter coefficient selection `IIR_16`.
+ */
+typedef enum {
+    TOUCH_PAD_FILTER_IIR_4 = 0, /*!<The filter mode is first-order IIR filter. The coefficient is 4. */
+    TOUCH_PAD_FILTER_IIR_8,     /*!<The filter mode is first-order IIR filter. The coefficient is 8. */
+    TOUCH_PAD_FILTER_IIR_16,    /*!<The filter mode is first-order IIR filter. The coefficient is 16 (Typical value). */
+    TOUCH_PAD_FILTER_IIR_32,    /*!<The filter mode is first-order IIR filter. The coefficient is 32. */
+    TOUCH_PAD_FILTER_IIR_64,    /*!<The filter mode is first-order IIR filter. The coefficient is 64. */
+    TOUCH_PAD_FILTER_IIR_128,   /*!<The filter mode is first-order IIR filter. The coefficient is 128. */
+    TOUCH_PAD_FILTER_IIR_256,   /*!<The filter mode is first-order IIR filter. The coefficient is 256. */
+    TOUCH_PAD_FILTER_JITTER,    /*!<The filter mode is jitter filter */
+    TOUCH_PAD_FILTER_MAX
+} touch_filter_mode_t;
+
+/**
+ * @brief Level of filter applied on the original data against large noise interference.
+ * @note On ESP32S2. There is an error in the IIR calculation. The magnitude of the error is twice the filter coefficient.
+ *       So please select a smaller filter coefficient on the basis of meeting the filtering requirements.
+ *       Recommended filter coefficient selection `IIR_2`.
+ */
+typedef enum {
+    TOUCH_PAD_SMOOTH_OFF   = 0, /*!<No filtering of raw data. */
+    TOUCH_PAD_SMOOTH_IIR_2 = 1, /*!<Filter the raw data. The coefficient is 2 (Typical value). */
+    TOUCH_PAD_SMOOTH_IIR_4 = 2, /*!<Filter the raw data. The coefficient is 4. */
+    TOUCH_PAD_SMOOTH_IIR_8 = 3, /*!<Filter the raw data. The coefficient is 8. */
+    TOUCH_PAD_SMOOTH_MAX,
+} touch_smooth_mode_t;
+
+/** Touch sensor filter configuration */
+typedef struct touch_filter_config {
+    touch_filter_mode_t mode;   /*!<Set filter mode. The input of the filter is the raw value of touch reading,
+                                    and the output of the filter is involved in the judgment of the touch state. */
+    uint32_t debounce_cnt;      /*!<Set debounce count, such as `n`. If the measured values continue to exceed
+                                    the threshold for `n+1` times, the touch sensor state changes.
+                                    Range: 0 ~ 7 */
+    uint32_t noise_thr;         /*!<Noise threshold coefficient. Higher = More noise resistance.
+                                    The actual noise should be less than (noise coefficient * touch threshold).
+                                    Range: 0 ~ 3. The coefficient is 0: 4/8;  1: 3/8;   2: 2/8;   3: 1; */
+    uint32_t jitter_step;       /*!<Set jitter filter step size. Range: 0 ~ 15 */
+    touch_smooth_mode_t smh_lvl;/*!<Level of filter applied on the original data against large noise interference. */
+#define TOUCH_DEBOUNCE_CNT_MAX      (7)
+#define TOUCH_NOISE_THR_MAX         (3)
+#define TOUCH_JITTER_STEP_MAX       (15)
+} touch_filter_config_t;
+
+/** Touch sensor channel sleep configuration */
+typedef struct {
+    touch_pad_t touch_num;          /*!<Set touch channel number for sleep pad.
+                                        Only one touch sensor channel is supported in deep sleep mode.
+                                        If clear the sleep channel, point this pad to `TOUCH_PAD_NUM0`  */
+    bool en_proximity;              /*!<enable proximity function for sleep pad */
+} touch_pad_sleep_channel_t;
+
+#endif // !CONFIG_IDF_TARGET_ESP32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/include/hal/touch_sensor_types.h b/components/hal/include/hal/touch_sensor_types.h
deleted file mode 100644
index dac11762f3e..00000000000
--- a/components/hal/include/hal/touch_sensor_types.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "sdkconfig.h"
-#include "esp_attr.h"
-#include "esp_bit_defs.h"
-#include "soc/soc_caps.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Touch pad channel */
-typedef enum {
-    TOUCH_PAD_NUM0 = 0, /*!< Touch pad channel 0 is GPIO4(ESP32) */
-    TOUCH_PAD_NUM1,     /*!< Touch pad channel 1 is GPIO0(ESP32) / GPIO1(ESP32-S2) */
-    TOUCH_PAD_NUM2,     /*!< Touch pad channel 2 is GPIO2(ESP32) / GPIO2(ESP32-S2) */
-    TOUCH_PAD_NUM3,     /*!< Touch pad channel 3 is GPIO15(ESP32) / GPIO3(ESP32-S2) */
-    TOUCH_PAD_NUM4,     /*!< Touch pad channel 4 is GPIO13(ESP32) / GPIO4(ESP32-S2) */
-    TOUCH_PAD_NUM5,     /*!< Touch pad channel 5 is GPIO12(ESP32) / GPIO5(ESP32-S2) */
-    TOUCH_PAD_NUM6,     /*!< Touch pad channel 6 is GPIO14(ESP32) / GPIO6(ESP32-S2) */
-    TOUCH_PAD_NUM7,     /*!< Touch pad channel 7 is GPIO27(ESP32) / GPIO7(ESP32-S2) */
-    TOUCH_PAD_NUM8,     /*!< Touch pad channel 8 is GPIO33(ESP32) / GPIO8(ESP32-S2) */
-    TOUCH_PAD_NUM9,     /*!< Touch pad channel 9 is GPIO32(ESP32) / GPIO9(ESP32-S2) */
-#if SOC_TOUCH_SENSOR_NUM > 10
-    TOUCH_PAD_NUM10,    /*!< Touch channel 10 is GPIO10(ESP32-S2) */
-    TOUCH_PAD_NUM11,    /*!< Touch channel 11 is GPIO11(ESP32-S2) */
-    TOUCH_PAD_NUM12,    /*!< Touch channel 12 is GPIO12(ESP32-S2) */
-    TOUCH_PAD_NUM13,    /*!< Touch channel 13 is GPIO13(ESP32-S2) */
-    TOUCH_PAD_NUM14,    /*!< Touch channel 14 is GPIO14(ESP32-S2) */
-#endif
-    TOUCH_PAD_MAX,
-} touch_pad_t;
-
-/** Touch sensor high reference voltage */
-typedef enum {
-    TOUCH_HVOLT_KEEP = -1, /*!<Touch sensor high reference voltage, no change  */
-    TOUCH_HVOLT_2V4 = 0,   /*!<Touch sensor high reference voltage, 2.4V  */
-    TOUCH_HVOLT_2V5,       /*!<Touch sensor high reference voltage, 2.5V  */
-    TOUCH_HVOLT_2V6,       /*!<Touch sensor high reference voltage, 2.6V  */
-    TOUCH_HVOLT_2V7,       /*!<Touch sensor high reference voltage, 2.7V  */
-    TOUCH_HVOLT_MAX,
-} touch_high_volt_t;
-
-/** Touch sensor low reference voltage */
-typedef enum {
-    TOUCH_LVOLT_KEEP = -1, /*!<Touch sensor low reference voltage, no change  */
-    TOUCH_LVOLT_0V5 = 0,   /*!<Touch sensor low reference voltage, 0.5V  */
-    TOUCH_LVOLT_0V6,       /*!<Touch sensor low reference voltage, 0.6V  */
-    TOUCH_LVOLT_0V7,       /*!<Touch sensor low reference voltage, 0.7V  */
-    TOUCH_LVOLT_0V8,       /*!<Touch sensor low reference voltage, 0.8V  */
-    TOUCH_LVOLT_MAX,
-} touch_low_volt_t;
-
-/** Touch sensor high reference voltage attenuation */
-typedef enum {
-    TOUCH_HVOLT_ATTEN_KEEP = -1,  /*!<Touch sensor high reference voltage attenuation, no change  */
-    TOUCH_HVOLT_ATTEN_1V5 = 0,    /*!<Touch sensor high reference voltage attenuation, 1.5V attenuation  */
-    TOUCH_HVOLT_ATTEN_1V,         /*!<Touch sensor high reference voltage attenuation, 1.0V attenuation  */
-    TOUCH_HVOLT_ATTEN_0V5,        /*!<Touch sensor high reference voltage attenuation, 0.5V attenuation  */
-    TOUCH_HVOLT_ATTEN_0V,         /*!<Touch sensor high reference voltage attenuation,   0V attenuation  */
-    TOUCH_HVOLT_ATTEN_MAX,
-} touch_volt_atten_t;
-
-/** Touch sensor charge/discharge speed */
-typedef enum {
-    TOUCH_PAD_SLOPE_0 = 0,       /*!<Touch sensor charge / discharge speed, always zero  */
-    TOUCH_PAD_SLOPE_1 = 1,       /*!<Touch sensor charge / discharge speed, slowest  */
-    TOUCH_PAD_SLOPE_2 = 2,       /*!<Touch sensor charge / discharge speed */
-    TOUCH_PAD_SLOPE_3 = 3,       /*!<Touch sensor charge / discharge speed  */
-    TOUCH_PAD_SLOPE_4 = 4,       /*!<Touch sensor charge / discharge speed  */
-    TOUCH_PAD_SLOPE_5 = 5,       /*!<Touch sensor charge / discharge speed  */
-    TOUCH_PAD_SLOPE_6 = 6,       /*!<Touch sensor charge / discharge speed  */
-    TOUCH_PAD_SLOPE_7 = 7,       /*!<Touch sensor charge / discharge speed, fast  */
-    TOUCH_PAD_SLOPE_MAX,
-} touch_cnt_slope_t;
-
-/** Touch sensor initial charge level */
-typedef enum {
-    TOUCH_PAD_TIE_OPT_LOW = 0,    /*!<Initial level of charging voltage, low level */
-    TOUCH_PAD_TIE_OPT_HIGH = 1,   /*!<Initial level of charging voltage, high level */
-    TOUCH_PAD_TIE_OPT_MAX,
-} touch_tie_opt_t;
-
-/** Touch sensor FSM mode */
-typedef enum {
-    TOUCH_FSM_MODE_TIMER = 0,   /*!<To start touch FSM by timer */
-    TOUCH_FSM_MODE_SW,          /*!<To start touch FSM by software trigger */
-    TOUCH_FSM_MODE_MAX,
-} touch_fsm_mode_t;
-
-/**** ESP32 Only *****/
-
-typedef enum {
-    TOUCH_TRIGGER_BELOW = 0,   /*!<Touch interrupt will happen if counter value is less than threshold.*/
-    TOUCH_TRIGGER_ABOVE = 1,   /*!<Touch interrupt will happen if counter value is larger than threshold.*/
-    TOUCH_TRIGGER_MAX,
-} touch_trigger_mode_t;
-
-typedef enum {
-    TOUCH_TRIGGER_SOURCE_BOTH = 0,  /*!< wakeup interrupt is generated if both SET1 and SET2 are "touched"*/
-    TOUCH_TRIGGER_SOURCE_SET1 = 1,  /*!< wakeup interrupt is generated if SET1 is "touched"*/
-    TOUCH_TRIGGER_SOURCE_MAX,
-} touch_trigger_src_t;
-
-/********************************/
-#define TOUCH_PAD_BIT_MASK_ALL              ((1<<SOC_TOUCH_SENSOR_NUM)-1)
-#define TOUCH_PAD_SLOPE_DEFAULT             (TOUCH_PAD_SLOPE_7)
-#define TOUCH_PAD_TIE_OPT_DEFAULT           (TOUCH_PAD_TIE_OPT_LOW)
-#define TOUCH_PAD_BIT_MASK_MAX              (TOUCH_PAD_BIT_MASK_ALL)
-#define TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD    (TOUCH_HVOLT_2V7)
-#define TOUCH_PAD_LOW_VOLTAGE_THRESHOLD     (TOUCH_LVOLT_0V5)
-#define TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD   (TOUCH_HVOLT_ATTEN_0V5)
-#define TOUCH_PAD_IDLE_CH_CONNECT_DEFAULT   (TOUCH_PAD_CONN_GND)
-#if SOC_TOUCH_SENSOR_VERSION == 1
-#define TOUCH_PAD_THRESHOLD_MAX             (0)         /*!< If set touch threshold max value, The touch sensor can't be in touched status */
-#elif SOC_TOUCH_SENSOR_VERSION == 2
-#define TOUCH_PAD_THRESHOLD_MAX             (0x1FFFFF)  /*!< If set touch threshold max value, The touch sensor can't be in touched status */
-#elif SOC_TOUCH_SENSOR_VERSION == 3
-#define TOUCH_PAD_THRESHOLD_MAX             (0xFFFF)    /*!< If set touch threshold max value, The touch sensor can't be in touched status */
-#endif
-
-#ifdef CONFIG_IDF_TARGET_ESP32
-
-#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT   (0x1000)  /*!<The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options), max value is 0xffff */
-#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (0x7fff)  /*!<The timer frequency is 8Mhz, the max value is 0x7fff */
-#define TOUCH_FSM_MODE_DEFAULT          (TOUCH_FSM_MODE_SW)  /*!<The touch FSM my be started by the software or timer */
-#define TOUCH_TRIGGER_MODE_DEFAULT      (TOUCH_TRIGGER_BELOW)   /*!<Interrupts can be triggered if sensor value gets below or above threshold */
-#define TOUCH_TRIGGER_SOURCE_DEFAULT    (TOUCH_TRIGGER_SOURCE_SET1)  /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */
-
-#endif // CONFIG_IDF_TARGET ESP32
-
-#if !CONFIG_IDF_TARGET_ESP32
-/**
- * Excessive total time will slow down the touch response.
- * Too small measurement time will not be sampled enough, resulting in inaccurate measurements.
- *
- * @note The greater the duty cycle of the measurement time, the more system power is consumed.
- */
-#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT   (0xf)   /*!<The number of sleep cycle in each measure process of touch channels.
-                                                    The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options).
-                                                    Range: 0 ~ 0xffff */
-#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (500)   /*!<The times of charge and discharge in each measure process of touch channels.
-                                                    The timer frequency is 8Mhz.
-                                                    Recommended typical value: Modify this value to make the measurement time around 1ms.
-                                                    Range: 0 ~ 0xffff */
-
-// TODO: replace by ll macro
-typedef enum {
-    TOUCH_PAD_INTR_MASK_DONE = BIT(0),      /*!<Measurement done for one of the enabled channels. */
-    TOUCH_PAD_INTR_MASK_ACTIVE = BIT(1),    /*!<Active for one of the enabled channels. */
-    TOUCH_PAD_INTR_MASK_INACTIVE = BIT(2),  /*!<Inactive for one of the enabled channels. */
-    TOUCH_PAD_INTR_MASK_SCAN_DONE = BIT(3), /*!<Measurement done for all the enabled channels. */
-    TOUCH_PAD_INTR_MASK_TIMEOUT = BIT(4),   /*!<Timeout for one of the enabled channels. */
-#if SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED
-    TOUCH_PAD_INTR_MASK_PROXI_MEAS_DONE = BIT(5),   /*!<For proximity sensor, when the number of measurements reaches the set count of measurements, an interrupt will be generated. */
-    TOUCH_PAD_INTR_MASK_MAX
-#define TOUCH_PAD_INTR_MASK_ALL (TOUCH_PAD_INTR_MASK_TIMEOUT    \
-                                | TOUCH_PAD_INTR_MASK_SCAN_DONE \
-                                | TOUCH_PAD_INTR_MASK_INACTIVE  \
-                                | TOUCH_PAD_INTR_MASK_ACTIVE    \
-                                | TOUCH_PAD_INTR_MASK_DONE      \
-                                | TOUCH_PAD_INTR_MASK_PROXI_MEAS_DONE) /*!<All touch interrupt type enable. */
-#else
-    TOUCH_PAD_INTR_MASK_MAX
-#define TOUCH_PAD_INTR_MASK_ALL (TOUCH_PAD_INTR_MASK_TIMEOUT    \
-                                | TOUCH_PAD_INTR_MASK_SCAN_DONE \
-                                | TOUCH_PAD_INTR_MASK_INACTIVE  \
-                                | TOUCH_PAD_INTR_MASK_ACTIVE    \
-                                | TOUCH_PAD_INTR_MASK_DONE) /*!<All touch interrupt type enable. */
-#endif
-} touch_pad_intr_mask_t;
-
-typedef enum {
-    TOUCH_PAD_DENOISE_BIT12 = 0,    /*!<Denoise range is 12bit */
-    TOUCH_PAD_DENOISE_BIT10 = 1,    /*!<Denoise range is 10bit */
-    TOUCH_PAD_DENOISE_BIT8 = 2,     /*!<Denoise range is 8bit */
-    TOUCH_PAD_DENOISE_BIT4 = 3,     /*!<Denoise range is 4bit */
-    TOUCH_PAD_DENOISE_MAX
-} touch_pad_denoise_grade_t;
-
-typedef enum {
-    TOUCH_PAD_DENOISE_CAP_L0 = 0,   /*!<Denoise channel internal reference capacitance is 5pf */
-    TOUCH_PAD_DENOISE_CAP_L1 = 1,   /*!<Denoise channel internal reference capacitance is 6.4pf */
-    TOUCH_PAD_DENOISE_CAP_L2 = 2,   /*!<Denoise channel internal reference capacitance is 7.8pf */
-    TOUCH_PAD_DENOISE_CAP_L3 = 3,   /*!<Denoise channel internal reference capacitance is 9.2pf */
-    TOUCH_PAD_DENOISE_CAP_L4 = 4,   /*!<Denoise channel internal reference capacitance is 10.6pf */
-    TOUCH_PAD_DENOISE_CAP_L5 = 5,   /*!<Denoise channel internal reference capacitance is 12.0pf */
-    TOUCH_PAD_DENOISE_CAP_L6 = 6,   /*!<Denoise channel internal reference capacitance is 13.4pf */
-    TOUCH_PAD_DENOISE_CAP_L7 = 7,   /*!<Denoise channel internal reference capacitance is 14.8pf */
-    TOUCH_PAD_DENOISE_CAP_MAX = 8
-} touch_pad_denoise_cap_t;
-
-/** Touch sensor denoise configuration */
-typedef struct touch_pad_denoise {
-    touch_pad_denoise_grade_t grade;    /*!<Select denoise range of denoise channel.
-                                            Determined by measuring the noise amplitude of the denoise channel. */
-    touch_pad_denoise_cap_t cap_level;  /*!<Select internal reference capacitance of denoise channel.
-                                            Ensure that the denoise readings are closest to the readings of the channel being measured.
-                                            Use `touch_pad_denoise_read_data` to get the reading of denoise channel.
-                                            The equivalent capacitance of the shielded channel can be calculated
-                                            from the reading of denoise channel. */
-} touch_pad_denoise_t;
-
-/** Touch sensor shield channel drive capability level */
-typedef enum {
-    TOUCH_PAD_SHIELD_DRV_L0 = 0,/*!<The max equivalent capacitance in shield channel is 40pf */
-    TOUCH_PAD_SHIELD_DRV_L1,    /*!<The max equivalent capacitance in shield channel is 80pf */
-    TOUCH_PAD_SHIELD_DRV_L2,    /*!<The max equivalent capacitance in shield channel is 120pf */
-    TOUCH_PAD_SHIELD_DRV_L3,    /*!<The max equivalent capacitance in shield channel is 160pf */
-    TOUCH_PAD_SHIELD_DRV_L4,    /*!<The max equivalent capacitance in shield channel is 200pf */
-    TOUCH_PAD_SHIELD_DRV_L5,    /*!<The max equivalent capacitance in shield channel is 240pf */
-    TOUCH_PAD_SHIELD_DRV_L6,    /*!<The max equivalent capacitance in shield channel is 280pf */
-    TOUCH_PAD_SHIELD_DRV_L7,    /*!<The max equivalent capacitance in shield channel is 320pf */
-    TOUCH_PAD_SHIELD_DRV_MAX
-} touch_pad_shield_driver_t;
-
-/** Touch sensor waterproof configuration */
-typedef struct touch_pad_waterproof {
-    touch_pad_t guard_ring_pad;             /*!<Waterproof. Select touch channel use for guard pad.
-                                                Guard pad is used to detect the large area of water covering the touch panel. */
-    touch_pad_shield_driver_t shield_driver;/*!<Waterproof. Shield channel drive capability configuration.
-                                                Shield pad is used to shield the influence of water droplets covering the touch panel.
-                                                When the waterproof function is enabled, Touch14 is set as shield channel by default.
-                                                The larger the parasitic capacitance on the shielding channel, the higher the drive capability needs to be set.
-                                                The equivalent capacitance of the shield channel can be estimated through the reading value of the denoise channel(Touch0).*/
-} touch_pad_waterproof_t;
-
-/** Touch sensor proximity detection configuration */
-#define TOUCH_PROXIMITY_MEAS_NUM_MAX (0xFF)
-
-/** Touch channel idle state configuration */
-typedef enum {
-    TOUCH_PAD_CONN_HIGHZ = 0,   /*!<Idle status of touch channel is high resistance state */
-    TOUCH_PAD_CONN_GND = 1,     /*!<Idle status of touch channel is ground connection */
-    TOUCH_PAD_CONN_MAX
-} touch_pad_conn_type_t;
-
-/**
- * @brief Touch channel IIR filter coefficient configuration.
- * @note On ESP32S2. There is an error in the IIR calculation. The magnitude of the error is twice the filter coefficient.
- *       So please select a smaller filter coefficient on the basis of meeting the filtering requirements.
- *       Recommended filter coefficient selection `IIR_16`.
- */
-typedef enum {
-    TOUCH_PAD_FILTER_IIR_4 = 0, /*!<The filter mode is first-order IIR filter. The coefficient is 4. */
-    TOUCH_PAD_FILTER_IIR_8,     /*!<The filter mode is first-order IIR filter. The coefficient is 8. */
-    TOUCH_PAD_FILTER_IIR_16,    /*!<The filter mode is first-order IIR filter. The coefficient is 16 (Typical value). */
-    TOUCH_PAD_FILTER_IIR_32,    /*!<The filter mode is first-order IIR filter. The coefficient is 32. */
-    TOUCH_PAD_FILTER_IIR_64,    /*!<The filter mode is first-order IIR filter. The coefficient is 64. */
-    TOUCH_PAD_FILTER_IIR_128,   /*!<The filter mode is first-order IIR filter. The coefficient is 128. */
-    TOUCH_PAD_FILTER_IIR_256,   /*!<The filter mode is first-order IIR filter. The coefficient is 256. */
-    TOUCH_PAD_FILTER_JITTER,    /*!<The filter mode is jitter filter */
-    TOUCH_PAD_FILTER_MAX
-} touch_filter_mode_t;
-
-/**
- * @brief Level of filter applied on the original data against large noise interference.
- * @note On ESP32S2. There is an error in the IIR calculation. The magnitude of the error is twice the filter coefficient.
- *       So please select a smaller filter coefficient on the basis of meeting the filtering requirements.
- *       Recommended filter coefficient selection `IIR_2`.
- */
-typedef enum {
-    TOUCH_PAD_SMOOTH_OFF   = 0, /*!<No filtering of raw data. */
-    TOUCH_PAD_SMOOTH_IIR_2 = 1, /*!<Filter the raw data. The coefficient is 2 (Typical value). */
-    TOUCH_PAD_SMOOTH_IIR_4 = 2, /*!<Filter the raw data. The coefficient is 4. */
-    TOUCH_PAD_SMOOTH_IIR_8 = 3, /*!<Filter the raw data. The coefficient is 8. */
-    TOUCH_PAD_SMOOTH_MAX,
-} touch_smooth_mode_t;
-
-#if SOC_TOUCH_SENSOR_VERSION == 3
-/**
- * @brief Touch channel counting mode of the binarized touch output
- *
- */
-typedef enum {
-    TOUCH_PAD_OUT_AS_DATA,      /*!< Counting the output of touch channel as data.
-                                 *   The value will be smaller than actual value but more sensitive when the frequency of touch_out is close to the source clock
-                                 *   Normally we treat the output as data when it is lower than the sample clock
-                                 */
-    TOUCH_PAD_OUT_AS_CLOCK,     /*!< Counting the output of touch channel as clock.
-                                 *   The value is accurate but less sensitive when the frequency of touch_out is close to the source clock
-                                 *   Normally we treat the output as clock when it is higher than the sample clock
-                                 */
-} touch_out_mode_t;
-#endif
-
-/** Touch sensor filter configuration */
-typedef struct touch_filter_config {
-    touch_filter_mode_t mode;   /*!<Set filter mode. The input of the filter is the raw value of touch reading,
-                                    and the output of the filter is involved in the judgment of the touch state. */
-    uint32_t debounce_cnt;      /*!<Set debounce count, such as `n`. If the measured values continue to exceed
-                                    the threshold for `n+1` times, the touch sensor state changes.
-                                    Range: 0 ~ 7 */
-    uint32_t noise_thr;         /*!<Noise threshold coefficient. Higher = More noise resistance.
-                                    The actual noise should be less than (noise coefficient * touch threshold).
-                                    Range: 0 ~ 3. The coefficient is 0: 4/8;  1: 3/8;   2: 2/8;   3: 1; */
-    uint32_t jitter_step;       /*!<Set jitter filter step size. Range: 0 ~ 15 */
-    touch_smooth_mode_t smh_lvl;/*!<Level of filter applied on the original data against large noise interference. */
-#define TOUCH_DEBOUNCE_CNT_MAX      (7)
-#define TOUCH_NOISE_THR_MAX         (3)
-#define TOUCH_JITTER_STEP_MAX       (15)
-} touch_filter_config_t;
-
-/** Touch sensor channel sleep configuration */
-typedef struct {
-    touch_pad_t touch_num;          /*!<Set touch channel number for sleep pad.
-                                        Only one touch sensor channel is supported in deep sleep mode.
-                                        If clear the sleep channel, point this pad to `TOUCH_PAD_NUM0`  */
-    bool en_proximity;              /*!<enable proximity function for sleep pad */
-} touch_pad_sleep_channel_t;
-
-#endif // !CONFIG_IDF_TARGET_ESP32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/hal/include/hal/usb_dwc_hal.h b/components/hal/include/hal/usb_dwc_hal.h
index 33ac57be75e..d4c880571f7 100644
--- a/components/hal/include/hal/usb_dwc_hal.h
+++ b/components/hal/include/hal/usb_dwc_hal.h
@@ -171,13 +171,23 @@ typedef struct {
  * @brief HAL context structure
  */
 typedef struct {
-    //Context
-    usb_dwc_dev_t *dev;                            /**< Pointer to base address of DWC_OTG registers */
-    //Host Port related
-    uint32_t *periodic_frame_list;                 /**< Pointer to scheduling frame list */
-    usb_hal_frame_list_len_t frame_list_len;       /**< Length of the periodic scheduling frame list */
-    //FIFO related
-    usb_dwc_hal_fifo_config_t fifo_config;         /**< FIFO sizes configuration */
+    // HW context
+    usb_dwc_dev_t *dev;                         /**< Pointer to base address of DWC_OTG registers */
+
+    // Host Port related
+    uint32_t *periodic_frame_list;              /**< Pointer to scheduling frame list */
+    usb_hal_frame_list_len_t frame_list_len;    /**< Length of the periodic scheduling frame list */
+
+    // FIFO related
+    usb_dwc_hal_fifo_config_t fifo_config;      /**< FIFO sizes configuration */
+
+    // Configuration of the USB-DWC core. Read from read-only HW registers
+    struct {
+        unsigned chan_num_total;                /**< Total number of channels for this configuration */
+        unsigned hsphy_type;                    /**< HS PHY type of this configuration */
+        unsigned fifo_size;                     /**< Total FIFO size [in lines] in this configuration */
+    } constant_config;
+
     union {
         struct {
             uint32_t dbnc_lock_enabled: 1;      /**< Debounce lock enabled */
@@ -188,11 +198,12 @@ typedef struct {
         };
         uint32_t val;
     } flags;
-    //Channel related
+
+    // Channel related
     struct {
-        int num_allocd;                             /**< Number of channels currently allocated */
-        uint32_t chan_pend_intrs_msk;               /**< Bit mask of channels with pending interrupts */
-        usb_dwc_hal_chan_t *hdls[OTG_NUM_HOST_CHAN];    /**< Handles of each channel. Set to NULL if channel has not been allocated */
+        int num_allocated;                      /**< Number of channels currently allocated */
+        uint32_t chan_pend_intrs_msk;           /**< Bit mask of channels with pending interrupts */
+        usb_dwc_hal_chan_t **hdls;              /**< Handles of each channel. Set to NULL if channel has not been allocated */
     } channels;
 } usb_dwc_hal_context_t;
 
@@ -208,16 +219,20 @@ typedef struct {
  * - Interrupt allocated but DISABLED (in case of an unknown interrupt state)
  * Exit:
  * - Checks to see if DWC_OTG is alive, and if HW version/config is correct
- * - HAl context initialized
+ * - HAL context initialized
+ * - Read and save relevant USB-DWC configuration parameters
  * - Sets default values to some global and OTG registers (GAHBCFG and GUSBCFG)
  * - Umask global interrupt signal
  * - Put DWC_OTG into host mode. Require 25ms delay before this takes effect.
  * - State -> USB_DWC_HAL_PORT_STATE_OTG
  * - Interrupts cleared. Users can now enable their ISR
  *
- * @param[inout] hal Context of the HAL layer
+ * @attention The user must allocate memory for channel handlers with
+ *            `hal->channels.hdls = malloc(hal->constant_config.chan_num_total * sizeof(usb_dwc_hal_chan_t*))`
+ * @param[inout] hal     Context of the HAL layer
+ * @param[in]    port_id USB port ID
  */
-void usb_dwc_hal_init(usb_dwc_hal_context_t *hal);
+void usb_dwc_hal_init(usb_dwc_hal_context_t *hal, int port_id);
 
 /**
  * @brief Deinitialize the HAL context
@@ -241,7 +256,7 @@ void usb_dwc_hal_deinit(usb_dwc_hal_context_t *hal);
  *
  * @note This has nothing to do with a USB bus reset. It simply resets the peripheral
  *
- * @param hal Context of the HAL layer
+ * @param[in] hal Context of the HAL layer
  */
 void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal);
 
diff --git a/components/hal/include/hal/usb_dwc_ll.h b/components/hal/include/hal/usb_dwc_ll.h
deleted file mode 100644
index 49ade504051..00000000000
--- a/components/hal/include/hal/usb_dwc_ll.h
+++ /dev/null
@@ -1,999 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc/soc_caps.h"
-/*
-This header is shared across all targets. Resolve to an empty header for targets
-that don't support USB OTG.
-*/
-#if SOC_USB_OTG_SUPPORTED
-#include <stdint.h>
-#include <stdbool.h>
-#include "soc/usb_dwc_struct.h"
-#include "soc/usb_dwc_cfg.h"
-#include "hal/usb_dwc_types.h"
-#include "hal/misc.h"
-#endif // SOC_USB_OTG_SUPPORTED
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if SOC_USB_OTG_SUPPORTED
-
-/* -----------------------------------------------------------------------------
---------------------------------- DWC Constants --------------------------------
------------------------------------------------------------------------------ */
-
-#define USB_DWC_QTD_LIST_MEM_ALIGN              512
-#define USB_DWC_FRAME_LIST_MEM_ALIGN            512     // The frame list needs to be 512 bytes aligned (contrary to the databook)
-
-/* -----------------------------------------------------------------------------
-------------------------------- Global Registers -------------------------------
------------------------------------------------------------------------------ */
-
-/*
- * Interrupt bit masks of the GINTSTS and GINTMSK registers
- */
-#define USB_DWC_LL_INTR_CORE_WKUPINT        (1 << 31)
-#define USB_DWC_LL_INTR_CORE_SESSREQINT     (1 << 30)
-#define USB_DWC_LL_INTR_CORE_DISCONNINT     (1 << 29)
-#define USB_DWC_LL_INTR_CORE_CONIDSTSCHNG   (1 << 28)
-#define USB_DWC_LL_INTR_CORE_PTXFEMP        (1 << 26)
-#define USB_DWC_LL_INTR_CORE_HCHINT         (1 << 25)
-#define USB_DWC_LL_INTR_CORE_PRTINT         (1 << 24)
-#define USB_DWC_LL_INTR_CORE_RESETDET       (1 << 23)
-#define USB_DWC_LL_INTR_CORE_FETSUSP        (1 << 22)
-#define USB_DWC_LL_INTR_CORE_INCOMPIP       (1 << 21)
-#define USB_DWC_LL_INTR_CORE_INCOMPISOIN    (1 << 20)
-#define USB_DWC_LL_INTR_CORE_OEPINT         (1 << 19)
-#define USB_DWC_LL_INTR_CORE_IEPINT         (1 << 18)
-#define USB_DWC_LL_INTR_CORE_EPMIS          (1 << 17)
-#define USB_DWC_LL_INTR_CORE_EOPF           (1 << 15)
-#define USB_DWC_LL_INTR_CORE_ISOOUTDROP     (1 << 14)
-#define USB_DWC_LL_INTR_CORE_ENUMDONE       (1 << 13)
-#define USB_DWC_LL_INTR_CORE_USBRST         (1 << 12)
-#define USB_DWC_LL_INTR_CORE_USBSUSP        (1 << 11)
-#define USB_DWC_LL_INTR_CORE_ERLYSUSP       (1 << 10)
-#define USB_DWC_LL_INTR_CORE_GOUTNAKEFF     (1 << 7)
-#define USB_DWC_LL_INTR_CORE_GINNAKEFF      (1 << 6)
-#define USB_DWC_LL_INTR_CORE_NPTXFEMP       (1 << 5)
-#define USB_DWC_LL_INTR_CORE_RXFLVL         (1 << 4)
-#define USB_DWC_LL_INTR_CORE_SOF            (1 << 3)
-#define USB_DWC_LL_INTR_CORE_OTGINT         (1 << 2)
-#define USB_DWC_LL_INTR_CORE_MODEMIS        (1 << 1)
-#define USB_DWC_LL_INTR_CORE_CURMOD         (1 << 0)
-
-/*
- * Bit mask of interrupt generating bits of the the HPRT register. These bits
- * are ORd into the USB_DWC_LL_INTR_CORE_PRTINT interrupt.
- *
- * Note: Some fields of the HPRT are W1C (write 1 clear), this we cannot do a
- * simple read and write-back to clear the HPRT interrupt bits. Instead we need
- * a W1C mask the non-interrupt related bits
- */
-#define USB_DWC_LL_HPRT_W1C_MSK             (0x2E)
-#define USB_DWC_LL_HPRT_ENA_MSK             (0x04)
-#define USB_DWC_LL_INTR_HPRT_PRTOVRCURRCHNG (1 << 5)
-#define USB_DWC_LL_INTR_HPRT_PRTENCHNG      (1 << 3)
-#define USB_DWC_LL_INTR_HPRT_PRTCONNDET     (1 << 1)
-
-/*
- * Bit mask of channel interrupts (HCINTi and HCINTMSKi registers)
- *
- * Note: Under Scatter/Gather DMA mode, only the following interrupts can be unmasked
- * - DESC_LS_ROLL
- * - XCS_XACT_ERR (always unmasked)
- * - BNAINTR
- * - CHHLTD
- * - XFERCOMPL
- * The remaining interrupt bits will still be set (when the corresponding event occurs)
- * but will not generate an interrupt. Therefore we must proxy through the
- * USB_DWC_LL_INTR_CHAN_CHHLTD interrupt to check the other interrupt bits.
- */
-#define USB_DWC_LL_INTR_CHAN_DESC_LS_ROLL   (1 << 13)
-#define USB_DWC_LL_INTR_CHAN_XCS_XACT_ERR   (1 << 12)
-#define USB_DWC_LL_INTR_CHAN_BNAINTR        (1 << 11)
-#define USB_DWC_LL_INTR_CHAN_DATATGLERR     (1 << 10)
-#define USB_DWC_LL_INTR_CHAN_FRMOVRUN       (1 << 9)
-#define USB_DWC_LL_INTR_CHAN_BBLEER         (1 << 8)
-#define USB_DWC_LL_INTR_CHAN_XACTERR        (1 << 7)
-#define USB_DWC_LL_INTR_CHAN_NYET           (1 << 6)
-#define USB_DWC_LL_INTR_CHAN_ACK            (1 << 5)
-#define USB_DWC_LL_INTR_CHAN_NAK            (1 << 4)
-#define USB_DWC_LL_INTR_CHAN_STALL          (1 << 3)
-#define USB_DWC_LL_INTR_CHAN_AHBERR         (1 << 2)
-#define USB_DWC_LL_INTR_CHAN_CHHLTD         (1 << 1)
-#define USB_DWC_LL_INTR_CHAN_XFERCOMPL      (1 << 0)
-
-/*
- * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
- * Each QTD describes one transfer. Scatter gather mode will automatically split
- * a transfer into multiple MPS packets. Each QTD is 64bits in size
- *
- * Note: The status information part of the QTD is interpreted differently depending
- * on IN or OUT, and ISO or non-ISO
- */
-typedef struct {
-    union {
-        struct {
-            uint32_t xfer_size: 17;
-            uint32_t aqtd_offset: 6;
-            uint32_t aqtd_valid: 1;
-            uint32_t reserved_24: 1;
-            uint32_t intr_cplt: 1;
-            uint32_t eol: 1;
-            uint32_t reserved_27: 1;
-            uint32_t rx_status: 2;
-            uint32_t reserved_30: 1;
-            uint32_t active: 1;
-        } in_non_iso;
-        struct {
-            uint32_t xfer_size: 12;
-            uint32_t reserved_12_24: 13;
-            uint32_t intr_cplt: 1;
-            uint32_t reserved_26_27: 2;
-            uint32_t rx_status: 2;
-            uint32_t reserved_30: 1;
-            uint32_t active: 1;
-        } in_iso;
-        struct {
-            uint32_t xfer_size: 17;
-            uint32_t reserved_17_23: 7;
-            uint32_t is_setup: 1;
-            uint32_t intr_cplt: 1;
-            uint32_t eol: 1;
-            uint32_t reserved_27: 1;
-            uint32_t tx_status: 2;
-            uint32_t reserved_30: 1;
-            uint32_t active: 1;
-        } out_non_iso;
-        struct {
-            uint32_t xfer_size: 12;
-            uint32_t reserved_12_24: 13;
-            uint32_t intr_cplt: 1;
-            uint32_t eol: 1;
-            uint32_t reserved_27: 1;
-            uint32_t tx_status: 2;
-            uint32_t reserved_30: 1;
-            uint32_t active: 1;
-        } out_iso;
-        uint32_t buffer_status_val;
-    };
-    uint8_t *buffer;
-} usb_dwc_ll_dma_qtd_t;
-
-
-/* -----------------------------------------------------------------------------
-------------------------------- Global Registers -------------------------------
------------------------------------------------------------------------------ */
-
-// --------------------------- GAHBCFG Register --------------------------------
-
-static inline void usb_dwc_ll_gahbcfg_en_dma_mode(usb_dwc_dev_t *hw)
-{
-    hw->gahbcfg_reg.dmaen = 1;
-}
-
-static inline void usb_dwc_ll_gahbcfg_en_slave_mode(usb_dwc_dev_t *hw)
-{
-    hw->gahbcfg_reg.dmaen = 0;
-}
-
-static inline void usb_dwc_ll_gahbcfg_set_hbstlen(usb_dwc_dev_t *hw, uint32_t burst_len)
-{
-    hw->gahbcfg_reg.hbstlen = burst_len;
-}
-
-static inline void usb_dwc_ll_gahbcfg_en_global_intr(usb_dwc_dev_t *hw)
-{
-    hw->gahbcfg_reg.glbllntrmsk = 1;
-}
-
-static inline void usb_dwc_ll_gahbcfg_dis_global_intr(usb_dwc_dev_t *hw)
-{
-    hw->gahbcfg_reg.glbllntrmsk = 0;
-}
-
-// --------------------------- GUSBCFG Register --------------------------------
-
-static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
-{
-    hw->gusbcfg_reg.forcehstmode = 1;
-}
-
-static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw)
-{
-    hw->gusbcfg_reg.hnpcap = 0;
-}
-
-static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw)
-{
-    hw->gusbcfg_reg.srpcap = 0;
-}
-
-static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
-{
-    hw->gusbcfg_reg.toutcal = tout_cal;
-}
-
-#if (OTG_HSPHY_INTERFACE != 0)
-static inline void usb_dwc_ll_gusbcfg_set_utmi_phy(usb_dwc_dev_t *hw)
-{
-    hw->gusbcfg_reg.phyif = 1;       // 16 bits interface
-    hw->gusbcfg_reg.ulpiutmisel = 0; // UTMI+
-    hw->gusbcfg_reg.physel = 0;      // HS PHY
-}
-#endif // (OTG_HSPHY_INTERFACE != 0)
-
-// --------------------------- GRSTCTL Register --------------------------------
-
-static inline bool usb_dwc_ll_grstctl_is_ahb_idle(usb_dwc_dev_t *hw)
-{
-    return hw->grstctl_reg.ahbidle;
-}
-
-static inline bool usb_dwc_ll_grstctl_is_dma_req_in_progress(usb_dwc_dev_t *hw)
-{
-    return hw->grstctl_reg.dmareq;
-}
-
-static inline void usb_dwc_ll_grstctl_flush_nptx_fifo(usb_dwc_dev_t *hw)
-{
-    hw->grstctl_reg.txfnum = 0;     //Set the TX FIFO number to 0 to select the non-periodic TX FIFO
-    hw->grstctl_reg.txfflsh = 1;    //Flush the selected TX FIFO
-    //Wait for the flushing to complete
-    while (hw->grstctl_reg.txfflsh) {
-        ;
-    }
-}
-
-static inline void usb_dwc_ll_grstctl_flush_ptx_fifo(usb_dwc_dev_t *hw)
-{
-    hw->grstctl_reg.txfnum = 1;     //Set the TX FIFO number to 1 to select the periodic TX FIFO
-    hw->grstctl_reg.txfflsh = 1;    //FLush the select TX FIFO
-    //Wait for the flushing to complete
-    while (hw->grstctl_reg.txfflsh) {
-        ;
-    }
-}
-
-static inline void usb_dwc_ll_grstctl_flush_rx_fifo(usb_dwc_dev_t *hw)
-{
-    hw->grstctl_reg.rxfflsh = 1;
-    //Wait for the flushing to complete
-    while (hw->grstctl_reg.rxfflsh) {
-        ;
-    }
-}
-
-static inline void usb_dwc_ll_grstctl_reset_frame_counter(usb_dwc_dev_t *hw)
-{
-    hw->grstctl_reg.frmcntrrst = 1;
-}
-
-static inline void usb_dwc_ll_grstctl_core_soft_reset(usb_dwc_dev_t *hw)
-{
-    hw->grstctl_reg.csftrst = 1;
-}
-
-static inline bool usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(usb_dwc_dev_t *hw)
-{
-    return hw->grstctl_reg.csftrst;
-}
-
-// --------------------------- GINTSTS Register --------------------------------
-
-/**
- * @brief Reads and clears the global interrupt register
- *
- * @param hw Start address of the DWC_OTG registers
- * @return uint32_t Mask of interrupts
- */
-static inline uint32_t usb_dwc_ll_gintsts_read_and_clear_intrs(usb_dwc_dev_t *hw)
-{
-    usb_dwc_gintsts_reg_t gintsts;
-    gintsts.val = hw->gintsts_reg.val;
-    hw->gintsts_reg.val = gintsts.val;  //Write back to clear
-    return gintsts.val;
-}
-
-/**
- * @brief Clear specific interrupts
- *
- * @param hw Start address of the DWC_OTG registers
- * @param intr_msk Mask of interrupts to clear
- */
-static inline void usb_dwc_ll_gintsts_clear_intrs(usb_dwc_dev_t *hw, uint32_t intr_msk)
-{
-    //All GINTSTS fields are either W1C or read only. So safe to write directly
-    hw->gintsts_reg.val = intr_msk;
-}
-
-// --------------------------- GINTMSK Register --------------------------------
-
-static inline void usb_dwc_ll_gintmsk_en_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)
-{
-    hw->gintmsk_reg.val |= intr_mask;
-}
-
-static inline void usb_dwc_ll_gintmsk_dis_intrs(usb_dwc_dev_t *hw, uint32_t intr_mask)
-{
-    hw->gintmsk_reg.val &= ~intr_mask;
-}
-
-// --------------------------- GRXFSIZ Register --------------------------------
-
-static inline void usb_dwc_ll_grxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t num_lines)
-{
-    //Set size in words
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->grxfsiz_reg, rxfdep, num_lines);
-}
-
-// -------------------------- GNPTXFSIZ Register -------------------------------
-
-static inline void usb_dwc_ll_gnptxfsiz_set_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
-{
-    usb_dwc_gnptxfsiz_reg_t gnptxfsiz;
-    gnptxfsiz.val = hw->gnptxfsiz_reg.val;
-    HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfstaddr, addr);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(gnptxfsiz, nptxfdep, num_lines);
-    hw->gnptxfsiz_reg.val = gnptxfsiz.val;
-}
-
-// --------------------------- GSNPSID Register --------------------------------
-
-static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
-{
-    return hw->gsnpsid_reg.val;
-}
-
-// --------------------------- GHWCFGx Register --------------------------------
-
-/**
- * @brief Get the hardware configuration regiters of the DWC_OTG controller
- *
- * The hardware configuraiton regitsers are read only and indicate the various
- * features of the DWC_OTG core.
- *
- * @param hw Start address of the DWC_OTG registers
- * @param[out] ghwcfg1 Hardware configuration registesr 1
- * @param[out] ghwcfg2 Hardware configuration registesr 2
- * @param[out] ghwcfg3 Hardware configuration registesr 3
- * @param[out] ghwcfg4 Hardware configuration registesr 4
- */
-static inline void usb_dwc_ll_ghwcfg_get_hw_config(usb_dwc_dev_t *hw, uint32_t *ghwcfg1, uint32_t *ghwcfg2, uint32_t *ghwcfg3, uint32_t *ghwcfg4)
-{
-    *ghwcfg1 = hw->ghwcfg1_reg.val;
-    *ghwcfg2 = hw->ghwcfg2_reg.val;
-    *ghwcfg3 = hw->ghwcfg3_reg.val;
-    *ghwcfg4 = hw->ghwcfg4_reg.val;
-}
-
-// --------------------------- HPTXFSIZ Register -------------------------------
-
-static inline void usb_dwc_ll_hptxfsiz_set_ptx_fifo_size(usb_dwc_dev_t *hw, uint32_t addr, uint32_t num_lines)
-{
-    usb_dwc_hptxfsiz_reg_t hptxfsiz;
-    hptxfsiz.val = hw->hptxfsiz_reg.val;
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfstaddr, addr);
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hptxfsiz, ptxfsize, num_lines);
-    hw->hptxfsiz_reg.val = hptxfsiz.val;
-}
-
-/* -----------------------------------------------------------------------------
--------------------------------- Host Registers --------------------------------
------------------------------------------------------------------------------ */
-
-// ----------------------------- HCFG Register ---------------------------------
-
-static inline void usb_dwc_ll_hcfg_en_perio_sched(usb_dwc_dev_t *hw)
-{
-    hw->hcfg_reg.perschedena = 1;
-}
-
-static inline void usb_dwc_ll_hcfg_dis_perio_sched(usb_dwc_dev_t *hw)
-{
-    hw->hcfg_reg.perschedena = 0;
-}
-
-/**
- * Sets the length of the frame list
- *
- * @param num_entires Number of entires in the frame list
- */
-static inline void usb_dwc_ll_hcfg_set_num_frame_list_entries(usb_dwc_dev_t *hw, usb_hal_frame_list_len_t num_entries)
-{
-    uint32_t frlisten;
-    switch (num_entries) {
-        case USB_HAL_FRAME_LIST_LEN_8:
-            frlisten = 0;
-            break;
-        case USB_HAL_FRAME_LIST_LEN_16:
-            frlisten = 1;
-            break;
-        case USB_HAL_FRAME_LIST_LEN_32:
-            frlisten = 2;
-            break;
-        default: //USB_HAL_FRAME_LIST_LEN_64
-            frlisten = 3;
-            break;
-    }
-    hw->hcfg_reg.frlisten = frlisten;
-}
-
-static inline void usb_dwc_ll_hcfg_en_scatt_gatt_dma(usb_dwc_dev_t *hw)
-{
-    hw->hcfg_reg.descdma = 1;
-}
-
-static inline void usb_dwc_ll_hcfg_set_fsls_supp_only(usb_dwc_dev_t *hw)
-{
-    hw->hcfg_reg.fslssupp = 1;
-}
-
-static inline void usb_dwc_ll_hcfg_set_fsls_pclk_sel(usb_dwc_dev_t *hw)
-{
-    hw->hcfg_reg.fslspclksel = 1;
-}
-
-/**
- * @brief Sets some default values to HCFG to operate in Host mode with scatter/gather DMA
- *
- * @param[in] hw    Start address of the DWC_OTG registers
- * @param[in] speed Speed to initialize the host port at
- */
-static inline void usb_dwc_ll_hcfg_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
-{
-    hw->hcfg_reg.descdma = 1;   //Enable scatt/gatt
-#if (OTG_HSPHY_INTERFACE == 0)
-    /*
-    Indicate to the OTG core what speed the PHY clock is at
-    Note: It seems like S2/S3 PHY has an implicit 8 divider applied when in LS mode,
-          so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
-    */
-    hw->hcfg_reg.fslspclksel = (speed == USB_DWC_SPEED_FULL) ? 1 : 2;  //PHY clock on esp32-sx for FS/LS-only
-#endif // (OTG_HSPHY_INTERFACE == 0)
-    hw->hcfg_reg.perschedena = 0;   //Disable perio sched
-}
-
-// ----------------------------- HFIR Register ---------------------------------
-
-static inline void usb_dwc_ll_hfir_set_defaults(usb_dwc_dev_t *hw, usb_dwc_speed_t speed)
-{
-#if (OTG_HSPHY_INTERFACE == 0)
-    usb_dwc_hfir_reg_t hfir;
-    hfir.val = hw->hfir_reg.val;
-    hfir.hfirrldctrl = 0;       //Disable dynamic loading
-    /*
-    Set frame interval to be equal to 1ms
-    Note: It seems like our PHY has an implicit 8 divider applied when in LS mode,
-          so the values of FSLSPclkSel and FrInt have to be adjusted accordingly.
-    */
-    hfir.frint = (speed == USB_DWC_SPEED_FULL) ? 48000 : 6000; //esp32-sx targets only support FS or LS
-    hw->hfir_reg.val = hfir.val;
-#endif // (OTG_HSPHY_INTERFACE == 0)
-}
-
-// ----------------------------- HFNUM Register --------------------------------
-
-static inline uint32_t usb_dwc_ll_hfnum_get_frame_time_rem(usb_dwc_dev_t *hw)
-{
-    return HAL_FORCE_READ_U32_REG_FIELD(hw->hfnum_reg, frrem);
-}
-
-static inline uint32_t usb_dwc_ll_hfnum_get_frame_num(usb_dwc_dev_t *hw)
-{
-    return hw->hfnum_reg.frnum;
-}
-
-// ---------------------------- HPTXSTS Register -------------------------------
-
-static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_top(usb_dwc_dev_t *hw)
-{
-    return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxqtop);
-}
-
-static inline uint32_t usb_dwc_ll_hptxsts_get_ptxq_space_avail(usb_dwc_dev_t *hw)
-{
-    return hw->hptxsts_reg.ptxqspcavail;
-}
-
-static inline uint32_t usb_dwc_ll_ptxsts_get_ptxf_space_avail(usb_dwc_dev_t *hw)
-{
-    return HAL_FORCE_READ_U32_REG_FIELD(hw->hptxsts_reg, ptxfspcavail);
-}
-
-// ----------------------------- HAINT Register --------------------------------
-
-static inline uint32_t usb_dwc_ll_haint_get_chan_intrs(usb_dwc_dev_t *hw)
-{
-    return HAL_FORCE_READ_U32_REG_FIELD(hw->haint_reg, haint);
-}
-
-// --------------------------- HAINTMSK Register -------------------------------
-
-static inline void usb_dwc_ll_haintmsk_en_chan_intr(usb_dwc_dev_t *hw, uint32_t mask)
-{
-
-    hw->haintmsk_reg.val |= mask;
-}
-
-static inline void usb_dwc_ll_haintmsk_dis_chan_intr(usb_dwc_dev_t *hw, uint32_t mask)
-{
-    hw->haintmsk_reg.val &= ~mask;
-}
-
-// --------------------------- HFLBAddr Register -------------------------------
-
-/**
- * @brief Set the base address of the scheduling frame list
- *
- * @note For some reason, this address must be 512 bytes aligned or else a bunch of frames will not be scheduled when
- *       the frame list rolls over. However, according to the databook, there is no mention of the HFLBAddr needing to
- *       be aligned.
- *
- * @param hw Start address of the DWC_OTG registers
- * @param addr Base address of the scheduling frame list
- */
-static inline void usb_dwc_ll_hflbaddr_set_base_addr(usb_dwc_dev_t *hw, uint32_t addr)
-{
-    hw->hflbaddr_reg.hflbaddr = addr;
-}
-
-/**
- * @brief Get the base address of the scheduling frame list
- *
- * @param hw Start address of the DWC_OTG registers
- * @return uint32_t Base address of the scheduling frame list
- */
-static inline uint32_t usb_dwc_ll_hflbaddr_get_base_addr(usb_dwc_dev_t *hw)
-{
-    return hw->hflbaddr_reg.hflbaddr;
-}
-
-// ----------------------------- HPRT Register ---------------------------------
-
-static inline usb_dwc_speed_t usb_dwc_ll_hprt_get_speed(usb_dwc_dev_t *hw)
-{
-    return (usb_dwc_speed_t)hw->hprt_reg.prtspd;
-}
-
-static inline uint32_t usb_dwc_ll_hprt_get_test_ctl(usb_dwc_dev_t *hw)
-{
-    return hw->hprt_reg.prttstctl;
-}
-
-static inline void usb_dwc_ll_hprt_set_test_ctl(usb_dwc_dev_t *hw, uint32_t test_mode)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hprt.prttstctl = test_mode;
-    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
-}
-
-static inline void usb_dwc_ll_hprt_en_pwr(usb_dwc_dev_t *hw)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hprt.prtpwr = 1;
-    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
-}
-
-static inline void usb_dwc_ll_hprt_dis_pwr(usb_dwc_dev_t *hw)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hprt.prtpwr = 0;
-    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
-}
-
-static inline uint32_t usb_dwc_ll_hprt_get_pwr_line_status(usb_dwc_dev_t *hw)
-{
-    return hw->hprt_reg.prtlnsts;
-}
-
-static inline void usb_dwc_ll_hprt_set_port_reset(usb_dwc_dev_t *hw, bool reset)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hprt.prtrst = reset;
-    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
-}
-
-static inline bool usb_dwc_ll_hprt_get_port_reset(usb_dwc_dev_t *hw)
-{
-    return hw->hprt_reg.prtrst;
-}
-
-static inline void usb_dwc_ll_hprt_set_port_suspend(usb_dwc_dev_t *hw)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hprt.prtsusp = 1;
-    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
-}
-
-static inline bool usb_dwc_ll_hprt_get_port_suspend(usb_dwc_dev_t *hw)
-{
-    return hw->hprt_reg.prtsusp;
-}
-
-static inline void usb_dwc_ll_hprt_set_port_resume(usb_dwc_dev_t *hw)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hprt.prtres = 1;
-    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
-}
-
-static inline void usb_dwc_ll_hprt_clr_port_resume(usb_dwc_dev_t *hw)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hprt.prtres = 0;
-    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_W1C_MSK);
-}
-
-static inline bool usb_dwc_ll_hprt_get_port_resume(usb_dwc_dev_t *hw)
-{
-    return hw->hprt_reg.prtres;
-}
-
-static inline bool usb_dwc_ll_hprt_get_port_overcur(usb_dwc_dev_t *hw)
-{
-    return hw->hprt_reg.prtovrcurract;
-}
-
-static inline bool usb_dwc_ll_hprt_get_port_en(usb_dwc_dev_t *hw)
-{
-    return hw->hprt_reg.prtena;
-}
-
-static inline void usb_dwc_ll_hprt_port_dis(usb_dwc_dev_t *hw)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hprt.prtena = 1;        //W1C to disable
-    //we want to W1C ENA but not W1C the interrupt bits
-    hw->hprt_reg.val = hprt.val & ((~USB_DWC_LL_HPRT_W1C_MSK) | USB_DWC_LL_HPRT_ENA_MSK);
-}
-
-static inline bool usb_dwc_ll_hprt_get_conn_status(usb_dwc_dev_t *hw)
-{
-    return hw->hprt_reg.prtconnsts;
-}
-
-static inline uint32_t usb_dwc_ll_hprt_intr_read_and_clear(usb_dwc_dev_t *hw)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    //We want to W1C the interrupt bits but not that ENA
-    hw->hprt_reg.val = hprt.val & (~USB_DWC_LL_HPRT_ENA_MSK);
-    //Return only the interrupt bits
-    return (hprt.val & (USB_DWC_LL_HPRT_W1C_MSK & ~(USB_DWC_LL_HPRT_ENA_MSK)));
-}
-
-static inline void usb_dwc_ll_hprt_intr_clear(usb_dwc_dev_t *hw, uint32_t intr_mask)
-{
-    usb_dwc_hprt_reg_t hprt;
-    hprt.val = hw->hprt_reg.val;
-    hw->hprt_reg.val = ((hprt.val & ~USB_DWC_LL_HPRT_ENA_MSK) & ~USB_DWC_LL_HPRT_W1C_MSK) | intr_mask;
-}
-
-//Per Channel registers
-
-// --------------------------- HCCHARi Register --------------------------------
-
-static inline void usb_dwc_ll_hcchar_enable_chan(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    chan->hcchar_reg.chena = 1;
-}
-
-static inline bool usb_dwc_ll_hcchar_chan_is_enabled(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    return chan->hcchar_reg.chena;
-}
-
-static inline void usb_dwc_ll_hcchar_disable_chan(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    chan->hcchar_reg.chdis = 1;
-}
-
-static inline void usb_dwc_ll_hcchar_set_odd_frame(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    chan->hcchar_reg.oddfrm = 1;
-}
-
-static inline void usb_dwc_ll_hcchar_set_even_frame(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    chan->hcchar_reg.oddfrm = 0;
-}
-
-static inline void usb_dwc_ll_hcchar_set_dev_addr(volatile usb_dwc_host_chan_regs_t *chan, uint32_t addr)
-{
-    chan->hcchar_reg.devaddr = addr;
-}
-
-static inline void usb_dwc_ll_hcchar_set_ep_type(volatile usb_dwc_host_chan_regs_t *chan, usb_dwc_xfer_type_t type)
-{
-    chan->hcchar_reg.eptype = (uint32_t)type;
-}
-
-//Indicates whether channel is commuunicating with a LS device connected via a FS hub. Setting this bit to 1 will cause
-//each packet to be preceded by a PREamble packet
-static inline void usb_dwc_ll_hcchar_set_lspddev(volatile usb_dwc_host_chan_regs_t *chan, bool is_ls)
-{
-    chan->hcchar_reg.lspddev = is_ls;
-}
-
-static inline void usb_dwc_ll_hcchar_set_dir(volatile usb_dwc_host_chan_regs_t *chan, bool is_in)
-{
-    chan->hcchar_reg.epdir = is_in;
-}
-
-static inline void usb_dwc_ll_hcchar_set_ep_num(volatile usb_dwc_host_chan_regs_t *chan, uint32_t num)
-{
-    chan->hcchar_reg.epnum = num;
-}
-
-static inline void usb_dwc_ll_hcchar_set_mps(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mps)
-{
-    chan->hcchar_reg.mps = mps;
-}
-
-static inline void usb_dwc_ll_hcchar_init(volatile usb_dwc_host_chan_regs_t *chan, int dev_addr, int ep_num, int mps, usb_dwc_xfer_type_t type, bool is_in, bool is_ls)
-{
-    //Sets all persistent fields of the channel over its lifetimez
-    usb_dwc_ll_hcchar_set_dev_addr(chan, dev_addr);
-    usb_dwc_ll_hcchar_set_ep_type(chan, type);
-    usb_dwc_ll_hcchar_set_lspddev(chan, is_ls);
-    usb_dwc_ll_hcchar_set_dir(chan, is_in);
-    usb_dwc_ll_hcchar_set_ep_num(chan, ep_num);
-    usb_dwc_ll_hcchar_set_mps(chan, mps);
-}
-
-// ---------------------------- HCINTi Register --------------------------------
-
-static inline uint32_t usb_dwc_ll_hcint_read_and_clear_intrs(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    usb_dwc_hcint_reg_t hcint;
-    hcint.val = chan->hcint_reg.val;
-    chan->hcint_reg.val = hcint.val;
-    return hcint.val;
-}
-
-// --------------------------- HCINTMSKi Register ------------------------------
-
-static inline void usb_dwc_ll_hcintmsk_set_intr_mask(volatile usb_dwc_host_chan_regs_t *chan, uint32_t mask)
-{
-    chan->hcintmsk_reg.val = mask;
-}
-
-// ---------------------------- HCTSIZi Register -------------------------------
-
-static inline void usb_dwc_ll_hctsiz_set_pid(volatile usb_dwc_host_chan_regs_t *chan, uint32_t data_pid)
-{
-    if (data_pid == 0) {
-        chan->hctsiz_reg.pid = 0;
-    } else {
-        chan->hctsiz_reg.pid = 2;
-    }
-}
-
-static inline uint32_t usb_dwc_ll_hctsiz_get_pid(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    if (chan->hctsiz_reg.pid == 0) {
-        return 0;   //DATA0
-    } else {
-        return 1;   //DATA1
-    }
-}
-
-static inline void usb_dwc_ll_hctsiz_set_qtd_list_len(volatile usb_dwc_host_chan_regs_t *chan, int qtd_list_len)
-{
-    usb_dwc_hctsiz_reg_t hctsiz;
-    hctsiz.val = chan->hctsiz_reg.val;
-    //Set the length of the descriptor list. NTD occupies xfersize[15:8]
-    hctsiz.xfersize &= ~(0xFF << 8);
-    hctsiz.xfersize |= ((qtd_list_len - 1) & 0xFF) << 8;
-    chan->hctsiz_reg.val = hctsiz.val;
-}
-
-static inline void usb_dwc_ll_hctsiz_init(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    usb_dwc_hctsiz_reg_t hctsiz;
-    hctsiz.val = chan->hctsiz_reg.val;
-    hctsiz.dopng = 0;         //Don't do ping
-    /*
-    Set SCHED_INFO which occupies xfersize[7:0]
-    It is always set to 0xFF for full speed and not used in Bulk/Ctrl channels
-    */
-    hctsiz.xfersize |= 0xFF;
-    chan->hctsiz_reg.val = hctsiz.val;
-}
-
-static inline void usb_dwc_ll_hctsiz_set_sched_info(volatile usb_dwc_host_chan_regs_t *chan, int tokens_per_frame, int offset)
-{
-    // @see USB-OTG databook: Table 5-47
-    // This function is relevant only for HS
-    usb_dwc_hctsiz_reg_t hctsiz;
-    hctsiz.val = chan->hctsiz_reg.val;
-    uint8_t sched_info_val;
-    switch (tokens_per_frame) {
-        case 1:
-            offset %= 8; // If the required offset > 8, we must wrap around to SCHED_INFO size = 8
-            sched_info_val = 0b00000001;
-            break;
-        case 2:
-            offset %= 4;
-            sched_info_val = 0b00010001;
-            break;
-        case 4:
-            offset %= 2;
-            sched_info_val = 0b01010101;
-            break;
-        case 8:
-            offset = 0;
-            sched_info_val = 0b11111111;
-            break;
-        default:
-            abort();
-            break;
-    }
-    sched_info_val <<= offset;
-    hctsiz.xfersize &= ~(0xFF);
-    hctsiz.xfersize |= sched_info_val;
-    chan->hctsiz_reg.val = hctsiz.val;
-}
-
-// ---------------------------- HCDMAi Register --------------------------------
-
-static inline void usb_dwc_ll_hcdma_set_qtd_list_addr(volatile usb_dwc_host_chan_regs_t *chan, void *dmaaddr, uint32_t qtd_idx)
-{
-    usb_dwc_hcdma_reg_t hcdma;
-    /*
-    Set the base address portion of the field which is dmaaddr[31:9]. This is
-    the based address of the QTD list and must be 512 bytes aligned
-    */
-    hcdma.dmaaddr = ((uint32_t)dmaaddr) & 0xFFFFFE00;
-    //Set the current QTD index in the QTD list which is dmaaddr[8:3]
-    hcdma.dmaaddr |= (qtd_idx & 0x3F) << 3;
-    //dmaaddr[2:0] is reserved thus doesn't not need to be set
-
-    chan->hcdma_reg.val = hcdma.val;
-}
-
-static inline int usb_dwc_ll_hcdam_get_cur_qtd_idx(usb_dwc_host_chan_regs_t *chan)
-{
-    //The current QTD index is dmaaddr[8:3]
-    return (chan->hcdma_reg.dmaaddr >> 3) & 0x3F;
-}
-
-// ---------------------------- HCDMABi Register -------------------------------
-
-static inline void *usb_dwc_ll_hcdmab_get_buff_addr(volatile usb_dwc_host_chan_regs_t *chan)
-{
-    return (void *)chan->hcdmab_reg.hcdmab;
-}
-
-/* -----------------------------------------------------------------------------
----------------------------- Scatter/Gather DMA QTDs ---------------------------
------------------------------------------------------------------------------ */
-
-// ---------------------------- Helper Functions -------------------------------
-
-/**
- * @brief Get the base address of a channel's register based on the channel's index
- *
- * @param dev Start address of the DWC_OTG registers
- * @param chan_idx The channel's index
- * @return usb_dwc_host_chan_regs_t* Pointer to channel's registers
- */
-static inline usb_dwc_host_chan_regs_t *usb_dwc_ll_chan_get_regs(usb_dwc_dev_t *dev, int chan_idx)
-{
-    return &dev->host_chans[chan_idx];
-}
-
-// ------------------------------ QTD related ----------------------------------
-
-#define USB_DWC_LL_QTD_STATUS_SUCCESS      0x0     //If QTD was processed, it indicates the data was transmitted/received successfully
-#define USB_DWC_LL_QTD_STATUS_PKTERR       0x1     //Data trasnmitted/received with errors (CRC/Timeout/Stuff/False EOP/Excessive NAK).
-//Note: 0x2 is reserved
-#define USB_DWC_LL_QTD_STATUS_BUFFER       0x3     //AHB error occurred.
-#define USB_DWC_LL_QTD_STATUS_NOT_EXECUTED 0x4     //QTD as never processed
-
-/**
- * @brief Set a QTD for a non isochronous IN transfer
- *
- * @param qtd Pointer to the QTD
- * @param data_buff Pointer to buffer containing the data to transfer
- * @param xfer_len Number of bytes in transfer. Setting 0 will do a zero length IN transfer.
- *                 Non zero length must be mulitple of the endpoint's MPS.
- * @param hoc Halt on complete (will generate an interrupt and halt the channel)
- */
-static inline void usb_dwc_ll_qtd_set_in(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc)
-{
-    qtd->buffer = data_buff;        //Set pointer to data buffer
-    qtd->buffer_status_val = 0;     //Reset all flags to zero
-    qtd->in_non_iso.xfer_size = xfer_len;
-    if (hoc) {
-        qtd->in_non_iso.intr_cplt = 1;  //We need to set this to distinguish between a halt due to a QTD
-        qtd->in_non_iso.eol = 1;        //Used to halt the channel at this qtd
-    }
-    qtd->in_non_iso.active = 1;
-}
-
-/**
- * @brief Set a QTD for a non isochronous OUT transfer
- *
- * @param qtd Poitner to the QTD
- * @param data_buff Pointer to buffer containing the data to transfer
- * @param xfer_len Number of bytes to transfer. Setting 0 will do a zero length transfer.
- *                 For ctrl setup packets, this should be set to 8.
- * @param hoc Halt on complete (will generate an interrupt)
- * @param is_setup Indicates whether this is a control transfer setup packet or a normal OUT Data transfer.
- *                 (As per the USB protocol, setup packets cannot be STALLd or NAKd by the device)
- */
-static inline void usb_dwc_ll_qtd_set_out(usb_dwc_ll_dma_qtd_t *qtd, uint8_t *data_buff, int xfer_len, bool hoc, bool is_setup)
-{
-    qtd->buffer = data_buff;        //Set pointer to data buffer
-    qtd->buffer_status_val = 0;     //Reset all flags to zero
-    qtd->out_non_iso.xfer_size = xfer_len;
-    if (is_setup) {
-        qtd->out_non_iso.is_setup = 1;
-    }
-    if (hoc) {
-        qtd->in_non_iso.intr_cplt = 1;  //We need to set this to distinguish between a halt due to a QTD
-        qtd->in_non_iso.eol = 1;        //Used to halt the channel at this qtd
-    }
-    qtd->out_non_iso.active = 1;
-}
-
-/**
- * @brief Set a QTD as NULL
- *
- * This sets the QTD to a value of 0. This is only useful when you need to insert
- * blank QTDs into a list of QTDs
- *
- * @param qtd Pointer to the QTD
- */
-static inline void usb_dwc_ll_qtd_set_null(usb_dwc_ll_dma_qtd_t *qtd)
-{
-    qtd->buffer = NULL;
-    qtd->buffer_status_val = 0;     //Disable qtd by clearing it to zero. Used by interrupt/isoc as an unscheudled frame
-}
-
-/**
- * @brief Get the status of a QTD
- *
- * When a channel get's halted, call this to check whether each QTD was executed successfully
- *
- * @param qtd Poitner to the QTD
- * @param[out] rem_len Number of bytes ramining in the QTD
- * @param[out] status Status of the QTD
- */
-static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem_len, int *status)
-{
-    //Status is the same regardless of IN or OUT
-    if (qtd->in_non_iso.active) {
-        //QTD was never processed
-        *status = USB_DWC_LL_QTD_STATUS_NOT_EXECUTED;
-    } else {
-        *status = qtd->in_non_iso.rx_status;
-    }
-    *rem_len = qtd->in_non_iso.xfer_size;
-    //Clear the QTD just for safety
-    qtd->buffer_status_val = 0;
-}
-
-#endif // SOC_USB_OTG_SUPPORTED
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/hal/include/hal/usb_utmi_hal.h b/components/hal/include/hal/usb_utmi_hal.h
new file mode 100644
index 00000000000..dcb859a21c3
--- /dev/null
+++ b/components/hal/include/hal/usb_utmi_hal.h
@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#if (SOC_USB_UTMI_PHY_NUM > 0)
+#include "soc/usb_utmi_struct.h"
+#include "hal/usb_utmi_ll.h"
+#endif // (SOC_USB_UTMI_PHY_NUM > 0)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (SOC_USB_UTMI_PHY_NUM > 0)
+
+/**
+ * @brief HAL context type of USB UTMI driver
+ */
+typedef struct {
+    usb_utmi_dev_t *dev;
+} usb_utmi_hal_context_t;
+
+/**
+ * @brief Sets UTMI defaults
+ *
+ * Enable clock, reset the peripheral, sets default options (LS support, disconnection detection)
+ *
+ * @param[in] hal USB UTMI HAL context
+ */
+void _usb_utmi_hal_init(usb_utmi_hal_context_t *hal);
+
+#if SOC_RCC_IS_INDEPENDENT
+#define usb_utmi_hal_init(...)   _usb_utmi_hal_init(__VA_ARGS__)
+#else
+// Use a macro to wrap the function, force the caller to use it in a critical section
+// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define usb_utmi_hal_init(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; _usb_utmi_hal_init(__VA_ARGS__);} while(0)
+#endif
+
+/**
+ * @brief Disable UTMI
+ *
+ * Disable clock to the peripheral
+ */
+void _usb_utmi_hal_disable(void);
+
+#if SOC_RCC_IS_INDEPENDENT
+#define usb_utmi_hal_disable(...)   _usb_utmi_hal_disable(__VA_ARGS__)
+#else
+// Use a macro to wrap the function, force the caller to use it in a critical section
+// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define usb_utmi_hal_disable(...) do {(void)__DECLARE_RCC_ATOMIC_ENV; _usb_utmi_hal_disable(__VA_ARGS__);} while(0)
+#endif
+
+#endif // (SOC_USB_UTMI_PHY_NUM > 0)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/hal/include/hal/usb_wrap_hal.h b/components/hal/include/hal/usb_wrap_hal.h
index ceb69f36527..8477b6927d0 100644
--- a/components/hal/include/hal/usb_wrap_hal.h
+++ b/components/hal/include/hal/usb_wrap_hal.h
@@ -8,17 +8,17 @@
 
 #include <stdbool.h>
 #include "soc/soc_caps.h"
-#if SOC_USB_OTG_SUPPORTED
+#if (SOC_USB_OTG_PERIPH_NUM > 0)
 #include "soc/usb_wrap_struct.h"
 #include "hal/usb_wrap_ll.h"
-#endif
+#endif // (SOC_USB_OTG_PERIPH_NUM > 0)
 #include "hal/usb_wrap_types.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#if SOC_USB_OTG_SUPPORTED
+#if (SOC_USB_OTG_PERIPH_NUM > 0)
 
 /**
  * @brief HAL context type of USB WRAP driver
@@ -89,7 +89,7 @@ static inline void usb_wrap_hal_phy_test_mode_set_signals(usb_wrap_hal_context_t
     usb_wrap_ll_phy_test_mode_set_signals(hal->dev, vals);
 }
 
-#endif // SOC_USB_OTG_SUPPORTED
+#endif // (SOC_USB_OTG_PERIPH_NUM > 0)
 
 #ifdef __cplusplus
 }
diff --git a/components/hal/include/hal/usb_wrap_types.h b/components/hal/include/hal/usb_wrap_types.h
index 9d3310fb065..a8727f0ef8a 100644
--- a/components/hal/include/hal/usb_wrap_types.h
+++ b/components/hal/include/hal/usb_wrap_types.h
@@ -13,7 +13,7 @@
 extern "C" {
 #endif
 
-#if SOC_USB_OTG_SUPPORTED
+#if (SOC_USB_OTG_PERIPH_NUM > 0)
 
 /**
  * @brief USB WRAP pull up/down resistor override values
@@ -46,7 +46,7 @@ typedef struct {
     bool rx_rcv;        /**< Differential receive data from D+ and D- lines */
 } usb_wrap_test_mode_vals_t;
 
-#endif // SOC_USB_OTG_SUPPORTED
+#endif // (SOC_USB_OTG_PERIPH_NUM > 0)
 
 #ifdef __cplusplus
 }
diff --git a/components/hal/mipi_dsi_hal.c b/components/hal/mipi_dsi_hal.c
index 06565f7c372..0a7f4c3c58b 100644
--- a/components/hal/mipi_dsi_hal.c
+++ b/components/hal/mipi_dsi_hal.c
@@ -206,10 +206,10 @@ void mipi_dsi_hal_host_gen_read_short_packet(mipi_dsi_hal_context_t *hal, uint8_
     while (!mipi_dsi_host_ll_gen_is_read_fifo_empty(hal->host)) {
         temp = mipi_dsi_host_ll_gen_read_payload_fifo(hal->host);
         for (int i = 0; i < 4; i++) {
-            if ((counter + i) < buffer_size) {
-                receive_buffer[counter + i] = (temp >> (8 * i)) & 0xFF;
+            if (counter < buffer_size) {
+                receive_buffer[counter] = (temp >> (8 * i)) & 0xFF;
+                counter++;
             }
-            counter++;
         }
     }
 }
@@ -220,7 +220,7 @@ void mipi_dsi_hal_host_gen_read_dcs_command(mipi_dsi_hal_context_t *hal, uint8_t
     mipi_dsi_hal_host_gen_read_short_packet(hal, vc, MIPI_DSI_DT_DCS_READ_0, header_data, ret_param, param_buf_size);
 }
 
-void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_rgb_pixel_format_t color_coding, uint32_t sub_config)
+void mipi_dsi_hal_host_dpi_set_color_coding(mipi_dsi_hal_context_t *hal, lcd_color_format_t color_coding, uint32_t sub_config)
 {
     mipi_dsi_host_ll_dpi_set_color_coding(hal->host, color_coding, sub_config);
     mipi_dsi_brg_ll_set_pixel_format(hal->bridge, color_coding, sub_config);
diff --git a/components/hal/test_apps/crypto/README.md b/components/hal/test_apps/crypto/README.md
index 4e2c6f4f57a..3b25adda8ab 100644
--- a/components/hal/test_apps/crypto/README.md
+++ b/components/hal/test_apps/crypto/README.md
@@ -67,7 +67,8 @@ This contains tests for the following features of the crypto peripherals:
         - SHA-512/256
         - SHA-512/t
 
-> **_NOTE:_** The verification tests for the HMAC and Digital Signature peripherals would get exercised in only in an FPGA environment.
+> **_NOTE:_** The verification tests for the HMAC and Digital Signature peripherals would get exercised only by enabling the example config in an FPGA environment.
+
 # Burning the HMAC key
 
 The HMAC tests need an HMAC key to be burned in the `BLOCK_KEY3` and `BLOCK_KEY4` of the efuses. As this verification application is independent of the efuse component, the user needs to manually burn the keys and their key purposes using `espefuse.py`.
diff --git a/components/hal/test_apps/crypto/main/Kconfig.projbuild b/components/hal/test_apps/crypto/main/Kconfig.projbuild
index 051c5bae14b..ee68e84f19b 100644
--- a/components/hal/test_apps/crypto/main/Kconfig.projbuild
+++ b/components/hal/test_apps/crypto/main/Kconfig.projbuild
@@ -1,6 +1,14 @@
 
 menu "Test App Configuration"
 
+    config CRYPTO_TEST_APP_ENABLE_FPGA_TESTS
+        bool "Allow enabling the crypto tests that require burning efuses"
+        default y if IDF_ENV_FPGA
+        default n
+        help
+            This includes the crypto tests that actually require burning some efuses.
+            It is better to run these tests on an FPGA to avoid mistakenly burning eFuses.
+
     config CRYPTO_TEST_APP_ENABLE_DS_TESTS
         bool "Enable DS Peripheral test cases"
         default y
diff --git a/components/hal/test_apps/crypto/main/app_main.c b/components/hal/test_apps/crypto/main/app_main.c
index 460445a343a..87dcee3d8ef 100644
--- a/components/hal/test_apps/crypto/main/app_main.c
+++ b/components/hal/test_apps/crypto/main/app_main.c
@@ -34,7 +34,7 @@ static void run_all_tests(void)
     RUN_TEST_GROUP(key_manager);
 #endif
 
-#if CONFIG_IDF_ENV_FPGA
+#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS
 
 #if CONFIG_SOC_HMAC_SUPPORTED && CONFIG_CRYPTO_TEST_APP_ENABLE_HMAC_TESTS
     RUN_TEST_GROUP(hmac);
@@ -48,7 +48,7 @@ static void run_all_tests(void)
     RUN_TEST_GROUP(ecdsa)
 #endif
 
-#endif /* CONFIG_IDF_ENV_FPGA */
+#endif /* CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS */
 }
 
 static void test_task(void *pvParameters)
diff --git a/components/hal/test_apps/crypto/main/key_manager/test_key_manager.c b/components/hal/test_apps/crypto/main/key_manager/test_key_manager.c
index ca424eb1321..2def4096e8f 100644
--- a/components/hal/test_apps/crypto/main/key_manager/test_key_manager.c
+++ b/components/hal/test_apps/crypto/main/key_manager/test_key_manager.c
@@ -263,7 +263,7 @@ static void key_mgr_test_ecdsa_random_mode(void)
     TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
 }
 
-#if CONFIG_IDF_ENV_FPGA
+#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS
 
 static void test_xts_aes_key_random_mode(void)
 {
@@ -351,7 +351,7 @@ TEST(key_manager, ecdsa_key_random_deployment)
     key_mgr_test_ecdsa_random_mode();
 }
 
-#if CONFIG_IDF_ENV_FPGA
+#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS
 TEST(key_manager, xts_key_random_deployment)
 {
     key_mgr_test_xts_aes_128_random_mode();
@@ -367,7 +367,7 @@ TEST_GROUP_RUNNER(key_manager)
     RUN_TEST_CASE(key_manager, xts_key_ecdh0_deployment);
     RUN_TEST_CASE(key_manager, ecdsa_key_ecdh0_deployment);
     RUN_TEST_CASE(key_manager, ecdsa_key_random_deployment);
-#if CONFIG_IDF_ENV_FPGA
+#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS
     RUN_TEST_CASE(key_manager, xts_key_random_deployment);
 #endif
 
diff --git a/components/hal/touch_sens_hal.c b/components/hal/touch_sens_hal.c
new file mode 100644
index 00000000000..35262325c24
--- /dev/null
+++ b/components/hal/touch_sens_hal.c
@@ -0,0 +1,88 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include "soc/soc_caps.h"
+#include "hal/touch_sensor_ll.h"
+#include "hal/touch_sens_hal.h"
+#include "hal/touch_sens_types.h"
+
+
+typedef struct {
+    int deep_slp_chan;
+    touch_hal_config_t slp_cfg;
+    bool apply_slp_cfg;
+} touch_hal_deep_sleep_obj_t;
+
+static touch_hal_deep_sleep_obj_t s_touch_slp_obj = {
+    .deep_slp_chan = -1,
+    .apply_slp_cfg = false,
+};
+
+void touch_hal_config_controller(const touch_hal_config_t *cfg)
+{
+    HAL_ASSERT(cfg);
+    touch_ll_sleep_set_channel_num(TOUCH_LL_NULL_CHANNEL);
+    touch_ll_set_power_on_wait_cycle(cfg->power_on_wait_ticks);
+    touch_ll_set_measure_interval_ticks(cfg->meas_interval_ticks);
+    touch_ll_set_timeout(cfg->timeout_ticks);
+
+#if SOC_TOUCH_SENSOR_VERSION == 2
+    touch_ll_set_charge_times(cfg->sample_cfg->charge_times);
+    touch_ll_set_charge_voltage_high_limit(cfg->sample_cfg->charge_volt_lim_h);
+    touch_ll_set_charge_voltage_low_limit(cfg->sample_cfg->charge_volt_lim_l);
+    touch_ll_set_idle_channel_connection(cfg->sample_cfg->idle_conn);
+    touch_ll_set_bias_type(cfg->sample_cfg->bias_type);
+#elif SOC_TOUCH_SENSOR_VERSION == 3
+    touch_ll_sample_cfg_set_engaged_num(cfg->sample_cfg_num);
+    touch_ll_set_out_mode(cfg->output_mode);
+    for (int i = 0; i < cfg->sample_cfg_num; i++) {
+        touch_ll_set_clock_div(i, cfg->sample_cfg[i].div_num);
+        touch_ll_set_charge_times(i, cfg->sample_cfg[i].charge_times);
+        touch_ll_sample_cfg_set_rc_filter(i, cfg->sample_cfg[i].rc_filter_cap, cfg->sample_cfg[i].rc_filter_res);
+        touch_ll_sample_cfg_set_driver(i, cfg->sample_cfg[i].low_drv, cfg->sample_cfg[i].high_drv);
+        touch_ll_sample_cfg_bypass_shield_output(i, cfg->sample_cfg[i].bypass_shield_output);
+        touch_ll_sample_cfg_set_bias_voltage(i, cfg->sample_cfg[i].bias_volt);
+    }
+#else
+    HAL_ASSERT(0);  // Unsupported touch sensor version
+#endif
+}
+
+void touch_hal_save_sleep_config(int deep_slp_chan, const touch_hal_config_t *deep_slp_cfg)
+{
+    s_touch_slp_obj.deep_slp_chan = deep_slp_chan;
+    /* If particular deep sleep configuration is given, save it and apply it before entering the deep sleep */
+    if (deep_slp_chan >= 0 && deep_slp_cfg) {
+        s_touch_slp_obj.apply_slp_cfg = true;
+        memcpy(&s_touch_slp_obj.slp_cfg, deep_slp_cfg, sizeof(touch_hal_config_t));
+    } else {
+        s_touch_slp_obj.apply_slp_cfg = false;
+    }
+}
+
+//This function will only be called when the chip is going to deep sleep.
+static void s_touch_hal_apply_sleep_config(void)
+{
+    /* Apply the particular configuration for deep sleep */
+    if (s_touch_slp_obj.apply_slp_cfg) {
+        touch_hal_config_controller(&s_touch_slp_obj.slp_cfg);
+    }
+    /* Whether to enable touch sensor wake-up the chip from deep sleep */
+    if (s_touch_slp_obj.deep_slp_chan >= 0) {
+        touch_ll_sleep_set_channel_num(s_touch_slp_obj.deep_slp_chan);
+        touch_ll_enable_channel_mask(BIT(s_touch_slp_obj.deep_slp_chan));
+    } else {
+        touch_ll_sleep_set_channel_num(TOUCH_LL_NULL_CHANNEL);
+    }
+}
+
+void touch_hal_prepare_deep_sleep(void)
+{
+    s_touch_hal_apply_sleep_config();
+    touch_ll_sleep_reset_benchmark();
+    touch_ll_interrupt_clear(TOUCH_LL_INTR_MASK_ALL);
+}
diff --git a/components/hal/touch_sensor_hal.c b/components/hal/touch_sensor_hal.c
index f69f0163bcb..3121f03e2d5 100644
--- a/components/hal/touch_sensor_hal.c
+++ b/components/hal/touch_sensor_hal.c
@@ -7,7 +7,7 @@
 // The HAL layer for Touch Sensor (common part)
 
 #include "hal/touch_sensor_hal.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 #include "soc/soc_caps.h"
 
 void touch_hal_config(touch_pad_t touch_num)
diff --git a/components/hal/usb_dwc_hal.c b/components/hal/usb_dwc_hal.c
index bcc8870ed47..3f437626375 100644
--- a/components/hal/usb_dwc_hal.c
+++ b/components/hal/usb_dwc_hal.c
@@ -10,7 +10,7 @@
 #include <stdlib.h> // For abort()
 #include "sdkconfig.h"
 #include "soc/chip_revision.h"
-#include "soc/usb_dwc_cfg.h"
+#include "soc/usb_dwc_periph.h"
 #include "hal/usb_dwc_hal.h"
 #include "hal/usb_dwc_ll.h"
 #include "hal/efuse_hal.h"
@@ -18,14 +18,6 @@
 
 // ------------------------------------------------ Macros and Types ---------------------------------------------------
 
-// TODO: Remove target specific section after support for multiple USB peripherals is implemented
-#include "sdkconfig.h"
-#if (CONFIG_IDF_TARGET_ESP32P4)
-#define USB_BASE USB_DWC_HS
-#else
-#define USB_BASE USB_DWC
-#endif
-
 // ---------------------- Constants ------------------------
 
 #define BENDPOINTADDRESS_NUM_MSK     0x0F   //Endpoint number mask of the bEndpointAddress field of an endpoint descriptor
@@ -118,10 +110,12 @@ static void set_defaults(usb_dwc_hal_context_t *hal)
     //GUSBCFG register
     usb_dwc_ll_gusbcfg_dis_hnp_cap(hal->dev);       //Disable HNP
     usb_dwc_ll_gusbcfg_dis_srp_cap(hal->dev);       //Disable SRP
-#if (OTG_HSPHY_INTERFACE != 0)
-    usb_dwc_ll_gusbcfg_set_timeout_cal(hal->dev, 5); // 5 PHY clocks for our HS PHY
-    usb_dwc_ll_gusbcfg_set_utmi_phy(hal->dev);
-#endif // (OTG_HSPHY_INTERFACE != 0)
+
+    // If this USB-DWC supports HS PHY, use it
+    if (hal->constant_config.hsphy_type != 0) {
+        usb_dwc_ll_gusbcfg_set_timeout_cal(hal->dev, 5); // 5 PHY clocks for our HS PHY
+        usb_dwc_ll_gusbcfg_set_utmi_phy(hal->dev);
+    }
     //Enable interruts
     usb_dwc_ll_gintmsk_dis_intrs(hal->dev, 0xFFFFFFFF);     //Mask all interrupts first
     usb_dwc_ll_gintmsk_en_intrs(hal->dev, CORE_INTRS_EN_MSK);   //Unmask global interrupts
@@ -131,16 +125,29 @@ static void set_defaults(usb_dwc_hal_context_t *hal)
     usb_dwc_ll_gusbcfg_force_host_mode(hal->dev);
 }
 
-void usb_dwc_hal_init(usb_dwc_hal_context_t *hal)
+void usb_dwc_hal_init(usb_dwc_hal_context_t *hal, int port_id)
 {
-    //Check if a peripheral is alive by reading the core ID registers
-    usb_dwc_dev_t *dev = &USB_BASE;
+    // Check if a peripheral is alive by reading the core ID registers
+    HAL_ASSERT(port_id < SOC_USB_OTG_PERIPH_NUM);
+    usb_dwc_dev_t *dev = USB_DWC_LL_GET_HW(port_id);
     uint32_t core_id = usb_dwc_ll_gsnpsid_get_id(dev);
     HAL_ASSERT(core_id == CORE_REG_GSNPSID);
     (void) core_id;     //Suppress unused variable warning if asserts are disabled
-    //Initialize HAL context
+
+    // Initialize HAL context
     memset(hal, 0, sizeof(usb_dwc_hal_context_t));
     hal->dev = dev;
+
+    // Save constant configuration of this USB-DWC instance
+    /*
+    * EPINFO_CTL is located at the end of FIFO, its size is fixed in HW.
+    * The reserved size is always the worst-case, which is device mode that requires 4 locations per EP direction (including EP0).
+    * Here we just read the FIFO size from HW register, to avoid any ambivalence
+    */
+    hal->constant_config.fifo_size = usb_dwc_ll_ghwcfg_get_fifo_depth(dev);
+    hal->constant_config.hsphy_type = usb_dwc_ll_ghwcfg_get_hsphy_type(dev);
+    hal->constant_config.chan_num_total = usb_dwc_ll_ghwcfg_get_channel_num(dev);
+
     set_defaults(hal);
 }
 
@@ -157,32 +164,31 @@ void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal)
 {
     usb_dwc_ll_grstctl_core_soft_reset(hal->dev);
     while (usb_dwc_ll_grstctl_is_core_soft_reset_in_progress(hal->dev)) {
-        ;   //Wait until core reset is done
+        ;   // Wait until core reset is done
     }
     while (!usb_dwc_ll_grstctl_is_ahb_idle(hal->dev)) {
-        ;   //Wait until AHB Master bus is idle before doing any other operations
+        ;   // Wait until AHB Master bus is idle before doing any other operations
     }
-    //Set the default bits
+
+    // Set the default bits in USB-DWC registers
     set_defaults(hal);
-    //Clear all the flags and channels
+
+    // Clear all the flags and channels
     hal->periodic_frame_list = NULL;
     hal->flags.val = 0;
-    hal->channels.num_allocd = 0;
+    hal->channels.num_allocated = 0;
     hal->channels.chan_pend_intrs_msk = 0;
-    memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * OTG_NUM_HOST_CHAN);
+    if (hal->channels.hdls) {
+        for (int i = 0; i < hal->constant_config.chan_num_total; i++) {
+            hal->channels.hdls[i] = NULL;
+        }
+    }
 }
 
 void usb_dwc_hal_set_fifo_bias(usb_dwc_hal_context_t *hal, const usb_hal_fifo_bias_t fifo_bias)
 {
-    /*
-    * EPINFO_CTL is located at the end of FIFO, its size is fixed in HW.
-    * The reserved size is always the worst-case, which is device mode that requires 4 locations per EP direction (including EP0).
-    * Here we just read the FIFO size from HW register, to avoid any ambivalence
-    */
-    uint32_t ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4;
-    usb_dwc_ll_ghwcfg_get_hw_config(hal->dev, &ghwcfg1, &ghwcfg2, &ghwcfg3, &ghwcfg4);
-    const uint16_t fifo_size_lines = ((usb_dwc_ghwcfg3_reg_t)ghwcfg3).dfifodepth;
-
+    HAL_ASSERT(hal->channels.hdls);
+    const uint16_t fifo_size_lines = hal->constant_config.fifo_size;
     /*
     * Recommended FIFO sizes (see 2.1.2.4 for programming guide)
     *
@@ -193,23 +199,28 @@ void usb_dwc_hal_set_fifo_bias(usb_dwc_hal_context_t *hal, const usb_hal_fifo_bi
     * Recommended sizes fit 2 packets of each type. For S2 and S3 we can't fit even one MPS ISOC packet (1023 FS and 1024 HS).
     * So the calculations below are compromises between the available FIFO size and optimal performance.
     */
+
+    // Information for maintainers: this calculation is here for backward compatibility
+    // It should be removed when we allow HAL users to configure the FIFO sizes IDF-9042
+    const int otg_dfifo_depth = hal->constant_config.hsphy_type ? 1024 : 256;
+
     usb_dwc_hal_fifo_config_t fifo_config;
     switch (fifo_bias) {
         // Define minimum viable (fits at least 1 MPS) FIFO sizes for non-biased FIFO types
         // Allocate the remaining size to the biased FIFO type
         case USB_HAL_FIFO_BIAS_DEFAULT:
-            fifo_config.nptx_fifo_lines = OTG_DFIFO_DEPTH / 4;
-            fifo_config.ptx_fifo_lines  = OTG_DFIFO_DEPTH / 8;
+            fifo_config.nptx_fifo_lines = otg_dfifo_depth / 4;
+            fifo_config.ptx_fifo_lines  = otg_dfifo_depth / 8;
             fifo_config.rx_fifo_lines   = fifo_size_lines - fifo_config.ptx_fifo_lines - fifo_config.nptx_fifo_lines;
             break;
         case USB_HAL_FIFO_BIAS_RX:
-            fifo_config.nptx_fifo_lines = OTG_DFIFO_DEPTH / 16;
-            fifo_config.ptx_fifo_lines  = OTG_DFIFO_DEPTH / 8;
+            fifo_config.nptx_fifo_lines = otg_dfifo_depth / 16;
+            fifo_config.ptx_fifo_lines  = otg_dfifo_depth / 8;
             fifo_config.rx_fifo_lines   = fifo_size_lines - fifo_config.ptx_fifo_lines - fifo_config.nptx_fifo_lines;
             break;
         case USB_HAL_FIFO_BIAS_PTX:
-            fifo_config.rx_fifo_lines   = OTG_DFIFO_DEPTH / 8 + 2; // 2 extra lines are allocated for status information. See USB-OTG Programming Guide, chapter 2.1.2.1
-            fifo_config.nptx_fifo_lines = OTG_DFIFO_DEPTH / 16;
+            fifo_config.rx_fifo_lines   = otg_dfifo_depth / 8 + 2; // 2 extra lines are allocated for status information. See USB-OTG Programming Guide, chapter 2.1.2.1
+            fifo_config.nptx_fifo_lines = otg_dfifo_depth / 16;
             fifo_config.ptx_fifo_lines  = fifo_size_lines - fifo_config.nptx_fifo_lines - fifo_config.rx_fifo_lines;
             break;
         default:
@@ -218,7 +229,7 @@ void usb_dwc_hal_set_fifo_bias(usb_dwc_hal_context_t *hal, const usb_hal_fifo_bi
 
     HAL_ASSERT((fifo_config.rx_fifo_lines + fifo_config.nptx_fifo_lines + fifo_config.ptx_fifo_lines) <= fifo_size_lines);
     //Check that none of the channels are active
-    for (int i = 0; i < OTG_NUM_HOST_CHAN; i++) {
+    for (int i = 0; i < hal->constant_config.chan_num_total; i++) {
         if (hal->channels.hdls[i] != NULL) {
             HAL_ASSERT(!hal->channels.hdls[i]->flags.active);
         }
@@ -257,11 +268,15 @@ static inline void debounce_lock_enable(usb_dwc_hal_context_t *hal)
 
 void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal)
 {
-    usb_dwc_speed_t speed = usb_dwc_ll_hprt_get_speed(hal->dev);
-    //Host Configuration
-    usb_dwc_ll_hcfg_set_defaults(hal->dev, speed);
-    //Configure HFIR
-    usb_dwc_ll_hfir_set_defaults(hal->dev, speed);
+    // Host Configuration
+    usb_dwc_ll_hcfg_en_scatt_gatt_dma(hal->dev); // Enable Scatther-Gather DMA mode
+    usb_dwc_ll_hcfg_dis_perio_sched(hal->dev);   // Disable Periodic Scheduler (for now)
+
+    // Configure PHY clock: Only for USB-DWC with FSLS PHY
+    if (hal->constant_config.hsphy_type == 0) {
+        usb_dwc_ll_hcfg_set_fsls_phy_clock(hal->dev);
+        usb_dwc_ll_hfir_set_frame_interval(hal->dev);
+    }
 }
 
 // ----------------------------------------------------- Channel -------------------------------------------------------
@@ -270,17 +285,18 @@ void usb_dwc_hal_port_enable(usb_dwc_hal_context_t *hal)
 
 bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj, void *chan_ctx)
 {
-    HAL_ASSERT(hal->flags.fifo_sizes_set);  //FIFO sizes should be set befor attempting to allocate a channel
+    HAL_ASSERT(hal->channels.hdls);
+    HAL_ASSERT(hal->flags.fifo_sizes_set);  //FIFO sizes should be set before attempting to allocate a channel
     //Attempt to allocate channel
-    if (hal->channels.num_allocd == OTG_NUM_HOST_CHAN) {
+    if (hal->channels.num_allocated == hal->constant_config.chan_num_total) {
         return false;    //Out of free channels
     }
     int chan_idx = -1;
-    for (int i = 0; i < OTG_NUM_HOST_CHAN; i++) {
+    for (int i = 0; i < hal->constant_config.chan_num_total; i++) {
         if (hal->channels.hdls[i] == NULL) {
             hal->channels.hdls[i] = chan_obj;
             chan_idx = i;
-            hal->channels.num_allocd++;
+            hal->channels.num_allocated++;
             break;
         }
     }
@@ -302,6 +318,7 @@ bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan
 
 void usb_dwc_hal_chan_free(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_obj)
 {
+    HAL_ASSERT(hal->channels.hdls);
     if (chan_obj->type == USB_DWC_XFER_TYPE_INTR || chan_obj->type == USB_DWC_XFER_TYPE_ISOCHRONOUS) {
         //Unschedule this channel
         for (int i = 0; i < hal->frame_list_len; i++) {
@@ -314,8 +331,8 @@ void usb_dwc_hal_chan_free(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan_
     usb_dwc_ll_haintmsk_dis_chan_intr(hal->dev, 1 << chan_obj->flags.chan_idx);
     //Deallocate channel
     hal->channels.hdls[chan_obj->flags.chan_idx] = NULL;
-    hal->channels.num_allocd--;
-    HAL_ASSERT(hal->channels.num_allocd >= 0);
+    hal->channels.num_allocated--;
+    HAL_ASSERT(hal->channels.num_allocated >= 0);
 }
 
 // ---------------- Channel Configuration ------------------
@@ -467,6 +484,7 @@ usb_dwc_hal_port_event_t usb_dwc_hal_decode_intr(usb_dwc_hal_context_t *hal)
 
 usb_dwc_hal_chan_t *usb_dwc_hal_get_chan_pending_intr(usb_dwc_hal_context_t *hal)
 {
+    HAL_ASSERT(hal->channels.hdls);
     int chan_num = __builtin_ffs(hal->channels.chan_pend_intrs_msk);
     if (chan_num) {
         hal->channels.chan_pend_intrs_msk &= ~(1 << (chan_num - 1));      //Clear the pending bit for that channel
diff --git a/components/hal/usb_utmi_hal.c b/components/hal/usb_utmi_hal.c
new file mode 100644
index 00000000000..cb7ceb49ba2
--- /dev/null
+++ b/components/hal/usb_utmi_hal.c
@@ -0,0 +1,29 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "hal/usb_utmi_ll.h"
+#include "hal/usb_utmi_hal.h"
+
+void _usb_utmi_hal_init(usb_utmi_hal_context_t *hal)
+{
+    hal->dev = &USB_UTMI;
+    _usb_utmi_ll_enable_bus_clock(true);
+    _usb_utmi_ll_reset_register();
+
+    /*
+    Additional setting to solve missing DCONN event on ESP32P4 (IDF-9953).
+
+    Note: On ESP32P4, the HP_SYSTEM_OTG_SUSPENDM is not connected to 1 by hardware.
+    For correct detection of the device detaching, internal signal should be set to 1 by the software.
+    */
+    usb_utmi_ll_enable_precise_detection(true);
+    usb_utmi_ll_configure_ls(hal->dev, true);
+}
+
+void _usb_utmi_hal_disable(void)
+{
+    _usb_utmi_ll_enable_bus_clock(false);
+}
diff --git a/components/idf_test/include/esp32c61/idf_performance_target.h b/components/idf_test/include/esp32c61/idf_performance_target.h
index 1053cbef3dd..f6f61792655 100644
--- a/components/idf_test/include/esp32c61/idf_performance_target.h
+++ b/components/idf_test/include/esp32c61/idf_performance_target.h
@@ -7,3 +7,11 @@
 #pragma once
 
 #define IDF_PERFORMANCE_MAX_ESP_TIMER_GET_TIME_PER_CALL                         1300
+
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_NO_FILTER                 5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_2                  5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_4                  5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_8                  5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_16                 5
+#define IDF_PERFORMANCE_MAX_ADC_CONTINUOUS_STD_ATTEN3_FILTER_64                 5
+#define IDF_PERFORMANCE_MAX_ADC_ONESHOT_STD_ATTEN3                              5
diff --git a/components/ieee802154/driver/esp_ieee802154_dev.c b/components/ieee802154/driver/esp_ieee802154_dev.c
index 5376f192411..52dad817069 100644
--- a/components/ieee802154/driver/esp_ieee802154_dev.c
+++ b/components/ieee802154/driver/esp_ieee802154_dev.c
@@ -161,7 +161,7 @@ uint8_t ieee802154_get_recent_lqi(void)
     return s_rx_frame_info[s_recent_rx_frame_info_index].lqi;
 }
 
-IEEE802154_STATIC void set_next_rx_buffer(void)
+IEEE802154_STATIC IEEE802154_NOINLINE void set_next_rx_buffer(void)
 {
     uint8_t* next_rx_buffer = NULL;
     uint8_t index = 0;
@@ -194,7 +194,7 @@ IEEE802154_STATIC void set_next_rx_buffer(void)
     ieee802154_ll_set_rx_addr(next_rx_buffer);
 }
 
-static bool stop_rx(void)
+IEEE802154_NOINLINE static bool stop_rx(void)
 {
     ieee802154_ll_events events;
 
@@ -210,7 +210,7 @@ static bool stop_rx(void)
     return true;
 }
 
-static bool stop_tx_ack(void)
+IEEE802154_NOINLINE static bool stop_tx_ack(void)
 {
     ieee802154_set_cmd(IEEE802154_CMD_STOP);
 
@@ -221,7 +221,7 @@ static bool stop_tx_ack(void)
     return true;
 }
 
-static bool stop_tx(void)
+IEEE802154_NOINLINE static bool stop_tx(void)
 {
     ieee802154_ll_events events;
 
@@ -245,21 +245,21 @@ static bool stop_tx(void)
     return true;
 }
 
-static bool stop_cca(void)
+IEEE802154_NOINLINE static bool stop_cca(void)
 {
     ieee802154_set_cmd(IEEE802154_CMD_STOP);
     ieee802154_ll_clear_events(IEEE802154_EVENT_ED_DONE | IEEE802154_EVENT_RX_ABORT);
     return true;
 }
 
-static bool stop_tx_cca(void)
+IEEE802154_NOINLINE static bool stop_tx_cca(void)
 {
     stop_tx(); // in case the transmission already started
     ieee802154_ll_clear_events(IEEE802154_EVENT_TX_ABORT);
     return true;
 }
 
-static bool stop_rx_ack(void)
+IEEE802154_NOINLINE static bool stop_rx_ack(void)
 {
     ieee802154_ll_events events;
 
@@ -281,7 +281,7 @@ static bool stop_rx_ack(void)
     return true;
 }
 
-static bool stop_ed(void)
+IEEE802154_NOINLINE static bool stop_ed(void)
 {
     ieee802154_set_cmd(IEEE802154_CMD_STOP);
 
@@ -290,7 +290,7 @@ static bool stop_ed(void)
     return true;
 }
 
-IEEE802154_STATIC bool stop_current_operation(void)
+IEEE802154_NOINLINE IEEE802154_STATIC bool stop_current_operation(void)
 {
     event_end_process();
     switch (s_ieee802154_state) {
@@ -341,8 +341,23 @@ IEEE802154_STATIC bool stop_current_operation(void)
     return true;
 }
 
+FORCE_INLINE_ATTR void extcoex_tx_stage_start(void)
+{
+#if CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE
+    esp_coex_ieee802154_extcoex_tx_stage();
+#endif
+}
+
+FORCE_INLINE_ATTR void extcoex_rx_stage_start(void)
+{
+#if CONFIG_ESP_COEX_EXTERNAL_COEXIST_ENABLE
+    esp_coex_ieee802154_extcoex_rx_stage();
+#endif
+}
+
 static void enable_rx(void)
 {
+    extcoex_rx_stage_start();
     set_next_rx_buffer();
     IEEE802154_SET_TXRX_PTI(IEEE802154_SCENE_RX);
 
@@ -403,6 +418,7 @@ static IRAM_ATTR void isr_handle_tx_done(void)
         NEEDS_NEXT_OPT(true);
     } else if (s_ieee802154_state == IEEE802154_STATE_TX || s_ieee802154_state == IEEE802154_STATE_TX_CCA) {
         if (ieee802154_frame_is_ack_required(s_tx_frame) && ieee802154_ll_get_rx_auto_ack()) {
+            extcoex_rx_stage_start();
             ieee802154_set_state(IEEE802154_STATE_RX_ACK);
 #if !CONFIG_IEEE802154_TEST
             receive_ack_timeout_timer_start(200000); // 200ms for receive ack timeout
@@ -423,6 +439,7 @@ static IRAM_ATTR void isr_handle_rx_done(void)
     if (s_ieee802154_state == IEEE802154_STATE_RX) {
         if (ieee802154_frame_is_ack_required(s_rx_frame[s_rx_index]) && ieee802154_frame_get_version(s_rx_frame[s_rx_index]) <= IEEE802154_FRAME_VERSION_1
                 && ieee802154_ll_get_tx_auto_ack()) {
+            extcoex_tx_stage_start();
             // auto tx ack only works for the frame with version 0b00 and 0b01
             s_rx_frame_info[s_rx_index].pending = ieee802154_ack_config_pending_bit(s_rx_frame[s_rx_index]);
             ieee802154_set_state(IEEE802154_STATE_TX_ACK);
@@ -432,6 +449,7 @@ static IRAM_ATTR void isr_handle_rx_done(void)
             s_rx_frame_info[s_rx_index].pending = ieee802154_ack_config_pending_bit(s_rx_frame[s_rx_index]);
             // For 2015 enh-ack, SW should generate an enh-ack then send it manually
             if (esp_ieee802154_enh_ack_generator(s_rx_frame[s_rx_index], &s_rx_frame_info[s_rx_index], s_enh_ack_frame) == ESP_OK) {
+                extcoex_tx_stage_start();
 #if !CONFIG_IEEE802154_TEST
                 // Send the Enh-Ack frame if generator succeeds.
                 ieee802154_ll_set_tx_addr(s_enh_ack_frame);
@@ -456,6 +474,7 @@ static IRAM_ATTR void isr_handle_rx_done(void)
 
 static IRAM_ATTR void isr_handle_ack_tx_done(void)
 {
+    extcoex_rx_stage_start();
     ieee802154_receive_done((uint8_t *)s_rx_frame[s_rx_index], &s_rx_frame_info[s_rx_index]);
     NEEDS_NEXT_OPT(true);
 }
@@ -469,11 +488,10 @@ static IRAM_ATTR void isr_handle_ack_rx_done(void)
     NEEDS_NEXT_OPT(true);
 }
 
-static IRAM_ATTR void isr_handle_rx_phase_rx_abort(void)
+static IRAM_ATTR void isr_handle_rx_phase_rx_abort(ieee802154_ll_rx_abort_reason_t rx_abort_reason)
 {
     event_end_process();
     uint32_t rx_status = ieee802154_ll_get_rx_status();
-    ieee802154_ll_rx_abort_reason_t rx_abort_reason = ieee802154_ll_get_rx_abort_reason();
     switch (rx_abort_reason) {
     case IEEE802154_RX_ABORT_BY_RX_STOP:
     case IEEE802154_RX_ABORT_BY_TX_ACK_STOP:
@@ -508,13 +526,12 @@ static IRAM_ATTR void isr_handle_rx_phase_rx_abort(void)
     NEEDS_NEXT_OPT(true);
 }
 
-static IRAM_ATTR void isr_handle_tx_ack_phase_rx_abort(void)
+static IRAM_ATTR void isr_handle_tx_ack_phase_rx_abort(ieee802154_ll_rx_abort_reason_t rx_abort_reason)
 {
     event_end_process();
 #if CONFIG_IEEE802154_TEST
     uint32_t rx_status = ieee802154_ll_get_rx_status();
 #endif
-    ieee802154_ll_rx_abort_reason_t rx_abort_reason = ieee802154_ll_get_rx_abort_reason();
     switch (rx_abort_reason) {
     case IEEE802154_RX_ABORT_BY_RX_STOP:
     case IEEE802154_RX_ABORT_BY_TX_ACK_STOP:
@@ -553,10 +570,9 @@ static IRAM_ATTR void isr_handle_tx_ack_phase_rx_abort(void)
     NEEDS_NEXT_OPT(true);
 }
 
-static IRAM_ATTR void isr_handle_tx_abort(void)
+static IRAM_ATTR void isr_handle_tx_abort(ieee802154_ll_tx_abort_reason_t tx_abort_reason)
 {
     event_end_process();
-    ieee802154_ll_tx_abort_reason_t tx_abort_reason = ieee802154_ll_get_tx_abort_reason();
     switch (tx_abort_reason) {
     case IEEE802154_TX_ABORT_BY_RX_ACK_STOP:
     case IEEE802154_TX_ABORT_BY_TX_STOP:
@@ -632,10 +648,12 @@ IEEE802154_STATIC IRAM_ATTR void ieee802154_exit_critical(void)
     portEXIT_CRITICAL(&s_ieee802154_spinlock);
 }
 
-static void ieee802154_isr(void *arg)
+IEEE802154_NOINLINE static void ieee802154_isr(void *arg)
 {
     ieee802154_enter_critical();
     ieee802154_ll_events events = ieee802154_ll_get_events();
+    ieee802154_ll_rx_abort_reason_t rx_abort_reason = ieee802154_ll_get_rx_abort_reason();
+    ieee802154_ll_tx_abort_reason_t tx_abort_reason = ieee802154_ll_get_tx_abort_reason();
 
     IEEE802154_PROBE(events);
 
@@ -643,7 +661,7 @@ static void ieee802154_isr(void *arg)
 
     if (events & IEEE802154_EVENT_RX_ABORT) {
         // First phase rx abort process, will clear RX_ABORT event in second.
-        isr_handle_rx_phase_rx_abort();
+        isr_handle_rx_phase_rx_abort(rx_abort_reason);
     }
 
     if (events & IEEE802154_EVENT_RX_SFD_DONE) {
@@ -701,12 +719,12 @@ static void ieee802154_isr(void *arg)
 
     if (events & IEEE802154_EVENT_RX_ABORT) {
         // Second phase rx abort process, clears RX_ABORT event.
-        isr_handle_tx_ack_phase_rx_abort();
+        isr_handle_tx_ack_phase_rx_abort(rx_abort_reason);
         events &= (uint16_t)(~IEEE802154_EVENT_RX_ABORT);
     }
 
     if (events & IEEE802154_EVENT_TX_ABORT) {
-        isr_handle_tx_abort();
+        isr_handle_tx_abort(tx_abort_reason);
 
         events &= (uint16_t)(~IEEE802154_EVENT_TX_ABORT);
     }
@@ -833,6 +851,7 @@ IEEE802154_STATIC void tx_init(const uint8_t *frame)
         // set rx pointer for ack frame
         set_next_rx_buffer();
     }
+    extcoex_tx_stage_start();
 }
 
 static inline esp_err_t ieee802154_transmit_internal(const uint8_t *frame, bool cca)
@@ -879,7 +898,7 @@ esp_err_t ieee802154_transmit(const uint8_t *frame, bool cca)
     return ieee802154_transmit_internal(frame, cca);
 }
 
-static inline bool is_target_time_expired(uint32_t target, uint32_t now)
+IEEE802154_NOINLINE static bool is_target_time_expired(uint32_t target, uint32_t now)
 {
     return (((now - target) & (1 << 31)) == 0);
 }
diff --git a/components/ieee802154/driver/esp_ieee802154_pib.c b/components/ieee802154/driver/esp_ieee802154_pib.c
index 2c52a6ca8bf..8654d5cef1e 100644
--- a/components/ieee802154/driver/esp_ieee802154_pib.c
+++ b/components/ieee802154/driver/esp_ieee802154_pib.c
@@ -45,7 +45,7 @@ void ieee802154_pib_init(void)
     set_pending();
 }
 
-static uint8_t ieee802154_txpower_convert(int8_t txpower)
+IEEE802154_NOINLINE static uint8_t ieee802154_txpower_convert(int8_t txpower)
 {
     uint8_t ieee820154_txpower_index = 0;
     if (txpower >= IEEE802154_TXPOWER_VALUE_MAX) {
diff --git a/components/ieee802154/include/esp_ieee802154_types.h b/components/ieee802154/include/esp_ieee802154_types.h
index 0b83cf2eed5..8c551f75526 100644
--- a/components/ieee802154/include/esp_ieee802154_types.h
+++ b/components/ieee802154/include/esp_ieee802154_types.h
@@ -9,6 +9,8 @@
 #include <stdint.h>
 #include <stdbool.h>
 
+#define US_PER_SYMBLE 16
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/ieee802154/linker.lf b/components/ieee802154/linker.lf
index e78d00a5dbc..8f57bdff951 100644
--- a/components/ieee802154/linker.lf
+++ b/components/ieee802154/linker.lf
@@ -44,7 +44,6 @@ entries:
             esp_ieee802154_dev: ieee802154_receive (noflash)
             esp_ieee802154_pib: ieee802154_pib_update (noflash)
             esp_ieee802154_pib: ieee802154_txpower_convert (noflash)
-            esp_ieee802154_pib: ieee802154_set_panid_addr (noflash)
             esp_ieee802154_util: ieee802154_channel_to_freq (noflash)
             esp_ieee802154: esp_ieee802154_transmit_at (noflash)
             esp_ieee802154: esp_ieee802154_receive_at (noflash)
@@ -55,7 +54,6 @@ entries:
             esp_ieee802154: esp_ieee802154_enh_ack_generator (noflash)
             esp_ieee802154: esp_ieee802154_get_extended_address (noflash)
             esp_ieee802154: esp_ieee802154_set_transmit_security  (noflash)
-            esp_ieee802154_pib: ieee802154_pib_get_extended_address (noflash)
 
         if OPENTHREAD_LINK_METRICS = y:
             esp_ieee802154: esp_ieee802154_get_recent_lqi (noflash)
diff --git a/components/log/CMakeLists.txt b/components/log/CMakeLists.txt
index e162bfb8537..0743b16e724 100644
--- a/components/log/CMakeLists.txt
+++ b/components/log/CMakeLists.txt
@@ -1,6 +1,7 @@
 idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(non_os_build NON_OS_BUILD)
 
-if(BOOTLOADER_BUILD)
+if(non_os_build)
     set(system_target "noos")
 else()
     if(${target} STREQUAL "linux")
@@ -15,7 +16,7 @@ set(srcs "src/${system_target}/log_timestamp.c"
          "src/${system_target}/log_lock.c")
 set(priv_requires "")
 
-if(NOT BOOTLOADER_BUILD)
+if(NOT non_os_build)
     list(APPEND priv_requires soc hal esp_hw_support)
 
     list(APPEND srcs "src/os/log_write.c")
diff --git a/components/log/Kconfig.format b/components/log/Kconfig.format
index ba0c6286ed8..e743dabff2e 100644
--- a/components/log/Kconfig.format
+++ b/components/log/Kconfig.format
@@ -2,7 +2,7 @@ menu "Format"
 
     config LOG_COLORS
         bool "Color"
-        default y
+        default n
         help
             Enable ANSI terminal color codes.
             In order to view these, your terminal program must support ANSI color codes.
diff --git a/components/log/include/esp_log.h b/components/log/include/esp_log.h
index 8d11d9ca94d..e2cb068f436 100644
--- a/components/log/include/esp_log.h
+++ b/components/log/include/esp_log.h
@@ -101,7 +101,7 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
             esp_rom_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \
         }} while(0)
 
-#ifndef BOOTLOADER_BUILD
+#ifndef NON_OS_BUILD
 #if defined(__cplusplus) && (__cplusplus >  201703L)
 #define ESP_LOGE( tag, format, ... ) ESP_LOG_LEVEL_LOCAL(ESP_LOG_ERROR,   tag, format __VA_OPT__(,) __VA_ARGS__)
 #define ESP_LOGW( tag, format, ... ) ESP_LOG_LEVEL_LOCAL(ESP_LOG_WARN,    tag, format __VA_OPT__(,) __VA_ARGS__)
@@ -147,7 +147,7 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
 /// macro to output logs at ``ESP_LOG_VERBOSE`` level.  @see ``ESP_LOGE``
 #define ESP_LOGV( tag, format, ... )  ESP_EARLY_LOGV(tag, format, ##__VA_ARGS__)
 #endif // !(defined(__cplusplus) && (__cplusplus >  201703L))
-#endif  // BOOTLOADER_BUILD
+#endif  // !NON_OS_BUILD
 
 /** runtime macro to output logs at a specified level.
  *
diff --git a/components/log/include/esp_log_buffer.h b/components/log/include/esp_log_buffer.h
index d5726f5e2bf..5453061403b 100644
--- a/components/log/include/esp_log_buffer.h
+++ b/components/log/include/esp_log_buffer.h
@@ -13,7 +13,7 @@
 extern "C" {
 #endif
 
-#if !BOOTLOADER_BUILD || __DOXYGEN__
+#if !NON_OS_BUILD || __DOXYGEN__
 
 /**
  * @brief Logs a buffer of hexadecimal bytes at the specified log level.
@@ -173,7 +173,7 @@ static inline void esp_log_buffer_char(const char *tag, const void *buffer, uint
 }
 /** @endcond */
 
-#endif // !BOOTLOADER_BUILD || __DOXYGEN__
+#endif // !NON_OS_BUILD || __DOXYGEN__
 
 #ifdef __cplusplus
 }
diff --git a/components/log/include/esp_log_level.h b/components/log/include/esp_log_level.h
index 80aeaa5ac1d..1f10660b992 100644
--- a/components/log/include/esp_log_level.h
+++ b/components/log/include/esp_log_level.h
@@ -37,12 +37,12 @@ typedef enum {
 #endif // !BOOTLOADER_BUILD
 #endif // LOG_LOCAL_LEVEL
 
-#if BOOTLOADER_BUILD
+#ifdef NON_OS_BUILD
 
 #define _ESP_LOG_ENABLED(log_level) (LOG_LOCAL_LEVEL >= (log_level))
 #define _ESP_LOG_EARLY_ENABLED(log_level) _ESP_LOG_ENABLED(log_level)
 
-#else // !BOOTLOADER_BUILD
+#else // !NON_OS_BUILD
 
 #if CONFIG_LOG_MASTER_LEVEL
 #define _ESP_LOG_ENABLED(log_level) (esp_log_get_level_master() >= (log_level) && LOG_LOCAL_LEVEL >= (log_level))
@@ -54,7 +54,7 @@ typedef enum {
 currently configured min log level are higher than the log level */
 #define _ESP_LOG_EARLY_ENABLED(log_level) (LOG_LOCAL_LEVEL >= (log_level) && esp_log_get_default_level() >= (log_level))
 
-#endif // !BOOTLOADER_BUILD
+#endif // !NON_OS_BUILD
 
 /** @endcond */
 
diff --git a/components/log/src/log_timestamp_common.c b/components/log/src/log_timestamp_common.c
index ba9521908f5..7905899da5b 100644
--- a/components/log/src/log_timestamp_common.c
+++ b/components/log/src/log_timestamp_common.c
@@ -12,7 +12,7 @@
 #include "esp_private/log_timestamp.h"
 #include "sdkconfig.h"
 
-#if !BOOTLOADER_BUILD
+#ifndef NON_OS_BUILD
 #include <sys/lock.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
@@ -60,7 +60,7 @@ char *esp_log_system_timestamp(void)
     }
     return buffer;
 }
-#endif // !BOOTLOADER_BUILD
+#endif // !NON_OS_BUILD
 
 uint64_t esp_log_timestamp64(bool critical)
 {
diff --git a/components/lwip/Kconfig b/components/lwip/Kconfig
index 231536c39d8..33f87955b22 100644
--- a/components/lwip/Kconfig
+++ b/components/lwip/Kconfig
@@ -433,6 +433,20 @@ menu "LWIP"
                 Enabling this option allows DHCP server to support temporary static ARP entries
                 for DHCP Client. This will help the DHCP server to send the DHCP OFFER and DHCP ACK using IP unicast.
 
+        config LWIP_DHCPS_ADD_DNS
+            bool "Always add DNS option in DHCP responses"
+            default y
+            depends on LWIP_DHCPS
+            help
+                This allows the DNS option to be optional in the DHCP offers,
+                depending on the server's runtime configuration.
+                When enabled, the DHCP server will always add the DNS option to DHCP responses.
+                If a DNS server is not explicitly configured, the server's IP address will be used
+                as the fallback for the DNS option.
+                When disabled, the DHCP server will only include the DNS option in responses
+                if a DNS server has been explicitly configured.
+                This option will be removed in IDF v6.x
+
     endmenu # DHCPS
 
     menuconfig LWIP_AUTOIP
@@ -730,8 +744,8 @@ menu "LWIP"
             int "The maximum number of pbufs queued on OOSEQ per pcb"
             depends on LWIP_TCP_QUEUE_OOSEQ
             range 0 12
-            default 4 if !SPIRAM_TRY_ALLOCATE_WIFI_LWIP
-            default 0 if SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+            default 4 if !(SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
+            default 0 if (SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
             help
                 If LWIP_TCP_OOSEQ_MAX_PBUFS = 0, TCP will not control the number of OOSEQ pbufs.
 
@@ -787,7 +801,7 @@ menu "LWIP"
 
         config LWIP_WND_SCALE
             bool "Support TCP window scale"
-            depends on SPIRAM_TRY_ALLOCATE_WIFI_LWIP
+            depends on (SPIRAM_TRY_ALLOCATE_WIFI_LWIP && !SPIRAM_IGNORE_NOTFOUND)
             default n
             help
                 Enable this feature to support TCP window scaling.
diff --git a/components/lwip/apps/dhcpserver/dhcpserver.c b/components/lwip/apps/dhcpserver/dhcpserver.c
index e6abfd743cf..8859e52c63b 100644
--- a/components/lwip/apps/dhcpserver/dhcpserver.c
+++ b/components/lwip/apps/dhcpserver/dhcpserver.c
@@ -454,18 +454,22 @@ static u8_t *add_offer_options(dhcps_t *dhcps, u8_t *optptr)
         }
     }
 
-    *optptr++ = DHCP_OPTION_DNS_SERVER;
-    *optptr++ = 4;
     if (dhcps_dns_enabled(dhcps->dhcps_dns)) {
+        *optptr++ = DHCP_OPTION_DNS_SERVER;
+        *optptr++ = 4;
         *optptr++ = ip4_addr1(&dhcps->dns_server);
         *optptr++ = ip4_addr2(&dhcps->dns_server);
         *optptr++ = ip4_addr3(&dhcps->dns_server);
         *optptr++ = ip4_addr4(&dhcps->dns_server);
+#ifdef CONFIG_LWIP_DHCPS_ADD_DNS
     }else {
+        *optptr++ = DHCP_OPTION_DNS_SERVER;
+        *optptr++ = 4;
         *optptr++ = ip4_addr1(&ipadd);
         *optptr++ = ip4_addr2(&ipadd);
         *optptr++ = ip4_addr3(&ipadd);
         *optptr++ = ip4_addr4(&ipadd);
+#endif /* CONFIG_LWIP_DHCPS_ADD_DNS */
     }
 
     ip4_addr_t broadcast_addr = { .addr = (ipadd.addr & dhcps->dhcps_mask.addr) | ~dhcps->dhcps_mask.addr };
diff --git a/components/lwip/apps/ping/ping_sock.c b/components/lwip/apps/ping/ping_sock.c
index 28cce40ff7d..fc302cfa733 100644
--- a/components/lwip/apps/ping/ping_sock.c
+++ b/components/lwip/apps/ping/ping_sock.c
@@ -133,7 +133,8 @@ static int esp_ping_receive(esp_ping_t *ep)
             if (IP_IS_V6_VAL(recv_addr)) {      // Currently we process IPv6
                 struct ip6_hdr *iphdr = (struct ip6_hdr *)buf;
                 struct icmp6_echo_hdr *iecho6 = (struct icmp6_echo_hdr *)(buf + sizeof(struct ip6_hdr)); // IPv6 head length is 40
-                if ((iecho6->id == ep->packet_hdr->id) && (iecho6->seqno == ep->packet_hdr->seqno)) {
+                if ((iecho6->type == ICMP6_TYPE_EREP) // only check the ICMPv6 echo reply types
+                    && (iecho6->id == ep->packet_hdr->id) && (iecho6->seqno == ep->packet_hdr->seqno)) {
                     ip_addr_copy(ep->recv_addr, recv_addr);
                     ep->received++;
                     ep->recv_len = IP6H_PLEN(iphdr) - sizeof(struct icmp6_echo_hdr); //The data portion of ICMPv6
diff --git a/components/lwip/lwip b/components/lwip/lwip
index f150e2321ac..c816f0ee5cd 160000
--- a/components/lwip/lwip
+++ b/components/lwip/lwip
@@ -1 +1 @@
-Subproject commit f150e2321ac09bb0fd35a7fcbc1b116fbf93434e
+Subproject commit c816f0ee5cd9dc15143767d0b33aafd39a1a9a3d
diff --git a/components/mbedtls/CMakeLists.txt b/components/mbedtls/CMakeLists.txt
index 93cb165b434..d3f4fe40a7d 100644
--- a/components/mbedtls/CMakeLists.txt
+++ b/components/mbedtls/CMakeLists.txt
@@ -61,7 +61,7 @@ if(CONFIG_MBEDTLS_CERTIFICATE_BUNDLE)
         list(APPEND crt_paths ${custom_bundle_path})
 
     endif()
-    list(APPEND args --input ${crt_paths} -q)
+    list(APPEND args --input ${crt_paths} -q --max-certs "${CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS}")
 
     get_filename_component(crt_bundle
         ${bundle_name}
@@ -96,7 +96,13 @@ idf_build_get_property(python PYTHON)
 set(Python3_EXECUTABLE ${python})
 
 # Needed to for include_next includes to work from within mbedtls
-include_directories("${COMPONENT_DIR}/port/include")
+set(include_dirs "${COMPONENT_DIR}/port/include")
+
+if(CONFIG_MBEDTLS_CERTIFICATE_BUNDLE)
+    list(APPEND include_dirs "${COMPONENT_DIR}/esp_crt_bundle/include")
+endif()
+
+include_directories(${include_dirs})
 
 # Needed to for mbedtls_rom includes to work from within mbedtls
 if(CONFIG_MBEDTLS_USE_CRYPTO_ROM_IMPL)
diff --git a/components/mbedtls/Kconfig b/components/mbedtls/Kconfig
index 367ba114eeb..1defa61db57 100644
--- a/components/mbedtls/Kconfig
+++ b/components/mbedtls/Kconfig
@@ -667,6 +667,14 @@ menu "mbedTLS"
         help
             Enable MBEDTLS_SHA512_C adds support for SHA-384 and SHA-512.
 
+    config MBEDTLS_SHA3_C
+        bool "Enable the SHA3 cryptographic hash algorithm"
+        default n
+        help
+            Enabling MBEDTLS_SHA3_C adds support for SHA3.
+            Enabling this configuration option increases the flash footprint
+            by almost 4KB.
+
     choice MBEDTLS_TLS_MODE
         bool "TLS Protocol Role"
         default MBEDTLS_TLS_SERVER_AND_CLIENT
@@ -1103,12 +1111,12 @@ menu "mbedTLS"
     config MBEDTLS_ECP_FIXED_POINT_OPTIM
         bool "Enable fixed-point multiplication optimisations"
         depends on MBEDTLS_ECP_C
-        default y
+        default n
         help
             This configuration option enables optimizations to speedup (about 3 ~ 4 times) the ECP
             fixed point multiplication using pre-computed tables in the flash memory.
-            Disabling this configuration option saves flash footprint (about 29KB if all Elliptic Curve selected)
-            in the application binary.
+            Enabling this configuration option increases the flash footprint
+            (about 29KB if all Elliptic Curve selected) in the application binary.
 
             # end of Elliptic Curve options
 
diff --git a/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c b/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c
index 2da38500877..65f817f7bdd 100644
--- a/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c
+++ b/components/mbedtls/esp_crt_bundle/esp_crt_bundle.c
@@ -1,79 +1,211 @@
 /*
- * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <string.h>
 #include <stdbool.h>
+#include <sys/param.h>
+
+#include "esp_check.h"
 #include "esp_crt_bundle.h"
 #include "esp_log.h"
 
-#define BUNDLE_HEADER_OFFSET 2
-#define CRT_HEADER_OFFSET 4
+#include "mbedtls/pk.h"
+#include "mbedtls/oid.h"
+#include "mbedtls/asn1.h"
+
+/*
+    Format of certificate bundle:
+    First, n uint32 "offset" entries, each describing the start of one certificate's data in terms of
+    bytes from the beginning of the bundle. This offset list is immediately followed by the 1st...n-th
+    certificate data. Hence, the first offset entry, i.e. the uint32 at the very start of the bundle,
+    is equal to the size of the offset list in bytes and therefore the # of certificates in the bundle
+    is [first offset]/sizeof(uint32_t)
+    [offset of 1st certificate](u32)
+    [offset of 2nd certificate](u32)
+    ...
+    [offset of n-th certificate](u32)
+    [1st certificate](variable)
+    ...
+    [n-th certificate](variable)
+
+    Structure of each certificate:
+    [length of CN](u16)
+    [length of key](u16)
+    [CN](variable)
+    [key](variable)
+
+    The offset list is used for fast random access to any certificate by index.
+    For verification, a certificate is looked up by its CN via binary search; for this reason,
+    the offset list *must* be sorted by CN (ascending) and the first certificate must be the
+    one with the least CN in the bundle, so that the first offset in the list still refers to the
+    first certificate after the list (see above).
+
+*/
+
+#define CRT_NAME_LEN_OFFSET 0 //<! offset of certificate name length value
+#define CRT_KEY_LEN_OFFSET (CRT_NAME_LEN_OFFSET + sizeof(uint16_t)) //<! offset of certificate key length value
+#define CRT_NAME_OFFSET (CRT_KEY_LEN_OFFSET + sizeof(uint16_t)) //<! certificate name data starts here
+
+#define CRT_HEADER_SIZE CRT_NAME_OFFSET //<! size of certificate header
 
 static const char *TAG = "esp-x509-crt-bundle";
 
 /* a dummy certificate so that
  * cacert_ptr passes non-NULL check during handshake */
-static mbedtls_x509_crt s_dummy_crt;
-
+static const mbedtls_x509_crt s_dummy_crt;
 
 extern const uint8_t x509_crt_imported_bundle_bin_start[] asm("_binary_x509_crt_bundle_start");
 extern const uint8_t x509_crt_imported_bundle_bin_end[]   asm("_binary_x509_crt_bundle_end");
 
+typedef const uint8_t* bundle_t;
+typedef const uint8_t* cert_t;
+
+static bundle_t s_crt_bundle;
+
+// Read a 16-bit value stored in little-endian format from the given address
+static uint16_t get16_le(const uint8_t* ptr)
+{
+#if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__)
+    return *((const uint16_t*)ptr);
+#else
+    return (((uint16_t)ptr[1]) << 8) | ptr[0];
+#endif
+}
+
+static uint16_t esp_crt_get_name_len(const cert_t cert)
+{
+    return get16_le(cert + CRT_NAME_LEN_OFFSET);
+}
 
-typedef struct crt_bundle_t {
-    const uint8_t **crts;
-    uint16_t num_certs;
-    size_t x509_crt_bundle_len;
-} crt_bundle_t;
+static const uint8_t* esp_crt_get_name(const cert_t cert)
+{
+    return cert + CRT_NAME_OFFSET;
+}
 
-static crt_bundle_t s_crt_bundle;
+static uint16_t esp_crt_get_key_len(const cert_t cert)
+{
+    return get16_le(cert + CRT_KEY_LEN_OFFSET);
+}
 
-static int esp_crt_check_signature(mbedtls_x509_crt *child, const uint8_t *pub_key_buf, size_t pub_key_len);
+static const uint8_t* esp_crt_get_key(const cert_t cert)
+{
+    return esp_crt_get_name(cert) + esp_crt_get_name_len(cert);
+}
 
+static uint16_t esp_crt_get_len(const cert_t cert)
+{
+    return CRT_HEADER_SIZE + esp_crt_get_name_len(cert) + esp_crt_get_key_len(cert);
+}
 
-static int esp_crt_check_signature(mbedtls_x509_crt *child, const uint8_t *pub_key_buf, size_t pub_key_len)
+static uint32_t esp_crt_get_cert_offset(const bundle_t bundle, const uint32_t index)
+{
+    return ((const uint32_t*)bundle)[index];
+}
+
+static uint32_t esp_crt_get_certcount(const bundle_t bundle)
+{
+    // Offset of 1st certificate == end of offset list == size of offset list == # of certs * sizeof(uint32_t)
+    return esp_crt_get_cert_offset(bundle, 0) / sizeof(uint32_t);
+}
+
+/**
+ * @brief Get the certificate at the given index within a bundle.
+ *
+ * @param bundle pointer to the \c bundle_t
+ * @param index of the certificate; must be less than \c esp_crt_get_certcount(...) !
+ * @return pointer to the certificate
+ */
+static cert_t esp_crt_get_cert(const bundle_t bundle, const uint32_t index)
+{
+    return bundle + esp_crt_get_cert_offset(bundle, index);
+}
+
+static int esp_crt_check_signature(const mbedtls_x509_crt* child, const uint8_t* pub_key_buf, const size_t pub_key_len)
 {
     int ret = 0;
-    mbedtls_x509_crt parent;
+    mbedtls_pk_context pubkey;
     const mbedtls_md_info_t *md_info;
-    unsigned char hash[MBEDTLS_MD_MAX_SIZE];
 
-    mbedtls_x509_crt_init(&parent);
+    mbedtls_pk_init(&pubkey);
 
-    if ( (ret = mbedtls_pk_parse_public_key(&parent.pk, pub_key_buf, pub_key_len) ) != 0) {
-        ESP_LOGE(TAG, "PK parse failed with error %X", ret);
+    if (unlikely((ret = mbedtls_pk_parse_public_key(&pubkey, pub_key_buf, pub_key_len)) != 0)) {
+        ESP_LOGE(TAG, "PK parse failed with error 0x%x", -ret);
         goto cleanup;
     }
 
-
     // Fast check to avoid expensive computations when not necessary
-    if (!mbedtls_pk_can_do(&parent.pk, child->MBEDTLS_PRIVATE(sig_pk))) {
-        ESP_LOGE(TAG, "Simple compare failed");
-        ret = -1;
+    if (unlikely(!mbedtls_pk_can_do(&pubkey, child->MBEDTLS_PRIVATE(sig_pk)))) {
+        ESP_LOGE(TAG, "Unsuitable public key");
+        ret = MBEDTLS_ERR_PK_TYPE_MISMATCH;
         goto cleanup;
     }
 
     md_info = mbedtls_md_info_from_type(child->MBEDTLS_PRIVATE(sig_md));
-    if ( (ret = mbedtls_md( md_info, child->tbs.p, child->tbs.len, hash )) != 0 ) {
-        ESP_LOGE(TAG, "Internal mbedTLS error %X", ret);
+
+    if (unlikely(md_info == NULL)) {
+        ESP_LOGE(TAG, "Unknown message digest");
+        ret = MBEDTLS_ERR_X509_FEATURE_UNAVAILABLE;
         goto cleanup;
     }
 
-    if ( (ret = mbedtls_pk_verify_ext( child->MBEDTLS_PRIVATE(sig_pk), child->MBEDTLS_PRIVATE(sig_opts), &parent.pk,
-                                       child->MBEDTLS_PRIVATE(sig_md), hash, mbedtls_md_get_size( md_info ),
-                                       child->MBEDTLS_PRIVATE(sig).p, child->MBEDTLS_PRIVATE(sig).len )) != 0 ) {
+    unsigned char hash[MBEDTLS_MD_MAX_SIZE];
+    const unsigned char md_size = mbedtls_md_get_size(md_info);
 
-        ESP_LOGE(TAG, "PK verify failed with error %X", ret);
+    if ((ret = mbedtls_md(md_info, child->tbs.p, child->tbs.len, hash)) != 0) {
+        ESP_LOGE(TAG, "MD failed with error 0x%x", -ret);
+        goto cleanup;
+    }
+
+    if (unlikely((ret = mbedtls_pk_verify_ext(child->MBEDTLS_PRIVATE(sig_pk), child->MBEDTLS_PRIVATE(sig_opts), &pubkey,
+                                              child->MBEDTLS_PRIVATE(sig_md), hash, md_size,
+                                              child->MBEDTLS_PRIVATE(sig).p, child->MBEDTLS_PRIVATE(sig).len)) != 0)) {
+        ESP_LOGE(TAG, "PK verify failed with error 0x%x", -ret);
         goto cleanup;
     }
-cleanup:
-    mbedtls_x509_crt_free(&parent);
 
+cleanup:
+    mbedtls_pk_free(&pubkey);
     return ret;
 }
 
+static cert_t esp_crt_find_cert(const unsigned char* const issuer, const size_t issuer_len)
+{
+    if (unlikely(issuer == NULL || issuer_len == 0)) {
+        return NULL;
+    }
+
+    int start = 0;
+    int end = esp_crt_get_certcount(s_crt_bundle) - 1;
+    int middle = (start + end) / 2;
+
+    cert_t cert = NULL;
+    size_t cert_name_len = 0;
+
+    /* Look for the certificate using binary search on subject name */
+    while (start <= end) {
+        cert = esp_crt_get_cert(s_crt_bundle, middle);
+        cert_name_len = esp_crt_get_name_len(cert);
+
+        // Issuers are in DER encoding, with lengths encoded in the content; if valid DER, differing lengths
+        // are reflected in differing content.
+        // Still, we won't try to memcmp beyond the given length:
+        int cmp_res = memcmp(issuer, esp_crt_get_name(cert), MIN(issuer_len, cert_name_len));
+
+        if (unlikely(cmp_res == 0)) {
+            return cert;
+        } else if (cmp_res < 0) {
+            end = middle - 1;
+        } else {
+            start = middle + 1;
+        }
+        middle = (start + end) / 2;
+    }
+
+    return NULL;
+}
+
 
 /* This callback is called for every certificate in the chain. If the chain
  * is proper each intermediate certificate is validated through its parent
@@ -81,9 +213,9 @@ static int esp_crt_check_signature(mbedtls_x509_crt *child, const uint8_t *pub_k
  * only verify the first untrusted link in the chain is signed by the
  * root certificate in the trusted bundle
 */
-int esp_crt_verify_callback(void *buf, mbedtls_x509_crt *crt, int depth, uint32_t *flags)
+int esp_crt_verify_callback(void *buf, mbedtls_x509_crt* const crt, const int depth, uint32_t* const flags)
 {
-    mbedtls_x509_crt *child = crt;
+    const mbedtls_x509_crt* const child = crt;
 
     /* It's OK for a trusted cert to have a weak signature hash alg.
        as we already trust this certificate */
@@ -94,120 +226,119 @@ int esp_crt_verify_callback(void *buf, mbedtls_x509_crt *crt, int depth, uint32_
     }
 
 
-    if (s_crt_bundle.crts == NULL) {
+    if (unlikely(s_crt_bundle == NULL)) {
         ESP_LOGE(TAG, "No certificates in bundle");
         return MBEDTLS_ERR_X509_FATAL_ERROR;
     }
 
-    ESP_LOGD(TAG, "%d certificates in bundle", s_crt_bundle.num_certs);
+    ESP_LOGD(TAG, "%" PRIu16 " certificates in bundle", (uint16_t)esp_crt_get_certcount(s_crt_bundle));
 
-    size_t name_len = 0;
-    const uint8_t *crt_name;
+    cert_t cert = esp_crt_find_cert(child->issuer_raw.p, child->issuer_raw.len);
 
-    bool crt_found = false;
-    int start = 0;
-    int end = s_crt_bundle.num_certs - 1;
-    int middle = (end - start) / 2;
+    if (likely(cert != NULL)) {
 
-    /* Look for the certificate using binary search on subject name */
-    while (start <= end) {
-        name_len = s_crt_bundle.crts[middle][0] << 8 | s_crt_bundle.crts[middle][1];
-        crt_name = s_crt_bundle.crts[middle] + CRT_HEADER_OFFSET;
+        const int ret = esp_crt_check_signature(child, esp_crt_get_key(cert), esp_crt_get_key_len(cert));
 
-        int cmp_res = memcmp(child->issuer_raw.p, crt_name, name_len );
-        if (cmp_res == 0) {
-            crt_found = true;
-            break;
-        } else if (cmp_res < 0) {
-            end = middle - 1;
+        if (likely(ret == 0)) {
+            ESP_LOGI(TAG, "Certificate validated");
+            *flags = 0;
+            return 0;
         } else {
-            start = middle + 1;
+            ESP_LOGE(TAG, "Certificate matched but signature verification failed");
+#if (CONFIG_LOG_DEFAULT_LEVEL_DEBUG || CONFIG_LOG_DEFAULT_LEVEL_VERBOSE)
+            char *cert_name = malloc((esp_crt_get_name_len(cert) + 1) * sizeof(char));
+            if (cert_name) {
+                memcpy(cert_name, esp_crt_get_name(cert), esp_crt_get_name_len(cert));
+                cert_name[esp_crt_get_name_len(cert)] = '\0';
+                ESP_LOGE(TAG, "Certificate matched with %s but signature verification failed", cert_name);
+                free(cert_name);
+            }
+#endif
         }
-        middle = (start + end) / 2;
-    }
-
-    int ret = MBEDTLS_ERR_X509_FATAL_ERROR;
-    if (crt_found) {
-        size_t key_len = s_crt_bundle.crts[middle][2] << 8 | s_crt_bundle.crts[middle][3];
-        ret = esp_crt_check_signature(child, s_crt_bundle.crts[middle] + CRT_HEADER_OFFSET + name_len, key_len);
-    }
 
-    if (ret == 0) {
-        ESP_LOGI(TAG, "Certificate validated");
-        *flags = 0;
-        return 0;
+    } else {
+        ESP_LOGI(TAG, "No matching trusted root certificate found");
     }
 
     ESP_LOGE(TAG, "Failed to verify certificate");
-    return MBEDTLS_ERR_X509_FATAL_ERROR;
+    return MBEDTLS_ERR_X509_CERT_VERIFY_FAILED;
 }
 
-
-/* Initialize the bundle into an array so we can do binary search for certs,
-   the bundle generated by the python utility is already presorted by subject name
+/**
+ * @brief Perform some consistency checks on the user-provided bundle data to try and make sure
+ * it actually is a certificate bundle.
+ *
+ * @param x509_bundle pointer to the bundle data
+ * @param bundle_size size of bundle data
+ * @return true the given bundle data is consistent
+ * @return false the given bundle data is invalid
  */
-static esp_err_t esp_crt_bundle_init(const uint8_t *x509_bundle, size_t bundle_size)
+static bool esp_crt_check_bundle(const uint8_t* const x509_bundle, const size_t bundle_size)
 {
-    if (bundle_size < BUNDLE_HEADER_OFFSET + CRT_HEADER_OFFSET) {
-        ESP_LOGE(TAG, "Invalid certificate bundle");
-        return ESP_ERR_INVALID_ARG;
+    if (unlikely(x509_bundle == NULL || bundle_size <= (sizeof(uint32_t) + CRT_HEADER_SIZE))) {
+        // Bundle is too small for even one offset and one certificate
+        return false;
     }
 
-    uint16_t num_certs = (x509_bundle[0] << 8) | x509_bundle[1];
-    if (num_certs > CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS) {
-        ESP_LOGE(TAG, "No. of certs in the certificate bundle = %d exceeds\n"
-                      "Max allowed certificates in the certificate bundle = %d\n"
-                      "Please update the menuconfig option with appropriate value", num_certs, CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS);
-        return ESP_ERR_INVALID_ARG;
+    // Pointer to the first offset entry
+    const uint32_t* offsets = (const uint32_t*)x509_bundle;
+
+    if (unlikely(offsets[0] == 0 || (offsets[0] % sizeof(uint32_t)) != 0)) {
+        // First offset is invalid.
+        // The first certificate must start after N uint32_t offset values.
+        return false;
     }
 
-    const uint8_t **crts = calloc(num_certs, sizeof(x509_bundle));
-    if (crts == NULL) {
-        ESP_LOGE(TAG, "Unable to allocate memory for bundle");
-        return ESP_ERR_NO_MEM;
+    if (unlikely(offsets[0] >= bundle_size)) {
+        // First cert starts beyond end of bundle
+        return false;
     }
 
-    const uint8_t *cur_crt;
-    /* This is the maximum region that is allowed to access */
-    const uint8_t *bundle_end = x509_bundle + bundle_size;
-    cur_crt = x509_bundle + BUNDLE_HEADER_OFFSET;
+    const uint32_t num_certs = esp_crt_get_certcount(x509_bundle);
+
+    if (unlikely(num_certs > CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS)) {
+        ESP_LOGE(TAG, "Cert bundle certificates exceed max allowed certificates");
+        return false;
+    }
 
-    for (int i = 0; i < num_certs; i++) {
-        crts[i] = cur_crt;
-        if (cur_crt + CRT_HEADER_OFFSET > bundle_end) {
-            ESP_LOGE(TAG, "Invalid certificate bundle");
-            free(crts);
-            return ESP_ERR_INVALID_ARG;
+    // Check all offsets for consistency with certificate data
+    for (uint32_t i = 0; i < num_certs - 1; ++i) {
+        const uint32_t off = offsets[i];
+        cert_t cert = x509_bundle + off;
+        // The next offset in the list must point to right after the current cert
+        const uint32_t expected_next_offset = off + esp_crt_get_len(cert);
+
+        if (unlikely(offsets[i + 1] != expected_next_offset || expected_next_offset >= bundle_size)) {
+            return false;
         }
-        size_t name_len = cur_crt[0] << 8 | cur_crt[1];
-        size_t key_len = cur_crt[2] << 8 | cur_crt[3];
-        cur_crt = cur_crt + CRT_HEADER_OFFSET + name_len + key_len;
     }
 
-    if (cur_crt > bundle_end) {
-        ESP_LOGE(TAG, "Invalid certificate bundle");
-        free(crts);
+    // All checks passed.
+    return true;
+}
+
+/*
+   the bundle generated by the python utility is already presorted by subject name
+ */
+static esp_err_t esp_crt_bundle_init(const uint8_t* const x509_bundle, const size_t bundle_size)
+{
+    if (likely(esp_crt_check_bundle(x509_bundle, bundle_size))) {
+        s_crt_bundle = x509_bundle;
+        return ESP_OK;
+    } else {
         return ESP_ERR_INVALID_ARG;
     }
-
-    /* The previous crt bundle is only updated when initialization of the
-     * current crt_bundle is successful */
-    /* Free previous crt_bundle */
-    free(s_crt_bundle.crts);
-    s_crt_bundle.num_certs = num_certs;
-    s_crt_bundle.crts = crts;
-    return ESP_OK;
 }
 
 esp_err_t esp_crt_bundle_attach(void *conf)
 {
     esp_err_t ret = ESP_OK;
     // If no bundle has been set by the user then use the bundle embedded in the binary
-    if (s_crt_bundle.crts == NULL) {
+    if (s_crt_bundle == NULL) {
         ret = esp_crt_bundle_init(x509_crt_imported_bundle_bin_start, x509_crt_imported_bundle_bin_end - x509_crt_imported_bundle_bin_start);
     }
 
-    if (ret != ESP_OK) {
+    if (unlikely(ret != ESP_OK)) {
         ESP_LOGE(TAG, "Failed to attach bundle");
         return ret;
     }
@@ -218,8 +349,7 @@ esp_err_t esp_crt_bundle_attach(void *conf)
          * cacert_ptr passes non-NULL check during handshake
          */
         mbedtls_ssl_config *ssl_conf = (mbedtls_ssl_config *)conf;
-        mbedtls_x509_crt_init(&s_dummy_crt);
-        mbedtls_ssl_conf_ca_chain(ssl_conf, &s_dummy_crt, NULL);
+        mbedtls_ssl_conf_ca_chain(ssl_conf, (mbedtls_x509_crt*)&s_dummy_crt, NULL);
         mbedtls_ssl_conf_verify(ssl_conf, esp_crt_verify_callback, NULL);
     }
 
@@ -228,8 +358,7 @@ esp_err_t esp_crt_bundle_attach(void *conf)
 
 void esp_crt_bundle_detach(mbedtls_ssl_config *conf)
 {
-    free(s_crt_bundle.crts);
-    s_crt_bundle.crts = NULL;
+    s_crt_bundle = NULL;
     if (conf) {
         mbedtls_ssl_conf_verify(conf, NULL, NULL);
     }
@@ -239,3 +368,8 @@ esp_err_t esp_crt_bundle_set(const uint8_t *x509_bundle, size_t bundle_size)
 {
     return esp_crt_bundle_init(x509_bundle, bundle_size);
 }
+
+bool esp_crt_bundle_in_use(const mbedtls_x509_crt* ca_chain)
+{
+    return ((ca_chain == &s_dummy_crt) ? true : false);
+}
diff --git a/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py b/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py
index 0211514a460..2e5bca544b1 100755
--- a/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py
+++ b/components/mbedtls/esp_crt_bundle/gen_crt_bundle.py
@@ -8,18 +8,16 @@
 # The bundle will have the format: number of certificates; crt 1 subject name length; crt 1 public key length;
 # crt 1 subject name; crt 1 public key; crt 2...
 #
-# SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
-
-from __future__ import with_statement
-
 import argparse
 import csv
 import os
 import re
 import struct
 import sys
-from io import open
+
+DEFAULT_CERT_BUNDLE_MAX_CERTS = 200
 
 try:
     from cryptography import x509
@@ -54,9 +52,6 @@ def __init__(self):
         self.certificates = []
         self.compressed_crts = []
 
-        if os.path.isfile(ca_bundle_bin_file):
-            os.remove(ca_bundle_bin_file)
-
     def add_from_path(self, crts_path):
 
         found = False
@@ -116,11 +111,21 @@ def add_from_der(self, crt_str):
         self.certificates.append(x509.load_der_x509_certificate(crt_str, default_backend()))
         status('Successfully added 1 certificate')
 
-    def create_bundle(self):
+    def create_bundle(self, max_certs=DEFAULT_CERT_BUNDLE_MAX_CERTS):
+        if max_certs < len(self.certificates):
+            critical(f'No. of certs in the certificate bundle = {len(self.certificates)} exceeds\n \
+                    Max allowed certificates in the certificate bundle = {max_certs} \
+                    Please update the menuconfig option with appropriate value')
+            raise ValueError
+
         # Sort certificates in order to do binary search when looking up certificates
         self.certificates = sorted(self.certificates, key=lambda cert: cert.subject.public_bytes(default_backend()))
 
-        bundle = struct.pack('>H', len(self.certificates))
+        # List of offsets in bytes from the start of the bundle to each certificate inside
+        offsets = []
+        len_offsets = 4 * len(self.certificates)  # final size of the offsets list
+
+        bundle = b''
 
         for crt in self.certificates:
             """ Read the public key as DER format """
@@ -132,12 +137,18 @@ def create_bundle(self):
 
             name_len = len(sub_name_der)
             key_len = len(pub_key_der)
-            len_data = struct.pack('>HH', name_len, key_len)
+            len_data = struct.pack('<HH', name_len, key_len)
+
+            # Certificate starts at this position in the bundle
+            offsets.append(len_offsets + len(bundle))
 
             bundle += len_data
             bundle += sub_name_der
             bundle += pub_key_der
 
+        # Output all offsets before the first certificate
+        bundle = struct.pack('<{0:d}L'.format(len(offsets)), *offsets) + bundle
+
         return bundle
 
     def add_with_filter(self, crts_path, filter_path):
@@ -182,6 +193,8 @@ def main():
                         help='Paths to the custom certificate folders or files to parse, parses all .pem or .der files')
     parser.add_argument('--filter', '-f', help='Path to CSV-file where the second columns contains the name of the certificates \
                         that should be included from cacrt_all.pem')
+    parser.add_argument('--max-certs', '-m', help='Maximum number of certificates allowed in the certificate bundle',
+                        type=int, default=DEFAULT_CERT_BUNDLE_MAX_CERTS)
 
     args = parser.parse_args()
 
@@ -202,7 +215,7 @@ def main():
 
     status('Successfully added %d certificates in total' % len(bundle.certificates))
 
-    crt_bundle = bundle.create_bundle()
+    crt_bundle = bundle.create_bundle(args.max_certs)
 
     with open(ca_bundle_bin_file, 'wb') as f:
         f.write(crt_bundle)
diff --git a/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h b/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h
index 49069185b3a..61c09f0bd03 100644
--- a/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h
+++ b/components/mbedtls/esp_crt_bundle/include/esp_crt_bundle.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,7 +27,7 @@ extern "C" {
  *
  * @return
  *             - ESP_OK  if adding certificates was successful.
- *             - Other   if an error occured or an action must be taken by the calling process.
+ *             - Other   if an error occurred or an action must be taken by the calling process.
  */
 esp_err_t esp_crt_bundle_attach(void *conf);
 
@@ -55,10 +55,19 @@ void esp_crt_bundle_detach(mbedtls_ssl_config *conf);
  *
  * @return
  *             - ESP_OK  if adding certificates was successful.
- *             - Other   if an error occured or an action must be taken by the calling process.
+ *             - Other   if an error occurred or an action must be taken by the calling process.
  */
 esp_err_t esp_crt_bundle_set(const uint8_t *x509_bundle, size_t bundle_size);
 
+/**
+ * @brief   Check if the given CA certificate chain is the default "dummy"
+ *          certificate chain attached by the esp_crt_bundle
+ *
+ * @param ca_chain  A pointer to the CA chain.
+ * @return true     if the ca_chain is the dummy CA chain attached by esp_crt_bundle
+ * @return false    otherwise
+ */
+bool esp_crt_bundle_in_use(const mbedtls_x509_crt* ca_chain);
 
 #ifdef __cplusplus
 }
diff --git a/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/baltimore_crt_bundle b/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/baltimore_crt_bundle
index 07068589404..14354a43358 100644
Binary files a/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/baltimore_crt_bundle and b/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/baltimore_crt_bundle differ
diff --git a/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/entrust_crt_bundle b/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/entrust_crt_bundle
index cc20092c0d7..555bf671d18 100644
Binary files a/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/entrust_crt_bundle and b/components/mbedtls/esp_crt_bundle/test_gen_crt_bundle/entrust_crt_bundle differ
diff --git a/components/mbedtls/mbedtls b/components/mbedtls/mbedtls
index f635fed5926..98fcfd6d2ce 160000
--- a/components/mbedtls/mbedtls
+++ b/components/mbedtls/mbedtls
@@ -1 +1 @@
-Subproject commit f635fed59269b1ae14d1a1c50403cd63f78ac094
+Subproject commit 98fcfd6d2cea90d306e8fde8e5bffd6087c9cda8
diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
index 5846c9f081c..6fc1f5661ce 100644
--- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
+++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c
@@ -322,7 +322,7 @@ static inline void dma_desc_append(crypto_dma_desc_t **head, crypto_dma_desc_t *
 
 static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_t *actual_size)
 {
-    return heap_caps_aligned_calloc(DMA_DESC_MEM_ALIGN_SIZE, num, size, caps | MALLOC_CAP_DMA | MALLOC_CAP_8BIT);
+    return heap_caps_aligned_calloc(DMA_DESC_MEM_ALIGN_SIZE, num, size, caps);
 }
 
 static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_dma_desc_num)
@@ -766,14 +766,14 @@ int esp_aes_process_dma_gcm(esp_aes_context *ctx, const unsigned char *input, un
 
     out_desc_tail = &output_desc[output_dma_desc_num - 1];
 
-    len_desc = aes_dma_calloc(1, sizeof(crypto_dma_desc_t), MALLOC_CAP_DMA, NULL);
+    len_desc = aes_dma_calloc(1, sizeof(crypto_dma_desc_t), AES_DMA_ALLOC_CAPS, NULL);
     if (len_desc == NULL) {
         mbedtls_platform_zeroize(output, len);
         ESP_LOGE(TAG, "Failed to allocate memory for len descriptor");
         return -1;
     }
 
-    uint32_t *len_buf = aes_dma_calloc(4, sizeof(uint32_t), MALLOC_CAP_DMA, NULL);
+    uint32_t *len_buf = aes_dma_calloc(4, sizeof(uint32_t), AES_DMA_ALLOC_CAPS, NULL);
     if (len_buf == NULL) {
         mbedtls_platform_zeroize(output, len);
         ESP_LOGE(TAG, "Failed to allocate memory for len buffer");
diff --git a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c
index a5ea9fb337a..d76f6b5049c 100644
--- a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c
+++ b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.c
@@ -1,11 +1,16 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <string.h>
 #include "esp_mbedtls_dynamic_impl.h"
+#include "sdkconfig.h"
+
+#if CONFIG_MBEDTLS_CERTIFICATE_BUNDLE
+#include "esp_crt_bundle.h"
+#endif
 
 #define COUNTER_SIZE (8)
 #define CACHE_IV_SIZE (16)
@@ -532,7 +537,18 @@ void esp_mbedtls_free_cacert(mbedtls_ssl_context *ssl)
     if (ssl->MBEDTLS_PRIVATE(conf)->MBEDTLS_PRIVATE(ca_chain)) {
         mbedtls_ssl_config *conf = (mbedtls_ssl_config * )mbedtls_ssl_context_get_config(ssl);
 
+#if CONFIG_MBEDTLS_CERTIFICATE_BUNDLE
+        /* In case of mbedtls certificate bundle, we attach a "static const"
+         * dummy cert, thus we need to avoid the write operations (memset())
+         * performed by `mbedtls_x509_crt_free()`
+         */
+        if (!esp_crt_bundle_in_use(conf->MBEDTLS_PRIVATE(ca_chain))) {
+            mbedtls_x509_crt_free(conf->MBEDTLS_PRIVATE(ca_chain));
+        }
+#else
         mbedtls_x509_crt_free(conf->MBEDTLS_PRIVATE(ca_chain));
+#endif
+
         conf->MBEDTLS_PRIVATE(ca_chain) = NULL;
     }
 }
diff --git a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h
index 72641b3a549..ad7a716be58 100644
--- a/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h
+++ b/components/mbedtls/port/dynamic/esp_mbedtls_dynamic_impl.h
@@ -24,6 +24,7 @@
 #include "mbedtls/ssl.h"
 #include "mbedtls/platform.h"
 #include "esp_log.h"
+#include "sdkconfig.h"
 
 #define TRACE_CHECK(_fn, _state) \
 ({ \
diff --git a/components/mbedtls/port/include/mbedtls/esp_config.h b/components/mbedtls/port/include/mbedtls/esp_config.h
index 90d90729bb5..d1413571db7 100644
--- a/components/mbedtls/port/include/mbedtls/esp_config.h
+++ b/components/mbedtls/port/include/mbedtls/esp_config.h
@@ -2560,6 +2560,21 @@
 #undef MBEDTLS_SHA512_C
 #endif
 
+/**
+ * \def MBEDTLS_SHA3_C
+ *
+ *  Enable the SHA3 cryptographic hash algorithm.
+ *
+ * Module:  library/sha3.c
+ *
+ * This module adds support for SHA3.
+ */
+#ifdef CONFIG_MBEDTLS_SHA3_C
+#define MBEDTLS_SHA3_C
+#else
+#undef MBEDTLS_SHA3_C
+#endif
+
 /**
  * \def MBEDTLS_SSL_CACHE_C
  *
diff --git a/components/mbedtls/test_apps/.build-test-rules.yml b/components/mbedtls/test_apps/.build-test-rules.yml
index f33fabc474c..0e72c8d3dc4 100644
--- a/components/mbedtls/test_apps/.build-test-rules.yml
+++ b/components/mbedtls/test_apps/.build-test-rules.yml
@@ -7,5 +7,6 @@ components/mbedtls/test_apps:
     - if: CONFIG_NAME == "ecdsa_sign" and SOC_ECDSA_SUPPORTED != 1
   depends_components:
     - efuse
-  depends_filepatterns:
-    - components/mbedtls/port/ecdsa/*
+    - mbedtls
+    - esp_security
+    - esp_mm
diff --git a/components/mbedtls/test_apps/main/crts/server_cert_bundle b/components/mbedtls/test_apps/main/crts/server_cert_bundle
index 0b7f09aa06d..5a0a2f139f5 100644
Binary files a/components/mbedtls/test_apps/main/crts/server_cert_bundle and b/components/mbedtls/test_apps/main/crts/server_cert_bundle differ
diff --git a/components/mbedtls/test_apps/main/test_aes.c b/components/mbedtls/test_apps/main/test_aes.c
index 5ac71e82ec9..c73256e8d72 100644
--- a/components/mbedtls/test_apps/main/test_aes.c
+++ b/components/mbedtls/test_apps/main/test_aes.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -67,7 +67,7 @@ static const uint8_t iv[] = {
     print(as_c_array(plain))
     ct = encryptor.update(plain) + encryptor.finalize()
 
-    print("Chipertext: {}".format(as_c_array(ct)))
+    print("Ciphertext: {}".format(as_c_array(ct)))
 */
 TEST_CASE("mbedtls CBC AES-256 test", "[aes]")
 {
@@ -85,11 +85,11 @@ TEST_CASE("mbedtls CBC AES-256 test", "[aes]")
     memcpy(nonce, iv, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -100,19 +100,19 @@ TEST_CASE("mbedtls CBC AES-256 test", "[aes]")
     memset(decryptedtext, 0x0, SZ);
 
     // Encrypt
-    mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext);
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
+    mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
 
     // Decrypt
     memcpy(nonce, iv, 16);
     mbedtls_aes_setkey_dec(&ctx, key_256, 256);
-    mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext);
+    mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext);
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -134,11 +134,11 @@ TEST_CASE("mbedtls CBC AES-256 DMA buffer align test", "[aes]")
     memcpy(nonce, iv, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -149,19 +149,19 @@ TEST_CASE("mbedtls CBC AES-256 DMA buffer align test", "[aes]")
     memset(decryptedtext, 0x0, SZ);
 
     // Encrypt
-    mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext);
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
+    mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
 
     // Decrypt
     memcpy(nonce, iv, 16);
     mbedtls_aes_setkey_dec(&ctx, key_256, 256);
-    mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext);
+    mbedtls_aes_crypt_cbc(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext);
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -183,11 +183,11 @@ TEST_CASE("mbedtls CTR AES-256 test", "[aes]")
     memcpy(nonce, iv, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -198,19 +198,19 @@ TEST_CASE("mbedtls CTR AES-256 test", "[aes]")
     memset(decryptedtext, 0x0, SZ);
 
     // Encrypt
-    mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, plaintext, chipertext);
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
+    mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, plaintext, ciphertext);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
 
     // Decrypt
     nc_off = 0;
     memcpy(nonce, iv, 16);
-    mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, chipertext, decryptedtext);
+    mbedtls_aes_crypt_ctr(&ctx, SZ, &nc_off, nonce, stream_block, ciphertext, decryptedtext);
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -231,11 +231,11 @@ TEST_CASE("mbedtls OFB AES-256 test", "[aes]")
     memcpy(nonce, iv, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -246,19 +246,19 @@ TEST_CASE("mbedtls OFB AES-256 test", "[aes]")
     memset(decryptedtext, 0x0, SZ);
 
     // Encrypt
-    mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, chipertext);
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
+    mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, ciphertext);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
 
     // Decrypt
     nc_off = 0;
     memcpy(nonce, iv, 16);
-    mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, chipertext, decryptedtext);
+    mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, ciphertext, decryptedtext);
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -278,11 +278,11 @@ TEST_CASE("mbedtls CFB-8 AES-256 test", "[aes]")
     memcpy(nonce, iv, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -293,18 +293,18 @@ TEST_CASE("mbedtls CFB-8 AES-256 test", "[aes]")
     memset(decryptedtext, 0x0, SZ);
 
     // Encrypt
-    mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, chipertext);
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
+    mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, SZ, nonce, plaintext, ciphertext);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
 
     // Decrypt
     memcpy(nonce, iv, 16);
-    mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, chipertext, decryptedtext);
+    mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, SZ, nonce, ciphertext, decryptedtext);
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -325,11 +325,11 @@ TEST_CASE("mbedtls CFB-128 AES-256 test", "[aes]")
     memcpy(nonce, iv, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -340,19 +340,19 @@ TEST_CASE("mbedtls CFB-128 AES-256 test", "[aes]")
     memset(decryptedtext, 0x0, SZ);
 
     // Encrypt
-    mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT,  SZ, &nc_off, nonce, plaintext, chipertext);
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
+    mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT,  SZ, &nc_off, nonce, plaintext, ciphertext);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
 
     // Decrypt
     nc_off = 0;
     memcpy(nonce, iv, 16);
-    mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, SZ, &nc_off, nonce, chipertext, decryptedtext);
+    mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, SZ, &nc_off, nonce, ciphertext, decryptedtext);
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -401,11 +401,11 @@ static void aes_ctr_stream_test(void)
     memset(key, 0x44, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -419,7 +419,7 @@ static void aes_ctr_stream_test(void)
     for (int bytes_to_process = 1; bytes_to_process < SZ; bytes_to_process++) {
         ESP_LOGD("test", "bytes_to_process %d", bytes_to_process);
         memset(nonce, 0xEE, 16);
-        memset(chipertext, 0x0, SZ);
+        memset(ciphertext, 0x0, SZ);
         memset(decryptedtext, 0x0, SZ);
 
         size_t offset = 0;
@@ -429,12 +429,12 @@ static void aes_ctr_stream_test(void)
             size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process;
 
             mbedtls_aes_crypt_ctr(&ctx, length, &offset, nonce,
-                                  stream_block, plaintext + idx, chipertext + idx );
+                                  stream_block, plaintext + idx, ciphertext + idx );
         }
         ESP_LOG_BUFFER_HEXDUMP("expected", expected_cipher, SZ, ESP_LOG_DEBUG);
-        ESP_LOG_BUFFER_HEXDUMP("actual  ", chipertext, SZ, ESP_LOG_DEBUG);
+        ESP_LOG_BUFFER_HEXDUMP("actual  ", ciphertext, SZ, ESP_LOG_DEBUG);
 
-        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ);
+        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ);
 
         // Decrypt
         memset(nonce, 0xEE, 16);
@@ -444,7 +444,7 @@ static void aes_ctr_stream_test(void)
             // Limit length of last call to avoid exceeding buffer size
             size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process;
             mbedtls_aes_crypt_ctr(&ctx, length, &offset, nonce,
-                                  stream_block, chipertext + idx, decryptedtext + idx );
+                                  stream_block, ciphertext + idx, decryptedtext + idx );
         }
         ESP_LOG_BUFFER_HEXDUMP("decrypted", decryptedtext, SZ, ESP_LOG_DEBUG);
         TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
@@ -452,7 +452,7 @@ static void aes_ctr_stream_test(void)
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -505,11 +505,11 @@ TEST_CASE("mbedtls OFB stream test", "[aes]")
     memset(key, 0x44, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -529,10 +529,10 @@ TEST_CASE("mbedtls OFB stream test", "[aes]")
         for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) {
             // Limit length of last call to avoid exceeding buffer size
             size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process;
-            mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, plaintext + idx, chipertext + idx);
+            mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, plaintext + idx, ciphertext + idx);
 
         }
-        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ);
+        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ);
 
         // Decrypt
         memset(iv, 0xEE, 16);
@@ -541,14 +541,14 @@ TEST_CASE("mbedtls OFB stream test", "[aes]")
         for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) {
             // Limit length of last call to avoid exceeding buffer size
             size_t length = (idx + bytes_to_process > SZ) ? (SZ - idx) : bytes_to_process;
-            mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, chipertext + idx, decryptedtext + idx);
+            mbedtls_aes_crypt_ofb(&ctx, length, &offset, iv, ciphertext + idx, decryptedtext + idx);
         }
         TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
     }
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -595,11 +595,11 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]")
     memset(key, 0x44, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -616,16 +616,16 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]")
         for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) {
             // Limit length of last call to avoid exceeding buffer size
             size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process;
-            mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, length, iv, plaintext + idx, chipertext + idx);
+            mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_ENCRYPT, length, iv, plaintext + idx, ciphertext + idx);
 
         }
-        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ);
+        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ);
 
         memset(iv, 0xEE, 16);
         for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) {
             // Limit length of last call to avoid exceeding buffer size
             size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process;
-            mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, length, iv, chipertext + idx, decryptedtext + idx);
+            mbedtls_aes_crypt_cfb8(&ctx, MBEDTLS_AES_DECRYPT, length, iv, ciphertext + idx, decryptedtext + idx);
 
         }
         TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
@@ -633,7 +633,7 @@ TEST_CASE("mbedtls CFB8 stream test", "[aes]")
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -680,11 +680,11 @@ TEST_CASE("mbedtls CFB128 stream test", "[aes]")
     memset(key, 0x44, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -703,24 +703,24 @@ TEST_CASE("mbedtls CFB128 stream test", "[aes]")
     for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) {
         // Limit length of last call to avoid exceeding buffer size
         size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process;
-        mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, length, &offset, iv, plaintext + idx, chipertext + idx);
+        mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_ENCRYPT, length, &offset, iv, plaintext + idx, ciphertext + idx);
 
     }
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, chipertext, SZ);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher, ciphertext, SZ);
 
     offset = 0;
     memset(iv, 0xEE, 16);
     for (int idx = 0; idx < SZ; idx = idx + bytes_to_process) {
         // Limit length of last call to avoid exceeding buffer size
         size_t length = ( (idx + bytes_to_process) > SZ) ? (SZ - idx) : bytes_to_process;
-        mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, length, &offset, iv, chipertext + idx, decryptedtext + idx);
+        mbedtls_aes_crypt_cfb128(&ctx, MBEDTLS_AES_DECRYPT, length, &offset, iv, ciphertext + idx, decryptedtext + idx);
 
     }
     TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -804,11 +804,11 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]")
     memcpy(nonce, iv, 16);
 
     // allocate internal memory
-    uint8_t *chipertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *plaintext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -819,20 +819,20 @@ TEST_CASE("mbedtls OFB, chained DMA descriptors", "[aes]")
     memset(decryptedtext, 0x0, SZ);
 
     // Encrypt
-    mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, chipertext);
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, chipertext + SZ - 32, 32);
+    mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, plaintext, ciphertext);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_end, ciphertext + SZ - 32, 32);
 
 
     // Decrypt
     nc_off = 0;
     memcpy(nonce, iv, 16);
-    mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, chipertext, decryptedtext);
+    mbedtls_aes_crypt_ofb(&ctx, SZ, &nc_off, nonce, ciphertext, decryptedtext);
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -858,11 +858,11 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps)
     memset(key, 0x1E, 16);
 
     // allocate memory according the requested caps
-    uint8_t *chipertext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, output_buf_caps);
+    uint8_t *ciphertext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, output_buf_caps);
     uint8_t *plaintext = heap_caps_malloc(SZ + ALIGNMENT_SIZE_BYTES, input_buf_caps);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(plaintext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
@@ -877,14 +877,14 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps)
         // Encrypt with input buffer in external ram
         offset = 0;
         memset(nonce, 0x2F, 16);
-        mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, chipertext + i);
-        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, chipertext + i + SZ - 32, 32);
+        mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, plaintext + i, ciphertext + i);
+        TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_ctr_end, ciphertext + i + SZ - 32, 32);
 
         // Decrypt
         offset = 0;
         memset(nonce, 0x2F, 16);
         // Decrypt with input buffer in instruction memory, the crypto DMA can't access this
-        mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, chipertext + i, decryptedtext);
+        mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, ciphertext + i, decryptedtext);
 
         TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext, decryptedtext, SZ);
 
@@ -892,7 +892,7 @@ void aes_ctr_alignment_test(uint32_t input_buf_caps, uint32_t output_buf_caps)
 
     mbedtls_aes_free(&ctx);
     free(plaintext);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -1483,10 +1483,10 @@ void aes_ext_flash_ctr_test(uint32_t output_buf_caps)
     memset(nonce, 0x2F, 16);
     memset(key, 0x1E, 16);
 
-    uint8_t *chipertext = heap_caps_malloc(SZ, output_buf_caps);
+    uint8_t *ciphertext = heap_caps_malloc(SZ, output_buf_caps);
     uint8_t *decryptedtext = heap_caps_malloc(SZ, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
 
-    TEST_ASSERT_NOT_NULL(chipertext);
+    TEST_ASSERT_NOT_NULL(ciphertext);
     TEST_ASSERT_NOT_NULL(decryptedtext);
 
     mbedtls_aes_init(&ctx);
@@ -1497,19 +1497,19 @@ void aes_ext_flash_ctr_test(uint32_t output_buf_caps)
     // Encrypt with input buffer in external flash
     offset = 0;
     memset(nonce, 0x2F, 16);
-    mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, long_input, chipertext);
-    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_long_input_end, chipertext + SZ - 32, 32);
+    mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, long_input, ciphertext);
+    TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_cipher_long_input_end, ciphertext + SZ - 32, 32);
 
     // Decrypt
     offset = 0;
     memset(nonce, 0x2F, 16);
     // Decrypt with input buffer in external flash, the crypto DMA can't access this
-    mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, chipertext, decryptedtext);
+    mbedtls_aes_crypt_ctr(&ctx, SZ, &offset, nonce, stream_block, ciphertext, decryptedtext);
 
     TEST_ASSERT_EQUAL_HEX8_ARRAY(long_input, decryptedtext, SZ);
 
     mbedtls_aes_free(&ctx);
-    free(chipertext);
+    free(ciphertext);
     free(decryptedtext);
 }
 
@@ -1540,7 +1540,8 @@ static void __attribute__((unused)) aes_ctr_stream_test_task(void *pv)
     vTaskDelete(NULL);
 }
 
-#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
+#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK && !CONFIG_IDF_TARGET_ESP32H2
+// Not enough rtc memory for test on H2
 
 TEST_CASE("mbedtls AES stack in RTC RAM", "[mbedtls]")
 {
@@ -1561,9 +1562,9 @@ TEST_CASE("mbedtls AES stack in RTC RAM", "[mbedtls]")
     vSemaphoreDelete(done_sem);
 }
 
-#endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
+#endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK && !CONFIG_IDF_TARGET_ESP32H2
 
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC
+#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM && CONFIG_SPIRAM_USE_MALLOC
 
 TEST_CASE("mbedtls AES stack in PSRAM", "[mbedtls]")
 {
@@ -1585,4 +1586,4 @@ TEST_CASE("mbedtls AES stack in PSRAM", "[mbedtls]")
     vSemaphoreDelete(done_sem);
 }
 
-#endif //CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC
+#endif //CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM && CONFIG_SPIRAM_USE_MALLOC
diff --git a/components/mbedtls/test_apps/main/test_esp_crt_bundle.c b/components/mbedtls/test_apps/main/test_esp_crt_bundle.c
index 777af0425bd..4b4ae1f927b 100644
--- a/components/mbedtls/test_apps/main/test_esp_crt_bundle.c
+++ b/components/mbedtls/test_apps/main/test_esp_crt_bundle.c
@@ -6,8 +6,9 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
- * SPDX-FileContributor: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2019-2024 Espressif Systems (Shanghai) CO LTD
  */
+#include <string.h>
 #include "esp_err.h"
 #include "esp_log.h"
 
@@ -41,6 +42,7 @@ extern const uint8_t server_cert_chain_pem_end[]   asm("_binary_server_cert_chai
 extern const uint8_t server_pk_start[] asm("_binary_prvtkey_pem_start");
 extern const uint8_t server_pk_end[]   asm("_binary_prvtkey_pem_end");
 
+// `server_cert_bundle_corrupt` is created by generating the cert bundle using `server_root.pem`
 extern const uint8_t server_cert_bundle_start[] asm("_binary_server_cert_bundle_start");
 extern const uint8_t server_cert_bundle_end[] asm("_binary_server_cert_bundle_end");
 
@@ -272,7 +274,7 @@ void client_task(void *pvParameters)
         goto exit;
     }
 
-    /* Test with default crt bundle that doesnt contain the ca crt */
+    /* Test with default crt bundle that does not contain the ca crt */
     ESP_LOGI(TAG, "Connecting to %s:%s...", SERVER_ADDRESS, SERVER_PORT);
     if ((ret = mbedtls_net_connect(&client.client_fd, SERVER_ADDRESS, SERVER_PORT, MBEDTLS_NET_PROTO_TCP)) != 0) {
         ESP_LOGE(TAG, "mbedtls_net_connect returned -%x", -ret);
@@ -300,7 +302,7 @@ void client_task(void *pvParameters)
     } else {
         ESP_LOGE(TAG, "Certificate verification failed!");
     }
-    TEST_ASSERT(res == ESP_CRT_VALIDATE_FAIL);
+    TEST_ASSERT_EQUAL(ESP_CRT_VALIDATE_FAIL, res);
 
     // Reset session before new connection
     mbedtls_ssl_close_notify(&client.ssl);
@@ -338,7 +340,7 @@ void client_task(void *pvParameters)
     } else {
         ESP_LOGE(TAG, "Certificate verification failed!");
     }
-    TEST_ASSERT(res == ESP_CRT_VALIDATE_OK);
+    TEST_ASSERT_EQUAL(ESP_CRT_VALIDATE_OK, res);
 
     // Reset session before new connection
     mbedtls_ssl_close_notify(&client.ssl);
@@ -406,7 +408,7 @@ TEST_CASE("custom certificate bundle - weak hash", "[mbedtls]")
 
     mbedtls_x509_crt_init( &crt );
     mbedtls_x509_crt_parse(&crt, bad_md_crt_pem_start, bad_md_crt_pem_end - bad_md_crt_pem_start);
-    TEST_ASSERT(mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL) == 0);
+    TEST_ASSERT_EQUAL(0, mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL));
 
     mbedtls_x509_crt_free(&crt);
 
@@ -426,62 +428,119 @@ TEST_CASE("custom certificate bundle - wrong signature", "[mbedtls]")
     /* esp32.com cert chain where 1 byte in the signature is changed */
     printf("Testing certificate with wrong signature\n");
     mbedtls_x509_crt_parse(&crt, wrong_sig_crt_pem_start, wrong_sig_crt_pem_end - wrong_sig_crt_pem_start);
-    TEST_ASSERT(mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL) != 0);
+    TEST_ASSERT_NOT_EQUAL(0, mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL));
     mbedtls_x509_crt_free(&crt);
 
     mbedtls_x509_crt_init( &crt );
     /* the correct esp32.com cert chain*/
     printf("Testing certificate with correct signature\n");
     mbedtls_x509_crt_parse(&crt, correct_sig_crt_pem_start, correct_sig_crt_pem_end - correct_sig_crt_pem_start);
-    TEST_ASSERT(mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL) == 0);
+    TEST_ASSERT_EQUAL(0, mbedtls_x509_crt_verify(&crt, NULL, NULL, NULL, &flags, esp_crt_verify_callback, NULL));
     mbedtls_x509_crt_free(&crt);
 
     esp_crt_bundle_detach(NULL);
 }
 
-TEST_CASE("custom certificate bundle init API - bound checking", "[mbedtls]")
+TEST_CASE("custom certificate bundle init API - bound checking - NULL certificate bundle", "[mbedtls]")
 {
+    esp_err_t esp_ret;
+
+    /* The API should fail when NULL is passed as the bundle */
+    esp_ret = esp_crt_bundle_set(NULL, 0);
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret);
+}
 
-    uint8_t test_bundle[256] = {0};
+TEST_CASE("custom certificate bundle init API - bound checking - Invalid size of certificate bundle", "[mbedtls]")
+{
+    uint8_t test_bundle[1024] = {0};
     esp_err_t esp_ret;
+
     /* The API should fail with bundle size given as 1 */
     esp_ret = esp_crt_bundle_set(test_bundle, 1);
-    TEST_ASSERT( esp_ret == ESP_ERR_INVALID_ARG);
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret);
+}
+
+TEST_CASE("custom certificate bundle init API - bound checking - Invalid first certificate offset", "[mbedtls]")
+{
+    uint8_t test_bundle[1024] = {0};
+    esp_err_t esp_ret;
+
+    /* Check that the esp_crt_bundle_set API will not accept
+     * the first offset to be invalid */
+
+    /* The first certificate must start after N uint32_t offset values,
+     * thus, it cannot start from the 0th position */
+    test_bundle[0] = 0;
+    esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret);
+
+    /* The first certificate must start after N uint32_t offset values, thus,
+     * the offset from where the it would start should be divisible by sizeof(uint32_t) */
+    test_bundle[0] = 1;
+    esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret);
+
+    /* Check that the esp_crt_bundle_set API will not accept a bundle
+     * which in which the first cert starts beyond end of bundle*/
+    uint8_t *dummy_test_bundle = test_bundle + sizeof(uint32_t);
+
+    esp_ret = esp_crt_bundle_set(dummy_test_bundle, sizeof(test_bundle));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret);
+}
+
+TEST_CASE("custom certificate bundle init API - bound checking - Certificates count overflow", "[mbedtls]")
+{
+    uint8_t test_bundle[1024] = {0};
+    esp_err_t esp_ret;
+
+    memset(test_bundle, 0, sizeof(test_bundle));
 
     /* Check that the esp_crt_bundle_set API will not accept a bundle
      * which has more no. of certs than configured in
      * CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS */
+    *((uint32_t*) test_bundle) = ((CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS + 1) * sizeof(uint32_t));
 
-    uint8_t rand;
-    esp_fill_random(&rand, 1);
-    test_bundle[0] = rand;
+    esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret);
 
-    /* Make sure that the number of certs will always be greater than
-     * CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS */
-    test_bundle[1] = rand + CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_MAX_CERTS;
+    esp_crt_bundle_detach(NULL);
+}
+
+TEST_CASE("custom certificate bundle init API - bound checking - Incorrect certificate offset", "[mbedtls]")
+{
+    uint8_t test_bundle[1024] = {0};
+    esp_err_t esp_ret;
+
+    memset(test_bundle, 0, sizeof(test_bundle));
+
+    /* Check that the esp_crt_bundle_set API will not accept a bundle where
+       all offsets are not consistent with certificate data */
+
+    /*
+    | offset 1 | offset 2 | Cert 1 name len | Cert 1 key len | Cert 1 name | Cert 1 key | Cert 2 name len | ..... |
+    | ----- offsets ----- |
+                          | ---------------------- Certificate 1 ---------------------- |
+                                                                                        | ---- Certificate 2 ---- |
+    */
+
+    *((uint32_t*) &test_bundle[0]) = (2 * sizeof(uint32_t));
+    *((uint16_t*) &test_bundle[8]) = 2;     // Cert 1 name len
+    *((uint16_t*) &test_bundle[10]) = 4;    // Cert 1 key len
+
+    /* Correct offset of certificate 2 should be
+        = 2 * sizeof(uint32_t) (Offsets of 2 certs) + 2 * sizeof(uint16_t) (Cert name and len) + 2 (Cert 1 name len) + 4 (Cert 1 key len);
+        = 18
+    */
+    *((uint32_t*) &test_bundle[4]) = 16;    // Incorrect certificate 2 offset
 
     esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle));
-    TEST_ASSERT( esp_ret == ESP_ERR_INVALID_ARG);
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret);
 
-    /* The API should fail with bundle_size < BUNDLE_HEADER_OFFSET (2) + CRT_HEADER_OFFSET (4) */
-    test_bundle[0] = 0;
-    test_bundle[1] = 1; /* set num_certs = 1 */
-    esp_ret = esp_crt_bundle_set(test_bundle, 5);
-    TEST_ASSERT(esp_ret == ESP_ERR_INVALID_ARG);
-
-    /* Cert number is greater than actual certs present, The API should fail */
-    /* Actual No. of certs present in bundle = 1, setting num_certs to 5 */
-    test_bundle[1] = 5; /* num_certs */
-    test_bundle[3] = 5; /* cert_1_name_len */
-    test_bundle[5] = 10; /* cert_1_pub_key_len */
-    /* Actual bundle size becomes BUNDLE_HEADER_OFFSET (2) + CRT_HEADER_OFFSET (4) + cert_1_name_len(5) + cert_1_pub_key_len(10)
-     * i.e. 21 bytes */
-    esp_ret = esp_crt_bundle_set(test_bundle, 21);
-    TEST_ASSERT(esp_ret == ESP_ERR_INVALID_ARG);
-
-    /* The API should fail if bundle_size < BUNDLE_HEADER_OFFSET (2) + CRT_HEADER_OFFSET (4) + cert_1_name_len(5) + cert_1_pub_key_len(10) */
-    esp_ret = esp_crt_bundle_set(test_bundle, 20);
-    TEST_ASSERT(esp_ret == ESP_ERR_INVALID_ARG);
+    /* Check that the esp_crt_bundle_set API will not accept a bundle where
+       all offsets are not consistency with certificate data and the certificate
+       offsets exceeds the bundle size */
+    *((uint32_t*) &test_bundle[4]) = sizeof(test_bundle) + 1;    // Offset exceeds the test_bundle size
 
-    esp_crt_bundle_detach(NULL);
+    esp_ret = esp_crt_bundle_set(test_bundle, sizeof(test_bundle));
+    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ret);
 }
diff --git a/components/mbedtls/test_apps/main/test_mbedtls_sha.c b/components/mbedtls/test_apps/main/test_mbedtls_sha.c
index 003b35db8b5..5b6d71e2f3b 100644
--- a/components/mbedtls/test_apps/main/test_mbedtls_sha.c
+++ b/components/mbedtls/test_apps/main/test_mbedtls_sha.c
@@ -563,7 +563,8 @@ TEST_CASE("mbedtls SHA256 PSRAM DMA large buffer", "[hw_crypto]")
 
 #endif //CONFIG_SPIRAM_USE_MALLOC
 
-#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
+#if CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK && !CONFIG_IDF_TARGET_ESP32H2
+// Not enough rtc memory for test on H2
 
 TEST_CASE("mbedtls SHA stack in RTC RAM", "[mbedtls]")
 {
@@ -587,7 +588,7 @@ TEST_CASE("mbedtls SHA stack in RTC RAM", "[mbedtls]")
 
 #endif //CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
 
-#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC
+#if CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM && CONFIG_SPIRAM_USE_MALLOC
 
 TEST_CASE("mbedtls SHA stack in PSRAM", "[mbedtls]")
 {
@@ -609,4 +610,4 @@ TEST_CASE("mbedtls SHA stack in PSRAM", "[mbedtls]")
     vSemaphoreDelete(done_sem);
 }
 
-#endif //CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY && CONFIG_SPIRAM_USE_MALLOC
+#endif //CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM && CONFIG_SPIRAM_USE_MALLOC
diff --git a/components/mbedtls/test_apps/pytest_mbedtls_ut.py b/components/mbedtls/test_apps/pytest_mbedtls_ut.py
index f7b1437f5a7..3614c8dcaa2 100644
--- a/components/mbedtls/test_apps/pytest_mbedtls_ut.py
+++ b/components/mbedtls/test_apps/pytest_mbedtls_ut.py
@@ -27,6 +27,7 @@ def test_mbedtls_esp32_compiler_perf_opt(dut: Dut) -> None:
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.esp32c3
+@pytest.mark.esp32c5
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
@@ -43,6 +44,7 @@ def test_mbedtls_aes_no_hw(dut: Dut) -> None:
 @pytest.mark.esp32s2
 @pytest.mark.esp32s3
 @pytest.mark.esp32c5
+@pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
diff --git a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext
index ad3452cf7b8..cd0e64116c8 100644
--- a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext
+++ b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext
@@ -1,4 +1,4 @@
 CONFIG_SPIRAM=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
diff --git a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext_esp32p4_200m b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext_esp32p4_200m
index 1c29e19bb93..6ed71c76e36 100644
--- a/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext_esp32p4_200m
+++ b/components/mbedtls/test_apps/sdkconfig.ci.psram_all_ext_esp32p4_200m
@@ -1,7 +1,7 @@
 CONFIG_IDF_TARGET="esp32p4"
 CONFIG_SPIRAM=y
 CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
 
 CONFIG_IDF_EXPERIMENTAL_FEATURES=y
diff --git a/components/newlib/CMakeLists.txt b/components/newlib/CMakeLists.txt
index 0d05270881d..c0af7ac692e 100644
--- a/components/newlib/CMakeLists.txt
+++ b/components/newlib/CMakeLists.txt
@@ -1,4 +1,5 @@
 idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(non_os_build NON_OS_BUILD)
 
 if(${target} STREQUAL "linux")
     return() # This component is not supported by the POSIX/Linux simulator
@@ -6,7 +7,7 @@ endif()
 
 set(include_dirs "platform_include")
 
-if(BOOTLOADER_BUILD)
+if(non_os_build)
     # Bootloader builds need the platform_include directory (for assert.h), but nothing else
     idf_component_register(INCLUDE_DIRS platform_include)
     return()
diff --git a/components/newlib/platform_include/esp_newlib.h b/components/newlib/platform_include/esp_newlib.h
index fe5e4cf343f..23da9f2d6b3 100644
--- a/components/newlib/platform_include/esp_newlib.h
+++ b/components/newlib/platform_include/esp_newlib.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/components/newlib/platform_include/pthread.h b/components/newlib/platform_include/pthread.h
index d814db9859a..9b591202c61 100644
--- a/components/newlib/platform_include/pthread.h
+++ b/components/newlib/platform_include/pthread.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +20,18 @@ int pthread_condattr_getclock(const pthread_condattr_t * attr, clockid_t * clock
 
 int pthread_condattr_setclock(pthread_condattr_t *attr, clockid_t clock_id);
 
+/* Dynamic Thread Scheduling Parameters Access */
+int pthread_getschedparam(pthread_t thread, int *policy, struct sched_param *param);
+
+int pthread_setschedparam(pthread_t thread, int policy, const struct sched_param *param);
+
+/* Set Scheduling Priority of a Thread */
+int pthread_setschedprio(pthread_t thread, int prio);
+
+int sched_get_priority_min(int policy);
+
+int sched_get_priority_max(int policy);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/newlib/test_apps/newlib/pytest_newlib.py b/components/newlib/test_apps/newlib/pytest_newlib.py
index 78c01517d50..8b2c5cc4505 100644
--- a/components/newlib/test_apps/newlib/pytest_newlib.py
+++ b/components/newlib/test_apps/newlib/pytest_newlib.py
@@ -1,35 +1,9 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-import subprocess
-from os import path
-
 import pytest
-import yaml
 from pytest_embedded import Dut
 
 
-def validate_sbom(dut: Dut) -> None:
-    dirname = path.dirname(path.abspath(__file__))
-    sbom_file = path.join(path.dirname(path.dirname(dirname)), 'sbom.yml')
-    gcc_input_file = path.join(dirname, 'test_sbom', 'newlib_version.c')
-    gcc = 'riscv32-esp-elf-gcc'
-    if dut.target in dut.XTENSA_TARGETS:
-        gcc = f'xtensa-{dut.target}-elf-gcc'
-    gcc_process = subprocess.run(f'{gcc} -E {gcc_input_file}',
-                                 shell=True,
-                                 stdout=subprocess.PIPE,
-                                 stderr=subprocess.PIPE,
-                                 text=True,
-                                 check=True)
-    output_lines = gcc_process.stdout.splitlines()
-    assert output_lines, 'Can not get newlib version'
-    toolchain_newlib_version = output_lines[-1].replace(' ', '.')
-    with open(sbom_file, 'r', encoding='utf-8') as yaml_file:
-        sbom_newlib_version = yaml.safe_load(yaml_file).get('version')
-        assert sbom_newlib_version, 'Can not get newlib version from sbom.yml'
-        assert toolchain_newlib_version == sbom_newlib_version, 'toolchain_newlib_version != sbom_newlib_version'
-
-
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
@@ -44,5 +18,4 @@ def validate_sbom(dut: Dut) -> None:
     indirect=True
 )
 def test_newlib(dut: Dut) -> None:
-    validate_sbom(dut)
     dut.run_all_single_board_cases()
diff --git a/components/nvs_flash/nvs_partition_tool/nvs_check.py b/components/nvs_flash/nvs_partition_tool/nvs_check.py
index b6a4da3abaf..ca2cd4680a4 100644
--- a/components/nvs_flash/nvs_partition_tool/nvs_check.py
+++ b/components/nvs_flash/nvs_partition_tool/nvs_check.py
@@ -22,6 +22,22 @@
 
 
 def check_partition_size(nvs_partition: NVS_Partition, nvs_log: NVS_Logger) -> bool:
+    """ Checks if the partition is large enough and has enough pages
+    """
+    if len(nvs_partition.raw_data) / 0x1000 < 3:
+        nvs_log.info(
+            nvs_log.yellow(
+                'NVS Partition size must be at least 0x3000 (4kiB * 3 pages == 12kiB)!'
+            )
+        )
+        return False
+    if len(nvs_partition.raw_data) % 0x1000 != 0:
+        nvs_log.info(
+            nvs_log.yellow(
+                'NVS Partition size must be a multiple of 0x1000 (4kiB)!'
+            )
+        )
+        return False
     if len(nvs_partition.pages) < 3:
         nvs_log.info(
             nvs_log.yellow(
@@ -83,16 +99,22 @@ def check_page_crc(nvs_page: NVS_Page, nvs_log: NVS_Logger) -> bool:
         return False
 
 
-def identify_entry_duplicates(entry: NVS_Entry, seen_written_entires: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]:
+def identify_entry_duplicates(entry: NVS_Entry, entry_dict: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]:
+    """Identifies and logs written entries
+
+    Part 1 of duplicate entry check mechanism
+    """
     if entry.state == 'Written':
-        if entry.key in seen_written_entires:
-            seen_written_entires[entry.key].append(entry)
+        if entry.key in entry_dict:
+            entry_dict[entry.key].append(entry)
         else:
-            seen_written_entires[entry.key] = [entry]
-    return seen_written_entires
+            entry_dict[entry.key] = [entry]
+    return entry_dict
 
 
 def check_page_entries(nvs_page: NVS_Page, nvs_log: NVS_Logger) -> Dict[str, List[NVS_Entry]]:
+    """Checks entries in the given page (entry state, children CRC32, entry type, span and gathers blobs and namespaces)
+    """
     seen_written_entires: Dict[str, List[NVS_Entry]] = {}
 
     for entry in nvs_page.entries:
@@ -203,6 +225,11 @@ def check_page_entries(nvs_page: NVS_Page, nvs_log: NVS_Logger) -> Dict[str, Lis
 
 
 def filter_namespaces_fake_duplicates(duplicate_entries_dict: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]:
+    """Takes a dictionary of entries (as written) and returns a new dictionary with "fake" duplicates,
+    where entries which have the same key but under different namespaces are filtered out
+
+    Use `filter_entry_duplicates()` to properly filter out all duplicates
+    """
     new_duplicate_entries_dict: Dict[str, List[NVS_Entry]] = {}
     for key, duplicate_entries in duplicate_entries_dict.items():
         seen_entries: List[NVS_Entry] = []
@@ -237,6 +264,11 @@ def filter_namespaces_fake_duplicates(duplicate_entries_dict: Dict[str, List[NVS
 
 
 def filter_blob_related_duplicates(duplicate_entries_dict: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]:
+    """Takes a dictionary of entries (as written) and returns a new dictionary with "fake" duplicates,
+    where entries related to blob index and blob data under the same namespace are filtered out
+
+    Use `filter_entry_duplicates()` to properly filter out all duplicates
+    """
     new_duplicate_entries_dict: Dict[str, List[NVS_Entry]] = {}
     for key, duplicate_entries in duplicate_entries_dict.items():
         seen_blob_index: List[NVS_Entry] = []
@@ -298,9 +330,19 @@ def filter_blob_related_duplicates(duplicate_entries_dict: Dict[str, List[NVS_En
     return new_duplicate_entries_dict
 
 
-def filter_entry_duplicates(seen_written_entires: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]:
-    duplicate_entries_list = {key: v for key, v in seen_written_entires.items() if len(v) > 1}
+def filter_entry_duplicates(entries: Dict[str, List[NVS_Entry]]) -> Dict[str, List[NVS_Entry]]:
+    """Takes a dictionary of (seen written) entries and outputs a new dictionary with "fake" duplicates filtered out, keeping only real duplicates in
+
+    (i.e. duplicate keys under different namespaces and blob index and blob data having the same key under the same namespace are allowed
+    and should be filtered out)
+
+    Part 2 of duplicate entry check mechanism
+    """
+    # Only keep seen written entries which have been observerd multiple times (duplicates)
+    duplicate_entries_list = {key: v for key, v in entries.items() if len(v) > 1}
+    # Filter out "fake" duplicates 1 (duplicate keys under different namespaces are allowed)
     duplicate_entries_list_1 = filter_namespaces_fake_duplicates(duplicate_entries_list)
+    # Filter out "fake" duplicates 2 (blob index and blob data are allowed to have the same key even in the same namespace)
     duplicate_entries_list_2 = filter_blob_related_duplicates(duplicate_entries_list_1)
     return duplicate_entries_list_2
 
@@ -341,6 +383,8 @@ def print_entry_duplicates(duplicate_entries_list: Dict[str, List[NVS_Entry]], n
 
 
 def assemble_blobs(nvs_log: NVS_Logger) -> None:
+    """Assembles blob data from blob chunks
+    """
     for chunk in blob_chunks:
         # chunk: NVS_Entry
         parent = blobs.get(
@@ -361,6 +405,8 @@ def assemble_blobs(nvs_log: NVS_Logger) -> None:
 
 
 def check_blob_data(nvs_log: NVS_Logger) -> None:
+    """Checks blob data for missing chunks or data
+    """
     for blob_key in blobs:
         blob_index = blobs[blob_key][0]
         blob_chunks = blobs[blob_key][1:]
@@ -395,6 +441,8 @@ def check_blobs(nvs_log: NVS_Logger) -> None:
 
 
 def check_namespaces(nvs_log: NVS_Logger) -> None:
+    """Checks namespaces (entries using undefined namespace indexes, unused namespaces)
+    """
     # Undefined namespace index check
     for used_ns in used_namespaces:
         key = found_namespaces.pop(used_ns, None)
@@ -415,6 +463,9 @@ def check_namespaces(nvs_log: NVS_Logger) -> None:
 
 
 def reset_global_variables() -> None:
+    """Global variables need to be cleared out before calling `integrity_check()` multiple times from a script
+    (e.g. when running tests) to avoid incorrect output
+    """
     global used_namespaces, found_namespaces, blobs, blob_chunks
     used_namespaces = {}
     found_namespaces = {}
@@ -423,6 +474,8 @@ def reset_global_variables() -> None:
 
 
 def integrity_check(nvs_partition: NVS_Partition, nvs_log: NVS_Logger) -> None:
+    """Function for multi-stage integrity check of a NVS partition
+    """
     # Partition size check
     check_partition_size(nvs_partition, nvs_log)
 
@@ -431,18 +484,19 @@ def integrity_check(nvs_partition: NVS_Partition, nvs_log: NVS_Logger) -> None:
 
     seen_written_entires_all: Dict[str, List[NVS_Entry]] = {}
 
+    # Loop through all pages in the partition
     for page in nvs_partition.pages:
         # page: NVS_Page
 
-        # Print page header
+        # Print a page header
         if page.header['status'] == 'Empty':
-            # Check if page is truly empty
+            # Check if a page is truly empty
             check_empty_page_content(page, nvs_log)
         else:
-            # Check page header CRC32
+            # Check a page header CRC32
             check_page_crc(page, nvs_log)
 
-        # Check all entries
+        # Check all entries in a page
         seen_written_entires = check_page_entries(page, nvs_log)
 
         # Collect all seen written entries
diff --git a/components/nvs_flash/nvs_partition_tool/nvs_parser.py b/components/nvs_flash/nvs_partition_tool/nvs_parser.py
index 29b610b33b2..a4bb3dae570 100644
--- a/components/nvs_flash/nvs_partition_tool/nvs_parser.py
+++ b/components/nvs_flash/nvs_partition_tool/nvs_parser.py
@@ -64,8 +64,9 @@ def __init__(self, name: str, raw_data: bytearray):
                 f'Given partition data is not aligned to page size ({len(raw_data)} % {nvs_const.page_size} = {len(raw_data)%nvs_const.page_size})'
             )
 
-        # Divide partition into pages
         self.name = name
+        self.raw_data = raw_data
+        # Divide partition into pages
         self.pages = []
         for i in range(0, len(raw_data), nvs_const.page_size):
             self.pages.append(NVS_Page(raw_data[i: i + nvs_const.page_size], i))
diff --git a/components/nvs_flash/nvs_partition_tool/test_nvs_gen_check.py b/components/nvs_flash/nvs_partition_tool/test_nvs_gen_check.py
index 380943b481d..5463abef606 100644
--- a/components/nvs_flash/nvs_partition_tool/test_nvs_gen_check.py
+++ b/components/nvs_flash/nvs_partition_tool/test_nvs_gen_check.py
@@ -201,13 +201,20 @@ def setup_bad_mixed_same_key_different_page(nvs_obj: NVS) -> None:
         data_type = prim_types[i % len(prim_types)]
         nvs_partition_gen.write_entry(nvs_obj, f'test_{i}', 'data', data_type, str(i))  # Conflicting keys under "abcd" namespace - 6 duplicates
     nvs_partition_gen.write_entry(nvs_obj, 'lorem_string_key', 'data', 'string', 'abc')  # Conflicting key for string - 7th duplicate
-    nvs_partition_gen.write_entry(nvs_obj, 'storage', 'namespace', '', '')  # Conflicting namespace - 8th duplicate
+
+    # Create new duplicates of storage namespace with an unsafe version of write_namespace function
+    nvs_obj.write_namespace_unsafe('storage')  # Conflicting namespace - 8th duplicate (the function is only for testing)
+
     nvs_partition_gen.write_entry(nvs_obj, 'storage2', 'namespace', '', '')  # New namespace, ignored
     nvs_partition_gen.write_entry(nvs_obj, 'lorem_string_key', 'data', 'string', 'abc')  # Should be ignored as is under different "storage2" namespace
     nvs_partition_gen.write_entry(nvs_obj, 'lorem_string', 'data', 'string', 'abc')  # 3 conflicting keys under "storage2" namespace - 9th duplicate
     nvs_partition_gen.write_entry(nvs_obj, 'lorem_string', 'data', 'string', 'def')
     nvs_partition_gen.write_entry(nvs_obj, 'lorem_string', 'data', 'string', '123')
 
+    # This no longer (nvs generator version >= 0.1.5) creates a duplicate namespace entry, only changes
+    # the current used namespace index
+    nvs_partition_gen.write_entry(nvs_obj, 'storage', 'namespace', '', '')
+
 
 def setup_bad_same_key_primitive(nvs_obj: NVS) -> None:
     nvs_partition_gen.write_entry(nvs_obj, 'storage', 'namespace', '', '')
diff --git a/components/openthread/CMakeLists.txt b/components/openthread/CMakeLists.txt
index 51b66bb4489..66119f65aa4 100644
--- a/components/openthread/CMakeLists.txt
+++ b/components/openthread/CMakeLists.txt
@@ -15,7 +15,6 @@ if(CONFIG_OPENTHREAD_ENABLED)
 
     set(private_include_dirs
         "openthread/examples/platforms"
-        "openthread/include/openthread"
         "openthread/src"
         "openthread/src/core"
         "openthread/src/lib"
@@ -140,6 +139,19 @@ if(CONFIG_OPENTHREAD_ENABLED)
         list(APPEND exclude_srcs
             "src/port/esp_openthread_radio.c"
             "src/port/esp_openthread_sleep.c")
+    elseif(CONFIG_OPENTHREAD_RADIO_154_NONE)
+        list(APPEND exclude_srcs
+            "src/port/esp_openthread_radio_spinel.cpp"
+            "src/port/esp_spi_spinel_interface.cpp"
+            "src/port/esp_uart_spinel_interface.cpp"
+            "src/port/esp_openthread_radio.c"
+            "src/port/esp_openthread_sleep.c"
+            )
+    endif()
+
+    if(NOT CONFIG_OPENTHREAD_RADIO_TREL)
+        list(APPEND exclude_srcs
+            "src/port/esp_openthread_trel.c")
     endif()
 
     if(CONFIG_OPENTHREAD_BORDER_ROUTER)
@@ -259,6 +271,10 @@ idf_component_register(SRC_DIRS "${src_dirs}"
                        PRIV_REQUIRES console esp_event esp_partition esp_timer
                                      ieee802154 mbedtls nvs_flash)
 
+if(CONFIG_OPENTHREAD_RADIO_TREL)
+    idf_component_optional_requires(PRIVATE espressif__mdns)
+endif()
+
 if(CONFIG_OPENTHREAD_ENABLED OR CONFIG_OPENTHREAD_SPINEL_ONLY)
     if(CONFIG_OPENTHREAD_RADIO)
         set(CONFIG_FILE_TYPE "radio")
diff --git a/components/openthread/Kconfig b/components/openthread/Kconfig
index 160084fbcb7..a739f701635 100644
--- a/components/openthread/Kconfig
+++ b/components/openthread/Kconfig
@@ -101,7 +101,7 @@ menu "OpenThread"
         default 5 if OPENTHREAD_LOG_LEVEL_DEBG
 
     choice OPENTHREAD_RADIO_TYPE
-        prompt "Config the Thread radio type"
+        prompt "Config the Thread radio type with 15.4 link"
         depends on OPENTHREAD_ENABLED
         default OPENTHREAD_RADIO_NATIVE if SOC_IEEE802154_SUPPORTED
         default OPENTHREAD_RADIO_SPINEL_UART
@@ -124,8 +124,26 @@ menu "OpenThread"
             help
                 Select this to connect to a Radio Co-Processor via SPI.
 
+        config OPENTHREAD_RADIO_154_NONE
+            bool "Disable the Thread radio based on 15.4 link"
+            help
+                Select this to disable the Thread radio based on 15.4 link.
     endchoice
 
+    config OPENTHREAD_RADIO_TREL
+        bool "Enable Thread Radio Encapsulation Link (TREL)"
+        depends on EXAMPLE_CONNECT_WIFI || EXAMPLE_CONNECT_ETHERNET
+        default n
+        help
+            Select this option to enable Thread Radio Encapsulation Link.
+
+    config OPENTHREAD_TREL_PORT
+        int "The port of openthread trel service"
+        depends on OPENTHREAD_RADIO_TREL
+        default 12390
+        help
+            Configure the port number of TREL service.
+
     choice OPENTHREAD_DEVICE_TYPE
         prompt "Config the Thread device type"
         depends on OPENTHREAD_ENABLED
@@ -260,12 +278,20 @@ menu "OpenThread"
         help
             Select this option to enable border router features in OpenThread.
 
-    config OPENTHREAD_PLATFORM_MSGPOOL_MANAGEMENT
-        bool 'Allocate message pool buffer from PSRAM'
+    menu "Thread Memory Allocation Config"
         depends on OPENTHREAD_ENABLED && (SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC)
-        default n
-        help
-            If enabled, the message pool is managed by platform defined logic.
+        config OPENTHREAD_MEM_ALLOC_EXTERNAL
+            bool 'Allocate memory from PSRAM'
+            default y
+            help
+                Select this option to allocate buffer from PSRAM for Thread
+
+        config OPENTHREAD_PLATFORM_MSGPOOL_MANAGEMENT
+            bool 'Allocate message pool buffer from PSRAM'
+            default n
+            help
+                If enabled, the message pool is managed by platform defined logic.
+    endmenu
 
     config OPENTHREAD_NUM_MESSAGE_BUFFERS
         int "The number of openthread message buffers"
diff --git a/components/openthread/include/esp_openthread_border_router.h b/components/openthread/include/esp_openthread_border_router.h
index de4b8ee6048..8960fc861d5 100644
--- a/components/openthread/include/esp_openthread_border_router.h
+++ b/components/openthread/include/esp_openthread_border_router.h
@@ -66,6 +66,16 @@ esp_netif_t *esp_openthread_get_backbone_netif(void);
  */
 void esp_openthread_register_rcp_failure_handler(esp_openthread_rcp_failure_handler handler);
 
+/**
+ * @brief   Registers the callback for spinel compatibility error.
+ *
+ * @note This function must be called before esp_openthread_init.
+ *
+ * @param[in]  callback   The callback.
+ *
+ */
+void esp_openthread_set_compatibility_error_callback(esp_openthread_compatibility_error_callback callback);
+
 /**
  * @brief   Deinitializes the connection to RCP.
  *
diff --git a/components/openthread/include/esp_openthread_types.h b/components/openthread/include/esp_openthread_types.h
index 03095940194..ce1d258a3dc 100644
--- a/components/openthread/include/esp_openthread_types.h
+++ b/components/openthread/include/esp_openthread_types.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -46,6 +46,7 @@ typedef enum {
     OPENTHREAD_EVENT_SET_DNS_SERVER,            /*!< OpenThread stack set DNS server >*/
     OPENTHREAD_EVENT_PUBLISH_MESHCOP_E,         /*!< OpenThread stack start to publish meshcop-e service >*/
     OPENTHREAD_EVENT_REMOVE_MESHCOP_E,          /*!< OpenThread stack start to remove  meshcop-e service >*/
+    OPENTHREAD_EVENT_DATASET_CHANGED,           /*!< OpenThread dataset changed >*/
 } esp_openthread_event_t;
 
 /**
@@ -63,6 +64,24 @@ typedef struct {
     otDeviceRole current_role;  /*!< Current Thread role */
 } esp_openthread_role_changed_event_t;
 
+/**
+ * @brief OpenThread dataset type
+ *
+ */
+typedef enum {
+    OPENTHREAD_ACTIVE_DATASET,  /*!< Active dataset */
+    OPENTHREAD_PENDING_DATASET, /*!< Pending dataset */
+} esp_openthread_dataset_type_t;
+
+/**
+ * @brief OpenThread dataset changed event data
+ *
+ */
+typedef struct {
+    esp_openthread_dataset_type_t type; /*!< Dataset type */
+    otOperationalDataset new_dataset;   /*!< New dataset */
+} esp_openthread_dataset_changed_event_t;
+
 /**
  * This structure represents a context for a select() based mainloop.
  *
@@ -117,6 +136,7 @@ typedef enum {
     RADIO_MODE_NATIVE = 0x0,   /*!< Use the native 15.4 radio */
     RADIO_MODE_UART_RCP,       /*!< UART connection to a 15.4 capable radio co-processor (RCP) */
     RADIO_MODE_SPI_RCP,        /*!< SPI connection to a 15.4 capable radio co-processor (RCP) */
+    RADIO_MODE_TREL,           /*!< Use the Thread Radio Encapsulation Link (TREL) */
     RADIO_MODE_MAX,            /*!< Using for parameter check */
 } esp_openthread_radio_mode_t;
 
@@ -180,6 +200,8 @@ typedef struct {
 
 typedef void (*esp_openthread_rcp_failure_handler)(void);
 
+typedef void (*esp_openthread_compatibility_error_callback)(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/openthread/include/esp_radio_spinel.h b/components/openthread/include/esp_radio_spinel.h
index 24c5f1a6299..710d61d6465 100644
--- a/components/openthread/include/esp_radio_spinel.h
+++ b/components/openthread/include/esp_radio_spinel.h
@@ -46,6 +46,7 @@ typedef struct {
 typedef void (*esp_radio_spinel_rcp_failure_handler)(void);                                                                     /* The handler for rcp failure.*/
 typedef esp_err_t (*esp_radio_spinel_uart_init_handler)(const esp_radio_spinel_uart_config_t *uart_config_t, int *uart_fd);     /* The handler for UART initialization.*/
 typedef esp_err_t (*esp_radio_spinel_uart_deinit_handler)(const esp_radio_spinel_uart_config_t *uart_config_t, int *uart_fd);   /* The handler for UART deinitialization.*/
+typedef void (*esp_radio_spinel_compatibility_error_callback)(void);
 
 typedef struct
 {
@@ -391,6 +392,16 @@ esp_err_t esp_radio_spinel_rcp_deinit(esp_radio_spinel_idx_t idx);
  */
 esp_err_t esp_radio_spinel_rcp_version_get(char *running_rcp_version, esp_radio_spinel_idx_t idx);
 
+/**
+ * @brief   Registers the callback for spinel compatibility error.
+ *
+ * @note This function must be called before esp_radio_spinel_init.
+ *
+ * @param[in]  callback   The callback.
+ *
+ */
+void esp_radio_spinel_set_compatibility_error_callback(esp_radio_spinel_compatibility_error_callback callback);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/openthread/include/esp_radio_spinel_platform.h b/components/openthread/include/esp_radio_spinel_platform.h
new file mode 100644
index 00000000000..d6ce8717161
--- /dev/null
+++ b/components/openthread/include/esp_radio_spinel_platform.h
@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief  Get frame counter.
+ *
+ * @param[in]  idx   The index of 802.15.4 related protocol stack.
+ *
+ * @return
+ *      - The frame counter
+ *
+ */
+uint32_t esp_radio_spinel_extern_get_frame_counter(esp_radio_spinel_idx_t idx);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/openthread/lib b/components/openthread/lib
index 56af58057c2..55f18e4cc6a 160000
--- a/components/openthread/lib
+++ b/components/openthread/lib
@@ -1 +1 @@
-Subproject commit 56af58057c259405aa90c478e294f6216cc2f6db
+Subproject commit 55f18e4cc6a249974247fd408aad79b1049d4b31
diff --git a/components/openthread/openthread b/components/openthread/openthread
index f32c18bc084..005c5cefc22 160000
--- a/components/openthread/openthread
+++ b/components/openthread/openthread
@@ -1 +1 @@
-Subproject commit f32c18bc0840f400182456e58ae3900fc2fb4af7
+Subproject commit 005c5cefc22aaf0396e4327ee7f2e0ad32a7733b
diff --git a/components/openthread/private_include/esp_openthread_common.hpp b/components/openthread/private_include/esp_openthread_common.hpp
new file mode 100644
index 00000000000..c4dbf749ee8
--- /dev/null
+++ b/components/openthread/private_include/esp_openthread_common.hpp
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_heap_caps.h"
+#include <utility>
+#include "common/new.hpp"
+
+template <typename T, typename... Args>
+inline T *New(uint32_t alloc_caps, Args &&...args)
+{
+    void *p = heap_caps_calloc(1, sizeof(T), alloc_caps);
+    if (p != nullptr) {
+        return new (p) T(std::forward<Args>(args)...);
+    }
+    return nullptr;
+}
diff --git a/components/openthread/private_include/esp_openthread_platform.h b/components/openthread/private_include/esp_openthread_platform.h
index 6919e914be2..3999322a8d1 100644
--- a/components/openthread/private_include/esp_openthread_platform.h
+++ b/components/openthread/private_include/esp_openthread_platform.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -84,7 +84,7 @@ void esp_openthread_platform_workflow_unregister(const char *name);
  * @brief   Initializes the platform-specific support for the OpenThread stack.
  *
  * @note This function is not called by and will not call the OpenThread library.
- *       The user needs to call otInstanceInitSingle to intialize the OpenThread
+ *       The user needs to call otInstanceInitSingle to initialize the OpenThread
  *       stack after calling this function.
  *
  * @param[in]  init_config      The initialization configuration.
@@ -146,6 +146,15 @@ esp_err_t esp_openthread_platform_process(otInstance *instance, const esp_openth
  *
  */
 void esp_openthread_set_storage_name(const char *name);
+
+/**
+ * @brief   Gets the caps of memory allocation.
+ *
+ * @return
+ *      - The caps of the memory.
+ */
+uint32_t esp_openthread_get_alloc_caps(void);
+
 #ifdef __cplusplus
 } // end of extern "C"
 #endif
diff --git a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h
index aa8882f2341..42ea9d9546c 100644
--- a/components/openthread/private_include/openthread-core-esp32x-ftd-config.h
+++ b/components/openthread/private_include/openthread-core-esp32x-ftd-config.h
@@ -203,28 +203,40 @@
 #define OPENTHREAD_CONFIG_DNSSD_SERVER_ENABLE 1
 #endif
 
+/**
+ * @def OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE
+ *
+ * Define to 1 to enable Backbone Router support.
+ *
+ */
+#ifndef OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE
+#define OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE 1
+#endif
+
+#endif // CONFIG_OPENTHREAD_BORDER_ROUTER
+
 /**
  * @def OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE
  *
  * Set to 1 to enable support for Thread Radio Encapsulation Link (TREL).
  *
  */
-#ifndef OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE
-#define OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE 0
-#endif
+#if CONFIG_OPENTHREAD_RADIO_TREL
+#define OPENTHREAD_CONFIG_RADIO_LINK_TREL_ENABLE 1
+#endif // CONFIG_OPENTHREAD_RADIO_TREL
 
 /**
- * @def OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE
+ * @def OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE
  *
- * Define to 1 to enable Backbone Router support.
+ * Set to 1 to enable support for IEEE802.15.4 radio link.
  *
  */
-#ifndef OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE
-#define OPENTHREAD_CONFIG_BACKBONE_ROUTER_ENABLE 1
+#if !CONFIG_OPENTHREAD_RADIO_154_NONE
+#define OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE 1
+#else
+#define OPENTHREAD_CONFIG_RADIO_LINK_IEEE_802_15_4_ENABLE 0
 #endif
 
-#endif // CONFIG_OPENTHREAD_BORDER_ROUTER
-
 #if !CONFIG_OPENTHREAD_RADIO_NATIVE
 /**
  * @def OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT
@@ -249,6 +261,16 @@
 #define OPENTHREAD_POSIX_CONFIG_RCP_TIME_SYNC_INTERVAL (60 * 1000 * 1000)
 #endif
 
+/**
+ * @def OPENTHREAD_SPINEL_CONFIG_COMPATIBILITY_ERROR_CALLBACK_ENABLE
+ *
+ * Enables compatibility error callback in Spinel
+ */
+#ifndef OPENTHREAD_SPINEL_CONFIG_COMPATIBILITY_ERROR_CALLBACK_ENABLE
+#define OPENTHREAD_SPINEL_CONFIG_COMPATIBILITY_ERROR_CALLBACK_ENABLE 1
+#endif
+
+
 #endif
 
 /**
diff --git a/components/openthread/private_include/openthread-core-esp32x-mtd-config.h b/components/openthread/private_include/openthread-core-esp32x-mtd-config.h
index f21c9ce01ea..dd247037d74 100644
--- a/components/openthread/private_include/openthread-core-esp32x-mtd-config.h
+++ b/components/openthread/private_include/openthread-core-esp32x-mtd-config.h
@@ -73,6 +73,24 @@
  */
 #define OPENTHREAD_CONFIG_NUM_MESSAGE_BUFFERS CONFIG_OPENTHREAD_NUM_MESSAGE_BUFFERS
 
+/**
+ * @def OPENTHREAD_CONFIG_COAP_API_ENABLE
+ *
+ * Define to 1 to enable the CoAP API.
+ *
+ */
+#define OPENTHREAD_CONFIG_COAP_API_ENABLE 1
+
+/**
+ * @def OPENTHREAD_CONFIG_PLATFORM_NETIF_ENABLE
+ *
+ * Define to 1 to enable platform NETIF support.
+ *
+ */
+#ifndef OPENTHREAD_CONFIG_PLATFORM_NETIF_ENABLE
+#define OPENTHREAD_CONFIG_PLATFORM_NETIF_ENABLE 1
+#endif
+
 /**
  * @def OPENTHREAD_CONFIG_HEAP_EXTERNAL_ENABLE
  *
diff --git a/components/openthread/private_include/openthread-core-esp32x-spinel-config.h b/components/openthread/private_include/openthread-core-esp32x-spinel-config.h
index 3c9def78404..0b257baebae 100644
--- a/components/openthread/private_include/openthread-core-esp32x-spinel-config.h
+++ b/components/openthread/private_include/openthread-core-esp32x-spinel-config.h
@@ -41,7 +41,6 @@
  *
  */
 #ifndef OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT
-// TZ-567: Set OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT to 3 after adding rcp failure notification mechanism
 #define OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT 3
 #endif
 
@@ -77,3 +76,23 @@
 #ifndef OPENTHREAD_CONFIG_MAC_MAX_CSMA_BACKOFFS_DIRECT
 #define OPENTHREAD_CONFIG_MAC_MAX_CSMA_BACKOFFS_DIRECT CONFIG_OPENTHREAD_MAC_MAX_CSMA_BACKOFFS_DIRECT
 #endif
+
+
+/**
+ * @def OPENTHREAD_SPINEL_CONFIG_COMPATIBILITY_ERROR_CALLBACK_ENABLE
+ *
+ * Enables compatibility error callback in Spinel
+ */
+#ifndef OPENTHREAD_SPINEL_CONFIG_COMPATIBILITY_ERROR_CALLBACK_ENABLE
+#define OPENTHREAD_SPINEL_CONFIG_COMPATIBILITY_ERROR_CALLBACK_ENABLE 1
+#endif
+
+/**
+ * @def OPENTHREAD_SPINEL_CONFIG_MAX_SRC_MATCH_ENTRIES
+ *
+ * Defines size of the local source match table used by RadioSpinel
+ * when OPENTHREAD_SPINEL_CONFIG_RCP_RESTORATION_MAX_COUNT is used.
+ */
+#ifndef OPENTHREAD_SPINEL_CONFIG_MAX_SRC_MATCH_ENTRIES
+#define OPENTHREAD_SPINEL_CONFIG_MAX_SRC_MATCH_ENTRIES 12
+#endif
diff --git a/components/openthread/sbom_openthread.yml b/components/openthread/sbom_openthread.yml
index 7738bbe0a2e..b227b42db85 100644
--- a/components/openthread/sbom_openthread.yml
+++ b/components/openthread/sbom_openthread.yml
@@ -5,4 +5,4 @@ supplier: 'Organization: Espressif Systems (Shanghai) CO LTD'
 originator: 'Organization: Google LLC'
 description: OpenThread released by Google is an open-source implementation of the Thread networking
 url: https://github.com/espressif/openthread
-hash: f32c18bc0840f400182456e58ae3900fc2fb4af7
+hash: 005c5cefc22aaf0396e4327ee7f2e0ad32a7733b
diff --git a/components/openthread/src/esp_openthread_dns64.c b/components/openthread/src/esp_openthread_dns64.c
index 79faa1ad922..86d8b5fb0e5 100644
--- a/components/openthread/src/esp_openthread_dns64.c
+++ b/components/openthread/src/esp_openthread_dns64.c
@@ -75,7 +75,7 @@ static void dns_found_handler(const char *name, const ip_addr_t *ipaddr, void *c
 {
     dns_resolve_entry_t *resolve_entry = (dns_resolve_entry_t *)callback_arg;
     if (resolve_entry && resolve_entry->found) {
-        if (lwip_strnicmp(name, resolve_entry->name, sizeof(resolve_entry->name)) == 0) {
+        if (ipaddr && lwip_strnicmp(name, resolve_entry->name, sizeof(resolve_entry->name)) == 0) {
             ip_addr_t ipaddr_copy = *ipaddr;
             ip6_addr_t nat64_prefix;
             if (ipaddr_copy.type == IPADDR_TYPE_V4 && esp_openthread_get_nat64_prefix(&nat64_prefix) == ESP_OK) {
diff --git a/components/openthread/src/esp_openthread_netif_glue.c b/components/openthread/src/esp_openthread_netif_glue.c
index e7184698682..dd623aa5f78 100644
--- a/components/openthread/src/esp_openthread_netif_glue.c
+++ b/components/openthread/src/esp_openthread_netif_glue.c
@@ -16,6 +16,7 @@
 #include "esp_log.h"
 #include "esp_netif.h"
 #include "esp_openthread.h"
+#include "esp_openthread_border_router.h"
 #include "esp_openthread_common_macro.h"
 #include "esp_openthread_lock.h"
 #include "esp_openthread_netif_glue_priv.h"
@@ -33,6 +34,7 @@
 #include "openthread/ip6.h"
 #include "openthread/link.h"
 #include "openthread/message.h"
+#include "openthread/platform/infra_if.h"
 #include "openthread/thread.h"
 
 typedef struct {
@@ -381,3 +383,16 @@ esp_netif_t *esp_openthread_get_netif(void)
 {
     return s_openthread_netif;
 }
+
+otError otPlatGetInfraIfLinkLayerAddress(otInstance *aInstance, uint32_t aIfIndex, otPlatInfraIfLinkLayerAddress *aInfraIfLinkLayerAddress)
+{
+    esp_netif_t *backbone_netif = esp_openthread_get_backbone_netif();
+    if (esp_netif_get_netif_impl_index(backbone_netif) != aIfIndex) {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to get LL address, error: Invalid If index");
+        return OT_ERROR_FAILED;
+    } else {
+        esp_netif_get_mac(backbone_netif, aInfraIfLinkLayerAddress->mAddress);
+        aInfraIfLinkLayerAddress->mLength = 6;
+        return OT_ERROR_NONE;
+    }
+}
diff --git a/components/openthread/src/esp_openthread_platform.cpp b/components/openthread/src/esp_openthread_platform.cpp
index 8beb8143dc4..51bfd779042 100644
--- a/components/openthread/src/esp_openthread_platform.cpp
+++ b/components/openthread/src/esp_openthread_platform.cpp
@@ -204,3 +204,13 @@ esp_err_t esp_openthread_platform_process(otInstance *instance, const esp_openth
     }
     return ESP_OK;
 }
+
+uint32_t esp_openthread_get_alloc_caps(void)
+{
+    return
+#if CONFIG_OPENTHREAD_PLATFORM_MALLOC_CAP_SPIRAM
+    (MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
+#else
+    (MALLOC_CAP_DEFAULT | MALLOC_CAP_8BIT);
+#endif
+}
diff --git a/components/openthread/src/port/esp_openthread_radio.c b/components/openthread/src/port/esp_openthread_radio.c
index 4276809c528..f87cb682914 100644
--- a/components/openthread/src/port/esp_openthread_radio.c
+++ b/components/openthread/src/port/esp_openthread_radio.c
@@ -7,7 +7,6 @@
 #include <stdatomic.h>
 #include "esp_openthread_radio.h"
 
-#include "error.h"
 #include "esp_err.h"
 #include "sdkconfig.h"
 #include "esp_check.h"
@@ -25,6 +24,7 @@
 #include "rom/ets_sys.h"
 
 #include "openthread-core-config.h"
+#include "openthread/error.h"
 #include "openthread/link.h"
 #include "openthread/platform/diag.h"
 #include "openthread/platform/radio.h"
@@ -412,7 +412,8 @@ void otPlatRadioClearSrcMatchExtEntries(otInstance *aInstance)
 
 otError otPlatRadioEnergyScan(otInstance *aInstance, uint8_t aScanChannel, uint16_t aScanDuration)
 {
-    esp_ieee802154_energy_detect(aScanDuration);
+    esp_ieee802154_set_channel(aScanChannel);
+    esp_ieee802154_energy_detect(aScanDuration * US_PER_MS / US_PER_SYMBLE);
 
     return OT_ERROR_NONE;
 }
diff --git a/components/openthread/src/port/esp_openthread_radio_spinel.cpp b/components/openthread/src/port/esp_openthread_radio_spinel.cpp
index 3d566b05e9a..67cb2bb66ae 100644
--- a/components/openthread/src/port/esp_openthread_radio_spinel.cpp
+++ b/components/openthread/src/port/esp_openthread_radio_spinel.cpp
@@ -6,7 +6,6 @@
 
 #include "esp_openthread_radio.h"
 
-#include "link_raw.h"
 #include "sdkconfig.h"
 #include "esp_check.h"
 #include "esp_err.h"
@@ -55,6 +54,8 @@ static const char *radiospinel_workflow = "radio_spinel";
 
 static const esp_openthread_radio_config_t *s_esp_openthread_radio_config = NULL;
 
+static esp_openthread_compatibility_error_callback s_compatibility_error_callback = NULL;
+
 static void esp_openthread_radio_config_set(const esp_openthread_radio_config_t *config)
 {
     s_esp_openthread_radio_config = config;
@@ -65,6 +66,22 @@ static const esp_openthread_radio_config_t *esp_openthread_radio_config_get(void
     return s_esp_openthread_radio_config;
 }
 
+static void ot_spinel_compatibility_error_callback(void *context)
+{
+    OT_UNUSED_VARIABLE(context);
+    if (s_compatibility_error_callback) {
+        s_compatibility_error_callback();
+    } else {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "None callback to handle compatibility error of openthread spinel");
+        assert(false);
+    }
+}
+
+void esp_openthread_set_compatibility_error_callback(esp_openthread_compatibility_error_callback callback)
+{
+    s_compatibility_error_callback = callback;
+}
+
 esp_err_t esp_openthread_radio_init(const esp_openthread_platform_config_t *config)
 {
     spinel_iid_t iidList[ot::Spinel::kSpinelHeaderMaxNumIid];
@@ -90,7 +107,8 @@ esp_err_t esp_openthread_radio_init(const esp_openthread_platform_config_t *conf
                         "Spinel interface init failed");
 #endif
     s_spinel_driver.Init(s_spinel_interface.GetSpinelInterface(), true, iidList, ot::Spinel::kSpinelHeaderMaxNumIid);
-    s_radio.Init(/*skip_rcp_compatibility_check=*/false, /*reset_radio=*/true, &s_spinel_driver, s_radio_caps);
+    s_radio.SetCompatibilityErrorCallback(ot_spinel_compatibility_error_callback, esp_openthread_get_instance());
+    s_radio.Init(/*skip_rcp_compatibility_check=*/false, /*reset_radio=*/true, &s_spinel_driver, s_radio_caps, /*RCP_time_sync=*/true);
 #if CONFIG_OPENTHREAD_RADIO_SPINEL_SPI // CONFIG_OPENTHREAD_RADIO_SPINEL_SPI
     ESP_RETURN_ON_ERROR(s_spinel_interface.GetSpinelInterface().AfterRadioInit(), OT_PLAT_LOG_TAG, "Spinel interface init failed");
 #endif
@@ -337,15 +355,15 @@ void otPlatRadioSetMacFrameCounter(otInstance *aInstance, uint32_t aMacFrameCoun
 }
 
 #if CONFIG_OPENTHREAD_DIAG
-otError otPlatDiagProcess(otInstance *instance, int argc, char *argv[], char *output, size_t output_max_len)
+otError otPlatDiagProcess(otInstance *aInstance, uint8_t aArgsLength, char *aArgs[])
 {
     // deliver the platform specific diags commands to radio only ncp.
     char cmd[OPENTHREAD_CONFIG_DIAG_CMD_LINE_BUFFER_SIZE] = {'\0'};
     char *cur = cmd;
     char *end = cmd + sizeof(cmd);
 
-    for (int index = 0; index < argc; index++) {
-        cur += snprintf(cur, static_cast<size_t>(end - cur), "%s ", argv[index]);
+    for (int index = 0; index < aArgsLength; index++) {
+        cur += snprintf(cur, static_cast<size_t>(end - cur), "%s ", aArgs[index]);
     }
 
     return s_radio.PlatDiagProcess(cmd);
diff --git a/components/openthread/src/port/esp_openthread_state.c b/components/openthread/src/port/esp_openthread_state.c
index 6dbe1016705..7d04cba9f52 100644
--- a/components/openthread/src/port/esp_openthread_state.c
+++ b/components/openthread/src/port/esp_openthread_state.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -80,6 +80,21 @@ static void handle_ot_role_change(otInstance* instance)
     s_previous_role = role;
 }
 
+static void handle_ot_dataset_change(esp_openthread_dataset_type_t type, otInstance *instance)
+{
+    esp_openthread_dataset_changed_event_t event_data;
+    event_data.type = type;
+    memset(&event_data.new_dataset, 0, sizeof(event_data.new_dataset));
+    if (type == OPENTHREAD_ACTIVE_DATASET) {
+        (void)otDatasetGetActive(instance, &event_data.new_dataset);
+    } else if (type == OPENTHREAD_PENDING_DATASET) {
+        (void)otDatasetGetPending(instance, &event_data.new_dataset);
+    }
+    if (esp_event_post(OPENTHREAD_EVENT, OPENTHREAD_EVENT_DATASET_CHANGED, &event_data, sizeof(event_data), 0) != ESP_OK) {
+        ESP_LOGE(TAG, "Failed to post dataset changed event");
+    }
+}
+
 static void ot_state_change_callback(otChangedFlags changed_flags, void* ctx)
 {
     OT_UNUSED_VARIABLE(ctx);
@@ -99,6 +114,14 @@ static void ot_state_change_callback(otChangedFlags changed_flags, void* ctx)
     if (changed_flags & OT_CHANGED_THREAD_NETIF_STATE) {
         handle_ot_netif_state_change(instance);
     }
+
+    if (changed_flags & OT_CHANGED_ACTIVE_DATASET) {
+        handle_ot_dataset_change(OPENTHREAD_ACTIVE_DATASET, instance);
+    }
+
+    if (changed_flags & OT_CHANGED_PENDING_DATASET) {
+        handle_ot_dataset_change(OPENTHREAD_PENDING_DATASET, instance);
+    }
 }
 
 esp_err_t esp_openthread_state_event_init(otInstance* instance)
diff --git a/components/openthread/src/port/esp_openthread_trel.c b/components/openthread/src/port/esp_openthread_trel.c
new file mode 100644
index 00000000000..8424a7631d4
--- /dev/null
+++ b/components/openthread/src/port/esp_openthread_trel.c
@@ -0,0 +1,352 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_err.h"
+#include "esp_netif_types.h"
+#include "lwip/ip6_addr.h"
+#include "sdkconfig.h"
+#include "common/code_utils.hpp"
+#include "openthread/error.h"
+#include "esp_check.h"
+#include "esp_event.h"
+#include "esp_log.h"
+#include "esp_netif.h"
+#include "mdns.h"
+#include "esp_netif_ip_addr.h"
+#include "esp_openthread.h"
+#include "esp_openthread_border_router.h"
+#include "esp_openthread_common_macro.h"
+#include "esp_openthread_lock.h"
+#include "esp_openthread_radio.h"
+#include "esp_openthread_task_queue.h"
+#include "lwip/pbuf.h"
+#include "lwip/tcpip.h"
+#include "lwip/udp.h"
+#include "openthread/trel.h"
+#include "openthread/platform/diag.h"
+
+static esp_netif_t *s_trel_netif = NULL;
+static otPlatTrelCounters s_trel_counters;
+
+#define TREL_MDNS_TYPE "_trel"
+#define TREL_MDNS_PROTO "_udp"
+
+typedef struct {
+    uint16_t port;
+    struct udp_pcb *trel_pcb;
+} ot_trel_t;
+
+typedef struct {
+    struct pbuf *p;
+} ot_trel_recv_task_t;
+
+typedef struct {
+    struct udp_pcb *pcb;
+    const uint8_t *payload;
+    uint16_t length;
+    ip_addr_t peer_addr;
+    uint16_t peer_port;
+} ot_trel_send_task_t;
+
+static ot_trel_t s_ot_trel = {CONFIG_OPENTHREAD_TREL_PORT, NULL};
+static bool s_is_service_registered = false;
+
+static void trel_browse_notifier(mdns_result_t *result)
+{
+    while (result) {
+        if (result->addr && result->addr->addr.type == IPADDR_TYPE_V6) {
+            otPlatTrelPeerInfo info;
+            uint8_t trel_txt[1024] = {0};
+            uint16_t trel_txt_len = 0;
+            size_t index = 0;
+            while (index < result->txt_count) {
+                trel_txt[trel_txt_len++] = strlen(result->txt[index].key) + result->txt_value_len[index] + 1;
+                memcpy((trel_txt + trel_txt_len), (void *)result->txt[index].key, strlen(result->txt[index].key));
+                trel_txt_len += (strlen(result->txt[index].key));
+                trel_txt[trel_txt_len++] = '=';
+                memcpy((trel_txt + trel_txt_len), (void *)result->txt[index].value, result->txt_value_len[index]);
+                trel_txt_len += result->txt_value_len[index];
+                index++;
+            }
+            if (!s_trel_netif) {
+                s_trel_netif = result->esp_netif;
+            }
+            info.mTxtData = trel_txt;
+            info.mTxtLength = trel_txt_len;
+            info.mSockAddr.mPort = result->port;
+            memcpy(info.mSockAddr.mAddress.mFields.m32, result->addr->addr.u_addr.ip6.addr, OT_IP6_ADDRESS_SIZE);
+            info.mRemoved = (result->ttl == 0);
+            ESP_LOGI(OT_PLAT_LOG_TAG, "%s TREL peer: address: %s, port:%d", info.mRemoved ? "Remove" : "Found", ip6addr_ntoa(((ip6_addr_t*)(&result->addr->addr.u_addr.ip6))), info.mSockAddr.mPort);
+            esp_openthread_task_switching_lock_acquire(portMAX_DELAY);
+            otPlatTrelHandleDiscoveredPeerInfo(esp_openthread_get_instance(), &info);
+            esp_openthread_task_switching_lock_release();
+        }
+        result = result->next;
+    }
+}
+
+static void trel_recv_task(void *ctx)
+{
+    struct pbuf *recv_buf = (struct pbuf *)ctx;
+    uint8_t *data_buf = (uint8_t *)recv_buf->payload;
+    uint8_t *data_buf_to_free = NULL;
+    uint16_t length = recv_buf->len;
+
+    if (recv_buf->next != NULL) {
+        data_buf = (uint8_t *)malloc(recv_buf->tot_len);
+        if (data_buf != NULL) {
+            length = recv_buf->tot_len;
+            data_buf_to_free = data_buf;
+            pbuf_copy_partial(recv_buf, data_buf, recv_buf->tot_len, 0);
+        } else {
+            ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to allocate data buf when receiving Thread TREL message");
+            ExitNow();
+        }
+    }
+    otPlatTrelHandleReceived(esp_openthread_get_instance(), data_buf, length);
+
+exit:
+    if (data_buf_to_free) {
+        free(data_buf_to_free);
+    }
+    pbuf_free(recv_buf);
+}
+
+static void handle_trel_udp_recv(void *ctx, struct udp_pcb *pcb, struct pbuf *p, const ip_addr_t *addr, uint16_t port)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Receive from %s:%d", ip6addr_ntoa(&(addr->u_addr.ip6)), port);
+    if (esp_openthread_task_queue_post(trel_recv_task, p) != ESP_OK) {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to receive OpenThread TREL message");
+    }
+}
+
+static esp_err_t ot_new_trel(void *ctx)
+{
+    ot_trel_t *task = (ot_trel_t *)ctx;
+
+    task->trel_pcb = udp_new();
+    ESP_RETURN_ON_FALSE(task->trel_pcb != NULL, ESP_ERR_NO_MEM, OT_PLAT_LOG_TAG, "Failed to create a new UDP pcb");
+    udp_bind(task->trel_pcb, IP6_ADDR_ANY, task->port);
+    udp_recv(task->trel_pcb, handle_trel_udp_recv, NULL);
+    return ESP_OK;
+}
+
+void otPlatTrelEnable(otInstance *aInstance, uint16_t *aUdpPort)
+{
+    *aUdpPort = s_ot_trel.port;
+    esp_openthread_task_switching_lock_release();
+    esp_err_t err = esp_netif_tcpip_exec(ot_new_trel, &s_ot_trel);
+    if (err != ESP_OK) {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "Fail to create trel udp");
+    }
+    mdns_browse_new(TREL_MDNS_TYPE, TREL_MDNS_PROTO, trel_browse_notifier);
+    esp_openthread_task_switching_lock_acquire(portMAX_DELAY);
+}
+
+static void trel_send_task(void *ctx)
+{
+    err_t err = ERR_OK;
+    struct pbuf *send_buf = NULL;
+    ot_trel_send_task_t *task = (ot_trel_send_task_t *)ctx;
+
+    task->pcb = s_ot_trel.trel_pcb;
+    task->pcb->ttl = UDP_TTL;
+    task->pcb->netif_idx = esp_netif_get_netif_impl_index(s_trel_netif);
+    task->peer_addr.u_addr.ip6.zone = 0;
+    task->peer_addr.type = IPADDR_TYPE_V6;
+    task->pcb->flags = (task->pcb->flags & (~UDP_FLAGS_MULTICAST_LOOP));
+    task->pcb->local_port = s_ot_trel.port;
+    send_buf = pbuf_alloc(PBUF_TRANSPORT, task->length, PBUF_RAM);
+    if (send_buf == NULL) {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to allocate data buf when sending Thread TREL message");
+        ExitNow();
+    }
+    memcpy(send_buf->payload, task->payload, task->length);
+    err = udp_sendto_if(task->pcb, send_buf, &task->peer_addr, task->peer_port, netif_get_by_index(task->pcb->netif_idx));
+    if(err != ERR_OK) {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "Fail to send trel msg to %s:%d %d (%d)", ip6addr_ntoa(&(task->peer_addr.u_addr.ip6)), task->peer_port, task->pcb->netif_idx, err);
+    }
+exit:
+    pbuf_free(send_buf);
+    free(task);
+}
+
+void otPlatTrelSend(otInstance       *aInstance,
+                    const uint8_t    *aUdpPayload,
+                    uint16_t          aUdpPayloadLen,
+                    const otSockAddr *aDestSockAddr)
+{
+    if (!s_trel_netif) {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "None Thread TREL interface");
+        return;
+    }
+    ot_trel_send_task_t *task = (ot_trel_send_task_t *)malloc(sizeof(ot_trel_send_task_t));
+    if (task == NULL) {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "Failed to allocate buf for Thread TREL");
+        return;
+    }
+    memcpy(task->peer_addr.u_addr.ip6.addr, aDestSockAddr->mAddress.mFields.m32, OT_IP6_ADDRESS_SIZE);
+    task->peer_port = aDestSockAddr->mPort;
+    ESP_LOGD(OT_PLAT_LOG_TAG, "send trel msg to %s:%d", ip6addr_ntoa(&(task->peer_addr.u_addr.ip6)), task->peer_port);
+    task->payload = aUdpPayload;
+    task->length = aUdpPayloadLen;
+    esp_openthread_task_switching_lock_release();
+    tcpip_callback(trel_send_task, task);
+    esp_openthread_task_switching_lock_acquire(portMAX_DELAY);
+}
+
+void otPlatTrelRegisterService(otInstance *aInstance, uint16_t aPort, const uint8_t *aTxtData, uint8_t aTxtLength)
+{
+    esp_err_t ret = ESP_OK;
+
+    esp_openthread_task_switching_lock_release();
+    if (s_is_service_registered) {
+        mdns_service_remove(TREL_MDNS_TYPE, TREL_MDNS_PROTO);
+    }
+    mdns_service_add(NULL, TREL_MDNS_TYPE, TREL_MDNS_PROTO, aPort, NULL, 0);
+    s_is_service_registered = true;
+    uint16_t index = 0;
+    while (index < aTxtLength) {
+        const uint8_t *item_header = aTxtData + index + 1;
+        uint8_t item_len = aTxtData[index];
+
+        char key[UINT8_MAX + 1];
+        for (uint16_t i = 0; i < item_len; i++) {
+            if (item_header[i] == '=') {
+                ESP_GOTO_ON_FALSE(i != 0, ESP_FAIL, exit, OT_PLAT_LOG_TAG, "Wrong format of _trel._udp txt key");
+                key[i] = '\0';
+                uint16_t value_len = item_len - i - 1;
+                ESP_GOTO_ON_FALSE(value_len != 0, ESP_FAIL, exit, OT_PLAT_LOG_TAG, "Wrong format of _trel._udp txt value");
+                mdns_service_txt_item_set_with_explicit_value_len(TREL_MDNS_TYPE, TREL_MDNS_PROTO, key, (const char *)item_header + i + 1, value_len);
+                break;
+            }
+            key[i] = item_header[i];
+        }
+        index += item_len + 1;
+    }
+exit:
+    if (ret != ESP_OK) {
+        ESP_LOGE(OT_PLAT_LOG_TAG, "Registered TREL service with some errors");
+    }
+    esp_openthread_task_switching_lock_acquire(portMAX_DELAY);
+}
+
+void otPlatTrelResetCounters(otInstance *aInstance)
+{
+    memset(&s_trel_counters, 0, sizeof(otPlatTrelCounters));
+}
+
+static void trel_disable_task(void *ctx)
+{
+    struct udp_pcb *pcb = (struct udp_pcb *)ctx;
+    udp_remove(pcb);
+}
+
+void otPlatTrelDisable(otInstance *aInstance)
+{
+    esp_openthread_task_switching_lock_release();
+    if (s_ot_trel.trel_pcb) {
+        tcpip_callback(trel_disable_task, s_ot_trel.trel_pcb);
+    }
+    mdns_service_remove(TREL_MDNS_TYPE, TREL_MDNS_PROTO);
+    s_is_service_registered = false;
+    mdns_browse_delete(TREL_MDNS_TYPE, TREL_MDNS_PROTO);
+    esp_openthread_task_switching_lock_acquire(portMAX_DELAY);
+    s_ot_trel.trel_pcb = NULL;
+}
+
+const otPlatTrelCounters *otPlatTrelGetCounters(otInstance *aInstance)
+{
+    return &s_trel_counters;
+}
+
+// TODO: TZ-1169
+OT_TOOL_WEAK otError otPlatRadioSetTransmitPower(otInstance *aInstance, int8_t aPower)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioSetTransmitPower`");
+    return OT_ERROR_NOT_IMPLEMENTED;
+}
+
+OT_TOOL_WEAK otError otPlatRadioGetTransmitPower(otInstance *aInstance, int8_t *aPower)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetTransmitPower`");
+    return OT_ERROR_NOT_IMPLEMENTED;
+}
+
+OT_TOOL_WEAK bool otPlatRadioGetPromiscuous(otInstance *aInstance)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetPromiscuous`");
+    return false;
+}
+
+OT_TOOL_WEAK otError otPlatRadioSetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t aThreshold)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioSetCcaEnergyDetectThreshold`");
+    return OT_ERROR_NOT_IMPLEMENTED;
+}
+
+OT_TOOL_WEAK otError otPlatRadioGetCcaEnergyDetectThreshold(otInstance *aInstance, int8_t *aThreshold)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetCcaEnergyDetectThreshold`");
+    return OT_ERROR_NOT_IMPLEMENTED;
+}
+
+OT_TOOL_WEAK void otPlatRadioGetIeeeEui64(otInstance *aInstance, uint8_t *aIeeeEui64)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetIeeeEui64`");
+}
+
+OT_TOOL_WEAK otRadioFrame *otPlatRadioGetTransmitBuffer(otInstance *aInstance)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatRadioGetTransmitBuffer`");
+    return NULL;
+}
+
+#if CONFIG_OPENTHREAD_DIAG
+
+OT_TOOL_WEAK void otPlatDiagSetOutputCallback(otInstance *aInstance, otPlatDiagOutputCallback aCallback, void *aContext)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagSetOutputCallback`");
+}
+
+OT_TOOL_WEAK void otPlatDiagModeSet(bool mode)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagModeSet`");
+}
+
+OT_TOOL_WEAK bool otPlatDiagModeGet(void)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagModeGet`");
+    return false;
+}
+
+OT_TOOL_WEAK void otPlatDiagTxPowerSet(int8_t tx_power)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagTxPowerSet`");
+}
+
+OT_TOOL_WEAK void otPlatDiagChannelSet(uint8_t channel)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagChannelSet`");
+}
+
+OT_TOOL_WEAK void otPlatDiagAlarmCallback(otInstance *aInstance)
+{
+    ESP_LOGD(OT_PLAT_LOG_TAG, "Running in TREL mode and not support `otPlatDiagAlarmCallback`");
+}
+
+#endif // CONFIG_OPENTHREAD_DIAG
+
+OT_TOOL_WEAK esp_err_t esp_openthread_radio_init(const esp_openthread_platform_config_t *config)
+{
+    ESP_LOGI(OT_PLAT_LOG_TAG, "Running in TREL mode");
+    return ESP_OK;
+}
+
+OT_TOOL_WEAK void esp_openthread_radio_deinit(void)
+{
+    ESP_LOGI(OT_PLAT_LOG_TAG, "Running in TREL mode");
+}
diff --git a/components/openthread/src/port/esp_spi_spinel_interface.cpp b/components/openthread/src/port/esp_spi_spinel_interface.cpp
index e19acd91527..61d6cfab2fa 100644
--- a/components/openthread/src/port/esp_spi_spinel_interface.cpp
+++ b/components/openthread/src/port/esp_spi_spinel_interface.cpp
@@ -6,7 +6,7 @@
 
 #include "esp_spi_spinel_interface.hpp"
 
-#include "error.h"
+#include "openthread/error.h"
 #include "esp_check.h"
 #include "esp_openthread_common_macro.h"
 #include "esp_rom_sys.h"
diff --git a/components/openthread/src/spinel/esp_radio_spinel.cpp b/components/openthread/src/spinel/esp_radio_spinel.cpp
index fbf794046df..79ae1efbe77 100644
--- a/components/openthread/src/spinel/esp_radio_spinel.cpp
+++ b/components/openthread/src/spinel/esp_radio_spinel.cpp
@@ -10,9 +10,11 @@
 #include "platform/exit_code.h"
 #include "radio_spinel.hpp"
 #include "esp_radio_spinel.h"
+#include "esp_radio_spinel_platform.h"
 #include "esp_radio_spinel_adapter.hpp"
 #include "esp_radio_spinel_uart_interface.hpp"
 #include "spinel_driver.hpp"
+#include "openthread/link.h"
 
 #define SPINEL_VENDOR_PROPERTY_BIT_PENDINGMODE BIT(0)
 #define SPINEL_VENDOR_PROPERTY_BIT_COORDINATOR BIT(1)
@@ -39,6 +41,8 @@ static otRadioCaps s_radio_caps = (OT_RADIO_CAPS_ENERGY_SCAN       |
                                    OT_RADIO_CAPS_ACK_TIMEOUT       |
                                    OT_RADIO_CAPS_SLEEP_TO_TX);
 
+static esp_radio_spinel_compatibility_error_callback s_radio_spinel_compatibility_error_callback = NULL;
+
 static esp_radio_spinel_idx_t get_index_from_instance(otInstance *instance)
 {
     // TZ-563: Implement the function to get the esp radio spinel idx from otInstance for multipan rcp
@@ -67,6 +71,22 @@ static void esp_radio_spinel_restore_vendor_properities(void *context)
     }
 }
 
+static void radio_spinel_compatibility_error_callback(void *context)
+{
+    OT_UNUSED_VARIABLE(context);
+    if (s_radio_spinel_compatibility_error_callback) {
+        s_radio_spinel_compatibility_error_callback();
+    } else {
+        ESP_LOGE(ESP_SPINEL_LOG_TAG, "None callback to handle compatibility error of openthread spinel");
+        assert(false);
+    }
+}
+
+void esp_openthread_set_compatibility_error_callback(esp_radio_spinel_compatibility_error_callback callback)
+{
+    s_radio_spinel_compatibility_error_callback = callback;
+}
+
 void ReceiveDone(otInstance *aInstance, otRadioFrame *aFrame, otError aError)
 {
     esp_radio_spinel_idx_t idx = get_index_from_instance(aInstance);
@@ -242,12 +262,13 @@ esp_err_t esp_radio_spinel_uart_interface_enable(const esp_radio_spinel_uart_con
 void esp_radio_spinel_init(esp_radio_spinel_idx_t idx)
 {
     spinel_iid_t iidList[ot::Spinel::kSpinelHeaderMaxNumIid];
+    otInstance *instance = get_instance_from_index(idx);
 
     // Multipan is not currently supported
     iidList[0] = 0;
     s_spinel_driver[idx].Init(s_spinel_interface[idx].GetSpinelInterface(), true, iidList, ot::Spinel::kSpinelHeaderMaxNumIid);
-    s_radio[idx].Init(/*skip_rcp_compatibility_check=*/false, /*reset_radio=*/true, &s_spinel_driver[idx], s_radio_caps);
-    otInstance *instance = get_instance_from_index(idx);
+    s_radio[idx].SetCompatibilityErrorCallback(radio_spinel_compatibility_error_callback, instance);
+    s_radio[idx].Init(/*skip_rcp_compatibility_check=*/false, /*reset_radio=*/true, &s_spinel_driver[idx], s_radio_caps, false);
     s_radio[idx].SetVendorRestorePropertiesCallback(esp_radio_spinel_restore_vendor_properities, instance);
 }
 
@@ -405,6 +426,19 @@ esp_err_t esp_radio_spinel_set_rcp_ready(esp_radio_spinel_idx_t idx)
     return ESP_OK;
 }
 
+// TZ-1261
+uint32_t otLinkGetFrameCounter(otInstance *aInstance)
+{
+    esp_radio_spinel_idx_t idx = get_index_from_instance(aInstance);
+    return esp_radio_spinel_extern_get_frame_counter(idx);
+}
+
+__attribute__((weak)) uint32_t esp_radio_spinel_extern_get_frame_counter(esp_radio_spinel_idx_t idx)
+{
+    ESP_LOGW(ESP_SPINEL_LOG_TAG, "None function to get frame counter");
+    return 0;
+}
+
 namespace ot {
 namespace Spinel {
 
diff --git a/components/partition_table/CMakeLists.txt b/components/partition_table/CMakeLists.txt
index d5844374b0d..61fe492c7b5 100644
--- a/components/partition_table/CMakeLists.txt
+++ b/components/partition_table/CMakeLists.txt
@@ -1,12 +1,22 @@
 idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(non_os_build NON_OS_BUILD)
+
 set(priv_req)
 if(NOT ${target} STREQUAL "linux")
     list(APPEND priv_req esptool_py)
 endif()
 
+if(NOT DEFINED BOOTLOADER_OFFSET)  # For Linux target
+    if(DEFINED CONFIG_BOOTLOADER_OFFSET_IN_FLASH)
+        set(BOOTLOADER_OFFSET ${CONFIG_BOOTLOADER_OFFSET_IN_FLASH})
+    else()
+        set(BOOTLOADER_OFFSET 0)
+    endif()
+endif()
+
 idf_component_register(PRIV_REQUIRES ${priv_req})
 
-if(BOOTLOADER_BUILD)
+if(non_os_build)
     return()
 endif()
 
@@ -22,6 +32,10 @@ else()
     set(final_partition_target "build_partition_table")
 endif()
 
+if(CONFIG_BOOTLOADER_RECOVERY_OFFSET)
+    set(recovery_bootloader_option --recovery-bootloader-offset ${CONFIG_BOOTLOADER_RECOVERY_OFFSET})
+endif()
+
 if(NOT CONFIG_PARTITION_TABLE_MD5)
     set(md5_opt --disable-md5sum)
 endif()
@@ -53,8 +67,13 @@ idf_build_get_property(build_dir BUILD_DIR)
 idf_build_get_property(python PYTHON)
 idf_build_get_property(extra_subtypes EXTRA_PARTITION_SUBTYPES)
 
-set(gen_partition_table "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/gen_esp32part.py" "-q"
-                        "--offset" "${PARTITION_TABLE_OFFSET}" "${md5_opt}" "${flashsize_opt}"
+set(gen_partition_table "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/gen_esp32part.py"
+                        "-q"
+                        "--offset" "${PARTITION_TABLE_OFFSET}"
+                        "--primary-bootloader-offset" "${BOOTLOADER_OFFSET}"
+                        "${recovery_bootloader_option}"
+                        "${md5_opt}"
+                        "${flashsize_opt}"
                         "${partition_secure_opt}" ${extra_partition_subtypes} "--")
 
 set(partition_table_display
diff --git a/components/partition_table/gen_esp32part.py b/components/partition_table/gen_esp32part.py
index cce5b78e916..d8d19d6e7e4 100755
--- a/components/partition_table/gen_esp32part.py
+++ b/components/partition_table/gen_esp32part.py
@@ -7,11 +7,8 @@
 # See https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/partition-tables.html
 # for explanation of partition table structure and uses.
 #
-# SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
-
-from __future__ import division, print_function, unicode_literals
-
 import argparse
 import binascii
 import errno
@@ -32,12 +29,16 @@
 SECURE_V1 = 'v1'
 SECURE_V2 = 'v2'
 
-__version__ = '1.3'
+__version__ = '1.4'
 
 APP_TYPE = 0x00
 DATA_TYPE = 0x01
+BOOTLOADER_TYPE = 0x02
+PARTITION_TABLE_TYPE = 0x03
 
 TYPES = {
+    'bootloader': BOOTLOADER_TYPE,
+    'partition_table': PARTITION_TABLE_TYPE,
     'app': APP_TYPE,
     'data': DATA_TYPE,
 }
@@ -56,6 +57,15 @@ def get_ptype_as_int(ptype):
 
 # Keep this map in sync with esp_partition_subtype_t enum in esp_partition.h
 SUBTYPES = {
+    BOOTLOADER_TYPE: {
+        'primary': 0x00,
+        'ota': 0x01,
+        'recovery': 0x02,
+    },
+    PARTITION_TABLE_TYPE: {
+        'primary': 0x00,
+        'ota': 0x01,
+    },
     APP_TYPE: {
         'factory': 0x00,
         'test': 0x20,
@@ -90,6 +100,8 @@ def get_subtype_as_int(ptype, subtype):
 ALIGNMENT = {
     APP_TYPE: 0x10000,
     DATA_TYPE: 0x1000,
+    BOOTLOADER_TYPE: 0x1000,
+    PARTITION_TABLE_TYPE: 0x1000,
 }
 
 
@@ -110,7 +122,7 @@ def get_alignment_size_for_type(ptype):
         else:
             # For no secure boot enabled case, app partition must be 4K aligned (min. flash erase size)
             return 0x1000
-    # No specific size alignement requirement as such
+    # No specific size alignment requirement as such
     return 0x1
 
 
@@ -119,6 +131,10 @@ def get_partition_type(ptype):
         return APP_TYPE
     if ptype == 'data':
         return DATA_TYPE
+    if ptype == 'bootloader':
+        return BOOTLOADER_TYPE
+    if ptype == 'partition_table':
+        return PARTITION_TABLE_TYPE
     raise InputError('Invalid partition type')
 
 
@@ -138,6 +154,8 @@ def add_extra_subtypes(csv):
 md5sum = True
 secure = SECURE_NONE
 offset_part_table = 0
+primary_bootloader_offset = None
+recovery_bootloader_offset = None
 
 
 def status(msg):
@@ -195,6 +213,11 @@ def expand_vars(f):
         # fix up missing offsets & negative sizes
         last_end = offset_part_table + PARTITION_TABLE_SIZE  # first offset after partition table
         for e in res:
+            is_primary_bootloader = (e.type == BOOTLOADER_TYPE and e.subtype == SUBTYPES[e.type]['primary'])
+            is_primary_partition_table = (e.type == PARTITION_TABLE_TYPE and e.subtype == SUBTYPES[e.type]['primary'])
+            if is_primary_bootloader or is_primary_partition_table:
+                # They do not participate in the restoration of missing offsets
+                continue
             if e.offset is not None and e.offset < last_end:
                 if e == res[0]:
                     raise InputError('CSV Error at line %d: Partitions overlap. Partition sets offset 0x%x. '
@@ -265,7 +288,10 @@ def verify(self):
         last = None
         for p in sorted(self, key=lambda x:x.offset):
             if p.offset < offset_part_table + PARTITION_TABLE_SIZE:
-                raise InputError('Partition offset 0x%x is below 0x%x' % (p.offset, offset_part_table + PARTITION_TABLE_SIZE))
+                is_primary_bootloader = (p.type == BOOTLOADER_TYPE and p.subtype == SUBTYPES[p.type]['primary'])
+                is_primary_partition_table = (p.type == PARTITION_TABLE_TYPE and p.subtype == SUBTYPES[p.type]['primary'])
+                if not (is_primary_bootloader or is_primary_partition_table):
+                    raise InputError('Partition offset 0x%x is below 0x%x' % (p.offset, offset_part_table + PARTITION_TABLE_SIZE))
             if last is not None and p.offset < last.offset + last.size:
                 raise InputError('Partition at 0x%x overlaps 0x%x-0x%x' % (p.offset, last.offset, last.offset + last.size - 1))
             last = p
@@ -373,8 +399,8 @@ def from_csv(cls, line, line_no):
         res.name = fields[0]
         res.type = res.parse_type(fields[1])
         res.subtype = res.parse_subtype(fields[2])
-        res.offset = res.parse_address(fields[3])
-        res.size = res.parse_address(fields[4])
+        res.offset = res.parse_address(fields[3], res.type, res.subtype)
+        res.size = res.parse_size(fields[4], res.type)
         if res.size is None:
             raise InputError("Size field can't be empty")
 
@@ -428,7 +454,29 @@ def parse_subtype(self, strval):
             return SUBTYPES[DATA_TYPE]['undefined']
         return parse_int(strval, SUBTYPES.get(self.type, {}))
 
-    def parse_address(self, strval):
+    def parse_size(self, strval, ptype):
+        if ptype == BOOTLOADER_TYPE:
+            if primary_bootloader_offset is None:
+                raise InputError(f'Primary bootloader offset is not defined. Please use --primary-bootloader-offset')
+            return offset_part_table - primary_bootloader_offset
+        if ptype == PARTITION_TABLE_TYPE:
+            return PARTITION_TABLE_SIZE
+        if strval == '':
+            return None  # PartitionTable will fill in default
+        return parse_int(strval)
+
+    def parse_address(self, strval, ptype, psubtype):
+        if ptype == BOOTLOADER_TYPE:
+            if psubtype == SUBTYPES[ptype]['primary']:
+                if primary_bootloader_offset is None:
+                    raise InputError(f'Primary bootloader offset is not defined. Please use --primary-bootloader-offset')
+                return primary_bootloader_offset
+            if psubtype == SUBTYPES[ptype]['recovery']:
+                if recovery_bootloader_offset is None:
+                    raise InputError(f'Recovery bootloader offset is not defined. Please use --recovery-bootloader-offset')
+                return recovery_bootloader_offset
+        if ptype == PARTITION_TABLE_TYPE and psubtype == SUBTYPES[ptype]['primary']:
+            return offset_part_table
         if strval == '':
             return None  # PartitionTable will fill in default
         return parse_int(strval)
@@ -548,6 +596,8 @@ def main():
     global md5sum
     global offset_part_table
     global secure
+    global primary_bootloader_offset
+    global recovery_bootloader_offset
     parser = argparse.ArgumentParser(description='ESP32 partition table utility')
 
     parser.add_argument('--flash-size', help='Optional flash size limit, checks partition table fits in flash',
@@ -558,6 +608,8 @@ def main():
                                                'enabled by default and this flag does nothing.', action='store_true')
     parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
     parser.add_argument('--offset', '-o', help='Set offset partition table', default='0x8000')
+    parser.add_argument('--primary-bootloader-offset', help='Set primary bootloader offset', default=None)
+    parser.add_argument('--recovery-bootloader-offset', help='Set recovery bootloader offset', default=None)
     parser.add_argument('--secure', help='Require app partitions to be suitable for secure boot', nargs='?', const=SECURE_V1, choices=[SECURE_V1, SECURE_V2])
     parser.add_argument('--extra-partition-subtypes', help='Extra partition subtype entries', nargs='*')
     parser.add_argument('input', help='Path to CSV or binary file to parse.', type=argparse.FileType('rb'))
@@ -570,6 +622,15 @@ def main():
     md5sum = not args.disable_md5sum
     secure = args.secure
     offset_part_table = int(args.offset, 0)
+    if args.primary_bootloader_offset is not None:
+        primary_bootloader_offset = int(args.primary_bootloader_offset, 0)
+        if primary_bootloader_offset >= offset_part_table:
+            raise InputError(
+                f'Unsupported configuration. Primary bootloader must be below partition table. '
+                f'Check --primary-bootloader-offset={primary_bootloader_offset:#x} and --offset={offset_part_table:#x}'
+            )
+    if args.recovery_bootloader_offset is not None:
+        recovery_bootloader_offset = int(args.recovery_bootloader_offset, 0)
     if args.extra_partition_subtypes:
         add_extra_subtypes(args.extra_partition_subtypes)
 
diff --git a/components/partition_table/parttool.py b/components/partition_table/parttool.py
index 85167f3af14..03ef8920580 100755
--- a/components/partition_table/parttool.py
+++ b/components/partition_table/parttool.py
@@ -14,7 +14,7 @@
 
 import gen_esp32part as gen
 
-__version__ = '2.1'
+__version__ = '2.2'
 
 COMPONENTS_PATH = os.path.expandvars(os.path.join('$IDF_PATH', 'components'))
 ESPTOOL_PY = os.path.join(COMPONENTS_PATH, 'esptool_py', 'esptool', 'esptool.py')
@@ -56,12 +56,14 @@ def __init__(self, p_type, subtype, part_list=None):
 
 class ParttoolTarget():
 
-    def __init__(self, port=None, baud=None, partition_table_offset=PARTITION_TABLE_OFFSET, partition_table_file=None,
-                 esptool_args=[], esptool_write_args=[], esptool_read_args=[], esptool_erase_args=[]):
+    def __init__(self, port=None, baud=None, partition_table_offset=PARTITION_TABLE_OFFSET, primary_bootloader_offset=None, recovery_bootloader_offset=None,
+                 partition_table_file=None, esptool_args=[], esptool_write_args=[], esptool_read_args=[], esptool_erase_args=[]):
         self.port = port
         self.baud = baud
 
         gen.offset_part_table = partition_table_offset
+        gen.primary_bootloader_offset = primary_bootloader_offset
+        gen.recovery_bootloader_offset = recovery_bootloader_offset
 
         def parse_esptool_args(esptool_args):
             results = list()
@@ -239,6 +241,8 @@ def main():
     parser.add_argument('--baud', '-b', help='baudrate to use', type=int)
 
     parser.add_argument('--partition-table-offset', '-o', help='offset to read the partition table from', type=str)
+    parser.add_argument('--primary-bootloader-offset', help='offset for primary bootloader', type=str)
+    parser.add_argument('--recovery-bootloader-offset', help='offset for recovery bootloader', type=str)
     parser.add_argument('--partition-table-file', '-f', help='file (CSV/binary) to read the partition table from; \
                                                             overrides device attached to specified port as the partition table source when defined')
 
@@ -313,6 +317,12 @@ def main():
     if args.partition_table_offset:
         target_args['partition_table_offset'] = int(args.partition_table_offset, 0)
 
+    if args.primary_bootloader_offset:
+        target_args['primary_bootloader_offset'] = int(args.primary_bootloader_offset, 0)
+
+    if args.recovery_bootloader_offset:
+        target_args['recovery_bootloader_offset'] = int(args.recovery_bootloader_offset, 0)
+
     if args.esptool_args:
         target_args['esptool_args'] = args.esptool_args
 
diff --git a/components/partition_table/project_include.cmake b/components/partition_table/project_include.cmake
index 7778af11558..41f8b2a70ef 100644
--- a/components/partition_table/project_include.cmake
+++ b/components/partition_table/project_include.cmake
@@ -1,11 +1,25 @@
 set(PARTITION_TABLE_OFFSET ${CONFIG_PARTITION_TABLE_OFFSET})
+if(NOT DEFINED BOOTLOADER_OFFSET)  # For Linux target
+    if(DEFINED CONFIG_BOOTLOADER_OFFSET_IN_FLASH)
+        set(BOOTLOADER_OFFSET ${CONFIG_BOOTLOADER_OFFSET_IN_FLASH})
+    else()
+        set(BOOTLOADER_OFFSET 0)
+    endif()
+endif()
+
+if(CONFIG_BOOTLOADER_RECOVERY_OFFSET)
+    set(RECOVERY_BOOTLOADER_OPTION --recovery-bootloader-offset ${CONFIG_BOOTLOADER_RECOVERY_OFFSET})
+else()
+    set(RECOVERY_BOOTLOADER_OPTION "")
+endif()
 
 set(PARTITION_TABLE_CHECK_SIZES_TOOL_PATH "${CMAKE_CURRENT_LIST_DIR}/check_sizes.py")
 
 idf_build_get_property(build_dir BUILD_DIR)
 idf_build_set_property(PARTITION_TABLE_BIN_PATH "${build_dir}/partition_table/partition-table.bin")
+idf_build_get_property(non_os_build NON_OS_BUILD)
 
-if(NOT BOOTLOADER_BUILD)
+if(NOT non_os_build)
     # Set PARTITION_CSV_PATH to the configured partition CSV file
     # absolute path
     if(CONFIG_PARTITION_TABLE_CUSTOM)
@@ -57,6 +71,8 @@ function(partition_table_get_partition_info result get_part_info_args part_info)
     execute_process(COMMAND ${python}
         ${idf_path}/components/partition_table/parttool.py -q
         --partition-table-offset ${PARTITION_TABLE_OFFSET}
+        --primary-bootloader-offset ${BOOTLOADER_OFFSET}
+        ${RECOVERY_BOOTLOADER_OPTION}
         --partition-table-file ${PARTITION_CSV_PATH}
         get_partition_info ${get_part_info_args} --info ${part_info}
         ${extra_partition_subtypes}
diff --git a/components/partition_table/test_gen_esp32part_host/gen_esp32part_tests.py b/components/partition_table/test_gen_esp32part_host/gen_esp32part_tests.py
index 1fcd855e183..0c930a8c42c 100755
--- a/components/partition_table/test_gen_esp32part_host/gen_esp32part_tests.py
+++ b/components/partition_table/test_gen_esp32part_host/gen_esp32part_tests.py
@@ -1,8 +1,6 @@
 #!/usr/bin/env python
-# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
-from __future__ import division, print_function
-
 import csv
 import io
 import os
@@ -64,6 +62,10 @@ def _strip_trailing_ffs(binary_table):
 
 
 class CSVParserTests(Py23TestCase):
+    def tearDown(self):
+        gen_esp32part.primary_bootloader_offset = None
+        gen_esp32part.recovery_bootloader_offset = None
+        gen_esp32part.offset_part_table = 0
 
     def test_simple_partition(self):
         table = gen_esp32part.PartitionTable.from_csv(SIMPLE_CSV)
@@ -182,6 +184,47 @@ def test_unique_name_fail(self):
             t = gen_esp32part.PartitionTable.from_csv(csv)
             t.verify()
 
+    def test_bootloader_and_part_table_partitions_no_sdkconfig(self):
+        csv = """
+bootloader, bootloader, primary, N/A, N/A
+"""
+        with self.assertRaisesRegex(gen_esp32part.InputError, 'Primary bootloader offset is not defined. Please use --primary-bootloader-offset'):
+            gen_esp32part.PartitionTable.from_csv(csv)
+
+    def test_bootloader_and_part_table_partitions(self):
+        csv = """
+bootloader,       bootloader,       primary, N/A, N/A
+partition_table,  partition_table,  primary, N/A, N/A
+FactoryApp,       app,              factory, ,    1M
+OtaBTLDR,         bootloader,       ota,     ,    N/A
+OtaPrtTable,      partition_table,  ota,     ,    N/A
+RecoveryBTLDR,    bootloader,       recovery, N/A, N/A
+"""
+        gen_esp32part.primary_bootloader_offset = 0x1000
+        gen_esp32part.recovery_bootloader_offset = 0x200000
+        gen_esp32part.offset_part_table = 0x9000
+        part_table_size = 0x1000
+        bootloader_size = gen_esp32part.offset_part_table - gen_esp32part.primary_bootloader_offset
+        t = gen_esp32part.PartitionTable.from_csv(csv)
+        t.verify()
+        # bootloader
+        self.assertEqual(t[0].offset, gen_esp32part.primary_bootloader_offset)
+        self.assertEqual(t[0].size, bootloader_size)
+        # partition_table
+        self.assertEqual(t[1].offset, gen_esp32part.offset_part_table)
+        self.assertEqual(t[1].size, part_table_size)
+        # FactoryApp
+        self.assertEqual(t[2].offset, 0x10000)
+        # OtaBTLDR
+        self.assertEqual(t[3].offset, 0x110000)
+        self.assertEqual(t[3].size, bootloader_size)
+        # OtaPrtTable
+        self.assertEqual(t[4].offset, 0x118000)
+        self.assertEqual(t[4].size, part_table_size)
+        # RecoveryBTLDR
+        self.assertEqual(t[5].offset, gen_esp32part.recovery_bootloader_offset)
+        self.assertEqual(t[5].size, bootloader_size)
+
 
 class BinaryOutputTests(Py23TestCase):
     def test_binary_entry(self):
@@ -369,7 +412,7 @@ def test_basic_cmdline(self):
                 from_csv = gen_esp32part.PartitionTable.from_csv(f.read())
             self.assertEqual(_strip_trailing_ffs(from_csv.to_binary()), LONGER_BINARY_TABLE)
 
-            # run gen_esp32part.py to conver the CSV to binary again
+            # run gen_esp32part.py to convert the CSV to binary again
             output = subprocess.check_output([sys.executable, '../gen_esp32part.py',
                                               csvpath, binpath], stderr=subprocess.STDOUT)
             self.assertNotIn(b'WARNING', output)
diff --git a/components/pthread/pthread.c b/components/pthread/pthread.c
index 0e73fe86bf1..69f0c440f0d 100644
--- a/components/pthread/pthread.c
+++ b/components/pthread/pthread.c
@@ -916,6 +916,81 @@ int pthread_attr_setdetachstate(pthread_attr_t *attr, int detachstate)
     return EINVAL;
 }
 
+int pthread_getschedparam(pthread_t thread, int *policy, struct sched_param *param)
+{
+    int ret;
+    if (!policy || !param) {
+        return EINVAL;
+    }
+
+    _lock_acquire(&s_threads_lock);
+    TaskHandle_t handle = pthread_find_handle(thread);
+    if (!handle) {
+        ret = ESRCH;
+    } else {
+        *policy = SCHED_OTHER;
+        param->sched_priority = uxTaskPriorityGet(handle);
+        ret = 0;
+    }
+    _lock_release(&s_threads_lock);
+
+    return ret;
+}
+
+static int set_prio(pthread_t thread, int policy, int prio)
+{
+    int ret;
+    if (prio < sched_get_priority_min(policy) || sched_get_priority_max(policy) < prio) {
+        return EINVAL;
+    }
+
+    _lock_acquire(&s_threads_lock);
+    TaskHandle_t handle = pthread_find_handle(thread);
+    if (!handle) {
+        ret = ESRCH;
+    } else {
+        vTaskPrioritySet(handle, prio);
+        ret = 0;
+    }
+    _lock_release(&s_threads_lock);
+
+    return ret;
+}
+
+int pthread_setschedparam(pthread_t thread, int policy, const struct sched_param *param)
+{
+    // the policy does not change anything for the FreeRTOS kernel, ignore it.
+    int ret;
+    if (!param) {
+        return EINVAL;
+    }
+
+    ret = set_prio(thread, policy, param->sched_priority);
+
+    return ret;
+}
+
+int pthread_setschedprio(pthread_t thread, int prio)
+{
+    // the policy does not change anything for the FreeRTOS kernel, ignore it.
+    int policy = SCHED_OTHER;
+    return set_prio(thread, policy, prio);
+}
+
+int sched_get_priority_min(int policy)
+{
+    // the policy does not change anything for the FreeRTOS kernel, ignore it.
+    (void) policy;
+    return tskIDLE_PRIORITY;
+}
+
+int sched_get_priority_max(int policy)
+{
+    // the policy does not change anything for the FreeRTOS kernel, ignore it.
+    (void) policy;
+    return configMAX_PRIORITIES - 1;
+}
+
 /* Hook function to force linking this file */
 void pthread_include_pthread_impl(void)
 {
diff --git a/components/pthread/test_apps/pthread_unity_tests/main/test_pthread.c b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread.c
index 551158bda85..1f2232c3bad 100644
--- a/components/pthread/test_apps/pthread_unity_tests/main/test_pthread.c
+++ b/components/pthread/test_apps/pthread_unity_tests/main/test_pthread.c
@@ -298,3 +298,46 @@ TEST_CASE("pthread mutex trylock timedlock", "[pthread]")
         pthread_mutex_destroy(&mutex);
     }
 }
+
+static volatile bool finish_test;
+
+static void *test_thread(void * arg)
+{
+    while (!finish_test) {
+        vTaskDelay(1);
+    }
+    printf("Thread 0x%"PRIx32" exiting\n", pthread_self());
+    return NULL;
+}
+
+TEST_CASE("pthread set and get sched param", "[pthread]")
+{
+    finish_test = false;
+    pthread_t thread;
+    TEST_ASSERT_EQUAL_INT(0, pthread_create(&thread, NULL, test_thread, NULL));
+
+    int policy;
+    struct sched_param param;
+    TEST_ASSERT_EQUAL_INT(0, pthread_getschedparam(thread, &policy, &param));
+    int orig_prio = param.sched_priority;
+    printf("Origin Priority: %d\n", param.sched_priority);
+    printf("Policy: %d (2=SCHED_RR)\n", policy);
+
+    param.sched_priority += 1;
+    TEST_ASSERT_EQUAL_INT(0, pthread_setschedparam(thread, policy, &param));
+    param.sched_priority += 1;
+    TEST_ASSERT_EQUAL_INT(0, pthread_setschedprio(thread, param.sched_priority));
+
+    TEST_ASSERT_EQUAL_INT(0, pthread_getschedparam(thread, &policy, &param));
+    printf("Priority: %d + 2 = %d\n", orig_prio, param.sched_priority);
+    TEST_ASSERT_EQUAL_INT(orig_prio + 2, param.sched_priority);
+
+    // return priority back
+    TEST_ASSERT_EQUAL_INT(0, pthread_setschedprio(thread, orig_prio));
+    TEST_ASSERT_EQUAL_INT(0, pthread_getschedparam(thread, &policy, &param));
+    TEST_ASSERT_EQUAL_INT(orig_prio, param.sched_priority);
+    printf("Return Priority back to %d, current is %d\n", orig_prio, param.sched_priority);
+    // Wait for the thread to finish 100ms sleep
+    finish_test = true;
+    TEST_ASSERT_EQUAL_INT(0, pthread_join(thread, NULL));
+}
diff --git a/components/sdmmc/sdmmc_common.h b/components/sdmmc/include/esp_private/sdmmc_common.h
similarity index 86%
rename from components/sdmmc/sdmmc_common.h
rename to components/sdmmc/include/esp_private/sdmmc_common.h
index 2753d3d6818..07096e6d6c0 100644
--- a/components/sdmmc/sdmmc_common.h
+++ b/components/sdmmc/include/esp_private/sdmmc_common.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
- * Adaptations to ESP-IDF Copyright (c) 2016-2018 Espressif Systems (Shanghai) PTE LTD
+ * Adaptations to ESP-IDF Copyright (c) 2016-2024 Espressif Systems (Shanghai) PTE LTD
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -18,6 +18,7 @@
 
 #include <string.h>
 #include "esp_log.h"
+#include "esp_check.h"
 #include "esp_heap_caps.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
@@ -26,8 +27,13 @@
 #include "sdmmc_cmd.h"
 #include "sys/param.h"
 #include "soc/soc_memory_layout.h"
+#include "soc/soc_caps.h"
 #include "esp_dma_utils.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #define SDMMC_GO_IDLE_DELAY_MS              20
 #define SDMMC_IO_SEND_OP_COND_DELAY_MS      10
 
@@ -57,6 +63,8 @@
 #define SDMMC_MMC_TRIM_ARG      1
 #define SDMMC_MMC_DISCARD_ARG   3
 
+#define SDMMC_FREQ_SDR104       208000      /*!< MMC 208MHz speed */
+
 /* Functions to send individual commands */
 esp_err_t sdmmc_send_cmd(sdmmc_card_t* card, sdmmc_command_t* cmd);
 esp_err_t sdmmc_send_app_cmd(sdmmc_card_t* card, sdmmc_command_t* cmd);
@@ -77,15 +85,20 @@ esp_err_t sdmmc_send_cmd_send_scr(sdmmc_card_t* card, sdmmc_scr_t *out_scr);
 esp_err_t sdmmc_send_cmd_set_bus_width(sdmmc_card_t* card, int width);
 esp_err_t sdmmc_send_cmd_send_status(sdmmc_card_t* card, uint32_t* out_status);
 esp_err_t sdmmc_send_cmd_crc_on_off(sdmmc_card_t* card, bool crc_enable);
+esp_err_t sdmmc_send_cmd_num_of_written_blocks(sdmmc_card_t* card, size_t* out_num_blocks);
+esp_err_t sdmmc_send_cmd_voltage_switch(sdmmc_card_t* card);
 
 /* Higher level functions */
-esp_err_t sdmmc_enable_hs_mode(sdmmc_card_t* card);
+esp_err_t sdmmc_enter_higher_speed_mode(sdmmc_card_t* card);
 esp_err_t sdmmc_enable_hs_mode_and_check(sdmmc_card_t* card);
 esp_err_t sdmmc_write_sectors_dma(sdmmc_card_t* card, const void* src,
         size_t start_block, size_t block_count, size_t buffer_len);
 esp_err_t sdmmc_read_sectors_dma(sdmmc_card_t* card, void* dst,
         size_t start_block, size_t block_count, size_t buffer_len);
 uint32_t sdmmc_get_erase_timeout_ms(const sdmmc_card_t* card, int arg, size_t erase_size_kb);
+esp_err_t sdmmc_select_driver_strength(sdmmc_card_t *card, sdmmc_driver_strength_t driver_strength);
+esp_err_t sdmmc_select_current_limit(sdmmc_card_t *card, sdmmc_current_limit_t current_limit);
+esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card);
 
 /* SD specific */
 esp_err_t sdmmc_check_scr(sdmmc_card_t* card);
@@ -139,6 +152,10 @@ esp_err_t sdmmc_init_mmc_bus_width(sdmmc_card_t* card);
 esp_err_t sdmmc_init_card_hs_mode(sdmmc_card_t* card);
 esp_err_t sdmmc_init_host_frequency(sdmmc_card_t* card);
 esp_err_t sdmmc_init_mmc_check_ext_csd(sdmmc_card_t* card);
+esp_err_t sdmmc_init_sd_uhs1(sdmmc_card_t* card);
+esp_err_t sdmmc_init_sd_driver_strength(sdmmc_card_t *card);
+esp_err_t sdmmc_init_sd_current_limit(sdmmc_card_t *card);
+esp_err_t sdmmc_init_sd_timing_tuning(sdmmc_card_t *card);
 
 /* Various helper functions */
 static inline bool host_is_spi(const sdmmc_card_t* card)
@@ -154,10 +171,22 @@ static inline uint32_t get_host_ocr(float voltage)
     return SD_OCR_VOL_MASK;
 }
 
+static inline bool sdmmc_ready_for_data(uint32_t status)
+{
+    return (status & MMC_R1_READY_FOR_DATA) && (MMC_R1_CURRENT_STATE_STATUS(status) == MMC_R1_CURRENT_STATE_TRAN);
+}
+
 void sdmmc_flip_byte_order(uint32_t* response, size_t size);
 
 esp_err_t sdmmc_fix_host_flags(sdmmc_card_t* card);
 
+// Use only with SDMMC mode (not SDSPI)
+esp_err_t sdmmc_wait_for_idle(sdmmc_card_t* card, uint32_t status);
+
 //Currently only SDIO support using this buffer. And only 512 block size is supported.
 #define SDMMC_IO_BLOCK_SIZE     512
 esp_err_t sdmmc_allocate_aligned_buf(sdmmc_card_t* card);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/sdmmc/include/sd_protocol_defs.h b/components/sdmmc/include/sd_protocol_defs.h
index a1b6a8ec022..f943789dc80 100644
--- a/components/sdmmc/include/sd_protocol_defs.h
+++ b/components/sdmmc/include/sd_protocol_defs.h
@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: ISC
  *
- * SPDX-FileContributor: 2016-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileContributor: 2016-2024 Espressif Systems (Shanghai) CO LTD
  */
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
@@ -46,6 +46,7 @@ extern "C" {
 #define MMC_SET_BLOCKLEN                16      /* R1 */
 #define MMC_READ_BLOCK_SINGLE           17      /* R1 */
 #define MMC_READ_BLOCK_MULTIPLE         18      /* R1 */
+#define MMC_SEND_TUNING_BLOCK           19      /* R1 */
 #define MMC_WRITE_DAT_UNTIL_STOP        20      /* R1 */
 #define MMC_SET_BLOCK_COUNT             23      /* R1 */
 #define MMC_WRITE_BLOCK_SINGLE          24      /* R1 */
@@ -59,6 +60,7 @@ extern "C" {
 #define SD_SEND_RELATIVE_ADDR           3       /* R6 */
 #define SD_SEND_SWITCH_FUNC             6       /* R1 */
 #define SD_SEND_IF_COND                 8       /* R7 */
+#define SD_SWITCH_VOLTAGE               11      /* R1 */
 #define SD_ERASE_GROUP_START            32      /* R1 */
 #define SD_ERASE_GROUP_END              33      /* R1 */
 #define SD_READ_OCR                     58      /* R3 */
@@ -67,6 +69,7 @@ extern "C" {
 /* SD application commands */                   /* response type */
 #define SD_APP_SET_BUS_WIDTH            6       /* R1 */
 #define SD_APP_SD_STATUS                13      /* R2 */
+#define SD_APP_SEND_NUM_WR_BLOCKS       22      /* R1 */
 #define SD_APP_OP_COND                  41      /* R3 */
 #define SD_APP_SEND_SCR                 51      /* R1 */
 
@@ -98,8 +101,20 @@ extern "C" {
 #define MMC_OCR_2_0V_2_1V               (1<<8)
 #define MMC_OCR_1_65V_1_95V             (1<<7)
 
-#define SD_OCR_SDHC_CAP                 (1<<30)
-#define SD_OCR_VOL_MASK                 0xFF8000 /* bits 23:15 */
+#define SD_OCR_CARD_READY               MMC_OCR_MEM_READY   /* bit-31: power-up status */
+#define SD_OCR_SDHC_CAP                 (1<<30)             /* HCS bit */
+#define SD_OCR_XPC                      (1<<28)             /* SDXC Power Control (bit 28) */
+#define SD_OCR_S18_RA                   (1<<24)             /* S18R/A bit: 1.8V voltage support, UHS-I only */
+#define SD_OCR_VOL_MASK                 0xFF8000            /* SD OCR voltage bits 23:15 */
+#define SD_OCR_3_5V_3_6V                MMC_OCR_3_5V_3_6V   /* bit-23 */
+#define SD_OCR_3_4V_3_5V                MMC_OCR_3_4V_3_5V   /* bit-22 */
+#define SD_OCR_3_3V_3_4V                MMC_OCR_3_3V_3_4V   /* ...    */
+#define SD_OCR_3_2V_3_3V                MMC_OCR_3_2V_3_3V
+#define SD_OCR_3_1V_3_2V                MMC_OCR_3_1V_3_2V
+#define SD_OCR_3_0V_3_1V                MMC_OCR_3_0V_3_1V
+#define SD_OCR_2_9V_3_0V                MMC_OCR_2_9V_3_0V
+#define SD_OCR_2_8V_2_9V                MMC_OCR_2_8V_2_9V   /* ...    */
+#define SD_OCR_2_7V_2_8V                MMC_OCR_2_7V_2_8V   /* bit-15 */
 
 /* SD mode R1 response type bits */
 #define MMC_R1_READY_FOR_DATA           (1<<8)  /* ready for next transfer */
@@ -108,6 +123,7 @@ extern "C" {
 #define MMC_R1_CURRENT_STATE_POS        (9)
 #define MMC_R1_CURRENT_STATE_MASK       (0x1E00)/* card current state */
 #define MMC_R1_CURRENT_STATE_TRAN       (4)
+#define MMC_R1_CURRENT_STATE_STATUS(status)     (((status) & MMC_R1_CURRENT_STATE_MASK) >> MMC_R1_CURRENT_STATE_POS)
 
 /* SPI mode R1 response type bits */
 #define SD_SPI_R1_IDLE_STATE            (1<<0)
@@ -246,6 +262,7 @@ extern "C" {
 #define MMC_CSD_CAPACITY(resp)          ((MMC_CSD_C_SIZE((resp))+1) << \
                                          (MMC_CSD_C_SIZE_MULT((resp))+2))
 #define MMC_CSD_C_SIZE_MULT(resp)       MMC_RSP_BITS((resp), 47, 3)
+#define MMC_CSD_WRITE_BL_PARTIAL(resp)  MMC_RSP_BITS((resp), 21, 1)
 
 /* MMC v1 R2 response (CID) */
 #define MMC_CID_MID_V1(resp)            MMC_RSP_BITS((resp), 104, 24)
@@ -289,6 +306,8 @@ extern "C" {
 #define SD_CSD_SPEED(resp)              MMC_RSP_BITS((resp), 96, 8)
 #define  SD_CSD_SPEED_25_MHZ            0x32
 #define  SD_CSD_SPEED_50_MHZ            0x5a
+#define  SD_CSD_SPEED_100_MHZ           0xb
+#define  SD_CSD_SPEED_200_MHZ           0x2b
 #define SD_CSD_CCC(resp)                MMC_RSP_BITS((resp), 84, 12)
 #define  SD_CSD_CCC_BASIC               (1 << 0)        /* basic */
 #define  SD_CSD_CCC_BR                  (1 << 2)        /* block read */
@@ -402,6 +421,14 @@ extern "C" {
 #define SD_SFUNC_FUNC_MAX       15
 
 #define SD_ACCESS_MODE          1       /* Function group 1, Access Mode */
+#define SD_COMMAND_SYSTEM       2       /* Function group 1, Command System */
+#define SD_DRIVER_STRENGTH      3       /* Function group 1, Driver Strength */
+#define SD_CURRENT_LIMIT        4       /* Function group 1, Current Limit */
+
+#define SD_DRIVER_STRENGTH_B    0       /* Type B */
+#define SD_DRIVER_STRENGTH_A    1       /* Type A */
+#define SD_DRIVER_STRENGTH_C    2       /* Type C */
+#define SD_DRIVER_STRENGTH_D    3       /* Type D */
 
 #define SD_ACCESS_MODE_SDR12    0       /* 25 MHz clock */
 #define SD_ACCESS_MODE_SDR25    1       /* 50 MHz clock */
@@ -424,7 +451,7 @@ extern "C" {
  *
  * 67 45 23 01 ef cd ab 89
  *
- * MMC_RSP_BITS will extact bits as follows:
+ * MMC_RSP_BITS will extract bits as follows:
  *
  * start=0  len=4   -> result=0x00000007
  * start=0  len=12  -> result=0x00000567
diff --git a/components/sdmmc/include/sd_protocol_types.h b/components/sdmmc/include/sd_protocol_types.h
index effe3b4a0fd..70cdf76d122 100644
--- a/components/sdmmc/include/sd_protocol_types.h
+++ b/components/sdmmc/include/sd_protocol_types.h
@@ -149,12 +149,18 @@ typedef struct {
     /** @endcond */
     esp_err_t error;            /*!< error returned from transfer */
     uint32_t timeout_ms;        /*!< response timeout, in milliseconds */
+    esp_err_t (*volt_switch_cb)(void*, int); /*!< callback to be called during CMD11 to switch voltage */
+    void* volt_switch_cb_arg;   /*!< argument to be passed to the CMD11 callback */
 } sdmmc_command_t;
 
 /**
  * SD/MMC Host clock timing delay phases
  *
- * This will only take effect when the host works in SDMMC_FREQ_HIGHSPEED or SDMMC_FREQ_52M.
+ * This will only take effect when the host works in
+ * - SDMMC_FREQ_HIGHSPEED
+ * - SDMMC_FREQ_52M
+ * - SDR50
+ * - DDR50
  * Driver will print out how long the delay is, in picosecond (ps).
  */
 typedef enum {
@@ -162,8 +168,29 @@ typedef enum {
     SDMMC_DELAY_PHASE_1,            /*!< Delay phase 1 */
     SDMMC_DELAY_PHASE_2,            /*!< Delay phase 2 */
     SDMMC_DELAY_PHASE_3,            /*!< Delay phase 3 */
+    SDMMC_DELAY_PHASE_AUTO,         /*!< Auto detect phase, only valid for UHS-I mode */
 } sdmmc_delay_phase_t;
 
+/**
+ * @brief SD/MMC Driver Strength
+ */
+typedef enum {
+    SDMMC_DRIVER_STRENGTH_B,         /*!< Type B */
+    SDMMC_DRIVER_STRENGTH_A,         /*!< Type A */
+    SDMMC_DRIVER_STRENGTH_C,         /*!< Type C */
+    SDMMC_DRIVER_STRENGTH_D,         /*!< Type D */
+} sdmmc_driver_strength_t;
+
+/**
+ * @brief SD/MMC Current Limit
+ */
+typedef enum {
+    SDMMC_CURRENT_LIMIT_200MA,       /*!< 200 mA */
+    SDMMC_CURRENT_LIMIT_400MA,       /*!< 400 mA */
+    SDMMC_CURRENT_LIMIT_600MA,       /*!< 600 mA */
+    SDMMC_CURRENT_LIMIT_800MA,       /*!< 800 mA */
+} sdmmc_current_limit_t;
+
 /**
  * SD/MMC Host description
  *
@@ -190,7 +217,11 @@ typedef struct {
 #define SDMMC_FREQ_PROBING      400         /*!< SD/MMC probing speed */
 #define SDMMC_FREQ_52M          52000       /*!< MMC 52MHz speed */
 #define SDMMC_FREQ_26M          26000       /*!< MMC 26MHz speed */
+#define SDMMC_FREQ_DDR50        50000       /*!< MMC 50MHz speed */
+#define SDMMC_FREQ_SDR50        100000      /*!< MMC 100MHz speed */
     float io_voltage;           /*!< I/O voltage used by the controller (voltage switching is not supported) */
+    sdmmc_driver_strength_t driver_strength; /*!< Driver Strength */
+    sdmmc_current_limit_t current_limit;     /*!< Current Limit */
     esp_err_t (*init)(void);    /*!< Host function to initialize the driver */
     esp_err_t (*set_bus_width)(int slot, size_t width);    /*!< host function to set bus width */
     size_t (*get_bus_width)(int slot); /*!< host function to get bus width */
@@ -211,6 +242,7 @@ typedef struct {
     void* dma_aligned_buffer; /*!< Leave it NULL. Reserved for cache aligned buffers for SDIO mode */
     sd_pwr_ctrl_handle_t pwr_ctrl_handle;  /*!< Power control handle */
     esp_err_t (*get_dma_info)(int slot, esp_dma_mem_info_t *dma_mem_info); /*!< host function to dma memory information*/
+    esp_err_t (*is_slot_set_to_uhs1)(int slot, bool *is_uhs1); /*!< host slot is set to uhs1 or not*/
 } sdmmc_host_t;
 
 /**
@@ -229,7 +261,7 @@ typedef struct {
     sdmmc_ssr_t ssr;            /*!< decoded SSR (SD Status Register) value */
     sdmmc_ext_csd_t ext_csd;    /*!< decoded EXT_CSD (Extended Card Specific Data) register value */
     uint16_t rca;               /*!< RCA (Relative Card Address) */
-    uint16_t max_freq_khz;      /*!< Maximum frequency, in kHz, supported by the card */
+    uint32_t max_freq_khz;      /*!< Maximum frequency, in kHz, supported by the card */
     int real_freq_khz;          /*!< Real working frequency, in kHz, configured on the host controller */
     uint32_t is_mem : 1;        /*!< Bit indicates if the card is a memory card */
     uint32_t is_sdio : 1;       /*!< Bit indicates if the card is an IO card */
@@ -237,7 +269,8 @@ typedef struct {
     uint32_t num_io_functions : 3;  /*!< If is_sdio is 1, contains the number of IO functions on the card */
     uint32_t log_bus_width : 2; /*!< log2(bus width supported by card) */
     uint32_t is_ddr : 1;        /*!< Card supports DDR mode */
-    uint32_t reserved : 23;     /*!< Reserved for future expansion */
+    uint32_t is_uhs1 : 1;       /*!< Card supports UHS-1 mode */
+    uint32_t reserved : 22;     /*!< Reserved for future expansion */
 } sdmmc_card_t;
 
 /**
diff --git a/components/sdmmc/sdmmc_cmd.c b/components/sdmmc/sdmmc_cmd.c
index fb18a9d6962..71f23ec756b 100644
--- a/components/sdmmc/sdmmc_cmd.c
+++ b/components/sdmmc/sdmmc_cmd.c
@@ -5,8 +5,7 @@
  */
 
 #include <inttypes.h>
-#include "esp_timer.h"
-#include "sdmmc_common.h"
+#include "esp_private/sdmmc_common.h"
 
 static const char* TAG = "sdmmc_cmd";
 
@@ -264,7 +263,22 @@ esp_err_t sdmmc_send_cmd_set_relative_addr(sdmmc_card_t* card, uint16_t* out_rca
     if (err != ESP_OK) {
         return err;
     }
-    *out_rca = (card->is_mmc) ? mmc_rca : SD_R6_RCA(cmd.response);
+
+    if (card->is_mmc) {
+        *out_rca = mmc_rca;
+    } else {
+        uint16_t response_rca = SD_R6_RCA(cmd.response);
+        if (response_rca == 0) {
+            // Try to get another RCA value if RCA value in the previous response was 0x0000
+            // The value 0x0000 is reserved to set all cards into the Stand-by State with CMD7
+            err = sdmmc_send_cmd(card, &cmd);
+            if (err != ESP_OK) {
+                return err;
+            }
+            response_rca = SD_R6_RCA(cmd.response);
+        }
+        *out_rca = response_rca;
+    }
     return ESP_OK;
 }
 
@@ -394,6 +408,43 @@ esp_err_t sdmmc_send_cmd_send_status(sdmmc_card_t* card, uint32_t* out_status)
     return ESP_OK;
 }
 
+esp_err_t sdmmc_send_cmd_num_of_written_blocks(sdmmc_card_t* card, size_t* out_num_blocks)
+{
+    size_t datalen = sizeof(uint32_t);
+    esp_err_t err = ESP_OK;
+    void* buf = NULL;
+    esp_dma_mem_info_t dma_mem_info;
+    card->host.get_dma_info(card->host.slot, &dma_mem_info);
+    size_t actual_size = 0;
+    err = esp_dma_capable_malloc(datalen, &dma_mem_info, &buf, &actual_size);
+    if (err != ESP_OK) {
+        return err;
+    }
+
+    sdmmc_command_t cmd = {
+        .data = buf,
+        .datalen = datalen,
+        .buflen = actual_size,
+        .blklen = datalen,
+        .flags = SCF_CMD_ADTC | SCF_RSP_R1 | SCF_CMD_READ,
+        .opcode = SD_APP_SEND_NUM_WR_BLOCKS
+    };
+
+    err = sdmmc_send_app_cmd(card, &cmd);
+    if (err != ESP_OK) {
+        free(buf);
+        ESP_LOGE(TAG, "%s: sdmmc_send_app_cmd returned 0x%x, failed to get number of written write blocks", __func__, err);
+        return err;
+    }
+
+    size_t result = __builtin_bswap32(*(uint32_t*)buf);
+    if (out_num_blocks) {
+        *out_num_blocks = result;
+    }
+    free(buf);
+    return err;
+}
+
 esp_err_t sdmmc_write_sectors(sdmmc_card_t* card, const void* src,
         size_t start_block, size_t block_count)
 {
@@ -469,36 +520,46 @@ esp_err_t sdmmc_write_sectors_dma(sdmmc_card_t* card, const void* src,
     } else {
         cmd.arg = start_block * block_size;
     }
+
+    uint32_t status = 0;
     esp_err_t err = sdmmc_send_cmd(card, &cmd);
+    esp_err_t err_cmd13 = sdmmc_send_cmd_send_status(card, &status);
+
     if (err != ESP_OK) {
-        ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x", __func__, err);
+        if (cmd.opcode == MMC_WRITE_BLOCK_MULTIPLE) {
+            if (!host_is_spi(card)) {
+                sdmmc_wait_for_idle(card, status); // wait for the card to be idle (in transfer state)
+            } else {
+                vTaskDelay(1); // when the host is in spi mode
+            }
+            size_t successfully_written_blocks = 0;
+            if (sdmmc_send_cmd_num_of_written_blocks(card, &successfully_written_blocks) == ESP_OK) {
+                ESP_LOGD(TAG, "%s: successfully wrote %zu blocks out of %zu", __func__, successfully_written_blocks, block_count);
+            } else {
+                ESP_LOGE(TAG, "%s: sdmmc_send_cmd_num_of_written_blocks returned 0x%x", __func__, err);
+            }
+        }
+        if (err_cmd13 == ESP_OK) {
+            ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x, status 0x%" PRIx32, __func__, err, status);
+        } else {
+            ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x, failed to get status (0x%x)", __func__, err, err_cmd13);
+        }
         return err;
     }
-    uint32_t status = 0;
-    size_t count = 0;
-    int64_t yield_delay_us = 100 * 1000; // initially 100ms
-    int64_t t0 = esp_timer_get_time();
-    int64_t t1 = 0;
+
     /* SD mode: wait for the card to become idle based on R1 status */
-    while (!host_is_spi(card) && !(status & MMC_R1_READY_FOR_DATA)) {
-        t1 = esp_timer_get_time();
-        if (t1 - t0 > SDMMC_READY_FOR_DATA_TIMEOUT_US) {
-            ESP_LOGE(TAG, "write sectors dma - timeout");
-            return ESP_ERR_TIMEOUT;
-        }
-        if (t1 - t0 > yield_delay_us) {
-            yield_delay_us *= 2;
-            vTaskDelay(1);
-        }
-        err = sdmmc_send_cmd_send_status(card, &status);
-        if (err != ESP_OK) {
-            ESP_LOGE(TAG, "%s: sdmmc_send_cmd_send_status returned 0x%x", __func__, err);
-            return err;
-        }
-        if (++count % 16 == 0) {
-            ESP_LOGV(TAG, "waiting for card to become ready (%" PRIu32 ")", (uint32_t) count);
+    if (!host_is_spi(card)) {
+        switch (sdmmc_wait_for_idle(card, status)) {
+            case ESP_OK:
+                break;
+            case ESP_ERR_TIMEOUT:
+                ESP_LOGE(TAG, "%s: sdmmc_wait_for_idle timeout", __func__);
+                return ESP_ERR_TIMEOUT;
+            default:
+                return err;
         }
     }
+
     /* SPI mode: although card busy indication is based on the busy token,
      * SD spec recommends that the host checks the results of programming by sending
      * SEND_STATUS command. Some of the conditions reported in SEND_STATUS are not
@@ -591,34 +652,30 @@ esp_err_t sdmmc_read_sectors_dma(sdmmc_card_t* card, void* dst,
     } else {
         cmd.arg = start_block * block_size;
     }
+
+    uint32_t status = 0;
     esp_err_t err = sdmmc_send_cmd(card, &cmd);
+    esp_err_t err_cmd13 = sdmmc_send_cmd_send_status(card, &status);
+
     if (err != ESP_OK) {
-        ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x", __func__, err);
+        if (err_cmd13 == ESP_OK) {
+            ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x, status 0x%" PRIx32, __func__, err, status);
+        } else {
+            ESP_LOGE(TAG, "%s: sdmmc_send_cmd returned 0x%x, failed to get status (0x%x)", __func__, err, err_cmd13);
+        }
         return err;
     }
-    uint32_t status = 0;
-    size_t count = 0;
-    int64_t yield_delay_us = 100 * 1000; // initially 100ms
-    int64_t t0 = esp_timer_get_time();
-    int64_t t1 = 0;
+
     /* SD mode: wait for the card to become idle based on R1 status */
-    while (!host_is_spi(card) && !(status & MMC_R1_READY_FOR_DATA)) {
-        t1 = esp_timer_get_time();
-        if (t1 - t0 > SDMMC_READY_FOR_DATA_TIMEOUT_US) {
-            ESP_LOGE(TAG, "read sectors dma - timeout");
-            return ESP_ERR_TIMEOUT;
-        }
-        if (t1 - t0 > yield_delay_us) {
-            yield_delay_us *= 2;
-            vTaskDelay(1);
-        }
-        err = sdmmc_send_cmd_send_status(card, &status);
-        if (err != ESP_OK) {
-            ESP_LOGE(TAG, "%s: sdmmc_send_cmd_send_status returned 0x%x", __func__, err);
-            return err;
-        }
-        if (++count % 16 == 0) {
-            ESP_LOGV(TAG, "waiting for card to become ready (%d)", count);
+    if (!host_is_spi(card)) {
+        switch (sdmmc_wait_for_idle(card, status)) {
+            case ESP_OK:
+                break;
+            case ESP_ERR_TIMEOUT:
+                ESP_LOGE(TAG, "%s: sdmmc_wait_for_idle timeout", __func__);
+                return ESP_ERR_TIMEOUT;
+            default:
+                return err;
         }
     }
     return ESP_OK;
diff --git a/components/sdmmc/sdmmc_common.c b/components/sdmmc/sdmmc_common.c
index 8135e593e24..169a95dd9b6 100644
--- a/components/sdmmc/sdmmc_common.c
+++ b/components/sdmmc/sdmmc_common.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
- * Adaptations to ESP-IDF Copyright (c) 2016-2018 Espressif Systems (Shanghai) PTE LTD
+ * Adaptations to ESP-IDF Copyright (c) 2016-2024 Espressif Systems (Shanghai) PTE LTD
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,7 +16,9 @@
  */
 
 #include <inttypes.h>
-#include "sdmmc_common.h"
+#include "esp_log.h"
+#include "esp_timer.h"
+#include "esp_private/sdmmc_common.h"
 
 static const char* TAG = "sdmmc_common";
 
@@ -42,6 +44,16 @@ esp_err_t sdmmc_init_ocr(sdmmc_card_t* card)
         acmd41_arg |= SD_OCR_SDHC_CAP;
     }
 
+    bool to_set_to_uhs1 = false;
+    if (card->host.is_slot_set_to_uhs1) {
+        ESP_RETURN_ON_ERROR(card->host.is_slot_set_to_uhs1(card->host.slot, &to_set_to_uhs1), TAG, "failed to get slot info");
+    }
+    if (to_set_to_uhs1) {
+        acmd41_arg |= SD_OCR_S18_RA;
+        acmd41_arg |= SD_OCR_XPC;
+    }
+    ESP_LOGV(TAG, "%s: acmd41_arg=0x%08" PRIx32, __func__, card->ocr);
+
     /* Send SEND_OP_COND (ACMD41) command to the card until it becomes ready. */
     err = sdmmc_send_cmd_send_op_cond(card, acmd41_arg, &card->ocr);
 
@@ -182,6 +194,21 @@ esp_err_t sdmmc_init_card_hs_mode(sdmmc_card_t* card)
     return ESP_OK;
 }
 
+esp_err_t sdmmc_init_sd_driver_strength(sdmmc_card_t *card)
+{
+    return sdmmc_select_driver_strength(card, card->host.driver_strength);
+}
+
+esp_err_t sdmmc_init_sd_current_limit(sdmmc_card_t *card)
+{
+    return sdmmc_select_current_limit(card, card->host.current_limit);
+}
+
+esp_err_t sdmmc_init_sd_timing_tuning(sdmmc_card_t *card)
+{
+    return sdmmc_do_timing_tuning(card);
+}
+
 esp_err_t sdmmc_init_host_bus_width(sdmmc_card_t* card)
 {
     int bus_width = 1;
@@ -209,6 +236,14 @@ esp_err_t sdmmc_init_host_frequency(sdmmc_card_t* card)
     esp_err_t err;
     assert(card->max_freq_khz <= card->host.max_freq_khz);
 
+#if !SOC_SDMMC_UHS_I_SUPPORTED
+    ESP_RETURN_ON_FALSE(card->host.input_delay_phase != SDMMC_DELAY_PHASE_AUTO, ESP_ERR_INVALID_ARG, TAG, "auto tuning not supported");
+#endif
+
+    if (card->host.input_delay_phase == SDMMC_DELAY_PHASE_AUTO) {
+        ESP_RETURN_ON_FALSE((card->host.max_freq_khz == SDMMC_FREQ_SDR50 || card->host.max_freq_khz == SDMMC_FREQ_SDR104), ESP_ERR_INVALID_ARG, TAG, "auto tuning only supported for SDR50 / SDR104");
+    }
+
     if (card->max_freq_khz > SDMMC_FREQ_PROBING) {
         err = (*card->host.set_card_clk)(card->host.slot, card->max_freq_khz);
         if (err != ESP_OK) {
@@ -278,7 +313,15 @@ void sdmmc_card_print_info(FILE* stream, const sdmmc_card_t* card)
         type = "MMC";
         print_csd = true;
     } else {
-        type = (card->ocr & SD_OCR_SDHC_CAP) ? "SDHC/SDXC" : "SDSC";
+        if ((card->ocr & SD_OCR_SDHC_CAP) == 0) {
+            type = "SDSC";
+        } else {
+            if (card->ocr & SD_OCR_S18_RA) {
+                type = "SDHC/SDXC (UHS-I)";
+            } else {
+                type = "SDHC";
+            }
+        }
         print_csd = true;
     }
     fprintf(stream, "Type: %s\n", type);
@@ -332,6 +375,19 @@ esp_err_t sdmmc_fix_host_flags(sdmmc_card_t* card)
             card->host.flags |= width_4bit;
         }
     }
+
+#if !SOC_SDMMC_UHS_I_SUPPORTED
+    if ((card->host.max_freq_khz == SDMMC_FREQ_SDR50) ||
+        (card->host.max_freq_khz == SDMMC_FREQ_DDR50) ||
+        (card->host.max_freq_khz == SDMMC_FREQ_SDR104)) {
+        ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "UHS-I is not supported");
+    }
+#else
+    if (card->host.max_freq_khz == SDMMC_FREQ_DDR50) {
+        ESP_RETURN_ON_FALSE(((card->host.flags & SDMMC_HOST_FLAG_DDR) != 0), ESP_ERR_INVALID_ARG, TAG, "DDR is not selected");
+    }
+#endif
+
     return ESP_OK;
 }
 
@@ -361,3 +417,33 @@ uint32_t sdmmc_get_erase_timeout_ms(const sdmmc_card_t* card, int arg, size_t er
         return sdmmc_sd_get_erase_timeout_ms(card, arg, erase_size_kb);
     }
 }
+
+esp_err_t sdmmc_wait_for_idle(sdmmc_card_t* card, uint32_t status)
+{
+    assert(!host_is_spi(card));
+    esp_err_t err = ESP_OK;
+    size_t count = 0;
+    int64_t yield_delay_us = 100 * 1000; // initially 100ms
+    int64_t t0 = esp_timer_get_time();
+    int64_t t1 = 0;
+    /* SD mode: wait for the card to become idle based on R1 status */
+    while (!sdmmc_ready_for_data(status)) {
+        t1 = esp_timer_get_time();
+        if (t1 - t0 > SDMMC_READY_FOR_DATA_TIMEOUT_US) {
+            return ESP_ERR_TIMEOUT;
+        }
+        if (t1 - t0 > yield_delay_us) {
+            yield_delay_us *= 2;
+            vTaskDelay(1);
+        }
+        err = sdmmc_send_cmd_send_status(card, &status);
+        if (err != ESP_OK) {
+            ESP_LOGE(TAG, "%s: sdmmc_send_cmd_send_status returned 0x%x", __func__, err);
+            return err;
+        }
+        if (++count % 16 == 0) {
+            ESP_LOGV(TAG, "waiting for card to become ready (%" PRIu32 ")", (uint32_t) count);
+        }
+    }
+    return err;
+}
diff --git a/components/sdmmc/sdmmc_init.c b/components/sdmmc/sdmmc_init.c
index 41d1ac6fc02..3e62209d368 100644
--- a/components/sdmmc/sdmmc_init.c
+++ b/components/sdmmc/sdmmc_init.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
- * Adaptations to ESP-IDF Copyright (c) 2016-2018 Espressif Systems (Shanghai) PTE LTD
+ * Adaptations to ESP-IDF Copyright (c) 2016-2024 Espressif Systems (Shanghai) PTE LTD
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -15,7 +15,7 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include "sdmmc_common.h"
+#include "esp_private/sdmmc_common.h"
 #include "sd_pwr_ctrl_by_on_chip_ldo.h"
 #include "sd_pwr_ctrl.h"
 
@@ -95,6 +95,11 @@ esp_err_t sdmmc_card_init(const sdmmc_host_t* config, sdmmc_card_t* card)
     ESP_LOGD(TAG, "%s: card type is %s", __func__,
             is_sdio ? "SDIO" : is_mmc ? "MMC" : "SD");
 
+    /* switch to 1.8V if supported (UHS-I) */
+    bool is_uhs1 = is_sdmem && (card->ocr & SD_OCR_S18_RA) && (card->ocr & SD_OCR_SDHC_CAP);
+    ESP_LOGV(TAG, "is_uhs1: %d", is_uhs1);
+    SDMMC_INIT_STEP(is_uhs1, sdmmc_init_sd_uhs1);
+
     /* Read the contents of CID register*/
     SDMMC_INIT_STEP(is_mem, sdmmc_init_cid);
 
@@ -142,12 +147,21 @@ esp_err_t sdmmc_card_init(const sdmmc_host_t* config, sdmmc_card_t* card)
         SDMMC_INIT_STEP(always, sdmmc_init_host_bus_width);
     }
 
+    /* Driver Strength */
+    SDMMC_INIT_STEP(is_uhs1, sdmmc_init_sd_driver_strength);
+
+    /* Current Limit */
+    SDMMC_INIT_STEP(is_uhs1, sdmmc_init_sd_current_limit);
+
     /* SD card: read SD Status register */
     SDMMC_INIT_STEP(is_sdmem, sdmmc_init_sd_ssr);
 
     /* Switch to the host to use card->max_freq_khz frequency. */
     SDMMC_INIT_STEP(always, sdmmc_init_host_frequency);
 
+    /* Timing tuning */
+    SDMMC_INIT_STEP(is_uhs1, sdmmc_init_sd_timing_tuning);
+
     /* Sanity check after switching the bus mode and frequency */
     SDMMC_INIT_STEP(is_sdmem, sdmmc_check_scr);
     /* Sanity check after eMMC switch to HS mode */
diff --git a/components/sdmmc/sdmmc_io.c b/components/sdmmc/sdmmc_io.c
index 970657dfe19..64492f2da3f 100644
--- a/components/sdmmc/sdmmc_io.c
+++ b/components/sdmmc/sdmmc_io.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
- * Adaptations to ESP-IDF Copyright (c) 2016-2018 Espressif Systems (Shanghai) PTE LTD
+ * Adaptations to ESP-IDF Copyright (c) 2016-2024 Espressif Systems (Shanghai) PTE LTD
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,7 +16,7 @@
  */
 
 #include <inttypes.h>
-#include "sdmmc_common.h"
+#include "esp_private/sdmmc_common.h"
 #include "esp_attr.h"
 #include "esp_compiler.h"
 
diff --git a/components/sdmmc/sdmmc_mmc.c b/components/sdmmc/sdmmc_mmc.c
index e3f44bc865b..a4fed8a4c97 100644
--- a/components/sdmmc/sdmmc_mmc.c
+++ b/components/sdmmc/sdmmc_mmc.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
- * Adaptations to ESP-IDF Copyright (c) 2016-2018 Espressif Systems (Shanghai) PTE LTD
+ * Adaptations to ESP-IDF Copyright (c) 2016-2024 Espressif Systems (Shanghai) PTE LTD
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -17,7 +17,7 @@
 
 #include <inttypes.h>
 #include <unistd.h>
-#include "sdmmc_common.h"
+#include "esp_private/sdmmc_common.h"
 
 static const char* TAG = "sdmmc_mmc";
 
@@ -69,7 +69,7 @@ esp_err_t sdmmc_init_mmc_read_ext_csd(sdmmc_card_t* card)
     }
     /* For MMC cards, use speed value from EXT_CSD */
     card->csd.tr_speed = card->max_freq_khz * 1000;
-    ESP_LOGD(TAG, "MMC card type %d, max_freq_khz=%d, is_ddr=%d", card_type, card->max_freq_khz, card->is_ddr);
+    ESP_LOGD(TAG, "MMC card type %d, max_freq_khz=%"PRId32", is_ddr=%d", card_type, card->max_freq_khz, card->is_ddr);
     card->max_freq_khz = MIN(card->max_freq_khz, card->host.max_freq_khz);
 
     if (card->host.flags & SDMMC_HOST_FLAG_8BIT) {
@@ -272,8 +272,8 @@ esp_err_t sdmmc_init_mmc_check_ext_csd(sdmmc_card_t* card)
         ESP_LOGE(TAG, "%s: send_status returned 0x%x", __func__, err);
         goto out;
     }
-    status = ((status & MMC_R1_CURRENT_STATE_MASK) >> MMC_R1_CURRENT_STATE_POS);
-    if (status != MMC_R1_CURRENT_STATE_TRAN) {
+
+    if (MMC_R1_CURRENT_STATE_STATUS(status) != MMC_R1_CURRENT_STATE_TRAN) {
         ESP_LOGE(TAG, "%s: card not in transfer state", __func__);
         err = ESP_ERR_INVALID_STATE;
         goto out;
diff --git a/components/sdmmc/sdmmc_sd.c b/components/sdmmc/sdmmc_sd.c
index 3fbebc67cbf..45b13beb6ed 100644
--- a/components/sdmmc/sdmmc_sd.c
+++ b/components/sdmmc/sdmmc_sd.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
- * Adaptations to ESP-IDF Copyright (c) 2016-2018 Espressif Systems (Shanghai) PTE LTD
+ * Adaptations to ESP-IDF Copyright (c) 2016-2024 Espressif Systems (Shanghai) PTE LTD
  *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
@@ -16,9 +16,10 @@
  */
 
 #include <inttypes.h>
+#include "esp_check.h"
 #include "esp_timer.h"
 #include "esp_cache.h"
-#include "sdmmc_common.h"
+#include "esp_private/sdmmc_common.h"
 
 static const char* TAG = "sdmmc_sd";
 
@@ -228,7 +229,7 @@ esp_err_t sdmmc_send_cmd_switch_func(sdmmc_card_t* card,
     return ESP_OK;
 }
 
-esp_err_t sdmmc_enable_hs_mode(sdmmc_card_t* card)
+esp_err_t sdmmc_enter_higher_speed_mode(sdmmc_card_t* card)
 {
     /* This will determine if the card supports SWITCH_FUNC command,
      * and high speed mode. If the cards supports both, this will enable
@@ -255,14 +256,62 @@ esp_err_t sdmmc_enable_hs_mode(sdmmc_card_t* card)
         goto out;
     }
     uint32_t supported_mask = SD_SFUNC_SUPPORTED(response->data, 1);
-    if ((supported_mask & BIT(SD_ACCESS_MODE_SDR25)) == 0) {
-        err = ESP_ERR_NOT_SUPPORTED;
-        goto out;
-    }
-    err = sdmmc_send_cmd_switch_func(card, 1, SD_ACCESS_MODE, SD_ACCESS_MODE_SDR25, response);
-    if (err != ESP_OK) {
-        ESP_LOGD(TAG, "%s: sdmmc_send_cmd_switch_func (2) returned 0x%x", __func__, err);
-        goto out;
+    ESP_LOGV(TAG, "%s: access mode supported_mask: 0x%"PRIx32, __func__, supported_mask);
+
+    if (((card->host.flags & SDMMC_HOST_FLAG_DDR) != 0) && (card->is_uhs1 == 1)) {
+        //UHS-I DDR50
+        ESP_LOGV(TAG, "%s: to switch to DDR50", __func__);
+        if ((supported_mask & BIT(SD_ACCESS_MODE_DDR50)) == 0) {
+            err = ESP_ERR_NOT_SUPPORTED;
+            goto out;
+        }
+        err = sdmmc_send_cmd_switch_func(card, 1, SD_ACCESS_MODE, SD_ACCESS_MODE_DDR50, response);
+        if (err != ESP_OK) {
+            ESP_LOGD(TAG, "%s: sdmmc_send_cmd_switch_func (2) returned 0x%x", __func__, err);
+            goto out;
+        }
+
+        card->is_ddr = 1;
+        err = (*card->host.set_bus_ddr_mode)(card->host.slot, true);
+        if (err != ESP_OK) {
+            ESP_LOGE(TAG, "%s: failed to switch bus to DDR mode (0x%x)", __func__, err);
+            return err;
+        }
+    } else if (card->host.max_freq_khz == SDMMC_FREQ_SDR104) {
+        //UHS-I SDR104
+        ESP_LOGV(TAG, "%s: to switch to SDR104", __func__);
+        if ((supported_mask & BIT(SD_ACCESS_MODE_SDR104)) == 0) {
+            err = ESP_ERR_NOT_SUPPORTED;
+            goto out;
+        }
+        err = sdmmc_send_cmd_switch_func(card, 1, SD_ACCESS_MODE, SD_ACCESS_MODE_SDR104, response);
+        if (err != ESP_OK) {
+            ESP_LOGD(TAG, "%s: sdmmc_send_cmd_switch_func (2) returned 0x%x", __func__, err);
+            goto out;
+        }
+    } else if (card->host.max_freq_khz == SDMMC_FREQ_SDR50) {
+        //UHS-I SDR50
+        ESP_LOGV(TAG, "%s: to switch to SDR50", __func__);
+        if ((supported_mask & BIT(SD_ACCESS_MODE_SDR50)) == 0) {
+            err = ESP_ERR_NOT_SUPPORTED;
+            goto out;
+        }
+        err = sdmmc_send_cmd_switch_func(card, 1, SD_ACCESS_MODE, SD_ACCESS_MODE_SDR50, response);
+        if (err != ESP_OK) {
+            ESP_LOGD(TAG, "%s: sdmmc_send_cmd_switch_func (2) returned 0x%x", __func__, err);
+            goto out;
+        }
+    } else {
+        ESP_LOGV(TAG, "%s: to switch to SDR25", __func__);
+        if ((supported_mask & BIT(SD_ACCESS_MODE_SDR25)) == 0) {
+            err = ESP_ERR_NOT_SUPPORTED;
+            goto out;
+        }
+        err = sdmmc_send_cmd_switch_func(card, 1, SD_ACCESS_MODE, SD_ACCESS_MODE_SDR25, response);
+        if (err != ESP_OK) {
+            ESP_LOGD(TAG, "%s: sdmmc_send_cmd_switch_func (2) returned 0x%x", __func__, err);
+            goto out;
+        }
     }
 
 out:
@@ -270,6 +319,172 @@ esp_err_t sdmmc_enable_hs_mode(sdmmc_card_t* card)
     return err;
 }
 
+static const uint8_t s_tuning_block_pattern[] = {
+	0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
+	0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
+	0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
+	0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
+	0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
+	0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
+	0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
+	0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
+};
+
+/**
+ * Find consecutive successful sampling points.
+ * e.g. array: {1, 1, 0, 0, 1, 1, 1, 0}
+ * out_length: 3
+ * outout_end_index: 6
+ */
+static void find_max_consecutive_success_points(int *array, size_t size, size_t *out_length, uint32_t *out_end_index)
+{
+    uint32_t max = 0;
+    uint32_t match_num = 0;
+    uint32_t i = 0;
+    uint32_t end = 0;
+
+    while (i < size) {
+        if (array[i] == 1) {
+            match_num++;
+        } else {
+            if (match_num > max) {
+                max = match_num;
+                end = i - 1;
+            }
+            match_num = 0;
+        }
+        i++;
+    }
+
+    *out_length = match_num > max ? match_num : max;
+    *out_end_index = match_num == size ? size : end;
+}
+
+static esp_err_t read_tuning_block(sdmmc_card_t *card)
+{
+    esp_err_t ret = ESP_FAIL;
+    size_t tuning_block_size = sizeof(s_tuning_block_pattern);
+    ESP_LOGV(TAG, "tuning_block_size: %zu", tuning_block_size);
+    uint8_t *databuf = NULL;
+    databuf = heap_caps_calloc(1, tuning_block_size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
+    ESP_RETURN_ON_FALSE(databuf, ESP_ERR_NO_MEM, TAG, "no mem for tuning block databuf");
+
+    sdmmc_command_t cmd = {
+        .opcode = MMC_SEND_TUNING_BLOCK,
+        .flags = SCF_CMD_ADTC | SCF_CMD_READ | SCF_RSP_R1,
+        .blklen = tuning_block_size,
+        .data = (void *) databuf,
+        .datalen = 1 * tuning_block_size,
+        .buflen = tuning_block_size,
+    };
+
+    ret = sdmmc_send_cmd(card, &cmd);
+    if (ret != ESP_OK) {
+        ESP_LOGW(TAG, "%s: sdmmc_send_cmd returned 0x%x", __func__, ret);
+        return ret;
+    }
+
+    uint32_t status = 0;
+    size_t count = 0;
+    int64_t yield_delay_us = 100 * 1000; // initially 100ms
+    int64_t t0 = esp_timer_get_time();
+    int64_t t1 = 0;
+    while (!host_is_spi(card) && !(status & MMC_R1_READY_FOR_DATA)) {
+        t1 = esp_timer_get_time();
+        if (t1 - t0 > SDMMC_READY_FOR_DATA_TIMEOUT_US) {
+            ESP_LOGW(TAG, "read sectors dma - timeout");
+            return ESP_ERR_TIMEOUT;
+        }
+        if (t1 - t0 > yield_delay_us) {
+            yield_delay_us *= 2;
+            vTaskDelay(1);
+        }
+        ret = sdmmc_send_cmd_send_status(card, &status);
+        if (ret != ESP_OK) {
+            ESP_LOGW(TAG, "%s: sdmmc_send_cmd_send_status returned 0x%x", __func__, ret);
+            return ret;
+        }
+        if (++count % 16 == 0) {
+            ESP_LOGV(TAG, "waiting for card to become ready (%d)", count);
+        }
+    }
+
+    bool success = false;
+    if (memcmp(s_tuning_block_pattern, databuf, tuning_block_size) == 0) {
+        success = true;
+    }
+
+    return success ? ESP_OK : ESP_FAIL;
+}
+
+esp_err_t sdmmc_do_timing_tuning(sdmmc_card_t *card)
+{
+    esp_err_t ret = ESP_FAIL;
+
+    ESP_RETURN_ON_FALSE(!host_is_spi(card), ESP_ERR_NOT_SUPPORTED, TAG, "sdspi not supported timing tuning");
+    ESP_RETURN_ON_FALSE(card->host.set_input_delay, ESP_ERR_NOT_SUPPORTED, TAG, "input phase delay feature isn't supported");
+
+    int results[SDMMC_DELAY_PHASE_AUTO] = {};
+    int slot = card->host.slot;
+    for (int i = SDMMC_DELAY_PHASE_0; i < SDMMC_DELAY_PHASE_AUTO; i++) {
+        ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, i), TAG, "failed to set input delay");
+
+        ret = read_tuning_block(card);
+        if (ret == ESP_OK) {
+            results[i] += 1;
+        }
+    }
+
+    for (int i = 0; i < 4; i++) {
+        ESP_LOGV(TAG, "results[%d]: %d", i, results[i]);
+    }
+
+    size_t consecutive_len = 0;
+    uint32_t end = 0;
+    find_max_consecutive_success_points(results, SDMMC_DELAY_PHASE_AUTO, &consecutive_len, &end);
+
+    sdmmc_delay_phase_t proper_delay_phase = SDMMC_DELAY_PHASE_AUTO;
+    if (consecutive_len == 1) {
+        proper_delay_phase = end;
+    } else if (consecutive_len <= SDMMC_DELAY_PHASE_AUTO) {
+        proper_delay_phase = end / 2;
+    } else {
+        assert(false && "exceeds max tuning point");
+    }
+    ESP_LOGV(TAG, "%s: proper_delay_phase: %d\n", __func__, proper_delay_phase);
+
+    if (proper_delay_phase != SDMMC_DELAY_PHASE_AUTO) {
+        ESP_RETURN_ON_ERROR((*card->host.set_input_delay)(slot, proper_delay_phase), TAG, "failed to set input delay");
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t sdmmc_select_driver_strength(sdmmc_card_t *card, sdmmc_driver_strength_t driver_strength)
+{
+    if (card->scr.sd_spec < SCR_SD_SPEC_VER_1_10 ||
+        ((card->csd.card_command_class & SD_CSD_CCC_SWITCH) == 0)) {
+            return ESP_ERR_NOT_SUPPORTED;
+    }
+
+    esp_err_t ret = ESP_FAIL;
+    sdmmc_switch_func_rsp_t *response = NULL;
+    response = heap_caps_calloc(1, sizeof(*response), MALLOC_CAP_DMA);
+    ESP_RETURN_ON_FALSE(response, ESP_ERR_NO_MEM, TAG, "no mem for response buf");
+
+    ret = sdmmc_send_cmd_switch_func(card, 1, SD_DRIVER_STRENGTH, driver_strength, response);
+    ESP_GOTO_ON_ERROR(ret, out, TAG, "%s: sdmmc_send_cmd_switch_func (1) returned 0x%x", __func__, ret);
+
+    uint32_t supported_mask = SD_SFUNC_SELECTED(response->data, SD_DRIVER_STRENGTH);
+    ESP_GOTO_ON_FALSE(supported_mask != 0xf, ESP_ERR_NOT_SUPPORTED, out, TAG, "switch group1 result fail");
+    ESP_LOGV(TAG, "driver strength: supported_mask: 0x%"PRIx32, supported_mask);
+    ESP_GOTO_ON_FALSE(supported_mask == driver_strength, ESP_ERR_INVALID_ARG, out, TAG, "fail to switch to type 0x%x", driver_strength);
+
+out:
+    free(response);
+    return ret;
+}
+
 esp_err_t sdmmc_enable_hs_mode_and_check(sdmmc_card_t* card)
 {
     /* All cards should support at least default speed */
@@ -281,10 +496,11 @@ esp_err_t sdmmc_enable_hs_mode_and_check(sdmmc_card_t* card)
     }
 
     /* Try to enabled HS mode */
-    esp_err_t err = sdmmc_enable_hs_mode(card);
+    esp_err_t err = sdmmc_enter_higher_speed_mode(card);
     if (err != ESP_OK) {
         return err;
     }
+
     /* HS mode has been enabled on the card.
      * Read CSD again, it should now indicate that the card supports
      * 50MHz clock.
@@ -313,15 +529,63 @@ esp_err_t sdmmc_enable_hs_mode_and_check(sdmmc_card_t* card)
         }
     }
 
-    if (card->csd.tr_speed != 50000000) {
-        ESP_LOGW(TAG, "unexpected: after enabling HS mode, tr_speed=%d", card->csd.tr_speed);
-        return ESP_ERR_NOT_SUPPORTED;
-    }
+    ESP_LOGD(TAG, "%s: after enabling HS mode, tr_speed=%d", __func__, card->csd.tr_speed);
+    card->max_freq_khz = MIN(card->host.max_freq_khz, SDMMC_FREQ_SDR104);
 
-    card->max_freq_khz = MIN(card->host.max_freq_khz, SDMMC_FREQ_HIGHSPEED);
     return ESP_OK;
 }
 
+static esp_err_t sdmmc_init_sd_uhs1_volt_sw_cb(void* arg, int voltage_mv)
+{
+    sdmmc_card_t* card = (sdmmc_card_t*)arg;
+    ESP_LOGV(TAG, "%s: Voltage switch callback (%umv)", __func__, voltage_mv);
+    return sd_pwr_ctrl_set_io_voltage(card->host.pwr_ctrl_handle, voltage_mv);
+}
+
+esp_err_t sdmmc_init_sd_uhs1(sdmmc_card_t* card)
+{
+    sdmmc_command_t cmd = {
+            .opcode = SD_SWITCH_VOLTAGE,
+            .arg = 0,
+            .flags = SCF_CMD_AC | SCF_RSP_R1,
+            .volt_switch_cb = &sdmmc_init_sd_uhs1_volt_sw_cb,
+            .volt_switch_cb_arg = card
+    };
+    esp_err_t err = sdmmc_send_cmd(card, &cmd);
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "%s: send_cmd returned 0x%x", __func__, err);
+    }
+
+    card->is_uhs1 = 1;
+
+    return err;
+}
+
+esp_err_t sdmmc_select_current_limit(sdmmc_card_t *card, sdmmc_current_limit_t current_limit)
+{
+    if (card->scr.sd_spec < SCR_SD_SPEC_VER_1_10 ||
+        ((card->csd.card_command_class & SD_CSD_CCC_SWITCH) == 0)) {
+            return ESP_ERR_NOT_SUPPORTED;
+    }
+
+    esp_err_t ret = ESP_FAIL;
+    sdmmc_switch_func_rsp_t *response = NULL;
+    response = heap_caps_calloc(1, sizeof(*response), MALLOC_CAP_DMA);
+    ESP_RETURN_ON_FALSE(response, ESP_ERR_NO_MEM, TAG, "no mem for response buf");
+
+    ret = sdmmc_send_cmd_switch_func(card, 1, SD_CURRENT_LIMIT, current_limit, response);
+    ESP_GOTO_ON_ERROR(ret, out, TAG, "%s: sdmmc_send_cmd_switch_func (1) returned 0x%x", __func__, ret);
+
+    uint32_t supported_mask = SD_SFUNC_SELECTED(response->data, SD_CURRENT_LIMIT);
+    ESP_GOTO_ON_FALSE(supported_mask != 0xf, ESP_ERR_NOT_SUPPORTED, out, TAG, "switch group4 result fail");
+    ESP_LOGV(TAG, "current limit: supported_mask: 0x%"PRIx32, supported_mask);
+    ESP_GOTO_ON_FALSE(supported_mask == current_limit, ESP_ERR_INVALID_ARG, out, TAG, "fail to switch to type 0x%x", current_limit);
+
+out:
+    free(response);
+    return ret;
+}
+
 esp_err_t sdmmc_check_scr(sdmmc_card_t* card)
 {
     /* If frequency switch has been performed, read SCR register one more time
@@ -390,11 +654,22 @@ esp_err_t sdmmc_decode_csd(sdmmc_response_t response, sdmmc_csd_t* out_csd)
         out_csd->capacity *= read_bl_size / out_csd->sector_size;
     }
     int speed = SD_CSD_SPEED(response);
-    if (speed == SD_CSD_SPEED_50_MHZ) {
+    ESP_LOGV(TAG, "%s: speed: 0x%x", __func__, speed);
+    switch (speed) {
+    case SD_CSD_SPEED_50_MHZ:
         out_csd->tr_speed = 50000000;
-    } else {
+        break;
+    case SD_CSD_SPEED_100_MHZ:
+        out_csd->tr_speed = 100000000;
+        break;
+    case SD_CSD_SPEED_200_MHZ:
+        out_csd->tr_speed = 200000000;
+        break;
+    default:
         out_csd->tr_speed = 25000000;
+        break;
     }
+
     return ESP_OK;
 }
 
diff --git a/components/soc/CMakeLists.txt b/components/soc/CMakeLists.txt
index 765cde298b7..032467798f5 100644
--- a/components/soc/CMakeLists.txt
+++ b/components/soc/CMakeLists.txt
@@ -47,6 +47,10 @@ if(CONFIG_SOC_EMAC_SUPPORTED)
     list(APPEND srcs "${target_folder}/emac_periph.c")
 endif()
 
+if(CONFIG_SOC_ETM_SUPPORTED)
+    list(APPEND srcs "${target_folder}/etm_periph.c")
+endif()
+
 if(CONFIG_SOC_GDMA_SUPPORTED)
     list(APPEND srcs "${target_folder}/gdma_periph.c")
 endif()
@@ -142,10 +146,7 @@ if(CONFIG_SOC_IEEE802154_SUPPORTED)
 endif()
 
 if(CONFIG_SOC_USB_OTG_SUPPORTED)
-    if(NOT ${target} STREQUAL "esp32p4")
-        list(APPEND srcs "${target_folder}/usb_periph.c"
-                         "${target_folder}/usb_dwc_periph.c")
-    endif()
+    list(APPEND srcs "${target_folder}/usb_dwc_periph.c")
 endif()
 
 if(CONFIG_SOC_DAC_SUPPORTED)
diff --git a/components/soc/esp32/include/soc/Kconfig.soc_caps.in b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
index f6f4b25e22c..2279f424d16 100644
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@@ -483,6 +483,10 @@ config SOC_LEDC_SUPPORT_HS_MODE
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 8
@@ -895,6 +899,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D4
+    bool
+    default y
+
 config SOC_SDMMC_USE_IOMUX
     bool
     default y
diff --git a/components/soc/esp32/include/soc/clk_tree_defs.h b/components/soc/esp32/include/soc/clk_tree_defs.h
index 9e843c28c40..c0b0a8d1942 100644
--- a/components/soc/esp32/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32/include/soc/clk_tree_defs.h
@@ -21,7 +21,7 @@ extern "C" {
  *
  * 2) External 2~40MHz Crystal Clock: XTAL
  *
- * 3) Internal 150kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
+ * 3) Internal 150kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~150kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.
@@ -86,9 +86,12 @@ typedef enum {
  */
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_XTAL_D4 = 0,      /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 1,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< XTAL_D4_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
 } soc_rtc_fast_clk_src_t;
 
 /**
diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index bb35d3718a5..22364a42215 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -241,6 +241,7 @@
 #define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
 #define SOC_LEDC_SUPPORT_REF_TICK        (1)
 #define SOC_LEDC_SUPPORT_HS_MODE         (1)
+#define SOC_LEDC_TIMER_NUM               (4)
 #define SOC_LEDC_CHANNEL_NUM             (8)
 #define SOC_LEDC_TIMER_BIT_WIDTH         (20)
 
@@ -425,6 +426,8 @@
 
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D4           (1)     /*!< Support XTAL_D4 clock as the LP_FAST clock source */
+
 /*-------------------------- SDMMC CAPS -----------------------------------------*/
 
 /* On ESP32, clock/cmd/data pins use IO MUX.
diff --git a/components/soc/esp32/register/soc/sdmmc_reg.h b/components/soc/esp32/register/soc/sdmmc_reg.h
index 8370f9dc82c..0cdb0272d7c 100644
--- a/components/soc/esp32/register/soc/sdmmc_reg.h
+++ b/components/soc/esp32/register/soc/sdmmc_reg.h
@@ -67,6 +67,7 @@
 #define SDMMC_INTMASK_HLE       BIT(12)
 #define SDMMC_INTMASK_FRUN      BIT(11)
 #define SDMMC_INTMASK_HTO       BIT(10)
+#define SDMMC_INTMASK_VOLT_SW   SDMMC_INTMASK_HTO
 #define SDMMC_INTMASK_DTO       BIT(9)
 #define SDMMC_INTMASK_RTO       BIT(8)
 #define SDMMC_INTMASK_DCRC      BIT(7)
diff --git a/components/soc/esp32/register/soc/spi_struct.h b/components/soc/esp32/register/soc/spi_struct.h
index 36fe885c73d..320df8e9489 100644
--- a/components/soc/esp32/register/soc/spi_struct.h
+++ b/components/soc/esp32/register/soc/spi_struct.h
@@ -488,177 +488,7 @@ typedef volatile struct spi_dev_s {
     uint32_t dma_outlink_dscr_bf1;                          /*The content of current out descriptor data buffer pointer.*/
     uint32_t dma_rx_status;                                 /*spi dma read data from memory status.*/
     uint32_t dma_tx_status;                                 /*spi dma write data to memory status.*/
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
+    uint32_t reserved_150[171];
     union {
         struct {
             uint32_t date:      28;                         /*SPI register version.*/
@@ -667,6 +497,7 @@ typedef volatile struct spi_dev_s {
         uint32_t val;
     } date;
 } spi_dev_t;
+
 extern spi_dev_t SPI0;                                      /* SPI0 IS FOR INTERNAL USE*/
 extern spi_dev_t SPI1;
 extern spi_dev_t SPI2;
diff --git a/components/soc/esp32/register/soc/uart_struct.h b/components/soc/esp32/register/soc/uart_struct.h
index d81e0a90861..21cfb49428a 100644
--- a/components/soc/esp32/register/soc/uart_struct.h
+++ b/components/soc/esp32/register/soc/uart_struct.h
@@ -243,8 +243,8 @@ typedef volatile struct uart_dev_s {
         struct {
             uint32_t xon_threshold:  8;             /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/
             uint32_t xoff_threshold: 8;             /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/
-            uint32_t xon_char:       8;             /*This register stores the xon flow control char.*/
-            uint32_t xoff_char:      8;             /*This register stores the xoff flow control char.*/
+            uint32_t xon_character:  8;             /*This register stores the xon flow control char.*/
+            uint32_t xoff_character: 8;             /*This register stores the xoff flow control char.*/
         };
         uint32_t val;
     } swfc_conf;
@@ -294,7 +294,7 @@ typedef volatile struct uart_dev_s {
     union {
         struct {
             uint32_t data:        8;                /*This register is used to configure the content of at_cmd char.*/
-            uint32_t char_num:    8;                /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
+            uint32_t at_char_num: 8;                /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
             uint32_t reserved16: 16;
         };
         uint32_t val;
diff --git a/components/soc/esp32/spi_periph.c b/components/soc/esp32/spi_periph.c
index 934fcde61c9..5ff8450533c 100644
--- a/components/soc/esp32/spi_periph.c
+++ b/components/soc/esp32/spi_periph.c
@@ -31,7 +31,6 @@ const spi_signal_conn_t spi_periph_signal[3] = {
         .spics0_iomux_pin = MSPI_IOMUX_PIN_NUM_CS0,
         .irq = ETS_SPI1_INTR_SOURCE,
         .irq_dma = ETS_SPI1_DMA_INTR_SOURCE,
-        .module = PERIPH_SPI_MODULE,
         .func = MSPI_FUNC_NUM,
         .hw = &SPI1
     }, {
@@ -55,7 +54,6 @@ const spi_signal_conn_t spi_periph_signal[3] = {
         .spics0_iomux_pin = HSPI_IOMUX_PIN_NUM_CS,
         .irq = ETS_SPI2_INTR_SOURCE,
         .irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
-        .module = PERIPH_HSPI_MODULE,
         .func = HSPI_FUNC_NUM,
         .hw = &SPI2
     }, {
@@ -79,7 +77,6 @@ const spi_signal_conn_t spi_periph_signal[3] = {
         .spics0_iomux_pin = VSPI_IOMUX_PIN_NUM_CS,
         .irq = ETS_SPI3_INTR_SOURCE,
         .irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
-        .module = PERIPH_VSPI_MODULE,
         .func = VSPI_FUNC_NUM,
         .hw = &SPI3
     }
diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
index 4ece6275e65..47ff2ad605f 100644
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@@ -383,6 +383,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6
@@ -751,6 +755,10 @@ config SOC_CLK_OSC_SLOW_SUPPORTED
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    bool
+    default y
+
 config SOC_WIFI_HW_TSF
     bool
     default y
diff --git a/components/soc/esp32c2/include/soc/assist_debug_reg.h b/components/soc/esp32c2/include/soc/assist_debug_reg.h
deleted file mode 100644
index 2734f5e2984..00000000000
--- a/components/soc/esp32c2/include/soc/assist_debug_reg.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
- *  core0 monitor enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [0]; default: 0;
- *  enbale sp underlow monitor
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  0
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [1]; default: 0;
- *  enbale sp overflow monitor
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  1
-
-/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
- *  core0 monitor interrupt status register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [0]; default: 0;
- *  sp underlow monitor interrupt status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  0
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [1]; default: 0;
- *  sp overflow monitor interupt status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  1
-
-/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
- *  core0 monitor interrupt enable register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [0]; default: 0;
- *  enbale sp underlow monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  0
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [1]; default: 0;
- *  enbale sp overflow monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  1
-
-/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
- *  core0 monitor interrupt clr register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [0]; default: 0;
- *  clr sp underlow monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  0
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [1]; default: 0;
- *  clr sp overflow monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  1
-
-/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
- *  stack min value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
-/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
- *  stack max value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
-/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
- *  core0 sp pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
- *  stack monitor pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
-/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
- *  record enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
-/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable record PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
- *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
- *  recorded PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
- *  recorded sp
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
-
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
- *  cpu's lastpc before exception
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
-
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
- *  cpu debug mode status, 1 means cpu enter debug mode.
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
- *  cpu debug_module active status
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
-
-/** ASSIST_DEBUG_CLOCK_GATE_REG register
- *  clock gate register
- */
-#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
-/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  clock gate register
- */
-#define ASSIST_DEBUG_CLK_EN    (BIT(0))
-#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
-#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
-#define ASSIST_DEBUG_CLK_EN_S  0
-
-/** ASSIST_DEBUG_DATE_REG register
- *  version register
- */
-#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc)
-/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34627616;
- *  version register
- */
-#define ASSIST_DEBUG_DATE    0x0FFFFFFFU
-#define ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
-#define ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
-#define ASSIST_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c2/include/soc/clk_tree_defs.h b/components/soc/esp32c2/include/soc/clk_tree_defs.h
index 1d7a2cfe5f9..9b9f1a46f32 100644
--- a/components/soc/esp32c2/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c2/include/soc/clk_tree_defs.h
@@ -21,7 +21,7 @@ extern "C" {
  *
  * 2) External 26/40MHz Crystal Clock: XTAL
  *
- * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.
@@ -82,9 +82,12 @@ typedef enum {
  */
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0,      /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 1,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
 } soc_rtc_fast_clk_src_t;
 
 /**
diff --git a/components/soc/esp32c2/include/soc/dport_access.h b/components/soc/esp32c2/include/soc/dport_access.h
index 5a847ca4842..e499a791bdd 100644
--- a/components/soc/esp32c2/include/soc/dport_access.h
+++ b/components/soc/esp32c2/include/soc/dport_access.h
@@ -8,8 +8,7 @@
 #define _DPORT_ACCESS_H_
 
 #include <stdint.h>
-#include "soc.h"
-#include "uart_reg.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32c2/include/soc/ecc_mult_reg.h b/components/soc/esp32c2/include/soc/ecc_mult_reg.h
deleted file mode 100644
index 906a91b7af7..00000000000
--- a/components/soc/esp32c2/include/soc/ecc_mult_reg.h
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ECC_MULT_INT_RAW_REG          (DR_REG_ECC_MULT_BASE + 0xC)
-/* ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt.*/
-#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_RAW_M  (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_RAW_V  0x1
-#define ECC_MULT_CALC_DONE_INT_RAW_S  0
-
-#define ECC_MULT_INT_ST_REG          (DR_REG_ECC_MULT_BASE + 0x10)
-/* ECC_MULT_CALC_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_rx_done_int interrupt.*/
-#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ST_M  (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ST_V  0x1
-#define ECC_MULT_CALC_DONE_INT_ST_S  0
-
-#define ECC_MULT_INT_ENA_REG          (DR_REG_ECC_MULT_BASE + 0x14)
-/* ECC_MULT_CALC_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_rx_done_int interrupt.*/
-#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ENA_M  (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ENA_V  0x1
-#define ECC_MULT_CALC_DONE_INT_ENA_S  0
-
-#define ECC_MULT_INT_CLR_REG          (DR_REG_ECC_MULT_BASE + 0x18)
-/* ECC_MULT_CALC_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_rx_done_int interrupt.*/
-#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_CLR_M  (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_CLR_V  0x1
-#define ECC_MULT_CALC_DONE_INT_CLR_S  0
-
-#define ECC_MULT_CONF_REG          (DR_REG_ECC_MULT_BASE + 0x1C)
-/* ECC_MULT_VERIFICATION_RESULT : RO/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Reserve.*/
-#define ECC_MULT_VERIFICATION_RESULT    (BIT(8))
-#define ECC_MULT_VERIFICATION_RESULT_M  (BIT(8))
-#define ECC_MULT_VERIFICATION_RESULT_V  0x1
-#define ECC_MULT_VERIFICATION_RESULT_S  8
-/* ECC_MULT_WORK_MODE : R/W ;bitpos:[7:5] ;default: 3'b0 ; */
-/*description:  Reserved.*/
-#define ECC_MULT_WORK_MODE    0x00000007
-#define ECC_MULT_WORK_MODE_M  ((ECC_MULT_WORK_MODE_V)<<(ECC_MULT_WORK_MODE_S))
-#define ECC_MULT_WORK_MODE_V  0x7
-#define ECC_MULT_WORK_MODE_S  5
-/* ECC_MULT_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: clk gate.*/
-#define ECC_MULT_CLK_EN    (BIT(4))
-#define ECC_MULT_CLK_EN_M  (BIT(4))
-#define ECC_MULT_CLK_EN_V  0x1
-#define ECC_MULT_CLK_EN_S  4
-/* ECC_MULT_SECURITY_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable slave receiver mode.*/
-#define ECC_MULT_SECURITY_MODE    (BIT(3))
-#define ECC_MULT_SECURITY_MODE_M  (BIT(3))
-#define ECC_MULT_SECURITY_MODE_V  0x1
-#define ECC_MULT_SECURITY_MODE_S  3
-/* ECC_MULT_KEY_LENGTH : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to start receiving data.*/
-#define ECC_MULT_KEY_LENGTH    (BIT(2))
-#define ECC_MULT_KEY_LENGTH_M  (BIT(2))
-#define ECC_MULT_KEY_LENGTH_V  0x1
-#define ECC_MULT_KEY_LENGTH_S  2
-/* ECC_MULT_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to reset Rx AFIFO.*/
-#define ECC_MULT_RESET    (BIT(1))
-#define ECC_MULT_RESET_M  (BIT(1))
-#define ECC_MULT_RESET_V  0x1
-#define ECC_MULT_RESET_S  1
-/* ECC_MULT_START : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to reset receiver.*/
-#define ECC_MULT_START    (BIT(0))
-#define ECC_MULT_START_M  (BIT(0))
-#define ECC_MULT_START_V  0x1
-#define ECC_MULT_START_S  0
-
-#define ECC_MULT_DATE_REG          (DR_REG_ECC_MULT_BASE + 0xFC)
-/* ECC_MULT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012230 ; */
-/*description: ECC mult version control register.*/
-#define ECC_MULT_DATE    0x0FFFFFFF
-#define ECC_MULT_DATE_M  ((ECC_MULT_DATE_V)<<(ECC_MULT_DATE_S))
-#define ECC_MULT_DATE_V  0xFFFFFFF
-#define ECC_MULT_DATE_S  0
-
-#define ECC_MULT_K_1_REG          (DR_REG_ECC_MULT_BASE + 0x0100)
-/* ECC_MULT_MEM_K_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter k.*/
-#define ECC_MULT_MEM_K_1  0xFFFFFFFF
-#define ECC_MULT_MEM_K_1_M  ((ECC_MULT_MEM_K_1_V)<<(ECC_MULT_MEM_K_1_S))
-#define ECC_MULT_MEM_K_1_V  0xFFFFFFFF
-#define ECC_MULT_MEM_K_1_S  0
-
-#define ECC_MULT_K_2_REG          (DR_REG_ECC_MULT_BASE + 0x0104)
-/* ECC_MULT_MEM_K_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter k.*/
-#define ECC_MULT_MEM_K_2  0xFFFFFFFF
-#define ECC_MULT_MEM_K_2_M  ((ECC_MULT_MEM_K_2_V)<<(ECC_MULT_MEM_K_2_S))
-#define ECC_MULT_MEM_K_2_V  0xFFFFFFFF
-#define ECC_MULT_MEM_K_2_S  0
-
-#define ECC_MULT_K_3_REG          (DR_REG_ECC_MULT_BASE + 0x0108)
-/* ECC_MULT_MEM_K_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter k.*/
-#define ECC_MULT_MEM_K_3  0xFFFFFFFF
-#define ECC_MULT_MEM_K_3_M  ((ECC_MULT_MEM_K_3_V)<<(ECC_MULT_MEM_K_3_S))
-#define ECC_MULT_MEM_K_3_V  0xFFFFFFFF
-#define ECC_MULT_MEM_K_3_S  0
-
-#define ECC_MULT_K_4_REG          (DR_REG_ECC_MULT_BASE + 0x010c)
-/* ECC_MULT_MEM_K_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter k.*/
-#define ECC_MULT_MEM_K_4  0xFFFFFFFF
-#define ECC_MULT_MEM_K_4_M  ((ECC_MULT_MEM_K_4_V)<<(ECC_MULT_MEM_K_4_S))
-#define ECC_MULT_MEM_K_4_V  0xFFFFFFFF
-#define ECC_MULT_MEM_K_4_S  0
-
-#define ECC_MULT_K_5_REG          (DR_REG_ECC_MULT_BASE + 0x0110)
-/* ECC_MULT_MEM_K_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter k.*/
-#define ECC_MULT_MEM_K_5  0xFFFFFFFF
-#define ECC_MULT_MEM_K_5_M  ((ECC_MULT_MEM_K_5_V)<<(ECC_MULT_MEM_K_5_S))
-#define ECC_MULT_MEM_K_5_V  0xFFFFFFFF
-#define ECC_MULT_MEM_K_5_S  0
-
-#define ECC_MULT_K_6_REG          (DR_REG_ECC_MULT_BASE + 0x0114)
-/* ECC_MULT_MEM_K_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter k.*/
-#define ECC_MULT_MEM_K_6  0xFFFFFFFF
-#define ECC_MULT_MEM_K_6_M  ((ECC_MULT_MEM_K_6_V)<<(ECC_MULT_MEM_K_6_S))
-#define ECC_MULT_MEM_K_6_V  0xFFFFFFFF
-#define ECC_MULT_MEM_K_6_S  0
-
-#define ECC_MULT_K_7_REG          (DR_REG_ECC_MULT_BASE + 0x0118)
-/* ECC_MULT_MEM_K_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter k.*/
-#define ECC_MULT_MEM_K_7  0xFFFFFFFF
-#define ECC_MULT_MEM_K_7_M  ((ECC_MULT_MEM_K_7_V)<<(ECC_MULT_MEM_K_7_S))
-#define ECC_MULT_MEM_K_7_V  0xFFFFFFFF
-#define ECC_MULT_MEM_K_7_S  0
-
-#define ECC_MULT_K_8_REG          (DR_REG_ECC_MULT_BASE + 0x011c)
-/* ECC_MULT_MEM_K_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter k.*/
-#define ECC_MULT_MEM_K_8  0xFFFFFFFF
-#define ECC_MULT_MEM_K_8_M  ((ECC_MULT_MEM_K_8_V)<<(ECC_MULT_MEM_K_8_S))
-#define ECC_MULT_MEM_K_8_V  0xFFFFFFFF
-#define ECC_MULT_MEM_K_8_S  0
-
-#define ECC_MULT_PX_1_REG          (DR_REG_ECC_MULT_BASE + 0x0120)
-/* ECC_MULT_MEM_PX_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Px.*/
-#define ECC_MULT_MEM_PX_1  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_1_M  ((ECC_MULT_MEM_PX_1_V)<<(ECC_MULT_MEM_PX_1_S))
-#define ECC_MULT_MEM_PX_1_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_1_S  0
-
-#define ECC_MULT_PX_2_REG          (DR_REG_ECC_MULT_BASE + 0x0124)
-/* ECC_MULT_MEM_PX_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Px.*/
-#define ECC_MULT_MEM_PX_2  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_2_M  ((ECC_MULT_MEM_PX_2_V)<<(ECC_MULT_MEM_PX_2_S))
-#define ECC_MULT_MEM_PX_2_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_2_S  0
-
-#define ECC_MULT_PX_3_REG          (DR_REG_ECC_MULT_BASE + 0x0128)
-/* ECC_MULT_MEM_PX_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Px.*/
-#define ECC_MULT_MEM_PX_3  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_3_M  ((ECC_MULT_MEM_PX_3_V)<<(ECC_MULT_MEM_PX_3_S))
-#define ECC_MULT_MEM_PX_3_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_3_S  0
-
-#define ECC_MULT_PX_4_REG          (DR_REG_ECC_MULT_BASE + 0x012c)
-/* ECC_MULT_MEM_PX_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Px.*/
-#define ECC_MULT_MEM_PX_4  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_4_M  ((ECC_MULT_MEM_PX_4_V)<<(ECC_MULT_MEM_PX_4_S))
-#define ECC_MULT_MEM_PX_4_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_4_S  0
-
-#define ECC_MULT_PX_5_REG          (DR_REG_ECC_MULT_BASE + 0x0130)
-/* ECC_MULT_MEM_PX_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Px.*/
-#define ECC_MULT_MEM_PX_5  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_5_M  ((ECC_MULT_MEM_PX_5_V)<<(ECC_MULT_MEM_PX_5_S))
-#define ECC_MULT_MEM_PX_5_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_5_S  0
-
-#define ECC_MULT_PX_6_REG          (DR_REG_ECC_MULT_BASE + 0x0134)
-/* ECC_MULT_MEM_PX_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Px.*/
-#define ECC_MULT_MEM_PX_6  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_6_M  ((ECC_MULT_MEM_PX_6_V)<<(ECC_MULT_MEM_PX_6_S))
-#define ECC_MULT_MEM_PX_6_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_6_S  0
-
-#define ECC_MULT_PX_7_REG          (DR_REG_ECC_MULT_BASE + 0x0138)
-/* ECC_MULT_MEM_PX_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Px.*/
-#define ECC_MULT_MEM_PX_7  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_7_M  ((ECC_MULT_MEM_PX_7_V)<<(ECC_MULT_MEM_PX_7_S))
-#define ECC_MULT_MEM_PX_7_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_7_S  0
-
-#define ECC_MULT_PX_8_REG          (DR_REG_ECC_MULT_BASE + 0x013c)
-/* ECC_MULT_MEM_PX_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Px.*/
-#define ECC_MULT_MEM_PX_8  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_8_M  ((ECC_MULT_MEM_PX_8_V)<<(ECC_MULT_MEM_PX_8_S))
-#define ECC_MULT_MEM_PX_8_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PX_8_S  0
-
-#define ECC_MULT_PY_1_REG          (DR_REG_ECC_MULT_BASE + 0x0140)
-/* ECC_MULT_MEM_PY_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Py.*/
-#define ECC_MULT_MEM_PY_1  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_1_M  ((ECC_MULT_MEM_PY_1_V)<<(ECC_MULT_MEM_PY_1_S))
-#define ECC_MULT_MEM_PY_1_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_1_S  0
-
-#define ECC_MULT_PY_2_REG          (DR_REG_ECC_MULT_BASE + 0x0144)
-/* ECC_MULT_MEM_PY_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Py.*/
-#define ECC_MULT_MEM_PY_2  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_2_M  ((ECC_MULT_MEM_PY_2_V)<<(ECC_MULT_MEM_PY_2_S))
-#define ECC_MULT_MEM_PY_2_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_2_S  0
-
-#define ECC_MULT_PY_3_REG          (DR_REG_ECC_MULT_BASE + 0x0148)
-/* ECC_MULT_MEM_PY_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Py.*/
-#define ECC_MULT_MEM_PY_3  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_3_M  ((ECC_MULT_MEM_PY_3_V)<<(ECC_MULT_MEM_PY_3_S))
-#define ECC_MULT_MEM_PY_3_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_3_S  0
-
-#define ECC_MULT_PY_4_REG          (DR_REG_ECC_MULT_BASE + 0x014c)
-/* ECC_MULT_MEM_PY_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Py.*/
-#define ECC_MULT_MEM_PY_4  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_4_M  ((ECC_MULT_MEM_PY_4_V)<<(ECC_MULT_MEM_PY_4_S))
-#define ECC_MULT_MEM_PY_4_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_4_S  0
-
-#define ECC_MULT_PY_5_REG          (DR_REG_ECC_MULT_BASE + 0x0150)
-/* ECC_MULT_MEM_PY_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Py.*/
-#define ECC_MULT_MEM_PY_5  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_5_M  ((ECC_MULT_MEM_PY_5_V)<<(ECC_MULT_MEM_PY_5_S))
-#define ECC_MULT_MEM_PY_5_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_5_S  0
-
-#define ECC_MULT_PY_6_REG          (DR_REG_ECC_MULT_BASE + 0x0154)
-/* ECC_MULT_MEM_PY_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Py.*/
-#define ECC_MULT_MEM_PY_6  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_6_M  ((ECC_MULT_MEM_PY_6_V)<<(ECC_MULT_MEM_PY_6_S))
-#define ECC_MULT_MEM_PY_6_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_6_S  0
-
-#define ECC_MULT_PY_7_REG          (DR_REG_ECC_MULT_BASE + 0x0158)
-/* ECC_MULT_MEM_PY_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Py.*/
-#define ECC_MULT_MEM_PY_7  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_7_M  ((ECC_MULT_MEM_PY_7_V)<<(ECC_MULT_MEM_PY_7_S))
-#define ECC_MULT_MEM_PY_7_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_7_S  0
-
-#define ECC_MULT_PY_8_REG          (DR_REG_ECC_MULT_BASE + 0x015c)
-/* ECC_MULT_MEM_PY_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: ECC Mem Parameter Py.*/
-#define ECC_MULT_MEM_PY_8  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_8_M  ((ECC_MULT_MEM_PY_8_V)<<(ECC_MULT_MEM_PY_8_S))
-#define ECC_MULT_MEM_PY_8_V  0xFFFFFFFF
-#define ECC_MULT_MEM_PY_8_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c2/include/soc/efuse_reg.h b/components/soc/esp32c2/include/soc/efuse_reg.h
deleted file mode 100644
index 6f13f2a2bae..00000000000
--- a/components/soc/esp32c2/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,1211 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#include "efuse_defs.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 1st 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 2nd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 3rd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 0th 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 1st 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 2nd 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS_REG register
- *  BLOCK0 data register 0.
- */
-#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [7:0]; default: 0;
- *  Disable programming of individual eFuses.
- */
-#define EFUSE_WR_DIS    0x000000FFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0x000000FFU
-#define EFUSE_WR_DIS_S  0
-/** EFUSE_RESERVED_0_8 : RW; bitpos: [31:8]; default: 0; */
-#define EFUSE_RESERVED_0_8    0x00FFFFFFU
-#define EFUSE_RESERVED_0_8_M  (EFUSE_RESERVED_0_8_V << EFUSE_RESERVED_0_8_S)
-#define EFUSE_RESERVED_0_8_V  0x00FFFFFFU
-#define EFUSE_RESERVED_0_8_S  8
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  BLOCK0 data register 1.
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [1:0]; default: 0;
- *  The bit be set to disable software read high/low 128-bit of BLK3.
- */
-#define EFUSE_RD_DIS    0x00000003U
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x00000003U
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [3:2]; default: 0;
- *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
- *  80000. 2: 160000. 3:320000.
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  2
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [4]; default: 0;
- *  Set this bit to disable pad jtag.
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(4))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  4
-/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [5]; default: 0;
- *  The bit be set to disable icache in download mode.
- */
-#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(5))
-#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
-#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_ICACHE_S  5
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [6]; default: 0;
- *  The bit be set to disable manual encryption.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(6))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  6
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [9:7]; default: 0;
- *  These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
- *  number of 1: disable.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  7
-/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [10]; default: 0;
- *  The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise,
- *  XTS_AES use 128-bit eFuse data in BLOCK3.
- */
-#define EFUSE_XTS_KEY_LENGTH_256    (BIT(10))
-#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
-#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
-#define EFUSE_XTS_KEY_LENGTH_256_S  10
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [12:11]; default: 0;
- *  Set this bit to disable usb printing.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  11
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
- *  Set this bit to force ROM code to send a resume command during SPI boot.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  13
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [14]; default: 0;
- *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(14))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  14
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [15]; default: 0;
- *  This bit set means disable direct_boot mode.
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(15))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  15
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [16]; default: 0;
- *  Set this bit to enable secure UART download mode.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(16))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  16
-/** EFUSE_FLASH_TPUW : RO; bitpos: [20:17]; default: 0;
- *  Configures flash waiting time after power-up, in unit of ms. If the value is less
- *  than 15, the waiting time is the configurable value.  Otherwise, the waiting time
- *  is twice the configurable value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  17
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [21]; default: 0;
- *  The bit be set to enable secure boot.
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(21))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  21
-/** EFUSE_SECURE_VERSION : R; bitpos: [25:22]; default: 0;
- *  Secure version for anti-rollback
- */
-#define EFUSE_SECURE_VERSION    0x0000000FU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000000FU
-#define EFUSE_SECURE_VERSION_S  22
-/** EFUSE_CUSTOM_MAC_USED : R; bitpos: [26]; default: 0;
- *  True if MAC_CUSTOM is burned
- */
-#define EFUSE_CUSTOM_MAC_USED    (BIT(26))
-#define EFUSE_CUSTOM_MAC_USED_M  (EFUSE_CUSTOM_MAC_USED_V << EFUSE_CUSTOM_MAC_USED_S)
-#define EFUSE_CUSTOM_MAC_USED_V  0x00000001U
-#define EFUSE_CUSTOM_MAC_USED_S  26
-/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [27]; default: 0;
- *  Disables check of wafer version major
- */
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(27))
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  27
-/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [28]; default: 0;
- *  Disables check of blk version major
- */
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(28))
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  28
-/** EFUSE_RESERVED_0_61 : R; bitpos: [31:29]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_0_61    0x00000007U
-#define EFUSE_RESERVED_0_61_M  (EFUSE_RESERVED_0_61_V << EFUSE_RESERVED_0_61_S)
-#define EFUSE_RESERVED_0_61_V  0x00000007U
-#define EFUSE_RESERVED_0_61_S  29
-
-/** EFUSE_RD_BLK1_DATA0_REG register
- *  BLOCK1 data register 0.
- */
-#define EFUSE_RD_BLK1_DATA0_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:0]; default: 0;
- *  Custom MAC address
- */
-#define EFUSE_CUSTOM_MAC    0xFFFFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0xFFFFFFFFU
-#define EFUSE_CUSTOM_MAC_S  0
-
-/** EFUSE_RD_BLK1_DATA1_REG register
- *  BLOCK1 data register 1.
- */
-#define EFUSE_RD_BLK1_DATA1_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [15:0]; default: 0;
- *  Custom MAC address
- */
-#define EFUSE_CUSTOM_MAC_1    0x0000FFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x0000FFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_1_48 : R; bitpos: [31:16]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_48    0x0000FFFFU
-#define EFUSE_RESERVED_1_48_M  (EFUSE_RESERVED_1_48_V << EFUSE_RESERVED_1_48_S)
-#define EFUSE_RESERVED_1_48_V  0x0000FFFFU
-#define EFUSE_RESERVED_1_48_S  16
-
-/** EFUSE_RD_BLK1_DATA2_REG register
- *  BLOCK1 data register 2.
- */
-#define EFUSE_RD_BLK1_DATA2_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_SYSTEM_DATA2 : RO; bitpos: [23:0]; default: 0;
- *  Stores the bits [64:87] of system data.
- */
-#define EFUSE_SYSTEM_DATA2    0x00FFFFFFU
-#define EFUSE_SYSTEM_DATA2_M  (EFUSE_SYSTEM_DATA2_V << EFUSE_SYSTEM_DATA2_S)
-#define EFUSE_SYSTEM_DATA2_V  0x00FFFFFFU
-#define EFUSE_SYSTEM_DATA2_S  0
-
-/** EFUSE_RD_BLK2_DATA0_REG register
- *  Register 0 of BLOCK2.
- */
-#define EFUSE_RD_BLK2_DATA0_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_MAC : R; bitpos: [31:0]; default: 0;
- *  MAC address
- */
-#define EFUSE_MAC    0xFFFFFFFFU
-#define EFUSE_MAC_M  (EFUSE_MAC_V << EFUSE_MAC_S)
-#define EFUSE_MAC_V  0xFFFFFFFFU
-#define EFUSE_MAC_S  0
-
-/** EFUSE_RD_BLK2_DATA1_REG register
- *  Register 1 of BLOCK2.
- */
-#define EFUSE_RD_BLK2_DATA1_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_1 : R; bitpos: [15:0]; default: 0;
- *  MAC address
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [19:16]; default: 0;
- *  WAFER_VERSION_MINOR
- */
-#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
-#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_S  16
-/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [21:20]; default: 0;
- *  WAFER_VERSION_MAJOR
- */
-#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_S  20
-/** EFUSE_PKG_VERSION : R; bitpos: [24:22]; default: 0;
- *  EFUSE_PKG_VERSION
- */
-#define EFUSE_PKG_VERSION    0x00000007U
-#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
-#define EFUSE_PKG_VERSION_V  0x00000007U
-#define EFUSE_PKG_VERSION_S  22
-/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [27:25]; default: 0;
- *  Minor version of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MINOR    0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
-#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_S  25
-/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [29:28]; default: 0;
- *  Major version of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
-#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_S  28
-/** EFUSE_OCODE : R; bitpos: [31:30]; default: 0;
- *  OCode
- */
-#define EFUSE_OCODE    0x00000003U
-#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
-#define EFUSE_OCODE_V  0x00000003U
-#define EFUSE_OCODE_S  30
-
-/** EFUSE_RD_BLK2_DATA2_REG register
- *  Register 2 of BLOCK2.
- */
-#define EFUSE_RD_BLK2_DATA2_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_OCODE_1 : R; bitpos: [4:0]; default: 0;
- *  OCode
- */
-#define EFUSE_OCODE_1    0x0000001FU
-#define EFUSE_OCODE_1_M  (EFUSE_OCODE_1_V << EFUSE_OCODE_1_S)
-#define EFUSE_OCODE_1_V  0x0000001FU
-#define EFUSE_OCODE_1_S  0
-/** EFUSE_TEMP_CALIB : R; bitpos: [13:5]; default: 0;
- *  Temperature calibration data
- */
-#define EFUSE_TEMP_CALIB    0x000001FFU
-#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
-#define EFUSE_TEMP_CALIB_V  0x000001FFU
-#define EFUSE_TEMP_CALIB_S  5
-/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [21:14]; default: 0;
- *  ADC1 init code at atten0
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0    0x000000FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_V  0x000000FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_S  14
-/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [26:22]; default: 0;
- *  ADC1 init code at atten3
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN3    0x0000001FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_V  0x0000001FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_S  22
-/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:27]; default: 0;
- *  ADC1 calibration voltage at atten0
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN0    0x0000001FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_V  0x0000001FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_S  27
-
-/** EFUSE_RD_BLK2_DATA3_REG register
- *  Register 3 of BLOCK2.
- */
-#define EFUSE_RD_BLK2_DATA3_REG (DR_REG_EFUSE_BASE + 0x4c)
-/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
- *  ADC1 calibration voltage at atten0
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1    0x00000007U
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V  0x00000007U
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S  0
-/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:3]; default: 0;
- *  ADC1 calibration voltage at atten3
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN3    0x0000003FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_V  0x0000003FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_S  3
-/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [13:9]; default: 0;
- *  BLOCK2 digital dbias when hvt
- */
-#define EFUSE_DIG_DBIAS_HVT    0x0000001FU
-#define EFUSE_DIG_DBIAS_HVT_M  (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
-#define EFUSE_DIG_DBIAS_HVT_V  0x0000001FU
-#define EFUSE_DIG_DBIAS_HVT_S  9
-/** EFUSE_DIG_LDO_SLP_DBIAS2 : R; bitpos: [20:14]; default: 0;
- *  BLOCK2 DIG_LDO_DBG0_DBIAS2
- */
-#define EFUSE_DIG_LDO_SLP_DBIAS2    0x0000007FU
-#define EFUSE_DIG_LDO_SLP_DBIAS2_M  (EFUSE_DIG_LDO_SLP_DBIAS2_V << EFUSE_DIG_LDO_SLP_DBIAS2_S)
-#define EFUSE_DIG_LDO_SLP_DBIAS2_V  0x0000007FU
-#define EFUSE_DIG_LDO_SLP_DBIAS2_S  14
-/** EFUSE_DIG_LDO_SLP_DBIAS26 : R; bitpos: [28:21]; default: 0;
- *  BLOCK2 DIG_LDO_DBG0_DBIAS26
- */
-#define EFUSE_DIG_LDO_SLP_DBIAS26    0x000000FFU
-#define EFUSE_DIG_LDO_SLP_DBIAS26_M  (EFUSE_DIG_LDO_SLP_DBIAS26_V << EFUSE_DIG_LDO_SLP_DBIAS26_S)
-#define EFUSE_DIG_LDO_SLP_DBIAS26_V  0x000000FFU
-#define EFUSE_DIG_LDO_SLP_DBIAS26_S  21
-/** EFUSE_DIG_LDO_ACT_DBIAS26 : R; bitpos: [31:29]; default: 0;
- *  BLOCK2 DIG_LDO_ACT_DBIAS26
- */
-#define EFUSE_DIG_LDO_ACT_DBIAS26    0x00000007U
-#define EFUSE_DIG_LDO_ACT_DBIAS26_M  (EFUSE_DIG_LDO_ACT_DBIAS26_V << EFUSE_DIG_LDO_ACT_DBIAS26_S)
-#define EFUSE_DIG_LDO_ACT_DBIAS26_V  0x00000007U
-#define EFUSE_DIG_LDO_ACT_DBIAS26_S  29
-
-/** EFUSE_RD_BLK2_DATA4_REG register
- *  Register 4 of BLOCK2.
- */
-#define EFUSE_RD_BLK2_DATA4_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_DIG_LDO_ACT_DBIAS26_1 : R; bitpos: [2:0]; default: 0;
- *  BLOCK2 DIG_LDO_ACT_DBIAS26
- */
-#define EFUSE_DIG_LDO_ACT_DBIAS26_1    0x00000007U
-#define EFUSE_DIG_LDO_ACT_DBIAS26_1_M  (EFUSE_DIG_LDO_ACT_DBIAS26_1_V << EFUSE_DIG_LDO_ACT_DBIAS26_1_S)
-#define EFUSE_DIG_LDO_ACT_DBIAS26_1_V  0x00000007U
-#define EFUSE_DIG_LDO_ACT_DBIAS26_1_S  0
-/** EFUSE_DIG_LDO_ACT_STEPD10 : R; bitpos: [6:3]; default: 0;
- *  BLOCK2 DIG_LDO_ACT_STEPD10
- */
-#define EFUSE_DIG_LDO_ACT_STEPD10    0x0000000FU
-#define EFUSE_DIG_LDO_ACT_STEPD10_M  (EFUSE_DIG_LDO_ACT_STEPD10_V << EFUSE_DIG_LDO_ACT_STEPD10_S)
-#define EFUSE_DIG_LDO_ACT_STEPD10_V  0x0000000FU
-#define EFUSE_DIG_LDO_ACT_STEPD10_S  3
-/** EFUSE_RTC_LDO_SLP_DBIAS13 : R; bitpos: [13:7]; default: 0;
- *  BLOCK2 DIG_LDO_SLP_DBIAS13
- */
-#define EFUSE_RTC_LDO_SLP_DBIAS13    0x0000007FU
-#define EFUSE_RTC_LDO_SLP_DBIAS13_M  (EFUSE_RTC_LDO_SLP_DBIAS13_V << EFUSE_RTC_LDO_SLP_DBIAS13_S)
-#define EFUSE_RTC_LDO_SLP_DBIAS13_V  0x0000007FU
-#define EFUSE_RTC_LDO_SLP_DBIAS13_S  7
-/** EFUSE_RTC_LDO_SLP_DBIAS29 : R; bitpos: [22:14]; default: 0;
- *  BLOCK2 DIG_LDO_SLP_DBIAS29
- */
-#define EFUSE_RTC_LDO_SLP_DBIAS29    0x000001FFU
-#define EFUSE_RTC_LDO_SLP_DBIAS29_M  (EFUSE_RTC_LDO_SLP_DBIAS29_V << EFUSE_RTC_LDO_SLP_DBIAS29_S)
-#define EFUSE_RTC_LDO_SLP_DBIAS29_V  0x000001FFU
-#define EFUSE_RTC_LDO_SLP_DBIAS29_S  14
-/** EFUSE_RTC_LDO_SLP_DBIAS31 : R; bitpos: [28:23]; default: 0;
- *  BLOCK2 DIG_LDO_SLP_DBIAS31
- */
-#define EFUSE_RTC_LDO_SLP_DBIAS31    0x0000003FU
-#define EFUSE_RTC_LDO_SLP_DBIAS31_M  (EFUSE_RTC_LDO_SLP_DBIAS31_V << EFUSE_RTC_LDO_SLP_DBIAS31_S)
-#define EFUSE_RTC_LDO_SLP_DBIAS31_V  0x0000003FU
-#define EFUSE_RTC_LDO_SLP_DBIAS31_S  23
-/** EFUSE_RTC_LDO_ACT_DBIAS31 : R; bitpos: [31:29]; default: 0;
- *  BLOCK2 DIG_LDO_ACT_DBIAS31
- */
-#define EFUSE_RTC_LDO_ACT_DBIAS31    0x00000007U
-#define EFUSE_RTC_LDO_ACT_DBIAS31_M  (EFUSE_RTC_LDO_ACT_DBIAS31_V << EFUSE_RTC_LDO_ACT_DBIAS31_S)
-#define EFUSE_RTC_LDO_ACT_DBIAS31_V  0x00000007U
-#define EFUSE_RTC_LDO_ACT_DBIAS31_S  29
-
-/** EFUSE_RD_BLK2_DATA5_REG register
- *  Register 5 of BLOCK2.
- */
-#define EFUSE_RD_BLK2_DATA5_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_RTC_LDO_ACT_DBIAS31_1 : R; bitpos: [2:0]; default: 0;
- *  BLOCK2 DIG_LDO_ACT_DBIAS31
- */
-#define EFUSE_RTC_LDO_ACT_DBIAS31_1    0x00000007U
-#define EFUSE_RTC_LDO_ACT_DBIAS31_1_M  (EFUSE_RTC_LDO_ACT_DBIAS31_1_V << EFUSE_RTC_LDO_ACT_DBIAS31_1_S)
-#define EFUSE_RTC_LDO_ACT_DBIAS31_1_V  0x00000007U
-#define EFUSE_RTC_LDO_ACT_DBIAS31_1_S  0
-/** EFUSE_RTC_LDO_ACT_DBIAS13 : R; bitpos: [10:3]; default: 0;
- *  BLOCK2 DIG_LDO_ACT_DBIAS13
- */
-#define EFUSE_RTC_LDO_ACT_DBIAS13    0x000000FFU
-#define EFUSE_RTC_LDO_ACT_DBIAS13_M  (EFUSE_RTC_LDO_ACT_DBIAS13_V << EFUSE_RTC_LDO_ACT_DBIAS13_S)
-#define EFUSE_RTC_LDO_ACT_DBIAS13_V  0x000000FFU
-#define EFUSE_RTC_LDO_ACT_DBIAS13_S  3
-/** EFUSE_RESERVED_2_171 : R; bitpos: [31:11]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_171    0x001FFFFFU
-#define EFUSE_RESERVED_2_171_M  (EFUSE_RESERVED_2_171_V << EFUSE_RESERVED_2_171_S)
-#define EFUSE_RESERVED_2_171_V  0x001FFFFFU
-#define EFUSE_RESERVED_2_171_S  11
-
-/** EFUSE_RD_BLK2_DATA6_REG register
- *  Register 6 of BLOCK2.
- */
-#define EFUSE_RD_BLK2_DATA6_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_ADC_CALIBRATION_3 : RO; bitpos: [10:0]; default: 0;
- *  Store the bit [86:96] of ADC calibration data.
- */
-#define EFUSE_ADC_CALIBRATION_3    0x000007FFU
-#define EFUSE_ADC_CALIBRATION_3_M  (EFUSE_ADC_CALIBRATION_3_V << EFUSE_ADC_CALIBRATION_3_S)
-#define EFUSE_ADC_CALIBRATION_3_V  0x000007FFU
-#define EFUSE_ADC_CALIBRATION_3_S  0
-/** EFUSE_BLK2_RESERVED_DATA_0 : RO; bitpos: [31:11]; default: 0;
- *  Store the bit [0:20] of block2 reserved data.
- */
-#define EFUSE_BLK2_RESERVED_DATA_0    0x001FFFFFU
-#define EFUSE_BLK2_RESERVED_DATA_0_M  (EFUSE_BLK2_RESERVED_DATA_0_V << EFUSE_BLK2_RESERVED_DATA_0_S)
-#define EFUSE_BLK2_RESERVED_DATA_0_V  0x001FFFFFU
-#define EFUSE_BLK2_RESERVED_DATA_0_S  11
-
-/** EFUSE_RD_BLK2_DATA7_REG register
- *  Register 7 of BLOCK2.
- */
-#define EFUSE_RD_BLK2_DATA7_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_BLK2_RESERVED_DATA_1 : RO; bitpos: [31:0]; default: 0;
- *  Store the bit [21:52] of block2 reserved data.
- */
-#define EFUSE_BLK2_RESERVED_DATA_1    0xFFFFFFFFU
-#define EFUSE_BLK2_RESERVED_DATA_1_M  (EFUSE_BLK2_RESERVED_DATA_1_V << EFUSE_BLK2_RESERVED_DATA_1_S)
-#define EFUSE_BLK2_RESERVED_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_BLK2_RESERVED_DATA_1_S  0
-
-/** EFUSE_RD_BLK3_DATA0_REG register
- *  Register 0 of BLOCK3.
- */
-#define EFUSE_RD_BLK3_DATA0_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_BLK3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Store the first 32-bit of Block3.
- */
-#define EFUSE_BLK3_DATA0    0xFFFFFFFFU
-#define EFUSE_BLK3_DATA0_M  (EFUSE_BLK3_DATA0_V << EFUSE_BLK3_DATA0_S)
-#define EFUSE_BLK3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_BLK3_DATA0_S  0
-
-/** EFUSE_RD_BLK3_DATA1_REG register
- *  Register 1 of BLOCK3.
- */
-#define EFUSE_RD_BLK3_DATA1_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_BLK3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Store the second 32-bit of Block3.
- */
-#define EFUSE_BLK3_DATA1    0xFFFFFFFFU
-#define EFUSE_BLK3_DATA1_M  (EFUSE_BLK3_DATA1_V << EFUSE_BLK3_DATA1_S)
-#define EFUSE_BLK3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_BLK3_DATA1_S  0
-
-/** EFUSE_RD_BLK3_DATA2_REG register
- *  Register 2 of BLOCK3.
- */
-#define EFUSE_RD_BLK3_DATA2_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_BLK3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Store the third 32-bit of Block3.
- */
-#define EFUSE_BLK3_DATA2    0xFFFFFFFFU
-#define EFUSE_BLK3_DATA2_M  (EFUSE_BLK3_DATA2_V << EFUSE_BLK3_DATA2_S)
-#define EFUSE_BLK3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_BLK3_DATA2_S  0
-
-/** EFUSE_RD_BLK3_DATA3_REG register
- *  Register 3 of BLOCK3.
- */
-#define EFUSE_RD_BLK3_DATA3_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_BLK3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Store the fourth 32-bit of Block3.
- */
-#define EFUSE_BLK3_DATA3    0xFFFFFFFFU
-#define EFUSE_BLK3_DATA3_M  (EFUSE_BLK3_DATA3_V << EFUSE_BLK3_DATA3_S)
-#define EFUSE_BLK3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_BLK3_DATA3_S  0
-
-/** EFUSE_RD_BLK3_DATA4_REG register
- *  Register 4 of BLOCK3.
- */
-#define EFUSE_RD_BLK3_DATA4_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_BLK3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Store the fifth 32-bit of Block3.
- */
-#define EFUSE_BLK3_DATA4    0xFFFFFFFFU
-#define EFUSE_BLK3_DATA4_M  (EFUSE_BLK3_DATA4_V << EFUSE_BLK3_DATA4_S)
-#define EFUSE_BLK3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_BLK3_DATA4_S  0
-
-/** EFUSE_RD_BLK3_DATA5_REG register
- *  Register 5 of BLOCK3.
- */
-#define EFUSE_RD_BLK3_DATA5_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_BLK3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Store the sixth 32-bit of Block3.
- */
-#define EFUSE_BLK3_DATA5    0xFFFFFFFFU
-#define EFUSE_BLK3_DATA5_M  (EFUSE_BLK3_DATA5_V << EFUSE_BLK3_DATA5_S)
-#define EFUSE_BLK3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_BLK3_DATA5_S  0
-
-/** EFUSE_RD_BLK3_DATA6_REG register
- *  Register 6 of BLOCK3.
- */
-#define EFUSE_RD_BLK3_DATA6_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_BLK3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Store the seventh 32-bit of Block3.
- */
-#define EFUSE_BLK3_DATA6    0xFFFFFFFFU
-#define EFUSE_BLK3_DATA6_M  (EFUSE_BLK3_DATA6_V << EFUSE_BLK3_DATA6_S)
-#define EFUSE_BLK3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_BLK3_DATA6_S  0
-
-/** EFUSE_RD_BLK3_DATA7_REG register
- *  Register 7 of BLOCK3.
- */
-#define EFUSE_RD_BLK3_DATA7_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_BLK3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Store the eighth 32-bit of Block3.
- */
-#define EFUSE_BLK3_DATA7    0xFFFFFFFFU
-#define EFUSE_BLK3_DATA7_M  (EFUSE_BLK3_DATA7_V << EFUSE_BLK3_DATA7_S)
-#define EFUSE_BLK3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_BLK3_DATA7_S  0
-
-/** EFUSE_RD_REPEAT_ERR_REG register
- *  Programming error record register 0 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [1:0]; default: 0;
- *  If any bit in RD_DIS is 1, then it indicates a programming error.
- */
-#define EFUSE_RD_DIS_ERR    0x00000003U
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x00000003U
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [3:2]; default: 0;
- *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  2
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [4]; default: 0;
- *  If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(4))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  4
-/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [5]; default: 0;
- *  If any bit in this filed is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(5))
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  5
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [6]; default: 0;
- *  If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming
- *  error.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(6))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  6
-/** EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR : RO; bitpos: [9:7]; default: 0;
- *  If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming
- *  error.
- */
-#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S  7
-/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [10]; default: 0;
- *  If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.
- */
-#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(10))
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  10
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [12:11]; default: 0;
- *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  11
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
- *  If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [14]; default: 0;
- *  If any bit in this filed is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(14))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  14
-/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [15]; default: 0;
- *  If any bit in this filed is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(15))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  15
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [16]; default: 0;
- *  If any bit in this filed is 1, then it indicates a programming error.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(16))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  16
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [20:17]; default: 0;
- *  If any bit in this filed is 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  17
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [21]; default: 0;
- *  If any bit in this filed is 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  21
-/** EFUSE_RPT4_RESERVED_ERR : RO; bitpos: [31:22]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED_ERR    0x000003FFU
-#define EFUSE_RPT4_RESERVED_ERR_M  (EFUSE_RPT4_RESERVED_ERR_V << EFUSE_RPT4_RESERVED_ERR_S)
-#define EFUSE_RPT4_RESERVED_ERR_V  0x000003FFU
-#define EFUSE_RPT4_RESERVED_ERR_S  22
-
-/** EFUSE_RD_RS_ERR_REG register
- *  Programming error record register 0 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_BLK1_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes in block1.
- */
-#define EFUSE_BLK1_ERR_NUM    0x00000007U
-#define EFUSE_BLK1_ERR_NUM_M  (EFUSE_BLK1_ERR_NUM_V << EFUSE_BLK1_ERR_NUM_S)
-#define EFUSE_BLK1_ERR_NUM_V  0x00000007U
-#define EFUSE_BLK1_ERR_NUM_S  0
-/** EFUSE_BLK1_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of block1 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_BLK1_FAIL    (BIT(3))
-#define EFUSE_BLK1_FAIL_M  (EFUSE_BLK1_FAIL_V << EFUSE_BLK1_FAIL_S)
-#define EFUSE_BLK1_FAIL_V  0x00000001U
-#define EFUSE_BLK1_FAIL_S  3
-/** EFUSE_BLK2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes in block2.
- */
-#define EFUSE_BLK2_ERR_NUM    0x00000007U
-#define EFUSE_BLK2_ERR_NUM_M  (EFUSE_BLK2_ERR_NUM_V << EFUSE_BLK2_ERR_NUM_S)
-#define EFUSE_BLK2_ERR_NUM_V  0x00000007U
-#define EFUSE_BLK2_ERR_NUM_S  4
-/** EFUSE_BLK2_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of block2 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_BLK2_FAIL    (BIT(7))
-#define EFUSE_BLK2_FAIL_M  (EFUSE_BLK2_FAIL_V << EFUSE_BLK2_FAIL_S)
-#define EFUSE_BLK2_FAIL_V  0x00000001U
-#define EFUSE_BLK2_FAIL_S  7
-/** EFUSE_BLK3_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  The value of this signal means the number of error bytes in block3.
- */
-#define EFUSE_BLK3_ERR_NUM    0x00000007U
-#define EFUSE_BLK3_ERR_NUM_M  (EFUSE_BLK3_ERR_NUM_V << EFUSE_BLK3_ERR_NUM_S)
-#define EFUSE_BLK3_ERR_NUM_V  0x00000007U
-#define EFUSE_BLK3_ERR_NUM_S  8
-/** EFUSE_BLK3_FAIL : RO; bitpos: [11]; default: 0;
- *  0: Means no failure and that the block3 data is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_BLK3_FAIL    (BIT(11))
-#define EFUSE_BLK3_FAIL_M  (EFUSE_BLK3_FAIL_V << EFUSE_BLK3_FAIL_S)
-#define EFUSE_BLK3_FAIL_V  0x00000001U
-#define EFUSE_BLK3_FAIL_S  11
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_EFUSE_MEM_FORCE_PD_M  (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_EFUSE_MEM_FORCE_PU_M  (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit and force to enable clock signal of eFuse memory.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
- *  The value of OTP_LOAD_SW.
- */
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
-#define EFUSE_OTP_LOAD_SW_V  0x00000001U
-#define EFUSE_OTP_LOAD_SW_S  4
-/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
- *  The value of OTP_VDDQ_C_SYNC2.
- */
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
- *  The value of OTP_STROBE_SW.
- */
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
-#define EFUSE_OTP_STROBE_SW_V  0x00000001U
-#define EFUSE_OTP_STROBE_SW_S  6
-/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
- *  The value of OTP_CSB_SW.
- */
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
-#define EFUSE_OTP_CSB_SW_V  0x00000001U
-#define EFUSE_OTP_CSB_SW_S  7
-/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
- *  The value of OTP_PGENB_SW.
- */
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
-#define EFUSE_OTP_PGENB_SW_V  0x00000001U
-#define EFUSE_OTP_PGENB_SW_S  8
-/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
- *  The value of OTP_VDDQ_IS_SW.
- */
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [15:10]; default: 0;
- *  Record the number of bit '1' in BLOCK0.
- */
-#define EFUSE_BLK0_VALID_BIT_CNT    0x0000003FU
-#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x0000003FU
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [3:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-3 corresponds to block
- *  number 0-3, respectively.
- */
-#define EFUSE_BLK_NUM    0x00000003U
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x00000003U
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_READ_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures hold time for efuse read.
- */
-#define EFUSE_THR_A    0x000000FFU
-#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
-#define EFUSE_THR_A_V  0x000000FFU
-#define EFUSE_THR_A_S  0
-/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
- *  Configures pulse time for efuse read.
- */
-#define EFUSE_TRD    0x000000FFU
-#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
-#define EFUSE_TRD_V  0x000000FFU
-#define EFUSE_TRD_S  8
-/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
- *  Configures setup time for efuse read.
- */
-#define EFUSE_TSUR_A    0x000000FFU
-#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
-#define EFUSE_TSUR_A_V  0x000000FFU
-#define EFUSE_TSUR_A_S  16
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
- *  Configures the initial read time of eFuse.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF0_REG register
- *  Configurarion register 0 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures hold time for efuse program.
- */
-#define EFUSE_THP_A    0x000000FFU
-#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
-#define EFUSE_THP_A_V  0x000000FFU
-#define EFUSE_THP_A_S  0
-/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1;
- *  Configures pulse time for burning '0' bit.
- */
-#define EFUSE_TPGM_INACTIVE    0x000000FFU
-#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
-#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
-#define EFUSE_TPGM_INACTIVE_S  8
-/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200;
- *  Configures pulse time for burning '1' bit.
- */
-#define EFUSE_TPGM    0x0000FFFFU
-#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
-#define EFUSE_TPGM_V  0x0000FFFFU
-#define EFUSE_TPGM_S  16
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures setup time for efuse program.
- */
-#define EFUSE_TSUP_A    0x000000FFU
-#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
-#define EFUSE_TSUP_A_V  0x000000FFU
-#define EFUSE_TSUP_A_S  0
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34636176;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c2/include/soc/efuse_struct.h b/components/soc/esp32c2/include/soc/efuse_struct.h
deleted file mode 100644
index c30ded3f9c9..00000000000
--- a/components/soc/esp32c2/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,1084 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PGM Data Register */
-/** Type of pgm_data0 register
- *  Register 0 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Register 1 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 1st 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Register 2 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 2nd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Register 3 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 3rd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Register 4 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 4th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Register 5 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 5th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Register 6 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 6th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Register 7 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 7th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-/** Type of pgm_check_value0 register
- *  Register 0 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 0th 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Register 1 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 1st 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Register 2 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 2nd 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: Read Data Register */
-/** Type of rd_wr_dis register
- *  BLOCK0 data register 0.
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [7:0]; default: 0;
-         *  Disable programming of individual eFuses.
-         */
-        uint32_t wr_dis:8;
-        /** reserved_0_8 : RW; bitpos: [31:8]; default: 0; */
-        uint32_t reserved_0_8:24;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  BLOCK0 data register 1.
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [1:0]; default: 0;
-         *  The bit be set to disable software read high/low 128-bit of BLK3.
-         */
-        uint32_t rd_dis:2;
-        /** wdt_delay_sel : RO; bitpos: [3:2]; default: 0;
-         *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
-         *  80000. 2: 160000. 3:320000.
-         */
-        uint32_t wdt_delay_sel:2;
-        /** dis_pad_jtag : RO; bitpos: [4]; default: 0;
-         *  Set this bit to disable pad jtag.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_icache : RO; bitpos: [5]; default: 0;
-         *  The bit be set to disable icache in download mode.
-         */
-        uint32_t dis_download_icache:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [6]; default: 0;
-         *  The bit be set to disable manual encryption.
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** spi_boot_crypt_cnt : RO; bitpos: [9:7]; default: 0;
-         *  These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
-         *  number of 1: disable.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** xts_key_length_256 : RO; bitpos: [10]; default: 0;
-         *  The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise,
-         *  XTS_AES use 128-bit eFuse data in BLOCK3.
-         */
-        uint32_t xts_key_length_256:1;
-        /** uart_print_control : RO; bitpos: [12:11]; default: 0;
-         *  Set this bit to disable usb printing.
-         */
-        uint32_t uart_print_control:2;
-        /** force_send_resume : RO; bitpos: [13]; default: 0;
-         *  Set this bit to force ROM code to send a resume command during SPI boot.
-         */
-        uint32_t force_send_resume:1;
-        /** dis_download_mode : RO; bitpos: [14]; default: 0;
-         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [15]; default: 0;
-         *  This bit set means disable direct_boot mode.
-         */
-        uint32_t dis_direct_boot:1;
-        /** enable_security_download : RO; bitpos: [16]; default: 0;
-         *  Set this bit to enable secure UART download mode.
-         */
-        uint32_t enable_security_download:1;
-        /** flash_tpuw : RO; bitpos: [20:17]; default: 0;
-         *  Configures flash waiting time after power-up, in unit of ms. If the value is less
-         *  than 15, the waiting time is the configurable value.  Otherwise, the waiting time
-         *  is twice the configurable value.
-         */
-        uint32_t flash_tpuw:4;
-        /** secure_boot_en : RO; bitpos: [21]; default: 0;
-         *  The bit be set to enable secure boot.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_version : R; bitpos: [25:22]; default: 0;
-         *  Secure version for anti-rollback
-         */
-        uint32_t secure_version:4;
-        /** custom_mac_used : R; bitpos: [26]; default: 0;
-         *  True if MAC_CUSTOM is burned
-         */
-        uint32_t custom_mac_used:1;
-        /** disable_wafer_version_major : R; bitpos: [27]; default: 0;
-         *  Disables check of wafer version major
-         */
-        uint32_t disable_wafer_version_major:1;
-        /** disable_blk_version_major : R; bitpos: [28]; default: 0;
-         *  Disables check of blk version major
-         */
-        uint32_t disable_blk_version_major:1;
-        /** reserved_0_61 : R; bitpos: [31:29]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_0_61:3;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_blk1_data0 register
- *  BLOCK1 data register 0.
- */
-typedef union {
-    struct {
-        /** custom_mac : R; bitpos: [31:0]; default: 0;
-         *  Custom MAC address
-         */
-        uint32_t custom_mac:32;
-    };
-    uint32_t val;
-} efuse_rd_blk1_data0_reg_t;
-
-/** Type of rd_blk1_data1 register
- *  BLOCK1 data register 1.
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [15:0]; default: 0;
-         *  Custom MAC address
-         */
-        uint32_t custom_mac_1:16;
-        /** reserved_1_48 : R; bitpos: [31:16]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_48:16;
-    };
-    uint32_t val;
-} efuse_rd_blk1_data1_reg_t;
-
-/** Type of rd_blk1_data2 register
- *  BLOCK1 data register 2.
- */
-typedef union {
-    struct {
-        /** system_data2 : RO; bitpos: [23:0]; default: 0;
-         *  Stores the bits [64:87] of system data.
-         */
-        uint32_t system_data2:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_rd_blk1_data2_reg_t;
-
-/** Type of rd_blk2_data0 register
- *  Register 0 of BLOCK2.
- */
-typedef union {
-    struct {
-        /** mac : R; bitpos: [31:0]; default: 0;
-         *  MAC address
-         */
-        uint32_t mac:32;
-    };
-    uint32_t val;
-} efuse_rd_blk2_data0_reg_t;
-
-/** Type of rd_blk2_data1 register
- *  Register 1 of BLOCK2.
- */
-typedef union {
-    struct {
-        /** mac_1 : R; bitpos: [15:0]; default: 0;
-         *  MAC address
-         */
-        uint32_t mac_1:16;
-        /** wafer_version_minor : R; bitpos: [19:16]; default: 0;
-         *  WAFER_VERSION_MINOR
-         */
-        uint32_t wafer_version_minor:4;
-        /** wafer_version_major : R; bitpos: [21:20]; default: 0;
-         *  WAFER_VERSION_MAJOR
-         */
-        uint32_t wafer_version_major:2;
-        /** pkg_version : R; bitpos: [24:22]; default: 0;
-         *  EFUSE_PKG_VERSION
-         */
-        uint32_t pkg_version:3;
-        /** blk_version_minor : R; bitpos: [27:25]; default: 0;
-         *  Minor version of BLOCK2
-         */
-        uint32_t blk_version_minor:3;
-        /** blk_version_major : R; bitpos: [29:28]; default: 0;
-         *  Major version of BLOCK2
-         */
-        uint32_t blk_version_major:2;
-        /** ocode : R; bitpos: [31:30]; default: 0;
-         *  OCode
-         */
-        uint32_t ocode:2;
-    };
-    uint32_t val;
-} efuse_rd_blk2_data1_reg_t;
-
-/** Type of rd_blk2_data2 register
- *  Register 2 of BLOCK2.
- */
-typedef union {
-    struct {
-        /** ocode_1 : R; bitpos: [4:0]; default: 0;
-         *  OCode
-         */
-        uint32_t ocode_1:5;
-        /** temp_calib : R; bitpos: [13:5]; default: 0;
-         *  Temperature calibration data
-         */
-        uint32_t temp_calib:9;
-        /** adc1_init_code_atten0 : R; bitpos: [21:14]; default: 0;
-         *  ADC1 init code at atten0
-         */
-        uint32_t adc1_init_code_atten0:8;
-        /** adc1_init_code_atten3 : R; bitpos: [26:22]; default: 0;
-         *  ADC1 init code at atten3
-         */
-        uint32_t adc1_init_code_atten3:5;
-        /** adc1_cal_vol_atten0 : R; bitpos: [31:27]; default: 0;
-         *  ADC1 calibration voltage at atten0
-         */
-        uint32_t adc1_cal_vol_atten0:5;
-    };
-    uint32_t val;
-} efuse_rd_blk2_data2_reg_t;
-
-/** Type of rd_blk2_data3 register
- *  Register 3 of BLOCK2.
- */
-typedef union {
-    struct {
-        /** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0;
-         *  ADC1 calibration voltage at atten0
-         */
-        uint32_t adc1_cal_vol_atten0_1:3;
-        /** adc1_cal_vol_atten3 : R; bitpos: [8:3]; default: 0;
-         *  ADC1 calibration voltage at atten3
-         */
-        uint32_t adc1_cal_vol_atten3:6;
-        /** dig_dbias_hvt : R; bitpos: [13:9]; default: 0;
-         *  BLOCK2 digital dbias when hvt
-         */
-        uint32_t dig_dbias_hvt:5;
-        /** dig_ldo_slp_dbias2 : R; bitpos: [20:14]; default: 0;
-         *  BLOCK2 DIG_LDO_DBG0_DBIAS2
-         */
-        uint32_t dig_ldo_slp_dbias2:7;
-        /** dig_ldo_slp_dbias26 : R; bitpos: [28:21]; default: 0;
-         *  BLOCK2 DIG_LDO_DBG0_DBIAS26
-         */
-        uint32_t dig_ldo_slp_dbias26:8;
-        /** dig_ldo_act_dbias26 : R; bitpos: [31:29]; default: 0;
-         *  BLOCK2 DIG_LDO_ACT_DBIAS26
-         */
-        uint32_t dig_ldo_act_dbias26:3;
-    };
-    uint32_t val;
-} efuse_rd_blk2_data3_reg_t;
-
-/** Type of rd_blk2_data4 register
- *  Register 4 of BLOCK2.
- */
-typedef union {
-    struct {
-        /** dig_ldo_act_dbias26_1 : R; bitpos: [2:0]; default: 0;
-         *  BLOCK2 DIG_LDO_ACT_DBIAS26
-         */
-        uint32_t dig_ldo_act_dbias26_1:3;
-        /** dig_ldo_act_stepd10 : R; bitpos: [6:3]; default: 0;
-         *  BLOCK2 DIG_LDO_ACT_STEPD10
-         */
-        uint32_t dig_ldo_act_stepd10:4;
-        /** rtc_ldo_slp_dbias13 : R; bitpos: [13:7]; default: 0;
-         *  BLOCK2 DIG_LDO_SLP_DBIAS13
-         */
-        uint32_t rtc_ldo_slp_dbias13:7;
-        /** rtc_ldo_slp_dbias29 : R; bitpos: [22:14]; default: 0;
-         *  BLOCK2 DIG_LDO_SLP_DBIAS29
-         */
-        uint32_t rtc_ldo_slp_dbias29:9;
-        /** rtc_ldo_slp_dbias31 : R; bitpos: [28:23]; default: 0;
-         *  BLOCK2 DIG_LDO_SLP_DBIAS31
-         */
-        uint32_t rtc_ldo_slp_dbias31:6;
-        /** rtc_ldo_act_dbias31 : R; bitpos: [31:29]; default: 0;
-         *  BLOCK2 DIG_LDO_ACT_DBIAS31
-         */
-        uint32_t rtc_ldo_act_dbias31:3;
-    };
-    uint32_t val;
-} efuse_rd_blk2_data4_reg_t;
-
-/** Type of rd_blk2_data5 register
- *  Register 5 of BLOCK2.
- */
-typedef union {
-    struct {
-        /** rtc_ldo_act_dbias31_1 : R; bitpos: [2:0]; default: 0;
-         *  BLOCK2 DIG_LDO_ACT_DBIAS31
-         */
-        uint32_t rtc_ldo_act_dbias31_1:3;
-        /** rtc_ldo_act_dbias13 : R; bitpos: [10:3]; default: 0;
-         *  BLOCK2 DIG_LDO_ACT_DBIAS13
-         */
-        uint32_t rtc_ldo_act_dbias13:8;
-        /** reserved_2_171 : R; bitpos: [31:11]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_171:21;
-    };
-    uint32_t val;
-} efuse_rd_blk2_data5_reg_t;
-
-/** Type of rd_blk2_data6 register
- *  Register 6 of BLOCK2.
- */
-typedef union {
-    struct {
-        /** adc_calibration_3 : RO; bitpos: [10:0]; default: 0;
-         *  Store the bit [86:96] of ADC calibration data.
-         */
-        uint32_t adc_calibration_3:11;
-        /** blk2_reserved_data_0 : RO; bitpos: [31:11]; default: 0;
-         *  Store the bit [0:20] of block2 reserved data.
-         */
-        uint32_t blk2_reserved_data_0:21;
-    };
-    uint32_t val;
-} efuse_rd_blk2_data6_reg_t;
-
-/** Type of rd_blk2_data7 register
- *  Register 7 of BLOCK2.
- */
-typedef union {
-    struct {
-        /** blk2_reserved_data_1 : RO; bitpos: [31:0]; default: 0;
-         *  Store the bit [21:52] of block2 reserved data.
-         */
-        uint32_t blk2_reserved_data_1:32;
-    };
-    uint32_t val;
-} efuse_rd_blk2_data7_reg_t;
-
-/** Type of rd_blk3_data0 register
- *  Register 0 of BLOCK3.
- */
-typedef union {
-    struct {
-        /** blk3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Store the first 32-bit of Block3.
-         */
-        uint32_t blk3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_blk3_data0_reg_t;
-
-/** Type of rd_blk3_data1 register
- *  Register 1 of BLOCK3.
- */
-typedef union {
-    struct {
-        /** blk3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Store the second 32-bit of Block3.
-         */
-        uint32_t blk3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_blk3_data1_reg_t;
-
-/** Type of rd_blk3_data2 register
- *  Register 2 of BLOCK3.
- */
-typedef union {
-    struct {
-        /** blk3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Store the third 32-bit of Block3.
-         */
-        uint32_t blk3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_blk3_data2_reg_t;
-
-/** Type of rd_blk3_data3 register
- *  Register 3 of BLOCK3.
- */
-typedef union {
-    struct {
-        /** blk3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Store the fourth 32-bit of Block3.
-         */
-        uint32_t blk3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_blk3_data3_reg_t;
-
-/** Type of rd_blk3_data4 register
- *  Register 4 of BLOCK3.
- */
-typedef union {
-    struct {
-        /** blk3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Store the fifth 32-bit of Block3.
-         */
-        uint32_t blk3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_blk3_data4_reg_t;
-
-/** Type of rd_blk3_data5 register
- *  Register 5 of BLOCK3.
- */
-typedef union {
-    struct {
-        /** blk3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Store the sixth 32-bit of Block3.
-         */
-        uint32_t blk3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_blk3_data5_reg_t;
-
-/** Type of rd_blk3_data6 register
- *  Register 6 of BLOCK3.
- */
-typedef union {
-    struct {
-        /** blk3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Store the seventh 32-bit of Block3.
-         */
-        uint32_t blk3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_blk3_data6_reg_t;
-
-/** Type of rd_blk3_data7 register
- *  Register 7 of BLOCK3.
- */
-typedef union {
-    struct {
-        /** blk3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Store the eighth 32-bit of Block3.
-         */
-        uint32_t blk3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_blk3_data7_reg_t;
-
-
-/** Group: Report Register */
-/** Type of rd_repeat_err register
- *  Programming error record register 0 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [1:0]; default: 0;
-         *  If any bit in RD_DIS is 1, then it indicates a programming error.
-         */
-        uint32_t rd_dis_err:2;
-        /** wdt_delay_sel_err : RO; bitpos: [3:2]; default: 0;
-         *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** dis_pad_jtag_err : RO; bitpos: [4]; default: 0;
-         *  If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_icache_err : RO; bitpos: [5]; default: 0;
-         *  If any bit in this filed is 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_icache_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [6]; default: 0;
-         *  If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming
-         *  error.
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** spi_boot_encrypt_decrypt_cnt_err : RO; bitpos: [9:7]; default: 0;
-         *  If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming
-         *  error.
-         */
-        uint32_t spi_boot_encrypt_decrypt_cnt_err:3;
-        /** xts_key_length_256_err : RO; bitpos: [10]; default: 0;
-         *  If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.
-         */
-        uint32_t xts_key_length_256_err:1;
-        /** uart_print_control_err : RO; bitpos: [12:11]; default: 0;
-         *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
-         */
-        uint32_t uart_print_control_err:2;
-        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
-         *  If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.
-         */
-        uint32_t force_send_resume_err:1;
-        /** dis_download_mode_err : RO; bitpos: [14]; default: 0;
-         *  If any bit in this filed is 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [15]; default: 0;
-         *  If any bit in this filed is 1, then it indicates a programming error.
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** enable_security_download_err : RO; bitpos: [16]; default: 0;
-         *  If any bit in this filed is 1, then it indicates a programming error.
-         */
-        uint32_t enable_security_download_err:1;
-        /** flash_tpuw_err : RO; bitpos: [20:17]; default: 0;
-         *  If any bit in this filed is 1, then it indicates a programming error.
-         */
-        uint32_t flash_tpuw_err:4;
-        /** secure_boot_en_err : RO; bitpos: [21]; default: 0;
-         *  If any bit in this filed is 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_en_err:1;
-        /** rpt4_reserved_err : RO; bitpos: [31:22]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved_err:10;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err_reg_t;
-
-/** Type of rd_rs_err register
- *  Programming error record register 0 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** blk1_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes in block1.
-         */
-        uint32_t blk1_err_num:3;
-        /** blk1_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of block1 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t blk1_fail:1;
-        /** blk2_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes in block2.
-         */
-        uint32_t blk2_err_num:3;
-        /** blk2_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of block2 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t blk2_fail:1;
-        /** blk3_err_num : RO; bitpos: [10:8]; default: 0;
-         *  The value of this signal means the number of error bytes in block3.
-         */
-        uint32_t blk3_err_num:3;
-        /** blk3_fail : RO; bitpos: [11]; default: 0;
-         *  0: Means no failure and that the block3 data is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t blk3_fail:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} efuse_rd_rs_err_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t efuse_mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t efuse_mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit and force to enable clock signal of eFuse memory.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuraiton register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
-         */
-        uint32_t op_code:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [3:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-3 corresponds to block
-         *  number 0-3, respectively.
-         */
-        uint32_t blk_num:2;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures hold time for efuse read.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures pulse time for efuse read.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures setup time for efuse read.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
-         *  Configures the initial read time of eFuse.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf0 register
- *  Configurarion register 0 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** thp_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures hold time for efuse program.
-         */
-        uint32_t thp_a:8;
-        /** tpgm_inactive : R/W; bitpos: [15:8]; default: 1;
-         *  Configures pulse time for burning '0' bit.
-         */
-        uint32_t tpgm_inactive:8;
-        /** tpgm : R/W; bitpos: [31:16]; default: 200;
-         *  Configures pulse time for burning '1' bit.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures setup time for efuse program.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** blk0_valid_bit_cnt : RO; bitpos: [15:10]; default: 0;
-         *  Record the number of bit '1' in BLOCK0.
-         */
-        uint32_t blk0_valid_bit_cnt:6;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 34636176;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_blk1_data0_reg_t rd_blk1_data0;
-    volatile efuse_rd_blk1_data1_reg_t rd_blk1_data1;
-    volatile efuse_rd_blk1_data2_reg_t rd_blk1_data2;
-    volatile efuse_rd_blk2_data0_reg_t rd_blk2_data0;
-    volatile efuse_rd_blk2_data1_reg_t rd_blk2_data1;
-    volatile efuse_rd_blk2_data2_reg_t rd_blk2_data2;
-    volatile efuse_rd_blk2_data3_reg_t rd_blk2_data3;
-    volatile efuse_rd_blk2_data4_reg_t rd_blk2_data4;
-    volatile efuse_rd_blk2_data5_reg_t rd_blk2_data5;
-    volatile efuse_rd_blk2_data6_reg_t rd_blk2_data6;
-    volatile efuse_rd_blk2_data7_reg_t rd_blk2_data7;
-    volatile efuse_rd_blk3_data0_reg_t rd_blk3_data0;
-    volatile efuse_rd_blk3_data1_reg_t rd_blk3_data1;
-    volatile efuse_rd_blk3_data2_reg_t rd_blk3_data2;
-    volatile efuse_rd_blk3_data3_reg_t rd_blk3_data3;
-    volatile efuse_rd_blk3_data4_reg_t rd_blk3_data4;
-    volatile efuse_rd_blk3_data5_reg_t rd_blk3_data5;
-    volatile efuse_rd_blk3_data6_reg_t rd_blk3_data6;
-    volatile efuse_rd_blk3_data7_reg_t rd_blk3_data7;
-    volatile efuse_rd_repeat_err_reg_t rd_repeat_err;
-    volatile efuse_rd_rs_err_reg_t rd_rs_err;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    uint32_t reserved_0a0[24];
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf0_reg_t wr_tim_conf0;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    uint32_t reserved_11c[56];
-    volatile efuse_date_reg_t date;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c2/include/soc/interrupt_reg.h b/components/soc/esp32c2/include/soc/interrupt_reg.h
index 749a2e92167..d02c2d5c20c 100644
--- a/components/soc/esp32c2/include/soc/interrupt_reg.h
+++ b/components/soc/esp32c2/include/soc/interrupt_reg.h
@@ -5,7 +5,7 @@
  */
 #pragma once
 
-#include "interrupt_core0_reg.h"
+#include "soc/interrupt_core0_reg.h"
 
 #define INTERRUPT_CURRENT_CORE_INT_THRESH_REG   INTERRUPT_CORE0_CPU_INT_THRESH_REG
 #define INTERRUPT_PRIO_REG(n)                   (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
diff --git a/components/soc/esp32c2/include/soc/io_mux_reg.h b/components/soc/esp32c2/include/soc/io_mux_reg.h
deleted file mode 100644
index b54614e4778..00000000000
--- a/components/soc/esp32c2/include/soc/io_mux_reg.h
+++ /dev/null
@@ -1,286 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_IO_MUX_REG_H_
-#define _SOC_IO_MUX_REG_H_
-
-#pragma once
-#include "soc.h"
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Pin used for wakeup from sleep */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
-#define FILTER_EN (BIT(15))
-#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
-#define FILTER_EN_V 1
-#define FILTER_EN_S 15
-
-#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-
-
-#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
-
-#define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_XTAL_32K_P_U
-#define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_XTAL_32K_N_U
-#define IO_MUX_GPIO2_REG               PERIPHS_IO_MUX_GPIO2_U
-#define IO_MUX_GPIO3_REG               PERIPHS_IO_MUX_GPIO3_U
-#define IO_MUX_GPIO4_REG               PERIPHS_IO_MUX_MTMS_U
-#define IO_MUX_GPIO5_REG               PERIPHS_IO_MUX_MTDI_U
-#define IO_MUX_GPIO6_REG               PERIPHS_IO_MUX_MTCK_U
-#define IO_MUX_GPIO7_REG               PERIPHS_IO_MUX_MTDO_U
-#define IO_MUX_GPIO8_REG               PERIPHS_IO_MUX_GPIO8_U
-#define IO_MUX_GPIO9_REG               PERIPHS_IO_MUX_GPIO9_U
-#define IO_MUX_GPIO10_REG              PERIPHS_IO_MUX_GPIO10_U
-#define IO_MUX_GPIO11_REG              PERIPHS_IO_MUX_VDD_SPI_U
-#define IO_MUX_GPIO12_REG              PERIPHS_IO_MUX_SPIHD_U
-#define IO_MUX_GPIO13_REG              PERIPHS_IO_MUX_SPIWP_U
-#define IO_MUX_GPIO14_REG              PERIPHS_IO_MUX_SPICS0_U
-#define IO_MUX_GPIO15_REG              PERIPHS_IO_MUX_SPICLK_U
-#define IO_MUX_GPIO16_REG              PERIPHS_IO_MUX_SPID_U
-#define IO_MUX_GPIO17_REG              PERIPHS_IO_MUX_SPIQ_U
-#define IO_MUX_GPIO18_REG              PERIPHS_IO_MUX_GPIO18_U
-#define IO_MUX_GPIO19_REG              PERIPHS_IO_MUX_U0RXD_U
-#define IO_MUX_GPIO20_REG              PERIPHS_IO_MUX_U0TXD_U
-
-#define PIN_FUNC_GPIO								1
-
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
-#define SPI_HD_GPIO_NUM              12
-#define SPI_WP_GPIO_NUM              13
-#define SPI_CS0_GPIO_NUM             14
-#define SPI_CLK_GPIO_NUM             15
-#define SPI_D_GPIO_NUM               16
-#define SPI_Q_GPIO_NUM               17
-
-#define EXT_OSC_SLOW_GPIO_NUM        0
-
-#define MAX_RTC_GPIO_NUM              5
-#define MAX_PAD_GPIO_NUM             20
-#define MAX_GPIO_NUM                 24
-#define DIG_IO_HOLD_BIT_SHIFT         0
-
-
-#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
-#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
-#define PAD_POWER_SEL                               BIT(15)
-#define PAD_POWER_SEL_V                             0x1
-#define PAD_POWER_SEL_M                             BIT(15)
-#define PAD_POWER_SEL_S                             15
-
-#define PAD_POWER_SWITCH_DELAY                      0x7
-#define PAD_POWER_SWITCH_DELAY_V                    0x7
-#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
-#define PAD_POWER_SWITCH_DELAY_S                    12
-
-#define CLK_OUT3                                    0xf
-#define CLK_OUT3_V                                  CLK_OUT3
-#define CLK_OUT3_S                                  8
-#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
-#define CLK_OUT2                                    0xf
-#define CLK_OUT2_V                                  CLK_OUT2
-#define CLK_OUT2_S                                  4
-#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
-#define CLK_OUT1                                    0xf
-#define CLK_OUT1_V                                  CLK_OUT1
-#define CLK_OUT1_S                                  0
-#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
-// definitions above are inherited from previous version of code, should double check
-
-// definitions below are generated from pin_txt.csv
-#define PERIPHS_IO_MUX_XTAL_32K_P_U           (REG_IO_MUX_BASE + 0x4)
-#define FUNC_XTAL_32K_P_GPIO0                                       1
-#define FUNC_XTAL_32K_P_GPIO0_0                                     0
-
-#define PERIPHS_IO_MUX_XTAL_32K_N_U           (REG_IO_MUX_BASE + 0x8)
-#define FUNC_XTAL_32K_N_GPIO1                                       1
-#define FUNC_XTAL_32K_N_GPIO1_0                                     0
-
-#define PERIPHS_IO_MUX_GPIO2_U                (REG_IO_MUX_BASE + 0xC)
-#define FUNC_GPIO2_FSPIQ                                            2
-#define FUNC_GPIO2_GPIO2                                            1
-#define FUNC_GPIO2_GPIO2_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO3_U               (REG_IO_MUX_BASE + 0x10)
-#define FUNC_GPIO3_GPIO3                                            1
-#define FUNC_GPIO3_GPIO3_0                                          0
-
-#define PERIPHS_IO_MUX_MTMS_U                (REG_IO_MUX_BASE + 0x14)
-#define FUNC_MTMS_FSPIHD                                            2
-#define FUNC_MTMS_GPIO4                                             1
-#define FUNC_MTMS_MTMS                                              0
-
-#define PERIPHS_IO_MUX_MTDI_U                (REG_IO_MUX_BASE + 0x18)
-#define FUNC_MTDI_FSPIWP                                            2
-#define FUNC_MTDI_GPIO5                                             1
-#define FUNC_MTDI_MTDI                                              0
-
-#define PERIPHS_IO_MUX_MTCK_U                (REG_IO_MUX_BASE + 0x1C)
-#define FUNC_MTCK_FSPICLK                                           2
-#define FUNC_MTCK_GPIO6                                             1
-#define FUNC_MTCK_MTCK                                              0
-
-#define PERIPHS_IO_MUX_MTDO_U                (REG_IO_MUX_BASE + 0x20)
-#define FUNC_MTDO_FSPID                                             2
-#define FUNC_MTDO_GPIO7                                             1
-#define FUNC_MTDO_MTDO                                              0
-
-#define PERIPHS_IO_MUX_GPIO8_U               (REG_IO_MUX_BASE + 0x24)
-#define FUNC_GPIO8_GPIO8                                            1
-#define FUNC_GPIO8_GPIO8_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO9_U               (REG_IO_MUX_BASE + 0x28)
-#define FUNC_GPIO9_GPIO9                                            1
-#define FUNC_GPIO9_GPIO9_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO10_U              (REG_IO_MUX_BASE + 0x2C)
-#define FUNC_GPIO10_FSPICS0                                         2
-#define FUNC_GPIO10_GPIO10                                          1
-#define FUNC_GPIO10_GPIO10_0                                        0
-
-#define PERIPHS_IO_MUX_VDD_SPI_U             (REG_IO_MUX_BASE + 0x30)
-#define FUNC_VDD_SPI_GPIO11                                         1
-#define FUNC_VDD_SPI_GPIO11_0                                       0
-
-#define PERIPHS_IO_MUX_SPIHD_U               (REG_IO_MUX_BASE + 0x34)
-#define FUNC_SPIHD_GPIO12                                           1
-#define FUNC_SPIHD_SPIHD                                            0
-
-#define PERIPHS_IO_MUX_SPIWP_U               (REG_IO_MUX_BASE + 0x38)
-#define FUNC_SPIWP_GPIO13                                           1
-#define FUNC_SPIWP_SPIWP                                            0
-
-#define PERIPHS_IO_MUX_SPICS0_U              (REG_IO_MUX_BASE + 0x3C)
-#define FUNC_SPICS0_GPIO14                                          1
-#define FUNC_SPICS0_SPICS0                                          0
-
-#define PERIPHS_IO_MUX_SPICLK_U              (REG_IO_MUX_BASE + 0x40)
-#define FUNC_SPICLK_GPIO15                                          1
-#define FUNC_SPICLK_SPICLK                                          0
-
-#define PERIPHS_IO_MUX_SPID_U                (REG_IO_MUX_BASE + 0x44)
-#define FUNC_SPID_GPIO16                                            1
-#define FUNC_SPID_SPID                                              0
-
-#define PERIPHS_IO_MUX_SPIQ_U                (REG_IO_MUX_BASE + 0x48)
-#define FUNC_SPIQ_GPIO17                                            1
-#define FUNC_SPIQ_SPIQ                                              0
-
-#define PERIPHS_IO_MUX_GPIO18_U              (REG_IO_MUX_BASE + 0x4C)
-#define FUNC_GPIO18_GPIO18                                          1
-#define FUNC_GPIO18_GPIO18_0                                        0
-
-#define PERIPHS_IO_MUX_U0RXD_U               (REG_IO_MUX_BASE + 0x50)
-#define FUNC_U0RXD_GPIO19                                           1
-#define FUNC_U0RXD_U0RXD                                            0
-
-#define PERIPHS_IO_MUX_U0TXD_U               (REG_IO_MUX_BASE + 0x54)
-#define FUNC_U0TXD_GPIO20                                           1
-#define FUNC_U0TXD_U0TXD                                            0
-
-#define IO_MUX_PIN_CTRL_REG          (REG_IO_MUX_BASE + 0x0)
-/* IO_MUX_CLK_OUT3 : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. C
-LK_OUT_out3 can be found in peripheral output signals..*/
-#define IO_MUX_CLK_OUT3    0x0000000F
-#define IO_MUX_CLK_OUT3_M  ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S))
-#define IO_MUX_CLK_OUT3_V  0xF
-#define IO_MUX_CLK_OUT3_S  8
-/* IO_MUX_CLK_OUT2 : R/W ;bitpos:[7:4] ;default: 4'hf ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. C
-LK_OUT_out2 can be found in peripheral output signals..*/
-#define IO_MUX_CLK_OUT2    0x0000000F
-#define IO_MUX_CLK_OUT2_M  ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S))
-#define IO_MUX_CLK_OUT2_V  0xF
-#define IO_MUX_CLK_OUT2_S  4
-/* IO_MUX_CLK_OUT1 : R/W ;bitpos:[3:0] ;default: 4'hf ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. C
-LK_OUT_out1 can be found in peripheral output signals..*/
-#define IO_MUX_CLK_OUT1    0x0000000F
-#define IO_MUX_CLK_OUT1_M  ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S))
-#define IO_MUX_CLK_OUT1_V  0xF
-#define IO_MUX_CLK_OUT1_S  0
-/* IO_MUX_DATE_REG : R/W ;bitpos:[27:0] ;default: 28'h2106190 ; */
-/*description: Version control register.*/
-#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0xFC)
-#define IO_MUX_DATE_REG_M  ((IO_MUX_DATE_REG_V)<<(IO_MUX_DATE_REG_S))
-#define IO_MUX_DATE_REG_V  0xFFFFFFF
-#define IO_MUX_DATE_REG_S  0
-
-#endif
diff --git a/components/soc/esp32c2/include/soc/reg_base.h b/components/soc/esp32c2/include/soc/reg_base.h
deleted file mode 100644
index b410fbb3f3d..00000000000
--- a/components/soc/esp32c2/include/soc/reg_base.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#define DR_REG_SYSTEM_BASE                      0x600c0000
-#define DR_REG_SENSITIVE_BASE                   0x600c1000
-#define DR_REG_INTERRUPT_BASE                   0x600c2000
-#define DR_REG_EXTMEM_BASE                      0x600c4000 // CACHE_CONFIG
-#define DR_REG_MMU_TABLE                        0x600c5000
-#define DR_REG_SHA_BASE                         0x6003b000
-#define DR_REG_ECC_MULT_BASE                    0x6003e000
-#define DR_REG_GDMA_BASE                        0x6003f000
-#define DR_REG_ASSIST_DEBUG_BASE                0x600ce000
-#define DR_REG_DEDICATED_GPIO_BASE              0x600cf000
-#define DR_REG_WORLD_CNTL_BASE                  0x600d0000
-#define DR_REG_UART_BASE                        0x60000000
-#define DR_REG_SPI1_BASE                        0x60002000
-#define DR_REG_SPI0_BASE                        0x60003000
-#define DR_REG_GPIO_BASE                        0x60004000
-#define DR_REG_FE2_BASE                         0x60005000
-#define DR_REG_FE_BASE                          0x60006000
-#define DR_REG_RTCCNTL_BASE                     0x60008000
-#define DR_REG_IO_MUX_BASE                      0x60009000
-#define DR_REG_RTC_I2C_BASE                     0x6000e000
-#define DR_REG_UART1_BASE                       0x60010000
-#define DR_REG_I2C_EXT_BASE                     0x60013000
-#define DR_REG_LEDC_BASE                        0x60019000
-#define DR_REG_EFUSE_BASE                       0x60008800
-#define DR_REG_NRX_BASE                         0x6001CC00
-#define DR_REG_BB_BASE                          0x6001D000
-#define DR_REG_TIMERGROUP0_BASE                 0x6001F000
-#define DR_REG_SYSTIMER_BASE                    0x60023000
-#define DR_REG_SPI2_BASE                        0x60024000
-#define DR_REG_SYSCON_BASE                      0x60026000
-#define DR_REG_APB_SARADC_BASE                  0x60040000
-#define DR_REG_WDEVLE_BASE                      0x60045000
-#define DR_REG_ETM_BIT_BASE                     0x6004B000
-#define DR_REG_BLE_TIMER_BASE                   0x6004B800
-#define DR_REG_BLE_SEC_BASE                     0x6004C000
-#define DR_REG_COEX_BIT_BASE                    0x6004C400
-#define DR_REG_MODEM_CLKRST_BASE                0x6004d800
-#define DR_REG_I2C_MST_BASE                     0x6004E800
-#define DR_REG_XTS_AES_BASE                     0x600CC000
-
-/* For backward compatability with the older register name */
-#define DR_REG_AES_XTS_BASE                     DR_REG_XTS_AES_BASE
diff --git a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h b/components/soc/esp32c2/include/soc/rtc_cntl_reg.h
deleted file mode 100644
index e5ce9bff061..00000000000
--- a/components/soc/esp32c2/include/soc/rtc_cntl_reg.h
+++ /dev/null
@@ -1,1916 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_RTC_CNTL_REG_H_
-#define _SOC_RTC_CNTL_REG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
-#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
-
-#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
-/* RTC_CNTL_SW_SYS_RST :  ;bitpos:[31] ;default: 1'd0 ; */
-/*description: SW system reset.*/
-#define RTC_CNTL_SW_SYS_RST    (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_V  0x1
-#define RTC_CNTL_SW_SYS_RST_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_NORST :  ;bitpos:[30] ;default: 1'd0 ; */
-/*description: digital core force no reset in deep sleep.*/
-#define RTC_CNTL_DG_WRAP_FORCE_NORST    (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
-/* RTC_CNTL_DG_WRAP_FORCE_RST :  ;bitpos:[29] ;default: 1'd0 ; */
-/*description: digital wrap force reset in deep sleep.*/
-#define RTC_CNTL_DG_WRAP_FORCE_RST    (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
-/* RTC_CNTL_ANALOG_FORCE_NOISO :  ;bitpos:[28] ;default: 1'd1 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_ANALOG_FORCE_NOISO    (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
-#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
-/* RTC_CNTL_ANALOG_FORCE_ISO :  ;bitpos:[25] ;default: 1'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_ANALOG_FORCE_ISO    (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
-#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
-/* RTC_CNTL_XTL_EXT_CTR_SEL :  ;bitpos:[22:20] ;default: 3'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_XTL_EXT_CTR_SEL    0x00000007
-#define RTC_CNTL_XTL_EXT_CTR_SEL_M  ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S))
-#define RTC_CNTL_XTL_EXT_CTR_SEL_V  0x7
-#define RTC_CNTL_XTL_EXT_CTR_SEL_S  20
-/* RTC_CNTL_XTL_EN_WAIT :  ;bitpos:[17:14] ;default: 4'd2 ; */
-/*description: wait bias_sleep and current source wakeup.*/
-#define RTC_CNTL_XTL_EN_WAIT    0x0000000F
-#define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
-#define RTC_CNTL_XTL_EN_WAIT_V  0xF
-#define RTC_CNTL_XTL_EN_WAIT_S  14
-/* RTC_CNTL_XTL_FORCE_PU :  ;bitpos:[13] ;default: 1'd1 ; */
-/*description: crystall force power up.*/
-#define RTC_CNTL_XTL_FORCE_PU    (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_V  0x1
-#define RTC_CNTL_XTL_FORCE_PU_S  13
-/* RTC_CNTL_XTL_FORCE_PD :  ;bitpos:[12] ;default: 1'b0 ; */
-/*description: crystall force power down.*/
-#define RTC_CNTL_XTL_FORCE_PD    (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_V  0x1
-#define RTC_CNTL_XTL_FORCE_PD_S  12
-/* RTC_CNTL_BBPLL_FORCE_PU :  ;bitpos:[11] ;default: 1'd0 ; */
-/*description: BB_PLL force power up.*/
-#define RTC_CNTL_BBPLL_FORCE_PU    (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
-#define RTC_CNTL_BBPLL_FORCE_PU_S  11
-/* RTC_CNTL_BBPLL_FORCE_PD :  ;bitpos:[10] ;default: 1'b0 ; */
-/*description: BB_PLL force power down.*/
-#define RTC_CNTL_BBPLL_FORCE_PD    (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
-#define RTC_CNTL_BBPLL_FORCE_PD_S  10
-/* RTC_CNTL_BBPLL_I2C_FORCE_PU :  ;bitpos:[9] ;default: 1'd0 ; */
-/*description: BB_PLL_I2C force power up.*/
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU    (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
-/* RTC_CNTL_BBPLL_I2C_FORCE_PD :  ;bitpos:[8] ;default: 1'b0 ; */
-/*description: BB_PLL _I2C force power down.*/
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD    (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
-/* RTC_CNTL_BB_I2C_FORCE_PU :  ;bitpos:[7] ;default: 1'd0 ; */
-/*description: BB_I2C force power up.*/
-#define RTC_CNTL_BB_I2C_FORCE_PU    (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
-/* RTC_CNTL_BB_I2C_FORCE_PD :  ;bitpos:[6] ;default: 1'b0 ; */
-/*description: BB_I2C force power down.*/
-#define RTC_CNTL_BB_I2C_FORCE_PD    (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
-/* RTC_CNTL_SW_PROCPU_RST :  ;bitpos:[5] ;default: 1'b0 ; */
-/*description: PRO CPU SW reset.*/
-#define RTC_CNTL_SW_PROCPU_RST    (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_V  0x1
-#define RTC_CNTL_SW_PROCPU_RST_S  5
-/* RTC_CNTL_SW_STALL_PROCPU_C0 :  ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P
-RO CPU.*/
-#define RTC_CNTL_SW_STALL_PROCPU_C0    0x00000003
-#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
-#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
-#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
-
-#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x4)
-/* RTC_CNTL_SLP_VAL_LO :  ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SLP_VAL_LO    0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
-#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_S  0
-
-#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x8)
-/* RTC_CNTL_MAIN_TIMER_ALARM_EN :  ;bitpos:[16] ;default: 1'h0 ; */
-/*description: timer alarm enable bit.*/
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN    (BIT(16))
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
-/* RTC_CNTL_SLP_VAL_HI :  ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC sleep timer high 16 bits.*/
-#define RTC_CNTL_SLP_VAL_HI    0x0000FFFF
-#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
-#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
-#define RTC_CNTL_SLP_VAL_HI_S  0
-
-#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0xC)
-/* RTC_CNTL_TIME_UPDATE :  ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Set 1: to update register with RTC timer.*/
-#define RTC_CNTL_TIME_UPDATE    (BIT(31))
-#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
-#define RTC_CNTL_TIME_UPDATE_V  0x1
-#define RTC_CNTL_TIME_UPDATE_S  31
-/* RTC_CNTL_TIMER_SYS_RST :  ;bitpos:[29] ;default: 1'b0 ; */
-/*description: enable to record system reset time.*/
-#define RTC_CNTL_TIMER_SYS_RST    (BIT(29))
-#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
-#define RTC_CNTL_TIMER_SYS_RST_V  0x1
-#define RTC_CNTL_TIMER_SYS_RST_S  29
-/* RTC_CNTL_TIMER_XTL_OFF :  ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Enable to record 40M XTAL OFF time.*/
-#define RTC_CNTL_TIMER_XTL_OFF    (BIT(28))
-#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
-#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
-#define RTC_CNTL_TIMER_XTL_OFF_S  28
-/* RTC_CNTL_TIMER_SYS_STALL :  ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Enable to record system stall time.*/
-#define RTC_CNTL_TIMER_SYS_STALL    (BIT(27))
-#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
-#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
-#define RTC_CNTL_TIMER_SYS_STALL_S  27
-
-#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x10)
-/* RTC_CNTL_TIMER_VALUE0_LOW :  ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: RTC timer low 32 bits.*/
-#define RTC_CNTL_TIMER_VALUE0_LOW    0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
-#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
-
-#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x14)
-/* RTC_CNTL_TIMER_VALUE0_HIGH :  ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC timer high 16 bits.*/
-#define RTC_CNTL_TIMER_VALUE0_HIGH    0x0000FFFF
-#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
-#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
-#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
-
-#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
-/* RTC_CNTL_SLEEP_EN :  ;bitpos:[31] ;default: 1'd0 ; */
-/*description: sleep enable bit.*/
-#define RTC_CNTL_SLEEP_EN    (BIT(31))
-#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
-#define RTC_CNTL_SLEEP_EN_V  0x1
-#define RTC_CNTL_SLEEP_EN_S  31
-/* RTC_CNTL_SLP_REJECT :  ;bitpos:[30] ;default: 1'd0 ; */
-/*description: leep reject bit.*/
-#define RTC_CNTL_SLP_REJECT    (BIT(30))
-#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
-#define RTC_CNTL_SLP_REJECT_V  0x1
-#define RTC_CNTL_SLP_REJECT_S  30
-/* RTC_CNTL_SLP_WAKEUP :  ;bitpos:[29] ;default: 1'd0 ; */
-/*description: leep wakeup bit.*/
-#define RTC_CNTL_SLP_WAKEUP    (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_S  29
-/* RTC_CNTL_SDIO_ACTIVE_IND :  ;bitpos:[28] ;default: 1'd0 ; */
-/*description: SDIO active indication.*/
-#define RTC_CNTL_SDIO_ACTIVE_IND    (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
-#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
-/* RTC_CNTL_APB2RTC_BRIDGE_SEL :  ;bitpos:[22] ;default: 1'd0 ; */
-/*description: 1: APB to RTC using bridge.*/
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL    (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
-/* RTC_CNTL_SLP_REJECT_CAUSE_CLR :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: clear rtc sleep reject cause.*/
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
-/* RTC_CNTL_SW_CPU_INT :  ;bitpos:[0] ;default: 1'b0 ; */
-/*description: rtc software interrupt to main cpu.*/
-#define RTC_CNTL_SW_CPU_INT    (BIT(0))
-#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
-#define RTC_CNTL_SW_CPU_INT_V  0x1
-#define RTC_CNTL_SW_CPU_INT_S  0
-
-#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1C)
-/* RTC_CNTL_PLL_BUF_WAIT :  ;bitpos:[31:24] ;default: 8'd40 ; */
-/*description: PLL wait cycles in slow_clk_rtc.*/
-#define RTC_CNTL_PLL_BUF_WAIT    0x000000FF
-#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
-#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
-#define RTC_CNTL_PLL_BUF_WAIT_S  24
-/* RTC_CNTL_XTL_BUF_WAIT :  ;bitpos:[23:14] ;default: 10'd80 ; */
-/*description: XTAL wait cycles in slow_clk_rtc.*/
-#define RTC_CNTL_XTL_BUF_WAIT    0x000003FF
-#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
-#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
-#define RTC_CNTL_XTL_BUF_WAIT_S  14
-/* RTC_CNTL_CK8M_WAIT :  ;bitpos:[13:6] ;default: 8'h10 ; */
-/*description: CK8M wait cycles in slow_clk_rtc.*/
-#define RTC_CNTL_CK8M_WAIT    0x000000FF
-#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
-#define RTC_CNTL_CK8M_WAIT_V  0xFF
-#define RTC_CNTL_CK8M_WAIT_S  6
-/* RTC_CNTL_CPU_STALL_WAIT :  ;bitpos:[5:1] ;default: 5'd1 ; */
-/*description: CPU stall wait cycles in fast_clk_rtc.*/
-#define RTC_CNTL_CPU_STALL_WAIT    0x0000001F
-#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
-#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
-#define RTC_CNTL_CPU_STALL_WAIT_S  1
-/* RTC_CNTL_CPU_STALL_EN :  ;bitpos:[0] ;default: 1'd1 ; */
-/*description: CPU stall enable bit.*/
-#define RTC_CNTL_CPU_STALL_EN    (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_V  0x1
-#define RTC_CNTL_CPU_STALL_EN_S  0
-
-#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
-/* RTC_CNTL_MIN_TIME_CK8M_OFF :  ;bitpos:[31:24] ;default: 8'h1 ; */
-/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/
-#define RTC_CNTL_MIN_TIME_CK8M_OFF    0x000000FF
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
-
-#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x24)
-/* RTC_CNTL_DG_WRAP_POWERUP_TIMER :  ;bitpos:[31:25] ;default: 7'h8 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER    0x0000007F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
-/* RTC_CNTL_DG_WRAP_WAIT_TIMER :  ;bitpos:[24:16] ;default: 9'h20 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER    0x000001FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
-
-#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x28)
-/* RTC_CNTL_MIN_SLP_VAL :  ;bitpos:[15:8] ;default: 8'h80 ; */
-/*description: minimal sleep cycles in slow_clk_rtc.*/
-#define RTC_CNTL_MIN_SLP_VAL    0x000000FF
-#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
-#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
-#define RTC_CNTL_MIN_SLP_VAL_S  8
-
-#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x2C)
-/* RTC_CNTL_PLL_I2C_PU :  ;bitpos:[31] ;default: 1'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_PLL_I2C_PU    (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_V  0x1
-#define RTC_CNTL_PLL_I2C_PU_S  31
-/* RTC_CNTL_CKGEN_I2C_PU :  ;bitpos:[30] ;default: 1'd0 ; */
-/*description: 1: CKGEN_I2C power up.*/
-#define RTC_CNTL_CKGEN_I2C_PU    (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
-#define RTC_CNTL_CKGEN_I2C_PU_S  30
-/* RTC_CNTL_RFRX_PBUS_PU :  ;bitpos:[28] ;default: 1'd0 ; */
-/*description: 1: RFRX_PBUS power up.*/
-#define RTC_CNTL_RFRX_PBUS_PU    (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
-#define RTC_CNTL_RFRX_PBUS_PU_S  28
-/* RTC_CNTL_TXRF_I2C_PU :  ;bitpos:[27] ;default: 1'd0 ; */
-/*description: 1: TXRF_I2C power up.*/
-#define RTC_CNTL_TXRF_I2C_PU    (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_V  0x1
-#define RTC_CNTL_TXRF_I2C_PU_S  27
-/* RTC_CNTL_BBPLL_CAL_SLP_START :  ;bitpos:[25] ;default: 1'b0 ; */
-/*description: start BBPLL calibration during sleep.*/
-#define RTC_CNTL_BBPLL_CAL_SLP_START    (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
-#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
-/* RTC_CNTL_SAR_I2C_PU :  ;bitpos:[22] ;default: 1'b1 ; */
-/*description: PLLA force power up.*/
-#define RTC_CNTL_SAR_I2C_PU    (BIT(22))
-#define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
-#define RTC_CNTL_SAR_I2C_PU_V  0x1
-#define RTC_CNTL_SAR_I2C_PU_S  22
-/* RTC_CNTL_I2C_RESET_POR_FORCE_PU :  ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU    (BIT(19))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
-/* RTC_CNTL_I2C_RESET_POR_FORCE_PD :  ;bitpos:[18] ;default: 1'b1 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD    (BIT(18))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
-
-#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x30)
-/* RTC_CNTL_DRESET_MASK_PROCPU :  ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DRESET_MASK_PROCPU    (BIT(20))
-#define RTC_CNTL_DRESET_MASK_PROCPU_M  (BIT(20))
-#define RTC_CNTL_DRESET_MASK_PROCPU_V  0x1
-#define RTC_CNTL_DRESET_MASK_PROCPU_S  20
-/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU :  ;bitpos:[19] ;default: 1'b0 ; */
-/*description: PROCPU OcdHaltOnReset.*/
-#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU    (BIT(19))
-#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M  (BIT(19))
-#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V  0x1
-#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S  19
-/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU :  ;bitpos:[13] ;default: 1'b1 ; */
-/*description: PRO CPU state vector sel.*/
-#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU    (BIT(13))
-#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M  (BIT(13))
-#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V  0x1
-#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S  13
-/* RTC_CNTL_RESET_CAUSE_PROCPU :  ;bitpos:[5:0] ;default: 0 ; */
-/*description: reset cause of PRO CPU.*/
-#define RTC_CNTL_RESET_CAUSE_PROCPU    0x0000003F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
-#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
-
-#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x34)
-/* RTC_CNTL_WAKEUP_ENA :  ;bitpos:[31:15] ;default: 17'b1100 ; */
-/*description: wakeup enable bitmap.*/
-#define RTC_CNTL_WAKEUP_ENA    0x0001FFFF
-#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
-#define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
-#define RTC_CNTL_WAKEUP_ENA_S  15
-
-#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x38)
-/* RTC_CNTL_BBPLL_CAL_INT_ENA : BIT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BBPLL_CAL_INT_ENA    (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_S  20
-/* RTC_CNTL_SWD_INT_ENA : BIT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define RTC_CNTL_SWD_INT_ENA    (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_ENA : BIT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt.*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA : BIT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt.*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
-/* RTC_CNTL_WDT_INT_ENA : BIT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define RTC_CNTL_WDT_INT_ENA    (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_S  3
-/* RTC_CNTL_SLP_REJECT_INT_ENA : BIT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt.*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA : BIT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
-
-#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x3C)
-/* RTC_CNTL_BBPLL_CAL_INT_RAW :  ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BBPLL_CAL_INT_RAW    (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_RAW_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_RAW_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_RAW_S  20
-/* RTC_CNTL_SWD_INT_RAW :  ;bitpos:[15] ;default: 1'b0 ; */
-/*description: super watch dog interrupt raw.*/
-#define RTC_CNTL_SWD_INT_RAW    (BIT(15))
-#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_RAW_V  0x1
-#define RTC_CNTL_SWD_INT_RAW_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_RAW :  ;bitpos:[10] ;default: 1'b0 ; */
-/*description: RTC main timer interrupt raw.*/
-#define RTC_CNTL_MAIN_TIMER_INT_RAW    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
-/* RTC_CNTL_BROWN_OUT_INT_RAW :  ;bitpos:[9] ;default: 1'b0 ; */
-/*description: brown out interrupt raw.*/
-#define RTC_CNTL_BROWN_OUT_INT_RAW    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
-/* RTC_CNTL_WDT_INT_RAW :  ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt raw.*/
-#define RTC_CNTL_WDT_INT_RAW    (BIT(3))
-#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_RAW_V  0x1
-#define RTC_CNTL_WDT_INT_RAW_S  3
-/* RTC_CNTL_SLP_REJECT_INT_RAW :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: sleep reject interrupt raw.*/
-#define RTC_CNTL_SLP_REJECT_INT_RAW    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_RAW :  ;bitpos:[0] ;default: 1'b0 ; */
-/*description: sleep wakeup interrupt raw.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
-
-#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x40)
-/* RTC_CNTL_BBPLL_CAL_INT_ST :  ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BBPLL_CAL_INT_ST    (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ST_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ST_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_ST_S  20
-/* RTC_CNTL_SWD_INT_ST :  ;bitpos:[15] ;default: 1'b0 ; */
-/*description: super watch dog interrupt state.*/
-#define RTC_CNTL_SWD_INT_ST    (BIT(15))
-#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ST_V  0x1
-#define RTC_CNTL_SWD_INT_ST_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_ST :  ;bitpos:[10] ;default: 1'b0 ; */
-/*description: RTC main timer interrupt state.*/
-#define RTC_CNTL_MAIN_TIMER_INT_ST    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ST :  ;bitpos:[9] ;default: 1'b0 ; */
-/*description: brown out interrupt state.*/
-#define RTC_CNTL_BROWN_OUT_INT_ST    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
-/* RTC_CNTL_WDT_INT_ST :  ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt state.*/
-#define RTC_CNTL_WDT_INT_ST    (BIT(3))
-#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ST_V  0x1
-#define RTC_CNTL_WDT_INT_ST_S  3
-/* RTC_CNTL_SLP_REJECT_INT_ST :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: sleep reject interrupt state.*/
-#define RTC_CNTL_SLP_REJECT_INT_ST    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ST :  ;bitpos:[0] ;default: 1'b0 ; */
-/*description: sleep wakeup interrupt state.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ST    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
-
-#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x44)
-/* RTC_CNTL_BBPLL_CAL_INT_CLR :  ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BBPLL_CAL_INT_CLR    (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_CLR_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_CLR_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_CLR_S  20
-/* RTC_CNTL_SWD_INT_CLR :  ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Clear super watch dog interrupt state.*/
-#define RTC_CNTL_SWD_INT_CLR    (BIT(15))
-#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_CLR_V  0x1
-#define RTC_CNTL_SWD_INT_CLR_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_CLR :  ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Clear RTC main timer interrupt state.*/
-#define RTC_CNTL_MAIN_TIMER_INT_CLR    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
-/* RTC_CNTL_BROWN_OUT_INT_CLR :  ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Clear brown out interrupt state.*/
-#define RTC_CNTL_BROWN_OUT_INT_CLR    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
-/* RTC_CNTL_WDT_INT_CLR :  ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Clear RTC WDT interrupt state.*/
-#define RTC_CNTL_WDT_INT_CLR    (BIT(3))
-#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_CLR_V  0x1
-#define RTC_CNTL_WDT_INT_CLR_S  3
-/* RTC_CNTL_SLP_REJECT_INT_CLR :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Clear sleep reject interrupt state.*/
-#define RTC_CNTL_SLP_REJECT_INT_CLR    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_CLR :  ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Clear sleep wakeup interrupt state.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
-
-#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x48)
-/* RTC_CNTL_SCRATCH0 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SCRATCH0    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
-#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH0_S  0
-
-#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x4C)
-/* RTC_CNTL_SCRATCH1 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SCRATCH1    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
-#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH1_S  0
-
-#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x50)
-/* RTC_CNTL_SCRATCH2 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SCRATCH2    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
-#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH2_S  0
-
-#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x54)
-/* RTC_CNTL_SCRATCH3 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SCRATCH3    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
-#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH3_S  0
-
-#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x58)
-/* RTC_CNTL_XTL_EXT_CTR_EN :  ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_XTL_EXT_CTR_EN    (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
-#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
-/* RTC_CNTL_XTL_EXT_CTR_LV :  ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: power down XTAL at high level.*/
-#define RTC_CNTL_XTL_EXT_CTR_LV    (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
-#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
-
-#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x5C)
-/* RTC_CNTL_GPIO_WAKEUP_FILTER :  ;bitpos:[31] ;default: 1'b0 ; */
-/*description: enable filter for gpio wakeup event.*/
-#define RTC_CNTL_GPIO_WAKEUP_FILTER    (BIT(31))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(31))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  31
-
-#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
-/* RTC_CNTL_DEEP_SLP_REJECT_EN :  ;bitpos:[31] ;default: 1'b0 ; */
-/*description: enable reject for deep sleep.*/
-#define RTC_CNTL_DEEP_SLP_REJECT_EN    (BIT(31))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
-/* RTC_CNTL_LIGHT_SLP_REJECT_EN :  ;bitpos:[30] ;default: 1'b0 ; */
-/*description: enable reject for light sleep.*/
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN    (BIT(30))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
-/* RTC_CNTL_SLEEP_REJECT_ENA :  ;bitpos:[29:12] ;default: 17'd0 ; */
-/*description: sleep reject enable.*/
-#define RTC_CNTL_SLEEP_REJECT_ENA    0x0003FFFF
-#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
-#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
-#define RTC_CNTL_SLEEP_REJECT_ENA_S  12
-
-#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x64)
-/* RTC_CNTL_CPUPERIOD_SEL :  ;bitpos:[31:30] ;default: 2'b00 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_CPUPERIOD_SEL    0x00000003
-#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
-#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
-#define RTC_CNTL_CPUPERIOD_SEL_S  30
-/* RTC_CNTL_CPUSEL_CONF :  ;bitpos:[29] ;default: 1'b0 ; */
-/*description: CPU sel option.*/
-#define RTC_CNTL_CPUSEL_CONF    (BIT(29))
-#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
-#define RTC_CNTL_CPUSEL_CONF_V  0x1
-#define RTC_CNTL_CPUSEL_CONF_S  29
-
-#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x68)
-/* RTC_CNTL_ANA_CLK_RTC_SEL :  ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_ANA_CLK_RTC_SEL    0x00000003
-#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
-#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
-#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
-/* RTC_CNTL_FAST_CLK_RTC_SEL :  ;bitpos:[29] ;default: 1'b0 ; */
-/*description: fast_clk_rtc sel. 0: XTAL div 2.*/
-#define RTC_CNTL_FAST_CLK_RTC_SEL    (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
-#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
-/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING :  ;bitpos:[28] ;default: 1'b1 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING    (BIT(28))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
-/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING :  ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING    (BIT(27))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
-/* RTC_CNTL_CK8M_FORCE_PU :  ;bitpos:[26] ;default: 1'd0 ; */
-/*description: CK8M force power up.*/
-#define RTC_CNTL_CK8M_FORCE_PU    (BIT(26))
-#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
-#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
-#define RTC_CNTL_CK8M_FORCE_PU_S  26
-/* RTC_CNTL_CK8M_FORCE_PD :  ;bitpos:[25] ;default: 1'd0 ; */
-/*description: CK8M force power down.*/
-#define RTC_CNTL_CK8M_FORCE_PD    (BIT(25))
-#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
-#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
-#define RTC_CNTL_CK8M_FORCE_PD_S  25
-/* RTC_CNTL_CK8M_DFREQ :  ;bitpos:[24:17] ;default: 8'd172 ; */
-/*description: CK8M_DFREQ.*/
-#define RTC_CNTL_CK8M_DFREQ    0x000000FF
-#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
-#define RTC_CNTL_CK8M_DFREQ_V  0xFF
-#define RTC_CNTL_CK8M_DFREQ_S  17
-/* RTC_CNTL_CK8M_FORCE_NOGATING :  ;bitpos:[16] ;default: 1'd0 ; */
-/*description: CK8M force no gating during sleep.*/
-#define RTC_CNTL_CK8M_FORCE_NOGATING    (BIT(16))
-#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
-#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
-/* RTC_CNTL_XTAL_FORCE_NOGATING :  ;bitpos:[15] ;default: 1'd0 ; */
-/*description: XTAL force no gating during sleep.*/
-#define RTC_CNTL_XTAL_FORCE_NOGATING    (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
-/* RTC_CNTL_CK8M_DIV_SEL :  ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: divider = reg_ck8m_div_sel + 1.*/
-#define RTC_CNTL_CK8M_DIV_SEL    0x00000007
-#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
-#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
-#define RTC_CNTL_CK8M_DIV_SEL_S  12
-/* RTC_CNTL_DIG_CLK8M_EN :  ;bitpos:[10] ;default: 1'd0 ; */
-/*description: enable CK8M for digital core (no relationship with RTC core).*/
-#define RTC_CNTL_DIG_CLK8M_EN    (BIT(10))
-#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
-#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
-#define RTC_CNTL_DIG_CLK8M_EN_S  10
-/* RTC_CNTL_DIG_CLK8M_D256_EN :  ;bitpos:[9] ;default: 1'd1 ; */
-/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/
-#define RTC_CNTL_DIG_CLK8M_D256_EN    (BIT(9))
-#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
-#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
-#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
-/* RTC_CNTL_DIG_XTAL32K_EN :  ;bitpos:[8] ;default: 1'd0 ; */
-/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/
-#define RTC_CNTL_DIG_XTAL32K_EN    (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
-#define RTC_CNTL_DIG_XTAL32K_EN_S  8
-/* RTC_CNTL_ENB_CK8M_DIV :  ;bitpos:[7] ;default: 1'd0 ; */
-/*description: 1: CK8M_D256_OUT is actually CK8M.*/
-#define RTC_CNTL_ENB_CK8M_DIV    (BIT(7))
-#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
-#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
-#define RTC_CNTL_ENB_CK8M_DIV_S  7
-/* RTC_CNTL_ENB_CK8M :  ;bitpos:[6] ;default: 1'd0 ; */
-/*description: disable CK8M and CK8M_D256_OUT.*/
-#define RTC_CNTL_ENB_CK8M    (BIT(6))
-#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
-#define RTC_CNTL_ENB_CK8M_V  0x1
-#define RTC_CNTL_ENB_CK8M_S  6
-/* RTC_CNTL_CK8M_DIV :  ;bitpos:[5:4] ;default: 2'b01 ; */
-/*description: CK8M_D256_OUT divider. 00: div128.*/
-#define RTC_CNTL_CK8M_DIV    0x00000003
-#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
-#define RTC_CNTL_CK8M_DIV_V  0x3
-#define RTC_CNTL_CK8M_DIV_S  4
-/* RTC_CNTL_CK8M_DIV_SEL_VLD :  ;bitpos:[3] ;default: 1'b1 ; */
-/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/
-#define RTC_CNTL_CK8M_DIV_SEL_VLD    (BIT(3))
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
-/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING :  ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING    (BIT(2))
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
-/* RTC_CNTL_EFUSE_CLK_FORCE_GATING :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING    (BIT(1))
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
-
-#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x6C)
-/* RTC_CNTL_SLOW_CLK_NEXT_EDGE :  ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE    (BIT(31))
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
-/* RTC_CNTL_ANA_CLK_DIV :  ;bitpos:[30:23] ;default: 8'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_ANA_CLK_DIV    0x000000FF
-#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
-#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
-#define RTC_CNTL_ANA_CLK_DIV_S  23
-/* RTC_CNTL_ANA_CLK_DIV_VLD :  ;bitpos:[22] ;default: 1'b1 ; */
-/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/
-#define RTC_CNTL_ANA_CLK_DIV_VLD    (BIT(22))
-#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
-#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
-#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
-
-#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
-/* RTC_CNTL_DBG_ATTEN_ACTIVE :  ;bitpos:[29:26] ;default: 4'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DBG_ATTEN_ACTIVE    0x0000000F
-#define RTC_CNTL_DBG_ATTEN_ACTIVE_M  ((RTC_CNTL_DBG_ATTEN_ACTIVE_V)<<(RTC_CNTL_DBG_ATTEN_ACTIVE_S))
-#define RTC_CNTL_DBG_ATTEN_ACTIVE_V  0xF
-#define RTC_CNTL_DBG_ATTEN_ACTIVE_S  26
-/* RTC_CNTL_DBG_ATTEN_MONITOR :  ;bitpos:[25:22] ;default: 4'd0 ; */
-/*description: DBG_ATTEN when rtc in active state.*/
-#define RTC_CNTL_DBG_ATTEN_MONITOR    0x0000000F
-#define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
-#define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
-#define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
-/* RTC_CNTL_DBG_ATTEN_DEEP_SLP :  ;bitpos:[21:18] ;default: 4'd0 ; */
-/*description: DBG_ATTEN when rtc in sleep state.*/
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP    0x0000000F
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
-/* RTC_CNTL_BIAS_SLEEP_MONITOR :  ;bitpos:[17] ;default: 1'b0 ; */
-/*description: bias_sleep when rtc in monitor state.*/
-#define RTC_CNTL_BIAS_SLEEP_MONITOR    (BIT(17))
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
-/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP :  ;bitpos:[16] ;default: 1'b1 ; */
-/*description: bias_sleep when rtc in sleep_state.*/
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP    (BIT(16))
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
-/* RTC_CNTL_PD_CUR_MONITOR :  ;bitpos:[15] ;default: 1'b0 ; */
-/*description: xpd cur when rtc in monitor state.*/
-#define RTC_CNTL_PD_CUR_MONITOR    (BIT(15))
-#define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
-#define RTC_CNTL_PD_CUR_MONITOR_V  0x1
-#define RTC_CNTL_PD_CUR_MONITOR_S  15
-/* RTC_CNTL_PD_CUR_DEEP_SLP :  ;bitpos:[14] ;default: 1'b0 ; */
-/*description: xpd cur when rtc in sleep_state.*/
-#define RTC_CNTL_PD_CUR_DEEP_SLP    (BIT(14))
-#define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
-#define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
-#define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
-/* RTC_CNTL_BIAS_BUF_MONITOR :  ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BIAS_BUF_MONITOR    (BIT(13))
-#define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
-#define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
-#define RTC_CNTL_BIAS_BUF_MONITOR_S  13
-/* RTC_CNTL_BIAS_BUF_DEEP_SLP :  ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP    (BIT(12))
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
-/* RTC_CNTL_BIAS_BUF_WAKE :  ;bitpos:[11] ;default: 1'b1 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BIAS_BUF_WAKE    (BIT(11))
-#define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
-#define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
-#define RTC_CNTL_BIAS_BUF_WAKE_S  11
-/* RTC_CNTL_BIAS_BUF_IDLE :  ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BIAS_BUF_IDLE    (BIT(10))
-#define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
-#define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
-#define RTC_CNTL_BIAS_BUF_IDLE_S  10
-/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN :  ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN    (BIT(8))
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M  (BIT(8))
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V  0x1
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S  8
-/* RTC_CNTL_DG_VDD_DRV_B_SLP :  ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DG_VDD_DRV_B_SLP    0x000000FF
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_S  0
-
-#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x74)
-/* RTC_CNTL_REGULATOR_FORCE_PU :  ;bitpos:[31] ;default: 1'd1 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_REGULATOR_FORCE_PU    (BIT(31))
-#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
-#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
-#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
-/* RTC_CNTL_REGULATOR_FORCE_PD :  ;bitpos:[30] ;default: 1'd0 ; */
-/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0
-.8v or lower ).*/
-#define RTC_CNTL_REGULATOR_FORCE_PD    (BIT(30))
-#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
-#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
-#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
-/* RTC_CNTL_SCK_DCAP :  ;bitpos:[21:14] ;default: 8'd0 ; */
-/*description: SCK_DCAP.*/
-#define RTC_CNTL_SCK_DCAP    0x000000FF
-#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
-#define RTC_CNTL_SCK_DCAP_V  0xFF
-#define RTC_CNTL_SCK_DCAP_S  14
-/* RTC_CNTL_DIG_REG_CAL_EN :  ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DIG_REG_CAL_EN    (BIT(7))
-#define RTC_CNTL_DIG_REG_CAL_EN_M  (BIT(7))
-#define RTC_CNTL_DIG_REG_CAL_EN_V  0x1
-#define RTC_CNTL_DIG_REG_CAL_EN_S  7
-
-#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x78)
-/* RTC_CNTL_PAD_FORCE_HOLD :  ;bitpos:[21] ;default: 1'd0 ; */
-/*description: rtc pad force hold.*/
-#define RTC_CNTL_PAD_FORCE_HOLD    (BIT(21))
-#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
-#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
-#define RTC_CNTL_PAD_FORCE_HOLD_S  21
-
-#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x7C)
-/* RTC_CNTL_DG_WRAP_PD_EN :  ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DG_WRAP_PD_EN    (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
-#define RTC_CNTL_DG_WRAP_PD_EN_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_PU :  ;bitpos:[20] ;default: 1'd1 ; */
-/*description: digital core force power up.*/
-#define RTC_CNTL_DG_WRAP_FORCE_PU    (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
-/* RTC_CNTL_DG_WRAP_FORCE_PD :  ;bitpos:[19] ;default: 1'b0 ; */
-/*description: digital core force power down.*/
-#define RTC_CNTL_DG_WRAP_FORCE_PD    (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
-/* RTC_CNTL_LSLP_MEM_FORCE_PU :  ;bitpos:[5] ;default: 1'b1 ; */
-/*description: memories in digital core force no PD in sleep.*/
-#define RTC_CNTL_LSLP_MEM_FORCE_PU    (BIT(5))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(5))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  5
-/* RTC_CNTL_LSLP_MEM_FORCE_PD :  ;bitpos:[4] ;default: 1'b0 ; */
-/*description: memories in digital core force PD in sleep.*/
-#define RTC_CNTL_LSLP_MEM_FORCE_PD    (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  4
-/* RTC_CNTL_VDD_SPI_PD_EN :  ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_VDD_SPI_PD_EN    (BIT(3))
-#define RTC_CNTL_VDD_SPI_PD_EN_M  (BIT(3))
-#define RTC_CNTL_VDD_SPI_PD_EN_V  0x1
-#define RTC_CNTL_VDD_SPI_PD_EN_S  3
-/* RTC_CNTL_VDD_SPI_PWR_FORCE :  ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_VDD_SPI_PWR_FORCE    (BIT(2))
-#define RTC_CNTL_VDD_SPI_PWR_FORCE_M  (BIT(2))
-#define RTC_CNTL_VDD_SPI_PWR_FORCE_V  0x1
-#define RTC_CNTL_VDD_SPI_PWR_FORCE_S  2
-/* RTC_CNTL_VDD_SPI_PWR_DRV :  ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_VDD_SPI_PWR_DRV    0x00000003
-#define RTC_CNTL_VDD_SPI_PWR_DRV_M  ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S))
-#define RTC_CNTL_VDD_SPI_PWR_DRV_V  0x3
-#define RTC_CNTL_VDD_SPI_PWR_DRV_S  0
-
-#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x80)
-/* RTC_CNTL_DG_WRAP_FORCE_NOISO :  ;bitpos:[31] ;default: 1'd1 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO    (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_ISO :  ;bitpos:[30] ;default: 1'd0 ; */
-/*description: digital core force ISO.*/
-#define RTC_CNTL_DG_WRAP_FORCE_ISO    (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
-/* RTC_CNTL_DG_PAD_FORCE_HOLD :  ;bitpos:[15] ;default: 1'd0 ; */
-/*description: digital pad force hold.*/
-#define RTC_CNTL_DG_PAD_FORCE_HOLD    (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
-/* RTC_CNTL_DG_PAD_FORCE_UNHOLD :  ;bitpos:[14] ;default: 1'd1 ; */
-/*description: digital pad force un-hold.*/
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD    (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
-/* RTC_CNTL_DG_PAD_FORCE_ISO :  ;bitpos:[13] ;default: 1'd0 ; */
-/*description: digital pad force ISO.*/
-#define RTC_CNTL_DG_PAD_FORCE_ISO    (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
-/* RTC_CNTL_DG_PAD_FORCE_NOISO :  ;bitpos:[12] ;default: 1'd1 ; */
-/*description: digital pad force no ISO.*/
-#define RTC_CNTL_DG_PAD_FORCE_NOISO    (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
-/* RTC_CNTL_DG_PAD_AUTOHOLD_EN :  ;bitpos:[11] ;default: 1'd0 ; */
-/*description: digital pad enable auto-hold.*/
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN    (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
-/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD :  ;bitpos:[10] ;default: 1'd0 ; */
-/*description: wtite only register to clear digital pad auto-hold.*/
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD    (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
-/* RTC_CNTL_DG_PAD_AUTOHOLD :  ;bitpos:[9] ;default: 1'd0 ; */
-/*description: read only register to indicate digital pad auto-hold status.*/
-#define RTC_CNTL_DG_PAD_AUTOHOLD    (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
-#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
-/* RTC_CNTL_DIG_ISO_FORCE_ON :  ;bitpos:[8] ;default: 1'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DIG_ISO_FORCE_ON    (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
-#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
-/* RTC_CNTL_DIG_ISO_FORCE_OFF :  ;bitpos:[7] ;default: 1'd1 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DIG_ISO_FORCE_OFF    (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
-
-#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x84)
-/* RTC_CNTL_WDT_EN :  ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_WDT_EN    (BIT(31))
-#define RTC_CNTL_WDT_EN_M  (BIT(31))
-#define RTC_CNTL_WDT_EN_V  0x1
-#define RTC_CNTL_WDT_EN_S  31
-/* RTC_CNTL_WDT_STG0 :  ;bitpos:[30:28] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en.*/
-#define RTC_CNTL_WDT_STG0    0x00000007
-#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
-#define RTC_CNTL_WDT_STG0_V  0x7
-#define RTC_CNTL_WDT_STG0_S  28
-/* RTC_CNTL_WDT_STG1 :  ;bitpos:[27:25] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en.*/
-#define RTC_CNTL_WDT_STG1    0x00000007
-#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
-#define RTC_CNTL_WDT_STG1_V  0x7
-#define RTC_CNTL_WDT_STG1_S  25
-/* RTC_CNTL_WDT_STG2 :  ;bitpos:[24:22] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en.*/
-#define RTC_CNTL_WDT_STG2    0x00000007
-#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
-#define RTC_CNTL_WDT_STG2_V  0x7
-#define RTC_CNTL_WDT_STG2_S  22
-/* RTC_CNTL_WDT_STG3 :  ;bitpos:[21:19] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en.*/
-#define RTC_CNTL_WDT_STG3    0x00000007
-#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
-#define RTC_CNTL_WDT_STG3_V  0x7
-#define RTC_CNTL_WDT_STG3_S  19
-
-/* RTC_CNTL_WDT_STGX : */
-/*description: stage action selection values */
-#define RTC_WDT_STG_SEL_OFF             0
-#define RTC_WDT_STG_SEL_INT             1
-#define RTC_WDT_STG_SEL_RESET_CPU       2
-#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
-#define RTC_WDT_STG_SEL_RESET_RTC       4
-
-/* RTC_CNTL_WDT_CPU_RESET_LENGTH :  ;bitpos:[18:16] ;default: 3'h1 ; */
-/*description: CPU reset counter length.*/
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH    0x00000007
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
-/* RTC_CNTL_WDT_SYS_RESET_LENGTH :  ;bitpos:[15:13] ;default: 3'h1 ; */
-/*description: system reset counter length.*/
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH    0x00000007
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
-/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN :  ;bitpos:[12] ;default: 1'h1 ; */
-/*description: enable WDT in flash boot.*/
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN    (BIT(12))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
-/* RTC_CNTL_WDT_PROCPU_RESET_EN :  ;bitpos:[11] ;default: 1'd0 ; */
-/*description: enable WDT reset PRO CPU.*/
-#define RTC_CNTL_WDT_PROCPU_RESET_EN    (BIT(11))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
-/* RTC_CNTL_WDT_PAUSE_IN_SLP :  ;bitpos:[9] ;default: 1'd1 ; */
-/*description: pause WDT in sleep.*/
-#define RTC_CNTL_WDT_PAUSE_IN_SLP    (BIT(9))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
-/* RTC_CNTL_WDT_CHIP_RESET_EN :  ;bitpos:[8] ;default: 1'b0 ; */
-/*description: wdt reset whole chip enable.*/
-#define RTC_CNTL_WDT_CHIP_RESET_EN    (BIT(8))
-#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
-#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
-/* RTC_CNTL_WDT_CHIP_RESET_WIDTH :  ;bitpos:[7:0] ;default: 8'd20 ; */
-/*description: chip reset siginal pulse width.*/
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH    0x000000FF
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
-
-#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x88)
-/* RTC_CNTL_WDT_STG0_HOLD :  ;bitpos:[31:0] ;default: 32'd200000 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_WDT_STG0_HOLD    0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
-#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x8C)
-/* RTC_CNTL_WDT_STG1_HOLD :  ;bitpos:[31:0] ;default: 32'd80000 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_WDT_STG1_HOLD    0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
-#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x90)
-/* RTC_CNTL_WDT_STG2_HOLD :  ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_WDT_STG2_HOLD    0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
-#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x94)
-/* RTC_CNTL_WDT_STG3_HOLD :  ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_WDT_STG3_HOLD    0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
-#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_S  0
-
-#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0x98)
-/* RTC_CNTL_WDT_FEED :  ;bitpos:[31] ;default: 1'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_WDT_FEED    (BIT(31))
-#define RTC_CNTL_WDT_FEED_M  (BIT(31))
-#define RTC_CNTL_WDT_FEED_V  0x1
-#define RTC_CNTL_WDT_FEED_S  31
-
-#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x9C)
-/* RTC_CNTL_WDT_WKEY :  ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_WDT_WKEY    0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
-#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_S  0
-
-#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xA0)
-/* RTC_CNTL_SWD_AUTO_FEED_EN :  ;bitpos:[31] ;default: 1'b0 ; */
-/*description: automatically feed swd when int comes.*/
-#define RTC_CNTL_SWD_AUTO_FEED_EN    (BIT(31))
-#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
-#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
-#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
-/* RTC_CNTL_SWD_DISABLE :  ;bitpos:[30] ;default: 1'b0 ; */
-/*description: disabel SWD.*/
-#define RTC_CNTL_SWD_DISABLE    (BIT(30))
-#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
-#define RTC_CNTL_SWD_DISABLE_V  0x1
-#define RTC_CNTL_SWD_DISABLE_S  30
-/* RTC_CNTL_SWD_FEED :  ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Sw feed swd.*/
-#define RTC_CNTL_SWD_FEED    (BIT(29))
-#define RTC_CNTL_SWD_FEED_M  (BIT(29))
-#define RTC_CNTL_SWD_FEED_V  0x1
-#define RTC_CNTL_SWD_FEED_S  29
-/* RTC_CNTL_SWD_RST_FLAG_CLR :  ;bitpos:[28] ;default: 1'b0 ; */
-/*description: reset swd reset flag.*/
-#define RTC_CNTL_SWD_RST_FLAG_CLR    (BIT(28))
-#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
-#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
-#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
-/* RTC_CNTL_SWD_SIGNAL_WIDTH :  ;bitpos:[27:18] ;default: 10'd300 ; */
-/*description: adjust signal width send to swd.*/
-#define RTC_CNTL_SWD_SIGNAL_WIDTH    0x000003FF
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
-/* RTC_CNTL_SWD_BYPASS_RST :  ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SWD_BYPASS_RST    (BIT(17))
-#define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
-#define RTC_CNTL_SWD_BYPASS_RST_V  0x1
-#define RTC_CNTL_SWD_BYPASS_RST_S  17
-/* RTC_CNTL_SWD_FEED_INT :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: swd interrupt for feeding.*/
-#define RTC_CNTL_SWD_FEED_INT    (BIT(1))
-#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
-#define RTC_CNTL_SWD_FEED_INT_V  0x1
-#define RTC_CNTL_SWD_FEED_INT_S  1
-/* RTC_CNTL_SWD_RESET_FLAG :  ;bitpos:[0] ;default: 1'b0 ; */
-/*description: swd reset flag.*/
-#define RTC_CNTL_SWD_RESET_FLAG    (BIT(0))
-#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
-#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
-#define RTC_CNTL_SWD_RESET_FLAG_S  0
-
-#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xA4)
-/* RTC_CNTL_SWD_WKEY :  ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SWD_WKEY    0xFFFFFFFF
-#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
-#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
-#define RTC_CNTL_SWD_WKEY_S  0
-
-#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0xA8)
-/* RTC_CNTL_SW_STALL_PROCPU_C1 :  ;bitpos:[31:26] ;default: 6'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SW_STALL_PROCPU_C1    0x0000003F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
-#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
-
-#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0xAC)
-/* RTC_CNTL_SCRATCH4 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SCRATCH4    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
-#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH4_S  0
-
-#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0xB0)
-/* RTC_CNTL_SCRATCH5 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SCRATCH5    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
-#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH5_S  0
-
-#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0xB4)
-/* RTC_CNTL_SCRATCH6 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SCRATCH6    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
-#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH6_S  0
-
-#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0xB8)
-/* RTC_CNTL_SCRATCH7 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SCRATCH7    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
-#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH7_S  0
-
-#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0xBC)
-/* RTC_CNTL_MAIN_STATE :  ;bitpos:[31:28] ;default: 4'd0 ; */
-/*description: rtc main state machine status.*/
-#define RTC_CNTL_MAIN_STATE    0x0000000F
-#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
-#define RTC_CNTL_MAIN_STATE_V  0xF
-#define RTC_CNTL_MAIN_STATE_S  28
-/* RTC_CNTL_MAIN_STATE_IN_IDLE :  ;bitpos:[27] ;default: 1'b0 ; */
-/*description: rtc main state machine is in idle state.*/
-#define RTC_CNTL_MAIN_STATE_IN_IDLE    (BIT(27))
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
-/* RTC_CNTL_MAIN_STATE_IN_SLP :  ;bitpos:[26] ;default: 1'b0 ; */
-/*description: rtc main state machine is in sleep state.*/
-#define RTC_CNTL_MAIN_STATE_IN_SLP    (BIT(26))
-#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
-#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL :  ;bitpos:[25] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait xtal state.*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL    (BIT(25))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL :  ;bitpos:[24] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait pll state.*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL    (BIT(24))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M :  ;bitpos:[23] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait 8m state.*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M    (BIT(23))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
-/* RTC_CNTL_IN_LOW_POWER_STATE :  ;bitpos:[22] ;default: 1'b0 ; */
-/*description: rtc main state machine is in the states of low power.*/
-#define RTC_CNTL_IN_LOW_POWER_STATE    (BIT(22))
-#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
-#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
-#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
-/* RTC_CNTL_IN_WAKEUP_STATE :  ;bitpos:[21] ;default: 1'b0 ; */
-/*description: rtc main state machine is in the states of wakeup process.*/
-#define RTC_CNTL_IN_WAKEUP_STATE    (BIT(21))
-#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
-#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
-#define RTC_CNTL_IN_WAKEUP_STATE_S  21
-/* RTC_CNTL_MAIN_STATE_WAIT_END :  ;bitpos:[20] ;default: 1'b0 ; */
-/*description: rtc main state machine has been waited for some cycles.*/
-#define RTC_CNTL_MAIN_STATE_WAIT_END    (BIT(20))
-#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
-#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
-#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
-/* RTC_CNTL_RDY_FOR_WAKEUP :  ;bitpos:[19] ;default: 1'b0 ; */
-/*description: rtc is ready to receive wake up trigger from wake up source.*/
-#define RTC_CNTL_RDY_FOR_WAKEUP    (BIT(19))
-#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
-#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
-#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
-/* RTC_CNTL_MAIN_STATE_PLL_ON :  ;bitpos:[18] ;default: 1'b0 ; */
-/*description: rtc main state machine is in states that pll should be running.*/
-#define RTC_CNTL_MAIN_STATE_PLL_ON    (BIT(18))
-#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
-#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
-#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
-/* RTC_CNTL_MAIN_STATE_XTAL_ISO :  ;bitpos:[17] ;default: 1'b0 ; */
-/*description: no use any more.*/
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO    (BIT(17))
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
-/* RTC_CNTL_COCPU_STATE_DONE :  ;bitpos:[16] ;default: 1'b0 ; */
-/*description: ulp/cocpu is done.*/
-#define RTC_CNTL_COCPU_STATE_DONE    (BIT(16))
-#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
-#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
-#define RTC_CNTL_COCPU_STATE_DONE_S  16
-/* RTC_CNTL_COCPU_STATE_SLP :  ;bitpos:[15] ;default: 1'b0 ; */
-/*description: ulp/cocpu is in sleep state.*/
-#define RTC_CNTL_COCPU_STATE_SLP    (BIT(15))
-#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
-#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
-#define RTC_CNTL_COCPU_STATE_SLP_S  15
-/* RTC_CNTL_COCPU_STATE_SWITCH :  ;bitpos:[14] ;default: 1'b0 ; */
-/*description: ulp/cocpu is about to working. Switch rtc main state.*/
-#define RTC_CNTL_COCPU_STATE_SWITCH    (BIT(14))
-#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
-#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
-#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
-/* RTC_CNTL_COCPU_STATE_START :  ;bitpos:[13] ;default: 1'b0 ; */
-/*description: ulp/cocpu should start to work.*/
-#define RTC_CNTL_COCPU_STATE_START    (BIT(13))
-#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
-#define RTC_CNTL_COCPU_STATE_START_V  0x1
-#define RTC_CNTL_COCPU_STATE_START_S  13
-/* RTC_CNTL_TOUCH_STATE_DONE :  ;bitpos:[12] ;default: 1'b0 ; */
-/*description: touch is done.*/
-#define RTC_CNTL_TOUCH_STATE_DONE    (BIT(12))
-#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
-#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
-#define RTC_CNTL_TOUCH_STATE_DONE_S  12
-/* RTC_CNTL_TOUCH_STATE_SLP :  ;bitpos:[11] ;default: 1'b0 ; */
-/*description: touch is in sleep state.*/
-#define RTC_CNTL_TOUCH_STATE_SLP    (BIT(11))
-#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
-#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
-#define RTC_CNTL_TOUCH_STATE_SLP_S  11
-/* RTC_CNTL_TOUCH_STATE_SWITCH :  ;bitpos:[10] ;default: 1'b0 ; */
-/*description: touch is about to working. Switch rtc main state.*/
-#define RTC_CNTL_TOUCH_STATE_SWITCH    (BIT(10))
-#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
-#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
-#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
-/* RTC_CNTL_TOUCH_STATE_START :  ;bitpos:[9] ;default: 1'b0 ; */
-/*description: touch should start to work.*/
-#define RTC_CNTL_TOUCH_STATE_START    (BIT(9))
-#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
-#define RTC_CNTL_TOUCH_STATE_START_V  0x1
-#define RTC_CNTL_TOUCH_STATE_START_S  9
-/* RTC_CNTL_XPD_DIG :  ;bitpos:[8] ;default: 1'b0 ; */
-/*description: digital wrap power down.*/
-#define RTC_CNTL_XPD_DIG    (BIT(8))
-#define RTC_CNTL_XPD_DIG_M  (BIT(8))
-#define RTC_CNTL_XPD_DIG_V  0x1
-#define RTC_CNTL_XPD_DIG_S  8
-
-#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0xC0)
-/* RTC_CNTL_LOW_POWER_DIAG1 :  ;bitpos:[31:0] ;default: 0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_LOW_POWER_DIAG1    0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
-#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG1_S  0
-
-#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xC4)
-/* RTC_CNTL_GPIO_PIN5_HOLD :  ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN5_HOLD    (BIT(5))
-#define RTC_CNTL_GPIO_PIN5_HOLD_M  (BIT(5))
-#define RTC_CNTL_GPIO_PIN5_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN5_HOLD_S  5
-/* RTC_CNTL_GPIO_PIN4_HOLD :  ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN4_HOLD    (BIT(4))
-#define RTC_CNTL_GPIO_PIN4_HOLD_M  (BIT(4))
-#define RTC_CNTL_GPIO_PIN4_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN4_HOLD_S  4
-/* RTC_CNTL_GPIO_PIN3_HOLD :  ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN3_HOLD    (BIT(3))
-#define RTC_CNTL_GPIO_PIN3_HOLD_M  (BIT(3))
-#define RTC_CNTL_GPIO_PIN3_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN3_HOLD_S  3
-/* RTC_CNTL_GPIO_PIN2_HOLD :  ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN2_HOLD    (BIT(2))
-#define RTC_CNTL_GPIO_PIN2_HOLD_M  (BIT(2))
-#define RTC_CNTL_GPIO_PIN2_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN2_HOLD_S  2
-/* RTC_CNTL_GPIO_PIN1_HOLD :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN1_HOLD    (BIT(1))
-#define RTC_CNTL_GPIO_PIN1_HOLD_M  (BIT(1))
-#define RTC_CNTL_GPIO_PIN1_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN1_HOLD_S  1
-/* RTC_CNTL_GPIO_PIN0_HOLD :  ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN0_HOLD    (BIT(0))
-#define RTC_CNTL_GPIO_PIN0_HOLD_M  (BIT(0))
-#define RTC_CNTL_GPIO_PIN0_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN0_HOLD_S  0
-
-#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xC8)
-/* RTC_CNTL_DIG_PAD_HOLD :  ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DIG_PAD_HOLD    0xFFFFFFFF
-#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
-#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_DIG_PAD_HOLD_S  0
-
-#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0xCC)
-/* RTC_CNTL_BROWN_OUT_DET :  ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BROWN_OUT_DET    (BIT(31))
-#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
-#define RTC_CNTL_BROWN_OUT_DET_V  0x1
-#define RTC_CNTL_BROWN_OUT_DET_S  31
-/* RTC_CNTL_BROWN_OUT_ENA :  ;bitpos:[30] ;default: 1'b1 ; */
-/*description: enable brown out.*/
-#define RTC_CNTL_BROWN_OUT_ENA    (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_ENA_S  30
-/* RTC_CNTL_BROWN_OUT_CNT_CLR :  ;bitpos:[29] ;default: 1'b0 ; */
-/*description: clear brown out counter.*/
-#define RTC_CNTL_BROWN_OUT_CNT_CLR    (BIT(29))
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
-/* RTC_CNTL_BROWN_OUT_ANA_RST_EN :  ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN    (BIT(28))
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
-/* RTC_CNTL_BROWN_OUT_RST_SEL :  ;bitpos:[27] ;default: 1'b0 ; */
-/*description: 1:  4-pos reset.*/
-#define RTC_CNTL_BROWN_OUT_RST_SEL    (BIT(27))
-#define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
-#define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
-#define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
-/* RTC_CNTL_BROWN_OUT_RST_ENA :  ;bitpos:[26] ;default: 1'b0 ; */
-/*description: enable brown out reset.*/
-#define RTC_CNTL_BROWN_OUT_RST_ENA    (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
-/* RTC_CNTL_BROWN_OUT_RST_WAIT :  ;bitpos:[25:16] ;default: 10'h3ff ; */
-/*description: brown out reset wait cycles.*/
-#define RTC_CNTL_BROWN_OUT_RST_WAIT    0x000003FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
-/* RTC_CNTL_BROWN_OUT_PD_RF_ENA :  ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable power down RF when brown out happens.*/
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA    (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
-/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA :  ;bitpos:[14] ;default: 1'b0 ; */
-/*description: enable close flash when brown out happens.*/
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA    (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
-/* RTC_CNTL_BROWN_OUT_INT_WAIT :  ;bitpos:[13:4] ;default: 10'h1 ; */
-/*description: brown out interrupt wait cycles.*/
-#define RTC_CNTL_BROWN_OUT_INT_WAIT    0x000003FF
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
-
-#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0xD0)
-/* RTC_CNTL_TIMER_VALUE1_LOW :  ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: RTC timer low 32 bits.*/
-#define RTC_CNTL_TIMER_VALUE1_LOW    0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
-#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
-
-#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0xD4)
-/* RTC_CNTL_TIMER_VALUE1_HIGH :  ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC timer high 16 bits.*/
-#define RTC_CNTL_TIMER_VALUE1_HIGH    0x0000FFFF
-#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
-#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
-#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
-
-#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xD8)
-/* RTC_CNTL_IO_MUX_RESET_DISABLE :  ;bitpos:[18] ;default: 1'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_IO_MUX_RESET_DISABLE    (BIT(18))
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
-
-#define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0xDC)
-/* RTC_CNTL_REJECT_CAUSE :  ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: sleep reject cause.*/
-#define RTC_CNTL_REJECT_CAUSE    0x0003FFFF
-#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
-#define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
-#define RTC_CNTL_REJECT_CAUSE_S  0
-
-#define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0xE0)
-/* RTC_CNTL_FORCE_DOWNLOAD_BOOT :  ;bitpos:[0] ;default: 1'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT    (BIT(0))
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
-
-#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0xE4)
-/* RTC_CNTL_WAKEUP_CAUSE :  ;bitpos:[16:0] ;default: 17'd0 ; */
-/*description: sleep wakeup cause.*/
-#define RTC_CNTL_WAKEUP_CAUSE    0x0001FFFF
-#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
-#define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
-#define RTC_CNTL_WAKEUP_CAUSE_S  0
-
-#define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0xE8)
-/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE :  ;bitpos:[31:8] ;default: 24'd200 ; */
-/*description: sleep cycles for ULP-coprocessor timer.*/
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE    0x00FFFFFF
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
-
-#define RTC_CNTL_INT_ENA_RTC_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0xEC)
-/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS :  ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS    (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S  20
-/* RTC_CNTL_SWD_INT_ENA_W1TS :  ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define RTC_CNTL_SWD_INT_ENA_W1TS    (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS :  ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt.*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS :  ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt.*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
-/* RTC_CNTL_WDT_INT_ENA_W1TS :  ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define RTC_CNTL_WDT_INT_ENA_W1TS    (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
-/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt.*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS :  ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
-
-#define RTC_CNTL_INT_ENA_RTC_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0xF0)
-/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC :  ;bitpos:[20] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC    (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S  20
-/* RTC_CNTL_SWD_INT_ENA_W1TC :  ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define RTC_CNTL_SWD_INT_ENA_W1TC    (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC :  ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt.*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC :  ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt.*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
-/* RTC_CNTL_WDT_INT_ENA_W1TC :  ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define RTC_CNTL_WDT_INT_ENA_W1TC    (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
-/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt.*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC :  ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
-
-#define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0xF4)
-/* RTC_CNTL_RETENTION_WAIT :  ;bitpos:[31:27] ;default: 5'd20 ; */
-/*description: wait cycles for rention operation.*/
-#define RTC_CNTL_RETENTION_WAIT    0x0000001F
-#define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
-#define RTC_CNTL_RETENTION_WAIT_V  0x1F
-#define RTC_CNTL_RETENTION_WAIT_S  27
-/* RTC_CNTL_RETENTION_EN :  ;bitpos:[26] ;default: 1'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_RETENTION_EN    (BIT(26))
-#define RTC_CNTL_RETENTION_EN_M  (BIT(26))
-#define RTC_CNTL_RETENTION_EN_V  0x1
-#define RTC_CNTL_RETENTION_EN_S  26
-/* RTC_CNTL_RETENTION_CLKOFF_WAIT :  ;bitpos:[25:22] ;default: 4'd3 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT    0x0000000F
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  22
-/* RTC_CNTL_RETENTION_DONE_WAIT :  ;bitpos:[21:19] ;default: 3'd2 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_RETENTION_DONE_WAIT    0x00000007
-#define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
-#define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
-#define RTC_CNTL_RETENTION_DONE_WAIT_S  19
-/* RTC_CNTL_RETENTION_CLK_SEL :  ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_RETENTION_CLK_SEL    (BIT(18))
-#define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(18))
-#define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
-#define RTC_CNTL_RETENTION_CLK_SEL_S  18
-
-#define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0xF8)
-/* RTC_CNTL_FIB_SEL :  ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: select use analog fib signal.*/
-#define RTC_CNTL_FIB_SEL    0x00000007
-#define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
-#define RTC_CNTL_FIB_SEL_V  0x7
-#define RTC_CNTL_FIB_SEL_S  0
-
-#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
-#define RTC_CNTL_FIB_BOD_RST BIT(1)
-#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
-
-#define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0xFC)
-/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE :  ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE    (BIT(31))
-#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(31))
-#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S  31
-/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE :  ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE    (BIT(30))
-#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(30))
-#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S  30
-/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE :  ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE    (BIT(29))
-#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(29))
-#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S  29
-/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE :  ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE    (BIT(28))
-#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(28))
-#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S  28
-/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE :  ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE    (BIT(27))
-#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(27))
-#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S  27
-/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE :  ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE    (BIT(26))
-#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(26))
-#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S  26
-/* RTC_CNTL_GPIO_PIN0_INT_TYPE :  ;bitpos:[25:23] ;default: 3'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN0_INT_TYPE    0x00000007
-#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S  23
-/* RTC_CNTL_GPIO_PIN1_INT_TYPE :  ;bitpos:[22:20] ;default: 3'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN1_INT_TYPE    0x00000007
-#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S  20
-/* RTC_CNTL_GPIO_PIN2_INT_TYPE :  ;bitpos:[19:17] ;default: 3'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN2_INT_TYPE    0x00000007
-#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S  17
-/* RTC_CNTL_GPIO_PIN3_INT_TYPE :  ;bitpos:[16:14] ;default: 3'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN3_INT_TYPE    0x00000007
-#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S  14
-/* RTC_CNTL_GPIO_PIN4_INT_TYPE :  ;bitpos:[13:11] ;default: 3'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN4_INT_TYPE    0x00000007
-#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S  11
-/* RTC_CNTL_GPIO_PIN5_INT_TYPE :  ;bitpos:[10:8] ;default: 3'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN5_INT_TYPE    0x00000007
-#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S  8
-/* RTC_CNTL_GPIO_PIN_CLK_GATE :  ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN_CLK_GATE    (BIT(7))
-#define RTC_CNTL_GPIO_PIN_CLK_GATE_M  (BIT(7))
-#define RTC_CNTL_GPIO_PIN_CLK_GATE_V  0x1
-#define RTC_CNTL_GPIO_PIN_CLK_GATE_S  7
-/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR :  ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR    (BIT(6))
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M  (BIT(6))
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V  0x1
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S  6
-/* RTC_CNTL_GPIO_WAKEUP_STATUS :  ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_WAKEUP_STATUS    0x0000003F
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_M  ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S))
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_V  0x3F
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_S  0
-
-#define RTC_CNTL_DBG_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x100)
-/* RTC_CNTL_DEBUG_SEL4 :  ;bitpos:[31:27] ;default: 5'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DEBUG_SEL4    0x0000001F
-#define RTC_CNTL_DEBUG_SEL4_M  ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S))
-#define RTC_CNTL_DEBUG_SEL4_V  0x1F
-#define RTC_CNTL_DEBUG_SEL4_S  27
-/* RTC_CNTL_DEBUG_SEL3 :  ;bitpos:[26:22] ;default: 5'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DEBUG_SEL3    0x0000001F
-#define RTC_CNTL_DEBUG_SEL3_M  ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S))
-#define RTC_CNTL_DEBUG_SEL3_V  0x1F
-#define RTC_CNTL_DEBUG_SEL3_S  22
-/* RTC_CNTL_DEBUG_SEL2 :  ;bitpos:[21:17] ;default: 5'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DEBUG_SEL2    0x0000001F
-#define RTC_CNTL_DEBUG_SEL2_M  ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S))
-#define RTC_CNTL_DEBUG_SEL2_V  0x1F
-#define RTC_CNTL_DEBUG_SEL2_S  17
-/* RTC_CNTL_DEBUG_SEL1 :  ;bitpos:[16:12] ;default: 5'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DEBUG_SEL1    0x0000001F
-#define RTC_CNTL_DEBUG_SEL1_M  ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S))
-#define RTC_CNTL_DEBUG_SEL1_V  0x1F
-#define RTC_CNTL_DEBUG_SEL1_S  12
-/* RTC_CNTL_DEBUG_SEL0 :  ;bitpos:[11:7] ;default: 5'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DEBUG_SEL0    0x0000001F
-#define RTC_CNTL_DEBUG_SEL0_M  ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S))
-#define RTC_CNTL_DEBUG_SEL0_V  0x1F
-#define RTC_CNTL_DEBUG_SEL0_S  7
-/* RTC_CNTL_DEBUG_BIT_SEL :  ;bitpos:[6:2] ;default: 5'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DEBUG_BIT_SEL    0x0000001F
-#define RTC_CNTL_DEBUG_BIT_SEL_M  ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S))
-#define RTC_CNTL_DEBUG_BIT_SEL_V  0x1F
-#define RTC_CNTL_DEBUG_BIT_SEL_S  2
-/* RTC_CNTL_DEBUG_12M_NO_GATING :  ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DEBUG_12M_NO_GATING    (BIT(1))
-#define RTC_CNTL_DEBUG_12M_NO_GATING_M  (BIT(1))
-#define RTC_CNTL_DEBUG_12M_NO_GATING_V  0x1
-#define RTC_CNTL_DEBUG_12M_NO_GATING_S  1
-
-#define RTC_CNTL_DBG_MAP_REG          (DR_REG_RTCCNTL_BASE + 0x104)
-/* RTC_CNTL_GPIO_PIN0_FUN_SEL :  ;bitpos:[31:28] ;default: 4'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN0_FUN_SEL    0x0000000F
-#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S  28
-/* RTC_CNTL_GPIO_PIN1_FUN_SEL :  ;bitpos:[27:24] ;default: 4'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN1_FUN_SEL    0x0000000F
-#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S  24
-/* RTC_CNTL_GPIO_PIN2_FUN_SEL :  ;bitpos:[23:20] ;default: 4'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN2_FUN_SEL    0x0000000F
-#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S  20
-/* RTC_CNTL_GPIO_PIN3_FUN_SEL :  ;bitpos:[19:16] ;default: 4'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN3_FUN_SEL    0x0000000F
-#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S  16
-/* RTC_CNTL_GPIO_PIN4_FUN_SEL :  ;bitpos:[15:12] ;default: 4'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN4_FUN_SEL    0x0000000F
-#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S  12
-/* RTC_CNTL_GPIO_PIN5_FUN_SEL :  ;bitpos:[11:8] ;default: 4'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN5_FUN_SEL    0x0000000F
-#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S  8
-/* RTC_CNTL_GPIO_PIN0_MUX_SEL :  ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN0_MUX_SEL    (BIT(7))
-#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M  (BIT(7))
-#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S  7
-/* RTC_CNTL_GPIO_PIN1_MUX_SEL :  ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN1_MUX_SEL    (BIT(6))
-#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M  (BIT(6))
-#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S  6
-/* RTC_CNTL_GPIO_PIN2_MUX_SEL :  ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN2_MUX_SEL    (BIT(5))
-#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M  (BIT(5))
-#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S  5
-/* RTC_CNTL_GPIO_PIN3_MUX_SEL :  ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN3_MUX_SEL    (BIT(4))
-#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M  (BIT(4))
-#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S  4
-/* RTC_CNTL_GPIO_PIN4_MUX_SEL :  ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN4_MUX_SEL    (BIT(3))
-#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M  (BIT(3))
-#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S  3
-/* RTC_CNTL_GPIO_PIN5_MUX_SEL :  ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_GPIO_PIN5_MUX_SEL    (BIT(2))
-#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M  (BIT(2))
-#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S  2
-
-#define RTC_CNTL_SENSOR_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x108)
-/* RTC_CNTL_FORCE_XPD_SAR :  ;bitpos:[31:30] ;default: 2'b0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_FORCE_XPD_SAR    0x00000003
-#define RTC_CNTL_FORCE_XPD_SAR_M  ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S))
-#define RTC_CNTL_FORCE_XPD_SAR_V  0x3
-#define RTC_CNTL_FORCE_XPD_SAR_S  30
-/* RTC_CNTL_SAR2_PWDET_CCT :  ;bitpos:[29:27] ;default: 3'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SAR2_PWDET_CCT    0x00000007
-#define RTC_CNTL_SAR2_PWDET_CCT_M  ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S))
-#define RTC_CNTL_SAR2_PWDET_CCT_V  0x7
-#define RTC_CNTL_SAR2_PWDET_CCT_S  27
-
-#define RTC_CNTL_DBG_SAR_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x10C)
-/* RTC_CNTL_SAR_DEBUG_SEL :  ;bitpos:[31:27] ;default: 5'd0 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_SAR_DEBUG_SEL    0x0000001F
-#define RTC_CNTL_SAR_DEBUG_SEL_M  ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S))
-#define RTC_CNTL_SAR_DEBUG_SEL_V  0x1F
-#define RTC_CNTL_SAR_DEBUG_SEL_S  27
-
-#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x1FC)
-/* RTC_CNTL_DATE :  ;bitpos:[27:0] ;default: 28'h2107190 ; */
-/*description: Need add desc.*/
-#define RTC_CNTL_DATE    0x0FFFFFFF
-#define RTC_CNTL_DATE_M  ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S))
-#define RTC_CNTL_DATE_V  0xFFFFFFF
-#define RTC_CNTL_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_RTC_CNTL_REG_H_ */
diff --git a/components/soc/esp32c2/include/soc/rtc_cntl_struct.h b/components/soc/esp32c2/include/soc/rtc_cntl_struct.h
deleted file mode 100644
index 89a7820dc27..00000000000
--- a/components/soc/esp32c2/include/soc/rtc_cntl_struct.h
+++ /dev/null
@@ -1,708 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct rtc_cntl_dev_s{
-    union {
-        struct {
-            uint32_t reserved0                     :    2;  /*Reserved*/
-            uint32_t sw_stall_procpu_c0            :    2;  /*{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
-            uint32_t reserved4                     :    1;  /*Reserved*/
-            uint32_t sw_procpu_rst                 :    1;  /*PRO CPU SW reset*/
-            uint32_t bb_i2c_force_pd               :    1;  /*BB_I2C force power down*/
-            uint32_t bb_i2c_force_pu               :    1;  /*BB_I2C force power up*/
-            uint32_t bbpll_i2c_force_pd            :    1;  /*BB_PLL _I2C force power down*/
-            uint32_t bbpll_i2c_force_pu            :    1;  /*BB_PLL_I2C force power up*/
-            uint32_t bbpll_force_pd                :    1;  /*BB_PLL force power down*/
-            uint32_t bbpll_force_pu                :    1;  /*BB_PLL force power up*/
-            uint32_t xtl_force_pd                  :    1;  /*crystall force power down*/
-            uint32_t xtl_force_pu                  :    1;  /*crystall force power up*/
-            uint32_t xtl_en_wait                   :    4;  /*wait bias_sleep and current source wakeup*/
-            uint32_t reserved18                    :    2;  /*Reserved*/
-            uint32_t ctr_sel                       :    3;  /*Need add desc*/
-            uint32_t reserved23                    :    2;  /*Reserved*/
-            uint32_t analog_force_iso              :    1;  /*Need add desc*/
-            uint32_t reserved26                    :    2;  /*Reserved*/
-            uint32_t analog_force_noiso            :    1;  /*Need add desc*/
-            uint32_t dg_wrap_force_rst             :    1;  /*digital wrap force reset in deep sleep*/
-            uint32_t dg_wrap_force_norst           :    1;  /*digital core force no reset in deep sleep*/
-            uint32_t sw_sys_rst                    :    1;  /*SW system reset*/
-        };
-        uint32_t val;
-    } options0;
-    uint32_t slp_timer0;
-    union {
-        struct {
-            uint32_t slp_val_hi                    :    16;  /*RTC sleep timer high 16 bits*/
-            uint32_t main_timer_alarm_en           :    1;  /*timer alarm enable bit*/
-            uint32_t reserved17                    :    15;  /*Reserved*/
-        };
-        uint32_t val;
-    } slp_timer1;
-    union {
-        struct {
-            uint32_t reserved0                     :    27;  /*Reserved*/
-            uint32_t timer_sys_stall               :    1;  /*Enable to record system stall time*/
-            uint32_t timer_xtl_off                 :    1;  /*Enable to record 40M XTAL OFF time*/
-            uint32_t timer_sys_rst                 :    1;  /*enable to record system reset time*/
-            uint32_t reserved30                    :    1;  /*Reserved*/
-            uint32_t update                        :    1;  /*Set 1: to update register with RTC timer*/
-        };
-        uint32_t val;
-    } time_update;
-    uint32_t time_low0;
-    union {
-        struct {
-            uint32_t rtc_timer_value0_high         :    16;  /*RTC timer high 16 bits*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } time_high0;
-    union {
-        struct {
-            uint32_t rtc_sw_cpu_int                :    1;  /*rtc software interrupt to main cpu*/
-            uint32_t rtc_slp_reject_cause_clr      :    1;  /*clear rtc sleep reject cause*/
-            uint32_t reserved2                     :    20;  /*Reserved*/
-            uint32_t apb2rtc_bridge_sel            :    1;  /*1: APB to RTC using bridge*/
-            uint32_t reserved23                    :    5;  /*Reserved*/
-            uint32_t sdio_active_ind               :    1;  /*SDIO active indication*/
-            uint32_t slp_wakeup                    :    1;  /*leep wakeup bit*/
-            uint32_t slp_reject                    :    1;  /*leep reject bit*/
-            uint32_t sleep_en                      :    1;  /*sleep enable bit*/
-        };
-        uint32_t val;
-    } state0;
-    union {
-        struct {
-            uint32_t cpu_stall_en                  :    1;  /*CPU stall enable bit*/
-            uint32_t cpu_stall_wait                :    5;  /*CPU stall wait cycles in fast_clk_rtc*/
-            uint32_t ck8m_wait                     :    8;  /*CK8M wait cycles in slow_clk_rtc*/
-            uint32_t xtl_buf_wait                  :    10;  /*XTAL wait cycles in slow_clk_rtc*/
-            uint32_t pll_buf_wait                  :    8;  /*PLL wait cycles in slow_clk_rtc*/
-        };
-        uint32_t val;
-    } timer1;
-    union {
-        struct {
-            uint32_t reserved0                     :    24;  /*Reserved*/
-            uint32_t min_time_ck8m_off             :    8;  /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
-        };
-        uint32_t val;
-    } timer2;
-    union {
-        struct {
-            uint32_t reserved0                     :    16;  /*Reserved*/
-            uint32_t dg_wrap_wait_timer            :    9;  /*Need add desc*/
-            uint32_t dg_wrap_powerup_timer         :    7;  /*Need add desc*/
-        };
-        uint32_t val;
-    } timer4;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;  /*Reserved*/
-            uint32_t min_slp_val                   :    8;  /*minimal sleep cycles in slow_clk_rtc*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } timer5;
-    union {
-        struct {
-            uint32_t reserved0                     :    18;  /*Reserved*/
-            uint32_t i2c_reset_por_force_pd        :    1;  /*Need add desc*/
-            uint32_t i2c_reset_por_force_pu        :    1;  /*Need add desc*/
-            uint32_t reserved20                    :    2;  /*ReservedPLLA force power down*/
-            uint32_t sar_i2c_pu                    :    1;  /*PLLA force power up*/
-            uint32_t reserved23                    :    2;  /*Reserved*/
-            uint32_t bbpll_cal_slp_start           :    1;  /*start BBPLL calibration during sleep*/
-            uint32_t reserved26                    :    1;  /*Reserved*/
-            uint32_t txrf_i2c_pu                   :    1;  /*1: TXRF_I2C power up*/
-            uint32_t rfrx_pbus_pu                  :    1;  /*1: RFRX_PBUS power up*/
-            uint32_t reserved29                    :    1;  /*Reserved*/
-            uint32_t ckgen_i2c_pu                  :    1;  /*1: CKGEN_I2C power up*/
-            uint32_t pll_i2c_pu                    :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } ana_conf;
-    union {
-        struct {
-            uint32_t reset_cause_procpu            :    6;  /*reset cause of PRO CPU*/
-            uint32_t reserved6                     :    7;  /*Reserved*/
-            uint32_t stat_vector_sel_procpu        :    1;  /*PRO CPU state vector sel*/
-            uint32_t reserved14                    :    5;  /*Reserved*/
-            uint32_t ocd_halt_on_reset_procpu      :    1;  /*PROCPU OcdHaltOnReset*/
-            uint32_t rtc_dreset_mask_procpu        :    1;  /*Need add desc*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } reset_state;
-    union {
-        struct {
-            uint32_t reserved0                     :    15;  /*Reserved*/
-            uint32_t rtc_wakeup_ena                :    17;  /*wakeup enable bitmap*/
-        };
-        uint32_t val;
-    } wakeup_state;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject                    :    1;  /*enable sleep reject interrupt*/
-            uint32_t reserved2                     :    1;  /*Reservedenable SDIO idle interrupt*/
-            uint32_t rtc_wdt                       :    1;  /*enable RTC WDT interrupt*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t rtc_brown_out                 :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer                :    1;  /*enable RTC main timer interrupt*/
-            uint32_t reserved11                    :    4;  /*Reservedenable saradc2 interrupt*/
-            uint32_t rtc_swd                       :    1;  /*enable super watch dog interrupt*/
-            uint32_t reserved16                    :    4;  /*Reservedenable touch timeout interrupt*/
-            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt raw*/
-            uint32_t slp_reject                    :    1;  /*sleep reject interrupt raw*/
-            uint32_t reserved2                     :    1;  /*ReservedSDIO idle interrupt raw*/
-            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt raw*/
-            uint32_t reserved4                     :    5;  /*Reservedtouch inactive interrupt raw*/
-            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt raw*/
-            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt raw*/
-            uint32_t reserved11                    :    4;  /*Reservedsaradc2 interrupt raw*/
-            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt raw*/
-            uint32_t reserved16                    :    4;  /*Reservedtouch timeout interrupt raw*/
-            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt state*/
-            uint32_t slp_reject                    :    1;  /*sleep reject interrupt state*/
-            uint32_t reserved2                     :    1;  /*Reserved*/
-            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt state*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt state*/
-            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt state*/
-            uint32_t reserved11                    :    4;  /*Reserved*/
-            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt state*/
-            uint32_t reserved16                    :    4;  /*Reserved*/
-            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*Clear sleep wakeup interrupt state*/
-            uint32_t slp_reject                    :    1;  /*Clear sleep reject interrupt state*/
-            uint32_t reserved2                     :    1;  /*Reserved*/
-            uint32_t rtc_wdt                       :    1;  /*Clear RTC WDT interrupt state*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t rtc_brown_out                 :    1;  /*Clear brown out interrupt state*/
-            uint32_t rtc_main_timer                :    1;  /*Clear RTC main timer interrupt state*/
-            uint32_t reserved11                    :    4;  /*Reserved*/
-            uint32_t rtc_swd                       :    1;  /*Clear super watch dog interrupt state*/
-            uint32_t reserved16                    :    4;  /*Reserved*/
-            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    uint32_t store[4];
-    union {
-        struct {
-            uint32_t reserved0                     :    30;  /*Reserved*/
-            uint32_t ctr_lv                        :    1;  /*0: power down XTAL at high level*/
-            uint32_t ctr_en                        :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } ext_xtl_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    31;  /*Reserved*/
-            uint32_t gpio_wakeup_filter            :    1;  /*enable filter for gpio wakeup event*/
-        };
-        uint32_t val;
-    } ext_wakeup_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    12;  /*Reserved*/
-            uint32_t rtc_sleep_reject_ena          :    18;  /*sleep reject enable*/
-            uint32_t light_slp_reject_en           :    1;  /*enable reject for light sleep*/
-            uint32_t deep_slp_reject_en            :    1;  /*enable reject for deep sleep*/
-        };
-        uint32_t val;
-    } slp_reject_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    29;  /*Reserved*/
-            uint32_t cpusel_conf                   :    1;  /*CPU sel option*/
-            uint32_t cpuperiod_sel                 :    2;  /*Need add desc*/
-        };
-        uint32_t val;
-    } cpu_period_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;  /*Reserved*/
-            uint32_t efuse_clk_force_gating        :    1;  /*Need add desc*/
-            uint32_t efuse_clk_force_nogating      :    1;  /*Need add desc*/
-            uint32_t ck8m_div_sel_vld              :    1;  /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
-            uint32_t ck8m_div                      :    2;  /*CK8M_D256_OUT divider. 00: div128*/
-            uint32_t enb_ck8m                      :    1;  /*disable CK8M and CK8M_D256_OUT*/
-            uint32_t enb_ck8m_div                  :    1;  /*1: CK8M_D256_OUT is actually CK8M*/
-            uint32_t dig_xtal32k_en                :    1;  /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_d256_en             :    1;  /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_en                  :    1;  /*enable CK8M for digital core (no relationship with RTC core)*/
-            uint32_t reserved11                    :    1;  /*Reserved*/
-            uint32_t ck8m_div_sel                  :    3;  /*divider = reg_ck8m_div_sel + 1*/
-            uint32_t xtal_force_nogating           :    1;  /*XTAL force no gating during sleep*/
-            uint32_t ck8m_force_nogating           :    1;  /*CK8M force no gating during sleep*/
-            uint32_t ck8m_dfreq                    :    8;  /*CK8M_DFREQ*/
-            uint32_t ck8m_force_pd                 :    1;  /*CK8M force power down*/
-            uint32_t ck8m_force_pu                 :    1;  /*CK8M force power up*/
-            uint32_t xtal_global_force_gating      :    1;  /*Need add desc*/
-            uint32_t xtal_global_force_nogating    :    1;  /*Need add desc*/
-            uint32_t fast_clk_rtc_sel              :    1;  /*fast_clk_rtc sel. 0: XTAL div 2*/
-            uint32_t ana_clk_rtc_sel               :    2;  /*Need add desc*/
-        };
-        uint32_t val;
-    } clk_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    22;  /*Reserved*/
-            uint32_t rtc_ana_clk_div_vld           :    1;  /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
-            uint32_t rtc_ana_clk_div               :    8;  /*Need add desc*/
-            uint32_t slow_clk_next_edge            :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } slow_clk_conf;
-    union {
-        struct {
-            uint32_t dg_vdd_drv_b_slp              :    8;  /*Need add desc*/
-            uint32_t dg_vdd_drv_b_slp_en           :    1;  /*Need add desc*/
-            uint32_t reserved9                     :    1;  /*Reserved*/
-            uint32_t bias_buf_idle                 :    1;  /*Need add desc*/
-            uint32_t bias_buf_wake                 :    1;  /*Need add desc*/
-            uint32_t bias_buf_deep_slp             :    1;  /*Need add desc*/
-            uint32_t bias_buf_monitor              :    1;  /*Need add desc*/
-            uint32_t pd_cur_deep_slp               :    1;  /*xpd cur when rtc in sleep_state*/
-            uint32_t pd_cur_monitor                :    1;  /*xpd cur when rtc in monitor state*/
-            uint32_t bias_sleep_deep_slp           :    1;  /*bias_sleep when rtc in sleep_state*/
-            uint32_t bias_sleep_monitor            :    1;  /*bias_sleep when rtc in monitor state*/
-            uint32_t dbg_atten_deep_slp            :    4;  /*DBG_ATTEN when rtc in sleep state*/
-            uint32_t dbg_atten_monitor             :    4;  /*DBG_ATTEN when rtc in active state*/
-            uint32_t dbg_atten_active              :    4;  /*Need add desc*/
-            uint32_t reserved30                    :    2;  /*Reserved*/
-        };
-        uint32_t val;
-    } bias_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;  /*Reserved*/
-            uint32_t dig_cal_en                    :    1;  /*Need add desc*/
-            uint32_t reserved8                     :    6;  /*Reserved*/
-            uint32_t sck_dcap                      :    8;  /*SCK_DCAP*/
-            uint32_t reserved22                    :    8;  /*Reserved*/
-            uint32_t rtculator_force_pd            :    1;  /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
-            uint32_t rtculator_force_pu            :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } rtc;
-    union {
-        struct {
-            uint32_t reserved0                     :    21;  /*Reserved*/
-            uint32_t rtc_pad_force_hold            :    1;  /*rtc pad force hold*/
-            uint32_t reserved22                    :    10;  /*Reserved*/
-        };
-        uint32_t val;
-    } pwc;
-    union {
-        struct {
-            uint32_t vdd_spi_pwr_drv               :    2;  /*Need add desc*/
-            uint32_t vdd_spi_pwr_force             :    1;  /*Need add desc*/
-            uint32_t vdd_spi_pd_en                 :    1;  /*Need add desc*/
-            uint32_t lslp_mem_force_pd             :    1;  /*memories in digital core force PD in sleep*/
-            uint32_t lslp_mem_force_pu             :    1;  /*memories in digital core force no PD in sleep*/
-            uint32_t reserved6                     :    13;  /*Reserved*/
-            uint32_t dg_wrap_force_pd              :    1;  /*digital core force power down*/
-            uint32_t dg_wrap_force_pu              :    1;  /*digital core force power up*/
-            uint32_t reserved21                    :    10;  /*Reserved*/
-            uint32_t dg_wrap_pd_en                 :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } dig_pwc;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;  /*Reserved*/
-            uint32_t dig_iso_force_off             :    1;  /*Need add desc*/
-            uint32_t dig_iso_force_on              :    1;  /*Need add desc*/
-            uint32_t dg_pad_autohold               :    1;  /*read only register to indicate digital pad auto-hold status*/
-            uint32_t clr_dg_pad_autohold           :    1;  /*wtite only register to clear digital pad auto-hold*/
-            uint32_t dg_pad_autohold_en            :    1;  /*digital pad enable auto-hold*/
-            uint32_t dg_pad_force_noiso            :    1;  /*digital pad force no ISO*/
-            uint32_t dg_pad_force_iso              :    1;  /*digital pad force ISO*/
-            uint32_t dg_pad_force_unhold           :    1;  /*digital pad force un-hold*/
-            uint32_t dg_pad_force_hold             :    1;  /*digital pad force hold*/
-            uint32_t reserved16                    :    14;  /*Reserved*/
-            uint32_t dg_wrap_force_iso             :    1;  /*digital core force ISO*/
-            uint32_t dg_wrap_force_noiso           :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } dig_iso;
-    union {
-        struct {
-            uint32_t chip_reset_width              :    8;  /*chip reset siginal pulse width*/
-            uint32_t chip_reset_en                 :    1;  /*wdt reset whole chip enable*/
-            uint32_t pause_in_slp                  :    1;  /*pause WDT in sleep*/
-            uint32_t reserved10                    :    1;  /*Reservedenable WDT reset APP CPU*/
-            uint32_t procpu_reset_en               :    1;  /*enable WDT reset PRO CPU*/
-            uint32_t flashboot_mod_en              :    1;  /*enable WDT in flash boot*/
-            uint32_t sys_reset_length              :    3;  /*system reset counter length*/
-            uint32_t cpu_reset_length              :    3;  /*CPU reset counter length*/
-            uint32_t stg3                          :    3;  /*1: interrupt stage en*/
-            uint32_t stg2                          :    3;  /*1: interrupt stage en*/
-            uint32_t stg1                          :    3;  /*1: interrupt stage en*/
-            uint32_t stg0                          :    3;  /*1: interrupt stage en*/
-            uint32_t en                            :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } wdt_config0;
-    uint32_t wdt_config1;
-    uint32_t wdt_config2;
-    uint32_t wdt_config3;
-    uint32_t wdt_config4;
-    union {
-        struct {
-            uint32_t reserved0                     :    31;  /*Reserved*/
-            uint32_t feed                          :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } wdt_feed;
-    uint32_t wdt_wprotect;
-    union {
-        struct {
-            uint32_t swd_reset_flag                :    1;  /*swd reset flag*/
-            uint32_t swd_feed_int                  :    1;  /*swd interrupt for feeding*/
-            uint32_t reserved2                     :    15;  /*Reserved*/
-            uint32_t swd_bypass_rst                :    1;  /*Need add desc*/
-            uint32_t swd_signal_width              :    10;  /*adjust signal width send to swd*/
-            uint32_t swd_rst_flag_clr              :    1;  /*reset swd reset flag*/
-            uint32_t swd_feed                      :    1;  /*Sw feed swd*/
-            uint32_t swd_disable                   :    1;  /*disabel SWD*/
-            uint32_t swd_auto_feed_en              :    1;  /*automatically feed swd when int comes*/
-        };
-        uint32_t val;
-    } swd_conf;
-    uint32_t swd_wprotect;
-    union {
-        struct {
-            uint32_t reserved0                     :    26;  /*Reserved*/
-            uint32_t procpu_c1                     :    6;  /*Need add desc*/
-        };
-        uint32_t val;
-    } sw_cpu_stall;
-    uint32_t store4;
-    uint32_t store5;
-    uint32_t store6;
-    uint32_t store7;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;  /*Reserveddigital wrap iso*/
-            uint32_t xpd_dig                       :    1;  /*digital wrap power down*/
-            uint32_t rtc_touch_state_start         :    1;  /*touch should start to work*/
-            uint32_t rtc_touch_state_switch        :    1;  /*touch is about to working. Switch rtc main state*/
-            uint32_t rtc_touch_state_slp           :    1;  /*touch is in sleep state*/
-            uint32_t rtc_touch_state_done          :    1;  /*touch is done*/
-            uint32_t rtc_cocpu_state_start         :    1;  /*ulp/cocpu should start to work*/
-            uint32_t rtc_cocpu_state_switch        :    1;  /*ulp/cocpu is about to working. Switch rtc main state*/
-            uint32_t rtc_cocpu_state_slp           :    1;  /*ulp/cocpu is in sleep state*/
-            uint32_t rtc_cocpu_state_done          :    1;  /*ulp/cocpu is done*/
-            uint32_t rtc_main_state_xtal_iso       :    1;  /*no use any more*/
-            uint32_t rtc_main_state_pll_on         :    1;  /*rtc main state machine is in states that pll should be running*/
-            uint32_t rtc_rdy_for_wakeup            :    1;  /*rtc is ready to receive wake up trigger from wake up source*/
-            uint32_t rtc_main_state_wait_end       :    1;  /*rtc main state machine has been waited for some cycles*/
-            uint32_t rtc_in_wakeup_state           :    1;  /*rtc main state machine is in the states of wakeup process*/
-            uint32_t rtc_in_low_power_state        :    1;  /*rtc main state machine is in the states of low power*/
-            uint32_t rtc_main_state_in_wait_8m     :    1;  /*rtc main state machine is in wait 8m state*/
-            uint32_t rtc_main_state_in_wait_pll    :    1;  /*rtc main state machine is in wait pll state*/
-            uint32_t rtc_main_state_in_wait_xtl    :    1;  /*rtc main state machine is in wait xtal state*/
-            uint32_t rtc_main_state_in_slp         :    1;  /*rtc main state machine is in sleep state*/
-            uint32_t rtc_main_state_in_idle        :    1;  /*rtc main state machine is in idle state*/
-            uint32_t rtc_main_state                :    4;  /*rtc main state machine status*/
-        };
-        uint32_t val;
-    } low_power_st;
-    uint32_t diag0;
-    union {
-        struct {
-            uint32_t rtc_gpio_pin0_hold            :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin1_hold            :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin2_hold            :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin3_hold            :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin4_hold            :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin5_hold            :    1;  /*Need add desc*/
-            uint32_t reserved6                     :    26;  /*Reserved*/
-        };
-        uint32_t val;
-    } pad_hold;
-    uint32_t dig_pad_hold;
-    union {
-        struct {
-            uint32_t reserved0                     :    4;  /*Reserved*/
-            uint32_t int_wait                      :    10;  /*brown out interrupt wait cycles*/
-            uint32_t close_flash_ena               :    1;  /*enable close flash when brown out happens*/
-            uint32_t pd_rf_ena                     :    1;  /*enable power down RF when brown out happens*/
-            uint32_t rst_wait                      :    10;  /*brown out reset wait cycles*/
-            uint32_t rst_ena                       :    1;  /*enable brown out reset*/
-            uint32_t rst_sel                       :    1;  /*1:  4-pos reset*/
-            uint32_t ana_rst_en                    :    1;  /*Need add desc*/
-            uint32_t cnt_clr                       :    1;  /*clear brown out counter*/
-            uint32_t ena                           :    1;  /*enable brown out*/
-            uint32_t det                           :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } brown_out;
-    uint32_t time_low1;
-    union {
-        struct {
-            uint32_t rtc_timer_value1_high         :    16;  /*RTC timer high 16 bits*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } time_high1;
-    union {
-        struct {
-            uint32_t reserved0                     :    18;  /*Reserved*/
-            uint32_t io_mux_reset_disable          :    1;  /*Need add desc*/
-            uint32_t reserved19                    :    13;  /*Reserved*/
-        };
-        uint32_t val;
-    } usb_conf;
-    union {
-        struct {
-            uint32_t reject_cause                  :    18;  /*sleep reject cause*/
-            uint32_t reserved18                    :    14;  /*Reserved*/
-        };
-        uint32_t val;
-    } slp_reject_cause;
-    union {
-        struct {
-            uint32_t force_download_boot           :    1;  /*Need add desc*/
-            uint32_t reserved1                     :    31;  /*Reserved*/
-        };
-        uint32_t val;
-    } option1;
-    union {
-        struct {
-            uint32_t wakeup_cause                  :    17;  /*sleep wakeup cause*/
-            uint32_t reserved17                    :    15;  /*Reserved*/
-        };
-        uint32_t val;
-    } slp_wakeup_cause;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;  /*Reserved*/
-            uint32_t ulp_cp_timer_slp_cycle        :    24;  /*sleep cycles for ULP-coprocessor timer*/
-        };
-        uint32_t val;
-    } ulp_cp_timer_1;
-    union {
-        struct {
-            uint32_t slp_wakeup_w1ts               :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject_w1ts               :    1;  /*enable sleep reject interrupt*/
-            uint32_t reserved2                     :    1;  /*Reserved*/
-            uint32_t rtc_wdt_w1ts                  :    1;  /*enable RTC WDT interrupt*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t w1ts                          :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer_w1ts           :    1;  /*enable RTC main timer interrupt*/
-            uint32_t reserved11                    :    4;  /*Reserved*/
-            uint32_t rtc_swd_w1ts                  :    1;  /*enable super watch dog interrupt*/
-            uint32_t reserved16                    :    4;  /*Reservedenbale gitch det interrupt*/
-            uint32_t rtc_bbpll_cal_w1ts            :    1;  /*Need add desc*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena_w1ts;
-    union {
-        struct {
-            uint32_t slp_wakeup_w1tc               :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject_w1tc               :    1;  /*enable sleep reject interrupt*/
-            uint32_t reserved2                     :    1;  /*Reserved*/
-            uint32_t rtc_wdt_w1tc                  :    1;  /*enable RTC WDT interrupt*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t w1tc                          :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer_w1tc           :    1;  /*enable RTC main timer interrupt*/
-            uint32_t reserved11                    :    4;  /*Reserved*/
-            uint32_t rtc_swd_w1tc                  :    1;  /*enable super watch dog interrupt*/
-            uint32_t reserved16                    :    4;  /*Reservedenbale gitch det interrupt*/
-            uint32_t rtc_bbpll_cal_w1tc            :    1;  /*Need add desc*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena_w1tc;
-    union {
-        struct {
-            uint32_t reserved0                     :    18;  /*Reserved*/
-            uint32_t retention_clk_sel             :    1;  /*Need add desc*/
-            uint32_t retention_done_wait           :    3;  /*Need add desc*/
-            uint32_t retention_clkoff_wait         :    4;  /*Need add desc*/
-            uint32_t retention_en                  :    1;  /*Need add desc*/
-            uint32_t retention_wait                :    5;  /*wait cycles for rention operation*/
-        };
-        uint32_t val;
-    } retention_ctrl;
-    union {
-        struct {
-            uint32_t rtc_fib_sel                   :    3;  /*select use analog fib signal*/
-            uint32_t reserved3                     :    29;  /*Reserved*/
-        };
-        uint32_t val;
-    } fib_sel;
-    union {
-        struct {
-            uint32_t rtc_gpio_wakeup_status        :    6;  /*Need add desc*/
-            uint32_t rtc_gpio_wakeup_status_clr    :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin_clk_gate         :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin5_int_type        :    3;  /*Need add desc*/
-            uint32_t rtc_gpio_pin4_int_type        :    3;  /*Need add desc*/
-            uint32_t rtc_gpio_pin3_int_type        :    3;  /*Need add desc*/
-            uint32_t rtc_gpio_pin2_int_type        :    3;  /*Need add desc*/
-            uint32_t rtc_gpio_pin1_int_type        :    3;  /*Need add desc*/
-            uint32_t rtc_gpio_pin0_int_type        :    3;  /*Need add desc*/
-            uint32_t rtc_gpio_pin5_wakeup_enable   :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin4_wakeup_enable   :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin3_wakeup_enable   :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin2_wakeup_enable   :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin1_wakeup_enable   :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin0_wakeup_enable   :    1;  /*Need add desc*/
-        };
-        uint32_t val;
-    } gpio_wakeup;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;  /*Reserved*/
-            uint32_t rtc_debug_12m_no_gating       :    1;  /*Need add desc*/
-            uint32_t rtc_debug_bit_sel             :    5;  /*Need add desc*/
-            uint32_t rtc_debug_sel0                :    5;  /*Need add desc*/
-            uint32_t rtc_debug_sel1                :    5;  /*Need add desc*/
-            uint32_t rtc_debug_sel2                :    5;  /*Need add desc*/
-            uint32_t rtc_debug_sel3                :    5;  /*Need add desc*/
-            uint32_t rtc_debug_sel4                :    5;  /*Need add desc*/
-        };
-        uint32_t val;
-    } dbg_sel;
-    union {
-        struct {
-            uint32_t reserved0                     :    2;  /*Reserved*/
-            uint32_t rtc_gpio_pin5_mux_sel         :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin4_mux_sel         :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin3_mux_sel         :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin2_mux_sel         :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin1_mux_sel         :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin0_mux_sel         :    1;  /*Need add desc*/
-            uint32_t rtc_gpio_pin5_fun_sel         :    4;  /*Need add desc*/
-            uint32_t rtc_gpio_pin4_fun_sel         :    4;  /*Need add desc*/
-            uint32_t rtc_gpio_pin3_fun_sel         :    4;  /*Need add desc*/
-            uint32_t rtc_gpio_pin2_fun_sel         :    4;  /*Need add desc*/
-            uint32_t rtc_gpio_pin1_fun_sel         :    4;  /*Need add desc*/
-            uint32_t rtc_gpio_pin0_fun_sel         :    4;  /*Need add desc*/
-        };
-        uint32_t val;
-    } dbg_map;
-    union {
-        struct {
-            uint32_t reserved0                     :    27;  /*Reserved*/
-            uint32_t sar2_pwdet_cct                :    3;  /*Need add desc*/
-            uint32_t force_xpd_sar                 :    2;  /*Need add desc*/
-        };
-        uint32_t val;
-    } sensor_ctrl;
-    union {
-        struct {
-            uint32_t reserved0                     :    27;  /*Reserved*/
-            uint32_t sar_debug_sel                 :    5;  /*Need add desc*/
-        };
-        uint32_t val;
-    } dbg_sar_sel;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*Need add desc*/
-            uint32_t reserved28                    :    4;  /*Reserved*/
-        };
-        uint32_t val;
-    } date;
-} rtc_cntl_dev_t;
-extern rtc_cntl_dev_t RTCCNTL;
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h
index a57b15794ae..a24a2b197e6 100644
--- a/components/soc/esp32c2/include/soc/soc.h
+++ b/components/soc/esp32c2/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 
diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h
index 7e93ba62266..3cd251ac81c 100644
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@@ -170,6 +170,7 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK  (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK     (1)
+#define SOC_LEDC_TIMER_NUM              (4)
 #define SOC_LEDC_CHANNEL_NUM            (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH        (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP      (1)
@@ -335,6 +336,8 @@
 
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< ESP32C2 only supports to connect an external oscillator, not a crystal */
 
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2           (1)     /*!< Support XTAL_D2 clock as the LP_FAST clock source */
+
 /*------------------------------------ WI-FI CAPS ------------------------------------*/
 #define SOC_WIFI_HW_TSF                           (1)    /*!< Support hardware TSF */
 #define SOC_WIFI_FTM_SUPPORT                      (1)    /*!< Support FTM */
diff --git a/components/soc/esp32c2/include/soc/spi_mem_reg.h b/components/soc/esp32c2/include/soc/spi_mem_reg.h
deleted file mode 100644
index bd22f94efb1..00000000000
--- a/components/soc/esp32c2/include/soc/spi_mem_reg.h
+++ /dev/null
@@ -1,1270 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SPI_MEM_REG_H_
-#define _SOC_SPI_MEM_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
-/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (BIT(31))
-#define SPI_MEM_FLASH_READ_V  0x1
-#define SPI_MEM_FLASH_READ_S  31
-/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
-bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (BIT(30))
-#define SPI_MEM_FLASH_WREN_V  0x1
-#define SPI_MEM_FLASH_WREN_S  30
-/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Write flash disable. Write disable command will be sent when the bit is set. The
- bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
-#define SPI_MEM_FLASH_WRDI_V  0x1
-#define SPI_MEM_FLASH_WRDI_S  29
-/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
-e cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (BIT(28))
-#define SPI_MEM_FLASH_RDID_V  0x1
-#define SPI_MEM_FLASH_RDID_S  28
-/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Read status register-1.  Read status operation will be triggered when the bit is
- set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
-#define SPI_MEM_FLASH_RDSR_V  0x1
-#define SPI_MEM_FLASH_RDSR_S  27
-/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write status register enable.   Write status operation  will be triggered when t
-he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
-ble..*/
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
-#define SPI_MEM_FLASH_WRSR_V  0x1
-#define SPI_MEM_FLASH_WRSR_S  26
-/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
-tion  will be triggered when the bit is set. The bit will be cleared once the op
-eration done .1: enable 0: disable..*/
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (BIT(25))
-#define SPI_MEM_FLASH_PP_V  0x1
-#define SPI_MEM_FLASH_PP_S  25
-/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
-is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (BIT(24))
-#define SPI_MEM_FLASH_SE_V  0x1
-#define SPI_MEM_FLASH_SE_S  24
-/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
- is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (BIT(23))
-#define SPI_MEM_FLASH_BE_V  0x1
-#define SPI_MEM_FLASH_BE_S  23
-/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (BIT(22))
-#define SPI_MEM_FLASH_CE_V  0x1
-#define SPI_MEM_FLASH_CE_S  22
-/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
-. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (BIT(21))
-#define SPI_MEM_FLASH_DP_V  0x1
-#define SPI_MEM_FLASH_DP_S  21
-/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
-e or high performance mode and obtains the devices ID. The bit will be cleared o
-nce the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (BIT(20))
-#define SPI_MEM_FLASH_RES_V  0x1
-#define SPI_MEM_FLASH_RES_S  20
-/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
-ion done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (BIT(19))
-#define SPI_MEM_FLASH_HPM_V  0x1
-#define SPI_MEM_FLASH_HPM_S  19
-/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
-/*description: User define command enable.  An operation will be triggered when the bit is set.
- The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (BIT(18))
-#define SPI_MEM_USR_V  0x1
-#define SPI_MEM_USR_S  18
-/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
-/*description: In user mode, it is set to indicate that program/erase operation will be trigger
-ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
-peration done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (BIT(17))
-#define SPI_MEM_FLASH_PE_V  0x1
-#define SPI_MEM_FLASH_PE_S  17
-/* SPI_MEM_MSPI_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation sta
-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
-ate, 6:write data state, 7: done state, 8: read data end state..*/
-#define SPI_MEM_MSPI_ST    0x0000000F
-#define SPI_MEM_MSPI_ST_M  ((SPI_MEM_MSPI_ST_V)<<(SPI_MEM_MSPI_ST_S))
-#define SPI_MEM_MSPI_ST_V  0xF
-#define SPI_MEM_MSPI_ST_S  4
-/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: The current status of SPI1 master FSM..*/
-#define SPI_MEM_MST_ST    0x0000000F
-#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
-#define SPI_MEM_MST_ST_V  0xF
-#define SPI_MEM_MST_ST_S  0
-
-#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
-/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
-address, the bit24-bit31 are the byte length of a transfer..*/
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_S  0
-
-#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
-/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
-ble 0: disable..*/
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (BIT(24))
-#define SPI_MEM_FREAD_QIO_V  0x1
-#define SPI_MEM_FREAD_QIO_S  24
-/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
-ble 0: disable..*/
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (BIT(23))
-#define SPI_MEM_FREAD_DIO_V  0x1
-#define SPI_MEM_FREAD_DIO_S  23
-/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
-isable..*/
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (BIT(22))
-#define SPI_MEM_WRSR_2B_V  0x1
-#define SPI_MEM_WRSR_2B_S  22
-/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (BIT(21))
-#define SPI_MEM_WP_REG_V  0x1
-#define SPI_MEM_WP_REG_S  21
-/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
-#define SPI_MEM_FREAD_QUAD_V  0x1
-#define SPI_MEM_FREAD_QUAD_S  20
-/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (BIT(19))
-#define SPI_MEM_D_POL_V  0x1
-#define SPI_MEM_D_POL_S  19
-/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (BIT(18))
-#define SPI_MEM_Q_POL_V  0x1
-#define SPI_MEM_Q_POL_S  18
-/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-spi_mem_flash_res bit. 1: enable 0: disable..*/
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (BIT(15))
-#define SPI_MEM_RESANDRES_V  0x1
-#define SPI_MEM_RESANDRES_S  15
-/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
-#define SPI_MEM_FREAD_DUAL_V  0x1
-#define SPI_MEM_FREAD_DUAL_S  14
-/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
-UT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
-#define SPI_MEM_FASTRD_MODE_V  0x1
-#define SPI_MEM_FASTRD_MODE_S  13
-/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
-e.*/
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
-#define SPI_MEM_TX_CRC_EN_V  0x1
-#define SPI_MEM_TX_CRC_EN_S  11
-/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
-e low..*/
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_V  0x1
-#define SPI_MEM_FCS_CRC_EN_S  10
-/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
-#define SPI_MEM_FCMD_QUAD_V  0x1
-#define SPI_MEM_FCMD_QUAD_S  8
-/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Apply 2 signals during command phase 1:enable 0: disable.*/
-#define SPI_MEM_FCMD_DUAL    (BIT(7))
-#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
-#define SPI_MEM_FCMD_DUAL_V  0x1
-#define SPI_MEM_FCMD_DUAL_S  7
-/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: In the dummy phase the signal level of spi is output by the spi controller..*/
-#define SPI_MEM_FDUMMY_OUT    (BIT(3))
-#define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
-#define SPI_MEM_FDUMMY_OUT_V  0x1
-#define SPI_MEM_FDUMMY_OUT_S  3
-
-#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
-/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: SPI0 RX FIFO reset signal..*/
-#define SPI_MEM_RXFIFO_RST    (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
-#define SPI_MEM_RXFIFO_RST_V  0x1
-#define SPI_MEM_RXFIFO_RST_S  30
-/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
-/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
-12) SPI_CLK cycles..*/
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
-#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
-/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on..*/
-#define SPI_MEM_CLK_MODE    0x00000003
-#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
-#define SPI_MEM_CLK_MODE_V  0x3
-#define SPI_MEM_CLK_MODE_S  0
-
-#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
-/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The FSM will be reset..*/
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (BIT(31))
-#define SPI_MEM_SYNC_RESET_V  0x1
-#define SPI_MEM_SYNC_RESET_S  31
-/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
- clock cycles..*/
-#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
-/*description: Spi cs signal is delayed to inactive by spi clock this bits are combined with sp
-i_mem_cs_hold bit..*/
-#define SPI_MEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
-#define SPI_MEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
-/*description: (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_
-setup bit..*/
-#define SPI_MEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
-#define SPI_MEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_CS_SETUP_TIME_S  0
-
-#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
-/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit in 1-division mode..*/
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
-/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- system/(spi_mem_clkcnt_N+1).*/
-#define SPI_MEM_CLKCNT_N    0x000000FF
-#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
-#define SPI_MEM_CLKCNT_N_V  0xFF
-#define SPI_MEM_CLKCNT_N_S  16
-/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define SPI_MEM_CLKCNT_H    0x000000FF
-#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
-#define SPI_MEM_CLKCNT_H_V  0xFF
-#define SPI_MEM_CLKCNT_H_S  8
-/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
-#define SPI_MEM_CLKCNT_L    0x000000FF
-#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
-#define SPI_MEM_CLKCNT_L_V  0xFF
-#define SPI_MEM_CLKCNT_L_S  0
-
-#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
-/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation..*/
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (BIT(31))
-#define SPI_MEM_USR_COMMAND_V  0x1
-#define SPI_MEM_USR_COMMAND_S  31
-/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation..*/
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (BIT(30))
-#define SPI_MEM_USR_ADDR_V  0x1
-#define SPI_MEM_USR_ADDR_S  30
-/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation..*/
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (BIT(29))
-#define SPI_MEM_USR_DUMMY_V  0x1
-#define SPI_MEM_USR_DUMMY_S  29
-/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation..*/
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (BIT(28))
-#define SPI_MEM_USR_MISO_V  0x1
-#define SPI_MEM_USR_MISO_S  28
-/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation..*/
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (BIT(27))
-#define SPI_MEM_USR_MOSI_V  0x1
-#define SPI_MEM_USR_MOSI_S  27
-/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable..*/
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
-1: enable 0: disable..*/
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
-: enable 0: disable..*/
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 4 signals..*/
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
-#define SPI_MEM_FWRITE_QIO_V  0x1
-#define SPI_MEM_FWRITE_QIO_S  15
-/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 2 signals..*/
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
-#define SPI_MEM_FWRITE_DIO_V  0x1
-#define SPI_MEM_FWRITE_DIO_S  14
-/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals.*/
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_V  0x1
-#define SPI_MEM_FWRITE_QUAD_S  13
-/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals.*/
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_V  0x1
-#define SPI_MEM_FWRITE_DUAL_S  12
-/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode
-..*/
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_V  0x1
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
-#define SPI_MEM_CS_SETUP    (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (BIT(7))
-#define SPI_MEM_CS_SETUP_V  0x1
-#define SPI_MEM_CS_SETUP_S  7
-/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
-#define SPI_MEM_CS_HOLD    (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (BIT(6))
-#define SPI_MEM_CS_HOLD_V  0x1
-#define SPI_MEM_CS_HOLD_S  6
-
-#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
-/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
-/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
-/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
-cle_num-1)..*/
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
-/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
-#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
-/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command..*/
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
-#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
-#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-
-#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
-/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
-
-#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
-/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
-
-#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
-/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
-it..*/
-#define SPI_MEM_WB_MODE    0x000000FF
-#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
-#define SPI_MEM_WB_MODE_V  0xFF
-#define SPI_MEM_WB_MODE_S  16
-/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
-#define SPI_MEM_STATUS    0x0000FFFF
-#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
-#define SPI_MEM_STATUS_V  0xFFFF
-#define SPI_MEM_STATUS_S  0
-
-#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
-/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: spi cs line keep low when the bit is set..*/
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
-/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle.*/
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_V  0x1
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/* SPI_MEM_CSPI_ST_TRANS_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt of spi0_slv_st controlled transmitting i
-s done..*/
-#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA    (BIT(6))
-#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_M  (BIT(6))
-#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_V  0x1
-#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_S  6
-/* SPI_MEM_CSPI_ST_TRANS_END : R/W/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the  spi0_slv_st controlled transmitting is done..*/
-#define SPI_MEM_CSPI_ST_TRANS_END    (BIT(5))
-#define SPI_MEM_CSPI_ST_TRANS_END_M  (BIT(5))
-#define SPI_MEM_CSPI_ST_TRANS_END_V  0x1
-#define SPI_MEM_CSPI_ST_TRANS_END_S  5
-/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting
-is done..*/
-#define SPI_MEM_TRANS_END_INT_ENA    (BIT(4))
-#define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(4))
-#define SPI_MEM_TRANS_END_INT_ENA_V  0x1
-#define SPI_MEM_TRANS_END_INT_ENA_S  4
-/* SPI_MEM_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the  spi0_mst_st controlled transmitting is done..*/
-#define SPI_MEM_TRANS_END    (BIT(3))
-#define SPI_MEM_TRANS_END_M  (BIT(3))
-#define SPI_MEM_TRANS_END_V  0x1
-#define SPI_MEM_TRANS_END_S  3
-/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
-evice, such as flash, external RAM and so on..*/
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (BIT(1))
-#define SPI_MEM_CS1_DIS_V  0x1
-#define SPI_MEM_CS1_DIS_S  1
-/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
-evice, such as flash, external RAM and so on..*/
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (BIT(0))
-#define SPI_MEM_CS0_DIS_V  0x1
-#define SPI_MEM_CS0_DIS_S  0
-
-#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
-/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: For SPI1, the value of crc32..*/
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_S  0
-
-#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
-/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_qio..*/
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
-#define SPI_MEM_FADDR_QUAD_V  0x1
-#define SPI_MEM_FADDR_QUAD_S  8
-/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
-e same with spi_mem_fread_qio..*/
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_V  0x1
-#define SPI_MEM_FDOUT_QUAD_S  7
-/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
- same with spi_mem_fread_qio..*/
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
-#define SPI_MEM_FDIN_QUAD_V  0x1
-#define SPI_MEM_FDIN_QUAD_S  6
-/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_dio..*/
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
-#define SPI_MEM_FADDR_DUAL_V  0x1
-#define SPI_MEM_FADDR_DUAL_S  5
-/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
- same with spi_mem_fread_dio..*/
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_V  0x1
-#define SPI_MEM_FDOUT_DUAL_S  4
-/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
-same with spi_mem_fread_dio..*/
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
-#define SPI_MEM_FDIN_DUAL_V  0x1
-#define SPI_MEM_FDIN_DUAL_S  3
-/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
-#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
-/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, Cache access enable, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_REQ_EN    (BIT(0))
-#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
-#define SPI_MEM_CACHE_REQ_EN_V  0x1
-#define SPI_MEM_CACHE_REQ_EN_S  0
-
-#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
-/* SPI_MEM_CSPI_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
-/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
-#define SPI_MEM_CSPI_LOCK_DELAY_TIME    0x0000001F
-#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M  ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S))
-#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V  0x1F
-#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S  7
-/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GR
-ANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDM
-A sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
-#define SPI_MEM_EM_ST    0x00000007
-#define SPI_MEM_EM_ST_M  ((SPI_MEM_EM_ST_V)<<(SPI_MEM_EM_ST_S))
-#define SPI_MEM_EM_ST_V  0x7
-#define SPI_MEM_EM_ST_S  4
-/* SPI_MEM_CSPI_ST : RO ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation
- state, 2: send command state, 3: send address state, 4: wait state, 5: read dat
-a state, 6:write data state, 7: done state, 8: read data end state..*/
-#define SPI_MEM_CSPI_ST    0x0000000F
-#define SPI_MEM_CSPI_ST_M  ((SPI_MEM_CSPI_ST_V)<<(SPI_MEM_CSPI_ST_S))
-#define SPI_MEM_CSPI_ST_V  0xF
-#define SPI_MEM_CSPI_ST_S  0
-
-#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
-/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF0    0xFFFFFFFF
-#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
-#define SPI_MEM_BUF0_V  0xFFFFFFFF
-#define SPI_MEM_BUF0_S  0
-
-#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
-/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF1    0xFFFFFFFF
-#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
-#define SPI_MEM_BUF1_V  0xFFFFFFFF
-#define SPI_MEM_BUF1_S  0
-
-#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
-/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF2    0xFFFFFFFF
-#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
-#define SPI_MEM_BUF2_V  0xFFFFFFFF
-#define SPI_MEM_BUF2_S  0
-
-#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
-/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF3    0xFFFFFFFF
-#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
-#define SPI_MEM_BUF3_V  0xFFFFFFFF
-#define SPI_MEM_BUF3_S  0
-
-#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
-/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF4    0xFFFFFFFF
-#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
-#define SPI_MEM_BUF4_V  0xFFFFFFFF
-#define SPI_MEM_BUF4_S  0
-
-#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
-/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF5    0xFFFFFFFF
-#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
-#define SPI_MEM_BUF5_V  0xFFFFFFFF
-#define SPI_MEM_BUF5_S  0
-
-#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
-/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF6    0xFFFFFFFF
-#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
-#define SPI_MEM_BUF6_V  0xFFFFFFFF
-#define SPI_MEM_BUF6_S  0
-
-#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
-/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF7    0xFFFFFFFF
-#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
-#define SPI_MEM_BUF7_V  0xFFFFFFFF
-#define SPI_MEM_BUF7_S  0
-
-#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
-/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF8    0xFFFFFFFF
-#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
-#define SPI_MEM_BUF8_V  0xFFFFFFFF
-#define SPI_MEM_BUF8_S  0
-
-#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
-/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF9    0xFFFFFFFF
-#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
-#define SPI_MEM_BUF9_V  0xFFFFFFFF
-#define SPI_MEM_BUF9_S  0
-
-#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
-/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF10    0xFFFFFFFF
-#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
-#define SPI_MEM_BUF10_V  0xFFFFFFFF
-#define SPI_MEM_BUF10_S  0
-
-#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
-/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF11    0xFFFFFFFF
-#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
-#define SPI_MEM_BUF11_V  0xFFFFFFFF
-#define SPI_MEM_BUF11_S  0
-
-#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
-/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF12    0xFFFFFFFF
-#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
-#define SPI_MEM_BUF12_V  0xFFFFFFFF
-#define SPI_MEM_BUF12_S  0
-
-#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
-/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF13    0xFFFFFFFF
-#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
-#define SPI_MEM_BUF13_V  0xFFFFFFFF
-#define SPI_MEM_BUF13_S  0
-
-#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
-/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF14    0xFFFFFFFF
-#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
-#define SPI_MEM_BUF14_V  0xFFFFFFFF
-#define SPI_MEM_BUF14_S  0
-
-#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
-/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF15    0xFFFFFFFF
-#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
-#define SPI_MEM_BUF15_V  0xFFFFFFFF
-#define SPI_MEM_BUF15_S  0
-
-#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
-/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
-/*description: The dummy cycle length when wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
-/*description: The command to wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_CMD    0x000000FF
-#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
-#define SPI_MEM_WAITI_CMD_V  0xFF
-#define SPI_MEM_WAITI_CMD_S  2
-/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The dummy phase enable when wait flash idle (RDSR).*/
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_V  0x1
-#define SPI_MEM_WAITI_DUMMY_S  1
-
-#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
-/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
-/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
- it will be treated as check pass..*/
-#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
-/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
-s of flash. 0: Only need to check WIP is 0..*/
-#define SPI_MEM_PES_END_EN    (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (BIT(24))
-#define SPI_MEM_PES_END_EN_V  0x1
-#define SPI_MEM_PES_END_EN_S  24
-/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
- of flash. 0: Only need to check WIP is 0..*/
-#define SPI_MEM_PER_END_EN    (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (BIT(23))
-#define SPI_MEM_PER_END_EN_V  0x1
-#define SPI_MEM_PER_END_EN_S  23
-/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
-hen check flash SUS/SUS1/SUS2 status bit.*/
-#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
-#define SPI_MEM_FMEM_RD_SUS_2B_S  22
-/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
-/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
-status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
-out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
-2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
-#define SPI_MEM_PESR_END_MSK    0x0000FFFF
-#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
-#define SPI_MEM_PESR_END_MSK_V  0xFFFF
-#define SPI_MEM_PESR_END_MSK_S  6
-/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable Auto-suspending function..*/
-#define SPI_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_V  0x1
-#define SPI_MEM_FLASH_PES_EN_S  5
-/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
-pplication should send PER after PES is done..*/
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (BIT(4))
-#define SPI_MEM_PES_PER_EN_V  0x1
-#define SPI_MEM_PES_PER_EN_S  4
-/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-program erase suspend command is sent. 0: SPI1 does not wait after program erase
- suspend command is sent..*/
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-program erase resume command is sent. 0: SPI1 does not wait after program erase
-resume command is sent..*/
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program erase suspend bit, program erase suspend operation will be triggered whe
-n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
-isable..*/
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (BIT(1))
-#define SPI_MEM_FLASH_PES_V  0x1
-#define SPI_MEM_FLASH_PES_S  1
-/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: program erase resume bit, program erase suspend operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: di
-sable..*/
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (BIT(0))
-#define SPI_MEM_FLASH_PER_V  0x1
-#define SPI_MEM_FLASH_PER_S  0
-
-#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
-/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
-/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
-/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
-..*/
-#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
-/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:8] ;default: 8'h75 ; */
-/*description: Program/Erase suspend command..*/
-#define SPI_MEM_FLASH_PES_COMMAND    0x000000FF
-#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
-#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
-#define SPI_MEM_FLASH_PES_COMMAND_S  8
-/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[7:0] ;default: 8'h7a ; */
-/*description: Program/Erase resume command..*/
-#define SPI_MEM_FLASH_PER_COMMAND    0x000000FF
-#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
-#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
-#define SPI_MEM_FLASH_PER_COMMAND_S  0
-
-#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
-/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
-#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_V  0x1
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
-#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
-#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
-mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
-after DP command is sent..*/
-#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after RES command is sent..*/
-#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after HPM command is sent..*/
-#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
-#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The status of flash suspend, only used in SPI1..*/
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (BIT(0))
-#define SPI_MEM_FLASH_SUS_V  0x1
-#define SPI_MEM_FLASH_SUS_S  0
-
-#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA8)
-/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_TIMING_CALI_V  0x1
-#define SPI_MEM_TIMING_CALI_S  1
-/* SPI_MEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable timing adjust clock for all reading operations..*/
-#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xAC)
-/* SPI_MEM_DIN3_MODE : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN3_MODE    0x00000003
-#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
-#define SPI_MEM_DIN3_MODE_V  0x3
-#define SPI_MEM_DIN3_MODE_S  6
-/* SPI_MEM_DIN2_MODE : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN2_MODE    0x00000003
-#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
-#define SPI_MEM_DIN2_MODE_V  0x3
-#define SPI_MEM_DIN2_MODE_S  4
-/* SPI_MEM_DIN1_MODE : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN1_MODE    0x00000003
-#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
-#define SPI_MEM_DIN1_MODE_V  0x3
-#define SPI_MEM_DIN1_MODE_S  2
-/* SPI_MEM_DIN0_MODE : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN0_MODE    0x00000003
-#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
-#define SPI_MEM_DIN0_MODE_V  0x3
-#define SPI_MEM_DIN0_MODE_S  0
-
-#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB0)
-/* SPI_MEM_DIN3_NUM : HRO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN3_NUM    (BIT(3))
-#define SPI_MEM_DIN3_NUM_M  (BIT(3))
-#define SPI_MEM_DIN3_NUM_V  0x1
-#define SPI_MEM_DIN3_NUM_S  3
-/* SPI_MEM_DIN2_NUM : HRO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN2_NUM    (BIT(2))
-#define SPI_MEM_DIN2_NUM_M  (BIT(2))
-#define SPI_MEM_DIN2_NUM_V  0x1
-#define SPI_MEM_DIN2_NUM_S  2
-/* SPI_MEM_DIN1_NUM : HRO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN1_NUM    (BIT(1))
-#define SPI_MEM_DIN1_NUM_M  (BIT(1))
-#define SPI_MEM_DIN1_NUM_V  0x1
-#define SPI_MEM_DIN1_NUM_S  1
-/* SPI_MEM_DIN0_NUM : HRO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN0_NUM    (BIT(0))
-#define SPI_MEM_DIN0_NUM_M  (BIT(0))
-#define SPI_MEM_DIN0_NUM_V  0x1
-#define SPI_MEM_DIN0_NUM_S  0
-
-#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB4)
-/* SPI_MEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_DOUT3_MODE_S  3
-/* SPI_MEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_DOUT2_MODE_S  2
-/* SPI_MEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_DOUT1_MODE_S  1
-/* SPI_MEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
-/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(5))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(5))
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  5
-/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_V  0x1
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_V  0x1
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_V  0x1
-#define SPI_MEM_PER_END_INT_ENA_S  0
-
-#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
-/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(5))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(5))
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  5
-/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_V  0x1
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_V  0x1
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_V  0x1
-#define SPI_MEM_PER_END_INT_CLR_S  0
-
-#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
-/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-chip is loosing power and RTC module sends out brown out close flash request to
-SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
- and MSPI returns to idle state. 0: Others..*/
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(5))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(5))
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  5
-/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
-is changed from non idle state to idle state. 0: Others..*/
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
-is changed from non idle state to idle state. It means that SPI_CS raises high.
-0: Others.*/
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
-E is sent and flash is already idle. 0: Others..*/
-#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_V  0x1
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
-mand (0x75) is sent and flash is suspended. 0: Others..*/
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_V  0x1
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
-mand (0x7A) is sent and flash is resumed. 0: Others..*/
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_V  0x1
-#define SPI_MEM_PER_END_INT_RAW_S  0
-
-#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
-/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(5))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(5))
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ST_S  5
-/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_V  0x1
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_V  0x1
-#define SPI_MEM_PES_END_INT_ST_S  1
-/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_V  0x1
-#define SPI_MEM_PER_END_INT_ST_S  0
-
-#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xDC)
-/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
-#define SPI_MEM_CLK_EN    (BIT(0))
-#define SPI_MEM_CLK_EN_M  (BIT(0))
-#define SPI_MEM_CLK_EN_V  0x1
-#define SPI_MEM_CLK_EN_S  0
-
-#define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE0)
-/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: When the digital system clock selects PLL clock and the frequency of PLL clock i
-s 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz
-. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz.
-3: Not used. When the digital system clock selects PLL clock and the frequency o
-f PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (
-clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (c
-lk) 160MHz. 3: Not used..*/
-#define SPI_MEM_SPI01_CLK_SEL    0x00000003
-#define SPI_MEM_SPI01_CLK_SEL_M  ((SPI_MEM_SPI01_CLK_SEL_V)<<(SPI_MEM_SPI01_CLK_SEL_S))
-#define SPI_MEM_SPI01_CLK_SEL_V  0x3
-#define SPI_MEM_SPI01_CLK_SEL_S  0
-
-#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
-/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106191 ; */
-/*description: SPI register version..*/
-#define SPI_MEM_DATE    0x0FFFFFFF
-#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
-#define SPI_MEM_DATE_V  0xFFFFFFF
-#define SPI_MEM_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32c2/include/soc/spi_mem_struct.h b/components/soc/esp32c2/include/soc/spi_mem_struct.h
deleted file mode 100644
index c2cc1c5010a..00000000000
--- a/components/soc/esp32c2/include/soc/spi_mem_struct.h
+++ /dev/null
@@ -1,574 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct spi_mem_dev_s{
-    union {
-        struct {
-            uint32_t mst_st                        :    4;  /*The current status of SPI1 master FSM.*/
-            uint32_t slv_st                        :    4;  /*The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
-            uint32_t reserved8                     :    9;  /*reserved*/
-            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
-            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    3;  /*reserved*/
-            uint32_t fdummy_out                    :    1;  /*In the dummy phase the signal level of spi is output by the spi controller.*/
-            uint32_t reserved4                     :    3;  /*reserved*/
-            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable*/
-            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
-            uint32_t reserved9                     :    1;  /*reserved*/
-            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
-            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
-            uint32_t reserved12                    :    1;  /*reserved*/
-            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
-            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
-            uint32_t reserved16                    :    2;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
-            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
-            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
-            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
-            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
-            uint32_t reserved2                     :    18;  /*reserved*/
-            uint32_t rxfifo_rst                    :    1;  /*SPI0 RX FIFO reset signal.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } ctrl1;
-    union {
-        struct {
-            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
-            uint32_t cs_hold_time                  :    5;  /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
-            uint32_t reserved10                    :    15;  /*reserved*/
-            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t sync_reset                    :    1;  /*The FSM will be reset.*/
-        };
-        uint32_t val;
-    } ctrl2;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
-            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
-            uint32_t clk_equ_sysclk                :    1;  /*Set this bit in 1-division mode.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
-            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
-            uint32_t reserved8                     :    1;  /*reserved*/
-            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
-            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
-            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
-            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
-            uint32_t reserved16                    :    8;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
-            uint32_t reserved6                     :    20;  /*reserved*/
-            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of  command.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } mosi_dlen;
-    union {
-        struct {
-            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } miso_dlen;
-    union {
-        struct {
-            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
-            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t reserved24                    :    8;  /*reserved*/
-        };
-        uint32_t val;
-    } rd_status;
-    uint32_t reserved_30;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t reserved0                     :    1;  /*reserved*/
-            uint32_t mst_st_trans_end              :    1;  /*The bit is used to indicate the  spi0_mst_st controlled transmitting is done.*/
-            uint32_t mst_st_trans_end_en           :    1;  /*The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.*/
-            uint32_t slv_st_trans_end              :    1;  /*The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
-            uint32_t slv_st_trans_end_en           :    1;  /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
-            uint32_t reserved7                     :    2;  /*reserved*/
-            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle */
-            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } misc;
-    uint32_t tx_crc;
-    union {
-        struct {
-            uint32_t req_en                        :    1;  /*For SPI0, Cache access enable, 1: enable, 0:disable.*/
-            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
-            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
-            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } cache_fctrl;
-    uint32_t reserved_40;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    union {
-        struct {
-            uint32_t spi0_slv_st                   :    4;  /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
-            uint32_t spi0_mst_st                   :    3;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
-            uint32_t cspi_lock_delay_time          :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } fsm;
-    uint32_t data_buf[16];
-    union {
-        struct {
-            uint32_t reserved0                     :    1;  /*reserved*/
-            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
-            uint32_t waiti_cmd                     :    8;  /*The command to wait flash idle(RDSR).*/
-            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } flash_waiti_ctrl;
-    union {
-        struct {
-            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
-            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
-            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
-            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
-            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
-            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
-            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
-        };
-        uint32_t val;
-    } flash_sus_ctrl;
-    union {
-        struct {
-            uint32_t flash_per_command             :    8;  /*Program/Erase resume command.*/
-            uint32_t flash_pes_command             :    8;  /*Program/Erase suspend command.*/
-            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
-        };
-        uint32_t val;
-    } flash_sus_cmd;
-    union {
-        struct {
-            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
-            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
-            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
-            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
-            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
-            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
-            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
-            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
-            uint32_t reserved8                     :    24;  /*reserved*/
-        };
-        uint32_t val;
-    } sus_status;
-    union {
-        struct {
-            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } timing_cali;
-    union {
-        struct {
-            uint32_t din0_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din1_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din2_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din3_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved8                     :    24;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din1_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din2_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din3_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    union {
-        struct {
-            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
-            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
-            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
-            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
-            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
-            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    union {
-        struct {
-            uint32_t spi01_clk_sel                 :    2;  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. */
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } core_clk_sel;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*SPI register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_mem_dev_t;
-extern spi_mem_dev_t SPIMEM0;
-extern spi_mem_dev_t SPIMEM1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c2/include/soc/spi_reg.h b/components/soc/esp32c2/include/soc/spi_reg.h
deleted file mode 100644
index eaa92535e1e..00000000000
--- a/components/soc/esp32c2/include/soc/spi_reg.h
+++ /dev/null
@@ -1,1749 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SPI_REG_H_
-#define _SOC_SPI_REG_H_
-
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
-/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: User define command enable.  An operation will be triggered when the bit is set.
- The bit will be cleared once the operation done.1: enable 0: disable. Can not b
-e changed by CONF_buf..*/
-#define SPI_USR    (BIT(24))
-#define SPI_USR_M  (BIT(24))
-#define SPI_USR_V  0x1
-#define SPI_USR_S  24
-/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
-clock domain, which is only used in SPI master mode..*/
-#define SPI_UPDATE    (BIT(23))
-#define SPI_UPDATE_M  (BIT(23))
-#define SPI_UPDATE_V  0x1
-#define SPI_UPDATE_S  23
-/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: Define the APB cycles of  SPI_CONF state. Can be configured in CONF state..*/
-#define SPI_CONF_BITLEN    0x0003FFFF
-#define SPI_CONF_BITLEN_M  ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
-#define SPI_CONF_BITLEN_V  0x3FFFF
-#define SPI_CONF_BITLEN_S  0
-
-#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
-/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Address to slave. Can be configured in CONF state..*/
-#define SPI_USR_ADDR_VALUE    0xFFFFFFFF
-#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
-#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_USR_ADDR_VALUE_S  0
-
-#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
-/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */
-/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
-figured in CONF state..*/
-#define SPI_WR_BIT_ORDER    0x00000003
-#define SPI_WR_BIT_ORDER_M  ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
-#define SPI_WR_BIT_ORDER_V  0x3
-#define SPI_WR_BIT_ORDER_S  25
-/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
-/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
-tate..*/
-#define SPI_RD_BIT_ORDER    0x00000003
-#define SPI_RD_BIT_ORDER_M  ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
-#define SPI_RD_BIT_ORDER_V  0x3
-#define SPI_RD_BIT_ORDER_S  23
-/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
-an be configured in CONF state..*/
-#define SPI_WP_POL    (BIT(21))
-#define SPI_WP_POL_M  (BIT(21))
-#define SPI_WP_POL_V  0x1
-#define SPI_WP_POL_S  21
-/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co
-nfigured in CONF state..*/
-#define SPI_HOLD_POL    (BIT(20))
-#define SPI_HOLD_POL_M  (BIT(20))
-#define SPI_HOLD_POL_V  0x1
-#define SPI_HOLD_POL_S  20
-/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-CONF state..*/
-#define SPI_D_POL    (BIT(19))
-#define SPI_D_POL_M  (BIT(19))
-#define SPI_D_POL_V  0x1
-#define SPI_D_POL_S  19
-/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-CONF state..*/
-#define SPI_Q_POL    (BIT(18))
-#define SPI_Q_POL_M  (BIT(18))
-#define SPI_Q_POL_V  0x1
-#define SPI_Q_POL_S  18
-/* SPI_FREAD_OCT : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  C
-an be configured in CONF state..*/
-#define SPI_FREAD_OCT    (BIT(16))
-#define SPI_FREAD_OCT_M  (BIT(16))
-#define SPI_FREAD_OCT_V  0x1
-#define SPI_FREAD_OCT_S  16
-/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  C
-an be configured in CONF state..*/
-#define SPI_FREAD_QUAD    (BIT(15))
-#define SPI_FREAD_QUAD_M  (BIT(15))
-#define SPI_FREAD_QUAD_V  0x1
-#define SPI_FREAD_QUAD_S  15
-/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C
-an be configured in CONF state..*/
-#define SPI_FREAD_DUAL    (BIT(14))
-#define SPI_FREAD_DUAL_M  (BIT(14))
-#define SPI_FREAD_DUAL_V  0x1
-#define SPI_FREAD_DUAL_S  14
-/* SPI_FCMD_OCT : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Apply 8 signals during command phase 1:enable 0: disable. Can be configured in C
-ONF state..*/
-#define SPI_FCMD_OCT    (BIT(10))
-#define SPI_FCMD_OCT_M  (BIT(10))
-#define SPI_FCMD_OCT_V  0x1
-#define SPI_FCMD_OCT_S  10
-/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
-ONF state..*/
-#define SPI_FCMD_QUAD    (BIT(9))
-#define SPI_FCMD_QUAD_M  (BIT(9))
-#define SPI_FCMD_QUAD_V  0x1
-#define SPI_FCMD_QUAD_S  9
-/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C
-ONF state..*/
-#define SPI_FCMD_DUAL    (BIT(8))
-#define SPI_FCMD_DUAL_M  (BIT(8))
-#define SPI_FCMD_DUAL_V  0x1
-#define SPI_FCMD_DUAL_S  8
-/* SPI_FADDR_OCT : HRO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- state..*/
-#define SPI_FADDR_OCT    (BIT(7))
-#define SPI_FADDR_OCT_M  (BIT(7))
-#define SPI_FADDR_OCT_V  0x1
-#define SPI_FADDR_OCT_S  7
-/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- state..*/
-#define SPI_FADDR_QUAD    (BIT(6))
-#define SPI_FADDR_QUAD_M  (BIT(6))
-#define SPI_FADDR_QUAD_V  0x1
-#define SPI_FADDR_QUAD_S  6
-/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- state..*/
-#define SPI_FADDR_DUAL    (BIT(5))
-#define SPI_FADDR_DUAL_M  (BIT(5))
-#define SPI_FADDR_DUAL_V  0x1
-#define SPI_FADDR_DUAL_S  5
-/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phas
-e, the FSPI bus signals are output. Can be configured in CONF state..*/
-#define SPI_DUMMY_OUT    (BIT(3))
-#define SPI_DUMMY_OUT_M  (BIT(3))
-#define SPI_DUMMY_OUT_V  0x1
-#define SPI_DUMMY_OUT_S  3
-
-#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0xC)
-/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst
-em clock. Can be configured in CONF state..*/
-#define SPI_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_V  0x1
-#define SPI_CLK_EQU_SYSCLK_S  31
-/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
-/*description: In the master mode it is pre-divider of spi_clk.  Can be configured in CONF stat
-e..*/
-#define SPI_CLKDIV_PRE    0x0000000F
-#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
-#define SPI_CLKDIV_PRE_V  0xF
-#define SPI_CLKDIV_PRE_S  18
-/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
-/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/
-(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
-#define SPI_CLKCNT_N    0x0000003F
-#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
-#define SPI_CLKCNT_N_V  0x3F
-#define SPI_CLKCNT_N_S  12
-/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
-/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-must be 0. Can be configured in CONF state..*/
-#define SPI_CLKCNT_H    0x0000003F
-#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
-#define SPI_CLKCNT_H_V  0x3F
-#define SPI_CLKCNT_H_S  6
-/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
-/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b
-e 0. Can be configured in CONF state..*/
-#define SPI_CLKCNT_L    0x0000003F
-#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
-#define SPI_CLKCNT_L_V  0x3F
-#define SPI_CLKCNT_L_S  0
-
-#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x10)
-/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation. Can be configured in CONF sta
-te..*/
-#define SPI_USR_COMMAND    (BIT(31))
-#define SPI_USR_COMMAND_M  (BIT(31))
-#define SPI_USR_COMMAND_V  0x1
-#define SPI_USR_COMMAND_S  31
-/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation. Can be configured in CONF sta
-te..*/
-#define SPI_USR_ADDR    (BIT(30))
-#define SPI_USR_ADDR_M  (BIT(30))
-#define SPI_USR_ADDR_V  0x1
-#define SPI_USR_ADDR_S  30
-/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
-..*/
-#define SPI_USR_DUMMY    (BIT(29))
-#define SPI_USR_DUMMY_M  (BIT(29))
-#define SPI_USR_DUMMY_V  0x1
-#define SPI_USR_DUMMY_S  29
-/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s
-tate..*/
-#define SPI_USR_MISO    (BIT(28))
-#define SPI_USR_MISO_M  (BIT(28))
-#define SPI_USR_MISO_V  0x1
-#define SPI_USR_MISO_S  28
-/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation. Can be configured in CONF
-state..*/
-#define SPI_USR_MOSI    (BIT(27))
-#define SPI_USR_MOSI_M  (BIT(27))
-#define SPI_USR_MOSI_V  0x1
-#define SPI_USR_MOSI_S  27
-/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
- CONF state..*/
-#define SPI_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_USR_DUMMY_IDLE_V  0x1
-#define SPI_USR_DUMMY_IDLE_S  26
-/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl
-e 0: disable.  Can be configured in CONF state..*/
-#define SPI_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_V  0x1
-#define SPI_USR_MOSI_HIGHPART_S  25
-/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
- 0: disable. Can be configured in CONF state..*/
-#define SPI_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_USR_MISO_HIGHPART_V  0x1
-#define SPI_USR_MISO_HIGHPART_S  24
-/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha
-re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/
-#define SPI_SIO    (BIT(17))
-#define SPI_SIO_M  (BIT(17))
-#define SPI_SIO_V  0x1
-#define SPI_SIO_S  17
-/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-will continue. 0: The seg-trans will end after the current SPI seg-trans or this
- is not seg-trans mode. Can be configured in CONF state..*/
-#define SPI_USR_CONF_NXT    (BIT(15))
-#define SPI_USR_CONF_NXT_M  (BIT(15))
-#define SPI_USR_CONF_NXT_V  0x1
-#define SPI_USR_CONF_NXT_S  15
-/* SPI_FWRITE_OCT : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 8 signals. Can be configured in CO
-NF state..*/
-#define SPI_FWRITE_OCT    (BIT(14))
-#define SPI_FWRITE_OCT_M  (BIT(14))
-#define SPI_FWRITE_OCT_V  0x1
-#define SPI_FWRITE_OCT_S  14
-/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO
-NF state..*/
-#define SPI_FWRITE_QUAD    (BIT(13))
-#define SPI_FWRITE_QUAD_M  (BIT(13))
-#define SPI_FWRITE_QUAD_V  0x1
-#define SPI_FWRITE_QUAD_S  13
-/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO
-NF state..*/
-#define SPI_FWRITE_DUAL    (BIT(12))
-#define SPI_FWRITE_DUAL_M  (BIT(12))
-#define SPI_FWRITE_DUAL_V  0x1
-#define SPI_FWRITE_DUAL_S  12
-/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca
-n be configured in CONF state..*/
-#define SPI_CK_OUT_EDGE    (BIT(9))
-#define SPI_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_CK_OUT_EDGE_V  0x1
-#define SPI_CK_OUT_EDGE_S  9
-/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
-= !spi_ck_i. 1:rsck = spi_ck_i..*/
-#define SPI_RSCK_I_EDGE    (BIT(8))
-#define SPI_RSCK_I_EDGE_M  (BIT(8))
-#define SPI_RSCK_I_EDGE_V  0x1
-#define SPI_RSCK_I_EDGE_S  8
-/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be co
-nfigured in CONF state..*/
-#define SPI_CS_SETUP    (BIT(7))
-#define SPI_CS_SETUP_M  (BIT(7))
-#define SPI_CS_SETUP_V  0x1
-#define SPI_CS_SETUP_S  7
-/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be config
-ured in CONF state..*/
-#define SPI_CS_HOLD    (BIT(6))
-#define SPI_CS_HOLD_M  (BIT(6))
-#define SPI_CS_HOLD_V  0x1
-#define SPI_CS_HOLD_S  6
-/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
-= spi_ck_i. 1:tsck = !spi_ck_i..*/
-#define SPI_TSCK_I_EDGE    (BIT(5))
-#define SPI_TSCK_I_EDGE_M  (BIT(5))
-#define SPI_TSCK_I_EDGE_V  0x1
-#define SPI_TSCK_I_EDGE_S  5
-/* SPI_OPI_MODE : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others
-. Can be configured in CONF state..*/
-#define SPI_OPI_MODE    (BIT(4))
-#define SPI_OPI_MODE_M  (BIT(4))
-#define SPI_OPI_MODE_V  0x1
-#define SPI_OPI_MODE_S  4
-/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others
-. Can be configured in CONF state..*/
-#define SPI_QPI_MODE    (BIT(3))
-#define SPI_QPI_MODE_M  (BIT(3))
-#define SPI_QPI_MODE_V  0x1
-#define SPI_QPI_MODE_S  3
-/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUTDIN    (BIT(0))
-#define SPI_DOUTDIN_M  (BIT(0))
-#define SPI_DOUTDIN_V  0x1
-#define SPI_DOUTDIN_S  0
-
-#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x14)
-/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca
-n be configured in CONF state..*/
-#define SPI_USR_ADDR_BITLEN    0x0000001F
-#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
-#define SPI_USR_ADDR_BITLEN_V  0x1F
-#define SPI_USR_ADDR_BITLEN_S  27
-/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */
-/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
- Can be configured in CONF state..*/
-#define SPI_CS_HOLD_TIME    0x0000001F
-#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
-#define SPI_CS_HOLD_TIME_V  0x1F
-#define SPI_CS_HOLD_TIME_S  22
-/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
-/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu
-p bit. Can be configured in CONF state..*/
-#define SPI_CS_SETUP_TIME    0x0000001F
-#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
-#define SPI_CS_SETUP_TIME_V  0x1F
-#define SPI_CS_SETUP_TIME_S  17
-/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
- FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
- in GP-SPI master FD/HD-mode..*/
-#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_M  (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_V  0x1
-#define SPI_MST_WFULL_ERR_END_EN_S  16
-/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
-/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_
-num-1). Can be configured in CONF state..*/
-#define SPI_USR_DUMMY_CYCLELEN    0x000000FF
-#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
-#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x18)
-/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca
-n be configured in CONF state..*/
-#define SPI_USR_COMMAND_BITLEN    0x0000000F
-#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
-#define SPI_USR_COMMAND_BITLEN_V  0xF
-#define SPI_USR_COMMAND_BITLEN_S  28
-/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
-/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
-aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro
-r is valid in GP-SPI master FD/HD-mode..*/
-#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_M  (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_V  0x1
-#define SPI_MST_REMPTY_ERR_END_EN_S  27
-/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command. Can be configured in CONF state..*/
-#define SPI_USR_COMMAND_VALUE    0x0000FFFF
-#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
-#define SPI_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_USR_COMMAND_VALUE_S  0
-
-#define SPI_MS_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x1C)
-/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
-/*description: The value of these bits is the configured SPI transmission data bit length in ma
-ster mode DMA controlled transfer or CPU controlled transfer. The value is also
-the configured bit length in slave mode DMA RX controlled transfer. The register
- value shall be (bit_num-1). Can be configured in CONF state..*/
-#define SPI_MS_DATA_BITLEN    0x0003FFFF
-#define SPI_MS_DATA_BITLEN_M  ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
-#define SPI_MS_DATA_BITLEN_V  0x3FFFF
-#define SPI_MS_DATA_BITLEN_S  0
-
-#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
-/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0
-:  spi quad input swap disable. Can be configured in CONF state..*/
-#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
-#define SPI_QUAD_DIN_PIN_SWAP_S  31
-/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/
-#define SPI_CS_KEEP_ACTIVE    (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_V  0x1
-#define SPI_CS_KEEP_ACTIVE_S  30
-/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle. Can be c
-onfigured in CONF state..*/
-#define SPI_CK_IDLE_EDGE    (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (BIT(29))
-#define SPI_CK_IDLE_EDGE_V  0x1
-#define SPI_CK_IDLE_EDGE_S  29
-/* SPI_DQS_IDLE_EDGE : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: The default value of spi_dqs. Can be configured in CONF state..*/
-#define SPI_DQS_IDLE_EDGE    (BIT(24))
-#define SPI_DQS_IDLE_EDGE_M  (BIT(24))
-#define SPI_DQS_IDLE_EDGE_V  0x1
-#define SPI_DQS_IDLE_EDGE_S  24
-/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
-CONF state..*/
-#define SPI_SLAVE_CS_POL    (BIT(23))
-#define SPI_SLAVE_CS_POL_M  (BIT(23))
-#define SPI_SLAVE_CS_POL_V  0x1
-#define SPI_SLAVE_CS_POL_S  23
-/* SPI_CMD_DTR_EN : HRO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/
-4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be confi
-gured in CONF state..*/
-#define SPI_CMD_DTR_EN    (BIT(19))
-#define SPI_CMD_DTR_EN_M  (BIT(19))
-#define SPI_CMD_DTR_EN_V  0x1
-#define SPI_CMD_DTR_EN_S  19
-/* SPI_ADDR_DTR_EN : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2
-/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be co
-nfigured in CONF state..*/
-#define SPI_ADDR_DTR_EN    (BIT(18))
-#define SPI_ADDR_DTR_EN_M  (BIT(18))
-#define SPI_ADDR_DTR_EN_V  0x1
-#define SPI_ADDR_DTR_EN_S  18
-/* SPI_DATA_DTR_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including mas
-ter 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR m
-ode. Can be configured in CONF state..*/
-#define SPI_DATA_DTR_EN    (BIT(17))
-#define SPI_DATA_DTR_EN_M  (BIT(17))
-#define SPI_DATA_DTR_EN_V  0x1
-#define SPI_DATA_DTR_EN_S  17
-/* SPI_CLK_DATA_DTR_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master D
-TR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19..*/
-#define SPI_CLK_DATA_DTR_EN    (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_M  (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_V  0x1
-#define SPI_CLK_DATA_DTR_EN_S  16
-/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
-/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva
-lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/
-#define SPI_MASTER_CS_POL    0x0000003F
-#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
-#define SPI_MASTER_CS_POL_V  0x3F
-#define SPI_MASTER_CS_POL_S  7
-/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: 1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state..*/
-#define SPI_CK_DIS    (BIT(6))
-#define SPI_CK_DIS_M  (BIT(6))
-#define SPI_CK_DIS_V  0x1
-#define SPI_CK_DIS_S  6
-/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS5_DIS    (BIT(5))
-#define SPI_CS5_DIS_M  (BIT(5))
-#define SPI_CS5_DIS_V  0x1
-#define SPI_CS5_DIS_S  5
-/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS4_DIS    (BIT(4))
-#define SPI_CS4_DIS_M  (BIT(4))
-#define SPI_CS4_DIS_V  0x1
-#define SPI_CS4_DIS_S  4
-/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS3_DIS    (BIT(3))
-#define SPI_CS3_DIS_M  (BIT(3))
-#define SPI_CS3_DIS_V  0x1
-#define SPI_CS3_DIS_S  3
-/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS2_DIS    (BIT(2))
-#define SPI_CS2_DIS_M  (BIT(2))
-#define SPI_CS2_DIS_V  0x1
-#define SPI_CS2_DIS_S  2
-/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS1_DIS    (BIT(1))
-#define SPI_CS1_DIS_M  (BIT(1))
-#define SPI_CS1_DIS_V  0x1
-#define SPI_CS1_DIS_S  1
-/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS0_DIS    (BIT(0))
-#define SPI_CS0_DIS_M  (BIT(0))
-#define SPI_CS0_DIS_V  0x1
-#define SPI_CS0_DIS_S  0
-
-#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x24)
-/* SPI_TIMING_HCLK_ACTIVE : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: 1:enable hclk in SPI input timing module.  0: disable it. Can be configured in C
-ONF state..*/
-#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_M  (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_V  0x1
-#define SPI_TIMING_HCLK_ACTIVE_S  16
-/* SPI_DIN7_MODE : HRO ;bitpos:[15:14] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN7_MODE    0x00000003
-#define SPI_DIN7_MODE_M  ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S))
-#define SPI_DIN7_MODE_V  0x3
-#define SPI_DIN7_MODE_S  14
-/* SPI_DIN6_MODE : HRO ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN6_MODE    0x00000003
-#define SPI_DIN6_MODE_M  ((SPI_DIN6_MODE_V)<<(SPI_DIN6_MODE_S))
-#define SPI_DIN6_MODE_V  0x3
-#define SPI_DIN6_MODE_S  12
-/* SPI_DIN5_MODE : HRO ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN5_MODE    0x00000003
-#define SPI_DIN5_MODE_M  ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S))
-#define SPI_DIN5_MODE_V  0x3
-#define SPI_DIN5_MODE_S  10
-/* SPI_DIN4_MODE : HRO ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN4_MODE    0x00000003
-#define SPI_DIN4_MODE_M  ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S))
-#define SPI_DIN4_MODE_V  0x3
-#define SPI_DIN4_MODE_S  8
-/* SPI_DIN3_MODE : HRO ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN3_MODE    0x00000003
-#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
-#define SPI_DIN3_MODE_V  0x3
-#define SPI_DIN3_MODE_S  6
-/* SPI_DIN2_MODE : HRO ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN2_MODE    0x00000003
-#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
-#define SPI_DIN2_MODE_V  0x3
-#define SPI_DIN2_MODE_S  4
-/* SPI_DIN1_MODE : HRO ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN1_MODE    0x00000003
-#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
-#define SPI_DIN1_MODE_V  0x3
-#define SPI_DIN1_MODE_S  2
-/* SPI_DIN0_MODE : HRO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN0_MODE    0x00000003
-#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
-#define SPI_DIN0_MODE_V  0x3
-#define SPI_DIN0_MODE_S  0
-
-#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x28)
-/* SPI_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN7_NUM    0x00000003
-#define SPI_DIN7_NUM_M  ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S))
-#define SPI_DIN7_NUM_V  0x3
-#define SPI_DIN7_NUM_S  14
-/* SPI_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN6_NUM    0x00000003
-#define SPI_DIN6_NUM_M  ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S))
-#define SPI_DIN6_NUM_V  0x3
-#define SPI_DIN6_NUM_S  12
-/* SPI_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN5_NUM    0x00000003
-#define SPI_DIN5_NUM_M  ((SPI_DIN5_NUM_V)<<(SPI_DIN5_NUM_S))
-#define SPI_DIN5_NUM_V  0x3
-#define SPI_DIN5_NUM_S  10
-/* SPI_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN4_NUM    0x00000003
-#define SPI_DIN4_NUM_M  ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S))
-#define SPI_DIN4_NUM_V  0x3
-#define SPI_DIN4_NUM_S  8
-/* SPI_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN3_NUM    0x00000003
-#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
-#define SPI_DIN3_NUM_V  0x3
-#define SPI_DIN3_NUM_S  6
-/* SPI_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN2_NUM    0x00000003
-#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
-#define SPI_DIN2_NUM_V  0x3
-#define SPI_DIN2_NUM_S  4
-/* SPI_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN1_NUM    0x00000003
-#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
-#define SPI_DIN1_NUM_V  0x3
-#define SPI_DIN1_NUM_S  2
-/* SPI_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN0_NUM    0x00000003
-#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
-#define SPI_DIN0_NUM_V  0x3
-#define SPI_DIN0_NUM_S  0
-
-#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x2C)
-/* SPI_D_DQS_MODE : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
-delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-be configured in CONF state..*/
-#define SPI_D_DQS_MODE    (BIT(8))
-#define SPI_D_DQS_MODE_M  (BIT(8))
-#define SPI_D_DQS_MODE_V  0x1
-#define SPI_D_DQS_MODE_S  8
-/* SPI_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT7_MODE    (BIT(7))
-#define SPI_DOUT7_MODE_M  (BIT(7))
-#define SPI_DOUT7_MODE_V  0x1
-#define SPI_DOUT7_MODE_S  7
-/* SPI_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT6_MODE    (BIT(6))
-#define SPI_DOUT6_MODE_M  (BIT(6))
-#define SPI_DOUT6_MODE_V  0x1
-#define SPI_DOUT6_MODE_S  6
-/* SPI_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT5_MODE    (BIT(5))
-#define SPI_DOUT5_MODE_M  (BIT(5))
-#define SPI_DOUT5_MODE_V  0x1
-#define SPI_DOUT5_MODE_S  5
-/* SPI_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT4_MODE    (BIT(4))
-#define SPI_DOUT4_MODE_M  (BIT(4))
-#define SPI_DOUT4_MODE_V  0x1
-#define SPI_DOUT4_MODE_S  4
-/* SPI_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT3_MODE    (BIT(3))
-#define SPI_DOUT3_MODE_M  (BIT(3))
-#define SPI_DOUT3_MODE_V  0x1
-#define SPI_DOUT3_MODE_S  3
-/* SPI_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT2_MODE    (BIT(2))
-#define SPI_DOUT2_MODE_M  (BIT(2))
-#define SPI_DOUT2_MODE_V  0x1
-#define SPI_DOUT2_MODE_S  2
-/* SPI_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT1_MODE    (BIT(1))
-#define SPI_DOUT1_MODE_M  (BIT(1))
-#define SPI_DOUT1_MODE_V  0x1
-#define SPI_DOUT1_MODE_S  1
-/* SPI_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT0_MODE    (BIT(0))
-#define SPI_DOUT0_MODE_M  (BIT(0))
-#define SPI_DOUT0_MODE_V  0x1
-#define SPI_DOUT0_MODE_S  0
-
-#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x30)
-/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
-DMA controlled mode transfer..*/
-#define SPI_DMA_AFIFO_RST    (BIT(31))
-#define SPI_DMA_AFIFO_RST_M  (BIT(31))
-#define SPI_DMA_AFIFO_RST_V  0x1
-#define SPI_DMA_AFIFO_RST_S  31
-/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
- controlled mode transfer and master mode transfer..*/
-#define SPI_BUF_AFIFO_RST    (BIT(30))
-#define SPI_BUF_AFIFO_RST_M  (BIT(30))
-#define SPI_BUF_AFIFO_RST_V  0x1
-#define SPI_BUF_AFIFO_RST_S  30
-/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-slave mode transfer..*/
-#define SPI_RX_AFIFO_RST    (BIT(29))
-#define SPI_RX_AFIFO_RST_M  (BIT(29))
-#define SPI_RX_AFIFO_RST_V  0x1
-#define SPI_RX_AFIFO_RST_S  29
-/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI DMA controlled send data mode..*/
-#define SPI_DMA_TX_ENA    (BIT(28))
-#define SPI_DMA_TX_ENA_M  (BIT(28))
-#define SPI_DMA_TX_ENA_V  0x1
-#define SPI_DMA_TX_ENA_S  28
-/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: Set this bit to enable SPI DMA controlled receive data mode..*/
-#define SPI_DMA_RX_ENA    (BIT(27))
-#define SPI_DMA_RX_ENA_M  (BIT(27))
-#define SPI_DMA_RX_ENA_V  0x1
-#define SPI_DMA_RX_ENA_S  27
-/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
-o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_d
-ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don
-e in seg-trans..*/
-#define SPI_RX_EOF_EN    (BIT(21))
-#define SPI_RX_EOF_EN_M  (BIT(21))
-#define SPI_RX_EOF_EN_V  0x1
-#define SPI_RX_EOF_EN_S  21
-/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
-mpty_vld is cleared by spi_trans_done..*/
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x1
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
-/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full
-_vld is cleared by spi_trans_done..*/
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x1
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
-/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/
-#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
-#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
-/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat
-a. 0: DMA RX FIFO is ready for receiving data..*/
-#define SPI_DMA_INFIFO_FULL    (BIT(1))
-#define SPI_DMA_INFIFO_FULL_M  (BIT(1))
-#define SPI_DMA_INFIFO_FULL_V  0x1
-#define SPI_DMA_INFIFO_FULL_S  1
-/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data.
- 0: DMA TX FIFO is ready for sending data..*/
-#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_M  (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_S  0
-
-#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
-/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_ENA    (BIT(20))
-#define SPI_APP1_INT_ENA_M  (BIT(20))
-#define SPI_APP1_INT_ENA_V  0x1
-#define SPI_APP1_INT_ENA_S  20
-/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_ENA    (BIT(19))
-#define SPI_APP2_INT_ENA_M  (BIT(19))
-#define SPI_APP2_INT_ENA_V  0x1
-#define SPI_APP2_INT_ENA_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
-/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_V  0x1
-#define SPI_SLV_CMD_ERR_INT_ENA_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
-/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
-/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_V  0x1
-#define SPI_TRANS_DONE_INT_ENA_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
-/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_V  0x1
-#define SPI_SLV_CMDA_INT_ENA_S  7
-/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_V  0x1
-#define SPI_SLV_CMD9_INT_ENA_S  6
-/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_V  0x1
-#define SPI_SLV_CMD8_INT_ENA_S  5
-/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_V  0x1
-#define SPI_SLV_CMD7_INT_ENA_S  4
-/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_V  0x1
-#define SPI_SLV_EN_QPI_INT_ENA_S  3
-/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_V  0x1
-#define SPI_SLV_EX_QPI_INT_ENA_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
-
-#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x38)
-/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_CLR    (BIT(20))
-#define SPI_APP1_INT_CLR_M  (BIT(20))
-#define SPI_APP1_INT_CLR_V  0x1
-#define SPI_APP1_INT_CLR_S  20
-/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_CLR    (BIT(19))
-#define SPI_APP2_INT_CLR_M  (BIT(19))
-#define SPI_APP2_INT_CLR_V  0x1
-#define SPI_APP2_INT_CLR_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
-/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_V  0x1
-#define SPI_SLV_CMD_ERR_INT_CLR_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
-/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
-/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_V  0x1
-#define SPI_TRANS_DONE_INT_CLR_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
-/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_V  0x1
-#define SPI_SLV_CMDA_INT_CLR_S  7
-/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_V  0x1
-#define SPI_SLV_CMD9_INT_CLR_S  6
-/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_V  0x1
-#define SPI_SLV_CMD8_INT_CLR_S  5
-/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_V  0x1
-#define SPI_SLV_CMD7_INT_CLR_S  4
-/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_V  0x1
-#define SPI_SLV_EN_QPI_INT_CLR_S  3
-/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_V  0x1
-#define SPI_SLV_EX_QPI_INT_CLR_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
-
-#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x3C)
-/* SPI_APP1_INT_RAW : R/WTC/SS ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software
-..*/
-#define SPI_APP1_INT_RAW    (BIT(20))
-#define SPI_APP1_INT_RAW_M  (BIT(20))
-#define SPI_APP1_INT_RAW_V  0x1
-#define SPI_APP1_INT_RAW_S  20
-/* SPI_APP2_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software
-..*/
-#define SPI_APP2_INT_RAW    (BIT(19))
-#define SPI_APP2_INT_RAW_M  (BIT(19))
-#define SPI_APP2_INT_RAW_V  0x1
-#define SPI_APP2_INT_RAW_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
- write-full error when SPI inputs data in master mode. 0: Others..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
-/* SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
- current SPI slave HD mode transmission is not supported. 0: Others..*/
-#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_V  0x1
-#define SPI_SLV_CMD_ERR_INT_RAW_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres
-s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
- is bigger than 63. 0: Others..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
-/* SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff
-er is error in the DMA seg-conf-trans. 0: others..*/
-#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-du
-plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
-ta has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is
-not ended or not occurred..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
-/* SPI_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
- ended. 0: others..*/
-#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_V  0x1
-#define SPI_TRANS_DONE_INT_RAW_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
-/* SPI_SLV_CMDA_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_V  0x1
-#define SPI_SLV_CMDA_INT_RAW_S  7
-/* SPI_SLV_CMD9_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_V  0x1
-#define SPI_SLV_CMD9_INT_RAW_S  6
-/* SPI_SLV_CMD8_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_V  0x1
-#define SPI_SLV_CMD8_INT_RAW_S  5
-/* SPI_SLV_CMD7_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_V  0x1
-#define SPI_SLV_CMD7_INT_RAW_S  4
-/* SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio
-n is ended. 0: Others..*/
-#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_V  0x1
-#define SPI_SLV_EN_QPI_INT_RAW_S  3
-/* SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio
-n is ended. 0: Others..*/
-#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_V  0x1
-#define SPI_SLV_EX_QPI_INT_RAW_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
- master mode and send out all 0 in slave mode.  0: Others..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
-the receive data.  0: Others..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
-
-#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x40)
-/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The status bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_ST    (BIT(20))
-#define SPI_APP1_INT_ST_M  (BIT(20))
-#define SPI_APP1_INT_ST_V  0x1
-#define SPI_APP1_INT_ST_S  20
-/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The status bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_ST    (BIT(19))
-#define SPI_APP2_INT_ST_M  (BIT(19))
-#define SPI_APP2_INT_ST_V  0x1
-#define SPI_APP2_INT_ST_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
-/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_V  0x1
-#define SPI_SLV_CMD_ERR_INT_ST_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
-/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
-/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_ST    (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_V  0x1
-#define SPI_TRANS_DONE_INT_ST_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
-/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_ST    (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_V  0x1
-#define SPI_SLV_CMDA_INT_ST_S  7
-/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_ST    (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_V  0x1
-#define SPI_SLV_CMD9_INT_ST_S  6
-/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_ST    (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_V  0x1
-#define SPI_SLV_CMD8_INT_ST_S  5
-/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_ST    (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_V  0x1
-#define SPI_SLV_CMD7_INT_ST_S  4
-/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_V  0x1
-#define SPI_SLV_EN_QPI_INT_ST_S  3
-/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_V  0x1
-#define SPI_SLV_EX_QPI_INT_ST_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
-
-#define SPI_DMA_INT_SET_REG(i)          (REG_SPI_BASE(i) + 0x44)
-/* SPI_APP1_INT_SET : WT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_SET    (BIT(20))
-#define SPI_APP1_INT_SET_M  (BIT(20))
-#define SPI_APP1_INT_SET_V  0x1
-#define SPI_APP1_INT_SET_S  20
-/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_SET    (BIT(19))
-#define SPI_APP2_INT_SET_M  (BIT(19))
-#define SPI_APP2_INT_SET_V  0x1
-#define SPI_APP2_INT_SET_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
-/* SPI_SLV_CMD_ERR_INT_SET : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_V  0x1
-#define SPI_SLV_CMD_ERR_INT_SET_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
-/* SPI_SEG_MAGIC_ERR_INT_SET : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_SET : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
-/* SPI_TRANS_DONE_INT_SET : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_SET    (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_V  0x1
-#define SPI_TRANS_DONE_INT_SET_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_SET : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_SET : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_SET : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
-/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_SET    (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_V  0x1
-#define SPI_SLV_CMDA_INT_SET_S  7
-/* SPI_SLV_CMD9_INT_SET : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_SET    (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_V  0x1
-#define SPI_SLV_CMD9_INT_SET_S  6
-/* SPI_SLV_CMD8_INT_SET : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_SET    (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_V  0x1
-#define SPI_SLV_CMD8_INT_SET_S  5
-/* SPI_SLV_CMD7_INT_SET : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_SET    (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_V  0x1
-#define SPI_SLV_CMD7_INT_SET_S  4
-/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_V  0x1
-#define SPI_SLV_EN_QPI_INT_SET_S  3
-/* SPI_SLV_EX_QPI_INT_SET : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_V  0x1
-#define SPI_SLV_EX_QPI_INT_SET_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
-
-#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x98)
-/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF0    0xFFFFFFFF
-#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
-#define SPI_BUF0_V  0xFFFFFFFF
-#define SPI_BUF0_S  0
-
-#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x9C)
-/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF1    0xFFFFFFFF
-#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
-#define SPI_BUF1_V  0xFFFFFFFF
-#define SPI_BUF1_S  0
-
-#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0xA0)
-/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF2    0xFFFFFFFF
-#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
-#define SPI_BUF2_V  0xFFFFFFFF
-#define SPI_BUF2_S  0
-
-#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0xA4)
-/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF3    0xFFFFFFFF
-#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
-#define SPI_BUF3_V  0xFFFFFFFF
-#define SPI_BUF3_S  0
-
-#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0xA8)
-/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF4    0xFFFFFFFF
-#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
-#define SPI_BUF4_V  0xFFFFFFFF
-#define SPI_BUF4_S  0
-
-#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0xAC)
-/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF5    0xFFFFFFFF
-#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
-#define SPI_BUF5_V  0xFFFFFFFF
-#define SPI_BUF5_S  0
-
-#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0xB0)
-/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF6    0xFFFFFFFF
-#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
-#define SPI_BUF6_V  0xFFFFFFFF
-#define SPI_BUF6_S  0
-
-#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0xB4)
-/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF7    0xFFFFFFFF
-#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
-#define SPI_BUF7_V  0xFFFFFFFF
-#define SPI_BUF7_S  0
-
-#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xB8)
-/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF8    0xFFFFFFFF
-#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
-#define SPI_BUF8_V  0xFFFFFFFF
-#define SPI_BUF8_S  0
-
-#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xBC)
-/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF9    0xFFFFFFFF
-#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
-#define SPI_BUF9_V  0xFFFFFFFF
-#define SPI_BUF9_S  0
-
-#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xC0)
-/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF10    0xFFFFFFFF
-#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
-#define SPI_BUF10_V  0xFFFFFFFF
-#define SPI_BUF10_S  0
-
-#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xC4)
-/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF11    0xFFFFFFFF
-#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
-#define SPI_BUF11_V  0xFFFFFFFF
-#define SPI_BUF11_S  0
-
-#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xC8)
-/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF12    0xFFFFFFFF
-#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
-#define SPI_BUF12_V  0xFFFFFFFF
-#define SPI_BUF12_S  0
-
-#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xCC)
-/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF13    0xFFFFFFFF
-#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
-#define SPI_BUF13_V  0xFFFFFFFF
-#define SPI_BUF13_S  0
-
-#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xD0)
-/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF14    0xFFFFFFFF
-#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
-#define SPI_BUF14_V  0xFFFFFFFF
-#define SPI_BUF14_S  0
-
-#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xD4)
-/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF15    0xFFFFFFFF
-#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
-#define SPI_BUF15_V  0xFFFFFFFF
-#define SPI_BUF15_S  0
-
-#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0xE0)
-/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
-ns will start. 0: This is not seg-trans mode..*/
-#define SPI_USR_CONF    (BIT(28))
-#define SPI_USR_CONF_M  (BIT(28))
-#define SPI_USR_CONF_V  0x1
-#define SPI_USR_CONF_S  28
-/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
-onfigured in CONF state..*/
-#define SPI_SOFT_RESET    (BIT(27))
-#define SPI_SOFT_RESET_M  (BIT(27))
-#define SPI_SOFT_RESET_V  0x1
-#define SPI_SOFT_RESET_S  27
-/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
-#define SPI_SLAVE_MODE    (BIT(26))
-#define SPI_SLAVE_MODE_M  (BIT(26))
-#define SPI_SLAVE_MODE_V  0x1
-#define SPI_SLAVE_MODE_S  26
-/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
-/*description: The magic value of BM table in master DMA seg-trans..*/
-#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000F
-#define SPI_DMA_SEG_MAGIC_VALUE_M  ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
-#define SPI_DMA_SEG_MAGIC_VALUE_V  0xF
-#define SPI_DMA_SEG_MAGIC_VALUE_S  22
-/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
-th in CPU controlled mode(Wr_BUF). 0: others.*/
-#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_M  (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_V  0x1
-#define SPI_SLV_WRBUF_BITLEN_EN_S  11
-/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
-n CPU controlled mode(Rd_BUF). 0: others.*/
-#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_M  (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_V  0x1
-#define SPI_SLV_RDBUF_BITLEN_EN_S  10
-/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
-th in DMA controlled mode(Wr_DMA). 0: others.*/
-#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_M  (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_V  0x1
-#define SPI_SLV_WRDMA_BITLEN_EN_S  9
-/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
-n DMA controlled mode(Rd_DMA). 0: others.*/
-#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_M  (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_V  0x1
-#define SPI_SLV_RDDMA_BITLEN_EN_S  8
-/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
-dge   0: output data at tsck posedge.*/
-#define SPI_RSCK_DATA_OUT    (BIT(3))
-#define SPI_RSCK_DATA_OUT_M  (BIT(3))
-#define SPI_RSCK_DATA_OUT_V  0x1
-#define SPI_RSCK_DATA_OUT_S  3
-/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
- 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
-#define SPI_CLK_MODE_13    (BIT(2))
-#define SPI_CLK_MODE_13_M  (BIT(2))
-#define SPI_CLK_MODE_13_V  0x1
-#define SPI_CLK_MODE_13_S  2
-/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/
-#define SPI_CLK_MODE    0x00000003
-#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
-#define SPI_CLK_MODE_V  0x3
-#define SPI_CLK_MODE_S  0
-
-#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0xE4)
-/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
-/*description: In the slave mode it is the value of address..*/
-#define SPI_SLV_LAST_ADDR    0x0000003F
-#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
-#define SPI_SLV_LAST_ADDR_V  0x3F
-#define SPI_SLV_LAST_ADDR_S  26
-/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
-/*description: In the slave mode it is the value of command..*/
-#define SPI_SLV_LAST_COMMAND    0x000000FF
-#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
-#define SPI_SLV_LAST_COMMAND_V  0xFF
-#define SPI_SLV_LAST_COMMAND_S  18
-/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: The transferred data bit length in SPI slave FD and HD mode..*/
-#define SPI_SLV_DATA_BITLEN    0x0003FFFF
-#define SPI_SLV_DATA_BITLEN_M  ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
-#define SPI_SLV_DATA_BITLEN_V  0x3FFFF
-#define SPI_SLV_DATA_BITLEN_S  0
-
-#define SPI_CLK_GATE_REG(i)          (REG_SPI_BASE(i) + 0xE8)
-/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
-M. 0: XTAL CLK..*/
-#define SPI_MST_CLK_SEL    (BIT(2))
-#define SPI_MST_CLK_SEL_M  (BIT(2))
-#define SPI_MST_CLK_SEL_V  0x1
-#define SPI_MST_CLK_SEL_S  2
-/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to power on the SPI module clock..*/
-#define SPI_MST_CLK_ACTIVE    (BIT(1))
-#define SPI_MST_CLK_ACTIVE_M  (BIT(1))
-#define SPI_MST_CLK_ACTIVE_V  0x1
-#define SPI_MST_CLK_ACTIVE_S  1
-/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable clk gate.*/
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (BIT(0))
-#define SPI_CLK_EN_V  0x1
-#define SPI_CLK_EN_S  0
-
-#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
-/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106070 ; */
-/*description: SPI register version..*/
-#define SPI_DATE    0x0FFFFFFF
-#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
-#define SPI_DATE_V  0xFFFFFFF
-#define SPI_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_REG_H_ */
diff --git a/components/soc/esp32c2/include/soc/spi_struct.h b/components/soc/esp32c2/include/soc/spi_struct.h
deleted file mode 100644
index da359da8450..00000000000
--- a/components/soc/esp32c2/include/soc/spi_struct.h
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SPI_STRUCT_H_
-#define _SOC_SPI_STRUCT_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-typedef volatile struct spi_dev_s{
-    union {
-        struct {
-            uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
-            uint32_t reserved18                    :    5;  /*reserved*/
-            uint32_t update                        :    1;  /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
-            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    3;  /*reserved*/
-            uint32_t dummy_out                     :    1;  /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
-            uint32_t reserved4                     :    1;  /*reserved*/
-            uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved11                    :    3;  /*reserved*/
-            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
-            uint32_t fread_oct                     :    1;  /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
-            uint32_t reserved17                    :    1;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
-            uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
-            uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
-            uint32_t reserved22                    :    1;  /*reserved*/
-            uint32_t rd_bit_order                  :    2;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
-            uint32_t wr_bit_order                  :    2;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    6;  /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
-            uint32_t clkcnt_h                      :    6;  /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
-            uint32_t clkcnt_n                      :    6;  /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
-            uint32_t clkdiv_pre                    :    4;  /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
-            uint32_t reserved22                    :    9;  /*reserved*/
-            uint32_t clk_equ_sysclk                :    1;  /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t doutdin                       :    1;  /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved1                     :    2;  /*reserved*/
-            uint32_t qpi_mode                      :    1;  /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
-            uint32_t opi_mode                      :    1;  /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
-            uint32_t tsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
-            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t rsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
-            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
-            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
-            uint32_t fwrite_oct                    :    1;  /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
-            uint32_t usr_conf_nxt                  :    1;  /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
-            uint32_t reserved16                    :    1;  /*reserved*/
-            uint32_t sio                           :    1;  /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved18                    :    6;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.*/
-            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    8;  /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
-            uint32_t reserved8                     :    8;  /*reserved*/
-            uint32_t mst_wfull_err_end_en          :    1;  /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
-            uint32_t cs_setup_time                 :    5;  /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
-            uint32_t cs_hold_time                  :    5;  /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
-            uint32_t usr_addr_bitlen               :    5;  /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of  command. Can be configured in CONF state.*/
-            uint32_t reserved16                    :    11;  /*reserved*/
-            uint32_t mst_rempty_err_end_en         :    1;  /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t ms_data_bitlen                :    18;  /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } ms_dlen;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs1_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs2_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs3_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs4_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs5_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t ck_dis                        :    1;  /*1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.*/
-            uint32_t master_cs_pol                 :    6;  /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
-            uint32_t reserved13                    :    3;  /*reserved*/
-            uint32_t clk_data_dtr_en               :    1;  /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19. */
-            uint32_t data_dtr_en                   :    1;  /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
-            uint32_t addr_dtr_en                   :    1;  /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
-            uint32_t cmd_dtr_en                    :    1;  /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
-            uint32_t reserved20                    :    3;  /*reserved*/
-            uint32_t slave_cs_pol                  :    1;  /*spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.*/
-            uint32_t dqs_idle_edge                 :    1;  /*The default value of spi_dqs. Can be configured in CONF state.*/
-            uint32_t reserved25                    :    4;  /*reserved*/
-            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
-            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
-            uint32_t quad_din_pin_swap             :    1;  /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } misc;
-    union {
-        struct {
-            uint32_t din0_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din1_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din2_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din3_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din4_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din5_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din6_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din7_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t timing_hclk_active            :    1;  /*1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.*/
-            uint32_t reserved17                    :    15;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din1_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din2_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din3_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din4_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din5_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din6_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din7_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout1_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout2_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout3_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout4_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout5_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout6_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout7_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t d_dqs_mode                    :    1;  /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    union {
-        struct {
-            uint32_t dma_outfifo_empty             :    1;  /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
-            uint32_t dma_infifo_full               :    1;  /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
-            uint32_t reserved2                     :    16;  /*reserved*/
-            uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
-            uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
-            uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
-            uint32_t rx_eof_en                     :    1;  /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
-            uint32_t reserved22                    :    5;  /*reserved*/
-            uint32_t dma_rx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled receive data mode.*/
-            uint32_t dma_tx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled send data mode.*/
-            uint32_t rx_afifo_rst                  :    1;  /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
-            uint32_t buf_afifo_rst                 :    1;  /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
-            uint32_t dma_afifo_rst                 :    1;  /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
-        };
-        uint32_t val;
-    } dma_conf;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The enable bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The enable bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The enable bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The enable bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The enable bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The enable bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The enable bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The enable bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_ena;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The clear bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The clear bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The clear bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The clear bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The clear bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The clear bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The clear bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The clear bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_clr;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.  */
-            uint32_t outfifo_empty_err             :    1;  /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.  */
-            uint32_t ex_qpi                        :    1;  /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
-            uint32_t en_qpi                        :    1;  /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
-            uint32_t cmd7                          :    1;  /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
-            uint32_t cmd8                          :    1;  /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
-            uint32_t cmd9                          :    1;  /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
-            uint32_t cmda                          :    1;  /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
-            uint32_t rd_dma_done                   :    1;  /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
-            uint32_t wr_dma_done                   :    1;  /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
-            uint32_t rd_buf_done                   :    1;  /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
-            uint32_t wr_buf_done                   :    1;  /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
-            uint32_t trans_done                    :    1;  /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred. */
-            uint32_t seg_magic_err                 :    1;  /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
-            uint32_t buf_addr_err                  :    1;  /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
-            uint32_t cmd_err                       :    1;  /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
-            uint32_t app2                          :    1;  /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
-            uint32_t app1                          :    1;  /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_raw;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The status bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The status bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The status bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The status bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The status bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The status bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The status bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The status bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_st;
-    union {
-        struct {
-            uint32_t infifo_full_err_int_set       :    1;  /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err_int_set     :    1;  /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi_int_set                :    1;  /*The software set bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi_int_set                :    1;  /*The software set bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7_int_set                  :    1;  /*The software set bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8_int_set                  :    1;  /*The software set bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9_int_set                  :    1;  /*The software set bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda_int_set                  :    1;  /*The software set bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done_int_set            :    1;  /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done_int_set    :    1;  /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err_int_set         :    1;  /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err_int_set          :    1;  /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err_int_set               :    1;  /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err_int_set:    1;  /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err_int_set:    1;  /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2_int_set                  :    1;  /*The software set bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1_int_set                  :    1;  /*The software set bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_set;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t data_buf[16];
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
-            uint32_t clk_mode_13                   :    1;  /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
-            uint32_t rsck_data_out                 :    1;  /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge */
-            uint32_t reserved4                     :    4;  /*reserved*/
-            uint32_t rddma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
-            uint32_t wrdma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
-            uint32_t rdbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
-            uint32_t wrbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
-            uint32_t reserved12                    :    10;  /*reserved*/
-            uint32_t dma_seg_magic_value           :    4;  /*The magic value of BM table in master DMA seg-trans.*/
-            uint32_t slave_mode                    :    1;  /*Set SPI work mode. 1: slave mode 0: master mode.*/
-            uint32_t soft_reset                    :    1;  /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
-            uint32_t usr_conf                      :    1;  /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
-            uint32_t reserved29                    :    3;  /*reserved*/
-        };
-        uint32_t val;
-    } slave;
-    union {
-        struct {
-            uint32_t data_bitlen                   :    18;  /*The transferred data bit length in SPI slave FD and HD mode. */
-            uint32_t last_command                  :    8;  /*In the slave mode it is the value of command.*/
-            uint32_t last_addr                     :    6;  /*In the slave mode it is the value of address.*/
-        };
-        uint32_t val;
-    } slave1;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
-            uint32_t mst_clk_active                :    1;  /*Set this bit to power on the SPI module clock.*/
-            uint32_t mst_clk_sel                   :    1;  /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } clk_gate;
-    uint32_t reserved_ec;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*SPI register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_dev_t;
-extern spi_dev_t GPSPI2;
-extern spi_dev_t GPSPI3;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_STRUCT_H_ */
diff --git a/components/soc/esp32c2/include/soc/syscon_reg.h b/components/soc/esp32c2/include/soc/syscon_reg.h
deleted file mode 100644
index 9c4f8b5e610..00000000000
--- a/components/soc/esp32c2/include/soc/syscon_reg.h
+++ /dev/null
@@ -1,637 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SYSCON_REG_H_
-#define _SOC_SYSCON_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x0)
-/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: reg_rst_tick_cnt.*/
-#define SYSCON_RST_TICK_CNT    (BIT(12))
-#define SYSCON_RST_TICK_CNT_M  (BIT(12))
-#define SYSCON_RST_TICK_CNT_V  0x1
-#define SYSCON_RST_TICK_CNT_S  12
-/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: reg_clk_en.*/
-#define SYSCON_CLK_EN    (BIT(11))
-#define SYSCON_CLK_EN_M  (BIT(11))
-#define SYSCON_CLK_EN_V  0x1
-#define SYSCON_CLK_EN_S  11
-/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: reg_clk_320m_en.*/
-#define SYSCON_CLK_320M_EN    (BIT(10))
-#define SYSCON_CLK_320M_EN_M  (BIT(10))
-#define SYSCON_CLK_320M_EN_V  0x1
-#define SYSCON_CLK_320M_EN_S  10
-/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
-/*description: reg_pre_div_cnt.*/
-#define SYSCON_PRE_DIV_CNT    0x000003FF
-#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
-#define SYSCON_PRE_DIV_CNT_V  0x3FF
-#define SYSCON_PRE_DIV_CNT_S  0
-
-#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x4)
-/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: reg_tick_enable.*/
-#define SYSCON_TICK_ENABLE    (BIT(16))
-#define SYSCON_TICK_ENABLE_M  (BIT(16))
-#define SYSCON_TICK_ENABLE_V  0x1
-#define SYSCON_TICK_ENABLE_S  16
-/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
-/*description: reg_ck8m_tick_num.*/
-#define SYSCON_CK8M_TICK_NUM    0x000000FF
-#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
-#define SYSCON_CK8M_TICK_NUM_V  0xFF
-#define SYSCON_CK8M_TICK_NUM_S  8
-/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
-/*description: reg_xtal_tick_num.*/
-#define SYSCON_XTAL_TICK_NUM    0x000000FF
-#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
-#define SYSCON_XTAL_TICK_NUM_V  0xFF
-#define SYSCON_XTAL_TICK_NUM_S  0
-
-#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x8)
-/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: reg_clk_xtal_oen.*/
-#define SYSCON_CLK_XTAL_OEN    (BIT(10))
-#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
-#define SYSCON_CLK_XTAL_OEN_V  0x1
-#define SYSCON_CLK_XTAL_OEN_S  10
-/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: reg_clk40x_bb_oen.*/
-#define SYSCON_CLK40X_BB_OEN    (BIT(9))
-#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
-#define SYSCON_CLK40X_BB_OEN_V  0x1
-#define SYSCON_CLK40X_BB_OEN_S  9
-/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: reg_clk_dac_cpu_oen.*/
-#define SYSCON_CLK_DAC_CPU_OEN    (BIT(8))
-#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
-#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
-#define SYSCON_CLK_DAC_CPU_OEN_S  8
-/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: reg_clk_adc_inf_oen.*/
-#define SYSCON_CLK_ADC_INF_OEN    (BIT(7))
-#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
-#define SYSCON_CLK_ADC_INF_OEN_V  0x1
-#define SYSCON_CLK_ADC_INF_OEN_S  7
-/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: reg_clk_320m_oen.*/
-#define SYSCON_CLK_320M_OEN    (BIT(6))
-#define SYSCON_CLK_320M_OEN_M  (BIT(6))
-#define SYSCON_CLK_320M_OEN_V  0x1
-#define SYSCON_CLK_320M_OEN_S  6
-/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: reg_clk160_oen.*/
-#define SYSCON_CLK160_OEN    (BIT(5))
-#define SYSCON_CLK160_OEN_M  (BIT(5))
-#define SYSCON_CLK160_OEN_V  0x1
-#define SYSCON_CLK160_OEN_S  5
-/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: reg_clk80_oen.*/
-#define SYSCON_CLK80_OEN    (BIT(4))
-#define SYSCON_CLK80_OEN_M  (BIT(4))
-#define SYSCON_CLK80_OEN_V  0x1
-#define SYSCON_CLK80_OEN_S  4
-/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: reg_clk_bb_oen.*/
-#define SYSCON_CLK_BB_OEN    (BIT(3))
-#define SYSCON_CLK_BB_OEN_M  (BIT(3))
-#define SYSCON_CLK_BB_OEN_V  0x1
-#define SYSCON_CLK_BB_OEN_S  3
-/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: reg_clk44_oen.*/
-#define SYSCON_CLK44_OEN    (BIT(2))
-#define SYSCON_CLK44_OEN_M  (BIT(2))
-#define SYSCON_CLK44_OEN_V  0x1
-#define SYSCON_CLK44_OEN_S  2
-/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: reg_clk22_oen.*/
-#define SYSCON_CLK22_OEN    (BIT(1))
-#define SYSCON_CLK22_OEN_M  (BIT(1))
-#define SYSCON_CLK22_OEN_V  0x1
-#define SYSCON_CLK22_OEN_S  1
-/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: reg_clk20_oen.*/
-#define SYSCON_CLK20_OEN    (BIT(0))
-#define SYSCON_CLK20_OEN_M  (BIT(0))
-#define SYSCON_CLK20_OEN_V  0x1
-#define SYSCON_CLK20_OEN_S  0
-
-#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0xC)
-/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: reg_wifi_bb_cfg.*/
-#define SYSCON_WIFI_BB_CFG    0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
-#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_S  0
-
-#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x10)
-/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: reg_wifi_bb_cfg_2.*/
-#define SYSCON_WIFI_BB_CFG_2    0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
-#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_2_S  0
-
-#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x14)
-/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: reg_wifi_clk_en.*/
-#define SYSCON_WIFI_CLK_EN    0xFFFFFFFF
-#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
-#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
-#define SYSCON_WIFI_CLK_EN_S  0
-
-#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x18)
-/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: reg_wifi_rst.*/
-#define SYSCON_WIFI_RST    0xFFFFFFFF
-#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
-#define SYSCON_WIFI_RST_V  0xFFFFFFFF
-#define SYSCON_WIFI_RST_S  0
-
-#define SYSTEM_WIFI_CLK_EN_REG          SYSCON_WIFI_CLK_EN_REG
-/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: */
-#define SYSTEM_WIFI_CLK_EN  0x00FB9FCF
-#define SYSTEM_WIFI_CLK_EN_M  ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
-#define SYSTEM_WIFI_CLK_EN_V  0x00FB9FCF
-#define SYSTEM_WIFI_CLK_EN_S  0
-
-/* Mask for all Wifi clock bits, 6 */
-#define SYSTEM_WIFI_CLK_WIFI_EN  0x0
-#define SYSTEM_WIFI_CLK_WIFI_EN_M  ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
-#define SYSTEM_WIFI_CLK_WIFI_EN_V  0x0
-#define SYSTEM_WIFI_CLK_WIFI_EN_S  0
-/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */
-#define SYSTEM_WIFI_CLK_BT_EN  0x0
-#define SYSTEM_WIFI_CLK_BT_EN_M  ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
-#define SYSTEM_WIFI_CLK_BT_EN_V  0x0
-#define SYSTEM_WIFI_CLK_BT_EN_S  0
-/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
-#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
-
-/* Digital team to check */
-//bluetooth baseband bit11
-#define SYSTEM_BT_BASEBAND_EN  BIT(11)
-//bluetooth LC bit16 and bit17
-#define SYSTEM_BT_LC_EN  (BIT(16)|BIT(17))
-
-/* Remaining single bit clock masks */
-#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
-#define SYSTEM_WIFI_CLK_UNUSED_BIT5  BIT(5)
-#define SYSTEM_WIFI_CLK_UNUSED_BIT12  BIT(12)
-#define SYSTEM_WIFI_CLK_EMAC_EN  BIT(14)
-#define SYSTEM_WIFI_CLK_RNG_EN  BIT(15)
-
-#define SYSTEM_CORE_RST_EN_REG        SYSTEM_WIFI_RST_EN_REG
-#define SYSTEM_WIFI_RST_EN_REG        SYSCON_WIFI_RST_EN_REG
-/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SYSTEM_BB_RST           BIT(0)
-#define SYSTEM_FE_RST           BIT(1)
-#define SYSTEM_MAC_RST          BIT(2)
-#define SYSTEM_BT_RST           BIT(3)
-#define SYSTEM_BTMAC_RST        BIT(4)
-#define SYSTEM_SDIO_RST         BIT(5)
-#define SYSTEM_EMAC_RST         BIT(7)
-#define SYSTEM_MACPWR_RST       BIT(8)
-#define SYSTEM_RW_BTMAC_RST     BIT(9)
-#define SYSTEM_RW_BTLP_RST      BIT(10)
-#define BLE_REG_REST_BIT        BIT(11)
-#define BLE_PWR_REG_REST_BIT    BIT(12)
-#define BLE_BB_REG_REST_BIT     BIT(13)
-#define BLE_RPA_REST_BIT        BIT(27)
-
-#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x1C)
-/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: reg_peri_io_swap.*/
-#define SYSCON_PERI_IO_SWAP    0x000000FF
-#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
-#define SYSCON_PERI_IO_SWAP_V  0xFF
-#define SYSCON_PERI_IO_SWAP_S  0
-
-#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x20)
-/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: reg_ext_mem_pms_lock.*/
-#define SYSCON_EXT_MEM_PMS_LOCK    (BIT(0))
-#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
-#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
-#define SYSCON_EXT_MEM_PMS_LOCK_S  0
-
-#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x28)
-/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: reg_flash_ace0_attr.*/
-#define SYSCON_FLASH_ACE0_ATTR    0x00000003
-#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
-#define SYSCON_FLASH_ACE0_ATTR_V  0x3
-#define SYSCON_FLASH_ACE0_ATTR_S  0
-
-#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x2C)
-/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: reg_flash_ace1_attr.*/
-#define SYSCON_FLASH_ACE1_ATTR    0x00000003
-#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
-#define SYSCON_FLASH_ACE1_ATTR_V  0x3
-#define SYSCON_FLASH_ACE1_ATTR_S  0
-
-#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x30)
-/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: reg_flash_ace2_attr.*/
-#define SYSCON_FLASH_ACE2_ATTR    0x00000003
-#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
-#define SYSCON_FLASH_ACE2_ATTR_V  0x3
-#define SYSCON_FLASH_ACE2_ATTR_S  0
-
-#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x34)
-/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: reg_flash_ace3_attr.*/
-#define SYSCON_FLASH_ACE3_ATTR    0x00000003
-#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
-#define SYSCON_FLASH_ACE3_ATTR_V  0x3
-#define SYSCON_FLASH_ACE3_ATTR_S  0
-
-#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x38)
-/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: reg_flash_ace0_addr_s.*/
-#define SYSCON_FLASH_ACE0_ADDR_S    0xFFFFFFFF
-#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
-#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE0_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x3C)
-/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
-/*description: reg_flash_ace1_addr_s.*/
-#define SYSCON_FLASH_ACE1_ADDR_S    0xFFFFFFFF
-#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
-#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE1_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x40)
-/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
-/*description: reg_flash_ace2_addr_s.*/
-#define SYSCON_FLASH_ACE2_ADDR_S    0xFFFFFFFF
-#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
-#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE2_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x44)
-/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */
-/*description: reg_flash_ace3_addr_s.*/
-#define SYSCON_FLASH_ACE3_ADDR_S    0xFFFFFFFF
-#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
-#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE3_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x48)
-/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: reg_flash_ace0_size.*/
-#define SYSCON_FLASH_ACE0_SIZE    0x00001FFF
-#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
-#define SYSCON_FLASH_ACE0_SIZE_V  0x1FFF
-#define SYSCON_FLASH_ACE0_SIZE_S  0
-
-#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x4C)
-/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: reg_flash_ace1_size.*/
-#define SYSCON_FLASH_ACE1_SIZE    0x00001FFF
-#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
-#define SYSCON_FLASH_ACE1_SIZE_V  0x1FFF
-#define SYSCON_FLASH_ACE1_SIZE_S  0
-
-#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x50)
-/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: reg_flash_ace2_size.*/
-#define SYSCON_FLASH_ACE2_SIZE    0x00001FFF
-#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
-#define SYSCON_FLASH_ACE2_SIZE_V  0x1FFF
-#define SYSCON_FLASH_ACE2_SIZE_S  0
-
-#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x54)
-/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: reg_flash_ace3_size.*/
-#define SYSCON_FLASH_ACE3_SIZE    0x00001FFF
-#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
-#define SYSCON_FLASH_ACE3_SIZE_V  0x1FFF
-#define SYSCON_FLASH_ACE3_SIZE_S  0
-
-#define SYSCON_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x88)
-/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
-/*description: reg_spi_mem_reject_cde.*/
-#define SYSCON_SPI_MEM_REJECT_CDE    0x0000001F
-#define SYSCON_SPI_MEM_REJECT_CDE_M  ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
-#define SYSCON_SPI_MEM_REJECT_CDE_V  0x1F
-#define SYSCON_SPI_MEM_REJECT_CDE_S  2
-/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: reg_spi_mem_reject_clr.*/
-#define SYSCON_SPI_MEM_REJECT_CLR    (BIT(1))
-#define SYSCON_SPI_MEM_REJECT_CLR_M  (BIT(1))
-#define SYSCON_SPI_MEM_REJECT_CLR_V  0x1
-#define SYSCON_SPI_MEM_REJECT_CLR_S  1
-/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: reg_spi_mem_reject_int.*/
-#define SYSCON_SPI_MEM_REJECT_INT    (BIT(0))
-#define SYSCON_SPI_MEM_REJECT_INT_M  (BIT(0))
-#define SYSCON_SPI_MEM_REJECT_INT_V  0x1
-#define SYSCON_SPI_MEM_REJECT_INT_S  0
-
-#define SYSCON_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x8C)
-/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: reg_spi_mem_reject_addr.*/
-#define SYSCON_SPI_MEM_REJECT_ADDR    0xFFFFFFFF
-#define SYSCON_SPI_MEM_REJECT_ADDR_M  ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
-#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
-#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
-
-#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x90)
-/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: reg_sdio_win_access_en.*/
-#define SYSCON_SDIO_WIN_ACCESS_EN    (BIT(0))
-#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
-#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
-#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
-
-#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x94)
-/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: reg_redcy_andor.*/
-#define SYSCON_REDCY_ANDOR    (BIT(31))
-#define SYSCON_REDCY_ANDOR_M  (BIT(31))
-#define SYSCON_REDCY_ANDOR_V  0x1
-#define SYSCON_REDCY_ANDOR_S  31
-/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: reg_redcy_sig0.*/
-#define SYSCON_REDCY_SIG0    0x7FFFFFFF
-#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
-#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
-#define SYSCON_REDCY_SIG0_S  0
-
-#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x98)
-/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: reg_redcy_nandor.*/
-#define SYSCON_REDCY_NANDOR    (BIT(31))
-#define SYSCON_REDCY_NANDOR_M  (BIT(31))
-#define SYSCON_REDCY_NANDOR_V  0x1
-#define SYSCON_REDCY_NANDOR_S  31
-/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: reg_redcy_sig1.*/
-#define SYSCON_REDCY_SIG1    0x7FFFFFFF
-#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
-#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
-#define SYSCON_REDCY_SIG1_S  0
-
-#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x9C)
-/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: reg_freq_mem_force_pd.*/
-#define SYSCON_FREQ_MEM_FORCE_PD    (BIT(7))
-#define SYSCON_FREQ_MEM_FORCE_PD_M  (BIT(7))
-#define SYSCON_FREQ_MEM_FORCE_PD_V  0x1
-#define SYSCON_FREQ_MEM_FORCE_PD_S  7
-/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: reg_freq_mem_force_pu.*/
-#define SYSCON_FREQ_MEM_FORCE_PU    (BIT(6))
-#define SYSCON_FREQ_MEM_FORCE_PU_M  (BIT(6))
-#define SYSCON_FREQ_MEM_FORCE_PU_V  0x1
-#define SYSCON_FREQ_MEM_FORCE_PU_S  6
-/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: reg_dc_mem_force_pd.*/
-#define SYSCON_DC_MEM_FORCE_PD    (BIT(5))
-#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
-#define SYSCON_DC_MEM_FORCE_PD_V  0x1
-#define SYSCON_DC_MEM_FORCE_PD_S  5
-/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: reg_dc_mem_force_pu.*/
-#define SYSCON_DC_MEM_FORCE_PU    (BIT(4))
-#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
-#define SYSCON_DC_MEM_FORCE_PU_V  0x1
-#define SYSCON_DC_MEM_FORCE_PU_S  4
-/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: reg_pbus_mem_force_pd.*/
-#define SYSCON_PBUS_MEM_FORCE_PD    (BIT(3))
-#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
-#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
-#define SYSCON_PBUS_MEM_FORCE_PD_S  3
-/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: reg_pbus_mem_force_pu.*/
-#define SYSCON_PBUS_MEM_FORCE_PU    (BIT(2))
-#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
-#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
-#define SYSCON_PBUS_MEM_FORCE_PU_S  2
-/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: reg_agc_mem_force_pd.*/
-#define SYSCON_AGC_MEM_FORCE_PD    (BIT(1))
-#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
-#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
-#define SYSCON_AGC_MEM_FORCE_PD_S  1
-/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: reg_agc_mem_force_pu.*/
-#define SYSCON_AGC_MEM_FORCE_PU    (BIT(0))
-#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
-#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
-#define SYSCON_AGC_MEM_FORCE_PU_S  0
-
-#define SYSCON_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0xA0)
-/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: reg_nobypass_cpu_iso_rst.*/
-#define SYSCON_NOBYPASS_CPU_ISO_RST    (BIT(27))
-#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
-#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x1
-#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
-/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
-/*description: reg_retention_link_addr.*/
-#define SYSCON_RETENTION_LINK_ADDR    0x07FFFFFF
-#define SYSCON_RETENTION_LINK_ADDR_M  ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
-#define SYSCON_RETENTION_LINK_ADDR_V  0x7FFFFFF
-#define SYSCON_RETENTION_LINK_ADDR_S  0
-
-#define SYSCON_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0xA4)
-/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */
-/*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t
-hen only when have access the sram have clock.*/
-#define SYSCON_SRAM_CLKGATE_FORCE_ON    0x0000000F
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0xF
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  3
-/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th
-en only when have access the rom have clock.*/
-#define SYSCON_ROM_CLKGATE_FORCE_ON    0x00000007
-#define SYSCON_ROM_CLKGATE_FORCE_ON_M  ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
-#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x7
-#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
-
-#define SYSCON_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0xA8)
-/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */
-/*description: Set 1 to let sram power down.*/
-#define SYSCON_SRAM_POWER_DOWN    0x0000000F
-#define SYSCON_SRAM_POWER_DOWN_M  ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
-#define SYSCON_SRAM_POWER_DOWN_V  0xF
-#define SYSCON_SRAM_POWER_DOWN_S  3
-/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set 1 to let rom power down.*/
-#define SYSCON_ROM_POWER_DOWN    0x00000007
-#define SYSCON_ROM_POWER_DOWN_M  ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
-#define SYSCON_ROM_POWER_DOWN_V  0x7
-#define SYSCON_ROM_POWER_DOWN_S  0
-
-#define SYSCON_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0xAC)
-/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */
-/*description: Set 1 to let sram power up.*/
-#define SYSCON_SRAM_POWER_UP    0x0000000F
-#define SYSCON_SRAM_POWER_UP_M  ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
-#define SYSCON_SRAM_POWER_UP_V  0xF
-#define SYSCON_SRAM_POWER_UP_S  3
-/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set 1 to let rom power up.*/
-#define SYSCON_ROM_POWER_UP    0x00000007
-#define SYSCON_ROM_POWER_UP_M  ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
-#define SYSCON_ROM_POWER_UP_V  0x7
-#define SYSCON_ROM_POWER_UP_S  0
-
-#define SYSCON_RND_DATA_REG          (DR_REG_SYSCON_BASE + 0xB0)
-/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: reg_rnd_data.*/
-#define SYSCON_RND_DATA    0xFFFFFFFF
-#define SYSCON_RND_DATA_M  ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
-#define SYSCON_RND_DATA_V  0xFFFFFFFF
-#define SYSCON_RND_DATA_S  0
-
-#define SYSCON_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0xB4)
-/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: reg_peri_backup_ena.*/
-#define SYSCON_PERI_BACKUP_ENA    (BIT(31))
-#define SYSCON_PERI_BACKUP_ENA_M  (BIT(31))
-#define SYSCON_PERI_BACKUP_ENA_V  0x1
-#define SYSCON_PERI_BACKUP_ENA_S  31
-/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: reg_peri_backup_to_mem.*/
-#define SYSCON_PERI_BACKUP_TO_MEM    (BIT(30))
-#define SYSCON_PERI_BACKUP_TO_MEM_M  (BIT(30))
-#define SYSCON_PERI_BACKUP_TO_MEM_V  0x1
-#define SYSCON_PERI_BACKUP_TO_MEM_S  30
-/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: reg_peri_backup_start.*/
-#define SYSCON_PERI_BACKUP_START    (BIT(29))
-#define SYSCON_PERI_BACKUP_START_M  (BIT(29))
-#define SYSCON_PERI_BACKUP_START_V  0x1
-#define SYSCON_PERI_BACKUP_START_S  29
-/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
-/*description: reg_peri_backup_size.*/
-#define SYSCON_PERI_BACKUP_SIZE    0x000003FF
-#define SYSCON_PERI_BACKUP_SIZE_M  ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
-#define SYSCON_PERI_BACKUP_SIZE_V  0x3FF
-#define SYSCON_PERI_BACKUP_SIZE_S  19
-/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
-/*description: reg_peri_backup_tout_thres.*/
-#define SYSCON_PERI_BACKUP_TOUT_THRES    0x000003FF
-#define SYSCON_PERI_BACKUP_TOUT_THRES_M  ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S))
-#define SYSCON_PERI_BACKUP_TOUT_THRES_V  0x3FF
-#define SYSCON_PERI_BACKUP_TOUT_THRES_S  9
-/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
-/*description: reg_peri_backup_burst_limit.*/
-#define SYSCON_PERI_BACKUP_BURST_LIMIT    0x0000001F
-#define SYSCON_PERI_BACKUP_BURST_LIMIT_M  ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
-#define SYSCON_PERI_BACKUP_BURST_LIMIT_V  0x1F
-#define SYSCON_PERI_BACKUP_BURST_LIMIT_S  4
-/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: reg_peri_backup_flow_err.*/
-#define SYSCON_PERI_BACKUP_FLOW_ERR    0x00000003
-#define SYSCON_PERI_BACKUP_FLOW_ERR_M  ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
-#define SYSCON_PERI_BACKUP_FLOW_ERR_V  0x3
-#define SYSCON_PERI_BACKUP_FLOW_ERR_S  1
-
-#define SYSCON_PERI_BACKUP_APB_ADDR_REG          (DR_REG_SYSCON_BASE + 0xB8)
-/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: reg_backup_apb_start_addr.*/
-#define SYSCON_BACKUP_APB_START_ADDR    0xFFFFFFFF
-#define SYSCON_BACKUP_APB_START_ADDR_M  ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
-#define SYSCON_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
-#define SYSCON_BACKUP_APB_START_ADDR_S  0
-
-#define SYSCON_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_SYSCON_BASE + 0xBC)
-/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: reg_backup_mem_start_addr.*/
-#define SYSCON_BACKUP_MEM_START_ADDR    0xFFFFFFFF
-#define SYSCON_BACKUP_MEM_START_ADDR_M  ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
-#define SYSCON_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
-#define SYSCON_BACKUP_MEM_START_ADDR_S  0
-
-#define SYSCON_PERI_BACKUP_INT_RAW_REG          (DR_REG_SYSCON_BASE + 0xC0)
-/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: reg_peri_backup_err_int_raw.*/
-#define SYSCON_PERI_BACKUP_ERR_INT_RAW    (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V  0x1
-#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S  1
-/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: reg_peri_backup_done_int_raw.*/
-#define SYSCON_PERI_BACKUP_DONE_INT_RAW    (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V  0x1
-#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S  0
-
-#define SYSCON_PERI_BACKUP_INT_ST_REG          (DR_REG_SYSCON_BASE + 0xC4)
-/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: reg_peri_backup_err_int_st.*/
-#define SYSCON_PERI_BACKUP_ERR_INT_ST    (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_ST_V  0x1
-#define SYSCON_PERI_BACKUP_ERR_INT_ST_S  1
-/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: reg_peri_backup_done_int_st.*/
-#define SYSCON_PERI_BACKUP_DONE_INT_ST    (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_ST_V  0x1
-#define SYSCON_PERI_BACKUP_DONE_INT_ST_S  0
-
-#define SYSCON_PERI_BACKUP_INT_ENA_REG          (DR_REG_SYSCON_BASE + 0xC8)
-/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: reg_peri_backup_err_int_ena.*/
-#define SYSCON_PERI_BACKUP_ERR_INT_ENA    (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V  0x1
-#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S  1
-/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: reg_peri_backup_done_int_ena.*/
-#define SYSCON_PERI_BACKUP_DONE_INT_ENA    (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V  0x1
-#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S  0
-
-#define SYSCON_PERI_BACKUP_INT_CLR_REG          (DR_REG_SYSCON_BASE + 0xD0)
-/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: reg_peri_backup_err_int_clr.*/
-#define SYSCON_PERI_BACKUP_ERR_INT_CLR    (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V  0x1
-#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S  1
-/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: reg_peri_backup_done_int_clr.*/
-#define SYSCON_PERI_BACKUP_DONE_INT_CLR    (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V  0x1
-#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S  0
-
-#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
-/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */
-/*description: reg_dateVersion control.*/
-#define SYSCON_DATE    0xFFFFFFFF
-#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
-#define SYSCON_DATE_V  0xFFFFFFFF
-#define SYSCON_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SYSCON_REG_H_ */
diff --git a/components/soc/esp32c2/include/soc/uart_reg.h b/components/soc/esp32c2/include/soc/uart_reg.h
deleted file mode 100644
index 0f105fa0b2f..00000000000
--- a/components/soc/esp32c2/include/soc/uart_reg.h
+++ /dev/null
@@ -1,1255 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_UART_REG_H_
-#define _SOC_UART_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
-/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: UART $n accesses FIFO via this register..*/
-#define UART_RXFIFO_RD_BYTE    0x000000FF
-#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
-#define UART_RXFIFO_RD_BYTE_V  0xFF
-#define UART_RXFIFO_RD_BYTE_S  0
-
-#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
-/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when input rxd edge changes more time
-s than what reg_active_threshold specifies in light sleeping mode..*/
-#define UART_WAKEUP_INT_RAW    (BIT(19))
-#define UART_WAKEUP_INT_RAW_M  (BIT(19))
-#define UART_WAKEUP_INT_RAW_V  0x1
-#define UART_WAKEUP_INT_RAW_S  19
-/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects the configured
-at_cmd char..*/
-#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when detects a clash between transmit
-ter and receiver in rs485 mode..*/
-#define UART_RS485_CLASH_INT_RAW    (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_V  0x1
-#define UART_RS485_CLASH_INT_RAW_S  17
-/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a data frame er
-ror from the echo of transmitter in rs485 mode..*/
-#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a parity error
-from the echo of transmitter in rs485 mode..*/
-#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter has send out all dat
-a in FIFO..*/
-#define UART_TX_DONE_INT_RAW    (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (BIT(14))
-#define UART_TX_DONE_INT_RAW_V  0x1
-#define UART_TX_DONE_INT_RAW_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter has kept the shortes
-t duration after sending the  last data..*/
-#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter completes  sending
-NULL characters, after all data in Tx-FIFO are sent..*/
-#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_V  0x1
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a glitch in the
- middle of a start bit..*/
-#define UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_V  0x1
-#define UART_GLITCH_DET_INT_RAW_S  11
-/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives Xoff char when
- uart_sw_flow_con_en is set to 1..*/
-#define UART_SW_XOFF_INT_RAW    (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
-#define UART_SW_XOFF_INT_RAW_V  0x1
-#define UART_SW_XOFF_INT_RAW_S  10
-/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver recevies Xon char when
-uart_sw_flow_con_en is set to 1..*/
-#define UART_SW_XON_INT_RAW    (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (BIT(9))
-#define UART_SW_XON_INT_RAW_V  0x1
-#define UART_SW_XON_INT_RAW_S  9
-/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver takes more time than rx
-_tout_thrhd to receive a byte..*/
-#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a 0 after the s
-top bit..*/
-#define UART_BRK_DET_INT_RAW    (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (BIT(7))
-#define UART_BRK_DET_INT_RAW_V  0x1
-#define UART_BRK_DET_INT_RAW_S  7
-/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects the edge change
- of CTSn signal..*/
-#define UART_CTS_CHG_INT_RAW    (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
-#define UART_CTS_CHG_INT_RAW_V  0x1
-#define UART_CTS_CHG_INT_RAW_S  6
-/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects the edge change
- of DSRn signal..*/
-#define UART_DSR_CHG_INT_RAW    (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
-#define UART_DSR_CHG_INT_RAW_V  0x1
-#define UART_DSR_CHG_INT_RAW_S  5
-/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives more data than
- the FIFO can store..*/
-#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_V  0x1
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a data frame er
-ror ..*/
-#define UART_FRM_ERR_INT_RAW    (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
-#define UART_FRM_ERR_INT_RAW_V  0x1
-#define UART_FRM_ERR_INT_RAW_S  3
-/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects a parity error
-in the data..*/
-#define UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_V  0x1
-#define UART_PARITY_ERR_INT_RAW_S  2
-/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */
-/*description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- less than what txfifo_empty_thrhd specifies ..*/
-#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives more data than
- what rxfifo_full_thrhd specifies..*/
-#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_V  0x1
-#define UART_RXFIFO_FULL_INT_RAW_S  0
-
-#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
-/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set t
-o 1..*/
-#define UART_WAKEUP_INT_ST    (BIT(19))
-#define UART_WAKEUP_INT_ST_M  (BIT(19))
-#define UART_WAKEUP_INT_ST_V  0x1
-#define UART_WAKEUP_INT_ST_S  19
-/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is se
-t to 1..*/
-#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set t
-o 1..*/
-#define UART_RS485_CLASH_INT_ST    (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
-#define UART_RS485_CLASH_INT_ST_V  0x1
-#define UART_RS485_CLASH_INT_ST_S  17
-/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is se
-t to 1..*/
-#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_V  0x1
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
- set to 1..*/
-#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1..*/
-#define UART_TX_DONE_INT_ST    (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (BIT(14))
-#define UART_TX_DONE_INT_ST_V  0x1
-#define UART_TX_DONE_INT_ST_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en
-a is set to 1..*/
-#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set t
-o 1..*/
-#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_V  0x1
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
-1..*/
-#define UART_GLITCH_DET_INT_ST    (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
-#define UART_GLITCH_DET_INT_ST_V  0x1
-#define UART_GLITCH_DET_INT_ST_S  11
-/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1..*/
-#define UART_SW_XOFF_INT_ST    (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (BIT(10))
-#define UART_SW_XOFF_INT_ST_V  0x1
-#define UART_SW_XOFF_INT_ST_S  10
-/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1..*/
-#define UART_SW_XON_INT_ST    (BIT(9))
-#define UART_SW_XON_INT_ST_M  (BIT(9))
-#define UART_SW_XON_INT_ST_V  0x1
-#define UART_SW_XON_INT_ST_S  9
-/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set t
-o 1..*/
-#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_V  0x1
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1..*/
-#define UART_BRK_DET_INT_ST    (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (BIT(7))
-#define UART_BRK_DET_INT_ST_V  0x1
-#define UART_BRK_DET_INT_ST_S  7
-/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1..*/
-#define UART_CTS_CHG_INT_ST    (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (BIT(6))
-#define UART_CTS_CHG_INT_ST_V  0x1
-#define UART_CTS_CHG_INT_ST_S  6
-/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1..*/
-#define UART_DSR_CHG_INT_ST    (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (BIT(5))
-#define UART_DSR_CHG_INT_ST_V  0x1
-#define UART_DSR_CHG_INT_ST_S  5
-/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
-1..*/
-#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_V  0x1
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1..*/
-#define UART_FRM_ERR_INT_ST    (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (BIT(3))
-#define UART_FRM_ERR_INT_ST_V  0x1
-#define UART_FRM_ERR_INT_ST_S  3
-/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
-1..*/
-#define UART_PARITY_ERR_INT_ST    (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
-#define UART_PARITY_ERR_INT_ST_V  0x1
-#define UART_PARITY_ERR_INT_ST_S  2
-/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is s
-et to 1..*/
-#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set t
-o 1..*/
-#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_V  0x1
-#define UART_RXFIFO_FULL_INT_ST_S  0
-
-#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
-/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the enable bit for uart_wakeup_int_st register..*/
-#define UART_WAKEUP_INT_ENA    (BIT(19))
-#define UART_WAKEUP_INT_ENA_M  (BIT(19))
-#define UART_WAKEUP_INT_ENA_V  0x1
-#define UART_WAKEUP_INT_ENA_S  19
-/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This is the enable bit for at_cmd_char_det_int_st register..*/
-#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_clash_int_st register..*/
-#define UART_RS485_CLASH_INT_ENA    (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_V  0x1
-#define UART_RS485_CLASH_INT_ENA_S  17
-/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_parity_err_int_st register..*/
-#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_parity_err_int_st register..*/
-#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_done_int_st register..*/
-#define UART_TX_DONE_INT_ENA    (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (BIT(14))
-#define UART_TX_DONE_INT_ENA_V  0x1
-#define UART_TX_DONE_INT_ENA_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_brk_idle_done_int_st register..*/
-#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_brk_done_int_st register..*/
-#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_V  0x1
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This is the enable bit for glitch_det_int_st register..*/
-#define UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_V  0x1
-#define UART_GLITCH_DET_INT_ENA_S  11
-/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the enable bit for sw_xoff_int_st register..*/
-#define UART_SW_XOFF_INT_ENA    (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
-#define UART_SW_XOFF_INT_ENA_V  0x1
-#define UART_SW_XOFF_INT_ENA_S  10
-/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This is the enable bit for sw_xon_int_st register..*/
-#define UART_SW_XON_INT_ENA    (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (BIT(9))
-#define UART_SW_XON_INT_ENA_V  0x1
-#define UART_SW_XON_INT_ENA_S  9
-/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_tout_int_st register..*/
-#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the enable bit for brk_det_int_st register..*/
-#define UART_BRK_DET_INT_ENA    (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (BIT(7))
-#define UART_BRK_DET_INT_ENA_V  0x1
-#define UART_BRK_DET_INT_ENA_S  7
-/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the enable bit for cts_chg_int_st register..*/
-#define UART_CTS_CHG_INT_ENA    (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
-#define UART_CTS_CHG_INT_ENA_V  0x1
-#define UART_CTS_CHG_INT_ENA_S  6
-/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the enable bit for dsr_chg_int_st register..*/
-#define UART_DSR_CHG_INT_ENA    (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
-#define UART_DSR_CHG_INT_ENA_V  0x1
-#define UART_DSR_CHG_INT_ENA_S  5
-/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_ovf_int_st register..*/
-#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_V  0x1
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the enable bit for frm_err_int_st register..*/
-#define UART_FRM_ERR_INT_ENA    (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
-#define UART_FRM_ERR_INT_ENA_V  0x1
-#define UART_FRM_ERR_INT_ENA_S  3
-/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the enable bit for parity_err_int_st register..*/
-#define UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_V  0x1
-#define UART_PARITY_ERR_INT_ENA_S  2
-/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the enable bit for txfifo_empty_int_st register..*/
-#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_full_int_st register..*/
-#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_V  0x1
-#define UART_RXFIFO_FULL_INT_ENA_S  0
-
-#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
-/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this bit to clear the uart_wakeup_int_raw interrupt..*/
-#define UART_WAKEUP_INT_CLR    (BIT(19))
-#define UART_WAKEUP_INT_CLR_M  (BIT(19))
-#define UART_WAKEUP_INT_CLR_V  0x1
-#define UART_WAKEUP_INT_CLR_S  19
-/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt..*/
-#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_clash_int_raw interrupt..*/
-#define UART_RS485_CLASH_INT_CLR    (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_V  0x1
-#define UART_RS485_CLASH_INT_CLR_S  17
-/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt..*/
-#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt..*/
-#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_done_int_raw interrupt..*/
-#define UART_TX_DONE_INT_CLR    (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (BIT(14))
-#define UART_TX_DONE_INT_CLR_V  0x1
-#define UART_TX_DONE_INT_CLR_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt..*/
-#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_brk_done_int_raw interrupt...*/
-#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_V  0x1
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to clear the glitch_det_int_raw interrupt..*/
-#define UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_V  0x1
-#define UART_GLITCH_DET_INT_CLR_S  11
-/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to clear the sw_xoff_int_raw interrupt..*/
-#define UART_SW_XOFF_INT_CLR    (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
-#define UART_SW_XOFF_INT_CLR_V  0x1
-#define UART_SW_XOFF_INT_CLR_S  10
-/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to clear the sw_xon_int_raw interrupt..*/
-#define UART_SW_XON_INT_CLR    (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (BIT(9))
-#define UART_SW_XON_INT_CLR_V  0x1
-#define UART_SW_XON_INT_CLR_S  9
-/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt..*/
-#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear the brk_det_int_raw interrupt..*/
-#define UART_BRK_DET_INT_CLR    (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (BIT(7))
-#define UART_BRK_DET_INT_CLR_V  0x1
-#define UART_BRK_DET_INT_CLR_S  7
-/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear the cts_chg_int_raw interrupt..*/
-#define UART_CTS_CHG_INT_CLR    (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
-#define UART_CTS_CHG_INT_CLR_V  0x1
-#define UART_CTS_CHG_INT_CLR_S  6
-/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear the dsr_chg_int_raw interrupt..*/
-#define UART_DSR_CHG_INT_CLR    (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
-#define UART_DSR_CHG_INT_CLR_V  0x1
-#define UART_DSR_CHG_INT_CLR_S  5
-/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt..*/
-#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_V  0x1
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear frm_err_int_raw interrupt..*/
-#define UART_FRM_ERR_INT_CLR    (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
-#define UART_FRM_ERR_INT_CLR_V  0x1
-#define UART_FRM_ERR_INT_CLR_S  3
-/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear parity_err_int_raw interrupt..*/
-#define UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_V  0x1
-#define UART_PARITY_ERR_INT_CLR_S  2
-/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear txfifo_empty_int_raw interrupt..*/
-#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_full_int_raw interrupt..*/
-#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_V  0x1
-#define UART_RXFIFO_FULL_INT_CLR_S  0
-
-#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
-/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
-/*description: The decimal part of the frequency divider factor..*/
-#define UART_CLKDIV_FRAG    0x0000000F
-#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
-#define UART_CLKDIV_FRAG_V  0xF
-#define UART_CLKDIV_FRAG_S  20
-/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2b6 ; */
-/*description: The integral part of the frequency divider factor..*/
-#define UART_CLKDIV    0x00000FFF
-#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
-#define UART_CLKDIV_V  0xFFF
-#define UART_CLKDIV_S  0
-
-#define UART_RX_FILT_REG(i)          (REG_UART_BASE(i) + 0x18)
-/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enable Rx signal filter..*/
-#define UART_GLITCH_FILT_EN    (BIT(8))
-#define UART_GLITCH_FILT_EN_M  (BIT(8))
-#define UART_GLITCH_FILT_EN_V  0x1
-#define UART_GLITCH_FILT_EN_S  8
-/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */
-/*description: when input pulse width is lower than this value, the pulse is ignored..*/
-#define UART_GLITCH_FILT    0x000000FF
-#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
-#define UART_GLITCH_FILT_V  0xFF
-#define UART_GLITCH_FILT_S  0
-
-#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
-/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */
-/*description: This bit represents the  level of the internal uart txd signal..*/
-#define UART_TXD    (BIT(31))
-#define UART_TXD_M  (BIT(31))
-#define UART_TXD_V  0x1
-#define UART_TXD_S  31
-/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This bit represents the level of the internal uart rts signal..*/
-#define UART_RTSN    (BIT(30))
-#define UART_RTSN_M  (BIT(30))
-#define UART_RTSN_V  0x1
-#define UART_RTSN_S  30
-/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit represents the level of the internal uart dtr signal..*/
-#define UART_DTRN    (BIT(29))
-#define UART_DTRN_M  (BIT(29))
-#define UART_DTRN_V  0x1
-#define UART_DTRN_S  29
-/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */
-/*description: Stores the byte number of data in Tx-FIFO..*/
-#define UART_TXFIFO_CNT    0x000003FF
-#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
-#define UART_TXFIFO_CNT_V  0x3FF
-#define UART_TXFIFO_CNT_S  16
-/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */
-/*description: This register represent the  level value of the internal uart rxd signal..*/
-#define UART_RXD    (BIT(15))
-#define UART_RXD_M  (BIT(15))
-#define UART_RXD_V  0x1
-#define UART_RXD_S  15
-/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */
-/*description: This register represent the level value of the internal uart cts signal..*/
-#define UART_CTSN    (BIT(14))
-#define UART_CTSN_M  (BIT(14))
-#define UART_CTSN_V  0x1
-#define UART_CTSN_S  14
-/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The register represent the level value of the internal uart dsr signal..*/
-#define UART_DSRN    (BIT(13))
-#define UART_DSRN_M  (BIT(13))
-#define UART_DSRN_V  0x1
-#define UART_DSRN_S  13
-/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: Stores the byte number of valid data in Rx-FIFO..*/
-#define UART_RXFIFO_CNT    0x000003FF
-#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
-#define UART_RXFIFO_CNT_V  0x3FF
-#define UART_RXFIFO_CNT_S  0
-
-#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
-/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */
-/*description: UART memory clock gate enable signal..*/
-#define UART_MEM_CLK_EN    (BIT(28))
-#define UART_MEM_CLK_EN_M  (BIT(28))
-#define UART_MEM_CLK_EN_V  0x1
-#define UART_MEM_CLK_EN_S  28
-/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This is the enable bit for detecting baudrate..*/
-#define UART_AUTOBAUD_EN    (BIT(27))
-#define UART_AUTOBAUD_EN_M  (BIT(27))
-#define UART_AUTOBAUD_EN_V  0x1
-#define UART_AUTOBAUD_EN_S  27
-/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver s
-tores the data even if the  received data is wrong..*/
-#define UART_ERR_WR_MASK    (BIT(26))
-#define UART_ERR_WR_MASK_M  (BIT(26))
-#define UART_ERR_WR_MASK_V  0x1
-#define UART_ERR_WR_MASK_S  26
-/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
-tes registers..*/
-#define UART_CLK_EN    (BIT(25))
-#define UART_CLK_EN_M  (BIT(25))
-#define UART_CLK_EN_V  0x1
-#define UART_CLK_EN_S  25
-/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart dtr signal..*/
-#define UART_DTR_INV    (BIT(24))
-#define UART_DTR_INV_M  (BIT(24))
-#define UART_DTR_INV_V  0x1
-#define UART_DTR_INV_S  24
-/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart rts signal..*/
-#define UART_RTS_INV    (BIT(23))
-#define UART_RTS_INV_M  (BIT(23))
-#define UART_RTS_INV_V  0x1
-#define UART_RTS_INV_S  23
-/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart txd signal..*/
-#define UART_TXD_INV    (BIT(22))
-#define UART_TXD_INV_M  (BIT(22))
-#define UART_TXD_INV_V  0x1
-#define UART_TXD_INV_S  22
-/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart dsr signal..*/
-#define UART_DSR_INV    (BIT(21))
-#define UART_DSR_INV_M  (BIT(21))
-#define UART_DSR_INV_V  0x1
-#define UART_DSR_INV_S  21
-/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart cts signal..*/
-#define UART_CTS_INV    (BIT(20))
-#define UART_CTS_INV_M  (BIT(20))
-#define UART_CTS_INV_V  0x1
-#define UART_CTS_INV_S  20
-/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart rxd signal..*/
-#define UART_RXD_INV    (BIT(19))
-#define UART_RXD_INV_M  (BIT(19))
-#define UART_RXD_INV_V  0x1
-#define UART_RXD_INV_S  19
-/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: Set this bit to reset the uart transmit-FIFO..*/
-#define UART_TXFIFO_RST    (BIT(18))
-#define UART_TXFIFO_RST_M  (BIT(18))
-#define UART_TXFIFO_RST_V  0x1
-#define UART_TXFIFO_RST_S  18
-/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: Set this bit to reset the uart receive-FIFO..*/
-#define UART_RXFIFO_RST    (BIT(17))
-#define UART_RXFIFO_RST_M  (BIT(17))
-#define UART_RXFIFO_RST_V  0x1
-#define UART_RXFIFO_RST_S  17
-/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: Set this bit to enable IrDA protocol..*/
-#define UART_IRDA_EN    (BIT(16))
-#define UART_IRDA_EN_M  (BIT(16))
-#define UART_IRDA_EN_V  0x1
-#define UART_IRDA_EN_S  16
-/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to enable flow control function for transmitter..*/
-#define UART_TX_FLOW_EN    (BIT(15))
-#define UART_TX_FLOW_EN_M  (BIT(15))
-#define UART_TX_FLOW_EN_V  0x1
-#define UART_TX_FLOW_EN_S  15
-/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable uart loopback test mode..*/
-#define UART_LOOPBACK    (BIT(14))
-#define UART_LOOPBACK_M  (BIT(14))
-#define UART_LOOPBACK_V  0x1
-#define UART_LOOPBACK_S  14
-/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to invert the level of IrDA receiver..*/
-#define UART_IRDA_RX_INV    (BIT(13))
-#define UART_IRDA_RX_INV_M  (BIT(13))
-#define UART_IRDA_RX_INV_V  0x1
-#define UART_IRDA_RX_INV_S  13
-/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to invert the level of  IrDA transmitter..*/
-#define UART_IRDA_TX_INV    (BIT(12))
-#define UART_IRDA_TX_INV_M  (BIT(12))
-#define UART_IRDA_TX_INV_V  0x1
-#define UART_IRDA_TX_INV_S  12
-/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA tr
-ansmitter's 11th bit to 0..*/
-#define UART_IRDA_WCTL    (BIT(11))
-#define UART_IRDA_WCTL_M  (BIT(11))
-#define UART_IRDA_WCTL_V  0x1
-#define UART_IRDA_WCTL_S  11
-/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the start enable bit for IrDA transmitter..*/
-#define UART_IRDA_TX_EN    (BIT(10))
-#define UART_IRDA_TX_EN_M  (BIT(10))
-#define UART_IRDA_TX_EN_V  0x1
-#define UART_IRDA_TX_EN_S  10
-/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to enable IrDA loopback mode..*/
-#define UART_IRDA_DPLX    (BIT(9))
-#define UART_IRDA_DPLX_M  (BIT(9))
-#define UART_IRDA_DPLX_V  0x1
-#define UART_IRDA_DPLX_S  9
-/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enbale transmitter to  send NULL when the process of sending dat
-a is done..*/
-#define UART_TXD_BRK    (BIT(8))
-#define UART_TXD_BRK_M  (BIT(8))
-#define UART_TXD_BRK_V  0x1
-#define UART_TXD_BRK_S  8
-/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This register is used to configure the software dtr signal which is used in soft
-ware flow control..*/
-#define UART_SW_DTR    (BIT(7))
-#define UART_SW_DTR_M  (BIT(7))
-#define UART_SW_DTR_V  0x1
-#define UART_SW_DTR_S  7
-/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This register is used to configure the software rts signal which is used in soft
-ware flow control..*/
-#define UART_SW_RTS    (BIT(6))
-#define UART_SW_RTS_M  (BIT(6))
-#define UART_SW_RTS_V  0x1
-#define UART_SW_RTS_S  6
-/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
-/*description: This register is used to set the length of  stop bit..*/
-#define UART_STOP_BIT_NUM    0x00000003
-#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
-#define UART_STOP_BIT_NUM_V  0x3
-#define UART_STOP_BIT_NUM_S  4
-/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
-/*description: This register is used to set the length of data..*/
-#define UART_BIT_NUM    0x00000003
-#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
-#define UART_BIT_NUM_V  0x3
-#define UART_BIT_NUM_S  2
-/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to enable uart parity check..*/
-#define UART_PARITY_EN    (BIT(1))
-#define UART_PARITY_EN_M  (BIT(1))
-#define UART_PARITY_EN_V  0x1
-#define UART_PARITY_EN_S  1
-/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This register is used to configure the parity check mode..*/
-#define UART_PARITY    (BIT(0))
-#define UART_PARITY_M  (BIT(0))
-#define UART_PARITY_V  0x1
-#define UART_PARITY_S  0
-
-#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
-/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: This is the enble bit for uart receiver's timeout function..*/
-#define UART_RX_TOUT_EN    (BIT(21))
-#define UART_RX_TOUT_EN_M  (BIT(21))
-#define UART_RX_TOUT_EN_V  0x1
-#define UART_RX_TOUT_EN_S  21
-/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This is the flow enable bit for UART receiver..*/
-#define UART_RX_FLOW_EN    (BIT(20))
-#define UART_RX_FLOW_EN_M  (BIT(20))
-#define UART_RX_FLOW_EN_V  0x1
-#define UART_RX_FLOW_EN_S  20
-/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works..*/
-#define UART_RX_TOUT_FLOW_DIS    (BIT(19))
-#define UART_RX_TOUT_FLOW_DIS_M  (BIT(19))
-#define UART_RX_TOUT_FLOW_DIS_V  0x1
-#define UART_RX_TOUT_FLOW_DIS_S  19
-/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: Disable UART Rx data overflow detect..*/
-#define UART_DIS_RX_DAT_OVF    (BIT(18))
-#define UART_DIS_RX_DAT_OVF_M  (BIT(18))
-#define UART_DIS_RX_DAT_OVF_V  0x1
-#define UART_DIS_RX_DAT_OVF_S  18
-/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */
-/*description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is le
-ss than this register value..*/
-#define UART_TXFIFO_EMPTY_THRHD    0x000001FF
-#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
-#define UART_TXFIFO_EMPTY_THRHD_V  0x1FF
-#define UART_TXFIFO_EMPTY_THRHD_S  9
-/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */
-/*description: It will produce rxfifo_full_int interrupt when receiver receives more data than
-this register value..*/
-#define UART_RXFIFO_FULL_THRHD    0x000001FF
-#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
-#define UART_RXFIFO_FULL_THRHD_V  0x1FF
-#define UART_RXFIFO_FULL_THRHD_S  0
-
-#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
-/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
-/*description: This register stores the value of the minimum duration time of the low level pul
-se. It is used in baud rate-detect process..*/
-#define UART_LOWPULSE_MIN_CNT    0x00000FFF
-#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
-#define UART_LOWPULSE_MIN_CNT_V  0xFFF
-#define UART_LOWPULSE_MIN_CNT_S  0
-
-#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
-/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
-/*description: This register stores  the value of the maxinum duration time for the high level
-pulse. It is used in baud rate-detect process..*/
-#define UART_HIGHPULSE_MIN_CNT    0x00000FFF
-#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
-#define UART_HIGHPULSE_MIN_CNT_V  0xFFF
-#define UART_HIGHPULSE_MIN_CNT_S  0
-
-#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
-/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register stores the count of rxd edge change. It is used in baud rate-detec
-t process..*/
-#define UART_RXD_EDGE_CNT    0x000003FF
-#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
-#define UART_RXD_EDGE_CNT_V  0x3FF
-#define UART_RXD_EDGE_CNT_S  0
-
-#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
-/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to send Xoff char. It is cleared by hardware automatically..*/
-#define UART_SEND_XOFF    (BIT(5))
-#define UART_SEND_XOFF_M  (BIT(5))
-#define UART_SEND_XOFF_V  0x1
-#define UART_SEND_XOFF_S  5
-/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to send Xon char. It is cleared by hardware automatically..*/
-#define UART_SEND_XON    (BIT(4))
-#define UART_SEND_XON_M  (BIT(4))
-#define UART_SEND_XON_V  0x1
-#define UART_SEND_XON_S  4
-/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to stop the  transmitter from sending data..*/
-#define UART_FORCE_XOFF    (BIT(3))
-#define UART_FORCE_XOFF_M  (BIT(3))
-#define UART_FORCE_XOFF_V  0x1
-#define UART_FORCE_XOFF_S  3
-/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to enable the transmitter to go on sending data..*/
-#define UART_FORCE_XON    (BIT(2))
-#define UART_FORCE_XON_M  (BIT(2))
-#define UART_FORCE_XON_V  0x1
-#define UART_FORCE_XON_S  2
-/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to remove flow control char from the received data..*/
-#define UART_XONOFF_DEL    (BIT(1))
-#define UART_XONOFF_DEL_M  (BIT(1))
-#define UART_XONOFF_DEL_V  0x1
-#define UART_XONOFF_DEL_S  1
-/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable software flow control. It is used with register sw_xon or
- sw_xoff..*/
-#define UART_SW_FLOW_CON_EN    (BIT(0))
-#define UART_SW_FLOW_CON_EN_M  (BIT(0))
-#define UART_SW_FLOW_CON_EN_V  0x1
-#define UART_SW_FLOW_CON_EN_S  0
-
-#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
-/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
-/*description: The uart is activated from light sleeping mode when the input rxd edge changes m
-ore times than this register value..*/
-#define UART_ACTIVE_THRESHOLD    0x000003FF
-#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
-#define UART_ACTIVE_THRESHOLD_V  0x3FF
-#define UART_ACTIVE_THRESHOLD_S  0
-
-#define UART_SWFC_CONF0_REG(i)          (REG_UART_BASE(i) + 0x3C)
-/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */
-/*description: This register stores the Xoff flow control char..*/
-#define UART_XOFF_CHAR    0x000000FF
-#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
-#define UART_XOFF_CHAR_V  0xFF
-#define UART_XOFF_CHAR_S  9
-/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */
-/*description: When the data amount in Rx-FIFO is more than this register value with uart_sw_fl
-ow_con_en set to 1, it will send a Xoff char..*/
-#define UART_XOFF_THRESHOLD    0x000001FF
-#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
-#define UART_XOFF_THRESHOLD_V  0x1FF
-#define UART_XOFF_THRESHOLD_S  0
-
-#define UART_SWFC_CONF1_REG(i)          (REG_UART_BASE(i) + 0x40)
-/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */
-/*description: This register stores the Xon flow control char..*/
-#define UART_XON_CHAR    0x000000FF
-#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
-#define UART_XON_CHAR_V  0xFF
-#define UART_XON_CHAR_S  9
-/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: When the data amount in Rx-FIFO is less than this register value with uart_sw_fl
-ow_con_en set to 1, it will send a Xon char..*/
-#define UART_XON_THRESHOLD    0x000001FF
-#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
-#define UART_XON_THRESHOLD_V  0x1FF
-#define UART_XON_THRESHOLD_S  0
-
-#define UART_TXBRK_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
-/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */
-/*description: This register is used to configure the number of 0 to be sent after the process
-of sending data is done. It is active when txd_brk is set to 1..*/
-#define UART_TX_BRK_NUM    0x000000FF
-#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
-#define UART_TX_BRK_NUM_V  0xFF
-#define UART_TX_BRK_NUM_S  0
-
-#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x48)
-/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
-/*description: This register is used to configure the duration time between transfers..*/
-#define UART_TX_IDLE_NUM    0x000003FF
-#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
-#define UART_TX_IDLE_NUM_V  0x3FF
-#define UART_TX_IDLE_NUM_S  10
-/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
-/*description: It will produce frame end signal when receiver takes more time to receive one by
-te data than this register value..*/
-#define UART_RX_IDLE_THRHD    0x000003FF
-#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
-#define UART_RX_IDLE_THRHD_V  0x3FF
-#define UART_RX_IDLE_THRHD_S  0
-
-#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x4C)
-/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
-/*description: This register is used to delay the transmitter's internal data signal..*/
-#define UART_RS485_TX_DLY_NUM    0x0000000F
-#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
-#define UART_RS485_TX_DLY_NUM_V  0xF
-#define UART_RS485_TX_DLY_NUM_S  6
-/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This register is used to delay the receiver's internal data signal..*/
-#define UART_RS485_RX_DLY_NUM    (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
-#define UART_RS485_RX_DLY_NUM_V  0x1
-#define UART_RS485_RX_DLY_NUM_S  5
-/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy..*/
-#define UART_RS485RXBY_TX_EN    (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (BIT(4))
-#define UART_RS485RXBY_TX_EN_V  0x1
-#define UART_RS485RXBY_TX_EN_S  4
-/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable receiver could receive data when the transmitter is trans
-mitting data in rs485 mode..*/
-#define UART_RS485TX_RX_EN    (BIT(3))
-#define UART_RS485TX_RX_EN_M  (BIT(3))
-#define UART_RS485TX_RX_EN_V  0x1
-#define UART_RS485TX_RX_EN_S  3
-/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to delay the stop bit by 1 bit..*/
-#define UART_DL1_EN    (BIT(2))
-#define UART_DL1_EN_M  (BIT(2))
-#define UART_DL1_EN_V  0x1
-#define UART_DL1_EN_S  2
-/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to delay the stop bit by 1 bit..*/
-#define UART_DL0_EN    (BIT(1))
-#define UART_DL0_EN_M  (BIT(1))
-#define UART_DL0_EN_V  0x1
-#define UART_DL0_EN_S  1
-/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to choose the rs485 mode..*/
-#define UART_RS485_EN    (BIT(0))
-#define UART_RS485_EN_M  (BIT(0))
-#define UART_RS485_EN_V  0x1
-#define UART_RS485_EN_S  0
-
-#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x50)
-/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
-/*description: This register is used to configure the idle duration time before the first at_cm
-d is received by receiver..*/
-#define UART_PRE_IDLE_NUM    0x0000FFFF
-#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
-#define UART_PRE_IDLE_NUM_V  0xFFFF
-#define UART_PRE_IDLE_NUM_S  0
-
-#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x54)
-/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
-/*description: This register is used to configure the duration time between the last at_cmd and
- the next data..*/
-#define UART_POST_IDLE_NUM    0x0000FFFF
-#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
-#define UART_POST_IDLE_NUM_V  0xFFFF
-#define UART_POST_IDLE_NUM_S  0
-
-#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x58)
-/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */
-/*description: This register is used to configure the duration time between the at_cmd chars..*/
-#define UART_RX_GAP_TOUT    0x0000FFFF
-#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
-#define UART_RX_GAP_TOUT_V  0xFFFF
-#define UART_RX_GAP_TOUT_S  0
-
-#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x5C)
-/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
-/*description: This register is used to configure the num of continuous at_cmd chars received b
-y receiver..*/
-#define UART_CHAR_NUM    0x000000FF
-#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
-#define UART_CHAR_NUM_V  0xFF
-#define UART_CHAR_NUM_S  8
-/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
-/*description: This register is used to configure the content of at_cmd char..*/
-#define UART_AT_CMD_CHAR    0x000000FF
-#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
-#define UART_AT_CMD_CHAR_V  0xFF
-#define UART_AT_CMD_CHAR_S  0
-
-#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x60)
-/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to force power up UART memory..*/
-#define UART_MEM_FORCE_PU    (BIT(27))
-#define UART_MEM_FORCE_PU_M  (BIT(27))
-#define UART_MEM_FORCE_PU_V  0x1
-#define UART_MEM_FORCE_PU_S  27
-/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to force power down UART memory..*/
-#define UART_MEM_FORCE_PD    (BIT(26))
-#define UART_MEM_FORCE_PD_M  (BIT(26))
-#define UART_MEM_FORCE_PD_V  0x1
-#define UART_MEM_FORCE_PD_S  26
-/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */
-/*description: This register is used to configure the threshold time that receiver takes to rec
-eive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver t
-akes more time to receive one byte with rx_tout_en set to 1..*/
-#define UART_RX_TOUT_THRHD    0x000003FF
-#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
-#define UART_RX_TOUT_THRHD_V  0x3FF
-#define UART_RX_TOUT_THRHD_S  16
-/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
-/*description: This register is used to configure the maximum amount of data that can be receiv
-ed  when hardware flow control works..*/
-#define UART_RX_FLOW_THRHD    0x000001FF
-#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
-#define UART_RX_FLOW_THRHD_V  0x1FF
-#define UART_RX_FLOW_THRHD_S  7
-/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */
-/*description: This register is used to configure the amount of mem allocated for transmit-FIFO
-. The default number is 128 bytes..*/
-#define UART_TX_SIZE    0x00000007
-#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
-#define UART_TX_SIZE_V  0x7
-#define UART_TX_SIZE_S  4
-/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */
-/*description: This register is used to configure the amount of mem allocated for receive-FIFO.
- The default number is 128 bytes..*/
-#define UART_RX_SIZE    0x00000007
-#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
-#define UART_RX_SIZE_V  0x7
-#define UART_RX_SIZE_S  1
-
-#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
-/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
-/*description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx
--FIFO_Ctrl..*/
-#define UART_TX_RADDR    0x000003FF
-#define UART_TX_RADDR_M  ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S))
-#define UART_TX_RADDR_V  0x3FF
-#define UART_TX_RADDR_S  11
-/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
-via APB..*/
-#define UART_APB_TX_WADDR    0x000003FF
-#define UART_APB_TX_WADDR_M  ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S))
-#define UART_APB_TX_WADDR_V  0x3FF
-#define UART_APB_TX_WADDR_S  0
-
-#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x68)
-/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h100 ; */
-/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-F
-IFO. UART0 is 10'h100. UART1 is 10'h180..*/
-#define UART_RX_WADDR    0x000003FF
-#define UART_RX_WADDR_M  ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
-#define UART_RX_WADDR_V  0x3FF
-#define UART_RX_WADDR_S  11
-/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */
-/*description: This register stores the offset address in RX-FIFO when software reads data from
- Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180..*/
-#define UART_APB_RX_RADDR    0x000003FF
-#define UART_APB_RX_RADDR_M  ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S))
-#define UART_APB_RX_RADDR_V  0x3FF
-#define UART_APB_RX_RADDR_S  0
-
-#define UART_FSM_STATUS_REG(i)          (REG_UART_BASE(i) + 0x6C)
-/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: This is the status register of transmitter..*/
-#define UART_ST_UTX_OUT    0x0000000F
-#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
-#define UART_ST_UTX_OUT_V  0xF
-#define UART_ST_UTX_OUT_S  4
-/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: This is the status register of receiver..*/
-#define UART_ST_URX_OUT    0x0000000F
-#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
-#define UART_ST_URX_OUT_V  0xF
-#define UART_ST_URX_OUT_S  0
-
-#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x70)
-/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
-/*description: This register stores the minimal input clock count between two positive edges. I
-t is used in boudrate-detect process..*/
-#define UART_POSEDGE_MIN_CNT    0x00000FFF
-#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
-#define UART_POSEDGE_MIN_CNT_V  0xFFF
-#define UART_POSEDGE_MIN_CNT_S  0
-
-#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x74)
-/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
-/*description: This register stores the minimal input clock count between two negative edges. I
-t is used in boudrate-detect process..*/
-#define UART_NEGEDGE_MIN_CNT    0x00000FFF
-#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
-#define UART_NEGEDGE_MIN_CNT_V  0xFFF
-#define UART_NEGEDGE_MIN_CNT_S  0
-
-#define UART_CLK_CONF_REG(i)          (REG_UART_BASE(i) + 0x78)
-/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit, reset UART Rx..*/
-#define UART_RX_RST_CORE    (BIT(27))
-#define UART_RX_RST_CORE_M  (BIT(27))
-#define UART_RX_RST_CORE_V  0x1
-#define UART_RX_RST_CORE_S  27
-/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit, reset UART Tx..*/
-#define UART_TX_RST_CORE    (BIT(26))
-#define UART_TX_RST_CORE_M  (BIT(26))
-#define UART_TX_RST_CORE_V  0x1
-#define UART_TX_RST_CORE_S  26
-/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Rx clock..*/
-#define UART_RX_SCLK_EN    (BIT(25))
-#define UART_RX_SCLK_EN_M  (BIT(25))
-#define UART_RX_SCLK_EN_V  0x1
-#define UART_RX_SCLK_EN_S  25
-/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Tx clock..*/
-#define UART_TX_SCLK_EN    (BIT(24))
-#define UART_TX_SCLK_EN_M  (BIT(24))
-#define UART_TX_SCLK_EN_V  0x1
-#define UART_TX_SCLK_EN_S  24
-/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit, reset UART Tx/Rx..*/
-#define UART_RST_CORE    (BIT(23))
-#define UART_RST_CORE_M  (BIT(23))
-#define UART_RST_CORE_V  0x1
-#define UART_RST_CORE_S  23
-/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Tx/Rx clock..*/
-#define UART_SCLK_EN    (BIT(22))
-#define UART_SCLK_EN_M  (BIT(22))
-#define UART_SCLK_EN_V  0x1
-#define UART_SCLK_EN_S  22
-/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */
-/*description: UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL..*/
-#define UART_SCLK_SEL    0x00000003
-#define UART_SCLK_SEL_M  ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S))
-#define UART_SCLK_SEL_V  0x3
-#define UART_SCLK_SEL_S  20
-/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */
-/*description: The integral part of the frequency divider factor..*/
-#define UART_SCLK_DIV_NUM    0x000000FF
-#define UART_SCLK_DIV_NUM_M  ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S))
-#define UART_SCLK_DIV_NUM_V  0xFF
-#define UART_SCLK_DIV_NUM_S  12
-/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */
-/*description: The numerator of the frequency divider factor..*/
-#define UART_SCLK_DIV_A    0x0000003F
-#define UART_SCLK_DIV_A_M  ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S))
-#define UART_SCLK_DIV_A_V  0x3F
-#define UART_SCLK_DIV_A_S  6
-/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: The  denominator of the frequency divider factor..*/
-#define UART_SCLK_DIV_B    0x0000003F
-#define UART_SCLK_DIV_B_M  ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S))
-#define UART_SCLK_DIV_B_V  0x3F
-#define UART_SCLK_DIV_B_S  0
-
-#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x7C)
-/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */
-/*description: This is the version register..*/
-#define UART_DATE    0xFFFFFFFF
-#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
-#define UART_DATE_V  0xFFFFFFFF
-#define UART_DATE_S  0
-
-#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x80)
-/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Software write 1 would synchronize registers into UART Core clock domain and wou
-ld be cleared by hardware after synchronization is done..*/
-#define UART_UPDATE    (BIT(31))
-#define UART_UPDATE_M  (BIT(31))
-#define UART_UPDATE_V  0x1
-#define UART_UPDATE_S  31
-/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This bit used to select synchronize mode. 1: Registers are auto synchronized int
-o UART Core clock and UART core should be keep the same with APB clock. 0: After
- configure registers, software needs to write 1 to UART_REG_UPDATE to synchroniz
-e registers..*/
-#define UART_HIGH_SPEED    (BIT(30))
-#define UART_HIGH_SPEED_M  (BIT(30))
-#define UART_HIGH_SPEED_V  0x1
-#define UART_HIGH_SPEED_S  30
-/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */
-/*description: This register is used to configure the uart_id..*/
-#define UART_ID    0x3FFFFFFF
-#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
-#define UART_ID_V  0x3FFFFFFF
-#define UART_ID_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_UART_REG_H_ */
diff --git a/components/soc/esp32c2/include/soc/uart_struct.h b/components/soc/esp32c2/include/soc/uart_struct.h
deleted file mode 100644
index 64c4504e39d..00000000000
--- a/components/soc/esp32c2/include/soc/uart_struct.h
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct uart_dev_s {
-    union {
-        struct {
-            uint32_t rw_byte                       :    32;  /*UART $n accesses FIFO via this register.*/
-        };
-        uint32_t val;
-    } ahb_fifo;
-    union {
-        struct {
-            uint32_t rxfifo_full                   :    1;  /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
-            uint32_t txfifo_empty                  :    1;  /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
-            uint32_t parity_err                    :    1;  /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
-            uint32_t frm_err                       :    1;  /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
-            uint32_t rxfifo_ovf                    :    1;  /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
-            uint32_t dsr_chg                       :    1;  /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
-            uint32_t cts_chg                       :    1;  /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
-            uint32_t brk_det                       :    1;  /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
-            uint32_t rxfifo_tout                   :    1;  /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
-            uint32_t sw_xon                        :    1;  /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
-            uint32_t sw_xoff                       :    1;  /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
-            uint32_t glitch_det                    :    1;  /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
-            uint32_t tx_brk_done                   :    1;  /*This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.*/
-            uint32_t tx_brk_idle_done              :    1;  /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.*/
-            uint32_t tx_done                       :    1;  /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
-            uint32_t rs485_parity_err              :    1;  /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
-            uint32_t rs485_frm_err                 :    1;  /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
-            uint32_t rs485_clash                   :    1;  /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
-            uint32_t at_cmd_char_det               :    1;  /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
-            uint32_t wakeup                        :    1;  /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rxfifo_full                   :    1;  /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
-            uint32_t txfifo_empty                  :    1;  /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
-            uint32_t parity_err                    :    1;  /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
-            uint32_t frm_err                       :    1;  /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
-            uint32_t rxfifo_ovf                    :    1;  /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
-            uint32_t dsr_chg                       :    1;  /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
-            uint32_t cts_chg                       :    1;  /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
-            uint32_t brk_det                       :    1;  /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
-            uint32_t rxfifo_tout                   :    1;  /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
-            uint32_t sw_xon                        :    1;  /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
-            uint32_t sw_xoff                       :    1;  /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
-            uint32_t glitch_det                    :    1;  /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
-            uint32_t tx_brk_done                   :    1;  /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
-            uint32_t tx_brk_idle_done              :    1;  /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
-            uint32_t tx_done                       :    1;  /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
-            uint32_t rs485_parity_err              :    1;  /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
-            uint32_t rs485_frm_err                 :    1;  /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
-            uint32_t rs485_clash                   :    1;  /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
-            uint32_t at_cmd_char_det               :    1;  /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
-            uint32_t wakeup                        :    1;  /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t rxfifo_full                   :    1;  /*This is the enable bit for rxfifo_full_int_st register.*/
-            uint32_t txfifo_empty                  :    1;  /*This is the enable bit for txfifo_empty_int_st register.*/
-            uint32_t parity_err                    :    1;  /*This is the enable bit for parity_err_int_st register.*/
-            uint32_t frm_err                       :    1;  /*This is the enable bit for frm_err_int_st register.*/
-            uint32_t rxfifo_ovf                    :    1;  /*This is the enable bit for rxfifo_ovf_int_st register.*/
-            uint32_t dsr_chg                       :    1;  /*This is the enable bit for dsr_chg_int_st register.*/
-            uint32_t cts_chg                       :    1;  /*This is the enable bit for cts_chg_int_st register.*/
-            uint32_t brk_det                       :    1;  /*This is the enable bit for brk_det_int_st register.*/
-            uint32_t rxfifo_tout                   :    1;  /*This is the enable bit for rxfifo_tout_int_st register.*/
-            uint32_t sw_xon                        :    1;  /*This is the enable bit for sw_xon_int_st register.*/
-            uint32_t sw_xoff                       :    1;  /*This is the enable bit for sw_xoff_int_st register.*/
-            uint32_t glitch_det                    :    1;  /*This is the enable bit for glitch_det_int_st register.*/
-            uint32_t tx_brk_done                   :    1;  /*This is the enable bit for tx_brk_done_int_st register.*/
-            uint32_t tx_brk_idle_done              :    1;  /*This is the enable bit for tx_brk_idle_done_int_st register.*/
-            uint32_t tx_done                       :    1;  /*This is the enable bit for tx_done_int_st register.*/
-            uint32_t rs485_parity_err              :    1;  /*This is the enable bit for rs485_parity_err_int_st register.*/
-            uint32_t rs485_frm_err                 :    1;  /*This is the enable bit for rs485_parity_err_int_st register.*/
-            uint32_t rs485_clash                   :    1;  /*This is the enable bit for rs485_clash_int_st register.*/
-            uint32_t at_cmd_char_det               :    1;  /*This is the enable bit for at_cmd_char_det_int_st register.*/
-            uint32_t wakeup                        :    1;  /*This is the enable bit for uart_wakeup_int_st register.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rxfifo_full                   :    1;  /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
-            uint32_t txfifo_empty                  :    1;  /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
-            uint32_t parity_err                    :    1;  /*Set this bit to clear parity_err_int_raw interrupt.*/
-            uint32_t frm_err                       :    1;  /*Set this bit to clear frm_err_int_raw interrupt.*/
-            uint32_t rxfifo_ovf                    :    1;  /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
-            uint32_t dsr_chg                       :    1;  /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
-            uint32_t cts_chg                       :    1;  /*Set this bit to clear the cts_chg_int_raw interrupt.*/
-            uint32_t brk_det                       :    1;  /*Set this bit to clear the brk_det_int_raw interrupt.*/
-            uint32_t rxfifo_tout                   :    1;  /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
-            uint32_t sw_xon                        :    1;  /*Set this bit to clear the sw_xon_int_raw interrupt.*/
-            uint32_t sw_xoff                       :    1;  /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
-            uint32_t glitch_det                    :    1;  /*Set this bit to clear the glitch_det_int_raw interrupt.*/
-            uint32_t tx_brk_done                   :    1;  /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
-            uint32_t tx_brk_idle_done              :    1;  /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
-            uint32_t tx_done                       :    1;  /*Set this bit to clear the tx_done_int_raw interrupt.*/
-            uint32_t rs485_parity_err              :    1;  /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
-            uint32_t rs485_frm_err                 :    1;  /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
-            uint32_t rs485_clash                   :    1;  /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
-            uint32_t at_cmd_char_det               :    1;  /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
-            uint32_t wakeup                        :    1;  /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t div_int                       :    12;  /*The integral part of the frequency divider factor.*/
-            uint32_t reserved12                    :    8;
-            uint32_t div_frag                      :    4;  /*The decimal part of the frequency divider factor.*/
-            uint32_t reserved24                    :    8;  /*Reserved*/
-        };
-        uint32_t val;
-    } clk_div;
-    union {
-        struct {
-            uint32_t glitch_filt                   :    8;  /*when input pulse width is lower than this value, the pulse is ignored.*/
-            uint32_t glitch_filt_en                :    1;  /*Set this bit to enable Rx signal filter.*/
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } rx_filt;
-    union {
-        struct {
-            uint32_t rxfifo_cnt                    :    10;  /*Stores the byte number of valid data in Rx-FIFO.*/
-            uint32_t reserved10                    :    3;
-            uint32_t dsrn                          :    1;  /*The register represent the level value of the internal uart dsr signal.*/
-            uint32_t ctsn                          :    1;  /*This register represent the level value of the internal uart cts signal.*/
-            uint32_t rxd                           :    1;  /*This register represent the  level value of the internal uart rxd signal.*/
-            uint32_t txfifo_cnt                    :    10;  /*Stores the byte number of data in Tx-FIFO.*/
-            uint32_t reserved26                    :    3;  /*Reserved*/
-            uint32_t dtrn                          :    1;  /*This bit represents the level of the internal uart dtr signal.*/
-            uint32_t rtsn                          :    1;  /*This bit represents the level of the internal uart rts signal.*/
-            uint32_t txd                           :    1;  /*This bit represents the  level of the internal uart txd signal.*/
-        };
-        uint32_t val;
-    } status;
-    union {
-        struct {
-            uint32_t parity                        :    1;  /*This register is used to configure the parity check mode.*/
-            uint32_t parity_en                     :    1;  /*Set this bit to enable uart parity check.*/
-            uint32_t bit_num                       :    2;  /*This register is used to set the length of data.*/
-            uint32_t stop_bit_num                  :    2;  /*This register is used to set the length of  stop bit.*/
-            uint32_t sw_rts                        :    1;  /*This register is used to configure the software rts signal which is used in software flow control.*/
-            uint32_t sw_dtr                        :    1;  /*This register is used to configure the software dtr signal which is used in software flow control.*/
-            uint32_t txd_brk                       :    1;  /*Set this bit to enbale transmitter to  send NULL when the process of sending data is done.*/
-            uint32_t irda_dplx                     :    1;  /*Set this bit to enable IrDA loopback mode.*/
-            uint32_t irda_tx_en                    :    1;  /*This is the start enable bit for IrDA transmitter.*/
-            uint32_t irda_wctl                     :    1;  /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
-            uint32_t irda_tx_inv                   :    1;  /*Set this bit to invert the level of  IrDA transmitter.*/
-            uint32_t irda_rx_inv                   :    1;  /*Set this bit to invert the level of IrDA receiver.*/
-            uint32_t loopback                      :    1;  /*Set this bit to enable uart loopback test mode.*/
-            uint32_t tx_flow_en                    :    1;  /*Set this bit to enable flow control function for transmitter.*/
-            uint32_t irda_en                       :    1;  /*Set this bit to enable IrDA protocol.*/
-            uint32_t rxfifo_rst                    :    1;  /*Set this bit to reset the uart receive-FIFO.*/
-            uint32_t txfifo_rst                    :    1;  /*Set this bit to reset the uart transmit-FIFO.*/
-            uint32_t rxd_inv                       :    1;  /*Set this bit to inverse the level value of uart rxd signal.*/
-            uint32_t cts_inv                       :    1;  /*Set this bit to inverse the level value of uart cts signal.*/
-            uint32_t dsr_inv                       :    1;  /*Set this bit to inverse the level value of uart dsr signal.*/
-            uint32_t txd_inv                       :    1;  /*Set this bit to inverse the level value of uart txd signal.*/
-            uint32_t rts_inv                       :    1;  /*Set this bit to inverse the level value of uart rts signal.*/
-            uint32_t dtr_inv                       :    1;  /*Set this bit to inverse the level value of uart dtr signal.*/
-            uint32_t clk_en                        :    1;  /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
-            uint32_t err_wr_mask                   :    1;  /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.*/
-            uint32_t autobaud_en                   :    1;  /*This is the enable bit for detecting baudrate.*/
-            uint32_t mem_clk_en                    :    1;  /*UART memory clock gate enable signal.*/
-            uint32_t reserved29                    :    3;
-        };
-        uint32_t val;
-    } conf0;
-    union {
-        struct {
-            uint32_t rxfifo_full_thrhd             :    9;  /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
-            uint32_t txfifo_empty_thrhd            :    9;  /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
-            uint32_t dis_rx_dat_ovf                :    1;  /*Disable UART Rx data overflow detect. */
-            uint32_t rx_tout_flow_dis              :    1;  /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
-            uint32_t rx_flow_en                    :    1;  /*This is the flow enable bit for UART receiver.*/
-            uint32_t rx_tout_en                    :    1;  /*This is the enble bit for uart receiver's timeout function.*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } conf1;
-    union {
-        struct {
-            uint32_t min_cnt                       :    12;  /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
-            uint32_t reserved12                    :    20;  /*Reserved*/
-        };
-        uint32_t val;
-    } lowpulse;
-    union {
-        struct {
-            uint32_t min_cnt                       :    12;  /*This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
-            uint32_t reserved12                    :    20;  /*Reserved*/
-        };
-        uint32_t val;
-    } highpulse;
-    union {
-        struct {
-            uint32_t edge_cnt                      :    10;  /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
-            uint32_t reserved10                    :    22;  /*Reserved*/
-        };
-        uint32_t val;
-    } rxd_cnt;
-    union {
-        struct {
-            uint32_t sw_flow_con_en                :    1;  /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
-            uint32_t xonoff_del                    :    1;  /*Set this bit to remove flow control char from the received data.*/
-            uint32_t force_xon                     :    1;  /*Set this bit to enable the transmitter to go on sending data.*/
-            uint32_t force_xoff                    :    1;  /*Set this bit to stop the  transmitter from sending data.*/
-            uint32_t send_xon                      :    1;  /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
-            uint32_t send_xoff                     :    1;  /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
-            uint32_t reserved6                     :    26;  /*Reserved*/
-        };
-        uint32_t val;
-    } flow_conf;
-    union {
-        struct {
-            uint32_t active_threshold              :    10;  /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
-            uint32_t reserved10                    :    22;  /*Reserved*/
-        };
-        uint32_t val;
-    } sleep_conf;
-    union {
-        struct {
-            uint32_t xoff_threshold                :    9;  /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/
-            uint32_t xoff_char                     :    8;  /*This register stores the Xoff flow control char.*/
-            uint32_t reserved17                    :    15;  /*Reserved*/
-        };
-        uint32_t val;
-    } swfc_conf0;
-    union {
-        struct {
-            uint32_t xon_threshold                 :    9;  /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/
-            uint32_t xon_char                      :    8;  /*This register stores the Xon flow control char.*/
-            uint32_t reserved17                    :    15;  /*Reserved*/
-        };
-        uint32_t val;
-    } swfc_conf1;
-    union {
-        struct {
-            uint32_t tx_brk_num                    :    8;  /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } txbrk_conf;
-    union {
-        struct {
-            uint32_t rx_idle_thrhd                 :    10;  /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
-            uint32_t tx_idle_num                   :    10;  /*This register is used to configure the duration time between transfers.*/
-            uint32_t reserved20                    :    12;  /*Reserved*/
-        };
-        uint32_t val;
-    } idle_conf;
-    union {
-        struct {
-            uint32_t en                            :    1;  /*Set this bit to choose the rs485 mode.*/
-            uint32_t dl0_en                        :    1;  /*Set this bit to delay the stop bit by 1 bit.*/
-            uint32_t dl1_en                        :    1;  /*Set this bit to delay the stop bit by 1 bit.*/
-            uint32_t tx_rx_en                      :    1;  /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.  */
-            uint32_t rx_busy_tx_en                 :    1;  /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. */
-            uint32_t rx_dly_num                    :    1;  /*This register is used to delay the receiver's internal data signal.*/
-            uint32_t tx_dly_num                    :    4;  /*This register is used to delay the transmitter's internal data signal.*/
-            uint32_t reserved10                    :    22;  /*Reserved*/
-        };
-        uint32_t val;
-    } rs485_conf;
-    union {
-        struct {
-            uint32_t pre_idle_num                  :    16;  /*This register is used to configure the idle duration time before the first at_cmd is received by receiver. */
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_precnt;
-    union {
-        struct {
-            uint32_t post_idle_num                 :    16;  /*This register is used to configure the duration time between the last at_cmd and the next data.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_postcnt;
-    union {
-        struct {
-            uint32_t rx_gap_tout                   :    16;  /*This register is used to configure the duration time between the at_cmd chars.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_gaptout;
-    union {
-        struct {
-            uint32_t data                          :    8;  /*This register is used to configure the content of at_cmd char.*/
-            uint32_t char_num                      :    8;  /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_char;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;
-            uint32_t rx_size                       :    3;  /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
-            uint32_t tx_size                       :    3;  /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
-            uint32_t rx_flow_thrhd                 :    9;  /*This register is used to configure the maximum amount of data that can be received  when hardware flow control works.*/
-            uint32_t rx_tout_thrhd                 :    10;  /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
-            uint32_t force_pd                      :    1;  /*Set this bit to force power down UART memory.*/
-            uint32_t force_pu                      :    1;  /*Set this bit to force power up UART memory.*/
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } mem_conf;
-    union {
-        struct {
-            uint32_t apb_tx_waddr                  :    10;  /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
-            uint32_t reserved10                    :    1;  /*Reserved*/
-            uint32_t tx_raddr                      :    10;  /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } mem_tx_status;
-    union {
-        struct {
-            uint32_t apb_rx_raddr                  :    10;  /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
-            uint32_t reserved10                    :    1;  /*Reserved*/
-            uint32_t rx_waddr                      :    10;  /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
-            uint32_t reserved21                    :    11;  /*Reserved*/
-        };
-        uint32_t val;
-    } mem_rx_status;
-    union {
-        struct {
-            uint32_t st_urx_out                    :    4;  /*This is the status register of receiver.*/
-            uint32_t st_utx_out                    :    4;  /*This is the status register of transmitter.*/
-            uint32_t reserved8                     :    24;  /*Reserved*/
-        };
-        uint32_t val;
-    } fsm_status;
-    union {
-        struct {
-            uint32_t min_cnt                       :    12;  /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
-            uint32_t reserved12                    :    20;  /*Reserved*/
-        };
-        uint32_t val;
-    } pospulse;
-    union {
-        struct {
-            uint32_t min_cnt                       :    12;  /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
-            uint32_t reserved12                    :    20;  /*Reserved*/
-        };
-        uint32_t val;
-    } negpulse;
-    union {
-        struct {
-            uint32_t sclk_div_b                    :    6;  /*The  denominator of the frequency divider factor.*/
-            uint32_t sclk_div_a                    :    6;  /*The numerator of the frequency divider factor.*/
-            uint32_t sclk_div_num                  :    8;  /*The integral part of the frequency divider factor.*/
-            uint32_t sclk_sel                      :    2;  /*UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.*/
-            uint32_t sclk_en                       :    1;  /*Set this bit to enable UART Tx/Rx clock.*/
-            uint32_t rst_core                      :    1;  /*Write 1 then write 0 to this bit, reset UART Tx/Rx.*/
-            uint32_t tx_sclk_en                    :    1;  /*Set this bit to enable UART Tx clock.*/
-            uint32_t rx_sclk_en                    :    1;  /*Set this bit to enable UART Rx clock.*/
-            uint32_t tx_rst_core                   :    1;  /*Write 1 then write 0 to this bit, reset UART Tx.*/
-            uint32_t rx_rst_core                   :    1;  /*Write 1 then write 0 to this bit, reset UART Rx.*/
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } clk_conf;
-    uint32_t date;
-    union {
-        struct {
-            uint32_t id                            :    30;  /*This register is used to configure the uart_id.*/
-            uint32_t high_speed                    :    1;  /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
-            uint32_t update                        :    1;  /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
-        };
-        uint32_t val;
-    } id;
-} uart_dev_t;
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c2/include/soc/xts_aes_reg.h b/components/soc/esp32c2/include/soc/xts_aes_reg.h
deleted file mode 100644
index 9845d0b0582..00000000000
--- a/components/soc/esp32c2/include/soc/xts_aes_reg.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** XTS_AES_PLAIN_MEM register
- *  The memory that stores plaintext
- */
-#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
-#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
-
-/** XTS_AES_LINESIZE_REG register
- *  XTS-AES line-size register
- */
-#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
-/** XTS_AES_LINESIZE : R/W; bitpos: [0]; default: 0;
- *  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
- */
-#define XTS_AES_LINESIZE    (BIT(0))
-#define XTS_AES_LINESIZE_M  (XTS_AES_LINESIZE_V << XTS_AES_LINESIZE_S)
-#define XTS_AES_LINESIZE_V  0x00000001U
-#define XTS_AES_LINESIZE_S  0
-
-/** XTS_AES_DESTINATION_REG register
- *  XTS-AES destination register
- */
-#define XTS_AES_DESTINATION_REG (DR_REG_XTS_AES_BASE + 0x44)
-/** XTS_AES_DESTINATION : R/W; bitpos: [0]; default: 0;
- *  This bit stores the destination. 0: flash(default). 1: reserved.
- */
-#define XTS_AES_DESTINATION    (BIT(0))
-#define XTS_AES_DESTINATION_M  (XTS_AES_DESTINATION_V << XTS_AES_DESTINATION_S)
-#define XTS_AES_DESTINATION_V  0x00000001U
-#define XTS_AES_DESTINATION_S  0
-
-/** XTS_AES_PHYSICAL_ADDRESS_REG register
- *  XTS-AES physical address register
- */
-#define XTS_AES_PHYSICAL_ADDRESS_REG (DR_REG_XTS_AES_BASE + 0x48)
-/** XTS_AES_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0;
- *  Those bits stores the physical address. If linesize is 16-byte, the physical
- *  address should be aligned of 16 bytes. If linesize is 32-byte, the physical address
- *  should be aligned of 32 bytes.
- */
-#define XTS_AES_PHYSICAL_ADDRESS    0x3FFFFFFFU
-#define XTS_AES_PHYSICAL_ADDRESS_M  (XTS_AES_PHYSICAL_ADDRESS_V << XTS_AES_PHYSICAL_ADDRESS_S)
-#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFFFU
-#define XTS_AES_PHYSICAL_ADDRESS_S  0
-
-/** XTS_AES_TRIGGER_REG register
- *  XTS-AES trigger register
- */
-#define XTS_AES_TRIGGER_REG (DR_REG_XTS_AES_BASE + 0x4c)
-/** XTS_AES_TRIGGER : WT; bitpos: [0]; default: 0;
- *  Set this bit to start manual encryption calculation
- */
-#define XTS_AES_TRIGGER    (BIT(0))
-#define XTS_AES_TRIGGER_M  (XTS_AES_TRIGGER_V << XTS_AES_TRIGGER_S)
-#define XTS_AES_TRIGGER_V  0x00000001U
-#define XTS_AES_TRIGGER_S  0
-
-/** XTS_AES_RELEASE_REG register
- *  XTS-AES release register
- */
-#define XTS_AES_RELEASE_REG (DR_REG_XTS_AES_BASE + 0x50)
-/** XTS_AES_RELEASE : WT; bitpos: [0]; default: 0;
- *  Set this bit to release the manual encrypted result, after that the result will be
- *  visible to spi
- */
-#define XTS_AES_RELEASE    (BIT(0))
-#define XTS_AES_RELEASE_M  (XTS_AES_RELEASE_V << XTS_AES_RELEASE_S)
-#define XTS_AES_RELEASE_V  0x00000001U
-#define XTS_AES_RELEASE_S  0
-
-/** XTS_AES_DESTROY_REG register
- *  XTS-AES destroy register
- */
-#define XTS_AES_DESTROY_REG (DR_REG_XTS_AES_BASE + 0x54)
-/** XTS_AES_DESTROY : WT; bitpos: [0]; default: 0;
- *  Set this bit to destroy XTS-AES result.
- */
-#define XTS_AES_DESTROY    (BIT(0))
-#define XTS_AES_DESTROY_M  (XTS_AES_DESTROY_V << XTS_AES_DESTROY_S)
-#define XTS_AES_DESTROY_V  0x00000001U
-#define XTS_AES_DESTROY_S  0
-
-/** XTS_AES_STATE_REG register
- *  XTS-AES status register
- */
-#define XTS_AES_STATE_REG (DR_REG_XTS_AES_BASE + 0x58)
-/** XTS_AES_STATE : RO; bitpos: [1:0]; default: 0;
- *  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that
- *  XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means
- *  the encrypted result is generated but not visible to mspi. USE means that the
- *  encrypted result is visible to mspi.
- */
-#define XTS_AES_STATE    0x00000003U
-#define XTS_AES_STATE_M  (XTS_AES_STATE_V << XTS_AES_STATE_S)
-#define XTS_AES_STATE_V  0x00000003U
-#define XTS_AES_STATE_S  0
-
-/** XTS_AES_DATE_REG register
- *  XTS-AES version control register
- */
-#define XTS_AES_DATE_REG (DR_REG_XTS_AES_BASE + 0x5c)
-/** XTS_AES_DATE : R/W; bitpos: [29:0]; default: 538969635;
- *  Those bits stores the version information of XTS-AES.
- */
-#define XTS_AES_DATE    0x3FFFFFFFU
-#define XTS_AES_DATE_M  (XTS_AES_DATE_V << XTS_AES_DATE_S)
-#define XTS_AES_DATE_V  0x3FFFFFFFU
-#define XTS_AES_DATE_S  0
-
-/* For backward compatability with the older register names */
-#define AES_XTS_PLAIN_BASE          XTS_AES_PLAIN_MEM
-#define AES_XTS_SIZE_REG            XTS_AES_LINESIZE_REG
-#define AES_XTS_DESTINATION_REG     XTS_AES_DESTINATION_REG
-#define AES_XTS_PHYSICAL_ADDR_REG   XTS_AES_PHYSICAL_ADDRESS_REG
-#define AES_XTS_TRIGGER_REG         XTS_AES_TRIGGER_REG
-#define AES_XTS_RELEASE_REG         XTS_AES_RELEASE_REG
-#define AES_XTS_DESTROY_REG         XTS_AES_DESTROY_REG
-#define AES_XTS_STATE_REG           XTS_AES_STATE_REG
-#define AES_XTS_DATE_REG            XTS_AES_DATE_REG
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c2/include/soc/apb_saradc_reg.h b/components/soc/esp32c2/register/soc/apb_saradc_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/apb_saradc_reg.h
rename to components/soc/esp32c2/register/soc/apb_saradc_reg.h
diff --git a/components/soc/esp32c2/include/soc/apb_saradc_struct.h b/components/soc/esp32c2/register/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/apb_saradc_struct.h
rename to components/soc/esp32c2/register/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32c2/register/soc/assist_debug_reg.h b/components/soc/esp32c2/register/soc/assist_debug_reg.h
new file mode 100644
index 00000000000..bee2070557c
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/assist_debug_reg.h
@@ -0,0 +1,225 @@
+/**
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [0]; default: 0;
+ *  enable sp underflow monitor
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [1]; default: 0;
+ *  enable sp overflow monitor
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  1
+
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [0]; default: 0;
+ *  sp underflow monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [1]; default: 0;
+ *  sp overflow monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  1
+
+/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [0]; default: 0;
+ *  enable sp underflow monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  0
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [1]; default: 0;
+ *  enable sp overflow monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  1
+
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [0]; default: 0;
+ *  clr sp underflow monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [1]; default: 0;
+ *  clr sp overflow monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  1
+
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core0 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core0 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CLOCK_GATE_REG register
+ *  clock gate register
+ */
+#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  clock gate register
+ */
+#define ASSIST_DEBUG_CLK_EN    (BIT(0))
+#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
+#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
+#define ASSIST_DEBUG_CLK_EN_S  0
+
+/** ASSIST_DEBUG_DATE_REG register
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc)
+/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34627616;
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/register/soc/ecc_mult_reg.h b/components/soc/esp32c2/register/soc/ecc_mult_reg.h
new file mode 100644
index 00000000000..cb4bf5797b9
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/ecc_mult_reg.h
@@ -0,0 +1,292 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ECC_MULT_INT_RAW_REG          (DR_REG_ECC_MULT_BASE + 0xC)
+/* ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt.*/
+#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x1
+#define ECC_MULT_CALC_DONE_INT_RAW_S  0
+
+#define ECC_MULT_INT_ST_REG          (DR_REG_ECC_MULT_BASE + 0x10)
+/* ECC_MULT_CALC_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_done_int interrupt.*/
+#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_M  (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x1
+#define ECC_MULT_CALC_DONE_INT_ST_S  0
+
+#define ECC_MULT_INT_ENA_REG          (DR_REG_ECC_MULT_BASE + 0x14)
+/* ECC_MULT_CALC_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_done_int interrupt.*/
+#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x1
+#define ECC_MULT_CALC_DONE_INT_ENA_S  0
+
+#define ECC_MULT_INT_CLR_REG          (DR_REG_ECC_MULT_BASE + 0x18)
+/* ECC_MULT_CALC_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_done_int interrupt.*/
+#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x1
+#define ECC_MULT_CALC_DONE_INT_CLR_S  0
+
+#define ECC_MULT_CONF_REG          (DR_REG_ECC_MULT_BASE + 0x1C)
+/* ECC_MULT_VERIFICATION_RESULT : RO/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Reserve.*/
+#define ECC_MULT_VERIFICATION_RESULT    (BIT(8))
+#define ECC_MULT_VERIFICATION_RESULT_M  (BIT(8))
+#define ECC_MULT_VERIFICATION_RESULT_V  0x1
+#define ECC_MULT_VERIFICATION_RESULT_S  8
+/* ECC_MULT_WORK_MODE : R/W ;bitpos:[7:5] ;default: 3'b0 ; */
+/*description:  Reserved.*/
+#define ECC_MULT_WORK_MODE    0x00000007
+#define ECC_MULT_WORK_MODE_M  ((ECC_MULT_WORK_MODE_V)<<(ECC_MULT_WORK_MODE_S))
+#define ECC_MULT_WORK_MODE_V  0x7
+#define ECC_MULT_WORK_MODE_S  5
+/* ECC_MULT_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: clk gate.*/
+#define ECC_MULT_CLK_EN    (BIT(4))
+#define ECC_MULT_CLK_EN_M  (BIT(4))
+#define ECC_MULT_CLK_EN_V  0x1
+#define ECC_MULT_CLK_EN_S  4
+/* ECC_MULT_SECURITY_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave receiver mode.*/
+#define ECC_MULT_SECURITY_MODE    (BIT(3))
+#define ECC_MULT_SECURITY_MODE_M  (BIT(3))
+#define ECC_MULT_SECURITY_MODE_V  0x1
+#define ECC_MULT_SECURITY_MODE_S  3
+/* ECC_MULT_KEY_LENGTH : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to start receiving data.*/
+#define ECC_MULT_KEY_LENGTH    (BIT(2))
+#define ECC_MULT_KEY_LENGTH_M  (BIT(2))
+#define ECC_MULT_KEY_LENGTH_V  0x1
+#define ECC_MULT_KEY_LENGTH_S  2
+/* ECC_MULT_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset Rx AFIFO.*/
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (BIT(1))
+#define ECC_MULT_RESET_V  0x1
+#define ECC_MULT_RESET_S  1
+/* ECC_MULT_START : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to reset receiver.*/
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (BIT(0))
+#define ECC_MULT_START_V  0x1
+#define ECC_MULT_START_S  0
+
+#define ECC_MULT_DATE_REG          (DR_REG_ECC_MULT_BASE + 0xFC)
+/* ECC_MULT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012230 ; */
+/*description: ECC mult version control register.*/
+#define ECC_MULT_DATE    0x0FFFFFFF
+#define ECC_MULT_DATE_M  ((ECC_MULT_DATE_V)<<(ECC_MULT_DATE_S))
+#define ECC_MULT_DATE_V  0xFFFFFFF
+#define ECC_MULT_DATE_S  0
+
+#define ECC_MULT_K_1_REG          (DR_REG_ECC_MULT_BASE + 0x0100)
+/* ECC_MULT_MEM_K_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_1  0xFFFFFFFF
+#define ECC_MULT_MEM_K_1_M  ((ECC_MULT_MEM_K_1_V)<<(ECC_MULT_MEM_K_1_S))
+#define ECC_MULT_MEM_K_1_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_1_S  0
+
+#define ECC_MULT_K_2_REG          (DR_REG_ECC_MULT_BASE + 0x0104)
+/* ECC_MULT_MEM_K_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_2  0xFFFFFFFF
+#define ECC_MULT_MEM_K_2_M  ((ECC_MULT_MEM_K_2_V)<<(ECC_MULT_MEM_K_2_S))
+#define ECC_MULT_MEM_K_2_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_2_S  0
+
+#define ECC_MULT_K_3_REG          (DR_REG_ECC_MULT_BASE + 0x0108)
+/* ECC_MULT_MEM_K_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_3  0xFFFFFFFF
+#define ECC_MULT_MEM_K_3_M  ((ECC_MULT_MEM_K_3_V)<<(ECC_MULT_MEM_K_3_S))
+#define ECC_MULT_MEM_K_3_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_3_S  0
+
+#define ECC_MULT_K_4_REG          (DR_REG_ECC_MULT_BASE + 0x010c)
+/* ECC_MULT_MEM_K_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_4  0xFFFFFFFF
+#define ECC_MULT_MEM_K_4_M  ((ECC_MULT_MEM_K_4_V)<<(ECC_MULT_MEM_K_4_S))
+#define ECC_MULT_MEM_K_4_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_4_S  0
+
+#define ECC_MULT_K_5_REG          (DR_REG_ECC_MULT_BASE + 0x0110)
+/* ECC_MULT_MEM_K_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_5  0xFFFFFFFF
+#define ECC_MULT_MEM_K_5_M  ((ECC_MULT_MEM_K_5_V)<<(ECC_MULT_MEM_K_5_S))
+#define ECC_MULT_MEM_K_5_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_5_S  0
+
+#define ECC_MULT_K_6_REG          (DR_REG_ECC_MULT_BASE + 0x0114)
+/* ECC_MULT_MEM_K_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_6  0xFFFFFFFF
+#define ECC_MULT_MEM_K_6_M  ((ECC_MULT_MEM_K_6_V)<<(ECC_MULT_MEM_K_6_S))
+#define ECC_MULT_MEM_K_6_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_6_S  0
+
+#define ECC_MULT_K_7_REG          (DR_REG_ECC_MULT_BASE + 0x0118)
+/* ECC_MULT_MEM_K_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_7  0xFFFFFFFF
+#define ECC_MULT_MEM_K_7_M  ((ECC_MULT_MEM_K_7_V)<<(ECC_MULT_MEM_K_7_S))
+#define ECC_MULT_MEM_K_7_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_7_S  0
+
+#define ECC_MULT_K_8_REG          (DR_REG_ECC_MULT_BASE + 0x011c)
+/* ECC_MULT_MEM_K_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter k.*/
+#define ECC_MULT_MEM_K_8  0xFFFFFFFF
+#define ECC_MULT_MEM_K_8_M  ((ECC_MULT_MEM_K_8_V)<<(ECC_MULT_MEM_K_8_S))
+#define ECC_MULT_MEM_K_8_V  0xFFFFFFFF
+#define ECC_MULT_MEM_K_8_S  0
+
+#define ECC_MULT_PX_1_REG          (DR_REG_ECC_MULT_BASE + 0x0120)
+/* ECC_MULT_MEM_PX_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_1  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_1_M  ((ECC_MULT_MEM_PX_1_V)<<(ECC_MULT_MEM_PX_1_S))
+#define ECC_MULT_MEM_PX_1_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_1_S  0
+
+#define ECC_MULT_PX_2_REG          (DR_REG_ECC_MULT_BASE + 0x0124)
+/* ECC_MULT_MEM_PX_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_2  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_2_M  ((ECC_MULT_MEM_PX_2_V)<<(ECC_MULT_MEM_PX_2_S))
+#define ECC_MULT_MEM_PX_2_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_2_S  0
+
+#define ECC_MULT_PX_3_REG          (DR_REG_ECC_MULT_BASE + 0x0128)
+/* ECC_MULT_MEM_PX_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_3  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_3_M  ((ECC_MULT_MEM_PX_3_V)<<(ECC_MULT_MEM_PX_3_S))
+#define ECC_MULT_MEM_PX_3_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_3_S  0
+
+#define ECC_MULT_PX_4_REG          (DR_REG_ECC_MULT_BASE + 0x012c)
+/* ECC_MULT_MEM_PX_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_4  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_4_M  ((ECC_MULT_MEM_PX_4_V)<<(ECC_MULT_MEM_PX_4_S))
+#define ECC_MULT_MEM_PX_4_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_4_S  0
+
+#define ECC_MULT_PX_5_REG          (DR_REG_ECC_MULT_BASE + 0x0130)
+/* ECC_MULT_MEM_PX_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_5  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_5_M  ((ECC_MULT_MEM_PX_5_V)<<(ECC_MULT_MEM_PX_5_S))
+#define ECC_MULT_MEM_PX_5_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_5_S  0
+
+#define ECC_MULT_PX_6_REG          (DR_REG_ECC_MULT_BASE + 0x0134)
+/* ECC_MULT_MEM_PX_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_6  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_6_M  ((ECC_MULT_MEM_PX_6_V)<<(ECC_MULT_MEM_PX_6_S))
+#define ECC_MULT_MEM_PX_6_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_6_S  0
+
+#define ECC_MULT_PX_7_REG          (DR_REG_ECC_MULT_BASE + 0x0138)
+/* ECC_MULT_MEM_PX_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_7  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_7_M  ((ECC_MULT_MEM_PX_7_V)<<(ECC_MULT_MEM_PX_7_S))
+#define ECC_MULT_MEM_PX_7_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_7_S  0
+
+#define ECC_MULT_PX_8_REG          (DR_REG_ECC_MULT_BASE + 0x013c)
+/* ECC_MULT_MEM_PX_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Px.*/
+#define ECC_MULT_MEM_PX_8  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_8_M  ((ECC_MULT_MEM_PX_8_V)<<(ECC_MULT_MEM_PX_8_S))
+#define ECC_MULT_MEM_PX_8_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PX_8_S  0
+
+#define ECC_MULT_PY_1_REG          (DR_REG_ECC_MULT_BASE + 0x0140)
+/* ECC_MULT_MEM_PY_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_1  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_1_M  ((ECC_MULT_MEM_PY_1_V)<<(ECC_MULT_MEM_PY_1_S))
+#define ECC_MULT_MEM_PY_1_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_1_S  0
+
+#define ECC_MULT_PY_2_REG          (DR_REG_ECC_MULT_BASE + 0x0144)
+/* ECC_MULT_MEM_PY_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_2  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_2_M  ((ECC_MULT_MEM_PY_2_V)<<(ECC_MULT_MEM_PY_2_S))
+#define ECC_MULT_MEM_PY_2_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_2_S  0
+
+#define ECC_MULT_PY_3_REG          (DR_REG_ECC_MULT_BASE + 0x0148)
+/* ECC_MULT_MEM_PY_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_3  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_3_M  ((ECC_MULT_MEM_PY_3_V)<<(ECC_MULT_MEM_PY_3_S))
+#define ECC_MULT_MEM_PY_3_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_3_S  0
+
+#define ECC_MULT_PY_4_REG          (DR_REG_ECC_MULT_BASE + 0x014c)
+/* ECC_MULT_MEM_PY_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_4  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_4_M  ((ECC_MULT_MEM_PY_4_V)<<(ECC_MULT_MEM_PY_4_S))
+#define ECC_MULT_MEM_PY_4_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_4_S  0
+
+#define ECC_MULT_PY_5_REG          (DR_REG_ECC_MULT_BASE + 0x0150)
+/* ECC_MULT_MEM_PY_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_5  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_5_M  ((ECC_MULT_MEM_PY_5_V)<<(ECC_MULT_MEM_PY_5_S))
+#define ECC_MULT_MEM_PY_5_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_5_S  0
+
+#define ECC_MULT_PY_6_REG          (DR_REG_ECC_MULT_BASE + 0x0154)
+/* ECC_MULT_MEM_PY_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_6  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_6_M  ((ECC_MULT_MEM_PY_6_V)<<(ECC_MULT_MEM_PY_6_S))
+#define ECC_MULT_MEM_PY_6_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_6_S  0
+
+#define ECC_MULT_PY_7_REG          (DR_REG_ECC_MULT_BASE + 0x0158)
+/* ECC_MULT_MEM_PY_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_7  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_7_M  ((ECC_MULT_MEM_PY_7_V)<<(ECC_MULT_MEM_PY_7_S))
+#define ECC_MULT_MEM_PY_7_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_7_S  0
+
+#define ECC_MULT_PY_8_REG          (DR_REG_ECC_MULT_BASE + 0x015c)
+/* ECC_MULT_MEM_PY_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: ECC Mem Parameter Py.*/
+#define ECC_MULT_MEM_PY_8  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_8_M  ((ECC_MULT_MEM_PY_8_V)<<(ECC_MULT_MEM_PY_8_S))
+#define ECC_MULT_MEM_PY_8_V  0xFFFFFFFF
+#define ECC_MULT_MEM_PY_8_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/register/soc/efuse_reg.h b/components/soc/esp32c2/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..8471fef930a
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/efuse_reg.h
@@ -0,0 +1,1211 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/efuse_defs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [7:0]; default: 0;
+ *  Disable programming of individual eFuses.
+ */
+#define EFUSE_WR_DIS    0x000000FFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0x000000FFU
+#define EFUSE_WR_DIS_S  0
+/** EFUSE_RESERVED_0_8 : RW; bitpos: [31:8]; default: 0; */
+#define EFUSE_RESERVED_0_8    0x00FFFFFFU
+#define EFUSE_RESERVED_0_8_M  (EFUSE_RESERVED_0_8_V << EFUSE_RESERVED_0_8_S)
+#define EFUSE_RESERVED_0_8_V  0x00FFFFFFU
+#define EFUSE_RESERVED_0_8_S  8
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [1:0]; default: 0;
+ *  The bit be set to disable software read high/low 128-bit of BLK3.
+ */
+#define EFUSE_RD_DIS    0x00000003U
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x00000003U
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [3:2]; default: 0;
+ *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
+ *  80000. 2: 160000. 3:320000.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  2
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [4]; default: 0;
+ *  Set this bit to disable pad jtag.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(4))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  4
+/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [5]; default: 0;
+ *  The bit be set to disable icache in download mode.
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(5))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  5
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [6]; default: 0;
+ *  The bit be set to disable manual encryption.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(6))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  6
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [9:7]; default: 0;
+ *  These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+ *  number of 1: disable.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  7
+/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [10]; default: 0;
+ *  The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise,
+ *  XTS_AES use 128-bit eFuse data in BLOCK3.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256    (BIT(10))
+#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
+#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_S  10
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [12:11]; default: 0;
+ *  Set this bit to disable usb printing.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  11
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
+ *  Set this bit to force ROM code to send a resume command during SPI boot.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [14]; default: 0;
+ *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(14))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  14
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [15]; default: 0;
+ *  This bit set means disable direct_boot mode.
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(15))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  15
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [16]; default: 0;
+ *  Set this bit to enable secure UART download mode.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(16))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  16
+/** EFUSE_FLASH_TPUW : RO; bitpos: [20:17]; default: 0;
+ *  Configures flash waiting time after power-up, in unit of ms. If the value is less
+ *  than 15, the waiting time is the configurable value.  Otherwise, the waiting time
+ *  is twice the configurable value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  17
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [21]; default: 0;
+ *  The bit be set to enable secure boot.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(21))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  21
+/** EFUSE_SECURE_VERSION : R; bitpos: [25:22]; default: 0;
+ *  Secure version for anti-rollback
+ */
+#define EFUSE_SECURE_VERSION    0x0000000FU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000000FU
+#define EFUSE_SECURE_VERSION_S  22
+/** EFUSE_CUSTOM_MAC_USED : R; bitpos: [26]; default: 0;
+ *  True if MAC_CUSTOM is burned
+ */
+#define EFUSE_CUSTOM_MAC_USED    (BIT(26))
+#define EFUSE_CUSTOM_MAC_USED_M  (EFUSE_CUSTOM_MAC_USED_V << EFUSE_CUSTOM_MAC_USED_S)
+#define EFUSE_CUSTOM_MAC_USED_V  0x00000001U
+#define EFUSE_CUSTOM_MAC_USED_S  26
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [27]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(27))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  27
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [28]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(28))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  28
+/** EFUSE_RESERVED_0_61 : R; bitpos: [31:29]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_0_61    0x00000007U
+#define EFUSE_RESERVED_0_61_M  (EFUSE_RESERVED_0_61_V << EFUSE_RESERVED_0_61_S)
+#define EFUSE_RESERVED_0_61_V  0x00000007U
+#define EFUSE_RESERVED_0_61_S  29
+
+/** EFUSE_RD_BLK1_DATA0_REG register
+ *  BLOCK1 data register 0.
+ */
+#define EFUSE_RD_BLK1_DATA0_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:0]; default: 0;
+ *  Custom MAC address
+ */
+#define EFUSE_CUSTOM_MAC    0xFFFFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0xFFFFFFFFU
+#define EFUSE_CUSTOM_MAC_S  0
+
+/** EFUSE_RD_BLK1_DATA1_REG register
+ *  BLOCK1 data register 1.
+ */
+#define EFUSE_RD_BLK1_DATA1_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [15:0]; default: 0;
+ *  Custom MAC address
+ */
+#define EFUSE_CUSTOM_MAC_1    0x0000FFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x0000FFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_1_48 : R; bitpos: [31:16]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_48    0x0000FFFFU
+#define EFUSE_RESERVED_1_48_M  (EFUSE_RESERVED_1_48_V << EFUSE_RESERVED_1_48_S)
+#define EFUSE_RESERVED_1_48_V  0x0000FFFFU
+#define EFUSE_RESERVED_1_48_S  16
+
+/** EFUSE_RD_BLK1_DATA2_REG register
+ *  BLOCK1 data register 2.
+ */
+#define EFUSE_RD_BLK1_DATA2_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_SYSTEM_DATA2 : RO; bitpos: [23:0]; default: 0;
+ *  Stores the bits [64:87] of system data.
+ */
+#define EFUSE_SYSTEM_DATA2    0x00FFFFFFU
+#define EFUSE_SYSTEM_DATA2_M  (EFUSE_SYSTEM_DATA2_V << EFUSE_SYSTEM_DATA2_S)
+#define EFUSE_SYSTEM_DATA2_V  0x00FFFFFFU
+#define EFUSE_SYSTEM_DATA2_S  0
+
+/** EFUSE_RD_BLK2_DATA0_REG register
+ *  Register 0 of BLOCK2.
+ */
+#define EFUSE_RD_BLK2_DATA0_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_MAC : R; bitpos: [31:0]; default: 0;
+ *  MAC address
+ */
+#define EFUSE_MAC    0xFFFFFFFFU
+#define EFUSE_MAC_M  (EFUSE_MAC_V << EFUSE_MAC_S)
+#define EFUSE_MAC_V  0xFFFFFFFFU
+#define EFUSE_MAC_S  0
+
+/** EFUSE_RD_BLK2_DATA1_REG register
+ *  Register 1 of BLOCK2.
+ */
+#define EFUSE_RD_BLK2_DATA1_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_1 : R; bitpos: [15:0]; default: 0;
+ *  MAC address
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [19:16]; default: 0;
+ *  WAFER_VERSION_MINOR
+ */
+#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_S  16
+/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [21:20]; default: 0;
+ *  WAFER_VERSION_MAJOR
+ */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  20
+/** EFUSE_PKG_VERSION : R; bitpos: [24:22]; default: 0;
+ *  EFUSE_PKG_VERSION
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  22
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [27:25]; default: 0;
+ *  Minor version of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  25
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [29:28]; default: 0;
+ *  Major version of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  28
+/** EFUSE_OCODE : R; bitpos: [31:30]; default: 0;
+ *  OCode
+ */
+#define EFUSE_OCODE    0x00000003U
+#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
+#define EFUSE_OCODE_V  0x00000003U
+#define EFUSE_OCODE_S  30
+
+/** EFUSE_RD_BLK2_DATA2_REG register
+ *  Register 2 of BLOCK2.
+ */
+#define EFUSE_RD_BLK2_DATA2_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_OCODE_1 : R; bitpos: [4:0]; default: 0;
+ *  OCode
+ */
+#define EFUSE_OCODE_1    0x0000001FU
+#define EFUSE_OCODE_1_M  (EFUSE_OCODE_1_V << EFUSE_OCODE_1_S)
+#define EFUSE_OCODE_1_V  0x0000001FU
+#define EFUSE_OCODE_1_S  0
+/** EFUSE_TEMP_CALIB : R; bitpos: [13:5]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMP_CALIB    0x000001FFU
+#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
+#define EFUSE_TEMP_CALIB_V  0x000001FFU
+#define EFUSE_TEMP_CALIB_S  5
+/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [21:14]; default: 0;
+ *  ADC1 init code at atten0
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0    0x000000FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_V  0x000000FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_S  14
+/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [26:22]; default: 0;
+ *  ADC1 init code at atten3
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN3    0x0000001FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_V  0x0000001FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_S  22
+/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:27]; default: 0;
+ *  ADC1 calibration voltage at atten0
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN0    0x0000001FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_V  0x0000001FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_S  27
+
+/** EFUSE_RD_BLK2_DATA3_REG register
+ *  Register 3 of BLOCK2.
+ */
+#define EFUSE_RD_BLK2_DATA3_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
+ *  ADC1 calibration voltage at atten0
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1    0x00000007U
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V  0x00000007U
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S  0
+/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:3]; default: 0;
+ *  ADC1 calibration voltage at atten3
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN3    0x0000003FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_V  0x0000003FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_S  3
+/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [13:9]; default: 0;
+ *  BLOCK2 digital dbias when hvt
+ */
+#define EFUSE_DIG_DBIAS_HVT    0x0000001FU
+#define EFUSE_DIG_DBIAS_HVT_M  (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
+#define EFUSE_DIG_DBIAS_HVT_V  0x0000001FU
+#define EFUSE_DIG_DBIAS_HVT_S  9
+/** EFUSE_DIG_LDO_SLP_DBIAS2 : R; bitpos: [20:14]; default: 0;
+ *  BLOCK2 DIG_LDO_DBG0_DBIAS2
+ */
+#define EFUSE_DIG_LDO_SLP_DBIAS2    0x0000007FU
+#define EFUSE_DIG_LDO_SLP_DBIAS2_M  (EFUSE_DIG_LDO_SLP_DBIAS2_V << EFUSE_DIG_LDO_SLP_DBIAS2_S)
+#define EFUSE_DIG_LDO_SLP_DBIAS2_V  0x0000007FU
+#define EFUSE_DIG_LDO_SLP_DBIAS2_S  14
+/** EFUSE_DIG_LDO_SLP_DBIAS26 : R; bitpos: [28:21]; default: 0;
+ *  BLOCK2 DIG_LDO_DBG0_DBIAS26
+ */
+#define EFUSE_DIG_LDO_SLP_DBIAS26    0x000000FFU
+#define EFUSE_DIG_LDO_SLP_DBIAS26_M  (EFUSE_DIG_LDO_SLP_DBIAS26_V << EFUSE_DIG_LDO_SLP_DBIAS26_S)
+#define EFUSE_DIG_LDO_SLP_DBIAS26_V  0x000000FFU
+#define EFUSE_DIG_LDO_SLP_DBIAS26_S  21
+/** EFUSE_DIG_LDO_ACT_DBIAS26 : R; bitpos: [31:29]; default: 0;
+ *  BLOCK2 DIG_LDO_ACT_DBIAS26
+ */
+#define EFUSE_DIG_LDO_ACT_DBIAS26    0x00000007U
+#define EFUSE_DIG_LDO_ACT_DBIAS26_M  (EFUSE_DIG_LDO_ACT_DBIAS26_V << EFUSE_DIG_LDO_ACT_DBIAS26_S)
+#define EFUSE_DIG_LDO_ACT_DBIAS26_V  0x00000007U
+#define EFUSE_DIG_LDO_ACT_DBIAS26_S  29
+
+/** EFUSE_RD_BLK2_DATA4_REG register
+ *  Register 4 of BLOCK2.
+ */
+#define EFUSE_RD_BLK2_DATA4_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_DIG_LDO_ACT_DBIAS26_1 : R; bitpos: [2:0]; default: 0;
+ *  BLOCK2 DIG_LDO_ACT_DBIAS26
+ */
+#define EFUSE_DIG_LDO_ACT_DBIAS26_1    0x00000007U
+#define EFUSE_DIG_LDO_ACT_DBIAS26_1_M  (EFUSE_DIG_LDO_ACT_DBIAS26_1_V << EFUSE_DIG_LDO_ACT_DBIAS26_1_S)
+#define EFUSE_DIG_LDO_ACT_DBIAS26_1_V  0x00000007U
+#define EFUSE_DIG_LDO_ACT_DBIAS26_1_S  0
+/** EFUSE_DIG_LDO_ACT_STEPD10 : R; bitpos: [6:3]; default: 0;
+ *  BLOCK2 DIG_LDO_ACT_STEPD10
+ */
+#define EFUSE_DIG_LDO_ACT_STEPD10    0x0000000FU
+#define EFUSE_DIG_LDO_ACT_STEPD10_M  (EFUSE_DIG_LDO_ACT_STEPD10_V << EFUSE_DIG_LDO_ACT_STEPD10_S)
+#define EFUSE_DIG_LDO_ACT_STEPD10_V  0x0000000FU
+#define EFUSE_DIG_LDO_ACT_STEPD10_S  3
+/** EFUSE_RTC_LDO_SLP_DBIAS13 : R; bitpos: [13:7]; default: 0;
+ *  BLOCK2 DIG_LDO_SLP_DBIAS13
+ */
+#define EFUSE_RTC_LDO_SLP_DBIAS13    0x0000007FU
+#define EFUSE_RTC_LDO_SLP_DBIAS13_M  (EFUSE_RTC_LDO_SLP_DBIAS13_V << EFUSE_RTC_LDO_SLP_DBIAS13_S)
+#define EFUSE_RTC_LDO_SLP_DBIAS13_V  0x0000007FU
+#define EFUSE_RTC_LDO_SLP_DBIAS13_S  7
+/** EFUSE_RTC_LDO_SLP_DBIAS29 : R; bitpos: [22:14]; default: 0;
+ *  BLOCK2 DIG_LDO_SLP_DBIAS29
+ */
+#define EFUSE_RTC_LDO_SLP_DBIAS29    0x000001FFU
+#define EFUSE_RTC_LDO_SLP_DBIAS29_M  (EFUSE_RTC_LDO_SLP_DBIAS29_V << EFUSE_RTC_LDO_SLP_DBIAS29_S)
+#define EFUSE_RTC_LDO_SLP_DBIAS29_V  0x000001FFU
+#define EFUSE_RTC_LDO_SLP_DBIAS29_S  14
+/** EFUSE_RTC_LDO_SLP_DBIAS31 : R; bitpos: [28:23]; default: 0;
+ *  BLOCK2 DIG_LDO_SLP_DBIAS31
+ */
+#define EFUSE_RTC_LDO_SLP_DBIAS31    0x0000003FU
+#define EFUSE_RTC_LDO_SLP_DBIAS31_M  (EFUSE_RTC_LDO_SLP_DBIAS31_V << EFUSE_RTC_LDO_SLP_DBIAS31_S)
+#define EFUSE_RTC_LDO_SLP_DBIAS31_V  0x0000003FU
+#define EFUSE_RTC_LDO_SLP_DBIAS31_S  23
+/** EFUSE_RTC_LDO_ACT_DBIAS31 : R; bitpos: [31:29]; default: 0;
+ *  BLOCK2 DIG_LDO_ACT_DBIAS31
+ */
+#define EFUSE_RTC_LDO_ACT_DBIAS31    0x00000007U
+#define EFUSE_RTC_LDO_ACT_DBIAS31_M  (EFUSE_RTC_LDO_ACT_DBIAS31_V << EFUSE_RTC_LDO_ACT_DBIAS31_S)
+#define EFUSE_RTC_LDO_ACT_DBIAS31_V  0x00000007U
+#define EFUSE_RTC_LDO_ACT_DBIAS31_S  29
+
+/** EFUSE_RD_BLK2_DATA5_REG register
+ *  Register 5 of BLOCK2.
+ */
+#define EFUSE_RD_BLK2_DATA5_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_RTC_LDO_ACT_DBIAS31_1 : R; bitpos: [2:0]; default: 0;
+ *  BLOCK2 DIG_LDO_ACT_DBIAS31
+ */
+#define EFUSE_RTC_LDO_ACT_DBIAS31_1    0x00000007U
+#define EFUSE_RTC_LDO_ACT_DBIAS31_1_M  (EFUSE_RTC_LDO_ACT_DBIAS31_1_V << EFUSE_RTC_LDO_ACT_DBIAS31_1_S)
+#define EFUSE_RTC_LDO_ACT_DBIAS31_1_V  0x00000007U
+#define EFUSE_RTC_LDO_ACT_DBIAS31_1_S  0
+/** EFUSE_RTC_LDO_ACT_DBIAS13 : R; bitpos: [10:3]; default: 0;
+ *  BLOCK2 DIG_LDO_ACT_DBIAS13
+ */
+#define EFUSE_RTC_LDO_ACT_DBIAS13    0x000000FFU
+#define EFUSE_RTC_LDO_ACT_DBIAS13_M  (EFUSE_RTC_LDO_ACT_DBIAS13_V << EFUSE_RTC_LDO_ACT_DBIAS13_S)
+#define EFUSE_RTC_LDO_ACT_DBIAS13_V  0x000000FFU
+#define EFUSE_RTC_LDO_ACT_DBIAS13_S  3
+/** EFUSE_RESERVED_2_171 : R; bitpos: [31:11]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_171    0x001FFFFFU
+#define EFUSE_RESERVED_2_171_M  (EFUSE_RESERVED_2_171_V << EFUSE_RESERVED_2_171_S)
+#define EFUSE_RESERVED_2_171_V  0x001FFFFFU
+#define EFUSE_RESERVED_2_171_S  11
+
+/** EFUSE_RD_BLK2_DATA6_REG register
+ *  Register 6 of BLOCK2.
+ */
+#define EFUSE_RD_BLK2_DATA6_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_ADC_CALIBRATION_3 : RO; bitpos: [10:0]; default: 0;
+ *  Store the bit [86:96] of ADC calibration data.
+ */
+#define EFUSE_ADC_CALIBRATION_3    0x000007FFU
+#define EFUSE_ADC_CALIBRATION_3_M  (EFUSE_ADC_CALIBRATION_3_V << EFUSE_ADC_CALIBRATION_3_S)
+#define EFUSE_ADC_CALIBRATION_3_V  0x000007FFU
+#define EFUSE_ADC_CALIBRATION_3_S  0
+/** EFUSE_BLK2_RESERVED_DATA_0 : RO; bitpos: [31:11]; default: 0;
+ *  Store the bit [0:20] of block2 reserved data.
+ */
+#define EFUSE_BLK2_RESERVED_DATA_0    0x001FFFFFU
+#define EFUSE_BLK2_RESERVED_DATA_0_M  (EFUSE_BLK2_RESERVED_DATA_0_V << EFUSE_BLK2_RESERVED_DATA_0_S)
+#define EFUSE_BLK2_RESERVED_DATA_0_V  0x001FFFFFU
+#define EFUSE_BLK2_RESERVED_DATA_0_S  11
+
+/** EFUSE_RD_BLK2_DATA7_REG register
+ *  Register 7 of BLOCK2.
+ */
+#define EFUSE_RD_BLK2_DATA7_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_BLK2_RESERVED_DATA_1 : RO; bitpos: [31:0]; default: 0;
+ *  Store the bit [21:52] of block2 reserved data.
+ */
+#define EFUSE_BLK2_RESERVED_DATA_1    0xFFFFFFFFU
+#define EFUSE_BLK2_RESERVED_DATA_1_M  (EFUSE_BLK2_RESERVED_DATA_1_V << EFUSE_BLK2_RESERVED_DATA_1_S)
+#define EFUSE_BLK2_RESERVED_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_BLK2_RESERVED_DATA_1_S  0
+
+/** EFUSE_RD_BLK3_DATA0_REG register
+ *  Register 0 of BLOCK3.
+ */
+#define EFUSE_RD_BLK3_DATA0_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_BLK3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Store the first 32-bit of Block3.
+ */
+#define EFUSE_BLK3_DATA0    0xFFFFFFFFU
+#define EFUSE_BLK3_DATA0_M  (EFUSE_BLK3_DATA0_V << EFUSE_BLK3_DATA0_S)
+#define EFUSE_BLK3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_BLK3_DATA0_S  0
+
+/** EFUSE_RD_BLK3_DATA1_REG register
+ *  Register 1 of BLOCK3.
+ */
+#define EFUSE_RD_BLK3_DATA1_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_BLK3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Store the second 32-bit of Block3.
+ */
+#define EFUSE_BLK3_DATA1    0xFFFFFFFFU
+#define EFUSE_BLK3_DATA1_M  (EFUSE_BLK3_DATA1_V << EFUSE_BLK3_DATA1_S)
+#define EFUSE_BLK3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_BLK3_DATA1_S  0
+
+/** EFUSE_RD_BLK3_DATA2_REG register
+ *  Register 2 of BLOCK3.
+ */
+#define EFUSE_RD_BLK3_DATA2_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_BLK3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Store the third 32-bit of Block3.
+ */
+#define EFUSE_BLK3_DATA2    0xFFFFFFFFU
+#define EFUSE_BLK3_DATA2_M  (EFUSE_BLK3_DATA2_V << EFUSE_BLK3_DATA2_S)
+#define EFUSE_BLK3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_BLK3_DATA2_S  0
+
+/** EFUSE_RD_BLK3_DATA3_REG register
+ *  Register 3 of BLOCK3.
+ */
+#define EFUSE_RD_BLK3_DATA3_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_BLK3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Store the fourth 32-bit of Block3.
+ */
+#define EFUSE_BLK3_DATA3    0xFFFFFFFFU
+#define EFUSE_BLK3_DATA3_M  (EFUSE_BLK3_DATA3_V << EFUSE_BLK3_DATA3_S)
+#define EFUSE_BLK3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_BLK3_DATA3_S  0
+
+/** EFUSE_RD_BLK3_DATA4_REG register
+ *  Register 4 of BLOCK3.
+ */
+#define EFUSE_RD_BLK3_DATA4_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_BLK3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Store the fifth 32-bit of Block3.
+ */
+#define EFUSE_BLK3_DATA4    0xFFFFFFFFU
+#define EFUSE_BLK3_DATA4_M  (EFUSE_BLK3_DATA4_V << EFUSE_BLK3_DATA4_S)
+#define EFUSE_BLK3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_BLK3_DATA4_S  0
+
+/** EFUSE_RD_BLK3_DATA5_REG register
+ *  Register 5 of BLOCK3.
+ */
+#define EFUSE_RD_BLK3_DATA5_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_BLK3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Store the sixth 32-bit of Block3.
+ */
+#define EFUSE_BLK3_DATA5    0xFFFFFFFFU
+#define EFUSE_BLK3_DATA5_M  (EFUSE_BLK3_DATA5_V << EFUSE_BLK3_DATA5_S)
+#define EFUSE_BLK3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_BLK3_DATA5_S  0
+
+/** EFUSE_RD_BLK3_DATA6_REG register
+ *  Register 6 of BLOCK3.
+ */
+#define EFUSE_RD_BLK3_DATA6_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_BLK3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Store the seventh 32-bit of Block3.
+ */
+#define EFUSE_BLK3_DATA6    0xFFFFFFFFU
+#define EFUSE_BLK3_DATA6_M  (EFUSE_BLK3_DATA6_V << EFUSE_BLK3_DATA6_S)
+#define EFUSE_BLK3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_BLK3_DATA6_S  0
+
+/** EFUSE_RD_BLK3_DATA7_REG register
+ *  Register 7 of BLOCK3.
+ */
+#define EFUSE_RD_BLK3_DATA7_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_BLK3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Store the eighth 32-bit of Block3.
+ */
+#define EFUSE_BLK3_DATA7    0xFFFFFFFFU
+#define EFUSE_BLK3_DATA7_M  (EFUSE_BLK3_DATA7_V << EFUSE_BLK3_DATA7_S)
+#define EFUSE_BLK3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_BLK3_DATA7_S  0
+
+/** EFUSE_RD_REPEAT_ERR_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [1:0]; default: 0;
+ *  If any bit in RD_DIS is 1, then it indicates a programming error.
+ */
+#define EFUSE_RD_DIS_ERR    0x00000003U
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x00000003U
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [3:2]; default: 0;
+ *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  2
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [4]; default: 0;
+ *  If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(4))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  4
+/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [5]; default: 0;
+ *  If any bit in this filed is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(5))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  5
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [6]; default: 0;
+ *  If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming
+ *  error.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(6))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  6
+/** EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR : RO; bitpos: [9:7]; default: 0;
+ *  If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming
+ *  error.
+ */
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR_S  7
+/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [10]; default: 0;
+ *  If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(10))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  10
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [12:11]; default: 0;
+ *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  11
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
+ *  If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [14]; default: 0;
+ *  If any bit in this filed is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(14))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  14
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [15]; default: 0;
+ *  If any bit in this filed is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(15))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  15
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [16]; default: 0;
+ *  If any bit in this filed is 1, then it indicates a programming error.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(16))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  16
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [20:17]; default: 0;
+ *  If any bit in this filed is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  17
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [21]; default: 0;
+ *  If any bit in this filed is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  21
+/** EFUSE_RPT4_RESERVED_ERR : RO; bitpos: [31:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED_ERR    0x000003FFU
+#define EFUSE_RPT4_RESERVED_ERR_M  (EFUSE_RPT4_RESERVED_ERR_V << EFUSE_RPT4_RESERVED_ERR_S)
+#define EFUSE_RPT4_RESERVED_ERR_V  0x000003FFU
+#define EFUSE_RPT4_RESERVED_ERR_S  22
+
+/** EFUSE_RD_RS_ERR_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_BLK1_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes in block1.
+ */
+#define EFUSE_BLK1_ERR_NUM    0x00000007U
+#define EFUSE_BLK1_ERR_NUM_M  (EFUSE_BLK1_ERR_NUM_V << EFUSE_BLK1_ERR_NUM_S)
+#define EFUSE_BLK1_ERR_NUM_V  0x00000007U
+#define EFUSE_BLK1_ERR_NUM_S  0
+/** EFUSE_BLK1_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of block1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_BLK1_FAIL    (BIT(3))
+#define EFUSE_BLK1_FAIL_M  (EFUSE_BLK1_FAIL_V << EFUSE_BLK1_FAIL_S)
+#define EFUSE_BLK1_FAIL_V  0x00000001U
+#define EFUSE_BLK1_FAIL_S  3
+/** EFUSE_BLK2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes in block2.
+ */
+#define EFUSE_BLK2_ERR_NUM    0x00000007U
+#define EFUSE_BLK2_ERR_NUM_M  (EFUSE_BLK2_ERR_NUM_V << EFUSE_BLK2_ERR_NUM_S)
+#define EFUSE_BLK2_ERR_NUM_V  0x00000007U
+#define EFUSE_BLK2_ERR_NUM_S  4
+/** EFUSE_BLK2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of block2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_BLK2_FAIL    (BIT(7))
+#define EFUSE_BLK2_FAIL_M  (EFUSE_BLK2_FAIL_V << EFUSE_BLK2_FAIL_S)
+#define EFUSE_BLK2_FAIL_V  0x00000001U
+#define EFUSE_BLK2_FAIL_S  7
+/** EFUSE_BLK3_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes in block3.
+ */
+#define EFUSE_BLK3_ERR_NUM    0x00000007U
+#define EFUSE_BLK3_ERR_NUM_M  (EFUSE_BLK3_ERR_NUM_V << EFUSE_BLK3_ERR_NUM_S)
+#define EFUSE_BLK3_ERR_NUM_V  0x00000007U
+#define EFUSE_BLK3_ERR_NUM_S  8
+/** EFUSE_BLK3_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the block3 data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_BLK3_FAIL    (BIT(11))
+#define EFUSE_BLK3_FAIL_M  (EFUSE_BLK3_FAIL_V << EFUSE_BLK3_FAIL_S)
+#define EFUSE_BLK3_FAIL_V  0x00000001U
+#define EFUSE_BLK3_FAIL_S  11
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_EFUSE_MEM_FORCE_PD_M  (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_EFUSE_MEM_FORCE_PU_M  (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit and force to enable clock signal of eFuse memory.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [15:10]; default: 0;
+ *  Record the number of bit '1' in BLOCK0.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x0000003FU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x0000003FU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-3 corresponds to block
+ *  number 0-3, respectively.
+ */
+#define EFUSE_BLK_NUM    0x00000003U
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x00000003U
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_READ_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures hold time for efuse read.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures pulse time for efuse read.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures setup time for efuse read.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
+ *  Configures the initial read time of eFuse.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF0_REG register
+ *  Configurarion register 0 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures hold time for efuse program.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  0
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1;
+ *  Configures pulse time for burning '0' bit.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  8
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200;
+ *  Configures pulse time for burning '1' bit.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures setup time for efuse program.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34636176;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/register/soc/efuse_struct.h b/components/soc/esp32c2/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..fa1800be944
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/efuse_struct.h
@@ -0,0 +1,1084 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: Read Data Register */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [7:0]; default: 0;
+         *  Disable programming of individual eFuses.
+         */
+        uint32_t wr_dis:8;
+        /** reserved_0_8 : RW; bitpos: [31:8]; default: 0; */
+        uint32_t reserved_0_8:24;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [1:0]; default: 0;
+         *  The bit be set to disable software read high/low 128-bit of BLK3.
+         */
+        uint32_t rd_dis:2;
+        /** wdt_delay_sel : RO; bitpos: [3:2]; default: 0;
+         *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
+         *  80000. 2: 160000. 3:320000.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** dis_pad_jtag : RO; bitpos: [4]; default: 0;
+         *  Set this bit to disable pad jtag.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_icache : RO; bitpos: [5]; default: 0;
+         *  The bit be set to disable icache in download mode.
+         */
+        uint32_t dis_download_icache:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [6]; default: 0;
+         *  The bit be set to disable manual encryption.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** spi_boot_crypt_cnt : RO; bitpos: [9:7]; default: 0;
+         *  These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+         *  number of 1: disable.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** xts_key_length_256 : RO; bitpos: [10]; default: 0;
+         *  The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise,
+         *  XTS_AES use 128-bit eFuse data in BLOCK3.
+         */
+        uint32_t xts_key_length_256:1;
+        /** uart_print_control : RO; bitpos: [12:11]; default: 0;
+         *  Set this bit to disable usb printing.
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [13]; default: 0;
+         *  Set this bit to force ROM code to send a resume command during SPI boot.
+         */
+        uint32_t force_send_resume:1;
+        /** dis_download_mode : RO; bitpos: [14]; default: 0;
+         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7).
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [15]; default: 0;
+         *  This bit set means disable direct_boot mode.
+         */
+        uint32_t dis_direct_boot:1;
+        /** enable_security_download : RO; bitpos: [16]; default: 0;
+         *  Set this bit to enable secure UART download mode.
+         */
+        uint32_t enable_security_download:1;
+        /** flash_tpuw : RO; bitpos: [20:17]; default: 0;
+         *  Configures flash waiting time after power-up, in unit of ms. If the value is less
+         *  than 15, the waiting time is the configurable value.  Otherwise, the waiting time
+         *  is twice the configurable value.
+         */
+        uint32_t flash_tpuw:4;
+        /** secure_boot_en : RO; bitpos: [21]; default: 0;
+         *  The bit be set to enable secure boot.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_version : R; bitpos: [25:22]; default: 0;
+         *  Secure version for anti-rollback
+         */
+        uint32_t secure_version:4;
+        /** custom_mac_used : R; bitpos: [26]; default: 0;
+         *  True if MAC_CUSTOM is burned
+         */
+        uint32_t custom_mac_used:1;
+        /** disable_wafer_version_major : R; bitpos: [27]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [28]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** reserved_0_61 : R; bitpos: [31:29]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_0_61:3;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_blk1_data0 register
+ *  BLOCK1 data register 0.
+ */
+typedef union {
+    struct {
+        /** custom_mac : R; bitpos: [31:0]; default: 0;
+         *  Custom MAC address
+         */
+        uint32_t custom_mac:32;
+    };
+    uint32_t val;
+} efuse_rd_blk1_data0_reg_t;
+
+/** Type of rd_blk1_data1 register
+ *  BLOCK1 data register 1.
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [15:0]; default: 0;
+         *  Custom MAC address
+         */
+        uint32_t custom_mac_1:16;
+        /** reserved_1_48 : R; bitpos: [31:16]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_48:16;
+    };
+    uint32_t val;
+} efuse_rd_blk1_data1_reg_t;
+
+/** Type of rd_blk1_data2 register
+ *  BLOCK1 data register 2.
+ */
+typedef union {
+    struct {
+        /** system_data2 : RO; bitpos: [23:0]; default: 0;
+         *  Stores the bits [64:87] of system data.
+         */
+        uint32_t system_data2:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_blk1_data2_reg_t;
+
+/** Type of rd_blk2_data0 register
+ *  Register 0 of BLOCK2.
+ */
+typedef union {
+    struct {
+        /** mac : R; bitpos: [31:0]; default: 0;
+         *  MAC address
+         */
+        uint32_t mac:32;
+    };
+    uint32_t val;
+} efuse_rd_blk2_data0_reg_t;
+
+/** Type of rd_blk2_data1 register
+ *  Register 1 of BLOCK2.
+ */
+typedef union {
+    struct {
+        /** mac_1 : R; bitpos: [15:0]; default: 0;
+         *  MAC address
+         */
+        uint32_t mac_1:16;
+        /** wafer_version_minor : R; bitpos: [19:16]; default: 0;
+         *  WAFER_VERSION_MINOR
+         */
+        uint32_t wafer_version_minor:4;
+        /** wafer_version_major : R; bitpos: [21:20]; default: 0;
+         *  WAFER_VERSION_MAJOR
+         */
+        uint32_t wafer_version_major:2;
+        /** pkg_version : R; bitpos: [24:22]; default: 0;
+         *  EFUSE_PKG_VERSION
+         */
+        uint32_t pkg_version:3;
+        /** blk_version_minor : R; bitpos: [27:25]; default: 0;
+         *  Minor version of BLOCK2
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [29:28]; default: 0;
+         *  Major version of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+        /** ocode : R; bitpos: [31:30]; default: 0;
+         *  OCode
+         */
+        uint32_t ocode:2;
+    };
+    uint32_t val;
+} efuse_rd_blk2_data1_reg_t;
+
+/** Type of rd_blk2_data2 register
+ *  Register 2 of BLOCK2.
+ */
+typedef union {
+    struct {
+        /** ocode_1 : R; bitpos: [4:0]; default: 0;
+         *  OCode
+         */
+        uint32_t ocode_1:5;
+        /** temp_calib : R; bitpos: [13:5]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temp_calib:9;
+        /** adc1_init_code_atten0 : R; bitpos: [21:14]; default: 0;
+         *  ADC1 init code at atten0
+         */
+        uint32_t adc1_init_code_atten0:8;
+        /** adc1_init_code_atten3 : R; bitpos: [26:22]; default: 0;
+         *  ADC1 init code at atten3
+         */
+        uint32_t adc1_init_code_atten3:5;
+        /** adc1_cal_vol_atten0 : R; bitpos: [31:27]; default: 0;
+         *  ADC1 calibration voltage at atten0
+         */
+        uint32_t adc1_cal_vol_atten0:5;
+    };
+    uint32_t val;
+} efuse_rd_blk2_data2_reg_t;
+
+/** Type of rd_blk2_data3 register
+ *  Register 3 of BLOCK2.
+ */
+typedef union {
+    struct {
+        /** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0;
+         *  ADC1 calibration voltage at atten0
+         */
+        uint32_t adc1_cal_vol_atten0_1:3;
+        /** adc1_cal_vol_atten3 : R; bitpos: [8:3]; default: 0;
+         *  ADC1 calibration voltage at atten3
+         */
+        uint32_t adc1_cal_vol_atten3:6;
+        /** dig_dbias_hvt : R; bitpos: [13:9]; default: 0;
+         *  BLOCK2 digital dbias when hvt
+         */
+        uint32_t dig_dbias_hvt:5;
+        /** dig_ldo_slp_dbias2 : R; bitpos: [20:14]; default: 0;
+         *  BLOCK2 DIG_LDO_DBG0_DBIAS2
+         */
+        uint32_t dig_ldo_slp_dbias2:7;
+        /** dig_ldo_slp_dbias26 : R; bitpos: [28:21]; default: 0;
+         *  BLOCK2 DIG_LDO_DBG0_DBIAS26
+         */
+        uint32_t dig_ldo_slp_dbias26:8;
+        /** dig_ldo_act_dbias26 : R; bitpos: [31:29]; default: 0;
+         *  BLOCK2 DIG_LDO_ACT_DBIAS26
+         */
+        uint32_t dig_ldo_act_dbias26:3;
+    };
+    uint32_t val;
+} efuse_rd_blk2_data3_reg_t;
+
+/** Type of rd_blk2_data4 register
+ *  Register 4 of BLOCK2.
+ */
+typedef union {
+    struct {
+        /** dig_ldo_act_dbias26_1 : R; bitpos: [2:0]; default: 0;
+         *  BLOCK2 DIG_LDO_ACT_DBIAS26
+         */
+        uint32_t dig_ldo_act_dbias26_1:3;
+        /** dig_ldo_act_stepd10 : R; bitpos: [6:3]; default: 0;
+         *  BLOCK2 DIG_LDO_ACT_STEPD10
+         */
+        uint32_t dig_ldo_act_stepd10:4;
+        /** rtc_ldo_slp_dbias13 : R; bitpos: [13:7]; default: 0;
+         *  BLOCK2 DIG_LDO_SLP_DBIAS13
+         */
+        uint32_t rtc_ldo_slp_dbias13:7;
+        /** rtc_ldo_slp_dbias29 : R; bitpos: [22:14]; default: 0;
+         *  BLOCK2 DIG_LDO_SLP_DBIAS29
+         */
+        uint32_t rtc_ldo_slp_dbias29:9;
+        /** rtc_ldo_slp_dbias31 : R; bitpos: [28:23]; default: 0;
+         *  BLOCK2 DIG_LDO_SLP_DBIAS31
+         */
+        uint32_t rtc_ldo_slp_dbias31:6;
+        /** rtc_ldo_act_dbias31 : R; bitpos: [31:29]; default: 0;
+         *  BLOCK2 DIG_LDO_ACT_DBIAS31
+         */
+        uint32_t rtc_ldo_act_dbias31:3;
+    };
+    uint32_t val;
+} efuse_rd_blk2_data4_reg_t;
+
+/** Type of rd_blk2_data5 register
+ *  Register 5 of BLOCK2.
+ */
+typedef union {
+    struct {
+        /** rtc_ldo_act_dbias31_1 : R; bitpos: [2:0]; default: 0;
+         *  BLOCK2 DIG_LDO_ACT_DBIAS31
+         */
+        uint32_t rtc_ldo_act_dbias31_1:3;
+        /** rtc_ldo_act_dbias13 : R; bitpos: [10:3]; default: 0;
+         *  BLOCK2 DIG_LDO_ACT_DBIAS13
+         */
+        uint32_t rtc_ldo_act_dbias13:8;
+        /** reserved_2_171 : R; bitpos: [31:11]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_171:21;
+    };
+    uint32_t val;
+} efuse_rd_blk2_data5_reg_t;
+
+/** Type of rd_blk2_data6 register
+ *  Register 6 of BLOCK2.
+ */
+typedef union {
+    struct {
+        /** adc_calibration_3 : RO; bitpos: [10:0]; default: 0;
+         *  Store the bit [86:96] of ADC calibration data.
+         */
+        uint32_t adc_calibration_3:11;
+        /** blk2_reserved_data_0 : RO; bitpos: [31:11]; default: 0;
+         *  Store the bit [0:20] of block2 reserved data.
+         */
+        uint32_t blk2_reserved_data_0:21;
+    };
+    uint32_t val;
+} efuse_rd_blk2_data6_reg_t;
+
+/** Type of rd_blk2_data7 register
+ *  Register 7 of BLOCK2.
+ */
+typedef union {
+    struct {
+        /** blk2_reserved_data_1 : RO; bitpos: [31:0]; default: 0;
+         *  Store the bit [21:52] of block2 reserved data.
+         */
+        uint32_t blk2_reserved_data_1:32;
+    };
+    uint32_t val;
+} efuse_rd_blk2_data7_reg_t;
+
+/** Type of rd_blk3_data0 register
+ *  Register 0 of BLOCK3.
+ */
+typedef union {
+    struct {
+        /** blk3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Store the first 32-bit of Block3.
+         */
+        uint32_t blk3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_blk3_data0_reg_t;
+
+/** Type of rd_blk3_data1 register
+ *  Register 1 of BLOCK3.
+ */
+typedef union {
+    struct {
+        /** blk3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Store the second 32-bit of Block3.
+         */
+        uint32_t blk3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_blk3_data1_reg_t;
+
+/** Type of rd_blk3_data2 register
+ *  Register 2 of BLOCK3.
+ */
+typedef union {
+    struct {
+        /** blk3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Store the third 32-bit of Block3.
+         */
+        uint32_t blk3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_blk3_data2_reg_t;
+
+/** Type of rd_blk3_data3 register
+ *  Register 3 of BLOCK3.
+ */
+typedef union {
+    struct {
+        /** blk3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Store the fourth 32-bit of Block3.
+         */
+        uint32_t blk3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_blk3_data3_reg_t;
+
+/** Type of rd_blk3_data4 register
+ *  Register 4 of BLOCK3.
+ */
+typedef union {
+    struct {
+        /** blk3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Store the fifth 32-bit of Block3.
+         */
+        uint32_t blk3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_blk3_data4_reg_t;
+
+/** Type of rd_blk3_data5 register
+ *  Register 5 of BLOCK3.
+ */
+typedef union {
+    struct {
+        /** blk3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Store the sixth 32-bit of Block3.
+         */
+        uint32_t blk3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_blk3_data5_reg_t;
+
+/** Type of rd_blk3_data6 register
+ *  Register 6 of BLOCK3.
+ */
+typedef union {
+    struct {
+        /** blk3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Store the seventh 32-bit of Block3.
+         */
+        uint32_t blk3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_blk3_data6_reg_t;
+
+/** Type of rd_blk3_data7 register
+ *  Register 7 of BLOCK3.
+ */
+typedef union {
+    struct {
+        /** blk3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Store the eighth 32-bit of Block3.
+         */
+        uint32_t blk3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_blk3_data7_reg_t;
+
+
+/** Group: Report Register */
+/** Type of rd_repeat_err register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [1:0]; default: 0;
+         *  If any bit in RD_DIS is 1, then it indicates a programming error.
+         */
+        uint32_t rd_dis_err:2;
+        /** wdt_delay_sel_err : RO; bitpos: [3:2]; default: 0;
+         *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** dis_pad_jtag_err : RO; bitpos: [4]; default: 0;
+         *  If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_icache_err : RO; bitpos: [5]; default: 0;
+         *  If any bit in this filed is 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_icache_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [6]; default: 0;
+         *  If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming
+         *  error.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** spi_boot_encrypt_decrypt_cnt_err : RO; bitpos: [9:7]; default: 0;
+         *  If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming
+         *  error.
+         */
+        uint32_t spi_boot_encrypt_decrypt_cnt_err:3;
+        /** xts_key_length_256_err : RO; bitpos: [10]; default: 0;
+         *  If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error.
+         */
+        uint32_t xts_key_length_256_err:1;
+        /** uart_print_control_err : RO; bitpos: [12:11]; default: 0;
+         *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
+         *  If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error.
+         */
+        uint32_t force_send_resume_err:1;
+        /** dis_download_mode_err : RO; bitpos: [14]; default: 0;
+         *  If any bit in this filed is 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [15]; default: 0;
+         *  If any bit in this filed is 1, then it indicates a programming error.
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** enable_security_download_err : RO; bitpos: [16]; default: 0;
+         *  If any bit in this filed is 1, then it indicates a programming error.
+         */
+        uint32_t enable_security_download_err:1;
+        /** flash_tpuw_err : RO; bitpos: [20:17]; default: 0;
+         *  If any bit in this filed is 1, then it indicates a programming error.
+         */
+        uint32_t flash_tpuw_err:4;
+        /** secure_boot_en_err : RO; bitpos: [21]; default: 0;
+         *  If any bit in this filed is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** rpt4_reserved_err : RO; bitpos: [31:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved_err:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err_reg_t;
+
+/** Type of rd_rs_err register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** blk1_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes in block1.
+         */
+        uint32_t blk1_err_num:3;
+        /** blk1_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of block1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t blk1_fail:1;
+        /** blk2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes in block2.
+         */
+        uint32_t blk2_err_num:3;
+        /** blk2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of block2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t blk2_fail:1;
+        /** blk3_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes in block3.
+         */
+        uint32_t blk3_err_num:3;
+        /** blk3_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the block3 data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t blk3_fail:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} efuse_rd_rs_err_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t efuse_mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t efuse_mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit and force to enable clock signal of eFuse memory.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+         */
+        uint32_t op_code:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [3:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-3 corresponds to block
+         *  number 0-3, respectively.
+         */
+        uint32_t blk_num:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures hold time for efuse read.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures pulse time for efuse read.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures setup time for efuse read.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
+         *  Configures the initial read time of eFuse.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf0 register
+ *  Configurarion register 0 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** thp_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures hold time for efuse program.
+         */
+        uint32_t thp_a:8;
+        /** tpgm_inactive : R/W; bitpos: [15:8]; default: 1;
+         *  Configures pulse time for burning '0' bit.
+         */
+        uint32_t tpgm_inactive:8;
+        /** tpgm : R/W; bitpos: [31:16]; default: 200;
+         *  Configures pulse time for burning '1' bit.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures setup time for efuse program.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [15:10]; default: 0;
+         *  Record the number of bit '1' in BLOCK0.
+         */
+        uint32_t blk0_valid_bit_cnt:6;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 34636176;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_blk1_data0_reg_t rd_blk1_data0;
+    volatile efuse_rd_blk1_data1_reg_t rd_blk1_data1;
+    volatile efuse_rd_blk1_data2_reg_t rd_blk1_data2;
+    volatile efuse_rd_blk2_data0_reg_t rd_blk2_data0;
+    volatile efuse_rd_blk2_data1_reg_t rd_blk2_data1;
+    volatile efuse_rd_blk2_data2_reg_t rd_blk2_data2;
+    volatile efuse_rd_blk2_data3_reg_t rd_blk2_data3;
+    volatile efuse_rd_blk2_data4_reg_t rd_blk2_data4;
+    volatile efuse_rd_blk2_data5_reg_t rd_blk2_data5;
+    volatile efuse_rd_blk2_data6_reg_t rd_blk2_data6;
+    volatile efuse_rd_blk2_data7_reg_t rd_blk2_data7;
+    volatile efuse_rd_blk3_data0_reg_t rd_blk3_data0;
+    volatile efuse_rd_blk3_data1_reg_t rd_blk3_data1;
+    volatile efuse_rd_blk3_data2_reg_t rd_blk3_data2;
+    volatile efuse_rd_blk3_data3_reg_t rd_blk3_data3;
+    volatile efuse_rd_blk3_data4_reg_t rd_blk3_data4;
+    volatile efuse_rd_blk3_data5_reg_t rd_blk3_data5;
+    volatile efuse_rd_blk3_data6_reg_t rd_blk3_data6;
+    volatile efuse_rd_blk3_data7_reg_t rd_blk3_data7;
+    volatile efuse_rd_repeat_err_reg_t rd_repeat_err;
+    volatile efuse_rd_rs_err_reg_t rd_rs_err;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    uint32_t reserved_0a0[24];
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf0_reg_t wr_tim_conf0;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    uint32_t reserved_11c[56];
+    volatile efuse_date_reg_t date;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/include/soc/extmem_reg.h b/components/soc/esp32c2/register/soc/extmem_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/extmem_reg.h
rename to components/soc/esp32c2/register/soc/extmem_reg.h
diff --git a/components/soc/esp32c2/include/soc/gdma_reg.h b/components/soc/esp32c2/register/soc/gdma_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/gdma_reg.h
rename to components/soc/esp32c2/register/soc/gdma_reg.h
diff --git a/components/soc/esp32c2/include/soc/gdma_struct.h b/components/soc/esp32c2/register/soc/gdma_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/gdma_struct.h
rename to components/soc/esp32c2/register/soc/gdma_struct.h
diff --git a/components/soc/esp32c2/include/soc/gpio_reg.h b/components/soc/esp32c2/register/soc/gpio_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/gpio_reg.h
rename to components/soc/esp32c2/register/soc/gpio_reg.h
diff --git a/components/soc/esp32c2/include/soc/gpio_struct.h b/components/soc/esp32c2/register/soc/gpio_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/gpio_struct.h
rename to components/soc/esp32c2/register/soc/gpio_struct.h
diff --git a/components/soc/esp32c2/include/soc/i2c_reg.h b/components/soc/esp32c2/register/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/i2c_reg.h
rename to components/soc/esp32c2/register/soc/i2c_reg.h
diff --git a/components/soc/esp32c2/include/soc/i2c_struct.h b/components/soc/esp32c2/register/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/i2c_struct.h
rename to components/soc/esp32c2/register/soc/i2c_struct.h
diff --git a/components/soc/esp32c2/include/soc/interrupt_core0_reg.h b/components/soc/esp32c2/register/soc/interrupt_core0_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/interrupt_core0_reg.h
rename to components/soc/esp32c2/register/soc/interrupt_core0_reg.h
diff --git a/components/soc/esp32c2/register/soc/io_mux_reg.h b/components/soc/esp32c2/register/soc/io_mux_reg.h
new file mode 100644
index 00000000000..7a59d046f7f
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/io_mux_reg.h
@@ -0,0 +1,286 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_IO_MUX_REG_H_
+#define _SOC_IO_MUX_REG_H_
+
+#pragma once
+#include "soc/soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+
+#define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO2_REG               PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG               PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG               PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO5_REG               PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO6_REG               PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO7_REG               PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO8_REG               PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG               PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG              PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG              PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO12_REG              PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO13_REG              PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO14_REG              PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO15_REG              PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO16_REG              PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO17_REG              PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO18_REG              PERIPHS_IO_MUX_GPIO18_U
+#define IO_MUX_GPIO19_REG              PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO20_REG              PERIPHS_IO_MUX_U0TXD_U
+
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define SPI_HD_GPIO_NUM              12
+#define SPI_WP_GPIO_NUM              13
+#define SPI_CS0_GPIO_NUM             14
+#define SPI_CLK_GPIO_NUM             15
+#define SPI_D_GPIO_NUM               16
+#define SPI_Q_GPIO_NUM               17
+
+#define EXT_OSC_SLOW_GPIO_NUM        0
+
+#define MAX_RTC_GPIO_NUM              5
+#define MAX_PAD_GPIO_NUM             20
+#define MAX_GPIO_NUM                 24
+#define DIG_IO_HOLD_BIT_SHIFT         0
+
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
+#define PAD_POWER_SEL                               BIT(15)
+#define PAD_POWER_SEL_V                             0x1
+#define PAD_POWER_SEL_M                             BIT(15)
+#define PAD_POWER_SEL_S                             15
+
+#define PAD_POWER_SWITCH_DELAY                      0x7
+#define PAD_POWER_SWITCH_DELAY_V                    0x7
+#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
+#define PAD_POWER_SWITCH_DELAY_S                    12
+
+#define CLK_OUT3                                    0xf
+#define CLK_OUT3_V                                  CLK_OUT3
+#define CLK_OUT3_S                                  8
+#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2                                    0xf
+#define CLK_OUT2_V                                  CLK_OUT2
+#define CLK_OUT2_S                                  4
+#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1                                    0xf
+#define CLK_OUT1_V                                  CLK_OUT1
+#define CLK_OUT1_S                                  0
+#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
+// definitions above are inherited from previous version of code, should double check
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_XTAL_32K_P_U           (REG_IO_MUX_BASE + 0x4)
+#define FUNC_XTAL_32K_P_GPIO0                                       1
+#define FUNC_XTAL_32K_P_GPIO0_0                                     0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U           (REG_IO_MUX_BASE + 0x8)
+#define FUNC_XTAL_32K_N_GPIO1                                       1
+#define FUNC_XTAL_32K_N_GPIO1_0                                     0
+
+#define PERIPHS_IO_MUX_GPIO2_U                (REG_IO_MUX_BASE + 0xC)
+#define FUNC_GPIO2_FSPIQ                                            2
+#define FUNC_GPIO2_GPIO2                                            1
+#define FUNC_GPIO2_GPIO2_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO3_U               (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO3_GPIO3                                            1
+#define FUNC_GPIO3_GPIO3_0                                          0
+
+#define PERIPHS_IO_MUX_MTMS_U                (REG_IO_MUX_BASE + 0x14)
+#define FUNC_MTMS_FSPIHD                                            2
+#define FUNC_MTMS_GPIO4                                             1
+#define FUNC_MTMS_MTMS                                              0
+
+#define PERIPHS_IO_MUX_MTDI_U                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_MTDI_FSPIWP                                            2
+#define FUNC_MTDI_GPIO5                                             1
+#define FUNC_MTDI_MTDI                                              0
+
+#define PERIPHS_IO_MUX_MTCK_U                (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_MTCK_FSPICLK                                           2
+#define FUNC_MTCK_GPIO6                                             1
+#define FUNC_MTCK_MTCK                                              0
+
+#define PERIPHS_IO_MUX_MTDO_U                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_MTDO_FSPID                                             2
+#define FUNC_MTDO_GPIO7                                             1
+#define FUNC_MTDO_MTDO                                              0
+
+#define PERIPHS_IO_MUX_GPIO8_U               (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_GPIO8                                            1
+#define FUNC_GPIO8_GPIO8_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO9_U               (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_GPIO9                                            1
+#define FUNC_GPIO9_GPIO9_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO10_U              (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_GPIO10_FSPICS0                                         2
+#define FUNC_GPIO10_GPIO10                                          1
+#define FUNC_GPIO10_GPIO10_0                                        0
+
+#define PERIPHS_IO_MUX_VDD_SPI_U             (REG_IO_MUX_BASE + 0x30)
+#define FUNC_VDD_SPI_GPIO11                                         1
+#define FUNC_VDD_SPI_GPIO11_0                                       0
+
+#define PERIPHS_IO_MUX_SPIHD_U               (REG_IO_MUX_BASE + 0x34)
+#define FUNC_SPIHD_GPIO12                                           1
+#define FUNC_SPIHD_SPIHD                                            0
+
+#define PERIPHS_IO_MUX_SPIWP_U               (REG_IO_MUX_BASE + 0x38)
+#define FUNC_SPIWP_GPIO13                                           1
+#define FUNC_SPIWP_SPIWP                                            0
+
+#define PERIPHS_IO_MUX_SPICS0_U              (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_SPICS0_GPIO14                                          1
+#define FUNC_SPICS0_SPICS0                                          0
+
+#define PERIPHS_IO_MUX_SPICLK_U              (REG_IO_MUX_BASE + 0x40)
+#define FUNC_SPICLK_GPIO15                                          1
+#define FUNC_SPICLK_SPICLK                                          0
+
+#define PERIPHS_IO_MUX_SPID_U                (REG_IO_MUX_BASE + 0x44)
+#define FUNC_SPID_GPIO16                                            1
+#define FUNC_SPID_SPID                                              0
+
+#define PERIPHS_IO_MUX_SPIQ_U                (REG_IO_MUX_BASE + 0x48)
+#define FUNC_SPIQ_GPIO17                                            1
+#define FUNC_SPIQ_SPIQ                                              0
+
+#define PERIPHS_IO_MUX_GPIO18_U              (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_GPIO18_GPIO18                                          1
+#define FUNC_GPIO18_GPIO18_0                                        0
+
+#define PERIPHS_IO_MUX_U0RXD_U               (REG_IO_MUX_BASE + 0x50)
+#define FUNC_U0RXD_GPIO19                                           1
+#define FUNC_U0RXD_U0RXD                                            0
+
+#define PERIPHS_IO_MUX_U0TXD_U               (REG_IO_MUX_BASE + 0x54)
+#define FUNC_U0TXD_GPIO20                                           1
+#define FUNC_U0TXD_U0TXD                                            0
+
+#define IO_MUX_PIN_CTRL_REG          (REG_IO_MUX_BASE + 0x0)
+/* IO_MUX_CLK_OUT3 : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
+/*description: If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. C
+LK_OUT_out3 can be found in peripheral output signals..*/
+#define IO_MUX_CLK_OUT3    0x0000000F
+#define IO_MUX_CLK_OUT3_M  ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S))
+#define IO_MUX_CLK_OUT3_V  0xF
+#define IO_MUX_CLK_OUT3_S  8
+/* IO_MUX_CLK_OUT2 : R/W ;bitpos:[7:4] ;default: 4'hf ; */
+/*description: If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. C
+LK_OUT_out2 can be found in peripheral output signals..*/
+#define IO_MUX_CLK_OUT2    0x0000000F
+#define IO_MUX_CLK_OUT2_M  ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S))
+#define IO_MUX_CLK_OUT2_V  0xF
+#define IO_MUX_CLK_OUT2_S  4
+/* IO_MUX_CLK_OUT1 : R/W ;bitpos:[3:0] ;default: 4'hf ; */
+/*description: If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. C
+LK_OUT_out1 can be found in peripheral output signals..*/
+#define IO_MUX_CLK_OUT1    0x0000000F
+#define IO_MUX_CLK_OUT1_M  ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S))
+#define IO_MUX_CLK_OUT1_V  0xF
+#define IO_MUX_CLK_OUT1_S  0
+/* IO_MUX_DATE_REG : R/W ;bitpos:[27:0] ;default: 28'h2106190 ; */
+/*description: Version control register.*/
+#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0xFC)
+#define IO_MUX_DATE_REG_M  ((IO_MUX_DATE_REG_V)<<(IO_MUX_DATE_REG_S))
+#define IO_MUX_DATE_REG_V  0xFFFFFFF
+#define IO_MUX_DATE_REG_S  0
+
+#endif
diff --git a/components/soc/esp32c2/include/soc/ledc_reg.h b/components/soc/esp32c2/register/soc/ledc_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/ledc_reg.h
rename to components/soc/esp32c2/register/soc/ledc_reg.h
diff --git a/components/soc/esp32c2/include/soc/ledc_struct.h b/components/soc/esp32c2/register/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/ledc_struct.h
rename to components/soc/esp32c2/register/soc/ledc_struct.h
diff --git a/components/soc/esp32c2/include/soc/modem_clkrst_reg.h b/components/soc/esp32c2/register/soc/modem_clkrst_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/modem_clkrst_reg.h
rename to components/soc/esp32c2/register/soc/modem_clkrst_reg.h
diff --git a/components/soc/esp32c2/register/soc/reg_base.h b/components/soc/esp32c2/register/soc/reg_base.h
new file mode 100644
index 00000000000..34b56a9d95b
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/reg_base.h
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DR_REG_SYSTEM_BASE                      0x600c0000
+#define DR_REG_SENSITIVE_BASE                   0x600c1000
+#define DR_REG_INTERRUPT_BASE                   0x600c2000
+#define DR_REG_EXTMEM_BASE                      0x600c4000 // CACHE_CONFIG
+#define DR_REG_MMU_TABLE                        0x600c5000
+#define DR_REG_SHA_BASE                         0x6003b000
+#define DR_REG_ECC_MULT_BASE                    0x6003e000
+#define DR_REG_GDMA_BASE                        0x6003f000
+#define DR_REG_ASSIST_DEBUG_BASE                0x600ce000
+#define DR_REG_DEDICATED_GPIO_BASE              0x600cf000
+#define DR_REG_WORLD_CNTL_BASE                  0x600d0000
+#define DR_REG_UART_BASE                        0x60000000
+#define DR_REG_SPI1_BASE                        0x60002000
+#define DR_REG_SPI0_BASE                        0x60003000
+#define DR_REG_GPIO_BASE                        0x60004000
+#define DR_REG_FE2_BASE                         0x60005000
+#define DR_REG_FE_BASE                          0x60006000
+#define DR_REG_RTCCNTL_BASE                     0x60008000
+#define DR_REG_IO_MUX_BASE                      0x60009000
+#define DR_REG_RTC_I2C_BASE                     0x6000e000
+#define DR_REG_UART1_BASE                       0x60010000
+#define DR_REG_I2C_EXT_BASE                     0x60013000
+#define DR_REG_LEDC_BASE                        0x60019000
+#define DR_REG_EFUSE_BASE                       0x60008800
+#define DR_REG_NRX_BASE                         0x6001CC00
+#define DR_REG_BB_BASE                          0x6001D000
+#define DR_REG_TIMERGROUP0_BASE                 0x6001F000
+#define DR_REG_SYSTIMER_BASE                    0x60023000
+#define DR_REG_SPI2_BASE                        0x60024000
+#define DR_REG_SYSCON_BASE                      0x60026000
+#define DR_REG_APB_SARADC_BASE                  0x60040000
+#define DR_REG_WDEVLE_BASE                      0x60045000
+#define DR_REG_ETM_BIT_BASE                     0x6004B000
+#define DR_REG_BLE_TIMER_BASE                   0x6004B800
+#define DR_REG_BLE_SEC_BASE                     0x6004C000
+#define DR_REG_COEX_BIT_BASE                    0x6004C400
+#define DR_REG_MODEM_CLKRST_BASE                0x6004d800
+#define DR_REG_I2C_MST_BASE                     0x6004E800
+#define DR_REG_XTS_AES_BASE                     0x600CC000
+
+/* For backward compatibility with the older register name */
+#define DR_REG_AES_XTS_BASE                     DR_REG_XTS_AES_BASE
diff --git a/components/soc/esp32c2/register/soc/rtc_cntl_reg.h b/components/soc/esp32c2/register/soc/rtc_cntl_reg.h
new file mode 100644
index 00000000000..2a9a5659f7f
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/rtc_cntl_reg.h
@@ -0,0 +1,1916 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_RTC_CNTL_REG_H_
+#define _SOC_RTC_CNTL_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
+#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
+
+#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
+/* RTC_CNTL_SW_SYS_RST :  ;bitpos:[31] ;default: 1'd0 ; */
+/*description: SW system reset.*/
+#define RTC_CNTL_SW_SYS_RST    (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_V  0x1
+#define RTC_CNTL_SW_SYS_RST_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_NORST :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force no reset in deep sleep.*/
+#define RTC_CNTL_DG_WRAP_FORCE_NORST    (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
+/* RTC_CNTL_DG_WRAP_FORCE_RST :  ;bitpos:[29] ;default: 1'd0 ; */
+/*description: digital wrap force reset in deep sleep.*/
+#define RTC_CNTL_DG_WRAP_FORCE_RST    (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
+/* RTC_CNTL_ANALOG_FORCE_NOISO :  ;bitpos:[28] ;default: 1'd1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_ANALOG_FORCE_NOISO    (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
+/* RTC_CNTL_ANALOG_FORCE_ISO :  ;bitpos:[25] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_ANALOG_FORCE_ISO    (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
+/* RTC_CNTL_XTL_EXT_CTR_SEL :  ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_XTL_EXT_CTR_SEL    0x00000007
+#define RTC_CNTL_XTL_EXT_CTR_SEL_M  ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S))
+#define RTC_CNTL_XTL_EXT_CTR_SEL_V  0x7
+#define RTC_CNTL_XTL_EXT_CTR_SEL_S  20
+/* RTC_CNTL_XTL_EN_WAIT :  ;bitpos:[17:14] ;default: 4'd2 ; */
+/*description: wait bias_sleep and current source wakeup.*/
+#define RTC_CNTL_XTL_EN_WAIT    0x0000000F
+#define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
+#define RTC_CNTL_XTL_EN_WAIT_V  0xF
+#define RTC_CNTL_XTL_EN_WAIT_S  14
+/* RTC_CNTL_XTL_FORCE_PU :  ;bitpos:[13] ;default: 1'd1 ; */
+/*description: crystall force power up.*/
+#define RTC_CNTL_XTL_FORCE_PU    (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_V  0x1
+#define RTC_CNTL_XTL_FORCE_PU_S  13
+/* RTC_CNTL_XTL_FORCE_PD :  ;bitpos:[12] ;default: 1'b0 ; */
+/*description: crystall force power down.*/
+#define RTC_CNTL_XTL_FORCE_PD    (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_V  0x1
+#define RTC_CNTL_XTL_FORCE_PD_S  12
+/* RTC_CNTL_BBPLL_FORCE_PU :  ;bitpos:[11] ;default: 1'd0 ; */
+/*description: BB_PLL force power up.*/
+#define RTC_CNTL_BBPLL_FORCE_PU    (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PU_S  11
+/* RTC_CNTL_BBPLL_FORCE_PD :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: BB_PLL force power down.*/
+#define RTC_CNTL_BBPLL_FORCE_PD    (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PD_S  10
+/* RTC_CNTL_BBPLL_I2C_FORCE_PU :  ;bitpos:[9] ;default: 1'd0 ; */
+/*description: BB_PLL_I2C force power up.*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU    (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
+/* RTC_CNTL_BBPLL_I2C_FORCE_PD :  ;bitpos:[8] ;default: 1'b0 ; */
+/*description: BB_PLL _I2C force power down.*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD    (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
+/* RTC_CNTL_BB_I2C_FORCE_PU :  ;bitpos:[7] ;default: 1'd0 ; */
+/*description: BB_I2C force power up.*/
+#define RTC_CNTL_BB_I2C_FORCE_PU    (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
+/* RTC_CNTL_BB_I2C_FORCE_PD :  ;bitpos:[6] ;default: 1'b0 ; */
+/*description: BB_I2C force power down.*/
+#define RTC_CNTL_BB_I2C_FORCE_PD    (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
+/* RTC_CNTL_SW_PROCPU_RST :  ;bitpos:[5] ;default: 1'b0 ; */
+/*description: PRO CPU SW reset.*/
+#define RTC_CNTL_SW_PROCPU_RST    (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_V  0x1
+#define RTC_CNTL_SW_PROCPU_RST_S  5
+/* RTC_CNTL_SW_STALL_PROCPU_C0 :  ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P
+RO CPU.*/
+#define RTC_CNTL_SW_STALL_PROCPU_C0    0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
+
+#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x4)
+/* RTC_CNTL_SLP_VAL_LO :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SLP_VAL_LO    0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
+#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_S  0
+
+#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x8)
+/* RTC_CNTL_MAIN_TIMER_ALARM_EN :  ;bitpos:[16] ;default: 1'h0 ; */
+/*description: timer alarm enable bit.*/
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN    (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
+/* RTC_CNTL_SLP_VAL_HI :  ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC sleep timer high 16 bits.*/
+#define RTC_CNTL_SLP_VAL_HI    0x0000FFFF
+#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
+#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
+#define RTC_CNTL_SLP_VAL_HI_S  0
+
+#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0xC)
+/* RTC_CNTL_TIME_UPDATE :  ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Set 1: to update register with RTC timer.*/
+#define RTC_CNTL_TIME_UPDATE    (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_V  0x1
+#define RTC_CNTL_TIME_UPDATE_S  31
+/* RTC_CNTL_TIMER_SYS_RST :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: enable to record system reset time.*/
+#define RTC_CNTL_TIMER_SYS_RST    (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_V  0x1
+#define RTC_CNTL_TIMER_SYS_RST_S  29
+/* RTC_CNTL_TIMER_XTL_OFF :  ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Enable to record 40M XTAL OFF time.*/
+#define RTC_CNTL_TIMER_XTL_OFF    (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
+#define RTC_CNTL_TIMER_XTL_OFF_S  28
+/* RTC_CNTL_TIMER_SYS_STALL :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable to record system stall time.*/
+#define RTC_CNTL_TIMER_SYS_STALL    (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
+#define RTC_CNTL_TIMER_SYS_STALL_S  27
+
+#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x10)
+/* RTC_CNTL_TIMER_VALUE0_LOW :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits.*/
+#define RTC_CNTL_TIMER_VALUE0_LOW    0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
+#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x14)
+/* RTC_CNTL_TIMER_VALUE0_HIGH :  ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits.*/
+#define RTC_CNTL_TIMER_VALUE0_HIGH    0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
+
+#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
+/* RTC_CNTL_SLEEP_EN :  ;bitpos:[31] ;default: 1'd0 ; */
+/*description: sleep enable bit.*/
+#define RTC_CNTL_SLEEP_EN    (BIT(31))
+#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_V  0x1
+#define RTC_CNTL_SLEEP_EN_S  31
+/* RTC_CNTL_SLP_REJECT :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: leep reject bit.*/
+#define RTC_CNTL_SLP_REJECT    (BIT(30))
+#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_V  0x1
+#define RTC_CNTL_SLP_REJECT_S  30
+/* RTC_CNTL_SLP_WAKEUP :  ;bitpos:[29] ;default: 1'd0 ; */
+/*description: leep wakeup bit.*/
+#define RTC_CNTL_SLP_WAKEUP    (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_S  29
+/* RTC_CNTL_SDIO_ACTIVE_IND :  ;bitpos:[28] ;default: 1'd0 ; */
+/*description: SDIO active indication.*/
+#define RTC_CNTL_SDIO_ACTIVE_IND    (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
+#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
+/* RTC_CNTL_APB2RTC_BRIDGE_SEL :  ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: APB to RTC using bridge.*/
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL    (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
+/* RTC_CNTL_SLP_REJECT_CAUSE_CLR :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear rtc sleep reject cause.*/
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
+/* RTC_CNTL_SW_CPU_INT :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rtc software interrupt to main cpu.*/
+#define RTC_CNTL_SW_CPU_INT    (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_V  0x1
+#define RTC_CNTL_SW_CPU_INT_S  0
+
+#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1C)
+/* RTC_CNTL_PLL_BUF_WAIT :  ;bitpos:[31:24] ;default: 8'd40 ; */
+/*description: PLL wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_PLL_BUF_WAIT    0x000000FF
+#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
+#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
+#define RTC_CNTL_PLL_BUF_WAIT_S  24
+/* RTC_CNTL_XTL_BUF_WAIT :  ;bitpos:[23:14] ;default: 10'd80 ; */
+/*description: XTAL wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_XTL_BUF_WAIT    0x000003FF
+#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
+#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
+#define RTC_CNTL_XTL_BUF_WAIT_S  14
+/* RTC_CNTL_CK8M_WAIT :  ;bitpos:[13:6] ;default: 8'h10 ; */
+/*description: CK8M wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_CK8M_WAIT    0x000000FF
+#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
+#define RTC_CNTL_CK8M_WAIT_V  0xFF
+#define RTC_CNTL_CK8M_WAIT_S  6
+/* RTC_CNTL_CPU_STALL_WAIT :  ;bitpos:[5:1] ;default: 5'd1 ; */
+/*description: CPU stall wait cycles in fast_clk_rtc.*/
+#define RTC_CNTL_CPU_STALL_WAIT    0x0000001F
+#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
+#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
+#define RTC_CNTL_CPU_STALL_WAIT_S  1
+/* RTC_CNTL_CPU_STALL_EN :  ;bitpos:[0] ;default: 1'd1 ; */
+/*description: CPU stall enable bit.*/
+#define RTC_CNTL_CPU_STALL_EN    (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_V  0x1
+#define RTC_CNTL_CPU_STALL_EN_S  0
+
+#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
+/* RTC_CNTL_MIN_TIME_CK8M_OFF :  ;bitpos:[31:24] ;default: 8'h1 ; */
+/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/
+#define RTC_CNTL_MIN_TIME_CK8M_OFF    0x000000FF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
+
+#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x24)
+/* RTC_CNTL_DG_WRAP_POWERUP_TIMER :  ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER    0x0000007F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_WRAP_WAIT_TIMER :  ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER    0x000001FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
+
+#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x28)
+/* RTC_CNTL_MIN_SLP_VAL :  ;bitpos:[15:8] ;default: 8'h80 ; */
+/*description: minimal sleep cycles in slow_clk_rtc.*/
+#define RTC_CNTL_MIN_SLP_VAL    0x000000FF
+#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
+#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
+#define RTC_CNTL_MIN_SLP_VAL_S  8
+
+#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x2C)
+/* RTC_CNTL_PLL_I2C_PU :  ;bitpos:[31] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_PLL_I2C_PU    (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_V  0x1
+#define RTC_CNTL_PLL_I2C_PU_S  31
+/* RTC_CNTL_CKGEN_I2C_PU :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: CKGEN_I2C power up.*/
+#define RTC_CNTL_CKGEN_I2C_PU    (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
+#define RTC_CNTL_CKGEN_I2C_PU_S  30
+/* RTC_CNTL_RFRX_PBUS_PU :  ;bitpos:[28] ;default: 1'd0 ; */
+/*description: 1: RFRX_PBUS power up.*/
+#define RTC_CNTL_RFRX_PBUS_PU    (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
+#define RTC_CNTL_RFRX_PBUS_PU_S  28
+/* RTC_CNTL_TXRF_I2C_PU :  ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: TXRF_I2C power up.*/
+#define RTC_CNTL_TXRF_I2C_PU    (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_V  0x1
+#define RTC_CNTL_TXRF_I2C_PU_S  27
+/* RTC_CNTL_BBPLL_CAL_SLP_START :  ;bitpos:[25] ;default: 1'b0 ; */
+/*description: start BBPLL calibration during sleep.*/
+#define RTC_CNTL_BBPLL_CAL_SLP_START    (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
+/* RTC_CNTL_SAR_I2C_PU :  ;bitpos:[22] ;default: 1'b1 ; */
+/*description: PLLA force power up.*/
+#define RTC_CNTL_SAR_I2C_PU    (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_V  0x1
+#define RTC_CNTL_SAR_I2C_PU_S  22
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PU :  ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU    (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PD :  ;bitpos:[18] ;default: 1'b1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD    (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
+
+#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x30)
+/* RTC_CNTL_DRESET_MASK_PROCPU :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DRESET_MASK_PROCPU    (BIT(20))
+#define RTC_CNTL_DRESET_MASK_PROCPU_M  (BIT(20))
+#define RTC_CNTL_DRESET_MASK_PROCPU_V  0x1
+#define RTC_CNTL_DRESET_MASK_PROCPU_S  20
+/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU :  ;bitpos:[19] ;default: 1'b0 ; */
+/*description: PROCPU OcdHaltOnReset.*/
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU    (BIT(19))
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M  (BIT(19))
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V  0x1
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S  19
+/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU :  ;bitpos:[13] ;default: 1'b1 ; */
+/*description: PRO CPU state vector sel.*/
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU    (BIT(13))
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M  (BIT(13))
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V  0x1
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S  13
+/* RTC_CNTL_RESET_CAUSE_PROCPU :  ;bitpos:[5:0] ;default: 0 ; */
+/*description: reset cause of PRO CPU.*/
+#define RTC_CNTL_RESET_CAUSE_PROCPU    0x0000003F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
+#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
+
+#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x34)
+/* RTC_CNTL_WAKEUP_ENA :  ;bitpos:[31:15] ;default: 17'b1100 ; */
+/*description: wakeup enable bitmap.*/
+#define RTC_CNTL_WAKEUP_ENA    0x0001FFFF
+#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
+#define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_ENA_S  15
+
+#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x38)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA : BIT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_ENA    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_S  20
+/* RTC_CNTL_SWD_INT_ENA : BIT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA : BIT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA : BIT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
+/* RTC_CNTL_WDT_INT_ENA : BIT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA : BIT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA : BIT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
+
+#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x3C)
+/* RTC_CNTL_BBPLL_CAL_INT_RAW :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_RAW    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_S  20
+/* RTC_CNTL_SWD_INT_RAW :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt raw.*/
+#define RTC_CNTL_SWD_INT_RAW    (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_V  0x1
+#define RTC_CNTL_SWD_INT_RAW_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_RAW :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt raw.*/
+#define RTC_CNTL_MAIN_TIMER_INT_RAW    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
+/* RTC_CNTL_BROWN_OUT_INT_RAW :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt raw.*/
+#define RTC_CNTL_BROWN_OUT_INT_RAW    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
+/* RTC_CNTL_WDT_INT_RAW :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt raw.*/
+#define RTC_CNTL_WDT_INT_RAW    (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_V  0x1
+#define RTC_CNTL_WDT_INT_RAW_S  3
+/* RTC_CNTL_SLP_REJECT_INT_RAW :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt raw.*/
+#define RTC_CNTL_SLP_REJECT_INT_RAW    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_RAW :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt raw.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
+
+#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x40)
+/* RTC_CNTL_BBPLL_CAL_INT_ST :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_ST    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ST_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ST_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ST_S  20
+/* RTC_CNTL_SWD_INT_ST :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt state.*/
+#define RTC_CNTL_SWD_INT_ST    (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_V  0x1
+#define RTC_CNTL_SWD_INT_ST_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ST :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt state.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ST    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ST :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt state.*/
+#define RTC_CNTL_BROWN_OUT_INT_ST    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
+/* RTC_CNTL_WDT_INT_ST :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt state.*/
+#define RTC_CNTL_WDT_INT_ST    (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_V  0x1
+#define RTC_CNTL_WDT_INT_ST_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ST :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt state.*/
+#define RTC_CNTL_SLP_REJECT_INT_ST    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ST :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt state.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ST    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
+
+#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x44)
+/* RTC_CNTL_BBPLL_CAL_INT_CLR :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_CLR    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_S  20
+/* RTC_CNTL_SWD_INT_CLR :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Clear super watch dog interrupt state.*/
+#define RTC_CNTL_SWD_INT_CLR    (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_V  0x1
+#define RTC_CNTL_SWD_INT_CLR_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_CLR :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Clear RTC main timer interrupt state.*/
+#define RTC_CNTL_MAIN_TIMER_INT_CLR    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
+/* RTC_CNTL_BROWN_OUT_INT_CLR :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Clear brown out interrupt state.*/
+#define RTC_CNTL_BROWN_OUT_INT_CLR    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
+/* RTC_CNTL_WDT_INT_CLR :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state.*/
+#define RTC_CNTL_WDT_INT_CLR    (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_V  0x1
+#define RTC_CNTL_WDT_INT_CLR_S  3
+/* RTC_CNTL_SLP_REJECT_INT_CLR :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Clear sleep reject interrupt state.*/
+#define RTC_CNTL_SLP_REJECT_INT_CLR    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_CLR :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Clear sleep wakeup interrupt state.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
+
+#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x48)
+/* RTC_CNTL_SCRATCH0 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH0    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
+#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_S  0
+
+#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x4C)
+/* RTC_CNTL_SCRATCH1 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH1    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
+#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_S  0
+
+#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x50)
+/* RTC_CNTL_SCRATCH2 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH2    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
+#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_S  0
+
+#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x54)
+/* RTC_CNTL_SCRATCH3 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH3    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
+#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_S  0
+
+#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x58)
+/* RTC_CNTL_XTL_EXT_CTR_EN :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_XTL_EXT_CTR_EN    (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
+/* RTC_CNTL_XTL_EXT_CTR_LV :  ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: power down XTAL at high level.*/
+#define RTC_CNTL_XTL_EXT_CTR_LV    (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
+
+#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x5C)
+/* RTC_CNTL_GPIO_WAKEUP_FILTER :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable filter for gpio wakeup event.*/
+#define RTC_CNTL_GPIO_WAKEUP_FILTER    (BIT(31))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(31))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  31
+
+#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
+/* RTC_CNTL_DEEP_SLP_REJECT_EN :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable reject for deep sleep.*/
+#define RTC_CNTL_DEEP_SLP_REJECT_EN    (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
+/* RTC_CNTL_LIGHT_SLP_REJECT_EN :  ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable reject for light sleep.*/
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN    (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
+/* RTC_CNTL_SLEEP_REJECT_ENA :  ;bitpos:[29:12] ;default: 17'd0 ; */
+/*description: sleep reject enable.*/
+#define RTC_CNTL_SLEEP_REJECT_ENA    0x0003FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
+#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_S  12
+
+#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x64)
+/* RTC_CNTL_CPUPERIOD_SEL :  ;bitpos:[31:30] ;default: 2'b00 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_CPUPERIOD_SEL    0x00000003
+#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
+#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
+#define RTC_CNTL_CPUPERIOD_SEL_S  30
+/* RTC_CNTL_CPUSEL_CONF :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: CPU sel option.*/
+#define RTC_CNTL_CPUSEL_CONF    (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_V  0x1
+#define RTC_CNTL_CPUSEL_CONF_S  29
+
+#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x68)
+/* RTC_CNTL_ANA_CLK_RTC_SEL :  ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_ANA_CLK_RTC_SEL    0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
+#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
+/* RTC_CNTL_FAST_CLK_RTC_SEL :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: fast_clk_rtc sel. 0: XTAL div 2.*/
+#define RTC_CNTL_FAST_CLK_RTC_SEL    (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING :  ;bitpos:[28] ;default: 1'b1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING    (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING    (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
+/* RTC_CNTL_CK8M_FORCE_PU :  ;bitpos:[26] ;default: 1'd0 ; */
+/*description: CK8M force power up.*/
+#define RTC_CNTL_CK8M_FORCE_PU    (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PU_S  26
+/* RTC_CNTL_CK8M_FORCE_PD :  ;bitpos:[25] ;default: 1'd0 ; */
+/*description: CK8M force power down.*/
+#define RTC_CNTL_CK8M_FORCE_PD    (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PD_S  25
+/* RTC_CNTL_CK8M_DFREQ :  ;bitpos:[24:17] ;default: 8'd172 ; */
+/*description: CK8M_DFREQ.*/
+#define RTC_CNTL_CK8M_DFREQ    0x000000FF
+#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
+#define RTC_CNTL_CK8M_DFREQ_V  0xFF
+#define RTC_CNTL_CK8M_DFREQ_S  17
+/* RTC_CNTL_CK8M_FORCE_NOGATING :  ;bitpos:[16] ;default: 1'd0 ; */
+/*description: CK8M force no gating during sleep.*/
+#define RTC_CNTL_CK8M_FORCE_NOGATING    (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
+/* RTC_CNTL_XTAL_FORCE_NOGATING :  ;bitpos:[15] ;default: 1'd0 ; */
+/*description: XTAL force no gating during sleep.*/
+#define RTC_CNTL_XTAL_FORCE_NOGATING    (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
+/* RTC_CNTL_CK8M_DIV_SEL :  ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: divider = reg_ck8m_div_sel + 1.*/
+#define RTC_CNTL_CK8M_DIV_SEL    0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
+#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
+#define RTC_CNTL_CK8M_DIV_SEL_S  12
+/* RTC_CNTL_DIG_CLK8M_EN :  ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable CK8M for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_CLK8M_EN    (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_EN_S  10
+/* RTC_CNTL_DIG_CLK8M_D256_EN :  ;bitpos:[9] ;default: 1'd1 ; */
+/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_CLK8M_D256_EN    (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
+/* RTC_CNTL_DIG_XTAL32K_EN :  ;bitpos:[8] ;default: 1'd0 ; */
+/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_XTAL32K_EN    (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
+#define RTC_CNTL_DIG_XTAL32K_EN_S  8
+/* RTC_CNTL_ENB_CK8M_DIV :  ;bitpos:[7] ;default: 1'd0 ; */
+/*description: 1: CK8M_D256_OUT is actually CK8M.*/
+#define RTC_CNTL_ENB_CK8M_DIV    (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
+#define RTC_CNTL_ENB_CK8M_DIV_S  7
+/* RTC_CNTL_ENB_CK8M :  ;bitpos:[6] ;default: 1'd0 ; */
+/*description: disable CK8M and CK8M_D256_OUT.*/
+#define RTC_CNTL_ENB_CK8M    (BIT(6))
+#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_V  0x1
+#define RTC_CNTL_ENB_CK8M_S  6
+/* RTC_CNTL_CK8M_DIV :  ;bitpos:[5:4] ;default: 2'b01 ; */
+/*description: CK8M_D256_OUT divider. 00: div128.*/
+#define RTC_CNTL_CK8M_DIV    0x00000003
+#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
+#define RTC_CNTL_CK8M_DIV_V  0x3
+#define RTC_CNTL_CK8M_DIV_S  4
+/* RTC_CNTL_CK8M_DIV_SEL_VLD :  ;bitpos:[3] ;default: 1'b1 ; */
+/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/
+#define RTC_CNTL_CK8M_DIV_SEL_VLD    (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
+/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING :  ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING    (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
+/* RTC_CNTL_EFUSE_CLK_FORCE_GATING :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING    (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
+
+#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x6C)
+/* RTC_CNTL_SLOW_CLK_NEXT_EDGE :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE    (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
+/* RTC_CNTL_ANA_CLK_DIV :  ;bitpos:[30:23] ;default: 8'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_ANA_CLK_DIV    0x000000FF
+#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
+#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
+#define RTC_CNTL_ANA_CLK_DIV_S  23
+/* RTC_CNTL_ANA_CLK_DIV_VLD :  ;bitpos:[22] ;default: 1'b1 ; */
+/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/
+#define RTC_CNTL_ANA_CLK_DIV_VLD    (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
+#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
+
+#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
+/* RTC_CNTL_DBG_ATTEN_ACTIVE :  ;bitpos:[29:26] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DBG_ATTEN_ACTIVE    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_ACTIVE_M  ((RTC_CNTL_DBG_ATTEN_ACTIVE_V)<<(RTC_CNTL_DBG_ATTEN_ACTIVE_S))
+#define RTC_CNTL_DBG_ATTEN_ACTIVE_V  0xF
+#define RTC_CNTL_DBG_ATTEN_ACTIVE_S  26
+/* RTC_CNTL_DBG_ATTEN_MONITOR :  ;bitpos:[25:22] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in active state.*/
+#define RTC_CNTL_DBG_ATTEN_MONITOR    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
+#define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
+#define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
+/* RTC_CNTL_DBG_ATTEN_DEEP_SLP :  ;bitpos:[21:18] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in sleep state.*/
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
+/* RTC_CNTL_BIAS_SLEEP_MONITOR :  ;bitpos:[17] ;default: 1'b0 ; */
+/*description: bias_sleep when rtc in monitor state.*/
+#define RTC_CNTL_BIAS_SLEEP_MONITOR    (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
+/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP :  ;bitpos:[16] ;default: 1'b1 ; */
+/*description: bias_sleep when rtc in sleep_state.*/
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP    (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
+/* RTC_CNTL_PD_CUR_MONITOR :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in monitor state.*/
+#define RTC_CNTL_PD_CUR_MONITOR    (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_V  0x1
+#define RTC_CNTL_PD_CUR_MONITOR_S  15
+/* RTC_CNTL_PD_CUR_DEEP_SLP :  ;bitpos:[14] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in sleep_state.*/
+#define RTC_CNTL_PD_CUR_DEEP_SLP    (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
+#define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
+/* RTC_CNTL_BIAS_BUF_MONITOR :  ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BIAS_BUF_MONITOR    (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_BUF_MONITOR_S  13
+/* RTC_CNTL_BIAS_BUF_DEEP_SLP :  ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP    (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
+/* RTC_CNTL_BIAS_BUF_WAKE :  ;bitpos:[11] ;default: 1'b1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BIAS_BUF_WAKE    (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
+#define RTC_CNTL_BIAS_BUF_WAKE_S  11
+/* RTC_CNTL_BIAS_BUF_IDLE :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BIAS_BUF_IDLE    (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
+#define RTC_CNTL_BIAS_BUF_IDLE_S  10
+/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN :  ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN    (BIT(8))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M  (BIT(8))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V  0x1
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S  8
+/* RTC_CNTL_DG_VDD_DRV_B_SLP :  ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_VDD_DRV_B_SLP    0x000000FF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_S  0
+
+#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x74)
+/* RTC_CNTL_REGULATOR_FORCE_PU :  ;bitpos:[31] ;default: 1'd1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_REGULATOR_FORCE_PU    (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
+/* RTC_CNTL_REGULATOR_FORCE_PD :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0
+.8v or lower ).*/
+#define RTC_CNTL_REGULATOR_FORCE_PD    (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
+/* RTC_CNTL_SCK_DCAP :  ;bitpos:[21:14] ;default: 8'd0 ; */
+/*description: SCK_DCAP.*/
+#define RTC_CNTL_SCK_DCAP    0x000000FF
+#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
+#define RTC_CNTL_SCK_DCAP_V  0xFF
+#define RTC_CNTL_SCK_DCAP_S  14
+/* RTC_CNTL_DIG_REG_CAL_EN :  ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DIG_REG_CAL_EN    (BIT(7))
+#define RTC_CNTL_DIG_REG_CAL_EN_M  (BIT(7))
+#define RTC_CNTL_DIG_REG_CAL_EN_V  0x1
+#define RTC_CNTL_DIG_REG_CAL_EN_S  7
+
+#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x78)
+/* RTC_CNTL_PAD_FORCE_HOLD :  ;bitpos:[21] ;default: 1'd0 ; */
+/*description: rtc pad force hold.*/
+#define RTC_CNTL_PAD_FORCE_HOLD    (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_PAD_FORCE_HOLD_S  21
+
+#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x7C)
+/* RTC_CNTL_DG_WRAP_PD_EN :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_WRAP_PD_EN    (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
+#define RTC_CNTL_DG_WRAP_PD_EN_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_PU :  ;bitpos:[20] ;default: 1'd1 ; */
+/*description: digital core force power up.*/
+#define RTC_CNTL_DG_WRAP_FORCE_PU    (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
+/* RTC_CNTL_DG_WRAP_FORCE_PD :  ;bitpos:[19] ;default: 1'b0 ; */
+/*description: digital core force power down.*/
+#define RTC_CNTL_DG_WRAP_FORCE_PD    (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
+/* RTC_CNTL_LSLP_MEM_FORCE_PU :  ;bitpos:[5] ;default: 1'b1 ; */
+/*description: memories in digital core force no PD in sleep.*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PU    (BIT(5))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(5))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  5
+/* RTC_CNTL_LSLP_MEM_FORCE_PD :  ;bitpos:[4] ;default: 1'b0 ; */
+/*description: memories in digital core force PD in sleep.*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PD    (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  4
+/* RTC_CNTL_VDD_SPI_PD_EN :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_VDD_SPI_PD_EN    (BIT(3))
+#define RTC_CNTL_VDD_SPI_PD_EN_M  (BIT(3))
+#define RTC_CNTL_VDD_SPI_PD_EN_V  0x1
+#define RTC_CNTL_VDD_SPI_PD_EN_S  3
+/* RTC_CNTL_VDD_SPI_PWR_FORCE :  ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_VDD_SPI_PWR_FORCE    (BIT(2))
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_M  (BIT(2))
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_V  0x1
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_S  2
+/* RTC_CNTL_VDD_SPI_PWR_DRV :  ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_VDD_SPI_PWR_DRV    0x00000003
+#define RTC_CNTL_VDD_SPI_PWR_DRV_M  ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S))
+#define RTC_CNTL_VDD_SPI_PWR_DRV_V  0x3
+#define RTC_CNTL_VDD_SPI_PWR_DRV_S  0
+
+#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x80)
+/* RTC_CNTL_DG_WRAP_FORCE_NOISO :  ;bitpos:[31] ;default: 1'd1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO    (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_ISO :  ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force ISO.*/
+#define RTC_CNTL_DG_WRAP_FORCE_ISO    (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
+/* RTC_CNTL_DG_PAD_FORCE_HOLD :  ;bitpos:[15] ;default: 1'd0 ; */
+/*description: digital pad force hold.*/
+#define RTC_CNTL_DG_PAD_FORCE_HOLD    (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
+/* RTC_CNTL_DG_PAD_FORCE_UNHOLD :  ;bitpos:[14] ;default: 1'd1 ; */
+/*description: digital pad force un-hold.*/
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD    (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
+/* RTC_CNTL_DG_PAD_FORCE_ISO :  ;bitpos:[13] ;default: 1'd0 ; */
+/*description: digital pad force ISO.*/
+#define RTC_CNTL_DG_PAD_FORCE_ISO    (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
+/* RTC_CNTL_DG_PAD_FORCE_NOISO :  ;bitpos:[12] ;default: 1'd1 ; */
+/*description: digital pad force no ISO.*/
+#define RTC_CNTL_DG_PAD_FORCE_NOISO    (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
+/* RTC_CNTL_DG_PAD_AUTOHOLD_EN :  ;bitpos:[11] ;default: 1'd0 ; */
+/*description: digital pad enable auto-hold.*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN    (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
+/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD :  ;bitpos:[10] ;default: 1'd0 ; */
+/*description: wtite only register to clear digital pad auto-hold.*/
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD    (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
+/* RTC_CNTL_DG_PAD_AUTOHOLD :  ;bitpos:[9] ;default: 1'd0 ; */
+/*description: read only register to indicate digital pad auto-hold status.*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD    (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
+/* RTC_CNTL_DIG_ISO_FORCE_ON :  ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DIG_ISO_FORCE_ON    (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
+/* RTC_CNTL_DIG_ISO_FORCE_OFF :  ;bitpos:[7] ;default: 1'd1 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DIG_ISO_FORCE_OFF    (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
+
+#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x84)
+/* RTC_CNTL_WDT_EN :  ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_EN    (BIT(31))
+#define RTC_CNTL_WDT_EN_M  (BIT(31))
+#define RTC_CNTL_WDT_EN_V  0x1
+#define RTC_CNTL_WDT_EN_S  31
+/* RTC_CNTL_WDT_STG0 :  ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG0    0x00000007
+#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
+#define RTC_CNTL_WDT_STG0_V  0x7
+#define RTC_CNTL_WDT_STG0_S  28
+/* RTC_CNTL_WDT_STG1 :  ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG1    0x00000007
+#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
+#define RTC_CNTL_WDT_STG1_V  0x7
+#define RTC_CNTL_WDT_STG1_S  25
+/* RTC_CNTL_WDT_STG2 :  ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG2    0x00000007
+#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
+#define RTC_CNTL_WDT_STG2_V  0x7
+#define RTC_CNTL_WDT_STG2_S  22
+/* RTC_CNTL_WDT_STG3 :  ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG3    0x00000007
+#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
+#define RTC_CNTL_WDT_STG3_V  0x7
+#define RTC_CNTL_WDT_STG3_S  19
+
+/* RTC_CNTL_WDT_STGX : */
+/*description: stage action selection values */
+#define RTC_WDT_STG_SEL_OFF             0
+#define RTC_WDT_STG_SEL_INT             1
+#define RTC_WDT_STG_SEL_RESET_CPU       2
+#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
+#define RTC_WDT_STG_SEL_RESET_RTC       4
+
+/* RTC_CNTL_WDT_CPU_RESET_LENGTH :  ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: CPU reset counter length.*/
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH    0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
+/* RTC_CNTL_WDT_SYS_RESET_LENGTH :  ;bitpos:[15:13] ;default: 3'h1 ; */
+/*description: system reset counter length.*/
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH    0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
+/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN :  ;bitpos:[12] ;default: 1'h1 ; */
+/*description: enable WDT in flash boot.*/
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN    (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
+/* RTC_CNTL_WDT_PROCPU_RESET_EN :  ;bitpos:[11] ;default: 1'd0 ; */
+/*description: enable WDT reset PRO CPU.*/
+#define RTC_CNTL_WDT_PROCPU_RESET_EN    (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
+/* RTC_CNTL_WDT_PAUSE_IN_SLP :  ;bitpos:[9] ;default: 1'd1 ; */
+/*description: pause WDT in sleep.*/
+#define RTC_CNTL_WDT_PAUSE_IN_SLP    (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
+/* RTC_CNTL_WDT_CHIP_RESET_EN :  ;bitpos:[8] ;default: 1'b0 ; */
+/*description: wdt reset whole chip enable.*/
+#define RTC_CNTL_WDT_CHIP_RESET_EN    (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
+/* RTC_CNTL_WDT_CHIP_RESET_WIDTH :  ;bitpos:[7:0] ;default: 8'd20 ; */
+/*description: chip reset siginal pulse width.*/
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH    0x000000FF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
+
+#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x88)
+/* RTC_CNTL_WDT_STG0_HOLD :  ;bitpos:[31:0] ;default: 32'd200000 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_STG0_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
+#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x8C)
+/* RTC_CNTL_WDT_STG1_HOLD :  ;bitpos:[31:0] ;default: 32'd80000 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_STG1_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
+#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x90)
+/* RTC_CNTL_WDT_STG2_HOLD :  ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_STG2_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
+#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x94)
+/* RTC_CNTL_WDT_STG3_HOLD :  ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_STG3_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
+#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_S  0
+
+#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0x98)
+/* RTC_CNTL_WDT_FEED :  ;bitpos:[31] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_FEED    (BIT(31))
+#define RTC_CNTL_WDT_FEED_M  (BIT(31))
+#define RTC_CNTL_WDT_FEED_V  0x1
+#define RTC_CNTL_WDT_FEED_S  31
+
+#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x9C)
+/* RTC_CNTL_WDT_WKEY :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_WDT_WKEY    0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
+#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_S  0
+
+#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xA0)
+/* RTC_CNTL_SWD_AUTO_FEED_EN :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: automatically feed swd when int comes.*/
+#define RTC_CNTL_SWD_AUTO_FEED_EN    (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
+#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
+/* RTC_CNTL_SWD_DISABLE :  ;bitpos:[30] ;default: 1'b0 ; */
+/*description: disable SWD.*/
+#define RTC_CNTL_SWD_DISABLE    (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_V  0x1
+#define RTC_CNTL_SWD_DISABLE_S  30
+/* RTC_CNTL_SWD_FEED :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Sw feed swd.*/
+#define RTC_CNTL_SWD_FEED    (BIT(29))
+#define RTC_CNTL_SWD_FEED_M  (BIT(29))
+#define RTC_CNTL_SWD_FEED_V  0x1
+#define RTC_CNTL_SWD_FEED_S  29
+/* RTC_CNTL_SWD_RST_FLAG_CLR :  ;bitpos:[28] ;default: 1'b0 ; */
+/*description: reset swd reset flag.*/
+#define RTC_CNTL_SWD_RST_FLAG_CLR    (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
+#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
+/* RTC_CNTL_SWD_SIGNAL_WIDTH :  ;bitpos:[27:18] ;default: 10'd300 ; */
+/*description: adjust signal width send to swd.*/
+#define RTC_CNTL_SWD_SIGNAL_WIDTH    0x000003FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
+/* RTC_CNTL_SWD_BYPASS_RST :  ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SWD_BYPASS_RST    (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_V  0x1
+#define RTC_CNTL_SWD_BYPASS_RST_S  17
+/* RTC_CNTL_SWD_FEED_INT :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: swd interrupt for feeding.*/
+#define RTC_CNTL_SWD_FEED_INT    (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_V  0x1
+#define RTC_CNTL_SWD_FEED_INT_S  1
+/* RTC_CNTL_SWD_RESET_FLAG :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: swd reset flag.*/
+#define RTC_CNTL_SWD_RESET_FLAG    (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
+#define RTC_CNTL_SWD_RESET_FLAG_S  0
+
+#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xA4)
+/* RTC_CNTL_SWD_WKEY :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SWD_WKEY    0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
+#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_S  0
+
+#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0xA8)
+/* RTC_CNTL_SW_STALL_PROCPU_C1 :  ;bitpos:[31:26] ;default: 6'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SW_STALL_PROCPU_C1    0x0000003F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
+
+#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0xAC)
+/* RTC_CNTL_SCRATCH4 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH4    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
+#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_S  0
+
+#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0xB0)
+/* RTC_CNTL_SCRATCH5 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH5    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
+#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_S  0
+
+#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0xB4)
+/* RTC_CNTL_SCRATCH6 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH6    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
+#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_S  0
+
+#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0xB8)
+/* RTC_CNTL_SCRATCH7 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SCRATCH7    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
+#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_S  0
+
+#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0xBC)
+/* RTC_CNTL_MAIN_STATE :  ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: rtc main state machine status.*/
+#define RTC_CNTL_MAIN_STATE    0x0000000F
+#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
+#define RTC_CNTL_MAIN_STATE_V  0xF
+#define RTC_CNTL_MAIN_STATE_S  28
+/* RTC_CNTL_MAIN_STATE_IN_IDLE :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: rtc main state machine is in idle state.*/
+#define RTC_CNTL_MAIN_STATE_IN_IDLE    (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
+/* RTC_CNTL_MAIN_STATE_IN_SLP :  ;bitpos:[26] ;default: 1'b0 ; */
+/*description: rtc main state machine is in sleep state.*/
+#define RTC_CNTL_MAIN_STATE_IN_SLP    (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL :  ;bitpos:[25] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait xtal state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL    (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL :  ;bitpos:[24] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait pll state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL    (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M :  ;bitpos:[23] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait 8m state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M    (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
+/* RTC_CNTL_IN_LOW_POWER_STATE :  ;bitpos:[22] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of low power.*/
+#define RTC_CNTL_IN_LOW_POWER_STATE    (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
+#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
+/* RTC_CNTL_IN_WAKEUP_STATE :  ;bitpos:[21] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of wakeup process.*/
+#define RTC_CNTL_IN_WAKEUP_STATE    (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
+#define RTC_CNTL_IN_WAKEUP_STATE_S  21
+/* RTC_CNTL_MAIN_STATE_WAIT_END :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: rtc main state machine has been waited for some cycles.*/
+#define RTC_CNTL_MAIN_STATE_WAIT_END    (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
+#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
+/* RTC_CNTL_RDY_FOR_WAKEUP :  ;bitpos:[19] ;default: 1'b0 ; */
+/*description: rtc is ready to receive wake up trigger from wake up source.*/
+#define RTC_CNTL_RDY_FOR_WAKEUP    (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
+#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
+/* RTC_CNTL_MAIN_STATE_PLL_ON :  ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc main state machine is in states that pll should be running.*/
+#define RTC_CNTL_MAIN_STATE_PLL_ON    (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
+#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
+/* RTC_CNTL_MAIN_STATE_XTAL_ISO :  ;bitpos:[17] ;default: 1'b0 ; */
+/*description: no use any more.*/
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO    (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
+/* RTC_CNTL_COCPU_STATE_DONE :  ;bitpos:[16] ;default: 1'b0 ; */
+/*description: ulp/cocpu is done.*/
+#define RTC_CNTL_COCPU_STATE_DONE    (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
+#define RTC_CNTL_COCPU_STATE_DONE_S  16
+/* RTC_CNTL_COCPU_STATE_SLP :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: ulp/cocpu is in sleep state.*/
+#define RTC_CNTL_COCPU_STATE_SLP    (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
+#define RTC_CNTL_COCPU_STATE_SLP_S  15
+/* RTC_CNTL_COCPU_STATE_SWITCH :  ;bitpos:[14] ;default: 1'b0 ; */
+/*description: ulp/cocpu is about to working. Switch rtc main state.*/
+#define RTC_CNTL_COCPU_STATE_SWITCH    (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
+#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
+/* RTC_CNTL_COCPU_STATE_START :  ;bitpos:[13] ;default: 1'b0 ; */
+/*description: ulp/cocpu should start to work.*/
+#define RTC_CNTL_COCPU_STATE_START    (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_V  0x1
+#define RTC_CNTL_COCPU_STATE_START_S  13
+/* RTC_CNTL_TOUCH_STATE_DONE :  ;bitpos:[12] ;default: 1'b0 ; */
+/*description: touch is done.*/
+#define RTC_CNTL_TOUCH_STATE_DONE    (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
+#define RTC_CNTL_TOUCH_STATE_DONE_S  12
+/* RTC_CNTL_TOUCH_STATE_SLP :  ;bitpos:[11] ;default: 1'b0 ; */
+/*description: touch is in sleep state.*/
+#define RTC_CNTL_TOUCH_STATE_SLP    (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SLP_S  11
+/* RTC_CNTL_TOUCH_STATE_SWITCH :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: touch is about to working. Switch rtc main state.*/
+#define RTC_CNTL_TOUCH_STATE_SWITCH    (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
+/* RTC_CNTL_TOUCH_STATE_START :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: touch should start to work.*/
+#define RTC_CNTL_TOUCH_STATE_START    (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_V  0x1
+#define RTC_CNTL_TOUCH_STATE_START_S  9
+/* RTC_CNTL_XPD_DIG :  ;bitpos:[8] ;default: 1'b0 ; */
+/*description: digital wrap power down.*/
+#define RTC_CNTL_XPD_DIG    (BIT(8))
+#define RTC_CNTL_XPD_DIG_M  (BIT(8))
+#define RTC_CNTL_XPD_DIG_V  0x1
+#define RTC_CNTL_XPD_DIG_S  8
+
+#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0xC0)
+/* RTC_CNTL_LOW_POWER_DIAG1 :  ;bitpos:[31:0] ;default: 0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_LOW_POWER_DIAG1    0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
+#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_S  0
+
+#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xC4)
+/* RTC_CNTL_GPIO_PIN5_HOLD :  ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_HOLD    (BIT(5))
+#define RTC_CNTL_GPIO_PIN5_HOLD_M  (BIT(5))
+#define RTC_CNTL_GPIO_PIN5_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN5_HOLD_S  5
+/* RTC_CNTL_GPIO_PIN4_HOLD :  ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_HOLD    (BIT(4))
+#define RTC_CNTL_GPIO_PIN4_HOLD_M  (BIT(4))
+#define RTC_CNTL_GPIO_PIN4_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN4_HOLD_S  4
+/* RTC_CNTL_GPIO_PIN3_HOLD :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_HOLD    (BIT(3))
+#define RTC_CNTL_GPIO_PIN3_HOLD_M  (BIT(3))
+#define RTC_CNTL_GPIO_PIN3_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN3_HOLD_S  3
+/* RTC_CNTL_GPIO_PIN2_HOLD :  ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_HOLD    (BIT(2))
+#define RTC_CNTL_GPIO_PIN2_HOLD_M  (BIT(2))
+#define RTC_CNTL_GPIO_PIN2_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN2_HOLD_S  2
+/* RTC_CNTL_GPIO_PIN1_HOLD :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_HOLD    (BIT(1))
+#define RTC_CNTL_GPIO_PIN1_HOLD_M  (BIT(1))
+#define RTC_CNTL_GPIO_PIN1_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN1_HOLD_S  1
+/* RTC_CNTL_GPIO_PIN0_HOLD :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_HOLD    (BIT(0))
+#define RTC_CNTL_GPIO_PIN0_HOLD_M  (BIT(0))
+#define RTC_CNTL_GPIO_PIN0_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN0_HOLD_S  0
+
+#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xC8)
+/* RTC_CNTL_DIG_PAD_HOLD :  ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DIG_PAD_HOLD    0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
+#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_S  0
+
+#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0xCC)
+/* RTC_CNTL_BROWN_OUT_DET :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BROWN_OUT_DET    (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_V  0x1
+#define RTC_CNTL_BROWN_OUT_DET_S  31
+/* RTC_CNTL_BROWN_OUT_ENA :  ;bitpos:[30] ;default: 1'b1 ; */
+/*description: enable brown out.*/
+#define RTC_CNTL_BROWN_OUT_ENA    (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_ENA_S  30
+/* RTC_CNTL_BROWN_OUT_CNT_CLR :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: clear brown out counter.*/
+#define RTC_CNTL_BROWN_OUT_CNT_CLR    (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
+/* RTC_CNTL_BROWN_OUT_ANA_RST_EN :  ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN    (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
+/* RTC_CNTL_BROWN_OUT_RST_SEL :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 1:  4-pos reset.*/
+#define RTC_CNTL_BROWN_OUT_RST_SEL    (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
+/* RTC_CNTL_BROWN_OUT_RST_ENA :  ;bitpos:[26] ;default: 1'b0 ; */
+/*description: enable brown out reset.*/
+#define RTC_CNTL_BROWN_OUT_RST_ENA    (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
+/* RTC_CNTL_BROWN_OUT_RST_WAIT :  ;bitpos:[25:16] ;default: 10'h3ff ; */
+/*description: brown out reset wait cycles.*/
+#define RTC_CNTL_BROWN_OUT_RST_WAIT    0x000003FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
+/* RTC_CNTL_BROWN_OUT_PD_RF_ENA :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable power down RF when brown out happens.*/
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA    (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
+/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA :  ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable close flash when brown out happens.*/
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA    (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
+/* RTC_CNTL_BROWN_OUT_INT_WAIT :  ;bitpos:[13:4] ;default: 10'h1 ; */
+/*description: brown out interrupt wait cycles.*/
+#define RTC_CNTL_BROWN_OUT_INT_WAIT    0x000003FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
+
+#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0xD0)
+/* RTC_CNTL_TIMER_VALUE1_LOW :  ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits.*/
+#define RTC_CNTL_TIMER_VALUE1_LOW    0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
+#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0xD4)
+/* RTC_CNTL_TIMER_VALUE1_HIGH :  ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits.*/
+#define RTC_CNTL_TIMER_VALUE1_HIGH    0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
+
+#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xD8)
+/* RTC_CNTL_IO_MUX_RESET_DISABLE :  ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_IO_MUX_RESET_DISABLE    (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
+
+#define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0xDC)
+/* RTC_CNTL_REJECT_CAUSE :  ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: sleep reject cause.*/
+#define RTC_CNTL_REJECT_CAUSE    0x0003FFFF
+#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
+#define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
+#define RTC_CNTL_REJECT_CAUSE_S  0
+
+#define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0xE0)
+/* RTC_CNTL_FORCE_DOWNLOAD_BOOT :  ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT    (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
+
+#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0xE4)
+/* RTC_CNTL_WAKEUP_CAUSE :  ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: sleep wakeup cause.*/
+#define RTC_CNTL_WAKEUP_CAUSE    0x0001FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
+#define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_S  0
+
+#define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0xE8)
+/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE :  ;bitpos:[31:8] ;default: 24'd200 ; */
+/*description: sleep cycles for ULP-coprocessor timer.*/
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE    0x00FFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
+
+#define RTC_CNTL_INT_ENA_RTC_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0xEC)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S  20
+/* RTC_CNTL_SWD_INT_ENA_W1TS :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA_W1TS    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
+/* RTC_CNTL_WDT_INT_ENA_W1TS :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA_W1TS    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
+
+#define RTC_CNTL_INT_ENA_RTC_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0xF0)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC :  ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC    (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S  20
+/* RTC_CNTL_SWD_INT_ENA_W1TC :  ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA_W1TC    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC :  ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC :  ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
+/* RTC_CNTL_WDT_INT_ENA_W1TC :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA_W1TC    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC :  ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
+
+#define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0xF4)
+/* RTC_CNTL_RETENTION_WAIT :  ;bitpos:[31:27] ;default: 5'd20 ; */
+/*description: wait cycles for rention operation.*/
+#define RTC_CNTL_RETENTION_WAIT    0x0000001F
+#define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
+#define RTC_CNTL_RETENTION_WAIT_V  0x1F
+#define RTC_CNTL_RETENTION_WAIT_S  27
+/* RTC_CNTL_RETENTION_EN :  ;bitpos:[26] ;default: 1'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_RETENTION_EN    (BIT(26))
+#define RTC_CNTL_RETENTION_EN_M  (BIT(26))
+#define RTC_CNTL_RETENTION_EN_V  0x1
+#define RTC_CNTL_RETENTION_EN_S  26
+/* RTC_CNTL_RETENTION_CLKOFF_WAIT :  ;bitpos:[25:22] ;default: 4'd3 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT    0x0000000F
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  22
+/* RTC_CNTL_RETENTION_DONE_WAIT :  ;bitpos:[21:19] ;default: 3'd2 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_RETENTION_DONE_WAIT    0x00000007
+#define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
+#define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
+#define RTC_CNTL_RETENTION_DONE_WAIT_S  19
+/* RTC_CNTL_RETENTION_CLK_SEL :  ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_RETENTION_CLK_SEL    (BIT(18))
+#define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(18))
+#define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
+#define RTC_CNTL_RETENTION_CLK_SEL_S  18
+
+#define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0xF8)
+/* RTC_CNTL_FIB_SEL :  ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: select use analog fib signal.*/
+#define RTC_CNTL_FIB_SEL    0x00000007
+#define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
+#define RTC_CNTL_FIB_SEL_V  0x7
+#define RTC_CNTL_FIB_SEL_S  0
+
+#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
+#define RTC_CNTL_FIB_BOD_RST BIT(1)
+#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
+
+#define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0xFC)
+/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE :  ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE    (BIT(31))
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(31))
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S  31
+/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE :  ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE    (BIT(30))
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(30))
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S  30
+/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE :  ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE    (BIT(29))
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(29))
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S  29
+/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE :  ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE    (BIT(28))
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(28))
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S  28
+/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE :  ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE    (BIT(27))
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(27))
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S  27
+/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE :  ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE    (BIT(26))
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(26))
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S  26
+/* RTC_CNTL_GPIO_PIN0_INT_TYPE :  ;bitpos:[25:23] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S  23
+/* RTC_CNTL_GPIO_PIN1_INT_TYPE :  ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S  20
+/* RTC_CNTL_GPIO_PIN2_INT_TYPE :  ;bitpos:[19:17] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S  17
+/* RTC_CNTL_GPIO_PIN3_INT_TYPE :  ;bitpos:[16:14] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S  14
+/* RTC_CNTL_GPIO_PIN4_INT_TYPE :  ;bitpos:[13:11] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S  11
+/* RTC_CNTL_GPIO_PIN5_INT_TYPE :  ;bitpos:[10:8] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE    0x00000007
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S  8
+/* RTC_CNTL_GPIO_PIN_CLK_GATE :  ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN_CLK_GATE    (BIT(7))
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_M  (BIT(7))
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_V  0x1
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_S  7
+/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR :  ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR    (BIT(6))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M  (BIT(6))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S  6
+/* RTC_CNTL_GPIO_WAKEUP_STATUS :  ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_WAKEUP_STATUS    0x0000003F
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_M  ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_V  0x3F
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_S  0
+
+#define RTC_CNTL_DBG_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x100)
+/* RTC_CNTL_DEBUG_SEL4 :  ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL4    0x0000001F
+#define RTC_CNTL_DEBUG_SEL4_M  ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S))
+#define RTC_CNTL_DEBUG_SEL4_V  0x1F
+#define RTC_CNTL_DEBUG_SEL4_S  27
+/* RTC_CNTL_DEBUG_SEL3 :  ;bitpos:[26:22] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL3    0x0000001F
+#define RTC_CNTL_DEBUG_SEL3_M  ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S))
+#define RTC_CNTL_DEBUG_SEL3_V  0x1F
+#define RTC_CNTL_DEBUG_SEL3_S  22
+/* RTC_CNTL_DEBUG_SEL2 :  ;bitpos:[21:17] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL2    0x0000001F
+#define RTC_CNTL_DEBUG_SEL2_M  ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S))
+#define RTC_CNTL_DEBUG_SEL2_V  0x1F
+#define RTC_CNTL_DEBUG_SEL2_S  17
+/* RTC_CNTL_DEBUG_SEL1 :  ;bitpos:[16:12] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL1    0x0000001F
+#define RTC_CNTL_DEBUG_SEL1_M  ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S))
+#define RTC_CNTL_DEBUG_SEL1_V  0x1F
+#define RTC_CNTL_DEBUG_SEL1_S  12
+/* RTC_CNTL_DEBUG_SEL0 :  ;bitpos:[11:7] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_SEL0    0x0000001F
+#define RTC_CNTL_DEBUG_SEL0_M  ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S))
+#define RTC_CNTL_DEBUG_SEL0_V  0x1F
+#define RTC_CNTL_DEBUG_SEL0_S  7
+/* RTC_CNTL_DEBUG_BIT_SEL :  ;bitpos:[6:2] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_BIT_SEL    0x0000001F
+#define RTC_CNTL_DEBUG_BIT_SEL_M  ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S))
+#define RTC_CNTL_DEBUG_BIT_SEL_V  0x1F
+#define RTC_CNTL_DEBUG_BIT_SEL_S  2
+/* RTC_CNTL_DEBUG_12M_NO_GATING :  ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DEBUG_12M_NO_GATING    (BIT(1))
+#define RTC_CNTL_DEBUG_12M_NO_GATING_M  (BIT(1))
+#define RTC_CNTL_DEBUG_12M_NO_GATING_V  0x1
+#define RTC_CNTL_DEBUG_12M_NO_GATING_S  1
+
+#define RTC_CNTL_DBG_MAP_REG          (DR_REG_RTCCNTL_BASE + 0x104)
+/* RTC_CNTL_GPIO_PIN0_FUN_SEL :  ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S  28
+/* RTC_CNTL_GPIO_PIN1_FUN_SEL :  ;bitpos:[27:24] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S  24
+/* RTC_CNTL_GPIO_PIN2_FUN_SEL :  ;bitpos:[23:20] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S  20
+/* RTC_CNTL_GPIO_PIN3_FUN_SEL :  ;bitpos:[19:16] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S  16
+/* RTC_CNTL_GPIO_PIN4_FUN_SEL :  ;bitpos:[15:12] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S  12
+/* RTC_CNTL_GPIO_PIN5_FUN_SEL :  ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL    0x0000000F
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S  8
+/* RTC_CNTL_GPIO_PIN0_MUX_SEL :  ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL    (BIT(7))
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M  (BIT(7))
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S  7
+/* RTC_CNTL_GPIO_PIN1_MUX_SEL :  ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL    (BIT(6))
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M  (BIT(6))
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S  6
+/* RTC_CNTL_GPIO_PIN2_MUX_SEL :  ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL    (BIT(5))
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M  (BIT(5))
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S  5
+/* RTC_CNTL_GPIO_PIN3_MUX_SEL :  ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL    (BIT(4))
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M  (BIT(4))
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S  4
+/* RTC_CNTL_GPIO_PIN4_MUX_SEL :  ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL    (BIT(3))
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M  (BIT(3))
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S  3
+/* RTC_CNTL_GPIO_PIN5_MUX_SEL :  ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL    (BIT(2))
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M  (BIT(2))
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S  2
+
+#define RTC_CNTL_SENSOR_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x108)
+/* RTC_CNTL_FORCE_XPD_SAR :  ;bitpos:[31:30] ;default: 2'b0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_FORCE_XPD_SAR    0x00000003
+#define RTC_CNTL_FORCE_XPD_SAR_M  ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S))
+#define RTC_CNTL_FORCE_XPD_SAR_V  0x3
+#define RTC_CNTL_FORCE_XPD_SAR_S  30
+/* RTC_CNTL_SAR2_PWDET_CCT :  ;bitpos:[29:27] ;default: 3'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SAR2_PWDET_CCT    0x00000007
+#define RTC_CNTL_SAR2_PWDET_CCT_M  ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S))
+#define RTC_CNTL_SAR2_PWDET_CCT_V  0x7
+#define RTC_CNTL_SAR2_PWDET_CCT_S  27
+
+#define RTC_CNTL_DBG_SAR_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x10C)
+/* RTC_CNTL_SAR_DEBUG_SEL :  ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_SAR_DEBUG_SEL    0x0000001F
+#define RTC_CNTL_SAR_DEBUG_SEL_M  ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S))
+#define RTC_CNTL_SAR_DEBUG_SEL_V  0x1F
+#define RTC_CNTL_SAR_DEBUG_SEL_S  27
+
+#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x1FC)
+/* RTC_CNTL_DATE :  ;bitpos:[27:0] ;default: 28'h2107190 ; */
+/*description: Need add desc.*/
+#define RTC_CNTL_DATE    0x0FFFFFFF
+#define RTC_CNTL_DATE_M  ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S))
+#define RTC_CNTL_DATE_V  0xFFFFFFF
+#define RTC_CNTL_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_CNTL_REG_H_ */
diff --git a/components/soc/esp32c2/register/soc/rtc_cntl_struct.h b/components/soc/esp32c2/register/soc/rtc_cntl_struct.h
new file mode 100644
index 00000000000..5252040c3f0
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/rtc_cntl_struct.h
@@ -0,0 +1,708 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct rtc_cntl_dev_s{
+    union {
+        struct {
+            uint32_t reserved0                     :    2;  /*Reserved*/
+            uint32_t sw_stall_procpu_c0            :    2;  /*{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
+            uint32_t reserved4                     :    1;  /*Reserved*/
+            uint32_t sw_procpu_rst                 :    1;  /*PRO CPU SW reset*/
+            uint32_t bb_i2c_force_pd               :    1;  /*BB_I2C force power down*/
+            uint32_t bb_i2c_force_pu               :    1;  /*BB_I2C force power up*/
+            uint32_t bbpll_i2c_force_pd            :    1;  /*BB_PLL _I2C force power down*/
+            uint32_t bbpll_i2c_force_pu            :    1;  /*BB_PLL_I2C force power up*/
+            uint32_t bbpll_force_pd                :    1;  /*BB_PLL force power down*/
+            uint32_t bbpll_force_pu                :    1;  /*BB_PLL force power up*/
+            uint32_t xtl_force_pd                  :    1;  /*crystall force power down*/
+            uint32_t xtl_force_pu                  :    1;  /*crystall force power up*/
+            uint32_t xtl_en_wait                   :    4;  /*wait bias_sleep and current source wakeup*/
+            uint32_t reserved18                    :    2;  /*Reserved*/
+            uint32_t ctr_sel                       :    3;  /*Need add desc*/
+            uint32_t reserved23                    :    2;  /*Reserved*/
+            uint32_t analog_force_iso              :    1;  /*Need add desc*/
+            uint32_t reserved26                    :    2;  /*Reserved*/
+            uint32_t analog_force_noiso            :    1;  /*Need add desc*/
+            uint32_t dg_wrap_force_rst             :    1;  /*digital wrap force reset in deep sleep*/
+            uint32_t dg_wrap_force_norst           :    1;  /*digital core force no reset in deep sleep*/
+            uint32_t sw_sys_rst                    :    1;  /*SW system reset*/
+        };
+        uint32_t val;
+    } options0;
+    uint32_t slp_timer0;
+    union {
+        struct {
+            uint32_t slp_val_hi                    :    16;  /*RTC sleep timer high 16 bits*/
+            uint32_t main_timer_alarm_en           :    1;  /*timer alarm enable bit*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } slp_timer1;
+    union {
+        struct {
+            uint32_t reserved0                     :    27;  /*Reserved*/
+            uint32_t timer_sys_stall               :    1;  /*Enable to record system stall time*/
+            uint32_t timer_xtl_off                 :    1;  /*Enable to record 40M XTAL OFF time*/
+            uint32_t timer_sys_rst                 :    1;  /*enable to record system reset time*/
+            uint32_t reserved30                    :    1;  /*Reserved*/
+            uint32_t update                        :    1;  /*Set 1: to update register with RTC timer*/
+        };
+        uint32_t val;
+    } time_update;
+    uint32_t time_low0;
+    union {
+        struct {
+            uint32_t rtc_timer_value0_high         :    16;  /*RTC timer high 16 bits*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } time_high0;
+    union {
+        struct {
+            uint32_t rtc_sw_cpu_int                :    1;  /*rtc software interrupt to main cpu*/
+            uint32_t rtc_slp_reject_cause_clr      :    1;  /*clear rtc sleep reject cause*/
+            uint32_t reserved2                     :    20;  /*Reserved*/
+            uint32_t apb2rtc_bridge_sel            :    1;  /*1: APB to RTC using bridge*/
+            uint32_t reserved23                    :    5;  /*Reserved*/
+            uint32_t sdio_active_ind               :    1;  /*SDIO active indication*/
+            uint32_t slp_wakeup                    :    1;  /*leep wakeup bit*/
+            uint32_t slp_reject                    :    1;  /*leep reject bit*/
+            uint32_t sleep_en                      :    1;  /*sleep enable bit*/
+        };
+        uint32_t val;
+    } state0;
+    union {
+        struct {
+            uint32_t cpu_stall_en                  :    1;  /*CPU stall enable bit*/
+            uint32_t cpu_stall_wait                :    5;  /*CPU stall wait cycles in fast_clk_rtc*/
+            uint32_t ck8m_wait                     :    8;  /*CK8M wait cycles in slow_clk_rtc*/
+            uint32_t xtl_buf_wait                  :    10;  /*XTAL wait cycles in slow_clk_rtc*/
+            uint32_t pll_buf_wait                  :    8;  /*PLL wait cycles in slow_clk_rtc*/
+        };
+        uint32_t val;
+    } timer1;
+    union {
+        struct {
+            uint32_t reserved0                     :    24;  /*Reserved*/
+            uint32_t min_time_ck8m_off             :    8;  /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
+        };
+        uint32_t val;
+    } timer2;
+    union {
+        struct {
+            uint32_t reserved0                     :    16;  /*Reserved*/
+            uint32_t dg_wrap_wait_timer            :    9;  /*Need add desc*/
+            uint32_t dg_wrap_powerup_timer         :    7;  /*Need add desc*/
+        };
+        uint32_t val;
+    } timer4;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*Reserved*/
+            uint32_t min_slp_val                   :    8;  /*minimal sleep cycles in slow_clk_rtc*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } timer5;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*Reserved*/
+            uint32_t i2c_reset_por_force_pd        :    1;  /*Need add desc*/
+            uint32_t i2c_reset_por_force_pu        :    1;  /*Need add desc*/
+            uint32_t reserved20                    :    2;  /*ReservedPLLA force power down*/
+            uint32_t sar_i2c_pu                    :    1;  /*PLLA force power up*/
+            uint32_t reserved23                    :    2;  /*Reserved*/
+            uint32_t bbpll_cal_slp_start           :    1;  /*start BBPLL calibration during sleep*/
+            uint32_t reserved26                    :    1;  /*Reserved*/
+            uint32_t txrf_i2c_pu                   :    1;  /*1: TXRF_I2C power up*/
+            uint32_t rfrx_pbus_pu                  :    1;  /*1: RFRX_PBUS power up*/
+            uint32_t reserved29                    :    1;  /*Reserved*/
+            uint32_t ckgen_i2c_pu                  :    1;  /*1: CKGEN_I2C power up*/
+            uint32_t pll_i2c_pu                    :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } ana_conf;
+    union {
+        struct {
+            uint32_t reset_cause_procpu            :    6;  /*reset cause of PRO CPU*/
+            uint32_t reserved6                     :    7;  /*Reserved*/
+            uint32_t stat_vector_sel_procpu        :    1;  /*PRO CPU state vector sel*/
+            uint32_t reserved14                    :    5;  /*Reserved*/
+            uint32_t ocd_halt_on_reset_procpu      :    1;  /*PROCPU OcdHaltOnReset*/
+            uint32_t rtc_dreset_mask_procpu        :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } reset_state;
+    union {
+        struct {
+            uint32_t reserved0                     :    15;  /*Reserved*/
+            uint32_t rtc_wakeup_ena                :    17;  /*wakeup enable bitmap*/
+        };
+        uint32_t val;
+    } wakeup_state;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject                    :    1;  /*enable sleep reject interrupt*/
+            uint32_t reserved2                     :    1;  /*Reservedenable SDIO idle interrupt*/
+            uint32_t rtc_wdt                       :    1;  /*enable RTC WDT interrupt*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t rtc_brown_out                 :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer                :    1;  /*enable RTC main timer interrupt*/
+            uint32_t reserved11                    :    4;  /*Reservedenable saradc2 interrupt*/
+            uint32_t rtc_swd                       :    1;  /*enable super watch dog interrupt*/
+            uint32_t reserved16                    :    4;  /*Reservedenable touch timeout interrupt*/
+            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt raw*/
+            uint32_t slp_reject                    :    1;  /*sleep reject interrupt raw*/
+            uint32_t reserved2                     :    1;  /*ReservedSDIO idle interrupt raw*/
+            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt raw*/
+            uint32_t reserved4                     :    5;  /*Reservedtouch inactive interrupt raw*/
+            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt raw*/
+            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt raw*/
+            uint32_t reserved11                    :    4;  /*Reservedsaradc2 interrupt raw*/
+            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt raw*/
+            uint32_t reserved16                    :    4;  /*Reservedtouch timeout interrupt raw*/
+            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt state*/
+            uint32_t slp_reject                    :    1;  /*sleep reject interrupt state*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt state*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt state*/
+            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt state*/
+            uint32_t reserved11                    :    4;  /*Reserved*/
+            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt state*/
+            uint32_t reserved16                    :    4;  /*Reserved*/
+            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*Clear sleep wakeup interrupt state*/
+            uint32_t slp_reject                    :    1;  /*Clear sleep reject interrupt state*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t rtc_wdt                       :    1;  /*Clear RTC WDT interrupt state*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t rtc_brown_out                 :    1;  /*Clear brown out interrupt state*/
+            uint32_t rtc_main_timer                :    1;  /*Clear RTC main timer interrupt state*/
+            uint32_t reserved11                    :    4;  /*Reserved*/
+            uint32_t rtc_swd                       :    1;  /*Clear super watch dog interrupt state*/
+            uint32_t reserved16                    :    4;  /*Reserved*/
+            uint32_t rtc_bbpll_cal                 :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t store[4];
+    union {
+        struct {
+            uint32_t reserved0                     :    30;  /*Reserved*/
+            uint32_t ctr_lv                        :    1;  /*0: power down XTAL at high level*/
+            uint32_t ctr_en                        :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } ext_xtl_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    31;  /*Reserved*/
+            uint32_t gpio_wakeup_filter            :    1;  /*enable filter for gpio wakeup event*/
+        };
+        uint32_t val;
+    } ext_wakeup_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    12;  /*Reserved*/
+            uint32_t rtc_sleep_reject_ena          :    18;  /*sleep reject enable*/
+            uint32_t light_slp_reject_en           :    1;  /*enable reject for light sleep*/
+            uint32_t deep_slp_reject_en            :    1;  /*enable reject for deep sleep*/
+        };
+        uint32_t val;
+    } slp_reject_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    29;  /*Reserved*/
+            uint32_t cpusel_conf                   :    1;  /*CPU sel option*/
+            uint32_t cpuperiod_sel                 :    2;  /*Need add desc*/
+        };
+        uint32_t val;
+    } cpu_period_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*Reserved*/
+            uint32_t efuse_clk_force_gating        :    1;  /*Need add desc*/
+            uint32_t efuse_clk_force_nogating      :    1;  /*Need add desc*/
+            uint32_t ck8m_div_sel_vld              :    1;  /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
+            uint32_t ck8m_div                      :    2;  /*CK8M_D256_OUT divider. 00: div128*/
+            uint32_t enb_ck8m                      :    1;  /*disable CK8M and CK8M_D256_OUT*/
+            uint32_t enb_ck8m_div                  :    1;  /*1: CK8M_D256_OUT is actually CK8M*/
+            uint32_t dig_xtal32k_en                :    1;  /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_d256_en             :    1;  /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_en                  :    1;  /*enable CK8M for digital core (no relationship with RTC core)*/
+            uint32_t reserved11                    :    1;  /*Reserved*/
+            uint32_t ck8m_div_sel                  :    3;  /*divider = reg_ck8m_div_sel + 1*/
+            uint32_t xtal_force_nogating           :    1;  /*XTAL force no gating during sleep*/
+            uint32_t ck8m_force_nogating           :    1;  /*CK8M force no gating during sleep*/
+            uint32_t ck8m_dfreq                    :    8;  /*CK8M_DFREQ*/
+            uint32_t ck8m_force_pd                 :    1;  /*CK8M force power down*/
+            uint32_t ck8m_force_pu                 :    1;  /*CK8M force power up*/
+            uint32_t xtal_global_force_gating      :    1;  /*Need add desc*/
+            uint32_t xtal_global_force_nogating    :    1;  /*Need add desc*/
+            uint32_t fast_clk_rtc_sel              :    1;  /*fast_clk_rtc sel. 0: XTAL div 2*/
+            uint32_t ana_clk_rtc_sel               :    2;  /*Need add desc*/
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    22;  /*Reserved*/
+            uint32_t rtc_ana_clk_div_vld           :    1;  /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
+            uint32_t rtc_ana_clk_div               :    8;  /*Need add desc*/
+            uint32_t slow_clk_next_edge            :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } slow_clk_conf;
+    union {
+        struct {
+            uint32_t dg_vdd_drv_b_slp              :    8;  /*Need add desc*/
+            uint32_t dg_vdd_drv_b_slp_en           :    1;  /*Need add desc*/
+            uint32_t reserved9                     :    1;  /*Reserved*/
+            uint32_t bias_buf_idle                 :    1;  /*Need add desc*/
+            uint32_t bias_buf_wake                 :    1;  /*Need add desc*/
+            uint32_t bias_buf_deep_slp             :    1;  /*Need add desc*/
+            uint32_t bias_buf_monitor              :    1;  /*Need add desc*/
+            uint32_t pd_cur_deep_slp               :    1;  /*xpd cur when rtc in sleep_state*/
+            uint32_t pd_cur_monitor                :    1;  /*xpd cur when rtc in monitor state*/
+            uint32_t bias_sleep_deep_slp           :    1;  /*bias_sleep when rtc in sleep_state*/
+            uint32_t bias_sleep_monitor            :    1;  /*bias_sleep when rtc in monitor state*/
+            uint32_t dbg_atten_deep_slp            :    4;  /*DBG_ATTEN when rtc in sleep state*/
+            uint32_t dbg_atten_monitor             :    4;  /*DBG_ATTEN when rtc in active state*/
+            uint32_t dbg_atten_active              :    4;  /*Need add desc*/
+            uint32_t reserved30                    :    2;  /*Reserved*/
+        };
+        uint32_t val;
+    } bias_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;  /*Reserved*/
+            uint32_t dig_cal_en                    :    1;  /*Need add desc*/
+            uint32_t reserved8                     :    6;  /*Reserved*/
+            uint32_t sck_dcap                      :    8;  /*SCK_DCAP*/
+            uint32_t reserved22                    :    8;  /*Reserved*/
+            uint32_t rtculator_force_pd            :    1;  /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
+            uint32_t rtculator_force_pu            :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } rtc;
+    union {
+        struct {
+            uint32_t reserved0                     :    21;  /*Reserved*/
+            uint32_t rtc_pad_force_hold            :    1;  /*rtc pad force hold*/
+            uint32_t reserved22                    :    10;  /*Reserved*/
+        };
+        uint32_t val;
+    } pwc;
+    union {
+        struct {
+            uint32_t vdd_spi_pwr_drv               :    2;  /*Need add desc*/
+            uint32_t vdd_spi_pwr_force             :    1;  /*Need add desc*/
+            uint32_t vdd_spi_pd_en                 :    1;  /*Need add desc*/
+            uint32_t lslp_mem_force_pd             :    1;  /*memories in digital core force PD in sleep*/
+            uint32_t lslp_mem_force_pu             :    1;  /*memories in digital core force no PD in sleep*/
+            uint32_t reserved6                     :    13;  /*Reserved*/
+            uint32_t dg_wrap_force_pd              :    1;  /*digital core force power down*/
+            uint32_t dg_wrap_force_pu              :    1;  /*digital core force power up*/
+            uint32_t reserved21                    :    10;  /*Reserved*/
+            uint32_t dg_wrap_pd_en                 :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dig_pwc;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;  /*Reserved*/
+            uint32_t dig_iso_force_off             :    1;  /*Need add desc*/
+            uint32_t dig_iso_force_on              :    1;  /*Need add desc*/
+            uint32_t dg_pad_autohold               :    1;  /*read only register to indicate digital pad auto-hold status*/
+            uint32_t clr_dg_pad_autohold           :    1;  /*wtite only register to clear digital pad auto-hold*/
+            uint32_t dg_pad_autohold_en            :    1;  /*digital pad enable auto-hold*/
+            uint32_t dg_pad_force_noiso            :    1;  /*digital pad force no ISO*/
+            uint32_t dg_pad_force_iso              :    1;  /*digital pad force ISO*/
+            uint32_t dg_pad_force_unhold           :    1;  /*digital pad force un-hold*/
+            uint32_t dg_pad_force_hold             :    1;  /*digital pad force hold*/
+            uint32_t reserved16                    :    14;  /*Reserved*/
+            uint32_t dg_wrap_force_iso             :    1;  /*digital core force ISO*/
+            uint32_t dg_wrap_force_noiso           :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dig_iso;
+    union {
+        struct {
+            uint32_t chip_reset_width              :    8;  /*chip reset siginal pulse width*/
+            uint32_t chip_reset_en                 :    1;  /*wdt reset whole chip enable*/
+            uint32_t pause_in_slp                  :    1;  /*pause WDT in sleep*/
+            uint32_t reserved10                    :    1;  /*Reservedenable WDT reset APP CPU*/
+            uint32_t procpu_reset_en               :    1;  /*enable WDT reset PRO CPU*/
+            uint32_t flashboot_mod_en              :    1;  /*enable WDT in flash boot*/
+            uint32_t sys_reset_length              :    3;  /*system reset counter length*/
+            uint32_t cpu_reset_length              :    3;  /*CPU reset counter length*/
+            uint32_t stg3                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg2                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg1                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg0                          :    3;  /*1: interrupt stage en*/
+            uint32_t en                            :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } wdt_config0;
+    uint32_t wdt_config1;
+    uint32_t wdt_config2;
+    uint32_t wdt_config3;
+    uint32_t wdt_config4;
+    union {
+        struct {
+            uint32_t reserved0                     :    31;  /*Reserved*/
+            uint32_t feed                          :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } wdt_feed;
+    uint32_t wdt_wprotect;
+    union {
+        struct {
+            uint32_t swd_reset_flag                :    1;  /*swd reset flag*/
+            uint32_t swd_feed_int                  :    1;  /*swd interrupt for feeding*/
+            uint32_t reserved2                     :    15;  /*Reserved*/
+            uint32_t swd_bypass_rst                :    1;  /*Need add desc*/
+            uint32_t swd_signal_width              :    10;  /*adjust signal width send to swd*/
+            uint32_t swd_rst_flag_clr              :    1;  /*reset swd reset flag*/
+            uint32_t swd_feed                      :    1;  /*Sw feed swd*/
+            uint32_t swd_disable                   :    1;  /*disable SWD*/
+            uint32_t swd_auto_feed_en              :    1;  /*automatically feed swd when int comes*/
+        };
+        uint32_t val;
+    } swd_conf;
+    uint32_t swd_wprotect;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;  /*Reserved*/
+            uint32_t procpu_c1                     :    6;  /*Need add desc*/
+        };
+        uint32_t val;
+    } sw_cpu_stall;
+    uint32_t store4;
+    uint32_t store5;
+    uint32_t store6;
+    uint32_t store7;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*Reserveddigital wrap iso*/
+            uint32_t xpd_dig                       :    1;  /*digital wrap power down*/
+            uint32_t rtc_touch_state_start         :    1;  /*touch should start to work*/
+            uint32_t rtc_touch_state_switch        :    1;  /*touch is about to working. Switch rtc main state*/
+            uint32_t rtc_touch_state_slp           :    1;  /*touch is in sleep state*/
+            uint32_t rtc_touch_state_done          :    1;  /*touch is done*/
+            uint32_t rtc_cocpu_state_start         :    1;  /*ulp/cocpu should start to work*/
+            uint32_t rtc_cocpu_state_switch        :    1;  /*ulp/cocpu is about to working. Switch rtc main state*/
+            uint32_t rtc_cocpu_state_slp           :    1;  /*ulp/cocpu is in sleep state*/
+            uint32_t rtc_cocpu_state_done          :    1;  /*ulp/cocpu is done*/
+            uint32_t rtc_main_state_xtal_iso       :    1;  /*no use any more*/
+            uint32_t rtc_main_state_pll_on         :    1;  /*rtc main state machine is in states that pll should be running*/
+            uint32_t rtc_rdy_for_wakeup            :    1;  /*rtc is ready to receive wake up trigger from wake up source*/
+            uint32_t rtc_main_state_wait_end       :    1;  /*rtc main state machine has been waited for some cycles*/
+            uint32_t rtc_in_wakeup_state           :    1;  /*rtc main state machine is in the states of wakeup process*/
+            uint32_t rtc_in_low_power_state        :    1;  /*rtc main state machine is in the states of low power*/
+            uint32_t rtc_main_state_in_wait_8m     :    1;  /*rtc main state machine is in wait 8m state*/
+            uint32_t rtc_main_state_in_wait_pll    :    1;  /*rtc main state machine is in wait pll state*/
+            uint32_t rtc_main_state_in_wait_xtl    :    1;  /*rtc main state machine is in wait xtal state*/
+            uint32_t rtc_main_state_in_slp         :    1;  /*rtc main state machine is in sleep state*/
+            uint32_t rtc_main_state_in_idle        :    1;  /*rtc main state machine is in idle state*/
+            uint32_t rtc_main_state                :    4;  /*rtc main state machine status*/
+        };
+        uint32_t val;
+    } low_power_st;
+    uint32_t diag0;
+    union {
+        struct {
+            uint32_t rtc_gpio_pin0_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_hold            :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin5_hold            :    1;  /*Need add desc*/
+            uint32_t reserved6                     :    26;  /*Reserved*/
+        };
+        uint32_t val;
+    } pad_hold;
+    uint32_t dig_pad_hold;
+    union {
+        struct {
+            uint32_t reserved0                     :    4;  /*Reserved*/
+            uint32_t int_wait                      :    10;  /*brown out interrupt wait cycles*/
+            uint32_t close_flash_ena               :    1;  /*enable close flash when brown out happens*/
+            uint32_t pd_rf_ena                     :    1;  /*enable power down RF when brown out happens*/
+            uint32_t rst_wait                      :    10;  /*brown out reset wait cycles*/
+            uint32_t rst_ena                       :    1;  /*enable brown out reset*/
+            uint32_t rst_sel                       :    1;  /*1:  4-pos reset*/
+            uint32_t ana_rst_en                    :    1;  /*Need add desc*/
+            uint32_t cnt_clr                       :    1;  /*clear brown out counter*/
+            uint32_t ena                           :    1;  /*enable brown out*/
+            uint32_t det                           :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } brown_out;
+    uint32_t time_low1;
+    union {
+        struct {
+            uint32_t rtc_timer_value1_high         :    16;  /*RTC timer high 16 bits*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } time_high1;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*Reserved*/
+            uint32_t io_mux_reset_disable          :    1;  /*Need add desc*/
+            uint32_t reserved19                    :    13;  /*Reserved*/
+        };
+        uint32_t val;
+    } usb_conf;
+    union {
+        struct {
+            uint32_t reject_cause                  :    18;  /*sleep reject cause*/
+            uint32_t reserved18                    :    14;  /*Reserved*/
+        };
+        uint32_t val;
+    } slp_reject_cause;
+    union {
+        struct {
+            uint32_t force_download_boot           :    1;  /*Need add desc*/
+            uint32_t reserved1                     :    31;  /*Reserved*/
+        };
+        uint32_t val;
+    } option1;
+    union {
+        struct {
+            uint32_t wakeup_cause                  :    17;  /*sleep wakeup cause*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } slp_wakeup_cause;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*Reserved*/
+            uint32_t ulp_cp_timer_slp_cycle        :    24;  /*sleep cycles for ULP-coprocessor timer*/
+        };
+        uint32_t val;
+    } ulp_cp_timer_1;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1ts               :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1ts               :    1;  /*enable sleep reject interrupt*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t rtc_wdt_w1ts                  :    1;  /*enable RTC WDT interrupt*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t w1ts                          :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1ts           :    1;  /*enable RTC main timer interrupt*/
+            uint32_t reserved11                    :    4;  /*Reserved*/
+            uint32_t rtc_swd_w1ts                  :    1;  /*enable super watch dog interrupt*/
+            uint32_t reserved16                    :    4;  /*Reservedenbale gitch det interrupt*/
+            uint32_t rtc_bbpll_cal_w1ts            :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena_w1ts;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1tc               :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1tc               :    1;  /*enable sleep reject interrupt*/
+            uint32_t reserved2                     :    1;  /*Reserved*/
+            uint32_t rtc_wdt_w1tc                  :    1;  /*enable RTC WDT interrupt*/
+            uint32_t reserved4                     :    5;  /*Reserved*/
+            uint32_t w1tc                          :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1tc           :    1;  /*enable RTC main timer interrupt*/
+            uint32_t reserved11                    :    4;  /*Reserved*/
+            uint32_t rtc_swd_w1tc                  :    1;  /*enable super watch dog interrupt*/
+            uint32_t reserved16                    :    4;  /*Reservedenbale gitch det interrupt*/
+            uint32_t rtc_bbpll_cal_w1tc            :    1;  /*Need add desc*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena_w1tc;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*Reserved*/
+            uint32_t retention_clk_sel             :    1;  /*Need add desc*/
+            uint32_t retention_done_wait           :    3;  /*Need add desc*/
+            uint32_t retention_clkoff_wait         :    4;  /*Need add desc*/
+            uint32_t retention_en                  :    1;  /*Need add desc*/
+            uint32_t retention_wait                :    5;  /*wait cycles for rention operation*/
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t rtc_fib_sel                   :    3;  /*select use analog fib signal*/
+            uint32_t reserved3                     :    29;  /*Reserved*/
+        };
+        uint32_t val;
+    } fib_sel;
+    union {
+        struct {
+            uint32_t rtc_gpio_wakeup_status        :    6;  /*Need add desc*/
+            uint32_t rtc_gpio_wakeup_status_clr    :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin_clk_gate         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin5_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin0_int_type        :    3;  /*Need add desc*/
+            uint32_t rtc_gpio_pin5_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_wakeup_enable   :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin0_wakeup_enable   :    1;  /*Need add desc*/
+        };
+        uint32_t val;
+    } gpio_wakeup;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*Reserved*/
+            uint32_t rtc_debug_12m_no_gating       :    1;  /*Need add desc*/
+            uint32_t rtc_debug_bit_sel             :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel0                :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel1                :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel2                :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel3                :    5;  /*Need add desc*/
+            uint32_t rtc_debug_sel4                :    5;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dbg_sel;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;  /*Reserved*/
+            uint32_t rtc_gpio_pin5_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin0_mux_sel         :    1;  /*Need add desc*/
+            uint32_t rtc_gpio_pin5_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin4_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin3_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin2_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin1_fun_sel         :    4;  /*Need add desc*/
+            uint32_t rtc_gpio_pin0_fun_sel         :    4;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dbg_map;
+    union {
+        struct {
+            uint32_t reserved0                     :    27;  /*Reserved*/
+            uint32_t sar2_pwdet_cct                :    3;  /*Need add desc*/
+            uint32_t force_xpd_sar                 :    2;  /*Need add desc*/
+        };
+        uint32_t val;
+    } sensor_ctrl;
+    union {
+        struct {
+            uint32_t reserved0                     :    27;  /*Reserved*/
+            uint32_t sar_debug_sel                 :    5;  /*Need add desc*/
+        };
+        uint32_t val;
+    } dbg_sar_sel;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*Need add desc*/
+            uint32_t reserved28                    :    4;  /*Reserved*/
+        };
+        uint32_t val;
+    } date;
+} rtc_cntl_dev_t;
+extern rtc_cntl_dev_t RTCCNTL;
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/include/soc/sensitive_reg.h b/components/soc/esp32c2/register/soc/sensitive_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/sensitive_reg.h
rename to components/soc/esp32c2/register/soc/sensitive_reg.h
diff --git a/components/soc/esp32c2/include/soc/sensitive_struct.h b/components/soc/esp32c2/register/soc/sensitive_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/sensitive_struct.h
rename to components/soc/esp32c2/register/soc/sensitive_struct.h
diff --git a/components/soc/esp32c2/register/soc/spi_mem_reg.h b/components/soc/esp32c2/register/soc/spi_mem_reg.h
new file mode 100644
index 00000000000..8eeb65b014f
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/spi_mem_reg.h
@@ -0,0 +1,1270 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_MEM_REG_H_
+#define _SOC_SPI_MEM_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
+/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_READ    (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
+bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WREN    (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when the bit is set. The
+ bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WRDI    (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
+e cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDID    (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered when the bit is
+ set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDSR    (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will be triggered when t
+he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
+ble..*/
+#define SPI_MEM_FLASH_WRSR    (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
+tion  will be triggered when the bit is set. The bit will be cleared once the op
+eration done .1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PP    (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
+is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_SE    (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
+ is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_BE    (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_CE    (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
+. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_DP    (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
+e or high performance mode and obtains the devices ID. The bit will be cleared once
+the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RES    (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared once the operation
+done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_HPM    (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when the bit is set.
+ The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_USR    (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode, it is set to indicate that program/erase operation will be trigger
+ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
+peration done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PE    (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+/* SPI_MEM_MSPI_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation
+state, 2: send command state, 3: send address state, 4: wait state, 5: read data st
+ate, 6:write data state, 7: done state, 8: read data end state..*/
+#define SPI_MEM_MSPI_ST    0x0000000F
+#define SPI_MEM_MSPI_ST_M  ((SPI_MEM_MSPI_ST_V)<<(SPI_MEM_MSPI_ST_S))
+#define SPI_MEM_MSPI_ST_V  0xF
+#define SPI_MEM_MSPI_ST_S  4
+/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The current status of SPI1 master FSM..*/
+#define SPI_MEM_MST_ST    0x0000000F
+#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
+#define SPI_MEM_MST_ST_V  0xF
+#define SPI_MEM_MST_ST_S  0
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
+address, the bit24-bit31 are the byte length of a transfer..*/
+#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_QIO    (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_DIO    (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
+isable..*/
+#define SPI_MEM_WRSR_2B    (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
+#define SPI_MEM_WP_REG    (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
+#define SPI_MEM_D_POL    (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
+#define SPI_MEM_Q_POL    (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
+spi_mem_flash_res bit. 1: enable 0: disable..*/
+#define SPI_MEM_RESANDRES    (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
+UT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
+#define SPI_MEM_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+e.*/
+#define SPI_MEM_TX_CRC_EN    (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
+e low..*/
+#define SPI_MEM_FCS_CRC_EN    (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_DUAL    (BIT(7))
+#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_V  0x1
+#define SPI_MEM_FCMD_DUAL_S  7
+/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the dummy phase the signal level of spi is output by the spi controller..*/
+#define SPI_MEM_FDUMMY_OUT    (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_V  0x1
+#define SPI_MEM_FDUMMY_OUT_S  3
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
+/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI0 RX FIFO reset signal..*/
+#define SPI_MEM_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_V  0x1
+#define SPI_MEM_RXFIFO_RST_S  30
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
+/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
+12) SPI_CLK cycles..*/
+#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on..*/
+#define SPI_MEM_CLK_MODE    0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
+/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The FSM will be reset..*/
+#define SPI_MEM_SYNC_RESET    (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
+ clock cycles..*/
+#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: Spi cs signal is delayed to inactive by spi clock this bits are combined with sp
+i_mem_cs_hold bit..*/
+#define SPI_MEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_CS_HOLD_TIME_S  5
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_
+setup bit..*/
+#define SPI_MEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit in 1-division mode..*/
+#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+ system/(spi_mem_clkcnt_N+1).*/
+#define SPI_MEM_CLKCNT_N    0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define SPI_MEM_CLKCNT_H    0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
+#define SPI_MEM_CLKCNT_L    0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation..*/
+#define SPI_MEM_USR_COMMAND    (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation..*/
+#define SPI_MEM_USR_ADDR    (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation..*/
+#define SPI_MEM_USR_DUMMY    (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation..*/
+#define SPI_MEM_USR_MISO    (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation..*/
+#define SPI_MEM_USR_MOSI    (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable..*/
+#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+1: enable 0: disable..*/
+#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
+: enable 0: disable..*/
+#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals..*/
+#define SPI_MEM_FWRITE_QIO    (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals..*/
+#define SPI_MEM_FWRITE_DIO    (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals.*/
+#define SPI_MEM_FWRITE_QUAD    (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals.*/
+#define SPI_MEM_FWRITE_DUAL    (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode
+..*/
+#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_SETUP    (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_HOLD    (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
+cle_num-1)..*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command..*/
+#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
+it..*/
+#define SPI_MEM_WB_MODE    0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
+#define SPI_MEM_STATUS    0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set..*/
+#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle.*/
+#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_CSPI_ST_TRANS_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of spi0_slv_st controlled transmitting i
+s done..*/
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA    (BIT(6))
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_M  (BIT(6))
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_S  6
+/* SPI_MEM_CSPI_ST_TRANS_END : R/W/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the  spi0_slv_st controlled transmitting is done..*/
+#define SPI_MEM_CSPI_ST_TRANS_END    (BIT(5))
+#define SPI_MEM_CSPI_ST_TRANS_END_M  (BIT(5))
+#define SPI_MEM_CSPI_ST_TRANS_END_V  0x1
+#define SPI_MEM_CSPI_ST_TRANS_END_S  5
+/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting
+is done..*/
+#define SPI_MEM_TRANS_END_INT_ENA    (BIT(4))
+#define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_TRANS_END_INT_ENA_S  4
+/* SPI_MEM_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the  spi0_mst_st controlled transmitting is done..*/
+#define SPI_MEM_TRANS_END    (BIT(3))
+#define SPI_MEM_TRANS_END_M  (BIT(3))
+#define SPI_MEM_TRANS_END_V  0x1
+#define SPI_MEM_TRANS_END_S  3
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS1_DIS    (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS0_DIS    (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: For SPI1, the value of crc32..*/
+#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_qio..*/
+#define SPI_MEM_FADDR_QUAD    (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
+e same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDOUT_QUAD    (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
+ same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDIN_QUAD    (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_dio..*/
+#define SPI_MEM_FADDR_DUAL    (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+ same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDOUT_DUAL    (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDIN_DUAL    (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
+/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, Cache access enable, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_REQ_EN    (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_V  0x1
+#define SPI_MEM_CACHE_REQ_EN_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
+/* SPI_MEM_CSPI_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
+/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME    0x0000001F
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M  ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S))
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V  0x1F
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S  7
+/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GR
+ANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDM
+A sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
+#define SPI_MEM_EM_ST    0x00000007
+#define SPI_MEM_EM_ST_M  ((SPI_MEM_EM_ST_V)<<(SPI_MEM_EM_ST_S))
+#define SPI_MEM_EM_ST_V  0x7
+#define SPI_MEM_EM_ST_S  4
+/* SPI_MEM_CSPI_ST : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation
+ state, 2: send command state, 3: send address state, 4: wait state, 5: read dat
+a state, 6:write data state, 7: done state, 8: read data end state..*/
+#define SPI_MEM_CSPI_ST    0x0000000F
+#define SPI_MEM_CSPI_ST_M  ((SPI_MEM_CSPI_ST_V)<<(SPI_MEM_CSPI_ST_S))
+#define SPI_MEM_CSPI_ST_V  0xF
+#define SPI_MEM_CSPI_ST_S  0
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
+/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF0    0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
+/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF1    0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
+/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF2    0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
+/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF3    0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
+/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF4    0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
+/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF5    0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
+/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF6    0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
+/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF7    0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
+/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF8    0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
+/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF9    0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
+/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF10    0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
+/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF11    0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
+/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF12    0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
+/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF13    0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
+/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF14    0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
+/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF15    0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: The dummy cycle length when wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
+/*description: The command to wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_CMD    0x000000FF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFF
+#define SPI_MEM_WAITI_CMD_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The dummy phase enable when wait flash idle (RDSR).*/
+#define SPI_MEM_WAITI_DUMMY    (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
+/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
+/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
+ it will be treated as check pass..*/
+#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
+#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
+#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
+#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
+s of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PES_END_EN    (BIT(24))
+#define SPI_MEM_PES_END_EN_M  (BIT(24))
+#define SPI_MEM_PES_END_EN_V  0x1
+#define SPI_MEM_PES_END_EN_S  24
+/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
+ of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PER_END_EN    (BIT(23))
+#define SPI_MEM_PER_END_EN_M  (BIT(23))
+#define SPI_MEM_PER_END_EN_V  0x1
+#define SPI_MEM_PER_END_EN_S  23
+/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
+hen check flash SUS/SUS1/SUS2 status bit.*/
+#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
+#define SPI_MEM_FMEM_RD_SUS_2B_S  22
+/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
+/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
+2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
+#define SPI_MEM_PESR_END_MSK    0x0000FFFF
+#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
+#define SPI_MEM_PESR_END_MSK_V  0xFFFF
+#define SPI_MEM_PESR_END_MSK_S  6
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable Auto-suspending function..*/
+#define SPI_MEM_FLASH_PES_EN    (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  5
+/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
+application should send PER after PES is done..*/
+#define SPI_MEM_PES_PER_EN    (BIT(4))
+#define SPI_MEM_PES_PER_EN_M  (BIT(4))
+#define SPI_MEM_PES_PER_EN_V  0x1
+#define SPI_MEM_PES_PER_EN_S  4
+/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase suspend command is sent. 0: SPI1 does not wait after program erase
+ suspend command is sent..*/
+#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
+/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase resume command is sent. 0: SPI1 does not wait after program erase
+resume command is sent..*/
+#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
+/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit, program erase suspend operation will be triggered when
+the bit is set. The bit will be cleared once the operation done.1: enable 0: d
+isable..*/
+#define SPI_MEM_FLASH_PES    (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit, program erase suspend operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: di
+sable..*/
+#define SPI_MEM_FLASH_PER    (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
+/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
+/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
+..*/
+#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
+#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:8] ;default: 8'h75 ; */
+/*description: Program/Erase suspend command..*/
+#define SPI_MEM_FLASH_PES_COMMAND    0x000000FF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  8
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[7:0] ;default: 8'h7a ; */
+/*description: Program/Erase resume command..*/
+#define SPI_MEM_FLASH_PER_COMMAND    0x000000FF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
+/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
+#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_V  0x1
+#define SPI_MEM_SPI0_LOCK_EN_S  7
+/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
+#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PES_DLY_128_S  6
+/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
+#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PER_DLY_128_S  5
+/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
+mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+after DP command is sent..*/
+#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
+#define SPI_MEM_FLASH_DP_DLY_128_S  4
+/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after RES command is sent..*/
+#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_RES_DLY_128_S  3
+/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after HPM command is sent..*/
+#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
+#define SPI_MEM_FLASH_HPM_DLY_128_S  2
+/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
+#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
+#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
+/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend, only used in SPI1..*/
+#define SPI_MEM_FLASH_SUS    (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA8)
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
+#define SPI_MEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations..*/
+#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xAC)
+/* SPI_MEM_DIN3_MODE : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN3_MODE    0x00000003
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x3
+#define SPI_MEM_DIN3_MODE_S  6
+/* SPI_MEM_DIN2_MODE : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN2_MODE    0x00000003
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x3
+#define SPI_MEM_DIN2_MODE_S  4
+/* SPI_MEM_DIN1_MODE : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN1_MODE    0x00000003
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x3
+#define SPI_MEM_DIN1_MODE_S  2
+/* SPI_MEM_DIN0_MODE : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN0_MODE    0x00000003
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x3
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB0)
+/* SPI_MEM_DIN3_NUM : HRO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN3_NUM    (BIT(3))
+#define SPI_MEM_DIN3_NUM_M  (BIT(3))
+#define SPI_MEM_DIN3_NUM_V  0x1
+#define SPI_MEM_DIN3_NUM_S  3
+/* SPI_MEM_DIN2_NUM : HRO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN2_NUM    (BIT(2))
+#define SPI_MEM_DIN2_NUM_M  (BIT(2))
+#define SPI_MEM_DIN2_NUM_V  0x1
+#define SPI_MEM_DIN2_NUM_S  2
+/* SPI_MEM_DIN1_NUM : HRO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN1_NUM    (BIT(1))
+#define SPI_MEM_DIN1_NUM_M  (BIT(1))
+#define SPI_MEM_DIN1_NUM_V  0x1
+#define SPI_MEM_DIN1_NUM_S  1
+/* SPI_MEM_DIN0_NUM : HRO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN0_NUM    (BIT(0))
+#define SPI_MEM_DIN0_NUM_M  (BIT(0))
+#define SPI_MEM_DIN0_NUM_V  0x1
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB4)
+/* SPI_MEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_DOUT3_MODE_S  3
+/* SPI_MEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_DOUT2_MODE_S  2
+/* SPI_MEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_DOUT1_MODE_S  1
+/* SPI_MEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
+/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ENA_S  5
+/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ENA_S  4
+/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
+/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_V  0x1
+#define SPI_MEM_WPE_END_INT_ENA_S  2
+/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_V  0x1
+#define SPI_MEM_PES_END_INT_ENA_S  1
+/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_V  0x1
+#define SPI_MEM_PER_END_INT_ENA_S  0
+
+#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
+/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_CLR_S  5
+/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_MST_ST_END_INT_CLR_S  4
+/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
+/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_V  0x1
+#define SPI_MEM_WPE_END_INT_CLR_S  2
+/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_V  0x1
+#define SPI_MEM_PES_END_INT_CLR_S  1
+/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_V  0x1
+#define SPI_MEM_PER_END_INT_CLR_S  0
+
+#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
+/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+chip is losing power and RTC module sends out brown out close flash request to
+SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+ and MSPI returns to idle state. 0: Others..*/
+#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_RAW_S  5
+/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
+is changed from non idle state to idle state. 0: Others..*/
+#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_MST_ST_END_INT_RAW_S  4
+/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
+is changed from non idle state to idle state. It means that SPI_CS raises high.
+0: Others.*/
+#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
+/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
+E is sent and flash is already idle. 0: Others..*/
+#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_V  0x1
+#define SPI_MEM_WPE_END_INT_RAW_S  2
+/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
+mand (0x75) is sent and flash is suspended. 0: Others..*/
+#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_V  0x1
+#define SPI_MEM_PES_END_INT_RAW_S  1
+/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
+mand (0x7A) is sent and flash is resumed. 0: Others..*/
+#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_V  0x1
+#define SPI_MEM_PER_END_INT_RAW_S  0
+
+#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
+/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(5))
+#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ST_S  5
+/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ST_S  4
+/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ST_S  3
+/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_V  0x1
+#define SPI_MEM_WPE_END_INT_ST_S  2
+/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ST    (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_V  0x1
+#define SPI_MEM_PES_END_INT_ST_S  1
+/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ST    (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_V  0x1
+#define SPI_MEM_PER_END_INT_ST_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xDC)
+/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
+#define SPI_MEM_CLK_EN    (BIT(0))
+#define SPI_MEM_CLK_EN_M  (BIT(0))
+#define SPI_MEM_CLK_EN_V  0x1
+#define SPI_MEM_CLK_EN_S  0
+
+#define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE0)
+/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: When the digital system clock selects PLL clock and the frequency of PLL clock i
+s 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz
+. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz.
+3: Not used. When the digital system clock selects PLL clock and the frequency o
+f PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (
+clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (c
+lk) 160MHz. 3: Not used..*/
+#define SPI_MEM_SPI01_CLK_SEL    0x00000003
+#define SPI_MEM_SPI01_CLK_SEL_M  ((SPI_MEM_SPI01_CLK_SEL_V)<<(SPI_MEM_SPI01_CLK_SEL_S))
+#define SPI_MEM_SPI01_CLK_SEL_V  0x3
+#define SPI_MEM_SPI01_CLK_SEL_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106191 ; */
+/*description: SPI register version..*/
+#define SPI_MEM_DATE    0x0FFFFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0xFFFFFFF
+#define SPI_MEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32c2/register/soc/spi_mem_struct.h b/components/soc/esp32c2/register/soc/spi_mem_struct.h
new file mode 100644
index 00000000000..230c292b4b2
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/spi_mem_struct.h
@@ -0,0 +1,574 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct spi_mem_dev_s{
+    union {
+        struct {
+            uint32_t mst_st                        :    4;  /*The current status of SPI1 master FSM.*/
+            uint32_t slv_st                        :    4;  /*The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
+            uint32_t reserved8                     :    9;  /*reserved*/
+            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
+            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;  /*reserved*/
+            uint32_t fdummy_out                    :    1;  /*In the dummy phase the signal level of spi is output by the spi controller.*/
+            uint32_t reserved4                     :    3;  /*reserved*/
+            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t reserved9                     :    1;  /*reserved*/
+            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12                    :    1;  /*reserved*/
+            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
+            uint32_t reserved16                    :    2;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
+            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
+            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
+            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
+            uint32_t reserved2                     :    18;  /*reserved*/
+            uint32_t rxfifo_rst                    :    1;  /*SPI0 RX FIFO reset signal.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
+            uint32_t cs_hold_time                  :    5;  /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
+            uint32_t reserved10                    :    15;  /*reserved*/
+            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t sync_reset                    :    1;  /*The FSM will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
+            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
+            uint32_t clk_equ_sysclk                :    1;  /*Set this bit in 1-division mode.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. */
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
+            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
+            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
+            uint32_t reserved16                    :    8;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t reserved6                     :    20;  /*reserved*/
+            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t reserved_30;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t mst_st_trans_end              :    1;  /*The bit is used to indicate the  spi0_mst_st controlled transmitting is done.*/
+            uint32_t mst_st_trans_end_en           :    1;  /*The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.*/
+            uint32_t slv_st_trans_end              :    1;  /*The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
+            uint32_t slv_st_trans_end_en           :    1;  /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
+            uint32_t reserved7                     :    2;  /*reserved*/
+            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle */
+            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;
+    union {
+        struct {
+            uint32_t req_en                        :    1;  /*For SPI0, Cache access enable, 1: enable, 0:disable.*/
+            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
+            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
+            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    union {
+        struct {
+            uint32_t spi0_slv_st                   :    4;  /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
+            uint32_t spi0_mst_st                   :    3;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
+            uint32_t cspi_lock_delay_time          :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    uint32_t data_buf[16];
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
+            uint32_t waiti_cmd                     :    8;  /*The command to wait flash idle(RDSR).*/
+            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
+            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
+            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
+            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
+            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t flash_per_command             :    8;  /*Program/Erase resume command.*/
+            uint32_t flash_pes_command             :    8;  /*Program/Erase suspend command.*/
+            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
+            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
+            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
+            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
+            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
+            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
+            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
+            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } sus_status;
+    union {
+        struct {
+            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din1_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din2_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din3_mode                     :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din1_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din2_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din3_num                      :    1;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    union {
+        struct {
+            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
+            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
+            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
+            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t spi01_clk_sel                 :    2;  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. */
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } core_clk_sel;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/register/soc/spi_reg.h b/components/soc/esp32c2/register/soc/spi_reg.h
new file mode 100644
index 00000000000..29293c94699
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/spi_reg.h
@@ -0,0 +1,1749 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_REG_H_
+#define _SOC_SPI_REG_H_
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
+/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when the bit is set.
+ The bit will be cleared once the operation done.1: enable 0: disable. Can not b
+e changed by CONF_buf..*/
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (BIT(24))
+#define SPI_USR_V  0x1
+#define SPI_USR_S  24
+/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
+clock domain, which is only used in SPI master mode..*/
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (BIT(23))
+#define SPI_UPDATE_V  0x1
+#define SPI_UPDATE_S  23
+/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: Define the APB cycles of  SPI_CONF state. Can be configured in CONF state..*/
+#define SPI_CONF_BITLEN    0x0003FFFF
+#define SPI_CONF_BITLEN_M  ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
+#define SPI_CONF_BITLEN_V  0x3FFFF
+#define SPI_CONF_BITLEN_S  0
+
+#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
+/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Address to slave. Can be configured in CONF state..*/
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_S  0
+
+#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
+figured in CONF state..*/
+#define SPI_WR_BIT_ORDER    0x00000003
+#define SPI_WR_BIT_ORDER_M  ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
+#define SPI_WR_BIT_ORDER_V  0x3
+#define SPI_WR_BIT_ORDER_S  25
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
+/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
+tate..*/
+#define SPI_RD_BIT_ORDER    0x00000003
+#define SPI_RD_BIT_ORDER_M  ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
+#define SPI_RD_BIT_ORDER_V  0x3
+#define SPI_RD_BIT_ORDER_S  23
+/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
+an be configured in CONF state..*/
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (BIT(21))
+#define SPI_WP_POL_V  0x1
+#define SPI_WP_POL_S  21
+/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co
+nfigured in CONF state..*/
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (BIT(20))
+#define SPI_HOLD_POL_V  0x1
+#define SPI_HOLD_POL_S  20
+/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (BIT(19))
+#define SPI_D_POL_V  0x1
+#define SPI_D_POL_S  19
+/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (BIT(18))
+#define SPI_Q_POL_V  0x1
+#define SPI_Q_POL_S  18
+/* SPI_FREAD_OCT : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  C
+an be configured in CONF state..*/
+#define SPI_FREAD_OCT    (BIT(16))
+#define SPI_FREAD_OCT_M  (BIT(16))
+#define SPI_FREAD_OCT_V  0x1
+#define SPI_FREAD_OCT_S  16
+/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  C
+an be configured in CONF state..*/
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (BIT(15))
+#define SPI_FREAD_QUAD_V  0x1
+#define SPI_FREAD_QUAD_S  15
+/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C
+an be configured in CONF state..*/
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (BIT(14))
+#define SPI_FREAD_DUAL_V  0x1
+#define SPI_FREAD_DUAL_S  14
+/* SPI_FCMD_OCT : HRO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Apply 8 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_OCT    (BIT(10))
+#define SPI_FCMD_OCT_M  (BIT(10))
+#define SPI_FCMD_OCT_V  0x1
+#define SPI_FCMD_OCT_S  10
+/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (BIT(9))
+#define SPI_FCMD_QUAD_V  0x1
+#define SPI_FCMD_QUAD_S  9
+/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (BIT(8))
+#define SPI_FCMD_DUAL_V  0x1
+#define SPI_FCMD_DUAL_S  8
+/* SPI_FADDR_OCT : HRO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_OCT    (BIT(7))
+#define SPI_FADDR_OCT_M  (BIT(7))
+#define SPI_FADDR_OCT_V  0x1
+#define SPI_FADDR_OCT_S  7
+/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (BIT(6))
+#define SPI_FADDR_QUAD_V  0x1
+#define SPI_FADDR_QUAD_S  6
+/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (BIT(5))
+#define SPI_FADDR_DUAL_V  0x1
+#define SPI_FADDR_DUAL_S  5
+/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phas
+e, the FSPI bus signals are output. Can be configured in CONF state..*/
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (BIT(3))
+#define SPI_DUMMY_OUT_V  0x1
+#define SPI_DUMMY_OUT_S  3
+
+#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0xC)
+/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst
+em clock. Can be configured in CONF state..*/
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_V  0x1
+#define SPI_CLK_EQU_SYSCLK_S  31
+/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
+/*description: In the master mode it is pre-divider of spi_clk.  Can be configured in CONF stat
+e..*/
+#define SPI_CLKDIV_PRE    0x0000000F
+#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
+#define SPI_CLKDIV_PRE_V  0xF
+#define SPI_CLKDIV_PRE_S  18
+/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
+/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/
+(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
+#define SPI_CLKCNT_N    0x0000003F
+#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
+#define SPI_CLKCNT_N_V  0x3F
+#define SPI_CLKCNT_N_S  12
+/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
+/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+must be 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_H    0x0000003F
+#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
+#define SPI_CLKCNT_H_V  0x3F
+#define SPI_CLKCNT_H_S  6
+/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b
+e 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_L    0x0000003F
+#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
+#define SPI_CLKCNT_L_V  0x3F
+#define SPI_CLKCNT_L_S  0
+
+#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x10)
+/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (BIT(31))
+#define SPI_USR_COMMAND_V  0x1
+#define SPI_USR_COMMAND_S  31
+/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (BIT(30))
+#define SPI_USR_ADDR_V  0x1
+#define SPI_USR_ADDR_S  30
+/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
+..*/
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (BIT(29))
+#define SPI_USR_DUMMY_V  0x1
+#define SPI_USR_DUMMY_S  29
+/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s
+tate..*/
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (BIT(28))
+#define SPI_USR_MISO_V  0x1
+#define SPI_USR_MISO_S  28
+/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (BIT(27))
+#define SPI_USR_MOSI_V  0x1
+#define SPI_USR_MOSI_S  27
+/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ CONF state..*/
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_USR_DUMMY_IDLE_V  0x1
+#define SPI_USR_DUMMY_IDLE_S  26
+/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl
+e 0: disable.  Can be configured in CONF state..*/
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_V  0x1
+#define SPI_USR_MOSI_HIGHPART_S  25
+/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ 0: disable. Can be configured in CONF state..*/
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_USR_MISO_HIGHPART_V  0x1
+#define SPI_USR_MISO_HIGHPART_S  24
+/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha
+re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (BIT(17))
+#define SPI_SIO_V  0x1
+#define SPI_SIO_S  17
+/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+will continue. 0: The seg-trans will end after the current SPI seg-trans or this
+ is not seg-trans mode. Can be configured in CONF state..*/
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (BIT(15))
+#define SPI_USR_CONF_NXT_V  0x1
+#define SPI_USR_CONF_NXT_S  15
+/* SPI_FWRITE_OCT : HRO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 8 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_OCT    (BIT(14))
+#define SPI_FWRITE_OCT_M  (BIT(14))
+#define SPI_FWRITE_OCT_V  0x1
+#define SPI_FWRITE_OCT_S  14
+/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (BIT(13))
+#define SPI_FWRITE_QUAD_V  0x1
+#define SPI_FWRITE_QUAD_S  13
+/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (BIT(12))
+#define SPI_FWRITE_DUAL_V  0x1
+#define SPI_FWRITE_DUAL_S  12
+/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca
+n be configured in CONF state..*/
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_CK_OUT_EDGE_V  0x1
+#define SPI_CK_OUT_EDGE_S  9
+/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
+= !spi_ck_i. 1:rsck = spi_ck_i..*/
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (BIT(8))
+#define SPI_RSCK_I_EDGE_V  0x1
+#define SPI_RSCK_I_EDGE_S  8
+/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (BIT(7))
+#define SPI_CS_SETUP_V  0x1
+#define SPI_CS_SETUP_S  7
+/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be config
+ured in CONF state..*/
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (BIT(6))
+#define SPI_CS_HOLD_V  0x1
+#define SPI_CS_HOLD_S  6
+/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
+= spi_ck_i. 1:tsck = !spi_ck_i..*/
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (BIT(5))
+#define SPI_TSCK_I_EDGE_V  0x1
+#define SPI_TSCK_I_EDGE_S  5
+/* SPI_OPI_MODE : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others
+. Can be configured in CONF state..*/
+#define SPI_OPI_MODE    (BIT(4))
+#define SPI_OPI_MODE_M  (BIT(4))
+#define SPI_OPI_MODE_V  0x1
+#define SPI_OPI_MODE_S  4
+/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others
+. Can be configured in CONF state..*/
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (BIT(3))
+#define SPI_QPI_MODE_V  0x1
+#define SPI_QPI_MODE_S  3
+/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (BIT(0))
+#define SPI_DOUTDIN_V  0x1
+#define SPI_DOUTDIN_S  0
+
+#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x14)
+/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_ADDR_BITLEN    0x0000001F
+#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
+#define SPI_USR_ADDR_BITLEN_V  0x1F
+#define SPI_USR_ADDR_BITLEN_S  27
+/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */
+/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ Can be configured in CONF state..*/
+#define SPI_CS_HOLD_TIME    0x0000001F
+#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
+#define SPI_CS_HOLD_TIME_V  0x1F
+#define SPI_CS_HOLD_TIME_S  22
+/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
+/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu
+p bit. Can be configured in CONF state..*/
+#define SPI_CS_SETUP_TIME    0x0000001F
+#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
+#define SPI_CS_SETUP_TIME_V  0x1F
+#define SPI_CS_SETUP_TIME_S  17
+/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
+ in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_V  0x1
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
+/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_
+num-1). Can be configured in CONF state..*/
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
+#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x18)
+/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
+#define SPI_USR_COMMAND_BITLEN_V  0xF
+#define SPI_USR_COMMAND_BITLEN_S  28
+/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
+aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+r is valid in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x1
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command. Can be configured in CONF state..*/
+#define SPI_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
+#define SPI_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_USR_COMMAND_VALUE_S  0
+
+#define SPI_MS_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x1C)
+/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: The value of these bits is the configured SPI transmission data bit length in ma
+ster mode DMA controlled transfer or CPU controlled transfer. The value is also
+the configured bit length in slave mode DMA RX controlled transfer. The register
+ value shall be (bit_num-1). Can be configured in CONF state..*/
+#define SPI_MS_DATA_BITLEN    0x0003FFFF
+#define SPI_MS_DATA_BITLEN_M  ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
+#define SPI_MS_DATA_BITLEN_V  0x3FFFF
+#define SPI_MS_DATA_BITLEN_S  0
+
+#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
+/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0
+:  spi quad input swap disable. Can be configured in CONF state..*/
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_V  0x1
+#define SPI_CS_KEEP_ACTIVE_S  30
+/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle. Can be c
+onfigured in CONF state..*/
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (BIT(29))
+#define SPI_CK_IDLE_EDGE_V  0x1
+#define SPI_CK_IDLE_EDGE_S  29
+/* SPI_DQS_IDLE_EDGE : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The default value of spi_dqs. Can be configured in CONF state..*/
+#define SPI_DQS_IDLE_EDGE    (BIT(24))
+#define SPI_DQS_IDLE_EDGE_M  (BIT(24))
+#define SPI_DQS_IDLE_EDGE_V  0x1
+#define SPI_DQS_IDLE_EDGE_S  24
+/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+CONF state..*/
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (BIT(23))
+#define SPI_SLAVE_CS_POL_V  0x1
+#define SPI_SLAVE_CS_POL_S  23
+/* SPI_CMD_DTR_EN : HRO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/
+4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be confi
+gured in CONF state..*/
+#define SPI_CMD_DTR_EN    (BIT(19))
+#define SPI_CMD_DTR_EN_M  (BIT(19))
+#define SPI_CMD_DTR_EN_V  0x1
+#define SPI_CMD_DTR_EN_S  19
+/* SPI_ADDR_DTR_EN : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2
+/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be co
+nfigured in CONF state..*/
+#define SPI_ADDR_DTR_EN    (BIT(18))
+#define SPI_ADDR_DTR_EN_M  (BIT(18))
+#define SPI_ADDR_DTR_EN_V  0x1
+#define SPI_ADDR_DTR_EN_S  18
+/* SPI_DATA_DTR_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including mas
+ter 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR m
+ode. Can be configured in CONF state..*/
+#define SPI_DATA_DTR_EN    (BIT(17))
+#define SPI_DATA_DTR_EN_M  (BIT(17))
+#define SPI_DATA_DTR_EN_V  0x1
+#define SPI_DATA_DTR_EN_S  17
+/* SPI_CLK_DATA_DTR_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master D
+TR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19..*/
+#define SPI_CLK_DATA_DTR_EN    (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_M  (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_V  0x1
+#define SPI_CLK_DATA_DTR_EN_S  16
+/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
+/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva
+lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/
+#define SPI_MASTER_CS_POL    0x0000003F
+#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
+#define SPI_MASTER_CS_POL_V  0x3F
+#define SPI_MASTER_CS_POL_S  7
+/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state..*/
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (BIT(6))
+#define SPI_CK_DIS_V  0x1
+#define SPI_CK_DIS_S  6
+/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (BIT(5))
+#define SPI_CS5_DIS_V  0x1
+#define SPI_CS5_DIS_S  5
+/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (BIT(4))
+#define SPI_CS4_DIS_V  0x1
+#define SPI_CS4_DIS_S  4
+/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (BIT(3))
+#define SPI_CS3_DIS_V  0x1
+#define SPI_CS3_DIS_S  3
+/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (BIT(2))
+#define SPI_CS2_DIS_V  0x1
+#define SPI_CS2_DIS_S  2
+/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (BIT(1))
+#define SPI_CS1_DIS_V  0x1
+#define SPI_CS1_DIS_S  1
+/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (BIT(0))
+#define SPI_CS0_DIS_V  0x1
+#define SPI_CS0_DIS_S  0
+
+#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x24)
+/* SPI_TIMING_HCLK_ACTIVE : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1:enable hclk in SPI input timing module.  0: disable it. Can be configured in C
+ONF state..*/
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_V  0x1
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+/* SPI_DIN7_MODE : HRO ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN7_MODE    0x00000003
+#define SPI_DIN7_MODE_M  ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S))
+#define SPI_DIN7_MODE_V  0x3
+#define SPI_DIN7_MODE_S  14
+/* SPI_DIN6_MODE : HRO ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN6_MODE    0x00000003
+#define SPI_DIN6_MODE_M  ((SPI_DIN6_MODE_V)<<(SPI_DIN6_MODE_S))
+#define SPI_DIN6_MODE_V  0x3
+#define SPI_DIN6_MODE_S  12
+/* SPI_DIN5_MODE : HRO ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN5_MODE    0x00000003
+#define SPI_DIN5_MODE_M  ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S))
+#define SPI_DIN5_MODE_V  0x3
+#define SPI_DIN5_MODE_S  10
+/* SPI_DIN4_MODE : HRO ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN4_MODE    0x00000003
+#define SPI_DIN4_MODE_M  ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S))
+#define SPI_DIN4_MODE_V  0x3
+#define SPI_DIN4_MODE_S  8
+/* SPI_DIN3_MODE : HRO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN3_MODE    0x00000003
+#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
+#define SPI_DIN3_MODE_V  0x3
+#define SPI_DIN3_MODE_S  6
+/* SPI_DIN2_MODE : HRO ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN2_MODE    0x00000003
+#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
+#define SPI_DIN2_MODE_V  0x3
+#define SPI_DIN2_MODE_S  4
+/* SPI_DIN1_MODE : HRO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN1_MODE    0x00000003
+#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
+#define SPI_DIN1_MODE_V  0x3
+#define SPI_DIN1_MODE_S  2
+/* SPI_DIN0_MODE : HRO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN0_MODE    0x00000003
+#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
+#define SPI_DIN0_MODE_V  0x3
+#define SPI_DIN0_MODE_S  0
+
+#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x28)
+/* SPI_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN7_NUM    0x00000003
+#define SPI_DIN7_NUM_M  ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S))
+#define SPI_DIN7_NUM_V  0x3
+#define SPI_DIN7_NUM_S  14
+/* SPI_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN6_NUM    0x00000003
+#define SPI_DIN6_NUM_M  ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S))
+#define SPI_DIN6_NUM_V  0x3
+#define SPI_DIN6_NUM_S  12
+/* SPI_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN5_NUM    0x00000003
+#define SPI_DIN5_NUM_M  ((SPI_DIN5_NUM_V)<<(SPI_DIN5_NUM_S))
+#define SPI_DIN5_NUM_V  0x3
+#define SPI_DIN5_NUM_S  10
+/* SPI_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN4_NUM    0x00000003
+#define SPI_DIN4_NUM_M  ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S))
+#define SPI_DIN4_NUM_V  0x3
+#define SPI_DIN4_NUM_S  8
+/* SPI_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN3_NUM    0x00000003
+#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
+#define SPI_DIN3_NUM_V  0x3
+#define SPI_DIN3_NUM_S  6
+/* SPI_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN2_NUM    0x00000003
+#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
+#define SPI_DIN2_NUM_V  0x3
+#define SPI_DIN2_NUM_S  4
+/* SPI_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN1_NUM    0x00000003
+#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
+#define SPI_DIN1_NUM_V  0x3
+#define SPI_DIN1_NUM_S  2
+/* SPI_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN0_NUM    0x00000003
+#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
+#define SPI_DIN0_NUM_V  0x3
+#define SPI_DIN0_NUM_S  0
+
+#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x2C)
+/* SPI_D_DQS_MODE : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+be configured in CONF state..*/
+#define SPI_D_DQS_MODE    (BIT(8))
+#define SPI_D_DQS_MODE_M  (BIT(8))
+#define SPI_D_DQS_MODE_V  0x1
+#define SPI_D_DQS_MODE_S  8
+/* SPI_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT7_MODE    (BIT(7))
+#define SPI_DOUT7_MODE_M  (BIT(7))
+#define SPI_DOUT7_MODE_V  0x1
+#define SPI_DOUT7_MODE_S  7
+/* SPI_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT6_MODE    (BIT(6))
+#define SPI_DOUT6_MODE_M  (BIT(6))
+#define SPI_DOUT6_MODE_V  0x1
+#define SPI_DOUT6_MODE_S  6
+/* SPI_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT5_MODE    (BIT(5))
+#define SPI_DOUT5_MODE_M  (BIT(5))
+#define SPI_DOUT5_MODE_V  0x1
+#define SPI_DOUT5_MODE_S  5
+/* SPI_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT4_MODE    (BIT(4))
+#define SPI_DOUT4_MODE_M  (BIT(4))
+#define SPI_DOUT4_MODE_V  0x1
+#define SPI_DOUT4_MODE_S  4
+/* SPI_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (BIT(3))
+#define SPI_DOUT3_MODE_V  0x1
+#define SPI_DOUT3_MODE_S  3
+/* SPI_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (BIT(2))
+#define SPI_DOUT2_MODE_V  0x1
+#define SPI_DOUT2_MODE_S  2
+/* SPI_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (BIT(1))
+#define SPI_DOUT1_MODE_V  0x1
+#define SPI_DOUT1_MODE_S  1
+/* SPI_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (BIT(0))
+#define SPI_DOUT0_MODE_V  0x1
+#define SPI_DOUT0_MODE_S  0
+
+#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x30)
+/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
+DMA controlled mode transfer..*/
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (BIT(31))
+#define SPI_DMA_AFIFO_RST_V  0x1
+#define SPI_DMA_AFIFO_RST_S  31
+/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ controlled mode transfer and master mode transfer..*/
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (BIT(30))
+#define SPI_BUF_AFIFO_RST_V  0x1
+#define SPI_BUF_AFIFO_RST_S  30
+/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+slave mode transfer..*/
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (BIT(29))
+#define SPI_RX_AFIFO_RST_V  0x1
+#define SPI_RX_AFIFO_RST_S  29
+/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI DMA controlled send data mode..*/
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (BIT(28))
+#define SPI_DMA_TX_ENA_V  0x1
+#define SPI_DMA_TX_ENA_S  28
+/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Set this bit to enable SPI DMA controlled receive data mode..*/
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (BIT(27))
+#define SPI_DMA_RX_ENA_V  0x1
+#define SPI_DMA_RX_ENA_S  27
+/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
+o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_d
+ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don
+e in seg-trans..*/
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (BIT(21))
+#define SPI_RX_EOF_EN_V  0x1
+#define SPI_RX_EOF_EN_S  21
+/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
+mpty_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full
+_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat
+a. 0: DMA RX FIFO is ready for receiving data..*/
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (BIT(1))
+#define SPI_DMA_INFIFO_FULL_V  0x1
+#define SPI_DMA_INFIFO_FULL_S  1
+/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data.
+ 0: DMA TX FIFO is ready for sending data..*/
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
+
+#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
+/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (BIT(20))
+#define SPI_APP1_INT_ENA_V  0x1
+#define SPI_APP1_INT_ENA_S  20
+/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (BIT(19))
+#define SPI_APP2_INT_ENA_V  0x1
+#define SPI_APP2_INT_ENA_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_V  0x1
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_V  0x1
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_V  0x1
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_V  0x1
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+
+#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x38)
+/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (BIT(20))
+#define SPI_APP1_INT_CLR_V  0x1
+#define SPI_APP1_INT_CLR_S  20
+/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (BIT(19))
+#define SPI_APP2_INT_CLR_V  0x1
+#define SPI_APP2_INT_CLR_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x1
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_V  0x1
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_V  0x1
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_V  0x1
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_V  0x1
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+
+#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x3C)
+/* SPI_APP1_INT_RAW : R/WTC/SS ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software
+..*/
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (BIT(20))
+#define SPI_APP1_INT_RAW_V  0x1
+#define SPI_APP1_INT_RAW_S  20
+/* SPI_APP2_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software
+..*/
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (BIT(19))
+#define SPI_APP2_INT_RAW_V  0x1
+#define SPI_APP2_INT_RAW_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ write-full error when SPI inputs data in master mode. 0: Others..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/* SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ current SPI slave HD mode transmission is not supported. 0: Others..*/
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x1
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
+ is bigger than 63. 0: Others..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/* SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff
+er is error in the DMA seg-conf-trans. 0: others..*/
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-du
+plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
+ta has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is
+not ended or not occurred..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/* SPI_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ ended. 0: others..*/
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/* SPI_SLV_CMDA_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_V  0x1
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/* SPI_SLV_CMD9_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_V  0x1
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/* SPI_SLV_CMD8_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_V  0x1
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/* SPI_SLV_CMD7_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_V  0x1
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/* SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/* SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ master mode and send out all 0 in slave mode.  0: Others..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
+the receive data.  0: Others..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+
+#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x40)
+/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (BIT(20))
+#define SPI_APP1_INT_ST_V  0x1
+#define SPI_APP1_INT_ST_S  20
+/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (BIT(19))
+#define SPI_APP2_INT_ST_V  0x1
+#define SPI_APP2_INT_ST_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_V  0x1
+#define SPI_TRANS_DONE_INT_ST_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_V  0x1
+#define SPI_SLV_CMDA_INT_ST_S  7
+/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_V  0x1
+#define SPI_SLV_CMD9_INT_ST_S  6
+/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_V  0x1
+#define SPI_SLV_CMD8_INT_ST_S  5
+/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_V  0x1
+#define SPI_SLV_CMD7_INT_ST_S  4
+/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_V  0x1
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_V  0x1
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+
+#define SPI_DMA_INT_SET_REG(i)          (REG_SPI_BASE(i) + 0x44)
+/* SPI_APP1_INT_SET : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_SET    (BIT(20))
+#define SPI_APP1_INT_SET_M  (BIT(20))
+#define SPI_APP1_INT_SET_V  0x1
+#define SPI_APP1_INT_SET_S  20
+/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_SET    (BIT(19))
+#define SPI_APP2_INT_SET_M  (BIT(19))
+#define SPI_APP2_INT_SET_V  0x1
+#define SPI_APP2_INT_SET_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/* SPI_SLV_CMD_ERR_INT_SET : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_V  0x1
+#define SPI_SLV_CMD_ERR_INT_SET_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/* SPI_SEG_MAGIC_ERR_INT_SET : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_SET : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
+/* SPI_TRANS_DONE_INT_SET : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_V  0x1
+#define SPI_TRANS_DONE_INT_SET_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_SET : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_SET : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_SET : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
+/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_SET    (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_V  0x1
+#define SPI_SLV_CMDA_INT_SET_S  7
+/* SPI_SLV_CMD9_INT_SET : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_SET    (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_V  0x1
+#define SPI_SLV_CMD9_INT_SET_S  6
+/* SPI_SLV_CMD8_INT_SET : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_SET    (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_V  0x1
+#define SPI_SLV_CMD8_INT_SET_S  5
+/* SPI_SLV_CMD7_INT_SET : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_SET    (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_V  0x1
+#define SPI_SLV_CMD7_INT_SET_S  4
+/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_V  0x1
+#define SPI_SLV_EN_QPI_INT_SET_S  3
+/* SPI_SLV_EX_QPI_INT_SET : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_V  0x1
+#define SPI_SLV_EX_QPI_INT_SET_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
+
+#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x98)
+/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF0    0xFFFFFFFF
+#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
+#define SPI_BUF0_V  0xFFFFFFFF
+#define SPI_BUF0_S  0
+
+#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x9C)
+/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF1    0xFFFFFFFF
+#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
+#define SPI_BUF1_V  0xFFFFFFFF
+#define SPI_BUF1_S  0
+
+#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0xA0)
+/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF2    0xFFFFFFFF
+#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
+#define SPI_BUF2_V  0xFFFFFFFF
+#define SPI_BUF2_S  0
+
+#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0xA4)
+/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF3    0xFFFFFFFF
+#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
+#define SPI_BUF3_V  0xFFFFFFFF
+#define SPI_BUF3_S  0
+
+#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0xA8)
+/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF4    0xFFFFFFFF
+#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
+#define SPI_BUF4_V  0xFFFFFFFF
+#define SPI_BUF4_S  0
+
+#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0xAC)
+/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF5    0xFFFFFFFF
+#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
+#define SPI_BUF5_V  0xFFFFFFFF
+#define SPI_BUF5_S  0
+
+#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0xB0)
+/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF6    0xFFFFFFFF
+#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
+#define SPI_BUF6_V  0xFFFFFFFF
+#define SPI_BUF6_S  0
+
+#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0xB4)
+/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF7    0xFFFFFFFF
+#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
+#define SPI_BUF7_V  0xFFFFFFFF
+#define SPI_BUF7_S  0
+
+#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xB8)
+/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF8    0xFFFFFFFF
+#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
+#define SPI_BUF8_V  0xFFFFFFFF
+#define SPI_BUF8_S  0
+
+#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xBC)
+/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF9    0xFFFFFFFF
+#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
+#define SPI_BUF9_V  0xFFFFFFFF
+#define SPI_BUF9_S  0
+
+#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xC0)
+/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF10    0xFFFFFFFF
+#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
+#define SPI_BUF10_V  0xFFFFFFFF
+#define SPI_BUF10_S  0
+
+#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xC4)
+/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF11    0xFFFFFFFF
+#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
+#define SPI_BUF11_V  0xFFFFFFFF
+#define SPI_BUF11_S  0
+
+#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xC8)
+/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF12    0xFFFFFFFF
+#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
+#define SPI_BUF12_V  0xFFFFFFFF
+#define SPI_BUF12_S  0
+
+#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xCC)
+/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF13    0xFFFFFFFF
+#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
+#define SPI_BUF13_V  0xFFFFFFFF
+#define SPI_BUF13_S  0
+
+#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xD0)
+/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF14    0xFFFFFFFF
+#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
+#define SPI_BUF14_V  0xFFFFFFFF
+#define SPI_BUF14_S  0
+
+#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xD4)
+/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF15    0xFFFFFFFF
+#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
+#define SPI_BUF15_V  0xFFFFFFFF
+#define SPI_BUF15_S  0
+
+#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0xE0)
+/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
+ns will start. 0: This is not seg-trans mode..*/
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (BIT(28))
+#define SPI_USR_CONF_V  0x1
+#define SPI_USR_CONF_S  28
+/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
+onfigured in CONF state..*/
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (BIT(27))
+#define SPI_SOFT_RESET_V  0x1
+#define SPI_SOFT_RESET_S  27
+/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (BIT(26))
+#define SPI_SLAVE_MODE_V  0x1
+#define SPI_SLAVE_MODE_S  26
+/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
+/*description: The magic value of BM table in master DMA seg-trans..*/
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000F
+#define SPI_DMA_SEG_MAGIC_VALUE_M  ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0xF
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in CPU controlled mode(Wr_BUF). 0: others.*/
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n CPU controlled mode(Rd_BUF). 0: others.*/
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in DMA controlled mode(Wr_DMA). 0: others.*/
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n DMA controlled mode(Rd_DMA). 0: others.*/
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
+dge   0: output data at tsck posedge.*/
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (BIT(3))
+#define SPI_RSCK_DATA_OUT_V  0x1
+#define SPI_RSCK_DATA_OUT_S  3
+/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
+ 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (BIT(2))
+#define SPI_CLK_MODE_13_V  0x1
+#define SPI_CLK_MODE_13_S  2
+/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on. Can be configured in CONF state..*/
+#define SPI_CLK_MODE    0x00000003
+#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
+#define SPI_CLK_MODE_V  0x3
+#define SPI_CLK_MODE_S  0
+
+#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0xE4)
+/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
+/*description: In the slave mode it is the value of address..*/
+#define SPI_SLV_LAST_ADDR    0x0000003F
+#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
+#define SPI_SLV_LAST_ADDR_V  0x3F
+#define SPI_SLV_LAST_ADDR_S  26
+/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of command..*/
+#define SPI_SLV_LAST_COMMAND    0x000000FF
+#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
+#define SPI_SLV_LAST_COMMAND_V  0xFF
+#define SPI_SLV_LAST_COMMAND_S  18
+/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: The transferred data bit length in SPI slave FD and HD mode..*/
+#define SPI_SLV_DATA_BITLEN    0x0003FFFF
+#define SPI_SLV_DATA_BITLEN_M  ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
+#define SPI_SLV_DATA_BITLEN_V  0x3FFFF
+#define SPI_SLV_DATA_BITLEN_S  0
+
+#define SPI_CLK_GATE_REG(i)          (REG_SPI_BASE(i) + 0xE8)
+/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
+M. 0: XTAL CLK..*/
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (BIT(2))
+#define SPI_MST_CLK_SEL_V  0x1
+#define SPI_MST_CLK_SEL_S  2
+/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to power on the SPI module clock..*/
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (BIT(1))
+#define SPI_MST_CLK_ACTIVE_V  0x1
+#define SPI_MST_CLK_ACTIVE_S  1
+/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate.*/
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (BIT(0))
+#define SPI_CLK_EN_V  0x1
+#define SPI_CLK_EN_S  0
+
+#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
+/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2106070 ; */
+/*description: SPI register version..*/
+#define SPI_DATE    0x0FFFFFFF
+#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
+#define SPI_DATE_V  0xFFFFFFF
+#define SPI_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_REG_H_ */
diff --git a/components/soc/esp32c2/register/soc/spi_struct.h b/components/soc/esp32c2/register/soc/spi_struct.h
new file mode 100644
index 00000000000..08920a09e6a
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/spi_struct.h
@@ -0,0 +1,420 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_STRUCT_H_
+#define _SOC_SPI_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+typedef volatile struct spi_dev_s{
+    union {
+        struct {
+            uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    5;  /*reserved*/
+            uint32_t update                        :    1;  /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
+            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;  /*reserved*/
+            uint32_t dummy_out                     :    1;  /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved11                    :    3;  /*reserved*/
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t fread_oct                     :    1;  /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t reserved17                    :    1;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
+            uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    1;  /*reserved*/
+            uint32_t rd_bit_order                  :    2;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
+            uint32_t wr_bit_order                  :    2;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    6;  /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_h                      :    6;  /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_n                      :    6;  /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
+            uint32_t clkdiv_pre                    :    4;  /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    9;  /*reserved*/
+            uint32_t clk_equ_sysclk                :    1;  /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t doutdin                       :    1;  /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved1                     :    2;  /*reserved*/
+            uint32_t qpi_mode                      :    1;  /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
+            uint32_t opi_mode                      :    1;  /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
+            uint32_t tsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t rsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
+            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
+            uint32_t fwrite_oct                    :    1;  /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
+            uint32_t usr_conf_nxt                  :    1;  /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t sio                           :    1;  /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    6;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    8;  /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
+            uint32_t reserved8                     :    8;  /*reserved*/
+            uint32_t mst_wfull_err_end_en          :    1;  /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t cs_setup_time                 :    5;  /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
+            uint32_t cs_hold_time                  :    5;  /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
+            uint32_t usr_addr_bitlen               :    5;  /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    11;  /*reserved*/
+            uint32_t mst_rempty_err_end_en         :    1;  /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t ms_data_bitlen                :    18;  /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } ms_dlen;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs1_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs2_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs3_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs4_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs5_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t ck_dis                        :    1;  /*1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.*/
+            uint32_t master_cs_pol                 :    6;  /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
+            uint32_t reserved13                    :    3;  /*reserved*/
+            uint32_t clk_data_dtr_en               :    1;  /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19. */
+            uint32_t data_dtr_en                   :    1;  /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
+            uint32_t addr_dtr_en                   :    1;  /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
+            uint32_t cmd_dtr_en                    :    1;  /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
+            uint32_t reserved20                    :    3;  /*reserved*/
+            uint32_t slave_cs_pol                  :    1;  /*spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.*/
+            uint32_t dqs_idle_edge                 :    1;  /*The default value of spi_dqs. Can be configured in CONF state.*/
+            uint32_t reserved25                    :    4;  /*reserved*/
+            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
+            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
+            uint32_t quad_din_pin_swap             :    1;  /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } misc;
+    union {
+        struct {
+            uint32_t din0_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din1_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din2_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din3_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din4_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din5_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din6_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din7_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t timing_hclk_active            :    1;  /*1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.*/
+            uint32_t reserved17                    :    15;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din4_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din5_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din6_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din7_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout1_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout2_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout3_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout4_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout5_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout6_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout7_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t d_dqs_mode                    :    1;  /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t dma_outfifo_empty             :    1;  /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
+            uint32_t dma_infifo_full               :    1;  /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
+            uint32_t reserved2                     :    16;  /*reserved*/
+            uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
+            uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
+            uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
+            uint32_t rx_eof_en                     :    1;  /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
+            uint32_t reserved22                    :    5;  /*reserved*/
+            uint32_t dma_rx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled receive data mode.*/
+            uint32_t dma_tx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled send data mode.*/
+            uint32_t rx_afifo_rst                  :    1;  /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
+            uint32_t buf_afifo_rst                 :    1;  /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
+            uint32_t dma_afifo_rst                 :    1;  /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The enable bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The enable bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The enable bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The enable bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The enable bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The enable bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The enable bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The enable bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_ena;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The clear bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The clear bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The clear bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The clear bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The clear bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The clear bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The clear bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The clear bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_clr;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.  */
+            uint32_t outfifo_empty_err             :    1;  /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.  */
+            uint32_t ex_qpi                        :    1;  /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
+            uint32_t en_qpi                        :    1;  /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
+            uint32_t cmd7                          :    1;  /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
+            uint32_t cmd8                          :    1;  /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
+            uint32_t cmd9                          :    1;  /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
+            uint32_t cmda                          :    1;  /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
+            uint32_t rd_dma_done                   :    1;  /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
+            uint32_t wr_dma_done                   :    1;  /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
+            uint32_t rd_buf_done                   :    1;  /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
+            uint32_t wr_buf_done                   :    1;  /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
+            uint32_t trans_done                    :    1;  /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred. */
+            uint32_t seg_magic_err                 :    1;  /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
+            uint32_t buf_addr_err                  :    1;  /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
+            uint32_t cmd_err                       :    1;  /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
+            uint32_t app2                          :    1;  /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
+            uint32_t app1                          :    1;  /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_raw;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The status bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The status bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The status bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The status bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The status bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The status bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The status bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The status bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_st;
+    union {
+        struct {
+            uint32_t infifo_full_err_int_set       :    1;  /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err_int_set     :    1;  /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi_int_set                :    1;  /*The software set bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi_int_set                :    1;  /*The software set bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7_int_set                  :    1;  /*The software set bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8_int_set                  :    1;  /*The software set bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9_int_set                  :    1;  /*The software set bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda_int_set                  :    1;  /*The software set bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done_int_set            :    1;  /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done_int_set    :    1;  /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err_int_set         :    1;  /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err_int_set          :    1;  /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err_int_set               :    1;  /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err_int_set:    1;  /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err_int_set:    1;  /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2_int_set                  :    1;  /*The software set bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1_int_set                  :    1;  /*The software set bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_set;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t data_buf[16];
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/
+            uint32_t clk_mode_13                   :    1;  /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
+            uint32_t rsck_data_out                 :    1;  /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge */
+            uint32_t reserved4                     :    4;  /*reserved*/
+            uint32_t rddma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
+            uint32_t wrdma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
+            uint32_t rdbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
+            uint32_t wrbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
+            uint32_t reserved12                    :    10;  /*reserved*/
+            uint32_t dma_seg_magic_value           :    4;  /*The magic value of BM table in master DMA seg-trans.*/
+            uint32_t slave_mode                    :    1;  /*Set SPI work mode. 1: slave mode 0: master mode.*/
+            uint32_t soft_reset                    :    1;  /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
+            uint32_t usr_conf                      :    1;  /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
+            uint32_t reserved29                    :    3;  /*reserved*/
+        };
+        uint32_t val;
+    } slave;
+    union {
+        struct {
+            uint32_t data_bitlen                   :    18;  /*The transferred data bit length in SPI slave FD and HD mode. */
+            uint32_t last_command                  :    8;  /*In the slave mode it is the value of command.*/
+            uint32_t last_addr                     :    6;  /*In the slave mode it is the value of address.*/
+        };
+        uint32_t val;
+    } slave1;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
+            uint32_t mst_clk_active                :    1;  /*Set this bit to power on the SPI module clock.*/
+            uint32_t mst_clk_sel                   :    1;  /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } clk_gate;
+    uint32_t reserved_ec;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_dev_t;
+extern spi_dev_t GPSPI2;
+extern spi_dev_t GPSPI3;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_STRUCT_H_ */
diff --git a/components/soc/esp32c2/register/soc/syscon_reg.h b/components/soc/esp32c2/register/soc/syscon_reg.h
new file mode 100644
index 00000000000..fbbf7706bcb
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/syscon_reg.h
@@ -0,0 +1,637 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSCON_REG_H_
+#define _SOC_SYSCON_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x0)
+/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: reg_rst_tick_cnt.*/
+#define SYSCON_RST_TICK_CNT    (BIT(12))
+#define SYSCON_RST_TICK_CNT_M  (BIT(12))
+#define SYSCON_RST_TICK_CNT_V  0x1
+#define SYSCON_RST_TICK_CNT_S  12
+/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: reg_clk_en.*/
+#define SYSCON_CLK_EN    (BIT(11))
+#define SYSCON_CLK_EN_M  (BIT(11))
+#define SYSCON_CLK_EN_V  0x1
+#define SYSCON_CLK_EN_S  11
+/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: reg_clk_320m_en.*/
+#define SYSCON_CLK_320M_EN    (BIT(10))
+#define SYSCON_CLK_320M_EN_M  (BIT(10))
+#define SYSCON_CLK_320M_EN_V  0x1
+#define SYSCON_CLK_320M_EN_S  10
+/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: reg_pre_div_cnt.*/
+#define SYSCON_PRE_DIV_CNT    0x000003FF
+#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
+#define SYSCON_PRE_DIV_CNT_V  0x3FF
+#define SYSCON_PRE_DIV_CNT_S  0
+
+#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x4)
+/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: reg_tick_enable.*/
+#define SYSCON_TICK_ENABLE    (BIT(16))
+#define SYSCON_TICK_ENABLE_M  (BIT(16))
+#define SYSCON_TICK_ENABLE_V  0x1
+#define SYSCON_TICK_ENABLE_S  16
+/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: reg_ck8m_tick_num.*/
+#define SYSCON_CK8M_TICK_NUM    0x000000FF
+#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
+#define SYSCON_CK8M_TICK_NUM_V  0xFF
+#define SYSCON_CK8M_TICK_NUM_S  8
+/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: reg_xtal_tick_num.*/
+#define SYSCON_XTAL_TICK_NUM    0x000000FF
+#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
+#define SYSCON_XTAL_TICK_NUM_V  0xFF
+#define SYSCON_XTAL_TICK_NUM_S  0
+
+#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x8)
+/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: reg_clk_xtal_oen.*/
+#define SYSCON_CLK_XTAL_OEN    (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_V  0x1
+#define SYSCON_CLK_XTAL_OEN_S  10
+/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: reg_clk40x_bb_oen.*/
+#define SYSCON_CLK40X_BB_OEN    (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_V  0x1
+#define SYSCON_CLK40X_BB_OEN_S  9
+/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: reg_clk_dac_cpu_oen.*/
+#define SYSCON_CLK_DAC_CPU_OEN    (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
+#define SYSCON_CLK_DAC_CPU_OEN_S  8
+/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: reg_clk_adc_inf_oen.*/
+#define SYSCON_CLK_ADC_INF_OEN    (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_V  0x1
+#define SYSCON_CLK_ADC_INF_OEN_S  7
+/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: reg_clk_320m_oen.*/
+#define SYSCON_CLK_320M_OEN    (BIT(6))
+#define SYSCON_CLK_320M_OEN_M  (BIT(6))
+#define SYSCON_CLK_320M_OEN_V  0x1
+#define SYSCON_CLK_320M_OEN_S  6
+/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: reg_clk160_oen.*/
+#define SYSCON_CLK160_OEN    (BIT(5))
+#define SYSCON_CLK160_OEN_M  (BIT(5))
+#define SYSCON_CLK160_OEN_V  0x1
+#define SYSCON_CLK160_OEN_S  5
+/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: reg_clk80_oen.*/
+#define SYSCON_CLK80_OEN    (BIT(4))
+#define SYSCON_CLK80_OEN_M  (BIT(4))
+#define SYSCON_CLK80_OEN_V  0x1
+#define SYSCON_CLK80_OEN_S  4
+/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: reg_clk_bb_oen.*/
+#define SYSCON_CLK_BB_OEN    (BIT(3))
+#define SYSCON_CLK_BB_OEN_M  (BIT(3))
+#define SYSCON_CLK_BB_OEN_V  0x1
+#define SYSCON_CLK_BB_OEN_S  3
+/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: reg_clk44_oen.*/
+#define SYSCON_CLK44_OEN    (BIT(2))
+#define SYSCON_CLK44_OEN_M  (BIT(2))
+#define SYSCON_CLK44_OEN_V  0x1
+#define SYSCON_CLK44_OEN_S  2
+/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: reg_clk22_oen.*/
+#define SYSCON_CLK22_OEN    (BIT(1))
+#define SYSCON_CLK22_OEN_M  (BIT(1))
+#define SYSCON_CLK22_OEN_V  0x1
+#define SYSCON_CLK22_OEN_S  1
+/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: reg_clk20_oen.*/
+#define SYSCON_CLK20_OEN    (BIT(0))
+#define SYSCON_CLK20_OEN_M  (BIT(0))
+#define SYSCON_CLK20_OEN_V  0x1
+#define SYSCON_CLK20_OEN_S  0
+
+#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0xC)
+/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_bb_cfg.*/
+#define SYSCON_WIFI_BB_CFG    0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
+#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_S  0
+
+#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x10)
+/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_bb_cfg_2.*/
+#define SYSCON_WIFI_BB_CFG_2    0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
+#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_S  0
+
+#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x14)
+/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: reg_wifi_clk_en.*/
+#define SYSCON_WIFI_CLK_EN    0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
+#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_S  0
+
+#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x18)
+/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_wifi_rst.*/
+#define SYSCON_WIFI_RST    0xFFFFFFFF
+#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
+#define SYSCON_WIFI_RST_V  0xFFFFFFFF
+#define SYSCON_WIFI_RST_S  0
+
+#define SYSTEM_WIFI_CLK_EN_REG          SYSCON_WIFI_CLK_EN_REG
+/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define SYSTEM_WIFI_CLK_EN  0x00FB9FCF
+#define SYSTEM_WIFI_CLK_EN_M  ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
+#define SYSTEM_WIFI_CLK_EN_V  0x00FB9FCF
+#define SYSTEM_WIFI_CLK_EN_S  0
+
+/* Mask for all Wifi clock bits, 6 */
+#define SYSTEM_WIFI_CLK_WIFI_EN  0x0
+#define SYSTEM_WIFI_CLK_WIFI_EN_M  ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
+#define SYSTEM_WIFI_CLK_WIFI_EN_V  0x0
+#define SYSTEM_WIFI_CLK_WIFI_EN_S  0
+/* Mask for all Bluetooth clock bits, 11, 12, 16, 17 */
+#define SYSTEM_WIFI_CLK_BT_EN  0x0
+#define SYSTEM_WIFI_CLK_BT_EN_M  ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
+#define SYSTEM_WIFI_CLK_BT_EN_V  0x0
+#define SYSTEM_WIFI_CLK_BT_EN_S  0
+/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
+#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
+
+/* Digital team to check */
+//bluetooth baseband bit11
+#define SYSTEM_BT_BASEBAND_EN  BIT(11)
+//bluetooth LC bit16 and bit17
+#define SYSTEM_BT_LC_EN  (BIT(16)|BIT(17))
+
+/* Remaining single bit clock masks */
+#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
+#define SYSTEM_WIFI_CLK_UNUSED_BIT5  BIT(5)
+#define SYSTEM_WIFI_CLK_UNUSED_BIT12  BIT(12)
+#define SYSTEM_WIFI_CLK_EMAC_EN  BIT(14)
+#define SYSTEM_WIFI_CLK_RNG_EN  BIT(15)
+
+#define SYSTEM_CORE_RST_EN_REG        SYSTEM_WIFI_RST_EN_REG
+#define SYSTEM_WIFI_RST_EN_REG        SYSCON_WIFI_RST_EN_REG
+/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSTEM_BB_RST           BIT(0)
+#define SYSTEM_FE_RST           BIT(1)
+#define SYSTEM_MAC_RST          BIT(2)
+#define SYSTEM_BT_RST           BIT(3)
+#define SYSTEM_BTMAC_RST        BIT(4)
+#define SYSTEM_SDIO_RST         BIT(5)
+#define SYSTEM_EMAC_RST         BIT(7)
+#define SYSTEM_MACPWR_RST       BIT(8)
+#define SYSTEM_RW_BTMAC_RST     BIT(9)
+#define SYSTEM_RW_BTLP_RST      BIT(10)
+#define BLE_REG_REST_BIT        BIT(11)
+#define BLE_PWR_REG_REST_BIT    BIT(12)
+#define BLE_BB_REG_REST_BIT     BIT(13)
+#define BLE_RPA_REST_BIT        BIT(27)
+
+#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x1C)
+/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: reg_peri_io_swap.*/
+#define SYSCON_PERI_IO_SWAP    0x000000FF
+#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
+#define SYSCON_PERI_IO_SWAP_V  0xFF
+#define SYSCON_PERI_IO_SWAP_S  0
+
+#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x20)
+/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: reg_ext_mem_pms_lock.*/
+#define SYSCON_EXT_MEM_PMS_LOCK    (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
+#define SYSCON_EXT_MEM_PMS_LOCK_S  0
+
+#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x28)
+/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace0_attr.*/
+#define SYSCON_FLASH_ACE0_ATTR    0x00000003
+#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
+#define SYSCON_FLASH_ACE0_ATTR_V  0x3
+#define SYSCON_FLASH_ACE0_ATTR_S  0
+
+#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x2C)
+/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace1_attr.*/
+#define SYSCON_FLASH_ACE1_ATTR    0x00000003
+#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
+#define SYSCON_FLASH_ACE1_ATTR_V  0x3
+#define SYSCON_FLASH_ACE1_ATTR_S  0
+
+#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x30)
+/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace2_attr.*/
+#define SYSCON_FLASH_ACE2_ATTR    0x00000003
+#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
+#define SYSCON_FLASH_ACE2_ATTR_V  0x3
+#define SYSCON_FLASH_ACE2_ATTR_S  0
+
+#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x34)
+/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: reg_flash_ace3_attr.*/
+#define SYSCON_FLASH_ACE3_ATTR    0x00000003
+#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
+#define SYSCON_FLASH_ACE3_ATTR_V  0x3
+#define SYSCON_FLASH_ACE3_ATTR_S  0
+
+#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x38)
+/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_flash_ace0_addr_s.*/
+#define SYSCON_FLASH_ACE0_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
+#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x3C)
+/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
+/*description: reg_flash_ace1_addr_s.*/
+#define SYSCON_FLASH_ACE1_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
+#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x40)
+/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
+/*description: reg_flash_ace2_addr_s.*/
+#define SYSCON_FLASH_ACE2_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
+#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x44)
+/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hc00000 ; */
+/*description: reg_flash_ace3_addr_s.*/
+#define SYSCON_FLASH_ACE3_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
+#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x48)
+/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace0_size.*/
+#define SYSCON_FLASH_ACE0_SIZE    0x00001FFF
+#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
+#define SYSCON_FLASH_ACE0_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE0_SIZE_S  0
+
+#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x4C)
+/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace1_size.*/
+#define SYSCON_FLASH_ACE1_SIZE    0x00001FFF
+#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
+#define SYSCON_FLASH_ACE1_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE1_SIZE_S  0
+
+#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x50)
+/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace2_size.*/
+#define SYSCON_FLASH_ACE2_SIZE    0x00001FFF
+#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
+#define SYSCON_FLASH_ACE2_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE2_SIZE_S  0
+
+#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x54)
+/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: reg_flash_ace3_size.*/
+#define SYSCON_FLASH_ACE3_SIZE    0x00001FFF
+#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
+#define SYSCON_FLASH_ACE3_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE3_SIZE_S  0
+
+#define SYSCON_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x88)
+/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: reg_spi_mem_reject_cde.*/
+#define SYSCON_SPI_MEM_REJECT_CDE    0x0000001F
+#define SYSCON_SPI_MEM_REJECT_CDE_M  ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
+#define SYSCON_SPI_MEM_REJECT_CDE_V  0x1F
+#define SYSCON_SPI_MEM_REJECT_CDE_S  2
+/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reg_spi_mem_reject_clr.*/
+#define SYSCON_SPI_MEM_REJECT_CLR    (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_V  0x1
+#define SYSCON_SPI_MEM_REJECT_CLR_S  1
+/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: reg_spi_mem_reject_int.*/
+#define SYSCON_SPI_MEM_REJECT_INT    (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_V  0x1
+#define SYSCON_SPI_MEM_REJECT_INT_S  0
+
+#define SYSCON_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x8C)
+/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: reg_spi_mem_reject_addr.*/
+#define SYSCON_SPI_MEM_REJECT_ADDR    0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_M  ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
+#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
+
+#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x90)
+/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: reg_sdio_win_access_en.*/
+#define SYSCON_SDIO_WIN_ACCESS_EN    (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
+#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
+
+#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x94)
+/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: reg_redcy_andor.*/
+#define SYSCON_REDCY_ANDOR    (BIT(31))
+#define SYSCON_REDCY_ANDOR_M  (BIT(31))
+#define SYSCON_REDCY_ANDOR_V  0x1
+#define SYSCON_REDCY_ANDOR_S  31
+/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: reg_redcy_sig0.*/
+#define SYSCON_REDCY_SIG0    0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
+#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_S  0
+
+#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x98)
+/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: reg_redcy_nandor.*/
+#define SYSCON_REDCY_NANDOR    (BIT(31))
+#define SYSCON_REDCY_NANDOR_M  (BIT(31))
+#define SYSCON_REDCY_NANDOR_V  0x1
+#define SYSCON_REDCY_NANDOR_S  31
+/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: reg_redcy_sig1.*/
+#define SYSCON_REDCY_SIG1    0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
+#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_S  0
+
+#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x9C)
+/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: reg_freq_mem_force_pd.*/
+#define SYSCON_FREQ_MEM_FORCE_PD    (BIT(7))
+#define SYSCON_FREQ_MEM_FORCE_PD_M  (BIT(7))
+#define SYSCON_FREQ_MEM_FORCE_PD_V  0x1
+#define SYSCON_FREQ_MEM_FORCE_PD_S  7
+/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: reg_freq_mem_force_pu.*/
+#define SYSCON_FREQ_MEM_FORCE_PU    (BIT(6))
+#define SYSCON_FREQ_MEM_FORCE_PU_M  (BIT(6))
+#define SYSCON_FREQ_MEM_FORCE_PU_V  0x1
+#define SYSCON_FREQ_MEM_FORCE_PU_S  6
+/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: reg_dc_mem_force_pd.*/
+#define SYSCON_DC_MEM_FORCE_PD    (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_V  0x1
+#define SYSCON_DC_MEM_FORCE_PD_S  5
+/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: reg_dc_mem_force_pu.*/
+#define SYSCON_DC_MEM_FORCE_PU    (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_V  0x1
+#define SYSCON_DC_MEM_FORCE_PU_S  4
+/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: reg_pbus_mem_force_pd.*/
+#define SYSCON_PBUS_MEM_FORCE_PD    (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PD_S  3
+/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: reg_pbus_mem_force_pu.*/
+#define SYSCON_PBUS_MEM_FORCE_PU    (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PU_S  2
+/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: reg_agc_mem_force_pd.*/
+#define SYSCON_AGC_MEM_FORCE_PD    (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PD_S  1
+/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: reg_agc_mem_force_pu.*/
+#define SYSCON_AGC_MEM_FORCE_PU    (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PU_S  0
+
+#define SYSCON_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0xA0)
+/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: reg_nobypass_cpu_iso_rst.*/
+#define SYSCON_NOBYPASS_CPU_ISO_RST    (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x1
+#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
+/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: reg_retention_link_addr.*/
+#define SYSCON_RETENTION_LINK_ADDR    0x07FFFFFF
+#define SYSCON_RETENTION_LINK_ADDR_M  ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
+#define SYSCON_RETENTION_LINK_ADDR_V  0x7FFFFFF
+#define SYSCON_RETENTION_LINK_ADDR_S  0
+
+#define SYSCON_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0xA4)
+/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set the bit to 1 to force sram always have clock, for low power can clear to 0 t
+hen only when have access the sram have clock.*/
+#define SYSCON_SRAM_CLKGATE_FORCE_ON    0x0000000F
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0xF
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  3
+/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set the bit to 1 to force rom always have clock, for low power can clear to 0 th
+en only when have access the rom have clock.*/
+#define SYSCON_ROM_CLKGATE_FORCE_ON    0x00000007
+#define SYSCON_ROM_CLKGATE_FORCE_ON_M  ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
+#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x7
+#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
+
+#define SYSCON_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0xA8)
+/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set 1 to let sram power down.*/
+#define SYSCON_SRAM_POWER_DOWN    0x0000000F
+#define SYSCON_SRAM_POWER_DOWN_M  ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
+#define SYSCON_SRAM_POWER_DOWN_V  0xF
+#define SYSCON_SRAM_POWER_DOWN_S  3
+/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set 1 to let rom power down.*/
+#define SYSCON_ROM_POWER_DOWN    0x00000007
+#define SYSCON_ROM_POWER_DOWN_M  ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
+#define SYSCON_ROM_POWER_DOWN_V  0x7
+#define SYSCON_ROM_POWER_DOWN_S  0
+
+#define SYSCON_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0xAC)
+/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[6:3] ;default: 4'hf ; */
+/*description: Set 1 to let sram power up.*/
+#define SYSCON_SRAM_POWER_UP    0x0000000F
+#define SYSCON_SRAM_POWER_UP_M  ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
+#define SYSCON_SRAM_POWER_UP_V  0xF
+#define SYSCON_SRAM_POWER_UP_S  3
+/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set 1 to let rom power up.*/
+#define SYSCON_ROM_POWER_UP    0x00000007
+#define SYSCON_ROM_POWER_UP_M  ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
+#define SYSCON_ROM_POWER_UP_V  0x7
+#define SYSCON_ROM_POWER_UP_S  0
+
+#define SYSCON_RND_DATA_REG          (DR_REG_SYSCON_BASE + 0xB0)
+/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: reg_rnd_data.*/
+#define SYSCON_RND_DATA    0xFFFFFFFF
+#define SYSCON_RND_DATA_M  ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
+#define SYSCON_RND_DATA_V  0xFFFFFFFF
+#define SYSCON_RND_DATA_S  0
+
+#define SYSCON_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0xB4)
+/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: reg_peri_backup_ena.*/
+#define SYSCON_PERI_BACKUP_ENA    (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_M  (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_ENA_S  31
+/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: reg_peri_backup_to_mem.*/
+#define SYSCON_PERI_BACKUP_TO_MEM    (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_M  (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_V  0x1
+#define SYSCON_PERI_BACKUP_TO_MEM_S  30
+/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: reg_peri_backup_start.*/
+#define SYSCON_PERI_BACKUP_START    (BIT(29))
+#define SYSCON_PERI_BACKUP_START_M  (BIT(29))
+#define SYSCON_PERI_BACKUP_START_V  0x1
+#define SYSCON_PERI_BACKUP_START_S  29
+/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
+/*description: reg_peri_backup_size.*/
+#define SYSCON_PERI_BACKUP_SIZE    0x000003FF
+#define SYSCON_PERI_BACKUP_SIZE_M  ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
+#define SYSCON_PERI_BACKUP_SIZE_V  0x3FF
+#define SYSCON_PERI_BACKUP_SIZE_S  19
+/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
+/*description: reg_peri_backup_tout_thres.*/
+#define SYSCON_PERI_BACKUP_TOUT_THRES    0x000003FF
+#define SYSCON_PERI_BACKUP_TOUT_THRES_M  ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S))
+#define SYSCON_PERI_BACKUP_TOUT_THRES_V  0x3FF
+#define SYSCON_PERI_BACKUP_TOUT_THRES_S  9
+/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
+/*description: reg_peri_backup_burst_limit.*/
+#define SYSCON_PERI_BACKUP_BURST_LIMIT    0x0000001F
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_M  ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_V  0x1F
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_S  4
+/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: reg_peri_backup_flow_err.*/
+#define SYSCON_PERI_BACKUP_FLOW_ERR    0x00000003
+#define SYSCON_PERI_BACKUP_FLOW_ERR_M  ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
+#define SYSCON_PERI_BACKUP_FLOW_ERR_V  0x3
+#define SYSCON_PERI_BACKUP_FLOW_ERR_S  1
+
+#define SYSCON_PERI_BACKUP_APB_ADDR_REG          (DR_REG_SYSCON_BASE + 0xB8)
+/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: reg_backup_apb_start_addr.*/
+#define SYSCON_BACKUP_APB_START_ADDR    0xFFFFFFFF
+#define SYSCON_BACKUP_APB_START_ADDR_M  ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
+#define SYSCON_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
+#define SYSCON_BACKUP_APB_START_ADDR_S  0
+
+#define SYSCON_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_SYSCON_BASE + 0xBC)
+/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: reg_backup_mem_start_addr.*/
+#define SYSCON_BACKUP_MEM_START_ADDR    0xFFFFFFFF
+#define SYSCON_BACKUP_MEM_START_ADDR_M  ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
+#define SYSCON_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
+#define SYSCON_BACKUP_MEM_START_ADDR_S  0
+
+#define SYSCON_PERI_BACKUP_INT_RAW_REG          (DR_REG_SYSCON_BASE + 0xC0)
+/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_raw.*/
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_raw.*/
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S  0
+
+#define SYSCON_PERI_BACKUP_INT_ST_REG          (DR_REG_SYSCON_BASE + 0xC4)
+/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_st.*/
+#define SYSCON_PERI_BACKUP_ERR_INT_ST    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_st.*/
+#define SYSCON_PERI_BACKUP_DONE_INT_ST    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_S  0
+
+#define SYSCON_PERI_BACKUP_INT_ENA_REG          (DR_REG_SYSCON_BASE + 0xC8)
+/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_ena.*/
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_ena.*/
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S  0
+
+#define SYSCON_PERI_BACKUP_INT_CLR_REG          (DR_REG_SYSCON_BASE + 0xD0)
+/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: reg_peri_backup_err_int_clr.*/
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: reg_peri_backup_done_int_clr.*/
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S  0
+
+#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
+/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2106080 ; */
+/*description: reg_dateVersion control.*/
+#define SYSCON_DATE    0xFFFFFFFF
+#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
+#define SYSCON_DATE_V  0xFFFFFFFF
+#define SYSCON_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSCON_REG_H_ */
diff --git a/components/soc/esp32c2/include/soc/syscon_struct.h b/components/soc/esp32c2/register/soc/syscon_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/syscon_struct.h
rename to components/soc/esp32c2/register/soc/syscon_struct.h
diff --git a/components/soc/esp32c2/include/soc/system_reg.h b/components/soc/esp32c2/register/soc/system_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/system_reg.h
rename to components/soc/esp32c2/register/soc/system_reg.h
diff --git a/components/soc/esp32c2/include/soc/system_struct.h b/components/soc/esp32c2/register/soc/system_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/system_struct.h
rename to components/soc/esp32c2/register/soc/system_struct.h
diff --git a/components/soc/esp32c2/include/soc/systimer_reg.h b/components/soc/esp32c2/register/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/systimer_reg.h
rename to components/soc/esp32c2/register/soc/systimer_reg.h
diff --git a/components/soc/esp32c2/include/soc/systimer_struct.h b/components/soc/esp32c2/register/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/systimer_struct.h
rename to components/soc/esp32c2/register/soc/systimer_struct.h
diff --git a/components/soc/esp32c2/include/soc/timer_group_reg.h b/components/soc/esp32c2/register/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/timer_group_reg.h
rename to components/soc/esp32c2/register/soc/timer_group_reg.h
diff --git a/components/soc/esp32c2/include/soc/timer_group_struct.h b/components/soc/esp32c2/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32c2/include/soc/timer_group_struct.h
rename to components/soc/esp32c2/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32c2/register/soc/uart_reg.h b/components/soc/esp32c2/register/soc/uart_reg.h
new file mode 100644
index 00000000000..70413882e77
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/uart_reg.h
@@ -0,0 +1,1255 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_UART_REG_H_
+#define _SOC_UART_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
+/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: UART $n accesses FIFO via this register..*/
+#define UART_RXFIFO_RD_BYTE    0x000000FF
+#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
+#define UART_RXFIFO_RD_BYTE_V  0xFF
+#define UART_RXFIFO_RD_BYTE_S  0
+
+#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
+/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when input rxd edge changes more time
+s than what reg_active_threshold specifies in light sleeping mode..*/
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (BIT(19))
+#define UART_WAKEUP_INT_RAW_V  0x1
+#define UART_WAKEUP_INT_RAW_S  19
+/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects the configured
+at_cmd char..*/
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when detects a clash between transmit
+ter and receiver in rs485 mode..*/
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_V  0x1
+#define UART_RS485_CLASH_INT_RAW_S  17
+/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a data frame er
+ror from the echo of transmitter in rs485 mode..*/
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a parity error
+from the echo of transmitter in rs485 mode..*/
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has send out all dat
+a in FIFO..*/
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (BIT(14))
+#define UART_TX_DONE_INT_RAW_V  0x1
+#define UART_TX_DONE_INT_RAW_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has kept the shortes
+t duration after sending the  last data..*/
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter completes  sending
+NULL characters, after all data in Tx-FIFO are sent..*/
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a glitch in the
+ middle of a start bit..*/
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_V  0x1
+#define UART_GLITCH_DET_INT_RAW_S  11
+/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives Xoff char when
+ uart_sw_flow_con_en is set to 1..*/
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
+#define UART_SW_XOFF_INT_RAW_V  0x1
+#define UART_SW_XOFF_INT_RAW_S  10
+/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives Xon char when
+uart_sw_flow_con_en is set to 1..*/
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (BIT(9))
+#define UART_SW_XON_INT_RAW_V  0x1
+#define UART_SW_XON_INT_RAW_S  9
+/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver takes more time than rx
+_tout_thrhd to receive a byte..*/
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a 0 after the s
+top bit..*/
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (BIT(7))
+#define UART_BRK_DET_INT_RAW_V  0x1
+#define UART_BRK_DET_INT_RAW_S  7
+/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects the edge change
+ of CTSn signal..*/
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
+#define UART_CTS_CHG_INT_RAW_V  0x1
+#define UART_CTS_CHG_INT_RAW_S  6
+/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects the edge change
+ of DSRn signal..*/
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
+#define UART_DSR_CHG_INT_RAW_V  0x1
+#define UART_DSR_CHG_INT_RAW_S  5
+/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives more data than
+ the FIFO can store..*/
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_V  0x1
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a data frame er
+ror ..*/
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
+#define UART_FRM_ERR_INT_RAW_V  0x1
+#define UART_FRM_ERR_INT_RAW_S  3
+/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects a parity error
+in the data..*/
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_V  0x1
+#define UART_PARITY_ERR_INT_RAW_S  2
+/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */
+/*description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ less than what txfifo_empty_thrhd specifies ..*/
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives more data than
+ what rxfifo_full_thrhd specifies..*/
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_V  0x1
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+
+#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
+/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set t
+o 1..*/
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (BIT(19))
+#define UART_WAKEUP_INT_ST_V  0x1
+#define UART_WAKEUP_INT_ST_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is se
+t to 1..*/
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set t
+o 1..*/
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ST_V  0x1
+#define UART_RS485_CLASH_INT_ST_S  17
+/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is se
+t to 1..*/
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_V  0x1
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ set to 1..*/
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1..*/
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (BIT(14))
+#define UART_TX_DONE_INT_ST_V  0x1
+#define UART_TX_DONE_INT_ST_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en
+a is set to 1..*/
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set t
+o 1..*/
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
+1..*/
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ST_V  0x1
+#define UART_GLITCH_DET_INT_ST_S  11
+/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1..*/
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (BIT(10))
+#define UART_SW_XOFF_INT_ST_V  0x1
+#define UART_SW_XOFF_INT_ST_S  10
+/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1..*/
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (BIT(9))
+#define UART_SW_XON_INT_ST_V  0x1
+#define UART_SW_XON_INT_ST_S  9
+/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set t
+o 1..*/
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_V  0x1
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1..*/
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (BIT(7))
+#define UART_BRK_DET_INT_ST_V  0x1
+#define UART_BRK_DET_INT_ST_S  7
+/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1..*/
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (BIT(6))
+#define UART_CTS_CHG_INT_ST_V  0x1
+#define UART_CTS_CHG_INT_ST_S  6
+/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1..*/
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (BIT(5))
+#define UART_DSR_CHG_INT_ST_V  0x1
+#define UART_DSR_CHG_INT_ST_S  5
+/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
+1..*/
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_V  0x1
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1..*/
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (BIT(3))
+#define UART_FRM_ERR_INT_ST_V  0x1
+#define UART_FRM_ERR_INT_ST_S  3
+/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
+1..*/
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ST_V  0x1
+#define UART_PARITY_ERR_INT_ST_S  2
+/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is s
+et to 1..*/
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set t
+o 1..*/
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_V  0x1
+#define UART_RXFIFO_FULL_INT_ST_S  0
+
+#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
+/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the enable bit for uart_wakeup_int_st register..*/
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (BIT(19))
+#define UART_WAKEUP_INT_ENA_V  0x1
+#define UART_WAKEUP_INT_ENA_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the enable bit for at_cmd_char_det_int_st register..*/
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_clash_int_st register..*/
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_V  0x1
+#define UART_RS485_CLASH_INT_ENA_S  17
+/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register..*/
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register..*/
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_done_int_st register..*/
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (BIT(14))
+#define UART_TX_DONE_INT_ENA_V  0x1
+#define UART_TX_DONE_INT_ENA_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_idle_done_int_st register..*/
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_done_int_st register..*/
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the enable bit for glitch_det_int_st register..*/
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_V  0x1
+#define UART_GLITCH_DET_INT_ENA_S  11
+/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xoff_int_st register..*/
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
+#define UART_SW_XOFF_INT_ENA_V  0x1
+#define UART_SW_XOFF_INT_ENA_S  10
+/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xon_int_st register..*/
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (BIT(9))
+#define UART_SW_XON_INT_ENA_V  0x1
+#define UART_SW_XON_INT_ENA_S  9
+/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_tout_int_st register..*/
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the enable bit for brk_det_int_st register..*/
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (BIT(7))
+#define UART_BRK_DET_INT_ENA_V  0x1
+#define UART_BRK_DET_INT_ENA_S  7
+/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the enable bit for cts_chg_int_st register..*/
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
+#define UART_CTS_CHG_INT_ENA_V  0x1
+#define UART_CTS_CHG_INT_ENA_S  6
+/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the enable bit for dsr_chg_int_st register..*/
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
+#define UART_DSR_CHG_INT_ENA_V  0x1
+#define UART_DSR_CHG_INT_ENA_S  5
+/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_ovf_int_st register..*/
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_V  0x1
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the enable bit for frm_err_int_st register..*/
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
+#define UART_FRM_ERR_INT_ENA_V  0x1
+#define UART_FRM_ERR_INT_ENA_S  3
+/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the enable bit for parity_err_int_st register..*/
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_V  0x1
+#define UART_PARITY_ERR_INT_ENA_S  2
+/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the enable bit for txfifo_empty_int_st register..*/
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_full_int_st register..*/
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_V  0x1
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+
+#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
+/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to clear the uart_wakeup_int_raw interrupt..*/
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (BIT(19))
+#define UART_WAKEUP_INT_CLR_V  0x1
+#define UART_WAKEUP_INT_CLR_S  19
+/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt..*/
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_clash_int_raw interrupt..*/
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_V  0x1
+#define UART_RS485_CLASH_INT_CLR_S  17
+/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt..*/
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt..*/
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_done_int_raw interrupt..*/
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (BIT(14))
+#define UART_TX_DONE_INT_CLR_V  0x1
+#define UART_TX_DONE_INT_CLR_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt..*/
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_done_int_raw interrupt...*/
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the glitch_det_int_raw interrupt..*/
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_V  0x1
+#define UART_GLITCH_DET_INT_CLR_S  11
+/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xoff_int_raw interrupt..*/
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
+#define UART_SW_XOFF_INT_CLR_V  0x1
+#define UART_SW_XOFF_INT_CLR_S  10
+/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xon_int_raw interrupt..*/
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (BIT(9))
+#define UART_SW_XON_INT_CLR_V  0x1
+#define UART_SW_XON_INT_CLR_S  9
+/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt..*/
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the brk_det_int_raw interrupt..*/
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (BIT(7))
+#define UART_BRK_DET_INT_CLR_V  0x1
+#define UART_BRK_DET_INT_CLR_S  7
+/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the cts_chg_int_raw interrupt..*/
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
+#define UART_CTS_CHG_INT_CLR_V  0x1
+#define UART_CTS_CHG_INT_CLR_S  6
+/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the dsr_chg_int_raw interrupt..*/
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
+#define UART_DSR_CHG_INT_CLR_V  0x1
+#define UART_DSR_CHG_INT_CLR_S  5
+/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt..*/
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_V  0x1
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear frm_err_int_raw interrupt..*/
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
+#define UART_FRM_ERR_INT_CLR_V  0x1
+#define UART_FRM_ERR_INT_CLR_S  3
+/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear parity_err_int_raw interrupt..*/
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_V  0x1
+#define UART_PARITY_ERR_INT_CLR_S  2
+/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear txfifo_empty_int_raw interrupt..*/
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_full_int_raw interrupt..*/
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_V  0x1
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+
+#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
+/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
+/*description: The decimal part of the frequency divider factor..*/
+#define UART_CLKDIV_FRAG    0x0000000F
+#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
+#define UART_CLKDIV_FRAG_V  0xF
+#define UART_CLKDIV_FRAG_S  20
+/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2b6 ; */
+/*description: The integral part of the frequency divider factor..*/
+#define UART_CLKDIV    0x00000FFF
+#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
+#define UART_CLKDIV_V  0xFFF
+#define UART_CLKDIV_S  0
+
+#define UART_RX_FILT_REG(i)          (REG_UART_BASE(i) + 0x18)
+/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable Rx signal filter..*/
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (BIT(8))
+#define UART_GLITCH_FILT_EN_V  0x1
+#define UART_GLITCH_FILT_EN_S  8
+/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */
+/*description: when input pulse width is lower than this value, the pulse is ignored..*/
+#define UART_GLITCH_FILT    0x000000FF
+#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
+#define UART_GLITCH_FILT_V  0xFF
+#define UART_GLITCH_FILT_S  0
+
+#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
+/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */
+/*description: This bit represents the  level of the internal uart txd signal..*/
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (BIT(31))
+#define UART_TXD_V  0x1
+#define UART_TXD_S  31
+/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This bit represents the level of the internal uart rts signal..*/
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (BIT(30))
+#define UART_RTSN_V  0x1
+#define UART_RTSN_S  30
+/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit represents the level of the internal uart dtr signal..*/
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (BIT(29))
+#define UART_DTRN_V  0x1
+#define UART_DTRN_S  29
+/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */
+/*description: Stores the byte number of data in Tx-FIFO..*/
+#define UART_TXFIFO_CNT    0x000003FF
+#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
+#define UART_TXFIFO_CNT_V  0x3FF
+#define UART_TXFIFO_CNT_S  16
+/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */
+/*description: This register represent the  level value of the internal uart rxd signal..*/
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (BIT(15))
+#define UART_RXD_V  0x1
+#define UART_RXD_S  15
+/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */
+/*description: This register represent the level value of the internal uart cts signal..*/
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (BIT(14))
+#define UART_CTSN_V  0x1
+#define UART_CTSN_S  14
+/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The register represent the level value of the internal uart dsr signal..*/
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (BIT(13))
+#define UART_DSRN_V  0x1
+#define UART_DSRN_S  13
+/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: Stores the byte number of valid data in Rx-FIFO..*/
+#define UART_RXFIFO_CNT    0x000003FF
+#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
+#define UART_RXFIFO_CNT_V  0x3FF
+#define UART_RXFIFO_CNT_S  0
+
+#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
+/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */
+/*description: UART memory clock gate enable signal..*/
+#define UART_MEM_CLK_EN    (BIT(28))
+#define UART_MEM_CLK_EN_M  (BIT(28))
+#define UART_MEM_CLK_EN_V  0x1
+#define UART_MEM_CLK_EN_S  28
+/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This is the enable bit for detecting baudrate..*/
+#define UART_AUTOBAUD_EN    (BIT(27))
+#define UART_AUTOBAUD_EN_M  (BIT(27))
+#define UART_AUTOBAUD_EN_V  0x1
+#define UART_AUTOBAUD_EN_S  27
+/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver s
+tores the data even if the  received data is wrong..*/
+#define UART_ERR_WR_MASK    (BIT(26))
+#define UART_ERR_WR_MASK_M  (BIT(26))
+#define UART_ERR_WR_MASK_V  0x1
+#define UART_ERR_WR_MASK_S  26
+/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
+tes registers..*/
+#define UART_CLK_EN    (BIT(25))
+#define UART_CLK_EN_M  (BIT(25))
+#define UART_CLK_EN_V  0x1
+#define UART_CLK_EN_S  25
+/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dtr signal..*/
+#define UART_DTR_INV    (BIT(24))
+#define UART_DTR_INV_M  (BIT(24))
+#define UART_DTR_INV_V  0x1
+#define UART_DTR_INV_S  24
+/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rts signal..*/
+#define UART_RTS_INV    (BIT(23))
+#define UART_RTS_INV_M  (BIT(23))
+#define UART_RTS_INV_V  0x1
+#define UART_RTS_INV_S  23
+/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart txd signal..*/
+#define UART_TXD_INV    (BIT(22))
+#define UART_TXD_INV_M  (BIT(22))
+#define UART_TXD_INV_V  0x1
+#define UART_TXD_INV_S  22
+/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dsr signal..*/
+#define UART_DSR_INV    (BIT(21))
+#define UART_DSR_INV_M  (BIT(21))
+#define UART_DSR_INV_V  0x1
+#define UART_DSR_INV_S  21
+/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart cts signal..*/
+#define UART_CTS_INV    (BIT(20))
+#define UART_CTS_INV_M  (BIT(20))
+#define UART_CTS_INV_V  0x1
+#define UART_CTS_INV_S  20
+/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rxd signal..*/
+#define UART_RXD_INV    (BIT(19))
+#define UART_RXD_INV_M  (BIT(19))
+#define UART_RXD_INV_V  0x1
+#define UART_RXD_INV_S  19
+/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Set this bit to reset the uart transmit-FIFO..*/
+#define UART_TXFIFO_RST    (BIT(18))
+#define UART_TXFIFO_RST_M  (BIT(18))
+#define UART_TXFIFO_RST_V  0x1
+#define UART_TXFIFO_RST_S  18
+/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: Set this bit to reset the uart receive-FIFO..*/
+#define UART_RXFIFO_RST    (BIT(17))
+#define UART_RXFIFO_RST_M  (BIT(17))
+#define UART_RXFIFO_RST_V  0x1
+#define UART_RXFIFO_RST_S  17
+/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: Set this bit to enable IrDA protocol..*/
+#define UART_IRDA_EN    (BIT(16))
+#define UART_IRDA_EN_M  (BIT(16))
+#define UART_IRDA_EN_V  0x1
+#define UART_IRDA_EN_S  16
+/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable flow control function for transmitter..*/
+#define UART_TX_FLOW_EN    (BIT(15))
+#define UART_TX_FLOW_EN_M  (BIT(15))
+#define UART_TX_FLOW_EN_V  0x1
+#define UART_TX_FLOW_EN_S  15
+/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart loopback test mode..*/
+#define UART_LOOPBACK    (BIT(14))
+#define UART_LOOPBACK_M  (BIT(14))
+#define UART_LOOPBACK_V  0x1
+#define UART_LOOPBACK_S  14
+/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to invert the level of IrDA receiver..*/
+#define UART_IRDA_RX_INV    (BIT(13))
+#define UART_IRDA_RX_INV_M  (BIT(13))
+#define UART_IRDA_RX_INV_V  0x1
+#define UART_IRDA_RX_INV_S  13
+/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to invert the level of  IrDA transmitter..*/
+#define UART_IRDA_TX_INV    (BIT(12))
+#define UART_IRDA_TX_INV_M  (BIT(12))
+#define UART_IRDA_TX_INV_V  0x1
+#define UART_IRDA_TX_INV_S  12
+/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA tr
+ansmitter's 11th bit to 0..*/
+#define UART_IRDA_WCTL    (BIT(11))
+#define UART_IRDA_WCTL_M  (BIT(11))
+#define UART_IRDA_WCTL_V  0x1
+#define UART_IRDA_WCTL_S  11
+/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the start enable bit for IrDA transmitter..*/
+#define UART_IRDA_TX_EN    (BIT(10))
+#define UART_IRDA_TX_EN_M  (BIT(10))
+#define UART_IRDA_TX_EN_V  0x1
+#define UART_IRDA_TX_EN_S  10
+/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to enable IrDA loopback mode..*/
+#define UART_IRDA_DPLX    (BIT(9))
+#define UART_IRDA_DPLX_M  (BIT(9))
+#define UART_IRDA_DPLX_V  0x1
+#define UART_IRDA_DPLX_S  9
+/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter to  send NULL when the process of sending dat
+a is done..*/
+#define UART_TXD_BRK    (BIT(8))
+#define UART_TXD_BRK_M  (BIT(8))
+#define UART_TXD_BRK_V  0x1
+#define UART_TXD_BRK_S  8
+/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This register is used to configure the software dtr signal which is used in soft
+ware flow control..*/
+#define UART_SW_DTR    (BIT(7))
+#define UART_SW_DTR_M  (BIT(7))
+#define UART_SW_DTR_V  0x1
+#define UART_SW_DTR_S  7
+/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This register is used to configure the software rts signal which is used in soft
+ware flow control..*/
+#define UART_SW_RTS    (BIT(6))
+#define UART_SW_RTS_M  (BIT(6))
+#define UART_SW_RTS_V  0x1
+#define UART_SW_RTS_S  6
+/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
+/*description: This register is used to set the length of  stop bit..*/
+#define UART_STOP_BIT_NUM    0x00000003
+#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
+#define UART_STOP_BIT_NUM_V  0x3
+#define UART_STOP_BIT_NUM_S  4
+/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+/*description: This register is used to set the length of data..*/
+#define UART_BIT_NUM    0x00000003
+#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
+#define UART_BIT_NUM_V  0x3
+#define UART_BIT_NUM_S  2
+/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart parity check..*/
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (BIT(1))
+#define UART_PARITY_EN_V  0x1
+#define UART_PARITY_EN_S  1
+/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This register is used to configure the parity check mode..*/
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (BIT(0))
+#define UART_PARITY_V  0x1
+#define UART_PARITY_S  0
+
+#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
+/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: This is the enable bit for uart receiver's timeout function..*/
+#define UART_RX_TOUT_EN    (BIT(21))
+#define UART_RX_TOUT_EN_M  (BIT(21))
+#define UART_RX_TOUT_EN_V  0x1
+#define UART_RX_TOUT_EN_S  21
+/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This is the flow enable bit for UART receiver..*/
+#define UART_RX_FLOW_EN    (BIT(20))
+#define UART_RX_FLOW_EN_M  (BIT(20))
+#define UART_RX_FLOW_EN_V  0x1
+#define UART_RX_FLOW_EN_S  20
+/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works..*/
+#define UART_RX_TOUT_FLOW_DIS    (BIT(19))
+#define UART_RX_TOUT_FLOW_DIS_M  (BIT(19))
+#define UART_RX_TOUT_FLOW_DIS_V  0x1
+#define UART_RX_TOUT_FLOW_DIS_S  19
+/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Disable UART Rx data overflow detect..*/
+#define UART_DIS_RX_DAT_OVF    (BIT(18))
+#define UART_DIS_RX_DAT_OVF_M  (BIT(18))
+#define UART_DIS_RX_DAT_OVF_V  0x1
+#define UART_DIS_RX_DAT_OVF_S  18
+/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */
+/*description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is le
+ss than this register value..*/
+#define UART_TXFIFO_EMPTY_THRHD    0x000001FF
+#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
+#define UART_TXFIFO_EMPTY_THRHD_V  0x1FF
+#define UART_TXFIFO_EMPTY_THRHD_S  9
+/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */
+/*description: It will produce rxfifo_full_int interrupt when receiver receives more data than
+this register value..*/
+#define UART_RXFIFO_FULL_THRHD    0x000001FF
+#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
+#define UART_RXFIFO_FULL_THRHD_V  0x1FF
+#define UART_RXFIFO_FULL_THRHD_S  0
+
+#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
+/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
+/*description: This register stores the value of the minimum duration time of the low level pul
+se. It is used in baud rate-detect process..*/
+#define UART_LOWPULSE_MIN_CNT    0x00000FFF
+#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
+#define UART_LOWPULSE_MIN_CNT_V  0xFFF
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
+/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
+/*description: This register stores  the value of the maximum duration time for the high level
+pulse. It is used in baud rate-detect process..*/
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFF
+#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
+#define UART_HIGHPULSE_MIN_CNT_V  0xFFF
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
+/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the count of rxd edge change. It is used in baud rate-detec
+t process..*/
+#define UART_RXD_EDGE_CNT    0x000003FF
+#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
+#define UART_RXD_EDGE_CNT_V  0x3FF
+#define UART_RXD_EDGE_CNT_S  0
+
+#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
+/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to send Xoff char. It is cleared by hardware automatically..*/
+#define UART_SEND_XOFF    (BIT(5))
+#define UART_SEND_XOFF_M  (BIT(5))
+#define UART_SEND_XOFF_V  0x1
+#define UART_SEND_XOFF_S  5
+/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to send Xon char. It is cleared by hardware automatically..*/
+#define UART_SEND_XON    (BIT(4))
+#define UART_SEND_XON_M  (BIT(4))
+#define UART_SEND_XON_V  0x1
+#define UART_SEND_XON_S  4
+/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to stop the  transmitter from sending data..*/
+#define UART_FORCE_XOFF    (BIT(3))
+#define UART_FORCE_XOFF_M  (BIT(3))
+#define UART_FORCE_XOFF_V  0x1
+#define UART_FORCE_XOFF_S  3
+/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable the transmitter to go on sending data..*/
+#define UART_FORCE_XON    (BIT(2))
+#define UART_FORCE_XON_M  (BIT(2))
+#define UART_FORCE_XON_V  0x1
+#define UART_FORCE_XON_S  2
+/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to remove flow control char from the received data..*/
+#define UART_XONOFF_DEL    (BIT(1))
+#define UART_XONOFF_DEL_M  (BIT(1))
+#define UART_XONOFF_DEL_V  0x1
+#define UART_XONOFF_DEL_S  1
+/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable software flow control. It is used with register sw_xon or
+ sw_xoff..*/
+#define UART_SW_FLOW_CON_EN    (BIT(0))
+#define UART_SW_FLOW_CON_EN_M  (BIT(0))
+#define UART_SW_FLOW_CON_EN_V  0x1
+#define UART_SW_FLOW_CON_EN_S  0
+
+#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
+/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
+/*description: The uart is activated from light sleeping mode when the input rxd edge changes m
+or times than this register value..*/
+#define UART_ACTIVE_THRESHOLD    0x000003FF
+#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
+#define UART_ACTIVE_THRESHOLD_V  0x3FF
+#define UART_ACTIVE_THRESHOLD_S  0
+
+#define UART_SWFC_CONF0_REG(i)          (REG_UART_BASE(i) + 0x3C)
+/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */
+/*description: This register stores the Xoff flow control char..*/
+#define UART_XOFF_CHAR    0x000000FF
+#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
+#define UART_XOFF_CHAR_V  0xFF
+#define UART_XOFF_CHAR_S  9
+/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */
+/*description: When the data amount in Rx-FIFO is more than this register value with uart_sw_fl
+ow_con_en set to 1, it will send a Xoff char..*/
+#define UART_XOFF_THRESHOLD    0x000001FF
+#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
+#define UART_XOFF_THRESHOLD_V  0x1FF
+#define UART_XOFF_THRESHOLD_S  0
+
+#define UART_SWFC_CONF1_REG(i)          (REG_UART_BASE(i) + 0x40)
+/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */
+/*description: This register stores the Xon flow control char..*/
+#define UART_XON_CHAR    0x000000FF
+#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
+#define UART_XON_CHAR_V  0xFF
+#define UART_XON_CHAR_S  9
+/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: When the data amount in Rx-FIFO is less than this register value with uart_sw_fl
+ow_con_en set to 1, it will send a Xon char..*/
+#define UART_XON_THRESHOLD    0x000001FF
+#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
+#define UART_XON_THRESHOLD_V  0x1FF
+#define UART_XON_THRESHOLD_S  0
+
+#define UART_TXBRK_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
+/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */
+/*description: This register is used to configure the number of 0 to be sent after the process
+of sending data is done. It is active when txd_brk is set to 1..*/
+#define UART_TX_BRK_NUM    0x000000FF
+#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
+#define UART_TX_BRK_NUM_V  0xFF
+#define UART_TX_BRK_NUM_S  0
+
+#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x48)
+/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
+/*description: This register is used to configure the duration time between transfers..*/
+#define UART_TX_IDLE_NUM    0x000003FF
+#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
+#define UART_TX_IDLE_NUM_V  0x3FF
+#define UART_TX_IDLE_NUM_S  10
+/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: It will produce frame end signal when receiver takes more time to receive one byte
+data than this register value..*/
+#define UART_RX_IDLE_THRHD    0x000003FF
+#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
+#define UART_RX_IDLE_THRHD_V  0x3FF
+#define UART_RX_IDLE_THRHD_S  0
+
+#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x4C)
+/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
+/*description: This register is used to delay the transmitter's internal data signal..*/
+#define UART_RS485_TX_DLY_NUM    0x0000000F
+#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
+#define UART_RS485_TX_DLY_NUM_V  0xF
+#define UART_RS485_TX_DLY_NUM_S  6
+/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This register is used to delay the receiver's internal data signal..*/
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
+#define UART_RS485_RX_DLY_NUM_V  0x1
+#define UART_RS485_RX_DLY_NUM_S  5
+/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy..*/
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (BIT(4))
+#define UART_RS485RXBY_TX_EN_V  0x1
+#define UART_RS485RXBY_TX_EN_S  4
+/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver could receive data when the transmitter is trans
+mitting data in rs485 mode..*/
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (BIT(3))
+#define UART_RS485TX_RX_EN_V  0x1
+#define UART_RS485TX_RX_EN_S  3
+/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit..*/
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (BIT(2))
+#define UART_DL1_EN_V  0x1
+#define UART_DL1_EN_S  2
+/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit..*/
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (BIT(1))
+#define UART_DL0_EN_V  0x1
+#define UART_DL0_EN_S  1
+/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to choose the rs485 mode..*/
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (BIT(0))
+#define UART_RS485_EN_V  0x1
+#define UART_RS485_EN_S  0
+
+#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x50)
+/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: This register is used to configure the idle duration time before the first at_cm
+d is received by receiver..*/
+#define UART_PRE_IDLE_NUM    0x0000FFFF
+#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
+#define UART_PRE_IDLE_NUM_V  0xFFFF
+#define UART_PRE_IDLE_NUM_S  0
+
+#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x54)
+/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: This register is used to configure the duration time between the last at_cmd and
+ the next data..*/
+#define UART_POST_IDLE_NUM    0x0000FFFF
+#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
+#define UART_POST_IDLE_NUM_V  0xFFFF
+#define UART_POST_IDLE_NUM_S  0
+
+#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x58)
+/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */
+/*description: This register is used to configure the duration time between the at_cmd chars..*/
+#define UART_RX_GAP_TOUT    0x0000FFFF
+#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
+#define UART_RX_GAP_TOUT_V  0xFFFF
+#define UART_RX_GAP_TOUT_S  0
+
+#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x5C)
+/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
+/*description: This register is used to configure the num of continuous at_cmd chars received b
+y receiver..*/
+#define UART_CHAR_NUM    0x000000FF
+#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
+#define UART_CHAR_NUM_V  0xFF
+#define UART_CHAR_NUM_S  8
+/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
+/*description: This register is used to configure the content of at_cmd char..*/
+#define UART_AT_CMD_CHAR    0x000000FF
+#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
+#define UART_AT_CMD_CHAR_V  0xFF
+#define UART_AT_CMD_CHAR_S  0
+
+#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x60)
+/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to force power up UART memory..*/
+#define UART_MEM_FORCE_PU    (BIT(27))
+#define UART_MEM_FORCE_PU_M  (BIT(27))
+#define UART_MEM_FORCE_PU_V  0x1
+#define UART_MEM_FORCE_PU_S  27
+/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to force power down UART memory..*/
+#define UART_MEM_FORCE_PD    (BIT(26))
+#define UART_MEM_FORCE_PD_M  (BIT(26))
+#define UART_MEM_FORCE_PD_V  0x1
+#define UART_MEM_FORCE_PD_S  26
+/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */
+/*description: This register is used to configure the threshold time that receiver takes to rec
+eive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver t
+akes more time to receive one byte with rx_tout_en set to 1..*/
+#define UART_RX_TOUT_THRHD    0x000003FF
+#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
+#define UART_RX_TOUT_THRHD_V  0x3FF
+#define UART_RX_TOUT_THRHD_S  16
+/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
+/*description: This register is used to configure the maximum amount of data that can be receive
+ed  when hardware flow control works..*/
+#define UART_RX_FLOW_THRHD    0x000001FF
+#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
+#define UART_RX_FLOW_THRHD_V  0x1FF
+#define UART_RX_FLOW_THRHD_S  7
+/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */
+/*description: This register is used to configure the amount of mem allocated for transmit-FIFO
+. The default number is 128 bytes..*/
+#define UART_TX_SIZE    0x00000007
+#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
+#define UART_TX_SIZE_V  0x7
+#define UART_TX_SIZE_S  4
+/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */
+/*description: This register is used to configure the amount of mem allocated for receive-FIFO.
+ The default number is 128 bytes..*/
+#define UART_RX_SIZE    0x00000007
+#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
+#define UART_RX_SIZE_V  0x7
+#define UART_RX_SIZE_S  1
+
+#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
+/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
+/*description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx
+-FIFO_Ctrl..*/
+#define UART_TX_RADDR    0x000003FF
+#define UART_TX_RADDR_M  ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S))
+#define UART_TX_RADDR_V  0x3FF
+#define UART_TX_RADDR_S  11
+/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
+via APB..*/
+#define UART_APB_TX_WADDR    0x000003FF
+#define UART_APB_TX_WADDR_M  ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S))
+#define UART_APB_TX_WADDR_V  0x3FF
+#define UART_APB_TX_WADDR_S  0
+
+#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x68)
+/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h100 ; */
+/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-F
+IFO. UART0 is 10'h100. UART1 is 10'h180..*/
+#define UART_RX_WADDR    0x000003FF
+#define UART_RX_WADDR_M  ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
+#define UART_RX_WADDR_V  0x3FF
+#define UART_RX_WADDR_S  11
+/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: This register stores the offset address in RX-FIFO when software reads data from
+ Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180..*/
+#define UART_APB_RX_RADDR    0x000003FF
+#define UART_APB_RX_RADDR_M  ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S))
+#define UART_APB_RX_RADDR_V  0x3FF
+#define UART_APB_RX_RADDR_S  0
+
+#define UART_FSM_STATUS_REG(i)          (REG_UART_BASE(i) + 0x6C)
+/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: This is the status register of transmitter..*/
+#define UART_ST_UTX_OUT    0x0000000F
+#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
+#define UART_ST_UTX_OUT_V  0xF
+#define UART_ST_UTX_OUT_S  4
+/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: This is the status register of receiver..*/
+#define UART_ST_URX_OUT    0x0000000F
+#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
+#define UART_ST_URX_OUT_V  0xF
+#define UART_ST_URX_OUT_S  0
+
+#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x70)
+/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
+/*description: This register stores the minimal input clock count between two positive edges. I
+t is used in boudrate-detect process..*/
+#define UART_POSEDGE_MIN_CNT    0x00000FFF
+#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
+#define UART_POSEDGE_MIN_CNT_V  0xFFF
+#define UART_POSEDGE_MIN_CNT_S  0
+
+#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x74)
+/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
+/*description: This register stores the minimal input clock count between two negative edges. I
+t is used in boudrate-detect process..*/
+#define UART_NEGEDGE_MIN_CNT    0x00000FFF
+#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
+#define UART_NEGEDGE_MIN_CNT_V  0xFFF
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+#define UART_CLK_CONF_REG(i)          (REG_UART_BASE(i) + 0x78)
+/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit, reset UART Rx..*/
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (BIT(27))
+#define UART_RX_RST_CORE_V  0x1
+#define UART_RX_RST_CORE_S  27
+/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit, reset UART Tx..*/
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (BIT(26))
+#define UART_TX_RST_CORE_V  0x1
+#define UART_TX_RST_CORE_S  26
+/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Rx clock..*/
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (BIT(25))
+#define UART_RX_SCLK_EN_V  0x1
+#define UART_RX_SCLK_EN_S  25
+/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Tx clock..*/
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (BIT(24))
+#define UART_TX_SCLK_EN_V  0x1
+#define UART_TX_SCLK_EN_S  24
+/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit, reset UART Tx/Rx..*/
+#define UART_RST_CORE    (BIT(23))
+#define UART_RST_CORE_M  (BIT(23))
+#define UART_RST_CORE_V  0x1
+#define UART_RST_CORE_S  23
+/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Tx/Rx clock..*/
+#define UART_SCLK_EN    (BIT(22))
+#define UART_SCLK_EN_M  (BIT(22))
+#define UART_SCLK_EN_V  0x1
+#define UART_SCLK_EN_S  22
+/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */
+/*description: UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL..*/
+#define UART_SCLK_SEL    0x00000003
+#define UART_SCLK_SEL_M  ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S))
+#define UART_SCLK_SEL_V  0x3
+#define UART_SCLK_SEL_S  20
+/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */
+/*description: The integral part of the frequency divider factor..*/
+#define UART_SCLK_DIV_NUM    0x000000FF
+#define UART_SCLK_DIV_NUM_M  ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S))
+#define UART_SCLK_DIV_NUM_V  0xFF
+#define UART_SCLK_DIV_NUM_S  12
+/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */
+/*description: The numerator of the frequency divider factor..*/
+#define UART_SCLK_DIV_A    0x0000003F
+#define UART_SCLK_DIV_A_M  ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S))
+#define UART_SCLK_DIV_A_V  0x3F
+#define UART_SCLK_DIV_A_S  6
+/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: The  denominator of the frequency divider factor..*/
+#define UART_SCLK_DIV_B    0x0000003F
+#define UART_SCLK_DIV_B_M  ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S))
+#define UART_SCLK_DIV_B_V  0x3F
+#define UART_SCLK_DIV_B_S  0
+
+#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x7C)
+/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */
+/*description: This is the version register..*/
+#define UART_DATE    0xFFFFFFFF
+#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
+#define UART_DATE_V  0xFFFFFFFF
+#define UART_DATE_S  0
+
+#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x80)
+/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Software write 1 would synchronize registers into UART Core clock domain and wou
+ld be cleared by hardware after synchronization is done..*/
+#define UART_UPDATE    (BIT(31))
+#define UART_UPDATE_M  (BIT(31))
+#define UART_UPDATE_V  0x1
+#define UART_UPDATE_S  31
+/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This bit used to select synchronize mode. 1: Registers are auto synchronized int
+o UART Core clock and UART core should be keep the same with APB clock. 0: After
+ configure registers, software needs to write 1 to UART_REG_UPDATE to synchroniz
+e registers..*/
+#define UART_HIGH_SPEED    (BIT(30))
+#define UART_HIGH_SPEED_M  (BIT(30))
+#define UART_HIGH_SPEED_V  0x1
+#define UART_HIGH_SPEED_S  30
+/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */
+/*description: This register is used to configure the uart_id..*/
+#define UART_ID    0x3FFFFFFF
+#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
+#define UART_ID_V  0x3FFFFFFF
+#define UART_ID_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UART_REG_H_ */
diff --git a/components/soc/esp32c2/register/soc/uart_struct.h b/components/soc/esp32c2/register/soc/uart_struct.h
new file mode 100644
index 00000000000..5082bf267d2
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/uart_struct.h
@@ -0,0 +1,398 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct uart_dev_s {
+    union {
+        struct {
+            uint32_t rw_byte                       :    32;  /*UART $n accesses FIFO via this register.*/
+        };
+        uint32_t val;
+    } ahb_fifo;
+    union {
+        struct {
+            uint32_t rxfifo_full                   :    1;  /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
+            uint32_t txfifo_empty                  :    1;  /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
+            uint32_t parity_err                    :    1;  /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
+            uint32_t frm_err                       :    1;  /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
+            uint32_t rxfifo_ovf                    :    1;  /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
+            uint32_t dsr_chg                       :    1;  /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
+            uint32_t cts_chg                       :    1;  /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
+            uint32_t brk_det                       :    1;  /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
+            uint32_t rxfifo_tout                   :    1;  /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
+            uint32_t sw_xon                        :    1;  /*This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1.*/
+            uint32_t sw_xoff                       :    1;  /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
+            uint32_t glitch_det                    :    1;  /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
+            uint32_t tx_brk_done                   :    1;  /*This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.*/
+            uint32_t tx_brk_idle_done              :    1;  /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.*/
+            uint32_t tx_done                       :    1;  /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
+            uint32_t rs485_parity_err              :    1;  /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
+            uint32_t rs485_frm_err                 :    1;  /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
+            uint32_t rs485_clash                   :    1;  /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
+            uint32_t at_cmd_char_det               :    1;  /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
+            uint32_t wakeup                        :    1;  /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rxfifo_full                   :    1;  /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
+            uint32_t txfifo_empty                  :    1;  /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
+            uint32_t parity_err                    :    1;  /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
+            uint32_t frm_err                       :    1;  /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
+            uint32_t rxfifo_ovf                    :    1;  /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
+            uint32_t dsr_chg                       :    1;  /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
+            uint32_t cts_chg                       :    1;  /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
+            uint32_t brk_det                       :    1;  /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
+            uint32_t rxfifo_tout                   :    1;  /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
+            uint32_t sw_xon                        :    1;  /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
+            uint32_t sw_xoff                       :    1;  /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
+            uint32_t glitch_det                    :    1;  /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
+            uint32_t tx_brk_done                   :    1;  /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
+            uint32_t tx_brk_idle_done              :    1;  /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
+            uint32_t tx_done                       :    1;  /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
+            uint32_t rs485_parity_err              :    1;  /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
+            uint32_t rs485_frm_err                 :    1;  /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
+            uint32_t rs485_clash                   :    1;  /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
+            uint32_t at_cmd_char_det               :    1;  /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
+            uint32_t wakeup                        :    1;  /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rxfifo_full                   :    1;  /*This is the enable bit for rxfifo_full_int_st register.*/
+            uint32_t txfifo_empty                  :    1;  /*This is the enable bit for txfifo_empty_int_st register.*/
+            uint32_t parity_err                    :    1;  /*This is the enable bit for parity_err_int_st register.*/
+            uint32_t frm_err                       :    1;  /*This is the enable bit for frm_err_int_st register.*/
+            uint32_t rxfifo_ovf                    :    1;  /*This is the enable bit for rxfifo_ovf_int_st register.*/
+            uint32_t dsr_chg                       :    1;  /*This is the enable bit for dsr_chg_int_st register.*/
+            uint32_t cts_chg                       :    1;  /*This is the enable bit for cts_chg_int_st register.*/
+            uint32_t brk_det                       :    1;  /*This is the enable bit for brk_det_int_st register.*/
+            uint32_t rxfifo_tout                   :    1;  /*This is the enable bit for rxfifo_tout_int_st register.*/
+            uint32_t sw_xon                        :    1;  /*This is the enable bit for sw_xon_int_st register.*/
+            uint32_t sw_xoff                       :    1;  /*This is the enable bit for sw_xoff_int_st register.*/
+            uint32_t glitch_det                    :    1;  /*This is the enable bit for glitch_det_int_st register.*/
+            uint32_t tx_brk_done                   :    1;  /*This is the enable bit for tx_brk_done_int_st register.*/
+            uint32_t tx_brk_idle_done              :    1;  /*This is the enable bit for tx_brk_idle_done_int_st register.*/
+            uint32_t tx_done                       :    1;  /*This is the enable bit for tx_done_int_st register.*/
+            uint32_t rs485_parity_err              :    1;  /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_frm_err                 :    1;  /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_clash                   :    1;  /*This is the enable bit for rs485_clash_int_st register.*/
+            uint32_t at_cmd_char_det               :    1;  /*This is the enable bit for at_cmd_char_det_int_st register.*/
+            uint32_t wakeup                        :    1;  /*This is the enable bit for uart_wakeup_int_st register.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rxfifo_full                   :    1;  /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
+            uint32_t txfifo_empty                  :    1;  /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
+            uint32_t parity_err                    :    1;  /*Set this bit to clear parity_err_int_raw interrupt.*/
+            uint32_t frm_err                       :    1;  /*Set this bit to clear frm_err_int_raw interrupt.*/
+            uint32_t rxfifo_ovf                    :    1;  /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
+            uint32_t dsr_chg                       :    1;  /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
+            uint32_t cts_chg                       :    1;  /*Set this bit to clear the cts_chg_int_raw interrupt.*/
+            uint32_t brk_det                       :    1;  /*Set this bit to clear the brk_det_int_raw interrupt.*/
+            uint32_t rxfifo_tout                   :    1;  /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
+            uint32_t sw_xon                        :    1;  /*Set this bit to clear the sw_xon_int_raw interrupt.*/
+            uint32_t sw_xoff                       :    1;  /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
+            uint32_t glitch_det                    :    1;  /*Set this bit to clear the glitch_det_int_raw interrupt.*/
+            uint32_t tx_brk_done                   :    1;  /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
+            uint32_t tx_brk_idle_done              :    1;  /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
+            uint32_t tx_done                       :    1;  /*Set this bit to clear the tx_done_int_raw interrupt.*/
+            uint32_t rs485_parity_err              :    1;  /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
+            uint32_t rs485_frm_err                 :    1;  /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
+            uint32_t rs485_clash                   :    1;  /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
+            uint32_t at_cmd_char_det               :    1;  /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
+            uint32_t wakeup                        :    1;  /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t div_int                       :    12;  /*The integral part of the frequency divider factor.*/
+            uint32_t reserved12                    :    8;
+            uint32_t div_frag                      :    4;  /*The decimal part of the frequency divider factor.*/
+            uint32_t reserved24                    :    8;  /*Reserved*/
+        };
+        uint32_t val;
+    } clk_div;
+    union {
+        struct {
+            uint32_t glitch_filt                   :    8;  /*when input pulse width is lower than this value, the pulse is ignored.*/
+            uint32_t glitch_filt_en                :    1;  /*Set this bit to enable Rx signal filter.*/
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } rx_filt;
+    union {
+        struct {
+            uint32_t rxfifo_cnt                    :    10;  /*Stores the byte number of valid data in Rx-FIFO.*/
+            uint32_t reserved10                    :    3;
+            uint32_t dsrn                          :    1;  /*The register represent the level value of the internal uart dsr signal.*/
+            uint32_t ctsn                          :    1;  /*This register represent the level value of the internal uart cts signal.*/
+            uint32_t rxd                           :    1;  /*This register represent the  level value of the internal uart rxd signal.*/
+            uint32_t txfifo_cnt                    :    10;  /*Stores the byte number of data in Tx-FIFO.*/
+            uint32_t reserved26                    :    3;  /*Reserved*/
+            uint32_t dtrn                          :    1;  /*This bit represents the level of the internal uart dtr signal.*/
+            uint32_t rtsn                          :    1;  /*This bit represents the level of the internal uart rts signal.*/
+            uint32_t txd                           :    1;  /*This bit represents the  level of the internal uart txd signal.*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t parity                        :    1;  /*This register is used to configure the parity check mode.*/
+            uint32_t parity_en                     :    1;  /*Set this bit to enable uart parity check.*/
+            uint32_t bit_num                       :    2;  /*This register is used to set the length of data.*/
+            uint32_t stop_bit_num                  :    2;  /*This register is used to set the length of  stop bit.*/
+            uint32_t sw_rts                        :    1;  /*This register is used to configure the software rts signal which is used in software flow control.*/
+            uint32_t sw_dtr                        :    1;  /*This register is used to configure the software dtr signal which is used in software flow control.*/
+            uint32_t txd_brk                       :    1;  /*Set this bit to enable transmitter to  send NULL when the process of sending data is done.*/
+            uint32_t irda_dplx                     :    1;  /*Set this bit to enable IrDA loopback mode.*/
+            uint32_t irda_tx_en                    :    1;  /*This is the start enable bit for IrDA transmitter.*/
+            uint32_t irda_wctl                     :    1;  /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
+            uint32_t irda_tx_inv                   :    1;  /*Set this bit to invert the level of  IrDA transmitter.*/
+            uint32_t irda_rx_inv                   :    1;  /*Set this bit to invert the level of IrDA receiver.*/
+            uint32_t loopback                      :    1;  /*Set this bit to enable uart loopback test mode.*/
+            uint32_t tx_flow_en                    :    1;  /*Set this bit to enable flow control function for transmitter.*/
+            uint32_t irda_en                       :    1;  /*Set this bit to enable IrDA protocol.*/
+            uint32_t rxfifo_rst                    :    1;  /*Set this bit to reset the uart receive-FIFO.*/
+            uint32_t txfifo_rst                    :    1;  /*Set this bit to reset the uart transmit-FIFO.*/
+            uint32_t rxd_inv                       :    1;  /*Set this bit to inverse the level value of uart rxd signal.*/
+            uint32_t cts_inv                       :    1;  /*Set this bit to inverse the level value of uart cts signal.*/
+            uint32_t dsr_inv                       :    1;  /*Set this bit to inverse the level value of uart dsr signal.*/
+            uint32_t txd_inv                       :    1;  /*Set this bit to inverse the level value of uart txd signal.*/
+            uint32_t rts_inv                       :    1;  /*Set this bit to inverse the level value of uart rts signal.*/
+            uint32_t dtr_inv                       :    1;  /*Set this bit to inverse the level value of uart dtr signal.*/
+            uint32_t clk_en                        :    1;  /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
+            uint32_t err_wr_mask                   :    1;  /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.*/
+            uint32_t autobaud_en                   :    1;  /*This is the enable bit for detecting baudrate.*/
+            uint32_t mem_clk_en                    :    1;  /*UART memory clock gate enable signal.*/
+            uint32_t reserved29                    :    3;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t rxfifo_full_thrhd             :    9;  /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
+            uint32_t txfifo_empty_thrhd            :    9;  /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
+            uint32_t dis_rx_dat_ovf                :    1;  /*Disable UART Rx data overflow detect. */
+            uint32_t rx_tout_flow_dis              :    1;  /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
+            uint32_t rx_flow_en                    :    1;  /*This is the flow enable bit for UART receiver.*/
+            uint32_t rx_tout_en                    :    1;  /*This is the enable bit for uart receiver's timeout function.*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } conf1;
+    union {
+        struct {
+            uint32_t min_cnt                       :    12;  /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
+            uint32_t reserved12                    :    20;  /*Reserved*/
+        };
+        uint32_t val;
+    } lowpulse;
+    union {
+        struct {
+            uint32_t min_cnt                       :    12;  /*This register stores  the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process.*/
+            uint32_t reserved12                    :    20;  /*Reserved*/
+        };
+        uint32_t val;
+    } highpulse;
+    union {
+        struct {
+            uint32_t edge_cnt                      :    10;  /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
+            uint32_t reserved10                    :    22;  /*Reserved*/
+        };
+        uint32_t val;
+    } rxd_cnt;
+    union {
+        struct {
+            uint32_t sw_flow_con_en                :    1;  /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
+            uint32_t xonoff_del                    :    1;  /*Set this bit to remove flow control char from the received data.*/
+            uint32_t force_xon                     :    1;  /*Set this bit to enable the transmitter to go on sending data.*/
+            uint32_t force_xoff                    :    1;  /*Set this bit to stop the  transmitter from sending data.*/
+            uint32_t send_xon                      :    1;  /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
+            uint32_t send_xoff                     :    1;  /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
+            uint32_t reserved6                     :    26;  /*Reserved*/
+        };
+        uint32_t val;
+    } flow_conf;
+    union {
+        struct {
+            uint32_t active_threshold              :    10;  /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
+            uint32_t reserved10                    :    22;  /*Reserved*/
+        };
+        uint32_t val;
+    } sleep_conf;
+    union {
+        struct {
+            uint32_t xoff_threshold                :    9;  /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.*/
+            uint32_t xoff_character                :    8;  /*This register stores the Xoff flow control char.*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } swfc_conf0;
+    union {
+        struct {
+            uint32_t xon_threshold                 :    9;  /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.*/
+            uint32_t xon_character                 :    8;  /*This register stores the Xon flow control char.*/
+            uint32_t reserved17                    :    15;  /*Reserved*/
+        };
+        uint32_t val;
+    } swfc_conf1;
+    union {
+        struct {
+            uint32_t tx_brk_num                    :    8;  /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } txbrk_conf;
+    union {
+        struct {
+            uint32_t rx_idle_thrhd                 :    10;  /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
+            uint32_t tx_idle_num                   :    10;  /*This register is used to configure the duration time between transfers.*/
+            uint32_t reserved20                    :    12;  /*Reserved*/
+        };
+        uint32_t val;
+    } idle_conf;
+    union {
+        struct {
+            uint32_t en                            :    1;  /*Set this bit to choose the rs485 mode.*/
+            uint32_t dl0_en                        :    1;  /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t dl1_en                        :    1;  /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t tx_rx_en                      :    1;  /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.  */
+            uint32_t rx_busy_tx_en                 :    1;  /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. */
+            uint32_t rx_dly_num                    :    1;  /*This register is used to delay the receiver's internal data signal.*/
+            uint32_t tx_dly_num                    :    4;  /*This register is used to delay the transmitter's internal data signal.*/
+            uint32_t reserved10                    :    22;  /*Reserved*/
+        };
+        uint32_t val;
+    } rs485_conf;
+    union {
+        struct {
+            uint32_t pre_idle_num                  :    16;  /*This register is used to configure the idle duration time before the first at_cmd is received by receiver. */
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_precnt;
+    union {
+        struct {
+            uint32_t post_idle_num                 :    16;  /*This register is used to configure the duration time between the last at_cmd and the next data.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_postcnt;
+    union {
+        struct {
+            uint32_t rx_gap_tout                   :    16;  /*This register is used to configure the duration time between the at_cmd chars.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_gaptout;
+    union {
+        struct {
+            uint32_t data                          :    8;  /*This register is used to configure the content of at_cmd char.*/
+            uint32_t at_char_num                   :    8;  /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
+            uint32_t reserved16                    :    16;  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_char;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;
+            uint32_t rx_size                       :    3;  /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
+            uint32_t tx_size                       :    3;  /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
+            uint32_t rx_flow_thrhd                 :    9;  /*This register is used to configure the maximum amount of data that can be received  when hardware flow control works.*/
+            uint32_t rx_tout_thrhd                 :    10;  /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
+            uint32_t force_pd                      :    1;  /*Set this bit to force power down UART memory.*/
+            uint32_t force_pu                      :    1;  /*Set this bit to force power up UART memory.*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } mem_conf;
+    union {
+        struct {
+            uint32_t apb_tx_waddr                  :    10;  /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
+            uint32_t reserved10                    :    1;  /*Reserved*/
+            uint32_t tx_raddr                      :    10;  /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } mem_tx_status;
+    union {
+        struct {
+            uint32_t apb_rx_raddr                  :    10;  /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
+            uint32_t reserved10                    :    1;  /*Reserved*/
+            uint32_t rx_waddr                      :    10;  /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
+            uint32_t reserved21                    :    11;  /*Reserved*/
+        };
+        uint32_t val;
+    } mem_rx_status;
+    union {
+        struct {
+            uint32_t st_urx_out                    :    4;  /*This is the status register of receiver.*/
+            uint32_t st_utx_out                    :    4;  /*This is the status register of transmitter.*/
+            uint32_t reserved8                     :    24;  /*Reserved*/
+        };
+        uint32_t val;
+    } fsm_status;
+    union {
+        struct {
+            uint32_t min_cnt                       :    12;  /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
+            uint32_t reserved12                    :    20;  /*Reserved*/
+        };
+        uint32_t val;
+    } pospulse;
+    union {
+        struct {
+            uint32_t min_cnt                       :    12;  /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
+            uint32_t reserved12                    :    20;  /*Reserved*/
+        };
+        uint32_t val;
+    } negpulse;
+    union {
+        struct {
+            uint32_t sclk_div_b                    :    6;  /*The  denominator of the frequency divider factor.*/
+            uint32_t sclk_div_a                    :    6;  /*The numerator of the frequency divider factor.*/
+            uint32_t sclk_div_num                  :    8;  /*The integral part of the frequency divider factor.*/
+            uint32_t sclk_sel                      :    2;  /*UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.*/
+            uint32_t sclk_en                       :    1;  /*Set this bit to enable UART Tx/Rx clock.*/
+            uint32_t rst_core                      :    1;  /*Write 1 then write 0 to this bit, reset UART Tx/Rx.*/
+            uint32_t tx_sclk_en                    :    1;  /*Set this bit to enable UART Tx clock.*/
+            uint32_t rx_sclk_en                    :    1;  /*Set this bit to enable UART Rx clock.*/
+            uint32_t tx_rst_core                   :    1;  /*Write 1 then write 0 to this bit, reset UART Tx.*/
+            uint32_t rx_rst_core                   :    1;  /*Write 1 then write 0 to this bit, reset UART Rx.*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } clk_conf;
+    uint32_t date;
+    union {
+        struct {
+            uint32_t id                            :    30;  /*This register is used to configure the uart_id.*/
+            uint32_t high_speed                    :    1;  /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
+            uint32_t update                        :    1;  /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
+        };
+        uint32_t val;
+    } id;
+} uart_dev_t;
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/register/soc/xts_aes_reg.h b/components/soc/esp32c2/register/soc/xts_aes_reg.h
new file mode 100644
index 00000000000..6a6e64539c5
--- /dev/null
+++ b/components/soc/esp32c2/register/soc/xts_aes_reg.h
@@ -0,0 +1,135 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** XTS_AES_PLAIN_MEM register
+ *  The memory that stores plaintext
+ */
+#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
+#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
+
+/** XTS_AES_LINESIZE_REG register
+ *  XTS-AES line-size register
+ */
+#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
+/** XTS_AES_LINESIZE : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
+ */
+#define XTS_AES_LINESIZE    (BIT(0))
+#define XTS_AES_LINESIZE_M  (XTS_AES_LINESIZE_V << XTS_AES_LINESIZE_S)
+#define XTS_AES_LINESIZE_V  0x00000001U
+#define XTS_AES_LINESIZE_S  0
+
+/** XTS_AES_DESTINATION_REG register
+ *  XTS-AES destination register
+ */
+#define XTS_AES_DESTINATION_REG (DR_REG_XTS_AES_BASE + 0x44)
+/** XTS_AES_DESTINATION : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the destination. 0: flash(default). 1: reserved.
+ */
+#define XTS_AES_DESTINATION    (BIT(0))
+#define XTS_AES_DESTINATION_M  (XTS_AES_DESTINATION_V << XTS_AES_DESTINATION_S)
+#define XTS_AES_DESTINATION_V  0x00000001U
+#define XTS_AES_DESTINATION_S  0
+
+/** XTS_AES_PHYSICAL_ADDRESS_REG register
+ *  XTS-AES physical address register
+ */
+#define XTS_AES_PHYSICAL_ADDRESS_REG (DR_REG_XTS_AES_BASE + 0x48)
+/** XTS_AES_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0;
+ *  Those bits stores the physical address. If linesize is 16-byte, the physical
+ *  address should be aligned of 16 bytes. If linesize is 32-byte, the physical address
+ *  should be aligned of 32 bytes.
+ */
+#define XTS_AES_PHYSICAL_ADDRESS    0x3FFFFFFFU
+#define XTS_AES_PHYSICAL_ADDRESS_M  (XTS_AES_PHYSICAL_ADDRESS_V << XTS_AES_PHYSICAL_ADDRESS_S)
+#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFFFU
+#define XTS_AES_PHYSICAL_ADDRESS_S  0
+
+/** XTS_AES_TRIGGER_REG register
+ *  XTS-AES trigger register
+ */
+#define XTS_AES_TRIGGER_REG (DR_REG_XTS_AES_BASE + 0x4c)
+/** XTS_AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start manual encryption calculation
+ */
+#define XTS_AES_TRIGGER    (BIT(0))
+#define XTS_AES_TRIGGER_M  (XTS_AES_TRIGGER_V << XTS_AES_TRIGGER_S)
+#define XTS_AES_TRIGGER_V  0x00000001U
+#define XTS_AES_TRIGGER_S  0
+
+/** XTS_AES_RELEASE_REG register
+ *  XTS-AES release register
+ */
+#define XTS_AES_RELEASE_REG (DR_REG_XTS_AES_BASE + 0x50)
+/** XTS_AES_RELEASE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to release the manual encrypted result, after that the result will be
+ *  visible to spi
+ */
+#define XTS_AES_RELEASE    (BIT(0))
+#define XTS_AES_RELEASE_M  (XTS_AES_RELEASE_V << XTS_AES_RELEASE_S)
+#define XTS_AES_RELEASE_V  0x00000001U
+#define XTS_AES_RELEASE_S  0
+
+/** XTS_AES_DESTROY_REG register
+ *  XTS-AES destroy register
+ */
+#define XTS_AES_DESTROY_REG (DR_REG_XTS_AES_BASE + 0x54)
+/** XTS_AES_DESTROY : WT; bitpos: [0]; default: 0;
+ *  Set this bit to destroy XTS-AES result.
+ */
+#define XTS_AES_DESTROY    (BIT(0))
+#define XTS_AES_DESTROY_M  (XTS_AES_DESTROY_V << XTS_AES_DESTROY_S)
+#define XTS_AES_DESTROY_V  0x00000001U
+#define XTS_AES_DESTROY_S  0
+
+/** XTS_AES_STATE_REG register
+ *  XTS-AES status register
+ */
+#define XTS_AES_STATE_REG (DR_REG_XTS_AES_BASE + 0x58)
+/** XTS_AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that
+ *  XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means
+ *  the encrypted result is generated but not visible to mspi. USE means that the
+ *  encrypted result is visible to mspi.
+ */
+#define XTS_AES_STATE    0x00000003U
+#define XTS_AES_STATE_M  (XTS_AES_STATE_V << XTS_AES_STATE_S)
+#define XTS_AES_STATE_V  0x00000003U
+#define XTS_AES_STATE_S  0
+
+/** XTS_AES_DATE_REG register
+ *  XTS-AES version control register
+ */
+#define XTS_AES_DATE_REG (DR_REG_XTS_AES_BASE + 0x5c)
+/** XTS_AES_DATE : R/W; bitpos: [29:0]; default: 538969635;
+ *  Those bits stores the version information of XTS-AES.
+ */
+#define XTS_AES_DATE    0x3FFFFFFFU
+#define XTS_AES_DATE_M  (XTS_AES_DATE_V << XTS_AES_DATE_S)
+#define XTS_AES_DATE_V  0x3FFFFFFFU
+#define XTS_AES_DATE_S  0
+
+/* For backward compatibility with the older register names */
+#define AES_XTS_PLAIN_BASE          XTS_AES_PLAIN_MEM
+#define AES_XTS_SIZE_REG            XTS_AES_LINESIZE_REG
+#define AES_XTS_DESTINATION_REG     XTS_AES_DESTINATION_REG
+#define AES_XTS_PHYSICAL_ADDR_REG   XTS_AES_PHYSICAL_ADDRESS_REG
+#define AES_XTS_TRIGGER_REG         XTS_AES_TRIGGER_REG
+#define AES_XTS_RELEASE_REG         XTS_AES_RELEASE_REG
+#define AES_XTS_DESTROY_REG         XTS_AES_DESTROY_REG
+#define AES_XTS_STATE_REG           XTS_AES_STATE_REG
+#define AES_XTS_DATE_REG            XTS_AES_DATE_REG
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c2/spi_periph.c b/components/soc/esp32c2/spi_periph.c
index 5ae7aed529f..b270a925236 100644
--- a/components/soc/esp32c2/spi_periph.c
+++ b/components/soc/esp32c2/spi_periph.c
@@ -33,7 +33,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = -1,
         .irq = -1,
         .irq_dma = -1,
-        .module = -1,
         .hw = NULL,
         .func = -1,
     }, {
@@ -57,7 +56,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
         .irq = ETS_SPI2_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_SPI2_MODULE,
         .hw = &GPSPI2,
         .func = SPI2_FUNC_NUM,
     }
diff --git a/components/soc/esp32c3/i2s_periph.c b/components/soc/esp32c3/i2s_periph.c
index ff597698b5b..dfb1ba6df82 100644
--- a/components/soc/esp32c3/i2s_periph.c
+++ b/components/soc/esp32c3/i2s_periph.c
@@ -29,6 +29,6 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
         .data_out_sigs[1] = I2SO_SD1_OUT_IDX,
         .data_in_sig  = I2SI_SD_IN_IDX,
 
-        .irq          = ETS_I2S1_INTR_SOURCE,
+        .irq          = ETS_I2S0_INTR_SOURCE,
     }
 };
diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
index 8ef4c16e695..3ad7bc6afdc 100644
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@@ -527,6 +527,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6
@@ -1071,6 +1075,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y
diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_reg.h b/components/soc/esp32c3/include/soc/apb_ctrl_reg.h
deleted file mode 100644
index cb1966505e8..00000000000
--- a/components/soc/esp32c3/include/soc/apb_ctrl_reg.h
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_APB_CTRL_REG_H_
-#define _SOC_APB_CTRL_REG_H_
-
-#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x000)
-/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_RST_TICK_CNT  (BIT(12))
-#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
-#define APB_CTRL_RST_TICK_CNT_V  0x1
-#define APB_CTRL_RST_TICK_CNT_S  12
-/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_CLK_EN  (BIT(11))
-#define APB_CTRL_CLK_EN_M  (BIT(11))
-#define APB_CTRL_CLK_EN_V  0x1
-#define APB_CTRL_CLK_EN_S  11
-/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_CLK_320M_EN  (BIT(10))
-#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
-#define APB_CTRL_CLK_320M_EN_V  0x1
-#define APB_CTRL_CLK_320M_EN_S  10
-/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
-/*description: */
-#define APB_CTRL_PRE_DIV_CNT  0x000003FF
-#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
-#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
-#define APB_CTRL_PRE_DIV_CNT_S  0
-
-#define APB_CTRL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x004)
-/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: */
-#define APB_CTRL_TICK_ENABLE  (BIT(16))
-#define APB_CTRL_TICK_ENABLE_M  (BIT(16))
-#define APB_CTRL_TICK_ENABLE_V  0x1
-#define APB_CTRL_TICK_ENABLE_S  16
-/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
-/*description: */
-#define APB_CTRL_CK8M_TICK_NUM  0x000000FF
-#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
-#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
-#define APB_CTRL_CK8M_TICK_NUM_S  8
-/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
-/*description: */
-#define APB_CTRL_XTAL_TICK_NUM  0x000000FF
-#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
-#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
-#define APB_CTRL_XTAL_TICK_NUM_S  0
-
-#define APB_CTRL_CLK_OUT_EN_REG          (DR_REG_APB_CTRL_BASE + 0x008)
-/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK_XTAL_OEN  (BIT(10))
-#define APB_CTRL_CLK_XTAL_OEN_M  (BIT(10))
-#define APB_CTRL_CLK_XTAL_OEN_V  0x1
-#define APB_CTRL_CLK_XTAL_OEN_S  10
-/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK40X_BB_OEN  (BIT(9))
-#define APB_CTRL_CLK40X_BB_OEN_M  (BIT(9))
-#define APB_CTRL_CLK40X_BB_OEN_V  0x1
-#define APB_CTRL_CLK40X_BB_OEN_S  9
-/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK_DAC_CPU_OEN  (BIT(8))
-#define APB_CTRL_CLK_DAC_CPU_OEN_M  (BIT(8))
-#define APB_CTRL_CLK_DAC_CPU_OEN_V  0x1
-#define APB_CTRL_CLK_DAC_CPU_OEN_S  8
-/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK_ADC_INF_OEN  (BIT(7))
-#define APB_CTRL_CLK_ADC_INF_OEN_M  (BIT(7))
-#define APB_CTRL_CLK_ADC_INF_OEN_V  0x1
-#define APB_CTRL_CLK_ADC_INF_OEN_S  7
-/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK_320M_OEN  (BIT(6))
-#define APB_CTRL_CLK_320M_OEN_M  (BIT(6))
-#define APB_CTRL_CLK_320M_OEN_V  0x1
-#define APB_CTRL_CLK_320M_OEN_S  6
-/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK160_OEN  (BIT(5))
-#define APB_CTRL_CLK160_OEN_M  (BIT(5))
-#define APB_CTRL_CLK160_OEN_V  0x1
-#define APB_CTRL_CLK160_OEN_S  5
-/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK80_OEN  (BIT(4))
-#define APB_CTRL_CLK80_OEN_M  (BIT(4))
-#define APB_CTRL_CLK80_OEN_V  0x1
-#define APB_CTRL_CLK80_OEN_S  4
-/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK_BB_OEN  (BIT(3))
-#define APB_CTRL_CLK_BB_OEN_M  (BIT(3))
-#define APB_CTRL_CLK_BB_OEN_V  0x1
-#define APB_CTRL_CLK_BB_OEN_S  3
-/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK44_OEN  (BIT(2))
-#define APB_CTRL_CLK44_OEN_M  (BIT(2))
-#define APB_CTRL_CLK44_OEN_V  0x1
-#define APB_CTRL_CLK44_OEN_S  2
-/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK22_OEN  (BIT(1))
-#define APB_CTRL_CLK22_OEN_M  (BIT(1))
-#define APB_CTRL_CLK22_OEN_V  0x1
-#define APB_CTRL_CLK22_OEN_S  1
-/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_CLK20_OEN  (BIT(0))
-#define APB_CTRL_CLK20_OEN_M  (BIT(0))
-#define APB_CTRL_CLK20_OEN_V  0x1
-#define APB_CTRL_CLK20_OEN_S  0
-
-#define APB_CTRL_WIFI_BB_CFG_REG          (DR_REG_APB_CTRL_BASE + 0x00C)
-/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define APB_CTRL_WIFI_BB_CFG  0xFFFFFFFF
-#define APB_CTRL_WIFI_BB_CFG_M  ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
-#define APB_CTRL_WIFI_BB_CFG_V  0xFFFFFFFF
-#define APB_CTRL_WIFI_BB_CFG_S  0
-
-#define APB_CTRL_WIFI_BB_CFG_2_REG          (DR_REG_APB_CTRL_BASE + 0x010)
-/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define APB_CTRL_WIFI_BB_CFG_2  0xFFFFFFFF
-#define APB_CTRL_WIFI_BB_CFG_2_M  ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
-#define APB_CTRL_WIFI_BB_CFG_2_V  0xFFFFFFFF
-#define APB_CTRL_WIFI_BB_CFG_2_S  0
-
-#define APB_CTRL_WIFI_CLK_EN_REG          (DR_REG_APB_CTRL_BASE + 0x014)
-/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: */
-#define APB_CTRL_WIFI_CLK_EN  0xFFFFFFFF
-#define APB_CTRL_WIFI_CLK_EN_M  ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
-#define APB_CTRL_WIFI_CLK_EN_V  0xFFFFFFFF
-#define APB_CTRL_WIFI_CLK_EN_S  0
-
-#define APB_CTRL_WIFI_RST_EN_REG          (DR_REG_APB_CTRL_BASE + 0x018)
-/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define APB_CTRL_WIFI_RST  0xFFFFFFFF
-#define APB_CTRL_WIFI_RST_M  ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
-#define APB_CTRL_WIFI_RST_V  0xFFFFFFFF
-#define APB_CTRL_WIFI_RST_S  0
-
-#define APB_CTRL_HOST_INF_SEL_REG          (DR_REG_APB_CTRL_BASE + 0x01C)
-/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define APB_CTRL_PERI_IO_SWAP  0x000000FF
-#define APB_CTRL_PERI_IO_SWAP_M  ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
-#define APB_CTRL_PERI_IO_SWAP_V  0xFF
-#define APB_CTRL_PERI_IO_SWAP_S  0
-
-#define APB_CTRL_EXT_MEM_PMS_LOCK_REG          (DR_REG_APB_CTRL_BASE + 0x020)
-/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_EXT_MEM_PMS_LOCK  (BIT(0))
-#define APB_CTRL_EXT_MEM_PMS_LOCK_M  (BIT(0))
-#define APB_CTRL_EXT_MEM_PMS_LOCK_V  0x1
-#define APB_CTRL_EXT_MEM_PMS_LOCK_S  0
-
-#define APB_CTRL_FLASH_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x028)
-/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE0_ATTR  0x00000003
-#define APB_CTRL_FLASH_ACE0_ATTR_M  ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
-#define APB_CTRL_FLASH_ACE0_ATTR_V  0x3
-#define APB_CTRL_FLASH_ACE0_ATTR_S  0
-
-#define APB_CTRL_FLASH_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x02C)
-/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE1_ATTR  0x00000003
-#define APB_CTRL_FLASH_ACE1_ATTR_M  ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
-#define APB_CTRL_FLASH_ACE1_ATTR_V  0x3
-#define APB_CTRL_FLASH_ACE1_ATTR_S  0
-
-#define APB_CTRL_FLASH_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x030)
-/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE2_ATTR  0x00000003
-#define APB_CTRL_FLASH_ACE2_ATTR_M  ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
-#define APB_CTRL_FLASH_ACE2_ATTR_V  0x3
-#define APB_CTRL_FLASH_ACE2_ATTR_S  0
-
-#define APB_CTRL_FLASH_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x034)
-/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE3_ATTR  0x00000003
-#define APB_CTRL_FLASH_ACE3_ATTR_M  ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
-#define APB_CTRL_FLASH_ACE3_ATTR_V  0x3
-#define APB_CTRL_FLASH_ACE3_ATTR_S  0
-
-#define APB_CTRL_FLASH_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x038)
-/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE0_ADDR_S  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE0_ADDR_S_M  ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
-#define APB_CTRL_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE0_ADDR_S_S  0
-
-#define APB_CTRL_FLASH_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x03C)
-/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE1_ADDR_S  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE1_ADDR_S_M  ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
-#define APB_CTRL_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE1_ADDR_S_S  0
-
-#define APB_CTRL_FLASH_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x040)
-/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE2_ADDR_S  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE2_ADDR_S_M  ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
-#define APB_CTRL_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE2_ADDR_S_S  0
-
-#define APB_CTRL_FLASH_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x044)
-/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE3_ADDR_S  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE3_ADDR_S_M  ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
-#define APB_CTRL_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE3_ADDR_S_S  0
-
-#define APB_CTRL_FLASH_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x048)
-/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE0_SIZE  0x00001FFF
-#define APB_CTRL_FLASH_ACE0_SIZE_M  ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
-#define APB_CTRL_FLASH_ACE0_SIZE_V  0x1FFF
-#define APB_CTRL_FLASH_ACE0_SIZE_S  0
-
-#define APB_CTRL_FLASH_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x04C)
-/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE1_SIZE  0x00001FFF
-#define APB_CTRL_FLASH_ACE1_SIZE_M  ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
-#define APB_CTRL_FLASH_ACE1_SIZE_V  0x1FFF
-#define APB_CTRL_FLASH_ACE1_SIZE_S  0
-
-#define APB_CTRL_FLASH_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x050)
-/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE2_SIZE  0x00001FFF
-#define APB_CTRL_FLASH_ACE2_SIZE_M  ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
-#define APB_CTRL_FLASH_ACE2_SIZE_V  0x1FFF
-#define APB_CTRL_FLASH_ACE2_SIZE_S  0
-
-#define APB_CTRL_FLASH_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x054)
-/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: */
-#define APB_CTRL_FLASH_ACE3_SIZE  0x00001FFF
-#define APB_CTRL_FLASH_ACE3_SIZE_M  ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
-#define APB_CTRL_FLASH_ACE3_SIZE_V  0x1FFF
-#define APB_CTRL_FLASH_ACE3_SIZE_S  0
-
-#define APB_CTRL_SPI_MEM_PMS_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x088)
-/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
-/*description: */
-#define APB_CTRL_SPI_MEM_REJECT_CDE  0x0000001F
-#define APB_CTRL_SPI_MEM_REJECT_CDE_M  ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
-#define APB_CTRL_SPI_MEM_REJECT_CDE_V  0x1F
-#define APB_CTRL_SPI_MEM_REJECT_CDE_S  2
-/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_SPI_MEM_REJECT_CLR  (BIT(1))
-#define APB_CTRL_SPI_MEM_REJECT_CLR_M  (BIT(1))
-#define APB_CTRL_SPI_MEM_REJECT_CLR_V  0x1
-#define APB_CTRL_SPI_MEM_REJECT_CLR_S  1
-/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_SPI_MEM_REJECT_INT  (BIT(0))
-#define APB_CTRL_SPI_MEM_REJECT_INT_M  (BIT(0))
-#define APB_CTRL_SPI_MEM_REJECT_INT_V  0x1
-#define APB_CTRL_SPI_MEM_REJECT_INT_S  0
-
-#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x08C)
-/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define APB_CTRL_SPI_MEM_REJECT_ADDR  0xFFFFFFFF
-#define APB_CTRL_SPI_MEM_REJECT_ADDR_M  ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
-#define APB_CTRL_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
-#define APB_CTRL_SPI_MEM_REJECT_ADDR_S  0
-
-#define APB_CTRL_SDIO_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x090)
-/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define APB_CTRL_SDIO_WIN_ACCESS_EN  (BIT(0))
-#define APB_CTRL_SDIO_WIN_ACCESS_EN_M  (BIT(0))
-#define APB_CTRL_SDIO_WIN_ACCESS_EN_V  0x1
-#define APB_CTRL_SDIO_WIN_ACCESS_EN_S  0
-
-#define APB_CTRL_REDCY_SIG0_REG          (DR_REG_APB_CTRL_BASE + 0x094)
-/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define APB_CTRL_REDCY_ANDOR  (BIT(31))
-#define APB_CTRL_REDCY_ANDOR_M  (BIT(31))
-#define APB_CTRL_REDCY_ANDOR_V  0x1
-#define APB_CTRL_REDCY_ANDOR_S  31
-/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: */
-#define APB_CTRL_REDCY_SIG0  0x7FFFFFFF
-#define APB_CTRL_REDCY_SIG0_M  ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
-#define APB_CTRL_REDCY_SIG0_V  0x7FFFFFFF
-#define APB_CTRL_REDCY_SIG0_S  0
-
-#define APB_CTRL_REDCY_SIG1_REG          (DR_REG_APB_CTRL_BASE + 0x098)
-/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define APB_CTRL_REDCY_NANDOR  (BIT(31))
-#define APB_CTRL_REDCY_NANDOR_M  (BIT(31))
-#define APB_CTRL_REDCY_NANDOR_V  0x1
-#define APB_CTRL_REDCY_NANDOR_S  31
-/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: */
-#define APB_CTRL_REDCY_SIG1  0x7FFFFFFF
-#define APB_CTRL_REDCY_SIG1_M  ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
-#define APB_CTRL_REDCY_SIG1_V  0x7FFFFFFF
-#define APB_CTRL_REDCY_SIG1_S  0
-
-#define APB_CTRL_FRONT_END_MEM_PD_REG          (DR_REG_APB_CTRL_BASE + 0x09C)
-/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_DC_MEM_FORCE_PD  (BIT(5))
-#define APB_CTRL_DC_MEM_FORCE_PD_M  (BIT(5))
-#define APB_CTRL_DC_MEM_FORCE_PD_V  0x1
-#define APB_CTRL_DC_MEM_FORCE_PD_S  5
-/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_DC_MEM_FORCE_PU  (BIT(4))
-#define APB_CTRL_DC_MEM_FORCE_PU_M  (BIT(4))
-#define APB_CTRL_DC_MEM_FORCE_PU_V  0x1
-#define APB_CTRL_DC_MEM_FORCE_PU_S  4
-/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_PBUS_MEM_FORCE_PD  (BIT(3))
-#define APB_CTRL_PBUS_MEM_FORCE_PD_M  (BIT(3))
-#define APB_CTRL_PBUS_MEM_FORCE_PD_V  0x1
-#define APB_CTRL_PBUS_MEM_FORCE_PD_S  3
-/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_PBUS_MEM_FORCE_PU  (BIT(2))
-#define APB_CTRL_PBUS_MEM_FORCE_PU_M  (BIT(2))
-#define APB_CTRL_PBUS_MEM_FORCE_PU_V  0x1
-#define APB_CTRL_PBUS_MEM_FORCE_PU_S  2
-/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_AGC_MEM_FORCE_PD  (BIT(1))
-#define APB_CTRL_AGC_MEM_FORCE_PD_M  (BIT(1))
-#define APB_CTRL_AGC_MEM_FORCE_PD_V  0x1
-#define APB_CTRL_AGC_MEM_FORCE_PD_S  1
-/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define APB_CTRL_AGC_MEM_FORCE_PU  (BIT(0))
-#define APB_CTRL_AGC_MEM_FORCE_PU_M  (BIT(0))
-#define APB_CTRL_AGC_MEM_FORCE_PU_V  0x1
-#define APB_CTRL_AGC_MEM_FORCE_PU_S  0
-
-#define APB_CTRL_RETENTION_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x0A0)
-/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_NOBYPASS_CPU_ISO_RST  (BIT(27))
-#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
-#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V  0x1
-#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S  27
-/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
-/*description: */
-#define APB_CTRL_RETENTION_LINK_ADDR  0x07FFFFFF
-#define APB_CTRL_RETENTION_LINK_ADDR_M  ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S))
-#define APB_CTRL_RETENTION_LINK_ADDR_V  0x7FFFFFF
-#define APB_CTRL_RETENTION_LINK_ADDR_S  0
-
-#define APB_CTRL_CLKGATE_FORCE_ON_REG          (DR_REG_APB_CTRL_BASE + 0x0A4)
-/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
-/*description: */
-#define APB_CTRL_SRAM_CLKGATE_FORCE_ON  0x0000000F
-#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M  ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
-#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V  0xF
-#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S  2
-/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define APB_CTRL_ROM_CLKGATE_FORCE_ON  0x00000003
-#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M  ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
-#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V  0x3
-#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S  0
-
-#define APB_CTRL_MEM_POWER_DOWN_REG          (DR_REG_APB_CTRL_BASE + 0x0A8)
-/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
-/*description: */
-#define APB_CTRL_SRAM_POWER_DOWN  0x0000000F
-#define APB_CTRL_SRAM_POWER_DOWN_M  ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
-#define APB_CTRL_SRAM_POWER_DOWN_V  0xF
-#define APB_CTRL_SRAM_POWER_DOWN_S  2
-/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define APB_CTRL_ROM_POWER_DOWN  0x00000003
-#define APB_CTRL_ROM_POWER_DOWN_M  ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
-#define APB_CTRL_ROM_POWER_DOWN_V  0x3
-#define APB_CTRL_ROM_POWER_DOWN_S  0
-
-#define APB_CTRL_MEM_POWER_UP_REG          (DR_REG_APB_CTRL_BASE + 0x0AC)
-/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
-/*description: */
-#define APB_CTRL_SRAM_POWER_UP  0x0000000F
-#define APB_CTRL_SRAM_POWER_UP_M  ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
-#define APB_CTRL_SRAM_POWER_UP_V  0xF
-#define APB_CTRL_SRAM_POWER_UP_S  2
-/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define APB_CTRL_ROM_POWER_UP  0x00000003
-#define APB_CTRL_ROM_POWER_UP_M  ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
-#define APB_CTRL_ROM_POWER_UP_V  0x3
-#define APB_CTRL_ROM_POWER_UP_S  0
-
-#define APB_CTRL_RND_DATA_REG          (DR_REG_APB_CTRL_BASE + 0x0B0)
-/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define APB_CTRL_RND_DATA  0xFFFFFFFF
-#define APB_CTRL_RND_DATA_M  ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
-#define APB_CTRL_RND_DATA_V  0xFFFFFFFF
-#define APB_CTRL_RND_DATA_S  0
-
-#define APB_CTRL_PERI_BACKUP_CONFIG_REG          (DR_REG_APB_CTRL_BASE + 0x0B4)
-/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_ENA  (BIT(31))
-#define APB_CTRL_PERI_BACKUP_ENA_M  (BIT(31))
-#define APB_CTRL_PERI_BACKUP_ENA_V  0x1
-#define APB_CTRL_PERI_BACKUP_ENA_S  31
-/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_TO_MEM  (BIT(30))
-#define APB_CTRL_PERI_BACKUP_TO_MEM_M  (BIT(30))
-#define APB_CTRL_PERI_BACKUP_TO_MEM_V  0x1
-#define APB_CTRL_PERI_BACKUP_TO_MEM_S  30
-/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_START  (BIT(29))
-#define APB_CTRL_PERI_BACKUP_START_M  (BIT(29))
-#define APB_CTRL_PERI_BACKUP_START_V  0x1
-#define APB_CTRL_PERI_BACKUP_START_S  29
-/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_SIZE  0x000003FF
-#define APB_CTRL_PERI_BACKUP_SIZE_M  ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
-#define APB_CTRL_PERI_BACKUP_SIZE_V  0x3FF
-#define APB_CTRL_PERI_BACKUP_SIZE_S  19
-/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_TOUT_THRES  0x000003FF
-#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M  ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
-#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V  0x3FF
-#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S  9
-/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_BURST_LIMIT  0x0000001F
-#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M  ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
-#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V  0x1F
-#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S  4
-/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_FLOW_ERR  0x00000003
-#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M  ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
-#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V  0x3
-#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S  1
-
-#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x0B8)
-/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: */
-#define APB_CTRL_BACKUP_APB_START_ADDR  0xFFFFFFFF
-#define APB_CTRL_BACKUP_APB_START_ADDR_M  ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S))
-#define APB_CTRL_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
-#define APB_CTRL_BACKUP_APB_START_ADDR_S  0
-
-#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x0BC)
-/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: */
-#define APB_CTRL_BACKUP_MEM_START_ADDR  0xFFFFFFFF
-#define APB_CTRL_BACKUP_MEM_START_ADDR_M  ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S))
-#define APB_CTRL_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
-#define APB_CTRL_BACKUP_MEM_START_ADDR_S  0
-
-#define APB_CTRL_PERI_BACKUP_INT_RAW_REG          (DR_REG_APB_CTRL_BASE + 0x0C0)
-/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW  (BIT(1))
-#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
-#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V  0x1
-#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S  1
-/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW  (BIT(0))
-#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
-#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V  0x1
-#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S  0
-
-#define APB_CTRL_PERI_BACKUP_INT_ST_REG          (DR_REG_APB_CTRL_BASE + 0x0C4)
-/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_ERR_INT_ST  (BIT(1))
-#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
-#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V  0x1
-#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S  1
-/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_DONE_INT_ST  (BIT(0))
-#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
-#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V  0x1
-#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S  0
-
-#define APB_CTRL_PERI_BACKUP_INT_ENA_REG          (DR_REG_APB_CTRL_BASE + 0x0C8)
-/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA  (BIT(1))
-#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
-#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V  0x1
-#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S  1
-/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA  (BIT(0))
-#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
-#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V  0x1
-#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S  0
-
-#define APB_CTRL_PERI_BACKUP_INT_CLR_REG          (DR_REG_APB_CTRL_BASE + 0x0D0)
-/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR  (BIT(1))
-#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
-#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V  0x1
-#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S  1
-/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR  (BIT(0))
-#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
-#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V  0x1
-#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S  0
-
-#define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x3FC)
-/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
-/*description: Version control*/
-#define APB_CTRL_DATE  0xFFFFFFFF
-#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
-#define APB_CTRL_DATE_V  0xFFFFFFFF
-#define APB_CTRL_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_APB_CTRL_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/apb_saradc_reg.h b/components/soc/esp32c3/include/soc/apb_saradc_reg.h
deleted file mode 100644
index 69785ca84da..00000000000
--- a/components/soc/esp32c3/include/soc/apb_saradc_reg.h
+++ /dev/null
@@ -1,631 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_APB_SARADC_REG_H_
-#define _SOC_APB_SARADC_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x000)
-/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
-/*description: wait arbit signal stable after sar_done*/
-#define APB_SARADC_WAIT_ARB_CYCLE  0x00000003
-#define APB_SARADC_WAIT_ARB_CYCLE_M  ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
-#define APB_SARADC_WAIT_ARB_CYCLE_V  0x3
-#define APB_SARADC_WAIT_ARB_CYCLE_S  30
-/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
-/*description: force option to xpd sar blocks*/
-#define APB_SARADC_XPD_SAR_FORCE  0x00000003
-#define APB_SARADC_XPD_SAR_FORCE_M  ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
-#define APB_SARADC_XPD_SAR_FORCE_V  0x3
-#define APB_SARADC_XPD_SAR_FORCE_S  27
-/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
-#define APB_SARADC_SAR_PATT_P_CLEAR  (BIT(23))
-#define APB_SARADC_SAR_PATT_P_CLEAR_M  (BIT(23))
-#define APB_SARADC_SAR_PATT_P_CLEAR_V  0x1
-#define APB_SARADC_SAR_PATT_P_CLEAR_S  23
-/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */
-/*description: 0 ~ 15 means length 1 ~ 16*/
-#define APB_SARADC_SAR_PATT_LEN  0x00000007
-#define APB_SARADC_SAR_PATT_LEN_M  ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S))
-#define APB_SARADC_SAR_PATT_LEN_V  0x7
-#define APB_SARADC_SAR_PATT_LEN_S  15
-/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
-/*description: SAR clock divider*/
-#define APB_SARADC_SAR_CLK_DIV  0x000000FF
-#define APB_SARADC_SAR_CLK_DIV_M  ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
-#define APB_SARADC_SAR_CLK_DIV_V  0xFF
-#define APB_SARADC_SAR_CLK_DIV_S  7
-/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define APB_SARADC_SAR_CLK_GATED  (BIT(6))
-#define APB_SARADC_SAR_CLK_GATED_M  (BIT(6))
-#define APB_SARADC_SAR_CLK_GATED_V  0x1
-#define APB_SARADC_SAR_CLK_GATED_S  6
-/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define APB_SARADC_START  (BIT(1))
-#define APB_SARADC_START_M  (BIT(1))
-#define APB_SARADC_START_V  0x1
-#define APB_SARADC_START_S  1
-/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define APB_SARADC_START_FORCE  (BIT(0))
-#define APB_SARADC_START_FORCE_M  (BIT(0))
-#define APB_SARADC_START_FORCE_V  0x1
-#define APB_SARADC_START_FORCE_S  0
-
-#define APB_SARADC_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x004)
-/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: to enable saradc timer trigger*/
-#define APB_SARADC_TIMER_EN  (BIT(24))
-#define APB_SARADC_TIMER_EN_M  (BIT(24))
-#define APB_SARADC_TIMER_EN_V  0x1
-#define APB_SARADC_TIMER_EN_S  24
-/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
-/*description: to set saradc timer target*/
-#define APB_SARADC_TIMER_TARGET  0x00000FFF
-#define APB_SARADC_TIMER_TARGET_M  ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
-#define APB_SARADC_TIMER_TARGET_V  0xFFF
-#define APB_SARADC_TIMER_TARGET_S  12
-/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
-#define APB_SARADC_SAR2_INV  (BIT(10))
-#define APB_SARADC_SAR2_INV_M  (BIT(10))
-#define APB_SARADC_SAR2_INV_V  0x1
-#define APB_SARADC_SAR2_INV_S  10
-/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
-#define APB_SARADC_SAR1_INV  (BIT(9))
-#define APB_SARADC_SAR1_INV_M  (BIT(9))
-#define APB_SARADC_SAR1_INV_V  0x1
-#define APB_SARADC_SAR1_INV_S  9
-/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
-/*description: max conversion number*/
-#define APB_SARADC_MAX_MEAS_NUM  0x000000FF
-#define APB_SARADC_MAX_MEAS_NUM_M  ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
-#define APB_SARADC_MAX_MEAS_NUM_V  0xFF
-#define APB_SARADC_MAX_MEAS_NUM_S  1
-/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define APB_SARADC_MEAS_NUM_LIMIT  (BIT(0))
-#define APB_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
-#define APB_SARADC_MEAS_NUM_LIMIT_V  0x1
-#define APB_SARADC_MEAS_NUM_LIMIT_S  0
-
-#define APB_SARADC_FILTER_CTRL1_REG          (DR_REG_APB_SARADC_BASE + 0x008)
-/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
-/*description: */
-#define APB_SARADC_FILTER_FACTOR0  0x00000007
-#define APB_SARADC_FILTER_FACTOR0_M  ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
-#define APB_SARADC_FILTER_FACTOR0_V  0x7
-#define APB_SARADC_FILTER_FACTOR0_S  29
-/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
-/*description: */
-#define APB_SARADC_FILTER_FACTOR1  0x00000007
-#define APB_SARADC_FILTER_FACTOR1_M  ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
-#define APB_SARADC_FILTER_FACTOR1_V  0x7
-#define APB_SARADC_FILTER_FACTOR1_S  26
-
-#define APB_SARADC_FSM_WAIT_REG          (DR_REG_APB_SARADC_BASE + 0x00C)
-/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
-/*description: */
-#define APB_SARADC_STANDBY_WAIT  0x000000FF
-#define APB_SARADC_STANDBY_WAIT_M  ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
-#define APB_SARADC_STANDBY_WAIT_V  0xFF
-#define APB_SARADC_STANDBY_WAIT_S  16
-/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
-/*description: */
-#define APB_SARADC_RSTB_WAIT  0x000000FF
-#define APB_SARADC_RSTB_WAIT_M  ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
-#define APB_SARADC_RSTB_WAIT_V  0xFF
-#define APB_SARADC_RSTB_WAIT_S  8
-/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
-/*description: */
-#define APB_SARADC_XPD_WAIT  0x000000FF
-#define APB_SARADC_XPD_WAIT_M  ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
-#define APB_SARADC_XPD_WAIT_V  0xFF
-#define APB_SARADC_XPD_WAIT_S  0
-
-#define APB_SARADC_SAR1_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x010)
-/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: */
-#define APB_SARADC_SAR1_STATUS  0xFFFFFFFF
-#define APB_SARADC_SAR1_STATUS_M  ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
-#define APB_SARADC_SAR1_STATUS_V  0xFFFFFFFF
-#define APB_SARADC_SAR1_STATUS_S  0
-
-#define APB_SARADC_SAR2_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x014)
-/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: */
-#define APB_SARADC_SAR2_STATUS  0xFFFFFFFF
-#define APB_SARADC_SAR2_STATUS_M  ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
-#define APB_SARADC_SAR2_STATUS_V  0xFFFFFFFF
-#define APB_SARADC_SAR2_STATUS_S  0
-
-#define APB_SARADC_SAR_PATT_TAB1_REG          (DR_REG_APB_SARADC_BASE + 0x018)
-/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
-#define APB_SARADC_SAR_PATT_TAB1  0x00FFFFFF
-#define APB_SARADC_SAR_PATT_TAB1_M  ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S))
-#define APB_SARADC_SAR_PATT_TAB1_V  0xFFFFFF
-#define APB_SARADC_SAR_PATT_TAB1_S  0
-
-#define APB_SARADC_SAR_PATT_TAB2_REG          (DR_REG_APB_SARADC_BASE + 0x01C)
-/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
-#define APB_SARADC_SAR_PATT_TAB2  0x00FFFFFF
-#define APB_SARADC_SAR_PATT_TAB2_M  ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S))
-#define APB_SARADC_SAR_PATT_TAB2_V  0xFFFFFF
-#define APB_SARADC_SAR_PATT_TAB2_S  0
-
-#define APB_SARADC_ONETIME_SAMPLE_REG          (DR_REG_APB_SARADC_BASE + 0x020)
-/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC1_ONETIME_SAMPLE  (BIT(31))
-#define APB_SARADC1_ONETIME_SAMPLE_M  (BIT(31))
-#define APB_SARADC1_ONETIME_SAMPLE_V  0x1
-#define APB_SARADC1_ONETIME_SAMPLE_S  31
-/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC2_ONETIME_SAMPLE  (BIT(30))
-#define APB_SARADC2_ONETIME_SAMPLE_M  (BIT(30))
-#define APB_SARADC2_ONETIME_SAMPLE_V  0x1
-#define APB_SARADC2_ONETIME_SAMPLE_S  30
-/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ONETIME_START  (BIT(29))
-#define APB_SARADC_ONETIME_START_M  (BIT(29))
-#define APB_SARADC_ONETIME_START_V  0x1
-#define APB_SARADC_ONETIME_START_S  29
-/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */
-/*description: */
-#define APB_SARADC_ONETIME_CHANNEL  0x0000000F
-#define APB_SARADC_ONETIME_CHANNEL_M  ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S))
-#define APB_SARADC_ONETIME_CHANNEL_V  0xF
-#define APB_SARADC_ONETIME_CHANNEL_S  25
-/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
-/*description: */
-#define APB_SARADC_ONETIME_ATTEN  0x00000003
-#define APB_SARADC_ONETIME_ATTEN_M  ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S))
-#define APB_SARADC_ONETIME_ATTEN_V  0x3
-#define APB_SARADC_ONETIME_ATTEN_S  23
-
-#define APB_SARADC_APB_ADC_ARB_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x024)
-/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: adc2 arbiter uses fixed priority*/
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY  (BIT(12))
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (BIT(12))
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x1
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
-/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
-/*description: Set adc2 arbiter wifi priority*/
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY  0x00000003
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x3
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
-/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
-/*description: Set adc2 arbiter rtc priority*/
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY  0x00000003
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x3
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
-/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Set adc2 arbiterapb priority*/
-#define APB_SARADC_ADC_ARB_APB_PRIORITY  0x00000003
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x3
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
-/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: adc2 arbiter force grant*/
-#define APB_SARADC_ADC_ARB_GRANT_FORCE  (BIT(5))
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (BIT(5))
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x1
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
-/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: adc2 arbiter force to enable wifi controller*/
-#define APB_SARADC_ADC_ARB_WIFI_FORCE  (BIT(4))
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (BIT(4))
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x1
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
-/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: adc2 arbiter force to enable rtc controller*/
-#define APB_SARADC_ADC_ARB_RTC_FORCE  (BIT(3))
-#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (BIT(3))
-#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x1
-#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
-/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: adc2 arbiter force to enableapb controller*/
-#define APB_SARADC_ADC_ARB_APB_FORCE  (BIT(2))
-#define APB_SARADC_ADC_ARB_APB_FORCE_M  (BIT(2))
-#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x1
-#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
-
-#define APB_SARADC_FILTER_CTRL0_REG          (DR_REG_APB_SARADC_BASE + 0x028)
-/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: enable apb_adc1_filter*/
-#define APB_SARADC_FILTER_RESET  (BIT(31))
-#define APB_SARADC_FILTER_RESET_M  (BIT(31))
-#define APB_SARADC_FILTER_RESET_V  0x1
-#define APB_SARADC_FILTER_RESET_S  31
-/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */
-/*description: apb_adc1_filter_factor*/
-#define APB_SARADC_FILTER_CHANNEL0  0x0000000F
-#define APB_SARADC_FILTER_CHANNEL0_M  ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
-#define APB_SARADC_FILTER_CHANNEL0_V  0xF
-#define APB_SARADC_FILTER_CHANNEL0_S  22
-/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */
-/*description: */
-#define APB_SARADC_FILTER_CHANNEL1  0x0000000F
-#define APB_SARADC_FILTER_CHANNEL1_M  ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
-#define APB_SARADC_FILTER_CHANNEL1_V  0xF
-#define APB_SARADC_FILTER_CHANNEL1_S  18
-
-#define APB_SARADC_1_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x02C)
-/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
-/*description: */
-#define APB_SARADC_ADC1_DATA  0x0001FFFF
-#define APB_SARADC_ADC1_DATA_M  ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
-#define APB_SARADC_ADC1_DATA_V  0x1FFFF
-#define APB_SARADC_ADC1_DATA_S  0
-
-#define APB_SARADC_2_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x030)
-/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
-/*description: */
-#define APB_SARADC_ADC2_DATA  0x0001FFFF
-#define APB_SARADC_ADC2_DATA_M  ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
-#define APB_SARADC_ADC2_DATA_V  0x1FFFF
-#define APB_SARADC_ADC2_DATA_S  0
-
-#define APB_SARADC_THRES0_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x034)
-/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
-/*description: saradc1's thres0 monitor thres*/
-#define APB_SARADC_THRES0_LOW  0x00001FFF
-#define APB_SARADC_THRES0_LOW_M  ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
-#define APB_SARADC_THRES0_LOW_V  0x1FFF
-#define APB_SARADC_THRES0_LOW_S  18
-/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
-/*description: saradc1's thres0 monitor thres*/
-#define APB_SARADC_THRES0_HIGH  0x00001FFF
-#define APB_SARADC_THRES0_HIGH_M  ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
-#define APB_SARADC_THRES0_HIGH_V  0x1FFF
-#define APB_SARADC_THRES0_HIGH_S  5
-/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
-/*description: */
-#define APB_SARADC_THRES0_CHANNEL  0x0000000F
-#define APB_SARADC_THRES0_CHANNEL_M  ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
-#define APB_SARADC_THRES0_CHANNEL_V  0xF
-#define APB_SARADC_THRES0_CHANNEL_S  0
-
-#define APB_SARADC_THRES1_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x038)
-/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
-/*description: saradc1's thres0 monitor thres*/
-#define APB_SARADC_THRES1_LOW  0x00001FFF
-#define APB_SARADC_THRES1_LOW_M  ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
-#define APB_SARADC_THRES1_LOW_V  0x1FFF
-#define APB_SARADC_THRES1_LOW_S  18
-/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
-/*description: saradc1's thres0 monitor thres*/
-#define APB_SARADC_THRES1_HIGH  0x00001FFF
-#define APB_SARADC_THRES1_HIGH_M  ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
-#define APB_SARADC_THRES1_HIGH_V  0x1FFF
-#define APB_SARADC_THRES1_HIGH_S  5
-/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
-/*description: */
-#define APB_SARADC_THRES1_CHANNEL  0x0000000F
-#define APB_SARADC_THRES1_CHANNEL_M  ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
-#define APB_SARADC_THRES1_CHANNEL_V  0xF
-#define APB_SARADC_THRES1_CHANNEL_S  0
-
-#define APB_SARADC_THRES_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x03C)
-/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_EN  (BIT(31))
-#define APB_SARADC_THRES0_EN_M  (BIT(31))
-#define APB_SARADC_THRES0_EN_V  0x1
-#define APB_SARADC_THRES0_EN_S  31
-/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_EN  (BIT(30))
-#define APB_SARADC_THRES1_EN_M  (BIT(30))
-#define APB_SARADC_THRES1_EN_V  0x1
-#define APB_SARADC_THRES1_EN_S  30
-/*description: */
-#define APB_SARADC_THRES_ALL_EN  (BIT(27))
-#define APB_SARADC_THRES_ALL_EN_M  (BIT(27))
-#define APB_SARADC_THRES_ALL_EN_V  0x1
-#define APB_SARADC_THRES_ALL_EN_S  27
-
-#define APB_SARADC_INT_ENA_REG          (DR_REG_APB_SARADC_BASE + 0x040)
-/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ADC1_DONE_INT_ENA  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_ENA_M  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_ENA_V  0x1
-#define APB_SARADC_ADC1_DONE_INT_ENA_S  31
-/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ADC2_DONE_INT_ENA  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_ENA_M  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_ENA_V  0x1
-#define APB_SARADC_ADC2_DONE_INT_ENA_S  30
-/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_HIGH_INT_ENA  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_ENA_M  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_ENA_V  0x1
-#define APB_SARADC_THRES0_HIGH_INT_ENA_S  29
-/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_HIGH_INT_ENA  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_ENA_M  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_ENA_V  0x1
-#define APB_SARADC_THRES1_HIGH_INT_ENA_S  28
-/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_LOW_INT_ENA  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_ENA_M  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_ENA_V  0x1
-#define APB_SARADC_THRES0_LOW_INT_ENA_S  27
-/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_LOW_INT_ENA  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_ENA_M  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_ENA_V  0x1
-#define APB_SARADC_THRES1_LOW_INT_ENA_S  26
-
-#define APB_SARADC_INT_RAW_REG          (DR_REG_APB_SARADC_BASE + 0x044)
-/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ADC1_DONE_INT_RAW  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_RAW_M  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_RAW_V  0x1
-#define APB_SARADC_ADC1_DONE_INT_RAW_S  31
-/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ADC2_DONE_INT_RAW  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_RAW_M  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_RAW_V  0x1
-#define APB_SARADC_ADC2_DONE_INT_RAW_S  30
-/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_HIGH_INT_RAW  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_RAW_M  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_RAW_V  0x1
-#define APB_SARADC_THRES0_HIGH_INT_RAW_S  29
-/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_HIGH_INT_RAW  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_RAW_M  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_RAW_V  0x1
-#define APB_SARADC_THRES1_HIGH_INT_RAW_S  28
-/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_LOW_INT_RAW  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_RAW_M  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_RAW_V  0x1
-#define APB_SARADC_THRES0_LOW_INT_RAW_S  27
-/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_LOW_INT_RAW  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_RAW_M  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_RAW_V  0x1
-#define APB_SARADC_THRES1_LOW_INT_RAW_S  26
-
-#define APB_SARADC_INT_ST_REG          (DR_REG_APB_SARADC_BASE + 0x048)
-/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ADC1_DONE_INT_ST  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_ST_M  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_ST_V  0x1
-#define APB_SARADC_ADC1_DONE_INT_ST_S  31
-/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ADC2_DONE_INT_ST  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_ST_M  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_ST_V  0x1
-#define APB_SARADC_ADC2_DONE_INT_ST_S  30
-/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_HIGH_INT_ST  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_ST_M  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_ST_V  0x1
-#define APB_SARADC_THRES0_HIGH_INT_ST_S  29
-/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_HIGH_INT_ST  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_ST_M  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_ST_V  0x1
-#define APB_SARADC_THRES1_HIGH_INT_ST_S  28
-/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_LOW_INT_ST  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_ST_M  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_ST_V  0x1
-#define APB_SARADC_THRES0_LOW_INT_ST_S  27
-/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_LOW_INT_ST  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_ST_M  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_ST_V  0x1
-#define APB_SARADC_THRES1_LOW_INT_ST_S  26
-
-#define APB_SARADC_INT_CLR_REG          (DR_REG_APB_SARADC_BASE + 0x04C)
-/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ADC1_DONE_INT_CLR  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_CLR_M  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_CLR_V  0x1
-#define APB_SARADC_ADC1_DONE_INT_CLR_S  31
-/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_ADC2_DONE_INT_CLR  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_CLR_M  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_CLR_V  0x1
-#define APB_SARADC_ADC2_DONE_INT_CLR_S  30
-/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_HIGH_INT_CLR  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_CLR_M  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_CLR_V  0x1
-#define APB_SARADC_THRES0_HIGH_INT_CLR_S  29
-/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_HIGH_INT_CLR  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_CLR_M  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_CLR_V  0x1
-#define APB_SARADC_THRES1_HIGH_INT_CLR_S  28
-/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES0_LOW_INT_CLR  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_CLR_M  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_CLR_V  0x1
-#define APB_SARADC_THRES0_LOW_INT_CLR_S  27
-/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_THRES1_LOW_INT_CLR  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_CLR_M  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_CLR_V  0x1
-#define APB_SARADC_THRES1_LOW_INT_CLR_S  26
-
-#define APB_SARADC_DMA_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x050)
-/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: enable apb_adc use spi_dma*/
-#define APB_SARADC_APB_ADC_TRANS  (BIT(31))
-#define APB_SARADC_APB_ADC_TRANS_M  (BIT(31))
-#define APB_SARADC_APB_ADC_TRANS_V  0x1
-#define APB_SARADC_APB_ADC_TRANS_S  31
-/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: reset_apb_adc_state*/
-#define APB_SARADC_APB_ADC_RESET_FSM  (BIT(30))
-#define APB_SARADC_APB_ADC_RESET_FSM_M  (BIT(30))
-#define APB_SARADC_APB_ADC_RESET_FSM_V  0x1
-#define APB_SARADC_APB_ADC_RESET_FSM_S  30
-/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
-/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
-#define APB_SARADC_APB_ADC_EOF_NUM  0x0000FFFF
-#define APB_SARADC_APB_ADC_EOF_NUM_M  ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
-#define APB_SARADC_APB_ADC_EOF_NUM_V  0xFFFF
-#define APB_SARADC_APB_ADC_EOF_NUM_S  0
-
-#define APB_SARADC_APB_ADC_CLKM_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x054)
-/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
-/*description: Set this bit to enable clk_apll*/
-#define APB_SARADC_CLK_SEL  0x00000003
-#define APB_SARADC_CLK_SEL_M  ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
-#define APB_SARADC_CLK_SEL_V  0x3
-#define APB_SARADC_CLK_SEL_S  21
-/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: */
-#define APB_SARADC_CLK_EN  (BIT(20))
-#define APB_SARADC_CLK_EN_M  (BIT(20))
-#define APB_SARADC_CLK_EN_V  0x1
-#define APB_SARADC_CLK_EN_S  20
-/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
-/*description: Fractional clock divider denominator value*/
-#define APB_SARADC_CLKM_DIV_A  0x0000003F
-#define APB_SARADC_CLKM_DIV_A_M  ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
-#define APB_SARADC_CLKM_DIV_A_V  0x3F
-#define APB_SARADC_CLKM_DIV_A_S  14
-/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
-/*description: Fractional clock divider numerator value*/
-#define APB_SARADC_CLKM_DIV_B  0x0000003F
-#define APB_SARADC_CLKM_DIV_B_M  ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
-#define APB_SARADC_CLKM_DIV_B_V  0x3F
-#define APB_SARADC_CLKM_DIV_B_S  8
-/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
-/*description: Integral I2S clock divider value*/
-#define APB_SARADC_CLKM_DIV_NUM  0x000000FF
-#define APB_SARADC_CLKM_DIV_NUM_M  ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
-#define APB_SARADC_CLKM_DIV_NUM_V  0xFF
-#define APB_SARADC_CLKM_DIV_NUM_S  0
-
-#define APB_SARADC_APB_TSENS_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x058)
-/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_TSENS_PU  (BIT(22))
-#define APB_SARADC_TSENS_PU_M  (BIT(22))
-#define APB_SARADC_TSENS_PU_V  0x1
-#define APB_SARADC_TSENS_PU_S  22
-/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */
-/*description: */
-#define APB_SARADC_TSENS_CLK_DIV  0x000000FF
-#define APB_SARADC_TSENS_CLK_DIV_M  ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S))
-#define APB_SARADC_TSENS_CLK_DIV_V  0xFF
-#define APB_SARADC_TSENS_CLK_DIV_S  14
-/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_TSENS_IN_INV  (BIT(13))
-#define APB_SARADC_TSENS_IN_INV_M  (BIT(13))
-#define APB_SARADC_TSENS_IN_INV_V  0x1
-#define APB_SARADC_TSENS_IN_INV_S  13
-/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define APB_SARADC_TSENS_OUT  0x000000FF
-#define APB_SARADC_TSENS_OUT_M  ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S))
-#define APB_SARADC_TSENS_OUT_V  0xFF
-#define APB_SARADC_TSENS_OUT_S  0
-
-#define APB_SARADC_APB_TSENS_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x05C)
-/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define APB_SARADC_TSENS_CLK_SEL  (BIT(15))
-#define APB_SARADC_TSENS_CLK_SEL_M  (BIT(15))
-#define APB_SARADC_TSENS_CLK_SEL_V  0x1
-#define APB_SARADC_TSENS_CLK_SEL_S  15
-/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: */
-#define APB_SARADC_TSENS_CLK_INV  (BIT(14))
-#define APB_SARADC_TSENS_CLK_INV_M  (BIT(14))
-#define APB_SARADC_TSENS_CLK_INV_V  0x1
-#define APB_SARADC_TSENS_CLK_INV_S  14
-/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: */
-#define APB_SARADC_TSENS_XPD_FORCE  0x00000003
-#define APB_SARADC_TSENS_XPD_FORCE_M  ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S))
-#define APB_SARADC_TSENS_XPD_FORCE_V  0x3
-#define APB_SARADC_TSENS_XPD_FORCE_S  12
-/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
-/*description: */
-#define APB_SARADC_TSENS_XPD_WAIT  0x00000FFF
-#define APB_SARADC_TSENS_XPD_WAIT_M  ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S))
-#define APB_SARADC_TSENS_XPD_WAIT_V  0xFFF
-#define APB_SARADC_TSENS_XPD_WAIT_S  0
-
-#define APB_SARADC_CALI_REG          (DR_REG_APB_SARADC_BASE + 0x060)
-/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */
-/*description: */
-#define APB_SARADC_CALI_CFG  0x0001FFFF
-#define APB_SARADC_CALI_CFG_M  ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S))
-#define APB_SARADC_CALI_CFG_V  0x1FFFF
-#define APB_SARADC_CALI_CFG_S  0
-
-#define APB_SARADC_APB_CTRL_DATE_REG          (DR_REG_APB_SARADC_BASE + 0x3fc)
-/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */
-/*description: */
-#define APB_SARADC_DATE  0xFFFFFFFF
-#define APB_SARADC_DATE_M  ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S))
-#define APB_SARADC_DATE_V  0xFFFFFFFF
-#define APB_SARADC_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_APB_SARADC_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/assist_debug_reg.h b/components/soc/esp32c3/include/soc/assist_debug_reg.h
deleted file mode 100644
index 2b13d1f5f41..00000000000
--- a/components/soc/esp32c3/include/soc/assist_debug_reg.h
+++ /dev/null
@@ -1,691 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_ASSIST_DEBUG_REG_H_
-#define _SOC_ASSIST_DEBUG_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x000)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
-
-#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x004)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
-
-#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x008)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
-
-#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x00C)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x010)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x014)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x018)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x01C)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x020)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x024)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x028)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x02C)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x030)
-/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_PC  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M  ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x034)
-/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_AREA_SP  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M  ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
-
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x038)
-/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_MIN  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x03C)
-/* ASSIST_DEBUG_CORE_0_SP_MAX : RW ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_MAX  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x040)
-/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_SP_PC  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_EN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x044)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable CPU Pdebug function  if enable  CPU will update PdebugPC*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x1
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
-/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable recording function  if enable  assist_debug will update
- PdebugPC  so you can read it*/
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x1
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x048)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x04C)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
-
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x050)
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0  (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0  0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
-
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x054)
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1  (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1  0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x058)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0  0x0000000F
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0xF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  24
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0  0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x05C)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x060)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1  0x0000000F
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0xF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  24
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1  0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x064)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
-
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x068)
-/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0  0x000FFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0xFFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
-
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x06C)
-/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1  0x000FFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0xFFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
-
-#define ASSIST_DEBUG_LOG_SETTING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x070)
-/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE  (BIT(7))
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M  (BIT(7))
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V  0x1
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S  7
-/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MODE  0x0000000F
-#define ASSIST_DEBUG_LOG_MODE_M  ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
-#define ASSIST_DEBUG_LOG_MODE_V  0xF
-#define ASSIST_DEBUG_LOG_MODE_S  3
-/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_ENA  0x00000007
-#define ASSIST_DEBUG_LOG_ENA_M  ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
-#define ASSIST_DEBUG_LOG_ENA_V  0x7
-#define ASSIST_DEBUG_LOG_ENA_S  0
-
-#define ASSIST_DEBUG_LOG_DATA_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x074)
-/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_DATA_0  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_0_M  ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
-#define ASSIST_DEBUG_LOG_DATA_0_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_0_S  0
-
-#define ASSIST_DEBUG_LOG_DATA_MASK_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x078)
-/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_DATA_SIZE  0x0000FFFF
-#define ASSIST_DEBUG_LOG_DATA_SIZE_M  ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
-#define ASSIST_DEBUG_LOG_DATA_SIZE_V  0xFFFF
-#define ASSIST_DEBUG_LOG_DATA_SIZE_S  0
-
-#define ASSIST_DEBUG_LOG_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x07C)
-/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MIN  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MIN_M  ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
-#define ASSIST_DEBUG_LOG_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MIN_S  0
-
-#define ASSIST_DEBUG_LOG_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x080)
-/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MAX  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MAX_M  ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
-#define ASSIST_DEBUG_LOG_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MAX_S  0
-
-#define ASSIST_DEBUG_LOG_MEM_START_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x084)
-/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_START  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_START_M  ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
-#define ASSIST_DEBUG_LOG_MEM_START_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_START_S  0
-
-#define ASSIST_DEBUG_LOG_MEM_END_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x088)
-/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_END  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_END_M  ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
-#define ASSIST_DEBUG_LOG_MEM_END_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_END_S  0
-
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x08C)
-/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M  ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S  0
-
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x090)
-/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG  (BIT(1))
-#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M  (BIT(1))
-#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V  0x1
-#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S  1
-/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG  (BIT(0))
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M  (BIT(0))
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V  0x1
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S  0
-
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x094)
-/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S))
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
-
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x098)
-/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x1
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
-/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x1
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
-
-#define ASSIST_DEBUG_DATE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
-/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */
-/*description: */
-#define ASSIST_DEBUG_DATE  0x0FFFFFFF
-#define ASSIST_DEBUG_DATE_M  ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S))
-#define ASSIST_DEBUG_DATE_V  0xFFFFFFF
-#define ASSIST_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_ASSIST_DEBUG_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/clk_tree_defs.h b/components/soc/esp32c3/include/soc/clk_tree_defs.h
index 4aa6e8f7530..901f3fa5130 100644
--- a/components/soc/esp32c3/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c3/include/soc/clk_tree_defs.h
@@ -21,7 +21,7 @@ extern "C" {
  *
  * 2) External 40MHz Crystal Clock: XTAL
  *
- * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.
@@ -83,9 +83,12 @@ typedef enum {
  */
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0,      /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 1,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
 } soc_rtc_fast_clk_src_t;
 
 /**
diff --git a/components/soc/esp32c3/include/soc/dport_access.h b/components/soc/esp32c3/include/soc/dport_access.h
index 5a847ca4842..e499a791bdd 100644
--- a/components/soc/esp32c3/include/soc/dport_access.h
+++ b/components/soc/esp32c3/include/soc/dport_access.h
@@ -8,8 +8,7 @@
 #define _DPORT_ACCESS_H_
 
 #include <stdint.h>
-#include "soc.h"
-#include "uart_reg.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32c3/include/soc/efuse_reg.h b/components/soc/esp32c3/include/soc/efuse_reg.h
deleted file mode 100644
index 4d6781c976b..00000000000
--- a/components/soc/esp32c3/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,2637 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#include "efuse_defs.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 1st 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 2nd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 3rd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 0th 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 1st 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 2nd 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS_REG register
- *  BLOCK0 data register 0.
- */
-#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Disable programming of individual eFuses.
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  BLOCK0 data register 1.
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Set this bit to disable reading from BlOCK4-10.
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0;
- *  Set this bit to disable boot from RTC RAM.
- */
-#define EFUSE_DIS_RTC_RAM_BOOT    (BIT(7))
-#define EFUSE_DIS_RTC_RAM_BOOT_M  (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S)
-#define EFUSE_DIS_RTC_RAM_BOOT_V  0x00000001U
-#define EFUSE_DIS_RTC_RAM_BOOT_S  7
-/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
- *  Set this bit to disable Icache.
- */
-#define EFUSE_DIS_ICACHE    (BIT(8))
-#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
-#define EFUSE_DIS_ICACHE_V  0x00000001U
-#define EFUSE_DIS_ICACHE_S  8
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
- *  Set this bit to disable function of usb switch to jtag in module of usb device.
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  9
-/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0;
- *  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6,
- *  7).
- */
-#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(10))
-#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
-#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
- *  Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Set this bit to disable the function that forces chip into download mode.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/** EFUSE_RPT4_RESERVED6 : RO; bitpos: [13]; default: 0;
- *  Reserved (used for four backups method).
- */
-#define EFUSE_RPT4_RESERVED6    (BIT(13))
-#define EFUSE_RPT4_RESERVED6_M  (EFUSE_RPT4_RESERVED6_V << EFUSE_RPT4_RESERVED6_S)
-#define EFUSE_RPT4_RESERVED6_V  0x00000001U
-#define EFUSE_RPT4_RESERVED6_S  13
-/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Set this bit to disable CAN function.
- */
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
-#define EFUSE_DIS_TWAI_V  0x00000001U
-#define EFUSE_DIS_TWAI_S  14
-/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
- */
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
-#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_S  15
-/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG
- *  can be enabled in HMAC module.
- */
-#define EFUSE_SOFT_DIS_JTAG    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
-#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Set this bit to disable flash encryption when in download boot modes.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored
- *  in eFuse.
- */
-#define EFUSE_USB_DREFH    0x00000003U
-#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
-#define EFUSE_USB_DREFH_V  0x00000003U
-#define EFUSE_USB_DREFH_S  21
-/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
- *  stored in eFuse.
- */
-#define EFUSE_USB_DREFL    0x00000003U
-#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
-#define EFUSE_USB_DREFL_V  0x00000003U
-#define EFUSE_USB_DREFL_S  23
-/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
- *  Set this bit to exchange USB D+ and D- pins.
- */
-#define EFUSE_USB_EXCHG_PINS    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
-#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_S  25
-/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
- *  Set this bit to vdd spi pin function as gpio.
- */
-#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
-#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_S  26
-/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0;
- *  Enable btlc gpio.
- */
-#define EFUSE_BTLC_GPIO_ENABLE    0x00000003U
-#define EFUSE_BTLC_GPIO_ENABLE_M  (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S)
-#define EFUSE_BTLC_GPIO_ENABLE_V  0x00000003U
-#define EFUSE_BTLC_GPIO_ENABLE_S  27
-/** EFUSE_POWERGLITCH_EN : RO; bitpos: [29]; default: 0;
- *  Set this bit to enable power glitch function.
- */
-#define EFUSE_POWERGLITCH_EN    (BIT(29))
-#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
-#define EFUSE_POWERGLITCH_EN_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_S  29
-/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [31:30]; default: 0;
- *  Sample delay configuration of power glitch.
- */
-#define EFUSE_POWER_GLITCH_DSENSE    0x00000003U
-#define EFUSE_POWER_GLITCH_DSENSE_M  (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S)
-#define EFUSE_POWER_GLITCH_DSENSE_V  0x00000003U
-#define EFUSE_POWER_GLITCH_DSENSE_S  30
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  BLOCK0 data register 2.
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_RPT4_RESERVED2 : RO; bitpos: [15:0]; default: 0;
- *  Reserved (used for four backups method).
- */
-#define EFUSE_RPT4_RESERVED2    0x0000FFFFU
-#define EFUSE_RPT4_RESERVED2_M  (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S)
-#define EFUSE_RPT4_RESERVED2_V  0x0000FFFFU
-#define EFUSE_RPT4_RESERVED2_S  0
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
- *  80000. 2: 160000. 3:320000.
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
- *  number of 1: disable.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Set this bit to enable revoking first secure boot key.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Set this bit to enable revoking second secure boot key.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Set this bit to enable revoking third secure boot key.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  24
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  BLOCK0 data register 3.
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  0
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  4
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  8
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  12
-/** EFUSE_RPT4_RESERVED3 : RO; bitpos: [19:16]; default: 0;
- *  Reserved (used for four backups method).
- */
-#define EFUSE_RPT4_RESERVED3    0x0000000FU
-#define EFUSE_RPT4_RESERVED3_M  (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S)
-#define EFUSE_RPT4_RESERVED3_V  0x0000000FU
-#define EFUSE_RPT4_RESERVED3_S  16
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Set this bit to enable secure boot.
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Set this bit to enable revoking aggressive secure boot.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [27:22]; default: 0;
- *  Reserved (used for four backups method).
- */
-#define EFUSE_RPT4_RESERVED0    0x0000003FU
-#define EFUSE_RPT4_RESERVED0_M  (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S)
-#define EFUSE_RPT4_RESERVED0_V  0x0000003FU
-#define EFUSE_RPT4_RESERVED0_S  22
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Configures flash waiting time after power-up, in unit of ms. If the value is less
- *  than 15, the waiting time is the configurable value; Otherwise, the waiting time is
- *  twice the configurable value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  BLOCK0 data register 4.
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Disable direct boot mode
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0;
- *  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
- *  use 16to17 byte mode.
- */
-#define EFUSE_FLASH_ECC_MODE    (BIT(3))
-#define EFUSE_FLASH_ECC_MODE_M  (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S)
-#define EFUSE_FLASH_ECC_MODE_V  0x00000001U
-#define EFUSE_FLASH_ECC_MODE_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Disable UART download mode through USB-Serial-JTAG
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Set this bit to enable secure UART download mode.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8
- *  is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0;
- *  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
- */
-#define EFUSE_PIN_POWER_SELECTION    (BIT(8))
-#define EFUSE_PIN_POWER_SELECTION_M  (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S)
-#define EFUSE_PIN_POWER_SELECTION_V  0x00000001U
-#define EFUSE_PIN_POWER_SELECTION_S  8
-/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0;
- *  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
- */
-#define EFUSE_FLASH_TYPE    (BIT(9))
-#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
-#define EFUSE_FLASH_TYPE_V  0x00000001U
-#define EFUSE_FLASH_TYPE_S  9
-/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0;
- *  Set Flash page size.
- */
-#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
-#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_S  10
-/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0;
- *  Set 1 to enable ECC for flash boot.
- */
-#define EFUSE_FLASH_ECC_EN    (BIT(12))
-#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
-#define EFUSE_FLASH_ECC_EN_V  0x00000001U
-#define EFUSE_FLASH_ECC_EN_S  12
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
- *  Set this bit to force ROM code to send a resume command during SPI boot.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  13
-/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0;
- *  Secure version (used by ESP-IDF anti-rollback feature).
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  14
-/** EFUSE_RESERVED_0_158 : R; bitpos: [30]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_0_158    (BIT(30))
-#define EFUSE_RESERVED_0_158_M  (EFUSE_RESERVED_0_158_V << EFUSE_RESERVED_0_158_S)
-#define EFUSE_RESERVED_0_158_V  0x00000001U
-#define EFUSE_RESERVED_0_158_S  30
-/** EFUSE_ERR_RST_ENABLE : R; bitpos: [31]; default: 0;
- *  Use BLOCK0 to check error record registers
- */
-#define EFUSE_ERR_RST_ENABLE    (BIT(31))
-#define EFUSE_ERR_RST_ENABLE_M  (EFUSE_ERR_RST_ENABLE_V << EFUSE_ERR_RST_ENABLE_S)
-#define EFUSE_ERR_RST_ENABLE_V  0x00000001U
-#define EFUSE_ERR_RST_ENABLE_S  31
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  BLOCK0 data register 5.
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0;
- *  Disables check of wafer version major
- */
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(0))
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  0
-/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0;
- *  Disables check of blk version major
- */
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(1))
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  1
-/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_0_162    0x003FFFFFU
-#define EFUSE_RESERVED_0_162_M  (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S)
-#define EFUSE_RESERVED_0_162_V  0x003FFFFFU
-#define EFUSE_RESERVED_0_162_S  2
-
-/** EFUSE_RD_MAC_SPI_SYS_0_REG register
- *  BLOCK1 data register 0.
- */
-#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the low 32 bits of MAC address.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SPI_SYS_1_REG register
- *  BLOCK1 data register 1.
- */
-#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Stores the high 16 bits of MAC address.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0;
- *  SPI PAD CLK
- */
-#define EFUSE_SPI_PAD_CONFIG_CLK    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_CLK_M  (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S)
-#define EFUSE_SPI_PAD_CONFIG_CLK_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_CLK_S  16
-/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0;
- *  SPI PAD Q(D1)
- */
-#define EFUSE_SPI_PAD_CONFIG_Q    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_Q_M  (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S)
-#define EFUSE_SPI_PAD_CONFIG_Q_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_Q_S  22
-/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0;
- *  SPI PAD D(D0)
- */
-#define EFUSE_SPI_PAD_CONFIG_D    0x0000000FU
-#define EFUSE_SPI_PAD_CONFIG_D_M  (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S)
-#define EFUSE_SPI_PAD_CONFIG_D_V  0x0000000FU
-#define EFUSE_SPI_PAD_CONFIG_D_S  28
-
-/** EFUSE_RD_MAC_SPI_SYS_2_REG register
- *  BLOCK1 data register 2.
- */
-#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
-/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0;
- *  SPI PAD D(D0)
- */
-#define EFUSE_SPI_PAD_CONFIG_D_1    0x00000003U
-#define EFUSE_SPI_PAD_CONFIG_D_1_M  (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S)
-#define EFUSE_SPI_PAD_CONFIG_D_1_V  0x00000003U
-#define EFUSE_SPI_PAD_CONFIG_D_1_S  0
-/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0;
- *  SPI PAD CS
- */
-#define EFUSE_SPI_PAD_CONFIG_CS    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_CS_M  (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S)
-#define EFUSE_SPI_PAD_CONFIG_CS_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_CS_S  2
-/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0;
- *  SPI PAD HD(D3)
- */
-#define EFUSE_SPI_PAD_CONFIG_HD    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_HD_M  (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S)
-#define EFUSE_SPI_PAD_CONFIG_HD_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_HD_S  8
-/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0;
- *  SPI PAD WP(D2)
- */
-#define EFUSE_SPI_PAD_CONFIG_WP    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_WP_M  (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S)
-#define EFUSE_SPI_PAD_CONFIG_WP_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_WP_S  14
-/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0;
- *  SPI PAD DQS
- */
-#define EFUSE_SPI_PAD_CONFIG_DQS    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_DQS_M  (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S)
-#define EFUSE_SPI_PAD_CONFIG_DQS_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_DQS_S  20
-/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0;
- *  SPI PAD D4
- */
-#define EFUSE_SPI_PAD_CONFIG_D4    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D4_M  (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S)
-#define EFUSE_SPI_PAD_CONFIG_D4_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D4_S  26
-
-/** EFUSE_RD_MAC_SPI_SYS_3_REG register
- *  BLOCK1 data register 3.
- */
-#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0;
- *  SPI PAD D5
- */
-#define EFUSE_SPI_PAD_CONFIG_D5    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D5_M  (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S)
-#define EFUSE_SPI_PAD_CONFIG_D5_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D5_S  0
-/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0;
- *  SPI PAD D6
- */
-#define EFUSE_SPI_PAD_CONFIG_D6    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D6_M  (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S)
-#define EFUSE_SPI_PAD_CONFIG_D6_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D6_S  6
-/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0;
- *  SPI PAD D7
- */
-#define EFUSE_SPI_PAD_CONFIG_D7    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D7_M  (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S)
-#define EFUSE_SPI_PAD_CONFIG_D7_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D7_S  12
-/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0;
- *  WAFER_VERSION_MINOR least significant bits
- */
-#define EFUSE_WAFER_VERSION_MINOR_LO    0x00000007U
-#define EFUSE_WAFER_VERSION_MINOR_LO_M  (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S)
-#define EFUSE_WAFER_VERSION_MINOR_LO_V  0x00000007U
-#define EFUSE_WAFER_VERSION_MINOR_LO_S  18
-/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0;
- *  Package version
- */
-#define EFUSE_PKG_VERSION    0x00000007U
-#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
-#define EFUSE_PKG_VERSION_V  0x00000007U
-#define EFUSE_PKG_VERSION_S  21
-/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0;
- *  BLK_VERSION_MINOR
- */
-#define EFUSE_BLK_VERSION_MINOR    0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
-#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_S  24
-/** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0;
- *  Flash capacity
- */
-#define EFUSE_FLASH_CAP    0x00000007U
-#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
-#define EFUSE_FLASH_CAP_V  0x00000007U
-#define EFUSE_FLASH_CAP_S  27
-/** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0;
- *  Flash temperature
- */
-#define EFUSE_FLASH_TEMP    0x00000003U
-#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
-#define EFUSE_FLASH_TEMP_V  0x00000003U
-#define EFUSE_FLASH_TEMP_S  30
-
-/** EFUSE_RD_MAC_SPI_SYS_4_REG register
- *  BLOCK1 data register 4.
- */
-#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0;
- *  Flash vendor
- */
-#define EFUSE_FLASH_VENDOR    0x00000007U
-#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
-#define EFUSE_FLASH_VENDOR_V  0x00000007U
-#define EFUSE_FLASH_VENDOR_S  0
-/** EFUSE_RESERVED_1_131 : R; bitpos: [6:3]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_131    0x0000000FU
-#define EFUSE_RESERVED_1_131_M  (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S)
-#define EFUSE_RESERVED_1_131_V  0x0000000FU
-#define EFUSE_RESERVED_1_131_S  3
-/** EFUSE_K_RTC_LDO : R; bitpos: [13:7]; default: 0;
- *  BLOCK1 K_RTC_LDO
- */
-#define EFUSE_K_RTC_LDO    0x0000007FU
-#define EFUSE_K_RTC_LDO_M  (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S)
-#define EFUSE_K_RTC_LDO_V  0x0000007FU
-#define EFUSE_K_RTC_LDO_S  7
-/** EFUSE_K_DIG_LDO : R; bitpos: [20:14]; default: 0;
- *  BLOCK1 K_DIG_LDO
- */
-#define EFUSE_K_DIG_LDO    0x0000007FU
-#define EFUSE_K_DIG_LDO_M  (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S)
-#define EFUSE_K_DIG_LDO_V  0x0000007FU
-#define EFUSE_K_DIG_LDO_S  14
-/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [28:21]; default: 0;
- *  BLOCK1 voltage of rtc dbias20
- */
-#define EFUSE_V_RTC_DBIAS20    0x000000FFU
-#define EFUSE_V_RTC_DBIAS20_M  (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S)
-#define EFUSE_V_RTC_DBIAS20_V  0x000000FFU
-#define EFUSE_V_RTC_DBIAS20_S  21
-/** EFUSE_V_DIG_DBIAS20 : R; bitpos: [31:29]; default: 0;
- *  BLOCK1 voltage of digital dbias20
- */
-#define EFUSE_V_DIG_DBIAS20    0x00000007U
-#define EFUSE_V_DIG_DBIAS20_M  (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S)
-#define EFUSE_V_DIG_DBIAS20_V  0x00000007U
-#define EFUSE_V_DIG_DBIAS20_S  29
-
-/** EFUSE_RD_MAC_SPI_SYS_5_REG register
- *  BLOCK1 data register 5.
- */
-#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_V_DIG_DBIAS20_1 : R; bitpos: [4:0]; default: 0;
- *  BLOCK1 voltage of digital dbias20
- */
-#define EFUSE_V_DIG_DBIAS20_1    0x0000001FU
-#define EFUSE_V_DIG_DBIAS20_1_M  (EFUSE_V_DIG_DBIAS20_1_V << EFUSE_V_DIG_DBIAS20_1_S)
-#define EFUSE_V_DIG_DBIAS20_1_V  0x0000001FU
-#define EFUSE_V_DIG_DBIAS20_1_S  0
-/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [9:5]; default: 0;
- *  BLOCK1 digital dbias when hvt
- */
-#define EFUSE_DIG_DBIAS_HVT    0x0000001FU
-#define EFUSE_DIG_DBIAS_HVT_M  (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
-#define EFUSE_DIG_DBIAS_HVT_V  0x0000001FU
-#define EFUSE_DIG_DBIAS_HVT_S  5
-/** EFUSE_THRES_HVT : R; bitpos: [19:10]; default: 0;
- *  BLOCK1 pvt threshold when hvt
- */
-#define EFUSE_THRES_HVT    0x000003FFU
-#define EFUSE_THRES_HVT_M  (EFUSE_THRES_HVT_V << EFUSE_THRES_HVT_S)
-#define EFUSE_THRES_HVT_V  0x000003FFU
-#define EFUSE_THRES_HVT_S  10
-/** EFUSE_RESERVED_1_180 : R; bitpos: [22:20]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_180    0x00000007U
-#define EFUSE_RESERVED_1_180_M  (EFUSE_RESERVED_1_180_V << EFUSE_RESERVED_1_180_S)
-#define EFUSE_RESERVED_1_180_V  0x00000007U
-#define EFUSE_RESERVED_1_180_S  20
-/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0;
- *  WAFER_VERSION_MINOR most significant bit
- */
-#define EFUSE_WAFER_VERSION_MINOR_HI    (BIT(23))
-#define EFUSE_WAFER_VERSION_MINOR_HI_M  (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S)
-#define EFUSE_WAFER_VERSION_MINOR_HI_V  0x00000001U
-#define EFUSE_WAFER_VERSION_MINOR_HI_S  23
-/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0;
- *  WAFER_VERSION_MAJOR
- */
-#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_S  24
-/** EFUSE_RESERVED_1_186 : R; bitpos: [31:26]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_186    0x0000003FU
-#define EFUSE_RESERVED_1_186_M  (EFUSE_RESERVED_1_186_V << EFUSE_RESERVED_1_186_S)
-#define EFUSE_RESERVED_1_186_V  0x0000003FU
-#define EFUSE_RESERVED_1_186_S  26
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Register 0 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Register 1 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Register 2 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Register 3 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Register 4 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0;
- *  BLK_VERSION_MAJOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
-#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_S  0
-/** EFUSE_RESERVED_2_130 : R; bitpos: [2]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_130    (BIT(2))
-#define EFUSE_RESERVED_2_130_M  (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S)
-#define EFUSE_RESERVED_2_130_V  0x00000001U
-#define EFUSE_RESERVED_2_130_S  2
-/** EFUSE_TEMP_CALIB : R; bitpos: [11:3]; default: 0;
- *  Temperature calibration data
- */
-#define EFUSE_TEMP_CALIB    0x000001FFU
-#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
-#define EFUSE_TEMP_CALIB_V  0x000001FFU
-#define EFUSE_TEMP_CALIB_S  3
-/** EFUSE_OCODE : R; bitpos: [19:12]; default: 0;
- *  ADC OCode
- */
-#define EFUSE_OCODE    0x000000FFU
-#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
-#define EFUSE_OCODE_V  0x000000FFU
-#define EFUSE_OCODE_S  12
-/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [29:20]; default: 0;
- *  ADC1 init code at atten0
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0    0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_V  0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_S  20
-/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:30]; default: 0;
- *  ADC1 init code at atten1
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN1    0x00000003U
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_V  0x00000003U
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_S  30
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Register 5 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [7:0]; default: 0;
- *  ADC1 init code at atten1
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1    0x000000FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V  0x000000FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S  0
-/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [17:8]; default: 0;
- *  ADC1 init code at atten2
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN2    0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_M  (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_V  0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_S  8
-/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [27:18]; default: 0;
- *  ADC1 init code at atten3
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN3    0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_V  0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_S  18
-/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:28]; default: 0;
- *  ADC1 calibration voltage at atten0
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN0    0x0000000FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_V  0x0000000FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_S  28
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Register 6 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [5:0]; default: 0;
- *  ADC1 calibration voltage at atten0
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1    0x0000003FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V  0x0000003FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S  0
-/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [15:6]; default: 0;
- *  ADC1 calibration voltage at atten1
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN1    0x000003FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_M  (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_V  0x000003FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_S  6
-/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [25:16]; default: 0;
- *  ADC1 calibration voltage at atten2
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN2    0x000003FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_M  (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_V  0x000003FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_S  16
-/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0;
- *  ADC1 calibration voltage at atten3
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN3    0x0000003FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_V  0x0000003FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_S  26
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Register 7 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_ADC1_CAL_VOL_ATTEN3_1 : R; bitpos: [3:0]; default: 0;
- *  ADC1 calibration voltage at atten3
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_1    0x0000000FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_1_V << EFUSE_ADC1_CAL_VOL_ATTEN3_1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_V  0x0000000FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_S  0
-/** EFUSE_RESERVED_2_228 : R; bitpos: [31:4]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_228    0x0FFFFFFFU
-#define EFUSE_RESERVED_2_228_M  (EFUSE_RESERVED_2_228_V << EFUSE_RESERVED_2_228_S)
-#define EFUSE_RESERVED_2_228_V  0x0FFFFFFFU
-#define EFUSE_RESERVED_2_228_S  4
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Register 0 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Register 1 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Register 2 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Register 3 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Register 4 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Register 5 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Register 6 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_192    0x000000FFU
-#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
-#define EFUSE_RESERVED_3_192_V  0x000000FFU
-#define EFUSE_RESERVED_3_192_S  0
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
- *  Custom MAC address
- */
-#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_S  8
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Register 7 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
- *  Custom MAC address
- */
-#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_248    0x000000FFU
-#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
-#define EFUSE_RESERVED_3_248_V  0x000000FFU
-#define EFUSE_RESERVED_3_248_S  24
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Register 0 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Register 1 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Register 2 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Register 3 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Register 4 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Register 5 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Register 6 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Register 7 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Register 0 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Register 1 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Register 2 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Register 3 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Register 4 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Register 5 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Register 6 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Register 7 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Register 0 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Register 1 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Register 2 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Register 3 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Register 4 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Register 5 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Register 6 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Register 7 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Register 0 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Register 1 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Register 2 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Register 3 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Register 4 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Register 5 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Register 6 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Register 7 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Register 0 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Register 1 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Register 2 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Register 3 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Register 4 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Register 5 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Register 6 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Register 7 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Register 0 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Register 1 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Register 2 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Register 3 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Register 4 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Register 5 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Register 6 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Register 7 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Register 0 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 0th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Register 1 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 1st 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Register 2 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 2nd 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Register 3 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 3rd 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Register 4 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 4th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Register 5 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 5th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Register 6 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 6th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Register 7 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 7th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_ERR0_REG register
- *  Programming error record register 0 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  If any bit in RD_DIS is 1, then it indicates a programming error.
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0;
- *  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_RTC_RAM_BOOT_ERR    (BIT(7))
-#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M  (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S)
-#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S  7
-/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
- *  If DIS_ICACHE is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
-#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
-#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_ICACHE_ERR_S  8
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  If DIS_USB_JTAG is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  9
-/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0;
- *  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(10))
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  10
-/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [11]; default: 0;
- *  If DIS_USB_DEVICE is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_USB_DEVICE_ERR    (BIT(11))
-#define EFUSE_DIS_USB_DEVICE_ERR_M  (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S)
-#define EFUSE_DIS_USB_DEVICE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_DEVICE_ERR_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/** EFUSE_RPT4_RESERVED6_ERR : RO; bitpos: [13]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED6_ERR    (BIT(13))
-#define EFUSE_RPT4_RESERVED6_ERR_M  (EFUSE_RPT4_RESERVED6_ERR_V << EFUSE_RPT4_RESERVED6_ERR_S)
-#define EFUSE_RPT4_RESERVED6_ERR_V  0x00000001U
-#define EFUSE_RPT4_RESERVED6_ERR_S  13
-/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0;
- *  If DIS_CAN is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_CAN_ERR    (BIT(14))
-#define EFUSE_DIS_CAN_ERR_M  (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S)
-#define EFUSE_DIS_CAN_ERR_V  0x00000001U
-#define EFUSE_DIS_CAN_ERR_S  14
-/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
- *  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
- */
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
-/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
- */
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  If DIS_PAD_JTAG is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
- *  If any bit in USB_DREFH is 1, then it indicates a programming error.
- */
-#define EFUSE_USB_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
-#define EFUSE_USB_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DREFH_ERR_S  21
-/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
- *  If any bit in USB_DREFL is 1, then it indicates a programming error.
- */
-#define EFUSE_USB_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
-#define EFUSE_USB_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DREFL_ERR_S  23
-/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
- *  If USB_EXCHG_PINS is 1, then it indicates a programming error.
- */
-#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
-#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_ERR_S  25
-/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
- *  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
-/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0;
- *  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
- */
-#define EFUSE_BTLC_GPIO_ENABLE_ERR    0x00000003U
-#define EFUSE_BTLC_GPIO_ENABLE_ERR_M  (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S)
-#define EFUSE_BTLC_GPIO_ENABLE_ERR_V  0x00000003U
-#define EFUSE_BTLC_GPIO_ENABLE_ERR_S  27
-/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [29]; default: 0;
- *  If POWERGLITCH_EN is 1, then it indicates a programming error.
- */
-#define EFUSE_POWERGLITCH_EN_ERR    (BIT(29))
-#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
-#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_ERR_S  29
-/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [31:30]; default: 0;
- *  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
- */
-#define EFUSE_POWER_GLITCH_DSENSE_ERR    0x00000003U
-#define EFUSE_POWER_GLITCH_DSENSE_ERR_M  (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S)
-#define EFUSE_POWER_GLITCH_DSENSE_ERR_V  0x00000003U
-#define EFUSE_POWER_GLITCH_DSENSE_ERR_S  30
-
-/** EFUSE_RD_REPEAT_ERR1_REG register
- *  Programming error record register 1 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [15:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED2_ERR    0x0000FFFFU
-#define EFUSE_RPT4_RESERVED2_ERR_M  (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S)
-#define EFUSE_RPT4_RESERVED2_ERR_V  0x0000FFFFU
-#define EFUSE_RPT4_RESERVED2_ERR_S  0
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR2_REG register
- *  Programming error record register 2 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  0
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/** EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [19:16]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_ERR    0x0000000FU
-#define EFUSE_RPT4_RESERVED3_ERR_M  (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S)
-#define EFUSE_RPT4_RESERVED3_ERR_V  0x0000000FU
-#define EFUSE_RPT4_RESERVED3_ERR_S  16
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  If SECURE_BOOT_EN is 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [27:22]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_ERR    0x0000003FU
-#define EFUSE_RPT4_RESERVED0_ERR_M  (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S)
-#define EFUSE_RPT4_RESERVED0_ERR_V  0x0000003FU
-#define EFUSE_RPT4_RESERVED0_ERR_S  22
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR3_REG register
- *  Programming error record register 3 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M  (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S)
-#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S  1
-/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0;
- *  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
- */
-#define EFUSE_UART_PRINT_CHANNEL_ERR    (BIT(2))
-#define EFUSE_UART_PRINT_CHANNEL_ERR_M  (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S)
-#define EFUSE_UART_PRINT_CHANNEL_ERR_V  0x00000001U
-#define EFUSE_UART_PRINT_CHANNEL_ERR_S  2
-/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0;
- *  If FLASH_ECC_MODE is 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_ECC_MODE_ERR    (BIT(3))
-#define EFUSE_FLASH_ECC_MODE_ERR_M  (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S)
-#define EFUSE_FLASH_ECC_MODE_ERR_V  0x00000001U
-#define EFUSE_FLASH_ECC_MODE_ERR_S  3
-/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0;
- *  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
- */
-#define EFUSE_PIN_POWER_SELECTION_ERR    (BIT(8))
-#define EFUSE_PIN_POWER_SELECTION_ERR_M  (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S)
-#define EFUSE_PIN_POWER_SELECTION_ERR_V  0x00000001U
-#define EFUSE_PIN_POWER_SELECTION_ERR_S  8
-/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0;
- *  If FLASH_TYPE is 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_TYPE_ERR    (BIT(9))
-#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
-#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
-#define EFUSE_FLASH_TYPE_ERR_S  9
-/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0;
- *  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
-#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_S  10
-/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0;
- *  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_ECC_EN_ERR    (BIT(12))
-#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
-#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
-#define EFUSE_FLASH_ECC_EN_ERR_S  12
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
- *  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0;
- *  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  14
-/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31:30]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED1_ERR    0x00000003U
-#define EFUSE_RPT4_RESERVED1_ERR_M  (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S)
-#define EFUSE_RPT4_RESERVED1_ERR_V  0x00000003U
-#define EFUSE_RPT4_RESERVED1_ERR_S  30
-
-/** EFUSE_RD_REPEAT_ERR4_REG register
- *  Programming error record register 4 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
-/** EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED4_ERR    0x00FFFFFFU
-#define EFUSE_RPT4_RESERVED4_ERR_M  (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S)
-#define EFUSE_RPT4_RESERVED4_ERR_V  0x00FFFFFFU
-#define EFUSE_RPT4_RESERVED4_ERR_S  0
-
-/** EFUSE_RD_RS_ERR0_REG register
- *  Programming error record register 0 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
-#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
-#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
-#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
-/** EFUSE_RESERVED_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_RESERVED_FAIL    (BIT(3))
-#define EFUSE_RESERVED_FAIL_M  (EFUSE_RESERVED_FAIL_V << EFUSE_RESERVED_FAIL_S)
-#define EFUSE_RESERVED_FAIL_V  0x00000001U
-#define EFUSE_RESERVED_FAIL_S  3
-/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART1_NUM    0x00000007U
-#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
-#define EFUSE_SYS_PART1_NUM_V  0x00000007U
-#define EFUSE_SYS_PART1_NUM_S  4
-/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part1 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_MAC_SPI_8M_FAIL    (BIT(7))
-#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
-#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
-#define EFUSE_MAC_SPI_8M_FAIL_S  7
-/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
-#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_S  8
-/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [11]; default: 0;
- *  0: Means no failure and that the user data is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART1_FAIL    (BIT(11))
-#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
-#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART1_FAIL_S  11
-/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY0_ERR_NUM    0x00000007U
-#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
-#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY0_ERR_NUM_S  12
-/** EFUSE_USR_DATA_FAIL : RO; bitpos: [15]; default: 0;
- *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
- *  key0 failed and the number of error bytes is over 6.
- */
-#define EFUSE_USR_DATA_FAIL    (BIT(15))
-#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
-#define EFUSE_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_USR_DATA_FAIL_S  15
-/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY1_ERR_NUM    0x00000007U
-#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
-#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY1_ERR_NUM_S  16
-/** EFUSE_KEY0_FAIL : RO; bitpos: [19]; default: 0;
- *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
- *  key1 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY0_FAIL    (BIT(19))
-#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
-#define EFUSE_KEY0_FAIL_V  0x00000001U
-#define EFUSE_KEY0_FAIL_S  19
-/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY2_ERR_NUM    0x00000007U
-#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
-#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY2_ERR_NUM_S  20
-/** EFUSE_KEY1_FAIL : RO; bitpos: [23]; default: 0;
- *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
- *  key2 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY1_FAIL    (BIT(23))
-#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
-#define EFUSE_KEY1_FAIL_V  0x00000001U
-#define EFUSE_KEY1_FAIL_S  23
-/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY3_ERR_NUM    0x00000007U
-#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
-#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY3_ERR_NUM_S  24
-/** EFUSE_KEY2_FAIL : RO; bitpos: [27]; default: 0;
- *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
- *  key3 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY2_FAIL    (BIT(27))
-#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
-#define EFUSE_KEY2_FAIL_V  0x00000001U
-#define EFUSE_KEY2_FAIL_S  27
-/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY4_ERR_NUM    0x00000007U
-#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
-#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY4_ERR_NUM_S  28
-/** EFUSE_KEY3_FAIL : RO; bitpos: [31]; default: 0;
- *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
- *  key4 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY3_FAIL    (BIT(31))
-#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
-#define EFUSE_KEY3_FAIL_V  0x00000001U
-#define EFUSE_KEY3_FAIL_S  31
-
-/** EFUSE_RD_RS_ERR1_REG register
- *  Programming error record register 1 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY5_ERR_NUM    0x00000007U
-#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
-#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY5_ERR_NUM_S  0
-/** EFUSE_KEY4_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY4_FAIL    (BIT(3))
-#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
-#define EFUSE_KEY4_FAIL_V  0x00000001U
-#define EFUSE_KEY4_FAIL_S  3
-/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
-#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_S  4
-/** EFUSE_KEY5_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part2 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY5_FAIL    (BIT(7))
-#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
-#define EFUSE_KEY5_FAIL_V  0x00000001U
-#define EFUSE_KEY5_FAIL_S  7
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
-/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_EFUSE_MEM_FORCE_PD_M  (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_EFUSE_MEM_FORCE_PU_M  (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit and force to enable clock signal of eFuse memory.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register;
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
- *  The value of OTP_LOAD_SW.
- */
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
-#define EFUSE_OTP_LOAD_SW_V  0x00000001U
-#define EFUSE_OTP_LOAD_SW_S  4
-/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
- *  The value of OTP_VDDQ_C_SYNC2.
- */
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
- *  The value of OTP_STROBE_SW.
- */
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
-#define EFUSE_OTP_STROBE_SW_V  0x00000001U
-#define EFUSE_OTP_STROBE_SW_S  6
-/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
- *  The value of OTP_CSB_SW.
- */
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
-#define EFUSE_OTP_CSB_SW_V  0x00000001U
-#define EFUSE_OTP_CSB_SW_S  7
-/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
- *  The value of OTP_PGENB_SW.
- */
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
-#define EFUSE_OTP_PGENB_SW_V  0x00000001U
-#define EFUSE_OTP_PGENB_SW_S  8
-/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
- *  The value of OTP_VDDQ_IS_SW.
- */
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0;
- *  Indicates the number of error bits during programming BLOCK0.
- */
-#define EFUSE_REPEAT_ERR_CNT    0x000000FFU
-#define EFUSE_REPEAT_ERR_CNT_M  (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S)
-#define EFUSE_REPEAT_ERR_CNT_V  0x000000FFU
-#define EFUSE_REPEAT_ERR_CNT_S  10
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
- *  Configures the initial read time of eFuse.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 33583616;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/efuse_struct.h b/components/soc/esp32c3/include/soc/efuse_struct.h
deleted file mode 100644
index 99f8c39ec57..00000000000
--- a/components/soc/esp32c3/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,2386 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PGM Data Register */
-/** Type of pgm_data0 register
- *  Register 0 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Register 1 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 1st 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Register 2 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 2nd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Register 3 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 3rd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Register 4 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 4th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Register 5 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 5th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Register 6 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 6th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Register 7 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 7th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-/** Type of pgm_check_value0 register
- *  Register 0 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 0th 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Register 1 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 1st 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Register 2 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 2nd 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: Read Data Register */
-/** Type of rd_wr_dis register
- *  BLOCK0 data register 0.
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Disable programming of individual eFuses.
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  BLOCK0 data register 1.
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Set this bit to disable reading from BlOCK4-10.
-         */
-        uint32_t rd_dis:7;
-        /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0;
-         *  Set this bit to disable boot from RTC RAM.
-         */
-        uint32_t dis_rtc_ram_boot:1;
-        /** dis_icache : RO; bitpos: [8]; default: 0;
-         *  Set this bit to disable Icache.
-         */
-        uint32_t dis_icache:1;
-        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Set this bit to disable function of usb switch to jtag in module of usb device.
-         */
-        uint32_t dis_usb_jtag:1;
-        /** dis_download_icache : RO; bitpos: [10]; default: 0;
-         *  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6,
-         *  7).
-         */
-        uint32_t dis_download_icache:1;
-        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
-         *  Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled
-         */
-        uint32_t dis_usb_serial_jtag:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Set this bit to disable the function that forces chip into download mode.
-         */
-        uint32_t dis_force_download:1;
-        /** rpt4_reserved6 : RO; bitpos: [13]; default: 0;
-         *  Reserved (used for four backups method).
-         */
-        uint32_t rpt4_reserved6:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Set this bit to disable CAN function.
-         */
-        uint32_t dis_twai:1;
-        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
-         */
-        uint32_t jtag_sel_enable:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG
-         *  can be enabled in HMAC module.
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Set this bit to disable flash encryption when in download boot modes.
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored
-         *  in eFuse.
-         */
-        uint32_t usb_drefh:2;
-        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
-         *  stored in eFuse.
-         */
-        uint32_t usb_drefl:2;
-        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
-         *  Set this bit to exchange USB D+ and D- pins.
-         */
-        uint32_t usb_exchg_pins:1;
-        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
-         *  Set this bit to vdd spi pin function as gpio.
-         */
-        uint32_t vdd_spi_as_gpio:1;
-        /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0;
-         *  Enable btlc gpio.
-         */
-        uint32_t btlc_gpio_enable:2;
-        /** powerglitch_en : RO; bitpos: [29]; default: 0;
-         *  Set this bit to enable power glitch function.
-         */
-        uint32_t powerglitch_en:1;
-        /** power_glitch_dsense : RO; bitpos: [31:30]; default: 0;
-         *  Sample delay configuration of power glitch.
-         */
-        uint32_t power_glitch_dsense:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  BLOCK0 data register 2.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved2 : RO; bitpos: [15:0]; default: 0;
-         *  Reserved (used for four backups method).
-         */
-        uint32_t rpt4_reserved2:16;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
-         *  80000. 2: 160000. 3:320000.
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
-         *  number of 1: disable.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Set this bit to enable revoking first secure boot key.
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Set this bit to enable revoking second secure boot key.
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Set this bit to enable revoking third secure boot key.
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  BLOCK0 data register 3.
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** rpt4_reserved3 : RO; bitpos: [19:16]; default: 0;
-         *  Reserved (used for four backups method).
-         */
-        uint32_t rpt4_reserved3:4;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Set this bit to enable secure boot.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Set this bit to enable revoking aggressive secure boot.
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** rpt4_reserved0 : RO; bitpos: [27:22]; default: 0;
-         *  Reserved (used for four backups method).
-         */
-        uint32_t rpt4_reserved0:6;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Configures flash waiting time after power-up, in unit of ms. If the value is less
-         *  than 15, the waiting time is the configurable value; Otherwise, the waiting time is
-         *  twice the configurable value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  BLOCK0 data register 4.
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Disable direct boot mode
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** flash_ecc_mode : RO; bitpos: [3]; default: 0;
-         *  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
-         *  use 16to17 byte mode.
-         */
-        uint32_t flash_ecc_mode:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Disable UART download mode through USB-Serial-JTAG
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Set this bit to enable secure UART download mode.
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8
-         *  is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
-         */
-        uint32_t uart_print_control:2;
-        /** pin_power_selection : RO; bitpos: [8]; default: 0;
-         *  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
-         */
-        uint32_t pin_power_selection:1;
-        /** flash_type : RO; bitpos: [9]; default: 0;
-         *  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
-         */
-        uint32_t flash_type:1;
-        /** flash_page_size : RO; bitpos: [11:10]; default: 0;
-         *  Set Flash page size.
-         */
-        uint32_t flash_page_size:2;
-        /** flash_ecc_en : RO; bitpos: [12]; default: 0;
-         *  Set 1 to enable ECC for flash boot.
-         */
-        uint32_t flash_ecc_en:1;
-        /** force_send_resume : RO; bitpos: [13]; default: 0;
-         *  Set this bit to force ROM code to send a resume command during SPI boot.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [29:14]; default: 0;
-         *  Secure version (used by ESP-IDF anti-rollback feature).
-         */
-        uint32_t secure_version:16;
-        /** reserved_0_158 : R; bitpos: [30]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_0_158:1;
-        /** err_rst_enable : R; bitpos: [31]; default: 0;
-         *  Use BLOCK0 to check error record registers
-         */
-        uint32_t err_rst_enable:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  BLOCK0 data register 5.
- */
-typedef union {
-    struct {
-        /** disable_wafer_version_major : R; bitpos: [0]; default: 0;
-         *  Disables check of wafer version major
-         */
-        uint32_t disable_wafer_version_major:1;
-        /** disable_blk_version_major : R; bitpos: [1]; default: 0;
-         *  Disables check of blk version major
-         */
-        uint32_t disable_blk_version_major:1;
-        /** reserved_0_162 : R; bitpos: [23:2]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_0_162:22;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-/** Type of rd_mac_spi_sys_0 register
- *  BLOCK1 data register 0.
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the low 32 bits of MAC address.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_0_reg_t;
-
-/** Type of rd_mac_spi_sys_1 register
- *  BLOCK1 data register 1.
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Stores the high 16 bits of MAC address.
-         */
-        uint32_t mac_1:16;
-        /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0;
-         *  SPI PAD CLK
-         */
-        uint32_t spi_pad_config_clk:6;
-        /** spi_pad_config_q : R; bitpos: [27:22]; default: 0;
-         *  SPI PAD Q(D1)
-         */
-        uint32_t spi_pad_config_q:6;
-        /** spi_pad_config_d : R; bitpos: [31:28]; default: 0;
-         *  SPI PAD D(D0)
-         */
-        uint32_t spi_pad_config_d:4;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_1_reg_t;
-
-/** Type of rd_mac_spi_sys_2 register
- *  BLOCK1 data register 2.
- */
-typedef union {
-    struct {
-        /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0;
-         *  SPI PAD D(D0)
-         */
-        uint32_t spi_pad_config_d_1:2;
-        /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0;
-         *  SPI PAD CS
-         */
-        uint32_t spi_pad_config_cs:6;
-        /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0;
-         *  SPI PAD HD(D3)
-         */
-        uint32_t spi_pad_config_hd:6;
-        /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0;
-         *  SPI PAD WP(D2)
-         */
-        uint32_t spi_pad_config_wp:6;
-        /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0;
-         *  SPI PAD DQS
-         */
-        uint32_t spi_pad_config_dqs:6;
-        /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0;
-         *  SPI PAD D4
-         */
-        uint32_t spi_pad_config_d4:6;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_2_reg_t;
-
-/** Type of rd_mac_spi_sys_3 register
- *  BLOCK1 data register 3.
- */
-typedef union {
-    struct {
-        /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0;
-         *  SPI PAD D5
-         */
-        uint32_t spi_pad_config_d5:6;
-        /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0;
-         *  SPI PAD D6
-         */
-        uint32_t spi_pad_config_d6:6;
-        /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0;
-         *  SPI PAD D7
-         */
-        uint32_t spi_pad_config_d7:6;
-        /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0;
-         *  WAFER_VERSION_MINOR least significant bits
-         */
-        uint32_t wafer_version_minor_lo:3;
-        /** pkg_version : R; bitpos: [23:21]; default: 0;
-         *  Package version
-         */
-        uint32_t pkg_version:3;
-        /** blk_version_minor : R; bitpos: [26:24]; default: 0;
-         *  BLK_VERSION_MINOR
-         */
-        uint32_t blk_version_minor:3;
-        /** flash_cap : R; bitpos: [29:27]; default: 0;
-         *  Flash capacity
-         */
-        uint32_t flash_cap:3;
-        /** flash_temp : R; bitpos: [31:30]; default: 0;
-         *  Flash temperature
-         */
-        uint32_t flash_temp:2;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_3_reg_t;
-
-/** Type of rd_mac_spi_sys_4 register
- *  BLOCK1 data register 4.
- */
-typedef union {
-    struct {
-        /** flash_vendor : R; bitpos: [2:0]; default: 0;
-         *  Flash vendor
-         */
-        uint32_t flash_vendor:3;
-        /** reserved_1_131 : R; bitpos: [6:3]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_131:4;
-        /** k_rtc_ldo : R; bitpos: [13:7]; default: 0;
-         *  BLOCK1 K_RTC_LDO
-         */
-        uint32_t k_rtc_ldo:7;
-        /** k_dig_ldo : R; bitpos: [20:14]; default: 0;
-         *  BLOCK1 K_DIG_LDO
-         */
-        uint32_t k_dig_ldo:7;
-        /** v_rtc_dbias20 : R; bitpos: [28:21]; default: 0;
-         *  BLOCK1 voltage of rtc dbias20
-         */
-        uint32_t v_rtc_dbias20:8;
-        /** v_dig_dbias20 : R; bitpos: [31:29]; default: 0;
-         *  BLOCK1 voltage of digital dbias20
-         */
-        uint32_t v_dig_dbias20:3;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_4_reg_t;
-
-/** Type of rd_mac_spi_sys_5 register
- *  BLOCK1 data register 5.
- */
-typedef union {
-    struct {
-        /** v_dig_dbias20_1 : R; bitpos: [4:0]; default: 0;
-         *  BLOCK1 voltage of digital dbias20
-         */
-        uint32_t v_dig_dbias20_1:5;
-        /** dig_dbias_hvt : R; bitpos: [9:5]; default: 0;
-         *  BLOCK1 digital dbias when hvt
-         */
-        uint32_t dig_dbias_hvt:5;
-        /** thres_hvt : R; bitpos: [19:10]; default: 0;
-         *  BLOCK1 pvt threshold when hvt
-         */
-        uint32_t thres_hvt:10;
-        /** reserved_1_180 : R; bitpos: [22:20]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_180:3;
-        /** wafer_version_minor_hi : R; bitpos: [23]; default: 0;
-         *  WAFER_VERSION_MINOR most significant bit
-         */
-        uint32_t wafer_version_minor_hi:1;
-        /** wafer_version_major : R; bitpos: [25:24]; default: 0;
-         *  WAFER_VERSION_MAJOR
-         */
-        uint32_t wafer_version_major:2;
-        /** reserved_1_186 : R; bitpos: [31:26]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_186:6;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_5_reg_t;
-
-/** Type of rd_sys_part1_data0 register
- *  Register 0 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Register 1 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Register 2 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Register 3 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Register 4 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** blk_version_major : R; bitpos: [1:0]; default: 0;
-         *  BLK_VERSION_MAJOR of BLOCK2
-         */
-        uint32_t blk_version_major:2;
-        /** reserved_2_130 : R; bitpos: [2]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_130:1;
-        /** temp_calib : R; bitpos: [11:3]; default: 0;
-         *  Temperature calibration data
-         */
-        uint32_t temp_calib:9;
-        /** ocode : R; bitpos: [19:12]; default: 0;
-         *  ADC OCode
-         */
-        uint32_t ocode:8;
-        /** adc1_init_code_atten0 : R; bitpos: [29:20]; default: 0;
-         *  ADC1 init code at atten0
-         */
-        uint32_t adc1_init_code_atten0:10;
-        /** adc1_init_code_atten1 : R; bitpos: [31:30]; default: 0;
-         *  ADC1 init code at atten1
-         */
-        uint32_t adc1_init_code_atten1:2;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Register 5 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_init_code_atten1_1 : R; bitpos: [7:0]; default: 0;
-         *  ADC1 init code at atten1
-         */
-        uint32_t adc1_init_code_atten1_1:8;
-        /** adc1_init_code_atten2 : R; bitpos: [17:8]; default: 0;
-         *  ADC1 init code at atten2
-         */
-        uint32_t adc1_init_code_atten2:10;
-        /** adc1_init_code_atten3 : R; bitpos: [27:18]; default: 0;
-         *  ADC1 init code at atten3
-         */
-        uint32_t adc1_init_code_atten3:10;
-        /** adc1_cal_vol_atten0 : R; bitpos: [31:28]; default: 0;
-         *  ADC1 calibration voltage at atten0
-         */
-        uint32_t adc1_cal_vol_atten0:4;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Register 6 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_cal_vol_atten0_1 : R; bitpos: [5:0]; default: 0;
-         *  ADC1 calibration voltage at atten0
-         */
-        uint32_t adc1_cal_vol_atten0_1:6;
-        /** adc1_cal_vol_atten1 : R; bitpos: [15:6]; default: 0;
-         *  ADC1 calibration voltage at atten1
-         */
-        uint32_t adc1_cal_vol_atten1:10;
-        /** adc1_cal_vol_atten2 : R; bitpos: [25:16]; default: 0;
-         *  ADC1 calibration voltage at atten2
-         */
-        uint32_t adc1_cal_vol_atten2:10;
-        /** adc1_cal_vol_atten3 : R; bitpos: [31:26]; default: 0;
-         *  ADC1 calibration voltage at atten3
-         */
-        uint32_t adc1_cal_vol_atten3:6;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Register 7 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_cal_vol_atten3_1 : R; bitpos: [3:0]; default: 0;
-         *  ADC1 calibration voltage at atten3
-         */
-        uint32_t adc1_cal_vol_atten3_1:4;
-        /** reserved_2_228 : R; bitpos: [31:4]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_228:28;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-/** Type of rd_usr_data0 register
- *  Register 0 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Register 1 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Register 2 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Register 3 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Register 4 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Register 5 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Register 6 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_192:8;
-        /** custom_mac : R; bitpos: [31:8]; default: 0;
-         *  Custom MAC address
-         */
-        uint32_t custom_mac:24;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Register 7 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
-         *  Custom MAC address
-         */
-        uint32_t custom_mac_1:24;
-        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_248:8;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-/** Type of rd_key0_data0 register
- *  Register 0 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Register 1 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Register 2 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Register 3 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Register 4 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Register 5 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Register 6 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Register 7 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-/** Type of rd_key1_data0 register
- *  Register 0 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Register 1 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Register 2 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Register 3 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Register 4 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Register 5 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Register 6 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Register 7 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-/** Type of rd_key2_data0 register
- *  Register 0 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Register 1 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Register 2 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Register 3 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Register 4 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Register 5 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Register 6 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Register 7 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-/** Type of rd_key3_data0 register
- *  Register 0 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Register 1 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Register 2 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Register 3 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Register 4 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Register 5 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Register 6 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Register 7 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-/** Type of rd_key4_data0 register
- *  Register 0 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Register 1 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Register 2 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Register 3 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Register 4 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Register 5 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Register 6 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Register 7 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-/** Type of rd_key5_data0 register
- *  Register 0 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Register 1 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Register 2 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Register 3 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Register 4 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Register 5 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Register 6 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Register 7 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-/** Type of rd_sys_part2_data0 register
- *  Register 0 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 0th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Register 1 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 1st 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Register 2 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 2nd 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Register 3 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 3rd 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Register 4 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 4th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Register 5 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 5th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Register 6 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 6th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Register 7 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 7th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-
-/** Group: Report Register */
-/** Type of rd_repeat_err0 register
- *  Programming error record register 0 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  If any bit in RD_DIS is 1, then it indicates a programming error.
-         */
-        uint32_t rd_dis_err:7;
-        /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0;
-         *  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
-         */
-        uint32_t dis_rtc_ram_boot_err:1;
-        /** dis_icache_err : RO; bitpos: [8]; default: 0;
-         *  If DIS_ICACHE is 1, then it indicates a programming error.
-         */
-        uint32_t dis_icache_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  If DIS_USB_JTAG is 1, then it indicates a programming error.
-         */
-        uint32_t dis_usb_jtag_err:1;
-        /** dis_download_icache_err : RO; bitpos: [10]; default: 0;
-         *  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_icache_err:1;
-        /** dis_usb_device_err : RO; bitpos: [11]; default: 0;
-         *  If DIS_USB_DEVICE is 1, then it indicates a programming error.
-         */
-        uint32_t dis_usb_device_err:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
-         */
-        uint32_t dis_force_download_err:1;
-        /** rpt4_reserved6_err : RO; bitpos: [13]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved6_err:1;
-        /** dis_can_err : RO; bitpos: [14]; default: 0;
-         *  If DIS_CAN is 1, then it indicates a programming error.
-         */
-        uint32_t dis_can_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  If DIS_PAD_JTAG is 1, then it indicates a programming error.
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
-         *  If any bit in USB_DREFH is 1, then it indicates a programming error.
-         */
-        uint32_t usb_drefh_err:2;
-        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
-         *  If any bit in USB_DREFL is 1, then it indicates a programming error.
-         */
-        uint32_t usb_drefl_err:2;
-        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
-         *  If USB_EXCHG_PINS is 1, then it indicates a programming error.
-         */
-        uint32_t usb_exchg_pins_err:1;
-        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
-         *  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_as_gpio_err:1;
-        /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0;
-         *  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
-         */
-        uint32_t btlc_gpio_enable_err:2;
-        /** powerglitch_en_err : RO; bitpos: [29]; default: 0;
-         *  If POWERGLITCH_EN is 1, then it indicates a programming error.
-         */
-        uint32_t powerglitch_en_err:1;
-        /** power_glitch_dsense_err : RO; bitpos: [31:30]; default: 0;
-         *  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
-         */
-        uint32_t power_glitch_dsense_err:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err0_reg_t;
-
-/** Type of rd_repeat_err1 register
- *  Programming error record register 1 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved2_err : RO; bitpos: [15:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved2_err:16;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err1_reg_t;
-
-/** Type of rd_repeat_err2 register
- *  Programming error record register 2 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_5_err:4;
-        /** rpt4_reserved3_err : RO; bitpos: [19:16]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_err:4;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  If SECURE_BOOT_EN is 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        /** rpt4_reserved0_err : RO; bitpos: [27:22]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_err:6;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err2_reg_t;
-
-/** Type of rd_repeat_err3 register
- *  Programming error record register 3 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0;
-         *  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
-         */
-        uint32_t dis_legacy_spi_boot_err:1;
-        /** uart_print_channel_err : RO; bitpos: [2]; default: 0;
-         *  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
-         */
-        uint32_t uart_print_channel_err:1;
-        /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0;
-         *  If FLASH_ECC_MODE is 1, then it indicates a programming error.
-         */
-        uint32_t flash_ecc_mode_err:1;
-        /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
-         */
-        uint32_t dis_usb_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
-         */
-        uint32_t uart_print_control_err:2;
-        /** pin_power_selection_err : RO; bitpos: [8]; default: 0;
-         *  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
-         */
-        uint32_t pin_power_selection_err:1;
-        /** flash_type_err : RO; bitpos: [9]; default: 0;
-         *  If FLASH_TYPE is 1, then it indicates a programming error.
-         */
-        uint32_t flash_type_err:1;
-        /** flash_page_size_err : RO; bitpos: [11:10]; default: 0;
-         *  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
-         */
-        uint32_t flash_page_size_err:2;
-        /** flash_ecc_en_err : RO; bitpos: [12]; default: 0;
-         *  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
-         */
-        uint32_t flash_ecc_en_err:1;
-        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
-         *  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [29:14]; default: 0;
-         *  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
-         */
-        uint32_t secure_version_err:16;
-        /** rpt4_reserved1_err : RO; bitpos: [31:30]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved1_err:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err3_reg_t;
-
-/** Type of rd_repeat_err4 register
- *  Programming error record register 4 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved4_err:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err4_reg_t;
-
-/** Type of rd_rs_err0 register
- *  Programming error record register 0 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t mac_spi_8m_err_num:3;
-        /** reserved_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t reserved_fail:1;
-        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part1_num:3;
-        /** mac_spi_8m_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t mac_spi_8m_fail:1;
-        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t usr_data_err_num:3;
-        /** sys_part1_fail : RO; bitpos: [11]; default: 0;
-         *  0: Means no failure and that the user data is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part1_fail:1;
-        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key0_err_num:3;
-        /** usr_data_fail : RO; bitpos: [15]; default: 0;
-         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
-         *  key0 failed and the number of error bytes is over 6.
-         */
-        uint32_t usr_data_fail:1;
-        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key1_err_num:3;
-        /** key0_fail : RO; bitpos: [19]; default: 0;
-         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
-         *  key1 failed and the number of error bytes is over 6.
-         */
-        uint32_t key0_fail:1;
-        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key2_err_num:3;
-        /** key1_fail : RO; bitpos: [23]; default: 0;
-         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
-         *  key2 failed and the number of error bytes is over 6.
-         */
-        uint32_t key1_fail:1;
-        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key3_err_num:3;
-        /** key2_fail : RO; bitpos: [27]; default: 0;
-         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
-         *  key3 failed and the number of error bytes is over 6.
-         */
-        uint32_t key2_fail:1;
-        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key4_err_num:3;
-        /** key3_fail : RO; bitpos: [31]; default: 0;
-         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
-         *  key4 failed and the number of error bytes is over 6.
-         */
-        uint32_t key3_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_err0_reg_t;
-
-/** Type of rd_rs_err1 register
- *  Programming error record register 1 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key5_err_num:3;
-        /** key4_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t key4_fail:1;
-        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part2_err_num:3;
-        /** key5_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t key5_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_err1_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t efuse_mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t efuse_mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit and force to enable clock signal of eFuse memory.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuraiton register;
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
-         */
-        uint32_t op_code:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/WS/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
-         *  Configures the initial read time of eFuse.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0;
-         *  Indicates the number of error bits during programming BLOCK0.
-         */
-        uint32_t repeat_err_cnt:8;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WO; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 33583616;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0;
-    volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1;
-    volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2;
-    volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3;
-    volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4;
-    volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
-    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
-    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
-    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
-    uint32_t reserved_18c;
-    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
-    uint32_t reserved_194[11];
-    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
-    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    uint32_t reserved_1f8;
-    volatile efuse_date_reg_t date;
-} efuse_dev_t;
-extern efuse_dev_t EFUSE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/extmem_reg.h b/components/soc/esp32c3/include/soc/extmem_reg.h
deleted file mode 100644
index 71ab60f6400..00000000000
--- a/components/soc/esp32c3/include/soc/extmem_reg.h
+++ /dev/null
@@ -1,992 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_EXTMEM_REG_H_
-#define _SOC_EXTMEM_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define EXTMEM_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x000)
-/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to activate the data cache. 0: disable  1: enable*/
-#define EXTMEM_ICACHE_ENABLE  (BIT(0))
-#define EXTMEM_ICACHE_ENABLE_M  (BIT(0))
-#define EXTMEM_ICACHE_ENABLE_V  0x1
-#define EXTMEM_ICACHE_ENABLE_S  0
-
-#define EXTMEM_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x004)
-/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to disable core1 ibus  0: enable  1: disable*/
-#define EXTMEM_ICACHE_SHUT_DBUS  (BIT(1))
-#define EXTMEM_ICACHE_SHUT_DBUS_M  (BIT(1))
-#define EXTMEM_ICACHE_SHUT_DBUS_V  0x1
-#define EXTMEM_ICACHE_SHUT_DBUS_S  1
-/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to disable core0 ibus  0: enable  1: disable*/
-#define EXTMEM_ICACHE_SHUT_IBUS  (BIT(0))
-#define EXTMEM_ICACHE_SHUT_IBUS_M  (BIT(0))
-#define EXTMEM_ICACHE_SHUT_IBUS_V  0x1
-#define EXTMEM_ICACHE_SHUT_IBUS_S  0
-
-#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x008)
-/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to power  icache tag memory up  0: follow rtc_lslp  1: power up*/
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU  (BIT(2))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V  0x1
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S  2
-/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to power  icache tag memory down  0: follow rtc_lslp
-  1: power down*/
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD  (BIT(1))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V  0x1
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S  1
-/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of  icache tag memory.
- 1: close gating  0: open clock gating.*/
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON  (BIT(0))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V  0x1
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S  0
-
-#define EXTMEM_ICACHE_PRELOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x00C)
-/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section of prelock function.*/
-#define EXTMEM_ICACHE_PRELOCK_SCT1_EN  (BIT(1))
-#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V  0x1
-#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S  1
-/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section of prelock function.*/
-#define EXTMEM_ICACHE_PRELOCK_SCT0_EN  (BIT(0))
-#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M  (BIT(0))
-#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V  0x1
-#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S  0
-
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x010)
-/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to configure the first start virtual address
- of data prelock  which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S))
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S  0
-
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x014)
-/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to configure the second start virtual address
- of data prelock  which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S))
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S  0
-
-#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x018)
-/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: The bits are used to configure the first length of data locking
-  which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
-#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE  0x0000FFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S))
-#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V  0xFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S  16
-/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the second length of data locking
-  which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
-#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE  0x0000FFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S))
-#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V  0xFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S  0
-
-#define EXTMEM_ICACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x01C)
-/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to indicate unlock/lock operation is finished.*/
-#define EXTMEM_ICACHE_LOCK_DONE  (BIT(2))
-#define EXTMEM_ICACHE_LOCK_DONE_M  (BIT(2))
-#define EXTMEM_ICACHE_LOCK_DONE_V  0x1
-#define EXTMEM_ICACHE_LOCK_DONE_S  2
-/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable unlock operation. It will be cleared
- by hardware after unlock operation done.*/
-#define EXTMEM_ICACHE_UNLOCK_ENA  (BIT(1))
-#define EXTMEM_ICACHE_UNLOCK_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_UNLOCK_ENA_V  0x1
-#define EXTMEM_ICACHE_UNLOCK_ENA_S  1
-/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable lock operation. It will be cleared
- by hardware after lock operation done.*/
-#define EXTMEM_ICACHE_LOCK_ENA  (BIT(0))
-#define EXTMEM_ICACHE_LOCK_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_LOCK_ENA_V  0x1
-#define EXTMEM_ICACHE_LOCK_ENA_S  0
-
-#define EXTMEM_ICACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x020)
-/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for
- lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/
-#define EXTMEM_ICACHE_LOCK_ADDR  0xFFFFFFFF
-#define EXTMEM_ICACHE_LOCK_ADDR_M  ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S))
-#define EXTMEM_ICACHE_LOCK_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_LOCK_ADDR_S  0
-
-#define EXTMEM_ICACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x024)
-/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the length for lock operations.
- The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
-#define EXTMEM_ICACHE_LOCK_SIZE  0x0000FFFF
-#define EXTMEM_ICACHE_LOCK_SIZE_M  ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S))
-#define EXTMEM_ICACHE_LOCK_SIZE_V  0xFFFF
-#define EXTMEM_ICACHE_LOCK_SIZE_S  0
-
-#define EXTMEM_ICACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x028)
-/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to indicate invalidate operation is finished.*/
-#define EXTMEM_ICACHE_SYNC_DONE  (BIT(1))
-#define EXTMEM_ICACHE_SYNC_DONE_M  (BIT(1))
-#define EXTMEM_ICACHE_SYNC_DONE_V  0x1
-#define EXTMEM_ICACHE_SYNC_DONE_S  1
-/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable invalidate operation. It will be cleared
- by hardware after invalidate operation done.*/
-#define EXTMEM_ICACHE_INVALIDATE_ENA  (BIT(0))
-#define EXTMEM_ICACHE_INVALIDATE_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_INVALIDATE_ENA_V  0x1
-#define EXTMEM_ICACHE_INVALIDATE_ENA_S  0
-
-#define EXTMEM_ICACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x02C)
-/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for
- clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/
-#define EXTMEM_ICACHE_SYNC_ADDR  0xFFFFFFFF
-#define EXTMEM_ICACHE_SYNC_ADDR_M  ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
-#define EXTMEM_ICACHE_SYNC_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_SYNC_ADDR_S  0
-
-#define EXTMEM_ICACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x030)
-/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
-/*description: The bits are used to configure the length for sync operations.
- The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
-#define EXTMEM_ICACHE_SYNC_SIZE  0x007FFFFF
-#define EXTMEM_ICACHE_SYNC_SIZE_M  ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
-#define EXTMEM_ICACHE_SYNC_SIZE_V  0x7FFFFF
-#define EXTMEM_ICACHE_SYNC_SIZE_S  0
-
-#define EXTMEM_ICACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x034)
-/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to configure the direction of preload operation.
- 1: descending  0: ascending.*/
-#define EXTMEM_ICACHE_PRELOAD_ORDER  (BIT(2))
-#define EXTMEM_ICACHE_PRELOAD_ORDER_M  (BIT(2))
-#define EXTMEM_ICACHE_PRELOAD_ORDER_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_ORDER_S  2
-/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to indicate preload operation is finished.*/
-#define EXTMEM_ICACHE_PRELOAD_DONE  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_DONE_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_DONE_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_DONE_S  1
-/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable preload operation. It will be cleared
- by hardware after preload operation done.*/
-#define EXTMEM_ICACHE_PRELOAD_ENA  (BIT(0))
-#define EXTMEM_ICACHE_PRELOAD_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_PRELOAD_ENA_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_ENA_S  0
-
-#define EXTMEM_ICACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x038)
-/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for
- preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/
-#define EXTMEM_ICACHE_PRELOAD_ADDR  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOAD_ADDR_M  ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S))
-#define EXTMEM_ICACHE_PRELOAD_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOAD_ADDR_S  0
-
-#define EXTMEM_ICACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x03C)
-/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the length for preload operation.
- The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
-#define EXTMEM_ICACHE_PRELOAD_SIZE  0x0000FFFF
-#define EXTMEM_ICACHE_PRELOAD_SIZE_M  ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S))
-#define EXTMEM_ICACHE_PRELOAD_SIZE_V  0xFFFF
-#define EXTMEM_ICACHE_PRELOAD_SIZE_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x040)
-/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
-/*description: The bits are used to configure trigger conditions for autoload.
- 0/3: cache miss  1: cache hit  2: both cache miss and hit.*/
-#define EXTMEM_ICACHE_AUTOLOAD_RQST  0x00000003
-#define EXTMEM_ICACHE_AUTOLOAD_RQST_M  ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S))
-#define EXTMEM_ICACHE_AUTOLOAD_RQST_V  0x3
-#define EXTMEM_ICACHE_AUTOLOAD_RQST_S  5
-/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bits are used to configure the direction of autoload. 1:
- descending  0: ascending.*/
-#define EXTMEM_ICACHE_AUTOLOAD_ORDER  (BIT(4))
-#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M  (BIT(4))
-#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S  4
-/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
-/*description: The bit is used to indicate autoload operation is finished.*/
-#define EXTMEM_ICACHE_AUTOLOAD_DONE  (BIT(3))
-#define EXTMEM_ICACHE_AUTOLOAD_DONE_M  (BIT(3))
-#define EXTMEM_ICACHE_AUTOLOAD_DONE_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_DONE_S  3
-/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable and disable autoload operation. It
- is combined with icache_autoload_done. 1: enable  0: disable.*/
-#define EXTMEM_ICACHE_AUTOLOAD_ENA  (BIT(2))
-#define EXTMEM_ICACHE_AUTOLOAD_ENA_M  (BIT(2))
-#define EXTMEM_ICACHE_AUTOLOAD_ENA_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_ENA_S  2
-/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bits are used to enable the second section for autoload operation.*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA  (BIT(1))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S  1
-/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bits are used to enable the first section for autoload operation.*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA  (BIT(0))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x044)
-/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address of the
- first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x048)
-/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: The bits are used to configure the length of the first section
- for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE  0x07FFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V  0x7FFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x04C)
-/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address of the
- second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x050)
-/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: The bits are used to configure the length of the second section
- for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE  0x07FFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V  0x7FFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x054)
-/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */
-/*description: The bits are used to configure the start virtual address of ibus
- to access flash. The register is used to give constraints to ibus access counter.*/
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR  0xFFFFFFFF
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S))
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S  0
-
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x058)
-/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h427FFFFF ; */
-/*description: The bits are used to configure the end virtual address of ibus
- to access flash. The register is used to give constraints to ibus access counter.*/
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR  0xFFFFFFFF
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S  0
-
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x05C)
-/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C000000 ; */
-/*description: The bits are used to configure the start virtual address of dbus
- to access flash. The register is used to give constraints to dbus access counter.*/
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR  0xFFFFFFFF
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S))
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S  0
-
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x060)
-/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C7FFFFF ; */
-/*description: The bits are used to configure the end virtual address of dbus
- to access flash. The register is used to give constraints to dbus access counter.*/
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR  0xFFFFFFFF
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S  0
-
-#define EXTMEM_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x064)
-/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to clear dbus counter.*/
-#define EXTMEM_DBUS_ACS_CNT_CLR  (BIT(1))
-#define EXTMEM_DBUS_ACS_CNT_CLR_M  (BIT(1))
-#define EXTMEM_DBUS_ACS_CNT_CLR_V  0x1
-#define EXTMEM_DBUS_ACS_CNT_CLR_S  1
-/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to clear ibus counter.*/
-#define EXTMEM_IBUS_ACS_CNT_CLR  (BIT(0))
-#define EXTMEM_IBUS_ACS_CNT_CLR_M  (BIT(0))
-#define EXTMEM_IBUS_ACS_CNT_CLR_V  0x1
-#define EXTMEM_IBUS_ACS_CNT_CLR_S  0
-
-#define EXTMEM_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x068)
-/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of the cache miss caused
- by ibus access flash.*/
-#define EXTMEM_IBUS_ACS_MISS_CNT  0xFFFFFFFF
-#define EXTMEM_IBUS_ACS_MISS_CNT_M  ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S))
-#define EXTMEM_IBUS_ACS_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_IBUS_ACS_MISS_CNT_S  0
-
-#define EXTMEM_IBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x06C)
-/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of ibus access flash through icache.*/
-#define EXTMEM_IBUS_ACS_CNT  0xFFFFFFFF
-#define EXTMEM_IBUS_ACS_CNT_M  ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S))
-#define EXTMEM_IBUS_ACS_CNT_V  0xFFFFFFFF
-#define EXTMEM_IBUS_ACS_CNT_S  0
-
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x070)
-/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of the cache miss caused
- by dbus access flash.*/
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT  0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M  ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S))
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S  0
-
-#define EXTMEM_DBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x074)
-/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of dbus access flash through icache.*/
-#define EXTMEM_DBUS_ACS_CNT  0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_CNT_M  ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S))
-#define EXTMEM_DBUS_ACS_CNT_V  0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_CNT_S  0
-
-#define EXTMEM_CACHE_ILG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x078)
-/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by dbus counter overflow.*/
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA  (BIT(8))
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M  (BIT(8))
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V  0x1
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S  8
-/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by ibus counter overflow.*/
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA  (BIT(7))
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M  (BIT(7))
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V  0x1
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S  7
-/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by mmu entry fault.*/
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V  0x1
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S  5
-/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by preload configurations fault.*/
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S  1
-/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by sync configurations fault.*/
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V  0x1
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S  0
-
-#define EXTMEM_CACHE_ILG_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x07C)
-/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by dbus counter overflow.*/
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR  (BIT(8))
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M  (BIT(8))
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V  0x1
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S  8
-/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by ibus counter overflow.*/
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR  (BIT(7))
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M  (BIT(7))
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V  0x1
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S  7
-/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by mmu entry fault.*/
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V  0x1
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S  5
-/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by preload configurations fault.*/
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S  1
-/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by sync configurations fault.*/
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V  0x1
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S  0
-
-#define EXTMEM_CACHE_ILG_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x080)
-/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by dbus access flash miss
- counter overflow.*/
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST  (BIT(10))
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M  (BIT(10))
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V  0x1
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S  10
-/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by dbus access flash/spiram
- counter overflow.*/
-#define EXTMEM_DBUS_ACS_CNT_OVF_ST  (BIT(9))
-#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M  (BIT(9))
-#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V  0x1
-#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S  9
-/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by ibus access flash/spiram
- miss counter overflow.*/
-#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST  (BIT(8))
-#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
-#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V  0x1
-#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S  8
-/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by ibus access flash/spiram
- counter overflow.*/
-#define EXTMEM_IBUS_ACS_CNT_OVF_ST  (BIT(7))
-#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M  (BIT(7))
-#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V  0x1
-#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S  7
-/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by mmu entry fault.*/
-#define EXTMEM_MMU_ENTRY_FAULT_ST  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_ST_M  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_ST_V  0x1
-#define EXTMEM_MMU_ENTRY_FAULT_ST_S  5
-/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by preload configurations fault.*/
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S  1
-/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by sync configurations fault.*/
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V  0x1
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S  0
-
-#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x084)
-/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by dbus trying to write icache*/
-#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA  (BIT(5))
-#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M  (BIT(5))
-#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V  0x1
-#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S  5
-/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by authentication fail.*/
-#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V  0x1
-#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S  4
-/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by cpu access icache while
- the corresponding dbus is disabled which include speculative access.*/
-#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V  0x1
-#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S  3
-/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by authentication fail.*/
-#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V  0x1
-#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S  2
-/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by ibus trying to write icache*/
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V  0x1
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S  1
-/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by cpu access icache while
- the corresponding ibus is disabled which include speculative access.*/
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S  0
-
-#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x088)
-/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by dbus trying to write icache*/
-#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR  (BIT(5))
-#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M  (BIT(5))
-#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V  0x1
-#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S  5
-/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by authentication fail.*/
-#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V  0x1
-#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S  4
-/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by cpu access icache while
- the corresponding dbus is disabled or icache is disabled which include speculative access.*/
-#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V  0x1
-#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S  3
-/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by authentication fail.*/
-#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V  0x1
-#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S  2
-/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by ibus trying to write icache*/
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V  0x1
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S  1
-/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by cpu access icache while
- the corresponding ibus is disabled or icache is disabled which include speculative access.*/
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S  0
-
-#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x08C)
-/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by dbus trying to write icache*/
-#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST  (BIT(5))
-#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M  (BIT(5))
-#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V  0x1
-#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S  5
-/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by authentication fail.*/
-#define EXTMEM_CORE0_DBUS_REJECT_ST  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_ST_M  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_ST_V  0x1
-#define EXTMEM_CORE0_DBUS_REJECT_ST_S  4
-/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by cpu access icache while
- the core0_dbus is disabled or icache is disabled which include speculative access.*/
-#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V  0x1
-#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S  3
-/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by authentication fail.*/
-#define EXTMEM_CORE0_IBUS_REJECT_ST  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_ST_M  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_ST_V  0x1
-#define EXTMEM_CORE0_IBUS_REJECT_ST_S  2
-/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by ibus trying to write icache*/
-#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V  0x1
-#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S  1
-/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by cpu access  icache while
- the core0_ibus is disabled or icache is disabled which include speculative access.*/
-#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V  0x1
-#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S  0
-
-#define EXTMEM_CORE0_DBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x090)
-/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the world of CPU access dbus when
- authentication fail. 0: WORLD0  1: WORLD1*/
-#define EXTMEM_CORE0_DBUS_WORLD  (BIT(3))
-#define EXTMEM_CORE0_DBUS_WORLD_M  (BIT(3))
-#define EXTMEM_CORE0_DBUS_WORLD_V  0x1
-#define EXTMEM_CORE0_DBUS_WORLD_S  3
-/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of CPU access dbus
- when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
-#define EXTMEM_CORE0_DBUS_ATTR  0x00000007
-#define EXTMEM_CORE0_DBUS_ATTR_M  ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
-#define EXTMEM_CORE0_DBUS_ATTR_V  0x7
-#define EXTMEM_CORE0_DBUS_ATTR_S  0
-
-#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x094)
-/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: The bits are used to indicate the virtual address of CPU access
- dbus when authentication fail.*/
-#define EXTMEM_CORE0_DBUS_VADDR  0xFFFFFFFF
-#define EXTMEM_CORE0_DBUS_VADDR_M  ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
-#define EXTMEM_CORE0_DBUS_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CORE0_DBUS_VADDR_S  0
-
-#define EXTMEM_CORE0_IBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x098)
-/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the world of CPU access ibus when
- authentication fail. 0: WORLD0  1: WORLD1*/
-#define EXTMEM_CORE0_IBUS_WORLD  (BIT(3))
-#define EXTMEM_CORE0_IBUS_WORLD_M  (BIT(3))
-#define EXTMEM_CORE0_IBUS_WORLD_V  0x1
-#define EXTMEM_CORE0_IBUS_WORLD_S  3
-/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of CPU access ibus
- when authentication fail. 0: invalidate  1: execute-able  2: read-able*/
-#define EXTMEM_CORE0_IBUS_ATTR  0x00000007
-#define EXTMEM_CORE0_IBUS_ATTR_M  ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S))
-#define EXTMEM_CORE0_IBUS_ATTR_V  0x7
-#define EXTMEM_CORE0_IBUS_ATTR_S  0
-
-#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x09C)
-/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: The bits are used to indicate the virtual address of CPU access
-  ibus when authentication fail.*/
-#define EXTMEM_CORE0_IBUS_VADDR  0xFFFFFFFF
-#define EXTMEM_CORE0_IBUS_VADDR_M  ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
-#define EXTMEM_CORE0_IBUS_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CORE0_IBUS_VADDR_S  0
-
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x0A0)
-/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */
-/*description: The right-most 3 bits are used to indicate the operations which
- cause mmu fault occurrence. 0: default  1: cpu miss  2: preload miss  3: writeback  4: cpu miss evict recovery address  5: load miss evict recovery address  6: external dma tx  7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/
-#define EXTMEM_CACHE_MMU_FAULT_CODE  0x0000000F
-#define EXTMEM_CACHE_MMU_FAULT_CODE_M  ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S))
-#define EXTMEM_CACHE_MMU_FAULT_CODE_V  0xF
-#define EXTMEM_CACHE_MMU_FAULT_CODE_S  10
-/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT  0x000003FF
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M  ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V  0x3FF
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S  0
-
-#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x0A4)
-/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to indicate the virtual address which cause mmu fault..*/
-#define EXTMEM_CACHE_MMU_FAULT_VADDR  0xFFFFFFFF
-#define EXTMEM_CACHE_MMU_FAULT_VADDR_M  ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
-#define EXTMEM_CACHE_MMU_FAULT_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CACHE_MMU_FAULT_VADDR_S  0
-
-#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0A8)
-/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable wrap around mode when read data from flash.*/
-#define EXTMEM_CACHE_FLASH_WRAP_AROUND  (BIT(0))
-#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
-#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V  0x1
-#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S  0
-
-#define EXTMEM_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0AC)
-/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power up*/
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PU  (BIT(2))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M  (BIT(2))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V  0x1
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S  2
-/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power down*/
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PD  (BIT(1))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M  (BIT(1))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V  0x1
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S  1
-/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable clock gating to save power when access
- mmu memory  0: enable  1: disable*/
-#define EXTMEM_CACHE_MMU_MEM_FORCE_ON  (BIT(0))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V  0x1
-#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S  0
-
-#define EXTMEM_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x0B0)
-/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */
-/*description: The bit is used to indicate whether  icache main fsm is in idle
- state or not. 1: in idle state   0: not in idle state*/
-#define EXTMEM_ICACHE_STATE  0x00000FFF
-#define EXTMEM_ICACHE_STATE_M  ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
-#define EXTMEM_ICACHE_STATE_V  0xFFF
-#define EXTMEM_ICACHE_STATE_S  0
-
-#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0x0B4)
-/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Reserved.*/
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT  (BIT(1))
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S  1
-/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Reserved.*/
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT  (BIT(0))
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V  0x1
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S  0
-
-#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0x0B8)
-/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of external memory encrypt
- and decrypt clock. 1: close gating  0: open clock gating.*/
-#define EXTMEM_CLK_FORCE_ON_CRYPT  (BIT(2))
-#define EXTMEM_CLK_FORCE_ON_CRYPT_M  (BIT(2))
-#define EXTMEM_CLK_FORCE_ON_CRYPT_V  0x1
-#define EXTMEM_CLK_FORCE_ON_CRYPT_S  2
-/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of automatic crypt clock.
- 1: close gating  0: open clock gating.*/
-#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT  (BIT(1))
-#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M  (BIT(1))
-#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V  0x1
-#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S  1
-/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of manual crypt clock.
- 1: close gating  0: open clock gating.*/
-#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT  (BIT(0))
-#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M  (BIT(0))
-#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V  0x1
-#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S  0
-
-#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0BC)
-/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to clear the interrupt by  icache pre-load done.*/
-#define EXTMEM_ICACHE_PRELOAD_INT_CLR  (BIT(2))
-#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
-#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S  2
-/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt by  icache pre-load done.*/
-#define EXTMEM_ICACHE_PRELOAD_INT_ENA  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S  1
-/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the interrupt by  icache pre-load done.*/
-#define EXTMEM_ICACHE_PRELOAD_INT_ST  (BIT(0))
-#define EXTMEM_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
-#define EXTMEM_ICACHE_PRELOAD_INT_ST_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_INT_ST_S  0
-
-#define EXTMEM_CACHE_SYNC_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0C0)
-/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to clear the interrupt by  icache sync done.*/
-#define EXTMEM_ICACHE_SYNC_INT_CLR  (BIT(2))
-#define EXTMEM_ICACHE_SYNC_INT_CLR_M  (BIT(2))
-#define EXTMEM_ICACHE_SYNC_INT_CLR_V  0x1
-#define EXTMEM_ICACHE_SYNC_INT_CLR_S  2
-/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt by  icache sync done.*/
-#define EXTMEM_ICACHE_SYNC_INT_ENA  (BIT(1))
-#define EXTMEM_ICACHE_SYNC_INT_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_SYNC_INT_ENA_V  0x1
-#define EXTMEM_ICACHE_SYNC_INT_ENA_S  1
-/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the interrupt by  icache sync done.*/
-#define EXTMEM_ICACHE_SYNC_INT_ST  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_INT_ST_M  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_INT_ST_V  0x1
-#define EXTMEM_ICACHE_SYNC_INT_ST_S  0
-
-#define EXTMEM_CACHE_MMU_OWNER_REG          (DR_REG_EXTMEM_BASE + 0x0C4)
-/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus  bit1/bit3: dbus*/
-#define EXTMEM_CACHE_MMU_OWNER  0x0000000F
-#define EXTMEM_CACHE_MMU_OWNER_M  ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
-#define EXTMEM_CACHE_MMU_OWNER_V  0xF
-#define EXTMEM_CACHE_MMU_OWNER_S  0
-
-#define EXTMEM_CACHE_CONF_MISC_REG          (DR_REG_EXTMEM_BASE + 0x0C8)
-/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to enable cache trace function.*/
-#define EXTMEM_CACHE_TRACE_ENA  (BIT(2))
-#define EXTMEM_CACHE_TRACE_ENA_M  (BIT(2))
-#define EXTMEM_CACHE_TRACE_ENA_V  0x1
-#define EXTMEM_CACHE_TRACE_ENA_S  2
-/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to disable checking mmu entry fault by sync operation.*/
-#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT  (BIT(1))
-#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M  (BIT(1))
-#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V  0x1
-#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S  1
-/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to disable checking mmu entry fault by preload operation.*/
-#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT  (BIT(0))
-#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M  (BIT(0))
-#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V  0x1
-#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S  0
-
-#define EXTMEM_ICACHE_FREEZE_REG          (DR_REG_EXTMEM_BASE + 0x0CC)
-/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to indicate icache freeze success*/
-#define EXTMEM_ICACHE_FREEZE_DONE  (BIT(2))
-#define EXTMEM_ICACHE_FREEZE_DONE_M  (BIT(2))
-#define EXTMEM_ICACHE_FREEZE_DONE_V  0x1
-#define EXTMEM_ICACHE_FREEZE_DONE_S  2
-/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to configure freeze mode  0:  assert busy if
- CPU miss 1: assert hit if CPU miss*/
-#define EXTMEM_ICACHE_FREEZE_MODE  (BIT(1))
-#define EXTMEM_ICACHE_FREEZE_MODE_M  (BIT(1))
-#define EXTMEM_ICACHE_FREEZE_MODE_V  0x1
-#define EXTMEM_ICACHE_FREEZE_MODE_S  1
-/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable icache freeze mode*/
-#define EXTMEM_ICACHE_FREEZE_ENA  (BIT(0))
-#define EXTMEM_ICACHE_FREEZE_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_FREEZE_ENA_V  0x1
-#define EXTMEM_ICACHE_FREEZE_ENA_S  0
-
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG          (DR_REG_EXTMEM_BASE + 0x0D0)
-/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to activate icache atomic operation protection.
- In this case  sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA  (BIT(0))
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V  0x1
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S  0
-
-#define EXTMEM_CACHE_REQUEST_REG          (DR_REG_EXTMEM_BASE + 0x0D4)
-/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to disable request recording which could cause performance issue*/
-#define EXTMEM_CACHE_REQUEST_BYPASS  (BIT(0))
-#define EXTMEM_CACHE_REQUEST_BYPASS_M  (BIT(0))
-#define EXTMEM_CACHE_REQUEST_BYPASS_V  0x1
-#define EXTMEM_CACHE_REQUEST_BYPASS_S  0
-
-#define EXTMEM_IBUS_PMS_TBL_LOCK_REG          (DR_REG_EXTMEM_BASE + 0x0D8)
-/* EXTMEM_IBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to configure the ibus permission control section boundary0*/
-#define EXTMEM_IBUS_PMS_LOCK  (BIT(0))
-#define EXTMEM_IBUS_PMS_LOCK_M  (BIT(0))
-#define EXTMEM_IBUS_PMS_LOCK_V  0x1
-#define EXTMEM_IBUS_PMS_LOCK_S  0
-
-#define EXTMEM_IBUS_PMS_TBL_BOUNDARY0_REG          (DR_REG_EXTMEM_BASE + 0x0DC)
-/* EXTMEM_IBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: The bit is used to configure the ibus permission control section boundary0*/
-#define EXTMEM_IBUS_PMS_BOUNDARY0  0x00000FFF
-#define EXTMEM_IBUS_PMS_BOUNDARY0_M  ((EXTMEM_IBUS_PMS_BOUNDARY0_V)<<(EXTMEM_IBUS_PMS_BOUNDARY0_S))
-#define EXTMEM_IBUS_PMS_BOUNDARY0_V  0xFFF
-#define EXTMEM_IBUS_PMS_BOUNDARY0_S  0
-
-#define EXTMEM_IBUS_PMS_TBL_BOUNDARY1_REG          (DR_REG_EXTMEM_BASE + 0x0E0)
-/* EXTMEM_IBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
-/*description: The bit is used to configure the ibus permission control section boundary1*/
-#define EXTMEM_IBUS_PMS_BOUNDARY1  0x00000FFF
-#define EXTMEM_IBUS_PMS_BOUNDARY1_M  ((EXTMEM_IBUS_PMS_BOUNDARY1_V)<<(EXTMEM_IBUS_PMS_BOUNDARY1_S))
-#define EXTMEM_IBUS_PMS_BOUNDARY1_V  0xFFF
-#define EXTMEM_IBUS_PMS_BOUNDARY1_S  0
-
-#define EXTMEM_IBUS_PMS_TBL_BOUNDARY2_REG          (DR_REG_EXTMEM_BASE + 0x0E4)
-/* EXTMEM_IBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
-/*description: The bit is used to configure the ibus permission control section boundary2*/
-#define EXTMEM_IBUS_PMS_BOUNDARY2  0x00000FFF
-#define EXTMEM_IBUS_PMS_BOUNDARY2_M  ((EXTMEM_IBUS_PMS_BOUNDARY2_V)<<(EXTMEM_IBUS_PMS_BOUNDARY2_S))
-#define EXTMEM_IBUS_PMS_BOUNDARY2_V  0xFFF
-#define EXTMEM_IBUS_PMS_BOUNDARY2_S  0
-
-#define EXTMEM_IBUS_PMS_TBL_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x0E8)
-/* EXTMEM_IBUS_PMS_SCT2_ATTR : R/W ;bitpos:[7:4] ;default: 4'hF ; */
-/*description: The bit is used to configure attribute of the ibus permission
- control section2  bit0: fetch in world0  bit1: load in world0  bit2: fetch in world1  bit3: load in world1*/
-#define EXTMEM_IBUS_PMS_SCT2_ATTR  0x0000000F
-#define EXTMEM_IBUS_PMS_SCT2_ATTR_M  ((EXTMEM_IBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT2_ATTR_S))
-#define EXTMEM_IBUS_PMS_SCT2_ATTR_V  0xF
-#define EXTMEM_IBUS_PMS_SCT2_ATTR_S  4
-/* EXTMEM_IBUS_PMS_SCT1_ATTR : R/W ;bitpos:[3:0] ;default: 4'hF ; */
-/*description: The bit is used to configure attribute of the ibus permission
- control section1  bit0: fetch in world0  bit1: load in world0  bit2: fetch in world1  bit3: load in world1*/
-#define EXTMEM_IBUS_PMS_SCT1_ATTR  0x0000000F
-#define EXTMEM_IBUS_PMS_SCT1_ATTR_M  ((EXTMEM_IBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT1_ATTR_S))
-#define EXTMEM_IBUS_PMS_SCT1_ATTR_V  0xF
-#define EXTMEM_IBUS_PMS_SCT1_ATTR_S  0
-
-#define EXTMEM_DBUS_PMS_TBL_LOCK_REG          (DR_REG_EXTMEM_BASE + 0x0EC)
-/* EXTMEM_DBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to configure the ibus permission control section boundary0*/
-#define EXTMEM_DBUS_PMS_LOCK  (BIT(0))
-#define EXTMEM_DBUS_PMS_LOCK_M  (BIT(0))
-#define EXTMEM_DBUS_PMS_LOCK_V  0x1
-#define EXTMEM_DBUS_PMS_LOCK_S  0
-
-#define EXTMEM_DBUS_PMS_TBL_BOUNDARY0_REG          (DR_REG_EXTMEM_BASE + 0x0F0)
-/* EXTMEM_DBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
-/*description: The bit is used to configure the dbus permission control section boundary0*/
-#define EXTMEM_DBUS_PMS_BOUNDARY0  0x00000FFF
-#define EXTMEM_DBUS_PMS_BOUNDARY0_M  ((EXTMEM_DBUS_PMS_BOUNDARY0_V)<<(EXTMEM_DBUS_PMS_BOUNDARY0_S))
-#define EXTMEM_DBUS_PMS_BOUNDARY0_V  0xFFF
-#define EXTMEM_DBUS_PMS_BOUNDARY0_S  0
-
-#define EXTMEM_DBUS_PMS_TBL_BOUNDARY1_REG          (DR_REG_EXTMEM_BASE + 0x0F4)
-/* EXTMEM_DBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
-/*description: The bit is used to configure the dbus permission control section boundary1*/
-#define EXTMEM_DBUS_PMS_BOUNDARY1  0x00000FFF
-#define EXTMEM_DBUS_PMS_BOUNDARY1_M  ((EXTMEM_DBUS_PMS_BOUNDARY1_V)<<(EXTMEM_DBUS_PMS_BOUNDARY1_S))
-#define EXTMEM_DBUS_PMS_BOUNDARY1_V  0xFFF
-#define EXTMEM_DBUS_PMS_BOUNDARY1_S  0
-
-#define EXTMEM_DBUS_PMS_TBL_BOUNDARY2_REG          (DR_REG_EXTMEM_BASE + 0x0F8)
-/* EXTMEM_DBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
-/*description: The bit is used to configure the dbus permission control section boundary2*/
-#define EXTMEM_DBUS_PMS_BOUNDARY2  0x00000FFF
-#define EXTMEM_DBUS_PMS_BOUNDARY2_M  ((EXTMEM_DBUS_PMS_BOUNDARY2_V)<<(EXTMEM_DBUS_PMS_BOUNDARY2_S))
-#define EXTMEM_DBUS_PMS_BOUNDARY2_V  0xFFF
-#define EXTMEM_DBUS_PMS_BOUNDARY2_S  0
-
-#define EXTMEM_DBUS_PMS_TBL_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x0FC)
-/* EXTMEM_DBUS_PMS_SCT2_ATTR : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
-/*description: The bit is used to configure attribute of the dbus permission
- control section2  bit0: load in world0  bit2: load in world1*/
-#define EXTMEM_DBUS_PMS_SCT2_ATTR  0x00000003
-#define EXTMEM_DBUS_PMS_SCT2_ATTR_M  ((EXTMEM_DBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT2_ATTR_S))
-#define EXTMEM_DBUS_PMS_SCT2_ATTR_V  0x3
-#define EXTMEM_DBUS_PMS_SCT2_ATTR_S  2
-/* EXTMEM_DBUS_PMS_SCT1_ATTR : R/W ;bitpos:[1:0] ;default: 2'd3 ; */
-/*description: The bit is used to configure attribute of the dbus permission
- control section1  bit0: load in world0  bit2: load in world1*/
-#define EXTMEM_DBUS_PMS_SCT1_ATTR  0x00000003
-#define EXTMEM_DBUS_PMS_SCT1_ATTR_M  ((EXTMEM_DBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT1_ATTR_S))
-#define EXTMEM_DBUS_PMS_SCT1_ATTR_V  0x3
-#define EXTMEM_DBUS_PMS_SCT1_ATTR_S  0
-
-#define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x100)
-/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Reserved.*/
-#define EXTMEM_CLK_EN  (BIT(0))
-#define EXTMEM_CLK_EN_M  (BIT(0))
-#define EXTMEM_CLK_EN_V  0x1
-#define EXTMEM_CLK_EN_S  0
-
-#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
-/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007160 ; */
-/*description: Reserved.*/
-#define EXTMEM_DATE  0x0FFFFFFF
-#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
-#define EXTMEM_DATE_V  0xFFFFFFF
-#define EXTMEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_EXTMEM_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/gpio_reg.h b/components/soc/esp32c3/include/soc/gpio_reg.h
deleted file mode 100644
index a674277f994..00000000000
--- a/components/soc/esp32c3/include/soc/gpio_reg.h
+++ /dev/null
@@ -1,4588 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_REG_H_
-#define _SOC_GPIO_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define GPIO_PIN_CONFIG_MSB                    12
-#define GPIO_PIN_CONFIG_LSB                     11
-#define GPIO_PIN_CONFIG_MASK                   0x00001800
-#define GPIO_PIN_CONFIG_GET(x)                 (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
-#define GPIO_PIN_CONFIG_SET(x)                  (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
-
-#define GPIO_WAKEUP_ENABLE                     1
-#define GPIO_WAKEUP_DISABLE                    (~GPIO_WAKEUP_ENABLE)
-#define GPIO_PIN_WAKEUP_ENABLE_MSB             10
-#define GPIO_PIN_WAKEUP_ENABLE_LSB              10
-#define GPIO_PIN_WAKEUP_ENABLE_MASK            0x00000400
-#define GPIO_PIN_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
-
-#define GPIO_PIN_INT_TYPE_MASK                 0x380
-#define GPIO_PIN_INT_TYPE_MSB                  9
-#define GPIO_PIN_INT_TYPE_LSB                  7
-#define GPIO_PIN_INT_TYPE_GET(x)               (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
-#define GPIO_PIN_INT_TYPE_SET(x)               (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
-
-#define GPIO_PAD_DRIVER_ENABLE                 1
-#define GPIO_PAD_DRIVER_DISABLE                        (~GPIO_PAD_DRIVER_ENABLE)
-#define GPIO_PIN_PAD_DRIVER_MSB                        2
-#define GPIO_PIN_PAD_DRIVER_LSB                        2
-#define GPIO_PIN_PAD_DRIVER_MASK               0x00000004
-#define GPIO_PIN_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
-#define GPIO_PIN_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
-
-#define GPIO_BT_SELECT_REG          (DR_REG_GPIO_BASE + 0x0)
-/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define GPIO_BT_SEL  0xFFFFFFFF
-#define GPIO_BT_SEL_M  ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
-#define GPIO_BT_SEL_V  0xFFFFFFFF
-#define GPIO_BT_SEL_S  0
-
-#define GPIO_OUT_REG          (DR_REG_GPIO_BASE + 0x4)
-/* GPIO_OUT_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_OUT_DATA  0x03FFFFFF
-#define GPIO_OUT_DATA_M  ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
-#define GPIO_OUT_DATA_V  0x3FFFFFF
-#define GPIO_OUT_DATA_S  0
-
-#define GPIO_OUT_W1TS_REG          (DR_REG_GPIO_BASE + 0x8)
-/* GPIO_OUT_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_OUT_W1TS  0x03FFFFFF
-#define GPIO_OUT_W1TS_M  ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S))
-#define GPIO_OUT_W1TS_V  0x3FFFFFF
-#define GPIO_OUT_W1TS_S  0
-
-#define GPIO_OUT_W1TC_REG          (DR_REG_GPIO_BASE + 0xC)
-/* GPIO_OUT_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_OUT_W1TC  0x03FFFFFF
-#define GPIO_OUT_W1TC_M  ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S))
-#define GPIO_OUT_W1TC_V  0x3FFFFFF
-#define GPIO_OUT_W1TC_S  0
-
-#define GPIO_SDIO_SELECT_REG          (DR_REG_GPIO_BASE + 0x1C)
-/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SDIO_SEL  0x000000FF
-#define GPIO_SDIO_SEL_M  ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
-#define GPIO_SDIO_SEL_V  0xFF
-#define GPIO_SDIO_SEL_S  0
-
-#define GPIO_ENABLE_REG          (DR_REG_GPIO_BASE + 0x20)
-/* GPIO_ENABLE_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_ENABLE_DATA  0x03FFFFFF
-#define GPIO_ENABLE_DATA_M  ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
-#define GPIO_ENABLE_DATA_V  0x3FFFFFF
-#define GPIO_ENABLE_DATA_S  0
-
-#define GPIO_ENABLE_W1TS_REG          (DR_REG_GPIO_BASE + 0x24)
-/* GPIO_ENABLE_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_ENABLE_W1TS  0x03FFFFFF
-#define GPIO_ENABLE_W1TS_M  ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S))
-#define GPIO_ENABLE_W1TS_V  0x3FFFFFF
-#define GPIO_ENABLE_W1TS_S  0
-
-#define GPIO_ENABLE_W1TC_REG          (DR_REG_GPIO_BASE + 0x28)
-/* GPIO_ENABLE_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_ENABLE_W1TC  0x03FFFFFF
-#define GPIO_ENABLE_W1TC_M  ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S))
-#define GPIO_ENABLE_W1TC_V  0x3FFFFFF
-#define GPIO_ENABLE_W1TC_S  0
-
-#define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x38)
-/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
-/*description: */
-#define GPIO_STRAPPING  0x0000FFFF
-#define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
-#define GPIO_STRAPPING_V  0xFFFF
-#define GPIO_STRAPPING_S  0
-
-#define GPIO_IN_REG          (DR_REG_GPIO_BASE + 0x3C)
-/* GPIO_IN_DATA : RO ;bitpos:[25:0] ;default:  ; */
-/*description: */
-#define GPIO_IN_DATA  0x03FFFFFF
-#define GPIO_IN_DATA_M  ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
-#define GPIO_IN_DATA_V  0x3FFFFFF
-#define GPIO_IN_DATA_S  0
-
-#define GPIO_STATUS_REG          (DR_REG_GPIO_BASE + 0x44)
-/* GPIO_STATUS_INT : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_STATUS_INT  0x03FFFFFF
-#define GPIO_STATUS_INT_M  ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
-#define GPIO_STATUS_INT_V  0x3FFFFFF
-#define GPIO_STATUS_INT_S  0
-
-#define GPIO_STATUS_W1TS_REG          (DR_REG_GPIO_BASE + 0x48)
-/* GPIO_STATUS_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_STATUS_W1TS  0x03FFFFFF
-#define GPIO_STATUS_W1TS_M  ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S))
-#define GPIO_STATUS_W1TS_V  0x3FFFFFF
-#define GPIO_STATUS_W1TS_S  0
-
-#define GPIO_STATUS_W1TC_REG          (DR_REG_GPIO_BASE + 0x4C)
-/* GPIO_STATUS_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_STATUS_W1TC  0x03FFFFFF
-#define GPIO_STATUS_W1TC_M  ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S))
-#define GPIO_STATUS_W1TC_V  0x3FFFFFF
-#define GPIO_STATUS_W1TC_S  0
-
-#define GPIO_PCPU_INT_REG          (DR_REG_GPIO_BASE + 0x5C)
-/* GPIO_PROCPU_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_PROCPU_INT  0x03FFFFFF
-#define GPIO_PROCPU_INT_M  ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
-#define GPIO_PROCPU_INT_V  0x3FFFFFF
-#define GPIO_PROCPU_INT_S  0
-
-#define GPIO_PCPU_NMI_INT_REG          (DR_REG_GPIO_BASE + 0x60)
-/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_PROCPU_NMI_INT  0x03FFFFFF
-#define GPIO_PROCPU_NMI_INT_M  ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
-#define GPIO_PROCPU_NMI_INT_V  0x3FFFFFF
-#define GPIO_PROCPU_NMI_INT_S  0
-
-#define GPIO_CPUSDIO_INT_REG          (DR_REG_GPIO_BASE + 0x64)
-/* GPIO_SDIO_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_SDIO_INT  0x03FFFFFF
-#define GPIO_SDIO_INT_M  ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
-#define GPIO_SDIO_INT_V  0x3FFFFFF
-#define GPIO_SDIO_INT_S  0
-
-#define GPIO_PIN0_REG          (DR_REG_GPIO_BASE + 0x74)
-/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN0_INT_ENA  0x0000001F
-#define GPIO_PIN0_INT_ENA_M  ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
-#define GPIO_PIN0_INT_ENA_V  0x1F
-#define GPIO_PIN0_INT_ENA_S  13
-/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN0_CONFIG  0x00000003
-#define GPIO_PIN0_CONFIG_M  ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
-#define GPIO_PIN0_CONFIG_V  0x3
-#define GPIO_PIN0_CONFIG_S  11
-/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN0_WAKEUP_ENABLE_S  10
-/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN0_INT_TYPE  0x00000007
-#define GPIO_PIN0_INT_TYPE_M  ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
-#define GPIO_PIN0_INT_TYPE_V  0x7
-#define GPIO_PIN0_INT_TYPE_S  7
-/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN0_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN0_SYNC1_BYPASS_M  ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
-#define GPIO_PIN0_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN0_SYNC1_BYPASS_S  3
-/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN0_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_V  0x1
-#define GPIO_PIN0_PAD_DRIVER_S  2
-/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN0_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN0_SYNC2_BYPASS_M  ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S))
-#define GPIO_PIN0_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN0_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN1_REG          (DR_REG_GPIO_BASE + 0x78)
-/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN1_INT_ENA  0x0000001F
-#define GPIO_PIN1_INT_ENA_M  ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
-#define GPIO_PIN1_INT_ENA_V  0x1F
-#define GPIO_PIN1_INT_ENA_S  13
-/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN1_CONFIG  0x00000003
-#define GPIO_PIN1_CONFIG_M  ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
-#define GPIO_PIN1_CONFIG_V  0x3
-#define GPIO_PIN1_CONFIG_S  11
-/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN1_WAKEUP_ENABLE_S  10
-/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN1_INT_TYPE  0x00000007
-#define GPIO_PIN1_INT_TYPE_M  ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
-#define GPIO_PIN1_INT_TYPE_V  0x7
-#define GPIO_PIN1_INT_TYPE_S  7
-/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN1_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN1_SYNC1_BYPASS_M  ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S))
-#define GPIO_PIN1_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN1_SYNC1_BYPASS_S  3
-/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN1_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_V  0x1
-#define GPIO_PIN1_PAD_DRIVER_S  2
-/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN1_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN1_SYNC2_BYPASS_M  ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S))
-#define GPIO_PIN1_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN1_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN2_REG          (DR_REG_GPIO_BASE + 0x7C)
-/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN2_INT_ENA  0x0000001F
-#define GPIO_PIN2_INT_ENA_M  ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
-#define GPIO_PIN2_INT_ENA_V  0x1F
-#define GPIO_PIN2_INT_ENA_S  13
-/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN2_CONFIG  0x00000003
-#define GPIO_PIN2_CONFIG_M  ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
-#define GPIO_PIN2_CONFIG_V  0x3
-#define GPIO_PIN2_CONFIG_S  11
-/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN2_WAKEUP_ENABLE_S  10
-/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN2_INT_TYPE  0x00000007
-#define GPIO_PIN2_INT_TYPE_M  ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
-#define GPIO_PIN2_INT_TYPE_V  0x7
-#define GPIO_PIN2_INT_TYPE_S  7
-/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN2_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN2_SYNC1_BYPASS_M  ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S))
-#define GPIO_PIN2_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN2_SYNC1_BYPASS_S  3
-/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN2_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_V  0x1
-#define GPIO_PIN2_PAD_DRIVER_S  2
-/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN2_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN2_SYNC2_BYPASS_M  ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S))
-#define GPIO_PIN2_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN2_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN3_REG          (DR_REG_GPIO_BASE + 0x80)
-/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN3_INT_ENA  0x0000001F
-#define GPIO_PIN3_INT_ENA_M  ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
-#define GPIO_PIN3_INT_ENA_V  0x1F
-#define GPIO_PIN3_INT_ENA_S  13
-/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN3_CONFIG  0x00000003
-#define GPIO_PIN3_CONFIG_M  ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
-#define GPIO_PIN3_CONFIG_V  0x3
-#define GPIO_PIN3_CONFIG_S  11
-/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN3_WAKEUP_ENABLE_S  10
-/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN3_INT_TYPE  0x00000007
-#define GPIO_PIN3_INT_TYPE_M  ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
-#define GPIO_PIN3_INT_TYPE_V  0x7
-#define GPIO_PIN3_INT_TYPE_S  7
-/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN3_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN3_SYNC1_BYPASS_M  ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S))
-#define GPIO_PIN3_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN3_SYNC1_BYPASS_S  3
-/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN3_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_V  0x1
-#define GPIO_PIN3_PAD_DRIVER_S  2
-/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN3_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN3_SYNC2_BYPASS_M  ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S))
-#define GPIO_PIN3_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN3_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN4_REG          (DR_REG_GPIO_BASE + 0x84)
-/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN4_INT_ENA  0x0000001F
-#define GPIO_PIN4_INT_ENA_M  ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
-#define GPIO_PIN4_INT_ENA_V  0x1F
-#define GPIO_PIN4_INT_ENA_S  13
-/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN4_CONFIG  0x00000003
-#define GPIO_PIN4_CONFIG_M  ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
-#define GPIO_PIN4_CONFIG_V  0x3
-#define GPIO_PIN4_CONFIG_S  11
-/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN4_WAKEUP_ENABLE_S  10
-/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN4_INT_TYPE  0x00000007
-#define GPIO_PIN4_INT_TYPE_M  ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
-#define GPIO_PIN4_INT_TYPE_V  0x7
-#define GPIO_PIN4_INT_TYPE_S  7
-/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN4_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN4_SYNC1_BYPASS_M  ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S))
-#define GPIO_PIN4_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN4_SYNC1_BYPASS_S  3
-/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN4_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_V  0x1
-#define GPIO_PIN4_PAD_DRIVER_S  2
-/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN4_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN4_SYNC2_BYPASS_M  ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S))
-#define GPIO_PIN4_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN4_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN5_REG          (DR_REG_GPIO_BASE + 0x88)
-/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN5_INT_ENA  0x0000001F
-#define GPIO_PIN5_INT_ENA_M  ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
-#define GPIO_PIN5_INT_ENA_V  0x1F
-#define GPIO_PIN5_INT_ENA_S  13
-/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN5_CONFIG  0x00000003
-#define GPIO_PIN5_CONFIG_M  ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
-#define GPIO_PIN5_CONFIG_V  0x3
-#define GPIO_PIN5_CONFIG_S  11
-/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN5_WAKEUP_ENABLE_S  10
-/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN5_INT_TYPE  0x00000007
-#define GPIO_PIN5_INT_TYPE_M  ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
-#define GPIO_PIN5_INT_TYPE_V  0x7
-#define GPIO_PIN5_INT_TYPE_S  7
-/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN5_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN5_SYNC1_BYPASS_M  ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S))
-#define GPIO_PIN5_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN5_SYNC1_BYPASS_S  3
-/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN5_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_V  0x1
-#define GPIO_PIN5_PAD_DRIVER_S  2
-/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN5_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN5_SYNC2_BYPASS_M  ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S))
-#define GPIO_PIN5_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN5_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN6_REG          (DR_REG_GPIO_BASE + 0x8C)
-/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN6_INT_ENA  0x0000001F
-#define GPIO_PIN6_INT_ENA_M  ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
-#define GPIO_PIN6_INT_ENA_V  0x1F
-#define GPIO_PIN6_INT_ENA_S  13
-/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN6_CONFIG  0x00000003
-#define GPIO_PIN6_CONFIG_M  ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
-#define GPIO_PIN6_CONFIG_V  0x3
-#define GPIO_PIN6_CONFIG_S  11
-/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN6_WAKEUP_ENABLE_S  10
-/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN6_INT_TYPE  0x00000007
-#define GPIO_PIN6_INT_TYPE_M  ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
-#define GPIO_PIN6_INT_TYPE_V  0x7
-#define GPIO_PIN6_INT_TYPE_S  7
-/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN6_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN6_SYNC1_BYPASS_M  ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S))
-#define GPIO_PIN6_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN6_SYNC1_BYPASS_S  3
-/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN6_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_V  0x1
-#define GPIO_PIN6_PAD_DRIVER_S  2
-/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN6_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN6_SYNC2_BYPASS_M  ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S))
-#define GPIO_PIN6_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN6_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN7_REG          (DR_REG_GPIO_BASE + 0x90)
-/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN7_INT_ENA  0x0000001F
-#define GPIO_PIN7_INT_ENA_M  ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
-#define GPIO_PIN7_INT_ENA_V  0x1F
-#define GPIO_PIN7_INT_ENA_S  13
-/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN7_CONFIG  0x00000003
-#define GPIO_PIN7_CONFIG_M  ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
-#define GPIO_PIN7_CONFIG_V  0x3
-#define GPIO_PIN7_CONFIG_S  11
-/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN7_WAKEUP_ENABLE_S  10
-/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN7_INT_TYPE  0x00000007
-#define GPIO_PIN7_INT_TYPE_M  ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
-#define GPIO_PIN7_INT_TYPE_V  0x7
-#define GPIO_PIN7_INT_TYPE_S  7
-/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN7_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN7_SYNC1_BYPASS_M  ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S))
-#define GPIO_PIN7_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN7_SYNC1_BYPASS_S  3
-/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN7_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_V  0x1
-#define GPIO_PIN7_PAD_DRIVER_S  2
-/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN7_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN7_SYNC2_BYPASS_M  ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S))
-#define GPIO_PIN7_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN7_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN8_REG          (DR_REG_GPIO_BASE + 0x94)
-/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN8_INT_ENA  0x0000001F
-#define GPIO_PIN8_INT_ENA_M  ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
-#define GPIO_PIN8_INT_ENA_V  0x1F
-#define GPIO_PIN8_INT_ENA_S  13
-/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN8_CONFIG  0x00000003
-#define GPIO_PIN8_CONFIG_M  ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
-#define GPIO_PIN8_CONFIG_V  0x3
-#define GPIO_PIN8_CONFIG_S  11
-/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN8_WAKEUP_ENABLE_S  10
-/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN8_INT_TYPE  0x00000007
-#define GPIO_PIN8_INT_TYPE_M  ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
-#define GPIO_PIN8_INT_TYPE_V  0x7
-#define GPIO_PIN8_INT_TYPE_S  7
-/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN8_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN8_SYNC1_BYPASS_M  ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S))
-#define GPIO_PIN8_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN8_SYNC1_BYPASS_S  3
-/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN8_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_V  0x1
-#define GPIO_PIN8_PAD_DRIVER_S  2
-/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN8_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN8_SYNC2_BYPASS_M  ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S))
-#define GPIO_PIN8_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN8_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN9_REG          (DR_REG_GPIO_BASE + 0x98)
-/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN9_INT_ENA  0x0000001F
-#define GPIO_PIN9_INT_ENA_M  ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
-#define GPIO_PIN9_INT_ENA_V  0x1F
-#define GPIO_PIN9_INT_ENA_S  13
-/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN9_CONFIG  0x00000003
-#define GPIO_PIN9_CONFIG_M  ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
-#define GPIO_PIN9_CONFIG_V  0x3
-#define GPIO_PIN9_CONFIG_S  11
-/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN9_WAKEUP_ENABLE_S  10
-/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN9_INT_TYPE  0x00000007
-#define GPIO_PIN9_INT_TYPE_M  ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
-#define GPIO_PIN9_INT_TYPE_V  0x7
-#define GPIO_PIN9_INT_TYPE_S  7
-/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN9_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN9_SYNC1_BYPASS_M  ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S))
-#define GPIO_PIN9_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN9_SYNC1_BYPASS_S  3
-/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN9_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_V  0x1
-#define GPIO_PIN9_PAD_DRIVER_S  2
-/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN9_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN9_SYNC2_BYPASS_M  ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S))
-#define GPIO_PIN9_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN9_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN10_REG          (DR_REG_GPIO_BASE + 0x9C)
-/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN10_INT_ENA  0x0000001F
-#define GPIO_PIN10_INT_ENA_M  ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
-#define GPIO_PIN10_INT_ENA_V  0x1F
-#define GPIO_PIN10_INT_ENA_S  13
-/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN10_CONFIG  0x00000003
-#define GPIO_PIN10_CONFIG_M  ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
-#define GPIO_PIN10_CONFIG_V  0x3
-#define GPIO_PIN10_CONFIG_S  11
-/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN10_WAKEUP_ENABLE_S  10
-/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN10_INT_TYPE  0x00000007
-#define GPIO_PIN10_INT_TYPE_M  ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
-#define GPIO_PIN10_INT_TYPE_V  0x7
-#define GPIO_PIN10_INT_TYPE_S  7
-/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN10_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN10_SYNC1_BYPASS_M  ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S))
-#define GPIO_PIN10_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN10_SYNC1_BYPASS_S  3
-/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN10_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_V  0x1
-#define GPIO_PIN10_PAD_DRIVER_S  2
-/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN10_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN10_SYNC2_BYPASS_M  ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S))
-#define GPIO_PIN10_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN10_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN11_REG          (DR_REG_GPIO_BASE + 0xA0)
-/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN11_INT_ENA  0x0000001F
-#define GPIO_PIN11_INT_ENA_M  ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
-#define GPIO_PIN11_INT_ENA_V  0x1F
-#define GPIO_PIN11_INT_ENA_S  13
-/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN11_CONFIG  0x00000003
-#define GPIO_PIN11_CONFIG_M  ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
-#define GPIO_PIN11_CONFIG_V  0x3
-#define GPIO_PIN11_CONFIG_S  11
-/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN11_WAKEUP_ENABLE_S  10
-/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN11_INT_TYPE  0x00000007
-#define GPIO_PIN11_INT_TYPE_M  ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
-#define GPIO_PIN11_INT_TYPE_V  0x7
-#define GPIO_PIN11_INT_TYPE_S  7
-/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN11_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN11_SYNC1_BYPASS_M  ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S))
-#define GPIO_PIN11_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN11_SYNC1_BYPASS_S  3
-/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN11_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_V  0x1
-#define GPIO_PIN11_PAD_DRIVER_S  2
-/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN11_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN11_SYNC2_BYPASS_M  ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S))
-#define GPIO_PIN11_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN11_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN12_REG          (DR_REG_GPIO_BASE + 0xA4)
-/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN12_INT_ENA  0x0000001F
-#define GPIO_PIN12_INT_ENA_M  ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
-#define GPIO_PIN12_INT_ENA_V  0x1F
-#define GPIO_PIN12_INT_ENA_S  13
-/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN12_CONFIG  0x00000003
-#define GPIO_PIN12_CONFIG_M  ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
-#define GPIO_PIN12_CONFIG_V  0x3
-#define GPIO_PIN12_CONFIG_S  11
-/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN12_WAKEUP_ENABLE_S  10
-/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN12_INT_TYPE  0x00000007
-#define GPIO_PIN12_INT_TYPE_M  ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
-#define GPIO_PIN12_INT_TYPE_V  0x7
-#define GPIO_PIN12_INT_TYPE_S  7
-/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN12_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN12_SYNC1_BYPASS_M  ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S))
-#define GPIO_PIN12_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN12_SYNC1_BYPASS_S  3
-/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN12_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_V  0x1
-#define GPIO_PIN12_PAD_DRIVER_S  2
-/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN12_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN12_SYNC2_BYPASS_M  ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S))
-#define GPIO_PIN12_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN12_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN13_REG          (DR_REG_GPIO_BASE + 0xA8)
-/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN13_INT_ENA  0x0000001F
-#define GPIO_PIN13_INT_ENA_M  ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
-#define GPIO_PIN13_INT_ENA_V  0x1F
-#define GPIO_PIN13_INT_ENA_S  13
-/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN13_CONFIG  0x00000003
-#define GPIO_PIN13_CONFIG_M  ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
-#define GPIO_PIN13_CONFIG_V  0x3
-#define GPIO_PIN13_CONFIG_S  11
-/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN13_WAKEUP_ENABLE_S  10
-/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN13_INT_TYPE  0x00000007
-#define GPIO_PIN13_INT_TYPE_M  ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
-#define GPIO_PIN13_INT_TYPE_V  0x7
-#define GPIO_PIN13_INT_TYPE_S  7
-/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN13_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN13_SYNC1_BYPASS_M  ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S))
-#define GPIO_PIN13_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN13_SYNC1_BYPASS_S  3
-/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN13_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_V  0x1
-#define GPIO_PIN13_PAD_DRIVER_S  2
-/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN13_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN13_SYNC2_BYPASS_M  ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S))
-#define GPIO_PIN13_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN13_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN14_REG          (DR_REG_GPIO_BASE + 0xAC)
-/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN14_INT_ENA  0x0000001F
-#define GPIO_PIN14_INT_ENA_M  ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
-#define GPIO_PIN14_INT_ENA_V  0x1F
-#define GPIO_PIN14_INT_ENA_S  13
-/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN14_CONFIG  0x00000003
-#define GPIO_PIN14_CONFIG_M  ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
-#define GPIO_PIN14_CONFIG_V  0x3
-#define GPIO_PIN14_CONFIG_S  11
-/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN14_WAKEUP_ENABLE_S  10
-/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN14_INT_TYPE  0x00000007
-#define GPIO_PIN14_INT_TYPE_M  ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
-#define GPIO_PIN14_INT_TYPE_V  0x7
-#define GPIO_PIN14_INT_TYPE_S  7
-/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN14_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN14_SYNC1_BYPASS_M  ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S))
-#define GPIO_PIN14_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN14_SYNC1_BYPASS_S  3
-/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN14_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_V  0x1
-#define GPIO_PIN14_PAD_DRIVER_S  2
-/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN14_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN14_SYNC2_BYPASS_M  ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S))
-#define GPIO_PIN14_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN14_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN15_REG          (DR_REG_GPIO_BASE + 0xB0)
-/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN15_INT_ENA  0x0000001F
-#define GPIO_PIN15_INT_ENA_M  ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
-#define GPIO_PIN15_INT_ENA_V  0x1F
-#define GPIO_PIN15_INT_ENA_S  13
-/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN15_CONFIG  0x00000003
-#define GPIO_PIN15_CONFIG_M  ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
-#define GPIO_PIN15_CONFIG_V  0x3
-#define GPIO_PIN15_CONFIG_S  11
-/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN15_WAKEUP_ENABLE_S  10
-/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN15_INT_TYPE  0x00000007
-#define GPIO_PIN15_INT_TYPE_M  ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
-#define GPIO_PIN15_INT_TYPE_V  0x7
-#define GPIO_PIN15_INT_TYPE_S  7
-/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN15_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN15_SYNC1_BYPASS_M  ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S))
-#define GPIO_PIN15_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN15_SYNC1_BYPASS_S  3
-/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN15_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_V  0x1
-#define GPIO_PIN15_PAD_DRIVER_S  2
-/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN15_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN15_SYNC2_BYPASS_M  ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S))
-#define GPIO_PIN15_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN15_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN16_REG          (DR_REG_GPIO_BASE + 0xB4)
-/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN16_INT_ENA  0x0000001F
-#define GPIO_PIN16_INT_ENA_M  ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
-#define GPIO_PIN16_INT_ENA_V  0x1F
-#define GPIO_PIN16_INT_ENA_S  13
-/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN16_CONFIG  0x00000003
-#define GPIO_PIN16_CONFIG_M  ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
-#define GPIO_PIN16_CONFIG_V  0x3
-#define GPIO_PIN16_CONFIG_S  11
-/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN16_WAKEUP_ENABLE_S  10
-/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN16_INT_TYPE  0x00000007
-#define GPIO_PIN16_INT_TYPE_M  ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
-#define GPIO_PIN16_INT_TYPE_V  0x7
-#define GPIO_PIN16_INT_TYPE_S  7
-/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN16_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN16_SYNC1_BYPASS_M  ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S))
-#define GPIO_PIN16_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN16_SYNC1_BYPASS_S  3
-/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN16_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_V  0x1
-#define GPIO_PIN16_PAD_DRIVER_S  2
-/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN16_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN16_SYNC2_BYPASS_M  ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S))
-#define GPIO_PIN16_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN16_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN17_REG          (DR_REG_GPIO_BASE + 0xB8)
-/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN17_INT_ENA  0x0000001F
-#define GPIO_PIN17_INT_ENA_M  ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
-#define GPIO_PIN17_INT_ENA_V  0x1F
-#define GPIO_PIN17_INT_ENA_S  13
-/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN17_CONFIG  0x00000003
-#define GPIO_PIN17_CONFIG_M  ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
-#define GPIO_PIN17_CONFIG_V  0x3
-#define GPIO_PIN17_CONFIG_S  11
-/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN17_WAKEUP_ENABLE_S  10
-/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN17_INT_TYPE  0x00000007
-#define GPIO_PIN17_INT_TYPE_M  ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
-#define GPIO_PIN17_INT_TYPE_V  0x7
-#define GPIO_PIN17_INT_TYPE_S  7
-/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN17_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN17_SYNC1_BYPASS_M  ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S))
-#define GPIO_PIN17_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN17_SYNC1_BYPASS_S  3
-/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN17_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_V  0x1
-#define GPIO_PIN17_PAD_DRIVER_S  2
-/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN17_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN17_SYNC2_BYPASS_M  ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S))
-#define GPIO_PIN17_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN17_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN18_REG          (DR_REG_GPIO_BASE + 0xBC)
-/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN18_INT_ENA  0x0000001F
-#define GPIO_PIN18_INT_ENA_M  ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
-#define GPIO_PIN18_INT_ENA_V  0x1F
-#define GPIO_PIN18_INT_ENA_S  13
-/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN18_CONFIG  0x00000003
-#define GPIO_PIN18_CONFIG_M  ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
-#define GPIO_PIN18_CONFIG_V  0x3
-#define GPIO_PIN18_CONFIG_S  11
-/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN18_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN18_WAKEUP_ENABLE_S  10
-/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN18_INT_TYPE  0x00000007
-#define GPIO_PIN18_INT_TYPE_M  ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
-#define GPIO_PIN18_INT_TYPE_V  0x7
-#define GPIO_PIN18_INT_TYPE_S  7
-/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN18_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN18_SYNC1_BYPASS_M  ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S))
-#define GPIO_PIN18_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN18_SYNC1_BYPASS_S  3
-/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN18_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_V  0x1
-#define GPIO_PIN18_PAD_DRIVER_S  2
-/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN18_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN18_SYNC2_BYPASS_M  ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S))
-#define GPIO_PIN18_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN18_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN19_REG          (DR_REG_GPIO_BASE + 0xC0)
-/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN19_INT_ENA  0x0000001F
-#define GPIO_PIN19_INT_ENA_M  ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
-#define GPIO_PIN19_INT_ENA_V  0x1F
-#define GPIO_PIN19_INT_ENA_S  13
-/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN19_CONFIG  0x00000003
-#define GPIO_PIN19_CONFIG_M  ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
-#define GPIO_PIN19_CONFIG_V  0x3
-#define GPIO_PIN19_CONFIG_S  11
-/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN19_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN19_WAKEUP_ENABLE_S  10
-/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN19_INT_TYPE  0x00000007
-#define GPIO_PIN19_INT_TYPE_M  ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
-#define GPIO_PIN19_INT_TYPE_V  0x7
-#define GPIO_PIN19_INT_TYPE_S  7
-/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN19_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN19_SYNC1_BYPASS_M  ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S))
-#define GPIO_PIN19_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN19_SYNC1_BYPASS_S  3
-/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN19_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_V  0x1
-#define GPIO_PIN19_PAD_DRIVER_S  2
-/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN19_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN19_SYNC2_BYPASS_M  ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S))
-#define GPIO_PIN19_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN19_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN20_REG          (DR_REG_GPIO_BASE + 0xC4)
-/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN20_INT_ENA  0x0000001F
-#define GPIO_PIN20_INT_ENA_M  ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
-#define GPIO_PIN20_INT_ENA_V  0x1F
-#define GPIO_PIN20_INT_ENA_S  13
-/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN20_CONFIG  0x00000003
-#define GPIO_PIN20_CONFIG_M  ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
-#define GPIO_PIN20_CONFIG_V  0x3
-#define GPIO_PIN20_CONFIG_S  11
-/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN20_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN20_WAKEUP_ENABLE_S  10
-/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN20_INT_TYPE  0x00000007
-#define GPIO_PIN20_INT_TYPE_M  ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
-#define GPIO_PIN20_INT_TYPE_V  0x7
-#define GPIO_PIN20_INT_TYPE_S  7
-/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN20_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN20_SYNC1_BYPASS_M  ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S))
-#define GPIO_PIN20_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN20_SYNC1_BYPASS_S  3
-/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN20_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_V  0x1
-#define GPIO_PIN20_PAD_DRIVER_S  2
-/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN20_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN20_SYNC2_BYPASS_M  ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S))
-#define GPIO_PIN20_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN20_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN21_REG          (DR_REG_GPIO_BASE + 0xC8)
-/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN21_INT_ENA  0x0000001F
-#define GPIO_PIN21_INT_ENA_M  ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
-#define GPIO_PIN21_INT_ENA_V  0x1F
-#define GPIO_PIN21_INT_ENA_S  13
-/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN21_CONFIG  0x00000003
-#define GPIO_PIN21_CONFIG_M  ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
-#define GPIO_PIN21_CONFIG_V  0x3
-#define GPIO_PIN21_CONFIG_S  11
-/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN21_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN21_WAKEUP_ENABLE_S  10
-/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN21_INT_TYPE  0x00000007
-#define GPIO_PIN21_INT_TYPE_M  ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
-#define GPIO_PIN21_INT_TYPE_V  0x7
-#define GPIO_PIN21_INT_TYPE_S  7
-/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN21_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN21_SYNC1_BYPASS_M  ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S))
-#define GPIO_PIN21_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN21_SYNC1_BYPASS_S  3
-/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN21_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_V  0x1
-#define GPIO_PIN21_PAD_DRIVER_S  2
-/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN21_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN21_SYNC2_BYPASS_M  ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S))
-#define GPIO_PIN21_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN21_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN22_REG          (DR_REG_GPIO_BASE + 0xCC)
-/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN22_INT_ENA  0x0000001F
-#define GPIO_PIN22_INT_ENA_M  ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
-#define GPIO_PIN22_INT_ENA_V  0x1F
-#define GPIO_PIN22_INT_ENA_S  13
-/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN22_CONFIG  0x00000003
-#define GPIO_PIN22_CONFIG_M  ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
-#define GPIO_PIN22_CONFIG_V  0x3
-#define GPIO_PIN22_CONFIG_S  11
-/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN22_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN22_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN22_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN22_WAKEUP_ENABLE_S  10
-/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN22_INT_TYPE  0x00000007
-#define GPIO_PIN22_INT_TYPE_M  ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
-#define GPIO_PIN22_INT_TYPE_V  0x7
-#define GPIO_PIN22_INT_TYPE_S  7
-/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN22_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN22_SYNC1_BYPASS_M  ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S))
-#define GPIO_PIN22_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN22_SYNC1_BYPASS_S  3
-/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN22_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN22_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN22_PAD_DRIVER_V  0x1
-#define GPIO_PIN22_PAD_DRIVER_S  2
-/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN22_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN22_SYNC2_BYPASS_M  ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S))
-#define GPIO_PIN22_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN22_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN23_REG          (DR_REG_GPIO_BASE + 0xD0)
-/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN23_INT_ENA  0x0000001F
-#define GPIO_PIN23_INT_ENA_M  ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
-#define GPIO_PIN23_INT_ENA_V  0x1F
-#define GPIO_PIN23_INT_ENA_S  13
-/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN23_CONFIG  0x00000003
-#define GPIO_PIN23_CONFIG_M  ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
-#define GPIO_PIN23_CONFIG_V  0x3
-#define GPIO_PIN23_CONFIG_S  11
-/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN23_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN23_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN23_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN23_WAKEUP_ENABLE_S  10
-/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN23_INT_TYPE  0x00000007
-#define GPIO_PIN23_INT_TYPE_M  ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
-#define GPIO_PIN23_INT_TYPE_V  0x7
-#define GPIO_PIN23_INT_TYPE_S  7
-/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN23_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN23_SYNC1_BYPASS_M  ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S))
-#define GPIO_PIN23_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN23_SYNC1_BYPASS_S  3
-/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN23_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN23_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN23_PAD_DRIVER_V  0x1
-#define GPIO_PIN23_PAD_DRIVER_S  2
-/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN23_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN23_SYNC2_BYPASS_M  ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S))
-#define GPIO_PIN23_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN23_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN24_REG          (DR_REG_GPIO_BASE + 0xD4)
-/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN24_INT_ENA  0x0000001F
-#define GPIO_PIN24_INT_ENA_M  ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
-#define GPIO_PIN24_INT_ENA_V  0x1F
-#define GPIO_PIN24_INT_ENA_S  13
-/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN24_CONFIG  0x00000003
-#define GPIO_PIN24_CONFIG_M  ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
-#define GPIO_PIN24_CONFIG_V  0x3
-#define GPIO_PIN24_CONFIG_S  11
-/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN24_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN24_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN24_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN24_WAKEUP_ENABLE_S  10
-/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN24_INT_TYPE  0x00000007
-#define GPIO_PIN24_INT_TYPE_M  ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
-#define GPIO_PIN24_INT_TYPE_V  0x7
-#define GPIO_PIN24_INT_TYPE_S  7
-/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN24_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN24_SYNC1_BYPASS_M  ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S))
-#define GPIO_PIN24_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN24_SYNC1_BYPASS_S  3
-/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN24_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN24_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN24_PAD_DRIVER_V  0x1
-#define GPIO_PIN24_PAD_DRIVER_S  2
-/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN24_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN24_SYNC2_BYPASS_M  ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S))
-#define GPIO_PIN24_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN24_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN25_REG          (DR_REG_GPIO_BASE + 0xD8)
-/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_PIN25_INT_ENA  0x0000001F
-#define GPIO_PIN25_INT_ENA_M  ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
-#define GPIO_PIN25_INT_ENA_V  0x1F
-#define GPIO_PIN25_INT_ENA_S  13
-/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN25_CONFIG  0x00000003
-#define GPIO_PIN25_CONFIG_M  ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
-#define GPIO_PIN25_CONFIG_V  0x3
-#define GPIO_PIN25_CONFIG_S  11
-/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN25_WAKEUP_ENABLE  (BIT(10))
-#define GPIO_PIN25_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN25_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN25_WAKEUP_ENABLE_S  10
-/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: */
-#define GPIO_PIN25_INT_TYPE  0x00000007
-#define GPIO_PIN25_INT_TYPE_M  ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
-#define GPIO_PIN25_INT_TYPE_V  0x7
-#define GPIO_PIN25_INT_TYPE_S  7
-/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN25_SYNC1_BYPASS  0x00000003
-#define GPIO_PIN25_SYNC1_BYPASS_M  ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S))
-#define GPIO_PIN25_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN25_SYNC1_BYPASS_S  3
-/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_PIN25_PAD_DRIVER  (BIT(2))
-#define GPIO_PIN25_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN25_PAD_DRIVER_V  0x1
-#define GPIO_PIN25_PAD_DRIVER_S  2
-/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: */
-#define GPIO_PIN25_SYNC2_BYPASS  0x00000003
-#define GPIO_PIN25_SYNC2_BYPASS_M  ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S))
-#define GPIO_PIN25_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN25_SYNC2_BYPASS_S  0
-
-#define GPIO_STATUS_NEXT_REG          (DR_REG_GPIO_BASE + 0x14C)
-/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: */
-#define GPIO_STATUS_INTERRUPT_NEXT  0x03FFFFFF
-#define GPIO_STATUS_INTERRUPT_NEXT_M  ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S))
-#define GPIO_STATUS_INTERRUPT_NEXT_V  0x3FFFFFF
-#define GPIO_STATUS_INTERRUPT_NEXT_S  0
-
-#define GPIO_FUNC0_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x154)
-/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG0_IN_SEL  (BIT(6))
-#define GPIO_SIG0_IN_SEL_M  (BIT(6))
-#define GPIO_SIG0_IN_SEL_V  0x1
-#define GPIO_SIG0_IN_SEL_S  6
-/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC0_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC0_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC0_IN_INV_SEL_V  0x1
-#define GPIO_FUNC0_IN_INV_SEL_S  5
-/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC0_IN_SEL  0x0000001F
-#define GPIO_FUNC0_IN_SEL_M  ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
-#define GPIO_FUNC0_IN_SEL_V  0x1F
-#define GPIO_FUNC0_IN_SEL_S  0
-
-#define GPIO_FUNC1_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x158)
-/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG1_IN_SEL  (BIT(6))
-#define GPIO_SIG1_IN_SEL_M  (BIT(6))
-#define GPIO_SIG1_IN_SEL_V  0x1
-#define GPIO_SIG1_IN_SEL_S  6
-/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC1_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC1_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC1_IN_INV_SEL_V  0x1
-#define GPIO_FUNC1_IN_INV_SEL_S  5
-/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC1_IN_SEL  0x0000001F
-#define GPIO_FUNC1_IN_SEL_M  ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
-#define GPIO_FUNC1_IN_SEL_V  0x1F
-#define GPIO_FUNC1_IN_SEL_S  0
-
-#define GPIO_FUNC2_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x15C)
-/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG2_IN_SEL  (BIT(6))
-#define GPIO_SIG2_IN_SEL_M  (BIT(6))
-#define GPIO_SIG2_IN_SEL_V  0x1
-#define GPIO_SIG2_IN_SEL_S  6
-/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC2_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC2_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC2_IN_INV_SEL_V  0x1
-#define GPIO_FUNC2_IN_INV_SEL_S  5
-/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC2_IN_SEL  0x0000001F
-#define GPIO_FUNC2_IN_SEL_M  ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
-#define GPIO_FUNC2_IN_SEL_V  0x1F
-#define GPIO_FUNC2_IN_SEL_S  0
-
-#define GPIO_FUNC3_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x160)
-/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG3_IN_SEL  (BIT(6))
-#define GPIO_SIG3_IN_SEL_M  (BIT(6))
-#define GPIO_SIG3_IN_SEL_V  0x1
-#define GPIO_SIG3_IN_SEL_S  6
-/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC3_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC3_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC3_IN_INV_SEL_V  0x1
-#define GPIO_FUNC3_IN_INV_SEL_S  5
-/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC3_IN_SEL  0x0000001F
-#define GPIO_FUNC3_IN_SEL_M  ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
-#define GPIO_FUNC3_IN_SEL_V  0x1F
-#define GPIO_FUNC3_IN_SEL_S  0
-
-#define GPIO_FUNC4_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x164)
-/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG4_IN_SEL  (BIT(6))
-#define GPIO_SIG4_IN_SEL_M  (BIT(6))
-#define GPIO_SIG4_IN_SEL_V  0x1
-#define GPIO_SIG4_IN_SEL_S  6
-/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC4_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC4_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC4_IN_INV_SEL_V  0x1
-#define GPIO_FUNC4_IN_INV_SEL_S  5
-/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC4_IN_SEL  0x0000001F
-#define GPIO_FUNC4_IN_SEL_M  ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
-#define GPIO_FUNC4_IN_SEL_V  0x1F
-#define GPIO_FUNC4_IN_SEL_S  0
-
-#define GPIO_FUNC5_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x168)
-/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG5_IN_SEL  (BIT(6))
-#define GPIO_SIG5_IN_SEL_M  (BIT(6))
-#define GPIO_SIG5_IN_SEL_V  0x1
-#define GPIO_SIG5_IN_SEL_S  6
-/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC5_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC5_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC5_IN_INV_SEL_V  0x1
-#define GPIO_FUNC5_IN_INV_SEL_S  5
-/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC5_IN_SEL  0x0000001F
-#define GPIO_FUNC5_IN_SEL_M  ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
-#define GPIO_FUNC5_IN_SEL_V  0x1F
-#define GPIO_FUNC5_IN_SEL_S  0
-
-#define GPIO_FUNC6_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x16C)
-/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG6_IN_SEL  (BIT(6))
-#define GPIO_SIG6_IN_SEL_M  (BIT(6))
-#define GPIO_SIG6_IN_SEL_V  0x1
-#define GPIO_SIG6_IN_SEL_S  6
-/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC6_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC6_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC6_IN_INV_SEL_V  0x1
-#define GPIO_FUNC6_IN_INV_SEL_S  5
-/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC6_IN_SEL  0x0000001F
-#define GPIO_FUNC6_IN_SEL_M  ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
-#define GPIO_FUNC6_IN_SEL_V  0x1F
-#define GPIO_FUNC6_IN_SEL_S  0
-
-#define GPIO_FUNC7_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x170)
-/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG7_IN_SEL  (BIT(6))
-#define GPIO_SIG7_IN_SEL_M  (BIT(6))
-#define GPIO_SIG7_IN_SEL_V  0x1
-#define GPIO_SIG7_IN_SEL_S  6
-/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC7_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC7_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC7_IN_INV_SEL_V  0x1
-#define GPIO_FUNC7_IN_INV_SEL_S  5
-/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC7_IN_SEL  0x0000001F
-#define GPIO_FUNC7_IN_SEL_M  ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
-#define GPIO_FUNC7_IN_SEL_V  0x1F
-#define GPIO_FUNC7_IN_SEL_S  0
-
-#define GPIO_FUNC8_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x174)
-/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG8_IN_SEL  (BIT(6))
-#define GPIO_SIG8_IN_SEL_M  (BIT(6))
-#define GPIO_SIG8_IN_SEL_V  0x1
-#define GPIO_SIG8_IN_SEL_S  6
-/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC8_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC8_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC8_IN_INV_SEL_V  0x1
-#define GPIO_FUNC8_IN_INV_SEL_S  5
-/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC8_IN_SEL  0x0000001F
-#define GPIO_FUNC8_IN_SEL_M  ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
-#define GPIO_FUNC8_IN_SEL_V  0x1F
-#define GPIO_FUNC8_IN_SEL_S  0
-
-#define GPIO_FUNC9_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x178)
-/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG9_IN_SEL  (BIT(6))
-#define GPIO_SIG9_IN_SEL_M  (BIT(6))
-#define GPIO_SIG9_IN_SEL_V  0x1
-#define GPIO_SIG9_IN_SEL_S  6
-/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC9_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC9_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC9_IN_INV_SEL_V  0x1
-#define GPIO_FUNC9_IN_INV_SEL_S  5
-/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC9_IN_SEL  0x0000001F
-#define GPIO_FUNC9_IN_SEL_M  ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
-#define GPIO_FUNC9_IN_SEL_V  0x1F
-#define GPIO_FUNC9_IN_SEL_S  0
-
-#define GPIO_FUNC10_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x17C)
-/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG10_IN_SEL  (BIT(6))
-#define GPIO_SIG10_IN_SEL_M  (BIT(6))
-#define GPIO_SIG10_IN_SEL_V  0x1
-#define GPIO_SIG10_IN_SEL_S  6
-/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC10_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC10_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC10_IN_INV_SEL_V  0x1
-#define GPIO_FUNC10_IN_INV_SEL_S  5
-/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC10_IN_SEL  0x0000001F
-#define GPIO_FUNC10_IN_SEL_M  ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
-#define GPIO_FUNC10_IN_SEL_V  0x1F
-#define GPIO_FUNC10_IN_SEL_S  0
-
-#define GPIO_FUNC11_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x180)
-/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG11_IN_SEL  (BIT(6))
-#define GPIO_SIG11_IN_SEL_M  (BIT(6))
-#define GPIO_SIG11_IN_SEL_V  0x1
-#define GPIO_SIG11_IN_SEL_S  6
-/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC11_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC11_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC11_IN_INV_SEL_V  0x1
-#define GPIO_FUNC11_IN_INV_SEL_S  5
-/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC11_IN_SEL  0x0000001F
-#define GPIO_FUNC11_IN_SEL_M  ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
-#define GPIO_FUNC11_IN_SEL_V  0x1F
-#define GPIO_FUNC11_IN_SEL_S  0
-
-#define GPIO_FUNC12_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x184)
-/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG12_IN_SEL  (BIT(6))
-#define GPIO_SIG12_IN_SEL_M  (BIT(6))
-#define GPIO_SIG12_IN_SEL_V  0x1
-#define GPIO_SIG12_IN_SEL_S  6
-/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC12_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC12_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC12_IN_INV_SEL_V  0x1
-#define GPIO_FUNC12_IN_INV_SEL_S  5
-/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC12_IN_SEL  0x0000001F
-#define GPIO_FUNC12_IN_SEL_M  ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
-#define GPIO_FUNC12_IN_SEL_V  0x1F
-#define GPIO_FUNC12_IN_SEL_S  0
-
-#define GPIO_FUNC13_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x188)
-/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG13_IN_SEL  (BIT(6))
-#define GPIO_SIG13_IN_SEL_M  (BIT(6))
-#define GPIO_SIG13_IN_SEL_V  0x1
-#define GPIO_SIG13_IN_SEL_S  6
-/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC13_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC13_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC13_IN_INV_SEL_V  0x1
-#define GPIO_FUNC13_IN_INV_SEL_S  5
-/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC13_IN_SEL  0x0000001F
-#define GPIO_FUNC13_IN_SEL_M  ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
-#define GPIO_FUNC13_IN_SEL_V  0x1F
-#define GPIO_FUNC13_IN_SEL_S  0
-
-#define GPIO_FUNC14_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x18C)
-/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG14_IN_SEL  (BIT(6))
-#define GPIO_SIG14_IN_SEL_M  (BIT(6))
-#define GPIO_SIG14_IN_SEL_V  0x1
-#define GPIO_SIG14_IN_SEL_S  6
-/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC14_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC14_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC14_IN_INV_SEL_V  0x1
-#define GPIO_FUNC14_IN_INV_SEL_S  5
-/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC14_IN_SEL  0x0000001F
-#define GPIO_FUNC14_IN_SEL_M  ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
-#define GPIO_FUNC14_IN_SEL_V  0x1F
-#define GPIO_FUNC14_IN_SEL_S  0
-
-#define GPIO_FUNC15_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x190)
-/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG15_IN_SEL  (BIT(6))
-#define GPIO_SIG15_IN_SEL_M  (BIT(6))
-#define GPIO_SIG15_IN_SEL_V  0x1
-#define GPIO_SIG15_IN_SEL_S  6
-/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC15_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC15_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC15_IN_INV_SEL_V  0x1
-#define GPIO_FUNC15_IN_INV_SEL_S  5
-/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC15_IN_SEL  0x0000001F
-#define GPIO_FUNC15_IN_SEL_M  ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
-#define GPIO_FUNC15_IN_SEL_V  0x1F
-#define GPIO_FUNC15_IN_SEL_S  0
-
-#define GPIO_FUNC16_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x194)
-/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG16_IN_SEL  (BIT(6))
-#define GPIO_SIG16_IN_SEL_M  (BIT(6))
-#define GPIO_SIG16_IN_SEL_V  0x1
-#define GPIO_SIG16_IN_SEL_S  6
-/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC16_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC16_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC16_IN_INV_SEL_V  0x1
-#define GPIO_FUNC16_IN_INV_SEL_S  5
-/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC16_IN_SEL  0x0000001F
-#define GPIO_FUNC16_IN_SEL_M  ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
-#define GPIO_FUNC16_IN_SEL_V  0x1F
-#define GPIO_FUNC16_IN_SEL_S  0
-
-#define GPIO_FUNC17_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x198)
-/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG17_IN_SEL  (BIT(6))
-#define GPIO_SIG17_IN_SEL_M  (BIT(6))
-#define GPIO_SIG17_IN_SEL_V  0x1
-#define GPIO_SIG17_IN_SEL_S  6
-/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC17_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC17_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC17_IN_INV_SEL_V  0x1
-#define GPIO_FUNC17_IN_INV_SEL_S  5
-/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC17_IN_SEL  0x0000001F
-#define GPIO_FUNC17_IN_SEL_M  ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
-#define GPIO_FUNC17_IN_SEL_V  0x1F
-#define GPIO_FUNC17_IN_SEL_S  0
-
-#define GPIO_FUNC18_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x19C)
-/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG18_IN_SEL  (BIT(6))
-#define GPIO_SIG18_IN_SEL_M  (BIT(6))
-#define GPIO_SIG18_IN_SEL_V  0x1
-#define GPIO_SIG18_IN_SEL_S  6
-/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC18_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC18_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC18_IN_INV_SEL_V  0x1
-#define GPIO_FUNC18_IN_INV_SEL_S  5
-/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC18_IN_SEL  0x0000001F
-#define GPIO_FUNC18_IN_SEL_M  ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
-#define GPIO_FUNC18_IN_SEL_V  0x1F
-#define GPIO_FUNC18_IN_SEL_S  0
-
-#define GPIO_FUNC19_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A0)
-/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG19_IN_SEL  (BIT(6))
-#define GPIO_SIG19_IN_SEL_M  (BIT(6))
-#define GPIO_SIG19_IN_SEL_V  0x1
-#define GPIO_SIG19_IN_SEL_S  6
-/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC19_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC19_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC19_IN_INV_SEL_V  0x1
-#define GPIO_FUNC19_IN_INV_SEL_S  5
-/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC19_IN_SEL  0x0000001F
-#define GPIO_FUNC19_IN_SEL_M  ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
-#define GPIO_FUNC19_IN_SEL_V  0x1F
-#define GPIO_FUNC19_IN_SEL_S  0
-
-#define GPIO_FUNC20_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A4)
-/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG20_IN_SEL  (BIT(6))
-#define GPIO_SIG20_IN_SEL_M  (BIT(6))
-#define GPIO_SIG20_IN_SEL_V  0x1
-#define GPIO_SIG20_IN_SEL_S  6
-/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC20_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC20_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC20_IN_INV_SEL_V  0x1
-#define GPIO_FUNC20_IN_INV_SEL_S  5
-/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC20_IN_SEL  0x0000001F
-#define GPIO_FUNC20_IN_SEL_M  ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
-#define GPIO_FUNC20_IN_SEL_V  0x1F
-#define GPIO_FUNC20_IN_SEL_S  0
-
-#define GPIO_FUNC21_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A8)
-/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG21_IN_SEL  (BIT(6))
-#define GPIO_SIG21_IN_SEL_M  (BIT(6))
-#define GPIO_SIG21_IN_SEL_V  0x1
-#define GPIO_SIG21_IN_SEL_S  6
-/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC21_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC21_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC21_IN_INV_SEL_V  0x1
-#define GPIO_FUNC21_IN_INV_SEL_S  5
-/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC21_IN_SEL  0x0000001F
-#define GPIO_FUNC21_IN_SEL_M  ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
-#define GPIO_FUNC21_IN_SEL_V  0x1F
-#define GPIO_FUNC21_IN_SEL_S  0
-
-#define GPIO_FUNC22_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1AC)
-/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG22_IN_SEL  (BIT(6))
-#define GPIO_SIG22_IN_SEL_M  (BIT(6))
-#define GPIO_SIG22_IN_SEL_V  0x1
-#define GPIO_SIG22_IN_SEL_S  6
-/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC22_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC22_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC22_IN_INV_SEL_V  0x1
-#define GPIO_FUNC22_IN_INV_SEL_S  5
-/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC22_IN_SEL  0x0000001F
-#define GPIO_FUNC22_IN_SEL_M  ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
-#define GPIO_FUNC22_IN_SEL_V  0x1F
-#define GPIO_FUNC22_IN_SEL_S  0
-
-#define GPIO_FUNC23_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B0)
-/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG23_IN_SEL  (BIT(6))
-#define GPIO_SIG23_IN_SEL_M  (BIT(6))
-#define GPIO_SIG23_IN_SEL_V  0x1
-#define GPIO_SIG23_IN_SEL_S  6
-/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC23_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC23_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC23_IN_INV_SEL_V  0x1
-#define GPIO_FUNC23_IN_INV_SEL_S  5
-/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC23_IN_SEL  0x0000001F
-#define GPIO_FUNC23_IN_SEL_M  ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
-#define GPIO_FUNC23_IN_SEL_V  0x1F
-#define GPIO_FUNC23_IN_SEL_S  0
-
-#define GPIO_FUNC24_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B4)
-/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG24_IN_SEL  (BIT(6))
-#define GPIO_SIG24_IN_SEL_M  (BIT(6))
-#define GPIO_SIG24_IN_SEL_V  0x1
-#define GPIO_SIG24_IN_SEL_S  6
-/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC24_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC24_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC24_IN_INV_SEL_V  0x1
-#define GPIO_FUNC24_IN_INV_SEL_S  5
-/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC24_IN_SEL  0x0000001F
-#define GPIO_FUNC24_IN_SEL_M  ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
-#define GPIO_FUNC24_IN_SEL_V  0x1F
-#define GPIO_FUNC24_IN_SEL_S  0
-
-#define GPIO_FUNC25_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B8)
-/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG25_IN_SEL  (BIT(6))
-#define GPIO_SIG25_IN_SEL_M  (BIT(6))
-#define GPIO_SIG25_IN_SEL_V  0x1
-#define GPIO_SIG25_IN_SEL_S  6
-/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC25_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC25_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC25_IN_INV_SEL_V  0x1
-#define GPIO_FUNC25_IN_INV_SEL_S  5
-/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC25_IN_SEL  0x0000001F
-#define GPIO_FUNC25_IN_SEL_M  ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
-#define GPIO_FUNC25_IN_SEL_V  0x1F
-#define GPIO_FUNC25_IN_SEL_S  0
-
-#define GPIO_FUNC26_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1BC)
-/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG26_IN_SEL  (BIT(6))
-#define GPIO_SIG26_IN_SEL_M  (BIT(6))
-#define GPIO_SIG26_IN_SEL_V  0x1
-#define GPIO_SIG26_IN_SEL_S  6
-/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC26_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC26_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC26_IN_INV_SEL_V  0x1
-#define GPIO_FUNC26_IN_INV_SEL_S  5
-/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC26_IN_SEL  0x0000001F
-#define GPIO_FUNC26_IN_SEL_M  ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
-#define GPIO_FUNC26_IN_SEL_V  0x1F
-#define GPIO_FUNC26_IN_SEL_S  0
-
-#define GPIO_FUNC27_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C0)
-/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG27_IN_SEL  (BIT(6))
-#define GPIO_SIG27_IN_SEL_M  (BIT(6))
-#define GPIO_SIG27_IN_SEL_V  0x1
-#define GPIO_SIG27_IN_SEL_S  6
-/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC27_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC27_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC27_IN_INV_SEL_V  0x1
-#define GPIO_FUNC27_IN_INV_SEL_S  5
-/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC27_IN_SEL  0x0000001F
-#define GPIO_FUNC27_IN_SEL_M  ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
-#define GPIO_FUNC27_IN_SEL_V  0x1F
-#define GPIO_FUNC27_IN_SEL_S  0
-
-#define GPIO_FUNC28_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C4)
-/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG28_IN_SEL  (BIT(6))
-#define GPIO_SIG28_IN_SEL_M  (BIT(6))
-#define GPIO_SIG28_IN_SEL_V  0x1
-#define GPIO_SIG28_IN_SEL_S  6
-/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC28_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC28_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC28_IN_INV_SEL_V  0x1
-#define GPIO_FUNC28_IN_INV_SEL_S  5
-/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC28_IN_SEL  0x0000001F
-#define GPIO_FUNC28_IN_SEL_M  ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
-#define GPIO_FUNC28_IN_SEL_V  0x1F
-#define GPIO_FUNC28_IN_SEL_S  0
-
-#define GPIO_FUNC29_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C8)
-/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG29_IN_SEL  (BIT(6))
-#define GPIO_SIG29_IN_SEL_M  (BIT(6))
-#define GPIO_SIG29_IN_SEL_V  0x1
-#define GPIO_SIG29_IN_SEL_S  6
-/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC29_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC29_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC29_IN_INV_SEL_V  0x1
-#define GPIO_FUNC29_IN_INV_SEL_S  5
-/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC29_IN_SEL  0x0000001F
-#define GPIO_FUNC29_IN_SEL_M  ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
-#define GPIO_FUNC29_IN_SEL_V  0x1F
-#define GPIO_FUNC29_IN_SEL_S  0
-
-#define GPIO_FUNC30_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1CC)
-/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG30_IN_SEL  (BIT(6))
-#define GPIO_SIG30_IN_SEL_M  (BIT(6))
-#define GPIO_SIG30_IN_SEL_V  0x1
-#define GPIO_SIG30_IN_SEL_S  6
-/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC30_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC30_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC30_IN_INV_SEL_V  0x1
-#define GPIO_FUNC30_IN_INV_SEL_S  5
-/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC30_IN_SEL  0x0000001F
-#define GPIO_FUNC30_IN_SEL_M  ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
-#define GPIO_FUNC30_IN_SEL_V  0x1F
-#define GPIO_FUNC30_IN_SEL_S  0
-
-#define GPIO_FUNC31_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D0)
-/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG31_IN_SEL  (BIT(6))
-#define GPIO_SIG31_IN_SEL_M  (BIT(6))
-#define GPIO_SIG31_IN_SEL_V  0x1
-#define GPIO_SIG31_IN_SEL_S  6
-/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC31_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC31_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC31_IN_INV_SEL_V  0x1
-#define GPIO_FUNC31_IN_INV_SEL_S  5
-/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC31_IN_SEL  0x0000001F
-#define GPIO_FUNC31_IN_SEL_M  ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
-#define GPIO_FUNC31_IN_SEL_V  0x1F
-#define GPIO_FUNC31_IN_SEL_S  0
-
-#define GPIO_FUNC32_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D4)
-/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG32_IN_SEL  (BIT(6))
-#define GPIO_SIG32_IN_SEL_M  (BIT(6))
-#define GPIO_SIG32_IN_SEL_V  0x1
-#define GPIO_SIG32_IN_SEL_S  6
-/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC32_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC32_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC32_IN_INV_SEL_V  0x1
-#define GPIO_FUNC32_IN_INV_SEL_S  5
-/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC32_IN_SEL  0x0000001F
-#define GPIO_FUNC32_IN_SEL_M  ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
-#define GPIO_FUNC32_IN_SEL_V  0x1F
-#define GPIO_FUNC32_IN_SEL_S  0
-
-#define GPIO_FUNC33_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D8)
-/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG33_IN_SEL  (BIT(6))
-#define GPIO_SIG33_IN_SEL_M  (BIT(6))
-#define GPIO_SIG33_IN_SEL_V  0x1
-#define GPIO_SIG33_IN_SEL_S  6
-/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC33_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC33_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC33_IN_INV_SEL_V  0x1
-#define GPIO_FUNC33_IN_INV_SEL_S  5
-/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC33_IN_SEL  0x0000001F
-#define GPIO_FUNC33_IN_SEL_M  ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
-#define GPIO_FUNC33_IN_SEL_V  0x1F
-#define GPIO_FUNC33_IN_SEL_S  0
-
-#define GPIO_FUNC34_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1DC)
-/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG34_IN_SEL  (BIT(6))
-#define GPIO_SIG34_IN_SEL_M  (BIT(6))
-#define GPIO_SIG34_IN_SEL_V  0x1
-#define GPIO_SIG34_IN_SEL_S  6
-/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC34_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC34_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC34_IN_INV_SEL_V  0x1
-#define GPIO_FUNC34_IN_INV_SEL_S  5
-/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC34_IN_SEL  0x0000001F
-#define GPIO_FUNC34_IN_SEL_M  ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
-#define GPIO_FUNC34_IN_SEL_V  0x1F
-#define GPIO_FUNC34_IN_SEL_S  0
-
-#define GPIO_FUNC35_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E0)
-/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG35_IN_SEL  (BIT(6))
-#define GPIO_SIG35_IN_SEL_M  (BIT(6))
-#define GPIO_SIG35_IN_SEL_V  0x1
-#define GPIO_SIG35_IN_SEL_S  6
-/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC35_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC35_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC35_IN_INV_SEL_V  0x1
-#define GPIO_FUNC35_IN_INV_SEL_S  5
-/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC35_IN_SEL  0x0000001F
-#define GPIO_FUNC35_IN_SEL_M  ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
-#define GPIO_FUNC35_IN_SEL_V  0x1F
-#define GPIO_FUNC35_IN_SEL_S  0
-
-#define GPIO_FUNC36_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E4)
-/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG36_IN_SEL  (BIT(6))
-#define GPIO_SIG36_IN_SEL_M  (BIT(6))
-#define GPIO_SIG36_IN_SEL_V  0x1
-#define GPIO_SIG36_IN_SEL_S  6
-/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC36_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC36_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC36_IN_INV_SEL_V  0x1
-#define GPIO_FUNC36_IN_INV_SEL_S  5
-/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC36_IN_SEL  0x0000001F
-#define GPIO_FUNC36_IN_SEL_M  ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
-#define GPIO_FUNC36_IN_SEL_V  0x1F
-#define GPIO_FUNC36_IN_SEL_S  0
-
-#define GPIO_FUNC37_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E8)
-/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG37_IN_SEL  (BIT(6))
-#define GPIO_SIG37_IN_SEL_M  (BIT(6))
-#define GPIO_SIG37_IN_SEL_V  0x1
-#define GPIO_SIG37_IN_SEL_S  6
-/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC37_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC37_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC37_IN_INV_SEL_V  0x1
-#define GPIO_FUNC37_IN_INV_SEL_S  5
-/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC37_IN_SEL  0x0000001F
-#define GPIO_FUNC37_IN_SEL_M  ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
-#define GPIO_FUNC37_IN_SEL_V  0x1F
-#define GPIO_FUNC37_IN_SEL_S  0
-
-#define GPIO_FUNC38_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1EC)
-/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG38_IN_SEL  (BIT(6))
-#define GPIO_SIG38_IN_SEL_M  (BIT(6))
-#define GPIO_SIG38_IN_SEL_V  0x1
-#define GPIO_SIG38_IN_SEL_S  6
-/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC38_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC38_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC38_IN_INV_SEL_V  0x1
-#define GPIO_FUNC38_IN_INV_SEL_S  5
-/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC38_IN_SEL  0x0000001F
-#define GPIO_FUNC38_IN_SEL_M  ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
-#define GPIO_FUNC38_IN_SEL_V  0x1F
-#define GPIO_FUNC38_IN_SEL_S  0
-
-#define GPIO_FUNC39_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F0)
-/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG39_IN_SEL  (BIT(6))
-#define GPIO_SIG39_IN_SEL_M  (BIT(6))
-#define GPIO_SIG39_IN_SEL_V  0x1
-#define GPIO_SIG39_IN_SEL_S  6
-/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC39_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC39_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC39_IN_INV_SEL_V  0x1
-#define GPIO_FUNC39_IN_INV_SEL_S  5
-/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC39_IN_SEL  0x0000001F
-#define GPIO_FUNC39_IN_SEL_M  ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
-#define GPIO_FUNC39_IN_SEL_V  0x1F
-#define GPIO_FUNC39_IN_SEL_S  0
-
-#define GPIO_FUNC40_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F4)
-/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG40_IN_SEL  (BIT(6))
-#define GPIO_SIG40_IN_SEL_M  (BIT(6))
-#define GPIO_SIG40_IN_SEL_V  0x1
-#define GPIO_SIG40_IN_SEL_S  6
-/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC40_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC40_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC40_IN_INV_SEL_V  0x1
-#define GPIO_FUNC40_IN_INV_SEL_S  5
-/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC40_IN_SEL  0x0000001F
-#define GPIO_FUNC40_IN_SEL_M  ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
-#define GPIO_FUNC40_IN_SEL_V  0x1F
-#define GPIO_FUNC40_IN_SEL_S  0
-
-#define GPIO_FUNC41_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F8)
-/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG41_IN_SEL  (BIT(6))
-#define GPIO_SIG41_IN_SEL_M  (BIT(6))
-#define GPIO_SIG41_IN_SEL_V  0x1
-#define GPIO_SIG41_IN_SEL_S  6
-/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC41_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC41_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC41_IN_INV_SEL_V  0x1
-#define GPIO_FUNC41_IN_INV_SEL_S  5
-/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC41_IN_SEL  0x0000001F
-#define GPIO_FUNC41_IN_SEL_M  ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
-#define GPIO_FUNC41_IN_SEL_V  0x1F
-#define GPIO_FUNC41_IN_SEL_S  0
-
-#define GPIO_FUNC42_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1FC)
-/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG42_IN_SEL  (BIT(6))
-#define GPIO_SIG42_IN_SEL_M  (BIT(6))
-#define GPIO_SIG42_IN_SEL_V  0x1
-#define GPIO_SIG42_IN_SEL_S  6
-/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC42_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC42_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC42_IN_INV_SEL_V  0x1
-#define GPIO_FUNC42_IN_INV_SEL_S  5
-/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC42_IN_SEL  0x0000001F
-#define GPIO_FUNC42_IN_SEL_M  ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
-#define GPIO_FUNC42_IN_SEL_V  0x1F
-#define GPIO_FUNC42_IN_SEL_S  0
-
-#define GPIO_FUNC43_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x200)
-/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG43_IN_SEL  (BIT(6))
-#define GPIO_SIG43_IN_SEL_M  (BIT(6))
-#define GPIO_SIG43_IN_SEL_V  0x1
-#define GPIO_SIG43_IN_SEL_S  6
-/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC43_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC43_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC43_IN_INV_SEL_V  0x1
-#define GPIO_FUNC43_IN_INV_SEL_S  5
-/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC43_IN_SEL  0x0000001F
-#define GPIO_FUNC43_IN_SEL_M  ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
-#define GPIO_FUNC43_IN_SEL_V  0x1F
-#define GPIO_FUNC43_IN_SEL_S  0
-
-#define GPIO_FUNC44_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x204)
-/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG44_IN_SEL  (BIT(6))
-#define GPIO_SIG44_IN_SEL_M  (BIT(6))
-#define GPIO_SIG44_IN_SEL_V  0x1
-#define GPIO_SIG44_IN_SEL_S  6
-/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC44_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC44_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC44_IN_INV_SEL_V  0x1
-#define GPIO_FUNC44_IN_INV_SEL_S  5
-/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC44_IN_SEL  0x0000001F
-#define GPIO_FUNC44_IN_SEL_M  ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
-#define GPIO_FUNC44_IN_SEL_V  0x1F
-#define GPIO_FUNC44_IN_SEL_S  0
-
-#define GPIO_FUNC45_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x208)
-/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG45_IN_SEL  (BIT(6))
-#define GPIO_SIG45_IN_SEL_M  (BIT(6))
-#define GPIO_SIG45_IN_SEL_V  0x1
-#define GPIO_SIG45_IN_SEL_S  6
-/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC45_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC45_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC45_IN_INV_SEL_V  0x1
-#define GPIO_FUNC45_IN_INV_SEL_S  5
-/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC45_IN_SEL  0x0000001F
-#define GPIO_FUNC45_IN_SEL_M  ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
-#define GPIO_FUNC45_IN_SEL_V  0x1F
-#define GPIO_FUNC45_IN_SEL_S  0
-
-#define GPIO_FUNC46_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x20C)
-/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG46_IN_SEL  (BIT(6))
-#define GPIO_SIG46_IN_SEL_M  (BIT(6))
-#define GPIO_SIG46_IN_SEL_V  0x1
-#define GPIO_SIG46_IN_SEL_S  6
-/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC46_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC46_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC46_IN_INV_SEL_V  0x1
-#define GPIO_FUNC46_IN_INV_SEL_S  5
-/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC46_IN_SEL  0x0000001F
-#define GPIO_FUNC46_IN_SEL_M  ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
-#define GPIO_FUNC46_IN_SEL_V  0x1F
-#define GPIO_FUNC46_IN_SEL_S  0
-
-#define GPIO_FUNC47_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x210)
-/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG47_IN_SEL  (BIT(6))
-#define GPIO_SIG47_IN_SEL_M  (BIT(6))
-#define GPIO_SIG47_IN_SEL_V  0x1
-#define GPIO_SIG47_IN_SEL_S  6
-/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC47_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC47_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC47_IN_INV_SEL_V  0x1
-#define GPIO_FUNC47_IN_INV_SEL_S  5
-/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC47_IN_SEL  0x0000001F
-#define GPIO_FUNC47_IN_SEL_M  ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
-#define GPIO_FUNC47_IN_SEL_V  0x1F
-#define GPIO_FUNC47_IN_SEL_S  0
-
-#define GPIO_FUNC48_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x214)
-/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG48_IN_SEL  (BIT(6))
-#define GPIO_SIG48_IN_SEL_M  (BIT(6))
-#define GPIO_SIG48_IN_SEL_V  0x1
-#define GPIO_SIG48_IN_SEL_S  6
-/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC48_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC48_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC48_IN_INV_SEL_V  0x1
-#define GPIO_FUNC48_IN_INV_SEL_S  5
-/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC48_IN_SEL  0x0000001F
-#define GPIO_FUNC48_IN_SEL_M  ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
-#define GPIO_FUNC48_IN_SEL_V  0x1F
-#define GPIO_FUNC48_IN_SEL_S  0
-
-#define GPIO_FUNC49_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x218)
-/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG49_IN_SEL  (BIT(6))
-#define GPIO_SIG49_IN_SEL_M  (BIT(6))
-#define GPIO_SIG49_IN_SEL_V  0x1
-#define GPIO_SIG49_IN_SEL_S  6
-/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC49_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC49_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC49_IN_INV_SEL_V  0x1
-#define GPIO_FUNC49_IN_INV_SEL_S  5
-/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC49_IN_SEL  0x0000001F
-#define GPIO_FUNC49_IN_SEL_M  ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
-#define GPIO_FUNC49_IN_SEL_V  0x1F
-#define GPIO_FUNC49_IN_SEL_S  0
-
-#define GPIO_FUNC50_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x21C)
-/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG50_IN_SEL  (BIT(6))
-#define GPIO_SIG50_IN_SEL_M  (BIT(6))
-#define GPIO_SIG50_IN_SEL_V  0x1
-#define GPIO_SIG50_IN_SEL_S  6
-/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC50_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC50_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC50_IN_INV_SEL_V  0x1
-#define GPIO_FUNC50_IN_INV_SEL_S  5
-/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC50_IN_SEL  0x0000001F
-#define GPIO_FUNC50_IN_SEL_M  ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
-#define GPIO_FUNC50_IN_SEL_V  0x1F
-#define GPIO_FUNC50_IN_SEL_S  0
-
-#define GPIO_FUNC51_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x220)
-/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG51_IN_SEL  (BIT(6))
-#define GPIO_SIG51_IN_SEL_M  (BIT(6))
-#define GPIO_SIG51_IN_SEL_V  0x1
-#define GPIO_SIG51_IN_SEL_S  6
-/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC51_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC51_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC51_IN_INV_SEL_V  0x1
-#define GPIO_FUNC51_IN_INV_SEL_S  5
-/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC51_IN_SEL  0x0000001F
-#define GPIO_FUNC51_IN_SEL_M  ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
-#define GPIO_FUNC51_IN_SEL_V  0x1F
-#define GPIO_FUNC51_IN_SEL_S  0
-
-#define GPIO_FUNC52_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x224)
-/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG52_IN_SEL  (BIT(6))
-#define GPIO_SIG52_IN_SEL_M  (BIT(6))
-#define GPIO_SIG52_IN_SEL_V  0x1
-#define GPIO_SIG52_IN_SEL_S  6
-/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC52_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC52_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC52_IN_INV_SEL_V  0x1
-#define GPIO_FUNC52_IN_INV_SEL_S  5
-/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC52_IN_SEL  0x0000001F
-#define GPIO_FUNC52_IN_SEL_M  ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
-#define GPIO_FUNC52_IN_SEL_V  0x1F
-#define GPIO_FUNC52_IN_SEL_S  0
-
-#define GPIO_FUNC53_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x228)
-/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG53_IN_SEL  (BIT(6))
-#define GPIO_SIG53_IN_SEL_M  (BIT(6))
-#define GPIO_SIG53_IN_SEL_V  0x1
-#define GPIO_SIG53_IN_SEL_S  6
-/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC53_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC53_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC53_IN_INV_SEL_V  0x1
-#define GPIO_FUNC53_IN_INV_SEL_S  5
-/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC53_IN_SEL  0x0000001F
-#define GPIO_FUNC53_IN_SEL_M  ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
-#define GPIO_FUNC53_IN_SEL_V  0x1F
-#define GPIO_FUNC53_IN_SEL_S  0
-
-#define GPIO_FUNC54_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x22C)
-/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG54_IN_SEL  (BIT(6))
-#define GPIO_SIG54_IN_SEL_M  (BIT(6))
-#define GPIO_SIG54_IN_SEL_V  0x1
-#define GPIO_SIG54_IN_SEL_S  6
-/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC54_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC54_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC54_IN_INV_SEL_V  0x1
-#define GPIO_FUNC54_IN_INV_SEL_S  5
-/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC54_IN_SEL  0x0000001F
-#define GPIO_FUNC54_IN_SEL_M  ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
-#define GPIO_FUNC54_IN_SEL_V  0x1F
-#define GPIO_FUNC54_IN_SEL_S  0
-
-#define GPIO_FUNC55_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x230)
-/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG55_IN_SEL  (BIT(6))
-#define GPIO_SIG55_IN_SEL_M  (BIT(6))
-#define GPIO_SIG55_IN_SEL_V  0x1
-#define GPIO_SIG55_IN_SEL_S  6
-/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC55_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC55_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC55_IN_INV_SEL_V  0x1
-#define GPIO_FUNC55_IN_INV_SEL_S  5
-/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC55_IN_SEL  0x0000001F
-#define GPIO_FUNC55_IN_SEL_M  ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
-#define GPIO_FUNC55_IN_SEL_V  0x1F
-#define GPIO_FUNC55_IN_SEL_S  0
-
-#define GPIO_FUNC56_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x234)
-/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG56_IN_SEL  (BIT(6))
-#define GPIO_SIG56_IN_SEL_M  (BIT(6))
-#define GPIO_SIG56_IN_SEL_V  0x1
-#define GPIO_SIG56_IN_SEL_S  6
-/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC56_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC56_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC56_IN_INV_SEL_V  0x1
-#define GPIO_FUNC56_IN_INV_SEL_S  5
-/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC56_IN_SEL  0x0000001F
-#define GPIO_FUNC56_IN_SEL_M  ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
-#define GPIO_FUNC56_IN_SEL_V  0x1F
-#define GPIO_FUNC56_IN_SEL_S  0
-
-#define GPIO_FUNC57_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x238)
-/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG57_IN_SEL  (BIT(6))
-#define GPIO_SIG57_IN_SEL_M  (BIT(6))
-#define GPIO_SIG57_IN_SEL_V  0x1
-#define GPIO_SIG57_IN_SEL_S  6
-/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC57_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC57_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC57_IN_INV_SEL_V  0x1
-#define GPIO_FUNC57_IN_INV_SEL_S  5
-/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC57_IN_SEL  0x0000001F
-#define GPIO_FUNC57_IN_SEL_M  ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
-#define GPIO_FUNC57_IN_SEL_V  0x1F
-#define GPIO_FUNC57_IN_SEL_S  0
-
-#define GPIO_FUNC58_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x23C)
-/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG58_IN_SEL  (BIT(6))
-#define GPIO_SIG58_IN_SEL_M  (BIT(6))
-#define GPIO_SIG58_IN_SEL_V  0x1
-#define GPIO_SIG58_IN_SEL_S  6
-/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC58_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC58_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC58_IN_INV_SEL_V  0x1
-#define GPIO_FUNC58_IN_INV_SEL_S  5
-/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC58_IN_SEL  0x0000001F
-#define GPIO_FUNC58_IN_SEL_M  ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
-#define GPIO_FUNC58_IN_SEL_V  0x1F
-#define GPIO_FUNC58_IN_SEL_S  0
-
-#define GPIO_FUNC59_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x240)
-/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG59_IN_SEL  (BIT(6))
-#define GPIO_SIG59_IN_SEL_M  (BIT(6))
-#define GPIO_SIG59_IN_SEL_V  0x1
-#define GPIO_SIG59_IN_SEL_S  6
-/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC59_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC59_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC59_IN_INV_SEL_V  0x1
-#define GPIO_FUNC59_IN_INV_SEL_S  5
-/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC59_IN_SEL  0x0000001F
-#define GPIO_FUNC59_IN_SEL_M  ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
-#define GPIO_FUNC59_IN_SEL_V  0x1F
-#define GPIO_FUNC59_IN_SEL_S  0
-
-#define GPIO_FUNC60_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x244)
-/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG60_IN_SEL  (BIT(6))
-#define GPIO_SIG60_IN_SEL_M  (BIT(6))
-#define GPIO_SIG60_IN_SEL_V  0x1
-#define GPIO_SIG60_IN_SEL_S  6
-/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC60_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC60_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC60_IN_INV_SEL_V  0x1
-#define GPIO_FUNC60_IN_INV_SEL_S  5
-/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC60_IN_SEL  0x0000001F
-#define GPIO_FUNC60_IN_SEL_M  ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
-#define GPIO_FUNC60_IN_SEL_V  0x1F
-#define GPIO_FUNC60_IN_SEL_S  0
-
-#define GPIO_FUNC61_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x248)
-/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG61_IN_SEL  (BIT(6))
-#define GPIO_SIG61_IN_SEL_M  (BIT(6))
-#define GPIO_SIG61_IN_SEL_V  0x1
-#define GPIO_SIG61_IN_SEL_S  6
-/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC61_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC61_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC61_IN_INV_SEL_V  0x1
-#define GPIO_FUNC61_IN_INV_SEL_S  5
-/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC61_IN_SEL  0x0000001F
-#define GPIO_FUNC61_IN_SEL_M  ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
-#define GPIO_FUNC61_IN_SEL_V  0x1F
-#define GPIO_FUNC61_IN_SEL_S  0
-
-#define GPIO_FUNC62_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x24C)
-/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG62_IN_SEL  (BIT(6))
-#define GPIO_SIG62_IN_SEL_M  (BIT(6))
-#define GPIO_SIG62_IN_SEL_V  0x1
-#define GPIO_SIG62_IN_SEL_S  6
-/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC62_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC62_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC62_IN_INV_SEL_V  0x1
-#define GPIO_FUNC62_IN_INV_SEL_S  5
-/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC62_IN_SEL  0x0000001F
-#define GPIO_FUNC62_IN_SEL_M  ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
-#define GPIO_FUNC62_IN_SEL_V  0x1F
-#define GPIO_FUNC62_IN_SEL_S  0
-
-#define GPIO_FUNC63_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x250)
-/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG63_IN_SEL  (BIT(6))
-#define GPIO_SIG63_IN_SEL_M  (BIT(6))
-#define GPIO_SIG63_IN_SEL_V  0x1
-#define GPIO_SIG63_IN_SEL_S  6
-/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC63_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC63_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC63_IN_INV_SEL_V  0x1
-#define GPIO_FUNC63_IN_INV_SEL_S  5
-/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC63_IN_SEL  0x0000001F
-#define GPIO_FUNC63_IN_SEL_M  ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
-#define GPIO_FUNC63_IN_SEL_V  0x1F
-#define GPIO_FUNC63_IN_SEL_S  0
-
-#define GPIO_FUNC64_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x254)
-/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG64_IN_SEL  (BIT(6))
-#define GPIO_SIG64_IN_SEL_M  (BIT(6))
-#define GPIO_SIG64_IN_SEL_V  0x1
-#define GPIO_SIG64_IN_SEL_S  6
-/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC64_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC64_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC64_IN_INV_SEL_V  0x1
-#define GPIO_FUNC64_IN_INV_SEL_S  5
-/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC64_IN_SEL  0x0000001F
-#define GPIO_FUNC64_IN_SEL_M  ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
-#define GPIO_FUNC64_IN_SEL_V  0x1F
-#define GPIO_FUNC64_IN_SEL_S  0
-
-#define GPIO_FUNC65_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x258)
-/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG65_IN_SEL  (BIT(6))
-#define GPIO_SIG65_IN_SEL_M  (BIT(6))
-#define GPIO_SIG65_IN_SEL_V  0x1
-#define GPIO_SIG65_IN_SEL_S  6
-/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC65_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC65_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC65_IN_INV_SEL_V  0x1
-#define GPIO_FUNC65_IN_INV_SEL_S  5
-/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC65_IN_SEL  0x0000001F
-#define GPIO_FUNC65_IN_SEL_M  ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
-#define GPIO_FUNC65_IN_SEL_V  0x1F
-#define GPIO_FUNC65_IN_SEL_S  0
-
-#define GPIO_FUNC66_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x25C)
-/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG66_IN_SEL  (BIT(6))
-#define GPIO_SIG66_IN_SEL_M  (BIT(6))
-#define GPIO_SIG66_IN_SEL_V  0x1
-#define GPIO_SIG66_IN_SEL_S  6
-/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC66_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC66_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC66_IN_INV_SEL_V  0x1
-#define GPIO_FUNC66_IN_INV_SEL_S  5
-/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC66_IN_SEL  0x0000001F
-#define GPIO_FUNC66_IN_SEL_M  ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
-#define GPIO_FUNC66_IN_SEL_V  0x1F
-#define GPIO_FUNC66_IN_SEL_S  0
-
-#define GPIO_FUNC67_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x260)
-/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG67_IN_SEL  (BIT(6))
-#define GPIO_SIG67_IN_SEL_M  (BIT(6))
-#define GPIO_SIG67_IN_SEL_V  0x1
-#define GPIO_SIG67_IN_SEL_S  6
-/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC67_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC67_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC67_IN_INV_SEL_V  0x1
-#define GPIO_FUNC67_IN_INV_SEL_S  5
-/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC67_IN_SEL  0x0000001F
-#define GPIO_FUNC67_IN_SEL_M  ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
-#define GPIO_FUNC67_IN_SEL_V  0x1F
-#define GPIO_FUNC67_IN_SEL_S  0
-
-#define GPIO_FUNC68_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x264)
-/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG68_IN_SEL  (BIT(6))
-#define GPIO_SIG68_IN_SEL_M  (BIT(6))
-#define GPIO_SIG68_IN_SEL_V  0x1
-#define GPIO_SIG68_IN_SEL_S  6
-/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC68_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC68_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC68_IN_INV_SEL_V  0x1
-#define GPIO_FUNC68_IN_INV_SEL_S  5
-/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC68_IN_SEL  0x0000001F
-#define GPIO_FUNC68_IN_SEL_M  ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
-#define GPIO_FUNC68_IN_SEL_V  0x1F
-#define GPIO_FUNC68_IN_SEL_S  0
-
-#define GPIO_FUNC69_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x268)
-/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG69_IN_SEL  (BIT(6))
-#define GPIO_SIG69_IN_SEL_M  (BIT(6))
-#define GPIO_SIG69_IN_SEL_V  0x1
-#define GPIO_SIG69_IN_SEL_S  6
-/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC69_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC69_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC69_IN_INV_SEL_V  0x1
-#define GPIO_FUNC69_IN_INV_SEL_S  5
-/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC69_IN_SEL  0x0000001F
-#define GPIO_FUNC69_IN_SEL_M  ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
-#define GPIO_FUNC69_IN_SEL_V  0x1F
-#define GPIO_FUNC69_IN_SEL_S  0
-
-#define GPIO_FUNC70_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x26C)
-/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG70_IN_SEL  (BIT(6))
-#define GPIO_SIG70_IN_SEL_M  (BIT(6))
-#define GPIO_SIG70_IN_SEL_V  0x1
-#define GPIO_SIG70_IN_SEL_S  6
-/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC70_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC70_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC70_IN_INV_SEL_V  0x1
-#define GPIO_FUNC70_IN_INV_SEL_S  5
-/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC70_IN_SEL  0x0000001F
-#define GPIO_FUNC70_IN_SEL_M  ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
-#define GPIO_FUNC70_IN_SEL_V  0x1F
-#define GPIO_FUNC70_IN_SEL_S  0
-
-#define GPIO_FUNC71_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x270)
-/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG71_IN_SEL  (BIT(6))
-#define GPIO_SIG71_IN_SEL_M  (BIT(6))
-#define GPIO_SIG71_IN_SEL_V  0x1
-#define GPIO_SIG71_IN_SEL_S  6
-/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC71_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC71_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC71_IN_INV_SEL_V  0x1
-#define GPIO_FUNC71_IN_INV_SEL_S  5
-/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC71_IN_SEL  0x0000001F
-#define GPIO_FUNC71_IN_SEL_M  ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
-#define GPIO_FUNC71_IN_SEL_V  0x1F
-#define GPIO_FUNC71_IN_SEL_S  0
-
-#define GPIO_FUNC72_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x274)
-/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG72_IN_SEL  (BIT(6))
-#define GPIO_SIG72_IN_SEL_M  (BIT(6))
-#define GPIO_SIG72_IN_SEL_V  0x1
-#define GPIO_SIG72_IN_SEL_S  6
-/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC72_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC72_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC72_IN_INV_SEL_V  0x1
-#define GPIO_FUNC72_IN_INV_SEL_S  5
-/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC72_IN_SEL  0x0000001F
-#define GPIO_FUNC72_IN_SEL_M  ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
-#define GPIO_FUNC72_IN_SEL_V  0x1F
-#define GPIO_FUNC72_IN_SEL_S  0
-
-#define GPIO_FUNC73_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x278)
-/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG73_IN_SEL  (BIT(6))
-#define GPIO_SIG73_IN_SEL_M  (BIT(6))
-#define GPIO_SIG73_IN_SEL_V  0x1
-#define GPIO_SIG73_IN_SEL_S  6
-/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC73_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC73_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC73_IN_INV_SEL_V  0x1
-#define GPIO_FUNC73_IN_INV_SEL_S  5
-/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC73_IN_SEL  0x0000001F
-#define GPIO_FUNC73_IN_SEL_M  ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
-#define GPIO_FUNC73_IN_SEL_V  0x1F
-#define GPIO_FUNC73_IN_SEL_S  0
-
-#define GPIO_FUNC74_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x27C)
-/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG74_IN_SEL  (BIT(6))
-#define GPIO_SIG74_IN_SEL_M  (BIT(6))
-#define GPIO_SIG74_IN_SEL_V  0x1
-#define GPIO_SIG74_IN_SEL_S  6
-/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC74_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC74_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC74_IN_INV_SEL_V  0x1
-#define GPIO_FUNC74_IN_INV_SEL_S  5
-/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC74_IN_SEL  0x0000001F
-#define GPIO_FUNC74_IN_SEL_M  ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
-#define GPIO_FUNC74_IN_SEL_V  0x1F
-#define GPIO_FUNC74_IN_SEL_S  0
-
-#define GPIO_FUNC75_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x280)
-/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG75_IN_SEL  (BIT(6))
-#define GPIO_SIG75_IN_SEL_M  (BIT(6))
-#define GPIO_SIG75_IN_SEL_V  0x1
-#define GPIO_SIG75_IN_SEL_S  6
-/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC75_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC75_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC75_IN_INV_SEL_V  0x1
-#define GPIO_FUNC75_IN_INV_SEL_S  5
-/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC75_IN_SEL  0x0000001F
-#define GPIO_FUNC75_IN_SEL_M  ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
-#define GPIO_FUNC75_IN_SEL_V  0x1F
-#define GPIO_FUNC75_IN_SEL_S  0
-
-#define GPIO_FUNC76_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x284)
-/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG76_IN_SEL  (BIT(6))
-#define GPIO_SIG76_IN_SEL_M  (BIT(6))
-#define GPIO_SIG76_IN_SEL_V  0x1
-#define GPIO_SIG76_IN_SEL_S  6
-/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC76_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC76_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC76_IN_INV_SEL_V  0x1
-#define GPIO_FUNC76_IN_INV_SEL_S  5
-/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC76_IN_SEL  0x0000001F
-#define GPIO_FUNC76_IN_SEL_M  ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
-#define GPIO_FUNC76_IN_SEL_V  0x1F
-#define GPIO_FUNC76_IN_SEL_S  0
-
-#define GPIO_FUNC77_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x288)
-/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG77_IN_SEL  (BIT(6))
-#define GPIO_SIG77_IN_SEL_M  (BIT(6))
-#define GPIO_SIG77_IN_SEL_V  0x1
-#define GPIO_SIG77_IN_SEL_S  6
-/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC77_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC77_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC77_IN_INV_SEL_V  0x1
-#define GPIO_FUNC77_IN_INV_SEL_S  5
-/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC77_IN_SEL  0x0000001F
-#define GPIO_FUNC77_IN_SEL_M  ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
-#define GPIO_FUNC77_IN_SEL_V  0x1F
-#define GPIO_FUNC77_IN_SEL_S  0
-
-#define GPIO_FUNC78_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x28C)
-/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG78_IN_SEL  (BIT(6))
-#define GPIO_SIG78_IN_SEL_M  (BIT(6))
-#define GPIO_SIG78_IN_SEL_V  0x1
-#define GPIO_SIG78_IN_SEL_S  6
-/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC78_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC78_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC78_IN_INV_SEL_V  0x1
-#define GPIO_FUNC78_IN_INV_SEL_S  5
-/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC78_IN_SEL  0x0000001F
-#define GPIO_FUNC78_IN_SEL_M  ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
-#define GPIO_FUNC78_IN_SEL_V  0x1F
-#define GPIO_FUNC78_IN_SEL_S  0
-
-#define GPIO_FUNC79_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x290)
-/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG79_IN_SEL  (BIT(6))
-#define GPIO_SIG79_IN_SEL_M  (BIT(6))
-#define GPIO_SIG79_IN_SEL_V  0x1
-#define GPIO_SIG79_IN_SEL_S  6
-/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC79_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC79_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC79_IN_INV_SEL_V  0x1
-#define GPIO_FUNC79_IN_INV_SEL_S  5
-/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC79_IN_SEL  0x0000001F
-#define GPIO_FUNC79_IN_SEL_M  ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
-#define GPIO_FUNC79_IN_SEL_V  0x1F
-#define GPIO_FUNC79_IN_SEL_S  0
-
-#define GPIO_FUNC80_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x294)
-/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG80_IN_SEL  (BIT(6))
-#define GPIO_SIG80_IN_SEL_M  (BIT(6))
-#define GPIO_SIG80_IN_SEL_V  0x1
-#define GPIO_SIG80_IN_SEL_S  6
-/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC80_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC80_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC80_IN_INV_SEL_V  0x1
-#define GPIO_FUNC80_IN_INV_SEL_S  5
-/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC80_IN_SEL  0x0000001F
-#define GPIO_FUNC80_IN_SEL_M  ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
-#define GPIO_FUNC80_IN_SEL_V  0x1F
-#define GPIO_FUNC80_IN_SEL_S  0
-
-#define GPIO_FUNC81_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x298)
-/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG81_IN_SEL  (BIT(6))
-#define GPIO_SIG81_IN_SEL_M  (BIT(6))
-#define GPIO_SIG81_IN_SEL_V  0x1
-#define GPIO_SIG81_IN_SEL_S  6
-/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC81_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC81_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC81_IN_INV_SEL_V  0x1
-#define GPIO_FUNC81_IN_INV_SEL_S  5
-/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC81_IN_SEL  0x0000001F
-#define GPIO_FUNC81_IN_SEL_M  ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
-#define GPIO_FUNC81_IN_SEL_V  0x1F
-#define GPIO_FUNC81_IN_SEL_S  0
-
-#define GPIO_FUNC82_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x29C)
-/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG82_IN_SEL  (BIT(6))
-#define GPIO_SIG82_IN_SEL_M  (BIT(6))
-#define GPIO_SIG82_IN_SEL_V  0x1
-#define GPIO_SIG82_IN_SEL_S  6
-/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC82_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC82_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC82_IN_INV_SEL_V  0x1
-#define GPIO_FUNC82_IN_INV_SEL_S  5
-/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC82_IN_SEL  0x0000001F
-#define GPIO_FUNC82_IN_SEL_M  ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
-#define GPIO_FUNC82_IN_SEL_V  0x1F
-#define GPIO_FUNC82_IN_SEL_S  0
-
-#define GPIO_FUNC83_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A0)
-/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG83_IN_SEL  (BIT(6))
-#define GPIO_SIG83_IN_SEL_M  (BIT(6))
-#define GPIO_SIG83_IN_SEL_V  0x1
-#define GPIO_SIG83_IN_SEL_S  6
-/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC83_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC83_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC83_IN_INV_SEL_V  0x1
-#define GPIO_FUNC83_IN_INV_SEL_S  5
-/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC83_IN_SEL  0x0000001F
-#define GPIO_FUNC83_IN_SEL_M  ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
-#define GPIO_FUNC83_IN_SEL_V  0x1F
-#define GPIO_FUNC83_IN_SEL_S  0
-
-#define GPIO_FUNC84_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A4)
-/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG84_IN_SEL  (BIT(6))
-#define GPIO_SIG84_IN_SEL_M  (BIT(6))
-#define GPIO_SIG84_IN_SEL_V  0x1
-#define GPIO_SIG84_IN_SEL_S  6
-/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC84_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC84_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC84_IN_INV_SEL_V  0x1
-#define GPIO_FUNC84_IN_INV_SEL_S  5
-/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC84_IN_SEL  0x0000001F
-#define GPIO_FUNC84_IN_SEL_M  ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
-#define GPIO_FUNC84_IN_SEL_V  0x1F
-#define GPIO_FUNC84_IN_SEL_S  0
-
-#define GPIO_FUNC85_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A8)
-/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG85_IN_SEL  (BIT(6))
-#define GPIO_SIG85_IN_SEL_M  (BIT(6))
-#define GPIO_SIG85_IN_SEL_V  0x1
-#define GPIO_SIG85_IN_SEL_S  6
-/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC85_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC85_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC85_IN_INV_SEL_V  0x1
-#define GPIO_FUNC85_IN_INV_SEL_S  5
-/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC85_IN_SEL  0x0000001F
-#define GPIO_FUNC85_IN_SEL_M  ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
-#define GPIO_FUNC85_IN_SEL_V  0x1F
-#define GPIO_FUNC85_IN_SEL_S  0
-
-#define GPIO_FUNC86_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2AC)
-/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG86_IN_SEL  (BIT(6))
-#define GPIO_SIG86_IN_SEL_M  (BIT(6))
-#define GPIO_SIG86_IN_SEL_V  0x1
-#define GPIO_SIG86_IN_SEL_S  6
-/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC86_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC86_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC86_IN_INV_SEL_V  0x1
-#define GPIO_FUNC86_IN_INV_SEL_S  5
-/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC86_IN_SEL  0x0000001F
-#define GPIO_FUNC86_IN_SEL_M  ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
-#define GPIO_FUNC86_IN_SEL_V  0x1F
-#define GPIO_FUNC86_IN_SEL_S  0
-
-#define GPIO_FUNC87_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B0)
-/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG87_IN_SEL  (BIT(6))
-#define GPIO_SIG87_IN_SEL_M  (BIT(6))
-#define GPIO_SIG87_IN_SEL_V  0x1
-#define GPIO_SIG87_IN_SEL_S  6
-/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC87_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC87_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC87_IN_INV_SEL_V  0x1
-#define GPIO_FUNC87_IN_INV_SEL_S  5
-/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC87_IN_SEL  0x0000001F
-#define GPIO_FUNC87_IN_SEL_M  ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
-#define GPIO_FUNC87_IN_SEL_V  0x1F
-#define GPIO_FUNC87_IN_SEL_S  0
-
-#define GPIO_FUNC88_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B4)
-/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG88_IN_SEL  (BIT(6))
-#define GPIO_SIG88_IN_SEL_M  (BIT(6))
-#define GPIO_SIG88_IN_SEL_V  0x1
-#define GPIO_SIG88_IN_SEL_S  6
-/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC88_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC88_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC88_IN_INV_SEL_V  0x1
-#define GPIO_FUNC88_IN_INV_SEL_S  5
-/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC88_IN_SEL  0x0000001F
-#define GPIO_FUNC88_IN_SEL_M  ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
-#define GPIO_FUNC88_IN_SEL_V  0x1F
-#define GPIO_FUNC88_IN_SEL_S  0
-
-#define GPIO_FUNC89_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B8)
-/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG89_IN_SEL  (BIT(6))
-#define GPIO_SIG89_IN_SEL_M  (BIT(6))
-#define GPIO_SIG89_IN_SEL_V  0x1
-#define GPIO_SIG89_IN_SEL_S  6
-/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC89_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC89_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC89_IN_INV_SEL_V  0x1
-#define GPIO_FUNC89_IN_INV_SEL_S  5
-/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC89_IN_SEL  0x0000001F
-#define GPIO_FUNC89_IN_SEL_M  ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
-#define GPIO_FUNC89_IN_SEL_V  0x1F
-#define GPIO_FUNC89_IN_SEL_S  0
-
-#define GPIO_FUNC90_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2BC)
-/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG90_IN_SEL  (BIT(6))
-#define GPIO_SIG90_IN_SEL_M  (BIT(6))
-#define GPIO_SIG90_IN_SEL_V  0x1
-#define GPIO_SIG90_IN_SEL_S  6
-/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC90_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC90_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC90_IN_INV_SEL_V  0x1
-#define GPIO_FUNC90_IN_INV_SEL_S  5
-/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC90_IN_SEL  0x0000001F
-#define GPIO_FUNC90_IN_SEL_M  ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
-#define GPIO_FUNC90_IN_SEL_V  0x1F
-#define GPIO_FUNC90_IN_SEL_S  0
-
-#define GPIO_FUNC91_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C0)
-/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG91_IN_SEL  (BIT(6))
-#define GPIO_SIG91_IN_SEL_M  (BIT(6))
-#define GPIO_SIG91_IN_SEL_V  0x1
-#define GPIO_SIG91_IN_SEL_S  6
-/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC91_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC91_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC91_IN_INV_SEL_V  0x1
-#define GPIO_FUNC91_IN_INV_SEL_S  5
-/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC91_IN_SEL  0x0000001F
-#define GPIO_FUNC91_IN_SEL_M  ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
-#define GPIO_FUNC91_IN_SEL_V  0x1F
-#define GPIO_FUNC91_IN_SEL_S  0
-
-#define GPIO_FUNC92_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C4)
-/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG92_IN_SEL  (BIT(6))
-#define GPIO_SIG92_IN_SEL_M  (BIT(6))
-#define GPIO_SIG92_IN_SEL_V  0x1
-#define GPIO_SIG92_IN_SEL_S  6
-/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC92_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC92_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC92_IN_INV_SEL_V  0x1
-#define GPIO_FUNC92_IN_INV_SEL_S  5
-/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC92_IN_SEL  0x0000001F
-#define GPIO_FUNC92_IN_SEL_M  ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
-#define GPIO_FUNC92_IN_SEL_V  0x1F
-#define GPIO_FUNC92_IN_SEL_S  0
-
-#define GPIO_FUNC93_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C8)
-/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG93_IN_SEL  (BIT(6))
-#define GPIO_SIG93_IN_SEL_M  (BIT(6))
-#define GPIO_SIG93_IN_SEL_V  0x1
-#define GPIO_SIG93_IN_SEL_S  6
-/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC93_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC93_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC93_IN_INV_SEL_V  0x1
-#define GPIO_FUNC93_IN_INV_SEL_S  5
-/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC93_IN_SEL  0x0000001F
-#define GPIO_FUNC93_IN_SEL_M  ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
-#define GPIO_FUNC93_IN_SEL_V  0x1F
-#define GPIO_FUNC93_IN_SEL_S  0
-
-#define GPIO_FUNC94_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2CC)
-/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG94_IN_SEL  (BIT(6))
-#define GPIO_SIG94_IN_SEL_M  (BIT(6))
-#define GPIO_SIG94_IN_SEL_V  0x1
-#define GPIO_SIG94_IN_SEL_S  6
-/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC94_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC94_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC94_IN_INV_SEL_V  0x1
-#define GPIO_FUNC94_IN_INV_SEL_S  5
-/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC94_IN_SEL  0x0000001F
-#define GPIO_FUNC94_IN_SEL_M  ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
-#define GPIO_FUNC94_IN_SEL_V  0x1F
-#define GPIO_FUNC94_IN_SEL_S  0
-
-#define GPIO_FUNC95_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D0)
-/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG95_IN_SEL  (BIT(6))
-#define GPIO_SIG95_IN_SEL_M  (BIT(6))
-#define GPIO_SIG95_IN_SEL_V  0x1
-#define GPIO_SIG95_IN_SEL_S  6
-/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC95_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC95_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC95_IN_INV_SEL_V  0x1
-#define GPIO_FUNC95_IN_INV_SEL_S  5
-/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC95_IN_SEL  0x0000001F
-#define GPIO_FUNC95_IN_SEL_M  ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
-#define GPIO_FUNC95_IN_SEL_V  0x1F
-#define GPIO_FUNC95_IN_SEL_S  0
-
-#define GPIO_FUNC96_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D4)
-/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG96_IN_SEL  (BIT(6))
-#define GPIO_SIG96_IN_SEL_M  (BIT(6))
-#define GPIO_SIG96_IN_SEL_V  0x1
-#define GPIO_SIG96_IN_SEL_S  6
-/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC96_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC96_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC96_IN_INV_SEL_V  0x1
-#define GPIO_FUNC96_IN_INV_SEL_S  5
-/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC96_IN_SEL  0x0000001F
-#define GPIO_FUNC96_IN_SEL_M  ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
-#define GPIO_FUNC96_IN_SEL_V  0x1F
-#define GPIO_FUNC96_IN_SEL_S  0
-
-#define GPIO_FUNC97_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D8)
-/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG97_IN_SEL  (BIT(6))
-#define GPIO_SIG97_IN_SEL_M  (BIT(6))
-#define GPIO_SIG97_IN_SEL_V  0x1
-#define GPIO_SIG97_IN_SEL_S  6
-/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC97_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC97_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC97_IN_INV_SEL_V  0x1
-#define GPIO_FUNC97_IN_INV_SEL_S  5
-/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC97_IN_SEL  0x0000001F
-#define GPIO_FUNC97_IN_SEL_M  ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
-#define GPIO_FUNC97_IN_SEL_V  0x1F
-#define GPIO_FUNC97_IN_SEL_S  0
-
-#define GPIO_FUNC98_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2DC)
-/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG98_IN_SEL  (BIT(6))
-#define GPIO_SIG98_IN_SEL_M  (BIT(6))
-#define GPIO_SIG98_IN_SEL_V  0x1
-#define GPIO_SIG98_IN_SEL_S  6
-/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC98_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC98_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC98_IN_INV_SEL_V  0x1
-#define GPIO_FUNC98_IN_INV_SEL_S  5
-/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC98_IN_SEL  0x0000001F
-#define GPIO_FUNC98_IN_SEL_M  ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
-#define GPIO_FUNC98_IN_SEL_V  0x1F
-#define GPIO_FUNC98_IN_SEL_S  0
-
-#define GPIO_FUNC99_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E0)
-/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG99_IN_SEL  (BIT(6))
-#define GPIO_SIG99_IN_SEL_M  (BIT(6))
-#define GPIO_SIG99_IN_SEL_V  0x1
-#define GPIO_SIG99_IN_SEL_S  6
-/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC99_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC99_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC99_IN_INV_SEL_V  0x1
-#define GPIO_FUNC99_IN_INV_SEL_S  5
-/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC99_IN_SEL  0x0000001F
-#define GPIO_FUNC99_IN_SEL_M  ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
-#define GPIO_FUNC99_IN_SEL_V  0x1F
-#define GPIO_FUNC99_IN_SEL_S  0
-
-#define GPIO_FUNC100_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E4)
-/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG100_IN_SEL  (BIT(6))
-#define GPIO_SIG100_IN_SEL_M  (BIT(6))
-#define GPIO_SIG100_IN_SEL_V  0x1
-#define GPIO_SIG100_IN_SEL_S  6
-/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC100_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC100_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC100_IN_INV_SEL_V  0x1
-#define GPIO_FUNC100_IN_INV_SEL_S  5
-/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC100_IN_SEL  0x0000001F
-#define GPIO_FUNC100_IN_SEL_M  ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
-#define GPIO_FUNC100_IN_SEL_V  0x1F
-#define GPIO_FUNC100_IN_SEL_S  0
-
-#define GPIO_FUNC101_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E8)
-/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG101_IN_SEL  (BIT(6))
-#define GPIO_SIG101_IN_SEL_M  (BIT(6))
-#define GPIO_SIG101_IN_SEL_V  0x1
-#define GPIO_SIG101_IN_SEL_S  6
-/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC101_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC101_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC101_IN_INV_SEL_V  0x1
-#define GPIO_FUNC101_IN_INV_SEL_S  5
-/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC101_IN_SEL  0x0000001F
-#define GPIO_FUNC101_IN_SEL_M  ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
-#define GPIO_FUNC101_IN_SEL_V  0x1F
-#define GPIO_FUNC101_IN_SEL_S  0
-
-#define GPIO_FUNC102_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2EC)
-/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG102_IN_SEL  (BIT(6))
-#define GPIO_SIG102_IN_SEL_M  (BIT(6))
-#define GPIO_SIG102_IN_SEL_V  0x1
-#define GPIO_SIG102_IN_SEL_S  6
-/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC102_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC102_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC102_IN_INV_SEL_V  0x1
-#define GPIO_FUNC102_IN_INV_SEL_S  5
-/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC102_IN_SEL  0x0000001F
-#define GPIO_FUNC102_IN_SEL_M  ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
-#define GPIO_FUNC102_IN_SEL_V  0x1F
-#define GPIO_FUNC102_IN_SEL_S  0
-
-#define GPIO_FUNC103_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F0)
-/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG103_IN_SEL  (BIT(6))
-#define GPIO_SIG103_IN_SEL_M  (BIT(6))
-#define GPIO_SIG103_IN_SEL_V  0x1
-#define GPIO_SIG103_IN_SEL_S  6
-/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC103_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC103_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC103_IN_INV_SEL_V  0x1
-#define GPIO_FUNC103_IN_INV_SEL_S  5
-/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC103_IN_SEL  0x0000001F
-#define GPIO_FUNC103_IN_SEL_M  ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
-#define GPIO_FUNC103_IN_SEL_V  0x1F
-#define GPIO_FUNC103_IN_SEL_S  0
-
-#define GPIO_FUNC104_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F4)
-/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG104_IN_SEL  (BIT(6))
-#define GPIO_SIG104_IN_SEL_M  (BIT(6))
-#define GPIO_SIG104_IN_SEL_V  0x1
-#define GPIO_SIG104_IN_SEL_S  6
-/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC104_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC104_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC104_IN_INV_SEL_V  0x1
-#define GPIO_FUNC104_IN_INV_SEL_S  5
-/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC104_IN_SEL  0x0000001F
-#define GPIO_FUNC104_IN_SEL_M  ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
-#define GPIO_FUNC104_IN_SEL_V  0x1F
-#define GPIO_FUNC104_IN_SEL_S  0
-
-#define GPIO_FUNC105_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F8)
-/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG105_IN_SEL  (BIT(6))
-#define GPIO_SIG105_IN_SEL_M  (BIT(6))
-#define GPIO_SIG105_IN_SEL_V  0x1
-#define GPIO_SIG105_IN_SEL_S  6
-/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC105_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC105_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC105_IN_INV_SEL_V  0x1
-#define GPIO_FUNC105_IN_INV_SEL_S  5
-/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC105_IN_SEL  0x0000001F
-#define GPIO_FUNC105_IN_SEL_M  ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
-#define GPIO_FUNC105_IN_SEL_V  0x1F
-#define GPIO_FUNC105_IN_SEL_S  0
-
-#define GPIO_FUNC106_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2FC)
-/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG106_IN_SEL  (BIT(6))
-#define GPIO_SIG106_IN_SEL_M  (BIT(6))
-#define GPIO_SIG106_IN_SEL_V  0x1
-#define GPIO_SIG106_IN_SEL_S  6
-/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC106_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC106_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC106_IN_INV_SEL_V  0x1
-#define GPIO_FUNC106_IN_INV_SEL_S  5
-/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC106_IN_SEL  0x0000001F
-#define GPIO_FUNC106_IN_SEL_M  ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
-#define GPIO_FUNC106_IN_SEL_V  0x1F
-#define GPIO_FUNC106_IN_SEL_S  0
-
-#define GPIO_FUNC107_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x300)
-/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG107_IN_SEL  (BIT(6))
-#define GPIO_SIG107_IN_SEL_M  (BIT(6))
-#define GPIO_SIG107_IN_SEL_V  0x1
-#define GPIO_SIG107_IN_SEL_S  6
-/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC107_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC107_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC107_IN_INV_SEL_V  0x1
-#define GPIO_FUNC107_IN_INV_SEL_S  5
-/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC107_IN_SEL  0x0000001F
-#define GPIO_FUNC107_IN_SEL_M  ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
-#define GPIO_FUNC107_IN_SEL_V  0x1F
-#define GPIO_FUNC107_IN_SEL_S  0
-
-#define GPIO_FUNC108_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x304)
-/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG108_IN_SEL  (BIT(6))
-#define GPIO_SIG108_IN_SEL_M  (BIT(6))
-#define GPIO_SIG108_IN_SEL_V  0x1
-#define GPIO_SIG108_IN_SEL_S  6
-/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC108_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC108_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC108_IN_INV_SEL_V  0x1
-#define GPIO_FUNC108_IN_INV_SEL_S  5
-/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC108_IN_SEL  0x0000001F
-#define GPIO_FUNC108_IN_SEL_M  ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
-#define GPIO_FUNC108_IN_SEL_V  0x1F
-#define GPIO_FUNC108_IN_SEL_S  0
-
-#define GPIO_FUNC109_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x308)
-/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG109_IN_SEL  (BIT(6))
-#define GPIO_SIG109_IN_SEL_M  (BIT(6))
-#define GPIO_SIG109_IN_SEL_V  0x1
-#define GPIO_SIG109_IN_SEL_S  6
-/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC109_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC109_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC109_IN_INV_SEL_V  0x1
-#define GPIO_FUNC109_IN_INV_SEL_S  5
-/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC109_IN_SEL  0x0000001F
-#define GPIO_FUNC109_IN_SEL_M  ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
-#define GPIO_FUNC109_IN_SEL_V  0x1F
-#define GPIO_FUNC109_IN_SEL_S  0
-
-#define GPIO_FUNC110_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x30C)
-/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG110_IN_SEL  (BIT(6))
-#define GPIO_SIG110_IN_SEL_M  (BIT(6))
-#define GPIO_SIG110_IN_SEL_V  0x1
-#define GPIO_SIG110_IN_SEL_S  6
-/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC110_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC110_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC110_IN_INV_SEL_V  0x1
-#define GPIO_FUNC110_IN_INV_SEL_S  5
-/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC110_IN_SEL  0x0000001F
-#define GPIO_FUNC110_IN_SEL_M  ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
-#define GPIO_FUNC110_IN_SEL_V  0x1F
-#define GPIO_FUNC110_IN_SEL_S  0
-
-#define GPIO_FUNC111_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x310)
-/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG111_IN_SEL  (BIT(6))
-#define GPIO_SIG111_IN_SEL_M  (BIT(6))
-#define GPIO_SIG111_IN_SEL_V  0x1
-#define GPIO_SIG111_IN_SEL_S  6
-/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC111_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC111_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC111_IN_INV_SEL_V  0x1
-#define GPIO_FUNC111_IN_INV_SEL_S  5
-/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC111_IN_SEL  0x0000001F
-#define GPIO_FUNC111_IN_SEL_M  ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
-#define GPIO_FUNC111_IN_SEL_V  0x1F
-#define GPIO_FUNC111_IN_SEL_S  0
-
-#define GPIO_FUNC112_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x314)
-/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG112_IN_SEL  (BIT(6))
-#define GPIO_SIG112_IN_SEL_M  (BIT(6))
-#define GPIO_SIG112_IN_SEL_V  0x1
-#define GPIO_SIG112_IN_SEL_S  6
-/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC112_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC112_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC112_IN_INV_SEL_V  0x1
-#define GPIO_FUNC112_IN_INV_SEL_S  5
-/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC112_IN_SEL  0x0000001F
-#define GPIO_FUNC112_IN_SEL_M  ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
-#define GPIO_FUNC112_IN_SEL_V  0x1F
-#define GPIO_FUNC112_IN_SEL_S  0
-
-#define GPIO_FUNC113_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x318)
-/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG113_IN_SEL  (BIT(6))
-#define GPIO_SIG113_IN_SEL_M  (BIT(6))
-#define GPIO_SIG113_IN_SEL_V  0x1
-#define GPIO_SIG113_IN_SEL_S  6
-/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC113_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC113_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC113_IN_INV_SEL_V  0x1
-#define GPIO_FUNC113_IN_INV_SEL_S  5
-/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC113_IN_SEL  0x0000001F
-#define GPIO_FUNC113_IN_SEL_M  ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
-#define GPIO_FUNC113_IN_SEL_V  0x1F
-#define GPIO_FUNC113_IN_SEL_S  0
-
-#define GPIO_FUNC114_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x31C)
-/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG114_IN_SEL  (BIT(6))
-#define GPIO_SIG114_IN_SEL_M  (BIT(6))
-#define GPIO_SIG114_IN_SEL_V  0x1
-#define GPIO_SIG114_IN_SEL_S  6
-/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC114_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC114_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC114_IN_INV_SEL_V  0x1
-#define GPIO_FUNC114_IN_INV_SEL_S  5
-/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC114_IN_SEL  0x0000001F
-#define GPIO_FUNC114_IN_SEL_M  ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
-#define GPIO_FUNC114_IN_SEL_V  0x1F
-#define GPIO_FUNC114_IN_SEL_S  0
-
-#define GPIO_FUNC115_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x320)
-/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG115_IN_SEL  (BIT(6))
-#define GPIO_SIG115_IN_SEL_M  (BIT(6))
-#define GPIO_SIG115_IN_SEL_V  0x1
-#define GPIO_SIG115_IN_SEL_S  6
-/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC115_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC115_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC115_IN_INV_SEL_V  0x1
-#define GPIO_FUNC115_IN_INV_SEL_S  5
-/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC115_IN_SEL  0x0000001F
-#define GPIO_FUNC115_IN_SEL_M  ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
-#define GPIO_FUNC115_IN_SEL_V  0x1F
-#define GPIO_FUNC115_IN_SEL_S  0
-
-#define GPIO_FUNC116_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x324)
-/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG116_IN_SEL  (BIT(6))
-#define GPIO_SIG116_IN_SEL_M  (BIT(6))
-#define GPIO_SIG116_IN_SEL_V  0x1
-#define GPIO_SIG116_IN_SEL_S  6
-/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC116_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC116_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC116_IN_INV_SEL_V  0x1
-#define GPIO_FUNC116_IN_INV_SEL_S  5
-/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC116_IN_SEL  0x0000001F
-#define GPIO_FUNC116_IN_SEL_M  ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
-#define GPIO_FUNC116_IN_SEL_V  0x1F
-#define GPIO_FUNC116_IN_SEL_S  0
-
-#define GPIO_FUNC117_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x328)
-/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG117_IN_SEL  (BIT(6))
-#define GPIO_SIG117_IN_SEL_M  (BIT(6))
-#define GPIO_SIG117_IN_SEL_V  0x1
-#define GPIO_SIG117_IN_SEL_S  6
-/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC117_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC117_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC117_IN_INV_SEL_V  0x1
-#define GPIO_FUNC117_IN_INV_SEL_S  5
-/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC117_IN_SEL  0x0000001F
-#define GPIO_FUNC117_IN_SEL_M  ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
-#define GPIO_FUNC117_IN_SEL_V  0x1F
-#define GPIO_FUNC117_IN_SEL_S  0
-
-#define GPIO_FUNC118_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x32C)
-/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG118_IN_SEL  (BIT(6))
-#define GPIO_SIG118_IN_SEL_M  (BIT(6))
-#define GPIO_SIG118_IN_SEL_V  0x1
-#define GPIO_SIG118_IN_SEL_S  6
-/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC118_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC118_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC118_IN_INV_SEL_V  0x1
-#define GPIO_FUNC118_IN_INV_SEL_S  5
-/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC118_IN_SEL  0x0000001F
-#define GPIO_FUNC118_IN_SEL_M  ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
-#define GPIO_FUNC118_IN_SEL_V  0x1F
-#define GPIO_FUNC118_IN_SEL_S  0
-
-#define GPIO_FUNC119_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x330)
-/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG119_IN_SEL  (BIT(6))
-#define GPIO_SIG119_IN_SEL_M  (BIT(6))
-#define GPIO_SIG119_IN_SEL_V  0x1
-#define GPIO_SIG119_IN_SEL_S  6
-/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC119_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC119_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC119_IN_INV_SEL_V  0x1
-#define GPIO_FUNC119_IN_INV_SEL_S  5
-/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC119_IN_SEL  0x0000001F
-#define GPIO_FUNC119_IN_SEL_M  ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
-#define GPIO_FUNC119_IN_SEL_V  0x1F
-#define GPIO_FUNC119_IN_SEL_S  0
-
-#define GPIO_FUNC120_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x334)
-/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG120_IN_SEL  (BIT(6))
-#define GPIO_SIG120_IN_SEL_M  (BIT(6))
-#define GPIO_SIG120_IN_SEL_V  0x1
-#define GPIO_SIG120_IN_SEL_S  6
-/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC120_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC120_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC120_IN_INV_SEL_V  0x1
-#define GPIO_FUNC120_IN_INV_SEL_S  5
-/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC120_IN_SEL  0x0000001F
-#define GPIO_FUNC120_IN_SEL_M  ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
-#define GPIO_FUNC120_IN_SEL_V  0x1F
-#define GPIO_FUNC120_IN_SEL_S  0
-
-#define GPIO_FUNC121_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x338)
-/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG121_IN_SEL  (BIT(6))
-#define GPIO_SIG121_IN_SEL_M  (BIT(6))
-#define GPIO_SIG121_IN_SEL_V  0x1
-#define GPIO_SIG121_IN_SEL_S  6
-/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC121_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC121_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC121_IN_INV_SEL_V  0x1
-#define GPIO_FUNC121_IN_INV_SEL_S  5
-/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC121_IN_SEL  0x0000001F
-#define GPIO_FUNC121_IN_SEL_M  ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
-#define GPIO_FUNC121_IN_SEL_V  0x1F
-#define GPIO_FUNC121_IN_SEL_S  0
-
-#define GPIO_FUNC122_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x33C)
-/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG122_IN_SEL  (BIT(6))
-#define GPIO_SIG122_IN_SEL_M  (BIT(6))
-#define GPIO_SIG122_IN_SEL_V  0x1
-#define GPIO_SIG122_IN_SEL_S  6
-/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC122_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC122_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC122_IN_INV_SEL_V  0x1
-#define GPIO_FUNC122_IN_INV_SEL_S  5
-/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC122_IN_SEL  0x0000001F
-#define GPIO_FUNC122_IN_SEL_M  ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
-#define GPIO_FUNC122_IN_SEL_V  0x1F
-#define GPIO_FUNC122_IN_SEL_S  0
-
-#define GPIO_FUNC123_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x340)
-/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG123_IN_SEL  (BIT(6))
-#define GPIO_SIG123_IN_SEL_M  (BIT(6))
-#define GPIO_SIG123_IN_SEL_V  0x1
-#define GPIO_SIG123_IN_SEL_S  6
-/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC123_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC123_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC123_IN_INV_SEL_V  0x1
-#define GPIO_FUNC123_IN_INV_SEL_S  5
-/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC123_IN_SEL  0x0000001F
-#define GPIO_FUNC123_IN_SEL_M  ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
-#define GPIO_FUNC123_IN_SEL_V  0x1F
-#define GPIO_FUNC123_IN_SEL_S  0
-
-#define GPIO_FUNC124_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x344)
-/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG124_IN_SEL  (BIT(6))
-#define GPIO_SIG124_IN_SEL_M  (BIT(6))
-#define GPIO_SIG124_IN_SEL_V  0x1
-#define GPIO_SIG124_IN_SEL_S  6
-/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC124_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC124_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC124_IN_INV_SEL_V  0x1
-#define GPIO_FUNC124_IN_INV_SEL_S  5
-/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC124_IN_SEL  0x0000001F
-#define GPIO_FUNC124_IN_SEL_M  ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
-#define GPIO_FUNC124_IN_SEL_V  0x1F
-#define GPIO_FUNC124_IN_SEL_S  0
-
-#define GPIO_FUNC125_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x348)
-/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG125_IN_SEL  (BIT(6))
-#define GPIO_SIG125_IN_SEL_M  (BIT(6))
-#define GPIO_SIG125_IN_SEL_V  0x1
-#define GPIO_SIG125_IN_SEL_S  6
-/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC125_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC125_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC125_IN_INV_SEL_V  0x1
-#define GPIO_FUNC125_IN_INV_SEL_S  5
-/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC125_IN_SEL  0x0000001F
-#define GPIO_FUNC125_IN_SEL_M  ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
-#define GPIO_FUNC125_IN_SEL_V  0x1F
-#define GPIO_FUNC125_IN_SEL_S  0
-
-#define GPIO_FUNC126_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x34C)
-/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG126_IN_SEL  (BIT(6))
-#define GPIO_SIG126_IN_SEL_M  (BIT(6))
-#define GPIO_SIG126_IN_SEL_V  0x1
-#define GPIO_SIG126_IN_SEL_S  6
-/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC126_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC126_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC126_IN_INV_SEL_V  0x1
-#define GPIO_FUNC126_IN_INV_SEL_S  5
-/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC126_IN_SEL  0x0000001F
-#define GPIO_FUNC126_IN_SEL_M  ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
-#define GPIO_FUNC126_IN_SEL_V  0x1F
-#define GPIO_FUNC126_IN_SEL_S  0
-
-#define GPIO_FUNC127_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x350)
-/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SIG127_IN_SEL  (BIT(6))
-#define GPIO_SIG127_IN_SEL_M  (BIT(6))
-#define GPIO_SIG127_IN_SEL_V  0x1
-#define GPIO_SIG127_IN_SEL_S  6
-/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC127_IN_INV_SEL  (BIT(5))
-#define GPIO_FUNC127_IN_INV_SEL_M  (BIT(5))
-#define GPIO_FUNC127_IN_INV_SEL_V  0x1
-#define GPIO_FUNC127_IN_INV_SEL_S  5
-/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
-/*description: */
-#define GPIO_FUNC127_IN_SEL  0x0000001F
-#define GPIO_FUNC127_IN_SEL_M  ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
-#define GPIO_FUNC127_IN_SEL_V  0x1F
-#define GPIO_FUNC127_IN_SEL_S  0
-
-#define GPIO_FUNC0_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x554)
-/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC0_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC0_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC0_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC0_OEN_INV_SEL_S  10
-/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC0_OEN_SEL  (BIT(9))
-#define GPIO_FUNC0_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC0_OEN_SEL_V  0x1
-#define GPIO_FUNC0_OEN_SEL_S  9
-/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC0_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC0_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC0_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC0_OUT_INV_SEL_S  8
-/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC0_OUT_SEL  0x000000FF
-#define GPIO_FUNC0_OUT_SEL_M  ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
-#define GPIO_FUNC0_OUT_SEL_V  0xFF
-#define GPIO_FUNC0_OUT_SEL_S  0
-
-#define GPIO_FUNC1_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x558)
-/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC1_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC1_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC1_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC1_OEN_INV_SEL_S  10
-/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC1_OEN_SEL  (BIT(9))
-#define GPIO_FUNC1_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC1_OEN_SEL_V  0x1
-#define GPIO_FUNC1_OEN_SEL_S  9
-/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC1_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC1_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC1_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC1_OUT_INV_SEL_S  8
-/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC1_OUT_SEL  0x000000FF
-#define GPIO_FUNC1_OUT_SEL_M  ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
-#define GPIO_FUNC1_OUT_SEL_V  0xFF
-#define GPIO_FUNC1_OUT_SEL_S  0
-
-#define GPIO_FUNC2_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x55C)
-/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC2_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC2_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC2_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC2_OEN_INV_SEL_S  10
-/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC2_OEN_SEL  (BIT(9))
-#define GPIO_FUNC2_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC2_OEN_SEL_V  0x1
-#define GPIO_FUNC2_OEN_SEL_S  9
-/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC2_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC2_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC2_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC2_OUT_INV_SEL_S  8
-/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC2_OUT_SEL  0x000000FF
-#define GPIO_FUNC2_OUT_SEL_M  ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
-#define GPIO_FUNC2_OUT_SEL_V  0xFF
-#define GPIO_FUNC2_OUT_SEL_S  0
-
-#define GPIO_FUNC3_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x560)
-/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC3_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC3_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC3_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC3_OEN_INV_SEL_S  10
-/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC3_OEN_SEL  (BIT(9))
-#define GPIO_FUNC3_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC3_OEN_SEL_V  0x1
-#define GPIO_FUNC3_OEN_SEL_S  9
-/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC3_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC3_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC3_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC3_OUT_INV_SEL_S  8
-/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC3_OUT_SEL  0x000000FF
-#define GPIO_FUNC3_OUT_SEL_M  ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
-#define GPIO_FUNC3_OUT_SEL_V  0xFF
-#define GPIO_FUNC3_OUT_SEL_S  0
-
-#define GPIO_FUNC4_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x564)
-/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC4_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC4_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC4_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC4_OEN_INV_SEL_S  10
-/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC4_OEN_SEL  (BIT(9))
-#define GPIO_FUNC4_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC4_OEN_SEL_V  0x1
-#define GPIO_FUNC4_OEN_SEL_S  9
-/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC4_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC4_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC4_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC4_OUT_INV_SEL_S  8
-/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC4_OUT_SEL  0x000000FF
-#define GPIO_FUNC4_OUT_SEL_M  ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
-#define GPIO_FUNC4_OUT_SEL_V  0xFF
-#define GPIO_FUNC4_OUT_SEL_S  0
-
-#define GPIO_FUNC5_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x568)
-/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC5_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC5_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC5_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC5_OEN_INV_SEL_S  10
-/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC5_OEN_SEL  (BIT(9))
-#define GPIO_FUNC5_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC5_OEN_SEL_V  0x1
-#define GPIO_FUNC5_OEN_SEL_S  9
-/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC5_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC5_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC5_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC5_OUT_INV_SEL_S  8
-/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC5_OUT_SEL  0x000000FF
-#define GPIO_FUNC5_OUT_SEL_M  ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
-#define GPIO_FUNC5_OUT_SEL_V  0xFF
-#define GPIO_FUNC5_OUT_SEL_S  0
-
-#define GPIO_FUNC6_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x56C)
-/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC6_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC6_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC6_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC6_OEN_INV_SEL_S  10
-/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC6_OEN_SEL  (BIT(9))
-#define GPIO_FUNC6_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC6_OEN_SEL_V  0x1
-#define GPIO_FUNC6_OEN_SEL_S  9
-/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC6_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC6_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC6_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC6_OUT_INV_SEL_S  8
-/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC6_OUT_SEL  0x000000FF
-#define GPIO_FUNC6_OUT_SEL_M  ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
-#define GPIO_FUNC6_OUT_SEL_V  0xFF
-#define GPIO_FUNC6_OUT_SEL_S  0
-
-#define GPIO_FUNC7_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x570)
-/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC7_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC7_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC7_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC7_OEN_INV_SEL_S  10
-/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC7_OEN_SEL  (BIT(9))
-#define GPIO_FUNC7_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC7_OEN_SEL_V  0x1
-#define GPIO_FUNC7_OEN_SEL_S  9
-/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC7_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC7_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC7_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC7_OUT_INV_SEL_S  8
-/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC7_OUT_SEL  0x000000FF
-#define GPIO_FUNC7_OUT_SEL_M  ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
-#define GPIO_FUNC7_OUT_SEL_V  0xFF
-#define GPIO_FUNC7_OUT_SEL_S  0
-
-#define GPIO_FUNC8_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x574)
-/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC8_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC8_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC8_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC8_OEN_INV_SEL_S  10
-/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC8_OEN_SEL  (BIT(9))
-#define GPIO_FUNC8_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC8_OEN_SEL_V  0x1
-#define GPIO_FUNC8_OEN_SEL_S  9
-/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC8_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC8_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC8_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC8_OUT_INV_SEL_S  8
-/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC8_OUT_SEL  0x000000FF
-#define GPIO_FUNC8_OUT_SEL_M  ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
-#define GPIO_FUNC8_OUT_SEL_V  0xFF
-#define GPIO_FUNC8_OUT_SEL_S  0
-
-#define GPIO_FUNC9_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x578)
-/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC9_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC9_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC9_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC9_OEN_INV_SEL_S  10
-/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC9_OEN_SEL  (BIT(9))
-#define GPIO_FUNC9_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC9_OEN_SEL_V  0x1
-#define GPIO_FUNC9_OEN_SEL_S  9
-/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC9_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC9_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC9_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC9_OUT_INV_SEL_S  8
-/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC9_OUT_SEL  0x000000FF
-#define GPIO_FUNC9_OUT_SEL_M  ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
-#define GPIO_FUNC9_OUT_SEL_V  0xFF
-#define GPIO_FUNC9_OUT_SEL_S  0
-
-#define GPIO_FUNC10_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x57C)
-/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC10_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC10_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC10_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC10_OEN_INV_SEL_S  10
-/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC10_OEN_SEL  (BIT(9))
-#define GPIO_FUNC10_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC10_OEN_SEL_V  0x1
-#define GPIO_FUNC10_OEN_SEL_S  9
-/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC10_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC10_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC10_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC10_OUT_INV_SEL_S  8
-/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC10_OUT_SEL  0x000000FF
-#define GPIO_FUNC10_OUT_SEL_M  ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
-#define GPIO_FUNC10_OUT_SEL_V  0xFF
-#define GPIO_FUNC10_OUT_SEL_S  0
-
-#define GPIO_FUNC11_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x580)
-/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC11_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC11_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC11_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC11_OEN_INV_SEL_S  10
-/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC11_OEN_SEL  (BIT(9))
-#define GPIO_FUNC11_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC11_OEN_SEL_V  0x1
-#define GPIO_FUNC11_OEN_SEL_S  9
-/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC11_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC11_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC11_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC11_OUT_INV_SEL_S  8
-/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC11_OUT_SEL  0x000000FF
-#define GPIO_FUNC11_OUT_SEL_M  ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
-#define GPIO_FUNC11_OUT_SEL_V  0xFF
-#define GPIO_FUNC11_OUT_SEL_S  0
-
-#define GPIO_FUNC12_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x584)
-/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC12_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC12_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC12_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC12_OEN_INV_SEL_S  10
-/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC12_OEN_SEL  (BIT(9))
-#define GPIO_FUNC12_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC12_OEN_SEL_V  0x1
-#define GPIO_FUNC12_OEN_SEL_S  9
-/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC12_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC12_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC12_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC12_OUT_INV_SEL_S  8
-/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC12_OUT_SEL  0x000000FF
-#define GPIO_FUNC12_OUT_SEL_M  ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
-#define GPIO_FUNC12_OUT_SEL_V  0xFF
-#define GPIO_FUNC12_OUT_SEL_S  0
-
-#define GPIO_FUNC13_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x588)
-/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC13_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC13_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC13_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC13_OEN_INV_SEL_S  10
-/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC13_OEN_SEL  (BIT(9))
-#define GPIO_FUNC13_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC13_OEN_SEL_V  0x1
-#define GPIO_FUNC13_OEN_SEL_S  9
-/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC13_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC13_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC13_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC13_OUT_INV_SEL_S  8
-/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC13_OUT_SEL  0x000000FF
-#define GPIO_FUNC13_OUT_SEL_M  ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
-#define GPIO_FUNC13_OUT_SEL_V  0xFF
-#define GPIO_FUNC13_OUT_SEL_S  0
-
-#define GPIO_FUNC14_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x58C)
-/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC14_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC14_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC14_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC14_OEN_INV_SEL_S  10
-/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC14_OEN_SEL  (BIT(9))
-#define GPIO_FUNC14_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC14_OEN_SEL_V  0x1
-#define GPIO_FUNC14_OEN_SEL_S  9
-/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC14_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC14_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC14_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC14_OUT_INV_SEL_S  8
-/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC14_OUT_SEL  0x000000FF
-#define GPIO_FUNC14_OUT_SEL_M  ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
-#define GPIO_FUNC14_OUT_SEL_V  0xFF
-#define GPIO_FUNC14_OUT_SEL_S  0
-
-#define GPIO_FUNC15_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x590)
-/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC15_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC15_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC15_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC15_OEN_INV_SEL_S  10
-/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC15_OEN_SEL  (BIT(9))
-#define GPIO_FUNC15_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC15_OEN_SEL_V  0x1
-#define GPIO_FUNC15_OEN_SEL_S  9
-/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC15_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC15_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC15_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC15_OUT_INV_SEL_S  8
-/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC15_OUT_SEL  0x000000FF
-#define GPIO_FUNC15_OUT_SEL_M  ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
-#define GPIO_FUNC15_OUT_SEL_V  0xFF
-#define GPIO_FUNC15_OUT_SEL_S  0
-
-#define GPIO_FUNC16_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x594)
-/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC16_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC16_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC16_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC16_OEN_INV_SEL_S  10
-/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC16_OEN_SEL  (BIT(9))
-#define GPIO_FUNC16_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC16_OEN_SEL_V  0x1
-#define GPIO_FUNC16_OEN_SEL_S  9
-/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC16_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC16_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC16_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC16_OUT_INV_SEL_S  8
-/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC16_OUT_SEL  0x000000FF
-#define GPIO_FUNC16_OUT_SEL_M  ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
-#define GPIO_FUNC16_OUT_SEL_V  0xFF
-#define GPIO_FUNC16_OUT_SEL_S  0
-
-#define GPIO_FUNC17_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x598)
-/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC17_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC17_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC17_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC17_OEN_INV_SEL_S  10
-/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC17_OEN_SEL  (BIT(9))
-#define GPIO_FUNC17_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC17_OEN_SEL_V  0x1
-#define GPIO_FUNC17_OEN_SEL_S  9
-/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC17_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC17_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC17_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC17_OUT_INV_SEL_S  8
-/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC17_OUT_SEL  0x000000FF
-#define GPIO_FUNC17_OUT_SEL_M  ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
-#define GPIO_FUNC17_OUT_SEL_V  0xFF
-#define GPIO_FUNC17_OUT_SEL_S  0
-
-#define GPIO_FUNC18_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x59C)
-/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC18_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC18_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC18_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC18_OEN_INV_SEL_S  10
-/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC18_OEN_SEL  (BIT(9))
-#define GPIO_FUNC18_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC18_OEN_SEL_V  0x1
-#define GPIO_FUNC18_OEN_SEL_S  9
-/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC18_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC18_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC18_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC18_OUT_INV_SEL_S  8
-/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC18_OUT_SEL  0x000000FF
-#define GPIO_FUNC18_OUT_SEL_M  ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
-#define GPIO_FUNC18_OUT_SEL_V  0xFF
-#define GPIO_FUNC18_OUT_SEL_S  0
-
-#define GPIO_FUNC19_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A0)
-/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC19_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC19_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC19_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC19_OEN_INV_SEL_S  10
-/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC19_OEN_SEL  (BIT(9))
-#define GPIO_FUNC19_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC19_OEN_SEL_V  0x1
-#define GPIO_FUNC19_OEN_SEL_S  9
-/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC19_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC19_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC19_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC19_OUT_INV_SEL_S  8
-/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC19_OUT_SEL  0x000000FF
-#define GPIO_FUNC19_OUT_SEL_M  ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
-#define GPIO_FUNC19_OUT_SEL_V  0xFF
-#define GPIO_FUNC19_OUT_SEL_S  0
-
-#define GPIO_FUNC20_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A4)
-/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC20_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC20_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC20_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC20_OEN_INV_SEL_S  10
-/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC20_OEN_SEL  (BIT(9))
-#define GPIO_FUNC20_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC20_OEN_SEL_V  0x1
-#define GPIO_FUNC20_OEN_SEL_S  9
-/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC20_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC20_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC20_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC20_OUT_INV_SEL_S  8
-/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC20_OUT_SEL  0x000000FF
-#define GPIO_FUNC20_OUT_SEL_M  ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
-#define GPIO_FUNC20_OUT_SEL_V  0xFF
-#define GPIO_FUNC20_OUT_SEL_S  0
-
-#define GPIO_FUNC21_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A8)
-/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC21_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC21_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC21_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC21_OEN_INV_SEL_S  10
-/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC21_OEN_SEL  (BIT(9))
-#define GPIO_FUNC21_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC21_OEN_SEL_V  0x1
-#define GPIO_FUNC21_OEN_SEL_S  9
-/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC21_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC21_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC21_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC21_OUT_INV_SEL_S  8
-/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC21_OUT_SEL  0x000000FF
-#define GPIO_FUNC21_OUT_SEL_M  ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
-#define GPIO_FUNC21_OUT_SEL_V  0xFF
-#define GPIO_FUNC21_OUT_SEL_S  0
-
-#define GPIO_FUNC22_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5AC)
-/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC22_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC22_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC22_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC22_OEN_INV_SEL_S  10
-/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC22_OEN_SEL  (BIT(9))
-#define GPIO_FUNC22_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC22_OEN_SEL_V  0x1
-#define GPIO_FUNC22_OEN_SEL_S  9
-/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC22_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC22_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC22_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC22_OUT_INV_SEL_S  8
-/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC22_OUT_SEL  0x000000FF
-#define GPIO_FUNC22_OUT_SEL_M  ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
-#define GPIO_FUNC22_OUT_SEL_V  0xFF
-#define GPIO_FUNC22_OUT_SEL_S  0
-
-#define GPIO_FUNC23_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B0)
-/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC23_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC23_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC23_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC23_OEN_INV_SEL_S  10
-/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC23_OEN_SEL  (BIT(9))
-#define GPIO_FUNC23_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC23_OEN_SEL_V  0x1
-#define GPIO_FUNC23_OEN_SEL_S  9
-/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC23_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC23_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC23_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC23_OUT_INV_SEL_S  8
-/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC23_OUT_SEL  0x000000FF
-#define GPIO_FUNC23_OUT_SEL_M  ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
-#define GPIO_FUNC23_OUT_SEL_V  0xFF
-#define GPIO_FUNC23_OUT_SEL_S  0
-
-#define GPIO_FUNC24_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B4)
-/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC24_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC24_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC24_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC24_OEN_INV_SEL_S  10
-/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC24_OEN_SEL  (BIT(9))
-#define GPIO_FUNC24_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC24_OEN_SEL_V  0x1
-#define GPIO_FUNC24_OEN_SEL_S  9
-/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC24_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC24_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC24_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC24_OUT_INV_SEL_S  8
-/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC24_OUT_SEL  0x000000FF
-#define GPIO_FUNC24_OUT_SEL_M  ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
-#define GPIO_FUNC24_OUT_SEL_V  0xFF
-#define GPIO_FUNC24_OUT_SEL_S  0
-
-#define GPIO_FUNC25_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B8)
-/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC25_OEN_INV_SEL  (BIT(10))
-#define GPIO_FUNC25_OEN_INV_SEL_M  (BIT(10))
-#define GPIO_FUNC25_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC25_OEN_INV_SEL_S  10
-/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC25_OEN_SEL  (BIT(9))
-#define GPIO_FUNC25_OEN_SEL_M  (BIT(9))
-#define GPIO_FUNC25_OEN_SEL_V  0x1
-#define GPIO_FUNC25_OEN_SEL_S  9
-/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_FUNC25_OUT_INV_SEL  (BIT(8))
-#define GPIO_FUNC25_OUT_INV_SEL_M  (BIT(8))
-#define GPIO_FUNC25_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC25_OUT_INV_SEL_S  8
-/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
-/*description: */
-#define GPIO_FUNC25_OUT_SEL  0x000000FF
-#define GPIO_FUNC25_OUT_SEL_M  ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
-#define GPIO_FUNC25_OUT_SEL_V  0xFF
-#define GPIO_FUNC25_OUT_SEL_S  0
-
-#define GPIO_CLOCK_GATE_REG          (DR_REG_GPIO_BASE + 0x62C)
-/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define GPIO_CLK_EN  (BIT(0))
-#define GPIO_CLK_EN_M  (BIT(0))
-#define GPIO_CLK_EN_V  0x1
-#define GPIO_CLK_EN_S  0
-
-#define GPIO_DATE_REG          (DR_REG_GPIO_BASE + 0x6FC)
-/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006130 ; */
-/*description: */
-#define GPIO_DATE  0x0FFFFFFF
-#define GPIO_DATE_M  ((GPIO_DATE_V)<<(GPIO_DATE_S))
-#define GPIO_DATE_V  0xFFFFFFF
-#define GPIO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_GPIO_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/gpio_sd_reg.h b/components/soc/esp32c3/include/soc/gpio_sd_reg.h
deleted file mode 100644
index 3c72df5d404..00000000000
--- a/components/soc/esp32c3/include/soc/gpio_sd_reg.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0000)
-/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD0_PRESCALE  0x000000FF
-#define GPIO_SD0_PRESCALE_M  ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
-#define GPIO_SD0_PRESCALE_V  0xFF
-#define GPIO_SD0_PRESCALE_S  8
-/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD0_IN  0x000000FF
-#define GPIO_SD0_IN_M  ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
-#define GPIO_SD0_IN_V  0xFF
-#define GPIO_SD0_IN_S  0
-
-#define GPIO_SIGMADELTA1_REG          (DR_REG_GPIO_SD_BASE + 0x0004)
-/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD1_PRESCALE  0x000000FF
-#define GPIO_SD1_PRESCALE_M  ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
-#define GPIO_SD1_PRESCALE_V  0xFF
-#define GPIO_SD1_PRESCALE_S  8
-/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD1_IN  0x000000FF
-#define GPIO_SD1_IN_M  ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
-#define GPIO_SD1_IN_V  0xFF
-#define GPIO_SD1_IN_S  0
-
-#define GPIO_SIGMADELTA2_REG          (DR_REG_GPIO_SD_BASE + 0x0008)
-/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD2_PRESCALE  0x000000FF
-#define GPIO_SD2_PRESCALE_M  ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
-#define GPIO_SD2_PRESCALE_V  0xFF
-#define GPIO_SD2_PRESCALE_S  8
-/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD2_IN  0x000000FF
-#define GPIO_SD2_IN_M  ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
-#define GPIO_SD2_IN_V  0xFF
-#define GPIO_SD2_IN_S  0
-
-#define GPIO_SIGMADELTA3_REG          (DR_REG_GPIO_SD_BASE + 0x000c)
-/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: */
-#define GPIO_SD3_PRESCALE  0x000000FF
-#define GPIO_SD3_PRESCALE_M  ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
-#define GPIO_SD3_PRESCALE_V  0xFF
-#define GPIO_SD3_PRESCALE_S  8
-/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define GPIO_SD3_IN  0x000000FF
-#define GPIO_SD3_IN_M  ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
-#define GPIO_SD3_IN_V  0xFF
-#define GPIO_SD3_IN_S  0
-
-#define GPIO_SIGMADELTA_CG_REG          (DR_REG_GPIO_SD_BASE + 0x0020)
-/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SD_CLK_EN  (BIT(31))
-#define GPIO_SD_CLK_EN_M  (BIT(31))
-#define GPIO_SD_CLK_EN_V  0x1
-#define GPIO_SD_CLK_EN_S  31
-
-#define GPIO_SIGMADELTA_MISC_REG          (DR_REG_GPIO_SD_BASE + 0x0024)
-/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define GPIO_SPI_SWAP  (BIT(31))
-#define GPIO_SPI_SWAP_M  (BIT(31))
-#define GPIO_SPI_SWAP_V  0x1
-#define GPIO_SPI_SWAP_S  31
-/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: */
-#define GPIO_FUNCTION_CLK_EN  (BIT(30))
-#define GPIO_FUNCTION_CLK_EN_M  (BIT(30))
-#define GPIO_FUNCTION_CLK_EN_V  0x1
-#define GPIO_FUNCTION_CLK_EN_S  30
-
-#define GPIO_SIGMADELTA_VERSION_REG          (DR_REG_GPIO_SD_BASE + 0x0028)
-/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006230 ; */
-/*description: */
-#define GPIO_SD_DATE  0x0FFFFFFF
-#define GPIO_SD_DATE_M  ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
-#define GPIO_SD_DATE_V  0xFFFFFFF
-#define GPIO_SD_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/gpio_struct.h b/components/soc/esp32c3/include/soc/gpio_struct.h
deleted file mode 100644
index 45f5e55412c..00000000000
--- a/components/soc/esp32c3/include/soc/gpio_struct.h
+++ /dev/null
@@ -1,437 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_STRUCT_H_
-#define _SOC_GPIO_STRUCT_H_
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct gpio_dev_s {
-    uint32_t bt_select;                               /**/
-    union {
-        struct {
-            uint32_t data:         26;
-            uint32_t reserved26:    6;
-        };
-        uint32_t val;
-    } out;
-    union {
-        struct {
-            uint32_t out_w1ts:  26;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } out_w1ts;
-    union {
-        struct {
-            uint32_t out_w1tc:  26;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } out_w1tc;
-    uint32_t reserved_10;
-    uint32_t reserved_14;
-    uint32_t reserved_18;
-    union {
-        struct {
-            uint32_t sel:        8;
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } sdio_select;
-    union {
-        struct {
-            uint32_t data:       26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } enable;
-    union {
-        struct {
-            uint32_t enable_w1ts:26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } enable_w1ts;
-    union {
-        struct {
-            uint32_t enable_w1tc:26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } enable_w1tc;
-    uint32_t reserved_2c;
-    uint32_t reserved_30;
-    uint32_t reserved_34;
-    union {
-        struct {
-            uint32_t strapping: 16;
-            uint32_t reserved16:16;
-        };
-        uint32_t val;
-    } strap;
-    union {
-        struct {
-            uint32_t data:        26;
-            uint32_t reserved26:   6;
-        };
-        uint32_t val;
-    } in;
-    uint32_t reserved_40;
-    union {
-        struct {
-            uint32_t intr_st:         26;
-            uint32_t reserved26:       6;
-        };
-        uint32_t val;
-    } status;
-    union {
-        struct {
-            uint32_t status_w1ts:26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } status_w1ts;
-    union {
-        struct {
-            uint32_t status_w1tc:26;
-            uint32_t reserved26:  6;
-        };
-        uint32_t val;
-    } status_w1tc;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    union {
-        struct {
-            uint32_t intr:      26;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } pcpu_int;
-    union {
-        struct {
-            uint32_t intr:          26;
-            uint32_t reserved26:     6;
-        };
-        uint32_t val;
-    } pcpu_nmi_int;
-    union {
-        struct {
-            uint32_t intr:      26;
-            uint32_t reserved26: 6;
-        };
-        uint32_t val;
-    } cpusdio_int;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    union {
-        struct {
-            uint32_t sync2_bypass:       2;
-            uint32_t pad_driver:         1;
-            uint32_t sync1_bypass:       2;
-            uint32_t reserved5:          2;
-            uint32_t int_type:           3;
-            uint32_t wakeup_enable:      1;
-            uint32_t config:             2;
-            uint32_t int_ena:            5;
-            uint32_t reserved18:        14;
-        };
-        uint32_t val;
-    } pin[26];
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    union {
-        struct {
-            uint32_t intr_st_next:         26;
-            uint32_t reserved26:            6;
-        };
-        uint32_t val;
-    } status_next;
-    uint32_t reserved_150;
-    union {
-        struct {
-            uint32_t func_sel:         5;
-            uint32_t sig_in_inv:       1;
-            uint32_t sig_in_sel:       1;
-            uint32_t reserved7:       25;
-        };
-        uint32_t val;
-    } func_in_sel_cfg[128];
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    uint32_t reserved_3fc;
-    uint32_t reserved_400;
-    uint32_t reserved_404;
-    uint32_t reserved_408;
-    uint32_t reserved_40c;
-    uint32_t reserved_410;
-    uint32_t reserved_414;
-    uint32_t reserved_418;
-    uint32_t reserved_41c;
-    uint32_t reserved_420;
-    uint32_t reserved_424;
-    uint32_t reserved_428;
-    uint32_t reserved_42c;
-    uint32_t reserved_430;
-    uint32_t reserved_434;
-    uint32_t reserved_438;
-    uint32_t reserved_43c;
-    uint32_t reserved_440;
-    uint32_t reserved_444;
-    uint32_t reserved_448;
-    uint32_t reserved_44c;
-    uint32_t reserved_450;
-    uint32_t reserved_454;
-    uint32_t reserved_458;
-    uint32_t reserved_45c;
-    uint32_t reserved_460;
-    uint32_t reserved_464;
-    uint32_t reserved_468;
-    uint32_t reserved_46c;
-    uint32_t reserved_470;
-    uint32_t reserved_474;
-    uint32_t reserved_478;
-    uint32_t reserved_47c;
-    uint32_t reserved_480;
-    uint32_t reserved_484;
-    uint32_t reserved_488;
-    uint32_t reserved_48c;
-    uint32_t reserved_490;
-    uint32_t reserved_494;
-    uint32_t reserved_498;
-    uint32_t reserved_49c;
-    uint32_t reserved_4a0;
-    uint32_t reserved_4a4;
-    uint32_t reserved_4a8;
-    uint32_t reserved_4ac;
-    uint32_t reserved_4b0;
-    uint32_t reserved_4b4;
-    uint32_t reserved_4b8;
-    uint32_t reserved_4bc;
-    uint32_t reserved_4c0;
-    uint32_t reserved_4c4;
-    uint32_t reserved_4c8;
-    uint32_t reserved_4cc;
-    uint32_t reserved_4d0;
-    uint32_t reserved_4d4;
-    uint32_t reserved_4d8;
-    uint32_t reserved_4dc;
-    uint32_t reserved_4e0;
-    uint32_t reserved_4e4;
-    uint32_t reserved_4e8;
-    uint32_t reserved_4ec;
-    uint32_t reserved_4f0;
-    uint32_t reserved_4f4;
-    uint32_t reserved_4f8;
-    uint32_t reserved_4fc;
-    uint32_t reserved_500;
-    uint32_t reserved_504;
-    uint32_t reserved_508;
-    uint32_t reserved_50c;
-    uint32_t reserved_510;
-    uint32_t reserved_514;
-    uint32_t reserved_518;
-    uint32_t reserved_51c;
-    uint32_t reserved_520;
-    uint32_t reserved_524;
-    uint32_t reserved_528;
-    uint32_t reserved_52c;
-    uint32_t reserved_530;
-    uint32_t reserved_534;
-    uint32_t reserved_538;
-    uint32_t reserved_53c;
-    uint32_t reserved_540;
-    uint32_t reserved_544;
-    uint32_t reserved_548;
-    uint32_t reserved_54c;
-    uint32_t reserved_550;
-    union {
-        struct {
-            uint32_t func_sel:          8;
-            uint32_t inv_sel:           1;
-            uint32_t oen_sel:           1;
-            uint32_t oen_inv_sel:       1;
-            uint32_t reserved11:       21;
-        };
-        uint32_t val;
-    } func_out_sel_cfg[26];
-    uint32_t reserved_5bc;
-    uint32_t reserved_5c0;
-    uint32_t reserved_5c4;
-    uint32_t reserved_5c8;
-    uint32_t reserved_5cc;
-    uint32_t reserved_5d0;
-    uint32_t reserved_5d4;
-    uint32_t reserved_5d8;
-    uint32_t reserved_5dc;
-    uint32_t reserved_5e0;
-    uint32_t reserved_5e4;
-    uint32_t reserved_5e8;
-    uint32_t reserved_5ec;
-    uint32_t reserved_5f0;
-    uint32_t reserved_5f4;
-    uint32_t reserved_5f8;
-    uint32_t reserved_5fc;
-    uint32_t reserved_600;
-    uint32_t reserved_604;
-    uint32_t reserved_608;
-    uint32_t reserved_60c;
-    uint32_t reserved_610;
-    uint32_t reserved_614;
-    uint32_t reserved_618;
-    uint32_t reserved_61c;
-    uint32_t reserved_620;
-    uint32_t reserved_624;
-    uint32_t reserved_628;
-    union {
-        struct {
-            uint32_t clk_en:     1;
-            uint32_t reserved1: 31;
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_630;
-    uint32_t reserved_634;
-    uint32_t reserved_638;
-    uint32_t reserved_63c;
-    uint32_t reserved_640;
-    uint32_t reserved_644;
-    uint32_t reserved_648;
-    uint32_t reserved_64c;
-    uint32_t reserved_650;
-    uint32_t reserved_654;
-    uint32_t reserved_658;
-    uint32_t reserved_65c;
-    uint32_t reserved_660;
-    uint32_t reserved_664;
-    uint32_t reserved_668;
-    uint32_t reserved_66c;
-    uint32_t reserved_670;
-    uint32_t reserved_674;
-    uint32_t reserved_678;
-    uint32_t reserved_67c;
-    uint32_t reserved_680;
-    uint32_t reserved_684;
-    uint32_t reserved_688;
-    uint32_t reserved_68c;
-    uint32_t reserved_690;
-    uint32_t reserved_694;
-    uint32_t reserved_698;
-    uint32_t reserved_69c;
-    uint32_t reserved_6a0;
-    uint32_t reserved_6a4;
-    uint32_t reserved_6a8;
-    uint32_t reserved_6ac;
-    uint32_t reserved_6b0;
-    uint32_t reserved_6b4;
-    uint32_t reserved_6b8;
-    uint32_t reserved_6bc;
-    uint32_t reserved_6c0;
-    uint32_t reserved_6c4;
-    uint32_t reserved_6c8;
-    uint32_t reserved_6cc;
-    uint32_t reserved_6d0;
-    uint32_t reserved_6d4;
-    uint32_t reserved_6d8;
-    uint32_t reserved_6dc;
-    uint32_t reserved_6e0;
-    uint32_t reserved_6e4;
-    uint32_t reserved_6e8;
-    uint32_t reserved_6ec;
-    uint32_t reserved_6f0;
-    uint32_t reserved_6f4;
-    uint32_t reserved_6f8;
-    union {
-        struct {
-            uint32_t date:      28;
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } date;
-} gpio_dev_t;
-extern gpio_dev_t GPIO;
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* _SOC_GPIO_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/i2c_reg.h b/components/soc/esp32c3/include/soc/i2c_reg.h
deleted file mode 100644
index 6a45d008276..00000000000
--- a/components/soc/esp32c3/include/soc/i2c_reg.h
+++ /dev/null
@@ -1,1062 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_I2C_REG_H_
-#define _SOC_I2C_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define I2C_SCL_LOW_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0)
-/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
-/*description: .*/
-#define I2C_SCL_LOW_PERIOD    0x000001FF
-#define I2C_SCL_LOW_PERIOD_M  ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
-#define I2C_SCL_LOW_PERIOD_V  0x1FF
-#define I2C_SCL_LOW_PERIOD_S  0
-
-#define I2C_CTR_REG(i)          (REG_I2C_BASE(i) + 0x4)
-/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
-#define I2C_ADDR_BROADCASTING_EN_M  (BIT(14))
-#define I2C_ADDR_BROADCASTING_EN_V  0x1
-#define I2C_ADDR_BROADCASTING_EN_S  14
-/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
-#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (BIT(13))
-#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x1
-#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
-/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
-#define I2C_SLV_TX_AUTO_START_EN_M  (BIT(12))
-#define I2C_SLV_TX_AUTO_START_EN_V  0x1
-#define I2C_SLV_TX_AUTO_START_EN_S  12
-/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_CONF_UPGATE    (BIT(11))
-#define I2C_CONF_UPGATE_M  (BIT(11))
-#define I2C_CONF_UPGATE_V  0x1
-#define I2C_CONF_UPGATE_S  11
-/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_FSM_RST    (BIT(10))
-#define I2C_FSM_RST_M  (BIT(10))
-#define I2C_FSM_RST_V  0x1
-#define I2C_FSM_RST_S  10
-/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_ARBITRATION_EN    (BIT(9))
-#define I2C_ARBITRATION_EN_M  (BIT(9))
-#define I2C_ARBITRATION_EN_V  0x1
-#define I2C_ARBITRATION_EN_S  9
-/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_CLK_EN    (BIT(8))
-#define I2C_CLK_EN_M  (BIT(8))
-#define I2C_CLK_EN_V  0x1
-#define I2C_CLK_EN_S  8
-/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define I2C_RX_LSB_FIRST    (BIT(7))
-#define I2C_RX_LSB_FIRST_M  (BIT(7))
-#define I2C_RX_LSB_FIRST_V  0x1
-#define I2C_RX_LSB_FIRST_S  7
-/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TX_LSB_FIRST    (BIT(6))
-#define I2C_TX_LSB_FIRST_M  (BIT(6))
-#define I2C_TX_LSB_FIRST_V  0x1
-#define I2C_TX_LSB_FIRST_S  6
-/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_START    (BIT(5))
-#define I2C_TRANS_START_M  (BIT(5))
-#define I2C_TRANS_START_V  0x1
-#define I2C_TRANS_START_S  5
-/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_MS_MODE    (BIT(4))
-#define I2C_MS_MODE_M  (BIT(4))
-#define I2C_MS_MODE_V  0x1
-#define I2C_MS_MODE_S  4
-/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
-#define I2C_RX_FULL_ACK_LEVEL_M  (BIT(3))
-#define I2C_RX_FULL_ACK_LEVEL_V  0x1
-#define I2C_RX_FULL_ACK_LEVEL_S  3
-/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_M  (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_V  0x1
-#define I2C_SAMPLE_SCL_LEVEL_S  2
-/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_SCL_FORCE_OUT    (BIT(1))
-#define I2C_SCL_FORCE_OUT_M  (BIT(1))
-#define I2C_SCL_FORCE_OUT_V  0x1
-#define I2C_SCL_FORCE_OUT_S  1
-/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_SDA_FORCE_OUT    (BIT(0))
-#define I2C_SDA_FORCE_OUT_M  (BIT(0))
-#define I2C_SDA_FORCE_OUT_V  0x1
-#define I2C_SDA_FORCE_OUT_S  0
-
-#define I2C_SR_REG(i)          (REG_I2C_BASE(i) + 0x8)
-/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
-/*description: .*/
-#define I2C_SCL_STATE_LAST    0x00000007
-#define I2C_SCL_STATE_LAST_M  ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
-#define I2C_SCL_STATE_LAST_V  0x7
-#define I2C_SCL_STATE_LAST_S  28
-/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
-/*description: .*/
-#define I2C_SCL_MAIN_STATE_LAST    0x00000007
-#define I2C_SCL_MAIN_STATE_LAST_M  ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
-#define I2C_SCL_MAIN_STATE_LAST_V  0x7
-#define I2C_SCL_MAIN_STATE_LAST_S  24
-/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_CNT    0x0000003F
-#define I2C_TXFIFO_CNT_M  ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
-#define I2C_TXFIFO_CNT_V  0x3F
-#define I2C_TXFIFO_CNT_S  18
-/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */
-/*description: .*/
-#define I2C_STRETCH_CAUSE    0x00000003
-#define I2C_STRETCH_CAUSE_M  ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S))
-#define I2C_STRETCH_CAUSE_V  0x3
-#define I2C_STRETCH_CAUSE_S  14
-/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_CNT    0x0000003F
-#define I2C_RXFIFO_CNT_M  ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
-#define I2C_RXFIFO_CNT_V  0x3F
-#define I2C_RXFIFO_CNT_S  8
-/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_ADDRESSED    (BIT(5))
-#define I2C_SLAVE_ADDRESSED_M  (BIT(5))
-#define I2C_SLAVE_ADDRESSED_V  0x1
-#define I2C_SLAVE_ADDRESSED_S  5
-/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_BUS_BUSY    (BIT(4))
-#define I2C_BUS_BUSY_M  (BIT(4))
-#define I2C_BUS_BUSY_V  0x1
-#define I2C_BUS_BUSY_S  4
-/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ARB_LOST    (BIT(3))
-#define I2C_ARB_LOST_M  (BIT(3))
-#define I2C_ARB_LOST_V  0x1
-#define I2C_ARB_LOST_S  3
-/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_RW    (BIT(1))
-#define I2C_SLAVE_RW_M  (BIT(1))
-#define I2C_SLAVE_RW_V  0x1
-#define I2C_SLAVE_RW_S  1
-/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RESP_REC    (BIT(0))
-#define I2C_RESP_REC_M  (BIT(0))
-#define I2C_RESP_REC_V  0x1
-#define I2C_RESP_REC_S  0
-
-#define I2C_TO_REG(i)          (REG_I2C_BASE(i) + 0xC)
-/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TIME_OUT_EN    (BIT(5))
-#define I2C_TIME_OUT_EN_M  (BIT(5))
-#define I2C_TIME_OUT_EN_V  0x1
-#define I2C_TIME_OUT_EN_S  5
-/* I2C_TIME_OUT_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
-/*description: .*/
-#define I2C_TIME_OUT_REG    0x0000001F
-#define I2C_TIME_OUT_REG_M  ((I2C_TIME_OUT_VALUE_V)<<(I2C_TIME_OUT_VALUE_S))
-#define I2C_TIME_OUT_REG_V  0x1F
-#define I2C_TIME_OUT_REG_S  0
-
-#define I2C_SLAVE_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x10)
-/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ADDR_10BIT_EN    (BIT(31))
-#define I2C_ADDR_10BIT_EN_M  (BIT(31))
-#define I2C_ADDR_10BIT_EN_V  0x1
-#define I2C_ADDR_10BIT_EN_S  31
-/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_ADDR    0x00007FFF
-#define I2C_SLAVE_ADDR_M  ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
-#define I2C_SLAVE_ADDR_V  0x7FFF
-#define I2C_SLAVE_ADDR_S  0
-
-#define I2C_FIFO_ST_REG(i)          (REG_I2C_BASE(i) + 0x14)
-/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_RW_POINT    0x000000FF
-#define I2C_SLAVE_RW_POINT_M  ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S))
-#define I2C_SLAVE_RW_POINT_V  0xFF
-#define I2C_SLAVE_RW_POINT_S  22
-/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_WADDR    0x0000001F
-#define I2C_TXFIFO_WADDR_M  ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S))
-#define I2C_TXFIFO_WADDR_V  0x1F
-#define I2C_TXFIFO_WADDR_S  15
-/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_RADDR    0x0000001F
-#define I2C_TXFIFO_RADDR_M  ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S))
-#define I2C_TXFIFO_RADDR_V  0x1F
-#define I2C_TXFIFO_RADDR_S  10
-/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_WADDR    0x0000001F
-#define I2C_RXFIFO_WADDR_M  ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S))
-#define I2C_RXFIFO_WADDR_V  0x1F
-#define I2C_RXFIFO_WADDR_S  5
-/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_RADDR    0x0000001F
-#define I2C_RXFIFO_RADDR_M  ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S))
-#define I2C_RXFIFO_RADDR_V  0x1F
-#define I2C_RXFIFO_RADDR_S  0
-
-#define I2C_FIFO_CONF_REG(i)          (REG_I2C_BASE(i) + 0x18)
-/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_FIFO_PRT_EN    (BIT(14))
-#define I2C_FIFO_PRT_EN_M  (BIT(14))
-#define I2C_FIFO_PRT_EN_V  0x1
-#define I2C_FIFO_PRT_EN_S  14
-/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TX_FIFO_RST    (BIT(13))
-#define I2C_TX_FIFO_RST_M  (BIT(13))
-#define I2C_TX_FIFO_RST_V  0x1
-#define I2C_TX_FIFO_RST_S  13
-/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RX_FIFO_RST    (BIT(12))
-#define I2C_RX_FIFO_RST_M  (BIT(12))
-#define I2C_RX_FIFO_RST_V  0x1
-#define I2C_RX_FIFO_RST_S  12
-/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_M  (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_V  0x1
-#define I2C_FIFO_ADDR_CFG_EN_S  11
-/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_NONFIFO_EN    (BIT(10))
-#define I2C_NONFIFO_EN_M  (BIT(10))
-#define I2C_NONFIFO_EN_V  0x1
-#define I2C_NONFIFO_EN_S  10
-/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
-/*description: .*/
-#define I2C_TXFIFO_WM_THRHD    0x0000001F
-#define I2C_TXFIFO_WM_THRHD_M  ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S))
-#define I2C_TXFIFO_WM_THRHD_V  0x1F
-#define I2C_TXFIFO_WM_THRHD_S  5
-/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
-/*description: .*/
-#define I2C_RXFIFO_WM_THRHD    0x0000001F
-#define I2C_RXFIFO_WM_THRHD_M  ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S))
-#define I2C_RXFIFO_WM_THRHD_V  0x1F
-#define I2C_RXFIFO_WM_THRHD_S  0
-
-#define I2C_DATA_REG(i)          (REG_I2C_BASE(i) + 0x1C)
-/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: .*/
-#define I2C_FIFO_RDATA    0x000000FF
-#define I2C_FIFO_RDATA_M  ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
-#define I2C_FIFO_RDATA_V  0xFF
-#define I2C_FIFO_RDATA_S  0
-
-#define I2C_INT_RAW_REG(i)          (REG_I2C_BASE(i) + 0x20)
-/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
-#define I2C_GENERAL_CALL_INT_RAW_M  (BIT(17))
-#define I2C_GENERAL_CALL_INT_RAW_V  0x1
-#define I2C_GENERAL_CALL_INT_RAW_S  17
-/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_RAW_M  (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_RAW_V  0x1
-#define I2C_SLAVE_STRETCH_INT_RAW_S  16
-/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_DET_START_INT_RAW    (BIT(15))
-#define I2C_DET_START_INT_RAW_M  (BIT(15))
-#define I2C_DET_START_INT_RAW_V  0x1
-#define I2C_DET_START_INT_RAW_S  15
-/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x1
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
-/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
-#define I2C_SCL_ST_TO_INT_RAW_M  (BIT(13))
-#define I2C_SCL_ST_TO_INT_RAW_V  0x1
-#define I2C_SCL_ST_TO_INT_RAW_S  13
-/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_RAW_M  (BIT(12))
-#define I2C_RXFIFO_UDF_INT_RAW_V  0x1
-#define I2C_RXFIFO_UDF_INT_RAW_S  12
-/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_RAW_M  (BIT(11))
-#define I2C_TXFIFO_OVF_INT_RAW_V  0x1
-#define I2C_TXFIFO_OVF_INT_RAW_S  11
-/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_NACK_INT_RAW    (BIT(10))
-#define I2C_NACK_INT_RAW_M  (BIT(10))
-#define I2C_NACK_INT_RAW_V  0x1
-#define I2C_NACK_INT_RAW_S  10
-/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_START_INT_RAW    (BIT(9))
-#define I2C_TRANS_START_INT_RAW_M  (BIT(9))
-#define I2C_TRANS_START_INT_RAW_V  0x1
-#define I2C_TRANS_START_INT_RAW_S  9
-/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TIME_OUT_INT_RAW    (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_M  (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_V  0x1
-#define I2C_TIME_OUT_INT_RAW_S  8
-/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_V  0x1
-#define I2C_TRANS_COMPLETE_INT_RAW_S  7
-/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x1
-#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
-/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_V  0x1
-#define I2C_ARBITRATION_LOST_INT_RAW_S  5
-/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x1
-#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
-/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_END_DETECT_INT_RAW    (BIT(3))
-#define I2C_END_DETECT_INT_RAW_M  (BIT(3))
-#define I2C_END_DETECT_INT_RAW_V  0x1
-#define I2C_END_DETECT_INT_RAW_S  3
-/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_M  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_V  0x1
-#define I2C_RXFIFO_OVF_INT_RAW_S  2
-/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
-#define I2C_TXFIFO_WM_INT_RAW_M  (BIT(1))
-#define I2C_TXFIFO_WM_INT_RAW_V  0x1
-#define I2C_TXFIFO_WM_INT_RAW_S  1
-/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
-#define I2C_RXFIFO_WM_INT_RAW_M  (BIT(0))
-#define I2C_RXFIFO_WM_INT_RAW_V  0x1
-#define I2C_RXFIFO_WM_INT_RAW_S  0
-
-#define I2C_INT_CLR_REG(i)          (REG_I2C_BASE(i) + 0x24)
-/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
-#define I2C_GENERAL_CALL_INT_CLR_M  (BIT(17))
-#define I2C_GENERAL_CALL_INT_CLR_V  0x1
-#define I2C_GENERAL_CALL_INT_CLR_S  17
-/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_CLR_M  (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_CLR_V  0x1
-#define I2C_SLAVE_STRETCH_INT_CLR_S  16
-/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_DET_START_INT_CLR    (BIT(15))
-#define I2C_DET_START_INT_CLR_M  (BIT(15))
-#define I2C_DET_START_INT_CLR_V  0x1
-#define I2C_DET_START_INT_CLR_S  15
-/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x1
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
-/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
-#define I2C_SCL_ST_TO_INT_CLR_M  (BIT(13))
-#define I2C_SCL_ST_TO_INT_CLR_V  0x1
-#define I2C_SCL_ST_TO_INT_CLR_S  13
-/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_CLR_M  (BIT(12))
-#define I2C_RXFIFO_UDF_INT_CLR_V  0x1
-#define I2C_RXFIFO_UDF_INT_CLR_S  12
-/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_CLR_M  (BIT(11))
-#define I2C_TXFIFO_OVF_INT_CLR_V  0x1
-#define I2C_TXFIFO_OVF_INT_CLR_S  11
-/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_NACK_INT_CLR    (BIT(10))
-#define I2C_NACK_INT_CLR_M  (BIT(10))
-#define I2C_NACK_INT_CLR_V  0x1
-#define I2C_NACK_INT_CLR_S  10
-/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_START_INT_CLR    (BIT(9))
-#define I2C_TRANS_START_INT_CLR_M  (BIT(9))
-#define I2C_TRANS_START_INT_CLR_V  0x1
-#define I2C_TRANS_START_INT_CLR_S  9
-/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TIME_OUT_INT_CLR    (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_M  (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_V  0x1
-#define I2C_TIME_OUT_INT_CLR_S  8
-/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_V  0x1
-#define I2C_TRANS_COMPLETE_INT_CLR_S  7
-/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x1
-#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
-/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_V  0x1
-#define I2C_ARBITRATION_LOST_INT_CLR_S  5
-/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x1
-#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
-/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_END_DETECT_INT_CLR    (BIT(3))
-#define I2C_END_DETECT_INT_CLR_M  (BIT(3))
-#define I2C_END_DETECT_INT_CLR_V  0x1
-#define I2C_END_DETECT_INT_CLR_S  3
-/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_M  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_V  0x1
-#define I2C_RXFIFO_OVF_INT_CLR_S  2
-/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
-#define I2C_TXFIFO_WM_INT_CLR_M  (BIT(1))
-#define I2C_TXFIFO_WM_INT_CLR_V  0x1
-#define I2C_TXFIFO_WM_INT_CLR_S  1
-/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
-#define I2C_RXFIFO_WM_INT_CLR_M  (BIT(0))
-#define I2C_RXFIFO_WM_INT_CLR_V  0x1
-#define I2C_RXFIFO_WM_INT_CLR_S  0
-
-#define I2C_INT_ENA_REG(i)          (REG_I2C_BASE(i) + 0x28)
-/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
-#define I2C_GENERAL_CALL_INT_ENA_M  (BIT(17))
-#define I2C_GENERAL_CALL_INT_ENA_V  0x1
-#define I2C_GENERAL_CALL_INT_ENA_S  17
-/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ENA_M  (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ENA_V  0x1
-#define I2C_SLAVE_STRETCH_INT_ENA_S  16
-/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_DET_START_INT_ENA    (BIT(15))
-#define I2C_DET_START_INT_ENA_M  (BIT(15))
-#define I2C_DET_START_INT_ENA_V  0x1
-#define I2C_DET_START_INT_ENA_S  15
-/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x1
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
-/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
-#define I2C_SCL_ST_TO_INT_ENA_M  (BIT(13))
-#define I2C_SCL_ST_TO_INT_ENA_V  0x1
-#define I2C_SCL_ST_TO_INT_ENA_S  13
-/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ENA_M  (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ENA_V  0x1
-#define I2C_RXFIFO_UDF_INT_ENA_S  12
-/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ENA_M  (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ENA_V  0x1
-#define I2C_TXFIFO_OVF_INT_ENA_S  11
-/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_NACK_INT_ENA    (BIT(10))
-#define I2C_NACK_INT_ENA_M  (BIT(10))
-#define I2C_NACK_INT_ENA_V  0x1
-#define I2C_NACK_INT_ENA_S  10
-/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_START_INT_ENA    (BIT(9))
-#define I2C_TRANS_START_INT_ENA_M  (BIT(9))
-#define I2C_TRANS_START_INT_ENA_V  0x1
-#define I2C_TRANS_START_INT_ENA_S  9
-/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TIME_OUT_INT_ENA    (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_M  (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_V  0x1
-#define I2C_TIME_OUT_INT_ENA_S  8
-/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_V  0x1
-#define I2C_TRANS_COMPLETE_INT_ENA_S  7
-/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x1
-#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
-/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_V  0x1
-#define I2C_ARBITRATION_LOST_INT_ENA_S  5
-/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x1
-#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
-/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_END_DETECT_INT_ENA    (BIT(3))
-#define I2C_END_DETECT_INT_ENA_M  (BIT(3))
-#define I2C_END_DETECT_INT_ENA_V  0x1
-#define I2C_END_DETECT_INT_ENA_S  3
-/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_M  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_V  0x1
-#define I2C_RXFIFO_OVF_INT_ENA_S  2
-/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
-#define I2C_TXFIFO_WM_INT_ENA_M  (BIT(1))
-#define I2C_TXFIFO_WM_INT_ENA_V  0x1
-#define I2C_TXFIFO_WM_INT_ENA_S  1
-/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
-#define I2C_RXFIFO_WM_INT_ENA_M  (BIT(0))
-#define I2C_RXFIFO_WM_INT_ENA_V  0x1
-#define I2C_RXFIFO_WM_INT_ENA_S  0
-
-#define I2C_INT_STATUS_REG(i)          (REG_I2C_BASE(i) + 0x2C)
-/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
-#define I2C_GENERAL_CALL_INT_ST_M  (BIT(17))
-#define I2C_GENERAL_CALL_INT_ST_V  0x1
-#define I2C_GENERAL_CALL_INT_ST_S  17
-/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ST_M  (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ST_V  0x1
-#define I2C_SLAVE_STRETCH_INT_ST_S  16
-/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_DET_START_INT_ST    (BIT(15))
-#define I2C_DET_START_INT_ST_M  (BIT(15))
-#define I2C_DET_START_INT_ST_V  0x1
-#define I2C_DET_START_INT_ST_S  15
-/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x1
-#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
-/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
-#define I2C_SCL_ST_TO_INT_ST_M  (BIT(13))
-#define I2C_SCL_ST_TO_INT_ST_V  0x1
-#define I2C_SCL_ST_TO_INT_ST_S  13
-/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ST_M  (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ST_V  0x1
-#define I2C_RXFIFO_UDF_INT_ST_S  12
-/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ST_M  (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ST_V  0x1
-#define I2C_TXFIFO_OVF_INT_ST_S  11
-/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_NACK_INT_ST    (BIT(10))
-#define I2C_NACK_INT_ST_M  (BIT(10))
-#define I2C_NACK_INT_ST_V  0x1
-#define I2C_NACK_INT_ST_S  10
-/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_START_INT_ST    (BIT(9))
-#define I2C_TRANS_START_INT_ST_M  (BIT(9))
-#define I2C_TRANS_START_INT_ST_V  0x1
-#define I2C_TRANS_START_INT_ST_S  9
-/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TIME_OUT_INT_ST    (BIT(8))
-#define I2C_TIME_OUT_INT_ST_M  (BIT(8))
-#define I2C_TIME_OUT_INT_ST_V  0x1
-#define I2C_TIME_OUT_INT_ST_S  8
-/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_M  (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_V  0x1
-#define I2C_TRANS_COMPLETE_INT_ST_S  7
-/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ST_M  (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x1
-#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
-/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_M  (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_V  0x1
-#define I2C_ARBITRATION_LOST_INT_ST_S  5
-/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ST_M  (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x1
-#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
-/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_END_DETECT_INT_ST    (BIT(3))
-#define I2C_END_DETECT_INT_ST_M  (BIT(3))
-#define I2C_END_DETECT_INT_ST_V  0x1
-#define I2C_END_DETECT_INT_ST_S  3
-/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_M  (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_V  0x1
-#define I2C_RXFIFO_OVF_INT_ST_S  2
-/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
-#define I2C_TXFIFO_WM_INT_ST_M  (BIT(1))
-#define I2C_TXFIFO_WM_INT_ST_V  0x1
-#define I2C_TXFIFO_WM_INT_ST_S  1
-/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
-#define I2C_RXFIFO_WM_INT_ST_M  (BIT(0))
-#define I2C_RXFIFO_WM_INT_ST_V  0x1
-#define I2C_RXFIFO_WM_INT_ST_S  0
-
-#define I2C_SDA_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x30)
-/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
-/*description: .*/
-#define I2C_SDA_HOLD_TIME    0x000001FF
-#define I2C_SDA_HOLD_TIME_M  ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
-#define I2C_SDA_HOLD_TIME_V  0x1FF
-#define I2C_SDA_HOLD_TIME_S  0
-
-#define I2C_SDA_SAMPLE_REG(i)          (REG_I2C_BASE(i) + 0x34)
-/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
-/*description: .*/
-#define I2C_SDA_SAMPLE_TIME    0x000001FF
-#define I2C_SDA_SAMPLE_TIME_M  ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
-#define I2C_SDA_SAMPLE_TIME_V  0x1FF
-#define I2C_SDA_SAMPLE_TIME_S  0
-
-#define I2C_SCL_HIGH_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x38)
-/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */
-/*description: .*/
-#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007F
-#define I2C_SCL_WAIT_HIGH_PERIOD_M  ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S))
-#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x7F
-#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
-/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
-/*description: .*/
-#define I2C_SCL_HIGH_PERIOD    0x000001FF
-#define I2C_SCL_HIGH_PERIOD_M  ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
-#define I2C_SCL_HIGH_PERIOD_V  0x1FF
-#define I2C_SCL_HIGH_PERIOD_S  0
-
-#define I2C_SCL_START_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x40)
-/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
-/*description: .*/
-#define I2C_SCL_START_HOLD_TIME    0x000001FF
-#define I2C_SCL_START_HOLD_TIME_M  ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
-#define I2C_SCL_START_HOLD_TIME_V  0x1FF
-#define I2C_SCL_START_HOLD_TIME_S  0
-
-#define I2C_SCL_RSTART_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x44)
-/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
-/*description: .*/
-#define I2C_SCL_RSTART_SETUP_TIME    0x000001FF
-#define I2C_SCL_RSTART_SETUP_TIME_M  ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
-#define I2C_SCL_RSTART_SETUP_TIME_V  0x1FF
-#define I2C_SCL_RSTART_SETUP_TIME_S  0
-
-#define I2C_SCL_STOP_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x48)
-/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
-/*description: .*/
-#define I2C_SCL_STOP_HOLD_TIME    0x000001FF
-#define I2C_SCL_STOP_HOLD_TIME_M  ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
-#define I2C_SCL_STOP_HOLD_TIME_V  0x1FF
-#define I2C_SCL_STOP_HOLD_TIME_S  0
-
-#define I2C_SCL_STOP_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x4C)
-/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
-/*description: .*/
-#define I2C_SCL_STOP_SETUP_TIME    0x000001FF
-#define I2C_SCL_STOP_SETUP_TIME_M  ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
-#define I2C_SCL_STOP_SETUP_TIME_V  0x1FF
-#define I2C_SCL_STOP_SETUP_TIME_S  0
-
-#define I2C_FILTER_CFG_REG(i)          (REG_I2C_BASE(i) + 0x50)
-/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_SDA_FILTER_EN    (BIT(9))
-#define I2C_SDA_FILTER_EN_M  (BIT(9))
-#define I2C_SDA_FILTER_EN_V  0x1
-#define I2C_SDA_FILTER_EN_S  9
-/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_SCL_FILTER_EN    (BIT(8))
-#define I2C_SCL_FILTER_EN_M  (BIT(8))
-#define I2C_SCL_FILTER_EN_V  0x1
-#define I2C_SCL_FILTER_EN_S  8
-/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: .*/
-#define I2C_SDA_FILTER_THRES    0x0000000F
-#define I2C_SDA_FILTER_THRES_M  ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
-#define I2C_SDA_FILTER_THRES_V  0xF
-#define I2C_SDA_FILTER_THRES_S  4
-/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: .*/
-#define I2C_SCL_FILTER_THRES    0x0000000F
-#define I2C_SCL_FILTER_THRES_M  ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
-#define I2C_SCL_FILTER_THRES_V  0xF
-#define I2C_SCL_FILTER_THRES_S  0
-
-#define I2C_CLK_CONF_REG(i)          (REG_I2C_BASE(i) + 0x54)
-/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: .*/
-#define I2C_SCLK_ACTIVE    (BIT(21))
-#define I2C_SCLK_ACTIVE_M  (BIT(21))
-#define I2C_SCLK_ACTIVE_V  0x1
-#define I2C_SCLK_ACTIVE_S  21
-/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCLK_SEL    (BIT(20))
-#define I2C_SCLK_SEL_M  (BIT(20))
-#define I2C_SCLK_SEL_V  0x1
-#define I2C_SCLK_SEL_S  20
-/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */
-/*description: .*/
-#define I2C_SCLK_DIV_B    0x0000003F
-#define I2C_SCLK_DIV_B_M  ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S))
-#define I2C_SCLK_DIV_B_V  0x3F
-#define I2C_SCLK_DIV_B_S  14
-/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */
-/*description: .*/
-#define I2C_SCLK_DIV_A    0x0000003F
-#define I2C_SCLK_DIV_A_M  ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S))
-#define I2C_SCLK_DIV_A_V  0x3F
-#define I2C_SCLK_DIV_A_S  8
-/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: .*/
-#define I2C_SCLK_DIV_NUM    0x000000FF
-#define I2C_SCLK_DIV_NUM_M  ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S))
-#define I2C_SCLK_DIV_NUM_V  0xFF
-#define I2C_SCLK_DIV_NUM_S  0
-
-#define I2C_COMD0_REG(i)          (REG_I2C_BASE(i) + 0x58)
-/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_COMMAND0_DONE    (BIT(31))
-#define I2C_COMMAND0_DONE_M  (BIT(31))
-#define I2C_COMMAND0_DONE_V  0x1
-#define I2C_COMMAND0_DONE_S  31
-/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define I2C_COMMAND0    0x00003FFF
-#define I2C_COMMAND0_M  ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
-#define I2C_COMMAND0_V  0x3FFF
-#define I2C_COMMAND0_S  0
-
-#define I2C_COMD1_REG(i)          (REG_I2C_BASE(i) + 0x5C)
-/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_COMMAND1_DONE    (BIT(31))
-#define I2C_COMMAND1_DONE_M  (BIT(31))
-#define I2C_COMMAND1_DONE_V  0x1
-#define I2C_COMMAND1_DONE_S  31
-/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define I2C_COMMAND1    0x00003FFF
-#define I2C_COMMAND1_M  ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
-#define I2C_COMMAND1_V  0x3FFF
-#define I2C_COMMAND1_S  0
-
-#define I2C_COMD2_REG(i)          (REG_I2C_BASE(i) + 0x60)
-/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_COMMAND2_DONE    (BIT(31))
-#define I2C_COMMAND2_DONE_M  (BIT(31))
-#define I2C_COMMAND2_DONE_V  0x1
-#define I2C_COMMAND2_DONE_S  31
-/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define I2C_COMMAND2    0x00003FFF
-#define I2C_COMMAND2_M  ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
-#define I2C_COMMAND2_V  0x3FFF
-#define I2C_COMMAND2_S  0
-
-#define I2C_COMD3_REG(i)          (REG_I2C_BASE(i) + 0x64)
-/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_COMMAND3_DONE    (BIT(31))
-#define I2C_COMMAND3_DONE_M  (BIT(31))
-#define I2C_COMMAND3_DONE_V  0x1
-#define I2C_COMMAND3_DONE_S  31
-/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define I2C_COMMAND3    0x00003FFF
-#define I2C_COMMAND3_M  ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
-#define I2C_COMMAND3_V  0x3FFF
-#define I2C_COMMAND3_S  0
-
-#define I2C_COMD4_REG(i)          (REG_I2C_BASE(i) + 0x68)
-/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_COMMAND4_DONE    (BIT(31))
-#define I2C_COMMAND4_DONE_M  (BIT(31))
-#define I2C_COMMAND4_DONE_V  0x1
-#define I2C_COMMAND4_DONE_S  31
-/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define I2C_COMMAND4    0x00003FFF
-#define I2C_COMMAND4_M  ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
-#define I2C_COMMAND4_V  0x3FFF
-#define I2C_COMMAND4_S  0
-
-#define I2C_COMD5_REG(i)          (REG_I2C_BASE(i) + 0x6C)
-/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_COMMAND5_DONE    (BIT(31))
-#define I2C_COMMAND5_DONE_M  (BIT(31))
-#define I2C_COMMAND5_DONE_V  0x1
-#define I2C_COMMAND5_DONE_S  31
-/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define I2C_COMMAND5    0x00003FFF
-#define I2C_COMMAND5_M  ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
-#define I2C_COMMAND5_V  0x3FFF
-#define I2C_COMMAND5_S  0
-
-#define I2C_COMD6_REG(i)          (REG_I2C_BASE(i) + 0x70)
-/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_COMMAND6_DONE    (BIT(31))
-#define I2C_COMMAND6_DONE_M  (BIT(31))
-#define I2C_COMMAND6_DONE_V  0x1
-#define I2C_COMMAND6_DONE_S  31
-/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define I2C_COMMAND6    0x00003FFF
-#define I2C_COMMAND6_M  ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
-#define I2C_COMMAND6_V  0x3FFF
-#define I2C_COMMAND6_S  0
-
-#define I2C_COMD7_REG(i)          (REG_I2C_BASE(i) + 0x74)
-/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_COMMAND7_DONE    (BIT(31))
-#define I2C_COMMAND7_DONE_M  (BIT(31))
-#define I2C_COMMAND7_DONE_V  0x1
-#define I2C_COMMAND7_DONE_S  31
-/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define I2C_COMMAND7    0x00003FFF
-#define I2C_COMMAND7_M  ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
-#define I2C_COMMAND7_V  0x3FFF
-#define I2C_COMMAND7_S  0
-
-#define I2C_SCL_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x78)
-/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
-/*description: no more than 23.*/
-#define I2C_SCL_ST_TO_REG    0x0000001F
-#define I2C_SCL_ST_TO_REG_M  ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S))
-#define I2C_SCL_ST_TO_REG_V  0x1F
-#define I2C_SCL_ST_TO_REG_S  0
-
-#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x7C)
-/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
-/*description: no more than 23.*/
-#define I2C_SCL_MAIN_ST_TO_REG    0x0000001F
-#define I2C_SCL_MAIN_ST_TO_REG_M  ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S))
-#define I2C_SCL_MAIN_ST_TO_REG_V  0x1F
-#define I2C_SCL_MAIN_ST_TO_REG_S  0
-
-#define I2C_SCL_SP_CONF_REG(i)          (REG_I2C_BASE(i) + 0x80)
-/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SDA_PD_EN    (BIT(7))
-#define I2C_SDA_PD_EN_M  (BIT(7))
-#define I2C_SDA_PD_EN_V  0x1
-#define I2C_SDA_PD_EN_S  7
-/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_PD_EN    (BIT(6))
-#define I2C_SCL_PD_EN_M  (BIT(6))
-#define I2C_SCL_PD_EN_V  0x1
-#define I2C_SCL_PD_EN_S  6
-/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */
-/*description: .*/
-#define I2C_SCL_RST_SLV_NUM    0x0000001F
-#define I2C_SCL_RST_SLV_NUM_M  ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S))
-#define I2C_SCL_RST_SLV_NUM_V  0x1F
-#define I2C_SCL_RST_SLV_NUM_S  1
-/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SCL_RST_SLV_EN    (BIT(0))
-#define I2C_SCL_RST_SLV_EN_M  (BIT(0))
-#define I2C_SCL_RST_SLV_EN_V  0x1
-#define I2C_SCL_RST_SLV_EN_S  0
-
-#define I2C_SCL_STRETCH_CONF_REG(i)          (REG_I2C_BASE(i) + 0x84)
-/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
-#define I2C_SLAVE_BYTE_ACK_LVL_M  (BIT(13))
-#define I2C_SLAVE_BYTE_ACK_LVL_V  0x1
-#define I2C_SLAVE_BYTE_ACK_LVL_S  13
-/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (BIT(12))
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x1
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
-/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
-#define I2C_SLAVE_SCL_STRETCH_CLR_M  (BIT(11))
-#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x1
-#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
-/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
-#define I2C_SLAVE_SCL_STRETCH_EN_M  (BIT(10))
-#define I2C_SLAVE_SCL_STRETCH_EN_V  0x1
-#define I2C_SLAVE_SCL_STRETCH_EN_S  10
-/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: .*/
-#define I2C_STRETCH_PROTECT_NUM    0x000003FF
-#define I2C_STRETCH_PROTECT_NUM_M  ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S))
-#define I2C_STRETCH_PROTECT_NUM_V  0x3FF
-#define I2C_STRETCH_PROTECT_NUM_S  0
-
-#define I2C_DATE_REG(i)          (REG_I2C_BASE(i) + 0xF8)
-/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */
-/*description: .*/
-#define I2C_DATE    0xFFFFFFFF
-#define I2C_DATE_M  ((I2C_DATE_V)<<(I2C_DATE_S))
-#define I2C_DATE_V  0xFFFFFFFF
-#define I2C_DATE_S  0
-
-#define I2C_TXFIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x100)
-
-#define I2C_RXFIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x180)
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_I2C_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/i2c_struct.h b/components/soc/esp32c3/include/soc/i2c_struct.h
deleted file mode 100644
index 1009fedd6e0..00000000000
--- a/components/soc/esp32c3/include/soc/i2c_struct.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_I2C_STRUCT_H_
-#define _SOC_I2C_STRUCT_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-typedef volatile struct i2c_dev_s {
-    union {
-        struct {
-            uint32_t period                        :    9;
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } scl_low_period;
-    union {
-        struct {
-            uint32_t sda_force_out                 :    1;
-            uint32_t scl_force_out                 :    1;
-            uint32_t sample_scl_level              :    1;
-            uint32_t rx_full_ack_level             :    1;
-            uint32_t ms_mode                       :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t tx_lsb_first                  :    1;
-            uint32_t rx_lsb_first                  :    1;
-            uint32_t clk_en                        :    1;
-            uint32_t arbitration_en                :    1;
-            uint32_t fsm_rst                       :    1;
-            uint32_t conf_upgate                   :    1;
-            uint32_t slv_tx_auto_start_en          :    1;
-            uint32_t addr_10bit_rw_check_en        :    1;
-            uint32_t addr_broadcasting_en          :    1;
-            uint32_t reserved15                    :    17;
-        };
-        uint32_t val;
-    } ctr;
-    union {
-        struct {
-            uint32_t resp_rec                      :    1;
-            uint32_t slave_rw                      :    1;
-            uint32_t reserved2                     :    1;
-            uint32_t arb_lost                      :    1;
-            uint32_t bus_busy                      :    1;
-            uint32_t slave_addressed               :    1;
-            uint32_t reserved6                     :    1;
-            uint32_t reserved7                     :    1;
-            uint32_t rx_fifo_cnt                   :    6;
-            uint32_t stretch_cause                 :    2;
-            uint32_t reserved16                    :    2;
-            uint32_t tx_fifo_cnt                   :    6;
-            uint32_t scl_main_state_last           :    3;
-            uint32_t reserved27                    :    1;
-            uint32_t scl_state_last                :    3;
-            uint32_t reserved31                    :    1;
-        };
-        uint32_t val;
-    } sr;
-    union {
-        struct {
-            uint32_t time_out_value                :    5;
-            uint32_t time_out_en                   :    1;
-            uint32_t reserved6                     :    26;
-        };
-        uint32_t val;
-    } timeout;
-    union {
-        struct {
-            uint32_t addr                          :    15;
-            uint32_t reserved15                    :    16;
-            uint32_t en_10bit                      :    1;
-        };
-        uint32_t val;
-    } slave_addr;
-    union {
-        struct {
-            uint32_t rx_fifo_raddr                 :    5;
-            uint32_t rx_fifo_waddr                 :    5;
-            uint32_t tx_fifo_raddr                 :    5;
-            uint32_t tx_fifo_waddr                 :    5;
-            uint32_t reserved20                    :    1;
-            uint32_t reserved21                    :    1;
-            uint32_t slave_rw_point                :    8;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } fifo_st;
-    union {
-        struct {
-            uint32_t rx_fifo_wm_thrhd              :    5;
-            uint32_t tx_fifo_wm_thrhd              :    5;
-            uint32_t nonfifo_en                    :    1;
-            uint32_t fifo_addr_cfg_en              :    1;
-            uint32_t rx_fifo_rst                   :    1;
-            uint32_t tx_fifo_rst                   :    1;
-            uint32_t fifo_prt_en                   :    1;
-            uint32_t reserved15                    :    5;
-            uint32_t reserved20                    :    6;
-            uint32_t reserved26                    :    1;
-            uint32_t reserved27                    :    5;
-        };
-        uint32_t val;
-    } fifo_conf;
-    union {
-        struct {
-            uint32_t data                          :    8;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } fifo_data;
-    union {
-        struct {
-            uint32_t rx_fifo_wm                    :    1;
-            uint32_t tx_fifo_wm                    :    1;
-            uint32_t rx_fifo_ovf                   :    1;
-            uint32_t end_detect                    :    1;
-            uint32_t byte_trans_done               :    1;
-            uint32_t arbitration_lost              :    1;
-            uint32_t mst_tx_fifo_udf               :    1;
-            uint32_t trans_complete                :    1;
-            uint32_t time_out                      :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t nack                          :    1;
-            uint32_t tx_fifo_ovf                   :    1;
-            uint32_t rx_fifo_udf                   :    1;
-            uint32_t scl_st_to                     :    1;
-            uint32_t scl_main_st_to                :    1;
-            uint32_t det_start                     :    1;
-            uint32_t slave_stretch                 :    1;
-            uint32_t general_call                  :    1;
-            uint32_t reserved18                    :    14;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rx_fifo_wm                    :    1;
-            uint32_t tx_fifo_wm                    :    1;
-            uint32_t rx_fifo_ovf                   :    1;
-            uint32_t end_detect                    :    1;
-            uint32_t byte_trans_done               :    1;
-            uint32_t arbitration_lost              :    1;
-            uint32_t mst_tx_fifo_udf               :    1;
-            uint32_t trans_complete                :    1;
-            uint32_t time_out                      :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t nack                          :    1;
-            uint32_t tx_fifo_ovf                   :    1;
-            uint32_t rx_fifo_udf                   :    1;
-            uint32_t scl_st_to                     :    1;
-            uint32_t scl_main_st_to                :    1;
-            uint32_t det_start                     :    1;
-            uint32_t slave_stretch                 :    1;
-            uint32_t general_call                  :    1;
-            uint32_t reserved18                    :    14;
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t rx_fifo_wm                    :    1;
-            uint32_t tx_fifo_wm                    :    1;
-            uint32_t rx_fifo_ovf                   :    1;
-            uint32_t end_detect                    :    1;
-            uint32_t byte_trans_done               :    1;
-            uint32_t arbitration_lost              :    1;
-            uint32_t mst_tx_fifo_udf               :    1;
-            uint32_t trans_complete                :    1;
-            uint32_t time_out                      :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t nack                          :    1;
-            uint32_t tx_fifo_ovf                   :    1;
-            uint32_t rx_fifo_udf                   :    1;
-            uint32_t scl_st_to                     :    1;
-            uint32_t scl_main_st_to                :    1;
-            uint32_t det_start                     :    1;
-            uint32_t slave_stretch                 :    1;
-            uint32_t general_call                  :    1;
-            uint32_t reserved18                    :    14;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rx_fifo_wm                    :    1;
-            uint32_t tx_fifo_wm                    :    1;
-            uint32_t rx_fifo_ovf                   :    1;
-            uint32_t end_detect                    :    1;
-            uint32_t byte_trans_done               :    1;
-            uint32_t arbitration_lost              :    1;
-            uint32_t mst_tx_fifo_udf               :    1;
-            uint32_t trans_complete                :    1;
-            uint32_t time_out                      :    1;
-            uint32_t trans_start                   :    1;
-            uint32_t nack                          :    1;
-            uint32_t tx_fifo_ovf                   :    1;
-            uint32_t rx_fifo_udf                   :    1;
-            uint32_t scl_st_to                     :    1;
-            uint32_t scl_main_st_to                :    1;
-            uint32_t det_start                     :    1;
-            uint32_t slave_stretch                 :    1;
-            uint32_t general_call                  :    1;
-            uint32_t reserved18                    :    14;
-        };
-        uint32_t val;
-    } int_status;
-    union {
-        struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } sda_hold;
-    union {
-        struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } sda_sample;
-    union {
-        struct {
-            uint32_t period                        :    9;
-            uint32_t scl_wait_high_period          :    7;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } scl_high_period;
-    uint32_t reserved_3c;
-    union {
-        struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } scl_start_hold;
-    union {
-        struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } scl_rstart_setup;
-    union {
-        struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } scl_stop_hold;
-    union {
-        struct {
-            uint32_t time                          :    9;
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } scl_stop_setup;
-    union {
-        struct {
-            uint32_t scl_thres                     :    4;
-            uint32_t sda_thres                     :    4;
-            uint32_t scl_en                        :    1;
-            uint32_t sda_en                        :    1;
-            uint32_t reserved10                    :    22;
-        };
-        uint32_t val;
-    } filter_cfg;
-    union {
-        struct {
-            uint32_t sclk_div_num                  :    8;
-            uint32_t sclk_div_a                    :    6;
-            uint32_t sclk_div_b                    :    6;
-            uint32_t sclk_sel                      :    1;
-            uint32_t sclk_active                   :    1;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } clk_conf;
-    union {
-        struct {
-            uint32_t command0                      :    14;
-            uint32_t reserved14                    :    17;
-            uint32_t command0_done                 :    1;
-        };
-        uint32_t val;
-    } command[8];
-    union {
-        struct {
-            uint32_t scl_st_to                     :    5;  /*no more than 23*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } scl_st_time_out;
-    union {
-        struct {
-            uint32_t scl_main_st_to                :    5;  /*no more than 23*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } scl_main_st_time_out;
-    union {
-        struct {
-            uint32_t scl_rst_slv_en                :    1;
-            uint32_t scl_rst_slv_num               :    5;
-            uint32_t scl_pd_en                     :    1;
-            uint32_t sda_pd_en                     :    1;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } scl_sp_conf;
-    union {
-        struct {
-            uint32_t stretch_protect_num           :    10;
-            uint32_t slave_scl_stretch_en          :    1;
-            uint32_t slave_scl_stretch_clr         :    1;
-            uint32_t slave_byte_ack_ctl_en         :    1;
-            uint32_t slave_byte_ack_level          :    1;
-            uint32_t reserved14                    :    18;
-        };
-        uint32_t val;
-    } scl_stretch_conf;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t reserved_98;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t date;
-    uint32_t reserved_fc;
-    uint32_t txfifo_mem[32];
-    uint32_t rxfifo_mem[32];
-} i2c_dev_t;
-extern i2c_dev_t I2C0;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_I2C_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/i2s_reg.h b/components/soc/esp32c3/include/soc/i2s_reg.h
deleted file mode 100644
index 2b3ed91f610..00000000000
--- a/components/soc/esp32c3/include/soc/i2s_reg.h
+++ /dev/null
@@ -1,1043 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_I2S_REG_H_
-#define _SOC_I2S_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0x000c)
-/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
-#define I2S_TX_HUNG_INT_RAW  (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_M  (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_V  0x1
-#define I2S_TX_HUNG_INT_RAW_S  3
-/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
-#define I2S_RX_HUNG_INT_RAW  (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_M  (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_V  0x1
-#define I2S_RX_HUNG_INT_RAW_S  2
-/* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_tx_done_int interrupt*/
-#define I2S_TX_DONE_INT_RAW  (BIT(1))
-#define I2S_TX_DONE_INT_RAW_M  (BIT(1))
-#define I2S_TX_DONE_INT_RAW_V  0x1
-#define I2S_TX_DONE_INT_RAW_S  1
-/* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_rx_done_int interrupt*/
-#define I2S_RX_DONE_INT_RAW  (BIT(0))
-#define I2S_RX_DONE_INT_RAW_M  (BIT(0))
-#define I2S_RX_DONE_INT_RAW_V  0x1
-#define I2S_RX_DONE_INT_RAW_S  0
-
-#define I2S_INT_ST_REG(i)          (REG_I2S_BASE(i) + 0x0010)
-/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
-#define I2S_TX_HUNG_INT_ST  (BIT(3))
-#define I2S_TX_HUNG_INT_ST_M  (BIT(3))
-#define I2S_TX_HUNG_INT_ST_V  0x1
-#define I2S_TX_HUNG_INT_ST_S  3
-/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
-#define I2S_RX_HUNG_INT_ST  (BIT(2))
-#define I2S_RX_HUNG_INT_ST_M  (BIT(2))
-#define I2S_RX_HUNG_INT_ST_V  0x1
-#define I2S_RX_HUNG_INT_ST_S  2
-/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_tx_done_int interrupt*/
-#define I2S_TX_DONE_INT_ST  (BIT(1))
-#define I2S_TX_DONE_INT_ST_M  (BIT(1))
-#define I2S_TX_DONE_INT_ST_V  0x1
-#define I2S_TX_DONE_INT_ST_S  1
-/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_rx_done_int interrupt*/
-#define I2S_RX_DONE_INT_ST  (BIT(0))
-#define I2S_RX_DONE_INT_ST_M  (BIT(0))
-#define I2S_RX_DONE_INT_ST_V  0x1
-#define I2S_RX_DONE_INT_ST_S  0
-
-#define I2S_INT_ENA_REG(i)          (REG_I2S_BASE(i) + 0x0014)
-/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
-#define I2S_TX_HUNG_INT_ENA  (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_M  (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_V  0x1
-#define I2S_TX_HUNG_INT_ENA_S  3
-/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
-#define I2S_RX_HUNG_INT_ENA  (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_M  (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_V  0x1
-#define I2S_RX_HUNG_INT_ENA_S  2
-/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_tx_done_int interrupt*/
-#define I2S_TX_DONE_INT_ENA  (BIT(1))
-#define I2S_TX_DONE_INT_ENA_M  (BIT(1))
-#define I2S_TX_DONE_INT_ENA_V  0x1
-#define I2S_TX_DONE_INT_ENA_S  1
-/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_rx_done_int interrupt*/
-#define I2S_RX_DONE_INT_ENA  (BIT(0))
-#define I2S_RX_DONE_INT_ENA_M  (BIT(0))
-#define I2S_RX_DONE_INT_ENA_V  0x1
-#define I2S_RX_DONE_INT_ENA_S  0
-
-#define I2S_INT_CLR_REG(i)          (REG_I2S_BASE(i) + 0x0018)
-/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/
-#define I2S_TX_HUNG_INT_CLR  (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_M  (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_V  0x1
-#define I2S_TX_HUNG_INT_CLR_S  3
-/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/
-#define I2S_RX_HUNG_INT_CLR  (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_M  (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_V  0x1
-#define I2S_RX_HUNG_INT_CLR_S  2
-/* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_tx_done_int interrupt*/
-#define I2S_TX_DONE_INT_CLR  (BIT(1))
-#define I2S_TX_DONE_INT_CLR_M  (BIT(1))
-#define I2S_TX_DONE_INT_CLR_V  0x1
-#define I2S_TX_DONE_INT_CLR_S  1
-/* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_rx_done_int interrupt*/
-#define I2S_RX_DONE_INT_CLR  (BIT(0))
-#define I2S_RX_DONE_INT_CLR_M  (BIT(0))
-#define I2S_RX_DONE_INT_CLR_V  0x1
-#define I2S_RX_DONE_INT_CLR_S  0
-
-#define I2S_RX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0020)
-/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/
-#define I2S_RX_PDM_EN  (BIT(20))
-#define I2S_RX_PDM_EN_M  (BIT(20))
-#define I2S_RX_PDM_EN_V  0x1
-#define I2S_RX_PDM_EN_S  20
-/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/
-#define I2S_RX_TDM_EN  (BIT(19))
-#define I2S_RX_TDM_EN_M  (BIT(19))
-#define I2S_RX_TDM_EN_V  0x1
-#define I2S_RX_TDM_EN_S  19
-/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: I2S Rx bit endian. 1:small endian  the LSB is received first.
- 0:big endian  the MSB is received first.*/
-#define I2S_RX_BIT_ORDER  (BIT(18))
-#define I2S_RX_BIT_ORDER_M  (BIT(18))
-#define I2S_RX_BIT_ORDER_V  0x1
-#define I2S_RX_BIT_ORDER_S  18
-/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: 0: WS should be 0 when receiving left channel data  and WS is
- 1in right channel.  1: WS should be 1 when receiving left channel data  and WS is 0in right channel.*/
-#define I2S_RX_WS_IDLE_POL  (BIT(17))
-#define I2S_RX_WS_IDLE_POL_M  (BIT(17))
-#define I2S_RX_WS_IDLE_POL_V  0x1
-#define I2S_RX_WS_IDLE_POL_S  17
-/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
-#define I2S_RX_24_FILL_EN  (BIT(16))
-#define I2S_RX_24_FILL_EN_M  (BIT(16))
-#define I2S_RX_24_FILL_EN_V  0x1
-#define I2S_RX_24_FILL_EN_S  16
-/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
-#define I2S_RX_LEFT_ALIGN  (BIT(15))
-#define I2S_RX_LEFT_ALIGN_M  (BIT(15))
-#define I2S_RX_LEFT_ALIGN_V  0x1
-#define I2S_RX_LEFT_ALIGN_S  15
-/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */
-/*description: 0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop
- when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
-#define I2S_RX_STOP_MODE  0x00000003
-#define I2S_RX_STOP_MODE_M  ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S))
-#define I2S_RX_STOP_MODE_V  0x3
-#define I2S_RX_STOP_MODE_S  13
-/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to bypass Compress/Decompress module for received data.*/
-#define I2S_RX_PCM_BYPASS  (BIT(12))
-#define I2S_RX_PCM_BYPASS_M  (BIT(12))
-#define I2S_RX_PCM_BYPASS_V  0x1
-#define I2S_RX_PCM_BYPASS_S  12
-/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */
-/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law
- decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
-#define I2S_RX_PCM_CONF  0x00000003
-#define I2S_RX_PCM_CONF_M  ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
-#define I2S_RX_PCM_CONF_V  0x3
-#define I2S_RX_PCM_CONF_S  10
-/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: 1: The first channel data value is valid in I2S RX mono mode.
-   0: The second channel data value is valid in I2S RX mono mode.*/
-#define I2S_RX_MONO_FST_VLD  (BIT(9))
-#define I2S_RX_MONO_FST_VLD_M  (BIT(9))
-#define I2S_RX_MONO_FST_VLD_V  0x1
-#define I2S_RX_MONO_FST_VLD_S  9
-/* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set 1 to update I2S RX registers from APB clock domain to I2S
- RX clock domain. This bit will be cleared by hardware after update register done.*/
-#define I2S_RX_UPDATE  (BIT(8))
-#define I2S_RX_UPDATE_M  (BIT(8))
-#define I2S_RX_UPDATE_V  0x1
-#define I2S_RX_UPDATE_S  8
-/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: I2S Rx byte endian  1: low addr value to high addr. 0: low addr
- with low addr value.*/
-#define I2S_RX_BIG_ENDIAN  (BIT(7))
-#define I2S_RX_BIG_ENDIAN_M  (BIT(7))
-#define I2S_RX_BIG_ENDIAN_V  0x1
-#define I2S_RX_BIG_ENDIAN_S  7
-/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable receiver  in mono mode*/
-#define I2S_RX_MONO  (BIT(5))
-#define I2S_RX_MONO_M  (BIT(5))
-#define I2S_RX_MONO_V  0x1
-#define I2S_RX_MONO_S  5
-/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable slave receiver mode*/
-#define I2S_RX_SLAVE_MOD  (BIT(3))
-#define I2S_RX_SLAVE_MOD_M  (BIT(3))
-#define I2S_RX_SLAVE_MOD_V  0x1
-#define I2S_RX_SLAVE_MOD_S  3
-/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to start receiving data*/
-#define I2S_RX_START  (BIT(2))
-#define I2S_RX_START_M  (BIT(2))
-#define I2S_RX_START_V  0x1
-#define I2S_RX_START_S  2
-/* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to reset Rx AFIFO*/
-#define I2S_RX_FIFO_RESET  (BIT(1))
-#define I2S_RX_FIFO_RESET_M  (BIT(1))
-#define I2S_RX_FIFO_RESET_V  0x1
-#define I2S_RX_FIFO_RESET_S  1
-/* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to reset receiver*/
-#define I2S_RX_RESET  (BIT(0))
-#define I2S_RX_RESET_M  (BIT(0))
-#define I2S_RX_RESET_V  0x1
-#define I2S_RX_RESET_S  0
-
-#define I2S_TX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0024)
-/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Enable signal loop back mode with transmitter module and receiver
- module sharing the same WS and BCK signals.*/
-#define I2S_SIG_LOOPBACK  (BIT(27))
-#define I2S_SIG_LOOPBACK_M  (BIT(27))
-#define I2S_SIG_LOOPBACK_V  0x1
-#define I2S_SIG_LOOPBACK_S  27
-/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */
-/*description: I2S transmitter channel mode configuration bits.*/
-#define I2S_TX_CHAN_MOD  0x00000007
-#define I2S_TX_CHAN_MOD_M  ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S))
-#define I2S_TX_CHAN_MOD_V  0x7
-#define I2S_TX_CHAN_MOD_S  24
-/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/
-#define I2S_TX_PDM_EN  (BIT(20))
-#define I2S_TX_PDM_EN_M  (BIT(20))
-#define I2S_TX_PDM_EN_V  0x1
-#define I2S_TX_PDM_EN_S  20
-/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/
-#define I2S_TX_TDM_EN  (BIT(19))
-#define I2S_TX_TDM_EN_M  (BIT(19))
-#define I2S_TX_TDM_EN_V  0x1
-#define I2S_TX_TDM_EN_S  19
-/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: I2S Tx bit endian. 1:small endian  the LSB is sent first. 0:big
- endian  the MSB is sent first.*/
-#define I2S_TX_BIT_ORDER  (BIT(18))
-#define I2S_TX_BIT_ORDER_M  (BIT(18))
-#define I2S_TX_BIT_ORDER_V  0x1
-#define I2S_TX_BIT_ORDER_S  18
-/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: 0: WS should be 0 when sending left channel data  and WS is 1in
- right channel.  1: WS should be 1 when sending left channel data  and WS is 0in right channel.*/
-#define I2S_TX_WS_IDLE_POL  (BIT(17))
-#define I2S_TX_WS_IDLE_POL_M  (BIT(17))
-#define I2S_TX_WS_IDLE_POL_V  0x1
-#define I2S_TX_WS_IDLE_POL_S  17
-/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
-#define I2S_TX_24_FILL_EN  (BIT(16))
-#define I2S_TX_24_FILL_EN_M  (BIT(16))
-#define I2S_TX_24_FILL_EN_V  0x1
-#define I2S_TX_24_FILL_EN_S  16
-/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
-#define I2S_TX_LEFT_ALIGN  (BIT(15))
-#define I2S_TX_LEFT_ALIGN_M  (BIT(15))
-#define I2S_TX_LEFT_ALIGN_V  0x1
-#define I2S_TX_LEFT_ALIGN_S  15
-/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to stop disable output BCK signal and WS signal
- when tx FIFO is emtpy*/
-#define I2S_TX_STOP_EN  (BIT(13))
-#define I2S_TX_STOP_EN_M  (BIT(13))
-#define I2S_TX_STOP_EN_V  0x1
-#define I2S_TX_STOP_EN_S  13
-/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to bypass  Compress/Decompress module for transmitted data.*/
-#define I2S_TX_PCM_BYPASS  (BIT(12))
-#define I2S_TX_PCM_BYPASS_M  (BIT(12))
-#define I2S_TX_PCM_BYPASS_V  0x1
-#define I2S_TX_PCM_BYPASS_S  12
-/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law
- decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
-#define I2S_TX_PCM_CONF  0x00000003
-#define I2S_TX_PCM_CONF_M  ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
-#define I2S_TX_PCM_CONF_V  0x3
-#define I2S_TX_PCM_CONF_S  10
-/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: 1: The first channel data value is valid in I2S TX mono mode.
-   0: The second channel data value is valid in I2S TX mono mode.*/
-#define I2S_TX_MONO_FST_VLD  (BIT(9))
-#define I2S_TX_MONO_FST_VLD_M  (BIT(9))
-#define I2S_TX_MONO_FST_VLD_V  0x1
-#define I2S_TX_MONO_FST_VLD_S  9
-/* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set 1 to update I2S TX registers from APB clock domain to I2S
- TX clock domain. This bit will be cleared by hardware after update register done.*/
-#define I2S_TX_UPDATE  (BIT(8))
-#define I2S_TX_UPDATE_M  (BIT(8))
-#define I2S_TX_UPDATE_V  0x1
-#define I2S_TX_UPDATE_S  8
-/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: I2S Tx byte endian  1: low addr value to high addr.  0: low addr
- with low addr value.*/
-#define I2S_TX_BIG_ENDIAN  (BIT(7))
-#define I2S_TX_BIG_ENDIAN_M  (BIT(7))
-#define I2S_TX_BIG_ENDIAN_V  0x1
-#define I2S_TX_BIG_ENDIAN_S  7
-/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: 1: The value of Left channel data is equal to the value of right
- channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
-#define I2S_TX_CHAN_EQUAL  (BIT(6))
-#define I2S_TX_CHAN_EQUAL_M  (BIT(6))
-#define I2S_TX_CHAN_EQUAL_V  0x1
-#define I2S_TX_CHAN_EQUAL_S  6
-/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable transmitter in mono mode*/
-#define I2S_TX_MONO  (BIT(5))
-#define I2S_TX_MONO_M  (BIT(5))
-#define I2S_TX_MONO_V  0x1
-#define I2S_TX_MONO_S  5
-/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable slave transmitter mode*/
-#define I2S_TX_SLAVE_MOD  (BIT(3))
-#define I2S_TX_SLAVE_MOD_M  (BIT(3))
-#define I2S_TX_SLAVE_MOD_V  0x1
-#define I2S_TX_SLAVE_MOD_S  3
-/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to start transmitting data*/
-#define I2S_TX_START  (BIT(2))
-#define I2S_TX_START_M  (BIT(2))
-#define I2S_TX_START_V  0x1
-#define I2S_TX_START_S  2
-/* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to reset Tx AFIFO*/
-#define I2S_TX_FIFO_RESET  (BIT(1))
-#define I2S_TX_FIFO_RESET_M  (BIT(1))
-#define I2S_TX_FIFO_RESET_V  0x1
-#define I2S_TX_FIFO_RESET_S  1
-/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to reset transmitter*/
-#define I2S_TX_RESET  (BIT(0))
-#define I2S_TX_RESET_M  (BIT(0))
-#define I2S_TX_RESET_V  0x1
-#define I2S_TX_RESET_S  0
-
-#define I2S_RX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x0028)
-/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to enable receiver in Phillips standard mode*/
-#define I2S_RX_MSB_SHIFT  (BIT(29))
-#define I2S_RX_MSB_SHIFT_M  (BIT(29))
-#define I2S_RX_MSB_SHIFT_V  0x1
-#define I2S_RX_MSB_SHIFT_S  29
-/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */
-/*description: The Rx bit number for each channel minus 1in TDM mode.*/
-#define I2S_RX_TDM_CHAN_BITS  0x0000001F
-#define I2S_RX_TDM_CHAN_BITS_M  ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S))
-#define I2S_RX_TDM_CHAN_BITS_V  0x1F
-#define I2S_RX_TDM_CHAN_BITS_S  24
-/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */
-/*description: I2S Rx half sample bits -1.*/
-#define I2S_RX_HALF_SAMPLE_BITS  0x0000003F
-#define I2S_RX_HALF_SAMPLE_BITS_M  ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S))
-#define I2S_RX_HALF_SAMPLE_BITS_V  0x3F
-#define I2S_RX_HALF_SAMPLE_BITS_S  18
-/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */
-/*description: Set the bits to configure bit length of I2S receiver channel.*/
-#define I2S_RX_BITS_MOD  0x0000001F
-#define I2S_RX_BITS_MOD_M  ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
-#define I2S_RX_BITS_MOD_V  0x1F
-#define I2S_RX_BITS_MOD_S  13
-/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
-/*description: Bit clock configuration bits in receiver mode.*/
-#define I2S_RX_BCK_DIV_NUM  0x0000003F
-#define I2S_RX_BCK_DIV_NUM_M  ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S))
-#define I2S_RX_BCK_DIV_NUM_V  0x3F
-#define I2S_RX_BCK_DIV_NUM_S  7
-/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
-/*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
-#define I2S_RX_TDM_WS_WIDTH  0x0000007F
-#define I2S_RX_TDM_WS_WIDTH_M  ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S))
-#define I2S_RX_TDM_WS_WIDTH_V  0x7F
-#define I2S_RX_TDM_WS_WIDTH_S  0
-
-#define I2S_TX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x002C)
-/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to enable transmitter in Phillips standard mode*/
-#define I2S_TX_MSB_SHIFT  (BIT(29))
-#define I2S_TX_MSB_SHIFT_M  (BIT(29))
-#define I2S_TX_MSB_SHIFT_V  0x1
-#define I2S_TX_MSB_SHIFT_S  29
-/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */
-/*description: The Tx bit number for each channel minus 1in TDM mode.*/
-#define I2S_TX_TDM_CHAN_BITS  0x0000001F
-#define I2S_TX_TDM_CHAN_BITS_M  ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S))
-#define I2S_TX_TDM_CHAN_BITS_V  0x1F
-#define I2S_TX_TDM_CHAN_BITS_S  24
-/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */
-/*description: I2S Tx half sample bits -1.*/
-#define I2S_TX_HALF_SAMPLE_BITS  0x0000003F
-#define I2S_TX_HALF_SAMPLE_BITS_M  ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S))
-#define I2S_TX_HALF_SAMPLE_BITS_V  0x3F
-#define I2S_TX_HALF_SAMPLE_BITS_S  18
-/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */
-/*description: Set the bits to configure bit length of I2S transmitter channel.*/
-#define I2S_TX_BITS_MOD  0x0000001F
-#define I2S_TX_BITS_MOD_M  ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S))
-#define I2S_TX_BITS_MOD_V  0x1F
-#define I2S_TX_BITS_MOD_S  13
-/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
-/*description: Bit clock configuration bits in transmitter mode.*/
-#define I2S_TX_BCK_DIV_NUM  0x0000003F
-#define I2S_TX_BCK_DIV_NUM_M  ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S))
-#define I2S_TX_BCK_DIV_NUM_V  0x3F
-#define I2S_TX_BCK_DIV_NUM_S  7
-/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
-/*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
-#define I2S_TX_TDM_WS_WIDTH  0x0000007F
-#define I2S_TX_TDM_WS_WIDTH_M  ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S))
-#define I2S_TX_TDM_WS_WIDTH_V  0x7F
-#define I2S_TX_TDM_WS_WIDTH_S  0
-
-#define I2S_RX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0030)
-/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module
- clock as I2S_MCLK_OUT.*/
-#define I2S_MCLK_SEL  (BIT(29))
-#define I2S_MCLK_SEL_M  (BIT(29))
-#define I2S_MCLK_SEL_V  0x1
-#define I2S_MCLK_SEL_S  29
-/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
-/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160.
- 3: I2S_MCLK_in.*/
-#define I2S_RX_CLK_SEL  0x00000003
-#define I2S_RX_CLK_SEL_M  ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S))
-#define I2S_RX_CLK_SEL_V  0x3
-#define I2S_RX_CLK_SEL_S  27
-/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: I2S Rx module clock enable signal.*/
-#define I2S_RX_CLK_ACTIVE  (BIT(26))
-#define I2S_RX_CLK_ACTIVE_M  (BIT(26))
-#define I2S_RX_CLK_ACTIVE_V  0x1
-#define I2S_RX_CLK_ACTIVE_S  26
-/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
-/*description: Integral I2S clock divider value*/
-#define I2S_RX_CLKM_DIV_NUM  0x000000FF
-#define I2S_RX_CLKM_DIV_NUM_M  ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S))
-#define I2S_RX_CLKM_DIV_NUM_V  0xFF
-#define I2S_RX_CLKM_DIV_NUM_S  0
-
-#define I2S_TX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0034)
-/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable clk gate*/
-#define I2S_CLK_EN  (BIT(29))
-#define I2S_CLK_EN_M  (BIT(29))
-#define I2S_CLK_EN_V  0x1
-#define I2S_CLK_EN_S  29
-/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
-/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2:
- CLK160. 3: I2S_MCLK_in.*/
-#define I2S_TX_CLK_SEL  0x00000003
-#define I2S_TX_CLK_SEL_M  ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S))
-#define I2S_TX_CLK_SEL_V  0x3
-#define I2S_TX_CLK_SEL_S  27
-/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: I2S Tx module clock enable signal.*/
-#define I2S_TX_CLK_ACTIVE  (BIT(26))
-#define I2S_TX_CLK_ACTIVE_M  (BIT(26))
-#define I2S_TX_CLK_ACTIVE_V  0x1
-#define I2S_TX_CLK_ACTIVE_S  26
-/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
-/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a).
- There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
-#define I2S_TX_CLKM_DIV_NUM  0x000000FF
-#define I2S_TX_CLKM_DIV_NUM_M  ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S))
-#define I2S_TX_CLKM_DIV_NUM_V  0xFF
-#define I2S_TX_CLKM_DIV_NUM_S  0
-
-#define I2S_RX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0038)
-/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b >
- a/2  the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
-#define I2S_RX_CLKM_DIV_YN1  (BIT(27))
-#define I2S_RX_CLKM_DIV_YN1_M  (BIT(27))
-#define I2S_RX_CLKM_DIV_YN1_V  0x1
-#define I2S_RX_CLKM_DIV_YN1_S  27
-/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
-/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For
- b > a/2  the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
-#define I2S_RX_CLKM_DIV_X  0x000001FF
-#define I2S_RX_CLKM_DIV_X_M  ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S))
-#define I2S_RX_CLKM_DIV_X_V  0x1FF
-#define I2S_RX_CLKM_DIV_X_S  18
-/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
-/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b
- > a/2  the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
-#define I2S_RX_CLKM_DIV_Y  0x000001FF
-#define I2S_RX_CLKM_DIV_Y_M  ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S))
-#define I2S_RX_CLKM_DIV_Y_V  0x1FF
-#define I2S_RX_CLKM_DIV_Y_S  9
-/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2
-  the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
-#define I2S_RX_CLKM_DIV_Z  0x000001FF
-#define I2S_RX_CLKM_DIV_Z_M  ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S))
-#define I2S_RX_CLKM_DIV_Z_V  0x1FF
-#define I2S_RX_CLKM_DIV_Z_S  0
-
-#define I2S_TX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x003C)
-/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b >
- a/2  the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
-#define I2S_TX_CLKM_DIV_YN1  (BIT(27))
-#define I2S_TX_CLKM_DIV_YN1_M  (BIT(27))
-#define I2S_TX_CLKM_DIV_YN1_V  0x1
-#define I2S_TX_CLKM_DIV_YN1_S  27
-/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
-/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For
- b > a/2  the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
-#define I2S_TX_CLKM_DIV_X  0x000001FF
-#define I2S_TX_CLKM_DIV_X_M  ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S))
-#define I2S_TX_CLKM_DIV_X_V  0x1FF
-#define I2S_TX_CLKM_DIV_X_S  18
-/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
-/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b
- > a/2  the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
-#define I2S_TX_CLKM_DIV_Y  0x000001FF
-#define I2S_TX_CLKM_DIV_Y_M  ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S))
-#define I2S_TX_CLKM_DIV_Y_V  0x1FF
-#define I2S_TX_CLKM_DIV_Y_S  9
-/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2
-  the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
-#define I2S_TX_CLKM_DIV_Z  0x000001FF
-#define I2S_TX_CLKM_DIV_Z_M  ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S))
-#define I2S_TX_CLKM_DIV_Z_V  0x1FF
-#define I2S_TX_CLKM_DIV_Z_S  0
-
-#define I2S_TX_PCM2PDM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x040)
-/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: I2S TX PDM Converter enable.*/
-#define I2S_PCM2PDM_CONV_EN    (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_M  (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_V  0x1
-#define I2S_PCM2PDM_CONV_EN_S  25
-/* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: I2S TX PDM dac 2channel enable.*/
-#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_M  (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_V  0x1
-#define I2S_TX_PDM_DAC_MODE_EN_S  24
-/* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: I2S TX PDM dac mode enable.*/
-#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_M  (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_V  0x1
-#define I2S_TX_PDM_DAC_2OUT_EN_S  23
-/* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: I2S TX PDM sigmadelta dither value.*/
-#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x1
-#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
-/* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: I2S TX PDM sigmadelta dither2 value.*/
-#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x1
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
-/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */
-/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
-/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */
-/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
-#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003
-#define I2S_TX_PDM_SINC_IN_SHIFT_M  ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
-#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
-/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */
-/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
-#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003
-#define I2S_TX_PDM_LP_IN_SHIFT_M  ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
-#define I2S_TX_PDM_LP_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_LP_IN_SHIFT_S  15
-/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
-/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
-#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003
-#define I2S_TX_PDM_HP_IN_SHIFT_M  ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
-#define I2S_TX_PDM_HP_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_HP_IN_SHIFT_S  13
-/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */
-/*description: I2S TX PDM prescale for sigmadelta.*/
-#define I2S_TX_PDM_PRESCALE    0x000000FF
-#define I2S_TX_PDM_PRESCALE_M  ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
-#define I2S_TX_PDM_PRESCALE_V  0xFF
-#define I2S_TX_PDM_PRESCALE_S  5
-/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */
-/*description: I2S TX PDM OSR2 value.*/
-#define I2S_TX_PDM_SINC_OSR2    0x0000000F
-#define I2S_TX_PDM_SINC_OSR2_M  ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
-#define I2S_TX_PDM_SINC_OSR2_V  0xF
-#define I2S_TX_PDM_SINC_OSR2_S  1
-/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/
-#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
-#define I2S_TX_PDM_HP_BYPASS_M  (BIT(0))
-#define I2S_TX_PDM_HP_BYPASS_V  0x1
-#define I2S_TX_PDM_HP_BYPASS_S  0
-
-#define I2S_TX_PCM2PDM_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x44)
-/* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */
-/*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL
-T12_0[2:0]).*/
-#define I2S_TX_IIR_HP_MULT12_0    0x00000007
-#define I2S_TX_IIR_HP_MULT12_0_M  ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S))
-#define I2S_TX_IIR_HP_MULT12_0_V  0x7
-#define I2S_TX_IIR_HP_MULT12_0_S  23
-/* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */
-/*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL
-T12_5[2:0]).*/
-#define I2S_TX_IIR_HP_MULT12_5    0x00000007
-#define I2S_TX_IIR_HP_MULT12_5_M  ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S))
-#define I2S_TX_IIR_HP_MULT12_5_V  0x7
-#define I2S_TX_IIR_HP_MULT12_5_S  20
-/* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */
-/*description: I2S TX PDM Fs.*/
-#define I2S_TX_PDM_FS    0x000003FF
-#define I2S_TX_PDM_FS_M  ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
-#define I2S_TX_PDM_FS_V  0x3FF
-#define I2S_TX_PDM_FS_S  10
-/* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */
-/*description: I2S TX PDM Fp.*/
-#define I2S_TX_PDM_FP    0x000003FF
-#define I2S_TX_PDM_FP_M  ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
-#define I2S_TX_PDM_FP_V  0x3FF
-#define I2S_TX_PDM_FP_S  0
-
-#define I2S_RX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x050)
-/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
-/*description: The total channel number of I2S TX TDM mode.*/
-#define I2S_RX_TDM_TOT_CHAN_NUM  0x0000000F
-#define I2S_RX_TDM_TOT_CHAN_NUM_M  ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S))
-#define I2S_RX_TDM_TOT_CHAN_NUM_V  0xF
-#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
-/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
- Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_CHAN15_EN  (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_M  (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_V  0x1
-#define I2S_RX_TDM_CHAN15_EN_S  15
-/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
- Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_CHAN14_EN  (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_M  (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_V  0x1
-#define I2S_RX_TDM_CHAN14_EN_S  14
-/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
- Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_CHAN13_EN  (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_M  (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_V  0x1
-#define I2S_RX_TDM_CHAN13_EN_S  13
-/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
- Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_CHAN12_EN  (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_M  (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_V  0x1
-#define I2S_RX_TDM_CHAN12_EN_S  12
-/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
- Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_CHAN11_EN  (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_M  (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_V  0x1
-#define I2S_RX_TDM_CHAN11_EN_S  11
-/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
- Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_CHAN10_EN  (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_M  (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_V  0x1
-#define I2S_RX_TDM_CHAN10_EN_S  10
-/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
- Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_CHAN9_EN  (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_M  (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_V  0x1
-#define I2S_RX_TDM_CHAN9_EN_S  9
-/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
- Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_CHAN8_EN  (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_M  (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_V  0x1
-#define I2S_RX_TDM_CHAN8_EN_S  8
-/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
- 0:  Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_PDM_CHAN7_EN  (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_M  (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
-/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
- 0:  Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_PDM_CHAN6_EN  (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_M  (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
-/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
- 0:  Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_PDM_CHAN5_EN  (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_M  (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
-/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
- 0:  Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_PDM_CHAN4_EN  (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_M  (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
-/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
- 0:  Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_PDM_CHAN3_EN  (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_M  (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
-/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
- 0:  Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_PDM_CHAN2_EN  (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_M  (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
-/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
- 0:  Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_PDM_CHAN1_EN  (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_M  (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
-/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
- 0:  Disable  just input 0 in this channel.*/
-#define I2S_RX_TDM_PDM_CHAN0_EN  (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_M  (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
-
-#define I2S_TX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x0054)
-/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM
- + 1)  channels  and only the data of the enabled channels is sent  then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
-#define I2S_TX_TDM_SKIP_MSK_EN  (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_M  (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_V  0x1
-#define I2S_TX_TDM_SKIP_MSK_EN_S  20
-/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
-/*description: The total channel number minus 1 of I2S TX TDM mode.*/
-#define I2S_TX_TDM_TOT_CHAN_NUM  0x0000000F
-#define I2S_TX_TDM_TOT_CHAN_NUM_M  ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S))
-#define I2S_TX_TDM_TOT_CHAN_NUM_V  0xF
-#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
-/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN15_EN  (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_M  (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_V  0x1
-#define I2S_TX_TDM_CHAN15_EN_S  15
-/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN14_EN  (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_M  (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_V  0x1
-#define I2S_TX_TDM_CHAN14_EN_S  14
-/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN13_EN  (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_M  (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_V  0x1
-#define I2S_TX_TDM_CHAN13_EN_S  13
-/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN12_EN  (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_M  (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_V  0x1
-#define I2S_TX_TDM_CHAN12_EN_S  12
-/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN11_EN  (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_M  (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_V  0x1
-#define I2S_TX_TDM_CHAN11_EN_S  11
-/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN10_EN  (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_M  (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_V  0x1
-#define I2S_TX_TDM_CHAN10_EN_S  10
-/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN9_EN  (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_M  (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_V  0x1
-#define I2S_TX_TDM_CHAN9_EN_S  9
-/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN8_EN  (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_M  (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_V  0x1
-#define I2S_TX_TDM_CHAN8_EN_S  8
-/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN7_EN  (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_M  (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_V  0x1
-#define I2S_TX_TDM_CHAN7_EN_S  7
-/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN6_EN  (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_M  (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_V  0x1
-#define I2S_TX_TDM_CHAN6_EN_S  6
-/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN5_EN  (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_M  (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_V  0x1
-#define I2S_TX_TDM_CHAN5_EN_S  5
-/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN4_EN  (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_M  (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_V  0x1
-#define I2S_TX_TDM_CHAN4_EN_S  4
-/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN3_EN  (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_M  (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_V  0x1
-#define I2S_TX_TDM_CHAN3_EN_S  3
-/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN2_EN  (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_M  (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_V  0x1
-#define I2S_TX_TDM_CHAN2_EN_S  2
-/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN1_EN  (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_M  (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_V  0x1
-#define I2S_TX_TDM_CHAN1_EN_S  1
-/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
-  Disable  just output 0 in this channel.*/
-#define I2S_TX_TDM_CHAN0_EN  (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_M  (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_V  0x1
-#define I2S_TX_TDM_CHAN0_EN_S  0
-
-#define I2S_RX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x0058)
-/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_RX_BCK_IN_DM  0x00000003
-#define I2S_RX_BCK_IN_DM_M  ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S))
-#define I2S_RX_BCK_IN_DM_V  0x3
-#define I2S_RX_BCK_IN_DM_S  28
-/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_RX_WS_IN_DM  0x00000003
-#define I2S_RX_WS_IN_DM_M  ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S))
-#define I2S_RX_WS_IN_DM_V  0x3
-#define I2S_RX_WS_IN_DM_S  24
-/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_RX_BCK_OUT_DM  0x00000003
-#define I2S_RX_BCK_OUT_DM_M  ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S))
-#define I2S_RX_BCK_OUT_DM_V  0x3
-#define I2S_RX_BCK_OUT_DM_S  20
-/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_RX_WS_OUT_DM  0x00000003
-#define I2S_RX_WS_OUT_DM_M  ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S))
-#define I2S_RX_WS_OUT_DM_V  0x3
-#define I2S_RX_WS_OUT_DM_S  16
-/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_RX_SD_IN_DM  0x00000003
-#define I2S_RX_SD_IN_DM_M  ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S))
-#define I2S_RX_SD_IN_DM_V  0x3
-#define I2S_RX_SD_IN_DM_S  0
-
-#define I2S_TX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x005C)
-/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_TX_BCK_IN_DM  0x00000003
-#define I2S_TX_BCK_IN_DM_M  ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S))
-#define I2S_TX_BCK_IN_DM_V  0x3
-#define I2S_TX_BCK_IN_DM_S  28
-/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_TX_WS_IN_DM  0x00000003
-#define I2S_TX_WS_IN_DM_M  ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S))
-#define I2S_TX_WS_IN_DM_V  0x3
-#define I2S_TX_WS_IN_DM_S  24
-/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_TX_BCK_OUT_DM  0x00000003
-#define I2S_TX_BCK_OUT_DM_M  ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S))
-#define I2S_TX_BCK_OUT_DM_V  0x3
-#define I2S_TX_BCK_OUT_DM_S  20
-/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_TX_WS_OUT_DM  0x00000003
-#define I2S_TX_WS_OUT_DM_M  ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S))
-#define I2S_TX_WS_OUT_DM_V  0x3
-#define I2S_TX_WS_OUT_DM_S  16
-/* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
- delay by neg edge. 3: not used..*/
-#define I2S_TX_SD1_OUT_DM    0x00000003
-#define I2S_TX_SD1_OUT_DM_M  ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S))
-#define I2S_TX_SD1_OUT_DM_V  0x3
-#define I2S_TX_SD1_OUT_DM_S  4
-/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay
- by pos edge.  2: delay by neg edge. 3: not used.*/
-#define I2S_TX_SD_OUT_DM  0x00000003
-#define I2S_TX_SD_OUT_DM_M  ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S))
-#define I2S_TX_SD_OUT_DM_V  0x3
-#define I2S_TX_SD_OUT_DM_S  0
-
-#define I2S_LC_HUNG_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0060)
-/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: The enable bit for FIFO timeout*/
-#define I2S_LC_FIFO_TIMEOUT_ENA  (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_M  (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x1
-#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
-/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
-/*description: The bits are used to scale tick counter threshold. The tick counter
- is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
-#define I2S_LC_FIFO_TIMEOUT_SHIFT  0x00000007
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x7
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
-/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
-/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt
- will be triggered when fifo hung counter is equal to this value*/
-#define I2S_LC_FIFO_TIMEOUT  0x000000FF
-#define I2S_LC_FIFO_TIMEOUT_M  ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S))
-#define I2S_LC_FIFO_TIMEOUT_V  0xFF
-#define I2S_LC_FIFO_TIMEOUT_S  0
-
-#define I2S_RXEOF_NUM_REG(i)          (REG_I2S_BASE(i) + 0x0064)
-/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */
-/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
-#define I2S_RX_EOF_NUM  0x00000FFF
-#define I2S_RX_EOF_NUM_M  ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
-#define I2S_RX_EOF_NUM_V  0xFFF
-#define I2S_RX_EOF_NUM_S  0
-
-#define I2S_CONF_SIGLE_DATA_REG(i)          (REG_I2S_BASE(i) + 0x0068)
-/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: the right channel or left channel put out constant value stored
- in this register according to tx_chan_mod and reg_tx_msb_right*/
-#define I2S_SINGLE_DATA  0xFFFFFFFF
-#define I2S_SINGLE_DATA_M  ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S))
-#define I2S_SINGLE_DATA_V  0xFFFFFFFF
-#define I2S_SINGLE_DATA_S  0
-
-#define I2S_STATE_REG(i)          (REG_I2S_BASE(i) + 0x006C)
-/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/
-#define I2S_TX_IDLE  (BIT(0))
-#define I2S_TX_IDLE_M  (BIT(0))
-#define I2S_TX_IDLE_V  0x1
-#define I2S_TX_IDLE_S  0
-
-#define I2S_DATE_REG(i)          (REG_I2S_BASE(i) + 0x0080)
-/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */
-/*description: Version control register*/
-#define I2S_DATE  0x0FFFFFFF
-#define I2S_DATE_M  ((I2S_DATE_V)<<(I2S_DATE_S))
-#define I2S_DATE_V  0xFFFFFFF
-#define I2S_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_I2S_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/i2s_struct.h b/components/soc/esp32c3/include/soc/i2s_struct.h
deleted file mode 100644
index e0c10e91e97..00000000000
--- a/components/soc/esp32c3/include/soc/i2s_struct.h
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct i2s_dev_s {
-    uint32_t reserved_0;
-    uint32_t reserved_4;
-    uint32_t reserved_8;
-    union {
-        struct {
-            uint32_t rx_done:         1;             /*The raw interrupt status bit  for the i2s_rx_done_int interrupt*/
-            uint32_t tx_done:         1;             /*The raw interrupt status bit  for the i2s_tx_done_int interrupt*/
-            uint32_t rx_hung:         1;             /*The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
-            uint32_t tx_hung:         1;             /*The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
-            uint32_t reserved4:      28;             /*Reserve*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rx_done:        1;              /*The masked interrupt status bit  for the i2s_rx_done_int interrupt*/
-            uint32_t tx_done:        1;              /*The masked interrupt status bit  for the i2s_tx_done_int interrupt*/
-            uint32_t rx_hung:        1;              /*The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
-            uint32_t tx_hung:        1;              /*The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
-            uint32_t reserved4:     28;              /*Reserve*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t rx_done:         1;             /*The interrupt enable bit  for the i2s_rx_done_int interrupt*/
-            uint32_t tx_done:         1;             /*The interrupt enable bit  for the i2s_tx_done_int interrupt*/
-            uint32_t rx_hung:         1;             /*The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
-            uint32_t tx_hung:         1;             /*The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
-            uint32_t reserved4:      28;             /*Reserve*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rx_done:         1;             /*Set this bit to clear the i2s_rx_done_int interrupt*/
-            uint32_t tx_done:         1;             /*Set this bit to clear the i2s_tx_done_int interrupt*/
-            uint32_t rx_hung:         1;             /*Set this bit to clear the i2s_rx_hung_int interrupt*/
-            uint32_t tx_hung:         1;             /*Set this bit to clear the i2s_tx_hung_int interrupt*/
-            uint32_t reserved4:      28;             /*Reserve*/
-        };
-        uint32_t val;
-    } int_clr;
-    uint32_t reserved_1c;
-    union {
-        struct {
-            uint32_t rx_reset:              1;       /*Set this bit to reset receiver*/
-            uint32_t rx_fifo_reset:         1;       /*Set this bit to reset Rx AFIFO*/
-            uint32_t rx_start:              1;       /*Set this bit to start receiving data*/
-            uint32_t rx_slave_mod:          1;       /*Set this bit to enable slave receiver mode*/
-            uint32_t reserved4:             1;       /*Reserved*/
-            uint32_t rx_mono:               1;       /*Set this bit to enable receiver  in mono mode*/
-            uint32_t reserved6:             1;
-            uint32_t rx_big_endian:         1;       /*I2S Rx byte endian  1: low addr value to high addr. 0: low addr with low addr value.*/
-            uint32_t rx_update:             1;       /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
-            uint32_t rx_mono_fst_vld:       1;       /*1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.*/
-            uint32_t rx_pcm_conf:           2;       /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
-            uint32_t rx_pcm_bypass:         1;       /*Set this bit to bypass Compress/Decompress module for received data.*/
-            uint32_t rx_stop_mode:          2;       /*0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
-            uint32_t rx_left_align:         1;       /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
-            uint32_t rx_24_fill_en:         1;       /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
-            uint32_t rx_ws_idle_pol:        1;       /*0: WS should be 0 when receiving left channel data  and WS is 1in right channel.  1: WS should be 1 when receiving left channel data  and WS is 0in right channel.*/
-            uint32_t rx_bit_order:          1;       /*I2S Rx bit endian. 1:small endian  the LSB is received first. 0:big endian  the MSB is received first.*/
-            uint32_t rx_tdm_en:             1;       /*1: Enable I2S TDM Rx mode . 0: Disable.*/
-            uint32_t rx_pdm_en:             1;       /*1: Enable I2S PDM Rx mode . 0: Disable.*/
-            uint32_t reserved23:            11;       /*Reserve*/
-        };
-        uint32_t val;
-    } rx_conf;
-    union {
-        struct {
-            uint32_t tx_reset:        1;             /*Set this bit to reset transmitter*/
-            uint32_t tx_fifo_reset:   1;             /*Set this bit to reset Tx AFIFO*/
-            uint32_t tx_start:        1;             /*Set this bit to start transmitting data*/
-            uint32_t tx_slave_mod:    1;             /*Set this bit to enable slave transmitter mode*/
-            uint32_t reserved4:       1;             /*Reserved*/
-            uint32_t tx_mono:         1;             /*Set this bit to enable transmitter in mono mode*/
-            uint32_t tx_chan_equal:   1;             /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
-            uint32_t tx_big_endian:   1;             /*I2S Tx byte endian  1: low addr value to high addr.  0: low addr with low addr value.*/
-            uint32_t tx_update:       1;             /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
-            uint32_t tx_mono_fst_vld: 1;             /*1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.*/
-            uint32_t tx_pcm_conf:     2;             /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
-            uint32_t tx_pcm_bypass:   1;             /*Set this bit to bypass  Compress/Decompress module for transmitted data.*/
-            uint32_t tx_stop_en:      1;             /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
-            uint32_t reserved14:      1;
-            uint32_t tx_left_align:   1;             /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
-            uint32_t tx_24_fill_en:   1;             /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
-            uint32_t tx_ws_idle_pol:  1;             /*0: WS should be 0 when sending left channel data  and WS is 1in right channel.  1: WS should be 1 when sending left channel data  and WS is 0in right channel.*/
-            uint32_t tx_bit_order:    1;             /*I2S Tx bit endian. 1:small endian  the LSB is sent first. 0:big endian  the MSB is sent first.*/
-            uint32_t tx_tdm_en:       1;             /*1: Enable I2S TDM Tx mode . 0: Disable.*/
-            uint32_t tx_pdm_en:       1;             /*1: Enable I2S PDM Tx mode . 0: Disable.*/
-            uint32_t reserved21:      3;             /*Reserved*/
-            uint32_t tx_chan_mod:     3;             /*I2S transmitter channel mode configuration bits.*/
-            uint32_t sig_loopback:    1;             /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
-            uint32_t reserved28:      4;             /*Reserved*/
-        };
-        uint32_t val;
-    } tx_conf;
-    union {
-        struct {
-            uint32_t rx_tdm_ws_width:     7;         /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
-            uint32_t rx_bck_div_num:      6;         /*Bit clock configuration bits in receiver mode.*/
-            uint32_t rx_bits_mod:         5;         /*Set the bits to configure bit length of I2S receiver channel.*/
-            uint32_t rx_half_sample_bits: 6;         /*I2S Rx half sample bits -1.*/
-            uint32_t rx_tdm_chan_bits:    5;         /*The Rx bit number for each channel minus 1in TDM mode.*/
-            uint32_t rx_msb_shift:        1;         /*Set this bit to enable receiver in Phillips standard mode*/
-            uint32_t reserved30:          2;         /*Reserved*/
-        };
-        uint32_t val;
-    } rx_conf1;
-    union {
-        struct {
-            uint32_t tx_tdm_ws_width:     7;         /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
-            uint32_t tx_bck_div_num:      6;         /*Bit clock configuration bits in transmitter mode.*/
-            uint32_t tx_bits_mod:         5;         /*Set the bits to configure bit length of I2S transmitter channel.*/
-            uint32_t tx_half_sample_bits: 6;         /*I2S Tx half sample bits -1.*/
-            uint32_t tx_tdm_chan_bits:    5;         /*The Tx bit number for each channel minus 1in TDM mode.*/
-            uint32_t tx_msb_shift:        1;         /*Set this bit to enable transmitter in Phillips standard mode*/
-            uint32_t tx_bck_no_dly:       1;         /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
-            uint32_t reserved31:          1;               /* Reserved*/
-        };
-        uint32_t val;
-    } tx_conf1;
-    union {
-        struct {
-            uint32_t rx_clkm_div_num: 8;             /*Integral I2S clock divider value*/
-            uint32_t reserved8:      18;             /*Reserved*/
-            uint32_t rx_clk_active:   1;             /*I2S Rx module clock enable signal.*/
-            uint32_t rx_clk_sel:      2;             /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
-            uint32_t mclk_sel:        1;             /*0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
-            uint32_t reserved30:      2;             /*Reserved*/
-        };
-        uint32_t val;
-    } rx_clkm_conf;
-    union {
-        struct {
-            uint32_t tx_clkm_div_num: 8;             /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
-            uint32_t reserved8:      18;             /*Reserved*/
-            uint32_t tx_clk_active:   1;             /*I2S Tx module clock enable signal.*/
-            uint32_t tx_clk_sel:      2;             /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
-            uint32_t clk_en:          1;             /*Set this bit to enable clk gate*/
-            uint32_t reserved30:      2;             /*Reserved*/
-        };
-        uint32_t val;
-    } tx_clkm_conf;
-    union {
-        struct {
-            uint32_t rx_clkm_div_z:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2  the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
-            uint32_t rx_clkm_div_y:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2  the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
-            uint32_t rx_clkm_div_x:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2  the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
-            uint32_t rx_clkm_div_yn1: 1;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2  the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
-            uint32_t reserved28:      4;             /*Reserved*/
-        };
-        uint32_t val;
-    } rx_clkm_div_conf;
-    union {
-        struct {
-            uint32_t tx_clkm_div_z:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2  the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
-            uint32_t tx_clkm_div_y:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2  the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
-            uint32_t tx_clkm_div_x:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2  the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
-            uint32_t tx_clkm_div_yn1: 1;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2  the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
-            uint32_t reserved28:      4;             /*Reserved*/
-        };
-        uint32_t val;
-    } tx_clkm_div_conf;
-    union {
-        struct {
-            uint32_t tx_pdm_hp_bypass              :    1;  /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
-            uint32_t tx_pdm_sinc_osr2              :    4;  /*I2S TX PDM OSR2 value*/
-            uint32_t tx_pdm_prescale               :    8;  /*I2S TX PDM prescale for sigmadelta*/
-            uint32_t tx_pdm_hp_in_shift            :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
-            uint32_t tx_pdm_lp_in_shift            :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
-            uint32_t tx_pdm_sinc_in_shift          :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
-            uint32_t tx_pdm_sigmadelta_in_shift    :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
-            uint32_t tx_pdm_sigmadelta_dither2     :    1;  /*I2S TX PDM sigmadelta dither2 value*/
-            uint32_t tx_pdm_sigmadelta_dither      :    1;  /*I2S TX PDM sigmadelta dither value*/
-            uint32_t tx_pdm_dac_2out_en            :    1;  /*I2S TX PDM dac mode enable*/
-            uint32_t tx_pdm_dac_mode_en            :    1;  /*I2S TX PDM dac 2channel enable*/
-            uint32_t pcm2pdm_conv_en               :    1;  /*I2S TX PDM Converter enable*/
-            uint32_t reserved26                    :    6;  /*Reserved*/
-        };
-        uint32_t val;
-    } tx_pcm2pdm_conf;
-    union {
-        struct {
-            uint32_t tx_pdm_fp                     :    10;  /*I2S TX PDM Fp*/
-            uint32_t tx_pdm_fs                     :    10;  /*I2S TX PDM Fs*/
-            uint32_t tx_iir_hp_mult12_5            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
-            uint32_t tx_iir_hp_mult12_0            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
-            uint32_t reserved26                    :    6;  /*Reserved*/
-        };
-        uint32_t val;
-    } tx_pcm2pdm_conf1;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    union {
-        struct {
-            uint32_t rx_tdm_pdm_chan0_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_pdm_chan1_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_pdm_chan2_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_pdm_chan3_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_pdm_chan4_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_pdm_chan5_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_pdm_chan6_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_pdm_chan7_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan8_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan9_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan10_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan11_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan12_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan13_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan14_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan15_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_tot_chan_num: 4;         /*The total channel number of I2S TX TDM mode.*/
-            uint32_t reserved20:         12;         /*Reserved*/
-        };
-        uint32_t val;
-    } rx_tdm_ctrl;
-    union {
-        struct {
-            uint32_t tx_tdm_chan0_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan1_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan2_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan3_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan4_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan5_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan6_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan7_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan8_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan9_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan10_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan11_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan12_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan13_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan14_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_chan15_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
-            uint32_t tx_tdm_tot_chan_num: 4;         /*The total channel number minus 1 of I2S TX TDM mode.*/
-            uint32_t tx_tdm_skip_msk_en:  1;         /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels  and only the data of the enabled channels is sent  then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
-            uint32_t reserved21:         11;         /*Reserved*/
-        };
-        uint32_t val;
-    } tx_tdm_ctrl;
-    union {
-        struct {
-            uint32_t rx_sd_in_dm:   2;               /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved2                     :    14;  /* Reserved*/
-            uint32_t rx_ws_out_dm:  2;               /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved18:    2;
-            uint32_t rx_bck_out_dm: 2;               /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved22:    2;
-            uint32_t rx_ws_in_dm:   2;               /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved26:    2;
-            uint32_t rx_bck_in_dm:  2;               /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved30:    2;
-        };
-        uint32_t val;
-    } rx_timing;
-    union {
-        struct {
-            uint32_t tx_sd_out_dm                  :    2;  /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved2                     :    2;  /* Reserved*/
-            uint32_t tx_sd1_out_dm                 :    2;  /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved6                     :    10;  /* Reserved*/
-            uint32_t tx_ws_out_dm                  :    2;  /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved18                    :    2;  /* Reserved*/
-            uint32_t tx_bck_out_dm                 :    2;  /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved22                    :    2;  /* Reserved*/
-            uint32_t tx_ws_in_dm                   :    2;  /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved26                    :    2;  /* Reserved*/
-            uint32_t tx_bck_in_dm                  :    2;  /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved30                    :    2;  /* Reserved*/
-        };
-        uint32_t val;
-    } tx_timing;
-    union {
-        struct {
-            uint32_t fifo_timeout:          8;       /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
-            uint32_t fifo_timeout_shift:    3;       /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
-            uint32_t fifo_timeout_ena:      1;       /*The enable bit for FIFO timeout*/
-            uint32_t reserved12:           20;       /*Reserved*/
-        };
-        uint32_t val;
-    } lc_hung_conf;
-    union {
-        struct {
-            uint32_t rx_eof_num:12;                  /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
-            uint32_t reserved12:20;                  /*Reserved*/
-        };
-        uint32_t val;
-    } rx_eof_num;
-    uint32_t conf_single_data;                     /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
-    union {
-        struct {
-            uint32_t tx_idle:    1;                  /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
-            uint32_t reserved1: 31;                  /*Reserved*/
-        };
-        uint32_t val;
-    } state;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    union {
-        struct {
-            uint32_t date:      28;                  /*Version control register*/
-            uint32_t reserved28: 4;                  /*Reserved*/
-        };
-        uint32_t val;
-    } date;
-} i2s_dev_t;
-extern i2s_dev_t I2S0;
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/interrupt_core0_reg.h b/components/soc/esp32c3/include/soc/interrupt_core0_reg.h
deleted file mode 100644
index f606cdafcaf..00000000000
--- a/components/soc/esp32c3/include/soc/interrupt_core0_reg.h
+++ /dev/null
@@ -1,856 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_INTERRUPT_CORE0_REG_H_
-#define _SOC_INTERRUPT_CORE0_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
-
-#define INTERRUPT_CORE0_MAC_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
-/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_MAC_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_MAC_INTR_MAP_M  ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
-#define INTERRUPT_CORE0_MAC_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_MAC_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_MAC_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
-/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_MAC_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_MAC_NMI_MAP_M  ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
-#define INTERRUPT_CORE0_MAC_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_MAC_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_PWR_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
-/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_PWR_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_PWR_INTR_MAP_M  ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
-#define INTERRUPT_CORE0_PWR_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_PWR_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
-/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_BB_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_BB_INT_MAP_M  ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
-#define INTERRUPT_CORE0_BB_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_BB_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
-/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M  ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
-/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_BT_BB_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_M  ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
-/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
-/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP  0x0000001F
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V  0x1F
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S  0
-
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
-/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP  0x0000001F
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V  0x1F
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S  0
-
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x024)
-/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_RWBT_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_M  ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x028)
-/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M  ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x02C)
-/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x030)
-/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SLC0_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_M  ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x034)
-/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SLC1_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_M  ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x038)
-/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M  ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S))
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x03C)
-/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x040)
-/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP  0x0000001F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x1F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
-
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x044)
-/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x048)
-/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x04C)
-/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S  0
-
-#define INTERRUPT_CORE0_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
-/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_I2S1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_I2S1_INT_MAP_M  ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
-#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_I2S1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
-/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_UART_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_UART_INTR_MAP_M  ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
-#define INTERRUPT_CORE0_UART_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_UART_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_UART1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x058)
-/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_UART1_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_UART1_INTR_MAP_M  ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
-#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x05C)
-/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_LEDC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
-#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x060)
-/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_EFUSE_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_CAN_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
-/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CAN_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_CAN_INT_MAP_M  ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
-#define INTERRUPT_CORE0_CAN_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CAN_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_USB_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
-/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_USB_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_USB_INTR_MAP_M  ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
-#define INTERRUPT_CORE0_USB_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_USB_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x06C)
-/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M  ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_RMT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x070)
-/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_RMT_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_RMT_INTR_MAP_M  ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
-#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x074)
-/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x078)
-/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_TIMER_INT1_MAP  0x0000001F
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_M  ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_V  0x1F
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_S  0
-
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x07C)
-/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_TIMER_INT2_MAP  0x0000001F
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_M  ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_V  0x1F
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_S  0
-
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x080)
-/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG_T0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x084)
-/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x088)
-/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x08C)
-/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x090)
-/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x09C)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0)
-/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M  ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4)
-/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8)
-/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC)
-/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M  ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0)
-/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4)
-/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8)
-/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC)
-/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_RSA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_RSA_INT_MAP_M  ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
-#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_RSA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0)
-/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_AES_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_AES_INT_MAP_M  ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
-#define INTERRUPT_CORE0_AES_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_AES_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4)
-/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_SHA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
-#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SHA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
-
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8)
-/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC)
-/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0)
-/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4)
-/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8)
-/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC)
-/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0)
-/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4)
-/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_INTR_STATUS_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
-/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define INTERRUPT_CORE0_INTR_STATUS_0  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
-#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_0_S  0
-
-#define INTERRUPT_CORE0_INTR_STATUS_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
-/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define INTERRUPT_CORE0_INTR_STATUS_1  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
-#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_1_S  0
-
-#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
-/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define INTERRUPT_CORE0_CLK_EN  (BIT(0))
-#define INTERRUPT_CORE0_CLK_EN_M  (BIT(0))
-#define INTERRUPT_CORE0_CLK_EN_V  0x1
-#define INTERRUPT_CORE0_CLK_EN_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
-/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INT_ENABLE  0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_ENABLE_M  ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S))
-#define INTERRUPT_CORE0_CPU_INT_ENABLE_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_ENABLE_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_TYPE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
-/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INT_TYPE  0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_TYPE_M  ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S))
-#define INTERRUPT_CORE0_CPU_INT_TYPE_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_TYPE_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
-/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INT_CLEAR  0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_CLEAR_M  ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S))
-#define INTERRUPT_CORE0_CPU_INT_CLEAR_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_CLEAR_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
-/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS  0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M  ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S))
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
-/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_0_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
-/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_1_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
-/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_2_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
-/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_3_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
-/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_4_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
-/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_5_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
-/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_6_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
-/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_7_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
-/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_8_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
-/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_9_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
-/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_10_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
-/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_11_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
-/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_12_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
-/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_13_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
-/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_14_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
-/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_15_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
-/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_16_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
-/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_17_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
-/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_18_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
-/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_19_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
-/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_20_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
-/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_21_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
-/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_22_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
-/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_23_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
-/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_24_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
-/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_25_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
-/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_26_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
-/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_27_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
-/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_28_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
-/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_29_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
-/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_30_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
-/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_PRI_31_MAP  0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V  0xF
-#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S  0
-#define INTC_INT_PRIO_REG(n)                        (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
-
-#define INTERRUPT_CORE0_CPU_INT_THRESH_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
-/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INT_THRESH  0x0000000F
-#define INTERRUPT_CORE0_CPU_INT_THRESH_M  ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S))
-#define INTERRUPT_CORE0_CPU_INT_THRESH_V  0xF
-#define INTERRUPT_CORE0_CPU_INT_THRESH_S  0
-
-#define INTERRUPT_CORE0_INTERRUPT_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
-/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007210 ; */
-/*description: */
-#define INTERRUPT_CORE0_INTERRUPT_DATE  0x0FFFFFFF
-#define INTERRUPT_CORE0_INTERRUPT_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
-#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0xFFFFFFF
-#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/interrupt_reg.h b/components/soc/esp32c3/include/soc/interrupt_reg.h
index 749a2e92167..d02c2d5c20c 100644
--- a/components/soc/esp32c3/include/soc/interrupt_reg.h
+++ b/components/soc/esp32c3/include/soc/interrupt_reg.h
@@ -5,7 +5,7 @@
  */
 #pragma once
 
-#include "interrupt_core0_reg.h"
+#include "soc/interrupt_core0_reg.h"
 
 #define INTERRUPT_CURRENT_CORE_INT_THRESH_REG   INTERRUPT_CORE0_CPU_INT_THRESH_REG
 #define INTERRUPT_PRIO_REG(n)                   (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
diff --git a/components/soc/esp32c3/include/soc/interrupts.h b/components/soc/esp32c3/include/soc/interrupts.h
index f332295c4f1..661ec7fc821 100644
--- a/components/soc/esp32c3/include/soc/interrupts.h
+++ b/components/soc/esp32c3/include/soc/interrupts.h
@@ -35,7 +35,7 @@ typedef enum {
     ETS_GPIO_NMI_SOURCE,                        /**< interrupt of GPIO, NMI*/
     ETS_SPI1_INTR_SOURCE,                       /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
     ETS_SPI2_INTR_SOURCE,                       /**< interrupt of SPI2, level*/
-    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
+    ETS_I2S0_INTR_SOURCE,                       /**< interrupt of I2S0, level*/
     ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
     ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
     ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
@@ -51,7 +51,7 @@ typedef enum {
     ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
     ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level*/
     ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
-    ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
+    ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalid Access, LEVEL*/
     ETS_SYSTIMER_TARGET0_INTR_SOURCE,           /**< interrupt of system timer 0 */
     ETS_SYSTIMER_TARGET1_INTR_SOURCE,           /**< interrupt of system timer 1 */
     ETS_SYSTIMER_TARGET2_INTR_SOURCE,           /**< interrupt of system timer 2 */
diff --git a/components/soc/esp32c3/include/soc/io_mux_reg.h b/components/soc/esp32c3/include/soc/io_mux_reg.h
deleted file mode 100644
index f5abe8ee5e8..00000000000
--- a/components/soc/esp32c3/include/soc/io_mux_reg.h
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_IO_MUX_REG_H_
-#define _SOC_IO_MUX_REG_H_
-
-#include "soc.h"
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Pin used for wakeup from sleep */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
-#define FILTER_EN (BIT(15))
-#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
-#define FILTER_EN_V 1
-#define FILTER_EN_S 15
-
-#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-
-
-#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
-
-#define IO_MUX_GPIO0_REG		PERIPHS_IO_MUX_XTAL_32K_P_U
-#define IO_MUX_GPIO1_REG		PERIPHS_IO_MUX_XTAL_32K_N_U
-#define IO_MUX_GPIO2_REG		PERIPHS_IO_MUX_GPIO2_U
-#define IO_MUX_GPIO3_REG		PERIPHS_IO_MUX_GPIO3_U
-#define IO_MUX_GPIO4_REG		PERIPHS_IO_MUX_MTMS_U
-#define IO_MUX_GPIO5_REG		PERIPHS_IO_MUX_MTDI_U
-#define IO_MUX_GPIO6_REG		PERIPHS_IO_MUX_MTCK_U
-#define IO_MUX_GPIO7_REG		PERIPHS_IO_MUX_MTDO_U
-#define IO_MUX_GPIO8_REG		PERIPHS_IO_MUX_GPIO8_U
-#define IO_MUX_GPIO9_REG		PERIPHS_IO_MUX_GPIO9_U
-#define IO_MUX_GPIO10_REG	PERIPHS_IO_MUX_GPIO10_U
-#define IO_MUX_GPIO11_REG	PERIPHS_IO_MUX_VDD_SPI_U
-#define IO_MUX_GPIO12_REG	PERIPHS_IO_MUX_SPIHD_U
-#define IO_MUX_GPIO13_REG	PERIPHS_IO_MUX_SPIWP_U
-#define IO_MUX_GPIO14_REG	PERIPHS_IO_MUX_SPICS0_U
-#define IO_MUX_GPIO15_REG	PERIPHS_IO_MUX_SPICLK_U
-#define IO_MUX_GPIO16_REG	PERIPHS_IO_MUX_SPID_U
-#define IO_MUX_GPIO17_REG	PERIPHS_IO_MUX_SPIQ_U
-#define IO_MUX_GPIO18_REG	PERIPHS_IO_MUX_GPIO18_U
-#define IO_MUX_GPIO19_REG	PERIPHS_IO_MUX_GPIO19_U
-#define IO_MUX_GPIO20_REG	PERIPHS_IO_MUX_U0RXD_U
-#define IO_MUX_GPIO21_REG	PERIPHS_IO_MUX_U0TXD_U
-
-/* Value to set in IO Mux to use a pin as GPIO. */
-#define PIN_FUNC_GPIO								1
-
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
-#define SPI_HD_GPIO_NUM  12
-#define SPI_WP_GPIO_NUM  13
-#define SPI_CS0_GPIO_NUM 14
-#define SPI_CLK_GPIO_NUM 15
-#define SPI_D_GPIO_NUM   16
-#define SPI_Q_GPIO_NUM   17
-
-#define SD_CLK_GPIO_NUM 12
-#define SD_CMD_GPIO_NUM 11
-#define SD_DATA0_GPIO_NUM 13
-#define SD_DATA1_GPIO_NUM 14
-#define SD_DATA2_GPIO_NUM 9
-#define SD_DATA3_GPIO_NUM 10
-
-#define USB_INT_PHY0_DM_GPIO_NUM   18
-#define USB_INT_PHY0_DP_GPIO_NUM   19
-
-#define MAX_RTC_GPIO_NUM 5
-#define MAX_PAD_GPIO_NUM 21
-#define MAX_GPIO_NUM    25
-
-#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
-#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
-#define PAD_POWER_SEL                               BIT(15)
-#define PAD_POWER_SEL_V                             0x1
-#define PAD_POWER_SEL_M                             BIT(15)
-#define PAD_POWER_SEL_S                             15
-
-
-#define PAD_POWER_SWITCH_DELAY                      0x7
-#define PAD_POWER_SWITCH_DELAY_V                    0x7
-#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
-#define PAD_POWER_SWITCH_DELAY_S                    12
-
-
-#define CLK_OUT3                                    0xf
-#define CLK_OUT3_V                                  CLK_OUT3
-#define CLK_OUT3_S                                  8
-#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
-#define CLK_OUT2                                    0xf
-#define CLK_OUT2_V                                  CLK_OUT2
-#define CLK_OUT2_S                                  4
-#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
-#define CLK_OUT1                                    0xf
-#define CLK_OUT1_V                                  CLK_OUT1
-#define CLK_OUT1_S                                  0
-#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
-
-#define PERIPHS_IO_MUX_XTAL_32K_P_U       (REG_IO_MUX_BASE +0x04)
-#define FUNC_XTAL_32K_P_GPIO0                       1
-#define FUNC_XTAL_32K_P_GPIO0_0                     0
-
-#define PERIPHS_IO_MUX_XTAL_32K_N_U       (REG_IO_MUX_BASE +0x08)
-#define FUNC_XTAL_32K_N_GPIO1                       1
-#define FUNC_XTAL_32K_N_GPIO1_0                     0
-
-#define PERIPHS_IO_MUX_GPIO2_U            (REG_IO_MUX_BASE +0x0c)
-#define FUNC_GPIO2_FSPIQ                            2
-#define FUNC_GPIO2_GPIO2                            1
-#define FUNC_GPIO2_GPIO2_0                          0
-
-#define PERIPHS_IO_MUX_GPIO3_U            (REG_IO_MUX_BASE +0x10)
-#define FUNC_GPIO3_GPIO3                            1
-#define FUNC_GPIO3_GPIO3_0                          0
-
-#define PERIPHS_IO_MUX_MTMS_U             (REG_IO_MUX_BASE +0x14)
-#define FUNC_MTMS_FSPIHD                            2
-#define FUNC_MTMS_GPIO4                             1
-#define FUNC_MTMS_MTMS                              0
-
-#define PERIPHS_IO_MUX_MTDI_U             (REG_IO_MUX_BASE +0x18)
-#define FUNC_MTDI_FSPIWP                            2
-#define FUNC_MTDI_GPIO5                             1
-#define FUNC_MTDI_MTDI                              0
-
-#define PERIPHS_IO_MUX_MTCK_U             (REG_IO_MUX_BASE +0x1c)
-#define FUNC_MTCK_FSPICLK                           2
-#define FUNC_MTCK_GPIO6                             1
-#define FUNC_MTCK_MTCK                              0
-
-#define PERIPHS_IO_MUX_MTDO_U             (REG_IO_MUX_BASE +0x20)
-#define FUNC_MTDO_FSPID                             2
-#define FUNC_MTDO_GPIO7                             1
-#define FUNC_MTDO_MTDO                              0
-
-#define PERIPHS_IO_MUX_GPIO8_U            (REG_IO_MUX_BASE +0x24)
-#define FUNC_GPIO8_GPIO8                            1
-#define FUNC_GPIO8_GPIO8_0                          0
-
-#define PERIPHS_IO_MUX_GPIO9_U            (REG_IO_MUX_BASE +0x28)
-#define FUNC_GPIO9_GPIO9                            1
-#define FUNC_GPIO9_GPIO9_0                          0
-
-#define PERIPHS_IO_MUX_GPIO10_U           (REG_IO_MUX_BASE +0x2c)
-#define FUNC_GPIO10_FSPICS0                         2
-#define FUNC_GPIO10_GPIO10                          1
-#define FUNC_GPIO10_GPIO10_0                        0
-
-#define PERIPHS_IO_MUX_VDD_SPI_U          (REG_IO_MUX_BASE +0x30)
-#define FUNC_VDD_SPI_GPIO11                         1
-#define FUNC_VDD_SPI_GPIO11_0                       0
-
-#define PERIPHS_IO_MUX_SPIHD_U            (REG_IO_MUX_BASE +0x34)
-#define FUNC_SPIHD_GPIO12                           1
-#define FUNC_SPIHD_SPIHD                            0
-
-#define PERIPHS_IO_MUX_SPIWP_U            (REG_IO_MUX_BASE +0x38)
-#define FUNC_SPIWP_GPIO13                           1
-#define FUNC_SPIWP_SPIWP                            0
-
-#define PERIPHS_IO_MUX_SPICS0_U           (REG_IO_MUX_BASE +0x3c)
-#define FUNC_SPICS0_GPIO14                          1
-#define FUNC_SPICS0_SPICS0                          0
-
-#define PERIPHS_IO_MUX_SPICLK_U           (REG_IO_MUX_BASE +0x40)
-#define FUNC_SPICLK_GPIO15                          1
-#define FUNC_SPICLK_SPICLK                          0
-
-#define PERIPHS_IO_MUX_SPID_U             (REG_IO_MUX_BASE +0x44)
-#define FUNC_SPID_GPIO16                            1
-#define FUNC_SPID_SPID                              0
-
-#define PERIPHS_IO_MUX_SPIQ_U             (REG_IO_MUX_BASE +0x48)
-#define FUNC_SPIQ_GPIO17                            1
-#define FUNC_SPIQ_SPIQ                              0
-
-#define PERIPHS_IO_MUX_GPIO18_U           (REG_IO_MUX_BASE +0x4c)
-#define FUNC_GPIO18_GPIO18                          1
-#define FUNC_GPIO18_GPIO18_0                        0
-
-#define PERIPHS_IO_MUX_GPIO19_U           (REG_IO_MUX_BASE +0x50)
-#define FUNC_GPIO19_GPIO19                          1
-#define FUNC_GPIO19_GPIO19_0                        0
-
-#define PERIPHS_IO_MUX_U0RXD_U            (REG_IO_MUX_BASE +0x54)
-#define FUNC_U0RXD_GPIO20                           1
-#define FUNC_U0RXD_U0RXD                            0
-
-#define PERIPHS_IO_MUX_U0TXD_U            (REG_IO_MUX_BASE +0x58)
-#define FUNC_U0TXD_GPIO21                           1
-#define FUNC_U0TXD_U0TXD                            0
-
-#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
-#define IO_MUX_DATE 0xFFFFFFFF
-#define IO_MUX_DATE_S 0
-#define IO_MUX_DATE_VERSION 0x2006050
-
-#endif
diff --git a/components/soc/esp32c3/include/soc/ledc_reg.h b/components/soc/esp32c3/include/soc/ledc_reg.h
deleted file mode 100644
index 0cc9334130b..00000000000
--- a/components/soc/esp32c3/include/soc/ledc_reg.h
+++ /dev/null
@@ -1,1226 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_LEDC_REG_H_
-#define _SOC_LEDC_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define LEDC_LSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x0000)
-/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH0  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH0_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH0_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH0_S  16
-/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH0  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH0_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH0_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH0_S  15
-/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH0  0x000003FF
-#define LEDC_OVF_NUM_LSCH0_M  ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S))
-#define LEDC_OVF_NUM_LSCH0_V  0x3FF
-#define LEDC_OVF_NUM_LSCH0_S  5
-/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH0  (BIT(4))
-#define LEDC_PARA_UP_LSCH0_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH0_V  0x1
-#define LEDC_PARA_UP_LSCH0_S  4
-/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH0  (BIT(3))
-#define LEDC_IDLE_LV_LSCH0_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH0_V  0x1
-#define LEDC_IDLE_LV_LSCH0_S  3
-/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH0  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH0_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH0_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH0_S  2
-/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH0  0x00000003
-#define LEDC_TIMER_SEL_LSCH0_M  ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
-#define LEDC_TIMER_SEL_LSCH0_V  0x3
-#define LEDC_TIMER_SEL_LSCH0_S  0
-
-#define LEDC_LSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0004)
-/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH0  0x00003FFF
-#define LEDC_HPOINT_LSCH0_M  ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
-#define LEDC_HPOINT_LSCH0_V  0x3FFF
-#define LEDC_HPOINT_LSCH0_S  0
-
-#define LEDC_LSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x0008)
-/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH0  0x0007FFFF
-#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
-#define LEDC_DUTY_LSCH0_V  0x7FFFF
-#define LEDC_DUTY_LSCH0_S  0
-
-#define LEDC_LSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x000C)
-/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH0  (BIT(31))
-#define LEDC_DUTY_START_LSCH0_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH0_V  0x1
-#define LEDC_DUTY_START_LSCH0_S  31
-/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH0  (BIT(30))
-#define LEDC_DUTY_INC_LSCH0_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH0_V  0x1
-#define LEDC_DUTY_INC_LSCH0_S  30
-/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH0  0x000003FF
-#define LEDC_DUTY_NUM_LSCH0_M  ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
-#define LEDC_DUTY_NUM_LSCH0_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH0_S  20
-/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH0  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH0_M  ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
-#define LEDC_DUTY_CYCLE_LSCH0_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH0_S  10
-/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH0  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH0_M  ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
-#define LEDC_DUTY_SCALE_LSCH0_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH0_S  0
-
-#define LEDC_LSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0010)
-/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH0  0x0007FFFF
-#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
-#define LEDC_DUTY_LSCH0_V  0x7FFFF
-#define LEDC_DUTY_LSCH0_S  0
-
-#define LEDC_LSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x0014)
-/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH1  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH1_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH1_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH1_S  16
-/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH1  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH1_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH1_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH1_S  15
-/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH1  0x000003FF
-#define LEDC_OVF_NUM_LSCH1_M  ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S))
-#define LEDC_OVF_NUM_LSCH1_V  0x3FF
-#define LEDC_OVF_NUM_LSCH1_S  5
-/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH1  (BIT(4))
-#define LEDC_PARA_UP_LSCH1_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH1_V  0x1
-#define LEDC_PARA_UP_LSCH1_S  4
-/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH1  (BIT(3))
-#define LEDC_IDLE_LV_LSCH1_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH1_V  0x1
-#define LEDC_IDLE_LV_LSCH1_S  3
-/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH1  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH1_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH1_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH1_S  2
-/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH1  0x00000003
-#define LEDC_TIMER_SEL_LSCH1_M  ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
-#define LEDC_TIMER_SEL_LSCH1_V  0x3
-#define LEDC_TIMER_SEL_LSCH1_S  0
-
-#define LEDC_LSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0018)
-/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH1  0x00003FFF
-#define LEDC_HPOINT_LSCH1_M  ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
-#define LEDC_HPOINT_LSCH1_V  0x3FFF
-#define LEDC_HPOINT_LSCH1_S  0
-
-#define LEDC_LSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x001C)
-/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH1  0x0007FFFF
-#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
-#define LEDC_DUTY_LSCH1_V  0x7FFFF
-#define LEDC_DUTY_LSCH1_S  0
-
-#define LEDC_LSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x0020)
-/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH1  (BIT(31))
-#define LEDC_DUTY_START_LSCH1_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH1_V  0x1
-#define LEDC_DUTY_START_LSCH1_S  31
-/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH1  (BIT(30))
-#define LEDC_DUTY_INC_LSCH1_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH1_V  0x1
-#define LEDC_DUTY_INC_LSCH1_S  30
-/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH1  0x000003FF
-#define LEDC_DUTY_NUM_LSCH1_M  ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
-#define LEDC_DUTY_NUM_LSCH1_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH1_S  20
-/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH1  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH1_M  ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
-#define LEDC_DUTY_CYCLE_LSCH1_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH1_S  10
-/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH1  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH1_M  ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
-#define LEDC_DUTY_SCALE_LSCH1_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH1_S  0
-
-#define LEDC_LSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0024)
-/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH1  0x0007FFFF
-#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
-#define LEDC_DUTY_LSCH1_V  0x7FFFF
-#define LEDC_DUTY_LSCH1_S  0
-
-#define LEDC_LSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x0028)
-/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH2  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH2_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH2_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH2_S  16
-/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH2  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH2_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH2_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH2_S  15
-/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH2  0x000003FF
-#define LEDC_OVF_NUM_LSCH2_M  ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S))
-#define LEDC_OVF_NUM_LSCH2_V  0x3FF
-#define LEDC_OVF_NUM_LSCH2_S  5
-/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH2  (BIT(4))
-#define LEDC_PARA_UP_LSCH2_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH2_V  0x1
-#define LEDC_PARA_UP_LSCH2_S  4
-/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH2  (BIT(3))
-#define LEDC_IDLE_LV_LSCH2_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH2_V  0x1
-#define LEDC_IDLE_LV_LSCH2_S  3
-/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH2  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH2_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH2_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH2_S  2
-/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH2  0x00000003
-#define LEDC_TIMER_SEL_LSCH2_M  ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
-#define LEDC_TIMER_SEL_LSCH2_V  0x3
-#define LEDC_TIMER_SEL_LSCH2_S  0
-
-#define LEDC_LSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x002C)
-/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH2  0x00003FFF
-#define LEDC_HPOINT_LSCH2_M  ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
-#define LEDC_HPOINT_LSCH2_V  0x3FFF
-#define LEDC_HPOINT_LSCH2_S  0
-
-#define LEDC_LSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x0030)
-/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH2  0x0007FFFF
-#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
-#define LEDC_DUTY_LSCH2_V  0x7FFFF
-#define LEDC_DUTY_LSCH2_S  0
-
-#define LEDC_LSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x0034)
-/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH2  (BIT(31))
-#define LEDC_DUTY_START_LSCH2_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH2_V  0x1
-#define LEDC_DUTY_START_LSCH2_S  31
-/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH2  (BIT(30))
-#define LEDC_DUTY_INC_LSCH2_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH2_V  0x1
-#define LEDC_DUTY_INC_LSCH2_S  30
-/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH2  0x000003FF
-#define LEDC_DUTY_NUM_LSCH2_M  ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
-#define LEDC_DUTY_NUM_LSCH2_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH2_S  20
-/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH2  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH2_M  ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
-#define LEDC_DUTY_CYCLE_LSCH2_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH2_S  10
-/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH2  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH2_M  ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
-#define LEDC_DUTY_SCALE_LSCH2_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH2_S  0
-
-#define LEDC_LSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0038)
-/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH2  0x0007FFFF
-#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
-#define LEDC_DUTY_LSCH2_V  0x7FFFF
-#define LEDC_DUTY_LSCH2_S  0
-
-#define LEDC_LSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x003C)
-/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH3  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH3_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH3_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH3_S  16
-/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH3  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH3_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH3_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH3_S  15
-/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH3  0x000003FF
-#define LEDC_OVF_NUM_LSCH3_M  ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S))
-#define LEDC_OVF_NUM_LSCH3_V  0x3FF
-#define LEDC_OVF_NUM_LSCH3_S  5
-/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH3  (BIT(4))
-#define LEDC_PARA_UP_LSCH3_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH3_V  0x1
-#define LEDC_PARA_UP_LSCH3_S  4
-/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH3  (BIT(3))
-#define LEDC_IDLE_LV_LSCH3_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH3_V  0x1
-#define LEDC_IDLE_LV_LSCH3_S  3
-/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH3  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH3_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH3_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH3_S  2
-/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH3  0x00000003
-#define LEDC_TIMER_SEL_LSCH3_M  ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
-#define LEDC_TIMER_SEL_LSCH3_V  0x3
-#define LEDC_TIMER_SEL_LSCH3_S  0
-
-#define LEDC_LSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0040)
-/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH3  0x00003FFF
-#define LEDC_HPOINT_LSCH3_M  ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
-#define LEDC_HPOINT_LSCH3_V  0x3FFF
-#define LEDC_HPOINT_LSCH3_S  0
-
-#define LEDC_LSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x0044)
-/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH3  0x0007FFFF
-#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
-#define LEDC_DUTY_LSCH3_V  0x7FFFF
-#define LEDC_DUTY_LSCH3_S  0
-
-#define LEDC_LSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x0048)
-/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH3  (BIT(31))
-#define LEDC_DUTY_START_LSCH3_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH3_V  0x1
-#define LEDC_DUTY_START_LSCH3_S  31
-/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH3  (BIT(30))
-#define LEDC_DUTY_INC_LSCH3_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH3_V  0x1
-#define LEDC_DUTY_INC_LSCH3_S  30
-/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH3  0x000003FF
-#define LEDC_DUTY_NUM_LSCH3_M  ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
-#define LEDC_DUTY_NUM_LSCH3_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH3_S  20
-/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH3  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH3_M  ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
-#define LEDC_DUTY_CYCLE_LSCH3_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH3_S  10
-/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH3  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH3_M  ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
-#define LEDC_DUTY_SCALE_LSCH3_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH3_S  0
-
-#define LEDC_LSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x004C)
-/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH3  0x0007FFFF
-#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
-#define LEDC_DUTY_LSCH3_V  0x7FFFF
-#define LEDC_DUTY_LSCH3_S  0
-
-#define LEDC_LSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x0050)
-/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH4  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH4_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH4_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH4_S  16
-/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH4  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH4_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH4_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH4_S  15
-/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH4  0x000003FF
-#define LEDC_OVF_NUM_LSCH4_M  ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S))
-#define LEDC_OVF_NUM_LSCH4_V  0x3FF
-#define LEDC_OVF_NUM_LSCH4_S  5
-/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH4  (BIT(4))
-#define LEDC_PARA_UP_LSCH4_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH4_V  0x1
-#define LEDC_PARA_UP_LSCH4_S  4
-/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH4  (BIT(3))
-#define LEDC_IDLE_LV_LSCH4_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH4_V  0x1
-#define LEDC_IDLE_LV_LSCH4_S  3
-/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH4  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH4_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH4_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH4_S  2
-/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH4  0x00000003
-#define LEDC_TIMER_SEL_LSCH4_M  ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
-#define LEDC_TIMER_SEL_LSCH4_V  0x3
-#define LEDC_TIMER_SEL_LSCH4_S  0
-
-#define LEDC_LSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0054)
-/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH4  0x00003FFF
-#define LEDC_HPOINT_LSCH4_M  ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
-#define LEDC_HPOINT_LSCH4_V  0x3FFF
-#define LEDC_HPOINT_LSCH4_S  0
-
-#define LEDC_LSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x0058)
-/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH4  0x0007FFFF
-#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
-#define LEDC_DUTY_LSCH4_V  0x7FFFF
-#define LEDC_DUTY_LSCH4_S  0
-
-#define LEDC_LSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x005C)
-/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH4  (BIT(31))
-#define LEDC_DUTY_START_LSCH4_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH4_V  0x1
-#define LEDC_DUTY_START_LSCH4_S  31
-/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH4  (BIT(30))
-#define LEDC_DUTY_INC_LSCH4_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH4_V  0x1
-#define LEDC_DUTY_INC_LSCH4_S  30
-/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH4  0x000003FF
-#define LEDC_DUTY_NUM_LSCH4_M  ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
-#define LEDC_DUTY_NUM_LSCH4_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH4_S  20
-/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH4  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH4_M  ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
-#define LEDC_DUTY_CYCLE_LSCH4_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH4_S  10
-/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH4  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH4_M  ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
-#define LEDC_DUTY_SCALE_LSCH4_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH4_S  0
-
-#define LEDC_LSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0060)
-/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH4  0x0007FFFF
-#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
-#define LEDC_DUTY_LSCH4_V  0x7FFFF
-#define LEDC_DUTY_LSCH4_S  0
-
-#define LEDC_LSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0064)
-/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH5  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH5_M  (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH5_V  0x1
-#define LEDC_OVF_CNT_RESET_LSCH5_S  16
-/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH5  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH5_M  (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH5_V  0x1
-#define LEDC_OVF_CNT_EN_LSCH5_S  15
-/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH5  0x000003FF
-#define LEDC_OVF_NUM_LSCH5_M  ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S))
-#define LEDC_OVF_NUM_LSCH5_V  0x3FF
-#define LEDC_OVF_NUM_LSCH5_S  5
-/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH5  (BIT(4))
-#define LEDC_PARA_UP_LSCH5_M  (BIT(4))
-#define LEDC_PARA_UP_LSCH5_V  0x1
-#define LEDC_PARA_UP_LSCH5_S  4
-/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH5  (BIT(3))
-#define LEDC_IDLE_LV_LSCH5_M  (BIT(3))
-#define LEDC_IDLE_LV_LSCH5_V  0x1
-#define LEDC_IDLE_LV_LSCH5_S  3
-/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH5  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH5_M  (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH5_V  0x1
-#define LEDC_SIG_OUT_EN_LSCH5_S  2
-/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH5  0x00000003
-#define LEDC_TIMER_SEL_LSCH5_M  ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
-#define LEDC_TIMER_SEL_LSCH5_V  0x3
-#define LEDC_TIMER_SEL_LSCH5_S  0
-
-#define LEDC_LSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0068)
-/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH5  0x00003FFF
-#define LEDC_HPOINT_LSCH5_M  ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
-#define LEDC_HPOINT_LSCH5_V  0x3FFF
-#define LEDC_HPOINT_LSCH5_S  0
-
-#define LEDC_LSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x006C)
-/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH5  0x0007FFFF
-#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
-#define LEDC_DUTY_LSCH5_V  0x7FFFF
-#define LEDC_DUTY_LSCH5_S  0
-
-#define LEDC_LSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0070)
-/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH5  (BIT(31))
-#define LEDC_DUTY_START_LSCH5_M  (BIT(31))
-#define LEDC_DUTY_START_LSCH5_V  0x1
-#define LEDC_DUTY_START_LSCH5_S  31
-/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH5  (BIT(30))
-#define LEDC_DUTY_INC_LSCH5_M  (BIT(30))
-#define LEDC_DUTY_INC_LSCH5_V  0x1
-#define LEDC_DUTY_INC_LSCH5_S  30
-/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH5  0x000003FF
-#define LEDC_DUTY_NUM_LSCH5_M  ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
-#define LEDC_DUTY_NUM_LSCH5_V  0x3FF
-#define LEDC_DUTY_NUM_LSCH5_S  20
-/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH5  0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH5_M  ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
-#define LEDC_DUTY_CYCLE_LSCH5_V  0x3FF
-#define LEDC_DUTY_CYCLE_LSCH5_S  10
-/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH5  0x000003FF
-#define LEDC_DUTY_SCALE_LSCH5_M  ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
-#define LEDC_DUTY_SCALE_LSCH5_V  0x3FF
-#define LEDC_DUTY_SCALE_LSCH5_S  0
-
-#define LEDC_LSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0074)
-/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH5  0x0007FFFF
-#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
-#define LEDC_DUTY_LSCH5_V  0x7FFFF
-#define LEDC_DUTY_LSCH5_S  0
-
-#define LEDC_LSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x00a0)
-/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER0_PARA_UP  (BIT(25))
-#define LEDC_LSTIMER0_PARA_UP_M  (BIT(25))
-#define LEDC_LSTIMER0_PARA_UP_V  0x1
-#define LEDC_LSTIMER0_PARA_UP_S  25
-/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER0  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER0_M  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER0_V  0x1
-#define LEDC_TICK_SEL_LSTIMER0_S  24
-/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER0_RST  (BIT(23))
-#define LEDC_LSTIMER0_RST_M  (BIT(23))
-#define LEDC_LSTIMER0_RST_V  0x1
-#define LEDC_LSTIMER0_RST_S  23
-/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_PAUSE  (BIT(22))
-#define LEDC_LSTIMER0_PAUSE_M  (BIT(22))
-#define LEDC_LSTIMER0_PAUSE_V  0x1
-#define LEDC_LSTIMER0_PAUSE_S  22
-/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER0  0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER0_M  ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S))
-#define LEDC_CLK_DIV_LSTIMER0_V  0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER0_S  4
-/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER0_DUTY_RES  0x0000000F
-#define LEDC_LSTIMER0_DUTY_RES_M  ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
-#define LEDC_LSTIMER0_DUTY_RES_V  0xF
-#define LEDC_LSTIMER0_DUTY_RES_S  0
-
-#define LEDC_LSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x00a4)
-/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_CNT  0x00003FFF
-#define LEDC_LSTIMER0_CNT_M  ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
-#define LEDC_LSTIMER0_CNT_V  0x3FFF
-#define LEDC_LSTIMER0_CNT_S  0
-
-#define LEDC_LSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x00a8)
-/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER1_PARA_UP  (BIT(25))
-#define LEDC_LSTIMER1_PARA_UP_M  (BIT(25))
-#define LEDC_LSTIMER1_PARA_UP_V  0x1
-#define LEDC_LSTIMER1_PARA_UP_S  25
-/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER1  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER1_M  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER1_V  0x1
-#define LEDC_TICK_SEL_LSTIMER1_S  24
-/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER1_RST  (BIT(23))
-#define LEDC_LSTIMER1_RST_M  (BIT(23))
-#define LEDC_LSTIMER1_RST_V  0x1
-#define LEDC_LSTIMER1_RST_S  23
-/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_PAUSE  (BIT(22))
-#define LEDC_LSTIMER1_PAUSE_M  (BIT(22))
-#define LEDC_LSTIMER1_PAUSE_V  0x1
-#define LEDC_LSTIMER1_PAUSE_S  22
-/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER1  0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER1_M  ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S))
-#define LEDC_CLK_DIV_LSTIMER1_V  0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER1_S  4
-/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER1_DUTY_RES  0x0000000F
-#define LEDC_LSTIMER1_DUTY_RES_M  ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
-#define LEDC_LSTIMER1_DUTY_RES_V  0xF
-#define LEDC_LSTIMER1_DUTY_RES_S  0
-
-#define LEDC_LSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x00aC)
-/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_CNT  0x00003FFF
-#define LEDC_LSTIMER1_CNT_M  ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
-#define LEDC_LSTIMER1_CNT_V  0x3FFF
-#define LEDC_LSTIMER1_CNT_S  0
-
-#define LEDC_LSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x00b0)
-/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER2_PARA_UP  (BIT(25))
-#define LEDC_LSTIMER2_PARA_UP_M  (BIT(25))
-#define LEDC_LSTIMER2_PARA_UP_V  0x1
-#define LEDC_LSTIMER2_PARA_UP_S  25
-/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER2  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER2_M  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER2_V  0x1
-#define LEDC_TICK_SEL_LSTIMER2_S  24
-/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER2_RST  (BIT(23))
-#define LEDC_LSTIMER2_RST_M  (BIT(23))
-#define LEDC_LSTIMER2_RST_V  0x1
-#define LEDC_LSTIMER2_RST_S  23
-/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_PAUSE  (BIT(22))
-#define LEDC_LSTIMER2_PAUSE_M  (BIT(22))
-#define LEDC_LSTIMER2_PAUSE_V  0x1
-#define LEDC_LSTIMER2_PAUSE_S  22
-/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER2  0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER2_M  ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S))
-#define LEDC_CLK_DIV_LSTIMER2_V  0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER2_S  4
-/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER2_DUTY_RES  0x0000000F
-#define LEDC_LSTIMER2_DUTY_RES_M  ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
-#define LEDC_LSTIMER2_DUTY_RES_V  0xF
-#define LEDC_LSTIMER2_DUTY_RES_S  0
-
-#define LEDC_LSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x00b4)
-/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_CNT  0x00003FFF
-#define LEDC_LSTIMER2_CNT_M  ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
-#define LEDC_LSTIMER2_CNT_V  0x3FFF
-#define LEDC_LSTIMER2_CNT_S  0
-
-#define LEDC_LSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x00b8)
-/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER3_PARA_UP  (BIT(25))
-#define LEDC_LSTIMER3_PARA_UP_M  (BIT(25))
-#define LEDC_LSTIMER3_PARA_UP_V  0x1
-#define LEDC_LSTIMER3_PARA_UP_S  25
-/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER3  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER3_M  (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER3_V  0x1
-#define LEDC_TICK_SEL_LSTIMER3_S  24
-/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER3_RST  (BIT(23))
-#define LEDC_LSTIMER3_RST_M  (BIT(23))
-#define LEDC_LSTIMER3_RST_V  0x1
-#define LEDC_LSTIMER3_RST_S  23
-/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_PAUSE  (BIT(22))
-#define LEDC_LSTIMER3_PAUSE_M  (BIT(22))
-#define LEDC_LSTIMER3_PAUSE_V  0x1
-#define LEDC_LSTIMER3_PAUSE_S  22
-/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER3  0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER3_M  ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S))
-#define LEDC_CLK_DIV_LSTIMER3_V  0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER3_S  4
-/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER3_DUTY_RES  0x0000000F
-#define LEDC_LSTIMER3_DUTY_RES_M  ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
-#define LEDC_LSTIMER3_DUTY_RES_V  0xF
-#define LEDC_LSTIMER3_DUTY_RES_S  0
-
-#define LEDC_LSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x00BC)
-/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_CNT  0x00003FFF
-#define LEDC_LSTIMER3_CNT_M  ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
-#define LEDC_LSTIMER3_CNT_V  0x3FFF
-#define LEDC_LSTIMER3_CNT_S  0
-
-#define LEDC_INT_RAW_REG          (DR_REG_LEDC_BASE + 0x00C0)
-/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_RAW    (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_M  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_S  15
-/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_RAW    (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_M  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_S  14
-/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_RAW    (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_M  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_S  13
-/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_RAW    (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_M  (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_S  12
-/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_RAW    (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_M  (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_S  11
-/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_RAW    (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_M  (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_V  0x1
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_S  10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S  9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S  8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S  7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S  6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S  5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S  4
-/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_RAW  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_RAW_M  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_RAW_S  3
-/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_RAW  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_RAW_M  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_RAW_S  2
-/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_RAW  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_RAW_M  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_RAW_S  1
-/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_RAW  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_RAW_M  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_RAW_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_RAW_S  0
-
-#define LEDC_INT_ST_REG          (DR_REG_LEDC_BASE + 0x00c4)
-/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_ST  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_ST_M  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH5_INT_ST_S  15
-/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_ST  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_ST_M  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH4_INT_ST_S  14
-/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_ST  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_ST_M  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH3_INT_ST_S  13
-/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_ST    (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_ST_M  (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH2_INT_ST_S  12
-/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_ST    (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_ST_M  (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH1_INT_ST_S  11
-/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_ST    (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_ST_M  (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_ST_V  0x1
-#define LEDC_OVF_CNT_LSCH0_INT_ST_S  10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S  9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S  8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S  7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S  6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S  5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S  4
-/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_ST  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ST_M  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_ST_S  3
-/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_ST  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ST_M  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_ST_S  2
-/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_ST  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ST_M  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_ST_S  1
-/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_ST  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ST_M  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ST_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_ST_S  0
-
-#define LEDC_INT_ENA_REG          (DR_REG_LEDC_BASE + 0xC8)
-/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_ENA    (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_M  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_S  15
-/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_ENA    (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_M  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_S  14
-/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_ENA    (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_M  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_S  13
-/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_ENA    (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_M  (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_S  12
-/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_ENA    (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_M  (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_S  11
-/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_ENA    (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_M  (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_V  0x1
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_S  10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S  9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S  8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S  7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S  6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S  5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S  4
-/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_ENA  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ENA_M  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_ENA_S  3
-/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_ENA  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ENA_M  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_ENA_S  2
-/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_ENA  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ENA_M  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_ENA_S  1
-/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_ENA  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ENA_M  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ENA_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_ENA_S  0
-
-#define LEDC_INT_CLR_REG          (DR_REG_LEDC_BASE + 0xCC)
-/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_CLR    (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_M  (BIT(15))
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_S  15
-/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_CLR    (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_M  (BIT(14))
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_S  14
-/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_CLR    (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_M  (BIT(13))
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_S  13
-/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_CLR    (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_M  (BIT(12))
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_S  12
-/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_CLR    (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_M  (BIT(11))
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_S  11
-/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_CLR    (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_M  (BIT(10))
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_V  0x1
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_S  10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: reg_duty_chng_end_lsch5_int_clr..*/
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M  (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S  9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M  (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S  8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M  (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S  7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M  (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S  6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M  (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S  5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M  (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V  0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S  4
-/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_CLR  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_CLR_M  (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER3_OVF_INT_CLR_S  3
-/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_CLR  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_CLR_M  (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER2_OVF_INT_CLR_S  2
-/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_CLR  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_CLR_M  (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER1_OVF_INT_CLR_S  1
-/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_CLR  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_CLR_M  (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_CLR_V  0x1
-#define LEDC_LSTIMER0_OVF_INT_CLR_S  0
-
-#define LEDC_CONF_REG          (DR_REG_LEDC_BASE + 0x00d0)
-/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_CLK_EN  (BIT(31))
-#define LEDC_CLK_EN_M  (BIT(31))
-#define LEDC_CLK_EN_V  0x1
-#define LEDC_CLK_EN_S  31
-/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define LEDC_APB_CLK_SEL  0x00000003
-#define LEDC_APB_CLK_SEL_M  ((LEDC_APB_CLK_SEL_V)<<(LEDC_APB_CLK_SEL_S))
-#define LEDC_APB_CLK_SEL_V  0x3
-#define LEDC_APB_CLK_SEL_S  0
-
-#define LEDC_DATE_REG          (DR_REG_LEDC_BASE + 0x00FC)
-/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19061700 ; */
-/*description: */
-#define LEDC_DATE  0xFFFFFFFF
-#define LEDC_DATE_M  ((LEDC_DATE_V)<<(LEDC_DATE_S))
-#define LEDC_DATE_V  0xFFFFFFFF
-#define LEDC_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_LEDC_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/nrx_reg.h b/components/soc/esp32c3/include/soc/nrx_reg.h
deleted file mode 100644
index d80cb2a1785..00000000000
--- a/components/soc/esp32c3/include/soc/nrx_reg.h
+++ /dev/null
@@ -1,55 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#pragma once
-
-#include "soc/soc.h"
-
-/* Some of the WiFi RX control registers.
- * PU/PD fields defined here are used in sleep related functions.
- */
-
-#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
-#define NRX_CHAN_EST_FORCE_PU (BIT(7))
-#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
-#define NRX_CHAN_EST_FORCE_PU_V 1
-#define NRX_CHAN_EST_FORCE_PU_S 7
-#define NRX_CHAN_EST_FORCE_PD (BIT(6))
-#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
-#define NRX_CHAN_EST_FORCE_PD_V 1
-#define NRX_CHAN_EST_FORCE_PD_S 6
-#define NRX_RX_ROT_FORCE_PU (BIT(5))
-#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
-#define NRX_RX_ROT_FORCE_PU_V 1
-#define NRX_RX_ROT_FORCE_PU_S 5
-#define NRX_RX_ROT_FORCE_PD (BIT(4))
-#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
-#define NRX_RX_ROT_FORCE_PD_V 1
-#define NRX_RX_ROT_FORCE_PD_S 4
-#define NRX_VIT_FORCE_PU (BIT(3))
-#define NRX_VIT_FORCE_PU_M (BIT(3))
-#define NRX_VIT_FORCE_PU_V 1
-#define NRX_VIT_FORCE_PU_S 3
-#define NRX_VIT_FORCE_PD (BIT(2))
-#define NRX_VIT_FORCE_PD_M (BIT(2))
-#define NRX_VIT_FORCE_PD_V 1
-#define NRX_VIT_FORCE_PD_S 2
-#define NRX_DEMAP_FORCE_PU (BIT(1))
-#define NRX_DEMAP_FORCE_PU_M (BIT(1))
-#define NRX_DEMAP_FORCE_PU_V 1
-#define NRX_DEMAP_FORCE_PU_S 1
-#define NRX_DEMAP_FORCE_PD (BIT(0))
-#define NRX_DEMAP_FORCE_PD_M (BIT(0))
-#define NRX_DEMAP_FORCE_PD_V 1
-#define NRX_DEMAP_FORCE_PD_S 0
diff --git a/components/soc/esp32c3/include/soc/periph_defs.h b/components/soc/esp32c3/include/soc/periph_defs.h
index 063e4f95061..708ec23a835 100644
--- a/components/soc/esp32c3/include/soc/periph_defs.h
+++ b/components/soc/esp32c3/include/soc/periph_defs.h
@@ -18,7 +18,7 @@ typedef enum {
     PERIPH_UART1_MODULE,
     PERIPH_USB_DEVICE_MODULE,
     PERIPH_I2C0_MODULE,
-    PERIPH_I2S1_MODULE,
+    PERIPH_I2S0_MODULE,
     PERIPH_TIMG0_MODULE,
     PERIPH_TIMG1_MODULE,
     PERIPH_UHCI0_MODULE,
diff --git a/components/soc/esp32c3/include/soc/reg_base.h b/components/soc/esp32c3/include/soc/reg_base.h
deleted file mode 100644
index 4ec808f0ab9..00000000000
--- a/components/soc/esp32c3/include/soc/reg_base.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#define DR_REG_SYSTEM_BASE                      0x600c0000
-#define DR_REG_SENSITIVE_BASE                   0x600c1000
-#define DR_REG_INTERRUPT_BASE                   0x600c2000
-#define DR_REG_EXTMEM_BASE                      0x600c4000
-#define DR_REG_MMU_TABLE                        0x600c5000
-#define DR_REG_AES_BASE                         0x6003a000
-#define DR_REG_SHA_BASE                         0x6003b000
-#define DR_REG_RSA_BASE                         0x6003c000
-#define DR_REG_HMAC_BASE                        0x6003e000
-#define DR_REG_DIGITAL_SIGNATURE_BASE           0x6003d000
-#define DR_REG_GDMA_BASE                        0x6003f000
-#define DR_REG_ASSIST_DEBUG_BASE                0x600ce000
-#define DR_REG_DEDICATED_GPIO_BASE              0x600cf000
-#define DR_REG_WORLD_CNTL_BASE                  0x600d0000
-#define DR_REG_UART_BASE                        0x60000000
-#define DR_REG_SPI1_BASE                        0x60002000
-#define DR_REG_SPI0_BASE                        0x60003000
-#define DR_REG_GPIO_BASE                        0x60004000
-#define DR_REG_FE2_BASE                         0x60005000
-#define DR_REG_FE_BASE                          0x60006000
-#define DR_REG_RTCCNTL_BASE                     0x60008000
-#define DR_REG_IO_MUX_BASE                      0x60009000
-#define DR_REG_RTC_I2C_BASE                     0x6000e000
-#define DR_REG_UART1_BASE                       0x60010000
-#define DR_REG_I2C_EXT_BASE                     0x60013000
-#define DR_REG_UHCI0_BASE                       0x60014000
-#define DR_REG_RMT_BASE                         0x60016000
-#define DR_REG_LEDC_BASE                        0x60019000
-#define DR_REG_EFUSE_BASE                       0x60008800
-#define DR_REG_NRX_BASE                         0x6001CC00
-#define DR_REG_BB_BASE                          0x6001D000
-#define DR_REG_TIMERGROUP0_BASE                 0x6001F000
-#define DR_REG_TIMERGROUP1_BASE                 0x60020000
-#define DR_REG_SYSTIMER_BASE                    0x60023000
-#define DR_REG_SPI2_BASE                        0x60024000
-#define DR_REG_SYSCON_BASE                      0x60026000
-#define DR_REG_APB_CTRL_BASE                    0x60026000    /* Old name for SYSCON, to be removed */
-#define DR_REG_TWAI_BASE                        0x6002B000
-#define DR_REG_I2S_BASE                         0x6002D000
-#define DR_REG_APB_SARADC_BASE                  0x60040000
-#define DR_REG_USB_SERIAL_JTAG_BASE             0x60043000
-#define DR_REG_XTS_AES_BASE                     0x600CC000
-
-/* For backward compatability with the older register names */
-#define DR_REG_AES_XTS_BASE                     DR_REG_XTS_AES_BASE
diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
deleted file mode 100644
index 433ca196b3c..00000000000
--- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h
+++ /dev/null
@@ -1,2621 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_RTC_CNTL_REG_H_
-#define _SOC_RTC_CNTL_REG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
-#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
-
-#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0000)
-/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
-/*description: SW system reset*/
-#define RTC_CNTL_SW_SYS_RST  (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_V  0x1
-#define RTC_CNTL_SW_SYS_RST_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: digital core force no reset in deep sleep*/
-#define RTC_CNTL_DG_WRAP_FORCE_NORST  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
-/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: digital wrap force reset in deep sleep*/
-#define RTC_CNTL_DG_WRAP_FORCE_RST  (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
-/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_ANALOG_FORCE_NOISO  (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
-#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
-/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_PLL_FORCE_NOISO  (BIT(27))
-#define RTC_CNTL_PLL_FORCE_NOISO_M  (BIT(27))
-#define RTC_CNTL_PLL_FORCE_NOISO_V  0x1
-#define RTC_CNTL_PLL_FORCE_NOISO_S  27
-/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_XTL_FORCE_NOISO  (BIT(26))
-#define RTC_CNTL_XTL_FORCE_NOISO_M  (BIT(26))
-#define RTC_CNTL_XTL_FORCE_NOISO_V  0x1
-#define RTC_CNTL_XTL_FORCE_NOISO_S  26
-/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_ANALOG_FORCE_ISO  (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
-#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
-/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_PLL_FORCE_ISO  (BIT(24))
-#define RTC_CNTL_PLL_FORCE_ISO_M  (BIT(24))
-#define RTC_CNTL_PLL_FORCE_ISO_V  0x1
-#define RTC_CNTL_PLL_FORCE_ISO_S  24
-/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_XTL_FORCE_ISO  (BIT(23))
-#define RTC_CNTL_XTL_FORCE_ISO_M  (BIT(23))
-#define RTC_CNTL_XTL_FORCE_ISO_V  0x1
-#define RTC_CNTL_XTL_FORCE_ISO_S  23
-/* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
-/*description: */
-#define RTC_CNTL_XTL_EXT_CTR_SEL  0x00000007
-#define RTC_CNTL_XTL_EXT_CTR_SEL_M  ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S))
-#define RTC_CNTL_XTL_EXT_CTR_SEL_V  0x7
-#define RTC_CNTL_XTL_EXT_CTR_SEL_S  20
-/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */
-/*description: wait bias_sleep and current source wakeup*/
-#define RTC_CNTL_XTL_EN_WAIT  0x0000000F
-#define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
-#define RTC_CNTL_XTL_EN_WAIT_V  0xF
-#define RTC_CNTL_XTL_EN_WAIT_S  14
-/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
-/*description: crystall force power up*/
-#define RTC_CNTL_XTL_FORCE_PU  (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_V  0x1
-#define RTC_CNTL_XTL_FORCE_PU_S  13
-/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: crystall force power down*/
-#define RTC_CNTL_XTL_FORCE_PD  (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_V  0x1
-#define RTC_CNTL_XTL_FORCE_PD_S  12
-/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: BB_PLL force power up*/
-#define RTC_CNTL_BBPLL_FORCE_PU  (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
-#define RTC_CNTL_BBPLL_FORCE_PU_S  11
-/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: BB_PLL force power down*/
-#define RTC_CNTL_BBPLL_FORCE_PD  (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
-#define RTC_CNTL_BBPLL_FORCE_PD_S  10
-/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: BB_PLL_I2C force power up*/
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU  (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
-/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: BB_PLL _I2C force power down*/
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD  (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
-/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: BB_I2C force power up*/
-#define RTC_CNTL_BB_I2C_FORCE_PU  (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
-/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: BB_I2C force power down*/
-#define RTC_CNTL_BB_I2C_FORCE_PD  (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
-/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: PRO CPU SW reset*/
-#define RTC_CNTL_SW_PROCPU_RST  (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_V  0x1
-#define RTC_CNTL_SW_PROCPU_RST_S  5
-/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: APP CPU SW reset*/
-#define RTC_CNTL_SW_APPCPU_RST  (BIT(4))
-#define RTC_CNTL_SW_APPCPU_RST_M  (BIT(4))
-#define RTC_CNTL_SW_APPCPU_RST_V  0x1
-#define RTC_CNTL_SW_APPCPU_RST_S  4
-/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: {reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} ==
- 0x86 will stall PRO CPU*/
-#define RTC_CNTL_SW_STALL_PROCPU_C0  0x00000003
-#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
-#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
-#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
-/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
- 0x86 will stall APP CPU*/
-#define RTC_CNTL_SW_STALL_APPCPU_C0  0x00000003
-#define RTC_CNTL_SW_STALL_APPCPU_C0_M  ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
-#define RTC_CNTL_SW_STALL_APPCPU_C0_V  0x3
-#define RTC_CNTL_SW_STALL_APPCPU_C0_S  0
-
-#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x0004)
-/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define RTC_CNTL_SLP_VAL_LO  0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
-#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_S  0
-
-#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x0008)
-/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */
-/*description: timer alarm enable bit*/
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN  (BIT(16))
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
-/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC sleep timer high 16 bits*/
-#define RTC_CNTL_SLP_VAL_HI  0x0000FFFF
-#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
-#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
-#define RTC_CNTL_SLP_VAL_HI_S  0
-
-#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0x000C)
-/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Set 1: to update register with RTC timer*/
-#define RTC_CNTL_TIME_UPDATE  (BIT(31))
-#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
-#define RTC_CNTL_TIME_UPDATE_V  0x1
-#define RTC_CNTL_TIME_UPDATE_S  31
-/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: enable to record system reset time*/
-#define RTC_CNTL_TIMER_SYS_RST  (BIT(29))
-#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
-#define RTC_CNTL_TIMER_SYS_RST_V  0x1
-#define RTC_CNTL_TIMER_SYS_RST_S  29
-/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Enable to record 40M XTAL OFF time*/
-#define RTC_CNTL_TIMER_XTL_OFF  (BIT(28))
-#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
-#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
-#define RTC_CNTL_TIMER_XTL_OFF_S  28
-/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Enable to record system stall time*/
-#define RTC_CNTL_TIMER_SYS_STALL  (BIT(27))
-#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
-#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
-#define RTC_CNTL_TIMER_SYS_STALL_S  27
-
-#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x0010)
-/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: RTC timer low 32 bits*/
-#define RTC_CNTL_TIMER_VALUE0_LOW  0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
-#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
-
-#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x0014)
-/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC timer high 16 bits*/
-#define RTC_CNTL_TIMER_VALUE0_HIGH  0x0000FFFF
-#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
-#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
-#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
-
-#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x0018)
-/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: sleep enable bit*/
-#define RTC_CNTL_SLEEP_EN  (BIT(31))
-#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
-#define RTC_CNTL_SLEEP_EN_V  0x1
-#define RTC_CNTL_SLEEP_EN_S  31
-/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: leep reject bit*/
-#define RTC_CNTL_SLP_REJECT  (BIT(30))
-#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
-#define RTC_CNTL_SLP_REJECT_V  0x1
-#define RTC_CNTL_SLP_REJECT_S  30
-/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: leep wakeup bit*/
-#define RTC_CNTL_SLP_WAKEUP  (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_S  29
-/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
-/*description: SDIO active indication*/
-#define RTC_CNTL_SDIO_ACTIVE_IND  (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
-#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
-/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: 1: APB to RTC using bridge*/
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL  (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
-/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: clear rtc sleep reject cause*/
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
-/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: rtc software interrupt to main cpu*/
-#define RTC_CNTL_SW_CPU_INT  (BIT(0))
-#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
-#define RTC_CNTL_SW_CPU_INT_V  0x1
-#define RTC_CNTL_SW_CPU_INT_S  0
-
-#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x001C)
-/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
-/*description: PLL wait cycles in slow_clk_rtc*/
-#define RTC_CNTL_PLL_BUF_WAIT  0x000000FF
-#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
-#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
-#define RTC_CNTL_PLL_BUF_WAIT_S  24
-#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
-/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
-/*description: XTAL wait cycles in slow_clk_rtc*/
-#define RTC_CNTL_XTL_BUF_WAIT  0x000003FF
-#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
-#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
-#define RTC_CNTL_XTL_BUF_WAIT_S  14
-#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  100
-/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
-/*description: CK8M wait cycles in slow_clk_rtc*/
-#define RTC_CNTL_CK8M_WAIT  0x000000FF
-#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
-#define RTC_CNTL_CK8M_WAIT_V  0xFF
-#define RTC_CNTL_CK8M_WAIT_S  6
-/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
-/*description: CPU stall wait cycles in fast_clk_rtc*/
-#define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
-#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
-#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
-#define RTC_CNTL_CPU_STALL_WAIT_S  1
-/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
-/*description: CPU stall enable bit*/
-#define RTC_CNTL_CPU_STALL_EN  (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_V  0x1
-#define RTC_CNTL_CPU_STALL_EN_S  0
-
-#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x0020)
-/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
-/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/
-#define RTC_CNTL_MIN_TIME_CK8M_OFF  0x000000FF
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
-
-#define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x0024)
-/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */
-/*description: */
-#define RTC_CNTL_BT_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_BT_POWERUP_TIMER_M  ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S))
-#define RTC_CNTL_BT_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_BT_POWERUP_TIMER_S  25
-/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */
-/*description: */
-#define RTC_CNTL_BT_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_BT_WAIT_TIMER_M  ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S))
-#define RTC_CNTL_BT_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_BT_WAIT_TIMER_S  16
-/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
-/*description: */
-#define RTC_CNTL_WIFI_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_WIFI_POWERUP_TIMER_M  ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
-#define RTC_CNTL_WIFI_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_WIFI_POWERUP_TIMER_S  9
-/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
-/*description: */
-#define RTC_CNTL_WIFI_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_WIFI_WAIT_TIMER_M  ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
-#define RTC_CNTL_WIFI_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_WIFI_WAIT_TIMER_S  0
-
-#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x0028)
-/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
-/*description: */
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
-/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
-/*description: */
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
-/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
-/*description: */
-#define RTC_CNTL_CPU_TOP_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M  ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S))
-#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S  9
-/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
-/*description: */
-#define RTC_CNTL_CPU_TOP_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M  ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S))
-#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S  0
-
-#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x002C)
-/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
-/*description: minimal sleep cycles in slow_clk_rtc*/
-#define RTC_CNTL_MIN_SLP_VAL  0x000000FF
-#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
-#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
-#define RTC_CNTL_MIN_SLP_VAL_S  8
-
-#define RTC_CNTL_TIMER6_REG          (DR_REG_RTCCNTL_BASE + 0x0030)
-/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */
-/*description: */
-#define RTC_CNTL_DG_PERI_POWERUP_TIMER  0x0000007F
-#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M  ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S))
-#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S  25
-/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */
-/*description: */
-#define RTC_CNTL_DG_PERI_WAIT_TIMER  0x000001FF
-#define RTC_CNTL_DG_PERI_WAIT_TIMER_M  ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S))
-#define RTC_CNTL_DG_PERI_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_DG_PERI_WAIT_TIMER_S  16
-
-#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0034)
-/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_PLL_I2C_PU  (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_V  0x1
-#define RTC_CNTL_PLL_I2C_PU_S  31
-/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: 1: CKGEN_I2C power up*/
-#define RTC_CNTL_CKGEN_I2C_PU  (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
-#define RTC_CNTL_CKGEN_I2C_PU_S  30
-/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: 1: RFRX_PBUS power up*/
-#define RTC_CNTL_RFRX_PBUS_PU  (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
-#define RTC_CNTL_RFRX_PBUS_PU_S  28
-/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: 1: TXRF_I2C power up*/
-#define RTC_CNTL_TXRF_I2C_PU  (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_V  0x1
-#define RTC_CNTL_TXRF_I2C_PU_S  27
-/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: PVTMON power up*/
-#define RTC_CNTL_PVTMON_PU  (BIT(26))
-#define RTC_CNTL_PVTMON_PU_M  (BIT(26))
-#define RTC_CNTL_PVTMON_PU_V  0x1
-#define RTC_CNTL_PVTMON_PU_S  26
-/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: start BBPLL calibration during sleep*/
-#define RTC_CNTL_BBPLL_CAL_SLP_START  (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
-#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
-/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: PLLA force power up*/
-#define RTC_CNTL_PLLA_FORCE_PU  (BIT(24))
-#define RTC_CNTL_PLLA_FORCE_PU_M  (BIT(24))
-#define RTC_CNTL_PLLA_FORCE_PU_V  0x1
-#define RTC_CNTL_PLLA_FORCE_PU_S  24
-/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: PLLA force power down*/
-#define RTC_CNTL_PLLA_FORCE_PD  (BIT(23))
-#define RTC_CNTL_PLLA_FORCE_PD_M  (BIT(23))
-#define RTC_CNTL_PLLA_FORCE_PD_V  0x1
-#define RTC_CNTL_PLLA_FORCE_PD_S  23
-/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: PLLA force power up*/
-#define RTC_CNTL_SAR_I2C_PU  (BIT(22))
-#define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
-#define RTC_CNTL_SAR_I2C_PU_V  0x1
-#define RTC_CNTL_SAR_I2C_PU_S  22
-/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GLITCH_RST_EN  (BIT(20))
-#define RTC_CNTL_GLITCH_RST_EN_M  (BIT(20))
-#define RTC_CNTL_GLITCH_RST_EN_V  0x1
-#define RTC_CNTL_GLITCH_RST_EN_S  20
-/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU  (BIT(19))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
-/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: */
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD  (BIT(18))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
-
-#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x0038)
-/* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_DRESET_MASK_PROCPU  (BIT(25))
-#define RTC_CNTL_DRESET_MASK_PROCPU_M  (BIT(25))
-#define RTC_CNTL_DRESET_MASK_PROCPU_V  0x1
-#define RTC_CNTL_DRESET_MASK_PROCPU_S  25
-/* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_DRESET_MASK_APPCPU  (BIT(24))
-#define RTC_CNTL_DRESET_MASK_APPCPU_M  (BIT(24))
-#define RTC_CNTL_DRESET_MASK_APPCPU_V  0x1
-#define RTC_CNTL_DRESET_MASK_APPCPU_S  24
-/* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU  (BIT(23))
-#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M  (BIT(23))
-#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V  0x1
-#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S  23
-/* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU  (BIT(22))
-#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M  (BIT(22))
-#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V  0x1
-#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S  22
-/* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU  (BIT(21))
-#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M  (BIT(21))
-#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V  0x1
-#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S  21
-/* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU  (BIT(20))
-#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M  (BIT(20))
-#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V  0x1
-#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S  20
-/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: PROCPU OcdHaltOnReset*/
-#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU  (BIT(19))
-#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M  (BIT(19))
-#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V  0x1
-#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S  19
-/* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: APPCPU OcdHaltOnReset*/
-#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU  (BIT(18))
-#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M  (BIT(18))
-#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V  0x1
-#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S  18
-/* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: clear APP CPU reset flag*/
-#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU  (BIT(17))
-#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M  (BIT(17))
-#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V  0x1
-#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S  17
-/* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: clear PRO CPU reset_flag*/
-#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU  (BIT(16))
-#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M  (BIT(16))
-#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V  0x1
-#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S  16
-/* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: APP CPU reset flag*/
-#define RTC_CNTL_ALL_RESET_FLAG_APPCPU  (BIT(15))
-#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M  (BIT(15))
-#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V  0x1
-#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S  15
-/* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: PRO CPU reset_flag*/
-#define RTC_CNTL_ALL_RESET_FLAG_PROCPU  (BIT(14))
-#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M  (BIT(14))
-#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V  0x1
-#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S  14
-/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: PRO CPU state vector sel*/
-#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU  (BIT(13))
-#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M  (BIT(13))
-#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V  0x1
-#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S  13
-/* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: APP CPU state vector sel*/
-#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU  (BIT(12))
-#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M  (BIT(12))
-#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V  0x1
-#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S  12
-/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
-/*description: reset cause of APP CPU*/
-#define RTC_CNTL_RESET_CAUSE_APPCPU  0x0000003F
-#define RTC_CNTL_RESET_CAUSE_APPCPU_M  ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
-#define RTC_CNTL_RESET_CAUSE_APPCPU_V  0x3F
-#define RTC_CNTL_RESET_CAUSE_APPCPU_S  6
-/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
-/*description: reset cause of PRO CPU*/
-#define RTC_CNTL_RESET_CAUSE_PROCPU  0x0000003F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
-#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
-
-#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x003C)
-/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */
-/*description: wakeup enable bitmap*/
-#define RTC_CNTL_WAKEUP_ENA  0x0001FFFF
-#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
-#define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
-#define RTC_CNTL_WAKEUP_ENA_S  15
-
-#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x0040)
-/* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BBPLL_CAL_INT_ENA  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_S  20
-/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: enbale gitch det interrupt*/
-#define RTC_CNTL_GLITCH_DET_INT_ENA  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_ENA_S  19
-/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: enable xtal32k_dead  interrupt*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S  16
-/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt*/
-#define RTC_CNTL_SWD_INT_ENA  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
-/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt*/
-#define RTC_CNTL_WDT_INT_ENA  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_S  3
-/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
-
-#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x0044)
-/* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BBPLL_CAL_INT_RAW  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_RAW_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_RAW_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_RAW_S  20
-/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: glitch_det_interrupt_raw*/
-#define RTC_CNTL_GLITCH_DET_INT_RAW  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_RAW_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_RAW_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_RAW_S  19
-/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: xtal32k dead detection interrupt raw*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_RAW  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S  16
-/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: super watch dog interrupt raw*/
-#define RTC_CNTL_SWD_INT_RAW  (BIT(15))
-#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_RAW_V  0x1
-#define RTC_CNTL_SWD_INT_RAW_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: RTC main timer interrupt raw*/
-#define RTC_CNTL_MAIN_TIMER_INT_RAW  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
-/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: brown out interrupt raw*/
-#define RTC_CNTL_BROWN_OUT_INT_RAW  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
-/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt raw*/
-#define RTC_CNTL_WDT_INT_RAW  (BIT(3))
-#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_RAW_V  0x1
-#define RTC_CNTL_WDT_INT_RAW_S  3
-/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: sleep reject interrupt raw*/
-#define RTC_CNTL_SLP_REJECT_INT_RAW  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: sleep wakeup interrupt raw*/
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
-
-#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x0048)
-/* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BBPLL_CAL_INT_ST  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ST_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ST_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_ST_S  20
-/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: glitch_det_interrupt state*/
-#define RTC_CNTL_GLITCH_DET_INT_ST  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ST_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ST_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_ST_S  19
-/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: xtal32k dead detection interrupt state*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_ST  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S  16
-/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: super watch dog interrupt state*/
-#define RTC_CNTL_SWD_INT_ST  (BIT(15))
-#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ST_V  0x1
-#define RTC_CNTL_SWD_INT_ST_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: RTC main timer interrupt state*/
-#define RTC_CNTL_MAIN_TIMER_INT_ST  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: brown out interrupt state*/
-#define RTC_CNTL_BROWN_OUT_INT_ST  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
-/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt state*/
-#define RTC_CNTL_WDT_INT_ST  (BIT(3))
-#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ST_V  0x1
-#define RTC_CNTL_WDT_INT_ST_S  3
-/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: sleep reject interrupt state*/
-#define RTC_CNTL_SLP_REJECT_INT_ST  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: sleep wakeup interrupt state*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ST  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
-
-#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x004C)
-/* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BBPLL_CAL_INT_CLR  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_CLR_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_CLR_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_CLR_S  20
-/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Clear glitch det interrupt state*/
-#define RTC_CNTL_GLITCH_DET_INT_CLR  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_CLR_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_CLR_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_CLR_S  19
-/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Clear RTC WDT interrupt state*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_CLR  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S  16
-/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Clear super watch dog interrupt state*/
-#define RTC_CNTL_SWD_INT_CLR  (BIT(15))
-#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_CLR_V  0x1
-#define RTC_CNTL_SWD_INT_CLR_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Clear RTC main timer interrupt state*/
-#define RTC_CNTL_MAIN_TIMER_INT_CLR  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
-/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Clear brown out interrupt state*/
-#define RTC_CNTL_BROWN_OUT_INT_CLR  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
-/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Clear RTC WDT interrupt state*/
-#define RTC_CNTL_WDT_INT_CLR  (BIT(3))
-#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_CLR_V  0x1
-#define RTC_CNTL_WDT_INT_CLR_S  3
-/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Clear sleep reject interrupt state*/
-#define RTC_CNTL_SLP_REJECT_INT_CLR  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Clear sleep wakeup interrupt state*/
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
-
-#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x0050)
-/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_SCRATCH0  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
-#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH0_S  0
-
-#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x0054)
-/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_SCRATCH1  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
-#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH1_S  0
-
-#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x0058)
-/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_SCRATCH2  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
-#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH2_S  0
-
-#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x005C)
-/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_SCRATCH3  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
-#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH3_S  0
-
-#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0060)
-/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_XTL_EXT_CTR_EN  (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
-#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
-/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: power down XTAL at high level*/
-#define RTC_CNTL_XTL_EXT_CTR_LV  (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
-#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
-/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: XTAL_32K sel. 0: external XTAL_32K*/
-#define RTC_CNTL_XTAL32K_GPIO_SEL  (BIT(23))
-#define RTC_CNTL_XTAL32K_GPIO_SEL_M  (BIT(23))
-#define RTC_CNTL_XTAL32K_GPIO_SEL_V  0x1
-#define RTC_CNTL_XTAL32K_GPIO_SEL_S  23
-/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
-/*description: state of 32k_wdt*/
-#define RTC_CNTL_WDT_STATE  0x00000007
-#define RTC_CNTL_WDT_STATE_M  ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S))
-#define RTC_CNTL_WDT_STATE_V  0x7
-#define RTC_CNTL_WDT_STATE_S  20
-/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
-/*description: DAC_XTAL_32K*/
-#define RTC_CNTL_DAC_XTAL_32K  0x00000007
-#define RTC_CNTL_DAC_XTAL_32K_M  ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S))
-#define RTC_CNTL_DAC_XTAL_32K_V  0x7
-#define RTC_CNTL_DAC_XTAL_32K_S  17
-/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: XPD_XTAL_32K*/
-#define RTC_CNTL_XPD_XTAL_32K  (BIT(16))
-#define RTC_CNTL_XPD_XTAL_32K_M  (BIT(16))
-#define RTC_CNTL_XPD_XTAL_32K_V  0x1
-#define RTC_CNTL_XPD_XTAL_32K_S  16
-/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
-/*description: DRES_XTAL_32K*/
-#define RTC_CNTL_DRES_XTAL_32K  0x00000007
-#define RTC_CNTL_DRES_XTAL_32K_M  ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S))
-#define RTC_CNTL_DRES_XTAL_32K_V  0x7
-#define RTC_CNTL_DRES_XTAL_32K_S  13
-/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: xtal_32k gm control*/
-#define RTC_CNTL_DGM_XTAL_32K  0x00000007
-#define RTC_CNTL_DGM_XTAL_32K_M  ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S))
-#define RTC_CNTL_DGM_XTAL_32K_V  0x7
-#define RTC_CNTL_DGM_XTAL_32K_S  10
-/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 0: single-end buffer 1: differential buffer*/
-#define RTC_CNTL_DBUF_XTAL_32K  (BIT(9))
-#define RTC_CNTL_DBUF_XTAL_32K_M  (BIT(9))
-#define RTC_CNTL_DBUF_XTAL_32K_V  0x1
-#define RTC_CNTL_DBUF_XTAL_32K_S  9
-/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: apply an internal clock to help xtal 32k to start*/
-#define RTC_CNTL_ENCKINIT_XTAL_32K  (BIT(8))
-#define RTC_CNTL_ENCKINIT_XTAL_32K_M  (BIT(8))
-#define RTC_CNTL_ENCKINIT_XTAL_32K_V  0x1
-#define RTC_CNTL_ENCKINIT_XTAL_32K_S  8
-/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: Xtal 32k xpd control by sw or fsm*/
-#define RTC_CNTL_XTAL32K_XPD_FORCE  (BIT(7))
-#define RTC_CNTL_XTAL32K_XPD_FORCE_M  (BIT(7))
-#define RTC_CNTL_XTAL32K_XPD_FORCE_V  0x1
-#define RTC_CNTL_XTAL32K_XPD_FORCE_S  7
-/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: xtal 32k switch back xtal when xtal is restarted*/
-#define RTC_CNTL_XTAL32K_AUTO_RETURN  (BIT(6))
-#define RTC_CNTL_XTAL32K_AUTO_RETURN_M  (BIT(6))
-#define RTC_CNTL_XTAL32K_AUTO_RETURN_V  0x1
-#define RTC_CNTL_XTAL32K_AUTO_RETURN_S  6
-/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: xtal 32k restart xtal when xtal is dead*/
-#define RTC_CNTL_XTAL32K_AUTO_RESTART  (BIT(5))
-#define RTC_CNTL_XTAL32K_AUTO_RESTART_M  (BIT(5))
-#define RTC_CNTL_XTAL32K_AUTO_RESTART_V  0x1
-#define RTC_CNTL_XTAL32K_AUTO_RESTART_S  5
-/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: xtal 32k switch to back up clock when xtal is dead*/
-#define RTC_CNTL_XTAL32K_AUTO_BACKUP  (BIT(4))
-#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M  (BIT(4))
-#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V  0x1
-#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S  4
-/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: xtal 32k external xtal clock force on*/
-#define RTC_CNTL_XTAL32K_EXT_CLK_FO  (BIT(3))
-#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M  (BIT(3))
-#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V  0x1
-#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S  3
-/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog sw reset*/
-#define RTC_CNTL_XTAL32K_WDT_RESET  (BIT(2))
-#define RTC_CNTL_XTAL32K_WDT_RESET_M  (BIT(2))
-#define RTC_CNTL_XTAL32K_WDT_RESET_V  0x1
-#define RTC_CNTL_XTAL32K_WDT_RESET_S  2
-/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog clock force on*/
-#define RTC_CNTL_XTAL32K_WDT_CLK_FO  (BIT(1))
-#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M  (BIT(1))
-#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V  0x1
-#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S  1
-/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog enable*/
-#define RTC_CNTL_XTAL32K_WDT_EN  (BIT(0))
-#define RTC_CNTL_XTAL32K_WDT_EN_M  (BIT(0))
-#define RTC_CNTL_XTAL32K_WDT_EN_V  0x1
-#define RTC_CNTL_XTAL32K_WDT_EN_S  0
-
-#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0064)
-/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: enable filter for gpio wakeup event*/
-#define RTC_CNTL_GPIO_WAKEUP_FILTER  (BIT(31))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(31))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  31
-
-#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0068)
-/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: enable reject for deep sleep*/
-#define RTC_CNTL_DEEP_SLP_REJECT_EN  (BIT(31))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
-/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: enable reject for light sleep*/
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN  (BIT(30))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
-/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */
-/*description: sleep reject enable*/
-#define RTC_CNTL_SLEEP_REJECT_ENA  0x0003FFFF
-#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
-#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
-#define RTC_CNTL_SLEEP_REJECT_ENA_S  12
-
-#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x006C)
-/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
-/*description: */
-#define RTC_CNTL_CPUPERIOD_SEL  0x00000003
-#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
-#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
-#define RTC_CNTL_CPUPERIOD_SEL_S  30
-/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: CPU sel option*/
-#define RTC_CNTL_CPUSEL_CONF  (BIT(29))
-#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
-#define RTC_CNTL_CPUSEL_CONF_V  0x1
-#define RTC_CNTL_CPUSEL_CONF_S  29
-
-#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0070)
-/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: */
-#define RTC_CNTL_ANA_CLK_RTC_SEL  0x00000003
-#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
-#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
-#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
-/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: fast_clk_rtc sel. 0: XTAL div 2*/
-#define RTC_CNTL_FAST_CLK_RTC_SEL  (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
-#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
-/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: */
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING  (BIT(28))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
-/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING  (BIT(27))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
-/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: CK8M force power up*/
-#define RTC_CNTL_CK8M_FORCE_PU  (BIT(26))
-#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
-#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
-#define RTC_CNTL_CK8M_FORCE_PU_S  26
-/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: CK8M force power down*/
-#define RTC_CNTL_CK8M_FORCE_PD  (BIT(25))
-#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
-#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
-#define RTC_CNTL_CK8M_FORCE_PD_S  25
-/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */
-/*description: CK8M_DFREQ*/
-#define RTC_CNTL_CK8M_DFREQ  0x000000FF
-#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
-#define RTC_CNTL_CK8M_DFREQ_V  0xFF
-#define RTC_CNTL_CK8M_DFREQ_S  17
-/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: CK8M force no gating during sleep*/
-#define RTC_CNTL_CK8M_FORCE_NOGATING  (BIT(16))
-#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
-#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
-/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: XTAL force no gating during sleep*/
-#define RTC_CNTL_XTAL_FORCE_NOGATING  (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
-/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: divider = reg_ck8m_div_sel + 1*/
-#define RTC_CNTL_CK8M_DIV_SEL  0x00000007
-#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
-#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
-#define RTC_CNTL_CK8M_DIV_SEL_S  12
-/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: enable CK8M for digital core (no relationship with RTC core)*/
-#define RTC_CNTL_DIG_CLK8M_EN  (BIT(10))
-#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
-#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
-#define RTC_CNTL_DIG_CLK8M_EN_S  10
-/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
-/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
-#define RTC_CNTL_DIG_CLK8M_D256_EN  (BIT(9))
-#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
-#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
-#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
-/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
-#define RTC_CNTL_DIG_XTAL32K_EN  (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
-#define RTC_CNTL_DIG_XTAL32K_EN_S  8
-/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: 1: CK8M_D256_OUT is actually CK8M*/
-#define RTC_CNTL_ENB_CK8M_DIV  (BIT(7))
-#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
-#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
-#define RTC_CNTL_ENB_CK8M_DIV_S  7
-/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: disable CK8M and CK8M_D256_OUT*/
-#define RTC_CNTL_ENB_CK8M  (BIT(6))
-#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
-#define RTC_CNTL_ENB_CK8M_V  0x1
-#define RTC_CNTL_ENB_CK8M_S  6
-/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
-/*description: CK8M_D256_OUT divider. 00: div128*/
-#define RTC_CNTL_CK8M_DIV  0x00000003
-#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
-#define RTC_CNTL_CK8M_DIV_V  0x3
-#define RTC_CNTL_CK8M_DIV_S  4
-/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
-#define RTC_CNTL_CK8M_DIV_SEL_VLD  (BIT(3))
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
-/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING  (BIT(2))
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
-/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING  (BIT(1))
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
-
-#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0074)
-/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE  (BIT(31))
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
-/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */
-/*description: */
-#define RTC_CNTL_ANA_CLK_DIV  0x000000FF
-#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
-#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
-#define RTC_CNTL_ANA_CLK_DIV_S  23
-/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
-#define RTC_CNTL_ANA_CLK_DIV_VLD  (BIT(22))
-#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
-#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
-#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
-
-#define RTC_CNTL_SDIO_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0078)
-/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_XPD_SDIO_REG  (BIT(31))
-#define RTC_CNTL_XPD_SDIO_REG_M  (BIT(31))
-#define RTC_CNTL_XPD_SDIO_REG_V  0x1
-#define RTC_CNTL_XPD_SDIO_REG_S  31
-/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
-/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_DREFH_SDIO  0x00000003
-#define RTC_CNTL_DREFH_SDIO_M  ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
-#define RTC_CNTL_DREFH_SDIO_V  0x3
-#define RTC_CNTL_DREFH_SDIO_S  29
-/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */
-/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_DREFM_SDIO  0x00000003
-#define RTC_CNTL_DREFM_SDIO_M  ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
-#define RTC_CNTL_DREFM_SDIO_V  0x3
-#define RTC_CNTL_DREFM_SDIO_S  27
-/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
-/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_DREFL_SDIO  0x00000003
-#define RTC_CNTL_DREFL_SDIO_M  ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
-#define RTC_CNTL_DREFL_SDIO_V  0x3
-#define RTC_CNTL_DREFL_SDIO_S  25
-/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
-/*description: read only register for REG1P8_READY*/
-#define RTC_CNTL_REG1P8_READY  (BIT(24))
-#define RTC_CNTL_REG1P8_READY_M  (BIT(24))
-#define RTC_CNTL_REG1P8_READY_V  0x1
-#define RTC_CNTL_REG1P8_READY_S  24
-/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
-/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
-#define RTC_CNTL_SDIO_TIEH  (BIT(23))
-#define RTC_CNTL_SDIO_TIEH_M  (BIT(23))
-#define RTC_CNTL_SDIO_TIEH_V  0x1
-#define RTC_CNTL_SDIO_TIEH_S  23
-/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: 1: use SW option to control SDIO_REG*/
-#define RTC_CNTL_SDIO_FORCE  (BIT(22))
-#define RTC_CNTL_SDIO_FORCE_M  (BIT(22))
-#define RTC_CNTL_SDIO_FORCE_V  0x1
-#define RTC_CNTL_SDIO_FORCE_S  22
-/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
-/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
-#define RTC_CNTL_SDIO_PD_EN  (BIT(21))
-#define RTC_CNTL_SDIO_PD_EN_M  (BIT(21))
-#define RTC_CNTL_SDIO_PD_EN_V  0x1
-#define RTC_CNTL_SDIO_PD_EN_S  21
-/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */
-/*description: enable current limit*/
-#define RTC_CNTL_SDIO_ENCURLIM  (BIT(20))
-#define RTC_CNTL_SDIO_ENCURLIM_M  (BIT(20))
-#define RTC_CNTL_SDIO_ENCURLIM_V  0x1
-#define RTC_CNTL_SDIO_ENCURLIM_S  20
-/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: select current limit mode*/
-#define RTC_CNTL_SDIO_MODECURLIM  (BIT(19))
-#define RTC_CNTL_SDIO_MODECURLIM_M  (BIT(19))
-#define RTC_CNTL_SDIO_MODECURLIM_V  0x1
-#define RTC_CNTL_SDIO_MODECURLIM_S  19
-/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */
-/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
-#define RTC_CNTL_SDIO_DCURLIM  0x00000007
-#define RTC_CNTL_SDIO_DCURLIM_M  ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S))
-#define RTC_CNTL_SDIO_DCURLIM_V  0x7
-#define RTC_CNTL_SDIO_DCURLIM_S  16
-/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */
-/*description: 0 to set init[1:0]=0*/
-#define RTC_CNTL_SDIO_EN_INITI  (BIT(15))
-#define RTC_CNTL_SDIO_EN_INITI_M  (BIT(15))
-#define RTC_CNTL_SDIO_EN_INITI_V  0x1
-#define RTC_CNTL_SDIO_EN_INITI_S  15
-/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */
-/*description: add resistor from ldo output to ground. 0: no res*/
-#define RTC_CNTL_SDIO_INITI  0x00000003
-#define RTC_CNTL_SDIO_INITI_M  ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
-#define RTC_CNTL_SDIO_INITI_V  0x3
-#define RTC_CNTL_SDIO_INITI_S  13
-/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
-/*description: ability to prevent LDO from overshoot*/
-#define RTC_CNTL_SDIO_DCAP  0x00000003
-#define RTC_CNTL_SDIO_DCAP_M  ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S))
-#define RTC_CNTL_SDIO_DCAP_V  0x3
-#define RTC_CNTL_SDIO_DCAP_S  11
-/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */
-/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
-#define RTC_CNTL_SDIO_DTHDRV  0x00000003
-#define RTC_CNTL_SDIO_DTHDRV_M  ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S))
-#define RTC_CNTL_SDIO_DTHDRV_V  0x3
-#define RTC_CNTL_SDIO_DTHDRV_S  9
-/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
-/*description: timer count to apply reg_sdio_dcap after sdio power on*/
-#define RTC_CNTL_SDIO_TIMER_TARGET  0x000000FF
-#define RTC_CNTL_SDIO_TIMER_TARGET_M  ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S))
-#define RTC_CNTL_SDIO_TIMER_TARGET_V  0xFF
-#define RTC_CNTL_SDIO_TIMER_TARGET_S  0
-
-#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x007C)
-/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */
-/*description: DBG_ATTEN when rtc in monitor state*/
-#define RTC_CNTL_DBG_ATTEN_MONITOR  0x0000000F
-#define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
-#define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
-#define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
-/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */
-/*description: DBG_ATTEN when rtc in sleep state*/
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP  0x0000000F
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
-/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: bias_sleep when rtc in monitor state*/
-#define RTC_CNTL_BIAS_SLEEP_MONITOR  (BIT(17))
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
-/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: bias_sleep when rtc in sleep_state*/
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP  (BIT(16))
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
-/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: xpd cur when rtc in monitor state*/
-#define RTC_CNTL_PD_CUR_MONITOR  (BIT(15))
-#define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
-#define RTC_CNTL_PD_CUR_MONITOR_V  0x1
-#define RTC_CNTL_PD_CUR_MONITOR_S  15
-/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: xpd cur when rtc in sleep_state*/
-#define RTC_CNTL_PD_CUR_DEEP_SLP  (BIT(14))
-#define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
-#define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
-#define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
-/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BIAS_BUF_MONITOR  (BIT(13))
-#define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
-#define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
-#define RTC_CNTL_BIAS_BUF_MONITOR_S  13
-/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP  (BIT(12))
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
-/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: */
-#define RTC_CNTL_BIAS_BUF_WAKE  (BIT(11))
-#define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
-#define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
-#define RTC_CNTL_BIAS_BUF_WAKE_S  11
-/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BIAS_BUF_IDLE  (BIT(10))
-#define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
-#define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
-#define RTC_CNTL_BIAS_BUF_IDLE_S  10
-/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN  (BIT(8))
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M  (BIT(8))
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V  0x1
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S  8
-/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define RTC_CNTL_DG_VDD_DRV_B_SLP  0x000000FF
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_S  0
-
-#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x0080)
-/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_REGULATOR_FORCE_PU  (BIT(31))
-#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
-#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
-#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
-/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: RTC_REG force power down (for RTC_REG power down means decrease
- the voltage to 0.8v or lower )*/
-#define RTC_CNTL_REGULATOR_FORCE_PD  (BIT(30))
-#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
-#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
-#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
-/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
-/*description: RTC_DBOOST force power up*/
-#define RTC_CNTL_DBOOST_FORCE_PU  (BIT(29))
-#define RTC_CNTL_DBOOST_FORCE_PU_M  (BIT(29))
-#define RTC_CNTL_DBOOST_FORCE_PU_V  0x1
-#define RTC_CNTL_DBOOST_FORCE_PU_S  29
-/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: RTC_DBOOST force power down*/
-#define RTC_CNTL_DBOOST_FORCE_PD  (BIT(28))
-#define RTC_CNTL_DBOOST_FORCE_PD_M  (BIT(28))
-#define RTC_CNTL_DBOOST_FORCE_PD_V  0x1
-#define RTC_CNTL_DBOOST_FORCE_PD_S  28
-
-/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
-/*description: SCK_DCAP*/
-#define RTC_CNTL_SCK_DCAP  0x000000FF
-#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
-#define RTC_CNTL_SCK_DCAP_V  0xFF
-#define RTC_CNTL_SCK_DCAP_S  14
-#define RTC_CNTL_SCK_DCAP_DEFAULT   255
-/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_DIG_CAL_EN  (BIT(7))
-#define RTC_CNTL_DIG_CAL_EN_M  (BIT(7))
-#define RTC_CNTL_DIG_CAL_EN_V  0x1
-#define RTC_CNTL_DIG_CAL_EN_S  7
-
-#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x0084)
-/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: rtc pad force hold*/
-#define RTC_CNTL_PAD_FORCE_HOLD  (BIT(21))
-#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
-#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
-#define RTC_CNTL_PAD_FORCE_HOLD_S  21
-
-#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x0088)
-/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_DG_WRAP_PD_EN  (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
-#define RTC_CNTL_DG_WRAP_PD_EN_S  31
-/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: enable power down wifi in sleep*/
-#define RTC_CNTL_WIFI_PD_EN  (BIT(30))
-#define RTC_CNTL_WIFI_PD_EN_M  (BIT(30))
-#define RTC_CNTL_WIFI_PD_EN_V  0x1
-#define RTC_CNTL_WIFI_PD_EN_S  30
-/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_CPU_TOP_PD_EN  (BIT(29))
-#define RTC_CNTL_CPU_TOP_PD_EN_M  (BIT(29))
-#define RTC_CNTL_CPU_TOP_PD_EN_V  0x1
-#define RTC_CNTL_CPU_TOP_PD_EN_S  29
-/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_DG_PERI_PD_EN  (BIT(28))
-#define RTC_CNTL_DG_PERI_PD_EN_M  (BIT(28))
-#define RTC_CNTL_DG_PERI_PD_EN_V  0x1
-#define RTC_CNTL_DG_PERI_PD_EN_S  28
-/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BT_PD_EN  (BIT(27))
-#define RTC_CNTL_BT_PD_EN_M  (BIT(27))
-#define RTC_CNTL_BT_PD_EN_V  0x1
-#define RTC_CNTL_BT_PD_EN_S  27
-/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: */
-#define RTC_CNTL_CPU_TOP_FORCE_PU  (BIT(22))
-#define RTC_CNTL_CPU_TOP_FORCE_PU_M  (BIT(22))
-#define RTC_CNTL_CPU_TOP_FORCE_PU_V  0x1
-#define RTC_CNTL_CPU_TOP_FORCE_PU_S  22
-/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_CPU_TOP_FORCE_PD  (BIT(21))
-#define RTC_CNTL_CPU_TOP_FORCE_PD_M  (BIT(21))
-#define RTC_CNTL_CPU_TOP_FORCE_PD_V  0x1
-#define RTC_CNTL_CPU_TOP_FORCE_PD_S  21
-/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
-/*description: digital core force power up*/
-#define RTC_CNTL_DG_WRAP_FORCE_PU  (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
-/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: digital core force power down*/
-#define RTC_CNTL_DG_WRAP_FORCE_PD  (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
-/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
-/*description: wifi force power up*/
-#define RTC_CNTL_WIFI_FORCE_PU  (BIT(18))
-#define RTC_CNTL_WIFI_FORCE_PU_M  (BIT(18))
-#define RTC_CNTL_WIFI_FORCE_PU_V  0x1
-#define RTC_CNTL_WIFI_FORCE_PU_S  18
-/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: wifi force power down*/
-#define RTC_CNTL_WIFI_FORCE_PD  (BIT(17))
-#define RTC_CNTL_WIFI_FORCE_PD_M  (BIT(17))
-#define RTC_CNTL_WIFI_FORCE_PD_V  0x1
-#define RTC_CNTL_WIFI_FORCE_PD_S  17
-/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: */
-#define RTC_CNTL_FASTMEM_FORCE_LPU  (BIT(16))
-#define RTC_CNTL_FASTMEM_FORCE_LPU_M  (BIT(16))
-#define RTC_CNTL_FASTMEM_FORCE_LPU_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_LPU_S  16
-/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_FASTMEM_FORCE_LPD  (BIT(15))
-#define RTC_CNTL_FASTMEM_FORCE_LPD_M  (BIT(15))
-#define RTC_CNTL_FASTMEM_FORCE_LPD_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_LPD_S  15
-/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: */
-#define RTC_CNTL_DG_PERI_FORCE_PU  (BIT(14))
-#define RTC_CNTL_DG_PERI_FORCE_PU_M  (BIT(14))
-#define RTC_CNTL_DG_PERI_FORCE_PU_V  0x1
-#define RTC_CNTL_DG_PERI_FORCE_PU_S  14
-/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_DG_PERI_FORCE_PD  (BIT(13))
-#define RTC_CNTL_DG_PERI_FORCE_PD_M  (BIT(13))
-#define RTC_CNTL_DG_PERI_FORCE_PD_V  0x1
-#define RTC_CNTL_DG_PERI_FORCE_PD_S  13
-/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_BT_FORCE_PU  (BIT(12))
-#define RTC_CNTL_BT_FORCE_PU_M  (BIT(12))
-#define RTC_CNTL_BT_FORCE_PU_V  0x1
-#define RTC_CNTL_BT_FORCE_PU_S  12
-/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BT_FORCE_PD  (BIT(11))
-#define RTC_CNTL_BT_FORCE_PD_M  (BIT(11))
-#define RTC_CNTL_BT_FORCE_PD_V  0x1
-#define RTC_CNTL_BT_FORCE_PD_S  11
-/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: memories in digital core force no PD in sleep*/
-#define RTC_CNTL_LSLP_MEM_FORCE_PU  (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  4
-/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: memories in digital core force PD in sleep*/
-#define RTC_CNTL_LSLP_MEM_FORCE_PD  (BIT(3))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(3))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
-/* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_VDD_SPI_PWR_FORCE  (BIT(2))
-#define RTC_CNTL_VDD_SPI_PWR_FORCE_M  (BIT(2))
-#define RTC_CNTL_VDD_SPI_PWR_FORCE_V  0x1
-#define RTC_CNTL_VDD_SPI_PWR_FORCE_S  2
-/* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define RTC_CNTL_VDD_SPI_PWR_DRV  0x00000003
-#define RTC_CNTL_VDD_SPI_PWR_DRV_M  ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S))
-#define RTC_CNTL_VDD_SPI_PWR_DRV_V  0x3
-#define RTC_CNTL_VDD_SPI_PWR_DRV_S  0
-
-#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x008C)
-/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO  (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: digital core force ISO*/
-#define RTC_CNTL_DG_WRAP_FORCE_ISO  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
-/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
-/*description: wifi force no ISO*/
-#define RTC_CNTL_WIFI_FORCE_NOISO  (BIT(29))
-#define RTC_CNTL_WIFI_FORCE_NOISO_M  (BIT(29))
-#define RTC_CNTL_WIFI_FORCE_NOISO_V  0x1
-#define RTC_CNTL_WIFI_FORCE_NOISO_S  29
-/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: wifi force ISO*/
-#define RTC_CNTL_WIFI_FORCE_ISO  (BIT(28))
-#define RTC_CNTL_WIFI_FORCE_ISO_M  (BIT(28))
-#define RTC_CNTL_WIFI_FORCE_ISO_V  0x1
-#define RTC_CNTL_WIFI_FORCE_ISO_S  28
-/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: cpu force no ISO*/
-#define RTC_CNTL_CPU_TOP_FORCE_NOISO  (BIT(27))
-#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M  (BIT(27))
-#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V  0x1
-#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S  27
-/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: cpu force ISO*/
-#define RTC_CNTL_CPU_TOP_FORCE_ISO  (BIT(26))
-#define RTC_CNTL_CPU_TOP_FORCE_ISO_M  (BIT(26))
-#define RTC_CNTL_CPU_TOP_FORCE_ISO_V  0x1
-#define RTC_CNTL_CPU_TOP_FORCE_ISO_S  26
-/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_DG_PERI_FORCE_NOISO  (BIT(25))
-#define RTC_CNTL_DG_PERI_FORCE_NOISO_M  (BIT(25))
-#define RTC_CNTL_DG_PERI_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_PERI_FORCE_NOISO_S  25
-/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_DG_PERI_FORCE_ISO  (BIT(24))
-#define RTC_CNTL_DG_PERI_FORCE_ISO_M  (BIT(24))
-#define RTC_CNTL_DG_PERI_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_PERI_FORCE_ISO_S  24
-/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_BT_FORCE_NOISO  (BIT(23))
-#define RTC_CNTL_BT_FORCE_NOISO_M  (BIT(23))
-#define RTC_CNTL_BT_FORCE_NOISO_V  0x1
-#define RTC_CNTL_BT_FORCE_NOISO_S  23
-/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_BT_FORCE_ISO  (BIT(22))
-#define RTC_CNTL_BT_FORCE_ISO_M  (BIT(22))
-#define RTC_CNTL_BT_FORCE_ISO_V  0x1
-#define RTC_CNTL_BT_FORCE_ISO_S  22
-/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: digital pad force hold*/
-#define RTC_CNTL_DG_PAD_FORCE_HOLD  (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
-/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
-/*description: digital pad force un-hold*/
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD  (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
-/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: digital pad force ISO*/
-#define RTC_CNTL_DG_PAD_FORCE_ISO  (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
-/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
-/*description: digital pad force no ISO*/
-#define RTC_CNTL_DG_PAD_FORCE_NOISO  (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
-/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: digital pad enable auto-hold*/
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN  (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
-/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
-/*description: wtite only register to clear digital pad auto-hold*/
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD  (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
-/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: read only register to indicate digital pad auto-hold status*/
-#define RTC_CNTL_DG_PAD_AUTOHOLD  (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
-#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
-/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_DIG_ISO_FORCE_ON  (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
-#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
-/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */
-/*description: */
-#define RTC_CNTL_DIG_ISO_FORCE_OFF  (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
-
-#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x0090)
-/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define RTC_CNTL_WDT_EN  (BIT(31))
-#define RTC_CNTL_WDT_EN_M  (BIT(31))
-#define RTC_CNTL_WDT_EN_V  0x1
-#define RTC_CNTL_WDT_EN_S  31
-/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en*/
-#define RTC_CNTL_WDT_STG0  0x00000007
-#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
-#define RTC_CNTL_WDT_STG0_V  0x7
-#define RTC_CNTL_WDT_STG0_S  28
-/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en*/
-#define RTC_CNTL_WDT_STG1  0x00000007
-#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
-#define RTC_CNTL_WDT_STG1_V  0x7
-#define RTC_CNTL_WDT_STG1_S  25
-/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en*/
-#define RTC_CNTL_WDT_STG2  0x00000007
-#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
-#define RTC_CNTL_WDT_STG2_V  0x7
-#define RTC_CNTL_WDT_STG2_S  22
-/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en*/
-#define RTC_CNTL_WDT_STG3  0x00000007
-#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
-#define RTC_CNTL_WDT_STG3_V  0x7
-#define RTC_CNTL_WDT_STG3_S  19
-/* RTC_CNTL_WDT_STGX : */
-/*description: stage action selection values */
-#define RTC_WDT_STG_SEL_OFF             0
-#define RTC_WDT_STG_SEL_INT             1
-#define RTC_WDT_STG_SEL_RESET_CPU       2
-#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
-#define RTC_WDT_STG_SEL_RESET_RTC       4
-
-/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
-/*description: CPU reset counter length*/
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH  0x00000007
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
-/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
-/*description: system reset counter length*/
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH  0x00000007
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
-/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: enable WDT in flash boot*/
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN  (BIT(12))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
-/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: enable WDT reset PRO CPU*/
-#define RTC_CNTL_WDT_PROCPU_RESET_EN  (BIT(11))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
-/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: enable WDT reset APP CPU*/
-#define RTC_CNTL_WDT_APPCPU_RESET_EN  (BIT(10))
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_M  (BIT(10))
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_S  10
-/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */
-/*description: pause WDT in sleep*/
-#define RTC_CNTL_WDT_PAUSE_IN_SLP  (BIT(9))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
-/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: wdt reset whole chip enable*/
-#define RTC_CNTL_WDT_CHIP_RESET_EN  (BIT(8))
-#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
-#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
-/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */
-/*description: chip reset siginal pulse width*/
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH  0x000000FF
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
-
-#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x0094)
-/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
-/*description: */
-#define RTC_CNTL_WDT_STG0_HOLD  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
-#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x0098)
-/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
-/*description: */
-#define RTC_CNTL_WDT_STG1_HOLD  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
-#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x009C)
-/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: */
-#define RTC_CNTL_WDT_STG2_HOLD  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
-#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x00A0)
-/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: */
-#define RTC_CNTL_WDT_STG3_HOLD  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
-#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_S  0
-
-#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0x00A4)
-/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_WDT_FEED  (BIT(31))
-#define RTC_CNTL_WDT_FEED_M  (BIT(31))
-#define RTC_CNTL_WDT_FEED_V  0x1
-#define RTC_CNTL_WDT_FEED_S  31
-
-#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x00A8)
-/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
-/*description: */
-#define RTC_CNTL_WDT_WKEY  0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
-#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_S  0
-
-#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00AC)
-/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: automatically feed swd when int comes*/
-#define RTC_CNTL_SWD_AUTO_FEED_EN  (BIT(31))
-#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
-#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
-#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
-/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: disabel SWD*/
-#define RTC_CNTL_SWD_DISABLE  (BIT(30))
-#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
-#define RTC_CNTL_SWD_DISABLE_V  0x1
-#define RTC_CNTL_SWD_DISABLE_S  30
-/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Sw feed swd*/
-#define RTC_CNTL_SWD_FEED  (BIT(29))
-#define RTC_CNTL_SWD_FEED_M  (BIT(29))
-#define RTC_CNTL_SWD_FEED_V  0x1
-#define RTC_CNTL_SWD_FEED_S  29
-/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: reset swd reset flag*/
-#define RTC_CNTL_SWD_RST_FLAG_CLR  (BIT(28))
-#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
-#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
-#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
-/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
-/*description: adjust signal width send to swd*/
-#define RTC_CNTL_SWD_SIGNAL_WIDTH  0x000003FF
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
-/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_SWD_BYPASS_RST  (BIT(17))
-#define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
-#define RTC_CNTL_SWD_BYPASS_RST_V  0x1
-#define RTC_CNTL_SWD_BYPASS_RST_S  17
-/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: swd interrupt for feeding*/
-#define RTC_CNTL_SWD_FEED_INT  (BIT(1))
-#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
-#define RTC_CNTL_SWD_FEED_INT_V  0x1
-#define RTC_CNTL_SWD_FEED_INT_S  1
-/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: swd reset flag*/
-#define RTC_CNTL_SWD_RESET_FLAG  (BIT(0))
-#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
-#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
-#define RTC_CNTL_SWD_RESET_FLAG_S  0
-
-#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x00B0)
-/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
-/*description: */
-#define RTC_CNTL_SWD_WKEY  0xFFFFFFFF
-#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
-#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
-#define RTC_CNTL_SWD_WKEY_S  0
-
-#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0x00B4)
-/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
-/*description: */
-#define RTC_CNTL_SW_STALL_PROCPU_C1  0x0000003F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
-#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
-/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
-/*description: {reg_sw_stall_appcpu_c1[5:0]*/
-#define RTC_CNTL_SW_STALL_APPCPU_C1  0x0000003F
-#define RTC_CNTL_SW_STALL_APPCPU_C1_M  ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
-#define RTC_CNTL_SW_STALL_APPCPU_C1_V  0x3F
-#define RTC_CNTL_SW_STALL_APPCPU_C1_S  20
-
-#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0x00B8)
-/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_SCRATCH4  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
-#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH4_S  0
-
-#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0x00BC)
-/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_SCRATCH5  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
-#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH5_S  0
-
-#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0x00C0)
-/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_SCRATCH6  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
-#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH6_S  0
-
-#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0x00C4)
-/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_SCRATCH7  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
-#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH7_S  0
-
-#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0x00C8)
-/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */
-/*description: rtc main state machine status*/
-#define RTC_CNTL_MAIN_STATE  0x0000000F
-#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
-#define RTC_CNTL_MAIN_STATE_V  0xF
-#define RTC_CNTL_MAIN_STATE_S  28
-/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: rtc main state machine is in idle state*/
-#define RTC_CNTL_MAIN_STATE_IN_IDLE  (BIT(27))
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
-/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: rtc main state machine is in sleep state*/
-#define RTC_CNTL_MAIN_STATE_IN_SLP  (BIT(26))
-#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
-#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait xtal state*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL  (BIT(25))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait pll state*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL  (BIT(24))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait 8m state*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M  (BIT(23))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
-/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: rtc main state machine is in the states of low power*/
-#define RTC_CNTL_IN_LOW_POWER_STATE  (BIT(22))
-#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
-#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
-#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
-/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: rtc main state machine is in the states of wakeup process*/
-#define RTC_CNTL_IN_WAKEUP_STATE  (BIT(21))
-#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
-#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
-#define RTC_CNTL_IN_WAKEUP_STATE_S  21
-/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: rtc main state machine has been waited for some cycles*/
-#define RTC_CNTL_MAIN_STATE_WAIT_END  (BIT(20))
-#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
-#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
-#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
-/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: rtc is ready to receive wake up trigger from wake up source*/
-#define RTC_CNTL_RDY_FOR_WAKEUP  (BIT(19))
-#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
-#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
-#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
-/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: rtc main state machine is in states that pll should be running*/
-#define RTC_CNTL_MAIN_STATE_PLL_ON  (BIT(18))
-#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
-#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
-#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
-/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: no use any more*/
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO  (BIT(17))
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
-/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: ulp/cocpu is done*/
-#define RTC_CNTL_COCPU_STATE_DONE  (BIT(16))
-#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
-#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
-#define RTC_CNTL_COCPU_STATE_DONE_S  16
-/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: ulp/cocpu is in sleep state*/
-#define RTC_CNTL_COCPU_STATE_SLP  (BIT(15))
-#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
-#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
-#define RTC_CNTL_COCPU_STATE_SLP_S  15
-/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: ulp/cocpu is about to working. Switch rtc main state*/
-#define RTC_CNTL_COCPU_STATE_SWITCH  (BIT(14))
-#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
-#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
-#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
-/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: ulp/cocpu should start to work*/
-#define RTC_CNTL_COCPU_STATE_START  (BIT(13))
-#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
-#define RTC_CNTL_COCPU_STATE_START_V  0x1
-#define RTC_CNTL_COCPU_STATE_START_S  13
-/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: touch is done*/
-#define RTC_CNTL_TOUCH_STATE_DONE  (BIT(12))
-#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
-#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
-#define RTC_CNTL_TOUCH_STATE_DONE_S  12
-/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: touch is in sleep state*/
-#define RTC_CNTL_TOUCH_STATE_SLP  (BIT(11))
-#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
-#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
-#define RTC_CNTL_TOUCH_STATE_SLP_S  11
-/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: touch is about to working. Switch rtc main state*/
-#define RTC_CNTL_TOUCH_STATE_SWITCH  (BIT(10))
-#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
-#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
-#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
-/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: touch should start to work*/
-#define RTC_CNTL_TOUCH_STATE_START  (BIT(9))
-#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
-#define RTC_CNTL_TOUCH_STATE_START_V  0x1
-#define RTC_CNTL_TOUCH_STATE_START_S  9
-/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: digital wrap power down*/
-#define RTC_CNTL_XPD_DIG  (BIT(8))
-#define RTC_CNTL_XPD_DIG_M  (BIT(8))
-#define RTC_CNTL_XPD_DIG_V  0x1
-#define RTC_CNTL_XPD_DIG_S  8
-/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: digital wrap iso*/
-#define RTC_CNTL_DIG_ISO  (BIT(7))
-#define RTC_CNTL_DIG_ISO_M  (BIT(7))
-#define RTC_CNTL_DIG_ISO_V  0x1
-#define RTC_CNTL_DIG_ISO_S  7
-/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: wifi wrap power down*/
-#define RTC_CNTL_XPD_WIFI  (BIT(6))
-#define RTC_CNTL_XPD_WIFI_M  (BIT(6))
-#define RTC_CNTL_XPD_WIFI_V  0x1
-#define RTC_CNTL_XPD_WIFI_S  6
-/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: wifi iso*/
-#define RTC_CNTL_WIFI_ISO  (BIT(5))
-#define RTC_CNTL_WIFI_ISO_M  (BIT(5))
-#define RTC_CNTL_WIFI_ISO_V  0x1
-#define RTC_CNTL_WIFI_ISO_S  5
-/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: rtc peripheral power down*/
-#define RTC_CNTL_XPD_RTC_PERI  (BIT(4))
-#define RTC_CNTL_XPD_RTC_PERI_M  (BIT(4))
-#define RTC_CNTL_XPD_RTC_PERI_V  0x1
-#define RTC_CNTL_XPD_RTC_PERI_S  4
-/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: rtc peripheral iso*/
-#define RTC_CNTL_PERI_ISO  (BIT(3))
-#define RTC_CNTL_PERI_ISO_M  (BIT(3))
-#define RTC_CNTL_PERI_ISO_V  0x1
-#define RTC_CNTL_PERI_ISO_S  3
-/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: External DCDC power down*/
-#define RTC_CNTL_XPD_DIG_DCDC  (BIT(2))
-#define RTC_CNTL_XPD_DIG_DCDC_M  (BIT(2))
-#define RTC_CNTL_XPD_DIG_DCDC_V  0x1
-#define RTC_CNTL_XPD_DIG_DCDC_S  2
-/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: rom0 power down*/
-#define RTC_CNTL_XPD_ROM0  (BIT(0))
-#define RTC_CNTL_XPD_ROM0_M  (BIT(0))
-#define RTC_CNTL_XPD_ROM0_V  0x1
-#define RTC_CNTL_XPD_ROM0_S  0
-
-#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0x00CC)
-/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
-/*description: */
-#define RTC_CNTL_LOW_POWER_DIAG1  0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
-#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG1_S  0
-
-#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0x00D0)
-/* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN5_HOLD  (BIT(5))
-#define RTC_CNTL_GPIO_PIN5_HOLD_M  (BIT(5))
-#define RTC_CNTL_GPIO_PIN5_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN5_HOLD_S  5
-/* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN4_HOLD  (BIT(4))
-#define RTC_CNTL_GPIO_PIN4_HOLD_M  (BIT(4))
-#define RTC_CNTL_GPIO_PIN4_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN4_HOLD_S  4
-/* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN3_HOLD  (BIT(3))
-#define RTC_CNTL_GPIO_PIN3_HOLD_M  (BIT(3))
-#define RTC_CNTL_GPIO_PIN3_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN3_HOLD_S  3
-/* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN2_HOLD  (BIT(2))
-#define RTC_CNTL_GPIO_PIN2_HOLD_M  (BIT(2))
-#define RTC_CNTL_GPIO_PIN2_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN2_HOLD_S  2
-/* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN1_HOLD  (BIT(1))
-#define RTC_CNTL_GPIO_PIN1_HOLD_M  (BIT(1))
-#define RTC_CNTL_GPIO_PIN1_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN1_HOLD_S  1
-/* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN0_HOLD  (BIT(0))
-#define RTC_CNTL_GPIO_PIN0_HOLD_M  (BIT(0))
-#define RTC_CNTL_GPIO_PIN0_HOLD_V  0x1
-#define RTC_CNTL_GPIO_PIN0_HOLD_S  0
-
-#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0x00D4)
-/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define RTC_CNTL_DIG_PAD_HOLD  0xFFFFFFFF
-#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
-#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_DIG_PAD_HOLD_S  0
-
-#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0x00D8)
-/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BROWN_OUT_DET  (BIT(31))
-#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
-#define RTC_CNTL_BROWN_OUT_DET_V  0x1
-#define RTC_CNTL_BROWN_OUT_DET_S  31
-/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: enable brown out*/
-#define RTC_CNTL_BROWN_OUT_ENA  (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_ENA_S  30
-/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: clear brown out counter*/
-#define RTC_CNTL_BROWN_OUT_CNT_CLR  (BIT(29))
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
-/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN  (BIT(28))
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
-/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: 1:  4-pos reset*/
-#define RTC_CNTL_BROWN_OUT_RST_SEL  (BIT(27))
-#define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
-#define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
-#define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
-/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: enable brown out reset*/
-#define RTC_CNTL_BROWN_OUT_RST_ENA  (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
-/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
-/*description: brown out reset wait cycles*/
-#define RTC_CNTL_BROWN_OUT_RST_WAIT  0x000003FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
-/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable power down RF when brown out happens*/
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA  (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
-/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: enable close flash when brown out happens*/
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA  (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
-/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */
-/*description: brown out interrupt wait cycles*/
-#define RTC_CNTL_BROWN_OUT_INT_WAIT  0x000003FF
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
-
-#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0x00DC)
-/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: RTC timer low 32 bits*/
-#define RTC_CNTL_TIMER_VALUE1_LOW  0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
-#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
-
-#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0x00E0)
-/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC timer high 16 bits*/
-#define RTC_CNTL_TIMER_VALUE1_HIGH  0x0000FFFF
-#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
-#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
-#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
-
-#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG          (DR_REG_RTCCNTL_BASE + 0x00E4)
-/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: xtal 32k watch dog backup clock factor*/
-#define RTC_CNTL_XTAL32K_CLK_FACTOR  0xFFFFFFFF
-#define RTC_CNTL_XTAL32K_CLK_FACTOR_M  ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S))
-#define RTC_CNTL_XTAL32K_CLK_FACTOR_V  0xFFFFFFFF
-#define RTC_CNTL_XTAL32K_CLK_FACTOR_S  0
-
-#define RTC_CNTL_XTAL32K_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00E8)
-/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: if restarted xtal32k period is smaller than this*/
-#define RTC_CNTL_XTAL32K_STABLE_THRES  0x0000000F
-#define RTC_CNTL_XTAL32K_STABLE_THRES_M  ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S))
-#define RTC_CNTL_XTAL32K_STABLE_THRES_V  0xF
-#define RTC_CNTL_XTAL32K_STABLE_THRES_S  28
-/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
-/*description: If no clock detected for this amount of time*/
-#define RTC_CNTL_XTAL32K_WDT_TIMEOUT  0x000000FF
-#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M  ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S))
-#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V  0xFF
-#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S  20
-/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
-/*description: cycles to wait to repower on xtal 32k*/
-#define RTC_CNTL_XTAL32K_RESTART_WAIT  0x0000FFFF
-#define RTC_CNTL_XTAL32K_RESTART_WAIT_M  ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S))
-#define RTC_CNTL_XTAL32K_RESTART_WAIT_V  0xFFFF
-#define RTC_CNTL_XTAL32K_RESTART_WAIT_S  4
-/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: cycles to wait to return noral xtal 32k*/
-#define RTC_CNTL_XTAL32K_RETURN_WAIT  0x0000000F
-#define RTC_CNTL_XTAL32K_RETURN_WAIT_M  ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S))
-#define RTC_CNTL_XTAL32K_RETURN_WAIT_V  0xF
-#define RTC_CNTL_XTAL32K_RETURN_WAIT_S  0
-
-#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00EC)
-/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_IO_MUX_RESET_DISABLE  (BIT(18))
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
-
-#define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x00F0)
-/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: sleep reject cause*/
-#define RTC_CNTL_REJECT_CAUSE  0x0003FFFF
-#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
-#define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
-#define RTC_CNTL_REJECT_CAUSE_S  0
-
-#define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0x00F4)
-/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT  (BIT(0))
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
-
-#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x00F8)
-/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */
-/*description: sleep wakeup cause*/
-#define RTC_CNTL_WAKEUP_CAUSE  0x0001FFFF
-#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
-#define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
-#define RTC_CNTL_WAKEUP_CAUSE_S  0
-
-#define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0x00FC)
-/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */
-/*description: sleep cycles for ULP-coprocessor timer*/
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE  0x00FFFFFF
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
-
-#define RTC_CNTL_INT_ENA_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0x0100)
-/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S  20
-/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: enbale gitch det interrupt*/
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S  19
-/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: enable xtal32k_dead  interrupt*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S  16
-/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt*/
-#define RTC_CNTL_SWD_INT_ENA_W1TS  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
-/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt*/
-#define RTC_CNTL_WDT_INT_ENA_W1TS  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
-/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
-
-#define RTC_CNTL_INT_ENA_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0x0104)
-/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M  (BIT(20))
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S  20
-/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: enbale gitch det interrupt*/
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S  19
-/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: enable xtal32k_dead  interrupt*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S  16
-/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt*/
-#define RTC_CNTL_SWD_INT_ENA_W1TC  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
-/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
-/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt*/
-#define RTC_CNTL_WDT_INT_ENA_W1TC  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
-/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
-
-#define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0108)
-/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */
-/*description: wait cycles for rention operation*/
-#define RTC_CNTL_RETENTION_WAIT  0x0000001F
-#define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
-#define RTC_CNTL_RETENTION_WAIT_V  0x1F
-#define RTC_CNTL_RETENTION_WAIT_S  27
-/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: */
-#define RTC_CNTL_RETENTION_EN  (BIT(26))
-#define RTC_CNTL_RETENTION_EN_M  (BIT(26))
-#define RTC_CNTL_RETENTION_EN_V  0x1
-#define RTC_CNTL_RETENTION_EN_S  26
-/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */
-/*description: */
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT  0x0000000F
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  22
-/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */
-/*description: */
-#define RTC_CNTL_RETENTION_DONE_WAIT  0x00000007
-#define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
-#define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
-#define RTC_CNTL_RETENTION_DONE_WAIT_S  19
-/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_RETENTION_CLK_SEL  (BIT(18))
-#define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(18))
-#define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
-#define RTC_CNTL_RETENTION_CLK_SEL_S  18
-
-#define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x010C)
-/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: select use analog fib signal*/
-#define RTC_CNTL_FIB_SEL  0x00000007
-#define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
-#define RTC_CNTL_FIB_SEL_V  0x7
-#define RTC_CNTL_FIB_SEL_S  0
-
-#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
-#define RTC_CNTL_FIB_BOD_RST BIT(1)
-#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
-
-#define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0x0110)
-/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE  (BIT(31))
-#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(31))
-#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S  31
-/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE  (BIT(30))
-#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(30))
-#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S  30
-/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE  (BIT(29))
-#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(29))
-#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S  29
-/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE  (BIT(28))
-#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(28))
-#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S  28
-/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE  (BIT(27))
-#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(27))
-#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S  27
-/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE  (BIT(26))
-#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(26))
-#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
-#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S  26
-/* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN0_INT_TYPE  0x00000007
-#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S  23
-/* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN1_INT_TYPE  0x00000007
-#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S  20
-/* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN2_INT_TYPE  0x00000007
-#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S  17
-/* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN3_INT_TYPE  0x00000007
-#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S  14
-/* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN4_INT_TYPE  0x00000007
-#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S  11
-/* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN5_INT_TYPE  0x00000007
-#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S))
-#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V  0x7
-#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S  8
-/* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN_CLK_GATE  (BIT(7))
-#define RTC_CNTL_GPIO_PIN_CLK_GATE_M  (BIT(7))
-#define RTC_CNTL_GPIO_PIN_CLK_GATE_V  0x1
-#define RTC_CNTL_GPIO_PIN_CLK_GATE_S  7
-/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR  (BIT(6))
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M  (BIT(6))
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V  0x1
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S  6
-/* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_WAKEUP_STATUS  0x0000003F
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_M  ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S))
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_V  0x3F
-#define RTC_CNTL_GPIO_WAKEUP_STATUS_S  0
-
-#define RTC_CNTL_DBG_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x0114)
-/* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
-/*description: */
-#define RTC_CNTL_DEBUG_SEL4  0x0000001F
-#define RTC_CNTL_DEBUG_SEL4_M  ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S))
-#define RTC_CNTL_DEBUG_SEL4_V  0x1F
-#define RTC_CNTL_DEBUG_SEL4_S  27
-/* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */
-/*description: */
-#define RTC_CNTL_DEBUG_SEL3  0x0000001F
-#define RTC_CNTL_DEBUG_SEL3_M  ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S))
-#define RTC_CNTL_DEBUG_SEL3_V  0x1F
-#define RTC_CNTL_DEBUG_SEL3_S  22
-/* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */
-/*description: */
-#define RTC_CNTL_DEBUG_SEL2  0x0000001F
-#define RTC_CNTL_DEBUG_SEL2_M  ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S))
-#define RTC_CNTL_DEBUG_SEL2_V  0x1F
-#define RTC_CNTL_DEBUG_SEL2_S  17
-/* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */
-/*description: */
-#define RTC_CNTL_DEBUG_SEL1  0x0000001F
-#define RTC_CNTL_DEBUG_SEL1_M  ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S))
-#define RTC_CNTL_DEBUG_SEL1_V  0x1F
-#define RTC_CNTL_DEBUG_SEL1_S  12
-/* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */
-/*description: */
-#define RTC_CNTL_DEBUG_SEL0  0x0000001F
-#define RTC_CNTL_DEBUG_SEL0_M  ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S))
-#define RTC_CNTL_DEBUG_SEL0_V  0x1F
-#define RTC_CNTL_DEBUG_SEL0_S  7
-/* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */
-/*description: */
-#define RTC_CNTL_DEBUG_BIT_SEL  0x0000001F
-#define RTC_CNTL_DEBUG_BIT_SEL_M  ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S))
-#define RTC_CNTL_DEBUG_BIT_SEL_V  0x1F
-#define RTC_CNTL_DEBUG_BIT_SEL_S  2
-/* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_DEBUG_12M_NO_GATING  (BIT(1))
-#define RTC_CNTL_DEBUG_12M_NO_GATING_M  (BIT(1))
-#define RTC_CNTL_DEBUG_12M_NO_GATING_V  0x1
-#define RTC_CNTL_DEBUG_12M_NO_GATING_S  1
-
-#define RTC_CNTL_DBG_MAP_REG          (DR_REG_RTCCNTL_BASE + 0x0118)
-/* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN0_FUN_SEL  0x0000000F
-#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S  28
-/* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN1_FUN_SEL  0x0000000F
-#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S  24
-/* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN2_FUN_SEL  0x0000000F
-#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S  20
-/* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN3_FUN_SEL  0x0000000F
-#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S  16
-/* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN4_FUN_SEL  0x0000000F
-#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S  12
-/* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN5_FUN_SEL  0x0000000F
-#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S))
-#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V  0xF
-#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S  8
-/* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN0_MUX_SEL  (BIT(7))
-#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M  (BIT(7))
-#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S  7
-/* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN1_MUX_SEL  (BIT(6))
-#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M  (BIT(6))
-#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S  6
-/* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN2_MUX_SEL  (BIT(5))
-#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M  (BIT(5))
-#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S  5
-/* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN3_MUX_SEL  (BIT(4))
-#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M  (BIT(4))
-#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S  4
-/* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN4_MUX_SEL  (BIT(3))
-#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M  (BIT(3))
-#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S  3
-/* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_GPIO_PIN5_MUX_SEL  (BIT(2))
-#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M  (BIT(2))
-#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V  0x1
-#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S  2
-
-#define RTC_CNTL_SENSOR_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x011C)
-/* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */
-/*description: */
-#define RTC_CNTL_FORCE_XPD_SAR  0x00000003
-#define RTC_CNTL_FORCE_XPD_SAR_M  ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S))
-#define RTC_CNTL_FORCE_XPD_SAR_V  0x3
-#define RTC_CNTL_FORCE_XPD_SAR_S  30
-/* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */
-/*description: */
-#define RTC_CNTL_SAR2_PWDET_CCT  0x00000007
-#define RTC_CNTL_SAR2_PWDET_CCT_M  ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S))
-#define RTC_CNTL_SAR2_PWDET_CCT_V  0x7
-#define RTC_CNTL_SAR2_PWDET_CCT_S  27
-
-#define RTC_CNTL_DBG_SAR_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x0120)
-/* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
-/*description: */
-#define RTC_CNTL_SAR_DEBUG_SEL  0x0000001F
-#define RTC_CNTL_SAR_DEBUG_SEL_M  ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S))
-#define RTC_CNTL_SAR_DEBUG_SEL_V  0x1F
-#define RTC_CNTL_SAR_DEBUG_SEL_S  27
-
-#define RTC_CNTL_PG_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0124)
-/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_POWER_GLITCH_EN  (BIT(31))
-#define RTC_CNTL_POWER_GLITCH_EN_M  (BIT(31))
-#define RTC_CNTL_POWER_GLITCH_EN_V  0x1
-#define RTC_CNTL_POWER_GLITCH_EN_S  31
-/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL  (BIT(30))
-#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M  (BIT(30))
-#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V  0x1
-#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S  30
-/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_POWER_GLITCH_FORCE_PU  (BIT(29))
-#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M  (BIT(29))
-#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V  0x1
-#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S  29
-/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_POWER_GLITCH_FORCE_PD  (BIT(28))
-#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M  (BIT(28))
-#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V  0x1
-#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S  28
-/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */
-/*description: */
-#define RTC_CNTL_POWER_GLITCH_DSENSE  0x00000003
-#define RTC_CNTL_POWER_GLITCH_DSENSE_M  ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S))
-#define RTC_CNTL_POWER_GLITCH_DSENSE_V  0x3
-#define RTC_CNTL_POWER_GLITCH_DSENSE_S  26
-
-#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x01fc)
-/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */
-/*description: */
-#define RTC_CNTL_CNTL_DATE  0x0FFFFFFF
-#define RTC_CNTL_CNTL_DATE_M  ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S))
-#define RTC_CNTL_CNTL_DATE_V  0xFFFFFFF
-#define RTC_CNTL_CNTL_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_RTC_CNTL_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h b/components/soc/esp32c3/include/soc/rtc_cntl_struct.h
deleted file mode 100644
index 8b6bd3ad509..00000000000
--- a/components/soc/esp32c3/include/soc/rtc_cntl_struct.h
+++ /dev/null
@@ -1,834 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct rtc_cntl_dev_s {
-    union {
-        struct {
-            uint32_t sw_stall_appcpu_c0:  2;               /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
-            uint32_t sw_stall_procpu_c0:  2;               /*{reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
-            uint32_t sw_appcpu_rst:       1;               /*APP CPU SW reset*/
-            uint32_t sw_procpu_rst:       1;               /*PRO CPU SW reset*/
-            uint32_t bb_i2c_force_pd:     1;               /*BB_I2C force power down*/
-            uint32_t bb_i2c_force_pu:     1;               /*BB_I2C force power up*/
-            uint32_t bbpll_i2c_force_pd:  1;               /*BB_PLL _I2C force power down*/
-            uint32_t bbpll_i2c_force_pu:  1;               /*BB_PLL_I2C force power up*/
-            uint32_t bbpll_force_pd:      1;               /*BB_PLL force power down*/
-            uint32_t bbpll_force_pu:      1;               /*BB_PLL force power up*/
-            uint32_t xtl_force_pd:        1;               /*crystall force power down*/
-            uint32_t xtl_force_pu:        1;               /*crystall force power up*/
-            uint32_t xtl_en_wait:         4;               /*wait bias_sleep and current source wakeup*/
-            uint32_t reserved18:          2;
-            uint32_t ctr_sel:             3;
-            uint32_t xtl_force_iso:       1;
-            uint32_t pll_force_iso:       1;
-            uint32_t analog_force_iso:    1;
-            uint32_t xtl_force_noiso:     1;
-            uint32_t pll_force_noiso:     1;
-            uint32_t analog_force_noiso:  1;
-            uint32_t dg_wrap_force_rst:   1;               /*digital wrap force reset in deep sleep*/
-            uint32_t dg_wrap_force_norst: 1;               /*digital core force no reset in deep sleep*/
-            uint32_t sw_sys_rst:          1;               /*SW system reset*/
-        };
-        uint32_t val;
-    } options0;
-    uint32_t slp_timer0;                               /**/
-    union {
-        struct {
-            uint32_t slp_val_hi:             16;           /*RTC sleep timer high 16 bits*/
-            uint32_t main_timer_alarm_en:     1;           /*timer alarm enable bit*/
-            uint32_t reserved17:             15;
-        };
-        uint32_t val;
-    } slp_timer1;
-    union {
-        struct {
-            uint32_t reserved0:      27;
-            uint32_t timer_sys_stall: 1;                   /*Enable to record system stall time*/
-            uint32_t timer_xtl_off:   1;                   /*Enable to record 40M XTAL OFF time*/
-            uint32_t timer_sys_rst:   1;                   /*enable to record system reset time*/
-            uint32_t reserved30:      1;
-            uint32_t update:          1;                   /*Set 1: to update register with RTC timer*/
-        };
-        uint32_t val;
-    } time_update;
-    uint32_t time_low0;                                /*RTC timer low 32 bits*/
-    union {
-        struct {
-            uint32_t rtc_timer_value0_high:16;             /*RTC timer high 16 bits*/
-            uint32_t reserved16:           16;
-        };
-        uint32_t val;
-    } time_high0;
-    union {
-        struct {
-            uint32_t rtc_sw_cpu_int:           1;          /*rtc software interrupt to main cpu*/
-            uint32_t rtc_slp_reject_cause_clr: 1;          /*clear rtc sleep reject cause*/
-            uint32_t reserved2:               20;
-            uint32_t apb2rtc_bridge_sel:       1;          /*1: APB to RTC using bridge*/
-            uint32_t reserved23:               5;
-            uint32_t sdio_active_ind:          1;          /*SDIO active indication*/
-            uint32_t slp_wakeup:               1;          /*leep wakeup bit*/
-            uint32_t slp_reject:               1;          /*leep reject bit*/
-            uint32_t sleep_en:                 1;          /*sleep enable bit*/
-        };
-        uint32_t val;
-    } state0;
-    union {
-        struct {
-            uint32_t cpu_stall_en:   1;                    /*CPU stall enable bit*/
-            uint32_t cpu_stall_wait: 5;                    /*CPU stall wait cycles in fast_clk_rtc*/
-            uint32_t ck8m_wait:      8;                    /*CK8M wait cycles in slow_clk_rtc*/
-            uint32_t xtl_buf_wait:  10;                    /*XTAL wait cycles in slow_clk_rtc*/
-            uint32_t pll_buf_wait:   8;                    /*PLL wait cycles in slow_clk_rtc*/
-        };
-        uint32_t val;
-    } timer1;
-    union {
-        struct {
-            uint32_t reserved0:        24;
-            uint32_t min_time_ck8m_off: 8;                 /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
-        };
-        uint32_t val;
-    } timer2;
-    union {
-        struct {
-            uint32_t wifi_wait_timer:    9;
-            uint32_t wifi_powerup_timer: 7;
-            uint32_t bt_wait_timer:      9;
-            uint32_t bt_powerup_timer:   7;
-        };
-        uint32_t val;
-    } timer3;
-    union {
-        struct {
-            uint32_t cpu_top_wait_timer:    9;
-            uint32_t cpu_top_powerup_timer: 7;
-            uint32_t dg_wrap_wait_timer:    9;
-            uint32_t dg_wrap_powerup_timer: 7;
-        };
-        uint32_t val;
-    } timer4;
-    union {
-        struct {
-            uint32_t reserved0:   8;
-            uint32_t min_slp_val: 8;                       /*minimal sleep cycles in slow_clk_rtc*/
-            uint32_t reserved16: 16;
-        };
-        uint32_t val;
-    } timer5;
-    union {
-        struct {
-            uint32_t reserved0:            16;
-            uint32_t dg_peri_wait_timer:    9;
-            uint32_t dg_peri_powerup_timer: 7;
-        };
-        uint32_t val;
-    } timer6;
-    union {
-        struct {
-            uint32_t reserved0:             18;
-            uint32_t i2c_reset_por_force_pd: 1;
-            uint32_t i2c_reset_por_force_pu: 1;
-            uint32_t glitch_rst_en:          1;
-            uint32_t reserved21:             1;            /*PLLA force power down*/
-            uint32_t sar_i2c_pu:             1;            /*PLLA force power up*/
-            uint32_t plla_force_pd:          1;            /*PLLA force power down*/
-            uint32_t plla_force_pu:          1;            /*PLLA force power up*/
-            uint32_t bbpll_cal_slp_start:    1;            /*start BBPLL calibration during sleep*/
-            uint32_t pvtmon_pu:              1;            /*1: PVTMON power up*/
-            uint32_t txrf_i2c_pu:            1;            /*1: TXRF_I2C power up*/
-            uint32_t rfrx_pbus_pu:           1;            /*1: RFRX_PBUS power up*/
-            uint32_t reserved29:             1;
-            uint32_t ckgen_i2c_pu:           1;            /*1: CKGEN_I2C power up*/
-            uint32_t pll_i2c_pu:             1;
-        };
-        uint32_t val;
-    } ana_conf;
-    union {
-        struct {
-            uint32_t reset_cause_procpu:         6;        /*reset cause of PRO CPU*/
-            uint32_t reset_cause_appcpu:         6;        /*reset cause of APP CPU*/
-            uint32_t stat_vector_sel_appcpu:     1;        /*APP CPU state vector sel*/
-            uint32_t stat_vector_sel_procpu:     1;        /*PRO CPU state vector sel*/
-            uint32_t all_reset_flag_procpu:      1;        /*PRO CPU reset_flag*/
-            uint32_t all_reset_flag_appcpu:      1;        /*APP CPU reset flag*/
-            uint32_t all_reset_flag_clr_procpu:  1;        /*clear PRO CPU reset_flag*/
-            uint32_t all_reset_flag_clr_appcpu:  1;        /*clear APP CPU reset flag*/
-            uint32_t ocd_halt_on_reset_appcpu:   1;        /*APPCPU OcdHaltOnReset*/
-            uint32_t ocd_halt_on_reset_procpu:   1;        /*PROCPU OcdHaltOnReset*/
-            uint32_t jtag_reset_flag_procpu:     1;
-            uint32_t jtag_reset_flag_appcpu:     1;
-            uint32_t jtag_reset_flag_clr_procpu: 1;
-            uint32_t jtag_reset_flag_clr_appcpu: 1;
-            uint32_t rtc_dreset_mask_appcpu:     1;
-            uint32_t rtc_dreset_mask_procpu:     1;
-            uint32_t reserved26:                 6;
-        };
-        uint32_t val;
-    } reset_state;
-    union {
-        struct {
-            uint32_t reserved0:     15;
-            uint32_t rtc_wakeup_ena:17;                    /*wakeup enable bitmap*/
-        };
-        uint32_t val;
-    } wakeup_state;
-    union {
-        struct {
-            uint32_t slp_wakeup:               1;          /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject:               1;          /*enable sleep reject interrupt*/
-            uint32_t reserved2:                1;          /*enable SDIO idle interrupt*/
-            uint32_t rtc_wdt:                  1;          /*enable RTC WDT interrupt*/
-            uint32_t reserved4:                5;
-            uint32_t rtc_brown_out:            1;          /*enable brown out interrupt*/
-            uint32_t rtc_main_timer:           1;          /*enable RTC main timer interrupt*/
-            uint32_t reserved11:               4;          /*enable saradc2 interrupt*/
-            uint32_t rtc_swd:                  1;          /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead:         1;          /*enable xtal32k_dead  interrupt*/
-            uint32_t reserved17:               2;          /*enable touch timeout interrupt*/
-            uint32_t rtc_glitch_det:           1;          /*enbale gitch det interrupt*/
-            uint32_t rtc_bbpll_cal:            1;
-            uint32_t reserved21:              11;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t slp_wakeup:               1;          /*sleep wakeup interrupt raw*/
-            uint32_t slp_reject:               1;          /*sleep reject interrupt raw*/
-            uint32_t reserved2:                1;          /*SDIO idle interrupt raw*/
-            uint32_t rtc_wdt:                  1;          /*RTC WDT interrupt raw*/
-            uint32_t reserved4:                5;          /*touch inactive interrupt raw*/
-            uint32_t rtc_brown_out:            1;          /*brown out interrupt raw*/
-            uint32_t rtc_main_timer:           1;          /*RTC main timer interrupt raw*/
-            uint32_t reserved11:               4;          /*saradc2 interrupt raw*/
-            uint32_t rtc_swd:                  1;          /*super watch dog interrupt raw*/
-            uint32_t rtc_xtal32k_dead:         1;          /*xtal32k dead detection interrupt raw*/
-            uint32_t reserved17:               2;          /*touch timeout interrupt raw*/
-            uint32_t rtc_glitch_det:           1;          /*glitch_det_interrupt_raw*/
-            uint32_t rtc_bbpll_cal:            1;
-            uint32_t reserved21:              11;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t slp_wakeup:              1;           /*sleep wakeup interrupt state*/
-            uint32_t slp_reject:              1;           /*sleep reject interrupt state*/
-            uint32_t reserved2:               1;
-            uint32_t rtc_wdt:                 1;           /*RTC WDT interrupt state*/
-            uint32_t reserved4:               5;
-            uint32_t rtc_brown_out:           1;           /*brown out interrupt state*/
-            uint32_t rtc_main_timer:          1;           /*RTC main timer interrupt state*/
-            uint32_t reserved11:              4;
-            uint32_t rtc_swd:                 1;           /*super watch dog interrupt state*/
-            uint32_t rtc_xtal32k_dead:        1;           /*xtal32k dead detection interrupt state*/
-            uint32_t reserved17:              2;
-            uint32_t rtc_glitch_det:          1;           /*glitch_det_interrupt state*/
-            uint32_t rtc_bbpll_cal:           1;
-            uint32_t reserved21:             11;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t slp_wakeup:               1;          /*Clear sleep wakeup interrupt state*/
-            uint32_t slp_reject:               1;          /*Clear sleep reject interrupt state*/
-            uint32_t reserved2:                1;
-            uint32_t rtc_wdt:                  1;          /*Clear RTC WDT interrupt state*/
-            uint32_t reserved4:                5;
-            uint32_t rtc_brown_out:            1;          /*Clear brown out interrupt state*/
-            uint32_t rtc_main_timer:           1;          /*Clear RTC main timer interrupt state*/
-            uint32_t reserved11:               4;
-            uint32_t rtc_swd:                  1;          /*Clear super watch dog interrupt state*/
-            uint32_t rtc_xtal32k_dead:         1;          /*Clear RTC WDT interrupt state*/
-            uint32_t reserved17:               2;
-            uint32_t rtc_glitch_det:           1;          /*Clear glitch det interrupt state*/
-            uint32_t rtc_bbpll_cal:            1;
-            uint32_t reserved21:              11;
-        };
-        uint32_t val;
-    } int_clr;
-    uint32_t store[4];                                   /**/
-    union {
-        struct {
-            uint32_t xtal32k_wdt_en:       1;              /*xtal 32k watch dog enable*/
-            uint32_t xtal32k_wdt_clk_fo:   1;              /*xtal 32k watch dog clock force on*/
-            uint32_t xtal32k_wdt_reset:    1;              /*xtal 32k watch dog sw reset*/
-            uint32_t xtal32k_ext_clk_fo:   1;              /*xtal 32k external xtal clock force on*/
-            uint32_t xtal32k_auto_backup:  1;              /*xtal 32k switch to back up clock when xtal is dead*/
-            uint32_t xtal32k_auto_restart: 1;              /*xtal 32k restart xtal when xtal is dead*/
-            uint32_t xtal32k_auto_return:  1;              /*xtal 32k switch back xtal when xtal is restarted*/
-            uint32_t xtal32k_xpd_force:    1;              /*Xtal 32k xpd control by sw or fsm*/
-            uint32_t enckinit_xtal_32k:    1;              /*apply an internal clock to help xtal 32k to start*/
-            uint32_t dbuf_xtal_32k:        1;              /*0: single-end buffer 1: differential buffer*/
-            uint32_t dgm_xtal_32k:         3;              /*xtal_32k gm control*/
-            uint32_t dres_xtal_32k:        3;              /*DRES_XTAL_32K*/
-            uint32_t xpd_xtal_32k:         1;              /*XPD_XTAL_32K*/
-            uint32_t dac_xtal_32k:         3;              /*DAC_XTAL_32K*/
-            uint32_t rtc_wdt_state:        3;              /*state of 32k_wdt*/
-            uint32_t rtc_xtal32k_gpio_sel: 1;              /*XTAL_32K sel. 0: external XTAL_32K*/
-            uint32_t reserved24:           6;
-            uint32_t ctr_lv:               1;              /*0: power down XTAL at high level*/
-            uint32_t ctr_en:               1;
-        };
-        uint32_t val;
-    } ext_xtl_conf;
-    union {
-        struct {
-            uint32_t reserved0:         31;
-            uint32_t gpio_wakeup_filter: 1;                /*enable filter for gpio wakeup event*/
-        };
-        uint32_t val;
-    } ext_wakeup_conf;
-    union {
-        struct {
-            uint32_t reserved0:           12;
-            uint32_t rtc_sleep_reject_ena:18;              /*sleep reject enable*/
-            uint32_t light_slp_reject_en:  1;              /*enable reject for light sleep*/
-            uint32_t deep_slp_reject_en:   1;              /*enable reject for deep sleep*/
-        };
-        uint32_t val;
-    } slp_reject_conf;
-    union {
-        struct {
-            uint32_t reserved0:        29;
-            uint32_t cpusel_conf:       1;                 /*CPU sel option*/
-            uint32_t cpuperiod_sel:     2;
-        };
-        uint32_t val;
-    } cpu_period_conf;
-    union {
-        struct {
-            uint32_t reserved0:                  1;
-            uint32_t efuse_clk_force_gating:     1;
-            uint32_t efuse_clk_force_nogating:   1;
-            uint32_t ck8m_div_sel_vld:           1;        /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
-            uint32_t ck8m_div:                   2;        /*CK8M_D256_OUT divider. 00: div128*/
-            uint32_t enb_ck8m:                   1;        /*disable CK8M and CK8M_D256_OUT*/
-            uint32_t enb_ck8m_div:               1;        /*1: CK8M_D256_OUT is actually CK8M*/
-            uint32_t dig_xtal32k_en:             1;        /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_d256_en:          1;        /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_en:               1;        /*enable CK8M for digital core (no relationship with RTC core)*/
-            uint32_t reserved11:                 1;
-            uint32_t ck8m_div_sel:               3;        /*divider = reg_ck8m_div_sel + 1*/
-            uint32_t xtal_force_nogating:        1;        /*XTAL force no gating during sleep*/
-            uint32_t ck8m_force_nogating:        1;        /*CK8M force no gating during sleep*/
-            uint32_t ck8m_dfreq:                 8;        /*CK8M_DFREQ*/
-            uint32_t ck8m_force_pd:              1;        /*CK8M force power down*/
-            uint32_t ck8m_force_pu:              1;        /*CK8M force power up*/
-            uint32_t xtal_global_force_gating:   1;
-            uint32_t xtal_global_force_nogating: 1;
-            uint32_t fast_clk_rtc_sel:           1;        /*fast_clk_rtc sel. 0: XTAL div 2*/
-            uint32_t ana_clk_rtc_sel:            2;
-        };
-        uint32_t val;
-    } clk_conf;
-    union {
-        struct {
-            uint32_t reserved0:             22;
-            uint32_t rtc_ana_clk_div_vld:    1;            /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
-            uint32_t rtc_ana_clk_div:        8;
-            uint32_t slow_clk_next_edge:     1;
-        };
-        uint32_t val;
-    } slow_clk_conf;
-    union {
-        struct {
-            uint32_t sdio_timer_target: 8;                 /*timer count to apply reg_sdio_dcap after sdio power on*/
-            uint32_t reserved8:         1;
-            uint32_t sdio_dthdrv:       2;                 /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
-            uint32_t sdio_dcap:         2;                 /*ability to prevent LDO from overshoot*/
-            uint32_t sdio_initi:        2;                 /*add resistor from ldo output to ground. 0: no res*/
-            uint32_t sdio_en_initi:     1;                 /*0 to set init[1:0]=0*/
-            uint32_t sdio_dcurlim:      3;                 /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
-            uint32_t sdio_modecurlim:   1;                 /*select current limit mode*/
-            uint32_t sdio_encurlim:     1;                 /*enable current limit*/
-            uint32_t sdio_pd_en:        1;                 /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
-            uint32_t sdio_force:        1;                 /*1: use SW option to control SDIO_REG*/
-            uint32_t sdio_tieh:         1;                 /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
-            uint32_t reg1p8_ready:      1;                 /*read only register for REG1P8_READY*/
-            uint32_t drefl_sdio:        2;                 /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t drefm_sdio:        2;                 /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t drefh_sdio:        2;                 /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t xpd_sdio:          1;
-        };
-        uint32_t val;
-    } sdio_conf;
-    union {
-        struct {
-            uint32_t dg_vdd_drv_b_slp:    8;
-            uint32_t dg_vdd_drv_b_slp_en: 1;
-            uint32_t reserved9:           1;
-            uint32_t bias_buf_idle:       1;
-            uint32_t bias_buf_wake:       1;
-            uint32_t bias_buf_deep_slp:   1;
-            uint32_t bias_buf_monitor:    1;
-            uint32_t pd_cur_deep_slp:     1;               /*xpd cur when rtc in sleep_state*/
-            uint32_t pd_cur_monitor:      1;               /*xpd cur when rtc in monitor state*/
-            uint32_t bias_sleep_deep_slp: 1;               /*bias_sleep when rtc in sleep_state*/
-            uint32_t bias_sleep_monitor:  1;               /*bias_sleep when rtc in monitor state*/
-            uint32_t dbg_atten_deep_slp:  4;               /*DBG_ATTEN when rtc in sleep state*/
-            uint32_t dbg_atten_monitor:   4;               /*DBG_ATTEN when rtc in monitor state*/
-            uint32_t reserved26:          6;
-        };
-        uint32_t val;
-    } bias_conf;
-    union {
-        struct {
-            uint32_t reserved0:           7;
-            uint32_t dig_cal_en:          1;
-            uint32_t reserved8:           6;
-            uint32_t sck_dcap:            8;               /*SCK_DCAP*/
-            uint32_t reserved22:          6;
-            uint32_t rtc_dboost_force_pd: 1;               /*RTC_DBOOST force power down*/
-            uint32_t rtc_dboost_force_pu: 1;               /*RTC_DBOOST force power up*/
-            uint32_t rtculator_force_pd:  1;               /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
-            uint32_t rtculator_force_pu:  1;
-        };
-        uint32_t val;
-    } rtc;
-    union {
-        struct {
-            uint32_t reserved0:         21;
-            uint32_t rtc_pad_force_hold: 1;                /*rtc pad force hold*/
-            uint32_t reserved22:        10;
-        };
-        uint32_t val;
-    } rtc_pwc;
-    union {
-        struct {
-            uint32_t vdd_spi_pwr_drv:       2;
-            uint32_t vdd_spi_pwr_force:     1;
-            uint32_t lslp_mem_force_pd:     1;             /*memories in digital core force PD in sleep*/
-            uint32_t lslp_mem_force_pu:     1;             /*memories in digital core force no PD in sleep*/
-            uint32_t reserved5:             6;
-            uint32_t bt_force_pd:           1;
-            uint32_t bt_force_pu:           1;
-            uint32_t dg_peri_force_pd:      1;
-            uint32_t dg_peri_force_pu:      1;
-            uint32_t fastmem_force_lpd:     1;
-            uint32_t fastmem_force_lpu:     1;
-            uint32_t wifi_force_pd:         1;             /*wifi force power down*/
-            uint32_t wifi_force_pu:         1;             /*wifi force power up*/
-            uint32_t dg_wrap_force_pd:      1;             /*digital core force power down*/
-            uint32_t dg_wrap_force_pu:      1;             /*digital core force power up*/
-            uint32_t cpu_top_force_pd:      1;
-            uint32_t cpu_top_force_pu:      1;
-            uint32_t reserved23:            4;
-            uint32_t bt_pd_en:              1;
-            uint32_t dg_peri_pd_en:         1;
-            uint32_t cpu_top_pd_en:         1;
-            uint32_t wifi_pd_en:            1;             /*enable power down wifi in sleep*/
-            uint32_t dg_wrap_pd_en:         1;
-        };
-        uint32_t val;
-    } dig_pwc;
-    union {
-        struct {
-            uint32_t reserved0:           7;
-            uint32_t dig_iso_force_off:   1;
-            uint32_t dig_iso_force_on:    1;
-            uint32_t dg_pad_autohold:     1;               /*read only register to indicate digital pad auto-hold status*/
-            uint32_t clr_dg_pad_autohold: 1;               /*wtite only register to clear digital pad auto-hold*/
-            uint32_t dg_pad_autohold_en:  1;               /*digital pad enable auto-hold*/
-            uint32_t dg_pad_force_noiso:  1;               /*digital pad force no ISO*/
-            uint32_t dg_pad_force_iso:    1;               /*digital pad force ISO*/
-            uint32_t dg_pad_force_unhold: 1;               /*digital pad force un-hold*/
-            uint32_t dg_pad_force_hold:   1;               /*digital pad force hold*/
-            uint32_t reserved16:          6;
-            uint32_t bt_force_iso:        1;
-            uint32_t bt_force_noiso:      1;
-            uint32_t dg_peri_force_iso:   1;
-            uint32_t dg_peri_force_noiso: 1;
-            uint32_t cpu_top_force_iso:   1;               /*cpu force ISO*/
-            uint32_t cpu_top_force_noiso: 1;               /*cpu force no ISO*/
-            uint32_t wifi_force_iso:      1;               /*wifi force ISO*/
-            uint32_t wifi_force_noiso:    1;               /*wifi force no ISO*/
-            uint32_t dg_wrap_force_iso:   1;               /*digital core force ISO*/
-            uint32_t dg_wrap_force_noiso: 1;
-        };
-        uint32_t val;
-    } dig_iso;
-    union {
-        struct {
-            uint32_t chip_reset_width:     8;              /*chip reset siginal pulse width*/
-            uint32_t chip_reset_en:        1;              /*wdt reset whole chip enable*/
-            uint32_t pause_in_slp:         1;              /*pause WDT in sleep*/
-            uint32_t appcpu_reset_en:      1;              /*enable WDT reset APP CPU*/
-            uint32_t procpu_reset_en:      1;              /*enable WDT reset PRO CPU*/
-            uint32_t flashboot_mod_en:     1;              /*enable WDT in flash boot*/
-            uint32_t sys_reset_length:     3;              /*system reset counter length*/
-            uint32_t cpu_reset_length:     3;              /*CPU reset counter length*/
-            uint32_t stg3:                 3;              /*1: interrupt stage en*/
-            uint32_t stg2:                 3;              /*1: interrupt stage en*/
-            uint32_t stg1:                 3;              /*1: interrupt stage en*/
-            uint32_t stg0:                 3;              /*1: interrupt stage en*/
-            uint32_t en:                   1;
-        };
-        uint32_t val;
-    } wdt_config0;
-    uint32_t wdt_config1;                               /**/
-    uint32_t wdt_config2;                               /**/
-    uint32_t wdt_config3;                               /**/
-    uint32_t wdt_config4;                               /**/
-    union {
-        struct {
-            uint32_t reserved0:   31;
-            uint32_t feed:         1;
-        };
-        uint32_t val;
-    } wdt_feed;
-    uint32_t wdt_wprotect;                              /**/
-    union {
-        struct {
-            uint32_t swd_reset_flag:   1;                  /*swd reset flag*/
-            uint32_t swd_feed_int:     1;                  /*swd interrupt for feeding*/
-            uint32_t reserved2:       15;
-            uint32_t swd_bypass_rst:   1;
-            uint32_t swd_signal_width:10;                  /*adjust signal width send to swd*/
-            uint32_t swd_rst_flag_clr: 1;                  /*reset swd reset flag*/
-            uint32_t swd_feed:         1;                  /*Sw feed swd*/
-            uint32_t swd_disable:      1;                  /*disabel SWD*/
-            uint32_t swd_auto_feed_en: 1;                  /*automatically feed swd when int comes*/
-        };
-        uint32_t val;
-    } swd_conf;
-    uint32_t swd_wprotect;                             /**/
-    union {
-        struct {
-            uint32_t reserved0:         20;
-            uint32_t appcpu_c1:          6;                /*{reg_sw_stall_appcpu_c1[5:0]*/
-            uint32_t procpu_c1:          6;
-        };
-        uint32_t val;
-    } sw_cpu_stall;
-    uint32_t store4;                                   /**/
-    uint32_t store5;                                   /**/
-    uint32_t store6;                                   /**/
-    uint32_t store7;                                   /**/
-    union {
-        struct {
-            uint32_t xpd_rom0:                   1;        /*rom0 power down*/
-            uint32_t reserved1:                  1;
-            uint32_t xpd_dig_dcdc:               1;        /*External DCDC power down*/
-            uint32_t rtc_peri_iso:               1;        /*rtc peripheral iso*/
-            uint32_t xpd_rtc_peri:               1;        /*rtc peripheral power down*/
-            uint32_t wifi_iso:                   1;        /*wifi iso*/
-            uint32_t xpd_wifi:                   1;        /*wifi wrap power down*/
-            uint32_t dig_iso:                    1;        /*digital wrap iso*/
-            uint32_t xpd_dig:                    1;        /*digital wrap power down*/
-            uint32_t rtc_touch_state_start:      1;        /*touch should start to work*/
-            uint32_t rtc_touch_state_switch:     1;        /*touch is about to working. Switch rtc main state*/
-            uint32_t rtc_touch_state_slp:        1;        /*touch is in sleep state*/
-            uint32_t rtc_touch_state_done:       1;        /*touch is done*/
-            uint32_t rtc_cocpu_state_start:      1;        /*ulp/cocpu should start to work*/
-            uint32_t rtc_cocpu_state_switch:     1;        /*ulp/cocpu is about to working. Switch rtc main state*/
-            uint32_t rtc_cocpu_state_slp:        1;        /*ulp/cocpu is in sleep state*/
-            uint32_t rtc_cocpu_state_done:       1;        /*ulp/cocpu is done*/
-            uint32_t rtc_main_state_xtal_iso:    1;        /*no use any more*/
-            uint32_t rtc_main_state_pll_on:      1;        /*rtc main state machine is in states that pll should be running*/
-            uint32_t rtc_rdy_for_wakeup:         1;        /*rtc is ready to receive wake up trigger from wake up source*/
-            uint32_t rtc_main_state_wait_end:    1;        /*rtc main state machine has been waited for some cycles*/
-            uint32_t rtc_in_wakeup_state:        1;        /*rtc main state machine is in the states of wakeup process*/
-            uint32_t rtc_in_low_power_state:     1;        /*rtc main state machine is in the states of low power*/
-            uint32_t rtc_main_state_in_wait_8m:  1;        /*rtc main state machine is in wait 8m state*/
-            uint32_t rtc_main_state_in_wait_pll: 1;        /*rtc main state machine is in wait pll state*/
-            uint32_t rtc_main_state_in_wait_xtl: 1;        /*rtc main state machine is in wait xtal state*/
-            uint32_t rtc_main_state_in_slp:      1;        /*rtc main state machine is in sleep state*/
-            uint32_t rtc_main_state_in_idle:     1;        /*rtc main state machine is in idle state*/
-            uint32_t rtc_main_state:             4;        /*rtc main state machine status*/
-        };
-        uint32_t val;
-    } low_power_st;
-    uint32_t diag0;                                    /**/
-    union {
-        struct {
-            uint32_t rtc_gpio_pin0_hold: 1;
-            uint32_t rtc_gpio_pin1_hold: 1;
-            uint32_t rtc_gpio_pin2_hold: 1;
-            uint32_t rtc_gpio_pin3_hold: 1;
-            uint32_t rtc_gpio_pin4_hold: 1;
-            uint32_t rtc_gpio_pin5_hold: 1;
-            uint32_t reserved6:         26;
-        };
-        uint32_t val;
-    } pad_hold;
-    uint32_t dig_pad_hold;                                 /**/
-    union {
-        struct {
-            uint32_t reserved0:                 4;
-            uint32_t int_wait:                 10;         /*brown out interrupt wait cycles*/
-            uint32_t close_flash_ena:           1;         /*enable close flash when brown out happens*/
-            uint32_t pd_rf_ena:                 1;         /*enable power down RF when brown out happens*/
-            uint32_t rst_wait:                 10;         /*brown out reset wait cycles*/
-            uint32_t rst_ena:                   1;         /*enable brown out reset*/
-            uint32_t rst_sel:                   1;         /*1:  4-pos reset*/
-            uint32_t ana_rst_en:                1;
-            uint32_t cnt_clr:                   1;         /*clear brown out counter*/
-            uint32_t ena:                       1;         /*enable brown out*/
-            uint32_t det:                       1;
-        };
-        uint32_t val;
-    } brown_out;
-    uint32_t time_low1;                                /*RTC timer low 32 bits*/
-    union {
-        struct {
-            uint32_t rtc_timer_value1_high:16;             /*RTC timer high 16 bits*/
-            uint32_t reserved16:           16;
-        };
-        uint32_t val;
-    } time_high1;
-    uint32_t xtal32k_clk_factor;                       /*xtal 32k watch dog backup clock factor*/
-    union {
-        struct {
-            uint32_t xtal32k_return_wait:  4;              /*cycles to wait to return noral xtal 32k*/
-            uint32_t xtal32k_restart_wait:16;              /*cycles to wait to repower on xtal 32k*/
-            uint32_t xtal32k_wdt_timeout:  8;              /*If no clock detected for this amount of time*/
-            uint32_t xtal32k_stable_thres: 4;              /*if restarted xtal32k period is smaller than this*/
-        };
-        uint32_t val;
-    } xtal32k_conf;
-    union {
-        struct {
-            uint32_t reserved0:           18;
-            uint32_t io_mux_reset_disable: 1;
-            uint32_t reserved19:          13;
-        };
-        uint32_t val;
-    } usb_conf;
-    union {
-        struct {
-            uint32_t reject_cause:18;                      /*sleep reject cause*/
-            uint32_t reserved18:  14;
-        };
-        uint32_t val;
-    } slp_reject_cause;
-    union {
-        struct {
-            uint32_t force_download_boot: 1;
-            uint32_t reserved1:          31;
-        };
-        uint32_t val;
-    } option1;
-    union {
-        struct {
-            uint32_t wakeup_cause:17;                      /*sleep wakeup cause*/
-            uint32_t reserved17:  15;
-        };
-        uint32_t val;
-    } slp_wakeup_cause;
-    union {
-        struct {
-            uint32_t reserved0:              8;
-            uint32_t ulp_cp_timer_slp_cycle:24;            /*sleep cycles for ULP-coprocessor timer*/
-        };
-        uint32_t val;
-    } ulp_cp_timer_1;
-    union {
-        struct {
-            uint32_t slp_wakeup_w1ts:               1;     /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject_w1ts:               1;     /*enable sleep reject interrupt*/
-            uint32_t reserved2:                     1;
-            uint32_t rtc_wdt_w1ts:                  1;     /*enable RTC WDT interrupt*/
-            uint32_t reserved4:                     5;
-            uint32_t w1ts:                          1;     /*enable brown out interrupt*/
-            uint32_t rtc_main_timer_w1ts:           1;     /*enable RTC main timer interrupt*/
-            uint32_t reserved11:                    4;
-            uint32_t rtc_swd_w1ts:                  1;     /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead_w1ts:         1;     /*enable xtal32k_dead  interrupt*/
-            uint32_t reserved17:                    2;
-            uint32_t rtc_glitch_det_w1ts:           1;     /*enbale gitch det interrupt*/
-            uint32_t rtc_bbpll_cal_w1ts:            1;
-            uint32_t reserved21:                   11;
-        };
-        uint32_t val;
-    } int_ena_w1ts;
-    union {
-        struct {
-            uint32_t slp_wakeup_w1tc:               1;     /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject_w1tc:               1;     /*enable sleep reject interrupt*/
-            uint32_t reserved2:                     1;
-            uint32_t rtc_wdt_w1tc:                  1;     /*enable RTC WDT interrupt*/
-            uint32_t reserved4:                     5;
-            uint32_t w1tc:                          1;     /*enable brown out interrupt*/
-            uint32_t rtc_main_timer_w1tc:           1;     /*enable RTC main timer interrupt*/
-            uint32_t reserved11:                    4;
-            uint32_t rtc_swd_w1tc:                  1;     /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead_w1tc:         1;     /*enable xtal32k_dead  interrupt*/
-            uint32_t reserved17:                    2;
-            uint32_t rtc_glitch_det_w1tc:           1;     /*enbale gitch det interrupt*/
-            uint32_t rtc_bbpll_cal_w1tc:            1;
-            uint32_t reserved21:                   11;
-        };
-        uint32_t val;
-    } int_ena_w1tc;
-    union {
-        struct {
-            uint32_t reserved0:            18;
-            uint32_t retention_clk_sel:     1;
-            uint32_t retention_done_wait:   3;
-            uint32_t retention_clkoff_wait: 4;
-            uint32_t retention_en:          1;
-            uint32_t retention_wait:        5;             /*wait cycles for rention operation*/
-        };
-        uint32_t val;
-    } retention_ctrl;
-    union {
-        struct {
-            uint32_t rtc_fib_sel: 3;                       /*select use analog fib signal*/
-            uint32_t reserved3:  29;
-        };
-        uint32_t val;
-    } fib_sel;
-    union {
-        struct {
-            uint32_t rtc_gpio_wakeup_status:      6;
-            uint32_t rtc_gpio_wakeup_status_clr:  1;
-            uint32_t rtc_gpio_pin_clk_gate:       1;
-            uint32_t rtc_gpio_pin5_int_type:      3;
-            uint32_t rtc_gpio_pin4_int_type:      3;
-            uint32_t rtc_gpio_pin3_int_type:      3;
-            uint32_t rtc_gpio_pin2_int_type:      3;
-            uint32_t rtc_gpio_pin1_int_type:      3;
-            uint32_t rtc_gpio_pin0_int_type:      3;
-            uint32_t rtc_gpio_pin5_wakeup_enable: 1;
-            uint32_t rtc_gpio_pin4_wakeup_enable: 1;
-            uint32_t rtc_gpio_pin3_wakeup_enable: 1;
-            uint32_t rtc_gpio_pin2_wakeup_enable: 1;
-            uint32_t rtc_gpio_pin1_wakeup_enable: 1;
-            uint32_t rtc_gpio_pin0_wakeup_enable: 1;
-        };
-        uint32_t val;
-    } gpio_wakeup;
-    union {
-        struct {
-            uint32_t reserved0:               1;
-            uint32_t rtc_debug_12m_no_gating: 1;
-            uint32_t rtc_debug_bit_sel:       5;
-            uint32_t rtc_debug_sel0:          5;
-            uint32_t rtc_debug_sel1:          5;
-            uint32_t rtc_debug_sel2:          5;
-            uint32_t rtc_debug_sel3:          5;
-            uint32_t rtc_debug_sel4:          5;
-        };
-        uint32_t val;
-    } dbg_sel;
-    union {
-        struct {
-            uint32_t reserved0:             2;
-            uint32_t rtc_gpio_pin5_mux_sel: 1;
-            uint32_t rtc_gpio_pin4_mux_sel: 1;
-            uint32_t rtc_gpio_pin3_mux_sel: 1;
-            uint32_t rtc_gpio_pin2_mux_sel: 1;
-            uint32_t rtc_gpio_pin1_mux_sel: 1;
-            uint32_t rtc_gpio_pin0_mux_sel: 1;
-            uint32_t rtc_gpio_pin5_fun_sel: 4;
-            uint32_t rtc_gpio_pin4_fun_sel: 4;
-            uint32_t rtc_gpio_pin3_fun_sel: 4;
-            uint32_t rtc_gpio_pin2_fun_sel: 4;
-            uint32_t rtc_gpio_pin1_fun_sel: 4;
-            uint32_t rtc_gpio_pin0_fun_sel: 4;
-        };
-        uint32_t val;
-    } dbg_map;
-    union {
-        struct {
-            uint32_t reserved0:     27;
-            uint32_t sar2_pwdet_cct: 3;
-            uint32_t force_xpd_sar:  2;
-        };
-        uint32_t val;
-    } sensor_ctrl;
-    union {
-        struct {
-            uint32_t reserved0:    27;
-            uint32_t sar_debug_sel: 5;
-        };
-        uint32_t val;
-    } dbg_sar_sel;
-    union {
-        struct {
-            uint32_t reserved0:             26;
-            uint32_t power_glitch_dsense:    2;
-            uint32_t power_glitch_force_pd:  1;
-            uint32_t power_glitch_force_pu:  1;
-            uint32_t power_glitch_efuse_sel: 1;
-            uint32_t power_glitch_en:        1;
-        };
-        uint32_t val;
-    } pg_ctrl;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    union {
-        struct {
-            uint32_t date:      28;
-            uint32_t reserved28: 4;
-        };
-        uint32_t val;
-    } date;
-} rtc_cntl_dev_t;
-extern rtc_cntl_dev_t RTCCNTL;
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_reg.h b/components/soc/esp32c3/include/soc/rtc_i2c_reg.h
deleted file mode 100644
index 52bdefc0e56..00000000000
--- a/components/soc/esp32c3/include/soc/rtc_i2c_reg.h
+++ /dev/null
@@ -1,684 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_RTC_I2C_REG_H_
-#define _SOC_RTC_I2C_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define RTC_I2C_SCL_LOW_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0000)
-/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
-/*description: time period that scl = 0*/
-#define RTC_I2C_SCL_LOW_PERIOD  0x000FFFFF
-#define RTC_I2C_SCL_LOW_PERIOD_M  ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
-#define RTC_I2C_SCL_LOW_PERIOD_V  0xFFFFF
-#define RTC_I2C_SCL_LOW_PERIOD_S  0
-
-#define RTC_I2C_CTRL_REG          (DR_REG_RTC_I2C_BASE + 0x0004)
-/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: rtc i2c reg clk gating*/
-#define RTC_I2C_CLK_EN  (BIT(31))
-#define RTC_I2C_CLK_EN_M  (BIT(31))
-#define RTC_I2C_CLK_EN_V  0x1
-#define RTC_I2C_CLK_EN_S  31
-/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: rtc i2c sw reset*/
-#define RTC_I2C_RESET  (BIT(30))
-#define RTC_I2C_RESET_M  (BIT(30))
-#define RTC_I2C_RESET_V  0x1
-#define RTC_I2C_RESET_S  30
-/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define RTC_I2C_CTRL_CLK_GATE_EN  (BIT(29))
-#define RTC_I2C_CTRL_CLK_GATE_EN_M  (BIT(29))
-#define RTC_I2C_CTRL_CLK_GATE_EN_V  0x1
-#define RTC_I2C_CTRL_CLK_GATE_EN_S  29
-/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: receive lsb first*/
-#define RTC_I2C_RX_LSB_FIRST  (BIT(5))
-#define RTC_I2C_RX_LSB_FIRST_M  (BIT(5))
-#define RTC_I2C_RX_LSB_FIRST_V  0x1
-#define RTC_I2C_RX_LSB_FIRST_S  5
-/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: transit lsb first*/
-#define RTC_I2C_TX_LSB_FIRST  (BIT(4))
-#define RTC_I2C_TX_LSB_FIRST_M  (BIT(4))
-#define RTC_I2C_TX_LSB_FIRST_V  0x1
-#define RTC_I2C_TX_LSB_FIRST_S  4
-/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: force start*/
-#define RTC_I2C_TRANS_START  (BIT(3))
-#define RTC_I2C_TRANS_START_M  (BIT(3))
-#define RTC_I2C_TRANS_START_V  0x1
-#define RTC_I2C_TRANS_START_S  3
-/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1=master  0=slave*/
-#define RTC_I2C_MS_MODE  (BIT(2))
-#define RTC_I2C_MS_MODE_M  (BIT(2))
-#define RTC_I2C_MS_MODE_V  0x1
-#define RTC_I2C_MS_MODE_S  2
-/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1=push pull  0=open drain*/
-#define RTC_I2C_SCL_FORCE_OUT  (BIT(1))
-#define RTC_I2C_SCL_FORCE_OUT_M  (BIT(1))
-#define RTC_I2C_SCL_FORCE_OUT_V  0x1
-#define RTC_I2C_SCL_FORCE_OUT_S  1
-/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1=push pull  0=open drain*/
-#define RTC_I2C_SDA_FORCE_OUT  (BIT(0))
-#define RTC_I2C_SDA_FORCE_OUT_M  (BIT(0))
-#define RTC_I2C_SDA_FORCE_OUT_V  0x1
-#define RTC_I2C_SDA_FORCE_OUT_S  0
-
-#define RTC_I2C_STATUS_REG          (DR_REG_RTC_I2C_BASE + 0x0008)
-/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
-/*description: scl last status*/
-#define RTC_I2C_SCL_STATE_LAST  0x00000007
-#define RTC_I2C_SCL_STATE_LAST_M  ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
-#define RTC_I2C_SCL_STATE_LAST_V  0x7
-#define RTC_I2C_SCL_STATE_LAST_S  28
-/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
-/*description: i2c last main status*/
-#define RTC_I2C_SCL_MAIN_STATE_LAST  0x00000007
-#define RTC_I2C_SCL_MAIN_STATE_LAST_M  ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
-#define RTC_I2C_SCL_MAIN_STATE_LAST_V  0x7
-#define RTC_I2C_SCL_MAIN_STATE_LAST_S  24
-/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
-/*description: shifter content*/
-#define RTC_I2C_SHIFT  0x000000FF
-#define RTC_I2C_SHIFT_M  ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
-#define RTC_I2C_SHIFT_V  0xFF
-#define RTC_I2C_SHIFT_S  16
-/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: which operation is working*/
-#define RTC_I2C_OP_CNT  0x00000003
-#define RTC_I2C_OP_CNT_M  ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
-#define RTC_I2C_OP_CNT_V  0x3
-#define RTC_I2C_OP_CNT_S  6
-/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: One byte transit done*/
-#define RTC_I2C_BYTE_TRANS  (BIT(5))
-#define RTC_I2C_BYTE_TRANS_M  (BIT(5))
-#define RTC_I2C_BYTE_TRANS_V  0x1
-#define RTC_I2C_BYTE_TRANS_S  5
-/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: slave reg sub address*/
-#define RTC_I2C_SLAVE_ADDRESSED  (BIT(4))
-#define RTC_I2C_SLAVE_ADDRESSED_M  (BIT(4))
-#define RTC_I2C_SLAVE_ADDRESSED_V  0x1
-#define RTC_I2C_SLAVE_ADDRESSED_S  4
-/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: bus is busy*/
-#define RTC_I2C_BUS_BUSY  (BIT(3))
-#define RTC_I2C_BUS_BUSY_M  (BIT(3))
-#define RTC_I2C_BUS_BUSY_V  0x1
-#define RTC_I2C_BUS_BUSY_S  3
-/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: arbitration is lost*/
-#define RTC_I2C_ARB_LOST  (BIT(2))
-#define RTC_I2C_ARB_LOST_M  (BIT(2))
-#define RTC_I2C_ARB_LOST_V  0x1
-#define RTC_I2C_ARB_LOST_S  2
-/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: slave read or write*/
-#define RTC_I2C_SLAVE_RW  (BIT(1))
-#define RTC_I2C_SLAVE_RW_M  (BIT(1))
-#define RTC_I2C_SLAVE_RW_V  0x1
-#define RTC_I2C_SLAVE_RW_S  1
-/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: ack response*/
-#define RTC_I2C_ACK_REC  (BIT(0))
-#define RTC_I2C_ACK_REC_M  (BIT(0))
-#define RTC_I2C_ACK_REC_V  0x1
-#define RTC_I2C_ACK_REC_S  0
-
-#define RTC_I2C_TIMEOUT_REG          (DR_REG_RTC_I2C_BASE + 0x000c)
-/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
-/*description: time out threshold*/
-#define RTC_I2C_TIMEOUT  0x000FFFFF
-#define RTC_I2C_TIMEOUT_M  ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
-#define RTC_I2C_TIMEOUT_V  0xFFFFF
-#define RTC_I2C_TIMEOUT_S  0
-
-#define RTC_I2C_SLAVE_ADDR_REG          (DR_REG_RTC_I2C_BASE + 0x0010)
-/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: i2c 10bit mode enable*/
-#define RTC_I2C_ADDR_10BIT_EN  (BIT(31))
-#define RTC_I2C_ADDR_10BIT_EN_M  (BIT(31))
-#define RTC_I2C_ADDR_10BIT_EN_V  0x1
-#define RTC_I2C_ADDR_10BIT_EN_S  31
-/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
-/*description: slave address*/
-#define RTC_I2C_SLAVE_ADDR  0x00007FFF
-#define RTC_I2C_SLAVE_ADDR_M  ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
-#define RTC_I2C_SLAVE_ADDR_V  0x7FFF
-#define RTC_I2C_SLAVE_ADDR_S  0
-
-#define RTC_I2C_SCL_HIGH_REG          (DR_REG_RTC_I2C_BASE + 0x0014)
-/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
-/*description: time period that scl = 1*/
-#define RTC_I2C_SCL_HIGH_PERIOD  0x000FFFFF
-#define RTC_I2C_SCL_HIGH_PERIOD_M  ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
-#define RTC_I2C_SCL_HIGH_PERIOD_V  0xFFFFF
-#define RTC_I2C_SCL_HIGH_PERIOD_S  0
-
-#define RTC_I2C_SDA_DUTY_REG          (DR_REG_RTC_I2C_BASE + 0x0018)
-/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
-/*description: time period for SDA to toggle after SCL goes low*/
-#define RTC_I2C_SDA_DUTY_NUM  0x000FFFFF
-#define RTC_I2C_SDA_DUTY_NUM_M  ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
-#define RTC_I2C_SDA_DUTY_NUM_V  0xFFFFF
-#define RTC_I2C_SDA_DUTY_NUM_S  0
-
-#define RTC_I2C_SCL_START_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x001c)
-/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
-/*description: time period for SCL to toggle after I2C start is triggered*/
-#define RTC_I2C_SCL_START_PERIOD  0x000FFFFF
-#define RTC_I2C_SCL_START_PERIOD_M  ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
-#define RTC_I2C_SCL_START_PERIOD_V  0xFFFFF
-#define RTC_I2C_SCL_START_PERIOD_S  0
-
-#define RTC_I2C_SCL_STOP_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0020)
-/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
-/*description: time period for SCL to stop after I2C end is triggered*/
-#define RTC_I2C_SCL_STOP_PERIOD  0x000FFFFF
-#define RTC_I2C_SCL_STOP_PERIOD_M  ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
-#define RTC_I2C_SCL_STOP_PERIOD_V  0xFFFFF
-#define RTC_I2C_SCL_STOP_PERIOD_S  0
-
-#define RTC_I2C_INT_CLR_REG          (DR_REG_RTC_I2C_BASE + 0x0024)
-/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: clear detect start interrupt*/
-#define RTC_I2C_DETECT_START_INT_CLR  (BIT(8))
-#define RTC_I2C_DETECT_START_INT_CLR_M  (BIT(8))
-#define RTC_I2C_DETECT_START_INT_CLR_V  0x1
-#define RTC_I2C_DETECT_START_INT_CLR_S  8
-/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: clear transit load data complete interrupt*/
-#define RTC_I2C_TX_DATA_INT_CLR  (BIT(7))
-#define RTC_I2C_TX_DATA_INT_CLR_M  (BIT(7))
-#define RTC_I2C_TX_DATA_INT_CLR_V  0x1
-#define RTC_I2C_TX_DATA_INT_CLR_S  7
-/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: clear receive data interrupt*/
-#define RTC_I2C_RX_DATA_INT_CLR  (BIT(6))
-#define RTC_I2C_RX_DATA_INT_CLR_M  (BIT(6))
-#define RTC_I2C_RX_DATA_INT_CLR_V  0x1
-#define RTC_I2C_RX_DATA_INT_CLR_S  6
-/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: clear ack error interrupt*/
-#define RTC_I2C_ACK_ERR_INT_CLR  (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_CLR_M  (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_CLR_V  0x1
-#define RTC_I2C_ACK_ERR_INT_CLR_S  5
-/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: clear time out interrupt*/
-#define RTC_I2C_TIMEOUT_INT_CLR  (BIT(4))
-#define RTC_I2C_TIMEOUT_INT_CLR_M  (BIT(4))
-#define RTC_I2C_TIMEOUT_INT_CLR_V  0x1
-#define RTC_I2C_TIMEOUT_INT_CLR_S  4
-/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: clear transit complete interrupt*/
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR  (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V  0x1
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S  3
-/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: clear master transit complete interrupt*/
-#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR  (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M  (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V  0x1
-#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S  2
-/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: clear arbitration lost interrupt*/
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR  (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V  0x1
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S  1
-/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: clear slave transit complete interrupt*/
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR  (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M  (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x1
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S  0
-
-#define RTC_I2C_INT_RAW_REG          (DR_REG_RTC_I2C_BASE + 0x0028)
-/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: detect start interrupt raw*/
-#define RTC_I2C_DETECT_START_INT_RAW  (BIT(8))
-#define RTC_I2C_DETECT_START_INT_RAW_M  (BIT(8))
-#define RTC_I2C_DETECT_START_INT_RAW_V  0x1
-#define RTC_I2C_DETECT_START_INT_RAW_S  8
-/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: transit data interrupt raw*/
-#define RTC_I2C_TX_DATA_INT_RAW  (BIT(7))
-#define RTC_I2C_TX_DATA_INT_RAW_M  (BIT(7))
-#define RTC_I2C_TX_DATA_INT_RAW_V  0x1
-#define RTC_I2C_TX_DATA_INT_RAW_S  7
-/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: receive data interrupt raw*/
-#define RTC_I2C_RX_DATA_INT_RAW  (BIT(6))
-#define RTC_I2C_RX_DATA_INT_RAW_M  (BIT(6))
-#define RTC_I2C_RX_DATA_INT_RAW_V  0x1
-#define RTC_I2C_RX_DATA_INT_RAW_S  6
-/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: ack error interrupt raw*/
-#define RTC_I2C_ACK_ERR_INT_RAW  (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_RAW_M  (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_RAW_V  0x1
-#define RTC_I2C_ACK_ERR_INT_RAW_S  5
-/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: time out interrupt raw*/
-#define RTC_I2C_TIMEOUT_INT_RAW  (BIT(4))
-#define RTC_I2C_TIMEOUT_INT_RAW_M  (BIT(4))
-#define RTC_I2C_TIMEOUT_INT_RAW_V  0x1
-#define RTC_I2C_TIMEOUT_INT_RAW_S  4
-/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: transit complete interrupt raw*/
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW  (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V  0x1
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S  3
-/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: master transit complete interrupt raw*/
-#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW  (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M  (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V  0x1
-#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S  2
-/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: arbitration lost interrupt raw*/
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW  (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V  0x1
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S  1
-/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: slave transit complete interrupt raw*/
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW  (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M  (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x1
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S  0
-
-#define RTC_I2C_INT_ST_REG          (DR_REG_RTC_I2C_BASE + 0x002c)
-/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: detect start interrupt state*/
-#define RTC_I2C_DETECT_START_INT_ST  (BIT(8))
-#define RTC_I2C_DETECT_START_INT_ST_M  (BIT(8))
-#define RTC_I2C_DETECT_START_INT_ST_V  0x1
-#define RTC_I2C_DETECT_START_INT_ST_S  8
-/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: transit data interrupt state*/
-#define RTC_I2C_TX_DATA_INT_ST  (BIT(7))
-#define RTC_I2C_TX_DATA_INT_ST_M  (BIT(7))
-#define RTC_I2C_TX_DATA_INT_ST_V  0x1
-#define RTC_I2C_TX_DATA_INT_ST_S  7
-/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: receive data interrupt state*/
-#define RTC_I2C_RX_DATA_INT_ST  (BIT(6))
-#define RTC_I2C_RX_DATA_INT_ST_M  (BIT(6))
-#define RTC_I2C_RX_DATA_INT_ST_V  0x1
-#define RTC_I2C_RX_DATA_INT_ST_S  6
-/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: ack error interrupt state*/
-#define RTC_I2C_ACK_ERR_INT_ST  (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_ST_M  (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_ST_V  0x1
-#define RTC_I2C_ACK_ERR_INT_ST_S  5
-/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: time out interrupt state*/
-#define RTC_I2C_TIMEOUT_INT_ST  (BIT(4))
-#define RTC_I2C_TIMEOUT_INT_ST_M  (BIT(4))
-#define RTC_I2C_TIMEOUT_INT_ST_V  0x1
-#define RTC_I2C_TIMEOUT_INT_ST_S  4
-/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: transit complete interrupt state*/
-#define RTC_I2C_TRANS_COMPLETE_INT_ST  (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_ST_M  (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_ST_V  0x1
-#define RTC_I2C_TRANS_COMPLETE_INT_ST_S  3
-/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: master transit complete interrupt state*/
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ST  (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M  (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V  0x1
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S  2
-/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: arbitration lost interrupt state*/
-#define RTC_I2C_ARBITRATION_LOST_INT_ST  (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_ST_M  (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_ST_V  0x1
-#define RTC_I2C_ARBITRATION_LOST_INT_ST_S  1
-/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: slave transit complete interrupt state*/
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST  (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M  (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V  0x1
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S  0
-
-#define RTC_I2C_INT_ENA_REG          (DR_REG_RTC_I2C_BASE + 0x0030)
-/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: enable detect start interrupt*/
-#define RTC_I2C_DETECT_START_INT_ENA  (BIT(8))
-#define RTC_I2C_DETECT_START_INT_ENA_M  (BIT(8))
-#define RTC_I2C_DETECT_START_INT_ENA_V  0x1
-#define RTC_I2C_DETECT_START_INT_ENA_S  8
-/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: enable transit data interrupt*/
-#define RTC_I2C_TX_DATA_INT_ENA  (BIT(7))
-#define RTC_I2C_TX_DATA_INT_ENA_M  (BIT(7))
-#define RTC_I2C_TX_DATA_INT_ENA_V  0x1
-#define RTC_I2C_TX_DATA_INT_ENA_S  7
-/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: enable receive data interrupt*/
-#define RTC_I2C_RX_DATA_INT_ENA  (BIT(6))
-#define RTC_I2C_RX_DATA_INT_ENA_M  (BIT(6))
-#define RTC_I2C_RX_DATA_INT_ENA_V  0x1
-#define RTC_I2C_RX_DATA_INT_ENA_S  6
-/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: enable eack error interrupt*/
-#define RTC_I2C_ACK_ERR_INT_ENA  (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_ENA_M  (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_ENA_V  0x1
-#define RTC_I2C_ACK_ERR_INT_ENA_S  5
-/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: enable time out interrupt*/
-#define RTC_I2C_TIMEOUT_INT_ENA  (BIT(4))
-#define RTC_I2C_TIMEOUT_INT_ENA_M  (BIT(4))
-#define RTC_I2C_TIMEOUT_INT_ENA_V  0x1
-#define RTC_I2C_TIMEOUT_INT_ENA_S  4
-/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable transit complete interrupt*/
-#define RTC_I2C_TRANS_COMPLETE_INT_ENA  (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V  0x1
-#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S  3
-/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: enable master transit complete interrupt*/
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA  (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M  (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V  0x1
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S  2
-/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable arbitration lost interrupt*/
-#define RTC_I2C_ARBITRATION_LOST_INT_ENA  (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V  0x1
-#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S  1
-/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable slave transit complete interrupt*/
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA  (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M  (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x1
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S  0
-
-#define RTC_I2C_DATA_REG          (DR_REG_RTC_I2C_BASE + 0x0034)
-/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: i2c done*/
-#define RTC_I2C_DONE  (BIT(31))
-#define RTC_I2C_DONE_M  (BIT(31))
-#define RTC_I2C_DONE_V  0x1
-#define RTC_I2C_DONE_S  31
-/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
-/*description: data sent by slave*/
-#define RTC_I2C_SLAVE_TX_DATA  0x000000FF
-#define RTC_I2C_SLAVE_TX_DATA_M  ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
-#define RTC_I2C_SLAVE_TX_DATA_V  0xFF
-#define RTC_I2C_SLAVE_TX_DATA_S  8
-/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: data received*/
-#define RTC_I2C_RDATA  0x000000FF
-#define RTC_I2C_RDATA_M  ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
-#define RTC_I2C_RDATA_V  0xFF
-#define RTC_I2C_RDATA_S  0
-
-#define RTC_I2C_CMD0_REG          (DR_REG_RTC_I2C_BASE + 0x0038)
-/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command0_done*/
-#define RTC_I2C_COMMAND0_DONE  (BIT(31))
-#define RTC_I2C_COMMAND0_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND0_DONE_V  0x1
-#define RTC_I2C_COMMAND0_DONE_S  31
-/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
-/*description: command0*/
-#define RTC_I2C_COMMAND0  0x00003FFF
-#define RTC_I2C_COMMAND0_M  ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
-#define RTC_I2C_COMMAND0_V  0x3FFF
-#define RTC_I2C_COMMAND0_S  0
-
-#define RTC_I2C_CMD1_REG          (DR_REG_RTC_I2C_BASE + 0x003c)
-/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command1_done*/
-#define RTC_I2C_COMMAND1_DONE  (BIT(31))
-#define RTC_I2C_COMMAND1_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND1_DONE_V  0x1
-#define RTC_I2C_COMMAND1_DONE_S  31
-/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
-/*description: command1*/
-#define RTC_I2C_COMMAND1  0x00003FFF
-#define RTC_I2C_COMMAND1_M  ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
-#define RTC_I2C_COMMAND1_V  0x3FFF
-#define RTC_I2C_COMMAND1_S  0
-
-#define RTC_I2C_CMD2_REG          (DR_REG_RTC_I2C_BASE + 0x0040)
-/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command2_done*/
-#define RTC_I2C_COMMAND2_DONE  (BIT(31))
-#define RTC_I2C_COMMAND2_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND2_DONE_V  0x1
-#define RTC_I2C_COMMAND2_DONE_S  31
-/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
-/*description: command2*/
-#define RTC_I2C_COMMAND2  0x00003FFF
-#define RTC_I2C_COMMAND2_M  ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
-#define RTC_I2C_COMMAND2_V  0x3FFF
-#define RTC_I2C_COMMAND2_S  0
-
-#define RTC_I2C_CMD3_REG          (DR_REG_RTC_I2C_BASE + 0x0044)
-/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command3_done*/
-#define RTC_I2C_COMMAND3_DONE  (BIT(31))
-#define RTC_I2C_COMMAND3_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND3_DONE_V  0x1
-#define RTC_I2C_COMMAND3_DONE_S  31
-/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
-/*description: command3*/
-#define RTC_I2C_COMMAND3  0x00003FFF
-#define RTC_I2C_COMMAND3_M  ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
-#define RTC_I2C_COMMAND3_V  0x3FFF
-#define RTC_I2C_COMMAND3_S  0
-
-#define RTC_I2C_CMD4_REG          (DR_REG_RTC_I2C_BASE + 0x0048)
-/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command4_done*/
-#define RTC_I2C_COMMAND4_DONE  (BIT(31))
-#define RTC_I2C_COMMAND4_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND4_DONE_V  0x1
-#define RTC_I2C_COMMAND4_DONE_S  31
-/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
-/*description: command4*/
-#define RTC_I2C_COMMAND4  0x00003FFF
-#define RTC_I2C_COMMAND4_M  ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
-#define RTC_I2C_COMMAND4_V  0x3FFF
-#define RTC_I2C_COMMAND4_S  0
-
-#define RTC_I2C_CMD5_REG          (DR_REG_RTC_I2C_BASE + 0x004c)
-/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command5_done*/
-#define RTC_I2C_COMMAND5_DONE  (BIT(31))
-#define RTC_I2C_COMMAND5_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND5_DONE_V  0x1
-#define RTC_I2C_COMMAND5_DONE_S  31
-/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
-/*description: command5*/
-#define RTC_I2C_COMMAND5  0x00003FFF
-#define RTC_I2C_COMMAND5_M  ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
-#define RTC_I2C_COMMAND5_V  0x3FFF
-#define RTC_I2C_COMMAND5_S  0
-
-#define RTC_I2C_CMD6_REG          (DR_REG_RTC_I2C_BASE + 0x0050)
-/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command6_done*/
-#define RTC_I2C_COMMAND6_DONE  (BIT(31))
-#define RTC_I2C_COMMAND6_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND6_DONE_V  0x1
-#define RTC_I2C_COMMAND6_DONE_S  31
-/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
-/*description: command6*/
-#define RTC_I2C_COMMAND6  0x00003FFF
-#define RTC_I2C_COMMAND6_M  ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
-#define RTC_I2C_COMMAND6_V  0x3FFF
-#define RTC_I2C_COMMAND6_S  0
-
-#define RTC_I2C_CMD7_REG          (DR_REG_RTC_I2C_BASE + 0x0054)
-/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command7_done*/
-#define RTC_I2C_COMMAND7_DONE  (BIT(31))
-#define RTC_I2C_COMMAND7_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND7_DONE_V  0x1
-#define RTC_I2C_COMMAND7_DONE_S  31
-/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
-/*description: command7*/
-#define RTC_I2C_COMMAND7  0x00003FFF
-#define RTC_I2C_COMMAND7_M  ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
-#define RTC_I2C_COMMAND7_V  0x3FFF
-#define RTC_I2C_COMMAND7_S  0
-
-#define RTC_I2C_CMD8_REG          (DR_REG_RTC_I2C_BASE + 0x0058)
-/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command8_done*/
-#define RTC_I2C_COMMAND8_DONE  (BIT(31))
-#define RTC_I2C_COMMAND8_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND8_DONE_V  0x1
-#define RTC_I2C_COMMAND8_DONE_S  31
-/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
-/*description: command8*/
-#define RTC_I2C_COMMAND8  0x00003FFF
-#define RTC_I2C_COMMAND8_M  ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
-#define RTC_I2C_COMMAND8_V  0x3FFF
-#define RTC_I2C_COMMAND8_S  0
-
-#define RTC_I2C_CMD9_REG          (DR_REG_RTC_I2C_BASE + 0x005c)
-/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command9_done*/
-#define RTC_I2C_COMMAND9_DONE  (BIT(31))
-#define RTC_I2C_COMMAND9_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND9_DONE_V  0x1
-#define RTC_I2C_COMMAND9_DONE_S  31
-/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
-/*description: command9*/
-#define RTC_I2C_COMMAND9  0x00003FFF
-#define RTC_I2C_COMMAND9_M  ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
-#define RTC_I2C_COMMAND9_V  0x3FFF
-#define RTC_I2C_COMMAND9_S  0
-
-#define RTC_I2C_CMD10_REG          (DR_REG_RTC_I2C_BASE + 0x0060)
-/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command10_done*/
-#define RTC_I2C_COMMAND10_DONE  (BIT(31))
-#define RTC_I2C_COMMAND10_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND10_DONE_V  0x1
-#define RTC_I2C_COMMAND10_DONE_S  31
-/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
-/*description: command10*/
-#define RTC_I2C_COMMAND10  0x00003FFF
-#define RTC_I2C_COMMAND10_M  ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
-#define RTC_I2C_COMMAND10_V  0x3FFF
-#define RTC_I2C_COMMAND10_S  0
-
-#define RTC_I2C_CMD11_REG          (DR_REG_RTC_I2C_BASE + 0x0064)
-/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command11_done*/
-#define RTC_I2C_COMMAND11_DONE  (BIT(31))
-#define RTC_I2C_COMMAND11_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND11_DONE_V  0x1
-#define RTC_I2C_COMMAND11_DONE_S  31
-/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
-/*description: command11*/
-#define RTC_I2C_COMMAND11  0x00003FFF
-#define RTC_I2C_COMMAND11_M  ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
-#define RTC_I2C_COMMAND11_V  0x3FFF
-#define RTC_I2C_COMMAND11_S  0
-
-#define RTC_I2C_CMD12_REG          (DR_REG_RTC_I2C_BASE + 0x0068)
-/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command12_done*/
-#define RTC_I2C_COMMAND12_DONE  (BIT(31))
-#define RTC_I2C_COMMAND12_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND12_DONE_V  0x1
-#define RTC_I2C_COMMAND12_DONE_S  31
-/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
-/*description: command12*/
-#define RTC_I2C_COMMAND12  0x00003FFF
-#define RTC_I2C_COMMAND12_M  ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
-#define RTC_I2C_COMMAND12_V  0x3FFF
-#define RTC_I2C_COMMAND12_S  0
-
-#define RTC_I2C_CMD13_REG          (DR_REG_RTC_I2C_BASE + 0x006c)
-/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command13_done*/
-#define RTC_I2C_COMMAND13_DONE  (BIT(31))
-#define RTC_I2C_COMMAND13_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND13_DONE_V  0x1
-#define RTC_I2C_COMMAND13_DONE_S  31
-/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
-/*description: command13*/
-#define RTC_I2C_COMMAND13  0x00003FFF
-#define RTC_I2C_COMMAND13_M  ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
-#define RTC_I2C_COMMAND13_V  0x3FFF
-#define RTC_I2C_COMMAND13_S  0
-
-#define RTC_I2C_CMD14_REG          (DR_REG_RTC_I2C_BASE + 0x0070)
-/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command14_done*/
-#define RTC_I2C_COMMAND14_DONE  (BIT(31))
-#define RTC_I2C_COMMAND14_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND14_DONE_V  0x1
-#define RTC_I2C_COMMAND14_DONE_S  31
-/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: command14*/
-#define RTC_I2C_COMMAND14  0x00003FFF
-#define RTC_I2C_COMMAND14_M  ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
-#define RTC_I2C_COMMAND14_V  0x3FFF
-#define RTC_I2C_COMMAND14_S  0
-
-#define RTC_I2C_CMD15_REG          (DR_REG_RTC_I2C_BASE + 0x0074)
-/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: command15_done*/
-#define RTC_I2C_COMMAND15_DONE  (BIT(31))
-#define RTC_I2C_COMMAND15_DONE_M  (BIT(31))
-#define RTC_I2C_COMMAND15_DONE_V  0x1
-#define RTC_I2C_COMMAND15_DONE_S  31
-/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: command15*/
-#define RTC_I2C_COMMAND15  0x00003FFF
-#define RTC_I2C_COMMAND15_M  ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
-#define RTC_I2C_COMMAND15_V  0x3FFF
-#define RTC_I2C_COMMAND15_S  0
-
-#define RTC_I2C_DATE_REG          (DR_REG_RTC_I2C_BASE + 0x00FC)
-/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
-/*description: */
-#define RTC_I2C_DATE  0x0FFFFFFF
-#define RTC_I2C_DATE_M  ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
-#define RTC_I2C_DATE_V  0xFFFFFFF
-#define RTC_I2C_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_RTC_I2C_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/sensitive_reg.h b/components/soc/esp32c3/include/soc/sensitive_reg.h
deleted file mode 100644
index e1ce7d93ef7..00000000000
--- a/components/soc/esp32c3/include/soc/sensitive_reg.h
+++ /dev/null
@@ -1,2304 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SENSITIVE_REG_H_
-#define _SOC_SENSITIVE_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define SENSITIVE_ROM_TABLE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x000)
-/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_ROM_TABLE_LOCK  (BIT(0))
-#define SENSITIVE_ROM_TABLE_LOCK_M  (BIT(0))
-#define SENSITIVE_ROM_TABLE_LOCK_V  0x1
-#define SENSITIVE_ROM_TABLE_LOCK_S  0
-
-#define SENSITIVE_ROM_TABLE_REG          (DR_REG_SENSITIVE_BASE + 0x004)
-/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SENSITIVE_ROM_TABLE  0xFFFFFFFF
-#define SENSITIVE_ROM_TABLE_M  ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S))
-#define SENSITIVE_ROM_TABLE_V  0xFFFFFFFF
-#define SENSITIVE_ROM_TABLE_S  0
-
-#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x008)
-/* SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK  (BIT(0))
-#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M  (BIT(0))
-#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V  0x1
-#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S  0
-
-#define SENSITIVE_PRIVILEGE_MODE_SEL_REG          (DR_REG_SENSITIVE_BASE + 0x00C)
-/* SENSITIVE_PRIVILEGE_MODE_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_PRIVILEGE_MODE_SEL  (BIT(0))
-#define SENSITIVE_PRIVILEGE_MODE_SEL_M  (BIT(0))
-#define SENSITIVE_PRIVILEGE_MODE_SEL_V  0x1
-#define SENSITIVE_PRIVILEGE_MODE_SEL_S  0
-
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x010)
-/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK  (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x1
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S  0
-
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x014)
-/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST  (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x1
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG          (DR_REG_SENSITIVE_BASE + 0x018)
-/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x1
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG          (DR_REG_SENSITIVE_BASE + 0x01C)
-/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: ~3'h0 ; */
-/*description: */
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM  0x00000007
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V  0x7
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S  1
-/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: ~1'h0 ; */
-/*description: */
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V  0x1
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG          (DR_REG_SENSITIVE_BASE + 0x020)
-/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP  (BIT(3))
-#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M  (BIT(3))
-#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V  0x1
-#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S  3
-/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: */
-#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM  0x00000007
-#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V  0x7
-#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG          (DR_REG_SENSITIVE_BASE + 0x024)
-/* SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V  0x1
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S  0
-
-#define SENSITIVE_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x028)
-/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK  (BIT(0))
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x1
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S  0
-
-#define SENSITIVE_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x02C)
-/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_PRO_D_TAG_WR_ACS  (BIT(3))
-#define SENSITIVE_PRO_D_TAG_WR_ACS_M  (BIT(3))
-#define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x1
-#define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
-/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_PRO_D_TAG_RD_ACS  (BIT(2))
-#define SENSITIVE_PRO_D_TAG_RD_ACS_M  (BIT(2))
-#define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x1
-#define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
-/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_PRO_I_TAG_WR_ACS  (BIT(1))
-#define SENSITIVE_PRO_I_TAG_WR_ACS_M  (BIT(1))
-#define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x1
-#define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
-/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_PRO_I_TAG_RD_ACS  (BIT(0))
-#define SENSITIVE_PRO_I_TAG_RD_ACS_M  (BIT(0))
-#define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x1
-#define SENSITIVE_PRO_I_TAG_RD_ACS_S  0
-
-#define SENSITIVE_CACHE_MMU_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x030)
-/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK  (BIT(0))
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x1
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S  0
-
-#define SENSITIVE_CACHE_MMU_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x034)
-/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SENSITIVE_PRO_MMU_WR_ACS  (BIT(1))
-#define SENSITIVE_PRO_MMU_WR_ACS_M  (BIT(1))
-#define SENSITIVE_PRO_MMU_WR_ACS_V  0x1
-#define SENSITIVE_PRO_MMU_WR_ACS_S  1
-/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SENSITIVE_PRO_MMU_RD_ACS  (BIT(0))
-#define SENSITIVE_PRO_MMU_RD_ACS_M  (BIT(0))
-#define SENSITIVE_PRO_MMU_RD_ACS_V  0x1
-#define SENSITIVE_PRO_MMU_RD_ACS_S  0
-
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x038)
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x03C)
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x040)
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x044)
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x048)
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x04C)
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x050)
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x054)
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x058)
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x05C)
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x060)
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x064)
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x068)
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x06C)
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x070)
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x074)
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x078)
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x07C)
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x080)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x084)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN  (BIT(1))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x088)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[26:3] ;default: 24'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  3
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x08C)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN  0x0000000F
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x090)
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x094)
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR  0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x098)
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR  0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x09C)
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR  0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0  0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x0A0)
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR  0x000000FF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x0A4)
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR  0x000000FF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0A8)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0AC)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  18
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  12
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  9
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  6
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  3
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x0B0)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  18
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  12
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  9
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  6
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  3
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x0B4)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x0B8)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN  (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x0BC)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE  (BIT(2))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0C0)
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0C4)
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  26
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  24
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x0C8)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x0CC)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN  (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x0D0)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[27:4] ;default: 24'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK  (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x0D4)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN  0x0000000F
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0D8)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0DC)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x0E0)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x0E4)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x0E8)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x0EC)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x0F0)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x0F4)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x0F8)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x0FC)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1  0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0  0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x100)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H  0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L  0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H  0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L  0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x104)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x108)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x10C)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0  0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x110)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x114)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x118)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x11C)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x120)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x124)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x128)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S  0
-
-#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x12C)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: */
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x130)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x134)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x138)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE  (BIT(5))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE  0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x13C)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR  0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x140)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x144)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x148)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR  0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x14C)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x150)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S  30
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S  24
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S  18
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S  12
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S  8
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S  2
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x154)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S  30
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S  28
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S  22
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x158)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S  28
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S  22
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x15C)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S  12
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S  8
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S  2
-
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x160)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x164)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN  (BIT(1))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x168)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE  (BIT(6))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(6))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE  0x00000007
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  3
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S  1
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x16C)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR  0xFFFFFFFF
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V  0xFFFFFFFF
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S  0
-
-#define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x170)
-/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SENSITIVE_CLK_EN  (BIT(0))
-#define SENSITIVE_CLK_EN_M  (BIT(0))
-#define SENSITIVE_CLK_EN_V  0x1
-#define SENSITIVE_CLK_EN_S  0
-
-#define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
-/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010200 ; */
-/*description: */
-#define SENSITIVE_DATE  0x0FFFFFFF
-#define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
-#define SENSITIVE_DATE_V  0xFFFFFFF
-#define SENSITIVE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SENSITIVE_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/sensitive_struct.h b/components/soc/esp32c3/include/soc/sensitive_struct.h
deleted file mode 100644
index ba860e45cd7..00000000000
--- a/components/soc/esp32c3/include/soc/sensitive_struct.h
+++ /dev/null
@@ -1,1911 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SENSITIVE_STRUCT_H_
-#define _SOC_SENSITIVE_STRUCT_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-typedef volatile struct sensitive_dev_s {
-    union {
-        struct {
-            uint32_t reg_rom_table_lock            :    1;  /*rom_table_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } rom_table_lock;
-    uint32_t rom_table;
-    union {
-        struct {
-            uint32_t reg_privilege_mode_sel_lock   :    1;  /*privilege_mode_sel_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } privilege_mode_sel_lock;
-    union {
-        struct {
-            uint32_t reg_privilege_mode_sel        :    1;  /*privilege_mode_sel*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } privilege_mode_sel;
-    union {
-        struct {
-            uint32_t reg_apb_peripheral_access_lock:    1;  /*apb_peripheral_access_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } apb_peripheral_access_0;
-    union {
-        struct {
-            uint32_t reg_apb_peripheral_access_split_burst:    1;  /*apb_peripheral_access_split_burst*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } apb_peripheral_access_1;
-    union {
-        struct {
-            uint32_t reg_internal_sram_usage_lock  :    1;  /*internal_sram_usage_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } internal_sram_usage_0;
-    union {
-        struct {
-            uint32_t reg_internal_sram_usage_cpu_cache:    1;  /*internal_sram_usage_cpu_cache*/
-            uint32_t reg_internal_sram_usage_cpu_sram:    3;  /*internal_sram_usage_cpu_sram*/
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } internal_sram_usage_1;
-    union {
-        struct {
-            uint32_t reg_internal_sram_usage_mac_dump_sram:    3;  /*internal_sram_usage_mac_dump_sram*/
-            uint32_t reg_internal_sram_alloc_mac_dump:    1;  /*internal_sram_alloc_mac_dump*/
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } internal_sram_usage_3;
-    union {
-        struct {
-            uint32_t reg_internal_sram_usage_log_sram:    1;  /*internal_sram_usage_log_sram*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } internal_sram_usage_4;
-    union {
-        struct {
-            uint32_t reg_cache_tag_access_lock     :    1;  /*cache_tag_access_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cache_tag_access_0;
-    union {
-        struct {
-            uint32_t reg_pro_i_tag_rd_acs          :    1;  /*pro_i_tag_rd_acs*/
-            uint32_t reg_pro_i_tag_wr_acs          :    1;  /*pro_i_tag_wr_acs*/
-            uint32_t reg_pro_d_tag_rd_acs          :    1;  /*pro_d_tag_rd_acs*/
-            uint32_t reg_pro_d_tag_wr_acs          :    1;  /*pro_d_tag_wr_acs*/
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } cache_tag_access_1;
-    union {
-        struct {
-            uint32_t reg_cache_mmu_access_lock     :    1;  /*cache_mmu_access_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cache_mmu_access_0;
-    union {
-        struct {
-            uint32_t reg_pro_mmu_rd_acs            :    1;  /*pro_mmu_rd_acs*/
-            uint32_t reg_pro_mmu_wr_acs            :    1;  /*pro_mmu_wr_acs*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } cache_mmu_access_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_lock:    1;  /*dma_apbperi_spi2_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_spi2_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_spi2_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_lock:    1;  /*dma_apbperi_uchi0_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_uchi0_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_uchi0_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_lock:    1;  /*dma_apbperi_i2s0_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_i2s0_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_i2s0_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_mac_pms_constrain_lock:    1;  /*dma_apbperi_mac_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_mac_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_mac_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_backup_pms_constrain_lock:    1;  /*dma_apbperi_backup_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_backup_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_backup_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_lc_pms_constrain_lock:    1;  /*dma_apbperi_lc_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_lc_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_lc_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_aes_pms_constrain_lock:    1;  /*dma_apbperi_aes_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_aes_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_aes_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_sha_pms_constrain_lock:    1;  /*dma_apbperi_sha_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_sha_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_sha_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_lock:    1;  /*dma_apbperi_adc_dac_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_adc_dac_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } dma_apbperi_adc_dac_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_pms_monitor_lock:    1;  /*dma_apbperi_pms_monitor_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_pms_monitor_0;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_pms_monitor_violate_clr:    1;  /*dma_apbperi_pms_monitor_violate_clr*/
-            uint32_t reg_dma_apbperi_pms_monitor_violate_en:    1;  /*dma_apbperi_pms_monitor_violate_en*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } dma_apbperi_pms_monitor_1;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_pms_monitor_violate_intr:    1;  /*dma_apbperi_pms_monitor_violate_intr*/
-            uint32_t reg_dma_apbperi_pms_monitor_violate_status_world:    2;  /*dma_apbperi_pms_monitor_violate_status_world*/
-            uint32_t reg_dma_apbperi_pms_monitor_violate_status_addr:    24;  /*dma_apbperi_pms_monitor_violate_status_addr*/
-            uint32_t reserved27                    :    5;
-        };
-        uint32_t val;
-    } dma_apbperi_pms_monitor_2;
-    union {
-        struct {
-            uint32_t reg_dma_apbperi_pms_monitor_violate_status_wr:    1;  /*dma_apbperi_pms_monitor_violate_status_wr*/
-            uint32_t reg_dma_apbperi_pms_monitor_violate_status_byteen:    4;  /*dma_apbperi_pms_monitor_violate_status_byteen*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } dma_apbperi_pms_monitor_3;
-    union {
-        struct {
-            uint32_t reg_core_x_iram0_dram0_dma_split_line_constrain_lock:    1;  /*core_x_iram0_dram0_dma_split_line_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_0;
-    union {
-        struct {
-            uint32_t reg_core_x_iram0_dram0_dma_sram_category_0:    2;  /*core_x_iram0_dram0_dma_sram_category_0*/
-            uint32_t reg_core_x_iram0_dram0_dma_sram_category_1:    2;  /*core_x_iram0_dram0_dma_sram_category_1*/
-            uint32_t reg_core_x_iram0_dram0_dma_sram_category_2:    2;  /*core_x_iram0_dram0_dma_sram_category_2*/
-            uint32_t reserved6                     :    8;
-            uint32_t reg_core_x_iram0_dram0_dma_sram_splitaddr:    8;  /*core_x_iram0_dram0_dma_sram_splitaddr*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_1;
-    union {
-        struct {
-            uint32_t reg_core_x_iram0_sram_line_0_category_0:    2;  /*core_x_iram0_sram_line_0_category_0*/
-            uint32_t reg_core_x_iram0_sram_line_0_category_1:    2;  /*core_x_iram0_sram_line_0_category_1*/
-            uint32_t reg_core_x_iram0_sram_line_0_category_2:    2;  /*core_x_iram0_sram_line_0_category_2*/
-            uint32_t reserved6                     :    8;
-            uint32_t reg_core_x_iram0_sram_line_0_splitaddr:    8;  /*core_x_iram0_sram_line_0_splitaddr*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_2;
-    union {
-        struct {
-            uint32_t reg_core_x_iram0_sram_line_1_category_0:    2;  /*core_x_iram0_sram_line_1_category_0*/
-            uint32_t reg_core_x_iram0_sram_line_1_category_1:    2;  /*core_x_iram0_sram_line_1_category_1*/
-            uint32_t reg_core_x_iram0_sram_line_1_category_2:    2;  /*core_x_iram0_sram_line_1_category_2*/
-            uint32_t reserved6                     :    8;
-            uint32_t reg_core_x_iram0_sram_line_1_splitaddr:    8;  /*core_x_iram0_sram_line_1_splitaddr*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_3;
-    union {
-        struct {
-            uint32_t reg_core_x_dram0_dma_sram_line_0_category_0:    2;  /*core_x_dram0_dma_sram_line_0_category_0*/
-            uint32_t reg_core_x_dram0_dma_sram_line_0_category_1:    2;  /*core_x_dram0_dma_sram_line_0_category_1*/
-            uint32_t reg_core_x_dram0_dma_sram_line_0_category_2:    2;  /*core_x_dram0_dma_sram_line_0_category_2*/
-            uint32_t reserved6                     :    8;
-            uint32_t reg_core_x_dram0_dma_sram_line_0_splitaddr:    8;  /*core_x_dram0_dma_sram_line_0_splitaddr*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_4;
-    union {
-        struct {
-            uint32_t reg_core_x_dram0_dma_sram_line_1_category_0:    2;  /*core_x_dram0_dma_sram_line_1_category_0*/
-            uint32_t reg_core_x_dram0_dma_sram_line_1_category_1:    2;  /*core_x_dram0_dma_sram_line_1_category_1*/
-            uint32_t reg_core_x_dram0_dma_sram_line_1_category_2:    2;  /*core_x_dram0_dma_sram_line_1_category_2*/
-            uint32_t reserved6                     :    8;
-            uint32_t reg_core_x_dram0_dma_sram_line_1_splitaddr:    8;  /*core_x_dram0_dma_sram_line_1_splitaddr*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_5;
-    union {
-        struct {
-            uint32_t reg_core_x_iram0_pms_constrain_lock:    1;  /*core_x_iram0_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_x_iram0_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_1:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_2:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_3:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0*/
-            uint32_t reserved15                    :    3;
-            uint32_t reg_core_x_iram0_pms_constrain_rom_world_1_pms:    3;  /*core_x_iram0_pms_constrain_rom_world_1_pms*/
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } core_x_iram0_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_1:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_2:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_3:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0*/
-            uint32_t reserved15                    :    3;
-            uint32_t reg_core_x_iram0_pms_constrain_rom_world_0_pms:    3;  /*core_x_iram0_pms_constrain_rom_world_0_pms*/
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } core_x_iram0_pms_constrain_2;
-    union {
-        struct {
-            uint32_t reg_core_0_iram0_pms_monitor_lock:    1;  /*core_0_iram0_pms_monitor_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_iram0_pms_monitor_0;
-    union {
-        struct {
-            uint32_t reg_core_0_iram0_pms_monitor_violate_clr:    1;  /*core_0_iram0_pms_monitor_violate_clr*/
-            uint32_t reg_core_0_iram0_pms_monitor_violate_en:    1;  /*core_0_iram0_pms_monitor_violate_en*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_0_iram0_pms_monitor_1;
-    union {
-        struct {
-            uint32_t reg_core_0_iram0_pms_monitor_violate_intr:    1;  /*core_0_iram0_pms_monitor_violate_intr*/
-            uint32_t reg_core_0_iram0_pms_monitor_violate_status_wr:    1;  /*core_0_iram0_pms_monitor_violate_status_wr*/
-            uint32_t reg_core_0_iram0_pms_monitor_violate_status_loadstore:    1;  /*core_0_iram0_pms_monitor_violate_status_loadstore*/
-            uint32_t reg_core_0_iram0_pms_monitor_violate_status_world:    2;  /*core_0_iram0_pms_monitor_violate_status_world*/
-            uint32_t reg_core_0_iram0_pms_monitor_violate_status_addr:    24;  /*core_0_iram0_pms_monitor_violate_status_addr*/
-            uint32_t reserved29                    :    3;
-        };
-        uint32_t val;
-    } core_0_iram0_pms_monitor_2;
-    union {
-        struct {
-            uint32_t reg_core_x_dram0_pms_constrain_lock:    1;  /*core_x_dram0_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_x_dram0_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_0:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_0*/
-            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_1:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_1*/
-            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_2:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_2*/
-            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_3:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_3*/
-            uint32_t reserved8                     :    4;
-            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_0:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_0*/
-            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_1:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_1*/
-            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_2:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_2*/
-            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_3:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_3*/
-            uint32_t reserved20                    :    4;
-            uint32_t reg_core_x_dram0_pms_constrain_rom_world_0_pms:    2;  /*core_x_dram0_pms_constrain_rom_world_0_pms*/
-            uint32_t reg_core_x_dram0_pms_constrain_rom_world_1_pms:    2;  /*core_x_dram0_pms_constrain_rom_world_1_pms*/
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } core_x_dram0_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_core_0_dram0_pms_monitor_lock:    1;  /*core_0_dram0_pms_monitor_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_dram0_pms_monitor_0;
-    union {
-        struct {
-            uint32_t reg_core_0_dram0_pms_monitor_violate_clr:    1;  /*core_0_dram0_pms_monitor_violate_clr*/
-            uint32_t reg_core_0_dram0_pms_monitor_violate_en:    1;  /*core_0_dram0_pms_monitor_violate_en*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_0_dram0_pms_monitor_1;
-    union {
-        struct {
-            uint32_t reg_core_0_dram0_pms_monitor_violate_intr:    1;  /*core_0_dram0_pms_monitor_violate_intr*/
-            uint32_t reg_core_0_dram0_pms_monitor_violate_status_lock:    1;  /*core_0_dram0_pms_monitor_violate_status_lock*/
-            uint32_t reg_core_0_dram0_pms_monitor_violate_status_world:    2;  /*core_0_dram0_pms_monitor_violate_status_world*/
-            uint32_t reg_core_0_dram0_pms_monitor_violate_status_addr:    24;  /*core_0_dram0_pms_monitor_violate_status_addr*/
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } core_0_dram0_pms_monitor_2;
-    union {
-        struct {
-            uint32_t reg_core_0_dram0_pms_monitor_violate_status_wr:    1;  /*core_0_dram0_pms_monitor_violate_status_wr*/
-            uint32_t reg_core_0_dram0_pms_monitor_violate_status_byteen:    4;  /*core_0_dram0_pms_monitor_violate_status_byteen*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core_0_dram0_pms_monitor_3;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_lock:    1;  /*core_0_pif_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_world_0_uart:    2;  /*core_0_pif_pms_constrain_world_0_uart*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_1:    2;  /*core_0_pif_pms_constrain_world_0_g0spi_1*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_0:    2;  /*core_0_pif_pms_constrain_world_0_g0spi_0*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_gpio:    2;  /*core_0_pif_pms_constrain_world_0_gpio*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_fe2:    2;  /*core_0_pif_pms_constrain_world_0_fe2*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_fe:    2;  /*core_0_pif_pms_constrain_world_0_fe*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_timer:    2;  /*core_0_pif_pms_constrain_world_0_timer*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_rtc:    2;  /*core_0_pif_pms_constrain_world_0_rtc*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_io_mux:    2;  /*core_0_pif_pms_constrain_world_0_io_mux*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_wdg:    2;  /*core_0_pif_pms_constrain_world_0_wdg*/
-            uint32_t reserved20                    :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_misc:    2;  /*core_0_pif_pms_constrain_world_0_misc*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_i2c:    2;  /*core_0_pif_pms_constrain_world_0_i2c*/
-            uint32_t reserved28                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_uart1:    2;  /*core_0_pif_pms_constrain_world_0_uart1*/
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_world_0_bt:    2;  /*core_0_pif_pms_constrain_world_0_bt*/
-            uint32_t reserved2                     :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_i2c_ext0:    2;  /*core_0_pif_pms_constrain_world_0_i2c_ext0*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_uhci0:    2;  /*core_0_pif_pms_constrain_world_0_uhci0*/
-            uint32_t reserved8                     :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_rmt:    2;  /*core_0_pif_pms_constrain_world_0_rmt*/
-            uint32_t reserved12                    :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_ledc:    2;  /*core_0_pif_pms_constrain_world_0_ledc*/
-            uint32_t reserved18                    :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_bb:    2;  /*core_0_pif_pms_constrain_world_0_bb*/
-            uint32_t reserved24                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup:    2;  /*core_0_pif_pms_constrain_world_0_timergroup*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1:    2;  /*core_0_pif_pms_constrain_world_0_timergroup1*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_systimer:    2;  /*core_0_pif_pms_constrain_world_0_systimer*/
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_2;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_world_0_spi_2:    2;  /*core_0_pif_pms_constrain_world_0_spi_2*/
-            uint32_t reserved2                     :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_apb_ctrl:    2;  /*core_0_pif_pms_constrain_world_0_apb_ctrl*/
-            uint32_t reserved6                     :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_can:    2;  /*core_0_pif_pms_constrain_world_0_can*/
-            uint32_t reserved12                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_i2s1:    2;  /*core_0_pif_pms_constrain_world_0_i2s1*/
-            uint32_t reserved16                    :    6;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt:    2;  /*core_0_pif_pms_constrain_world_0_rwbt*/
-            uint32_t reserved24                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_wifimac:    2;  /*core_0_pif_pms_constrain_world_0_wifimac*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_pwr:    2;  /*core_0_pif_pms_constrain_world_0_pwr*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_3;
-    union {
-        struct {
-            uint32_t reserved0                     :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_usb_wrap:    2;  /*core_0_pif_pms_constrain_world_0_usb_wrap*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_peri:    2;  /*core_0_pif_pms_constrain_world_0_crypto_peri*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_dma:    2;  /*core_0_pif_pms_constrain_world_0_crypto_dma*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_apb_adc:    2;  /*core_0_pif_pms_constrain_world_0_apb_adc*/
-            uint32_t reserved10                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_bt_pwr:    2;  /*core_0_pif_pms_constrain_world_0_bt_pwr*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_usb_device:    2;  /*core_0_pif_pms_constrain_world_0_usb_device*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_system:    2;  /*core_0_pif_pms_constrain_world_0_system*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive:    2;  /*core_0_pif_pms_constrain_world_0_sensitive*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt:    2;  /*core_0_pif_pms_constrain_world_0_interrupt*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy:    2;  /*core_0_pif_pms_constrain_world_0_dma_copy*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config:    2;  /*core_0_pif_pms_constrain_world_0_cache_config*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_ad:    2;  /*core_0_pif_pms_constrain_world_0_ad*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_dio:    2;  /*core_0_pif_pms_constrain_world_0_dio*/
-            uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller:    2;  /*core_0_pif_pms_constrain_world_0_world_controller*/
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_4;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_world_1_uart:    2;  /*core_0_pif_pms_constrain_world_1_uart*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1:    2;  /*core_0_pif_pms_constrain_world_1_g0spi_1*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0:    2;  /*core_0_pif_pms_constrain_world_1_g0spi_0*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_gpio:    2;  /*core_0_pif_pms_constrain_world_1_gpio*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_fe2:    2;  /*core_0_pif_pms_constrain_world_1_fe2*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_fe:    2;  /*core_0_pif_pms_constrain_world_1_fe*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_timer:    2;  /*core_0_pif_pms_constrain_world_1_timer*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_rtc:    2;  /*core_0_pif_pms_constrain_world_1_rtc*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux:    2;  /*core_0_pif_pms_constrain_world_1_io_mux*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_wdg:    2;  /*core_0_pif_pms_constrain_world_1_wdg*/
-            uint32_t reserved20                    :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_misc:    2;  /*core_0_pif_pms_constrain_world_1_misc*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_i2c:    2;  /*core_0_pif_pms_constrain_world_1_i2c*/
-            uint32_t reserved28                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_uart1:    2;  /*core_0_pif_pms_constrain_world_1_uart1*/
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_5;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_world_1_bt:    2;  /*core_0_pif_pms_constrain_world_1_bt*/
-            uint32_t reserved2                     :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0:    2;  /*core_0_pif_pms_constrain_world_1_i2c_ext0*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0:    2;  /*core_0_pif_pms_constrain_world_1_uhci0*/
-            uint32_t reserved8                     :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_rmt:    2;  /*core_0_pif_pms_constrain_world_1_rmt*/
-            uint32_t reserved12                    :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_ledc:    2;  /*core_0_pif_pms_constrain_world_1_ledc*/
-            uint32_t reserved18                    :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_bb:    2;  /*core_0_pif_pms_constrain_world_1_bb*/
-            uint32_t reserved24                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup:    2;  /*core_0_pif_pms_constrain_world_1_timergroup*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1:    2;  /*core_0_pif_pms_constrain_world_1_timergroup1*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_systimer:    2;  /*core_0_pif_pms_constrain_world_1_systimer*/
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_6;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2:    2;  /*core_0_pif_pms_constrain_world_1_spi_2*/
-            uint32_t reserved2                     :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl:    2;  /*core_0_pif_pms_constrain_world_1_apb_ctrl*/
-            uint32_t reserved6                     :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_can:    2;  /*core_0_pif_pms_constrain_world_1_can*/
-            uint32_t reserved12                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1:    2;  /*core_0_pif_pms_constrain_world_1_i2s1*/
-            uint32_t reserved16                    :    6;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt:    2;  /*core_0_pif_pms_constrain_world_1_rwbt*/
-            uint32_t reserved24                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_wifimac:    2;  /*core_0_pif_pms_constrain_world_1_wifimac*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_pwr:    2;  /*core_0_pif_pms_constrain_world_1_pwr*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_7;
-    union {
-        struct {
-            uint32_t reserved0                     :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_usb_wrap:    2;  /*core_0_pif_pms_constrain_world_1_usb_wrap*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri:    2;  /*core_0_pif_pms_constrain_world_1_crypto_peri*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma:    2;  /*core_0_pif_pms_constrain_world_1_crypto_dma*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc:    2;  /*core_0_pif_pms_constrain_world_1_apb_adc*/
-            uint32_t reserved10                    :    2;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_bt_pwr:    2;  /*core_0_pif_pms_constrain_world_1_bt_pwr*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device:    2;  /*core_0_pif_pms_constrain_world_1_usb_device*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_system:    2;  /*core_0_pif_pms_constrain_world_1_system*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive:    2;  /*core_0_pif_pms_constrain_world_1_sensitive*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt:    2;  /*core_0_pif_pms_constrain_world_1_interrupt*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy:    2;  /*core_0_pif_pms_constrain_world_1_dma_copy*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config:    2;  /*core_0_pif_pms_constrain_world_1_cache_config*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_ad:    2;  /*core_0_pif_pms_constrain_world_1_ad*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_dio:    2;  /*core_0_pif_pms_constrain_world_1_dio*/
-            uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller:    2;  /*core_0_pif_pms_constrain_world_1_world_controller*/
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_8;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:    11;  /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_0*/
-            uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_1:    11;  /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_1*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_9;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l:    3;  /*core_0_pif_pms_constrain_rtcfast_world_0_l*/
-            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h:    3;  /*core_0_pif_pms_constrain_rtcfast_world_0_h*/
-            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l:    3;  /*core_0_pif_pms_constrain_rtcfast_world_1_l*/
-            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h:    3;  /*core_0_pif_pms_constrain_rtcfast_world_1_h*/
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_10;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_lock :    1;  /*region_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_world_0_area_0:    2;  /*region_pms_constrain_world_0_area_0*/
-            uint32_t reg_region_pms_constrain_world_0_area_1:    2;  /*region_pms_constrain_world_0_area_1*/
-            uint32_t reg_region_pms_constrain_world_0_area_2:    2;  /*region_pms_constrain_world_0_area_2*/
-            uint32_t reg_region_pms_constrain_world_0_area_3:    2;  /*region_pms_constrain_world_0_area_3*/
-            uint32_t reg_region_pms_constrain_world_0_area_4:    2;  /*region_pms_constrain_world_0_area_4*/
-            uint32_t reg_region_pms_constrain_world_0_area_5:    2;  /*region_pms_constrain_world_0_area_5*/
-            uint32_t reg_region_pms_constrain_world_0_area_6:    2;  /*region_pms_constrain_world_0_area_6*/
-            uint32_t reserved14                    :    18;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_world_1_area_0:    2;  /*region_pms_constrain_world_1_area_0*/
-            uint32_t reg_region_pms_constrain_world_1_area_1:    2;  /*region_pms_constrain_world_1_area_1*/
-            uint32_t reg_region_pms_constrain_world_1_area_2:    2;  /*region_pms_constrain_world_1_area_2*/
-            uint32_t reg_region_pms_constrain_world_1_area_3:    2;  /*region_pms_constrain_world_1_area_3*/
-            uint32_t reg_region_pms_constrain_world_1_area_4:    2;  /*region_pms_constrain_world_1_area_4*/
-            uint32_t reg_region_pms_constrain_world_1_area_5:    2;  /*region_pms_constrain_world_1_area_5*/
-            uint32_t reg_region_pms_constrain_world_1_area_6:    2;  /*region_pms_constrain_world_1_area_6*/
-            uint32_t reserved14                    :    18;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_2;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_addr_0:    30;  /*region_pms_constrain_addr_0*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_3;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_addr_1:    30;  /*region_pms_constrain_addr_1*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_4;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_addr_2:    30;  /*region_pms_constrain_addr_2*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_5;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_addr_3:    30;  /*region_pms_constrain_addr_3*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_6;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_addr_4:    30;  /*region_pms_constrain_addr_4*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_7;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_addr_5:    30;  /*region_pms_constrain_addr_5*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_8;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_addr_6:    30;  /*region_pms_constrain_addr_6*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_9;
-    union {
-        struct {
-            uint32_t reg_region_pms_constrain_addr_7:    30;  /*region_pms_constrain_addr_7*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } sensitiveion_pms_constrain_10;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_monitor_lock:    1;  /*core_0_pif_pms_monitor_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_0;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_monitor_violate_clr:    1;  /*core_0_pif_pms_monitor_violate_clr*/
-            uint32_t reg_core_0_pif_pms_monitor_violate_en:    1;  /*core_0_pif_pms_monitor_violate_en*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_1;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_monitor_violate_intr:    1;  /*core_0_pif_pms_monitor_violate_intr*/
-            uint32_t reg_core_0_pif_pms_monitor_violate_status_hport_0:    1;  /*core_0_pif_pms_monitor_violate_status_hport_0*/
-            uint32_t reg_core_0_pif_pms_monitor_violate_status_hsize:    3;  /*core_0_pif_pms_monitor_violate_status_hsize*/
-            uint32_t reg_core_0_pif_pms_monitor_violate_status_hwrite:    1;  /*core_0_pif_pms_monitor_violate_status_hwrite*/
-            uint32_t reg_core_0_pif_pms_monitor_violate_status_hworld:    2;  /*core_0_pif_pms_monitor_violate_status_hworld*/
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_2;
-    uint32_t core_0_pif_pms_monitor_3;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_clr:    1;  /*core_0_pif_pms_monitor_nonword_violate_clr*/
-            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_en:    1;  /*core_0_pif_pms_monitor_nonword_violate_en*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_4;
-    union {
-        struct {
-            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_intr:    1;  /*core_0_pif_pms_monitor_nonword_violate_intr*/
-            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hsize:    2;  /*core_0_pif_pms_monitor_nonword_violate_status_hsize*/
-            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hworld:    2;  /*core_0_pif_pms_monitor_nonword_violate_status_hworld*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_5;
-    uint32_t core_0_pif_pms_monitor_6;
-    union {
-        struct {
-            uint32_t reg_backup_bus_pms_constrain_lock:    1;  /*backup_bus_pms_constrain_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_0;
-    union {
-        struct {
-            uint32_t reg_backup_bus_pms_constrain_uart:    2;  /*backup_bus_pms_constrain_uart*/
-            uint32_t reg_backup_bus_pms_constrain_g0spi_1:    2;  /*backup_bus_pms_constrain_g0spi_1*/
-            uint32_t reg_backup_bus_pms_constrain_g0spi_0:    2;  /*backup_bus_pms_constrain_g0spi_0*/
-            uint32_t reg_backup_bus_pms_constrain_gpio:    2;  /*backup_bus_pms_constrain_gpio*/
-            uint32_t reg_backup_bus_pms_constrain_fe2:    2;  /*backup_bus_pms_constrain_fe2*/
-            uint32_t reg_backup_bus_pms_constrain_fe:    2;  /*backup_bus_pms_constrain_fe*/
-            uint32_t reg_backup_bus_pms_constrain_timer:    2;  /*backup_bus_pms_constrain_timer*/
-            uint32_t reg_backup_bus_pms_constrain_rtc:    2;  /*backup_bus_pms_constrain_rtc*/
-            uint32_t reg_backup_bus_pms_constrain_io_mux:    2;  /*backup_bus_pms_constrain_io_mux*/
-            uint32_t reg_backup_bus_pms_constrain_wdg:    2;  /*backup_bus_pms_constrain_wdg*/
-            uint32_t reserved20                    :    4;
-            uint32_t reg_backup_bus_pms_constrain_misc:    2;  /*backup_bus_pms_constrain_misc*/
-            uint32_t reg_backup_bus_pms_constrain_i2c:    2;  /*backup_bus_pms_constrain_i2c*/
-            uint32_t reserved28                    :    2;
-            uint32_t reg_backup_bus_pms_constrain_uart1:    2;  /*backup_bus_pms_constrain_uart1*/
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_1;
-    union {
-        struct {
-            uint32_t reg_backup_bus_pms_constrain_bt:    2;  /*backup_bus_pms_constrain_bt*/
-            uint32_t reserved2                     :    2;
-            uint32_t reg_backup_bus_pms_constrain_i2c_ext0:    2;  /*backup_bus_pms_constrain_i2c_ext0*/
-            uint32_t reg_backup_bus_pms_constrain_uhci0:    2;  /*backup_bus_pms_constrain_uhci0*/
-            uint32_t reserved8                     :    2;
-            uint32_t reg_backup_bus_pms_constrain_rmt:    2;  /*backup_bus_pms_constrain_rmt*/
-            uint32_t reserved12                    :    4;
-            uint32_t reg_backup_bus_pms_constrain_ledc:    2;  /*backup_bus_pms_constrain_ledc*/
-            uint32_t reserved18                    :    4;
-            uint32_t reg_backup_bus_pms_constrain_bb:    2;  /*backup_bus_pms_constrain_bb*/
-            uint32_t reserved24                    :    2;
-            uint32_t reg_backup_bus_pms_constrain_timergroup:    2;  /*backup_bus_pms_constrain_timergroup*/
-            uint32_t reg_backup_bus_pms_constrain_timergroup1:    2;  /*backup_bus_pms_constrain_timergroup1*/
-            uint32_t reg_backup_bus_pms_constrain_systimer:    2;  /*backup_bus_pms_constrain_systimer*/
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_2;
-    union {
-        struct {
-            uint32_t reg_backup_bus_pms_constrain_spi_2:    2;  /*backup_bus_pms_constrain_spi_2*/
-            uint32_t reserved2                     :    2;
-            uint32_t reg_backup_bus_pms_constrain_apb_ctrl:    2;  /*backup_bus_pms_constrain_apb_ctrl*/
-            uint32_t reserved6                     :    4;
-            uint32_t reg_backup_bus_pms_constrain_can:    2;  /*backup_bus_pms_constrain_can*/
-            uint32_t reserved12                    :    2;
-            uint32_t reg_backup_bus_pms_constrain_i2s1:    2;  /*backup_bus_pms_constrain_i2s1*/
-            uint32_t reserved16                    :    6;
-            uint32_t reg_backup_bus_pms_constrain_rwbt:    2;  /*backup_bus_pms_constrain_rwbt*/
-            uint32_t reserved24                    :    2;
-            uint32_t reg_backup_bus_pms_constrain_wifimac:    2;  /*backup_bus_pms_constrain_wifimac*/
-            uint32_t reg_backup_bus_pms_constrain_pwr:    2;  /*backup_bus_pms_constrain_pwr*/
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_3;
-    union {
-        struct {
-            uint32_t reserved0                     :    2;
-            uint32_t reg_backup_bus_pms_constrain_usb_wrap:    2;  /*backup_bus_pms_constrain_usb_wrap*/
-            uint32_t reg_backup_bus_pms_constrain_crypto_peri:    2;  /*backup_bus_pms_constrain_crypto_peri*/
-            uint32_t reg_backup_bus_pms_constrain_crypto_dma:    2;  /*backup_bus_pms_constrain_crypto_dma*/
-            uint32_t reg_backup_bus_pms_constrain_apb_adc:    2;  /*backup_bus_pms_constrain_apb_adc*/
-            uint32_t reserved10                    :    2;
-            uint32_t reg_backup_bus_pms_constrain_bt_pwr:    2;  /*backup_bus_pms_constrain_bt_pwr*/
-            uint32_t reg_backup_bus_pms_constrain_usb_device:    2;  /*backup_bus_pms_constrain_usb_device*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_4;
-    union {
-        struct {
-            uint32_t reg_backup_bus_pms_monitor_lock:    1;  /*backup_bus_pms_monitor_lock*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } backup_bus_pms_monitor_0;
-    union {
-        struct {
-            uint32_t reg_backup_bus_pms_monitor_violate_clr:    1;  /*backup_bus_pms_monitor_violate_clr*/
-            uint32_t reg_backup_bus_pms_monitor_violate_en:    1;  /*backup_bus_pms_monitor_violate_en*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } backup_bus_pms_monitor_1;
-    union {
-        struct {
-            uint32_t reg_backup_bus_pms_monitor_violate_intr:    1;  /*backup_bus_pms_monitor_violate_intr*/
-            uint32_t reg_backup_bus_pms_monitor_violate_status_htrans:    2;  /*backup_bus_pms_monitor_violate_status_htrans*/
-            uint32_t reg_backup_bus_pms_monitor_violate_status_hsize:    3;  /*backup_bus_pms_monitor_violate_status_hsize*/
-            uint32_t reg_backup_bus_pms_monitor_violate_status_hwrite:    1;  /*backup_bus_pms_monitor_violate_status_hwrite*/
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } backup_bus_pms_monitor_2;
-    uint32_t backup_bus_pms_monitor_3;
-    union {
-        struct {
-            uint32_t reg_clk_en                    :    1;  /*clk_en*/
-            uint32_t reserved1                     :    31;  /*SENSITIVE_CLOCK_GATE_REG_REG*/
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    uint32_t reserved_3fc;
-    uint32_t reserved_400;
-    uint32_t reserved_404;
-    uint32_t reserved_408;
-    uint32_t reserved_40c;
-    uint32_t reserved_410;
-    uint32_t reserved_414;
-    uint32_t reserved_418;
-    uint32_t reserved_41c;
-    uint32_t reserved_420;
-    uint32_t reserved_424;
-    uint32_t reserved_428;
-    uint32_t reserved_42c;
-    uint32_t reserved_430;
-    uint32_t reserved_434;
-    uint32_t reserved_438;
-    uint32_t reserved_43c;
-    uint32_t reserved_440;
-    uint32_t reserved_444;
-    uint32_t reserved_448;
-    uint32_t reserved_44c;
-    uint32_t reserved_450;
-    uint32_t reserved_454;
-    uint32_t reserved_458;
-    uint32_t reserved_45c;
-    uint32_t reserved_460;
-    uint32_t reserved_464;
-    uint32_t reserved_468;
-    uint32_t reserved_46c;
-    uint32_t reserved_470;
-    uint32_t reserved_474;
-    uint32_t reserved_478;
-    uint32_t reserved_47c;
-    uint32_t reserved_480;
-    uint32_t reserved_484;
-    uint32_t reserved_488;
-    uint32_t reserved_48c;
-    uint32_t reserved_490;
-    uint32_t reserved_494;
-    uint32_t reserved_498;
-    uint32_t reserved_49c;
-    uint32_t reserved_4a0;
-    uint32_t reserved_4a4;
-    uint32_t reserved_4a8;
-    uint32_t reserved_4ac;
-    uint32_t reserved_4b0;
-    uint32_t reserved_4b4;
-    uint32_t reserved_4b8;
-    uint32_t reserved_4bc;
-    uint32_t reserved_4c0;
-    uint32_t reserved_4c4;
-    uint32_t reserved_4c8;
-    uint32_t reserved_4cc;
-    uint32_t reserved_4d0;
-    uint32_t reserved_4d4;
-    uint32_t reserved_4d8;
-    uint32_t reserved_4dc;
-    uint32_t reserved_4e0;
-    uint32_t reserved_4e4;
-    uint32_t reserved_4e8;
-    uint32_t reserved_4ec;
-    uint32_t reserved_4f0;
-    uint32_t reserved_4f4;
-    uint32_t reserved_4f8;
-    uint32_t reserved_4fc;
-    uint32_t reserved_500;
-    uint32_t reserved_504;
-    uint32_t reserved_508;
-    uint32_t reserved_50c;
-    uint32_t reserved_510;
-    uint32_t reserved_514;
-    uint32_t reserved_518;
-    uint32_t reserved_51c;
-    uint32_t reserved_520;
-    uint32_t reserved_524;
-    uint32_t reserved_528;
-    uint32_t reserved_52c;
-    uint32_t reserved_530;
-    uint32_t reserved_534;
-    uint32_t reserved_538;
-    uint32_t reserved_53c;
-    uint32_t reserved_540;
-    uint32_t reserved_544;
-    uint32_t reserved_548;
-    uint32_t reserved_54c;
-    uint32_t reserved_550;
-    uint32_t reserved_554;
-    uint32_t reserved_558;
-    uint32_t reserved_55c;
-    uint32_t reserved_560;
-    uint32_t reserved_564;
-    uint32_t reserved_568;
-    uint32_t reserved_56c;
-    uint32_t reserved_570;
-    uint32_t reserved_574;
-    uint32_t reserved_578;
-    uint32_t reserved_57c;
-    uint32_t reserved_580;
-    uint32_t reserved_584;
-    uint32_t reserved_588;
-    uint32_t reserved_58c;
-    uint32_t reserved_590;
-    uint32_t reserved_594;
-    uint32_t reserved_598;
-    uint32_t reserved_59c;
-    uint32_t reserved_5a0;
-    uint32_t reserved_5a4;
-    uint32_t reserved_5a8;
-    uint32_t reserved_5ac;
-    uint32_t reserved_5b0;
-    uint32_t reserved_5b4;
-    uint32_t reserved_5b8;
-    uint32_t reserved_5bc;
-    uint32_t reserved_5c0;
-    uint32_t reserved_5c4;
-    uint32_t reserved_5c8;
-    uint32_t reserved_5cc;
-    uint32_t reserved_5d0;
-    uint32_t reserved_5d4;
-    uint32_t reserved_5d8;
-    uint32_t reserved_5dc;
-    uint32_t reserved_5e0;
-    uint32_t reserved_5e4;
-    uint32_t reserved_5e8;
-    uint32_t reserved_5ec;
-    uint32_t reserved_5f0;
-    uint32_t reserved_5f4;
-    uint32_t reserved_5f8;
-    uint32_t reserved_5fc;
-    uint32_t reserved_600;
-    uint32_t reserved_604;
-    uint32_t reserved_608;
-    uint32_t reserved_60c;
-    uint32_t reserved_610;
-    uint32_t reserved_614;
-    uint32_t reserved_618;
-    uint32_t reserved_61c;
-    uint32_t reserved_620;
-    uint32_t reserved_624;
-    uint32_t reserved_628;
-    uint32_t reserved_62c;
-    uint32_t reserved_630;
-    uint32_t reserved_634;
-    uint32_t reserved_638;
-    uint32_t reserved_63c;
-    uint32_t reserved_640;
-    uint32_t reserved_644;
-    uint32_t reserved_648;
-    uint32_t reserved_64c;
-    uint32_t reserved_650;
-    uint32_t reserved_654;
-    uint32_t reserved_658;
-    uint32_t reserved_65c;
-    uint32_t reserved_660;
-    uint32_t reserved_664;
-    uint32_t reserved_668;
-    uint32_t reserved_66c;
-    uint32_t reserved_670;
-    uint32_t reserved_674;
-    uint32_t reserved_678;
-    uint32_t reserved_67c;
-    uint32_t reserved_680;
-    uint32_t reserved_684;
-    uint32_t reserved_688;
-    uint32_t reserved_68c;
-    uint32_t reserved_690;
-    uint32_t reserved_694;
-    uint32_t reserved_698;
-    uint32_t reserved_69c;
-    uint32_t reserved_6a0;
-    uint32_t reserved_6a4;
-    uint32_t reserved_6a8;
-    uint32_t reserved_6ac;
-    uint32_t reserved_6b0;
-    uint32_t reserved_6b4;
-    uint32_t reserved_6b8;
-    uint32_t reserved_6bc;
-    uint32_t reserved_6c0;
-    uint32_t reserved_6c4;
-    uint32_t reserved_6c8;
-    uint32_t reserved_6cc;
-    uint32_t reserved_6d0;
-    uint32_t reserved_6d4;
-    uint32_t reserved_6d8;
-    uint32_t reserved_6dc;
-    uint32_t reserved_6e0;
-    uint32_t reserved_6e4;
-    uint32_t reserved_6e8;
-    uint32_t reserved_6ec;
-    uint32_t reserved_6f0;
-    uint32_t reserved_6f4;
-    uint32_t reserved_6f8;
-    uint32_t reserved_6fc;
-    uint32_t reserved_700;
-    uint32_t reserved_704;
-    uint32_t reserved_708;
-    uint32_t reserved_70c;
-    uint32_t reserved_710;
-    uint32_t reserved_714;
-    uint32_t reserved_718;
-    uint32_t reserved_71c;
-    uint32_t reserved_720;
-    uint32_t reserved_724;
-    uint32_t reserved_728;
-    uint32_t reserved_72c;
-    uint32_t reserved_730;
-    uint32_t reserved_734;
-    uint32_t reserved_738;
-    uint32_t reserved_73c;
-    uint32_t reserved_740;
-    uint32_t reserved_744;
-    uint32_t reserved_748;
-    uint32_t reserved_74c;
-    uint32_t reserved_750;
-    uint32_t reserved_754;
-    uint32_t reserved_758;
-    uint32_t reserved_75c;
-    uint32_t reserved_760;
-    uint32_t reserved_764;
-    uint32_t reserved_768;
-    uint32_t reserved_76c;
-    uint32_t reserved_770;
-    uint32_t reserved_774;
-    uint32_t reserved_778;
-    uint32_t reserved_77c;
-    uint32_t reserved_780;
-    uint32_t reserved_784;
-    uint32_t reserved_788;
-    uint32_t reserved_78c;
-    uint32_t reserved_790;
-    uint32_t reserved_794;
-    uint32_t reserved_798;
-    uint32_t reserved_79c;
-    uint32_t reserved_7a0;
-    uint32_t reserved_7a4;
-    uint32_t reserved_7a8;
-    uint32_t reserved_7ac;
-    uint32_t reserved_7b0;
-    uint32_t reserved_7b4;
-    uint32_t reserved_7b8;
-    uint32_t reserved_7bc;
-    uint32_t reserved_7c0;
-    uint32_t reserved_7c4;
-    uint32_t reserved_7c8;
-    uint32_t reserved_7cc;
-    uint32_t reserved_7d0;
-    uint32_t reserved_7d4;
-    uint32_t reserved_7d8;
-    uint32_t reserved_7dc;
-    uint32_t reserved_7e0;
-    uint32_t reserved_7e4;
-    uint32_t reserved_7e8;
-    uint32_t reserved_7ec;
-    uint32_t reserved_7f0;
-    uint32_t reserved_7f4;
-    uint32_t reserved_7f8;
-    uint32_t reserved_7fc;
-    uint32_t reserved_800;
-    uint32_t reserved_804;
-    uint32_t reserved_808;
-    uint32_t reserved_80c;
-    uint32_t reserved_810;
-    uint32_t reserved_814;
-    uint32_t reserved_818;
-    uint32_t reserved_81c;
-    uint32_t reserved_820;
-    uint32_t reserved_824;
-    uint32_t reserved_828;
-    uint32_t reserved_82c;
-    uint32_t reserved_830;
-    uint32_t reserved_834;
-    uint32_t reserved_838;
-    uint32_t reserved_83c;
-    uint32_t reserved_840;
-    uint32_t reserved_844;
-    uint32_t reserved_848;
-    uint32_t reserved_84c;
-    uint32_t reserved_850;
-    uint32_t reserved_854;
-    uint32_t reserved_858;
-    uint32_t reserved_85c;
-    uint32_t reserved_860;
-    uint32_t reserved_864;
-    uint32_t reserved_868;
-    uint32_t reserved_86c;
-    uint32_t reserved_870;
-    uint32_t reserved_874;
-    uint32_t reserved_878;
-    uint32_t reserved_87c;
-    uint32_t reserved_880;
-    uint32_t reserved_884;
-    uint32_t reserved_888;
-    uint32_t reserved_88c;
-    uint32_t reserved_890;
-    uint32_t reserved_894;
-    uint32_t reserved_898;
-    uint32_t reserved_89c;
-    uint32_t reserved_8a0;
-    uint32_t reserved_8a4;
-    uint32_t reserved_8a8;
-    uint32_t reserved_8ac;
-    uint32_t reserved_8b0;
-    uint32_t reserved_8b4;
-    uint32_t reserved_8b8;
-    uint32_t reserved_8bc;
-    uint32_t reserved_8c0;
-    uint32_t reserved_8c4;
-    uint32_t reserved_8c8;
-    uint32_t reserved_8cc;
-    uint32_t reserved_8d0;
-    uint32_t reserved_8d4;
-    uint32_t reserved_8d8;
-    uint32_t reserved_8dc;
-    uint32_t reserved_8e0;
-    uint32_t reserved_8e4;
-    uint32_t reserved_8e8;
-    uint32_t reserved_8ec;
-    uint32_t reserved_8f0;
-    uint32_t reserved_8f4;
-    uint32_t reserved_8f8;
-    uint32_t reserved_8fc;
-    uint32_t reserved_900;
-    uint32_t reserved_904;
-    uint32_t reserved_908;
-    uint32_t reserved_90c;
-    uint32_t reserved_910;
-    uint32_t reserved_914;
-    uint32_t reserved_918;
-    uint32_t reserved_91c;
-    uint32_t reserved_920;
-    uint32_t reserved_924;
-    uint32_t reserved_928;
-    uint32_t reserved_92c;
-    uint32_t reserved_930;
-    uint32_t reserved_934;
-    uint32_t reserved_938;
-    uint32_t reserved_93c;
-    uint32_t reserved_940;
-    uint32_t reserved_944;
-    uint32_t reserved_948;
-    uint32_t reserved_94c;
-    uint32_t reserved_950;
-    uint32_t reserved_954;
-    uint32_t reserved_958;
-    uint32_t reserved_95c;
-    uint32_t reserved_960;
-    uint32_t reserved_964;
-    uint32_t reserved_968;
-    uint32_t reserved_96c;
-    uint32_t reserved_970;
-    uint32_t reserved_974;
-    uint32_t reserved_978;
-    uint32_t reserved_97c;
-    uint32_t reserved_980;
-    uint32_t reserved_984;
-    uint32_t reserved_988;
-    uint32_t reserved_98c;
-    uint32_t reserved_990;
-    uint32_t reserved_994;
-    uint32_t reserved_998;
-    uint32_t reserved_99c;
-    uint32_t reserved_9a0;
-    uint32_t reserved_9a4;
-    uint32_t reserved_9a8;
-    uint32_t reserved_9ac;
-    uint32_t reserved_9b0;
-    uint32_t reserved_9b4;
-    uint32_t reserved_9b8;
-    uint32_t reserved_9bc;
-    uint32_t reserved_9c0;
-    uint32_t reserved_9c4;
-    uint32_t reserved_9c8;
-    uint32_t reserved_9cc;
-    uint32_t reserved_9d0;
-    uint32_t reserved_9d4;
-    uint32_t reserved_9d8;
-    uint32_t reserved_9dc;
-    uint32_t reserved_9e0;
-    uint32_t reserved_9e4;
-    uint32_t reserved_9e8;
-    uint32_t reserved_9ec;
-    uint32_t reserved_9f0;
-    uint32_t reserved_9f4;
-    uint32_t reserved_9f8;
-    uint32_t reserved_9fc;
-    uint32_t reserved_a00;
-    uint32_t reserved_a04;
-    uint32_t reserved_a08;
-    uint32_t reserved_a0c;
-    uint32_t reserved_a10;
-    uint32_t reserved_a14;
-    uint32_t reserved_a18;
-    uint32_t reserved_a1c;
-    uint32_t reserved_a20;
-    uint32_t reserved_a24;
-    uint32_t reserved_a28;
-    uint32_t reserved_a2c;
-    uint32_t reserved_a30;
-    uint32_t reserved_a34;
-    uint32_t reserved_a38;
-    uint32_t reserved_a3c;
-    uint32_t reserved_a40;
-    uint32_t reserved_a44;
-    uint32_t reserved_a48;
-    uint32_t reserved_a4c;
-    uint32_t reserved_a50;
-    uint32_t reserved_a54;
-    uint32_t reserved_a58;
-    uint32_t reserved_a5c;
-    uint32_t reserved_a60;
-    uint32_t reserved_a64;
-    uint32_t reserved_a68;
-    uint32_t reserved_a6c;
-    uint32_t reserved_a70;
-    uint32_t reserved_a74;
-    uint32_t reserved_a78;
-    uint32_t reserved_a7c;
-    uint32_t reserved_a80;
-    uint32_t reserved_a84;
-    uint32_t reserved_a88;
-    uint32_t reserved_a8c;
-    uint32_t reserved_a90;
-    uint32_t reserved_a94;
-    uint32_t reserved_a98;
-    uint32_t reserved_a9c;
-    uint32_t reserved_aa0;
-    uint32_t reserved_aa4;
-    uint32_t reserved_aa8;
-    uint32_t reserved_aac;
-    uint32_t reserved_ab0;
-    uint32_t reserved_ab4;
-    uint32_t reserved_ab8;
-    uint32_t reserved_abc;
-    uint32_t reserved_ac0;
-    uint32_t reserved_ac4;
-    uint32_t reserved_ac8;
-    uint32_t reserved_acc;
-    uint32_t reserved_ad0;
-    uint32_t reserved_ad4;
-    uint32_t reserved_ad8;
-    uint32_t reserved_adc;
-    uint32_t reserved_ae0;
-    uint32_t reserved_ae4;
-    uint32_t reserved_ae8;
-    uint32_t reserved_aec;
-    uint32_t reserved_af0;
-    uint32_t reserved_af4;
-    uint32_t reserved_af8;
-    uint32_t reserved_afc;
-    uint32_t reserved_b00;
-    uint32_t reserved_b04;
-    uint32_t reserved_b08;
-    uint32_t reserved_b0c;
-    uint32_t reserved_b10;
-    uint32_t reserved_b14;
-    uint32_t reserved_b18;
-    uint32_t reserved_b1c;
-    uint32_t reserved_b20;
-    uint32_t reserved_b24;
-    uint32_t reserved_b28;
-    uint32_t reserved_b2c;
-    uint32_t reserved_b30;
-    uint32_t reserved_b34;
-    uint32_t reserved_b38;
-    uint32_t reserved_b3c;
-    uint32_t reserved_b40;
-    uint32_t reserved_b44;
-    uint32_t reserved_b48;
-    uint32_t reserved_b4c;
-    uint32_t reserved_b50;
-    uint32_t reserved_b54;
-    uint32_t reserved_b58;
-    uint32_t reserved_b5c;
-    uint32_t reserved_b60;
-    uint32_t reserved_b64;
-    uint32_t reserved_b68;
-    uint32_t reserved_b6c;
-    uint32_t reserved_b70;
-    uint32_t reserved_b74;
-    uint32_t reserved_b78;
-    uint32_t reserved_b7c;
-    uint32_t reserved_b80;
-    uint32_t reserved_b84;
-    uint32_t reserved_b88;
-    uint32_t reserved_b8c;
-    uint32_t reserved_b90;
-    uint32_t reserved_b94;
-    uint32_t reserved_b98;
-    uint32_t reserved_b9c;
-    uint32_t reserved_ba0;
-    uint32_t reserved_ba4;
-    uint32_t reserved_ba8;
-    uint32_t reserved_bac;
-    uint32_t reserved_bb0;
-    uint32_t reserved_bb4;
-    uint32_t reserved_bb8;
-    uint32_t reserved_bbc;
-    uint32_t reserved_bc0;
-    uint32_t reserved_bc4;
-    uint32_t reserved_bc8;
-    uint32_t reserved_bcc;
-    uint32_t reserved_bd0;
-    uint32_t reserved_bd4;
-    uint32_t reserved_bd8;
-    uint32_t reserved_bdc;
-    uint32_t reserved_be0;
-    uint32_t reserved_be4;
-    uint32_t reserved_be8;
-    uint32_t reserved_bec;
-    uint32_t reserved_bf0;
-    uint32_t reserved_bf4;
-    uint32_t reserved_bf8;
-    uint32_t reserved_bfc;
-    uint32_t reserved_c00;
-    uint32_t reserved_c04;
-    uint32_t reserved_c08;
-    uint32_t reserved_c0c;
-    uint32_t reserved_c10;
-    uint32_t reserved_c14;
-    uint32_t reserved_c18;
-    uint32_t reserved_c1c;
-    uint32_t reserved_c20;
-    uint32_t reserved_c24;
-    uint32_t reserved_c28;
-    uint32_t reserved_c2c;
-    uint32_t reserved_c30;
-    uint32_t reserved_c34;
-    uint32_t reserved_c38;
-    uint32_t reserved_c3c;
-    uint32_t reserved_c40;
-    uint32_t reserved_c44;
-    uint32_t reserved_c48;
-    uint32_t reserved_c4c;
-    uint32_t reserved_c50;
-    uint32_t reserved_c54;
-    uint32_t reserved_c58;
-    uint32_t reserved_c5c;
-    uint32_t reserved_c60;
-    uint32_t reserved_c64;
-    uint32_t reserved_c68;
-    uint32_t reserved_c6c;
-    uint32_t reserved_c70;
-    uint32_t reserved_c74;
-    uint32_t reserved_c78;
-    uint32_t reserved_c7c;
-    uint32_t reserved_c80;
-    uint32_t reserved_c84;
-    uint32_t reserved_c88;
-    uint32_t reserved_c8c;
-    uint32_t reserved_c90;
-    uint32_t reserved_c94;
-    uint32_t reserved_c98;
-    uint32_t reserved_c9c;
-    uint32_t reserved_ca0;
-    uint32_t reserved_ca4;
-    uint32_t reserved_ca8;
-    uint32_t reserved_cac;
-    uint32_t reserved_cb0;
-    uint32_t reserved_cb4;
-    uint32_t reserved_cb8;
-    uint32_t reserved_cbc;
-    uint32_t reserved_cc0;
-    uint32_t reserved_cc4;
-    uint32_t reserved_cc8;
-    uint32_t reserved_ccc;
-    uint32_t reserved_cd0;
-    uint32_t reserved_cd4;
-    uint32_t reserved_cd8;
-    uint32_t reserved_cdc;
-    uint32_t reserved_ce0;
-    uint32_t reserved_ce4;
-    uint32_t reserved_ce8;
-    uint32_t reserved_cec;
-    uint32_t reserved_cf0;
-    uint32_t reserved_cf4;
-    uint32_t reserved_cf8;
-    uint32_t reserved_cfc;
-    uint32_t reserved_d00;
-    uint32_t reserved_d04;
-    uint32_t reserved_d08;
-    uint32_t reserved_d0c;
-    uint32_t reserved_d10;
-    uint32_t reserved_d14;
-    uint32_t reserved_d18;
-    uint32_t reserved_d1c;
-    uint32_t reserved_d20;
-    uint32_t reserved_d24;
-    uint32_t reserved_d28;
-    uint32_t reserved_d2c;
-    uint32_t reserved_d30;
-    uint32_t reserved_d34;
-    uint32_t reserved_d38;
-    uint32_t reserved_d3c;
-    uint32_t reserved_d40;
-    uint32_t reserved_d44;
-    uint32_t reserved_d48;
-    uint32_t reserved_d4c;
-    uint32_t reserved_d50;
-    uint32_t reserved_d54;
-    uint32_t reserved_d58;
-    uint32_t reserved_d5c;
-    uint32_t reserved_d60;
-    uint32_t reserved_d64;
-    uint32_t reserved_d68;
-    uint32_t reserved_d6c;
-    uint32_t reserved_d70;
-    uint32_t reserved_d74;
-    uint32_t reserved_d78;
-    uint32_t reserved_d7c;
-    uint32_t reserved_d80;
-    uint32_t reserved_d84;
-    uint32_t reserved_d88;
-    uint32_t reserved_d8c;
-    uint32_t reserved_d90;
-    uint32_t reserved_d94;
-    uint32_t reserved_d98;
-    uint32_t reserved_d9c;
-    uint32_t reserved_da0;
-    uint32_t reserved_da4;
-    uint32_t reserved_da8;
-    uint32_t reserved_dac;
-    uint32_t reserved_db0;
-    uint32_t reserved_db4;
-    uint32_t reserved_db8;
-    uint32_t reserved_dbc;
-    uint32_t reserved_dc0;
-    uint32_t reserved_dc4;
-    uint32_t reserved_dc8;
-    uint32_t reserved_dcc;
-    uint32_t reserved_dd0;
-    uint32_t reserved_dd4;
-    uint32_t reserved_dd8;
-    uint32_t reserved_ddc;
-    uint32_t reserved_de0;
-    uint32_t reserved_de4;
-    uint32_t reserved_de8;
-    uint32_t reserved_dec;
-    uint32_t reserved_df0;
-    uint32_t reserved_df4;
-    uint32_t reserved_df8;
-    uint32_t reserved_dfc;
-    uint32_t reserved_e00;
-    uint32_t reserved_e04;
-    uint32_t reserved_e08;
-    uint32_t reserved_e0c;
-    uint32_t reserved_e10;
-    uint32_t reserved_e14;
-    uint32_t reserved_e18;
-    uint32_t reserved_e1c;
-    uint32_t reserved_e20;
-    uint32_t reserved_e24;
-    uint32_t reserved_e28;
-    uint32_t reserved_e2c;
-    uint32_t reserved_e30;
-    uint32_t reserved_e34;
-    uint32_t reserved_e38;
-    uint32_t reserved_e3c;
-    uint32_t reserved_e40;
-    uint32_t reserved_e44;
-    uint32_t reserved_e48;
-    uint32_t reserved_e4c;
-    uint32_t reserved_e50;
-    uint32_t reserved_e54;
-    uint32_t reserved_e58;
-    uint32_t reserved_e5c;
-    uint32_t reserved_e60;
-    uint32_t reserved_e64;
-    uint32_t reserved_e68;
-    uint32_t reserved_e6c;
-    uint32_t reserved_e70;
-    uint32_t reserved_e74;
-    uint32_t reserved_e78;
-    uint32_t reserved_e7c;
-    uint32_t reserved_e80;
-    uint32_t reserved_e84;
-    uint32_t reserved_e88;
-    uint32_t reserved_e8c;
-    uint32_t reserved_e90;
-    uint32_t reserved_e94;
-    uint32_t reserved_e98;
-    uint32_t reserved_e9c;
-    uint32_t reserved_ea0;
-    uint32_t reserved_ea4;
-    uint32_t reserved_ea8;
-    uint32_t reserved_eac;
-    uint32_t reserved_eb0;
-    uint32_t reserved_eb4;
-    uint32_t reserved_eb8;
-    uint32_t reserved_ebc;
-    uint32_t reserved_ec0;
-    uint32_t reserved_ec4;
-    uint32_t reserved_ec8;
-    uint32_t reserved_ecc;
-    uint32_t reserved_ed0;
-    uint32_t reserved_ed4;
-    uint32_t reserved_ed8;
-    uint32_t reserved_edc;
-    uint32_t reserved_ee0;
-    uint32_t reserved_ee4;
-    uint32_t reserved_ee8;
-    uint32_t reserved_eec;
-    uint32_t reserved_ef0;
-    uint32_t reserved_ef4;
-    uint32_t reserved_ef8;
-    uint32_t reserved_efc;
-    uint32_t reserved_f00;
-    uint32_t reserved_f04;
-    uint32_t reserved_f08;
-    uint32_t reserved_f0c;
-    uint32_t reserved_f10;
-    uint32_t reserved_f14;
-    uint32_t reserved_f18;
-    uint32_t reserved_f1c;
-    uint32_t reserved_f20;
-    uint32_t reserved_f24;
-    uint32_t reserved_f28;
-    uint32_t reserved_f2c;
-    uint32_t reserved_f30;
-    uint32_t reserved_f34;
-    uint32_t reserved_f38;
-    uint32_t reserved_f3c;
-    uint32_t reserved_f40;
-    uint32_t reserved_f44;
-    uint32_t reserved_f48;
-    uint32_t reserved_f4c;
-    uint32_t reserved_f50;
-    uint32_t reserved_f54;
-    uint32_t reserved_f58;
-    uint32_t reserved_f5c;
-    uint32_t reserved_f60;
-    uint32_t reserved_f64;
-    uint32_t reserved_f68;
-    uint32_t reserved_f6c;
-    uint32_t reserved_f70;
-    uint32_t reserved_f74;
-    uint32_t reserved_f78;
-    uint32_t reserved_f7c;
-    uint32_t reserved_f80;
-    uint32_t reserved_f84;
-    uint32_t reserved_f88;
-    uint32_t reserved_f8c;
-    uint32_t reserved_f90;
-    uint32_t reserved_f94;
-    uint32_t reserved_f98;
-    uint32_t reserved_f9c;
-    uint32_t reserved_fa0;
-    uint32_t reserved_fa4;
-    uint32_t reserved_fa8;
-    uint32_t reserved_fac;
-    uint32_t reserved_fb0;
-    uint32_t reserved_fb4;
-    uint32_t reserved_fb8;
-    uint32_t reserved_fbc;
-    uint32_t reserved_fc0;
-    uint32_t reserved_fc4;
-    uint32_t reserved_fc8;
-    uint32_t reserved_fcc;
-    uint32_t reserved_fd0;
-    uint32_t reserved_fd4;
-    uint32_t reserved_fd8;
-    uint32_t reserved_fdc;
-    uint32_t reserved_fe0;
-    uint32_t reserved_fe4;
-    uint32_t reserved_fe8;
-    uint32_t reserved_fec;
-    uint32_t reserved_ff0;
-    uint32_t reserved_ff4;
-    uint32_t reserved_ff8;
-    union {
-        struct {
-            uint32_t reg_date                      :    28;  /*reg_date*/
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } date;
-} sensitive_dev_t;
-extern sensitive_dev_t SENSITIVE;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SENSITIVE_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h
index d661c4eb126..1b47dd70fb1 100644
--- a/components/soc/esp32c3/include/soc/soc.h
+++ b/components/soc/esp32c3/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 74c25ccd4d0..bbe96291fc5 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -223,6 +223,7 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK      (1)
+#define SOC_LEDC_TIMER_NUM               (4)
 #define SOC_LEDC_CHANNEL_NUM             (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH         (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP       (1)
@@ -449,6 +450,8 @@
 
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2           (1)     /*!< Support XTAL_D2 clock as the LP_FAST clock source */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                (1)
diff --git a/components/soc/esp32c3/include/soc/spi_mem_reg.h b/components/soc/esp32c3/include/soc/spi_mem_reg.h
deleted file mode 100644
index fcf3e292481..00000000000
--- a/components/soc/esp32c3/include/soc/spi_mem_reg.h
+++ /dev/null
@@ -1,1220 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SPI_MEM_REG_H_
-#define _SOC_SPI_MEM_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x000)
-/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Read flash enable. Read flash operation will be triggered when
- the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-#define SPI_MEM_FLASH_READ  (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (BIT(31))
-#define SPI_MEM_FLASH_READ_V  0x1
-#define SPI_MEM_FLASH_READ_S  31
-/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Write flash enable.  Write enable command will be sent when the
- bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-#define SPI_MEM_FLASH_WREN  (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (BIT(30))
-#define SPI_MEM_FLASH_WREN_V  0x1
-#define SPI_MEM_FLASH_WREN_S  30
-/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Write flash disable. Write disable command will be sent when
- the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-#define SPI_MEM_FLASH_WRDI  (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
-#define SPI_MEM_FLASH_WRDI_V  0x1
-#define SPI_MEM_FLASH_WRDI_S  29
-/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Read JEDEC ID . Read ID command will be sent when the bit is
- set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-#define SPI_MEM_FLASH_RDID  (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (BIT(28))
-#define SPI_MEM_FLASH_RDID_V  0x1
-#define SPI_MEM_FLASH_RDID_S  28
-/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Read status register-1.  Read status operation will be triggered
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_RDSR  (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
-#define SPI_MEM_FLASH_RDSR_V  0x1
-#define SPI_MEM_FLASH_RDSR_S  27
-/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write status register enable.   Write status operation  will
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_WRSR  (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
-#define SPI_MEM_FLASH_WRSR_V  0x1
-#define SPI_MEM_FLASH_WRSR_S  26
-/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Page program enable(1 byte ~256 bytes data to be programmed).
- Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
-#define SPI_MEM_FLASH_PP  (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (BIT(25))
-#define SPI_MEM_FLASH_PP_V  0x1
-#define SPI_MEM_FLASH_PP_S  25
-/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Sector erase enable(4KB). Sector erase operation will be triggered
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_SE  (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (BIT(24))
-#define SPI_MEM_FLASH_SE_V  0x1
-#define SPI_MEM_FLASH_SE_S  24
-/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Block erase enable(32KB) .  Block erase operation will be triggered
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_BE  (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (BIT(23))
-#define SPI_MEM_FLASH_BE_V  0x1
-#define SPI_MEM_FLASH_BE_S  23
-/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Chip erase enable. Chip erase operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_CE  (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (BIT(22))
-#define SPI_MEM_FLASH_CE_V  0x1
-#define SPI_MEM_FLASH_CE_S  22
-/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Drive Flash into power down.  An operation will be triggered
- when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_DP  (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (BIT(21))
-#define SPI_MEM_FLASH_DP_V  0x1
-#define SPI_MEM_FLASH_DP_S  21
-/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This bit combined with reg_resandres bit releases Flash from
- the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_RES  (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (BIT(20))
-#define SPI_MEM_FLASH_RES_V  0x1
-#define SPI_MEM_FLASH_RES_S  20
-/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Drive Flash into high performance mode.  The bit will be cleared
- once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_HPM  (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (BIT(19))
-#define SPI_MEM_FLASH_HPM_V  0x1
-#define SPI_MEM_FLASH_HPM_S  19
-/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
-/*description: User define command enable.  An operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_USR  (BIT(18))
-#define SPI_MEM_USR_M  (BIT(18))
-#define SPI_MEM_USR_V  0x1
-#define SPI_MEM_USR_S  18
-/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
-/*description: In user mode  it is set to indicate that program/erase operation
- will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_PE  (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (BIT(17))
-#define SPI_MEM_FLASH_PE_V  0x1
-#define SPI_MEM_FLASH_PE_S  17
-/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state
-  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
-#define SPI_MEM_SLV_ST  0x0000000F
-#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
-#define SPI_MEM_SLV_ST_V  0xF
-#define SPI_MEM_SLV_ST_S  4
-/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: The current status of SPI1 master FSM.*/
-#define SPI_MEM_MST_ST  0x0000000F
-#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
-#define SPI_MEM_MST_ST_V  0xF
-#define SPI_MEM_MST_ST_S  0
-
-#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x004)
-/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: In user mode  it is the memory address. other then the bit0-bit23
- is the memory address  the bit24-bit31 are the byte length of a transfer.*/
-#define SPI_MEM_USR_ADDR_VALUE  0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_S  0
-
-#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x008)
-/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply
- 4 signals. 1: enable 0: disable.*/
-#define SPI_MEM_FREAD_QIO  (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (BIT(24))
-#define SPI_MEM_FREAD_QIO_V  0x1
-#define SPI_MEM_FREAD_QIO_S  24
-/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply
- 2 signals. 1: enable 0: disable.*/
-#define SPI_MEM_FREAD_DIO  (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (BIT(23))
-#define SPI_MEM_FREAD_DIO_V  0x1
-#define SPI_MEM_FREAD_DIO_S  23
-/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: two bytes data will be written to status register when it is
- set. 1: enable 0: disable.*/
-#define SPI_MEM_WRSR_2B  (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (BIT(22))
-#define SPI_MEM_WRSR_2B_V  0x1
-#define SPI_MEM_WRSR_2B_S  22
-/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high  0: output low.*/
-#define SPI_MEM_WP_REG  (BIT(21))
-#define SPI_MEM_WP_REG_M  (BIT(21))
-#define SPI_MEM_WP_REG_V  0x1
-#define SPI_MEM_WP_REG_S  21
-/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
-#define SPI_MEM_FREAD_QUAD  (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
-#define SPI_MEM_FREAD_QUAD_V  0x1
-#define SPI_MEM_FREAD_QUAD_S  20
-/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity  1: high 0  low*/
-#define SPI_MEM_D_POL  (BIT(19))
-#define SPI_MEM_D_POL_M  (BIT(19))
-#define SPI_MEM_D_POL_V  0x1
-#define SPI_MEM_D_POL_S  19
-/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity  1: high 0  low*/
-#define SPI_MEM_Q_POL  (BIT(18))
-#define SPI_MEM_Q_POL_M  (BIT(18))
-#define SPI_MEM_Q_POL_V  0x1
-#define SPI_MEM_Q_POL_S  18
-/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: The Device ID is read out to SPI_MEM_RD_STATUS register   this
- bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
-#define SPI_MEM_RESANDRES  (BIT(15))
-#define SPI_MEM_RESANDRES_M  (BIT(15))
-#define SPI_MEM_RESANDRES_V  0x1
-#define SPI_MEM_RESANDRES_S  15
-/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
-#define SPI_MEM_FREAD_DUAL  (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
-#define SPI_MEM_FREAD_DUAL_V  0x1
-#define SPI_MEM_FREAD_DUAL_S  14
-/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit enable the bits: spi_mem_fread_qio  spi_mem_fread_dio
-  spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
-#define SPI_MEM_FASTRD_MODE  (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
-#define SPI_MEM_FASTRD_MODE_V  0x1
-#define SPI_MEM_FASTRD_MODE_S  13
-/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1   enable crc32 when writing encrypted data to flash.
- 1: enable 0:disable*/
-#define SPI_MEM_TX_CRC_EN  (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
-#define SPI_MEM_TX_CRC_EN_V  0x1
-#define SPI_MEM_TX_CRC_EN_S  11
-/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI1   initialize crc32 module before writing encrypted data
- to flash. Active low.*/
-#define SPI_MEM_FCS_CRC_EN  (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_V  0x1
-#define SPI_MEM_FCS_CRC_EN_S  10
-/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable*/
-#define SPI_MEM_FCMD_QUAD  (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
-#define SPI_MEM_FCMD_QUAD_V  0x1
-#define SPI_MEM_FCMD_QUAD_S  8
-/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Apply 2 signals during command phase 1:enable 0: disable*/
-#define SPI_MEM_FCMD_DUAL  (BIT(7))
-#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
-#define SPI_MEM_FCMD_DUAL_V  0x1
-#define SPI_MEM_FCMD_DUAL_S  7
-/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: In the dummy phase the signal level of spi is output by the spi controller.*/
-#define SPI_MEM_FDUMMY_OUT  (BIT(3))
-#define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
-#define SPI_MEM_FDUMMY_OUT_V  0x1
-#define SPI_MEM_FDUMMY_OUT_S  3
-
-#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x00C)
-/* SPI_MEM_RXFIFO_WFULL_ERR : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: SPI0 RX FIFO write full error  Cache/EDMA do not read all
- the data out. 0: Not error.*/
-#define SPI_MEM_RXFIFO_WFULL_ERR  (BIT(31))
-#define SPI_MEM_RXFIFO_WFULL_ERR_M  (BIT(31))
-#define SPI_MEM_RXFIFO_WFULL_ERR_V  0x1
-#define SPI_MEM_RXFIFO_WFULL_ERR_S  31
-/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: SPI0 RX FIFO reset signal.*/
-#define SPI_MEM_RXFIFO_RST  (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
-#define SPI_MEM_RXFIFO_RST_V  0x1
-#define SPI_MEM_RXFIFO_RST_S  30
-/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
-/*description: After RES/DP/HPM command is sent  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
- * 512) SPI_CLK cycles.*/
-#define SPI_MEM_CS_HOLD_DLY_RES  0x000003FF
-#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
-/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
- SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
-#define SPI_MEM_CLK_MODE  0x00000003
-#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
-#define SPI_MEM_CLK_MODE_V  0x3
-#define SPI_MEM_CLK_MODE_S  0
-
-#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x010)
-/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The FSM will be reset.*/
-#define SPI_MEM_SYNC_RESET  (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (BIT(31))
-#define SPI_MEM_SYNC_RESET_V  0x1
-#define SPI_MEM_SYNC_RESET_S  31
-/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between
- SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-#define SPI_MEM_CS_HOLD_DELAY  0x0000003F
-#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
-/*description: Spi cs signal is delayed to inactive by spi clock this bits are
- combined with spi_mem_cs_hold bit.*/
-#define SPI_MEM_CS_HOLD_TIME  0x0000001F
-#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
-#define SPI_MEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
-/*description: (cycles-1) of prepare phase by spi clock this bits are combined
- with spi_mem_cs_setup bit.*/
-#define SPI_MEM_CS_SETUP_TIME  0x0000001F
-#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
-#define SPI_MEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_CS_SETUP_TIME_S  0
-
-#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x014)
-/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit in 1-division mode.reserved for spi1*/
-#define SPI_MEM_CLK_EQU_SYSCLK  (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
-/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk
- frequency is system/(spi_mem_clkcnt_N+1)*/
-#define SPI_MEM_CLKCNT_N  0x000000FF
-#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
-#define SPI_MEM_CLKCNT_N_V  0xFF
-#define SPI_MEM_CLKCNT_N_S  16
-/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-#define SPI_MEM_CLKCNT_H  0x000000FF
-#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
-#define SPI_MEM_CLKCNT_H_V  0xFF
-#define SPI_MEM_CLKCNT_H_S  8
-/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: In the master mode it must be equal to spi_mem_clkcnt_N.*/
-#define SPI_MEM_CLKCNT_L  0x000000FF
-#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
-#define SPI_MEM_CLKCNT_L_V  0xFF
-#define SPI_MEM_CLKCNT_L_S  0
-
-#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x018)
-/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation.*/
-#define SPI_MEM_USR_COMMAND  (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (BIT(31))
-#define SPI_MEM_USR_COMMAND_V  0x1
-#define SPI_MEM_USR_COMMAND_S  31
-/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation.*/
-#define SPI_MEM_USR_ADDR  (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (BIT(30))
-#define SPI_MEM_USR_ADDR_V  0x1
-#define SPI_MEM_USR_ADDR_S  30
-/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation.*/
-#define SPI_MEM_USR_DUMMY  (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (BIT(29))
-#define SPI_MEM_USR_DUMMY_V  0x1
-#define SPI_MEM_USR_DUMMY_S  29
-/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation.*/
-#define SPI_MEM_USR_MISO  (BIT(28))
-#define SPI_MEM_USR_MISO_M  (BIT(28))
-#define SPI_MEM_USR_MISO_V  0x1
-#define SPI_MEM_USR_MISO_S  28
-/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation.*/
-#define SPI_MEM_USR_MOSI  (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (BIT(27))
-#define SPI_MEM_USR_MOSI_V  0x1
-#define SPI_MEM_USR_MOSI_S  27
-/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable.*/
-#define SPI_MEM_USR_DUMMY_IDLE  (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
- 1: enable 0: disable.*/
-#define SPI_MEM_USR_MOSI_HIGHPART  (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
- 1: enable 0: disable.*/
-#define SPI_MEM_USR_MISO_HIGHPART  (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 4 signals.*/
-#define SPI_MEM_FWRITE_QIO  (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
-#define SPI_MEM_FWRITE_QIO_V  0x1
-#define SPI_MEM_FWRITE_QIO_S  15
-/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 2 signals.*/
-#define SPI_MEM_FWRITE_DIO  (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
-#define SPI_MEM_FWRITE_DIO_V  0x1
-#define SPI_MEM_FWRITE_DIO_S  14
-/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals*/
-#define SPI_MEM_FWRITE_QUAD  (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_V  0x1
-#define SPI_MEM_FWRITE_QUAD_S  13
-/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals*/
-#define SPI_MEM_FWRITE_DUAL  (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_V  0x1
-#define SPI_MEM_FWRITE_DUAL_S  12
-/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi
- signal delay mode.*/
-#define SPI_MEM_CK_OUT_EDGE  (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_V  0x1
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
-#define SPI_MEM_CS_SETUP  (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (BIT(7))
-#define SPI_MEM_CS_SETUP_V  0x1
-#define SPI_MEM_CS_SETUP_S  7
-/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
-#define SPI_MEM_CS_HOLD  (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (BIT(6))
-#define SPI_MEM_CS_HOLD_V  0x1
-#define SPI_MEM_CS_HOLD_S  6
-
-#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x01C)
-/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/
-#define SPI_MEM_USR_ADDR_BITLEN  0x0000003F
-#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
-/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
-/*description: The length in spi_mem_clk cycles of dummy phase. The register
- value shall be (cycle_num-1).*/
-#define SPI_MEM_USR_DUMMY_CYCLELEN  0x0000003F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x020)
-/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/
-#define SPI_MEM_USR_COMMAND_BITLEN  0x0000000F
-#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
-/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command.*/
-#define SPI_MEM_USR_COMMAND_VALUE  0x0000FFFF
-#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
-#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-
-#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x024)
-/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/
-#define SPI_MEM_USR_MOSI_DBITLEN  0x000003FF
-#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
-
-#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x028)
-/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of  read-data. The register value shall be (bit_num-1).*/
-#define SPI_MEM_USR_MISO_DBITLEN  0x000003FF
-#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
-
-#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x02C)
-/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode
- bit.*/
-#define SPI_MEM_WB_MODE  0x000000FF
-#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
-#define SPI_MEM_WB_MODE_V  0xFF
-#define SPI_MEM_WB_MODE_S  16
-/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
-#define SPI_MEM_STATUS  0x0000FFFF
-#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
-#define SPI_MEM_STATUS_V  0xFFFF
-#define SPI_MEM_STATUS_S  0
-
-#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x034)
-/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: spi cs line keep low when the bit is set.*/
-#define SPI_MEM_CS_KEEP_ACTIVE  (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
-/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle*/
-#define SPI_MEM_CK_IDLE_EDGE  (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_V  0x1
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/* SPI_MEM_SLV_ST_TRANS_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt of spi0_slv_st controlled
- transmitting is done.*/
-#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA  (BIT(6))
-#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_M  (BIT(6))
-#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_V  0x1
-#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_S  6
-/* SPI_MEM_SLV_ST_TRANS_END : R/W/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
-#define SPI_MEM_SLV_ST_TRANS_END  (BIT(5))
-#define SPI_MEM_SLV_ST_TRANS_END_M  (BIT(5))
-#define SPI_MEM_SLV_ST_TRANS_END_V  0x1
-#define SPI_MEM_SLV_ST_TRANS_END_S  5
-/* SPI_MEM_CSPI_ST_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt of SPI0 cspi_st controlled
- transmitting is done.*/
-#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA  (BIT(4))
-#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_M  (BIT(4))
-#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_V  0x1
-#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_S  4
-/* SPI_MEM_CSPI_ST_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the SPI0 cspi_st controlled transmitting is done.*/
-#define SPI_MEM_CSPI_ST_TRANS_END  (BIT(3))
-#define SPI_MEM_CSPI_ST_TRANS_END_M  (BIT(3))
-#define SPI_MEM_CSPI_ST_TRANS_END_V  0x1
-#define SPI_MEM_CSPI_ST_TRANS_END_S  3
-/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt of SPI0 em_st controlled
- transmitting is done.*/
-#define SPI_MEM_TRANS_END_INT_ENA  (BIT(2))
-#define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(2))
-#define SPI_MEM_TRANS_END_INT_ENA_V  0x1
-#define SPI_MEM_TRANS_END_INT_ENA_S  2
-/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI_CS1 pin enable  1: disable SPI_CS1  0: SPI_CS1 pin is active
- to select SPI device  such as flash  external RAM and so on.*/
-#define SPI_MEM_CS1_DIS  (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (BIT(1))
-#define SPI_MEM_CS1_DIS_V  0x1
-#define SPI_MEM_CS1_DIS_S  1
-/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI_CS0 pin enable  1: disable SPI_CS0  0: SPI_CS0 pin is active
- to select SPI device  such as flash  external RAM and so on.*/
-#define SPI_MEM_CS0_DIS  (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (BIT(0))
-#define SPI_MEM_CS0_DIS_V  0x1
-#define SPI_MEM_CS0_DIS_S  0
-
-#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x038)
-/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: For SPI1  the value of crc32.*/
-#define SPI_MEM_TX_CRC_DATA  0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_S  0
-
-#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x03C)
-/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI1  address phase apply 4 signals. 1: enable 0: disable.
-  The bit is the same with spi_mem_fread_qio.*/
-#define SPI_MEM_FADDR_QUAD  (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
-#define SPI_MEM_FADDR_QUAD_V  0x1
-#define SPI_MEM_FADDR_QUAD_S  8
-/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI1  dout phase apply 4 signals. 1: enable 0: disable.
- The bit is the same with spi_mem_fread_qio.*/
-#define SPI_MEM_FDOUT_QUAD  (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_V  0x1
-#define SPI_MEM_FDOUT_QUAD_S  7
-/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: For SPI1  din phase apply 4 signals. 1: enable 0: disable.  The
- bit is the same with spi_mem_fread_qio.*/
-#define SPI_MEM_FDIN_QUAD  (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
-#define SPI_MEM_FDIN_QUAD_V  0x1
-#define SPI_MEM_FDIN_QUAD_S  6
-/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: For SPI1  address phase apply 2 signals. 1: enable 0: disable.
-  The bit is the same with spi_mem_fread_dio.*/
-#define SPI_MEM_FADDR_DUAL  (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
-#define SPI_MEM_FADDR_DUAL_V  0x1
-#define SPI_MEM_FADDR_DUAL_S  5
-/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: For SPI1  dout phase apply 2 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_fread_dio.*/
-#define SPI_MEM_FDOUT_DUAL  (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_V  0x1
-#define SPI_MEM_FDOUT_DUAL_S  4
-/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI1  din phase apply 2 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_fread_dio.*/
-#define SPI_MEM_FDIN_DUAL  (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
-#define SPI_MEM_FDIN_DUAL_V  0x1
-#define SPI_MEM_FDIN_DUAL_S  3
-/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0   cache  read flash for user define command  1: enable  0:disable.*/
-#define SPI_MEM_CACHE_FLASH_USR_CMD  (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
-#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
-/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0   cache  read flash with 4 bytes address  1: enable  0:disable.*/
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE  (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0  Cache access enable  1: enable  0:disable.*/
-#define SPI_MEM_CACHE_REQ_EN  (BIT(0))
-#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
-#define SPI_MEM_CACHE_REQ_EN_V  0x1
-#define SPI_MEM_CACHE_REQ_EN_S  0
-
-#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x054)
-/* SPI_MEM_CSPI_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
-/*description: The lock delay time of SPI0/1 arbiter by cspi_st  after PER is sent by SPI1.*/
-#define SPI_MEM_CSPI_LOCK_DELAY_TIME  0x0000001F
-#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M  ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S))
-#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V  0x1F
-#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S  7
-/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: The current status of SPI0 master FSM: cspi_st. 0: idle state
-  1:EM_CACHE_GRANT   2: program/erase suspend state  3: SPI0 read data state  4: wait cache/EDMA sent data is stored in SPI0 TX FIFO  5: SPI0 write data state.*/
-#define SPI_MEM_EM_ST  0x00000007
-#define SPI_MEM_EM_ST_M  ((SPI_MEM_EM_ST_V)<<(SPI_MEM_EM_ST_S))
-#define SPI_MEM_EM_ST_V  0x7
-#define SPI_MEM_EM_ST_S  4
-/* SPI_MEM_CSPI_ST : RO ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: The current status of SPI0 slave FSM: cspi_st. 0: idle state
-  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
-#define SPI_MEM_CSPI_ST  0x0000000F
-#define SPI_MEM_CSPI_ST_M  ((SPI_MEM_CSPI_ST_V)<<(SPI_MEM_CSPI_ST_S))
-#define SPI_MEM_CSPI_ST_V  0xF
-#define SPI_MEM_CSPI_ST_S  0
-
-#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x058)
-/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF0  0xFFFFFFFF
-#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
-#define SPI_MEM_BUF0_V  0xFFFFFFFF
-#define SPI_MEM_BUF0_S  0
-
-#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x05C)
-/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF1  0xFFFFFFFF
-#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
-#define SPI_MEM_BUF1_V  0xFFFFFFFF
-#define SPI_MEM_BUF1_S  0
-
-#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x060)
-/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF2  0xFFFFFFFF
-#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
-#define SPI_MEM_BUF2_V  0xFFFFFFFF
-#define SPI_MEM_BUF2_S  0
-
-#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x064)
-/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF3  0xFFFFFFFF
-#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
-#define SPI_MEM_BUF3_V  0xFFFFFFFF
-#define SPI_MEM_BUF3_S  0
-
-#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x068)
-/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF4  0xFFFFFFFF
-#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
-#define SPI_MEM_BUF4_V  0xFFFFFFFF
-#define SPI_MEM_BUF4_S  0
-
-#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x06C)
-/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF5  0xFFFFFFFF
-#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
-#define SPI_MEM_BUF5_V  0xFFFFFFFF
-#define SPI_MEM_BUF5_S  0
-
-#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x070)
-/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF6  0xFFFFFFFF
-#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
-#define SPI_MEM_BUF6_V  0xFFFFFFFF
-#define SPI_MEM_BUF6_S  0
-
-#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x074)
-/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF7  0xFFFFFFFF
-#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
-#define SPI_MEM_BUF7_V  0xFFFFFFFF
-#define SPI_MEM_BUF7_S  0
-
-#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x078)
-/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF8  0xFFFFFFFF
-#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
-#define SPI_MEM_BUF8_V  0xFFFFFFFF
-#define SPI_MEM_BUF8_S  0
-
-#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x07C)
-/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF9  0xFFFFFFFF
-#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
-#define SPI_MEM_BUF9_V  0xFFFFFFFF
-#define SPI_MEM_BUF9_S  0
-
-#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x080)
-/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF10  0xFFFFFFFF
-#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
-#define SPI_MEM_BUF10_V  0xFFFFFFFF
-#define SPI_MEM_BUF10_S  0
-
-#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x084)
-/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF11  0xFFFFFFFF
-#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
-#define SPI_MEM_BUF11_V  0xFFFFFFFF
-#define SPI_MEM_BUF11_S  0
-
-#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x088)
-/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF12  0xFFFFFFFF
-#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
-#define SPI_MEM_BUF12_V  0xFFFFFFFF
-#define SPI_MEM_BUF12_S  0
-
-#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x08C)
-/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF13  0xFFFFFFFF
-#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
-#define SPI_MEM_BUF13_V  0xFFFFFFFF
-#define SPI_MEM_BUF13_S  0
-
-#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x090)
-/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF14  0xFFFFFFFF
-#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
-#define SPI_MEM_BUF14_V  0xFFFFFFFF
-#define SPI_MEM_BUF14_S  0
-
-#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x094)
-/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer*/
-#define SPI_MEM_BUF15  0xFFFFFFFF
-#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
-#define SPI_MEM_BUF15_V  0xFFFFFFFF
-#define SPI_MEM_BUF15_S  0
-
-#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x098)
-/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
-/*description: The dummy cycle length when wait flash idle(RDSR).*/
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN  0x0000003F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
-/*description: The command to wait flash idle(RDSR).*/
-#define SPI_MEM_WAITI_CMD  0x000000FF
-#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
-#define SPI_MEM_WAITI_CMD_V  0xFF
-#define SPI_MEM_WAITI_CMD_S  2
-/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The dummy phase enable when wait flash idle (RDSR)*/
-#define SPI_MEM_WAITI_DUMMY  (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_V  0x1
-#define SPI_MEM_WAITI_DUMMY_S  1
-
-#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x09C)
-/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
-/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0]
- times  it will be treated as check pass.*/
-#define SPI_MEM_SUS_TIMEOUT_CNT  0x0000007F
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
-/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure
- the suspend status of flash. 0: Only need to check WIP is 0.*/
-#define SPI_MEM_PES_END_EN  (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (BIT(24))
-#define SPI_MEM_PES_END_EN_V  0x1
-#define SPI_MEM_PES_END_EN_S  24
-/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure
- the resume status of flash. 0: Only need to check WIP is 0.*/
-#define SPI_MEM_PER_END_EN  (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (BIT(23))
-#define SPI_MEM_PER_END_EN_V  0x1
-#define SPI_MEM_PER_END_EN_S  23
-/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit.
- 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
-#define SPI_MEM_FMEM_RD_SUS_2B  (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
-#define SPI_MEM_FMEM_RD_SUS_2B_S  22
-/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
-/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read
- status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out  status_in[15:0] is valid when two bytes of data are read out)  SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
-#define SPI_MEM_PESR_END_MSK  0x0000FFFF
-#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
-#define SPI_MEM_PESR_END_MSK_V  0xFFFF
-#define SPI_MEM_PESR_END_MSK_S  6
-/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable Auto-suspending function.*/
-#define SPI_MEM_FLASH_PES_EN  (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_V  0x1
-#define SPI_MEM_FLASH_PES_EN_S  5
-/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable PES transfer trigger PES transfer option.
- If this bit is 0  application should send PER after PES is done.*/
-#define SPI_MEM_PES_PER_EN  (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (BIT(4))
-#define SPI_MEM_PES_PER_EN_V  0x1
-#define SPI_MEM_PES_PER_EN_S  4
-/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
- * 4) SPI_CLK cycles after program erase suspend.*/
-#define SPI_MEM_FLASH_PES_WAIT_EN  (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
- * 4) SPI_CLK cycles after program erase resume.*/
-#define SPI_MEM_FLASH_PER_WAIT_EN  (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program erase suspend bit  program erase suspend operation will
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_PES  (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (BIT(1))
-#define SPI_MEM_FLASH_PES_V  0x1
-#define SPI_MEM_FLASH_PES_S  1
-/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: program erase resume bit  program erase suspend operation will
- be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-#define SPI_MEM_FLASH_PER  (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (BIT(0))
-#define SPI_MEM_FLASH_PER_V  0x1
-#define SPI_MEM_FLASH_PER_S  0
-
-#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A0)
-/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
-/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should
- be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
-#define SPI_MEM_WAIT_PESR_COMMAND  0x0000FFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
-/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:8] ;default: 8'h75 ; */
-/*description: Program/Erase suspend command.*/
-#define SPI_MEM_FLASH_PES_COMMAND  0x000000FF
-#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
-#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
-#define SPI_MEM_FLASH_PES_COMMAND_S  8
-/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[7:0] ;default: 8'h7a ; */
-/*description: Program/Erase resume command.*/
-#define SPI_MEM_FLASH_PER_COMMAND  0x000000FF
-#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
-#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
-#define SPI_MEM_FLASH_PER_COMMAND_S  0
-
-#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A4)
-/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
-#define SPI_MEM_SPI0_LOCK_EN  (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_V  0x1
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
- * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
-#define SPI_MEM_FLASH_PES_DLY_128  (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
- * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
-#define SPI_MEM_FLASH_PER_DLY_128  (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
- cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
-#define SPI_MEM_FLASH_DP_DLY_128  (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
- cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
-#define SPI_MEM_FLASH_RES_DLY_128  (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
- cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
-#define SPI_MEM_FLASH_HPM_DLY_128  (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2
- bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
-#define SPI_MEM_WAIT_PESR_CMD_2B  (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The status of flash suspend  only used in SPI1.*/
-#define SPI_MEM_FLASH_SUS  (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (BIT(0))
-#define SPI_MEM_FLASH_SUS_V  0x1
-#define SPI_MEM_FLASH_SUS_S  0
-
-#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A8)
-/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: add extra dummy spi clock cycle length for spi clock calibration.*/
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN  0x00000007
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable timing auto-calibration for all reading operations.*/
-#define SPI_MEM_TIMING_CALI  (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_TIMING_CALI_V  0x1
-#define SPI_MEM_TIMING_CALI_S  1
-/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable timing adjust clock for all reading operations.*/
-#define SPI_MEM_TIMING_CLK_ENA  (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0AC)
-/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles  0: input
- without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
-#define SPI_MEM_DIN3_MODE  0x00000003
-#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
-#define SPI_MEM_DIN3_MODE_V  0x3
-#define SPI_MEM_DIN3_MODE_S  6
-/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles  0: input
- without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
-#define SPI_MEM_DIN2_MODE  0x00000003
-#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
-#define SPI_MEM_DIN2_MODE_V  0x3
-#define SPI_MEM_DIN2_MODE_S  4
-/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles  0: input
- without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
-#define SPI_MEM_DIN1_MODE  0x00000003
-#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
-#define SPI_MEM_DIN1_MODE_V  0x3
-#define SPI_MEM_DIN1_MODE_S  2
-/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles  0: input
- without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
-#define SPI_MEM_DIN0_MODE  0x00000003
-#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
-#define SPI_MEM_DIN0_MODE_V  0x3
-#define SPI_MEM_DIN0_MODE_S  0
-
-#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B0)
-/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles  0: delayed
- by 1 cycle  1: delayed by 2 cycles ...*/
-#define SPI_MEM_DIN3_NUM  0x00000003
-#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
-#define SPI_MEM_DIN3_NUM_V  0x3
-#define SPI_MEM_DIN3_NUM_S  6
-/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles  0: delayed
- by 1 cycle  1: delayed by 2 cycles ...*/
-#define SPI_MEM_DIN2_NUM  0x00000003
-#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
-#define SPI_MEM_DIN2_NUM_V  0x3
-#define SPI_MEM_DIN2_NUM_S  4
-/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles  0: delayed
- by 1 cycle  1: delayed by 2 cycles ...*/
-#define SPI_MEM_DIN1_NUM  0x00000003
-#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
-#define SPI_MEM_DIN1_NUM_V  0x3
-#define SPI_MEM_DIN1_NUM_S  2
-/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles  0: delayed
- by 1 cycle  1: delayed by 2 cycles ...*/
-#define SPI_MEM_DIN0_NUM  0x00000003
-#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
-#define SPI_MEM_DIN0_NUM_V  0x3
-#define SPI_MEM_DIN0_NUM_S  0
-
-#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B4)
-/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles  0: output
- without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
-#define SPI_MEM_DOUT3_MODE  (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_DOUT3_MODE_S  3
-/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles  0: output
- without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
-#define SPI_MEM_DOUT2_MODE  (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_DOUT2_MODE_S  2
-/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles  0: output
- without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
-#define SPI_MEM_DOUT1_MODE  (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_DOUT1_MODE_S  1
-/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles  0: output
- without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
-#define SPI_MEM_DOUT0_MODE  (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C0)
-/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-#define SPI_MEM_MST_ST_END_INT_ENA  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-#define SPI_MEM_SLV_ST_END_INT_ENA  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
-#define SPI_MEM_WPE_END_INT_ENA  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_V  0x1
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PES_END_INT interrupt.*/
-#define SPI_MEM_PES_END_INT_ENA  (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_V  0x1
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PER_END_INT interrupt.*/
-#define SPI_MEM_PER_END_INT_ENA  (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_V  0x1
-#define SPI_MEM_PER_END_INT_ENA_S  0
-
-#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C4)
-/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-#define SPI_MEM_MST_ST_END_INT_CLR  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-#define SPI_MEM_SLV_ST_END_INT_CLR  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
-#define SPI_MEM_WPE_END_INT_CLR  (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_V  0x1
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PES_END_INT interrupt.*/
-#define SPI_MEM_PES_END_INT_CLR  (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_V  0x1
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PER_END_INT interrupt.*/
-#define SPI_MEM_PER_END_INT_CLR  (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_V  0x1
-#define SPI_MEM_PER_END_INT_CLR_S  0
-
-#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C8)
-/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered
- when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
-#define SPI_MEM_MST_ST_END_INT_RAW  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered
- when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
-#define SPI_MEM_SLV_ST_END_INT_RAW  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when
- WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
-#define SPI_MEM_WPE_END_INT_RAW  (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_V  0x1
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when
- Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
-#define SPI_MEM_PES_END_INT_RAW  (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_V  0x1
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when
- Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
-#define SPI_MEM_PER_END_INT_RAW  (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_V  0x1
-#define SPI_MEM_PER_END_INT_RAW_S  0
-
-#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0CC)
-/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-#define SPI_MEM_MST_ST_END_INT_ST  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-#define SPI_MEM_SLV_ST_END_INT_ST  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_WPE_END_INT interrupt.*/
-#define SPI_MEM_WPE_END_INT_ST  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_V  0x1
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PES_END_INT interrupt.*/
-#define SPI_MEM_PES_END_INT_ST  (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_V  0x1
-#define SPI_MEM_PES_END_INT_ST_S  1
-/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PER_END_INT interrupt.*/
-#define SPI_MEM_PER_END_INT_ST  (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_V  0x1
-#define SPI_MEM_PER_END_INT_ST_S  0
-
-#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0DC)
-/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable.*/
-#define SPI_MEM_CLK_EN  (BIT(0))
-#define SPI_MEM_CLK_EN_M  (BIT(0))
-#define SPI_MEM_CLK_EN_V  0x1
-#define SPI_MEM_CLK_EN_S  0
-
-#define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0E0)
-/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: When the digital system clock selects PLL clock and the frequency
- of PLL clock is 480MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
-#define SPI_MEM_SPI01_CLK_SEL  0x00000003
-#define SPI_MEM_SPI01_CLK_SEL_M  ((SPI_MEM_SPI01_CLK_SEL_V)<<(SPI_MEM_SPI01_CLK_SEL_S))
-#define SPI_MEM_SPI01_CLK_SEL_V  0x3
-#define SPI_MEM_SPI01_CLK_SEL_S  0
-
-#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
-/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007170 ; */
-/*description: Version control register*/
-#define SPI_MEM_DATE  0x0FFFFFFF
-#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
-#define SPI_MEM_DATE_V  0xFFFFFFF
-#define SPI_MEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/spi_mem_struct.h b/components/soc/esp32c3/include/soc/spi_mem_struct.h
deleted file mode 100644
index d816a9a290a..00000000000
--- a/components/soc/esp32c3/include/soc/spi_mem_struct.h
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct spi_mem_dev_s {
-    union {
-        struct {
-            uint32_t mst_st:         4;                 /*The current status of SPI1 master FSM.*/
-            uint32_t st:             4;                 /*The current status of SPI1 slave FSM: mspi_st. 0: idle state  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
-            uint32_t reserved8:      9;                 /*reserved*/
-            uint32_t flash_pe:       1;                 /*In user mode  it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t usr:            1;                 /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_hpm:      1;                 /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_res:      1;                 /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_dp:       1;                 /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_ce:       1;                 /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_be:       1;                 /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_se:       1;                 /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_pp:       1;                 /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
-            uint32_t flash_wrsr:     1;                 /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_rdsr:     1;                 /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_rdid:     1;                 /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-            uint32_t flash_wrdi:     1;                 /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-            uint32_t flash_wren:     1;                 /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-            uint32_t flash_read:     1;                 /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;                                      /*SPI1 address register*/
-    union {
-        struct {
-            uint32_t reserved0:       3;                /*reserved*/
-            uint32_t fdummy_out:      1;                /*In the dummy phase the signal level of spi is output by the spi controller.*/
-            uint32_t reserved4:       3;                /*reserved*/
-            uint32_t fcmd_dual:       1;                /*Apply 2 signals during command phase 1:enable 0: disable*/
-            uint32_t fcmd_quad:       1;                /*Apply 4 signals during command phase 1:enable 0: disable*/
-            uint32_t reserved9:       1;                /*reserved*/
-            uint32_t fcs_crc_en:      1;                /*For SPI1   initialize crc32 module before writing encrypted data to flash. Active low.*/
-            uint32_t tx_crc_en:       1;                /*For SPI1   enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
-            uint32_t reserved12:      1;                /*reserved*/
-            uint32_t fastrd_mode:     1;                /*This bit enable the bits: spi_mem_fread_qio  spi_mem_fread_dio  spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
-            uint32_t fread_dual:      1;                /*In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
-            uint32_t resandres:       1;                /*The Device ID is read out to SPI_MEM_RD_STATUS register   this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
-            uint32_t reserved16:      2;                /*reserved*/
-            uint32_t q_pol:           1;                /*The bit is used to set MISO line polarity  1: high 0  low*/
-            uint32_t d_pol:           1;                /*The bit is used to set MOSI line polarity  1: high 0  low*/
-            uint32_t fread_quad:      1;                /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
-            uint32_t wp:              1;                /*Write protect signal output when SPI is idle.  1: output high  0: output low.*/
-            uint32_t wrsr_2b:         1;                /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
-            uint32_t fread_dio:       1;                /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
-            uint32_t fread_qio:       1;                /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
-            uint32_t reserved25:      7;                /*reserved*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clk_mode:            2;            /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
-            uint32_t cs_hold_dly_res:    10;            /*After RES/DP/HPM command is sent  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
-            uint32_t reserved2:           18;               /*reserved*/
-            uint32_t rxfifo_rst:       1;               /*SPI0 RX FIFO reset signal.*/
-            uint32_t rxfifo_wfull_err: 1;               /*1: SPI0 RX FIFO write full error  Cache/EDMA do not read all the data out. 0: Not error.*/
-        };
-        uint32_t val;
-    } ctrl1;
-    union {
-        struct {
-            uint32_t cs_setup_time: 5;                  /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
-            uint32_t cs_hold_time:  5;                  /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
-            uint32_t reserved10:       15;                  /*reserved*/
-            uint32_t cs_hold_delay: 6;                  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t sync_reset:    1;                  /*The FSM will be reset.*/
-        };
-        uint32_t val;
-    } ctrl2;
-    union {
-        struct {
-            uint32_t clkcnt_l:       8;                 /*In the master mode it must be equal to spi_mem_clkcnt_N.*/
-            uint32_t clkcnt_h:       8;                 /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t clkcnt_n:       8;                 /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24:         7;                 /*reserved*/
-            uint32_t clk_equ_sysclk: 1;                 /*Set this bit in 1-division mode.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t reserved0:          6;                 /*reserved*/
-            uint32_t cs_hold:        1;                 /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
-            uint32_t cs_setup:       1;                 /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
-            uint32_t reserved8:          1;                 /*reserved*/
-            uint32_t ck_out_edge:       1;          /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
-            uint32_t reserved10:            2;          /*reserved*/
-            uint32_t fwrite_dual:       1;          /*In the write operations read-data phase apply 2 signals*/
-            uint32_t fwrite_quad:       1;          /*In the write operations read-data phase apply 4 signals*/
-            uint32_t fwrite_dio:        1;          /*In the write operations address phase and read-data phase apply 2 signals.*/
-            uint32_t fwrite_qio:        1;          /*In the write operations address phase and read-data phase apply 4 signals.*/
-            uint32_t reserved16:            8;          /*reserved*/
-            uint32_t usr_miso_highpart: 1;          /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
-            uint32_t usr_mosi_highpart: 1;          /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
-            uint32_t usr_dummy_idle:    1;          /*SPI clock is disable in dummy phase when the bit is enable.*/
-            uint32_t usr_mosi:          1;          /*This bit enable the write-data phase of an operation.*/
-            uint32_t usr_miso:          1;          /*This bit enable the read-data phase of an operation.*/
-            uint32_t usr_dummy:         1;          /*This bit enable the dummy phase of an operation.*/
-            uint32_t usr_addr:          1;          /*This bit enable the address phase of an operation.*/
-            uint32_t usr_command:       1;          /*This bit enable the command phase of an operation.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen:     6;         /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
-            uint32_t reserved6:             20;         /*reserved*/
-            uint32_t usr_addr_bitlen:        6;         /*The length in bits of address phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value:     16;         /*The value of  command.*/
-            uint32_t reserved16:            12;         /*reserved*/
-            uint32_t usr_command_bitlen:     4;         /*The length in bits of command phase. The register value shall be (bit_num-1)*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t usr_mosi_bit_len:    10;           /*The length in bits of write-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10:          22;           /*reserved*/
-        };
-        uint32_t val;
-    } mosi_dlen;
-    union {
-        struct {
-            uint32_t usr_miso_bit_len:    10;           /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10:          22;           /*reserved*/
-        };
-        uint32_t val;
-    } miso_dlen;
-    union {
-        struct {
-            uint32_t status:     16;                    /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
-            uint32_t wb_mode:     8;                    /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t reserved24:  8;                    /*reserved*/
-        };
-        uint32_t val;
-    } rd_status;
-    uint32_t reserved_30;
-    union {
-        struct {
-            uint32_t cs0_dis:            1;             /*SPI_CS0 pin enable  1: disable SPI_CS0  0: SPI_CS0 pin is active to select SPI device  such as flash  external RAM and so on.*/
-            uint32_t cs1_dis:            1;             /*SPI_CS1 pin enable  1: disable SPI_CS1  0: SPI_CS1 pin is active to select SPI device  such as flash  external RAM and so on.*/
-            uint32_t reserved2:          1;             /*reserved*/
-            uint32_t mst_st_trans_end:         1;       /*The bit is used to indicate the  spi0_mst_st controlled transmitting is done.*/
-            uint32_t mst_st_trans_end_en:      1;       /*The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.*/
-            uint32_t st_trans_end:             1;       /*The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
-            uint32_t st_trans_end_en:          1;       /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
-            uint32_t reserved7:                    2;       /*reserved*/
-            uint32_t ck_idle_edge:       1;             /*1: spi clk line is high when idle     0: spi clk line is low when idle*/
-            uint32_t cs_keep_active:     1;             /*spi cs line keep low when the bit is set.*/
-            uint32_t reserved11:                  21;       /*reserved*/
-        };
-        uint32_t val;
-    } misc;
-    uint32_t tx_crc;                                    /*SPI1 TX CRC data register.*/
-    union {
-        struct {
-            uint32_t req_en:               1;           /*For SPI0  Cache access enable  1: enable  0:disable.*/
-            uint32_t usr_addr_4byte:           1;       /*For SPI1   cache  read flash with 4 bytes address  1: enable  0:disable.*/
-            uint32_t flash_usr_cmd:        1;           /*For SPI0   cache  read flash for user define command  1: enable  0:disable.*/
-            uint32_t fdin_dual:                1;       /*For SPI1  din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdout_dual:               1;       /*For SPI1  dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t faddr_dual:               1;       /*For SPI1  address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdin_quad:                1;       /*For SPI1  din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t fdout_quad:               1;       /*For SPI1  dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t faddr_quad:               1;       /*For SPI1  address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t reserved9:               23;       /*reserved*/
-        };
-        uint32_t val;
-    } cache_fctrl;
-    uint32_t reserved_40;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    union {
-        struct {
-            uint32_t spi0_st:              4;           /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
-            uint32_t spi0_mst_st:          3;           /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state  1:EM_CACHE_GRANT   2: program/erase suspend state  3: SPI0 read data state  4: wait cache/EDMA sent data is stored in SPI0 TX FIFO  5: SPI0 write data state.*/
-            uint32_t cspi_lock_delay_time: 5;           /*The lock delay time of SPI0/1 arbiter by spi0_slv_st  after PER is sent by SPI1.*/
-            uint32_t reserved12:              20;           /*reserved*/
-        };
-        uint32_t val;
-    } fsm;
-    uint32_t data_buf[16];
-    union {
-        struct {
-            uint32_t reserved0:                1;       /*reserved*/
-            uint32_t waiti_dummy:              1;       /*The dummy phase enable when wait flash idle (RDSR)*/
-            uint32_t waiti_cmd:                8;       /*The command to wait flash idle(RDSR).*/
-            uint32_t waiti_dummy_cyclelen:     6;       /*The dummy cycle length when wait flash idle(RDSR).*/
-            uint32_t reserved16:              16;       /*reserved*/
-        };
-        uint32_t val;
-    } flash_waiti_ctrl;
-    union {
-        struct {
-            uint32_t flash_per:             1;          /*program erase resume bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_pes:             1;          /*program erase suspend bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
-            uint32_t flash_per_wait_en:     1;          /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after program erase suspend.*/
-            uint32_t flash_pes_wait_en:     1;          /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after program erase suspend.*/
-            uint32_t pes_per_en:            1;          /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0  application should send PER after PES is done.*/
-            uint32_t flash_pes_en:          1;          /*Set this bit to enable Auto-suspending function.*/
-            uint32_t pesr_end_msk:         16;          /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out  status_in[15:0] is valid when two bytes of data are read out)  SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
-            uint32_t frd_sus_2b:            1;          /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
-            uint32_t per_end_en:            1;          /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t pes_end_en:            1;          /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t sus_timeout_cnt:       7;          /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times  it will be treated as check pass.*/
-        };
-        uint32_t val;
-    } flash_sus_ctrl;
-    union {
-        struct {
-            uint32_t flash_per_command:     8;          /*Program/Erase resume command.*/
-            uint32_t flash_pes_command:     8;          /*Program/Erase suspend command.*/
-            uint32_t wait_pesr_command:    16;          /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
-        };
-        uint32_t val;
-    } flash_sus_cmd;
-    union {
-        struct {
-            uint32_t flash_sus:     1;                  /*The status of flash suspend  only used in SPI1.*/
-            uint32_t wait_pesr_cmd_2b:1;
-            uint32_t hpm_dly_128:   1;
-            uint32_t res_dly_128:   1;
-            uint32_t dp_dly_128:    1;
-            uint32_t per_dly_128:   1;
-            uint32_t pes_dly_128:   1;
-            uint32_t spi0_lock_en:  1;
-            uint32_t reserved1:    24;                  /*reserved*/
-        };
-        uint32_t val;
-    } sus_status;
-    union {
-        struct {
-            uint32_t timing_clk_ena:       1;           /*The bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t timing_cali:              1;       /*The bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t extra_dummy_cyclelen:     3;       /*add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t reserved5:               27;           /*reserved*/
-        };
-        uint32_t val;
-    } timing_cali;
-    union {
-        struct {
-            uint32_t din0_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
-            uint32_t din1_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
-            uint32_t din2_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
-            uint32_t din3_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
-            uint32_t reserved8:    24;                      /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
-            uint32_t din1_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
-            uint32_t din2_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
-            uint32_t din3_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
-            uint32_t reserved8:   24;                       /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
-            uint32_t dout1_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
-            uint32_t dout2_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
-            uint32_t dout3_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
-            uint32_t reserved4:     28;                     /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    union {
-        struct {
-            uint32_t per_end_int_ena:        1;         /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_int_ena:        1;         /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end_int_ena:        1;         /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t st_end_int_ena:         1;         /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end_int_ena:     1;         /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t reserved5:             27;         /*reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t per_end:                1;         /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end:                1;         /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end:                1;         /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t st_end:                 1;         /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end:             1;         /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t reserved5:             27;         /*reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t per_end:                1;         /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
-            uint32_t pes_end:                1;         /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
-            uint32_t wpe_end:                1;         /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
-            uint32_t st_end:                 1;         /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
-            uint32_t mst_st_end:             1;         /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
-            uint32_t reserved5:             27;         /*reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t per_end:               1;          /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end:               1;          /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end:               1;          /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t st_end:                1;          /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end:            1;          /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t reserved5:            27;          /*reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    union {
-        struct {
-            uint32_t clk_en:     1;                     /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
-            uint32_t reserved1: 31;                         /*reserved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    union {
-        struct {
-            uint32_t spi01_clk_sel: 2;                  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
-            uint32_t reserved2:        30;                  /*reserved*/
-        };
-        uint32_t val;
-    } core_clk_sel;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t date:      28;                     /*Version control register*/
-            uint32_t reserved28: 4;                     /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_mem_dev_t;
-extern spi_mem_dev_t SPIMEM0;
-extern spi_mem_dev_t SPIMEM1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/spi_reg.h b/components/soc/esp32c3/include/soc/spi_reg.h
deleted file mode 100644
index 361f58ba5c5..00000000000
--- a/components/soc/esp32c3/include/soc/spi_reg.h
+++ /dev/null
@@ -1,1435 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SPI_REG_H_
-#define _SOC_SPI_REG_H_
-
-#include "soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
-/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: User define command enable.  An operation will be triggered when the bit is set.
- The bit will be cleared once the operation done.1: enable 0: disable. Can not b
-e changed by CONF_buf..*/
-#define SPI_USR    (BIT(24))
-#define SPI_USR_M  (BIT(24))
-#define SPI_USR_V  0x1
-#define SPI_USR_S  24
-/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
-clock domain, which is only used in SPI master mode..*/
-#define SPI_UPDATE    (BIT(23))
-#define SPI_UPDATE_M  (BIT(23))
-#define SPI_UPDATE_V  0x1
-#define SPI_UPDATE_S  23
-/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: Define the APB cycles of  SPI_CONF state. Can be configured in CONF state..*/
-#define SPI_CONF_BITLEN    0x0003FFFF
-#define SPI_CONF_BITLEN_M  ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
-#define SPI_CONF_BITLEN_V  0x3FFFF
-#define SPI_CONF_BITLEN_S  0
-
-#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
-/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Address to slave. Can be configured in CONF state..*/
-#define SPI_USR_ADDR_VALUE    0xFFFFFFFF
-#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
-#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_USR_ADDR_VALUE_S  0
-
-#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
-/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
-figured in CONF state..*/
-#define SPI_WR_BIT_ORDER    (BIT(26))
-#define SPI_WR_BIT_ORDER_M  (BIT(26))
-#define SPI_WR_BIT_ORDER_V  0x1
-#define SPI_WR_BIT_ORDER_S  26
-/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
-tate..*/
-#define SPI_RD_BIT_ORDER    (BIT(25))
-#define SPI_RD_BIT_ORDER_M  (BIT(25))
-#define SPI_RD_BIT_ORDER_V  0x1
-#define SPI_RD_BIT_ORDER_S  25
-/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
-an be configured in CONF state..*/
-#define SPI_WP_POL    (BIT(21))
-#define SPI_WP_POL_M  (BIT(21))
-#define SPI_WP_POL_V  0x1
-#define SPI_WP_POL_S  21
-/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co
-nfigured in CONF state..*/
-#define SPI_HOLD_POL    (BIT(20))
-#define SPI_HOLD_POL_M  (BIT(20))
-#define SPI_HOLD_POL_V  0x1
-#define SPI_HOLD_POL_S  20
-/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-CONF state..*/
-#define SPI_D_POL    (BIT(19))
-#define SPI_D_POL_M  (BIT(19))
-#define SPI_D_POL_V  0x1
-#define SPI_D_POL_S  19
-/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-CONF state..*/
-#define SPI_Q_POL    (BIT(18))
-#define SPI_Q_POL_M  (BIT(18))
-#define SPI_Q_POL_V  0x1
-#define SPI_Q_POL_S  18
-/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  C
-an be configured in CONF state..*/
-#define SPI_FREAD_QUAD    (BIT(15))
-#define SPI_FREAD_QUAD_M  (BIT(15))
-#define SPI_FREAD_QUAD_V  0x1
-#define SPI_FREAD_QUAD_S  15
-/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C
-an be configured in CONF state..*/
-#define SPI_FREAD_DUAL    (BIT(14))
-#define SPI_FREAD_DUAL_M  (BIT(14))
-#define SPI_FREAD_DUAL_V  0x1
-#define SPI_FREAD_DUAL_S  14
-/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
-ONF state..*/
-#define SPI_FCMD_QUAD    (BIT(9))
-#define SPI_FCMD_QUAD_M  (BIT(9))
-#define SPI_FCMD_QUAD_V  0x1
-#define SPI_FCMD_QUAD_S  9
-/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C
-ONF state..*/
-#define SPI_FCMD_DUAL    (BIT(8))
-#define SPI_FCMD_DUAL_M  (BIT(8))
-#define SPI_FCMD_DUAL_V  0x1
-#define SPI_FCMD_DUAL_S  8
-/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- state..*/
-#define SPI_FADDR_QUAD    (BIT(6))
-#define SPI_FADDR_QUAD_M  (BIT(6))
-#define SPI_FADDR_QUAD_V  0x1
-#define SPI_FADDR_QUAD_S  6
-/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- state..*/
-#define SPI_FADDR_DUAL    (BIT(5))
-#define SPI_FADDR_DUAL_M  (BIT(5))
-#define SPI_FADDR_DUAL_V  0x1
-#define SPI_FADDR_DUAL_S  5
-/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: In the dummy phase the signal level of spi is output by the spi controller. Can
-be configured in CONF state..*/
-#define SPI_DUMMY_OUT    (BIT(3))
-#define SPI_DUMMY_OUT_M  (BIT(3))
-#define SPI_DUMMY_OUT_V  0x1
-#define SPI_DUMMY_OUT_S  3
-
-#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0xC)
-/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst
-em clock. Can be configured in CONF state..*/
-#define SPI_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_V  0x1
-#define SPI_CLK_EQU_SYSCLK_S  31
-/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
-/*description: In the master mode it is pre-divider of spi_clk.  Can be configured in CONF stat
-e..*/
-#define SPI_CLKDIV_PRE    0x0000000F
-#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
-#define SPI_CLKDIV_PRE_V  0xF
-#define SPI_CLKDIV_PRE_S  18
-/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
-/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/
-(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
-#define SPI_CLKCNT_N    0x0000003F
-#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
-#define SPI_CLKCNT_N_V  0x3F
-#define SPI_CLKCNT_N_S  12
-/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
-/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-must be 0. Can be configured in CONF state..*/
-#define SPI_CLKCNT_H    0x0000003F
-#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
-#define SPI_CLKCNT_H_V  0x3F
-#define SPI_CLKCNT_H_S  6
-/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
-/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b
-e 0. Can be configured in CONF state..*/
-#define SPI_CLKCNT_L    0x0000003F
-#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
-#define SPI_CLKCNT_L_V  0x3F
-#define SPI_CLKCNT_L_S  0
-
-#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x10)
-/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation. Can be configured in CONF sta
-te..*/
-#define SPI_USR_COMMAND    (BIT(31))
-#define SPI_USR_COMMAND_M  (BIT(31))
-#define SPI_USR_COMMAND_V  0x1
-#define SPI_USR_COMMAND_S  31
-/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation. Can be configured in CONF sta
-te..*/
-#define SPI_USR_ADDR    (BIT(30))
-#define SPI_USR_ADDR_M  (BIT(30))
-#define SPI_USR_ADDR_V  0x1
-#define SPI_USR_ADDR_S  30
-/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
-..*/
-#define SPI_USR_DUMMY    (BIT(29))
-#define SPI_USR_DUMMY_M  (BIT(29))
-#define SPI_USR_DUMMY_V  0x1
-#define SPI_USR_DUMMY_S  29
-/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s
-tate..*/
-#define SPI_USR_MISO    (BIT(28))
-#define SPI_USR_MISO_M  (BIT(28))
-#define SPI_USR_MISO_V  0x1
-#define SPI_USR_MISO_S  28
-/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation. Can be configured in CONF
-state..*/
-#define SPI_USR_MOSI    (BIT(27))
-#define SPI_USR_MOSI_M  (BIT(27))
-#define SPI_USR_MOSI_V  0x1
-#define SPI_USR_MOSI_S  27
-/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
- CONF state..*/
-#define SPI_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_USR_DUMMY_IDLE_V  0x1
-#define SPI_USR_DUMMY_IDLE_S  26
-/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl
-e 0: disable.  Can be configured in CONF state..*/
-#define SPI_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_V  0x1
-#define SPI_USR_MOSI_HIGHPART_S  25
-/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
- 0: disable. Can be configured in CONF state..*/
-#define SPI_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_USR_MISO_HIGHPART_V  0x1
-#define SPI_USR_MISO_HIGHPART_S  24
-/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha
-re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/
-#define SPI_SIO    (BIT(17))
-#define SPI_SIO_M  (BIT(17))
-#define SPI_SIO_V  0x1
-#define SPI_SIO_S  17
-/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-will continue. 0: The seg-trans will end after the current SPI seg-trans or this
- is not seg-trans mode. Can be configured in CONF state..*/
-#define SPI_USR_CONF_NXT    (BIT(15))
-#define SPI_USR_CONF_NXT_M  (BIT(15))
-#define SPI_USR_CONF_NXT_V  0x1
-#define SPI_USR_CONF_NXT_S  15
-/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO
-NF state..*/
-#define SPI_FWRITE_QUAD    (BIT(13))
-#define SPI_FWRITE_QUAD_M  (BIT(13))
-#define SPI_FWRITE_QUAD_V  0x1
-#define SPI_FWRITE_QUAD_S  13
-/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO
-NF state..*/
-#define SPI_FWRITE_DUAL    (BIT(12))
-#define SPI_FWRITE_DUAL_M  (BIT(12))
-#define SPI_FWRITE_DUAL_V  0x1
-#define SPI_FWRITE_DUAL_S  12
-/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca
-n be configured in CONF state..*/
-#define SPI_CK_OUT_EDGE    (BIT(9))
-#define SPI_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_CK_OUT_EDGE_V  0x1
-#define SPI_CK_OUT_EDGE_S  9
-/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
-= !spi_ck_i. 1:rsck = spi_ck_i..*/
-#define SPI_RSCK_I_EDGE    (BIT(8))
-#define SPI_RSCK_I_EDGE_M  (BIT(8))
-#define SPI_RSCK_I_EDGE_V  0x1
-#define SPI_RSCK_I_EDGE_S  8
-/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be co
-nfigured in CONF state..*/
-#define SPI_CS_SETUP    (BIT(7))
-#define SPI_CS_SETUP_M  (BIT(7))
-#define SPI_CS_SETUP_V  0x1
-#define SPI_CS_SETUP_S  7
-/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be config
-ured in CONF state..*/
-#define SPI_CS_HOLD    (BIT(6))
-#define SPI_CS_HOLD_M  (BIT(6))
-#define SPI_CS_HOLD_V  0x1
-#define SPI_CS_HOLD_S  6
-/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
-= spi_ck_i. 1:tsck = !spi_ck_i..*/
-#define SPI_TSCK_I_EDGE    (BIT(5))
-#define SPI_TSCK_I_EDGE_M  (BIT(5))
-#define SPI_TSCK_I_EDGE_V  0x1
-#define SPI_TSCK_I_EDGE_S  5
-/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others
-. Can be configured in CONF state..*/
-#define SPI_QPI_MODE    (BIT(3))
-#define SPI_QPI_MODE_M  (BIT(3))
-#define SPI_QPI_MODE_V  0x1
-#define SPI_QPI_MODE_S  3
-/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUTDIN    (BIT(0))
-#define SPI_DOUTDIN_M  (BIT(0))
-#define SPI_DOUTDIN_V  0x1
-#define SPI_DOUTDIN_S  0
-
-#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x14)
-/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca
-n be configured in CONF state..*/
-#define SPI_USR_ADDR_BITLEN    0x0000001F
-#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
-#define SPI_USR_ADDR_BITLEN_V  0x1F
-#define SPI_USR_ADDR_BITLEN_S  27
-/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */
-/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
- Can be configured in CONF state..*/
-#define SPI_CS_HOLD_TIME    0x0000001F
-#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
-#define SPI_CS_HOLD_TIME_V  0x1F
-#define SPI_CS_HOLD_TIME_S  22
-/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
-/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu
-p bit. Can be configured in CONF state..*/
-#define SPI_CS_SETUP_TIME    0x0000001F
-#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
-#define SPI_CS_SETUP_TIME_V  0x1F
-#define SPI_CS_SETUP_TIME_S  17
-/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
- FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
- in GP-SPI master FD/HD-mode..*/
-#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_M  (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_V  0x1
-#define SPI_MST_WFULL_ERR_END_EN_S  16
-/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
-/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_
-num-1). Can be configured in CONF state..*/
-#define SPI_USR_DUMMY_CYCLELEN    0x000000FF
-#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
-#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x18)
-/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca
-n be configured in CONF state..*/
-#define SPI_USR_COMMAND_BITLEN    0x0000000F
-#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
-#define SPI_USR_COMMAND_BITLEN_V  0xF
-#define SPI_USR_COMMAND_BITLEN_S  28
-/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
-/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
-aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro
-r is valid in GP-SPI master FD/HD-mode..*/
-#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_M  (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_V  0x1
-#define SPI_MST_REMPTY_ERR_END_EN_S  27
-/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command. Can be configured in CONF state..*/
-#define SPI_USR_COMMAND_VALUE    0x0000FFFF
-#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
-#define SPI_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_USR_COMMAND_VALUE_S  0
-
-#define SPI_MS_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x1C)
-/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
-/*description: The value of these bits is the configured SPI transmission data bit length in ma
-ster mode DMA controlled transfer or CPU controlled transfer. The value is also
-the configured bit length in slave mode DMA RX controlled transfer. The register
- value shall be (bit_num-1). Can be configured in CONF state..*/
-#define SPI_MS_DATA_BITLEN    0x0003FFFF
-#define SPI_MS_DATA_BITLEN_M  ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
-#define SPI_MS_DATA_BITLEN_V  0x3FFFF
-#define SPI_MS_DATA_BITLEN_S  0
-
-#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
-/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configur
-ed in CONF state..*/
-#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
-#define SPI_QUAD_DIN_PIN_SWAP_S  31
-/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/
-#define SPI_CS_KEEP_ACTIVE    (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_V  0x1
-#define SPI_CS_KEEP_ACTIVE_S  30
-/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle. Can be c
-onfigured in CONF state..*/
-#define SPI_CK_IDLE_EDGE    (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (BIT(29))
-#define SPI_CK_IDLE_EDGE_V  0x1
-#define SPI_CK_IDLE_EDGE_S  29
-/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
-CONF state..*/
-#define SPI_SLAVE_CS_POL    (BIT(23))
-#define SPI_SLAVE_CS_POL_M  (BIT(23))
-#define SPI_SLAVE_CS_POL_V  0x1
-#define SPI_SLAVE_CS_POL_S  23
-/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
-/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva
-lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/
-#define SPI_MASTER_CS_POL    0x0000003F
-#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
-#define SPI_MASTER_CS_POL_V  0x3F
-#define SPI_MASTER_CS_POL_S  7
-/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: 1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state..*/
-#define SPI_CK_DIS    (BIT(6))
-#define SPI_CK_DIS_M  (BIT(6))
-#define SPI_CK_DIS_V  0x1
-#define SPI_CK_DIS_S  6
-/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS5_DIS    (BIT(5))
-#define SPI_CS5_DIS_M  (BIT(5))
-#define SPI_CS5_DIS_V  0x1
-#define SPI_CS5_DIS_S  5
-/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS4_DIS    (BIT(4))
-#define SPI_CS4_DIS_M  (BIT(4))
-#define SPI_CS4_DIS_V  0x1
-#define SPI_CS4_DIS_S  4
-/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS3_DIS    (BIT(3))
-#define SPI_CS3_DIS_M  (BIT(3))
-#define SPI_CS3_DIS_V  0x1
-#define SPI_CS3_DIS_S  3
-/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS2_DIS    (BIT(2))
-#define SPI_CS2_DIS_M  (BIT(2))
-#define SPI_CS2_DIS_V  0x1
-#define SPI_CS2_DIS_S  2
-/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS1_DIS    (BIT(1))
-#define SPI_CS1_DIS_M  (BIT(1))
-#define SPI_CS1_DIS_V  0x1
-#define SPI_CS1_DIS_S  1
-/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS0_DIS    (BIT(0))
-#define SPI_CS0_DIS_M  (BIT(0))
-#define SPI_CS0_DIS_V  0x1
-#define SPI_CS0_DIS_S  0
-
-#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x24)
-/* SPI_TIMING_HCLK_ACTIVE : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: 1:enable hclk in SPI input timing module.  0: disable it. Can be configured in C
-ONF state..*/
-#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_M  (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_V  0x1
-#define SPI_TIMING_HCLK_ACTIVE_S  16
-/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN3_MODE    0x00000003
-#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
-#define SPI_DIN3_MODE_V  0x3
-#define SPI_DIN3_MODE_S  6
-/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN2_MODE    0x00000003
-#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
-#define SPI_DIN2_MODE_V  0x3
-#define SPI_DIN2_MODE_S  4
-/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN1_MODE    0x00000003
-#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
-#define SPI_DIN1_MODE_V  0x3
-#define SPI_DIN1_MODE_S  2
-/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN0_MODE    0x00000003
-#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
-#define SPI_DIN0_MODE_V  0x3
-#define SPI_DIN0_MODE_S  0
-
-#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x28)
-/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN3_NUM    0x00000003
-#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
-#define SPI_DIN3_NUM_V  0x3
-#define SPI_DIN3_NUM_S  6
-/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN2_NUM    0x00000003
-#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
-#define SPI_DIN2_NUM_V  0x3
-#define SPI_DIN2_NUM_S  4
-/* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN1_NUM    0x00000003
-#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
-#define SPI_DIN1_NUM_V  0x3
-#define SPI_DIN1_NUM_S  2
-/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN0_NUM    0x00000003
-#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
-#define SPI_DIN0_NUM_V  0x3
-#define SPI_DIN0_NUM_S  0
-
-#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x2C)
-/* SPI_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT3_MODE    (BIT(3))
-#define SPI_DOUT3_MODE_M  (BIT(3))
-#define SPI_DOUT3_MODE_V  0x1
-#define SPI_DOUT3_MODE_S  3
-/* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT2_MODE    (BIT(2))
-#define SPI_DOUT2_MODE_M  (BIT(2))
-#define SPI_DOUT2_MODE_V  0x1
-#define SPI_DOUT2_MODE_S  2
-/* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT1_MODE    (BIT(1))
-#define SPI_DOUT1_MODE_M  (BIT(1))
-#define SPI_DOUT1_MODE_V  0x1
-#define SPI_DOUT1_MODE_S  1
-/* SPI_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT0_MODE    (BIT(0))
-#define SPI_DOUT0_MODE_M  (BIT(0))
-#define SPI_DOUT0_MODE_V  0x1
-#define SPI_DOUT0_MODE_S  0
-
-#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x30)
-/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
-DMA controlled mode transfer..*/
-#define SPI_DMA_AFIFO_RST    (BIT(31))
-#define SPI_DMA_AFIFO_RST_M  (BIT(31))
-#define SPI_DMA_AFIFO_RST_V  0x1
-#define SPI_DMA_AFIFO_RST_S  31
-/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
- controlled mode transfer and master mode transfer..*/
-#define SPI_BUF_AFIFO_RST    (BIT(30))
-#define SPI_BUF_AFIFO_RST_M  (BIT(30))
-#define SPI_BUF_AFIFO_RST_V  0x1
-#define SPI_BUF_AFIFO_RST_S  30
-/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-slave mode transfer..*/
-#define SPI_RX_AFIFO_RST    (BIT(29))
-#define SPI_RX_AFIFO_RST_M  (BIT(29))
-#define SPI_RX_AFIFO_RST_V  0x1
-#define SPI_RX_AFIFO_RST_S  29
-/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI DMA controlled send data mode..*/
-#define SPI_DMA_TX_ENA    (BIT(28))
-#define SPI_DMA_TX_ENA_M  (BIT(28))
-#define SPI_DMA_TX_ENA_V  0x1
-#define SPI_DMA_TX_ENA_S  28
-/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: Set this bit to enable SPI DMA controlled receive data mode..*/
-#define SPI_DMA_RX_ENA    (BIT(27))
-#define SPI_DMA_RX_ENA_M  (BIT(27))
-#define SPI_DMA_RX_ENA_V  0x1
-#define SPI_DMA_RX_ENA_S  27
-/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
-o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_d
-ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don
-e in seg-trans..*/
-#define SPI_RX_EOF_EN    (BIT(21))
-#define SPI_RX_EOF_EN_M  (BIT(21))
-#define SPI_RX_EOF_EN_V  0x1
-#define SPI_RX_EOF_EN_S  21
-/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
-mpty_vld is cleared by spi_trans_done..*/
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x1
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
-/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full
-_vld is cleared by spi_trans_done..*/
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x1
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
-/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/
-#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
-#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
-
-#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
-/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_ENA    (BIT(20))
-#define SPI_APP1_INT_ENA_M  (BIT(20))
-#define SPI_APP1_INT_ENA_V  0x1
-#define SPI_APP1_INT_ENA_S  20
-/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_ENA    (BIT(19))
-#define SPI_APP2_INT_ENA_M  (BIT(19))
-#define SPI_APP2_INT_ENA_V  0x1
-#define SPI_APP2_INT_ENA_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
-/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_V  0x1
-#define SPI_SLV_CMD_ERR_INT_ENA_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
-/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
-/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_V  0x1
-#define SPI_TRANS_DONE_INT_ENA_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
-/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_V  0x1
-#define SPI_SLV_CMDA_INT_ENA_S  7
-/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_V  0x1
-#define SPI_SLV_CMD9_INT_ENA_S  6
-/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_V  0x1
-#define SPI_SLV_CMD8_INT_ENA_S  5
-/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_V  0x1
-#define SPI_SLV_CMD7_INT_ENA_S  4
-/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_V  0x1
-#define SPI_SLV_EN_QPI_INT_ENA_S  3
-/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_V  0x1
-#define SPI_SLV_EX_QPI_INT_ENA_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
-
-#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x38)
-/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_CLR    (BIT(20))
-#define SPI_APP1_INT_CLR_M  (BIT(20))
-#define SPI_APP1_INT_CLR_V  0x1
-#define SPI_APP1_INT_CLR_S  20
-/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_CLR    (BIT(19))
-#define SPI_APP2_INT_CLR_M  (BIT(19))
-#define SPI_APP2_INT_CLR_V  0x1
-#define SPI_APP2_INT_CLR_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
-/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_V  0x1
-#define SPI_SLV_CMD_ERR_INT_CLR_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
-/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
-/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_V  0x1
-#define SPI_TRANS_DONE_INT_CLR_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
-/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_V  0x1
-#define SPI_SLV_CMDA_INT_CLR_S  7
-/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_V  0x1
-#define SPI_SLV_CMD9_INT_CLR_S  6
-/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_V  0x1
-#define SPI_SLV_CMD8_INT_CLR_S  5
-/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_V  0x1
-#define SPI_SLV_CMD7_INT_CLR_S  4
-/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_V  0x1
-#define SPI_SLV_EN_QPI_INT_CLR_S  3
-/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_V  0x1
-#define SPI_SLV_EX_QPI_INT_CLR_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
-
-#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x3C)
-/* SPI_APP1_INT_RAW : R/W/WTC ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by applicat
-ion..*/
-#define SPI_APP1_INT_RAW    (BIT(20))
-#define SPI_APP1_INT_RAW_M  (BIT(20))
-#define SPI_APP1_INT_RAW_V  0x1
-#define SPI_APP1_INT_RAW_S  20
-/* SPI_APP2_INT_RAW : R/W/WTC ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by applicat
-ion..*/
-#define SPI_APP2_INT_RAW    (BIT(19))
-#define SPI_APP2_INT_RAW_M  (BIT(19))
-#define SPI_APP2_INT_RAW_V  0x1
-#define SPI_APP2_INT_RAW_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
- write-full error when SPI inputs data in master mode. 0: Others..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
-/* SPI_SLV_CMD_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
- current SPI slave HD mode transmission is not supported. 0: Others..*/
-#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_V  0x1
-#define SPI_SLV_CMD_ERR_INT_RAW_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres
-s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
- is bigger than 63. 0: Others..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
-/* SPI_SEG_MAGIC_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff
-er is error in the DMA seg-conf-trans. 0: others..*/
-#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-du
-plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
-ta has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is
-not ended or not occurred. .*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
-/* SPI_TRANS_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
- ended. 0: others..*/
-#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_V  0x1
-#define SPI_TRANS_DONE_INT_RAW_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
-/* SPI_SLV_CMDA_INT_RAW : R/W/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_V  0x1
-#define SPI_SLV_CMDA_INT_RAW_S  7
-/* SPI_SLV_CMD9_INT_RAW : R/W/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_V  0x1
-#define SPI_SLV_CMD9_INT_RAW_S  6
-/* SPI_SLV_CMD8_INT_RAW : R/W/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_V  0x1
-#define SPI_SLV_CMD8_INT_RAW_S  5
-/* SPI_SLV_CMD7_INT_RAW : R/W/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_V  0x1
-#define SPI_SLV_CMD7_INT_RAW_S  4
-/* SPI_SLV_EN_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio
-n is ended. 0: Others..*/
-#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_V  0x1
-#define SPI_SLV_EN_QPI_INT_RAW_S  3
-/* SPI_SLV_EX_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio
-n is ended. 0: Others..*/
-#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_V  0x1
-#define SPI_SLV_EX_QPI_INT_RAW_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
- master mode and send out all 0 in slave mode.  0: Others.  .*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
-the receive data.  0: Others.  .*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
-
-#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x40)
-/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The status bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_ST    (BIT(20))
-#define SPI_APP1_INT_ST_M  (BIT(20))
-#define SPI_APP1_INT_ST_V  0x1
-#define SPI_APP1_INT_ST_S  20
-/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The status bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_ST    (BIT(19))
-#define SPI_APP2_INT_ST_M  (BIT(19))
-#define SPI_APP2_INT_ST_V  0x1
-#define SPI_APP2_INT_ST_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
-/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_V  0x1
-#define SPI_SLV_CMD_ERR_INT_ST_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
-/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
-/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_ST    (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_V  0x1
-#define SPI_TRANS_DONE_INT_ST_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
-/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_ST    (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_V  0x1
-#define SPI_SLV_CMDA_INT_ST_S  7
-/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_ST    (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_V  0x1
-#define SPI_SLV_CMD9_INT_ST_S  6
-/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_ST    (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_V  0x1
-#define SPI_SLV_CMD8_INT_ST_S  5
-/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_ST    (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_V  0x1
-#define SPI_SLV_CMD7_INT_ST_S  4
-/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_V  0x1
-#define SPI_SLV_EN_QPI_INT_ST_S  3
-/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_V  0x1
-#define SPI_SLV_EX_QPI_INT_ST_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
-
-#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x98)
-/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF0    0xFFFFFFFF
-#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
-#define SPI_BUF0_V  0xFFFFFFFF
-#define SPI_BUF0_S  0
-
-#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x9C)
-/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF1    0xFFFFFFFF
-#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
-#define SPI_BUF1_V  0xFFFFFFFF
-#define SPI_BUF1_S  0
-
-#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0xA0)
-/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF2    0xFFFFFFFF
-#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
-#define SPI_BUF2_V  0xFFFFFFFF
-#define SPI_BUF2_S  0
-
-#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0xA4)
-/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF3    0xFFFFFFFF
-#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
-#define SPI_BUF3_V  0xFFFFFFFF
-#define SPI_BUF3_S  0
-
-#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0xA8)
-/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF4    0xFFFFFFFF
-#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
-#define SPI_BUF4_V  0xFFFFFFFF
-#define SPI_BUF4_S  0
-
-#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0xAC)
-/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF5    0xFFFFFFFF
-#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
-#define SPI_BUF5_V  0xFFFFFFFF
-#define SPI_BUF5_S  0
-
-#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0xB0)
-/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF6    0xFFFFFFFF
-#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
-#define SPI_BUF6_V  0xFFFFFFFF
-#define SPI_BUF6_S  0
-
-#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0xB4)
-/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF7    0xFFFFFFFF
-#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
-#define SPI_BUF7_V  0xFFFFFFFF
-#define SPI_BUF7_S  0
-
-#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xB8)
-/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF8    0xFFFFFFFF
-#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
-#define SPI_BUF8_V  0xFFFFFFFF
-#define SPI_BUF8_S  0
-
-#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xBC)
-/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF9    0xFFFFFFFF
-#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
-#define SPI_BUF9_V  0xFFFFFFFF
-#define SPI_BUF9_S  0
-
-#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xC0)
-/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF10    0xFFFFFFFF
-#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
-#define SPI_BUF10_V  0xFFFFFFFF
-#define SPI_BUF10_S  0
-
-#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xC4)
-/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF11    0xFFFFFFFF
-#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
-#define SPI_BUF11_V  0xFFFFFFFF
-#define SPI_BUF11_S  0
-
-#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xC8)
-/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF12    0xFFFFFFFF
-#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
-#define SPI_BUF12_V  0xFFFFFFFF
-#define SPI_BUF12_S  0
-
-#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xCC)
-/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF13    0xFFFFFFFF
-#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
-#define SPI_BUF13_V  0xFFFFFFFF
-#define SPI_BUF13_S  0
-
-#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xD0)
-/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF14    0xFFFFFFFF
-#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
-#define SPI_BUF14_V  0xFFFFFFFF
-#define SPI_BUF14_S  0
-
-#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xD4)
-/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF15    0xFFFFFFFF
-#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
-#define SPI_BUF15_V  0xFFFFFFFF
-#define SPI_BUF15_S  0
-
-#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0xE0)
-/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
-ns will start. 0: This is not seg-trans mode..*/
-#define SPI_USR_CONF    (BIT(28))
-#define SPI_USR_CONF_M  (BIT(28))
-#define SPI_USR_CONF_V  0x1
-#define SPI_USR_CONF_S  28
-/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
-onfigured in CONF state..*/
-#define SPI_SOFT_RESET    (BIT(27))
-#define SPI_SOFT_RESET_M  (BIT(27))
-#define SPI_SOFT_RESET_V  0x1
-#define SPI_SOFT_RESET_S  27
-/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
-#define SPI_SLAVE_MODE    (BIT(26))
-#define SPI_SLAVE_MODE_M  (BIT(26))
-#define SPI_SLAVE_MODE_V  0x1
-#define SPI_SLAVE_MODE_S  26
-/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
-/*description: The magic value of BM table in master DMA seg-trans..*/
-#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000F
-#define SPI_DMA_SEG_MAGIC_VALUE_M  ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
-#define SPI_DMA_SEG_MAGIC_VALUE_V  0xF
-#define SPI_DMA_SEG_MAGIC_VALUE_S  22
-/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
-th in CPU controlled mode(Wr_BUF). 0: others.*/
-#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_M  (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_V  0x1
-#define SPI_SLV_WRBUF_BITLEN_EN_S  11
-/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
-n CPU controlled mode(Rd_BUF). 0: others.*/
-#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_M  (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_V  0x1
-#define SPI_SLV_RDBUF_BITLEN_EN_S  10
-/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
-th in DMA controlled mode(Wr_DMA). 0: others.*/
-#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_M  (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_V  0x1
-#define SPI_SLV_WRDMA_BITLEN_EN_S  9
-/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
-n DMA controlled mode(Rd_DMA). 0: others.*/
-#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_M  (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_V  0x1
-#define SPI_SLV_RDDMA_BITLEN_EN_S  8
-/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
-dge   0: output data at tsck posedge .*/
-#define SPI_RSCK_DATA_OUT    (BIT(3))
-#define SPI_RSCK_DATA_OUT_M  (BIT(3))
-#define SPI_RSCK_DATA_OUT_V  0x1
-#define SPI_RSCK_DATA_OUT_S  3
-/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
- 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
-#define SPI_CLK_MODE_13    (BIT(2))
-#define SPI_CLK_MODE_13_M  (BIT(2))
-#define SPI_CLK_MODE_13_V  0x1
-#define SPI_CLK_MODE_13_S  2
-/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/
-#define SPI_CLK_MODE    0x00000003
-#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
-#define SPI_CLK_MODE_V  0x3
-#define SPI_CLK_MODE_S  0
-
-#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0xE4)
-/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
-/*description: In the slave mode it is the value of address..*/
-#define SPI_SLV_LAST_ADDR    0x0000003F
-#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
-#define SPI_SLV_LAST_ADDR_V  0x3F
-#define SPI_SLV_LAST_ADDR_S  26
-/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
-/*description: In the slave mode it is the value of command..*/
-#define SPI_SLV_LAST_COMMAND    0x000000FF
-#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
-#define SPI_SLV_LAST_COMMAND_V  0xFF
-#define SPI_SLV_LAST_COMMAND_S  18
-/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: The transferred data bit length in SPI slave FD and HD mode. .*/
-#define SPI_SLV_DATA_BITLEN    0x0003FFFF
-#define SPI_SLV_DATA_BITLEN_M  ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
-#define SPI_SLV_DATA_BITLEN_V  0x3FFFF
-#define SPI_SLV_DATA_BITLEN_S  0
-
-#define SPI_CLK_GATE_REG(i)          (REG_SPI_BASE(i) + 0xE8)
-/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
-M. 0: XTAL CLK..*/
-#define SPI_MST_CLK_SEL    (BIT(2))
-#define SPI_MST_CLK_SEL_M  (BIT(2))
-#define SPI_MST_CLK_SEL_V  0x1
-#define SPI_MST_CLK_SEL_S  2
-/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to power on the SPI module clock..*/
-#define SPI_MST_CLK_ACTIVE    (BIT(1))
-#define SPI_MST_CLK_ACTIVE_M  (BIT(1))
-#define SPI_MST_CLK_ACTIVE_V  0x1
-#define SPI_MST_CLK_ACTIVE_S  1
-/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable clk gate.*/
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (BIT(0))
-#define SPI_CLK_EN_V  0x1
-#define SPI_CLK_EN_S  0
-
-#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
-/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007220 ; */
-/*description: SPI register version..*/
-#define SPI_DATE    0x0FFFFFFF
-#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
-#define SPI_DATE_V  0xFFFFFFF
-#define SPI_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/spi_struct.h b/components/soc/esp32c3/include/soc/spi_struct.h
deleted file mode 100644
index 8cb6a7ee97a..00000000000
--- a/components/soc/esp32c3/include/soc/spi_struct.h
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct spi_dev_s {
-    union {
-        struct {
-            uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
-            uint32_t reserved18                    :    5;  /*reserved*/
-            uint32_t update                        :    1;  /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
-            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    3;  /*reserved*/
-            uint32_t dummy_out                     :    1;  /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/
-            uint32_t reserved4                     :    1;  /*reserved*/
-            uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved7                     :    1;  /*reserved*/
-            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved10                    :    4;  /*reserved*/
-            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
-            uint32_t reserved16                    :    1;  /*reserved*/
-            uint32_t reserved17                    :    1;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
-            uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
-            uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
-            uint32_t reserved22                    :    3;  /*reserved*/
-            uint32_t rd_bit_order                  :    1;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
-            uint32_t wr_bit_order                  :    1;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    6;  /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
-            uint32_t clkcnt_h                      :    6;  /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
-            uint32_t clkcnt_n                      :    6;  /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
-            uint32_t clkdiv_pre                    :    4;  /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
-            uint32_t reserved22                    :    9;  /*reserved*/
-            uint32_t clk_equ_sysclk                :    1;  /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t doutdin                       :    1;  /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved1                     :    2;  /*reserved*/
-            uint32_t qpi_mode                      :    1;  /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
-            uint32_t reserved4                     :    1;  /*reserved*/
-            uint32_t tsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
-            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t rsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
-            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
-            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
-            uint32_t reserved14                    :    1;  /*reserved*/
-            uint32_t usr_conf_nxt                  :    1;  /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
-            uint32_t reserved16                    :    1;  /*reserved*/
-            uint32_t sio                           :    1;  /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved18                    :    6;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.*/
-            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    8;  /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
-            uint32_t reserved8                     :    8;  /*reserved*/
-            uint32_t mst_wfull_err_end_en          :    1;  /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
-            uint32_t cs_setup_time                 :    5;  /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
-            uint32_t cs_hold_time                  :    5;  /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
-            uint32_t usr_addr_bitlen               :    5;  /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of  command. Can be configured in CONF state.*/
-            uint32_t reserved16                    :    11;  /*reserved*/
-            uint32_t mst_rempty_err_end_en         :    1;  /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t ms_data_bitlen                :    18;  /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } ms_dlen;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs1_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs2_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs3_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs4_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs5_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t ck_dis                        :    1;  /*1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.*/
-            uint32_t master_cs_pol                 :    6;  /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
-            uint32_t reserved13                    :    10;  /*reserved*/
-            uint32_t slave_cs_pol                  :    1;  /*spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.*/
-            uint32_t reserved24                    :    5;  /*reserved*/
-            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
-            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
-            uint32_t quad_din_pin_swap             :    1;  /*1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } misc;
-    union {
-        struct {
-            uint32_t din0_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din1_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din2_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din3_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t reserved8                     :    8;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t timing_hclk_active            :    1;  /*1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.*/
-            uint32_t reserved17                    :    15;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din1_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din2_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din3_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t reserved8                     :    24;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout1_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout2_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout3_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    union {
-        struct {
-            uint32_t reserved0                     :    18;  /*reserved*/
-            uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
-            uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
-            uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
-            uint32_t rx_eof_en                     :    1;  /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
-            uint32_t reserved22                    :    5;  /*reserved*/
-            uint32_t dma_rx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled receive data mode.*/
-            uint32_t dma_tx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled send data mode.*/
-            uint32_t rx_afifo_rst                  :    1;  /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
-            uint32_t buf_afifo_rst                 :    1;  /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
-            uint32_t dma_afifo_rst                 :    1;  /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
-        };
-        uint32_t val;
-    } dma_conf;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The enable bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The enable bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The enable bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The enable bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The enable bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The enable bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The enable bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The enable bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_ena;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The clear bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The clear bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The clear bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The clear bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The clear bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The clear bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The clear bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The clear bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_clr;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.  */
-            uint32_t outfifo_empty_err             :    1;  /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.  */
-            uint32_t ex_qpi                        :    1;  /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
-            uint32_t en_qpi                        :    1;  /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
-            uint32_t cmd7                          :    1;  /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
-            uint32_t cmd8                          :    1;  /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
-            uint32_t cmd9                          :    1;  /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
-            uint32_t cmda                          :    1;  /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
-            uint32_t rd_dma_done                   :    1;  /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
-            uint32_t wr_dma_done                   :    1;  /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
-            uint32_t rd_buf_done                   :    1;  /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
-            uint32_t wr_buf_done                   :    1;  /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
-            uint32_t trans_done                    :    1;  /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred. */
-            uint32_t seg_magic_err                 :    1;  /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
-            uint32_t buf_addr_err                  :    1;  /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
-            uint32_t cmd_err                       :    1;  /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
-            uint32_t app2                          :    1;  /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.*/
-            uint32_t app1                          :    1;  /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_raw;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The status bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The status bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The status bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The status bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The status bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The status bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The status bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The status bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_st;
-    uint32_t reserved_44;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t data_buf[16];
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
-            uint32_t clk_mode_13                   :    1;  /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
-            uint32_t rsck_data_out                 :    1;  /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge */
-            uint32_t reserved4                     :    4;  /*reserved*/
-            uint32_t rddma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
-            uint32_t wrdma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
-            uint32_t rdbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
-            uint32_t wrbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
-            uint32_t reserved12                    :    10;  /*reserved*/
-            uint32_t dma_seg_magic_value           :    4;  /*The magic value of BM table in master DMA seg-trans.*/
-            uint32_t slave_mode                    :    1;  /*Set SPI work mode. 1: slave mode 0: master mode.*/
-            uint32_t soft_reset                    :    1;  /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
-            uint32_t usr_conf                      :    1;  /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
-            uint32_t reserved29                    :    3;  /*reserved*/
-        };
-        uint32_t val;
-    } slave;
-    union {
-        struct {
-            uint32_t data_bitlen                   :    18;  /*The transferred data bit length in SPI slave FD and HD mode. */
-            uint32_t last_command                  :    8;  /*In the slave mode it is the value of command.*/
-            uint32_t last_addr                     :    6;  /*In the slave mode it is the value of address.*/
-        };
-        uint32_t val;
-    } slave1;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
-            uint32_t mst_clk_active                :    1;  /*Set this bit to power on the SPI module clock.*/
-            uint32_t mst_clk_sel                   :    1;  /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } clk_gate;
-    uint32_t reserved_ec;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*SPI register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_dev_t;
-
-extern spi_dev_t GPSPI2;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/syscon_reg.h b/components/soc/esp32c3/include/soc/syscon_reg.h
deleted file mode 100644
index e61f84eda35..00000000000
--- a/components/soc/esp32c3/include/soc/syscon_reg.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SYSCON_REG_H_
-#define _SOC_SYSCON_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x000)
-/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_RST_TICK_CNT  (BIT(12))
-#define SYSCON_RST_TICK_CNT_M  (BIT(12))
-#define SYSCON_RST_TICK_CNT_V  0x1
-#define SYSCON_RST_TICK_CNT_S  12
-/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_CLK_EN  (BIT(11))
-#define SYSCON_CLK_EN_M  (BIT(11))
-#define SYSCON_CLK_EN_V  0x1
-#define SYSCON_CLK_EN_S  11
-/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_CLK_320M_EN  (BIT(10))
-#define SYSCON_CLK_320M_EN_M  (BIT(10))
-#define SYSCON_CLK_320M_EN_V  0x1
-#define SYSCON_CLK_320M_EN_S  10
-/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
-/*description: */
-#define SYSCON_PRE_DIV_CNT  0x000003FF
-#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
-#define SYSCON_PRE_DIV_CNT_V  0x3FF
-#define SYSCON_PRE_DIV_CNT_S  0
-
-#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x004)
-/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: */
-#define SYSCON_TICK_ENABLE  (BIT(16))
-#define SYSCON_TICK_ENABLE_M  (BIT(16))
-#define SYSCON_TICK_ENABLE_V  0x1
-#define SYSCON_TICK_ENABLE_S  16
-/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
-/*description: */
-#define SYSCON_CK8M_TICK_NUM  0x000000FF
-#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
-#define SYSCON_CK8M_TICK_NUM_V  0xFF
-#define SYSCON_CK8M_TICK_NUM_S  8
-/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
-/*description: */
-#define SYSCON_XTAL_TICK_NUM  0x000000FF
-#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
-#define SYSCON_XTAL_TICK_NUM_V  0xFF
-#define SYSCON_XTAL_TICK_NUM_S  0
-
-#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x008)
-/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK_XTAL_OEN  (BIT(10))
-#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
-#define SYSCON_CLK_XTAL_OEN_V  0x1
-#define SYSCON_CLK_XTAL_OEN_S  10
-/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK40X_BB_OEN  (BIT(9))
-#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
-#define SYSCON_CLK40X_BB_OEN_V  0x1
-#define SYSCON_CLK40X_BB_OEN_S  9
-/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK_DAC_CPU_OEN  (BIT(8))
-#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
-#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
-#define SYSCON_CLK_DAC_CPU_OEN_S  8
-/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK_ADC_INF_OEN  (BIT(7))
-#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
-#define SYSCON_CLK_ADC_INF_OEN_V  0x1
-#define SYSCON_CLK_ADC_INF_OEN_S  7
-/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK_320M_OEN  (BIT(6))
-#define SYSCON_CLK_320M_OEN_M  (BIT(6))
-#define SYSCON_CLK_320M_OEN_V  0x1
-#define SYSCON_CLK_320M_OEN_S  6
-/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK160_OEN  (BIT(5))
-#define SYSCON_CLK160_OEN_M  (BIT(5))
-#define SYSCON_CLK160_OEN_V  0x1
-#define SYSCON_CLK160_OEN_S  5
-/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK80_OEN  (BIT(4))
-#define SYSCON_CLK80_OEN_M  (BIT(4))
-#define SYSCON_CLK80_OEN_V  0x1
-#define SYSCON_CLK80_OEN_S  4
-/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK_BB_OEN  (BIT(3))
-#define SYSCON_CLK_BB_OEN_M  (BIT(3))
-#define SYSCON_CLK_BB_OEN_V  0x1
-#define SYSCON_CLK_BB_OEN_S  3
-/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK44_OEN  (BIT(2))
-#define SYSCON_CLK44_OEN_M  (BIT(2))
-#define SYSCON_CLK44_OEN_V  0x1
-#define SYSCON_CLK44_OEN_S  2
-/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK22_OEN  (BIT(1))
-#define SYSCON_CLK22_OEN_M  (BIT(1))
-#define SYSCON_CLK22_OEN_V  0x1
-#define SYSCON_CLK22_OEN_S  1
-/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_CLK20_OEN  (BIT(0))
-#define SYSCON_CLK20_OEN_M  (BIT(0))
-#define SYSCON_CLK20_OEN_V  0x1
-#define SYSCON_CLK20_OEN_S  0
-
-#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0x00C)
-/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SYSCON_WIFI_BB_CFG  0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
-#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_S  0
-
-#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x010)
-/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SYSCON_WIFI_BB_CFG_2  0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
-#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_2_S  0
-
-#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x014)
-/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: */
-#define SYSCON_WIFI_CLK_EN  0xFFFFFFFF
-#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
-#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
-#define SYSCON_WIFI_CLK_EN_S  0
-
-#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x018)
-/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SYSCON_WIFI_RST  0xFFFFFFFF
-#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
-#define SYSCON_WIFI_RST_V  0xFFFFFFFF
-#define SYSCON_WIFI_RST_S  0
-
-#define SYSTEM_WIFI_CLK_EN_REG          SYSCON_WIFI_CLK_EN_REG
-/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: */
-#define SYSTEM_WIFI_CLK_EN  0x00FB9FCF
-#define SYSTEM_WIFI_CLK_EN_M  ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
-#define SYSTEM_WIFI_CLK_EN_V  0x00FB9FCF
-#define SYSTEM_WIFI_CLK_EN_S  0
-
-/* Mask for all Wifi clock bits, 6 */
-#define SYSTEM_WIFI_CLK_WIFI_EN  0x0
-#define SYSTEM_WIFI_CLK_WIFI_EN_M  ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
-#define SYSTEM_WIFI_CLK_WIFI_EN_V  0x0
-#define SYSTEM_WIFI_CLK_WIFI_EN_S  0
-/* Mask for all Bluetooth clock bits, 11, 16, 17 */
-#define SYSTEM_WIFI_CLK_BT_EN  0x0
-#define SYSTEM_WIFI_CLK_BT_EN_M  ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
-#define SYSTEM_WIFI_CLK_BT_EN_V  0x0
-#define SYSTEM_WIFI_CLK_BT_EN_S  0
-/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
-#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
-
-/* Digital team to check */
-//bluetooth baseband bit11
-#define SYSTEM_BT_BASEBAND_EN  BIT(11)
-//bluetooth LC bit16 and bit17
-#define SYSTEM_BT_LC_EN  (BIT(16)|BIT(17))
-
-/* Remaining single bit clock masks */
-#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
-#define SYSTEM_WIFI_CLK_I2C_CLK_EN  BIT(5)
-#define SYSTEM_WIFI_CLK_UNUSED_BIT12  BIT(12)
-#define SYSTEM_WIFI_CLK_EMAC_EN  BIT(14)
-#define SYSTEM_WIFI_CLK_RNG_EN  BIT(15)
-
-#define SYSTEM_CORE_RST_EN_REG        SYSTEM_WIFI_RST_EN_REG
-#define SYSTEM_WIFI_RST_EN_REG        SYSCON_WIFI_RST_EN_REG
-
-/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SYSTEM_WIFIBB_RST           BIT(0)
-#define SYSTEM_FE_RST               BIT(1)
-#define SYSTEM_WIFIMAC_RST          BIT(2)
-#define SYSTEM_BTBB_RST             BIT(3)    /* Bluetooth Baseband */
-#define SYSTEM_BTMAC_RST            BIT(4)    /* deprecated */
-#define SYSTEM_SDIO_RST             BIT(5)
-#define SYSTEM_EMAC_RST             BIT(7)
-#define SYSTEM_MACPWR_RST           BIT(8)
-#define SYSTEM_RW_BTMAC_RST         BIT(9)    /* Bluetooth MAC */
-#define SYSTEM_RW_BTLP_RST          BIT(10)   /* Bluetooth Low Power Module */
-#define SYSTEM_RW_BTMAC_REG_RST     BIT(11)   /* Bluetooth MAC Regsiters */
-#define SYSTEM_RW_BTLP_REG_RST      BIT(12)   /* Bluetooth Low Power Registers */
-#define SYSTEM_BTBB_REG_RST         BIT(13)   /* Bluetooth Baseband Registers */
-
-#define MODEM_RESET_FIELD_WHEN_PU   (SYSTEM_WIFIBB_RST       | \
-                                     SYSTEM_FE_RST           | \
-                                     SYSTEM_WIFIMAC_RST      | \
-                                     SYSTEM_BTBB_RST         | \
-                                     SYSTEM_BTMAC_RST        | \
-                                     SYSTEM_RW_BTMAC_RST     | \
-                                     SYSTEM_RW_BTMAC_REG_RST | \
-                                     SYSTEM_BTBB_REG_RST)
-
-#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x01C)
-/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: */
-#define SYSCON_PERI_IO_SWAP  0x000000FF
-#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
-#define SYSCON_PERI_IO_SWAP_V  0xFF
-#define SYSCON_PERI_IO_SWAP_S  0
-
-#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x020)
-/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_EXT_MEM_PMS_LOCK  (BIT(0))
-#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
-#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
-#define SYSCON_EXT_MEM_PMS_LOCK_S  0
-
-#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x028)
-/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: */
-#define SYSCON_FLASH_ACE0_ATTR  0x00000003
-#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
-#define SYSCON_FLASH_ACE0_ATTR_V  0x3
-#define SYSCON_FLASH_ACE0_ATTR_S  0
-
-#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x02C)
-/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: */
-#define SYSCON_FLASH_ACE1_ATTR  0x00000003
-#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
-#define SYSCON_FLASH_ACE1_ATTR_V  0x3
-#define SYSCON_FLASH_ACE1_ATTR_S  0
-
-#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x030)
-/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: */
-#define SYSCON_FLASH_ACE2_ATTR  0x00000003
-#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
-#define SYSCON_FLASH_ACE2_ATTR_V  0x3
-#define SYSCON_FLASH_ACE2_ATTR_S  0
-
-#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x034)
-/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
-/*description: */
-#define SYSCON_FLASH_ACE3_ATTR  0x00000003
-#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
-#define SYSCON_FLASH_ACE3_ATTR_V  0x3
-#define SYSCON_FLASH_ACE3_ATTR_S  0
-
-#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x038)
-/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SYSCON_FLASH_ACE0_ADDR_S  0xFFFFFFFF
-#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
-#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE0_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x03C)
-/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
-/*description: */
-#define SYSCON_FLASH_ACE1_ADDR_S  0xFFFFFFFF
-#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
-#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE1_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x040)
-/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
-/*description: */
-#define SYSCON_FLASH_ACE2_ADDR_S  0xFFFFFFFF
-#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
-#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE2_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x044)
-/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
-/*description: */
-#define SYSCON_FLASH_ACE3_ADDR_S  0xFFFFFFFF
-#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
-#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE3_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x048)
-/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: */
-#define SYSCON_FLASH_ACE0_SIZE  0x00001FFF
-#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
-#define SYSCON_FLASH_ACE0_SIZE_V  0x1FFF
-#define SYSCON_FLASH_ACE0_SIZE_S  0
-
-#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x04C)
-/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: */
-#define SYSCON_FLASH_ACE1_SIZE  0x00001FFF
-#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
-#define SYSCON_FLASH_ACE1_SIZE_V  0x1FFF
-#define SYSCON_FLASH_ACE1_SIZE_S  0
-
-#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x050)
-/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: */
-#define SYSCON_FLASH_ACE2_SIZE  0x00001FFF
-#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
-#define SYSCON_FLASH_ACE2_SIZE_V  0x1FFF
-#define SYSCON_FLASH_ACE2_SIZE_S  0
-
-#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x054)
-/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
-/*description: */
-#define SYSCON_FLASH_ACE3_SIZE  0x00001FFF
-#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
-#define SYSCON_FLASH_ACE3_SIZE_V  0x1FFF
-#define SYSCON_FLASH_ACE3_SIZE_S  0
-
-#define SYSCON_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x088)
-/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
-/*description: */
-#define SYSCON_SPI_MEM_REJECT_CDE  0x0000001F
-#define SYSCON_SPI_MEM_REJECT_CDE_M  ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
-#define SYSCON_SPI_MEM_REJECT_CDE_V  0x1F
-#define SYSCON_SPI_MEM_REJECT_CDE_S  2
-/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_SPI_MEM_REJECT_CLR  (BIT(1))
-#define SYSCON_SPI_MEM_REJECT_CLR_M  (BIT(1))
-#define SYSCON_SPI_MEM_REJECT_CLR_V  0x1
-#define SYSCON_SPI_MEM_REJECT_CLR_S  1
-/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_SPI_MEM_REJECT_INT  (BIT(0))
-#define SYSCON_SPI_MEM_REJECT_INT_M  (BIT(0))
-#define SYSCON_SPI_MEM_REJECT_INT_V  0x1
-#define SYSCON_SPI_MEM_REJECT_INT_S  0
-
-#define SYSCON_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x08C)
-/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SYSCON_SPI_MEM_REJECT_ADDR  0xFFFFFFFF
-#define SYSCON_SPI_MEM_REJECT_ADDR_M  ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
-#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
-#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
-
-#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x090)
-/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: */
-#define SYSCON_SDIO_WIN_ACCESS_EN  (BIT(0))
-#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
-#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
-#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
-
-#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x094)
-/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SYSCON_REDCY_ANDOR  (BIT(31))
-#define SYSCON_REDCY_ANDOR_M  (BIT(31))
-#define SYSCON_REDCY_ANDOR_V  0x1
-#define SYSCON_REDCY_ANDOR_S  31
-/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: */
-#define SYSCON_REDCY_SIG0  0x7FFFFFFF
-#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
-#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
-#define SYSCON_REDCY_SIG0_S  0
-
-#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x098)
-/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SYSCON_REDCY_NANDOR  (BIT(31))
-#define SYSCON_REDCY_NANDOR_M  (BIT(31))
-#define SYSCON_REDCY_NANDOR_V  0x1
-#define SYSCON_REDCY_NANDOR_S  31
-/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: */
-#define SYSCON_REDCY_SIG1  0x7FFFFFFF
-#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
-#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
-#define SYSCON_REDCY_SIG1_S  0
-
-#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x09C)
-/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_DC_MEM_FORCE_PD  (BIT(5))
-#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
-#define SYSCON_DC_MEM_FORCE_PD_V  0x1
-#define SYSCON_DC_MEM_FORCE_PD_S  5
-/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_DC_MEM_FORCE_PU  (BIT(4))
-#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
-#define SYSCON_DC_MEM_FORCE_PU_V  0x1
-#define SYSCON_DC_MEM_FORCE_PU_S  4
-/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_PBUS_MEM_FORCE_PD  (BIT(3))
-#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
-#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
-#define SYSCON_PBUS_MEM_FORCE_PD_S  3
-/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_PBUS_MEM_FORCE_PU  (BIT(2))
-#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
-#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
-#define SYSCON_PBUS_MEM_FORCE_PU_S  2
-/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_AGC_MEM_FORCE_PD  (BIT(1))
-#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
-#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
-#define SYSCON_AGC_MEM_FORCE_PD_S  1
-/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SYSCON_AGC_MEM_FORCE_PU  (BIT(0))
-#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
-#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
-#define SYSCON_AGC_MEM_FORCE_PU_S  0
-
-#define SYSCON_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0x0A0)
-/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_NOBYPASS_CPU_ISO_RST  (BIT(27))
-#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
-#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x1
-#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
-/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
-/*description: */
-#define SYSCON_RETENTION_LINK_ADDR  0x07FFFFFF
-#define SYSCON_RETENTION_LINK_ADDR_M  ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
-#define SYSCON_RETENTION_LINK_ADDR_V  0x7FFFFFF
-#define SYSCON_RETENTION_LINK_ADDR_S  0
-
-#define SYSCON_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0x0A4)
-/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
-/*description: */
-#define SYSCON_SRAM_CLKGATE_FORCE_ON  0x0000000F
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0xF
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  2
-/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SYSCON_ROM_CLKGATE_FORCE_ON  0x00000003
-#define SYSCON_ROM_CLKGATE_FORCE_ON_M  ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
-#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x3
-#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
-
-#define SYSCON_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0x0A8)
-/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
-/*description: */
-#define SYSCON_SRAM_POWER_DOWN  0x0000000F
-#define SYSCON_SRAM_POWER_DOWN_M  ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
-#define SYSCON_SRAM_POWER_DOWN_V  0xF
-#define SYSCON_SRAM_POWER_DOWN_S  2
-/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define SYSCON_ROM_POWER_DOWN  0x00000003
-#define SYSCON_ROM_POWER_DOWN_M  ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
-#define SYSCON_ROM_POWER_DOWN_V  0x3
-#define SYSCON_ROM_POWER_DOWN_S  0
-
-#define SYSCON_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0x0AC)
-/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
-/*description: */
-#define SYSCON_SRAM_POWER_UP  0x0000000F
-#define SYSCON_SRAM_POWER_UP_M  ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
-#define SYSCON_SRAM_POWER_UP_V  0xF
-#define SYSCON_SRAM_POWER_UP_S  2
-/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: */
-#define SYSCON_ROM_POWER_UP  0x00000003
-#define SYSCON_ROM_POWER_UP_M  ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
-#define SYSCON_ROM_POWER_UP_V  0x3
-#define SYSCON_ROM_POWER_UP_S  0
-
-#define SYSCON_RND_DATA_REG          (DR_REG_SYSCON_BASE + 0x0B0)
-/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SYSCON_RND_DATA  0xFFFFFFFF
-#define SYSCON_RND_DATA_M  ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
-#define SYSCON_RND_DATA_V  0xFFFFFFFF
-#define SYSCON_RND_DATA_S  0
-
-#define SYSCON_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0x0B4)
-/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_ENA  (BIT(31))
-#define SYSCON_PERI_BACKUP_ENA_M  (BIT(31))
-#define SYSCON_PERI_BACKUP_ENA_V  0x1
-#define SYSCON_PERI_BACKUP_ENA_S  31
-/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_TO_MEM  (BIT(30))
-#define SYSCON_PERI_BACKUP_TO_MEM_M  (BIT(30))
-#define SYSCON_PERI_BACKUP_TO_MEM_V  0x1
-#define SYSCON_PERI_BACKUP_TO_MEM_S  30
-/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_START  (BIT(29))
-#define SYSCON_PERI_BACKUP_START_M  (BIT(29))
-#define SYSCON_PERI_BACKUP_START_V  0x1
-#define SYSCON_PERI_BACKUP_START_S  29
-/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_SIZE  0x000003FF
-#define SYSCON_PERI_BACKUP_SIZE_M  ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
-#define SYSCON_PERI_BACKUP_SIZE_V  0x3FF
-#define SYSCON_PERI_BACKUP_SIZE_S  19
-/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_TOUT_THRES  0x000003FF
-#define SYSCON_PERI_BACKUP_TOUT_THRES_M  ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S))
-#define SYSCON_PERI_BACKUP_TOUT_THRES_V  0x3FF
-#define SYSCON_PERI_BACKUP_TOUT_THRES_S  9
-/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_BURST_LIMIT  0x0000001F
-#define SYSCON_PERI_BACKUP_BURST_LIMIT_M  ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
-#define SYSCON_PERI_BACKUP_BURST_LIMIT_V  0x1F
-#define SYSCON_PERI_BACKUP_BURST_LIMIT_S  4
-/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_FLOW_ERR  0x00000003
-#define SYSCON_PERI_BACKUP_FLOW_ERR_M  ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
-#define SYSCON_PERI_BACKUP_FLOW_ERR_V  0x3
-#define SYSCON_PERI_BACKUP_FLOW_ERR_S  1
-
-#define SYSCON_PERI_BACKUP_APB_ADDR_REG          (DR_REG_SYSCON_BASE + 0x0B8)
-/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: */
-#define SYSCON_BACKUP_APB_START_ADDR  0xFFFFFFFF
-#define SYSCON_BACKUP_APB_START_ADDR_M  ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
-#define SYSCON_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
-#define SYSCON_BACKUP_APB_START_ADDR_S  0
-
-#define SYSCON_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_SYSCON_BASE + 0x0BC)
-/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: */
-#define SYSCON_BACKUP_MEM_START_ADDR  0xFFFFFFFF
-#define SYSCON_BACKUP_MEM_START_ADDR_M  ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
-#define SYSCON_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
-#define SYSCON_BACKUP_MEM_START_ADDR_S  0
-
-#define SYSCON_PERI_BACKUP_INT_RAW_REG          (DR_REG_SYSCON_BASE + 0x0C0)
-/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_ERR_INT_RAW  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V  0x1
-#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S  1
-/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_DONE_INT_RAW  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V  0x1
-#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S  0
-
-#define SYSCON_PERI_BACKUP_INT_ST_REG          (DR_REG_SYSCON_BASE + 0x0C4)
-/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_ERR_INT_ST  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_ST_V  0x1
-#define SYSCON_PERI_BACKUP_ERR_INT_ST_S  1
-/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_DONE_INT_ST  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_ST_V  0x1
-#define SYSCON_PERI_BACKUP_DONE_INT_ST_S  0
-
-#define SYSCON_PERI_BACKUP_INT_ENA_REG          (DR_REG_SYSCON_BASE + 0x0C8)
-/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_ERR_INT_ENA  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V  0x1
-#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S  1
-/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_DONE_INT_ENA  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V  0x1
-#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S  0
-
-#define SYSCON_PERI_BACKUP_INT_CLR_REG          (DR_REG_SYSCON_BASE + 0x0D0)
-/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_ERR_INT_CLR  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
-#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V  0x1
-#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S  1
-/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
-/*description: */
-#define SYSCON_PERI_BACKUP_DONE_INT_CLR  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
-#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V  0x1
-#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S  0
-
-#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
-/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
-/*description: Version control*/
-#define SYSCON_DATE  0xFFFFFFFF
-#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
-#define SYSCON_DATE_V  0xFFFFFFFF
-#define SYSCON_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SYSCON_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/system_reg.h b/components/soc/esp32c3/include/soc/system_reg.h
deleted file mode 100644
index 7bcb904214d..00000000000
--- a/components/soc/esp32c3/include/soc/system_reg.h
+++ /dev/null
@@ -1,1030 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SYSTEM_REG_H_
-#define _SOC_SYSTEM_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define SYSTEM_CPU_PERI_CLK_EN_REG          (DR_REG_SYSTEM_BASE + 0x000)
-/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CLK_EN_DEDICATED_GPIO  (BIT(7))
-#define SYSTEM_CLK_EN_DEDICATED_GPIO_M  (BIT(7))
-#define SYSTEM_CLK_EN_DEDICATED_GPIO_V  0x1
-#define SYSTEM_CLK_EN_DEDICATED_GPIO_S  7
-/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CLK_EN_ASSIST_DEBUG  (BIT(6))
-#define SYSTEM_CLK_EN_ASSIST_DEBUG_M  (BIT(6))
-#define SYSTEM_CLK_EN_ASSIST_DEBUG_V  0x1
-#define SYSTEM_CLK_EN_ASSIST_DEBUG_S  6
-
-#define SYSTEM_CPU_PERI_RST_EN_REG          (DR_REG_SYSTEM_BASE + 0x004)
-/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_RST_EN_DEDICATED_GPIO  (BIT(7))
-#define SYSTEM_RST_EN_DEDICATED_GPIO_M  (BIT(7))
-#define SYSTEM_RST_EN_DEDICATED_GPIO_V  0x1
-#define SYSTEM_RST_EN_DEDICATED_GPIO_S  7
-/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_RST_EN_ASSIST_DEBUG  (BIT(6))
-#define SYSTEM_RST_EN_ASSIST_DEBUG_M  (BIT(6))
-#define SYSTEM_RST_EN_ASSIST_DEBUG_V  0x1
-#define SYSTEM_RST_EN_ASSIST_DEBUG_S  6
-
-#define SYSTEM_CPU_PER_CONF_REG          (DR_REG_SYSTEM_BASE + 0x008)
-/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
-/*description: */
-#define SYSTEM_CPU_WAITI_DELAY_NUM  0x0000000F
-#define SYSTEM_CPU_WAITI_DELAY_NUM_M  ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S))
-#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0xF
-#define SYSTEM_CPU_WAITI_DELAY_NUM_S  4
-/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_CPU_WAIT_MODE_FORCE_ON  (BIT(3))
-#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (BIT(3))
-#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x1
-#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  3
-/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_PLL_FREQ_SEL  (BIT(2))
-#define SYSTEM_PLL_FREQ_SEL_M  (BIT(2))
-#define SYSTEM_PLL_FREQ_SEL_V  0x1
-#define SYSTEM_PLL_FREQ_SEL_S  2
-/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define SYSTEM_CPUPERIOD_SEL  0x00000003
-#define SYSTEM_CPUPERIOD_SEL_M  ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S))
-#define SYSTEM_CPUPERIOD_SEL_V  0x3
-#define SYSTEM_CPUPERIOD_SEL_S  0
-
-#define SYSTEM_MEM_PD_MASK_REG          (DR_REG_SYSTEM_BASE + 0x00C)
-/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_LSLP_MEM_PD_MASK  (BIT(0))
-#define SYSTEM_LSLP_MEM_PD_MASK_M  (BIT(0))
-#define SYSTEM_LSLP_MEM_PD_MASK_V  0x1
-#define SYSTEM_LSLP_MEM_PD_MASK_S  0
-
-#define SYSTEM_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x010)
-/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
-/*description: */
-#define SYSTEM_SPI4_CLK_EN  (BIT(31))
-#define SYSTEM_SPI4_CLK_EN_M  (BIT(31))
-#define SYSTEM_SPI4_CLK_EN_V  0x1
-#define SYSTEM_SPI4_CLK_EN_S  31
-/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_ADC2_ARB_CLK_EN  (BIT(30))
-#define SYSTEM_ADC2_ARB_CLK_EN_M  (BIT(30))
-#define SYSTEM_ADC2_ARB_CLK_EN_V  0x1
-#define SYSTEM_ADC2_ARB_CLK_EN_S  30
-/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_SYSTIMER_CLK_EN  (BIT(29))
-#define SYSTEM_SYSTIMER_CLK_EN_M  (BIT(29))
-#define SYSTEM_SYSTIMER_CLK_EN_V  0x1
-#define SYSTEM_SYSTIMER_CLK_EN_S  29
-/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_APB_SARADC_CLK_EN  (BIT(28))
-#define SYSTEM_APB_SARADC_CLK_EN_M  (BIT(28))
-#define SYSTEM_APB_SARADC_CLK_EN_V  0x1
-#define SYSTEM_APB_SARADC_CLK_EN_S  28
-/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_SPI3_DMA_CLK_EN  (BIT(27))
-#define SYSTEM_SPI3_DMA_CLK_EN_M  (BIT(27))
-#define SYSTEM_SPI3_DMA_CLK_EN_V  0x1
-#define SYSTEM_SPI3_DMA_CLK_EN_S  27
-/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PWM3_CLK_EN  (BIT(26))
-#define SYSTEM_PWM3_CLK_EN_M  (BIT(26))
-#define SYSTEM_PWM3_CLK_EN_V  0x1
-#define SYSTEM_PWM3_CLK_EN_S  26
-/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PWM2_CLK_EN  (BIT(25))
-#define SYSTEM_PWM2_CLK_EN_M  (BIT(25))
-#define SYSTEM_PWM2_CLK_EN_V  0x1
-#define SYSTEM_PWM2_CLK_EN_S  25
-/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_UART_MEM_CLK_EN  (BIT(24))
-#define SYSTEM_UART_MEM_CLK_EN_M  (BIT(24))
-#define SYSTEM_UART_MEM_CLK_EN_V  0x1
-#define SYSTEM_UART_MEM_CLK_EN_S  24
-/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_USB_DEVICE_CLK_EN  (BIT(23))
-#define SYSTEM_USB_DEVICE_CLK_EN_M  (BIT(23))
-#define SYSTEM_USB_DEVICE_CLK_EN_V  0x1
-#define SYSTEM_USB_DEVICE_CLK_EN_S  23
-/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_SPI2_DMA_CLK_EN  (BIT(22))
-#define SYSTEM_SPI2_DMA_CLK_EN_M  (BIT(22))
-#define SYSTEM_SPI2_DMA_CLK_EN_V  0x1
-#define SYSTEM_SPI2_DMA_CLK_EN_S  22
-/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_I2S1_CLK_EN  (BIT(21))
-#define SYSTEM_I2S1_CLK_EN_M  (BIT(21))
-#define SYSTEM_I2S1_CLK_EN_V  0x1
-#define SYSTEM_I2S1_CLK_EN_S  21
-/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PWM1_CLK_EN  (BIT(20))
-#define SYSTEM_PWM1_CLK_EN_M  (BIT(20))
-#define SYSTEM_PWM1_CLK_EN_V  0x1
-#define SYSTEM_PWM1_CLK_EN_S  20
-/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_TWAI_CLK_EN  (BIT(19))
-#define SYSTEM_TWAI_CLK_EN_M  (BIT(19))
-#define SYSTEM_TWAI_CLK_EN_V  0x1
-#define SYSTEM_TWAI_CLK_EN_S  19
-/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_I2C_EXT1_CLK_EN  (BIT(18))
-#define SYSTEM_I2C_EXT1_CLK_EN_M  (BIT(18))
-#define SYSTEM_I2C_EXT1_CLK_EN_V  0x1
-#define SYSTEM_I2C_EXT1_CLK_EN_S  18
-/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PWM0_CLK_EN  (BIT(17))
-#define SYSTEM_PWM0_CLK_EN_M  (BIT(17))
-#define SYSTEM_PWM0_CLK_EN_V  0x1
-#define SYSTEM_PWM0_CLK_EN_S  17
-/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_SPI3_CLK_EN  (BIT(16))
-#define SYSTEM_SPI3_CLK_EN_M  (BIT(16))
-#define SYSTEM_SPI3_CLK_EN_V  0x1
-#define SYSTEM_SPI3_CLK_EN_S  16
-/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_TIMERGROUP1_CLK_EN  (BIT(15))
-#define SYSTEM_TIMERGROUP1_CLK_EN_M  (BIT(15))
-#define SYSTEM_TIMERGROUP1_CLK_EN_V  0x1
-#define SYSTEM_TIMERGROUP1_CLK_EN_S  15
-/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_EFUSE_CLK_EN  (BIT(14))
-#define SYSTEM_EFUSE_CLK_EN_M  (BIT(14))
-#define SYSTEM_EFUSE_CLK_EN_V  0x1
-#define SYSTEM_EFUSE_CLK_EN_S  14
-/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_TIMERGROUP_CLK_EN  (BIT(13))
-#define SYSTEM_TIMERGROUP_CLK_EN_M  (BIT(13))
-#define SYSTEM_TIMERGROUP_CLK_EN_V  0x1
-#define SYSTEM_TIMERGROUP_CLK_EN_S  13
-/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_UHCI1_CLK_EN  (BIT(12))
-#define SYSTEM_UHCI1_CLK_EN_M  (BIT(12))
-#define SYSTEM_UHCI1_CLK_EN_V  0x1
-#define SYSTEM_UHCI1_CLK_EN_S  12
-/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_LEDC_CLK_EN  (BIT(11))
-#define SYSTEM_LEDC_CLK_EN_M  (BIT(11))
-#define SYSTEM_LEDC_CLK_EN_V  0x1
-#define SYSTEM_LEDC_CLK_EN_S  11
-/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PCNT_CLK_EN  (BIT(10))
-#define SYSTEM_PCNT_CLK_EN_M  (BIT(10))
-#define SYSTEM_PCNT_CLK_EN_V  0x1
-#define SYSTEM_PCNT_CLK_EN_S  10
-/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_RMT_CLK_EN  (BIT(9))
-#define SYSTEM_RMT_CLK_EN_M  (BIT(9))
-#define SYSTEM_RMT_CLK_EN_V  0x1
-#define SYSTEM_RMT_CLK_EN_S  9
-/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_UHCI0_CLK_EN  (BIT(8))
-#define SYSTEM_UHCI0_CLK_EN_M  (BIT(8))
-#define SYSTEM_UHCI0_CLK_EN_V  0x1
-#define SYSTEM_UHCI0_CLK_EN_S  8
-/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_I2C_EXT0_CLK_EN  (BIT(7))
-#define SYSTEM_I2C_EXT0_CLK_EN_M  (BIT(7))
-#define SYSTEM_I2C_EXT0_CLK_EN_V  0x1
-#define SYSTEM_I2C_EXT0_CLK_EN_S  7
-/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_SPI2_CLK_EN  (BIT(6))
-#define SYSTEM_SPI2_CLK_EN_M  (BIT(6))
-#define SYSTEM_SPI2_CLK_EN_V  0x1
-#define SYSTEM_SPI2_CLK_EN_S  6
-/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_UART1_CLK_EN  (BIT(5))
-#define SYSTEM_UART1_CLK_EN_M  (BIT(5))
-#define SYSTEM_UART1_CLK_EN_V  0x1
-#define SYSTEM_UART1_CLK_EN_S  5
-/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_I2S0_CLK_EN  (BIT(4))
-#define SYSTEM_I2S0_CLK_EN_M  (BIT(4))
-#define SYSTEM_I2S0_CLK_EN_V  0x1
-#define SYSTEM_I2S0_CLK_EN_S  4
-/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_WDG_CLK_EN  (BIT(3))
-#define SYSTEM_WDG_CLK_EN_M  (BIT(3))
-#define SYSTEM_WDG_CLK_EN_V  0x1
-#define SYSTEM_WDG_CLK_EN_S  3
-/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_UART_CLK_EN  (BIT(2))
-#define SYSTEM_UART_CLK_EN_M  (BIT(2))
-#define SYSTEM_UART_CLK_EN_V  0x1
-#define SYSTEM_UART_CLK_EN_S  2
-/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_SPI01_CLK_EN  (BIT(1))
-#define SYSTEM_SPI01_CLK_EN_M  (BIT(1))
-#define SYSTEM_SPI01_CLK_EN_V  0x1
-#define SYSTEM_SPI01_CLK_EN_S  1
-/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_TIMERS_CLK_EN  (BIT(0))
-#define SYSTEM_TIMERS_CLK_EN_M  (BIT(0))
-#define SYSTEM_TIMERS_CLK_EN_V  0x1
-#define SYSTEM_TIMERS_CLK_EN_S  0
-
-#define SYSTEM_PERIP_CLK_EN1_REG          (DR_REG_SYSTEM_BASE + 0x014)
-/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_TSENS_CLK_EN  (BIT(10))
-#define SYSTEM_TSENS_CLK_EN_M  (BIT(10))
-#define SYSTEM_TSENS_CLK_EN_V  0x1
-#define SYSTEM_TSENS_CLK_EN_S  10
-/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_LCD_CAM_CLK_EN  (BIT(8))
-#define SYSTEM_LCD_CAM_CLK_EN_M  (BIT(8))
-#define SYSTEM_LCD_CAM_CLK_EN_V  0x1
-#define SYSTEM_LCD_CAM_CLK_EN_S  8
-/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_SDIO_HOST_CLK_EN  (BIT(7))
-#define SYSTEM_SDIO_HOST_CLK_EN_M  (BIT(7))
-#define SYSTEM_SDIO_HOST_CLK_EN_V  0x1
-#define SYSTEM_SDIO_HOST_CLK_EN_S  7
-/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_DMA_CLK_EN  (BIT(6))
-#define SYSTEM_DMA_CLK_EN_M  (BIT(6))
-#define SYSTEM_DMA_CLK_EN_V  0x1
-#define SYSTEM_DMA_CLK_EN_S  6
-/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CRYPTO_HMAC_CLK_EN  (BIT(5))
-#define SYSTEM_CRYPTO_HMAC_CLK_EN_M  (BIT(5))
-#define SYSTEM_CRYPTO_HMAC_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_HMAC_CLK_EN_S  5
-/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CRYPTO_DS_CLK_EN  (BIT(4))
-#define SYSTEM_CRYPTO_DS_CLK_EN_M  (BIT(4))
-#define SYSTEM_CRYPTO_DS_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_DS_CLK_EN_S  4
-/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CRYPTO_RSA_CLK_EN  (BIT(3))
-#define SYSTEM_CRYPTO_RSA_CLK_EN_M  (BIT(3))
-#define SYSTEM_CRYPTO_RSA_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_RSA_CLK_EN_S  3
-/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CRYPTO_SHA_CLK_EN  (BIT(2))
-#define SYSTEM_CRYPTO_SHA_CLK_EN_M  (BIT(2))
-#define SYSTEM_CRYPTO_SHA_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_SHA_CLK_EN_S  2
-/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CRYPTO_AES_CLK_EN  (BIT(1))
-#define SYSTEM_CRYPTO_AES_CLK_EN_M  (BIT(1))
-#define SYSTEM_CRYPTO_AES_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_AES_CLK_EN_S  1
-
-#define SYSTEM_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x018)
-/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define SYSTEM_SPI4_RST  (BIT(31))
-#define SYSTEM_SPI4_RST_M  (BIT(31))
-#define SYSTEM_SPI4_RST_V  0x1
-#define SYSTEM_SPI4_RST_S  31
-/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_ADC2_ARB_RST  (BIT(30))
-#define SYSTEM_ADC2_ARB_RST_M  (BIT(30))
-#define SYSTEM_ADC2_ARB_RST_V  0x1
-#define SYSTEM_ADC2_ARB_RST_S  30
-/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_SYSTIMER_RST  (BIT(29))
-#define SYSTEM_SYSTIMER_RST_M  (BIT(29))
-#define SYSTEM_SYSTIMER_RST_V  0x1
-#define SYSTEM_SYSTIMER_RST_S  29
-/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_APB_SARADC_RST  (BIT(28))
-#define SYSTEM_APB_SARADC_RST_M  (BIT(28))
-#define SYSTEM_APB_SARADC_RST_V  0x1
-#define SYSTEM_APB_SARADC_RST_S  28
-/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_SPI3_DMA_RST  (BIT(27))
-#define SYSTEM_SPI3_DMA_RST_M  (BIT(27))
-#define SYSTEM_SPI3_DMA_RST_V  0x1
-#define SYSTEM_SPI3_DMA_RST_S  27
-/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PWM3_RST  (BIT(26))
-#define SYSTEM_PWM3_RST_M  (BIT(26))
-#define SYSTEM_PWM3_RST_V  0x1
-#define SYSTEM_PWM3_RST_S  26
-/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PWM2_RST  (BIT(25))
-#define SYSTEM_PWM2_RST_M  (BIT(25))
-#define SYSTEM_PWM2_RST_V  0x1
-#define SYSTEM_PWM2_RST_S  25
-/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_UART_MEM_RST  (BIT(24))
-#define SYSTEM_UART_MEM_RST_M  (BIT(24))
-#define SYSTEM_UART_MEM_RST_V  0x1
-#define SYSTEM_UART_MEM_RST_S  24
-/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_USB_DEVICE_RST  (BIT(23))
-#define SYSTEM_USB_DEVICE_RST_M  (BIT(23))
-#define SYSTEM_USB_DEVICE_RST_V  0x1
-#define SYSTEM_USB_DEVICE_RST_S  23
-/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_SPI2_DMA_RST  (BIT(22))
-#define SYSTEM_SPI2_DMA_RST_M  (BIT(22))
-#define SYSTEM_SPI2_DMA_RST_V  0x1
-#define SYSTEM_SPI2_DMA_RST_S  22
-/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_I2S1_RST  (BIT(21))
-#define SYSTEM_I2S1_RST_M  (BIT(21))
-#define SYSTEM_I2S1_RST_V  0x1
-#define SYSTEM_I2S1_RST_S  21
-/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PWM1_RST  (BIT(20))
-#define SYSTEM_PWM1_RST_M  (BIT(20))
-#define SYSTEM_PWM1_RST_V  0x1
-#define SYSTEM_PWM1_RST_S  20
-/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_TWAI_RST  (BIT(19))
-#define SYSTEM_TWAI_RST_M  (BIT(19))
-#define SYSTEM_TWAI_RST_V  0x1
-#define SYSTEM_TWAI_RST_S  19
-/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_I2C_EXT1_RST  (BIT(18))
-#define SYSTEM_I2C_EXT1_RST_M  (BIT(18))
-#define SYSTEM_I2C_EXT1_RST_V  0x1
-#define SYSTEM_I2C_EXT1_RST_S  18
-/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PWM0_RST  (BIT(17))
-#define SYSTEM_PWM0_RST_M  (BIT(17))
-#define SYSTEM_PWM0_RST_V  0x1
-#define SYSTEM_PWM0_RST_S  17
-/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_SPI3_RST  (BIT(16))
-#define SYSTEM_SPI3_RST_M  (BIT(16))
-#define SYSTEM_SPI3_RST_V  0x1
-#define SYSTEM_SPI3_RST_S  16
-/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_TIMERGROUP1_RST  (BIT(15))
-#define SYSTEM_TIMERGROUP1_RST_M  (BIT(15))
-#define SYSTEM_TIMERGROUP1_RST_V  0x1
-#define SYSTEM_TIMERGROUP1_RST_S  15
-/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_EFUSE_RST  (BIT(14))
-#define SYSTEM_EFUSE_RST_M  (BIT(14))
-#define SYSTEM_EFUSE_RST_V  0x1
-#define SYSTEM_EFUSE_RST_S  14
-/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_TIMERGROUP_RST  (BIT(13))
-#define SYSTEM_TIMERGROUP_RST_M  (BIT(13))
-#define SYSTEM_TIMERGROUP_RST_V  0x1
-#define SYSTEM_TIMERGROUP_RST_S  13
-/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_UHCI1_RST  (BIT(12))
-#define SYSTEM_UHCI1_RST_M  (BIT(12))
-#define SYSTEM_UHCI1_RST_V  0x1
-#define SYSTEM_UHCI1_RST_S  12
-/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_LEDC_RST  (BIT(11))
-#define SYSTEM_LEDC_RST_M  (BIT(11))
-#define SYSTEM_LEDC_RST_V  0x1
-#define SYSTEM_LEDC_RST_S  11
-/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_PCNT_RST  (BIT(10))
-#define SYSTEM_PCNT_RST_M  (BIT(10))
-#define SYSTEM_PCNT_RST_V  0x1
-#define SYSTEM_PCNT_RST_S  10
-/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_RMT_RST  (BIT(9))
-#define SYSTEM_RMT_RST_M  (BIT(9))
-#define SYSTEM_RMT_RST_V  0x1
-#define SYSTEM_RMT_RST_S  9
-/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_UHCI0_RST  (BIT(8))
-#define SYSTEM_UHCI0_RST_M  (BIT(8))
-#define SYSTEM_UHCI0_RST_V  0x1
-#define SYSTEM_UHCI0_RST_S  8
-/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_I2C_EXT0_RST  (BIT(7))
-#define SYSTEM_I2C_EXT0_RST_M  (BIT(7))
-#define SYSTEM_I2C_EXT0_RST_V  0x1
-#define SYSTEM_I2C_EXT0_RST_S  7
-/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_SPI2_RST  (BIT(6))
-#define SYSTEM_SPI2_RST_M  (BIT(6))
-#define SYSTEM_SPI2_RST_V  0x1
-#define SYSTEM_SPI2_RST_S  6
-/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_UART1_RST  (BIT(5))
-#define SYSTEM_UART1_RST_M  (BIT(5))
-#define SYSTEM_UART1_RST_V  0x1
-#define SYSTEM_UART1_RST_S  5
-/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_I2S0_RST  (BIT(4))
-#define SYSTEM_I2S0_RST_M  (BIT(4))
-#define SYSTEM_I2S0_RST_V  0x1
-#define SYSTEM_I2S0_RST_S  4
-/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_WDG_RST  (BIT(3))
-#define SYSTEM_WDG_RST_M  (BIT(3))
-#define SYSTEM_WDG_RST_V  0x1
-#define SYSTEM_WDG_RST_S  3
-/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_UART_RST  (BIT(2))
-#define SYSTEM_UART_RST_M  (BIT(2))
-#define SYSTEM_UART_RST_V  0x1
-#define SYSTEM_UART_RST_S  2
-/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_SPI01_RST  (BIT(1))
-#define SYSTEM_SPI01_RST_M  (BIT(1))
-#define SYSTEM_SPI01_RST_V  0x1
-#define SYSTEM_SPI01_RST_S  1
-/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_TIMERS_RST  (BIT(0))
-#define SYSTEM_TIMERS_RST_M  (BIT(0))
-#define SYSTEM_TIMERS_RST_V  0x1
-#define SYSTEM_TIMERS_RST_S  0
-
-#define SYSTEM_PERIP_RST_EN1_REG          (DR_REG_SYSTEM_BASE + 0x01C)
-/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_TSENS_RST  (BIT(10))
-#define SYSTEM_TSENS_RST_M  (BIT(10))
-#define SYSTEM_TSENS_RST_V  0x1
-#define SYSTEM_TSENS_RST_S  10
-/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_LCD_CAM_RST  (BIT(8))
-#define SYSTEM_LCD_CAM_RST_M  (BIT(8))
-#define SYSTEM_LCD_CAM_RST_V  0x1
-#define SYSTEM_LCD_CAM_RST_S  8
-/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_SDIO_HOST_RST  (BIT(7))
-#define SYSTEM_SDIO_HOST_RST_M  (BIT(7))
-#define SYSTEM_SDIO_HOST_RST_V  0x1
-#define SYSTEM_SDIO_HOST_RST_S  7
-/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_DMA_RST  (BIT(6))
-#define SYSTEM_DMA_RST_M  (BIT(6))
-#define SYSTEM_DMA_RST_V  0x1
-#define SYSTEM_DMA_RST_S  6
-/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_CRYPTO_HMAC_RST  (BIT(5))
-#define SYSTEM_CRYPTO_HMAC_RST_M  (BIT(5))
-#define SYSTEM_CRYPTO_HMAC_RST_V  0x1
-#define SYSTEM_CRYPTO_HMAC_RST_S  5
-/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_CRYPTO_DS_RST  (BIT(4))
-#define SYSTEM_CRYPTO_DS_RST_M  (BIT(4))
-#define SYSTEM_CRYPTO_DS_RST_V  0x1
-#define SYSTEM_CRYPTO_DS_RST_S  4
-/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_CRYPTO_RSA_RST  (BIT(3))
-#define SYSTEM_CRYPTO_RSA_RST_M  (BIT(3))
-#define SYSTEM_CRYPTO_RSA_RST_V  0x1
-#define SYSTEM_CRYPTO_RSA_RST_S  3
-/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_CRYPTO_SHA_RST  (BIT(2))
-#define SYSTEM_CRYPTO_SHA_RST_M  (BIT(2))
-#define SYSTEM_CRYPTO_SHA_RST_V  0x1
-#define SYSTEM_CRYPTO_SHA_RST_S  2
-/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_CRYPTO_AES_RST  (BIT(1))
-#define SYSTEM_CRYPTO_AES_RST_M  (BIT(1))
-#define SYSTEM_CRYPTO_AES_RST_V  0x1
-#define SYSTEM_CRYPTO_AES_RST_S  1
-
-#define SYSTEM_BT_LPCK_DIV_INT_REG          (DR_REG_SYSTEM_BASE + 0x020)
-/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
-/*description: */
-#define SYSTEM_BT_LPCK_DIV_NUM  0x00000FFF
-#define SYSTEM_BT_LPCK_DIV_NUM_M  ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
-#define SYSTEM_BT_LPCK_DIV_NUM_V  0xFFF
-#define SYSTEM_BT_LPCK_DIV_NUM_S  0
-
-#define SYSTEM_BT_LPCK_DIV_FRAC_REG          (DR_REG_SYSTEM_BASE + 0x024)
-/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_LPCLK_RTC_EN  (BIT(28))
-#define SYSTEM_LPCLK_RTC_EN_M  (BIT(28))
-#define SYSTEM_LPCLK_RTC_EN_V  0x1
-#define SYSTEM_LPCLK_RTC_EN_S  28
-/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_LPCLK_SEL_XTAL32K  (BIT(27))
-#define SYSTEM_LPCLK_SEL_XTAL32K_M  (BIT(27))
-#define SYSTEM_LPCLK_SEL_XTAL32K_V  0x1
-#define SYSTEM_LPCLK_SEL_XTAL32K_S  27
-/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_LPCLK_SEL_XTAL  (BIT(26))
-#define SYSTEM_LPCLK_SEL_XTAL_M  (BIT(26))
-#define SYSTEM_LPCLK_SEL_XTAL_V  0x1
-#define SYSTEM_LPCLK_SEL_XTAL_S  26
-/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_LPCLK_SEL_8M  (BIT(25))
-#define SYSTEM_LPCLK_SEL_8M_M  (BIT(25))
-#define SYSTEM_LPCLK_SEL_8M_V  0x1
-#define SYSTEM_LPCLK_SEL_8M_S  25
-/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_LPCLK_SEL_RTC_SLOW  (BIT(24))
-#define SYSTEM_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
-#define SYSTEM_LPCLK_SEL_RTC_SLOW_V  0x1
-#define SYSTEM_LPCLK_SEL_RTC_SLOW_S  24
-/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
-/*description: */
-#define SYSTEM_BT_LPCK_DIV_A  0x00000FFF
-#define SYSTEM_BT_LPCK_DIV_A_M  ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S))
-#define SYSTEM_BT_LPCK_DIV_A_V  0xFFF
-#define SYSTEM_BT_LPCK_DIV_A_S  12
-/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
-/*description: */
-#define SYSTEM_BT_LPCK_DIV_B  0x00000FFF
-#define SYSTEM_BT_LPCK_DIV_B_M  ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S))
-#define SYSTEM_BT_LPCK_DIV_B_V  0xFFF
-#define SYSTEM_BT_LPCK_DIV_B_S  0
-
-#define SYSTEM_CPU_INTR_FROM_CPU_0_REG          (DR_REG_SYSTEM_BASE + 0x028)
-/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CPU_INTR_FROM_CPU_0  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_0_M  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_0_V  0x1
-#define SYSTEM_CPU_INTR_FROM_CPU_0_S  0
-
-#define SYSTEM_CPU_INTR_FROM_CPU_1_REG          (DR_REG_SYSTEM_BASE + 0x02C)
-/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CPU_INTR_FROM_CPU_1  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_1_M  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_1_V  0x1
-#define SYSTEM_CPU_INTR_FROM_CPU_1_S  0
-
-#define SYSTEM_CPU_INTR_FROM_CPU_2_REG          (DR_REG_SYSTEM_BASE + 0x030)
-/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CPU_INTR_FROM_CPU_2  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_2_M  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_2_V  0x1
-#define SYSTEM_CPU_INTR_FROM_CPU_2_S  0
-
-#define SYSTEM_CPU_INTR_FROM_CPU_3_REG          (DR_REG_SYSTEM_BASE + 0x034)
-/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_CPU_INTR_FROM_CPU_3  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_3_M  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_3_V  0x1
-#define SYSTEM_CPU_INTR_FROM_CPU_3_S  0
-
-#define SYSTEM_RSA_PD_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x038)
-/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_RSA_MEM_FORCE_PD  (BIT(2))
-#define SYSTEM_RSA_MEM_FORCE_PD_M  (BIT(2))
-#define SYSTEM_RSA_MEM_FORCE_PD_V  0x1
-#define SYSTEM_RSA_MEM_FORCE_PD_S  2
-/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_RSA_MEM_FORCE_PU  (BIT(1))
-#define SYSTEM_RSA_MEM_FORCE_PU_M  (BIT(1))
-#define SYSTEM_RSA_MEM_FORCE_PU_V  0x1
-#define SYSTEM_RSA_MEM_FORCE_PU_S  1
-/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_RSA_MEM_PD  (BIT(0))
-#define SYSTEM_RSA_MEM_PD_M  (BIT(0))
-#define SYSTEM_RSA_MEM_PD_V  0x1
-#define SYSTEM_RSA_MEM_PD_S  0
-
-#define SYSTEM_EDMA_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x03C)
-/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_EDMA_RESET  (BIT(1))
-#define SYSTEM_EDMA_RESET_M  (BIT(1))
-#define SYSTEM_EDMA_RESET_V  0x1
-#define SYSTEM_EDMA_RESET_S  1
-/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_EDMA_CLK_ON  (BIT(0))
-#define SYSTEM_EDMA_CLK_ON_M  (BIT(0))
-#define SYSTEM_EDMA_CLK_ON_V  0x1
-#define SYSTEM_EDMA_CLK_ON_S  0
-
-#define SYSTEM_CACHE_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x040)
-/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_DCACHE_RESET  (BIT(3))
-#define SYSTEM_DCACHE_RESET_M  (BIT(3))
-#define SYSTEM_DCACHE_RESET_V  0x1
-#define SYSTEM_DCACHE_RESET_S  3
-/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_DCACHE_CLK_ON  (BIT(2))
-#define SYSTEM_DCACHE_CLK_ON_M  (BIT(2))
-#define SYSTEM_DCACHE_CLK_ON_V  0x1
-#define SYSTEM_DCACHE_CLK_ON_S  2
-/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_ICACHE_RESET  (BIT(1))
-#define SYSTEM_ICACHE_RESET_M  (BIT(1))
-#define SYSTEM_ICACHE_RESET_V  0x1
-#define SYSTEM_ICACHE_RESET_S  1
-/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_ICACHE_CLK_ON  (BIT(0))
-#define SYSTEM_ICACHE_CLK_ON_M  (BIT(0))
-#define SYSTEM_ICACHE_CLK_ON_V  0x1
-#define SYSTEM_ICACHE_CLK_ON_S  0
-
-#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x044)
-/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT  (BIT(3))
-#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(3))
-#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
-#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
-/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT  (BIT(2))
-#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (BIT(2))
-#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x1
-#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
-/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT  (BIT(1))
-#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (BIT(1))
-#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x1
-#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
-/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT  (BIT(0))
-#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (BIT(0))
-#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x1
-#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
-
-#define SYSTEM_RTC_FASTMEM_CONFIG_REG          (DR_REG_SYSTEM_BASE + 0x048)
-/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_RTC_MEM_CRC_FINISH  (BIT(31))
-#define SYSTEM_RTC_MEM_CRC_FINISH_M  (BIT(31))
-#define SYSTEM_RTC_MEM_CRC_FINISH_V  0x1
-#define SYSTEM_RTC_MEM_CRC_FINISH_S  31
-/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
-/*description: */
-#define SYSTEM_RTC_MEM_CRC_LEN  0x000007FF
-#define SYSTEM_RTC_MEM_CRC_LEN_M  ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S))
-#define SYSTEM_RTC_MEM_CRC_LEN_V  0x7FF
-#define SYSTEM_RTC_MEM_CRC_LEN_S  20
-/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
-/*description: */
-#define SYSTEM_RTC_MEM_CRC_ADDR  0x000007FF
-#define SYSTEM_RTC_MEM_CRC_ADDR_M  ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S))
-#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x7FF
-#define SYSTEM_RTC_MEM_CRC_ADDR_S  9
-/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_RTC_MEM_CRC_START  (BIT(8))
-#define SYSTEM_RTC_MEM_CRC_START_M  (BIT(8))
-#define SYSTEM_RTC_MEM_CRC_START_V  0x1
-#define SYSTEM_RTC_MEM_CRC_START_S  8
-
-#define SYSTEM_RTC_FASTMEM_CRC_REG          (DR_REG_SYSTEM_BASE + 0x04C)
-/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: */
-#define SYSTEM_RTC_MEM_CRC_RES  0xFFFFFFFF
-#define SYSTEM_RTC_MEM_CRC_RES_M  ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S))
-#define SYSTEM_RTC_MEM_CRC_RES_V  0xFFFFFFFF
-#define SYSTEM_RTC_MEM_CRC_RES_S  0
-
-#define SYSTEM_REDUNDANT_ECO_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x050)
-/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_REDUNDANT_ECO_RESULT  (BIT(1))
-#define SYSTEM_REDUNDANT_ECO_RESULT_M  (BIT(1))
-#define SYSTEM_REDUNDANT_ECO_RESULT_V  0x1
-#define SYSTEM_REDUNDANT_ECO_RESULT_S  1
-/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_REDUNDANT_ECO_DRIVE  (BIT(0))
-#define SYSTEM_REDUNDANT_ECO_DRIVE_M  (BIT(0))
-#define SYSTEM_REDUNDANT_ECO_DRIVE_V  0x1
-#define SYSTEM_REDUNDANT_ECO_DRIVE_S  0
-
-#define SYSTEM_CLOCK_GATE_REG          (DR_REG_SYSTEM_BASE + 0x054)
-/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define SYSTEM_CLK_EN  (BIT(0))
-#define SYSTEM_CLK_EN_M  (BIT(0))
-#define SYSTEM_CLK_EN_V  0x1
-#define SYSTEM_CLK_EN_S  0
-
-#define SYSTEM_SYSCLK_CONF_REG          (DR_REG_SYSTEM_BASE + 0x058)
-/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
-/*description: */
-#define SYSTEM_CLK_DIV_EN  (BIT(19))
-#define SYSTEM_CLK_DIV_EN_M  (BIT(19))
-#define SYSTEM_CLK_DIV_EN_V  0x1
-#define SYSTEM_CLK_DIV_EN_S  19
-/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */
-/*description: */
-#define SYSTEM_CLK_XTAL_FREQ  0x0000007F
-#define SYSTEM_CLK_XTAL_FREQ_M  ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S))
-#define SYSTEM_CLK_XTAL_FREQ_V  0x7F
-#define SYSTEM_CLK_XTAL_FREQ_S  12
-/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: */
-#define SYSTEM_SOC_CLK_SEL  0x00000003
-#define SYSTEM_SOC_CLK_SEL_M  ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S))
-#define SYSTEM_SOC_CLK_SEL_V  0x3
-#define SYSTEM_SOC_CLK_SEL_S  10
-/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
-/*description: */
-#define SYSTEM_PRE_DIV_CNT  0x000003FF
-#define SYSTEM_PRE_DIV_CNT_M  ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
-#define SYSTEM_PRE_DIV_CNT_V  0x3FF
-#define SYSTEM_PRE_DIV_CNT_S  0
-
-#define SYSTEM_MEM_PVT_REG          (DR_REG_SYSTEM_BASE + 0x05C)
-/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: */
-#define SYSTEM_MEM_VT_SEL  0x00000003
-#define SYSTEM_MEM_VT_SEL_M  ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S))
-#define SYSTEM_MEM_VT_SEL_V  0x3
-#define SYSTEM_MEM_VT_SEL_S  22
-/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_MEM_TIMING_ERR_CNT  0x0000FFFF
-#define SYSTEM_MEM_TIMING_ERR_CNT_M  ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S))
-#define SYSTEM_MEM_TIMING_ERR_CNT_V  0xFFFF
-#define SYSTEM_MEM_TIMING_ERR_CNT_S  6
-/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_MEM_PVT_MONITOR_EN  (BIT(5))
-#define SYSTEM_MEM_PVT_MONITOR_EN_M  (BIT(5))
-#define SYSTEM_MEM_PVT_MONITOR_EN_V  0x1
-#define SYSTEM_MEM_PVT_MONITOR_EN_S  5
-/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_MEM_ERR_CNT_CLR  (BIT(4))
-#define SYSTEM_MEM_ERR_CNT_CLR_M  (BIT(4))
-#define SYSTEM_MEM_ERR_CNT_CLR_V  0x1
-#define SYSTEM_MEM_ERR_CNT_CLR_S  4
-/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */
-/*description: */
-#define SYSTEM_MEM_PATH_LEN  0x0000000F
-#define SYSTEM_MEM_PATH_LEN_M  ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S))
-#define SYSTEM_MEM_PATH_LEN_V  0xF
-#define SYSTEM_MEM_PATH_LEN_S  0
-
-#define SYSTEM_COMB_PVT_LVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x060)
-/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_COMB_PVT_MONITOR_EN_LVT  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V  0x1
-#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S  6
-/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_COMB_ERR_CNT_CLR_LVT  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V  0x1
-#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S  5
-/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
-/*description: */
-#define SYSTEM_COMB_PATH_LEN_LVT  0x0000001F
-#define SYSTEM_COMB_PATH_LEN_LVT_M  ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
-#define SYSTEM_COMB_PATH_LEN_LVT_V  0x1F
-#define SYSTEM_COMB_PATH_LEN_LVT_S  0
-
-#define SYSTEM_COMB_PVT_NVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x064)
-/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_COMB_PVT_MONITOR_EN_NVT  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V  0x1
-#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S  6
-/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_COMB_ERR_CNT_CLR_NVT  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V  0x1
-#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S  5
-/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
-/*description: */
-#define SYSTEM_COMB_PATH_LEN_NVT  0x0000001F
-#define SYSTEM_COMB_PATH_LEN_NVT_M  ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S))
-#define SYSTEM_COMB_PATH_LEN_NVT_V  0x1F
-#define SYSTEM_COMB_PATH_LEN_NVT_S  0
-
-#define SYSTEM_COMB_PVT_HVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x068)
-/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_COMB_PVT_MONITOR_EN_HVT  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V  0x1
-#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S  6
-/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define SYSTEM_COMB_ERR_CNT_CLR_HVT  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V  0x1
-#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S  5
-/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
-/*description: */
-#define SYSTEM_COMB_PATH_LEN_HVT  0x0000001F
-#define SYSTEM_COMB_PATH_LEN_HVT_M  ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S))
-#define SYSTEM_COMB_PATH_LEN_HVT_V  0x1F
-#define SYSTEM_COMB_PATH_LEN_HVT_S  0
-
-#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x06C)
-/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S  0
-
-#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x070)
-/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S  0
-
-#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x074)
-/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S  0
-
-#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x078)
-/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S  0
-
-#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x07C)
-/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S  0
-
-#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x080)
-/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S  0
-
-#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x084)
-/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S  0
-
-#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x088)
-/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S  0
-
-#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x08C)
-/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S  0
-
-#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x090)
-/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S  0
-
-#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x094)
-/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S  0
-
-#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x098)
-/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: */
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3  0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S  0
-
-#define SYSTEM_DATE_REG          (DR_REG_SYSTEM_BASE + 0xFFC)
-/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007150 ; */
-/*description: */
-#define SYSTEM_DATE  0x0FFFFFFF
-#define SYSTEM_DATE_M  ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
-#define SYSTEM_DATE_V  0xFFFFFFF
-#define SYSTEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SYSTEM_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/system_struct.h b/components/soc/esp32c3/include/soc/system_struct.h
deleted file mode 100644
index f4cb995aa22..00000000000
--- a/components/soc/esp32c3/include/soc/system_struct.h
+++ /dev/null
@@ -1,1404 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SYSTEM_STRUCT_H_
-#define _SOC_SYSTEM_STRUCT_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-typedef volatile struct system_dev_s {
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t reg_clk_en_assist_debug       :    1;  /*reg_clk_en_assist_debug*/
-            uint32_t reg_clk_en_dedicated_gpio     :    1;  /*reg_clk_en_dedicated_gpio*/
-            uint32_t reserved8                     :    24;  /*reserved*/
-        };
-        uint32_t val;
-    } cpu_peri_clk_en;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t reg_rst_en_assist_debug       :    1;  /*reg_rst_en_assist_debug*/
-            uint32_t reg_rst_en_dedicated_gpio     :    1;  /*reg_rst_en_dedicated_gpio*/
-            uint32_t reserved8                     :    24;  /*reserved*/
-        };
-        uint32_t val;
-    } cpu_peri_rst_en;
-    union {
-        struct {
-            uint32_t reg_cpuperiod_sel             :    2;  /*reg_cpuperiod_sel*/
-            uint32_t reg_pll_freq_sel              :    1;  /*reg_pll_freq_sel*/
-            uint32_t reg_cpu_wait_mode_force_on    :    1;  /*reg_cpu_wait_mode_force_on*/
-            uint32_t reg_cpu_waiti_delay_num       :    4;  /*reg_cpu_waiti_delay_num*/
-            uint32_t reserved8                     :    24;  /*reserved*/
-        };
-        uint32_t val;
-    } cpu_per_conf;
-    union {
-        struct {
-            uint32_t reg_lslp_mem_pd_mask          :    1;  /*reg_lslp_mem_pd_mask*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } mem_pd_mask;
-    union {
-        struct {
-            uint32_t reg_timers_clk_en             :    1;  /*reg_timers_clk_en*/
-            uint32_t reg_spi01_clk_en              :    1;  /*reg_spi01_clk_en*/
-            uint32_t reg_uart_clk_en               :    1;  /*reg_uart_clk_en*/
-            uint32_t reg_wdg_clk_en                :    1;  /*reg_wdg_clk_en*/
-            uint32_t reg_i2s0_clk_en               :    1;  /*reg_i2s0_clk_en*/
-            uint32_t reg_uart1_clk_en              :    1;  /*reg_uart1_clk_en*/
-            uint32_t reg_spi2_clk_en               :    1;  /*reg_spi2_clk_en*/
-            uint32_t reg_i2c_ext0_clk_en           :    1;  /*reg_i2c_ext0_clk_en*/
-            uint32_t reg_uhci0_clk_en              :    1;  /*reg_uhci0_clk_en*/
-            uint32_t reg_rmt_clk_en                :    1;  /*reg_rmt_clk_en*/
-            uint32_t reg_pcnt_clk_en               :    1;  /*reg_pcnt_clk_en*/
-            uint32_t reg_ledc_clk_en               :    1;  /*reg_ledc_clk_en*/
-            uint32_t reg_uhci1_clk_en              :    1;  /*reg_uhci1_clk_en*/
-            uint32_t reg_timergroup_clk_en         :    1;  /*reg_timergroup_clk_en*/
-            uint32_t reg_efuse_clk_en              :    1;  /*reg_efuse_clk_en*/
-            uint32_t reg_timergroup1_clk_en        :    1;  /*reg_timergroup1_clk_en*/
-            uint32_t reg_spi3_clk_en               :    1;  /*reg_spi3_clk_en*/
-            uint32_t reg_pwm0_clk_en               :    1;  /*reg_pwm0_clk_en*/
-            uint32_t reg_i2c_ext1_clk_en           :    1;  /*reg_i2c_ext1_clk_en*/
-            uint32_t reg_can_clk_en                :    1;  /*reg_can_clk_en*/
-            uint32_t reg_pwm1_clk_en               :    1;  /*reg_pwm1_clk_en*/
-            uint32_t reg_i2s1_clk_en               :    1;  /*reg_i2s1_clk_en*/
-            uint32_t reg_spi2_dma_clk_en           :    1;  /*reg_spi2_dma_clk_en*/
-            uint32_t reg_usb_device_clk_en         :    1;  /*reg_usb_device_clk_en*/
-            uint32_t reg_uart_mem_clk_en           :    1;  /*reg_uart_mem_clk_en*/
-            uint32_t reg_pwm2_clk_en               :    1;  /*reg_pwm2_clk_en*/
-            uint32_t reg_pwm3_clk_en               :    1;  /*reg_pwm3_clk_en*/
-            uint32_t reg_spi3_dma_clk_en           :    1;  /*reg_spi3_dma_clk_en*/
-            uint32_t reg_apb_saradc_clk_en         :    1;  /*reg_apb_saradc_clk_en*/
-            uint32_t reg_systimer_clk_en           :    1;  /*reg_systimer_clk_en*/
-            uint32_t reg_adc2_arb_clk_en           :    1;  /*reg_adc2_arb_clk_en*/
-            uint32_t reg_spi4_clk_en               :    1;  /*reg_spi4_clk_en*/
-        };
-        uint32_t val;
-    } perip_clk_en0;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;  /*peripheral reset register*/
-            uint32_t reg_crypto_aes_clk_en         :    1;  /*reg_crypto_aes_clk_en*/
-            uint32_t reg_crypto_sha_clk_en         :    1;  /*reg_crypto_sha_clk_en*/
-            uint32_t reg_crypto_rsa_clk_en         :    1;  /*reg_crypto_rsa_clk_en*/
-            uint32_t reg_crypto_ds_clk_en          :    1;  /*reg_crypto_ds_clk_en*/
-            uint32_t reg_crypto_hmac_clk_en        :    1;  /*reg_crypto_hmac_clk_en*/
-            uint32_t reg_dma_clk_en                :    1;  /*reg_dma_clk_en*/
-            uint32_t reg_sdio_host_clk_en          :    1;  /*reg_sdio_host_clk_en*/
-            uint32_t reg_lcd_cam_clk_en            :    1;  /*reg_lcd_cam_clk_en*/
-            uint32_t reserved9                     :    1;  /*reserved*/
-            uint32_t reg_tsens_clk_en              :    1;  /*reg_tsens_clk_en*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } perip_clk_en1;
-    union {
-        struct {
-            uint32_t reg_timers_rst                :    1;  /*reg_timers_rst*/
-            uint32_t reg_spi01_rst                 :    1;  /*reg_spi01_rst*/
-            uint32_t reg_uart_rst                  :    1;  /*reg_uart_rst*/
-            uint32_t reg_wdg_rst                   :    1;  /*reg_wdg_rst*/
-            uint32_t reg_i2s0_rst                  :    1;  /*reg_i2s0_rst*/
-            uint32_t reg_uart1_rst                 :    1;  /*reg_uart1_rst*/
-            uint32_t reg_spi2_rst                  :    1;  /*reg_spi2_rst*/
-            uint32_t reg_i2c_ext0_rst              :    1;  /*reg_i2c_ext0_rst*/
-            uint32_t reg_uhci0_rst                 :    1;  /*reg_uhci0_rst*/
-            uint32_t reg_rmt_rst                   :    1;  /*reg_rmt_rst*/
-            uint32_t reg_pcnt_rst                  :    1;  /*reg_pcnt_rst*/
-            uint32_t reg_ledc_rst                  :    1;  /*reg_ledc_rst*/
-            uint32_t reg_uhci1_rst                 :    1;  /*reg_uhci1_rst*/
-            uint32_t reg_timergroup_rst            :    1;  /*reg_timergroup_rst*/
-            uint32_t reg_efuse_rst                 :    1;  /*reg_efuse_rst*/
-            uint32_t reg_timergroup1_rst           :    1;  /*reg_timergroup1_rst*/
-            uint32_t reg_spi3_rst                  :    1;  /*reg_spi3_rst*/
-            uint32_t reg_pwm0_rst                  :    1;  /*reg_pwm0_rst*/
-            uint32_t reg_i2c_ext1_rst              :    1;  /*reg_i2c_ext1_rst*/
-            uint32_t reg_can_rst                   :    1;  /*reg_can_rst*/
-            uint32_t reg_pwm1_rst                  :    1;  /*reg_pwm1_rst*/
-            uint32_t reg_i2s1_rst                  :    1;  /*reg_i2s1_rst*/
-            uint32_t reg_spi2_dma_rst              :    1;  /*reg_spi2_dma_rst*/
-            uint32_t reg_usb_device_rst            :    1;  /*reg_usb_device_rst*/
-            uint32_t reg_uart_mem_rst              :    1;  /*reg_uart_mem_rst*/
-            uint32_t reg_pwm2_rst                  :    1;  /*reg_pwm2_rst*/
-            uint32_t reg_pwm3_rst                  :    1;  /*reg_pwm3_rst*/
-            uint32_t reg_spi3_dma_rst              :    1;  /*reg_spi3_dma_rst*/
-            uint32_t reg_apb_saradc_rst            :    1;  /*reg_apb_saradc_rst*/
-            uint32_t reg_systimer_rst              :    1;  /*reg_systimer_rst*/
-            uint32_t reg_adc2_arb_rst              :    1;  /*reg_adc2_arb_rst*/
-            uint32_t reg_spi4_rst                  :    1;  /*reg_spi4_rst*/
-        };
-        uint32_t val;
-    } perip_rst_en0;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;  /*reserved*/
-            uint32_t reg_crypto_aes_rst            :    1;  /*reg_crypto_aes_rst*/
-            uint32_t reg_crypto_sha_rst            :    1;  /*reg_crypto_sha_rst*/
-            uint32_t reg_crypto_rsa_rst            :    1;  /*reg_crypto_rsa_rst*/
-            uint32_t reg_crypto_ds_rst             :    1;  /*reg_crypto_ds_rst*/
-            uint32_t reg_crypto_hmac_rst           :    1;  /*reg_crypto_hmac_rst*/
-            uint32_t reg_dma_rst                   :    1;  /*reg_dma_rst*/
-            uint32_t reg_sdio_host_rst             :    1;  /*reg_sdio_host_rst*/
-            uint32_t reg_lcd_cam_rst               :    1;  /*reg_lcd_cam_rst*/
-            uint32_t reserved9                     :    1;  /*reserved*/
-            uint32_t reg_tsens_rst                 :    1;  /*reg_tsens_rst*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } perip_rst_en1;
-    union {
-        struct {
-            uint32_t reg_bt_lpck_div_num           :    12;  /*reg_bt_lpck_div_num*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } bt_lpck_div_int;
-    union {
-        struct {
-            uint32_t reg_bt_lpck_div_b             :    12;  /*reg_bt_lpck_div_b*/
-            uint32_t reg_bt_lpck_div_a             :    12;  /*reg_bt_lpck_div_a*/
-            uint32_t reg_lpclk_sel_rtc_slow        :    1;  /*reg_lpclk_sel_rtc_slow*/
-            uint32_t reg_lpclk_sel_8m              :    1;  /*reg_lpclk_sel_8m*/
-            uint32_t reg_lpclk_sel_xtal            :    1;  /*reg_lpclk_sel_xtal*/
-            uint32_t reg_lpclk_sel_xtal32k         :    1;  /*reg_lpclk_sel_xtal32k*/
-            uint32_t reg_lpclk_rtc_en              :    1;  /*reg_lpclk_rtc_en*/
-            uint32_t reserved29                    :    3;  /*reserved*/
-        };
-        uint32_t val;
-    } bt_lpck_div_frac;
-    union {
-        struct {
-            uint32_t reg_cpu_intr_from_cpu_0       :    1;  /*reg_cpu_intr_from_cpu_0*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } cpu_intr_from_cpu_0;
-    union {
-        struct {
-            uint32_t reg_cpu_intr_from_cpu_1       :    1;  /*reg_cpu_intr_from_cpu_1*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } cpu_intr_from_cpu_1;
-    union {
-        struct {
-            uint32_t reg_cpu_intr_from_cpu_2       :    1;  /*reg_cpu_intr_from_cpu_2*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } cpu_intr_from_cpu_2;
-    union {
-        struct {
-            uint32_t reg_cpu_intr_from_cpu_3       :    1;  /*reg_cpu_intr_from_cpu_3*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } cpu_intr_from_cpu_3;
-    union {
-        struct {
-            uint32_t reg_rsa_mem_pd                :    1;  /*reg_rsa_mem_pd*/
-            uint32_t reg_rsa_mem_force_pu          :    1;  /*reg_rsa_mem_force_pu*/
-            uint32_t reg_rsa_mem_force_pd          :    1;  /*reg_rsa_mem_force_pd*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } rsa_pd_ctrl;
-    union {
-        struct {
-            uint32_t reg_edma_clk_on               :    1;  /*reg_edma_clk_on*/
-            uint32_t reg_edma_reset                :    1;  /*reg_edma_reset*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } edma_ctrl;
-    union {
-        struct {
-            uint32_t reg_icache_clk_on             :    1;  /*reg_icache_clk_on*/
-            uint32_t reg_icache_reset              :    1;  /*reg_icache_reset*/
-            uint32_t reg_dcache_clk_on             :    1;  /*reg_dcache_clk_on*/
-            uint32_t reg_dcache_reset              :    1;  /*reg_dcache_reset*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } cache_control;
-    union {
-        struct {
-            uint32_t reg_enable_spi_manual_encrypt :    1;  /*reg_enable_spi_manual_encrypt*/
-            uint32_t reg_enable_download_db_encrypt:    1;  /*reg_enable_download_db_encrypt*/
-            uint32_t reg_enable_download_g0cb_decrypt:    1;  /*reg_enable_download_g0cb_decrypt*/
-            uint32_t reg_enable_download_manual_encrypt:    1;  /*reg_enable_download_manual_encrypt*/
-            uint32_t reserved4                     :    28;  /*reserved*/
-        };
-        uint32_t val;
-    } external_device_encrypt_decrypt_control;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;  /*fast memory crc register*/
-            uint32_t reg_rtc_mem_crc_start         :    1;  /*reg_rtc_mem_crc_start*/
-            uint32_t reg_rtc_mem_crc_addr          :    11;  /*reg_rtc_mem_crc_addr*/
-            uint32_t reg_rtc_mem_crc_len           :    11;  /*reg_rtc_mem_crc_len*/
-            uint32_t reg_rtc_mem_crc_finish        :    1;  /*reg_rtc_mem_crc_finish*/
-        };
-        uint32_t val;
-    } rtc_fastmem_config;
-    uint32_t rtc_fastmem_crc;
-    union {
-        struct {
-            uint32_t reg_redundant_eco_drive       :    1;  /*reg_redundant_eco_drive*/
-            uint32_t reg_redundant_eco_result      :    1;  /*reg_redundant_eco_result*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } redundant_eco_ctrl;
-    union {
-        struct {
-            uint32_t reg_clk_en                    :    1;  /*reg_clk_en*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    union {
-        struct {
-            uint32_t reg_pre_div_cnt               :    10;  /*reg_pre_div_cnt*/
-            uint32_t reg_soc_clk_sel               :    2;  /*reg_soc_clk_sel*/
-            uint32_t reg_clk_xtal_freq             :    7;  /*reg_clk_xtal_freq*/
-            uint32_t reg_clk_div_en                :    1;  /*reg_clk_div_en*/
-            uint32_t reserved20                    :    12;  /*reserved*/
-        };
-        uint32_t val;
-    } sysclk_conf;
-    union {
-        struct {
-            uint32_t reg_mem_path_len              :    4;  /*reg_mem_path_len*/
-            uint32_t reg_mem_err_cnt_clr           :    1;  /*reg_mem_err_cnt_clr*/
-            uint32_t reg_mem_pvt_monitor_en        :    1;  /*reg_mem_pvt_monitor_en*/
-            uint32_t reg_mem_timing_err_cnt        :    16;  /*reg_mem_timing_err_cnt*/
-            uint32_t reg_mem_vt_sel                :    2;  /*reg_mem_vt_sel*/
-            uint32_t reserved24                    :    8;  /*reserved*/
-        };
-        uint32_t val;
-    } mem_pvt;
-    union {
-        struct {
-            uint32_t reg_comb_path_len_lvt         :    5;  /*reg_comb_path_len_lvt*/
-            uint32_t reg_comb_err_cnt_clr_lvt      :    1;  /*reg_comb_err_cnt_clr_lvt*/
-            uint32_t reg_comb_pvt_monitor_en_lvt   :    1;  /*reg_comb_pvt_monitor_en_lvt*/
-            uint32_t reserved7                     :    18;  /*reserved*/
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_lvt_conf;
-    union {
-        struct {
-            uint32_t reg_comb_path_len_nvt         :    5;  /*reg_comb_path_len_nvt*/
-            uint32_t reg_comb_err_cnt_clr_nvt      :    1;  /*reg_comb_err_cnt_clr_nvt*/
-            uint32_t reg_comb_pvt_monitor_en_nvt   :    1;  /*reg_comb_pvt_monitor_en_nvt*/
-            uint32_t reserved7                     :    18;  /*reserved*/
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_nvt_conf;
-    union {
-        struct {
-            uint32_t reg_comb_path_len_hvt         :    5;  /*reg_comb_path_len_hvt*/
-            uint32_t reg_comb_err_cnt_clr_hvt      :    1;  /*reg_comb_err_cnt_clr_hvt*/
-            uint32_t reg_comb_pvt_monitor_en_hvt   :    1;  /*reg_comb_pvt_monitor_en_hvt*/
-            uint32_t reserved7                     :    18;  /*reserved*/
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_hvt_conf;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_lvt_site0:    16;  /*reg_comb_timing_err_cnt_lvt_site0*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_lvt_site0;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_nvt_site0:    16;  /*reg_comb_timing_err_cnt_nvt_site0*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_nvt_site0;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_hvt_site0:    16;  /*reg_comb_timing_err_cnt_hvt_site0*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_hvt_site0;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_lvt_site1:    16;  /*reg_comb_timing_err_cnt_lvt_site1*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_lvt_site1;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_nvt_site1:    16;  /*reg_comb_timing_err_cnt_nvt_site1*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_nvt_site1;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_hvt_site1:    16;  /*reg_comb_timing_err_cnt_hvt_site1*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_hvt_site1;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_lvt_site2:    16;  /*reg_comb_timing_err_cnt_lvt_site2*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_lvt_site2;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_nvt_site2:    16;  /*reg_comb_timing_err_cnt_nvt_site2*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_nvt_site2;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_hvt_site2:    16;  /*reg_comb_timing_err_cnt_hvt_site2*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_hvt_site2;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_lvt_site3:    16;  /*reg_comb_timing_err_cnt_lvt_site3*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_lvt_site3;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_nvt_site3:    16;  /*reg_comb_timing_err_cnt_nvt_site3*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_nvt_site3;
-    union {
-        struct {
-            uint32_t reg_comb_timing_err_cnt_hvt_site3:    16;  /*reg_comb_timing_err_cnt_hvt_site3*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } comb_pvt_err_hvt_site3;
-    uint32_t reserved_9c;
-    uint32_t reserved_a0;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    uint32_t reserved_3fc;
-    uint32_t reserved_400;
-    uint32_t reserved_404;
-    uint32_t reserved_408;
-    uint32_t reserved_40c;
-    uint32_t reserved_410;
-    uint32_t reserved_414;
-    uint32_t reserved_418;
-    uint32_t reserved_41c;
-    uint32_t reserved_420;
-    uint32_t reserved_424;
-    uint32_t reserved_428;
-    uint32_t reserved_42c;
-    uint32_t reserved_430;
-    uint32_t reserved_434;
-    uint32_t reserved_438;
-    uint32_t reserved_43c;
-    uint32_t reserved_440;
-    uint32_t reserved_444;
-    uint32_t reserved_448;
-    uint32_t reserved_44c;
-    uint32_t reserved_450;
-    uint32_t reserved_454;
-    uint32_t reserved_458;
-    uint32_t reserved_45c;
-    uint32_t reserved_460;
-    uint32_t reserved_464;
-    uint32_t reserved_468;
-    uint32_t reserved_46c;
-    uint32_t reserved_470;
-    uint32_t reserved_474;
-    uint32_t reserved_478;
-    uint32_t reserved_47c;
-    uint32_t reserved_480;
-    uint32_t reserved_484;
-    uint32_t reserved_488;
-    uint32_t reserved_48c;
-    uint32_t reserved_490;
-    uint32_t reserved_494;
-    uint32_t reserved_498;
-    uint32_t reserved_49c;
-    uint32_t reserved_4a0;
-    uint32_t reserved_4a4;
-    uint32_t reserved_4a8;
-    uint32_t reserved_4ac;
-    uint32_t reserved_4b0;
-    uint32_t reserved_4b4;
-    uint32_t reserved_4b8;
-    uint32_t reserved_4bc;
-    uint32_t reserved_4c0;
-    uint32_t reserved_4c4;
-    uint32_t reserved_4c8;
-    uint32_t reserved_4cc;
-    uint32_t reserved_4d0;
-    uint32_t reserved_4d4;
-    uint32_t reserved_4d8;
-    uint32_t reserved_4dc;
-    uint32_t reserved_4e0;
-    uint32_t reserved_4e4;
-    uint32_t reserved_4e8;
-    uint32_t reserved_4ec;
-    uint32_t reserved_4f0;
-    uint32_t reserved_4f4;
-    uint32_t reserved_4f8;
-    uint32_t reserved_4fc;
-    uint32_t reserved_500;
-    uint32_t reserved_504;
-    uint32_t reserved_508;
-    uint32_t reserved_50c;
-    uint32_t reserved_510;
-    uint32_t reserved_514;
-    uint32_t reserved_518;
-    uint32_t reserved_51c;
-    uint32_t reserved_520;
-    uint32_t reserved_524;
-    uint32_t reserved_528;
-    uint32_t reserved_52c;
-    uint32_t reserved_530;
-    uint32_t reserved_534;
-    uint32_t reserved_538;
-    uint32_t reserved_53c;
-    uint32_t reserved_540;
-    uint32_t reserved_544;
-    uint32_t reserved_548;
-    uint32_t reserved_54c;
-    uint32_t reserved_550;
-    uint32_t reserved_554;
-    uint32_t reserved_558;
-    uint32_t reserved_55c;
-    uint32_t reserved_560;
-    uint32_t reserved_564;
-    uint32_t reserved_568;
-    uint32_t reserved_56c;
-    uint32_t reserved_570;
-    uint32_t reserved_574;
-    uint32_t reserved_578;
-    uint32_t reserved_57c;
-    uint32_t reserved_580;
-    uint32_t reserved_584;
-    uint32_t reserved_588;
-    uint32_t reserved_58c;
-    uint32_t reserved_590;
-    uint32_t reserved_594;
-    uint32_t reserved_598;
-    uint32_t reserved_59c;
-    uint32_t reserved_5a0;
-    uint32_t reserved_5a4;
-    uint32_t reserved_5a8;
-    uint32_t reserved_5ac;
-    uint32_t reserved_5b0;
-    uint32_t reserved_5b4;
-    uint32_t reserved_5b8;
-    uint32_t reserved_5bc;
-    uint32_t reserved_5c0;
-    uint32_t reserved_5c4;
-    uint32_t reserved_5c8;
-    uint32_t reserved_5cc;
-    uint32_t reserved_5d0;
-    uint32_t reserved_5d4;
-    uint32_t reserved_5d8;
-    uint32_t reserved_5dc;
-    uint32_t reserved_5e0;
-    uint32_t reserved_5e4;
-    uint32_t reserved_5e8;
-    uint32_t reserved_5ec;
-    uint32_t reserved_5f0;
-    uint32_t reserved_5f4;
-    uint32_t reserved_5f8;
-    uint32_t reserved_5fc;
-    uint32_t reserved_600;
-    uint32_t reserved_604;
-    uint32_t reserved_608;
-    uint32_t reserved_60c;
-    uint32_t reserved_610;
-    uint32_t reserved_614;
-    uint32_t reserved_618;
-    uint32_t reserved_61c;
-    uint32_t reserved_620;
-    uint32_t reserved_624;
-    uint32_t reserved_628;
-    uint32_t reserved_62c;
-    uint32_t reserved_630;
-    uint32_t reserved_634;
-    uint32_t reserved_638;
-    uint32_t reserved_63c;
-    uint32_t reserved_640;
-    uint32_t reserved_644;
-    uint32_t reserved_648;
-    uint32_t reserved_64c;
-    uint32_t reserved_650;
-    uint32_t reserved_654;
-    uint32_t reserved_658;
-    uint32_t reserved_65c;
-    uint32_t reserved_660;
-    uint32_t reserved_664;
-    uint32_t reserved_668;
-    uint32_t reserved_66c;
-    uint32_t reserved_670;
-    uint32_t reserved_674;
-    uint32_t reserved_678;
-    uint32_t reserved_67c;
-    uint32_t reserved_680;
-    uint32_t reserved_684;
-    uint32_t reserved_688;
-    uint32_t reserved_68c;
-    uint32_t reserved_690;
-    uint32_t reserved_694;
-    uint32_t reserved_698;
-    uint32_t reserved_69c;
-    uint32_t reserved_6a0;
-    uint32_t reserved_6a4;
-    uint32_t reserved_6a8;
-    uint32_t reserved_6ac;
-    uint32_t reserved_6b0;
-    uint32_t reserved_6b4;
-    uint32_t reserved_6b8;
-    uint32_t reserved_6bc;
-    uint32_t reserved_6c0;
-    uint32_t reserved_6c4;
-    uint32_t reserved_6c8;
-    uint32_t reserved_6cc;
-    uint32_t reserved_6d0;
-    uint32_t reserved_6d4;
-    uint32_t reserved_6d8;
-    uint32_t reserved_6dc;
-    uint32_t reserved_6e0;
-    uint32_t reserved_6e4;
-    uint32_t reserved_6e8;
-    uint32_t reserved_6ec;
-    uint32_t reserved_6f0;
-    uint32_t reserved_6f4;
-    uint32_t reserved_6f8;
-    uint32_t reserved_6fc;
-    uint32_t reserved_700;
-    uint32_t reserved_704;
-    uint32_t reserved_708;
-    uint32_t reserved_70c;
-    uint32_t reserved_710;
-    uint32_t reserved_714;
-    uint32_t reserved_718;
-    uint32_t reserved_71c;
-    uint32_t reserved_720;
-    uint32_t reserved_724;
-    uint32_t reserved_728;
-    uint32_t reserved_72c;
-    uint32_t reserved_730;
-    uint32_t reserved_734;
-    uint32_t reserved_738;
-    uint32_t reserved_73c;
-    uint32_t reserved_740;
-    uint32_t reserved_744;
-    uint32_t reserved_748;
-    uint32_t reserved_74c;
-    uint32_t reserved_750;
-    uint32_t reserved_754;
-    uint32_t reserved_758;
-    uint32_t reserved_75c;
-    uint32_t reserved_760;
-    uint32_t reserved_764;
-    uint32_t reserved_768;
-    uint32_t reserved_76c;
-    uint32_t reserved_770;
-    uint32_t reserved_774;
-    uint32_t reserved_778;
-    uint32_t reserved_77c;
-    uint32_t reserved_780;
-    uint32_t reserved_784;
-    uint32_t reserved_788;
-    uint32_t reserved_78c;
-    uint32_t reserved_790;
-    uint32_t reserved_794;
-    uint32_t reserved_798;
-    uint32_t reserved_79c;
-    uint32_t reserved_7a0;
-    uint32_t reserved_7a4;
-    uint32_t reserved_7a8;
-    uint32_t reserved_7ac;
-    uint32_t reserved_7b0;
-    uint32_t reserved_7b4;
-    uint32_t reserved_7b8;
-    uint32_t reserved_7bc;
-    uint32_t reserved_7c0;
-    uint32_t reserved_7c4;
-    uint32_t reserved_7c8;
-    uint32_t reserved_7cc;
-    uint32_t reserved_7d0;
-    uint32_t reserved_7d4;
-    uint32_t reserved_7d8;
-    uint32_t reserved_7dc;
-    uint32_t reserved_7e0;
-    uint32_t reserved_7e4;
-    uint32_t reserved_7e8;
-    uint32_t reserved_7ec;
-    uint32_t reserved_7f0;
-    uint32_t reserved_7f4;
-    uint32_t reserved_7f8;
-    uint32_t reserved_7fc;
-    uint32_t reserved_800;
-    uint32_t reserved_804;
-    uint32_t reserved_808;
-    uint32_t reserved_80c;
-    uint32_t reserved_810;
-    uint32_t reserved_814;
-    uint32_t reserved_818;
-    uint32_t reserved_81c;
-    uint32_t reserved_820;
-    uint32_t reserved_824;
-    uint32_t reserved_828;
-    uint32_t reserved_82c;
-    uint32_t reserved_830;
-    uint32_t reserved_834;
-    uint32_t reserved_838;
-    uint32_t reserved_83c;
-    uint32_t reserved_840;
-    uint32_t reserved_844;
-    uint32_t reserved_848;
-    uint32_t reserved_84c;
-    uint32_t reserved_850;
-    uint32_t reserved_854;
-    uint32_t reserved_858;
-    uint32_t reserved_85c;
-    uint32_t reserved_860;
-    uint32_t reserved_864;
-    uint32_t reserved_868;
-    uint32_t reserved_86c;
-    uint32_t reserved_870;
-    uint32_t reserved_874;
-    uint32_t reserved_878;
-    uint32_t reserved_87c;
-    uint32_t reserved_880;
-    uint32_t reserved_884;
-    uint32_t reserved_888;
-    uint32_t reserved_88c;
-    uint32_t reserved_890;
-    uint32_t reserved_894;
-    uint32_t reserved_898;
-    uint32_t reserved_89c;
-    uint32_t reserved_8a0;
-    uint32_t reserved_8a4;
-    uint32_t reserved_8a8;
-    uint32_t reserved_8ac;
-    uint32_t reserved_8b0;
-    uint32_t reserved_8b4;
-    uint32_t reserved_8b8;
-    uint32_t reserved_8bc;
-    uint32_t reserved_8c0;
-    uint32_t reserved_8c4;
-    uint32_t reserved_8c8;
-    uint32_t reserved_8cc;
-    uint32_t reserved_8d0;
-    uint32_t reserved_8d4;
-    uint32_t reserved_8d8;
-    uint32_t reserved_8dc;
-    uint32_t reserved_8e0;
-    uint32_t reserved_8e4;
-    uint32_t reserved_8e8;
-    uint32_t reserved_8ec;
-    uint32_t reserved_8f0;
-    uint32_t reserved_8f4;
-    uint32_t reserved_8f8;
-    uint32_t reserved_8fc;
-    uint32_t reserved_900;
-    uint32_t reserved_904;
-    uint32_t reserved_908;
-    uint32_t reserved_90c;
-    uint32_t reserved_910;
-    uint32_t reserved_914;
-    uint32_t reserved_918;
-    uint32_t reserved_91c;
-    uint32_t reserved_920;
-    uint32_t reserved_924;
-    uint32_t reserved_928;
-    uint32_t reserved_92c;
-    uint32_t reserved_930;
-    uint32_t reserved_934;
-    uint32_t reserved_938;
-    uint32_t reserved_93c;
-    uint32_t reserved_940;
-    uint32_t reserved_944;
-    uint32_t reserved_948;
-    uint32_t reserved_94c;
-    uint32_t reserved_950;
-    uint32_t reserved_954;
-    uint32_t reserved_958;
-    uint32_t reserved_95c;
-    uint32_t reserved_960;
-    uint32_t reserved_964;
-    uint32_t reserved_968;
-    uint32_t reserved_96c;
-    uint32_t reserved_970;
-    uint32_t reserved_974;
-    uint32_t reserved_978;
-    uint32_t reserved_97c;
-    uint32_t reserved_980;
-    uint32_t reserved_984;
-    uint32_t reserved_988;
-    uint32_t reserved_98c;
-    uint32_t reserved_990;
-    uint32_t reserved_994;
-    uint32_t reserved_998;
-    uint32_t reserved_99c;
-    uint32_t reserved_9a0;
-    uint32_t reserved_9a4;
-    uint32_t reserved_9a8;
-    uint32_t reserved_9ac;
-    uint32_t reserved_9b0;
-    uint32_t reserved_9b4;
-    uint32_t reserved_9b8;
-    uint32_t reserved_9bc;
-    uint32_t reserved_9c0;
-    uint32_t reserved_9c4;
-    uint32_t reserved_9c8;
-    uint32_t reserved_9cc;
-    uint32_t reserved_9d0;
-    uint32_t reserved_9d4;
-    uint32_t reserved_9d8;
-    uint32_t reserved_9dc;
-    uint32_t reserved_9e0;
-    uint32_t reserved_9e4;
-    uint32_t reserved_9e8;
-    uint32_t reserved_9ec;
-    uint32_t reserved_9f0;
-    uint32_t reserved_9f4;
-    uint32_t reserved_9f8;
-    uint32_t reserved_9fc;
-    uint32_t reserved_a00;
-    uint32_t reserved_a04;
-    uint32_t reserved_a08;
-    uint32_t reserved_a0c;
-    uint32_t reserved_a10;
-    uint32_t reserved_a14;
-    uint32_t reserved_a18;
-    uint32_t reserved_a1c;
-    uint32_t reserved_a20;
-    uint32_t reserved_a24;
-    uint32_t reserved_a28;
-    uint32_t reserved_a2c;
-    uint32_t reserved_a30;
-    uint32_t reserved_a34;
-    uint32_t reserved_a38;
-    uint32_t reserved_a3c;
-    uint32_t reserved_a40;
-    uint32_t reserved_a44;
-    uint32_t reserved_a48;
-    uint32_t reserved_a4c;
-    uint32_t reserved_a50;
-    uint32_t reserved_a54;
-    uint32_t reserved_a58;
-    uint32_t reserved_a5c;
-    uint32_t reserved_a60;
-    uint32_t reserved_a64;
-    uint32_t reserved_a68;
-    uint32_t reserved_a6c;
-    uint32_t reserved_a70;
-    uint32_t reserved_a74;
-    uint32_t reserved_a78;
-    uint32_t reserved_a7c;
-    uint32_t reserved_a80;
-    uint32_t reserved_a84;
-    uint32_t reserved_a88;
-    uint32_t reserved_a8c;
-    uint32_t reserved_a90;
-    uint32_t reserved_a94;
-    uint32_t reserved_a98;
-    uint32_t reserved_a9c;
-    uint32_t reserved_aa0;
-    uint32_t reserved_aa4;
-    uint32_t reserved_aa8;
-    uint32_t reserved_aac;
-    uint32_t reserved_ab0;
-    uint32_t reserved_ab4;
-    uint32_t reserved_ab8;
-    uint32_t reserved_abc;
-    uint32_t reserved_ac0;
-    uint32_t reserved_ac4;
-    uint32_t reserved_ac8;
-    uint32_t reserved_acc;
-    uint32_t reserved_ad0;
-    uint32_t reserved_ad4;
-    uint32_t reserved_ad8;
-    uint32_t reserved_adc;
-    uint32_t reserved_ae0;
-    uint32_t reserved_ae4;
-    uint32_t reserved_ae8;
-    uint32_t reserved_aec;
-    uint32_t reserved_af0;
-    uint32_t reserved_af4;
-    uint32_t reserved_af8;
-    uint32_t reserved_afc;
-    uint32_t reserved_b00;
-    uint32_t reserved_b04;
-    uint32_t reserved_b08;
-    uint32_t reserved_b0c;
-    uint32_t reserved_b10;
-    uint32_t reserved_b14;
-    uint32_t reserved_b18;
-    uint32_t reserved_b1c;
-    uint32_t reserved_b20;
-    uint32_t reserved_b24;
-    uint32_t reserved_b28;
-    uint32_t reserved_b2c;
-    uint32_t reserved_b30;
-    uint32_t reserved_b34;
-    uint32_t reserved_b38;
-    uint32_t reserved_b3c;
-    uint32_t reserved_b40;
-    uint32_t reserved_b44;
-    uint32_t reserved_b48;
-    uint32_t reserved_b4c;
-    uint32_t reserved_b50;
-    uint32_t reserved_b54;
-    uint32_t reserved_b58;
-    uint32_t reserved_b5c;
-    uint32_t reserved_b60;
-    uint32_t reserved_b64;
-    uint32_t reserved_b68;
-    uint32_t reserved_b6c;
-    uint32_t reserved_b70;
-    uint32_t reserved_b74;
-    uint32_t reserved_b78;
-    uint32_t reserved_b7c;
-    uint32_t reserved_b80;
-    uint32_t reserved_b84;
-    uint32_t reserved_b88;
-    uint32_t reserved_b8c;
-    uint32_t reserved_b90;
-    uint32_t reserved_b94;
-    uint32_t reserved_b98;
-    uint32_t reserved_b9c;
-    uint32_t reserved_ba0;
-    uint32_t reserved_ba4;
-    uint32_t reserved_ba8;
-    uint32_t reserved_bac;
-    uint32_t reserved_bb0;
-    uint32_t reserved_bb4;
-    uint32_t reserved_bb8;
-    uint32_t reserved_bbc;
-    uint32_t reserved_bc0;
-    uint32_t reserved_bc4;
-    uint32_t reserved_bc8;
-    uint32_t reserved_bcc;
-    uint32_t reserved_bd0;
-    uint32_t reserved_bd4;
-    uint32_t reserved_bd8;
-    uint32_t reserved_bdc;
-    uint32_t reserved_be0;
-    uint32_t reserved_be4;
-    uint32_t reserved_be8;
-    uint32_t reserved_bec;
-    uint32_t reserved_bf0;
-    uint32_t reserved_bf4;
-    uint32_t reserved_bf8;
-    uint32_t reserved_bfc;
-    uint32_t reserved_c00;
-    uint32_t reserved_c04;
-    uint32_t reserved_c08;
-    uint32_t reserved_c0c;
-    uint32_t reserved_c10;
-    uint32_t reserved_c14;
-    uint32_t reserved_c18;
-    uint32_t reserved_c1c;
-    uint32_t reserved_c20;
-    uint32_t reserved_c24;
-    uint32_t reserved_c28;
-    uint32_t reserved_c2c;
-    uint32_t reserved_c30;
-    uint32_t reserved_c34;
-    uint32_t reserved_c38;
-    uint32_t reserved_c3c;
-    uint32_t reserved_c40;
-    uint32_t reserved_c44;
-    uint32_t reserved_c48;
-    uint32_t reserved_c4c;
-    uint32_t reserved_c50;
-    uint32_t reserved_c54;
-    uint32_t reserved_c58;
-    uint32_t reserved_c5c;
-    uint32_t reserved_c60;
-    uint32_t reserved_c64;
-    uint32_t reserved_c68;
-    uint32_t reserved_c6c;
-    uint32_t reserved_c70;
-    uint32_t reserved_c74;
-    uint32_t reserved_c78;
-    uint32_t reserved_c7c;
-    uint32_t reserved_c80;
-    uint32_t reserved_c84;
-    uint32_t reserved_c88;
-    uint32_t reserved_c8c;
-    uint32_t reserved_c90;
-    uint32_t reserved_c94;
-    uint32_t reserved_c98;
-    uint32_t reserved_c9c;
-    uint32_t reserved_ca0;
-    uint32_t reserved_ca4;
-    uint32_t reserved_ca8;
-    uint32_t reserved_cac;
-    uint32_t reserved_cb0;
-    uint32_t reserved_cb4;
-    uint32_t reserved_cb8;
-    uint32_t reserved_cbc;
-    uint32_t reserved_cc0;
-    uint32_t reserved_cc4;
-    uint32_t reserved_cc8;
-    uint32_t reserved_ccc;
-    uint32_t reserved_cd0;
-    uint32_t reserved_cd4;
-    uint32_t reserved_cd8;
-    uint32_t reserved_cdc;
-    uint32_t reserved_ce0;
-    uint32_t reserved_ce4;
-    uint32_t reserved_ce8;
-    uint32_t reserved_cec;
-    uint32_t reserved_cf0;
-    uint32_t reserved_cf4;
-    uint32_t reserved_cf8;
-    uint32_t reserved_cfc;
-    uint32_t reserved_d00;
-    uint32_t reserved_d04;
-    uint32_t reserved_d08;
-    uint32_t reserved_d0c;
-    uint32_t reserved_d10;
-    uint32_t reserved_d14;
-    uint32_t reserved_d18;
-    uint32_t reserved_d1c;
-    uint32_t reserved_d20;
-    uint32_t reserved_d24;
-    uint32_t reserved_d28;
-    uint32_t reserved_d2c;
-    uint32_t reserved_d30;
-    uint32_t reserved_d34;
-    uint32_t reserved_d38;
-    uint32_t reserved_d3c;
-    uint32_t reserved_d40;
-    uint32_t reserved_d44;
-    uint32_t reserved_d48;
-    uint32_t reserved_d4c;
-    uint32_t reserved_d50;
-    uint32_t reserved_d54;
-    uint32_t reserved_d58;
-    uint32_t reserved_d5c;
-    uint32_t reserved_d60;
-    uint32_t reserved_d64;
-    uint32_t reserved_d68;
-    uint32_t reserved_d6c;
-    uint32_t reserved_d70;
-    uint32_t reserved_d74;
-    uint32_t reserved_d78;
-    uint32_t reserved_d7c;
-    uint32_t reserved_d80;
-    uint32_t reserved_d84;
-    uint32_t reserved_d88;
-    uint32_t reserved_d8c;
-    uint32_t reserved_d90;
-    uint32_t reserved_d94;
-    uint32_t reserved_d98;
-    uint32_t reserved_d9c;
-    uint32_t reserved_da0;
-    uint32_t reserved_da4;
-    uint32_t reserved_da8;
-    uint32_t reserved_dac;
-    uint32_t reserved_db0;
-    uint32_t reserved_db4;
-    uint32_t reserved_db8;
-    uint32_t reserved_dbc;
-    uint32_t reserved_dc0;
-    uint32_t reserved_dc4;
-    uint32_t reserved_dc8;
-    uint32_t reserved_dcc;
-    uint32_t reserved_dd0;
-    uint32_t reserved_dd4;
-    uint32_t reserved_dd8;
-    uint32_t reserved_ddc;
-    uint32_t reserved_de0;
-    uint32_t reserved_de4;
-    uint32_t reserved_de8;
-    uint32_t reserved_dec;
-    uint32_t reserved_df0;
-    uint32_t reserved_df4;
-    uint32_t reserved_df8;
-    uint32_t reserved_dfc;
-    uint32_t reserved_e00;
-    uint32_t reserved_e04;
-    uint32_t reserved_e08;
-    uint32_t reserved_e0c;
-    uint32_t reserved_e10;
-    uint32_t reserved_e14;
-    uint32_t reserved_e18;
-    uint32_t reserved_e1c;
-    uint32_t reserved_e20;
-    uint32_t reserved_e24;
-    uint32_t reserved_e28;
-    uint32_t reserved_e2c;
-    uint32_t reserved_e30;
-    uint32_t reserved_e34;
-    uint32_t reserved_e38;
-    uint32_t reserved_e3c;
-    uint32_t reserved_e40;
-    uint32_t reserved_e44;
-    uint32_t reserved_e48;
-    uint32_t reserved_e4c;
-    uint32_t reserved_e50;
-    uint32_t reserved_e54;
-    uint32_t reserved_e58;
-    uint32_t reserved_e5c;
-    uint32_t reserved_e60;
-    uint32_t reserved_e64;
-    uint32_t reserved_e68;
-    uint32_t reserved_e6c;
-    uint32_t reserved_e70;
-    uint32_t reserved_e74;
-    uint32_t reserved_e78;
-    uint32_t reserved_e7c;
-    uint32_t reserved_e80;
-    uint32_t reserved_e84;
-    uint32_t reserved_e88;
-    uint32_t reserved_e8c;
-    uint32_t reserved_e90;
-    uint32_t reserved_e94;
-    uint32_t reserved_e98;
-    uint32_t reserved_e9c;
-    uint32_t reserved_ea0;
-    uint32_t reserved_ea4;
-    uint32_t reserved_ea8;
-    uint32_t reserved_eac;
-    uint32_t reserved_eb0;
-    uint32_t reserved_eb4;
-    uint32_t reserved_eb8;
-    uint32_t reserved_ebc;
-    uint32_t reserved_ec0;
-    uint32_t reserved_ec4;
-    uint32_t reserved_ec8;
-    uint32_t reserved_ecc;
-    uint32_t reserved_ed0;
-    uint32_t reserved_ed4;
-    uint32_t reserved_ed8;
-    uint32_t reserved_edc;
-    uint32_t reserved_ee0;
-    uint32_t reserved_ee4;
-    uint32_t reserved_ee8;
-    uint32_t reserved_eec;
-    uint32_t reserved_ef0;
-    uint32_t reserved_ef4;
-    uint32_t reserved_ef8;
-    uint32_t reserved_efc;
-    uint32_t reserved_f00;
-    uint32_t reserved_f04;
-    uint32_t reserved_f08;
-    uint32_t reserved_f0c;
-    uint32_t reserved_f10;
-    uint32_t reserved_f14;
-    uint32_t reserved_f18;
-    uint32_t reserved_f1c;
-    uint32_t reserved_f20;
-    uint32_t reserved_f24;
-    uint32_t reserved_f28;
-    uint32_t reserved_f2c;
-    uint32_t reserved_f30;
-    uint32_t reserved_f34;
-    uint32_t reserved_f38;
-    uint32_t reserved_f3c;
-    uint32_t reserved_f40;
-    uint32_t reserved_f44;
-    uint32_t reserved_f48;
-    uint32_t reserved_f4c;
-    uint32_t reserved_f50;
-    uint32_t reserved_f54;
-    uint32_t reserved_f58;
-    uint32_t reserved_f5c;
-    uint32_t reserved_f60;
-    uint32_t reserved_f64;
-    uint32_t reserved_f68;
-    uint32_t reserved_f6c;
-    uint32_t reserved_f70;
-    uint32_t reserved_f74;
-    uint32_t reserved_f78;
-    uint32_t reserved_f7c;
-    uint32_t reserved_f80;
-    uint32_t reserved_f84;
-    uint32_t reserved_f88;
-    uint32_t reserved_f8c;
-    uint32_t reserved_f90;
-    uint32_t reserved_f94;
-    uint32_t reserved_f98;
-    uint32_t reserved_f9c;
-    uint32_t reserved_fa0;
-    uint32_t reserved_fa4;
-    uint32_t reserved_fa8;
-    uint32_t reserved_fac;
-    uint32_t reserved_fb0;
-    uint32_t reserved_fb4;
-    uint32_t reserved_fb8;
-    uint32_t reserved_fbc;
-    uint32_t reserved_fc0;
-    uint32_t reserved_fc4;
-    uint32_t reserved_fc8;
-    uint32_t reserved_fcc;
-    uint32_t reserved_fd0;
-    uint32_t reserved_fd4;
-    uint32_t reserved_fd8;
-    uint32_t reserved_fdc;
-    uint32_t reserved_fe0;
-    uint32_t reserved_fe4;
-    uint32_t reserved_fe8;
-    uint32_t reserved_fec;
-    uint32_t reserved_ff0;
-    uint32_t reserved_ff4;
-    uint32_t reserved_ff8;
-    union {
-        struct {
-            uint32_t reg_system_reg_date           :    28;  /*reg_system_reg_date*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} system_dev_t;
-extern system_dev_t SYSTEM;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SYSTEM_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/systimer_reg.h b/components/soc/esp32c3/include/soc/systimer_reg.h
deleted file mode 100644
index 4e9f64fffa8..00000000000
--- a/components/soc/esp32c3/include/soc/systimer_reg.h
+++ /dev/null
@@ -1,567 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SYSTIMER_CONF_REG register
- *  SYSTIMER_CONF.
- */
-#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
-/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
- *  systimer clock force on
- */
-#define SYSTIMER_SYSTIMER_CLK_FO    (BIT(0))
-#define SYSTIMER_SYSTIMER_CLK_FO_M  (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
-#define SYSTIMER_SYSTIMER_CLK_FO_V  0x00000001
-#define SYSTIMER_SYSTIMER_CLK_FO_S  0
-/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
- *  target2 work enable
- */
-#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
-#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
-#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001
-#define SYSTIMER_TARGET2_WORK_EN_S  22
-/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
- *  target1 work enable
- */
-#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
-#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
-#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001
-#define SYSTIMER_TARGET1_WORK_EN_S  23
-/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
- *  target0 work enable
- */
-#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
-#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
-#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001
-#define SYSTIMER_TARGET0_WORK_EN_S  24
-/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
- *  If timer unit1 is stalled when core1 stalled
- */
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
-/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
- *  If timer unit1 is stalled when core0 stalled
- */
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
-/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
- *  If timer unit0 is stalled when core1 stalled
- */
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
-/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
- *  If timer unit0 is stalled when core0 stalled
- */
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
-/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
- *  timer unit1 work enable
- */
-#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
-/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
- *  timer unit0 work enable
- */
-#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
-/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  register file clk gating
- */
-#define SYSTIMER_CLK_EN    (BIT(31))
-#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
-#define SYSTIMER_CLK_EN_V  0x00000001
-#define SYSTIMER_CLK_EN_S  31
-
-/** SYSTIMER_UNIT0_OP_REG register
- *  SYSTIMER_UNIT0_OP.
- */
-#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
-/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  reg_timer_unit0_value_valid
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
-/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
- *  update timer_unit0
- */
-#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
-#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
-
-/** SYSTIMER_UNIT1_OP_REG register
- *  SYSTIMER_UNIT1_OP.
- */
-#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
-/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  timer value is sync and valid
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
-/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
- *  update timer unit1
- */
-#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
-#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
-
-/** SYSTIMER_UNIT0_LOAD_HI_REG register
- *  SYSTIMER_UNIT0_LOAD_HI.
- */
-#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
-/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit0 load high 32 bit
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFF
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
-
-/** SYSTIMER_UNIT0_LOAD_LO_REG register
- *  SYSTIMER_UNIT0_LOAD_LO.
- */
-#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
-/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit0 load low 32 bit
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
-
-/** SYSTIMER_UNIT1_LOAD_HI_REG register
- *  SYSTIMER_UNIT1_LOAD_HI.
- */
-#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
-/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit1 load high 32 bit
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFF
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
-
-/** SYSTIMER_UNIT1_LOAD_LO_REG register
- *  SYSTIMER_UNIT1_LOAD_LO.
- */
-#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
-/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit1 load low 32 bit
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
-
-/** SYSTIMER_TARGET0_HI_REG register
- *  SYSTIMER_TARGET0_HI.
- */
-#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
-/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget0 high 32 bit
- */
-#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFF
-#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
-#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_TARGET0_HI_S  0
-
-/** SYSTIMER_TARGET0_LO_REG register
- *  SYSTIMER_TARGET0_LO.
- */
-#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
-/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget0 low 32 bit
- */
-#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
-#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET0_LO_S  0
-
-/** SYSTIMER_TARGET1_HI_REG register
- *  SYSTIMER_TARGET1_HI.
- */
-#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
-/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget1 high 32 bit
- */
-#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFF
-#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
-#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_TARGET1_HI_S  0
-
-/** SYSTIMER_TARGET1_LO_REG register
- *  SYSTIMER_TARGET1_LO.
- */
-#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
-/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget1 low 32 bit
- */
-#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
-#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET1_LO_S  0
-
-/** SYSTIMER_TARGET2_HI_REG register
- *  SYSTIMER_TARGET2_HI.
- */
-#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
-/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget2 high 32 bit
- */
-#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFF
-#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
-#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_TARGET2_HI_S  0
-
-/** SYSTIMER_TARGET2_LO_REG register
- *  SYSTIMER_TARGET2_LO.
- */
-#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
-/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget2 low 32 bit
- */
-#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
-#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET2_LO_S  0
-
-/** SYSTIMER_TARGET0_CONF_REG register
- *  SYSTIMER_TARGET0_CONF.
- */
-#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
-/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target0 period
- */
-#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFF
-#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
-#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFF
-#define SYSTIMER_TARGET0_PERIOD_S  0
-/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target0 to period mode
- */
-#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
-#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001
-#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_TARGET1_CONF_REG register
- *  SYSTIMER_TARGET1_CONF.
- */
-#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
-/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target1 period
- */
-#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFF
-#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
-#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFF
-#define SYSTIMER_TARGET1_PERIOD_S  0
-/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target1 to period mode
- */
-#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
-#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001
-#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_TARGET2_CONF_REG register
- *  SYSTIMER_TARGET2_CONF.
- */
-#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
-/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target2 period
- */
-#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFF
-#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
-#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFF
-#define SYSTIMER_TARGET2_PERIOD_S  0
-/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target2 to period mode
- */
-#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
-#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001
-#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_UNIT0_VALUE_HI_REG register
- *  SYSTIMER_UNIT0_VALUE_HI.
- */
-#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
-/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 32bit
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFF
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
-
-/** SYSTIMER_UNIT0_VALUE_LO_REG register
- *  SYSTIMER_UNIT0_VALUE_LO.
- */
-#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
-/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bit
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
-
-/** SYSTIMER_UNIT1_VALUE_HI_REG register
- *  SYSTIMER_UNIT1_VALUE_HI.
- */
-#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
-/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 32bit
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFF
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
-
-/** SYSTIMER_UNIT1_VALUE_LO_REG register
- *  SYSTIMER_UNIT1_VALUE_LO.
- */
-#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
-/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bit
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
-
-/** SYSTIMER_COMP0_LOAD_REG register
- *  SYSTIMER_COMP0_LOAD.
- */
-#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
-/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp0 load value
- */
-#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
-#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_COMP0_LOAD_S  0
-
-/** SYSTIMER_COMP1_LOAD_REG register
- *  SYSTIMER_COMP1_LOAD.
- */
-#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
-/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp1 load value
- */
-#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
-#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_COMP1_LOAD_S  0
-
-/** SYSTIMER_COMP2_LOAD_REG register
- *  SYSTIMER_COMP2_LOAD.
- */
-#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
-/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp2 load value
- */
-#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
-#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_COMP2_LOAD_S  0
-
-/** SYSTIMER_UNIT0_LOAD_REG register
- *  SYSTIMER_UNIT0_LOAD.
- */
-#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
-/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit0 load value
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
-
-/** SYSTIMER_UNIT1_LOAD_REG register
- *  SYSTIMER_UNIT1_LOAD.
- */
-#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
-/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit1 load value
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
-
-/** SYSTIMER_INT_ENA_REG register
- *  SYSTIMER_INT_ENA.
- */
-#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
-/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  interupt0 enable
- */
-#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
-#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
-#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001
-#define SYSTIMER_TARGET0_INT_ENA_S  0
-/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  interupt1 enable
- */
-#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
-#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
-#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001
-#define SYSTIMER_TARGET1_INT_ENA_S  1
-/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  interupt2 enable
- */
-#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
-#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
-#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001
-#define SYSTIMER_TARGET2_INT_ENA_S  2
-
-/** SYSTIMER_INT_RAW_REG register
- *  SYSTIMER_INT_RAW.
- */
-#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
-/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  interupt0 raw
- */
-#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
-#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
-#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001
-#define SYSTIMER_TARGET0_INT_RAW_S  0
-/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  interupt1 raw
- */
-#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
-#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
-#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001
-#define SYSTIMER_TARGET1_INT_RAW_S  1
-/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  interupt2 raw
- */
-#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
-#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
-#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001
-#define SYSTIMER_TARGET2_INT_RAW_S  2
-
-/** SYSTIMER_INT_CLR_REG register
- *  SYSTIMER_INT_CLR.
- */
-#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
-/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  interupt0 clear
- */
-#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
-#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
-#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001
-#define SYSTIMER_TARGET0_INT_CLR_S  0
-/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  interupt1 clear
- */
-#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
-#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
-#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001
-#define SYSTIMER_TARGET1_INT_CLR_S  1
-/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  interupt2 clear
- */
-#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
-#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
-#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001
-#define SYSTIMER_TARGET2_INT_CLR_S  2
-
-/** SYSTIMER_INT_ST_REG register
- *  SYSTIMER_INT_ST.
- */
-#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
-/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
- *  reg_target0_int_st
- */
-#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
-#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
-#define SYSTIMER_TARGET0_INT_ST_V  0x00000001
-#define SYSTIMER_TARGET0_INT_ST_S  0
-/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
- *  reg_target1_int_st
- */
-#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
-#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
-#define SYSTIMER_TARGET1_INT_ST_V  0x00000001
-#define SYSTIMER_TARGET1_INT_ST_S  1
-/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
- *  reg_target2_int_st
- */
-#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
-#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
-#define SYSTIMER_TARGET2_INT_ST_V  0x00000001
-#define SYSTIMER_TARGET2_INT_ST_S  2
-
-/** SYSTIMER_DATE_REG register
- *  SYSTIMER_DATE.
- */
-#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
-/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377;
- *  reg_date
- */
-#define SYSTIMER_DATE    0xFFFFFFFF
-#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
-#define SYSTIMER_DATE_V  0xFFFFFFFF
-#define SYSTIMER_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/systimer_struct.h b/components/soc/esp32c3/include/soc/systimer_struct.h
deleted file mode 100644
index 47e7b7d30c2..00000000000
--- a/components/soc/esp32c3/include/soc/systimer_struct.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Configuration Register */
-/** Type of conf register
- *  SYSTIMER_CONF.
- */
-typedef union {
-    struct {
-        /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
-         *  systimer clock force on
-         */
-        uint32_t systimer_clk_fo: 1;
-        uint32_t reserved_1: 21;
-        /** target2_work_en : R/W; bitpos: [22]; default: 0;
-         *  target2 work enable
-         */
-        uint32_t target2_work_en: 1;
-        /** target1_work_en : R/W; bitpos: [23]; default: 0;
-         *  target1 work enable
-         */
-        uint32_t target1_work_en: 1;
-        /** target0_work_en : R/W; bitpos: [24]; default: 0;
-         *  target0 work enable
-         */
-        uint32_t target0_work_en: 1;
-        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
-         *  If timer unit1 is stalled when core1 stalled
-         */
-        uint32_t timer_unit1_core1_stall_en: 1;
-        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
-         *  If timer unit1 is stalled when core0 stalled
-         */
-        uint32_t timer_unit1_core0_stall_en: 1;
-        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
-         *  If timer unit0 is stalled when core1 stalled
-         */
-        uint32_t timer_unit0_core1_stall_en: 1;
-        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
-         *  If timer unit0 is stalled when core0 stalled
-         */
-        uint32_t timer_unit0_core0_stall_en: 1;
-        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
-         *  timer unit1 work enable
-         */
-        uint32_t timer_unit1_work_en: 1;
-        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
-         *  timer unit0 work enable
-         */
-        uint32_t timer_unit0_work_en: 1;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  register file clk gating
-         */
-        uint32_t clk_en: 1;
-    };
-    uint32_t val;
-} systimer_conf_reg_t;
-
-/** Type of unit_op register
- *  SYSTIMER_UNIT_OP.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0: 29;
-        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
-         *  reg_timer_unit0_value_valid
-         */
-        uint32_t timer_unit_value_valid: 1;
-        /** timer_unit_update : WT; bitpos: [30]; default: 0;
-         *  update timer_unit0
-         */
-        uint32_t timer_unit_update: 1;
-        uint32_t reserved31: 1;
-    };
-    uint32_t val;
-} systimer_unit_op_reg_t;
-
-/** Type of unit_load register
- *  SYSTIMER_UNIT_LOAD
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
-             *  timer unit load high 32 bit
-             */
-            uint32_t timer_unit_load_hi: 20;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
-             *  timer unit load low 32 bit
-             */
-            uint32_t timer_unit_load_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_unit_load_val_reg_t;
-
-/** Type of target register
- *  SYSTIMER_TARGET.
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
-             *  timer target high 32 bit
-             */
-            uint32_t timer_target_hi: 20;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
-             *  timer target low 32 bit
-             */
-            uint32_t timer_target_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_target_val_reg_t;
-
-/** Type of target_conf register
- *  SYSTIMER_TARGET_CONF.
- */
-typedef union {
-    struct {
-        /** target_period : R/W; bitpos: [25:0]; default: 0;
-         *  target period
-         */
-        uint32_t target_period: 26;
-        uint32_t reserved_26: 4;
-        /** target_period_mode : R/W; bitpos: [30]; default: 0;
-         *  Set target to period mode
-         */
-        uint32_t target_period_mode: 1;
-        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
-         *  select which unit to compare
-         */
-        uint32_t target_timer_unit_sel: 1;
-    };
-    uint32_t val;
-} systimer_target_conf_reg_t;
-
-/** Type of unit_value_hi register
- *  SYSTIMER_UNIT_VALUE_HI.
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
-             *  timer read value high 20bit
-             */
-            uint32_t timer_unit_value_hi: 20;
-            uint32_t reserved20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
-             *  timer read value low 32bit
-             */
-            uint32_t timer_unit_value_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_unit_value_reg_t;
-
-/** Type of comp_load register
- *  SYSTIMER_COMP_LOAD.
- */
-typedef union {
-    struct {
-        /** timer_comp_load : WT; bitpos: [0]; default: 0;
-         *  timer comp load value
-         */
-        uint32_t timer_comp_load: 1;
-        uint32_t reserved1: 31;
-    };
-    uint32_t val;
-} systimer_comp_load_reg_t;
-
-/** Type of unit_load register
- *  SYSTIMER_UNIT_LOAD.
- */
-typedef union {
-    struct {
-        /** timer_unit_load : WT; bitpos: [0]; default: 0;
-         *  timer unit load value
-         */
-        uint32_t timer_unit_load: 1;
-        uint32_t reserved1: 31;
-    };
-    uint32_t val;
-} systimer_unit_load_reg_t;
-
-/** Interrupt Register */
-/** Type of int_ena register
- *  SYSTIMER_INT_ENA.
- */
-typedef union {
-    struct {
-        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  interupt0 enable
-         */
-        uint32_t target0_int_ena: 1;
-        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  interupt1 enable
-         */
-        uint32_t target1_int_ena: 1;
-        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  interupt2 enable
-         */
-        uint32_t target2_int_ena: 1;
-        uint32_t reserved3: 29;
-    };
-    uint32_t val;
-} systimer_int_ena_reg_t;
-
-/** Type of int_raw register
- *  SYSTIMER_INT_RAW.
- */
-typedef union {
-    struct {
-        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  interupt0 raw
-         */
-        uint32_t target0_int_raw: 1;
-        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  interupt1 raw
-         */
-        uint32_t target1_int_raw: 1;
-        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  interupt2 raw
-         */
-        uint32_t target2_int_raw: 1;
-        uint32_t reserved3: 29;
-    };
-    uint32_t val;
-} systimer_int_raw_reg_t;
-
-/** Type of int_clr register
- *  SYSTIMER_INT_CLR.
- */
-typedef union {
-    struct {
-        /** target0_int_clr : WT; bitpos: [0]; default: 0;
-         *  interupt0 clear
-         */
-        uint32_t target0_int_clr: 1;
-        /** target1_int_clr : WT; bitpos: [1]; default: 0;
-         *  interupt1 clear
-         */
-        uint32_t target1_int_clr: 1;
-        /** target2_int_clr : WT; bitpos: [2]; default: 0;
-         *  interupt2 clear
-         */
-        uint32_t target2_int_clr: 1;
-        uint32_t reserved3: 29;
-    };
-    uint32_t val;
-} systimer_int_clr_reg_t;
-
-/** Type of int_st register
- *  SYSTIMER_INT_ST.
- */
-typedef union {
-    struct {
-        /** target0_int_st : RO; bitpos: [0]; default: 0;
-         *  reg_target0_int_st
-         */
-        uint32_t target0_int_st: 1;
-        /** target1_int_st : RO; bitpos: [1]; default: 0;
-         *  reg_target1_int_st
-         */
-        uint32_t target1_int_st: 1;
-        /** target2_int_st : RO; bitpos: [2]; default: 0;
-         *  reg_target2_int_st
-         */
-        uint32_t target2_int_st: 1;
-        uint32_t reserved3: 29;
-    };
-    uint32_t val;
-} systimer_int_st_reg_t;
-
-
-/** Version Register */
-/** Type of date register
- *  SYSTIMER_DATE.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 33579377;
-         *  reg_date
-         */
-        uint32_t date: 32;
-    };
-    uint32_t val;
-} systimer_date_reg_t;
-
-
-typedef struct systimer_dev_t {
-    volatile systimer_conf_reg_t conf;
-    volatile systimer_unit_op_reg_t unit_op[2];
-    volatile systimer_unit_load_val_reg_t unit_load_val[2];
-    volatile systimer_target_val_reg_t target_val[3];
-    volatile systimer_target_conf_reg_t target_conf[3];
-    volatile systimer_unit_value_reg_t unit_val[2];
-    volatile systimer_comp_load_reg_t comp_load[3];
-    volatile systimer_unit_load_reg_t unit_load[2];
-    volatile systimer_int_ena_reg_t int_ena;
-    volatile systimer_int_raw_reg_t int_raw;
-    volatile systimer_int_clr_reg_t int_clr;
-    volatile systimer_int_st_reg_t int_st;
-    uint32_t reserved_074;
-    uint32_t reserved_078;
-    uint32_t reserved_07c;
-    uint32_t reserved_080;
-    uint32_t reserved_084;
-    uint32_t reserved_088;
-    uint32_t reserved_08c;
-    uint32_t reserved_090;
-    uint32_t reserved_094;
-    uint32_t reserved_098;
-    uint32_t reserved_09c;
-    uint32_t reserved_0a0;
-    uint32_t reserved_0a4;
-    uint32_t reserved_0a8;
-    uint32_t reserved_0ac;
-    uint32_t reserved_0b0;
-    uint32_t reserved_0b4;
-    uint32_t reserved_0b8;
-    uint32_t reserved_0bc;
-    uint32_t reserved_0c0;
-    uint32_t reserved_0c4;
-    uint32_t reserved_0c8;
-    uint32_t reserved_0cc;
-    uint32_t reserved_0d0;
-    uint32_t reserved_0d4;
-    uint32_t reserved_0d8;
-    uint32_t reserved_0dc;
-    uint32_t reserved_0e0;
-    uint32_t reserved_0e4;
-    uint32_t reserved_0e8;
-    uint32_t reserved_0ec;
-    uint32_t reserved_0f0;
-    uint32_t reserved_0f4;
-    uint32_t reserved_0f8;
-    volatile systimer_date_reg_t date;
-} systimer_dev_t;
-
-extern systimer_dev_t SYSTIMER;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/uart_reg.h b/components/soc/esp32c3/include/soc/uart_reg.h
deleted file mode 100644
index a0d6c72735b..00000000000
--- a/components/soc/esp32c3/include/soc/uart_reg.h
+++ /dev/null
@@ -1,1258 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UART_REG_H_
-#define _SOC_UART_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
-/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: UART $n accesses FIFO via this register.*/
-#define UART_RXFIFO_RD_BYTE  0x000000FF
-#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
-#define UART_RXFIFO_RD_BYTE_V  0xFF
-#define UART_RXFIFO_RD_BYTE_S  0
-
-#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
-/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when input rxd edge
- changes more times than what reg_active_threshold specifies in light sleeping mode.*/
-#define UART_WAKEUP_INT_RAW  (BIT(19))
-#define UART_WAKEUP_INT_RAW_M  (BIT(19))
-#define UART_WAKEUP_INT_RAW_V  0x1
-#define UART_WAKEUP_INT_RAW_S  19
-/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- the configured at_cmd char.*/
-#define UART_AT_CMD_CHAR_DET_INT_RAW  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when detects a clash
- between transmitter and receiver in rs485 mode.*/
-#define UART_RS485_CLASH_INT_RAW  (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_V  0x1
-#define UART_RS485_CLASH_INT_RAW_S  17
-/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- a data frame error from the echo of transmitter in rs485 mode.*/
-#define UART_RS485_FRM_ERR_INT_RAW  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- a parity error from the echo of transmitter in rs485 mode.*/
-#define UART_RS485_PARITY_ERR_INT_RAW  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter has
- send out all data in FIFO.*/
-#define UART_TX_DONE_INT_RAW  (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (BIT(14))
-#define UART_TX_DONE_INT_RAW_V  0x1
-#define UART_TX_DONE_INT_RAW_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter has
- kept the shortest duration after sending the  last data.*/
-#define UART_TX_BRK_IDLE_DONE_INT_RAW  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when transmitter completes
-  sending  NULL characters  after all data in Tx-FIFO are sent.*/
-#define UART_TX_BRK_DONE_INT_RAW  (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_V  0x1
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- a glitch in the middle of a start bit.*/
-#define UART_GLITCH_DET_INT_RAW  (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_V  0x1
-#define UART_GLITCH_DET_INT_RAW_S  11
-/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives
- Xoff char when uart_sw_flow_con_en is set to 1.*/
-#define UART_SW_XOFF_INT_RAW  (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
-#define UART_SW_XOFF_INT_RAW_V  0x1
-#define UART_SW_XOFF_INT_RAW_S  10
-/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver recevies
- Xon char when uart_sw_flow_con_en is set to 1.*/
-#define UART_SW_XON_INT_RAW  (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (BIT(9))
-#define UART_SW_XON_INT_RAW_V  0x1
-#define UART_SW_XON_INT_RAW_S  9
-/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver takes
- more time than rx_tout_thrhd to receive a byte.*/
-#define UART_RXFIFO_TOUT_INT_RAW  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- a 0 after the stop bit.*/
-#define UART_BRK_DET_INT_RAW  (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (BIT(7))
-#define UART_BRK_DET_INT_RAW_V  0x1
-#define UART_BRK_DET_INT_RAW_S  7
-/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- the edge change of CTSn signal.*/
-#define UART_CTS_CHG_INT_RAW  (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
-#define UART_CTS_CHG_INT_RAW_V  0x1
-#define UART_CTS_CHG_INT_RAW_S  6
-/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- the edge change of DSRn signal.*/
-#define UART_DSR_CHG_INT_RAW  (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
-#define UART_DSR_CHG_INT_RAW_V  0x1
-#define UART_DSR_CHG_INT_RAW_S  5
-/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives
- more data than the FIFO can store.*/
-#define UART_RXFIFO_OVF_INT_RAW  (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_V  0x1
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- a data frame error .*/
-#define UART_FRM_ERR_INT_RAW  (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
-#define UART_FRM_ERR_INT_RAW_V  0x1
-#define UART_FRM_ERR_INT_RAW_S  3
-/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver detects
- a parity error in the data.*/
-#define UART_PARITY_ERR_INT_RAW  (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_V  0x1
-#define UART_PARITY_ERR_INT_RAW_S  2
-/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */
-/*description: This interrupt raw bit turns to high level when the amount of
- data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
-#define UART_TXFIFO_EMPTY_INT_RAW  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This interrupt raw bit turns to high level when receiver receives
- more data than what rxfifo_full_thrhd specifies.*/
-#define UART_RXFIFO_FULL_INT_RAW  (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_V  0x1
-#define UART_RXFIFO_FULL_INT_RAW_S  0
-
-#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
-/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena
- is set to 1.*/
-#define UART_WAKEUP_INT_ST  (BIT(19))
-#define UART_WAKEUP_INT_ST_M  (BIT(19))
-#define UART_WAKEUP_INT_ST_V  0x1
-#define UART_WAKEUP_INT_ST_S  19
-/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena
- is set to 1.*/
-#define UART_AT_CMD_CHAR_DET_INT_ST  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena
- is set to 1.*/
-#define UART_RS485_CLASH_INT_ST  (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
-#define UART_RS485_CLASH_INT_ST_V  0x1
-#define UART_RS485_CLASH_INT_ST_S  17
-/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena
- is set to 1.*/
-#define UART_RS485_FRM_ERR_INT_ST  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_V  0x1
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena
- is set to 1.*/
-#define UART_RS485_PARITY_ERR_INT_ST  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
-#define UART_TX_DONE_INT_ST  (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (BIT(14))
-#define UART_TX_DONE_INT_ST_V  0x1
-#define UART_TX_DONE_INT_ST_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- is set to 1.*/
-#define UART_TX_BRK_IDLE_DONE_INT_ST  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena
- is set to 1.*/
-#define UART_TX_BRK_DONE_INT_ST  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_V  0x1
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena
- is set to 1.*/
-#define UART_GLITCH_DET_INT_ST  (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
-#define UART_GLITCH_DET_INT_ST_V  0x1
-#define UART_GLITCH_DET_INT_ST_S  11
-/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
-#define UART_SW_XOFF_INT_ST  (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (BIT(10))
-#define UART_SW_XOFF_INT_ST_V  0x1
-#define UART_SW_XOFF_INT_ST_S  10
-/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
-#define UART_SW_XON_INT_ST  (BIT(9))
-#define UART_SW_XON_INT_ST_M  (BIT(9))
-#define UART_SW_XON_INT_ST_V  0x1
-#define UART_SW_XON_INT_ST_S  9
-/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena
- is set to 1.*/
-#define UART_RXFIFO_TOUT_INT_ST  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_V  0x1
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
-#define UART_BRK_DET_INT_ST  (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (BIT(7))
-#define UART_BRK_DET_INT_ST_V  0x1
-#define UART_BRK_DET_INT_ST_S  7
-/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
-#define UART_CTS_CHG_INT_ST  (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (BIT(6))
-#define UART_CTS_CHG_INT_ST_V  0x1
-#define UART_CTS_CHG_INT_ST_S  6
-/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
-#define UART_DSR_CHG_INT_ST  (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (BIT(5))
-#define UART_DSR_CHG_INT_ST_V  0x1
-#define UART_DSR_CHG_INT_ST_S  5
-/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena
- is set to 1.*/
-#define UART_RXFIFO_OVF_INT_ST  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_V  0x1
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
-#define UART_FRM_ERR_INT_ST  (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (BIT(3))
-#define UART_FRM_ERR_INT_ST_V  0x1
-#define UART_FRM_ERR_INT_ST_S  3
-/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena
- is set to 1.*/
-#define UART_PARITY_ERR_INT_ST  (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
-#define UART_PARITY_ERR_INT_ST_V  0x1
-#define UART_PARITY_ERR_INT_ST_S  2
-/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena
- is set to 1.*/
-#define UART_TXFIFO_EMPTY_INT_ST  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena
- is set to 1.*/
-#define UART_RXFIFO_FULL_INT_ST  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_V  0x1
-#define UART_RXFIFO_FULL_INT_ST_S  0
-
-#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
-/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: This is the enable bit for uart_wakeup_int_st register.*/
-#define UART_WAKEUP_INT_ENA  (BIT(19))
-#define UART_WAKEUP_INT_ENA_M  (BIT(19))
-#define UART_WAKEUP_INT_ENA_V  0x1
-#define UART_WAKEUP_INT_ENA_S  19
-/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: This is the enable bit for at_cmd_char_det_int_st register.*/
-#define UART_AT_CMD_CHAR_DET_INT_ENA  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_clash_int_st register.*/
-#define UART_RS485_CLASH_INT_ENA  (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_V  0x1
-#define UART_RS485_CLASH_INT_ENA_S  17
-/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_parity_err_int_st register.*/
-#define UART_RS485_FRM_ERR_INT_ENA  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: This is the enable bit for rs485_parity_err_int_st register.*/
-#define UART_RS485_PARITY_ERR_INT_ENA  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_done_int_st register.*/
-#define UART_TX_DONE_INT_ENA  (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (BIT(14))
-#define UART_TX_DONE_INT_ENA_V  0x1
-#define UART_TX_DONE_INT_ENA_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/
-#define UART_TX_BRK_IDLE_DONE_INT_ENA  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: This is the enable bit for tx_brk_done_int_st register.*/
-#define UART_TX_BRK_DONE_INT_ENA  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_V  0x1
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: This is the enable bit for glitch_det_int_st register.*/
-#define UART_GLITCH_DET_INT_ENA  (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_V  0x1
-#define UART_GLITCH_DET_INT_ENA_S  11
-/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the enable bit for sw_xoff_int_st register.*/
-#define UART_SW_XOFF_INT_ENA  (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
-#define UART_SW_XOFF_INT_ENA_V  0x1
-#define UART_SW_XOFF_INT_ENA_S  10
-/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This is the enable bit for sw_xon_int_st register.*/
-#define UART_SW_XON_INT_ENA  (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (BIT(9))
-#define UART_SW_XON_INT_ENA_V  0x1
-#define UART_SW_XON_INT_ENA_S  9
-/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_tout_int_st register.*/
-#define UART_RXFIFO_TOUT_INT_ENA  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This is the enable bit for brk_det_int_st register.*/
-#define UART_BRK_DET_INT_ENA  (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (BIT(7))
-#define UART_BRK_DET_INT_ENA_V  0x1
-#define UART_BRK_DET_INT_ENA_S  7
-/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the enable bit for cts_chg_int_st register.*/
-#define UART_CTS_CHG_INT_ENA  (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
-#define UART_CTS_CHG_INT_ENA_V  0x1
-#define UART_CTS_CHG_INT_ENA_S  6
-/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This is the enable bit for dsr_chg_int_st register.*/
-#define UART_DSR_CHG_INT_ENA  (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
-#define UART_DSR_CHG_INT_ENA_V  0x1
-#define UART_DSR_CHG_INT_ENA_S  5
-/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_ovf_int_st register.*/
-#define UART_RXFIFO_OVF_INT_ENA  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_V  0x1
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: This is the enable bit for frm_err_int_st register.*/
-#define UART_FRM_ERR_INT_ENA  (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
-#define UART_FRM_ERR_INT_ENA_V  0x1
-#define UART_FRM_ERR_INT_ENA_S  3
-/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This is the enable bit for parity_err_int_st register.*/
-#define UART_PARITY_ERR_INT_ENA  (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_V  0x1
-#define UART_PARITY_ERR_INT_ENA_S  2
-/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: This is the enable bit for txfifo_empty_int_st register.*/
-#define UART_TXFIFO_EMPTY_INT_ENA  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This is the enable bit for rxfifo_full_int_st register.*/
-#define UART_RXFIFO_FULL_INT_ENA  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_V  0x1
-#define UART_RXFIFO_FULL_INT_ENA_S  0
-
-#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
-/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this bit to clear the uart_wakeup_int_raw interrupt.*/
-#define UART_WAKEUP_INT_CLR  (BIT(19))
-#define UART_WAKEUP_INT_CLR_M  (BIT(19))
-#define UART_WAKEUP_INT_CLR_V  0x1
-#define UART_WAKEUP_INT_CLR_S  19
-/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
-#define UART_AT_CMD_CHAR_DET_INT_CLR  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/
-#define UART_RS485_CLASH_INT_CLR  (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_V  0x1
-#define UART_RS485_CLASH_INT_CLR_S  17
-/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
-#define UART_RS485_FRM_ERR_INT_CLR  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
-#define UART_RS485_PARITY_ERR_INT_CLR  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_done_int_raw interrupt.*/
-#define UART_TX_DONE_INT_CLR  (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (BIT(14))
-#define UART_TX_DONE_INT_CLR_V  0x1
-#define UART_TX_DONE_INT_CLR_S  14
-/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
-#define UART_TX_BRK_IDLE_DONE_INT_CLR  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/
-#define UART_TX_BRK_DONE_INT_CLR  (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_V  0x1
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/
-#define UART_GLITCH_DET_INT_CLR  (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_V  0x1
-#define UART_GLITCH_DET_INT_CLR_S  11
-/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to clear the sw_xoff_int_raw interrupt.*/
-#define UART_SW_XOFF_INT_CLR  (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
-#define UART_SW_XOFF_INT_CLR_V  0x1
-#define UART_SW_XOFF_INT_CLR_S  10
-/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/
-#define UART_SW_XON_INT_CLR  (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (BIT(9))
-#define UART_SW_XON_INT_CLR_V  0x1
-#define UART_SW_XON_INT_CLR_S  9
-/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
-#define UART_RXFIFO_TOUT_INT_CLR  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear the brk_det_int_raw interrupt.*/
-#define UART_BRK_DET_INT_CLR  (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (BIT(7))
-#define UART_BRK_DET_INT_CLR_V  0x1
-#define UART_BRK_DET_INT_CLR_S  7
-/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/
-#define UART_CTS_CHG_INT_CLR  (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
-#define UART_CTS_CHG_INT_CLR_V  0x1
-#define UART_CTS_CHG_INT_CLR_S  6
-/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/
-#define UART_DSR_CHG_INT_CLR  (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
-#define UART_DSR_CHG_INT_CLR_V  0x1
-#define UART_DSR_CHG_INT_CLR_S  5
-/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
-#define UART_RXFIFO_OVF_INT_CLR  (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_V  0x1
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear frm_err_int_raw interrupt.*/
-#define UART_FRM_ERR_INT_CLR  (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
-#define UART_FRM_ERR_INT_CLR_V  0x1
-#define UART_FRM_ERR_INT_CLR_S  3
-/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear parity_err_int_raw interrupt.*/
-#define UART_PARITY_ERR_INT_CLR  (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_V  0x1
-#define UART_PARITY_ERR_INT_CLR_S  2
-/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/
-#define UART_TXFIFO_EMPTY_INT_CLR  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/
-#define UART_RXFIFO_FULL_INT_CLR  (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_V  0x1
-#define UART_RXFIFO_FULL_INT_CLR_S  0
-
-#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
-/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
-/*description: The decimal part of the frequency divider factor.*/
-#define UART_CLKDIV_FRAG  0x0000000F
-#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
-#define UART_CLKDIV_FRAG_V  0xF
-#define UART_CLKDIV_FRAG_S  20
-/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2B6 ; */
-/*description: The integral part of the frequency divider factor.*/
-#define UART_CLKDIV  0x00000FFF
-#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
-#define UART_CLKDIV_V  0xFFF
-#define UART_CLKDIV_S  0
-
-#define UART_RX_FILT_REG(i)          (REG_UART_BASE(i) + 0x18)
-/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enable Rx signal filter.*/
-#define UART_GLITCH_FILT_EN  (BIT(8))
-#define UART_GLITCH_FILT_EN_M  (BIT(8))
-#define UART_GLITCH_FILT_EN_V  0x1
-#define UART_GLITCH_FILT_EN_S  8
-/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */
-/*description: when input pulse width is lower than this value  the pulse is ignored.*/
-#define UART_GLITCH_FILT  0x000000FF
-#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
-#define UART_GLITCH_FILT_V  0xFF
-#define UART_GLITCH_FILT_S  0
-
-#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
-/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */
-/*description: This bit represents the  level of the internal uart txd signal.*/
-#define UART_TXD  (BIT(31))
-#define UART_TXD_M  (BIT(31))
-#define UART_TXD_V  0x1
-#define UART_TXD_S  31
-/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This bit represents the level of the internal uart rts signal.*/
-#define UART_RTSN  (BIT(30))
-#define UART_RTSN_M  (BIT(30))
-#define UART_RTSN_V  0x1
-#define UART_RTSN_S  30
-/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */
-/*description: This bit represents the level of the internal uart dtr signal.*/
-#define UART_DTRN  (BIT(29))
-#define UART_DTRN_M  (BIT(29))
-#define UART_DTRN_V  0x1
-#define UART_DTRN_S  29
-/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */
-/*description: Stores the byte number of data in Tx-FIFO.*/
-#define UART_TXFIFO_CNT  0x000003FF
-#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
-#define UART_TXFIFO_CNT_V  0x3FF
-#define UART_TXFIFO_CNT_S  16
-/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */
-/*description: This register represent the  level value of the internal uart rxd signal.*/
-#define UART_RXD  (BIT(15))
-#define UART_RXD_M  (BIT(15))
-#define UART_RXD_V  0x1
-#define UART_RXD_S  15
-/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */
-/*description: This register represent the level value of the internal uart cts signal.*/
-#define UART_CTSN  (BIT(14))
-#define UART_CTSN_M  (BIT(14))
-#define UART_CTSN_V  0x1
-#define UART_CTSN_S  14
-/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The register represent the level value of the internal uart dsr signal.*/
-#define UART_DSRN  (BIT(13))
-#define UART_DSRN_M  (BIT(13))
-#define UART_DSRN_V  0x1
-#define UART_DSRN_S  13
-/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
-/*description: Stores the byte number of valid data in Rx-FIFO.*/
-#define UART_RXFIFO_CNT  0x000003FF
-#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
-#define UART_RXFIFO_CNT_V  0x3FF
-#define UART_RXFIFO_CNT_S  0
-
-#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
-/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */
-/*description: UART memory clock gate enable signal.*/
-#define UART_MEM_CLK_EN  (BIT(28))
-#define UART_MEM_CLK_EN_M  (BIT(28))
-#define UART_MEM_CLK_EN_V  0x1
-#define UART_MEM_CLK_EN_S  28
-/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This is the enable bit for detecting baudrate.*/
-#define UART_AUTOBAUD_EN  (BIT(27))
-#define UART_AUTOBAUD_EN_M  (BIT(27))
-#define UART_AUTOBAUD_EN_V  0x1
-#define UART_AUTOBAUD_EN_S  27
-/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong.
- 1'h0: Receiver stores the data even if the  received data is wrong.*/
-#define UART_ERR_WR_MASK  (BIT(26))
-#define UART_ERR_WR_MASK_M  (BIT(26))
-#define UART_ERR_WR_MASK_V  0x1
-#define UART_ERR_WR_MASK_S  26
-/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
-/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when
- application writes registers.*/
-#define UART_CLK_EN  (BIT(25))
-#define UART_CLK_EN_M  (BIT(25))
-#define UART_CLK_EN_V  0x1
-#define UART_CLK_EN_S  25
-/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart dtr signal.*/
-#define UART_DTR_INV  (BIT(24))
-#define UART_DTR_INV_M  (BIT(24))
-#define UART_DTR_INV_V  0x1
-#define UART_DTR_INV_S  24
-/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart rts signal.*/
-#define UART_RTS_INV  (BIT(23))
-#define UART_RTS_INV_M  (BIT(23))
-#define UART_RTS_INV_V  0x1
-#define UART_RTS_INV_S  23
-/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart txd signal.*/
-#define UART_TXD_INV  (BIT(22))
-#define UART_TXD_INV_M  (BIT(22))
-#define UART_TXD_INV_V  0x1
-#define UART_TXD_INV_S  22
-/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart dsr signal.*/
-#define UART_DSR_INV  (BIT(21))
-#define UART_DSR_INV_M  (BIT(21))
-#define UART_DSR_INV_V  0x1
-#define UART_DSR_INV_S  21
-/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart cts signal.*/
-#define UART_CTS_INV  (BIT(20))
-#define UART_CTS_INV_M  (BIT(20))
-#define UART_CTS_INV_V  0x1
-#define UART_CTS_INV_S  20
-/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: Set this bit to inverse the level value of uart rxd signal.*/
-#define UART_RXD_INV  (BIT(19))
-#define UART_RXD_INV_M  (BIT(19))
-#define UART_RXD_INV_V  0x1
-#define UART_RXD_INV_S  19
-/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: Set this bit to reset the uart transmit-FIFO.*/
-#define UART_TXFIFO_RST  (BIT(18))
-#define UART_TXFIFO_RST_M  (BIT(18))
-#define UART_TXFIFO_RST_V  0x1
-#define UART_TXFIFO_RST_S  18
-/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: Set this bit to reset the uart receive-FIFO.*/
-#define UART_RXFIFO_RST  (BIT(17))
-#define UART_RXFIFO_RST_M  (BIT(17))
-#define UART_RXFIFO_RST_V  0x1
-#define UART_RXFIFO_RST_S  17
-/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: Set this bit to enable IrDA protocol.*/
-#define UART_IRDA_EN  (BIT(16))
-#define UART_IRDA_EN_M  (BIT(16))
-#define UART_IRDA_EN_V  0x1
-#define UART_IRDA_EN_S  16
-/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to enable flow control function for transmitter.*/
-#define UART_TX_FLOW_EN  (BIT(15))
-#define UART_TX_FLOW_EN_M  (BIT(15))
-#define UART_TX_FLOW_EN_V  0x1
-#define UART_TX_FLOW_EN_S  15
-/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable uart loopback test mode.*/
-#define UART_LOOPBACK  (BIT(14))
-#define UART_LOOPBACK_M  (BIT(14))
-#define UART_LOOPBACK_V  0x1
-#define UART_LOOPBACK_S  14
-/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to invert the level of IrDA receiver.*/
-#define UART_IRDA_RX_INV  (BIT(13))
-#define UART_IRDA_RX_INV_M  (BIT(13))
-#define UART_IRDA_RX_INV_V  0x1
-#define UART_IRDA_RX_INV_S  13
-/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to invert the level of  IrDA transmitter.*/
-#define UART_IRDA_TX_INV  (BIT(12))
-#define UART_IRDA_TX_INV_M  (BIT(12))
-#define UART_IRDA_TX_INV_V  0x1
-#define UART_IRDA_TX_INV_S  12
-/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit.
- 1'h0: Set IrDA transmitter's 11th bit to 0.*/
-#define UART_IRDA_WCTL  (BIT(11))
-#define UART_IRDA_WCTL_M  (BIT(11))
-#define UART_IRDA_WCTL_V  0x1
-#define UART_IRDA_WCTL_S  11
-/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: This is the start enable bit for IrDA transmitter.*/
-#define UART_IRDA_TX_EN  (BIT(10))
-#define UART_IRDA_TX_EN_M  (BIT(10))
-#define UART_IRDA_TX_EN_V  0x1
-#define UART_IRDA_TX_EN_S  10
-/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to enable IrDA loopback mode.*/
-#define UART_IRDA_DPLX  (BIT(9))
-#define UART_IRDA_DPLX_M  (BIT(9))
-#define UART_IRDA_DPLX_V  0x1
-#define UART_IRDA_DPLX_S  9
-/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enbale transmitter to  send NULL when the process
- of sending data is done.*/
-#define UART_TXD_BRK  (BIT(8))
-#define UART_TXD_BRK_M  (BIT(8))
-#define UART_TXD_BRK_V  0x1
-#define UART_TXD_BRK_S  8
-/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: This register is used to configure the software dtr signal which
- is used in software flow control.*/
-#define UART_SW_DTR  (BIT(7))
-#define UART_SW_DTR_M  (BIT(7))
-#define UART_SW_DTR_V  0x1
-#define UART_SW_DTR_S  7
-/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This register is used to configure the software rts signal which
- is used in software flow control.*/
-#define UART_SW_RTS  (BIT(6))
-#define UART_SW_RTS_M  (BIT(6))
-#define UART_SW_RTS_V  0x1
-#define UART_SW_RTS_S  6
-/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
-/*description: This register is used to set the length of  stop bit.*/
-#define UART_STOP_BIT_NUM  0x00000003
-#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
-#define UART_STOP_BIT_NUM_V  0x3
-#define UART_STOP_BIT_NUM_S  4
-/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
-/*description: This register is used to set the length of data.*/
-#define UART_BIT_NUM  0x00000003
-#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
-#define UART_BIT_NUM_V  0x3
-#define UART_BIT_NUM_S  2
-/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to enable uart parity check.*/
-#define UART_PARITY_EN  (BIT(1))
-#define UART_PARITY_EN_M  (BIT(1))
-#define UART_PARITY_EN_V  0x1
-#define UART_PARITY_EN_S  1
-/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This register is used to configure the parity check mode.*/
-#define UART_PARITY  (BIT(0))
-#define UART_PARITY_M  (BIT(0))
-#define UART_PARITY_V  0x1
-#define UART_PARITY_S  0
-
-#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
-/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: This is the enble bit for uart receiver's timeout function.*/
-#define UART_RX_TOUT_EN  (BIT(21))
-#define UART_RX_TOUT_EN_M  (BIT(21))
-#define UART_RX_TOUT_EN_V  0x1
-#define UART_RX_TOUT_EN_S  21
-/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This is the flow enable bit for UART receiver.*/
-#define UART_RX_FLOW_EN  (BIT(20))
-#define UART_RX_FLOW_EN_M  (BIT(20))
-#define UART_RX_FLOW_EN_V  0x1
-#define UART_RX_FLOW_EN_S  20
-/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
-#define UART_RX_TOUT_FLOW_DIS  (BIT(19))
-#define UART_RX_TOUT_FLOW_DIS_M  (BIT(19))
-#define UART_RX_TOUT_FLOW_DIS_V  0x1
-#define UART_RX_TOUT_FLOW_DIS_S  19
-/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: Disable UART Rx data overflow detect.*/
-#define UART_DIS_RX_DAT_OVF  (BIT(18))
-#define UART_DIS_RX_DAT_OVF_M  (BIT(18))
-#define UART_DIS_RX_DAT_OVF_V  0x1
-#define UART_DIS_RX_DAT_OVF_S  18
-/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */
-/*description: It will produce txfifo_empty_int interrupt when the data amount
- in Tx-FIFO is less than this register value.*/
-#define UART_TXFIFO_EMPTY_THRHD  0x000001FF
-#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
-#define UART_TXFIFO_EMPTY_THRHD_V  0x1FF
-#define UART_TXFIFO_EMPTY_THRHD_S  9
-/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */
-/*description: It will produce rxfifo_full_int interrupt when receiver receives
- more data than this register value.*/
-#define UART_RXFIFO_FULL_THRHD  0x000001FF
-#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
-#define UART_RXFIFO_FULL_THRHD_V  0x1FF
-#define UART_RXFIFO_FULL_THRHD_S  0
-
-#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
-/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
-/*description: This register stores the value of the minimum duration time of
- the low level pulse. It is used in baud rate-detect process.*/
-#define UART_LOWPULSE_MIN_CNT  0x00000FFF
-#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
-#define UART_LOWPULSE_MIN_CNT_V  0xFFF
-#define UART_LOWPULSE_MIN_CNT_S  0
-
-#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
-/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
-/*description: This register stores  the value of the maxinum duration time
- for the high level pulse. It is used in baud rate-detect process.*/
-#define UART_HIGHPULSE_MIN_CNT  0x00000FFF
-#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
-#define UART_HIGHPULSE_MIN_CNT_V  0xFFF
-#define UART_HIGHPULSE_MIN_CNT_S  0
-
-#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
-/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register stores the count of rxd edge change. It is used
- in baud rate-detect process.*/
-#define UART_RXD_EDGE_CNT  0x000003FF
-#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
-#define UART_RXD_EDGE_CNT_V  0x3FF
-#define UART_RXD_EDGE_CNT_S  0
-
-#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
-/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to send Xoff char. It is cleared by hardware automatically.*/
-#define UART_SEND_XOFF  (BIT(5))
-#define UART_SEND_XOFF_M  (BIT(5))
-#define UART_SEND_XOFF_V  0x1
-#define UART_SEND_XOFF_S  5
-/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to send Xon char. It is cleared by hardware automatically.*/
-#define UART_SEND_XON  (BIT(4))
-#define UART_SEND_XON_M  (BIT(4))
-#define UART_SEND_XON_V  0x1
-#define UART_SEND_XON_S  4
-/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to stop the  transmitter from sending data.*/
-#define UART_FORCE_XOFF  (BIT(3))
-#define UART_FORCE_XOFF_M  (BIT(3))
-#define UART_FORCE_XOFF_V  0x1
-#define UART_FORCE_XOFF_S  3
-/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to enable the transmitter to go on sending data.*/
-#define UART_FORCE_XON  (BIT(2))
-#define UART_FORCE_XON_M  (BIT(2))
-#define UART_FORCE_XON_V  0x1
-#define UART_FORCE_XON_S  2
-/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to remove flow control char from the received data.*/
-#define UART_XONOFF_DEL  (BIT(1))
-#define UART_XONOFF_DEL_M  (BIT(1))
-#define UART_XONOFF_DEL_V  0x1
-#define UART_XONOFF_DEL_S  1
-/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable software flow control. It is used with
- register sw_xon or sw_xoff.*/
-#define UART_SW_FLOW_CON_EN  (BIT(0))
-#define UART_SW_FLOW_CON_EN_M  (BIT(0))
-#define UART_SW_FLOW_CON_EN_V  0x1
-#define UART_SW_FLOW_CON_EN_S  0
-
-#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
-/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
-/*description: The uart is activated from light sleeping mode when the input
- rxd edge changes more times than this register value.*/
-#define UART_ACTIVE_THRESHOLD  0x000003FF
-#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
-#define UART_ACTIVE_THRESHOLD_V  0x3FF
-#define UART_ACTIVE_THRESHOLD_S  0
-
-#define UART_SWFC_CONF0_REG(i)          (REG_UART_BASE(i) + 0x3C)
-/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */
-/*description: This register stores the Xoff flow control char.*/
-#define UART_XOFF_CHAR  0x000000FF
-#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
-#define UART_XOFF_CHAR_V  0xFF
-#define UART_XOFF_CHAR_S  9
-/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */
-/*description: When the data amount in Rx-FIFO is more than this register value
- with uart_sw_flow_con_en set to 1  it will send a Xoff char.*/
-#define UART_XOFF_THRESHOLD  0x000001FF
-#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
-#define UART_XOFF_THRESHOLD_V  0x1FF
-#define UART_XOFF_THRESHOLD_S  0
-
-#define UART_SWFC_CONF1_REG(i)          (REG_UART_BASE(i) + 0x40)
-/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */
-/*description: This register stores the Xon flow control char.*/
-#define UART_XON_CHAR  0x000000FF
-#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
-#define UART_XON_CHAR_V  0xFF
-#define UART_XON_CHAR_S  9
-/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: When the data amount in Rx-FIFO is less than this register value
- with uart_sw_flow_con_en set to 1  it will send a Xon char.*/
-#define UART_XON_THRESHOLD  0x000001FF
-#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
-#define UART_XON_THRESHOLD_V  0x1FF
-#define UART_XON_THRESHOLD_S  0
-
-#define UART_TXBRK_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
-/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */
-/*description: This register is used to configure the number of 0 to be sent
- after the process of sending data is done. It is active when txd_brk is set to 1.*/
-#define UART_TX_BRK_NUM  0x000000FF
-#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
-#define UART_TX_BRK_NUM_V  0xFF
-#define UART_TX_BRK_NUM_S  0
-
-#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x48)
-/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
-/*description: This register is used to configure the duration time between transfers.*/
-#define UART_TX_IDLE_NUM  0x000003FF
-#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
-#define UART_TX_IDLE_NUM_V  0x3FF
-#define UART_TX_IDLE_NUM_S  10
-/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
-/*description: It will produce frame end signal when receiver takes more time
- to receive one byte data than this register value.*/
-#define UART_RX_IDLE_THRHD  0x000003FF
-#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
-#define UART_RX_IDLE_THRHD_V  0x3FF
-#define UART_RX_IDLE_THRHD_S  0
-
-#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x4c)
-/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
-/*description: This register is used to delay the transmitter's internal data signal.*/
-#define UART_RS485_TX_DLY_NUM  0x0000000F
-#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
-#define UART_RS485_TX_DLY_NUM_V  0xF
-#define UART_RS485_TX_DLY_NUM_S  6
-/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: This register is used to delay the receiver's internal data signal.*/
-#define UART_RS485_RX_DLY_NUM  (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
-#define UART_RS485_RX_DLY_NUM_V  0x1
-#define UART_RS485_RX_DLY_NUM_S  5
-/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/
-#define UART_RS485RXBY_TX_EN  (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (BIT(4))
-#define UART_RS485RXBY_TX_EN_V  0x1
-#define UART_RS485RXBY_TX_EN_S  4
-/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable receiver could receive data when the transmitter
- is transmitting data in rs485 mode.*/
-#define UART_RS485TX_RX_EN  (BIT(3))
-#define UART_RS485TX_RX_EN_M  (BIT(3))
-#define UART_RS485TX_RX_EN_V  0x1
-#define UART_RS485TX_RX_EN_S  3
-/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to delay the stop bit by 1 bit.*/
-#define UART_DL1_EN  (BIT(2))
-#define UART_DL1_EN_M  (BIT(2))
-#define UART_DL1_EN_V  0x1
-#define UART_DL1_EN_S  2
-/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to delay the stop bit by 1 bit.*/
-#define UART_DL0_EN  (BIT(1))
-#define UART_DL0_EN_M  (BIT(1))
-#define UART_DL0_EN_V  0x1
-#define UART_DL0_EN_S  1
-/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to choose the rs485 mode.*/
-#define UART_RS485_EN  (BIT(0))
-#define UART_RS485_EN_M  (BIT(0))
-#define UART_RS485_EN_V  0x1
-#define UART_RS485_EN_S  0
-
-#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x50)
-/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
-/*description: This register is used to configure the idle duration time before
- the first at_cmd is received by receiver.*/
-#define UART_PRE_IDLE_NUM  0x0000FFFF
-#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
-#define UART_PRE_IDLE_NUM_V  0xFFFF
-#define UART_PRE_IDLE_NUM_S  0
-
-#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x54)
-/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
-/*description: This register is used to configure the duration time between
- the last at_cmd and the next data.*/
-#define UART_POST_IDLE_NUM  0x0000FFFF
-#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
-#define UART_POST_IDLE_NUM_V  0xFFFF
-#define UART_POST_IDLE_NUM_S  0
-
-#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x58)
-/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */
-/*description: This register is used to configure the duration time between the at_cmd chars.*/
-#define UART_RX_GAP_TOUT  0x0000FFFF
-#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
-#define UART_RX_GAP_TOUT_V  0xFFFF
-#define UART_RX_GAP_TOUT_S  0
-
-#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x5c)
-/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
-/*description: This register is used to configure the num of continuous at_cmd
- chars received by receiver.*/
-#define UART_CHAR_NUM  0x000000FF
-#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
-#define UART_CHAR_NUM_V  0xFF
-#define UART_CHAR_NUM_S  8
-/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
-/*description: This register is used to configure the content of at_cmd char.*/
-#define UART_AT_CMD_CHAR  0x000000FF
-#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
-#define UART_AT_CMD_CHAR_V  0xFF
-#define UART_AT_CMD_CHAR_S  0
-
-#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x60)
-/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to force power up UART memory.*/
-#define UART_MEM_FORCE_PU  (BIT(27))
-#define UART_MEM_FORCE_PU_M  (BIT(27))
-#define UART_MEM_FORCE_PU_V  0x1
-#define UART_MEM_FORCE_PU_S  27
-/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to force power down UART memory.*/
-#define UART_MEM_FORCE_PD  (BIT(26))
-#define UART_MEM_FORCE_PD_M  (BIT(26))
-#define UART_MEM_FORCE_PD_V  0x1
-#define UART_MEM_FORCE_PD_S  26
-/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */
-/*description: This register is used to configure the threshold time that receiver
- takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
-#define UART_RX_TOUT_THRHD  0x000003FF
-#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
-#define UART_RX_TOUT_THRHD_V  0x3FF
-#define UART_RX_TOUT_THRHD_S  16
-/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
-/*description: This register is used to configure the maximum amount of data
- that can be received  when hardware flow control works.*/
-#define UART_RX_FLOW_THRHD  0x000001FF
-#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
-#define UART_RX_FLOW_THRHD_V  0x1FF
-#define UART_RX_FLOW_THRHD_S  7
-/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */
-/*description: This register is used to configure the amount of mem allocated
- for transmit-FIFO. The default number is 128 bytes.*/
-#define UART_TX_SIZE  0x00000007
-#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
-#define UART_TX_SIZE_V  0x7
-#define UART_TX_SIZE_S  4
-/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */
-/*description: This register is used to configure the amount of mem allocated
- for receive-FIFO. The default number is 128 bytes.*/
-#define UART_RX_SIZE  0x00000007
-#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
-#define UART_RX_SIZE_V  0x7
-#define UART_RX_SIZE_S  1
-
-#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
-/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
-/*description: This register stores the offset address in Tx-FIFO when Tx-FSM
- reads data via Tx-FIFO_Ctrl.*/
-#define UART_TX_RADDR  0x000003FF
-#define UART_TX_RADDR_M  ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S))
-#define UART_TX_RADDR_V  0x3FF
-#define UART_TX_RADDR_S  11
-/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: This register stores the offset address in Tx-FIFO when software
- writes Tx-FIFO via APB.*/
-#define UART_APB_TX_WADDR  0x000003FF
-#define UART_APB_TX_WADDR_M  ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S))
-#define UART_APB_TX_WADDR_V  0x3FF
-#define UART_APB_TX_WADDR_S  0
-
-#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x68)
-/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h100 ; */
-/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl
- writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
-#define UART_RX_WADDR  0x000003FF
-#define UART_RX_WADDR_M  ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
-#define UART_RX_WADDR_V  0x3FF
-#define UART_RX_WADDR_S  11
-/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */
-/*description: This register stores the offset address in RX-FIFO when software
- reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
-#define UART_APB_RX_RADDR  0x000003FF
-#define UART_APB_RX_RADDR_M  ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S))
-#define UART_APB_RX_RADDR_V  0x3FF
-#define UART_APB_RX_RADDR_S  0
-
-#define UART_FSM_STATUS_REG(i)          (REG_UART_BASE(i) + 0x6c)
-/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: This is the status register of transmitter.*/
-#define UART_ST_UTX_OUT  0x0000000F
-#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
-#define UART_ST_UTX_OUT_V  0xF
-#define UART_ST_UTX_OUT_S  4
-/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: This is the status register of receiver.*/
-#define UART_ST_URX_OUT  0x0000000F
-#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
-#define UART_ST_URX_OUT_V  0xF
-#define UART_ST_URX_OUT_S  0
-
-#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x70)
-/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
-/*description: This register stores the minimal input clock count between two
- positive edges. It is used in boudrate-detect process.*/
-#define UART_POSEDGE_MIN_CNT  0x00000FFF
-#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
-#define UART_POSEDGE_MIN_CNT_V  0xFFF
-#define UART_POSEDGE_MIN_CNT_S  0
-
-#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x74)
-/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
-/*description: This register stores the minimal input clock count between two
- negative edges. It is used in boudrate-detect process.*/
-#define UART_NEGEDGE_MIN_CNT  0x00000FFF
-#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
-#define UART_NEGEDGE_MIN_CNT_V  0xFFF
-#define UART_NEGEDGE_MIN_CNT_S  0
-
-#define UART_CLK_CONF_REG(i)          (REG_UART_BASE(i) + 0x78)
-/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit  reset UART Rx.*/
-#define UART_RX_RST_CORE  (BIT(27))
-#define UART_RX_RST_CORE_M  (BIT(27))
-#define UART_RX_RST_CORE_V  0x1
-#define UART_RX_RST_CORE_S  27
-/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit  reset UART Tx.*/
-#define UART_TX_RST_CORE  (BIT(26))
-#define UART_TX_RST_CORE_M  (BIT(26))
-#define UART_TX_RST_CORE_V  0x1
-#define UART_TX_RST_CORE_S  26
-/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Rx clock.*/
-#define UART_RX_SCLK_EN  (BIT(25))
-#define UART_RX_SCLK_EN_M  (BIT(25))
-#define UART_RX_SCLK_EN_V  0x1
-#define UART_RX_SCLK_EN_S  25
-/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Tx clock.*/
-#define UART_TX_SCLK_EN  (BIT(24))
-#define UART_TX_SCLK_EN_M  (BIT(24))
-#define UART_TX_SCLK_EN_V  0x1
-#define UART_TX_SCLK_EN_S  24
-/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Write 1 then write 0 to this bit  reset UART Tx/Rx.*/
-#define UART_RST_CORE  (BIT(23))
-#define UART_RST_CORE_M  (BIT(23))
-#define UART_RST_CORE_V  0x1
-#define UART_RST_CORE_S  23
-/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: Set this bit to enable UART Tx/Rx clock.*/
-#define UART_SCLK_EN  (BIT(22))
-#define UART_SCLK_EN_M  (BIT(22))
-#define UART_SCLK_EN_V  0x1
-#define UART_SCLK_EN_S  22
-/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */
-/*description: UART clock source select. 1: 80Mhz  2: 8Mhz  3: XTAL.*/
-#define UART_SCLK_SEL  0x00000003
-#define UART_SCLK_SEL_M  ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S))
-#define UART_SCLK_SEL_V  0x3
-#define UART_SCLK_SEL_S  20
-/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */
-/*description: The integral part of the frequency divider factor.*/
-#define UART_SCLK_DIV_NUM  0x000000FF
-#define UART_SCLK_DIV_NUM_M  ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S))
-#define UART_SCLK_DIV_NUM_V  0xFF
-#define UART_SCLK_DIV_NUM_S  12
-/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */
-/*description: The numerator of the frequency divider factor.*/
-#define UART_SCLK_DIV_A  0x0000003F
-#define UART_SCLK_DIV_A_M  ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S))
-#define UART_SCLK_DIV_A_V  0x3F
-#define UART_SCLK_DIV_A_S  6
-/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: The  denominator of the frequency divider factor.*/
-#define UART_SCLK_DIV_B  0x0000003F
-#define UART_SCLK_DIV_B_M  ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S))
-#define UART_SCLK_DIV_B_V  0x3F
-#define UART_SCLK_DIV_B_S  0
-
-#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x7c)
-/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */
-/*description: This is the version register.*/
-#define UART_DATE  0xFFFFFFFF
-#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
-#define UART_DATE_V  0xFFFFFFFF
-#define UART_DATE_S  0
-
-#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x80)
-/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Software write 1 would synchronize registers into UART Core clock
- domain and would be cleared by hardware after synchronization is done.*/
-#define UART_UPDATE  (BIT(31))
-#define UART_UPDATE_M  (BIT(31))
-#define UART_UPDATE_V  0x1
-#define UART_UPDATE_S  31
-/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: This bit used to select synchronize mode. 1: Registers are auto
- synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers  software needs to write 1 to UART_REG_UPDATE to synchronize registers.*/
-#define UART_HIGH_SPEED  (BIT(30))
-#define UART_HIGH_SPEED_M  (BIT(30))
-#define UART_HIGH_SPEED_V  0x1
-#define UART_HIGH_SPEED_S  30
-/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */
-/*description: This register is used to configure the uart_id.*/
-#define UART_ID  0x3FFFFFFF
-#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
-#define UART_ID_V  0x3FFFFFFF
-#define UART_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_UART_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/uart_struct.h b/components/soc/esp32c3/include/soc/uart_struct.h
deleted file mode 100644
index b14191f3ff0..00000000000
--- a/components/soc/esp32c3/include/soc/uart_struct.h
+++ /dev/null
@@ -1,397 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct uart_dev_s {
-    union {
-        struct {
-            uint32_t rw_byte;                 /*a*/
-        };
-        uint32_t val;
-    } ahb_fifo;
-    union {
-        struct {
-            uint32_t rxfifo_full:              1;       /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
-            uint32_t txfifo_empty:             1;       /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
-            uint32_t parity_err:               1;       /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
-            uint32_t frm_err:                  1;       /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
-            uint32_t rxfifo_ovf:               1;       /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
-            uint32_t dsr_chg:                  1;       /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
-            uint32_t cts_chg:                  1;       /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
-            uint32_t brk_det:                  1;       /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
-            uint32_t rxfifo_tout:              1;       /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
-            uint32_t sw_xon:                   1;       /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
-            uint32_t sw_xoff:                  1;       /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
-            uint32_t glitch_det:               1;       /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
-            uint32_t tx_brk_done:              1;       /*This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters  after all data in Tx-FIFO are sent.*/
-            uint32_t tx_brk_idle_done:         1;       /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.*/
-            uint32_t tx_done:                  1;       /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
-            uint32_t rs485_parity_err:         1;       /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
-            uint32_t rs485_frm_err:            1;       /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
-            uint32_t rs485_clash:              1;       /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
-            uint32_t at_cmd_char_det:          1;       /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
-            uint32_t wakeup:                   1;       /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
-            uint32_t reserved20:              12;       /*Reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rxfifo_full:             1;        /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
-            uint32_t txfifo_empty:            1;        /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
-            uint32_t parity_err:              1;        /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
-            uint32_t frm_err:                 1;        /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
-            uint32_t rxfifo_ovf:              1;        /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
-            uint32_t dsr_chg:                 1;        /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
-            uint32_t cts_chg:                 1;        /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
-            uint32_t brk_det:                 1;        /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
-            uint32_t rxfifo_tout:             1;        /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
-            uint32_t sw_xon:                  1;        /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
-            uint32_t sw_xoff:                 1;        /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
-            uint32_t glitch_det:              1;        /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
-            uint32_t tx_brk_done:             1;        /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
-            uint32_t tx_brk_idle_done:        1;        /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
-            uint32_t tx_done:                 1;        /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
-            uint32_t rs485_parity_err:        1;        /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
-            uint32_t rs485_frm_err:           1;        /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
-            uint32_t rs485_clash:             1;        /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
-            uint32_t at_cmd_char_det:         1;        /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
-            uint32_t wakeup:                  1;        /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
-            uint32_t reserved20:             12;        /*Reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t rxfifo_full:              1;       /*This is the enable bit for rxfifo_full_int_st register.*/
-            uint32_t txfifo_empty:             1;       /*This is the enable bit for txfifo_empty_int_st register.*/
-            uint32_t parity_err:               1;       /*This is the enable bit for parity_err_int_st register.*/
-            uint32_t frm_err:                  1;       /*This is the enable bit for frm_err_int_st register.*/
-            uint32_t rxfifo_ovf:               1;       /*This is the enable bit for rxfifo_ovf_int_st register.*/
-            uint32_t dsr_chg:                  1;       /*This is the enable bit for dsr_chg_int_st register.*/
-            uint32_t cts_chg:                  1;       /*This is the enable bit for cts_chg_int_st register.*/
-            uint32_t brk_det:                  1;       /*This is the enable bit for brk_det_int_st register.*/
-            uint32_t rxfifo_tout:              1;       /*This is the enable bit for rxfifo_tout_int_st register.*/
-            uint32_t sw_xon:                   1;       /*This is the enable bit for sw_xon_int_st register.*/
-            uint32_t sw_xoff:                  1;       /*This is the enable bit for sw_xoff_int_st register.*/
-            uint32_t glitch_det:               1;       /*This is the enable bit for glitch_det_int_st register.*/
-            uint32_t tx_brk_done:              1;       /*This is the enable bit for tx_brk_done_int_st register.*/
-            uint32_t tx_brk_idle_done:         1;       /*This is the enable bit for tx_brk_idle_done_int_st register.*/
-            uint32_t tx_done:                  1;       /*This is the enable bit for tx_done_int_st register.*/
-            uint32_t rs485_parity_err:         1;       /*This is the enable bit for rs485_parity_err_int_st register.*/
-            uint32_t rs485_frm_err:            1;       /*This is the enable bit for rs485_parity_err_int_st register.*/
-            uint32_t rs485_clash:              1;       /*This is the enable bit for rs485_clash_int_st register.*/
-            uint32_t at_cmd_char_det:          1;       /*This is the enable bit for at_cmd_char_det_int_st register.*/
-            uint32_t wakeup:                   1;       /*This is the enable bit for uart_wakeup_int_st register.*/
-            uint32_t reserved20:              12;       /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rxfifo_full:              1;       /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
-            uint32_t txfifo_empty:             1;       /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
-            uint32_t parity_err:               1;       /*Set this bit to clear parity_err_int_raw interrupt.*/
-            uint32_t frm_err:                  1;       /*Set this bit to clear frm_err_int_raw interrupt.*/
-            uint32_t rxfifo_ovf:               1;       /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
-            uint32_t dsr_chg:                  1;       /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
-            uint32_t cts_chg:                  1;       /*Set this bit to clear the cts_chg_int_raw interrupt.*/
-            uint32_t brk_det:                  1;       /*Set this bit to clear the brk_det_int_raw interrupt.*/
-            uint32_t rxfifo_tout:              1;       /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
-            uint32_t sw_xon:                   1;       /*Set this bit to clear the sw_xon_int_raw interrupt.*/
-            uint32_t sw_xoff:                  1;       /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
-            uint32_t glitch_det:               1;       /*Set this bit to clear the glitch_det_int_raw interrupt.*/
-            uint32_t tx_brk_done:              1;       /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
-            uint32_t tx_brk_idle_done:         1;       /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
-            uint32_t tx_done:                  1;       /*Set this bit to clear the tx_done_int_raw interrupt.*/
-            uint32_t rs485_parity_err:         1;       /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
-            uint32_t rs485_frm_err:            1;       /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
-            uint32_t rs485_clash:              1;       /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
-            uint32_t at_cmd_char_det:          1;       /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
-            uint32_t wakeup:                   1;       /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
-            uint32_t reserved20:              12;       /*Reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t div_int:    12;                    /*The integral part of the frequency divider factor.*/
-            uint32_t reserved12:  8;
-            uint32_t div_frag:    4;                    /*The decimal part of the frequency divider factor.*/
-            uint32_t reserved24:  8;                    /*Reserved*/
-        };
-        uint32_t val;
-    } clk_div;
-    union {
-        struct {
-            uint32_t glitch_filt:    8;                 /*when input pulse width is lower than this value  the pulse is ignored.*/
-            uint32_t glitch_filt_en: 1;                 /*Set this bit to enable Rx signal filter.*/
-            uint32_t reserved9:     23;
-        };
-        uint32_t val;
-    } rx_filt;
-    union {
-        struct {
-            uint32_t rxfifo_cnt:10;                     /*Stores the byte number of valid data in Rx-FIFO.*/
-            uint32_t reserved10: 3;
-            uint32_t dsrn:       1;                     /*The register represent the level value of the internal uart dsr signal.*/
-            uint32_t ctsn:       1;                     /*This register represent the level value of the internal uart cts signal.*/
-            uint32_t rxd:        1;                     /*This register represent the  level value of the internal uart rxd signal.*/
-            uint32_t txfifo_cnt:10;                     /*Stores the byte number of data in Tx-FIFO.*/
-            uint32_t reserved26: 3;                     /*Reserved*/
-            uint32_t dtrn:       1;                     /*This bit represents the level of the internal uart dtr signal.*/
-            uint32_t rtsn:       1;                     /*This bit represents the level of the internal uart rts signal.*/
-            uint32_t txd:        1;                     /*This bit represents the  level of the internal uart txd signal.*/
-        };
-        uint32_t val;
-    } status;
-    union {
-        struct {
-            uint32_t parity:       1;                   /*This register is used to configure the parity check mode.*/
-            uint32_t parity_en:    1;                   /*Set this bit to enable uart parity check.*/
-            uint32_t bit_num:      2;                   /*This register is used to set the length of data.*/
-            uint32_t stop_bit_num: 2;                   /*This register is used to set the length of  stop bit.*/
-            uint32_t sw_rts:       1;                   /*This register is used to configure the software rts signal which is used in software flow control.*/
-            uint32_t sw_dtr:       1;                   /*This register is used to configure the software dtr signal which is used in software flow control.*/
-            uint32_t txd_brk:      1;                   /*Set this bit to enbale transmitter to  send NULL when the process of sending data is done.*/
-            uint32_t irda_dplx:    1;                   /*Set this bit to enable IrDA loopback mode.*/
-            uint32_t irda_tx_en:   1;                   /*This is the start enable bit for IrDA transmitter.*/
-            uint32_t irda_wctl:    1;                   /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
-            uint32_t irda_tx_inv:  1;                   /*Set this bit to invert the level of  IrDA transmitter.*/
-            uint32_t irda_rx_inv:  1;                   /*Set this bit to invert the level of IrDA receiver.*/
-            uint32_t loopback:     1;                   /*Set this bit to enable uart loopback test mode.*/
-            uint32_t tx_flow_en:   1;                   /*Set this bit to enable flow control function for transmitter.*/
-            uint32_t irda_en:      1;                   /*Set this bit to enable IrDA protocol.*/
-            uint32_t rxfifo_rst:   1;                   /*Set this bit to reset the uart receive-FIFO.*/
-            uint32_t txfifo_rst:   1;                   /*Set this bit to reset the uart transmit-FIFO.*/
-            uint32_t rxd_inv:      1;                   /*Set this bit to inverse the level value of uart rxd signal.*/
-            uint32_t cts_inv:      1;                   /*Set this bit to inverse the level value of uart cts signal.*/
-            uint32_t dsr_inv:      1;                   /*Set this bit to inverse the level value of uart dsr signal.*/
-            uint32_t txd_inv:      1;                   /*Set this bit to inverse the level value of uart txd signal.*/
-            uint32_t rts_inv:      1;                   /*Set this bit to inverse the level value of uart rts signal.*/
-            uint32_t dtr_inv:      1;                   /*Set this bit to inverse the level value of uart dtr signal.*/
-            uint32_t clk_en:       1;                   /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
-            uint32_t err_wr_mask:  1;                   /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.*/
-            uint32_t autobaud_en:  1;                   /*This is the enable bit for detecting baudrate.*/
-            uint32_t mem_clk_en:   1;                   /*UART memory clock gate enable signal.*/
-            uint32_t reserved29:   3;
-        };
-        uint32_t val;
-    } conf0;
-    union {
-        struct {
-            uint32_t rxfifo_full_thrhd:  9;             /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
-            uint32_t txfifo_empty_thrhd: 9;             /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
-            uint32_t dis_rx_dat_ovf:     1;             /*Disable UART Rx data overflow detect.*/
-            uint32_t rx_tout_flow_dis:   1;             /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
-            uint32_t rx_flow_en:         1;             /*This is the flow enable bit for UART receiver.*/
-            uint32_t rx_tout_en:         1;             /*This is the enble bit for uart receiver's timeout function.*/
-            uint32_t reserved22:        10;
-        };
-        uint32_t val;
-    } conf1;
-    union {
-        struct {
-            uint32_t min_cnt:         12;               /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
-            uint32_t reserved12:      20;               /*Reserved*/
-        };
-        uint32_t val;
-    } lowpulse;
-    union {
-        struct {
-            uint32_t min_cnt:          12;              /*This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
-            uint32_t reserved12:       20;              /*Reserved*/
-        };
-        uint32_t val;
-    } highpulse;
-    union {
-        struct {
-            uint32_t edge_cnt:    10;                   /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
-            uint32_t reserved10:  22;                   /*Reserved*/
-        };
-        uint32_t val;
-    } rxd_cnt;
-    union {
-        struct {
-            uint32_t sw_flow_con_en: 1;                 /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
-            uint32_t xonoff_del:     1;                 /*Set this bit to remove flow control char from the received data.*/
-            uint32_t force_xon:      1;                 /*Set this bit to enable the transmitter to go on sending data.*/
-            uint32_t force_xoff:     1;                 /*Set this bit to stop the  transmitter from sending data.*/
-            uint32_t send_xon:       1;                 /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
-            uint32_t send_xoff:      1;                 /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
-            uint32_t reserved6:     26;                 /*Reserved*/
-        };
-        uint32_t val;
-    } flow_conf;
-    union {
-        struct {
-            uint32_t active_threshold:10;               /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
-            uint32_t reserved10:      22;               /*Reserved*/
-        };
-        uint32_t val;
-    } sleep_conf;
-    union {
-        struct {
-            uint32_t xoff_threshold: 9;                 /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1  it will send a Xoff char.*/
-            uint32_t xoff_char:      8;                 /*This register stores the Xoff flow control char.*/
-            uint32_t reserved17:    15;                 /*Reserved*/
-        };
-        uint32_t val;
-    } swfc_conf0;
-    union {
-        struct {
-            uint32_t xon_threshold: 9;                  /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1  it will send a Xon char.*/
-            uint32_t xon_char:      8;                  /*This register stores the Xon flow control char.*/
-            uint32_t reserved17:   15;                  /*Reserved*/
-        };
-        uint32_t val;
-    } swfc_conf1;
-    union {
-        struct {
-            uint32_t tx_brk_num: 8;                     /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
-            uint32_t reserved8: 24;
-        };
-        uint32_t val;
-    } txbrk_conf;
-    union {
-        struct {
-            uint32_t rx_idle_thrhd:10;                  /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
-            uint32_t tx_idle_num:  10;                  /*This register is used to configure the duration time between transfers.*/
-            uint32_t reserved20:   12;                  /*Reserved*/
-        };
-        uint32_t val;
-    } idle_conf;
-    union {
-        struct {
-            uint32_t en:               1;               /*Set this bit to choose the rs485 mode.*/
-            uint32_t dl0_en:           1;               /*Set this bit to delay the stop bit by 1 bit.*/
-            uint32_t dl1_en:           1;               /*Set this bit to delay the stop bit by 1 bit.*/
-            uint32_t tx_rx_en:         1;               /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.*/
-            uint32_t rx_busy_tx_en:    1;               /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/
-            uint32_t rx_dly_num:       1;               /*This register is used to delay the receiver's internal data signal.*/
-            uint32_t tx_dly_num:       4;               /*This register is used to delay the transmitter's internal data signal.*/
-            uint32_t reserved10:      22;               /*Reserved*/
-        };
-        uint32_t val;
-    } rs485_conf;
-    union {
-        struct {
-            uint32_t pre_idle_num:16;                   /*This register is used to configure the idle duration time before the first at_cmd is received by receiver.*/
-            uint32_t reserved16:  16;                   /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_precnt;
-    union {
-        struct {
-            uint32_t post_idle_num:16;                  /*This register is used to configure the duration time between the last at_cmd and the next data.*/
-            uint32_t reserved16:   16;                  /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_postcnt;
-    union {
-        struct {
-            uint32_t rx_gap_tout:16;                    /*This register is used to configure the duration time between the at_cmd chars.*/
-            uint32_t reserved16: 16;                    /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_gaptout;
-    union {
-        struct {
-            uint32_t data:        8;                    /*This register is used to configure the content of at_cmd char.*/
-            uint32_t char_num:    8;                    /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
-            uint32_t reserved16: 16;                    /*Reserved*/
-        };
-        uint32_t val;
-    } at_cmd_char;
-    union {
-        struct {
-            uint32_t reserved0:     1;
-            uint32_t rx_size:       3;                  /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
-            uint32_t tx_size:       3;                  /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
-            uint32_t rx_flow_thrhd: 9;                  /*This register is used to configure the maximum amount of data that can be received  when hardware flow control works.*/
-            uint32_t rx_tout_thrhd:10;                  /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
-            uint32_t force_pd:      1;                  /*Set this bit to force power down UART memory.*/
-            uint32_t force_pu:      1;                  /*Set this bit to force power up UART memory.*/
-            uint32_t reserved28:    4;
-        };
-        uint32_t val;
-    } mem_conf;
-    union {
-        struct {
-            uint32_t apb_tx_waddr:10;                   /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
-            uint32_t reserved10:   1;                   /*Reserved*/
-            uint32_t tx_raddr:    10;                   /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
-            uint32_t reserved21:  11;                   /*Reserved*/
-        };
-        uint32_t val;
-    } mem_tx_status;
-    union {
-        struct {
-            uint32_t apb_rx_raddr:10;                   /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
-            uint32_t reserved10:   1;                   /*Reserved*/
-            uint32_t rx_waddr:    10;                   /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
-            uint32_t reserved21:  11;                   /*Reserved*/
-        };
-        uint32_t val;
-    } mem_rx_status;
-    union {
-        struct {
-            uint32_t st_urx_out: 4;                     /*This is the status register of receiver.*/
-            uint32_t st_utx_out: 4;                     /*This is the status register of transmitter.*/
-            uint32_t reserved8: 24;                     /*Reserved*/
-        };
-        uint32_t val;
-    } fsm_status;
-    union {
-        struct {
-            uint32_t min_cnt:        12;                /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
-            uint32_t reserved12:     20;                /*Reserved*/
-        };
-        uint32_t val;
-    } pospulse;
-    union {
-        struct {
-            uint32_t min_cnt:        12;                /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
-            uint32_t reserved12:     20;                /*Reserved*/
-        };
-        uint32_t val;
-    } negpulse;
-    union {
-        struct {
-            uint32_t sclk_div_b:   6;                   /*The  denominator of the frequency divider factor.*/
-            uint32_t sclk_div_a:   6;                   /*The numerator of the frequency divider factor.*/
-            uint32_t sclk_div_num: 8;                   /*The integral part of the frequency divider factor.*/
-            uint32_t sclk_sel:     2;                   /*UART clock source select. 1: 80Mhz  2: 8Mhz  3: XTAL.*/
-            uint32_t sclk_en:      1;                   /*Set this bit to enable UART Tx/Rx clock.*/
-            uint32_t rst_core:     1;                   /*Write 1 then write 0 to this bit  reset UART Tx/Rx.*/
-            uint32_t tx_sclk_en:   1;                   /*Set this bit to enable UART Tx clock.*/
-            uint32_t rx_sclk_en:   1;                   /*Set this bit to enable UART Rx clock.*/
-            uint32_t tx_rst_core:  1;                   /*Write 1 then write 0 to this bit  reset UART Tx.*/
-            uint32_t rx_rst_core:  1;                   /*Write 1 then write 0 to this bit  reset UART Rx.*/
-            uint32_t reserved28:   4;
-        };
-        uint32_t val;
-    } clk_conf;
-    uint32_t date;                                      /*UART Version register*/
-    union {
-        struct {
-            uint32_t id                            :    30;  /*This register is used to configure the uart_id.*/
-            uint32_t high_speed                    :    1;  /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
-            uint32_t update                        :    1;  /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
-        };
-        uint32_t val;
-    } id;
-} uart_dev_t;
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/uhci_reg.h b/components/soc/esp32c3/include/soc/uhci_reg.h
deleted file mode 100644
index 3a41dedb800..00000000000
--- a/components/soc/esp32c3/include/soc/uhci_reg.h
+++ /dev/null
@@ -1,748 +0,0 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UHCI_REG_H_
-#define _SOC_UHCI_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-#define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
-/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: If this bit is set to 1  UHCI will end payload receive process
- when NULL frame is received by UART.*/
-#define UHCI_UART_RX_BRK_EOF_EN  (BIT(12))
-#define UHCI_UART_RX_BRK_EOF_EN_M  (BIT(12))
-#define UHCI_UART_RX_BRK_EOF_EN_V  0x1
-#define UHCI_UART_RX_BRK_EOF_EN_S  12
-/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 1'b1: Force clock on for register. 1'b0: Support clock only when
- application writes registers.*/
-#define UHCI_CLK_EN  (BIT(11))
-#define UHCI_CLK_EN_M  (BIT(11))
-#define UHCI_CLK_EN_V  0x1
-#define UHCI_CLK_EN_S  11
-/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: Set this bit to enable data integrity checking by appending a
- 16 bit CCITT-CRC to end of the payload.*/
-#define UHCI_ENCODE_CRC_EN  (BIT(10))
-#define UHCI_ENCODE_CRC_EN_M  (BIT(10))
-#define UHCI_ENCODE_CRC_EN_V  0x1
-#define UHCI_ENCODE_CRC_EN_S  10
-/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: If this bit is set to 1  UHCI decoder receiving payload data
- is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0  UHCI decoder receiving payload data is end when 0xc0 is received.*/
-#define UHCI_LEN_EOF_EN  (BIT(9))
-#define UHCI_LEN_EOF_EN_M  (BIT(9))
-#define UHCI_LEN_EOF_EN_V  0x1
-#define UHCI_LEN_EOF_EN_S  9
-/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: If this bit is set to 1  UHCI will end the payload receiving
- process when UART has been in idle state.*/
-#define UHCI_UART_IDLE_EOF_EN  (BIT(8))
-#define UHCI_UART_IDLE_EOF_EN_M  (BIT(8))
-#define UHCI_UART_IDLE_EOF_EN_V  0x1
-#define UHCI_UART_IDLE_EOF_EN_S  8
-/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: Set this bit to enable UHCI to receive the 16 bit CRC.*/
-#define UHCI_CRC_REC_EN  (BIT(7))
-#define UHCI_CRC_REC_EN_M  (BIT(7))
-#define UHCI_CRC_REC_EN_V  0x1
-#define UHCI_CRC_REC_EN_S  7
-/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: Set this bit to encode the data packet with a formatting header.*/
-#define UHCI_HEAD_EN  (BIT(6))
-#define UHCI_HEAD_EN_M  (BIT(6))
-#define UHCI_HEAD_EN_V  0x1
-#define UHCI_HEAD_EN_S  6
-/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: Set this bit to separate the data frame using a special char.*/
-#define UHCI_SEPER_EN  (BIT(5))
-#define UHCI_SEPER_EN_M  (BIT(5))
-#define UHCI_SEPER_EN_V  0x1
-#define UHCI_SEPER_EN_S  5
-/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to link up HCI and UART1.*/
-#define UHCI_UART1_CE  (BIT(3))
-#define UHCI_UART1_CE_M  (BIT(3))
-#define UHCI_UART1_CE_V  0x1
-#define UHCI_UART1_CE_S  3
-/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: Set this bit to link up HCI and UART0.*/
-#define UHCI_UART0_CE  (BIT(2))
-#define UHCI_UART0_CE_M  (BIT(2))
-#define UHCI_UART0_CE_V  0x1
-#define UHCI_UART0_CE_S  2
-/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Write 1  then write 0 to this bit to reset encode state machine.*/
-#define UHCI_RX_RST  (BIT(1))
-#define UHCI_RX_RST_M  (BIT(1))
-#define UHCI_RX_RST_V  0x1
-#define UHCI_RX_RST_S  1
-/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Write 1  then write 0 to this bit to reset decode state machine.*/
-#define UHCI_TX_RST  (BIT(0))
-#define UHCI_TX_RST_M  (BIT(0))
-#define UHCI_TX_RST_V  0x1
-#define UHCI_TX_RST_S  0
-
-#define UHCI_INT_RAW_REG(i)          (REG_UHCI_BASE(i) + 0x4)
-/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Soft control int raw bit.*/
-#define UHCI_APP_CTRL1_INT_RAW  (BIT(8))
-#define UHCI_APP_CTRL1_INT_RAW_M  (BIT(8))
-#define UHCI_APP_CTRL1_INT_RAW_V  0x1
-#define UHCI_APP_CTRL1_INT_RAW_S  8
-/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Soft control int raw bit.*/
-#define UHCI_APP_CTRL0_INT_RAW  (BIT(7))
-#define UHCI_APP_CTRL0_INT_RAW_M  (BIT(7))
-#define UHCI_APP_CTRL0_INT_RAW_V  0x1
-#define UHCI_APP_CTRL0_INT_RAW_S  7
-/* UHCI_OUTLINK_EOF_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: This is the interrupt raw bit. Triggered when there are some
- errors in EOF in the*/
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S  6
-/* UHCI_SEND_A_Q_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SEND_A_Q_INT_RAW  (BIT(5))
-#define UHCI_SEND_A_Q_INT_RAW_M  (BIT(5))
-#define UHCI_SEND_A_Q_INT_RAW_V  0x1
-#define UHCI_SEND_A_Q_INT_RAW_S  5
-/* UHCI_SEND_S_Q_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SEND_S_Q_INT_RAW  (BIT(4))
-#define UHCI_SEND_S_Q_INT_RAW_M  (BIT(4))
-#define UHCI_SEND_S_Q_INT_RAW_V  0x1
-#define UHCI_SEND_S_Q_INT_RAW_S  4
-/* UHCI_TX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_HUNG_INT_RAW  (BIT(3))
-#define UHCI_TX_HUNG_INT_RAW_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_RAW_V  0x1
-#define UHCI_TX_HUNG_INT_RAW_S  3
-/* UHCI_RX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_HUNG_INT_RAW  (BIT(2))
-#define UHCI_RX_HUNG_INT_RAW_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_RAW_V  0x1
-#define UHCI_RX_HUNG_INT_RAW_S  2
-/* UHCI_TX_START_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_START_INT_RAW  (BIT(1))
-#define UHCI_TX_START_INT_RAW_M  (BIT(1))
-#define UHCI_TX_START_INT_RAW_V  0x1
-#define UHCI_TX_START_INT_RAW_S  1
-/* UHCI_RX_START_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_START_INT_RAW  (BIT(0))
-#define UHCI_RX_START_INT_RAW_M  (BIT(0))
-#define UHCI_RX_START_INT_RAW_V  0x1
-#define UHCI_RX_START_INT_RAW_S  0
-
-#define UHCI_INT_ST_REG(i)          (REG_UHCI_BASE(i) + 0x8)
-/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_APP_CTRL1_INT_ST  (BIT(8))
-#define UHCI_APP_CTRL1_INT_ST_M  (BIT(8))
-#define UHCI_APP_CTRL1_INT_ST_V  0x1
-#define UHCI_APP_CTRL1_INT_ST_S  8
-/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_APP_CTRL0_INT_ST  (BIT(7))
-#define UHCI_APP_CTRL0_INT_ST_M  (BIT(7))
-#define UHCI_APP_CTRL0_INT_ST_V  0x1
-#define UHCI_APP_CTRL0_INT_ST_S  7
-/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_OUTLINK_EOF_ERR_INT_ST  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
-/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SEND_A_Q_INT_ST  (BIT(5))
-#define UHCI_SEND_A_Q_INT_ST_M  (BIT(5))
-#define UHCI_SEND_A_Q_INT_ST_V  0x1
-#define UHCI_SEND_A_Q_INT_ST_S  5
-/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SEND_S_Q_INT_ST  (BIT(4))
-#define UHCI_SEND_S_Q_INT_ST_M  (BIT(4))
-#define UHCI_SEND_S_Q_INT_ST_V  0x1
-#define UHCI_SEND_S_Q_INT_ST_S  4
-/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_HUNG_INT_ST  (BIT(3))
-#define UHCI_TX_HUNG_INT_ST_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_ST_V  0x1
-#define UHCI_TX_HUNG_INT_ST_S  3
-/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_HUNG_INT_ST  (BIT(2))
-#define UHCI_RX_HUNG_INT_ST_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_ST_V  0x1
-#define UHCI_RX_HUNG_INT_ST_S  2
-/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_START_INT_ST  (BIT(1))
-#define UHCI_TX_START_INT_ST_M  (BIT(1))
-#define UHCI_TX_START_INT_ST_V  0x1
-#define UHCI_TX_START_INT_ST_S  1
-/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_START_INT_ST  (BIT(0))
-#define UHCI_RX_START_INT_ST_M  (BIT(0))
-#define UHCI_RX_START_INT_ST_V  0x1
-#define UHCI_RX_START_INT_ST_S  0
-
-#define UHCI_INT_ENA_REG(i)          (REG_UHCI_BASE(i) + 0xC)
-/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_APP_CTRL1_INT_ENA  (BIT(8))
-#define UHCI_APP_CTRL1_INT_ENA_M  (BIT(8))
-#define UHCI_APP_CTRL1_INT_ENA_V  0x1
-#define UHCI_APP_CTRL1_INT_ENA_S  8
-/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_APP_CTRL0_INT_ENA  (BIT(7))
-#define UHCI_APP_CTRL0_INT_ENA_M  (BIT(7))
-#define UHCI_APP_CTRL0_INT_ENA_V  0x1
-#define UHCI_APP_CTRL0_INT_ENA_S  7
-/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
-/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SEND_A_Q_INT_ENA  (BIT(5))
-#define UHCI_SEND_A_Q_INT_ENA_M  (BIT(5))
-#define UHCI_SEND_A_Q_INT_ENA_V  0x1
-#define UHCI_SEND_A_Q_INT_ENA_S  5
-/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SEND_S_Q_INT_ENA  (BIT(4))
-#define UHCI_SEND_S_Q_INT_ENA_M  (BIT(4))
-#define UHCI_SEND_S_Q_INT_ENA_V  0x1
-#define UHCI_SEND_S_Q_INT_ENA_S  4
-/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_HUNG_INT_ENA  (BIT(3))
-#define UHCI_TX_HUNG_INT_ENA_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_ENA_V  0x1
-#define UHCI_TX_HUNG_INT_ENA_S  3
-/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_HUNG_INT_ENA  (BIT(2))
-#define UHCI_RX_HUNG_INT_ENA_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_ENA_V  0x1
-#define UHCI_RX_HUNG_INT_ENA_S  2
-/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_START_INT_ENA  (BIT(1))
-#define UHCI_TX_START_INT_ENA_M  (BIT(1))
-#define UHCI_TX_START_INT_ENA_V  0x1
-#define UHCI_TX_START_INT_ENA_S  1
-/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_START_INT_ENA  (BIT(0))
-#define UHCI_RX_START_INT_ENA_M  (BIT(0))
-#define UHCI_RX_START_INT_ENA_V  0x1
-#define UHCI_RX_START_INT_ENA_S  0
-
-#define UHCI_INT_CLR_REG(i)          (REG_UHCI_BASE(i) + 0x10)
-/* UHCI_APP_CTRL1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_APP_CTRL1_INT_CLR  (BIT(8))
-#define UHCI_APP_CTRL1_INT_CLR_M  (BIT(8))
-#define UHCI_APP_CTRL1_INT_CLR_V  0x1
-#define UHCI_APP_CTRL1_INT_CLR_S  8
-/* UHCI_APP_CTRL0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_APP_CTRL0_INT_CLR  (BIT(7))
-#define UHCI_APP_CTRL0_INT_CLR_M  (BIT(7))
-#define UHCI_APP_CTRL0_INT_CLR_V  0x1
-#define UHCI_APP_CTRL0_INT_CLR_S  7
-/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
-/* UHCI_SEND_A_Q_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SEND_A_Q_INT_CLR  (BIT(5))
-#define UHCI_SEND_A_Q_INT_CLR_M  (BIT(5))
-#define UHCI_SEND_A_Q_INT_CLR_V  0x1
-#define UHCI_SEND_A_Q_INT_CLR_S  5
-/* UHCI_SEND_S_Q_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SEND_S_Q_INT_CLR  (BIT(4))
-#define UHCI_SEND_S_Q_INT_CLR_M  (BIT(4))
-#define UHCI_SEND_S_Q_INT_CLR_V  0x1
-#define UHCI_SEND_S_Q_INT_CLR_S  4
-/* UHCI_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_HUNG_INT_CLR  (BIT(3))
-#define UHCI_TX_HUNG_INT_CLR_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_CLR_V  0x1
-#define UHCI_TX_HUNG_INT_CLR_S  3
-/* UHCI_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_HUNG_INT_CLR  (BIT(2))
-#define UHCI_RX_HUNG_INT_CLR_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_CLR_V  0x1
-#define UHCI_RX_HUNG_INT_CLR_S  2
-/* UHCI_TX_START_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_START_INT_CLR  (BIT(1))
-#define UHCI_TX_START_INT_CLR_M  (BIT(1))
-#define UHCI_TX_START_INT_CLR_V  0x1
-#define UHCI_TX_START_INT_CLR_S  1
-/* UHCI_RX_START_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_START_INT_CLR  (BIT(0))
-#define UHCI_RX_START_INT_CLR_M  (BIT(0))
-#define UHCI_RX_START_INT_CLR_V  0x1
-#define UHCI_RX_START_INT_CLR_S  0
-
-#define UHCI_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x14)
-/* UHCI_SW_START : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SW_START  (BIT(8))
-#define UHCI_SW_START_M  (BIT(8))
-#define UHCI_SW_START_V  0x1
-#define UHCI_SW_START_S  8
-/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_WAIT_SW_START  (BIT(7))
-#define UHCI_WAIT_SW_START_M  (BIT(7))
-#define UHCI_WAIT_SW_START_V  0x1
-#define UHCI_WAIT_SW_START_S  7
-/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_TX_ACK_NUM_RE  (BIT(5))
-#define UHCI_TX_ACK_NUM_RE_M  (BIT(5))
-#define UHCI_TX_ACK_NUM_RE_V  0x1
-#define UHCI_TX_ACK_NUM_RE_S  5
-/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_TX_CHECK_SUM_RE  (BIT(4))
-#define UHCI_TX_CHECK_SUM_RE_M  (BIT(4))
-#define UHCI_TX_CHECK_SUM_RE_V  0x1
-#define UHCI_TX_CHECK_SUM_RE_S  4
-/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SAVE_HEAD  (BIT(3))
-#define UHCI_SAVE_HEAD_M  (BIT(3))
-#define UHCI_SAVE_HEAD_V  0x1
-#define UHCI_SAVE_HEAD_S  3
-/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_CRC_DISABLE  (BIT(2))
-#define UHCI_CRC_DISABLE_M  (BIT(2))
-#define UHCI_CRC_DISABLE_V  0x1
-#define UHCI_CRC_DISABLE_S  2
-/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_CHECK_SEQ_EN  (BIT(1))
-#define UHCI_CHECK_SEQ_EN_M  (BIT(1))
-#define UHCI_CHECK_SEQ_EN_V  0x1
-#define UHCI_CHECK_SEQ_EN_S  1
-/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_CHECK_SUM_EN  (BIT(0))
-#define UHCI_CHECK_SUM_EN_M  (BIT(0))
-#define UHCI_CHECK_SUM_EN_V  0x1
-#define UHCI_CHECK_SUM_EN_S  0
-
-#define UHCI_STATE0_REG(i)          (REG_UHCI_BASE(i) + 0x18)
-/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: a*/
-#define UHCI_DECODE_STATE  0x00000007
-#define UHCI_DECODE_STATE_M  ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
-#define UHCI_DECODE_STATE_V  0x7
-#define UHCI_DECODE_STATE_S  3
-/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: a*/
-#define UHCI_RX_ERR_CAUSE  0x00000007
-#define UHCI_RX_ERR_CAUSE_M  ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
-#define UHCI_RX_ERR_CAUSE_V  0x7
-#define UHCI_RX_ERR_CAUSE_S  0
-
-#define UHCI_STATE1_REG(i)          (REG_UHCI_BASE(i) + 0x1C)
-/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: a*/
-#define UHCI_ENCODE_STATE  0x00000007
-#define UHCI_ENCODE_STATE_M  ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
-#define UHCI_ENCODE_STATE_V  0x7
-#define UHCI_ENCODE_STATE_S  0
-
-#define UHCI_ESCAPE_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x20)
-/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_13_ESC_EN  (BIT(7))
-#define UHCI_RX_13_ESC_EN_M  (BIT(7))
-#define UHCI_RX_13_ESC_EN_V  0x1
-#define UHCI_RX_13_ESC_EN_S  7
-/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_RX_11_ESC_EN  (BIT(6))
-#define UHCI_RX_11_ESC_EN_M  (BIT(6))
-#define UHCI_RX_11_ESC_EN_V  0x1
-#define UHCI_RX_11_ESC_EN_S  6
-/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_RX_DB_ESC_EN  (BIT(5))
-#define UHCI_RX_DB_ESC_EN_M  (BIT(5))
-#define UHCI_RX_DB_ESC_EN_V  0x1
-#define UHCI_RX_DB_ESC_EN_S  5
-/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_RX_C0_ESC_EN  (BIT(4))
-#define UHCI_RX_C0_ESC_EN_M  (BIT(4))
-#define UHCI_RX_C0_ESC_EN_V  0x1
-#define UHCI_RX_C0_ESC_EN_S  4
-/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_13_ESC_EN  (BIT(3))
-#define UHCI_TX_13_ESC_EN_M  (BIT(3))
-#define UHCI_TX_13_ESC_EN_V  0x1
-#define UHCI_TX_13_ESC_EN_S  3
-/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_TX_11_ESC_EN  (BIT(2))
-#define UHCI_TX_11_ESC_EN_M  (BIT(2))
-#define UHCI_TX_11_ESC_EN_V  0x1
-#define UHCI_TX_11_ESC_EN_S  2
-/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_TX_DB_ESC_EN  (BIT(1))
-#define UHCI_TX_DB_ESC_EN_M  (BIT(1))
-#define UHCI_TX_DB_ESC_EN_V  0x1
-#define UHCI_TX_DB_ESC_EN_S  1
-/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_TX_C0_ESC_EN  (BIT(0))
-#define UHCI_TX_C0_ESC_EN_M  (BIT(0))
-#define UHCI_TX_C0_ESC_EN_V  0x1
-#define UHCI_TX_C0_ESC_EN_S  0
-
-#define UHCI_HUNG_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x24)
-/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_RXFIFO_TIMEOUT_ENA  (BIT(23))
-#define UHCI_RXFIFO_TIMEOUT_ENA_M  (BIT(23))
-#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x1
-#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
-/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
-/*description: a*/
-#define UHCI_RXFIFO_TIMEOUT_SHIFT  0x00000007
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x7
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
-/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
-/*description: a*/
-#define UHCI_RXFIFO_TIMEOUT  0x000000FF
-#define UHCI_RXFIFO_TIMEOUT_M  ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
-#define UHCI_RXFIFO_TIMEOUT_V  0xFF
-#define UHCI_RXFIFO_TIMEOUT_S  12
-/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_TXFIFO_TIMEOUT_ENA  (BIT(11))
-#define UHCI_TXFIFO_TIMEOUT_ENA_M  (BIT(11))
-#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x1
-#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
-/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
-/*description: a*/
-#define UHCI_TXFIFO_TIMEOUT_SHIFT  0x00000007
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x7
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
-/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
-/*description: a*/
-#define UHCI_TXFIFO_TIMEOUT  0x000000FF
-#define UHCI_TXFIFO_TIMEOUT_M  ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
-#define UHCI_TXFIFO_TIMEOUT_V  0xFF
-#define UHCI_TXFIFO_TIMEOUT_S  0
-
-#define UHCI_ACK_NUM_REG(i)          (REG_UHCI_BASE(i) + 0x28)
-/* UHCI_ACK_NUM_LOAD : WT ;bitpos:[3] ;default: 1'b1 ; */
-/*description: a*/
-#define UHCI_ACK_NUM_LOAD  (BIT(3))
-#define UHCI_ACK_NUM_LOAD_M  (BIT(3))
-#define UHCI_ACK_NUM_LOAD_V  0x1
-#define UHCI_ACK_NUM_LOAD_S  3
-/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: */
-#define UHCI_ACK_NUM  0x00000007
-#define UHCI_ACK_NUM_M  ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S))
-#define UHCI_ACK_NUM_V  0x7
-#define UHCI_ACK_NUM_S  0
-
-#define UHCI_RX_HEAD_REG(i)          (REG_UHCI_BASE(i) + 0x2C)
-/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_RX_HEAD  0xFFFFFFFF
-#define UHCI_RX_HEAD_M  ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
-#define UHCI_RX_HEAD_V  0xFFFFFFFF
-#define UHCI_RX_HEAD_S  0
-
-#define UHCI_QUICK_SENT_REG(i)          (REG_UHCI_BASE(i) + 0x30)
-/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_ALWAYS_SEND_EN  (BIT(7))
-#define UHCI_ALWAYS_SEND_EN_M  (BIT(7))
-#define UHCI_ALWAYS_SEND_EN_V  0x1
-#define UHCI_ALWAYS_SEND_EN_S  7
-/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: a*/
-#define UHCI_ALWAYS_SEND_NUM  0x00000007
-#define UHCI_ALWAYS_SEND_NUM_M  ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
-#define UHCI_ALWAYS_SEND_NUM_V  0x7
-#define UHCI_ALWAYS_SEND_NUM_S  4
-/* UHCI_SINGLE_SEND_EN : R/W/SC ;bitpos:[3] ;default: 1'b0 ; */
-/*description: a*/
-#define UHCI_SINGLE_SEND_EN  (BIT(3))
-#define UHCI_SINGLE_SEND_EN_M  (BIT(3))
-#define UHCI_SINGLE_SEND_EN_V  0x1
-#define UHCI_SINGLE_SEND_EN_S  3
-/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: a*/
-#define UHCI_SINGLE_SEND_NUM  0x00000007
-#define UHCI_SINGLE_SEND_NUM_M  ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
-#define UHCI_SINGLE_SEND_NUM_V  0x7
-#define UHCI_SINGLE_SEND_NUM_S  0
-
-#define UHCI_Q0_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x34)
-/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q0_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD0_M  ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
-#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD0_S  0
-
-#define UHCI_Q0_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x38)
-/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q0_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD1_M  ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
-#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD1_S  0
-
-#define UHCI_Q1_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x3C)
-/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q1_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD0_M  ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
-#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD0_S  0
-
-#define UHCI_Q1_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x40)
-/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q1_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD1_M  ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
-#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD1_S  0
-
-#define UHCI_Q2_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x44)
-/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q2_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD0_M  ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
-#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD0_S  0
-
-#define UHCI_Q2_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x48)
-/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q2_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD1_M  ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
-#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD1_S  0
-
-#define UHCI_Q3_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x4C)
-/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q3_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD0_M  ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
-#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD0_S  0
-
-#define UHCI_Q3_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x50)
-/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q3_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD1_M  ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
-#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD1_S  0
-
-#define UHCI_Q4_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x54)
-/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q4_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD0_M  ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
-#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD0_S  0
-
-#define UHCI_Q4_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x58)
-/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q4_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD1_M  ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
-#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD1_S  0
-
-#define UHCI_Q5_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x5C)
-/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q5_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD0_M  ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
-#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD0_S  0
-
-#define UHCI_Q5_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x60)
-/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q5_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD1_M  ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
-#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD1_S  0
-
-#define UHCI_Q6_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x64)
-/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q6_WORD0  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD0_M  ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
-#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD0_S  0
-
-#define UHCI_Q6_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x68)
-/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: a*/
-#define UHCI_SEND_Q6_WORD1  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD1_M  ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
-#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD1_S  0
-
-#define UHCI_ESC_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x6C)
-/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
-/*description: a*/
-#define UHCI_SEPER_ESC_CHAR1  0x000000FF
-#define UHCI_SEPER_ESC_CHAR1_M  ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
-#define UHCI_SEPER_ESC_CHAR1_V  0xFF
-#define UHCI_SEPER_ESC_CHAR1_S  16
-/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: a*/
-#define UHCI_SEPER_ESC_CHAR0  0x000000FF
-#define UHCI_SEPER_ESC_CHAR0_M  ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
-#define UHCI_SEPER_ESC_CHAR0_V  0xFF
-#define UHCI_SEPER_ESC_CHAR0_S  8
-/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
-/*description: a*/
-#define UHCI_SEPER_CHAR  0x000000FF
-#define UHCI_SEPER_CHAR_M  ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
-#define UHCI_SEPER_CHAR_V  0xFF
-#define UHCI_SEPER_CHAR_S  0
-
-#define UHCI_ESC_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x70)
-/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
-/*description: a*/
-#define UHCI_ESC_SEQ0_CHAR1  0x000000FF
-#define UHCI_ESC_SEQ0_CHAR1_M  ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
-#define UHCI_ESC_SEQ0_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ0_CHAR1_S  16
-/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: a*/
-#define UHCI_ESC_SEQ0_CHAR0  0x000000FF
-#define UHCI_ESC_SEQ0_CHAR0_M  ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
-#define UHCI_ESC_SEQ0_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ0_CHAR0_S  8
-/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
-/*description: a*/
-#define UHCI_ESC_SEQ0  0x000000FF
-#define UHCI_ESC_SEQ0_M  ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
-#define UHCI_ESC_SEQ0_V  0xFF
-#define UHCI_ESC_SEQ0_S  0
-
-#define UHCI_ESC_CONF2_REG(i)          (REG_UHCI_BASE(i) + 0x74)
-/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
-/*description: a*/
-#define UHCI_ESC_SEQ1_CHAR1  0x000000FF
-#define UHCI_ESC_SEQ1_CHAR1_M  ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
-#define UHCI_ESC_SEQ1_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ1_CHAR1_S  16
-/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: a*/
-#define UHCI_ESC_SEQ1_CHAR0  0x000000FF
-#define UHCI_ESC_SEQ1_CHAR0_M  ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
-#define UHCI_ESC_SEQ1_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ1_CHAR0_S  8
-/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
-/*description: a*/
-#define UHCI_ESC_SEQ1  0x000000FF
-#define UHCI_ESC_SEQ1_M  ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
-#define UHCI_ESC_SEQ1_V  0xFF
-#define UHCI_ESC_SEQ1_S  0
-
-#define UHCI_ESC_CONF3_REG(i)          (REG_UHCI_BASE(i) + 0x78)
-/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
-/*description: a*/
-#define UHCI_ESC_SEQ2_CHAR1  0x000000FF
-#define UHCI_ESC_SEQ2_CHAR1_M  ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
-#define UHCI_ESC_SEQ2_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ2_CHAR1_S  16
-/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: a*/
-#define UHCI_ESC_SEQ2_CHAR0  0x000000FF
-#define UHCI_ESC_SEQ2_CHAR0_M  ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
-#define UHCI_ESC_SEQ2_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ2_CHAR0_S  8
-/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
-/*description: a*/
-#define UHCI_ESC_SEQ2  0x000000FF
-#define UHCI_ESC_SEQ2_M  ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
-#define UHCI_ESC_SEQ2_V  0xFF
-#define UHCI_ESC_SEQ2_S  0
-
-#define UHCI_PKT_THRES_REG(i)          (REG_UHCI_BASE(i) + 0x7C)
-/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
-/*description: a*/
-#define UHCI_PKT_THRS  0x00001FFF
-#define UHCI_PKT_THRS_M  ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
-#define UHCI_PKT_THRS_V  0x1FFF
-#define UHCI_PKT_THRS_S  0
-
-#define UHCI_DATE_REG(i)          (REG_UHCI_BASE(i) + 0x80)
-/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007170 ; */
-/*description: a*/
-#define UHCI_DATE  0xFFFFFFFF
-#define UHCI_DATE_M  ((UHCI_DATE_V)<<(UHCI_DATE_S))
-#define UHCI_DATE_V  0xFFFFFFFF
-#define UHCI_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_UHCI_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h
deleted file mode 100644
index f4cf387fe6c..00000000000
--- a/components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h
+++ /dev/null
@@ -1,993 +0,0 @@
-
-/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
- *  SPDX-License-Identifier: Apache-2.0
- */
-
-
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/** Configuration Registers */
-
-/** USB_SERIAL_JTAG_EP1_REG register
- *  USB_SERIAL_JTAG_EP1_REG.
- */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
- * Write and read byte data to/from UART Tx/Rx FIFO through this field.
- * When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set  then user can write
- * data (up to 64 bytes) into UART Tx FIFO. When
- * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check
- * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to
- * know how many data is received, then read that amount of data from UART
- * Rx
- * FIFO.
- */
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FF
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FF
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-/** USB_SERIAL_JTAG_CONF0_REG register
- *  USB_SERIAL_JTAG_CONF0_REG.
- */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
- * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
- * PHY
- */
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
- * Enable software control USB D+ D-
- * exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
- * USB D+ D-
- * exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0;
- * Control single-end input high threshold. 1.76V to 2V, step
- * 80mV
- */
-#define USB_SERIAL_JTAG_VREFL    0x00000003
-#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
-#define USB_SERIAL_JTAG_VREFL_V  0x00000003
-#define USB_SERIAL_JTAG_VREFL_S  3
-/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0;
- * Control single-end input low threshold. 0.8V to 1.04V, step
- * 80mV
- */
-#define USB_SERIAL_JTAG_VREFH    0x00000003
-#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
-#define USB_SERIAL_JTAG_VREFH_V  0x00000003
-#define USB_SERIAL_JTAG_VREFH_S  5
-/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
- * Enable software control input
- * threshold
- */
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
- * Enable software control USB D+ D- pullup
- * pulldown
- */
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
- * Control USB D+ pull
- * up.
- */
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
- * Control USB D+ pull
- * down.
- */
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
- * Control USB D- pull
- * up.
- */
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
- * Control USB D- pull
- * down.
- */
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
- * Control pull up
- * value.
- */
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
- * Enable USB pad
- * function.
- */
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-
-/** USB_SERIAL_JTAG_TEST_REG register
- *  USB_SERIAL_JTAG_TEST_REG.
- */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
-/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- * Enable test of the USB
- * pad
- */
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- * USB pad oen in
- * test
- */
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- * USB D+ tx value in
- * test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- * USB D- tx value in
- * test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- *  USB_SERIAL_JTAG_MISC_CONF_REG.
- */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
- * 1'h1: Force clock on for register. 1'h0: Support clock only when
- * application writes
- * registers.
- */
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
-#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- *  USB_SERIAL_JTAG_MEM_CONF_REG.
- */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
- * 1: power down usb
- * memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- * 1: Force clock on for usb
- * memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-
-
-/** Status Registers */
-
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- *  USB_SERIAL_JTAG_EP1_CONF_REG.
- */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
- * Set this bit to indicate writing byte data to UART Tx FIFO is done.
- * This bit then stays 0 until data in UART Tx FIFO is read by the USB
- * Host.
- */
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
-#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
- * 1'b1: Indicate UART Tx FIFO is not full and data can be written into
- * in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the
- * data is sent to the USB
- * Host.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
- * 1'b1: Indicate there is data in UART Rx
- * FIFO.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- *  USB_SERIAL_JTAG_JFIFO_ST_REG.
- */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
- * JTAG in fifo
- * counter.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- * 1: JTAG in fifo is
- * empty.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
- * 1: JTAG in fifo is
- * full.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0;
- * JTAT out fifo
- * counter.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
- * 1: JTAG out fifo is
- * empty.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
- * 1: JTAG out fifo is
- * full.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
- * Write 1 to reset JTAG in
- * fifo.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
- * Write 1 to reset JTAG out
- * fifo.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- *  USB_SERIAL_JTAG_FRAM_NUM_REG.
- */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
- * Frame index of received SOF
- * frame.
- */
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FF
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FF
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- *  USB_SERIAL_JTAG_IN_EP0_ST_REG.
- */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
- * State of IN Endpoint
- * 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
- * Write data address of IN endpoint
- * 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
- * Read data address of IN endpoint
- * 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- *  USB_SERIAL_JTAG_IN_EP1_ST_REG.
- */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
-/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
- * State of IN Endpoint
- * 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
- * Write data address of IN endpoint
- * 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
- * Read data address of IN endpoint
- * 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- *  USB_SERIAL_JTAG_IN_EP2_ST_REG.
- */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
- * State of IN Endpoint
- * 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
- * Write data address of IN endpoint
- * 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
- * Read data address of IN endpoint
- * 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- *  USB_SERIAL_JTAG_IN_EP3_ST_REG.
- */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
- * State of IN Endpoint
- * 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0;
- * Write data address of IN endpoint
- * 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0;
- * Read data address of IN endpoint
- * 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- *  USB_SERIAL_JTAG_OUT_EP0_ST_REG.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
- * State of OUT Endpoint
- * 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
- * Write data address of OUT endpoint 0. When
- * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are
- * USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT
- * EP0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
- * Read data address of OUT endpoint
- * 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- *  USB_SERIAL_JTAG_OUT_EP1_ST_REG.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
-/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
- * State of OUT Endpoint
- * 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
- * Write data address of OUT endpoint 1. When
- * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are
- * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT
- * EP1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
- * Read data address of OUT endpoint
- * 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0;
- * Data count in OUT endpoint 1 when one packet is
- * received.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- *  USB_SERIAL_JTAG_OUT_EP2_ST_REG.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
- * State of OUT Endpoint
- * 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
- * Write data address of OUT endpoint 2. When
- * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are
- * USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT
- * EP2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
- * Read data address of OUT endpoint
- * 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-
-
-/** Interrupt Registers */
-
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- *  USB_SERIAL_JTAG_INT_RAW_REG.
- */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- * The raw interrupt bit turns to high level when a flush command is
- * received for IN endpoint 2 of
- * JTAG.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- * The raw interrupt bit turns to high level when a SOF frame is
- * received.
- */
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- * The raw interrupt bit turns to high level when the Serial Port OUT
- * Endpoint received one
- * packet.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
- * The raw interrupt bit turns to high level when the Serial Port IN
- * Endpoint is
- * empty.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- * The raw interrupt bit turns to high level when a PID error is
- * detected.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- * The raw interrupt bit turns to high level when a CRC5 error is
- * detected.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- * The raw interrupt bit turns to high level when a CRC16 error is
- * detected.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- * The raw interrupt bit turns to high level when a bit stuffing error is
- * detected.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- * The raw interrupt bit turns to high level when an IN token for IN
- * endpoint 1 is
- * received.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- * The raw interrupt bit turns to high level when a USB bus reset is
- * detected.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- * The raw interrupt bit turns to high level when OUT endpoint 1 received
- * packet with zero
- * payload.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- * The raw interrupt bit turns to high level when OUT endpoint 2 received
- * packet with zero
- * payload.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-
-/** USB_SERIAL_JTAG_INT_ST_REG register
- *  USB_SERIAL_JTAG_INT_ST_REG.
- */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
-/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
- * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
- * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
- * The raw interrupt status bit for the
- * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
- * The raw interrupt status bit for the
- * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
- * The raw interrupt status bit for the
- * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
- * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
- * The raw interrupt status bit for the
- * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
- * The raw interrupt status bit for the
- * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- *  USB_SERIAL_JTAG_INT_ENA_REG.
- */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
- * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
- * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
- * The interrupt enable bit for the
- * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
- * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
- * The interrupt enable bit for the
- * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
- * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
- * The interrupt enable bit for the
- * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
- * The interrupt enable bit for the
- * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-
-/** USB_SERIAL_JTAG_INT_CLR_REG register
- *  USB_SERIAL_JTAG_INT_CLR_REG.
- */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
- * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
- * interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-
-
-/** Version Registers */
-
-/** USB_SERIAL_JTAG_DATE_REG register
- *  USB_SERIAL_JTAG_DATE_REG.
- */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
- * register
- * version.
- */
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFF
-#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFF
-#define USB_SERIAL_JTAG_DATE_S  0
-
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h
deleted file mode 100644
index c1cfced04bb..00000000000
--- a/components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h
+++ /dev/null
@@ -1,262 +0,0 @@
-// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
-#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-typedef volatile struct usb_serial_jtag_dev_s {
-    union {
-        struct {
-            uint32_t rdwr_byte                     :    32;  /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set  then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
-        };
-        uint32_t val;
-    } ep1;
-    union {
-        struct {
-            uint32_t wr_done                       :    1;  /*Set this bit to indicate writing byte data to UART Tx FIFO is done.  This bit then stays 0 until data in UART Tx FIFO is read by the USB Host.*/
-            uint32_t serial_in_ep_data_free        :    1;  /*1'b1: Indicate UART Tx FIFO is not full and data can be written into in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the data is sent to the USB Host.*/
-            uint32_t serial_out_ep_data_avail      :    1;  /*1'b1: Indicate there is data in UART Rx FIFO.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } ep1_conf;
-    union {
-        struct {
-            uint32_t jtag_in_flush_int_raw         :    1;  /*The raw interrupt bit turns to high level when a flush command is received for IN endpoint 2 of JTAG.*/
-            uint32_t sof_int_raw                   :    1;  /*The raw interrupt bit turns to high level when a SOF frame is received.*/
-            uint32_t serial_out_recv_pkt_int_raw   :    1;  /*The raw interrupt bit turns to high level when the Serial Port OUT Endpoint received one packet.*/
-            uint32_t serial_in_empty_int_raw       :    1;  /*The raw interrupt bit turns to high level when the Serial Port IN Endpoint is empty.*/
-            uint32_t pid_err_int_raw               :    1;  /*The raw interrupt bit turns to high level when a PID error is detected.*/
-            uint32_t crc5_err_int_raw              :    1;  /*The raw interrupt bit turns to high level when a CRC5 error is detected.*/
-            uint32_t crc16_err_int_raw             :    1;  /*The raw interrupt bit turns to high level when a CRC16 error is detected.*/
-            uint32_t stuff_err_int_raw             :    1;  /*The raw interrupt bit turns to high level when a bit stuffing error is detected.*/
-            uint32_t in_token_rec_in_ep1_int_raw   :    1;  /*The raw interrupt bit turns to high level when an IN token for IN endpoint 1 is received.*/
-            uint32_t usb_bus_reset_int_raw         :    1;  /*The raw interrupt bit turns to high level when a USB bus reset is detected.*/
-            uint32_t out_ep1_zero_payload_int_raw  :    1;  /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero payload.*/
-            uint32_t out_ep2_zero_payload_int_raw  :    1;  /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero payload.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t jtag_in_flush_int_st          :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
-            uint32_t sof_int_st                    :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
-            uint32_t serial_out_recv_pkt_int_st    :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
-            uint32_t serial_in_empty_int_st        :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
-            uint32_t pid_err_int_st                :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
-            uint32_t crc5_err_int_st               :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
-            uint32_t crc16_err_int_st              :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
-            uint32_t stuff_err_int_st              :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
-            uint32_t in_token_rec_in_ep1_int_st    :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
-            uint32_t usb_bus_reset_int_st          :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
-            uint32_t out_ep1_zero_payload_int_st   :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t out_ep2_zero_payload_int_st   :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t jtag_in_flush_int_ena         :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
-            uint32_t sof_int_ena                   :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
-            uint32_t serial_out_recv_pkt_int_ena   :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
-            uint32_t serial_in_empty_int_ena       :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
-            uint32_t pid_err_int_ena               :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
-            uint32_t crc5_err_int_ena              :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
-            uint32_t crc16_err_int_ena             :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
-            uint32_t stuff_err_int_ena             :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
-            uint32_t in_token_rec_in_ep1_int_ena   :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
-            uint32_t usb_bus_reset_int_ena         :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
-            uint32_t out_ep1_zero_payload_int_ena  :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t out_ep2_zero_payload_int_ena  :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t jtag_in_flush_int_clr         :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
-            uint32_t sof_int_clr                   :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.*/
-            uint32_t serial_out_recv_pkt_int_clr   :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
-            uint32_t serial_in_empty_int_clr       :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
-            uint32_t pid_err_int_clr               :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
-            uint32_t crc5_err_int_clr              :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
-            uint32_t crc16_err_int_clr             :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
-            uint32_t stuff_err_int_clr             :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
-            uint32_t in_token_rec_in_ep1_int_clr   :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.*/
-            uint32_t usb_bus_reset_int_clr         :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
-            uint32_t out_ep1_zero_payload_int_clr  :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t out_ep2_zero_payload_int_clr  :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t phy_sel                       :    1;  /*Select internal/external PHY. 1’b0: internal PHY, 1’b1: external PHY*/
-            uint32_t exchg_pins_override           :    1;  /*Enable software control USB D+ D- exchange*/
-            uint32_t exchg_pins                    :    1;  /*USB D+ D- exchange*/
-            uint32_t vrefh                         :    2;  /*Control single-end input high threshold. 1.76V to 2V, step 80mV */
-            uint32_t vrefl                         :    2;  /*Control single-end input low threshold. 0.8V to 1.04V, step 80mV*/
-            uint32_t vref_override                 :    1;  /*Enable software control input  threshold*/
-            uint32_t pad_pull_override             :    1;  /*Enable software control USB D+ D- pullup pulldown*/
-            uint32_t dp_pullup                     :    1;  /*Control USB D+ pull up.*/
-            uint32_t dp_pulldown                   :    1;  /*Control USB D+ pull down.*/
-            uint32_t dm_pullup                     :    1;  /*Control USB D- pull up.*/
-            uint32_t dm_pulldown                   :    1;  /*Control USB D- pull down.*/
-            uint32_t pullup_value                  :    1;  /*Control pull up value.*/
-            uint32_t usb_pad_enable                :    1;  /*Enable USB pad function.*/
-            uint32_t reserved15                    :    17;
-        };
-        uint32_t val;
-    } conf0;
-    union {
-        struct {
-            uint32_t test_enable                   :    1;  /*Enable test of the USB pad*/
-            uint32_t test_usb_oe                   :    1;  /*USB pad oen in test*/
-            uint32_t test_tx_dp                    :    1;  /*USB D+ tx value in test*/
-            uint32_t test_tx_dm                    :    1;  /*USB D- tx value in test*/
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } test;
-    union {
-        struct {
-            uint32_t in_fifo_cnt                   :    2;  /*JTAG in fifo counter.*/
-            uint32_t in_fifo_empty                 :    1;  /*1: JTAG in fifo is empty.*/
-            uint32_t in_fifo_full                  :    1;  /*1: JTAG in fifo is full.*/
-            uint32_t out_fifo_cnt                  :    2;  /*JTAT out fifo counter.*/
-            uint32_t out_fifo_empty                :    1;  /*1: JTAG out fifo is empty.*/
-            uint32_t out_fifo_full                 :    1;  /*1: JTAG out fifo is full.*/
-            uint32_t in_fifo_reset                 :    1;  /*Write 1 to reset JTAG in fifo.*/
-            uint32_t out_fifo_reset                :    1;  /*Write 1 to reset JTAG out fifo.*/
-            uint32_t reserved10                    :    22;
-        };
-        uint32_t val;
-    } jfifo_st;
-    union {
-        struct {
-            uint32_t sof_frame_index               :    11;  /*Frame index of received SOF frame.*/
-            uint32_t reserved11                    :    21;
-        };
-        uint32_t val;
-    } fram_num;
-    union {
-        struct {
-            uint32_t in_ep0_state                  :    2;  /*State of IN Endpoint 0.*/
-            uint32_t in_ep0_wr_addr                :    7;  /*Write data address of IN endpoint 0.*/
-            uint32_t in_ep0_rd_addr                :    7;  /*Read data address of IN endpoint 0.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } in_ep0_st;
-    union {
-        struct {
-            uint32_t in_ep1_state                  :    2;  /*State of IN Endpoint 1.*/
-            uint32_t in_ep1_wr_addr                :    7;  /*Write data address of IN endpoint 1.*/
-            uint32_t in_ep1_rd_addr                :    7;  /*Read data address of IN endpoint 1.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } in_ep1_st;
-    union {
-        struct {
-            uint32_t in_ep2_state                  :    2;  /*State of IN Endpoint 2.*/
-            uint32_t in_ep2_wr_addr                :    7;  /*Write data address of IN endpoint 2.*/
-            uint32_t in_ep2_rd_addr                :    7;  /*Read data address of IN endpoint 2.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } in_ep2_st;
-    union {
-        struct {
-            uint32_t in_ep3_state                  :    2;  /*State of IN Endpoint 3.*/
-            uint32_t in_ep3_wr_addr                :    7;  /*Write data address of IN endpoint 3.*/
-            uint32_t in_ep3_rd_addr                :    7;  /*Read data address of IN endpoint 3.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } in_ep3_st;
-    union {
-        struct {
-            uint32_t out_ep0_state                 :    2;  /*State of OUT Endpoint 0.*/
-            uint32_t out_ep0_wr_addr               :    7;  /*Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */
-            uint32_t out_ep0_rd_addr               :    7;  /*Read data address of OUT endpoint 0.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } out_ep0_st;
-    union {
-        struct {
-            uint32_t out_ep1_state                 :    2;  /*State of OUT Endpoint 1.*/
-            uint32_t out_ep1_wr_addr               :    7;  /*Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
-            uint32_t out_ep1_rd_addr               :    7;  /*Read data address of OUT endpoint 1.*/
-            uint32_t out_ep1_rec_data_cnt          :    7;  /*Data count in OUT endpoint 1 when one packet is received.*/
-            uint32_t reserved23                    :    9;  /*reserved*/
-        };
-        uint32_t val;
-    } out_ep1_st;
-    union {
-        struct {
-            uint32_t out_ep2_state                 :    2;  /*State of OUT Endpoint 2.*/
-            uint32_t out_ep2_wr_addr               :    7;  /*Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
-            uint32_t out_ep2_rd_addr               :    7;  /*Read data address of OUT endpoint 2.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } out_ep2_st;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;  /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } misc_conf;
-    union {
-        struct {
-            uint32_t usb_mem_pd                    :    1;  /*1: power down usb memory.*/
-            uint32_t usb_mem_clk_en                :    1;  /*1: Force clock on for usb memory.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } mem_conf;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t date;
-} usb_serial_jtag_dev_t;
-extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */
diff --git a/components/soc/esp32c3/include/soc/xts_aes_reg.h b/components/soc/esp32c3/include/soc/xts_aes_reg.h
deleted file mode 100644
index 9845d0b0582..00000000000
--- a/components/soc/esp32c3/include/soc/xts_aes_reg.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** XTS_AES_PLAIN_MEM register
- *  The memory that stores plaintext
- */
-#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
-#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
-
-/** XTS_AES_LINESIZE_REG register
- *  XTS-AES line-size register
- */
-#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
-/** XTS_AES_LINESIZE : R/W; bitpos: [0]; default: 0;
- *  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
- */
-#define XTS_AES_LINESIZE    (BIT(0))
-#define XTS_AES_LINESIZE_M  (XTS_AES_LINESIZE_V << XTS_AES_LINESIZE_S)
-#define XTS_AES_LINESIZE_V  0x00000001U
-#define XTS_AES_LINESIZE_S  0
-
-/** XTS_AES_DESTINATION_REG register
- *  XTS-AES destination register
- */
-#define XTS_AES_DESTINATION_REG (DR_REG_XTS_AES_BASE + 0x44)
-/** XTS_AES_DESTINATION : R/W; bitpos: [0]; default: 0;
- *  This bit stores the destination. 0: flash(default). 1: reserved.
- */
-#define XTS_AES_DESTINATION    (BIT(0))
-#define XTS_AES_DESTINATION_M  (XTS_AES_DESTINATION_V << XTS_AES_DESTINATION_S)
-#define XTS_AES_DESTINATION_V  0x00000001U
-#define XTS_AES_DESTINATION_S  0
-
-/** XTS_AES_PHYSICAL_ADDRESS_REG register
- *  XTS-AES physical address register
- */
-#define XTS_AES_PHYSICAL_ADDRESS_REG (DR_REG_XTS_AES_BASE + 0x48)
-/** XTS_AES_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0;
- *  Those bits stores the physical address. If linesize is 16-byte, the physical
- *  address should be aligned of 16 bytes. If linesize is 32-byte, the physical address
- *  should be aligned of 32 bytes.
- */
-#define XTS_AES_PHYSICAL_ADDRESS    0x3FFFFFFFU
-#define XTS_AES_PHYSICAL_ADDRESS_M  (XTS_AES_PHYSICAL_ADDRESS_V << XTS_AES_PHYSICAL_ADDRESS_S)
-#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFFFU
-#define XTS_AES_PHYSICAL_ADDRESS_S  0
-
-/** XTS_AES_TRIGGER_REG register
- *  XTS-AES trigger register
- */
-#define XTS_AES_TRIGGER_REG (DR_REG_XTS_AES_BASE + 0x4c)
-/** XTS_AES_TRIGGER : WT; bitpos: [0]; default: 0;
- *  Set this bit to start manual encryption calculation
- */
-#define XTS_AES_TRIGGER    (BIT(0))
-#define XTS_AES_TRIGGER_M  (XTS_AES_TRIGGER_V << XTS_AES_TRIGGER_S)
-#define XTS_AES_TRIGGER_V  0x00000001U
-#define XTS_AES_TRIGGER_S  0
-
-/** XTS_AES_RELEASE_REG register
- *  XTS-AES release register
- */
-#define XTS_AES_RELEASE_REG (DR_REG_XTS_AES_BASE + 0x50)
-/** XTS_AES_RELEASE : WT; bitpos: [0]; default: 0;
- *  Set this bit to release the manual encrypted result, after that the result will be
- *  visible to spi
- */
-#define XTS_AES_RELEASE    (BIT(0))
-#define XTS_AES_RELEASE_M  (XTS_AES_RELEASE_V << XTS_AES_RELEASE_S)
-#define XTS_AES_RELEASE_V  0x00000001U
-#define XTS_AES_RELEASE_S  0
-
-/** XTS_AES_DESTROY_REG register
- *  XTS-AES destroy register
- */
-#define XTS_AES_DESTROY_REG (DR_REG_XTS_AES_BASE + 0x54)
-/** XTS_AES_DESTROY : WT; bitpos: [0]; default: 0;
- *  Set this bit to destroy XTS-AES result.
- */
-#define XTS_AES_DESTROY    (BIT(0))
-#define XTS_AES_DESTROY_M  (XTS_AES_DESTROY_V << XTS_AES_DESTROY_S)
-#define XTS_AES_DESTROY_V  0x00000001U
-#define XTS_AES_DESTROY_S  0
-
-/** XTS_AES_STATE_REG register
- *  XTS-AES status register
- */
-#define XTS_AES_STATE_REG (DR_REG_XTS_AES_BASE + 0x58)
-/** XTS_AES_STATE : RO; bitpos: [1:0]; default: 0;
- *  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that
- *  XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means
- *  the encrypted result is generated but not visible to mspi. USE means that the
- *  encrypted result is visible to mspi.
- */
-#define XTS_AES_STATE    0x00000003U
-#define XTS_AES_STATE_M  (XTS_AES_STATE_V << XTS_AES_STATE_S)
-#define XTS_AES_STATE_V  0x00000003U
-#define XTS_AES_STATE_S  0
-
-/** XTS_AES_DATE_REG register
- *  XTS-AES version control register
- */
-#define XTS_AES_DATE_REG (DR_REG_XTS_AES_BASE + 0x5c)
-/** XTS_AES_DATE : R/W; bitpos: [29:0]; default: 538969635;
- *  Those bits stores the version information of XTS-AES.
- */
-#define XTS_AES_DATE    0x3FFFFFFFU
-#define XTS_AES_DATE_M  (XTS_AES_DATE_V << XTS_AES_DATE_S)
-#define XTS_AES_DATE_V  0x3FFFFFFFU
-#define XTS_AES_DATE_S  0
-
-/* For backward compatability with the older register names */
-#define AES_XTS_PLAIN_BASE          XTS_AES_PLAIN_MEM
-#define AES_XTS_SIZE_REG            XTS_AES_LINESIZE_REG
-#define AES_XTS_DESTINATION_REG     XTS_AES_DESTINATION_REG
-#define AES_XTS_PHYSICAL_ADDR_REG   XTS_AES_PHYSICAL_ADDRESS_REG
-#define AES_XTS_TRIGGER_REG         XTS_AES_TRIGGER_REG
-#define AES_XTS_RELEASE_REG         XTS_AES_RELEASE_REG
-#define AES_XTS_DESTROY_REG         XTS_AES_DESTROY_REG
-#define AES_XTS_STATE_REG           XTS_AES_STATE_REG
-#define AES_XTS_DATE_REG            XTS_AES_DATE_REG
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c3/interrupts.c b/components/soc/esp32c3/interrupts.c
index 27775f61881..2a0d74de6ac 100644
--- a/components/soc/esp32c3/interrupts.c
+++ b/components/soc/esp32c3/interrupts.c
@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "soc/interrupts.h"
 
@@ -35,7 +27,7 @@ const char *const esp_isr_names[] = {
     [17] = "GPIO_NMI",
     [18] = "SPI1",
     [19] = "SPI2",
-    [20] = "I2S1",
+    [20] = "I2S0",
     [21] = "UART0",
     [22] = "UART1",
     [23] = "LEDC",
diff --git a/components/soc/esp32c3/register/soc/apb_ctrl_reg.h b/components/soc/esp32c3/register/soc/apb_ctrl_reg.h
new file mode 100644
index 00000000000..f7fb4f1ba97
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/apb_ctrl_reg.h
@@ -0,0 +1,569 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_APB_CTRL_REG_H_
+#define _SOC_APB_CTRL_REG_H_
+
+#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x000)
+/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_RST_TICK_CNT  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_V  0x1
+#define APB_CTRL_RST_TICK_CNT_S  12
+/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_CLK_EN  (BIT(11))
+#define APB_CTRL_CLK_EN_M  (BIT(11))
+#define APB_CTRL_CLK_EN_V  0x1
+#define APB_CTRL_CLK_EN_S  11
+/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_CLK_320M_EN  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_V  0x1
+#define APB_CTRL_CLK_320M_EN_S  10
+/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: */
+#define APB_CTRL_PRE_DIV_CNT  0x000003FF
+#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
+#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
+#define APB_CTRL_PRE_DIV_CNT_S  0
+
+#define APB_CTRL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x004)
+/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: */
+#define APB_CTRL_TICK_ENABLE  (BIT(16))
+#define APB_CTRL_TICK_ENABLE_M  (BIT(16))
+#define APB_CTRL_TICK_ENABLE_V  0x1
+#define APB_CTRL_TICK_ENABLE_S  16
+/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: */
+#define APB_CTRL_CK8M_TICK_NUM  0x000000FF
+#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
+#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
+#define APB_CTRL_CK8M_TICK_NUM_S  8
+/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: */
+#define APB_CTRL_XTAL_TICK_NUM  0x000000FF
+#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
+#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
+#define APB_CTRL_XTAL_TICK_NUM_S  0
+
+#define APB_CTRL_CLK_OUT_EN_REG          (DR_REG_APB_CTRL_BASE + 0x008)
+/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_XTAL_OEN  (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_M  (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_V  0x1
+#define APB_CTRL_CLK_XTAL_OEN_S  10
+/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK40X_BB_OEN  (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_M  (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_V  0x1
+#define APB_CTRL_CLK40X_BB_OEN_S  9
+/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_DAC_CPU_OEN  (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_V  0x1
+#define APB_CTRL_CLK_DAC_CPU_OEN_S  8
+/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_ADC_INF_OEN  (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_M  (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_V  0x1
+#define APB_CTRL_CLK_ADC_INF_OEN_S  7
+/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_320M_OEN  (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_M  (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_V  0x1
+#define APB_CTRL_CLK_320M_OEN_S  6
+/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK160_OEN  (BIT(5))
+#define APB_CTRL_CLK160_OEN_M  (BIT(5))
+#define APB_CTRL_CLK160_OEN_V  0x1
+#define APB_CTRL_CLK160_OEN_S  5
+/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK80_OEN  (BIT(4))
+#define APB_CTRL_CLK80_OEN_M  (BIT(4))
+#define APB_CTRL_CLK80_OEN_V  0x1
+#define APB_CTRL_CLK80_OEN_S  4
+/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_BB_OEN  (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_M  (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_V  0x1
+#define APB_CTRL_CLK_BB_OEN_S  3
+/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK44_OEN  (BIT(2))
+#define APB_CTRL_CLK44_OEN_M  (BIT(2))
+#define APB_CTRL_CLK44_OEN_V  0x1
+#define APB_CTRL_CLK44_OEN_S  2
+/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK22_OEN  (BIT(1))
+#define APB_CTRL_CLK22_OEN_M  (BIT(1))
+#define APB_CTRL_CLK22_OEN_V  0x1
+#define APB_CTRL_CLK22_OEN_S  1
+/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK20_OEN  (BIT(0))
+#define APB_CTRL_CLK20_OEN_M  (BIT(0))
+#define APB_CTRL_CLK20_OEN_V  0x1
+#define APB_CTRL_CLK20_OEN_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_REG          (DR_REG_APB_CTRL_BASE + 0x00C)
+/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_BB_CFG  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_M  ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
+#define APB_CTRL_WIFI_BB_CFG_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_2_REG          (DR_REG_APB_CTRL_BASE + 0x010)
+/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_BB_CFG_2  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_M  ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
+#define APB_CTRL_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_S  0
+
+#define APB_CTRL_WIFI_CLK_EN_REG          (DR_REG_APB_CTRL_BASE + 0x014)
+/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define APB_CTRL_WIFI_CLK_EN  0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_M  ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
+#define APB_CTRL_WIFI_CLK_EN_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_S  0
+
+#define APB_CTRL_WIFI_RST_EN_REG          (DR_REG_APB_CTRL_BASE + 0x018)
+/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_RST  0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_M  ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
+#define APB_CTRL_WIFI_RST_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_S  0
+
+#define APB_CTRL_HOST_INF_SEL_REG          (DR_REG_APB_CTRL_BASE + 0x01C)
+/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define APB_CTRL_PERI_IO_SWAP  0x000000FF
+#define APB_CTRL_PERI_IO_SWAP_M  ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
+#define APB_CTRL_PERI_IO_SWAP_V  0xFF
+#define APB_CTRL_PERI_IO_SWAP_S  0
+
+#define APB_CTRL_EXT_MEM_PMS_LOCK_REG          (DR_REG_APB_CTRL_BASE + 0x020)
+/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_EXT_MEM_PMS_LOCK  (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_V  0x1
+#define APB_CTRL_EXT_MEM_PMS_LOCK_S  0
+
+#define APB_CTRL_FLASH_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x028)
+/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_ATTR  0x00000003
+#define APB_CTRL_FLASH_ACE0_ATTR_M  ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
+#define APB_CTRL_FLASH_ACE0_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE0_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x02C)
+/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_ATTR  0x00000003
+#define APB_CTRL_FLASH_ACE1_ATTR_M  ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
+#define APB_CTRL_FLASH_ACE1_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE1_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x030)
+/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_ATTR  0x00000003
+#define APB_CTRL_FLASH_ACE2_ATTR_M  ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
+#define APB_CTRL_FLASH_ACE2_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE2_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x034)
+/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_ATTR  0x00000003
+#define APB_CTRL_FLASH_ACE3_ATTR_M  ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
+#define APB_CTRL_FLASH_ACE3_ATTR_V  0x3
+#define APB_CTRL_FLASH_ACE3_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x038)
+/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_M  ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x03C)
+/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_M  ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x040)
+/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_M  ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x044)
+/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_M  ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x048)
+/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_SIZE  0x00001FFF
+#define APB_CTRL_FLASH_ACE0_SIZE_M  ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
+#define APB_CTRL_FLASH_ACE0_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE0_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x04C)
+/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_SIZE  0x00001FFF
+#define APB_CTRL_FLASH_ACE1_SIZE_M  ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
+#define APB_CTRL_FLASH_ACE1_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE1_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x050)
+/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_SIZE  0x00001FFF
+#define APB_CTRL_FLASH_ACE2_SIZE_M  ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
+#define APB_CTRL_FLASH_ACE2_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE2_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x054)
+/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_SIZE  0x00001FFF
+#define APB_CTRL_FLASH_ACE3_SIZE_M  ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
+#define APB_CTRL_FLASH_ACE3_SIZE_V  0x1FFF
+#define APB_CTRL_FLASH_ACE3_SIZE_S  0
+
+#define APB_CTRL_SPI_MEM_PMS_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x088)
+/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: */
+#define APB_CTRL_SPI_MEM_REJECT_CDE  0x0000001F
+#define APB_CTRL_SPI_MEM_REJECT_CDE_M  ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
+#define APB_CTRL_SPI_MEM_REJECT_CDE_V  0x1F
+#define APB_CTRL_SPI_MEM_REJECT_CDE_S  2
+/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI_MEM_REJECT_CLR  (BIT(1))
+#define APB_CTRL_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define APB_CTRL_SPI_MEM_REJECT_CLR_V  0x1
+#define APB_CTRL_SPI_MEM_REJECT_CLR_S  1
+/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI_MEM_REJECT_INT  (BIT(0))
+#define APB_CTRL_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define APB_CTRL_SPI_MEM_REJECT_INT_V  0x1
+#define APB_CTRL_SPI_MEM_REJECT_INT_S  0
+
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x08C)
+/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_SPI_MEM_REJECT_ADDR  0xFFFFFFFF
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_M  ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_S  0
+
+#define APB_CTRL_SDIO_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x090)
+/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_SDIO_WIN_ACCESS_EN  (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_V  0x1
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_S  0
+
+#define APB_CTRL_REDCY_SIG0_REG          (DR_REG_APB_CTRL_BASE + 0x094)
+/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_ANDOR  (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_V  0x1
+#define APB_CTRL_REDCY_ANDOR_S  31
+/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_SIG0  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_M  ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
+#define APB_CTRL_REDCY_SIG0_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_S  0
+
+#define APB_CTRL_REDCY_SIG1_REG          (DR_REG_APB_CTRL_BASE + 0x098)
+/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_NANDOR  (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_V  0x1
+#define APB_CTRL_REDCY_NANDOR_S  31
+/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_SIG1  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_M  ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
+#define APB_CTRL_REDCY_SIG1_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_S  0
+
+#define APB_CTRL_FRONT_END_MEM_PD_REG          (DR_REG_APB_CTRL_BASE + 0x09C)
+/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_DC_MEM_FORCE_PD  (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_M  (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PD_S  5
+/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_DC_MEM_FORCE_PU  (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_M  (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PU_S  4
+/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PBUS_MEM_FORCE_PD  (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PD_S  3
+/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_PBUS_MEM_FORCE_PU  (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PU_S  2
+/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_AGC_MEM_FORCE_PD  (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PD_S  1
+/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_AGC_MEM_FORCE_PU  (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PU_S  0
+
+#define APB_CTRL_RETENTION_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x0A0)
+/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST  (BIT(27))
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V  0x1
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S  27
+/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: */
+#define APB_CTRL_RETENTION_LINK_ADDR  0x07FFFFFF
+#define APB_CTRL_RETENTION_LINK_ADDR_M  ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S))
+#define APB_CTRL_RETENTION_LINK_ADDR_V  0x7FFFFFF
+#define APB_CTRL_RETENTION_LINK_ADDR_S  0
+
+#define APB_CTRL_CLKGATE_FORCE_ON_REG          (DR_REG_APB_CTRL_BASE + 0x0A4)
+/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
+/*description: */
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON  0x0000000F
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M  ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V  0xF
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S  2
+/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON  0x00000003
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M  ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V  0x3
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S  0
+
+#define APB_CTRL_MEM_POWER_DOWN_REG          (DR_REG_APB_CTRL_BASE + 0x0A8)
+/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
+/*description: */
+#define APB_CTRL_SRAM_POWER_DOWN  0x0000000F
+#define APB_CTRL_SRAM_POWER_DOWN_M  ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
+#define APB_CTRL_SRAM_POWER_DOWN_V  0xF
+#define APB_CTRL_SRAM_POWER_DOWN_S  2
+/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define APB_CTRL_ROM_POWER_DOWN  0x00000003
+#define APB_CTRL_ROM_POWER_DOWN_M  ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
+#define APB_CTRL_ROM_POWER_DOWN_V  0x3
+#define APB_CTRL_ROM_POWER_DOWN_S  0
+
+#define APB_CTRL_MEM_POWER_UP_REG          (DR_REG_APB_CTRL_BASE + 0x0AC)
+/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
+/*description: */
+#define APB_CTRL_SRAM_POWER_UP  0x0000000F
+#define APB_CTRL_SRAM_POWER_UP_M  ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
+#define APB_CTRL_SRAM_POWER_UP_V  0xF
+#define APB_CTRL_SRAM_POWER_UP_S  2
+/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define APB_CTRL_ROM_POWER_UP  0x00000003
+#define APB_CTRL_ROM_POWER_UP_M  ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
+#define APB_CTRL_ROM_POWER_UP_V  0x3
+#define APB_CTRL_ROM_POWER_UP_S  0
+
+#define APB_CTRL_RND_DATA_REG          (DR_REG_APB_CTRL_BASE + 0x0B0)
+/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define APB_CTRL_RND_DATA  0xFFFFFFFF
+#define APB_CTRL_RND_DATA_M  ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
+#define APB_CTRL_RND_DATA_V  0xFFFFFFFF
+#define APB_CTRL_RND_DATA_S  0
+
+#define APB_CTRL_PERI_BACKUP_CONFIG_REG          (DR_REG_APB_CTRL_BASE + 0x0B4)
+/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ENA  (BIT(31))
+#define APB_CTRL_PERI_BACKUP_ENA_M  (BIT(31))
+#define APB_CTRL_PERI_BACKUP_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_ENA_S  31
+/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_TO_MEM  (BIT(30))
+#define APB_CTRL_PERI_BACKUP_TO_MEM_M  (BIT(30))
+#define APB_CTRL_PERI_BACKUP_TO_MEM_V  0x1
+#define APB_CTRL_PERI_BACKUP_TO_MEM_S  30
+/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_START  (BIT(29))
+#define APB_CTRL_PERI_BACKUP_START_M  (BIT(29))
+#define APB_CTRL_PERI_BACKUP_START_V  0x1
+#define APB_CTRL_PERI_BACKUP_START_S  29
+/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_SIZE  0x000003FF
+#define APB_CTRL_PERI_BACKUP_SIZE_M  ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
+#define APB_CTRL_PERI_BACKUP_SIZE_V  0x3FF
+#define APB_CTRL_PERI_BACKUP_SIZE_S  19
+/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES  0x000003FF
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M  ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V  0x3FF
+#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S  9
+/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT  0x0000001F
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M  ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V  0x1F
+#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S  4
+/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR  0x00000003
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M  ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V  0x3
+#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S  1
+
+#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x0B8)
+/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_CTRL_BACKUP_APB_START_ADDR  0xFFFFFFFF
+#define APB_CTRL_BACKUP_APB_START_ADDR_M  ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S))
+#define APB_CTRL_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_BACKUP_APB_START_ADDR_S  0
+
+#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x0BC)
+/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_CTRL_BACKUP_MEM_START_ADDR  0xFFFFFFFF
+#define APB_CTRL_BACKUP_MEM_START_ADDR_M  ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S))
+#define APB_CTRL_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_BACKUP_MEM_START_ADDR_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_RAW_REG          (DR_REG_APB_CTRL_BASE + 0x0C0)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_ST_REG          (DR_REG_APB_CTRL_BASE + 0x0C4)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_ENA_REG          (DR_REG_APB_CTRL_BASE + 0x0C8)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S  0
+
+#define APB_CTRL_PERI_BACKUP_INT_CLR_REG          (DR_REG_APB_CTRL_BASE + 0x0D0)
+/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V  0x1
+#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S  1
+/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V  0x1
+#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S  0
+
+#define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x3FC)
+/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
+/*description: Version control*/
+#define APB_CTRL_DATE  0xFFFFFFFF
+#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
+#define APB_CTRL_DATE_V  0xFFFFFFFF
+#define APB_CTRL_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_CTRL_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/apb_ctrl_struct.h b/components/soc/esp32c3/register/soc/apb_ctrl_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/apb_ctrl_struct.h
rename to components/soc/esp32c3/register/soc/apb_ctrl_struct.h
diff --git a/components/soc/esp32c3/register/soc/apb_saradc_reg.h b/components/soc/esp32c3/register/soc/apb_saradc_reg.h
new file mode 100644
index 00000000000..87deea2d3e9
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/apb_saradc_reg.h
@@ -0,0 +1,623 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_APB_SARADC_REG_H_
+#define _SOC_APB_SARADC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x000)
+/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
+/*description: wait arbit signal stable after sar_done*/
+#define APB_SARADC_WAIT_ARB_CYCLE  0x00000003
+#define APB_SARADC_WAIT_ARB_CYCLE_M  ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
+#define APB_SARADC_WAIT_ARB_CYCLE_V  0x3
+#define APB_SARADC_WAIT_ARB_CYCLE_S  30
+/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
+/*description: force option to xpd sar blocks*/
+#define APB_SARADC_XPD_SAR_FORCE  0x00000003
+#define APB_SARADC_XPD_SAR_FORCE_M  ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
+#define APB_SARADC_XPD_SAR_FORCE_V  0x3
+#define APB_SARADC_XPD_SAR_FORCE_S  27
+/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
+#define APB_SARADC_SAR_PATT_P_CLEAR  (BIT(23))
+#define APB_SARADC_SAR_PATT_P_CLEAR_M  (BIT(23))
+#define APB_SARADC_SAR_PATT_P_CLEAR_V  0x1
+#define APB_SARADC_SAR_PATT_P_CLEAR_S  23
+/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */
+/*description: 0 ~ 15 means length 1 ~ 16*/
+#define APB_SARADC_SAR_PATT_LEN  0x00000007
+#define APB_SARADC_SAR_PATT_LEN_M  ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S))
+#define APB_SARADC_SAR_PATT_LEN_V  0x7
+#define APB_SARADC_SAR_PATT_LEN_S  15
+/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
+/*description: SAR clock divider*/
+#define APB_SARADC_SAR_CLK_DIV  0x000000FF
+#define APB_SARADC_SAR_CLK_DIV_M  ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
+#define APB_SARADC_SAR_CLK_DIV_V  0xFF
+#define APB_SARADC_SAR_CLK_DIV_S  7
+/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define APB_SARADC_SAR_CLK_GATED  (BIT(6))
+#define APB_SARADC_SAR_CLK_GATED_M  (BIT(6))
+#define APB_SARADC_SAR_CLK_GATED_V  0x1
+#define APB_SARADC_SAR_CLK_GATED_S  6
+/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_SARADC_START  (BIT(1))
+#define APB_SARADC_START_M  (BIT(1))
+#define APB_SARADC_START_V  0x1
+#define APB_SARADC_START_S  1
+/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_SARADC_START_FORCE  (BIT(0))
+#define APB_SARADC_START_FORCE_M  (BIT(0))
+#define APB_SARADC_START_FORCE_V  0x1
+#define APB_SARADC_START_FORCE_S  0
+
+#define APB_SARADC_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x004)
+/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: to enable saradc timer trigger*/
+#define APB_SARADC_TIMER_EN  (BIT(24))
+#define APB_SARADC_TIMER_EN_M  (BIT(24))
+#define APB_SARADC_TIMER_EN_V  0x1
+#define APB_SARADC_TIMER_EN_S  24
+/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
+/*description: to set saradc timer target*/
+#define APB_SARADC_TIMER_TARGET  0x00000FFF
+#define APB_SARADC_TIMER_TARGET_M  ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
+#define APB_SARADC_TIMER_TARGET_V  0xFFF
+#define APB_SARADC_TIMER_TARGET_S  12
+/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+#define APB_SARADC_SAR2_INV  (BIT(10))
+#define APB_SARADC_SAR2_INV_M  (BIT(10))
+#define APB_SARADC_SAR2_INV_V  0x1
+#define APB_SARADC_SAR2_INV_S  10
+/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+#define APB_SARADC_SAR1_INV  (BIT(9))
+#define APB_SARADC_SAR1_INV_M  (BIT(9))
+#define APB_SARADC_SAR1_INV_V  0x1
+#define APB_SARADC_SAR1_INV_S  9
+/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
+/*description: max conversion number*/
+#define APB_SARADC_MAX_MEAS_NUM  0x000000FF
+#define APB_SARADC_MAX_MEAS_NUM_M  ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
+#define APB_SARADC_MAX_MEAS_NUM_V  0xFF
+#define APB_SARADC_MAX_MEAS_NUM_S  1
+/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_SARADC_MEAS_NUM_LIMIT  (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT_V  0x1
+#define APB_SARADC_MEAS_NUM_LIMIT_S  0
+
+#define APB_SARADC_FILTER_CTRL1_REG          (DR_REG_APB_SARADC_BASE + 0x008)
+/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: */
+#define APB_SARADC_FILTER_FACTOR0  0x00000007
+#define APB_SARADC_FILTER_FACTOR0_M  ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
+#define APB_SARADC_FILTER_FACTOR0_V  0x7
+#define APB_SARADC_FILTER_FACTOR0_S  29
+/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
+/*description: */
+#define APB_SARADC_FILTER_FACTOR1  0x00000007
+#define APB_SARADC_FILTER_FACTOR1_M  ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
+#define APB_SARADC_FILTER_FACTOR1_V  0x7
+#define APB_SARADC_FILTER_FACTOR1_S  26
+
+#define APB_SARADC_FSM_WAIT_REG          (DR_REG_APB_SARADC_BASE + 0x00C)
+/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
+/*description: */
+#define APB_SARADC_STANDBY_WAIT  0x000000FF
+#define APB_SARADC_STANDBY_WAIT_M  ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
+#define APB_SARADC_STANDBY_WAIT_V  0xFF
+#define APB_SARADC_STANDBY_WAIT_S  16
+/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
+/*description: */
+#define APB_SARADC_RSTB_WAIT  0x000000FF
+#define APB_SARADC_RSTB_WAIT_M  ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
+#define APB_SARADC_RSTB_WAIT_V  0xFF
+#define APB_SARADC_RSTB_WAIT_S  8
+/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: */
+#define APB_SARADC_XPD_WAIT  0x000000FF
+#define APB_SARADC_XPD_WAIT_M  ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
+#define APB_SARADC_XPD_WAIT_V  0xFF
+#define APB_SARADC_XPD_WAIT_S  0
+
+#define APB_SARADC_SAR1_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x010)
+/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_SARADC_SAR1_STATUS  0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS_M  ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
+#define APB_SARADC_SAR1_STATUS_V  0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS_S  0
+
+#define APB_SARADC_SAR2_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x014)
+/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_SARADC_SAR2_STATUS  0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS_M  ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
+#define APB_SARADC_SAR2_STATUS_V  0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS_S  0
+
+#define APB_SARADC_SAR_PATT_TAB1_REG          (DR_REG_APB_SARADC_BASE + 0x018)
+/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
+#define APB_SARADC_SAR_PATT_TAB1  0x00FFFFFF
+#define APB_SARADC_SAR_PATT_TAB1_M  ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S))
+#define APB_SARADC_SAR_PATT_TAB1_V  0xFFFFFF
+#define APB_SARADC_SAR_PATT_TAB1_S  0
+
+#define APB_SARADC_SAR_PATT_TAB2_REG          (DR_REG_APB_SARADC_BASE + 0x01C)
+/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
+#define APB_SARADC_SAR_PATT_TAB2  0x00FFFFFF
+#define APB_SARADC_SAR_PATT_TAB2_M  ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S))
+#define APB_SARADC_SAR_PATT_TAB2_V  0xFFFFFF
+#define APB_SARADC_SAR_PATT_TAB2_S  0
+
+#define APB_SARADC_ONETIME_SAMPLE_REG          (DR_REG_APB_SARADC_BASE + 0x020)
+/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC1_ONETIME_SAMPLE  (BIT(31))
+#define APB_SARADC1_ONETIME_SAMPLE_M  (BIT(31))
+#define APB_SARADC1_ONETIME_SAMPLE_V  0x1
+#define APB_SARADC1_ONETIME_SAMPLE_S  31
+/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC2_ONETIME_SAMPLE  (BIT(30))
+#define APB_SARADC2_ONETIME_SAMPLE_M  (BIT(30))
+#define APB_SARADC2_ONETIME_SAMPLE_V  0x1
+#define APB_SARADC2_ONETIME_SAMPLE_S  30
+/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ONETIME_START  (BIT(29))
+#define APB_SARADC_ONETIME_START_M  (BIT(29))
+#define APB_SARADC_ONETIME_START_V  0x1
+#define APB_SARADC_ONETIME_START_S  29
+/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */
+/*description: */
+#define APB_SARADC_ONETIME_CHANNEL  0x0000000F
+#define APB_SARADC_ONETIME_CHANNEL_M  ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S))
+#define APB_SARADC_ONETIME_CHANNEL_V  0xF
+#define APB_SARADC_ONETIME_CHANNEL_S  25
+/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
+/*description: */
+#define APB_SARADC_ONETIME_ATTEN  0x00000003
+#define APB_SARADC_ONETIME_ATTEN_M  ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S))
+#define APB_SARADC_ONETIME_ATTEN_V  0x3
+#define APB_SARADC_ONETIME_ATTEN_S  23
+
+#define APB_SARADC_APB_ADC_ARB_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x024)
+/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: adc2 arbiter uses fixed priority*/
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY  (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x1
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
+/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
+/*description: Set adc2 arbiter wifi priority*/
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY  0x00000003
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
+/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
+/*description: Set adc2 arbiter rtc priority*/
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY  0x00000003
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
+/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Set adc2 arbiterapb priority*/
+#define APB_SARADC_ADC_ARB_APB_PRIORITY  0x00000003
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
+/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: adc2 arbiter force grant*/
+#define APB_SARADC_ADC_ARB_GRANT_FORCE  (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
+/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable wifi controller*/
+#define APB_SARADC_ADC_ARB_WIFI_FORCE  (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
+/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable rtc controller*/
+#define APB_SARADC_ADC_ARB_RTC_FORCE  (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
+/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enableapb controller*/
+#define APB_SARADC_ADC_ARB_APB_FORCE  (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_M  (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
+
+#define APB_SARADC_FILTER_CTRL0_REG          (DR_REG_APB_SARADC_BASE + 0x028)
+/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable apb_adc1_filter*/
+#define APB_SARADC_FILTER_RESET  (BIT(31))
+#define APB_SARADC_FILTER_RESET_M  (BIT(31))
+#define APB_SARADC_FILTER_RESET_V  0x1
+#define APB_SARADC_FILTER_RESET_S  31
+/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */
+/*description: apb_adc1_filter_factor*/
+#define APB_SARADC_FILTER_CHANNEL0  0x0000000F
+#define APB_SARADC_FILTER_CHANNEL0_M  ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
+#define APB_SARADC_FILTER_CHANNEL0_V  0xF
+#define APB_SARADC_FILTER_CHANNEL0_S  22
+/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */
+/*description: */
+#define APB_SARADC_FILTER_CHANNEL1  0x0000000F
+#define APB_SARADC_FILTER_CHANNEL1_M  ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
+#define APB_SARADC_FILTER_CHANNEL1_V  0xF
+#define APB_SARADC_FILTER_CHANNEL1_S  18
+
+#define APB_SARADC_1_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x02C)
+/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DATA  0x0001FFFF
+#define APB_SARADC_ADC1_DATA_M  ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
+#define APB_SARADC_ADC1_DATA_V  0x1FFFF
+#define APB_SARADC_ADC1_DATA_S  0
+
+#define APB_SARADC_2_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x030)
+/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DATA  0x0001FFFF
+#define APB_SARADC_ADC2_DATA_M  ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
+#define APB_SARADC_ADC2_DATA_V  0x1FFFF
+#define APB_SARADC_ADC2_DATA_S  0
+
+#define APB_SARADC_THRES0_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x034)
+/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
+/*description: saradc1's thres0 monitor thres*/
+#define APB_SARADC_THRES0_LOW  0x00001FFF
+#define APB_SARADC_THRES0_LOW_M  ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
+#define APB_SARADC_THRES0_LOW_V  0x1FFF
+#define APB_SARADC_THRES0_LOW_S  18
+/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
+/*description: saradc1's thres0 monitor thres*/
+#define APB_SARADC_THRES0_HIGH  0x00001FFF
+#define APB_SARADC_THRES0_HIGH_M  ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
+#define APB_SARADC_THRES0_HIGH_V  0x1FFF
+#define APB_SARADC_THRES0_HIGH_S  5
+/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
+/*description: */
+#define APB_SARADC_THRES0_CHANNEL  0x0000000F
+#define APB_SARADC_THRES0_CHANNEL_M  ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
+#define APB_SARADC_THRES0_CHANNEL_V  0xF
+#define APB_SARADC_THRES0_CHANNEL_S  0
+
+#define APB_SARADC_THRES1_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x038)
+/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
+/*description: saradc1's thres0 monitor thres*/
+#define APB_SARADC_THRES1_LOW  0x00001FFF
+#define APB_SARADC_THRES1_LOW_M  ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
+#define APB_SARADC_THRES1_LOW_V  0x1FFF
+#define APB_SARADC_THRES1_LOW_S  18
+/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
+/*description: saradc1's thres0 monitor thres*/
+#define APB_SARADC_THRES1_HIGH  0x00001FFF
+#define APB_SARADC_THRES1_HIGH_M  ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
+#define APB_SARADC_THRES1_HIGH_V  0x1FFF
+#define APB_SARADC_THRES1_HIGH_S  5
+/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
+/*description: */
+#define APB_SARADC_THRES1_CHANNEL  0x0000000F
+#define APB_SARADC_THRES1_CHANNEL_M  ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
+#define APB_SARADC_THRES1_CHANNEL_V  0xF
+#define APB_SARADC_THRES1_CHANNEL_S  0
+
+#define APB_SARADC_THRES_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x03C)
+/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_EN  (BIT(31))
+#define APB_SARADC_THRES0_EN_M  (BIT(31))
+#define APB_SARADC_THRES0_EN_V  0x1
+#define APB_SARADC_THRES0_EN_S  31
+/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_EN  (BIT(30))
+#define APB_SARADC_THRES1_EN_M  (BIT(30))
+#define APB_SARADC_THRES1_EN_V  0x1
+#define APB_SARADC_THRES1_EN_S  30
+/*description: */
+#define APB_SARADC_THRES_ALL_EN  (BIT(27))
+#define APB_SARADC_THRES_ALL_EN_M  (BIT(27))
+#define APB_SARADC_THRES_ALL_EN_V  0x1
+#define APB_SARADC_THRES_ALL_EN_S  27
+
+#define APB_SARADC_INT_ENA_REG          (DR_REG_APB_SARADC_BASE + 0x040)
+/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DONE_INT_ENA  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_ENA_S  31
+/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DONE_INT_ENA  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_ENA_S  30
+/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_HIGH_INT_ENA  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_ENA_S  29
+/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_HIGH_INT_ENA  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_ENA_S  28
+/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_LOW_INT_ENA  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_ENA_S  27
+/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_LOW_INT_ENA  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_ENA_S  26
+
+#define APB_SARADC_INT_RAW_REG          (DR_REG_APB_SARADC_BASE + 0x044)
+/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DONE_INT_RAW  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_RAW_S  31
+/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DONE_INT_RAW  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_RAW_S  30
+/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_HIGH_INT_RAW  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_RAW_S  29
+/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_HIGH_INT_RAW  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_RAW_S  28
+/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_LOW_INT_RAW  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_RAW_S  27
+/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_LOW_INT_RAW  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_RAW_S  26
+
+#define APB_SARADC_INT_ST_REG          (DR_REG_APB_SARADC_BASE + 0x048)
+/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DONE_INT_ST  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_ST_S  31
+/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DONE_INT_ST  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_ST_S  30
+/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_HIGH_INT_ST  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_ST_S  29
+/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_HIGH_INT_ST  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_ST_S  28
+/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_LOW_INT_ST  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_ST_S  27
+/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_LOW_INT_ST  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_ST_S  26
+
+#define APB_SARADC_INT_CLR_REG          (DR_REG_APB_SARADC_BASE + 0x04C)
+/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC1_DONE_INT_CLR  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_CLR_S  31
+/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_ADC2_DONE_INT_CLR  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_CLR_S  30
+/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_HIGH_INT_CLR  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_CLR_S  29
+/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_HIGH_INT_CLR  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_CLR_S  28
+/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES0_LOW_INT_CLR  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_CLR_S  27
+/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_THRES1_LOW_INT_CLR  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_CLR_S  26
+
+#define APB_SARADC_DMA_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x050)
+/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: enable apb_adc use spi_dma*/
+#define APB_SARADC_APB_ADC_TRANS  (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_M  (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_V  0x1
+#define APB_SARADC_APB_ADC_TRANS_S  31
+/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: reset_apb_adc_state*/
+#define APB_SARADC_APB_ADC_RESET_FSM  (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_M  (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_V  0x1
+#define APB_SARADC_APB_ADC_RESET_FSM_S  30
+/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
+/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
+#define APB_SARADC_APB_ADC_EOF_NUM  0x0000FFFF
+#define APB_SARADC_APB_ADC_EOF_NUM_M  ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
+#define APB_SARADC_APB_ADC_EOF_NUM_V  0xFFFF
+#define APB_SARADC_APB_ADC_EOF_NUM_S  0
+
+#define APB_SARADC_APB_ADC_CLKM_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x054)
+/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
+/*description: Set this bit to enable clk_apll*/
+#define APB_SARADC_CLK_SEL  0x00000003
+#define APB_SARADC_CLK_SEL_M  ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
+#define APB_SARADC_CLK_SEL_V  0x3
+#define APB_SARADC_CLK_SEL_S  21
+/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: */
+#define APB_SARADC_CLK_EN  (BIT(20))
+#define APB_SARADC_CLK_EN_M  (BIT(20))
+#define APB_SARADC_CLK_EN_V  0x1
+#define APB_SARADC_CLK_EN_S  20
+/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
+/*description: Fractional clock divider denominator value*/
+#define APB_SARADC_CLKM_DIV_A  0x0000003F
+#define APB_SARADC_CLKM_DIV_A_M  ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
+#define APB_SARADC_CLKM_DIV_A_V  0x3F
+#define APB_SARADC_CLKM_DIV_A_S  14
+/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
+/*description: Fractional clock divider numerator value*/
+#define APB_SARADC_CLKM_DIV_B  0x0000003F
+#define APB_SARADC_CLKM_DIV_B_M  ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
+#define APB_SARADC_CLKM_DIV_B_V  0x3F
+#define APB_SARADC_CLKM_DIV_B_S  8
+/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
+/*description: Integral I2S clock divider value*/
+#define APB_SARADC_CLKM_DIV_NUM  0x000000FF
+#define APB_SARADC_CLKM_DIV_NUM_M  ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
+#define APB_SARADC_CLKM_DIV_NUM_V  0xFF
+#define APB_SARADC_CLKM_DIV_NUM_S  0
+
+#define APB_SARADC_APB_TSENS_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x058)
+/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_TSENS_PU  (BIT(22))
+#define APB_SARADC_TSENS_PU_M  (BIT(22))
+#define APB_SARADC_TSENS_PU_V  0x1
+#define APB_SARADC_TSENS_PU_S  22
+/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */
+/*description: */
+#define APB_SARADC_TSENS_CLK_DIV  0x000000FF
+#define APB_SARADC_TSENS_CLK_DIV_M  ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S))
+#define APB_SARADC_TSENS_CLK_DIV_V  0xFF
+#define APB_SARADC_TSENS_CLK_DIV_S  14
+/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_TSENS_IN_INV  (BIT(13))
+#define APB_SARADC_TSENS_IN_INV_M  (BIT(13))
+#define APB_SARADC_TSENS_IN_INV_V  0x1
+#define APB_SARADC_TSENS_IN_INV_S  13
+/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define APB_SARADC_TSENS_OUT  0x000000FF
+#define APB_SARADC_TSENS_OUT_M  ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S))
+#define APB_SARADC_TSENS_OUT_V  0xFF
+#define APB_SARADC_TSENS_OUT_S  0
+
+#define APB_SARADC_APB_TSENS_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x05C)
+/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define APB_SARADC_TSENS_CLK_SEL  (BIT(15))
+#define APB_SARADC_TSENS_CLK_SEL_M  (BIT(15))
+#define APB_SARADC_TSENS_CLK_SEL_V  0x1
+#define APB_SARADC_TSENS_CLK_SEL_S  15
+/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define APB_SARADC_TSENS_CLK_INV  (BIT(14))
+#define APB_SARADC_TSENS_CLK_INV_M  (BIT(14))
+#define APB_SARADC_TSENS_CLK_INV_V  0x1
+#define APB_SARADC_TSENS_CLK_INV_S  14
+/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define APB_SARADC_TSENS_XPD_FORCE  0x00000003
+#define APB_SARADC_TSENS_XPD_FORCE_M  ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S))
+#define APB_SARADC_TSENS_XPD_FORCE_V  0x3
+#define APB_SARADC_TSENS_XPD_FORCE_S  12
+/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
+/*description: */
+#define APB_SARADC_TSENS_XPD_WAIT  0x00000FFF
+#define APB_SARADC_TSENS_XPD_WAIT_M  ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S))
+#define APB_SARADC_TSENS_XPD_WAIT_V  0xFFF
+#define APB_SARADC_TSENS_XPD_WAIT_S  0
+
+#define APB_SARADC_CALI_REG          (DR_REG_APB_SARADC_BASE + 0x060)
+/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */
+/*description: */
+#define APB_SARADC_CALI_CFG  0x0001FFFF
+#define APB_SARADC_CALI_CFG_M  ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S))
+#define APB_SARADC_CALI_CFG_V  0x1FFFF
+#define APB_SARADC_CALI_CFG_S  0
+
+#define APB_SARADC_APB_CTRL_DATE_REG          (DR_REG_APB_SARADC_BASE + 0x3fc)
+/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */
+/*description: */
+#define APB_SARADC_DATE  0xFFFFFFFF
+#define APB_SARADC_DATE_M  ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S))
+#define APB_SARADC_DATE_V  0xFFFFFFFF
+#define APB_SARADC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_SARADC_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/apb_saradc_struct.h b/components/soc/esp32c3/register/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/apb_saradc_struct.h
rename to components/soc/esp32c3/register/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32c3/register/soc/assist_debug_reg.h b/components/soc/esp32c3/register/soc/assist_debug_reg.h
new file mode 100644
index 00000000000..615964bd740
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/assist_debug_reg.h
@@ -0,0 +1,683 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_ASSIST_DEBUG_REG_H_
+#define _SOC_ASSIST_DEBUG_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x000)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x004)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x008)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x00C)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x010)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x014)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x018)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x01C)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x020)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x024)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x028)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x02C)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x030)
+/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_PC  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x034)
+/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_AREA_SP  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x038)
+/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x03C)
+/* ASSIST_DEBUG_CORE_0_SP_MAX : RW ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x040)
+/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_SP_PC  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x044)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable CPU Pdebug function  if enable  CPU will update PdebugPC*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable recording function  if enable  assist_debug will update
+ PdebugPC  so you can read it*/
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x048)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x04C)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x050)
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0  0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x054)
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1  0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x058)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0  0x0000000F
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0xF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  24
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0  0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x05C)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x060)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1  0x0000000F
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0xF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  24
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1  0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x064)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x068)
+/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0  0x000FFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0xFFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x06C)
+/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1  0x000FFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0xFFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+#define ASSIST_DEBUG_LOG_SETTING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x070)
+/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE  (BIT(7))
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M  (BIT(7))
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S  7
+/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MODE  0x0000000F
+#define ASSIST_DEBUG_LOG_MODE_M  ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
+#define ASSIST_DEBUG_LOG_MODE_V  0xF
+#define ASSIST_DEBUG_LOG_MODE_S  3
+/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_ENA  0x00000007
+#define ASSIST_DEBUG_LOG_ENA_M  ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
+#define ASSIST_DEBUG_LOG_ENA_V  0x7
+#define ASSIST_DEBUG_LOG_ENA_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x074)
+/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_DATA_0  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_0_M  ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
+#define ASSIST_DEBUG_LOG_DATA_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_0_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_MASK_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x078)
+/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_DATA_SIZE  0x0000FFFF
+#define ASSIST_DEBUG_LOG_DATA_SIZE_M  ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
+#define ASSIST_DEBUG_LOG_DATA_SIZE_V  0xFFFF
+#define ASSIST_DEBUG_LOG_DATA_SIZE_S  0
+
+#define ASSIST_DEBUG_LOG_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x07C)
+/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MIN  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MIN_M  ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
+#define ASSIST_DEBUG_LOG_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MIN_S  0
+
+#define ASSIST_DEBUG_LOG_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x080)
+/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MAX  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MAX_M  ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
+#define ASSIST_DEBUG_LOG_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MAX_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_START_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x084)
+/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_START  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_START_M  ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
+#define ASSIST_DEBUG_LOG_MEM_START_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_START_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_END_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x088)
+/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_END  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_END_M  ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
+#define ASSIST_DEBUG_LOG_MEM_END_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_END_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x08C)
+/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M  ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x090)
+/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG  (BIT(1))
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M  (BIT(1))
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V  0x1
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S  1
+/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG  (BIT(0))
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M  (BIT(0))
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S  0
+
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x094)
+/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S))
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x098)
+/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x1
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x1
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+
+#define ASSIST_DEBUG_DATE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
+/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */
+/*description: */
+#define ASSIST_DEBUG_DATE  0x0FFFFFFF
+#define ASSIST_DEBUG_DATE_M  ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S))
+#define ASSIST_DEBUG_DATE_V  0xFFFFFFF
+#define ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_ASSIST_DEBUG_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/efuse_reg.h b/components/soc/esp32c3/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..39db7b9abb4
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/efuse_reg.h
@@ -0,0 +1,2637 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/efuse_defs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Disable programming of individual eFuses.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Set this bit to disable reading from BlOCK4-10.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0;
+ *  Set this bit to disable boot from RTC RAM.
+ */
+#define EFUSE_DIS_RTC_RAM_BOOT    (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S)
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x00000001U
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
+ *  Set this bit to disable Icache.
+ */
+#define EFUSE_DIS_ICACHE    (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
+#define EFUSE_DIS_ICACHE_V  0x00000001U
+#define EFUSE_DIS_ICACHE_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  Set this bit to disable function of usb switch to jtag in module of usb device.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0;
+ *  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6,
+ *  7).
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Set this bit to disable the function that forces chip into download mode.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_RPT4_RESERVED6 : RO; bitpos: [13]; default: 0;
+ *  Reserved (used for four backups method).
+ */
+#define EFUSE_RPT4_RESERVED6    (BIT(13))
+#define EFUSE_RPT4_RESERVED6_M  (EFUSE_RPT4_RESERVED6_V << EFUSE_RPT4_RESERVED6_S)
+#define EFUSE_RPT4_RESERVED6_V  0x00000001U
+#define EFUSE_RPT4_RESERVED6_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Set this bit to disable CAN function.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG
+ *  can be enabled in HMAC module.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Set this bit to disable flash encryption when in download boot modes.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored
+ *  in eFuse.
+ */
+#define EFUSE_USB_DREFH    0x00000003U
+#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
+#define EFUSE_USB_DREFH_V  0x00000003U
+#define EFUSE_USB_DREFH_S  21
+/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
+ *  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
+ *  stored in eFuse.
+ */
+#define EFUSE_USB_DREFL    0x00000003U
+#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
+#define EFUSE_USB_DREFL_V  0x00000003U
+#define EFUSE_USB_DREFL_S  23
+/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
+ *  Set this bit to exchange USB D+ and D- pins.
+ */
+#define EFUSE_USB_EXCHG_PINS    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
+#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_S  25
+/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
+ *  Set this bit to vdd spi pin function as gpio.
+ */
+#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
+#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_S  26
+/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0;
+ *  Enable btlc gpio.
+ */
+#define EFUSE_BTLC_GPIO_ENABLE    0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_M  (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S)
+#define EFUSE_BTLC_GPIO_ENABLE_V  0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_S  27
+/** EFUSE_POWERGLITCH_EN : RO; bitpos: [29]; default: 0;
+ *  Set this bit to enable power glitch function.
+ */
+#define EFUSE_POWERGLITCH_EN    (BIT(29))
+#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_S  29
+/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [31:30]; default: 0;
+ *  Sample delay configuration of power glitch.
+ */
+#define EFUSE_POWER_GLITCH_DSENSE    0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_M  (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S)
+#define EFUSE_POWER_GLITCH_DSENSE_V  0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_S  30
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register 2.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_RPT4_RESERVED2 : RO; bitpos: [15:0]; default: 0;
+ *  Reserved (used for four backups method).
+ */
+#define EFUSE_RPT4_RESERVED2    0x0000FFFFU
+#define EFUSE_RPT4_RESERVED2_M  (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S)
+#define EFUSE_RPT4_RESERVED2_V  0x0000FFFFU
+#define EFUSE_RPT4_RESERVED2_S  0
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
+ *  80000. 2: 160000. 3:320000.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+ *  number of 1: disable.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Set this bit to enable revoking first secure boot key.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Set this bit to enable revoking second secure boot key.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Set this bit to enable revoking third secure boot key.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register 3.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_RPT4_RESERVED3 : RO; bitpos: [19:16]; default: 0;
+ *  Reserved (used for four backups method).
+ */
+#define EFUSE_RPT4_RESERVED3    0x0000000FU
+#define EFUSE_RPT4_RESERVED3_M  (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S)
+#define EFUSE_RPT4_RESERVED3_V  0x0000000FU
+#define EFUSE_RPT4_RESERVED3_S  16
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Set this bit to enable secure boot.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Set this bit to enable revoking aggressive secure boot.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [27:22]; default: 0;
+ *  Reserved (used for four backups method).
+ */
+#define EFUSE_RPT4_RESERVED0    0x0000003FU
+#define EFUSE_RPT4_RESERVED0_M  (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S)
+#define EFUSE_RPT4_RESERVED0_V  0x0000003FU
+#define EFUSE_RPT4_RESERVED0_S  22
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Configures flash waiting time after power-up, in unit of ms. If the value is less
+ *  than 15, the waiting time is the configurable value; Otherwise, the waiting time is
+ *  twice the configurable value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register 4.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Disable direct boot mode
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0;
+ *  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
+ *  use 16to17 byte mode.
+ */
+#define EFUSE_FLASH_ECC_MODE    (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_M  (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S)
+#define EFUSE_FLASH_ECC_MODE_V  0x00000001U
+#define EFUSE_FLASH_ECC_MODE_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Disable UART download mode through USB-Serial-JTAG
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Set this bit to enable secure UART download mode.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8
+ *  is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0;
+ *  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+ */
+#define EFUSE_PIN_POWER_SELECTION    (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_M  (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S)
+#define EFUSE_PIN_POWER_SELECTION_V  0x00000001U
+#define EFUSE_PIN_POWER_SELECTION_S  8
+/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0;
+ *  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+ */
+#define EFUSE_FLASH_TYPE    (BIT(9))
+#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V  0x00000001U
+#define EFUSE_FLASH_TYPE_S  9
+/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0;
+ *  Set Flash page size.
+ */
+#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
+#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0;
+ *  Set 1 to enable ECC for flash boot.
+ */
+#define EFUSE_FLASH_ECC_EN    (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
+#define EFUSE_FLASH_ECC_EN_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_S  12
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
+ *  Set this bit to force ROM code to send a resume command during SPI boot.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0;
+ *  Secure version (used by ESP-IDF anti-rollback feature).
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  14
+/** EFUSE_RESERVED_0_158 : R; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_0_158    (BIT(30))
+#define EFUSE_RESERVED_0_158_M  (EFUSE_RESERVED_0_158_V << EFUSE_RESERVED_0_158_S)
+#define EFUSE_RESERVED_0_158_V  0x00000001U
+#define EFUSE_RESERVED_0_158_S  30
+/** EFUSE_ERR_RST_ENABLE : R; bitpos: [31]; default: 0;
+ *  Use BLOCK0 to check error record registers
+ */
+#define EFUSE_ERR_RST_ENABLE    (BIT(31))
+#define EFUSE_ERR_RST_ENABLE_M  (EFUSE_ERR_RST_ENABLE_V << EFUSE_ERR_RST_ENABLE_S)
+#define EFUSE_ERR_RST_ENABLE_V  0x00000001U
+#define EFUSE_ERR_RST_ENABLE_S  31
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register 5.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(0))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  0
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(1))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  1
+/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_0_162    0x003FFFFFU
+#define EFUSE_RESERVED_0_162_M  (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S)
+#define EFUSE_RESERVED_0_162_V  0x003FFFFFU
+#define EFUSE_RESERVED_0_162_S  2
+
+/** EFUSE_RD_MAC_SPI_SYS_0_REG register
+ *  BLOCK1 data register 0.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SPI_SYS_1_REG register
+ *  BLOCK1 data register 1.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0;
+ *  SPI PAD CLK
+ */
+#define EFUSE_SPI_PAD_CONFIG_CLK    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_CLK_M  (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S)
+#define EFUSE_SPI_PAD_CONFIG_CLK_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_CLK_S  16
+/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0;
+ *  SPI PAD Q(D1)
+ */
+#define EFUSE_SPI_PAD_CONFIG_Q    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_Q_M  (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S)
+#define EFUSE_SPI_PAD_CONFIG_Q_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_Q_S  22
+/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0;
+ *  SPI PAD D(D0)
+ */
+#define EFUSE_SPI_PAD_CONFIG_D    0x0000000FU
+#define EFUSE_SPI_PAD_CONFIG_D_M  (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S)
+#define EFUSE_SPI_PAD_CONFIG_D_V  0x0000000FU
+#define EFUSE_SPI_PAD_CONFIG_D_S  28
+
+/** EFUSE_RD_MAC_SPI_SYS_2_REG register
+ *  BLOCK1 data register 2.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0;
+ *  SPI PAD D(D0)
+ */
+#define EFUSE_SPI_PAD_CONFIG_D_1    0x00000003U
+#define EFUSE_SPI_PAD_CONFIG_D_1_M  (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S)
+#define EFUSE_SPI_PAD_CONFIG_D_1_V  0x00000003U
+#define EFUSE_SPI_PAD_CONFIG_D_1_S  0
+/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0;
+ *  SPI PAD CS
+ */
+#define EFUSE_SPI_PAD_CONFIG_CS    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_CS_M  (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S)
+#define EFUSE_SPI_PAD_CONFIG_CS_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_CS_S  2
+/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0;
+ *  SPI PAD HD(D3)
+ */
+#define EFUSE_SPI_PAD_CONFIG_HD    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_HD_M  (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S)
+#define EFUSE_SPI_PAD_CONFIG_HD_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_HD_S  8
+/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0;
+ *  SPI PAD WP(D2)
+ */
+#define EFUSE_SPI_PAD_CONFIG_WP    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_WP_M  (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S)
+#define EFUSE_SPI_PAD_CONFIG_WP_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_WP_S  14
+/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0;
+ *  SPI PAD DQS
+ */
+#define EFUSE_SPI_PAD_CONFIG_DQS    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_DQS_M  (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S)
+#define EFUSE_SPI_PAD_CONFIG_DQS_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_DQS_S  20
+/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0;
+ *  SPI PAD D4
+ */
+#define EFUSE_SPI_PAD_CONFIG_D4    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D4_M  (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S)
+#define EFUSE_SPI_PAD_CONFIG_D4_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D4_S  26
+
+/** EFUSE_RD_MAC_SPI_SYS_3_REG register
+ *  BLOCK1 data register 3.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0;
+ *  SPI PAD D5
+ */
+#define EFUSE_SPI_PAD_CONFIG_D5    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D5_M  (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S)
+#define EFUSE_SPI_PAD_CONFIG_D5_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D5_S  0
+/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0;
+ *  SPI PAD D6
+ */
+#define EFUSE_SPI_PAD_CONFIG_D6    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D6_M  (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S)
+#define EFUSE_SPI_PAD_CONFIG_D6_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D6_S  6
+/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0;
+ *  SPI PAD D7
+ */
+#define EFUSE_SPI_PAD_CONFIG_D7    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D7_M  (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S)
+#define EFUSE_SPI_PAD_CONFIG_D7_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D7_S  12
+/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0;
+ *  WAFER_VERSION_MINOR least significant bits
+ */
+#define EFUSE_WAFER_VERSION_MINOR_LO    0x00000007U
+#define EFUSE_WAFER_VERSION_MINOR_LO_M  (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S)
+#define EFUSE_WAFER_VERSION_MINOR_LO_V  0x00000007U
+#define EFUSE_WAFER_VERSION_MINOR_LO_S  18
+/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  21
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0;
+ *  BLK_VERSION_MINOR
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  24
+/** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0;
+ *  Flash capacity
+ */
+#define EFUSE_FLASH_CAP    0x00000007U
+#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
+#define EFUSE_FLASH_CAP_V  0x00000007U
+#define EFUSE_FLASH_CAP_S  27
+/** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0;
+ *  Flash temperature
+ */
+#define EFUSE_FLASH_TEMP    0x00000003U
+#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
+#define EFUSE_FLASH_TEMP_V  0x00000003U
+#define EFUSE_FLASH_TEMP_S  30
+
+/** EFUSE_RD_MAC_SPI_SYS_4_REG register
+ *  BLOCK1 data register 4.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0;
+ *  Flash vendor
+ */
+#define EFUSE_FLASH_VENDOR    0x00000007U
+#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
+#define EFUSE_FLASH_VENDOR_V  0x00000007U
+#define EFUSE_FLASH_VENDOR_S  0
+/** EFUSE_RESERVED_1_131 : R; bitpos: [6:3]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_131    0x0000000FU
+#define EFUSE_RESERVED_1_131_M  (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S)
+#define EFUSE_RESERVED_1_131_V  0x0000000FU
+#define EFUSE_RESERVED_1_131_S  3
+/** EFUSE_K_RTC_LDO : R; bitpos: [13:7]; default: 0;
+ *  BLOCK1 K_RTC_LDO
+ */
+#define EFUSE_K_RTC_LDO    0x0000007FU
+#define EFUSE_K_RTC_LDO_M  (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S)
+#define EFUSE_K_RTC_LDO_V  0x0000007FU
+#define EFUSE_K_RTC_LDO_S  7
+/** EFUSE_K_DIG_LDO : R; bitpos: [20:14]; default: 0;
+ *  BLOCK1 K_DIG_LDO
+ */
+#define EFUSE_K_DIG_LDO    0x0000007FU
+#define EFUSE_K_DIG_LDO_M  (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S)
+#define EFUSE_K_DIG_LDO_V  0x0000007FU
+#define EFUSE_K_DIG_LDO_S  14
+/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [28:21]; default: 0;
+ *  BLOCK1 voltage of rtc dbias20
+ */
+#define EFUSE_V_RTC_DBIAS20    0x000000FFU
+#define EFUSE_V_RTC_DBIAS20_M  (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S)
+#define EFUSE_V_RTC_DBIAS20_V  0x000000FFU
+#define EFUSE_V_RTC_DBIAS20_S  21
+/** EFUSE_V_DIG_DBIAS20 : R; bitpos: [31:29]; default: 0;
+ *  BLOCK1 voltage of digital dbias20
+ */
+#define EFUSE_V_DIG_DBIAS20    0x00000007U
+#define EFUSE_V_DIG_DBIAS20_M  (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S)
+#define EFUSE_V_DIG_DBIAS20_V  0x00000007U
+#define EFUSE_V_DIG_DBIAS20_S  29
+
+/** EFUSE_RD_MAC_SPI_SYS_5_REG register
+ *  BLOCK1 data register 5.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_V_DIG_DBIAS20_1 : R; bitpos: [4:0]; default: 0;
+ *  BLOCK1 voltage of digital dbias20
+ */
+#define EFUSE_V_DIG_DBIAS20_1    0x0000001FU
+#define EFUSE_V_DIG_DBIAS20_1_M  (EFUSE_V_DIG_DBIAS20_1_V << EFUSE_V_DIG_DBIAS20_1_S)
+#define EFUSE_V_DIG_DBIAS20_1_V  0x0000001FU
+#define EFUSE_V_DIG_DBIAS20_1_S  0
+/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [9:5]; default: 0;
+ *  BLOCK1 digital dbias when hvt
+ */
+#define EFUSE_DIG_DBIAS_HVT    0x0000001FU
+#define EFUSE_DIG_DBIAS_HVT_M  (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
+#define EFUSE_DIG_DBIAS_HVT_V  0x0000001FU
+#define EFUSE_DIG_DBIAS_HVT_S  5
+/** EFUSE_THRES_HVT : R; bitpos: [19:10]; default: 0;
+ *  BLOCK1 pvt threshold when hvt
+ */
+#define EFUSE_THRES_HVT    0x000003FFU
+#define EFUSE_THRES_HVT_M  (EFUSE_THRES_HVT_V << EFUSE_THRES_HVT_S)
+#define EFUSE_THRES_HVT_V  0x000003FFU
+#define EFUSE_THRES_HVT_S  10
+/** EFUSE_RESERVED_1_180 : R; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_180    0x00000007U
+#define EFUSE_RESERVED_1_180_M  (EFUSE_RESERVED_1_180_V << EFUSE_RESERVED_1_180_S)
+#define EFUSE_RESERVED_1_180_V  0x00000007U
+#define EFUSE_RESERVED_1_180_S  20
+/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0;
+ *  WAFER_VERSION_MINOR most significant bit
+ */
+#define EFUSE_WAFER_VERSION_MINOR_HI    (BIT(23))
+#define EFUSE_WAFER_VERSION_MINOR_HI_M  (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S)
+#define EFUSE_WAFER_VERSION_MINOR_HI_V  0x00000001U
+#define EFUSE_WAFER_VERSION_MINOR_HI_S  23
+/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0;
+ *  WAFER_VERSION_MAJOR
+ */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  24
+/** EFUSE_RESERVED_1_186 : R; bitpos: [31:26]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_186    0x0000003FU
+#define EFUSE_RESERVED_1_186_M  (EFUSE_RESERVED_1_186_V << EFUSE_RESERVED_1_186_S)
+#define EFUSE_RESERVED_1_186_V  0x0000003FU
+#define EFUSE_RESERVED_1_186_S  26
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register 0 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register 1 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register 2 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register 3 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register 4 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  0
+/** EFUSE_RESERVED_2_130 : R; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_130    (BIT(2))
+#define EFUSE_RESERVED_2_130_M  (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S)
+#define EFUSE_RESERVED_2_130_V  0x00000001U
+#define EFUSE_RESERVED_2_130_S  2
+/** EFUSE_TEMP_CALIB : R; bitpos: [11:3]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMP_CALIB    0x000001FFU
+#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
+#define EFUSE_TEMP_CALIB_V  0x000001FFU
+#define EFUSE_TEMP_CALIB_S  3
+/** EFUSE_OCODE : R; bitpos: [19:12]; default: 0;
+ *  ADC OCode
+ */
+#define EFUSE_OCODE    0x000000FFU
+#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
+#define EFUSE_OCODE_V  0x000000FFU
+#define EFUSE_OCODE_S  12
+/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [29:20]; default: 0;
+ *  ADC1 init code at atten0
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_S  20
+/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:30]; default: 0;
+ *  ADC1 init code at atten1
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN1    0x00000003U
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_V  0x00000003U
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_S  30
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register 5 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [7:0]; default: 0;
+ *  ADC1 init code at atten1
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1    0x000000FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V  0x000000FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S  0
+/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [17:8]; default: 0;
+ *  ADC1 init code at atten2
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_M  (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_S  8
+/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [27:18]; default: 0;
+ *  ADC1 init code at atten3
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_S  18
+/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:28]; default: 0;
+ *  ADC1 calibration voltage at atten0
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN0    0x0000000FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_V  0x0000000FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_S  28
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register 6 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [5:0]; default: 0;
+ *  ADC1 calibration voltage at atten0
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1    0x0000003FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V  0x0000003FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S  0
+/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [15:6]; default: 0;
+ *  ADC1 calibration voltage at atten1
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_M  (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_S  6
+/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [25:16]; default: 0;
+ *  ADC1 calibration voltage at atten2
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_M  (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_S  16
+/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0;
+ *  ADC1 calibration voltage at atten3
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN3    0x0000003FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_V  0x0000003FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_S  26
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register 7 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_ADC1_CAL_VOL_ATTEN3_1 : R; bitpos: [3:0]; default: 0;
+ *  ADC1 calibration voltage at atten3
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_1    0x0000000FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_1_V << EFUSE_ADC1_CAL_VOL_ATTEN3_1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_V  0x0000000FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_S  0
+/** EFUSE_RESERVED_2_228 : R; bitpos: [31:4]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_228    0x0FFFFFFFU
+#define EFUSE_RESERVED_2_228_M  (EFUSE_RESERVED_2_228_V << EFUSE_RESERVED_2_228_S)
+#define EFUSE_RESERVED_2_228_V  0x0FFFFFFFU
+#define EFUSE_RESERVED_2_228_S  4
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register 0 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register 1 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register 2 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register 3 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register 4 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register 5 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register 6 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC address
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register 7 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC address
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register 0 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register 1 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register 2 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register 3 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register 4 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register 5 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register 6 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register 7 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register 0 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register 1 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register 2 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register 3 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register 4 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register 5 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register 6 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register 7 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register 0 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register 1 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register 2 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register 3 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register 4 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register 5 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register 6 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register 7 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register 0 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register 1 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register 2 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register 3 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register 4 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register 5 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register 6 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register 7 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register 0 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register 1 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register 2 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register 3 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register 4 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register 5 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register 6 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register 7 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register 0 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register 1 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register 2 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register 3 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register 4 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register 5 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register 6 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register 7 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register 0 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 0th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register 1 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 1st 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register 2 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 2nd 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register 3 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 3rd 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register 4 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 4th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register 5 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 5th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register 6 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 6th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register 7 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 7th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  If any bit in RD_DIS is 1, then it indicates a programming error.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0;
+ *  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR    (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M  (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S)
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S  7
+/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
+ *  If DIS_ICACHE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
+#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_ICACHE_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  If DIS_USB_JTAG is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0;
+ *  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  10
+/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [11]; default: 0;
+ *  If DIS_USB_DEVICE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_DEVICE_ERR    (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_ERR_M  (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S)
+#define EFUSE_DIS_USB_DEVICE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DEVICE_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_RPT4_RESERVED6_ERR : RO; bitpos: [13]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED6_ERR    (BIT(13))
+#define EFUSE_RPT4_RESERVED6_ERR_M  (EFUSE_RPT4_RESERVED6_ERR_V << EFUSE_RPT4_RESERVED6_ERR_S)
+#define EFUSE_RPT4_RESERVED6_ERR_V  0x00000001U
+#define EFUSE_RPT4_RESERVED6_ERR_S  13
+/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0;
+ *  If DIS_CAN is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_CAN_ERR    (BIT(14))
+#define EFUSE_DIS_CAN_ERR_M  (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S)
+#define EFUSE_DIS_CAN_ERR_V  0x00000001U
+#define EFUSE_DIS_CAN_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  If DIS_PAD_JTAG is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  If any bit in USB_DREFH is 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
+#define EFUSE_USB_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DREFH_ERR_S  21
+/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
+ *  If any bit in USB_DREFL is 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
+#define EFUSE_USB_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DREFL_ERR_S  23
+/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
+ *  If USB_EXCHG_PINS is 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_ERR_S  25
+/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
+ *  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
+/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0;
+ *  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+ */
+#define EFUSE_BTLC_GPIO_ENABLE_ERR    0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_M  (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S)
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_V  0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_S  27
+/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [29]; default: 0;
+ *  If POWERGLITCH_EN is 1, then it indicates a programming error.
+ */
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(29))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_ERR_S  29
+/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [31:30]; default: 0;
+ *  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+ */
+#define EFUSE_POWER_GLITCH_DSENSE_ERR    0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_M  (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S)
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_V  0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_S  30
+
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [15:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_ERR    0x0000FFFFU
+#define EFUSE_RPT4_RESERVED2_ERR_M  (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S)
+#define EFUSE_RPT4_RESERVED2_ERR_V  0x0000FFFFU
+#define EFUSE_RPT4_RESERVED2_ERR_S  0
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [19:16]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR    0x0000000FU
+#define EFUSE_RPT4_RESERVED3_ERR_M  (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S)
+#define EFUSE_RPT4_RESERVED3_ERR_V  0x0000000FU
+#define EFUSE_RPT4_RESERVED3_ERR_S  16
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  If SECURE_BOOT_EN is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [27:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR    0x0000003FU
+#define EFUSE_RPT4_RESERVED0_ERR_M  (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S)
+#define EFUSE_RPT4_RESERVED0_ERR_V  0x0000003FU
+#define EFUSE_RPT4_RESERVED0_ERR_S  22
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M  (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S)
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S  1
+/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0;
+ *  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+ */
+#define EFUSE_UART_PRINT_CHANNEL_ERR    (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_ERR_M  (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S)
+#define EFUSE_UART_PRINT_CHANNEL_ERR_V  0x00000001U
+#define EFUSE_UART_PRINT_CHANNEL_ERR_S  2
+/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0;
+ *  If FLASH_ECC_MODE is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_ECC_MODE_ERR    (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_ERR_M  (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S)
+#define EFUSE_FLASH_ECC_MODE_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_MODE_ERR_S  3
+/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0;
+ *  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+ */
+#define EFUSE_PIN_POWER_SELECTION_ERR    (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_ERR_M  (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S)
+#define EFUSE_PIN_POWER_SELECTION_ERR_V  0x00000001U
+#define EFUSE_PIN_POWER_SELECTION_ERR_S  8
+/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0;
+ *  If FLASH_TYPE is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_TYPE_ERR    (BIT(9))
+#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
+#define EFUSE_FLASH_TYPE_ERR_S  9
+/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0;
+ *  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S  10
+/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0;
+ *  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_ECC_EN_ERR    (BIT(12))
+#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
+#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_ERR_S  12
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
+ *  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0;
+ *  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  14
+/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31:30]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED1_ERR    0x00000003U
+#define EFUSE_RPT4_RESERVED1_ERR_M  (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S)
+#define EFUSE_RPT4_RESERVED1_ERR_V  0x00000003U
+#define EFUSE_RPT4_RESERVED1_ERR_S  30
+
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
+/** EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_ERR    0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED4_ERR_M  (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S)
+#define EFUSE_RPT4_RESERVED4_ERR_V  0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED4_ERR_S  0
+
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
+#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
+/** EFUSE_RESERVED_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_RESERVED_FAIL    (BIT(3))
+#define EFUSE_RESERVED_FAIL_M  (EFUSE_RESERVED_FAIL_V << EFUSE_RESERVED_FAIL_S)
+#define EFUSE_RESERVED_FAIL_V  0x00000001U
+#define EFUSE_RESERVED_FAIL_S  3
+/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_NUM    0x00000007U
+#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
+#define EFUSE_SYS_PART1_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_NUM_S  4
+/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SPI_8M_FAIL    (BIT(7))
+#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
+#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
+#define EFUSE_MAC_SPI_8M_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(11))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+ *  key0 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(15))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY0_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+ *  key1 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(19))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY1_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+ *  key2 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(23))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY2_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+ *  key3 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(27))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY3_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+ *  key4 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(31))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  31
+
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY4_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(3))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_KEY5_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(7))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  7
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_EFUSE_MEM_FORCE_PD_M  (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_EFUSE_MEM_FORCE_PU_M  (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit and force to enable clock signal of eFuse memory.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register;
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0;
+ *  Indicates the number of error bits during programming BLOCK0.
+ */
+#define EFUSE_REPEAT_ERR_CNT    0x000000FFU
+#define EFUSE_REPEAT_ERR_CNT_M  (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S)
+#define EFUSE_REPEAT_ERR_CNT_V  0x000000FFU
+#define EFUSE_REPEAT_ERR_CNT_S  10
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
+ *  Configures the initial read time of eFuse.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 33583616;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/efuse_struct.h b/components/soc/esp32c3/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..f12563cebd0
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/efuse_struct.h
@@ -0,0 +1,2386 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: Read Data Register */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Disable programming of individual eFuses.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Set this bit to disable reading from BlOCK4-10.
+         */
+        uint32_t rd_dis:7;
+        /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0;
+         *  Set this bit to disable boot from RTC RAM.
+         */
+        uint32_t dis_rtc_ram_boot:1;
+        /** dis_icache : RO; bitpos: [8]; default: 0;
+         *  Set this bit to disable Icache.
+         */
+        uint32_t dis_icache:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Set this bit to disable function of usb switch to jtag in module of usb device.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** dis_download_icache : RO; bitpos: [10]; default: 0;
+         *  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6,
+         *  7).
+         */
+        uint32_t dis_download_icache:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled. 1: Disabled. 0: Enabled
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Set this bit to disable the function that forces chip into download mode.
+         */
+        uint32_t dis_force_download:1;
+        /** rpt4_reserved6 : RO; bitpos: [13]; default: 0;
+         *  Reserved (used for four backups method).
+         */
+        uint32_t rpt4_reserved6:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Set this bit to disable CAN function.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG
+         *  can be enabled in HMAC module.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable flash encryption when in download boot modes.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
+         *  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored
+         *  in eFuse.
+         */
+        uint32_t usb_drefh:2;
+        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
+         *  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
+         *  stored in eFuse.
+         */
+        uint32_t usb_drefl:2;
+        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
+         *  Set this bit to exchange USB D+ and D- pins.
+         */
+        uint32_t usb_exchg_pins:1;
+        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
+         *  Set this bit to vdd spi pin function as gpio.
+         */
+        uint32_t vdd_spi_as_gpio:1;
+        /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0;
+         *  Enable btlc gpio.
+         */
+        uint32_t btlc_gpio_enable:2;
+        /** powerglitch_en : RO; bitpos: [29]; default: 0;
+         *  Set this bit to enable power glitch function.
+         */
+        uint32_t powerglitch_en:1;
+        /** power_glitch_dsense : RO; bitpos: [31:30]; default: 0;
+         *  Sample delay configuration of power glitch.
+         */
+        uint32_t power_glitch_dsense:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register 2.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved2 : RO; bitpos: [15:0]; default: 0;
+         *  Reserved (used for four backups method).
+         */
+        uint32_t rpt4_reserved2:16;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
+         *  80000. 2: 160000. 3:320000.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+         *  number of 1: disable.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Set this bit to enable revoking first secure boot key.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Set this bit to enable revoking second secure boot key.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Set this bit to enable revoking third secure boot key.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register 3.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** rpt4_reserved3 : RO; bitpos: [19:16]; default: 0;
+         *  Reserved (used for four backups method).
+         */
+        uint32_t rpt4_reserved3:4;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Set this bit to enable secure boot.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Set this bit to enable revoking aggressive secure boot.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** rpt4_reserved0 : RO; bitpos: [27:22]; default: 0;
+         *  Reserved (used for four backups method).
+         */
+        uint32_t rpt4_reserved0:6;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Configures flash waiting time after power-up, in unit of ms. If the value is less
+         *  than 15, the waiting time is the configurable value; Otherwise, the waiting time is
+         *  twice the configurable value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register 4.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Disable direct boot mode
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Represents whether USB printing is disabled or enabled. 1: Disabled. 0: Enabled
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** flash_ecc_mode : RO; bitpos: [3]; default: 0;
+         *  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
+         *  use 16to17 byte mode.
+         */
+        uint32_t flash_ecc_mode:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Disable UART download mode through USB-Serial-JTAG
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Set this bit to enable secure UART download mode.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8
+         *  is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+         */
+        uint32_t uart_print_control:2;
+        /** pin_power_selection : RO; bitpos: [8]; default: 0;
+         *  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+         */
+        uint32_t pin_power_selection:1;
+        /** flash_type : RO; bitpos: [9]; default: 0;
+         *  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+         */
+        uint32_t flash_type:1;
+        /** flash_page_size : RO; bitpos: [11:10]; default: 0;
+         *  Set Flash page size.
+         */
+        uint32_t flash_page_size:2;
+        /** flash_ecc_en : RO; bitpos: [12]; default: 0;
+         *  Set 1 to enable ECC for flash boot.
+         */
+        uint32_t flash_ecc_en:1;
+        /** force_send_resume : RO; bitpos: [13]; default: 0;
+         *  Set this bit to force ROM code to send a resume command during SPI boot.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [29:14]; default: 0;
+         *  Secure version (used by ESP-IDF anti-rollback feature).
+         */
+        uint32_t secure_version:16;
+        /** reserved_0_158 : R; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_0_158:1;
+        /** err_rst_enable : R; bitpos: [31]; default: 0;
+         *  Use BLOCK0 to check error record registers
+         */
+        uint32_t err_rst_enable:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register 5.
+ */
+typedef union {
+    struct {
+        /** disable_wafer_version_major : R; bitpos: [0]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [1]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** reserved_0_162 : R; bitpos: [23:2]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_0_162:22;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_spi_sys_0 register
+ *  BLOCK1 data register 0.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_0_reg_t;
+
+/** Type of rd_mac_spi_sys_1 register
+ *  BLOCK1 data register 1.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0;
+         *  SPI PAD CLK
+         */
+        uint32_t spi_pad_config_clk:6;
+        /** spi_pad_config_q : R; bitpos: [27:22]; default: 0;
+         *  SPI PAD Q(D1)
+         */
+        uint32_t spi_pad_config_q:6;
+        /** spi_pad_config_d : R; bitpos: [31:28]; default: 0;
+         *  SPI PAD D(D0)
+         */
+        uint32_t spi_pad_config_d:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_1_reg_t;
+
+/** Type of rd_mac_spi_sys_2 register
+ *  BLOCK1 data register 2.
+ */
+typedef union {
+    struct {
+        /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0;
+         *  SPI PAD D(D0)
+         */
+        uint32_t spi_pad_config_d_1:2;
+        /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0;
+         *  SPI PAD CS
+         */
+        uint32_t spi_pad_config_cs:6;
+        /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0;
+         *  SPI PAD HD(D3)
+         */
+        uint32_t spi_pad_config_hd:6;
+        /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0;
+         *  SPI PAD WP(D2)
+         */
+        uint32_t spi_pad_config_wp:6;
+        /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0;
+         *  SPI PAD DQS
+         */
+        uint32_t spi_pad_config_dqs:6;
+        /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0;
+         *  SPI PAD D4
+         */
+        uint32_t spi_pad_config_d4:6;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_2_reg_t;
+
+/** Type of rd_mac_spi_sys_3 register
+ *  BLOCK1 data register 3.
+ */
+typedef union {
+    struct {
+        /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0;
+         *  SPI PAD D5
+         */
+        uint32_t spi_pad_config_d5:6;
+        /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0;
+         *  SPI PAD D6
+         */
+        uint32_t spi_pad_config_d6:6;
+        /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0;
+         *  SPI PAD D7
+         */
+        uint32_t spi_pad_config_d7:6;
+        /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0;
+         *  WAFER_VERSION_MINOR least significant bits
+         */
+        uint32_t wafer_version_minor_lo:3;
+        /** pkg_version : R; bitpos: [23:21]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** blk_version_minor : R; bitpos: [26:24]; default: 0;
+         *  BLK_VERSION_MINOR
+         */
+        uint32_t blk_version_minor:3;
+        /** flash_cap : R; bitpos: [29:27]; default: 0;
+         *  Flash capacity
+         */
+        uint32_t flash_cap:3;
+        /** flash_temp : R; bitpos: [31:30]; default: 0;
+         *  Flash temperature
+         */
+        uint32_t flash_temp:2;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_3_reg_t;
+
+/** Type of rd_mac_spi_sys_4 register
+ *  BLOCK1 data register 4.
+ */
+typedef union {
+    struct {
+        /** flash_vendor : R; bitpos: [2:0]; default: 0;
+         *  Flash vendor
+         */
+        uint32_t flash_vendor:3;
+        /** reserved_1_131 : R; bitpos: [6:3]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_131:4;
+        /** k_rtc_ldo : R; bitpos: [13:7]; default: 0;
+         *  BLOCK1 K_RTC_LDO
+         */
+        uint32_t k_rtc_ldo:7;
+        /** k_dig_ldo : R; bitpos: [20:14]; default: 0;
+         *  BLOCK1 K_DIG_LDO
+         */
+        uint32_t k_dig_ldo:7;
+        /** v_rtc_dbias20 : R; bitpos: [28:21]; default: 0;
+         *  BLOCK1 voltage of rtc dbias20
+         */
+        uint32_t v_rtc_dbias20:8;
+        /** v_dig_dbias20 : R; bitpos: [31:29]; default: 0;
+         *  BLOCK1 voltage of digital dbias20
+         */
+        uint32_t v_dig_dbias20:3;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_4_reg_t;
+
+/** Type of rd_mac_spi_sys_5 register
+ *  BLOCK1 data register 5.
+ */
+typedef union {
+    struct {
+        /** v_dig_dbias20_1 : R; bitpos: [4:0]; default: 0;
+         *  BLOCK1 voltage of digital dbias20
+         */
+        uint32_t v_dig_dbias20_1:5;
+        /** dig_dbias_hvt : R; bitpos: [9:5]; default: 0;
+         *  BLOCK1 digital dbias when hvt
+         */
+        uint32_t dig_dbias_hvt:5;
+        /** thres_hvt : R; bitpos: [19:10]; default: 0;
+         *  BLOCK1 pvt threshold when hvt
+         */
+        uint32_t thres_hvt:10;
+        /** reserved_1_180 : R; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_180:3;
+        /** wafer_version_minor_hi : R; bitpos: [23]; default: 0;
+         *  WAFER_VERSION_MINOR most significant bit
+         */
+        uint32_t wafer_version_minor_hi:1;
+        /** wafer_version_major : R; bitpos: [25:24]; default: 0;
+         *  WAFER_VERSION_MAJOR
+         */
+        uint32_t wafer_version_major:2;
+        /** reserved_1_186 : R; bitpos: [31:26]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_186:6;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register 0 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register 1 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register 2 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register 3 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register 4 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** blk_version_major : R; bitpos: [1:0]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+        /** reserved_2_130 : R; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_130:1;
+        /** temp_calib : R; bitpos: [11:3]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temp_calib:9;
+        /** ocode : R; bitpos: [19:12]; default: 0;
+         *  ADC OCode
+         */
+        uint32_t ocode:8;
+        /** adc1_init_code_atten0 : R; bitpos: [29:20]; default: 0;
+         *  ADC1 init code at atten0
+         */
+        uint32_t adc1_init_code_atten0:10;
+        /** adc1_init_code_atten1 : R; bitpos: [31:30]; default: 0;
+         *  ADC1 init code at atten1
+         */
+        uint32_t adc1_init_code_atten1:2;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register 5 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_init_code_atten1_1 : R; bitpos: [7:0]; default: 0;
+         *  ADC1 init code at atten1
+         */
+        uint32_t adc1_init_code_atten1_1:8;
+        /** adc1_init_code_atten2 : R; bitpos: [17:8]; default: 0;
+         *  ADC1 init code at atten2
+         */
+        uint32_t adc1_init_code_atten2:10;
+        /** adc1_init_code_atten3 : R; bitpos: [27:18]; default: 0;
+         *  ADC1 init code at atten3
+         */
+        uint32_t adc1_init_code_atten3:10;
+        /** adc1_cal_vol_atten0 : R; bitpos: [31:28]; default: 0;
+         *  ADC1 calibration voltage at atten0
+         */
+        uint32_t adc1_cal_vol_atten0:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register 6 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_cal_vol_atten0_1 : R; bitpos: [5:0]; default: 0;
+         *  ADC1 calibration voltage at atten0
+         */
+        uint32_t adc1_cal_vol_atten0_1:6;
+        /** adc1_cal_vol_atten1 : R; bitpos: [15:6]; default: 0;
+         *  ADC1 calibration voltage at atten1
+         */
+        uint32_t adc1_cal_vol_atten1:10;
+        /** adc1_cal_vol_atten2 : R; bitpos: [25:16]; default: 0;
+         *  ADC1 calibration voltage at atten2
+         */
+        uint32_t adc1_cal_vol_atten2:10;
+        /** adc1_cal_vol_atten3 : R; bitpos: [31:26]; default: 0;
+         *  ADC1 calibration voltage at atten3
+         */
+        uint32_t adc1_cal_vol_atten3:6;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register 7 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_cal_vol_atten3_1 : R; bitpos: [3:0]; default: 0;
+         *  ADC1 calibration voltage at atten3
+         */
+        uint32_t adc1_cal_vol_atten3_1:4;
+        /** reserved_2_228 : R; bitpos: [31:4]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_228:28;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register 0 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register 1 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register 2 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register 3 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register 4 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register 5 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register 6 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC address
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register 7 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC address
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register 0 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register 1 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register 2 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register 3 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register 4 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register 5 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register 6 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register 7 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register 0 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register 1 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register 2 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register 3 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register 4 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register 5 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register 6 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register 7 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register 0 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register 1 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register 2 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register 3 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register 4 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register 5 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register 6 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register 7 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register 0 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register 1 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register 2 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register 3 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register 4 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register 5 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register 6 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register 7 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register 0 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register 1 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register 2 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register 3 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register 4 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register 5 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register 6 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register 7 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register 0 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register 1 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register 2 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register 3 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register 4 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register 5 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register 6 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register 7 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register 0 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 0th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register 1 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 1st 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register 2 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 2nd 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register 3 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 3rd 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register 4 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 4th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register 5 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 5th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register 6 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 6th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register 7 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 7th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+
+/** Group: Report Register */
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  If any bit in RD_DIS is 1, then it indicates a programming error.
+         */
+        uint32_t rd_dis_err:7;
+        /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0;
+         *  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+         */
+        uint32_t dis_rtc_ram_boot_err:1;
+        /** dis_icache_err : RO; bitpos: [8]; default: 0;
+         *  If DIS_ICACHE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_icache_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  If DIS_USB_JTAG is 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** dis_download_icache_err : RO; bitpos: [10]; default: 0;
+         *  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_icache_err:1;
+        /** dis_usb_device_err : RO; bitpos: [11]; default: 0;
+         *  If DIS_USB_DEVICE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_device_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+         */
+        uint32_t dis_force_download_err:1;
+        /** rpt4_reserved6_err : RO; bitpos: [13]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved6_err:1;
+        /** dis_can_err : RO; bitpos: [14]; default: 0;
+         *  If DIS_CAN is 1, then it indicates a programming error.
+         */
+        uint32_t dis_can_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  If DIS_PAD_JTAG is 1, then it indicates a programming error.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  If any bit in USB_DREFH is 1, then it indicates a programming error.
+         */
+        uint32_t usb_drefh_err:2;
+        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
+         *  If any bit in USB_DREFL is 1, then it indicates a programming error.
+         */
+        uint32_t usb_drefl_err:2;
+        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
+         *  If USB_EXCHG_PINS is 1, then it indicates a programming error.
+         */
+        uint32_t usb_exchg_pins_err:1;
+        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
+         *  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_as_gpio_err:1;
+        /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0;
+         *  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+         */
+        uint32_t btlc_gpio_enable_err:2;
+        /** powerglitch_en_err : RO; bitpos: [29]; default: 0;
+         *  If POWERGLITCH_EN is 1, then it indicates a programming error.
+         */
+        uint32_t powerglitch_en_err:1;
+        /** power_glitch_dsense_err : RO; bitpos: [31:30]; default: 0;
+         *  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+         */
+        uint32_t power_glitch_dsense_err:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved2_err : RO; bitpos: [15:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_err:16;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** rpt4_reserved3_err : RO; bitpos: [19:16]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err:4;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  If SECURE_BOOT_EN is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        /** rpt4_reserved0_err : RO; bitpos: [27:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err:6;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0;
+         *  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+         */
+        uint32_t dis_legacy_spi_boot_err:1;
+        /** uart_print_channel_err : RO; bitpos: [2]; default: 0;
+         *  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+         */
+        uint32_t uart_print_channel_err:1;
+        /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0;
+         *  If FLASH_ECC_MODE is 1, then it indicates a programming error.
+         */
+        uint32_t flash_ecc_mode_err:1;
+        /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+         */
+        uint32_t uart_print_control_err:2;
+        /** pin_power_selection_err : RO; bitpos: [8]; default: 0;
+         *  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+         */
+        uint32_t pin_power_selection_err:1;
+        /** flash_type_err : RO; bitpos: [9]; default: 0;
+         *  If FLASH_TYPE is 1, then it indicates a programming error.
+         */
+        uint32_t flash_type_err:1;
+        /** flash_page_size_err : RO; bitpos: [11:10]; default: 0;
+         *  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+         */
+        uint32_t flash_page_size_err:2;
+        /** flash_ecc_en_err : RO; bitpos: [12]; default: 0;
+         *  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
+         *  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [29:14]; default: 0;
+         *  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+         */
+        uint32_t secure_version_err:16;
+        /** rpt4_reserved1_err : RO; bitpos: [31:30]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved1_err:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_err:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_spi_8m_err_num:3;
+        /** reserved_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t reserved_fail:1;
+        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_num:3;
+        /** mac_spi_8m_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_spi_8m_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** sys_part1_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** usr_data_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+         *  key0 failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key0_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+         *  key1 failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key1_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+         *  key2 failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key2_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+         *  key3 failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key3_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+         *  key4 failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key4_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** key5_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t efuse_mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t efuse_mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit and force to enable clock signal of eFuse memory.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register;
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+         */
+        uint32_t op_code:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/WS/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
+         *  Configures the initial read time of eFuse.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0;
+         *  Indicates the number of error bits during programming BLOCK0.
+         */
+        uint32_t repeat_err_cnt:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WO; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 33583616;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0;
+    volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1;
+    volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2;
+    volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3;
+    volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4;
+    volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    uint32_t reserved_18c;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_194[11];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    uint32_t reserved_1f8;
+    volatile efuse_date_reg_t date;
+} efuse_dev_t;
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/extmem_reg.h b/components/soc/esp32c3/register/soc/extmem_reg.h
new file mode 100644
index 00000000000..7a94ea7e66b
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/extmem_reg.h
@@ -0,0 +1,984 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_EXTMEM_REG_H_
+#define _SOC_EXTMEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define EXTMEM_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x000)
+/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to activate the data cache. 0: disable  1: enable*/
+#define EXTMEM_ICACHE_ENABLE  (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_M  (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_V  0x1
+#define EXTMEM_ICACHE_ENABLE_S  0
+
+#define EXTMEM_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x004)
+/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable core1 ibus  0: enable  1: disable*/
+#define EXTMEM_ICACHE_SHUT_DBUS  (BIT(1))
+#define EXTMEM_ICACHE_SHUT_DBUS_M  (BIT(1))
+#define EXTMEM_ICACHE_SHUT_DBUS_V  0x1
+#define EXTMEM_ICACHE_SHUT_DBUS_S  1
+/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable core0 ibus  0: enable  1: disable*/
+#define EXTMEM_ICACHE_SHUT_IBUS  (BIT(0))
+#define EXTMEM_ICACHE_SHUT_IBUS_M  (BIT(0))
+#define EXTMEM_ICACHE_SHUT_IBUS_V  0x1
+#define EXTMEM_ICACHE_SHUT_IBUS_S  0
+
+#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x008)
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power  icache tag memory up  0: follow rtc_lslp  1: power up*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU  (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S  2
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power  icache tag memory down  0: follow rtc_lslp
+  1: power down*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD  (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S  1
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of  icache tag memory.
+ 1: close gating  0: open clock gating.*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON  (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x00C)
+/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section of prelock function.*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN  (BIT(1))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V  0x1
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S  1
+/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section of prelock function.*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN  (BIT(0))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V  0x1
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x010)
+/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to configure the first start virtual address
+ of data prelock  which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x014)
+/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to configure the second start virtual address
+ of data prelock  which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x018)
+/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: The bits are used to configure the first length of data locking
+  which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE  0x0000FFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S  16
+/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the second length of data locking
+  which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE  0x0000FFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S  0
+
+#define EXTMEM_ICACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x01C)
+/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to indicate unlock/lock operation is finished.*/
+#define EXTMEM_ICACHE_LOCK_DONE  (BIT(2))
+#define EXTMEM_ICACHE_LOCK_DONE_M  (BIT(2))
+#define EXTMEM_ICACHE_LOCK_DONE_V  0x1
+#define EXTMEM_ICACHE_LOCK_DONE_S  2
+/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable unlock operation. It will be cleared
+ by hardware after unlock operation done.*/
+#define EXTMEM_ICACHE_UNLOCK_ENA  (BIT(1))
+#define EXTMEM_ICACHE_UNLOCK_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_UNLOCK_ENA_V  0x1
+#define EXTMEM_ICACHE_UNLOCK_ENA_S  1
+/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable lock operation. It will be cleared
+ by hardware after lock operation done.*/
+#define EXTMEM_ICACHE_LOCK_ENA  (BIT(0))
+#define EXTMEM_ICACHE_LOCK_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_LOCK_ENA_V  0x1
+#define EXTMEM_ICACHE_LOCK_ENA_S  0
+
+#define EXTMEM_ICACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x020)
+/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for
+ lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/
+#define EXTMEM_ICACHE_LOCK_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_LOCK_ADDR_M  ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S))
+#define EXTMEM_ICACHE_LOCK_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_LOCK_ADDR_S  0
+
+#define EXTMEM_ICACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x024)
+/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for lock operations.
+ The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
+#define EXTMEM_ICACHE_LOCK_SIZE  0x0000FFFF
+#define EXTMEM_ICACHE_LOCK_SIZE_M  ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S))
+#define EXTMEM_ICACHE_LOCK_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_LOCK_SIZE_S  0
+
+#define EXTMEM_ICACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x028)
+/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate invalidate operation is finished.*/
+#define EXTMEM_ICACHE_SYNC_DONE  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_M  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_V  0x1
+#define EXTMEM_ICACHE_SYNC_DONE_S  1
+/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable invalidate operation. It will be cleared
+ by hardware after invalidate operation done.*/
+#define EXTMEM_ICACHE_INVALIDATE_ENA  (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_V  0x1
+#define EXTMEM_ICACHE_INVALIDATE_ENA_S  0
+
+#define EXTMEM_ICACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x02C)
+/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for
+ clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/
+#define EXTMEM_ICACHE_SYNC_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_SYNC_ADDR_M  ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
+#define EXTMEM_ICACHE_SYNC_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_SYNC_ADDR_S  0
+
+#define EXTMEM_ICACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x030)
+/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
+/*description: The bits are used to configure the length for sync operations.
+ The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
+#define EXTMEM_ICACHE_SYNC_SIZE  0x007FFFFF
+#define EXTMEM_ICACHE_SYNC_SIZE_M  ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
+#define EXTMEM_ICACHE_SYNC_SIZE_V  0x7FFFFF
+#define EXTMEM_ICACHE_SYNC_SIZE_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x034)
+/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to configure the direction of preload operation.
+ 1: descending  0: ascending.*/
+#define EXTMEM_ICACHE_PRELOAD_ORDER  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_ORDER_M  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_ORDER_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_ORDER_S  2
+/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to indicate preload operation is finished.*/
+#define EXTMEM_ICACHE_PRELOAD_DONE  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_DONE_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_DONE_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_DONE_S  1
+/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable preload operation. It will be cleared
+ by hardware after preload operation done.*/
+#define EXTMEM_ICACHE_PRELOAD_ENA  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_ENA_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x038)
+/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for
+ preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/
+#define EXTMEM_ICACHE_PRELOAD_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOAD_ADDR_M  ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S))
+#define EXTMEM_ICACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOAD_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x03C)
+/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for preload operation.
+ The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
+#define EXTMEM_ICACHE_PRELOAD_SIZE  0x0000FFFF
+#define EXTMEM_ICACHE_PRELOAD_SIZE_M  ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S))
+#define EXTMEM_ICACHE_PRELOAD_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOAD_SIZE_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x040)
+/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
+/*description: The bits are used to configure trigger conditions for autoload.
+ 0/3: cache miss  1: cache hit  2: both cache miss and hit.*/
+#define EXTMEM_ICACHE_AUTOLOAD_RQST  0x00000003
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_M  ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S))
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_V  0x3
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_S  5
+/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bits are used to configure the direction of autoload. 1:
+ descending  0: ascending.*/
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER  (BIT(4))
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M  (BIT(4))
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S  4
+/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
+/*description: The bit is used to indicate autoload operation is finished.*/
+#define EXTMEM_ICACHE_AUTOLOAD_DONE  (BIT(3))
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_M  (BIT(3))
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_S  3
+/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable and disable autoload operation. It
+ is combined with icache_autoload_done. 1: enable  0: disable.*/
+#define EXTMEM_ICACHE_AUTOLOAD_ENA  (BIT(2))
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_M  (BIT(2))
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_S  2
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bits are used to enable the second section for autoload operation.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA  (BIT(1))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S  1
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bits are used to enable the first section for autoload operation.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA  (BIT(0))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x044)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of the
+ first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x048)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: The bits are used to configure the length of the first section
+ for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE  0x07FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V  0x7FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x04C)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of the
+ second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x050)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: The bits are used to configure the length of the second section
+ for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE  0x07FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V  0x7FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x054)
+/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */
+/*description: The bits are used to configure the start virtual address of ibus
+ to access flash. The register is used to give constraints to ibus access counter.*/
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S))
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S  0
+
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x058)
+/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h427FFFFF ; */
+/*description: The bits are used to configure the end virtual address of ibus
+ to access flash. The register is used to give constraints to ibus access counter.*/
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S  0
+
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x05C)
+/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C000000 ; */
+/*description: The bits are used to configure the start virtual address of dbus
+ to access flash. The register is used to give constraints to dbus access counter.*/
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S))
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S  0
+
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x060)
+/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C7FFFFF ; */
+/*description: The bits are used to configure the end virtual address of dbus
+ to access flash. The register is used to give constraints to dbus access counter.*/
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S  0
+
+#define EXTMEM_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x064)
+/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus counter.*/
+#define EXTMEM_DBUS_ACS_CNT_CLR  (BIT(1))
+#define EXTMEM_DBUS_ACS_CNT_CLR_M  (BIT(1))
+#define EXTMEM_DBUS_ACS_CNT_CLR_V  0x1
+#define EXTMEM_DBUS_ACS_CNT_CLR_S  1
+/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear ibus counter.*/
+#define EXTMEM_IBUS_ACS_CNT_CLR  (BIT(0))
+#define EXTMEM_IBUS_ACS_CNT_CLR_M  (BIT(0))
+#define EXTMEM_IBUS_ACS_CNT_CLR_V  0x1
+#define EXTMEM_IBUS_ACS_CNT_CLR_S  0
+
+#define EXTMEM_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x068)
+/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of the cache miss caused
+ by ibus access flash.*/
+#define EXTMEM_IBUS_ACS_MISS_CNT  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_MISS_CNT_M  ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S))
+#define EXTMEM_IBUS_ACS_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_MISS_CNT_S  0
+
+#define EXTMEM_IBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x06C)
+/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of ibus access flash through icache.*/
+#define EXTMEM_IBUS_ACS_CNT  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_CNT_M  ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S))
+#define EXTMEM_IBUS_ACS_CNT_V  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_CNT_S  0
+
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x070)
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of the cache miss caused
+ by dbus access flash.*/
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M  ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S  0
+
+#define EXTMEM_DBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x074)
+/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of dbus access flash through icache.*/
+#define EXTMEM_DBUS_ACS_CNT  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_CNT_M  ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S))
+#define EXTMEM_DBUS_ACS_CNT_V  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_CNT_S  0
+
+#define EXTMEM_CACHE_ILG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x078)
+/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dbus counter overflow.*/
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V  0x1
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S  8
+/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus counter overflow.*/
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V  0x1
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by mmu entry fault.*/
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by preload configurations fault.*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by sync configurations fault.*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S  0
+
+#define EXTMEM_CACHE_ILG_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x07C)
+/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dbus counter overflow.*/
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V  0x1
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S  8
+/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus counter overflow.*/
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V  0x1
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by mmu entry fault.*/
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by preload configurations fault.*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by sync configurations fault.*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S  0
+
+#define EXTMEM_CACHE_ILG_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x080)
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access flash miss
+ counter overflow.*/
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST  (BIT(10))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M  (BIT(10))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S  10
+/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access flash/spiram
+ counter overflow.*/
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST  (BIT(9))
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M  (BIT(9))
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S  9
+/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus access flash/spiram
+ miss counter overflow.*/
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST  (BIT(8))
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S  8
+/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus access flash/spiram
+ counter overflow.*/
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST  (BIT(7))
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M  (BIT(7))
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V  0x1
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S  7
+/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by mmu entry fault.*/
+#define EXTMEM_MMU_ENTRY_FAULT_ST  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_ST_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_ST_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_ST_S  5
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by preload configurations fault.*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by sync configurations fault.*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x084)
+/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dbus trying to write icache*/
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail.*/
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access icache while
+ the corresponding dbus is disabled which include speculative access.*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail.*/
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S  2
+/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus trying to write icache*/
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access icache while
+ the corresponding ibus is disabled which include speculative access.*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x088)
+/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dbus trying to write icache*/
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail.*/
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access icache while
+ the corresponding dbus is disabled or icache is disabled which include speculative access.*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail.*/
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S  2
+/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus trying to write icache*/
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access icache while
+ the corresponding ibus is disabled or icache is disabled which include speculative access.*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x08C)
+/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus trying to write icache*/
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M  (BIT(5))
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S  5
+/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail.*/
+#define EXTMEM_CORE0_DBUS_REJECT_ST  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_ST_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_ST_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access icache while
+ the core0_dbus is disabled or icache is disabled which include speculative access.*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail.*/
+#define EXTMEM_CORE0_IBUS_REJECT_ST  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_ST_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_ST_S  2
+/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus trying to write icache*/
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access  icache while
+ the core0_ibus is disabled or icache is disabled which include speculative access.*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S  0
+
+#define EXTMEM_CORE0_DBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x090)
+/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access dbus when
+ authentication fail. 0: WORLD0  1: WORLD1*/
+#define EXTMEM_CORE0_DBUS_WORLD  (BIT(3))
+#define EXTMEM_CORE0_DBUS_WORLD_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_WORLD_V  0x1
+#define EXTMEM_CORE0_DBUS_WORLD_S  3
+/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access dbus
+ when authentication fail. 0: invalidate  1: execute-able  2: read-able  4: write-able.*/
+#define EXTMEM_CORE0_DBUS_ATTR  0x00000007
+#define EXTMEM_CORE0_DBUS_ATTR_M  ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
+#define EXTMEM_CORE0_DBUS_ATTR_V  0x7
+#define EXTMEM_CORE0_DBUS_ATTR_S  0
+
+#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x094)
+/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access
+ dbus when authentication fail.*/
+#define EXTMEM_CORE0_DBUS_VADDR  0xFFFFFFFF
+#define EXTMEM_CORE0_DBUS_VADDR_M  ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
+#define EXTMEM_CORE0_DBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE0_DBUS_VADDR_S  0
+
+#define EXTMEM_CORE0_IBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x098)
+/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access ibus when
+ authentication fail. 0: WORLD0  1: WORLD1*/
+#define EXTMEM_CORE0_IBUS_WORLD  (BIT(3))
+#define EXTMEM_CORE0_IBUS_WORLD_M  (BIT(3))
+#define EXTMEM_CORE0_IBUS_WORLD_V  0x1
+#define EXTMEM_CORE0_IBUS_WORLD_S  3
+/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access ibus
+ when authentication fail. 0: invalidate  1: execute-able  2: read-able*/
+#define EXTMEM_CORE0_IBUS_ATTR  0x00000007
+#define EXTMEM_CORE0_IBUS_ATTR_M  ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S))
+#define EXTMEM_CORE0_IBUS_ATTR_V  0x7
+#define EXTMEM_CORE0_IBUS_ATTR_S  0
+
+#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x09C)
+/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access
+  ibus when authentication fail.*/
+#define EXTMEM_CORE0_IBUS_VADDR  0xFFFFFFFF
+#define EXTMEM_CORE0_IBUS_VADDR_M  ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
+#define EXTMEM_CORE0_IBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE0_IBUS_VADDR_S  0
+
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x0A0)
+/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */
+/*description: The right-most 3 bits are used to indicate the operations which
+ cause mmu fault occurrence. 0: default  1: cpu miss  2: preload miss  3: writeback  4: cpu miss evict recovery address  5: load miss evict recovery address  6: external dma tx  7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/
+#define EXTMEM_CACHE_MMU_FAULT_CODE  0x0000000F
+#define EXTMEM_CACHE_MMU_FAULT_CODE_M  ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S))
+#define EXTMEM_CACHE_MMU_FAULT_CODE_V  0xF
+#define EXTMEM_CACHE_MMU_FAULT_CODE_S  10
+/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT  0x000003FF
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M  ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V  0x3FF
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S  0
+
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x0A4)
+/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to indicate the virtual address which cause mmu fault..*/
+#define EXTMEM_CACHE_MMU_FAULT_VADDR  0xFFFFFFFF
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_M  ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_S  0
+
+#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0A8)
+/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable wrap around mode when read data from flash.*/
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND  (BIT(0))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V  0x1
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S  0
+
+#define EXTMEM_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0AC)
+/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power up*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU  (BIT(2))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S  2
+/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power mmu memory down  0: follow_rtc_lslp_pd  1: power down*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD  (BIT(1))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S  1
+/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable clock gating to save power when access
+ mmu memory  0: enable  1: disable*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON  (BIT(0))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S  0
+
+#define EXTMEM_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x0B0)
+/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */
+/*description: The bit is used to indicate whether  icache main fsm is in idle
+ state or not. 1: in idle state   0: not in idle state*/
+#define EXTMEM_ICACHE_STATE  0x00000FFF
+#define EXTMEM_ICACHE_STATE_M  ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
+#define EXTMEM_ICACHE_STATE_V  0xFFF
+#define EXTMEM_ICACHE_STATE_S  0
+
+#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0x0B4)
+/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Reserved.*/
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT  (BIT(1))
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S  1
+/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Reserved.*/
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT  (BIT(0))
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V  0x1
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S  0
+
+#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0x0B8)
+/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of external memory encrypt
+ and decrypt clock. 1: close gating  0: open clock gating.*/
+#define EXTMEM_CLK_FORCE_ON_CRYPT  (BIT(2))
+#define EXTMEM_CLK_FORCE_ON_CRYPT_M  (BIT(2))
+#define EXTMEM_CLK_FORCE_ON_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_CRYPT_S  2
+/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of automatic crypt clock.
+ 1: close gating  0: open clock gating.*/
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT  (BIT(1))
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M  (BIT(1))
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S  1
+/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of manual crypt clock.
+ 1: close gating  0: open clock gating.*/
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT  (BIT(0))
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M  (BIT(0))
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S  0
+
+#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0BC)
+/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by  icache pre-load done.*/
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S  2
+/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by  icache pre-load done.*/
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S  1
+/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by  icache pre-load done.*/
+#define EXTMEM_ICACHE_PRELOAD_INT_ST  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_S  0
+
+#define EXTMEM_CACHE_SYNC_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0C0)
+/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by  icache sync done.*/
+#define EXTMEM_ICACHE_SYNC_INT_CLR  (BIT(2))
+#define EXTMEM_ICACHE_SYNC_INT_CLR_M  (BIT(2))
+#define EXTMEM_ICACHE_SYNC_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_CLR_S  2
+/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by  icache sync done.*/
+#define EXTMEM_ICACHE_SYNC_INT_ENA  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_ENA_S  1
+/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by  icache sync done.*/
+#define EXTMEM_ICACHE_SYNC_INT_ST  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_INT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_INT_ST_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_ST_S  0
+
+#define EXTMEM_CACHE_MMU_OWNER_REG          (DR_REG_EXTMEM_BASE + 0x0C4)
+/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus  bit1/bit3: dbus*/
+#define EXTMEM_CACHE_MMU_OWNER  0x0000000F
+#define EXTMEM_CACHE_MMU_OWNER_M  ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
+#define EXTMEM_CACHE_MMU_OWNER_V  0xF
+#define EXTMEM_CACHE_MMU_OWNER_S  0
+
+#define EXTMEM_CACHE_CONF_MISC_REG          (DR_REG_EXTMEM_BASE + 0x0C8)
+/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to enable cache trace function.*/
+#define EXTMEM_CACHE_TRACE_ENA  (BIT(2))
+#define EXTMEM_CACHE_TRACE_ENA_M  (BIT(2))
+#define EXTMEM_CACHE_TRACE_ENA_V  0x1
+#define EXTMEM_CACHE_TRACE_ENA_S  2
+/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable checking mmu entry fault by sync operation.*/
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT  (BIT(1))
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M  (BIT(1))
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V  0x1
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S  1
+/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable checking mmu entry fault by preload operation.*/
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT  (BIT(0))
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M  (BIT(0))
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V  0x1
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S  0
+
+#define EXTMEM_ICACHE_FREEZE_REG          (DR_REG_EXTMEM_BASE + 0x0CC)
+/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate icache freeze success*/
+#define EXTMEM_ICACHE_FREEZE_DONE  (BIT(2))
+#define EXTMEM_ICACHE_FREEZE_DONE_M  (BIT(2))
+#define EXTMEM_ICACHE_FREEZE_DONE_V  0x1
+#define EXTMEM_ICACHE_FREEZE_DONE_S  2
+/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to configure freeze mode  0:  assert busy if
+ CPU miss 1: assert hit if CPU miss*/
+#define EXTMEM_ICACHE_FREEZE_MODE  (BIT(1))
+#define EXTMEM_ICACHE_FREEZE_MODE_M  (BIT(1))
+#define EXTMEM_ICACHE_FREEZE_MODE_V  0x1
+#define EXTMEM_ICACHE_FREEZE_MODE_S  1
+/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable icache freeze mode*/
+#define EXTMEM_ICACHE_FREEZE_ENA  (BIT(0))
+#define EXTMEM_ICACHE_FREEZE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_FREEZE_ENA_V  0x1
+#define EXTMEM_ICACHE_FREEZE_ENA_S  0
+
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG          (DR_REG_EXTMEM_BASE + 0x0D0)
+/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to activate icache atomic operation protection.
+ In this case  sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA  (BIT(0))
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V  0x1
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S  0
+
+#define EXTMEM_CACHE_REQUEST_REG          (DR_REG_EXTMEM_BASE + 0x0D4)
+/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to disable request recording which could cause performance issue*/
+#define EXTMEM_CACHE_REQUEST_BYPASS  (BIT(0))
+#define EXTMEM_CACHE_REQUEST_BYPASS_M  (BIT(0))
+#define EXTMEM_CACHE_REQUEST_BYPASS_V  0x1
+#define EXTMEM_CACHE_REQUEST_BYPASS_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_LOCK_REG          (DR_REG_EXTMEM_BASE + 0x0D8)
+/* EXTMEM_IBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to configure the ibus permission control section boundary0*/
+#define EXTMEM_IBUS_PMS_LOCK  (BIT(0))
+#define EXTMEM_IBUS_PMS_LOCK_M  (BIT(0))
+#define EXTMEM_IBUS_PMS_LOCK_V  0x1
+#define EXTMEM_IBUS_PMS_LOCK_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_BOUNDARY0_REG          (DR_REG_EXTMEM_BASE + 0x0DC)
+/* EXTMEM_IBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: The bit is used to configure the ibus permission control section boundary0*/
+#define EXTMEM_IBUS_PMS_BOUNDARY0  0x00000FFF
+#define EXTMEM_IBUS_PMS_BOUNDARY0_M  ((EXTMEM_IBUS_PMS_BOUNDARY0_V)<<(EXTMEM_IBUS_PMS_BOUNDARY0_S))
+#define EXTMEM_IBUS_PMS_BOUNDARY0_V  0xFFF
+#define EXTMEM_IBUS_PMS_BOUNDARY0_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_BOUNDARY1_REG          (DR_REG_EXTMEM_BASE + 0x0E0)
+/* EXTMEM_IBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: The bit is used to configure the ibus permission control section boundary1*/
+#define EXTMEM_IBUS_PMS_BOUNDARY1  0x00000FFF
+#define EXTMEM_IBUS_PMS_BOUNDARY1_M  ((EXTMEM_IBUS_PMS_BOUNDARY1_V)<<(EXTMEM_IBUS_PMS_BOUNDARY1_S))
+#define EXTMEM_IBUS_PMS_BOUNDARY1_V  0xFFF
+#define EXTMEM_IBUS_PMS_BOUNDARY1_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_BOUNDARY2_REG          (DR_REG_EXTMEM_BASE + 0x0E4)
+/* EXTMEM_IBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: The bit is used to configure the ibus permission control section boundary2*/
+#define EXTMEM_IBUS_PMS_BOUNDARY2  0x00000FFF
+#define EXTMEM_IBUS_PMS_BOUNDARY2_M  ((EXTMEM_IBUS_PMS_BOUNDARY2_V)<<(EXTMEM_IBUS_PMS_BOUNDARY2_S))
+#define EXTMEM_IBUS_PMS_BOUNDARY2_V  0xFFF
+#define EXTMEM_IBUS_PMS_BOUNDARY2_S  0
+
+#define EXTMEM_IBUS_PMS_TBL_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x0E8)
+/* EXTMEM_IBUS_PMS_SCT2_ATTR : R/W ;bitpos:[7:4] ;default: 4'hF ; */
+/*description: The bit is used to configure attribute of the ibus permission
+ control section2  bit0: fetch in world0  bit1: load in world0  bit2: fetch in world1  bit3: load in world1*/
+#define EXTMEM_IBUS_PMS_SCT2_ATTR  0x0000000F
+#define EXTMEM_IBUS_PMS_SCT2_ATTR_M  ((EXTMEM_IBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT2_ATTR_S))
+#define EXTMEM_IBUS_PMS_SCT2_ATTR_V  0xF
+#define EXTMEM_IBUS_PMS_SCT2_ATTR_S  4
+/* EXTMEM_IBUS_PMS_SCT1_ATTR : R/W ;bitpos:[3:0] ;default: 4'hF ; */
+/*description: The bit is used to configure attribute of the ibus permission
+ control section1  bit0: fetch in world0  bit1: load in world0  bit2: fetch in world1  bit3: load in world1*/
+#define EXTMEM_IBUS_PMS_SCT1_ATTR  0x0000000F
+#define EXTMEM_IBUS_PMS_SCT1_ATTR_M  ((EXTMEM_IBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT1_ATTR_S))
+#define EXTMEM_IBUS_PMS_SCT1_ATTR_V  0xF
+#define EXTMEM_IBUS_PMS_SCT1_ATTR_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_LOCK_REG          (DR_REG_EXTMEM_BASE + 0x0EC)
+/* EXTMEM_DBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to configure the ibus permission control section boundary0*/
+#define EXTMEM_DBUS_PMS_LOCK  (BIT(0))
+#define EXTMEM_DBUS_PMS_LOCK_M  (BIT(0))
+#define EXTMEM_DBUS_PMS_LOCK_V  0x1
+#define EXTMEM_DBUS_PMS_LOCK_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_BOUNDARY0_REG          (DR_REG_EXTMEM_BASE + 0x0F0)
+/* EXTMEM_DBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: The bit is used to configure the dbus permission control section boundary0*/
+#define EXTMEM_DBUS_PMS_BOUNDARY0  0x00000FFF
+#define EXTMEM_DBUS_PMS_BOUNDARY0_M  ((EXTMEM_DBUS_PMS_BOUNDARY0_V)<<(EXTMEM_DBUS_PMS_BOUNDARY0_S))
+#define EXTMEM_DBUS_PMS_BOUNDARY0_V  0xFFF
+#define EXTMEM_DBUS_PMS_BOUNDARY0_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_BOUNDARY1_REG          (DR_REG_EXTMEM_BASE + 0x0F4)
+/* EXTMEM_DBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: The bit is used to configure the dbus permission control section boundary1*/
+#define EXTMEM_DBUS_PMS_BOUNDARY1  0x00000FFF
+#define EXTMEM_DBUS_PMS_BOUNDARY1_M  ((EXTMEM_DBUS_PMS_BOUNDARY1_V)<<(EXTMEM_DBUS_PMS_BOUNDARY1_S))
+#define EXTMEM_DBUS_PMS_BOUNDARY1_V  0xFFF
+#define EXTMEM_DBUS_PMS_BOUNDARY1_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_BOUNDARY2_REG          (DR_REG_EXTMEM_BASE + 0x0F8)
+/* EXTMEM_DBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
+/*description: The bit is used to configure the dbus permission control section boundary2*/
+#define EXTMEM_DBUS_PMS_BOUNDARY2  0x00000FFF
+#define EXTMEM_DBUS_PMS_BOUNDARY2_M  ((EXTMEM_DBUS_PMS_BOUNDARY2_V)<<(EXTMEM_DBUS_PMS_BOUNDARY2_S))
+#define EXTMEM_DBUS_PMS_BOUNDARY2_V  0xFFF
+#define EXTMEM_DBUS_PMS_BOUNDARY2_S  0
+
+#define EXTMEM_DBUS_PMS_TBL_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x0FC)
+/* EXTMEM_DBUS_PMS_SCT2_ATTR : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+/*description: The bit is used to configure attribute of the dbus permission
+ control section2  bit0: load in world0  bit2: load in world1*/
+#define EXTMEM_DBUS_PMS_SCT2_ATTR  0x00000003
+#define EXTMEM_DBUS_PMS_SCT2_ATTR_M  ((EXTMEM_DBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT2_ATTR_S))
+#define EXTMEM_DBUS_PMS_SCT2_ATTR_V  0x3
+#define EXTMEM_DBUS_PMS_SCT2_ATTR_S  2
+/* EXTMEM_DBUS_PMS_SCT1_ATTR : R/W ;bitpos:[1:0] ;default: 2'd3 ; */
+/*description: The bit is used to configure attribute of the dbus permission
+ control section1  bit0: load in world0  bit2: load in world1*/
+#define EXTMEM_DBUS_PMS_SCT1_ATTR  0x00000003
+#define EXTMEM_DBUS_PMS_SCT1_ATTR_M  ((EXTMEM_DBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT1_ATTR_S))
+#define EXTMEM_DBUS_PMS_SCT1_ATTR_V  0x3
+#define EXTMEM_DBUS_PMS_SCT1_ATTR_S  0
+
+#define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x100)
+/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Reserved.*/
+#define EXTMEM_CLK_EN  (BIT(0))
+#define EXTMEM_CLK_EN_M  (BIT(0))
+#define EXTMEM_CLK_EN_V  0x1
+#define EXTMEM_CLK_EN_S  0
+
+#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
+/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007160 ; */
+/*description: Reserved.*/
+#define EXTMEM_DATE  0x0FFFFFFF
+#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
+#define EXTMEM_DATE_V  0xFFFFFFF
+#define EXTMEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EXTMEM_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/gdma_reg.h b/components/soc/esp32c3/register/soc/gdma_reg.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/gdma_reg.h
rename to components/soc/esp32c3/register/soc/gdma_reg.h
diff --git a/components/soc/esp32c3/include/soc/gdma_struct.h b/components/soc/esp32c3/register/soc/gdma_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/gdma_struct.h
rename to components/soc/esp32c3/register/soc/gdma_struct.h
diff --git a/components/soc/esp32c3/register/soc/gpio_reg.h b/components/soc/esp32c3/register/soc/gpio_reg.h
new file mode 100644
index 00000000000..b92e195e36d
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/gpio_reg.h
@@ -0,0 +1,4580 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_GPIO_REG_H_
+#define _SOC_GPIO_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define GPIO_PIN_CONFIG_MSB                    12
+#define GPIO_PIN_CONFIG_LSB                     11
+#define GPIO_PIN_CONFIG_MASK                   0x00001800
+#define GPIO_PIN_CONFIG_GET(x)                 (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_CONFIG_SET(x)                  (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
+
+#define GPIO_WAKEUP_ENABLE                     1
+#define GPIO_WAKEUP_DISABLE                    (~GPIO_WAKEUP_ENABLE)
+#define GPIO_PIN_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
+
+#define GPIO_PIN_INT_TYPE_MASK                 0x380
+#define GPIO_PIN_INT_TYPE_MSB                  9
+#define GPIO_PIN_INT_TYPE_LSB                  7
+#define GPIO_PIN_INT_TYPE_GET(x)               (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_INT_TYPE_SET(x)               (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
+
+#define GPIO_PAD_DRIVER_ENABLE                 1
+#define GPIO_PAD_DRIVER_DISABLE                        (~GPIO_PAD_DRIVER_ENABLE)
+#define GPIO_PIN_PAD_DRIVER_MSB                        2
+#define GPIO_PIN_PAD_DRIVER_LSB                        2
+#define GPIO_PIN_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
+#define GPIO_PIN_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
+
+#define GPIO_BT_SELECT_REG          (DR_REG_GPIO_BASE + 0x0)
+/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_BT_SEL  0xFFFFFFFF
+#define GPIO_BT_SEL_M  ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
+#define GPIO_BT_SEL_V  0xFFFFFFFF
+#define GPIO_BT_SEL_S  0
+
+#define GPIO_OUT_REG          (DR_REG_GPIO_BASE + 0x4)
+/* GPIO_OUT_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_OUT_DATA  0x03FFFFFF
+#define GPIO_OUT_DATA_M  ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
+#define GPIO_OUT_DATA_V  0x3FFFFFF
+#define GPIO_OUT_DATA_S  0
+
+#define GPIO_OUT_W1TS_REG          (DR_REG_GPIO_BASE + 0x8)
+/* GPIO_OUT_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_OUT_W1TS  0x03FFFFFF
+#define GPIO_OUT_W1TS_M  ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S))
+#define GPIO_OUT_W1TS_V  0x3FFFFFF
+#define GPIO_OUT_W1TS_S  0
+
+#define GPIO_OUT_W1TC_REG          (DR_REG_GPIO_BASE + 0xC)
+/* GPIO_OUT_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_OUT_W1TC  0x03FFFFFF
+#define GPIO_OUT_W1TC_M  ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S))
+#define GPIO_OUT_W1TC_V  0x3FFFFFF
+#define GPIO_OUT_W1TC_S  0
+
+#define GPIO_SDIO_SELECT_REG          (DR_REG_GPIO_BASE + 0x1C)
+/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SDIO_SEL  0x000000FF
+#define GPIO_SDIO_SEL_M  ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
+#define GPIO_SDIO_SEL_V  0xFF
+#define GPIO_SDIO_SEL_S  0
+
+#define GPIO_ENABLE_REG          (DR_REG_GPIO_BASE + 0x20)
+/* GPIO_ENABLE_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_ENABLE_DATA  0x03FFFFFF
+#define GPIO_ENABLE_DATA_M  ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
+#define GPIO_ENABLE_DATA_V  0x3FFFFFF
+#define GPIO_ENABLE_DATA_S  0
+
+#define GPIO_ENABLE_W1TS_REG          (DR_REG_GPIO_BASE + 0x24)
+/* GPIO_ENABLE_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_ENABLE_W1TS  0x03FFFFFF
+#define GPIO_ENABLE_W1TS_M  ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S))
+#define GPIO_ENABLE_W1TS_V  0x3FFFFFF
+#define GPIO_ENABLE_W1TS_S  0
+
+#define GPIO_ENABLE_W1TC_REG          (DR_REG_GPIO_BASE + 0x28)
+/* GPIO_ENABLE_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_ENABLE_W1TC  0x03FFFFFF
+#define GPIO_ENABLE_W1TC_M  ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S))
+#define GPIO_ENABLE_W1TC_V  0x3FFFFFF
+#define GPIO_ENABLE_W1TC_S  0
+
+#define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x38)
+/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
+/*description: */
+#define GPIO_STRAPPING  0x0000FFFF
+#define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
+#define GPIO_STRAPPING_V  0xFFFF
+#define GPIO_STRAPPING_S  0
+
+#define GPIO_IN_REG          (DR_REG_GPIO_BASE + 0x3C)
+/* GPIO_IN_DATA : RO ;bitpos:[25:0] ;default:  ; */
+/*description: */
+#define GPIO_IN_DATA  0x03FFFFFF
+#define GPIO_IN_DATA_M  ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
+#define GPIO_IN_DATA_V  0x3FFFFFF
+#define GPIO_IN_DATA_S  0
+
+#define GPIO_STATUS_REG          (DR_REG_GPIO_BASE + 0x44)
+/* GPIO_STATUS_INT : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_STATUS_INT  0x03FFFFFF
+#define GPIO_STATUS_INT_M  ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
+#define GPIO_STATUS_INT_V  0x3FFFFFF
+#define GPIO_STATUS_INT_S  0
+
+#define GPIO_STATUS_W1TS_REG          (DR_REG_GPIO_BASE + 0x48)
+/* GPIO_STATUS_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_STATUS_W1TS  0x03FFFFFF
+#define GPIO_STATUS_W1TS_M  ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S))
+#define GPIO_STATUS_W1TS_V  0x3FFFFFF
+#define GPIO_STATUS_W1TS_S  0
+
+#define GPIO_STATUS_W1TC_REG          (DR_REG_GPIO_BASE + 0x4C)
+/* GPIO_STATUS_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_STATUS_W1TC  0x03FFFFFF
+#define GPIO_STATUS_W1TC_M  ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S))
+#define GPIO_STATUS_W1TC_V  0x3FFFFFF
+#define GPIO_STATUS_W1TC_S  0
+
+#define GPIO_PCPU_INT_REG          (DR_REG_GPIO_BASE + 0x5C)
+/* GPIO_PROCPU_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_PROCPU_INT  0x03FFFFFF
+#define GPIO_PROCPU_INT_M  ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
+#define GPIO_PROCPU_INT_V  0x3FFFFFF
+#define GPIO_PROCPU_INT_S  0
+
+#define GPIO_PCPU_NMI_INT_REG          (DR_REG_GPIO_BASE + 0x60)
+/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_PROCPU_NMI_INT  0x03FFFFFF
+#define GPIO_PROCPU_NMI_INT_M  ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
+#define GPIO_PROCPU_NMI_INT_V  0x3FFFFFF
+#define GPIO_PROCPU_NMI_INT_S  0
+
+#define GPIO_CPUSDIO_INT_REG          (DR_REG_GPIO_BASE + 0x64)
+/* GPIO_SDIO_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_SDIO_INT  0x03FFFFFF
+#define GPIO_SDIO_INT_M  ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
+#define GPIO_SDIO_INT_V  0x3FFFFFF
+#define GPIO_SDIO_INT_S  0
+
+#define GPIO_PIN0_REG          (DR_REG_GPIO_BASE + 0x74)
+/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN0_INT_ENA  0x0000001F
+#define GPIO_PIN0_INT_ENA_M  ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
+#define GPIO_PIN0_INT_ENA_V  0x1F
+#define GPIO_PIN0_INT_ENA_S  13
+/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_CONFIG  0x00000003
+#define GPIO_PIN0_CONFIG_M  ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
+#define GPIO_PIN0_CONFIG_V  0x3
+#define GPIO_PIN0_CONFIG_S  11
+/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN0_INT_TYPE  0x00000007
+#define GPIO_PIN0_INT_TYPE_M  ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
+#define GPIO_PIN0_INT_TYPE_V  0x7
+#define GPIO_PIN0_INT_TYPE_S  7
+/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN0_SYNC1_BYPASS_M  ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN0_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_V  0x1
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN0_SYNC2_BYPASS_M  ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S))
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN1_REG          (DR_REG_GPIO_BASE + 0x78)
+/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN1_INT_ENA  0x0000001F
+#define GPIO_PIN1_INT_ENA_M  ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
+#define GPIO_PIN1_INT_ENA_V  0x1F
+#define GPIO_PIN1_INT_ENA_S  13
+/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_CONFIG  0x00000003
+#define GPIO_PIN1_CONFIG_M  ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
+#define GPIO_PIN1_CONFIG_V  0x3
+#define GPIO_PIN1_CONFIG_S  11
+/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN1_INT_TYPE  0x00000007
+#define GPIO_PIN1_INT_TYPE_M  ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
+#define GPIO_PIN1_INT_TYPE_V  0x7
+#define GPIO_PIN1_INT_TYPE_S  7
+/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN1_SYNC1_BYPASS_M  ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S))
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN1_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_V  0x1
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN1_SYNC2_BYPASS_M  ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S))
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN2_REG          (DR_REG_GPIO_BASE + 0x7C)
+/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN2_INT_ENA  0x0000001F
+#define GPIO_PIN2_INT_ENA_M  ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
+#define GPIO_PIN2_INT_ENA_V  0x1F
+#define GPIO_PIN2_INT_ENA_S  13
+/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_CONFIG  0x00000003
+#define GPIO_PIN2_CONFIG_M  ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
+#define GPIO_PIN2_CONFIG_V  0x3
+#define GPIO_PIN2_CONFIG_S  11
+/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN2_INT_TYPE  0x00000007
+#define GPIO_PIN2_INT_TYPE_M  ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
+#define GPIO_PIN2_INT_TYPE_V  0x7
+#define GPIO_PIN2_INT_TYPE_S  7
+/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN2_SYNC1_BYPASS_M  ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S))
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN2_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_V  0x1
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN2_SYNC2_BYPASS_M  ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S))
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN3_REG          (DR_REG_GPIO_BASE + 0x80)
+/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN3_INT_ENA  0x0000001F
+#define GPIO_PIN3_INT_ENA_M  ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
+#define GPIO_PIN3_INT_ENA_V  0x1F
+#define GPIO_PIN3_INT_ENA_S  13
+/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_CONFIG  0x00000003
+#define GPIO_PIN3_CONFIG_M  ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
+#define GPIO_PIN3_CONFIG_V  0x3
+#define GPIO_PIN3_CONFIG_S  11
+/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN3_INT_TYPE  0x00000007
+#define GPIO_PIN3_INT_TYPE_M  ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
+#define GPIO_PIN3_INT_TYPE_V  0x7
+#define GPIO_PIN3_INT_TYPE_S  7
+/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN3_SYNC1_BYPASS_M  ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S))
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN3_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_V  0x1
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN3_SYNC2_BYPASS_M  ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S))
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN4_REG          (DR_REG_GPIO_BASE + 0x84)
+/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN4_INT_ENA  0x0000001F
+#define GPIO_PIN4_INT_ENA_M  ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
+#define GPIO_PIN4_INT_ENA_V  0x1F
+#define GPIO_PIN4_INT_ENA_S  13
+/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_CONFIG  0x00000003
+#define GPIO_PIN4_CONFIG_M  ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
+#define GPIO_PIN4_CONFIG_V  0x3
+#define GPIO_PIN4_CONFIG_S  11
+/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN4_INT_TYPE  0x00000007
+#define GPIO_PIN4_INT_TYPE_M  ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
+#define GPIO_PIN4_INT_TYPE_V  0x7
+#define GPIO_PIN4_INT_TYPE_S  7
+/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN4_SYNC1_BYPASS_M  ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S))
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN4_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_V  0x1
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN4_SYNC2_BYPASS_M  ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S))
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN5_REG          (DR_REG_GPIO_BASE + 0x88)
+/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN5_INT_ENA  0x0000001F
+#define GPIO_PIN5_INT_ENA_M  ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
+#define GPIO_PIN5_INT_ENA_V  0x1F
+#define GPIO_PIN5_INT_ENA_S  13
+/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_CONFIG  0x00000003
+#define GPIO_PIN5_CONFIG_M  ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
+#define GPIO_PIN5_CONFIG_V  0x3
+#define GPIO_PIN5_CONFIG_S  11
+/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN5_INT_TYPE  0x00000007
+#define GPIO_PIN5_INT_TYPE_M  ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
+#define GPIO_PIN5_INT_TYPE_V  0x7
+#define GPIO_PIN5_INT_TYPE_S  7
+/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN5_SYNC1_BYPASS_M  ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S))
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN5_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_V  0x1
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN5_SYNC2_BYPASS_M  ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S))
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN6_REG          (DR_REG_GPIO_BASE + 0x8C)
+/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN6_INT_ENA  0x0000001F
+#define GPIO_PIN6_INT_ENA_M  ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
+#define GPIO_PIN6_INT_ENA_V  0x1F
+#define GPIO_PIN6_INT_ENA_S  13
+/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_CONFIG  0x00000003
+#define GPIO_PIN6_CONFIG_M  ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
+#define GPIO_PIN6_CONFIG_V  0x3
+#define GPIO_PIN6_CONFIG_S  11
+/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN6_INT_TYPE  0x00000007
+#define GPIO_PIN6_INT_TYPE_M  ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
+#define GPIO_PIN6_INT_TYPE_V  0x7
+#define GPIO_PIN6_INT_TYPE_S  7
+/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN6_SYNC1_BYPASS_M  ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S))
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN6_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_V  0x1
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN6_SYNC2_BYPASS_M  ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S))
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN7_REG          (DR_REG_GPIO_BASE + 0x90)
+/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN7_INT_ENA  0x0000001F
+#define GPIO_PIN7_INT_ENA_M  ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
+#define GPIO_PIN7_INT_ENA_V  0x1F
+#define GPIO_PIN7_INT_ENA_S  13
+/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_CONFIG  0x00000003
+#define GPIO_PIN7_CONFIG_M  ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
+#define GPIO_PIN7_CONFIG_V  0x3
+#define GPIO_PIN7_CONFIG_S  11
+/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN7_INT_TYPE  0x00000007
+#define GPIO_PIN7_INT_TYPE_M  ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
+#define GPIO_PIN7_INT_TYPE_V  0x7
+#define GPIO_PIN7_INT_TYPE_S  7
+/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN7_SYNC1_BYPASS_M  ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S))
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN7_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_V  0x1
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN7_SYNC2_BYPASS_M  ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S))
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN8_REG          (DR_REG_GPIO_BASE + 0x94)
+/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN8_INT_ENA  0x0000001F
+#define GPIO_PIN8_INT_ENA_M  ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
+#define GPIO_PIN8_INT_ENA_V  0x1F
+#define GPIO_PIN8_INT_ENA_S  13
+/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_CONFIG  0x00000003
+#define GPIO_PIN8_CONFIG_M  ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
+#define GPIO_PIN8_CONFIG_V  0x3
+#define GPIO_PIN8_CONFIG_S  11
+/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN8_INT_TYPE  0x00000007
+#define GPIO_PIN8_INT_TYPE_M  ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
+#define GPIO_PIN8_INT_TYPE_V  0x7
+#define GPIO_PIN8_INT_TYPE_S  7
+/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN8_SYNC1_BYPASS_M  ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S))
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN8_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_V  0x1
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN8_SYNC2_BYPASS_M  ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S))
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN9_REG          (DR_REG_GPIO_BASE + 0x98)
+/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN9_INT_ENA  0x0000001F
+#define GPIO_PIN9_INT_ENA_M  ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
+#define GPIO_PIN9_INT_ENA_V  0x1F
+#define GPIO_PIN9_INT_ENA_S  13
+/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_CONFIG  0x00000003
+#define GPIO_PIN9_CONFIG_M  ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
+#define GPIO_PIN9_CONFIG_V  0x3
+#define GPIO_PIN9_CONFIG_S  11
+/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN9_INT_TYPE  0x00000007
+#define GPIO_PIN9_INT_TYPE_M  ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
+#define GPIO_PIN9_INT_TYPE_V  0x7
+#define GPIO_PIN9_INT_TYPE_S  7
+/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN9_SYNC1_BYPASS_M  ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S))
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN9_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_V  0x1
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN9_SYNC2_BYPASS_M  ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S))
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN10_REG          (DR_REG_GPIO_BASE + 0x9C)
+/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN10_INT_ENA  0x0000001F
+#define GPIO_PIN10_INT_ENA_M  ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
+#define GPIO_PIN10_INT_ENA_V  0x1F
+#define GPIO_PIN10_INT_ENA_S  13
+/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_CONFIG  0x00000003
+#define GPIO_PIN10_CONFIG_M  ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
+#define GPIO_PIN10_CONFIG_V  0x3
+#define GPIO_PIN10_CONFIG_S  11
+/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN10_INT_TYPE  0x00000007
+#define GPIO_PIN10_INT_TYPE_M  ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
+#define GPIO_PIN10_INT_TYPE_V  0x7
+#define GPIO_PIN10_INT_TYPE_S  7
+/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN10_SYNC1_BYPASS_M  ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S))
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN10_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_V  0x1
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN10_SYNC2_BYPASS_M  ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S))
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN11_REG          (DR_REG_GPIO_BASE + 0xA0)
+/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN11_INT_ENA  0x0000001F
+#define GPIO_PIN11_INT_ENA_M  ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
+#define GPIO_PIN11_INT_ENA_V  0x1F
+#define GPIO_PIN11_INT_ENA_S  13
+/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_CONFIG  0x00000003
+#define GPIO_PIN11_CONFIG_M  ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
+#define GPIO_PIN11_CONFIG_V  0x3
+#define GPIO_PIN11_CONFIG_S  11
+/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN11_INT_TYPE  0x00000007
+#define GPIO_PIN11_INT_TYPE_M  ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
+#define GPIO_PIN11_INT_TYPE_V  0x7
+#define GPIO_PIN11_INT_TYPE_S  7
+/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN11_SYNC1_BYPASS_M  ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S))
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN11_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_V  0x1
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN11_SYNC2_BYPASS_M  ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S))
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN12_REG          (DR_REG_GPIO_BASE + 0xA4)
+/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN12_INT_ENA  0x0000001F
+#define GPIO_PIN12_INT_ENA_M  ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
+#define GPIO_PIN12_INT_ENA_V  0x1F
+#define GPIO_PIN12_INT_ENA_S  13
+/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_CONFIG  0x00000003
+#define GPIO_PIN12_CONFIG_M  ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
+#define GPIO_PIN12_CONFIG_V  0x3
+#define GPIO_PIN12_CONFIG_S  11
+/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN12_INT_TYPE  0x00000007
+#define GPIO_PIN12_INT_TYPE_M  ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
+#define GPIO_PIN12_INT_TYPE_V  0x7
+#define GPIO_PIN12_INT_TYPE_S  7
+/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN12_SYNC1_BYPASS_M  ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S))
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN12_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_V  0x1
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN12_SYNC2_BYPASS_M  ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S))
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN13_REG          (DR_REG_GPIO_BASE + 0xA8)
+/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN13_INT_ENA  0x0000001F
+#define GPIO_PIN13_INT_ENA_M  ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
+#define GPIO_PIN13_INT_ENA_V  0x1F
+#define GPIO_PIN13_INT_ENA_S  13
+/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_CONFIG  0x00000003
+#define GPIO_PIN13_CONFIG_M  ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
+#define GPIO_PIN13_CONFIG_V  0x3
+#define GPIO_PIN13_CONFIG_S  11
+/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN13_INT_TYPE  0x00000007
+#define GPIO_PIN13_INT_TYPE_M  ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
+#define GPIO_PIN13_INT_TYPE_V  0x7
+#define GPIO_PIN13_INT_TYPE_S  7
+/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN13_SYNC1_BYPASS_M  ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S))
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN13_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_V  0x1
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN13_SYNC2_BYPASS_M  ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S))
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN14_REG          (DR_REG_GPIO_BASE + 0xAC)
+/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN14_INT_ENA  0x0000001F
+#define GPIO_PIN14_INT_ENA_M  ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
+#define GPIO_PIN14_INT_ENA_V  0x1F
+#define GPIO_PIN14_INT_ENA_S  13
+/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_CONFIG  0x00000003
+#define GPIO_PIN14_CONFIG_M  ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
+#define GPIO_PIN14_CONFIG_V  0x3
+#define GPIO_PIN14_CONFIG_S  11
+/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN14_INT_TYPE  0x00000007
+#define GPIO_PIN14_INT_TYPE_M  ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
+#define GPIO_PIN14_INT_TYPE_V  0x7
+#define GPIO_PIN14_INT_TYPE_S  7
+/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN14_SYNC1_BYPASS_M  ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S))
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN14_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_V  0x1
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN14_SYNC2_BYPASS_M  ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S))
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN15_REG          (DR_REG_GPIO_BASE + 0xB0)
+/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN15_INT_ENA  0x0000001F
+#define GPIO_PIN15_INT_ENA_M  ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
+#define GPIO_PIN15_INT_ENA_V  0x1F
+#define GPIO_PIN15_INT_ENA_S  13
+/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_CONFIG  0x00000003
+#define GPIO_PIN15_CONFIG_M  ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
+#define GPIO_PIN15_CONFIG_V  0x3
+#define GPIO_PIN15_CONFIG_S  11
+/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN15_INT_TYPE  0x00000007
+#define GPIO_PIN15_INT_TYPE_M  ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
+#define GPIO_PIN15_INT_TYPE_V  0x7
+#define GPIO_PIN15_INT_TYPE_S  7
+/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN15_SYNC1_BYPASS_M  ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S))
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN15_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_V  0x1
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN15_SYNC2_BYPASS_M  ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S))
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN16_REG          (DR_REG_GPIO_BASE + 0xB4)
+/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN16_INT_ENA  0x0000001F
+#define GPIO_PIN16_INT_ENA_M  ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
+#define GPIO_PIN16_INT_ENA_V  0x1F
+#define GPIO_PIN16_INT_ENA_S  13
+/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_CONFIG  0x00000003
+#define GPIO_PIN16_CONFIG_M  ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
+#define GPIO_PIN16_CONFIG_V  0x3
+#define GPIO_PIN16_CONFIG_S  11
+/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN16_INT_TYPE  0x00000007
+#define GPIO_PIN16_INT_TYPE_M  ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
+#define GPIO_PIN16_INT_TYPE_V  0x7
+#define GPIO_PIN16_INT_TYPE_S  7
+/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN16_SYNC1_BYPASS_M  ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S))
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN16_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_V  0x1
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN16_SYNC2_BYPASS_M  ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S))
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN17_REG          (DR_REG_GPIO_BASE + 0xB8)
+/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN17_INT_ENA  0x0000001F
+#define GPIO_PIN17_INT_ENA_M  ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
+#define GPIO_PIN17_INT_ENA_V  0x1F
+#define GPIO_PIN17_INT_ENA_S  13
+/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_CONFIG  0x00000003
+#define GPIO_PIN17_CONFIG_M  ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
+#define GPIO_PIN17_CONFIG_V  0x3
+#define GPIO_PIN17_CONFIG_S  11
+/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN17_INT_TYPE  0x00000007
+#define GPIO_PIN17_INT_TYPE_M  ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
+#define GPIO_PIN17_INT_TYPE_V  0x7
+#define GPIO_PIN17_INT_TYPE_S  7
+/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN17_SYNC1_BYPASS_M  ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S))
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN17_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_V  0x1
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN17_SYNC2_BYPASS_M  ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S))
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN18_REG          (DR_REG_GPIO_BASE + 0xBC)
+/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN18_INT_ENA  0x0000001F
+#define GPIO_PIN18_INT_ENA_M  ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
+#define GPIO_PIN18_INT_ENA_V  0x1F
+#define GPIO_PIN18_INT_ENA_S  13
+/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_CONFIG  0x00000003
+#define GPIO_PIN18_CONFIG_M  ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
+#define GPIO_PIN18_CONFIG_V  0x3
+#define GPIO_PIN18_CONFIG_S  11
+/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN18_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN18_INT_TYPE  0x00000007
+#define GPIO_PIN18_INT_TYPE_M  ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
+#define GPIO_PIN18_INT_TYPE_V  0x7
+#define GPIO_PIN18_INT_TYPE_S  7
+/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN18_SYNC1_BYPASS_M  ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S))
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN18_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_V  0x1
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN18_SYNC2_BYPASS_M  ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S))
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN19_REG          (DR_REG_GPIO_BASE + 0xC0)
+/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN19_INT_ENA  0x0000001F
+#define GPIO_PIN19_INT_ENA_M  ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
+#define GPIO_PIN19_INT_ENA_V  0x1F
+#define GPIO_PIN19_INT_ENA_S  13
+/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_CONFIG  0x00000003
+#define GPIO_PIN19_CONFIG_M  ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
+#define GPIO_PIN19_CONFIG_V  0x3
+#define GPIO_PIN19_CONFIG_S  11
+/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN19_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN19_INT_TYPE  0x00000007
+#define GPIO_PIN19_INT_TYPE_M  ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
+#define GPIO_PIN19_INT_TYPE_V  0x7
+#define GPIO_PIN19_INT_TYPE_S  7
+/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN19_SYNC1_BYPASS_M  ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S))
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN19_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_V  0x1
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN19_SYNC2_BYPASS_M  ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S))
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN20_REG          (DR_REG_GPIO_BASE + 0xC4)
+/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN20_INT_ENA  0x0000001F
+#define GPIO_PIN20_INT_ENA_M  ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
+#define GPIO_PIN20_INT_ENA_V  0x1F
+#define GPIO_PIN20_INT_ENA_S  13
+/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_CONFIG  0x00000003
+#define GPIO_PIN20_CONFIG_M  ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
+#define GPIO_PIN20_CONFIG_V  0x3
+#define GPIO_PIN20_CONFIG_S  11
+/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN20_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN20_INT_TYPE  0x00000007
+#define GPIO_PIN20_INT_TYPE_M  ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
+#define GPIO_PIN20_INT_TYPE_V  0x7
+#define GPIO_PIN20_INT_TYPE_S  7
+/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN20_SYNC1_BYPASS_M  ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S))
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN20_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_V  0x1
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN20_SYNC2_BYPASS_M  ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S))
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN21_REG          (DR_REG_GPIO_BASE + 0xC8)
+/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN21_INT_ENA  0x0000001F
+#define GPIO_PIN21_INT_ENA_M  ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
+#define GPIO_PIN21_INT_ENA_V  0x1F
+#define GPIO_PIN21_INT_ENA_S  13
+/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_CONFIG  0x00000003
+#define GPIO_PIN21_CONFIG_M  ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
+#define GPIO_PIN21_CONFIG_V  0x3
+#define GPIO_PIN21_CONFIG_S  11
+/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN21_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN21_INT_TYPE  0x00000007
+#define GPIO_PIN21_INT_TYPE_M  ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
+#define GPIO_PIN21_INT_TYPE_V  0x7
+#define GPIO_PIN21_INT_TYPE_S  7
+/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN21_SYNC1_BYPASS_M  ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S))
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN21_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_V  0x1
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN21_SYNC2_BYPASS_M  ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S))
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN22_REG          (DR_REG_GPIO_BASE + 0xCC)
+/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN22_INT_ENA  0x0000001F
+#define GPIO_PIN22_INT_ENA_M  ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
+#define GPIO_PIN22_INT_ENA_V  0x1F
+#define GPIO_PIN22_INT_ENA_S  13
+/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_CONFIG  0x00000003
+#define GPIO_PIN22_CONFIG_M  ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
+#define GPIO_PIN22_CONFIG_V  0x3
+#define GPIO_PIN22_CONFIG_S  11
+/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN22_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN22_INT_TYPE  0x00000007
+#define GPIO_PIN22_INT_TYPE_M  ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
+#define GPIO_PIN22_INT_TYPE_V  0x7
+#define GPIO_PIN22_INT_TYPE_S  7
+/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN22_SYNC1_BYPASS_M  ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S))
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN22_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_V  0x1
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN22_SYNC2_BYPASS_M  ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S))
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN23_REG          (DR_REG_GPIO_BASE + 0xD0)
+/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN23_INT_ENA  0x0000001F
+#define GPIO_PIN23_INT_ENA_M  ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
+#define GPIO_PIN23_INT_ENA_V  0x1F
+#define GPIO_PIN23_INT_ENA_S  13
+/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_CONFIG  0x00000003
+#define GPIO_PIN23_CONFIG_M  ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
+#define GPIO_PIN23_CONFIG_V  0x3
+#define GPIO_PIN23_CONFIG_S  11
+/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN23_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN23_INT_TYPE  0x00000007
+#define GPIO_PIN23_INT_TYPE_M  ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
+#define GPIO_PIN23_INT_TYPE_V  0x7
+#define GPIO_PIN23_INT_TYPE_S  7
+/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN23_SYNC1_BYPASS_M  ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S))
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN23_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_V  0x1
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN23_SYNC2_BYPASS_M  ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S))
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN24_REG          (DR_REG_GPIO_BASE + 0xD4)
+/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN24_INT_ENA  0x0000001F
+#define GPIO_PIN24_INT_ENA_M  ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
+#define GPIO_PIN24_INT_ENA_V  0x1F
+#define GPIO_PIN24_INT_ENA_S  13
+/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_CONFIG  0x00000003
+#define GPIO_PIN24_CONFIG_M  ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
+#define GPIO_PIN24_CONFIG_V  0x3
+#define GPIO_PIN24_CONFIG_S  11
+/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN24_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN24_INT_TYPE  0x00000007
+#define GPIO_PIN24_INT_TYPE_M  ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
+#define GPIO_PIN24_INT_TYPE_V  0x7
+#define GPIO_PIN24_INT_TYPE_S  7
+/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN24_SYNC1_BYPASS_M  ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S))
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN24_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_V  0x1
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN24_SYNC2_BYPASS_M  ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S))
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN25_REG          (DR_REG_GPIO_BASE + 0xD8)
+/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN25_INT_ENA  0x0000001F
+#define GPIO_PIN25_INT_ENA_M  ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
+#define GPIO_PIN25_INT_ENA_V  0x1F
+#define GPIO_PIN25_INT_ENA_S  13
+/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_CONFIG  0x00000003
+#define GPIO_PIN25_CONFIG_M  ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
+#define GPIO_PIN25_CONFIG_V  0x3
+#define GPIO_PIN25_CONFIG_S  11
+/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN25_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN25_WAKEUP_ENABLE_S  10
+/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN25_INT_TYPE  0x00000007
+#define GPIO_PIN25_INT_TYPE_M  ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
+#define GPIO_PIN25_INT_TYPE_V  0x7
+#define GPIO_PIN25_INT_TYPE_S  7
+/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN25_SYNC1_BYPASS_M  ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S))
+#define GPIO_PIN25_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN25_SYNC1_BYPASS_S  3
+/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN25_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_V  0x1
+#define GPIO_PIN25_PAD_DRIVER_S  2
+/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN25_SYNC2_BYPASS_M  ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S))
+#define GPIO_PIN25_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN25_SYNC2_BYPASS_S  0
+
+#define GPIO_STATUS_NEXT_REG          (DR_REG_GPIO_BASE + 0x14C)
+/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: */
+#define GPIO_STATUS_INTERRUPT_NEXT  0x03FFFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT_M  ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S))
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0x3FFFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+#define GPIO_FUNC0_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x154)
+/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG0_IN_SEL  (BIT(6))
+#define GPIO_SIG0_IN_SEL_M  (BIT(6))
+#define GPIO_SIG0_IN_SEL_V  0x1
+#define GPIO_SIG0_IN_SEL_S  6
+/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC0_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC0_IN_INV_SEL_V  0x1
+#define GPIO_FUNC0_IN_INV_SEL_S  5
+/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC0_IN_SEL  0x0000001F
+#define GPIO_FUNC0_IN_SEL_M  ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
+#define GPIO_FUNC0_IN_SEL_V  0x1F
+#define GPIO_FUNC0_IN_SEL_S  0
+
+#define GPIO_FUNC1_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x158)
+/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG1_IN_SEL  (BIT(6))
+#define GPIO_SIG1_IN_SEL_M  (BIT(6))
+#define GPIO_SIG1_IN_SEL_V  0x1
+#define GPIO_SIG1_IN_SEL_S  6
+/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC1_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC1_IN_INV_SEL_V  0x1
+#define GPIO_FUNC1_IN_INV_SEL_S  5
+/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC1_IN_SEL  0x0000001F
+#define GPIO_FUNC1_IN_SEL_M  ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
+#define GPIO_FUNC1_IN_SEL_V  0x1F
+#define GPIO_FUNC1_IN_SEL_S  0
+
+#define GPIO_FUNC2_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x15C)
+/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG2_IN_SEL  (BIT(6))
+#define GPIO_SIG2_IN_SEL_M  (BIT(6))
+#define GPIO_SIG2_IN_SEL_V  0x1
+#define GPIO_SIG2_IN_SEL_S  6
+/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC2_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC2_IN_INV_SEL_V  0x1
+#define GPIO_FUNC2_IN_INV_SEL_S  5
+/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC2_IN_SEL  0x0000001F
+#define GPIO_FUNC2_IN_SEL_M  ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
+#define GPIO_FUNC2_IN_SEL_V  0x1F
+#define GPIO_FUNC2_IN_SEL_S  0
+
+#define GPIO_FUNC3_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x160)
+/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG3_IN_SEL  (BIT(6))
+#define GPIO_SIG3_IN_SEL_M  (BIT(6))
+#define GPIO_SIG3_IN_SEL_V  0x1
+#define GPIO_SIG3_IN_SEL_S  6
+/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC3_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC3_IN_INV_SEL_V  0x1
+#define GPIO_FUNC3_IN_INV_SEL_S  5
+/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC3_IN_SEL  0x0000001F
+#define GPIO_FUNC3_IN_SEL_M  ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
+#define GPIO_FUNC3_IN_SEL_V  0x1F
+#define GPIO_FUNC3_IN_SEL_S  0
+
+#define GPIO_FUNC4_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x164)
+/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG4_IN_SEL  (BIT(6))
+#define GPIO_SIG4_IN_SEL_M  (BIT(6))
+#define GPIO_SIG4_IN_SEL_V  0x1
+#define GPIO_SIG4_IN_SEL_S  6
+/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC4_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC4_IN_INV_SEL_V  0x1
+#define GPIO_FUNC4_IN_INV_SEL_S  5
+/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC4_IN_SEL  0x0000001F
+#define GPIO_FUNC4_IN_SEL_M  ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
+#define GPIO_FUNC4_IN_SEL_V  0x1F
+#define GPIO_FUNC4_IN_SEL_S  0
+
+#define GPIO_FUNC5_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x168)
+/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG5_IN_SEL  (BIT(6))
+#define GPIO_SIG5_IN_SEL_M  (BIT(6))
+#define GPIO_SIG5_IN_SEL_V  0x1
+#define GPIO_SIG5_IN_SEL_S  6
+/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC5_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC5_IN_INV_SEL_V  0x1
+#define GPIO_FUNC5_IN_INV_SEL_S  5
+/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC5_IN_SEL  0x0000001F
+#define GPIO_FUNC5_IN_SEL_M  ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
+#define GPIO_FUNC5_IN_SEL_V  0x1F
+#define GPIO_FUNC5_IN_SEL_S  0
+
+#define GPIO_FUNC6_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x16C)
+/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG6_IN_SEL  (BIT(6))
+#define GPIO_SIG6_IN_SEL_M  (BIT(6))
+#define GPIO_SIG6_IN_SEL_V  0x1
+#define GPIO_SIG6_IN_SEL_S  6
+/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC6_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC6_IN_INV_SEL_V  0x1
+#define GPIO_FUNC6_IN_INV_SEL_S  5
+/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC6_IN_SEL  0x0000001F
+#define GPIO_FUNC6_IN_SEL_M  ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
+#define GPIO_FUNC6_IN_SEL_V  0x1F
+#define GPIO_FUNC6_IN_SEL_S  0
+
+#define GPIO_FUNC7_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x170)
+/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG7_IN_SEL  (BIT(6))
+#define GPIO_SIG7_IN_SEL_M  (BIT(6))
+#define GPIO_SIG7_IN_SEL_V  0x1
+#define GPIO_SIG7_IN_SEL_S  6
+/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC7_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC7_IN_INV_SEL_V  0x1
+#define GPIO_FUNC7_IN_INV_SEL_S  5
+/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC7_IN_SEL  0x0000001F
+#define GPIO_FUNC7_IN_SEL_M  ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
+#define GPIO_FUNC7_IN_SEL_V  0x1F
+#define GPIO_FUNC7_IN_SEL_S  0
+
+#define GPIO_FUNC8_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x174)
+/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG8_IN_SEL  (BIT(6))
+#define GPIO_SIG8_IN_SEL_M  (BIT(6))
+#define GPIO_SIG8_IN_SEL_V  0x1
+#define GPIO_SIG8_IN_SEL_S  6
+/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC8_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC8_IN_INV_SEL_V  0x1
+#define GPIO_FUNC8_IN_INV_SEL_S  5
+/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC8_IN_SEL  0x0000001F
+#define GPIO_FUNC8_IN_SEL_M  ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
+#define GPIO_FUNC8_IN_SEL_V  0x1F
+#define GPIO_FUNC8_IN_SEL_S  0
+
+#define GPIO_FUNC9_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x178)
+/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG9_IN_SEL  (BIT(6))
+#define GPIO_SIG9_IN_SEL_M  (BIT(6))
+#define GPIO_SIG9_IN_SEL_V  0x1
+#define GPIO_SIG9_IN_SEL_S  6
+/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC9_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC9_IN_INV_SEL_V  0x1
+#define GPIO_FUNC9_IN_INV_SEL_S  5
+/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC9_IN_SEL  0x0000001F
+#define GPIO_FUNC9_IN_SEL_M  ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
+#define GPIO_FUNC9_IN_SEL_V  0x1F
+#define GPIO_FUNC9_IN_SEL_S  0
+
+#define GPIO_FUNC10_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x17C)
+/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG10_IN_SEL  (BIT(6))
+#define GPIO_SIG10_IN_SEL_M  (BIT(6))
+#define GPIO_SIG10_IN_SEL_V  0x1
+#define GPIO_SIG10_IN_SEL_S  6
+/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC10_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC10_IN_INV_SEL_V  0x1
+#define GPIO_FUNC10_IN_INV_SEL_S  5
+/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC10_IN_SEL  0x0000001F
+#define GPIO_FUNC10_IN_SEL_M  ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
+#define GPIO_FUNC10_IN_SEL_V  0x1F
+#define GPIO_FUNC10_IN_SEL_S  0
+
+#define GPIO_FUNC11_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x180)
+/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG11_IN_SEL  (BIT(6))
+#define GPIO_SIG11_IN_SEL_M  (BIT(6))
+#define GPIO_SIG11_IN_SEL_V  0x1
+#define GPIO_SIG11_IN_SEL_S  6
+/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC11_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC11_IN_INV_SEL_V  0x1
+#define GPIO_FUNC11_IN_INV_SEL_S  5
+/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC11_IN_SEL  0x0000001F
+#define GPIO_FUNC11_IN_SEL_M  ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
+#define GPIO_FUNC11_IN_SEL_V  0x1F
+#define GPIO_FUNC11_IN_SEL_S  0
+
+#define GPIO_FUNC12_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x184)
+/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG12_IN_SEL  (BIT(6))
+#define GPIO_SIG12_IN_SEL_M  (BIT(6))
+#define GPIO_SIG12_IN_SEL_V  0x1
+#define GPIO_SIG12_IN_SEL_S  6
+/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC12_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC12_IN_INV_SEL_V  0x1
+#define GPIO_FUNC12_IN_INV_SEL_S  5
+/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC12_IN_SEL  0x0000001F
+#define GPIO_FUNC12_IN_SEL_M  ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
+#define GPIO_FUNC12_IN_SEL_V  0x1F
+#define GPIO_FUNC12_IN_SEL_S  0
+
+#define GPIO_FUNC13_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x188)
+/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG13_IN_SEL  (BIT(6))
+#define GPIO_SIG13_IN_SEL_M  (BIT(6))
+#define GPIO_SIG13_IN_SEL_V  0x1
+#define GPIO_SIG13_IN_SEL_S  6
+/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC13_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC13_IN_INV_SEL_V  0x1
+#define GPIO_FUNC13_IN_INV_SEL_S  5
+/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC13_IN_SEL  0x0000001F
+#define GPIO_FUNC13_IN_SEL_M  ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
+#define GPIO_FUNC13_IN_SEL_V  0x1F
+#define GPIO_FUNC13_IN_SEL_S  0
+
+#define GPIO_FUNC14_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x18C)
+/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG14_IN_SEL  (BIT(6))
+#define GPIO_SIG14_IN_SEL_M  (BIT(6))
+#define GPIO_SIG14_IN_SEL_V  0x1
+#define GPIO_SIG14_IN_SEL_S  6
+/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC14_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC14_IN_INV_SEL_V  0x1
+#define GPIO_FUNC14_IN_INV_SEL_S  5
+/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC14_IN_SEL  0x0000001F
+#define GPIO_FUNC14_IN_SEL_M  ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
+#define GPIO_FUNC14_IN_SEL_V  0x1F
+#define GPIO_FUNC14_IN_SEL_S  0
+
+#define GPIO_FUNC15_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x190)
+/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG15_IN_SEL  (BIT(6))
+#define GPIO_SIG15_IN_SEL_M  (BIT(6))
+#define GPIO_SIG15_IN_SEL_V  0x1
+#define GPIO_SIG15_IN_SEL_S  6
+/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC15_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC15_IN_INV_SEL_V  0x1
+#define GPIO_FUNC15_IN_INV_SEL_S  5
+/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC15_IN_SEL  0x0000001F
+#define GPIO_FUNC15_IN_SEL_M  ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
+#define GPIO_FUNC15_IN_SEL_V  0x1F
+#define GPIO_FUNC15_IN_SEL_S  0
+
+#define GPIO_FUNC16_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x194)
+/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG16_IN_SEL  (BIT(6))
+#define GPIO_SIG16_IN_SEL_M  (BIT(6))
+#define GPIO_SIG16_IN_SEL_V  0x1
+#define GPIO_SIG16_IN_SEL_S  6
+/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC16_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC16_IN_INV_SEL_V  0x1
+#define GPIO_FUNC16_IN_INV_SEL_S  5
+/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC16_IN_SEL  0x0000001F
+#define GPIO_FUNC16_IN_SEL_M  ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
+#define GPIO_FUNC16_IN_SEL_V  0x1F
+#define GPIO_FUNC16_IN_SEL_S  0
+
+#define GPIO_FUNC17_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x198)
+/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG17_IN_SEL  (BIT(6))
+#define GPIO_SIG17_IN_SEL_M  (BIT(6))
+#define GPIO_SIG17_IN_SEL_V  0x1
+#define GPIO_SIG17_IN_SEL_S  6
+/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC17_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC17_IN_INV_SEL_V  0x1
+#define GPIO_FUNC17_IN_INV_SEL_S  5
+/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC17_IN_SEL  0x0000001F
+#define GPIO_FUNC17_IN_SEL_M  ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
+#define GPIO_FUNC17_IN_SEL_V  0x1F
+#define GPIO_FUNC17_IN_SEL_S  0
+
+#define GPIO_FUNC18_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x19C)
+/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG18_IN_SEL  (BIT(6))
+#define GPIO_SIG18_IN_SEL_M  (BIT(6))
+#define GPIO_SIG18_IN_SEL_V  0x1
+#define GPIO_SIG18_IN_SEL_S  6
+/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC18_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC18_IN_INV_SEL_V  0x1
+#define GPIO_FUNC18_IN_INV_SEL_S  5
+/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC18_IN_SEL  0x0000001F
+#define GPIO_FUNC18_IN_SEL_M  ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
+#define GPIO_FUNC18_IN_SEL_V  0x1F
+#define GPIO_FUNC18_IN_SEL_S  0
+
+#define GPIO_FUNC19_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A0)
+/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG19_IN_SEL  (BIT(6))
+#define GPIO_SIG19_IN_SEL_M  (BIT(6))
+#define GPIO_SIG19_IN_SEL_V  0x1
+#define GPIO_SIG19_IN_SEL_S  6
+/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC19_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC19_IN_INV_SEL_V  0x1
+#define GPIO_FUNC19_IN_INV_SEL_S  5
+/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC19_IN_SEL  0x0000001F
+#define GPIO_FUNC19_IN_SEL_M  ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
+#define GPIO_FUNC19_IN_SEL_V  0x1F
+#define GPIO_FUNC19_IN_SEL_S  0
+
+#define GPIO_FUNC20_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A4)
+/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG20_IN_SEL  (BIT(6))
+#define GPIO_SIG20_IN_SEL_M  (BIT(6))
+#define GPIO_SIG20_IN_SEL_V  0x1
+#define GPIO_SIG20_IN_SEL_S  6
+/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC20_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC20_IN_INV_SEL_V  0x1
+#define GPIO_FUNC20_IN_INV_SEL_S  5
+/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC20_IN_SEL  0x0000001F
+#define GPIO_FUNC20_IN_SEL_M  ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
+#define GPIO_FUNC20_IN_SEL_V  0x1F
+#define GPIO_FUNC20_IN_SEL_S  0
+
+#define GPIO_FUNC21_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A8)
+/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG21_IN_SEL  (BIT(6))
+#define GPIO_SIG21_IN_SEL_M  (BIT(6))
+#define GPIO_SIG21_IN_SEL_V  0x1
+#define GPIO_SIG21_IN_SEL_S  6
+/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC21_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC21_IN_INV_SEL_V  0x1
+#define GPIO_FUNC21_IN_INV_SEL_S  5
+/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC21_IN_SEL  0x0000001F
+#define GPIO_FUNC21_IN_SEL_M  ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
+#define GPIO_FUNC21_IN_SEL_V  0x1F
+#define GPIO_FUNC21_IN_SEL_S  0
+
+#define GPIO_FUNC22_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1AC)
+/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG22_IN_SEL  (BIT(6))
+#define GPIO_SIG22_IN_SEL_M  (BIT(6))
+#define GPIO_SIG22_IN_SEL_V  0x1
+#define GPIO_SIG22_IN_SEL_S  6
+/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC22_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC22_IN_INV_SEL_V  0x1
+#define GPIO_FUNC22_IN_INV_SEL_S  5
+/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC22_IN_SEL  0x0000001F
+#define GPIO_FUNC22_IN_SEL_M  ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
+#define GPIO_FUNC22_IN_SEL_V  0x1F
+#define GPIO_FUNC22_IN_SEL_S  0
+
+#define GPIO_FUNC23_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B0)
+/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG23_IN_SEL  (BIT(6))
+#define GPIO_SIG23_IN_SEL_M  (BIT(6))
+#define GPIO_SIG23_IN_SEL_V  0x1
+#define GPIO_SIG23_IN_SEL_S  6
+/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC23_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC23_IN_INV_SEL_V  0x1
+#define GPIO_FUNC23_IN_INV_SEL_S  5
+/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC23_IN_SEL  0x0000001F
+#define GPIO_FUNC23_IN_SEL_M  ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
+#define GPIO_FUNC23_IN_SEL_V  0x1F
+#define GPIO_FUNC23_IN_SEL_S  0
+
+#define GPIO_FUNC24_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B4)
+/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG24_IN_SEL  (BIT(6))
+#define GPIO_SIG24_IN_SEL_M  (BIT(6))
+#define GPIO_SIG24_IN_SEL_V  0x1
+#define GPIO_SIG24_IN_SEL_S  6
+/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC24_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC24_IN_INV_SEL_V  0x1
+#define GPIO_FUNC24_IN_INV_SEL_S  5
+/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC24_IN_SEL  0x0000001F
+#define GPIO_FUNC24_IN_SEL_M  ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
+#define GPIO_FUNC24_IN_SEL_V  0x1F
+#define GPIO_FUNC24_IN_SEL_S  0
+
+#define GPIO_FUNC25_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B8)
+/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG25_IN_SEL  (BIT(6))
+#define GPIO_SIG25_IN_SEL_M  (BIT(6))
+#define GPIO_SIG25_IN_SEL_V  0x1
+#define GPIO_SIG25_IN_SEL_S  6
+/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC25_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC25_IN_INV_SEL_V  0x1
+#define GPIO_FUNC25_IN_INV_SEL_S  5
+/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC25_IN_SEL  0x0000001F
+#define GPIO_FUNC25_IN_SEL_M  ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
+#define GPIO_FUNC25_IN_SEL_V  0x1F
+#define GPIO_FUNC25_IN_SEL_S  0
+
+#define GPIO_FUNC26_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1BC)
+/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG26_IN_SEL  (BIT(6))
+#define GPIO_SIG26_IN_SEL_M  (BIT(6))
+#define GPIO_SIG26_IN_SEL_V  0x1
+#define GPIO_SIG26_IN_SEL_S  6
+/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC26_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC26_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC26_IN_INV_SEL_V  0x1
+#define GPIO_FUNC26_IN_INV_SEL_S  5
+/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC26_IN_SEL  0x0000001F
+#define GPIO_FUNC26_IN_SEL_M  ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
+#define GPIO_FUNC26_IN_SEL_V  0x1F
+#define GPIO_FUNC26_IN_SEL_S  0
+
+#define GPIO_FUNC27_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C0)
+/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG27_IN_SEL  (BIT(6))
+#define GPIO_SIG27_IN_SEL_M  (BIT(6))
+#define GPIO_SIG27_IN_SEL_V  0x1
+#define GPIO_SIG27_IN_SEL_S  6
+/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC27_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC27_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC27_IN_INV_SEL_V  0x1
+#define GPIO_FUNC27_IN_INV_SEL_S  5
+/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC27_IN_SEL  0x0000001F
+#define GPIO_FUNC27_IN_SEL_M  ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
+#define GPIO_FUNC27_IN_SEL_V  0x1F
+#define GPIO_FUNC27_IN_SEL_S  0
+
+#define GPIO_FUNC28_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C4)
+/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG28_IN_SEL  (BIT(6))
+#define GPIO_SIG28_IN_SEL_M  (BIT(6))
+#define GPIO_SIG28_IN_SEL_V  0x1
+#define GPIO_SIG28_IN_SEL_S  6
+/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC28_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC28_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC28_IN_INV_SEL_V  0x1
+#define GPIO_FUNC28_IN_INV_SEL_S  5
+/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC28_IN_SEL  0x0000001F
+#define GPIO_FUNC28_IN_SEL_M  ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
+#define GPIO_FUNC28_IN_SEL_V  0x1F
+#define GPIO_FUNC28_IN_SEL_S  0
+
+#define GPIO_FUNC29_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C8)
+/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG29_IN_SEL  (BIT(6))
+#define GPIO_SIG29_IN_SEL_M  (BIT(6))
+#define GPIO_SIG29_IN_SEL_V  0x1
+#define GPIO_SIG29_IN_SEL_S  6
+/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC29_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC29_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC29_IN_INV_SEL_V  0x1
+#define GPIO_FUNC29_IN_INV_SEL_S  5
+/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC29_IN_SEL  0x0000001F
+#define GPIO_FUNC29_IN_SEL_M  ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
+#define GPIO_FUNC29_IN_SEL_V  0x1F
+#define GPIO_FUNC29_IN_SEL_S  0
+
+#define GPIO_FUNC30_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1CC)
+/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG30_IN_SEL  (BIT(6))
+#define GPIO_SIG30_IN_SEL_M  (BIT(6))
+#define GPIO_SIG30_IN_SEL_V  0x1
+#define GPIO_SIG30_IN_SEL_S  6
+/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC30_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC30_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC30_IN_INV_SEL_V  0x1
+#define GPIO_FUNC30_IN_INV_SEL_S  5
+/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC30_IN_SEL  0x0000001F
+#define GPIO_FUNC30_IN_SEL_M  ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
+#define GPIO_FUNC30_IN_SEL_V  0x1F
+#define GPIO_FUNC30_IN_SEL_S  0
+
+#define GPIO_FUNC31_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D0)
+/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG31_IN_SEL  (BIT(6))
+#define GPIO_SIG31_IN_SEL_M  (BIT(6))
+#define GPIO_SIG31_IN_SEL_V  0x1
+#define GPIO_SIG31_IN_SEL_S  6
+/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC31_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC31_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC31_IN_INV_SEL_V  0x1
+#define GPIO_FUNC31_IN_INV_SEL_S  5
+/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC31_IN_SEL  0x0000001F
+#define GPIO_FUNC31_IN_SEL_M  ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
+#define GPIO_FUNC31_IN_SEL_V  0x1F
+#define GPIO_FUNC31_IN_SEL_S  0
+
+#define GPIO_FUNC32_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D4)
+/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG32_IN_SEL  (BIT(6))
+#define GPIO_SIG32_IN_SEL_M  (BIT(6))
+#define GPIO_SIG32_IN_SEL_V  0x1
+#define GPIO_SIG32_IN_SEL_S  6
+/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC32_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC32_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC32_IN_INV_SEL_V  0x1
+#define GPIO_FUNC32_IN_INV_SEL_S  5
+/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC32_IN_SEL  0x0000001F
+#define GPIO_FUNC32_IN_SEL_M  ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
+#define GPIO_FUNC32_IN_SEL_V  0x1F
+#define GPIO_FUNC32_IN_SEL_S  0
+
+#define GPIO_FUNC33_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D8)
+/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG33_IN_SEL  (BIT(6))
+#define GPIO_SIG33_IN_SEL_M  (BIT(6))
+#define GPIO_SIG33_IN_SEL_V  0x1
+#define GPIO_SIG33_IN_SEL_S  6
+/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC33_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC33_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC33_IN_INV_SEL_V  0x1
+#define GPIO_FUNC33_IN_INV_SEL_S  5
+/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC33_IN_SEL  0x0000001F
+#define GPIO_FUNC33_IN_SEL_M  ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
+#define GPIO_FUNC33_IN_SEL_V  0x1F
+#define GPIO_FUNC33_IN_SEL_S  0
+
+#define GPIO_FUNC34_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1DC)
+/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG34_IN_SEL  (BIT(6))
+#define GPIO_SIG34_IN_SEL_M  (BIT(6))
+#define GPIO_SIG34_IN_SEL_V  0x1
+#define GPIO_SIG34_IN_SEL_S  6
+/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC34_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC34_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC34_IN_INV_SEL_V  0x1
+#define GPIO_FUNC34_IN_INV_SEL_S  5
+/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC34_IN_SEL  0x0000001F
+#define GPIO_FUNC34_IN_SEL_M  ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
+#define GPIO_FUNC34_IN_SEL_V  0x1F
+#define GPIO_FUNC34_IN_SEL_S  0
+
+#define GPIO_FUNC35_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E0)
+/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG35_IN_SEL  (BIT(6))
+#define GPIO_SIG35_IN_SEL_M  (BIT(6))
+#define GPIO_SIG35_IN_SEL_V  0x1
+#define GPIO_SIG35_IN_SEL_S  6
+/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC35_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC35_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC35_IN_INV_SEL_V  0x1
+#define GPIO_FUNC35_IN_INV_SEL_S  5
+/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC35_IN_SEL  0x0000001F
+#define GPIO_FUNC35_IN_SEL_M  ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
+#define GPIO_FUNC35_IN_SEL_V  0x1F
+#define GPIO_FUNC35_IN_SEL_S  0
+
+#define GPIO_FUNC36_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E4)
+/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG36_IN_SEL  (BIT(6))
+#define GPIO_SIG36_IN_SEL_M  (BIT(6))
+#define GPIO_SIG36_IN_SEL_V  0x1
+#define GPIO_SIG36_IN_SEL_S  6
+/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC36_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC36_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC36_IN_INV_SEL_V  0x1
+#define GPIO_FUNC36_IN_INV_SEL_S  5
+/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC36_IN_SEL  0x0000001F
+#define GPIO_FUNC36_IN_SEL_M  ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
+#define GPIO_FUNC36_IN_SEL_V  0x1F
+#define GPIO_FUNC36_IN_SEL_S  0
+
+#define GPIO_FUNC37_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E8)
+/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG37_IN_SEL  (BIT(6))
+#define GPIO_SIG37_IN_SEL_M  (BIT(6))
+#define GPIO_SIG37_IN_SEL_V  0x1
+#define GPIO_SIG37_IN_SEL_S  6
+/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC37_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC37_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC37_IN_INV_SEL_V  0x1
+#define GPIO_FUNC37_IN_INV_SEL_S  5
+/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC37_IN_SEL  0x0000001F
+#define GPIO_FUNC37_IN_SEL_M  ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
+#define GPIO_FUNC37_IN_SEL_V  0x1F
+#define GPIO_FUNC37_IN_SEL_S  0
+
+#define GPIO_FUNC38_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1EC)
+/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG38_IN_SEL  (BIT(6))
+#define GPIO_SIG38_IN_SEL_M  (BIT(6))
+#define GPIO_SIG38_IN_SEL_V  0x1
+#define GPIO_SIG38_IN_SEL_S  6
+/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC38_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC38_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC38_IN_INV_SEL_V  0x1
+#define GPIO_FUNC38_IN_INV_SEL_S  5
+/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC38_IN_SEL  0x0000001F
+#define GPIO_FUNC38_IN_SEL_M  ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
+#define GPIO_FUNC38_IN_SEL_V  0x1F
+#define GPIO_FUNC38_IN_SEL_S  0
+
+#define GPIO_FUNC39_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F0)
+/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG39_IN_SEL  (BIT(6))
+#define GPIO_SIG39_IN_SEL_M  (BIT(6))
+#define GPIO_SIG39_IN_SEL_V  0x1
+#define GPIO_SIG39_IN_SEL_S  6
+/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC39_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC39_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC39_IN_INV_SEL_V  0x1
+#define GPIO_FUNC39_IN_INV_SEL_S  5
+/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC39_IN_SEL  0x0000001F
+#define GPIO_FUNC39_IN_SEL_M  ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
+#define GPIO_FUNC39_IN_SEL_V  0x1F
+#define GPIO_FUNC39_IN_SEL_S  0
+
+#define GPIO_FUNC40_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F4)
+/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG40_IN_SEL  (BIT(6))
+#define GPIO_SIG40_IN_SEL_M  (BIT(6))
+#define GPIO_SIG40_IN_SEL_V  0x1
+#define GPIO_SIG40_IN_SEL_S  6
+/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC40_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC40_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC40_IN_INV_SEL_V  0x1
+#define GPIO_FUNC40_IN_INV_SEL_S  5
+/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC40_IN_SEL  0x0000001F
+#define GPIO_FUNC40_IN_SEL_M  ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
+#define GPIO_FUNC40_IN_SEL_V  0x1F
+#define GPIO_FUNC40_IN_SEL_S  0
+
+#define GPIO_FUNC41_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F8)
+/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG41_IN_SEL  (BIT(6))
+#define GPIO_SIG41_IN_SEL_M  (BIT(6))
+#define GPIO_SIG41_IN_SEL_V  0x1
+#define GPIO_SIG41_IN_SEL_S  6
+/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC41_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC41_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC41_IN_INV_SEL_V  0x1
+#define GPIO_FUNC41_IN_INV_SEL_S  5
+/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC41_IN_SEL  0x0000001F
+#define GPIO_FUNC41_IN_SEL_M  ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
+#define GPIO_FUNC41_IN_SEL_V  0x1F
+#define GPIO_FUNC41_IN_SEL_S  0
+
+#define GPIO_FUNC42_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1FC)
+/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG42_IN_SEL  (BIT(6))
+#define GPIO_SIG42_IN_SEL_M  (BIT(6))
+#define GPIO_SIG42_IN_SEL_V  0x1
+#define GPIO_SIG42_IN_SEL_S  6
+/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC42_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC42_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC42_IN_INV_SEL_V  0x1
+#define GPIO_FUNC42_IN_INV_SEL_S  5
+/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC42_IN_SEL  0x0000001F
+#define GPIO_FUNC42_IN_SEL_M  ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
+#define GPIO_FUNC42_IN_SEL_V  0x1F
+#define GPIO_FUNC42_IN_SEL_S  0
+
+#define GPIO_FUNC43_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x200)
+/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG43_IN_SEL  (BIT(6))
+#define GPIO_SIG43_IN_SEL_M  (BIT(6))
+#define GPIO_SIG43_IN_SEL_V  0x1
+#define GPIO_SIG43_IN_SEL_S  6
+/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC43_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC43_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC43_IN_INV_SEL_V  0x1
+#define GPIO_FUNC43_IN_INV_SEL_S  5
+/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC43_IN_SEL  0x0000001F
+#define GPIO_FUNC43_IN_SEL_M  ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
+#define GPIO_FUNC43_IN_SEL_V  0x1F
+#define GPIO_FUNC43_IN_SEL_S  0
+
+#define GPIO_FUNC44_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x204)
+/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG44_IN_SEL  (BIT(6))
+#define GPIO_SIG44_IN_SEL_M  (BIT(6))
+#define GPIO_SIG44_IN_SEL_V  0x1
+#define GPIO_SIG44_IN_SEL_S  6
+/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC44_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC44_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC44_IN_INV_SEL_V  0x1
+#define GPIO_FUNC44_IN_INV_SEL_S  5
+/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC44_IN_SEL  0x0000001F
+#define GPIO_FUNC44_IN_SEL_M  ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
+#define GPIO_FUNC44_IN_SEL_V  0x1F
+#define GPIO_FUNC44_IN_SEL_S  0
+
+#define GPIO_FUNC45_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x208)
+/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG45_IN_SEL  (BIT(6))
+#define GPIO_SIG45_IN_SEL_M  (BIT(6))
+#define GPIO_SIG45_IN_SEL_V  0x1
+#define GPIO_SIG45_IN_SEL_S  6
+/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC45_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC45_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC45_IN_INV_SEL_V  0x1
+#define GPIO_FUNC45_IN_INV_SEL_S  5
+/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC45_IN_SEL  0x0000001F
+#define GPIO_FUNC45_IN_SEL_M  ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
+#define GPIO_FUNC45_IN_SEL_V  0x1F
+#define GPIO_FUNC45_IN_SEL_S  0
+
+#define GPIO_FUNC46_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x20C)
+/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG46_IN_SEL  (BIT(6))
+#define GPIO_SIG46_IN_SEL_M  (BIT(6))
+#define GPIO_SIG46_IN_SEL_V  0x1
+#define GPIO_SIG46_IN_SEL_S  6
+/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC46_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC46_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC46_IN_INV_SEL_V  0x1
+#define GPIO_FUNC46_IN_INV_SEL_S  5
+/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC46_IN_SEL  0x0000001F
+#define GPIO_FUNC46_IN_SEL_M  ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
+#define GPIO_FUNC46_IN_SEL_V  0x1F
+#define GPIO_FUNC46_IN_SEL_S  0
+
+#define GPIO_FUNC47_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x210)
+/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG47_IN_SEL  (BIT(6))
+#define GPIO_SIG47_IN_SEL_M  (BIT(6))
+#define GPIO_SIG47_IN_SEL_V  0x1
+#define GPIO_SIG47_IN_SEL_S  6
+/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC47_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC47_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC47_IN_INV_SEL_V  0x1
+#define GPIO_FUNC47_IN_INV_SEL_S  5
+/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC47_IN_SEL  0x0000001F
+#define GPIO_FUNC47_IN_SEL_M  ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
+#define GPIO_FUNC47_IN_SEL_V  0x1F
+#define GPIO_FUNC47_IN_SEL_S  0
+
+#define GPIO_FUNC48_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x214)
+/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG48_IN_SEL  (BIT(6))
+#define GPIO_SIG48_IN_SEL_M  (BIT(6))
+#define GPIO_SIG48_IN_SEL_V  0x1
+#define GPIO_SIG48_IN_SEL_S  6
+/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC48_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC48_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC48_IN_INV_SEL_V  0x1
+#define GPIO_FUNC48_IN_INV_SEL_S  5
+/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC48_IN_SEL  0x0000001F
+#define GPIO_FUNC48_IN_SEL_M  ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
+#define GPIO_FUNC48_IN_SEL_V  0x1F
+#define GPIO_FUNC48_IN_SEL_S  0
+
+#define GPIO_FUNC49_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x218)
+/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG49_IN_SEL  (BIT(6))
+#define GPIO_SIG49_IN_SEL_M  (BIT(6))
+#define GPIO_SIG49_IN_SEL_V  0x1
+#define GPIO_SIG49_IN_SEL_S  6
+/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC49_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC49_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC49_IN_INV_SEL_V  0x1
+#define GPIO_FUNC49_IN_INV_SEL_S  5
+/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC49_IN_SEL  0x0000001F
+#define GPIO_FUNC49_IN_SEL_M  ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
+#define GPIO_FUNC49_IN_SEL_V  0x1F
+#define GPIO_FUNC49_IN_SEL_S  0
+
+#define GPIO_FUNC50_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x21C)
+/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG50_IN_SEL  (BIT(6))
+#define GPIO_SIG50_IN_SEL_M  (BIT(6))
+#define GPIO_SIG50_IN_SEL_V  0x1
+#define GPIO_SIG50_IN_SEL_S  6
+/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC50_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC50_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC50_IN_INV_SEL_V  0x1
+#define GPIO_FUNC50_IN_INV_SEL_S  5
+/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC50_IN_SEL  0x0000001F
+#define GPIO_FUNC50_IN_SEL_M  ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
+#define GPIO_FUNC50_IN_SEL_V  0x1F
+#define GPIO_FUNC50_IN_SEL_S  0
+
+#define GPIO_FUNC51_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x220)
+/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG51_IN_SEL  (BIT(6))
+#define GPIO_SIG51_IN_SEL_M  (BIT(6))
+#define GPIO_SIG51_IN_SEL_V  0x1
+#define GPIO_SIG51_IN_SEL_S  6
+/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC51_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC51_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC51_IN_INV_SEL_V  0x1
+#define GPIO_FUNC51_IN_INV_SEL_S  5
+/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC51_IN_SEL  0x0000001F
+#define GPIO_FUNC51_IN_SEL_M  ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
+#define GPIO_FUNC51_IN_SEL_V  0x1F
+#define GPIO_FUNC51_IN_SEL_S  0
+
+#define GPIO_FUNC52_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x224)
+/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG52_IN_SEL  (BIT(6))
+#define GPIO_SIG52_IN_SEL_M  (BIT(6))
+#define GPIO_SIG52_IN_SEL_V  0x1
+#define GPIO_SIG52_IN_SEL_S  6
+/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC52_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC52_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC52_IN_INV_SEL_V  0x1
+#define GPIO_FUNC52_IN_INV_SEL_S  5
+/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC52_IN_SEL  0x0000001F
+#define GPIO_FUNC52_IN_SEL_M  ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
+#define GPIO_FUNC52_IN_SEL_V  0x1F
+#define GPIO_FUNC52_IN_SEL_S  0
+
+#define GPIO_FUNC53_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x228)
+/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG53_IN_SEL  (BIT(6))
+#define GPIO_SIG53_IN_SEL_M  (BIT(6))
+#define GPIO_SIG53_IN_SEL_V  0x1
+#define GPIO_SIG53_IN_SEL_S  6
+/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC53_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC53_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC53_IN_INV_SEL_V  0x1
+#define GPIO_FUNC53_IN_INV_SEL_S  5
+/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC53_IN_SEL  0x0000001F
+#define GPIO_FUNC53_IN_SEL_M  ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
+#define GPIO_FUNC53_IN_SEL_V  0x1F
+#define GPIO_FUNC53_IN_SEL_S  0
+
+#define GPIO_FUNC54_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x22C)
+/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG54_IN_SEL  (BIT(6))
+#define GPIO_SIG54_IN_SEL_M  (BIT(6))
+#define GPIO_SIG54_IN_SEL_V  0x1
+#define GPIO_SIG54_IN_SEL_S  6
+/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC54_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC54_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC54_IN_INV_SEL_V  0x1
+#define GPIO_FUNC54_IN_INV_SEL_S  5
+/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC54_IN_SEL  0x0000001F
+#define GPIO_FUNC54_IN_SEL_M  ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
+#define GPIO_FUNC54_IN_SEL_V  0x1F
+#define GPIO_FUNC54_IN_SEL_S  0
+
+#define GPIO_FUNC55_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x230)
+/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG55_IN_SEL  (BIT(6))
+#define GPIO_SIG55_IN_SEL_M  (BIT(6))
+#define GPIO_SIG55_IN_SEL_V  0x1
+#define GPIO_SIG55_IN_SEL_S  6
+/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC55_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC55_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC55_IN_INV_SEL_V  0x1
+#define GPIO_FUNC55_IN_INV_SEL_S  5
+/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC55_IN_SEL  0x0000001F
+#define GPIO_FUNC55_IN_SEL_M  ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
+#define GPIO_FUNC55_IN_SEL_V  0x1F
+#define GPIO_FUNC55_IN_SEL_S  0
+
+#define GPIO_FUNC56_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x234)
+/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG56_IN_SEL  (BIT(6))
+#define GPIO_SIG56_IN_SEL_M  (BIT(6))
+#define GPIO_SIG56_IN_SEL_V  0x1
+#define GPIO_SIG56_IN_SEL_S  6
+/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC56_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC56_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC56_IN_INV_SEL_V  0x1
+#define GPIO_FUNC56_IN_INV_SEL_S  5
+/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC56_IN_SEL  0x0000001F
+#define GPIO_FUNC56_IN_SEL_M  ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
+#define GPIO_FUNC56_IN_SEL_V  0x1F
+#define GPIO_FUNC56_IN_SEL_S  0
+
+#define GPIO_FUNC57_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x238)
+/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG57_IN_SEL  (BIT(6))
+#define GPIO_SIG57_IN_SEL_M  (BIT(6))
+#define GPIO_SIG57_IN_SEL_V  0x1
+#define GPIO_SIG57_IN_SEL_S  6
+/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC57_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC57_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC57_IN_INV_SEL_V  0x1
+#define GPIO_FUNC57_IN_INV_SEL_S  5
+/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC57_IN_SEL  0x0000001F
+#define GPIO_FUNC57_IN_SEL_M  ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
+#define GPIO_FUNC57_IN_SEL_V  0x1F
+#define GPIO_FUNC57_IN_SEL_S  0
+
+#define GPIO_FUNC58_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x23C)
+/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG58_IN_SEL  (BIT(6))
+#define GPIO_SIG58_IN_SEL_M  (BIT(6))
+#define GPIO_SIG58_IN_SEL_V  0x1
+#define GPIO_SIG58_IN_SEL_S  6
+/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC58_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC58_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC58_IN_INV_SEL_V  0x1
+#define GPIO_FUNC58_IN_INV_SEL_S  5
+/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC58_IN_SEL  0x0000001F
+#define GPIO_FUNC58_IN_SEL_M  ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
+#define GPIO_FUNC58_IN_SEL_V  0x1F
+#define GPIO_FUNC58_IN_SEL_S  0
+
+#define GPIO_FUNC59_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x240)
+/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG59_IN_SEL  (BIT(6))
+#define GPIO_SIG59_IN_SEL_M  (BIT(6))
+#define GPIO_SIG59_IN_SEL_V  0x1
+#define GPIO_SIG59_IN_SEL_S  6
+/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC59_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC59_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC59_IN_INV_SEL_V  0x1
+#define GPIO_FUNC59_IN_INV_SEL_S  5
+/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC59_IN_SEL  0x0000001F
+#define GPIO_FUNC59_IN_SEL_M  ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
+#define GPIO_FUNC59_IN_SEL_V  0x1F
+#define GPIO_FUNC59_IN_SEL_S  0
+
+#define GPIO_FUNC60_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x244)
+/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG60_IN_SEL  (BIT(6))
+#define GPIO_SIG60_IN_SEL_M  (BIT(6))
+#define GPIO_SIG60_IN_SEL_V  0x1
+#define GPIO_SIG60_IN_SEL_S  6
+/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC60_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC60_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC60_IN_INV_SEL_V  0x1
+#define GPIO_FUNC60_IN_INV_SEL_S  5
+/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC60_IN_SEL  0x0000001F
+#define GPIO_FUNC60_IN_SEL_M  ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
+#define GPIO_FUNC60_IN_SEL_V  0x1F
+#define GPIO_FUNC60_IN_SEL_S  0
+
+#define GPIO_FUNC61_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x248)
+/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG61_IN_SEL  (BIT(6))
+#define GPIO_SIG61_IN_SEL_M  (BIT(6))
+#define GPIO_SIG61_IN_SEL_V  0x1
+#define GPIO_SIG61_IN_SEL_S  6
+/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC61_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC61_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC61_IN_INV_SEL_V  0x1
+#define GPIO_FUNC61_IN_INV_SEL_S  5
+/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC61_IN_SEL  0x0000001F
+#define GPIO_FUNC61_IN_SEL_M  ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
+#define GPIO_FUNC61_IN_SEL_V  0x1F
+#define GPIO_FUNC61_IN_SEL_S  0
+
+#define GPIO_FUNC62_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x24C)
+/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG62_IN_SEL  (BIT(6))
+#define GPIO_SIG62_IN_SEL_M  (BIT(6))
+#define GPIO_SIG62_IN_SEL_V  0x1
+#define GPIO_SIG62_IN_SEL_S  6
+/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC62_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC62_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC62_IN_INV_SEL_V  0x1
+#define GPIO_FUNC62_IN_INV_SEL_S  5
+/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC62_IN_SEL  0x0000001F
+#define GPIO_FUNC62_IN_SEL_M  ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
+#define GPIO_FUNC62_IN_SEL_V  0x1F
+#define GPIO_FUNC62_IN_SEL_S  0
+
+#define GPIO_FUNC63_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x250)
+/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG63_IN_SEL  (BIT(6))
+#define GPIO_SIG63_IN_SEL_M  (BIT(6))
+#define GPIO_SIG63_IN_SEL_V  0x1
+#define GPIO_SIG63_IN_SEL_S  6
+/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC63_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC63_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC63_IN_INV_SEL_V  0x1
+#define GPIO_FUNC63_IN_INV_SEL_S  5
+/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC63_IN_SEL  0x0000001F
+#define GPIO_FUNC63_IN_SEL_M  ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
+#define GPIO_FUNC63_IN_SEL_V  0x1F
+#define GPIO_FUNC63_IN_SEL_S  0
+
+#define GPIO_FUNC64_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x254)
+/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG64_IN_SEL  (BIT(6))
+#define GPIO_SIG64_IN_SEL_M  (BIT(6))
+#define GPIO_SIG64_IN_SEL_V  0x1
+#define GPIO_SIG64_IN_SEL_S  6
+/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC64_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC64_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC64_IN_INV_SEL_V  0x1
+#define GPIO_FUNC64_IN_INV_SEL_S  5
+/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC64_IN_SEL  0x0000001F
+#define GPIO_FUNC64_IN_SEL_M  ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
+#define GPIO_FUNC64_IN_SEL_V  0x1F
+#define GPIO_FUNC64_IN_SEL_S  0
+
+#define GPIO_FUNC65_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x258)
+/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG65_IN_SEL  (BIT(6))
+#define GPIO_SIG65_IN_SEL_M  (BIT(6))
+#define GPIO_SIG65_IN_SEL_V  0x1
+#define GPIO_SIG65_IN_SEL_S  6
+/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC65_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC65_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC65_IN_INV_SEL_V  0x1
+#define GPIO_FUNC65_IN_INV_SEL_S  5
+/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC65_IN_SEL  0x0000001F
+#define GPIO_FUNC65_IN_SEL_M  ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
+#define GPIO_FUNC65_IN_SEL_V  0x1F
+#define GPIO_FUNC65_IN_SEL_S  0
+
+#define GPIO_FUNC66_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x25C)
+/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG66_IN_SEL  (BIT(6))
+#define GPIO_SIG66_IN_SEL_M  (BIT(6))
+#define GPIO_SIG66_IN_SEL_V  0x1
+#define GPIO_SIG66_IN_SEL_S  6
+/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC66_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC66_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC66_IN_INV_SEL_V  0x1
+#define GPIO_FUNC66_IN_INV_SEL_S  5
+/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC66_IN_SEL  0x0000001F
+#define GPIO_FUNC66_IN_SEL_M  ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
+#define GPIO_FUNC66_IN_SEL_V  0x1F
+#define GPIO_FUNC66_IN_SEL_S  0
+
+#define GPIO_FUNC67_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x260)
+/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG67_IN_SEL  (BIT(6))
+#define GPIO_SIG67_IN_SEL_M  (BIT(6))
+#define GPIO_SIG67_IN_SEL_V  0x1
+#define GPIO_SIG67_IN_SEL_S  6
+/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC67_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC67_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC67_IN_INV_SEL_V  0x1
+#define GPIO_FUNC67_IN_INV_SEL_S  5
+/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC67_IN_SEL  0x0000001F
+#define GPIO_FUNC67_IN_SEL_M  ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
+#define GPIO_FUNC67_IN_SEL_V  0x1F
+#define GPIO_FUNC67_IN_SEL_S  0
+
+#define GPIO_FUNC68_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x264)
+/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG68_IN_SEL  (BIT(6))
+#define GPIO_SIG68_IN_SEL_M  (BIT(6))
+#define GPIO_SIG68_IN_SEL_V  0x1
+#define GPIO_SIG68_IN_SEL_S  6
+/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC68_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC68_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC68_IN_INV_SEL_V  0x1
+#define GPIO_FUNC68_IN_INV_SEL_S  5
+/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC68_IN_SEL  0x0000001F
+#define GPIO_FUNC68_IN_SEL_M  ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
+#define GPIO_FUNC68_IN_SEL_V  0x1F
+#define GPIO_FUNC68_IN_SEL_S  0
+
+#define GPIO_FUNC69_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x268)
+/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG69_IN_SEL  (BIT(6))
+#define GPIO_SIG69_IN_SEL_M  (BIT(6))
+#define GPIO_SIG69_IN_SEL_V  0x1
+#define GPIO_SIG69_IN_SEL_S  6
+/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC69_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC69_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC69_IN_INV_SEL_V  0x1
+#define GPIO_FUNC69_IN_INV_SEL_S  5
+/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC69_IN_SEL  0x0000001F
+#define GPIO_FUNC69_IN_SEL_M  ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
+#define GPIO_FUNC69_IN_SEL_V  0x1F
+#define GPIO_FUNC69_IN_SEL_S  0
+
+#define GPIO_FUNC70_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x26C)
+/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG70_IN_SEL  (BIT(6))
+#define GPIO_SIG70_IN_SEL_M  (BIT(6))
+#define GPIO_SIG70_IN_SEL_V  0x1
+#define GPIO_SIG70_IN_SEL_S  6
+/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC70_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC70_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC70_IN_INV_SEL_V  0x1
+#define GPIO_FUNC70_IN_INV_SEL_S  5
+/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC70_IN_SEL  0x0000001F
+#define GPIO_FUNC70_IN_SEL_M  ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
+#define GPIO_FUNC70_IN_SEL_V  0x1F
+#define GPIO_FUNC70_IN_SEL_S  0
+
+#define GPIO_FUNC71_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x270)
+/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG71_IN_SEL  (BIT(6))
+#define GPIO_SIG71_IN_SEL_M  (BIT(6))
+#define GPIO_SIG71_IN_SEL_V  0x1
+#define GPIO_SIG71_IN_SEL_S  6
+/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC71_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC71_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC71_IN_INV_SEL_V  0x1
+#define GPIO_FUNC71_IN_INV_SEL_S  5
+/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC71_IN_SEL  0x0000001F
+#define GPIO_FUNC71_IN_SEL_M  ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
+#define GPIO_FUNC71_IN_SEL_V  0x1F
+#define GPIO_FUNC71_IN_SEL_S  0
+
+#define GPIO_FUNC72_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x274)
+/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG72_IN_SEL  (BIT(6))
+#define GPIO_SIG72_IN_SEL_M  (BIT(6))
+#define GPIO_SIG72_IN_SEL_V  0x1
+#define GPIO_SIG72_IN_SEL_S  6
+/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC72_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC72_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC72_IN_INV_SEL_V  0x1
+#define GPIO_FUNC72_IN_INV_SEL_S  5
+/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC72_IN_SEL  0x0000001F
+#define GPIO_FUNC72_IN_SEL_M  ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
+#define GPIO_FUNC72_IN_SEL_V  0x1F
+#define GPIO_FUNC72_IN_SEL_S  0
+
+#define GPIO_FUNC73_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x278)
+/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG73_IN_SEL  (BIT(6))
+#define GPIO_SIG73_IN_SEL_M  (BIT(6))
+#define GPIO_SIG73_IN_SEL_V  0x1
+#define GPIO_SIG73_IN_SEL_S  6
+/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC73_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC73_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC73_IN_INV_SEL_V  0x1
+#define GPIO_FUNC73_IN_INV_SEL_S  5
+/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC73_IN_SEL  0x0000001F
+#define GPIO_FUNC73_IN_SEL_M  ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
+#define GPIO_FUNC73_IN_SEL_V  0x1F
+#define GPIO_FUNC73_IN_SEL_S  0
+
+#define GPIO_FUNC74_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x27C)
+/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG74_IN_SEL  (BIT(6))
+#define GPIO_SIG74_IN_SEL_M  (BIT(6))
+#define GPIO_SIG74_IN_SEL_V  0x1
+#define GPIO_SIG74_IN_SEL_S  6
+/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC74_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC74_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC74_IN_INV_SEL_V  0x1
+#define GPIO_FUNC74_IN_INV_SEL_S  5
+/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC74_IN_SEL  0x0000001F
+#define GPIO_FUNC74_IN_SEL_M  ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
+#define GPIO_FUNC74_IN_SEL_V  0x1F
+#define GPIO_FUNC74_IN_SEL_S  0
+
+#define GPIO_FUNC75_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x280)
+/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG75_IN_SEL  (BIT(6))
+#define GPIO_SIG75_IN_SEL_M  (BIT(6))
+#define GPIO_SIG75_IN_SEL_V  0x1
+#define GPIO_SIG75_IN_SEL_S  6
+/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC75_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC75_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC75_IN_INV_SEL_V  0x1
+#define GPIO_FUNC75_IN_INV_SEL_S  5
+/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC75_IN_SEL  0x0000001F
+#define GPIO_FUNC75_IN_SEL_M  ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
+#define GPIO_FUNC75_IN_SEL_V  0x1F
+#define GPIO_FUNC75_IN_SEL_S  0
+
+#define GPIO_FUNC76_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x284)
+/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG76_IN_SEL  (BIT(6))
+#define GPIO_SIG76_IN_SEL_M  (BIT(6))
+#define GPIO_SIG76_IN_SEL_V  0x1
+#define GPIO_SIG76_IN_SEL_S  6
+/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC76_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC76_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC76_IN_INV_SEL_V  0x1
+#define GPIO_FUNC76_IN_INV_SEL_S  5
+/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC76_IN_SEL  0x0000001F
+#define GPIO_FUNC76_IN_SEL_M  ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
+#define GPIO_FUNC76_IN_SEL_V  0x1F
+#define GPIO_FUNC76_IN_SEL_S  0
+
+#define GPIO_FUNC77_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x288)
+/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG77_IN_SEL  (BIT(6))
+#define GPIO_SIG77_IN_SEL_M  (BIT(6))
+#define GPIO_SIG77_IN_SEL_V  0x1
+#define GPIO_SIG77_IN_SEL_S  6
+/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC77_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC77_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC77_IN_INV_SEL_V  0x1
+#define GPIO_FUNC77_IN_INV_SEL_S  5
+/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC77_IN_SEL  0x0000001F
+#define GPIO_FUNC77_IN_SEL_M  ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
+#define GPIO_FUNC77_IN_SEL_V  0x1F
+#define GPIO_FUNC77_IN_SEL_S  0
+
+#define GPIO_FUNC78_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x28C)
+/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG78_IN_SEL  (BIT(6))
+#define GPIO_SIG78_IN_SEL_M  (BIT(6))
+#define GPIO_SIG78_IN_SEL_V  0x1
+#define GPIO_SIG78_IN_SEL_S  6
+/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC78_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC78_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC78_IN_INV_SEL_V  0x1
+#define GPIO_FUNC78_IN_INV_SEL_S  5
+/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC78_IN_SEL  0x0000001F
+#define GPIO_FUNC78_IN_SEL_M  ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
+#define GPIO_FUNC78_IN_SEL_V  0x1F
+#define GPIO_FUNC78_IN_SEL_S  0
+
+#define GPIO_FUNC79_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x290)
+/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG79_IN_SEL  (BIT(6))
+#define GPIO_SIG79_IN_SEL_M  (BIT(6))
+#define GPIO_SIG79_IN_SEL_V  0x1
+#define GPIO_SIG79_IN_SEL_S  6
+/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC79_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC79_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC79_IN_INV_SEL_V  0x1
+#define GPIO_FUNC79_IN_INV_SEL_S  5
+/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC79_IN_SEL  0x0000001F
+#define GPIO_FUNC79_IN_SEL_M  ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
+#define GPIO_FUNC79_IN_SEL_V  0x1F
+#define GPIO_FUNC79_IN_SEL_S  0
+
+#define GPIO_FUNC80_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x294)
+/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG80_IN_SEL  (BIT(6))
+#define GPIO_SIG80_IN_SEL_M  (BIT(6))
+#define GPIO_SIG80_IN_SEL_V  0x1
+#define GPIO_SIG80_IN_SEL_S  6
+/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC80_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC80_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC80_IN_INV_SEL_V  0x1
+#define GPIO_FUNC80_IN_INV_SEL_S  5
+/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC80_IN_SEL  0x0000001F
+#define GPIO_FUNC80_IN_SEL_M  ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
+#define GPIO_FUNC80_IN_SEL_V  0x1F
+#define GPIO_FUNC80_IN_SEL_S  0
+
+#define GPIO_FUNC81_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x298)
+/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG81_IN_SEL  (BIT(6))
+#define GPIO_SIG81_IN_SEL_M  (BIT(6))
+#define GPIO_SIG81_IN_SEL_V  0x1
+#define GPIO_SIG81_IN_SEL_S  6
+/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC81_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC81_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC81_IN_INV_SEL_V  0x1
+#define GPIO_FUNC81_IN_INV_SEL_S  5
+/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC81_IN_SEL  0x0000001F
+#define GPIO_FUNC81_IN_SEL_M  ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
+#define GPIO_FUNC81_IN_SEL_V  0x1F
+#define GPIO_FUNC81_IN_SEL_S  0
+
+#define GPIO_FUNC82_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x29C)
+/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG82_IN_SEL  (BIT(6))
+#define GPIO_SIG82_IN_SEL_M  (BIT(6))
+#define GPIO_SIG82_IN_SEL_V  0x1
+#define GPIO_SIG82_IN_SEL_S  6
+/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC82_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC82_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC82_IN_INV_SEL_V  0x1
+#define GPIO_FUNC82_IN_INV_SEL_S  5
+/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC82_IN_SEL  0x0000001F
+#define GPIO_FUNC82_IN_SEL_M  ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
+#define GPIO_FUNC82_IN_SEL_V  0x1F
+#define GPIO_FUNC82_IN_SEL_S  0
+
+#define GPIO_FUNC83_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A0)
+/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG83_IN_SEL  (BIT(6))
+#define GPIO_SIG83_IN_SEL_M  (BIT(6))
+#define GPIO_SIG83_IN_SEL_V  0x1
+#define GPIO_SIG83_IN_SEL_S  6
+/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC83_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC83_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC83_IN_INV_SEL_V  0x1
+#define GPIO_FUNC83_IN_INV_SEL_S  5
+/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC83_IN_SEL  0x0000001F
+#define GPIO_FUNC83_IN_SEL_M  ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
+#define GPIO_FUNC83_IN_SEL_V  0x1F
+#define GPIO_FUNC83_IN_SEL_S  0
+
+#define GPIO_FUNC84_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A4)
+/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG84_IN_SEL  (BIT(6))
+#define GPIO_SIG84_IN_SEL_M  (BIT(6))
+#define GPIO_SIG84_IN_SEL_V  0x1
+#define GPIO_SIG84_IN_SEL_S  6
+/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC84_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC84_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC84_IN_INV_SEL_V  0x1
+#define GPIO_FUNC84_IN_INV_SEL_S  5
+/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC84_IN_SEL  0x0000001F
+#define GPIO_FUNC84_IN_SEL_M  ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
+#define GPIO_FUNC84_IN_SEL_V  0x1F
+#define GPIO_FUNC84_IN_SEL_S  0
+
+#define GPIO_FUNC85_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A8)
+/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG85_IN_SEL  (BIT(6))
+#define GPIO_SIG85_IN_SEL_M  (BIT(6))
+#define GPIO_SIG85_IN_SEL_V  0x1
+#define GPIO_SIG85_IN_SEL_S  6
+/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC85_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC85_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC85_IN_INV_SEL_V  0x1
+#define GPIO_FUNC85_IN_INV_SEL_S  5
+/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC85_IN_SEL  0x0000001F
+#define GPIO_FUNC85_IN_SEL_M  ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
+#define GPIO_FUNC85_IN_SEL_V  0x1F
+#define GPIO_FUNC85_IN_SEL_S  0
+
+#define GPIO_FUNC86_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2AC)
+/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG86_IN_SEL  (BIT(6))
+#define GPIO_SIG86_IN_SEL_M  (BIT(6))
+#define GPIO_SIG86_IN_SEL_V  0x1
+#define GPIO_SIG86_IN_SEL_S  6
+/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC86_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC86_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC86_IN_INV_SEL_V  0x1
+#define GPIO_FUNC86_IN_INV_SEL_S  5
+/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC86_IN_SEL  0x0000001F
+#define GPIO_FUNC86_IN_SEL_M  ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
+#define GPIO_FUNC86_IN_SEL_V  0x1F
+#define GPIO_FUNC86_IN_SEL_S  0
+
+#define GPIO_FUNC87_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B0)
+/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG87_IN_SEL  (BIT(6))
+#define GPIO_SIG87_IN_SEL_M  (BIT(6))
+#define GPIO_SIG87_IN_SEL_V  0x1
+#define GPIO_SIG87_IN_SEL_S  6
+/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC87_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC87_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC87_IN_INV_SEL_V  0x1
+#define GPIO_FUNC87_IN_INV_SEL_S  5
+/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC87_IN_SEL  0x0000001F
+#define GPIO_FUNC87_IN_SEL_M  ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
+#define GPIO_FUNC87_IN_SEL_V  0x1F
+#define GPIO_FUNC87_IN_SEL_S  0
+
+#define GPIO_FUNC88_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B4)
+/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG88_IN_SEL  (BIT(6))
+#define GPIO_SIG88_IN_SEL_M  (BIT(6))
+#define GPIO_SIG88_IN_SEL_V  0x1
+#define GPIO_SIG88_IN_SEL_S  6
+/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC88_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC88_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC88_IN_INV_SEL_V  0x1
+#define GPIO_FUNC88_IN_INV_SEL_S  5
+/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC88_IN_SEL  0x0000001F
+#define GPIO_FUNC88_IN_SEL_M  ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
+#define GPIO_FUNC88_IN_SEL_V  0x1F
+#define GPIO_FUNC88_IN_SEL_S  0
+
+#define GPIO_FUNC89_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B8)
+/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG89_IN_SEL  (BIT(6))
+#define GPIO_SIG89_IN_SEL_M  (BIT(6))
+#define GPIO_SIG89_IN_SEL_V  0x1
+#define GPIO_SIG89_IN_SEL_S  6
+/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC89_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC89_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC89_IN_INV_SEL_V  0x1
+#define GPIO_FUNC89_IN_INV_SEL_S  5
+/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC89_IN_SEL  0x0000001F
+#define GPIO_FUNC89_IN_SEL_M  ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
+#define GPIO_FUNC89_IN_SEL_V  0x1F
+#define GPIO_FUNC89_IN_SEL_S  0
+
+#define GPIO_FUNC90_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2BC)
+/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG90_IN_SEL  (BIT(6))
+#define GPIO_SIG90_IN_SEL_M  (BIT(6))
+#define GPIO_SIG90_IN_SEL_V  0x1
+#define GPIO_SIG90_IN_SEL_S  6
+/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC90_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC90_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC90_IN_INV_SEL_V  0x1
+#define GPIO_FUNC90_IN_INV_SEL_S  5
+/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC90_IN_SEL  0x0000001F
+#define GPIO_FUNC90_IN_SEL_M  ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
+#define GPIO_FUNC90_IN_SEL_V  0x1F
+#define GPIO_FUNC90_IN_SEL_S  0
+
+#define GPIO_FUNC91_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C0)
+/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG91_IN_SEL  (BIT(6))
+#define GPIO_SIG91_IN_SEL_M  (BIT(6))
+#define GPIO_SIG91_IN_SEL_V  0x1
+#define GPIO_SIG91_IN_SEL_S  6
+/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC91_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC91_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC91_IN_INV_SEL_V  0x1
+#define GPIO_FUNC91_IN_INV_SEL_S  5
+/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC91_IN_SEL  0x0000001F
+#define GPIO_FUNC91_IN_SEL_M  ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
+#define GPIO_FUNC91_IN_SEL_V  0x1F
+#define GPIO_FUNC91_IN_SEL_S  0
+
+#define GPIO_FUNC92_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C4)
+/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG92_IN_SEL  (BIT(6))
+#define GPIO_SIG92_IN_SEL_M  (BIT(6))
+#define GPIO_SIG92_IN_SEL_V  0x1
+#define GPIO_SIG92_IN_SEL_S  6
+/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC92_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC92_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC92_IN_INV_SEL_V  0x1
+#define GPIO_FUNC92_IN_INV_SEL_S  5
+/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC92_IN_SEL  0x0000001F
+#define GPIO_FUNC92_IN_SEL_M  ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
+#define GPIO_FUNC92_IN_SEL_V  0x1F
+#define GPIO_FUNC92_IN_SEL_S  0
+
+#define GPIO_FUNC93_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C8)
+/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG93_IN_SEL  (BIT(6))
+#define GPIO_SIG93_IN_SEL_M  (BIT(6))
+#define GPIO_SIG93_IN_SEL_V  0x1
+#define GPIO_SIG93_IN_SEL_S  6
+/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC93_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC93_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC93_IN_INV_SEL_V  0x1
+#define GPIO_FUNC93_IN_INV_SEL_S  5
+/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC93_IN_SEL  0x0000001F
+#define GPIO_FUNC93_IN_SEL_M  ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
+#define GPIO_FUNC93_IN_SEL_V  0x1F
+#define GPIO_FUNC93_IN_SEL_S  0
+
+#define GPIO_FUNC94_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2CC)
+/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG94_IN_SEL  (BIT(6))
+#define GPIO_SIG94_IN_SEL_M  (BIT(6))
+#define GPIO_SIG94_IN_SEL_V  0x1
+#define GPIO_SIG94_IN_SEL_S  6
+/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC94_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC94_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC94_IN_INV_SEL_V  0x1
+#define GPIO_FUNC94_IN_INV_SEL_S  5
+/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC94_IN_SEL  0x0000001F
+#define GPIO_FUNC94_IN_SEL_M  ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
+#define GPIO_FUNC94_IN_SEL_V  0x1F
+#define GPIO_FUNC94_IN_SEL_S  0
+
+#define GPIO_FUNC95_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D0)
+/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG95_IN_SEL  (BIT(6))
+#define GPIO_SIG95_IN_SEL_M  (BIT(6))
+#define GPIO_SIG95_IN_SEL_V  0x1
+#define GPIO_SIG95_IN_SEL_S  6
+/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC95_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC95_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC95_IN_INV_SEL_V  0x1
+#define GPIO_FUNC95_IN_INV_SEL_S  5
+/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC95_IN_SEL  0x0000001F
+#define GPIO_FUNC95_IN_SEL_M  ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
+#define GPIO_FUNC95_IN_SEL_V  0x1F
+#define GPIO_FUNC95_IN_SEL_S  0
+
+#define GPIO_FUNC96_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D4)
+/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG96_IN_SEL  (BIT(6))
+#define GPIO_SIG96_IN_SEL_M  (BIT(6))
+#define GPIO_SIG96_IN_SEL_V  0x1
+#define GPIO_SIG96_IN_SEL_S  6
+/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC96_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC96_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC96_IN_INV_SEL_V  0x1
+#define GPIO_FUNC96_IN_INV_SEL_S  5
+/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC96_IN_SEL  0x0000001F
+#define GPIO_FUNC96_IN_SEL_M  ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
+#define GPIO_FUNC96_IN_SEL_V  0x1F
+#define GPIO_FUNC96_IN_SEL_S  0
+
+#define GPIO_FUNC97_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D8)
+/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG97_IN_SEL  (BIT(6))
+#define GPIO_SIG97_IN_SEL_M  (BIT(6))
+#define GPIO_SIG97_IN_SEL_V  0x1
+#define GPIO_SIG97_IN_SEL_S  6
+/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC97_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC97_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC97_IN_INV_SEL_V  0x1
+#define GPIO_FUNC97_IN_INV_SEL_S  5
+/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC97_IN_SEL  0x0000001F
+#define GPIO_FUNC97_IN_SEL_M  ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
+#define GPIO_FUNC97_IN_SEL_V  0x1F
+#define GPIO_FUNC97_IN_SEL_S  0
+
+#define GPIO_FUNC98_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2DC)
+/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG98_IN_SEL  (BIT(6))
+#define GPIO_SIG98_IN_SEL_M  (BIT(6))
+#define GPIO_SIG98_IN_SEL_V  0x1
+#define GPIO_SIG98_IN_SEL_S  6
+/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC98_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC98_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC98_IN_INV_SEL_V  0x1
+#define GPIO_FUNC98_IN_INV_SEL_S  5
+/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC98_IN_SEL  0x0000001F
+#define GPIO_FUNC98_IN_SEL_M  ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
+#define GPIO_FUNC98_IN_SEL_V  0x1F
+#define GPIO_FUNC98_IN_SEL_S  0
+
+#define GPIO_FUNC99_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E0)
+/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG99_IN_SEL  (BIT(6))
+#define GPIO_SIG99_IN_SEL_M  (BIT(6))
+#define GPIO_SIG99_IN_SEL_V  0x1
+#define GPIO_SIG99_IN_SEL_S  6
+/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC99_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC99_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC99_IN_INV_SEL_V  0x1
+#define GPIO_FUNC99_IN_INV_SEL_S  5
+/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC99_IN_SEL  0x0000001F
+#define GPIO_FUNC99_IN_SEL_M  ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
+#define GPIO_FUNC99_IN_SEL_V  0x1F
+#define GPIO_FUNC99_IN_SEL_S  0
+
+#define GPIO_FUNC100_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E4)
+/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG100_IN_SEL  (BIT(6))
+#define GPIO_SIG100_IN_SEL_M  (BIT(6))
+#define GPIO_SIG100_IN_SEL_V  0x1
+#define GPIO_SIG100_IN_SEL_S  6
+/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC100_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC100_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC100_IN_INV_SEL_V  0x1
+#define GPIO_FUNC100_IN_INV_SEL_S  5
+/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC100_IN_SEL  0x0000001F
+#define GPIO_FUNC100_IN_SEL_M  ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
+#define GPIO_FUNC100_IN_SEL_V  0x1F
+#define GPIO_FUNC100_IN_SEL_S  0
+
+#define GPIO_FUNC101_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E8)
+/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG101_IN_SEL  (BIT(6))
+#define GPIO_SIG101_IN_SEL_M  (BIT(6))
+#define GPIO_SIG101_IN_SEL_V  0x1
+#define GPIO_SIG101_IN_SEL_S  6
+/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC101_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC101_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC101_IN_INV_SEL_V  0x1
+#define GPIO_FUNC101_IN_INV_SEL_S  5
+/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC101_IN_SEL  0x0000001F
+#define GPIO_FUNC101_IN_SEL_M  ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
+#define GPIO_FUNC101_IN_SEL_V  0x1F
+#define GPIO_FUNC101_IN_SEL_S  0
+
+#define GPIO_FUNC102_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2EC)
+/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG102_IN_SEL  (BIT(6))
+#define GPIO_SIG102_IN_SEL_M  (BIT(6))
+#define GPIO_SIG102_IN_SEL_V  0x1
+#define GPIO_SIG102_IN_SEL_S  6
+/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC102_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC102_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC102_IN_INV_SEL_V  0x1
+#define GPIO_FUNC102_IN_INV_SEL_S  5
+/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC102_IN_SEL  0x0000001F
+#define GPIO_FUNC102_IN_SEL_M  ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
+#define GPIO_FUNC102_IN_SEL_V  0x1F
+#define GPIO_FUNC102_IN_SEL_S  0
+
+#define GPIO_FUNC103_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F0)
+/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG103_IN_SEL  (BIT(6))
+#define GPIO_SIG103_IN_SEL_M  (BIT(6))
+#define GPIO_SIG103_IN_SEL_V  0x1
+#define GPIO_SIG103_IN_SEL_S  6
+/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC103_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC103_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC103_IN_INV_SEL_V  0x1
+#define GPIO_FUNC103_IN_INV_SEL_S  5
+/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC103_IN_SEL  0x0000001F
+#define GPIO_FUNC103_IN_SEL_M  ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
+#define GPIO_FUNC103_IN_SEL_V  0x1F
+#define GPIO_FUNC103_IN_SEL_S  0
+
+#define GPIO_FUNC104_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F4)
+/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG104_IN_SEL  (BIT(6))
+#define GPIO_SIG104_IN_SEL_M  (BIT(6))
+#define GPIO_SIG104_IN_SEL_V  0x1
+#define GPIO_SIG104_IN_SEL_S  6
+/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC104_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC104_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC104_IN_INV_SEL_V  0x1
+#define GPIO_FUNC104_IN_INV_SEL_S  5
+/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC104_IN_SEL  0x0000001F
+#define GPIO_FUNC104_IN_SEL_M  ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
+#define GPIO_FUNC104_IN_SEL_V  0x1F
+#define GPIO_FUNC104_IN_SEL_S  0
+
+#define GPIO_FUNC105_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F8)
+/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG105_IN_SEL  (BIT(6))
+#define GPIO_SIG105_IN_SEL_M  (BIT(6))
+#define GPIO_SIG105_IN_SEL_V  0x1
+#define GPIO_SIG105_IN_SEL_S  6
+/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC105_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC105_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC105_IN_INV_SEL_V  0x1
+#define GPIO_FUNC105_IN_INV_SEL_S  5
+/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC105_IN_SEL  0x0000001F
+#define GPIO_FUNC105_IN_SEL_M  ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
+#define GPIO_FUNC105_IN_SEL_V  0x1F
+#define GPIO_FUNC105_IN_SEL_S  0
+
+#define GPIO_FUNC106_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2FC)
+/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG106_IN_SEL  (BIT(6))
+#define GPIO_SIG106_IN_SEL_M  (BIT(6))
+#define GPIO_SIG106_IN_SEL_V  0x1
+#define GPIO_SIG106_IN_SEL_S  6
+/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC106_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC106_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC106_IN_INV_SEL_V  0x1
+#define GPIO_FUNC106_IN_INV_SEL_S  5
+/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC106_IN_SEL  0x0000001F
+#define GPIO_FUNC106_IN_SEL_M  ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
+#define GPIO_FUNC106_IN_SEL_V  0x1F
+#define GPIO_FUNC106_IN_SEL_S  0
+
+#define GPIO_FUNC107_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x300)
+/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG107_IN_SEL  (BIT(6))
+#define GPIO_SIG107_IN_SEL_M  (BIT(6))
+#define GPIO_SIG107_IN_SEL_V  0x1
+#define GPIO_SIG107_IN_SEL_S  6
+/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC107_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC107_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC107_IN_INV_SEL_V  0x1
+#define GPIO_FUNC107_IN_INV_SEL_S  5
+/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC107_IN_SEL  0x0000001F
+#define GPIO_FUNC107_IN_SEL_M  ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
+#define GPIO_FUNC107_IN_SEL_V  0x1F
+#define GPIO_FUNC107_IN_SEL_S  0
+
+#define GPIO_FUNC108_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x304)
+/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG108_IN_SEL  (BIT(6))
+#define GPIO_SIG108_IN_SEL_M  (BIT(6))
+#define GPIO_SIG108_IN_SEL_V  0x1
+#define GPIO_SIG108_IN_SEL_S  6
+/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC108_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC108_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC108_IN_INV_SEL_V  0x1
+#define GPIO_FUNC108_IN_INV_SEL_S  5
+/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC108_IN_SEL  0x0000001F
+#define GPIO_FUNC108_IN_SEL_M  ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
+#define GPIO_FUNC108_IN_SEL_V  0x1F
+#define GPIO_FUNC108_IN_SEL_S  0
+
+#define GPIO_FUNC109_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x308)
+/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG109_IN_SEL  (BIT(6))
+#define GPIO_SIG109_IN_SEL_M  (BIT(6))
+#define GPIO_SIG109_IN_SEL_V  0x1
+#define GPIO_SIG109_IN_SEL_S  6
+/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC109_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC109_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC109_IN_INV_SEL_V  0x1
+#define GPIO_FUNC109_IN_INV_SEL_S  5
+/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC109_IN_SEL  0x0000001F
+#define GPIO_FUNC109_IN_SEL_M  ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
+#define GPIO_FUNC109_IN_SEL_V  0x1F
+#define GPIO_FUNC109_IN_SEL_S  0
+
+#define GPIO_FUNC110_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x30C)
+/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG110_IN_SEL  (BIT(6))
+#define GPIO_SIG110_IN_SEL_M  (BIT(6))
+#define GPIO_SIG110_IN_SEL_V  0x1
+#define GPIO_SIG110_IN_SEL_S  6
+/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC110_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC110_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC110_IN_INV_SEL_V  0x1
+#define GPIO_FUNC110_IN_INV_SEL_S  5
+/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC110_IN_SEL  0x0000001F
+#define GPIO_FUNC110_IN_SEL_M  ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
+#define GPIO_FUNC110_IN_SEL_V  0x1F
+#define GPIO_FUNC110_IN_SEL_S  0
+
+#define GPIO_FUNC111_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x310)
+/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG111_IN_SEL  (BIT(6))
+#define GPIO_SIG111_IN_SEL_M  (BIT(6))
+#define GPIO_SIG111_IN_SEL_V  0x1
+#define GPIO_SIG111_IN_SEL_S  6
+/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC111_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC111_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC111_IN_INV_SEL_V  0x1
+#define GPIO_FUNC111_IN_INV_SEL_S  5
+/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC111_IN_SEL  0x0000001F
+#define GPIO_FUNC111_IN_SEL_M  ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
+#define GPIO_FUNC111_IN_SEL_V  0x1F
+#define GPIO_FUNC111_IN_SEL_S  0
+
+#define GPIO_FUNC112_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x314)
+/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG112_IN_SEL  (BIT(6))
+#define GPIO_SIG112_IN_SEL_M  (BIT(6))
+#define GPIO_SIG112_IN_SEL_V  0x1
+#define GPIO_SIG112_IN_SEL_S  6
+/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC112_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC112_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC112_IN_INV_SEL_V  0x1
+#define GPIO_FUNC112_IN_INV_SEL_S  5
+/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC112_IN_SEL  0x0000001F
+#define GPIO_FUNC112_IN_SEL_M  ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
+#define GPIO_FUNC112_IN_SEL_V  0x1F
+#define GPIO_FUNC112_IN_SEL_S  0
+
+#define GPIO_FUNC113_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x318)
+/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG113_IN_SEL  (BIT(6))
+#define GPIO_SIG113_IN_SEL_M  (BIT(6))
+#define GPIO_SIG113_IN_SEL_V  0x1
+#define GPIO_SIG113_IN_SEL_S  6
+/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC113_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC113_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC113_IN_INV_SEL_V  0x1
+#define GPIO_FUNC113_IN_INV_SEL_S  5
+/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC113_IN_SEL  0x0000001F
+#define GPIO_FUNC113_IN_SEL_M  ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
+#define GPIO_FUNC113_IN_SEL_V  0x1F
+#define GPIO_FUNC113_IN_SEL_S  0
+
+#define GPIO_FUNC114_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x31C)
+/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG114_IN_SEL  (BIT(6))
+#define GPIO_SIG114_IN_SEL_M  (BIT(6))
+#define GPIO_SIG114_IN_SEL_V  0x1
+#define GPIO_SIG114_IN_SEL_S  6
+/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC114_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC114_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC114_IN_INV_SEL_V  0x1
+#define GPIO_FUNC114_IN_INV_SEL_S  5
+/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC114_IN_SEL  0x0000001F
+#define GPIO_FUNC114_IN_SEL_M  ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
+#define GPIO_FUNC114_IN_SEL_V  0x1F
+#define GPIO_FUNC114_IN_SEL_S  0
+
+#define GPIO_FUNC115_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x320)
+/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG115_IN_SEL  (BIT(6))
+#define GPIO_SIG115_IN_SEL_M  (BIT(6))
+#define GPIO_SIG115_IN_SEL_V  0x1
+#define GPIO_SIG115_IN_SEL_S  6
+/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC115_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC115_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC115_IN_INV_SEL_V  0x1
+#define GPIO_FUNC115_IN_INV_SEL_S  5
+/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC115_IN_SEL  0x0000001F
+#define GPIO_FUNC115_IN_SEL_M  ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
+#define GPIO_FUNC115_IN_SEL_V  0x1F
+#define GPIO_FUNC115_IN_SEL_S  0
+
+#define GPIO_FUNC116_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x324)
+/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG116_IN_SEL  (BIT(6))
+#define GPIO_SIG116_IN_SEL_M  (BIT(6))
+#define GPIO_SIG116_IN_SEL_V  0x1
+#define GPIO_SIG116_IN_SEL_S  6
+/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC116_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC116_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC116_IN_INV_SEL_V  0x1
+#define GPIO_FUNC116_IN_INV_SEL_S  5
+/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC116_IN_SEL  0x0000001F
+#define GPIO_FUNC116_IN_SEL_M  ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
+#define GPIO_FUNC116_IN_SEL_V  0x1F
+#define GPIO_FUNC116_IN_SEL_S  0
+
+#define GPIO_FUNC117_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x328)
+/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG117_IN_SEL  (BIT(6))
+#define GPIO_SIG117_IN_SEL_M  (BIT(6))
+#define GPIO_SIG117_IN_SEL_V  0x1
+#define GPIO_SIG117_IN_SEL_S  6
+/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC117_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC117_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC117_IN_INV_SEL_V  0x1
+#define GPIO_FUNC117_IN_INV_SEL_S  5
+/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC117_IN_SEL  0x0000001F
+#define GPIO_FUNC117_IN_SEL_M  ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
+#define GPIO_FUNC117_IN_SEL_V  0x1F
+#define GPIO_FUNC117_IN_SEL_S  0
+
+#define GPIO_FUNC118_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x32C)
+/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG118_IN_SEL  (BIT(6))
+#define GPIO_SIG118_IN_SEL_M  (BIT(6))
+#define GPIO_SIG118_IN_SEL_V  0x1
+#define GPIO_SIG118_IN_SEL_S  6
+/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC118_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC118_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC118_IN_INV_SEL_V  0x1
+#define GPIO_FUNC118_IN_INV_SEL_S  5
+/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC118_IN_SEL  0x0000001F
+#define GPIO_FUNC118_IN_SEL_M  ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
+#define GPIO_FUNC118_IN_SEL_V  0x1F
+#define GPIO_FUNC118_IN_SEL_S  0
+
+#define GPIO_FUNC119_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x330)
+/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG119_IN_SEL  (BIT(6))
+#define GPIO_SIG119_IN_SEL_M  (BIT(6))
+#define GPIO_SIG119_IN_SEL_V  0x1
+#define GPIO_SIG119_IN_SEL_S  6
+/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC119_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC119_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC119_IN_INV_SEL_V  0x1
+#define GPIO_FUNC119_IN_INV_SEL_S  5
+/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC119_IN_SEL  0x0000001F
+#define GPIO_FUNC119_IN_SEL_M  ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
+#define GPIO_FUNC119_IN_SEL_V  0x1F
+#define GPIO_FUNC119_IN_SEL_S  0
+
+#define GPIO_FUNC120_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x334)
+/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG120_IN_SEL  (BIT(6))
+#define GPIO_SIG120_IN_SEL_M  (BIT(6))
+#define GPIO_SIG120_IN_SEL_V  0x1
+#define GPIO_SIG120_IN_SEL_S  6
+/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC120_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC120_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC120_IN_INV_SEL_V  0x1
+#define GPIO_FUNC120_IN_INV_SEL_S  5
+/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC120_IN_SEL  0x0000001F
+#define GPIO_FUNC120_IN_SEL_M  ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
+#define GPIO_FUNC120_IN_SEL_V  0x1F
+#define GPIO_FUNC120_IN_SEL_S  0
+
+#define GPIO_FUNC121_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x338)
+/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG121_IN_SEL  (BIT(6))
+#define GPIO_SIG121_IN_SEL_M  (BIT(6))
+#define GPIO_SIG121_IN_SEL_V  0x1
+#define GPIO_SIG121_IN_SEL_S  6
+/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC121_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC121_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC121_IN_INV_SEL_V  0x1
+#define GPIO_FUNC121_IN_INV_SEL_S  5
+/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC121_IN_SEL  0x0000001F
+#define GPIO_FUNC121_IN_SEL_M  ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
+#define GPIO_FUNC121_IN_SEL_V  0x1F
+#define GPIO_FUNC121_IN_SEL_S  0
+
+#define GPIO_FUNC122_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x33C)
+/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG122_IN_SEL  (BIT(6))
+#define GPIO_SIG122_IN_SEL_M  (BIT(6))
+#define GPIO_SIG122_IN_SEL_V  0x1
+#define GPIO_SIG122_IN_SEL_S  6
+/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC122_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC122_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC122_IN_INV_SEL_V  0x1
+#define GPIO_FUNC122_IN_INV_SEL_S  5
+/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC122_IN_SEL  0x0000001F
+#define GPIO_FUNC122_IN_SEL_M  ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
+#define GPIO_FUNC122_IN_SEL_V  0x1F
+#define GPIO_FUNC122_IN_SEL_S  0
+
+#define GPIO_FUNC123_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x340)
+/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG123_IN_SEL  (BIT(6))
+#define GPIO_SIG123_IN_SEL_M  (BIT(6))
+#define GPIO_SIG123_IN_SEL_V  0x1
+#define GPIO_SIG123_IN_SEL_S  6
+/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC123_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC123_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC123_IN_INV_SEL_V  0x1
+#define GPIO_FUNC123_IN_INV_SEL_S  5
+/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC123_IN_SEL  0x0000001F
+#define GPIO_FUNC123_IN_SEL_M  ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
+#define GPIO_FUNC123_IN_SEL_V  0x1F
+#define GPIO_FUNC123_IN_SEL_S  0
+
+#define GPIO_FUNC124_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x344)
+/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG124_IN_SEL  (BIT(6))
+#define GPIO_SIG124_IN_SEL_M  (BIT(6))
+#define GPIO_SIG124_IN_SEL_V  0x1
+#define GPIO_SIG124_IN_SEL_S  6
+/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC124_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC124_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC124_IN_INV_SEL_V  0x1
+#define GPIO_FUNC124_IN_INV_SEL_S  5
+/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC124_IN_SEL  0x0000001F
+#define GPIO_FUNC124_IN_SEL_M  ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
+#define GPIO_FUNC124_IN_SEL_V  0x1F
+#define GPIO_FUNC124_IN_SEL_S  0
+
+#define GPIO_FUNC125_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x348)
+/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG125_IN_SEL  (BIT(6))
+#define GPIO_SIG125_IN_SEL_M  (BIT(6))
+#define GPIO_SIG125_IN_SEL_V  0x1
+#define GPIO_SIG125_IN_SEL_S  6
+/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC125_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC125_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC125_IN_INV_SEL_V  0x1
+#define GPIO_FUNC125_IN_INV_SEL_S  5
+/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC125_IN_SEL  0x0000001F
+#define GPIO_FUNC125_IN_SEL_M  ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
+#define GPIO_FUNC125_IN_SEL_V  0x1F
+#define GPIO_FUNC125_IN_SEL_S  0
+
+#define GPIO_FUNC126_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x34C)
+/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG126_IN_SEL  (BIT(6))
+#define GPIO_SIG126_IN_SEL_M  (BIT(6))
+#define GPIO_SIG126_IN_SEL_V  0x1
+#define GPIO_SIG126_IN_SEL_S  6
+/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC126_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC126_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC126_IN_INV_SEL_V  0x1
+#define GPIO_FUNC126_IN_INV_SEL_S  5
+/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC126_IN_SEL  0x0000001F
+#define GPIO_FUNC126_IN_SEL_M  ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
+#define GPIO_FUNC126_IN_SEL_V  0x1F
+#define GPIO_FUNC126_IN_SEL_S  0
+
+#define GPIO_FUNC127_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x350)
+/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG127_IN_SEL  (BIT(6))
+#define GPIO_SIG127_IN_SEL_M  (BIT(6))
+#define GPIO_SIG127_IN_SEL_V  0x1
+#define GPIO_SIG127_IN_SEL_S  6
+/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC127_IN_INV_SEL  (BIT(5))
+#define GPIO_FUNC127_IN_INV_SEL_M  (BIT(5))
+#define GPIO_FUNC127_IN_INV_SEL_V  0x1
+#define GPIO_FUNC127_IN_INV_SEL_S  5
+/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_FUNC127_IN_SEL  0x0000001F
+#define GPIO_FUNC127_IN_SEL_M  ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
+#define GPIO_FUNC127_IN_SEL_V  0x1F
+#define GPIO_FUNC127_IN_SEL_S  0
+
+#define GPIO_FUNC0_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x554)
+/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC0_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC0_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC0_OEN_INV_SEL_S  10
+/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OEN_SEL  (BIT(9))
+#define GPIO_FUNC0_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC0_OEN_SEL_V  0x1
+#define GPIO_FUNC0_OEN_SEL_S  9
+/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC0_OUT_INV_SEL_S  8
+/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC0_OUT_SEL  0x000000FF
+#define GPIO_FUNC0_OUT_SEL_M  ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
+#define GPIO_FUNC0_OUT_SEL_V  0xFF
+#define GPIO_FUNC0_OUT_SEL_S  0
+
+#define GPIO_FUNC1_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x558)
+/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC1_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC1_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC1_OEN_INV_SEL_S  10
+/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OEN_SEL  (BIT(9))
+#define GPIO_FUNC1_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC1_OEN_SEL_V  0x1
+#define GPIO_FUNC1_OEN_SEL_S  9
+/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC1_OUT_INV_SEL_S  8
+/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC1_OUT_SEL  0x000000FF
+#define GPIO_FUNC1_OUT_SEL_M  ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
+#define GPIO_FUNC1_OUT_SEL_V  0xFF
+#define GPIO_FUNC1_OUT_SEL_S  0
+
+#define GPIO_FUNC2_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x55C)
+/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC2_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC2_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC2_OEN_INV_SEL_S  10
+/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OEN_SEL  (BIT(9))
+#define GPIO_FUNC2_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC2_OEN_SEL_V  0x1
+#define GPIO_FUNC2_OEN_SEL_S  9
+/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC2_OUT_INV_SEL_S  8
+/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC2_OUT_SEL  0x000000FF
+#define GPIO_FUNC2_OUT_SEL_M  ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
+#define GPIO_FUNC2_OUT_SEL_V  0xFF
+#define GPIO_FUNC2_OUT_SEL_S  0
+
+#define GPIO_FUNC3_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x560)
+/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC3_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC3_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC3_OEN_INV_SEL_S  10
+/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OEN_SEL  (BIT(9))
+#define GPIO_FUNC3_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC3_OEN_SEL_V  0x1
+#define GPIO_FUNC3_OEN_SEL_S  9
+/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC3_OUT_INV_SEL_S  8
+/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC3_OUT_SEL  0x000000FF
+#define GPIO_FUNC3_OUT_SEL_M  ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
+#define GPIO_FUNC3_OUT_SEL_V  0xFF
+#define GPIO_FUNC3_OUT_SEL_S  0
+
+#define GPIO_FUNC4_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x564)
+/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC4_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC4_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC4_OEN_INV_SEL_S  10
+/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OEN_SEL  (BIT(9))
+#define GPIO_FUNC4_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC4_OEN_SEL_V  0x1
+#define GPIO_FUNC4_OEN_SEL_S  9
+/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC4_OUT_INV_SEL_S  8
+/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC4_OUT_SEL  0x000000FF
+#define GPIO_FUNC4_OUT_SEL_M  ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
+#define GPIO_FUNC4_OUT_SEL_V  0xFF
+#define GPIO_FUNC4_OUT_SEL_S  0
+
+#define GPIO_FUNC5_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x568)
+/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC5_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC5_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC5_OEN_INV_SEL_S  10
+/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OEN_SEL  (BIT(9))
+#define GPIO_FUNC5_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC5_OEN_SEL_V  0x1
+#define GPIO_FUNC5_OEN_SEL_S  9
+/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC5_OUT_INV_SEL_S  8
+/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC5_OUT_SEL  0x000000FF
+#define GPIO_FUNC5_OUT_SEL_M  ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
+#define GPIO_FUNC5_OUT_SEL_V  0xFF
+#define GPIO_FUNC5_OUT_SEL_S  0
+
+#define GPIO_FUNC6_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x56C)
+/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC6_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC6_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC6_OEN_INV_SEL_S  10
+/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OEN_SEL  (BIT(9))
+#define GPIO_FUNC6_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC6_OEN_SEL_V  0x1
+#define GPIO_FUNC6_OEN_SEL_S  9
+/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC6_OUT_INV_SEL_S  8
+/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC6_OUT_SEL  0x000000FF
+#define GPIO_FUNC6_OUT_SEL_M  ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
+#define GPIO_FUNC6_OUT_SEL_V  0xFF
+#define GPIO_FUNC6_OUT_SEL_S  0
+
+#define GPIO_FUNC7_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x570)
+/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC7_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC7_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC7_OEN_INV_SEL_S  10
+/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OEN_SEL  (BIT(9))
+#define GPIO_FUNC7_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC7_OEN_SEL_V  0x1
+#define GPIO_FUNC7_OEN_SEL_S  9
+/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC7_OUT_INV_SEL_S  8
+/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC7_OUT_SEL  0x000000FF
+#define GPIO_FUNC7_OUT_SEL_M  ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
+#define GPIO_FUNC7_OUT_SEL_V  0xFF
+#define GPIO_FUNC7_OUT_SEL_S  0
+
+#define GPIO_FUNC8_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x574)
+/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC8_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC8_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC8_OEN_INV_SEL_S  10
+/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OEN_SEL  (BIT(9))
+#define GPIO_FUNC8_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC8_OEN_SEL_V  0x1
+#define GPIO_FUNC8_OEN_SEL_S  9
+/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC8_OUT_INV_SEL_S  8
+/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC8_OUT_SEL  0x000000FF
+#define GPIO_FUNC8_OUT_SEL_M  ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
+#define GPIO_FUNC8_OUT_SEL_V  0xFF
+#define GPIO_FUNC8_OUT_SEL_S  0
+
+#define GPIO_FUNC9_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x578)
+/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC9_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC9_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC9_OEN_INV_SEL_S  10
+/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OEN_SEL  (BIT(9))
+#define GPIO_FUNC9_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC9_OEN_SEL_V  0x1
+#define GPIO_FUNC9_OEN_SEL_S  9
+/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC9_OUT_INV_SEL_S  8
+/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC9_OUT_SEL  0x000000FF
+#define GPIO_FUNC9_OUT_SEL_M  ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
+#define GPIO_FUNC9_OUT_SEL_V  0xFF
+#define GPIO_FUNC9_OUT_SEL_S  0
+
+#define GPIO_FUNC10_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x57C)
+/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC10_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC10_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC10_OEN_INV_SEL_S  10
+/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OEN_SEL  (BIT(9))
+#define GPIO_FUNC10_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC10_OEN_SEL_V  0x1
+#define GPIO_FUNC10_OEN_SEL_S  9
+/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC10_OUT_INV_SEL_S  8
+/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC10_OUT_SEL  0x000000FF
+#define GPIO_FUNC10_OUT_SEL_M  ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
+#define GPIO_FUNC10_OUT_SEL_V  0xFF
+#define GPIO_FUNC10_OUT_SEL_S  0
+
+#define GPIO_FUNC11_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x580)
+/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC11_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC11_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC11_OEN_INV_SEL_S  10
+/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OEN_SEL  (BIT(9))
+#define GPIO_FUNC11_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC11_OEN_SEL_V  0x1
+#define GPIO_FUNC11_OEN_SEL_S  9
+/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC11_OUT_INV_SEL_S  8
+/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC11_OUT_SEL  0x000000FF
+#define GPIO_FUNC11_OUT_SEL_M  ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
+#define GPIO_FUNC11_OUT_SEL_V  0xFF
+#define GPIO_FUNC11_OUT_SEL_S  0
+
+#define GPIO_FUNC12_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x584)
+/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC12_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC12_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC12_OEN_INV_SEL_S  10
+/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OEN_SEL  (BIT(9))
+#define GPIO_FUNC12_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC12_OEN_SEL_V  0x1
+#define GPIO_FUNC12_OEN_SEL_S  9
+/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC12_OUT_INV_SEL_S  8
+/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC12_OUT_SEL  0x000000FF
+#define GPIO_FUNC12_OUT_SEL_M  ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
+#define GPIO_FUNC12_OUT_SEL_V  0xFF
+#define GPIO_FUNC12_OUT_SEL_S  0
+
+#define GPIO_FUNC13_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x588)
+/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC13_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC13_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC13_OEN_INV_SEL_S  10
+/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OEN_SEL  (BIT(9))
+#define GPIO_FUNC13_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC13_OEN_SEL_V  0x1
+#define GPIO_FUNC13_OEN_SEL_S  9
+/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC13_OUT_INV_SEL_S  8
+/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC13_OUT_SEL  0x000000FF
+#define GPIO_FUNC13_OUT_SEL_M  ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
+#define GPIO_FUNC13_OUT_SEL_V  0xFF
+#define GPIO_FUNC13_OUT_SEL_S  0
+
+#define GPIO_FUNC14_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x58C)
+/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC14_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC14_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC14_OEN_INV_SEL_S  10
+/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OEN_SEL  (BIT(9))
+#define GPIO_FUNC14_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC14_OEN_SEL_V  0x1
+#define GPIO_FUNC14_OEN_SEL_S  9
+/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC14_OUT_INV_SEL_S  8
+/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC14_OUT_SEL  0x000000FF
+#define GPIO_FUNC14_OUT_SEL_M  ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
+#define GPIO_FUNC14_OUT_SEL_V  0xFF
+#define GPIO_FUNC14_OUT_SEL_S  0
+
+#define GPIO_FUNC15_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x590)
+/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC15_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC15_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC15_OEN_INV_SEL_S  10
+/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OEN_SEL  (BIT(9))
+#define GPIO_FUNC15_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC15_OEN_SEL_V  0x1
+#define GPIO_FUNC15_OEN_SEL_S  9
+/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC15_OUT_INV_SEL_S  8
+/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC15_OUT_SEL  0x000000FF
+#define GPIO_FUNC15_OUT_SEL_M  ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
+#define GPIO_FUNC15_OUT_SEL_V  0xFF
+#define GPIO_FUNC15_OUT_SEL_S  0
+
+#define GPIO_FUNC16_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x594)
+/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC16_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC16_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC16_OEN_INV_SEL_S  10
+/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OEN_SEL  (BIT(9))
+#define GPIO_FUNC16_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC16_OEN_SEL_V  0x1
+#define GPIO_FUNC16_OEN_SEL_S  9
+/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC16_OUT_INV_SEL_S  8
+/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC16_OUT_SEL  0x000000FF
+#define GPIO_FUNC16_OUT_SEL_M  ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
+#define GPIO_FUNC16_OUT_SEL_V  0xFF
+#define GPIO_FUNC16_OUT_SEL_S  0
+
+#define GPIO_FUNC17_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x598)
+/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC17_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC17_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC17_OEN_INV_SEL_S  10
+/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OEN_SEL  (BIT(9))
+#define GPIO_FUNC17_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC17_OEN_SEL_V  0x1
+#define GPIO_FUNC17_OEN_SEL_S  9
+/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC17_OUT_INV_SEL_S  8
+/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC17_OUT_SEL  0x000000FF
+#define GPIO_FUNC17_OUT_SEL_M  ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
+#define GPIO_FUNC17_OUT_SEL_V  0xFF
+#define GPIO_FUNC17_OUT_SEL_S  0
+
+#define GPIO_FUNC18_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x59C)
+/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC18_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC18_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC18_OEN_INV_SEL_S  10
+/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OEN_SEL  (BIT(9))
+#define GPIO_FUNC18_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC18_OEN_SEL_V  0x1
+#define GPIO_FUNC18_OEN_SEL_S  9
+/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC18_OUT_INV_SEL_S  8
+/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC18_OUT_SEL  0x000000FF
+#define GPIO_FUNC18_OUT_SEL_M  ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
+#define GPIO_FUNC18_OUT_SEL_V  0xFF
+#define GPIO_FUNC18_OUT_SEL_S  0
+
+#define GPIO_FUNC19_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A0)
+/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC19_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC19_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC19_OEN_INV_SEL_S  10
+/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OEN_SEL  (BIT(9))
+#define GPIO_FUNC19_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC19_OEN_SEL_V  0x1
+#define GPIO_FUNC19_OEN_SEL_S  9
+/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC19_OUT_INV_SEL_S  8
+/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC19_OUT_SEL  0x000000FF
+#define GPIO_FUNC19_OUT_SEL_M  ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
+#define GPIO_FUNC19_OUT_SEL_V  0xFF
+#define GPIO_FUNC19_OUT_SEL_S  0
+
+#define GPIO_FUNC20_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A4)
+/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC20_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC20_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC20_OEN_INV_SEL_S  10
+/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OEN_SEL  (BIT(9))
+#define GPIO_FUNC20_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC20_OEN_SEL_V  0x1
+#define GPIO_FUNC20_OEN_SEL_S  9
+/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC20_OUT_INV_SEL_S  8
+/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC20_OUT_SEL  0x000000FF
+#define GPIO_FUNC20_OUT_SEL_M  ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
+#define GPIO_FUNC20_OUT_SEL_V  0xFF
+#define GPIO_FUNC20_OUT_SEL_S  0
+
+#define GPIO_FUNC21_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A8)
+/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC21_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC21_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC21_OEN_INV_SEL_S  10
+/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OEN_SEL  (BIT(9))
+#define GPIO_FUNC21_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC21_OEN_SEL_V  0x1
+#define GPIO_FUNC21_OEN_SEL_S  9
+/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC21_OUT_INV_SEL_S  8
+/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC21_OUT_SEL  0x000000FF
+#define GPIO_FUNC21_OUT_SEL_M  ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
+#define GPIO_FUNC21_OUT_SEL_V  0xFF
+#define GPIO_FUNC21_OUT_SEL_S  0
+
+#define GPIO_FUNC22_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5AC)
+/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC22_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC22_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC22_OEN_INV_SEL_S  10
+/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OEN_SEL  (BIT(9))
+#define GPIO_FUNC22_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC22_OEN_SEL_V  0x1
+#define GPIO_FUNC22_OEN_SEL_S  9
+/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC22_OUT_INV_SEL_S  8
+/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC22_OUT_SEL  0x000000FF
+#define GPIO_FUNC22_OUT_SEL_M  ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
+#define GPIO_FUNC22_OUT_SEL_V  0xFF
+#define GPIO_FUNC22_OUT_SEL_S  0
+
+#define GPIO_FUNC23_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B0)
+/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC23_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC23_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC23_OEN_INV_SEL_S  10
+/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OEN_SEL  (BIT(9))
+#define GPIO_FUNC23_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC23_OEN_SEL_V  0x1
+#define GPIO_FUNC23_OEN_SEL_S  9
+/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC23_OUT_INV_SEL_S  8
+/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC23_OUT_SEL  0x000000FF
+#define GPIO_FUNC23_OUT_SEL_M  ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
+#define GPIO_FUNC23_OUT_SEL_V  0xFF
+#define GPIO_FUNC23_OUT_SEL_S  0
+
+#define GPIO_FUNC24_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B4)
+/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC24_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC24_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC24_OEN_INV_SEL_S  10
+/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OEN_SEL  (BIT(9))
+#define GPIO_FUNC24_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC24_OEN_SEL_V  0x1
+#define GPIO_FUNC24_OEN_SEL_S  9
+/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC24_OUT_INV_SEL_S  8
+/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC24_OUT_SEL  0x000000FF
+#define GPIO_FUNC24_OUT_SEL_M  ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
+#define GPIO_FUNC24_OUT_SEL_V  0xFF
+#define GPIO_FUNC24_OUT_SEL_S  0
+
+#define GPIO_FUNC25_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B8)
+/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OEN_INV_SEL  (BIT(10))
+#define GPIO_FUNC25_OEN_INV_SEL_M  (BIT(10))
+#define GPIO_FUNC25_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC25_OEN_INV_SEL_S  10
+/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OEN_SEL  (BIT(9))
+#define GPIO_FUNC25_OEN_SEL_M  (BIT(9))
+#define GPIO_FUNC25_OEN_SEL_V  0x1
+#define GPIO_FUNC25_OEN_SEL_S  9
+/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OUT_INV_SEL  (BIT(8))
+#define GPIO_FUNC25_OUT_INV_SEL_M  (BIT(8))
+#define GPIO_FUNC25_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC25_OUT_INV_SEL_S  8
+/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */
+/*description: */
+#define GPIO_FUNC25_OUT_SEL  0x000000FF
+#define GPIO_FUNC25_OUT_SEL_M  ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
+#define GPIO_FUNC25_OUT_SEL_V  0xFF
+#define GPIO_FUNC25_OUT_SEL_S  0
+
+#define GPIO_CLOCK_GATE_REG          (DR_REG_GPIO_BASE + 0x62C)
+/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define GPIO_CLK_EN  (BIT(0))
+#define GPIO_CLK_EN_M  (BIT(0))
+#define GPIO_CLK_EN_V  0x1
+#define GPIO_CLK_EN_S  0
+
+#define GPIO_DATE_REG          (DR_REG_GPIO_BASE + 0x6FC)
+/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006130 ; */
+/*description: */
+#define GPIO_DATE  0x0FFFFFFF
+#define GPIO_DATE_M  ((GPIO_DATE_V)<<(GPIO_DATE_S))
+#define GPIO_DATE_V  0xFFFFFFF
+#define GPIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_GPIO_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/gpio_sd_reg.h b/components/soc/esp32c3/register/soc/gpio_sd_reg.h
new file mode 100644
index 00000000000..57d66a44c0c
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/gpio_sd_reg.h
@@ -0,0 +1,102 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0000)
+/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD0_PRESCALE  0x000000FF
+#define GPIO_SD0_PRESCALE_M  ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
+#define GPIO_SD0_PRESCALE_V  0xFF
+#define GPIO_SD0_PRESCALE_S  8
+/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD0_IN  0x000000FF
+#define GPIO_SD0_IN_M  ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
+#define GPIO_SD0_IN_V  0xFF
+#define GPIO_SD0_IN_S  0
+
+#define GPIO_SIGMADELTA1_REG          (DR_REG_GPIO_SD_BASE + 0x0004)
+/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD1_PRESCALE  0x000000FF
+#define GPIO_SD1_PRESCALE_M  ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
+#define GPIO_SD1_PRESCALE_V  0xFF
+#define GPIO_SD1_PRESCALE_S  8
+/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD1_IN  0x000000FF
+#define GPIO_SD1_IN_M  ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
+#define GPIO_SD1_IN_V  0xFF
+#define GPIO_SD1_IN_S  0
+
+#define GPIO_SIGMADELTA2_REG          (DR_REG_GPIO_SD_BASE + 0x0008)
+/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD2_PRESCALE  0x000000FF
+#define GPIO_SD2_PRESCALE_M  ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
+#define GPIO_SD2_PRESCALE_V  0xFF
+#define GPIO_SD2_PRESCALE_S  8
+/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD2_IN  0x000000FF
+#define GPIO_SD2_IN_M  ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
+#define GPIO_SD2_IN_V  0xFF
+#define GPIO_SD2_IN_S  0
+
+#define GPIO_SIGMADELTA3_REG          (DR_REG_GPIO_SD_BASE + 0x000c)
+/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD3_PRESCALE  0x000000FF
+#define GPIO_SD3_PRESCALE_M  ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
+#define GPIO_SD3_PRESCALE_V  0xFF
+#define GPIO_SD3_PRESCALE_S  8
+/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD3_IN  0x000000FF
+#define GPIO_SD3_IN_M  ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
+#define GPIO_SD3_IN_V  0xFF
+#define GPIO_SD3_IN_S  0
+
+#define GPIO_SIGMADELTA_CG_REG          (DR_REG_GPIO_SD_BASE + 0x0020)
+/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SD_CLK_EN  (BIT(31))
+#define GPIO_SD_CLK_EN_M  (BIT(31))
+#define GPIO_SD_CLK_EN_V  0x1
+#define GPIO_SD_CLK_EN_S  31
+
+#define GPIO_SIGMADELTA_MISC_REG          (DR_REG_GPIO_SD_BASE + 0x0024)
+/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SPI_SWAP  (BIT(31))
+#define GPIO_SPI_SWAP_M  (BIT(31))
+#define GPIO_SPI_SWAP_V  0x1
+#define GPIO_SPI_SWAP_S  31
+/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: */
+#define GPIO_FUNCTION_CLK_EN  (BIT(30))
+#define GPIO_FUNCTION_CLK_EN_M  (BIT(30))
+#define GPIO_FUNCTION_CLK_EN_V  0x1
+#define GPIO_FUNCTION_CLK_EN_S  30
+
+#define GPIO_SIGMADELTA_VERSION_REG          (DR_REG_GPIO_SD_BASE + 0x0028)
+/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006230 ; */
+/*description: */
+#define GPIO_SD_DATE  0x0FFFFFFF
+#define GPIO_SD_DATE_M  ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
+#define GPIO_SD_DATE_V  0xFFFFFFF
+#define GPIO_SD_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/gpio_sd_struct.h b/components/soc/esp32c3/register/soc/gpio_sd_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/gpio_sd_struct.h
rename to components/soc/esp32c3/register/soc/gpio_sd_struct.h
diff --git a/components/soc/esp32c3/register/soc/gpio_struct.h b/components/soc/esp32c3/register/soc/gpio_struct.h
new file mode 100644
index 00000000000..1fbb0779b47
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/gpio_struct.h
@@ -0,0 +1,429 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_GPIO_STRUCT_H_
+#define _SOC_GPIO_STRUCT_H_
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct gpio_dev_s {
+    uint32_t bt_select;                               /**/
+    union {
+        struct {
+            uint32_t data:         26;
+            uint32_t reserved26:    6;
+        };
+        uint32_t val;
+    } out;
+    union {
+        struct {
+            uint32_t out_w1ts:  26;
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } out_w1ts;
+    union {
+        struct {
+            uint32_t out_w1tc:  26;
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } out_w1tc;
+    uint32_t reserved_10;
+    uint32_t reserved_14;
+    uint32_t reserved_18;
+    union {
+        struct {
+            uint32_t sel:        8;
+            uint32_t reserved8: 24;
+        };
+        uint32_t val;
+    } sdio_select;
+    union {
+        struct {
+            uint32_t data:       26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } enable;
+    union {
+        struct {
+            uint32_t enable_w1ts:26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } enable_w1ts;
+    union {
+        struct {
+            uint32_t enable_w1tc:26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } enable_w1tc;
+    uint32_t reserved_2c;
+    uint32_t reserved_30;
+    uint32_t reserved_34;
+    union {
+        struct {
+            uint32_t strapping: 16;
+            uint32_t reserved16:16;
+        };
+        uint32_t val;
+    } strap;
+    union {
+        struct {
+            uint32_t data:        26;
+            uint32_t reserved26:   6;
+        };
+        uint32_t val;
+    } in;
+    uint32_t reserved_40;
+    union {
+        struct {
+            uint32_t intr_st:         26;
+            uint32_t reserved26:       6;
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t status_w1ts:26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } status_w1ts;
+    union {
+        struct {
+            uint32_t status_w1tc:26;
+            uint32_t reserved26:  6;
+        };
+        uint32_t val;
+    } status_w1tc;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    union {
+        struct {
+            uint32_t intr:      26;
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } pcpu_int;
+    union {
+        struct {
+            uint32_t intr:          26;
+            uint32_t reserved26:     6;
+        };
+        uint32_t val;
+    } pcpu_nmi_int;
+    union {
+        struct {
+            uint32_t intr:      26;
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } cpusdio_int;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    union {
+        struct {
+            uint32_t sync2_bypass:       2;
+            uint32_t pad_driver:         1;
+            uint32_t sync1_bypass:       2;
+            uint32_t reserved5:          2;
+            uint32_t int_type:           3;
+            uint32_t wakeup_enable:      1;
+            uint32_t config:             2;
+            uint32_t int_ena:            5;
+            uint32_t reserved18:        14;
+        };
+        uint32_t val;
+    } pin[26];
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    union {
+        struct {
+            uint32_t intr_st_next:         26;
+            uint32_t reserved26:            6;
+        };
+        uint32_t val;
+    } status_next;
+    uint32_t reserved_150;
+    union {
+        struct {
+            uint32_t func_sel:         5;
+            uint32_t sig_in_inv:       1;
+            uint32_t sig_in_sel:       1;
+            uint32_t reserved7:       25;
+        };
+        uint32_t val;
+    } func_in_sel_cfg[128];
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    union {
+        struct {
+            uint32_t func_sel:          8;
+            uint32_t inv_sel:           1;
+            uint32_t oen_sel:           1;
+            uint32_t oen_inv_sel:       1;
+            uint32_t reserved11:       21;
+        };
+        uint32_t val;
+    } func_out_sel_cfg[26];
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    union {
+        struct {
+            uint32_t clk_en:     1;
+            uint32_t reserved1: 31;
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} gpio_dev_t;
+extern gpio_dev_t GPIO;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_GPIO_STRUCT_H_ */
diff --git a/components/soc/esp32c3/register/soc/i2c_reg.h b/components/soc/esp32c3/register/soc/i2c_reg.h
new file mode 100644
index 00000000000..03ec35dad0f
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/i2c_reg.h
@@ -0,0 +1,1054 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_I2C_REG_H_
+#define _SOC_I2C_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+#define I2C_SCL_LOW_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0)
+/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: .*/
+#define I2C_SCL_LOW_PERIOD    0x000001FF
+#define I2C_SCL_LOW_PERIOD_M  ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
+#define I2C_SCL_LOW_PERIOD_V  0x1FF
+#define I2C_SCL_LOW_PERIOD_S  0
+
+#define I2C_CTR_REG(i)          (REG_I2C_BASE(i) + 0x4)
+/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_M  (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_V  0x1
+#define I2C_ADDR_BROADCASTING_EN_S  14
+/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x1
+#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
+/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_M  (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_V  0x1
+#define I2C_SLV_TX_AUTO_START_EN_S  12
+/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (BIT(11))
+#define I2C_CONF_UPGATE_V  0x1
+#define I2C_CONF_UPGATE_S  11
+/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (BIT(10))
+#define I2C_FSM_RST_V  0x1
+#define I2C_FSM_RST_S  10
+/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (BIT(9))
+#define I2C_ARBITRATION_EN_V  0x1
+#define I2C_ARBITRATION_EN_S  9
+/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (BIT(8))
+#define I2C_CLK_EN_V  0x1
+#define I2C_CLK_EN_S  8
+/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (BIT(7))
+#define I2C_RX_LSB_FIRST_V  0x1
+#define I2C_RX_LSB_FIRST_S  7
+/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (BIT(6))
+#define I2C_TX_LSB_FIRST_V  0x1
+#define I2C_TX_LSB_FIRST_S  6
+/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (BIT(5))
+#define I2C_TRANS_START_V  0x1
+#define I2C_TRANS_START_S  5
+/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MS_MODE    (BIT(4))
+#define I2C_MS_MODE_M  (BIT(4))
+#define I2C_MS_MODE_V  0x1
+#define I2C_MS_MODE_S  4
+/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_V  0x1
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_V  0x1
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SCL_FORCE_OUT    (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (BIT(1))
+#define I2C_SCL_FORCE_OUT_V  0x1
+#define I2C_SCL_FORCE_OUT_S  1
+/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SDA_FORCE_OUT    (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (BIT(0))
+#define I2C_SDA_FORCE_OUT_V  0x1
+#define I2C_SDA_FORCE_OUT_S  0
+
+#define I2C_SR_REG(i)          (REG_I2C_BASE(i) + 0x8)
+/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: .*/
+#define I2C_SCL_STATE_LAST    0x00000007
+#define I2C_SCL_STATE_LAST_M  ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
+#define I2C_SCL_STATE_LAST_V  0x7
+#define I2C_SCL_STATE_LAST_S  28
+/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007
+#define I2C_SCL_MAIN_STATE_LAST_M  ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
+#define I2C_SCL_MAIN_STATE_LAST_V  0x7
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_CNT    0x0000003F
+#define I2C_TXFIFO_CNT_M  ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
+#define I2C_TXFIFO_CNT_V  0x3F
+#define I2C_TXFIFO_CNT_S  18
+/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */
+/*description: .*/
+#define I2C_STRETCH_CAUSE    0x00000003
+#define I2C_STRETCH_CAUSE_M  ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S))
+#define I2C_STRETCH_CAUSE_V  0x3
+#define I2C_STRETCH_CAUSE_S  14
+/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_CNT    0x0000003F
+#define I2C_RXFIFO_CNT_M  ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
+#define I2C_RXFIFO_CNT_V  0x3F
+#define I2C_RXFIFO_CNT_S  8
+/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_ADDRESSED    (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (BIT(5))
+#define I2C_SLAVE_ADDRESSED_V  0x1
+#define I2C_SLAVE_ADDRESSED_S  5
+/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (BIT(4))
+#define I2C_BUS_BUSY_V  0x1
+#define I2C_BUS_BUSY_S  4
+/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (BIT(3))
+#define I2C_ARB_LOST_V  0x1
+#define I2C_ARB_LOST_S  3
+/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_RW    (BIT(1))
+#define I2C_SLAVE_RW_M  (BIT(1))
+#define I2C_SLAVE_RW_V  0x1
+#define I2C_SLAVE_RW_S  1
+/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (BIT(0))
+#define I2C_RESP_REC_V  0x1
+#define I2C_RESP_REC_S  0
+
+#define I2C_TO_REG(i)          (REG_I2C_BASE(i) + 0xC)
+/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (BIT(5))
+#define I2C_TIME_OUT_EN_V  0x1
+#define I2C_TIME_OUT_EN_S  5
+/* I2C_TIME_OUT_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+/*description: .*/
+#define I2C_TIME_OUT_REG    0x0000001F
+#define I2C_TIME_OUT_REG_M  ((I2C_TIME_OUT_VALUE_V)<<(I2C_TIME_OUT_VALUE_S))
+#define I2C_TIME_OUT_REG_V  0x1F
+#define I2C_TIME_OUT_REG_S  0
+
+#define I2C_SLAVE_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x10)
+/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ADDR_10BIT_EN    (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (BIT(31))
+#define I2C_ADDR_10BIT_EN_V  0x1
+#define I2C_ADDR_10BIT_EN_S  31
+/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_ADDR    0x00007FFF
+#define I2C_SLAVE_ADDR_M  ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
+#define I2C_SLAVE_ADDR_V  0x7FFF
+#define I2C_SLAVE_ADDR_S  0
+
+#define I2C_FIFO_ST_REG(i)          (REG_I2C_BASE(i) + 0x14)
+/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_RW_POINT    0x000000FF
+#define I2C_SLAVE_RW_POINT_M  ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S))
+#define I2C_SLAVE_RW_POINT_V  0xFF
+#define I2C_SLAVE_RW_POINT_S  22
+/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_WADDR    0x0000001F
+#define I2C_TXFIFO_WADDR_M  ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S))
+#define I2C_TXFIFO_WADDR_V  0x1F
+#define I2C_TXFIFO_WADDR_S  15
+/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_RADDR    0x0000001F
+#define I2C_TXFIFO_RADDR_M  ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S))
+#define I2C_TXFIFO_RADDR_V  0x1F
+#define I2C_TXFIFO_RADDR_S  10
+/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WADDR    0x0000001F
+#define I2C_RXFIFO_WADDR_M  ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S))
+#define I2C_RXFIFO_WADDR_V  0x1F
+#define I2C_RXFIFO_WADDR_S  5
+/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_RADDR    0x0000001F
+#define I2C_RXFIFO_RADDR_M  ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S))
+#define I2C_RXFIFO_RADDR_V  0x1F
+#define I2C_RXFIFO_RADDR_S  0
+
+#define I2C_FIFO_CONF_REG(i)          (REG_I2C_BASE(i) + 0x18)
+/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (BIT(14))
+#define I2C_FIFO_PRT_EN_V  0x1
+#define I2C_FIFO_PRT_EN_S  14
+/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (BIT(13))
+#define I2C_TX_FIFO_RST_V  0x1
+#define I2C_TX_FIFO_RST_S  13
+/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (BIT(12))
+#define I2C_RX_FIFO_RST_V  0x1
+#define I2C_RX_FIFO_RST_S  12
+/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_V  0x1
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (BIT(10))
+#define I2C_NONFIFO_EN_V  0x1
+#define I2C_NONFIFO_EN_S  10
+/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_THRHD    0x0000001F
+#define I2C_TXFIFO_WM_THRHD_M  ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S))
+#define I2C_TXFIFO_WM_THRHD_V  0x1F
+#define I2C_TXFIFO_WM_THRHD_S  5
+/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_THRHD    0x0000001F
+#define I2C_RXFIFO_WM_THRHD_M  ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S))
+#define I2C_RXFIFO_WM_THRHD_V  0x1F
+#define I2C_RXFIFO_WM_THRHD_S  0
+
+#define I2C_DATA_REG(i)          (REG_I2C_BASE(i) + 0x1C)
+/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: .*/
+#define I2C_FIFO_RDATA    0x000000FF
+#define I2C_FIFO_RDATA_M  ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
+#define I2C_FIFO_RDATA_V  0xFF
+#define I2C_FIFO_RDATA_S  0
+
+#define I2C_INT_RAW_REG(i)          (REG_I2C_BASE(i) + 0x20)
+/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_M  (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_V  0x1
+#define I2C_GENERAL_CALL_INT_RAW_S  17
+/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_V  0x1
+#define I2C_SLAVE_STRETCH_INT_RAW_S  16
+/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (BIT(15))
+#define I2C_DET_START_INT_RAW_V  0x1
+#define I2C_DET_START_INT_RAW_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_V  0x1
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x1
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x1
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (BIT(10))
+#define I2C_NACK_INT_RAW_V  0x1
+#define I2C_NACK_INT_RAW_S  10
+/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (BIT(9))
+#define I2C_TRANS_START_INT_RAW_V  0x1
+#define I2C_TRANS_START_INT_RAW_S  9
+/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_V  0x1
+#define I2C_TIME_OUT_INT_RAW_S  8
+/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x1
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x1
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (BIT(3))
+#define I2C_END_DETECT_INT_RAW_V  0x1
+#define I2C_END_DETECT_INT_RAW_S  3
+/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x1
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_V  0x1
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_V  0x1
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+
+#define I2C_INT_CLR_REG(i)          (REG_I2C_BASE(i) + 0x24)
+/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_M  (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_V  0x1
+#define I2C_GENERAL_CALL_INT_CLR_S  17
+/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_V  0x1
+#define I2C_SLAVE_STRETCH_INT_CLR_S  16
+/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (BIT(15))
+#define I2C_DET_START_INT_CLR_V  0x1
+#define I2C_DET_START_INT_CLR_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_V  0x1
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x1
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x1
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (BIT(10))
+#define I2C_NACK_INT_CLR_V  0x1
+#define I2C_NACK_INT_CLR_S  10
+/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (BIT(9))
+#define I2C_TRANS_START_INT_CLR_V  0x1
+#define I2C_TRANS_START_INT_CLR_S  9
+/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_V  0x1
+#define I2C_TIME_OUT_INT_CLR_S  8
+/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x1
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x1
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (BIT(3))
+#define I2C_END_DETECT_INT_CLR_V  0x1
+#define I2C_END_DETECT_INT_CLR_S  3
+/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x1
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_V  0x1
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_V  0x1
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+
+#define I2C_INT_ENA_REG(i)          (REG_I2C_BASE(i) + 0x28)
+/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_M  (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_V  0x1
+#define I2C_GENERAL_CALL_INT_ENA_S  17
+/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_V  0x1
+#define I2C_SLAVE_STRETCH_INT_ENA_S  16
+/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (BIT(15))
+#define I2C_DET_START_INT_ENA_V  0x1
+#define I2C_DET_START_INT_ENA_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_V  0x1
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x1
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x1
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (BIT(10))
+#define I2C_NACK_INT_ENA_V  0x1
+#define I2C_NACK_INT_ENA_S  10
+/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (BIT(9))
+#define I2C_TRANS_START_INT_ENA_V  0x1
+#define I2C_TRANS_START_INT_ENA_S  9
+/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_V  0x1
+#define I2C_TIME_OUT_INT_ENA_S  8
+/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x1
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x1
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (BIT(3))
+#define I2C_END_DETECT_INT_ENA_V  0x1
+#define I2C_END_DETECT_INT_ENA_S  3
+/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x1
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_V  0x1
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_V  0x1
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+
+#define I2C_INT_STATUS_REG(i)          (REG_I2C_BASE(i) + 0x2C)
+/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_M  (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_V  0x1
+#define I2C_GENERAL_CALL_INT_ST_S  17
+/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_M  (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_V  0x1
+#define I2C_SLAVE_STRETCH_INT_ST_S  16
+/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (BIT(15))
+#define I2C_DET_START_INT_ST_V  0x1
+#define I2C_DET_START_INT_ST_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_V  0x1
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_V  0x1
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_V  0x1
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (BIT(10))
+#define I2C_NACK_INT_ST_V  0x1
+#define I2C_NACK_INT_ST_S  10
+/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (BIT(9))
+#define I2C_TRANS_START_INT_ST_V  0x1
+#define I2C_TRANS_START_INT_ST_S  9
+/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (BIT(8))
+#define I2C_TIME_OUT_INT_ST_V  0x1
+#define I2C_TIME_OUT_INT_ST_S  8
+/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x1
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x1
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x1
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x1
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (BIT(3))
+#define I2C_END_DETECT_INT_ST_V  0x1
+#define I2C_END_DETECT_INT_ST_S  3
+/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_V  0x1
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_V  0x1
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_V  0x1
+#define I2C_RXFIFO_WM_INT_ST_S  0
+
+#define I2C_SDA_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x30)
+/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: .*/
+#define I2C_SDA_HOLD_TIME    0x000001FF
+#define I2C_SDA_HOLD_TIME_M  ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
+#define I2C_SDA_HOLD_TIME_V  0x1FF
+#define I2C_SDA_HOLD_TIME_S  0
+
+#define I2C_SDA_SAMPLE_REG(i)          (REG_I2C_BASE(i) + 0x34)
+/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: .*/
+#define I2C_SDA_SAMPLE_TIME    0x000001FF
+#define I2C_SDA_SAMPLE_TIME_M  ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
+#define I2C_SDA_SAMPLE_TIME_V  0x1FF
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+#define I2C_SCL_HIGH_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x38)
+/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */
+/*description: .*/
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007F
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S))
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x7F
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */
+/*description: .*/
+#define I2C_SCL_HIGH_PERIOD    0x000001FF
+#define I2C_SCL_HIGH_PERIOD_M  ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
+#define I2C_SCL_HIGH_PERIOD_V  0x1FF
+#define I2C_SCL_HIGH_PERIOD_S  0
+
+#define I2C_SCL_START_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x40)
+/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+/*description: .*/
+#define I2C_SCL_START_HOLD_TIME    0x000001FF
+#define I2C_SCL_START_HOLD_TIME_M  ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
+#define I2C_SCL_START_HOLD_TIME_V  0x1FF
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+#define I2C_SCL_RSTART_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x44)
+/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+/*description: .*/
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FF
+#define I2C_SCL_RSTART_SETUP_TIME_M  ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x1FF
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+#define I2C_SCL_STOP_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x48)
+/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+/*description: .*/
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FF
+#define I2C_SCL_STOP_HOLD_TIME_M  ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
+#define I2C_SCL_STOP_HOLD_TIME_V  0x1FF
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+#define I2C_SCL_STOP_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x4C)
+/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */
+/*description: .*/
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FF
+#define I2C_SCL_STOP_SETUP_TIME_M  ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
+#define I2C_SCL_STOP_SETUP_TIME_V  0x1FF
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+#define I2C_FILTER_CFG_REG(i)          (REG_I2C_BASE(i) + 0x50)
+/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (BIT(9))
+#define I2C_SDA_FILTER_EN_V  0x1
+#define I2C_SDA_FILTER_EN_S  9
+/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (BIT(8))
+#define I2C_SCL_FILTER_EN_V  0x1
+#define I2C_SCL_FILTER_EN_S  8
+/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: .*/
+#define I2C_SDA_FILTER_THRES    0x0000000F
+#define I2C_SDA_FILTER_THRES_M  ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
+#define I2C_SDA_FILTER_THRES_V  0xF
+#define I2C_SDA_FILTER_THRES_S  4
+/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: .*/
+#define I2C_SCL_FILTER_THRES    0x0000000F
+#define I2C_SCL_FILTER_THRES_M  ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
+#define I2C_SCL_FILTER_THRES_V  0xF
+#define I2C_SCL_FILTER_THRES_S  0
+
+#define I2C_CLK_CONF_REG(i)          (REG_I2C_BASE(i) + 0x54)
+/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: .*/
+#define I2C_SCLK_ACTIVE    (BIT(21))
+#define I2C_SCLK_ACTIVE_M  (BIT(21))
+#define I2C_SCLK_ACTIVE_V  0x1
+#define I2C_SCLK_ACTIVE_S  21
+/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCLK_SEL    (BIT(20))
+#define I2C_SCLK_SEL_M  (BIT(20))
+#define I2C_SCLK_SEL_V  0x1
+#define I2C_SCLK_SEL_S  20
+/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */
+/*description: .*/
+#define I2C_SCLK_DIV_B    0x0000003F
+#define I2C_SCLK_DIV_B_M  ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S))
+#define I2C_SCLK_DIV_B_V  0x3F
+#define I2C_SCLK_DIV_B_S  14
+/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */
+/*description: .*/
+#define I2C_SCLK_DIV_A    0x0000003F
+#define I2C_SCLK_DIV_A_M  ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S))
+#define I2C_SCLK_DIV_A_V  0x3F
+#define I2C_SCLK_DIV_A_S  8
+/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: .*/
+#define I2C_SCLK_DIV_NUM    0x000000FF
+#define I2C_SCLK_DIV_NUM_M  ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S))
+#define I2C_SCLK_DIV_NUM_V  0xFF
+#define I2C_SCLK_DIV_NUM_S  0
+
+#define I2C_COMD0_REG(i)          (REG_I2C_BASE(i) + 0x58)
+/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (BIT(31))
+#define I2C_COMMAND0_DONE_V  0x1
+#define I2C_COMMAND0_DONE_S  31
+/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND0    0x00003FFF
+#define I2C_COMMAND0_M  ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
+#define I2C_COMMAND0_V  0x3FFF
+#define I2C_COMMAND0_S  0
+
+#define I2C_COMD1_REG(i)          (REG_I2C_BASE(i) + 0x5C)
+/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (BIT(31))
+#define I2C_COMMAND1_DONE_V  0x1
+#define I2C_COMMAND1_DONE_S  31
+/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND1    0x00003FFF
+#define I2C_COMMAND1_M  ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
+#define I2C_COMMAND1_V  0x3FFF
+#define I2C_COMMAND1_S  0
+
+#define I2C_COMD2_REG(i)          (REG_I2C_BASE(i) + 0x60)
+/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (BIT(31))
+#define I2C_COMMAND2_DONE_V  0x1
+#define I2C_COMMAND2_DONE_S  31
+/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND2    0x00003FFF
+#define I2C_COMMAND2_M  ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
+#define I2C_COMMAND2_V  0x3FFF
+#define I2C_COMMAND2_S  0
+
+#define I2C_COMD3_REG(i)          (REG_I2C_BASE(i) + 0x64)
+/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (BIT(31))
+#define I2C_COMMAND3_DONE_V  0x1
+#define I2C_COMMAND3_DONE_S  31
+/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND3    0x00003FFF
+#define I2C_COMMAND3_M  ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
+#define I2C_COMMAND3_V  0x3FFF
+#define I2C_COMMAND3_S  0
+
+#define I2C_COMD4_REG(i)          (REG_I2C_BASE(i) + 0x68)
+/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (BIT(31))
+#define I2C_COMMAND4_DONE_V  0x1
+#define I2C_COMMAND4_DONE_S  31
+/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND4    0x00003FFF
+#define I2C_COMMAND4_M  ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
+#define I2C_COMMAND4_V  0x3FFF
+#define I2C_COMMAND4_S  0
+
+#define I2C_COMD5_REG(i)          (REG_I2C_BASE(i) + 0x6C)
+/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (BIT(31))
+#define I2C_COMMAND5_DONE_V  0x1
+#define I2C_COMMAND5_DONE_S  31
+/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND5    0x00003FFF
+#define I2C_COMMAND5_M  ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
+#define I2C_COMMAND5_V  0x3FFF
+#define I2C_COMMAND5_S  0
+
+#define I2C_COMD6_REG(i)          (REG_I2C_BASE(i) + 0x70)
+/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (BIT(31))
+#define I2C_COMMAND6_DONE_V  0x1
+#define I2C_COMMAND6_DONE_S  31
+/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND6    0x00003FFF
+#define I2C_COMMAND6_M  ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
+#define I2C_COMMAND6_V  0x3FFF
+#define I2C_COMMAND6_S  0
+
+#define I2C_COMD7_REG(i)          (REG_I2C_BASE(i) + 0x74)
+/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (BIT(31))
+#define I2C_COMMAND7_DONE_V  0x1
+#define I2C_COMMAND7_DONE_S  31
+/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define I2C_COMMAND7    0x00003FFF
+#define I2C_COMMAND7_M  ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
+#define I2C_COMMAND7_V  0x3FFF
+#define I2C_COMMAND7_S  0
+
+#define I2C_SCL_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x78)
+/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+/*description: no more than 23.*/
+#define I2C_SCL_ST_TO_REG    0x0000001F
+#define I2C_SCL_ST_TO_REG_M  ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S))
+#define I2C_SCL_ST_TO_REG_V  0x1F
+#define I2C_SCL_ST_TO_REG_S  0
+
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x7C)
+/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */
+/*description: no more than 23.*/
+#define I2C_SCL_MAIN_ST_TO_REG    0x0000001F
+#define I2C_SCL_MAIN_ST_TO_REG_M  ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S))
+#define I2C_SCL_MAIN_ST_TO_REG_V  0x1F
+#define I2C_SCL_MAIN_ST_TO_REG_S  0
+
+#define I2C_SCL_SP_CONF_REG(i)          (REG_I2C_BASE(i) + 0x80)
+/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (BIT(7))
+#define I2C_SDA_PD_EN_V  0x1
+#define I2C_SDA_PD_EN_S  7
+/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (BIT(6))
+#define I2C_SCL_PD_EN_V  0x1
+#define I2C_SCL_PD_EN_S  6
+/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */
+/*description: .*/
+#define I2C_SCL_RST_SLV_NUM    0x0000001F
+#define I2C_SCL_RST_SLV_NUM_M  ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S))
+#define I2C_SCL_RST_SLV_NUM_V  0x1F
+#define I2C_SCL_RST_SLV_NUM_S  1
+/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (BIT(0))
+#define I2C_SCL_RST_SLV_EN_V  0x1
+#define I2C_SCL_RST_SLV_EN_S  0
+
+#define I2C_SCL_STRETCH_CONF_REG(i)          (REG_I2C_BASE(i) + 0x84)
+/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_M  (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_V  0x1
+#define I2C_SLAVE_BYTE_ACK_LVL_S  13
+/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x1
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
+/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_M  (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x1
+#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
+/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_M  (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_V  0x1
+#define I2C_SLAVE_SCL_STRETCH_EN_S  10
+/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: .*/
+#define I2C_STRETCH_PROTECT_NUM    0x000003FF
+#define I2C_STRETCH_PROTECT_NUM_M  ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S))
+#define I2C_STRETCH_PROTECT_NUM_V  0x3FF
+#define I2C_STRETCH_PROTECT_NUM_S  0
+
+#define I2C_DATE_REG(i)          (REG_I2C_BASE(i) + 0xF8)
+/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */
+/*description: .*/
+#define I2C_DATE    0xFFFFFFFF
+#define I2C_DATE_M  ((I2C_DATE_V)<<(I2C_DATE_S))
+#define I2C_DATE_V  0xFFFFFFFF
+#define I2C_DATE_S  0
+
+#define I2C_TXFIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x100)
+
+#define I2C_RXFIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x180)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2C_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/i2c_struct.h b/components/soc/esp32c3/register/soc/i2c_struct.h
new file mode 100644
index 00000000000..eb32d5a9cf9
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/i2c_struct.h
@@ -0,0 +1,368 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_I2C_STRUCT_H_
+#define _SOC_I2C_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+typedef volatile struct i2c_dev_s {
+    union {
+        struct {
+            uint32_t period                        :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_low_period;
+    union {
+        struct {
+            uint32_t sda_force_out                 :    1;
+            uint32_t scl_force_out                 :    1;
+            uint32_t sample_scl_level              :    1;
+            uint32_t rx_full_ack_level             :    1;
+            uint32_t ms_mode                       :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t tx_lsb_first                  :    1;
+            uint32_t rx_lsb_first                  :    1;
+            uint32_t clk_en                        :    1;
+            uint32_t arbitration_en                :    1;
+            uint32_t fsm_rst                       :    1;
+            uint32_t conf_upgate                   :    1;
+            uint32_t slv_tx_auto_start_en          :    1;
+            uint32_t addr_10bit_rw_check_en        :    1;
+            uint32_t addr_broadcasting_en          :    1;
+            uint32_t reserved15                    :    17;
+        };
+        uint32_t val;
+    } ctr;
+    union {
+        struct {
+            uint32_t resp_rec                      :    1;
+            uint32_t slave_rw                      :    1;
+            uint32_t reserved2                     :    1;
+            uint32_t arb_lost                      :    1;
+            uint32_t bus_busy                      :    1;
+            uint32_t slave_addressed               :    1;
+            uint32_t reserved6                     :    1;
+            uint32_t reserved7                     :    1;
+            uint32_t rx_fifo_cnt                   :    6;
+            uint32_t stretch_cause                 :    2;
+            uint32_t reserved16                    :    2;
+            uint32_t tx_fifo_cnt                   :    6;
+            uint32_t scl_main_state_last           :    3;
+            uint32_t reserved27                    :    1;
+            uint32_t scl_state_last                :    3;
+            uint32_t reserved31                    :    1;
+        };
+        uint32_t val;
+    } sr;
+    union {
+        struct {
+            uint32_t time_out_value                :    5;
+            uint32_t time_out_en                   :    1;
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } timeout;
+    union {
+        struct {
+            uint32_t addr                          :    15;
+            uint32_t reserved15                    :    16;
+            uint32_t en_10bit                      :    1;
+        };
+        uint32_t val;
+    } slave_addr;
+    union {
+        struct {
+            uint32_t rx_fifo_raddr                 :    5;
+            uint32_t rx_fifo_waddr                 :    5;
+            uint32_t tx_fifo_raddr                 :    5;
+            uint32_t tx_fifo_waddr                 :    5;
+            uint32_t reserved20                    :    1;
+            uint32_t reserved21                    :    1;
+            uint32_t slave_rw_point                :    8;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } fifo_st;
+    union {
+        struct {
+            uint32_t rx_fifo_wm_thrhd              :    5;
+            uint32_t tx_fifo_wm_thrhd              :    5;
+            uint32_t nonfifo_en                    :    1;
+            uint32_t fifo_addr_cfg_en              :    1;
+            uint32_t rx_fifo_rst                   :    1;
+            uint32_t tx_fifo_rst                   :    1;
+            uint32_t fifo_prt_en                   :    1;
+            uint32_t reserved15                    :    5;
+            uint32_t reserved20                    :    6;
+            uint32_t reserved26                    :    1;
+            uint32_t reserved27                    :    5;
+        };
+        uint32_t val;
+    } fifo_conf;
+    union {
+        struct {
+            uint32_t data                          :    8;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } fifo_data;
+    union {
+        struct {
+            uint32_t rx_fifo_wm                    :    1;
+            uint32_t tx_fifo_wm                    :    1;
+            uint32_t rx_fifo_ovf                   :    1;
+            uint32_t end_detect                    :    1;
+            uint32_t byte_trans_done               :    1;
+            uint32_t arbitration_lost              :    1;
+            uint32_t mst_tx_fifo_udf               :    1;
+            uint32_t trans_complete                :    1;
+            uint32_t time_out                      :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t nack                          :    1;
+            uint32_t tx_fifo_ovf                   :    1;
+            uint32_t rx_fifo_udf                   :    1;
+            uint32_t scl_st_to                     :    1;
+            uint32_t scl_main_st_to                :    1;
+            uint32_t det_start                     :    1;
+            uint32_t slave_stretch                 :    1;
+            uint32_t general_call                  :    1;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_fifo_wm                    :    1;
+            uint32_t tx_fifo_wm                    :    1;
+            uint32_t rx_fifo_ovf                   :    1;
+            uint32_t end_detect                    :    1;
+            uint32_t byte_trans_done               :    1;
+            uint32_t arbitration_lost              :    1;
+            uint32_t mst_tx_fifo_udf               :    1;
+            uint32_t trans_complete                :    1;
+            uint32_t time_out                      :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t nack                          :    1;
+            uint32_t tx_fifo_ovf                   :    1;
+            uint32_t rx_fifo_udf                   :    1;
+            uint32_t scl_st_to                     :    1;
+            uint32_t scl_main_st_to                :    1;
+            uint32_t det_start                     :    1;
+            uint32_t slave_stretch                 :    1;
+            uint32_t general_call                  :    1;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t rx_fifo_wm                    :    1;
+            uint32_t tx_fifo_wm                    :    1;
+            uint32_t rx_fifo_ovf                   :    1;
+            uint32_t end_detect                    :    1;
+            uint32_t byte_trans_done               :    1;
+            uint32_t arbitration_lost              :    1;
+            uint32_t mst_tx_fifo_udf               :    1;
+            uint32_t trans_complete                :    1;
+            uint32_t time_out                      :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t nack                          :    1;
+            uint32_t tx_fifo_ovf                   :    1;
+            uint32_t rx_fifo_udf                   :    1;
+            uint32_t scl_st_to                     :    1;
+            uint32_t scl_main_st_to                :    1;
+            uint32_t det_start                     :    1;
+            uint32_t slave_stretch                 :    1;
+            uint32_t general_call                  :    1;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rx_fifo_wm                    :    1;
+            uint32_t tx_fifo_wm                    :    1;
+            uint32_t rx_fifo_ovf                   :    1;
+            uint32_t end_detect                    :    1;
+            uint32_t byte_trans_done               :    1;
+            uint32_t arbitration_lost              :    1;
+            uint32_t mst_tx_fifo_udf               :    1;
+            uint32_t trans_complete                :    1;
+            uint32_t time_out                      :    1;
+            uint32_t trans_start                   :    1;
+            uint32_t nack                          :    1;
+            uint32_t tx_fifo_ovf                   :    1;
+            uint32_t rx_fifo_udf                   :    1;
+            uint32_t scl_st_to                     :    1;
+            uint32_t scl_main_st_to                :    1;
+            uint32_t det_start                     :    1;
+            uint32_t slave_stretch                 :    1;
+            uint32_t general_call                  :    1;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } int_status;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } sda_hold;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } sda_sample;
+    union {
+        struct {
+            uint32_t period                        :    9;
+            uint32_t scl_wait_high_period          :    7;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } scl_high_period;
+    uint32_t reserved_3c;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_start_hold;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_rstart_setup;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_stop_hold;
+    union {
+        struct {
+            uint32_t time                          :    9;
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } scl_stop_setup;
+    union {
+        struct {
+            uint32_t scl_thres                     :    4;
+            uint32_t sda_thres                     :    4;
+            uint32_t scl_en                        :    1;
+            uint32_t sda_en                        :    1;
+            uint32_t reserved10                    :    22;
+        };
+        uint32_t val;
+    } filter_cfg;
+    union {
+        struct {
+            uint32_t sclk_div_num                  :    8;
+            uint32_t sclk_div_a                    :    6;
+            uint32_t sclk_div_b                    :    6;
+            uint32_t sclk_sel                      :    1;
+            uint32_t sclk_active                   :    1;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t command0                      :    14;
+            uint32_t reserved14                    :    17;
+            uint32_t command0_done                 :    1;
+        };
+        uint32_t val;
+    } command[8];
+    union {
+        struct {
+            uint32_t scl_st_to                     :    5;  /*no more than 23*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } scl_st_time_out;
+    union {
+        struct {
+            uint32_t scl_main_st_to                :    5;  /*no more than 23*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } scl_main_st_time_out;
+    union {
+        struct {
+            uint32_t scl_rst_slv_en                :    1;
+            uint32_t scl_rst_slv_num               :    5;
+            uint32_t scl_pd_en                     :    1;
+            uint32_t sda_pd_en                     :    1;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } scl_sp_conf;
+    union {
+        struct {
+            uint32_t stretch_protect_num           :    10;
+            uint32_t slave_scl_stretch_en          :    1;
+            uint32_t slave_scl_stretch_clr         :    1;
+            uint32_t slave_byte_ack_ctl_en         :    1;
+            uint32_t slave_byte_ack_level          :    1;
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } scl_stretch_conf;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t date;
+    uint32_t reserved_fc;
+    uint32_t txfifo_mem[32];
+    uint32_t rxfifo_mem[32];
+} i2c_dev_t;
+extern i2c_dev_t I2C0;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2C_STRUCT_H_ */
diff --git a/components/soc/esp32c3/register/soc/i2s_reg.h b/components/soc/esp32c3/register/soc/i2s_reg.h
new file mode 100644
index 00000000000..7412fe1a13d
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/i2s_reg.h
@@ -0,0 +1,1043 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_I2S_REG_H_
+#define _SOC_I2S_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0x000c)
+/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_RAW  (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_V  0x1
+#define I2S_TX_HUNG_INT_RAW_S  3
+/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_RAW  (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_V  0x1
+#define I2S_RX_HUNG_INT_RAW_S  2
+/* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_done_int interrupt*/
+#define I2S_TX_DONE_INT_RAW  (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (BIT(1))
+#define I2S_TX_DONE_INT_RAW_V  0x1
+#define I2S_TX_DONE_INT_RAW_S  1
+/* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_done_int interrupt*/
+#define I2S_RX_DONE_INT_RAW  (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (BIT(0))
+#define I2S_RX_DONE_INT_RAW_V  0x1
+#define I2S_RX_DONE_INT_RAW_S  0
+
+#define I2S_INT_ST_REG(i)          (REG_I2S_BASE(i) + 0x0010)
+/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_ST  (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (BIT(3))
+#define I2S_TX_HUNG_INT_ST_V  0x1
+#define I2S_TX_HUNG_INT_ST_S  3
+/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_ST  (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (BIT(2))
+#define I2S_RX_HUNG_INT_ST_V  0x1
+#define I2S_RX_HUNG_INT_ST_S  2
+/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_done_int interrupt*/
+#define I2S_TX_DONE_INT_ST  (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (BIT(1))
+#define I2S_TX_DONE_INT_ST_V  0x1
+#define I2S_TX_DONE_INT_ST_S  1
+/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_done_int interrupt*/
+#define I2S_RX_DONE_INT_ST  (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (BIT(0))
+#define I2S_RX_DONE_INT_ST_V  0x1
+#define I2S_RX_DONE_INT_ST_S  0
+
+#define I2S_INT_ENA_REG(i)          (REG_I2S_BASE(i) + 0x0014)
+/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_ENA  (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_V  0x1
+#define I2S_TX_HUNG_INT_ENA_S  3
+/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_ENA  (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_V  0x1
+#define I2S_RX_HUNG_INT_ENA_S  2
+/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_done_int interrupt*/
+#define I2S_TX_DONE_INT_ENA  (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (BIT(1))
+#define I2S_TX_DONE_INT_ENA_V  0x1
+#define I2S_TX_DONE_INT_ENA_S  1
+/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_done_int interrupt*/
+#define I2S_RX_DONE_INT_ENA  (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (BIT(0))
+#define I2S_RX_DONE_INT_ENA_V  0x1
+#define I2S_RX_DONE_INT_ENA_S  0
+
+#define I2S_INT_CLR_REG(i)          (REG_I2S_BASE(i) + 0x0018)
+/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_CLR  (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_V  0x1
+#define I2S_TX_HUNG_INT_CLR_S  3
+/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_CLR  (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_V  0x1
+#define I2S_RX_HUNG_INT_CLR_S  2
+/* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_done_int interrupt*/
+#define I2S_TX_DONE_INT_CLR  (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (BIT(1))
+#define I2S_TX_DONE_INT_CLR_V  0x1
+#define I2S_TX_DONE_INT_CLR_S  1
+/* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_done_int interrupt*/
+#define I2S_RX_DONE_INT_CLR  (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (BIT(0))
+#define I2S_RX_DONE_INT_CLR_V  0x1
+#define I2S_RX_DONE_INT_CLR_S  0
+
+#define I2S_RX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0020)
+/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/
+#define I2S_RX_PDM_EN  (BIT(20))
+#define I2S_RX_PDM_EN_M  (BIT(20))
+#define I2S_RX_PDM_EN_V  0x1
+#define I2S_RX_PDM_EN_S  20
+/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/
+#define I2S_RX_TDM_EN  (BIT(19))
+#define I2S_RX_TDM_EN_M  (BIT(19))
+#define I2S_RX_TDM_EN_V  0x1
+#define I2S_RX_TDM_EN_S  19
+/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: I2S Rx bit endian. 1:small endian  the LSB is received first.
+ 0:big endian  the MSB is received first.*/
+#define I2S_RX_BIT_ORDER  (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (BIT(18))
+#define I2S_RX_BIT_ORDER_V  0x1
+#define I2S_RX_BIT_ORDER_S  18
+/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: 0: WS should be 0 when receiving left channel data  and WS is
+ 1in right channel.  1: WS should be 1 when receiving left channel data  and WS is 0in right channel.*/
+#define I2S_RX_WS_IDLE_POL  (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (BIT(17))
+#define I2S_RX_WS_IDLE_POL_V  0x1
+#define I2S_RX_WS_IDLE_POL_S  17
+/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
+#define I2S_RX_24_FILL_EN  (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (BIT(16))
+#define I2S_RX_24_FILL_EN_V  0x1
+#define I2S_RX_24_FILL_EN_S  16
+/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
+#define I2S_RX_LEFT_ALIGN  (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (BIT(15))
+#define I2S_RX_LEFT_ALIGN_V  0x1
+#define I2S_RX_LEFT_ALIGN_S  15
+/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */
+/*description: 0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop
+ when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
+#define I2S_RX_STOP_MODE  0x00000003
+#define I2S_RX_STOP_MODE_M  ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S))
+#define I2S_RX_STOP_MODE_V  0x3
+#define I2S_RX_STOP_MODE_S  13
+/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to bypass Compress/Decompress module for received data.*/
+#define I2S_RX_PCM_BYPASS  (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (BIT(12))
+#define I2S_RX_PCM_BYPASS_V  0x1
+#define I2S_RX_PCM_BYPASS_S  12
+/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */
+/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law
+ decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
+#define I2S_RX_PCM_CONF  0x00000003
+#define I2S_RX_PCM_CONF_M  ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
+#define I2S_RX_PCM_CONF_V  0x3
+#define I2S_RX_PCM_CONF_S  10
+/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: 1: The first channel data value is valid in I2S RX mono mode.
+   0: The second channel data value is valid in I2S RX mono mode.*/
+#define I2S_RX_MONO_FST_VLD  (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (BIT(9))
+#define I2S_RX_MONO_FST_VLD_V  0x1
+#define I2S_RX_MONO_FST_VLD_S  9
+/* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set 1 to update I2S RX registers from APB clock domain to I2S
+ RX clock domain. This bit will be cleared by hardware after update register done.*/
+#define I2S_RX_UPDATE  (BIT(8))
+#define I2S_RX_UPDATE_M  (BIT(8))
+#define I2S_RX_UPDATE_V  0x1
+#define I2S_RX_UPDATE_S  8
+/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: I2S Rx byte endian  1: low addr value to high addr. 0: low addr
+ with low addr value.*/
+#define I2S_RX_BIG_ENDIAN  (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (BIT(7))
+#define I2S_RX_BIG_ENDIAN_V  0x1
+#define I2S_RX_BIG_ENDIAN_S  7
+/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver  in mono mode*/
+#define I2S_RX_MONO  (BIT(5))
+#define I2S_RX_MONO_M  (BIT(5))
+#define I2S_RX_MONO_V  0x1
+#define I2S_RX_MONO_S  5
+/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave receiver mode*/
+#define I2S_RX_SLAVE_MOD  (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (BIT(3))
+#define I2S_RX_SLAVE_MOD_V  0x1
+#define I2S_RX_SLAVE_MOD_S  3
+/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to start receiving data*/
+#define I2S_RX_START  (BIT(2))
+#define I2S_RX_START_M  (BIT(2))
+#define I2S_RX_START_V  0x1
+#define I2S_RX_START_S  2
+/* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset Rx AFIFO*/
+#define I2S_RX_FIFO_RESET  (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (BIT(1))
+#define I2S_RX_FIFO_RESET_V  0x1
+#define I2S_RX_FIFO_RESET_S  1
+/* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to reset receiver*/
+#define I2S_RX_RESET  (BIT(0))
+#define I2S_RX_RESET_M  (BIT(0))
+#define I2S_RX_RESET_V  0x1
+#define I2S_RX_RESET_S  0
+
+#define I2S_TX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0024)
+/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable signal loop back mode with transmitter module and receiver
+ module sharing the same WS and BCK signals.*/
+#define I2S_SIG_LOOPBACK  (BIT(27))
+#define I2S_SIG_LOOPBACK_M  (BIT(27))
+#define I2S_SIG_LOOPBACK_V  0x1
+#define I2S_SIG_LOOPBACK_S  27
+/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: I2S transmitter channel mode configuration bits.*/
+#define I2S_TX_CHAN_MOD  0x00000007
+#define I2S_TX_CHAN_MOD_M  ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S))
+#define I2S_TX_CHAN_MOD_V  0x7
+#define I2S_TX_CHAN_MOD_S  24
+/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/
+#define I2S_TX_PDM_EN  (BIT(20))
+#define I2S_TX_PDM_EN_M  (BIT(20))
+#define I2S_TX_PDM_EN_V  0x1
+#define I2S_TX_PDM_EN_S  20
+/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/
+#define I2S_TX_TDM_EN  (BIT(19))
+#define I2S_TX_TDM_EN_M  (BIT(19))
+#define I2S_TX_TDM_EN_V  0x1
+#define I2S_TX_TDM_EN_S  19
+/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: I2S Tx bit endian. 1:small endian  the LSB is sent first. 0:big
+ endian  the MSB is sent first.*/
+#define I2S_TX_BIT_ORDER  (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (BIT(18))
+#define I2S_TX_BIT_ORDER_V  0x1
+#define I2S_TX_BIT_ORDER_S  18
+/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: 0: WS should be 0 when sending left channel data  and WS is 1in
+ right channel.  1: WS should be 1 when sending left channel data  and WS is 0in right channel.*/
+#define I2S_TX_WS_IDLE_POL  (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (BIT(17))
+#define I2S_TX_WS_IDLE_POL_V  0x1
+#define I2S_TX_WS_IDLE_POL_S  17
+/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
+#define I2S_TX_24_FILL_EN  (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (BIT(16))
+#define I2S_TX_24_FILL_EN_V  0x1
+#define I2S_TX_24_FILL_EN_S  16
+/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
+#define I2S_TX_LEFT_ALIGN  (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (BIT(15))
+#define I2S_TX_LEFT_ALIGN_V  0x1
+#define I2S_TX_LEFT_ALIGN_S  15
+/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to stop disable output BCK signal and WS signal
+ when tx FIFO is empty*/
+#define I2S_TX_STOP_EN  (BIT(13))
+#define I2S_TX_STOP_EN_M  (BIT(13))
+#define I2S_TX_STOP_EN_V  0x1
+#define I2S_TX_STOP_EN_S  13
+/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to bypass  Compress/Decompress module for transmitted data.*/
+#define I2S_TX_PCM_BYPASS  (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (BIT(12))
+#define I2S_TX_PCM_BYPASS_V  0x1
+#define I2S_TX_PCM_BYPASS_S  12
+/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law
+ decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
+#define I2S_TX_PCM_CONF  0x00000003
+#define I2S_TX_PCM_CONF_M  ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
+#define I2S_TX_PCM_CONF_V  0x3
+#define I2S_TX_PCM_CONF_S  10
+/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: 1: The first channel data value is valid in I2S TX mono mode.
+   0: The second channel data value is valid in I2S TX mono mode.*/
+#define I2S_TX_MONO_FST_VLD  (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (BIT(9))
+#define I2S_TX_MONO_FST_VLD_V  0x1
+#define I2S_TX_MONO_FST_VLD_S  9
+/* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set 1 to update I2S TX registers from APB clock domain to I2S
+ TX clock domain. This bit will be cleared by hardware after update register done.*/
+#define I2S_TX_UPDATE  (BIT(8))
+#define I2S_TX_UPDATE_M  (BIT(8))
+#define I2S_TX_UPDATE_V  0x1
+#define I2S_TX_UPDATE_S  8
+/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: I2S Tx byte endian  1: low addr value to high addr.  0: low addr
+ with low addr value.*/
+#define I2S_TX_BIG_ENDIAN  (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (BIT(7))
+#define I2S_TX_BIG_ENDIAN_V  0x1
+#define I2S_TX_BIG_ENDIAN_S  7
+/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: The value of Left channel data is equal to the value of right
+ channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
+#define I2S_TX_CHAN_EQUAL  (BIT(6))
+#define I2S_TX_CHAN_EQUAL_M  (BIT(6))
+#define I2S_TX_CHAN_EQUAL_V  0x1
+#define I2S_TX_CHAN_EQUAL_S  6
+/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter in mono mode*/
+#define I2S_TX_MONO  (BIT(5))
+#define I2S_TX_MONO_M  (BIT(5))
+#define I2S_TX_MONO_V  0x1
+#define I2S_TX_MONO_S  5
+/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave transmitter mode*/
+#define I2S_TX_SLAVE_MOD  (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (BIT(3))
+#define I2S_TX_SLAVE_MOD_V  0x1
+#define I2S_TX_SLAVE_MOD_S  3
+/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to start transmitting data*/
+#define I2S_TX_START  (BIT(2))
+#define I2S_TX_START_M  (BIT(2))
+#define I2S_TX_START_V  0x1
+#define I2S_TX_START_S  2
+/* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset Tx AFIFO*/
+#define I2S_TX_FIFO_RESET  (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (BIT(1))
+#define I2S_TX_FIFO_RESET_V  0x1
+#define I2S_TX_FIFO_RESET_S  1
+/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to reset transmitter*/
+#define I2S_TX_RESET  (BIT(0))
+#define I2S_TX_RESET_M  (BIT(0))
+#define I2S_TX_RESET_V  0x1
+#define I2S_TX_RESET_S  0
+
+#define I2S_RX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x0028)
+/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to enable receiver in Phillips standard mode*/
+#define I2S_RX_MSB_SHIFT  (BIT(29))
+#define I2S_RX_MSB_SHIFT_M  (BIT(29))
+#define I2S_RX_MSB_SHIFT_V  0x1
+#define I2S_RX_MSB_SHIFT_S  29
+/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */
+/*description: The Rx bit number for each channel minus 1in TDM mode.*/
+#define I2S_RX_TDM_CHAN_BITS  0x0000001F
+#define I2S_RX_TDM_CHAN_BITS_M  ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S))
+#define I2S_RX_TDM_CHAN_BITS_V  0x1F
+#define I2S_RX_TDM_CHAN_BITS_S  24
+/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */
+/*description: I2S Rx half sample bits -1.*/
+#define I2S_RX_HALF_SAMPLE_BITS  0x0000003F
+#define I2S_RX_HALF_SAMPLE_BITS_M  ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S))
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x3F
+#define I2S_RX_HALF_SAMPLE_BITS_S  18
+/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */
+/*description: Set the bits to configure bit length of I2S receiver channel.*/
+#define I2S_RX_BITS_MOD  0x0000001F
+#define I2S_RX_BITS_MOD_M  ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
+#define I2S_RX_BITS_MOD_V  0x1F
+#define I2S_RX_BITS_MOD_S  13
+/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
+/*description: Bit clock configuration bits in receiver mode.*/
+#define I2S_RX_BCK_DIV_NUM  0x0000003F
+#define I2S_RX_BCK_DIV_NUM_M  ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S))
+#define I2S_RX_BCK_DIV_NUM_V  0x3F
+#define I2S_RX_BCK_DIV_NUM_S  7
+/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
+#define I2S_RX_TDM_WS_WIDTH  0x0000007F
+#define I2S_RX_TDM_WS_WIDTH_M  ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S))
+#define I2S_RX_TDM_WS_WIDTH_V  0x7F
+#define I2S_RX_TDM_WS_WIDTH_S  0
+
+#define I2S_TX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x002C)
+/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to enable transmitter in Phillips standard mode*/
+#define I2S_TX_MSB_SHIFT  (BIT(29))
+#define I2S_TX_MSB_SHIFT_M  (BIT(29))
+#define I2S_TX_MSB_SHIFT_V  0x1
+#define I2S_TX_MSB_SHIFT_S  29
+/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */
+/*description: The Tx bit number for each channel minus 1in TDM mode.*/
+#define I2S_TX_TDM_CHAN_BITS  0x0000001F
+#define I2S_TX_TDM_CHAN_BITS_M  ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S))
+#define I2S_TX_TDM_CHAN_BITS_V  0x1F
+#define I2S_TX_TDM_CHAN_BITS_S  24
+/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */
+/*description: I2S Tx half sample bits -1.*/
+#define I2S_TX_HALF_SAMPLE_BITS  0x0000003F
+#define I2S_TX_HALF_SAMPLE_BITS_M  ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S))
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x3F
+#define I2S_TX_HALF_SAMPLE_BITS_S  18
+/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */
+/*description: Set the bits to configure bit length of I2S transmitter channel.*/
+#define I2S_TX_BITS_MOD  0x0000001F
+#define I2S_TX_BITS_MOD_M  ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S))
+#define I2S_TX_BITS_MOD_V  0x1F
+#define I2S_TX_BITS_MOD_S  13
+/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
+/*description: Bit clock configuration bits in transmitter mode.*/
+#define I2S_TX_BCK_DIV_NUM  0x0000003F
+#define I2S_TX_BCK_DIV_NUM_M  ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S))
+#define I2S_TX_BCK_DIV_NUM_V  0x3F
+#define I2S_TX_BCK_DIV_NUM_S  7
+/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
+#define I2S_TX_TDM_WS_WIDTH  0x0000007F
+#define I2S_TX_TDM_WS_WIDTH_M  ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S))
+#define I2S_TX_TDM_WS_WIDTH_V  0x7F
+#define I2S_TX_TDM_WS_WIDTH_S  0
+
+#define I2S_RX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0030)
+/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module
+ clock as I2S_MCLK_OUT.*/
+#define I2S_MCLK_SEL  (BIT(29))
+#define I2S_MCLK_SEL_M  (BIT(29))
+#define I2S_MCLK_SEL_V  0x1
+#define I2S_MCLK_SEL_S  29
+/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160.
+ 3: I2S_MCLK_in.*/
+#define I2S_RX_CLK_SEL  0x00000003
+#define I2S_RX_CLK_SEL_M  ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S))
+#define I2S_RX_CLK_SEL_V  0x3
+#define I2S_RX_CLK_SEL_S  27
+/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: I2S Rx module clock enable signal.*/
+#define I2S_RX_CLK_ACTIVE  (BIT(26))
+#define I2S_RX_CLK_ACTIVE_M  (BIT(26))
+#define I2S_RX_CLK_ACTIVE_V  0x1
+#define I2S_RX_CLK_ACTIVE_S  26
+/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: Integral I2S clock divider value*/
+#define I2S_RX_CLKM_DIV_NUM  0x000000FF
+#define I2S_RX_CLKM_DIV_NUM_M  ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S))
+#define I2S_RX_CLKM_DIV_NUM_V  0xFF
+#define I2S_RX_CLKM_DIV_NUM_S  0
+
+#define I2S_TX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0034)
+/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate*/
+#define I2S_CLK_EN  (BIT(29))
+#define I2S_CLK_EN_M  (BIT(29))
+#define I2S_CLK_EN_V  0x1
+#define I2S_CLK_EN_S  29
+/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2:
+ CLK160. 3: I2S_MCLK_in.*/
+#define I2S_TX_CLK_SEL  0x00000003
+#define I2S_TX_CLK_SEL_M  ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S))
+#define I2S_TX_CLK_SEL_V  0x3
+#define I2S_TX_CLK_SEL_S  27
+/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: I2S Tx module clock enable signal.*/
+#define I2S_TX_CLK_ACTIVE  (BIT(26))
+#define I2S_TX_CLK_ACTIVE_M  (BIT(26))
+#define I2S_TX_CLK_ACTIVE_V  0x1
+#define I2S_TX_CLK_ACTIVE_S  26
+/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a).
+ There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
+#define I2S_TX_CLKM_DIV_NUM  0x000000FF
+#define I2S_TX_CLKM_DIV_NUM_M  ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S))
+#define I2S_TX_CLKM_DIV_NUM_V  0xFF
+#define I2S_TX_CLKM_DIV_NUM_S  0
+
+#define I2S_RX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0038)
+/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b >
+ a/2  the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
+#define I2S_RX_CLKM_DIV_YN1  (BIT(27))
+#define I2S_RX_CLKM_DIV_YN1_M  (BIT(27))
+#define I2S_RX_CLKM_DIV_YN1_V  0x1
+#define I2S_RX_CLKM_DIV_YN1_S  27
+/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
+/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For
+ b > a/2  the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
+#define I2S_RX_CLKM_DIV_X  0x000001FF
+#define I2S_RX_CLKM_DIV_X_M  ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S))
+#define I2S_RX_CLKM_DIV_X_V  0x1FF
+#define I2S_RX_CLKM_DIV_X_S  18
+/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
+/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b
+ > a/2  the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
+#define I2S_RX_CLKM_DIV_Y  0x000001FF
+#define I2S_RX_CLKM_DIV_Y_M  ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S))
+#define I2S_RX_CLKM_DIV_Y_V  0x1FF
+#define I2S_RX_CLKM_DIV_Y_S  9
+/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: For b <= a/2  the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2
+  the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
+#define I2S_RX_CLKM_DIV_Z  0x000001FF
+#define I2S_RX_CLKM_DIV_Z_M  ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S))
+#define I2S_RX_CLKM_DIV_Z_V  0x1FF
+#define I2S_RX_CLKM_DIV_Z_S  0
+
+#define I2S_TX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x003C)
+/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b >
+ a/2  the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
+#define I2S_TX_CLKM_DIV_YN1  (BIT(27))
+#define I2S_TX_CLKM_DIV_YN1_M  (BIT(27))
+#define I2S_TX_CLKM_DIV_YN1_V  0x1
+#define I2S_TX_CLKM_DIV_YN1_S  27
+/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
+/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For
+ b > a/2  the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
+#define I2S_TX_CLKM_DIV_X  0x000001FF
+#define I2S_TX_CLKM_DIV_X_M  ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S))
+#define I2S_TX_CLKM_DIV_X_V  0x1FF
+#define I2S_TX_CLKM_DIV_X_S  18
+/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
+/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b
+ > a/2  the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
+#define I2S_TX_CLKM_DIV_Y  0x000001FF
+#define I2S_TX_CLKM_DIV_Y_M  ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S))
+#define I2S_TX_CLKM_DIV_Y_V  0x1FF
+#define I2S_TX_CLKM_DIV_Y_S  9
+/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: For b <= a/2  the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2
+  the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
+#define I2S_TX_CLKM_DIV_Z  0x000001FF
+#define I2S_TX_CLKM_DIV_Z_M  ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S))
+#define I2S_TX_CLKM_DIV_Z_V  0x1FF
+#define I2S_TX_CLKM_DIV_Z_S  0
+
+#define I2S_TX_PCM2PDM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x040)
+/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: I2S TX PDM Converter enable.*/
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_V  0x1
+#define I2S_PCM2PDM_CONV_EN_S  25
+/* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: I2S TX PDM dac 2channel enable.*/
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x1
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: I2S TX PDM dac mode enable.*/
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x1
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: I2S TX PDM sigmadelta dither value.*/
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x1
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: I2S TX PDM sigmadelta dither2 value.*/
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x1
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_LP_IN_SHIFT_M  ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_HP_IN_SHIFT_M  ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */
+/*description: I2S TX PDM prescale for sigmadelta.*/
+#define I2S_TX_PDM_PRESCALE    0x000000FF
+#define I2S_TX_PDM_PRESCALE_M  ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
+#define I2S_TX_PDM_PRESCALE_V  0xFF
+#define I2S_TX_PDM_PRESCALE_S  5
+/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */
+/*description: I2S TX PDM OSR2 value.*/
+#define I2S_TX_PDM_SINC_OSR2    0x0000000F
+#define I2S_TX_PDM_SINC_OSR2_M  ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
+#define I2S_TX_PDM_SINC_OSR2_V  0xF
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/
+#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_M  (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_V  0x1
+#define I2S_TX_PDM_HP_BYPASS_S  0
+
+#define I2S_TX_PCM2PDM_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x44)
+/* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */
+/*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL
+T12_0[2:0]).*/
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007
+#define I2S_TX_IIR_HP_MULT12_0_M  ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S))
+#define I2S_TX_IIR_HP_MULT12_0_V  0x7
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+/* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */
+/*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL
+T12_5[2:0]).*/
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007
+#define I2S_TX_IIR_HP_MULT12_5_M  ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S))
+#define I2S_TX_IIR_HP_MULT12_5_V  0x7
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */
+/*description: I2S TX PDM Fs.*/
+#define I2S_TX_PDM_FS    0x000003FF
+#define I2S_TX_PDM_FS_M  ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
+#define I2S_TX_PDM_FS_V  0x3FF
+#define I2S_TX_PDM_FS_S  10
+/* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */
+/*description: I2S TX PDM Fp.*/
+#define I2S_TX_PDM_FP    0x000003FF
+#define I2S_TX_PDM_FP_M  ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
+#define I2S_TX_PDM_FP_V  0x3FF
+#define I2S_TX_PDM_FP_S  0
+
+#define I2S_RX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x050)
+/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: The total channel number of I2S TX TDM mode.*/
+#define I2S_RX_TDM_TOT_CHAN_NUM  0x0000000F
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S))
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0xF
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN15_EN  (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_V  0x1
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN14_EN  (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_V  0x1
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN13_EN  (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_V  0x1
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN12_EN  (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_V  0x1
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN11_EN  (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_V  0x1
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN10_EN  (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_V  0x1
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN9_EN  (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_V  0x1
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
+ Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_CHAN8_EN  (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_V  0x1
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN7_EN  (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN6_EN  (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN5_EN  (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN4_EN  (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN3_EN  (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN2_EN  (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN1_EN  (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
+ 0:  Disable  just input 0 in this channel.*/
+#define I2S_RX_TDM_PDM_CHAN0_EN  (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+
+#define I2S_TX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x0054)
+/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM
+ + 1)  channels  and only the data of the enabled channels is sent  then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
+#define I2S_TX_TDM_SKIP_MSK_EN  (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x1
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: The total channel number minus 1 of I2S TX TDM mode.*/
+#define I2S_TX_TDM_TOT_CHAN_NUM  0x0000000F
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S))
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0xF
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN15_EN  (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_V  0x1
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN14_EN  (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_V  0x1
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN13_EN  (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_V  0x1
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN12_EN  (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_V  0x1
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN11_EN  (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_V  0x1
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN10_EN  (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_V  0x1
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN9_EN  (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_V  0x1
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN8_EN  (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_V  0x1
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN7_EN  (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_V  0x1
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN6_EN  (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_V  0x1
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN5_EN  (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_V  0x1
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN4_EN  (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_V  0x1
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN3_EN  (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_V  0x1
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN2_EN  (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_V  0x1
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN1_EN  (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_V  0x1
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
+  Disable  just output 0 in this channel.*/
+#define I2S_TX_TDM_CHAN0_EN  (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_V  0x1
+#define I2S_TX_TDM_CHAN0_EN_S  0
+
+#define I2S_RX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x0058)
+/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_BCK_IN_DM  0x00000003
+#define I2S_RX_BCK_IN_DM_M  ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S))
+#define I2S_RX_BCK_IN_DM_V  0x3
+#define I2S_RX_BCK_IN_DM_S  28
+/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_WS_IN_DM  0x00000003
+#define I2S_RX_WS_IN_DM_M  ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S))
+#define I2S_RX_WS_IN_DM_V  0x3
+#define I2S_RX_WS_IN_DM_S  24
+/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_BCK_OUT_DM  0x00000003
+#define I2S_RX_BCK_OUT_DM_M  ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S))
+#define I2S_RX_BCK_OUT_DM_V  0x3
+#define I2S_RX_BCK_OUT_DM_S  20
+/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_WS_OUT_DM  0x00000003
+#define I2S_RX_WS_OUT_DM_M  ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S))
+#define I2S_RX_WS_OUT_DM_V  0x3
+#define I2S_RX_WS_OUT_DM_S  16
+/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_RX_SD_IN_DM  0x00000003
+#define I2S_RX_SD_IN_DM_M  ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S))
+#define I2S_RX_SD_IN_DM_V  0x3
+#define I2S_RX_SD_IN_DM_S  0
+
+#define I2S_TX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x005C)
+/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_BCK_IN_DM  0x00000003
+#define I2S_TX_BCK_IN_DM_M  ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S))
+#define I2S_TX_BCK_IN_DM_V  0x3
+#define I2S_TX_BCK_IN_DM_S  28
+/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_WS_IN_DM  0x00000003
+#define I2S_TX_WS_IN_DM_M  ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S))
+#define I2S_TX_WS_IN_DM_V  0x3
+#define I2S_TX_WS_IN_DM_S  24
+/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_BCK_OUT_DM  0x00000003
+#define I2S_TX_BCK_OUT_DM_M  ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S))
+#define I2S_TX_BCK_OUT_DM_V  0x3
+#define I2S_TX_BCK_OUT_DM_S  20
+/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_WS_OUT_DM  0x00000003
+#define I2S_TX_WS_OUT_DM_M  ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S))
+#define I2S_TX_WS_OUT_DM_V  0x3
+#define I2S_TX_WS_OUT_DM_S  16
+/* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ delay by neg edge. 3: not used..*/
+#define I2S_TX_SD1_OUT_DM    0x00000003
+#define I2S_TX_SD1_OUT_DM_M  ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S))
+#define I2S_TX_SD1_OUT_DM_V  0x3
+#define I2S_TX_SD1_OUT_DM_S  4
+/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay
+ by pos edge.  2: delay by neg edge. 3: not used.*/
+#define I2S_TX_SD_OUT_DM  0x00000003
+#define I2S_TX_SD_OUT_DM_M  ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S))
+#define I2S_TX_SD_OUT_DM_V  0x3
+#define I2S_TX_SD_OUT_DM_S  0
+
+#define I2S_LC_HUNG_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0060)
+/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: The enable bit for FIFO timeout*/
+#define I2S_LC_FIFO_TIMEOUT_ENA  (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x1
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: The bits are used to scale tick counter threshold. The tick counter
+ is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
+#define I2S_LC_FIFO_TIMEOUT_SHIFT  0x00000007
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x7
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt
+ will be triggered when fifo hung counter is equal to this value*/
+#define I2S_LC_FIFO_TIMEOUT  0x000000FF
+#define I2S_LC_FIFO_TIMEOUT_M  ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S))
+#define I2S_LC_FIFO_TIMEOUT_V  0xFF
+#define I2S_LC_FIFO_TIMEOUT_S  0
+
+#define I2S_RXEOF_NUM_REG(i)          (REG_I2S_BASE(i) + 0x0064)
+/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */
+/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
+#define I2S_RX_EOF_NUM  0x00000FFF
+#define I2S_RX_EOF_NUM_M  ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
+#define I2S_RX_EOF_NUM_V  0xFFF
+#define I2S_RX_EOF_NUM_S  0
+
+#define I2S_CONF_SIGLE_DATA_REG(i)          (REG_I2S_BASE(i) + 0x0068)
+/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: the right channel or left channel put out constant value stored
+ in this register according to tx_chan_mod and reg_tx_msb_right*/
+#define I2S_SINGLE_DATA  0xFFFFFFFF
+#define I2S_SINGLE_DATA_M  ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S))
+#define I2S_SINGLE_DATA_V  0xFFFFFFFF
+#define I2S_SINGLE_DATA_S  0
+
+#define I2S_STATE_REG(i)          (REG_I2S_BASE(i) + 0x006C)
+/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/
+#define I2S_TX_IDLE  (BIT(0))
+#define I2S_TX_IDLE_M  (BIT(0))
+#define I2S_TX_IDLE_V  0x1
+#define I2S_TX_IDLE_S  0
+
+#define I2S_DATE_REG(i)          (REG_I2S_BASE(i) + 0x0080)
+/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */
+/*description: Version control register*/
+#define I2S_DATE  0x0FFFFFFF
+#define I2S_DATE_M  ((I2S_DATE_V)<<(I2S_DATE_S))
+#define I2S_DATE_V  0xFFFFFFF
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2S_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/i2s_struct.h b/components/soc/esp32c3/register/soc/i2s_struct.h
new file mode 100644
index 00000000000..29093ad2d97
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/i2s_struct.h
@@ -0,0 +1,328 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct i2s_dev_s {
+    uint32_t reserved_0;
+    uint32_t reserved_4;
+    uint32_t reserved_8;
+    union {
+        struct {
+            uint32_t rx_done:         1;             /*The raw interrupt status bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done:         1;             /*The raw interrupt status bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung:         1;             /*The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:         1;             /*The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4:      28;             /*Reserve*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_done:        1;              /*The masked interrupt status bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done:        1;              /*The masked interrupt status bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung:        1;              /*The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:        1;              /*The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4:     28;              /*Reserve*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rx_done:         1;             /*The interrupt enable bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done:         1;             /*The interrupt enable bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung:         1;             /*The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:         1;             /*The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4:      28;             /*Reserve*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rx_done:         1;             /*Set this bit to clear the i2s_rx_done_int interrupt*/
+            uint32_t tx_done:         1;             /*Set this bit to clear the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung:         1;             /*Set this bit to clear the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:         1;             /*Set this bit to clear the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4:      28;             /*Reserve*/
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t reserved_1c;
+    union {
+        struct {
+            uint32_t rx_reset:              1;       /*Set this bit to reset receiver*/
+            uint32_t rx_fifo_reset:         1;       /*Set this bit to reset Rx AFIFO*/
+            uint32_t rx_start:              1;       /*Set this bit to start receiving data*/
+            uint32_t rx_slave_mod:          1;       /*Set this bit to enable slave receiver mode*/
+            uint32_t reserved4:             1;       /*Reserved*/
+            uint32_t rx_mono:               1;       /*Set this bit to enable receiver  in mono mode*/
+            uint32_t reserved6:             1;
+            uint32_t rx_big_endian:         1;       /*I2S Rx byte endian  1: low addr value to high addr. 0: low addr with low addr value.*/
+            uint32_t rx_update:             1;       /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
+            uint32_t rx_mono_fst_vld:       1;       /*1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.*/
+            uint32_t rx_pcm_conf:           2;       /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
+            uint32_t rx_pcm_bypass:         1;       /*Set this bit to bypass Compress/Decompress module for received data.*/
+            uint32_t rx_stop_mode:          2;       /*0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
+            uint32_t rx_left_align:         1;       /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
+            uint32_t rx_24_fill_en:         1;       /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
+            uint32_t rx_ws_idle_pol:        1;       /*0: WS should be 0 when receiving left channel data  and WS is 1in right channel.  1: WS should be 1 when receiving left channel data  and WS is 0in right channel.*/
+            uint32_t rx_bit_order:          1;       /*I2S Rx bit endian. 1:small endian  the LSB is received first. 0:big endian  the MSB is received first.*/
+            uint32_t rx_tdm_en:             1;       /*1: Enable I2S TDM Rx mode . 0: Disable.*/
+            uint32_t rx_pdm_en:             1;       /*1: Enable I2S PDM Rx mode . 0: Disable.*/
+            uint32_t reserved23:            11;       /*Reserve*/
+        };
+        uint32_t val;
+    } rx_conf;
+    union {
+        struct {
+            uint32_t tx_reset:        1;             /*Set this bit to reset transmitter*/
+            uint32_t tx_fifo_reset:   1;             /*Set this bit to reset Tx AFIFO*/
+            uint32_t tx_start:        1;             /*Set this bit to start transmitting data*/
+            uint32_t tx_slave_mod:    1;             /*Set this bit to enable slave transmitter mode*/
+            uint32_t reserved4:       1;             /*Reserved*/
+            uint32_t tx_mono:         1;             /*Set this bit to enable transmitter in mono mode*/
+            uint32_t tx_chan_equal:   1;             /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
+            uint32_t tx_big_endian:   1;             /*I2S Tx byte endian  1: low addr value to high addr.  0: low addr with low addr value.*/
+            uint32_t tx_update:       1;             /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
+            uint32_t tx_mono_fst_vld: 1;             /*1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.*/
+            uint32_t tx_pcm_conf:     2;             /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress  1 (ltoa) : A-Law compress  2 (utol) : u-Law decompress  3 (ltou) : u-Law compress. &*/
+            uint32_t tx_pcm_bypass:   1;             /*Set this bit to bypass  Compress/Decompress module for transmitted data.*/
+            uint32_t tx_stop_en:      1;             /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty*/
+            uint32_t reserved14:      1;
+            uint32_t tx_left_align:   1;             /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
+            uint32_t tx_24_fill_en:   1;             /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
+            uint32_t tx_ws_idle_pol:  1;             /*0: WS should be 0 when sending left channel data  and WS is 1in right channel.  1: WS should be 1 when sending left channel data  and WS is 0in right channel.*/
+            uint32_t tx_bit_order:    1;             /*I2S Tx bit endian. 1:small endian  the LSB is sent first. 0:big endian  the MSB is sent first.*/
+            uint32_t tx_tdm_en:       1;             /*1: Enable I2S TDM Tx mode . 0: Disable.*/
+            uint32_t tx_pdm_en:       1;             /*1: Enable I2S PDM Tx mode . 0: Disable.*/
+            uint32_t reserved21:      3;             /*Reserved*/
+            uint32_t tx_chan_mod:     3;             /*I2S transmitter channel mode configuration bits.*/
+            uint32_t sig_loopback:    1;             /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
+            uint32_t reserved28:      4;             /*Reserved*/
+        };
+        uint32_t val;
+    } tx_conf;
+    union {
+        struct {
+            uint32_t rx_tdm_ws_width:     7;         /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
+            uint32_t rx_bck_div_num:      6;         /*Bit clock configuration bits in receiver mode.*/
+            uint32_t rx_bits_mod:         5;         /*Set the bits to configure bit length of I2S receiver channel.*/
+            uint32_t rx_half_sample_bits: 6;         /*I2S Rx half sample bits -1.*/
+            uint32_t rx_tdm_chan_bits:    5;         /*The Rx bit number for each channel minus 1in TDM mode.*/
+            uint32_t rx_msb_shift:        1;         /*Set this bit to enable receiver in Phillips standard mode*/
+            uint32_t reserved30:          2;         /*Reserved*/
+        };
+        uint32_t val;
+    } rx_conf1;
+    union {
+        struct {
+            uint32_t tx_tdm_ws_width:     7;         /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
+            uint32_t tx_bck_div_num:      6;         /*Bit clock configuration bits in transmitter mode.*/
+            uint32_t tx_bits_mod:         5;         /*Set the bits to configure bit length of I2S transmitter channel.*/
+            uint32_t tx_half_sample_bits: 6;         /*I2S Tx half sample bits -1.*/
+            uint32_t tx_tdm_chan_bits:    5;         /*The Tx bit number for each channel minus 1in TDM mode.*/
+            uint32_t tx_msb_shift:        1;         /*Set this bit to enable transmitter in Phillips standard mode*/
+            uint32_t tx_bck_no_dly:       1;         /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
+            uint32_t reserved31:          1;               /* Reserved*/
+        };
+        uint32_t val;
+    } tx_conf1;
+    union {
+        struct {
+            uint32_t rx_clkm_div_num: 8;             /*Integral I2S clock divider value*/
+            uint32_t reserved8:      18;             /*Reserved*/
+            uint32_t rx_clk_active:   1;             /*I2S Rx module clock enable signal.*/
+            uint32_t rx_clk_sel:      2;             /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
+            uint32_t mclk_sel:        1;             /*0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
+            uint32_t reserved30:      2;             /*Reserved*/
+        };
+        uint32_t val;
+    } rx_clkm_conf;
+    union {
+        struct {
+            uint32_t tx_clkm_div_num: 8;             /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2  z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2  z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
+            uint32_t reserved8:      18;             /*Reserved*/
+            uint32_t tx_clk_active:   1;             /*I2S Tx module clock enable signal.*/
+            uint32_t tx_clk_sel:      2;             /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
+            uint32_t clk_en:          1;             /*Set this bit to enable clk gate*/
+            uint32_t reserved30:      2;             /*Reserved*/
+        };
+        uint32_t val;
+    } tx_clkm_conf;
+    union {
+        struct {
+            uint32_t rx_clkm_div_z:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2  the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
+            uint32_t rx_clkm_div_y:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2  the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
+            uint32_t rx_clkm_div_x:   9;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2  the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
+            uint32_t rx_clkm_div_yn1: 1;             /*For b <= a/2  the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2  the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
+            uint32_t reserved28:      4;             /*Reserved*/
+        };
+        uint32_t val;
+    } rx_clkm_div_conf;
+    union {
+        struct {
+            uint32_t tx_clkm_div_z:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2  the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
+            uint32_t tx_clkm_div_y:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2  the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
+            uint32_t tx_clkm_div_x:   9;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2  the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
+            uint32_t tx_clkm_div_yn1: 1;             /*For b <= a/2  the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2  the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
+            uint32_t reserved28:      4;             /*Reserved*/
+        };
+        uint32_t val;
+    } tx_clkm_div_conf;
+    union {
+        struct {
+            uint32_t tx_pdm_hp_bypass              :    1;  /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
+            uint32_t tx_pdm_sinc_osr2              :    4;  /*I2S TX PDM OSR2 value*/
+            uint32_t tx_pdm_prescale               :    8;  /*I2S TX PDM prescale for sigmadelta*/
+            uint32_t tx_pdm_hp_in_shift            :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_pdm_lp_in_shift            :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_pdm_sinc_in_shift          :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_pdm_sigmadelta_in_shift    :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_pdm_sigmadelta_dither2     :    1;  /*I2S TX PDM sigmadelta dither2 value*/
+            uint32_t tx_pdm_sigmadelta_dither      :    1;  /*I2S TX PDM sigmadelta dither value*/
+            uint32_t tx_pdm_dac_2out_en            :    1;  /*I2S TX PDM dac mode enable*/
+            uint32_t tx_pdm_dac_mode_en            :    1;  /*I2S TX PDM dac 2channel enable*/
+            uint32_t pcm2pdm_conv_en               :    1;  /*I2S TX PDM Converter enable*/
+            uint32_t reserved26                    :    6;  /*Reserved*/
+        };
+        uint32_t val;
+    } tx_pcm2pdm_conf;
+    union {
+        struct {
+            uint32_t tx_pdm_fp                     :    10;  /*I2S TX PDM Fp*/
+            uint32_t tx_pdm_fs                     :    10;  /*I2S TX PDM Fs*/
+            uint32_t tx_iir_hp_mult12_5            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
+            uint32_t tx_iir_hp_mult12_0            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
+            uint32_t reserved26                    :    6;  /*Reserved*/
+        };
+        uint32_t val;
+    } tx_pcm2pdm_conf1;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    union {
+        struct {
+            uint32_t rx_tdm_pdm_chan0_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan1_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan2_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan3_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan4_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan5_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan6_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_pdm_chan7_en           :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan8_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan9_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan10_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan11_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan12_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan13_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan14_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan15_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_tot_chan_num: 4;         /*The total channel number of I2S TX TDM mode.*/
+            uint32_t reserved20:         12;         /*Reserved*/
+        };
+        uint32_t val;
+    } rx_tdm_ctrl;
+    union {
+        struct {
+            uint32_t tx_tdm_chan0_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan1_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan2_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan3_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan4_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan5_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan6_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan7_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan8_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan9_en:     1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan10_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan11_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan12_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan13_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan14_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_chan15_en:    1;         /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable  just output 0 in this channel.*/
+            uint32_t tx_tdm_tot_chan_num: 4;         /*The total channel number minus 1 of I2S TX TDM mode.*/
+            uint32_t tx_tdm_skip_msk_en:  1;         /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels  and only the data of the enabled channels is sent  then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
+            uint32_t reserved21:         11;         /*Reserved*/
+        };
+        uint32_t val;
+    } tx_tdm_ctrl;
+    union {
+        struct {
+            uint32_t rx_sd_in_dm:   2;               /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved2                     :    14;  /* Reserved*/
+            uint32_t rx_ws_out_dm:  2;               /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved18:    2;
+            uint32_t rx_bck_out_dm: 2;               /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved22:    2;
+            uint32_t rx_ws_in_dm:   2;               /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved26:    2;
+            uint32_t rx_bck_in_dm:  2;               /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved30:    2;
+        };
+        uint32_t val;
+    } rx_timing;
+    union {
+        struct {
+            uint32_t tx_sd_out_dm                  :    2;  /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved2                     :    2;  /* Reserved*/
+            uint32_t tx_sd1_out_dm                 :    2;  /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved6                     :    10;  /* Reserved*/
+            uint32_t tx_ws_out_dm                  :    2;  /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved18                    :    2;  /* Reserved*/
+            uint32_t tx_bck_out_dm                 :    2;  /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved22                    :    2;  /* Reserved*/
+            uint32_t tx_ws_in_dm                   :    2;  /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved26                    :    2;  /* Reserved*/
+            uint32_t tx_bck_in_dm                  :    2;  /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
+        };
+        uint32_t val;
+    } tx_timing;
+    union {
+        struct {
+            uint32_t fifo_timeout:          8;       /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
+            uint32_t fifo_timeout_shift:    3;       /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
+            uint32_t fifo_timeout_ena:      1;       /*The enable bit for FIFO timeout*/
+            uint32_t reserved12:           20;       /*Reserved*/
+        };
+        uint32_t val;
+    } lc_hung_conf;
+    union {
+        struct {
+            uint32_t rx_eof_num:12;                  /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
+            uint32_t reserved12:20;                  /*Reserved*/
+        };
+        uint32_t val;
+    } rx_eof_num;
+    uint32_t conf_single_data;                     /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
+    union {
+        struct {
+            uint32_t tx_idle:    1;                  /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
+            uint32_t reserved1: 31;                  /*Reserved*/
+        };
+        uint32_t val;
+    } state;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    union {
+        struct {
+            uint32_t date:      28;                  /*Version control register*/
+            uint32_t reserved28: 4;                  /*Reserved*/
+        };
+        uint32_t val;
+    } date;
+} i2s_dev_t;
+extern i2s_dev_t I2S0;
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/interrupt_core0_reg.h b/components/soc/esp32c3/register/soc/interrupt_core0_reg.h
new file mode 100644
index 00000000000..5f7c63c5201
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/interrupt_core0_reg.h
@@ -0,0 +1,848 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_INTERRUPT_CORE0_REG_H_
+#define _SOC_INTERRUPT_CORE0_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
+
+#define INTERRUPT_CORE0_MAC_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
+/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_MAC_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_MAC_INTR_MAP_M  ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
+#define INTERRUPT_CORE0_MAC_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_MAC_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_MAC_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
+/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_MAC_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_MAC_NMI_MAP_M  ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
+#define INTERRUPT_CORE0_MAC_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_MAC_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_PWR_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
+/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_PWR_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_PWR_INTR_MAP_M  ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
+#define INTERRUPT_CORE0_PWR_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_PWR_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
+/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BB_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BB_INT_MAP_M  ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
+#define INTERRUPT_CORE0_BB_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BB_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
+/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M  ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
+/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_BB_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_M  ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
+/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
+/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
+/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x024)
+/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBT_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_M  ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x028)
+/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M  ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x02C)
+/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x030)
+/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SLC0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_M  ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x034)
+/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SLC1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_M  ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x038)
+/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M  ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S))
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x03C)
+/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x040)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP  0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x044)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x048)
+/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x04C)
+/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S  0
+
+#define INTERRUPT_CORE0_I2S_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
+/* INTERRUPT_CORE0_I2S_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2S_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2S_INT_MAP_M  ((INTERRUPT_CORE0_I2S_INT_MAP_V)<<(INTERRUPT_CORE0_I2S_INT_MAP_S))
+#define INTERRUPT_CORE0_I2S_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2S_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
+/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_UART_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UART_INTR_MAP_M  ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UART1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x058)
+/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_UART1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UART1_INTR_MAP_M  ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x05C)
+/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_LEDC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
+#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x060)
+/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_EFUSE_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CAN_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
+/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CAN_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CAN_INT_MAP_M  ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
+#define INTERRUPT_CORE0_CAN_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CAN_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_USB_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
+/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_USB_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_USB_INTR_MAP_M  ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
+#define INTERRUPT_CORE0_USB_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_USB_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x06C)
+/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M  ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_RMT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x070)
+/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RMT_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_RMT_INTR_MAP_M  ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
+#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x074)
+/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x078)
+/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TIMER_INT1_MAP  0x0000001F
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_M  ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_V  0x1F
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x07C)
+/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TIMER_INT2_MAP  0x0000001F
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_M  ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_V  0x1F
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x080)
+/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG_T0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x084)
+/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x088)
+/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x08C)
+/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x090)
+/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x09C)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0)
+/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M  ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4)
+/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8)
+/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC)
+/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M  ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0)
+/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4)
+/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8)
+/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC)
+/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_RSA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_RSA_INT_MAP_M  ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
+#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_RSA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0)
+/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_AES_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_AES_INT_MAP_M  ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
+#define INTERRUPT_CORE0_AES_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_AES_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4)
+/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_SHA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
+#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SHA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
+
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8)
+/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC)
+/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0)
+/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4)
+/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8)
+/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC)
+/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0)
+/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4)
+/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
+/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTR_STATUS_0  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
+#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
+/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTR_STATUS_1  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
+#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_S  0
+
+#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define INTERRUPT_CORE0_CLK_EN  (BIT(0))
+#define INTERRUPT_CORE0_CLK_EN_M  (BIT(0))
+#define INTERRUPT_CORE0_CLK_EN_V  0x1
+#define INTERRUPT_CORE0_CLK_EN_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_ENABLE  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_M  ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S))
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_TYPE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_TYPE  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_TYPE_M  ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S))
+#define INTERRUPT_CORE0_CPU_INT_TYPE_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_TYPE_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
+/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_CLEAR  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_M  ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S))
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M  ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S))
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
+/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
+/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
+/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
+/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
+/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
+/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
+/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
+/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
+/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
+/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
+/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
+/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
+/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
+/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
+/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
+/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
+/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
+/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
+/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
+/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
+/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP  0x0000000F
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S))
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V  0xF
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S  0
+#define INTC_INT_PRIO_REG(n)                        (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
+
+#define INTERRUPT_CORE0_CPU_INT_THRESH_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
+/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INT_THRESH  0x0000000F
+#define INTERRUPT_CORE0_CPU_INT_THRESH_M  ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S))
+#define INTERRUPT_CORE0_CPU_INT_THRESH_V  0xF
+#define INTERRUPT_CORE0_CPU_INT_THRESH_S  0
+
+#define INTERRUPT_CORE0_INTERRUPT_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
+/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007210 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTERRUPT_DATE  0x0FFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
+#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0xFFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/io_mux_reg.h b/components/soc/esp32c3/register/soc/io_mux_reg.h
new file mode 100644
index 00000000000..a85a3434dd0
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/io_mux_reg.h
@@ -0,0 +1,273 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_IO_MUX_REG_H_
+#define _SOC_IO_MUX_REG_H_
+
+#include "soc/soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+
+#define IO_MUX_GPIO0_REG		PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO1_REG		PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO2_REG		PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG		PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG		PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO5_REG		PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO6_REG		PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO7_REG		PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO8_REG		PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG		PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG	PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG	PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO12_REG	PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO13_REG	PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO14_REG	PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO15_REG	PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO16_REG	PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO17_REG	PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO18_REG	PERIPHS_IO_MUX_GPIO18_U
+#define IO_MUX_GPIO19_REG	PERIPHS_IO_MUX_GPIO19_U
+#define IO_MUX_GPIO20_REG	PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO21_REG	PERIPHS_IO_MUX_U0TXD_U
+
+/* Value to set in IO Mux to use a pin as GPIO. */
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define SPI_HD_GPIO_NUM  12
+#define SPI_WP_GPIO_NUM  13
+#define SPI_CS0_GPIO_NUM 14
+#define SPI_CLK_GPIO_NUM 15
+#define SPI_D_GPIO_NUM   16
+#define SPI_Q_GPIO_NUM   17
+
+#define SD_CLK_GPIO_NUM 12
+#define SD_CMD_GPIO_NUM 11
+#define SD_DATA0_GPIO_NUM 13
+#define SD_DATA1_GPIO_NUM 14
+#define SD_DATA2_GPIO_NUM 9
+#define SD_DATA3_GPIO_NUM 10
+
+#define USB_INT_PHY0_DM_GPIO_NUM   18
+#define USB_INT_PHY0_DP_GPIO_NUM   19
+
+#define MAX_RTC_GPIO_NUM 5
+#define MAX_PAD_GPIO_NUM 21
+#define MAX_GPIO_NUM    25
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
+#define PAD_POWER_SEL                               BIT(15)
+#define PAD_POWER_SEL_V                             0x1
+#define PAD_POWER_SEL_M                             BIT(15)
+#define PAD_POWER_SEL_S                             15
+
+
+#define PAD_POWER_SWITCH_DELAY                      0x7
+#define PAD_POWER_SWITCH_DELAY_V                    0x7
+#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
+#define PAD_POWER_SWITCH_DELAY_S                    12
+
+
+#define CLK_OUT3                                    0xf
+#define CLK_OUT3_V                                  CLK_OUT3
+#define CLK_OUT3_S                                  8
+#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2                                    0xf
+#define CLK_OUT2_V                                  CLK_OUT2
+#define CLK_OUT2_S                                  4
+#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1                                    0xf
+#define CLK_OUT1_V                                  CLK_OUT1
+#define CLK_OUT1_S                                  0
+#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
+
+#define PERIPHS_IO_MUX_XTAL_32K_P_U       (REG_IO_MUX_BASE +0x04)
+#define FUNC_XTAL_32K_P_GPIO0                       1
+#define FUNC_XTAL_32K_P_GPIO0_0                     0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U       (REG_IO_MUX_BASE +0x08)
+#define FUNC_XTAL_32K_N_GPIO1                       1
+#define FUNC_XTAL_32K_N_GPIO1_0                     0
+
+#define PERIPHS_IO_MUX_GPIO2_U            (REG_IO_MUX_BASE +0x0c)
+#define FUNC_GPIO2_FSPIQ                            2
+#define FUNC_GPIO2_GPIO2                            1
+#define FUNC_GPIO2_GPIO2_0                          0
+
+#define PERIPHS_IO_MUX_GPIO3_U            (REG_IO_MUX_BASE +0x10)
+#define FUNC_GPIO3_GPIO3                            1
+#define FUNC_GPIO3_GPIO3_0                          0
+
+#define PERIPHS_IO_MUX_MTMS_U             (REG_IO_MUX_BASE +0x14)
+#define FUNC_MTMS_FSPIHD                            2
+#define FUNC_MTMS_GPIO4                             1
+#define FUNC_MTMS_MTMS                              0
+
+#define PERIPHS_IO_MUX_MTDI_U             (REG_IO_MUX_BASE +0x18)
+#define FUNC_MTDI_FSPIWP                            2
+#define FUNC_MTDI_GPIO5                             1
+#define FUNC_MTDI_MTDI                              0
+
+#define PERIPHS_IO_MUX_MTCK_U             (REG_IO_MUX_BASE +0x1c)
+#define FUNC_MTCK_FSPICLK                           2
+#define FUNC_MTCK_GPIO6                             1
+#define FUNC_MTCK_MTCK                              0
+
+#define PERIPHS_IO_MUX_MTDO_U             (REG_IO_MUX_BASE +0x20)
+#define FUNC_MTDO_FSPID                             2
+#define FUNC_MTDO_GPIO7                             1
+#define FUNC_MTDO_MTDO                              0
+
+#define PERIPHS_IO_MUX_GPIO8_U            (REG_IO_MUX_BASE +0x24)
+#define FUNC_GPIO8_GPIO8                            1
+#define FUNC_GPIO8_GPIO8_0                          0
+
+#define PERIPHS_IO_MUX_GPIO9_U            (REG_IO_MUX_BASE +0x28)
+#define FUNC_GPIO9_GPIO9                            1
+#define FUNC_GPIO9_GPIO9_0                          0
+
+#define PERIPHS_IO_MUX_GPIO10_U           (REG_IO_MUX_BASE +0x2c)
+#define FUNC_GPIO10_FSPICS0                         2
+#define FUNC_GPIO10_GPIO10                          1
+#define FUNC_GPIO10_GPIO10_0                        0
+
+#define PERIPHS_IO_MUX_VDD_SPI_U          (REG_IO_MUX_BASE +0x30)
+#define FUNC_VDD_SPI_GPIO11                         1
+#define FUNC_VDD_SPI_GPIO11_0                       0
+
+#define PERIPHS_IO_MUX_SPIHD_U            (REG_IO_MUX_BASE +0x34)
+#define FUNC_SPIHD_GPIO12                           1
+#define FUNC_SPIHD_SPIHD                            0
+
+#define PERIPHS_IO_MUX_SPIWP_U            (REG_IO_MUX_BASE +0x38)
+#define FUNC_SPIWP_GPIO13                           1
+#define FUNC_SPIWP_SPIWP                            0
+
+#define PERIPHS_IO_MUX_SPICS0_U           (REG_IO_MUX_BASE +0x3c)
+#define FUNC_SPICS0_GPIO14                          1
+#define FUNC_SPICS0_SPICS0                          0
+
+#define PERIPHS_IO_MUX_SPICLK_U           (REG_IO_MUX_BASE +0x40)
+#define FUNC_SPICLK_GPIO15                          1
+#define FUNC_SPICLK_SPICLK                          0
+
+#define PERIPHS_IO_MUX_SPID_U             (REG_IO_MUX_BASE +0x44)
+#define FUNC_SPID_GPIO16                            1
+#define FUNC_SPID_SPID                              0
+
+#define PERIPHS_IO_MUX_SPIQ_U             (REG_IO_MUX_BASE +0x48)
+#define FUNC_SPIQ_GPIO17                            1
+#define FUNC_SPIQ_SPIQ                              0
+
+#define PERIPHS_IO_MUX_GPIO18_U           (REG_IO_MUX_BASE +0x4c)
+#define FUNC_GPIO18_GPIO18                          1
+#define FUNC_GPIO18_GPIO18_0                        0
+
+#define PERIPHS_IO_MUX_GPIO19_U           (REG_IO_MUX_BASE +0x50)
+#define FUNC_GPIO19_GPIO19                          1
+#define FUNC_GPIO19_GPIO19_0                        0
+
+#define PERIPHS_IO_MUX_U0RXD_U            (REG_IO_MUX_BASE +0x54)
+#define FUNC_U0RXD_GPIO20                           1
+#define FUNC_U0RXD_U0RXD                            0
+
+#define PERIPHS_IO_MUX_U0TXD_U            (REG_IO_MUX_BASE +0x58)
+#define FUNC_U0TXD_GPIO21                           1
+#define FUNC_U0TXD_U0TXD                            0
+
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+#define IO_MUX_DATE 0xFFFFFFFF
+#define IO_MUX_DATE_S 0
+#define IO_MUX_DATE_VERSION 0x2006050
+
+#endif
diff --git a/components/soc/esp32c3/register/soc/ledc_reg.h b/components/soc/esp32c3/register/soc/ledc_reg.h
new file mode 100644
index 00000000000..c956e9e7dad
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/ledc_reg.h
@@ -0,0 +1,1218 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_LEDC_REG_H_
+#define _SOC_LEDC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define LEDC_LSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x0000)
+/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH0  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH0_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH0_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH0_S  16
+/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH0  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH0_S  15
+/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH0  0x000003FF
+#define LEDC_OVF_NUM_LSCH0_M  ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S))
+#define LEDC_OVF_NUM_LSCH0_V  0x3FF
+#define LEDC_OVF_NUM_LSCH0_S  5
+/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH0  (BIT(4))
+#define LEDC_PARA_UP_LSCH0_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH0_V  0x1
+#define LEDC_PARA_UP_LSCH0_S  4
+/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH0  (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_V  0x1
+#define LEDC_IDLE_LV_LSCH0_S  3
+/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH0  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH0_S  2
+/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH0  0x00000003
+#define LEDC_TIMER_SEL_LSCH0_M  ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
+#define LEDC_TIMER_SEL_LSCH0_V  0x3
+#define LEDC_TIMER_SEL_LSCH0_S  0
+
+#define LEDC_LSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0004)
+/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH0  0x00003FFF
+#define LEDC_HPOINT_LSCH0_M  ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
+#define LEDC_HPOINT_LSCH0_V  0x3FFF
+#define LEDC_HPOINT_LSCH0_S  0
+
+#define LEDC_LSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x0008)
+/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH0  0x0007FFFF
+#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V  0x7FFFF
+#define LEDC_DUTY_LSCH0_S  0
+
+#define LEDC_LSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x000C)
+/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH0  (BIT(31))
+#define LEDC_DUTY_START_LSCH0_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH0_V  0x1
+#define LEDC_DUTY_START_LSCH0_S  31
+/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH0  (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_V  0x1
+#define LEDC_DUTY_INC_LSCH0_S  30
+/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH0  0x000003FF
+#define LEDC_DUTY_NUM_LSCH0_M  ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
+#define LEDC_DUTY_NUM_LSCH0_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH0_S  20
+/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH0  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH0_M  ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
+#define LEDC_DUTY_CYCLE_LSCH0_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH0_S  10
+/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH0  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH0_M  ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
+#define LEDC_DUTY_SCALE_LSCH0_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH0_S  0
+
+#define LEDC_LSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0010)
+/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH0  0x0007FFFF
+#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V  0x7FFFF
+#define LEDC_DUTY_LSCH0_S  0
+
+#define LEDC_LSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x0014)
+/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH1  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH1_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH1_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH1_S  16
+/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH1  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH1_S  15
+/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH1  0x000003FF
+#define LEDC_OVF_NUM_LSCH1_M  ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S))
+#define LEDC_OVF_NUM_LSCH1_V  0x3FF
+#define LEDC_OVF_NUM_LSCH1_S  5
+/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH1  (BIT(4))
+#define LEDC_PARA_UP_LSCH1_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH1_V  0x1
+#define LEDC_PARA_UP_LSCH1_S  4
+/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH1  (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_V  0x1
+#define LEDC_IDLE_LV_LSCH1_S  3
+/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH1  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH1_S  2
+/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH1  0x00000003
+#define LEDC_TIMER_SEL_LSCH1_M  ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
+#define LEDC_TIMER_SEL_LSCH1_V  0x3
+#define LEDC_TIMER_SEL_LSCH1_S  0
+
+#define LEDC_LSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0018)
+/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH1  0x00003FFF
+#define LEDC_HPOINT_LSCH1_M  ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
+#define LEDC_HPOINT_LSCH1_V  0x3FFF
+#define LEDC_HPOINT_LSCH1_S  0
+
+#define LEDC_LSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x001C)
+/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH1  0x0007FFFF
+#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V  0x7FFFF
+#define LEDC_DUTY_LSCH1_S  0
+
+#define LEDC_LSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x0020)
+/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH1  (BIT(31))
+#define LEDC_DUTY_START_LSCH1_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH1_V  0x1
+#define LEDC_DUTY_START_LSCH1_S  31
+/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH1  (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_V  0x1
+#define LEDC_DUTY_INC_LSCH1_S  30
+/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH1  0x000003FF
+#define LEDC_DUTY_NUM_LSCH1_M  ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
+#define LEDC_DUTY_NUM_LSCH1_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH1_S  20
+/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH1  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH1_M  ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
+#define LEDC_DUTY_CYCLE_LSCH1_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH1_S  10
+/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH1  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH1_M  ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
+#define LEDC_DUTY_SCALE_LSCH1_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH1_S  0
+
+#define LEDC_LSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0024)
+/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH1  0x0007FFFF
+#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V  0x7FFFF
+#define LEDC_DUTY_LSCH1_S  0
+
+#define LEDC_LSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x0028)
+/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH2  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH2_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH2_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH2_S  16
+/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH2  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH2_S  15
+/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH2  0x000003FF
+#define LEDC_OVF_NUM_LSCH2_M  ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S))
+#define LEDC_OVF_NUM_LSCH2_V  0x3FF
+#define LEDC_OVF_NUM_LSCH2_S  5
+/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH2  (BIT(4))
+#define LEDC_PARA_UP_LSCH2_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH2_V  0x1
+#define LEDC_PARA_UP_LSCH2_S  4
+/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH2  (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_V  0x1
+#define LEDC_IDLE_LV_LSCH2_S  3
+/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH2  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH2_S  2
+/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH2  0x00000003
+#define LEDC_TIMER_SEL_LSCH2_M  ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
+#define LEDC_TIMER_SEL_LSCH2_V  0x3
+#define LEDC_TIMER_SEL_LSCH2_S  0
+
+#define LEDC_LSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x002C)
+/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH2  0x00003FFF
+#define LEDC_HPOINT_LSCH2_M  ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
+#define LEDC_HPOINT_LSCH2_V  0x3FFF
+#define LEDC_HPOINT_LSCH2_S  0
+
+#define LEDC_LSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x0030)
+/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH2  0x0007FFFF
+#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V  0x7FFFF
+#define LEDC_DUTY_LSCH2_S  0
+
+#define LEDC_LSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x0034)
+/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH2  (BIT(31))
+#define LEDC_DUTY_START_LSCH2_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH2_V  0x1
+#define LEDC_DUTY_START_LSCH2_S  31
+/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH2  (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_V  0x1
+#define LEDC_DUTY_INC_LSCH2_S  30
+/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH2  0x000003FF
+#define LEDC_DUTY_NUM_LSCH2_M  ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
+#define LEDC_DUTY_NUM_LSCH2_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH2_S  20
+/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH2  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH2_M  ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
+#define LEDC_DUTY_CYCLE_LSCH2_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH2_S  10
+/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH2  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH2_M  ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
+#define LEDC_DUTY_SCALE_LSCH2_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH2_S  0
+
+#define LEDC_LSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0038)
+/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH2  0x0007FFFF
+#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V  0x7FFFF
+#define LEDC_DUTY_LSCH2_S  0
+
+#define LEDC_LSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x003C)
+/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH3  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH3_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH3_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH3_S  16
+/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH3  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH3_S  15
+/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH3  0x000003FF
+#define LEDC_OVF_NUM_LSCH3_M  ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S))
+#define LEDC_OVF_NUM_LSCH3_V  0x3FF
+#define LEDC_OVF_NUM_LSCH3_S  5
+/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH3  (BIT(4))
+#define LEDC_PARA_UP_LSCH3_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH3_V  0x1
+#define LEDC_PARA_UP_LSCH3_S  4
+/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH3  (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_V  0x1
+#define LEDC_IDLE_LV_LSCH3_S  3
+/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH3  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH3_S  2
+/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH3  0x00000003
+#define LEDC_TIMER_SEL_LSCH3_M  ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
+#define LEDC_TIMER_SEL_LSCH3_V  0x3
+#define LEDC_TIMER_SEL_LSCH3_S  0
+
+#define LEDC_LSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0040)
+/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH3  0x00003FFF
+#define LEDC_HPOINT_LSCH3_M  ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
+#define LEDC_HPOINT_LSCH3_V  0x3FFF
+#define LEDC_HPOINT_LSCH3_S  0
+
+#define LEDC_LSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x0044)
+/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH3  0x0007FFFF
+#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V  0x7FFFF
+#define LEDC_DUTY_LSCH3_S  0
+
+#define LEDC_LSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x0048)
+/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH3  (BIT(31))
+#define LEDC_DUTY_START_LSCH3_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH3_V  0x1
+#define LEDC_DUTY_START_LSCH3_S  31
+/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH3  (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_V  0x1
+#define LEDC_DUTY_INC_LSCH3_S  30
+/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH3  0x000003FF
+#define LEDC_DUTY_NUM_LSCH3_M  ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
+#define LEDC_DUTY_NUM_LSCH3_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH3_S  20
+/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH3  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH3_M  ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
+#define LEDC_DUTY_CYCLE_LSCH3_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH3_S  10
+/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH3  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH3_M  ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
+#define LEDC_DUTY_SCALE_LSCH3_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH3_S  0
+
+#define LEDC_LSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x004C)
+/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH3  0x0007FFFF
+#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V  0x7FFFF
+#define LEDC_DUTY_LSCH3_S  0
+
+#define LEDC_LSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x0050)
+/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH4  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH4_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH4_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH4_S  16
+/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH4  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH4_S  15
+/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH4  0x000003FF
+#define LEDC_OVF_NUM_LSCH4_M  ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S))
+#define LEDC_OVF_NUM_LSCH4_V  0x3FF
+#define LEDC_OVF_NUM_LSCH4_S  5
+/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH4  (BIT(4))
+#define LEDC_PARA_UP_LSCH4_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH4_V  0x1
+#define LEDC_PARA_UP_LSCH4_S  4
+/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH4  (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_V  0x1
+#define LEDC_IDLE_LV_LSCH4_S  3
+/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH4  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH4_S  2
+/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH4  0x00000003
+#define LEDC_TIMER_SEL_LSCH4_M  ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
+#define LEDC_TIMER_SEL_LSCH4_V  0x3
+#define LEDC_TIMER_SEL_LSCH4_S  0
+
+#define LEDC_LSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0054)
+/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH4  0x00003FFF
+#define LEDC_HPOINT_LSCH4_M  ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
+#define LEDC_HPOINT_LSCH4_V  0x3FFF
+#define LEDC_HPOINT_LSCH4_S  0
+
+#define LEDC_LSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x0058)
+/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH4  0x0007FFFF
+#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V  0x7FFFF
+#define LEDC_DUTY_LSCH4_S  0
+
+#define LEDC_LSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x005C)
+/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH4  (BIT(31))
+#define LEDC_DUTY_START_LSCH4_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH4_V  0x1
+#define LEDC_DUTY_START_LSCH4_S  31
+/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH4  (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_V  0x1
+#define LEDC_DUTY_INC_LSCH4_S  30
+/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH4  0x000003FF
+#define LEDC_DUTY_NUM_LSCH4_M  ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
+#define LEDC_DUTY_NUM_LSCH4_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH4_S  20
+/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH4  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH4_M  ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
+#define LEDC_DUTY_CYCLE_LSCH4_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH4_S  10
+/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH4  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH4_M  ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
+#define LEDC_DUTY_SCALE_LSCH4_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH4_S  0
+
+#define LEDC_LSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0060)
+/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH4  0x0007FFFF
+#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V  0x7FFFF
+#define LEDC_DUTY_LSCH4_S  0
+
+#define LEDC_LSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0064)
+/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH5  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH5_M  (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH5_V  0x1
+#define LEDC_OVF_CNT_RESET_LSCH5_S  16
+/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH5  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH5_S  15
+/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH5  0x000003FF
+#define LEDC_OVF_NUM_LSCH5_M  ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S))
+#define LEDC_OVF_NUM_LSCH5_V  0x3FF
+#define LEDC_OVF_NUM_LSCH5_S  5
+/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH5  (BIT(4))
+#define LEDC_PARA_UP_LSCH5_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH5_V  0x1
+#define LEDC_PARA_UP_LSCH5_S  4
+/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH5  (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_V  0x1
+#define LEDC_IDLE_LV_LSCH5_S  3
+/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH5  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH5_S  2
+/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH5  0x00000003
+#define LEDC_TIMER_SEL_LSCH5_M  ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
+#define LEDC_TIMER_SEL_LSCH5_V  0x3
+#define LEDC_TIMER_SEL_LSCH5_S  0
+
+#define LEDC_LSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0068)
+/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH5  0x00003FFF
+#define LEDC_HPOINT_LSCH5_M  ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
+#define LEDC_HPOINT_LSCH5_V  0x3FFF
+#define LEDC_HPOINT_LSCH5_S  0
+
+#define LEDC_LSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x006C)
+/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH5  0x0007FFFF
+#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V  0x7FFFF
+#define LEDC_DUTY_LSCH5_S  0
+
+#define LEDC_LSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0070)
+/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH5  (BIT(31))
+#define LEDC_DUTY_START_LSCH5_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH5_V  0x1
+#define LEDC_DUTY_START_LSCH5_S  31
+/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH5  (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_V  0x1
+#define LEDC_DUTY_INC_LSCH5_S  30
+/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH5  0x000003FF
+#define LEDC_DUTY_NUM_LSCH5_M  ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
+#define LEDC_DUTY_NUM_LSCH5_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH5_S  20
+/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH5  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH5_M  ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
+#define LEDC_DUTY_CYCLE_LSCH5_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH5_S  10
+/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH5  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH5_M  ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
+#define LEDC_DUTY_SCALE_LSCH5_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH5_S  0
+
+#define LEDC_LSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0074)
+/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH5  0x0007FFFF
+#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V  0x7FFFF
+#define LEDC_DUTY_LSCH5_S  0
+
+#define LEDC_LSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x00a0)
+/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER0_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER0_PARA_UP_V  0x1
+#define LEDC_LSTIMER0_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER0  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER0_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER0_V  0x1
+#define LEDC_TICK_SEL_LSTIMER0_S  24
+/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER0_RST  (BIT(23))
+#define LEDC_LSTIMER0_RST_M  (BIT(23))
+#define LEDC_LSTIMER0_RST_V  0x1
+#define LEDC_LSTIMER0_RST_S  23
+/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_PAUSE  (BIT(22))
+#define LEDC_LSTIMER0_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER0_PAUSE_V  0x1
+#define LEDC_LSTIMER0_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER0  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER0_M  ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S))
+#define LEDC_CLK_DIV_LSTIMER0_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER0_S  4
+/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER0_DUTY_RES_M  ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
+#define LEDC_LSTIMER0_DUTY_RES_V  0xF
+#define LEDC_LSTIMER0_DUTY_RES_S  0
+
+#define LEDC_LSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x00a4)
+/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_CNT  0x00003FFF
+#define LEDC_LSTIMER0_CNT_M  ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
+#define LEDC_LSTIMER0_CNT_V  0x3FFF
+#define LEDC_LSTIMER0_CNT_S  0
+
+#define LEDC_LSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x00a8)
+/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER1_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER1_PARA_UP_V  0x1
+#define LEDC_LSTIMER1_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER1  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER1_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER1_V  0x1
+#define LEDC_TICK_SEL_LSTIMER1_S  24
+/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER1_RST  (BIT(23))
+#define LEDC_LSTIMER1_RST_M  (BIT(23))
+#define LEDC_LSTIMER1_RST_V  0x1
+#define LEDC_LSTIMER1_RST_S  23
+/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_PAUSE  (BIT(22))
+#define LEDC_LSTIMER1_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER1_PAUSE_V  0x1
+#define LEDC_LSTIMER1_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER1  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER1_M  ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S))
+#define LEDC_CLK_DIV_LSTIMER1_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER1_S  4
+/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER1_DUTY_RES_M  ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
+#define LEDC_LSTIMER1_DUTY_RES_V  0xF
+#define LEDC_LSTIMER1_DUTY_RES_S  0
+
+#define LEDC_LSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x00aC)
+/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_CNT  0x00003FFF
+#define LEDC_LSTIMER1_CNT_M  ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
+#define LEDC_LSTIMER1_CNT_V  0x3FFF
+#define LEDC_LSTIMER1_CNT_S  0
+
+#define LEDC_LSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x00b0)
+/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER2_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER2_PARA_UP_V  0x1
+#define LEDC_LSTIMER2_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER2  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER2_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER2_V  0x1
+#define LEDC_TICK_SEL_LSTIMER2_S  24
+/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER2_RST  (BIT(23))
+#define LEDC_LSTIMER2_RST_M  (BIT(23))
+#define LEDC_LSTIMER2_RST_V  0x1
+#define LEDC_LSTIMER2_RST_S  23
+/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_PAUSE  (BIT(22))
+#define LEDC_LSTIMER2_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER2_PAUSE_V  0x1
+#define LEDC_LSTIMER2_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER2  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER2_M  ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S))
+#define LEDC_CLK_DIV_LSTIMER2_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER2_S  4
+/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER2_DUTY_RES_M  ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
+#define LEDC_LSTIMER2_DUTY_RES_V  0xF
+#define LEDC_LSTIMER2_DUTY_RES_S  0
+
+#define LEDC_LSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x00b4)
+/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_CNT  0x00003FFF
+#define LEDC_LSTIMER2_CNT_M  ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
+#define LEDC_LSTIMER2_CNT_V  0x3FFF
+#define LEDC_LSTIMER2_CNT_S  0
+
+#define LEDC_LSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x00b8)
+/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_PARA_UP  (BIT(25))
+#define LEDC_LSTIMER3_PARA_UP_M  (BIT(25))
+#define LEDC_LSTIMER3_PARA_UP_V  0x1
+#define LEDC_LSTIMER3_PARA_UP_S  25
+/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER3  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER3_M  (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER3_V  0x1
+#define LEDC_TICK_SEL_LSTIMER3_S  24
+/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER3_RST  (BIT(23))
+#define LEDC_LSTIMER3_RST_M  (BIT(23))
+#define LEDC_LSTIMER3_RST_V  0x1
+#define LEDC_LSTIMER3_RST_S  23
+/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_PAUSE  (BIT(22))
+#define LEDC_LSTIMER3_PAUSE_M  (BIT(22))
+#define LEDC_LSTIMER3_PAUSE_V  0x1
+#define LEDC_LSTIMER3_PAUSE_S  22
+/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER3  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER3_M  ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S))
+#define LEDC_CLK_DIV_LSTIMER3_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER3_S  4
+/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_DUTY_RES  0x0000000F
+#define LEDC_LSTIMER3_DUTY_RES_M  ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
+#define LEDC_LSTIMER3_DUTY_RES_V  0xF
+#define LEDC_LSTIMER3_DUTY_RES_S  0
+
+#define LEDC_LSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x00BC)
+/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_CNT  0x00003FFF
+#define LEDC_LSTIMER3_CNT_M  ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
+#define LEDC_LSTIMER3_CNT_V  0x3FFF
+#define LEDC_LSTIMER3_CNT_S  0
+
+#define LEDC_INT_RAW_REG          (DR_REG_LEDC_BASE + 0x00C0)
+/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_RAW    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_RAW    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_RAW    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_RAW    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_RAW    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_RAW    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S  4
+/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_RAW  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_RAW_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_RAW_S  3
+/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_RAW  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_RAW_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_RAW_S  2
+/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_RAW  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_RAW_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_RAW_S  1
+/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_RAW  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_RAW_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_RAW_S  0
+
+#define LEDC_INT_ST_REG          (DR_REG_LEDC_BASE + 0x00c4)
+/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ST  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ST_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ST  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ST_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ST  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ST_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ST    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ST_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ST    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ST_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ST    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ST_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S  4
+/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_ST  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ST_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_ST_S  3
+/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_ST  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ST_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_ST_S  2
+/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_ST  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ST_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_ST_S  1
+/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_ST  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ST_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_ST_S  0
+
+#define LEDC_INT_ENA_REG          (DR_REG_LEDC_BASE + 0xC8)
+/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ENA    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ENA    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ENA    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ENA    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ENA    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ENA    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S  4
+/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_ENA  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ENA_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_ENA_S  3
+/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_ENA  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ENA_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_ENA_S  2
+/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_ENA  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ENA_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_ENA_S  1
+/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_ENA  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ENA_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_ENA_S  0
+
+#define LEDC_INT_CLR_REG          (DR_REG_LEDC_BASE + 0xCC)
+/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_CLR    (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_S  15
+/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_CLR    (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_S  14
+/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_CLR    (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_S  13
+/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_CLR    (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_S  12
+/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_CLR    (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_S  11
+/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_CLR    (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_S  10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: reg_duty_chng_end_lsch5_int_clr..*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S  9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S  8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M  (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S  7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M  (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S  6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M  (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S  5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M  (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S  4
+/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_CLR  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_CLR_M  (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_CLR_S  3
+/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_CLR  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_CLR_M  (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_CLR_S  2
+/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_CLR  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_CLR_M  (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_CLR_S  1
+/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_CLR  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_CLR_M  (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_CLR_S  0
+
+#define LEDC_CONF_REG          (DR_REG_LEDC_BASE + 0x00d0)
+/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_CLK_EN  (BIT(31))
+#define LEDC_CLK_EN_M  (BIT(31))
+#define LEDC_CLK_EN_V  0x1
+#define LEDC_CLK_EN_S  31
+/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define LEDC_APB_CLK_SEL  0x00000003
+#define LEDC_APB_CLK_SEL_M  ((LEDC_APB_CLK_SEL_V)<<(LEDC_APB_CLK_SEL_S))
+#define LEDC_APB_CLK_SEL_V  0x3
+#define LEDC_APB_CLK_SEL_S  0
+
+#define LEDC_DATE_REG          (DR_REG_LEDC_BASE + 0x00FC)
+/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19061700 ; */
+/*description: */
+#define LEDC_DATE  0xFFFFFFFF
+#define LEDC_DATE_M  ((LEDC_DATE_V)<<(LEDC_DATE_S))
+#define LEDC_DATE_V  0xFFFFFFFF
+#define LEDC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_LEDC_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/ledc_struct.h b/components/soc/esp32c3/register/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/ledc_struct.h
rename to components/soc/esp32c3/register/soc/ledc_struct.h
diff --git a/components/soc/esp32c3/register/soc/nrx_reg.h b/components/soc/esp32c3/register/soc/nrx_reg.h
new file mode 100644
index 00000000000..16e6e148497
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/nrx_reg.h
@@ -0,0 +1,47 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+
+/* Some of the WiFi RX control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
+#define NRX_CHAN_EST_FORCE_PU (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_V 1
+#define NRX_CHAN_EST_FORCE_PU_S 7
+#define NRX_CHAN_EST_FORCE_PD (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_V 1
+#define NRX_CHAN_EST_FORCE_PD_S 6
+#define NRX_RX_ROT_FORCE_PU (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_V 1
+#define NRX_RX_ROT_FORCE_PU_S 5
+#define NRX_RX_ROT_FORCE_PD (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_V 1
+#define NRX_RX_ROT_FORCE_PD_S 4
+#define NRX_VIT_FORCE_PU (BIT(3))
+#define NRX_VIT_FORCE_PU_M (BIT(3))
+#define NRX_VIT_FORCE_PU_V 1
+#define NRX_VIT_FORCE_PU_S 3
+#define NRX_VIT_FORCE_PD (BIT(2))
+#define NRX_VIT_FORCE_PD_M (BIT(2))
+#define NRX_VIT_FORCE_PD_V 1
+#define NRX_VIT_FORCE_PD_S 2
+#define NRX_DEMAP_FORCE_PU (BIT(1))
+#define NRX_DEMAP_FORCE_PU_M (BIT(1))
+#define NRX_DEMAP_FORCE_PU_V 1
+#define NRX_DEMAP_FORCE_PU_S 1
+#define NRX_DEMAP_FORCE_PD (BIT(0))
+#define NRX_DEMAP_FORCE_PD_M (BIT(0))
+#define NRX_DEMAP_FORCE_PD_V 1
+#define NRX_DEMAP_FORCE_PD_S 0
diff --git a/components/soc/esp32c3/register/soc/reg_base.h b/components/soc/esp32c3/register/soc/reg_base.h
new file mode 100644
index 00000000000..cf38bd9dbda
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/reg_base.h
@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DR_REG_SYSTEM_BASE                      0x600c0000
+#define DR_REG_SENSITIVE_BASE                   0x600c1000
+#define DR_REG_INTERRUPT_BASE                   0x600c2000
+#define DR_REG_EXTMEM_BASE                      0x600c4000
+#define DR_REG_MMU_TABLE                        0x600c5000
+#define DR_REG_AES_BASE                         0x6003a000
+#define DR_REG_SHA_BASE                         0x6003b000
+#define DR_REG_RSA_BASE                         0x6003c000
+#define DR_REG_HMAC_BASE                        0x6003e000
+#define DR_REG_DIGITAL_SIGNATURE_BASE           0x6003d000
+#define DR_REG_GDMA_BASE                        0x6003f000
+#define DR_REG_ASSIST_DEBUG_BASE                0x600ce000
+#define DR_REG_DEDICATED_GPIO_BASE              0x600cf000
+#define DR_REG_WORLD_CNTL_BASE                  0x600d0000
+#define DR_REG_UART_BASE                        0x60000000
+#define DR_REG_SPI1_BASE                        0x60002000
+#define DR_REG_SPI0_BASE                        0x60003000
+#define DR_REG_GPIO_BASE                        0x60004000
+#define DR_REG_FE2_BASE                         0x60005000
+#define DR_REG_FE_BASE                          0x60006000
+#define DR_REG_RTCCNTL_BASE                     0x60008000
+#define DR_REG_IO_MUX_BASE                      0x60009000
+#define DR_REG_RTC_I2C_BASE                     0x6000e000
+#define DR_REG_UART1_BASE                       0x60010000
+#define DR_REG_I2C_EXT_BASE                     0x60013000
+#define DR_REG_UHCI0_BASE                       0x60014000
+#define DR_REG_RMT_BASE                         0x60016000
+#define DR_REG_LEDC_BASE                        0x60019000
+#define DR_REG_EFUSE_BASE                       0x60008800
+#define DR_REG_NRX_BASE                         0x6001CC00
+#define DR_REG_BB_BASE                          0x6001D000
+#define DR_REG_TIMERGROUP0_BASE                 0x6001F000
+#define DR_REG_TIMERGROUP1_BASE                 0x60020000
+#define DR_REG_SYSTIMER_BASE                    0x60023000
+#define DR_REG_SPI2_BASE                        0x60024000
+#define DR_REG_SYSCON_BASE                      0x60026000
+#define DR_REG_APB_CTRL_BASE                    0x60026000    /* Old name for SYSCON, to be removed */
+#define DR_REG_TWAI_BASE                        0x6002B000
+#define DR_REG_I2S_BASE                         0x6002D000
+#define DR_REG_APB_SARADC_BASE                  0x60040000
+#define DR_REG_USB_SERIAL_JTAG_BASE             0x60043000
+#define DR_REG_XTS_AES_BASE                     0x600CC000
+
+/* For backward compatibility with the older register names */
+#define DR_REG_AES_XTS_BASE                     DR_REG_XTS_AES_BASE
diff --git a/components/soc/esp32c3/include/soc/rmt_reg.h b/components/soc/esp32c3/register/soc/rmt_reg.h
similarity index 99%
rename from components/soc/esp32c3/include/soc/rmt_reg.h
rename to components/soc/esp32c3/register/soc/rmt_reg.h
index 106fc786495..1ac39c2af35 100644
--- a/components/soc/esp32c3/include/soc/rmt_reg.h
+++ b/components/soc/esp32c3/register/soc/rmt_reg.h
@@ -5,7 +5,7 @@
  */
 #pragma once
 
-#include "soc.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32c3/include/soc/rmt_struct.h b/components/soc/esp32c3/register/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/rmt_struct.h
rename to components/soc/esp32c3/register/soc/rmt_struct.h
diff --git a/components/soc/esp32c3/register/soc/rtc_cntl_reg.h b/components/soc/esp32c3/register/soc/rtc_cntl_reg.h
new file mode 100644
index 00000000000..e67f6ed93d8
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/rtc_cntl_reg.h
@@ -0,0 +1,2621 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_RTC_CNTL_REG_H_
+#define _SOC_RTC_CNTL_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
+#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
+
+#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0000)
+/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: SW system reset*/
+#define RTC_CNTL_SW_SYS_RST  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_V  0x1
+#define RTC_CNTL_SW_SYS_RST_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force no reset in deep sleep*/
+#define RTC_CNTL_DG_WRAP_FORCE_NORST  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
+/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: digital wrap force reset in deep sleep*/
+#define RTC_CNTL_DG_WRAP_FORCE_RST  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
+/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_ANALOG_FORCE_NOISO  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
+/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_PLL_FORCE_NOISO  (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_M  (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_PLL_FORCE_NOISO_S  27
+/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_XTL_FORCE_NOISO  (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_M  (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_XTL_FORCE_NOISO_S  26
+/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_ANALOG_FORCE_ISO  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
+/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_PLL_FORCE_ISO  (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_M  (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_V  0x1
+#define RTC_CNTL_PLL_FORCE_ISO_S  24
+/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_XTL_FORCE_ISO  (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_M  (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_V  0x1
+#define RTC_CNTL_XTL_FORCE_ISO_S  23
+/* RTC_CNTL_XTL_EXT_CTR_SEL : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_XTL_EXT_CTR_SEL  0x00000007
+#define RTC_CNTL_XTL_EXT_CTR_SEL_M  ((RTC_CNTL_XTL_EXT_CTR_SEL_V)<<(RTC_CNTL_XTL_EXT_CTR_SEL_S))
+#define RTC_CNTL_XTL_EXT_CTR_SEL_V  0x7
+#define RTC_CNTL_XTL_EXT_CTR_SEL_S  20
+/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */
+/*description: wait bias_sleep and current source wakeup*/
+#define RTC_CNTL_XTL_EN_WAIT  0x0000000F
+#define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
+#define RTC_CNTL_XTL_EN_WAIT_V  0xF
+#define RTC_CNTL_XTL_EN_WAIT_S  14
+/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
+/*description: crystall force power up*/
+#define RTC_CNTL_XTL_FORCE_PU  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_V  0x1
+#define RTC_CNTL_XTL_FORCE_PU_S  13
+/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: crystall force power down*/
+#define RTC_CNTL_XTL_FORCE_PD  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_V  0x1
+#define RTC_CNTL_XTL_FORCE_PD_S  12
+/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: BB_PLL force power up*/
+#define RTC_CNTL_BBPLL_FORCE_PU  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PU_S  11
+/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: BB_PLL force power down*/
+#define RTC_CNTL_BBPLL_FORCE_PD  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PD_S  10
+/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: BB_PLL_I2C force power up*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
+/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: BB_PLL _I2C force power down*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
+/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: BB_I2C force power up*/
+#define RTC_CNTL_BB_I2C_FORCE_PU  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
+/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: BB_I2C force power down*/
+#define RTC_CNTL_BB_I2C_FORCE_PD  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
+/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: PRO CPU SW reset*/
+#define RTC_CNTL_SW_PROCPU_RST  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_V  0x1
+#define RTC_CNTL_SW_PROCPU_RST_S  5
+/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: APP CPU SW reset*/
+#define RTC_CNTL_SW_APPCPU_RST  (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_M  (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_V  0x1
+#define RTC_CNTL_SW_APPCPU_RST_S  4
+/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} ==
+ 0x86 will stall PRO CPU*/
+#define RTC_CNTL_SW_STALL_PROCPU_C0  0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
+/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
+ 0x86 will stall APP CPU*/
+#define RTC_CNTL_SW_STALL_APPCPU_C0  0x00000003
+#define RTC_CNTL_SW_STALL_APPCPU_C0_M  ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_APPCPU_C0_S  0
+
+#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x0004)
+/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define RTC_CNTL_SLP_VAL_LO  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
+#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_S  0
+
+#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x0008)
+/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */
+/*description: timer alarm enable bit*/
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
+/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC sleep timer high 16 bits*/
+#define RTC_CNTL_SLP_VAL_HI  0x0000FFFF
+#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
+#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
+#define RTC_CNTL_SLP_VAL_HI_S  0
+
+#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0x000C)
+/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Set 1: to update register with RTC timer*/
+#define RTC_CNTL_TIME_UPDATE  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_V  0x1
+#define RTC_CNTL_TIME_UPDATE_S  31
+/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: enable to record system reset time*/
+#define RTC_CNTL_TIMER_SYS_RST  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_V  0x1
+#define RTC_CNTL_TIMER_SYS_RST_S  29
+/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Enable to record 40M XTAL OFF time*/
+#define RTC_CNTL_TIMER_XTL_OFF  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
+#define RTC_CNTL_TIMER_XTL_OFF_S  28
+/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable to record system stall time*/
+#define RTC_CNTL_TIMER_SYS_STALL  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
+#define RTC_CNTL_TIMER_SYS_STALL_S  27
+
+#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x0010)
+/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits*/
+#define RTC_CNTL_TIMER_VALUE0_LOW  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
+#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x0014)
+/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits*/
+#define RTC_CNTL_TIMER_VALUE0_HIGH  0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
+
+#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x0018)
+/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: sleep enable bit*/
+#define RTC_CNTL_SLEEP_EN  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_V  0x1
+#define RTC_CNTL_SLEEP_EN_S  31
+/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: leep reject bit*/
+#define RTC_CNTL_SLP_REJECT  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_V  0x1
+#define RTC_CNTL_SLP_REJECT_S  30
+/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: leep wakeup bit*/
+#define RTC_CNTL_SLP_WAKEUP  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_S  29
+/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: SDIO active indication*/
+#define RTC_CNTL_SDIO_ACTIVE_IND  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
+#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
+/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: APB to RTC using bridge*/
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
+/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear rtc sleep reject cause*/
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
+/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rtc software interrupt to main cpu*/
+#define RTC_CNTL_SW_CPU_INT  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_V  0x1
+#define RTC_CNTL_SW_CPU_INT_S  0
+
+#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x001C)
+/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
+/*description: PLL wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_PLL_BUF_WAIT  0x000000FF
+#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
+#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
+#define RTC_CNTL_PLL_BUF_WAIT_S  24
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
+/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
+/*description: XTAL wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_XTL_BUF_WAIT  0x000003FF
+#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
+#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
+#define RTC_CNTL_XTL_BUF_WAIT_S  14
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  100
+/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
+/*description: CK8M wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_CK8M_WAIT  0x000000FF
+#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
+#define RTC_CNTL_CK8M_WAIT_V  0xFF
+#define RTC_CNTL_CK8M_WAIT_S  6
+/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
+/*description: CPU stall wait cycles in fast_clk_rtc*/
+#define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
+#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
+#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
+#define RTC_CNTL_CPU_STALL_WAIT_S  1
+/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: CPU stall enable bit*/
+#define RTC_CNTL_CPU_STALL_EN  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_V  0x1
+#define RTC_CNTL_CPU_STALL_EN_S  0
+
+#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x0020)
+/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
+/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/
+#define RTC_CNTL_MIN_TIME_CK8M_OFF  0x000000FF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
+
+#define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x0024)
+/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_BT_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_BT_POWERUP_TIMER_M  ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S))
+#define RTC_CNTL_BT_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_BT_POWERUP_TIMER_S  25
+/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_BT_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_BT_WAIT_TIMER_M  ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S))
+#define RTC_CNTL_BT_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_BT_WAIT_TIMER_S  16
+/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_WIFI_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_M  ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
+#define RTC_CNTL_WIFI_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_S  9
+/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_WIFI_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_M  ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
+#define RTC_CNTL_WIFI_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_S  0
+
+#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x0028)
+/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
+/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M  ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S))
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S  9
+/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M  ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S))
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S  0
+
+#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x002C)
+/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
+/*description: minimal sleep cycles in slow_clk_rtc*/
+#define RTC_CNTL_MIN_SLP_VAL  0x000000FF
+#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
+#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
+#define RTC_CNTL_MIN_SLP_VAL_S  8
+
+#define RTC_CNTL_TIMER6_REG          (DR_REG_RTCCNTL_BASE + 0x0030)
+/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M  ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_M  ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S))
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_S  16
+
+#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0034)
+/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_PLL_I2C_PU  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_V  0x1
+#define RTC_CNTL_PLL_I2C_PU_S  31
+/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: CKGEN_I2C power up*/
+#define RTC_CNTL_CKGEN_I2C_PU  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
+#define RTC_CNTL_CKGEN_I2C_PU_S  30
+/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: 1: RFRX_PBUS power up*/
+#define RTC_CNTL_RFRX_PBUS_PU  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
+#define RTC_CNTL_RFRX_PBUS_PU_S  28
+/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: TXRF_I2C power up*/
+#define RTC_CNTL_TXRF_I2C_PU  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_V  0x1
+#define RTC_CNTL_TXRF_I2C_PU_S  27
+/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: PVTMON power up*/
+#define RTC_CNTL_PVTMON_PU  (BIT(26))
+#define RTC_CNTL_PVTMON_PU_M  (BIT(26))
+#define RTC_CNTL_PVTMON_PU_V  0x1
+#define RTC_CNTL_PVTMON_PU_S  26
+/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: start BBPLL calibration during sleep*/
+#define RTC_CNTL_BBPLL_CAL_SLP_START  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
+/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: PLLA force power up*/
+#define RTC_CNTL_PLLA_FORCE_PU  (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_M  (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_V  0x1
+#define RTC_CNTL_PLLA_FORCE_PU_S  24
+/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: PLLA force power down*/
+#define RTC_CNTL_PLLA_FORCE_PD  (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_M  (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_V  0x1
+#define RTC_CNTL_PLLA_FORCE_PD_S  23
+/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: PLLA force power up*/
+#define RTC_CNTL_SAR_I2C_PU  (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_V  0x1
+#define RTC_CNTL_SAR_I2C_PU_S  22
+/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GLITCH_RST_EN  (BIT(20))
+#define RTC_CNTL_GLITCH_RST_EN_M  (BIT(20))
+#define RTC_CNTL_GLITCH_RST_EN_V  0x1
+#define RTC_CNTL_GLITCH_RST_EN_S  20
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU  (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD  (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
+
+#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x0038)
+/* RTC_CNTL_DRESET_MASK_PROCPU : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DRESET_MASK_PROCPU  (BIT(25))
+#define RTC_CNTL_DRESET_MASK_PROCPU_M  (BIT(25))
+#define RTC_CNTL_DRESET_MASK_PROCPU_V  0x1
+#define RTC_CNTL_DRESET_MASK_PROCPU_S  25
+/* RTC_CNTL_DRESET_MASK_APPCPU : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DRESET_MASK_APPCPU  (BIT(24))
+#define RTC_CNTL_DRESET_MASK_APPCPU_M  (BIT(24))
+#define RTC_CNTL_DRESET_MASK_APPCPU_V  0x1
+#define RTC_CNTL_DRESET_MASK_APPCPU_S  24
+/* RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU  (BIT(23))
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_M  (BIT(23))
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_V  0x1
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_APPCPU_S  23
+/* RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU  (BIT(22))
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_M  (BIT(22))
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_V  0x1
+#define RTC_CNTL_JTAG_RESET_FLAG_CLR_PROCPU_S  22
+/* RTC_CNTL_JTAG_RESET_FLAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU  (BIT(21))
+#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_M  (BIT(21))
+#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_V  0x1
+#define RTC_CNTL_JTAG_RESET_FLAG_APPCPU_S  21
+/* RTC_CNTL_JTAG_RESET_FLAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU  (BIT(20))
+#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_M  (BIT(20))
+#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_V  0x1
+#define RTC_CNTL_JTAG_RESET_FLAG_PROCPU_S  20
+/* RTC_CNTL_OCD_HALT_ON_RESET_PROCPU : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: PROCPU OcdHaltOnReset*/
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU  (BIT(19))
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_M  (BIT(19))
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_V  0x1
+#define RTC_CNTL_OCD_HALT_ON_RESET_PROCPU_S  19
+/* RTC_CNTL_OCD_HALT_ON_RESET_APPCPU : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: APPCPU OcdHaltOnReset*/
+#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU  (BIT(18))
+#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_M  (BIT(18))
+#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_V  0x1
+#define RTC_CNTL_OCD_HALT_ON_RESET_APPCPU_S  18
+/* RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: clear APP CPU reset flag*/
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU  (BIT(17))
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_M  (BIT(17))
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_V  0x1
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_APPCPU_S  17
+/* RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: clear PRO CPU reset_flag*/
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU  (BIT(16))
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_M  (BIT(16))
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_V  0x1
+#define RTC_CNTL_ALL_RESET_FLAG_CLR_PROCPU_S  16
+/* RTC_CNTL_ALL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: APP CPU reset flag*/
+#define RTC_CNTL_ALL_RESET_FLAG_APPCPU  (BIT(15))
+#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_M  (BIT(15))
+#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_V  0x1
+#define RTC_CNTL_ALL_RESET_FLAG_APPCPU_S  15
+/* RTC_CNTL_ALL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: PRO CPU reset_flag*/
+#define RTC_CNTL_ALL_RESET_FLAG_PROCPU  (BIT(14))
+#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_M  (BIT(14))
+#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_V  0x1
+#define RTC_CNTL_ALL_RESET_FLAG_PROCPU_S  14
+/* RTC_CNTL_STAT_VECTOR_SEL_PROCPU : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: PRO CPU state vector sel*/
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU  (BIT(13))
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_M  (BIT(13))
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_V  0x1
+#define RTC_CNTL_STAT_VECTOR_SEL_PROCPU_S  13
+/* RTC_CNTL_STAT_VECTOR_SEL_APPCPU : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: APP CPU state vector sel*/
+#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU  (BIT(12))
+#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_M  (BIT(12))
+#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_V  0x1
+#define RTC_CNTL_STAT_VECTOR_SEL_APPCPU_S  12
+/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
+/*description: reset cause of APP CPU*/
+#define RTC_CNTL_RESET_CAUSE_APPCPU  0x0000003F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_M  ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
+#define RTC_CNTL_RESET_CAUSE_APPCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_S  6
+/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
+/*description: reset cause of PRO CPU*/
+#define RTC_CNTL_RESET_CAUSE_PROCPU  0x0000003F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
+#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
+
+#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x003C)
+/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */
+/*description: wakeup enable bitmap*/
+#define RTC_CNTL_WAKEUP_ENA  0x0001FFFF
+#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
+#define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_ENA_S  15
+
+#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x0040)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_ENA  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enable gitch det interrupt*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S  16
+/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt*/
+#define RTC_CNTL_SWD_INT_ENA  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
+/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt*/
+#define RTC_CNTL_WDT_INT_ENA  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
+
+#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x0044)
+/* RTC_CNTL_BBPLL_CAL_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_RAW  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_RAW_S  20
+/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: glitch_det_interrupt_raw*/
+#define RTC_CNTL_GLITCH_DET_INT_RAW  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_RAW_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_RAW_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_RAW_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt raw*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S  16
+/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt raw*/
+#define RTC_CNTL_SWD_INT_RAW  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_V  0x1
+#define RTC_CNTL_SWD_INT_RAW_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt raw*/
+#define RTC_CNTL_MAIN_TIMER_INT_RAW  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
+/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt raw*/
+#define RTC_CNTL_BROWN_OUT_INT_RAW  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
+/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt raw*/
+#define RTC_CNTL_WDT_INT_RAW  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_V  0x1
+#define RTC_CNTL_WDT_INT_RAW_S  3
+/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt raw*/
+#define RTC_CNTL_SLP_REJECT_INT_RAW  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt raw*/
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
+
+#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x0048)
+/* RTC_CNTL_BBPLL_CAL_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_ST  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ST_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ST_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ST_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: glitch_det_interrupt state*/
+#define RTC_CNTL_GLITCH_DET_INT_ST  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ST_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ST_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ST_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt state*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S  16
+/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt state*/
+#define RTC_CNTL_SWD_INT_ST  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_V  0x1
+#define RTC_CNTL_SWD_INT_ST_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt state*/
+#define RTC_CNTL_MAIN_TIMER_INT_ST  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt state*/
+#define RTC_CNTL_BROWN_OUT_INT_ST  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
+/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt state*/
+#define RTC_CNTL_WDT_INT_ST  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_V  0x1
+#define RTC_CNTL_WDT_INT_ST_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt state*/
+#define RTC_CNTL_SLP_REJECT_INT_ST  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt state*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ST  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
+
+#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x004C)
+/* RTC_CNTL_BBPLL_CAL_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_CLR  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_CLR_S  20
+/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Clear glitch det interrupt state*/
+#define RTC_CNTL_GLITCH_DET_INT_CLR  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_CLR_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_CLR_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_CLR_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S  16
+/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Clear super watch dog interrupt state*/
+#define RTC_CNTL_SWD_INT_CLR  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_V  0x1
+#define RTC_CNTL_SWD_INT_CLR_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Clear RTC main timer interrupt state*/
+#define RTC_CNTL_MAIN_TIMER_INT_CLR  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
+/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Clear brown out interrupt state*/
+#define RTC_CNTL_BROWN_OUT_INT_CLR  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
+/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state*/
+#define RTC_CNTL_WDT_INT_CLR  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_V  0x1
+#define RTC_CNTL_WDT_INT_CLR_S  3
+/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Clear sleep reject interrupt state*/
+#define RTC_CNTL_SLP_REJECT_INT_CLR  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Clear sleep wakeup interrupt state*/
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
+
+#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x0050)
+/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH0  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
+#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_S  0
+
+#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x0054)
+/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH1  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
+#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_S  0
+
+#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x0058)
+/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH2  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
+#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_S  0
+
+#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x005C)
+/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH3  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
+#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_S  0
+
+#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0060)
+/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_XTL_EXT_CTR_EN  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
+/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: power down XTAL at high level*/
+#define RTC_CNTL_XTL_EXT_CTR_LV  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
+/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: XTAL_32K sel. 0: external XTAL_32K*/
+#define RTC_CNTL_XTAL32K_GPIO_SEL  (BIT(23))
+#define RTC_CNTL_XTAL32K_GPIO_SEL_M  (BIT(23))
+#define RTC_CNTL_XTAL32K_GPIO_SEL_V  0x1
+#define RTC_CNTL_XTAL32K_GPIO_SEL_S  23
+/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
+/*description: state of 32k_wdt*/
+#define RTC_CNTL_WDT_STATE  0x00000007
+#define RTC_CNTL_WDT_STATE_M  ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S))
+#define RTC_CNTL_WDT_STATE_V  0x7
+#define RTC_CNTL_WDT_STATE_S  20
+/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
+/*description: DAC_XTAL_32K*/
+#define RTC_CNTL_DAC_XTAL_32K  0x00000007
+#define RTC_CNTL_DAC_XTAL_32K_M  ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S))
+#define RTC_CNTL_DAC_XTAL_32K_V  0x7
+#define RTC_CNTL_DAC_XTAL_32K_S  17
+/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: XPD_XTAL_32K*/
+#define RTC_CNTL_XPD_XTAL_32K  (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_M  (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_V  0x1
+#define RTC_CNTL_XPD_XTAL_32K_S  16
+/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
+/*description: DRES_XTAL_32K*/
+#define RTC_CNTL_DRES_XTAL_32K  0x00000007
+#define RTC_CNTL_DRES_XTAL_32K_M  ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S))
+#define RTC_CNTL_DRES_XTAL_32K_V  0x7
+#define RTC_CNTL_DRES_XTAL_32K_S  13
+/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: xtal_32k gm control*/
+#define RTC_CNTL_DGM_XTAL_32K  0x00000007
+#define RTC_CNTL_DGM_XTAL_32K_M  ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S))
+#define RTC_CNTL_DGM_XTAL_32K_V  0x7
+#define RTC_CNTL_DGM_XTAL_32K_S  10
+/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 0: single-end buffer 1: differential buffer*/
+#define RTC_CNTL_DBUF_XTAL_32K  (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_M  (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_V  0x1
+#define RTC_CNTL_DBUF_XTAL_32K_S  9
+/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: apply an internal clock to help xtal 32k to start*/
+#define RTC_CNTL_ENCKINIT_XTAL_32K  (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_M  (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_V  0x1
+#define RTC_CNTL_ENCKINIT_XTAL_32K_S  8
+/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: Xtal 32k xpd control by sw or fsm*/
+#define RTC_CNTL_XTAL32K_XPD_FORCE  (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_M  (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_V  0x1
+#define RTC_CNTL_XTAL32K_XPD_FORCE_S  7
+/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: xtal 32k switch back xtal when xtal is restarted*/
+#define RTC_CNTL_XTAL32K_AUTO_RETURN  (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_M  (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_S  6
+/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: xtal 32k restart xtal when xtal is dead*/
+#define RTC_CNTL_XTAL32K_AUTO_RESTART  (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_M  (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_S  5
+/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: xtal 32k switch to back up clock when xtal is dead*/
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP  (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M  (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S  4
+/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: xtal 32k external xtal clock force on*/
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO  (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M  (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V  0x1
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S  3
+/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog sw reset*/
+#define RTC_CNTL_XTAL32K_WDT_RESET  (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_M  (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_RESET_S  2
+/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog clock force on*/
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO  (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M  (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S  1
+/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog enable*/
+#define RTC_CNTL_XTAL32K_WDT_EN  (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_M  (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_EN_S  0
+
+#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0064)
+/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable filter for gpio wakeup event*/
+#define RTC_CNTL_GPIO_WAKEUP_FILTER  (BIT(31))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(31))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  31
+
+#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0068)
+/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable reject for deep sleep*/
+#define RTC_CNTL_DEEP_SLP_REJECT_EN  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
+/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable reject for light sleep*/
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
+/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */
+/*description: sleep reject enable*/
+#define RTC_CNTL_SLEEP_REJECT_ENA  0x0003FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
+#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_S  12
+
+#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x006C)
+/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
+/*description: */
+#define RTC_CNTL_CPUPERIOD_SEL  0x00000003
+#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
+#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
+#define RTC_CNTL_CPUPERIOD_SEL_S  30
+/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: CPU sel option*/
+#define RTC_CNTL_CPUSEL_CONF  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_V  0x1
+#define RTC_CNTL_CPUSEL_CONF_S  29
+
+#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0070)
+/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: */
+#define RTC_CNTL_ANA_CLK_RTC_SEL  0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
+#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
+/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: fast_clk_rtc sel. 0: XTAL div 2*/
+#define RTC_CNTL_FAST_CLK_RTC_SEL  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING  (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING  (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
+/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: CK8M force power up*/
+#define RTC_CNTL_CK8M_FORCE_PU  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PU_S  26
+/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: CK8M force power down*/
+#define RTC_CNTL_CK8M_FORCE_PD  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PD_S  25
+/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */
+/*description: CK8M_DFREQ*/
+#define RTC_CNTL_CK8M_DFREQ  0x000000FF
+#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
+#define RTC_CNTL_CK8M_DFREQ_V  0xFF
+#define RTC_CNTL_CK8M_DFREQ_S  17
+/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: CK8M force no gating during sleep*/
+#define RTC_CNTL_CK8M_FORCE_NOGATING  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
+/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: XTAL force no gating during sleep*/
+#define RTC_CNTL_XTAL_FORCE_NOGATING  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
+/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: divider = reg_ck8m_div_sel + 1*/
+#define RTC_CNTL_CK8M_DIV_SEL  0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
+#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
+#define RTC_CNTL_CK8M_DIV_SEL_S  12
+/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable CK8M for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_CLK8M_EN  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_EN_S  10
+/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_CLK8M_D256_EN  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
+/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_XTAL32K_EN  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
+#define RTC_CNTL_DIG_XTAL32K_EN_S  8
+/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: 1: CK8M_D256_OUT is actually CK8M*/
+#define RTC_CNTL_ENB_CK8M_DIV  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
+#define RTC_CNTL_ENB_CK8M_DIV_S  7
+/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: disable CK8M and CK8M_D256_OUT*/
+#define RTC_CNTL_ENB_CK8M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_V  0x1
+#define RTC_CNTL_ENB_CK8M_S  6
+/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
+/*description: CK8M_D256_OUT divider. 00: div128*/
+#define RTC_CNTL_CK8M_DIV  0x00000003
+#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
+#define RTC_CNTL_CK8M_DIV_V  0x3
+#define RTC_CNTL_CK8M_DIV_S  4
+/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
+#define RTC_CNTL_CK8M_DIV_SEL_VLD  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
+/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING  (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
+/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING  (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
+
+#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0074)
+/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
+/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */
+/*description: */
+#define RTC_CNTL_ANA_CLK_DIV  0x000000FF
+#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
+#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
+#define RTC_CNTL_ANA_CLK_DIV_S  23
+/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
+#define RTC_CNTL_ANA_CLK_DIV_VLD  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
+#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
+
+#define RTC_CNTL_SDIO_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0078)
+/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_XPD_SDIO_REG  (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_M  (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_V  0x1
+#define RTC_CNTL_XPD_SDIO_REG_S  31
+/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
+/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFH_SDIO  0x00000003
+#define RTC_CNTL_DREFH_SDIO_M  ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
+#define RTC_CNTL_DREFH_SDIO_V  0x3
+#define RTC_CNTL_DREFH_SDIO_S  29
+/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */
+/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFM_SDIO  0x00000003
+#define RTC_CNTL_DREFM_SDIO_M  ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
+#define RTC_CNTL_DREFM_SDIO_V  0x3
+#define RTC_CNTL_DREFM_SDIO_S  27
+/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
+/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFL_SDIO  0x00000003
+#define RTC_CNTL_DREFL_SDIO_M  ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
+#define RTC_CNTL_DREFL_SDIO_V  0x3
+#define RTC_CNTL_DREFL_SDIO_S  25
+/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: read only register for REG1P8_READY*/
+#define RTC_CNTL_REG1P8_READY  (BIT(24))
+#define RTC_CNTL_REG1P8_READY_M  (BIT(24))
+#define RTC_CNTL_REG1P8_READY_V  0x1
+#define RTC_CNTL_REG1P8_READY_S  24
+/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_SDIO_TIEH  (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_M  (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_V  0x1
+#define RTC_CNTL_SDIO_TIEH_S  23
+/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: use SW option to control SDIO_REG*/
+#define RTC_CNTL_SDIO_FORCE  (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_M  (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_V  0x1
+#define RTC_CNTL_SDIO_FORCE_S  22
+/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
+/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
+#define RTC_CNTL_SDIO_PD_EN  (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_M  (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_V  0x1
+#define RTC_CNTL_SDIO_PD_EN_S  21
+/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: enable current limit*/
+#define RTC_CNTL_SDIO_ENCURLIM  (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_M  (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_V  0x1
+#define RTC_CNTL_SDIO_ENCURLIM_S  20
+/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: select current limit mode*/
+#define RTC_CNTL_SDIO_MODECURLIM  (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_M  (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_V  0x1
+#define RTC_CNTL_SDIO_MODECURLIM_S  19
+/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */
+/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
+#define RTC_CNTL_SDIO_DCURLIM  0x00000007
+#define RTC_CNTL_SDIO_DCURLIM_M  ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S))
+#define RTC_CNTL_SDIO_DCURLIM_V  0x7
+#define RTC_CNTL_SDIO_DCURLIM_S  16
+/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: 0 to set init[1:0]=0*/
+#define RTC_CNTL_SDIO_EN_INITI  (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_M  (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_V  0x1
+#define RTC_CNTL_SDIO_EN_INITI_S  15
+/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */
+/*description: add resistor from ldo output to ground. 0: no res*/
+#define RTC_CNTL_SDIO_INITI  0x00000003
+#define RTC_CNTL_SDIO_INITI_M  ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
+#define RTC_CNTL_SDIO_INITI_V  0x3
+#define RTC_CNTL_SDIO_INITI_S  13
+/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
+/*description: ability to prevent LDO from overshoot*/
+#define RTC_CNTL_SDIO_DCAP  0x00000003
+#define RTC_CNTL_SDIO_DCAP_M  ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S))
+#define RTC_CNTL_SDIO_DCAP_V  0x3
+#define RTC_CNTL_SDIO_DCAP_S  11
+/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */
+/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
+#define RTC_CNTL_SDIO_DTHDRV  0x00000003
+#define RTC_CNTL_SDIO_DTHDRV_M  ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S))
+#define RTC_CNTL_SDIO_DTHDRV_V  0x3
+#define RTC_CNTL_SDIO_DTHDRV_S  9
+/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
+/*description: timer count to apply reg_sdio_dcap after sdio power on*/
+#define RTC_CNTL_SDIO_TIMER_TARGET  0x000000FF
+#define RTC_CNTL_SDIO_TIMER_TARGET_M  ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S))
+#define RTC_CNTL_SDIO_TIMER_TARGET_V  0xFF
+#define RTC_CNTL_SDIO_TIMER_TARGET_S  0
+
+#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x007C)
+/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in monitor state*/
+#define RTC_CNTL_DBG_ATTEN_MONITOR  0x0000000F
+#define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
+#define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
+#define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
+/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in sleep state*/
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP  0x0000000F
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
+/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: bias_sleep when rtc in monitor state*/
+#define RTC_CNTL_BIAS_SLEEP_MONITOR  (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
+/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: bias_sleep when rtc in sleep_state*/
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP  (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
+/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in monitor state*/
+#define RTC_CNTL_PD_CUR_MONITOR  (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_V  0x1
+#define RTC_CNTL_PD_CUR_MONITOR_S  15
+/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in sleep_state*/
+#define RTC_CNTL_PD_CUR_DEEP_SLP  (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
+#define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
+/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BIAS_BUF_MONITOR  (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_BUF_MONITOR_S  13
+/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP  (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
+/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_BIAS_BUF_WAKE  (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
+#define RTC_CNTL_BIAS_BUF_WAKE_S  11
+/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BIAS_BUF_IDLE  (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
+#define RTC_CNTL_BIAS_BUF_IDLE_S  10
+/* RTC_CNTL_DG_VDD_DRV_B_SLP_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN  (BIT(8))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_M  (BIT(8))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_V  0x1
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_EN_S  8
+/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define RTC_CNTL_DG_VDD_DRV_B_SLP  0x000000FF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_S  0
+
+#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x0080)
+/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_REGULATOR_FORCE_PU  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
+/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: RTC_REG force power down (for RTC_REG power down means decrease
+ the voltage to 0.8v or lower )*/
+#define RTC_CNTL_REGULATOR_FORCE_PD  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
+/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: RTC_DBOOST force power up*/
+#define RTC_CNTL_DBOOST_FORCE_PU  (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_M  (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_V  0x1
+#define RTC_CNTL_DBOOST_FORCE_PU_S  29
+/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RTC_DBOOST force power down*/
+#define RTC_CNTL_DBOOST_FORCE_PD  (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_M  (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_V  0x1
+#define RTC_CNTL_DBOOST_FORCE_PD_S  28
+
+/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
+/*description: SCK_DCAP*/
+#define RTC_CNTL_SCK_DCAP  0x000000FF
+#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
+#define RTC_CNTL_SCK_DCAP_V  0xFF
+#define RTC_CNTL_SCK_DCAP_S  14
+#define RTC_CNTL_SCK_DCAP_DEFAULT   255
+/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DIG_CAL_EN  (BIT(7))
+#define RTC_CNTL_DIG_CAL_EN_M  (BIT(7))
+#define RTC_CNTL_DIG_CAL_EN_V  0x1
+#define RTC_CNTL_DIG_CAL_EN_S  7
+
+#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x0084)
+/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: rtc pad force hold*/
+#define RTC_CNTL_PAD_FORCE_HOLD  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_PAD_FORCE_HOLD_S  21
+
+#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x0088)
+/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_PD_EN  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
+#define RTC_CNTL_DG_WRAP_PD_EN_S  31
+/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable power down wifi in sleep*/
+#define RTC_CNTL_WIFI_PD_EN  (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_M  (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_V  0x1
+#define RTC_CNTL_WIFI_PD_EN_S  30
+/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_PD_EN  (BIT(29))
+#define RTC_CNTL_CPU_TOP_PD_EN_M  (BIT(29))
+#define RTC_CNTL_CPU_TOP_PD_EN_V  0x1
+#define RTC_CNTL_CPU_TOP_PD_EN_S  29
+/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_PD_EN  (BIT(28))
+#define RTC_CNTL_DG_PERI_PD_EN_M  (BIT(28))
+#define RTC_CNTL_DG_PERI_PD_EN_V  0x1
+#define RTC_CNTL_DG_PERI_PD_EN_S  28
+/* RTC_CNTL_BT_PD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BT_PD_EN  (BIT(27))
+#define RTC_CNTL_BT_PD_EN_M  (BIT(27))
+#define RTC_CNTL_BT_PD_EN_V  0x1
+#define RTC_CNTL_BT_PD_EN_S  27
+/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_FORCE_PU  (BIT(22))
+#define RTC_CNTL_CPU_TOP_FORCE_PU_M  (BIT(22))
+#define RTC_CNTL_CPU_TOP_FORCE_PU_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_PU_S  22
+/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_CPU_TOP_FORCE_PD  (BIT(21))
+#define RTC_CNTL_CPU_TOP_FORCE_PD_M  (BIT(21))
+#define RTC_CNTL_CPU_TOP_FORCE_PD_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_PD_S  21
+/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: digital core force power up*/
+#define RTC_CNTL_DG_WRAP_FORCE_PU  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
+/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: digital core force power down*/
+#define RTC_CNTL_DG_WRAP_FORCE_PD  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
+/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
+/*description: wifi force power up*/
+#define RTC_CNTL_WIFI_FORCE_PU  (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_M  (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_V  0x1
+#define RTC_CNTL_WIFI_FORCE_PU_S  18
+/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: wifi force power down*/
+#define RTC_CNTL_WIFI_FORCE_PD  (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_M  (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_V  0x1
+#define RTC_CNTL_WIFI_FORCE_PD_S  17
+/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_FASTMEM_FORCE_LPU  (BIT(16))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_M  (BIT(16))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPU_S  16
+/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_FASTMEM_FORCE_LPD  (BIT(15))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_M  (BIT(15))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPD_S  15
+/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_FORCE_PU  (BIT(14))
+#define RTC_CNTL_DG_PERI_FORCE_PU_M  (BIT(14))
+#define RTC_CNTL_DG_PERI_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_PU_S  14
+/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_FORCE_PD  (BIT(13))
+#define RTC_CNTL_DG_PERI_FORCE_PD_M  (BIT(13))
+#define RTC_CNTL_DG_PERI_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_PD_S  13
+/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_BT_FORCE_PU  (BIT(12))
+#define RTC_CNTL_BT_FORCE_PU_M  (BIT(12))
+#define RTC_CNTL_BT_FORCE_PU_V  0x1
+#define RTC_CNTL_BT_FORCE_PU_S  12
+/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BT_FORCE_PD  (BIT(11))
+#define RTC_CNTL_BT_FORCE_PD_M  (BIT(11))
+#define RTC_CNTL_BT_FORCE_PD_V  0x1
+#define RTC_CNTL_BT_FORCE_PD_S  11
+/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: memories in digital core force no PD in sleep*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PU  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  4
+/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: memories in digital core force PD in sleep*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PD  (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
+/* RTC_CNTL_VDD_SPI_PWR_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_VDD_SPI_PWR_FORCE  (BIT(2))
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_M  (BIT(2))
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_V  0x1
+#define RTC_CNTL_VDD_SPI_PWR_FORCE_S  2
+/* RTC_CNTL_VDD_SPI_PWR_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define RTC_CNTL_VDD_SPI_PWR_DRV  0x00000003
+#define RTC_CNTL_VDD_SPI_PWR_DRV_M  ((RTC_CNTL_VDD_SPI_PWR_DRV_V)<<(RTC_CNTL_VDD_SPI_PWR_DRV_S))
+#define RTC_CNTL_VDD_SPI_PWR_DRV_V  0x3
+#define RTC_CNTL_VDD_SPI_PWR_DRV_S  0
+
+#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x008C)
+/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force ISO*/
+#define RTC_CNTL_DG_WRAP_FORCE_ISO  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
+/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: wifi force no ISO*/
+#define RTC_CNTL_WIFI_FORCE_NOISO  (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_M  (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_V  0x1
+#define RTC_CNTL_WIFI_FORCE_NOISO_S  29
+/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: wifi force ISO*/
+#define RTC_CNTL_WIFI_FORCE_ISO  (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_M  (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_V  0x1
+#define RTC_CNTL_WIFI_FORCE_ISO_S  28
+/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: cpu force no ISO*/
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO  (BIT(27))
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M  (BIT(27))
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S  27
+/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: cpu force ISO*/
+#define RTC_CNTL_CPU_TOP_FORCE_ISO  (BIT(26))
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_M  (BIT(26))
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_S  26
+/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_FORCE_NOISO  (BIT(25))
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_M  (BIT(25))
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_S  25
+/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_DG_PERI_FORCE_ISO  (BIT(24))
+#define RTC_CNTL_DG_PERI_FORCE_ISO_M  (BIT(24))
+#define RTC_CNTL_DG_PERI_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_ISO_S  24
+/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_BT_FORCE_NOISO  (BIT(23))
+#define RTC_CNTL_BT_FORCE_NOISO_M  (BIT(23))
+#define RTC_CNTL_BT_FORCE_NOISO_V  0x1
+#define RTC_CNTL_BT_FORCE_NOISO_S  23
+/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_BT_FORCE_ISO  (BIT(22))
+#define RTC_CNTL_BT_FORCE_ISO_M  (BIT(22))
+#define RTC_CNTL_BT_FORCE_ISO_V  0x1
+#define RTC_CNTL_BT_FORCE_ISO_S  22
+/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: digital pad force hold*/
+#define RTC_CNTL_DG_PAD_FORCE_HOLD  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
+/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
+/*description: digital pad force un-hold*/
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
+/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: digital pad force ISO*/
+#define RTC_CNTL_DG_PAD_FORCE_ISO  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
+/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: digital pad force no ISO*/
+#define RTC_CNTL_DG_PAD_FORCE_NOISO  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
+/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: digital pad enable auto-hold*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
+/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: wtite only register to clear digital pad auto-hold*/
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
+/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: read only register to indicate digital pad auto-hold status*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
+/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_DIG_ISO_FORCE_ON  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
+/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_DIG_ISO_FORCE_OFF  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
+
+#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x0090)
+/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define RTC_CNTL_WDT_EN  (BIT(31))
+#define RTC_CNTL_WDT_EN_M  (BIT(31))
+#define RTC_CNTL_WDT_EN_V  0x1
+#define RTC_CNTL_WDT_EN_S  31
+/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en*/
+#define RTC_CNTL_WDT_STG0  0x00000007
+#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
+#define RTC_CNTL_WDT_STG0_V  0x7
+#define RTC_CNTL_WDT_STG0_S  28
+/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en*/
+#define RTC_CNTL_WDT_STG1  0x00000007
+#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
+#define RTC_CNTL_WDT_STG1_V  0x7
+#define RTC_CNTL_WDT_STG1_S  25
+/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en*/
+#define RTC_CNTL_WDT_STG2  0x00000007
+#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
+#define RTC_CNTL_WDT_STG2_V  0x7
+#define RTC_CNTL_WDT_STG2_S  22
+/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en*/
+#define RTC_CNTL_WDT_STG3  0x00000007
+#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
+#define RTC_CNTL_WDT_STG3_V  0x7
+#define RTC_CNTL_WDT_STG3_S  19
+/* RTC_CNTL_WDT_STGX : */
+/*description: stage action selection values */
+#define RTC_WDT_STG_SEL_OFF             0
+#define RTC_WDT_STG_SEL_INT             1
+#define RTC_WDT_STG_SEL_RESET_CPU       2
+#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
+#define RTC_WDT_STG_SEL_RESET_RTC       4
+
+/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: CPU reset counter length*/
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH  0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
+/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
+/*description: system reset counter length*/
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH  0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
+/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: enable WDT in flash boot*/
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
+/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: enable WDT reset PRO CPU*/
+#define RTC_CNTL_WDT_PROCPU_RESET_EN  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
+/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable WDT reset APP CPU*/
+#define RTC_CNTL_WDT_APPCPU_RESET_EN  (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_M  (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_S  10
+/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: pause WDT in sleep*/
+#define RTC_CNTL_WDT_PAUSE_IN_SLP  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
+/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: wdt reset whole chip enable*/
+#define RTC_CNTL_WDT_CHIP_RESET_EN  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
+/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */
+/*description: chip reset siginal pulse width*/
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH  0x000000FF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
+
+#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x0094)
+/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
+/*description: */
+#define RTC_CNTL_WDT_STG0_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
+#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x0098)
+/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
+/*description: */
+#define RTC_CNTL_WDT_STG1_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
+#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x009C)
+/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: */
+#define RTC_CNTL_WDT_STG2_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
+#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x00A0)
+/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: */
+#define RTC_CNTL_WDT_STG3_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
+#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_S  0
+
+#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0x00A4)
+/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_WDT_FEED  (BIT(31))
+#define RTC_CNTL_WDT_FEED_M  (BIT(31))
+#define RTC_CNTL_WDT_FEED_V  0x1
+#define RTC_CNTL_WDT_FEED_S  31
+
+#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x00A8)
+/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: */
+#define RTC_CNTL_WDT_WKEY  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
+#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_S  0
+
+#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00AC)
+/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: automatically feed swd when int comes*/
+#define RTC_CNTL_SWD_AUTO_FEED_EN  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
+#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
+/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: disable SWD*/
+#define RTC_CNTL_SWD_DISABLE  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_V  0x1
+#define RTC_CNTL_SWD_DISABLE_S  30
+/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Sw feed swd*/
+#define RTC_CNTL_SWD_FEED  (BIT(29))
+#define RTC_CNTL_SWD_FEED_M  (BIT(29))
+#define RTC_CNTL_SWD_FEED_V  0x1
+#define RTC_CNTL_SWD_FEED_S  29
+/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: reset swd reset flag*/
+#define RTC_CNTL_SWD_RST_FLAG_CLR  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
+#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
+/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
+/*description: adjust signal width send to swd*/
+#define RTC_CNTL_SWD_SIGNAL_WIDTH  0x000003FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
+/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SWD_BYPASS_RST  (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_V  0x1
+#define RTC_CNTL_SWD_BYPASS_RST_S  17
+/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: swd interrupt for feeding*/
+#define RTC_CNTL_SWD_FEED_INT  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_V  0x1
+#define RTC_CNTL_SWD_FEED_INT_S  1
+/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: swd reset flag*/
+#define RTC_CNTL_SWD_RESET_FLAG  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
+#define RTC_CNTL_SWD_RESET_FLAG_S  0
+
+#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x00B0)
+/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
+/*description: */
+#define RTC_CNTL_SWD_WKEY  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
+#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_S  0
+
+#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0x00B4)
+/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
+/*description: */
+#define RTC_CNTL_SW_STALL_PROCPU_C1  0x0000003F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
+/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0]*/
+#define RTC_CNTL_SW_STALL_APPCPU_C1  0x0000003F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_M  ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_S  20
+
+#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0x00B8)
+/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH4  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
+#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_S  0
+
+#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0x00BC)
+/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH5  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
+#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_S  0
+
+#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0x00C0)
+/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH6  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
+#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_S  0
+
+#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0x00C4)
+/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH7  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
+#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_S  0
+
+#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0x00C8)
+/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: rtc main state machine status*/
+#define RTC_CNTL_MAIN_STATE  0x0000000F
+#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
+#define RTC_CNTL_MAIN_STATE_V  0xF
+#define RTC_CNTL_MAIN_STATE_S  28
+/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: rtc main state machine is in idle state*/
+#define RTC_CNTL_MAIN_STATE_IN_IDLE  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
+/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: rtc main state machine is in sleep state*/
+#define RTC_CNTL_MAIN_STATE_IN_SLP  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait xtal state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait pll state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait 8m state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
+/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of low power*/
+#define RTC_CNTL_IN_LOW_POWER_STATE  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
+#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
+/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of wakeup process*/
+#define RTC_CNTL_IN_WAKEUP_STATE  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
+#define RTC_CNTL_IN_WAKEUP_STATE_S  21
+/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: rtc main state machine has been waited for some cycles*/
+#define RTC_CNTL_MAIN_STATE_WAIT_END  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
+#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
+/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: rtc is ready to receive wake up trigger from wake up source*/
+#define RTC_CNTL_RDY_FOR_WAKEUP  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
+#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
+/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc main state machine is in states that pll should be running*/
+#define RTC_CNTL_MAIN_STATE_PLL_ON  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
+#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
+/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: no use any more*/
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
+/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: ulp/cocpu is done*/
+#define RTC_CNTL_COCPU_STATE_DONE  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
+#define RTC_CNTL_COCPU_STATE_DONE_S  16
+/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: ulp/cocpu is in sleep state*/
+#define RTC_CNTL_COCPU_STATE_SLP  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
+#define RTC_CNTL_COCPU_STATE_SLP_S  15
+/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: ulp/cocpu is about to working. Switch rtc main state*/
+#define RTC_CNTL_COCPU_STATE_SWITCH  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
+#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
+/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: ulp/cocpu should start to work*/
+#define RTC_CNTL_COCPU_STATE_START  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_V  0x1
+#define RTC_CNTL_COCPU_STATE_START_S  13
+/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: touch is done*/
+#define RTC_CNTL_TOUCH_STATE_DONE  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
+#define RTC_CNTL_TOUCH_STATE_DONE_S  12
+/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: touch is in sleep state*/
+#define RTC_CNTL_TOUCH_STATE_SLP  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SLP_S  11
+/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: touch is about to working. Switch rtc main state*/
+#define RTC_CNTL_TOUCH_STATE_SWITCH  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
+/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: touch should start to work*/
+#define RTC_CNTL_TOUCH_STATE_START  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_V  0x1
+#define RTC_CNTL_TOUCH_STATE_START_S  9
+/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: digital wrap power down*/
+#define RTC_CNTL_XPD_DIG  (BIT(8))
+#define RTC_CNTL_XPD_DIG_M  (BIT(8))
+#define RTC_CNTL_XPD_DIG_V  0x1
+#define RTC_CNTL_XPD_DIG_S  8
+/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: digital wrap iso*/
+#define RTC_CNTL_DIG_ISO  (BIT(7))
+#define RTC_CNTL_DIG_ISO_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_V  0x1
+#define RTC_CNTL_DIG_ISO_S  7
+/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: wifi wrap power down*/
+#define RTC_CNTL_XPD_WIFI  (BIT(6))
+#define RTC_CNTL_XPD_WIFI_M  (BIT(6))
+#define RTC_CNTL_XPD_WIFI_V  0x1
+#define RTC_CNTL_XPD_WIFI_S  6
+/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: wifi iso*/
+#define RTC_CNTL_WIFI_ISO  (BIT(5))
+#define RTC_CNTL_WIFI_ISO_M  (BIT(5))
+#define RTC_CNTL_WIFI_ISO_V  0x1
+#define RTC_CNTL_WIFI_ISO_S  5
+/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: rtc peripheral power down*/
+#define RTC_CNTL_XPD_RTC_PERI  (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_M  (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_V  0x1
+#define RTC_CNTL_XPD_RTC_PERI_S  4
+/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: rtc peripheral iso*/
+#define RTC_CNTL_PERI_ISO  (BIT(3))
+#define RTC_CNTL_PERI_ISO_M  (BIT(3))
+#define RTC_CNTL_PERI_ISO_V  0x1
+#define RTC_CNTL_PERI_ISO_S  3
+/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: External DCDC power down*/
+#define RTC_CNTL_XPD_DIG_DCDC  (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_M  (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_V  0x1
+#define RTC_CNTL_XPD_DIG_DCDC_S  2
+/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rom0 power down*/
+#define RTC_CNTL_XPD_ROM0  (BIT(0))
+#define RTC_CNTL_XPD_ROM0_M  (BIT(0))
+#define RTC_CNTL_XPD_ROM0_V  0x1
+#define RTC_CNTL_XPD_ROM0_S  0
+
+#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0x00CC)
+/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_LOW_POWER_DIAG1  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
+#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_S  0
+
+#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0x00D0)
+/* RTC_CNTL_GPIO_PIN5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_HOLD  (BIT(5))
+#define RTC_CNTL_GPIO_PIN5_HOLD_M  (BIT(5))
+#define RTC_CNTL_GPIO_PIN5_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN5_HOLD_S  5
+/* RTC_CNTL_GPIO_PIN4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_HOLD  (BIT(4))
+#define RTC_CNTL_GPIO_PIN4_HOLD_M  (BIT(4))
+#define RTC_CNTL_GPIO_PIN4_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN4_HOLD_S  4
+/* RTC_CNTL_GPIO_PIN3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_HOLD  (BIT(3))
+#define RTC_CNTL_GPIO_PIN3_HOLD_M  (BIT(3))
+#define RTC_CNTL_GPIO_PIN3_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN3_HOLD_S  3
+/* RTC_CNTL_GPIO_PIN2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_HOLD  (BIT(2))
+#define RTC_CNTL_GPIO_PIN2_HOLD_M  (BIT(2))
+#define RTC_CNTL_GPIO_PIN2_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN2_HOLD_S  2
+/* RTC_CNTL_GPIO_PIN1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_HOLD  (BIT(1))
+#define RTC_CNTL_GPIO_PIN1_HOLD_M  (BIT(1))
+#define RTC_CNTL_GPIO_PIN1_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN1_HOLD_S  1
+/* RTC_CNTL_GPIO_PIN0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_HOLD  (BIT(0))
+#define RTC_CNTL_GPIO_PIN0_HOLD_M  (BIT(0))
+#define RTC_CNTL_GPIO_PIN0_HOLD_V  0x1
+#define RTC_CNTL_GPIO_PIN0_HOLD_S  0
+
+#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0x00D4)
+/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define RTC_CNTL_DIG_PAD_HOLD  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
+#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_S  0
+
+#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0x00D8)
+/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BROWN_OUT_DET  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_V  0x1
+#define RTC_CNTL_BROWN_OUT_DET_S  31
+/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: enable brown out*/
+#define RTC_CNTL_BROWN_OUT_ENA  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_ENA_S  30
+/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: clear brown out counter*/
+#define RTC_CNTL_BROWN_OUT_CNT_CLR  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
+/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN  (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
+/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 1:  4-pos reset*/
+#define RTC_CNTL_BROWN_OUT_RST_SEL  (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
+/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: enable brown out reset*/
+#define RTC_CNTL_BROWN_OUT_RST_ENA  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
+/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
+/*description: brown out reset wait cycles*/
+#define RTC_CNTL_BROWN_OUT_RST_WAIT  0x000003FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
+/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable power down RF when brown out happens*/
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
+/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable close flash when brown out happens*/
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
+/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */
+/*description: brown out interrupt wait cycles*/
+#define RTC_CNTL_BROWN_OUT_INT_WAIT  0x000003FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
+
+#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0x00DC)
+/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits*/
+#define RTC_CNTL_TIMER_VALUE1_LOW  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
+#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0x00E0)
+/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits*/
+#define RTC_CNTL_TIMER_VALUE1_HIGH  0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
+
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG          (DR_REG_RTCCNTL_BASE + 0x00E4)
+/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: xtal 32k watch dog backup clock factor*/
+#define RTC_CNTL_XTAL32K_CLK_FACTOR  0xFFFFFFFF
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_M  ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S))
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_V  0xFFFFFFFF
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_S  0
+
+#define RTC_CNTL_XTAL32K_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00E8)
+/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: if restarted xtal32k period is smaller than this*/
+#define RTC_CNTL_XTAL32K_STABLE_THRES  0x0000000F
+#define RTC_CNTL_XTAL32K_STABLE_THRES_M  ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S))
+#define RTC_CNTL_XTAL32K_STABLE_THRES_V  0xF
+#define RTC_CNTL_XTAL32K_STABLE_THRES_S  28
+/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
+/*description: If no clock detected for this amount of time*/
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT  0x000000FF
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M  ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S))
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V  0xFF
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S  20
+/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
+/*description: cycles to wait to repower on xtal 32k*/
+#define RTC_CNTL_XTAL32K_RESTART_WAIT  0x0000FFFF
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_M  ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S))
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_V  0xFFFF
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_S  4
+/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: cycles to wait to return normal xtal 32k*/
+#define RTC_CNTL_XTAL32K_RETURN_WAIT  0x0000000F
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_M  ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S))
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_V  0xF
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_S  0
+
+#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00EC)
+/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_IO_MUX_RESET_DISABLE  (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
+
+#define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x00F0)
+/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: sleep reject cause*/
+#define RTC_CNTL_REJECT_CAUSE  0x0003FFFF
+#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
+#define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
+#define RTC_CNTL_REJECT_CAUSE_S  0
+
+#define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0x00F4)
+/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT  (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
+
+#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x00F8)
+/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: sleep wakeup cause*/
+#define RTC_CNTL_WAKEUP_CAUSE  0x0001FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
+#define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_S  0
+
+#define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0x00FC)
+/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */
+/*description: sleep cycles for ULP-coprocessor timer*/
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE  0x00FFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
+
+#define RTC_CNTL_INT_ENA_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0x0100)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TS_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enable gitch det interrupt*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S  16
+/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt*/
+#define RTC_CNTL_SWD_INT_ENA_W1TS  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
+/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt*/
+#define RTC_CNTL_WDT_INT_ENA_W1TS  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
+
+#define RTC_CNTL_INT_ENA_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0x0104)
+/* RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_M  (BIT(20))
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BBPLL_CAL_INT_ENA_W1TC_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enable gitch det interrupt*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S  19
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S  16
+/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt*/
+#define RTC_CNTL_SWD_INT_ENA_W1TC  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
+/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt*/
+#define RTC_CNTL_WDT_INT_ENA_W1TC  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
+
+#define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0108)
+/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */
+/*description: wait cycles for rention operation*/
+#define RTC_CNTL_RETENTION_WAIT  0x0000001F
+#define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
+#define RTC_CNTL_RETENTION_WAIT_V  0x1F
+#define RTC_CNTL_RETENTION_WAIT_S  27
+/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_RETENTION_EN  (BIT(26))
+#define RTC_CNTL_RETENTION_EN_M  (BIT(26))
+#define RTC_CNTL_RETENTION_EN_V  0x1
+#define RTC_CNTL_RETENTION_EN_S  26
+/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[25:22] ;default: 4'd3 ; */
+/*description: */
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT  0x0000000F
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  22
+/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[21:19] ;default: 3'd2 ; */
+/*description: */
+#define RTC_CNTL_RETENTION_DONE_WAIT  0x00000007
+#define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
+#define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
+#define RTC_CNTL_RETENTION_DONE_WAIT_S  19
+/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_RETENTION_CLK_SEL  (BIT(18))
+#define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(18))
+#define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
+#define RTC_CNTL_RETENTION_CLK_SEL_S  18
+
+#define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x010C)
+/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: select use analog fib signal*/
+#define RTC_CNTL_FIB_SEL  0x00000007
+#define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
+#define RTC_CNTL_FIB_SEL_V  0x7
+#define RTC_CNTL_FIB_SEL_S  0
+
+#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
+#define RTC_CNTL_FIB_BOD_RST BIT(1)
+#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
+
+#define RTC_CNTL_GPIO_WAKEUP_REG          (DR_REG_RTCCNTL_BASE + 0x0110)
+/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE  (BIT(31))
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(31))
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S  31
+/* RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE  (BIT(30))
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(30))
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN1_WAKEUP_ENABLE_S  30
+/* RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE  (BIT(29))
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(29))
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN2_WAKEUP_ENABLE_S  29
+/* RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE  (BIT(28))
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(28))
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN3_WAKEUP_ENABLE_S  28
+/* RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE  (BIT(27))
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(27))
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN4_WAKEUP_ENABLE_S  27
+/* RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE  (BIT(26))
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(26))
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define RTC_CNTL_GPIO_PIN5_WAKEUP_ENABLE_S  26
+/* RTC_CNTL_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[25:23] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN0_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN0_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN0_INT_TYPE_S  23
+/* RTC_CNTL_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN1_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN1_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN1_INT_TYPE_S  20
+/* RTC_CNTL_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[19:17] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN2_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN2_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN2_INT_TYPE_S  17
+/* RTC_CNTL_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[16:14] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN3_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN3_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN3_INT_TYPE_S  14
+/* RTC_CNTL_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[13:11] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN4_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN4_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN4_INT_TYPE_S  11
+/* RTC_CNTL_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[10:8] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE  0x00000007
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_M  ((RTC_CNTL_GPIO_PIN5_INT_TYPE_V)<<(RTC_CNTL_GPIO_PIN5_INT_TYPE_S))
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_V  0x7
+#define RTC_CNTL_GPIO_PIN5_INT_TYPE_S  8
+/* RTC_CNTL_GPIO_PIN_CLK_GATE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN_CLK_GATE  (BIT(7))
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_M  (BIT(7))
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_V  0x1
+#define RTC_CNTL_GPIO_PIN_CLK_GATE_S  7
+/* RTC_CNTL_GPIO_WAKEUP_STATUS_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR  (BIT(6))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_M  (BIT(6))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_CLR_S  6
+/* RTC_CNTL_GPIO_WAKEUP_STATUS : RO ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_WAKEUP_STATUS  0x0000003F
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_M  ((RTC_CNTL_GPIO_WAKEUP_STATUS_V)<<(RTC_CNTL_GPIO_WAKEUP_STATUS_S))
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_V  0x3F
+#define RTC_CNTL_GPIO_WAKEUP_STATUS_S  0
+
+#define RTC_CNTL_DBG_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x0114)
+/* RTC_CNTL_DEBUG_SEL4 : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL4  0x0000001F
+#define RTC_CNTL_DEBUG_SEL4_M  ((RTC_CNTL_DEBUG_SEL4_V)<<(RTC_CNTL_DEBUG_SEL4_S))
+#define RTC_CNTL_DEBUG_SEL4_V  0x1F
+#define RTC_CNTL_DEBUG_SEL4_S  27
+/* RTC_CNTL_DEBUG_SEL3 : R/W ;bitpos:[26:22] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL3  0x0000001F
+#define RTC_CNTL_DEBUG_SEL3_M  ((RTC_CNTL_DEBUG_SEL3_V)<<(RTC_CNTL_DEBUG_SEL3_S))
+#define RTC_CNTL_DEBUG_SEL3_V  0x1F
+#define RTC_CNTL_DEBUG_SEL3_S  22
+/* RTC_CNTL_DEBUG_SEL2 : R/W ;bitpos:[21:17] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL2  0x0000001F
+#define RTC_CNTL_DEBUG_SEL2_M  ((RTC_CNTL_DEBUG_SEL2_V)<<(RTC_CNTL_DEBUG_SEL2_S))
+#define RTC_CNTL_DEBUG_SEL2_V  0x1F
+#define RTC_CNTL_DEBUG_SEL2_S  17
+/* RTC_CNTL_DEBUG_SEL1 : R/W ;bitpos:[16:12] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL1  0x0000001F
+#define RTC_CNTL_DEBUG_SEL1_M  ((RTC_CNTL_DEBUG_SEL1_V)<<(RTC_CNTL_DEBUG_SEL1_S))
+#define RTC_CNTL_DEBUG_SEL1_V  0x1F
+#define RTC_CNTL_DEBUG_SEL1_S  12
+/* RTC_CNTL_DEBUG_SEL0 : R/W ;bitpos:[11:7] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_SEL0  0x0000001F
+#define RTC_CNTL_DEBUG_SEL0_M  ((RTC_CNTL_DEBUG_SEL0_V)<<(RTC_CNTL_DEBUG_SEL0_S))
+#define RTC_CNTL_DEBUG_SEL0_V  0x1F
+#define RTC_CNTL_DEBUG_SEL0_S  7
+/* RTC_CNTL_DEBUG_BIT_SEL : R/W ;bitpos:[6:2] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_BIT_SEL  0x0000001F
+#define RTC_CNTL_DEBUG_BIT_SEL_M  ((RTC_CNTL_DEBUG_BIT_SEL_V)<<(RTC_CNTL_DEBUG_BIT_SEL_S))
+#define RTC_CNTL_DEBUG_BIT_SEL_V  0x1F
+#define RTC_CNTL_DEBUG_BIT_SEL_S  2
+/* RTC_CNTL_DEBUG_12M_NO_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_DEBUG_12M_NO_GATING  (BIT(1))
+#define RTC_CNTL_DEBUG_12M_NO_GATING_M  (BIT(1))
+#define RTC_CNTL_DEBUG_12M_NO_GATING_V  0x1
+#define RTC_CNTL_DEBUG_12M_NO_GATING_S  1
+
+#define RTC_CNTL_DBG_MAP_REG          (DR_REG_RTCCNTL_BASE + 0x0118)
+/* RTC_CNTL_GPIO_PIN0_FUN_SEL : R/W ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN0_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN0_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN0_FUN_SEL_S  28
+/* RTC_CNTL_GPIO_PIN1_FUN_SEL : R/W ;bitpos:[27:24] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN1_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN1_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN1_FUN_SEL_S  24
+/* RTC_CNTL_GPIO_PIN2_FUN_SEL : R/W ;bitpos:[23:20] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN2_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN2_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN2_FUN_SEL_S  20
+/* RTC_CNTL_GPIO_PIN3_FUN_SEL : R/W ;bitpos:[19:16] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN3_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN3_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN3_FUN_SEL_S  16
+/* RTC_CNTL_GPIO_PIN4_FUN_SEL : R/W ;bitpos:[15:12] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN4_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN4_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN4_FUN_SEL_S  12
+/* RTC_CNTL_GPIO_PIN5_FUN_SEL : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL  0x0000000F
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_M  ((RTC_CNTL_GPIO_PIN5_FUN_SEL_V)<<(RTC_CNTL_GPIO_PIN5_FUN_SEL_S))
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_V  0xF
+#define RTC_CNTL_GPIO_PIN5_FUN_SEL_S  8
+/* RTC_CNTL_GPIO_PIN0_MUX_SEL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL  (BIT(7))
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_M  (BIT(7))
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN0_MUX_SEL_S  7
+/* RTC_CNTL_GPIO_PIN1_MUX_SEL : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL  (BIT(6))
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_M  (BIT(6))
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN1_MUX_SEL_S  6
+/* RTC_CNTL_GPIO_PIN2_MUX_SEL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL  (BIT(5))
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_M  (BIT(5))
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN2_MUX_SEL_S  5
+/* RTC_CNTL_GPIO_PIN3_MUX_SEL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL  (BIT(4))
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_M  (BIT(4))
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN3_MUX_SEL_S  4
+/* RTC_CNTL_GPIO_PIN4_MUX_SEL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL  (BIT(3))
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_M  (BIT(3))
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN4_MUX_SEL_S  3
+/* RTC_CNTL_GPIO_PIN5_MUX_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL  (BIT(2))
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_M  (BIT(2))
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_V  0x1
+#define RTC_CNTL_GPIO_PIN5_MUX_SEL_S  2
+
+#define RTC_CNTL_SENSOR_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x011C)
+/* RTC_CNTL_FORCE_XPD_SAR : R/W ;bitpos:[31:30] ;default: 2'b0 ; */
+/*description: */
+#define RTC_CNTL_FORCE_XPD_SAR  0x00000003
+#define RTC_CNTL_FORCE_XPD_SAR_M  ((RTC_CNTL_FORCE_XPD_SAR_V)<<(RTC_CNTL_FORCE_XPD_SAR_S))
+#define RTC_CNTL_FORCE_XPD_SAR_V  0x3
+#define RTC_CNTL_FORCE_XPD_SAR_S  30
+/* RTC_CNTL_SAR2_PWDET_CCT : R/W ;bitpos:[29:27] ;default: 3'd0 ; */
+/*description: */
+#define RTC_CNTL_SAR2_PWDET_CCT  0x00000007
+#define RTC_CNTL_SAR2_PWDET_CCT_M  ((RTC_CNTL_SAR2_PWDET_CCT_V)<<(RTC_CNTL_SAR2_PWDET_CCT_S))
+#define RTC_CNTL_SAR2_PWDET_CCT_V  0x7
+#define RTC_CNTL_SAR2_PWDET_CCT_S  27
+
+#define RTC_CNTL_DBG_SAR_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x0120)
+/* RTC_CNTL_SAR_DEBUG_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: */
+#define RTC_CNTL_SAR_DEBUG_SEL  0x0000001F
+#define RTC_CNTL_SAR_DEBUG_SEL_M  ((RTC_CNTL_SAR_DEBUG_SEL_V)<<(RTC_CNTL_SAR_DEBUG_SEL_S))
+#define RTC_CNTL_SAR_DEBUG_SEL_V  0x1F
+#define RTC_CNTL_SAR_DEBUG_SEL_S  27
+
+#define RTC_CNTL_PG_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0124)
+/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_EN  (BIT(31))
+#define RTC_CNTL_POWER_GLITCH_EN_M  (BIT(31))
+#define RTC_CNTL_POWER_GLITCH_EN_V  0x1
+#define RTC_CNTL_POWER_GLITCH_EN_S  31
+/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL  (BIT(30))
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M  (BIT(30))
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V  0x1
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S  30
+/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU  (BIT(29))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M  (BIT(29))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V  0x1
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S  29
+/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD  (BIT(28))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M  (BIT(28))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V  0x1
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S  28
+/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */
+/*description: */
+#define RTC_CNTL_POWER_GLITCH_DSENSE  0x00000003
+#define RTC_CNTL_POWER_GLITCH_DSENSE_M  ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S))
+#define RTC_CNTL_POWER_GLITCH_DSENSE_V  0x3
+#define RTC_CNTL_POWER_GLITCH_DSENSE_S  26
+
+#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x01fc)
+/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007270 ; */
+/*description: */
+#define RTC_CNTL_CNTL_DATE  0x0FFFFFFF
+#define RTC_CNTL_CNTL_DATE_M  ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S))
+#define RTC_CNTL_CNTL_DATE_V  0xFFFFFFF
+#define RTC_CNTL_CNTL_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_CNTL_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/rtc_cntl_struct.h b/components/soc/esp32c3/register/soc/rtc_cntl_struct.h
new file mode 100644
index 00000000000..5c57701f695
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/rtc_cntl_struct.h
@@ -0,0 +1,834 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct rtc_cntl_dev_s {
+    union {
+        struct {
+            uint32_t sw_stall_appcpu_c0:  2;               /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
+            uint32_t sw_stall_procpu_c0:  2;               /*{reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
+            uint32_t sw_appcpu_rst:       1;               /*APP CPU SW reset*/
+            uint32_t sw_procpu_rst:       1;               /*PRO CPU SW reset*/
+            uint32_t bb_i2c_force_pd:     1;               /*BB_I2C force power down*/
+            uint32_t bb_i2c_force_pu:     1;               /*BB_I2C force power up*/
+            uint32_t bbpll_i2c_force_pd:  1;               /*BB_PLL _I2C force power down*/
+            uint32_t bbpll_i2c_force_pu:  1;               /*BB_PLL_I2C force power up*/
+            uint32_t bbpll_force_pd:      1;               /*BB_PLL force power down*/
+            uint32_t bbpll_force_pu:      1;               /*BB_PLL force power up*/
+            uint32_t xtl_force_pd:        1;               /*crystall force power down*/
+            uint32_t xtl_force_pu:        1;               /*crystall force power up*/
+            uint32_t xtl_en_wait:         4;               /*wait bias_sleep and current source wakeup*/
+            uint32_t reserved18:          2;
+            uint32_t ctr_sel:             3;
+            uint32_t xtl_force_iso:       1;
+            uint32_t pll_force_iso:       1;
+            uint32_t analog_force_iso:    1;
+            uint32_t xtl_force_noiso:     1;
+            uint32_t pll_force_noiso:     1;
+            uint32_t analog_force_noiso:  1;
+            uint32_t dg_wrap_force_rst:   1;               /*digital wrap force reset in deep sleep*/
+            uint32_t dg_wrap_force_norst: 1;               /*digital core force no reset in deep sleep*/
+            uint32_t sw_sys_rst:          1;               /*SW system reset*/
+        };
+        uint32_t val;
+    } options0;
+    uint32_t slp_timer0;                               /**/
+    union {
+        struct {
+            uint32_t slp_val_hi:             16;           /*RTC sleep timer high 16 bits*/
+            uint32_t main_timer_alarm_en:     1;           /*timer alarm enable bit*/
+            uint32_t reserved17:             15;
+        };
+        uint32_t val;
+    } slp_timer1;
+    union {
+        struct {
+            uint32_t reserved0:      27;
+            uint32_t timer_sys_stall: 1;                   /*Enable to record system stall time*/
+            uint32_t timer_xtl_off:   1;                   /*Enable to record 40M XTAL OFF time*/
+            uint32_t timer_sys_rst:   1;                   /*enable to record system reset time*/
+            uint32_t reserved30:      1;
+            uint32_t update:          1;                   /*Set 1: to update register with RTC timer*/
+        };
+        uint32_t val;
+    } time_update;
+    uint32_t time_low0;                                /*RTC timer low 32 bits*/
+    union {
+        struct {
+            uint32_t rtc_timer_value0_high:16;             /*RTC timer high 16 bits*/
+            uint32_t reserved16:           16;
+        };
+        uint32_t val;
+    } time_high0;
+    union {
+        struct {
+            uint32_t rtc_sw_cpu_int:           1;          /*rtc software interrupt to main cpu*/
+            uint32_t rtc_slp_reject_cause_clr: 1;          /*clear rtc sleep reject cause*/
+            uint32_t reserved2:               20;
+            uint32_t apb2rtc_bridge_sel:       1;          /*1: APB to RTC using bridge*/
+            uint32_t reserved23:               5;
+            uint32_t sdio_active_ind:          1;          /*SDIO active indication*/
+            uint32_t slp_wakeup:               1;          /*leep wakeup bit*/
+            uint32_t slp_reject:               1;          /*leep reject bit*/
+            uint32_t sleep_en:                 1;          /*sleep enable bit*/
+        };
+        uint32_t val;
+    } state0;
+    union {
+        struct {
+            uint32_t cpu_stall_en:   1;                    /*CPU stall enable bit*/
+            uint32_t cpu_stall_wait: 5;                    /*CPU stall wait cycles in fast_clk_rtc*/
+            uint32_t ck8m_wait:      8;                    /*CK8M wait cycles in slow_clk_rtc*/
+            uint32_t xtl_buf_wait:  10;                    /*XTAL wait cycles in slow_clk_rtc*/
+            uint32_t pll_buf_wait:   8;                    /*PLL wait cycles in slow_clk_rtc*/
+        };
+        uint32_t val;
+    } timer1;
+    union {
+        struct {
+            uint32_t reserved0:        24;
+            uint32_t min_time_ck8m_off: 8;                 /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
+        };
+        uint32_t val;
+    } timer2;
+    union {
+        struct {
+            uint32_t wifi_wait_timer:    9;
+            uint32_t wifi_powerup_timer: 7;
+            uint32_t bt_wait_timer:      9;
+            uint32_t bt_powerup_timer:   7;
+        };
+        uint32_t val;
+    } timer3;
+    union {
+        struct {
+            uint32_t cpu_top_wait_timer:    9;
+            uint32_t cpu_top_powerup_timer: 7;
+            uint32_t dg_wrap_wait_timer:    9;
+            uint32_t dg_wrap_powerup_timer: 7;
+        };
+        uint32_t val;
+    } timer4;
+    union {
+        struct {
+            uint32_t reserved0:   8;
+            uint32_t min_slp_val: 8;                       /*minimal sleep cycles in slow_clk_rtc*/
+            uint32_t reserved16: 16;
+        };
+        uint32_t val;
+    } timer5;
+    union {
+        struct {
+            uint32_t reserved0:            16;
+            uint32_t dg_peri_wait_timer:    9;
+            uint32_t dg_peri_powerup_timer: 7;
+        };
+        uint32_t val;
+    } timer6;
+    union {
+        struct {
+            uint32_t reserved0:             18;
+            uint32_t i2c_reset_por_force_pd: 1;
+            uint32_t i2c_reset_por_force_pu: 1;
+            uint32_t glitch_rst_en:          1;
+            uint32_t reserved21:             1;            /*PLLA force power down*/
+            uint32_t sar_i2c_pu:             1;            /*PLLA force power up*/
+            uint32_t plla_force_pd:          1;            /*PLLA force power down*/
+            uint32_t plla_force_pu:          1;            /*PLLA force power up*/
+            uint32_t bbpll_cal_slp_start:    1;            /*start BBPLL calibration during sleep*/
+            uint32_t pvtmon_pu:              1;            /*1: PVTMON power up*/
+            uint32_t txrf_i2c_pu:            1;            /*1: TXRF_I2C power up*/
+            uint32_t rfrx_pbus_pu:           1;            /*1: RFRX_PBUS power up*/
+            uint32_t reserved29:             1;
+            uint32_t ckgen_i2c_pu:           1;            /*1: CKGEN_I2C power up*/
+            uint32_t pll_i2c_pu:             1;
+        };
+        uint32_t val;
+    } ana_conf;
+    union {
+        struct {
+            uint32_t reset_cause_procpu:         6;        /*reset cause of PRO CPU*/
+            uint32_t reset_cause_appcpu:         6;        /*reset cause of APP CPU*/
+            uint32_t stat_vector_sel_appcpu:     1;        /*APP CPU state vector sel*/
+            uint32_t stat_vector_sel_procpu:     1;        /*PRO CPU state vector sel*/
+            uint32_t all_reset_flag_procpu:      1;        /*PRO CPU reset_flag*/
+            uint32_t all_reset_flag_appcpu:      1;        /*APP CPU reset flag*/
+            uint32_t all_reset_flag_clr_procpu:  1;        /*clear PRO CPU reset_flag*/
+            uint32_t all_reset_flag_clr_appcpu:  1;        /*clear APP CPU reset flag*/
+            uint32_t ocd_halt_on_reset_appcpu:   1;        /*APPCPU OcdHaltOnReset*/
+            uint32_t ocd_halt_on_reset_procpu:   1;        /*PROCPU OcdHaltOnReset*/
+            uint32_t jtag_reset_flag_procpu:     1;
+            uint32_t jtag_reset_flag_appcpu:     1;
+            uint32_t jtag_reset_flag_clr_procpu: 1;
+            uint32_t jtag_reset_flag_clr_appcpu: 1;
+            uint32_t rtc_dreset_mask_appcpu:     1;
+            uint32_t rtc_dreset_mask_procpu:     1;
+            uint32_t reserved26:                 6;
+        };
+        uint32_t val;
+    } reset_state;
+    union {
+        struct {
+            uint32_t reserved0:     15;
+            uint32_t rtc_wakeup_ena:17;                    /*wakeup enable bitmap*/
+        };
+        uint32_t val;
+    } wakeup_state;
+    union {
+        struct {
+            uint32_t slp_wakeup:               1;          /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject:               1;          /*enable sleep reject interrupt*/
+            uint32_t reserved2:                1;          /*enable SDIO idle interrupt*/
+            uint32_t rtc_wdt:                  1;          /*enable RTC WDT interrupt*/
+            uint32_t reserved4:                5;
+            uint32_t rtc_brown_out:            1;          /*enable brown out interrupt*/
+            uint32_t rtc_main_timer:           1;          /*enable RTC main timer interrupt*/
+            uint32_t reserved11:               4;          /*enable saradc2 interrupt*/
+            uint32_t rtc_swd:                  1;          /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead:         1;          /*enable xtal32k_dead  interrupt*/
+            uint32_t reserved17:               2;          /*enable touch timeout interrupt*/
+            uint32_t rtc_glitch_det:           1;          /*enable gitch det interrupt*/
+            uint32_t rtc_bbpll_cal:            1;
+            uint32_t reserved21:              11;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t slp_wakeup:               1;          /*sleep wakeup interrupt raw*/
+            uint32_t slp_reject:               1;          /*sleep reject interrupt raw*/
+            uint32_t reserved2:                1;          /*SDIO idle interrupt raw*/
+            uint32_t rtc_wdt:                  1;          /*RTC WDT interrupt raw*/
+            uint32_t reserved4:                5;          /*touch inactive interrupt raw*/
+            uint32_t rtc_brown_out:            1;          /*brown out interrupt raw*/
+            uint32_t rtc_main_timer:           1;          /*RTC main timer interrupt raw*/
+            uint32_t reserved11:               4;          /*saradc2 interrupt raw*/
+            uint32_t rtc_swd:                  1;          /*super watch dog interrupt raw*/
+            uint32_t rtc_xtal32k_dead:         1;          /*xtal32k dead detection interrupt raw*/
+            uint32_t reserved17:               2;          /*touch timeout interrupt raw*/
+            uint32_t rtc_glitch_det:           1;          /*glitch_det_interrupt_raw*/
+            uint32_t rtc_bbpll_cal:            1;
+            uint32_t reserved21:              11;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slp_wakeup:              1;           /*sleep wakeup interrupt state*/
+            uint32_t slp_reject:              1;           /*sleep reject interrupt state*/
+            uint32_t reserved2:               1;
+            uint32_t rtc_wdt:                 1;           /*RTC WDT interrupt state*/
+            uint32_t reserved4:               5;
+            uint32_t rtc_brown_out:           1;           /*brown out interrupt state*/
+            uint32_t rtc_main_timer:          1;           /*RTC main timer interrupt state*/
+            uint32_t reserved11:              4;
+            uint32_t rtc_swd:                 1;           /*super watch dog interrupt state*/
+            uint32_t rtc_xtal32k_dead:        1;           /*xtal32k dead detection interrupt state*/
+            uint32_t reserved17:              2;
+            uint32_t rtc_glitch_det:          1;           /*glitch_det_interrupt state*/
+            uint32_t rtc_bbpll_cal:           1;
+            uint32_t reserved21:             11;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slp_wakeup:               1;          /*Clear sleep wakeup interrupt state*/
+            uint32_t slp_reject:               1;          /*Clear sleep reject interrupt state*/
+            uint32_t reserved2:                1;
+            uint32_t rtc_wdt:                  1;          /*Clear RTC WDT interrupt state*/
+            uint32_t reserved4:                5;
+            uint32_t rtc_brown_out:            1;          /*Clear brown out interrupt state*/
+            uint32_t rtc_main_timer:           1;          /*Clear RTC main timer interrupt state*/
+            uint32_t reserved11:               4;
+            uint32_t rtc_swd:                  1;          /*Clear super watch dog interrupt state*/
+            uint32_t rtc_xtal32k_dead:         1;          /*Clear RTC WDT interrupt state*/
+            uint32_t reserved17:               2;
+            uint32_t rtc_glitch_det:           1;          /*Clear glitch det interrupt state*/
+            uint32_t rtc_bbpll_cal:            1;
+            uint32_t reserved21:              11;
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t store[4];                                   /**/
+    union {
+        struct {
+            uint32_t xtal32k_wdt_en:       1;              /*xtal 32k watch dog enable*/
+            uint32_t xtal32k_wdt_clk_fo:   1;              /*xtal 32k watch dog clock force on*/
+            uint32_t xtal32k_wdt_reset:    1;              /*xtal 32k watch dog sw reset*/
+            uint32_t xtal32k_ext_clk_fo:   1;              /*xtal 32k external xtal clock force on*/
+            uint32_t xtal32k_auto_backup:  1;              /*xtal 32k switch to back up clock when xtal is dead*/
+            uint32_t xtal32k_auto_restart: 1;              /*xtal 32k restart xtal when xtal is dead*/
+            uint32_t xtal32k_auto_return:  1;              /*xtal 32k switch back xtal when xtal is restarted*/
+            uint32_t xtal32k_xpd_force:    1;              /*Xtal 32k xpd control by sw or fsm*/
+            uint32_t enckinit_xtal_32k:    1;              /*apply an internal clock to help xtal 32k to start*/
+            uint32_t dbuf_xtal_32k:        1;              /*0: single-end buffer 1: differential buffer*/
+            uint32_t dgm_xtal_32k:         3;              /*xtal_32k gm control*/
+            uint32_t dres_xtal_32k:        3;              /*DRES_XTAL_32K*/
+            uint32_t xpd_xtal_32k:         1;              /*XPD_XTAL_32K*/
+            uint32_t dac_xtal_32k:         3;              /*DAC_XTAL_32K*/
+            uint32_t rtc_wdt_state:        3;              /*state of 32k_wdt*/
+            uint32_t rtc_xtal32k_gpio_sel: 1;              /*XTAL_32K sel. 0: external XTAL_32K*/
+            uint32_t reserved24:           6;
+            uint32_t ctr_lv:               1;              /*0: power down XTAL at high level*/
+            uint32_t ctr_en:               1;
+        };
+        uint32_t val;
+    } ext_xtl_conf;
+    union {
+        struct {
+            uint32_t reserved0:         31;
+            uint32_t gpio_wakeup_filter: 1;                /*enable filter for gpio wakeup event*/
+        };
+        uint32_t val;
+    } ext_wakeup_conf;
+    union {
+        struct {
+            uint32_t reserved0:           12;
+            uint32_t rtc_sleep_reject_ena:18;              /*sleep reject enable*/
+            uint32_t light_slp_reject_en:  1;              /*enable reject for light sleep*/
+            uint32_t deep_slp_reject_en:   1;              /*enable reject for deep sleep*/
+        };
+        uint32_t val;
+    } slp_reject_conf;
+    union {
+        struct {
+            uint32_t reserved0:        29;
+            uint32_t cpusel_conf:       1;                 /*CPU sel option*/
+            uint32_t cpuperiod_sel:     2;
+        };
+        uint32_t val;
+    } cpu_period_conf;
+    union {
+        struct {
+            uint32_t reserved0:                  1;
+            uint32_t efuse_clk_force_gating:     1;
+            uint32_t efuse_clk_force_nogating:   1;
+            uint32_t ck8m_div_sel_vld:           1;        /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
+            uint32_t ck8m_div:                   2;        /*CK8M_D256_OUT divider. 00: div128*/
+            uint32_t enb_ck8m:                   1;        /*disable CK8M and CK8M_D256_OUT*/
+            uint32_t enb_ck8m_div:               1;        /*1: CK8M_D256_OUT is actually CK8M*/
+            uint32_t dig_xtal32k_en:             1;        /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_d256_en:          1;        /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_en:               1;        /*enable CK8M for digital core (no relationship with RTC core)*/
+            uint32_t reserved11:                 1;
+            uint32_t ck8m_div_sel:               3;        /*divider = reg_ck8m_div_sel + 1*/
+            uint32_t xtal_force_nogating:        1;        /*XTAL force no gating during sleep*/
+            uint32_t ck8m_force_nogating:        1;        /*CK8M force no gating during sleep*/
+            uint32_t ck8m_dfreq:                 8;        /*CK8M_DFREQ*/
+            uint32_t ck8m_force_pd:              1;        /*CK8M force power down*/
+            uint32_t ck8m_force_pu:              1;        /*CK8M force power up*/
+            uint32_t xtal_global_force_gating:   1;
+            uint32_t xtal_global_force_nogating: 1;
+            uint32_t fast_clk_rtc_sel:           1;        /*fast_clk_rtc sel. 0: XTAL div 2*/
+            uint32_t ana_clk_rtc_sel:            2;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t reserved0:             22;
+            uint32_t rtc_ana_clk_div_vld:    1;            /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
+            uint32_t rtc_ana_clk_div:        8;
+            uint32_t slow_clk_next_edge:     1;
+        };
+        uint32_t val;
+    } slow_clk_conf;
+    union {
+        struct {
+            uint32_t sdio_timer_target: 8;                 /*timer count to apply reg_sdio_dcap after sdio power on*/
+            uint32_t reserved8:         1;
+            uint32_t sdio_dthdrv:       2;                 /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
+            uint32_t sdio_dcap:         2;                 /*ability to prevent LDO from overshoot*/
+            uint32_t sdio_initi:        2;                 /*add resistor from ldo output to ground. 0: no res*/
+            uint32_t sdio_en_initi:     1;                 /*0 to set init[1:0]=0*/
+            uint32_t sdio_dcurlim:      3;                 /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
+            uint32_t sdio_modecurlim:   1;                 /*select current limit mode*/
+            uint32_t sdio_encurlim:     1;                 /*enable current limit*/
+            uint32_t sdio_pd_en:        1;                 /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
+            uint32_t sdio_force:        1;                 /*1: use SW option to control SDIO_REG*/
+            uint32_t sdio_tieh:         1;                 /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
+            uint32_t reg1p8_ready:      1;                 /*read only register for REG1P8_READY*/
+            uint32_t drefl_sdio:        2;                 /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t drefm_sdio:        2;                 /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t drefh_sdio:        2;                 /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t xpd_sdio:          1;
+        };
+        uint32_t val;
+    } sdio_conf;
+    union {
+        struct {
+            uint32_t dg_vdd_drv_b_slp:    8;
+            uint32_t dg_vdd_drv_b_slp_en: 1;
+            uint32_t reserved9:           1;
+            uint32_t bias_buf_idle:       1;
+            uint32_t bias_buf_wake:       1;
+            uint32_t bias_buf_deep_slp:   1;
+            uint32_t bias_buf_monitor:    1;
+            uint32_t pd_cur_deep_slp:     1;               /*xpd cur when rtc in sleep_state*/
+            uint32_t pd_cur_monitor:      1;               /*xpd cur when rtc in monitor state*/
+            uint32_t bias_sleep_deep_slp: 1;               /*bias_sleep when rtc in sleep_state*/
+            uint32_t bias_sleep_monitor:  1;               /*bias_sleep when rtc in monitor state*/
+            uint32_t dbg_atten_deep_slp:  4;               /*DBG_ATTEN when rtc in sleep state*/
+            uint32_t dbg_atten_monitor:   4;               /*DBG_ATTEN when rtc in monitor state*/
+            uint32_t reserved26:          6;
+        };
+        uint32_t val;
+    } bias_conf;
+    union {
+        struct {
+            uint32_t reserved0:           7;
+            uint32_t dig_cal_en:          1;
+            uint32_t reserved8:           6;
+            uint32_t sck_dcap:            8;               /*SCK_DCAP*/
+            uint32_t reserved22:          6;
+            uint32_t rtc_dboost_force_pd: 1;               /*RTC_DBOOST force power down*/
+            uint32_t rtc_dboost_force_pu: 1;               /*RTC_DBOOST force power up*/
+            uint32_t rtculator_force_pd:  1;               /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
+            uint32_t rtculator_force_pu:  1;
+        };
+        uint32_t val;
+    } rtc;
+    union {
+        struct {
+            uint32_t reserved0:         21;
+            uint32_t rtc_pad_force_hold: 1;                /*rtc pad force hold*/
+            uint32_t reserved22:        10;
+        };
+        uint32_t val;
+    } rtc_pwc;
+    union {
+        struct {
+            uint32_t vdd_spi_pwr_drv:       2;
+            uint32_t vdd_spi_pwr_force:     1;
+            uint32_t lslp_mem_force_pd:     1;             /*memories in digital core force PD in sleep*/
+            uint32_t lslp_mem_force_pu:     1;             /*memories in digital core force no PD in sleep*/
+            uint32_t reserved5:             6;
+            uint32_t bt_force_pd:           1;
+            uint32_t bt_force_pu:           1;
+            uint32_t dg_peri_force_pd:      1;
+            uint32_t dg_peri_force_pu:      1;
+            uint32_t fastmem_force_lpd:     1;
+            uint32_t fastmem_force_lpu:     1;
+            uint32_t wifi_force_pd:         1;             /*wifi force power down*/
+            uint32_t wifi_force_pu:         1;             /*wifi force power up*/
+            uint32_t dg_wrap_force_pd:      1;             /*digital core force power down*/
+            uint32_t dg_wrap_force_pu:      1;             /*digital core force power up*/
+            uint32_t cpu_top_force_pd:      1;
+            uint32_t cpu_top_force_pu:      1;
+            uint32_t reserved23:            4;
+            uint32_t bt_pd_en:              1;
+            uint32_t dg_peri_pd_en:         1;
+            uint32_t cpu_top_pd_en:         1;
+            uint32_t wifi_pd_en:            1;             /*enable power down wifi in sleep*/
+            uint32_t dg_wrap_pd_en:         1;
+        };
+        uint32_t val;
+    } dig_pwc;
+    union {
+        struct {
+            uint32_t reserved0:           7;
+            uint32_t dig_iso_force_off:   1;
+            uint32_t dig_iso_force_on:    1;
+            uint32_t dg_pad_autohold:     1;               /*read only register to indicate digital pad auto-hold status*/
+            uint32_t clr_dg_pad_autohold: 1;               /*wtite only register to clear digital pad auto-hold*/
+            uint32_t dg_pad_autohold_en:  1;               /*digital pad enable auto-hold*/
+            uint32_t dg_pad_force_noiso:  1;               /*digital pad force no ISO*/
+            uint32_t dg_pad_force_iso:    1;               /*digital pad force ISO*/
+            uint32_t dg_pad_force_unhold: 1;               /*digital pad force un-hold*/
+            uint32_t dg_pad_force_hold:   1;               /*digital pad force hold*/
+            uint32_t reserved16:          6;
+            uint32_t bt_force_iso:        1;
+            uint32_t bt_force_noiso:      1;
+            uint32_t dg_peri_force_iso:   1;
+            uint32_t dg_peri_force_noiso: 1;
+            uint32_t cpu_top_force_iso:   1;               /*cpu force ISO*/
+            uint32_t cpu_top_force_noiso: 1;               /*cpu force no ISO*/
+            uint32_t wifi_force_iso:      1;               /*wifi force ISO*/
+            uint32_t wifi_force_noiso:    1;               /*wifi force no ISO*/
+            uint32_t dg_wrap_force_iso:   1;               /*digital core force ISO*/
+            uint32_t dg_wrap_force_noiso: 1;
+        };
+        uint32_t val;
+    } dig_iso;
+    union {
+        struct {
+            uint32_t chip_reset_width:     8;              /*chip reset siginal pulse width*/
+            uint32_t chip_reset_en:        1;              /*wdt reset whole chip enable*/
+            uint32_t pause_in_slp:         1;              /*pause WDT in sleep*/
+            uint32_t appcpu_reset_en:      1;              /*enable WDT reset APP CPU*/
+            uint32_t procpu_reset_en:      1;              /*enable WDT reset PRO CPU*/
+            uint32_t flashboot_mod_en:     1;              /*enable WDT in flash boot*/
+            uint32_t sys_reset_length:     3;              /*system reset counter length*/
+            uint32_t cpu_reset_length:     3;              /*CPU reset counter length*/
+            uint32_t stg3:                 3;              /*1: interrupt stage en*/
+            uint32_t stg2:                 3;              /*1: interrupt stage en*/
+            uint32_t stg1:                 3;              /*1: interrupt stage en*/
+            uint32_t stg0:                 3;              /*1: interrupt stage en*/
+            uint32_t en:                   1;
+        };
+        uint32_t val;
+    } wdt_config0;
+    uint32_t wdt_config1;                               /**/
+    uint32_t wdt_config2;                               /**/
+    uint32_t wdt_config3;                               /**/
+    uint32_t wdt_config4;                               /**/
+    union {
+        struct {
+            uint32_t reserved0:   31;
+            uint32_t feed:         1;
+        };
+        uint32_t val;
+    } wdt_feed;
+    uint32_t wdt_wprotect;                              /**/
+    union {
+        struct {
+            uint32_t swd_reset_flag:   1;                  /*swd reset flag*/
+            uint32_t swd_feed_int:     1;                  /*swd interrupt for feeding*/
+            uint32_t reserved2:       15;
+            uint32_t swd_bypass_rst:   1;
+            uint32_t swd_signal_width:10;                  /*adjust signal width send to swd*/
+            uint32_t swd_rst_flag_clr: 1;                  /*reset swd reset flag*/
+            uint32_t swd_feed:         1;                  /*Sw feed swd*/
+            uint32_t swd_disable:      1;                  /*disable SWD*/
+            uint32_t swd_auto_feed_en: 1;                  /*automatically feed swd when int comes*/
+        };
+        uint32_t val;
+    } swd_conf;
+    uint32_t swd_wprotect;                             /**/
+    union {
+        struct {
+            uint32_t reserved0:         20;
+            uint32_t appcpu_c1:          6;                /*{reg_sw_stall_appcpu_c1[5:0]*/
+            uint32_t procpu_c1:          6;
+        };
+        uint32_t val;
+    } sw_cpu_stall;
+    uint32_t store4;                                   /**/
+    uint32_t store5;                                   /**/
+    uint32_t store6;                                   /**/
+    uint32_t store7;                                   /**/
+    union {
+        struct {
+            uint32_t xpd_rom0:                   1;        /*rom0 power down*/
+            uint32_t reserved1:                  1;
+            uint32_t xpd_dig_dcdc:               1;        /*External DCDC power down*/
+            uint32_t rtc_peri_iso:               1;        /*rtc peripheral iso*/
+            uint32_t xpd_rtc_peri:               1;        /*rtc peripheral power down*/
+            uint32_t wifi_iso:                   1;        /*wifi iso*/
+            uint32_t xpd_wifi:                   1;        /*wifi wrap power down*/
+            uint32_t dig_iso:                    1;        /*digital wrap iso*/
+            uint32_t xpd_dig:                    1;        /*digital wrap power down*/
+            uint32_t rtc_touch_state_start:      1;        /*touch should start to work*/
+            uint32_t rtc_touch_state_switch:     1;        /*touch is about to working. Switch rtc main state*/
+            uint32_t rtc_touch_state_slp:        1;        /*touch is in sleep state*/
+            uint32_t rtc_touch_state_done:       1;        /*touch is done*/
+            uint32_t rtc_cocpu_state_start:      1;        /*ulp/cocpu should start to work*/
+            uint32_t rtc_cocpu_state_switch:     1;        /*ulp/cocpu is about to working. Switch rtc main state*/
+            uint32_t rtc_cocpu_state_slp:        1;        /*ulp/cocpu is in sleep state*/
+            uint32_t rtc_cocpu_state_done:       1;        /*ulp/cocpu is done*/
+            uint32_t rtc_main_state_xtal_iso:    1;        /*no use any more*/
+            uint32_t rtc_main_state_pll_on:      1;        /*rtc main state machine is in states that pll should be running*/
+            uint32_t rtc_rdy_for_wakeup:         1;        /*rtc is ready to receive wake up trigger from wake up source*/
+            uint32_t rtc_main_state_wait_end:    1;        /*rtc main state machine has been waited for some cycles*/
+            uint32_t rtc_in_wakeup_state:        1;        /*rtc main state machine is in the states of wakeup process*/
+            uint32_t rtc_in_low_power_state:     1;        /*rtc main state machine is in the states of low power*/
+            uint32_t rtc_main_state_in_wait_8m:  1;        /*rtc main state machine is in wait 8m state*/
+            uint32_t rtc_main_state_in_wait_pll: 1;        /*rtc main state machine is in wait pll state*/
+            uint32_t rtc_main_state_in_wait_xtl: 1;        /*rtc main state machine is in wait xtal state*/
+            uint32_t rtc_main_state_in_slp:      1;        /*rtc main state machine is in sleep state*/
+            uint32_t rtc_main_state_in_idle:     1;        /*rtc main state machine is in idle state*/
+            uint32_t rtc_main_state:             4;        /*rtc main state machine status*/
+        };
+        uint32_t val;
+    } low_power_st;
+    uint32_t diag0;                                    /**/
+    union {
+        struct {
+            uint32_t rtc_gpio_pin0_hold: 1;
+            uint32_t rtc_gpio_pin1_hold: 1;
+            uint32_t rtc_gpio_pin2_hold: 1;
+            uint32_t rtc_gpio_pin3_hold: 1;
+            uint32_t rtc_gpio_pin4_hold: 1;
+            uint32_t rtc_gpio_pin5_hold: 1;
+            uint32_t reserved6:         26;
+        };
+        uint32_t val;
+    } pad_hold;
+    uint32_t dig_pad_hold;                                 /**/
+    union {
+        struct {
+            uint32_t reserved0:                 4;
+            uint32_t int_wait:                 10;         /*brown out interrupt wait cycles*/
+            uint32_t close_flash_ena:           1;         /*enable close flash when brown out happens*/
+            uint32_t pd_rf_ena:                 1;         /*enable power down RF when brown out happens*/
+            uint32_t rst_wait:                 10;         /*brown out reset wait cycles*/
+            uint32_t rst_ena:                   1;         /*enable brown out reset*/
+            uint32_t rst_sel:                   1;         /*1:  4-pos reset*/
+            uint32_t ana_rst_en:                1;
+            uint32_t cnt_clr:                   1;         /*clear brown out counter*/
+            uint32_t ena:                       1;         /*enable brown out*/
+            uint32_t det:                       1;
+        };
+        uint32_t val;
+    } brown_out;
+    uint32_t time_low1;                                /*RTC timer low 32 bits*/
+    union {
+        struct {
+            uint32_t rtc_timer_value1_high:16;             /*RTC timer high 16 bits*/
+            uint32_t reserved16:           16;
+        };
+        uint32_t val;
+    } time_high1;
+    uint32_t xtal32k_clk_factor;                       /*xtal 32k watch dog backup clock factor*/
+    union {
+        struct {
+            uint32_t xtal32k_return_wait:  4;              /*cycles to wait to return normal xtal 32k*/
+            uint32_t xtal32k_restart_wait:16;              /*cycles to wait to repower on xtal 32k*/
+            uint32_t xtal32k_wdt_timeout:  8;              /*If no clock detected for this amount of time*/
+            uint32_t xtal32k_stable_thres: 4;              /*if restarted xtal32k period is smaller than this*/
+        };
+        uint32_t val;
+    } xtal32k_conf;
+    union {
+        struct {
+            uint32_t reserved0:           18;
+            uint32_t io_mux_reset_disable: 1;
+            uint32_t reserved19:          13;
+        };
+        uint32_t val;
+    } usb_conf;
+    union {
+        struct {
+            uint32_t reject_cause:18;                      /*sleep reject cause*/
+            uint32_t reserved18:  14;
+        };
+        uint32_t val;
+    } slp_reject_cause;
+    union {
+        struct {
+            uint32_t force_download_boot: 1;
+            uint32_t reserved1:          31;
+        };
+        uint32_t val;
+    } option1;
+    union {
+        struct {
+            uint32_t wakeup_cause:17;                      /*sleep wakeup cause*/
+            uint32_t reserved17:  15;
+        };
+        uint32_t val;
+    } slp_wakeup_cause;
+    union {
+        struct {
+            uint32_t reserved0:              8;
+            uint32_t ulp_cp_timer_slp_cycle:24;            /*sleep cycles for ULP-coprocessor timer*/
+        };
+        uint32_t val;
+    } ulp_cp_timer_1;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1ts:               1;     /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1ts:               1;     /*enable sleep reject interrupt*/
+            uint32_t reserved2:                     1;
+            uint32_t rtc_wdt_w1ts:                  1;     /*enable RTC WDT interrupt*/
+            uint32_t reserved4:                     5;
+            uint32_t w1ts:                          1;     /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1ts:           1;     /*enable RTC main timer interrupt*/
+            uint32_t reserved11:                    4;
+            uint32_t rtc_swd_w1ts:                  1;     /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead_w1ts:         1;     /*enable xtal32k_dead  interrupt*/
+            uint32_t reserved17:                    2;
+            uint32_t rtc_glitch_det_w1ts:           1;     /*enable gitch det interrupt*/
+            uint32_t rtc_bbpll_cal_w1ts:            1;
+            uint32_t reserved21:                   11;
+        };
+        uint32_t val;
+    } int_ena_w1ts;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1tc:               1;     /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1tc:               1;     /*enable sleep reject interrupt*/
+            uint32_t reserved2:                     1;
+            uint32_t rtc_wdt_w1tc:                  1;     /*enable RTC WDT interrupt*/
+            uint32_t reserved4:                     5;
+            uint32_t w1tc:                          1;     /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1tc:           1;     /*enable RTC main timer interrupt*/
+            uint32_t reserved11:                    4;
+            uint32_t rtc_swd_w1tc:                  1;     /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead_w1tc:         1;     /*enable xtal32k_dead  interrupt*/
+            uint32_t reserved17:                    2;
+            uint32_t rtc_glitch_det_w1tc:           1;     /*enable gitch det interrupt*/
+            uint32_t rtc_bbpll_cal_w1tc:            1;
+            uint32_t reserved21:                   11;
+        };
+        uint32_t val;
+    } int_ena_w1tc;
+    union {
+        struct {
+            uint32_t reserved0:            18;
+            uint32_t retention_clk_sel:     1;
+            uint32_t retention_done_wait:   3;
+            uint32_t retention_clkoff_wait: 4;
+            uint32_t retention_en:          1;
+            uint32_t retention_wait:        5;             /*wait cycles for rention operation*/
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t rtc_fib_sel: 3;                       /*select use analog fib signal*/
+            uint32_t reserved3:  29;
+        };
+        uint32_t val;
+    } fib_sel;
+    union {
+        struct {
+            uint32_t rtc_gpio_wakeup_status:      6;
+            uint32_t rtc_gpio_wakeup_status_clr:  1;
+            uint32_t rtc_gpio_pin_clk_gate:       1;
+            uint32_t rtc_gpio_pin5_int_type:      3;
+            uint32_t rtc_gpio_pin4_int_type:      3;
+            uint32_t rtc_gpio_pin3_int_type:      3;
+            uint32_t rtc_gpio_pin2_int_type:      3;
+            uint32_t rtc_gpio_pin1_int_type:      3;
+            uint32_t rtc_gpio_pin0_int_type:      3;
+            uint32_t rtc_gpio_pin5_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin4_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin3_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin2_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin1_wakeup_enable: 1;
+            uint32_t rtc_gpio_pin0_wakeup_enable: 1;
+        };
+        uint32_t val;
+    } gpio_wakeup;
+    union {
+        struct {
+            uint32_t reserved0:               1;
+            uint32_t rtc_debug_12m_no_gating: 1;
+            uint32_t rtc_debug_bit_sel:       5;
+            uint32_t rtc_debug_sel0:          5;
+            uint32_t rtc_debug_sel1:          5;
+            uint32_t rtc_debug_sel2:          5;
+            uint32_t rtc_debug_sel3:          5;
+            uint32_t rtc_debug_sel4:          5;
+        };
+        uint32_t val;
+    } dbg_sel;
+    union {
+        struct {
+            uint32_t reserved0:             2;
+            uint32_t rtc_gpio_pin5_mux_sel: 1;
+            uint32_t rtc_gpio_pin4_mux_sel: 1;
+            uint32_t rtc_gpio_pin3_mux_sel: 1;
+            uint32_t rtc_gpio_pin2_mux_sel: 1;
+            uint32_t rtc_gpio_pin1_mux_sel: 1;
+            uint32_t rtc_gpio_pin0_mux_sel: 1;
+            uint32_t rtc_gpio_pin5_fun_sel: 4;
+            uint32_t rtc_gpio_pin4_fun_sel: 4;
+            uint32_t rtc_gpio_pin3_fun_sel: 4;
+            uint32_t rtc_gpio_pin2_fun_sel: 4;
+            uint32_t rtc_gpio_pin1_fun_sel: 4;
+            uint32_t rtc_gpio_pin0_fun_sel: 4;
+        };
+        uint32_t val;
+    } dbg_map;
+    union {
+        struct {
+            uint32_t reserved0:     27;
+            uint32_t sar2_pwdet_cct: 3;
+            uint32_t force_xpd_sar:  2;
+        };
+        uint32_t val;
+    } sensor_ctrl;
+    union {
+        struct {
+            uint32_t reserved0:    27;
+            uint32_t sar_debug_sel: 5;
+        };
+        uint32_t val;
+    } dbg_sar_sel;
+    union {
+        struct {
+            uint32_t reserved0:             26;
+            uint32_t power_glitch_dsense:    2;
+            uint32_t power_glitch_force_pd:  1;
+            uint32_t power_glitch_force_pu:  1;
+            uint32_t power_glitch_efuse_sel: 1;
+            uint32_t power_glitch_en:        1;
+        };
+        uint32_t val;
+    } pg_ctrl;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rtc_cntl_dev_t;
+extern rtc_cntl_dev_t RTCCNTL;
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/rtc_i2c_reg.h b/components/soc/esp32c3/register/soc/rtc_i2c_reg.h
new file mode 100644
index 00000000000..eba7d42df63
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/rtc_i2c_reg.h
@@ -0,0 +1,676 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_RTC_I2C_REG_H_
+#define _SOC_RTC_I2C_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define RTC_I2C_SCL_LOW_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0000)
+/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
+/*description: time period that scl = 0*/
+#define RTC_I2C_SCL_LOW_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_LOW_PERIOD_M  ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
+#define RTC_I2C_SCL_LOW_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_LOW_PERIOD_S  0
+
+#define RTC_I2C_CTRL_REG          (DR_REG_RTC_I2C_BASE + 0x0004)
+/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: rtc i2c reg clk gating*/
+#define RTC_I2C_CLK_EN  (BIT(31))
+#define RTC_I2C_CLK_EN_M  (BIT(31))
+#define RTC_I2C_CLK_EN_V  0x1
+#define RTC_I2C_CLK_EN_S  31
+/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: rtc i2c sw reset*/
+#define RTC_I2C_RESET  (BIT(30))
+#define RTC_I2C_RESET_M  (BIT(30))
+#define RTC_I2C_RESET_V  0x1
+#define RTC_I2C_RESET_S  30
+/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define RTC_I2C_CTRL_CLK_GATE_EN  (BIT(29))
+#define RTC_I2C_CTRL_CLK_GATE_EN_M  (BIT(29))
+#define RTC_I2C_CTRL_CLK_GATE_EN_V  0x1
+#define RTC_I2C_CTRL_CLK_GATE_EN_S  29
+/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: receive lsb first*/
+#define RTC_I2C_RX_LSB_FIRST  (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_M  (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_V  0x1
+#define RTC_I2C_RX_LSB_FIRST_S  5
+/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: transit lsb first*/
+#define RTC_I2C_TX_LSB_FIRST  (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_M  (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_V  0x1
+#define RTC_I2C_TX_LSB_FIRST_S  4
+/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: force start*/
+#define RTC_I2C_TRANS_START  (BIT(3))
+#define RTC_I2C_TRANS_START_M  (BIT(3))
+#define RTC_I2C_TRANS_START_V  0x1
+#define RTC_I2C_TRANS_START_S  3
+/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1=master  0=slave*/
+#define RTC_I2C_MS_MODE  (BIT(2))
+#define RTC_I2C_MS_MODE_M  (BIT(2))
+#define RTC_I2C_MS_MODE_V  0x1
+#define RTC_I2C_MS_MODE_S  2
+/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1=push pull  0=open drain*/
+#define RTC_I2C_SCL_FORCE_OUT  (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_M  (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_V  0x1
+#define RTC_I2C_SCL_FORCE_OUT_S  1
+/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1=push pull  0=open drain*/
+#define RTC_I2C_SDA_FORCE_OUT  (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_M  (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_V  0x1
+#define RTC_I2C_SDA_FORCE_OUT_S  0
+
+#define RTC_I2C_STATUS_REG          (DR_REG_RTC_I2C_BASE + 0x0008)
+/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: scl last status*/
+#define RTC_I2C_SCL_STATE_LAST  0x00000007
+#define RTC_I2C_SCL_STATE_LAST_M  ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
+#define RTC_I2C_SCL_STATE_LAST_V  0x7
+#define RTC_I2C_SCL_STATE_LAST_S  28
+/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: i2c last main status*/
+#define RTC_I2C_SCL_MAIN_STATE_LAST  0x00000007
+#define RTC_I2C_SCL_MAIN_STATE_LAST_M  ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
+#define RTC_I2C_SCL_MAIN_STATE_LAST_V  0x7
+#define RTC_I2C_SCL_MAIN_STATE_LAST_S  24
+/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
+/*description: shifter content*/
+#define RTC_I2C_SHIFT  0x000000FF
+#define RTC_I2C_SHIFT_M  ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
+#define RTC_I2C_SHIFT_V  0xFF
+#define RTC_I2C_SHIFT_S  16
+/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: which operation is working*/
+#define RTC_I2C_OP_CNT  0x00000003
+#define RTC_I2C_OP_CNT_M  ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
+#define RTC_I2C_OP_CNT_V  0x3
+#define RTC_I2C_OP_CNT_S  6
+/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: One byte transit done*/
+#define RTC_I2C_BYTE_TRANS  (BIT(5))
+#define RTC_I2C_BYTE_TRANS_M  (BIT(5))
+#define RTC_I2C_BYTE_TRANS_V  0x1
+#define RTC_I2C_BYTE_TRANS_S  5
+/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: slave reg sub address*/
+#define RTC_I2C_SLAVE_ADDRESSED  (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_M  (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_V  0x1
+#define RTC_I2C_SLAVE_ADDRESSED_S  4
+/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: bus is busy*/
+#define RTC_I2C_BUS_BUSY  (BIT(3))
+#define RTC_I2C_BUS_BUSY_M  (BIT(3))
+#define RTC_I2C_BUS_BUSY_V  0x1
+#define RTC_I2C_BUS_BUSY_S  3
+/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: arbitration is lost*/
+#define RTC_I2C_ARB_LOST  (BIT(2))
+#define RTC_I2C_ARB_LOST_M  (BIT(2))
+#define RTC_I2C_ARB_LOST_V  0x1
+#define RTC_I2C_ARB_LOST_S  2
+/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: slave read or write*/
+#define RTC_I2C_SLAVE_RW  (BIT(1))
+#define RTC_I2C_SLAVE_RW_M  (BIT(1))
+#define RTC_I2C_SLAVE_RW_V  0x1
+#define RTC_I2C_SLAVE_RW_S  1
+/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: ack response*/
+#define RTC_I2C_ACK_REC  (BIT(0))
+#define RTC_I2C_ACK_REC_M  (BIT(0))
+#define RTC_I2C_ACK_REC_V  0x1
+#define RTC_I2C_ACK_REC_S  0
+
+#define RTC_I2C_TIMEOUT_REG          (DR_REG_RTC_I2C_BASE + 0x000c)
+/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
+/*description: time out threshold*/
+#define RTC_I2C_TIMEOUT  0x000FFFFF
+#define RTC_I2C_TIMEOUT_M  ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
+#define RTC_I2C_TIMEOUT_V  0xFFFFF
+#define RTC_I2C_TIMEOUT_S  0
+
+#define RTC_I2C_SLAVE_ADDR_REG          (DR_REG_RTC_I2C_BASE + 0x0010)
+/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: i2c 10bit mode enable*/
+#define RTC_I2C_ADDR_10BIT_EN  (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_M  (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_V  0x1
+#define RTC_I2C_ADDR_10BIT_EN_S  31
+/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+/*description: slave address*/
+#define RTC_I2C_SLAVE_ADDR  0x00007FFF
+#define RTC_I2C_SLAVE_ADDR_M  ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
+#define RTC_I2C_SLAVE_ADDR_V  0x7FFF
+#define RTC_I2C_SLAVE_ADDR_S  0
+
+#define RTC_I2C_SCL_HIGH_REG          (DR_REG_RTC_I2C_BASE + 0x0014)
+/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
+/*description: time period that scl = 1*/
+#define RTC_I2C_SCL_HIGH_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_HIGH_PERIOD_M  ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
+#define RTC_I2C_SCL_HIGH_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_HIGH_PERIOD_S  0
+
+#define RTC_I2C_SDA_DUTY_REG          (DR_REG_RTC_I2C_BASE + 0x0018)
+/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
+/*description: time period for SDA to toggle after SCL goes low*/
+#define RTC_I2C_SDA_DUTY_NUM  0x000FFFFF
+#define RTC_I2C_SDA_DUTY_NUM_M  ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
+#define RTC_I2C_SDA_DUTY_NUM_V  0xFFFFF
+#define RTC_I2C_SDA_DUTY_NUM_S  0
+
+#define RTC_I2C_SCL_START_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x001c)
+/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
+/*description: time period for SCL to toggle after I2C start is triggered*/
+#define RTC_I2C_SCL_START_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_START_PERIOD_M  ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
+#define RTC_I2C_SCL_START_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_START_PERIOD_S  0
+
+#define RTC_I2C_SCL_STOP_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0020)
+/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
+/*description: time period for SCL to stop after I2C end is triggered*/
+#define RTC_I2C_SCL_STOP_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_STOP_PERIOD_M  ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
+#define RTC_I2C_SCL_STOP_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_STOP_PERIOD_S  0
+
+#define RTC_I2C_INT_CLR_REG          (DR_REG_RTC_I2C_BASE + 0x0024)
+/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: clear detect start interrupt*/
+#define RTC_I2C_DETECT_START_INT_CLR  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_V  0x1
+#define RTC_I2C_DETECT_START_INT_CLR_S  8
+/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: clear transit load data complete interrupt*/
+#define RTC_I2C_TX_DATA_INT_CLR  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_V  0x1
+#define RTC_I2C_TX_DATA_INT_CLR_S  7
+/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: clear receive data interrupt*/
+#define RTC_I2C_RX_DATA_INT_CLR  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_V  0x1
+#define RTC_I2C_RX_DATA_INT_CLR_S  6
+/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: clear ack error interrupt*/
+#define RTC_I2C_ACK_ERR_INT_CLR  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_V  0x1
+#define RTC_I2C_ACK_ERR_INT_CLR_S  5
+/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: clear time out interrupt*/
+#define RTC_I2C_TIMEOUT_INT_CLR  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_CLR_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_CLR_V  0x1
+#define RTC_I2C_TIMEOUT_INT_CLR_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: clear transit complete interrupt*/
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: clear master transit complete interrupt*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear arbitration lost interrupt*/
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: clear slave transit complete interrupt*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S  0
+
+#define RTC_I2C_INT_RAW_REG          (DR_REG_RTC_I2C_BASE + 0x0028)
+/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: detect start interrupt raw*/
+#define RTC_I2C_DETECT_START_INT_RAW  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_V  0x1
+#define RTC_I2C_DETECT_START_INT_RAW_S  8
+/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: transit data interrupt raw*/
+#define RTC_I2C_TX_DATA_INT_RAW  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_V  0x1
+#define RTC_I2C_TX_DATA_INT_RAW_S  7
+/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: receive data interrupt raw*/
+#define RTC_I2C_RX_DATA_INT_RAW  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_V  0x1
+#define RTC_I2C_RX_DATA_INT_RAW_S  6
+/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ack error interrupt raw*/
+#define RTC_I2C_ACK_ERR_INT_RAW  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_V  0x1
+#define RTC_I2C_ACK_ERR_INT_RAW_S  5
+/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: time out interrupt raw*/
+#define RTC_I2C_TIMEOUT_INT_RAW  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_RAW_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_RAW_V  0x1
+#define RTC_I2C_TIMEOUT_INT_RAW_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: transit complete interrupt raw*/
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: master transit complete interrupt raw*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: arbitration lost interrupt raw*/
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: slave transit complete interrupt raw*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S  0
+
+#define RTC_I2C_INT_ST_REG          (DR_REG_RTC_I2C_BASE + 0x002c)
+/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: detect start interrupt state*/
+#define RTC_I2C_DETECT_START_INT_ST  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_V  0x1
+#define RTC_I2C_DETECT_START_INT_ST_S  8
+/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: transit data interrupt state*/
+#define RTC_I2C_TX_DATA_INT_ST  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_V  0x1
+#define RTC_I2C_TX_DATA_INT_ST_S  7
+/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: receive data interrupt state*/
+#define RTC_I2C_RX_DATA_INT_ST  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_V  0x1
+#define RTC_I2C_RX_DATA_INT_ST_S  6
+/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ack error interrupt state*/
+#define RTC_I2C_ACK_ERR_INT_ST  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_V  0x1
+#define RTC_I2C_ACK_ERR_INT_ST_S  5
+/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: time out interrupt state*/
+#define RTC_I2C_TIMEOUT_INT_ST  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ST_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ST_V  0x1
+#define RTC_I2C_TIMEOUT_INT_ST_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: transit complete interrupt state*/
+#define RTC_I2C_TRANS_COMPLETE_INT_ST  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: master transit complete interrupt state*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: arbitration lost interrupt state*/
+#define RTC_I2C_ARBITRATION_LOST_INT_ST  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: slave transit complete interrupt state*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S  0
+
+#define RTC_I2C_INT_ENA_REG          (DR_REG_RTC_I2C_BASE + 0x0030)
+/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable detect start interrupt*/
+#define RTC_I2C_DETECT_START_INT_ENA  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_V  0x1
+#define RTC_I2C_DETECT_START_INT_ENA_S  8
+/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable transit data interrupt*/
+#define RTC_I2C_TX_DATA_INT_ENA  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_V  0x1
+#define RTC_I2C_TX_DATA_INT_ENA_S  7
+/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable receive data interrupt*/
+#define RTC_I2C_RX_DATA_INT_ENA  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_V  0x1
+#define RTC_I2C_RX_DATA_INT_ENA_S  6
+/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable eack error interrupt*/
+#define RTC_I2C_ACK_ERR_INT_ENA  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_V  0x1
+#define RTC_I2C_ACK_ERR_INT_ENA_S  5
+/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable time out interrupt*/
+#define RTC_I2C_TIMEOUT_INT_ENA  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ENA_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ENA_V  0x1
+#define RTC_I2C_TIMEOUT_INT_ENA_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable transit complete interrupt*/
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable master transit complete interrupt*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable arbitration lost interrupt*/
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable slave transit complete interrupt*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S  0
+
+#define RTC_I2C_DATA_REG          (DR_REG_RTC_I2C_BASE + 0x0034)
+/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: i2c done*/
+#define RTC_I2C_DONE  (BIT(31))
+#define RTC_I2C_DONE_M  (BIT(31))
+#define RTC_I2C_DONE_V  0x1
+#define RTC_I2C_DONE_S  31
+/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: data sent by slave*/
+#define RTC_I2C_SLAVE_TX_DATA  0x000000FF
+#define RTC_I2C_SLAVE_TX_DATA_M  ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
+#define RTC_I2C_SLAVE_TX_DATA_V  0xFF
+#define RTC_I2C_SLAVE_TX_DATA_S  8
+/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: data received*/
+#define RTC_I2C_RDATA  0x000000FF
+#define RTC_I2C_RDATA_M  ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
+#define RTC_I2C_RDATA_V  0xFF
+#define RTC_I2C_RDATA_S  0
+
+#define RTC_I2C_CMD0_REG          (DR_REG_RTC_I2C_BASE + 0x0038)
+/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command0_done*/
+#define RTC_I2C_COMMAND0_DONE  (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_V  0x1
+#define RTC_I2C_COMMAND0_DONE_S  31
+/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
+/*description: command0*/
+#define RTC_I2C_COMMAND0  0x00003FFF
+#define RTC_I2C_COMMAND0_M  ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
+#define RTC_I2C_COMMAND0_V  0x3FFF
+#define RTC_I2C_COMMAND0_S  0
+
+#define RTC_I2C_CMD1_REG          (DR_REG_RTC_I2C_BASE + 0x003c)
+/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command1_done*/
+#define RTC_I2C_COMMAND1_DONE  (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_V  0x1
+#define RTC_I2C_COMMAND1_DONE_S  31
+/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command1*/
+#define RTC_I2C_COMMAND1  0x00003FFF
+#define RTC_I2C_COMMAND1_M  ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
+#define RTC_I2C_COMMAND1_V  0x3FFF
+#define RTC_I2C_COMMAND1_S  0
+
+#define RTC_I2C_CMD2_REG          (DR_REG_RTC_I2C_BASE + 0x0040)
+/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command2_done*/
+#define RTC_I2C_COMMAND2_DONE  (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_V  0x1
+#define RTC_I2C_COMMAND2_DONE_S  31
+/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
+/*description: command2*/
+#define RTC_I2C_COMMAND2  0x00003FFF
+#define RTC_I2C_COMMAND2_M  ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
+#define RTC_I2C_COMMAND2_V  0x3FFF
+#define RTC_I2C_COMMAND2_S  0
+
+#define RTC_I2C_CMD3_REG          (DR_REG_RTC_I2C_BASE + 0x0044)
+/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command3_done*/
+#define RTC_I2C_COMMAND3_DONE  (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_V  0x1
+#define RTC_I2C_COMMAND3_DONE_S  31
+/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
+/*description: command3*/
+#define RTC_I2C_COMMAND3  0x00003FFF
+#define RTC_I2C_COMMAND3_M  ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
+#define RTC_I2C_COMMAND3_V  0x3FFF
+#define RTC_I2C_COMMAND3_S  0
+
+#define RTC_I2C_CMD4_REG          (DR_REG_RTC_I2C_BASE + 0x0048)
+/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command4_done*/
+#define RTC_I2C_COMMAND4_DONE  (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_V  0x1
+#define RTC_I2C_COMMAND4_DONE_S  31
+/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
+/*description: command4*/
+#define RTC_I2C_COMMAND4  0x00003FFF
+#define RTC_I2C_COMMAND4_M  ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
+#define RTC_I2C_COMMAND4_V  0x3FFF
+#define RTC_I2C_COMMAND4_S  0
+
+#define RTC_I2C_CMD5_REG          (DR_REG_RTC_I2C_BASE + 0x004c)
+/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command5_done*/
+#define RTC_I2C_COMMAND5_DONE  (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_V  0x1
+#define RTC_I2C_COMMAND5_DONE_S  31
+/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
+/*description: command5*/
+#define RTC_I2C_COMMAND5  0x00003FFF
+#define RTC_I2C_COMMAND5_M  ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
+#define RTC_I2C_COMMAND5_V  0x3FFF
+#define RTC_I2C_COMMAND5_S  0
+
+#define RTC_I2C_CMD6_REG          (DR_REG_RTC_I2C_BASE + 0x0050)
+/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command6_done*/
+#define RTC_I2C_COMMAND6_DONE  (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_V  0x1
+#define RTC_I2C_COMMAND6_DONE_S  31
+/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command6*/
+#define RTC_I2C_COMMAND6  0x00003FFF
+#define RTC_I2C_COMMAND6_M  ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
+#define RTC_I2C_COMMAND6_V  0x3FFF
+#define RTC_I2C_COMMAND6_S  0
+
+#define RTC_I2C_CMD7_REG          (DR_REG_RTC_I2C_BASE + 0x0054)
+/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command7_done*/
+#define RTC_I2C_COMMAND7_DONE  (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_V  0x1
+#define RTC_I2C_COMMAND7_DONE_S  31
+/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
+/*description: command7*/
+#define RTC_I2C_COMMAND7  0x00003FFF
+#define RTC_I2C_COMMAND7_M  ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
+#define RTC_I2C_COMMAND7_V  0x3FFF
+#define RTC_I2C_COMMAND7_S  0
+
+#define RTC_I2C_CMD8_REG          (DR_REG_RTC_I2C_BASE + 0x0058)
+/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command8_done*/
+#define RTC_I2C_COMMAND8_DONE  (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_V  0x1
+#define RTC_I2C_COMMAND8_DONE_S  31
+/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command8*/
+#define RTC_I2C_COMMAND8  0x00003FFF
+#define RTC_I2C_COMMAND8_M  ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
+#define RTC_I2C_COMMAND8_V  0x3FFF
+#define RTC_I2C_COMMAND8_S  0
+
+#define RTC_I2C_CMD9_REG          (DR_REG_RTC_I2C_BASE + 0x005c)
+/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command9_done*/
+#define RTC_I2C_COMMAND9_DONE  (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_V  0x1
+#define RTC_I2C_COMMAND9_DONE_S  31
+/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
+/*description: command9*/
+#define RTC_I2C_COMMAND9  0x00003FFF
+#define RTC_I2C_COMMAND9_M  ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
+#define RTC_I2C_COMMAND9_V  0x3FFF
+#define RTC_I2C_COMMAND9_S  0
+
+#define RTC_I2C_CMD10_REG          (DR_REG_RTC_I2C_BASE + 0x0060)
+/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command10_done*/
+#define RTC_I2C_COMMAND10_DONE  (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_V  0x1
+#define RTC_I2C_COMMAND10_DONE_S  31
+/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
+/*description: command10*/
+#define RTC_I2C_COMMAND10  0x00003FFF
+#define RTC_I2C_COMMAND10_M  ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
+#define RTC_I2C_COMMAND10_V  0x3FFF
+#define RTC_I2C_COMMAND10_S  0
+
+#define RTC_I2C_CMD11_REG          (DR_REG_RTC_I2C_BASE + 0x0064)
+/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command11_done*/
+#define RTC_I2C_COMMAND11_DONE  (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_V  0x1
+#define RTC_I2C_COMMAND11_DONE_S  31
+/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
+/*description: command11*/
+#define RTC_I2C_COMMAND11  0x00003FFF
+#define RTC_I2C_COMMAND11_M  ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
+#define RTC_I2C_COMMAND11_V  0x3FFF
+#define RTC_I2C_COMMAND11_S  0
+
+#define RTC_I2C_CMD12_REG          (DR_REG_RTC_I2C_BASE + 0x0068)
+/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command12_done*/
+#define RTC_I2C_COMMAND12_DONE  (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_V  0x1
+#define RTC_I2C_COMMAND12_DONE_S  31
+/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
+/*description: command12*/
+#define RTC_I2C_COMMAND12  0x00003FFF
+#define RTC_I2C_COMMAND12_M  ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
+#define RTC_I2C_COMMAND12_V  0x3FFF
+#define RTC_I2C_COMMAND12_S  0
+
+#define RTC_I2C_CMD13_REG          (DR_REG_RTC_I2C_BASE + 0x006c)
+/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command13_done*/
+#define RTC_I2C_COMMAND13_DONE  (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_V  0x1
+#define RTC_I2C_COMMAND13_DONE_S  31
+/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command13*/
+#define RTC_I2C_COMMAND13  0x00003FFF
+#define RTC_I2C_COMMAND13_M  ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
+#define RTC_I2C_COMMAND13_V  0x3FFF
+#define RTC_I2C_COMMAND13_S  0
+
+#define RTC_I2C_CMD14_REG          (DR_REG_RTC_I2C_BASE + 0x0070)
+/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command14_done*/
+#define RTC_I2C_COMMAND14_DONE  (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_V  0x1
+#define RTC_I2C_COMMAND14_DONE_S  31
+/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: command14*/
+#define RTC_I2C_COMMAND14  0x00003FFF
+#define RTC_I2C_COMMAND14_M  ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
+#define RTC_I2C_COMMAND14_V  0x3FFF
+#define RTC_I2C_COMMAND14_S  0
+
+#define RTC_I2C_CMD15_REG          (DR_REG_RTC_I2C_BASE + 0x0074)
+/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command15_done*/
+#define RTC_I2C_COMMAND15_DONE  (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_V  0x1
+#define RTC_I2C_COMMAND15_DONE_S  31
+/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: command15*/
+#define RTC_I2C_COMMAND15  0x00003FFF
+#define RTC_I2C_COMMAND15_M  ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
+#define RTC_I2C_COMMAND15_V  0x3FFF
+#define RTC_I2C_COMMAND15_S  0
+
+#define RTC_I2C_DATE_REG          (DR_REG_RTC_I2C_BASE + 0x00FC)
+/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
+/*description: */
+#define RTC_I2C_DATE  0x0FFFFFFF
+#define RTC_I2C_DATE_M  ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
+#define RTC_I2C_DATE_V  0xFFFFFFF
+#define RTC_I2C_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_I2C_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/rtc_i2c_struct.h b/components/soc/esp32c3/register/soc/rtc_i2c_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/rtc_i2c_struct.h
rename to components/soc/esp32c3/register/soc/rtc_i2c_struct.h
diff --git a/components/soc/esp32c3/register/soc/sensitive_reg.h b/components/soc/esp32c3/register/soc/sensitive_reg.h
new file mode 100644
index 00000000000..089d9c4aa4a
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/sensitive_reg.h
@@ -0,0 +1,2296 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SENSITIVE_REG_H_
+#define _SOC_SENSITIVE_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define SENSITIVE_ROM_TABLE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x000)
+/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_ROM_TABLE_LOCK  (BIT(0))
+#define SENSITIVE_ROM_TABLE_LOCK_M  (BIT(0))
+#define SENSITIVE_ROM_TABLE_LOCK_V  0x1
+#define SENSITIVE_ROM_TABLE_LOCK_S  0
+
+#define SENSITIVE_ROM_TABLE_REG          (DR_REG_SENSITIVE_BASE + 0x004)
+/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SENSITIVE_ROM_TABLE  0xFFFFFFFF
+#define SENSITIVE_ROM_TABLE_M  ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S))
+#define SENSITIVE_ROM_TABLE_V  0xFFFFFFFF
+#define SENSITIVE_ROM_TABLE_S  0
+
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x008)
+/* SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK  (BIT(0))
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M  (BIT(0))
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V  0x1
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S  0
+
+#define SENSITIVE_PRIVILEGE_MODE_SEL_REG          (DR_REG_SENSITIVE_BASE + 0x00C)
+/* SENSITIVE_PRIVILEGE_MODE_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_PRIVILEGE_MODE_SEL  (BIT(0))
+#define SENSITIVE_PRIVILEGE_MODE_SEL_M  (BIT(0))
+#define SENSITIVE_PRIVILEGE_MODE_SEL_V  0x1
+#define SENSITIVE_PRIVILEGE_MODE_SEL_S  0
+
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x010)
+/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S  0
+
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x014)
+/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG          (DR_REG_SENSITIVE_BASE + 0x018)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG          (DR_REG_SENSITIVE_BASE + 0x01C)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: ~3'h0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM  0x00000007
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V  0x7
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S  1
+/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: ~1'h0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG          (DR_REG_SENSITIVE_BASE + 0x020)
+/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP  (BIT(3))
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M  (BIT(3))
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S  3
+/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM  0x00000007
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V  0x7
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG          (DR_REG_SENSITIVE_BASE + 0x024)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S  0
+
+#define SENSITIVE_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x028)
+/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK  (BIT(0))
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S  0
+
+#define SENSITIVE_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x02C)
+/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_PRO_D_TAG_WR_ACS  (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_M  (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x1
+#define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
+/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_PRO_D_TAG_RD_ACS  (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_M  (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
+/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_PRO_I_TAG_WR_ACS  (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_M  (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
+/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_PRO_I_TAG_RD_ACS  (BIT(0))
+#define SENSITIVE_PRO_I_TAG_RD_ACS_M  (BIT(0))
+#define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_RD_ACS_S  0
+
+#define SENSITIVE_CACHE_MMU_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x030)
+/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK  (BIT(0))
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S  0
+
+#define SENSITIVE_CACHE_MMU_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x034)
+/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_PRO_MMU_WR_ACS  (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_M  (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_WR_ACS_S  1
+/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_PRO_MMU_RD_ACS  (BIT(0))
+#define SENSITIVE_PRO_MMU_RD_ACS_M  (BIT(0))
+#define SENSITIVE_PRO_MMU_RD_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_RD_ACS_S  0
+
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x038)
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x03C)
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x040)
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x044)
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x048)
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x04C)
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x050)
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x054)
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x058)
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x05C)
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x060)
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x064)
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x068)
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x06C)
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x070)
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x074)
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x078)
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x07C)
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x080)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x084)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x088)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[26:3] ;default: 24'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  3
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x08C)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN  0x0000000F
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x090)
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x094)
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x098)
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x09C)
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x0A0)
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x0A4)
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR  0x000000FF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0A8)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0AC)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  18
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  12
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  9
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  6
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  3
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x0B0)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  18
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  12
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  9
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  6
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  3
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x0B4)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x0B8)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x0BC)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE  (BIT(2))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0C0)
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0C4)
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  26
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  24
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0  0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x0C8)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x0CC)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x0D0)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[27:4] ;default: 24'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR  0x00FFFFFF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD  0x00000003
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x0D4)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN  0x0000000F
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x0D8)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x0DC)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x0E0)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x0E4)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x0E8)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x0EC)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x0F0)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x0F4)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x0F8)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x0FC)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1  0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0  0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x100)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x104)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x108)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x10C)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
+/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0  0x00000003
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x110)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x114)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x118)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x11C)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x120)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x124)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x128)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S  0
+
+#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x12C)
+/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S))
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x130)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x134)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x138)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE  (BIT(5))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE  0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x13C)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x140)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x144)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x148)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x14C)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x150)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S  30
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S  24
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S  18
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S  16
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMER_S  12
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S  8
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S  2
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x154)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S  30
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S  28
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S  22
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S  16
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x158)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S  28
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S  22
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x15C)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S  12
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S  8
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S  2
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x160)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x164)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN  (BIT(1))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x168)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE  (BIT(6))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(6))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE  0x00000007
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  3
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S  1
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x16C)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR  0xFFFFFFFF
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S  0
+
+#define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x170)
+/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_CLK_EN  (BIT(0))
+#define SENSITIVE_CLK_EN_M  (BIT(0))
+#define SENSITIVE_CLK_EN_V  0x1
+#define SENSITIVE_CLK_EN_S  0
+
+#define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
+/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2010200 ; */
+/*description: */
+#define SENSITIVE_DATE  0x0FFFFFFF
+#define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
+#define SENSITIVE_DATE_V  0xFFFFFFF
+#define SENSITIVE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/sensitive_struct.h b/components/soc/esp32c3/register/soc/sensitive_struct.h
new file mode 100644
index 00000000000..a7adaca7b89
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/sensitive_struct.h
@@ -0,0 +1,1903 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SENSITIVE_STRUCT_H_
+#define _SOC_SENSITIVE_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+typedef volatile struct sensitive_dev_s {
+    union {
+        struct {
+            uint32_t reg_rom_table_lock            :    1;  /*rom_table_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } rom_table_lock;
+    uint32_t rom_table;
+    union {
+        struct {
+            uint32_t reg_privilege_mode_sel_lock   :    1;  /*privilege_mode_sel_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } privilege_mode_sel_lock;
+    union {
+        struct {
+            uint32_t reg_privilege_mode_sel        :    1;  /*privilege_mode_sel*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } privilege_mode_sel;
+    union {
+        struct {
+            uint32_t reg_apb_peripheral_access_lock:    1;  /*apb_peripheral_access_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } apb_peripheral_access_0;
+    union {
+        struct {
+            uint32_t reg_apb_peripheral_access_split_burst:    1;  /*apb_peripheral_access_split_burst*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } apb_peripheral_access_1;
+    union {
+        struct {
+            uint32_t reg_internal_sram_usage_lock  :    1;  /*internal_sram_usage_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } internal_sram_usage_0;
+    union {
+        struct {
+            uint32_t reg_internal_sram_usage_cpu_cache:    1;  /*internal_sram_usage_cpu_cache*/
+            uint32_t reg_internal_sram_usage_cpu_sram:    3;  /*internal_sram_usage_cpu_sram*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } internal_sram_usage_1;
+    union {
+        struct {
+            uint32_t reg_internal_sram_usage_mac_dump_sram:    3;  /*internal_sram_usage_mac_dump_sram*/
+            uint32_t reg_internal_sram_alloc_mac_dump:    1;  /*internal_sram_alloc_mac_dump*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } internal_sram_usage_3;
+    union {
+        struct {
+            uint32_t reg_internal_sram_usage_log_sram:    1;  /*internal_sram_usage_log_sram*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } internal_sram_usage_4;
+    union {
+        struct {
+            uint32_t reg_cache_tag_access_lock     :    1;  /*cache_tag_access_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_tag_access_0;
+    union {
+        struct {
+            uint32_t reg_pro_i_tag_rd_acs          :    1;  /*pro_i_tag_rd_acs*/
+            uint32_t reg_pro_i_tag_wr_acs          :    1;  /*pro_i_tag_wr_acs*/
+            uint32_t reg_pro_d_tag_rd_acs          :    1;  /*pro_d_tag_rd_acs*/
+            uint32_t reg_pro_d_tag_wr_acs          :    1;  /*pro_d_tag_wr_acs*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } cache_tag_access_1;
+    union {
+        struct {
+            uint32_t reg_cache_mmu_access_lock     :    1;  /*cache_mmu_access_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_mmu_access_0;
+    union {
+        struct {
+            uint32_t reg_pro_mmu_rd_acs            :    1;  /*pro_mmu_rd_acs*/
+            uint32_t reg_pro_mmu_wr_acs            :    1;  /*pro_mmu_wr_acs*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } cache_mmu_access_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_lock:    1;  /*dma_apbperi_spi2_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_spi2_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_spi2_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_lock:    1;  /*dma_apbperi_uchi0_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_uchi0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_uchi0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_lock:    1;  /*dma_apbperi_i2s0_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_i2s0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_i2s0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_mac_pms_constrain_lock:    1;  /*dma_apbperi_mac_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_mac_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_mac_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_mac_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_mac_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_backup_pms_constrain_lock:    1;  /*dma_apbperi_backup_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_backup_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_backup_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_backup_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_backup_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_lc_pms_constrain_lock:    1;  /*dma_apbperi_lc_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_lc_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_lc_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_lc_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_lc_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_aes_pms_constrain_lock:    1;  /*dma_apbperi_aes_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_aes_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_aes_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_aes_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_aes_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_sha_pms_constrain_lock:    1;  /*dma_apbperi_sha_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_sha_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_sha_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_sha_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_sha_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_lock:    1;  /*dma_apbperi_adc_dac_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_adc_dac_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3:    2;  /*dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } dma_apbperi_adc_dac_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_pms_monitor_lock:    1;  /*dma_apbperi_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_pms_monitor_violate_clr:    1;  /*dma_apbperi_pms_monitor_violate_clr*/
+            uint32_t reg_dma_apbperi_pms_monitor_violate_en:    1;  /*dma_apbperi_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_pms_monitor_violate_intr:    1;  /*dma_apbperi_pms_monitor_violate_intr*/
+            uint32_t reg_dma_apbperi_pms_monitor_violate_status_world:    2;  /*dma_apbperi_pms_monitor_violate_status_world*/
+            uint32_t reg_dma_apbperi_pms_monitor_violate_status_addr:    24;  /*dma_apbperi_pms_monitor_violate_status_addr*/
+            uint32_t reserved27                    :    5;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_2;
+    union {
+        struct {
+            uint32_t reg_dma_apbperi_pms_monitor_violate_status_wr:    1;  /*dma_apbperi_pms_monitor_violate_status_wr*/
+            uint32_t reg_dma_apbperi_pms_monitor_violate_status_byteen:    4;  /*dma_apbperi_pms_monitor_violate_status_byteen*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_3;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_dram0_dma_split_line_constrain_lock:    1;  /*core_x_iram0_dram0_dma_split_line_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_0;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_dram0_dma_sram_category_0:    2;  /*core_x_iram0_dram0_dma_sram_category_0*/
+            uint32_t reg_core_x_iram0_dram0_dma_sram_category_1:    2;  /*core_x_iram0_dram0_dma_sram_category_1*/
+            uint32_t reg_core_x_iram0_dram0_dma_sram_category_2:    2;  /*core_x_iram0_dram0_dma_sram_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_iram0_dram0_dma_sram_splitaddr:    8;  /*core_x_iram0_dram0_dma_sram_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_1;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_sram_line_0_category_0:    2;  /*core_x_iram0_sram_line_0_category_0*/
+            uint32_t reg_core_x_iram0_sram_line_0_category_1:    2;  /*core_x_iram0_sram_line_0_category_1*/
+            uint32_t reg_core_x_iram0_sram_line_0_category_2:    2;  /*core_x_iram0_sram_line_0_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_iram0_sram_line_0_splitaddr:    8;  /*core_x_iram0_sram_line_0_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_2;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_sram_line_1_category_0:    2;  /*core_x_iram0_sram_line_1_category_0*/
+            uint32_t reg_core_x_iram0_sram_line_1_category_1:    2;  /*core_x_iram0_sram_line_1_category_1*/
+            uint32_t reg_core_x_iram0_sram_line_1_category_2:    2;  /*core_x_iram0_sram_line_1_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_iram0_sram_line_1_splitaddr:    8;  /*core_x_iram0_sram_line_1_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_3;
+    union {
+        struct {
+            uint32_t reg_core_x_dram0_dma_sram_line_0_category_0:    2;  /*core_x_dram0_dma_sram_line_0_category_0*/
+            uint32_t reg_core_x_dram0_dma_sram_line_0_category_1:    2;  /*core_x_dram0_dma_sram_line_0_category_1*/
+            uint32_t reg_core_x_dram0_dma_sram_line_0_category_2:    2;  /*core_x_dram0_dma_sram_line_0_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_dram0_dma_sram_line_0_splitaddr:    8;  /*core_x_dram0_dma_sram_line_0_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_4;
+    union {
+        struct {
+            uint32_t reg_core_x_dram0_dma_sram_line_1_category_0:    2;  /*core_x_dram0_dma_sram_line_1_category_0*/
+            uint32_t reg_core_x_dram0_dma_sram_line_1_category_1:    2;  /*core_x_dram0_dma_sram_line_1_category_1*/
+            uint32_t reg_core_x_dram0_dma_sram_line_1_category_2:    2;  /*core_x_dram0_dma_sram_line_1_category_2*/
+            uint32_t reserved6                     :    8;
+            uint32_t reg_core_x_dram0_dma_sram_line_1_splitaddr:    8;  /*core_x_dram0_dma_sram_line_1_splitaddr*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_5;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_pms_constrain_lock:    1;  /*core_x_iram0_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_1:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_2:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_pms_3:    3;  /*core_x_iram0_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0*/
+            uint32_t reserved15                    :    3;
+            uint32_t reg_core_x_iram0_pms_constrain_rom_world_1_pms:    3;  /*core_x_iram0_pms_constrain_rom_world_1_pms*/
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_1:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_2:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_pms_3:    3;  /*core_x_iram0_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reg_core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0:    3;  /*core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0*/
+            uint32_t reserved15                    :    3;
+            uint32_t reg_core_x_iram0_pms_constrain_rom_world_0_pms:    3;  /*core_x_iram0_pms_constrain_rom_world_0_pms*/
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_2;
+    union {
+        struct {
+            uint32_t reg_core_0_iram0_pms_monitor_lock:    1;  /*core_0_iram0_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_core_0_iram0_pms_monitor_violate_clr:    1;  /*core_0_iram0_pms_monitor_violate_clr*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_en:    1;  /*core_0_iram0_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_core_0_iram0_pms_monitor_violate_intr:    1;  /*core_0_iram0_pms_monitor_violate_intr*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_status_wr:    1;  /*core_0_iram0_pms_monitor_violate_status_wr*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_status_loadstore:    1;  /*core_0_iram0_pms_monitor_violate_status_loadstore*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_status_world:    2;  /*core_0_iram0_pms_monitor_violate_status_world*/
+            uint32_t reg_core_0_iram0_pms_monitor_violate_status_addr:    24;  /*core_0_iram0_pms_monitor_violate_status_addr*/
+            uint32_t reserved29                    :    3;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_2;
+    union {
+        struct {
+            uint32_t reg_core_x_dram0_pms_constrain_lock:    1;  /*core_x_dram0_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_dram0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_0:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_0*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_1:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_1*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_2:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_2*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_0_pms_3:    2;  /*core_x_dram0_pms_constrain_sram_world_0_pms_3*/
+            uint32_t reserved8                     :    4;
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_0:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_0*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_1:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_1*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_2:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_2*/
+            uint32_t reg_core_x_dram0_pms_constrain_sram_world_1_pms_3:    2;  /*core_x_dram0_pms_constrain_sram_world_1_pms_3*/
+            uint32_t reserved20                    :    4;
+            uint32_t reg_core_x_dram0_pms_constrain_rom_world_0_pms:    2;  /*core_x_dram0_pms_constrain_rom_world_0_pms*/
+            uint32_t reg_core_x_dram0_pms_constrain_rom_world_1_pms:    2;  /*core_x_dram0_pms_constrain_rom_world_1_pms*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } core_x_dram0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_core_0_dram0_pms_monitor_lock:    1;  /*core_0_dram0_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_core_0_dram0_pms_monitor_violate_clr:    1;  /*core_0_dram0_pms_monitor_violate_clr*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_en:    1;  /*core_0_dram0_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_core_0_dram0_pms_monitor_violate_intr:    1;  /*core_0_dram0_pms_monitor_violate_intr*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_lock:    1;  /*core_0_dram0_pms_monitor_violate_status_lock*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_world:    2;  /*core_0_dram0_pms_monitor_violate_status_world*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_addr:    24;  /*core_0_dram0_pms_monitor_violate_status_addr*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_2;
+    union {
+        struct {
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_wr:    1;  /*core_0_dram0_pms_monitor_violate_status_wr*/
+            uint32_t reg_core_0_dram0_pms_monitor_violate_status_byteen:    4;  /*core_0_dram0_pms_monitor_violate_status_byteen*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_3;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_lock:    1;  /*core_0_pif_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_0_uart:    2;  /*core_0_pif_pms_constrain_world_0_uart*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_1:    2;  /*core_0_pif_pms_constrain_world_0_g0spi_1*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_g0spi_0:    2;  /*core_0_pif_pms_constrain_world_0_g0spi_0*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_gpio:    2;  /*core_0_pif_pms_constrain_world_0_gpio*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_fe2:    2;  /*core_0_pif_pms_constrain_world_0_fe2*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_fe:    2;  /*core_0_pif_pms_constrain_world_0_fe*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_timer:    2;  /*core_0_pif_pms_constrain_world_0_timer*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_rtc:    2;  /*core_0_pif_pms_constrain_world_0_rtc*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_io_mux:    2;  /*core_0_pif_pms_constrain_world_0_io_mux*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_wdg:    2;  /*core_0_pif_pms_constrain_world_0_wdg*/
+            uint32_t reserved20                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_misc:    2;  /*core_0_pif_pms_constrain_world_0_misc*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_i2c:    2;  /*core_0_pif_pms_constrain_world_0_i2c*/
+            uint32_t reserved28                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_uart1:    2;  /*core_0_pif_pms_constrain_world_0_uart1*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_0_bt:    2;  /*core_0_pif_pms_constrain_world_0_bt*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_i2c_ext0:    2;  /*core_0_pif_pms_constrain_world_0_i2c_ext0*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_uhci0:    2;  /*core_0_pif_pms_constrain_world_0_uhci0*/
+            uint32_t reserved8                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_rmt:    2;  /*core_0_pif_pms_constrain_world_0_rmt*/
+            uint32_t reserved12                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_ledc:    2;  /*core_0_pif_pms_constrain_world_0_ledc*/
+            uint32_t reserved18                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_bb:    2;  /*core_0_pif_pms_constrain_world_0_bb*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup:    2;  /*core_0_pif_pms_constrain_world_0_timergroup*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_timergroup1:    2;  /*core_0_pif_pms_constrain_world_0_timergroup1*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_systimer:    2;  /*core_0_pif_pms_constrain_world_0_systimer*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_2;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_0_spi_2:    2;  /*core_0_pif_pms_constrain_world_0_spi_2*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_apb_ctrl:    2;  /*core_0_pif_pms_constrain_world_0_apb_ctrl*/
+            uint32_t reserved6                     :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_can:    2;  /*core_0_pif_pms_constrain_world_0_can*/
+            uint32_t reserved12                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_i2s0:    2;  /*core_0_pif_pms_constrain_world_0_i2s0*/
+            uint32_t reserved16                    :    6;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_rwbt:    2;  /*core_0_pif_pms_constrain_world_0_rwbt*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_wifimac:    2;  /*core_0_pif_pms_constrain_world_0_wifimac*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_pwr:    2;  /*core_0_pif_pms_constrain_world_0_pwr*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_3;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_usb_wrap:    2;  /*core_0_pif_pms_constrain_world_0_usb_wrap*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_peri:    2;  /*core_0_pif_pms_constrain_world_0_crypto_peri*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_crypto_dma:    2;  /*core_0_pif_pms_constrain_world_0_crypto_dma*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_apb_adc:    2;  /*core_0_pif_pms_constrain_world_0_apb_adc*/
+            uint32_t reserved10                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_0_bt_pwr:    2;  /*core_0_pif_pms_constrain_world_0_bt_pwr*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_usb_device:    2;  /*core_0_pif_pms_constrain_world_0_usb_device*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_system:    2;  /*core_0_pif_pms_constrain_world_0_system*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_sensitive:    2;  /*core_0_pif_pms_constrain_world_0_sensitive*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_interrupt:    2;  /*core_0_pif_pms_constrain_world_0_interrupt*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_dma_copy:    2;  /*core_0_pif_pms_constrain_world_0_dma_copy*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_cache_config:    2;  /*core_0_pif_pms_constrain_world_0_cache_config*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_ad:    2;  /*core_0_pif_pms_constrain_world_0_ad*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_dio:    2;  /*core_0_pif_pms_constrain_world_0_dio*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_world_controller:    2;  /*core_0_pif_pms_constrain_world_0_world_controller*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_4;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_1_uart:    2;  /*core_0_pif_pms_constrain_world_1_uart*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_1:    2;  /*core_0_pif_pms_constrain_world_1_g0spi_1*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_g0spi_0:    2;  /*core_0_pif_pms_constrain_world_1_g0spi_0*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_gpio:    2;  /*core_0_pif_pms_constrain_world_1_gpio*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_fe2:    2;  /*core_0_pif_pms_constrain_world_1_fe2*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_fe:    2;  /*core_0_pif_pms_constrain_world_1_fe*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_timer:    2;  /*core_0_pif_pms_constrain_world_1_timer*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_rtc:    2;  /*core_0_pif_pms_constrain_world_1_rtc*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_io_mux:    2;  /*core_0_pif_pms_constrain_world_1_io_mux*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_wdg:    2;  /*core_0_pif_pms_constrain_world_1_wdg*/
+            uint32_t reserved20                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_misc:    2;  /*core_0_pif_pms_constrain_world_1_misc*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_i2c:    2;  /*core_0_pif_pms_constrain_world_1_i2c*/
+            uint32_t reserved28                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_uart1:    2;  /*core_0_pif_pms_constrain_world_1_uart1*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_5;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_1_bt:    2;  /*core_0_pif_pms_constrain_world_1_bt*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_i2c_ext0:    2;  /*core_0_pif_pms_constrain_world_1_i2c_ext0*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_uhci0:    2;  /*core_0_pif_pms_constrain_world_1_uhci0*/
+            uint32_t reserved8                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_rmt:    2;  /*core_0_pif_pms_constrain_world_1_rmt*/
+            uint32_t reserved12                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_ledc:    2;  /*core_0_pif_pms_constrain_world_1_ledc*/
+            uint32_t reserved18                    :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_bb:    2;  /*core_0_pif_pms_constrain_world_1_bb*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup:    2;  /*core_0_pif_pms_constrain_world_1_timergroup*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_timergroup1:    2;  /*core_0_pif_pms_constrain_world_1_timergroup1*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_systimer:    2;  /*core_0_pif_pms_constrain_world_1_systimer*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_6;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_world_1_spi_2:    2;  /*core_0_pif_pms_constrain_world_1_spi_2*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl:    2;  /*core_0_pif_pms_constrain_world_1_apb_ctrl*/
+            uint32_t reserved6                     :    4;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_can:    2;  /*core_0_pif_pms_constrain_world_1_can*/
+            uint32_t reserved12                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_i2s0:    2;  /*core_0_pif_pms_constrain_world_1_i2s0*/
+            uint32_t reserved16                    :    6;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_rwbt:    2;  /*core_0_pif_pms_constrain_world_1_rwbt*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_wifimac:    2;  /*core_0_pif_pms_constrain_world_1_wifimac*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_pwr:    2;  /*core_0_pif_pms_constrain_world_1_pwr*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_7;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_usb_wrap:    2;  /*core_0_pif_pms_constrain_world_1_usb_wrap*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_peri:    2;  /*core_0_pif_pms_constrain_world_1_crypto_peri*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_crypto_dma:    2;  /*core_0_pif_pms_constrain_world_1_crypto_dma*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_apb_adc:    2;  /*core_0_pif_pms_constrain_world_1_apb_adc*/
+            uint32_t reserved10                    :    2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_bt_pwr:    2;  /*core_0_pif_pms_constrain_world_1_bt_pwr*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_usb_device:    2;  /*core_0_pif_pms_constrain_world_1_usb_device*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_system:    2;  /*core_0_pif_pms_constrain_world_1_system*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_sensitive:    2;  /*core_0_pif_pms_constrain_world_1_sensitive*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_interrupt:    2;  /*core_0_pif_pms_constrain_world_1_interrupt*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_dma_copy:    2;  /*core_0_pif_pms_constrain_world_1_dma_copy*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_cache_config:    2;  /*core_0_pif_pms_constrain_world_1_cache_config*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_ad:    2;  /*core_0_pif_pms_constrain_world_1_ad*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_dio:    2;  /*core_0_pif_pms_constrain_world_1_dio*/
+            uint32_t reg_core_0_pif_pms_constrain_world_1_world_controller:    2;  /*core_0_pif_pms_constrain_world_1_world_controller*/
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_8;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:    11;  /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_0*/
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_spltaddr_world_1:    11;  /*core_0_pif_pms_constrain_rtcfast_spltaddr_world_1*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_9;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_l:    3;  /*core_0_pif_pms_constrain_rtcfast_world_0_l*/
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_0_h:    3;  /*core_0_pif_pms_constrain_rtcfast_world_0_h*/
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_l:    3;  /*core_0_pif_pms_constrain_rtcfast_world_1_l*/
+            uint32_t reg_core_0_pif_pms_constrain_rtcfast_world_1_h:    3;  /*core_0_pif_pms_constrain_rtcfast_world_1_h*/
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_10;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_lock :    1;  /*region_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_world_0_area_0:    2;  /*region_pms_constrain_world_0_area_0*/
+            uint32_t reg_region_pms_constrain_world_0_area_1:    2;  /*region_pms_constrain_world_0_area_1*/
+            uint32_t reg_region_pms_constrain_world_0_area_2:    2;  /*region_pms_constrain_world_0_area_2*/
+            uint32_t reg_region_pms_constrain_world_0_area_3:    2;  /*region_pms_constrain_world_0_area_3*/
+            uint32_t reg_region_pms_constrain_world_0_area_4:    2;  /*region_pms_constrain_world_0_area_4*/
+            uint32_t reg_region_pms_constrain_world_0_area_5:    2;  /*region_pms_constrain_world_0_area_5*/
+            uint32_t reg_region_pms_constrain_world_0_area_6:    2;  /*region_pms_constrain_world_0_area_6*/
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_world_1_area_0:    2;  /*region_pms_constrain_world_1_area_0*/
+            uint32_t reg_region_pms_constrain_world_1_area_1:    2;  /*region_pms_constrain_world_1_area_1*/
+            uint32_t reg_region_pms_constrain_world_1_area_2:    2;  /*region_pms_constrain_world_1_area_2*/
+            uint32_t reg_region_pms_constrain_world_1_area_3:    2;  /*region_pms_constrain_world_1_area_3*/
+            uint32_t reg_region_pms_constrain_world_1_area_4:    2;  /*region_pms_constrain_world_1_area_4*/
+            uint32_t reg_region_pms_constrain_world_1_area_5:    2;  /*region_pms_constrain_world_1_area_5*/
+            uint32_t reg_region_pms_constrain_world_1_area_6:    2;  /*region_pms_constrain_world_1_area_6*/
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_2;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_0:    30;  /*region_pms_constrain_addr_0*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_3;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_1:    30;  /*region_pms_constrain_addr_1*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_4;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_2:    30;  /*region_pms_constrain_addr_2*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_5;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_3:    30;  /*region_pms_constrain_addr_3*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_6;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_4:    30;  /*region_pms_constrain_addr_4*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_7;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_5:    30;  /*region_pms_constrain_addr_5*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_8;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_6:    30;  /*region_pms_constrain_addr_6*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_9;
+    union {
+        struct {
+            uint32_t reg_region_pms_constrain_addr_7:    30;  /*region_pms_constrain_addr_7*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } sensitiveion_pms_constrain_10;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_lock:    1;  /*core_0_pif_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_violate_clr:    1;  /*core_0_pif_pms_monitor_violate_clr*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_en:    1;  /*core_0_pif_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_violate_intr:    1;  /*core_0_pif_pms_monitor_violate_intr*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_status_hport_0:    1;  /*core_0_pif_pms_monitor_violate_status_hport_0*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_status_hsize:    3;  /*core_0_pif_pms_monitor_violate_status_hsize*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_status_hwrite:    1;  /*core_0_pif_pms_monitor_violate_status_hwrite*/
+            uint32_t reg_core_0_pif_pms_monitor_violate_status_hworld:    2;  /*core_0_pif_pms_monitor_violate_status_hworld*/
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_2;
+    uint32_t core_0_pif_pms_monitor_3;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_clr:    1;  /*core_0_pif_pms_monitor_nonword_violate_clr*/
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_en:    1;  /*core_0_pif_pms_monitor_nonword_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_4;
+    union {
+        struct {
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_intr:    1;  /*core_0_pif_pms_monitor_nonword_violate_intr*/
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hsize:    2;  /*core_0_pif_pms_monitor_nonword_violate_status_hsize*/
+            uint32_t reg_core_0_pif_pms_monitor_nonword_violate_status_hworld:    2;  /*core_0_pif_pms_monitor_nonword_violate_status_hworld*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_5;
+    uint32_t core_0_pif_pms_monitor_6;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_constrain_lock:    1;  /*backup_bus_pms_constrain_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_0;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_constrain_uart:    2;  /*backup_bus_pms_constrain_uart*/
+            uint32_t reg_backup_bus_pms_constrain_g0spi_1:    2;  /*backup_bus_pms_constrain_g0spi_1*/
+            uint32_t reg_backup_bus_pms_constrain_g0spi_0:    2;  /*backup_bus_pms_constrain_g0spi_0*/
+            uint32_t reg_backup_bus_pms_constrain_gpio:    2;  /*backup_bus_pms_constrain_gpio*/
+            uint32_t reg_backup_bus_pms_constrain_fe2:    2;  /*backup_bus_pms_constrain_fe2*/
+            uint32_t reg_backup_bus_pms_constrain_fe:    2;  /*backup_bus_pms_constrain_fe*/
+            uint32_t reg_backup_bus_pms_constrain_timer:    2;  /*backup_bus_pms_constrain_timer*/
+            uint32_t reg_backup_bus_pms_constrain_rtc:    2;  /*backup_bus_pms_constrain_rtc*/
+            uint32_t reg_backup_bus_pms_constrain_io_mux:    2;  /*backup_bus_pms_constrain_io_mux*/
+            uint32_t reg_backup_bus_pms_constrain_wdg:    2;  /*backup_bus_pms_constrain_wdg*/
+            uint32_t reserved20                    :    4;
+            uint32_t reg_backup_bus_pms_constrain_misc:    2;  /*backup_bus_pms_constrain_misc*/
+            uint32_t reg_backup_bus_pms_constrain_i2c:    2;  /*backup_bus_pms_constrain_i2c*/
+            uint32_t reserved28                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_uart1:    2;  /*backup_bus_pms_constrain_uart1*/
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_1;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_constrain_bt:    2;  /*backup_bus_pms_constrain_bt*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_backup_bus_pms_constrain_i2c_ext0:    2;  /*backup_bus_pms_constrain_i2c_ext0*/
+            uint32_t reg_backup_bus_pms_constrain_uhci0:    2;  /*backup_bus_pms_constrain_uhci0*/
+            uint32_t reserved8                     :    2;
+            uint32_t reg_backup_bus_pms_constrain_rmt:    2;  /*backup_bus_pms_constrain_rmt*/
+            uint32_t reserved12                    :    4;
+            uint32_t reg_backup_bus_pms_constrain_ledc:    2;  /*backup_bus_pms_constrain_ledc*/
+            uint32_t reserved18                    :    4;
+            uint32_t reg_backup_bus_pms_constrain_bb:    2;  /*backup_bus_pms_constrain_bb*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_timergroup:    2;  /*backup_bus_pms_constrain_timergroup*/
+            uint32_t reg_backup_bus_pms_constrain_timergroup1:    2;  /*backup_bus_pms_constrain_timergroup1*/
+            uint32_t reg_backup_bus_pms_constrain_systimer:    2;  /*backup_bus_pms_constrain_systimer*/
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_2;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_constrain_spi_2:    2;  /*backup_bus_pms_constrain_spi_2*/
+            uint32_t reserved2                     :    2;
+            uint32_t reg_backup_bus_pms_constrain_apb_ctrl:    2;  /*backup_bus_pms_constrain_apb_ctrl*/
+            uint32_t reserved6                     :    4;
+            uint32_t reg_backup_bus_pms_constrain_can:    2;  /*backup_bus_pms_constrain_can*/
+            uint32_t reserved12                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_i2s0:    2;  /*backup_bus_pms_constrain_i2s0*/
+            uint32_t reserved16                    :    6;
+            uint32_t reg_backup_bus_pms_constrain_rwbt:    2;  /*backup_bus_pms_constrain_rwbt*/
+            uint32_t reserved24                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_wifimac:    2;  /*backup_bus_pms_constrain_wifimac*/
+            uint32_t reg_backup_bus_pms_constrain_pwr:    2;  /*backup_bus_pms_constrain_pwr*/
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_3;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t reg_backup_bus_pms_constrain_usb_wrap:    2;  /*backup_bus_pms_constrain_usb_wrap*/
+            uint32_t reg_backup_bus_pms_constrain_crypto_peri:    2;  /*backup_bus_pms_constrain_crypto_peri*/
+            uint32_t reg_backup_bus_pms_constrain_crypto_dma:    2;  /*backup_bus_pms_constrain_crypto_dma*/
+            uint32_t reg_backup_bus_pms_constrain_apb_adc:    2;  /*backup_bus_pms_constrain_apb_adc*/
+            uint32_t reserved10                    :    2;
+            uint32_t reg_backup_bus_pms_constrain_bt_pwr:    2;  /*backup_bus_pms_constrain_bt_pwr*/
+            uint32_t reg_backup_bus_pms_constrain_usb_device:    2;  /*backup_bus_pms_constrain_usb_device*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_4;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_monitor_lock:    1;  /*backup_bus_pms_monitor_lock*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_0;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_monitor_violate_clr:    1;  /*backup_bus_pms_monitor_violate_clr*/
+            uint32_t reg_backup_bus_pms_monitor_violate_en:    1;  /*backup_bus_pms_monitor_violate_en*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_1;
+    union {
+        struct {
+            uint32_t reg_backup_bus_pms_monitor_violate_intr:    1;  /*backup_bus_pms_monitor_violate_intr*/
+            uint32_t reg_backup_bus_pms_monitor_violate_status_htrans:    2;  /*backup_bus_pms_monitor_violate_status_htrans*/
+            uint32_t reg_backup_bus_pms_monitor_violate_status_hsize:    3;  /*backup_bus_pms_monitor_violate_status_hsize*/
+            uint32_t reg_backup_bus_pms_monitor_violate_status_hwrite:    1;  /*backup_bus_pms_monitor_violate_status_hwrite*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_2;
+    uint32_t backup_bus_pms_monitor_3;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;  /*clk_en*/
+            uint32_t reserved1                     :    31;  /*SENSITIVE_CLOCK_GATE_REG_REG*/
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t reserved_800;
+    uint32_t reserved_804;
+    uint32_t reserved_808;
+    uint32_t reserved_80c;
+    uint32_t reserved_810;
+    uint32_t reserved_814;
+    uint32_t reserved_818;
+    uint32_t reserved_81c;
+    uint32_t reserved_820;
+    uint32_t reserved_824;
+    uint32_t reserved_828;
+    uint32_t reserved_82c;
+    uint32_t reserved_830;
+    uint32_t reserved_834;
+    uint32_t reserved_838;
+    uint32_t reserved_83c;
+    uint32_t reserved_840;
+    uint32_t reserved_844;
+    uint32_t reserved_848;
+    uint32_t reserved_84c;
+    uint32_t reserved_850;
+    uint32_t reserved_854;
+    uint32_t reserved_858;
+    uint32_t reserved_85c;
+    uint32_t reserved_860;
+    uint32_t reserved_864;
+    uint32_t reserved_868;
+    uint32_t reserved_86c;
+    uint32_t reserved_870;
+    uint32_t reserved_874;
+    uint32_t reserved_878;
+    uint32_t reserved_87c;
+    uint32_t reserved_880;
+    uint32_t reserved_884;
+    uint32_t reserved_888;
+    uint32_t reserved_88c;
+    uint32_t reserved_890;
+    uint32_t reserved_894;
+    uint32_t reserved_898;
+    uint32_t reserved_89c;
+    uint32_t reserved_8a0;
+    uint32_t reserved_8a4;
+    uint32_t reserved_8a8;
+    uint32_t reserved_8ac;
+    uint32_t reserved_8b0;
+    uint32_t reserved_8b4;
+    uint32_t reserved_8b8;
+    uint32_t reserved_8bc;
+    uint32_t reserved_8c0;
+    uint32_t reserved_8c4;
+    uint32_t reserved_8c8;
+    uint32_t reserved_8cc;
+    uint32_t reserved_8d0;
+    uint32_t reserved_8d4;
+    uint32_t reserved_8d8;
+    uint32_t reserved_8dc;
+    uint32_t reserved_8e0;
+    uint32_t reserved_8e4;
+    uint32_t reserved_8e8;
+    uint32_t reserved_8ec;
+    uint32_t reserved_8f0;
+    uint32_t reserved_8f4;
+    uint32_t reserved_8f8;
+    uint32_t reserved_8fc;
+    uint32_t reserved_900;
+    uint32_t reserved_904;
+    uint32_t reserved_908;
+    uint32_t reserved_90c;
+    uint32_t reserved_910;
+    uint32_t reserved_914;
+    uint32_t reserved_918;
+    uint32_t reserved_91c;
+    uint32_t reserved_920;
+    uint32_t reserved_924;
+    uint32_t reserved_928;
+    uint32_t reserved_92c;
+    uint32_t reserved_930;
+    uint32_t reserved_934;
+    uint32_t reserved_938;
+    uint32_t reserved_93c;
+    uint32_t reserved_940;
+    uint32_t reserved_944;
+    uint32_t reserved_948;
+    uint32_t reserved_94c;
+    uint32_t reserved_950;
+    uint32_t reserved_954;
+    uint32_t reserved_958;
+    uint32_t reserved_95c;
+    uint32_t reserved_960;
+    uint32_t reserved_964;
+    uint32_t reserved_968;
+    uint32_t reserved_96c;
+    uint32_t reserved_970;
+    uint32_t reserved_974;
+    uint32_t reserved_978;
+    uint32_t reserved_97c;
+    uint32_t reserved_980;
+    uint32_t reserved_984;
+    uint32_t reserved_988;
+    uint32_t reserved_98c;
+    uint32_t reserved_990;
+    uint32_t reserved_994;
+    uint32_t reserved_998;
+    uint32_t reserved_99c;
+    uint32_t reserved_9a0;
+    uint32_t reserved_9a4;
+    uint32_t reserved_9a8;
+    uint32_t reserved_9ac;
+    uint32_t reserved_9b0;
+    uint32_t reserved_9b4;
+    uint32_t reserved_9b8;
+    uint32_t reserved_9bc;
+    uint32_t reserved_9c0;
+    uint32_t reserved_9c4;
+    uint32_t reserved_9c8;
+    uint32_t reserved_9cc;
+    uint32_t reserved_9d0;
+    uint32_t reserved_9d4;
+    uint32_t reserved_9d8;
+    uint32_t reserved_9dc;
+    uint32_t reserved_9e0;
+    uint32_t reserved_9e4;
+    uint32_t reserved_9e8;
+    uint32_t reserved_9ec;
+    uint32_t reserved_9f0;
+    uint32_t reserved_9f4;
+    uint32_t reserved_9f8;
+    uint32_t reserved_9fc;
+    uint32_t reserved_a00;
+    uint32_t reserved_a04;
+    uint32_t reserved_a08;
+    uint32_t reserved_a0c;
+    uint32_t reserved_a10;
+    uint32_t reserved_a14;
+    uint32_t reserved_a18;
+    uint32_t reserved_a1c;
+    uint32_t reserved_a20;
+    uint32_t reserved_a24;
+    uint32_t reserved_a28;
+    uint32_t reserved_a2c;
+    uint32_t reserved_a30;
+    uint32_t reserved_a34;
+    uint32_t reserved_a38;
+    uint32_t reserved_a3c;
+    uint32_t reserved_a40;
+    uint32_t reserved_a44;
+    uint32_t reserved_a48;
+    uint32_t reserved_a4c;
+    uint32_t reserved_a50;
+    uint32_t reserved_a54;
+    uint32_t reserved_a58;
+    uint32_t reserved_a5c;
+    uint32_t reserved_a60;
+    uint32_t reserved_a64;
+    uint32_t reserved_a68;
+    uint32_t reserved_a6c;
+    uint32_t reserved_a70;
+    uint32_t reserved_a74;
+    uint32_t reserved_a78;
+    uint32_t reserved_a7c;
+    uint32_t reserved_a80;
+    uint32_t reserved_a84;
+    uint32_t reserved_a88;
+    uint32_t reserved_a8c;
+    uint32_t reserved_a90;
+    uint32_t reserved_a94;
+    uint32_t reserved_a98;
+    uint32_t reserved_a9c;
+    uint32_t reserved_aa0;
+    uint32_t reserved_aa4;
+    uint32_t reserved_aa8;
+    uint32_t reserved_aac;
+    uint32_t reserved_ab0;
+    uint32_t reserved_ab4;
+    uint32_t reserved_ab8;
+    uint32_t reserved_abc;
+    uint32_t reserved_ac0;
+    uint32_t reserved_ac4;
+    uint32_t reserved_ac8;
+    uint32_t reserved_acc;
+    uint32_t reserved_ad0;
+    uint32_t reserved_ad4;
+    uint32_t reserved_ad8;
+    uint32_t reserved_adc;
+    uint32_t reserved_ae0;
+    uint32_t reserved_ae4;
+    uint32_t reserved_ae8;
+    uint32_t reserved_aec;
+    uint32_t reserved_af0;
+    uint32_t reserved_af4;
+    uint32_t reserved_af8;
+    uint32_t reserved_afc;
+    uint32_t reserved_b00;
+    uint32_t reserved_b04;
+    uint32_t reserved_b08;
+    uint32_t reserved_b0c;
+    uint32_t reserved_b10;
+    uint32_t reserved_b14;
+    uint32_t reserved_b18;
+    uint32_t reserved_b1c;
+    uint32_t reserved_b20;
+    uint32_t reserved_b24;
+    uint32_t reserved_b28;
+    uint32_t reserved_b2c;
+    uint32_t reserved_b30;
+    uint32_t reserved_b34;
+    uint32_t reserved_b38;
+    uint32_t reserved_b3c;
+    uint32_t reserved_b40;
+    uint32_t reserved_b44;
+    uint32_t reserved_b48;
+    uint32_t reserved_b4c;
+    uint32_t reserved_b50;
+    uint32_t reserved_b54;
+    uint32_t reserved_b58;
+    uint32_t reserved_b5c;
+    uint32_t reserved_b60;
+    uint32_t reserved_b64;
+    uint32_t reserved_b68;
+    uint32_t reserved_b6c;
+    uint32_t reserved_b70;
+    uint32_t reserved_b74;
+    uint32_t reserved_b78;
+    uint32_t reserved_b7c;
+    uint32_t reserved_b80;
+    uint32_t reserved_b84;
+    uint32_t reserved_b88;
+    uint32_t reserved_b8c;
+    uint32_t reserved_b90;
+    uint32_t reserved_b94;
+    uint32_t reserved_b98;
+    uint32_t reserved_b9c;
+    uint32_t reserved_ba0;
+    uint32_t reserved_ba4;
+    uint32_t reserved_ba8;
+    uint32_t reserved_bac;
+    uint32_t reserved_bb0;
+    uint32_t reserved_bb4;
+    uint32_t reserved_bb8;
+    uint32_t reserved_bbc;
+    uint32_t reserved_bc0;
+    uint32_t reserved_bc4;
+    uint32_t reserved_bc8;
+    uint32_t reserved_bcc;
+    uint32_t reserved_bd0;
+    uint32_t reserved_bd4;
+    uint32_t reserved_bd8;
+    uint32_t reserved_bdc;
+    uint32_t reserved_be0;
+    uint32_t reserved_be4;
+    uint32_t reserved_be8;
+    uint32_t reserved_bec;
+    uint32_t reserved_bf0;
+    uint32_t reserved_bf4;
+    uint32_t reserved_bf8;
+    uint32_t reserved_bfc;
+    uint32_t reserved_c00;
+    uint32_t reserved_c04;
+    uint32_t reserved_c08;
+    uint32_t reserved_c0c;
+    uint32_t reserved_c10;
+    uint32_t reserved_c14;
+    uint32_t reserved_c18;
+    uint32_t reserved_c1c;
+    uint32_t reserved_c20;
+    uint32_t reserved_c24;
+    uint32_t reserved_c28;
+    uint32_t reserved_c2c;
+    uint32_t reserved_c30;
+    uint32_t reserved_c34;
+    uint32_t reserved_c38;
+    uint32_t reserved_c3c;
+    uint32_t reserved_c40;
+    uint32_t reserved_c44;
+    uint32_t reserved_c48;
+    uint32_t reserved_c4c;
+    uint32_t reserved_c50;
+    uint32_t reserved_c54;
+    uint32_t reserved_c58;
+    uint32_t reserved_c5c;
+    uint32_t reserved_c60;
+    uint32_t reserved_c64;
+    uint32_t reserved_c68;
+    uint32_t reserved_c6c;
+    uint32_t reserved_c70;
+    uint32_t reserved_c74;
+    uint32_t reserved_c78;
+    uint32_t reserved_c7c;
+    uint32_t reserved_c80;
+    uint32_t reserved_c84;
+    uint32_t reserved_c88;
+    uint32_t reserved_c8c;
+    uint32_t reserved_c90;
+    uint32_t reserved_c94;
+    uint32_t reserved_c98;
+    uint32_t reserved_c9c;
+    uint32_t reserved_ca0;
+    uint32_t reserved_ca4;
+    uint32_t reserved_ca8;
+    uint32_t reserved_cac;
+    uint32_t reserved_cb0;
+    uint32_t reserved_cb4;
+    uint32_t reserved_cb8;
+    uint32_t reserved_cbc;
+    uint32_t reserved_cc0;
+    uint32_t reserved_cc4;
+    uint32_t reserved_cc8;
+    uint32_t reserved_ccc;
+    uint32_t reserved_cd0;
+    uint32_t reserved_cd4;
+    uint32_t reserved_cd8;
+    uint32_t reserved_cdc;
+    uint32_t reserved_ce0;
+    uint32_t reserved_ce4;
+    uint32_t reserved_ce8;
+    uint32_t reserved_cec;
+    uint32_t reserved_cf0;
+    uint32_t reserved_cf4;
+    uint32_t reserved_cf8;
+    uint32_t reserved_cfc;
+    uint32_t reserved_d00;
+    uint32_t reserved_d04;
+    uint32_t reserved_d08;
+    uint32_t reserved_d0c;
+    uint32_t reserved_d10;
+    uint32_t reserved_d14;
+    uint32_t reserved_d18;
+    uint32_t reserved_d1c;
+    uint32_t reserved_d20;
+    uint32_t reserved_d24;
+    uint32_t reserved_d28;
+    uint32_t reserved_d2c;
+    uint32_t reserved_d30;
+    uint32_t reserved_d34;
+    uint32_t reserved_d38;
+    uint32_t reserved_d3c;
+    uint32_t reserved_d40;
+    uint32_t reserved_d44;
+    uint32_t reserved_d48;
+    uint32_t reserved_d4c;
+    uint32_t reserved_d50;
+    uint32_t reserved_d54;
+    uint32_t reserved_d58;
+    uint32_t reserved_d5c;
+    uint32_t reserved_d60;
+    uint32_t reserved_d64;
+    uint32_t reserved_d68;
+    uint32_t reserved_d6c;
+    uint32_t reserved_d70;
+    uint32_t reserved_d74;
+    uint32_t reserved_d78;
+    uint32_t reserved_d7c;
+    uint32_t reserved_d80;
+    uint32_t reserved_d84;
+    uint32_t reserved_d88;
+    uint32_t reserved_d8c;
+    uint32_t reserved_d90;
+    uint32_t reserved_d94;
+    uint32_t reserved_d98;
+    uint32_t reserved_d9c;
+    uint32_t reserved_da0;
+    uint32_t reserved_da4;
+    uint32_t reserved_da8;
+    uint32_t reserved_dac;
+    uint32_t reserved_db0;
+    uint32_t reserved_db4;
+    uint32_t reserved_db8;
+    uint32_t reserved_dbc;
+    uint32_t reserved_dc0;
+    uint32_t reserved_dc4;
+    uint32_t reserved_dc8;
+    uint32_t reserved_dcc;
+    uint32_t reserved_dd0;
+    uint32_t reserved_dd4;
+    uint32_t reserved_dd8;
+    uint32_t reserved_ddc;
+    uint32_t reserved_de0;
+    uint32_t reserved_de4;
+    uint32_t reserved_de8;
+    uint32_t reserved_dec;
+    uint32_t reserved_df0;
+    uint32_t reserved_df4;
+    uint32_t reserved_df8;
+    uint32_t reserved_dfc;
+    uint32_t reserved_e00;
+    uint32_t reserved_e04;
+    uint32_t reserved_e08;
+    uint32_t reserved_e0c;
+    uint32_t reserved_e10;
+    uint32_t reserved_e14;
+    uint32_t reserved_e18;
+    uint32_t reserved_e1c;
+    uint32_t reserved_e20;
+    uint32_t reserved_e24;
+    uint32_t reserved_e28;
+    uint32_t reserved_e2c;
+    uint32_t reserved_e30;
+    uint32_t reserved_e34;
+    uint32_t reserved_e38;
+    uint32_t reserved_e3c;
+    uint32_t reserved_e40;
+    uint32_t reserved_e44;
+    uint32_t reserved_e48;
+    uint32_t reserved_e4c;
+    uint32_t reserved_e50;
+    uint32_t reserved_e54;
+    uint32_t reserved_e58;
+    uint32_t reserved_e5c;
+    uint32_t reserved_e60;
+    uint32_t reserved_e64;
+    uint32_t reserved_e68;
+    uint32_t reserved_e6c;
+    uint32_t reserved_e70;
+    uint32_t reserved_e74;
+    uint32_t reserved_e78;
+    uint32_t reserved_e7c;
+    uint32_t reserved_e80;
+    uint32_t reserved_e84;
+    uint32_t reserved_e88;
+    uint32_t reserved_e8c;
+    uint32_t reserved_e90;
+    uint32_t reserved_e94;
+    uint32_t reserved_e98;
+    uint32_t reserved_e9c;
+    uint32_t reserved_ea0;
+    uint32_t reserved_ea4;
+    uint32_t reserved_ea8;
+    uint32_t reserved_eac;
+    uint32_t reserved_eb0;
+    uint32_t reserved_eb4;
+    uint32_t reserved_eb8;
+    uint32_t reserved_ebc;
+    uint32_t reserved_ec0;
+    uint32_t reserved_ec4;
+    uint32_t reserved_ec8;
+    uint32_t reserved_ecc;
+    uint32_t reserved_ed0;
+    uint32_t reserved_ed4;
+    uint32_t reserved_ed8;
+    uint32_t reserved_edc;
+    uint32_t reserved_ee0;
+    uint32_t reserved_ee4;
+    uint32_t reserved_ee8;
+    uint32_t reserved_eec;
+    uint32_t reserved_ef0;
+    uint32_t reserved_ef4;
+    uint32_t reserved_ef8;
+    uint32_t reserved_efc;
+    uint32_t reserved_f00;
+    uint32_t reserved_f04;
+    uint32_t reserved_f08;
+    uint32_t reserved_f0c;
+    uint32_t reserved_f10;
+    uint32_t reserved_f14;
+    uint32_t reserved_f18;
+    uint32_t reserved_f1c;
+    uint32_t reserved_f20;
+    uint32_t reserved_f24;
+    uint32_t reserved_f28;
+    uint32_t reserved_f2c;
+    uint32_t reserved_f30;
+    uint32_t reserved_f34;
+    uint32_t reserved_f38;
+    uint32_t reserved_f3c;
+    uint32_t reserved_f40;
+    uint32_t reserved_f44;
+    uint32_t reserved_f48;
+    uint32_t reserved_f4c;
+    uint32_t reserved_f50;
+    uint32_t reserved_f54;
+    uint32_t reserved_f58;
+    uint32_t reserved_f5c;
+    uint32_t reserved_f60;
+    uint32_t reserved_f64;
+    uint32_t reserved_f68;
+    uint32_t reserved_f6c;
+    uint32_t reserved_f70;
+    uint32_t reserved_f74;
+    uint32_t reserved_f78;
+    uint32_t reserved_f7c;
+    uint32_t reserved_f80;
+    uint32_t reserved_f84;
+    uint32_t reserved_f88;
+    uint32_t reserved_f8c;
+    uint32_t reserved_f90;
+    uint32_t reserved_f94;
+    uint32_t reserved_f98;
+    uint32_t reserved_f9c;
+    uint32_t reserved_fa0;
+    uint32_t reserved_fa4;
+    uint32_t reserved_fa8;
+    uint32_t reserved_fac;
+    uint32_t reserved_fb0;
+    uint32_t reserved_fb4;
+    uint32_t reserved_fb8;
+    uint32_t reserved_fbc;
+    uint32_t reserved_fc0;
+    uint32_t reserved_fc4;
+    uint32_t reserved_fc8;
+    uint32_t reserved_fcc;
+    uint32_t reserved_fd0;
+    uint32_t reserved_fd4;
+    uint32_t reserved_fd8;
+    uint32_t reserved_fdc;
+    uint32_t reserved_fe0;
+    uint32_t reserved_fe4;
+    uint32_t reserved_fe8;
+    uint32_t reserved_fec;
+    uint32_t reserved_ff0;
+    uint32_t reserved_ff4;
+    uint32_t reserved_ff8;
+    union {
+        struct {
+            uint32_t reg_date                      :    28;  /*reg_date*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } date;
+} sensitive_dev_t;
+extern sensitive_dev_t SENSITIVE;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_STRUCT_H_ */
diff --git a/components/soc/esp32c3/register/soc/spi_mem_reg.h b/components/soc/esp32c3/register/soc/spi_mem_reg.h
new file mode 100644
index 00000000000..22d6b26377e
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/spi_mem_reg.h
@@ -0,0 +1,1212 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_MEM_REG_H_
+#define _SOC_SPI_MEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x000)
+/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_READ  (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the
+ bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WREN  (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WRDI  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is
+ set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RDID  (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RDSR  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WRSR  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed).
+ Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PP  (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_SE  (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_BE  (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_CE  (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_DP  (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from
+ the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RES  (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared
+ once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_HPM  (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_USR  (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode  it is set to indicate that program/erase operation
+ will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PE  (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state
+  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
+#define SPI_MEM_SLV_ST  0x0000000F
+#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
+#define SPI_MEM_SLV_ST_V  0xF
+#define SPI_MEM_SLV_ST_S  4
+/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The current status of SPI1 master FSM.*/
+#define SPI_MEM_MST_ST  0x0000000F
+#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
+#define SPI_MEM_MST_ST_V  0xF
+#define SPI_MEM_MST_ST_S  0
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x004)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode  it is the memory address. other then the bit0-bit23
+ is the memory address  the bit24-bit31 are the byte length of a transfer.*/
+#define SPI_MEM_USR_ADDR_VALUE  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x008)
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply
+ 4 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_QIO  (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply
+ 2 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_DIO  (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is
+ set. 1: enable 0: disable.*/
+#define SPI_MEM_WRSR_2B  (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high  0: output low.*/
+#define SPI_MEM_WP_REG  (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_QUAD  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity  1: high 0  low*/
+#define SPI_MEM_D_POL  (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity  1: high 0  low*/
+#define SPI_MEM_Q_POL  (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register   this
+ bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
+#define SPI_MEM_RESANDRES  (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_DUAL  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: spi_mem_fread_qio  spi_mem_fread_dio
+  spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
+#define SPI_MEM_FASTRD_MODE  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1   enable crc32 when writing encrypted data to flash.
+ 1: enable 0:disable*/
+#define SPI_MEM_TX_CRC_EN  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1   initialize crc32 module before writing encrypted data
+ to flash. Active low.*/
+#define SPI_MEM_FCS_CRC_EN  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable*/
+#define SPI_MEM_FCMD_QUAD  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable*/
+#define SPI_MEM_FCMD_DUAL  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_V  0x1
+#define SPI_MEM_FCMD_DUAL_S  7
+/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the dummy phase the signal level of spi is output by the spi controller.*/
+#define SPI_MEM_FDUMMY_OUT  (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_V  0x1
+#define SPI_MEM_FDUMMY_OUT_S  3
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x00C)
+/* SPI_MEM_RXFIFO_WFULL_ERR : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SPI0 RX FIFO write full error  Cache/EDMA do not read all
+ the data out. 0: Not error.*/
+#define SPI_MEM_RXFIFO_WFULL_ERR  (BIT(31))
+#define SPI_MEM_RXFIFO_WFULL_ERR_M  (BIT(31))
+#define SPI_MEM_RXFIFO_WFULL_ERR_V  0x1
+#define SPI_MEM_RXFIFO_WFULL_ERR_S  31
+/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI0 RX FIFO reset signal.*/
+#define SPI_MEM_RXFIFO_RST  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_V  0x1
+#define SPI_MEM_RXFIFO_RST_S  30
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
+/*description: After RES/DP/HPM command is sent  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 512) SPI_CLK cycles.*/
+#define SPI_MEM_CS_HOLD_DLY_RES  0x000003FF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
+ SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
+#define SPI_MEM_CLK_MODE  0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x010)
+/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The FSM will be reset.*/
+#define SPI_MEM_SYNC_RESET  (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between
+ SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+#define SPI_MEM_CS_HOLD_DELAY  0x0000003F
+#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: Spi cs signal is delayed to inactive by spi clock this bits are
+ combined with spi_mem_cs_hold bit.*/
+#define SPI_MEM_CS_HOLD_TIME  0x0000001F
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_CS_HOLD_TIME_S  5
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of prepare phase by spi clock this bits are combined
+ with spi_mem_cs_setup bit.*/
+#define SPI_MEM_CS_SETUP_TIME  0x0000001F
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x014)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit in 1-division mode.reserved for spi1*/
+#define SPI_MEM_CLK_EQU_SYSCLK  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk
+ frequency is system/(spi_mem_clkcnt_N+1)*/
+#define SPI_MEM_CLKCNT_N  0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+#define SPI_MEM_CLKCNT_H  0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N.*/
+#define SPI_MEM_CLKCNT_L  0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x018)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation.*/
+#define SPI_MEM_USR_COMMAND  (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation.*/
+#define SPI_MEM_USR_ADDR  (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation.*/
+#define SPI_MEM_USR_DUMMY  (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation.*/
+#define SPI_MEM_USR_MISO  (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation.*/
+#define SPI_MEM_USR_MOSI  (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable.*/
+#define SPI_MEM_USR_DUMMY_IDLE  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+ 1: enable 0: disable.*/
+#define SPI_MEM_USR_MOSI_HIGHPART  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+ 1: enable 0: disable.*/
+#define SPI_MEM_USR_MISO_HIGHPART  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals.*/
+#define SPI_MEM_FWRITE_QIO  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals.*/
+#define SPI_MEM_FWRITE_DIO  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals*/
+#define SPI_MEM_FWRITE_QUAD  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals*/
+#define SPI_MEM_FWRITE_DUAL  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi
+ signal delay mode.*/
+#define SPI_MEM_CK_OUT_EDGE  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
+#define SPI_MEM_CS_SETUP  (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
+#define SPI_MEM_CS_HOLD  (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x01C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_ADDR_BITLEN  0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register
+ value shall be (cycle_num-1).*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN  0x0000003F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x020)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/
+#define SPI_MEM_USR_COMMAND_BITLEN  0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command.*/
+#define SPI_MEM_USR_COMMAND_VALUE  0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x024)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_MOSI_DBITLEN  0x000003FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x028)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_MISO_DBITLEN  0x000003FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x02C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode
+ bit.*/
+#define SPI_MEM_WB_MODE  0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+#define SPI_MEM_STATUS  0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x034)
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set.*/
+#define SPI_MEM_CS_KEEP_ACTIVE  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle*/
+#define SPI_MEM_CK_IDLE_EDGE  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_SLV_ST_TRANS_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of spi0_slv_st controlled
+ transmitting is done.*/
+#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA  (BIT(6))
+#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_M  (BIT(6))
+#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_TRANS_END_INT_ENA_S  6
+/* SPI_MEM_SLV_ST_TRANS_END : R/W/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
+#define SPI_MEM_SLV_ST_TRANS_END  (BIT(5))
+#define SPI_MEM_SLV_ST_TRANS_END_M  (BIT(5))
+#define SPI_MEM_SLV_ST_TRANS_END_V  0x1
+#define SPI_MEM_SLV_ST_TRANS_END_S  5
+/* SPI_MEM_CSPI_ST_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of SPI0 cspi_st controlled
+ transmitting is done.*/
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA  (BIT(4))
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_CSPI_ST_TRANS_END_INT_ENA_S  4
+/* SPI_MEM_CSPI_ST_TRANS_END : R/W/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the SPI0 cspi_st controlled transmitting is done.*/
+#define SPI_MEM_CSPI_ST_TRANS_END  (BIT(3))
+#define SPI_MEM_CSPI_ST_TRANS_END_M  (BIT(3))
+#define SPI_MEM_CSPI_ST_TRANS_END_V  0x1
+#define SPI_MEM_CSPI_ST_TRANS_END_S  3
+/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt of SPI0 em_st controlled
+ transmitting is done.*/
+#define SPI_MEM_TRANS_END_INT_ENA  (BIT(2))
+#define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_TRANS_END_INT_ENA_S  2
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI_CS1 pin enable  1: disable SPI_CS1  0: SPI_CS1 pin is active
+ to select SPI device  such as flash  external RAM and so on.*/
+#define SPI_MEM_CS1_DIS  (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI_CS0 pin enable  1: disable SPI_CS0  0: SPI_CS0 pin is active
+ to select SPI device  such as flash  external RAM and so on.*/
+#define SPI_MEM_CS0_DIS  (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x038)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: For SPI1  the value of crc32.*/
+#define SPI_MEM_TX_CRC_DATA  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x03C)
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI1  address phase apply 4 signals. 1: enable 0: disable.
+  The bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FADDR_QUAD  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI1  dout phase apply 4 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FDOUT_QUAD  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI1  din phase apply 4 signals. 1: enable 0: disable.  The
+ bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FDIN_QUAD  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI1  address phase apply 2 signals. 1: enable 0: disable.
+  The bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FADDR_DUAL  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI1  dout phase apply 2 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FDOUT_DUAL  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI1  din phase apply 2 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FDIN_DUAL  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0   cache  read flash for user define command  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0   cache  read flash with 4 bytes address  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
+/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0  Cache access enable  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_REQ_EN  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_V  0x1
+#define SPI_MEM_CACHE_REQ_EN_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x054)
+/* SPI_MEM_CSPI_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
+/*description: The lock delay time of SPI0/1 arbiter by cspi_st  after PER is sent by SPI1.*/
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME  0x0000001F
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_M  ((SPI_MEM_CSPI_LOCK_DELAY_TIME_V)<<(SPI_MEM_CSPI_LOCK_DELAY_TIME_S))
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_V  0x1F
+#define SPI_MEM_CSPI_LOCK_DELAY_TIME_S  7
+/* SPI_MEM_EM_ST : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: The current status of SPI0 master FSM: cspi_st. 0: idle state
+  1:EM_CACHE_GRANT   2: program/erase suspend state  3: SPI0 read data state  4: wait cache/EDMA sent data is stored in SPI0 TX FIFO  5: SPI0 write data state.*/
+#define SPI_MEM_EM_ST  0x00000007
+#define SPI_MEM_EM_ST_M  ((SPI_MEM_EM_ST_V)<<(SPI_MEM_EM_ST_S))
+#define SPI_MEM_EM_ST_V  0x7
+#define SPI_MEM_EM_ST_S  4
+/* SPI_MEM_CSPI_ST : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: The current status of SPI0 slave FSM: cspi_st. 0: idle state
+  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
+#define SPI_MEM_CSPI_ST  0x0000000F
+#define SPI_MEM_CSPI_ST_M  ((SPI_MEM_CSPI_ST_V)<<(SPI_MEM_CSPI_ST_S))
+#define SPI_MEM_CSPI_ST_V  0xF
+#define SPI_MEM_CSPI_ST_S  0
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x058)
+/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF0  0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x05C)
+/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF1  0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x060)
+/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF2  0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x064)
+/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF3  0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x068)
+/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF4  0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x06C)
+/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF5  0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x070)
+/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF6  0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x074)
+/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF7  0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x078)
+/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF8  0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x07C)
+/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF9  0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x080)
+/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF10  0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x084)
+/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF11  0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x088)
+/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF12  0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x08C)
+/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF13  0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x090)
+/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF14  0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x094)
+/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF15  0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x098)
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: The dummy cycle length when wait flash idle(RDSR).*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN  0x0000003F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
+/*description: The command to wait flash idle(RDSR).*/
+#define SPI_MEM_WAITI_CMD  0x000000FF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFF
+#define SPI_MEM_WAITI_CMD_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The dummy phase enable when wait flash idle (RDSR)*/
+#define SPI_MEM_WAITI_DUMMY  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x09C)
+/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
+/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0]
+ times  it will be treated as check pass.*/
+#define SPI_MEM_SUS_TIMEOUT_CNT  0x0000007F
+#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
+#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
+#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure
+ the suspend status of flash. 0: Only need to check WIP is 0.*/
+#define SPI_MEM_PES_END_EN  (BIT(24))
+#define SPI_MEM_PES_END_EN_M  (BIT(24))
+#define SPI_MEM_PES_END_EN_V  0x1
+#define SPI_MEM_PES_END_EN_S  24
+/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure
+ the resume status of flash. 0: Only need to check WIP is 0.*/
+#define SPI_MEM_PER_END_EN  (BIT(23))
+#define SPI_MEM_PER_END_EN_M  (BIT(23))
+#define SPI_MEM_PER_END_EN_V  0x1
+#define SPI_MEM_PER_END_EN_S  23
+/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit.
+ 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+#define SPI_MEM_FMEM_RD_SUS_2B  (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
+#define SPI_MEM_FMEM_RD_SUS_2B_S  22
+/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
+/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read
+ status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out  status_in[15:0] is valid when two bytes of data are read out)  SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+#define SPI_MEM_PESR_END_MSK  0x0000FFFF
+#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
+#define SPI_MEM_PESR_END_MSK_V  0xFFFF
+#define SPI_MEM_PESR_END_MSK_S  6
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable Auto-suspending function.*/
+#define SPI_MEM_FLASH_PES_EN  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  5
+/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable PES transfer trigger PES transfer option.
+ If this bit is 0  application should send PER after PES is done.*/
+#define SPI_MEM_PES_PER_EN  (BIT(4))
+#define SPI_MEM_PES_PER_EN_M  (BIT(4))
+#define SPI_MEM_PES_PER_EN_V  0x1
+#define SPI_MEM_PES_PER_EN_S  4
+/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 4) SPI_CLK cycles after program erase suspend.*/
+#define SPI_MEM_FLASH_PES_WAIT_EN  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
+/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 4) SPI_CLK cycles after program erase resume.*/
+#define SPI_MEM_FLASH_PER_WAIT_EN  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
+/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit  program erase suspend operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PES  (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit  program erase suspend operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PER  (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A0)
+/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should
+ be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+#define SPI_MEM_WAIT_PESR_COMMAND  0x0000FFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
+#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:8] ;default: 8'h75 ; */
+/*description: Program/Erase suspend command.*/
+#define SPI_MEM_FLASH_PES_COMMAND  0x000000FF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  8
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[7:0] ;default: 8'h7a ; */
+/*description: Program/Erase resume command.*/
+#define SPI_MEM_FLASH_PER_COMMAND  0x000000FF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A4)
+/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
+#define SPI_MEM_SPI0_LOCK_EN  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_V  0x1
+#define SPI_MEM_SPI0_LOCK_EN_S  7
+/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
+#define SPI_MEM_FLASH_PES_DLY_128  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PES_DLY_128_S  6
+/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0]
+ * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
+#define SPI_MEM_FLASH_PER_DLY_128  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PER_DLY_128_S  5
+/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
+ cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
+#define SPI_MEM_FLASH_DP_DLY_128  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
+#define SPI_MEM_FLASH_DP_DLY_128_S  4
+/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
+ cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
+#define SPI_MEM_FLASH_RES_DLY_128  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_RES_DLY_128_S  3
+/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK
+ cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
+#define SPI_MEM_FLASH_HPM_DLY_128  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
+#define SPI_MEM_FLASH_HPM_DLY_128_S  2
+/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2
+ bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
+#define SPI_MEM_WAIT_PESR_CMD_2B  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
+#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
+/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend  only used in SPI1.*/
+#define SPI_MEM_FLASH_SUS  (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A8)
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration.*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN  0x00000007
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations.*/
+#define SPI_MEM_TIMING_CALI  (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations.*/
+#define SPI_MEM_TIMING_CLK_ENA  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0AC)
+/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN3_MODE  0x00000003
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x3
+#define SPI_MEM_DIN3_MODE_S  6
+/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN2_MODE  0x00000003
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x3
+#define SPI_MEM_DIN2_MODE_S  4
+/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN1_MODE  0x00000003
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x3
+#define SPI_MEM_DIN1_MODE_S  2
+/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN0_MODE  0x00000003
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x3
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B0)
+/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN3_NUM  0x00000003
+#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
+#define SPI_MEM_DIN3_NUM_V  0x3
+#define SPI_MEM_DIN3_NUM_S  6
+/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN2_NUM  0x00000003
+#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
+#define SPI_MEM_DIN2_NUM_V  0x3
+#define SPI_MEM_DIN2_NUM_S  4
+/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN1_NUM  0x00000003
+#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
+#define SPI_MEM_DIN1_NUM_V  0x3
+#define SPI_MEM_DIN1_NUM_S  2
+/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN0_NUM  0x00000003
+#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
+#define SPI_MEM_DIN0_NUM_V  0x3
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B4)
+/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT3_MODE  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_DOUT3_MODE_S  3
+/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT2_MODE  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_DOUT2_MODE_S  2
+/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT1_MODE  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_DOUT1_MODE_S  1
+/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT0_MODE  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C0)
+/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+#define SPI_MEM_MST_ST_END_INT_ENA  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ENA_S  4
+/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+#define SPI_MEM_SLV_ST_END_INT_ENA  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
+/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+#define SPI_MEM_WPE_END_INT_ENA  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_V  0x1
+#define SPI_MEM_WPE_END_INT_ENA_S  2
+/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+#define SPI_MEM_PES_END_INT_ENA  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_V  0x1
+#define SPI_MEM_PES_END_INT_ENA_S  1
+/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+#define SPI_MEM_PER_END_INT_ENA  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_V  0x1
+#define SPI_MEM_PER_END_INT_ENA_S  0
+
+#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C4)
+/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+#define SPI_MEM_MST_ST_END_INT_CLR  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_MST_ST_END_INT_CLR_S  4
+/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+#define SPI_MEM_SLV_ST_END_INT_CLR  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
+/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+#define SPI_MEM_WPE_END_INT_CLR  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_V  0x1
+#define SPI_MEM_WPE_END_INT_CLR_S  2
+/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+#define SPI_MEM_PES_END_INT_CLR  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_V  0x1
+#define SPI_MEM_PES_END_INT_CLR_S  1
+/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+#define SPI_MEM_PER_END_INT_CLR  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_V  0x1
+#define SPI_MEM_PER_END_INT_CLR_S  0
+
+#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C8)
+/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered
+ when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
+#define SPI_MEM_MST_ST_END_INT_RAW  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_MST_ST_END_INT_RAW_S  4
+/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered
+ when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+#define SPI_MEM_SLV_ST_END_INT_RAW  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
+/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when
+ WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+#define SPI_MEM_WPE_END_INT_RAW  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_V  0x1
+#define SPI_MEM_WPE_END_INT_RAW_S  2
+/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when
+ Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
+#define SPI_MEM_PES_END_INT_RAW  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_V  0x1
+#define SPI_MEM_PES_END_INT_RAW_S  1
+/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when
+ Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
+#define SPI_MEM_PER_END_INT_RAW  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_V  0x1
+#define SPI_MEM_PER_END_INT_RAW_S  0
+
+#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0CC)
+/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+#define SPI_MEM_MST_ST_END_INT_ST  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ST_S  4
+/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+#define SPI_MEM_SLV_ST_END_INT_ST  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ST_S  3
+/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+#define SPI_MEM_WPE_END_INT_ST  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_V  0x1
+#define SPI_MEM_WPE_END_INT_ST_S  2
+/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PES_END_INT interrupt.*/
+#define SPI_MEM_PES_END_INT_ST  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_V  0x1
+#define SPI_MEM_PES_END_INT_ST_S  1
+/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PER_END_INT interrupt.*/
+#define SPI_MEM_PER_END_INT_ST  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_V  0x1
+#define SPI_MEM_PER_END_INT_ST_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0DC)
+/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable.*/
+#define SPI_MEM_CLK_EN  (BIT(0))
+#define SPI_MEM_CLK_EN_M  (BIT(0))
+#define SPI_MEM_CLK_EN_V  0x1
+#define SPI_MEM_CLK_EN_S  0
+
+#define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0E0)
+/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: When the digital system clock selects PLL clock and the frequency
+ of PLL clock is 480MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
+#define SPI_MEM_SPI01_CLK_SEL  0x00000003
+#define SPI_MEM_SPI01_CLK_SEL_M  ((SPI_MEM_SPI01_CLK_SEL_V)<<(SPI_MEM_SPI01_CLK_SEL_S))
+#define SPI_MEM_SPI01_CLK_SEL_V  0x3
+#define SPI_MEM_SPI01_CLK_SEL_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007170 ; */
+/*description: Version control register*/
+#define SPI_MEM_DATE  0x0FFFFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0xFFFFFFF
+#define SPI_MEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/spi_mem_struct.h b/components/soc/esp32c3/register/soc/spi_mem_struct.h
new file mode 100644
index 00000000000..95a0aae1ecf
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/spi_mem_struct.h
@@ -0,0 +1,569 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct spi_mem_dev_s {
+    union {
+        struct {
+            uint32_t mst_st:         4;                 /*The current status of SPI1 master FSM.*/
+            uint32_t st:             4;                 /*The current status of SPI1 slave FSM: mspi_st. 0: idle state  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
+            uint32_t reserved8:      9;                 /*reserved*/
+            uint32_t flash_pe:       1;                 /*In user mode  it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t usr:            1;                 /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_hpm:      1;                 /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_res:      1;                 /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_dp:       1;                 /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_ce:       1;                 /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_be:       1;                 /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_se:       1;                 /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_pp:       1;                 /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
+            uint32_t flash_wrsr:     1;                 /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_rdsr:     1;                 /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_rdid:     1;                 /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_wrdi:     1;                 /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_wren:     1;                 /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_read:     1;                 /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;                                      /*SPI1 address register*/
+    union {
+        struct {
+            uint32_t reserved0:       3;                /*reserved*/
+            uint32_t fdummy_out:      1;                /*In the dummy phase the signal level of spi is output by the spi controller.*/
+            uint32_t reserved4:       3;                /*reserved*/
+            uint32_t fcmd_dual:       1;                /*Apply 2 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_quad:       1;                /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t reserved9:       1;                /*reserved*/
+            uint32_t fcs_crc_en:      1;                /*For SPI1   initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en:       1;                /*For SPI1   enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12:      1;                /*reserved*/
+            uint32_t fastrd_mode:     1;                /*This bit enable the bits: spi_mem_fread_qio  spi_mem_fread_dio  spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
+            uint32_t fread_dual:      1;                /*In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
+            uint32_t resandres:       1;                /*The Device ID is read out to SPI_MEM_RD_STATUS register   this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
+            uint32_t reserved16:      2;                /*reserved*/
+            uint32_t q_pol:           1;                /*The bit is used to set MISO line polarity  1: high 0  low*/
+            uint32_t d_pol:           1;                /*The bit is used to set MOSI line polarity  1: high 0  low*/
+            uint32_t fread_quad:      1;                /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+            uint32_t wp:              1;                /*Write protect signal output when SPI is idle.  1: output high  0: output low.*/
+            uint32_t wrsr_2b:         1;                /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
+            uint32_t fread_dio:       1;                /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
+            uint32_t fread_qio:       1;                /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
+            uint32_t reserved25:      7;                /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode:            2;            /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
+            uint32_t cs_hold_dly_res:    10;            /*After RES/DP/HPM command is sent  SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
+            uint32_t reserved2:           18;               /*reserved*/
+            uint32_t rxfifo_rst:       1;               /*SPI0 RX FIFO reset signal.*/
+            uint32_t rxfifo_wfull_err: 1;               /*1: SPI0 RX FIFO write full error  Cache/EDMA do not read all the data out. 0: Not error.*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time: 5;                  /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
+            uint32_t cs_hold_time:  5;                  /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
+            uint32_t reserved10:       15;                  /*reserved*/
+            uint32_t cs_hold_delay: 6;                  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t sync_reset:    1;                  /*The FSM will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l:       8;                 /*In the master mode it must be equal to spi_mem_clkcnt_N.*/
+            uint32_t clkcnt_h:       8;                 /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t clkcnt_n:       8;                 /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24:         7;                 /*reserved*/
+            uint32_t clk_equ_sysclk: 1;                 /*Set this bit in 1-division mode.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0:          6;                 /*reserved*/
+            uint32_t cs_hold:        1;                 /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
+            uint32_t cs_setup:       1;                 /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
+            uint32_t reserved8:          1;                 /*reserved*/
+            uint32_t ck_out_edge:       1;          /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
+            uint32_t reserved10:            2;          /*reserved*/
+            uint32_t fwrite_dual:       1;          /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad:       1;          /*In the write operations read-data phase apply 4 signals*/
+            uint32_t fwrite_dio:        1;          /*In the write operations address phase and read-data phase apply 2 signals.*/
+            uint32_t fwrite_qio:        1;          /*In the write operations address phase and read-data phase apply 4 signals.*/
+            uint32_t reserved16:            8;          /*reserved*/
+            uint32_t usr_miso_highpart: 1;          /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
+            uint32_t usr_mosi_highpart: 1;          /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
+            uint32_t usr_dummy_idle:    1;          /*SPI clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi:          1;          /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso:          1;          /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy:         1;          /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr:          1;          /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command:       1;          /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen:     6;         /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t reserved6:             20;         /*reserved*/
+            uint32_t usr_addr_bitlen:        6;         /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value:     16;         /*The value of  command.*/
+            uint32_t reserved16:            12;         /*reserved*/
+            uint32_t usr_command_bitlen:     4;         /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len:    10;           /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10:          22;           /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len:    10;           /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10:          22;           /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status:     16;                    /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+            uint32_t wb_mode:     8;                    /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t reserved24:  8;                    /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t reserved_30;
+    union {
+        struct {
+            uint32_t cs0_dis:            1;             /*SPI_CS0 pin enable  1: disable SPI_CS0  0: SPI_CS0 pin is active to select SPI device  such as flash  external RAM and so on.*/
+            uint32_t cs1_dis:            1;             /*SPI_CS1 pin enable  1: disable SPI_CS1  0: SPI_CS1 pin is active to select SPI device  such as flash  external RAM and so on.*/
+            uint32_t reserved2:          1;             /*reserved*/
+            uint32_t mst_st_trans_end:         1;       /*The bit is used to indicate the  spi0_mst_st controlled transmitting is done.*/
+            uint32_t mst_st_trans_end_en:      1;       /*The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.*/
+            uint32_t st_trans_end:             1;       /*The bit is used to indicate the  spi0_slv_st controlled transmitting is done.*/
+            uint32_t st_trans_end_en:          1;       /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
+            uint32_t reserved7:                    2;       /*reserved*/
+            uint32_t ck_idle_edge:       1;             /*1: spi clk line is high when idle     0: spi clk line is low when idle*/
+            uint32_t cs_keep_active:     1;             /*spi cs line keep low when the bit is set.*/
+            uint32_t reserved11:                  21;       /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;                                    /*SPI1 TX CRC data register.*/
+    union {
+        struct {
+            uint32_t req_en:               1;           /*For SPI0  Cache access enable  1: enable  0:disable.*/
+            uint32_t usr_addr_4byte:           1;       /*For SPI1   cache  read flash with 4 bytes address  1: enable  0:disable.*/
+            uint32_t flash_usr_cmd:        1;           /*For SPI0   cache  read flash for user define command  1: enable  0:disable.*/
+            uint32_t fdin_dual:                1;       /*For SPI1  din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdout_dual:               1;       /*For SPI1  dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t faddr_dual:               1;       /*For SPI1  address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdin_quad:                1;       /*For SPI1  din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t fdout_quad:               1;       /*For SPI1  dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t faddr_quad:               1;       /*For SPI1  address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t reserved9:               23;       /*reserved*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    union {
+        struct {
+            uint32_t spi0_st:              4;           /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state  1: preparation state  2: send command state  3: send address state  4: wait state  5: read data state  6:write data state  7: done state  8: read data end state.*/
+            uint32_t spi0_mst_st:          3;           /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state  1:EM_CACHE_GRANT   2: program/erase suspend state  3: SPI0 read data state  4: wait cache/EDMA sent data is stored in SPI0 TX FIFO  5: SPI0 write data state.*/
+            uint32_t cspi_lock_delay_time: 5;           /*The lock delay time of SPI0/1 arbiter by spi0_slv_st  after PER is sent by SPI1.*/
+            uint32_t reserved12:              20;           /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    uint32_t data_buf[16];
+    union {
+        struct {
+            uint32_t reserved0:                1;       /*reserved*/
+            uint32_t waiti_dummy:              1;       /*The dummy phase enable when wait flash idle (RDSR)*/
+            uint32_t waiti_cmd:                8;       /*The command to wait flash idle(RDSR).*/
+            uint32_t waiti_dummy_cyclelen:     6;       /*The dummy cycle length when wait flash idle(RDSR).*/
+            uint32_t reserved16:              16;       /*reserved*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per:             1;          /*program erase resume bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_pes:             1;          /*program erase suspend bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_per_wait_en:     1;          /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after program erase suspend.*/
+            uint32_t flash_pes_wait_en:     1;          /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after program erase suspend.*/
+            uint32_t pes_per_en:            1;          /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0  application should send PER after PES is done.*/
+            uint32_t flash_pes_en:          1;          /*Set this bit to enable Auto-suspending function.*/
+            uint32_t pesr_end_msk:         16;          /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out  status_in[15:0] is valid when two bytes of data are read out)  SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+            uint32_t frd_sus_2b:            1;          /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+            uint32_t per_end_en:            1;          /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t pes_end_en:            1;          /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t sus_timeout_cnt:       7;          /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times  it will be treated as check pass.*/
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t flash_per_command:     8;          /*Program/Erase resume command.*/
+            uint32_t flash_pes_command:     8;          /*Program/Erase suspend command.*/
+            uint32_t wait_pesr_command:    16;          /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_sus:     1;                  /*The status of flash suspend  only used in SPI1.*/
+            uint32_t wait_pesr_cmd_2b:1;
+            uint32_t hpm_dly_128:   1;
+            uint32_t res_dly_128:   1;
+            uint32_t dp_dly_128:    1;
+            uint32_t per_dly_128:   1;
+            uint32_t pes_dly_128:   1;
+            uint32_t spi0_lock_en:  1;
+            uint32_t reserved1:    24;                  /*reserved*/
+        };
+        uint32_t val;
+    } sus_status;
+    union {
+        struct {
+            uint32_t timing_clk_ena:       1;           /*The bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t timing_cali:              1;       /*The bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t extra_dummy_cyclelen:     3;       /*add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t reserved5:               27;           /*reserved*/
+        };
+        uint32_t val;
+    } timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+            uint32_t din1_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+            uint32_t din2_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+            uint32_t din3_mode: 2;                      /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+            uint32_t reserved8:    24;                      /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din1_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din2_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din3_num: 2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t reserved8:   24;                       /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+            uint32_t dout1_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+            uint32_t dout2_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+            uint32_t dout3_mode: 1;                     /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+            uint32_t reserved4:     28;                     /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    union {
+        struct {
+            uint32_t per_end_int_ena:        1;         /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_int_ena:        1;         /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end_int_ena:        1;         /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t st_end_int_ena:         1;         /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end_int_ena:     1;         /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t reserved5:             27;         /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t per_end:                1;         /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end:                1;         /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end:                1;         /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t st_end:                 1;         /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end:             1;         /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t reserved5:             27;         /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t per_end:                1;         /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
+            uint32_t pes_end:                1;         /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
+            uint32_t wpe_end:                1;         /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+            uint32_t st_end:                 1;         /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+            uint32_t mst_st_end:             1;         /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
+            uint32_t reserved5:             27;         /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t per_end:               1;          /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end:               1;          /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end:               1;          /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t st_end:                1;          /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end:            1;          /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t reserved5:            27;          /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    union {
+        struct {
+            uint32_t clk_en:     1;                     /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1: 31;                         /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t spi01_clk_sel: 2;                  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz  the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
+            uint32_t reserved2:        30;                  /*reserved*/
+        };
+        uint32_t val;
+    } core_clk_sel;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date:      28;                     /*Version control register*/
+            uint32_t reserved28: 4;                     /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/spi_reg.h b/components/soc/esp32c3/register/soc/spi_reg.h
new file mode 100644
index 00000000000..e8e9fec283f
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/spi_reg.h
@@ -0,0 +1,1435 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_REG_H_
+#define _SOC_SPI_REG_H_
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
+/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when the bit is set.
+ The bit will be cleared once the operation done.1: enable 0: disable. Can not b
+e changed by CONF_buf..*/
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (BIT(24))
+#define SPI_USR_V  0x1
+#define SPI_USR_S  24
+/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
+clock domain, which is only used in SPI master mode..*/
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (BIT(23))
+#define SPI_UPDATE_V  0x1
+#define SPI_UPDATE_S  23
+/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: Define the APB cycles of  SPI_CONF state. Can be configured in CONF state..*/
+#define SPI_CONF_BITLEN    0x0003FFFF
+#define SPI_CONF_BITLEN_M  ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
+#define SPI_CONF_BITLEN_V  0x3FFFF
+#define SPI_CONF_BITLEN_S  0
+
+#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
+/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Address to slave. Can be configured in CONF state..*/
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_S  0
+
+#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
+figured in CONF state..*/
+#define SPI_WR_BIT_ORDER    (BIT(26))
+#define SPI_WR_BIT_ORDER_M  (BIT(26))
+#define SPI_WR_BIT_ORDER_V  0x1
+#define SPI_WR_BIT_ORDER_S  26
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
+tate..*/
+#define SPI_RD_BIT_ORDER    (BIT(25))
+#define SPI_RD_BIT_ORDER_M  (BIT(25))
+#define SPI_RD_BIT_ORDER_V  0x1
+#define SPI_RD_BIT_ORDER_S  25
+/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
+an be configured in CONF state..*/
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (BIT(21))
+#define SPI_WP_POL_V  0x1
+#define SPI_WP_POL_S  21
+/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co
+nfigured in CONF state..*/
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (BIT(20))
+#define SPI_HOLD_POL_V  0x1
+#define SPI_HOLD_POL_S  20
+/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (BIT(19))
+#define SPI_D_POL_V  0x1
+#define SPI_D_POL_S  19
+/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (BIT(18))
+#define SPI_Q_POL_V  0x1
+#define SPI_Q_POL_S  18
+/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  C
+an be configured in CONF state..*/
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (BIT(15))
+#define SPI_FREAD_QUAD_V  0x1
+#define SPI_FREAD_QUAD_S  15
+/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C
+an be configured in CONF state..*/
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (BIT(14))
+#define SPI_FREAD_DUAL_V  0x1
+#define SPI_FREAD_DUAL_S  14
+/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (BIT(9))
+#define SPI_FCMD_QUAD_V  0x1
+#define SPI_FCMD_QUAD_S  9
+/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (BIT(8))
+#define SPI_FCMD_DUAL_V  0x1
+#define SPI_FCMD_DUAL_S  8
+/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (BIT(6))
+#define SPI_FADDR_QUAD_V  0x1
+#define SPI_FADDR_QUAD_S  6
+/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (BIT(5))
+#define SPI_FADDR_DUAL_V  0x1
+#define SPI_FADDR_DUAL_S  5
+/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the dummy phase the signal level of spi is output by the spi controller. Can
+be configured in CONF state..*/
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (BIT(3))
+#define SPI_DUMMY_OUT_V  0x1
+#define SPI_DUMMY_OUT_S  3
+
+#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0xC)
+/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst
+em clock. Can be configured in CONF state..*/
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_V  0x1
+#define SPI_CLK_EQU_SYSCLK_S  31
+/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
+/*description: In the master mode it is pre-divider of spi_clk.  Can be configured in CONF stat
+e..*/
+#define SPI_CLKDIV_PRE    0x0000000F
+#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
+#define SPI_CLKDIV_PRE_V  0xF
+#define SPI_CLKDIV_PRE_S  18
+/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
+/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/
+(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
+#define SPI_CLKCNT_N    0x0000003F
+#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
+#define SPI_CLKCNT_N_V  0x3F
+#define SPI_CLKCNT_N_S  12
+/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
+/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+must be 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_H    0x0000003F
+#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
+#define SPI_CLKCNT_H_V  0x3F
+#define SPI_CLKCNT_H_S  6
+/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b
+e 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_L    0x0000003F
+#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
+#define SPI_CLKCNT_L_V  0x3F
+#define SPI_CLKCNT_L_S  0
+
+#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x10)
+/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (BIT(31))
+#define SPI_USR_COMMAND_V  0x1
+#define SPI_USR_COMMAND_S  31
+/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (BIT(30))
+#define SPI_USR_ADDR_V  0x1
+#define SPI_USR_ADDR_S  30
+/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
+..*/
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (BIT(29))
+#define SPI_USR_DUMMY_V  0x1
+#define SPI_USR_DUMMY_S  29
+/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s
+tate..*/
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (BIT(28))
+#define SPI_USR_MISO_V  0x1
+#define SPI_USR_MISO_S  28
+/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (BIT(27))
+#define SPI_USR_MOSI_V  0x1
+#define SPI_USR_MOSI_S  27
+/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ CONF state..*/
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_USR_DUMMY_IDLE_V  0x1
+#define SPI_USR_DUMMY_IDLE_S  26
+/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl
+e 0: disable.  Can be configured in CONF state..*/
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_V  0x1
+#define SPI_USR_MOSI_HIGHPART_S  25
+/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ 0: disable. Can be configured in CONF state..*/
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_USR_MISO_HIGHPART_V  0x1
+#define SPI_USR_MISO_HIGHPART_S  24
+/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha
+re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (BIT(17))
+#define SPI_SIO_V  0x1
+#define SPI_SIO_S  17
+/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+will continue. 0: The seg-trans will end after the current SPI seg-trans or this
+ is not seg-trans mode. Can be configured in CONF state..*/
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (BIT(15))
+#define SPI_USR_CONF_NXT_V  0x1
+#define SPI_USR_CONF_NXT_S  15
+/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (BIT(13))
+#define SPI_FWRITE_QUAD_V  0x1
+#define SPI_FWRITE_QUAD_S  13
+/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (BIT(12))
+#define SPI_FWRITE_DUAL_V  0x1
+#define SPI_FWRITE_DUAL_S  12
+/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca
+n be configured in CONF state..*/
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_CK_OUT_EDGE_V  0x1
+#define SPI_CK_OUT_EDGE_S  9
+/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
+= !spi_ck_i. 1:rsck = spi_ck_i..*/
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (BIT(8))
+#define SPI_RSCK_I_EDGE_V  0x1
+#define SPI_RSCK_I_EDGE_S  8
+/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (BIT(7))
+#define SPI_CS_SETUP_V  0x1
+#define SPI_CS_SETUP_S  7
+/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be config
+ured in CONF state..*/
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (BIT(6))
+#define SPI_CS_HOLD_V  0x1
+#define SPI_CS_HOLD_S  6
+/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
+= spi_ck_i. 1:tsck = !spi_ck_i..*/
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (BIT(5))
+#define SPI_TSCK_I_EDGE_V  0x1
+#define SPI_TSCK_I_EDGE_S  5
+/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others
+. Can be configured in CONF state..*/
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (BIT(3))
+#define SPI_QPI_MODE_V  0x1
+#define SPI_QPI_MODE_S  3
+/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (BIT(0))
+#define SPI_DOUTDIN_V  0x1
+#define SPI_DOUTDIN_S  0
+
+#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x14)
+/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_ADDR_BITLEN    0x0000001F
+#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
+#define SPI_USR_ADDR_BITLEN_V  0x1F
+#define SPI_USR_ADDR_BITLEN_S  27
+/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */
+/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ Can be configured in CONF state..*/
+#define SPI_CS_HOLD_TIME    0x0000001F
+#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
+#define SPI_CS_HOLD_TIME_V  0x1F
+#define SPI_CS_HOLD_TIME_S  22
+/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
+/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu
+p bit. Can be configured in CONF state..*/
+#define SPI_CS_SETUP_TIME    0x0000001F
+#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
+#define SPI_CS_SETUP_TIME_V  0x1F
+#define SPI_CS_SETUP_TIME_S  17
+/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
+ in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_V  0x1
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
+/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_
+num-1). Can be configured in CONF state..*/
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
+#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x18)
+/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
+#define SPI_USR_COMMAND_BITLEN_V  0xF
+#define SPI_USR_COMMAND_BITLEN_S  28
+/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
+aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+r is valid in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x1
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command. Can be configured in CONF state..*/
+#define SPI_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
+#define SPI_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_USR_COMMAND_VALUE_S  0
+
+#define SPI_MS_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x1C)
+/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: The value of these bits is the configured SPI transmission data bit length in ma
+ster mode DMA controlled transfer or CPU controlled transfer. The value is also
+the configured bit length in slave mode DMA RX controlled transfer. The register
+ value shall be (bit_num-1). Can be configured in CONF state..*/
+#define SPI_MS_DATA_BITLEN    0x0003FFFF
+#define SPI_MS_DATA_BITLEN_M  ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
+#define SPI_MS_DATA_BITLEN_V  0x3FFFF
+#define SPI_MS_DATA_BITLEN_S  0
+
+#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
+/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configur
+ed in CONF state..*/
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_V  0x1
+#define SPI_CS_KEEP_ACTIVE_S  30
+/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle. Can be c
+onfigured in CONF state..*/
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (BIT(29))
+#define SPI_CK_IDLE_EDGE_V  0x1
+#define SPI_CK_IDLE_EDGE_S  29
+/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+CONF state..*/
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (BIT(23))
+#define SPI_SLAVE_CS_POL_V  0x1
+#define SPI_SLAVE_CS_POL_S  23
+/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
+/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva
+lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/
+#define SPI_MASTER_CS_POL    0x0000003F
+#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
+#define SPI_MASTER_CS_POL_V  0x3F
+#define SPI_MASTER_CS_POL_S  7
+/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state..*/
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (BIT(6))
+#define SPI_CK_DIS_V  0x1
+#define SPI_CK_DIS_S  6
+/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (BIT(5))
+#define SPI_CS5_DIS_V  0x1
+#define SPI_CS5_DIS_S  5
+/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (BIT(4))
+#define SPI_CS4_DIS_V  0x1
+#define SPI_CS4_DIS_S  4
+/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (BIT(3))
+#define SPI_CS3_DIS_V  0x1
+#define SPI_CS3_DIS_S  3
+/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (BIT(2))
+#define SPI_CS2_DIS_V  0x1
+#define SPI_CS2_DIS_S  2
+/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (BIT(1))
+#define SPI_CS1_DIS_V  0x1
+#define SPI_CS1_DIS_S  1
+/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (BIT(0))
+#define SPI_CS0_DIS_V  0x1
+#define SPI_CS0_DIS_S  0
+
+#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x24)
+/* SPI_TIMING_HCLK_ACTIVE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1:enable hclk in SPI input timing module.  0: disable it. Can be configured in C
+ONF state..*/
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_V  0x1
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN3_MODE    0x00000003
+#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
+#define SPI_DIN3_MODE_V  0x3
+#define SPI_DIN3_MODE_S  6
+/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN2_MODE    0x00000003
+#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
+#define SPI_DIN2_MODE_V  0x3
+#define SPI_DIN2_MODE_S  4
+/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN1_MODE    0x00000003
+#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
+#define SPI_DIN1_MODE_V  0x3
+#define SPI_DIN1_MODE_S  2
+/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN0_MODE    0x00000003
+#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
+#define SPI_DIN0_MODE_V  0x3
+#define SPI_DIN0_MODE_S  0
+
+#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x28)
+/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN3_NUM    0x00000003
+#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
+#define SPI_DIN3_NUM_V  0x3
+#define SPI_DIN3_NUM_S  6
+/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN2_NUM    0x00000003
+#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
+#define SPI_DIN2_NUM_V  0x3
+#define SPI_DIN2_NUM_S  4
+/* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN1_NUM    0x00000003
+#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
+#define SPI_DIN1_NUM_V  0x3
+#define SPI_DIN1_NUM_S  2
+/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN0_NUM    0x00000003
+#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
+#define SPI_DIN0_NUM_V  0x3
+#define SPI_DIN0_NUM_S  0
+
+#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x2C)
+/* SPI_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (BIT(3))
+#define SPI_DOUT3_MODE_V  0x1
+#define SPI_DOUT3_MODE_S  3
+/* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (BIT(2))
+#define SPI_DOUT2_MODE_V  0x1
+#define SPI_DOUT2_MODE_S  2
+/* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (BIT(1))
+#define SPI_DOUT1_MODE_V  0x1
+#define SPI_DOUT1_MODE_S  1
+/* SPI_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (BIT(0))
+#define SPI_DOUT0_MODE_V  0x1
+#define SPI_DOUT0_MODE_S  0
+
+#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x30)
+/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
+DMA controlled mode transfer..*/
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (BIT(31))
+#define SPI_DMA_AFIFO_RST_V  0x1
+#define SPI_DMA_AFIFO_RST_S  31
+/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ controlled mode transfer and master mode transfer..*/
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (BIT(30))
+#define SPI_BUF_AFIFO_RST_V  0x1
+#define SPI_BUF_AFIFO_RST_S  30
+/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+slave mode transfer..*/
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (BIT(29))
+#define SPI_RX_AFIFO_RST_V  0x1
+#define SPI_RX_AFIFO_RST_S  29
+/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI DMA controlled send data mode..*/
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (BIT(28))
+#define SPI_DMA_TX_ENA_V  0x1
+#define SPI_DMA_TX_ENA_S  28
+/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Set this bit to enable SPI DMA controlled receive data mode..*/
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (BIT(27))
+#define SPI_DMA_RX_ENA_V  0x1
+#define SPI_DMA_RX_ENA_S  27
+/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
+o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_d
+ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don
+e in seg-trans..*/
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (BIT(21))
+#define SPI_RX_EOF_EN_V  0x1
+#define SPI_RX_EOF_EN_S  21
+/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
+mpty_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full
+_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+
+#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
+/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (BIT(20))
+#define SPI_APP1_INT_ENA_V  0x1
+#define SPI_APP1_INT_ENA_S  20
+/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (BIT(19))
+#define SPI_APP2_INT_ENA_V  0x1
+#define SPI_APP2_INT_ENA_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_V  0x1
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_V  0x1
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_V  0x1
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_V  0x1
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+
+#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x38)
+/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (BIT(20))
+#define SPI_APP1_INT_CLR_V  0x1
+#define SPI_APP1_INT_CLR_S  20
+/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (BIT(19))
+#define SPI_APP2_INT_CLR_V  0x1
+#define SPI_APP2_INT_CLR_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x1
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_V  0x1
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_V  0x1
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_V  0x1
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_V  0x1
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+
+#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x3C)
+/* SPI_APP1_INT_RAW : R/W/WTC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by applicat
+ion..*/
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (BIT(20))
+#define SPI_APP1_INT_RAW_V  0x1
+#define SPI_APP1_INT_RAW_S  20
+/* SPI_APP2_INT_RAW : R/W/WTC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by applicat
+ion..*/
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (BIT(19))
+#define SPI_APP2_INT_RAW_V  0x1
+#define SPI_APP2_INT_RAW_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ write-full error when SPI inputs data in master mode. 0: Others..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/* SPI_SLV_CMD_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ current SPI slave HD mode transmission is not supported. 0: Others..*/
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x1
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
+ is bigger than 63. 0: Others..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/* SPI_SEG_MAGIC_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff
+er is error in the DMA seg-conf-trans. 0: others..*/
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-du
+plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
+ta has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is
+not ended or not occurred. .*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/* SPI_TRANS_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ ended. 0: others..*/
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/W/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/* SPI_SLV_CMDA_INT_RAW : R/W/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_V  0x1
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/* SPI_SLV_CMD9_INT_RAW : R/W/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_V  0x1
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/* SPI_SLV_CMD8_INT_RAW : R/W/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_V  0x1
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/* SPI_SLV_CMD7_INT_RAW : R/W/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_V  0x1
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/* SPI_SLV_EN_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/* SPI_SLV_EX_QPI_INT_RAW : R/W/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ master mode and send out all 0 in slave mode.  0: Others.  .*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/W/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
+the receive data.  0: Others.  .*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+
+#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x40)
+/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (BIT(20))
+#define SPI_APP1_INT_ST_V  0x1
+#define SPI_APP1_INT_ST_S  20
+/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (BIT(19))
+#define SPI_APP2_INT_ST_V  0x1
+#define SPI_APP2_INT_ST_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_V  0x1
+#define SPI_TRANS_DONE_INT_ST_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_V  0x1
+#define SPI_SLV_CMDA_INT_ST_S  7
+/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_V  0x1
+#define SPI_SLV_CMD9_INT_ST_S  6
+/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_V  0x1
+#define SPI_SLV_CMD8_INT_ST_S  5
+/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_V  0x1
+#define SPI_SLV_CMD7_INT_ST_S  4
+/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_V  0x1
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_V  0x1
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+
+#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x98)
+/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF0    0xFFFFFFFF
+#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
+#define SPI_BUF0_V  0xFFFFFFFF
+#define SPI_BUF0_S  0
+
+#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x9C)
+/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF1    0xFFFFFFFF
+#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
+#define SPI_BUF1_V  0xFFFFFFFF
+#define SPI_BUF1_S  0
+
+#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0xA0)
+/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF2    0xFFFFFFFF
+#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
+#define SPI_BUF2_V  0xFFFFFFFF
+#define SPI_BUF2_S  0
+
+#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0xA4)
+/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF3    0xFFFFFFFF
+#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
+#define SPI_BUF3_V  0xFFFFFFFF
+#define SPI_BUF3_S  0
+
+#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0xA8)
+/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF4    0xFFFFFFFF
+#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
+#define SPI_BUF4_V  0xFFFFFFFF
+#define SPI_BUF4_S  0
+
+#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0xAC)
+/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF5    0xFFFFFFFF
+#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
+#define SPI_BUF5_V  0xFFFFFFFF
+#define SPI_BUF5_S  0
+
+#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0xB0)
+/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF6    0xFFFFFFFF
+#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
+#define SPI_BUF6_V  0xFFFFFFFF
+#define SPI_BUF6_S  0
+
+#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0xB4)
+/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF7    0xFFFFFFFF
+#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
+#define SPI_BUF7_V  0xFFFFFFFF
+#define SPI_BUF7_S  0
+
+#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xB8)
+/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF8    0xFFFFFFFF
+#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
+#define SPI_BUF8_V  0xFFFFFFFF
+#define SPI_BUF8_S  0
+
+#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xBC)
+/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF9    0xFFFFFFFF
+#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
+#define SPI_BUF9_V  0xFFFFFFFF
+#define SPI_BUF9_S  0
+
+#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xC0)
+/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF10    0xFFFFFFFF
+#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
+#define SPI_BUF10_V  0xFFFFFFFF
+#define SPI_BUF10_S  0
+
+#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xC4)
+/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF11    0xFFFFFFFF
+#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
+#define SPI_BUF11_V  0xFFFFFFFF
+#define SPI_BUF11_S  0
+
+#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xC8)
+/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF12    0xFFFFFFFF
+#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
+#define SPI_BUF12_V  0xFFFFFFFF
+#define SPI_BUF12_S  0
+
+#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xCC)
+/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF13    0xFFFFFFFF
+#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
+#define SPI_BUF13_V  0xFFFFFFFF
+#define SPI_BUF13_S  0
+
+#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xD0)
+/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF14    0xFFFFFFFF
+#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
+#define SPI_BUF14_V  0xFFFFFFFF
+#define SPI_BUF14_S  0
+
+#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xD4)
+/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF15    0xFFFFFFFF
+#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
+#define SPI_BUF15_V  0xFFFFFFFF
+#define SPI_BUF15_S  0
+
+#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0xE0)
+/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
+ns will start. 0: This is not seg-trans mode..*/
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (BIT(28))
+#define SPI_USR_CONF_V  0x1
+#define SPI_USR_CONF_S  28
+/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
+onfigured in CONF state..*/
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (BIT(27))
+#define SPI_SOFT_RESET_V  0x1
+#define SPI_SOFT_RESET_S  27
+/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (BIT(26))
+#define SPI_SLAVE_MODE_V  0x1
+#define SPI_SLAVE_MODE_S  26
+/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
+/*description: The magic value of BM table in master DMA seg-trans..*/
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000F
+#define SPI_DMA_SEG_MAGIC_VALUE_M  ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0xF
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in CPU controlled mode(Wr_BUF). 0: others.*/
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n CPU controlled mode(Rd_BUF). 0: others.*/
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in DMA controlled mode(Wr_DMA). 0: others.*/
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n DMA controlled mode(Rd_DMA). 0: others.*/
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
+dge   0: output data at tsck posedge .*/
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (BIT(3))
+#define SPI_RSCK_DATA_OUT_V  0x1
+#define SPI_RSCK_DATA_OUT_S  3
+/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
+ 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (BIT(2))
+#define SPI_CLK_MODE_13_V  0x1
+#define SPI_CLK_MODE_13_S  2
+/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on. Can be configured in CONF state..*/
+#define SPI_CLK_MODE    0x00000003
+#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
+#define SPI_CLK_MODE_V  0x3
+#define SPI_CLK_MODE_S  0
+
+#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0xE4)
+/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
+/*description: In the slave mode it is the value of address..*/
+#define SPI_SLV_LAST_ADDR    0x0000003F
+#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
+#define SPI_SLV_LAST_ADDR_V  0x3F
+#define SPI_SLV_LAST_ADDR_S  26
+/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of command..*/
+#define SPI_SLV_LAST_COMMAND    0x000000FF
+#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
+#define SPI_SLV_LAST_COMMAND_V  0xFF
+#define SPI_SLV_LAST_COMMAND_S  18
+/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: The transferred data bit length in SPI slave FD and HD mode. .*/
+#define SPI_SLV_DATA_BITLEN    0x0003FFFF
+#define SPI_SLV_DATA_BITLEN_M  ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
+#define SPI_SLV_DATA_BITLEN_V  0x3FFFF
+#define SPI_SLV_DATA_BITLEN_S  0
+
+#define SPI_CLK_GATE_REG(i)          (REG_SPI_BASE(i) + 0xE8)
+/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
+M. 0: XTAL CLK..*/
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (BIT(2))
+#define SPI_MST_CLK_SEL_V  0x1
+#define SPI_MST_CLK_SEL_S  2
+/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to power on the SPI module clock..*/
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (BIT(1))
+#define SPI_MST_CLK_ACTIVE_V  0x1
+#define SPI_MST_CLK_ACTIVE_S  1
+/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate.*/
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (BIT(0))
+#define SPI_CLK_EN_V  0x1
+#define SPI_CLK_EN_S  0
+
+#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
+/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007220 ; */
+/*description: SPI register version..*/
+#define SPI_DATE    0x0FFFFFFF
+#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
+#define SPI_DATE_V  0xFFFFFFF
+#define SPI_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/spi_struct.h b/components/soc/esp32c3/register/soc/spi_struct.h
new file mode 100644
index 00000000000..88d7476caf9
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/spi_struct.h
@@ -0,0 +1,368 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct spi_dev_s {
+    union {
+        struct {
+            uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    5;  /*reserved*/
+            uint32_t update                        :    1;  /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
+            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;  /*reserved*/
+            uint32_t dummy_out                     :    1;  /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved7                     :    1;  /*reserved*/
+            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved10                    :    4;  /*reserved*/
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t reserved17                    :    1;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
+            uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    3;  /*reserved*/
+            uint32_t rd_bit_order                  :    1;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
+            uint32_t wr_bit_order                  :    1;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    6;  /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_h                      :    6;  /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_n                      :    6;  /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
+            uint32_t clkdiv_pre                    :    4;  /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    9;  /*reserved*/
+            uint32_t clk_equ_sysclk                :    1;  /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t doutdin                       :    1;  /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved1                     :    2;  /*reserved*/
+            uint32_t qpi_mode                      :    1;  /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t tsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t rsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
+            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
+            uint32_t reserved14                    :    1;  /*reserved*/
+            uint32_t usr_conf_nxt                  :    1;  /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t sio                           :    1;  /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    6;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    8;  /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
+            uint32_t reserved8                     :    8;  /*reserved*/
+            uint32_t mst_wfull_err_end_en          :    1;  /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t cs_setup_time                 :    5;  /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
+            uint32_t cs_hold_time                  :    5;  /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
+            uint32_t usr_addr_bitlen               :    5;  /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    11;  /*reserved*/
+            uint32_t mst_rempty_err_end_en         :    1;  /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t ms_data_bitlen                :    18;  /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } ms_dlen;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs1_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs2_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs3_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs4_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs5_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t ck_dis                        :    1;  /*1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.*/
+            uint32_t master_cs_pol                 :    6;  /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
+            uint32_t reserved13                    :    10;  /*reserved*/
+            uint32_t slave_cs_pol                  :    1;  /*spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.*/
+            uint32_t reserved24                    :    5;  /*reserved*/
+            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
+            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
+            uint32_t quad_din_pin_swap             :    1;  /*1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } misc;
+    union {
+        struct {
+            uint32_t din0_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din1_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din2_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din3_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t reserved8                     :    8;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t timing_hclk_active            :    1;  /*1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.*/
+            uint32_t reserved17                    :    15;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout1_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout2_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout3_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;  /*reserved*/
+            uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
+            uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
+            uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
+            uint32_t rx_eof_en                     :    1;  /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
+            uint32_t reserved22                    :    5;  /*reserved*/
+            uint32_t dma_rx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled receive data mode.*/
+            uint32_t dma_tx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled send data mode.*/
+            uint32_t rx_afifo_rst                  :    1;  /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
+            uint32_t buf_afifo_rst                 :    1;  /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
+            uint32_t dma_afifo_rst                 :    1;  /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The enable bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The enable bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The enable bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The enable bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The enable bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The enable bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The enable bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The enable bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_ena;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The clear bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The clear bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The clear bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The clear bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The clear bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The clear bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The clear bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The clear bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_clr;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.  */
+            uint32_t outfifo_empty_err             :    1;  /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.  */
+            uint32_t ex_qpi                        :    1;  /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
+            uint32_t en_qpi                        :    1;  /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
+            uint32_t cmd7                          :    1;  /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
+            uint32_t cmd8                          :    1;  /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
+            uint32_t cmd9                          :    1;  /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
+            uint32_t cmda                          :    1;  /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
+            uint32_t rd_dma_done                   :    1;  /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
+            uint32_t wr_dma_done                   :    1;  /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
+            uint32_t rd_buf_done                   :    1;  /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
+            uint32_t wr_buf_done                   :    1;  /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
+            uint32_t trans_done                    :    1;  /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred. */
+            uint32_t seg_magic_err                 :    1;  /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
+            uint32_t buf_addr_err                  :    1;  /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
+            uint32_t cmd_err                       :    1;  /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
+            uint32_t app2                          :    1;  /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.*/
+            uint32_t app1                          :    1;  /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_raw;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The status bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The status bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The status bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The status bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The status bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The status bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The status bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The status bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_st;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t data_buf[16];
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/
+            uint32_t clk_mode_13                   :    1;  /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
+            uint32_t rsck_data_out                 :    1;  /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge */
+            uint32_t reserved4                     :    4;  /*reserved*/
+            uint32_t rddma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
+            uint32_t wrdma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
+            uint32_t rdbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
+            uint32_t wrbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
+            uint32_t reserved12                    :    10;  /*reserved*/
+            uint32_t dma_seg_magic_value           :    4;  /*The magic value of BM table in master DMA seg-trans.*/
+            uint32_t slave_mode                    :    1;  /*Set SPI work mode. 1: slave mode 0: master mode.*/
+            uint32_t soft_reset                    :    1;  /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
+            uint32_t usr_conf                      :    1;  /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
+            uint32_t reserved29                    :    3;  /*reserved*/
+        };
+        uint32_t val;
+    } slave;
+    union {
+        struct {
+            uint32_t data_bitlen                   :    18;  /*The transferred data bit length in SPI slave FD and HD mode. */
+            uint32_t last_command                  :    8;  /*In the slave mode it is the value of command.*/
+            uint32_t last_addr                     :    6;  /*In the slave mode it is the value of address.*/
+        };
+        uint32_t val;
+    } slave1;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
+            uint32_t mst_clk_active                :    1;  /*Set this bit to power on the SPI module clock.*/
+            uint32_t mst_clk_sel                   :    1;  /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } clk_gate;
+    uint32_t reserved_ec;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_dev_t;
+
+extern spi_dev_t GPSPI2;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/syscon_reg.h b/components/soc/esp32c3/register/soc/syscon_reg.h
new file mode 100644
index 00000000000..1aff9a57484
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/syscon_reg.h
@@ -0,0 +1,630 @@
+/**
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSCON_REG_H_
+#define _SOC_SYSCON_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x000)
+/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_RST_TICK_CNT  (BIT(12))
+#define SYSCON_RST_TICK_CNT_M  (BIT(12))
+#define SYSCON_RST_TICK_CNT_V  0x1
+#define SYSCON_RST_TICK_CNT_S  12
+/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_CLK_EN  (BIT(11))
+#define SYSCON_CLK_EN_M  (BIT(11))
+#define SYSCON_CLK_EN_V  0x1
+#define SYSCON_CLK_EN_S  11
+/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_CLK_320M_EN  (BIT(10))
+#define SYSCON_CLK_320M_EN_M  (BIT(10))
+#define SYSCON_CLK_320M_EN_V  0x1
+#define SYSCON_CLK_320M_EN_S  10
+/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: */
+#define SYSCON_PRE_DIV_CNT  0x000003FF
+#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
+#define SYSCON_PRE_DIV_CNT_V  0x3FF
+#define SYSCON_PRE_DIV_CNT_S  0
+
+#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x004)
+/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: */
+#define SYSCON_TICK_ENABLE  (BIT(16))
+#define SYSCON_TICK_ENABLE_M  (BIT(16))
+#define SYSCON_TICK_ENABLE_V  0x1
+#define SYSCON_TICK_ENABLE_S  16
+/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: */
+#define SYSCON_CK8M_TICK_NUM  0x000000FF
+#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
+#define SYSCON_CK8M_TICK_NUM_V  0xFF
+#define SYSCON_CK8M_TICK_NUM_S  8
+/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: */
+#define SYSCON_XTAL_TICK_NUM  0x000000FF
+#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
+#define SYSCON_XTAL_TICK_NUM_V  0xFF
+#define SYSCON_XTAL_TICK_NUM_S  0
+
+#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x008)
+/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_XTAL_OEN  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_V  0x1
+#define SYSCON_CLK_XTAL_OEN_S  10
+/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK40X_BB_OEN  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_V  0x1
+#define SYSCON_CLK40X_BB_OEN_S  9
+/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_DAC_CPU_OEN  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
+#define SYSCON_CLK_DAC_CPU_OEN_S  8
+/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_ADC_INF_OEN  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_V  0x1
+#define SYSCON_CLK_ADC_INF_OEN_S  7
+/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_320M_OEN  (BIT(6))
+#define SYSCON_CLK_320M_OEN_M  (BIT(6))
+#define SYSCON_CLK_320M_OEN_V  0x1
+#define SYSCON_CLK_320M_OEN_S  6
+/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK160_OEN  (BIT(5))
+#define SYSCON_CLK160_OEN_M  (BIT(5))
+#define SYSCON_CLK160_OEN_V  0x1
+#define SYSCON_CLK160_OEN_S  5
+/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK80_OEN  (BIT(4))
+#define SYSCON_CLK80_OEN_M  (BIT(4))
+#define SYSCON_CLK80_OEN_V  0x1
+#define SYSCON_CLK80_OEN_S  4
+/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_BB_OEN  (BIT(3))
+#define SYSCON_CLK_BB_OEN_M  (BIT(3))
+#define SYSCON_CLK_BB_OEN_V  0x1
+#define SYSCON_CLK_BB_OEN_S  3
+/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK44_OEN  (BIT(2))
+#define SYSCON_CLK44_OEN_M  (BIT(2))
+#define SYSCON_CLK44_OEN_V  0x1
+#define SYSCON_CLK44_OEN_S  2
+/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK22_OEN  (BIT(1))
+#define SYSCON_CLK22_OEN_M  (BIT(1))
+#define SYSCON_CLK22_OEN_V  0x1
+#define SYSCON_CLK22_OEN_S  1
+/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK20_OEN  (BIT(0))
+#define SYSCON_CLK20_OEN_M  (BIT(0))
+#define SYSCON_CLK20_OEN_V  0x1
+#define SYSCON_CLK20_OEN_S  0
+
+#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0x00C)
+/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_BB_CFG  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
+#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_S  0
+
+#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x010)
+/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_BB_CFG_2  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
+#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_S  0
+
+#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x014)
+/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define SYSCON_WIFI_CLK_EN  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
+#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_S  0
+
+#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x018)
+/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_RST  0xFFFFFFFF
+#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
+#define SYSCON_WIFI_RST_V  0xFFFFFFFF
+#define SYSCON_WIFI_RST_S  0
+
+#define SYSTEM_WIFI_CLK_EN_REG          SYSCON_WIFI_CLK_EN_REG
+/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define SYSTEM_WIFI_CLK_EN  0x00FB9FCF
+#define SYSTEM_WIFI_CLK_EN_M  ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
+#define SYSTEM_WIFI_CLK_EN_V  0x00FB9FCF
+#define SYSTEM_WIFI_CLK_EN_S  0
+
+/* Mask for all Wifi clock bits, 6 */
+#define SYSTEM_WIFI_CLK_WIFI_EN  0x0
+#define SYSTEM_WIFI_CLK_WIFI_EN_M  ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
+#define SYSTEM_WIFI_CLK_WIFI_EN_V  0x0
+#define SYSTEM_WIFI_CLK_WIFI_EN_S  0
+/* Mask for all Bluetooth clock bits, 11, 16, 17 */
+#define SYSTEM_WIFI_CLK_BT_EN  0x0
+#define SYSTEM_WIFI_CLK_BT_EN_M  ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
+#define SYSTEM_WIFI_CLK_BT_EN_V  0x0
+#define SYSTEM_WIFI_CLK_BT_EN_S  0
+/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
+#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
+
+/* Digital team to check */
+//bluetooth baseband bit11
+#define SYSTEM_BT_BASEBAND_EN  BIT(11)
+//bluetooth LC bit16 and bit17
+#define SYSTEM_BT_LC_EN  (BIT(16)|BIT(17))
+
+/* Remaining single bit clock masks */
+#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
+#define SYSTEM_WIFI_CLK_I2C_CLK_EN  BIT(5)
+#define SYSTEM_WIFI_CLK_UNUSED_BIT12  BIT(12)
+#define SYSTEM_WIFI_CLK_EMAC_EN  BIT(14)
+#define SYSTEM_WIFI_CLK_RNG_EN  BIT(15)
+
+#define SYSTEM_CORE_RST_EN_REG        SYSTEM_WIFI_RST_EN_REG
+#define SYSTEM_WIFI_RST_EN_REG        SYSCON_WIFI_RST_EN_REG
+
+/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSTEM_WIFIBB_RST           BIT(0)
+#define SYSTEM_FE_RST               BIT(1)
+#define SYSTEM_WIFIMAC_RST          BIT(2)
+#define SYSTEM_BTBB_RST             BIT(3)    /* Bluetooth Baseband */
+#define SYSTEM_BTMAC_RST            BIT(4)    /* deprecated */
+#define SYSTEM_SDIO_RST             BIT(5)
+#define SYSTEM_EMAC_RST             BIT(7)
+#define SYSTEM_MACPWR_RST           BIT(8)
+#define SYSTEM_RW_BTMAC_RST         BIT(9)    /* Bluetooth MAC */
+#define SYSTEM_RW_BTLP_RST          BIT(10)   /* Bluetooth Low Power Module */
+#define SYSTEM_RW_BTMAC_REG_RST     BIT(11)   /* Bluetooth MAC Registers */
+#define SYSTEM_RW_BTLP_REG_RST      BIT(12)   /* Bluetooth Low Power Registers */
+#define SYSTEM_BTBB_REG_RST         BIT(13)   /* Bluetooth Baseband Registers */
+
+#define MODEM_RESET_FIELD_WHEN_PU   (SYSTEM_WIFIBB_RST       | \
+                                     SYSTEM_FE_RST           | \
+                                     SYSTEM_WIFIMAC_RST      | \
+                                     SYSTEM_BTBB_RST         | \
+                                     SYSTEM_BTMAC_RST        | \
+                                     SYSTEM_RW_BTMAC_RST     | \
+                                     SYSTEM_RW_BTMAC_REG_RST | \
+                                     SYSTEM_BTBB_REG_RST)
+
+#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x01C)
+/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SYSCON_PERI_IO_SWAP  0x000000FF
+#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
+#define SYSCON_PERI_IO_SWAP_V  0xFF
+#define SYSCON_PERI_IO_SWAP_S  0
+
+#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x020)
+/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_EXT_MEM_PMS_LOCK  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
+#define SYSCON_EXT_MEM_PMS_LOCK_S  0
+
+#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x028)
+/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_ATTR  0x00000003
+#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
+#define SYSCON_FLASH_ACE0_ATTR_V  0x3
+#define SYSCON_FLASH_ACE0_ATTR_S  0
+
+#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x02C)
+/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_ATTR  0x00000003
+#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
+#define SYSCON_FLASH_ACE1_ATTR_V  0x3
+#define SYSCON_FLASH_ACE1_ATTR_S  0
+
+#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x030)
+/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_ATTR  0x00000003
+#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
+#define SYSCON_FLASH_ACE2_ATTR_V  0x3
+#define SYSCON_FLASH_ACE2_ATTR_S  0
+
+#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x034)
+/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_ATTR  0x00000003
+#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
+#define SYSCON_FLASH_ACE3_ATTR_V  0x3
+#define SYSCON_FLASH_ACE3_ATTR_S  0
+
+#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x038)
+/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
+#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x03C)
+/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
+#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x040)
+/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
+#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x044)
+/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
+#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x048)
+/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_SIZE  0x00001FFF
+#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
+#define SYSCON_FLASH_ACE0_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE0_SIZE_S  0
+
+#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x04C)
+/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_SIZE  0x00001FFF
+#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
+#define SYSCON_FLASH_ACE1_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE1_SIZE_S  0
+
+#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x050)
+/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_SIZE  0x00001FFF
+#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
+#define SYSCON_FLASH_ACE2_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE2_SIZE_S  0
+
+#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x054)
+/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_SIZE  0x00001FFF
+#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
+#define SYSCON_FLASH_ACE3_SIZE_V  0x1FFF
+#define SYSCON_FLASH_ACE3_SIZE_S  0
+
+#define SYSCON_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x088)
+/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: */
+#define SYSCON_SPI_MEM_REJECT_CDE  0x0000001F
+#define SYSCON_SPI_MEM_REJECT_CDE_M  ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
+#define SYSCON_SPI_MEM_REJECT_CDE_V  0x1F
+#define SYSCON_SPI_MEM_REJECT_CDE_S  2
+/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI_MEM_REJECT_CLR  (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_V  0x1
+#define SYSCON_SPI_MEM_REJECT_CLR_S  1
+/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI_MEM_REJECT_INT  (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_V  0x1
+#define SYSCON_SPI_MEM_REJECT_INT_S  0
+
+#define SYSCON_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x08C)
+/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_SPI_MEM_REJECT_ADDR  0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_M  ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
+#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
+
+#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x090)
+/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_SDIO_WIN_ACCESS_EN  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
+#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
+
+#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x094)
+/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_REDCY_ANDOR  (BIT(31))
+#define SYSCON_REDCY_ANDOR_M  (BIT(31))
+#define SYSCON_REDCY_ANDOR_V  0x1
+#define SYSCON_REDCY_ANDOR_S  31
+/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define SYSCON_REDCY_SIG0  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
+#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_S  0
+
+#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x098)
+/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_REDCY_NANDOR  (BIT(31))
+#define SYSCON_REDCY_NANDOR_M  (BIT(31))
+#define SYSCON_REDCY_NANDOR_V  0x1
+#define SYSCON_REDCY_NANDOR_S  31
+/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define SYSCON_REDCY_SIG1  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
+#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_S  0
+
+#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x09C)
+/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_DC_MEM_FORCE_PD  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_V  0x1
+#define SYSCON_DC_MEM_FORCE_PD_S  5
+/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_DC_MEM_FORCE_PU  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_V  0x1
+#define SYSCON_DC_MEM_FORCE_PU_S  4
+/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PBUS_MEM_FORCE_PD  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PD_S  3
+/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_PBUS_MEM_FORCE_PU  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PU_S  2
+/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_AGC_MEM_FORCE_PD  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PD_S  1
+/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_AGC_MEM_FORCE_PU  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PU_S  0
+
+#define SYSCON_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0x0A0)
+/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_NOBYPASS_CPU_ISO_RST  (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x1
+#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
+/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: */
+#define SYSCON_RETENTION_LINK_ADDR  0x07FFFFFF
+#define SYSCON_RETENTION_LINK_ADDR_M  ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
+#define SYSCON_RETENTION_LINK_ADDR_V  0x7FFFFFF
+#define SYSCON_RETENTION_LINK_ADDR_S  0
+
+#define SYSCON_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0x0A4)
+/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
+/*description: */
+#define SYSCON_SRAM_CLKGATE_FORCE_ON  0x0000000F
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0xF
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  2
+/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SYSCON_ROM_CLKGATE_FORCE_ON  0x00000003
+#define SYSCON_ROM_CLKGATE_FORCE_ON_M  ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
+#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x3
+#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
+
+#define SYSCON_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0x0A8)
+/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
+/*description: */
+#define SYSCON_SRAM_POWER_DOWN  0x0000000F
+#define SYSCON_SRAM_POWER_DOWN_M  ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
+#define SYSCON_SRAM_POWER_DOWN_V  0xF
+#define SYSCON_SRAM_POWER_DOWN_S  2
+/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SYSCON_ROM_POWER_DOWN  0x00000003
+#define SYSCON_ROM_POWER_DOWN_M  ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
+#define SYSCON_ROM_POWER_DOWN_V  0x3
+#define SYSCON_ROM_POWER_DOWN_S  0
+
+#define SYSCON_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0x0AC)
+/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
+/*description: */
+#define SYSCON_SRAM_POWER_UP  0x0000000F
+#define SYSCON_SRAM_POWER_UP_M  ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
+#define SYSCON_SRAM_POWER_UP_V  0xF
+#define SYSCON_SRAM_POWER_UP_S  2
+/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define SYSCON_ROM_POWER_UP  0x00000003
+#define SYSCON_ROM_POWER_UP_M  ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
+#define SYSCON_ROM_POWER_UP_V  0x3
+#define SYSCON_ROM_POWER_UP_S  0
+
+#define SYSCON_RND_DATA_REG          (DR_REG_SYSCON_BASE + 0x0B0)
+/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SYSCON_RND_DATA  0xFFFFFFFF
+#define SYSCON_RND_DATA_M  ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
+#define SYSCON_RND_DATA_V  0xFFFFFFFF
+#define SYSCON_RND_DATA_S  0
+
+#define SYSCON_PERI_BACKUP_CONFIG_REG          (DR_REG_SYSCON_BASE + 0x0B4)
+/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ENA  (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_M  (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_ENA_S  31
+/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_TO_MEM  (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_M  (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_V  0x1
+#define SYSCON_PERI_BACKUP_TO_MEM_S  30
+/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_START  (BIT(29))
+#define SYSCON_PERI_BACKUP_START_M  (BIT(29))
+#define SYSCON_PERI_BACKUP_START_V  0x1
+#define SYSCON_PERI_BACKUP_START_S  29
+/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_SIZE  0x000003FF
+#define SYSCON_PERI_BACKUP_SIZE_M  ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
+#define SYSCON_PERI_BACKUP_SIZE_V  0x3FF
+#define SYSCON_PERI_BACKUP_SIZE_S  19
+/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_TOUT_THRES  0x000003FF
+#define SYSCON_PERI_BACKUP_TOUT_THRES_M  ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S))
+#define SYSCON_PERI_BACKUP_TOUT_THRES_V  0x3FF
+#define SYSCON_PERI_BACKUP_TOUT_THRES_S  9
+/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_BURST_LIMIT  0x0000001F
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_M  ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_V  0x1F
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_S  4
+/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_FLOW_ERR  0x00000003
+#define SYSCON_PERI_BACKUP_FLOW_ERR_M  ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
+#define SYSCON_PERI_BACKUP_FLOW_ERR_V  0x3
+#define SYSCON_PERI_BACKUP_FLOW_ERR_S  1
+
+#define SYSCON_PERI_BACKUP_APB_ADDR_REG          (DR_REG_SYSCON_BASE + 0x0B8)
+/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define SYSCON_BACKUP_APB_START_ADDR  0xFFFFFFFF
+#define SYSCON_BACKUP_APB_START_ADDR_M  ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
+#define SYSCON_BACKUP_APB_START_ADDR_V  0xFFFFFFFF
+#define SYSCON_BACKUP_APB_START_ADDR_S  0
+
+#define SYSCON_PERI_BACKUP_MEM_ADDR_REG          (DR_REG_SYSCON_BASE + 0x0BC)
+/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define SYSCON_BACKUP_MEM_START_ADDR  0xFFFFFFFF
+#define SYSCON_BACKUP_MEM_START_ADDR_M  ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
+#define SYSCON_BACKUP_MEM_START_ADDR_V  0xFFFFFFFF
+#define SYSCON_BACKUP_MEM_START_ADDR_S  0
+
+#define SYSCON_PERI_BACKUP_INT_RAW_REG          (DR_REG_SYSCON_BASE + 0x0C0)
+/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S  0
+
+#define SYSCON_PERI_BACKUP_INT_ST_REG          (DR_REG_SYSCON_BASE + 0x0C4)
+/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ERR_INT_ST  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_DONE_INT_ST  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_S  0
+
+#define SYSCON_PERI_BACKUP_INT_ENA_REG          (DR_REG_SYSCON_BASE + 0x0C8)
+/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S  0
+
+#define SYSCON_PERI_BACKUP_INT_CLR_REG          (DR_REG_SYSCON_BASE + 0x0D0)
+/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M  (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V  0x1
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S  1
+/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M  (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V  0x1
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S  0
+
+#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
+/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
+/*description: Version control*/
+#define SYSCON_DATE  0xFFFFFFFF
+#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
+#define SYSCON_DATE_V  0xFFFFFFFF
+#define SYSCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSCON_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/syscon_struct.h b/components/soc/esp32c3/register/soc/syscon_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/syscon_struct.h
rename to components/soc/esp32c3/register/soc/syscon_struct.h
diff --git a/components/soc/esp32c3/register/soc/system_reg.h b/components/soc/esp32c3/register/soc/system_reg.h
new file mode 100644
index 00000000000..b82ae418440
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/system_reg.h
@@ -0,0 +1,1018 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSTEM_REG_H_
+#define _SOC_SYSTEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define SYSTEM_CPU_PERI_CLK_EN_REG          (DR_REG_SYSTEM_BASE + 0x000)
+/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CLK_EN_DEDICATED_GPIO  (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_M  (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_V  0x1
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_S  7
+/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CLK_EN_ASSIST_DEBUG  (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_M  (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_V  0x1
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_S  6
+
+#define SYSTEM_CPU_PERI_RST_EN_REG          (DR_REG_SYSTEM_BASE + 0x004)
+/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_RST_EN_DEDICATED_GPIO  (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_M  (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_V  0x1
+#define SYSTEM_RST_EN_DEDICATED_GPIO_S  7
+/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_RST_EN_ASSIST_DEBUG  (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_M  (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_V  0x1
+#define SYSTEM_RST_EN_ASSIST_DEBUG_S  6
+
+#define SYSTEM_CPU_PER_CONF_REG          (DR_REG_SYSTEM_BASE + 0x008)
+/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: */
+#define SYSTEM_CPU_WAITI_DELAY_NUM  0x0000000F
+#define SYSTEM_CPU_WAITI_DELAY_NUM_M  ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S))
+#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0xF
+#define SYSTEM_CPU_WAITI_DELAY_NUM_S  4
+/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON  (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x1
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  3
+/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_PLL_FREQ_SEL  (BIT(2))
+#define SYSTEM_PLL_FREQ_SEL_M  (BIT(2))
+#define SYSTEM_PLL_FREQ_SEL_V  0x1
+#define SYSTEM_PLL_FREQ_SEL_S  2
+/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define SYSTEM_CPUPERIOD_SEL  0x00000003
+#define SYSTEM_CPUPERIOD_SEL_M  ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S))
+#define SYSTEM_CPUPERIOD_SEL_V  0x3
+#define SYSTEM_CPUPERIOD_SEL_S  0
+
+#define SYSTEM_MEM_PD_MASK_REG          (DR_REG_SYSTEM_BASE + 0x00C)
+/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_LSLP_MEM_PD_MASK  (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_M  (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_V  0x1
+#define SYSTEM_LSLP_MEM_PD_MASK_S  0
+
+#define SYSTEM_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x010)
+/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
+/*description: */
+#define SYSTEM_SPI4_CLK_EN  (BIT(31))
+#define SYSTEM_SPI4_CLK_EN_M  (BIT(31))
+#define SYSTEM_SPI4_CLK_EN_V  0x1
+#define SYSTEM_SPI4_CLK_EN_S  31
+/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_ADC2_ARB_CLK_EN  (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_M  (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_V  0x1
+#define SYSTEM_ADC2_ARB_CLK_EN_S  30
+/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SYSTIMER_CLK_EN  (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_M  (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_V  0x1
+#define SYSTEM_SYSTIMER_CLK_EN_S  29
+/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_APB_SARADC_CLK_EN  (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_M  (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_V  0x1
+#define SYSTEM_APB_SARADC_CLK_EN_S  28
+/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI3_DMA_CLK_EN  (BIT(27))
+#define SYSTEM_SPI3_DMA_CLK_EN_M  (BIT(27))
+#define SYSTEM_SPI3_DMA_CLK_EN_V  0x1
+#define SYSTEM_SPI3_DMA_CLK_EN_S  27
+/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM3_CLK_EN  (BIT(26))
+#define SYSTEM_PWM3_CLK_EN_M  (BIT(26))
+#define SYSTEM_PWM3_CLK_EN_V  0x1
+#define SYSTEM_PWM3_CLK_EN_S  26
+/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM2_CLK_EN  (BIT(25))
+#define SYSTEM_PWM2_CLK_EN_M  (BIT(25))
+#define SYSTEM_PWM2_CLK_EN_V  0x1
+#define SYSTEM_PWM2_CLK_EN_S  25
+/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_UART_MEM_CLK_EN  (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_M  (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_V  0x1
+#define SYSTEM_UART_MEM_CLK_EN_S  24
+/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_USB_DEVICE_CLK_EN  (BIT(23))
+#define SYSTEM_USB_DEVICE_CLK_EN_M  (BIT(23))
+#define SYSTEM_USB_DEVICE_CLK_EN_V  0x1
+#define SYSTEM_USB_DEVICE_CLK_EN_S  23
+/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI2_DMA_CLK_EN  (BIT(22))
+#define SYSTEM_SPI2_DMA_CLK_EN_M  (BIT(22))
+#define SYSTEM_SPI2_DMA_CLK_EN_V  0x1
+#define SYSTEM_SPI2_DMA_CLK_EN_S  22
+/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2S0_CLK_EN  (BIT(21))
+#define SYSTEM_I2S0_CLK_EN_M  (BIT(21))
+#define SYSTEM_I2S0_CLK_EN_V  0x1
+#define SYSTEM_I2S0_CLK_EN_S  21
+/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM1_CLK_EN  (BIT(20))
+#define SYSTEM_PWM1_CLK_EN_M  (BIT(20))
+#define SYSTEM_PWM1_CLK_EN_V  0x1
+#define SYSTEM_PWM1_CLK_EN_S  20
+/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TWAI_CLK_EN  (BIT(19))
+#define SYSTEM_TWAI_CLK_EN_M  (BIT(19))
+#define SYSTEM_TWAI_CLK_EN_V  0x1
+#define SYSTEM_TWAI_CLK_EN_S  19
+/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2C_EXT1_CLK_EN  (BIT(18))
+#define SYSTEM_I2C_EXT1_CLK_EN_M  (BIT(18))
+#define SYSTEM_I2C_EXT1_CLK_EN_V  0x1
+#define SYSTEM_I2C_EXT1_CLK_EN_S  18
+/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM0_CLK_EN  (BIT(17))
+#define SYSTEM_PWM0_CLK_EN_M  (BIT(17))
+#define SYSTEM_PWM0_CLK_EN_V  0x1
+#define SYSTEM_PWM0_CLK_EN_S  17
+/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI3_CLK_EN  (BIT(16))
+#define SYSTEM_SPI3_CLK_EN_M  (BIT(16))
+#define SYSTEM_SPI3_CLK_EN_V  0x1
+#define SYSTEM_SPI3_CLK_EN_S  16
+/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_TIMERGROUP1_CLK_EN  (BIT(15))
+#define SYSTEM_TIMERGROUP1_CLK_EN_M  (BIT(15))
+#define SYSTEM_TIMERGROUP1_CLK_EN_V  0x1
+#define SYSTEM_TIMERGROUP1_CLK_EN_S  15
+/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_EFUSE_CLK_EN  (BIT(14))
+#define SYSTEM_EFUSE_CLK_EN_M  (BIT(14))
+#define SYSTEM_EFUSE_CLK_EN_V  0x1
+#define SYSTEM_EFUSE_CLK_EN_S  14
+/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_TIMERGROUP_CLK_EN  (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_M  (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_V  0x1
+#define SYSTEM_TIMERGROUP_CLK_EN_S  13
+/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UHCI1_CLK_EN  (BIT(12))
+#define SYSTEM_UHCI1_CLK_EN_M  (BIT(12))
+#define SYSTEM_UHCI1_CLK_EN_V  0x1
+#define SYSTEM_UHCI1_CLK_EN_S  12
+/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LEDC_CLK_EN  (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_M  (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_V  0x1
+#define SYSTEM_LEDC_CLK_EN_S  11
+/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PCNT_CLK_EN  (BIT(10))
+#define SYSTEM_PCNT_CLK_EN_M  (BIT(10))
+#define SYSTEM_PCNT_CLK_EN_V  0x1
+#define SYSTEM_PCNT_CLK_EN_S  10
+/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RMT_CLK_EN  (BIT(9))
+#define SYSTEM_RMT_CLK_EN_M  (BIT(9))
+#define SYSTEM_RMT_CLK_EN_V  0x1
+#define SYSTEM_RMT_CLK_EN_S  9
+/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UHCI0_CLK_EN  (BIT(8))
+#define SYSTEM_UHCI0_CLK_EN_M  (BIT(8))
+#define SYSTEM_UHCI0_CLK_EN_V  0x1
+#define SYSTEM_UHCI0_CLK_EN_S  8
+/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2C_EXT0_CLK_EN  (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_M  (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_V  0x1
+#define SYSTEM_I2C_EXT0_CLK_EN_S  7
+/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI2_CLK_EN  (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_M  (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_V  0x1
+#define SYSTEM_SPI2_CLK_EN_S  6
+/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_UART1_CLK_EN  (BIT(5))
+#define SYSTEM_UART1_CLK_EN_M  (BIT(5))
+#define SYSTEM_UART1_CLK_EN_V  0x1
+#define SYSTEM_UART1_CLK_EN_S  5
+/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_WDG_CLK_EN  (BIT(3))
+#define SYSTEM_WDG_CLK_EN_M  (BIT(3))
+#define SYSTEM_WDG_CLK_EN_V  0x1
+#define SYSTEM_WDG_CLK_EN_S  3
+/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_UART_CLK_EN  (BIT(2))
+#define SYSTEM_UART_CLK_EN_M  (BIT(2))
+#define SYSTEM_UART_CLK_EN_V  0x1
+#define SYSTEM_UART_CLK_EN_S  2
+/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SPI01_CLK_EN  (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_M  (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_V  0x1
+#define SYSTEM_SPI01_CLK_EN_S  1
+/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_TIMERS_CLK_EN  (BIT(0))
+#define SYSTEM_TIMERS_CLK_EN_M  (BIT(0))
+#define SYSTEM_TIMERS_CLK_EN_V  0x1
+#define SYSTEM_TIMERS_CLK_EN_S  0
+
+#define SYSTEM_PERIP_CLK_EN1_REG          (DR_REG_SYSTEM_BASE + 0x014)
+/* SYSTEM_TSENS_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TSENS_CLK_EN  (BIT(10))
+#define SYSTEM_TSENS_CLK_EN_M  (BIT(10))
+#define SYSTEM_TSENS_CLK_EN_V  0x1
+#define SYSTEM_TSENS_CLK_EN_S  10
+/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LCD_CAM_CLK_EN  (BIT(8))
+#define SYSTEM_LCD_CAM_CLK_EN_M  (BIT(8))
+#define SYSTEM_LCD_CAM_CLK_EN_V  0x1
+#define SYSTEM_LCD_CAM_CLK_EN_S  8
+/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SDIO_HOST_CLK_EN  (BIT(7))
+#define SYSTEM_SDIO_HOST_CLK_EN_M  (BIT(7))
+#define SYSTEM_SDIO_HOST_CLK_EN_V  0x1
+#define SYSTEM_SDIO_HOST_CLK_EN_S  7
+/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_DMA_CLK_EN  (BIT(6))
+#define SYSTEM_DMA_CLK_EN_M  (BIT(6))
+#define SYSTEM_DMA_CLK_EN_V  0x1
+#define SYSTEM_DMA_CLK_EN_S  6
+/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_HMAC_CLK_EN  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_M  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_S  5
+/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_DS_CLK_EN  (BIT(4))
+#define SYSTEM_CRYPTO_DS_CLK_EN_M  (BIT(4))
+#define SYSTEM_CRYPTO_DS_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_DS_CLK_EN_S  4
+/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_RSA_CLK_EN  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_CLK_EN_M  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_RSA_CLK_EN_S  3
+/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_SHA_CLK_EN  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_M  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_SHA_CLK_EN_S  2
+/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CRYPTO_AES_CLK_EN  (BIT(1))
+#define SYSTEM_CRYPTO_AES_CLK_EN_M  (BIT(1))
+#define SYSTEM_CRYPTO_AES_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_AES_CLK_EN_S  1
+
+#define SYSTEM_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x018)
+/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SYSTEM_SPI4_RST  (BIT(31))
+#define SYSTEM_SPI4_RST_M  (BIT(31))
+#define SYSTEM_SPI4_RST_V  0x1
+#define SYSTEM_SPI4_RST_S  31
+/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ADC2_ARB_RST  (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_M  (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_V  0x1
+#define SYSTEM_ADC2_ARB_RST_S  30
+/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SYSTIMER_RST  (BIT(29))
+#define SYSTEM_SYSTIMER_RST_M  (BIT(29))
+#define SYSTEM_SYSTIMER_RST_V  0x1
+#define SYSTEM_SYSTIMER_RST_S  29
+/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_APB_SARADC_RST  (BIT(28))
+#define SYSTEM_APB_SARADC_RST_M  (BIT(28))
+#define SYSTEM_APB_SARADC_RST_V  0x1
+#define SYSTEM_APB_SARADC_RST_S  28
+/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI3_DMA_RST  (BIT(27))
+#define SYSTEM_SPI3_DMA_RST_M  (BIT(27))
+#define SYSTEM_SPI3_DMA_RST_V  0x1
+#define SYSTEM_SPI3_DMA_RST_S  27
+/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM3_RST  (BIT(26))
+#define SYSTEM_PWM3_RST_M  (BIT(26))
+#define SYSTEM_PWM3_RST_V  0x1
+#define SYSTEM_PWM3_RST_S  26
+/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM2_RST  (BIT(25))
+#define SYSTEM_PWM2_RST_M  (BIT(25))
+#define SYSTEM_PWM2_RST_V  0x1
+#define SYSTEM_PWM2_RST_S  25
+/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UART_MEM_RST  (BIT(24))
+#define SYSTEM_UART_MEM_RST_M  (BIT(24))
+#define SYSTEM_UART_MEM_RST_V  0x1
+#define SYSTEM_UART_MEM_RST_S  24
+/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_USB_DEVICE_RST  (BIT(23))
+#define SYSTEM_USB_DEVICE_RST_M  (BIT(23))
+#define SYSTEM_USB_DEVICE_RST_V  0x1
+#define SYSTEM_USB_DEVICE_RST_S  23
+/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI2_DMA_RST  (BIT(22))
+#define SYSTEM_SPI2_DMA_RST_M  (BIT(22))
+#define SYSTEM_SPI2_DMA_RST_V  0x1
+#define SYSTEM_SPI2_DMA_RST_S  22
+/* SYSTEM_I2S0_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2S0_RST  (BIT(21))
+#define SYSTEM_I2S0_RST_M  (BIT(21))
+#define SYSTEM_I2S0_RST_V  0x1
+#define SYSTEM_I2S0_RST_S  21
+/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM1_RST  (BIT(20))
+#define SYSTEM_PWM1_RST_M  (BIT(20))
+#define SYSTEM_PWM1_RST_V  0x1
+#define SYSTEM_PWM1_RST_S  20
+/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TWAI_RST  (BIT(19))
+#define SYSTEM_TWAI_RST_M  (BIT(19))
+#define SYSTEM_TWAI_RST_V  0x1
+#define SYSTEM_TWAI_RST_S  19
+/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2C_EXT1_RST  (BIT(18))
+#define SYSTEM_I2C_EXT1_RST_M  (BIT(18))
+#define SYSTEM_I2C_EXT1_RST_V  0x1
+#define SYSTEM_I2C_EXT1_RST_S  18
+/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PWM0_RST  (BIT(17))
+#define SYSTEM_PWM0_RST_M  (BIT(17))
+#define SYSTEM_PWM0_RST_V  0x1
+#define SYSTEM_PWM0_RST_S  17
+/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI3_RST  (BIT(16))
+#define SYSTEM_SPI3_RST_M  (BIT(16))
+#define SYSTEM_SPI3_RST_V  0x1
+#define SYSTEM_SPI3_RST_S  16
+/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TIMERGROUP1_RST  (BIT(15))
+#define SYSTEM_TIMERGROUP1_RST_M  (BIT(15))
+#define SYSTEM_TIMERGROUP1_RST_V  0x1
+#define SYSTEM_TIMERGROUP1_RST_S  15
+/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_EFUSE_RST  (BIT(14))
+#define SYSTEM_EFUSE_RST_M  (BIT(14))
+#define SYSTEM_EFUSE_RST_V  0x1
+#define SYSTEM_EFUSE_RST_S  14
+/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TIMERGROUP_RST  (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_M  (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_V  0x1
+#define SYSTEM_TIMERGROUP_RST_S  13
+/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UHCI1_RST  (BIT(12))
+#define SYSTEM_UHCI1_RST_M  (BIT(12))
+#define SYSTEM_UHCI1_RST_V  0x1
+#define SYSTEM_UHCI1_RST_S  12
+/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LEDC_RST  (BIT(11))
+#define SYSTEM_LEDC_RST_M  (BIT(11))
+#define SYSTEM_LEDC_RST_V  0x1
+#define SYSTEM_LEDC_RST_S  11
+/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_PCNT_RST  (BIT(10))
+#define SYSTEM_PCNT_RST_M  (BIT(10))
+#define SYSTEM_PCNT_RST_V  0x1
+#define SYSTEM_PCNT_RST_S  10
+/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RMT_RST  (BIT(9))
+#define SYSTEM_RMT_RST_M  (BIT(9))
+#define SYSTEM_RMT_RST_V  0x1
+#define SYSTEM_RMT_RST_S  9
+/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UHCI0_RST  (BIT(8))
+#define SYSTEM_UHCI0_RST_M  (BIT(8))
+#define SYSTEM_UHCI0_RST_V  0x1
+#define SYSTEM_UHCI0_RST_S  8
+/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_I2C_EXT0_RST  (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_M  (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_V  0x1
+#define SYSTEM_I2C_EXT0_RST_S  7
+/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI2_RST  (BIT(6))
+#define SYSTEM_SPI2_RST_M  (BIT(6))
+#define SYSTEM_SPI2_RST_V  0x1
+#define SYSTEM_SPI2_RST_S  6
+/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UART1_RST  (BIT(5))
+#define SYSTEM_UART1_RST_M  (BIT(5))
+#define SYSTEM_UART1_RST_V  0x1
+#define SYSTEM_UART1_RST_S  5
+/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_WDG_RST  (BIT(3))
+#define SYSTEM_WDG_RST_M  (BIT(3))
+#define SYSTEM_WDG_RST_V  0x1
+#define SYSTEM_WDG_RST_S  3
+/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_UART_RST  (BIT(2))
+#define SYSTEM_UART_RST_M  (BIT(2))
+#define SYSTEM_UART_RST_V  0x1
+#define SYSTEM_UART_RST_S  2
+/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_SPI01_RST  (BIT(1))
+#define SYSTEM_SPI01_RST_M  (BIT(1))
+#define SYSTEM_SPI01_RST_V  0x1
+#define SYSTEM_SPI01_RST_S  1
+/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TIMERS_RST  (BIT(0))
+#define SYSTEM_TIMERS_RST_M  (BIT(0))
+#define SYSTEM_TIMERS_RST_V  0x1
+#define SYSTEM_TIMERS_RST_S  0
+
+#define SYSTEM_PERIP_RST_EN1_REG          (DR_REG_SYSTEM_BASE + 0x01C)
+/* SYSTEM_TSENS_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_TSENS_RST  (BIT(10))
+#define SYSTEM_TSENS_RST_M  (BIT(10))
+#define SYSTEM_TSENS_RST_V  0x1
+#define SYSTEM_TSENS_RST_S  10
+/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_LCD_CAM_RST  (BIT(8))
+#define SYSTEM_LCD_CAM_RST_M  (BIT(8))
+#define SYSTEM_LCD_CAM_RST_V  0x1
+#define SYSTEM_LCD_CAM_RST_S  8
+/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_SDIO_HOST_RST  (BIT(7))
+#define SYSTEM_SDIO_HOST_RST_M  (BIT(7))
+#define SYSTEM_SDIO_HOST_RST_V  0x1
+#define SYSTEM_SDIO_HOST_RST_S  7
+/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_DMA_RST  (BIT(6))
+#define SYSTEM_DMA_RST_M  (BIT(6))
+#define SYSTEM_DMA_RST_V  0x1
+#define SYSTEM_DMA_RST_S  6
+/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_HMAC_RST  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_RST_M  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_RST_V  0x1
+#define SYSTEM_CRYPTO_HMAC_RST_S  5
+/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_DS_RST  (BIT(4))
+#define SYSTEM_CRYPTO_DS_RST_M  (BIT(4))
+#define SYSTEM_CRYPTO_DS_RST_V  0x1
+#define SYSTEM_CRYPTO_DS_RST_S  4
+/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_RSA_RST  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_RST_M  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_RST_V  0x1
+#define SYSTEM_CRYPTO_RSA_RST_S  3
+/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_SHA_RST  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_M  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_V  0x1
+#define SYSTEM_CRYPTO_SHA_RST_S  2
+/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CRYPTO_AES_RST  (BIT(1))
+#define SYSTEM_CRYPTO_AES_RST_M  (BIT(1))
+#define SYSTEM_CRYPTO_AES_RST_V  0x1
+#define SYSTEM_CRYPTO_AES_RST_S  1
+
+#define SYSTEM_BT_LPCK_DIV_INT_REG          (DR_REG_SYSTEM_BASE + 0x020)
+/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
+/*description: */
+#define SYSTEM_BT_LPCK_DIV_NUM  0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_NUM_M  ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
+#define SYSTEM_BT_LPCK_DIV_NUM_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_NUM_S  0
+
+#define SYSTEM_BT_LPCK_DIV_FRAC_REG          (DR_REG_SYSTEM_BASE + 0x024)
+/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LPCLK_RTC_EN  (BIT(28))
+#define SYSTEM_LPCLK_RTC_EN_M  (BIT(28))
+#define SYSTEM_LPCLK_RTC_EN_V  0x1
+#define SYSTEM_LPCLK_RTC_EN_S  28
+/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LPCLK_SEL_XTAL32K  (BIT(27))
+#define SYSTEM_LPCLK_SEL_XTAL32K_M  (BIT(27))
+#define SYSTEM_LPCLK_SEL_XTAL32K_V  0x1
+#define SYSTEM_LPCLK_SEL_XTAL32K_S  27
+/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LPCLK_SEL_XTAL  (BIT(26))
+#define SYSTEM_LPCLK_SEL_XTAL_M  (BIT(26))
+#define SYSTEM_LPCLK_SEL_XTAL_V  0x1
+#define SYSTEM_LPCLK_SEL_XTAL_S  26
+/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_LPCLK_SEL_8M  (BIT(25))
+#define SYSTEM_LPCLK_SEL_8M_M  (BIT(25))
+#define SYSTEM_LPCLK_SEL_8M_V  0x1
+#define SYSTEM_LPCLK_SEL_8M_S  25
+/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_LPCLK_SEL_RTC_SLOW  (BIT(24))
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_V  0x1
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_S  24
+/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
+/*description: */
+#define SYSTEM_BT_LPCK_DIV_A  0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_A_M  ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S))
+#define SYSTEM_BT_LPCK_DIV_A_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_A_S  12
+/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
+/*description: */
+#define SYSTEM_BT_LPCK_DIV_B  0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_B_M  ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S))
+#define SYSTEM_BT_LPCK_DIV_B_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_B_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_0_REG          (DR_REG_SYSTEM_BASE + 0x028)
+/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CPU_INTR_FROM_CPU_0  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_0_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_1_REG          (DR_REG_SYSTEM_BASE + 0x02C)
+/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CPU_INTR_FROM_CPU_1  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_1_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_2_REG          (DR_REG_SYSTEM_BASE + 0x030)
+/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CPU_INTR_FROM_CPU_2  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_2_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_3_REG          (DR_REG_SYSTEM_BASE + 0x034)
+/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_CPU_INTR_FROM_CPU_3  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_3_S  0
+
+#define SYSTEM_RSA_PD_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x038)
+/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RSA_MEM_FORCE_PD  (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_M  (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_V  0x1
+#define SYSTEM_RSA_MEM_FORCE_PD_S  2
+/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RSA_MEM_FORCE_PU  (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_M  (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_V  0x1
+#define SYSTEM_RSA_MEM_FORCE_PU_S  1
+/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_RSA_MEM_PD  (BIT(0))
+#define SYSTEM_RSA_MEM_PD_M  (BIT(0))
+#define SYSTEM_RSA_MEM_PD_V  0x1
+#define SYSTEM_RSA_MEM_PD_S  0
+
+#define SYSTEM_EDMA_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x03C)
+/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_EDMA_RESET  (BIT(1))
+#define SYSTEM_EDMA_RESET_M  (BIT(1))
+#define SYSTEM_EDMA_RESET_V  0x1
+#define SYSTEM_EDMA_RESET_S  1
+/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_EDMA_CLK_ON  (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_M  (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_V  0x1
+#define SYSTEM_EDMA_CLK_ON_S  0
+
+#define SYSTEM_CACHE_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x040)
+/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_DCACHE_RESET  (BIT(3))
+#define SYSTEM_DCACHE_RESET_M  (BIT(3))
+#define SYSTEM_DCACHE_RESET_V  0x1
+#define SYSTEM_DCACHE_RESET_S  3
+/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_DCACHE_CLK_ON  (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_M  (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_V  0x1
+#define SYSTEM_DCACHE_CLK_ON_S  2
+/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ICACHE_RESET  (BIT(1))
+#define SYSTEM_ICACHE_RESET_M  (BIT(1))
+#define SYSTEM_ICACHE_RESET_V  0x1
+#define SYSTEM_ICACHE_RESET_S  1
+/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_ICACHE_CLK_ON  (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_M  (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_V  0x1
+#define SYSTEM_ICACHE_CLK_ON_S  0
+
+#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x044)
+/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT  (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT  (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT  (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT  (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+
+#define SYSTEM_RTC_FASTMEM_CONFIG_REG          (DR_REG_SYSTEM_BASE + 0x048)
+/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_FINISH  (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_M  (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_V  0x1
+#define SYSTEM_RTC_MEM_CRC_FINISH_S  31
+/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_LEN  0x000007FF
+#define SYSTEM_RTC_MEM_CRC_LEN_M  ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S))
+#define SYSTEM_RTC_MEM_CRC_LEN_V  0x7FF
+#define SYSTEM_RTC_MEM_CRC_LEN_S  20
+/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_ADDR  0x000007FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_M  ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S))
+#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x7FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_S  9
+/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_START  (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_M  (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_V  0x1
+#define SYSTEM_RTC_MEM_CRC_START_S  8
+
+#define SYSTEM_RTC_FASTMEM_CRC_REG          (DR_REG_SYSTEM_BASE + 0x04C)
+/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SYSTEM_RTC_MEM_CRC_RES  0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_M  ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S))
+#define SYSTEM_RTC_MEM_CRC_RES_V  0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_S  0
+
+#define SYSTEM_REDUNDANT_ECO_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x050)
+/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_REDUNDANT_ECO_RESULT  (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_M  (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_V  0x1
+#define SYSTEM_REDUNDANT_ECO_RESULT_S  1
+/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_REDUNDANT_ECO_DRIVE  (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_M  (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_V  0x1
+#define SYSTEM_REDUNDANT_ECO_DRIVE_S  0
+
+#define SYSTEM_CLOCK_GATE_REG          (DR_REG_SYSTEM_BASE + 0x054)
+/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CLK_EN  (BIT(0))
+#define SYSTEM_CLK_EN_M  (BIT(0))
+#define SYSTEM_CLK_EN_V  0x1
+#define SYSTEM_CLK_EN_S  0
+
+#define SYSTEM_SYSCLK_CONF_REG          (DR_REG_SYSTEM_BASE + 0x058)
+/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: */
+#define SYSTEM_CLK_DIV_EN  (BIT(19))
+#define SYSTEM_CLK_DIV_EN_M  (BIT(19))
+#define SYSTEM_CLK_DIV_EN_V  0x1
+#define SYSTEM_CLK_DIV_EN_S  19
+/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */
+/*description: */
+#define SYSTEM_CLK_XTAL_FREQ  0x0000007F
+#define SYSTEM_CLK_XTAL_FREQ_M  ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S))
+#define SYSTEM_CLK_XTAL_FREQ_V  0x7F
+#define SYSTEM_CLK_XTAL_FREQ_S  12
+/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: */
+#define SYSTEM_SOC_CLK_SEL  0x00000003
+#define SYSTEM_SOC_CLK_SEL_M  ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S))
+#define SYSTEM_SOC_CLK_SEL_V  0x3
+#define SYSTEM_SOC_CLK_SEL_S  10
+/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: */
+#define SYSTEM_PRE_DIV_CNT  0x000003FF
+#define SYSTEM_PRE_DIV_CNT_M  ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
+#define SYSTEM_PRE_DIV_CNT_V  0x3FF
+#define SYSTEM_PRE_DIV_CNT_S  0
+
+#define SYSTEM_MEM_PVT_REG          (DR_REG_SYSTEM_BASE + 0x05C)
+/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: */
+#define SYSTEM_MEM_VT_SEL  0x00000003
+#define SYSTEM_MEM_VT_SEL_M  ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S))
+#define SYSTEM_MEM_VT_SEL_V  0x3
+#define SYSTEM_MEM_VT_SEL_S  22
+/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_MEM_TIMING_ERR_CNT  0x0000FFFF
+#define SYSTEM_MEM_TIMING_ERR_CNT_M  ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S))
+#define SYSTEM_MEM_TIMING_ERR_CNT_V  0xFFFF
+#define SYSTEM_MEM_TIMING_ERR_CNT_S  6
+/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_MEM_PVT_MONITOR_EN  (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_M  (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_V  0x1
+#define SYSTEM_MEM_PVT_MONITOR_EN_S  5
+/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_MEM_ERR_CNT_CLR  (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_M  (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_V  0x1
+#define SYSTEM_MEM_ERR_CNT_CLR_S  4
+/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */
+/*description: */
+#define SYSTEM_MEM_PATH_LEN  0x0000000F
+#define SYSTEM_MEM_PATH_LEN_M  ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S))
+#define SYSTEM_MEM_PATH_LEN_V  0xF
+#define SYSTEM_MEM_PATH_LEN_S  0
+
+#define SYSTEM_COMB_PVT_LVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x060)
+/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S  5
+/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: */
+#define SYSTEM_COMB_PATH_LEN_LVT  0x0000001F
+#define SYSTEM_COMB_PATH_LEN_LVT_M  ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
+#define SYSTEM_COMB_PATH_LEN_LVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_LVT_S  0
+
+#define SYSTEM_COMB_PVT_NVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x064)
+/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S  5
+/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: */
+#define SYSTEM_COMB_PATH_LEN_NVT  0x0000001F
+#define SYSTEM_COMB_PATH_LEN_NVT_M  ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S))
+#define SYSTEM_COMB_PATH_LEN_NVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_NVT_S  0
+
+#define SYSTEM_COMB_PVT_HVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x068)
+/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S  5
+/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: */
+#define SYSTEM_COMB_PATH_LEN_HVT  0x0000001F
+#define SYSTEM_COMB_PATH_LEN_HVT_M  ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S))
+#define SYSTEM_COMB_PATH_LEN_HVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_HVT_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x06C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x070)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x074)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x078)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x07C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x080)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x084)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x088)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x08C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x090)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x094)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x098)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3  0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S  0
+
+#define SYSTEM_DATE_REG          (DR_REG_SYSTEM_BASE + 0xFFC)
+/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007150 ; */
+/*description: */
+#define SYSTEM_DATE  0x0FFFFFFF
+#define SYSTEM_DATE_M  ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
+#define SYSTEM_DATE_V  0xFFFFFFF
+#define SYSTEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/system_struct.h b/components/soc/esp32c3/register/soc/system_struct.h
new file mode 100644
index 00000000000..66e0ccaa19f
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/system_struct.h
@@ -0,0 +1,1404 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSTEM_STRUCT_H_
+#define _SOC_SYSTEM_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+typedef volatile struct system_dev_s {
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t reg_clk_en_assist_debug       :    1;  /*reg_clk_en_assist_debug*/
+            uint32_t reg_clk_en_dedicated_gpio     :    1;  /*reg_clk_en_dedicated_gpio*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_peri_clk_en;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t reg_rst_en_assist_debug       :    1;  /*reg_rst_en_assist_debug*/
+            uint32_t reg_rst_en_dedicated_gpio     :    1;  /*reg_rst_en_dedicated_gpio*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_peri_rst_en;
+    union {
+        struct {
+            uint32_t reg_cpuperiod_sel             :    2;  /*reg_cpuperiod_sel*/
+            uint32_t reg_pll_freq_sel              :    1;  /*reg_pll_freq_sel*/
+            uint32_t reg_cpu_wait_mode_force_on    :    1;  /*reg_cpu_wait_mode_force_on*/
+            uint32_t reg_cpu_waiti_delay_num       :    4;  /*reg_cpu_waiti_delay_num*/
+            uint32_t reserved8                     :    24;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_per_conf;
+    union {
+        struct {
+            uint32_t reg_lslp_mem_pd_mask          :    1;  /*reg_lslp_mem_pd_mask*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } mem_pd_mask;
+    union {
+        struct {
+            uint32_t reg_timers_clk_en             :    1;  /*reg_timers_clk_en*/
+            uint32_t reg_spi01_clk_en              :    1;  /*reg_spi01_clk_en*/
+            uint32_t reg_uart_clk_en               :    1;  /*reg_uart_clk_en*/
+            uint32_t reg_wdg_clk_en                :    1;  /*reg_wdg_clk_en*/
+            uint32_t reserved_04                   :    1;  /*reserved*/
+            uint32_t reg_uart1_clk_en              :    1;  /*reg_uart1_clk_en*/
+            uint32_t reg_spi2_clk_en               :    1;  /*reg_spi2_clk_en*/
+            uint32_t reg_i2c_ext0_clk_en           :    1;  /*reg_i2c_ext0_clk_en*/
+            uint32_t reg_uhci0_clk_en              :    1;  /*reg_uhci0_clk_en*/
+            uint32_t reg_rmt_clk_en                :    1;  /*reg_rmt_clk_en*/
+            uint32_t reg_pcnt_clk_en               :    1;  /*reg_pcnt_clk_en*/
+            uint32_t reg_ledc_clk_en               :    1;  /*reg_ledc_clk_en*/
+            uint32_t reg_uhci1_clk_en              :    1;  /*reg_uhci1_clk_en*/
+            uint32_t reg_timergroup_clk_en         :    1;  /*reg_timergroup_clk_en*/
+            uint32_t reg_efuse_clk_en              :    1;  /*reg_efuse_clk_en*/
+            uint32_t reg_timergroup1_clk_en        :    1;  /*reg_timergroup1_clk_en*/
+            uint32_t reg_spi3_clk_en               :    1;  /*reg_spi3_clk_en*/
+            uint32_t reg_pwm0_clk_en               :    1;  /*reg_pwm0_clk_en*/
+            uint32_t reg_i2c_ext1_clk_en           :    1;  /*reg_i2c_ext1_clk_en*/
+            uint32_t reg_can_clk_en                :    1;  /*reg_can_clk_en*/
+            uint32_t reg_pwm1_clk_en               :    1;  /*reg_pwm1_clk_en*/
+            uint32_t reg_i2s0_clk_en               :    1;  /*reg_i2s0_clk_en*/
+            uint32_t reg_spi2_dma_clk_en           :    1;  /*reg_spi2_dma_clk_en*/
+            uint32_t reg_usb_device_clk_en         :    1;  /*reg_usb_device_clk_en*/
+            uint32_t reg_uart_mem_clk_en           :    1;  /*reg_uart_mem_clk_en*/
+            uint32_t reg_pwm2_clk_en               :    1;  /*reg_pwm2_clk_en*/
+            uint32_t reg_pwm3_clk_en               :    1;  /*reg_pwm3_clk_en*/
+            uint32_t reg_spi3_dma_clk_en           :    1;  /*reg_spi3_dma_clk_en*/
+            uint32_t reg_apb_saradc_clk_en         :    1;  /*reg_apb_saradc_clk_en*/
+            uint32_t reg_systimer_clk_en           :    1;  /*reg_systimer_clk_en*/
+            uint32_t reg_adc2_arb_clk_en           :    1;  /*reg_adc2_arb_clk_en*/
+            uint32_t reg_spi4_clk_en               :    1;  /*reg_spi4_clk_en*/
+        };
+        uint32_t val;
+    } perip_clk_en0;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*peripheral reset register*/
+            uint32_t reg_crypto_aes_clk_en         :    1;  /*reg_crypto_aes_clk_en*/
+            uint32_t reg_crypto_sha_clk_en         :    1;  /*reg_crypto_sha_clk_en*/
+            uint32_t reg_crypto_rsa_clk_en         :    1;  /*reg_crypto_rsa_clk_en*/
+            uint32_t reg_crypto_ds_clk_en          :    1;  /*reg_crypto_ds_clk_en*/
+            uint32_t reg_crypto_hmac_clk_en        :    1;  /*reg_crypto_hmac_clk_en*/
+            uint32_t reg_dma_clk_en                :    1;  /*reg_dma_clk_en*/
+            uint32_t reg_sdio_host_clk_en          :    1;  /*reg_sdio_host_clk_en*/
+            uint32_t reg_lcd_cam_clk_en            :    1;  /*reg_lcd_cam_clk_en*/
+            uint32_t reserved9                     :    1;  /*reserved*/
+            uint32_t reg_tsens_clk_en              :    1;  /*reg_tsens_clk_en*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } perip_clk_en1;
+    union {
+        struct {
+            uint32_t reg_timers_rst                :    1;  /*reg_timers_rst*/
+            uint32_t reg_spi01_rst                 :    1;  /*reg_spi01_rst*/
+            uint32_t reg_uart_rst                  :    1;  /*reg_uart_rst*/
+            uint32_t reg_wdg_rst                   :    1;  /*reg_wdg_rst*/
+            uint32_t reserved_04                   :    1;  /*reserved*/
+            uint32_t reg_uart1_rst                 :    1;  /*reg_uart1_rst*/
+            uint32_t reg_spi2_rst                  :    1;  /*reg_spi2_rst*/
+            uint32_t reg_i2c_ext0_rst              :    1;  /*reg_i2c_ext0_rst*/
+            uint32_t reg_uhci0_rst                 :    1;  /*reg_uhci0_rst*/
+            uint32_t reg_rmt_rst                   :    1;  /*reg_rmt_rst*/
+            uint32_t reg_pcnt_rst                  :    1;  /*reg_pcnt_rst*/
+            uint32_t reg_ledc_rst                  :    1;  /*reg_ledc_rst*/
+            uint32_t reg_uhci1_rst                 :    1;  /*reg_uhci1_rst*/
+            uint32_t reg_timergroup_rst            :    1;  /*reg_timergroup_rst*/
+            uint32_t reg_efuse_rst                 :    1;  /*reg_efuse_rst*/
+            uint32_t reg_timergroup1_rst           :    1;  /*reg_timergroup1_rst*/
+            uint32_t reg_spi3_rst                  :    1;  /*reg_spi3_rst*/
+            uint32_t reg_pwm0_rst                  :    1;  /*reg_pwm0_rst*/
+            uint32_t reg_i2c_ext1_rst              :    1;  /*reg_i2c_ext1_rst*/
+            uint32_t reg_can_rst                   :    1;  /*reg_can_rst*/
+            uint32_t reg_pwm1_rst                  :    1;  /*reg_pwm1_rst*/
+            uint32_t reg_i2s0_rst                  :    1;  /*reg_i2s0_rst*/
+            uint32_t reg_spi2_dma_rst              :    1;  /*reg_spi2_dma_rst*/
+            uint32_t reg_usb_device_rst            :    1;  /*reg_usb_device_rst*/
+            uint32_t reg_uart_mem_rst              :    1;  /*reg_uart_mem_rst*/
+            uint32_t reg_pwm2_rst                  :    1;  /*reg_pwm2_rst*/
+            uint32_t reg_pwm3_rst                  :    1;  /*reg_pwm3_rst*/
+            uint32_t reg_spi3_dma_rst              :    1;  /*reg_spi3_dma_rst*/
+            uint32_t reg_apb_saradc_rst            :    1;  /*reg_apb_saradc_rst*/
+            uint32_t reg_systimer_rst              :    1;  /*reg_systimer_rst*/
+            uint32_t reg_adc2_arb_rst              :    1;  /*reg_adc2_arb_rst*/
+            uint32_t reg_spi4_rst                  :    1;  /*reg_spi4_rst*/
+        };
+        uint32_t val;
+    } perip_rst_en0;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;  /*reserved*/
+            uint32_t reg_crypto_aes_rst            :    1;  /*reg_crypto_aes_rst*/
+            uint32_t reg_crypto_sha_rst            :    1;  /*reg_crypto_sha_rst*/
+            uint32_t reg_crypto_rsa_rst            :    1;  /*reg_crypto_rsa_rst*/
+            uint32_t reg_crypto_ds_rst             :    1;  /*reg_crypto_ds_rst*/
+            uint32_t reg_crypto_hmac_rst           :    1;  /*reg_crypto_hmac_rst*/
+            uint32_t reg_dma_rst                   :    1;  /*reg_dma_rst*/
+            uint32_t reg_sdio_host_rst             :    1;  /*reg_sdio_host_rst*/
+            uint32_t reg_lcd_cam_rst               :    1;  /*reg_lcd_cam_rst*/
+            uint32_t reserved9                     :    1;  /*reserved*/
+            uint32_t reg_tsens_rst                 :    1;  /*reg_tsens_rst*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } perip_rst_en1;
+    union {
+        struct {
+            uint32_t reg_bt_lpck_div_num           :    12;  /*reg_bt_lpck_div_num*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } bt_lpck_div_int;
+    union {
+        struct {
+            uint32_t reg_bt_lpck_div_b             :    12;  /*reg_bt_lpck_div_b*/
+            uint32_t reg_bt_lpck_div_a             :    12;  /*reg_bt_lpck_div_a*/
+            uint32_t reg_lpclk_sel_rtc_slow        :    1;  /*reg_lpclk_sel_rtc_slow*/
+            uint32_t reg_lpclk_sel_8m              :    1;  /*reg_lpclk_sel_8m*/
+            uint32_t reg_lpclk_sel_xtal            :    1;  /*reg_lpclk_sel_xtal*/
+            uint32_t reg_lpclk_sel_xtal32k         :    1;  /*reg_lpclk_sel_xtal32k*/
+            uint32_t reg_lpclk_rtc_en              :    1;  /*reg_lpclk_rtc_en*/
+            uint32_t reserved29                    :    3;  /*reserved*/
+        };
+        uint32_t val;
+    } bt_lpck_div_frac;
+    union {
+        struct {
+            uint32_t reg_cpu_intr_from_cpu_0       :    1;  /*reg_cpu_intr_from_cpu_0*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_0;
+    union {
+        struct {
+            uint32_t reg_cpu_intr_from_cpu_1       :    1;  /*reg_cpu_intr_from_cpu_1*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_1;
+    union {
+        struct {
+            uint32_t reg_cpu_intr_from_cpu_2       :    1;  /*reg_cpu_intr_from_cpu_2*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_2;
+    union {
+        struct {
+            uint32_t reg_cpu_intr_from_cpu_3       :    1;  /*reg_cpu_intr_from_cpu_3*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_3;
+    union {
+        struct {
+            uint32_t reg_rsa_mem_pd                :    1;  /*reg_rsa_mem_pd*/
+            uint32_t reg_rsa_mem_force_pu          :    1;  /*reg_rsa_mem_force_pu*/
+            uint32_t reg_rsa_mem_force_pd          :    1;  /*reg_rsa_mem_force_pd*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } rsa_pd_ctrl;
+    union {
+        struct {
+            uint32_t reg_edma_clk_on               :    1;  /*reg_edma_clk_on*/
+            uint32_t reg_edma_reset                :    1;  /*reg_edma_reset*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } edma_ctrl;
+    union {
+        struct {
+            uint32_t reg_icache_clk_on             :    1;  /*reg_icache_clk_on*/
+            uint32_t reg_icache_reset              :    1;  /*reg_icache_reset*/
+            uint32_t reg_dcache_clk_on             :    1;  /*reg_dcache_clk_on*/
+            uint32_t reg_dcache_reset              :    1;  /*reg_dcache_reset*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_control;
+    union {
+        struct {
+            uint32_t reg_enable_spi_manual_encrypt :    1;  /*reg_enable_spi_manual_encrypt*/
+            uint32_t reg_enable_download_db_encrypt:    1;  /*reg_enable_download_db_encrypt*/
+            uint32_t reg_enable_download_g0cb_decrypt:    1;  /*reg_enable_download_g0cb_decrypt*/
+            uint32_t reg_enable_download_manual_encrypt:    1;  /*reg_enable_download_manual_encrypt*/
+            uint32_t reserved4                     :    28;  /*reserved*/
+        };
+        uint32_t val;
+    } external_device_encrypt_decrypt_control;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;  /*fast memory crc register*/
+            uint32_t reg_rtc_mem_crc_start         :    1;  /*reg_rtc_mem_crc_start*/
+            uint32_t reg_rtc_mem_crc_addr          :    11;  /*reg_rtc_mem_crc_addr*/
+            uint32_t reg_rtc_mem_crc_len           :    11;  /*reg_rtc_mem_crc_len*/
+            uint32_t reg_rtc_mem_crc_finish        :    1;  /*reg_rtc_mem_crc_finish*/
+        };
+        uint32_t val;
+    } rtc_fastmem_config;
+    uint32_t rtc_fastmem_crc;
+    union {
+        struct {
+            uint32_t reg_redundant_eco_drive       :    1;  /*reg_redundant_eco_drive*/
+            uint32_t reg_redundant_eco_result      :    1;  /*reg_redundant_eco_result*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } redundant_eco_ctrl;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;  /*reg_clk_en*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t reg_pre_div_cnt               :    10;  /*reg_pre_div_cnt*/
+            uint32_t reg_soc_clk_sel               :    2;  /*reg_soc_clk_sel*/
+            uint32_t reg_clk_xtal_freq             :    7;  /*reg_clk_xtal_freq*/
+            uint32_t reg_clk_div_en                :    1;  /*reg_clk_div_en*/
+            uint32_t reserved20                    :    12;  /*reserved*/
+        };
+        uint32_t val;
+    } sysclk_conf;
+    union {
+        struct {
+            uint32_t reg_mem_path_len              :    4;  /*reg_mem_path_len*/
+            uint32_t reg_mem_err_cnt_clr           :    1;  /*reg_mem_err_cnt_clr*/
+            uint32_t reg_mem_pvt_monitor_en        :    1;  /*reg_mem_pvt_monitor_en*/
+            uint32_t reg_mem_timing_err_cnt        :    16;  /*reg_mem_timing_err_cnt*/
+            uint32_t reg_mem_vt_sel                :    2;  /*reg_mem_vt_sel*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } mem_pvt;
+    union {
+        struct {
+            uint32_t reg_comb_path_len_lvt         :    5;  /*reg_comb_path_len_lvt*/
+            uint32_t reg_comb_err_cnt_clr_lvt      :    1;  /*reg_comb_err_cnt_clr_lvt*/
+            uint32_t reg_comb_pvt_monitor_en_lvt   :    1;  /*reg_comb_pvt_monitor_en_lvt*/
+            uint32_t reserved7                     :    18;  /*reserved*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_lvt_conf;
+    union {
+        struct {
+            uint32_t reg_comb_path_len_nvt         :    5;  /*reg_comb_path_len_nvt*/
+            uint32_t reg_comb_err_cnt_clr_nvt      :    1;  /*reg_comb_err_cnt_clr_nvt*/
+            uint32_t reg_comb_pvt_monitor_en_nvt   :    1;  /*reg_comb_pvt_monitor_en_nvt*/
+            uint32_t reserved7                     :    18;  /*reserved*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_nvt_conf;
+    union {
+        struct {
+            uint32_t reg_comb_path_len_hvt         :    5;  /*reg_comb_path_len_hvt*/
+            uint32_t reg_comb_err_cnt_clr_hvt      :    1;  /*reg_comb_err_cnt_clr_hvt*/
+            uint32_t reg_comb_pvt_monitor_en_hvt   :    1;  /*reg_comb_pvt_monitor_en_hvt*/
+            uint32_t reserved7                     :    18;  /*reserved*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_hvt_conf;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_lvt_site0:    16;  /*reg_comb_timing_err_cnt_lvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site0;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_nvt_site0:    16;  /*reg_comb_timing_err_cnt_nvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site0;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_hvt_site0:    16;  /*reg_comb_timing_err_cnt_hvt_site0*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site0;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_lvt_site1:    16;  /*reg_comb_timing_err_cnt_lvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site1;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_nvt_site1:    16;  /*reg_comb_timing_err_cnt_nvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site1;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_hvt_site1:    16;  /*reg_comb_timing_err_cnt_hvt_site1*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site1;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_lvt_site2:    16;  /*reg_comb_timing_err_cnt_lvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site2;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_nvt_site2:    16;  /*reg_comb_timing_err_cnt_nvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site2;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_hvt_site2:    16;  /*reg_comb_timing_err_cnt_hvt_site2*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site2;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_lvt_site3:    16;  /*reg_comb_timing_err_cnt_lvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site3;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_nvt_site3:    16;  /*reg_comb_timing_err_cnt_nvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site3;
+    union {
+        struct {
+            uint32_t reg_comb_timing_err_cnt_hvt_site3:    16;  /*reg_comb_timing_err_cnt_hvt_site3*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site3;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t reserved_800;
+    uint32_t reserved_804;
+    uint32_t reserved_808;
+    uint32_t reserved_80c;
+    uint32_t reserved_810;
+    uint32_t reserved_814;
+    uint32_t reserved_818;
+    uint32_t reserved_81c;
+    uint32_t reserved_820;
+    uint32_t reserved_824;
+    uint32_t reserved_828;
+    uint32_t reserved_82c;
+    uint32_t reserved_830;
+    uint32_t reserved_834;
+    uint32_t reserved_838;
+    uint32_t reserved_83c;
+    uint32_t reserved_840;
+    uint32_t reserved_844;
+    uint32_t reserved_848;
+    uint32_t reserved_84c;
+    uint32_t reserved_850;
+    uint32_t reserved_854;
+    uint32_t reserved_858;
+    uint32_t reserved_85c;
+    uint32_t reserved_860;
+    uint32_t reserved_864;
+    uint32_t reserved_868;
+    uint32_t reserved_86c;
+    uint32_t reserved_870;
+    uint32_t reserved_874;
+    uint32_t reserved_878;
+    uint32_t reserved_87c;
+    uint32_t reserved_880;
+    uint32_t reserved_884;
+    uint32_t reserved_888;
+    uint32_t reserved_88c;
+    uint32_t reserved_890;
+    uint32_t reserved_894;
+    uint32_t reserved_898;
+    uint32_t reserved_89c;
+    uint32_t reserved_8a0;
+    uint32_t reserved_8a4;
+    uint32_t reserved_8a8;
+    uint32_t reserved_8ac;
+    uint32_t reserved_8b0;
+    uint32_t reserved_8b4;
+    uint32_t reserved_8b8;
+    uint32_t reserved_8bc;
+    uint32_t reserved_8c0;
+    uint32_t reserved_8c4;
+    uint32_t reserved_8c8;
+    uint32_t reserved_8cc;
+    uint32_t reserved_8d0;
+    uint32_t reserved_8d4;
+    uint32_t reserved_8d8;
+    uint32_t reserved_8dc;
+    uint32_t reserved_8e0;
+    uint32_t reserved_8e4;
+    uint32_t reserved_8e8;
+    uint32_t reserved_8ec;
+    uint32_t reserved_8f0;
+    uint32_t reserved_8f4;
+    uint32_t reserved_8f8;
+    uint32_t reserved_8fc;
+    uint32_t reserved_900;
+    uint32_t reserved_904;
+    uint32_t reserved_908;
+    uint32_t reserved_90c;
+    uint32_t reserved_910;
+    uint32_t reserved_914;
+    uint32_t reserved_918;
+    uint32_t reserved_91c;
+    uint32_t reserved_920;
+    uint32_t reserved_924;
+    uint32_t reserved_928;
+    uint32_t reserved_92c;
+    uint32_t reserved_930;
+    uint32_t reserved_934;
+    uint32_t reserved_938;
+    uint32_t reserved_93c;
+    uint32_t reserved_940;
+    uint32_t reserved_944;
+    uint32_t reserved_948;
+    uint32_t reserved_94c;
+    uint32_t reserved_950;
+    uint32_t reserved_954;
+    uint32_t reserved_958;
+    uint32_t reserved_95c;
+    uint32_t reserved_960;
+    uint32_t reserved_964;
+    uint32_t reserved_968;
+    uint32_t reserved_96c;
+    uint32_t reserved_970;
+    uint32_t reserved_974;
+    uint32_t reserved_978;
+    uint32_t reserved_97c;
+    uint32_t reserved_980;
+    uint32_t reserved_984;
+    uint32_t reserved_988;
+    uint32_t reserved_98c;
+    uint32_t reserved_990;
+    uint32_t reserved_994;
+    uint32_t reserved_998;
+    uint32_t reserved_99c;
+    uint32_t reserved_9a0;
+    uint32_t reserved_9a4;
+    uint32_t reserved_9a8;
+    uint32_t reserved_9ac;
+    uint32_t reserved_9b0;
+    uint32_t reserved_9b4;
+    uint32_t reserved_9b8;
+    uint32_t reserved_9bc;
+    uint32_t reserved_9c0;
+    uint32_t reserved_9c4;
+    uint32_t reserved_9c8;
+    uint32_t reserved_9cc;
+    uint32_t reserved_9d0;
+    uint32_t reserved_9d4;
+    uint32_t reserved_9d8;
+    uint32_t reserved_9dc;
+    uint32_t reserved_9e0;
+    uint32_t reserved_9e4;
+    uint32_t reserved_9e8;
+    uint32_t reserved_9ec;
+    uint32_t reserved_9f0;
+    uint32_t reserved_9f4;
+    uint32_t reserved_9f8;
+    uint32_t reserved_9fc;
+    uint32_t reserved_a00;
+    uint32_t reserved_a04;
+    uint32_t reserved_a08;
+    uint32_t reserved_a0c;
+    uint32_t reserved_a10;
+    uint32_t reserved_a14;
+    uint32_t reserved_a18;
+    uint32_t reserved_a1c;
+    uint32_t reserved_a20;
+    uint32_t reserved_a24;
+    uint32_t reserved_a28;
+    uint32_t reserved_a2c;
+    uint32_t reserved_a30;
+    uint32_t reserved_a34;
+    uint32_t reserved_a38;
+    uint32_t reserved_a3c;
+    uint32_t reserved_a40;
+    uint32_t reserved_a44;
+    uint32_t reserved_a48;
+    uint32_t reserved_a4c;
+    uint32_t reserved_a50;
+    uint32_t reserved_a54;
+    uint32_t reserved_a58;
+    uint32_t reserved_a5c;
+    uint32_t reserved_a60;
+    uint32_t reserved_a64;
+    uint32_t reserved_a68;
+    uint32_t reserved_a6c;
+    uint32_t reserved_a70;
+    uint32_t reserved_a74;
+    uint32_t reserved_a78;
+    uint32_t reserved_a7c;
+    uint32_t reserved_a80;
+    uint32_t reserved_a84;
+    uint32_t reserved_a88;
+    uint32_t reserved_a8c;
+    uint32_t reserved_a90;
+    uint32_t reserved_a94;
+    uint32_t reserved_a98;
+    uint32_t reserved_a9c;
+    uint32_t reserved_aa0;
+    uint32_t reserved_aa4;
+    uint32_t reserved_aa8;
+    uint32_t reserved_aac;
+    uint32_t reserved_ab0;
+    uint32_t reserved_ab4;
+    uint32_t reserved_ab8;
+    uint32_t reserved_abc;
+    uint32_t reserved_ac0;
+    uint32_t reserved_ac4;
+    uint32_t reserved_ac8;
+    uint32_t reserved_acc;
+    uint32_t reserved_ad0;
+    uint32_t reserved_ad4;
+    uint32_t reserved_ad8;
+    uint32_t reserved_adc;
+    uint32_t reserved_ae0;
+    uint32_t reserved_ae4;
+    uint32_t reserved_ae8;
+    uint32_t reserved_aec;
+    uint32_t reserved_af0;
+    uint32_t reserved_af4;
+    uint32_t reserved_af8;
+    uint32_t reserved_afc;
+    uint32_t reserved_b00;
+    uint32_t reserved_b04;
+    uint32_t reserved_b08;
+    uint32_t reserved_b0c;
+    uint32_t reserved_b10;
+    uint32_t reserved_b14;
+    uint32_t reserved_b18;
+    uint32_t reserved_b1c;
+    uint32_t reserved_b20;
+    uint32_t reserved_b24;
+    uint32_t reserved_b28;
+    uint32_t reserved_b2c;
+    uint32_t reserved_b30;
+    uint32_t reserved_b34;
+    uint32_t reserved_b38;
+    uint32_t reserved_b3c;
+    uint32_t reserved_b40;
+    uint32_t reserved_b44;
+    uint32_t reserved_b48;
+    uint32_t reserved_b4c;
+    uint32_t reserved_b50;
+    uint32_t reserved_b54;
+    uint32_t reserved_b58;
+    uint32_t reserved_b5c;
+    uint32_t reserved_b60;
+    uint32_t reserved_b64;
+    uint32_t reserved_b68;
+    uint32_t reserved_b6c;
+    uint32_t reserved_b70;
+    uint32_t reserved_b74;
+    uint32_t reserved_b78;
+    uint32_t reserved_b7c;
+    uint32_t reserved_b80;
+    uint32_t reserved_b84;
+    uint32_t reserved_b88;
+    uint32_t reserved_b8c;
+    uint32_t reserved_b90;
+    uint32_t reserved_b94;
+    uint32_t reserved_b98;
+    uint32_t reserved_b9c;
+    uint32_t reserved_ba0;
+    uint32_t reserved_ba4;
+    uint32_t reserved_ba8;
+    uint32_t reserved_bac;
+    uint32_t reserved_bb0;
+    uint32_t reserved_bb4;
+    uint32_t reserved_bb8;
+    uint32_t reserved_bbc;
+    uint32_t reserved_bc0;
+    uint32_t reserved_bc4;
+    uint32_t reserved_bc8;
+    uint32_t reserved_bcc;
+    uint32_t reserved_bd0;
+    uint32_t reserved_bd4;
+    uint32_t reserved_bd8;
+    uint32_t reserved_bdc;
+    uint32_t reserved_be0;
+    uint32_t reserved_be4;
+    uint32_t reserved_be8;
+    uint32_t reserved_bec;
+    uint32_t reserved_bf0;
+    uint32_t reserved_bf4;
+    uint32_t reserved_bf8;
+    uint32_t reserved_bfc;
+    uint32_t reserved_c00;
+    uint32_t reserved_c04;
+    uint32_t reserved_c08;
+    uint32_t reserved_c0c;
+    uint32_t reserved_c10;
+    uint32_t reserved_c14;
+    uint32_t reserved_c18;
+    uint32_t reserved_c1c;
+    uint32_t reserved_c20;
+    uint32_t reserved_c24;
+    uint32_t reserved_c28;
+    uint32_t reserved_c2c;
+    uint32_t reserved_c30;
+    uint32_t reserved_c34;
+    uint32_t reserved_c38;
+    uint32_t reserved_c3c;
+    uint32_t reserved_c40;
+    uint32_t reserved_c44;
+    uint32_t reserved_c48;
+    uint32_t reserved_c4c;
+    uint32_t reserved_c50;
+    uint32_t reserved_c54;
+    uint32_t reserved_c58;
+    uint32_t reserved_c5c;
+    uint32_t reserved_c60;
+    uint32_t reserved_c64;
+    uint32_t reserved_c68;
+    uint32_t reserved_c6c;
+    uint32_t reserved_c70;
+    uint32_t reserved_c74;
+    uint32_t reserved_c78;
+    uint32_t reserved_c7c;
+    uint32_t reserved_c80;
+    uint32_t reserved_c84;
+    uint32_t reserved_c88;
+    uint32_t reserved_c8c;
+    uint32_t reserved_c90;
+    uint32_t reserved_c94;
+    uint32_t reserved_c98;
+    uint32_t reserved_c9c;
+    uint32_t reserved_ca0;
+    uint32_t reserved_ca4;
+    uint32_t reserved_ca8;
+    uint32_t reserved_cac;
+    uint32_t reserved_cb0;
+    uint32_t reserved_cb4;
+    uint32_t reserved_cb8;
+    uint32_t reserved_cbc;
+    uint32_t reserved_cc0;
+    uint32_t reserved_cc4;
+    uint32_t reserved_cc8;
+    uint32_t reserved_ccc;
+    uint32_t reserved_cd0;
+    uint32_t reserved_cd4;
+    uint32_t reserved_cd8;
+    uint32_t reserved_cdc;
+    uint32_t reserved_ce0;
+    uint32_t reserved_ce4;
+    uint32_t reserved_ce8;
+    uint32_t reserved_cec;
+    uint32_t reserved_cf0;
+    uint32_t reserved_cf4;
+    uint32_t reserved_cf8;
+    uint32_t reserved_cfc;
+    uint32_t reserved_d00;
+    uint32_t reserved_d04;
+    uint32_t reserved_d08;
+    uint32_t reserved_d0c;
+    uint32_t reserved_d10;
+    uint32_t reserved_d14;
+    uint32_t reserved_d18;
+    uint32_t reserved_d1c;
+    uint32_t reserved_d20;
+    uint32_t reserved_d24;
+    uint32_t reserved_d28;
+    uint32_t reserved_d2c;
+    uint32_t reserved_d30;
+    uint32_t reserved_d34;
+    uint32_t reserved_d38;
+    uint32_t reserved_d3c;
+    uint32_t reserved_d40;
+    uint32_t reserved_d44;
+    uint32_t reserved_d48;
+    uint32_t reserved_d4c;
+    uint32_t reserved_d50;
+    uint32_t reserved_d54;
+    uint32_t reserved_d58;
+    uint32_t reserved_d5c;
+    uint32_t reserved_d60;
+    uint32_t reserved_d64;
+    uint32_t reserved_d68;
+    uint32_t reserved_d6c;
+    uint32_t reserved_d70;
+    uint32_t reserved_d74;
+    uint32_t reserved_d78;
+    uint32_t reserved_d7c;
+    uint32_t reserved_d80;
+    uint32_t reserved_d84;
+    uint32_t reserved_d88;
+    uint32_t reserved_d8c;
+    uint32_t reserved_d90;
+    uint32_t reserved_d94;
+    uint32_t reserved_d98;
+    uint32_t reserved_d9c;
+    uint32_t reserved_da0;
+    uint32_t reserved_da4;
+    uint32_t reserved_da8;
+    uint32_t reserved_dac;
+    uint32_t reserved_db0;
+    uint32_t reserved_db4;
+    uint32_t reserved_db8;
+    uint32_t reserved_dbc;
+    uint32_t reserved_dc0;
+    uint32_t reserved_dc4;
+    uint32_t reserved_dc8;
+    uint32_t reserved_dcc;
+    uint32_t reserved_dd0;
+    uint32_t reserved_dd4;
+    uint32_t reserved_dd8;
+    uint32_t reserved_ddc;
+    uint32_t reserved_de0;
+    uint32_t reserved_de4;
+    uint32_t reserved_de8;
+    uint32_t reserved_dec;
+    uint32_t reserved_df0;
+    uint32_t reserved_df4;
+    uint32_t reserved_df8;
+    uint32_t reserved_dfc;
+    uint32_t reserved_e00;
+    uint32_t reserved_e04;
+    uint32_t reserved_e08;
+    uint32_t reserved_e0c;
+    uint32_t reserved_e10;
+    uint32_t reserved_e14;
+    uint32_t reserved_e18;
+    uint32_t reserved_e1c;
+    uint32_t reserved_e20;
+    uint32_t reserved_e24;
+    uint32_t reserved_e28;
+    uint32_t reserved_e2c;
+    uint32_t reserved_e30;
+    uint32_t reserved_e34;
+    uint32_t reserved_e38;
+    uint32_t reserved_e3c;
+    uint32_t reserved_e40;
+    uint32_t reserved_e44;
+    uint32_t reserved_e48;
+    uint32_t reserved_e4c;
+    uint32_t reserved_e50;
+    uint32_t reserved_e54;
+    uint32_t reserved_e58;
+    uint32_t reserved_e5c;
+    uint32_t reserved_e60;
+    uint32_t reserved_e64;
+    uint32_t reserved_e68;
+    uint32_t reserved_e6c;
+    uint32_t reserved_e70;
+    uint32_t reserved_e74;
+    uint32_t reserved_e78;
+    uint32_t reserved_e7c;
+    uint32_t reserved_e80;
+    uint32_t reserved_e84;
+    uint32_t reserved_e88;
+    uint32_t reserved_e8c;
+    uint32_t reserved_e90;
+    uint32_t reserved_e94;
+    uint32_t reserved_e98;
+    uint32_t reserved_e9c;
+    uint32_t reserved_ea0;
+    uint32_t reserved_ea4;
+    uint32_t reserved_ea8;
+    uint32_t reserved_eac;
+    uint32_t reserved_eb0;
+    uint32_t reserved_eb4;
+    uint32_t reserved_eb8;
+    uint32_t reserved_ebc;
+    uint32_t reserved_ec0;
+    uint32_t reserved_ec4;
+    uint32_t reserved_ec8;
+    uint32_t reserved_ecc;
+    uint32_t reserved_ed0;
+    uint32_t reserved_ed4;
+    uint32_t reserved_ed8;
+    uint32_t reserved_edc;
+    uint32_t reserved_ee0;
+    uint32_t reserved_ee4;
+    uint32_t reserved_ee8;
+    uint32_t reserved_eec;
+    uint32_t reserved_ef0;
+    uint32_t reserved_ef4;
+    uint32_t reserved_ef8;
+    uint32_t reserved_efc;
+    uint32_t reserved_f00;
+    uint32_t reserved_f04;
+    uint32_t reserved_f08;
+    uint32_t reserved_f0c;
+    uint32_t reserved_f10;
+    uint32_t reserved_f14;
+    uint32_t reserved_f18;
+    uint32_t reserved_f1c;
+    uint32_t reserved_f20;
+    uint32_t reserved_f24;
+    uint32_t reserved_f28;
+    uint32_t reserved_f2c;
+    uint32_t reserved_f30;
+    uint32_t reserved_f34;
+    uint32_t reserved_f38;
+    uint32_t reserved_f3c;
+    uint32_t reserved_f40;
+    uint32_t reserved_f44;
+    uint32_t reserved_f48;
+    uint32_t reserved_f4c;
+    uint32_t reserved_f50;
+    uint32_t reserved_f54;
+    uint32_t reserved_f58;
+    uint32_t reserved_f5c;
+    uint32_t reserved_f60;
+    uint32_t reserved_f64;
+    uint32_t reserved_f68;
+    uint32_t reserved_f6c;
+    uint32_t reserved_f70;
+    uint32_t reserved_f74;
+    uint32_t reserved_f78;
+    uint32_t reserved_f7c;
+    uint32_t reserved_f80;
+    uint32_t reserved_f84;
+    uint32_t reserved_f88;
+    uint32_t reserved_f8c;
+    uint32_t reserved_f90;
+    uint32_t reserved_f94;
+    uint32_t reserved_f98;
+    uint32_t reserved_f9c;
+    uint32_t reserved_fa0;
+    uint32_t reserved_fa4;
+    uint32_t reserved_fa8;
+    uint32_t reserved_fac;
+    uint32_t reserved_fb0;
+    uint32_t reserved_fb4;
+    uint32_t reserved_fb8;
+    uint32_t reserved_fbc;
+    uint32_t reserved_fc0;
+    uint32_t reserved_fc4;
+    uint32_t reserved_fc8;
+    uint32_t reserved_fcc;
+    uint32_t reserved_fd0;
+    uint32_t reserved_fd4;
+    uint32_t reserved_fd8;
+    uint32_t reserved_fdc;
+    uint32_t reserved_fe0;
+    uint32_t reserved_fe4;
+    uint32_t reserved_fe8;
+    uint32_t reserved_fec;
+    uint32_t reserved_ff0;
+    uint32_t reserved_ff4;
+    uint32_t reserved_ff8;
+    union {
+        struct {
+            uint32_t reg_system_reg_date           :    28;  /*reg_system_reg_date*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} system_dev_t;
+extern system_dev_t SYSTEM;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_STRUCT_H_ */
diff --git a/components/soc/esp32c3/register/soc/systimer_reg.h b/components/soc/esp32c3/register/soc/systimer_reg.h
new file mode 100644
index 00000000000..55316915df1
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/systimer_reg.h
@@ -0,0 +1,558 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSTIMER_CONF_REG register
+ *  SYSTIMER_CONF.
+ */
+#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
+/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
+ *  systimer clock force on
+ */
+#define SYSTIMER_SYSTIMER_CLK_FO    (BIT(0))
+#define SYSTIMER_SYSTIMER_CLK_FO_M  (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
+#define SYSTIMER_SYSTIMER_CLK_FO_V  0x00000001
+#define SYSTIMER_SYSTIMER_CLK_FO_S  0
+/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
+ *  target2 work enable
+ */
+#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
+#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
+#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET2_WORK_EN_S  22
+/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
+ *  target1 work enable
+ */
+#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
+#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
+#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET1_WORK_EN_S  23
+/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
+ *  target0 work enable
+ */
+#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
+#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
+#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET0_WORK_EN_S  24
+/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
+ *  If timer unit1 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
+/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
+ *  If timer unit1 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
+/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
+ *  If timer unit0 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
+/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
+ *  If timer unit0 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
+/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
+ *  timer unit1 work enable
+ */
+#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
+/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
+ *  timer unit0 work enable
+ */
+#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
+/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  register file clk gating
+ */
+#define SYSTIMER_CLK_EN    (BIT(31))
+#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
+#define SYSTIMER_CLK_EN_V  0x00000001
+#define SYSTIMER_CLK_EN_S  31
+
+/** SYSTIMER_UNIT0_OP_REG register
+ *  SYSTIMER_UNIT0_OP.
+ */
+#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
+/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  reg_timer_unit0_value_valid
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer_unit0
+ */
+#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
+
+/** SYSTIMER_UNIT1_OP_REG register
+ *  SYSTIMER_UNIT1_OP.
+ */
+#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
+/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  timer value is sync and valid
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer unit1
+ */
+#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
+
+/** SYSTIMER_UNIT0_LOAD_HI_REG register
+ *  SYSTIMER_UNIT0_LOAD_HI.
+ */
+#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
+/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit0 load high 32 bit
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT0_LOAD_LO_REG register
+ *  SYSTIMER_UNIT0_LOAD_LO.
+ */
+#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
+/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit0 load low 32 bit
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
+
+/** SYSTIMER_UNIT1_LOAD_HI_REG register
+ *  SYSTIMER_UNIT1_LOAD_HI.
+ */
+#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
+/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit1 load high 32 bit
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT1_LOAD_LO_REG register
+ *  SYSTIMER_UNIT1_LOAD_LO.
+ */
+#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
+/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit1 load low 32 bit
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
+
+/** SYSTIMER_TARGET0_HI_REG register
+ *  SYSTIMER_TARGET0_HI.
+ */
+#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
+/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget0 high 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
+#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET0_HI_S  0
+
+/** SYSTIMER_TARGET0_LO_REG register
+ *  SYSTIMER_TARGET0_LO.
+ */
+#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
+/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget0 low 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
+#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET0_LO_S  0
+
+/** SYSTIMER_TARGET1_HI_REG register
+ *  SYSTIMER_TARGET1_HI.
+ */
+#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
+/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget1 high 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
+#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET1_HI_S  0
+
+/** SYSTIMER_TARGET1_LO_REG register
+ *  SYSTIMER_TARGET1_LO.
+ */
+#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
+/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget1 low 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
+#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET1_LO_S  0
+
+/** SYSTIMER_TARGET2_HI_REG register
+ *  SYSTIMER_TARGET2_HI.
+ */
+#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
+/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget2 high 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
+#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET2_HI_S  0
+
+/** SYSTIMER_TARGET2_LO_REG register
+ *  SYSTIMER_TARGET2_LO.
+ */
+#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
+/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget2 low 32 bit
+ */
+#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
+#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET2_LO_S  0
+
+/** SYSTIMER_TARGET0_CONF_REG register
+ *  SYSTIMER_TARGET0_CONF.
+ */
+#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
+/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target0 period
+ */
+#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
+#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_S  0
+/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target0 to period mode
+ */
+#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
+#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET1_CONF_REG register
+ *  SYSTIMER_TARGET1_CONF.
+ */
+#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
+/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target1 period
+ */
+#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
+#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_S  0
+/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target1 to period mode
+ */
+#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
+#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET2_CONF_REG register
+ *  SYSTIMER_TARGET2_CONF.
+ */
+#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
+/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target2 period
+ */
+#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
+#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_S  0
+/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target2 to period mode
+ */
+#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
+#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_UNIT0_VALUE_HI_REG register
+ *  SYSTIMER_UNIT0_VALUE_HI.
+ */
+#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
+/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 32bit
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT0_VALUE_LO_REG register
+ *  SYSTIMER_UNIT0_VALUE_LO.
+ */
+#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
+/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bit
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
+
+/** SYSTIMER_UNIT1_VALUE_HI_REG register
+ *  SYSTIMER_UNIT1_VALUE_HI.
+ */
+#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
+/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 32bit
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT1_VALUE_LO_REG register
+ *  SYSTIMER_UNIT1_VALUE_LO.
+ */
+#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
+/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bit
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
+
+/** SYSTIMER_COMP0_LOAD_REG register
+ *  SYSTIMER_COMP0_LOAD.
+ */
+#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
+/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp0 load value
+ */
+#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
+#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP0_LOAD_S  0
+
+/** SYSTIMER_COMP1_LOAD_REG register
+ *  SYSTIMER_COMP1_LOAD.
+ */
+#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
+/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp1 load value
+ */
+#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
+#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP1_LOAD_S  0
+
+/** SYSTIMER_COMP2_LOAD_REG register
+ *  SYSTIMER_COMP2_LOAD.
+ */
+#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
+/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp2 load value
+ */
+#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
+#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP2_LOAD_S  0
+
+/** SYSTIMER_UNIT0_LOAD_REG register
+ *  SYSTIMER_UNIT0_LOAD.
+ */
+#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
+/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit0 load value
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
+
+/** SYSTIMER_UNIT1_LOAD_REG register
+ *  SYSTIMER_UNIT1_LOAD.
+ */
+#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
+/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit1 load value
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
+
+/** SYSTIMER_INT_ENA_REG register
+ *  SYSTIMER_INT_ENA.
+ */
+#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
+/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  interupt0 enable
+ */
+#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
+#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ENA_S  0
+/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  interupt1 enable
+ */
+#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
+#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ENA_S  1
+/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  interupt2 enable
+ */
+#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
+#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ENA_S  2
+
+/** SYSTIMER_INT_RAW_REG register
+ *  SYSTIMER_INT_RAW.
+ */
+#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
+/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  interupt0 raw
+ */
+#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
+#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
+#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET0_INT_RAW_S  0
+/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  interupt1 raw
+ */
+#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
+#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
+#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET1_INT_RAW_S  1
+/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  interupt2 raw
+ */
+#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
+#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
+#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET2_INT_RAW_S  2
+
+/** SYSTIMER_INT_CLR_REG register
+ *  SYSTIMER_INT_CLR.
+ */
+#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
+/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  interupt0 clear
+ */
+#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
+#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
+#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET0_INT_CLR_S  0
+/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  interupt1 clear
+ */
+#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
+#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
+#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET1_INT_CLR_S  1
+/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  interupt2 clear
+ */
+#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
+#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
+#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET2_INT_CLR_S  2
+
+/** SYSTIMER_INT_ST_REG register
+ *  SYSTIMER_INT_ST.
+ */
+#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
+/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  reg_target0_int_st
+ */
+#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
+#define SYSTIMER_TARGET0_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ST_S  0
+/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  reg_target1_int_st
+ */
+#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
+#define SYSTIMER_TARGET1_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ST_S  1
+/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  reg_target2_int_st
+ */
+#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
+#define SYSTIMER_TARGET2_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ST_S  2
+
+/** SYSTIMER_DATE_REG register
+ *  SYSTIMER_DATE.
+ */
+#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
+/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377;
+ *  reg_date
+ */
+#define SYSTIMER_DATE    0xFFFFFFFF
+#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
+#define SYSTIMER_DATE_V  0xFFFFFFFF
+#define SYSTIMER_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/systimer_struct.h b/components/soc/esp32c3/register/soc/systimer_struct.h
new file mode 100644
index 00000000000..cf10afab1c3
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/systimer_struct.h
@@ -0,0 +1,371 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Configuration Register */
+/** Type of conf register
+ *  SYSTIMER_CONF.
+ */
+typedef union {
+    struct {
+        /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
+         *  systimer clock force on
+         */
+        uint32_t systimer_clk_fo: 1;
+        uint32_t reserved_1: 21;
+        /** target2_work_en : R/W; bitpos: [22]; default: 0;
+         *  target2 work enable
+         */
+        uint32_t target2_work_en: 1;
+        /** target1_work_en : R/W; bitpos: [23]; default: 0;
+         *  target1 work enable
+         */
+        uint32_t target1_work_en: 1;
+        /** target0_work_en : R/W; bitpos: [24]; default: 0;
+         *  target0 work enable
+         */
+        uint32_t target0_work_en: 1;
+        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
+         *  If timer unit1 is stalled when core1 stalled
+         */
+        uint32_t timer_unit1_core1_stall_en: 1;
+        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
+         *  If timer unit1 is stalled when core0 stalled
+         */
+        uint32_t timer_unit1_core0_stall_en: 1;
+        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
+         *  If timer unit0 is stalled when core1 stalled
+         */
+        uint32_t timer_unit0_core1_stall_en: 1;
+        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
+         *  If timer unit0 is stalled when core0 stalled
+         */
+        uint32_t timer_unit0_core0_stall_en: 1;
+        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
+         *  timer unit1 work enable
+         */
+        uint32_t timer_unit1_work_en: 1;
+        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
+         *  timer unit0 work enable
+         */
+        uint32_t timer_unit0_work_en: 1;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  register file clk gating
+         */
+        uint32_t clk_en: 1;
+    };
+    uint32_t val;
+} systimer_conf_reg_t;
+
+/** Type of unit_op register
+ *  SYSTIMER_UNIT_OP.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 29;
+        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
+         *  reg_timer_unit0_value_valid
+         */
+        uint32_t timer_unit_value_valid: 1;
+        /** timer_unit_update : WT; bitpos: [30]; default: 0;
+         *  update timer_unit0
+         */
+        uint32_t timer_unit_update: 1;
+        uint32_t reserved31: 1;
+    };
+    uint32_t val;
+} systimer_unit_op_reg_t;
+
+/** Type of unit_load register
+ *  SYSTIMER_UNIT_LOAD
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer unit load high 32 bit
+             */
+            uint32_t timer_unit_load_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer unit load low 32 bit
+             */
+            uint32_t timer_unit_load_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_load_val_reg_t;
+
+/** Type of target register
+ *  SYSTIMER_TARGET.
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer target high 32 bit
+             */
+            uint32_t timer_target_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer target low 32 bit
+             */
+            uint32_t timer_target_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_target_val_reg_t;
+
+/** Type of target_conf register
+ *  SYSTIMER_TARGET_CONF.
+ */
+typedef union {
+    struct {
+        /** target_period : R/W; bitpos: [25:0]; default: 0;
+         *  target period
+         */
+        uint32_t target_period: 26;
+        uint32_t reserved_26: 4;
+        /** target_period_mode : R/W; bitpos: [30]; default: 0;
+         *  Set target to period mode
+         */
+        uint32_t target_period_mode: 1;
+        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
+         *  select which unit to compare
+         */
+        uint32_t target_timer_unit_sel: 1;
+    };
+    uint32_t val;
+} systimer_target_conf_reg_t;
+
+/** Type of unit_value_hi register
+ *  SYSTIMER_UNIT_VALUE_HI.
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
+             *  timer read value high 20bit
+             */
+            uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
+             *  timer read value low 32bit
+             */
+            uint32_t timer_unit_value_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_value_reg_t;
+
+/** Type of comp_load register
+ *  SYSTIMER_COMP_LOAD.
+ */
+typedef union {
+    struct {
+        /** timer_comp_load : WT; bitpos: [0]; default: 0;
+         *  timer comp load value
+         */
+        uint32_t timer_comp_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_comp_load_reg_t;
+
+/** Type of unit_load register
+ *  SYSTIMER_UNIT_LOAD.
+ */
+typedef union {
+    struct {
+        /** timer_unit_load : WT; bitpos: [0]; default: 0;
+         *  timer unit load value
+         */
+        uint32_t timer_unit_load: 1;
+        uint32_t reserved1: 31;
+    };
+    uint32_t val;
+} systimer_unit_load_reg_t;
+
+/** Interrupt Register */
+/** Type of int_ena register
+ *  SYSTIMER_INT_ENA.
+ */
+typedef union {
+    struct {
+        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  interupt0 enable
+         */
+        uint32_t target0_int_ena: 1;
+        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  interupt1 enable
+         */
+        uint32_t target1_int_ena: 1;
+        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  interupt2 enable
+         */
+        uint32_t target2_int_ena: 1;
+        uint32_t reserved3: 29;
+    };
+    uint32_t val;
+} systimer_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  SYSTIMER_INT_RAW.
+ */
+typedef union {
+    struct {
+        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  interupt0 raw
+         */
+        uint32_t target0_int_raw: 1;
+        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  interupt1 raw
+         */
+        uint32_t target1_int_raw: 1;
+        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  interupt2 raw
+         */
+        uint32_t target2_int_raw: 1;
+        uint32_t reserved3: 29;
+    };
+    uint32_t val;
+} systimer_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  SYSTIMER_INT_CLR.
+ */
+typedef union {
+    struct {
+        /** target0_int_clr : WT; bitpos: [0]; default: 0;
+         *  interupt0 clear
+         */
+        uint32_t target0_int_clr: 1;
+        /** target1_int_clr : WT; bitpos: [1]; default: 0;
+         *  interupt1 clear
+         */
+        uint32_t target1_int_clr: 1;
+        /** target2_int_clr : WT; bitpos: [2]; default: 0;
+         *  interupt2 clear
+         */
+        uint32_t target2_int_clr: 1;
+        uint32_t reserved3: 29;
+    };
+    uint32_t val;
+} systimer_int_clr_reg_t;
+
+/** Type of int_st register
+ *  SYSTIMER_INT_ST.
+ */
+typedef union {
+    struct {
+        /** target0_int_st : RO; bitpos: [0]; default: 0;
+         *  reg_target0_int_st
+         */
+        uint32_t target0_int_st: 1;
+        /** target1_int_st : RO; bitpos: [1]; default: 0;
+         *  reg_target1_int_st
+         */
+        uint32_t target1_int_st: 1;
+        /** target2_int_st : RO; bitpos: [2]; default: 0;
+         *  reg_target2_int_st
+         */
+        uint32_t target2_int_st: 1;
+        uint32_t reserved3: 29;
+    };
+    uint32_t val;
+} systimer_int_st_reg_t;
+
+
+/** Version Register */
+/** Type of date register
+ *  SYSTIMER_DATE.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 33579377;
+         *  reg_date
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} systimer_date_reg_t;
+
+
+typedef struct systimer_dev_t {
+    volatile systimer_conf_reg_t conf;
+    volatile systimer_unit_op_reg_t unit_op[2];
+    volatile systimer_unit_load_val_reg_t unit_load_val[2];
+    volatile systimer_target_val_reg_t target_val[3];
+    volatile systimer_target_conf_reg_t target_conf[3];
+    volatile systimer_unit_value_reg_t unit_val[2];
+    volatile systimer_comp_load_reg_t comp_load[3];
+    volatile systimer_unit_load_reg_t unit_load[2];
+    volatile systimer_int_ena_reg_t int_ena;
+    volatile systimer_int_raw_reg_t int_raw;
+    volatile systimer_int_clr_reg_t int_clr;
+    volatile systimer_int_st_reg_t int_st;
+    uint32_t reserved_074;
+    uint32_t reserved_078;
+    uint32_t reserved_07c;
+    uint32_t reserved_080;
+    uint32_t reserved_084;
+    uint32_t reserved_088;
+    uint32_t reserved_08c;
+    uint32_t reserved_090;
+    uint32_t reserved_094;
+    uint32_t reserved_098;
+    uint32_t reserved_09c;
+    uint32_t reserved_0a0;
+    uint32_t reserved_0a4;
+    uint32_t reserved_0a8;
+    uint32_t reserved_0ac;
+    uint32_t reserved_0b0;
+    uint32_t reserved_0b4;
+    uint32_t reserved_0b8;
+    uint32_t reserved_0bc;
+    uint32_t reserved_0c0;
+    uint32_t reserved_0c4;
+    uint32_t reserved_0c8;
+    uint32_t reserved_0cc;
+    uint32_t reserved_0d0;
+    uint32_t reserved_0d4;
+    uint32_t reserved_0d8;
+    uint32_t reserved_0dc;
+    uint32_t reserved_0e0;
+    uint32_t reserved_0e4;
+    uint32_t reserved_0e8;
+    uint32_t reserved_0ec;
+    uint32_t reserved_0f0;
+    uint32_t reserved_0f4;
+    uint32_t reserved_0f8;
+    volatile systimer_date_reg_t date;
+} systimer_dev_t;
+
+extern systimer_dev_t SYSTIMER;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/include/soc/timer_group_reg.h b/components/soc/esp32c3/register/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/timer_group_reg.h
rename to components/soc/esp32c3/register/soc/timer_group_reg.h
diff --git a/components/soc/esp32c3/include/soc/timer_group_struct.h b/components/soc/esp32c3/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/timer_group_struct.h
rename to components/soc/esp32c3/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32c3/include/soc/twai_struct.h b/components/soc/esp32c3/register/soc/twai_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/twai_struct.h
rename to components/soc/esp32c3/register/soc/twai_struct.h
diff --git a/components/soc/esp32c3/register/soc/uart_reg.h b/components/soc/esp32c3/register/soc/uart_reg.h
new file mode 100644
index 00000000000..c26bab99382
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/uart_reg.h
@@ -0,0 +1,1250 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_UART_REG_H_
+#define _SOC_UART_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
+/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: UART $n accesses FIFO via this register.*/
+#define UART_RXFIFO_RD_BYTE  0x000000FF
+#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
+#define UART_RXFIFO_RD_BYTE_V  0xFF
+#define UART_RXFIFO_RD_BYTE_S  0
+
+#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
+/* UART_WAKEUP_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when input rxd edge
+ changes more times than what reg_active_threshold specifies in light sleeping mode.*/
+#define UART_WAKEUP_INT_RAW  (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (BIT(19))
+#define UART_WAKEUP_INT_RAW_V  0x1
+#define UART_WAKEUP_INT_RAW_S  19
+/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the configured at_cmd char.*/
+#define UART_AT_CMD_CHAR_DET_INT_RAW  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/* UART_RS485_CLASH_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when detects a clash
+ between transmitter and receiver in rs485 mode.*/
+#define UART_RS485_CLASH_INT_RAW  (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_V  0x1
+#define UART_RS485_CLASH_INT_RAW_S  17
+/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a data frame error from the echo of transmitter in rs485 mode.*/
+#define UART_RS485_FRM_ERR_INT_RAW  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a parity error from the echo of transmitter in rs485 mode.*/
+#define UART_RS485_PARITY_ERR_INT_RAW  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/* UART_TX_DONE_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has
+ send out all data in FIFO.*/
+#define UART_TX_DONE_INT_RAW  (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (BIT(14))
+#define UART_TX_DONE_INT_RAW_V  0x1
+#define UART_TX_DONE_INT_RAW_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter has
+ kept the shortest duration after sending the  last data.*/
+#define UART_TX_BRK_IDLE_DONE_INT_RAW  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when transmitter completes
+  sending  NULL characters  after all data in Tx-FIFO are sent.*/
+#define UART_TX_BRK_DONE_INT_RAW  (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/* UART_GLITCH_DET_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a glitch in the middle of a start bit.*/
+#define UART_GLITCH_DET_INT_RAW  (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_V  0x1
+#define UART_GLITCH_DET_INT_RAW_S  11
+/* UART_SW_XOFF_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ Xoff char when uart_sw_flow_con_en is set to 1.*/
+#define UART_SW_XOFF_INT_RAW  (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
+#define UART_SW_XOFF_INT_RAW_V  0x1
+#define UART_SW_XOFF_INT_RAW_S  10
+/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ Xon char when uart_sw_flow_con_en is set to 1.*/
+#define UART_SW_XON_INT_RAW  (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (BIT(9))
+#define UART_SW_XON_INT_RAW_V  0x1
+#define UART_SW_XON_INT_RAW_S  9
+/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver takes
+ more time than rx_tout_thrhd to receive a byte.*/
+#define UART_RXFIFO_TOUT_INT_RAW  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/* UART_BRK_DET_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a 0 after the stop bit.*/
+#define UART_BRK_DET_INT_RAW  (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (BIT(7))
+#define UART_BRK_DET_INT_RAW_V  0x1
+#define UART_BRK_DET_INT_RAW_S  7
+/* UART_CTS_CHG_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the edge change of CTSn signal.*/
+#define UART_CTS_CHG_INT_RAW  (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
+#define UART_CTS_CHG_INT_RAW_V  0x1
+#define UART_CTS_CHG_INT_RAW_S  6
+/* UART_DSR_CHG_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ the edge change of DSRn signal.*/
+#define UART_DSR_CHG_INT_RAW  (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
+#define UART_DSR_CHG_INT_RAW_V  0x1
+#define UART_DSR_CHG_INT_RAW_S  5
+/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ more data than the FIFO can store.*/
+#define UART_RXFIFO_OVF_INT_RAW  (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_V  0x1
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/* UART_FRM_ERR_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a data frame error .*/
+#define UART_FRM_ERR_INT_RAW  (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
+#define UART_FRM_ERR_INT_RAW_V  0x1
+#define UART_FRM_ERR_INT_RAW_S  3
+/* UART_PARITY_ERR_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver detects
+ a parity error in the data.*/
+#define UART_PARITY_ERR_INT_RAW  (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_V  0x1
+#define UART_PARITY_ERR_INT_RAW_S  2
+/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b1 ; */
+/*description: This interrupt raw bit turns to high level when the amount of
+ data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
+#define UART_TXFIFO_EMPTY_INT_RAW  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This interrupt raw bit turns to high level when receiver receives
+ more data than what rxfifo_full_thrhd specifies.*/
+#define UART_RXFIFO_FULL_INT_RAW  (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_V  0x1
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+
+#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
+/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena
+ is set to 1.*/
+#define UART_WAKEUP_INT_ST  (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (BIT(19))
+#define UART_WAKEUP_INT_ST_V  0x1
+#define UART_WAKEUP_INT_ST_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena
+ is set to 1.*/
+#define UART_AT_CMD_CHAR_DET_INT_ST  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena
+ is set to 1.*/
+#define UART_RS485_CLASH_INT_ST  (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ST_V  0x1
+#define UART_RS485_CLASH_INT_ST_S  17
+/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena
+ is set to 1.*/
+#define UART_RS485_FRM_ERR_INT_ST  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_V  0x1
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena
+ is set to 1.*/
+#define UART_RS485_PARITY_ERR_INT_ST  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
+#define UART_TX_DONE_INT_ST  (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (BIT(14))
+#define UART_TX_DONE_INT_ST_V  0x1
+#define UART_TX_DONE_INT_ST_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ is set to 1.*/
+#define UART_TX_BRK_IDLE_DONE_INT_ST  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena
+ is set to 1.*/
+#define UART_TX_BRK_DONE_INT_ST  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena
+ is set to 1.*/
+#define UART_GLITCH_DET_INT_ST  (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ST_V  0x1
+#define UART_GLITCH_DET_INT_ST_S  11
+/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
+#define UART_SW_XOFF_INT_ST  (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (BIT(10))
+#define UART_SW_XOFF_INT_ST_V  0x1
+#define UART_SW_XOFF_INT_ST_S  10
+/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
+#define UART_SW_XON_INT_ST  (BIT(9))
+#define UART_SW_XON_INT_ST_M  (BIT(9))
+#define UART_SW_XON_INT_ST_V  0x1
+#define UART_SW_XON_INT_ST_S  9
+/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_TOUT_INT_ST  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_V  0x1
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
+#define UART_BRK_DET_INT_ST  (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (BIT(7))
+#define UART_BRK_DET_INT_ST_V  0x1
+#define UART_BRK_DET_INT_ST_S  7
+/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
+#define UART_CTS_CHG_INT_ST  (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (BIT(6))
+#define UART_CTS_CHG_INT_ST_V  0x1
+#define UART_CTS_CHG_INT_ST_S  6
+/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
+#define UART_DSR_CHG_INT_ST  (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (BIT(5))
+#define UART_DSR_CHG_INT_ST_V  0x1
+#define UART_DSR_CHG_INT_ST_S  5
+/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_OVF_INT_ST  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_V  0x1
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
+#define UART_FRM_ERR_INT_ST  (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (BIT(3))
+#define UART_FRM_ERR_INT_ST_V  0x1
+#define UART_FRM_ERR_INT_ST_S  3
+/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the status bit for parity_err_int_raw when parity_err_int_ena
+ is set to 1.*/
+#define UART_PARITY_ERR_INT_ST  (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ST_V  0x1
+#define UART_PARITY_ERR_INT_ST_S  2
+/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena
+ is set to 1.*/
+#define UART_TXFIFO_EMPTY_INT_ST  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena
+ is set to 1.*/
+#define UART_RXFIFO_FULL_INT_ST  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_V  0x1
+#define UART_RXFIFO_FULL_INT_ST_S  0
+
+#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
+/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the enable bit for uart_wakeup_int_st register.*/
+#define UART_WAKEUP_INT_ENA  (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (BIT(19))
+#define UART_WAKEUP_INT_ENA_V  0x1
+#define UART_WAKEUP_INT_ENA_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This is the enable bit for at_cmd_char_det_int_st register.*/
+#define UART_AT_CMD_CHAR_DET_INT_ENA  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_clash_int_st register.*/
+#define UART_RS485_CLASH_INT_ENA  (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_V  0x1
+#define UART_RS485_CLASH_INT_ENA_S  17
+/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register.*/
+#define UART_RS485_FRM_ERR_INT_ENA  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for rs485_parity_err_int_st register.*/
+#define UART_RS485_PARITY_ERR_INT_ENA  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_done_int_st register.*/
+#define UART_TX_DONE_INT_ENA  (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (BIT(14))
+#define UART_TX_DONE_INT_ENA_V  0x1
+#define UART_TX_DONE_INT_ENA_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_idle_done_int_st register.*/
+#define UART_TX_BRK_IDLE_DONE_INT_ENA  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: This is the enable bit for tx_brk_done_int_st register.*/
+#define UART_TX_BRK_DONE_INT_ENA  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: This is the enable bit for glitch_det_int_st register.*/
+#define UART_GLITCH_DET_INT_ENA  (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_V  0x1
+#define UART_GLITCH_DET_INT_ENA_S  11
+/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xoff_int_st register.*/
+#define UART_SW_XOFF_INT_ENA  (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
+#define UART_SW_XOFF_INT_ENA_V  0x1
+#define UART_SW_XOFF_INT_ENA_S  10
+/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This is the enable bit for sw_xon_int_st register.*/
+#define UART_SW_XON_INT_ENA  (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (BIT(9))
+#define UART_SW_XON_INT_ENA_V  0x1
+#define UART_SW_XON_INT_ENA_S  9
+/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_tout_int_st register.*/
+#define UART_RXFIFO_TOUT_INT_ENA  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the enable bit for brk_det_int_st register.*/
+#define UART_BRK_DET_INT_ENA  (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (BIT(7))
+#define UART_BRK_DET_INT_ENA_V  0x1
+#define UART_BRK_DET_INT_ENA_S  7
+/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the enable bit for cts_chg_int_st register.*/
+#define UART_CTS_CHG_INT_ENA  (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
+#define UART_CTS_CHG_INT_ENA_V  0x1
+#define UART_CTS_CHG_INT_ENA_S  6
+/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the enable bit for dsr_chg_int_st register.*/
+#define UART_DSR_CHG_INT_ENA  (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
+#define UART_DSR_CHG_INT_ENA_V  0x1
+#define UART_DSR_CHG_INT_ENA_S  5
+/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_ovf_int_st register.*/
+#define UART_RXFIFO_OVF_INT_ENA  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_V  0x1
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the enable bit for frm_err_int_st register.*/
+#define UART_FRM_ERR_INT_ENA  (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
+#define UART_FRM_ERR_INT_ENA_V  0x1
+#define UART_FRM_ERR_INT_ENA_S  3
+/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the enable bit for parity_err_int_st register.*/
+#define UART_PARITY_ERR_INT_ENA  (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_V  0x1
+#define UART_PARITY_ERR_INT_ENA_S  2
+/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the enable bit for txfifo_empty_int_st register.*/
+#define UART_TXFIFO_EMPTY_INT_ENA  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the enable bit for rxfifo_full_int_st register.*/
+#define UART_RXFIFO_FULL_INT_ENA  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_V  0x1
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+
+#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
+/* UART_WAKEUP_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to clear the uart_wakeup_int_raw interrupt.*/
+#define UART_WAKEUP_INT_CLR  (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (BIT(19))
+#define UART_WAKEUP_INT_CLR_V  0x1
+#define UART_WAKEUP_INT_CLR_S  19
+/* UART_AT_CMD_CHAR_DET_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
+#define UART_AT_CMD_CHAR_DET_INT_CLR  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/* UART_RS485_CLASH_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/
+#define UART_RS485_CLASH_INT_CLR  (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_V  0x1
+#define UART_RS485_CLASH_INT_CLR_S  17
+/* UART_RS485_FRM_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
+#define UART_RS485_FRM_ERR_INT_CLR  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/* UART_RS485_PARITY_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
+#define UART_RS485_PARITY_ERR_INT_CLR  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/* UART_TX_DONE_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_done_int_raw interrupt.*/
+#define UART_TX_DONE_INT_CLR  (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (BIT(14))
+#define UART_TX_DONE_INT_CLR_V  0x1
+#define UART_TX_DONE_INT_CLR_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
+#define UART_TX_BRK_IDLE_DONE_INT_CLR  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/* UART_TX_BRK_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/
+#define UART_TX_BRK_DONE_INT_CLR  (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/* UART_GLITCH_DET_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the glitch_det_int_raw interrupt.*/
+#define UART_GLITCH_DET_INT_CLR  (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_V  0x1
+#define UART_GLITCH_DET_INT_CLR_S  11
+/* UART_SW_XOFF_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xoff_int_raw interrupt.*/
+#define UART_SW_XOFF_INT_CLR  (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
+#define UART_SW_XOFF_INT_CLR_V  0x1
+#define UART_SW_XOFF_INT_CLR_S  10
+/* UART_SW_XON_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the sw_xon_int_raw interrupt.*/
+#define UART_SW_XON_INT_CLR  (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (BIT(9))
+#define UART_SW_XON_INT_CLR_V  0x1
+#define UART_SW_XON_INT_CLR_S  9
+/* UART_RXFIFO_TOUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
+#define UART_RXFIFO_TOUT_INT_CLR  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/* UART_BRK_DET_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the brk_det_int_raw interrupt.*/
+#define UART_BRK_DET_INT_CLR  (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (BIT(7))
+#define UART_BRK_DET_INT_CLR_V  0x1
+#define UART_BRK_DET_INT_CLR_S  7
+/* UART_CTS_CHG_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the cts_chg_int_raw interrupt.*/
+#define UART_CTS_CHG_INT_CLR  (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
+#define UART_CTS_CHG_INT_CLR_V  0x1
+#define UART_CTS_CHG_INT_CLR_S  6
+/* UART_DSR_CHG_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/
+#define UART_DSR_CHG_INT_CLR  (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
+#define UART_DSR_CHG_INT_CLR_V  0x1
+#define UART_DSR_CHG_INT_CLR_S  5
+/* UART_RXFIFO_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
+#define UART_RXFIFO_OVF_INT_CLR  (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_V  0x1
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/* UART_FRM_ERR_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear frm_err_int_raw interrupt.*/
+#define UART_FRM_ERR_INT_CLR  (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
+#define UART_FRM_ERR_INT_CLR_V  0x1
+#define UART_FRM_ERR_INT_CLR_S  3
+/* UART_PARITY_ERR_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear parity_err_int_raw interrupt.*/
+#define UART_PARITY_ERR_INT_CLR  (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_V  0x1
+#define UART_PARITY_ERR_INT_CLR_S  2
+/* UART_TXFIFO_EMPTY_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/
+#define UART_TXFIFO_EMPTY_INT_CLR  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/* UART_RXFIFO_FULL_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/
+#define UART_RXFIFO_FULL_INT_CLR  (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_V  0x1
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+
+#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
+/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
+/*description: The decimal part of the frequency divider factor.*/
+#define UART_CLKDIV_FRAG  0x0000000F
+#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
+#define UART_CLKDIV_FRAG_V  0xF
+#define UART_CLKDIV_FRAG_S  20
+/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2B6 ; */
+/*description: The integral part of the frequency divider factor.*/
+#define UART_CLKDIV  0x00000FFF
+#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
+#define UART_CLKDIV_V  0xFFF
+#define UART_CLKDIV_S  0
+
+#define UART_RX_FILT_REG(i)          (REG_UART_BASE(i) + 0x18)
+/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable Rx signal filter.*/
+#define UART_GLITCH_FILT_EN  (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (BIT(8))
+#define UART_GLITCH_FILT_EN_V  0x1
+#define UART_GLITCH_FILT_EN_S  8
+/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */
+/*description: when input pulse width is lower than this value  the pulse is ignored.*/
+#define UART_GLITCH_FILT  0x000000FF
+#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
+#define UART_GLITCH_FILT_V  0xFF
+#define UART_GLITCH_FILT_S  0
+
+#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
+/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */
+/*description: This bit represents the  level of the internal uart txd signal.*/
+#define UART_TXD  (BIT(31))
+#define UART_TXD_M  (BIT(31))
+#define UART_TXD_V  0x1
+#define UART_TXD_S  31
+/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This bit represents the level of the internal uart rts signal.*/
+#define UART_RTSN  (BIT(30))
+#define UART_RTSN_M  (BIT(30))
+#define UART_RTSN_V  0x1
+#define UART_RTSN_S  30
+/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit represents the level of the internal uart dtr signal.*/
+#define UART_DTRN  (BIT(29))
+#define UART_DTRN_M  (BIT(29))
+#define UART_DTRN_V  0x1
+#define UART_DTRN_S  29
+/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */
+/*description: Stores the byte number of data in Tx-FIFO.*/
+#define UART_TXFIFO_CNT  0x000003FF
+#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
+#define UART_TXFIFO_CNT_V  0x3FF
+#define UART_TXFIFO_CNT_S  16
+/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */
+/*description: This register represent the  level value of the internal uart rxd signal.*/
+#define UART_RXD  (BIT(15))
+#define UART_RXD_M  (BIT(15))
+#define UART_RXD_V  0x1
+#define UART_RXD_S  15
+/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */
+/*description: This register represent the level value of the internal uart cts signal.*/
+#define UART_CTSN  (BIT(14))
+#define UART_CTSN_M  (BIT(14))
+#define UART_CTSN_V  0x1
+#define UART_CTSN_S  14
+/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The register represent the level value of the internal uart dsr signal.*/
+#define UART_DSRN  (BIT(13))
+#define UART_DSRN_M  (BIT(13))
+#define UART_DSRN_V  0x1
+#define UART_DSRN_S  13
+/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: Stores the byte number of valid data in Rx-FIFO.*/
+#define UART_RXFIFO_CNT  0x000003FF
+#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
+#define UART_RXFIFO_CNT_V  0x3FF
+#define UART_RXFIFO_CNT_S  0
+
+#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
+/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */
+/*description: UART memory clock gate enable signal.*/
+#define UART_MEM_CLK_EN  (BIT(28))
+#define UART_MEM_CLK_EN_M  (BIT(28))
+#define UART_MEM_CLK_EN_V  0x1
+#define UART_MEM_CLK_EN_S  28
+/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This is the enable bit for detecting baudrate.*/
+#define UART_AUTOBAUD_EN  (BIT(27))
+#define UART_AUTOBAUD_EN_M  (BIT(27))
+#define UART_AUTOBAUD_EN_V  0x1
+#define UART_AUTOBAUD_EN_S  27
+/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1'h1: Receiver stops storing data into FIFO when data is wrong.
+ 1'h0: Receiver stores the data even if the  received data is wrong.*/
+#define UART_ERR_WR_MASK  (BIT(26))
+#define UART_ERR_WR_MASK_M  (BIT(26))
+#define UART_ERR_WR_MASK_V  0x1
+#define UART_ERR_WR_MASK_S  26
+/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when
+ application writes registers.*/
+#define UART_CLK_EN  (BIT(25))
+#define UART_CLK_EN_M  (BIT(25))
+#define UART_CLK_EN_V  0x1
+#define UART_CLK_EN_S  25
+/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dtr signal.*/
+#define UART_DTR_INV  (BIT(24))
+#define UART_DTR_INV_M  (BIT(24))
+#define UART_DTR_INV_V  0x1
+#define UART_DTR_INV_S  24
+/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rts signal.*/
+#define UART_RTS_INV  (BIT(23))
+#define UART_RTS_INV_M  (BIT(23))
+#define UART_RTS_INV_V  0x1
+#define UART_RTS_INV_S  23
+/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart txd signal.*/
+#define UART_TXD_INV  (BIT(22))
+#define UART_TXD_INV_M  (BIT(22))
+#define UART_TXD_INV_V  0x1
+#define UART_TXD_INV_S  22
+/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart dsr signal.*/
+#define UART_DSR_INV  (BIT(21))
+#define UART_DSR_INV_M  (BIT(21))
+#define UART_DSR_INV_V  0x1
+#define UART_DSR_INV_S  21
+/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart cts signal.*/
+#define UART_CTS_INV  (BIT(20))
+#define UART_CTS_INV_M  (BIT(20))
+#define UART_CTS_INV_V  0x1
+#define UART_CTS_INV_S  20
+/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: Set this bit to inverse the level value of uart rxd signal.*/
+#define UART_RXD_INV  (BIT(19))
+#define UART_RXD_INV_M  (BIT(19))
+#define UART_RXD_INV_V  0x1
+#define UART_RXD_INV_S  19
+/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Set this bit to reset the uart transmit-FIFO.*/
+#define UART_TXFIFO_RST  (BIT(18))
+#define UART_TXFIFO_RST_M  (BIT(18))
+#define UART_TXFIFO_RST_V  0x1
+#define UART_TXFIFO_RST_S  18
+/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: Set this bit to reset the uart receive-FIFO.*/
+#define UART_RXFIFO_RST  (BIT(17))
+#define UART_RXFIFO_RST_M  (BIT(17))
+#define UART_RXFIFO_RST_V  0x1
+#define UART_RXFIFO_RST_S  17
+/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: Set this bit to enable IrDA protocol.*/
+#define UART_IRDA_EN  (BIT(16))
+#define UART_IRDA_EN_M  (BIT(16))
+#define UART_IRDA_EN_V  0x1
+#define UART_IRDA_EN_S  16
+/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable flow control function for transmitter.*/
+#define UART_TX_FLOW_EN  (BIT(15))
+#define UART_TX_FLOW_EN_M  (BIT(15))
+#define UART_TX_FLOW_EN_V  0x1
+#define UART_TX_FLOW_EN_S  15
+/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart loopback test mode.*/
+#define UART_LOOPBACK  (BIT(14))
+#define UART_LOOPBACK_M  (BIT(14))
+#define UART_LOOPBACK_V  0x1
+#define UART_LOOPBACK_S  14
+/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to invert the level of IrDA receiver.*/
+#define UART_IRDA_RX_INV  (BIT(13))
+#define UART_IRDA_RX_INV_M  (BIT(13))
+#define UART_IRDA_RX_INV_V  0x1
+#define UART_IRDA_RX_INV_S  13
+/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to invert the level of  IrDA transmitter.*/
+#define UART_IRDA_TX_INV  (BIT(12))
+#define UART_IRDA_TX_INV_M  (BIT(12))
+#define UART_IRDA_TX_INV_V  0x1
+#define UART_IRDA_TX_INV_S  12
+/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit.
+ 1'h0: Set IrDA transmitter's 11th bit to 0.*/
+#define UART_IRDA_WCTL  (BIT(11))
+#define UART_IRDA_WCTL_M  (BIT(11))
+#define UART_IRDA_WCTL_V  0x1
+#define UART_IRDA_WCTL_S  11
+/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: This is the start enable bit for IrDA transmitter.*/
+#define UART_IRDA_TX_EN  (BIT(10))
+#define UART_IRDA_TX_EN_M  (BIT(10))
+#define UART_IRDA_TX_EN_V  0x1
+#define UART_IRDA_TX_EN_S  10
+/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to enable IrDA loopback mode.*/
+#define UART_IRDA_DPLX  (BIT(9))
+#define UART_IRDA_DPLX_M  (BIT(9))
+#define UART_IRDA_DPLX_V  0x1
+#define UART_IRDA_DPLX_S  9
+/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter to  send NULL when the process
+ of sending data is done.*/
+#define UART_TXD_BRK  (BIT(8))
+#define UART_TXD_BRK_M  (BIT(8))
+#define UART_TXD_BRK_V  0x1
+#define UART_TXD_BRK_S  8
+/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This register is used to configure the software dtr signal which
+ is used in software flow control.*/
+#define UART_SW_DTR  (BIT(7))
+#define UART_SW_DTR_M  (BIT(7))
+#define UART_SW_DTR_V  0x1
+#define UART_SW_DTR_S  7
+/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This register is used to configure the software rts signal which
+ is used in software flow control.*/
+#define UART_SW_RTS  (BIT(6))
+#define UART_SW_RTS_M  (BIT(6))
+#define UART_SW_RTS_V  0x1
+#define UART_SW_RTS_S  6
+/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
+/*description: This register is used to set the length of  stop bit.*/
+#define UART_STOP_BIT_NUM  0x00000003
+#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
+#define UART_STOP_BIT_NUM_V  0x3
+#define UART_STOP_BIT_NUM_S  4
+/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+/*description: This register is used to set the length of data.*/
+#define UART_BIT_NUM  0x00000003
+#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
+#define UART_BIT_NUM_V  0x3
+#define UART_BIT_NUM_S  2
+/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable uart parity check.*/
+#define UART_PARITY_EN  (BIT(1))
+#define UART_PARITY_EN_M  (BIT(1))
+#define UART_PARITY_EN_V  0x1
+#define UART_PARITY_EN_S  1
+/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This register is used to configure the parity check mode.*/
+#define UART_PARITY  (BIT(0))
+#define UART_PARITY_M  (BIT(0))
+#define UART_PARITY_V  0x1
+#define UART_PARITY_S  0
+
+#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
+/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: This is the enable bit for uart receiver's timeout function.*/
+#define UART_RX_TOUT_EN  (BIT(21))
+#define UART_RX_TOUT_EN_M  (BIT(21))
+#define UART_RX_TOUT_EN_V  0x1
+#define UART_RX_TOUT_EN_S  21
+/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This is the flow enable bit for UART receiver.*/
+#define UART_RX_FLOW_EN  (BIT(20))
+#define UART_RX_FLOW_EN_M  (BIT(20))
+#define UART_RX_FLOW_EN_V  0x1
+#define UART_RX_FLOW_EN_S  20
+/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
+#define UART_RX_TOUT_FLOW_DIS  (BIT(19))
+#define UART_RX_TOUT_FLOW_DIS_M  (BIT(19))
+#define UART_RX_TOUT_FLOW_DIS_V  0x1
+#define UART_RX_TOUT_FLOW_DIS_S  19
+/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: Disable UART Rx data overflow detect.*/
+#define UART_DIS_RX_DAT_OVF  (BIT(18))
+#define UART_DIS_RX_DAT_OVF_M  (BIT(18))
+#define UART_DIS_RX_DAT_OVF_V  0x1
+#define UART_DIS_RX_DAT_OVF_S  18
+/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */
+/*description: It will produce txfifo_empty_int interrupt when the data amount
+ in Tx-FIFO is less than this register value.*/
+#define UART_TXFIFO_EMPTY_THRHD  0x000001FF
+#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
+#define UART_TXFIFO_EMPTY_THRHD_V  0x1FF
+#define UART_TXFIFO_EMPTY_THRHD_S  9
+/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */
+/*description: It will produce rxfifo_full_int interrupt when receiver receives
+ more data than this register value.*/
+#define UART_RXFIFO_FULL_THRHD  0x000001FF
+#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
+#define UART_RXFIFO_FULL_THRHD_V  0x1FF
+#define UART_RXFIFO_FULL_THRHD_S  0
+
+#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
+/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
+/*description: This register stores the value of the minimum duration time of
+ the low level pulse. It is used in baud rate-detect process.*/
+#define UART_LOWPULSE_MIN_CNT  0x00000FFF
+#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
+#define UART_LOWPULSE_MIN_CNT_V  0xFFF
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
+/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
+/*description: This register stores  the value of the maximum duration time
+ for the high level pulse. It is used in baud rate-detect process.*/
+#define UART_HIGHPULSE_MIN_CNT  0x00000FFF
+#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
+#define UART_HIGHPULSE_MIN_CNT_V  0xFFF
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
+/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the count of rxd edge change. It is used
+ in baud rate-detect process.*/
+#define UART_RXD_EDGE_CNT  0x000003FF
+#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
+#define UART_RXD_EDGE_CNT_V  0x3FF
+#define UART_RXD_EDGE_CNT_S  0
+
+#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
+/* UART_SEND_XOFF : R/W/SS/SC ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to send Xoff char. It is cleared by hardware automatically.*/
+#define UART_SEND_XOFF  (BIT(5))
+#define UART_SEND_XOFF_M  (BIT(5))
+#define UART_SEND_XOFF_V  0x1
+#define UART_SEND_XOFF_S  5
+/* UART_SEND_XON : R/W/SS/SC ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to send Xon char. It is cleared by hardware automatically.*/
+#define UART_SEND_XON  (BIT(4))
+#define UART_SEND_XON_M  (BIT(4))
+#define UART_SEND_XON_V  0x1
+#define UART_SEND_XON_S  4
+/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to stop the  transmitter from sending data.*/
+#define UART_FORCE_XOFF  (BIT(3))
+#define UART_FORCE_XOFF_M  (BIT(3))
+#define UART_FORCE_XOFF_V  0x1
+#define UART_FORCE_XOFF_S  3
+/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable the transmitter to go on sending data.*/
+#define UART_FORCE_XON  (BIT(2))
+#define UART_FORCE_XON_M  (BIT(2))
+#define UART_FORCE_XON_V  0x1
+#define UART_FORCE_XON_S  2
+/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to remove flow control char from the received data.*/
+#define UART_XONOFF_DEL  (BIT(1))
+#define UART_XONOFF_DEL_M  (BIT(1))
+#define UART_XONOFF_DEL_V  0x1
+#define UART_XONOFF_DEL_S  1
+/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable software flow control. It is used with
+ register sw_xon or sw_xoff.*/
+#define UART_SW_FLOW_CON_EN  (BIT(0))
+#define UART_SW_FLOW_CON_EN_M  (BIT(0))
+#define UART_SW_FLOW_CON_EN_V  0x1
+#define UART_SW_FLOW_CON_EN_S  0
+
+#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
+/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
+/*description: The uart is activated from light sleeping mode when the input
+ rxd edge changes more times than this register value.*/
+#define UART_ACTIVE_THRESHOLD  0x000003FF
+#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
+#define UART_ACTIVE_THRESHOLD_V  0x3FF
+#define UART_ACTIVE_THRESHOLD_S  0
+
+#define UART_SWFC_CONF0_REG(i)          (REG_UART_BASE(i) + 0x3C)
+/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */
+/*description: This register stores the Xoff flow control char.*/
+#define UART_XOFF_CHAR  0x000000FF
+#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
+#define UART_XOFF_CHAR_V  0xFF
+#define UART_XOFF_CHAR_S  9
+/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */
+/*description: When the data amount in Rx-FIFO is more than this register value
+ with uart_sw_flow_con_en set to 1  it will send a Xoff char.*/
+#define UART_XOFF_THRESHOLD  0x000001FF
+#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
+#define UART_XOFF_THRESHOLD_V  0x1FF
+#define UART_XOFF_THRESHOLD_S  0
+
+#define UART_SWFC_CONF1_REG(i)          (REG_UART_BASE(i) + 0x40)
+/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */
+/*description: This register stores the Xon flow control char.*/
+#define UART_XON_CHAR  0x000000FF
+#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
+#define UART_XON_CHAR_V  0xFF
+#define UART_XON_CHAR_S  9
+/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: When the data amount in Rx-FIFO is less than this register value
+ with uart_sw_flow_con_en set to 1  it will send a Xon char.*/
+#define UART_XON_THRESHOLD  0x000001FF
+#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
+#define UART_XON_THRESHOLD_V  0x1FF
+#define UART_XON_THRESHOLD_S  0
+
+#define UART_TXBRK_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
+/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */
+/*description: This register is used to configure the number of 0 to be sent
+ after the process of sending data is done. It is active when txd_brk is set to 1.*/
+#define UART_TX_BRK_NUM  0x000000FF
+#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
+#define UART_TX_BRK_NUM_V  0xFF
+#define UART_TX_BRK_NUM_S  0
+
+#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x48)
+/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
+/*description: This register is used to configure the duration time between transfers.*/
+#define UART_TX_IDLE_NUM  0x000003FF
+#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
+#define UART_TX_IDLE_NUM_V  0x3FF
+#define UART_TX_IDLE_NUM_S  10
+/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: It will produce frame end signal when receiver takes more time
+ to receive one byte data than this register value.*/
+#define UART_RX_IDLE_THRHD  0x000003FF
+#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
+#define UART_RX_IDLE_THRHD_V  0x3FF
+#define UART_RX_IDLE_THRHD_S  0
+
+#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x4c)
+/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
+/*description: This register is used to delay the transmitter's internal data signal.*/
+#define UART_RS485_TX_DLY_NUM  0x0000000F
+#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
+#define UART_RS485_TX_DLY_NUM_V  0xF
+#define UART_RS485_TX_DLY_NUM_S  6
+/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This register is used to delay the receiver's internal data signal.*/
+#define UART_RS485_RX_DLY_NUM  (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
+#define UART_RS485_RX_DLY_NUM_V  0x1
+#define UART_RS485_RX_DLY_NUM_S  5
+/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/
+#define UART_RS485RXBY_TX_EN  (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (BIT(4))
+#define UART_RS485RXBY_TX_EN_V  0x1
+#define UART_RS485RXBY_TX_EN_S  4
+/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver could receive data when the transmitter
+ is transmitting data in rs485 mode.*/
+#define UART_RS485TX_RX_EN  (BIT(3))
+#define UART_RS485TX_RX_EN_M  (BIT(3))
+#define UART_RS485TX_RX_EN_V  0x1
+#define UART_RS485TX_RX_EN_S  3
+/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit.*/
+#define UART_DL1_EN  (BIT(2))
+#define UART_DL1_EN_M  (BIT(2))
+#define UART_DL1_EN_V  0x1
+#define UART_DL1_EN_S  2
+/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to delay the stop bit by 1 bit.*/
+#define UART_DL0_EN  (BIT(1))
+#define UART_DL0_EN_M  (BIT(1))
+#define UART_DL0_EN_V  0x1
+#define UART_DL0_EN_S  1
+/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to choose the rs485 mode.*/
+#define UART_RS485_EN  (BIT(0))
+#define UART_RS485_EN_M  (BIT(0))
+#define UART_RS485_EN_V  0x1
+#define UART_RS485_EN_S  0
+
+#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x50)
+/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: This register is used to configure the idle duration time before
+ the first at_cmd is received by receiver.*/
+#define UART_PRE_IDLE_NUM  0x0000FFFF
+#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
+#define UART_PRE_IDLE_NUM_V  0xFFFF
+#define UART_PRE_IDLE_NUM_S  0
+
+#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x54)
+/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: This register is used to configure the duration time between
+ the last at_cmd and the next data.*/
+#define UART_POST_IDLE_NUM  0x0000FFFF
+#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
+#define UART_POST_IDLE_NUM_V  0xFFFF
+#define UART_POST_IDLE_NUM_S  0
+
+#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x58)
+/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */
+/*description: This register is used to configure the duration time between the at_cmd chars.*/
+#define UART_RX_GAP_TOUT  0x0000FFFF
+#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
+#define UART_RX_GAP_TOUT_V  0xFFFF
+#define UART_RX_GAP_TOUT_S  0
+
+#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x5c)
+/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
+/*description: This register is used to configure the num of continuous at_cmd
+ chars received by receiver.*/
+#define UART_CHAR_NUM  0x000000FF
+#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
+#define UART_CHAR_NUM_V  0xFF
+#define UART_CHAR_NUM_S  8
+/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
+/*description: This register is used to configure the content of at_cmd char.*/
+#define UART_AT_CMD_CHAR  0x000000FF
+#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
+#define UART_AT_CMD_CHAR_V  0xFF
+#define UART_AT_CMD_CHAR_S  0
+
+#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x60)
+/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to force power up UART memory.*/
+#define UART_MEM_FORCE_PU  (BIT(27))
+#define UART_MEM_FORCE_PU_M  (BIT(27))
+#define UART_MEM_FORCE_PU_V  0x1
+#define UART_MEM_FORCE_PU_S  27
+/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to force power down UART memory.*/
+#define UART_MEM_FORCE_PD  (BIT(26))
+#define UART_MEM_FORCE_PD_M  (BIT(26))
+#define UART_MEM_FORCE_PD_V  0x1
+#define UART_MEM_FORCE_PD_S  26
+/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */
+/*description: This register is used to configure the threshold time that receiver
+ takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
+#define UART_RX_TOUT_THRHD  0x000003FF
+#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
+#define UART_RX_TOUT_THRHD_V  0x3FF
+#define UART_RX_TOUT_THRHD_S  16
+/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
+/*description: This register is used to configure the maximum amount of data
+ that can be received  when hardware flow control works.*/
+#define UART_RX_FLOW_THRHD  0x000001FF
+#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
+#define UART_RX_FLOW_THRHD_V  0x1FF
+#define UART_RX_FLOW_THRHD_S  7
+/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */
+/*description: This register is used to configure the amount of mem allocated
+ for transmit-FIFO. The default number is 128 bytes.*/
+#define UART_TX_SIZE  0x00000007
+#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
+#define UART_TX_SIZE_V  0x7
+#define UART_TX_SIZE_S  4
+/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */
+/*description: This register is used to configure the amount of mem allocated
+ for receive-FIFO. The default number is 128 bytes.*/
+#define UART_RX_SIZE  0x00000007
+#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
+#define UART_RX_SIZE_V  0x7
+#define UART_RX_SIZE_S  1
+
+#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
+/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
+/*description: This register stores the offset address in Tx-FIFO when Tx-FSM
+ reads data via Tx-FIFO_Ctrl.*/
+#define UART_TX_RADDR  0x000003FF
+#define UART_TX_RADDR_M  ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S))
+#define UART_TX_RADDR_V  0x3FF
+#define UART_TX_RADDR_S  11
+/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register stores the offset address in Tx-FIFO when software
+ writes Tx-FIFO via APB.*/
+#define UART_APB_TX_WADDR  0x000003FF
+#define UART_APB_TX_WADDR_M  ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S))
+#define UART_APB_TX_WADDR_V  0x3FF
+#define UART_APB_TX_WADDR_S  0
+
+#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x68)
+/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h100 ; */
+/*description: This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl
+ writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
+#define UART_RX_WADDR  0x000003FF
+#define UART_RX_WADDR_M  ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
+#define UART_RX_WADDR_V  0x3FF
+#define UART_RX_WADDR_S  11
+/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: This register stores the offset address in RX-FIFO when software
+ reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
+#define UART_APB_RX_RADDR  0x000003FF
+#define UART_APB_RX_RADDR_M  ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S))
+#define UART_APB_RX_RADDR_V  0x3FF
+#define UART_APB_RX_RADDR_S  0
+
+#define UART_FSM_STATUS_REG(i)          (REG_UART_BASE(i) + 0x6c)
+/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: This is the status register of transmitter.*/
+#define UART_ST_UTX_OUT  0x0000000F
+#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
+#define UART_ST_UTX_OUT_V  0xF
+#define UART_ST_UTX_OUT_S  4
+/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: This is the status register of receiver.*/
+#define UART_ST_URX_OUT  0x0000000F
+#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
+#define UART_ST_URX_OUT_V  0xF
+#define UART_ST_URX_OUT_S  0
+
+#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x70)
+/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
+/*description: This register stores the minimal input clock count between two
+ positive edges. It is used in boudrate-detect process.*/
+#define UART_POSEDGE_MIN_CNT  0x00000FFF
+#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
+#define UART_POSEDGE_MIN_CNT_V  0xFFF
+#define UART_POSEDGE_MIN_CNT_S  0
+
+#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x74)
+/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */
+/*description: This register stores the minimal input clock count between two
+ negative edges. It is used in boudrate-detect process.*/
+#define UART_NEGEDGE_MIN_CNT  0x00000FFF
+#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
+#define UART_NEGEDGE_MIN_CNT_V  0xFFF
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+#define UART_CLK_CONF_REG(i)          (REG_UART_BASE(i) + 0x78)
+/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit  reset UART Rx.*/
+#define UART_RX_RST_CORE  (BIT(27))
+#define UART_RX_RST_CORE_M  (BIT(27))
+#define UART_RX_RST_CORE_V  0x1
+#define UART_RX_RST_CORE_S  27
+/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit  reset UART Tx.*/
+#define UART_TX_RST_CORE  (BIT(26))
+#define UART_TX_RST_CORE_M  (BIT(26))
+#define UART_TX_RST_CORE_V  0x1
+#define UART_TX_RST_CORE_S  26
+/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Rx clock.*/
+#define UART_RX_SCLK_EN  (BIT(25))
+#define UART_RX_SCLK_EN_M  (BIT(25))
+#define UART_RX_SCLK_EN_V  0x1
+#define UART_RX_SCLK_EN_S  25
+/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Tx clock.*/
+#define UART_TX_SCLK_EN  (BIT(24))
+#define UART_TX_SCLK_EN_M  (BIT(24))
+#define UART_TX_SCLK_EN_V  0x1
+#define UART_TX_SCLK_EN_S  24
+/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Write 1 then write 0 to this bit  reset UART Tx/Rx.*/
+#define UART_RST_CORE  (BIT(23))
+#define UART_RST_CORE_M  (BIT(23))
+#define UART_RST_CORE_V  0x1
+#define UART_RST_CORE_S  23
+/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: Set this bit to enable UART Tx/Rx clock.*/
+#define UART_SCLK_EN  (BIT(22))
+#define UART_SCLK_EN_M  (BIT(22))
+#define UART_SCLK_EN_V  0x1
+#define UART_SCLK_EN_S  22
+/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */
+/*description: UART clock source select. 1: 80Mhz  2: 8Mhz  3: XTAL.*/
+#define UART_SCLK_SEL  0x00000003
+#define UART_SCLK_SEL_M  ((UART_SCLK_SEL_V)<<(UART_SCLK_SEL_S))
+#define UART_SCLK_SEL_V  0x3
+#define UART_SCLK_SEL_S  20
+/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */
+/*description: The integral part of the frequency divider factor.*/
+#define UART_SCLK_DIV_NUM  0x000000FF
+#define UART_SCLK_DIV_NUM_M  ((UART_SCLK_DIV_NUM_V)<<(UART_SCLK_DIV_NUM_S))
+#define UART_SCLK_DIV_NUM_V  0xFF
+#define UART_SCLK_DIV_NUM_S  12
+/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */
+/*description: The numerator of the frequency divider factor.*/
+#define UART_SCLK_DIV_A  0x0000003F
+#define UART_SCLK_DIV_A_M  ((UART_SCLK_DIV_A_V)<<(UART_SCLK_DIV_A_S))
+#define UART_SCLK_DIV_A_V  0x3F
+#define UART_SCLK_DIV_A_S  6
+/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: The  denominator of the frequency divider factor.*/
+#define UART_SCLK_DIV_B  0x0000003F
+#define UART_SCLK_DIV_B_M  ((UART_SCLK_DIV_B_V)<<(UART_SCLK_DIV_B_S))
+#define UART_SCLK_DIV_B_V  0x3F
+#define UART_SCLK_DIV_B_S  0
+
+#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x7c)
+/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2008270 ; */
+/*description: This is the version register.*/
+#define UART_DATE  0xFFFFFFFF
+#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
+#define UART_DATE_V  0xFFFFFFFF
+#define UART_DATE_S  0
+
+#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x80)
+/* UART_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Software write 1 would synchronize registers into UART Core clock
+ domain and would be cleared by hardware after synchronization is done.*/
+#define UART_UPDATE  (BIT(31))
+#define UART_UPDATE_M  (BIT(31))
+#define UART_UPDATE_V  0x1
+#define UART_UPDATE_S  31
+/* UART_HIGH_SPEED : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This bit used to select synchronize mode. 1: Registers are auto
+ synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers  software needs to write 1 to UART_REG_UPDATE to synchronize registers.*/
+#define UART_HIGH_SPEED  (BIT(30))
+#define UART_HIGH_SPEED_M  (BIT(30))
+#define UART_HIGH_SPEED_V  0x1
+#define UART_HIGH_SPEED_S  30
+/* UART_ID : R/W ;bitpos:[29:0] ;default: 30'h0500 ; */
+/*description: This register is used to configure the uart_id.*/
+#define UART_ID  0x3FFFFFFF
+#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
+#define UART_ID_V  0x3FFFFFFF
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UART_REG_H_ */
diff --git a/components/soc/esp32c3/register/soc/uart_struct.h b/components/soc/esp32c3/register/soc/uart_struct.h
new file mode 100644
index 00000000000..a93528b0900
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/uart_struct.h
@@ -0,0 +1,397 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct uart_dev_s {
+    union {
+        struct {
+            uint32_t rw_byte;                 /*a*/
+        };
+        uint32_t val;
+    } ahb_fifo;
+    union {
+        struct {
+            uint32_t rxfifo_full:              1;       /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
+            uint32_t txfifo_empty:             1;       /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
+            uint32_t parity_err:               1;       /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
+            uint32_t frm_err:                  1;       /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
+            uint32_t rxfifo_ovf:               1;       /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
+            uint32_t dsr_chg:                  1;       /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
+            uint32_t cts_chg:                  1;       /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
+            uint32_t brk_det:                  1;       /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
+            uint32_t rxfifo_tout:              1;       /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
+            uint32_t sw_xon:                   1;       /*This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1.*/
+            uint32_t sw_xoff:                  1;       /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
+            uint32_t glitch_det:               1;       /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
+            uint32_t tx_brk_done:              1;       /*This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters  after all data in Tx-FIFO are sent.*/
+            uint32_t tx_brk_idle_done:         1;       /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.*/
+            uint32_t tx_done:                  1;       /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
+            uint32_t rs485_parity_err:         1;       /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
+            uint32_t rs485_frm_err:            1;       /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
+            uint32_t rs485_clash:              1;       /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
+            uint32_t at_cmd_char_det:          1;       /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
+            uint32_t wakeup:                   1;       /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
+            uint32_t reserved20:              12;       /*Reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rxfifo_full:             1;        /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
+            uint32_t txfifo_empty:            1;        /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
+            uint32_t parity_err:              1;        /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
+            uint32_t frm_err:                 1;        /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
+            uint32_t rxfifo_ovf:              1;        /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
+            uint32_t dsr_chg:                 1;        /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
+            uint32_t cts_chg:                 1;        /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
+            uint32_t brk_det:                 1;        /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
+            uint32_t rxfifo_tout:             1;        /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
+            uint32_t sw_xon:                  1;        /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
+            uint32_t sw_xoff:                 1;        /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
+            uint32_t glitch_det:              1;        /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
+            uint32_t tx_brk_done:             1;        /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
+            uint32_t tx_brk_idle_done:        1;        /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
+            uint32_t tx_done:                 1;        /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
+            uint32_t rs485_parity_err:        1;        /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
+            uint32_t rs485_frm_err:           1;        /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
+            uint32_t rs485_clash:             1;        /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
+            uint32_t at_cmd_char_det:         1;        /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
+            uint32_t wakeup:                  1;        /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
+            uint32_t reserved20:             12;        /*Reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rxfifo_full:              1;       /*This is the enable bit for rxfifo_full_int_st register.*/
+            uint32_t txfifo_empty:             1;       /*This is the enable bit for txfifo_empty_int_st register.*/
+            uint32_t parity_err:               1;       /*This is the enable bit for parity_err_int_st register.*/
+            uint32_t frm_err:                  1;       /*This is the enable bit for frm_err_int_st register.*/
+            uint32_t rxfifo_ovf:               1;       /*This is the enable bit for rxfifo_ovf_int_st register.*/
+            uint32_t dsr_chg:                  1;       /*This is the enable bit for dsr_chg_int_st register.*/
+            uint32_t cts_chg:                  1;       /*This is the enable bit for cts_chg_int_st register.*/
+            uint32_t brk_det:                  1;       /*This is the enable bit for brk_det_int_st register.*/
+            uint32_t rxfifo_tout:              1;       /*This is the enable bit for rxfifo_tout_int_st register.*/
+            uint32_t sw_xon:                   1;       /*This is the enable bit for sw_xon_int_st register.*/
+            uint32_t sw_xoff:                  1;       /*This is the enable bit for sw_xoff_int_st register.*/
+            uint32_t glitch_det:               1;       /*This is the enable bit for glitch_det_int_st register.*/
+            uint32_t tx_brk_done:              1;       /*This is the enable bit for tx_brk_done_int_st register.*/
+            uint32_t tx_brk_idle_done:         1;       /*This is the enable bit for tx_brk_idle_done_int_st register.*/
+            uint32_t tx_done:                  1;       /*This is the enable bit for tx_done_int_st register.*/
+            uint32_t rs485_parity_err:         1;       /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_frm_err:            1;       /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_clash:              1;       /*This is the enable bit for rs485_clash_int_st register.*/
+            uint32_t at_cmd_char_det:          1;       /*This is the enable bit for at_cmd_char_det_int_st register.*/
+            uint32_t wakeup:                   1;       /*This is the enable bit for uart_wakeup_int_st register.*/
+            uint32_t reserved20:              12;       /*Reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rxfifo_full:              1;       /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
+            uint32_t txfifo_empty:             1;       /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
+            uint32_t parity_err:               1;       /*Set this bit to clear parity_err_int_raw interrupt.*/
+            uint32_t frm_err:                  1;       /*Set this bit to clear frm_err_int_raw interrupt.*/
+            uint32_t rxfifo_ovf:               1;       /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
+            uint32_t dsr_chg:                  1;       /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
+            uint32_t cts_chg:                  1;       /*Set this bit to clear the cts_chg_int_raw interrupt.*/
+            uint32_t brk_det:                  1;       /*Set this bit to clear the brk_det_int_raw interrupt.*/
+            uint32_t rxfifo_tout:              1;       /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
+            uint32_t sw_xon:                   1;       /*Set this bit to clear the sw_xon_int_raw interrupt.*/
+            uint32_t sw_xoff:                  1;       /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
+            uint32_t glitch_det:               1;       /*Set this bit to clear the glitch_det_int_raw interrupt.*/
+            uint32_t tx_brk_done:              1;       /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
+            uint32_t tx_brk_idle_done:         1;       /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
+            uint32_t tx_done:                  1;       /*Set this bit to clear the tx_done_int_raw interrupt.*/
+            uint32_t rs485_parity_err:         1;       /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
+            uint32_t rs485_frm_err:            1;       /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
+            uint32_t rs485_clash:              1;       /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
+            uint32_t at_cmd_char_det:          1;       /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
+            uint32_t wakeup:                   1;       /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
+            uint32_t reserved20:              12;       /*Reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t div_int:    12;                    /*The integral part of the frequency divider factor.*/
+            uint32_t reserved12:  8;
+            uint32_t div_frag:    4;                    /*The decimal part of the frequency divider factor.*/
+            uint32_t reserved24:  8;                    /*Reserved*/
+        };
+        uint32_t val;
+    } clk_div;
+    union {
+        struct {
+            uint32_t glitch_filt:    8;                 /*when input pulse width is lower than this value  the pulse is ignored.*/
+            uint32_t glitch_filt_en: 1;                 /*Set this bit to enable Rx signal filter.*/
+            uint32_t reserved9:     23;
+        };
+        uint32_t val;
+    } rx_filt;
+    union {
+        struct {
+            uint32_t rxfifo_cnt:10;                     /*Stores the byte number of valid data in Rx-FIFO.*/
+            uint32_t reserved10: 3;
+            uint32_t dsrn:       1;                     /*The register represent the level value of the internal uart dsr signal.*/
+            uint32_t ctsn:       1;                     /*This register represent the level value of the internal uart cts signal.*/
+            uint32_t rxd:        1;                     /*This register represent the  level value of the internal uart rxd signal.*/
+            uint32_t txfifo_cnt:10;                     /*Stores the byte number of data in Tx-FIFO.*/
+            uint32_t reserved26: 3;                     /*Reserved*/
+            uint32_t dtrn:       1;                     /*This bit represents the level of the internal uart dtr signal.*/
+            uint32_t rtsn:       1;                     /*This bit represents the level of the internal uart rts signal.*/
+            uint32_t txd:        1;                     /*This bit represents the  level of the internal uart txd signal.*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t parity:       1;                   /*This register is used to configure the parity check mode.*/
+            uint32_t parity_en:    1;                   /*Set this bit to enable uart parity check.*/
+            uint32_t bit_num:      2;                   /*This register is used to set the length of data.*/
+            uint32_t stop_bit_num: 2;                   /*This register is used to set the length of  stop bit.*/
+            uint32_t sw_rts:       1;                   /*This register is used to configure the software rts signal which is used in software flow control.*/
+            uint32_t sw_dtr:       1;                   /*This register is used to configure the software dtr signal which is used in software flow control.*/
+            uint32_t txd_brk:      1;                   /*Set this bit to enable transmitter to  send NULL when the process of sending data is done.*/
+            uint32_t irda_dplx:    1;                   /*Set this bit to enable IrDA loopback mode.*/
+            uint32_t irda_tx_en:   1;                   /*This is the start enable bit for IrDA transmitter.*/
+            uint32_t irda_wctl:    1;                   /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
+            uint32_t irda_tx_inv:  1;                   /*Set this bit to invert the level of  IrDA transmitter.*/
+            uint32_t irda_rx_inv:  1;                   /*Set this bit to invert the level of IrDA receiver.*/
+            uint32_t loopback:     1;                   /*Set this bit to enable uart loopback test mode.*/
+            uint32_t tx_flow_en:   1;                   /*Set this bit to enable flow control function for transmitter.*/
+            uint32_t irda_en:      1;                   /*Set this bit to enable IrDA protocol.*/
+            uint32_t rxfifo_rst:   1;                   /*Set this bit to reset the uart receive-FIFO.*/
+            uint32_t txfifo_rst:   1;                   /*Set this bit to reset the uart transmit-FIFO.*/
+            uint32_t rxd_inv:      1;                   /*Set this bit to inverse the level value of uart rxd signal.*/
+            uint32_t cts_inv:      1;                   /*Set this bit to inverse the level value of uart cts signal.*/
+            uint32_t dsr_inv:      1;                   /*Set this bit to inverse the level value of uart dsr signal.*/
+            uint32_t txd_inv:      1;                   /*Set this bit to inverse the level value of uart txd signal.*/
+            uint32_t rts_inv:      1;                   /*Set this bit to inverse the level value of uart rts signal.*/
+            uint32_t dtr_inv:      1;                   /*Set this bit to inverse the level value of uart dtr signal.*/
+            uint32_t clk_en:       1;                   /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
+            uint32_t err_wr_mask:  1;                   /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.*/
+            uint32_t autobaud_en:  1;                   /*This is the enable bit for detecting baudrate.*/
+            uint32_t mem_clk_en:   1;                   /*UART memory clock gate enable signal.*/
+            uint32_t reserved29:   3;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t rxfifo_full_thrhd:  9;             /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
+            uint32_t txfifo_empty_thrhd: 9;             /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
+            uint32_t dis_rx_dat_ovf:     1;             /*Disable UART Rx data overflow detect.*/
+            uint32_t rx_tout_flow_dis:   1;             /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
+            uint32_t rx_flow_en:         1;             /*This is the flow enable bit for UART receiver.*/
+            uint32_t rx_tout_en:         1;             /*This is the enable bit for uart receiver's timeout function.*/
+            uint32_t reserved22:        10;
+        };
+        uint32_t val;
+    } conf1;
+    union {
+        struct {
+            uint32_t min_cnt:         12;               /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
+            uint32_t reserved12:      20;               /*Reserved*/
+        };
+        uint32_t val;
+    } lowpulse;
+    union {
+        struct {
+            uint32_t min_cnt:          12;              /*This register stores  the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process.*/
+            uint32_t reserved12:       20;              /*Reserved*/
+        };
+        uint32_t val;
+    } highpulse;
+    union {
+        struct {
+            uint32_t edge_cnt:    10;                   /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
+            uint32_t reserved10:  22;                   /*Reserved*/
+        };
+        uint32_t val;
+    } rxd_cnt;
+    union {
+        struct {
+            uint32_t sw_flow_con_en: 1;                 /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
+            uint32_t xonoff_del:     1;                 /*Set this bit to remove flow control char from the received data.*/
+            uint32_t force_xon:      1;                 /*Set this bit to enable the transmitter to go on sending data.*/
+            uint32_t force_xoff:     1;                 /*Set this bit to stop the  transmitter from sending data.*/
+            uint32_t send_xon:       1;                 /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
+            uint32_t send_xoff:      1;                 /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
+            uint32_t reserved6:     26;                 /*Reserved*/
+        };
+        uint32_t val;
+    } flow_conf;
+    union {
+        struct {
+            uint32_t active_threshold:10;               /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
+            uint32_t reserved10:      22;               /*Reserved*/
+        };
+        uint32_t val;
+    } sleep_conf;
+    union {
+        struct {
+            uint32_t xoff_threshold: 9;                 /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1  it will send a Xoff char.*/
+            uint32_t xoff_character: 8;                 /*This register stores the Xoff flow control char.*/
+            uint32_t reserved17:    15;                 /*Reserved*/
+        };
+        uint32_t val;
+    } swfc_conf0;
+    union {
+        struct {
+            uint32_t xon_threshold: 9;                  /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1  it will send a Xon char.*/
+            uint32_t xon_character: 8;                  /*This register stores the Xon flow control char.*/
+            uint32_t reserved17:   15;                  /*Reserved*/
+        };
+        uint32_t val;
+    } swfc_conf1;
+    union {
+        struct {
+            uint32_t tx_brk_num: 8;                     /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
+            uint32_t reserved8: 24;
+        };
+        uint32_t val;
+    } txbrk_conf;
+    union {
+        struct {
+            uint32_t rx_idle_thrhd:10;                  /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
+            uint32_t tx_idle_num:  10;                  /*This register is used to configure the duration time between transfers.*/
+            uint32_t reserved20:   12;                  /*Reserved*/
+        };
+        uint32_t val;
+    } idle_conf;
+    union {
+        struct {
+            uint32_t en:               1;               /*Set this bit to choose the rs485 mode.*/
+            uint32_t dl0_en:           1;               /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t dl1_en:           1;               /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t tx_rx_en:         1;               /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.*/
+            uint32_t rx_busy_tx_en:    1;               /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/
+            uint32_t rx_dly_num:       1;               /*This register is used to delay the receiver's internal data signal.*/
+            uint32_t tx_dly_num:       4;               /*This register is used to delay the transmitter's internal data signal.*/
+            uint32_t reserved10:      22;               /*Reserved*/
+        };
+        uint32_t val;
+    } rs485_conf;
+    union {
+        struct {
+            uint32_t pre_idle_num:16;                   /*This register is used to configure the idle duration time before the first at_cmd is received by receiver.*/
+            uint32_t reserved16:  16;                   /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_precnt;
+    union {
+        struct {
+            uint32_t post_idle_num:16;                  /*This register is used to configure the duration time between the last at_cmd and the next data.*/
+            uint32_t reserved16:   16;                  /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_postcnt;
+    union {
+        struct {
+            uint32_t rx_gap_tout:16;                    /*This register is used to configure the duration time between the at_cmd chars.*/
+            uint32_t reserved16: 16;                    /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_gaptout;
+    union {
+        struct {
+            uint32_t data:        8;                    /*This register is used to configure the content of at_cmd char.*/
+            uint32_t at_char_num: 8;                    /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
+            uint32_t reserved16: 16;                    /*Reserved*/
+        };
+        uint32_t val;
+    } at_cmd_char;
+    union {
+        struct {
+            uint32_t reserved0:     1;
+            uint32_t rx_size:       3;                  /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
+            uint32_t tx_size:       3;                  /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
+            uint32_t rx_flow_thrhd: 9;                  /*This register is used to configure the maximum amount of data that can be received  when hardware flow control works.*/
+            uint32_t rx_tout_thrhd:10;                  /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
+            uint32_t force_pd:      1;                  /*Set this bit to force power down UART memory.*/
+            uint32_t force_pu:      1;                  /*Set this bit to force power up UART memory.*/
+            uint32_t reserved28:    4;
+        };
+        uint32_t val;
+    } mem_conf;
+    union {
+        struct {
+            uint32_t apb_tx_waddr:10;                   /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
+            uint32_t reserved10:   1;                   /*Reserved*/
+            uint32_t tx_raddr:    10;                   /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
+            uint32_t reserved21:  11;                   /*Reserved*/
+        };
+        uint32_t val;
+    } mem_tx_status;
+    union {
+        struct {
+            uint32_t apb_rx_raddr:10;                   /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
+            uint32_t reserved10:   1;                   /*Reserved*/
+            uint32_t rx_waddr:    10;                   /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
+            uint32_t reserved21:  11;                   /*Reserved*/
+        };
+        uint32_t val;
+    } mem_rx_status;
+    union {
+        struct {
+            uint32_t st_urx_out: 4;                     /*This is the status register of receiver.*/
+            uint32_t st_utx_out: 4;                     /*This is the status register of transmitter.*/
+            uint32_t reserved8: 24;                     /*Reserved*/
+        };
+        uint32_t val;
+    } fsm_status;
+    union {
+        struct {
+            uint32_t min_cnt:        12;                /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
+            uint32_t reserved12:     20;                /*Reserved*/
+        };
+        uint32_t val;
+    } pospulse;
+    union {
+        struct {
+            uint32_t min_cnt:        12;                /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
+            uint32_t reserved12:     20;                /*Reserved*/
+        };
+        uint32_t val;
+    } negpulse;
+    union {
+        struct {
+            uint32_t sclk_div_b:   6;                   /*The  denominator of the frequency divider factor.*/
+            uint32_t sclk_div_a:   6;                   /*The numerator of the frequency divider factor.*/
+            uint32_t sclk_div_num: 8;                   /*The integral part of the frequency divider factor.*/
+            uint32_t sclk_sel:     2;                   /*UART clock source select. 1: 80Mhz  2: 8Mhz  3: XTAL.*/
+            uint32_t sclk_en:      1;                   /*Set this bit to enable UART Tx/Rx clock.*/
+            uint32_t rst_core:     1;                   /*Write 1 then write 0 to this bit  reset UART Tx/Rx.*/
+            uint32_t tx_sclk_en:   1;                   /*Set this bit to enable UART Tx clock.*/
+            uint32_t rx_sclk_en:   1;                   /*Set this bit to enable UART Rx clock.*/
+            uint32_t tx_rst_core:  1;                   /*Write 1 then write 0 to this bit  reset UART Tx.*/
+            uint32_t rx_rst_core:  1;                   /*Write 1 then write 0 to this bit  reset UART Rx.*/
+            uint32_t reserved28:   4;
+        };
+        uint32_t val;
+    } clk_conf;
+    uint32_t date;                                      /*UART Version register*/
+    union {
+        struct {
+            uint32_t id                            :    30;  /*This register is used to configure the uart_id.*/
+            uint32_t high_speed                    :    1;  /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
+            uint32_t update                        :    1;  /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
+        };
+        uint32_t val;
+    } id;
+} uart_dev_t;
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/uhci_reg.h b/components/soc/esp32c3/register/soc/uhci_reg.h
new file mode 100644
index 00000000000..f387de7963a
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/uhci_reg.h
@@ -0,0 +1,740 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_UHCI_REG_H_
+#define _SOC_UHCI_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+#define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
+/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: If this bit is set to 1  UHCI will end payload receive process
+ when NULL frame is received by UART.*/
+#define UHCI_UART_RX_BRK_EOF_EN  (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_M  (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_V  0x1
+#define UHCI_UART_RX_BRK_EOF_EN_S  12
+/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1'b1: Force clock on for register. 1'b0: Support clock only when
+ application writes registers.*/
+#define UHCI_CLK_EN  (BIT(11))
+#define UHCI_CLK_EN_M  (BIT(11))
+#define UHCI_CLK_EN_V  0x1
+#define UHCI_CLK_EN_S  11
+/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: Set this bit to enable data integrity checking by appending a
+ 16 bit CCITT-CRC to end of the payload.*/
+#define UHCI_ENCODE_CRC_EN  (BIT(10))
+#define UHCI_ENCODE_CRC_EN_M  (BIT(10))
+#define UHCI_ENCODE_CRC_EN_V  0x1
+#define UHCI_ENCODE_CRC_EN_S  10
+/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: If this bit is set to 1  UHCI decoder receiving payload data
+ is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0  UHCI decoder receiving payload data is end when 0xc0 is received.*/
+#define UHCI_LEN_EOF_EN  (BIT(9))
+#define UHCI_LEN_EOF_EN_M  (BIT(9))
+#define UHCI_LEN_EOF_EN_V  0x1
+#define UHCI_LEN_EOF_EN_S  9
+/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: If this bit is set to 1  UHCI will end the payload receiving
+ process when UART has been in idle state.*/
+#define UHCI_UART_IDLE_EOF_EN  (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_M  (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_V  0x1
+#define UHCI_UART_IDLE_EOF_EN_S  8
+/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: Set this bit to enable UHCI to receive the 16 bit CRC.*/
+#define UHCI_CRC_REC_EN  (BIT(7))
+#define UHCI_CRC_REC_EN_M  (BIT(7))
+#define UHCI_CRC_REC_EN_V  0x1
+#define UHCI_CRC_REC_EN_S  7
+/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: Set this bit to encode the data packet with a formatting header.*/
+#define UHCI_HEAD_EN  (BIT(6))
+#define UHCI_HEAD_EN_M  (BIT(6))
+#define UHCI_HEAD_EN_V  0x1
+#define UHCI_HEAD_EN_S  6
+/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: Set this bit to separate the data frame using a special char.*/
+#define UHCI_SEPER_EN  (BIT(5))
+#define UHCI_SEPER_EN_M  (BIT(5))
+#define UHCI_SEPER_EN_V  0x1
+#define UHCI_SEPER_EN_S  5
+/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to link up HCI and UART1.*/
+#define UHCI_UART1_CE  (BIT(3))
+#define UHCI_UART1_CE_M  (BIT(3))
+#define UHCI_UART1_CE_V  0x1
+#define UHCI_UART1_CE_S  3
+/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to link up HCI and UART0.*/
+#define UHCI_UART0_CE  (BIT(2))
+#define UHCI_UART0_CE_M  (BIT(2))
+#define UHCI_UART0_CE_V  0x1
+#define UHCI_UART0_CE_S  2
+/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Write 1  then write 0 to this bit to reset encode state machine.*/
+#define UHCI_RX_RST  (BIT(1))
+#define UHCI_RX_RST_M  (BIT(1))
+#define UHCI_RX_RST_V  0x1
+#define UHCI_RX_RST_S  1
+/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Write 1  then write 0 to this bit to reset decode state machine.*/
+#define UHCI_TX_RST  (BIT(0))
+#define UHCI_TX_RST_M  (BIT(0))
+#define UHCI_TX_RST_V  0x1
+#define UHCI_TX_RST_S  0
+
+#define UHCI_INT_RAW_REG(i)          (REG_UHCI_BASE(i) + 0x4)
+/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Soft control int raw bit.*/
+#define UHCI_APP_CTRL1_INT_RAW  (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_V  0x1
+#define UHCI_APP_CTRL1_INT_RAW_S  8
+/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Soft control int raw bit.*/
+#define UHCI_APP_CTRL0_INT_RAW  (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_V  0x1
+#define UHCI_APP_CTRL0_INT_RAW_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit. Triggered when there are some
+ errors in EOF in the*/
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S  6
+/* UHCI_SEND_A_Q_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_A_Q_INT_RAW  (BIT(5))
+#define UHCI_SEND_A_Q_INT_RAW_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_RAW_V  0x1
+#define UHCI_SEND_A_Q_INT_RAW_S  5
+/* UHCI_SEND_S_Q_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_S_Q_INT_RAW  (BIT(4))
+#define UHCI_SEND_S_Q_INT_RAW_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_RAW_V  0x1
+#define UHCI_SEND_S_Q_INT_RAW_S  4
+/* UHCI_TX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_HUNG_INT_RAW  (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_V  0x1
+#define UHCI_TX_HUNG_INT_RAW_S  3
+/* UHCI_RX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_HUNG_INT_RAW  (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_V  0x1
+#define UHCI_RX_HUNG_INT_RAW_S  2
+/* UHCI_TX_START_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_START_INT_RAW  (BIT(1))
+#define UHCI_TX_START_INT_RAW_M  (BIT(1))
+#define UHCI_TX_START_INT_RAW_V  0x1
+#define UHCI_TX_START_INT_RAW_S  1
+/* UHCI_RX_START_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_START_INT_RAW  (BIT(0))
+#define UHCI_RX_START_INT_RAW_M  (BIT(0))
+#define UHCI_RX_START_INT_RAW_V  0x1
+#define UHCI_RX_START_INT_RAW_S  0
+
+#define UHCI_INT_ST_REG(i)          (REG_UHCI_BASE(i) + 0x8)
+/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL1_INT_ST  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_V  0x1
+#define UHCI_APP_CTRL1_INT_ST_S  8
+/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL0_INT_ST  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_V  0x1
+#define UHCI_APP_CTRL0_INT_ST_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_OUTLINK_EOF_ERR_INT_ST  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
+/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_A_Q_INT_ST  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ST_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ST_V  0x1
+#define UHCI_SEND_A_Q_INT_ST_S  5
+/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_S_Q_INT_ST  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ST_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ST_V  0x1
+#define UHCI_SEND_S_Q_INT_ST_S  4
+/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_HUNG_INT_ST  (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_V  0x1
+#define UHCI_TX_HUNG_INT_ST_S  3
+/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_HUNG_INT_ST  (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_V  0x1
+#define UHCI_RX_HUNG_INT_ST_S  2
+/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_START_INT_ST  (BIT(1))
+#define UHCI_TX_START_INT_ST_M  (BIT(1))
+#define UHCI_TX_START_INT_ST_V  0x1
+#define UHCI_TX_START_INT_ST_S  1
+/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_START_INT_ST  (BIT(0))
+#define UHCI_RX_START_INT_ST_M  (BIT(0))
+#define UHCI_RX_START_INT_ST_V  0x1
+#define UHCI_RX_START_INT_ST_S  0
+
+#define UHCI_INT_ENA_REG(i)          (REG_UHCI_BASE(i) + 0xC)
+/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL1_INT_ENA  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_V  0x1
+#define UHCI_APP_CTRL1_INT_ENA_S  8
+/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL0_INT_ENA  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_V  0x1
+#define UHCI_APP_CTRL0_INT_ENA_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
+/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_A_Q_INT_ENA  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ENA_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ENA_V  0x1
+#define UHCI_SEND_A_Q_INT_ENA_S  5
+/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_S_Q_INT_ENA  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ENA_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ENA_V  0x1
+#define UHCI_SEND_S_Q_INT_ENA_S  4
+/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_HUNG_INT_ENA  (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_V  0x1
+#define UHCI_TX_HUNG_INT_ENA_S  3
+/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_HUNG_INT_ENA  (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_V  0x1
+#define UHCI_RX_HUNG_INT_ENA_S  2
+/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_START_INT_ENA  (BIT(1))
+#define UHCI_TX_START_INT_ENA_M  (BIT(1))
+#define UHCI_TX_START_INT_ENA_V  0x1
+#define UHCI_TX_START_INT_ENA_S  1
+/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_START_INT_ENA  (BIT(0))
+#define UHCI_RX_START_INT_ENA_M  (BIT(0))
+#define UHCI_RX_START_INT_ENA_V  0x1
+#define UHCI_RX_START_INT_ENA_S  0
+
+#define UHCI_INT_CLR_REG(i)          (REG_UHCI_BASE(i) + 0x10)
+/* UHCI_APP_CTRL1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL1_INT_CLR  (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_V  0x1
+#define UHCI_APP_CTRL1_INT_CLR_S  8
+/* UHCI_APP_CTRL0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_APP_CTRL0_INT_CLR  (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_V  0x1
+#define UHCI_APP_CTRL0_INT_CLR_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
+/* UHCI_SEND_A_Q_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_A_Q_INT_CLR  (BIT(5))
+#define UHCI_SEND_A_Q_INT_CLR_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_CLR_V  0x1
+#define UHCI_SEND_A_Q_INT_CLR_S  5
+/* UHCI_SEND_S_Q_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SEND_S_Q_INT_CLR  (BIT(4))
+#define UHCI_SEND_S_Q_INT_CLR_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_CLR_V  0x1
+#define UHCI_SEND_S_Q_INT_CLR_S  4
+/* UHCI_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_HUNG_INT_CLR  (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_V  0x1
+#define UHCI_TX_HUNG_INT_CLR_S  3
+/* UHCI_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_HUNG_INT_CLR  (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_V  0x1
+#define UHCI_RX_HUNG_INT_CLR_S  2
+/* UHCI_TX_START_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_START_INT_CLR  (BIT(1))
+#define UHCI_TX_START_INT_CLR_M  (BIT(1))
+#define UHCI_TX_START_INT_CLR_V  0x1
+#define UHCI_TX_START_INT_CLR_S  1
+/* UHCI_RX_START_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_START_INT_CLR  (BIT(0))
+#define UHCI_RX_START_INT_CLR_M  (BIT(0))
+#define UHCI_RX_START_INT_CLR_V  0x1
+#define UHCI_RX_START_INT_CLR_S  0
+
+#define UHCI_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x14)
+/* UHCI_SW_START : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SW_START  (BIT(8))
+#define UHCI_SW_START_M  (BIT(8))
+#define UHCI_SW_START_V  0x1
+#define UHCI_SW_START_S  8
+/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_WAIT_SW_START  (BIT(7))
+#define UHCI_WAIT_SW_START_M  (BIT(7))
+#define UHCI_WAIT_SW_START_V  0x1
+#define UHCI_WAIT_SW_START_S  7
+/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TX_ACK_NUM_RE  (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_M  (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_V  0x1
+#define UHCI_TX_ACK_NUM_RE_S  5
+/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TX_CHECK_SUM_RE  (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_M  (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_V  0x1
+#define UHCI_TX_CHECK_SUM_RE_S  4
+/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SAVE_HEAD  (BIT(3))
+#define UHCI_SAVE_HEAD_M  (BIT(3))
+#define UHCI_SAVE_HEAD_V  0x1
+#define UHCI_SAVE_HEAD_S  3
+/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_CRC_DISABLE  (BIT(2))
+#define UHCI_CRC_DISABLE_M  (BIT(2))
+#define UHCI_CRC_DISABLE_V  0x1
+#define UHCI_CRC_DISABLE_S  2
+/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_CHECK_SEQ_EN  (BIT(1))
+#define UHCI_CHECK_SEQ_EN_M  (BIT(1))
+#define UHCI_CHECK_SEQ_EN_V  0x1
+#define UHCI_CHECK_SEQ_EN_S  1
+/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_CHECK_SUM_EN  (BIT(0))
+#define UHCI_CHECK_SUM_EN_M  (BIT(0))
+#define UHCI_CHECK_SUM_EN_V  0x1
+#define UHCI_CHECK_SUM_EN_S  0
+
+#define UHCI_STATE0_REG(i)          (REG_UHCI_BASE(i) + 0x18)
+/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_DECODE_STATE  0x00000007
+#define UHCI_DECODE_STATE_M  ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
+#define UHCI_DECODE_STATE_V  0x7
+#define UHCI_DECODE_STATE_S  3
+/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_RX_ERR_CAUSE  0x00000007
+#define UHCI_RX_ERR_CAUSE_M  ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
+#define UHCI_RX_ERR_CAUSE_V  0x7
+#define UHCI_RX_ERR_CAUSE_S  0
+
+#define UHCI_STATE1_REG(i)          (REG_UHCI_BASE(i) + 0x1C)
+/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_ENCODE_STATE  0x00000007
+#define UHCI_ENCODE_STATE_M  ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
+#define UHCI_ENCODE_STATE_V  0x7
+#define UHCI_ENCODE_STATE_S  0
+
+#define UHCI_ESCAPE_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x20)
+/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_13_ESC_EN  (BIT(7))
+#define UHCI_RX_13_ESC_EN_M  (BIT(7))
+#define UHCI_RX_13_ESC_EN_V  0x1
+#define UHCI_RX_13_ESC_EN_S  7
+/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_RX_11_ESC_EN  (BIT(6))
+#define UHCI_RX_11_ESC_EN_M  (BIT(6))
+#define UHCI_RX_11_ESC_EN_V  0x1
+#define UHCI_RX_11_ESC_EN_S  6
+/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_RX_DB_ESC_EN  (BIT(5))
+#define UHCI_RX_DB_ESC_EN_M  (BIT(5))
+#define UHCI_RX_DB_ESC_EN_V  0x1
+#define UHCI_RX_DB_ESC_EN_S  5
+/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_RX_C0_ESC_EN  (BIT(4))
+#define UHCI_RX_C0_ESC_EN_M  (BIT(4))
+#define UHCI_RX_C0_ESC_EN_V  0x1
+#define UHCI_RX_C0_ESC_EN_S  4
+/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_13_ESC_EN  (BIT(3))
+#define UHCI_TX_13_ESC_EN_M  (BIT(3))
+#define UHCI_TX_13_ESC_EN_V  0x1
+#define UHCI_TX_13_ESC_EN_S  3
+/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_TX_11_ESC_EN  (BIT(2))
+#define UHCI_TX_11_ESC_EN_M  (BIT(2))
+#define UHCI_TX_11_ESC_EN_V  0x1
+#define UHCI_TX_11_ESC_EN_S  2
+/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TX_DB_ESC_EN  (BIT(1))
+#define UHCI_TX_DB_ESC_EN_M  (BIT(1))
+#define UHCI_TX_DB_ESC_EN_V  0x1
+#define UHCI_TX_DB_ESC_EN_S  1
+/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TX_C0_ESC_EN  (BIT(0))
+#define UHCI_TX_C0_ESC_EN_M  (BIT(0))
+#define UHCI_TX_C0_ESC_EN_V  0x1
+#define UHCI_TX_C0_ESC_EN_S  0
+
+#define UHCI_HUNG_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x24)
+/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_RXFIFO_TIMEOUT_ENA  (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_M  (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x1
+#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
+/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_RXFIFO_TIMEOUT_SHIFT  0x00000007
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x7
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
+/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
+/*description: a*/
+#define UHCI_RXFIFO_TIMEOUT  0x000000FF
+#define UHCI_RXFIFO_TIMEOUT_M  ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
+#define UHCI_RXFIFO_TIMEOUT_V  0xFF
+#define UHCI_RXFIFO_TIMEOUT_S  12
+/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_TXFIFO_TIMEOUT_ENA  (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_M  (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x1
+#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
+/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: a*/
+#define UHCI_TXFIFO_TIMEOUT_SHIFT  0x00000007
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x7
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
+/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: a*/
+#define UHCI_TXFIFO_TIMEOUT  0x000000FF
+#define UHCI_TXFIFO_TIMEOUT_M  ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
+#define UHCI_TXFIFO_TIMEOUT_V  0xFF
+#define UHCI_TXFIFO_TIMEOUT_S  0
+
+#define UHCI_ACK_NUM_REG(i)          (REG_UHCI_BASE(i) + 0x28)
+/* UHCI_ACK_NUM_LOAD : WT ;bitpos:[3] ;default: 1'b1 ; */
+/*description: a*/
+#define UHCI_ACK_NUM_LOAD  (BIT(3))
+#define UHCI_ACK_NUM_LOAD_M  (BIT(3))
+#define UHCI_ACK_NUM_LOAD_V  0x1
+#define UHCI_ACK_NUM_LOAD_S  3
+/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: */
+#define UHCI_ACK_NUM  0x00000007
+#define UHCI_ACK_NUM_M  ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S))
+#define UHCI_ACK_NUM_V  0x7
+#define UHCI_ACK_NUM_S  0
+
+#define UHCI_RX_HEAD_REG(i)          (REG_UHCI_BASE(i) + 0x2C)
+/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_RX_HEAD  0xFFFFFFFF
+#define UHCI_RX_HEAD_M  ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
+#define UHCI_RX_HEAD_V  0xFFFFFFFF
+#define UHCI_RX_HEAD_S  0
+
+#define UHCI_QUICK_SENT_REG(i)          (REG_UHCI_BASE(i) + 0x30)
+/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_ALWAYS_SEND_EN  (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_M  (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_V  0x1
+#define UHCI_ALWAYS_SEND_EN_S  7
+/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: a*/
+#define UHCI_ALWAYS_SEND_NUM  0x00000007
+#define UHCI_ALWAYS_SEND_NUM_M  ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
+#define UHCI_ALWAYS_SEND_NUM_V  0x7
+#define UHCI_ALWAYS_SEND_NUM_S  4
+/* UHCI_SINGLE_SEND_EN : R/W/SC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: a*/
+#define UHCI_SINGLE_SEND_EN  (BIT(3))
+#define UHCI_SINGLE_SEND_EN_M  (BIT(3))
+#define UHCI_SINGLE_SEND_EN_V  0x1
+#define UHCI_SINGLE_SEND_EN_S  3
+/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: a*/
+#define UHCI_SINGLE_SEND_NUM  0x00000007
+#define UHCI_SINGLE_SEND_NUM_M  ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
+#define UHCI_SINGLE_SEND_NUM_V  0x7
+#define UHCI_SINGLE_SEND_NUM_S  0
+
+#define UHCI_Q0_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x34)
+/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q0_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_M  ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
+#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_S  0
+
+#define UHCI_Q0_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x38)
+/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q0_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_M  ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
+#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_S  0
+
+#define UHCI_Q1_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x3C)
+/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q1_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_M  ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
+#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_S  0
+
+#define UHCI_Q1_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x40)
+/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q1_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_M  ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
+#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_S  0
+
+#define UHCI_Q2_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x44)
+/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q2_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_M  ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
+#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_S  0
+
+#define UHCI_Q2_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x48)
+/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q2_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_M  ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
+#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_S  0
+
+#define UHCI_Q3_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x4C)
+/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q3_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_M  ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
+#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_S  0
+
+#define UHCI_Q3_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x50)
+/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q3_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_M  ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
+#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_S  0
+
+#define UHCI_Q4_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x54)
+/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q4_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_M  ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
+#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_S  0
+
+#define UHCI_Q4_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x58)
+/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q4_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_M  ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
+#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_S  0
+
+#define UHCI_Q5_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x5C)
+/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q5_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_M  ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
+#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_S  0
+
+#define UHCI_Q5_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x60)
+/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q5_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_M  ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
+#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_S  0
+
+#define UHCI_Q6_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x64)
+/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q6_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_M  ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
+#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_S  0
+
+#define UHCI_Q6_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x68)
+/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: a*/
+#define UHCI_SEND_Q6_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_M  ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
+#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_S  0
+
+#define UHCI_ESC_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x6C)
+/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
+/*description: a*/
+#define UHCI_SEPER_ESC_CHAR1  0x000000FF
+#define UHCI_SEPER_ESC_CHAR1_M  ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
+#define UHCI_SEPER_ESC_CHAR1_V  0xFF
+#define UHCI_SEPER_ESC_CHAR1_S  16
+/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_SEPER_ESC_CHAR0  0x000000FF
+#define UHCI_SEPER_ESC_CHAR0_M  ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
+#define UHCI_SEPER_ESC_CHAR0_V  0xFF
+#define UHCI_SEPER_ESC_CHAR0_S  8
+/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
+/*description: a*/
+#define UHCI_SEPER_CHAR  0x000000FF
+#define UHCI_SEPER_CHAR_M  ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
+#define UHCI_SEPER_CHAR_V  0xFF
+#define UHCI_SEPER_CHAR_S  0
+
+#define UHCI_ESC_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x70)
+/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
+/*description: a*/
+#define UHCI_ESC_SEQ0_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ0_CHAR1_M  ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
+#define UHCI_ESC_SEQ0_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ0_CHAR1_S  16
+/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_ESC_SEQ0_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ0_CHAR0_M  ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
+#define UHCI_ESC_SEQ0_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ0_CHAR0_S  8
+/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_ESC_SEQ0  0x000000FF
+#define UHCI_ESC_SEQ0_M  ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
+#define UHCI_ESC_SEQ0_V  0xFF
+#define UHCI_ESC_SEQ0_S  0
+
+#define UHCI_ESC_CONF2_REG(i)          (REG_UHCI_BASE(i) + 0x74)
+/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
+/*description: a*/
+#define UHCI_ESC_SEQ1_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ1_CHAR1_M  ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
+#define UHCI_ESC_SEQ1_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ1_CHAR1_S  16
+/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_ESC_SEQ1_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ1_CHAR0_M  ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
+#define UHCI_ESC_SEQ1_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ1_CHAR0_S  8
+/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
+/*description: a*/
+#define UHCI_ESC_SEQ1  0x000000FF
+#define UHCI_ESC_SEQ1_M  ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
+#define UHCI_ESC_SEQ1_V  0xFF
+#define UHCI_ESC_SEQ1_S  0
+
+#define UHCI_ESC_CONF3_REG(i)          (REG_UHCI_BASE(i) + 0x78)
+/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
+/*description: a*/
+#define UHCI_ESC_SEQ2_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ2_CHAR1_M  ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
+#define UHCI_ESC_SEQ2_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ2_CHAR1_S  16
+/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: a*/
+#define UHCI_ESC_SEQ2_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ2_CHAR0_M  ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
+#define UHCI_ESC_SEQ2_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ2_CHAR0_S  8
+/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
+/*description: a*/
+#define UHCI_ESC_SEQ2  0x000000FF
+#define UHCI_ESC_SEQ2_M  ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
+#define UHCI_ESC_SEQ2_V  0xFF
+#define UHCI_ESC_SEQ2_S  0
+
+#define UHCI_PKT_THRES_REG(i)          (REG_UHCI_BASE(i) + 0x7C)
+/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
+/*description: a*/
+#define UHCI_PKT_THRS  0x00001FFF
+#define UHCI_PKT_THRS_M  ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
+#define UHCI_PKT_THRS_V  0x1FFF
+#define UHCI_PKT_THRS_S  0
+
+#define UHCI_DATE_REG(i)          (REG_UHCI_BASE(i) + 0x80)
+/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007170 ; */
+/*description: a*/
+#define UHCI_DATE  0xFFFFFFFF
+#define UHCI_DATE_M  ((UHCI_DATE_V)<<(UHCI_DATE_S))
+#define UHCI_DATE_V  0xFFFFFFFF
+#define UHCI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UHCI_REG_H_ */
diff --git a/components/soc/esp32c3/include/soc/uhci_struct.h b/components/soc/esp32c3/register/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32c3/include/soc/uhci_struct.h
rename to components/soc/esp32c3/register/soc/uhci_struct.h
diff --git a/components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h
new file mode 100644
index 00000000000..6d908baec1b
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,993 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/** Configuration Registers */
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  USB_SERIAL_JTAG_EP1_REG.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
+ * Write and read byte data to/from UART Tx/Rx FIFO through this field.
+ * When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set  then user can write
+ * data (up to 64 bytes) into UART Tx FIFO. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check
+ * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to
+ * know how many data is received, then read that amount of data from UART
+ * Rx
+ * FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FF
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FF
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  USB_SERIAL_JTAG_CONF0_REG.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
+ * PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ * Enable software control USB D+ D-
+ * exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ * USB D+ D-
+ * exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0;
+ * Control single-end input high threshold. 1.76V to 2V, step
+ * 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003
+#define USB_SERIAL_JTAG_VREFL_S  3
+/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0;
+ * Control single-end input low threshold. 0.8V to 1.04V, step
+ * 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003
+#define USB_SERIAL_JTAG_VREFH_S  5
+/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ * Enable software control input
+ * threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ * Enable software control USB D+ D- pullup
+ * pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ * Control USB D+ pull
+ * up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ * Control USB D+ pull
+ * down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ * Control USB D- pull
+ * up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ * Control USB D- pull
+ * down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ * Control pull up
+ * value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ * Enable USB pad
+ * function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  USB_SERIAL_JTAG_TEST_REG.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ * Enable test of the USB
+ * pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ * USB pad one in
+ * test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ * USB D+ tx value in
+ * test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ * USB D- tx value in
+ * test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  USB_SERIAL_JTAG_MISC_CONF_REG.
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ * 1'h1: Force clock on for register. 1'h0: Support clock only when
+ * application writes
+ * registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  USB_SERIAL_JTAG_MEM_CONF_REG.
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ * 1: power down usb
+ * memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ * 1: Force clock on for usb
+ * memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+
+/** Status Registers */
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  USB_SERIAL_JTAG_EP1_CONF_REG.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ * Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ * This bit then stays 0 until data in UART Tx FIFO is read by the USB
+ * Host.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ * 1'b1: Indicate UART Tx FIFO is not full and data can be written into
+ * in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the
+ * data is sent to the USB
+ * Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ * 1'b1: Indicate there is data in UART Rx
+ * FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  USB_SERIAL_JTAG_JFIFO_ST_REG.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
+ * JTAG in fifo
+ * counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ * 1: JTAG in fifo is
+ * empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ * 1: JTAG in fifo is
+ * full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0;
+ * JTAT out fifo
+ * counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ * 1: JTAG out fifo is
+ * empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ * 1: JTAG out fifo is
+ * full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ * Write 1 to reset JTAG in
+ * fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ * Write 1 to reset JTAG out
+ * fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  USB_SERIAL_JTAG_FRAM_NUM_REG.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
+ * Frame index of received SOF
+ * frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FF
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FF
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  USB_SERIAL_JTAG_IN_EP0_ST_REG.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint
+ * 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint
+ * 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  USB_SERIAL_JTAG_IN_EP1_ST_REG.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint
+ * 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint
+ * 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  USB_SERIAL_JTAG_IN_EP2_ST_REG.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint
+ * 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint
+ * 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  USB_SERIAL_JTAG_IN_EP3_ST_REG.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint
+ * 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint
+ * 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  USB_SERIAL_JTAG_OUT_EP0_ST_REG.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 0. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are
+ * USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT
+ * EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  USB_SERIAL_JTAG_OUT_EP1_ST_REG.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 1. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are
+ * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT
+ * EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0;
+ * Data count in OUT endpoint 1 when one packet is
+ * received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  USB_SERIAL_JTAG_OUT_EP2_ST_REG.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 2. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are
+ * USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT
+ * EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+
+/** Interrupt Registers */
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  USB_SERIAL_JTAG_INT_RAW_REG.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ * The raw interrupt bit turns to high level when a flush command is
+ * received for IN endpoint 2 of
+ * JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ * The raw interrupt bit turns to high level when a SOF frame is
+ * received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ * The raw interrupt bit turns to high level when the Serial Port OUT
+ * Endpoint received one
+ * packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ * The raw interrupt bit turns to high level when the Serial Port IN
+ * Endpoint is
+ * empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ * The raw interrupt bit turns to high level when a PID error is
+ * detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ * The raw interrupt bit turns to high level when a CRC5 error is
+ * detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ * The raw interrupt bit turns to high level when a CRC16 error is
+ * detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ * The raw interrupt bit turns to high level when a bit stuffing error is
+ * detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ * The raw interrupt bit turns to high level when an IN token for IN
+ * endpoint 1 is
+ * received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ * The raw interrupt bit turns to high level when a USB bus reset is
+ * detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ * The raw interrupt bit turns to high level when OUT endpoint 1 received
+ * packet with zero
+ * payload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ * The raw interrupt bit turns to high level when OUT endpoint 2 received
+ * packet with zero
+ * payload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  USB_SERIAL_JTAG_INT_ST_REG.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  USB_SERIAL_JTAG_INT_ENA_REG.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  USB_SERIAL_JTAG_INT_CLR_REG.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+
+
+/** Version Registers */
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  USB_SERIAL_JTAG_DATE_REG.
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
+ * register
+ * version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFF
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFF
+#define USB_SERIAL_JTAG_DATE_S  0
+
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h b/components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h
new file mode 100644
index 00000000000..98b15060a42
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/usb_serial_jtag_struct.h
@@ -0,0 +1,254 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
+#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+typedef volatile struct usb_serial_jtag_dev_s {
+    union {
+        struct {
+            uint32_t rdwr_byte                     :    32;  /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set  then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
+        };
+        uint32_t val;
+    } ep1;
+    union {
+        struct {
+            uint32_t wr_done                       :    1;  /*Set this bit to indicate writing byte data to UART Tx FIFO is done.  This bit then stays 0 until data in UART Tx FIFO is read by the USB Host.*/
+            uint32_t serial_in_ep_data_free        :    1;  /*1'b1: Indicate UART Tx FIFO is not full and data can be written into in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the data is sent to the USB Host.*/
+            uint32_t serial_out_ep_data_avail      :    1;  /*1'b1: Indicate there is data in UART Rx FIFO.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } ep1_conf;
+    union {
+        struct {
+            uint32_t jtag_in_flush_int_raw         :    1;  /*The raw interrupt bit turns to high level when a flush command is received for IN endpoint 2 of JTAG.*/
+            uint32_t sof_int_raw                   :    1;  /*The raw interrupt bit turns to high level when a SOF frame is received.*/
+            uint32_t serial_out_recv_pkt_int_raw   :    1;  /*The raw interrupt bit turns to high level when the Serial Port OUT Endpoint received one packet.*/
+            uint32_t serial_in_empty_int_raw       :    1;  /*The raw interrupt bit turns to high level when the Serial Port IN Endpoint is empty.*/
+            uint32_t pid_err_int_raw               :    1;  /*The raw interrupt bit turns to high level when a PID error is detected.*/
+            uint32_t crc5_err_int_raw              :    1;  /*The raw interrupt bit turns to high level when a CRC5 error is detected.*/
+            uint32_t crc16_err_int_raw             :    1;  /*The raw interrupt bit turns to high level when a CRC16 error is detected.*/
+            uint32_t stuff_err_int_raw             :    1;  /*The raw interrupt bit turns to high level when a bit stuffing error is detected.*/
+            uint32_t in_token_rec_in_ep1_int_raw   :    1;  /*The raw interrupt bit turns to high level when an IN token for IN endpoint 1 is received.*/
+            uint32_t usb_bus_reset_int_raw         :    1;  /*The raw interrupt bit turns to high level when a USB bus reset is detected.*/
+            uint32_t out_ep1_zero_payload_int_raw  :    1;  /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero payload.*/
+            uint32_t out_ep2_zero_payload_int_raw  :    1;  /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero payload.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t jtag_in_flush_int_st          :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
+            uint32_t sof_int_st                    :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
+            uint32_t serial_out_recv_pkt_int_st    :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
+            uint32_t serial_in_empty_int_st        :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
+            uint32_t pid_err_int_st                :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
+            uint32_t crc5_err_int_st               :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
+            uint32_t crc16_err_int_st              :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
+            uint32_t stuff_err_int_st              :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
+            uint32_t in_token_rec_in_ep1_int_st    :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
+            uint32_t usb_bus_reset_int_st          :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
+            uint32_t out_ep1_zero_payload_int_st   :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t out_ep2_zero_payload_int_st   :    1;  /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t jtag_in_flush_int_ena         :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
+            uint32_t sof_int_ena                   :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
+            uint32_t serial_out_recv_pkt_int_ena   :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
+            uint32_t serial_in_empty_int_ena       :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
+            uint32_t pid_err_int_ena               :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
+            uint32_t crc5_err_int_ena              :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
+            uint32_t crc16_err_int_ena             :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
+            uint32_t stuff_err_int_ena             :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
+            uint32_t in_token_rec_in_ep1_int_ena   :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
+            uint32_t usb_bus_reset_int_ena         :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
+            uint32_t out_ep1_zero_payload_int_ena  :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t out_ep2_zero_payload_int_ena  :    1;  /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t jtag_in_flush_int_clr         :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
+            uint32_t sof_int_clr                   :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.*/
+            uint32_t serial_out_recv_pkt_int_clr   :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
+            uint32_t serial_in_empty_int_clr       :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
+            uint32_t pid_err_int_clr               :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
+            uint32_t crc5_err_int_clr              :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
+            uint32_t crc16_err_int_clr             :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
+            uint32_t stuff_err_int_clr             :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
+            uint32_t in_token_rec_in_ep1_int_clr   :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.*/
+            uint32_t usb_bus_reset_int_clr         :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
+            uint32_t out_ep1_zero_payload_int_clr  :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t out_ep2_zero_payload_int_clr  :    1;  /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t phy_sel                       :    1;  /*Select internal/external PHY. 1’b0: internal PHY, 1’b1: external PHY*/
+            uint32_t exchg_pins_override           :    1;  /*Enable software control USB D+ D- exchange*/
+            uint32_t exchg_pins                    :    1;  /*USB D+ D- exchange*/
+            uint32_t vrefh                         :    2;  /*Control single-end input high threshold. 1.76V to 2V, step 80mV */
+            uint32_t vrefl                         :    2;  /*Control single-end input low threshold. 0.8V to 1.04V, step 80mV*/
+            uint32_t vref_override                 :    1;  /*Enable software control input  threshold*/
+            uint32_t pad_pull_override             :    1;  /*Enable software control USB D+ D- pullup pulldown*/
+            uint32_t dp_pullup                     :    1;  /*Control USB D+ pull up.*/
+            uint32_t dp_pulldown                   :    1;  /*Control USB D+ pull down.*/
+            uint32_t dm_pullup                     :    1;  /*Control USB D- pull up.*/
+            uint32_t dm_pulldown                   :    1;  /*Control USB D- pull down.*/
+            uint32_t pullup_value                  :    1;  /*Control pull up value.*/
+            uint32_t usb_pad_enable                :    1;  /*Enable USB pad function.*/
+            uint32_t reserved15                    :    17;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t test_enable                   :    1;  /*Enable test of the USB pad*/
+            uint32_t test_usb_oe                   :    1;  /*USB pad oen in test*/
+            uint32_t test_tx_dp                    :    1;  /*USB D+ tx value in test*/
+            uint32_t test_tx_dm                    :    1;  /*USB D- tx value in test*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } test;
+    union {
+        struct {
+            uint32_t in_fifo_cnt                   :    2;  /*JTAG in fifo counter.*/
+            uint32_t in_fifo_empty                 :    1;  /*1: JTAG in fifo is empty.*/
+            uint32_t in_fifo_full                  :    1;  /*1: JTAG in fifo is full.*/
+            uint32_t out_fifo_cnt                  :    2;  /*JTAT out fifo counter.*/
+            uint32_t out_fifo_empty                :    1;  /*1: JTAG out fifo is empty.*/
+            uint32_t out_fifo_full                 :    1;  /*1: JTAG out fifo is full.*/
+            uint32_t in_fifo_reset                 :    1;  /*Write 1 to reset JTAG in fifo.*/
+            uint32_t out_fifo_reset                :    1;  /*Write 1 to reset JTAG out fifo.*/
+            uint32_t reserved10                    :    22;
+        };
+        uint32_t val;
+    } jfifo_st;
+    union {
+        struct {
+            uint32_t sof_frame_index               :    11;  /*Frame index of received SOF frame.*/
+            uint32_t reserved11                    :    21;
+        };
+        uint32_t val;
+    } fram_num;
+    union {
+        struct {
+            uint32_t in_ep0_state                  :    2;  /*State of IN Endpoint 0.*/
+            uint32_t in_ep0_wr_addr                :    7;  /*Write data address of IN endpoint 0.*/
+            uint32_t in_ep0_rd_addr                :    7;  /*Read data address of IN endpoint 0.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } in_ep0_st;
+    union {
+        struct {
+            uint32_t in_ep1_state                  :    2;  /*State of IN Endpoint 1.*/
+            uint32_t in_ep1_wr_addr                :    7;  /*Write data address of IN endpoint 1.*/
+            uint32_t in_ep1_rd_addr                :    7;  /*Read data address of IN endpoint 1.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } in_ep1_st;
+    union {
+        struct {
+            uint32_t in_ep2_state                  :    2;  /*State of IN Endpoint 2.*/
+            uint32_t in_ep2_wr_addr                :    7;  /*Write data address of IN endpoint 2.*/
+            uint32_t in_ep2_rd_addr                :    7;  /*Read data address of IN endpoint 2.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } in_ep2_st;
+    union {
+        struct {
+            uint32_t in_ep3_state                  :    2;  /*State of IN Endpoint 3.*/
+            uint32_t in_ep3_wr_addr                :    7;  /*Write data address of IN endpoint 3.*/
+            uint32_t in_ep3_rd_addr                :    7;  /*Read data address of IN endpoint 3.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } in_ep3_st;
+    union {
+        struct {
+            uint32_t out_ep0_state                 :    2;  /*State of OUT Endpoint 0.*/
+            uint32_t out_ep0_wr_addr               :    7;  /*Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */
+            uint32_t out_ep0_rd_addr               :    7;  /*Read data address of OUT endpoint 0.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } out_ep0_st;
+    union {
+        struct {
+            uint32_t out_ep1_state                 :    2;  /*State of OUT Endpoint 1.*/
+            uint32_t out_ep1_wr_addr               :    7;  /*Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
+            uint32_t out_ep1_rd_addr               :    7;  /*Read data address of OUT endpoint 1.*/
+            uint32_t out_ep1_rec_data_cnt          :    7;  /*Data count in OUT endpoint 1 when one packet is received.*/
+            uint32_t reserved23                    :    9;  /*reserved*/
+        };
+        uint32_t val;
+    } out_ep1_st;
+    union {
+        struct {
+            uint32_t out_ep2_state                 :    2;  /*State of OUT Endpoint 2.*/
+            uint32_t out_ep2_wr_addr               :    7;  /*Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected.  there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
+            uint32_t out_ep2_rd_addr               :    7;  /*Read data address of OUT endpoint 2.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } out_ep2_st;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } misc_conf;
+    union {
+        struct {
+            uint32_t usb_mem_pd                    :    1;  /*1: power down usb memory.*/
+            uint32_t usb_mem_clk_en                :    1;  /*1: Force clock on for usb memory.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } mem_conf;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t date;
+} usb_serial_jtag_dev_t;
+extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */
diff --git a/components/soc/esp32c3/register/soc/xts_aes_reg.h b/components/soc/esp32c3/register/soc/xts_aes_reg.h
new file mode 100644
index 00000000000..6a6e64539c5
--- /dev/null
+++ b/components/soc/esp32c3/register/soc/xts_aes_reg.h
@@ -0,0 +1,135 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** XTS_AES_PLAIN_MEM register
+ *  The memory that stores plaintext
+ */
+#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
+#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
+
+/** XTS_AES_LINESIZE_REG register
+ *  XTS-AES line-size register
+ */
+#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
+/** XTS_AES_LINESIZE : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
+ */
+#define XTS_AES_LINESIZE    (BIT(0))
+#define XTS_AES_LINESIZE_M  (XTS_AES_LINESIZE_V << XTS_AES_LINESIZE_S)
+#define XTS_AES_LINESIZE_V  0x00000001U
+#define XTS_AES_LINESIZE_S  0
+
+/** XTS_AES_DESTINATION_REG register
+ *  XTS-AES destination register
+ */
+#define XTS_AES_DESTINATION_REG (DR_REG_XTS_AES_BASE + 0x44)
+/** XTS_AES_DESTINATION : R/W; bitpos: [0]; default: 0;
+ *  This bit stores the destination. 0: flash(default). 1: reserved.
+ */
+#define XTS_AES_DESTINATION    (BIT(0))
+#define XTS_AES_DESTINATION_M  (XTS_AES_DESTINATION_V << XTS_AES_DESTINATION_S)
+#define XTS_AES_DESTINATION_V  0x00000001U
+#define XTS_AES_DESTINATION_S  0
+
+/** XTS_AES_PHYSICAL_ADDRESS_REG register
+ *  XTS-AES physical address register
+ */
+#define XTS_AES_PHYSICAL_ADDRESS_REG (DR_REG_XTS_AES_BASE + 0x48)
+/** XTS_AES_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0;
+ *  Those bits stores the physical address. If linesize is 16-byte, the physical
+ *  address should be aligned of 16 bytes. If linesize is 32-byte, the physical address
+ *  should be aligned of 32 bytes.
+ */
+#define XTS_AES_PHYSICAL_ADDRESS    0x3FFFFFFFU
+#define XTS_AES_PHYSICAL_ADDRESS_M  (XTS_AES_PHYSICAL_ADDRESS_V << XTS_AES_PHYSICAL_ADDRESS_S)
+#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFFFU
+#define XTS_AES_PHYSICAL_ADDRESS_S  0
+
+/** XTS_AES_TRIGGER_REG register
+ *  XTS-AES trigger register
+ */
+#define XTS_AES_TRIGGER_REG (DR_REG_XTS_AES_BASE + 0x4c)
+/** XTS_AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Set this bit to start manual encryption calculation
+ */
+#define XTS_AES_TRIGGER    (BIT(0))
+#define XTS_AES_TRIGGER_M  (XTS_AES_TRIGGER_V << XTS_AES_TRIGGER_S)
+#define XTS_AES_TRIGGER_V  0x00000001U
+#define XTS_AES_TRIGGER_S  0
+
+/** XTS_AES_RELEASE_REG register
+ *  XTS-AES release register
+ */
+#define XTS_AES_RELEASE_REG (DR_REG_XTS_AES_BASE + 0x50)
+/** XTS_AES_RELEASE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to release the manual encrypted result, after that the result will be
+ *  visible to spi
+ */
+#define XTS_AES_RELEASE    (BIT(0))
+#define XTS_AES_RELEASE_M  (XTS_AES_RELEASE_V << XTS_AES_RELEASE_S)
+#define XTS_AES_RELEASE_V  0x00000001U
+#define XTS_AES_RELEASE_S  0
+
+/** XTS_AES_DESTROY_REG register
+ *  XTS-AES destroy register
+ */
+#define XTS_AES_DESTROY_REG (DR_REG_XTS_AES_BASE + 0x54)
+/** XTS_AES_DESTROY : WT; bitpos: [0]; default: 0;
+ *  Set this bit to destroy XTS-AES result.
+ */
+#define XTS_AES_DESTROY    (BIT(0))
+#define XTS_AES_DESTROY_M  (XTS_AES_DESTROY_V << XTS_AES_DESTROY_S)
+#define XTS_AES_DESTROY_V  0x00000001U
+#define XTS_AES_DESTROY_S  0
+
+/** XTS_AES_STATE_REG register
+ *  XTS-AES status register
+ */
+#define XTS_AES_STATE_REG (DR_REG_XTS_AES_BASE + 0x58)
+/** XTS_AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that
+ *  XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means
+ *  the encrypted result is generated but not visible to mspi. USE means that the
+ *  encrypted result is visible to mspi.
+ */
+#define XTS_AES_STATE    0x00000003U
+#define XTS_AES_STATE_M  (XTS_AES_STATE_V << XTS_AES_STATE_S)
+#define XTS_AES_STATE_V  0x00000003U
+#define XTS_AES_STATE_S  0
+
+/** XTS_AES_DATE_REG register
+ *  XTS-AES version control register
+ */
+#define XTS_AES_DATE_REG (DR_REG_XTS_AES_BASE + 0x5c)
+/** XTS_AES_DATE : R/W; bitpos: [29:0]; default: 538969635;
+ *  Those bits stores the version information of XTS-AES.
+ */
+#define XTS_AES_DATE    0x3FFFFFFFU
+#define XTS_AES_DATE_M  (XTS_AES_DATE_V << XTS_AES_DATE_S)
+#define XTS_AES_DATE_V  0x3FFFFFFFU
+#define XTS_AES_DATE_S  0
+
+/* For backward compatibility with the older register names */
+#define AES_XTS_PLAIN_BASE          XTS_AES_PLAIN_MEM
+#define AES_XTS_SIZE_REG            XTS_AES_LINESIZE_REG
+#define AES_XTS_DESTINATION_REG     XTS_AES_DESTINATION_REG
+#define AES_XTS_PHYSICAL_ADDR_REG   XTS_AES_PHYSICAL_ADDRESS_REG
+#define AES_XTS_TRIGGER_REG         XTS_AES_TRIGGER_REG
+#define AES_XTS_RELEASE_REG         XTS_AES_RELEASE_REG
+#define AES_XTS_DESTROY_REG         XTS_AES_DESTROY_REG
+#define AES_XTS_STATE_REG           XTS_AES_STATE_REG
+#define AES_XTS_DATE_REG            XTS_AES_DATE_REG
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c3/spi_periph.c b/components/soc/esp32c3/spi_periph.c
index 5ae7aed529f..b270a925236 100644
--- a/components/soc/esp32c3/spi_periph.c
+++ b/components/soc/esp32c3/spi_periph.c
@@ -33,7 +33,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = -1,
         .irq = -1,
         .irq_dma = -1,
-        .module = -1,
         .hw = NULL,
         .func = -1,
     }, {
@@ -57,7 +56,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
         .irq = ETS_SPI2_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_SPI2_MODULE,
         .hw = &GPSPI2,
         .func = SPI2_FUNC_NUM,
     }
diff --git a/components/soc/esp32c5/etm_periph.c b/components/soc/esp32c5/etm_periph.c
new file mode 100644
index 00000000000..7b268c443a5
--- /dev/null
+++ b/components/soc/esp32c5/etm_periph.c
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/etm_periph.h"
+#include "soc/soc_etm_reg.h"
+
+/**
+ * ETM Registers to be saved during sleep retention
+ * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
+*/
+#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
+
+static const regdma_entries_config_t etm_regdma_entries[] = {
+    // backup stage: save the status of enabled channels
+    // restore stage: store the enabled channels
+    [0] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
+        SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    [1] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
+        SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
+        SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+};
+
+const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = {
+    [0] = {
+        .module = SLEEP_RETENTION_MODULE_ETM0,
+        .regdma_entry_array = etm_regdma_entries,
+        .array_size = ARRAY_SIZE(etm_regdma_entries)
+    },
+};
diff --git a/components/soc/esp32c5/i2c_periph.c b/components/soc/esp32c5/i2c_periph.c
index 5cc53907f94..bd702887f88 100644
--- a/components/soc/esp32c5/i2c_periph.c
+++ b/components/soc/esp32c5/i2c_periph.c
@@ -40,3 +40,32 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
         .irq = ETS_LP_I2C_INTR_SOURCE,
     },
 };
+
+// I2C sleep retention entries
+// I2C registers require set the reg_update bit to make the configuration take effect
+
+/* I2C Registers Context
+   Include: I2C_SCL_LOW_PERIOD_REG /
+            I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
+            I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
+            I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
+*/
+#define I2C0_RETENTION_REGS_CNT  18
+#define I2C0_RETENTION_MAP_BASE  I2C_SCL_LOW_PERIOD_REG(0)
+static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
+static const regdma_entries_config_t i2c0_regs_retention[] = {
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+};
+
+const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
+    {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
+};
diff --git a/components/soc/esp32c5/i2s_periph.c b/components/soc/esp32c5/i2s_periph.c
index 619da2ca46e..9866cc97892 100644
--- a/components/soc/esp32c5/i2s_periph.c
+++ b/components/soc/esp32c5/i2s_periph.c
@@ -30,7 +30,7 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
         .data_out_sigs[1] = I2SO_SD1_OUT_IDX,
         .data_in_sig  = I2SI_SD_IN_IDX,
 
-        .irq          = ETS_I2S1_INTR_SOURCE,
+        .irq          = ETS_I2S0_INTR_SOURCE,
     }
 };
 
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index 8943b4f2795..b5f1a63bff9 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -463,6 +463,10 @@ config SOC_ETM_CHANNELS_PER_GROUP
     int
     default 50
 
+config SOC_ETM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_GPIO_PORT
     int
     default 1
@@ -615,6 +619,10 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_LP_I2C_NUM
     int
     default 1
@@ -687,6 +695,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6
@@ -711,6 +723,10 @@ config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
     int
     default 10
 
+config SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MMU_PERIPH_NUM
     int
     default 1
@@ -751,6 +767,10 @@ config SOC_PCNT_SUPPORT_STEP_NOTIFY
     bool
     default y
 
+config SOC_PCNT_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_RMT_GROUPS
     int
     default 1
@@ -867,6 +887,10 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
     bool
     default y
 
+config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_PARLIO_GROUPS
     int
     default 1
@@ -907,6 +931,10 @@ config SOC_PARLIO_TX_SIZE_BY_DMA
     bool
     default y
 
+config SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MPI_MEM_BLOCKS_NUM
     int
     default 4
@@ -1003,6 +1031,10 @@ config SOC_SPI_SUPPORT_SLAVE_HD_VER2
     bool
     default y
 
+config SOC_SPI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_SPI_SUPPORT_CLK_XTAL
     bool
     default y
@@ -1155,6 +1187,14 @@ config SOC_EFUSE_ECDSA_KEY
     bool
     default y
 
+config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
+    bool
+    default y
+
+config SOC_KEY_MANAGER_FE_KEY_DEPLOY
+    bool
+    default y
+
 config SOC_SECURE_BOOT_V2_ECC
     bool
     default y
@@ -1339,10 +1379,6 @@ config SOC_PM_MODEM_RETENTION_BY_REGDMA
     bool
     default y
 
-config SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
-    bool
-    default y
-
 config SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN
     bool
     default y
@@ -1383,10 +1419,18 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    bool
+    default y
+
 config SOC_RCC_IS_INDEPENDENT
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y
@@ -1399,6 +1443,14 @@ config SOC_TEMPERATURE_SENSOR_INTR_SUPPORT
     bool
     default y
 
+config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
+config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN
+    bool
+    default y
+
 config SOC_WIFI_HW_TSF
     bool
     default y
diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h
index b1955e22253..2f7d2e97176 100644
--- a/components/soc/esp32c5/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h
@@ -92,9 +92,10 @@ typedef enum {
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1,      /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
     SOC_RTC_FAST_CLK_SRC_XTAL = 2,         /*!< Select XTAL_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
 } soc_rtc_fast_clk_src_t;
 
 /**
diff --git a/components/soc/esp32c5/include/soc/efuse_reg.h b/components/soc/esp32c5/include/soc/efuse_reg.h
deleted file mode 100644
index 1da0dd667ed..00000000000
--- a/components/soc/esp32c5/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,4263 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Represents pgm_data0
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Represents pgm_data1
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Represents pgm_data2
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Represents pgm_data3
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 3th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Represents pgm_data4
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Represents pgm_data5
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Represents pgm_data6
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Represents pgm_data7
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Represents pgm_check_value0
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Represents pgm_check_value1
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1th RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Represents pgm_check_value2
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2th RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS0_REG register
- *  Represents rd_wr_dis
- */
-#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Represents whether programming of individual eFuse memory bit is disabled or
- *  enabled.\\ 1: Disabled\\ 0: Enabled\\
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
- *  enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_RD_RESERVE_0_39 : RW; bitpos: [7]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_39    (BIT(7))
-#define EFUSE_RD_RESERVE_0_39_M  (EFUSE_RD_RESERVE_0_39_V << EFUSE_RD_RESERVE_0_39_S)
-#define EFUSE_RD_RESERVE_0_39_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_39_S  7
-/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
- *  Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_ICACHE    (BIT(8))
-#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
-#define EFUSE_DIS_ICACHE_V  0x00000001U
-#define EFUSE_DIS_ICACHE_S  8
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
- *  Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
- *  disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  9
-/** EFUSE_RD_RESERVE_0_42 : RW; bitpos: [10]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_42    (BIT(10))
-#define EFUSE_RD_RESERVE_0_42_M  (EFUSE_RD_RESERVE_0_42_V << EFUSE_RD_RESERVE_0_42_S)
-#define EFUSE_RD_RESERVE_0_42_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_42_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
- *  Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
- *  enabled\\
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Represents whether the function that forces chip into download mode is disabled or
- *  enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
- *  Represents whether SPI0 controller during boot_mode_download is disabled or
- *  enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
-/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0:
- *  enabled\\
- */
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
-#define EFUSE_DIS_TWAI_V  0x00000001U
-#define EFUSE_DIS_TWAI_S  14
-/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- *  is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
- */
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
-#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_S  15
-/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even
- *  number: enabled\\
- */
-#define EFUSE_SOFT_DIS_JTAG    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
-#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
- *  0: enabled\\
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
- *  mode).\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFH    0x00000003U
-#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
-#define EFUSE_USB_DREFH_V  0x00000003U
-#define EFUSE_USB_DREFH_S  21
-/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFL    0x00000003U
-#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
-#define EFUSE_USB_DREFL_V  0x00000003U
-#define EFUSE_USB_DREFL_S  23
-/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
- *  Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not
- *  exchanged\\
- */
-#define EFUSE_USB_EXCHG_PINS    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
-#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_S  25
-/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
- *  Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not
- *  functioned\\
- */
-#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
-#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_S  26
-/** EFUSE_RD_RESERVE_0_59 : RW; bitpos: [31:27]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_59    0x0000001FU
-#define EFUSE_RD_RESERVE_0_59_M  (EFUSE_RD_RESERVE_0_59_V << EFUSE_RD_RESERVE_0_59_S)
-#define EFUSE_RD_RESERVE_0_59_V  0x0000001FU
-#define EFUSE_RD_RESERVE_0_59_S  27
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [3:0]; default: 0;
- *  Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled
- *  \\ 0: enabled.\\
- */
-#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0;
- *  Set the bits to control key manager random number switch cycle. 0: control by
- *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_S  4
-/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0;
- *  Set each bit to control whether corresponding key can only be deployed once. 1 is
- *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
- */
-#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  6
-/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0;
- *  Set each bit to control whether corresponding key must come from key manager. 1 is
- *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
- */
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  10
-/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0;
- *  Set this bit to disable software written init key, and force use efuse_init_key.
- */
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(14))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  14
-/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_79    (BIT(15))
-#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
-#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_79_S  15
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original
- *  threshold configuration value of STG0 *2 \\1: Original threshold configuration
- *  value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3:
- *  Original threshold configuration value of STG0 *16 \\
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
- *  1: enabled\\ Even number of 1: disabled\\
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
- *  enabled\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
- *  enabled\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
- *  enabled\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Represents the purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  24
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Represents the purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Represents the purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  0
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Represents the purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  4
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Represents the purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  8
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Represents the purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  12
-/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the spa secure level by configuring the clock random divide mode.
- */
-#define EFUSE_SEC_DPA_LEVEL    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
-#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_S  16
-/** EFUSE_RD_RESERVE_0_114 : RW; bitpos: [19:18]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_114    0x00000003U
-#define EFUSE_RD_RESERVE_0_114_M  (EFUSE_RD_RESERVE_0_114_V << EFUSE_RD_RESERVE_0_114_S)
-#define EFUSE_RD_RESERVE_0_114_V  0x00000003U
-#define EFUSE_RD_RESERVE_0_114_S  18
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
- *  enabled.\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [26:22]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_118    0x0000001FU
-#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
-#define EFUSE_RD_RESERVE_0_118_V  0x0000001FU
-#define EFUSE_RD_RESERVE_0_118_S  22
-/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [27]; default: 0;
- *  Set this bitto configure flash encryption use xts-128 key. else use xts-256 key.
- */
-#define EFUSE_KM_XTS_KEY_LENGTH_256    (BIT(27))
-#define EFUSE_KM_XTS_KEY_LENGTH_256_M  (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S)
-#define EFUSE_KM_XTS_KEY_LENGTH_256_V  0x00000001U
-#define EFUSE_KM_XTS_KEY_LENGTH_256_S  27
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Represents the flash waiting time after power-up, in unit of ms. When the value
- *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
- *  is 2 times the programmed value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0:
- *  enabled\\
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0:
- *  enabled\\
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1:
- *  disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
- *  Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\
- */
-#define EFUSE_LOCK_KM_KEY    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
-#define EFUSE_LOCK_KM_KEY_V  0x00000001U
-#define EFUSE_LOCK_KM_KEY_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
- *  1: Disable\\ 0: Enable\\
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0:
- *  disabled\\
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable
- *  printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset
- *  at high level\\ 11: force disable printing\\
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
- *  Represents whether ROM code is forced to send a resume command during SPI boot.\\
- *  1: forced\\ 0:not forced\\
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  8
-/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
- *  Represents the version used by ESP-IDF anti-rollback feature.
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
- *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
- *  enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
-/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
- *  Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
- *  enabled\\ 0:disabled\\
- */
-#define EFUSE_HYS_EN_PAD    (BIT(26))
-#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
-#define EFUSE_HYS_EN_PAD_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_S  26
-/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0;
- *  Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2:
- *  Moderate 1. Low\\ 0: Disabled\\
- */
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL    0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S)
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V  0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S  27
-/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0;
- *  Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0:
- *  Disable.\\
- */
-#define EFUSE_XTS_DPA_CLK_ENABLE    (BIT(29))
-#define EFUSE_XTS_DPA_CLK_ENABLE_M  (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S)
-#define EFUSE_XTS_DPA_CLK_ENABLE_V  0x00000001U
-#define EFUSE_XTS_DPA_CLK_ENABLE_S  29
-/** EFUSE_RD_RESERVE_0_158 : RW; bitpos: [31:30]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_158    0x00000003U
-#define EFUSE_RD_RESERVE_0_158_M  (EFUSE_RD_RESERVE_0_158_V << EFUSE_RD_RESERVE_0_158_S)
-#define EFUSE_RD_RESERVE_0_158_V  0x00000003U
-#define EFUSE_RD_RESERVE_0_158_S  30
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_HUK_GEN_STATE : RO; bitpos: [8:0]; default: 0;
- *  Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\
- *  Even of 1 is valid.\\
- */
-#define EFUSE_HUK_GEN_STATE    0x000001FFU
-#define EFUSE_HUK_GEN_STATE_M  (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S)
-#define EFUSE_HUK_GEN_STATE_V  0x000001FFU
-#define EFUSE_HUK_GEN_STATE_S  0
-/** EFUSE_XTAL_48M_SEL : RO; bitpos: [11:9]; default: 0;
- *  Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used.
- *  If this field contains Odd number bit '1': Enable 48MHz XTAL\\ Even number bit '1':
- *  Enable 40MHz XTAL.
- */
-#define EFUSE_XTAL_48M_SEL    0x00000007U
-#define EFUSE_XTAL_48M_SEL_M  (EFUSE_XTAL_48M_SEL_V << EFUSE_XTAL_48M_SEL_S)
-#define EFUSE_XTAL_48M_SEL_V  0x00000007U
-#define EFUSE_XTAL_48M_SEL_S  9
-/** EFUSE_XTAL_48M_SEL_MODE : RO; bitpos: [12]; default: 0;
- *  Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1:
- *  eFuse\\ 0: strapping-PAD-state.
- */
-#define EFUSE_XTAL_48M_SEL_MODE    (BIT(12))
-#define EFUSE_XTAL_48M_SEL_MODE_M  (EFUSE_XTAL_48M_SEL_MODE_V << EFUSE_XTAL_48M_SEL_MODE_S)
-#define EFUSE_XTAL_48M_SEL_MODE_V  0x00000001U
-#define EFUSE_XTAL_48M_SEL_MODE_S  12
-/** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [13]; default: 0;
- *  Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable.
- */
-#define EFUSE_ECDSA_DISABLE_P192    (BIT(13))
-#define EFUSE_ECDSA_DISABLE_P192_M  (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S)
-#define EFUSE_ECDSA_DISABLE_P192_V  0x00000001U
-#define EFUSE_ECDSA_DISABLE_P192_S  13
-/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [14]; default: 0;
- *  Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
- *  \\ 0: Disable.
- */
-#define EFUSE_ECC_FORCE_CONST_TIME    (BIT(14))
-#define EFUSE_ECC_FORCE_CONST_TIME_M  (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S)
-#define EFUSE_ECC_FORCE_CONST_TIME_V  0x00000001U
-#define EFUSE_ECC_FORCE_CONST_TIME_S  14
-/** EFUSE_RD_RESERVE_0_175 : RW; bitpos: [31:15]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_175    0x0001FFFFU
-#define EFUSE_RD_RESERVE_0_175_M  (EFUSE_RD_RESERVE_0_175_V << EFUSE_RD_RESERVE_0_175_S)
-#define EFUSE_RD_RESERVE_0_175_V  0x0001FFFFU
-#define EFUSE_RD_RESERVE_0_175_S  15
-
-/** EFUSE_RD_MAC_SYS0_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents MAC address. Low 32-bit.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SYS1_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Represents MAC address. High 16-bit.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
- *  Represents the extended bits of MAC address.
- */
-#define EFUSE_MAC_EXT    0x0000FFFFU
-#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
-#define EFUSE_MAC_EXT_V  0x0000FFFFU
-#define EFUSE_MAC_EXT_S  16
-
-/** EFUSE_RD_MAC_SYS2_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c)
-/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
- *  Minor chip version
- */
-#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
-#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_S  0
-/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
- *  Minor chip version
- */
-#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_S  4
-/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
- *  Disables check of wafer version major
- */
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(6))
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  6
-/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
- *  Disables check of blk version major
- */
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
-/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
- *  BLK_VERSION_MINOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MINOR    0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
-#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_S  8
-/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
- *  BLK_VERSION_MAJOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
-#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_S  11
-/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
- *  Flash capacity
- */
-#define EFUSE_FLASH_CAP    0x00000007U
-#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
-#define EFUSE_FLASH_CAP_V  0x00000007U
-#define EFUSE_FLASH_CAP_S  13
-/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0;
- *  Flash vendor
- */
-#define EFUSE_FLASH_VENDOR    0x00000007U
-#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
-#define EFUSE_FLASH_VENDOR_V  0x00000007U
-#define EFUSE_FLASH_VENDOR_S  16
-/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0;
- *  Psram capacity
- */
-#define EFUSE_PSRAM_CAP    0x00000007U
-#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
-#define EFUSE_PSRAM_CAP_V  0x00000007U
-#define EFUSE_PSRAM_CAP_S  19
-/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0;
- *  Psram vendor
- */
-#define EFUSE_PSRAM_VENDOR    0x00000003U
-#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
-#define EFUSE_PSRAM_VENDOR_V  0x00000003U
-#define EFUSE_PSRAM_VENDOR_S  22
-/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0;
- *  Temp (die embedded inside)
- */
-#define EFUSE_TEMP    0x00000003U
-#define EFUSE_TEMP_M  (EFUSE_TEMP_V << EFUSE_TEMP_S)
-#define EFUSE_TEMP_V  0x00000003U
-#define EFUSE_TEMP_S  24
-/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0;
- *  Package version
- */
-#define EFUSE_PKG_VERSION    0x00000007U
-#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
-#define EFUSE_PKG_VERSION_V  0x00000007U
-#define EFUSE_PKG_VERSION_S  26
-/** EFUSE_PA_TRIM_VERSION : R; bitpos: [31:29]; default: 0;
- *  PADC CAL PA trim version
- */
-#define EFUSE_PA_TRIM_VERSION    0x00000007U
-#define EFUSE_PA_TRIM_VERSION_M  (EFUSE_PA_TRIM_VERSION_V << EFUSE_PA_TRIM_VERSION_S)
-#define EFUSE_PA_TRIM_VERSION_V  0x00000007U
-#define EFUSE_PA_TRIM_VERSION_S  29
-
-/** EFUSE_RD_MAC_SYS3_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0;
- *  PADC CAL N bias
- */
-#define EFUSE_TRIM_N_BIAS    0x0000001FU
-#define EFUSE_TRIM_N_BIAS_M  (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S)
-#define EFUSE_TRIM_N_BIAS_V  0x0000001FU
-#define EFUSE_TRIM_N_BIAS_S  0
-/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0;
- *  PADC CAL P bias
- */
-#define EFUSE_TRIM_P_BIAS    0x0000001FU
-#define EFUSE_TRIM_P_BIAS_M  (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S)
-#define EFUSE_TRIM_P_BIAS_V  0x0000001FU
-#define EFUSE_TRIM_P_BIAS_S  5
-/** EFUSE_RESERVED_1_106 : R; bitpos: [17:10]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_106    0x000000FFU
-#define EFUSE_RESERVED_1_106_M  (EFUSE_RESERVED_1_106_V << EFUSE_RESERVED_1_106_S)
-#define EFUSE_RESERVED_1_106_V  0x000000FFU
-#define EFUSE_RESERVED_1_106_S  10
-/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
- *  Represents the first 14-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
-#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_S  18
-
-/** EFUSE_RD_MAC_SYS4_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the first 14-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
-#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_S  0
-
-/** EFUSE_RD_MAC_SYS5_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the second 32-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
-#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Represents rd_sys_part1_data0
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Represents rd_sys_part1_data1
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Represents rd_sys_part1_data2
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Represents rd_sys_part1_data3
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Represents rd_sys_part1_data4
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_RESERVED_2_128 : R; bitpos: [8:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_128    0x000001FFU
-#define EFUSE_RESERVED_2_128_M  (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
-#define EFUSE_RESERVED_2_128_V  0x000001FFU
-#define EFUSE_RESERVED_2_128_S  0
-/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
- *  ADC OCode
- */
-#define EFUSE_OCODE    0x000000FFU
-#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
-#define EFUSE_OCODE_V  0x000000FFU
-#define EFUSE_OCODE_S  9
-/** EFUSE_RESERVED_2_145 : R; bitpos: [31:17]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_145    0x00007FFFU
-#define EFUSE_RESERVED_2_145_M  (EFUSE_RESERVED_2_145_V << EFUSE_RESERVED_2_145_S)
-#define EFUSE_RESERVED_2_145_V  0x00007FFFU
-#define EFUSE_RESERVED_2_145_S  17
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Represents rd_sys_part1_data5
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
-#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Represents rd_sys_part1_data6
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
-#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Represents rd_sys_part1_data7
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
-#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_S  0
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Represents rd_usr_data0
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Represents rd_usr_data1
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Represents rd_usr_data2
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Represents rd_usr_data3
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Represents rd_usr_data4
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Represents rd_usr_data5
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Represents rd_usr_data6
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_192    0x000000FFU
-#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
-#define EFUSE_RESERVED_3_192_V  0x000000FFU
-#define EFUSE_RESERVED_3_192_S  0
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_S  8
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Represents rd_usr_data7
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_248    0x000000FFU
-#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
-#define EFUSE_RESERVED_3_248_V  0x000000FFU
-#define EFUSE_RESERVED_3_248_S  24
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Represents rd_key0_data0
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Represents rd_key0_data1
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Represents rd_key0_data2
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Represents rd_key0_data3
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Represents rd_key0_data4
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Represents rd_key0_data5
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Represents rd_key0_data6
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Represents rd_key0_data7
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Represents rd_key1_data0
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Represents rd_key1_data1
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Represents rd_key1_data2
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Represents rd_key1_data3
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Represents rd_key1_data4
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Represents rd_key1_data5
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Represents rd_key1_data6
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Represents rd_key1_data7
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Represents rd_key2_data0
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Represents rd_key2_data1
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Represents rd_key2_data2
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Represents rd_key2_data3
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Represents rd_key2_data4
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Represents rd_key2_data5
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Represents rd_key2_data6
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Represents rd_key2_data7
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Represents rd_key3_data0
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Represents rd_key3_data1
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Represents rd_key3_data2
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Represents rd_key3_data3
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Represents rd_key3_data4
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Represents rd_key3_data5
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Represents rd_key3_data6
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Represents rd_key3_data7
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Represents rd_key4_data0
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Represents rd_key4_data1
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Represents rd_key4_data2
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Represents rd_key4_data3
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Represents rd_key4_data4
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Represents rd_key4_data5
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Represents rd_key4_data6
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Represents rd_key4_data7
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Represents rd_key5_data0
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Represents rd_key5_data1
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Represents rd_key5_data2
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Represents rd_key5_data3
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Represents rd_key5_data4
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Represents rd_key5_data5
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Represents rd_key5_data6
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Represents rd_key5_data7
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Represents rd_sys_part2_data0
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Represents rd_sys_part2_data1
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Represents rd_sys_part2_data2
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Represents rd_sys_part2_data3
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Represents rd_sys_part2_data4
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Represents rd_sys_part2_data5
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Represents rd_sys_part2_data6
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Represents rd_sys_part2_data7
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_DATA_ERR0_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  Represents the programming error of EFUSE_RD_DIS
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
- *  Represents the programming error of EFUSE_DIS_ICACHE
- */
-#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
-#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
-#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_ICACHE_ERR_S  8
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_JTAG
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  9
-/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
- *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
-/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
- *  Represents the programming error of EFUSE_DIS_TWAI
- */
-#define EFUSE_DIS_TWAI_ERR    (BIT(14))
-#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
-#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
-#define EFUSE_DIS_TWAI_ERR_S  14
-/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
- *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
- */
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
-/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
- */
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  Represents the programming error of EFUSE_DIS_PAD_JTAG
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
- *  Represents the programming error of EFUSE_USB_DREFH
- */
-#define EFUSE_USB_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
-#define EFUSE_USB_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DREFH_ERR_S  21
-/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
- *  Represents the programming error of EFUSE_USB_DREFL
- */
-#define EFUSE_USB_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
-#define EFUSE_USB_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DREFL_ERR_S  23
-/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
- *  Represents the programming error of EFUSE_USB_EXCHG_PINS
- */
-#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
-#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_ERR_S  25
-/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
- *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
- */
-#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
-
-/** EFUSE_RD_REPEAT_DATA_ERR1_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [3:0]; default: 0;
- *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
- */
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [5:4]; default: 0;
- *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  4
-/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [9:6]; default: 0;
- *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
- */
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  6
-/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [13:10]; default: 0;
- *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
- */
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  10
-/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [14]; default: 0;
- *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
- */
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(14))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  14
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Represents the programming error of EFUSE_WDT_DELAY_SEL
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_0
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_1
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-
-/** EFUSE_RD_REPEAT_DATA_ERR2_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_2
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  0
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_3
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_4
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_5
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
- */
-#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
-#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_EN
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [27]; default: 0;
- *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
- */
-#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR    (BIT(27))
-#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S)
-#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
-#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S  27
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  Represents the programming error of EFUSE_FLASH_TPUW
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_DATA_ERR3_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
- */
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
-/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
- *  Represents the programming error of EFUSE_LOCK_KM_KEY
- */
-#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
-#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
-#define EFUSE_LOCK_KM_KEY_ERR_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
- *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_VERSION
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
-/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
- *  Represents the programming error of EFUSE_HYS_EN_PAD
- */
-#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
-#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
-#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_ERR_S  26
-/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0;
- *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
- */
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR    0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S)
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V  0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S  27
-/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [29]; default: 0;
- *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
- */
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR    (BIT(29))
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M  (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S)
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V  0x00000001U
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S  29
-
-/** EFUSE_RD_REPEAT_DATA_ERR4_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
-/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [8:0]; default: 0;
- *  Represents the programming error of EFUSE_HUK_GEN_STATE
- */
-#define EFUSE_HUK_GEN_STATE_ERR    0x000001FFU
-#define EFUSE_HUK_GEN_STATE_ERR_M  (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S)
-#define EFUSE_HUK_GEN_STATE_ERR_V  0x000001FFU
-#define EFUSE_HUK_GEN_STATE_ERR_S  0
-/** EFUSE_XTAL_48M_SEL_ERR : RO; bitpos: [11:9]; default: 0;
- *  Represents the programming error of EFUSE_XTAL_48M_SEL
- */
-#define EFUSE_XTAL_48M_SEL_ERR    0x00000007U
-#define EFUSE_XTAL_48M_SEL_ERR_M  (EFUSE_XTAL_48M_SEL_ERR_V << EFUSE_XTAL_48M_SEL_ERR_S)
-#define EFUSE_XTAL_48M_SEL_ERR_V  0x00000007U
-#define EFUSE_XTAL_48M_SEL_ERR_S  9
-/** EFUSE_XTAL_48M_SEL_MODE_ERR : RO; bitpos: [12]; default: 0;
- *  Represents the programming error of EFUSE_XTAL_48M_SEL_MODE
- */
-#define EFUSE_XTAL_48M_SEL_MODE_ERR    (BIT(12))
-#define EFUSE_XTAL_48M_SEL_MODE_ERR_M  (EFUSE_XTAL_48M_SEL_MODE_ERR_V << EFUSE_XTAL_48M_SEL_MODE_ERR_S)
-#define EFUSE_XTAL_48M_SEL_MODE_ERR_V  0x00000001U
-#define EFUSE_XTAL_48M_SEL_MODE_ERR_S  12
-/** EFUSE_ECDSA_DISABLE_P192_ERR : RO; bitpos: [13]; default: 0;
- *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
- */
-#define EFUSE_ECDSA_DISABLE_P192_ERR    (BIT(13))
-#define EFUSE_ECDSA_DISABLE_P192_ERR_M  (EFUSE_ECDSA_DISABLE_P192_ERR_V << EFUSE_ECDSA_DISABLE_P192_ERR_S)
-#define EFUSE_ECDSA_DISABLE_P192_ERR_V  0x00000001U
-#define EFUSE_ECDSA_DISABLE_P192_ERR_S  13
-/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [14]; default: 0;
- *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
- */
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR    (BIT(14))
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M  (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S)
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V  0x00000001U
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S  14
-
-/** EFUSE_RD_RS_DATA_ERR0_REG register
- *  Represents rd_rs_data_err
- */
-#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190)
-/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS_ERR_NUM    0x00000007U
-#define EFUSE_RD_MAC_SYS_ERR_NUM_M  (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S)
-#define EFUSE_RD_MAC_SYS_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_MAC_SYS_ERR_NUM_S  0
-/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
- *  of error bytes is over 6.
- */
-#define EFUSE_RD_MAC_SYS_FAIL    (BIT(3))
-#define EFUSE_RD_MAC_SYS_FAIL_M  (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S)
-#define EFUSE_RD_MAC_SYS_FAIL_V  0x00000001U
-#define EFUSE_RD_MAC_SYS_FAIL_S  3
-/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_sys_part1_data
- */
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S)
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S  4
-/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
- *  and the number of error bytes is over 6.
- */
-#define EFUSE_RD_SYS_PART1_DATA_FAIL    (BIT(7))
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_M  (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S)
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_S  7
-/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_usr_data
- */
-#define EFUSE_RD_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_USR_DATA_ERR_NUM_M  (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S)
-#define EFUSE_RD_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_USR_DATA_ERR_NUM_S  8
-/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_RD_USR_DATA_FAIL_M  (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S)
-#define EFUSE_RD_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_USR_DATA_FAIL_S  11
-/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key0_data
- */
-#define EFUSE_RD_KEY0_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_M  (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_S  12
-/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY0_DATA_FAIL    (BIT(15))
-#define EFUSE_RD_KEY0_DATA_FAIL_M  (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S)
-#define EFUSE_RD_KEY0_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY0_DATA_FAIL_S  15
-/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key1_data
- */
-#define EFUSE_RD_KEY1_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_M  (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_S  16
-/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY1_DATA_FAIL    (BIT(19))
-#define EFUSE_RD_KEY1_DATA_FAIL_M  (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S)
-#define EFUSE_RD_KEY1_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY1_DATA_FAIL_S  19
-/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key2_data
- */
-#define EFUSE_RD_KEY2_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_M  (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_S  20
-/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY2_DATA_FAIL    (BIT(23))
-#define EFUSE_RD_KEY2_DATA_FAIL_M  (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S)
-#define EFUSE_RD_KEY2_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY2_DATA_FAIL_S  23
-/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key3_data
- */
-#define EFUSE_RD_KEY3_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_M  (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_S  24
-/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY3_DATA_FAIL    (BIT(27))
-#define EFUSE_RD_KEY3_DATA_FAIL_M  (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S)
-#define EFUSE_RD_KEY3_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY3_DATA_FAIL_S  27
-/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key4_data
- */
-#define EFUSE_RD_KEY4_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_M  (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_S  28
-/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY4_DATA_FAIL    (BIT(31))
-#define EFUSE_RD_KEY4_DATA_FAIL_M  (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S)
-#define EFUSE_RD_KEY4_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY4_DATA_FAIL_S  31
-
-/** EFUSE_RD_RS_DATA_ERR1_REG register
- *  Represents rd_rs_data_err
- */
-#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194)
-/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key5_data
- */
-#define EFUSE_RD_KEY5_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_M  (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_S  0
-/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY5_DATA_FAIL    (BIT(3))
-#define EFUSE_RD_KEY5_DATA_FAIL_M  (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S)
-#define EFUSE_RD_KEY5_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY5_DATA_FAIL_S  3
-/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_sys_part2_data
- */
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S)
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S  4
-/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
- *  and the number of error bytes is over 6.
- */
-#define EFUSE_RD_SYS_PART2_DATA_FAIL    (BIT(7))
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_M  (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S)
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_S  7
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37752960;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
-/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit to force enable eFuse register configuration clock signal.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuration register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A:  programming operation command 0x5AA5: read operation command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
- *  Configures which block to use for ECDSA key output.
- */
-#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
-#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_S  16
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
- *  The value of OTP_LOAD_SW.
- */
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
-#define EFUSE_OTP_LOAD_SW_V  0x00000001U
-#define EFUSE_OTP_LOAD_SW_S  4
-/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
- *  The value of OTP_VDDQ_C_SYNC2.
- */
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
- *  The value of OTP_STROBE_SW.
- */
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
-#define EFUSE_OTP_STROBE_SW_V  0x00000001U
-#define EFUSE_OTP_STROBE_SW_S  6
-/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
- *  The value of OTP_CSB_SW.
- */
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
-#define EFUSE_OTP_CSB_SW_V  0x00000001U
-#define EFUSE_OTP_CSB_SW_S  7
-/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
- *  The value of OTP_PGENB_SW.
- */
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
-#define EFUSE_OTP_PGENB_SW_V  0x00000001U
-#define EFUSE_OTP_PGENB_SW_S  8
-/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
- *  The value of OTP_VDDQ_IS_SW.
- */
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
- *  Indicates the number of block valid bit.
- */
-#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
- *  Indicates which block is used for ECDSA key output.
- */
-#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
-#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_S  20
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
-/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the read hold time.
- */
-#define EFUSE_THR_A    0x000000FFU
-#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
-#define EFUSE_THR_A_V  0x000000FFU
-#define EFUSE_THR_A_S  0
-/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
- *  Configures the read time.
- */
-#define EFUSE_TRD    0x000000FFU
-#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
-#define EFUSE_TRD_V  0x000000FFU
-#define EFUSE_TRD_S  8
-/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
- *  Configures the read setup time.
- */
-#define EFUSE_TSUR_A    0x000000FFU
-#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
-#define EFUSE_TSUR_A_V  0x000000FFU
-#define EFUSE_TSUR_A_S  16
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 22;
- *  Configures the waiting time of reading eFuse memory.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
-/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the programming setup time.
- */
-#define EFUSE_TSUP_A    0x000000FFU
-#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
-#define EFUSE_TSUP_A_V  0x000000FFU
-#define EFUSE_TSUP_A_S  0
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
- *  Configures the programming hold time.
- */
-#define EFUSE_THP_A    0x000000FFU
-#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
-#define EFUSE_THP_A_V  0x000000FFU
-#define EFUSE_THP_A_S  24
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200;
- *  Configures the active programming time.
- */
-#define EFUSE_TPGM    0x0000FFFFU
-#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
-#define EFUSE_TPGM_V  0x0000FFFFU
-#define EFUSE_TPGM_S  16
-
-/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
-/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
- *  Set this bit to bypass reed solomon correction step.
- */
-#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
-#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
-#define EFUSE_BYPASS_RS_CORRECTION_S  0
-/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
- *  Configures block number of programming twice operation.
- */
-#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
-#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_S  1
-/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
- *  Set this bit to update multi-bit register signals.
- */
-#define EFUSE_UPDATE    (BIT(12))
-#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
-#define EFUSE_UPDATE_V  0x00000001U
-#define EFUSE_UPDATE_S  12
-/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
- *  Configures the inactive programming time.
- */
-#define EFUSE_TPGM_INACTIVE    0x000000FFU
-#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
-#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
-#define EFUSE_TPGM_INACTIVE_S  13
-
-/** EFUSE_APB2OTP_WR_DIS_REG register
- *  eFuse apb2otp block0 data register1.
- */
-#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x500)
-/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 write disable data.
- */
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
- *  eFuse apb2otp block0 data register2.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x504)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
- *  eFuse apb2otp block0 data register3.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x508)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
- *  eFuse apb2otp block0 data register4.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x50c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
- *  eFuse apb2otp block0 data register5.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x510)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
- *  eFuse apb2otp block0 data register6.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x514)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
- *  eFuse apb2otp block0 data register7.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x518)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
- *  eFuse apb2otp block0 data register8.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x51c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
- *  eFuse apb2otp block0 data register9.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x520)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
- *  eFuse apb2otp block0 data register10.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x524)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
- *  eFuse apb2otp block0 data register11.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x528)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
- *  eFuse apb2otp block0 data register12.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x52c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
- *  eFuse apb2otp block0 data register13.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x530)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
- *  eFuse apb2otp block0 data register14.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x534)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
- *  eFuse apb2otp block0 data register15.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x538)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
- *  eFuse apb2otp block0 data register16.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x53c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
- *  eFuse apb2otp block0 data register17.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x540)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
- *  eFuse apb2otp block0 data register18.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x544)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
- *  eFuse apb2otp block0 data register19.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x548)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
- *  eFuse apb2otp block0 data register20.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x54c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
- *  eFuse apb2otp block0 data register21.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x550)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
-
-/** EFUSE_APB2OTP_BLK1_W1_REG register
- *  eFuse apb2otp block1 data register1.
- */
-#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x554)
-/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
-#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W1_S  0
-
-/** EFUSE_APB2OTP_BLK1_W2_REG register
- *  eFuse apb2otp block1 data register2.
- */
-#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x558)
-/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
-#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W2_S  0
-
-/** EFUSE_APB2OTP_BLK1_W3_REG register
- *  eFuse apb2otp block1 data register3.
- */
-#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x55c)
-/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
-#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W3_S  0
-
-/** EFUSE_APB2OTP_BLK1_W4_REG register
- *  eFuse apb2otp block1 data register4.
- */
-#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x560)
-/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
-#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W4_S  0
-
-/** EFUSE_APB2OTP_BLK1_W5_REG register
- *  eFuse apb2otp block1 data register5.
- */
-#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x564)
-/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
-#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W5_S  0
-
-/** EFUSE_APB2OTP_BLK1_W6_REG register
- *  eFuse apb2otp block1 data register6.
- */
-#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x568)
-/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
-#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W6_S  0
-
-/** EFUSE_APB2OTP_BLK1_W7_REG register
- *  eFuse apb2otp block1 data register7.
- */
-#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x56c)
-/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
-#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W7_S  0
-
-/** EFUSE_APB2OTP_BLK1_W8_REG register
- *  eFuse apb2otp block1 data register8.
- */
-#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x570)
-/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
-#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W8_S  0
-
-/** EFUSE_APB2OTP_BLK1_W9_REG register
- *  eFuse apb2otp block1 data register9.
- */
-#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x574)
-/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
-#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W9_S  0
-
-/** EFUSE_APB2OTP_BLK2_W1_REG register
- *  eFuse apb2otp block2 data register1.
- */
-#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x578)
-/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
-#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W1_S  0
-
-/** EFUSE_APB2OTP_BLK2_W2_REG register
- *  eFuse apb2otp block2 data register2.
- */
-#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x57c)
-/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
-#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W2_S  0
-
-/** EFUSE_APB2OTP_BLK2_W3_REG register
- *  eFuse apb2otp block2 data register3.
- */
-#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x580)
-/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
-#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W3_S  0
-
-/** EFUSE_APB2OTP_BLK2_W4_REG register
- *  eFuse apb2otp block2 data register4.
- */
-#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x584)
-/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
-#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W4_S  0
-
-/** EFUSE_APB2OTP_BLK2_W5_REG register
- *  eFuse apb2otp block2 data register5.
- */
-#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x588)
-/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
-#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W5_S  0
-
-/** EFUSE_APB2OTP_BLK2_W6_REG register
- *  eFuse apb2otp block2 data register6.
- */
-#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x58c)
-/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
-#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W6_S  0
-
-/** EFUSE_APB2OTP_BLK2_W7_REG register
- *  eFuse apb2otp block2 data register7.
- */
-#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x590)
-/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
-#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W7_S  0
-
-/** EFUSE_APB2OTP_BLK2_W8_REG register
- *  eFuse apb2otp block2 data register8.
- */
-#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x594)
-/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
-#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W8_S  0
-
-/** EFUSE_APB2OTP_BLK2_W9_REG register
- *  eFuse apb2otp block2 data register9.
- */
-#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x598)
-/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
-#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W9_S  0
-
-/** EFUSE_APB2OTP_BLK2_W10_REG register
- *  eFuse apb2otp block2 data register10.
- */
-#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x59c)
-/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
-#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W10_S  0
-
-/** EFUSE_APB2OTP_BLK2_W11_REG register
- *  eFuse apb2otp block2 data register11.
- */
-#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x5a0)
-/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
-#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W11_S  0
-
-/** EFUSE_APB2OTP_BLK3_W1_REG register
- *  eFuse apb2otp block3 data register1.
- */
-#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x5a4)
-/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
-#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W1_S  0
-
-/** EFUSE_APB2OTP_BLK3_W2_REG register
- *  eFuse apb2otp block3 data register2.
- */
-#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x5a8)
-/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
-#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W2_S  0
-
-/** EFUSE_APB2OTP_BLK3_W3_REG register
- *  eFuse apb2otp block3 data register3.
- */
-#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x5ac)
-/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
-#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W3_S  0
-
-/** EFUSE_APB2OTP_BLK3_W4_REG register
- *  eFuse apb2otp block3 data register4.
- */
-#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x5b0)
-/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
-#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W4_S  0
-
-/** EFUSE_APB2OTP_BLK3_W5_REG register
- *  eFuse apb2otp block3 data register5.
- */
-#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x5b4)
-/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
-#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W5_S  0
-
-/** EFUSE_APB2OTP_BLK3_W6_REG register
- *  eFuse apb2otp block3 data register6.
- */
-#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x5b8)
-/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
-#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W6_S  0
-
-/** EFUSE_APB2OTP_BLK3_W7_REG register
- *  eFuse apb2otp block3 data register7.
- */
-#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x5bc)
-/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
-#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W7_S  0
-
-/** EFUSE_APB2OTP_BLK3_W8_REG register
- *  eFuse apb2otp block3 data register8.
- */
-#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x5c0)
-/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
-#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W8_S  0
-
-/** EFUSE_APB2OTP_BLK3_W9_REG register
- *  eFuse apb2otp block3 data register9.
- */
-#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x5c4)
-/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
-#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W9_S  0
-
-/** EFUSE_APB2OTP_BLK3_W10_REG register
- *  eFuse apb2otp block3 data register10.
- */
-#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x5c8)
-/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
-#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W10_S  0
-
-/** EFUSE_APB2OTP_BLK3_W11_REG register
- *  eFuse apb2otp block3 data register11.
- */
-#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x5cc)
-/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
-#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W11_S  0
-
-/** EFUSE_APB2OTP_BLK4_W1_REG register
- *  eFuse apb2otp BLOCK7 data register1.
- */
-#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x5d0)
-/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
-#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W1_S  0
-
-/** EFUSE_APB2OTP_BLK4_W2_REG register
- *  eFuse apb2otp block4 data register2.
- */
-#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x5d4)
-/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
-#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W2_S  0
-
-/** EFUSE_APB2OTP_BLK4_W3_REG register
- *  eFuse apb2otp block4 data register3.
- */
-#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x5d8)
-/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
-#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W3_S  0
-
-/** EFUSE_APB2OTP_BLK4_W4_REG register
- *  eFuse apb2otp block4 data register4.
- */
-#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x5dc)
-/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
-#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W4_S  0
-
-/** EFUSE_APB2OTP_BLK4_W5_REG register
- *  eFuse apb2otp block4 data register5.
- */
-#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x5e0)
-/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
-#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W5_S  0
-
-/** EFUSE_APB2OTP_BLK4_W6_REG register
- *  eFuse apb2otp block4 data register6.
- */
-#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x5e4)
-/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
-#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W6_S  0
-
-/** EFUSE_APB2OTP_BLK4_W7_REG register
- *  eFuse apb2otp block4 data register7.
- */
-#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x5e8)
-/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
-#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W7_S  0
-
-/** EFUSE_APB2OTP_BLK4_W8_REG register
- *  eFuse apb2otp block4 data register8.
- */
-#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x5ec)
-/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
-#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W8_S  0
-
-/** EFUSE_APB2OTP_BLK4_W9_REG register
- *  eFuse apb2otp block4 data register9.
- */
-#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x5f0)
-/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
-#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W9_S  0
-
-/** EFUSE_APB2OTP_BLK4_W10_REG register
- *  eFuse apb2otp block4 data registe10.
- */
-#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x5f4)
-/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
-#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W10_S  0
-
-/** EFUSE_APB2OTP_BLK4_W11_REG register
- *  eFuse apb2otp block4 data register11.
- */
-#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x5f8)
-/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
-#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W11_S  0
-
-/** EFUSE_APB2OTP_BLK5_W1_REG register
- *  eFuse apb2otp block5 data register1.
- */
-#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x5fc)
-/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
-#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W1_S  0
-
-/** EFUSE_APB2OTP_BLK5_W2_REG register
- *  eFuse apb2otp block5 data register2.
- */
-#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x600)
-/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
-#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W2_S  0
-
-/** EFUSE_APB2OTP_BLK5_W3_REG register
- *  eFuse apb2otp block5 data register3.
- */
-#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x604)
-/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
-#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W3_S  0
-
-/** EFUSE_APB2OTP_BLK5_W4_REG register
- *  eFuse apb2otp block5 data register4.
- */
-#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x608)
-/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
-#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W4_S  0
-
-/** EFUSE_APB2OTP_BLK5_W5_REG register
- *  eFuse apb2otp block5 data register5.
- */
-#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x60c)
-/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
-#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W5_S  0
-
-/** EFUSE_APB2OTP_BLK5_W6_REG register
- *  eFuse apb2otp block5 data register6.
- */
-#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x610)
-/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
-#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W6_S  0
-
-/** EFUSE_APB2OTP_BLK5_W7_REG register
- *  eFuse apb2otp block5 data register7.
- */
-#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x614)
-/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
-#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W7_S  0
-
-/** EFUSE_APB2OTP_BLK5_W8_REG register
- *  eFuse apb2otp block5 data register8.
- */
-#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x618)
-/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
-#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W8_S  0
-
-/** EFUSE_APB2OTP_BLK5_W9_REG register
- *  eFuse apb2otp block5 data register9.
- */
-#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x61c)
-/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
-#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W9_S  0
-
-/** EFUSE_APB2OTP_BLK5_W10_REG register
- *  eFuse apb2otp block5 data register10.
- */
-#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x620)
-/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
-#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W10_S  0
-
-/** EFUSE_APB2OTP_BLK5_W11_REG register
- *  eFuse apb2otp block5 data register11.
- */
-#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x624)
-/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
-#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W11_S  0
-
-/** EFUSE_APB2OTP_BLK6_W1_REG register
- *  eFuse apb2otp block6 data register1.
- */
-#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x628)
-/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
-#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W1_S  0
-
-/** EFUSE_APB2OTP_BLK6_W2_REG register
- *  eFuse apb2otp block6 data register2.
- */
-#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x62c)
-/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
-#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W2_S  0
-
-/** EFUSE_APB2OTP_BLK6_W3_REG register
- *  eFuse apb2otp block6 data register3.
- */
-#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x630)
-/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
-#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W3_S  0
-
-/** EFUSE_APB2OTP_BLK6_W4_REG register
- *  eFuse apb2otp block6 data register4.
- */
-#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x634)
-/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
-#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W4_S  0
-
-/** EFUSE_APB2OTP_BLK6_W5_REG register
- *  eFuse apb2otp block6 data register5.
- */
-#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x638)
-/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
-#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W5_S  0
-
-/** EFUSE_APB2OTP_BLK6_W6_REG register
- *  eFuse apb2otp block6 data register6.
- */
-#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x63c)
-/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
-#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W6_S  0
-
-/** EFUSE_APB2OTP_BLK6_W7_REG register
- *  eFuse apb2otp block6 data register7.
- */
-#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x640)
-/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
-#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W7_S  0
-
-/** EFUSE_APB2OTP_BLK6_W8_REG register
- *  eFuse apb2otp block6 data register8.
- */
-#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x644)
-/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
-#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W8_S  0
-
-/** EFUSE_APB2OTP_BLK6_W9_REG register
- *  eFuse apb2otp block6 data register9.
- */
-#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x648)
-/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
-#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W9_S  0
-
-/** EFUSE_APB2OTP_BLK6_W10_REG register
- *  eFuse apb2otp block6 data register10.
- */
-#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x64c)
-/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
-#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W10_S  0
-
-/** EFUSE_APB2OTP_BLK6_W11_REG register
- *  eFuse apb2otp block6 data register11.
- */
-#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x650)
-/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
-#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W11_S  0
-
-/** EFUSE_APB2OTP_BLK7_W1_REG register
- *  eFuse apb2otp block7 data register1.
- */
-#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x654)
-/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
-#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W1_S  0
-
-/** EFUSE_APB2OTP_BLK7_W2_REG register
- *  eFuse apb2otp block7 data register2.
- */
-#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x658)
-/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
-#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W2_S  0
-
-/** EFUSE_APB2OTP_BLK7_W3_REG register
- *  eFuse apb2otp block7 data register3.
- */
-#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x65c)
-/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
-#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W3_S  0
-
-/** EFUSE_APB2OTP_BLK7_W4_REG register
- *  eFuse apb2otp block7 data register4.
- */
-#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x660)
-/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
-#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W4_S  0
-
-/** EFUSE_APB2OTP_BLK7_W5_REG register
- *  eFuse apb2otp block7 data register5.
- */
-#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x664)
-/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
-#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W5_S  0
-
-/** EFUSE_APB2OTP_BLK7_W6_REG register
- *  eFuse apb2otp block7 data register6.
- */
-#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x668)
-/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
-#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W6_S  0
-
-/** EFUSE_APB2OTP_BLK7_W7_REG register
- *  eFuse apb2otp block7 data register7.
- */
-#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x66c)
-/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
-#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W7_S  0
-
-/** EFUSE_APB2OTP_BLK7_W8_REG register
- *  eFuse apb2otp block7 data register8.
- */
-#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x670)
-/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
-#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W8_S  0
-
-/** EFUSE_APB2OTP_BLK7_W9_REG register
- *  eFuse apb2otp block7 data register9.
- */
-#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x674)
-/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
-#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W9_S  0
-
-/** EFUSE_APB2OTP_BLK7_W10_REG register
- *  eFuse apb2otp block7 data register10.
- */
-#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x678)
-/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
-#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W10_S  0
-
-/** EFUSE_APB2OTP_BLK7_W11_REG register
- *  eFuse apb2otp block7 data register11.
- */
-#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x67c)
-/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
-#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W11_S  0
-
-/** EFUSE_APB2OTP_BLK8_W1_REG register
- *  eFuse apb2otp block8 data register1.
- */
-#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x680)
-/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
-#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W1_S  0
-
-/** EFUSE_APB2OTP_BLK8_W2_REG register
- *  eFuse apb2otp block8 data register2.
- */
-#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x684)
-/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
-#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W2_S  0
-
-/** EFUSE_APB2OTP_BLK8_W3_REG register
- *  eFuse apb2otp block8 data register3.
- */
-#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x688)
-/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
-#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W3_S  0
-
-/** EFUSE_APB2OTP_BLK8_W4_REG register
- *  eFuse apb2otp block8 data register4.
- */
-#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x68c)
-/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
-#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W4_S  0
-
-/** EFUSE_APB2OTP_BLK8_W5_REG register
- *  eFuse apb2otp block8 data register5.
- */
-#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x690)
-/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
-#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W5_S  0
-
-/** EFUSE_APB2OTP_BLK8_W6_REG register
- *  eFuse apb2otp block8 data register6.
- */
-#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x694)
-/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
-#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W6_S  0
-
-/** EFUSE_APB2OTP_BLK8_W7_REG register
- *  eFuse apb2otp block8 data register7.
- */
-#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x698)
-/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
-#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W7_S  0
-
-/** EFUSE_APB2OTP_BLK8_W8_REG register
- *  eFuse apb2otp block8 data register8.
- */
-#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x69c)
-/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
-#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W8_S  0
-
-/** EFUSE_APB2OTP_BLK8_W9_REG register
- *  eFuse apb2otp block8 data register9.
- */
-#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x6a0)
-/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
-#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W9_S  0
-
-/** EFUSE_APB2OTP_BLK8_W10_REG register
- *  eFuse apb2otp block8 data register10.
- */
-#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x6a4)
-/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
-#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W10_S  0
-
-/** EFUSE_APB2OTP_BLK8_W11_REG register
- *  eFuse apb2otp block8 data register11.
- */
-#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x6a8)
-/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
-#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W11_S  0
-
-/** EFUSE_APB2OTP_BLK9_W1_REG register
- *  eFuse apb2otp block9 data register1.
- */
-#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x6ac)
-/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
-#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W1_S  0
-
-/** EFUSE_APB2OTP_BLK9_W2_REG register
- *  eFuse apb2otp block9 data register2.
- */
-#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x6b0)
-/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
-#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W2_S  0
-
-/** EFUSE_APB2OTP_BLK9_W3_REG register
- *  eFuse apb2otp block9 data register3.
- */
-#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x6b4)
-/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
-#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W3_S  0
-
-/** EFUSE_APB2OTP_BLK9_W4_REG register
- *  eFuse apb2otp block9 data register4.
- */
-#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x6b8)
-/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
-#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W4_S  0
-
-/** EFUSE_APB2OTP_BLK9_W5_REG register
- *  eFuse apb2otp block9 data register5.
- */
-#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x6bc)
-/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
-#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W5_S  0
-
-/** EFUSE_APB2OTP_BLK9_W6_REG register
- *  eFuse apb2otp block9 data register6.
- */
-#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x6c0)
-/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
-#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W6_S  0
-
-/** EFUSE_APB2OTP_BLK9_W7_REG register
- *  eFuse apb2otp block9 data register7.
- */
-#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x6c4)
-/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
-#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W7_S  0
-
-/** EFUSE_APB2OTP_BLK9_W8_REG register
- *  eFuse apb2otp block9 data register8.
- */
-#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x6c8)
-/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
-#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W8_S  0
-
-/** EFUSE_APB2OTP_BLK9_W9_REG register
- *  eFuse apb2otp block9 data register9.
- */
-#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x6cc)
-/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
-#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W9_S  0
-
-/** EFUSE_APB2OTP_BLK9_W10_REG register
- *  eFuse apb2otp block9 data register10.
- */
-#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x6d0)
-/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
-#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W10_S  0
-
-/** EFUSE_APB2OTP_BLK9_W11_REG register
- *  eFuse apb2otp block9 data register11.
- */
-#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x6d4)
-/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
-#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W11_S  0
-
-/** EFUSE_APB2OTP_BLK10_W1_REG register
- *  eFuse apb2otp block10 data register1.
- */
-#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x6d8)
-/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
-#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W1_S  0
-
-/** EFUSE_APB2OTP_BLK10_W2_REG register
- *  eFuse apb2otp block10 data register2.
- */
-#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x6dc)
-/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
-#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W2_S  0
-
-/** EFUSE_APB2OTP_BLK10_W3_REG register
- *  eFuse apb2otp block10 data register3.
- */
-#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x6e0)
-/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
-#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W3_S  0
-
-/** EFUSE_APB2OTP_BLK10_W4_REG register
- *  eFuse apb2otp block10 data register4.
- */
-#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x6e4)
-/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
-#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W4_S  0
-
-/** EFUSE_APB2OTP_BLK10_W5_REG register
- *  eFuse apb2otp block10 data register5.
- */
-#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x6e8)
-/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
-#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W5_S  0
-
-/** EFUSE_APB2OTP_BLK10_W6_REG register
- *  eFuse apb2otp block10 data register6.
- */
-#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x6ec)
-/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
-#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W6_S  0
-
-/** EFUSE_APB2OTP_BLK10_W7_REG register
- *  eFuse apb2otp block10 data register7.
- */
-#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x6f0)
-/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
-#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W7_S  0
-
-/** EFUSE_APB2OTP_BLK10_W8_REG register
- *  eFuse apb2otp block10 data register8.
- */
-#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x6f4)
-/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
-#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W8_S  0
-
-/** EFUSE_APB2OTP_BLK10_W9_REG register
- *  eFuse apb2otp block10 data register9.
- */
-#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x6f8)
-/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
-#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W9_S  0
-
-/** EFUSE_APB2OTP_BLK10_W10_REG register
- *  eFuse apb2otp block10 data register10.
- */
-#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x6fc)
-/** EFUSE_APB2OTP_BLOCK10_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W10_M  (EFUSE_APB2OTP_BLOCK10_W10_V << EFUSE_APB2OTP_BLOCK10_W10_S)
-#define EFUSE_APB2OTP_BLOCK10_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W10_S  0
-
-/** EFUSE_APB2OTP_BLK10_W11_REG register
- *  eFuse apb2otp block10 data register11.
- */
-#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0x700)
-/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
-#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W11_S  0
-
-/** EFUSE_APB2OTP_EN_REG register
- *  eFuse apb2otp enable configuration register.
- */
-#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0x708)
-/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
- *  Apb2otp mode enable signal.
- */
-#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
-#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
-#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
-#define EFUSE_APB2OTP_APB2OTP_EN_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/efuse_struct.h b/components/soc/esp32c5/include/soc/efuse_struct.h
deleted file mode 100644
index d4825477e61..00000000000
--- a/components/soc/esp32c5/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,4573 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: buffer0 registers */
-/** Type of pgm_data0 register
- *  Represents pgm_data0
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Represents pgm_data1
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Represents pgm_data2
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Represents pgm_data3
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Represents pgm_data4
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Represents pgm_data5
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Represents pgm_data6
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Represents pgm_data7
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-
-/** Group: buffer1 registers */
-/** Type of pgm_check_value0 register
- *  Represents pgm_check_value0
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Represents pgm_check_value1
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Represents pgm_check_value2
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: block0 registers */
-/** Type of rd_wr_dis0 register
- *  Represents rd_wr_dis
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled or
-         *  enabled.\\ 1: Disabled\\ 0: Enabled\\
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis0_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t rd_dis:7;
-        /** rd_reserve_0_39 : RW; bitpos: [7]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_39:1;
-        /** dis_icache : RO; bitpos: [8]; default: 0;
-         *  Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t dis_icache:1;
-        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
-         *  disabled\\ 0: enabled\\
-         */
-        uint32_t dis_usb_jtag:1;
-        /** rd_reserve_0_42 : RW; bitpos: [10]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_42:1;
-        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
-         *  Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
-         *  enabled\\
-         */
-        uint32_t dis_usb_serial_jtag:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Represents whether the function that forces chip into download mode is disabled or
-         *  enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t dis_force_download:1;
-        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
-         *  Represents whether SPI0 controller during boot_mode_download is disabled or
-         *  enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t spi_download_mspi_dis:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0:
-         *  enabled\\
-         */
-        uint32_t dis_twai:1;
-        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         *  is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
-         */
-        uint32_t jtag_sel_enable:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even
-         *  number: enabled\\
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
-         *  0: enabled\\
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
-         *  mode).\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefh:2;
-        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefl:2;
-        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
-         *  Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not
-         *  exchanged\\
-         */
-        uint32_t usb_exchg_pins:1;
-        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
-         *  Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not
-         *  functioned\\
-         */
-        uint32_t vdd_spi_as_gpio:1;
-        /** rd_reserve_0_59 : RW; bitpos: [31:27]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_59:5;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** km_disable_deploy_mode : RO; bitpos: [3:0]; default: 0;
-         *  Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled
-         *  \\ 0: enabled.\\
-         */
-        uint32_t km_disable_deploy_mode:4;
-        /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0;
-         *  Set the bits to control key manager random number switch cycle. 0: control by
-         *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
-         */
-        uint32_t km_rnd_switch_cycle:2;
-        /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0;
-         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
-         *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
-         */
-        uint32_t km_deploy_only_once:4;
-        /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0;
-         *  Set each bit to control whether corresponding key must come from key manager. 1 is
-         *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
-         */
-        uint32_t force_use_key_manager_key:4;
-        /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0;
-         *  Set this bit to disable software written init key, and force use efuse_init_key.
-         */
-        uint32_t force_disable_sw_init_key:1;
-        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_79:1;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original
-         *  threshold configuration value of STG0 *2 \\1: Original threshold configuration
-         *  value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3:
-         *  Original threshold configuration value of STG0 *16 \\
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
-         *  1: enabled\\ Even number of 1: disabled\\
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
-         *  enabled\\ 0: disabled\\
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
-         *  enabled\\ 0: disabled\\
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
-         *  enabled\\ 0: disabled\\
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Represents the purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Represents the purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Represents the purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Represents the purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Represents the purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Represents the purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
-         *  Represents the spa secure level by configuring the clock random divide mode.
-         */
-        uint32_t sec_dpa_level:2;
-        /** rd_reserve_0_114 : RW; bitpos: [19:18]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_114:2;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
-         *  enabled.\\ 0: disabled\\
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** rd_reserve_0_118 : RW; bitpos: [26:22]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_118:5;
-        /** km_xts_key_length_256 : RO; bitpos: [27]; default: 0;
-         *  Set this bitto configure flash encryption use xts-128 key. else use xts-256 key.
-         */
-        uint32_t km_xts_key_length_256:1;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Represents the flash waiting time after power-up, in unit of ms. When the value
-         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
-         *  is 2 times the programmed value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0:
-         *  enabled\\
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0:
-         *  enabled\\
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1:
-         *  disabled\\ 0: enabled\\
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** lock_km_key : RO; bitpos: [3]; default: 0;
-         *  Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\
-         */
-        uint32_t lock_km_key:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
-         *  1: Disable\\ 0: Enable\\
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0:
-         *  disabled\\
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable
-         *  printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset
-         *  at high level\\ 11: force disable printing\\
-         */
-        uint32_t uart_print_control:2;
-        /** force_send_resume : RO; bitpos: [8]; default: 0;
-         *  Represents whether ROM code is forced to send a resume command during SPI boot.\\
-         *  1: forced\\ 0:not forced\\
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [24:9]; default: 0;
-         *  Represents the version used by ESP-IDF anti-rollback feature.
-         */
-        uint32_t secure_version:16;
-        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
-         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
-         *  enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t secure_boot_disable_fast_wake:1;
-        /** hys_en_pad : RO; bitpos: [26]; default: 0;
-         *  Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
-         *  enabled\\ 0:disabled\\
-         */
-        uint32_t hys_en_pad:1;
-        /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0;
-         *  Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2:
-         *  Moderate 1. Low\\ 0: Disabled\\
-         */
-        uint32_t xts_dpa_pseudo_level:2;
-        /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0;
-         *  Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0:
-         *  Disable.\\
-         */
-        uint32_t xts_dpa_clk_enable:1;
-        /** rd_reserve_0_158 : RW; bitpos: [31:30]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_158:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** huk_gen_state : RO; bitpos: [8:0]; default: 0;
-         *  Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\
-         *  Even of 1 is valid.\\
-         */
-        uint32_t huk_gen_state:9;
-        /** xtal_48m_sel : RO; bitpos: [11:9]; default: 0;
-         *  Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used.
-         *  If this field contains Odd number bit '1': Enable 48MHz XTAL\\ Even number bit '1':
-         *  Enable 40MHz XTAL.
-         */
-        uint32_t xtal_48m_sel:3;
-        /** xtal_48m_sel_mode : RO; bitpos: [12]; default: 0;
-         *  Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1:
-         *  eFuse\\ 0: strapping-PAD-state.
-         */
-        uint32_t xtal_48m_sel_mode:1;
-        /** ecdsa_disable_p192 : RO; bitpos: [13]; default: 0;
-         *  Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable.
-         */
-        uint32_t ecdsa_disable_p192:1;
-        /** ecc_force_const_time : RO; bitpos: [14]; default: 0;
-         *  Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
-         *  \\ 0: Disable.
-         */
-        uint32_t ecc_force_const_time:1;
-        /** rd_reserve_0_175 : RW; bitpos: [31:15]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_175:17;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-
-/** Group: block1 registers */
-/** Type of rd_mac_sys0 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents MAC address. Low 32-bit.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys0_reg_t;
-
-/** Type of rd_mac_sys1 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Represents MAC address. High 16-bit.
-         */
-        uint32_t mac_1:16;
-        /** mac_ext : RO; bitpos: [31:16]; default: 0;
-         *  Represents the extended bits of MAC address.
-         */
-        uint32_t mac_ext:16;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys1_reg_t;
-
-/** Type of rd_mac_sys2 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** wafer_version_minor : R; bitpos: [3:0]; default: 0;
-         *  Minor chip version
-         */
-        uint32_t wafer_version_minor:4;
-        /** wafer_version_major : R; bitpos: [5:4]; default: 0;
-         *  Minor chip version
-         */
-        uint32_t wafer_version_major:2;
-        /** disable_wafer_version_major : R; bitpos: [6]; default: 0;
-         *  Disables check of wafer version major
-         */
-        uint32_t disable_wafer_version_major:1;
-        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
-         *  Disables check of blk version major
-         */
-        uint32_t disable_blk_version_major:1;
-        /** blk_version_minor : R; bitpos: [10:8]; default: 0;
-         *  BLK_VERSION_MINOR of BLOCK2
-         */
-        uint32_t blk_version_minor:3;
-        /** blk_version_major : R; bitpos: [12:11]; default: 0;
-         *  BLK_VERSION_MAJOR of BLOCK2
-         */
-        uint32_t blk_version_major:2;
-        /** flash_cap : R; bitpos: [15:13]; default: 0;
-         *  Flash capacity
-         */
-        uint32_t flash_cap:3;
-        /** flash_vendor : R; bitpos: [18:16]; default: 0;
-         *  Flash vendor
-         */
-        uint32_t flash_vendor:3;
-        /** psram_cap : R; bitpos: [21:19]; default: 0;
-         *  Psram capacity
-         */
-        uint32_t psram_cap:3;
-        /** psram_vendor : R; bitpos: [23:22]; default: 0;
-         *  Psram vendor
-         */
-        uint32_t psram_vendor:2;
-        /** temp : R; bitpos: [25:24]; default: 0;
-         *  Temp (die embedded inside)
-         */
-        uint32_t temp:2;
-        /** pkg_version : R; bitpos: [28:26]; default: 0;
-         *  Package version
-         */
-        uint32_t pkg_version:3;
-        /** pa_trim_version : R; bitpos: [31:29]; default: 0;
-         *  PADC CAL PA trim version
-         */
-        uint32_t pa_trim_version:3;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys2_reg_t;
-
-/** Type of rd_mac_sys3 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** trim_n_bias : R; bitpos: [4:0]; default: 0;
-         *  PADC CAL N bias
-         */
-        uint32_t trim_n_bias:5;
-        /** trim_p_bias : R; bitpos: [9:5]; default: 0;
-         *  PADC CAL P bias
-         */
-        uint32_t trim_p_bias:5;
-        /** reserved_1_106 : R; bitpos: [17:10]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_106:8;
-        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
-         *  Represents the first 14-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_0:14;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys3_reg_t;
-
-/** Type of rd_mac_sys4 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the first 14-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_1:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys4_reg_t;
-
-/** Type of rd_mac_sys5 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the second 32-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_2:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys5_reg_t;
-
-
-/** Group: block2 registers */
-/** Type of rd_sys_part1_data0 register
- *  Represents rd_sys_part1_data0
- */
-typedef union {
-    struct {
-        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Represents rd_sys_part1_data1
- */
-typedef union {
-    struct {
-        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Represents rd_sys_part1_data2
- */
-typedef union {
-    struct {
-        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Represents rd_sys_part1_data3
- */
-typedef union {
-    struct {
-        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Represents rd_sys_part1_data4
- */
-typedef union {
-    struct {
-        /** reserved_2_128 : R; bitpos: [8:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_128:9;
-        /** ocode : R; bitpos: [16:9]; default: 0;
-         *  ADC OCode
-         */
-        uint32_t ocode:8;
-        /** reserved_2_145 : R; bitpos: [31:17]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_145:15;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Represents rd_sys_part1_data5
- */
-typedef union {
-    struct {
-        /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Represents rd_sys_part1_data6
- */
-typedef union {
-    struct {
-        /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Represents rd_sys_part1_data7
- */
-typedef union {
-    struct {
-        /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-
-/** Group: block3 registers */
-/** Type of rd_usr_data0 register
- *  Represents rd_usr_data0
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Represents rd_usr_data1
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Represents rd_usr_data2
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Represents rd_usr_data3
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Represents rd_usr_data4
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Represents rd_usr_data5
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Represents rd_usr_data6
- */
-typedef union {
-    struct {
-        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_192:8;
-        /** custom_mac : R; bitpos: [31:8]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac:24;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Represents rd_usr_data7
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac_1:24;
-        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_248:8;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-
-/** Group: block4 registers */
-/** Type of rd_key0_data0 register
- *  Represents rd_key0_data0
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Represents rd_key0_data1
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Represents rd_key0_data2
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Represents rd_key0_data3
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Represents rd_key0_data4
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Represents rd_key0_data5
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Represents rd_key0_data6
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Represents rd_key0_data7
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-
-/** Group: block5 registers */
-/** Type of rd_key1_data0 register
- *  Represents rd_key1_data0
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Represents rd_key1_data1
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Represents rd_key1_data2
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Represents rd_key1_data3
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Represents rd_key1_data4
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Represents rd_key1_data5
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Represents rd_key1_data6
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Represents rd_key1_data7
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-
-/** Group: block6 registers */
-/** Type of rd_key2_data0 register
- *  Represents rd_key2_data0
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Represents rd_key2_data1
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Represents rd_key2_data2
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Represents rd_key2_data3
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Represents rd_key2_data4
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Represents rd_key2_data5
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Represents rd_key2_data6
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Represents rd_key2_data7
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-
-/** Group: block7 registers */
-/** Type of rd_key3_data0 register
- *  Represents rd_key3_data0
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Represents rd_key3_data1
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Represents rd_key3_data2
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Represents rd_key3_data3
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Represents rd_key3_data4
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Represents rd_key3_data5
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Represents rd_key3_data6
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Represents rd_key3_data7
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-
-/** Group: block8 registers */
-/** Type of rd_key4_data0 register
- *  Represents rd_key4_data0
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Represents rd_key4_data1
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Represents rd_key4_data2
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Represents rd_key4_data3
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Represents rd_key4_data4
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Represents rd_key4_data5
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Represents rd_key4_data6
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Represents rd_key4_data7
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-
-/** Group: block9 registers */
-/** Type of rd_key5_data0 register
- *  Represents rd_key5_data0
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Represents rd_key5_data1
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Represents rd_key5_data2
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Represents rd_key5_data3
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Represents rd_key5_data4
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Represents rd_key5_data5
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Represents rd_key5_data6
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Represents rd_key5_data7
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-
-/** Group: block10 registers */
-/** Type of rd_sys_part2_data0 register
- *  Represents rd_sys_part2_data0
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Represents rd_sys_part2_data1
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Represents rd_sys_part2_data2
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Represents rd_sys_part2_data3
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Represents rd_sys_part2_data4
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Represents rd_sys_part2_data5
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Represents rd_sys_part2_data6
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Represents rd_sys_part2_data7
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-
-/** Group: block0 error report registers */
-/** Type of rd_repeat_data_err0 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Represents the programming error of EFUSE_RD_DIS
-         */
-        uint32_t rd_dis_err:7;
-        uint32_t reserved_7:1;
-        /** dis_icache_err : RO; bitpos: [8]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_ICACHE
-         */
-        uint32_t dis_icache_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_JTAG
-         */
-        uint32_t dis_usb_jtag_err:1;
-        uint32_t reserved_10:1;
-        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
-         */
-        uint32_t dis_usb_serial_jtag_err:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
-         */
-        uint32_t dis_force_download_err:1;
-        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
-         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
-         */
-        uint32_t spi_download_mspi_dis_err:1;
-        /** dis_twai_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_TWAI
-         */
-        uint32_t dis_twai_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
-         *  Represents the programming error of EFUSE_USB_DREFH
-         */
-        uint32_t usb_drefh_err:2;
-        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
-         *  Represents the programming error of EFUSE_USB_DREFL
-         */
-        uint32_t usb_drefl_err:2;
-        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
-         *  Represents the programming error of EFUSE_USB_EXCHG_PINS
-         */
-        uint32_t usb_exchg_pins_err:1;
-        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
-         */
-        uint32_t vdd_spi_as_gpio_err:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err0_reg_t;
-
-/** Type of rd_repeat_data_err1 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** km_disable_deploy_mode_err : RO; bitpos: [3:0]; default: 0;
-         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
-         */
-        uint32_t km_disable_deploy_mode_err:4;
-        /** km_rnd_switch_cycle_err : RO; bitpos: [5:4]; default: 0;
-         *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
-         */
-        uint32_t km_rnd_switch_cycle_err:2;
-        /** km_deploy_only_once_err : RO; bitpos: [9:6]; default: 0;
-         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
-         */
-        uint32_t km_deploy_only_once_err:4;
-        /** force_use_key_manager_key_err : RO; bitpos: [13:10]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
-         */
-        uint32_t force_use_key_manager_key_err:4;
-        /** force_disable_sw_init_key_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
-         */
-        uint32_t force_disable_sw_init_key_err:1;
-        uint32_t reserved_15:1;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err1_reg_t;
-
-/** Type of rd_repeat_data_err2 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
-         */
-        uint32_t key_purpose_5_err:4;
-        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
-         */
-        uint32_t sec_dpa_level_err:2;
-        uint32_t reserved_18:2;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        uint32_t reserved_22:5;
-        /** km_xts_key_length_256_err : RO; bitpos: [27]; default: 0;
-         *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
-         */
-        uint32_t km_xts_key_length_256_err:1;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Represents the programming error of EFUSE_FLASH_TPUW
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err2_reg_t;
-
-/** Type of rd_repeat_data_err3 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
-         */
-        uint32_t dis_usb_serial_jtag_rom_print_err:1;
-        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
-         *  Represents the programming error of EFUSE_LOCK_KM_KEY
-         */
-        uint32_t lock_km_key_err:1;
-        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
-         */
-        uint32_t dis_usb_serial_jtag_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
-         */
-        uint32_t uart_print_control_err:2;
-        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_VERSION
-         */
-        uint32_t secure_version_err:16;
-        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
-         */
-        uint32_t secure_boot_disable_fast_wake_err:1;
-        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_HYS_EN_PAD
-         */
-        uint32_t hys_en_pad_err:1;
-        /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0;
-         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
-         */
-        uint32_t xts_dpa_pseudo_level_err:2;
-        /** xts_dpa_clk_enable_err : RO; bitpos: [29]; default: 0;
-         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
-         */
-        uint32_t xts_dpa_clk_enable_err:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err3_reg_t;
-
-/** Type of rd_repeat_data_err4 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** huk_gen_state_err : RO; bitpos: [8:0]; default: 0;
-         *  Represents the programming error of EFUSE_HUK_GEN_STATE
-         */
-        uint32_t huk_gen_state_err:9;
-        /** xtal_48m_sel_err : RO; bitpos: [11:9]; default: 0;
-         *  Represents the programming error of EFUSE_XTAL_48M_SEL
-         */
-        uint32_t xtal_48m_sel_err:3;
-        /** xtal_48m_sel_mode_err : RO; bitpos: [12]; default: 0;
-         *  Represents the programming error of EFUSE_XTAL_48M_SEL_MODE
-         */
-        uint32_t xtal_48m_sel_mode_err:1;
-        /** ecdsa_disable_p192_err : RO; bitpos: [13]; default: 0;
-         *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
-         */
-        uint32_t ecdsa_disable_p192_err:1;
-        /** ecc_force_const_time_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
-         */
-        uint32_t ecc_force_const_time_err:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err4_reg_t;
-
-
-/** Group: RS block error report registers */
-/** Type of rd_rs_data_err0 register
- *  Represents rd_rs_data_err
- */
-typedef union {
-    struct {
-        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_mac_sys
-         */
-        uint32_t rd_mac_sys_err_num:3;
-        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
-         *  of error bytes is over 6.
-         */
-        uint32_t rd_mac_sys_fail:1;
-        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_sys_part1_data
-         */
-        uint32_t rd_sys_part1_data_err_num:3;
-        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
-         *  and the number of error bytes is over 6.
-         */
-        uint32_t rd_sys_part1_data_fail:1;
-        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_usr_data
-         */
-        uint32_t rd_usr_data_err_num:3;
-        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_usr_data_fail:1;
-        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key0_data
-         */
-        uint32_t rd_key0_data_err_num:3;
-        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key0_data_fail:1;
-        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key1_data
-         */
-        uint32_t rd_key1_data_err_num:3;
-        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key1_data_fail:1;
-        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key2_data
-         */
-        uint32_t rd_key2_data_err_num:3;
-        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key2_data_fail:1;
-        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key3_data
-         */
-        uint32_t rd_key3_data_err_num:3;
-        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key3_data_fail:1;
-        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key4_data
-         */
-        uint32_t rd_key4_data_err_num:3;
-        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key4_data_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_data_err0_reg_t;
-
-/** Type of rd_rs_data_err1 register
- *  Represents rd_rs_data_err
- */
-typedef union {
-    struct {
-        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key5_data
-         */
-        uint32_t rd_key5_data_err_num:3;
-        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key5_data_fail:1;
-        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_sys_part2_data
-         */
-        uint32_t rd_sys_part2_data_err_num:3;
-        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
-         *  and the number of error bytes is over 6.
-         */
-        uint32_t rd_sys_part2_data_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_data_err1_reg_t;
-
-
-/** Group: EFUSE Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 37752960;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-/** Group: EFUSE Clock Registers */
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to force enable eFuse register configuration clock signal.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-
-/** Group: EFUSE Configure Registers */
-/** Type of conf register
- *  eFuse operation mode configuration register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
-         */
-        uint32_t op_code:16;
-        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
-         *  Configures which block to use for ECDSA key output.
-         */
-        uint32_t cfg_ecdsa_blk:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Group: EFUSE Configure Registers */
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the read hold time.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures the read time.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures the read setup time.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 22;
-         *  Configures the waiting time of reading eFuse memory.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the programming setup time.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        /** thp_a : R/W; bitpos: [31:24]; default: 1;
-         *  Configures the programming hold time.
-         */
-        uint32_t thp_a:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        /** tpgm : R/W; bitpos: [31:16]; default: 200;
-         *  Configures the active programming time.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-/** Type of wr_tim_conf0_rs_bypass register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-typedef union {
-    struct {
-        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to bypass reed solomon correction step.
-         */
-        uint32_t bypass_rs_correction:1;
-        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
-         *  Configures block number of programming twice operation.
-         */
-        uint32_t bypass_rs_blk_num:11;
-        /** update : WT; bitpos: [12]; default: 0;
-         *  Set this bit to update multi-bit register signals.
-         */
-        uint32_t update:1;
-        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
-         *  Configures the inactive programming time.
-         */
-        uint32_t tpgm_inactive:8;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_rs_bypass_reg_t;
-
-
-/** Group: EFUSE Status Registers */
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
-         *  Indicates which block is used for ECDSA key output.
-         */
-        uint32_t cur_ecdsa_blk:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-
-/** Group: EFUSE Command Registers */
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
-/** Type of apb2otp_wr_dis register
- *  eFuse apb2otp block0 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 write disable data.
-         */
-        uint32_t apb2otp_block0_wr_dis:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_wr_dis_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
-/** Type of apb2otp_blk0_backup1_w1 register
- *  eFuse apb2otp block0 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word1 data.
-         */
-        uint32_t apb2otp_block0_backup1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
-/** Type of apb2otp_blk0_backup1_w2 register
- *  eFuse apb2otp block0 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word2 data.
-         */
-        uint32_t apb2otp_block0_backup1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
-/** Type of apb2otp_blk0_backup1_w3 register
- *  eFuse apb2otp block0 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word3 data.
-         */
-        uint32_t apb2otp_block0_backup1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
-/** Type of apb2otp_blk0_backup1_w4 register
- *  eFuse apb2otp block0 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word4 data.
-         */
-        uint32_t apb2otp_block0_backup1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
-/** Type of apb2otp_blk0_backup1_w5 register
- *  eFuse apb2otp block0 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word5 data.
-         */
-        uint32_t apb2otp_block0_backup1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
-/** Type of apb2otp_blk0_backup2_w1 register
- *  eFuse apb2otp block0 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word1 data.
-         */
-        uint32_t apb2otp_block0_backup2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
-/** Type of apb2otp_blk0_backup2_w2 register
- *  eFuse apb2otp block0 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word2 data.
-         */
-        uint32_t apb2otp_block0_backup2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
-/** Type of apb2otp_blk0_backup2_w3 register
- *  eFuse apb2otp block0 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word3 data.
-         */
-        uint32_t apb2otp_block0_backup2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
-/** Type of apb2otp_blk0_backup2_w4 register
- *  eFuse apb2otp block0 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word4 data.
-         */
-        uint32_t apb2otp_block0_backup2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
-/** Type of apb2otp_blk0_backup2_w5 register
- *  eFuse apb2otp block0 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word5 data.
-         */
-        uint32_t apb2otp_block0_backup2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
-/** Type of apb2otp_blk0_backup3_w1 register
- *  eFuse apb2otp block0 data register12.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word1 data.
-         */
-        uint32_t apb2otp_block0_backup3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
-/** Type of apb2otp_blk0_backup3_w2 register
- *  eFuse apb2otp block0 data register13.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word2 data.
-         */
-        uint32_t apb2otp_block0_backup3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
-/** Type of apb2otp_blk0_backup3_w3 register
- *  eFuse apb2otp block0 data register14.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word3 data.
-         */
-        uint32_t apb2otp_block0_backup3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
-/** Type of apb2otp_blk0_backup3_w4 register
- *  eFuse apb2otp block0 data register15.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word4 data.
-         */
-        uint32_t apb2otp_block0_backup3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
-/** Type of apb2otp_blk0_backup3_w5 register
- *  eFuse apb2otp block0 data register16.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word5 data.
-         */
-        uint32_t apb2otp_block0_backup3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
-/** Type of apb2otp_blk0_backup4_w1 register
- *  eFuse apb2otp block0 data register17.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word1 data.
-         */
-        uint32_t apb2otp_block0_backup4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
-/** Type of apb2otp_blk0_backup4_w2 register
- *  eFuse apb2otp block0 data register18.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word2 data.
-         */
-        uint32_t apb2otp_block0_backup4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
-/** Type of apb2otp_blk0_backup4_w3 register
- *  eFuse apb2otp block0 data register19.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word3 data.
-         */
-        uint32_t apb2otp_block0_backup4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
-/** Type of apb2otp_blk0_backup4_w4 register
- *  eFuse apb2otp block0 data register20.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word4 data.
-         */
-        uint32_t apb2otp_block0_backup4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
-/** Type of apb2otp_blk0_backup4_w5 register
- *  eFuse apb2otp block0 data register21.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word5 data.
-         */
-        uint32_t apb2otp_block0_backup4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word1 Data */
-/** Type of apb2otp_blk1_w1 register
- *  eFuse apb2otp block1 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word1 data.
-         */
-        uint32_t apb2otp_block1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word2 Data */
-/** Type of apb2otp_blk1_w2 register
- *  eFuse apb2otp block1 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word2 data.
-         */
-        uint32_t apb2otp_block1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word3 Data */
-/** Type of apb2otp_blk1_w3 register
- *  eFuse apb2otp block1 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word3 data.
-         */
-        uint32_t apb2otp_block1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word4 Data */
-/** Type of apb2otp_blk1_w4 register
- *  eFuse apb2otp block1 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word4 data.
-         */
-        uint32_t apb2otp_block1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word5 Data */
-/** Type of apb2otp_blk1_w5 register
- *  eFuse apb2otp block1 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word5 data.
-         */
-        uint32_t apb2otp_block1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word6 Data */
-/** Type of apb2otp_blk1_w6 register
- *  eFuse apb2otp block1 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word6 data.
-         */
-        uint32_t apb2otp_block1_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word7 Data */
-/** Type of apb2otp_blk1_w7 register
- *  eFuse apb2otp block1 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word7 data.
-         */
-        uint32_t apb2otp_block1_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word8 Data */
-/** Type of apb2otp_blk1_w8 register
- *  eFuse apb2otp block1 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word8 data.
-         */
-        uint32_t apb2otp_block1_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word9 Data */
-/** Type of apb2otp_blk1_w9 register
- *  eFuse apb2otp block1 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word9 data.
-         */
-        uint32_t apb2otp_block1_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word1 Data */
-/** Type of apb2otp_blk2_w1 register
- *  eFuse apb2otp block2 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word1 data.
-         */
-        uint32_t apb2otp_block2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word2 Data */
-/** Type of apb2otp_blk2_w2 register
- *  eFuse apb2otp block2 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word2 data.
-         */
-        uint32_t apb2otp_block2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word3 Data */
-/** Type of apb2otp_blk2_w3 register
- *  eFuse apb2otp block2 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word3 data.
-         */
-        uint32_t apb2otp_block2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word4 Data */
-/** Type of apb2otp_blk2_w4 register
- *  eFuse apb2otp block2 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word4 data.
-         */
-        uint32_t apb2otp_block2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word5 Data */
-/** Type of apb2otp_blk2_w5 register
- *  eFuse apb2otp block2 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word5 data.
-         */
-        uint32_t apb2otp_block2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word6 Data */
-/** Type of apb2otp_blk2_w6 register
- *  eFuse apb2otp block2 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word6 data.
-         */
-        uint32_t apb2otp_block2_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word7 Data */
-/** Type of apb2otp_blk2_w7 register
- *  eFuse apb2otp block2 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word7 data.
-         */
-        uint32_t apb2otp_block2_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word8 Data */
-/** Type of apb2otp_blk2_w8 register
- *  eFuse apb2otp block2 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word8 data.
-         */
-        uint32_t apb2otp_block2_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word9 Data */
-/** Type of apb2otp_blk2_w9 register
- *  eFuse apb2otp block2 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word9 data.
-         */
-        uint32_t apb2otp_block2_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word10 Data */
-/** Type of apb2otp_blk2_w10 register
- *  eFuse apb2otp block2 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word10 data.
-         */
-        uint32_t apb2otp_block2_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word11 Data */
-/** Type of apb2otp_blk2_w11 register
- *  eFuse apb2otp block2 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word11 data.
-         */
-        uint32_t apb2otp_block2_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w11_reg_t;
-
-/** Group: EFUSE_APB2OTP Block2 Word11 Data */
-/** Type of apb2otp_blk10_w11 register
- *  eFuse apb2otp block10 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word11 data.
-         */
-        uint32_t apb2otp_block10_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word1 Data */
-/** Type of apb2otp_blk3_w1 register
- *  eFuse apb2otp block3 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word1 data.
-         */
-        uint32_t apb2otp_block3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word2 Data */
-/** Type of apb2otp_blk3_w2 register
- *  eFuse apb2otp block3 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word2 data.
-         */
-        uint32_t apb2otp_block3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word3 Data */
-/** Type of apb2otp_blk3_w3 register
- *  eFuse apb2otp block3 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word3 data.
-         */
-        uint32_t apb2otp_block3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word4 Data */
-/** Type of apb2otp_blk3_w4 register
- *  eFuse apb2otp block3 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word4 data.
-         */
-        uint32_t apb2otp_block3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word5 Data */
-/** Type of apb2otp_blk3_w5 register
- *  eFuse apb2otp block3 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word5 data.
-         */
-        uint32_t apb2otp_block3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word6 Data */
-/** Type of apb2otp_blk3_w6 register
- *  eFuse apb2otp block3 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word6 data.
-         */
-        uint32_t apb2otp_block3_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word7 Data */
-/** Type of apb2otp_blk3_w7 register
- *  eFuse apb2otp block3 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word7 data.
-         */
-        uint32_t apb2otp_block3_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word8 Data */
-/** Type of apb2otp_blk3_w8 register
- *  eFuse apb2otp block3 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word8 data.
-         */
-        uint32_t apb2otp_block3_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word9 Data */
-/** Type of apb2otp_blk3_w9 register
- *  eFuse apb2otp block3 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word9 data.
-         */
-        uint32_t apb2otp_block3_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word10 Data */
-/** Type of apb2otp_blk3_w10 register
- *  eFuse apb2otp block3 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word10 data.
-         */
-        uint32_t apb2otp_block3_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word11 Data */
-/** Type of apb2otp_blk3_w11 register
- *  eFuse apb2otp block3 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word11 data.
-         */
-        uint32_t apb2otp_block3_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word1 Data */
-/** Type of apb2otp_blk4_w1 register
- *  eFuse apb2otp BLOCK7 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word1 data.
-         */
-        uint32_t apb2otp_block4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word2 Data */
-/** Type of apb2otp_blk4_w2 register
- *  eFuse apb2otp block4 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word2 data.
-         */
-        uint32_t apb2otp_block4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word3 Data */
-/** Type of apb2otp_blk4_w3 register
- *  eFuse apb2otp block4 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word3 data.
-         */
-        uint32_t apb2otp_block4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word4 Data */
-/** Type of apb2otp_blk4_w4 register
- *  eFuse apb2otp block4 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word4 data.
-         */
-        uint32_t apb2otp_block4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word5 Data */
-/** Type of apb2otp_blk4_w5 register
- *  eFuse apb2otp block4 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word5 data.
-         */
-        uint32_t apb2otp_block4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word6 Data */
-/** Type of apb2otp_blk4_w6 register
- *  eFuse apb2otp block4 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word6 data.
-         */
-        uint32_t apb2otp_block4_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word7 Data */
-/** Type of apb2otp_blk4_w7 register
- *  eFuse apb2otp block4 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word7 data.
-         */
-        uint32_t apb2otp_block4_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word8 Data */
-/** Type of apb2otp_blk4_w8 register
- *  eFuse apb2otp block4 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word8 data.
-         */
-        uint32_t apb2otp_block4_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word9 Data */
-/** Type of apb2otp_blk4_w9 register
- *  eFuse apb2otp block4 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word9 data.
-         */
-        uint32_t apb2otp_block4_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word10 Data */
-/** Type of apb2otp_blk4_w10 register
- *  eFuse apb2otp block4 data registe10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word10 data.
-         */
-        uint32_t apb2otp_block4_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word11 Data */
-/** Type of apb2otp_blk4_w11 register
- *  eFuse apb2otp block4 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word11 data.
-         */
-        uint32_t apb2otp_block4_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word1 Data */
-/** Type of apb2otp_blk5_w1 register
- *  eFuse apb2otp block5 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word1 data.
-         */
-        uint32_t apb2otp_block5_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word2 Data */
-/** Type of apb2otp_blk5_w2 register
- *  eFuse apb2otp block5 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word2 data.
-         */
-        uint32_t apb2otp_block5_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word3 Data */
-/** Type of apb2otp_blk5_w3 register
- *  eFuse apb2otp block5 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word3 data.
-         */
-        uint32_t apb2otp_block5_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word4 Data */
-/** Type of apb2otp_blk5_w4 register
- *  eFuse apb2otp block5 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word4 data.
-         */
-        uint32_t apb2otp_block5_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word5 Data */
-/** Type of apb2otp_blk5_w5 register
- *  eFuse apb2otp block5 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word5 data.
-         */
-        uint32_t apb2otp_block5_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word6 Data */
-/** Type of apb2otp_blk5_w6 register
- *  eFuse apb2otp block5 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word6 data.
-         */
-        uint32_t apb2otp_block5_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word7 Data */
-/** Type of apb2otp_blk5_w7 register
- *  eFuse apb2otp block5 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word7 data.
-         */
-        uint32_t apb2otp_block5_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word8 Data */
-/** Type of apb2otp_blk5_w8 register
- *  eFuse apb2otp block5 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word8 data.
-         */
-        uint32_t apb2otp_block5_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word9 Data */
-/** Type of apb2otp_blk5_w9 register
- *  eFuse apb2otp block5 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word9 data.
-         */
-        uint32_t apb2otp_block5_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word10 Data */
-/** Type of apb2otp_blk5_w10 register
- *  eFuse apb2otp block5 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word10 data.
-         */
-        uint32_t apb2otp_block5_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word11 Data */
-/** Type of apb2otp_blk5_w11 register
- *  eFuse apb2otp block5 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word11 data.
-         */
-        uint32_t apb2otp_block5_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word1 Data */
-/** Type of apb2otp_blk6_w1 register
- *  eFuse apb2otp block6 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word1 data.
-         */
-        uint32_t apb2otp_block6_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word2 Data */
-/** Type of apb2otp_blk6_w2 register
- *  eFuse apb2otp block6 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word2 data.
-         */
-        uint32_t apb2otp_block6_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word3 Data */
-/** Type of apb2otp_blk6_w3 register
- *  eFuse apb2otp block6 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word3 data.
-         */
-        uint32_t apb2otp_block6_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word4 Data */
-/** Type of apb2otp_blk6_w4 register
- *  eFuse apb2otp block6 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word4 data.
-         */
-        uint32_t apb2otp_block6_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word5 Data */
-/** Type of apb2otp_blk6_w5 register
- *  eFuse apb2otp block6 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word5 data.
-         */
-        uint32_t apb2otp_block6_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word6 Data */
-/** Type of apb2otp_blk6_w6 register
- *  eFuse apb2otp block6 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word6 data.
-         */
-        uint32_t apb2otp_block6_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word7 Data */
-/** Type of apb2otp_blk6_w7 register
- *  eFuse apb2otp block6 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word7 data.
-         */
-        uint32_t apb2otp_block6_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word8 Data */
-/** Type of apb2otp_blk6_w8 register
- *  eFuse apb2otp block6 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word8 data.
-         */
-        uint32_t apb2otp_block6_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word9 Data */
-/** Type of apb2otp_blk6_w9 register
- *  eFuse apb2otp block6 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word9 data.
-         */
-        uint32_t apb2otp_block6_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word10 Data */
-/** Type of apb2otp_blk6_w10 register
- *  eFuse apb2otp block6 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word10 data.
-         */
-        uint32_t apb2otp_block6_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word11 Data */
-/** Type of apb2otp_blk6_w11 register
- *  eFuse apb2otp block6 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word11 data.
-         */
-        uint32_t apb2otp_block6_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word1 Data */
-/** Type of apb2otp_blk7_w1 register
- *  eFuse apb2otp block7 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word1 data.
-         */
-        uint32_t apb2otp_block7_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word2 Data */
-/** Type of apb2otp_blk7_w2 register
- *  eFuse apb2otp block7 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word2 data.
-         */
-        uint32_t apb2otp_block7_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word3 Data */
-/** Type of apb2otp_blk7_w3 register
- *  eFuse apb2otp block7 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word3 data.
-         */
-        uint32_t apb2otp_block7_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word4 Data */
-/** Type of apb2otp_blk7_w4 register
- *  eFuse apb2otp block7 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word4 data.
-         */
-        uint32_t apb2otp_block7_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word5 Data */
-/** Type of apb2otp_blk7_w5 register
- *  eFuse apb2otp block7 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word5 data.
-         */
-        uint32_t apb2otp_block7_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word6 Data */
-/** Type of apb2otp_blk7_w6 register
- *  eFuse apb2otp block7 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word6 data.
-         */
-        uint32_t apb2otp_block7_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word7 Data */
-/** Type of apb2otp_blk7_w7 register
- *  eFuse apb2otp block7 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word7 data.
-         */
-        uint32_t apb2otp_block7_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word8 Data */
-/** Type of apb2otp_blk7_w8 register
- *  eFuse apb2otp block7 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word8 data.
-         */
-        uint32_t apb2otp_block7_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word9 Data */
-/** Type of apb2otp_blk7_w9 register
- *  eFuse apb2otp block7 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word9 data.
-         */
-        uint32_t apb2otp_block7_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word10 Data */
-/** Type of apb2otp_blk7_w10 register
- *  eFuse apb2otp block7 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word10 data.
-         */
-        uint32_t apb2otp_block7_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word11 Data */
-/** Type of apb2otp_blk7_w11 register
- *  eFuse apb2otp block7 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word11 data.
-         */
-        uint32_t apb2otp_block7_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word1 Data */
-/** Type of apb2otp_blk8_w1 register
- *  eFuse apb2otp block8 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word1 data.
-         */
-        uint32_t apb2otp_block8_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word2 Data */
-/** Type of apb2otp_blk8_w2 register
- *  eFuse apb2otp block8 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word2 data.
-         */
-        uint32_t apb2otp_block8_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word3 Data */
-/** Type of apb2otp_blk8_w3 register
- *  eFuse apb2otp block8 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word3 data.
-         */
-        uint32_t apb2otp_block8_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word4 Data */
-/** Type of apb2otp_blk8_w4 register
- *  eFuse apb2otp block8 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word4 data.
-         */
-        uint32_t apb2otp_block8_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word5 Data */
-/** Type of apb2otp_blk8_w5 register
- *  eFuse apb2otp block8 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word5 data.
-         */
-        uint32_t apb2otp_block8_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word6 Data */
-/** Type of apb2otp_blk8_w6 register
- *  eFuse apb2otp block8 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word6 data.
-         */
-        uint32_t apb2otp_block8_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word7 Data */
-/** Type of apb2otp_blk8_w7 register
- *  eFuse apb2otp block8 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word7 data.
-         */
-        uint32_t apb2otp_block8_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word8 Data */
-/** Type of apb2otp_blk8_w8 register
- *  eFuse apb2otp block8 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word8 data.
-         */
-        uint32_t apb2otp_block8_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word9 Data */
-/** Type of apb2otp_blk8_w9 register
- *  eFuse apb2otp block8 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word9 data.
-         */
-        uint32_t apb2otp_block8_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word10 Data */
-/** Type of apb2otp_blk8_w10 register
- *  eFuse apb2otp block8 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word10 data.
-         */
-        uint32_t apb2otp_block8_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word11 Data */
-/** Type of apb2otp_blk8_w11 register
- *  eFuse apb2otp block8 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word11 data.
-         */
-        uint32_t apb2otp_block8_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word1 Data */
-/** Type of apb2otp_blk9_w1 register
- *  eFuse apb2otp block9 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word1 data.
-         */
-        uint32_t apb2otp_block9_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word2 Data */
-/** Type of apb2otp_blk9_w2 register
- *  eFuse apb2otp block9 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word2 data.
-         */
-        uint32_t apb2otp_block9_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word3 Data */
-/** Type of apb2otp_blk9_w3 register
- *  eFuse apb2otp block9 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word3 data.
-         */
-        uint32_t apb2otp_block9_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word4 Data */
-/** Type of apb2otp_blk9_w4 register
- *  eFuse apb2otp block9 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word4 data.
-         */
-        uint32_t apb2otp_block9_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word5 Data */
-/** Type of apb2otp_blk9_w5 register
- *  eFuse apb2otp block9 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word5 data.
-         */
-        uint32_t apb2otp_block9_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word6 Data */
-/** Type of apb2otp_blk9_w6 register
- *  eFuse apb2otp block9 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word6 data.
-         */
-        uint32_t apb2otp_block9_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word7 Data */
-/** Type of apb2otp_blk9_w7 register
- *  eFuse apb2otp block9 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word7 data.
-         */
-        uint32_t apb2otp_block9_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word8 Data */
-/** Type of apb2otp_blk9_w8 register
- *  eFuse apb2otp block9 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word8 data.
-         */
-        uint32_t apb2otp_block9_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word9 Data */
-/** Type of apb2otp_blk9_w9 register
- *  eFuse apb2otp block9 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word9 data.
-         */
-        uint32_t apb2otp_block9_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word10 Data */
-/** Type of apb2otp_blk9_w10 register
- *  eFuse apb2otp block9 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word10 data.
-         */
-        uint32_t apb2otp_block9_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word11 Data */
-/** Type of apb2otp_blk9_w11 register
- *  eFuse apb2otp block9 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word11 data.
-         */
-        uint32_t apb2otp_block9_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word1 Data */
-/** Type of apb2otp_blk10_w1 register
- *  eFuse apb2otp block10 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word1 data.
-         */
-        uint32_t apb2otp_block10_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word2 Data */
-/** Type of apb2otp_blk10_w2 register
- *  eFuse apb2otp block10 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word2 data.
-         */
-        uint32_t apb2otp_block10_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word3 Data */
-/** Type of apb2otp_blk10_w3 register
- *  eFuse apb2otp block10 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word3 data.
-         */
-        uint32_t apb2otp_block10_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word4 Data */
-/** Type of apb2otp_blk10_w4 register
- *  eFuse apb2otp block10 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word4 data.
-         */
-        uint32_t apb2otp_block10_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word5 Data */
-/** Type of apb2otp_blk10_w5 register
- *  eFuse apb2otp block10 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word5 data.
-         */
-        uint32_t apb2otp_block10_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word6 Data */
-/** Type of apb2otp_blk10_w6 register
- *  eFuse apb2otp block10 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word6 data.
-         */
-        uint32_t apb2otp_block10_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word7 Data */
-/** Type of apb2otp_blk10_w7 register
- *  eFuse apb2otp block10 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word7 data.
-         */
-        uint32_t apb2otp_block10_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word8 Data */
-/** Type of apb2otp_blk10_w8 register
- *  eFuse apb2otp block10 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word8 data.
-         */
-        uint32_t apb2otp_block10_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word9 Data */
-/** Type of apb2otp_blk10_w9 register
- *  eFuse apb2otp block10 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word9 data.
-         */
-        uint32_t apb2otp_block10_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word10 Data */
-/** Type of apb2otp_blk10_w10 register
- *  eFuse apb2otp block10 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word10 data.
-         */
-        uint32_t apb2otp_block10_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Function Enable Signal */
-/** Type of apb2otp_en register
- *  eFuse apb2otp enable configuration register.
- */
-typedef union {
-    struct {
-        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
-         *  Apb2otp mode enable signal.
-         */
-        uint32_t apb2otp_apb2otp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} efuse_apb2otp_en_reg_t;
-
-
-typedef struct {
-    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
-    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
-    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
-    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
-    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
-    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
-    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
-    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
-    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
-    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
-    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
-    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
-    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
-    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
-    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
-    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
-    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
-    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
-    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
-    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
-    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
-    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
-    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
-    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
-    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
-    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
-    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
-    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
-    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
-    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
-    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
-    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
-    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
-    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
-    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
-    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
-    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
-    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
-    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
-    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
-    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
-    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
-    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
-    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
-    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
-    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
-    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
-    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
-    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
-    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
-    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
-    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
-    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
-    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
-    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
-    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
-    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
-    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
-    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
-    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
-    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
-    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
-    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
-    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
-    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
-    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
-    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
-    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
-    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
-    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
-    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
-    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
-    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
-    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
-    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
-    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
-    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
-    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
-    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
-    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
-    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
-    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
-    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
-    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
-    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
-    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
-    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
-    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
-    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
-    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
-    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
-    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
-    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
-    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
-    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
-    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
-    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
-    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
-    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
-    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
-    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
-    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
-    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
-    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
-    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
-    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
-    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
-    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
-    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
-    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
-    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
-    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
-    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
-    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
-    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
-    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
-    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
-    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
-    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
-    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
-    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
-    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
-    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
-    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
-    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
-    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
-    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
-    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
-    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
-    uint32_t reserved_704;
-    volatile efuse_apb2otp_en_reg_t apb2otp_en;
-} otp_debug_dev_t;
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
-    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
-    volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2;
-    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
-    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
-    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
-    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
-    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
-    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
-    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
-    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
-    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
-    volatile efuse_date_reg_t date;
-    uint32_t reserved_19c[11];
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
-    uint32_t reserved_1fc[193];
-    volatile otp_debug_dev_t otp_debug;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE;
-extern otp_debug_dev_t OTP_DEBUG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/interrupts.h b/components/soc/esp32c5/include/soc/interrupts.h
index f4411dfc34b..5eb272ae64f 100644
--- a/components/soc/esp32c5/include/soc/interrupts.h
+++ b/components/soc/esp32c5/include/soc/interrupts.h
@@ -58,7 +58,7 @@ typedef enum {
     ETS_HP_APM_M4_INTR_SOURCE,
     ETS_LP_APM0_INTR_SOURCE,
     ETS_MSPI_INTR_SOURCE,
-    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
+    ETS_I2S0_INTR_SOURCE,                       /**< interrupt of I2S0, level*/
     ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
     ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
     ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h
deleted file mode 100644
index edc9199d436..00000000000
--- a/components/soc/esp32c5/include/soc/lp_analog_peri_reg.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_ANA_BOD_MODE0_CNTL_REG register
- *  Configure brownout mode0
- */
-#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
-/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
- *  enable suspend spi when brownout interrupt or not
- *  1:enable
- *  0:disable
- */
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA    (BIT(6))
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M  (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S  6
-/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
- *  enable power down RF when brownout interrupt or not
- *  1:enable
- *  0:disable
- */
-#define LP_ANA_BOD_MODE0_PD_RF_ENA    (BIT(7))
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_M  (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_S  7
-/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
- *  set the undervoltage hold time for triggering brownout interrupt
- */
-#define LP_ANA_BOD_MODE0_INTR_WAIT    0x000003FFU
-#define LP_ANA_BOD_MODE0_INTR_WAIT_M  (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
-#define LP_ANA_BOD_MODE0_INTR_WAIT_V  0x000003FFU
-#define LP_ANA_BOD_MODE0_INTR_WAIT_S  8
-/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
- *  set the undervoltage hold time for triggering brownout reset
- */
-#define LP_ANA_BOD_MODE0_RESET_WAIT    0x000003FFU
-#define LP_ANA_BOD_MODE0_RESET_WAIT_M  (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
-#define LP_ANA_BOD_MODE0_RESET_WAIT_V  0x000003FFU
-#define LP_ANA_BOD_MODE0_RESET_WAIT_S  18
-/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
- *  clear brownout count or not
- *  1: clear
- *  0: no operation
- */
-#define LP_ANA_BOD_MODE0_CNT_CLR    (BIT(28))
-#define LP_ANA_BOD_MODE0_CNT_CLR_M  (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
-#define LP_ANA_BOD_MODE0_CNT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_CNT_CLR_S  28
-/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
- *  enable brownout interrupt or not
- *  1: enable
- *  0: disable
- */
-#define LP_ANA_BOD_MODE0_INTR_ENA    (BIT(29))
-#define LP_ANA_BOD_MODE0_INTR_ENA_M  (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
-#define LP_ANA_BOD_MODE0_INTR_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INTR_ENA_S  29
-/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
- *  select brownout reset level
- *  1: system reset
- *  0: chip reset
- */
-#define LP_ANA_BOD_MODE0_RESET_SEL    (BIT(30))
-#define LP_ANA_BOD_MODE0_RESET_SEL_M  (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
-#define LP_ANA_BOD_MODE0_RESET_SEL_V  0x00000001U
-#define LP_ANA_BOD_MODE0_RESET_SEL_S  30
-/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
- *  enable brownout reset or not
- *  1: enable
- *  0: disable
- */
-#define LP_ANA_BOD_MODE0_RESET_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_RESET_ENA_M  (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
-#define LP_ANA_BOD_MODE0_RESET_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_RESET_ENA_S  31
-
-/** LP_ANA_BOD_MODE1_CNTL_REG register
- *  Configure brownout mode1
- */
-#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
-/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
- *  enable brownout mode1 reset or not
- *  1: enable
- *  0: disable
- */
-#define LP_ANA_BOD_MODE1_RESET_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE1_RESET_ENA_M  (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
-#define LP_ANA_BOD_MODE1_RESET_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE1_RESET_ENA_S  31
-
-/** LP_ANA_CK_GLITCH_CNTL_REG register
- *  Configure power glitch
- */
-#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
-/** LP_ANA_PWR_GLITCH_RESET_ENA : R/W; bitpos: [30:27]; default: 0;
- *  enable powerglitch or not
- */
-#define LP_ANA_PWR_GLITCH_RESET_ENA    0x0000000FU
-#define LP_ANA_PWR_GLITCH_RESET_ENA_M  (LP_ANA_PWR_GLITCH_RESET_ENA_V << LP_ANA_PWR_GLITCH_RESET_ENA_S)
-#define LP_ANA_PWR_GLITCH_RESET_ENA_V  0x0000000FU
-#define LP_ANA_PWR_GLITCH_RESET_ENA_S  27
-/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
- *  reserved
- */
-#define LP_ANA_CK_GLITCH_RESET_ENA    (BIT(31))
-#define LP_ANA_CK_GLITCH_RESET_ENA_M  (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
-#define LP_ANA_CK_GLITCH_RESET_ENA_V  0x00000001U
-#define LP_ANA_CK_GLITCH_RESET_ENA_S  31
-
-/** LP_ANA_FIB_ENABLE_REG register
- *  configure FIB REG
- */
-#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
-/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
- *  configure analog fib by software
- */
-#define LP_ANA_ANA_FIB_ENA    0xFFFFFFFFU
-#define LP_ANA_ANA_FIB_ENA_M  (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
-#define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
-#define LP_ANA_ANA_FIB_ENA_S  0
-
-/** LP_ANA_INT_RAW_REG register
- *  interrpt raw register
- */
-#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
-/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  brownout mode0 interrupt raw register
- */
-#define LP_ANA_BOD_MODE0_INT_RAW    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_RAW_M  (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
-#define LP_ANA_BOD_MODE0_INT_RAW_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_RAW_S  31
-
-/** LP_ANA_INT_ST_REG register
- *  interrpt status register
- */
-#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
-/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
- *  brownout mode0 interrupt status register
- */
-#define LP_ANA_BOD_MODE0_INT_ST    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_ST_M  (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
-#define LP_ANA_BOD_MODE0_INT_ST_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_ST_S  31
-
-/** LP_ANA_INT_ENA_REG register
- *  interrpt enable register
- */
-#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
-/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  brownout mode0 interrupt enable register
- */
-#define LP_ANA_BOD_MODE0_INT_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_ENA_M  (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
-#define LP_ANA_BOD_MODE0_INT_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_ENA_S  31
-
-/** LP_ANA_INT_CLR_REG register
- *  interrpt clear register
- */
-#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
-/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
- *  brownout mode0 interrupt clear register
- */
-#define LP_ANA_BOD_MODE0_INT_CLR    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_CLR_M  (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
-#define LP_ANA_BOD_MODE0_INT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_CLR_S  31
-
-/** LP_ANA_LP_INT_RAW_REG register
- *  lp interrupt raw register
- */
-#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
-/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  brownout mode0 lp interrupt raw register
- */
-#define LP_ANA_BOD_MODE0_LP_INT_RAW    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_M  (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_S  31
-
-/** LP_ANA_LP_INT_ST_REG register
- *  lp interrupt status register
- */
-#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
-/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
- *  brownout mode0 lp interrupt status register
- */
-#define LP_ANA_BOD_MODE0_LP_INT_ST    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_ST_M  (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
-#define LP_ANA_BOD_MODE0_LP_INT_ST_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_ST_S  31
-
-/** LP_ANA_LP_INT_ENA_REG register
- *  lp interrupt enable register
- */
-#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
-/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  brownout mode0 lp interrupt enable register
- */
-#define LP_ANA_BOD_MODE0_LP_INT_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_M  (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_S  31
-
-/** LP_ANA_LP_INT_CLR_REG register
- *  lp interrupt clear register
- */
-#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
-/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  brownout mode0 lp interrupt clear register
- */
-#define LP_ANA_BOD_MODE0_LP_INT_CLR    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_M  (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_S  31
-
-/** LP_ANA_DATE_REG register
- *  version register
- */
-#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
-/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 36774528;
- *  version register
- */
-#define LP_ANA_LP_ANA_DATE    0x7FFFFFFFU
-#define LP_ANA_LP_ANA_DATE_M  (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
-#define LP_ANA_LP_ANA_DATE_V  0x7FFFFFFFU
-#define LP_ANA_LP_ANA_DATE_S  0
-/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  reserved
- */
-#define LP_ANA_CLK_EN    (BIT(31))
-#define LP_ANA_CLK_EN_M  (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
-#define LP_ANA_CLK_EN_V  0x00000001U
-#define LP_ANA_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/pmu_struct.h b/components/soc/esp32c5/include/soc/pmu_struct.h
deleted file mode 100644
index 67f6269fc32..00000000000
--- a/components/soc/esp32c5/include/soc/pmu_struct.h
+++ /dev/null
@@ -1,763 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include <stddef.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "soc.h"
-#include "soc/pmu_reg.h"
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 21;
-        uint32_t vdd_spi_pd_en: 1;
-        uint32_t mem_dslp     : 1;
-        uint32_t mem_pd_en    : 4;
-        uint32_t wifi_pd_en   : 1;
-        uint32_t reserved1    : 1;
-        uint32_t cpu_pd_en    : 1;
-        uint32_t aon_pd_en    : 1;
-        uint32_t top_pd_en    : 1;
-    };
-    uint32_t val;
-} pmu_hp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 30;
-        uint32_t code     : 2;
-    };
-    uint32_t val;
-} pmu_hp_icg_modem_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 24;
-        uint32_t uart_wakeup_en : 1;
-        uint32_t lp_pad_hold_all: 1;
-        uint32_t hp_pad_hold_all: 1;
-        uint32_t dig_pad_slp_sel: 1;
-        uint32_t dig_pause_wdt  : 1;
-        uint32_t dig_cpu_stall  : 1;
-        uint32_t reserved1      : 2;
-    };
-    uint32_t val;
-} pmu_hp_sys_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 26;
-        uint32_t i2c_iso_en   : 1;
-        uint32_t i2c_retention: 1;
-        uint32_t xpd_bb_i2c   : 1;
-        uint32_t xpd_bbpll_i2c: 1;
-        uint32_t xpd_bbpll    : 1;
-        uint32_t reserved1    : 1;
-    };
-    uint32_t val;
-} pmu_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_hp_bias_reg_t;
-
-typedef union {
-    struct {    /* HP: Active State */
-        uint32_t reserved0                            : 4;
-        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
-        uint32_t hp_modem2active_backup_modem_clk_code: 2;
-        uint32_t reserved1                            : 2;
-        uint32_t hp_active_retention_mode             : 1;
-        uint32_t hp_sleep2active_retention_en         : 1;
-        uint32_t hp_modem2active_retention_en         : 1;
-        uint32_t reserved2                            : 1;
-        uint32_t hp_sleep2active_backup_clk_sel       : 2;
-        uint32_t hp_modem2active_backup_clk_sel       : 2;
-        uint32_t hp_sleep2active_backup_mode          : 5;
-        uint32_t hp_modem2active_backup_mode          : 5;
-        uint32_t reserved4                            : 1;
-        uint32_t hp_sleep2active_backup_en            : 1;
-        uint32_t hp_modem2active_backup_en            : 1;
-        uint32_t reserved5                            : 1;
-    };
-    struct {    /* HP: Modem State */
-        uint32_t reserved6                            : 4;
-        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
-        uint32_t reserved7                            : 4;
-        uint32_t hp_modem_retention_mode              : 1;
-        uint32_t hp_sleep2modem_retention_en          : 1;
-        uint32_t reserved8                            : 2;
-        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
-        uint32_t reserved9                            : 4;
-        uint32_t hp_sleep2modem_backup_mode           : 5;
-        uint32_t reserved10                           : 4;
-        uint32_t hp_sleep2modem_backup_en             : 1;
-        uint32_t reserved11                           : 2;
-    };
-    struct {    /* HP: Sleep State */
-        uint32_t reserved12                           : 6;
-        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
-        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
-        uint32_t hp_sleep_retention_mode              : 1;
-        uint32_t reserved13                           : 1;
-        uint32_t hp_modem2sleep_retention_en          : 1;
-        uint32_t hp_active2sleep_retention_en         : 1;
-        uint32_t reserved14                           : 2;
-        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
-        uint32_t hp_active2sleep_backup_clk_sel       : 2;
-        uint32_t hp_modem2sleep_backup_mode           : 5;
-        uint32_t hp_active2sleep_backup_mode          : 5;
-        uint32_t hp_modem2sleep_backup_en             : 1;
-        uint32_t hp_active2sleep_backup_en            : 1;
-    };
-    uint32_t val;
-} pmu_hp_backup_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0       : 26;
-        uint32_t dig_sysclk_nodiv: 1;
-        uint32_t icg_sysclk_en   : 1;
-        uint32_t sysclk_slp_sel  : 1;
-        uint32_t icg_slp_sel     : 1;
-        uint32_t dig_sysclk_sel  : 2;
-    };
-    uint32_t val;
-} pmu_hp_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 3;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t slp_connect_en : 1;
-        uint32_t slp_mem_xpd    : 1;
-        uint32_t slp_logic_xpd  : 1;
-        uint32_t xpd            : 1;
-        uint32_t slp_mem_dbias  : 4;
-        uint32_t slp_logic_dbias: 4;
-        uint32_t dbias          : 5;
-    };
-    uint32_t val;
-} pmu_hp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 8;
-        uint32_t drv_b    : 24;
-    };
-    uint32_t val;
-} pmu_hp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_hp_xtal_reg_t;
-
-typedef struct pmu_hp_hw_regmap_t{
-    pmu_hp_dig_power_reg_t     dig_power;
-    uint32_t                   icg_func;
-    uint32_t                   icg_apb;
-    pmu_hp_icg_modem_reg_t     icg_modem;
-    pmu_hp_sys_cntl_reg_t      syscntl;
-    pmu_hp_clk_power_reg_t     clk_power;
-    pmu_hp_bias_reg_t          bias;
-    pmu_hp_backup_reg_t        backup;
-    uint32_t                   backup_clk;
-    pmu_hp_sysclk_reg_t        sysclk;
-    pmu_hp_regulator0_reg_t    regulator0;
-    pmu_hp_regulator1_reg_t    regulator1;
-    pmu_hp_xtal_reg_t          xtal;
-} pmu_hp_hw_regmap_t;
-
-/** */
-typedef union {
-    struct {
-        uint32_t reserved0: 21;
-        uint32_t slp_xpd  : 1;
-        uint32_t xpd	  : 1;
-        uint32_t slp_dbias: 4;
-        uint32_t dbias    : 5;
-    };
-    uint32_t val;
-} pmu_lp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 28;
-        uint32_t drv_b    : 4;
-    };
-    uint32_t val;
-} pmu_lp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_lp_xtal_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 30;
-        uint32_t mem_dslp  : 1;
-        uint32_t peri_pd_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0  : 28;
-        uint32_t xpd_xtal32k: 1;
-        uint32_t xpd_rc32k  : 1;
-        uint32_t xpd_fosc   : 1;
-        uint32_t pd_osc     : 1;
-    };
-    uint32_t val;
-} pmu_lp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_lp_bias_reg_t;
-
-typedef struct pmu_lp_hw_regmap_t{
-    pmu_lp_regulator0_reg_t    regulator0;
-    pmu_lp_regulator1_reg_t    regulator1;
-    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
-    pmu_lp_dig_power_reg_t     dig_power;
-    pmu_lp_clk_power_reg_t     clk_power;
-    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
-} pmu_lp_hw_regmap_t;
-
-
-typedef union {
-    struct {
-        uint32_t tie_low_global_bbpll_icg : 1;
-        uint32_t tie_low_global_xtal_icg  : 1;
-        uint32_t tie_low_i2c_retention    : 1;
-        uint32_t tie_low_xpd_bb_i2c       : 1;
-        uint32_t tie_low_xpd_bbpll_i2c    : 1;
-        uint32_t tie_low_xpd_bbpll        : 1;
-        uint32_t tie_low_xpd_xtal         : 1;
-        uint32_t reserved0                : 18;
-        uint32_t tie_high_global_bbpll_icg: 1;
-        uint32_t tie_high_global_xtal_icg : 1;
-        uint32_t tie_high_i2c_retention   : 1;
-        uint32_t tie_high_xpd_bb_i2c      : 1;
-        uint32_t tie_high_xpd_bbpll_i2c   : 1;
-        uint32_t tie_high_xpd_bbpll       : 1;
-        uint32_t tie_high_xpd_xtal        : 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 28;
-        uint32_t update_dig_icg_switch: 1;
-        uint32_t tie_low_icg_slp_sel  : 1;
-        uint32_t tie_high_icg_slp_sel : 1;
-        uint32_t update_dig_sysclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_sleep_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0             : 31;
-        uint32_t update_dig_icg_func_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_func_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 31;
-        uint32_t update_dig_icg_apb_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_apb_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 31;
-        uint32_t update_dig_icg_modem_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_modem_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 30;
-        uint32_t tie_low_lp_rootclk_sel : 1;
-        uint32_t tie_high_lp_rootclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_lp_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0               : 28;
-        uint32_t tie_high_lp_pad_hold_all: 1;
-        uint32_t tie_low_lp_pad_hold_all : 1;
-        uint32_t tie_high_hp_pad_hold_all: 1;
-        uint32_t tie_low_hp_pad_hold_all : 1;
-    };
-    uint32_t val;
-} pmu_imm_pad_hold_all_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 30;
-        uint32_t tie_high_i2c_iso_en: 1;
-        uint32_t tie_low_i2c_iso_en : 1;
-    };
-    uint32_t val;
-} pmu_imm_i2c_isolate_reg_t;
-
-typedef struct pmu_imm_hw_regmap_t{
-    pmu_imm_hp_clk_power_reg_t     clk_power;
-    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
-    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
-    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
-    pmu_imm_modem_icg_reg_t        modem_icg;
-    pmu_imm_lp_icg_reg_t           lp_icg;
-    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
-    pmu_imm_i2c_isolate_reg_t      i2c_iso;
-} pmu_imm_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 5;
-        uint32_t powerdown_timer: 9;
-        uint32_t powerup_timer  : 9;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 9;
-        uint32_t powerdown_timer: 7;
-        uint32_t powerup_timer  : 7;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_iso_wait_timer : 8;
-        uint32_t lp_rst_wait_timer : 8;
-        uint32_t hp_iso_wait_timer : 8;
-        uint32_t hp_rst_wait_timer : 8;
-    };
-    uint32_t val;
-} pmu_power_wait_timer2_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_reset   : 1;
-        uint32_t force_iso     : 1;
-        uint32_t force_pu      : 1;
-        uint32_t force_no_reset: 1;
-        uint32_t force_no_iso  : 1;
-        uint32_t force_pd      : 1;
-        uint32_t mask          : 5;     /* Invalid of lp peripherals */
-        uint32_t reserved0     : 16;    /* Invalid of lp peripherals */
-        uint32_t pd_mask       : 5;     /* Invalid of lp peripherals */
-    };
-    uint32_t val;
-} pmu_power_domain_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_mem_iso   : 4;
-        uint32_t force_hp_mem_pd    : 4;
-        uint32_t reserved0          : 16;
-        uint32_t force_hp_mem_no_iso: 4;
-        uint32_t force_hp_mem_pu    : 4;
-    };
-    uint32_t val;
-} pmu_power_memory_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t mem2_pd_mask: 5;
-        uint32_t mem1_pd_mask: 5;
-        uint32_t mem0_pd_mask: 5;
-        uint32_t reserved0   : 2;
-        uint32_t mem2_mask   : 5;
-        uint32_t mem1_mask   : 5;
-        uint32_t mem0_mask   : 5;
-    };
-    uint32_t val;
-} pmu_power_memory_mask_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_pad_no_iso_all: 1;
-        uint32_t force_hp_pad_iso_all   : 1;
-        uint32_t reserved0              : 30;
-    };
-    uint32_t val;
-} pmu_power_hp_pad_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 18;
-        uint32_t pwr_wait  : 11;
-        uint32_t pwr_sw    : 2;
-        uint32_t pwr_sel_sw: 1;
-    };
-    uint32_t val;
-} pmu_power_vdd_spi_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wait_xtal_stable: 16;
-        uint32_t wait_pll_stable : 16;
-    };
-    uint32_t val;
-} pmu_power_clk_wait_cntl_reg_t;
-
-typedef struct pmu_power_hw_regmap_t{
-    pmu_power_wait_timer0_reg_t    wait_timer0;
-    pmu_power_wait_timer1_reg_t    wait_timer1;
-    pmu_power_wait_timer2_reg_t    wait_timer2;
-    pmu_power_domain_cntl_reg_t    hp_pd[5];
-    pmu_power_domain_cntl_reg_t    lp_peri;
-    pmu_power_memory_cntl_reg_t    mem_cntl;
-    pmu_power_memory_mask_reg_t    mem_mask;
-    pmu_power_hp_pad_reg_t         hp_pad;
-    pmu_power_vdd_spi_cntl_reg_t   vdd_spi;
-    pmu_power_clk_wait_cntl_reg_t  clk_wait;
-} pmu_power_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t sleep_reject_ena: 31;
-        uint32_t slp_reject_en   : 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_min_slp_val: 8;
-        uint32_t hp_min_slp_val: 8;
-        uint32_t sleep_prt_sel : 2;
-        uint32_t reserved0     : 14;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl3_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0           : 31;
-        uint32_t slp_reject_cause_clr: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl4_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modem_wait_target : 20;
-        uint32_t reserved0         : 4;
-        uint32_t lp_ana_wait_target: 8;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl5_reg_t;
-
-typedef union {
-    struct {
-        uint32_t soc_wakeup_wait    : 20;
-        uint32_t reserved0          : 10;
-        uint32_t soc_wakeup_wait_cfg: 2;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl6_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 16;
-        uint32_t ana_wait_target: 16;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl7_reg_t;
-
-typedef struct pmu_wakeup_hw_regmap_t{
-    pmu_slp_wakeup_cntl0_reg_t     cntl0;
-    pmu_slp_wakeup_cntl1_reg_t     cntl1;
-    uint32_t                       cntl2;
-    pmu_slp_wakeup_cntl3_reg_t     cntl3;
-    pmu_slp_wakeup_cntl4_reg_t     cntl4;
-    pmu_slp_wakeup_cntl5_reg_t     cntl5;
-    pmu_slp_wakeup_cntl6_reg_t     cntl6;
-    pmu_slp_wakeup_cntl7_reg_t     cntl7;
-    uint32_t                       status0;
-    uint32_t                       status1;
-} pmu_wakeup_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t i2c_por_wait_target: 8;
-        uint32_t reserved0          : 24;
-    };
-    uint32_t val;
-} pmu_hp_clk_poweron_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modify_icg_cntl_wait: 8;
-        uint32_t switch_icg_cntl_wait: 8;
-        uint32_t reserved0           : 16;
-    };
-    uint32_t val;
-} pmu_hp_clk_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t por_done : 1;
-    };
-    uint32_t val;
-} pmu_por_status_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0     : 23;
-        uint32_t xpd_ckgen5g   : 1;
-        uint32_t xpd_tc5g_i2c  : 1;
-        uint32_t xpd_rx5g_i2c  : 1;
-        uint32_t perif_i2c_rstb: 1;
-        uint32_t xpd_perif_i2c : 1;
-        uint32_t xpd_txrf_i2c  : 1;
-        uint32_t xpd_rfrx_pbus : 1;
-        uint32_t xpd_ckgen_i2c : 1;
-        uint32_t xpd_pll_i2c   : 1;
-    };
-    uint32_t val;
-} pmu_rf_pwc_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 31;
-        uint32_t backup_sysclk_nodiv: 1;
-    };
-    uint32_t val;
-} pmu_backup_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 27;
-        uint32_t lp_cpu_exc: 1;
-        uint32_t sdio_idle : 1;
-        uint32_t sw        : 1;
-        uint32_t reject    : 1;
-        uint32_t wakeup    : 1;
-    };
-    uint32_t val;
-} pmu_hp_intr_reg_t;
-
-typedef struct pmu_hp_ext_hw_regmap_t{
-    pmu_hp_clk_poweron_reg_t   clk_poweron;
-    pmu_hp_clk_cntl_reg_t      clk_cntl;
-    pmu_por_status_reg_t       por_status;
-    pmu_rf_pwc_reg_t           rf_pwc;
-    pmu_backup_cfg_reg_t       backup_cfg;
-    pmu_hp_intr_reg_t          int_raw;
-    pmu_hp_intr_reg_t          int_st;
-    pmu_hp_intr_reg_t          int_ena;
-    pmu_hp_intr_reg_t          int_clr;
-} pmu_hp_ext_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0                : 20;
-        uint32_t lp_cpu_wakeup            : 1;
-        uint32_t modem_switch_active_end  : 1;
-        uint32_t sleep_switch_active_end  : 1;
-        uint32_t sleep_switch_modem_end   : 1;
-        uint32_t modem_switch_sleep_end   : 1;
-        uint32_t active_swtich_sleep_end  : 1;
-        uint32_t modem_switch_active_start: 1;
-        uint32_t sleep_switch_active_start: 1;
-        uint32_t sleep_switch_modem_start : 1;
-        uint32_t modem_switch_sleep_start : 1;
-        uint32_t active_switch_sleep_start: 1;
-        uint32_t sw_trigger               : 1;
-    };
-    uint32_t val;
-} pmu_lp_intr_reg_t;
-
-typedef union {
-    struct {
-        uint32_t waiti_rdy         : 1;
-        uint32_t stall_rdy         : 1;
-        uint32_t reserved0         : 16;
-        uint32_t force_stall       : 1;
-        uint32_t slp_waiti_flag_en : 1;
-        uint32_t slp_stall_flag_en : 1;
-        uint32_t slp_stall_wait    : 8;
-        uint32_t slp_stall_en      : 1;
-        uint32_t slp_reset_en      : 1;
-        uint32_t slp_bypass_intr_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_en: 16;
-        uint32_t reserved0: 15;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr1_reg_t;
-
-typedef struct pmu_lp_ext_hw_regmap_t{
-    pmu_lp_intr_reg_t          int_raw;
-    pmu_lp_intr_reg_t          int_st;
-    pmu_lp_intr_reg_t          int_ena;
-    pmu_lp_intr_reg_t          int_clr;
-    pmu_lp_cpu_pwr0_reg_t      pwr0;
-    pmu_lp_cpu_pwr1_reg_t      pwr1;
-} pmu_lp_ext_hw_regmap_t;
-
-typedef struct pmu_dev_t{
-    volatile pmu_hp_hw_regmap_t     hp_sys[3];
-    volatile pmu_lp_hw_regmap_t     lp_sys[2];
-    volatile pmu_imm_hw_regmap_t    imm;
-    volatile pmu_power_hw_regmap_t  power;
-    volatile pmu_wakeup_hw_regmap_t wakeup;
-    volatile pmu_hp_ext_hw_regmap_t hp_ext;
-    volatile pmu_lp_ext_hw_regmap_t lp_ext;
-
-    union {
-        struct {
-            uint32_t reserved0    : 30;
-            volatile uint32_t lp_trigger_hp: 1;
-            volatile uint32_t hp_trigger_lp: 1;
-        };
-        volatile uint32_t val;
-    } hp_lp_cpu_comm;
-
-    union {
-        struct {
-            uint32_t reserved0           : 31;
-            volatile uint32_t dig_regulator_en_cal: 1;
-        };
-        volatile uint32_t val;
-    } hp_regulator_cfg;
-
-    union {
-        struct {
-            uint32_t reserved0 : 11;
-            volatile uint32_t last_st   : 7;
-            volatile uint32_t target_st : 7;
-            volatile uint32_t current_st: 7;
-        };
-        volatile uint32_t val;
-    } main_state;
-
-    union {
-        struct {
-            uint32_t reserved0: 13;
-            volatile uint32_t backup_st: 5;
-            volatile uint32_t lp_pwr_st: 5;
-            volatile uint32_t hp_pwr_st: 9;
-        };
-        volatile uint32_t val;
-    } pwr_state;
-
-    union {
-        struct {
-            volatile uint32_t stable_xpd_bbpll : 1;
-            volatile uint32_t stable_xpd_xtal  : 1;
-            volatile uint32_t reserved0        : 13;
-            volatile uint32_t sysclk_slp_sel   : 1;
-            volatile uint32_t sysclk_sel       : 2;
-            volatile uint32_t sysclk_nodiv     : 1;
-            volatile uint32_t icg_sysclk_en    : 1;
-            volatile uint32_t icg_modem_switch : 1;
-            volatile uint32_t icg_modem_code   : 2;
-            volatile uint32_t icg_slp_sel      : 1;
-            volatile uint32_t icg_global_xtal  : 1;
-            volatile uint32_t icg_global_pll   : 1;
-            volatile uint32_t ana_i2c_iso_en   : 1;
-            volatile uint32_t ana_i2c_retention: 1;
-            volatile uint32_t ana_xpd_bb_i2c   : 1;
-            volatile uint32_t ana_xpd_bbpll_i2c: 1;
-            volatile uint32_t ana_xpd_bbpll    : 1;
-            volatile uint32_t ana_xpd_xtal     : 1;
-        };
-        volatile uint32_t val;
-    } clk_state0;
-
-    volatile uint32_t clk_state1;
-    volatile uint32_t clk_state2;
-
-    union {
-        struct {
-            uint32_t reserved0             : 31;
-            volatile uint32_t stable_vdd_spi_pwr_drv: 1;
-        };
-        volatile uint32_t val;
-    } vdd_spi_status;
-
-    union {
-        struct {
-            volatile uint32_t pmu_date: 31;
-            volatile uint32_t clk_en  : 1;
-        };
-        volatile uint32_t val;
-    } date;
-} pmu_dev_t;
-
-extern pmu_dev_t PMU;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pmu_dev_t) == 0x1ac, "Invalid size of pmu_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/reg_base.h b/components/soc/esp32c5/include/soc/reg_base.h
deleted file mode 100644
index 6197746bbd7..00000000000
--- a/components/soc/esp32c5/include/soc/reg_base.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-/**
- * @brief Peripheral 0 Modules
- *
- */
-#define DR_REG_UART0_BASE                         0x60000000
-#define DR_REG_UART1_BASE                         0x60001000
-#define DR_REG_SPIMEM0_BASE                       0x60002000
-#define DR_REG_SPIMEM1_BASE                       0x60003000
-#define DR_REG_I2C_BASE                           0x60004000
-#define DR_REG_UHCI_BASE                          0x60005000
-#define DR_REG_RMT_BASE                           0x60006000
-#define DR_REG_LEDC_BASE                          0x60007000
-#define DR_REG_TIMERG0_BASE                       0x60008000
-#define DR_REG_TIMERG1_BASE                       0x60009000
-#define DR_REG_SYSTIMER_BASE                      0x6000A000
-#define DR_REG_TWAI0_BASE                         0x6000B000
-#define DR_REG_I2S_BASE                           0x6000C000
-#define DR_REG_TWAI1_BASE                         0x6000D000
-#define DR_REG_APB_SARADC_BASE                    0x6000E000
-#define DR_REG_USB_SERIAL_JTAG_BASE               0x6000F000
-#define DR_REG_INTERRUPT_MATRIX_BASE              0x60010000
-#define DR_REG_INTERRUPT_CORE0_BASE               DR_REG_INTERRUPT_MATRIX_BASE
-#define DR_REG_PCNT_BASE                          0x60012000
-#define DR_REG_SOC_ETM_BASE                       0x60013000
-#define DR_REG_MCPWM_BASE                         0x60014000
-#define DR_REG_PARL_IO_BASE                       0x60015000
-#define DR_REG_PVT_MONITOR_BASE                   0x60019000
-#define DR_REG_PSRAM_MEM_MONITOR_BASE             0x6001A000
-
-/**
- * @brief Peripheral 1 Modules
- *
- */
-#define DR_REG_AHB_DMA_BASE                       0x60080000
-#define DR_REG_GPSPI2_BASE                        0x60081000
-#define DR_REG_BITSCRAMBLER_BASE                  0x60082000
-#define DR_REG_KEYMNG_BASE                        0x60087000
-#define DR_REG_AES_BASE                           0x60088000
-#define DR_REG_SHA_BASE                           0x60089000
-#define DR_REG_RSA_BASE                           0x6008A000
-#define DR_REG_ECC_MULT_BASE                      0x6008B000
-#define DR_REG_DS_BASE                            0x6008C000
-#define DR_REG_HMAC_BASE                          0x6008D000
-#define DR_REG_ECDSA_BASE                         0x6008E000
-
-/**
- * @brief HP Top Peripheral Modules
- *
- */
-#define DR_REG_IO_MUX_BASE                        0x60090000
-#define DR_REG_GPIO_BASE                          0x60091000
-#define DR_REG_GPIO_EXT_BASE                      0x60091e00
-#define DR_REG_MEM_MONITOR_BASE                   0x60092000
-#define DR_REG_PAU_BASE                           0x60093000
-#define DR_REG_HP_SYSTEM_BASE                     0x60095000
-#define DR_REG_PCR_BASE                           0x60096000
-#define DR_REG_TEE_BASE                           0x60098000
-#define DR_REG_HP_APM_BASE                        0x60099000
-#define DR_REG_LP_APM0_BASE                       0x60099800
-#define DR_REG_MISC_BASE                          0x6009F000
-
-/**
- * @brief Modem Module
- *
- */
-#define DR_REG_MODEM0_BASE                        0x600A0000
-#define DR_REG_MODEM1_BASE                        0x600AC000
-#define DR_REG_MODEM_PWR0_BASE                    0x600AD000
-#define DR_REG_MODEM_PWR1_BASE                    0x600AF000
-
-#define PWDET_CONF_REG                            0x600A0810
-#define DR_REG_I2C_ANA_MST_BASE                   0x600AF800
-#define IEEE802154_REG_BASE                       0x600A3000
-
-/**
- * @brief LP System (RTC) Modules
- *
- */
-#define DR_REG_PMU_BASE                           0x600B0000
-#define DR_REG_LP_CLKRST_BASE                     0x600B0400
-#define DR_REG_LP_TIMER_BASE                      0x600B0C00
-#define DR_REG_LP_AON_BASE                        0x600B1000
-#define DR_REG_LP_UART_BASE                       0x600B1400
-#define DR_REG_LP_I2C_BASE                        0x600B1800
-#define DR_REG_LP_WDT_BASE                        0x600B1C00
-#define DR_REG_LP_I2C_ANA_MST_BASE                0x600B2400
-#define DR_REG_LPPERI_BASE                        0x600B2800
-#define DR_REG_LP_ANA_BASE                        0x600B2C00
-#define DR_REG_HUK_BASE                           0x600B3000
-#define DR_REG_LP_TEE_BASE                        0x600B3400
-#define DR_REG_LP_APM_BASE                        0x600B3800
-#define DR_REG_LP_IO_MUX_BASE                     0x600B4000
-#define DR_REG_LP_GPIO_BASE                       0x600B4400
-#define DR_REG_EFUSE_BASE                         0x600B4800
-#define DR_REG_OTP_DEBUG_BASE                     0x600B4D00
-
-/**
- * @brief CPU Peripheral Modules
- *
- */
-#define DR_REG_TRACE_BASE                         0x600C0000
-#define DR_REG_ASSIST_DEBUG_BASE                  0x600C2000
-#define DR_REG_INTPRI_BASE                        0x600C5000
-#define DR_REG_CACHE_BASE                         0x600C8000  // CACHE_CONFIG/EXTMEM
-#define DR_REG_CLINT_M_BASE                       0x20000000
diff --git a/components/soc/esp32c5/include/soc/regi2c_saradc.h b/components/soc/esp32c5/include/soc/regi2c_saradc.h
index 120d51fc20d..7fa3ff46026 100644
--- a/components/soc/esp32c5/include/soc/regi2c_saradc.h
+++ b/components/soc/esp32c5/include/soc/regi2c_saradc.h
@@ -81,3 +81,19 @@
 #define ADC_SARADC2_EN_TOUT_ADDR            0x8
 #define ADC_SARADC2_EN_TOUT_ADDR_MSB        0x2
 #define ADC_SARADC2_EN_TOUT_ADDR_LSB        0x2
+
+#define POWER_GLITCH_DREF_VDET_PERIF         11
+#define POWER_GLITCH_DREF_VDET_PERIF_MSB     2
+#define POWER_GLITCH_DREF_VDET_PERIF_LSB     0
+
+#define POWER_GLITCH_DREF_VDET_VDDPST        11
+#define POWER_GLITCH_DREF_VDET_VDDPST_MSB    6
+#define POWER_GLITCH_DREF_VDET_VDDPST_LSB    4
+
+#define POWER_GLITCH_DREF_VDET_XTAL          12
+#define POWER_GLITCH_DREF_VDET_XTAL_MSB      2
+#define POWER_GLITCH_DREF_VDET_XTAL_LSB      0
+
+#define POWER_GLITCH_DREF_VDET_PLL           12
+#define POWER_GLITCH_DREF_VDET_PLL_MSB       6
+#define POWER_GLITCH_DREF_VDET_PLL_LSB       4
diff --git a/components/soc/esp32c5/include/soc/reset_reasons.h b/components/soc/esp32c5/include/soc/reset_reasons.h
index f86a798e289..8822b2573a5 100644
--- a/components/soc/esp32c5/include/soc/reset_reasons.h
+++ b/components/soc/esp32c5/include/soc/reset_reasons.h
@@ -23,7 +23,6 @@ extern "C" {
 #endif
 
 
-// TODO: [ESP32C5] IDF-8660 Check reset reasons for MP version
 /**
  * @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
  * @note refer to TRM: <Reset and Clock> chapter
diff --git a/components/soc/esp32c5/include/soc/retention_periph_defs.h b/components/soc/esp32c5/include/soc/retention_periph_defs.h
index 02002a7d0fe..768dddce2fa 100644
--- a/components/soc/esp32c5/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32c5/include/soc/retention_periph_defs.h
@@ -15,6 +15,7 @@ extern "C" {
 
 typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_MIN          = 0,
+    SLEEP_RETENTION_MODULE_NULL         = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
     SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 2,
@@ -37,6 +38,13 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_UART0        = 14,
     SLEEP_RETENTION_MODULE_UART1        = 15,
     SLEEP_RETENTION_MODULE_I2S0         = 16,
+    SLEEP_RETENTION_MODULE_ETM0         = 17,
+    SLEEP_RETENTION_MODULE_TEMP_SENSOR  = 18,
+    SLEEP_RETENTION_MODULE_PARLIO0      = 19,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 20,
+    SLEEP_RETENTION_MODULE_LEDC         = 21,
+    SLEEP_RETENTION_MODULE_PCNT0        = 22,
+    SLEEP_RETENTION_MODULE_MCPWM0       = 23,
 
     /* modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
@@ -49,6 +57,8 @@ typedef enum periph_retention_module {
 } periph_retention_module_t;
 
 typedef enum periph_retention_module_bitmap {
+    SLEEP_RETENTION_MODULE_BM_NULL = BIT(SLEEP_RETENTION_MODULE_NULL),
+
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
     SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM  = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
@@ -76,6 +86,13 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_UART0        = BIT(SLEEP_RETENTION_MODULE_UART0),
     SLEEP_RETENTION_MODULE_BM_UART1        = BIT(SLEEP_RETENTION_MODULE_UART1),
     SLEEP_RETENTION_MODULE_BM_I2S0         = BIT(SLEEP_RETENTION_MODULE_I2S0),
+    SLEEP_RETENTION_MODULE_BM_ETM0         = BIT(SLEEP_RETENTION_MODULE_ETM0),
+    SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR  = BIT(SLEEP_RETENTION_MODULE_TEMP_SENSOR),
+    SLEEP_RETENTION_MODULE_BM_PARLIO0      = BIT(SLEEP_RETENTION_MODULE_PARLIO0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
+    SLEEP_RETENTION_MODULE_BM_PCNT0        = BIT(SLEEP_RETENTION_MODULE_PCNT0),
+    SLEEP_RETENTION_MODULE_BM_MCPWM0       = BIT(SLEEP_RETENTION_MODULE_MCPWM0),
 
     SLEEP_RETENTION_MODULE_BM_GDMA_CH0     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
     SLEEP_RETENTION_MODULE_BM_GDMA_CH1     = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
@@ -97,6 +114,14 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_UART0       \
                                   | SLEEP_RETENTION_MODULE_BM_UART1       \
                                   | SLEEP_RETENTION_MODULE_BM_I2S0        \
+                                  | SLEEP_RETENTION_MODULE_BM_ETM0        \
+                                  | SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR \
+                                  | SLEEP_RETENTION_MODULE_BM_PARLIO0     \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC        \
+                                  | SLEEP_RETENTION_MODULE_BM_PCNT0       \
+                                  | SLEEP_RETENTION_MODULE_BM_MCPWM0      \
+                                  | SLEEP_RETENTION_MODULE_BM_NULL       \
                                   )
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32c5/include/soc/soc.h b/components/soc/esp32c5/include/soc/soc.h
index 7134121e4b5..23fae74732f 100644
--- a/components/soc/esp32c5/include/soc/soc.h
+++ b/components/soc/esp32c5/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 
@@ -21,7 +21,7 @@
 #define REG_I2S_BASE(i)                         (DR_REG_I2S_BASE)                        // only one I2S on C5
 #define REG_TIMG_BASE(i)                        (DR_REG_TIMERG0_BASE + (i) * 0x1000)     // TIMERG0 and TIMERG1
 #define REG_SPI_MEM_BASE(i)                     (DR_REG_SPIMEM0_BASE + (i) * 0x1000)     // SPIMEM0 and SPIMEM1
-#define REG_SPI_BASE(i)                         (DR_REG_GPSPI2_BASE)                     // only one GPSPI on C5
+#define REG_SPI_BASE(i)                         (DR_REG_SPI2_BASE)                       // only one GPSPI on C5
 #define REG_I2C_BASE(i)                         (DR_REG_I2C_BASE)                        // only one I2C on C5
 #define REG_MCPWM_BASE(i)                       (DR_REG_MCPWM_BASE)                      // only one MCPWM on C5
 #define REG_TWAI_BASE(i)                        (DR_REG_TWAI0_BASE + (i) * 0x2000)       // TWAI0 and TWAI1
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index 5badeefac16..bef7ab59eb8 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -191,6 +191,7 @@
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
 #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
+#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1   // Support sleep retention
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-C5 has 1 GPIO peripheral
@@ -265,7 +266,7 @@
 #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
 #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
 
-// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
 
 /*-------------------------- LP_I2C CAPS -------------------------------------*/
 // ESP32-C5 has 1 LP_I2C
@@ -278,7 +279,6 @@
 #define SOC_I2S_HW_VERSION_2        (1)
 #define SOC_I2S_SUPPORTS_ETM        (1)
 #define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
-// #define SOC_I2S_SUPPORTS_RX_RECOMB  (1) //TODO[C5] IDF-9966
 #define SOC_I2S_SUPPORTS_XTAL       (1)
 #define SOC_I2S_SUPPORTS_PLL_F160M  (1)
 #define SOC_I2S_SUPPORTS_PLL_F240M  (1)
@@ -293,12 +293,14 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_SUPPORT_SLEEP_RETENTION    (1)
 
 /*-------------------------- MMU CAPS ----------------------------------------*/
 #define SOC_MMU_PERIPH_NUM                    (1U)
@@ -320,6 +322,7 @@
 #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
 #define SOC_PCNT_SUPPORT_CLEAR_SIGNAL         1
 #define SOC_PCNT_SUPPORT_STEP_NOTIFY          1
+#define SOC_PCNT_SUPPORT_SLEEP_RETENTION      1  /*!< The sleep retention feature can help back up PCNT registers before sleep */
 
 /*--------------------------- RMT CAPS ---------------------------------------*/
 #define SOC_RMT_GROUPS                        1U /*!< One RMT group */
@@ -354,6 +357,7 @@
 #define SOC_MCPWM_SUPPORT_ETM                    1  ///< Support ETM (Event Task Matrix)
 #define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR       1  ///< Support event comparator (based on ETM)
 #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP         1  ///< Capture timer shares clock with other PWM timers
+#define SOC_MCPWM_SUPPORT_SLEEP_RETENTION        1  ///< Support back up registers before sleep
 
 /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
 // #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
@@ -369,6 +373,7 @@
 #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT     1  /*!< Support output RX clock to a GPIO */
 #define SOC_PARLIO_TRANS_BIT_ALIGN           1  /*!< Support bit alignment in transaction */
 #define SOC_PARLIO_TX_SIZE_BY_DMA            1   /*!< Transaction length is controlled by DMA instead of indicated by register */
+#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION   1   /*!< Support back up registers before sleep */
 
 /*--------------------------- MPI CAPS ---------------------------------------*/
 #define SOC_MPI_MEM_BLOCKS_NUM (4)
@@ -420,6 +425,7 @@
 #define SOC_SPI_SUPPORT_CD_SIG              1
 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+#define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
 #define SOC_SPI_SUPPORT_CLK_XTAL            1
 #define SOC_SPI_SUPPORT_CLK_PLL_F160M       1
 #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
@@ -494,6 +500,10 @@
 // #define SOC_EFUSE_DIS_ICACHE 1
 #define SOC_EFUSE_ECDSA_KEY 1
 
+/*-------------------------- Key Manager CAPS----------------------------*/
+#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY    1 /*!< Key manager responsible to deploy ECDSA key */
+#define SOC_KEY_MANAGER_FE_KEY_DEPLOY       1 /*!< Key manager responsible to deploy Flash Encryption key */
+
 /*-------------------------- Secure Boot CAPS----------------------------*/
 #define SOC_SECURE_BOOT_V2_ECC              1
 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
@@ -568,7 +578,6 @@
 
 #define SOC_PM_CPU_RETENTION_BY_SW                 (1)
 #define SOC_PM_MODEM_RETENTION_BY_REGDMA           (1)
-#define SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD     (1)
 #define SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN        (1)
 
 #define SOC_PM_PAU_LINK_NUM                 (5)
@@ -584,12 +593,18 @@
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
 #define SOC_CLK_LP_FAST_SUPPORT_XTAL              (1)     /*!< Support XTAL clock as the LP_FAST clock source */
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2           (1)     /*!< Support XTAL_D2 clock as the LP_FAST clock source */
+
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                   (1)
+#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION        (1)
+#define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN            (1)
 
 /*------------------------------------ WI-FI CAPS ------------------------------------*/
 #define SOC_WIFI_HW_TSF                     (1)    /*!< Support hardware TSF */
diff --git a/components/soc/esp32c5/include/soc/system_reg.h b/components/soc/esp32c5/include/soc/system_reg.h
index 06daf447132..939bf695f0b 100644
--- a/components/soc/esp32c5/include/soc/system_reg.h
+++ b/components/soc/esp32c5/include/soc/system_reg.h
@@ -7,6 +7,6 @@
 #include "soc/hp_system_reg.h"
 
 // TODO: IDF-5720
-#include "intpri_reg.h"
+#include "soc/intpri_reg.h"
 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
 #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
diff --git a/components/soc/esp32c5/include/soc/uart_struct.h b/components/soc/esp32c5/include/soc/uart_struct.h
deleted file mode 100644
index 1cc6ed2d323..00000000000
--- a/components/soc/esp32c5/include/soc/uart_struct.h
+++ /dev/null
@@ -1,1364 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
-         *  Represents the data UART $n read from FIFO.\\
-         *  Measurement unit: byte.
-         */
-        uint32_t rxfifo_rd_byte:32;
-    };
-    uint32_t val;
-} uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable UART receiver's timeout function.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  Configures the amount of time that the bus can remain idle before timeout.\\
-         *  Measurement unit: bit time (the time to transmit 1 bit).
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status of UART_RXFIFO_FULL_INT.
-         */
-        uint32_t rxfifo_full_int_raw:1;
-        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
-         *  The raw interrupt status of UART_TXFIFO_EMPTY_INT.
-         */
-        uint32_t txfifo_empty_int_raw:1;
-        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status of UART_PARITY_ERR_INT.
-         */
-        uint32_t parity_err_int_raw:1;
-        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status of UART_FRM_ERR_INT.
-         */
-        uint32_t frm_err_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt status of UART_RXFIFO_OVF_INT.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt status of UART_DSR_CHG_INT.
-         */
-        uint32_t dsr_chg_int_raw:1;
-        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt status of UART_CTS_CHG_INT.
-         */
-        uint32_t cts_chg_int_raw:1;
-        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt status of UART_BRK_DET_INT.
-         */
-        uint32_t brk_det_int_raw:1;
-        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt status of UART_RXFIFO_TOUT_INT.
-         */
-        uint32_t rxfifo_tout_int_raw:1;
-        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt status of UART_SW_XON_INT.
-         */
-        uint32_t sw_xon_int_raw:1;
-        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  UART_SW_XOFF_INT.
-         */
-        uint32_t sw_xoff_int_raw:1;
-        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw interrupt status of UART_GLITCH_DET_INT.
-         */
-        uint32_t glitch_det_int_raw:1;
-        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw interrupt status of UART_TX_BRK_DONE_INT.
-         */
-        uint32_t tx_brk_done_int_raw:1;
-        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw interrupt status of UART_TX_BRK_IDLE_DONE_INT.
-         */
-        uint32_t tx_brk_idle_done_int_raw:1;
-        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw interrupt status of UART_TX_DONE_INT.
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw interrupt status of UART_RS485_PARITY_ERR_INT.
-         */
-        uint32_t rs485_parity_err_int_raw:1;
-        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw interrupt status of UART_RS485_FRM_ERR_INT.
-         */
-        uint32_t rs485_frm_err_int_raw:1;
-        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw interrupt status of UART_RS485_CLASH_INT.
-         */
-        uint32_t rs485_clash_int_raw:1;
-        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw interrupt status of UART_AT_CMD_CHAR_DET_INT.
-         */
-        uint32_t at_cmd_char_det_int_raw:1;
-        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw interrupt status of UART_WAKEUP_INT.
-         */
-        uint32_t wakeup_int_raw:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status of UART_RXFIFO_FULL_INT.
-         */
-        uint32_t rxfifo_full_int_st:1;
-        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status of UART_TXFIFO_EMPTY_INT.
-         */
-        uint32_t txfifo_empty_int_st:1;
-        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status of UART_PARITY_ERR_INT.
-         */
-        uint32_t parity_err_int_st:1;
-        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status of UART_FRM_ERR_INT.
-         */
-        uint32_t frm_err_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked interrupt status of UART_RXFIFO_OVF_INT.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked interrupt status of UART_DSR_CHG_INT.
-         */
-        uint32_t dsr_chg_int_st:1;
-        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked interrupt status of UART_CTS_CHG_INT.
-         */
-        uint32_t cts_chg_int_st:1;
-        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked interrupt status of UART_BRK_DET_INT.
-         */
-        uint32_t brk_det_int_st:1;
-        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked interrupt status of UART_RXFIFO_TOUT_INT.
-         */
-        uint32_t rxfifo_tout_int_st:1;
-        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked interrupt status of UART_SW_XON_INT.
-         */
-        uint32_t sw_xon_int_st:1;
-        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked interrupt status of UART_SW_XOFF_INT.
-         */
-        uint32_t sw_xoff_int_st:1;
-        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked interrupt status of UART_GLITCH_DET_INT.
-         */
-        uint32_t glitch_det_int_st:1;
-        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked interrupt status of UART_TX_BRK_DONE_INT.
-         */
-        uint32_t tx_brk_done_int_st:1;
-        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked interrupt status of UART_TX_BRK_IDLE_DONE_INT.
-         */
-        uint32_t tx_brk_idle_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked interrupt status of UART_TX_DONE_INT.
-         */
-        uint32_t tx_done_int_st:1;
-        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked interrupt status of UART_RS485_PARITY_ERR_INT.
-         */
-        uint32_t rs485_parity_err_int_st:1;
-        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
-         *  The masked interrupt status of UART_RS485_FRM_ERR_INT.
-         */
-        uint32_t rs485_frm_err_int_st:1;
-        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
-         *  The masked interrupt status of UART_RS485_CLASH_INT.
-         */
-        uint32_t rs485_clash_int_st:1;
-        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
-         *  The masked interrupt status of UART_AT_CMD_CHAR_DET_INT.
-         */
-        uint32_t at_cmd_char_det_int_st:1;
-        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
-         *  The masked interrupt status of UART_WAKEUP_INT.
-         */
-        uint32_t wakeup_int_st:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable UART_RXFIFO_FULL_INT.
-         */
-        uint32_t rxfifo_full_int_ena:1;
-        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable UART_TXFIFO_EMPTY_INT.
-         */
-        uint32_t txfifo_empty_int_ena:1;
-        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable UART_PARITY_ERR_INT.
-         */
-        uint32_t parity_err_int_ena:1;
-        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to enable UART_FRM_ERR_INT.
-         */
-        uint32_t frm_err_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to enable UART_RXFIFO_OVF_INT.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to enable UART_DSR_CHG_INT.
-         */
-        uint32_t dsr_chg_int_ena:1;
-        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Write 1 to enable UART_CTS_CHG_INT.
-         */
-        uint32_t cts_chg_int_ena:1;
-        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Write 1 to enable UART_BRK_DET_INT.
-         */
-        uint32_t brk_det_int_ena:1;
-        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to enable UART_RXFIFO_TOUT_INT.
-         */
-        uint32_t rxfifo_tout_int_ena:1;
-        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to enable UART_SW_XON_INT.
-         */
-        uint32_t sw_xon_int_ena:1;
-        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Write 1 to enable UART_SW_XOFF_INT.
-         */
-        uint32_t sw_xoff_int_ena:1;
-        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Write 1 to enable UART_GLITCH_DET_INT.
-         */
-        uint32_t glitch_det_int_ena:1;
-        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Write 1 to enable UART_TX_BRK_DONE_INT.
-         */
-        uint32_t tx_brk_done_int_ena:1;
-        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Write 1 to enable UART_TX_BRK_IDLE_DONE_INT.
-         */
-        uint32_t tx_brk_idle_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Write 1 to enable UART_TX_DONE_INT.
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Write 1 to enable UART_RS485_PARITY_ERR_INT.
-         */
-        uint32_t rs485_parity_err_int_ena:1;
-        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
-         *  Write 1 to enable UART_RS485_FRM_ERR_INT.
-         */
-        uint32_t rs485_frm_err_int_ena:1;
-        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
-         *  Write 1 to enable UART_RS485_CLASH_INT.
-         */
-        uint32_t rs485_clash_int_ena:1;
-        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
-         *  Write 1 to enable UART_AT_CMD_CHAR_DET_INT.
-         */
-        uint32_t at_cmd_char_det_int_ena:1;
-        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
-         *  Write 1 to enable UART_WAKEUP_INT.
-         */
-        uint32_t wakeup_int_ena:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear UART_RXFIFO_FULL_INT.
-         */
-        uint32_t rxfifo_full_int_clr:1;
-        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear UART_TXFIFO_EMPTY_INT.
-         */
-        uint32_t txfifo_empty_int_clr:1;
-        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear UART_PARITY_ERR_INT.
-         */
-        uint32_t parity_err_int_clr:1;
-        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear UART_FRM_ERR_INT.
-         */
-        uint32_t frm_err_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear UART_RXFIFO_OVF_INT.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear UART_DSR_CHG_INT.
-         */
-        uint32_t dsr_chg_int_clr:1;
-        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear UART_CTS_CHG_INT.
-         */
-        uint32_t cts_chg_int_clr:1;
-        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
-         *  Write 1 to clear UART_BRK_DET_INT.
-         */
-        uint32_t brk_det_int_clr:1;
-        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
-         *  Write 1 to clear UART_RXFIFO_TOUT_INT.
-         */
-        uint32_t rxfifo_tout_int_clr:1;
-        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
-         *  Write 1 to clear UART_SW_XON_INT.
-         */
-        uint32_t sw_xon_int_clr:1;
-        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
-         *  Write 1 to clear UART_SW_XOFF_INT.
-         */
-        uint32_t sw_xoff_int_clr:1;
-        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
-         *  Write 1 to clear UART_GLITCH_DET_INT.
-         */
-        uint32_t glitch_det_int_clr:1;
-        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  Write 1 to clear UART_TX_BRK_DONE_INT.
-         */
-        uint32_t tx_brk_done_int_clr:1;
-        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  Write 1 to clear UART_TX_BRK_IDLE_DONE_INT.
-         */
-        uint32_t tx_brk_idle_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  Write 1 to clear UART_TX_DONE_INT.
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
-         *  Write 1 to clear UART_RS485_PARITY_ERR_INT.
-         */
-        uint32_t rs485_parity_err_int_clr:1;
-        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
-         *  Write 1 to clear UART_RS485_FRM_ERR_INT.
-         */
-        uint32_t rs485_frm_err_int_clr:1;
-        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
-         *  Write 1 to clear UART_RS485_CLASH_INT.
-         */
-        uint32_t rs485_clash_int_clr:1;
-        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
-         *  Write 1 to clear UART_AT_CMD_CHAR_DET_INT.
-         */
-        uint32_t at_cmd_char_det_int_clr:1;
-        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
-         *  Write 1 to clear UART_WAKEUP_INT.
-         */
-        uint32_t wakeup_int_clr:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
-         *  Configures the integral part of the divisor for baud rate generation.
-         */
-        uint32_t clkdiv_int:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  Configures the fractional part of the divisor for baud rate generation.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  RX filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's
-         *  clock cycle.\\Pulses whose width is lower than this value will be ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable RX signal filter.\\
-         *  0: Disable\\
-         *  1: Enable
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  Configuration register 0
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  Configures the parity check mode.\\
-         *  0: Even parity\\
-         *  1: Odd parity\\
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable UART parity check.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  Configures the number of data bits.\\
-         *  0: 5 bits\\
-         *  1: 6 bits\\
-         *  2: 7 bits\\
-         *  3: 8 bits\\
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  Configures the number of stop bits.\\
-         *  0: Invalid. No effect\\
-         *  1: 1 bits\\
-         *  2: 1.5 bits\\
-         *  3: 2 bits\\
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to send NULL characters when finishing data
-         *  transmission.\\
-         *  0: Not send\\
-         *  1: Send\\
-         */
-        uint32_t txd_brk:1;
-        /** irda_dplx : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable IrDA loopback test.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t irda_dplx:1;
-        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable the IrDA transmitter.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t irda_tx_en:1;
-        /** irda_wctl : R/W; bitpos: [9]; default: 0;
-         *  Configures the 11th bit of the IrDA transmitter.\\
-         *  0: This bit is 0.\\
-         *  1: This bit is the same as the 10th bit.\\
-         */
-        uint32_t irda_wctl:1;
-        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to invert the level of the IrDA transmitter.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t irda_tx_inv:1;
-        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert the level of the IrDA receiver.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t irda_rx_inv:1;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable UART loopback test.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable flow control for the transmitter.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t tx_flow_en:1;
-        /** irda_en : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable IrDA protocol.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t irda_en:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to invert the level of UART RXD signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to invert the level of UART TXD signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to disable data overflow detection for the UART
-         *  receiver.\\
-         *  0: Enable\\
-         *  1: Disable\\
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to store the received data with errors into FIFO.\\
-         *  0: Store\\
-         *  1: Not store\\
-         */
-        uint32_t err_wr_mask:1;
-        /** autobaud_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable baud rate detection.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t autobaud_en:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable clock gating for UART memory.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  Configures the RTS signal used in software flow control.\\
-         *  0: The UART transmitter is allowed to send data.\\
-         *  1: The UART transmitted is not allowed to send data.\\
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Configures whether or not to reset the UART RX FIFO.\\
-         *  0: Not reset\\
-         *  1: Reset\\
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Configures whether or not to reset the UART TX FIFO.\\
-         *  0: Not reset\\
-         *  1: Reset\\
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
-         *  Configures the threshold for RX FIFO being full.\\Measurement unit: byte.
-         */
-        uint32_t rxfifo_full_thrhd:8;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
-         *  Configures the threshold for TX FIFO being empty.\\Measurement unit: byte.
-         */
-        uint32_t txfifo_empty_thrhd:8;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to invert the level of UART CTS signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to invert the level of UART DSR signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to invert the level of UART RTS signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to invert the level of UART DTR signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  Configures the DTR signal used in software flow control.\\
-         *  0: Data to be transmitted is not ready.\\
-         *  1: Data to be transmitted is ready.\\
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  Configures clock gating.\\
-         *  0: Support clock only when the application writes registers.\\
-         *  1: Always force the clock on for registers.\\
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow control configuration
- */
-typedef union {
-    struct {
-        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the maximum number of data bytes that can be received  during hardware
-         *  flow control.\\Measurement unit: byte.
-         */
-        uint32_t rx_flow_thrhd:8;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable the UART receiver.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configuration register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  Configures wakeup character 1.
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  Configures wakeup character 2.
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  Configures wakeup character 3.
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  Configures wakeup character 4.
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configuration register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  Configures wakeup character 0.
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configuration register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  Configures the number of RXD edge changes to wake up the chip in wakeup mode 0.
-         */
-        uint32_t active_threshold:10;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
-         *  Configures the number of received data bytes to wake up the chip in wakeup mode 1.
-         */
-        uint32_t rx_wake_up_thrhd:8;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  Configures the number of wakeup characters.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  Configures whether or not to mask wakeup characters.\\
-         *  0: Not mask\\
-         *  1: Mask\\
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  Configures which wakeup mode to select.\\
-         *  0: Mode 0\\
-         *  1: Mode 1\\
-         *  2: Mode 2\\
-         *  3: Mode 3\\
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  Configures the XON character for flow control.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  Configures the XOFF character for flow control.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  Configures whether the UART transmitter can send XON or XOFF characters when it is
-         *  disabled.\\
-         *  0: Cannot send\\
-         *  1: Can send\\
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable software flow control.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to remove flow control characters from the received
-         *  data.\\
-         *  0: Not move\\
-         *  1: Move\\
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Configures whether the transmitter continues to sending data.\\
-         *  0: Not send\\
-         *  1: Send\\
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to stop the transmitter from sending data.\\
-         *  0: Not stop\\
-         *  1: Stop\\
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Configures whether or not to send XON characters.\\
-         *  0: Not send\\
-         *  1: Send\\
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Configures whether or not to send XOFF characters.\\
-         *  0: Not send\\
-         *  1: Send\\
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow control character configuration
- */
-typedef union {
-    struct {
-        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the threshold for data in RX FIFO to send XON characters in software
-         *  flow control.\\Measurement unit: byte.
-         */
-        uint32_t xon_threshold:8;
-        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
-         *  Configures the threshold for data in RX FIFO to send XOFF characters in software
-         *  flow control.\\Measurement unit: byte.
-         */
-        uint32_t xoff_threshold:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  TX break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  Configures the number of NULL characters to be sent after finishing data
-         *  transmission.\\Valid only when UART_TXD_BRK is 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame end idle time configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  Configures the threshold to generate a frame end signal when the receiver takes
-         *  more time to receive one data byte data.\\Measurement unit: bit time (the time to
-         *  transmit 1 bit).
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  Configures the interval between two data transfers.\\Measurement unit: bit time
-         *  (the time to transmit 1 bit).
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        /** rs485_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable RS485 mode.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rs485_en:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\
-         *  0: Not add\\
-         *  1: Add\\
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\
-         *  0: Not add\\
-         *  1: Add\\
-         */
-        uint32_t dl1_en:1;
-        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable the receiver for data reception when the
-         *  transmitter is transmitting data in RS485 mode.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rs485tx_rx_en:1;
-        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether to enable the RS485 transmitter for data transmission when the
-         *  RS485 receiver is busy.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rs485rxby_tx_en:1;
-        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
-         *  Configures the delay of internal data signals in the receiver.\\Measurement unit:
-         *  bit time (the time to transmit 1 bit)..
-         */
-        uint32_t rs485_rx_dly_num:1;
-        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
-         *  Configures the delay of internal data signals in the transmitter.\\Measurement
-         *  unit: bit time (the time to transmit 1 bit).
-         */
-        uint32_t rs485_tx_dly_num:4;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rs485_conf_sync_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor.'
-         *  Only available to LP UART instance
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor.
-         *  Only available to LP UART instance
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor.
-         *  Only available to LP UART instance
-         */
-        uint32_t sclk_div_num:8;
-        uint32_t reserved_20:4;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Configures whether or not to enable UART TX clock.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Configures whether or not to enable UART RX clock.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 and then write 0 to reset UART TX.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 and then write 0 to reset UART RX.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
-         *  Represents the number of valid data bytes in RX FIFO.
-         */
-        uint32_t rxfifo_cnt:8;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  Represents the level of the internal UART DSR signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  Represents the level of the internal UART CTS signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  Represents the  level of the internal UART RXD signal.
-         */
-        uint32_t rxd:1;
-        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
-         *  Represents the number of valid data bytes in RX FIFO.
-         */
-        uint32_t txfifo_cnt:8;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  Represents the level of the internal UART DTR signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  Represents the level of the internal UART RTS signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  Represents the  level of the internal UART TXD signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  TX FIFO write and read offset address
- */
-typedef union {
-    struct {
-        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
-         *  Represents the offset address to write TX FIFO.
-         */
-        uint32_t tx_sram_waddr:8;
-        uint32_t reserved_8:1;
-        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
-         *  Represents the offset address to read TX FIFO.
-         */
-        uint32_t tx_sram_raddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx FIFO write and read offset address
- */
-typedef union {
-    struct {
-        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
-         *  Represents the offset address to read RX FIFO.
-         */
-        uint32_t rx_sram_raddr:8;
-        uint32_t reserved_8:1;
-        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
-         *  Represents the offset address to write RX FIFO.
-         */
-        uint32_t rx_sram_waddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  Represents the status of the receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  Represents the status of the transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART asynchronous FIFO status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not the APB TX asynchronous FIFO is full.\\
-         *  0: Not full\\
-         *  1: Full\\
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Represents whether or not the APB TX asynchronous FIFO is empty.\\
-         *  0: Not empty\\
-         *  1: Empty\\
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Represents whether or not the APB RX asynchronous FIFO is full.\\
-         *  0: Not full\\
-         *  1: Full\\
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Represents whether or not the APB RX asynchronous FIFO is empty.\\
-         *  0: Not empty\\
-         *  1: Empty\\
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  Configures the idle time before the receiver receives the first
-         *  AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit).
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  Configures the interval between the last AT_CMD and subsequent data.\\Measurement
-         *  unit: bit time (the time to transmit 1 bit).
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  Configures the interval between two AT_CMD characters.\\Measurement unit: bit time
-         *  (the time to transmit 1 bit).
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
-         *  Configures the AT_CMD character.
-         */
-        uint32_t at_cmd_char:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  Configures the number of continuous AT_CMD characters a receiver can receive.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Autobaud Register */
-/** Type of pospulse register
- *  Autobaud high pulse register
- */
-typedef union {
-    struct {
-        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  Represents the minimal input clock counter value between two positive edges. It is
-         *  used for baud rate detection.
-         */
-        uint32_t posedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_pospulse_reg_t;
-
-/** Type of negpulse register
- *  Autobaud low pulse register
- */
-typedef union {
-    struct {
-        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  Represents the minimal input clock counter value between two negative edges. It is
-         *  used for baud rate detection.
-         */
-        uint32_t negedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_negpulse_reg_t;
-
-/** Type of lowpulse register
- *  Autobaud minimum low pulse duration register
- */
-typedef union {
-    struct {
-        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  Represents the minimum duration time of a low-level pulse. It is used for baud rate
-         *  detection.\\Measurement unit: APB_CLK clock cycle.
-         */
-        uint32_t lowpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_lowpulse_reg_t;
-
-/** Type of highpulse register
- *  Autobaud minimum high pulse duration register
- */
-typedef union {
-    struct {
-        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  Represents  the maximum duration time for a high-level pulse. It is used for baud
-         *  rate detection.\\Measurement unit: APB_CLK clock cycle.
-         */
-        uint32_t highpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_highpulse_reg_t;
-
-/** Type of rxd_cnt register
- *  Autobaud edge change count register
- */
-typedef union {
-    struct {
-        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
-         *  Represents the number of RXD edge changes. It is used for baud rate detection.
-         */
-        uint32_t rxd_edge_cnt:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rxd_cnt_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 36774432;
-         *  Version control register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART register configuration update
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Configures whether or not to synchronize registers.\\
-         *  0: Not synchronize\\
-         *  1: Synchronize\\
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  Configures the UART ID.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} uart_id_reg_t;
-
-
-typedef struct {
-    volatile uart_fifo_reg_t fifo;
-    volatile uart_int_raw_reg_t int_raw;
-    volatile uart_int_st_reg_t int_st;
-    volatile uart_int_ena_reg_t int_ena;
-    volatile uart_int_clr_reg_t int_clr;
-    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile uart_rx_filt_reg_t rx_filt;
-    volatile uart_status_reg_t status;
-    volatile uart_conf0_sync_reg_t conf0_sync;
-    volatile uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile uart_sleep_conf0_reg_t sleep_conf0;
-    volatile uart_sleep_conf1_reg_t sleep_conf1;
-    volatile uart_sleep_conf2_reg_t sleep_conf2;
-    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile uart_swfc_conf1_reg_t swfc_conf1;
-    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile uart_mem_conf_reg_t mem_conf;
-    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile uart_mem_tx_status_reg_t mem_tx_status;
-    volatile uart_mem_rx_status_reg_t mem_rx_status;
-    volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;
-    volatile uart_negpulse_reg_t negpulse;
-    volatile uart_lowpulse_reg_t lowpulse;
-    volatile uart_highpulse_reg_t highpulse;
-    volatile uart_rxd_cnt_reg_t rxd_cnt;
-    volatile uart_clk_conf_reg_t clk_conf;
-    volatile uart_date_reg_t date;
-    volatile uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile uart_reg_update_reg_t reg_update;
-    volatile uart_id_reg_t id;
-} uart_dev_t;
-
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-extern uart_dev_t LP_UART;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h
deleted file mode 100644
index 5a8b1d4a06f..00000000000
--- a/components/soc/esp32c5/include/soc/usb_serial_jtag_reg.h
+++ /dev/null
@@ -1,1228 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** USB_SERIAL_JTAG_EP1_REG register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
- *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
- *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
- *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
- *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
- *  how many data is received, then read data from UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
- *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
- */
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
-#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
- *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
- *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
- *  USB Host.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
- *  1'b1: Indicate there is data in UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- *  Interrupt raw status register.
- */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when flush cmd is received for IN
- *  endpoint 2 of JTAG.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when SOF frame is received.
- */
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- *  one packet.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
- *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when pid error is detected.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt bit turns to high level when CRC5 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt bit turns to high level when CRC16 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt bit turns to high level when stuff error is detected.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
- *  received.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt bit turns to high level when usb bus reset is detected.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
-
-/** USB_SERIAL_JTAG_INT_ST_REG register
- *  Interrupt status register.
- */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
-
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- *  Interrupt enable status register.
- */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
-
-/** USB_SERIAL_JTAG_INT_CLR_REG register
- *  Interrupt clear status register.
- */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
-
-/** USB_SERIAL_JTAG_CONF0_REG register
- *  PHY hardware configuration.
- */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  Select internal/external PHY
- */
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
- *  Enable software control USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
- *  USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
- *  Control single-end input high threshold,1.76V to 2V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFH    0x00000003U
-#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
-#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFH_S  3
-/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
- *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFL    0x00000003U
-#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
-#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFL_S  5
-/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
- *  Enable software control input  threshold
- */
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
- *  Enable software control USB D+ D- pullup pulldown
- */
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
- *  Control USB D+ pull up.
- */
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
- *  Control USB D+ pull down.
- */
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
- *  Control USB D- pull up.
- */
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
- *  Control USB D- pull down.
- */
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
- *  Control pull up value.
- */
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
- *  Enable USB pad function.
- */
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
- *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
- *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
- *  through GPIO Matrix.
- */
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
-
-/** USB_SERIAL_JTAG_TEST_REG register
- *  Registers used for debugging the PHY.
- */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
-/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Enable test of the USB pad
- */
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad one in test
- */
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- *  USB D+ tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- *  USB D- tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
- *  USB RCV value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
-#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
-/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
- *  USB D+ rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
-#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
-/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
- *  USB D- rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
-#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
-
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- *  JTAG FIFO status and control registers.
- */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
- *  JTAT in fifo counter.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- *  1: JTAG in fifo is empty.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
- *  1: JTAG in fifo is full.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
- *  JTAT out fifo counter.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
- *  1: JTAG out fifo is empty.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
- *  1: JTAG out fifo is full.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
- *  Write 1 to reset JTAG in fifo.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
- *  Write 1 to reset JTAG out fifo.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- *  Last received SOF frame index register.
- */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
- *  Frame index of received SOF frame.
- */
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- *  Control IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- *  CDC-ACM IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
-/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- *  JTAG IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- *  Control OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- *  CDC-ACM OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
-/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
- *  Data count in OUT endpoint 1 when one packet is received.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- *  JTAG OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- *  Clock enable control
- */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
-#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- *  Memory power control
- */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  1: power down usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  1: Force clock on for usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-
-/** USB_SERIAL_JTAG_CHIP_RST_REG register
- *  CDC-ACM chip reset control.
- */
-#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
-/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
- *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_RTS    (BIT(0))
-#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
-#define USB_SERIAL_JTAG_RTS_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_S  0
-/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
- *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_DTR    (BIT(1))
-#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
-#define USB_SERIAL_JTAG_DTR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_S  1
-/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
- *  Set this bit to disable chip reset from usb serial channel to reset chip.
- */
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
- *  W0 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
-/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
- *  W1 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
-/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
-/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_S  16
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
- *  W0 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
-/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
- *  W1 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
-/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
-/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
-
-/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
- *  Configuration registers' value update
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
-/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
- *  Write 1 to this register would update the value of configure registers from APB
- *  clock domain to 48MHz clock domain.
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
-
-/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
- *  Serial AFIFO configure register
- */
-#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
- *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
-
-/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
- *  USB Bus reset status register
- */
-#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
-/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
- *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
- *  reset is released.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
-
-/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG register
- *  USB uart out endpoint timeout configuration.
- */
-#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
-/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN : R/W; bitpos: [0]; default: 0;
- *  USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
- *  is automatically cleared and reg_serial_timeout_status is asserted.
- */
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S)
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S  0
-/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS : R/WTC/SS; bitpos: [1]; default: 0;
- *  Serial out ep triggers a timeout event.
- */
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S)
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S  1
-/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear reg_serial_timeout_status.
- */
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S  2
-
-/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG register
- *  USB uart out endpoint timeout configuration.
- */
-#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
-/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX : R/W; bitpos: [31:0]; default: 4800768;
- *  USB serial out ep timeout max threshold value, indicates the maximum time that
- *  waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
- */
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S)
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S  0
-
-/** USB_SERIAL_JTAG_DATE_REG register
- *  Date register
- */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368;
- *  register version.
- */
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
deleted file mode 100644
index 21e8d68b209..00000000000
--- a/components/soc/esp32c5/include/soc/usb_serial_jtag_struct.h
+++ /dev/null
@@ -1,979 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of ep1 register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-typedef union {
-    struct {
-        /** rdwr_byte : R/W; bitpos: [7:0]; default: 0;
-         *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
-         *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
-         *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
-         *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
-         *  how many data is received, then read data from UART Rx FIFO.
-         */
-        uint32_t rdwr_byte:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_ep1_reg_t;
-
-/** Type of ep1_conf register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-typedef union {
-    struct {
-        /** wr_done : WT; bitpos: [0]; default: 0;
-         *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
-         */
-        uint32_t wr_done:1;
-        /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
-         *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
-         *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
-         *  USB Host.
-         */
-        uint32_t serial_in_ep_data_free:1;
-        /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
-         *  1'b1: Indicate there is data in UART Rx FIFO.
-         */
-        uint32_t serial_out_ep_data_avail:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} usb_serial_jtag_ep1_conf_reg_t;
-
-/** Type of conf0 register
- *  PHY hardware configuration.
- */
-typedef union {
-    struct {
-        /** phy_sel : R/W; bitpos: [0]; default: 0;
-         *  Select internal/external PHY
-         */
-        uint32_t phy_sel:1;
-        /** exchg_pins_override : R/W; bitpos: [1]; default: 0;
-         *  Enable software control USB D+ D- exchange
-         */
-        uint32_t exchg_pins_override:1;
-        /** exchg_pins : R/W; bitpos: [2]; default: 0;
-         *  USB D+ D- exchange
-         */
-        uint32_t exchg_pins:1;
-        /** vrefh : R/W; bitpos: [4:3]; default: 0;
-         *  Control single-end input high threshold,1.76V to 2V, step 80mV
-         */
-        uint32_t vrefh:2;
-        /** vrefl : R/W; bitpos: [6:5]; default: 0;
-         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
-         */
-        uint32_t vrefl:2;
-        /** vref_override : R/W; bitpos: [7]; default: 0;
-         *  Enable software control input  threshold
-         */
-        uint32_t vref_override:1;
-        /** pad_pull_override : R/W; bitpos: [8]; default: 0;
-         *  Enable software control USB D+ D- pullup pulldown
-         */
-        uint32_t pad_pull_override:1;
-        /** dp_pullup : R/W; bitpos: [9]; default: 1;
-         *  Control USB D+ pull up.
-         */
-        uint32_t dp_pullup:1;
-        /** dp_pulldown : R/W; bitpos: [10]; default: 0;
-         *  Control USB D+ pull down.
-         */
-        uint32_t dp_pulldown:1;
-        /** dm_pullup : R/W; bitpos: [11]; default: 0;
-         *  Control USB D- pull up.
-         */
-        uint32_t dm_pullup:1;
-        /** dm_pulldown : R/W; bitpos: [12]; default: 0;
-         *  Control USB D- pull down.
-         */
-        uint32_t dm_pulldown:1;
-        /** pullup_value : R/W; bitpos: [13]; default: 0;
-         *  Control pull up value.
-         */
-        uint32_t pullup_value:1;
-        /** usb_pad_enable : R/W; bitpos: [14]; default: 1;
-         *  Enable USB pad function.
-         */
-        uint32_t usb_pad_enable:1;
-        /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
-         *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
-         *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
-         *  through GPIO Matrix.
-         */
-        uint32_t usb_jtag_bridge_en:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_conf0_reg_t;
-
-/** Type of test register
- *  Registers used for debugging the PHY.
- */
-typedef union {
-    struct {
-        /** test_enable : R/W; bitpos: [0]; default: 0;
-         *  Enable test of the USB pad
-         */
-        uint32_t test_enable:1;
-        /** test_usb_oe : R/W; bitpos: [1]; default: 0;
-         *  USB pad one in test
-         */
-        uint32_t test_usb_oe:1;
-        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
-         *  USB D+ tx value in test
-         */
-        uint32_t test_tx_dp:1;
-        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
-         *  USB D- tx value in test
-         */
-        uint32_t test_tx_dm:1;
-        /** test_rx_rcv : RO; bitpos: [4]; default: 1;
-         *  USB RCV value in test
-         */
-        uint32_t test_rx_rcv:1;
-        /** test_rx_dp : RO; bitpos: [5]; default: 1;
-         *  USB D+ rx value in test
-         */
-        uint32_t test_rx_dp:1;
-        /** test_rx_dm : RO; bitpos: [6]; default: 0;
-         *  USB D- rx value in test
-         */
-        uint32_t test_rx_dm:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} usb_serial_jtag_test_reg_t;
-
-/** Type of misc_conf register
- *  Clock enable control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_misc_conf_reg_t;
-
-/** Type of mem_conf register
- *  Memory power control
- */
-typedef union {
-    struct {
-        /** usb_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  1: power down usb memory.
-         */
-        uint32_t usb_mem_pd:1;
-        /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
-         *  1: Force clock on for usb memory.
-         */
-        uint32_t usb_mem_clk_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} usb_serial_jtag_mem_conf_reg_t;
-
-/** Type of chip_rst register
- *  CDC-ACM chip reset control.
- */
-typedef union {
-    struct {
-        /** rts : RO; bitpos: [0]; default: 0;
-         *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
-         */
-        uint32_t rts:1;
-        /** dtr : RO; bitpos: [1]; default: 0;
-         *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
-         */
-        uint32_t dtr:1;
-        /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to disable chip reset from usb serial channel to reset chip.
-         */
-        uint32_t usb_uart_chip_rst_dis:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} usb_serial_jtag_chip_rst_reg_t;
-
-/** Type of get_line_code_w0 register
- *  W0 of GET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
-         *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_dw_dte_rate:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_get_line_code_w0_reg_t;
-
-/** Type of get_line_code_w1 register
- *  W1 of GET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
-         *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bdata_bits:8;
-        /** get_bparity_type : R/W; bitpos: [15:8]; default: 0;
-         *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bparity_type:8;
-        /** get_bchar_format : R/W; bitpos: [23:16]; default: 0;
-         *  The value of bDataBits set by software which is requested by GET_LINE_CODING
-         *  command.
-         */
-        uint32_t get_bchar_format:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} usb_serial_jtag_get_line_code_w1_reg_t;
-
-/** Type of config_update register
- *  Configuration registers' value update
- */
-typedef union {
-    struct {
-        /** config_update : WT; bitpos: [0]; default: 0;
-         *  Write 1 to this register would update the value of configure registers from APB
-         *  clock domain to 48MHz clock domain.
-         */
-        uint32_t config_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_config_update_reg_t;
-
-/** Type of ser_afifo_config register
- *  Serial AFIFO configure register
- */
-typedef union {
-    struct {
-        /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
-         */
-        uint32_t serial_in_afifo_reset_wr:1;
-        /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
-         */
-        uint32_t serial_in_afifo_reset_rd:1;
-        /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
-         */
-        uint32_t serial_out_afifo_reset_wr:1;
-        /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
-         */
-        uint32_t serial_out_afifo_reset_rd:1;
-        /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
-         *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
-         */
-        uint32_t serial_out_afifo_rempty:1;
-        /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
-         *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
-         */
-        uint32_t serial_in_afifo_wfull:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} usb_serial_jtag_ser_afifo_config_reg_t;
-
-/** Type of serial_ep_timeout0 register
- *  USB uart out endpoint timeout configuration.
- */
-typedef union {
-    struct {
-        /** serial_timeout_en : R/W; bitpos: [0]; default: 0;
-         *  USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
-         *  is automatically cleared and reg_serial_timeout_status is asserted.
-         */
-        uint32_t serial_timeout_en:1;
-        /** serial_timeout_status : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Serial out ep triggers a timeout event.
-         */
-        uint32_t serial_timeout_status:1;
-        /** serial_timeout_status_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear reg_serial_timeout_status.
-         */
-        uint32_t serial_timeout_status_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} usb_serial_jtag_serial_ep_timeout0_reg_t;
-
-/** Type of serial_ep_timeout1 register
- *  USB uart out endpoint timeout configuration.
- */
-typedef union {
-    struct {
-        /** serial_timeout_max : R/W; bitpos: [31:0]; default: 4800768;
-         *  USB serial out ep timeout max threshold value, indicates the maximum time that
-         *  waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
-         */
-        uint32_t serial_timeout_max:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_serial_ep_timeout1_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_raw register
- *  Interrupt raw status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt bit turns to high level when flush cmd is received for IN
-         *  endpoint 2 of JTAG.
-         */
-        uint32_t jtag_in_flush_int_raw:1;
-        /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt bit turns to high level when SOF frame is received.
-         */
-        uint32_t sof_int_raw:1;
-        /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
-         *  one packet.
-         */
-        uint32_t serial_out_recv_pkt_int_raw:1;
-        /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
-         *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
-         */
-        uint32_t serial_in_empty_int_raw:1;
-        /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt bit turns to high level when pid error is detected.
-         */
-        uint32_t pid_err_int_raw:1;
-        /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt bit turns to high level when CRC5 error is detected.
-         */
-        uint32_t crc5_err_int_raw:1;
-        /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt bit turns to high level when CRC16 error is detected.
-         */
-        uint32_t crc16_err_int_raw:1;
-        /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt bit turns to high level when stuff error is detected.
-         */
-        uint32_t stuff_err_int_raw:1;
-        /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
-         *  received.
-         */
-        uint32_t in_token_rec_in_ep1_int_raw:1;
-        /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt bit turns to high level when usb bus reset is detected.
-         */
-        uint32_t usb_bus_reset_int_raw:1;
-        /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
-         *  zero palyload.
-         */
-        uint32_t out_ep1_zero_payload_int_raw:1;
-        /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
-         *  zero palyload.
-         */
-        uint32_t out_ep2_zero_payload_int_raw:1;
-        /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
-         *  is changed.
-         */
-        uint32_t rts_chg_int_raw:1;
-        /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
-         *  is changed.
-         */
-        uint32_t dtr_chg_int_raw:1;
-        /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
-         *  received.
-         */
-        uint32_t get_line_code_int_raw:1;
-        /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
-         *  received.
-         */
-        uint32_t set_line_code_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_raw_reg_t;
-
-/** Type of int_st register
- *  Interrupt status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_st:1;
-        /** sof_int_st : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
-         */
-        uint32_t sof_int_st:1;
-        /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
-         *  interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_st:1;
-        /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_st:1;
-        /** pid_err_int_st : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_st:1;
-        /** crc5_err_int_st : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_st:1;
-        /** crc16_err_int_st : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_st:1;
-        /** stuff_err_int_st : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_st:1;
-        /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
-         *  interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_st:1;
-        /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_st:1;
-        /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
-         *  interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_st:1;
-        /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
-         *  interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_st:1;
-        /** rts_chg_int_st : RO; bitpos: [12]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_st:1;
-        /** dtr_chg_int_st : RO; bitpos: [13]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_st:1;
-        /** get_line_code_int_st : RO; bitpos: [14]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_st:1;
-        /** set_line_code_int_st : RO; bitpos: [15]; default: 0;
-         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_ena:1;
-        /** sof_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
-         */
-        uint32_t sof_int_ena:1;
-        /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_ena:1;
-        /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_ena:1;
-        /** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_ena:1;
-        /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_ena:1;
-        /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_ena:1;
-        /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_ena:1;
-        /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_ena:1;
-        /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_ena:1;
-        /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_ena:1;
-        /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_ena:1;
-        /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_ena:1;
-        /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_ena:1;
-        /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_ena:1;
-        /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear status register.
- */
-typedef union {
-    struct {
-        /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
-         */
-        uint32_t jtag_in_flush_int_clr:1;
-        /** sof_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
-         */
-        uint32_t sof_int_clr:1;
-        /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
-         */
-        uint32_t serial_out_recv_pkt_int_clr:1;
-        /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
-         */
-        uint32_t serial_in_empty_int_clr:1;
-        /** pid_err_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
-         */
-        uint32_t pid_err_int_clr:1;
-        /** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
-         */
-        uint32_t crc5_err_int_clr:1;
-        /** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
-         */
-        uint32_t crc16_err_int_clr:1;
-        /** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
-         */
-        uint32_t stuff_err_int_clr:1;
-        /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
-         */
-        uint32_t in_token_rec_in_ep1_int_clr:1;
-        /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
-         */
-        uint32_t usb_bus_reset_int_clr:1;
-        /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep1_zero_payload_int_clr:1;
-        /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-         */
-        uint32_t out_ep2_zero_payload_int_clr:1;
-        /** rts_chg_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
-         */
-        uint32_t rts_chg_int_clr:1;
-        /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
-         */
-        uint32_t dtr_chg_int_clr:1;
-        /** get_line_code_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
-         */
-        uint32_t get_line_code_int_clr:1;
-        /** set_line_code_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
-         */
-        uint32_t set_line_code_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_int_clr_reg_t;
-
-
-/** Group: Status Registers */
-/** Type of jfifo_st register
- *  JTAG FIFO status and control registers.
- */
-typedef union {
-    struct {
-        /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
-         *  JTAT in fifo counter.
-         */
-        uint32_t in_fifo_cnt:2;
-        /** in_fifo_empty : RO; bitpos: [2]; default: 1;
-         *  1: JTAG in fifo is empty.
-         */
-        uint32_t in_fifo_empty:1;
-        /** in_fifo_full : RO; bitpos: [3]; default: 0;
-         *  1: JTAG in fifo is full.
-         */
-        uint32_t in_fifo_full:1;
-        /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
-         *  JTAT out fifo counter.
-         */
-        uint32_t out_fifo_cnt:2;
-        /** out_fifo_empty : RO; bitpos: [6]; default: 1;
-         *  1: JTAG out fifo is empty.
-         */
-        uint32_t out_fifo_empty:1;
-        /** out_fifo_full : RO; bitpos: [7]; default: 0;
-         *  1: JTAG out fifo is full.
-         */
-        uint32_t out_fifo_full:1;
-        /** in_fifo_reset : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to reset JTAG in fifo.
-         */
-        uint32_t in_fifo_reset:1;
-        /** out_fifo_reset : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to reset JTAG out fifo.
-         */
-        uint32_t out_fifo_reset:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} usb_serial_jtag_jfifo_st_reg_t;
-
-/** Type of fram_num register
- *  Last received SOF frame index register.
- */
-typedef union {
-    struct {
-        /** sof_frame_index : RO; bitpos: [10:0]; default: 0;
-         *  Frame index of received SOF frame.
-         */
-        uint32_t sof_frame_index:11;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} usb_serial_jtag_fram_num_reg_t;
-
-/** Type of in_ep0_st register
- *  Control IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep0_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 0.
-         */
-        uint32_t in_ep0_state:2;
-        /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 0.
-         */
-        uint32_t in_ep0_wr_addr:7;
-        /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 0.
-         */
-        uint32_t in_ep0_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep0_st_reg_t;
-
-/** Type of in_ep1_st register
- *  CDC-ACM IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep1_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 1.
-         */
-        uint32_t in_ep1_state:2;
-        /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 1.
-         */
-        uint32_t in_ep1_wr_addr:7;
-        /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 1.
-         */
-        uint32_t in_ep1_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep1_st_reg_t;
-
-/** Type of in_ep2_st register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep2_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 2.
-         */
-        uint32_t in_ep2_state:2;
-        /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 2.
-         */
-        uint32_t in_ep2_wr_addr:7;
-        /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 2.
-         */
-        uint32_t in_ep2_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep2_st_reg_t;
-
-/** Type of in_ep3_st register
- *  JTAG IN endpoint status information.
- */
-typedef union {
-    struct {
-        /** in_ep3_state : RO; bitpos: [1:0]; default: 1;
-         *  State of IN Endpoint 3.
-         */
-        uint32_t in_ep3_state:2;
-        /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of IN endpoint 3.
-         */
-        uint32_t in_ep3_wr_addr:7;
-        /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of IN endpoint 3.
-         */
-        uint32_t in_ep3_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_in_ep3_st_reg_t;
-
-/** Type of out_ep0_st register
- *  Control OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep0_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 0.
-         */
-        uint32_t out_ep0_state:2;
-        /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
-         *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
-         */
-        uint32_t out_ep0_wr_addr:7;
-        /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 0.
-         */
-        uint32_t out_ep0_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep0_st_reg_t;
-
-/** Type of out_ep1_st register
- *  CDC-ACM OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep1_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 1.
-         */
-        uint32_t out_ep1_state:2;
-        /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
-         *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
-         */
-        uint32_t out_ep1_wr_addr:7;
-        /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 1.
-         */
-        uint32_t out_ep1_rd_addr:7;
-        /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
-         *  Data count in OUT endpoint 1 when one packet is received.
-         */
-        uint32_t out_ep1_rec_data_cnt:7;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep1_st_reg_t;
-
-/** Type of out_ep2_st register
- *  JTAG OUT endpoint status information.
- */
-typedef union {
-    struct {
-        /** out_ep2_state : RO; bitpos: [1:0]; default: 0;
-         *  State of OUT Endpoint 2.
-         */
-        uint32_t out_ep2_state:2;
-        /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
-         *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
-         *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
-         */
-        uint32_t out_ep2_wr_addr:7;
-        /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
-         *  Read data address of OUT endpoint 2.
-         */
-        uint32_t out_ep2_rd_addr:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} usb_serial_jtag_out_ep2_st_reg_t;
-
-/** Type of set_line_code_w0 register
- *  W0 of SET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** dw_dte_rate : RO; bitpos: [31:0]; default: 0;
-         *  The value of dwDTERate set by host through SET_LINE_CODING command.
-         */
-        uint32_t dw_dte_rate:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_set_line_code_w0_reg_t;
-
-/** Type of set_line_code_w1 register
- *  W1 of SET_LINE_CODING command.
- */
-typedef union {
-    struct {
-        /** bchar_format : RO; bitpos: [7:0]; default: 0;
-         *  The value of bCharFormat set by host through SET_LINE_CODING command.
-         */
-        uint32_t bchar_format:8;
-        /** bparity_type : RO; bitpos: [15:8]; default: 0;
-         *  The value of bParityTpye set by host through SET_LINE_CODING command.
-         */
-        uint32_t bparity_type:8;
-        /** bdata_bits : RO; bitpos: [23:16]; default: 0;
-         *  The value of bDataBits set by host through SET_LINE_CODING command.
-         */
-        uint32_t bdata_bits:8;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} usb_serial_jtag_set_line_code_w1_reg_t;
-
-/** Type of bus_reset_st register
- *  USB Bus reset status register
- */
-typedef union {
-    struct {
-        /** usb_bus_reset_st : RO; bitpos: [0]; default: 1;
-         *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
-         *  reset is released.
-         */
-        uint32_t usb_bus_reset_st:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} usb_serial_jtag_bus_reset_st_reg_t;
-
-
-/** Group: Version Registers */
-/** Type of date register
- *  Date register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 36770368;
-         *  register version.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} usb_serial_jtag_date_reg_t;
-
-
-typedef struct {
-    volatile usb_serial_jtag_ep1_reg_t ep1;
-    volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
-    volatile usb_serial_jtag_int_raw_reg_t int_raw;
-    volatile usb_serial_jtag_int_st_reg_t int_st;
-    volatile usb_serial_jtag_int_ena_reg_t int_ena;
-    volatile usb_serial_jtag_int_clr_reg_t int_clr;
-    volatile usb_serial_jtag_conf0_reg_t conf0;
-    volatile usb_serial_jtag_test_reg_t test;
-    volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
-    volatile usb_serial_jtag_fram_num_reg_t fram_num;
-    volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
-    volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
-    volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
-    volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
-    volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
-    volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
-    volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
-    volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
-    volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
-    volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
-    volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
-    volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
-    volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
-    volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
-    volatile usb_serial_jtag_config_update_reg_t config_update;
-    volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
-    volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
-    volatile usb_serial_jtag_serial_ep_timeout0_reg_t serial_ep_timeout0;
-    volatile usb_serial_jtag_serial_ep_timeout1_reg_t serial_ep_timeout1;
-    uint32_t reserved_074[3];
-    volatile usb_serial_jtag_date_reg_t date;
-} usb_serial_jtag_dev_t;
-
-extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c5/interrupts.c b/components/soc/esp32c5/interrupts.c
index eb4a89c989e..23421b66278 100644
--- a/components/soc/esp32c5/interrupts.c
+++ b/components/soc/esp32c5/interrupts.c
@@ -50,7 +50,7 @@ const char *const esp_isr_names[] = {
     [ETS_HP_APM_M4_INTR_SOURCE] = "HP_APM_M4",
     [ETS_LP_APM0_INTR_SOURCE] = "LP_APM0",
     [ETS_MSPI_INTR_SOURCE] = "MSPI",
-    [ETS_I2S1_INTR_SOURCE] = "I2S1",
+    [ETS_I2S0_INTR_SOURCE] = "I2S0",
     [ETS_UHCI0_INTR_SOURCE] = "UHCI0",
     [ETS_UART0_INTR_SOURCE] = "UART0",
     [ETS_UART1_INTR_SOURCE] = "UART1",
diff --git a/components/soc/esp32c5/ledc_periph.c b/components/soc/esp32c5/ledc_periph.c
index fa64b659225..1279e25dce7 100644
--- a/components/soc/esp32c5/ledc_periph.c
+++ b/components/soc/esp32c5/ledc_periph.c
@@ -15,3 +15,152 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
     }
 };
+
+/**
+ * LEDC registers to be saved for sleep retention
+ *
+ * channel:
+ * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
+ * LEDC_CHx_GAMMA_CONF_REG, LEDC_CHx_GAMMA_RANGEi_REG
+ *
+ * timer:
+ * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
+ *
+ * common:
+ * LEDC_INT_ENA_REG,
+ * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
+ * LEDC_CONF_REG,
+ *
+ * Note 1: Gamma parameter registers are backuped and restored. But we won't start a fade automatically after wake-up.
+ *         Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep.
+ *
+ * Note 2: For timer/channel registers to get synced, update bits need to be set
+ *
+ * Note 3: Gamma RAM registers R/W relies both APB and function clock, therefore, retention requires the existence of function clock
+ */
+#define LEDC_COMMON_RETENTION_REGS_CNT  5
+#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
+static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x400, 0x0, 0x0};
+static const regdma_entries_config_t ledc_common_regdma_entries[] = {
+    // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
+    // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
+			 							    LEDC_INT_ENA_REG, 0,
+			 							    (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1),
+		    .owner = LEDC_RETENTION_ENTRY },
+    [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
+                                               LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
+                                               LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
+                                               ledc_common_regs_map[0], ledc_common_regs_map[1],
+                                               ledc_common_regs_map[2], ledc_common_regs_map[3]),
+            .owner = LEDC_RETENTION_ENTRY },
+};
+
+#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
+	[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
+			 								     LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+			 								     LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
+			 							    LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
+static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
+static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0};
+#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
+	[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
+                                               LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
+                                               LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
+                                               ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
+                                               ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+                                                 LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
+			 							    LEDC_DUTY_START_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
+			 							    LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
+			 							    LEDC_PARA_UP_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \
+                                                 LEDC_CH##chan##_GAMMA_CONF_REG, LEDC_CH##chan##_GAMMA_CONF_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+    [5] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x05), \
+                                               LEDC_CH##chan##_GAMMA_RANGE0_REG, LEDC_CH##chan##_GAMMA_RANGE0_REG, \
+                                               SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX, 0, 0, \
+                                               ledc_channel_gamma_regs_map[0], ledc_channel_gamma_regs_map[1], \
+                                               ledc_channel_gamma_regs_map[2], ledc_channel_gamma_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
+
+static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
+static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
+static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+    .common = {
+		.regdma_entry_array = ledc_common_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
+	},
+	.timer[0] = {
+		.regdma_entry_array = ledc_timer0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
+	},
+	.timer[1] = {
+		.regdma_entry_array = ledc_timer1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
+	},
+	.timer[2] = {
+		.regdma_entry_array = ledc_timer2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
+	},
+	.timer[3] = {
+		.regdma_entry_array = ledc_timer3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
+	},
+	.channel[0] = {
+		.regdma_entry_array = ledc_channel0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
+	},
+	.channel[1] = {
+		.regdma_entry_array = ledc_channel1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
+	},
+	.channel[2] = {
+		.regdma_entry_array = ledc_channel2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
+	},
+	.channel[3] = {
+		.regdma_entry_array = ledc_channel3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
+	},
+	.channel[4] = {
+		.regdma_entry_array = ledc_channel4_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
+	},
+	.channel[5] = {
+		.regdma_entry_array = ledc_channel5_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
+	},
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};
diff --git a/components/soc/esp32c5/mcpwm_periph.c b/components/soc/esp32c5/mcpwm_periph.c
index 87ac9a7eb3e..b7f1d713088 100644
--- a/components/soc/esp32c5/mcpwm_periph.c
+++ b/components/soc/esp32c5/mcpwm_periph.c
@@ -6,6 +6,7 @@
 
 #include "soc/soc.h"
 #include "soc/mcpwm_periph.h"
+#include "soc/mcpwm_reg.h"
 #include "soc/gpio_sig_map.h"
 
 const mcpwm_signal_conn_t mcpwm_periph_signals = {
@@ -81,3 +82,46 @@ const mcpwm_signal_conn_t mcpwm_periph_signals = {
         }
     }
 };
+
+/**
+ * MCPWM Registers to be saved during sleep retention
+ * - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
+ * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
+ * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
+ *   |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
+ *   |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
+ *   |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
+ *   └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
+ * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
+ * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
+ * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG
+ * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
+*/
+#define MCPWM_RETENTION_REGS_CNT 68
+#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
+static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
+static const regdma_entries_config_t mcpwm_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
+                                               MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
+                                               MCPWM_RETENTION_REGS_CNT, 0, 0,
+                                               mcpwm_regs_map[0], mcpwm_regs_map[1],
+                                               mcpwm_regs_map[2], mcpwm_regs_map[3]),
+                                               .owner = ENTRY(0) | ENTRY(2) },
+    // restore stage: trigger a forced update of all active registers
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
+                                                MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
+                                                .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
+                                                MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = mcpwm_regs_retention,
+        .array_size = ARRAY_SIZE(mcpwm_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_MCPWM0
+    },
+};
diff --git a/components/soc/esp32c5/parlio_periph.c b/components/soc/esp32c5/parlio_periph.c
index 142e461cf17..bd17bfceb11 100644
--- a/components/soc/esp32c5/parlio_periph.c
+++ b/components/soc/esp32c5/parlio_periph.c
@@ -48,3 +48,31 @@ const parlio_signal_conn_t parlio_periph_signals = {
         },
     },
 };
+
+/**
+ * PARLIO Registers to be saved during sleep retention
+ * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG
+ * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG
+ * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG
+ * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG
+*/
+#define PARLIO_RETENTION_REGS_CNT 8
+#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0)
+static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0};
+static const regdma_entries_config_t parlio_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \
+                                               PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \
+                                               PARLIO_RETENTION_REGS_CNT, 0, 0, \
+                                               parlio_regs_map[0], parlio_regs_map[1], \
+                                               parlio_regs_map[2], parlio_regs_map[3]), \
+                                               .owner = ENTRY(0) | ENTRY(2) }, \
+};
+const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = parlio_regs_retention,
+        .array_size = ARRAY_SIZE(parlio_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_PARLIO0
+    },
+};
diff --git a/components/soc/esp32c5/pcnt_periph.c b/components/soc/esp32c5/pcnt_periph.c
index 162db5aa27b..c96644dae1d 100644
--- a/components/soc/esp32c5/pcnt_periph.c
+++ b/components/soc/esp32c5/pcnt_periph.c
@@ -6,6 +6,7 @@
 
 #include "soc/pcnt_periph.h"
 #include "soc/gpio_sig_map.h"
+#include "soc/pcnt_reg.h"
 
 const pcnt_signal_conn_t pcnt_periph_signals = {
     .groups = {
@@ -68,3 +69,31 @@ const pcnt_signal_conn_t pcnt_periph_signals = {
         }
     }
 };
+
+/**
+ * PCNT Registers to be saved during sleep retention
+ * - Configuration registers, e.g.: PCNT_CTRL_REG, PCNT_U0_CONF0_REG, PCNT_U0_CONF1_REG, PCNT_U0_CONF2_REG, PCNT_U1_CONF0_REG...
+ * - Step Configuration registers, e.g.: PCNT_U0_CHANGE_CONF_REG, PCNT_U1_CHANGE_CONF_REG, PCNT_U2_CHANGE_CONF_REG, PCNT_U3_CHANGE_CONF_REG
+ * - Interrupt enable registers, e.g.: PCNT_INT_ENA_REG
+*/
+#define PCNT_RETENTION_REGS_CNT 18
+#define PCNT_RETENTION_REGS_BASE (DR_REG_PCNT_BASE + 0x0)
+static const uint32_t pcnt_regs_map[4] = {0x1f040fff, 0x0, 0x0, 0x0};
+static const regdma_entries_config_t pcnt_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \
+                                               PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \
+                                               PCNT_RETENTION_REGS_CNT, 0, 0, \
+                                               pcnt_regs_map[0], pcnt_regs_map[1], \
+                                               pcnt_regs_map[2], pcnt_regs_map[3]), \
+                                               .owner = ENTRY(0) | ENTRY(2) }, \
+};
+
+const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = pcnt_regs_retention,
+        .array_size = ARRAY_SIZE(pcnt_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_PCNT0
+    },
+};
diff --git a/components/soc/esp32c5/register/soc/.gitkeep b/components/soc/esp32c5/register/soc/.gitkeep
deleted file mode 100644
index e69de29bb2d..00000000000
diff --git a/components/soc/esp32c5/include/soc/aes_reg.h b/components/soc/esp32c5/register/soc/aes_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/aes_reg.h
rename to components/soc/esp32c5/register/soc/aes_reg.h
diff --git a/components/soc/esp32c5/include/soc/aes_struct.h b/components/soc/esp32c5/register/soc/aes_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/aes_struct.h
rename to components/soc/esp32c5/register/soc/aes_struct.h
diff --git a/components/soc/esp32c5/include/soc/ahb_dma_reg.h b/components/soc/esp32c5/register/soc/ahb_dma_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ahb_dma_reg.h
rename to components/soc/esp32c5/register/soc/ahb_dma_reg.h
diff --git a/components/soc/esp32c5/include/soc/ahb_dma_struct.h b/components/soc/esp32c5/register/soc/ahb_dma_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ahb_dma_struct.h
rename to components/soc/esp32c5/register/soc/ahb_dma_struct.h
diff --git a/components/soc/esp32c5/include/soc/apb_saradc_reg.h b/components/soc/esp32c5/register/soc/apb_saradc_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/apb_saradc_reg.h
rename to components/soc/esp32c5/register/soc/apb_saradc_reg.h
diff --git a/components/soc/esp32c5/include/soc/apb_saradc_struct.h b/components/soc/esp32c5/register/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/apb_saradc_struct.h
rename to components/soc/esp32c5/register/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32c5/include/soc/assist_debug_reg.h b/components/soc/esp32c5/register/soc/assist_debug_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/assist_debug_reg.h
rename to components/soc/esp32c5/register/soc/assist_debug_reg.h
diff --git a/components/soc/esp32c5/include/soc/assist_debug_struct.h b/components/soc/esp32c5/register/soc/assist_debug_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/assist_debug_struct.h
rename to components/soc/esp32c5/register/soc/assist_debug_struct.h
diff --git a/components/soc/esp32c5/include/soc/bitscrambler_reg.h b/components/soc/esp32c5/register/soc/bitscrambler_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/bitscrambler_reg.h
rename to components/soc/esp32c5/register/soc/bitscrambler_reg.h
diff --git a/components/soc/esp32c5/include/soc/bitscrambler_struct.h b/components/soc/esp32c5/register/soc/bitscrambler_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/bitscrambler_struct.h
rename to components/soc/esp32c5/register/soc/bitscrambler_struct.h
diff --git a/components/soc/esp32c5/include/soc/cache_reg.h b/components/soc/esp32c5/register/soc/cache_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/cache_reg.h
rename to components/soc/esp32c5/register/soc/cache_reg.h
diff --git a/components/soc/esp32c5/include/soc/cache_struct.h b/components/soc/esp32c5/register/soc/cache_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/cache_struct.h
rename to components/soc/esp32c5/register/soc/cache_struct.h
diff --git a/components/soc/esp32c5/include/soc/ds_reg.h b/components/soc/esp32c5/register/soc/ds_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ds_reg.h
rename to components/soc/esp32c5/register/soc/ds_reg.h
diff --git a/components/soc/esp32c5/include/soc/ds_struct.h b/components/soc/esp32c5/register/soc/ds_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ds_struct.h
rename to components/soc/esp32c5/register/soc/ds_struct.h
diff --git a/components/soc/esp32c5/include/soc/ecc_mult_reg.h b/components/soc/esp32c5/register/soc/ecc_mult_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ecc_mult_reg.h
rename to components/soc/esp32c5/register/soc/ecc_mult_reg.h
diff --git a/components/soc/esp32c5/include/soc/ecc_mult_struct.h b/components/soc/esp32c5/register/soc/ecc_mult_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ecc_mult_struct.h
rename to components/soc/esp32c5/register/soc/ecc_mult_struct.h
diff --git a/components/soc/esp32c5/include/soc/ecdsa_reg.h b/components/soc/esp32c5/register/soc/ecdsa_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ecdsa_reg.h
rename to components/soc/esp32c5/register/soc/ecdsa_reg.h
diff --git a/components/soc/esp32c5/include/soc/ecdsa_struct.h b/components/soc/esp32c5/register/soc/ecdsa_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ecdsa_struct.h
rename to components/soc/esp32c5/register/soc/ecdsa_struct.h
diff --git a/components/soc/esp32c5/register/soc/efuse_reg.h b/components/soc/esp32c5/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..51a6a3122df
--- /dev/null
+++ b/components/soc/esp32c5/register/soc/efuse_reg.h
@@ -0,0 +1,4403 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Represents pgm_data0
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Represents pgm_data1
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Represents pgm_data2
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Represents pgm_data3
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Represents pgm_data4
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Represents pgm_data5
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Represents pgm_data6
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Represents pgm_data7
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Represents pgm_check_value0
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Represents pgm_check_value1
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Represents pgm_check_value2
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS0_REG register
+ *  Represents rd_wr_dis
+ */
+#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled or
+ *  enabled.\\ 1: Disabled\\ 0: Enabled\\
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+ *  enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_RD_RESERVE_0_39 : RW; bitpos: [7]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_39    (BIT(7))
+#define EFUSE_RD_RESERVE_0_39_M  (EFUSE_RD_RESERVE_0_39_V << EFUSE_RD_RESERVE_0_39_S)
+#define EFUSE_RD_RESERVE_0_39_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_39_S  7
+/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
+ *  Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_ICACHE    (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
+#define EFUSE_DIS_ICACHE_V  0x00000001U
+#define EFUSE_DIS_ICACHE_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
+ *  disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_RD_RESERVE_0_42 : RW; bitpos: [10]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_42    (BIT(10))
+#define EFUSE_RD_RESERVE_0_42_M  (EFUSE_RD_RESERVE_0_42_V << EFUSE_RD_RESERVE_0_42_S)
+#define EFUSE_RD_RESERVE_0_42_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_42_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
+ *  enabled\\
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
+ *  Represents whether SPI0 controller during boot_mode_download is disabled or
+ *  enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0:
+ *  enabled\\
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ *  is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even
+ *  number: enabled\\
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
+ *  0: enabled\\
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode).\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
+ */
+#define EFUSE_USB_DREFH    0x00000003U
+#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
+#define EFUSE_USB_DREFH_V  0x00000003U
+#define EFUSE_USB_DREFH_S  21
+/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
+ *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
+ */
+#define EFUSE_USB_DREFL    0x00000003U
+#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
+#define EFUSE_USB_DREFL_V  0x00000003U
+#define EFUSE_USB_DREFL_S  23
+/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
+ *  Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not
+ *  exchanged\\
+ */
+#define EFUSE_USB_EXCHG_PINS    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
+#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_S  25
+/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
+ *  Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not
+ *  functioned\\
+ */
+#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
+#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_S  26
+/** EFUSE_RD_RESERVE_0_59 : RW; bitpos: [31:27]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_59    0x0000001FU
+#define EFUSE_RD_RESERVE_0_59_M  (EFUSE_RD_RESERVE_0_59_V << EFUSE_RD_RESERVE_0_59_S)
+#define EFUSE_RD_RESERVE_0_59_V  0x0000001FU
+#define EFUSE_RD_RESERVE_0_59_S  27
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [3:0]; default: 0;
+ *  Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled
+ *  \\ 0: enabled.\\
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [5:4]; default: 0;
+ *  Set the bits to control key manager random number switch cycle. 0: control by
+ *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_S  4
+/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [9:6]; default: 0;
+ *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+ *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  6
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [13:10]; default: 0;
+ *  Set each bit to control whether corresponding key must come from key manager. 1 is
+ *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  10
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [14]; default: 0;
+ *  Set this bit to disable software written init key, and force use efuse_init_key.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(14))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  14
+/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_79    (BIT(15))
+#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
+#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_79_S  15
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original
+ *  threshold configuration value of STG0 *2 \\1: Original threshold configuration
+ *  value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3:
+ *  Original threshold configuration value of STG0 *16 \\
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
+ *  1: enabled\\ Even number of 1: disabled\\
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
+ *  enabled\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
+ *  enabled\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
+ *  enabled\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Represents the purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  16
+/** EFUSE_RD_RESERVE_0_114 : RW; bitpos: [19:18]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_114    0x00000003U
+#define EFUSE_RD_RESERVE_0_114_M  (EFUSE_RD_RESERVE_0_114_V << EFUSE_RD_RESERVE_0_114_S)
+#define EFUSE_RD_RESERVE_0_114_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_114_S  18
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
+ *  enabled.\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [26:22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_118    0x0000001FU
+#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
+#define EFUSE_RD_RESERVE_0_118_V  0x0000001FU
+#define EFUSE_RD_RESERVE_0_118_S  22
+/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [27]; default: 0;
+ *  Set this bitto configure flash encryption use xts-128 key. else use xts-256 key.
+ */
+#define EFUSE_KM_XTS_KEY_LENGTH_256    (BIT(27))
+#define EFUSE_KM_XTS_KEY_LENGTH_256_M  (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S)
+#define EFUSE_KM_XTS_KEY_LENGTH_256_V  0x00000001U
+#define EFUSE_KM_XTS_KEY_LENGTH_256_S  27
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+ *  is 2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0:
+ *  enabled\\
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0:
+ *  enabled\\
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1:
+ *  disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
+ *  Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\
+ */
+#define EFUSE_LOCK_KM_KEY    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
+#define EFUSE_LOCK_KM_KEY_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
+ *  1: Disable\\ 0: Enable\\
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0:
+ *  disabled\\
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable
+ *  printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset
+ *  at high level\\ 11: force disable printing\\
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot.\\
+ *  1: forced\\ 0:not forced\\
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  8
+/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
+ *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+ *  enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
+/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
+ *  Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
+ *  enabled\\ 0:disabled\\
+ */
+#define EFUSE_HYS_EN_PAD    (BIT(26))
+#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
+#define EFUSE_HYS_EN_PAD_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_S  26
+/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0;
+ *  Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2:
+ *  Moderate 1. Low\\ 0: Disabled\\
+ */
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL    0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S)
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V  0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S  27
+/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0;
+ *  Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0:
+ *  Disable.\\
+ */
+#define EFUSE_XTS_DPA_CLK_ENABLE    (BIT(29))
+#define EFUSE_XTS_DPA_CLK_ENABLE_M  (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S)
+#define EFUSE_XTS_DPA_CLK_ENABLE_V  0x00000001U
+#define EFUSE_XTS_DPA_CLK_ENABLE_S  29
+/** EFUSE_RD_RESERVE_0_158 : RW; bitpos: [31:30]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_158    0x00000003U
+#define EFUSE_RD_RESERVE_0_158_M  (EFUSE_RD_RESERVE_0_158_V << EFUSE_RD_RESERVE_0_158_S)
+#define EFUSE_RD_RESERVE_0_158_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_158_S  30
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_HUK_GEN_STATE : RO; bitpos: [8:0]; default: 0;
+ *  Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\
+ *  Even of 1 is valid.\\
+ */
+#define EFUSE_HUK_GEN_STATE    0x000001FFU
+#define EFUSE_HUK_GEN_STATE_M  (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S)
+#define EFUSE_HUK_GEN_STATE_V  0x000001FFU
+#define EFUSE_HUK_GEN_STATE_S  0
+/** EFUSE_XTAL_48M_SEL : RO; bitpos: [11:9]; default: 0;
+ *  Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used.
+ *  If this field contains Odd number bit '1': Enable 48MHz XTAL\\ Even number bit '1':
+ *  Enable 40MHz XTAL.
+ */
+#define EFUSE_XTAL_48M_SEL    0x00000007U
+#define EFUSE_XTAL_48M_SEL_M  (EFUSE_XTAL_48M_SEL_V << EFUSE_XTAL_48M_SEL_S)
+#define EFUSE_XTAL_48M_SEL_V  0x00000007U
+#define EFUSE_XTAL_48M_SEL_S  9
+/** EFUSE_XTAL_48M_SEL_MODE : RO; bitpos: [12]; default: 0;
+ *  Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1:
+ *  eFuse\\ 0: strapping-PAD-state.
+ */
+#define EFUSE_XTAL_48M_SEL_MODE    (BIT(12))
+#define EFUSE_XTAL_48M_SEL_MODE_M  (EFUSE_XTAL_48M_SEL_MODE_V << EFUSE_XTAL_48M_SEL_MODE_S)
+#define EFUSE_XTAL_48M_SEL_MODE_V  0x00000001U
+#define EFUSE_XTAL_48M_SEL_MODE_S  12
+/** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [13]; default: 0;
+ *  Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable.
+ */
+#define EFUSE_ECDSA_DISABLE_P192    (BIT(13))
+#define EFUSE_ECDSA_DISABLE_P192_M  (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S)
+#define EFUSE_ECDSA_DISABLE_P192_V  0x00000001U
+#define EFUSE_ECDSA_DISABLE_P192_S  13
+/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [14]; default: 0;
+ *  Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
+ *  \\ 0: Disable.
+ */
+#define EFUSE_ECC_FORCE_CONST_TIME    (BIT(14))
+#define EFUSE_ECC_FORCE_CONST_TIME_M  (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S)
+#define EFUSE_ECC_FORCE_CONST_TIME_V  0x00000001U
+#define EFUSE_ECC_FORCE_CONST_TIME_S  14
+/** EFUSE_RD_RESERVE_0_175 : RW; bitpos: [31:15]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_175    0x0001FFFFU
+#define EFUSE_RD_RESERVE_0_175_M  (EFUSE_RD_RESERVE_0_175_V << EFUSE_RD_RESERVE_0_175_S)
+#define EFUSE_RD_RESERVE_0_175_V  0x0001FFFFU
+#define EFUSE_RD_RESERVE_0_175_S  15
+
+/** EFUSE_RD_MAC_SYS0_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents MAC address. Low 32-bit.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SYS1_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Represents MAC address. High 16-bit.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
+ *  Represents the extended bits of MAC address.
+ */
+#define EFUSE_MAC_EXT    0x0000FFFFU
+#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
+#define EFUSE_MAC_EXT_V  0x0000FFFFU
+#define EFUSE_MAC_EXT_S  16
+
+/** EFUSE_RD_MAC_SYS2_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
+ *  Minor chip version
+ */
+#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_S  0
+/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
+ *  Minor chip version
+ */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  4
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(6))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  6
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
+ *  BLK_VERSION_MINOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  8
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  11
+/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
+ *  Flash capacity
+ */
+#define EFUSE_FLASH_CAP    0x00000007U
+#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
+#define EFUSE_FLASH_CAP_V  0x00000007U
+#define EFUSE_FLASH_CAP_S  13
+/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0;
+ *  Flash vendor
+ */
+#define EFUSE_FLASH_VENDOR    0x00000007U
+#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
+#define EFUSE_FLASH_VENDOR_V  0x00000007U
+#define EFUSE_FLASH_VENDOR_S  16
+/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0;
+ *  Psram capacity
+ */
+#define EFUSE_PSRAM_CAP    0x00000007U
+#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
+#define EFUSE_PSRAM_CAP_V  0x00000007U
+#define EFUSE_PSRAM_CAP_S  19
+/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0;
+ *  Psram vendor
+ */
+#define EFUSE_PSRAM_VENDOR    0x00000003U
+#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
+#define EFUSE_PSRAM_VENDOR_V  0x00000003U
+#define EFUSE_PSRAM_VENDOR_S  22
+/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0;
+ *  Temp (die embedded inside)
+ */
+#define EFUSE_TEMP    0x00000003U
+#define EFUSE_TEMP_M  (EFUSE_TEMP_V << EFUSE_TEMP_S)
+#define EFUSE_TEMP_V  0x00000003U
+#define EFUSE_TEMP_S  24
+/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  26
+/** EFUSE_PA_TRIM_VERSION : R; bitpos: [31:29]; default: 0;
+ *  PADC CAL PA trim version
+ */
+#define EFUSE_PA_TRIM_VERSION    0x00000007U
+#define EFUSE_PA_TRIM_VERSION_M  (EFUSE_PA_TRIM_VERSION_V << EFUSE_PA_TRIM_VERSION_S)
+#define EFUSE_PA_TRIM_VERSION_V  0x00000007U
+#define EFUSE_PA_TRIM_VERSION_S  29
+
+/** EFUSE_RD_MAC_SYS3_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_TRIM_N_BIAS : R; bitpos: [4:0]; default: 0;
+ *  PADC CAL N bias
+ */
+#define EFUSE_TRIM_N_BIAS    0x0000001FU
+#define EFUSE_TRIM_N_BIAS_M  (EFUSE_TRIM_N_BIAS_V << EFUSE_TRIM_N_BIAS_S)
+#define EFUSE_TRIM_N_BIAS_V  0x0000001FU
+#define EFUSE_TRIM_N_BIAS_S  0
+/** EFUSE_TRIM_P_BIAS : R; bitpos: [9:5]; default: 0;
+ *  PADC CAL P bias
+ */
+#define EFUSE_TRIM_P_BIAS    0x0000001FU
+#define EFUSE_TRIM_P_BIAS_M  (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S)
+#define EFUSE_TRIM_P_BIAS_V  0x0000001FU
+#define EFUSE_TRIM_P_BIAS_S  5
+/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [13:10]; default: 0;
+ *  Active HP DBIAS of fixed voltage
+ */
+#define EFUSE_ACTIVE_HP_DBIAS    0x0000000FU
+#define EFUSE_ACTIVE_HP_DBIAS_M  (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
+#define EFUSE_ACTIVE_HP_DBIAS_V  0x0000000FU
+#define EFUSE_ACTIVE_HP_DBIAS_S  10
+/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [17:14]; default: 0;
+ *  Active LP DBIAS of fixed voltage
+ */
+#define EFUSE_ACTIVE_LP_DBIAS    0x0000000FU
+#define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
+#define EFUSE_ACTIVE_LP_DBIAS_V  0x0000000FU
+#define EFUSE_ACTIVE_LP_DBIAS_S  14
+/** EFUSE_LSLP_HP_DBG : R; bitpos: [19:18]; default: 0;
+ *  LSLP HP DBG of fixed voltage
+ */
+#define EFUSE_LSLP_HP_DBG    0x00000003U
+#define EFUSE_LSLP_HP_DBG_M  (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S)
+#define EFUSE_LSLP_HP_DBG_V  0x00000003U
+#define EFUSE_LSLP_HP_DBG_S  18
+/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [23:20]; default: 0;
+ *  LSLP HP DBIAS of fixed voltage
+ */
+#define EFUSE_LSLP_HP_DBIAS    0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_M  (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
+#define EFUSE_LSLP_HP_DBIAS_V  0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_S  20
+/** EFUSE_DSLP_LP_DBG : R; bitpos: [27:24]; default: 0;
+ *  DSLP LP DBG of fixed voltage
+ */
+#define EFUSE_DSLP_LP_DBG    0x0000000FU
+#define EFUSE_DSLP_LP_DBG_M  (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S)
+#define EFUSE_DSLP_LP_DBG_V  0x0000000FU
+#define EFUSE_DSLP_LP_DBG_S  24
+/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [31:28]; default: 0;
+ *  DSLP LP DBIAS of fixed voltage
+ */
+#define EFUSE_DSLP_LP_DBIAS    0x0000000FU
+#define EFUSE_DSLP_LP_DBIAS_M  (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
+#define EFUSE_DSLP_LP_DBIAS_V  0x0000000FU
+#define EFUSE_DSLP_LP_DBIAS_S  28
+
+/** EFUSE_RD_MAC_SYS4_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_DSLP_LP_DBIAS_1 : R; bitpos: [0]; default: 0;
+ *  DSLP LP DBIAS of fixed voltage
+ */
+#define EFUSE_DSLP_LP_DBIAS_1    (BIT(0))
+#define EFUSE_DSLP_LP_DBIAS_1_M  (EFUSE_DSLP_LP_DBIAS_1_V << EFUSE_DSLP_LP_DBIAS_1_S)
+#define EFUSE_DSLP_LP_DBIAS_1_V  0x00000001U
+#define EFUSE_DSLP_LP_DBIAS_1_S  0
+/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [5:1]; default: 0;
+ *  DBIAS gap between LP and HP
+ */
+#define EFUSE_LP_HP_DBIAS_VOL_GAP    0x0000001FU
+#define EFUSE_LP_HP_DBIAS_VOL_GAP_M  (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S)
+#define EFUSE_LP_HP_DBIAS_VOL_GAP_V  0x0000001FU
+#define EFUSE_LP_HP_DBIAS_VOL_GAP_S  1
+/** EFUSE_RESERVED_1_134 : R; bitpos: [31:6]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_134    0x03FFFFFFU
+#define EFUSE_RESERVED_1_134_M  (EFUSE_RESERVED_1_134_V << EFUSE_RESERVED_1_134_S)
+#define EFUSE_RESERVED_1_134_V  0x03FFFFFFU
+#define EFUSE_RESERVED_1_134_S  6
+
+/** EFUSE_RD_MAC_SYS5_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the second 32-bit of zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Represents rd_sys_part1_data0
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Represents rd_sys_part1_data1
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Represents rd_sys_part1_data2
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Represents rd_sys_part1_data3
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Represents rd_sys_part1_data4
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMPERATURE_SENSOR    0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_M  (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
+#define EFUSE_TEMPERATURE_SENSOR_V  0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_S  0
+/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
+ *  ADC OCode
+ */
+#define EFUSE_OCODE    0x000000FFU
+#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
+#define EFUSE_OCODE_V  0x000000FFU
+#define EFUSE_OCODE_S  9
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S  17
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1    0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V  0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S  27
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Represents rd_sys_part1_data5
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1    0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V  0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S  0
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S  5
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S  15
+/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
+ *  HI DOUT of ADC1 atten0
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0    0x0000007FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_V  0x0000007FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_S  25
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Represents rd_sys_part1_data6
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
+ *  HI DOUT of ADC1 atten0
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1    0x00000007U
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V  0x00000007U
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S  0
+/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
+ *  HI DOUT of ADC1 atten1
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_S  3
+/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
+ *  HI DOUT of ADC1 atten2
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_M  (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_S  13
+/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
+ *  HI DOUT of ADC1 atten3
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3    0x000001FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_V  0x000001FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_S  23
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Represents rd_sys_part1_data7
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
+ *  HI DOUT of ADC1 atten3
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1    (BIT(0))
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V  0x00000001U
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S  0
+/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
+ *  Gap between ADC1 CH0 and average initcode
+ */
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S  1
+/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
+ *  Gap between ADC1 CH1 and average initcode
+ */
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S  5
+/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
+ *  Gap between ADC1 CH2 and average initcode
+ */
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S  9
+/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
+ *  Gap between ADC1 CH3 and average initcode
+ */
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S  13
+/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0;
+ *  Gap between ADC1 CH4 and average initcode
+ */
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S  17
+/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [24:21]; default: 0;
+ *  Gap between ADC1 CH5 and average initcode
+ */
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S  21
+/** EFUSE_RESERVED_2_249 : R; bitpos: [31:25]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_249    0x0000007FU
+#define EFUSE_RESERVED_2_249_M  (EFUSE_RESERVED_2_249_V << EFUSE_RESERVED_2_249_S)
+#define EFUSE_RESERVED_2_249_V  0x0000007FU
+#define EFUSE_RESERVED_2_249_S  25
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Represents rd_usr_data0
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Represents rd_usr_data1
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Represents rd_usr_data2
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Represents rd_usr_data3
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Represents rd_usr_data4
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Represents rd_usr_data5
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Represents rd_usr_data6
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Represents rd_usr_data7
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Represents rd_key0_data0
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Represents rd_key0_data1
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Represents rd_key0_data2
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Represents rd_key0_data3
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Represents rd_key0_data4
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Represents rd_key0_data5
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Represents rd_key0_data6
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Represents rd_key0_data7
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Represents rd_key1_data0
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Represents rd_key1_data1
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Represents rd_key1_data2
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Represents rd_key1_data3
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Represents rd_key1_data4
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Represents rd_key1_data5
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Represents rd_key1_data6
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Represents rd_key1_data7
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Represents rd_key2_data0
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Represents rd_key2_data1
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Represents rd_key2_data2
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Represents rd_key2_data3
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Represents rd_key2_data4
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Represents rd_key2_data5
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Represents rd_key2_data6
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Represents rd_key2_data7
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Represents rd_key3_data0
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Represents rd_key3_data1
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Represents rd_key3_data2
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Represents rd_key3_data3
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Represents rd_key3_data4
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Represents rd_key3_data5
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Represents rd_key3_data6
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Represents rd_key3_data7
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Represents rd_key4_data0
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Represents rd_key4_data1
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Represents rd_key4_data2
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Represents rd_key4_data3
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Represents rd_key4_data4
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Represents rd_key4_data5
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Represents rd_key4_data6
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Represents rd_key4_data7
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Represents rd_key5_data0
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Represents rd_key5_data1
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Represents rd_key5_data2
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Represents rd_key5_data3
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Represents rd_key5_data4
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Represents rd_key5_data5
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Represents rd_key5_data6
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Represents rd_key5_data7
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Represents rd_sys_part2_data0
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Represents rd_sys_part2_data1
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Represents rd_sys_part2_data2
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Represents rd_sys_part2_data3
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Represents rd_sys_part2_data4
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Represents rd_sys_part2_data5
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Represents rd_sys_part2_data6
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Represents rd_sys_part2_data7
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_DATA_ERR0_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Represents the programming error of EFUSE_RD_DIS
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_ICACHE
+ */
+#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
+#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_ICACHE_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_JTAG
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
+ *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_TWAI
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_PAD_JTAG
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Represents the programming error of EFUSE_USB_DREFH
+ */
+#define EFUSE_USB_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
+#define EFUSE_USB_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DREFH_ERR_S  21
+/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
+ *  Represents the programming error of EFUSE_USB_DREFL
+ */
+#define EFUSE_USB_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
+#define EFUSE_USB_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DREFL_ERR_S  23
+/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
+ *  Represents the programming error of EFUSE_USB_EXCHG_PINS
+ */
+#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_ERR_S  25
+/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
+ *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
+ */
+#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
+
+/** EFUSE_RD_REPEAT_DATA_ERR1_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [5:4]; default: 0;
+ *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  4
+/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [9:6]; default: 0;
+ *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  6
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [13:10]; default: 0;
+ *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  10
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [14]; default: 0;
+ *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(14))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  14
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_0
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_1
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_DATA_ERR2_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_2
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_3
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_4
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_5
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_EN
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [27]; default: 0;
+ *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
+ */
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR    (BIT(27))
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S)
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S  27
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Represents the programming error of EFUSE_FLASH_TPUW
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_DATA_ERR3_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
+/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
+ *  Represents the programming error of EFUSE_LOCK_KM_KEY
+ */
+#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
+#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_ERR_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
+ *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_VERSION
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
+/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
+ *  Represents the programming error of EFUSE_HYS_EN_PAD
+ */
+#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
+#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
+#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_ERR_S  26
+/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0;
+ *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+ */
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR    0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S)
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V  0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S  27
+/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [29]; default: 0;
+ *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+ */
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR    (BIT(29))
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M  (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S)
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V  0x00000001U
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S  29
+
+/** EFUSE_RD_REPEAT_DATA_ERR4_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
+/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [8:0]; default: 0;
+ *  Represents the programming error of EFUSE_HUK_GEN_STATE
+ */
+#define EFUSE_HUK_GEN_STATE_ERR    0x000001FFU
+#define EFUSE_HUK_GEN_STATE_ERR_M  (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S)
+#define EFUSE_HUK_GEN_STATE_ERR_V  0x000001FFU
+#define EFUSE_HUK_GEN_STATE_ERR_S  0
+/** EFUSE_XTAL_48M_SEL_ERR : RO; bitpos: [11:9]; default: 0;
+ *  Represents the programming error of EFUSE_XTAL_48M_SEL
+ */
+#define EFUSE_XTAL_48M_SEL_ERR    0x00000007U
+#define EFUSE_XTAL_48M_SEL_ERR_M  (EFUSE_XTAL_48M_SEL_ERR_V << EFUSE_XTAL_48M_SEL_ERR_S)
+#define EFUSE_XTAL_48M_SEL_ERR_V  0x00000007U
+#define EFUSE_XTAL_48M_SEL_ERR_S  9
+/** EFUSE_XTAL_48M_SEL_MODE_ERR : RO; bitpos: [12]; default: 0;
+ *  Represents the programming error of EFUSE_XTAL_48M_SEL_MODE
+ */
+#define EFUSE_XTAL_48M_SEL_MODE_ERR    (BIT(12))
+#define EFUSE_XTAL_48M_SEL_MODE_ERR_M  (EFUSE_XTAL_48M_SEL_MODE_ERR_V << EFUSE_XTAL_48M_SEL_MODE_ERR_S)
+#define EFUSE_XTAL_48M_SEL_MODE_ERR_V  0x00000001U
+#define EFUSE_XTAL_48M_SEL_MODE_ERR_S  12
+/** EFUSE_ECDSA_DISABLE_P192_ERR : RO; bitpos: [13]; default: 0;
+ *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
+ */
+#define EFUSE_ECDSA_DISABLE_P192_ERR    (BIT(13))
+#define EFUSE_ECDSA_DISABLE_P192_ERR_M  (EFUSE_ECDSA_DISABLE_P192_ERR_V << EFUSE_ECDSA_DISABLE_P192_ERR_S)
+#define EFUSE_ECDSA_DISABLE_P192_ERR_V  0x00000001U
+#define EFUSE_ECDSA_DISABLE_P192_ERR_S  13
+/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [14]; default: 0;
+ *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+ */
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR    (BIT(14))
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M  (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S)
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V  0x00000001U
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S  14
+
+/** EFUSE_RD_RS_DATA_ERR0_REG register
+ *  Represents rd_rs_data_err
+ */
+#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x190)
+/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS_ERR_NUM    0x00000007U
+#define EFUSE_RD_MAC_SYS_ERR_NUM_M  (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S)
+#define EFUSE_RD_MAC_SYS_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_MAC_SYS_ERR_NUM_S  0
+/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
+ *  of error bytes is over 6.
+ */
+#define EFUSE_RD_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_RD_MAC_SYS_FAIL_M  (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S)
+#define EFUSE_RD_MAC_SYS_FAIL_V  0x00000001U
+#define EFUSE_RD_MAC_SYS_FAIL_S  3
+/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_sys_part1_data
+ */
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S)
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S  4
+/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
+ *  and the number of error bytes is over 6.
+ */
+#define EFUSE_RD_SYS_PART1_DATA_FAIL    (BIT(7))
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_M  (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S)
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_S  7
+/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_usr_data
+ */
+#define EFUSE_RD_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_USR_DATA_ERR_NUM_M  (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S)
+#define EFUSE_RD_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_USR_DATA_ERR_NUM_S  8
+/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_RD_USR_DATA_FAIL_M  (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S)
+#define EFUSE_RD_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_USR_DATA_FAIL_S  11
+/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key0_data
+ */
+#define EFUSE_RD_KEY0_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_M  (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_S  12
+/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY0_DATA_FAIL    (BIT(15))
+#define EFUSE_RD_KEY0_DATA_FAIL_M  (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S)
+#define EFUSE_RD_KEY0_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY0_DATA_FAIL_S  15
+/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key1_data
+ */
+#define EFUSE_RD_KEY1_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_M  (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_S  16
+/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY1_DATA_FAIL    (BIT(19))
+#define EFUSE_RD_KEY1_DATA_FAIL_M  (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S)
+#define EFUSE_RD_KEY1_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY1_DATA_FAIL_S  19
+/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key2_data
+ */
+#define EFUSE_RD_KEY2_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_M  (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_S  20
+/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY2_DATA_FAIL    (BIT(23))
+#define EFUSE_RD_KEY2_DATA_FAIL_M  (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S)
+#define EFUSE_RD_KEY2_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY2_DATA_FAIL_S  23
+/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key3_data
+ */
+#define EFUSE_RD_KEY3_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_M  (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_S  24
+/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY3_DATA_FAIL    (BIT(27))
+#define EFUSE_RD_KEY3_DATA_FAIL_M  (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S)
+#define EFUSE_RD_KEY3_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY3_DATA_FAIL_S  27
+/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key4_data
+ */
+#define EFUSE_RD_KEY4_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_M  (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_S  28
+/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY4_DATA_FAIL    (BIT(31))
+#define EFUSE_RD_KEY4_DATA_FAIL_M  (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S)
+#define EFUSE_RD_KEY4_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY4_DATA_FAIL_S  31
+
+/** EFUSE_RD_RS_DATA_ERR1_REG register
+ *  Represents rd_rs_data_err
+ */
+#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x194)
+/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key5_data
+ */
+#define EFUSE_RD_KEY5_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_M  (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_S  0
+/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY5_DATA_FAIL    (BIT(3))
+#define EFUSE_RD_KEY5_DATA_FAIL_M  (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S)
+#define EFUSE_RD_KEY5_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY5_DATA_FAIL_S  3
+/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S)
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S  4
+/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
+ *  and the number of error bytes is over 6.
+ */
+#define EFUSE_RD_SYS_PART2_DATA_FAIL    (BIT(7))
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_M  (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S)
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_S  7
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x198)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37752960;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to force enable eFuse register configuration clock signal.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
+ *  Configures which block to use for ECDSA key output.
+ */
+#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
+#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_S  16
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Indicates the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Indicates which block is used for ECDSA key output.
+ */
+#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
+#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_S  20
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 22;
+ *  Configures the waiting time of reading eFuse memory.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200;
+ *  Configures the active programming time.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to bypass reed solomon correction step.
+ */
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures block number of programming twice operation.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Set this bit to update multi-bit register signals.
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
+
+/** EFUSE_APB2OTP_WR_DIS_REG register
+ *  eFuse apb2otp block0 data register1.
+ */
+#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x500)
+/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 write disable data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
+ *  eFuse apb2otp block0 data register2.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x504)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
+ *  eFuse apb2otp block0 data register3.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x508)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
+ *  eFuse apb2otp block0 data register4.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x50c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
+ *  eFuse apb2otp block0 data register5.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x510)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
+ *  eFuse apb2otp block0 data register6.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x514)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
+ *  eFuse apb2otp block0 data register7.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x518)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
+ *  eFuse apb2otp block0 data register8.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x51c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
+ *  eFuse apb2otp block0 data register9.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x520)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
+ *  eFuse apb2otp block0 data register10.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x524)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
+ *  eFuse apb2otp block0 data register11.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x528)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
+ *  eFuse apb2otp block0 data register12.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x52c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
+ *  eFuse apb2otp block0 data register13.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x530)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
+ *  eFuse apb2otp block0 data register14.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x534)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
+ *  eFuse apb2otp block0 data register15.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x538)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
+ *  eFuse apb2otp block0 data register16.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x53c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
+ *  eFuse apb2otp block0 data register17.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x540)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
+ *  eFuse apb2otp block0 data register18.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x544)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
+ *  eFuse apb2otp block0 data register19.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x548)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
+ *  eFuse apb2otp block0 data register20.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x54c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
+ *  eFuse apb2otp block0 data register21.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x550)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W1_REG register
+ *  eFuse apb2otp block1 data register1.
+ */
+#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x554)
+/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
+#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK1_W2_REG register
+ *  eFuse apb2otp block1 data register2.
+ */
+#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x558)
+/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
+#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK1_W3_REG register
+ *  eFuse apb2otp block1 data register3.
+ */
+#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x55c)
+/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
+#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK1_W4_REG register
+ *  eFuse apb2otp block1 data register4.
+ */
+#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x560)
+/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
+#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK1_W5_REG register
+ *  eFuse apb2otp block1 data register5.
+ */
+#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x564)
+/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
+#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W6_REG register
+ *  eFuse apb2otp block1 data register6.
+ */
+#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x568)
+/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
+#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_S  0
+
+/** EFUSE_APB2OTP_BLK1_W7_REG register
+ *  eFuse apb2otp block1 data register7.
+ */
+#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x56c)
+/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
+#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_S  0
+
+/** EFUSE_APB2OTP_BLK1_W8_REG register
+ *  eFuse apb2otp block1 data register8.
+ */
+#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x570)
+/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
+#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_S  0
+
+/** EFUSE_APB2OTP_BLK1_W9_REG register
+ *  eFuse apb2otp block1 data register9.
+ */
+#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x574)
+/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
+#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W1_REG register
+ *  eFuse apb2otp block2 data register1.
+ */
+#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x578)
+/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
+#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK2_W2_REG register
+ *  eFuse apb2otp block2 data register2.
+ */
+#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x57c)
+/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
+#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK2_W3_REG register
+ *  eFuse apb2otp block2 data register3.
+ */
+#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x580)
+/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
+#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK2_W4_REG register
+ *  eFuse apb2otp block2 data register4.
+ */
+#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x584)
+/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
+#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK2_W5_REG register
+ *  eFuse apb2otp block2 data register5.
+ */
+#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x588)
+/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
+#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK2_W6_REG register
+ *  eFuse apb2otp block2 data register6.
+ */
+#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x58c)
+/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
+#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_S  0
+
+/** EFUSE_APB2OTP_BLK2_W7_REG register
+ *  eFuse apb2otp block2 data register7.
+ */
+#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x590)
+/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
+#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_S  0
+
+/** EFUSE_APB2OTP_BLK2_W8_REG register
+ *  eFuse apb2otp block2 data register8.
+ */
+#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x594)
+/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
+#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_S  0
+
+/** EFUSE_APB2OTP_BLK2_W9_REG register
+ *  eFuse apb2otp block2 data register9.
+ */
+#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x598)
+/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
+#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W10_REG register
+ *  eFuse apb2otp block2 data register10.
+ */
+#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x59c)
+/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
+#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_S  0
+
+/** EFUSE_APB2OTP_BLK2_W11_REG register
+ *  eFuse apb2otp block2 data register11.
+ */
+#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x5a0)
+/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
+#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_S  0
+
+/** EFUSE_APB2OTP_BLK3_W1_REG register
+ *  eFuse apb2otp block3 data register1.
+ */
+#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x5a4)
+/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
+#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK3_W2_REG register
+ *  eFuse apb2otp block3 data register2.
+ */
+#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x5a8)
+/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
+#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK3_W3_REG register
+ *  eFuse apb2otp block3 data register3.
+ */
+#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x5ac)
+/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
+#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK3_W4_REG register
+ *  eFuse apb2otp block3 data register4.
+ */
+#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x5b0)
+/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
+#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK3_W5_REG register
+ *  eFuse apb2otp block3 data register5.
+ */
+#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x5b4)
+/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
+#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK3_W6_REG register
+ *  eFuse apb2otp block3 data register6.
+ */
+#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x5b8)
+/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
+#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_S  0
+
+/** EFUSE_APB2OTP_BLK3_W7_REG register
+ *  eFuse apb2otp block3 data register7.
+ */
+#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x5bc)
+/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
+#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_S  0
+
+/** EFUSE_APB2OTP_BLK3_W8_REG register
+ *  eFuse apb2otp block3 data register8.
+ */
+#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x5c0)
+/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
+#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_S  0
+
+/** EFUSE_APB2OTP_BLK3_W9_REG register
+ *  eFuse apb2otp block3 data register9.
+ */
+#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x5c4)
+/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
+#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_S  0
+
+/** EFUSE_APB2OTP_BLK3_W10_REG register
+ *  eFuse apb2otp block3 data register10.
+ */
+#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x5c8)
+/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
+#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_S  0
+
+/** EFUSE_APB2OTP_BLK3_W11_REG register
+ *  eFuse apb2otp block3 data register11.
+ */
+#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x5cc)
+/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
+#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_S  0
+
+/** EFUSE_APB2OTP_BLK4_W1_REG register
+ *  eFuse apb2otp BLOCK7 data register1.
+ */
+#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x5d0)
+/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
+#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK4_W2_REG register
+ *  eFuse apb2otp block4 data register2.
+ */
+#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x5d4)
+/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
+#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK4_W3_REG register
+ *  eFuse apb2otp block4 data register3.
+ */
+#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x5d8)
+/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
+#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK4_W4_REG register
+ *  eFuse apb2otp block4 data register4.
+ */
+#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x5dc)
+/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
+#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK4_W5_REG register
+ *  eFuse apb2otp block4 data register5.
+ */
+#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x5e0)
+/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
+#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK4_W6_REG register
+ *  eFuse apb2otp block4 data register6.
+ */
+#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x5e4)
+/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
+#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_S  0
+
+/** EFUSE_APB2OTP_BLK4_W7_REG register
+ *  eFuse apb2otp block4 data register7.
+ */
+#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x5e8)
+/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
+#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_S  0
+
+/** EFUSE_APB2OTP_BLK4_W8_REG register
+ *  eFuse apb2otp block4 data register8.
+ */
+#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x5ec)
+/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
+#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_S  0
+
+/** EFUSE_APB2OTP_BLK4_W9_REG register
+ *  eFuse apb2otp block4 data register9.
+ */
+#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x5f0)
+/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
+#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_S  0
+
+/** EFUSE_APB2OTP_BLK4_W10_REG register
+ *  eFuse apb2otp block4 data registe10.
+ */
+#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x5f4)
+/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
+#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_S  0
+
+/** EFUSE_APB2OTP_BLK4_W11_REG register
+ *  eFuse apb2otp block4 data register11.
+ */
+#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x5f8)
+/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
+#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_S  0
+
+/** EFUSE_APB2OTP_BLK5_W1_REG register
+ *  eFuse apb2otp block5 data register1.
+ */
+#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x5fc)
+/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
+#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_S  0
+
+/** EFUSE_APB2OTP_BLK5_W2_REG register
+ *  eFuse apb2otp block5 data register2.
+ */
+#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x600)
+/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
+#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_S  0
+
+/** EFUSE_APB2OTP_BLK5_W3_REG register
+ *  eFuse apb2otp block5 data register3.
+ */
+#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x604)
+/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
+#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_S  0
+
+/** EFUSE_APB2OTP_BLK5_W4_REG register
+ *  eFuse apb2otp block5 data register4.
+ */
+#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x608)
+/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
+#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_S  0
+
+/** EFUSE_APB2OTP_BLK5_W5_REG register
+ *  eFuse apb2otp block5 data register5.
+ */
+#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x60c)
+/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
+#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_S  0
+
+/** EFUSE_APB2OTP_BLK5_W6_REG register
+ *  eFuse apb2otp block5 data register6.
+ */
+#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x610)
+/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
+#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_S  0
+
+/** EFUSE_APB2OTP_BLK5_W7_REG register
+ *  eFuse apb2otp block5 data register7.
+ */
+#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x614)
+/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
+#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_S  0
+
+/** EFUSE_APB2OTP_BLK5_W8_REG register
+ *  eFuse apb2otp block5 data register8.
+ */
+#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x618)
+/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
+#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_S  0
+
+/** EFUSE_APB2OTP_BLK5_W9_REG register
+ *  eFuse apb2otp block5 data register9.
+ */
+#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x61c)
+/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
+#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_S  0
+
+/** EFUSE_APB2OTP_BLK5_W10_REG register
+ *  eFuse apb2otp block5 data register10.
+ */
+#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x620)
+/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
+#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_S  0
+
+/** EFUSE_APB2OTP_BLK5_W11_REG register
+ *  eFuse apb2otp block5 data register11.
+ */
+#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x624)
+/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
+#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_S  0
+
+/** EFUSE_APB2OTP_BLK6_W1_REG register
+ *  eFuse apb2otp block6 data register1.
+ */
+#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x628)
+/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
+#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_S  0
+
+/** EFUSE_APB2OTP_BLK6_W2_REG register
+ *  eFuse apb2otp block6 data register2.
+ */
+#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x62c)
+/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
+#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_S  0
+
+/** EFUSE_APB2OTP_BLK6_W3_REG register
+ *  eFuse apb2otp block6 data register3.
+ */
+#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x630)
+/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
+#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_S  0
+
+/** EFUSE_APB2OTP_BLK6_W4_REG register
+ *  eFuse apb2otp block6 data register4.
+ */
+#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x634)
+/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
+#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_S  0
+
+/** EFUSE_APB2OTP_BLK6_W5_REG register
+ *  eFuse apb2otp block6 data register5.
+ */
+#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x638)
+/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
+#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_S  0
+
+/** EFUSE_APB2OTP_BLK6_W6_REG register
+ *  eFuse apb2otp block6 data register6.
+ */
+#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x63c)
+/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
+#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_S  0
+
+/** EFUSE_APB2OTP_BLK6_W7_REG register
+ *  eFuse apb2otp block6 data register7.
+ */
+#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x640)
+/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
+#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_S  0
+
+/** EFUSE_APB2OTP_BLK6_W8_REG register
+ *  eFuse apb2otp block6 data register8.
+ */
+#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x644)
+/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
+#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_S  0
+
+/** EFUSE_APB2OTP_BLK6_W9_REG register
+ *  eFuse apb2otp block6 data register9.
+ */
+#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x648)
+/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
+#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_S  0
+
+/** EFUSE_APB2OTP_BLK6_W10_REG register
+ *  eFuse apb2otp block6 data register10.
+ */
+#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x64c)
+/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
+#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_S  0
+
+/** EFUSE_APB2OTP_BLK6_W11_REG register
+ *  eFuse apb2otp block6 data register11.
+ */
+#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x650)
+/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
+#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_S  0
+
+/** EFUSE_APB2OTP_BLK7_W1_REG register
+ *  eFuse apb2otp block7 data register1.
+ */
+#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x654)
+/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
+#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_S  0
+
+/** EFUSE_APB2OTP_BLK7_W2_REG register
+ *  eFuse apb2otp block7 data register2.
+ */
+#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x658)
+/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
+#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_S  0
+
+/** EFUSE_APB2OTP_BLK7_W3_REG register
+ *  eFuse apb2otp block7 data register3.
+ */
+#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x65c)
+/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
+#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_S  0
+
+/** EFUSE_APB2OTP_BLK7_W4_REG register
+ *  eFuse apb2otp block7 data register4.
+ */
+#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x660)
+/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
+#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_S  0
+
+/** EFUSE_APB2OTP_BLK7_W5_REG register
+ *  eFuse apb2otp block7 data register5.
+ */
+#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x664)
+/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
+#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_S  0
+
+/** EFUSE_APB2OTP_BLK7_W6_REG register
+ *  eFuse apb2otp block7 data register6.
+ */
+#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x668)
+/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
+#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_S  0
+
+/** EFUSE_APB2OTP_BLK7_W7_REG register
+ *  eFuse apb2otp block7 data register7.
+ */
+#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x66c)
+/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
+#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_S  0
+
+/** EFUSE_APB2OTP_BLK7_W8_REG register
+ *  eFuse apb2otp block7 data register8.
+ */
+#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x670)
+/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
+#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_S  0
+
+/** EFUSE_APB2OTP_BLK7_W9_REG register
+ *  eFuse apb2otp block7 data register9.
+ */
+#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x674)
+/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
+#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_S  0
+
+/** EFUSE_APB2OTP_BLK7_W10_REG register
+ *  eFuse apb2otp block7 data register10.
+ */
+#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x678)
+/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
+#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_S  0
+
+/** EFUSE_APB2OTP_BLK7_W11_REG register
+ *  eFuse apb2otp block7 data register11.
+ */
+#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x67c)
+/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
+#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_S  0
+
+/** EFUSE_APB2OTP_BLK8_W1_REG register
+ *  eFuse apb2otp block8 data register1.
+ */
+#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x680)
+/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
+#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_S  0
+
+/** EFUSE_APB2OTP_BLK8_W2_REG register
+ *  eFuse apb2otp block8 data register2.
+ */
+#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x684)
+/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
+#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_S  0
+
+/** EFUSE_APB2OTP_BLK8_W3_REG register
+ *  eFuse apb2otp block8 data register3.
+ */
+#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x688)
+/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
+#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_S  0
+
+/** EFUSE_APB2OTP_BLK8_W4_REG register
+ *  eFuse apb2otp block8 data register4.
+ */
+#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x68c)
+/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
+#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_S  0
+
+/** EFUSE_APB2OTP_BLK8_W5_REG register
+ *  eFuse apb2otp block8 data register5.
+ */
+#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x690)
+/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
+#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_S  0
+
+/** EFUSE_APB2OTP_BLK8_W6_REG register
+ *  eFuse apb2otp block8 data register6.
+ */
+#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x694)
+/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
+#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_S  0
+
+/** EFUSE_APB2OTP_BLK8_W7_REG register
+ *  eFuse apb2otp block8 data register7.
+ */
+#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x698)
+/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
+#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_S  0
+
+/** EFUSE_APB2OTP_BLK8_W8_REG register
+ *  eFuse apb2otp block8 data register8.
+ */
+#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x69c)
+/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
+#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_S  0
+
+/** EFUSE_APB2OTP_BLK8_W9_REG register
+ *  eFuse apb2otp block8 data register9.
+ */
+#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x6a0)
+/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
+#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_S  0
+
+/** EFUSE_APB2OTP_BLK8_W10_REG register
+ *  eFuse apb2otp block8 data register10.
+ */
+#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x6a4)
+/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
+#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_S  0
+
+/** EFUSE_APB2OTP_BLK8_W11_REG register
+ *  eFuse apb2otp block8 data register11.
+ */
+#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x6a8)
+/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
+#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_S  0
+
+/** EFUSE_APB2OTP_BLK9_W1_REG register
+ *  eFuse apb2otp block9 data register1.
+ */
+#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x6ac)
+/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
+#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_S  0
+
+/** EFUSE_APB2OTP_BLK9_W2_REG register
+ *  eFuse apb2otp block9 data register2.
+ */
+#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x6b0)
+/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
+#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_S  0
+
+/** EFUSE_APB2OTP_BLK9_W3_REG register
+ *  eFuse apb2otp block9 data register3.
+ */
+#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x6b4)
+/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
+#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_S  0
+
+/** EFUSE_APB2OTP_BLK9_W4_REG register
+ *  eFuse apb2otp block9 data register4.
+ */
+#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x6b8)
+/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
+#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_S  0
+
+/** EFUSE_APB2OTP_BLK9_W5_REG register
+ *  eFuse apb2otp block9 data register5.
+ */
+#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x6bc)
+/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
+#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_S  0
+
+/** EFUSE_APB2OTP_BLK9_W6_REG register
+ *  eFuse apb2otp block9 data register6.
+ */
+#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x6c0)
+/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
+#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_S  0
+
+/** EFUSE_APB2OTP_BLK9_W7_REG register
+ *  eFuse apb2otp block9 data register7.
+ */
+#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x6c4)
+/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
+#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_S  0
+
+/** EFUSE_APB2OTP_BLK9_W8_REG register
+ *  eFuse apb2otp block9 data register8.
+ */
+#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x6c8)
+/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
+#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_S  0
+
+/** EFUSE_APB2OTP_BLK9_W9_REG register
+ *  eFuse apb2otp block9 data register9.
+ */
+#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x6cc)
+/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
+#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_S  0
+
+/** EFUSE_APB2OTP_BLK9_W10_REG register
+ *  eFuse apb2otp block9 data register10.
+ */
+#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x6d0)
+/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
+#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_S  0
+
+/** EFUSE_APB2OTP_BLK9_W11_REG register
+ *  eFuse apb2otp block9 data register11.
+ */
+#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x6d4)
+/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
+#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_S  0
+
+/** EFUSE_APB2OTP_BLK10_W1_REG register
+ *  eFuse apb2otp block10 data register1.
+ */
+#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x6d8)
+/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
+#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_S  0
+
+/** EFUSE_APB2OTP_BLK10_W2_REG register
+ *  eFuse apb2otp block10 data register2.
+ */
+#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x6dc)
+/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
+#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_S  0
+
+/** EFUSE_APB2OTP_BLK10_W3_REG register
+ *  eFuse apb2otp block10 data register3.
+ */
+#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x6e0)
+/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
+#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_S  0
+
+/** EFUSE_APB2OTP_BLK10_W4_REG register
+ *  eFuse apb2otp block10 data register4.
+ */
+#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x6e4)
+/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
+#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_S  0
+
+/** EFUSE_APB2OTP_BLK10_W5_REG register
+ *  eFuse apb2otp block10 data register5.
+ */
+#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x6e8)
+/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
+#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_S  0
+
+/** EFUSE_APB2OTP_BLK10_W6_REG register
+ *  eFuse apb2otp block10 data register6.
+ */
+#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x6ec)
+/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
+#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_S  0
+
+/** EFUSE_APB2OTP_BLK10_W7_REG register
+ *  eFuse apb2otp block10 data register7.
+ */
+#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x6f0)
+/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
+#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_S  0
+
+/** EFUSE_APB2OTP_BLK10_W8_REG register
+ *  eFuse apb2otp block10 data register8.
+ */
+#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x6f4)
+/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
+#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_S  0
+
+/** EFUSE_APB2OTP_BLK10_W9_REG register
+ *  eFuse apb2otp block10 data register9.
+ */
+#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x6f8)
+/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
+#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_S  0
+
+/** EFUSE_APB2OTP_BLK10_W10_REG register
+ *  eFuse apb2otp block10 data register10.
+ */
+#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x6fc)
+/** EFUSE_APB2OTP_BLOCK10_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W10_M  (EFUSE_APB2OTP_BLOCK10_W10_V << EFUSE_APB2OTP_BLOCK10_W10_S)
+#define EFUSE_APB2OTP_BLOCK10_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W10_S  0
+
+/** EFUSE_APB2OTP_BLK10_W11_REG register
+ *  eFuse apb2otp block10 data register11.
+ */
+#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0x700)
+/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
+#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_S  0
+
+/** EFUSE_APB2OTP_EN_REG register
+ *  eFuse apb2otp enable configuration register.
+ */
+#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0x708)
+/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
+ *  Apb2otp mode enable signal.
+ */
+#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
+#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
+#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
+#define EFUSE_APB2OTP_APB2OTP_EN_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/register/soc/efuse_struct.h b/components/soc/esp32c5/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..8e614477830
--- /dev/null
+++ b/components/soc/esp32c5/register/soc/efuse_struct.h
@@ -0,0 +1,4654 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: buffer0 registers */
+/** Type of pgm_data0 register
+ *  Represents pgm_data0
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Represents pgm_data1
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Represents pgm_data2
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Represents pgm_data3
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Represents pgm_data4
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Represents pgm_data5
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Represents pgm_data6
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Represents pgm_data7
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+
+/** Group: buffer1 registers */
+/** Type of pgm_check_value0 register
+ *  Represents pgm_check_value0
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Represents pgm_check_value1
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Represents pgm_check_value2
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: block0 registers */
+/** Type of rd_wr_dis0 register
+ *  Represents rd_wr_dis
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled or
+         *  enabled.\\ 1: Disabled\\ 0: Enabled\\
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis0_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t rd_dis:7;
+        /** rd_reserve_0_39 : RW; bitpos: [7]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_39:1;
+        /** dis_icache : RO; bitpos: [8]; default: 0;
+         *  Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t dis_icache:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
+         *  disabled\\ 0: enabled\\
+         */
+        uint32_t dis_usb_jtag:1;
+        /** rd_reserve_0_42 : RW; bitpos: [10]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_42:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
+         *  enabled\\
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Represents whether SPI0 controller during boot_mode_download is disabled or
+         *  enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0:
+         *  enabled\\
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         *  is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even
+         *  number: enabled\\
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
+         *  0: enabled\\
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode).\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
+         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
+         */
+        uint32_t usb_drefh:2;
+        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
+         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
+         */
+        uint32_t usb_drefl:2;
+        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
+         *  Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not
+         *  exchanged\\
+         */
+        uint32_t usb_exchg_pins:1;
+        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
+         *  Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not
+         *  functioned\\
+         */
+        uint32_t vdd_spi_as_gpio:1;
+        /** rd_reserve_0_59 : RW; bitpos: [31:27]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_59:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** km_disable_deploy_mode : RO; bitpos: [3:0]; default: 0;
+         *  Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled
+         *  \\ 0: enabled.\\
+         */
+        uint32_t km_disable_deploy_mode:4;
+        /** km_rnd_switch_cycle : RO; bitpos: [5:4]; default: 0;
+         *  Set the bits to control key manager random number switch cycle. 0: control by
+         *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+         */
+        uint32_t km_rnd_switch_cycle:2;
+        /** km_deploy_only_once : RO; bitpos: [9:6]; default: 0;
+         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+         *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
+         */
+        uint32_t km_deploy_only_once:4;
+        /** force_use_key_manager_key : RO; bitpos: [13:10]; default: 0;
+         *  Set each bit to control whether corresponding key must come from key manager. 1 is
+         *  true, 0 is false. bit 0: ecsda, bit 1: xts, bit2: hmac, bit3: ds
+         */
+        uint32_t force_use_key_manager_key:4;
+        /** force_disable_sw_init_key : RO; bitpos: [14]; default: 0;
+         *  Set this bit to disable software written init key, and force use efuse_init_key.
+         */
+        uint32_t force_disable_sw_init_key:1;
+        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_79:1;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original
+         *  threshold configuration value of STG0 *2 \\1: Original threshold configuration
+         *  value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3:
+         *  Original threshold configuration value of STG0 *16 \\
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
+         *  1: enabled\\ Even number of 1: disabled\\
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
+         *  enabled\\ 0: disabled\\
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
+         *  enabled\\ 0: disabled\\
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
+         *  enabled\\ 0: disabled\\
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Represents the purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** rd_reserve_0_114 : RW; bitpos: [19:18]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_114:2;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
+         *  enabled.\\ 0: disabled\\
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** rd_reserve_0_118 : RW; bitpos: [26:22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_118:5;
+        /** km_xts_key_length_256 : RO; bitpos: [27]; default: 0;
+         *  Set this bitto configure flash encryption use xts-128 key. else use xts-256 key.
+         */
+        uint32_t km_xts_key_length_256:1;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+         *  is 2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0:
+         *  enabled\\
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0:
+         *  enabled\\
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1:
+         *  disabled\\ 0: enabled\\
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** lock_km_key : RO; bitpos: [3]; default: 0;
+         *  Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\
+         */
+        uint32_t lock_km_key:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
+         *  1: Disable\\ 0: Enable\\
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0:
+         *  disabled\\
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable
+         *  printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset
+         *  at high level\\ 11: force disable printing\\
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [8]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot.\\
+         *  1: forced\\ 0:not forced\\
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [24:9]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
+         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+         *  enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [26]; default: 0;
+         *  Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
+         *  enabled\\ 0:disabled\\
+         */
+        uint32_t hys_en_pad:1;
+        /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0;
+         *  Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2:
+         *  Moderate 1. Low\\ 0: Disabled\\
+         */
+        uint32_t xts_dpa_pseudo_level:2;
+        /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0;
+         *  Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0:
+         *  Disable.\\
+         */
+        uint32_t xts_dpa_clk_enable:1;
+        /** rd_reserve_0_158 : RW; bitpos: [31:30]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_158:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** huk_gen_state : RO; bitpos: [8:0]; default: 0;
+         *  Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\
+         *  Even of 1 is valid.\\
+         */
+        uint32_t huk_gen_state:9;
+        /** xtal_48m_sel : RO; bitpos: [11:9]; default: 0;
+         *  Represents whether XTAL frequency is 48MHz or not. If not, 40MHz XTAL will be used.
+         *  If this field contains Odd number bit '1': Enable 48MHz XTAL\\ Even number bit '1':
+         *  Enable 40MHz XTAL.
+         */
+        uint32_t xtal_48m_sel:3;
+        /** xtal_48m_sel_mode : RO; bitpos: [12]; default: 0;
+         *  Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1:
+         *  eFuse\\ 0: strapping-PAD-state.
+         */
+        uint32_t xtal_48m_sel_mode:1;
+        /** ecdsa_disable_p192 : RO; bitpos: [13]; default: 0;
+         *  Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable.
+         */
+        uint32_t ecdsa_disable_p192:1;
+        /** ecc_force_const_time : RO; bitpos: [14]; default: 0;
+         *  Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
+         *  \\ 0: Disable.
+         */
+        uint32_t ecc_force_const_time:1;
+        /** rd_reserve_0_175 : RW; bitpos: [31:15]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_175:17;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+
+/** Group: block1 registers */
+/** Type of rd_mac_sys0 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents MAC address. Low 32-bit.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys0_reg_t;
+
+/** Type of rd_mac_sys1 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Represents MAC address. High 16-bit.
+         */
+        uint32_t mac_1:16;
+        /** mac_ext : RO; bitpos: [31:16]; default: 0;
+         *  Represents the extended bits of MAC address.
+         */
+        uint32_t mac_ext:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys1_reg_t;
+
+/** Type of rd_mac_sys2 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** wafer_version_minor : R; bitpos: [3:0]; default: 0;
+         *  Minor chip version
+         */
+        uint32_t wafer_version_minor:4;
+        /** wafer_version_major : R; bitpos: [5:4]; default: 0;
+         *  Minor chip version
+         */
+        uint32_t wafer_version_major:2;
+        /** disable_wafer_version_major : R; bitpos: [6]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** blk_version_minor : R; bitpos: [10:8]; default: 0;
+         *  BLK_VERSION_MINOR of BLOCK2
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [12:11]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+        /** flash_cap : R; bitpos: [15:13]; default: 0;
+         *  Flash capacity
+         */
+        uint32_t flash_cap:3;
+        /** flash_vendor : R; bitpos: [18:16]; default: 0;
+         *  Flash vendor
+         */
+        uint32_t flash_vendor:3;
+        /** psram_cap : R; bitpos: [21:19]; default: 0;
+         *  Psram capacity
+         */
+        uint32_t psram_cap:3;
+        /** psram_vendor : R; bitpos: [23:22]; default: 0;
+         *  Psram vendor
+         */
+        uint32_t psram_vendor:2;
+        /** temp : R; bitpos: [25:24]; default: 0;
+         *  Temp (die embedded inside)
+         */
+        uint32_t temp:2;
+        /** pkg_version : R; bitpos: [28:26]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** pa_trim_version : R; bitpos: [31:29]; default: 0;
+         *  PADC CAL PA trim version
+         */
+        uint32_t pa_trim_version:3;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys2_reg_t;
+
+/** Type of rd_mac_sys3 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** trim_n_bias : R; bitpos: [4:0]; default: 0;
+         *  PADC CAL N bias
+         */
+        uint32_t trim_n_bias:5;
+        /** trim_p_bias : R; bitpos: [9:5]; default: 0;
+         *  PADC CAL P bias
+         */
+        uint32_t trim_p_bias:5;
+        /** active_hp_dbias : R; bitpos: [13:10]; default: 0;
+         *  Active HP DBIAS of fixed voltage
+         */
+        uint32_t active_hp_dbias:4;
+        /** active_lp_dbias : R; bitpos: [17:14]; default: 0;
+         *  Active LP DBIAS of fixed voltage
+         */
+        uint32_t active_lp_dbias:4;
+        /** lslp_hp_dbg : R; bitpos: [19:18]; default: 0;
+         *  LSLP HP DBG of fixed voltage
+         */
+        uint32_t lslp_hp_dbg:2;
+        /** lslp_hp_dbias : R; bitpos: [23:20]; default: 0;
+         *  LSLP HP DBIAS of fixed voltage
+         */
+        uint32_t lslp_hp_dbias:4;
+        /** dslp_lp_dbg : R; bitpos: [27:24]; default: 0;
+         *  DSLP LP DBG of fixed voltage
+         */
+        uint32_t dslp_lp_dbg:4;
+        /** dslp_lp_dbias : R; bitpos: [31:28]; default: 0;
+         *  DSLP LP DBIAS of fixed voltage
+         */
+        uint32_t dslp_lp_dbias:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys3_reg_t;
+
+/** Type of rd_mac_sys4 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** dslp_lp_dbias_1 : R; bitpos: [0]; default: 0;
+         *  DSLP LP DBIAS of fixed voltage
+         */
+        uint32_t dslp_lp_dbias_1:1;
+        /** lp_hp_dbias_vol_gap : R; bitpos: [5:1]; default: 0;
+         *  DBIAS gap between LP and HP
+         */
+        uint32_t lp_hp_dbias_vol_gap:5;
+        /** reserved_1_134 : R; bitpos: [31:6]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_134:26;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys4_reg_t;
+
+/** Type of rd_mac_sys5 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the second 32-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys5_reg_t;
+
+
+/** Group: block2 registers */
+/** Type of rd_sys_part1_data0 register
+ *  Represents rd_sys_part1_data0
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Represents rd_sys_part1_data1
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Represents rd_sys_part1_data2
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Represents rd_sys_part1_data3
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Represents rd_sys_part1_data4
+ */
+typedef union {
+    struct {
+        /** temperature_sensor : R; bitpos: [8:0]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temperature_sensor:9;
+        /** ocode : R; bitpos: [16:9]; default: 0;
+         *  ADC OCode
+         */
+        uint32_t ocode:8;
+        /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_initcode_atten0:10;
+        /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_initcode_atten1:5;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Represents rd_sys_part1_data5
+ */
+typedef union {
+    struct {
+        /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_initcode_atten1_1:5;
+        /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_initcode_atten2:10;
+        /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_initcode_atten3:10;
+        /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
+         *  HI DOUT of ADC1 atten0
+         */
+        uint32_t adc1_hi_dout_atten0:7;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Represents rd_sys_part1_data6
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
+         *  HI DOUT of ADC1 atten0
+         */
+        uint32_t adc1_hi_dout_atten0_1:3;
+        /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
+         *  HI DOUT of ADC1 atten1
+         */
+        uint32_t adc1_hi_dout_atten1:10;
+        /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
+         *  HI DOUT of ADC1 atten2
+         */
+        uint32_t adc1_hi_dout_atten2:10;
+        /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
+         *  HI DOUT of ADC1 atten3
+         */
+        uint32_t adc1_hi_dout_atten3:9;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Represents rd_sys_part1_data7
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
+         *  HI DOUT of ADC1 atten3
+         */
+        uint32_t adc1_hi_dout_atten3_1:1;
+        /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
+         *  Gap between ADC1 CH0 and average initcode
+         */
+        uint32_t adc1_ch0_atten0_initcode_diff:4;
+        /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
+         *  Gap between ADC1 CH1 and average initcode
+         */
+        uint32_t adc1_ch1_atten0_initcode_diff:4;
+        /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
+         *  Gap between ADC1 CH2 and average initcode
+         */
+        uint32_t adc1_ch2_atten0_initcode_diff:4;
+        /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
+         *  Gap between ADC1 CH3 and average initcode
+         */
+        uint32_t adc1_ch3_atten0_initcode_diff:4;
+        /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0;
+         *  Gap between ADC1 CH4 and average initcode
+         */
+        uint32_t adc1_ch4_atten0_initcode_diff:4;
+        /** adc1_ch5_atten0_initcode_diff : R; bitpos: [24:21]; default: 0;
+         *  Gap between ADC1 CH5 and average initcode
+         */
+        uint32_t adc1_ch5_atten0_initcode_diff:4;
+        /** reserved_2_249 : R; bitpos: [31:25]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_249:7;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+
+/** Group: block3 registers */
+/** Type of rd_usr_data0 register
+ *  Represents rd_usr_data0
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Represents rd_usr_data1
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Represents rd_usr_data2
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Represents rd_usr_data3
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Represents rd_usr_data4
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Represents rd_usr_data5
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Represents rd_usr_data6
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Represents rd_usr_data7
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+
+/** Group: block4 registers */
+/** Type of rd_key0_data0 register
+ *  Represents rd_key0_data0
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Represents rd_key0_data1
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Represents rd_key0_data2
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Represents rd_key0_data3
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Represents rd_key0_data4
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Represents rd_key0_data5
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Represents rd_key0_data6
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Represents rd_key0_data7
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+
+/** Group: block5 registers */
+/** Type of rd_key1_data0 register
+ *  Represents rd_key1_data0
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Represents rd_key1_data1
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Represents rd_key1_data2
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Represents rd_key1_data3
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Represents rd_key1_data4
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Represents rd_key1_data5
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Represents rd_key1_data6
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Represents rd_key1_data7
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+
+/** Group: block6 registers */
+/** Type of rd_key2_data0 register
+ *  Represents rd_key2_data0
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Represents rd_key2_data1
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Represents rd_key2_data2
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Represents rd_key2_data3
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Represents rd_key2_data4
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Represents rd_key2_data5
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Represents rd_key2_data6
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Represents rd_key2_data7
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+
+/** Group: block7 registers */
+/** Type of rd_key3_data0 register
+ *  Represents rd_key3_data0
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Represents rd_key3_data1
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Represents rd_key3_data2
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Represents rd_key3_data3
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Represents rd_key3_data4
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Represents rd_key3_data5
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Represents rd_key3_data6
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Represents rd_key3_data7
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+
+/** Group: block8 registers */
+/** Type of rd_key4_data0 register
+ *  Represents rd_key4_data0
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Represents rd_key4_data1
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Represents rd_key4_data2
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Represents rd_key4_data3
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Represents rd_key4_data4
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Represents rd_key4_data5
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Represents rd_key4_data6
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Represents rd_key4_data7
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+
+/** Group: block9 registers */
+/** Type of rd_key5_data0 register
+ *  Represents rd_key5_data0
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Represents rd_key5_data1
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Represents rd_key5_data2
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Represents rd_key5_data3
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Represents rd_key5_data4
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Represents rd_key5_data5
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Represents rd_key5_data6
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Represents rd_key5_data7
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+
+/** Group: block10 registers */
+/** Type of rd_sys_part2_data0 register
+ *  Represents rd_sys_part2_data0
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Represents rd_sys_part2_data1
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Represents rd_sys_part2_data2
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Represents rd_sys_part2_data3
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Represents rd_sys_part2_data4
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Represents rd_sys_part2_data5
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Represents rd_sys_part2_data6
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Represents rd_sys_part2_data7
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+
+/** Group: block0 error report registers */
+/** Type of rd_repeat_data_err0 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Represents the programming error of EFUSE_RD_DIS
+         */
+        uint32_t rd_dis_err:7;
+        uint32_t reserved_7:1;
+        /** dis_icache_err : RO; bitpos: [8]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_ICACHE
+         */
+        uint32_t dis_icache_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_JTAG
+         */
+        uint32_t dis_usb_jtag_err:1;
+        uint32_t reserved_10:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_TWAI
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  Represents the programming error of EFUSE_USB_DREFH
+         */
+        uint32_t usb_drefh_err:2;
+        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
+         *  Represents the programming error of EFUSE_USB_DREFL
+         */
+        uint32_t usb_drefl_err:2;
+        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_USB_EXCHG_PINS
+         */
+        uint32_t usb_exchg_pins_err:1;
+        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
+         */
+        uint32_t vdd_spi_as_gpio_err:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err0_reg_t;
+
+/** Type of rd_repeat_data_err1 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** km_disable_deploy_mode_err : RO; bitpos: [3:0]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
+         */
+        uint32_t km_disable_deploy_mode_err:4;
+        /** km_rnd_switch_cycle_err : RO; bitpos: [5:4]; default: 0;
+         *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
+         */
+        uint32_t km_rnd_switch_cycle_err:2;
+        /** km_deploy_only_once_err : RO; bitpos: [9:6]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
+         */
+        uint32_t km_deploy_only_once_err:4;
+        /** force_use_key_manager_key_err : RO; bitpos: [13:10]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
+         */
+        uint32_t force_use_key_manager_key_err:4;
+        /** force_disable_sw_init_key_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
+         */
+        uint32_t force_disable_sw_init_key_err:1;
+        uint32_t reserved_15:1;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err1_reg_t;
+
+/** Type of rd_repeat_data_err2 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
+         */
+        uint32_t sec_dpa_level_err:2;
+        uint32_t reserved_18:2;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        uint32_t reserved_22:5;
+        /** km_xts_key_length_256_err : RO; bitpos: [27]; default: 0;
+         *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
+         */
+        uint32_t km_xts_key_length_256_err:1;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Represents the programming error of EFUSE_FLASH_TPUW
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err2_reg_t;
+
+/** Type of rd_repeat_data_err3 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_LOCK_KM_KEY
+         */
+        uint32_t lock_km_key_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_VERSION
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_HYS_EN_PAD
+         */
+        uint32_t hys_en_pad_err:1;
+        /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+         */
+        uint32_t xts_dpa_pseudo_level_err:2;
+        /** xts_dpa_clk_enable_err : RO; bitpos: [29]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+         */
+        uint32_t xts_dpa_clk_enable_err:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err3_reg_t;
+
+/** Type of rd_repeat_data_err4 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** huk_gen_state_err : RO; bitpos: [8:0]; default: 0;
+         *  Represents the programming error of EFUSE_HUK_GEN_STATE
+         */
+        uint32_t huk_gen_state_err:9;
+        /** xtal_48m_sel_err : RO; bitpos: [11:9]; default: 0;
+         *  Represents the programming error of EFUSE_XTAL_48M_SEL
+         */
+        uint32_t xtal_48m_sel_err:3;
+        /** xtal_48m_sel_mode_err : RO; bitpos: [12]; default: 0;
+         *  Represents the programming error of EFUSE_XTAL_48M_SEL_MODE
+         */
+        uint32_t xtal_48m_sel_mode_err:1;
+        /** ecdsa_disable_p192_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
+         */
+        uint32_t ecdsa_disable_p192_err:1;
+        /** ecc_force_const_time_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+         */
+        uint32_t ecc_force_const_time_err:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err4_reg_t;
+
+
+/** Group: RS block error report registers */
+/** Type of rd_rs_data_err0 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_mac_sys
+         */
+        uint32_t rd_mac_sys_err_num:3;
+        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
+         *  of error bytes is over 6.
+         */
+        uint32_t rd_mac_sys_fail:1;
+        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_sys_part1_data
+         */
+        uint32_t rd_sys_part1_data_err_num:3;
+        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
+         *  and the number of error bytes is over 6.
+         */
+        uint32_t rd_sys_part1_data_fail:1;
+        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_usr_data
+         */
+        uint32_t rd_usr_data_err_num:3;
+        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_usr_data_fail:1;
+        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key0_data
+         */
+        uint32_t rd_key0_data_err_num:3;
+        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key0_data_fail:1;
+        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key1_data
+         */
+        uint32_t rd_key1_data_err_num:3;
+        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key1_data_fail:1;
+        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key2_data
+         */
+        uint32_t rd_key2_data_err_num:3;
+        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key2_data_fail:1;
+        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key3_data
+         */
+        uint32_t rd_key3_data_err_num:3;
+        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key3_data_fail:1;
+        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key4_data
+         */
+        uint32_t rd_key4_data_err_num:3;
+        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key4_data_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err0_reg_t;
+
+/** Type of rd_rs_data_err1 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key5_data
+         */
+        uint32_t rd_key5_data_err_num:3;
+        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key5_data_fail:1;
+        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_sys_part2_data
+         */
+        uint32_t rd_sys_part2_data_err_num:3;
+        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
+         *  and the number of error bytes is over 6.
+         */
+        uint32_t rd_sys_part2_data_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err1_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37752960;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE Clock Registers */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+
+/** Group: EFUSE Configure Registers */
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
+         *  Configures which block to use for ECDSA key output.
+         */
+        uint32_t cfg_ecdsa_blk:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+
+/** Group: EFUSE Status Registers */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
+         *  Indicates which block is used for ECDSA key output.
+         */
+        uint32_t cur_ecdsa_blk:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: EFUSE Command Registers */
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+/** Group: EFUSE Configure Registers */
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 22;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 200;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
+/** Type of apb2otp_wr_dis register
+ *  eFuse apb2otp block0 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t apb2otp_block0_wr_dis:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_wr_dis_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
+/** Type of apb2otp_blk0_backup1_w1 register
+ *  eFuse apb2otp block0 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t apb2otp_block0_backup1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
+/** Type of apb2otp_blk0_backup1_w2 register
+ *  eFuse apb2otp block0 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t apb2otp_block0_backup1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
+/** Type of apb2otp_blk0_backup1_w3 register
+ *  eFuse apb2otp block0 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t apb2otp_block0_backup1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
+/** Type of apb2otp_blk0_backup1_w4 register
+ *  eFuse apb2otp block0 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t apb2otp_block0_backup1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
+/** Type of apb2otp_blk0_backup1_w5 register
+ *  eFuse apb2otp block0 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t apb2otp_block0_backup1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
+/** Type of apb2otp_blk0_backup2_w1 register
+ *  eFuse apb2otp block0 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t apb2otp_block0_backup2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
+/** Type of apb2otp_blk0_backup2_w2 register
+ *  eFuse apb2otp block0 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t apb2otp_block0_backup2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
+/** Type of apb2otp_blk0_backup2_w3 register
+ *  eFuse apb2otp block0 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t apb2otp_block0_backup2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
+/** Type of apb2otp_blk0_backup2_w4 register
+ *  eFuse apb2otp block0 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t apb2otp_block0_backup2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
+/** Type of apb2otp_blk0_backup2_w5 register
+ *  eFuse apb2otp block0 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t apb2otp_block0_backup2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
+/** Type of apb2otp_blk0_backup3_w1 register
+ *  eFuse apb2otp block0 data register12.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t apb2otp_block0_backup3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
+/** Type of apb2otp_blk0_backup3_w2 register
+ *  eFuse apb2otp block0 data register13.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t apb2otp_block0_backup3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
+/** Type of apb2otp_blk0_backup3_w3 register
+ *  eFuse apb2otp block0 data register14.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t apb2otp_block0_backup3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
+/** Type of apb2otp_blk0_backup3_w4 register
+ *  eFuse apb2otp block0 data register15.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t apb2otp_block0_backup3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
+/** Type of apb2otp_blk0_backup3_w5 register
+ *  eFuse apb2otp block0 data register16.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t apb2otp_block0_backup3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
+/** Type of apb2otp_blk0_backup4_w1 register
+ *  eFuse apb2otp block0 data register17.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t apb2otp_block0_backup4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
+/** Type of apb2otp_blk0_backup4_w2 register
+ *  eFuse apb2otp block0 data register18.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t apb2otp_block0_backup4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
+/** Type of apb2otp_blk0_backup4_w3 register
+ *  eFuse apb2otp block0 data register19.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t apb2otp_block0_backup4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
+/** Type of apb2otp_blk0_backup4_w4 register
+ *  eFuse apb2otp block0 data register20.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t apb2otp_block0_backup4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
+/** Type of apb2otp_blk0_backup4_w5 register
+ *  eFuse apb2otp block0 data register21.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t apb2otp_block0_backup4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word1 Data */
+/** Type of apb2otp_blk1_w1 register
+ *  eFuse apb2otp block1 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t apb2otp_block1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word2 Data */
+/** Type of apb2otp_blk1_w2 register
+ *  eFuse apb2otp block1 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t apb2otp_block1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word3 Data */
+/** Type of apb2otp_blk1_w3 register
+ *  eFuse apb2otp block1 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t apb2otp_block1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word4 Data */
+/** Type of apb2otp_blk1_w4 register
+ *  eFuse apb2otp block1 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t apb2otp_block1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word5 Data */
+/** Type of apb2otp_blk1_w5 register
+ *  eFuse apb2otp block1 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t apb2otp_block1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word6 Data */
+/** Type of apb2otp_blk1_w6 register
+ *  eFuse apb2otp block1 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t apb2otp_block1_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word7 Data */
+/** Type of apb2otp_blk1_w7 register
+ *  eFuse apb2otp block1 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t apb2otp_block1_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word8 Data */
+/** Type of apb2otp_blk1_w8 register
+ *  eFuse apb2otp block1 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t apb2otp_block1_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word9 Data */
+/** Type of apb2otp_blk1_w9 register
+ *  eFuse apb2otp block1 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t apb2otp_block1_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word1 Data */
+/** Type of apb2otp_blk2_w1 register
+ *  eFuse apb2otp block2 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t apb2otp_block2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word2 Data */
+/** Type of apb2otp_blk2_w2 register
+ *  eFuse apb2otp block2 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t apb2otp_block2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word3 Data */
+/** Type of apb2otp_blk2_w3 register
+ *  eFuse apb2otp block2 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t apb2otp_block2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word4 Data */
+/** Type of apb2otp_blk2_w4 register
+ *  eFuse apb2otp block2 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t apb2otp_block2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word5 Data */
+/** Type of apb2otp_blk2_w5 register
+ *  eFuse apb2otp block2 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t apb2otp_block2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word6 Data */
+/** Type of apb2otp_blk2_w6 register
+ *  eFuse apb2otp block2 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t apb2otp_block2_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word7 Data */
+/** Type of apb2otp_blk2_w7 register
+ *  eFuse apb2otp block2 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t apb2otp_block2_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word8 Data */
+/** Type of apb2otp_blk2_w8 register
+ *  eFuse apb2otp block2 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t apb2otp_block2_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word9 Data */
+/** Type of apb2otp_blk2_w9 register
+ *  eFuse apb2otp block2 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t apb2otp_block2_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word10 Data */
+/** Type of apb2otp_blk2_w10 register
+ *  eFuse apb2otp block2 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t apb2otp_block2_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk2_w11 register
+ *  eFuse apb2otp block2 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t apb2otp_block2_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w11_reg_t;
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk10_w11 register
+ *  eFuse apb2otp block10 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t apb2otp_block10_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word1 Data */
+/** Type of apb2otp_blk3_w1 register
+ *  eFuse apb2otp block3 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t apb2otp_block3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word2 Data */
+/** Type of apb2otp_blk3_w2 register
+ *  eFuse apb2otp block3 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t apb2otp_block3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word3 Data */
+/** Type of apb2otp_blk3_w3 register
+ *  eFuse apb2otp block3 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t apb2otp_block3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word4 Data */
+/** Type of apb2otp_blk3_w4 register
+ *  eFuse apb2otp block3 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t apb2otp_block3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word5 Data */
+/** Type of apb2otp_blk3_w5 register
+ *  eFuse apb2otp block3 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t apb2otp_block3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word6 Data */
+/** Type of apb2otp_blk3_w6 register
+ *  eFuse apb2otp block3 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t apb2otp_block3_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word7 Data */
+/** Type of apb2otp_blk3_w7 register
+ *  eFuse apb2otp block3 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t apb2otp_block3_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word8 Data */
+/** Type of apb2otp_blk3_w8 register
+ *  eFuse apb2otp block3 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t apb2otp_block3_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word9 Data */
+/** Type of apb2otp_blk3_w9 register
+ *  eFuse apb2otp block3 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t apb2otp_block3_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word10 Data */
+/** Type of apb2otp_blk3_w10 register
+ *  eFuse apb2otp block3 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t apb2otp_block3_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word11 Data */
+/** Type of apb2otp_blk3_w11 register
+ *  eFuse apb2otp block3 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t apb2otp_block3_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word1 Data */
+/** Type of apb2otp_blk4_w1 register
+ *  eFuse apb2otp BLOCK7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t apb2otp_block4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word2 Data */
+/** Type of apb2otp_blk4_w2 register
+ *  eFuse apb2otp block4 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t apb2otp_block4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word3 Data */
+/** Type of apb2otp_blk4_w3 register
+ *  eFuse apb2otp block4 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t apb2otp_block4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word4 Data */
+/** Type of apb2otp_blk4_w4 register
+ *  eFuse apb2otp block4 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t apb2otp_block4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word5 Data */
+/** Type of apb2otp_blk4_w5 register
+ *  eFuse apb2otp block4 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t apb2otp_block4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word6 Data */
+/** Type of apb2otp_blk4_w6 register
+ *  eFuse apb2otp block4 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t apb2otp_block4_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word7 Data */
+/** Type of apb2otp_blk4_w7 register
+ *  eFuse apb2otp block4 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t apb2otp_block4_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word8 Data */
+/** Type of apb2otp_blk4_w8 register
+ *  eFuse apb2otp block4 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t apb2otp_block4_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word9 Data */
+/** Type of apb2otp_blk4_w9 register
+ *  eFuse apb2otp block4 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t apb2otp_block4_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word10 Data */
+/** Type of apb2otp_blk4_w10 register
+ *  eFuse apb2otp block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t apb2otp_block4_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word11 Data */
+/** Type of apb2otp_blk4_w11 register
+ *  eFuse apb2otp block4 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t apb2otp_block4_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word1 Data */
+/** Type of apb2otp_blk5_w1 register
+ *  eFuse apb2otp block5 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t apb2otp_block5_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word2 Data */
+/** Type of apb2otp_blk5_w2 register
+ *  eFuse apb2otp block5 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t apb2otp_block5_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word3 Data */
+/** Type of apb2otp_blk5_w3 register
+ *  eFuse apb2otp block5 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t apb2otp_block5_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word4 Data */
+/** Type of apb2otp_blk5_w4 register
+ *  eFuse apb2otp block5 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t apb2otp_block5_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word5 Data */
+/** Type of apb2otp_blk5_w5 register
+ *  eFuse apb2otp block5 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t apb2otp_block5_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word6 Data */
+/** Type of apb2otp_blk5_w6 register
+ *  eFuse apb2otp block5 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t apb2otp_block5_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word7 Data */
+/** Type of apb2otp_blk5_w7 register
+ *  eFuse apb2otp block5 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t apb2otp_block5_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word8 Data */
+/** Type of apb2otp_blk5_w8 register
+ *  eFuse apb2otp block5 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t apb2otp_block5_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word9 Data */
+/** Type of apb2otp_blk5_w9 register
+ *  eFuse apb2otp block5 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t apb2otp_block5_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word10 Data */
+/** Type of apb2otp_blk5_w10 register
+ *  eFuse apb2otp block5 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t apb2otp_block5_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word11 Data */
+/** Type of apb2otp_blk5_w11 register
+ *  eFuse apb2otp block5 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t apb2otp_block5_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word1 Data */
+/** Type of apb2otp_blk6_w1 register
+ *  eFuse apb2otp block6 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t apb2otp_block6_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word2 Data */
+/** Type of apb2otp_blk6_w2 register
+ *  eFuse apb2otp block6 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t apb2otp_block6_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word3 Data */
+/** Type of apb2otp_blk6_w3 register
+ *  eFuse apb2otp block6 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t apb2otp_block6_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word4 Data */
+/** Type of apb2otp_blk6_w4 register
+ *  eFuse apb2otp block6 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t apb2otp_block6_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word5 Data */
+/** Type of apb2otp_blk6_w5 register
+ *  eFuse apb2otp block6 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t apb2otp_block6_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word6 Data */
+/** Type of apb2otp_blk6_w6 register
+ *  eFuse apb2otp block6 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t apb2otp_block6_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word7 Data */
+/** Type of apb2otp_blk6_w7 register
+ *  eFuse apb2otp block6 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t apb2otp_block6_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word8 Data */
+/** Type of apb2otp_blk6_w8 register
+ *  eFuse apb2otp block6 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t apb2otp_block6_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word9 Data */
+/** Type of apb2otp_blk6_w9 register
+ *  eFuse apb2otp block6 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t apb2otp_block6_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word10 Data */
+/** Type of apb2otp_blk6_w10 register
+ *  eFuse apb2otp block6 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t apb2otp_block6_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word11 Data */
+/** Type of apb2otp_blk6_w11 register
+ *  eFuse apb2otp block6 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t apb2otp_block6_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word1 Data */
+/** Type of apb2otp_blk7_w1 register
+ *  eFuse apb2otp block7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t apb2otp_block7_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word2 Data */
+/** Type of apb2otp_blk7_w2 register
+ *  eFuse apb2otp block7 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t apb2otp_block7_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word3 Data */
+/** Type of apb2otp_blk7_w3 register
+ *  eFuse apb2otp block7 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t apb2otp_block7_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word4 Data */
+/** Type of apb2otp_blk7_w4 register
+ *  eFuse apb2otp block7 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t apb2otp_block7_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word5 Data */
+/** Type of apb2otp_blk7_w5 register
+ *  eFuse apb2otp block7 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t apb2otp_block7_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word6 Data */
+/** Type of apb2otp_blk7_w6 register
+ *  eFuse apb2otp block7 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t apb2otp_block7_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word7 Data */
+/** Type of apb2otp_blk7_w7 register
+ *  eFuse apb2otp block7 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t apb2otp_block7_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word8 Data */
+/** Type of apb2otp_blk7_w8 register
+ *  eFuse apb2otp block7 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t apb2otp_block7_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word9 Data */
+/** Type of apb2otp_blk7_w9 register
+ *  eFuse apb2otp block7 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t apb2otp_block7_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word10 Data */
+/** Type of apb2otp_blk7_w10 register
+ *  eFuse apb2otp block7 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t apb2otp_block7_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word11 Data */
+/** Type of apb2otp_blk7_w11 register
+ *  eFuse apb2otp block7 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t apb2otp_block7_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word1 Data */
+/** Type of apb2otp_blk8_w1 register
+ *  eFuse apb2otp block8 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t apb2otp_block8_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word2 Data */
+/** Type of apb2otp_blk8_w2 register
+ *  eFuse apb2otp block8 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t apb2otp_block8_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word3 Data */
+/** Type of apb2otp_blk8_w3 register
+ *  eFuse apb2otp block8 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t apb2otp_block8_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word4 Data */
+/** Type of apb2otp_blk8_w4 register
+ *  eFuse apb2otp block8 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t apb2otp_block8_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word5 Data */
+/** Type of apb2otp_blk8_w5 register
+ *  eFuse apb2otp block8 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t apb2otp_block8_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word6 Data */
+/** Type of apb2otp_blk8_w6 register
+ *  eFuse apb2otp block8 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t apb2otp_block8_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word7 Data */
+/** Type of apb2otp_blk8_w7 register
+ *  eFuse apb2otp block8 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t apb2otp_block8_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word8 Data */
+/** Type of apb2otp_blk8_w8 register
+ *  eFuse apb2otp block8 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t apb2otp_block8_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word9 Data */
+/** Type of apb2otp_blk8_w9 register
+ *  eFuse apb2otp block8 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t apb2otp_block8_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word10 Data */
+/** Type of apb2otp_blk8_w10 register
+ *  eFuse apb2otp block8 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t apb2otp_block8_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word11 Data */
+/** Type of apb2otp_blk8_w11 register
+ *  eFuse apb2otp block8 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t apb2otp_block8_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word1 Data */
+/** Type of apb2otp_blk9_w1 register
+ *  eFuse apb2otp block9 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t apb2otp_block9_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word2 Data */
+/** Type of apb2otp_blk9_w2 register
+ *  eFuse apb2otp block9 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t apb2otp_block9_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word3 Data */
+/** Type of apb2otp_blk9_w3 register
+ *  eFuse apb2otp block9 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t apb2otp_block9_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word4 Data */
+/** Type of apb2otp_blk9_w4 register
+ *  eFuse apb2otp block9 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t apb2otp_block9_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word5 Data */
+/** Type of apb2otp_blk9_w5 register
+ *  eFuse apb2otp block9 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t apb2otp_block9_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word6 Data */
+/** Type of apb2otp_blk9_w6 register
+ *  eFuse apb2otp block9 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t apb2otp_block9_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word7 Data */
+/** Type of apb2otp_blk9_w7 register
+ *  eFuse apb2otp block9 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t apb2otp_block9_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word8 Data */
+/** Type of apb2otp_blk9_w8 register
+ *  eFuse apb2otp block9 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t apb2otp_block9_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word9 Data */
+/** Type of apb2otp_blk9_w9 register
+ *  eFuse apb2otp block9 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t apb2otp_block9_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word10 Data */
+/** Type of apb2otp_blk9_w10 register
+ *  eFuse apb2otp block9 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t apb2otp_block9_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word11 Data */
+/** Type of apb2otp_blk9_w11 register
+ *  eFuse apb2otp block9 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t apb2otp_block9_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word1 Data */
+/** Type of apb2otp_blk10_w1 register
+ *  eFuse apb2otp block10 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t apb2otp_block10_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word2 Data */
+/** Type of apb2otp_blk10_w2 register
+ *  eFuse apb2otp block10 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t apb2otp_block10_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word3 Data */
+/** Type of apb2otp_blk10_w3 register
+ *  eFuse apb2otp block10 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t apb2otp_block10_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word4 Data */
+/** Type of apb2otp_blk10_w4 register
+ *  eFuse apb2otp block10 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t apb2otp_block10_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word5 Data */
+/** Type of apb2otp_blk10_w5 register
+ *  eFuse apb2otp block10 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t apb2otp_block10_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word6 Data */
+/** Type of apb2otp_blk10_w6 register
+ *  eFuse apb2otp block10 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t apb2otp_block10_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word7 Data */
+/** Type of apb2otp_blk10_w7 register
+ *  eFuse apb2otp block10 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t apb2otp_block10_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word8 Data */
+/** Type of apb2otp_blk10_w8 register
+ *  eFuse apb2otp block10 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t apb2otp_block10_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word9 Data */
+/** Type of apb2otp_blk10_w9 register
+ *  eFuse apb2otp block10 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t apb2otp_block10_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word10 Data */
+/** Type of apb2otp_blk10_w10 register
+ *  eFuse apb2otp block10 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t apb2otp_block10_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Function Enable Signal */
+/** Type of apb2otp_en register
+ *  eFuse apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Apb2otp mode enable signal.
+         */
+        uint32_t apb2otp_apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_apb2otp_en_reg_t;
+
+
+typedef struct {
+    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
+    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
+    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
+    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
+    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
+    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
+    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
+    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
+    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
+    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
+    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
+    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
+    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
+    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
+    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
+    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
+    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
+    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
+    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
+    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
+    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
+    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
+    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
+    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
+    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
+    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
+    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
+    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
+    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
+    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
+    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
+    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
+    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
+    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
+    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
+    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
+    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
+    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
+    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
+    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
+    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
+    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
+    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
+    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
+    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
+    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
+    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
+    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
+    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
+    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
+    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
+    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
+    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
+    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
+    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
+    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
+    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
+    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
+    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
+    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
+    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
+    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
+    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
+    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
+    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
+    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
+    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
+    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
+    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
+    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
+    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
+    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
+    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
+    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
+    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
+    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
+    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
+    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
+    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
+    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
+    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
+    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
+    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
+    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
+    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
+    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
+    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
+    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
+    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
+    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
+    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
+    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
+    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
+    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
+    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
+    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
+    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
+    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
+    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
+    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
+    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
+    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
+    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
+    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
+    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
+    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
+    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
+    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
+    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
+    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
+    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
+    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
+    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
+    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
+    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
+    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
+    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
+    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
+    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
+    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
+    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
+    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
+    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
+    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
+    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
+    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
+    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
+    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
+    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
+    uint32_t reserved_704;
+    volatile efuse_apb2otp_en_reg_t apb2otp_en;
+} otp_debug_dev_t;
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
+    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
+    volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2;
+    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
+    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
+    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
+    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
+    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
+    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
+    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
+    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
+    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_19c[11];
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    uint32_t reserved_1fc[193];
+    volatile otp_debug_dev_t otp_debug;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+extern otp_debug_dev_t OTP_DEBUG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/include/soc/gpio_reg.h b/components/soc/esp32c5/register/soc/gpio_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/gpio_reg.h
rename to components/soc/esp32c5/register/soc/gpio_reg.h
diff --git a/components/soc/esp32c5/include/soc/gpio_struct.h b/components/soc/esp32c5/register/soc/gpio_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/gpio_struct.h
rename to components/soc/esp32c5/register/soc/gpio_struct.h
diff --git a/components/soc/esp32c5/include/soc/hmac_reg.h b/components/soc/esp32c5/register/soc/hmac_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/hmac_reg.h
rename to components/soc/esp32c5/register/soc/hmac_reg.h
diff --git a/components/soc/esp32c5/include/soc/hmac_struct.h b/components/soc/esp32c5/register/soc/hmac_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/hmac_struct.h
rename to components/soc/esp32c5/register/soc/hmac_struct.h
diff --git a/components/soc/esp32c5/include/soc/hp_apm_reg.h b/components/soc/esp32c5/register/soc/hp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/hp_apm_reg.h
rename to components/soc/esp32c5/register/soc/hp_apm_reg.h
diff --git a/components/soc/esp32c5/include/soc/hp_apm_struct.h b/components/soc/esp32c5/register/soc/hp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/hp_apm_struct.h
rename to components/soc/esp32c5/register/soc/hp_apm_struct.h
diff --git a/components/soc/esp32c5/include/soc/hp_system_reg.h b/components/soc/esp32c5/register/soc/hp_system_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/hp_system_reg.h
rename to components/soc/esp32c5/register/soc/hp_system_reg.h
diff --git a/components/soc/esp32c5/include/soc/hp_system_struct.h b/components/soc/esp32c5/register/soc/hp_system_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/hp_system_struct.h
rename to components/soc/esp32c5/register/soc/hp_system_struct.h
diff --git a/components/soc/esp32c5/include/soc/huk_reg.h b/components/soc/esp32c5/register/soc/huk_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/huk_reg.h
rename to components/soc/esp32c5/register/soc/huk_reg.h
diff --git a/components/soc/esp32c5/include/soc/huk_struct.h b/components/soc/esp32c5/register/soc/huk_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/huk_struct.h
rename to components/soc/esp32c5/register/soc/huk_struct.h
diff --git a/components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/i2c_ana_mst_reg.h
rename to components/soc/esp32c5/register/soc/i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c5/include/soc/i2c_reg.h b/components/soc/esp32c5/register/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/i2c_reg.h
rename to components/soc/esp32c5/register/soc/i2c_reg.h
diff --git a/components/soc/esp32c5/include/soc/i2c_struct.h b/components/soc/esp32c5/register/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/i2c_struct.h
rename to components/soc/esp32c5/register/soc/i2c_struct.h
diff --git a/components/soc/esp32c5/include/soc/i2s_reg.h b/components/soc/esp32c5/register/soc/i2s_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/i2s_reg.h
rename to components/soc/esp32c5/register/soc/i2s_reg.h
diff --git a/components/soc/esp32c5/include/soc/i2s_struct.h b/components/soc/esp32c5/register/soc/i2s_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/i2s_struct.h
rename to components/soc/esp32c5/register/soc/i2s_struct.h
diff --git a/components/soc/esp32c5/include/soc/ieee802154_reg.h b/components/soc/esp32c5/register/soc/ieee802154_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ieee802154_reg.h
rename to components/soc/esp32c5/register/soc/ieee802154_reg.h
diff --git a/components/soc/esp32c5/include/soc/ieee802154_struct.h b/components/soc/esp32c5/register/soc/ieee802154_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ieee802154_struct.h
rename to components/soc/esp32c5/register/soc/ieee802154_struct.h
diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c5/register/soc/interrupt_matrix_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/interrupt_matrix_reg.h
rename to components/soc/esp32c5/register/soc/interrupt_matrix_reg.h
diff --git a/components/soc/esp32c5/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c5/register/soc/interrupt_matrix_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/interrupt_matrix_struct.h
rename to components/soc/esp32c5/register/soc/interrupt_matrix_struct.h
diff --git a/components/soc/esp32c5/include/soc/intpri_reg.h b/components/soc/esp32c5/register/soc/intpri_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/intpri_reg.h
rename to components/soc/esp32c5/register/soc/intpri_reg.h
diff --git a/components/soc/esp32c5/include/soc/intpri_struct.h b/components/soc/esp32c5/register/soc/intpri_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/intpri_struct.h
rename to components/soc/esp32c5/register/soc/intpri_struct.h
diff --git a/components/soc/esp32c5/include/soc/io_mux_reg.h b/components/soc/esp32c5/register/soc/io_mux_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/io_mux_reg.h
rename to components/soc/esp32c5/register/soc/io_mux_reg.h
diff --git a/components/soc/esp32c5/include/soc/io_mux_struct.h b/components/soc/esp32c5/register/soc/io_mux_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/io_mux_struct.h
rename to components/soc/esp32c5/register/soc/io_mux_struct.h
diff --git a/components/soc/esp32c5/include/soc/keymng_reg.h b/components/soc/esp32c5/register/soc/keymng_reg.h
similarity index 90%
rename from components/soc/esp32c5/include/soc/keymng_reg.h
rename to components/soc/esp32c5/register/soc/keymng_reg.h
index 48324b814cb..66ab3903733 100644
--- a/components/soc/esp32c5/include/soc/keymng_reg.h
+++ b/components/soc/esp32c5/register/soc/keymng_reg.h
@@ -147,6 +147,22 @@ extern "C" {
 #define KEYMNG_USE_EFUSE_KEY_M  (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
 #define KEYMNG_USE_EFUSE_KEY_V  0x0000001FU
 #define KEYMNG_USE_EFUSE_KEY_S  0
+
+/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa.*/
+#define KEYMNG_USE_EFUSE_KEY_ECDSA    (BIT(0))
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_M  ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S))
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_ECDSA_S  0
+
+/* KEYMNG_USE_EFUSE_KEY_FLASH : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set this bit to choose efuse key instead of key manager deployed key for flash.*/
+#define KEYMNG_USE_EFUSE_KEY_FLASH    (BIT(1))
+#define KEYMNG_USE_EFUSE_KEY_FLASH_M  ((KEYMNG_USE_EFUSE_KEY_FLASH_V)<<(KEYMNG_USE_EFUSE_KEY_FLASH_S))
+#define KEYMNG_USE_EFUSE_KEY_FLASH_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_FLASH_S  1
+
+
 /** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
  *  The core clock cycle number to sample one rng input data. Please set it bigger than
  *  the clock cycle ratio: T_rng/T_km
@@ -191,6 +207,23 @@ extern "C" {
 #define KEYMNG_USE_EFUSE_KEY_LOCK_M  (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
 #define KEYMNG_USE_EFUSE_KEY_LOCK_V  0x0000001FU
 #define KEYMNG_USE_EFUSE_KEY_LOCK_S  0
+
+/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W1 ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Write 1 to lock reg_use_efuse_key for esdsa*/
+
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA    (BIT(0))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M  ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S  0
+
+/* KEYMNG_USE_EFUSE_KEY_LOCK_FLASH : R/W1 ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Write 1 to lock reg_use_efuse_key for FLASH*/
+
+#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH    (BIT(1))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_M  ((KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S))
+#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V  0x1
+#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S  1
+
 /** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
  *  Write 1 to lock reg_rnd_switch_cycle.
  */
diff --git a/components/soc/esp32c5/include/soc/keymng_struct.h b/components/soc/esp32c5/register/soc/keymng_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/keymng_struct.h
rename to components/soc/esp32c5/register/soc/keymng_struct.h
diff --git a/components/soc/esp32c5/include/soc/ledc_reg.h b/components/soc/esp32c5/register/soc/ledc_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ledc_reg.h
rename to components/soc/esp32c5/register/soc/ledc_reg.h
diff --git a/components/soc/esp32c5/include/soc/ledc_struct.h b/components/soc/esp32c5/register/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/ledc_struct.h
rename to components/soc/esp32c5/register/soc/ledc_struct.h
diff --git a/components/soc/esp32c5/register/soc/lp_analog_peri_reg.h b/components/soc/esp32c5/register/soc/lp_analog_peri_reg.h
new file mode 100644
index 00000000000..13fd8e80e16
--- /dev/null
+++ b/components/soc/esp32c5/register/soc/lp_analog_peri_reg.h
@@ -0,0 +1,254 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_ANA_BOD_MODE0_CNTL_REG register
+ *  Configure brownout mode0
+ */
+#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
+/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
+ *  enable suspend spi when brownout interrupt or not
+ *  1:enable
+ *  0:disable
+ */
+#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA    (BIT(6))
+#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M  (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
+#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S  6
+/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
+ *  enable power down RF when brownout interrupt or not
+ *  1:enable
+ *  0:disable
+ */
+#define LP_ANA_BOD_MODE0_PD_RF_ENA    (BIT(7))
+#define LP_ANA_BOD_MODE0_PD_RF_ENA_M  (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
+#define LP_ANA_BOD_MODE0_PD_RF_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_PD_RF_ENA_S  7
+/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
+ *  set the undervoltage hold time for triggering brownout interrupt
+ */
+#define LP_ANA_BOD_MODE0_INTR_WAIT    0x000003FFU
+#define LP_ANA_BOD_MODE0_INTR_WAIT_M  (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
+#define LP_ANA_BOD_MODE0_INTR_WAIT_V  0x000003FFU
+#define LP_ANA_BOD_MODE0_INTR_WAIT_S  8
+/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
+ *  set the undervoltage hold time for triggering brownout reset
+ */
+#define LP_ANA_BOD_MODE0_RESET_WAIT    0x000003FFU
+#define LP_ANA_BOD_MODE0_RESET_WAIT_M  (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
+#define LP_ANA_BOD_MODE0_RESET_WAIT_V  0x000003FFU
+#define LP_ANA_BOD_MODE0_RESET_WAIT_S  18
+/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
+ *  clear brownout count or not
+ *  1: clear
+ *  0: no operation
+ */
+#define LP_ANA_BOD_MODE0_CNT_CLR    (BIT(28))
+#define LP_ANA_BOD_MODE0_CNT_CLR_M  (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
+#define LP_ANA_BOD_MODE0_CNT_CLR_V  0x00000001U
+#define LP_ANA_BOD_MODE0_CNT_CLR_S  28
+/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
+ *  enable brownout interrupt or not
+ *  1: enable
+ *  0: disable
+ */
+#define LP_ANA_BOD_MODE0_INTR_ENA    (BIT(29))
+#define LP_ANA_BOD_MODE0_INTR_ENA_M  (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
+#define LP_ANA_BOD_MODE0_INTR_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INTR_ENA_S  29
+/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
+ *  select brownout reset level
+ *  1: system reset
+ *  0: chip reset
+ */
+#define LP_ANA_BOD_MODE0_RESET_SEL    (BIT(30))
+#define LP_ANA_BOD_MODE0_RESET_SEL_M  (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
+#define LP_ANA_BOD_MODE0_RESET_SEL_V  0x00000001U
+#define LP_ANA_BOD_MODE0_RESET_SEL_S  30
+/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
+ *  enable brownout reset or not
+ *  1: enable
+ *  0: disable
+ */
+#define LP_ANA_BOD_MODE0_RESET_ENA    (BIT(31))
+#define LP_ANA_BOD_MODE0_RESET_ENA_M  (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
+#define LP_ANA_BOD_MODE0_RESET_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_RESET_ENA_S  31
+
+/** LP_ANA_BOD_MODE1_CNTL_REG register
+ *  Configure brownout mode1
+ */
+#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
+/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
+ *  enable brownout mode1 reset or not
+ *  1: enable
+ *  0: disable
+ */
+#define LP_ANA_BOD_MODE1_RESET_ENA    (BIT(31))
+#define LP_ANA_BOD_MODE1_RESET_ENA_M  (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
+#define LP_ANA_BOD_MODE1_RESET_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE1_RESET_ENA_S  31
+
+/** LP_ANA_CK_GLITCH_CNTL_REG register
+ *  Configure power glitch
+ */
+#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
+/** LP_ANA_PWR_GLITCH_RESET_ENA : R/W; bitpos: [30:27]; default: 0;
+ *  enable powerglitch or not
+ */
+#define LP_ANA_PWR_GLITCH_RESET_ENA    0x0000000FU
+#define LP_ANA_PWR_GLITCH_RESET_ENA_M  (LP_ANA_PWR_GLITCH_RESET_ENA_V << LP_ANA_PWR_GLITCH_RESET_ENA_S)
+#define LP_ANA_PWR_GLITCH_RESET_ENA_V  0x0000000FU
+#define LP_ANA_PWR_GLITCH_RESET_ENA_S  27
+/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define LP_ANA_CK_GLITCH_RESET_ENA    (BIT(31))
+#define LP_ANA_CK_GLITCH_RESET_ENA_M  (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
+#define LP_ANA_CK_GLITCH_RESET_ENA_V  0x00000001U
+#define LP_ANA_CK_GLITCH_RESET_ENA_S  31
+
+/** LP_ANA_FIB_ENABLE_REG register
+ *  configure FIB REG
+ */
+#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
+/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
+ *  configure analog fib by software
+ */
+#define LP_ANA_ANA_FIB_ENA    0xFFFFFFFFU
+#define LP_ANA_ANA_FIB_ENA_M  (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
+#define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
+#define LP_ANA_ANA_FIB_ENA_S  0
+
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA    0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M  (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S)
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V  0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S  2
+
+/** LP_ANA_INT_RAW_REG register
+ *  interrpt raw register
+ */
+#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
+/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  brownout mode0 interrupt raw register
+ */
+#define LP_ANA_BOD_MODE0_INT_RAW    (BIT(31))
+#define LP_ANA_BOD_MODE0_INT_RAW_M  (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
+#define LP_ANA_BOD_MODE0_INT_RAW_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INT_RAW_S  31
+
+/** LP_ANA_INT_ST_REG register
+ *  interrpt status register
+ */
+#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
+/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
+ *  brownout mode0 interrupt status register
+ */
+#define LP_ANA_BOD_MODE0_INT_ST    (BIT(31))
+#define LP_ANA_BOD_MODE0_INT_ST_M  (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
+#define LP_ANA_BOD_MODE0_INT_ST_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INT_ST_S  31
+
+/** LP_ANA_INT_ENA_REG register
+ *  interrpt enable register
+ */
+#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
+/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  brownout mode0 interrupt enable register
+ */
+#define LP_ANA_BOD_MODE0_INT_ENA    (BIT(31))
+#define LP_ANA_BOD_MODE0_INT_ENA_M  (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
+#define LP_ANA_BOD_MODE0_INT_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INT_ENA_S  31
+
+/** LP_ANA_INT_CLR_REG register
+ *  interrpt clear register
+ */
+#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
+/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  brownout mode0 interrupt clear register
+ */
+#define LP_ANA_BOD_MODE0_INT_CLR    (BIT(31))
+#define LP_ANA_BOD_MODE0_INT_CLR_M  (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
+#define LP_ANA_BOD_MODE0_INT_CLR_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INT_CLR_S  31
+
+/** LP_ANA_LP_INT_RAW_REG register
+ *  lp interrupt raw register
+ */
+#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
+/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  brownout mode0 lp interrupt raw register
+ */
+#define LP_ANA_BOD_MODE0_LP_INT_RAW    (BIT(31))
+#define LP_ANA_BOD_MODE0_LP_INT_RAW_M  (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
+#define LP_ANA_BOD_MODE0_LP_INT_RAW_V  0x00000001U
+#define LP_ANA_BOD_MODE0_LP_INT_RAW_S  31
+
+/** LP_ANA_LP_INT_ST_REG register
+ *  lp interrupt status register
+ */
+#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
+/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  brownout mode0 lp interrupt status register
+ */
+#define LP_ANA_BOD_MODE0_LP_INT_ST    (BIT(31))
+#define LP_ANA_BOD_MODE0_LP_INT_ST_M  (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
+#define LP_ANA_BOD_MODE0_LP_INT_ST_V  0x00000001U
+#define LP_ANA_BOD_MODE0_LP_INT_ST_S  31
+
+/** LP_ANA_LP_INT_ENA_REG register
+ *  lp interrupt enable register
+ */
+#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
+/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  brownout mode0 lp interrupt enable register
+ */
+#define LP_ANA_BOD_MODE0_LP_INT_ENA    (BIT(31))
+#define LP_ANA_BOD_MODE0_LP_INT_ENA_M  (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
+#define LP_ANA_BOD_MODE0_LP_INT_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_LP_INT_ENA_S  31
+
+/** LP_ANA_LP_INT_CLR_REG register
+ *  lp interrupt clear register
+ */
+#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
+/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  brownout mode0 lp interrupt clear register
+ */
+#define LP_ANA_BOD_MODE0_LP_INT_CLR    (BIT(31))
+#define LP_ANA_BOD_MODE0_LP_INT_CLR_M  (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
+#define LP_ANA_BOD_MODE0_LP_INT_CLR_V  0x00000001U
+#define LP_ANA_BOD_MODE0_LP_INT_CLR_S  31
+
+/** LP_ANA_DATE_REG register
+ *  version register
+ */
+#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
+/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 36774528;
+ *  version register
+ */
+#define LP_ANA_LP_ANA_DATE    0x7FFFFFFFU
+#define LP_ANA_LP_ANA_DATE_M  (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
+#define LP_ANA_LP_ANA_DATE_V  0x7FFFFFFFU
+#define LP_ANA_LP_ANA_DATE_S  0
+/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define LP_ANA_CLK_EN    (BIT(31))
+#define LP_ANA_CLK_EN_M  (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
+#define LP_ANA_CLK_EN_V  0x00000001U
+#define LP_ANA_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c5/register/soc/lp_analog_peri_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_analog_peri_struct.h
rename to components/soc/esp32c5/register/soc/lp_analog_peri_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_aon_reg.h b/components/soc/esp32c5/register/soc/lp_aon_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_aon_reg.h
rename to components/soc/esp32c5/register/soc/lp_aon_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_aon_struct.h b/components/soc/esp32c5/register/soc/lp_aon_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_aon_struct.h
rename to components/soc/esp32c5/register/soc/lp_aon_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_apm0_reg.h b/components/soc/esp32c5/register/soc/lp_apm0_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_apm0_reg.h
rename to components/soc/esp32c5/register/soc/lp_apm0_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_apm0_struct.h b/components/soc/esp32c5/register/soc/lp_apm0_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_apm0_struct.h
rename to components/soc/esp32c5/register/soc/lp_apm0_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_apm_reg.h b/components/soc/esp32c5/register/soc/lp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_apm_reg.h
rename to components/soc/esp32c5/register/soc/lp_apm_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_apm_struct.h b/components/soc/esp32c5/register/soc/lp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_apm_struct.h
rename to components/soc/esp32c5/register/soc/lp_apm_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_reg.h b/components/soc/esp32c5/register/soc/lp_clkrst_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_clkrst_reg.h
rename to components/soc/esp32c5/register/soc/lp_clkrst_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_clkrst_struct.h b/components/soc/esp32c5/register/soc/lp_clkrst_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_clkrst_struct.h
rename to components/soc/esp32c5/register/soc/lp_clkrst_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_gpio_reg.h b/components/soc/esp32c5/register/soc/lp_gpio_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_gpio_reg.h
rename to components/soc/esp32c5/register/soc/lp_gpio_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_gpio_struct.h b/components/soc/esp32c5/register/soc/lp_gpio_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_gpio_struct.h
rename to components/soc/esp32c5/register/soc/lp_gpio_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c5/register/soc/lp_i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_i2c_ana_mst_reg.h
rename to components/soc/esp32c5/register/soc/lp_i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c5/register/soc/lp_i2c_ana_mst_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_i2c_ana_mst_struct.h
rename to components/soc/esp32c5/register/soc/lp_i2c_ana_mst_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_i2c_reg.h b/components/soc/esp32c5/register/soc/lp_i2c_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_i2c_reg.h
rename to components/soc/esp32c5/register/soc/lp_i2c_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_i2c_struct.h b/components/soc/esp32c5/register/soc/lp_i2c_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_i2c_struct.h
rename to components/soc/esp32c5/register/soc/lp_i2c_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_iomux_reg.h b/components/soc/esp32c5/register/soc/lp_iomux_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_iomux_reg.h
rename to components/soc/esp32c5/register/soc/lp_iomux_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_iomux_struct.h b/components/soc/esp32c5/register/soc/lp_iomux_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_iomux_struct.h
rename to components/soc/esp32c5/register/soc/lp_iomux_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_tee_reg.h b/components/soc/esp32c5/register/soc/lp_tee_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_tee_reg.h
rename to components/soc/esp32c5/register/soc/lp_tee_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_tee_struct.h b/components/soc/esp32c5/register/soc/lp_tee_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_tee_struct.h
rename to components/soc/esp32c5/register/soc/lp_tee_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_timer_reg.h b/components/soc/esp32c5/register/soc/lp_timer_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_timer_reg.h
rename to components/soc/esp32c5/register/soc/lp_timer_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_timer_struct.h b/components/soc/esp32c5/register/soc/lp_timer_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_timer_struct.h
rename to components/soc/esp32c5/register/soc/lp_timer_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_uart_reg.h b/components/soc/esp32c5/register/soc/lp_uart_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_uart_reg.h
rename to components/soc/esp32c5/register/soc/lp_uart_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_uart_struct.h b/components/soc/esp32c5/register/soc/lp_uart_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_uart_struct.h
rename to components/soc/esp32c5/register/soc/lp_uart_struct.h
diff --git a/components/soc/esp32c5/include/soc/lp_wdt_reg.h b/components/soc/esp32c5/register/soc/lp_wdt_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_wdt_reg.h
rename to components/soc/esp32c5/register/soc/lp_wdt_reg.h
diff --git a/components/soc/esp32c5/include/soc/lp_wdt_struct.h b/components/soc/esp32c5/register/soc/lp_wdt_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lp_wdt_struct.h
rename to components/soc/esp32c5/register/soc/lp_wdt_struct.h
diff --git a/components/soc/esp32c5/include/soc/lpperi_reg.h b/components/soc/esp32c5/register/soc/lpperi_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lpperi_reg.h
rename to components/soc/esp32c5/register/soc/lpperi_reg.h
diff --git a/components/soc/esp32c5/include/soc/lpperi_struct.h b/components/soc/esp32c5/register/soc/lpperi_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/lpperi_struct.h
rename to components/soc/esp32c5/register/soc/lpperi_struct.h
diff --git a/components/soc/esp32c5/include/soc/mcpwm_reg.h b/components/soc/esp32c5/register/soc/mcpwm_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/mcpwm_reg.h
rename to components/soc/esp32c5/register/soc/mcpwm_reg.h
diff --git a/components/soc/esp32c5/include/soc/mcpwm_struct.h b/components/soc/esp32c5/register/soc/mcpwm_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/mcpwm_struct.h
rename to components/soc/esp32c5/register/soc/mcpwm_struct.h
diff --git a/components/soc/esp32c5/include/soc/mem_monitor_reg.h b/components/soc/esp32c5/register/soc/mem_monitor_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/mem_monitor_reg.h
rename to components/soc/esp32c5/register/soc/mem_monitor_reg.h
diff --git a/components/soc/esp32c5/include/soc/mem_monitor_struct.h b/components/soc/esp32c5/register/soc/mem_monitor_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/mem_monitor_struct.h
rename to components/soc/esp32c5/register/soc/mem_monitor_struct.h
diff --git a/components/soc/esp32c5/include/soc/parl_io_reg.h b/components/soc/esp32c5/register/soc/parl_io_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/parl_io_reg.h
rename to components/soc/esp32c5/register/soc/parl_io_reg.h
diff --git a/components/soc/esp32c5/include/soc/parl_io_struct.h b/components/soc/esp32c5/register/soc/parl_io_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/parl_io_struct.h
rename to components/soc/esp32c5/register/soc/parl_io_struct.h
diff --git a/components/soc/esp32c5/include/soc/pau_reg.h b/components/soc/esp32c5/register/soc/pau_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pau_reg.h
rename to components/soc/esp32c5/register/soc/pau_reg.h
diff --git a/components/soc/esp32c5/include/soc/pau_struct.h b/components/soc/esp32c5/register/soc/pau_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pau_struct.h
rename to components/soc/esp32c5/register/soc/pau_struct.h
diff --git a/components/soc/esp32c5/include/soc/pcnt_reg.h b/components/soc/esp32c5/register/soc/pcnt_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pcnt_reg.h
rename to components/soc/esp32c5/register/soc/pcnt_reg.h
diff --git a/components/soc/esp32c5/include/soc/pcnt_struct.h b/components/soc/esp32c5/register/soc/pcnt_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pcnt_struct.h
rename to components/soc/esp32c5/register/soc/pcnt_struct.h
diff --git a/components/soc/esp32c5/include/soc/pcr_reg.h b/components/soc/esp32c5/register/soc/pcr_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pcr_reg.h
rename to components/soc/esp32c5/register/soc/pcr_reg.h
diff --git a/components/soc/esp32c5/include/soc/pcr_struct.h b/components/soc/esp32c5/register/soc/pcr_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pcr_struct.h
rename to components/soc/esp32c5/register/soc/pcr_struct.h
diff --git a/components/soc/esp32c5/include/soc/pmu_reg.h b/components/soc/esp32c5/register/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pmu_reg.h
rename to components/soc/esp32c5/register/soc/pmu_reg.h
diff --git a/components/soc/esp32c5/register/soc/pmu_struct.h b/components/soc/esp32c5/register/soc/pmu_struct.h
new file mode 100644
index 00000000000..ad7fc03d016
--- /dev/null
+++ b/components/soc/esp32c5/register/soc/pmu_struct.h
@@ -0,0 +1,763 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "soc/soc.h"
+#include "soc/pmu_reg.h"
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t vdd_spi_pd_en: 1;
+        uint32_t mem_dslp     : 1;
+        uint32_t mem_pd_en    : 4;
+        uint32_t wifi_pd_en   : 1;
+        uint32_t reserved1    : 1;
+        uint32_t cpu_pd_en    : 1;
+        uint32_t aon_pd_en    : 1;
+        uint32_t top_pd_en    : 1;
+    };
+    uint32_t val;
+} pmu_hp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 30;
+        uint32_t code     : 2;
+    };
+    uint32_t val;
+} pmu_hp_icg_modem_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 24;
+        uint32_t uart_wakeup_en : 1;
+        uint32_t lp_pad_hold_all: 1;
+        uint32_t hp_pad_hold_all: 1;
+        uint32_t dig_pad_slp_sel: 1;
+        uint32_t dig_pause_wdt  : 1;
+        uint32_t dig_cpu_stall  : 1;
+        uint32_t reserved1      : 2;
+    };
+    uint32_t val;
+} pmu_hp_sys_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 26;
+        uint32_t i2c_iso_en   : 1;
+        uint32_t i2c_retention: 1;
+        uint32_t xpd_bb_i2c   : 1;
+        uint32_t xpd_bbpll_i2c: 1;
+        uint32_t xpd_bbpll    : 1;
+        uint32_t reserved1    : 1;
+    };
+    uint32_t val;
+} pmu_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_hp_bias_reg_t;
+
+typedef union {
+    struct {    /* HP: Active State */
+        uint32_t reserved0                            : 4;
+        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
+        uint32_t hp_modem2active_backup_modem_clk_code: 2;
+        uint32_t reserved1                            : 2;
+        uint32_t hp_active_retention_mode             : 1;
+        uint32_t hp_sleep2active_retention_en         : 1;
+        uint32_t hp_modem2active_retention_en         : 1;
+        uint32_t reserved2                            : 1;
+        uint32_t hp_sleep2active_backup_clk_sel       : 2;
+        uint32_t hp_modem2active_backup_clk_sel       : 2;
+        uint32_t hp_sleep2active_backup_mode          : 5;
+        uint32_t hp_modem2active_backup_mode          : 5;
+        uint32_t reserved4                            : 1;
+        uint32_t hp_sleep2active_backup_en            : 1;
+        uint32_t hp_modem2active_backup_en            : 1;
+        uint32_t reserved5                            : 1;
+    };
+    struct {    /* HP: Modem State */
+        uint32_t reserved6                            : 4;
+        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
+        uint32_t reserved7                            : 4;
+        uint32_t hp_modem_retention_mode              : 1;
+        uint32_t hp_sleep2modem_retention_en          : 1;
+        uint32_t reserved8                            : 2;
+        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
+        uint32_t reserved9                            : 4;
+        uint32_t hp_sleep2modem_backup_mode           : 5;
+        uint32_t reserved10                           : 4;
+        uint32_t hp_sleep2modem_backup_en             : 1;
+        uint32_t reserved11                           : 2;
+    };
+    struct {    /* HP: Sleep State */
+        uint32_t reserved12                           : 6;
+        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
+        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
+        uint32_t hp_sleep_retention_mode              : 1;
+        uint32_t reserved13                           : 1;
+        uint32_t hp_modem2sleep_retention_en          : 1;
+        uint32_t hp_active2sleep_retention_en         : 1;
+        uint32_t reserved14                           : 2;
+        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
+        uint32_t hp_active2sleep_backup_clk_sel       : 2;
+        uint32_t hp_modem2sleep_backup_mode           : 5;
+        uint32_t hp_active2sleep_backup_mode          : 5;
+        uint32_t hp_modem2sleep_backup_en             : 1;
+        uint32_t hp_active2sleep_backup_en            : 1;
+    };
+    uint32_t val;
+} pmu_hp_backup_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0       : 26;
+        uint32_t dig_sysclk_nodiv: 1;
+        uint32_t icg_sysclk_en   : 1;
+        uint32_t sysclk_slp_sel  : 1;
+        uint32_t icg_slp_sel     : 1;
+        uint32_t dig_sysclk_sel  : 2;
+    };
+    uint32_t val;
+} pmu_hp_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 3;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t slp_connect_en : 1;
+        uint32_t slp_mem_xpd    : 1;
+        uint32_t slp_logic_xpd  : 1;
+        uint32_t xpd            : 1;
+        uint32_t slp_mem_dbias  : 4;
+        uint32_t slp_logic_dbias: 4;
+        uint32_t dbias          : 5;
+    };
+    uint32_t val;
+} pmu_hp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 8;
+        uint32_t drv_b    : 24;
+    };
+    uint32_t val;
+} pmu_hp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_hp_xtal_reg_t;
+
+typedef struct pmu_hp_hw_regmap_t{
+    pmu_hp_dig_power_reg_t     dig_power;
+    uint32_t                   icg_func;
+    uint32_t                   icg_apb;
+    pmu_hp_icg_modem_reg_t     icg_modem;
+    pmu_hp_sys_cntl_reg_t      syscntl;
+    pmu_hp_clk_power_reg_t     clk_power;
+    pmu_hp_bias_reg_t          bias;
+    pmu_hp_backup_reg_t        backup;
+    uint32_t                   backup_clk;
+    pmu_hp_sysclk_reg_t        sysclk;
+    pmu_hp_regulator0_reg_t    regulator0;
+    pmu_hp_regulator1_reg_t    regulator1;
+    pmu_hp_xtal_reg_t          xtal;
+} pmu_hp_hw_regmap_t;
+
+/** */
+typedef union {
+    struct {
+        uint32_t reserved0: 21;
+        uint32_t slp_xpd  : 1;
+        uint32_t xpd	  : 1;
+        uint32_t slp_dbias: 4;
+        uint32_t dbias    : 5;
+    };
+    uint32_t val;
+} pmu_lp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 28;
+        uint32_t drv_b    : 4;
+    };
+    uint32_t val;
+} pmu_lp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_lp_xtal_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 30;
+        uint32_t mem_dslp  : 1;
+        uint32_t peri_pd_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0  : 28;
+        uint32_t xpd_xtal32k: 1;
+        uint32_t xpd_rc32k  : 1;
+        uint32_t xpd_fosc   : 1;
+        uint32_t pd_osc     : 1;
+    };
+    uint32_t val;
+} pmu_lp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_lp_bias_reg_t;
+
+typedef struct pmu_lp_hw_regmap_t{
+    pmu_lp_regulator0_reg_t    regulator0;
+    pmu_lp_regulator1_reg_t    regulator1;
+    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
+    pmu_lp_dig_power_reg_t     dig_power;
+    pmu_lp_clk_power_reg_t     clk_power;
+    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
+} pmu_lp_hw_regmap_t;
+
+
+typedef union {
+    struct {
+        uint32_t tie_low_global_bbpll_icg : 1;
+        uint32_t tie_low_global_xtal_icg  : 1;
+        uint32_t tie_low_i2c_retention    : 1;
+        uint32_t tie_low_xpd_bb_i2c       : 1;
+        uint32_t tie_low_xpd_bbpll_i2c    : 1;
+        uint32_t tie_low_xpd_bbpll        : 1;
+        uint32_t tie_low_xpd_xtal         : 1;
+        uint32_t reserved0                : 18;
+        uint32_t tie_high_global_bbpll_icg: 1;
+        uint32_t tie_high_global_xtal_icg : 1;
+        uint32_t tie_high_i2c_retention   : 1;
+        uint32_t tie_high_xpd_bb_i2c      : 1;
+        uint32_t tie_high_xpd_bbpll_i2c   : 1;
+        uint32_t tie_high_xpd_bbpll       : 1;
+        uint32_t tie_high_xpd_xtal        : 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 28;
+        uint32_t update_dig_icg_switch: 1;
+        uint32_t tie_low_icg_slp_sel  : 1;
+        uint32_t tie_high_icg_slp_sel : 1;
+        uint32_t update_dig_sysclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_sleep_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0             : 31;
+        uint32_t update_dig_icg_func_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_func_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 31;
+        uint32_t update_dig_icg_apb_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_apb_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 31;
+        uint32_t update_dig_icg_modem_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_modem_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 30;
+        uint32_t tie_low_lp_rootclk_sel : 1;
+        uint32_t tie_high_lp_rootclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_lp_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0               : 28;
+        uint32_t tie_high_lp_pad_hold_all: 1;
+        uint32_t tie_low_lp_pad_hold_all : 1;
+        uint32_t tie_high_hp_pad_hold_all: 1;
+        uint32_t tie_low_hp_pad_hold_all : 1;
+    };
+    uint32_t val;
+} pmu_imm_pad_hold_all_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 30;
+        uint32_t tie_high_i2c_iso_en: 1;
+        uint32_t tie_low_i2c_iso_en : 1;
+    };
+    uint32_t val;
+} pmu_imm_i2c_isolate_reg_t;
+
+typedef struct pmu_imm_hw_regmap_t{
+    pmu_imm_hp_clk_power_reg_t     clk_power;
+    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
+    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
+    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
+    pmu_imm_modem_icg_reg_t        modem_icg;
+    pmu_imm_lp_icg_reg_t           lp_icg;
+    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
+    pmu_imm_i2c_isolate_reg_t      i2c_iso;
+} pmu_imm_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 9;
+        uint32_t powerdown_timer: 7;
+        uint32_t powerup_timer  : 7;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t lp_iso_wait_timer : 8;
+        uint32_t lp_rst_wait_timer : 8;
+        uint32_t hp_iso_wait_timer : 8;
+        uint32_t hp_rst_wait_timer : 8;
+    };
+    uint32_t val;
+} pmu_power_wait_timer2_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_reset   : 1;
+        uint32_t force_iso     : 1;
+        uint32_t force_pu      : 1;
+        uint32_t force_no_reset: 1;
+        uint32_t force_no_iso  : 1;
+        uint32_t force_pd      : 1;
+        uint32_t mask          : 5;     /* Invalid of lp peripherals */
+        uint32_t reserved0     : 16;    /* Invalid of lp peripherals */
+        uint32_t pd_mask       : 5;     /* Invalid of lp peripherals */
+    };
+    uint32_t val;
+} pmu_power_domain_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_mem_iso   : 4;
+        uint32_t force_hp_mem_pd    : 4;
+        uint32_t reserved0          : 16;
+        uint32_t force_hp_mem_no_iso: 4;
+        uint32_t force_hp_mem_pu    : 4;
+    };
+    uint32_t val;
+} pmu_power_memory_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t mem2_pd_mask: 5;
+        uint32_t mem1_pd_mask: 5;
+        uint32_t mem0_pd_mask: 5;
+        uint32_t reserved0   : 2;
+        uint32_t mem2_mask   : 5;
+        uint32_t mem1_mask   : 5;
+        uint32_t mem0_mask   : 5;
+    };
+    uint32_t val;
+} pmu_power_memory_mask_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_pad_no_iso_all: 1;
+        uint32_t force_hp_pad_iso_all   : 1;
+        uint32_t reserved0              : 30;
+    };
+    uint32_t val;
+} pmu_power_hp_pad_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 18;
+        uint32_t pwr_wait  : 11;
+        uint32_t pwr_sw    : 2;
+        uint32_t pwr_sel_sw: 1;
+    };
+    uint32_t val;
+} pmu_power_vdd_spi_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wait_xtal_stable: 16;
+        uint32_t wait_pll_stable : 16;
+    };
+    uint32_t val;
+} pmu_power_clk_wait_cntl_reg_t;
+
+typedef struct pmu_power_hw_regmap_t{
+    pmu_power_wait_timer0_reg_t    wait_timer0;
+    pmu_power_wait_timer1_reg_t    wait_timer1;
+    pmu_power_wait_timer2_reg_t    wait_timer2;
+    pmu_power_domain_cntl_reg_t    hp_pd[5];
+    pmu_power_domain_cntl_reg_t    lp_peri;
+    pmu_power_memory_cntl_reg_t    mem_cntl;
+    pmu_power_memory_mask_reg_t    mem_mask;
+    pmu_power_hp_pad_reg_t         hp_pad;
+    pmu_power_vdd_spi_cntl_reg_t   vdd_spi;
+    pmu_power_clk_wait_cntl_reg_t  clk_wait;
+} pmu_power_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_ena: 31;
+        uint32_t slp_reject_en   : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t lp_min_slp_val: 8;
+        uint32_t hp_min_slp_val: 8;
+        uint32_t sleep_prt_sel : 2;
+        uint32_t reserved0     : 14;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0           : 31;
+        uint32_t slp_reject_cause_clr: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modem_wait_target : 20;
+        uint32_t reserved0         : 4;
+        uint32_t lp_ana_wait_target: 8;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl5_reg_t;
+
+typedef union {
+    struct {
+        uint32_t soc_wakeup_wait    : 20;
+        uint32_t reserved0          : 10;
+        uint32_t soc_wakeup_wait_cfg: 2;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl6_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 16;
+        uint32_t ana_wait_target: 16;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl7_reg_t;
+
+typedef struct pmu_wakeup_hw_regmap_t{
+    pmu_slp_wakeup_cntl0_reg_t     cntl0;
+    pmu_slp_wakeup_cntl1_reg_t     cntl1;
+    uint32_t                       cntl2;
+    pmu_slp_wakeup_cntl3_reg_t     cntl3;
+    pmu_slp_wakeup_cntl4_reg_t     cntl4;
+    pmu_slp_wakeup_cntl5_reg_t     cntl5;
+    pmu_slp_wakeup_cntl6_reg_t     cntl6;
+    pmu_slp_wakeup_cntl7_reg_t     cntl7;
+    uint32_t                       status0;
+    uint32_t                       status1;
+} pmu_wakeup_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t i2c_por_wait_target: 8;
+        uint32_t reserved0          : 24;
+    };
+    uint32_t val;
+} pmu_hp_clk_poweron_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modify_icg_cntl_wait: 8;
+        uint32_t switch_icg_cntl_wait: 8;
+        uint32_t reserved0           : 16;
+    };
+    uint32_t val;
+} pmu_hp_clk_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t por_done : 1;
+    };
+    uint32_t val;
+} pmu_por_status_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0     : 23;
+        uint32_t xpd_ckgen5g   : 1;
+        uint32_t xpd_tc5g_i2c  : 1;
+        uint32_t xpd_rx5g_i2c  : 1;
+        uint32_t perif_i2c_rstb: 1;
+        uint32_t xpd_perif_i2c : 1;
+        uint32_t xpd_txrf_i2c  : 1;
+        uint32_t xpd_rfrx_pbus : 1;
+        uint32_t xpd_ckgen_i2c : 1;
+        uint32_t xpd_pll_i2c   : 1;
+    };
+    uint32_t val;
+} pmu_rf_pwc_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t backup_sysclk_nodiv: 1;
+    };
+    uint32_t val;
+} pmu_backup_cfg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 27;
+        uint32_t lp_cpu_exc: 1;
+        uint32_t sdio_idle : 1;
+        uint32_t sw        : 1;
+        uint32_t reject    : 1;
+        uint32_t wakeup    : 1;
+    };
+    uint32_t val;
+} pmu_hp_intr_reg_t;
+
+typedef struct pmu_hp_ext_hw_regmap_t{
+    pmu_hp_clk_poweron_reg_t   clk_poweron;
+    pmu_hp_clk_cntl_reg_t      clk_cntl;
+    pmu_por_status_reg_t       por_status;
+    pmu_rf_pwc_reg_t           rf_pwc;
+    pmu_backup_cfg_reg_t       backup_cfg;
+    pmu_hp_intr_reg_t          int_raw;
+    pmu_hp_intr_reg_t          int_st;
+    pmu_hp_intr_reg_t          int_ena;
+    pmu_hp_intr_reg_t          int_clr;
+} pmu_hp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0                : 20;
+        uint32_t lp_cpu_wakeup            : 1;
+        uint32_t modem_switch_active_end  : 1;
+        uint32_t sleep_switch_active_end  : 1;
+        uint32_t sleep_switch_modem_end   : 1;
+        uint32_t modem_switch_sleep_end   : 1;
+        uint32_t active_swtich_sleep_end  : 1;
+        uint32_t modem_switch_active_start: 1;
+        uint32_t sleep_switch_active_start: 1;
+        uint32_t sleep_switch_modem_start : 1;
+        uint32_t modem_switch_sleep_start : 1;
+        uint32_t active_switch_sleep_start: 1;
+        uint32_t sw_trigger               : 1;
+    };
+    uint32_t val;
+} pmu_lp_intr_reg_t;
+
+typedef union {
+    struct {
+        uint32_t waiti_rdy         : 1;
+        uint32_t stall_rdy         : 1;
+        uint32_t reserved0         : 16;
+        uint32_t force_stall       : 1;
+        uint32_t slp_waiti_flag_en : 1;
+        uint32_t slp_stall_flag_en : 1;
+        uint32_t slp_stall_wait    : 8;
+        uint32_t slp_stall_en      : 1;
+        uint32_t slp_reset_en      : 1;
+        uint32_t slp_bypass_intr_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_en: 16;
+        uint32_t reserved0: 15;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr1_reg_t;
+
+typedef struct pmu_lp_ext_hw_regmap_t{
+    pmu_lp_intr_reg_t          int_raw;
+    pmu_lp_intr_reg_t          int_st;
+    pmu_lp_intr_reg_t          int_ena;
+    pmu_lp_intr_reg_t          int_clr;
+    pmu_lp_cpu_pwr0_reg_t      pwr0;
+    pmu_lp_cpu_pwr1_reg_t      pwr1;
+} pmu_lp_ext_hw_regmap_t;
+
+typedef struct pmu_dev_t{
+    volatile pmu_hp_hw_regmap_t     hp_sys[3];
+    volatile pmu_lp_hw_regmap_t     lp_sys[2];
+    volatile pmu_imm_hw_regmap_t    imm;
+    volatile pmu_power_hw_regmap_t  power;
+    volatile pmu_wakeup_hw_regmap_t wakeup;
+    volatile pmu_hp_ext_hw_regmap_t hp_ext;
+    volatile pmu_lp_ext_hw_regmap_t lp_ext;
+
+    union {
+        struct {
+            uint32_t reserved0    : 30;
+            volatile uint32_t lp_trigger_hp: 1;
+            volatile uint32_t hp_trigger_lp: 1;
+        };
+        volatile uint32_t val;
+    } hp_lp_cpu_comm;
+
+    union {
+        struct {
+            uint32_t reserved0           : 31;
+            volatile uint32_t dig_regulator_en_cal: 1;
+        };
+        volatile uint32_t val;
+    } hp_regulator_cfg;
+
+    union {
+        struct {
+            uint32_t reserved0 : 11;
+            volatile uint32_t last_st   : 7;
+            volatile uint32_t target_st : 7;
+            volatile uint32_t current_st: 7;
+        };
+        volatile uint32_t val;
+    } main_state;
+
+    union {
+        struct {
+            uint32_t reserved0: 13;
+            volatile uint32_t backup_st: 5;
+            volatile uint32_t lp_pwr_st: 5;
+            volatile uint32_t hp_pwr_st: 9;
+        };
+        volatile uint32_t val;
+    } pwr_state;
+
+    union {
+        struct {
+            volatile uint32_t stable_xpd_bbpll : 1;
+            volatile uint32_t stable_xpd_xtal  : 1;
+            volatile uint32_t reserved0        : 13;
+            volatile uint32_t sysclk_slp_sel   : 1;
+            volatile uint32_t sysclk_sel       : 2;
+            volatile uint32_t sysclk_nodiv     : 1;
+            volatile uint32_t icg_sysclk_en    : 1;
+            volatile uint32_t icg_modem_switch : 1;
+            volatile uint32_t icg_modem_code   : 2;
+            volatile uint32_t icg_slp_sel      : 1;
+            volatile uint32_t icg_global_xtal  : 1;
+            volatile uint32_t icg_global_pll   : 1;
+            volatile uint32_t ana_i2c_iso_en   : 1;
+            volatile uint32_t ana_i2c_retention: 1;
+            volatile uint32_t ana_xpd_bb_i2c   : 1;
+            volatile uint32_t ana_xpd_bbpll_i2c: 1;
+            volatile uint32_t ana_xpd_bbpll    : 1;
+            volatile uint32_t ana_xpd_xtal     : 1;
+        };
+        volatile uint32_t val;
+    } clk_state0;
+
+    volatile uint32_t clk_state1;
+    volatile uint32_t clk_state2;
+
+    union {
+        struct {
+            uint32_t reserved0             : 31;
+            volatile uint32_t stable_vdd_spi_pwr_drv: 1;
+        };
+        volatile uint32_t val;
+    } vdd_spi_status;
+
+    union {
+        struct {
+            volatile uint32_t pmu_date: 31;
+            volatile uint32_t clk_en  : 1;
+        };
+        volatile uint32_t val;
+    } date;
+} pmu_dev_t;
+
+extern pmu_dev_t PMU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pmu_dev_t) == 0x1ac, "Invalid size of pmu_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/include/soc/pvt_reg.h b/components/soc/esp32c5/register/soc/pvt_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pvt_reg.h
rename to components/soc/esp32c5/register/soc/pvt_reg.h
diff --git a/components/soc/esp32c5/include/soc/pvt_struct.h b/components/soc/esp32c5/register/soc/pvt_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/pvt_struct.h
rename to components/soc/esp32c5/register/soc/pvt_struct.h
diff --git a/components/soc/esp32c5/register/soc/reg_base.h b/components/soc/esp32c5/register/soc/reg_base.h
new file mode 100644
index 00000000000..b2516ec71ca
--- /dev/null
+++ b/components/soc/esp32c5/register/soc/reg_base.h
@@ -0,0 +1,113 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @brief Peripheral 0 Modules
+ *
+ */
+#define DR_REG_UART0_BASE                         0x60000000
+#define DR_REG_UART1_BASE                         0x60001000
+#define DR_REG_SPIMEM0_BASE                       0x60002000
+#define DR_REG_SPIMEM1_BASE                       0x60003000
+#define DR_REG_I2C_BASE                           0x60004000
+#define DR_REG_UHCI_BASE                          0x60005000
+#define DR_REG_RMT_BASE                           0x60006000
+#define DR_REG_LEDC_BASE                          0x60007000
+#define DR_REG_TIMERG0_BASE                       0x60008000
+#define DR_REG_TIMERG1_BASE                       0x60009000
+#define DR_REG_SYSTIMER_BASE                      0x6000A000
+#define DR_REG_TWAI0_BASE                         0x6000B000
+#define DR_REG_I2S_BASE                           0x6000C000
+#define DR_REG_TWAI1_BASE                         0x6000D000
+#define DR_REG_APB_SARADC_BASE                    0x6000E000
+#define DR_REG_USB_SERIAL_JTAG_BASE               0x6000F000
+#define DR_REG_INTERRUPT_MATRIX_BASE              0x60010000
+#define DR_REG_INTERRUPT_CORE0_BASE               DR_REG_INTERRUPT_MATRIX_BASE
+#define DR_REG_PCNT_BASE                          0x60012000
+#define DR_REG_SOC_ETM_BASE                       0x60013000
+#define DR_REG_MCPWM_BASE                         0x60014000
+#define DR_REG_PARL_IO_BASE                       0x60015000
+#define DR_REG_PVT_MONITOR_BASE                   0x60019000
+#define DR_REG_PSRAM_MEM_MONITOR_BASE             0x6001A000
+
+/**
+ * @brief Peripheral 1 Modules
+ *
+ */
+#define DR_REG_AHB_DMA_BASE                       0x60080000
+#define DR_REG_SPI2_BASE                          0x60081000
+#define DR_REG_BITSCRAMBLER_BASE                  0x60082000
+#define DR_REG_KEYMNG_BASE                        0x60087000
+#define DR_REG_AES_BASE                           0x60088000
+#define DR_REG_SHA_BASE                           0x60089000
+#define DR_REG_RSA_BASE                           0x6008A000
+#define DR_REG_ECC_MULT_BASE                      0x6008B000
+#define DR_REG_DS_BASE                            0x6008C000
+#define DR_REG_HMAC_BASE                          0x6008D000
+#define DR_REG_ECDSA_BASE                         0x6008E000
+
+/**
+ * @brief HP Top Peripheral Modules
+ *
+ */
+#define DR_REG_IO_MUX_BASE                        0x60090000
+#define DR_REG_GPIO_BASE                          0x60091000
+#define DR_REG_GPIO_EXT_BASE                      0x60091e00
+#define DR_REG_MEM_MONITOR_BASE                   0x60092000
+#define DR_REG_PAU_BASE                           0x60093000
+#define DR_REG_HP_SYSTEM_BASE                     0x60095000
+#define DR_REG_PCR_BASE                           0x60096000
+#define DR_REG_TEE_BASE                           0x60098000
+#define DR_REG_HP_APM_BASE                        0x60099000
+#define DR_REG_LP_APM0_BASE                       0x60099800
+#define DR_REG_MISC_BASE                          0x6009F000
+
+/**
+ * @brief Modem Module
+ *
+ */
+#define DR_REG_MODEM0_BASE                        0x600A0000
+#define DR_REG_MODEM1_BASE                        0x600AC000
+#define DR_REG_MODEM_PWR0_BASE                    0x600AD000
+#define DR_REG_MODEM_PWR1_BASE                    0x600AF000
+
+#define PWDET_CONF_REG                            0x600A0810
+#define DR_REG_I2C_ANA_MST_BASE                   0x600AF800
+#define IEEE802154_REG_BASE                       0x600A3000
+
+/**
+ * @brief LP System (RTC) Modules
+ *
+ */
+#define DR_REG_PMU_BASE                           0x600B0000
+#define DR_REG_LP_CLKRST_BASE                     0x600B0400
+#define DR_REG_LP_TIMER_BASE                      0x600B0C00
+#define DR_REG_LP_AON_BASE                        0x600B1000
+#define DR_REG_LP_UART_BASE                       0x600B1400
+#define DR_REG_LP_I2C_BASE                        0x600B1800
+#define DR_REG_LP_WDT_BASE                        0x600B1C00
+#define DR_REG_LP_I2C_ANA_MST_BASE                0x600B2400
+#define DR_REG_LPPERI_BASE                        0x600B2800
+#define DR_REG_LP_ANA_BASE                        0x600B2C00
+#define DR_REG_HUK_BASE                           0x600B3000
+#define DR_REG_LP_TEE_BASE                        0x600B3400
+#define DR_REG_LP_APM_BASE                        0x600B3800
+#define DR_REG_LP_IO_MUX_BASE                     0x600B4000
+#define DR_REG_LP_GPIO_BASE                       0x600B4400
+#define DR_REG_EFUSE_BASE                         0x600B4800
+#define DR_REG_OTP_DEBUG_BASE                     0x600B4D00
+
+/**
+ * @brief CPU Peripheral Modules
+ *
+ */
+#define DR_REG_TRACE_BASE                         0x600C0000
+#define DR_REG_ASSIST_DEBUG_BASE                  0x600C2000
+#define DR_REG_INTPRI_BASE                        0x600C5000
+#define DR_REG_CACHE_BASE                         0x600C8000  // CACHE_CONFIG/EXTMEM
+#define DR_REG_CLINT_M_BASE                       0x20000000
diff --git a/components/soc/esp32c5/include/soc/rmt_reg.h b/components/soc/esp32c5/register/soc/rmt_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/rmt_reg.h
rename to components/soc/esp32c5/register/soc/rmt_reg.h
diff --git a/components/soc/esp32c5/include/soc/rmt_struct.h b/components/soc/esp32c5/register/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/rmt_struct.h
rename to components/soc/esp32c5/register/soc/rmt_struct.h
diff --git a/components/soc/esp32c5/include/soc/rsa_reg.h b/components/soc/esp32c5/register/soc/rsa_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/rsa_reg.h
rename to components/soc/esp32c5/register/soc/rsa_reg.h
diff --git a/components/soc/esp32c5/include/soc/rsa_struct.h b/components/soc/esp32c5/register/soc/rsa_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/rsa_struct.h
rename to components/soc/esp32c5/register/soc/rsa_struct.h
diff --git a/components/soc/esp32c5/include/soc/sha_reg.h b/components/soc/esp32c5/register/soc/sha_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/sha_reg.h
rename to components/soc/esp32c5/register/soc/sha_reg.h
diff --git a/components/soc/esp32c5/include/soc/sha_struct.h b/components/soc/esp32c5/register/soc/sha_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/sha_struct.h
rename to components/soc/esp32c5/register/soc/sha_struct.h
diff --git a/components/soc/esp32c5/include/soc/soc_etm_reg.h b/components/soc/esp32c5/register/soc/soc_etm_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/soc_etm_reg.h
rename to components/soc/esp32c5/register/soc/soc_etm_reg.h
diff --git a/components/soc/esp32c5/include/soc/soc_etm_struct.h b/components/soc/esp32c5/register/soc/soc_etm_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/soc_etm_struct.h
rename to components/soc/esp32c5/register/soc/soc_etm_struct.h
diff --git a/components/soc/esp32c5/include/soc/spi1_mem_reg.h b/components/soc/esp32c5/register/soc/spi1_mem_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/spi1_mem_reg.h
rename to components/soc/esp32c5/register/soc/spi1_mem_reg.h
diff --git a/components/soc/esp32c5/include/soc/spi1_mem_struct.h b/components/soc/esp32c5/register/soc/spi1_mem_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/spi1_mem_struct.h
rename to components/soc/esp32c5/register/soc/spi1_mem_struct.h
diff --git a/components/soc/esp32c5/include/soc/spi_mem_c_reg.h b/components/soc/esp32c5/register/soc/spi_mem_c_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/spi_mem_c_reg.h
rename to components/soc/esp32c5/register/soc/spi_mem_c_reg.h
diff --git a/components/soc/esp32c5/include/soc/spi_mem_c_struct.h b/components/soc/esp32c5/register/soc/spi_mem_c_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/spi_mem_c_struct.h
rename to components/soc/esp32c5/register/soc/spi_mem_c_struct.h
diff --git a/components/soc/esp32c5/include/soc/spi_reg.h b/components/soc/esp32c5/register/soc/spi_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/spi_reg.h
rename to components/soc/esp32c5/register/soc/spi_reg.h
diff --git a/components/soc/esp32c5/include/soc/spi_struct.h b/components/soc/esp32c5/register/soc/spi_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/spi_struct.h
rename to components/soc/esp32c5/register/soc/spi_struct.h
diff --git a/components/soc/esp32c5/include/soc/systimer_reg.h b/components/soc/esp32c5/register/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/systimer_reg.h
rename to components/soc/esp32c5/register/soc/systimer_reg.h
diff --git a/components/soc/esp32c5/include/soc/systimer_struct.h b/components/soc/esp32c5/register/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/systimer_struct.h
rename to components/soc/esp32c5/register/soc/systimer_struct.h
diff --git a/components/soc/esp32c5/include/soc/tee_reg.h b/components/soc/esp32c5/register/soc/tee_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/tee_reg.h
rename to components/soc/esp32c5/register/soc/tee_reg.h
diff --git a/components/soc/esp32c5/include/soc/tee_struct.h b/components/soc/esp32c5/register/soc/tee_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/tee_struct.h
rename to components/soc/esp32c5/register/soc/tee_struct.h
diff --git a/components/soc/esp32c5/include/soc/timer_group_reg.h b/components/soc/esp32c5/register/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/timer_group_reg.h
rename to components/soc/esp32c5/register/soc/timer_group_reg.h
diff --git a/components/soc/esp32c5/include/soc/timer_group_struct.h b/components/soc/esp32c5/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/timer_group_struct.h
rename to components/soc/esp32c5/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32c5/include/soc/trace_reg.h b/components/soc/esp32c5/register/soc/trace_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/trace_reg.h
rename to components/soc/esp32c5/register/soc/trace_reg.h
diff --git a/components/soc/esp32c5/include/soc/trace_struct.h b/components/soc/esp32c5/register/soc/trace_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/trace_struct.h
rename to components/soc/esp32c5/register/soc/trace_struct.h
diff --git a/components/soc/esp32c5/include/soc/twaifd_reg.h b/components/soc/esp32c5/register/soc/twaifd_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/twaifd_reg.h
rename to components/soc/esp32c5/register/soc/twaifd_reg.h
diff --git a/components/soc/esp32c5/include/soc/twaifd_struct.h b/components/soc/esp32c5/register/soc/twaifd_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/twaifd_struct.h
rename to components/soc/esp32c5/register/soc/twaifd_struct.h
diff --git a/components/soc/esp32c5/include/soc/uart_reg.h b/components/soc/esp32c5/register/soc/uart_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/uart_reg.h
rename to components/soc/esp32c5/register/soc/uart_reg.h
diff --git a/components/soc/esp32c5/register/soc/uart_struct.h b/components/soc/esp32c5/register/soc/uart_struct.h
new file mode 100644
index 00000000000..220e1201caf
--- /dev/null
+++ b/components/soc/esp32c5/register/soc/uart_struct.h
@@ -0,0 +1,1364 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  Represents the data UART $n read from FIFO.\\
+         *  Measurement unit: byte.
+         */
+        uint32_t rxfifo_rd_byte:32;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable UART receiver's timeout function.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  Configures the amount of time that the bus can remain idle before timeout.\\
+         *  Measurement unit: bit time (the time to transmit 1 bit).
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of UART_RXFIFO_FULL_INT.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  The raw interrupt status of UART_TXFIFO_EMPTY_INT.
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of UART_PARITY_ERR_INT.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of UART_FRM_ERR_INT.
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of UART_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of UART_DSR_CHG_INT.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of UART_CTS_CHG_INT.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of UART_BRK_DET_INT.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt status of UART_RXFIFO_TOUT_INT.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt status of UART_SW_XON_INT.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  UART_SW_XOFF_INT.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt status of UART_GLITCH_DET_INT.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt status of UART_TX_BRK_DONE_INT.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt status of UART_TX_BRK_IDLE_DONE_INT.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt status of UART_TX_DONE_INT.
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt status of UART_RS485_PARITY_ERR_INT.
+         */
+        uint32_t rs485_parity_err_int_raw:1;
+        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw interrupt status of UART_RS485_FRM_ERR_INT.
+         */
+        uint32_t rs485_frm_err_int_raw:1;
+        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw interrupt status of UART_RS485_CLASH_INT.
+         */
+        uint32_t rs485_clash_int_raw:1;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw interrupt status of UART_AT_CMD_CHAR_DET_INT.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw interrupt status of UART_WAKEUP_INT.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of UART_RXFIFO_FULL_INT.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of UART_TXFIFO_EMPTY_INT.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of UART_PARITY_ERR_INT.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of UART_FRM_ERR_INT.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of UART_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of UART_DSR_CHG_INT.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of UART_CTS_CHG_INT.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of UART_BRK_DET_INT.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status of UART_RXFIFO_TOUT_INT.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status of UART_SW_XON_INT.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status of UART_SW_XOFF_INT.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status of UART_GLITCH_DET_INT.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status of UART_TX_BRK_DONE_INT.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status of UART_TX_BRK_IDLE_DONE_INT.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status of UART_TX_DONE_INT.
+         */
+        uint32_t tx_done_int_st:1;
+        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status of UART_RS485_PARITY_ERR_INT.
+         */
+        uint32_t rs485_parity_err_int_st:1;
+        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status of UART_RS485_FRM_ERR_INT.
+         */
+        uint32_t rs485_frm_err_int_st:1;
+        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status of UART_RS485_CLASH_INT.
+         */
+        uint32_t rs485_clash_int_st:1;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status of UART_AT_CMD_CHAR_DET_INT.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  The masked interrupt status of UART_WAKEUP_INT.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable UART_RXFIFO_FULL_INT.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable UART_TXFIFO_EMPTY_INT.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable UART_PARITY_ERR_INT.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable UART_FRM_ERR_INT.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable UART_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable UART_DSR_CHG_INT.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable UART_CTS_CHG_INT.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable UART_BRK_DET_INT.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable UART_RXFIFO_TOUT_INT.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable UART_SW_XON_INT.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable UART_SW_XOFF_INT.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable UART_GLITCH_DET_INT.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable UART_TX_BRK_DONE_INT.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable UART_TX_BRK_IDLE_DONE_INT.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable UART_TX_DONE_INT.
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Write 1 to enable UART_RS485_PARITY_ERR_INT.
+         */
+        uint32_t rs485_parity_err_int_ena:1;
+        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable UART_RS485_FRM_ERR_INT.
+         */
+        uint32_t rs485_frm_err_int_ena:1;
+        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable UART_RS485_CLASH_INT.
+         */
+        uint32_t rs485_clash_int_ena:1;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable UART_AT_CMD_CHAR_DET_INT.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  Write 1 to enable UART_WAKEUP_INT.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear UART_RXFIFO_FULL_INT.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear UART_TXFIFO_EMPTY_INT.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear UART_PARITY_ERR_INT.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear UART_FRM_ERR_INT.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear UART_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear UART_DSR_CHG_INT.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear UART_CTS_CHG_INT.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear UART_BRK_DET_INT.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear UART_RXFIFO_TOUT_INT.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear UART_SW_XON_INT.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear UART_SW_XOFF_INT.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear UART_GLITCH_DET_INT.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear UART_TX_BRK_DONE_INT.
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear UART_TX_BRK_IDLE_DONE_INT.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear UART_TX_DONE_INT.
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  Write 1 to clear UART_RS485_PARITY_ERR_INT.
+         */
+        uint32_t rs485_parity_err_int_clr:1;
+        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear UART_RS485_FRM_ERR_INT.
+         */
+        uint32_t rs485_frm_err_int_clr:1;
+        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear UART_RS485_CLASH_INT.
+         */
+        uint32_t rs485_clash_int_clr:1;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear UART_AT_CMD_CHAR_DET_INT.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Write 1 to clear UART_WAKEUP_INT.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
+         *  Configures the integral part of the divisor for baud rate generation.
+         */
+        uint32_t clkdiv_int:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  Configures the fractional part of the divisor for baud rate generation.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  RX filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's
+         *  clock cycle.\\Pulses whose width is lower than this value will be ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable RX signal filter.\\
+         *  0: Disable\\
+         *  1: Enable
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  Configuration register 0
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  Configures the parity check mode.\\
+         *  0: Even parity\\
+         *  1: Odd parity\\
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable UART parity check.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  Configures the number of data bits.\\
+         *  0: 5 bits\\
+         *  1: 6 bits\\
+         *  2: 7 bits\\
+         *  3: 8 bits\\
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  Configures the number of stop bits.\\
+         *  0: Invalid. No effect\\
+         *  1: 1 bits\\
+         *  2: 1.5 bits\\
+         *  3: 2 bits\\
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to send NULL characters when finishing data
+         *  transmission.\\
+         *  0: Not send\\
+         *  1: Send\\
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable IrDA loopback test.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable the IrDA transmitter.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [9]; default: 0;
+         *  Configures the 11th bit of the IrDA transmitter.\\
+         *  0: This bit is 0.\\
+         *  1: This bit is the same as the 10th bit.\\
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to invert the level of the IrDA transmitter.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert the level of the IrDA receiver.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable UART loopback test.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable flow control for the transmitter.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable IrDA protocol.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t irda_en:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to invert the level of UART RXD signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to invert the level of UART TXD signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to disable data overflow detection for the UART
+         *  receiver.\\
+         *  0: Enable\\
+         *  1: Disable\\
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to store the received data with errors into FIFO.\\
+         *  0: Store\\
+         *  1: Not store\\
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable baud rate detection.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable clock gating for UART memory.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  Configures the RTS signal used in software flow control.\\
+         *  0: The UART transmitter is allowed to send data.\\
+         *  1: The UART transmitted is not allowed to send data.\\
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to reset the UART RX FIFO.\\
+         *  0: Not reset\\
+         *  1: Reset\\
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to reset the UART TX FIFO.\\
+         *  0: Not reset\\
+         *  1: Reset\\
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
+         *  Configures the threshold for RX FIFO being full.\\Measurement unit: byte.
+         */
+        uint32_t rxfifo_full_thrhd:8;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
+         *  Configures the threshold for TX FIFO being empty.\\Measurement unit: byte.
+         */
+        uint32_t txfifo_empty_thrhd:8;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to invert the level of UART CTS signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to invert the level of UART DSR signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to invert the level of UART RTS signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to invert the level of UART DTR signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  Configures the DTR signal used in software flow control.\\
+         *  0: Data to be transmitted is not ready.\\
+         *  1: Data to be transmitted is ready.\\
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  Configures clock gating.\\
+         *  0: Support clock only when the application writes registers.\\
+         *  1: Always force the clock on for registers.\\
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow control configuration
+ */
+typedef union {
+    struct {
+        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the maximum number of data bytes that can be received  during hardware
+         *  flow control.\\Measurement unit: byte.
+         */
+        uint32_t rx_flow_thrhd:8;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable the UART receiver.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configuration register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  Configures wakeup character 1.
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  Configures wakeup character 2.
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  Configures wakeup character 3.
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  Configures wakeup character 4.
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configuration register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  Configures wakeup character 0.
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configuration register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  Configures the number of RXD edge changes to wake up the chip in wakeup mode 0.
+         */
+        uint32_t active_threshold:10;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
+         *  Configures the number of received data bytes to wake up the chip in wakeup mode 1.
+         */
+        uint32_t rx_wake_up_thrhd:8;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  Configures the number of wakeup characters.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  Configures whether or not to mask wakeup characters.\\
+         *  0: Not mask\\
+         *  1: Mask\\
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  Configures which wakeup mode to select.\\
+         *  0: Mode 0\\
+         *  1: Mode 1\\
+         *  2: Mode 2\\
+         *  3: Mode 3\\
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_character : R/W; bitpos: [7:0]; default: 17;
+         *  Configures the XON character for flow control.
+         */
+        uint32_t xon_character:8;
+        /** xoff_character : R/W; bitpos: [15:8]; default: 19;
+         *  Configures the XOFF character for flow control.
+         */
+        uint32_t xoff_character:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  Configures whether the UART transmitter can send XON or XOFF characters when it is
+         *  disabled.\\
+         *  0: Cannot send\\
+         *  1: Can send\\
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable software flow control.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to remove flow control characters from the received
+         *  data.\\
+         *  0: Not move\\
+         *  1: Move\\
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Configures whether the transmitter continues to sending data.\\
+         *  0: Not send\\
+         *  1: Send\\
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to stop the transmitter from sending data.\\
+         *  0: Not stop\\
+         *  1: Stop\\
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Configures whether or not to send XON characters.\\
+         *  0: Not send\\
+         *  1: Send\\
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Configures whether or not to send XOFF characters.\\
+         *  0: Not send\\
+         *  1: Send\\
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the threshold for data in RX FIFO to send XON characters in software
+         *  flow control.\\Measurement unit: byte.
+         */
+        uint32_t xon_threshold:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
+         *  Configures the threshold for data in RX FIFO to send XOFF characters in software
+         *  flow control.\\Measurement unit: byte.
+         */
+        uint32_t xoff_threshold:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  TX break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  Configures the number of NULL characters to be sent after finishing data
+         *  transmission.\\Valid only when UART_TXD_BRK is 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame end idle time configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  Configures the threshold to generate a frame end signal when the receiver takes
+         *  more time to receive one data byte data.\\Measurement unit: bit time (the time to
+         *  transmit 1 bit).
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  Configures the interval between two data transfers.\\Measurement unit: bit time
+         *  (the time to transmit 1 bit).
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable RS485 mode.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\
+         *  0: Not add\\
+         *  1: Add\\
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\
+         *  0: Not add\\
+         *  1: Add\\
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable the receiver for data reception when the
+         *  transmitter is transmitting data in RS485 mode.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable the RS485 transmitter for data transmission when the
+         *  RS485 receiver is busy.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  Configures the delay of internal data signals in the receiver.\\Measurement unit:
+         *  bit time (the time to transmit 1 bit)..
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  Configures the delay of internal data signals in the transmitter.\\Measurement
+         *  unit: bit time (the time to transmit 1 bit).
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.'
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         *  Only available to LP UART instance
+         */
+        uint32_t sclk_div_num:8;
+        uint32_t reserved_20:4;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Configures whether or not to enable UART TX clock.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Configures whether or not to enable UART RX clock.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 and then write 0 to reset UART TX.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 and then write 0 to reset UART RX.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
+         *  Represents the number of valid data bytes in RX FIFO.
+         */
+        uint32_t rxfifo_cnt:8;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  Represents the level of the internal UART DSR signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  Represents the level of the internal UART CTS signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  Represents the  level of the internal UART RXD signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
+         *  Represents the number of valid data bytes in RX FIFO.
+         */
+        uint32_t txfifo_cnt:8;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  Represents the level of the internal UART DTR signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  Represents the level of the internal UART RTS signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  Represents the  level of the internal UART TXD signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  TX FIFO write and read offset address
+ */
+typedef union {
+    struct {
+        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
+         *  Represents the offset address to write TX FIFO.
+         */
+        uint32_t tx_sram_waddr:8;
+        uint32_t reserved_8:1;
+        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
+         *  Represents the offset address to read TX FIFO.
+         */
+        uint32_t tx_sram_raddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx FIFO write and read offset address
+ */
+typedef union {
+    struct {
+        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
+         *  Represents the offset address to read RX FIFO.
+         */
+        uint32_t rx_sram_raddr:8;
+        uint32_t reserved_8:1;
+        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
+         *  Represents the offset address to write RX FIFO.
+         */
+        uint32_t rx_sram_waddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  Represents the status of the receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  Represents the status of the transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART asynchronous FIFO status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the APB TX asynchronous FIFO is full.\\
+         *  0: Not full\\
+         *  1: Full\\
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Represents whether or not the APB TX asynchronous FIFO is empty.\\
+         *  0: Not empty\\
+         *  1: Empty\\
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Represents whether or not the APB RX asynchronous FIFO is full.\\
+         *  0: Not full\\
+         *  1: Full\\
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Represents whether or not the APB RX asynchronous FIFO is empty.\\
+         *  0: Not empty\\
+         *  1: Empty\\
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  Configures the idle time before the receiver receives the first
+         *  AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit).
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  Configures the interval between the last AT_CMD and subsequent data.\\Measurement
+         *  unit: bit time (the time to transmit 1 bit).
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  Configures the interval between two AT_CMD characters.\\Measurement unit: bit time
+         *  (the time to transmit 1 bit).
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  Configures the AT_CMD character.
+         */
+        uint32_t at_cmd_char:8;
+        /** at_char_num : R/W; bitpos: [15:8]; default: 3;
+         *  Configures the number of continuous AT_CMD characters a receiver can receive.
+         */
+        uint32_t at_char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  Represents the minimal input clock counter value between two positive edges. It is
+         *  used for baud rate detection.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  Represents the minimal input clock counter value between two negative edges. It is
+         *  used for baud rate detection.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  Represents the minimum duration time of a low-level pulse. It is used for baud rate
+         *  detection.\\Measurement unit: APB_CLK clock cycle.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  Represents  the maximum duration time for a high-level pulse. It is used for baud
+         *  rate detection.\\Measurement unit: APB_CLK clock cycle.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  Represents the number of RXD edge changes. It is used for baud rate detection.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36774432;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART register configuration update
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether or not to synchronize registers.\\
+         *  0: Not synchronize\\
+         *  1: Synchronize\\
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  Configures the UART ID.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct {
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_sync_reg_t conf0_sync;
+    volatile uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile uart_sleep_conf0_reg_t sleep_conf0;
+    volatile uart_sleep_conf1_reg_t sleep_conf1;
+    volatile uart_sleep_conf2_reg_t sleep_conf2;
+    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;
+    volatile uart_negpulse_reg_t negpulse;
+    volatile uart_lowpulse_reg_t lowpulse;
+    volatile uart_highpulse_reg_t highpulse;
+    volatile uart_rxd_cnt_reg_t rxd_cnt;
+    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_date_reg_t date;
+    volatile uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile uart_reg_update_reg_t reg_update;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+extern uart_dev_t LP_UART;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/include/soc/uhci_reg.h b/components/soc/esp32c5/register/soc/uhci_reg.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/uhci_reg.h
rename to components/soc/esp32c5/register/soc/uhci_reg.h
diff --git a/components/soc/esp32c5/include/soc/uhci_struct.h b/components/soc/esp32c5/register/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32c5/include/soc/uhci_struct.h
rename to components/soc/esp32c5/register/soc/uhci_struct.h
diff --git a/components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h
new file mode 100644
index 00000000000..255d08ed4bb
--- /dev/null
+++ b/components/soc/esp32c5/register/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,1228 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
+ *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
+ *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
+ *  how many data is received, then read data from UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
+ *  USB Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFH_S  3
+/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFL_S  5
+/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+ *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+ *  through GPIO Matrix.
+ */
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
+ *  USB RCV value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
+ *  USB D+ rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_SERIAL_JTAG_CHIP_RST_REG register
+ *  CDC-ACM chip reset control.
+ */
+#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
+/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
+ *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_RTS    (BIT(0))
+#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
+#define USB_SERIAL_JTAG_RTS_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_S  0
+/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
+ *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_DTR    (BIT(1))
+#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
+#define USB_SERIAL_JTAG_DTR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_S  1
+/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable chip reset from usb serial channel to reset chip.
+ */
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
+ *  W0 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
+/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
+ *  W1 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
+/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
+/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_S  16
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
+ *  W0 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
+/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
+ *  W1 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
+/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
+/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
+
+/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
+ *  Configuration registers' value update
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
+/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this register would update the value of configure registers from APB
+ *  clock domain to 48MHz clock domain.
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
+
+/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
+ *  Serial AFIFO configure register
+ */
+#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
+ *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
+
+/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
+ *  USB Bus reset status register
+ */
+#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
+/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
+ *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+ *  reset is released.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
+
+/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG register
+ *  USB uart out endpoint timeout configuration.
+ */
+#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
+/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
+ *  is automatically cleared and reg_serial_timeout_status is asserted.
+ */
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S)
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S  0
+/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Serial out ep triggers a timeout event.
+ */
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S)
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S  1
+/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear reg_serial_timeout_status.
+ */
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S  2
+
+/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG register
+ *  USB uart out endpoint timeout configuration.
+ */
+#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
+/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX : R/W; bitpos: [31:0]; default: 4800768;
+ *  USB serial out ep timeout max threshold value, indicates the maximum time that
+ *  waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
+ */
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S)
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S  0
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  Date register
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368;
+ *  register version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h b/components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h
new file mode 100644
index 00000000000..603db37ff62
--- /dev/null
+++ b/components/soc/esp32c5/register/soc/usb_serial_jtag_struct.h
@@ -0,0 +1,979 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of ep1 register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+typedef union {
+    struct {
+        /** rdwr_byte : R/W; bitpos: [7:0]; default: 0;
+         *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+         *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
+         *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
+         *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
+         *  how many data is received, then read data from UART Rx FIFO.
+         */
+        uint32_t rdwr_byte:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_reg_t;
+
+/** Type of ep1_conf register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+typedef union {
+    struct {
+        /** wr_done : WT; bitpos: [0]; default: 0;
+         *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+         */
+        uint32_t wr_done:1;
+        /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
+         *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+         *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
+         *  USB Host.
+         */
+        uint32_t serial_in_ep_data_free:1;
+        /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
+         *  1'b1: Indicate there is data in UART Rx FIFO.
+         */
+        uint32_t serial_out_ep_data_avail:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_conf_reg_t;
+
+/** Type of conf0 register
+ *  PHY hardware configuration.
+ */
+typedef union {
+    struct {
+        /** phy_sel : R/W; bitpos: [0]; default: 0;
+         *  Select internal/external PHY
+         */
+        uint32_t phy_sel:1;
+        /** exchg_pins_override : R/W; bitpos: [1]; default: 0;
+         *  Enable software control USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [2]; default: 0;
+         *  USB D+ D- exchange
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [4:3]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [6:5]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [7]; default: 0;
+         *  Enable software control input  threshold
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [8]; default: 0;
+         *  Enable software control USB D+ D- pullup pulldown
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [9]; default: 1;
+         *  Control USB D+ pull up.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [10]; default: 0;
+         *  Control USB D+ pull down.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [11]; default: 0;
+         *  Control USB D- pull up.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [12]; default: 0;
+         *  Control USB D- pull down.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [13]; default: 0;
+         *  Control pull up value.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [14]; default: 1;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
+         *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+         *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+         *  through GPIO Matrix.
+         */
+        uint32_t usb_jtag_bridge_en:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_conf0_reg_t;
+
+/** Type of test register
+ *  Registers used for debugging the PHY.
+ */
+typedef union {
+    struct {
+        /** test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable test of the USB pad
+         */
+        uint32_t test_enable:1;
+        /** test_usb_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test
+         */
+        uint32_t test_usb_oe:1;
+        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test
+         */
+        uint32_t test_tx_dp:1;
+        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test
+         */
+        uint32_t test_tx_dm:1;
+        /** test_rx_rcv : RO; bitpos: [4]; default: 1;
+         *  USB RCV value in test
+         */
+        uint32_t test_rx_rcv:1;
+        /** test_rx_dp : RO; bitpos: [5]; default: 1;
+         *  USB D+ rx value in test
+         */
+        uint32_t test_rx_dp:1;
+        /** test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test
+         */
+        uint32_t test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_serial_jtag_test_reg_t;
+
+/** Type of misc_conf register
+ *  Clock enable control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_misc_conf_reg_t;
+
+/** Type of mem_conf register
+ *  Memory power control
+ */
+typedef union {
+    struct {
+        /** usb_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  1: power down usb memory.
+         */
+        uint32_t usb_mem_pd:1;
+        /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
+         *  1: Force clock on for usb memory.
+         */
+        uint32_t usb_mem_clk_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_mem_conf_reg_t;
+
+/** Type of chip_rst register
+ *  CDC-ACM chip reset control.
+ */
+typedef union {
+    struct {
+        /** rts : RO; bitpos: [0]; default: 0;
+         *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+         */
+        uint32_t rts:1;
+        /** dtr : RO; bitpos: [1]; default: 0;
+         *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+         */
+        uint32_t dtr:1;
+        /** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to disable chip reset from usb serial channel to reset chip.
+         */
+        uint32_t usb_uart_chip_rst_dis:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_chip_rst_reg_t;
+
+/** Type of get_line_code_w0 register
+ *  W0 of GET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
+         *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_dw_dte_rate:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_get_line_code_w0_reg_t;
+
+/** Type of get_line_code_w1 register
+ *  W1 of GET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
+         *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bdata_bits:8;
+        /** get_bparity_type : R/W; bitpos: [15:8]; default: 0;
+         *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bparity_type:8;
+        /** get_bchar_format : R/W; bitpos: [23:16]; default: 0;
+         *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+         *  command.
+         */
+        uint32_t get_bchar_format:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} usb_serial_jtag_get_line_code_w1_reg_t;
+
+/** Type of config_update register
+ *  Configuration registers' value update
+ */
+typedef union {
+    struct {
+        /** config_update : WT; bitpos: [0]; default: 0;
+         *  Write 1 to this register would update the value of configure registers from APB
+         *  clock domain to 48MHz clock domain.
+         */
+        uint32_t config_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_config_update_reg_t;
+
+/** Type of ser_afifo_config register
+ *  Serial AFIFO configure register
+ */
+typedef union {
+    struct {
+        /** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+         */
+        uint32_t serial_in_afifo_reset_wr:1;
+        /** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+         */
+        uint32_t serial_in_afifo_reset_rd:1;
+        /** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+         */
+        uint32_t serial_out_afifo_reset_wr:1;
+        /** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+         */
+        uint32_t serial_out_afifo_reset_rd:1;
+        /** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
+         *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
+         */
+        uint32_t serial_out_afifo_rempty:1;
+        /** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
+         *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+         */
+        uint32_t serial_in_afifo_wfull:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} usb_serial_jtag_ser_afifo_config_reg_t;
+
+/** Type of serial_ep_timeout0 register
+ *  USB uart out endpoint timeout configuration.
+ */
+typedef union {
+    struct {
+        /** serial_timeout_en : R/W; bitpos: [0]; default: 0;
+         *  USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
+         *  is automatically cleared and reg_serial_timeout_status is asserted.
+         */
+        uint32_t serial_timeout_en:1;
+        /** serial_timeout_status : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Serial out ep triggers a timeout event.
+         */
+        uint32_t serial_timeout_status:1;
+        /** serial_timeout_status_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear reg_serial_timeout_status.
+         */
+        uint32_t serial_timeout_status_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_serial_ep_timeout0_reg_t;
+
+/** Type of serial_ep_timeout1 register
+ *  USB uart out endpoint timeout configuration.
+ */
+typedef union {
+    struct {
+        /** serial_timeout_max : R/W; bitpos: [31:0]; default: 4800768;
+         *  USB serial out ep timeout max threshold value, indicates the maximum time that
+         *  waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
+         */
+        uint32_t serial_timeout_max:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_serial_ep_timeout1_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  Interrupt raw status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when flush cmd is received for IN
+         *  endpoint 2 of JTAG.
+         */
+        uint32_t jtag_in_flush_int_raw:1;
+        /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when SOF frame is received.
+         */
+        uint32_t sof_int_raw:1;
+        /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+         *  one packet.
+         */
+        uint32_t serial_out_recv_pkt_int_raw:1;
+        /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
+         *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+         */
+        uint32_t serial_in_empty_int_raw:1;
+        /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when pid error is detected.
+         */
+        uint32_t pid_err_int_raw:1;
+        /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC5 error is detected.
+         */
+        uint32_t crc5_err_int_raw:1;
+        /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC16 error is detected.
+         */
+        uint32_t crc16_err_int_raw:1;
+        /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when stuff error is detected.
+         */
+        uint32_t stuff_err_int_raw:1;
+        /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+         *  received.
+         */
+        uint32_t in_token_rec_in_ep1_int_raw:1;
+        /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when usb bus reset is detected.
+         */
+        uint32_t usb_bus_reset_int_raw:1;
+        /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+         *  zero palyload.
+         */
+        uint32_t out_ep1_zero_payload_int_raw:1;
+        /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+         *  zero palyload.
+         */
+        uint32_t out_ep2_zero_payload_int_raw:1;
+        /** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+         *  is changed.
+         */
+        uint32_t rts_chg_int_raw:1;
+        /** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+         *  is changed.
+         */
+        uint32_t dtr_chg_int_raw:1;
+        /** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+         *  received.
+         */
+        uint32_t get_line_code_int_raw:1;
+        /** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+         *  received.
+         */
+        uint32_t set_line_code_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_st:1;
+        /** sof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+         */
+        uint32_t sof_int_st:1;
+        /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+         *  interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_st:1;
+        /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_st:1;
+        /** pid_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_st:1;
+        /** crc5_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_st:1;
+        /** crc16_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_st:1;
+        /** stuff_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_st:1;
+        /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+         *  interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_st:1;
+        /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_st:1;
+        /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+         *  interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_st:1;
+        /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+         *  interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_st:1;
+        /** rts_chg_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_st:1;
+        /** dtr_chg_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_st:1;
+        /** get_line_code_int_st : RO; bitpos: [14]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_st:1;
+        /** set_line_code_int_st : RO; bitpos: [15]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_ena:1;
+        /** sof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+         */
+        uint32_t sof_int_ena:1;
+        /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_ena:1;
+        /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_ena:1;
+        /** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_ena:1;
+        /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_ena:1;
+        /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_ena:1;
+        /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_ena:1;
+        /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_ena:1;
+        /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_ena:1;
+        /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_ena:1;
+        /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_ena:1;
+        /** rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_ena:1;
+        /** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_ena:1;
+        /** get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_ena:1;
+        /** set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_clr:1;
+        /** sof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
+         */
+        uint32_t sof_int_clr:1;
+        /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_clr:1;
+        /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_clr:1;
+        /** pid_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_clr:1;
+        /** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_clr:1;
+        /** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_clr:1;
+        /** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_clr:1;
+        /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_clr:1;
+        /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_clr:1;
+        /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_clr:1;
+        /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_clr:1;
+        /** rts_chg_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+         */
+        uint32_t rts_chg_int_clr:1;
+        /** dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+         */
+        uint32_t dtr_chg_int_clr:1;
+        /** get_line_code_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+         */
+        uint32_t get_line_code_int_clr:1;
+        /** set_line_code_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+         */
+        uint32_t set_line_code_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of jfifo_st register
+ *  JTAG FIFO status and control registers.
+ */
+typedef union {
+    struct {
+        /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
+         *  JTAT in fifo counter.
+         */
+        uint32_t in_fifo_cnt:2;
+        /** in_fifo_empty : RO; bitpos: [2]; default: 1;
+         *  1: JTAG in fifo is empty.
+         */
+        uint32_t in_fifo_empty:1;
+        /** in_fifo_full : RO; bitpos: [3]; default: 0;
+         *  1: JTAG in fifo is full.
+         */
+        uint32_t in_fifo_full:1;
+        /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
+         *  JTAT out fifo counter.
+         */
+        uint32_t out_fifo_cnt:2;
+        /** out_fifo_empty : RO; bitpos: [6]; default: 1;
+         *  1: JTAG out fifo is empty.
+         */
+        uint32_t out_fifo_empty:1;
+        /** out_fifo_full : RO; bitpos: [7]; default: 0;
+         *  1: JTAG out fifo is full.
+         */
+        uint32_t out_fifo_full:1;
+        /** in_fifo_reset : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to reset JTAG in fifo.
+         */
+        uint32_t in_fifo_reset:1;
+        /** out_fifo_reset : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to reset JTAG out fifo.
+         */
+        uint32_t out_fifo_reset:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} usb_serial_jtag_jfifo_st_reg_t;
+
+/** Type of fram_num register
+ *  Last received SOF frame index register.
+ */
+typedef union {
+    struct {
+        /** sof_frame_index : RO; bitpos: [10:0]; default: 0;
+         *  Frame index of received SOF frame.
+         */
+        uint32_t sof_frame_index:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} usb_serial_jtag_fram_num_reg_t;
+
+/** Type of in_ep0_st register
+ *  Control IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep0_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 0.
+         */
+        uint32_t in_ep0_state:2;
+        /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 0.
+         */
+        uint32_t in_ep0_wr_addr:7;
+        /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 0.
+         */
+        uint32_t in_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep0_st_reg_t;
+
+/** Type of in_ep1_st register
+ *  CDC-ACM IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep1_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 1.
+         */
+        uint32_t in_ep1_state:2;
+        /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 1.
+         */
+        uint32_t in_ep1_wr_addr:7;
+        /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 1.
+         */
+        uint32_t in_ep1_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep1_st_reg_t;
+
+/** Type of in_ep2_st register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep2_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 2.
+         */
+        uint32_t in_ep2_state:2;
+        /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 2.
+         */
+        uint32_t in_ep2_wr_addr:7;
+        /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 2.
+         */
+        uint32_t in_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep2_st_reg_t;
+
+/** Type of in_ep3_st register
+ *  JTAG IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep3_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 3.
+         */
+        uint32_t in_ep3_state:2;
+        /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 3.
+         */
+        uint32_t in_ep3_wr_addr:7;
+        /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 3.
+         */
+        uint32_t in_ep3_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep3_st_reg_t;
+
+/** Type of out_ep0_st register
+ *  Control OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep0_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 0.
+         */
+        uint32_t out_ep0_state:2;
+        /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+         *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+         */
+        uint32_t out_ep0_wr_addr:7;
+        /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 0.
+         */
+        uint32_t out_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep0_st_reg_t;
+
+/** Type of out_ep1_st register
+ *  CDC-ACM OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep1_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 1.
+         */
+        uint32_t out_ep1_state:2;
+        /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+         *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+         */
+        uint32_t out_ep1_wr_addr:7;
+        /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 1.
+         */
+        uint32_t out_ep1_rd_addr:7;
+        /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
+         *  Data count in OUT endpoint 1 when one packet is received.
+         */
+        uint32_t out_ep1_rec_data_cnt:7;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep1_st_reg_t;
+
+/** Type of out_ep2_st register
+ *  JTAG OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep2_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 2.
+         */
+        uint32_t out_ep2_state:2;
+        /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+         *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+         */
+        uint32_t out_ep2_wr_addr:7;
+        /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 2.
+         */
+        uint32_t out_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep2_st_reg_t;
+
+/** Type of set_line_code_w0 register
+ *  W0 of SET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** dw_dte_rate : RO; bitpos: [31:0]; default: 0;
+         *  The value of dwDTERate set by host through SET_LINE_CODING command.
+         */
+        uint32_t dw_dte_rate:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_set_line_code_w0_reg_t;
+
+/** Type of set_line_code_w1 register
+ *  W1 of SET_LINE_CODING command.
+ */
+typedef union {
+    struct {
+        /** bchar_format : RO; bitpos: [7:0]; default: 0;
+         *  The value of bCharFormat set by host through SET_LINE_CODING command.
+         */
+        uint32_t bchar_format:8;
+        /** bparity_type : RO; bitpos: [15:8]; default: 0;
+         *  The value of bParityTpye set by host through SET_LINE_CODING command.
+         */
+        uint32_t bparity_type:8;
+        /** bdata_bits : RO; bitpos: [23:16]; default: 0;
+         *  The value of bDataBits set by host through SET_LINE_CODING command.
+         */
+        uint32_t bdata_bits:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} usb_serial_jtag_set_line_code_w1_reg_t;
+
+/** Type of bus_reset_st register
+ *  USB Bus reset status register
+ */
+typedef union {
+    struct {
+        /** usb_bus_reset_st : RO; bitpos: [0]; default: 1;
+         *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+         *  reset is released.
+         */
+        uint32_t usb_bus_reset_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_bus_reset_st_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Date register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36770368;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_date_reg_t;
+
+
+typedef struct {
+    volatile usb_serial_jtag_ep1_reg_t ep1;
+    volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
+    volatile usb_serial_jtag_int_raw_reg_t int_raw;
+    volatile usb_serial_jtag_int_st_reg_t int_st;
+    volatile usb_serial_jtag_int_ena_reg_t int_ena;
+    volatile usb_serial_jtag_int_clr_reg_t int_clr;
+    volatile usb_serial_jtag_conf0_reg_t conf0;
+    volatile usb_serial_jtag_test_reg_t test;
+    volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
+    volatile usb_serial_jtag_fram_num_reg_t fram_num;
+    volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
+    volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
+    volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
+    volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
+    volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
+    volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
+    volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
+    volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
+    volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
+    volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
+    volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
+    volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
+    volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
+    volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
+    volatile usb_serial_jtag_config_update_reg_t config_update;
+    volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
+    volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
+    volatile usb_serial_jtag_serial_ep_timeout0_reg_t serial_ep_timeout0;
+    volatile usb_serial_jtag_serial_ep_timeout1_reg_t serial_ep_timeout1;
+    uint32_t reserved_074[3];
+    volatile usb_serial_jtag_date_reg_t date;
+} usb_serial_jtag_dev_t;
+
+extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c5/rmt_periph.c b/components/soc/esp32c5/rmt_periph.c
index 87c00ebd260..aa92c87aea3 100644
--- a/components/soc/esp32c5/rmt_periph.c
+++ b/components/soc/esp32c5/rmt_periph.c
@@ -60,6 +60,7 @@ static const regdma_entries_config_t rmt_regdma_entries[] = {
 
 const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_RMT0,
         .regdma_entry_array = rmt_regdma_entries,
         .array_size = ARRAY_SIZE(rmt_regdma_entries)
     },
diff --git a/components/soc/esp32c5/spi_periph.c b/components/soc/esp32c5/spi_periph.c
index dc15ae60eaa..67fa9fdcb95 100644
--- a/components/soc/esp32c5/spi_periph.c
+++ b/components/soc/esp32c5/spi_periph.c
@@ -13,29 +13,6 @@
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
     {
         // MSPI has dedicated iomux pins
-        .spiclk_out = -1,
-        .spiclk_in = -1,
-        .spid_out = -1,
-        .spiq_out = -1,
-        .spiwp_out = -1,
-        .spihd_out = -1,
-        .spid_in = -1,
-        .spiq_in = -1,
-        .spiwp_in = -1,
-        .spihd_in = -1,
-        .spics_out = {-1},
-        .spics_in = -1,
-        .spiclk_iomux_pin = -1,
-        .spid_iomux_pin = -1,
-        .spiq_iomux_pin = -1,
-        .spiwp_iomux_pin = -1,
-        .spihd_iomux_pin = -1,
-        .spics0_iomux_pin = -1,
-        .irq = -1,
-        .irq_dma = -1,
-        .module = -1,
-        .hw = NULL,
-        .func = -1,
     }, {
         .spiclk_out = FSPICLK_OUT_IDX,
         .spiclk_in = FSPICLK_IN_IDX,
@@ -57,8 +34,50 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
         .irq = ETS_GPSPI2_INTR_SOURCE,
         .irq_dma = -1,
-        .module = -1,
         .hw = &GPSPI2,
         .func = SPI2_FUNC_NUM,
     },
 };
+
+/**
+ * Backup registers in Light sleep: (total cnt 12)
+ *
+ * cmd
+ * addr
+ * ctrl
+ * clock
+ * user
+ * user1
+ * user2
+ * ms_dlen
+ * misc
+ * dma_conf
+ * dma_int_ena
+ * slave
+ */
+#define SPI_RETENTION_REGS_CNT 12
+static const uint32_t spi_regs_map[4] = {0x31ff, 0x1000000, 0x0, 0x0};
+#define SPI_REG_RETENTION_ENTRIES(num) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
+                                               REG_SPI_BASE(num), REG_SPI_BASE(num), \
+                                               SPI_RETENTION_REGS_CNT, 0, 0, \
+                                               spi_regs_map[0], spi_regs_map[1], \
+                                               spi_regs_map[2], spi_regs_map[3]), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+    /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
+                                            SPI_DMA_INT_SET_REG(num), \
+                                            SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET , \
+                                            UINT32_MAX, 1, 0), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2);   // '2' for GPSPI2
+
+const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = {   // '-1' to except mspi
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI2,
+        .entry_array = spi2_regs_retention,
+        .array_size = ARRAY_SIZE(spi2_regs_retention),
+    },
+};
diff --git a/components/soc/esp32c5/temperature_sensor_periph.c b/components/soc/esp32c5/temperature_sensor_periph.c
index b0b6cfef7eb..45410347bda 100644
--- a/components/soc/esp32c5/temperature_sensor_periph.c
+++ b/components/soc/esp32c5/temperature_sensor_periph.c
@@ -4,7 +4,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
+#include "soc/regdma.h"
 #include "soc/temperature_sensor_periph.h"
+#include "soc/apb_saradc_reg.h"
 
 const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
     /*Offset  reg_val  min  max  error */
@@ -14,3 +17,24 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S
     { 1,       11,    -30,   50,   2},
     { 2,       10,    -40,   20,   3},
 };
+
+// Temperature sensor sleep retention entries
+// Temperature sensor registers require set the reg_update bit to make the configuration take effect
+
+/* Temperature sensor Registers Context
+   Include: APB_SARADC_INT_ENA_REG /
+            APB_SARADC_APB_TSENS_CTRL_REG / APB_SARADC_TSENS_CTRL2_REG / APB_TSENS_WAKE_REG / APB_TSENS_SAMPLE_REG
+*/
+#define TEMPERATURE_SENSOR_RETENTION_REGS_CNT  5
+#define TEMPERATURE_SENSOR_RETENTION_MAP_BASE  APB_SARADC_INT_ENA_REG
+static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0};
+static const regdma_entries_config_t temperature_sensor_regs_entries[] = {
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+};
+
+const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = {
+    .link_list = temperature_sensor_regs_entries,
+    .link_num = ARRAY_SIZE(temperature_sensor_regs_entries),
+    .module_id = SLEEP_RETENTION_MODULE_TEMP_SENSOR,
+};
diff --git a/components/soc/esp32c5/uart_periph.c b/components/soc/esp32c5/uart_periph.c
index 733cde884b9..b98467fc4b9 100644
--- a/components/soc/esp32c5/uart_periph.c
+++ b/components/soc/esp32c5/uart_periph.c
@@ -150,10 +150,12 @@ static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTI
 
 const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_UART0,
         .regdma_entry_array = uart0_regdma_entries,
         .array_size = ARRAY_SIZE(uart0_regdma_entries),
     },
     [1] = {
+        .module = SLEEP_RETENTION_MODULE_UART1,
         .regdma_entry_array = uart1_regdma_entries,
         .array_size = ARRAY_SIZE(uart1_regdma_entries),
     },
diff --git a/components/soc/esp32c6/etm_periph.c b/components/soc/esp32c6/etm_periph.c
new file mode 100644
index 00000000000..7b268c443a5
--- /dev/null
+++ b/components/soc/esp32c6/etm_periph.c
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/etm_periph.h"
+#include "soc/soc_etm_reg.h"
+
+/**
+ * ETM Registers to be saved during sleep retention
+ * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
+*/
+#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
+
+static const regdma_entries_config_t etm_regdma_entries[] = {
+    // backup stage: save the status of enabled channels
+    // restore stage: store the enabled channels
+    [0] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
+        SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    [1] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
+        SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
+        SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+};
+
+const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = {
+    [0] = {
+        .module = SLEEP_RETENTION_MODULE_ETM0,
+        .regdma_entry_array = etm_regdma_entries,
+        .array_size = ARRAY_SIZE(etm_regdma_entries)
+    },
+};
diff --git a/components/soc/esp32c6/i2c_periph.c b/components/soc/esp32c6/i2c_periph.c
index 21771444744..c2a39d3c9c6 100644
--- a/components/soc/esp32c6/i2c_periph.c
+++ b/components/soc/esp32c6/i2c_periph.c
@@ -50,7 +50,7 @@ static const regdma_entries_config_t i2c0_regs_retention[] = {
     [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
            .owner = ENTRY(0) | ENTRY(2) }, \
     [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
-    .owner = ENTRY(0) | ENTRY(2) }, \
+           .owner = ENTRY(0) | ENTRY(2) }, \
     [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
            .owner = ENTRY(0) | ENTRY(2) }, \
     [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
@@ -58,5 +58,5 @@ static const regdma_entries_config_t i2c0_regs_retention[] = {
 };
 
 const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
-    {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention)},
+    {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
 };
diff --git a/components/soc/esp32c6/i2s_periph.c b/components/soc/esp32c6/i2s_periph.c
index 0eba95654e1..fb1cea5bb1f 100644
--- a/components/soc/esp32c6/i2s_periph.c
+++ b/components/soc/esp32c6/i2s_periph.c
@@ -30,7 +30,7 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
         .data_out_sigs[1] = I2SO_SD1_OUT_IDX,
         .data_in_sig  = I2SI_SD_IN_IDX,
 
-        .irq          = ETS_I2S1_INTR_SOURCE,
+        .irq          = ETS_I2S0_INTR_SOURCE,
     }
 };
 
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index 9493c491a5d..8d594e41acf 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -459,6 +459,10 @@ config SOC_ETM_CHANNELS_PER_GROUP
     int
     default 50
 
+config SOC_ETM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_GPIO_PORT
     int
     default 1
@@ -683,6 +687,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6
@@ -707,6 +715,10 @@ config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
     int
     default 10
 
+config SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MMU_PAGE_SIZE_CONFIGURABLE
     bool
     default y
@@ -767,6 +779,10 @@ config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
     bool
     default y
 
+config SOC_PCNT_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_RMT_GROUPS
     int
     default 1
@@ -879,6 +895,10 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
     bool
     default y
 
+config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_PARLIO_GROUPS
     int
     default 1
@@ -903,6 +923,10 @@ config SOC_PARLIO_TX_RX_SHARE_INTERRUPT
     bool
     default y
 
+config SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MPI_MEM_BLOCKS_NUM
     int
     default 4
@@ -991,6 +1015,10 @@ config SOC_SPI_SUPPORT_SLAVE_HD_VER2
     bool
     default y
 
+config SOC_SPI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_SPI_SUPPORT_CLK_XTAL
     bool
     default y
@@ -1171,6 +1199,10 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
     bool
     default y
 
+config SOC_TWAI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
     bool
     default y
@@ -1435,10 +1467,18 @@ config SOC_CLK_RC32K_SUPPORTED
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    bool
+    default y
+
 config SOC_RCC_IS_INDEPENDENT
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y
@@ -1455,6 +1495,14 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM
     bool
     default y
 
+config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
+config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN
+    bool
+    default y
+
 config SOC_RNG_CLOCK_IS_INDEPENDENT
     bool
     default y
@@ -1546,3 +1594,7 @@ config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR
 config SOC_LP_CORE_SUPPORT_ETM
     bool
     default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
diff --git a/components/soc/esp32c6/include/soc/assist_debug_reg.h b/components/soc/esp32c6/include/soc/assist_debug_reg.h
deleted file mode 100644
index 8e0426dc6f5..00000000000
--- a/components/soc/esp32c6/include/soc/assist_debug_reg.h
+++ /dev/null
@@ -1,777 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
- *  core0 monitor enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
- *  IBUS busy monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor enbale
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
- *  core0 monitor interrupt status register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
- *  DBUS busy monitor initerrupt status
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
- *  core0 monitor interrupt enable register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt enbale
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
- *  core0 monitor interrupt clr register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
- *  core0 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 dram0 region0 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
- *  core0 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 dram0 region0 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
- *  core0 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 dram0 region1 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
- *  core0 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 dram0 region1 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
- *  core0 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 PIF region0 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
- *  core0 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 PIF region0 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
- *  core0 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 PIF region1 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
- *  core0 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 PIF region1 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
- *  core0 area pc status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
-/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
- *  the stackpointer when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
- *  core0 area sp status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
-/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
- *  the PC when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
- *  stack min value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
-/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
- *  stack max value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
-/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
- *  core0 sp pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
- *  stack monitor pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
-/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
- *  record enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
-/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable record PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
- *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
- *  recorded PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
- *  recorded sp
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
-
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_iram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_iram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
- *  reg_core_0_iram0_recording_loadstore_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
-
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_iram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_iram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
- *  reg_core_0_iram0_recording_loadstore_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register2
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_dram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_dram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  24
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
- *  reg_core_0_dram0_recording_byteen_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register3
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_0_dram0_recording_pc_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
- *  exception monitor status register4
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_dram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_dram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  24
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
- *  reg_core_0_dram0_recording_byteen_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
- *  exception monitor status register5
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_0_dram0_recording_pc_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
-
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register6
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
- *  reg_core_x_iram0_dram0_limit_cycle_0
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
-
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register7
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
- *  reg_core_x_iram0_dram0_limit_cycle_1
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
-
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
- *  cpu's lastpc before exception
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
-
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
- *  cpu debug mode status, 1 means cpu enter debug mode.
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
- *  cpu debug_module active status
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
-
-/** ASSIST_DEBUG_CLOCK_GATE_REG register
- *  clock register
- */
-#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
-/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 force on the clock gate
- */
-#define ASSIST_DEBUG_CLK_EN    (BIT(0))
-#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
-#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
-#define ASSIST_DEBUG_CLK_EN_S  0
-
-/** ASSIST_DEBUG_DATE_REG register
- *  version register
- */
-#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
-/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
- *  version register
- */
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/assist_debug_struct.h b/components/soc/esp32c6/include/soc/assist_debug_struct.h
deleted file mode 100644
index 24c28c33efa..00000000000
--- a/components/soc/esp32c6/include/soc/assist_debug_struct.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: monitor configuration registers */
-/** Type of core_0_intr_ena register
- *  core0 monitor enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor enable
-         */
-        uint32_t core_0_area_dram0_0_rd_ena:1;
-        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor enable
-         */
-        uint32_t core_0_area_dram0_0_wr_ena:1;
-        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor enable
-         */
-        uint32_t core_0_area_dram0_1_rd_ena:1;
-        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor enable
-         */
-        uint32_t core_0_area_dram0_1_wr_ena:1;
-        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor enable
-         */
-        uint32_t core_0_area_pif_0_rd_ena:1;
-        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor enable
-         */
-        uint32_t core_0_area_pif_0_wr_ena:1;
-        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor enable
-         */
-        uint32_t core_0_area_pif_1_rd_ena:1;
-        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor enable
-         */
-        uint32_t core_0_area_pif_1_wr_ena:1;
-        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor enable
-         */
-        uint32_t core_0_sp_spill_min_ena:1;
-        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor enable
-         */
-        uint32_t core_0_sp_spill_max_ena:1;
-        /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
-         *  IBUS busy monitor enable
-         */
-        uint32_t core_0_iram0_exception_monitor_ena:1;
-        /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor enbale
-         */
-        uint32_t core_0_dram0_exception_monitor_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_ena_reg_t;
-
-/** Type of core_0_area_dram0_0_min register
- *  core0 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 dram0 region0 start addr
-         */
-        uint32_t core_0_area_dram0_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_min_reg_t;
-
-/** Type of core_0_area_dram0_0_max register
- *  core0 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 dram0 region0 end addr
-         */
-        uint32_t core_0_area_dram0_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_max_reg_t;
-
-/** Type of core_0_area_dram0_1_min register
- *  core0 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 dram0 region1 start addr
-         */
-        uint32_t core_0_area_dram0_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_min_reg_t;
-
-/** Type of core_0_area_dram0_1_max register
- *  core0 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 dram0 region1 end addr
-         */
-        uint32_t core_0_area_dram0_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_max_reg_t;
-
-/** Type of core_0_area_pif_0_min register
- *  core0 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 PIF region0 start addr
-         */
-        uint32_t core_0_area_pif_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_min_reg_t;
-
-/** Type of core_0_area_pif_0_max register
- *  core0 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 PIF region0 end addr
-         */
-        uint32_t core_0_area_pif_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_max_reg_t;
-
-/** Type of core_0_area_pif_1_min register
- *  core0 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 PIF region1 start addr
-         */
-        uint32_t core_0_area_pif_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_min_reg_t;
-
-/** Type of core_0_area_pif_1_max register
- *  core0 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 PIF region1 end addr
-         */
-        uint32_t core_0_area_pif_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_max_reg_t;
-
-/** Type of core_0_area_pc register
- *  core0 area pc status register
- */
-typedef union {
-    struct {
-        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
-         *  the stackpointer when first touch region monitor interrupt
-         */
-        uint32_t core_0_area_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pc_reg_t;
-
-/** Type of core_0_area_sp register
- *  core0 area sp status register
- */
-typedef union {
-    struct {
-        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
-         *  the PC when first touch region monitor interrupt
-         */
-        uint32_t core_0_area_sp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_sp_reg_t;
-
-/** Type of core_0_sp_min register
- *  stack min value
- */
-typedef union {
-    struct {
-        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core0 sp region configuration regsiter
-         */
-        uint32_t core_0_sp_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_min_reg_t;
-
-/** Type of core_0_sp_max register
- *  stack max value
- */
-typedef union {
-    struct {
-        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
-         *  core0 sp pc status register
-         */
-        uint32_t core_0_sp_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_max_reg_t;
-
-/** Type of core_0_sp_pc register
- *  stack monitor pc status register
- */
-typedef union {
-    struct {
-        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
-         */
-        uint32_t core_0_sp_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_pc_reg_t;
-
-
-/** Group: interrupt configuration register */
-/** Type of core_0_intr_raw register
- *  core0 monitor interrupt status register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_0_rd_raw:1;
-        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_0_wr_raw:1;
-        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_1_rd_raw:1;
-        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_1_wr_raw:1;
-        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt status
-         */
-        uint32_t core_0_area_pif_0_rd_raw:1;
-        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt status
-         */
-        uint32_t core_0_area_pif_0_wr_raw:1;
-        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt status
-         */
-        uint32_t core_0_area_pif_1_rd_raw:1;
-        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt status
-         */
-        uint32_t core_0_area_pif_1_wr_raw:1;
-        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt status
-         */
-        uint32_t core_0_sp_spill_min_raw:1;
-        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt status
-         */
-        uint32_t core_0_sp_spill_max_raw:1;
-        /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt status
-         */
-        uint32_t core_0_iram0_exception_monitor_raw:1;
-        /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
-         *  DBUS busy monitor initerrupt status
-         */
-        uint32_t core_0_dram0_exception_monitor_raw:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_raw_reg_t;
-
-/** Type of core_0_intr_rls register
- *  core0 monitor interrupt enable register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_rd_rls:1;
-        /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_wr_rls:1;
-        /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_rd_rls:1;
-        /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_wr_rls:1;
-        /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_rd_rls:1;
-        /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_wr_rls:1;
-        /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_rd_rls:1;
-        /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_wr_rls:1;
-        /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_min_rls:1;
-        /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_max_rls:1;
-        /** core_0_iram0_exception_monitor_rls : R/W; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt enable
-         */
-        uint32_t core_0_iram0_exception_monitor_rls:1;
-        /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt enbale
-         */
-        uint32_t core_0_dram0_exception_monitor_rls:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_rls_reg_t;
-
-/** Type of core_0_intr_clr register
- *  core0 monitor interrupt clr register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_0_rd_clr:1;
-        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_0_wr_clr:1;
-        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_1_rd_clr:1;
-        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_1_wr_clr:1;
-        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_0_rd_clr:1;
-        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_0_wr_clr:1;
-        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_1_rd_clr:1;
-        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_1_wr_clr:1;
-        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt clr
-         */
-        uint32_t core_0_sp_spill_min_clr:1;
-        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt clr
-         */
-        uint32_t core_0_sp_spill_max_clr:1;
-        /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt clr
-         */
-        uint32_t core_0_iram0_exception_monitor_clr:1;
-        /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt clr
-         */
-        uint32_t core_0_dram0_exception_monitor_clr:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_clr_reg_t;
-
-
-/** Group: pc reording configuration register */
-/** Type of core_0_rcd_en register
- *  record enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable record PC
-         */
-        uint32_t core_0_rcd_recorden:1;
-        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
-         */
-        uint32_t core_0_rcd_pdebugen:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_en_reg_t;
-
-
-/** Group: pc reording status register */
-/** Type of core_0_rcd_pdebugpc register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
-         *  recorded PC
-         */
-        uint32_t core_0_rcd_pdebugpc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugpc_reg_t;
-
-/** Type of core_0_rcd_pdebugsp register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
-         *  recorded sp
-         */
-        uint32_t core_0_rcd_pdebugsp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugsp_reg_t;
-
-
-/** Group: exception monitor regsiter */
-/** Type of core_0_iram0_exception_monitor_0 register
- *  exception monitor status register0
- */
-typedef union {
-    struct {
-        /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_iram0_recording_addr_0
-         */
-        uint32_t core_0_iram0_recording_addr_0:24;
-        /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_iram0_recording_wr_0
-         */
-        uint32_t core_0_iram0_recording_wr_0:1;
-        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
-         *  reg_core_0_iram0_recording_loadstore_0
-         */
-        uint32_t core_0_iram0_recording_loadstore_0:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
-
-/** Type of core_0_iram0_exception_monitor_1 register
- *  exception monitor status register1
- */
-typedef union {
-    struct {
-        /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_iram0_recording_addr_1
-         */
-        uint32_t core_0_iram0_recording_addr_1:24;
-        /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_iram0_recording_wr_1
-         */
-        uint32_t core_0_iram0_recording_wr_1:1;
-        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
-         *  reg_core_0_iram0_recording_loadstore_1
-         */
-        uint32_t core_0_iram0_recording_loadstore_1:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_0 register
- *  exception monitor status register2
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_dram0_recording_addr_0
-         */
-        uint32_t core_0_dram0_recording_addr_0:24;
-        /** core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_dram0_recording_wr_0
-         */
-        uint32_t core_0_dram0_recording_wr_0:1;
-        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0;
-         *  reg_core_0_dram0_recording_byteen_0
-         */
-        uint32_t core_0_dram0_recording_byteen_0:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_1 register
- *  exception monitor status register3
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_0_dram0_recording_pc_0
-         */
-        uint32_t core_0_dram0_recording_pc_0:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_2 register
- *  exception monitor status register4
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_dram0_recording_addr_1
-         */
-        uint32_t core_0_dram0_recording_addr_1:24;
-        /** core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_dram0_recording_wr_1
-         */
-        uint32_t core_0_dram0_recording_wr_1:1;
-        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0;
-         *  reg_core_0_dram0_recording_byteen_1
-         */
-        uint32_t core_0_dram0_recording_byteen_1:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_3 register
- *  exception monitor status register5
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_0_dram0_recording_pc_1
-         */
-        uint32_t core_0_dram0_recording_pc_1:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
-
-/** Type of core_x_iram0_dram0_exception_monitor_0 register
- *  exception monitor status register6
- */
-typedef union {
-    struct {
-        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
-         *  reg_core_x_iram0_dram0_limit_cycle_0
-         */
-        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_x_iram0_dram0_exception_monitor_1 register
- *  exception monitor status register7
- */
-typedef union {
-    struct {
-        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
-         *  reg_core_x_iram0_dram0_limit_cycle_1
-         */
-        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
-
-
-/** Group: cpu status registers */
-/** Type of core_0_lastpc_before_exception register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
-         *  cpu's lastpc before exception
-         */
-        uint32_t core_0_lastpc_before_exc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_lastpc_before_exception_reg_t;
-
-/** Type of core_0_debug_mode register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
-         *  cpu debug mode status, 1 means cpu enter debug mode.
-         */
-        uint32_t core_0_debug_mode:1;
-        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
-         *  cpu debug_module active status
-         */
-        uint32_t core_0_debug_module_active:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_debug_mode_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of clock_gate register
- *  clock register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 force on the clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} assist_debug_clock_gate_reg_t;
-
-/** Type of date register
- *  version register
- */
-typedef union {
-    struct {
-        /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
-         *  version register
-         */
-        uint32_t assist_debug_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} assist_debug_date_reg_t;
-
-
-typedef struct assist_debug_dev_t {
-    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
-    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
-    volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
-    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
-    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
-    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
-    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
-    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
-    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
-    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
-    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
-    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
-    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
-    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
-    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
-    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
-    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
-    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
-    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
-    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
-    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
-    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
-    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
-    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
-    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
-    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
-    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
-    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
-    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
-    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
-    volatile assist_debug_clock_gate_reg_t clock_gate;
-    uint32_t reserved_07c[224];
-    volatile assist_debug_date_reg_t date;
-} assist_debug_dev_t;
-
-extern assist_debug_dev_t ASSIST_DEBUG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/clk_tree_defs.h b/components/soc/esp32c6/include/soc/clk_tree_defs.h
index dba6e79df46..599ccba6643 100644
--- a/components/soc/esp32c6/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c6/include/soc/clk_tree_defs.h
@@ -96,8 +96,11 @@ typedef enum {
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1,      /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
 } soc_rtc_fast_clk_src_t;
 
 /**
diff --git a/components/soc/esp32c6/include/soc/dport_access.h b/components/soc/esp32c6/include/soc/dport_access.h
index 000b58c36a1..54eb8a0a352 100644
--- a/components/soc/esp32c6/include/soc/dport_access.h
+++ b/components/soc/esp32c6/include/soc/dport_access.h
@@ -9,7 +9,6 @@
 
 #include <stdint.h>
 #include "soc.h"
-#include "uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32c6/include/soc/ecc_mult_reg.h b/components/soc/esp32c6/include/soc/ecc_mult_reg.h
deleted file mode 100644
index dca2cc1206a..00000000000
--- a/components/soc/esp32c6/include/soc/ecc_mult_reg.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ECC_MULT_INT_RAW_REG register
- *  ECC interrupt raw register, valid in level.
- */
-#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
-/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
-#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_RAW_S  0
-
-/** ECC_MULT_INT_ST_REG register
- *  ECC interrupt status register.
- */
-#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
-/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
-#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_ST_S  0
-
-/** ECC_MULT_INT_ENA_REG register
- *  ECC interrupt enable register.
- */
-#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
-/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
-#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_ENA_S  0
-
-/** ECC_MULT_INT_CLR_REG register
- *  ECC interrupt clear register.
- */
-#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
-/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
-#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_CLR_S  0
-
-/** ECC_MULT_CONF_REG register
- *  ECC configure register
- */
-#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
-/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
- *  the caculatrion is done.
- */
-#define ECC_MULT_START    (BIT(0))
-#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
-#define ECC_MULT_START_V  0x00000001U
-#define ECC_MULT_START_S  0
-/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
- *  Write 1 to reset ECC Accelerator.
- */
-#define ECC_MULT_RESET    (BIT(1))
-#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
-#define ECC_MULT_RESET_V  0x00000001U
-#define ECC_MULT_RESET_S  1
-/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
- *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
- */
-#define ECC_MULT_KEY_LENGTH    (BIT(2))
-#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
-#define ECC_MULT_KEY_LENGTH_V  0x00000001U
-#define ECC_MULT_KEY_LENGTH_S  2
-/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define ECC_MULT_SECURITY_MODE    (BIT(3))
-#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
-#define ECC_MULT_SECURITY_MODE_V  0x00000001U
-#define ECC_MULT_SECURITY_MODE_S  3
-/** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0;
- *  Write 1 to force on register clock gate.
- */
-#define ECC_MULT_CLK_EN    (BIT(4))
-#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
-#define ECC_MULT_CLK_EN_V  0x00000001U
-#define ECC_MULT_CLK_EN_S  4
-/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:5]; default: 0;
- *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2:
- *  Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5:
- *  Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
- */
-#define ECC_MULT_WORK_MODE    0x00000007U
-#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
-#define ECC_MULT_WORK_MODE_V  0x00000007U
-#define ECC_MULT_WORK_MODE_S  5
-/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [8]; default: 0;
- *  The verification result bit of ECC Accelerator, only valid when calculation is done.
- */
-#define ECC_MULT_VERIFICATION_RESULT    (BIT(8))
-#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
-#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
-#define ECC_MULT_VERIFICATION_RESULT_S  8
-/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 1;
- *  ECC memory clock gate force on register
- */
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
-
-/** ECC_MULT_DATE_REG register
- *  Version control register
- */
-#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
-/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 35656256;
- *  ECC mult version control register
- */
-#define ECC_MULT_DATE    0x0FFFFFFFU
-#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
-#define ECC_MULT_DATE_V  0x0FFFFFFFU
-#define ECC_MULT_DATE_S  0
-
-/** ECC_MULT_K_MEM register
- *  The memory that stores k.
- */
-#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
-#define ECC_MULT_K_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_PX_MEM register
- *  The memory that stores Px.
- */
-#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
-#define ECC_MULT_PX_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_PY_MEM register
- *  The memory that stores Py.
- */
-#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
-#define ECC_MULT_PY_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/ecc_mult_struct.h b/components/soc/esp32c6/include/soc/ecc_mult_struct.h
deleted file mode 100644
index c120fb068de..00000000000
--- a/components/soc/esp32c6/include/soc/ecc_mult_struct.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Memory data */
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  ECC interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_raw:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_raw_reg_t;
-
-/** Type of int_st register
- *  ECC interrupt status register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_st:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_st_reg_t;
-
-/** Type of int_ena register
- *  ECC interrupt enable register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_ena:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_ena_reg_t;
-
-/** Type of int_clr register
- *  ECC interrupt clear register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of conf register
- *  ECC configure register
- */
-typedef union {
-    struct {
-        /** start : R/W/SC; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
-         *  the caculatrion is done.
-         */
-        uint32_t start:1;
-        /** reset : WT; bitpos: [1]; default: 0;
-         *  Write 1 to reset ECC Accelerator.
-         */
-        uint32_t reset:1;
-        /** key_length : R/W; bitpos: [2]; default: 0;
-         *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
-         */
-        uint32_t key_length:1;
-        /** security_mode : R/W; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t security_mode:1;
-        /** clk_en : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_en:1;
-        /** work_mode : R/W; bitpos: [7:5]; default: 0;
-         *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2:
-         *  Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5:
-         *  Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
-         */
-        uint32_t work_mode:3;
-        /** verification_result : RO/SS; bitpos: [8]; default: 0;
-         *  The verification result bit of ECC Accelerator, only valid when calculation is done.
-         */
-        uint32_t verification_result:1;
-        uint32_t reserved_9:22;
-        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 1;
-         *  ECC memory clock gate force on register
-         */
-        uint32_t mem_clock_gate_force_on:1;
-    };
-    uint32_t val;
-} ecc_mult_conf_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35656256;
-         *  ECC mult version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ecc_mult_date_reg_t;
-
-
-typedef struct ecc_mult_dev_t {
-    uint32_t reserved_000[3];
-    volatile ecc_mult_int_raw_reg_t int_raw;
-    volatile ecc_mult_int_st_reg_t int_st;
-    volatile ecc_mult_int_ena_reg_t int_ena;
-    volatile ecc_mult_int_clr_reg_t int_clr;
-    volatile ecc_mult_conf_reg_t conf;
-    uint32_t reserved_020[55];
-    volatile ecc_mult_date_reg_t date;
-    volatile uint32_t k[8];
-    volatile uint32_t px[8];
-    volatile uint32_t py[8];
-} ecc_mult_dev_t;
-
-extern ecc_mult_dev_t ECC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/efuse_reg.h b/components/soc/esp32c6/include/soc/efuse_reg.h
deleted file mode 100644
index 882041ac413..00000000000
--- a/components/soc/esp32c6/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,2727 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#include "efuse_defs.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 3rd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS_REG register
- *  BLOCK0 data register 0.
- */
-#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Represents whether programming of individual eFuse memory bit is disabled or
- *  enabled. 1: Disabled. 0 Enabled.
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  BLOCK0 data register 1.
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_SWAP_UART_SDIO_EN : RO; bitpos: [7]; default: 0;
- *  Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not
- *  swapped.
- */
-#define EFUSE_SWAP_UART_SDIO_EN    (BIT(7))
-#define EFUSE_SWAP_UART_SDIO_EN_M  (EFUSE_SWAP_UART_SDIO_EN_V << EFUSE_SWAP_UART_SDIO_EN_S)
-#define EFUSE_SWAP_UART_SDIO_EN_V  0x00000001U
-#define EFUSE_SWAP_UART_SDIO_EN_S  7
-/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
- *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_ICACHE    (BIT(8))
-#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
-#define EFUSE_DIS_ICACHE_V  0x00000001U
-#define EFUSE_DIS_ICACHE_S  8
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
- *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  9
-/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0;
- *  Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0:
- *  enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(10))
-#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
-#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
- *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Represents whether the function that forces chip into download mode is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
- *  Represents whether SPI0 controller during boot_mode_download is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
-/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
-#define EFUSE_DIS_TWAI_V  0x00000001U
-#define EFUSE_DIS_TWAI_S  14
-/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- *  is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
-#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_S  15
-/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
- *  enabled.
- */
-#define EFUSE_SOFT_DIS_JTAG    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
-#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
- *  enabled.
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
- *  mode). 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFH    0x00000003U
-#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
-#define EFUSE_USB_DREFH_V  0x00000003U
-#define EFUSE_USB_DREFH_S  21
-/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFL    0x00000003U
-#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
-#define EFUSE_USB_DREFL_V  0x00000003U
-#define EFUSE_USB_DREFL_S  23
-/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
- *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.
- */
-#define EFUSE_USB_EXCHG_PINS    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
-#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_S  25
-/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
- *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
- *  functioned.
- */
-#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
-#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_S  26
-/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_2    0x00000003U
-#define EFUSE_RPT4_RESERVED0_2_M  (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S)
-#define EFUSE_RPT4_RESERVED0_2_V  0x00000003U
-#define EFUSE_RPT4_RESERVED0_2_S  27
-/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_1    (BIT(29))
-#define EFUSE_RPT4_RESERVED0_1_M  (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S)
-#define EFUSE_RPT4_RESERVED0_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED0_1_S  29
-/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_0    0x00000003U
-#define EFUSE_RPT4_RESERVED0_0_M  (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S)
-#define EFUSE_RPT4_RESERVED0_0_V  0x00000003U
-#define EFUSE_RPT4_RESERVED0_0_S  30
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  BLOCK0 data register 2.
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_RPT4_RESERVED1_0 : RO; bitpos: [15:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED1_0    0x0000FFFFU
-#define EFUSE_RPT4_RESERVED1_0_M  (EFUSE_RPT4_RESERVED1_0_V << EFUSE_RPT4_RESERVED1_0_S)
-#define EFUSE_RPT4_RESERVED1_0_V  0x0000FFFFU
-#define EFUSE_RPT4_RESERVED1_0_S  0
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
- *  selected. 0: not selected.
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
- *  1: enabled. Even number of 1: disabled.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking first secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Represents whether revoking second secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Represents whether revoking third secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Represents the purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  24
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Represents the purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  BLOCK0 data register 3.
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Represents the purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  0
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Represents the purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  4
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Represents the purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  8
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Represents the purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  12
-/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the spa secure level by configuring the clock random divide mode.
- */
-#define EFUSE_SEC_DPA_LEVEL    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
-#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_S  16
-/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [18]; default: 0;
- *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
- */
-#define EFUSE_CRYPT_DPA_ENABLE    (BIT(18))
-#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
-#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_S  18
-/** EFUSE_RPT4_RESERVED2_1 : RO; bitpos: [19]; default: 1;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED2_1    (BIT(19))
-#define EFUSE_RPT4_RESERVED2_1_M  (EFUSE_RPT4_RESERVED2_1_V << EFUSE_RPT4_RESERVED2_1_S)
-#define EFUSE_RPT4_RESERVED2_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED2_1_S  19
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED2_0    0x0000003FU
-#define EFUSE_RPT4_RESERVED2_0_M  (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S)
-#define EFUSE_RPT4_RESERVED2_0_V  0x0000003FU
-#define EFUSE_RPT4_RESERVED2_0_S  22
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Represents the flash waiting time after power-up, in unit of ms. When the value
- *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
- *  is 2 times the programmed value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  BLOCK0 data register 4.
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
- *  0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_5    (BIT(3))
-#define EFUSE_RPT4_RESERVED3_5_M  (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S)
-#define EFUSE_RPT4_RESERVED3_5_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_5_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Represents whether security download is enabled or disabled. 1: enabled. 0:
- *  disabled.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Represents the type of UART printing. 00: force enable printing. 01: enable
- *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
- *  at high level. 11: force disable printing.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/** EFUSE_RPT4_RESERVED3_4 : RO; bitpos: [8]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_4    (BIT(8))
-#define EFUSE_RPT4_RESERVED3_4_M  (EFUSE_RPT4_RESERVED3_4_V << EFUSE_RPT4_RESERVED3_4_S)
-#define EFUSE_RPT4_RESERVED3_4_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_4_S  8
-/** EFUSE_RPT4_RESERVED3_3 : RO; bitpos: [9]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_3    (BIT(9))
-#define EFUSE_RPT4_RESERVED3_3_M  (EFUSE_RPT4_RESERVED3_3_V << EFUSE_RPT4_RESERVED3_3_S)
-#define EFUSE_RPT4_RESERVED3_3_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_3_S  9
-/** EFUSE_RPT4_RESERVED3_2 : RO; bitpos: [11:10]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_2    0x00000003U
-#define EFUSE_RPT4_RESERVED3_2_M  (EFUSE_RPT4_RESERVED3_2_V << EFUSE_RPT4_RESERVED3_2_S)
-#define EFUSE_RPT4_RESERVED3_2_V  0x00000003U
-#define EFUSE_RPT4_RESERVED3_2_S  10
-/** EFUSE_RPT4_RESERVED3_1 : RO; bitpos: [12]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_1    (BIT(12))
-#define EFUSE_RPT4_RESERVED3_1_M  (EFUSE_RPT4_RESERVED3_1_V << EFUSE_RPT4_RESERVED3_1_S)
-#define EFUSE_RPT4_RESERVED3_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_1_S  12
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
- *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
- *  forced. 0:not forced.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  13
-/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0;
- *  Represents the version used by ESP-IDF anti-rollback feature.
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  14
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [30]; default: 0;
- *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(30))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  30
-/** EFUSE_RPT4_RESERVED3_0 : RO; bitpos: [31]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_0    (BIT(31))
-#define EFUSE_RPT4_RESERVED3_0_M  (EFUSE_RPT4_RESERVED3_0_V << EFUSE_RPT4_RESERVED3_0_S)
-#define EFUSE_RPT4_RESERVED3_0_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_0_S  31
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  BLOCK0 data register 5.
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0;
- *  Disables check of wafer version major
- */
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(0))
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  0
-/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0;
- *  Disables check of blk version major
- */
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(1))
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  1
-/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_0_162    0x003FFFFFU
-#define EFUSE_RESERVED_0_162_M  (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S)
-#define EFUSE_RESERVED_0_162_V  0x003FFFFFU
-#define EFUSE_RESERVED_0_162_S  2
-/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED4_0    0x000000FFU
-#define EFUSE_RPT4_RESERVED4_0_M  (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S)
-#define EFUSE_RPT4_RESERVED4_0_V  0x000000FFU
-#define EFUSE_RPT4_RESERVED4_0_S  24
-
-/** EFUSE_RD_MAC_SPI_SYS_0_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the low 32 bits of MAC address.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SPI_SYS_1_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Stores the high 16 bits of MAC address.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
- *  Stores the extended bits of MAC address.
- */
-#define EFUSE_MAC_EXT    0x0000FFFFU
-#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
-#define EFUSE_MAC_EXT_V  0x0000FFFFU
-#define EFUSE_MAC_EXT_S  16
-
-/** EFUSE_RD_MAC_SPI_SYS_2_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
-/** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [4:0]; default: 0;
- *  Stores the active hp dbias.
- */
-#define EFUSE_ACTIVE_HP_DBIAS    0x0000001FU
-#define EFUSE_ACTIVE_HP_DBIAS_M  (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
-#define EFUSE_ACTIVE_HP_DBIAS_V  0x0000001FU
-#define EFUSE_ACTIVE_HP_DBIAS_S  0
-/** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [9:5]; default: 0;
- *  Stores the active lp dbias.
- */
-#define EFUSE_ACTIVE_LP_DBIAS    0x0000001FU
-#define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
-#define EFUSE_ACTIVE_LP_DBIAS_V  0x0000001FU
-#define EFUSE_ACTIVE_LP_DBIAS_S  5
-/** EFUSE_LSLP_HP_DBG : RO; bitpos: [11:10]; default: 0;
- *  Stores the lslp hp dbg.
- */
-#define EFUSE_LSLP_HP_DBG    0x00000003U
-#define EFUSE_LSLP_HP_DBG_M  (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S)
-#define EFUSE_LSLP_HP_DBG_V  0x00000003U
-#define EFUSE_LSLP_HP_DBG_S  10
-/** EFUSE_LSLP_HP_DBIAS : RO; bitpos: [15:12]; default: 0;
- *  Stores the lslp hp dbias.
- */
-#define EFUSE_LSLP_HP_DBIAS    0x0000000FU
-#define EFUSE_LSLP_HP_DBIAS_M  (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
-#define EFUSE_LSLP_HP_DBIAS_V  0x0000000FU
-#define EFUSE_LSLP_HP_DBIAS_S  12
-/** EFUSE_DSLP_LP_DBG : RO; bitpos: [18:16]; default: 0;
- *  Stores the dslp lp dbg.
- */
-#define EFUSE_DSLP_LP_DBG    0x00000007U
-#define EFUSE_DSLP_LP_DBG_M  (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S)
-#define EFUSE_DSLP_LP_DBG_V  0x00000007U
-#define EFUSE_DSLP_LP_DBG_S  16
-/** EFUSE_DSLP_LP_DBIAS : RO; bitpos: [22:19]; default: 0;
- *  Stores the dslp lp dbias.
- */
-#define EFUSE_DSLP_LP_DBIAS    0x0000000FU
-#define EFUSE_DSLP_LP_DBIAS_M  (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
-#define EFUSE_DSLP_LP_DBIAS_V  0x0000000FU
-#define EFUSE_DSLP_LP_DBIAS_S  19
-/** EFUSE_DBIAS_VOL_GAP : RO; bitpos: [27:23]; default: 0;
- *  Stores the hp and lp dbias vol gap.
- */
-#define EFUSE_DBIAS_VOL_GAP    0x0000001FU
-#define EFUSE_DBIAS_VOL_GAP_M  (EFUSE_DBIAS_VOL_GAP_V << EFUSE_DBIAS_VOL_GAP_S)
-#define EFUSE_DBIAS_VOL_GAP_V  0x0000001FU
-#define EFUSE_DBIAS_VOL_GAP_S  23
-/** EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:28]; default: 0;
- *  Stores the first part of SPI_PAD_CONF.
- */
-#define EFUSE_SPI_PAD_CONF_1    0x0000000FU
-#define EFUSE_SPI_PAD_CONF_1_M  (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S)
-#define EFUSE_SPI_PAD_CONF_1_V  0x0000000FU
-#define EFUSE_SPI_PAD_CONF_1_S  28
-
-/** EFUSE_RD_MAC_SPI_SYS_3_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0;
- *  Stores the second part of SPI_PAD_CONF.
- */
-#define EFUSE_SPI_PAD_CONF_2    0x0003FFFFU
-#define EFUSE_SPI_PAD_CONF_2_M  (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S)
-#define EFUSE_SPI_PAD_CONF_2_V  0x0003FFFFU
-#define EFUSE_SPI_PAD_CONF_2_S  0
-/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [21:18]; default: 0; */
-#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
-#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_S  18
-/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [23:22]; default: 0; */
-#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_S  22
-/** EFUSE_PKG_VERSION : R; bitpos: [26:24]; default: 0;
- *  Package version
- */
-#define EFUSE_PKG_VERSION    0x00000007U
-#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
-#define EFUSE_PKG_VERSION_V  0x00000007U
-#define EFUSE_PKG_VERSION_S  24
-/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [29:27]; default: 0;
- *  BLK_VERSION_MINOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MINOR    0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
-#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_S  27
-/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [31:30]; default: 0;
- *  BLK_VERSION_MAJOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
-#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_S  30
-
-/** EFUSE_RD_MAC_SPI_SYS_4_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_FLASH_CAP : R; bitpos: [2:0]; default: 0; */
-#define EFUSE_FLASH_CAP    0x00000007U
-#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
-#define EFUSE_FLASH_CAP_V  0x00000007U
-#define EFUSE_FLASH_CAP_S  0
-/** EFUSE_FLASH_TEMP : R; bitpos: [4:3]; default: 0; */
-#define EFUSE_FLASH_TEMP    0x00000003U
-#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
-#define EFUSE_FLASH_TEMP_V  0x00000003U
-#define EFUSE_FLASH_TEMP_S  3
-/** EFUSE_FLASH_VENDOR : R; bitpos: [7:5]; default: 0; */
-#define EFUSE_FLASH_VENDOR    0x00000007U
-#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
-#define EFUSE_FLASH_VENDOR_V  0x00000007U
-#define EFUSE_FLASH_VENDOR_S  5
-/** EFUSE_RESERVED_1_136 : R; bitpos: [31:8]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_136    0x00FFFFFFU
-#define EFUSE_RESERVED_1_136_M  (EFUSE_RESERVED_1_136_V << EFUSE_RESERVED_1_136_S)
-#define EFUSE_RESERVED_1_136_V  0x00FFFFFFU
-#define EFUSE_RESERVED_1_136_S  8
-
-/** EFUSE_RD_MAC_SPI_SYS_5_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
-#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_TEMP_CALIB : R; bitpos: [8:0]; default: 0;
- *  Temperature calibration data
- */
-#define EFUSE_TEMP_CALIB    0x000001FFU
-#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
-#define EFUSE_TEMP_CALIB_V  0x000001FFU
-#define EFUSE_TEMP_CALIB_S  0
-/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
- *  ADC OCode
- */
-#define EFUSE_OCODE    0x000000FFU
-#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
-#define EFUSE_OCODE_V  0x000000FFU
-#define EFUSE_OCODE_S  9
-/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
- *  ADC1 init code at atten0
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0    0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_V  0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_S  17
-/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
- *  ADC1 init code at atten1
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN1    0x0000001FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_V  0x0000001FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_S  27
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
- *  ADC1 init code at atten1
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1    0x0000001FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V  0x0000001FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S  0
-/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
- *  ADC1 init code at atten2
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN2    0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_M  (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_V  0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_S  5
-/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
- *  ADC1 init code at atten3
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN3    0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_V  0x000003FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_S  15
-/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:25]; default: 0;
- *  ADC1 calibration voltage at atten0
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN0    0x0000007FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_V  0x0000007FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_S  25
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
- *  ADC1 calibration voltage at atten0
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1    0x00000007U
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V  0x00000007U
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S  0
-/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [12:3]; default: 0;
- *  ADC1 calibration voltage at atten1
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN1    0x000003FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_M  (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_V  0x000003FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_S  3
-/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [22:13]; default: 0;
- *  ADC1 calibration voltage at atten2
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN2    0x000003FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_M  (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_V  0x000003FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_S  13
-/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [31:23]; default: 0;
- *  ADC1 calibration voltage at atten3
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN3    0x000001FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_V  0x000001FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_S  23
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_ADC1_CAL_VOL_ATTEN3_1 : R; bitpos: [0]; default: 0;
- *  ADC1 calibration voltage at atten3
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_1    (BIT(0))
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_1_V << EFUSE_ADC1_CAL_VOL_ATTEN3_1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_V  0x00000001U
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_S  0
-/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH0 : R; bitpos: [4:1]; default: 0;
- *  ADC1 init code at atten0 ch0
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0    0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_V  0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_S  1
-/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH1 : R; bitpos: [8:5]; default: 0;
- *  ADC1 init code at atten0 ch1
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1    0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_V  0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_S  5
-/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH2 : R; bitpos: [12:9]; default: 0;
- *  ADC1 init code at atten0 ch2
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2    0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_V  0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_S  9
-/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH3 : R; bitpos: [16:13]; default: 0;
- *  ADC1 init code at atten0 ch3
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3    0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_V  0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_S  13
-/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH4 : R; bitpos: [20:17]; default: 0;
- *  ADC1 init code at atten0 ch4
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4    0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_V  0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_S  17
-/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH5 : R; bitpos: [24:21]; default: 0;
- *  ADC1 init code at atten0 ch5
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5    0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_V  0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_S  21
-/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH6 : R; bitpos: [28:25]; default: 0;
- *  ADC1 init code at atten0 ch6
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6    0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_V  0x0000000FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_S  25
-/** EFUSE_RESERVED_2_253 : R; bitpos: [31:29]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_253    0x00000007U
-#define EFUSE_RESERVED_2_253_M  (EFUSE_RESERVED_2_253_V << EFUSE_RESERVED_2_253_S)
-#define EFUSE_RESERVED_2_253_V  0x00000007U
-#define EFUSE_RESERVED_2_253_S  29
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_192    0x000000FFU
-#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
-#define EFUSE_RESERVED_3_192_V  0x000000FFU
-#define EFUSE_RESERVED_3_192_S  0
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_S  8
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_248    0x000000FFU
-#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
-#define EFUSE_RESERVED_3_248_V  0x000000FFU
-#define EFUSE_RESERVED_3_248_S  24
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_ERR0_REG register
- *  Programming error record register 0 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  Indicates a programming error of RD_DIS.
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_SWAP_UART_SDIO_EN_ERR : RO; bitpos: [7]; default: 0;
- *  Indicates a programming error of SWAP_UART_SDIO_EN.
- */
-#define EFUSE_SWAP_UART_SDIO_EN_ERR    (BIT(7))
-#define EFUSE_SWAP_UART_SDIO_EN_ERR_M  (EFUSE_SWAP_UART_SDIO_EN_ERR_V << EFUSE_SWAP_UART_SDIO_EN_ERR_S)
-#define EFUSE_SWAP_UART_SDIO_EN_ERR_V  0x00000001U
-#define EFUSE_SWAP_UART_SDIO_EN_ERR_S  7
-/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of DIS_ICACHE.
- */
-#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
-#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
-#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_ICACHE_ERR_S  8
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  Indicates a programming error of DIS_USB_JTAG.
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  9
-/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_ICACHE.
- */
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(10))
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
- *  Indicates a programming error of DIS_USB_DEVICE.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
-/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
- *  Indicates a programming error of DIS_CAN.
- */
-#define EFUSE_DIS_TWAI_ERR    (BIT(14))
-#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
-#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
-#define EFUSE_DIS_TWAI_ERR_S  14
-/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
- *  Indicates a programming error of JTAG_SEL_ENABLE.
- */
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
-/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  Indicates a programming error of SOFT_DIS_JTAG.
- */
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of DIS_PAD_JTAG.
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
- *  Indicates a programming error of USB_DREFH.
- */
-#define EFUSE_USB_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
-#define EFUSE_USB_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DREFH_ERR_S  21
-/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
- *  Indicates a programming error of USB_DREFL.
- */
-#define EFUSE_USB_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
-#define EFUSE_USB_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DREFL_ERR_S  23
-/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of USB_EXCHG_PINS.
- */
-#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
-#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_ERR_S  25
-/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
- *  Indicates a programming error of VDD_SPI_AS_GPIO.
- */
-#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
-/** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_ERR_2    0x00000003U
-#define EFUSE_RPT4_RESERVED0_ERR_2_M  (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S)
-#define EFUSE_RPT4_RESERVED0_ERR_2_V  0x00000003U
-#define EFUSE_RPT4_RESERVED0_ERR_2_S  27
-/** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_ERR_1    (BIT(29))
-#define EFUSE_RPT4_RESERVED0_ERR_1_M  (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S)
-#define EFUSE_RPT4_RESERVED0_ERR_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED0_ERR_1_S  29
-/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_ERR_0    0x00000003U
-#define EFUSE_RPT4_RESERVED0_ERR_0_M  (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S)
-#define EFUSE_RPT4_RESERVED0_ERR_0_V  0x00000003U
-#define EFUSE_RPT4_RESERVED0_ERR_0_S  30
-
-/** EFUSE_RD_REPEAT_ERR1_REG register
- *  Programming error record register 1 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED1_ERR_0    0x0000FFFFU
-#define EFUSE_RPT4_RESERVED1_ERR_0_M  (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S)
-#define EFUSE_RPT4_RESERVED1_ERR_0_V  0x0000FFFFU
-#define EFUSE_RPT4_RESERVED1_ERR_0_S  0
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of WDT_DELAY_SEL.
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_0.
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_1.
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR2_REG register
- *  Programming error record register 2 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_2.
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  0
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_3.
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_4.
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_5.
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of SEC_DPA_LEVEL.
- */
-#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
-#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
-/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED2_ERR_1    (BIT(18))
-#define EFUSE_RPT4_RESERVED2_ERR_1_M  (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S)
-#define EFUSE_RPT4_RESERVED2_ERR_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED2_ERR_1_S  18
-/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of CRYPT_DPA_ENABLE.
- */
-#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_EN.
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED2_ERR_0    0x0000003FU
-#define EFUSE_RPT4_RESERVED2_ERR_0_M  (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S)
-#define EFUSE_RPT4_RESERVED2_ERR_0_V  0x0000003FU
-#define EFUSE_RPT4_RESERVED2_ERR_0_S  22
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of FLASH_TPUW.
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR3_REG register
- *  Programming error record register 3 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  Indicates a programming error of DIS_DIRECT_BOOT.
- */
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
-/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0;
- *  Indicates a programming error of UART_PRINT_CHANNEL.
- */
-#define EFUSE_USB_PRINT_ERR    (BIT(2))
-#define EFUSE_USB_PRINT_ERR_M  (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S)
-#define EFUSE_USB_PRINT_ERR_V  0x00000001U
-#define EFUSE_USB_PRINT_ERR_S  2
-/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_ERR_5    (BIT(3))
-#define EFUSE_RPT4_RESERVED3_ERR_5_M  (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S)
-#define EFUSE_RPT4_RESERVED3_ERR_5_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_ERR_5_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  Indicates a programming error of UART_PRINT_CONTROL.
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/** EFUSE_RPT4_RESERVED3_ERR_4 : RO; bitpos: [8]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_ERR_4    (BIT(8))
-#define EFUSE_RPT4_RESERVED3_ERR_4_M  (EFUSE_RPT4_RESERVED3_ERR_4_V << EFUSE_RPT4_RESERVED3_ERR_4_S)
-#define EFUSE_RPT4_RESERVED3_ERR_4_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_ERR_4_S  8
-/** EFUSE_RPT4_RESERVED3_ERR_3 : RO; bitpos: [9]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_ERR_3    (BIT(9))
-#define EFUSE_RPT4_RESERVED3_ERR_3_M  (EFUSE_RPT4_RESERVED3_ERR_3_V << EFUSE_RPT4_RESERVED3_ERR_3_S)
-#define EFUSE_RPT4_RESERVED3_ERR_3_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_ERR_3_S  9
-/** EFUSE_RPT4_RESERVED3_ERR_2 : RO; bitpos: [11:10]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_ERR_2    0x00000003U
-#define EFUSE_RPT4_RESERVED3_ERR_2_M  (EFUSE_RPT4_RESERVED3_ERR_2_V << EFUSE_RPT4_RESERVED3_ERR_2_S)
-#define EFUSE_RPT4_RESERVED3_ERR_2_V  0x00000003U
-#define EFUSE_RPT4_RESERVED3_ERR_2_S  10
-/** EFUSE_RPT4_RESERVED3_ERR_1 : RO; bitpos: [12]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_ERR_1    (BIT(12))
-#define EFUSE_RPT4_RESERVED3_ERR_1_M  (EFUSE_RPT4_RESERVED3_ERR_1_V << EFUSE_RPT4_RESERVED3_ERR_1_S)
-#define EFUSE_RPT4_RESERVED3_ERR_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_ERR_1_S  12
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of FORCE_SEND_RESUME.
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0;
- *  Indicates a programming error of SECURE_VERSION.
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  14
-/** EFUSE_RPT4_RESERVED3_ERR_0 : RO; bitpos: [31:30]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_ERR_0    0x00000003U
-#define EFUSE_RPT4_RESERVED3_ERR_0_M  (EFUSE_RPT4_RESERVED3_ERR_0_V << EFUSE_RPT4_RESERVED3_ERR_0_S)
-#define EFUSE_RPT4_RESERVED3_ERR_0_V  0x00000003U
-#define EFUSE_RPT4_RESERVED3_ERR_0_S  30
-
-/** EFUSE_RD_REPEAT_ERR4_REG register
- *  Programming error record register 4 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
-/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED4_ERR_1    0x00FFFFFFU
-#define EFUSE_RPT4_RESERVED4_ERR_1_M  (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S)
-#define EFUSE_RPT4_RESERVED4_ERR_1_V  0x00FFFFFFU
-#define EFUSE_RPT4_RESERVED4_ERR_1_S  0
-/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED4_ERR_0    0x000000FFU
-#define EFUSE_RPT4_RESERVED4_ERR_0_M  (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S)
-#define EFUSE_RPT4_RESERVED4_ERR_0_V  0x000000FFU
-#define EFUSE_RPT4_RESERVED4_ERR_0_S  24
-
-/** EFUSE_RD_RS_ERR0_REG register
- *  Programming error record register 0 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
-#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
-#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
-#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
-/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_MAC_SPI_8M_FAIL    (BIT(3))
-#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
-#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
-#define EFUSE_MAC_SPI_8M_FAIL_S  3
-/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART1_NUM    0x00000007U
-#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
-#define EFUSE_SYS_PART1_NUM_V  0x00000007U
-#define EFUSE_SYS_PART1_NUM_S  4
-/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part1 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART1_FAIL    (BIT(7))
-#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
-#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART1_FAIL_S  7
-/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
-#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_S  8
-/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  0: Means no failure and that the user data is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
-#define EFUSE_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_USR_DATA_FAIL_S  11
-/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY0_ERR_NUM    0x00000007U
-#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
-#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY0_ERR_NUM_S  12
-/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
- *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
- *  key0 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY0_FAIL    (BIT(15))
-#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
-#define EFUSE_KEY0_FAIL_V  0x00000001U
-#define EFUSE_KEY0_FAIL_S  15
-/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY1_ERR_NUM    0x00000007U
-#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
-#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY1_ERR_NUM_S  16
-/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
- *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
- *  key1 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY1_FAIL    (BIT(19))
-#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
-#define EFUSE_KEY1_FAIL_V  0x00000001U
-#define EFUSE_KEY1_FAIL_S  19
-/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY2_ERR_NUM    0x00000007U
-#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
-#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY2_ERR_NUM_S  20
-/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
- *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
- *  key2 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY2_FAIL    (BIT(23))
-#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
-#define EFUSE_KEY2_FAIL_V  0x00000001U
-#define EFUSE_KEY2_FAIL_S  23
-/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY3_ERR_NUM    0x00000007U
-#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
-#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY3_ERR_NUM_S  24
-/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
- *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
- *  key3 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY3_FAIL    (BIT(27))
-#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
-#define EFUSE_KEY3_FAIL_V  0x00000001U
-#define EFUSE_KEY3_FAIL_S  27
-/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY4_ERR_NUM    0x00000007U
-#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
-#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY4_ERR_NUM_S  28
-/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
- *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
- *  key4 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY4_FAIL    (BIT(31))
-#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
-#define EFUSE_KEY4_FAIL_V  0x00000001U
-#define EFUSE_KEY4_FAIL_S  31
-
-/** EFUSE_RD_RS_ERR1_REG register
- *  Programming error record register 1 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY5_ERR_NUM    0x00000007U
-#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
-#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY5_ERR_NUM_S  0
-/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
- *  key5 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY5_FAIL    (BIT(3))
-#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
-#define EFUSE_KEY5_FAIL_V  0x00000001U
-#define EFUSE_KEY5_FAIL_S  3
-/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
-#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_S  4
-/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part2 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART2_FAIL    (BIT(7))
-#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
-#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART2_FAIL_S  7
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
-/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit to force enable eFuse register configuration clock signal.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A:  programming operation command 0x5AA5: read operation command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
- *  The value of OTP_LOAD_SW.
- */
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
-#define EFUSE_OTP_LOAD_SW_V  0x00000001U
-#define EFUSE_OTP_LOAD_SW_S  4
-/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
- *  The value of OTP_VDDQ_C_SYNC2.
- */
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
- *  The value of OTP_STROBE_SW.
- */
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
-#define EFUSE_OTP_STROBE_SW_V  0x00000001U
-#define EFUSE_OTP_STROBE_SW_S  6
-/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
- *  The value of OTP_CSB_SW.
- */
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
-#define EFUSE_OTP_CSB_SW_V  0x00000001U
-#define EFUSE_OTP_CSB_SW_S  7
-/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
- *  The value of OTP_PGENB_SW.
- */
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
-#define EFUSE_OTP_PGENB_SW_V  0x00000001U
-#define EFUSE_OTP_PGENB_SW_S  8
-/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
- *  The value of OTP_VDDQ_IS_SW.
- */
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
- *  Indicates the number of block valid bit.
- */
-#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
-/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the read hold time.
- */
-#define EFUSE_THR_A    0x000000FFU
-#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
-#define EFUSE_THR_A_V  0x000000FFU
-#define EFUSE_THR_A_S  0
-/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
- *  Configures the read time.
- */
-#define EFUSE_TRD    0x000000FFU
-#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
-#define EFUSE_TRD_V  0x000000FFU
-#define EFUSE_TRD_S  8
-/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
- *  Configures the read setup time.
- */
-#define EFUSE_TSUR_A    0x000000FFU
-#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
-#define EFUSE_TSUR_A_V  0x000000FFU
-#define EFUSE_TSUR_A_S  16
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
- *  Configures the waiting time of reading eFuse memory.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
-/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the programming setup time.
- */
-#define EFUSE_TSUP_A    0x000000FFU
-#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
-#define EFUSE_TSUP_A_V  0x000000FFU
-#define EFUSE_TSUP_A_S  0
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
- *  Configures the programming hold time.
- */
-#define EFUSE_THP_A    0x000000FFU
-#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
-#define EFUSE_THP_A_V  0x000000FFU
-#define EFUSE_THP_A_S  24
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200;
- *  Configures the active programming time.
- */
-#define EFUSE_TPGM    0x0000FFFFU
-#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
-#define EFUSE_TPGM_V  0x0000FFFFU
-#define EFUSE_TPGM_S  16
-
-/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
-/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
- *  Set this bit to bypass reed solomon correction step.
- */
-#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
-#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
-#define EFUSE_BYPASS_RS_CORRECTION_S  0
-/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
- *  Configures block number of programming twice operation.
- */
-#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
-#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_S  1
-/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
- *  Set this bit to update multi-bit register signals.
- */
-#define EFUSE_UPDATE    (BIT(12))
-#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
-#define EFUSE_UPDATE_V  0x00000001U
-#define EFUSE_UPDATE_S  12
-/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
- *  Configures the inactive programming time.
- */
-#define EFUSE_TPGM_INACTIVE    0x000000FFU
-#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
-#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
-#define EFUSE_TPGM_INACTIVE_S  13
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35676928;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/efuse_struct.h b/components/soc/esp32c6/include/soc/efuse_struct.h
deleted file mode 100644
index e6971b4d583..00000000000
--- a/components/soc/esp32c6/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,2443 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PGM Data Register */
-/** Type of pgm_data0 register
- *  Register 0 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Register 1 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Register 2 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Register 3 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 3rd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Register 4 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 4th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Register 5 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 5th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Register 6 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 6th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Register 7 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 7th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-/** Type of pgm_check_value0 register
- *  Register 0 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Register 1 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Register 2 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: Read Data Register */
-/** Type of rd_wr_dis register
- *  BLOCK0 data register 0.
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled or
-         *  enabled. 1: Disabled. 0 Enabled.
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  BLOCK0 data register 1.
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t rd_dis:7;
-        /** swap_uart_sdio_en : RO; bitpos: [7]; default: 0;
-         *  Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not
-         *  swapped.
-         */
-        uint32_t swap_uart_sdio_en:1;
-        /** dis_icache : RO; bitpos: [8]; default: 0;
-         *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_icache:1;
-        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_jtag:1;
-        /** dis_download_icache : RO; bitpos: [10]; default: 0;
-         *  Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_download_icache:1;
-        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
-         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Represents whether the function that forces chip into download mode is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_force_download:1;
-        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
-         *  Represents whether SPI0 controller during boot_mode_download is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t spi_download_mspi_dis:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_twai:1;
-        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         *  is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t jtag_sel_enable:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
-         *  enabled.
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
-         *  mode). 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefh:2;
-        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefl:2;
-        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
-         *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.
-         */
-        uint32_t usb_exchg_pins:1;
-        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
-         *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
-         *  functioned.
-         */
-        uint32_t vdd_spi_as_gpio:1;
-        /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_2:2;
-        /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_1:1;
-        /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_0:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  BLOCK0 data register 2.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved1_0 : RO; bitpos: [15:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved1_0:16;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
-         *  selected. 0: not selected.
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
-         *  1: enabled. Even number of 1: disabled.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Represents the purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Represents the purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  BLOCK0 data register 3.
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Represents the purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Represents the purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Represents the purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Represents the purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
-         *  Represents the spa secure level by configuring the clock random divide mode.
-         */
-        uint32_t sec_dpa_level:2;
-        /** crypt_dpa_enable : RO; bitpos: [18]; default: 0;
-         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
-         */
-        uint32_t crypt_dpa_enable:1;
-        /** rpt4_reserved2_1 : RO; bitpos: [19]; default: 1;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved2_1:1;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved2_0:6;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Represents the flash waiting time after power-up, in unit of ms. When the value
-         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
-         *  is 2 times the programmed value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  BLOCK0 data register 4.
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
-         *  0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_5:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
-         *  disabled.
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Represents the type of UART printing. 00: force enable printing. 01: enable
-         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
-         *  at high level. 11: force disable printing.
-         */
-        uint32_t uart_print_control:2;
-        /** rpt4_reserved3_4 : RO; bitpos: [8]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_4:1;
-        /** rpt4_reserved3_3 : RO; bitpos: [9]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_3:1;
-        /** rpt4_reserved3_2 : RO; bitpos: [11:10]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_2:2;
-        /** rpt4_reserved3_1 : RO; bitpos: [12]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_1:1;
-        /** force_send_resume : RO; bitpos: [13]; default: 0;
-         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
-         *  forced. 0:not forced.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [29:14]; default: 0;
-         *  Represents the version used by ESP-IDF anti-rollback feature.
-         */
-        uint32_t secure_version:16;
-        /** secure_boot_disable_fast_wake : RO; bitpos: [30]; default: 0;
-         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t secure_boot_disable_fast_wake:1;
-        /** rpt4_reserved3_0 : RO; bitpos: [31]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_0:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  BLOCK0 data register 5.
- */
-typedef union {
-    struct {
-        /** disable_wafer_version_major : R; bitpos: [0]; default: 0;
-         *  Disables check of wafer version major
-         */
-        uint32_t disable_wafer_version_major:1;
-        /** disable_blk_version_major : R; bitpos: [1]; default: 0;
-         *  Disables check of blk version major
-         */
-        uint32_t disable_blk_version_major:1;
-        /** reserved_0_162 : R; bitpos: [23:2]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_0_162:22;
-        /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved4_0:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-/** Type of rd_mac_spi_sys_0 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the low 32 bits of MAC address.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_0_reg_t;
-
-/** Type of rd_mac_spi_sys_1 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Stores the high 16 bits of MAC address.
-         */
-        uint32_t mac_1:16;
-        /** mac_ext : RO; bitpos: [31:16]; default: 0;
-         *  Stores the extended bits of MAC address.
-         */
-        uint32_t mac_ext:16;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_1_reg_t;
-
-/** Type of rd_mac_spi_sys_2 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** active_hp_dbias : RO; bitpos: [4:0]; default: 0;
-         *  Stores the active hp dbias.
-         */
-        uint32_t active_hp_dbias:5;
-        /** active_lp_dbias : RO; bitpos: [9:5]; default: 0;
-         *  Stores the active lp dbias.
-         */
-        uint32_t active_lp_dbias:5;
-        /** lslp_hp_dbg : RO; bitpos: [11:10]; default: 0;
-         *  Stores the lslp hp dbg.
-         */
-        uint32_t lslp_hp_dbg:2;
-        /** lslp_hp_dbias : RO; bitpos: [15:12]; default: 0;
-         *  Stores the lslp hp dbias.
-         */
-        uint32_t lslp_hp_dbias:4;
-        /** dslp_lp_dbg : RO; bitpos: [18:16]; default: 0;
-         *  Stores the dslp lp dbg.
-         */
-        uint32_t dslp_lp_dbg:3;
-        /** dslp_lp_dbias : RO; bitpos: [22:19]; default: 0;
-         *  Stores the dslp lp dbias.
-         */
-        uint32_t dslp_lp_dbias:4;
-        /** dbias_vol_gap : RO; bitpos: [27:23]; default: 0;
-         *  Stores the hp and lp dbias vol gap.
-         */
-        uint32_t dbias_vol_gap:5;
-        /** spi_pad_conf_1 : RO; bitpos: [31:28]; default: 0;
-         *  Stores the first part of SPI_PAD_CONF.
-         */
-        uint32_t spi_pad_conf_1:4;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_2_reg_t;
-
-/** Type of rd_mac_spi_sys_3 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** spi_pad_conf_2 : RO; bitpos: [17:0]; default: 0;
-         *  Stores the second part of SPI_PAD_CONF.
-         */
-        uint32_t spi_pad_conf_2:18;
-        /** wafer_version_minor : R; bitpos: [21:18]; default: 0; */
-        uint32_t wafer_version_minor:4;
-        /** wafer_version_major : R; bitpos: [23:22]; default: 0; */
-        uint32_t wafer_version_major:2;
-        /** pkg_version : R; bitpos: [26:24]; default: 0;
-         *  Package version
-         */
-        uint32_t pkg_version:3;
-        /** blk_version_minor : R; bitpos: [29:27]; default: 0;
-         *  BLK_VERSION_MINOR of BLOCK2
-         */
-        uint32_t blk_version_minor:3;
-        /** blk_version_major : R; bitpos: [31:30]; default: 0;
-         *  BLK_VERSION_MAJOR of BLOCK2
-         */
-        uint32_t blk_version_major:2;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_3_reg_t;
-
-/** Type of rd_mac_spi_sys_4 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** flash_cap : R; bitpos: [2:0]; default: 0; */
-        uint32_t flash_cap:3;
-        /** flash_temp : R; bitpos: [4:3]; default: 0; */
-        uint32_t flash_temp:2;
-        /** flash_vendor : R; bitpos: [7:5]; default: 0; */
-        uint32_t flash_vendor:3;
-        /** reserved_1_136 : R; bitpos: [31:8]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_136:24;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_4_reg_t;
-
-/** Type of rd_mac_spi_sys_5 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_2:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_5_reg_t;
-
-/** Type of rd_sys_part1_data0 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** temp_calib : R; bitpos: [8:0]; default: 0;
-         *  Temperature calibration data
-         */
-        uint32_t temp_calib:9;
-        /** ocode : R; bitpos: [16:9]; default: 0;
-         *  ADC OCode
-         */
-        uint32_t ocode:8;
-        /** adc1_init_code_atten0 : R; bitpos: [26:17]; default: 0;
-         *  ADC1 init code at atten0
-         */
-        uint32_t adc1_init_code_atten0:10;
-        /** adc1_init_code_atten1 : R; bitpos: [31:27]; default: 0;
-         *  ADC1 init code at atten1
-         */
-        uint32_t adc1_init_code_atten1:5;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_init_code_atten1_1 : R; bitpos: [4:0]; default: 0;
-         *  ADC1 init code at atten1
-         */
-        uint32_t adc1_init_code_atten1_1:5;
-        /** adc1_init_code_atten2 : R; bitpos: [14:5]; default: 0;
-         *  ADC1 init code at atten2
-         */
-        uint32_t adc1_init_code_atten2:10;
-        /** adc1_init_code_atten3 : R; bitpos: [24:15]; default: 0;
-         *  ADC1 init code at atten3
-         */
-        uint32_t adc1_init_code_atten3:10;
-        /** adc1_cal_vol_atten0 : R; bitpos: [31:25]; default: 0;
-         *  ADC1 calibration voltage at atten0
-         */
-        uint32_t adc1_cal_vol_atten0:7;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0;
-         *  ADC1 calibration voltage at atten0
-         */
-        uint32_t adc1_cal_vol_atten0_1:3;
-        /** adc1_cal_vol_atten1 : R; bitpos: [12:3]; default: 0;
-         *  ADC1 calibration voltage at atten1
-         */
-        uint32_t adc1_cal_vol_atten1:10;
-        /** adc1_cal_vol_atten2 : R; bitpos: [22:13]; default: 0;
-         *  ADC1 calibration voltage at atten2
-         */
-        uint32_t adc1_cal_vol_atten2:10;
-        /** adc1_cal_vol_atten3 : R; bitpos: [31:23]; default: 0;
-         *  ADC1 calibration voltage at atten3
-         */
-        uint32_t adc1_cal_vol_atten3:9;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_cal_vol_atten3_1 : R; bitpos: [0]; default: 0;
-         *  ADC1 calibration voltage at atten3
-         */
-        uint32_t adc1_cal_vol_atten3_1:1;
-        /** adc1_init_code_atten0_ch0 : R; bitpos: [4:1]; default: 0;
-         *  ADC1 init code at atten0 ch0
-         */
-        uint32_t adc1_init_code_atten0_ch0:4;
-        /** adc1_init_code_atten0_ch1 : R; bitpos: [8:5]; default: 0;
-         *  ADC1 init code at atten0 ch1
-         */
-        uint32_t adc1_init_code_atten0_ch1:4;
-        /** adc1_init_code_atten0_ch2 : R; bitpos: [12:9]; default: 0;
-         *  ADC1 init code at atten0 ch2
-         */
-        uint32_t adc1_init_code_atten0_ch2:4;
-        /** adc1_init_code_atten0_ch3 : R; bitpos: [16:13]; default: 0;
-         *  ADC1 init code at atten0 ch3
-         */
-        uint32_t adc1_init_code_atten0_ch3:4;
-        /** adc1_init_code_atten0_ch4 : R; bitpos: [20:17]; default: 0;
-         *  ADC1 init code at atten0 ch4
-         */
-        uint32_t adc1_init_code_atten0_ch4:4;
-        /** adc1_init_code_atten0_ch5 : R; bitpos: [24:21]; default: 0;
-         *  ADC1 init code at atten0 ch5
-         */
-        uint32_t adc1_init_code_atten0_ch5:4;
-        /** adc1_init_code_atten0_ch6 : R; bitpos: [28:25]; default: 0;
-         *  ADC1 init code at atten0 ch6
-         */
-        uint32_t adc1_init_code_atten0_ch6:4;
-        /** reserved_2_253 : R; bitpos: [31:29]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_253:3;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-/** Type of rd_usr_data0 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_192:8;
-        /** custom_mac : R; bitpos: [31:8]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac:24;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac_1:24;
-        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_248:8;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-/** Type of rd_key0_data0 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-/** Type of rd_key1_data0 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-/** Type of rd_key2_data0 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-/** Type of rd_key3_data0 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-/** Type of rd_key4_data0 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-/** Type of rd_key5_data0 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-/** Type of rd_sys_part2_data0 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-
-/** Group: Report Register */
-/** Type of rd_repeat_err0 register
- *  Programming error record register 0 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Indicates a programming error of RD_DIS.
-         */
-        uint32_t rd_dis_err:7;
-        /** swap_uart_sdio_en_err : RO; bitpos: [7]; default: 0;
-         *  Indicates a programming error of SWAP_UART_SDIO_EN.
-         */
-        uint32_t swap_uart_sdio_en_err:1;
-        /** dis_icache_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of DIS_ICACHE.
-         */
-        uint32_t dis_icache_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Indicates a programming error of DIS_USB_JTAG.
-         */
-        uint32_t dis_usb_jtag_err:1;
-        /** dis_download_icache_err : RO; bitpos: [10]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_ICACHE.
-         */
-        uint32_t dis_download_icache_err:1;
-        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
-         *  Indicates a programming error of DIS_USB_DEVICE.
-         */
-        uint32_t dis_usb_serial_jtag_err:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
-         */
-        uint32_t dis_force_download_err:1;
-        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
-         */
-        uint32_t spi_download_mspi_dis_err:1;
-        /** dis_twai_err : RO; bitpos: [14]; default: 0;
-         *  Indicates a programming error of DIS_CAN.
-         */
-        uint32_t dis_twai_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  Indicates a programming error of JTAG_SEL_ENABLE.
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  Indicates a programming error of SOFT_DIS_JTAG.
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of DIS_PAD_JTAG.
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
-         *  Indicates a programming error of USB_DREFH.
-         */
-        uint32_t usb_drefh_err:2;
-        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
-         *  Indicates a programming error of USB_DREFL.
-         */
-        uint32_t usb_drefl_err:2;
-        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of USB_EXCHG_PINS.
-         */
-        uint32_t usb_exchg_pins_err:1;
-        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
-         *  Indicates a programming error of VDD_SPI_AS_GPIO.
-         */
-        uint32_t vdd_spi_as_gpio_err:1;
-        /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_err_2:2;
-        /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_err_1:1;
-        /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_err_0:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err0_reg_t;
-
-/** Type of rd_repeat_err1 register
- *  Programming error record register 1 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved1_err_0:16;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of WDT_DELAY_SEL.
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_0.
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_1.
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err1_reg_t;
-
-/** Type of rd_repeat_err2 register
- *  Programming error record register 2 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_2.
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_3.
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_4.
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_5.
-         */
-        uint32_t key_purpose_5_err:4;
-        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of SEC_DPA_LEVEL.
-         */
-        uint32_t sec_dpa_level_err:2;
-        /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved2_err_1:1;
-        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of CRYPT_DPA_ENABLE.
-         */
-        uint32_t crypt_dpa_enable_err:1;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_EN.
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved2_err_0:6;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of FLASH_TPUW.
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err2_reg_t;
-
-/** Type of rd_repeat_err3 register
- *  Programming error record register 3 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Indicates a programming error of DIS_DIRECT_BOOT.
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** usb_print_err : RO; bitpos: [2]; default: 0;
-         *  Indicates a programming error of UART_PRINT_CHANNEL.
-         */
-        uint32_t usb_print_err:1;
-        /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_err_5:1;
-        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  Indicates a programming error of UART_PRINT_CONTROL.
-         */
-        uint32_t uart_print_control_err:2;
-        /** rpt4_reserved3_err_4 : RO; bitpos: [8]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_err_4:1;
-        /** rpt4_reserved3_err_3 : RO; bitpos: [9]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_err_3:1;
-        /** rpt4_reserved3_err_2 : RO; bitpos: [11:10]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_err_2:2;
-        /** rpt4_reserved3_err_1 : RO; bitpos: [12]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_err_1:1;
-        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of FORCE_SEND_RESUME.
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [29:14]; default: 0;
-         *  Indicates a programming error of SECURE_VERSION.
-         */
-        uint32_t secure_version_err:16;
-        /** rpt4_reserved3_err_0 : RO; bitpos: [31:30]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_err_0:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err3_reg_t;
-
-/** Type of rd_repeat_err4 register
- *  Programming error record register 4 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved4_err_1 : RO; bitpos: [23:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved4_err_1:24;
-        /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved4_err_0:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err4_reg_t;
-
-/** Type of rd_rs_err0 register
- *  Programming error record register 0 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t mac_spi_8m_err_num:3;
-        /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t mac_spi_8m_fail:1;
-        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part1_num:3;
-        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part1_fail:1;
-        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t usr_data_err_num:3;
-        /** usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  0: Means no failure and that the user data is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t usr_data_fail:1;
-        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key0_err_num:3;
-        /** key0_fail : RO; bitpos: [15]; default: 0;
-         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
-         *  key0 failed and the number of error bytes is over 6.
-         */
-        uint32_t key0_fail:1;
-        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key1_err_num:3;
-        /** key1_fail : RO; bitpos: [19]; default: 0;
-         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
-         *  key1 failed and the number of error bytes is over 6.
-         */
-        uint32_t key1_fail:1;
-        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key2_err_num:3;
-        /** key2_fail : RO; bitpos: [23]; default: 0;
-         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
-         *  key2 failed and the number of error bytes is over 6.
-         */
-        uint32_t key2_fail:1;
-        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key3_err_num:3;
-        /** key3_fail : RO; bitpos: [27]; default: 0;
-         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
-         *  key3 failed and the number of error bytes is over 6.
-         */
-        uint32_t key3_fail:1;
-        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key4_err_num:3;
-        /** key4_fail : RO; bitpos: [31]; default: 0;
-         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
-         *  key4 failed and the number of error bytes is over 6.
-         */
-        uint32_t key4_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_err0_reg_t;
-
-/** Type of rd_rs_err1 register
- *  Programming error record register 1 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key5_err_num:3;
-        /** key5_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
-         *  key5 failed and the number of error bytes is over 6.
-         */
-        uint32_t key5_fail:1;
-        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part2_err_num:3;
-        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part2_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_err1_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to force enable eFuse register configuration clock signal.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuraiton register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
-         */
-        uint32_t op_code:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the read hold time.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures the read time.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures the read setup time.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
-         *  Configures the waiting time of reading eFuse memory.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the programming setup time.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        /** thp_a : R/W; bitpos: [31:24]; default: 1;
-         *  Configures the programming hold time.
-         */
-        uint32_t thp_a:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        /** tpgm : R/W; bitpos: [31:16]; default: 200;
-         *  Configures the active programming time.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-/** Type of wr_tim_conf0_rs_bypass register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-typedef union {
-    struct {
-        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to bypass reed solomon correction step.
-         */
-        uint32_t bypass_rs_correction:1;
-        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
-         *  Configures block number of programming twice operation.
-         */
-        uint32_t bypass_rs_blk_num:11;
-        /** update : WT; bitpos: [12]; default: 0;
-         *  Set this bit to update multi-bit register signals.
-         */
-        uint32_t update:1;
-        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
-         *  Configures the inactive programming time.
-         */
-        uint32_t tpgm_inactive:8;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_rs_bypass_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WO; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35676928;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0;
-    volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1;
-    volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2;
-    volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3;
-    volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4;
-    volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
-    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
-    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
-    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
-    uint32_t reserved_18c;
-    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
-    uint32_t reserved_194[11];
-    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
-    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
-    volatile efuse_date_reg_t date;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/extmem_reg.h b/components/soc/esp32c6/include/soc/extmem_reg.h
deleted file mode 100644
index a9cb6935862..00000000000
--- a/components/soc/esp32c6/include/soc/extmem_reg.h
+++ /dev/null
@@ -1,871 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define EXTMEM_L1_CACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x4)
-/* EXTMEM_L1_CACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
-#define EXTMEM_L1_CACHE_SHUT_DBUS    (BIT(1))
-#define EXTMEM_L1_CACHE_SHUT_DBUS_M  (BIT(1))
-#define EXTMEM_L1_CACHE_SHUT_DBUS_V  0x1
-#define EXTMEM_L1_CACHE_SHUT_DBUS_S  1
-/* EXTMEM_L1_CACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
-#define EXTMEM_L1_CACHE_SHUT_IBUS    (BIT(0))
-#define EXTMEM_L1_CACHE_SHUT_IBUS_M  (BIT(0))
-#define EXTMEM_L1_CACHE_SHUT_IBUS_V  0x1
-#define EXTMEM_L1_CACHE_SHUT_IBUS_S  0
-
-#define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x20)
-/* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
-#define EXTMEM_L1_CACHE_WRAP    (BIT(4))
-#define EXTMEM_L1_CACHE_WRAP_M  (BIT(4))
-#define EXTMEM_L1_CACHE_WRAP_V  0x1
-#define EXTMEM_L1_CACHE_WRAP_S  4
-
-#define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x24)
-/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
-/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_M  (BIT(18))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_S  18
-/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power
-down.*/
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_M  (BIT(17))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_S  17
-/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating,
-0: open clock gating..*/
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_M  (BIT(16))
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_S  16
-
-#define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x28)
-/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
-/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u
-p.*/
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_M  (BIT(18))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_S  18
-/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
- down.*/
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_M  (BIT(17))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_S  17
-/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to close clock gating of  L1-Cache data memory. 1: close gating,
- 0: open clock gating..*/
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_M  (BIT(16))
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_S  16
-
-#define EXTMEM_L1_CACHE_FREEZE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x2C)
-/* EXTMEM_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */
-/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or
-not. 0: not finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_FREEZE_DONE    (BIT(18))
-#define EXTMEM_L1_CACHE_FREEZE_DONE_M  (BIT(18))
-#define EXTMEM_L1_CACHE_FREEZE_DONE_V  0x1
-#define EXTMEM_L1_CACHE_FREEZE_DONE_S  18
-/* EXTMEM_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
- will not stuck. 1: a miss-access will stuck..*/
-#define EXTMEM_L1_CACHE_FREEZE_MODE    (BIT(17))
-#define EXTMEM_L1_CACHE_FREEZE_MODE_M  (BIT(17))
-#define EXTMEM_L1_CACHE_FREEZE_MODE_V  0x1
-#define EXTMEM_L1_CACHE_FREEZE_MODE_S  17
-/* EXTMEM_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof
-tware..*/
-#define EXTMEM_L1_CACHE_FREEZE_EN    (BIT(16))
-#define EXTMEM_L1_CACHE_FREEZE_EN_M  (BIT(16))
-#define EXTMEM_L1_CACHE_FREEZE_EN_V  0x1
-#define EXTMEM_L1_CACHE_FREEZE_EN_S  16
-
-#define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG          (DR_REG_EXTMEM_BASE + 0x30)
-/* EXTMEM_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable,
-1: enable..*/
-#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
-#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_M  (BIT(17))
-#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_S  17
-/* EXTMEM_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1
-: enable..*/
-#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
-#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_M  (BIT(16))
-#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_V  0x1
-#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_S  16
-
-#define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG          (DR_REG_EXTMEM_BASE + 0x34)
-/* EXTMEM_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1
-: enable..*/
-#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
-#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_M  (BIT(17))
-#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_S  17
-/* EXTMEM_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
- enable..*/
-#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
-#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_M  (BIT(16))
-#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_V  0x1
-#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_S  16
-
-#define EXTMEM_L1_CACHE_PRELOCK_CONF_REG          (DR_REG_EXTMEM_BASE + 0x78)
-/* EXTMEM_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_M  (BIT(1))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_V  0x1
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_S  1
-/* EXTMEM_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_M  (BIT(0))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_V  0x1
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_S  0
-
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x7C)
-/* EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the first section
-of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0
-_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x80)
-/* EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the second section
- of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT
-1_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x84)
-/* EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */
-/*description: Those bits are used to configure the size of the second section of prelock on L1
--Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x3FFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
-/* EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */
-/*description: Those bits are used to configure the size of the first section of prelock on L1-
-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S))
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x3FFF
-#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x88)
-/* EXTMEM_L1_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0:
- not finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_LOCK_DONE    (BIT(2))
-#define EXTMEM_L1_CACHE_LOCK_DONE_M  (BIT(2))
-#define EXTMEM_L1_CACHE_LOCK_DONE_V  0x1
-#define EXTMEM_L1_CACHE_LOCK_DONE_S  2
-/* EXTMEM_L1_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
- unlock operation done.*/
-#define EXTMEM_L1_CACHE_UNLOCK_ENA    (BIT(1))
-#define EXTMEM_L1_CACHE_UNLOCK_ENA_M  (BIT(1))
-#define EXTMEM_L1_CACHE_UNLOCK_ENA_V  0x1
-#define EXTMEM_L1_CACHE_UNLOCK_ENA_S  1
-/* EXTMEM_L1_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
-ock operation done.*/
-#define EXTMEM_L1_CACHE_LOCK_ENA    (BIT(0))
-#define EXTMEM_L1_CACHE_LOCK_ENA_M  (BIT(0))
-#define EXTMEM_L1_CACHE_LOCK_ENA_V  0x1
-#define EXTMEM_L1_CACHE_LOCK_ENA_S  0
-
-#define EXTMEM_L1_CACHE_LOCK_MAP_REG          (DR_REG_EXTMEM_BASE + 0x8C)
-/* EXTMEM_L1_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: Those bits are used to indicate which caches in the two-level cache structure wi
-ll apply this lock/unlock operation. [4]: L1-Cache.*/
-#define EXTMEM_L1_CACHE_LOCK_MAP    0x0000003F
-#define EXTMEM_L1_CACHE_LOCK_MAP_M  ((EXTMEM_L1_CACHE_LOCK_MAP_V)<<(EXTMEM_L1_CACHE_LOCK_MAP_S))
-#define EXTMEM_L1_CACHE_LOCK_MAP_V  0x3F
-#define EXTMEM_L1_CACHE_LOCK_MAP_S  0
-
-#define EXTMEM_L1_CACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x90)
-/* EXTMEM_L1_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the lock/unlock op
-eration, which should be used together with CACHE_LOCK_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_LOCK_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_LOCK_ADDR_M  ((EXTMEM_L1_CACHE_LOCK_ADDR_V)<<(EXTMEM_L1_CACHE_LOCK_ADDR_S))
-#define EXTMEM_L1_CACHE_LOCK_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_LOCK_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x94)
-/* EXTMEM_L1_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: Those bits are used to configure the size of the lock/unlock operation, which sh
-ould be used together with CACHE_LOCK_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_LOCK_SIZE    0x0000FFFF
-#define EXTMEM_L1_CACHE_LOCK_SIZE_M  ((EXTMEM_L1_CACHE_LOCK_SIZE_V)<<(EXTMEM_L1_CACHE_LOCK_SIZE_S))
-#define EXTMEM_L1_CACHE_LOCK_SIZE_V  0xFFFF
-#define EXTMEM_L1_CACHE_LOCK_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x98)
-/* EXTMEM_L1_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback
-, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE    (BIT(4))
-#define EXTMEM_L1_CACHE_SYNC_DONE_M  (BIT(4))
-#define EXTMEM_L1_CACHE_SYNC_DONE_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_S  4
-/* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
-/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
-hardware after writeback-invalidate operation done. Note that this bit and the o
-ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
-, that is, those bits can not be set to 1 at the same time..*/
-#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
-#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
-#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_V  0x1
-#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_S  3
-/* EXTMEM_L1_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
-ter writeback operation done. Note that this bit and the other sync-bits (invali
-date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
-those bits can not be set to 1 at the same time..*/
-#define EXTMEM_L1_CACHE_WRITEBACK_ENA    (BIT(2))
-#define EXTMEM_L1_CACHE_WRITEBACK_ENA_M  (BIT(2))
-#define EXTMEM_L1_CACHE_WRITEBACK_ENA_V  0x1
-#define EXTMEM_L1_CACHE_WRITEBACK_ENA_S  2
-/* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable clean operation. It will be cleared by hardware after
-clean operation done. Note that this bit and the other sync-bits (invalidate_ena
-, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
-e bits can not be set to 1 at the same time..*/
-#define EXTMEM_L1_CACHE_CLEAN_ENA    (BIT(1))
-#define EXTMEM_L1_CACHE_CLEAN_ENA_M  (BIT(1))
-#define EXTMEM_L1_CACHE_CLEAN_ENA_V  0x1
-#define EXTMEM_L1_CACHE_CLEAN_ENA_S  1
-/* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
-/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
-fter invalidate operation done. Note that this bit and the other sync-bits (clea
-n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
- those bits can not be set to 1 at the same time..*/
-#define EXTMEM_L1_CACHE_INVALIDATE_ENA    (BIT(0))
-#define EXTMEM_L1_CACHE_INVALIDATE_ENA_M  (BIT(0))
-#define EXTMEM_L1_CACHE_INVALIDATE_ENA_V  0x1
-#define EXTMEM_L1_CACHE_INVALIDATE_ENA_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_MAP_REG          (DR_REG_EXTMEM_BASE + 0x9C)
-/* EXTMEM_L1_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
-/*description: Those bits are used to indicate which caches in the two-level cache structure wi
-ll apply the sync operation.  [4]: L1-Cache.*/
-#define EXTMEM_L1_CACHE_SYNC_MAP    0x0000003F
-#define EXTMEM_L1_CACHE_SYNC_MAP_M  ((EXTMEM_L1_CACHE_SYNC_MAP_V)<<(EXTMEM_L1_CACHE_SYNC_MAP_S))
-#define EXTMEM_L1_CACHE_SYNC_MAP_V  0x3F
-#define EXTMEM_L1_CACHE_SYNC_MAP_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xA0)
-/* EXTMEM_L1_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the sync operation
-, which should be used together with CACHE_SYNC_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_SYNC_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_SYNC_ADDR_M  ((EXTMEM_L1_CACHE_SYNC_ADDR_V)<<(EXTMEM_L1_CACHE_SYNC_ADDR_S))
-#define EXTMEM_L1_CACHE_SYNC_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_SYNC_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xA4)
-/* EXTMEM_L1_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Those bits are used to configure the size of the sync operation, which should be
- used together with CACHE_SYNC_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_SYNC_SIZE    0x00FFFFFF
-#define EXTMEM_L1_CACHE_SYNC_SIZE_M  ((EXTMEM_L1_CACHE_SYNC_SIZE_V)<<(EXTMEM_L1_CACHE_SYNC_SIZE_S))
-#define EXTMEM_L1_CACHE_SYNC_SIZE_V  0xFFFFFF
-#define EXTMEM_L1_CACHE_SYNC_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xD8)
-/* EXTMEM_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
-/*description: The bit is used to set  the gid of l1 cache preload..*/
-#define EXTMEM_L1_CACHE_PRELOAD_RGID    0x0000000F
-#define EXTMEM_L1_CACHE_PRELOAD_RGID_M  ((EXTMEM_L1_CACHE_PRELOAD_RGID_V)<<(EXTMEM_L1_CACHE_PRELOAD_RGID_S))
-#define EXTMEM_L1_CACHE_PRELOAD_RGID_V  0xF
-#define EXTMEM_L1_CACHE_PRELOAD_RGID_S  3
-/* EXTMEM_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1
-: descending..*/
-#define EXTMEM_L1_CACHE_PRELOAD_ORDER    (BIT(2))
-#define EXTMEM_L1_CACHE_PRELOAD_ORDER_M  (BIT(2))
-#define EXTMEM_L1_CACHE_PRELOAD_ORDER_V  0x1
-#define EXTMEM_L1_CACHE_PRELOAD_ORDER_S  2
-/* EXTMEM_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether preload operation is finished or not. 0: not
- finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_PRELOAD_DONE    (BIT(1))
-#define EXTMEM_L1_CACHE_PRELOAD_DONE_M  (BIT(1))
-#define EXTMEM_L1_CACHE_PRELOAD_DONE_V  0x1
-#define EXTMEM_L1_CACHE_PRELOAD_DONE_S  1
-/* EXTMEM_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h
-ardware automatically after preload operation is done..*/
-#define EXTMEM_L1_CACHE_PRELOAD_ENA    (BIT(0))
-#define EXTMEM_L1_CACHE_PRELOAD_ENA_M  (BIT(0))
-#define EXTMEM_L1_CACHE_PRELOAD_ENA_V  0x1
-#define EXTMEM_L1_CACHE_PRELOAD_ENA_S  0
-
-#define EXTMEM_L1_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xDC)
-/* EXTMEM_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of preload on L1-Cach
-e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/
-#define EXTMEM_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOAD_ADDR_M  ((EXTMEM_L1_CACHE_PRELOAD_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOAD_ADDR_S))
-#define EXTMEM_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_PRELOAD_ADDR_S  0
-
-#define EXTMEM_L1_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xE0)
-/* EXTMEM_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: Those bits are used to configure the size of the first section of prelock on L1-
-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/
-#define EXTMEM_L1_CACHE_PRELOAD_SIZE    0x00003FFF
-#define EXTMEM_L1_CACHE_PRELOAD_SIZE_M  ((EXTMEM_L1_CACHE_PRELOAD_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOAD_SIZE_S))
-#define EXTMEM_L1_CACHE_PRELOAD_SIZE_V  0x3FFF
-#define EXTMEM_L1_CACHE_PRELOAD_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x134)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (BIT(9))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (BIT(8))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/* EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0
-/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003
-#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x3
-#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/* EXTMEM_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0:
- ascending. 1: descending..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_M  (BIT(2))
-#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_S  2
-/* EXTMEM_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o
-r not. 0: not finished. 1: finished..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_M  (BIT(1))
-#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_S  1
-/* EXTMEM_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable and disable autoload operation on L1-Cache.  1: enable
-, 0: disable..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_M  (BIT(0))
-#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_V  0x1
-#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x138)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the first section
-for autoload operation on L1-Cache. Note that it should be used together with L1
-_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x13C)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
-/*description: Those bits are used to configure the size of the first section for autoload oper
-ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
-CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x140)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the second section
- for autoload operation on L1-Cache. Note that it should be used together with L
-1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x144)
-/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
-/*description: Those bits are used to configure the size of the second section for autoload ope
-ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
-SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S))
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFFF
-#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-#define EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x158)
-/* EXTMEM_L1_DBUS_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
-1-DCache due to bus1 accesses L1-DCache..*/
-#define EXTMEM_L1_DBUS_OVF_INT_ENA    (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_ENA_M  (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_ENA_V  0x1
-#define EXTMEM_L1_DBUS_OVF_INT_ENA_S  5
-/* EXTMEM_L1_IBUS_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
-1-DCache due to bus0 accesses L1-DCache..*/
-#define EXTMEM_L1_IBUS_OVF_INT_ENA    (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_ENA_M  (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_ENA_V  0x1
-#define EXTMEM_L1_IBUS_OVF_INT_ENA_S  4
-
-#define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x15C)
-/* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus1 accesses L1-DCache..*/
-#define EXTMEM_L1_DBUS_OVF_INT_CLR    (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_CLR_M  (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_CLR_V  0x1
-#define EXTMEM_L1_DBUS_OVF_INT_CLR_S  5
-/* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus0 accesses L1-DCache..*/
-#define EXTMEM_L1_IBUS_OVF_INT_CLR    (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_CLR_M  (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_CLR_V  0x1
-#define EXTMEM_L1_IBUS_OVF_INT_CLR_S  4
-
-#define EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x160)
-/* EXTMEM_L1_DBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
-e due to bus1 accesses L1-DCache..*/
-#define EXTMEM_L1_DBUS_OVF_INT_RAW    (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_RAW_M  (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_RAW_V  0x1
-#define EXTMEM_L1_DBUS_OVF_INT_RAW_S  5
-/* EXTMEM_L1_IBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
-e due to bus0 accesses L1-DCache..*/
-#define EXTMEM_L1_IBUS_OVF_INT_RAW    (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_RAW_M  (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_RAW_V  0x1
-#define EXTMEM_L1_IBUS_OVF_INT_RAW_S  4
-
-#define EXTMEM_L1_CACHE_ACS_CNT_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x164)
-/* EXTMEM_L1_DBUS_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
-n L1-DCache due to bus1 accesses L1-DCache..*/
-#define EXTMEM_L1_DBUS_OVF_INT_ST    (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_ST_M  (BIT(5))
-#define EXTMEM_L1_DBUS_OVF_INT_ST_V  0x1
-#define EXTMEM_L1_DBUS_OVF_INT_ST_S  5
-/* EXTMEM_L1_IBUS_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
-n L1-DCache due to bus0 accesses L1-DCache..*/
-#define EXTMEM_L1_IBUS_OVF_INT_ST    (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_ST_M  (BIT(4))
-#define EXTMEM_L1_IBUS_OVF_INT_ST_V  0x1
-#define EXTMEM_L1_IBUS_OVF_INT_ST_S  4
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x168)
-/* EXTMEM_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due
-to cpu accesses L1-DCache..*/
-#define EXTMEM_L1_CACHE_FAIL_INT_ENA    (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_ENA_M  (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_FAIL_INT_ENA_S  4
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x16C)
-/* EXTMEM_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t
-o cpu accesses L1-DCache..*/
-#define EXTMEM_L1_CACHE_FAIL_INT_CLR    (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_CLR_M  (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_FAIL_INT_CLR_S  4
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x170)
-/* EXTMEM_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/
-#define EXTMEM_L1_CACHE_FAIL_INT_RAW    (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_RAW_M  (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_FAIL_INT_RAW_S  4
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x174)
-/* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
-ue to cpu accesses L1-DCache..*/
-#define EXTMEM_L1_CACHE_FAIL_INT_ST    (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
-#define EXTMEM_L1_CACHE_FAIL_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_FAIL_INT_ST_S  4
-
-#define EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x178)
-/* EXTMEM_L1_DBUS_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */
-/*description: The bit is used to clear dbus1 counter in L1-DCache..*/
-#define EXTMEM_L1_DBUS_CNT_CLR    (BIT(21))
-#define EXTMEM_L1_DBUS_CNT_CLR_M  (BIT(21))
-#define EXTMEM_L1_DBUS_CNT_CLR_V  0x1
-#define EXTMEM_L1_DBUS_CNT_CLR_S  21
-/* EXTMEM_L1_IBUS_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
-#define EXTMEM_L1_IBUS_CNT_CLR    (BIT(20))
-#define EXTMEM_L1_IBUS_CNT_CLR_M  (BIT(20))
-#define EXTMEM_L1_IBUS_CNT_CLR_V  0x1
-#define EXTMEM_L1_IBUS_CNT_CLR_S  20
-/* EXTMEM_L1_DBUS_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable dbus1 counter in L1-DCache..*/
-#define EXTMEM_L1_DBUS_CNT_ENA    (BIT(5))
-#define EXTMEM_L1_DBUS_CNT_ENA_M  (BIT(5))
-#define EXTMEM_L1_DBUS_CNT_ENA_V  0x1
-#define EXTMEM_L1_DBUS_CNT_ENA_S  5
-/* EXTMEM_L1_IBUS_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable dbus0 counter in L1-DCache..*/
-#define EXTMEM_L1_IBUS_CNT_ENA    (BIT(4))
-#define EXTMEM_L1_IBUS_CNT_ENA_M  (BIT(4))
-#define EXTMEM_L1_IBUS_CNT_ENA_V  0x1
-#define EXTMEM_L1_IBUS_CNT_ENA_S  4
-
-#define EXTMEM_L1_IBUS_ACS_HIT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1BC)
-/* EXTMEM_L1_IBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of hits when bus0 accesses L1-Cache..*/
-#define EXTMEM_L1_IBUS_HIT_CNT    0xFFFFFFFF
-#define EXTMEM_L1_IBUS_HIT_CNT_M  ((EXTMEM_L1_IBUS_HIT_CNT_V)<<(EXTMEM_L1_IBUS_HIT_CNT_S))
-#define EXTMEM_L1_IBUS_HIT_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_IBUS_HIT_CNT_S  0
-
-#define EXTMEM_L1_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C0)
-/* EXTMEM_L1_IBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of missing when bus0 accesses L1-Cache..*/
-#define EXTMEM_L1_IBUS_MISS_CNT    0xFFFFFFFF
-#define EXTMEM_L1_IBUS_MISS_CNT_M  ((EXTMEM_L1_IBUS_MISS_CNT_V)<<(EXTMEM_L1_IBUS_MISS_CNT_S))
-#define EXTMEM_L1_IBUS_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_IBUS_MISS_CNT_S  0
-
-#define EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C4)
-/* EXTMEM_L1_IBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/
-#define EXTMEM_L1_IBUS_CONFLICT_CNT    0xFFFFFFFF
-#define EXTMEM_L1_IBUS_CONFLICT_CNT_M  ((EXTMEM_L1_IBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_IBUS_CONFLICT_CNT_S))
-#define EXTMEM_L1_IBUS_CONFLICT_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_IBUS_CONFLICT_CNT_S  0
-
-#define EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C8)
-/* EXTMEM_L1_IBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
-bus0 accessing L1-Cache..*/
-#define EXTMEM_L1_IBUS_NXTLVL_CNT    0xFFFFFFFF
-#define EXTMEM_L1_IBUS_NXTLVL_CNT_M  ((EXTMEM_L1_IBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_IBUS_NXTLVL_CNT_S))
-#define EXTMEM_L1_IBUS_NXTLVL_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_IBUS_NXTLVL_CNT_S  0
-
-#define EXTMEM_L1_DBUS_ACS_HIT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1CC)
-/* EXTMEM_L1_DBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of hits when bus1 accesses L1-Cache..*/
-#define EXTMEM_L1_DBUS_HIT_CNT    0xFFFFFFFF
-#define EXTMEM_L1_DBUS_HIT_CNT_M  ((EXTMEM_L1_DBUS_HIT_CNT_V)<<(EXTMEM_L1_DBUS_HIT_CNT_S))
-#define EXTMEM_L1_DBUS_HIT_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_DBUS_HIT_CNT_S  0
-
-#define EXTMEM_L1_DBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D0)
-/* EXTMEM_L1_DBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of missing when bus1 accesses L1-Cache..*/
-#define EXTMEM_L1_DBUS_MISS_CNT    0xFFFFFFFF
-#define EXTMEM_L1_DBUS_MISS_CNT_M  ((EXTMEM_L1_DBUS_MISS_CNT_V)<<(EXTMEM_L1_DBUS_MISS_CNT_S))
-#define EXTMEM_L1_DBUS_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_DBUS_MISS_CNT_S  0
-
-#define EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D4)
-/* EXTMEM_L1_DBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/
-#define EXTMEM_L1_DBUS_CONFLICT_CNT    0xFFFFFFFF
-#define EXTMEM_L1_DBUS_CONFLICT_CNT_M  ((EXTMEM_L1_DBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_DBUS_CONFLICT_CNT_S))
-#define EXTMEM_L1_DBUS_CONFLICT_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_DBUS_CONFLICT_CNT_S  0
-
-#define EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D8)
-/* EXTMEM_L1_DBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
-bus1 accessing L1-Cache..*/
-#define EXTMEM_L1_DBUS_NXTLVL_CNT    0xFFFFFFFF
-#define EXTMEM_L1_DBUS_NXTLVL_CNT_M  ((EXTMEM_L1_DBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_DBUS_NXTLVL_CNT_S))
-#define EXTMEM_L1_DBUS_NXTLVL_CNT_V  0xFFFFFFFF
-#define EXTMEM_L1_DBUS_NXTLVL_CNT_S  0
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x21C)
-/* EXTMEM_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: The register records the attribution of fail-access when cache accesses L1-Cache
-..*/
-#define EXTMEM_L1_CACHE_FAIL_ATTR    0x0000FFFF
-#define EXTMEM_L1_CACHE_FAIL_ATTR_M  ((EXTMEM_L1_CACHE_FAIL_ATTR_V)<<(EXTMEM_L1_CACHE_FAIL_ATTR_S))
-#define EXTMEM_L1_CACHE_FAIL_ATTR_V  0xFFFF
-#define EXTMEM_L1_CACHE_FAIL_ATTR_S  16
-/* EXTMEM_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/
-#define EXTMEM_L1_CACHE_FAIL_ID    0x0000FFFF
-#define EXTMEM_L1_CACHE_FAIL_ID_M  ((EXTMEM_L1_CACHE_FAIL_ID_V)<<(EXTMEM_L1_CACHE_FAIL_ID_S))
-#define EXTMEM_L1_CACHE_FAIL_ID_V  0xFFFF
-#define EXTMEM_L1_CACHE_FAIL_ID_S  0
-
-#define EXTMEM_L1_CACHE_ACS_FAIL_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x220)
-/* EXTMEM_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the address of fail-access when cache accesses L1-Cache..*/
-#define EXTMEM_L1_CACHE_FAIL_ADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_FAIL_ADDR_M  ((EXTMEM_L1_CACHE_FAIL_ADDR_V)<<(EXTMEM_L1_CACHE_FAIL_ADDR_S))
-#define EXTMEM_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_FAIL_ADDR_S  0
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x224)
-/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of Cache sync-operation error..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA    (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_M  (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_S  13
-/* EXTMEM_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_M  (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_S  11
-/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of Cache sync-operation done..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA    (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_M  (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_S  6
-/* EXTMEM_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op
-eration is done, interrupt occurs..*/
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_V  0x1
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_S  4
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x228)
-/* EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of Cache sync-operation error..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR    (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_M  (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_S  13
-/* EXTMEM_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_M  (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_S  11
-/* EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is
- done..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR    (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_M  (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_S  6
-/* EXTMEM_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat
-ion is done..*/
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_V  0x1
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_S  4
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x22C)
-/* EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc
-curs..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW    (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_M  (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_S  13
-/* EXTMEM_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er
-ror occurs..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_M  (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_S  11
-/* EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW    (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_M  (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_S  6
-/* EXTMEM_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
- done..*/
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_V  0x1
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_S  4
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x230)
-/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST    (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_M  (BIT(13))
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S  13
-/* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro
-r..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_S  11
-/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o
-peration is done..*/
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST    (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_M  (BIT(6))
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_S  6
-/* EXTMEM_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre
-load-operation is done..*/
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_V  0x1
-#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_S  4
-
-#define EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG          (DR_REG_EXTMEM_BASE + 0x234)
-/* EXTMEM_L1_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: The values 0-2 are available which means sync map, command conflict and size are
- error in Cache System..*/
-#define EXTMEM_L1_CACHE_SYNC_ERR_CODE    0x00000003
-#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_M  ((EXTMEM_L1_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_L1_CACHE_SYNC_ERR_CODE_S))
-#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_V  0x3
-#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_S  12
-/* EXTMEM_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/
-#define EXTMEM_L1_CACHE_PLD_ERR_CODE    0x00000003
-#define EXTMEM_L1_CACHE_PLD_ERR_CODE_M  ((EXTMEM_L1_CACHE_PLD_ERR_CODE_V)<<(EXTMEM_L1_CACHE_PLD_ERR_CODE_S))
-#define EXTMEM_L1_CACHE_PLD_ERR_CODE_V  0x3
-#define EXTMEM_L1_CACHE_PLD_ERR_CODE_S  8
-
-#define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x238)
-/* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl
-y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
-#define EXTMEM_L1_CACHE_SYNC_RST    (BIT(4))
-#define EXTMEM_L1_CACHE_SYNC_RST_M  (BIT(4))
-#define EXTMEM_L1_CACHE_SYNC_RST_V  0x1
-#define EXTMEM_L1_CACHE_SYNC_RST_S  4
-
-#define EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x23C)
-/* EXTMEM_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-only be used to initialize preload-logic when some fatal error of preload-logic
-occurs..*/
-#define EXTMEM_L1_CACHE_PLD_RST    (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_RST_M  (BIT(4))
-#define EXTMEM_L1_CACHE_PLD_RST_V  0x1
-#define EXTMEM_L1_CACHE_PLD_RST_S  4
-
-#define EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x240)
-/* EXTMEM_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au
-toload will not work in L1-Cache. This bit should not be active when autoload wo
-rks in L1-Cache..*/
-#define EXTMEM_L1_CACHE_ALD_BUF_CLR    (BIT(4))
-#define EXTMEM_L1_CACHE_ALD_BUF_CLR_M  (BIT(4))
-#define EXTMEM_L1_CACHE_ALD_BUF_CLR_V  0x1
-#define EXTMEM_L1_CACHE_ALD_BUF_CLR_S  4
-
-#define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_EXTMEM_BASE + 0x244)
-/* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
-llocate request is responsed but not completed..*/
-#define EXTMEM_L1_CACHE_UNALLOC_CLR    (BIT(4))
-#define EXTMEM_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
-#define EXTMEM_L1_CACHE_UNALLOC_CLR_V  0x1
-#define EXTMEM_L1_CACHE_UNALLOC_CLR_S  4
-
-#define EXTMEM_L1_CACHE_OBJECT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x248)
-/* EXTMEM_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi
-th the others fields inside this register..*/
-#define EXTMEM_L1_CACHE_MEM_OBJECT    (BIT(10))
-#define EXTMEM_L1_CACHE_MEM_OBJECT_M  (BIT(10))
-#define EXTMEM_L1_CACHE_MEM_OBJECT_V  0x1
-#define EXTMEM_L1_CACHE_MEM_OBJECT_S  10
-/* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit
-h the others fields inside this register..*/
-#define EXTMEM_L1_CACHE_TAG_OBJECT    (BIT(4))
-#define EXTMEM_L1_CACHE_TAG_OBJECT_M  (BIT(4))
-#define EXTMEM_L1_CACHE_TAG_OBJECT_V  0x1
-#define EXTMEM_L1_CACHE_TAG_OBJECT_S  4
-
-#define EXTMEM_L1_CACHE_WAY_OBJECT_REG          (DR_REG_EXTMEM_BASE + 0x24C)
-/* EXTMEM_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
-: way1, 2: way2, 3: way3, ?, 7: way7..*/
-#define EXTMEM_L1_CACHE_WAY_OBJECT    0x00000007
-#define EXTMEM_L1_CACHE_WAY_OBJECT_M  ((EXTMEM_L1_CACHE_WAY_OBJECT_V)<<(EXTMEM_L1_CACHE_WAY_OBJECT_S))
-#define EXTMEM_L1_CACHE_WAY_OBJECT_V  0x7
-#define EXTMEM_L1_CACHE_WAY_OBJECT_S  0
-
-#define EXTMEM_L1_CACHE_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x250)
-/* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
-/*description: Those bits stores the virtual address which will decide where inside the specifi
-ed tag memory object will be accessed..*/
-#define EXTMEM_L1_CACHE_VADDR    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_VADDR_M  ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S))
-#define EXTMEM_L1_CACHE_VADDR_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_VADDR_S  0
-
-#define EXTMEM_L1_CACHE_DEBUG_BUS_REG          (DR_REG_EXTMEM_BASE + 0x254)
-/* EXTMEM_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */
-/*description: This is a constant place where we can write data to or read data from the tag/da
-ta memory on the specified cache..*/
-#define EXTMEM_L1_CACHE_DEBUG_BUS    0xFFFFFFFF
-#define EXTMEM_L1_CACHE_DEBUG_BUS_M  ((EXTMEM_L1_CACHE_DEBUG_BUS_V)<<(EXTMEM_L1_CACHE_DEBUG_BUS_S))
-#define EXTMEM_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFF
-#define EXTMEM_L1_CACHE_DEBUG_BUS_S  0
-
-#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
-/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */
-/*description: version control register. Note that this default value stored is the latest date
- when the hardware logic was updated..*/
-#define EXTMEM_DATE    0x0FFFFFFF
-#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
-#define EXTMEM_DATE_V  0xFFFFFFF
-#define EXTMEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/extmem_struct.h b/components/soc/esp32c6/include/soc/extmem_struct.h
deleted file mode 100644
index d309e09235e..00000000000
--- a/components/soc/esp32c6/include/soc/extmem_struct.h
+++ /dev/null
@@ -1,5747 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Control and configuration registers */
-/** Type of l1_icache_ctrl register
- *  L1 instruction Cache(L1-ICache) control register
- */
-typedef union {
-    struct {
-        /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus0:1;
-        /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus1:1;
-        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus2:1;
-        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus3:1;
-        /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_undef_op:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_icache_ctrl_reg_t;
-
-/** Type of l1_cache_ctrl register
- *  L1 data Cache(L1-Cache) control register
- */
-typedef union {
-    struct {
-        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus0:1;
-        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus1:1;
-        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus2:1;
-        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus3:1;
-        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_dma:1;
-        uint32_t reserved_5:3;
-        /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_undef_op:4;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l1_cache_ctrl_reg_t;
-
-/** Type of l2_cache_ctrl register
- *  L2 Cache(L2-Cache) control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
-         */
-        uint32_t l2_cache_shut_dma:1;
-        /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_cache_undef_op:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} extmem_l2_cache_ctrl_reg_t;
-
-
-/** Group: Bypass Cache Control and configuration registers */
-/** Type of l1_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache0_en:1;
-        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache1_en:1;
-        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache2_en:1;
-        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache3_en:1;
-        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_dcache_en:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_bypass_cache_conf_reg_t;
-
-/** Type of l2_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l2_cache_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_bypass_cache_conf_reg_t;
-
-
-/** Group: Cache Atomic Control and configuration registers */
-/** Type of l1_cache_atomic_conf register
- *  L1 Cache atomic feature configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
-         *  L1-Cache.  1: disable, 1: enable.
-         */
-        uint32_t l1_cache_atomic_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} extmem_l1_cache_atomic_conf_reg_t;
-
-
-/** Group: Cache Mode Control and configuration registers */
-/** Type of l1_icache_cachesize_conf register
- *  L1 instruction Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1k:1;
-        /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2k:1;
-        /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4k:1;
-        /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_8k:1;
-        /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_16k:1;
-        /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_32k:1;
-        /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_64k:1;
-        /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_128k:1;
-        /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_256k:1;
-        /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_512k:1;
-        /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1024k:1;
-        /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2048k:1;
-        /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l1_icache_cachesize_conf_reg_t;
-
-/** Type of l1_icache_blocksize_conf register
- *  L1 instruction Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_8:1;
-        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_16:1;
-        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_32:1;
-        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_64:1;
-        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_128:1;
-        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache_blocksize_conf_reg_t;
-
-/** Type of l1_cache_cachesize_conf register
- *  L1 data Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1k:1;
-        /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2k:1;
-        /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4k:1;
-        /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_8k:1;
-        /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_16k:1;
-        /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1;
-         *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_32k:1;
-        /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_64k:1;
-        /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_128k:1;
-        /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_256k:1;
-        /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_512k:1;
-        /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1024k:1;
-        /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2048k:1;
-        /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l1_cache_cachesize_conf_reg_t;
-
-/** Type of l1_cache_blocksize_conf register
- *  L1 data Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_8:1;
-        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_16:1;
-        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
-         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_32:1;
-        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_64:1;
-        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_128:1;
-        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_cache_blocksize_conf_reg_t;
-
-/** Type of l2_cache_cachesize_conf register
- *  L2 Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1k:1;
-        /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2k:1;
-        /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4k:1;
-        /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_8k:1;
-        /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_16k:1;
-        /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_32k:1;
-        /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_64k:1;
-        /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_128k:1;
-        /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_256k:1;
-        /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_512k:1;
-        /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1024k:1;
-        /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2048k:1;
-        /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_cachesize_conf_reg_t;
-
-/** Type of l2_cache_blocksize_conf register
- *  L2 Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_8:1;
-        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_16:1;
-        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_32:1;
-        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_64:1;
-        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_128:1;
-        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_blocksize_conf_reg_t;
-
-
-/** Group: Wrap Mode Control and configuration registers */
-/** Type of l1_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
-         */
-        uint32_t l1_icache0_wrap:1;
-        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
-         */
-        uint32_t l1_icache1_wrap:1;
-        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_wrap:1;
-        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_wrap:1;
-        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
-         *  Set this bit as 1 to enable L1-DCache wrap around mode.
-         */
-        uint32_t l1_cache_wrap:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_wrap_around_ctrl_reg_t;
-
-/** Type of l2_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
-         *  Set this bit as 1 to enable L2-Cache wrap around mode.
-         */
-        uint32_t l2_cache_wrap:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_wrap_around_ctrl_reg_t;
-
-
-/** Group: Cache Tag Memory Power Control registers */
-/** Type of l1_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache0_tag_mem_force_on:1;
-        /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache0_tag_mem_force_pd:1;
-        /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1;
-         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache0_tag_mem_force_pu:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache1_tag_mem_force_on:1;
-        /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache1_tag_mem_force_pd:1;
-        /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1;
-         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache1_tag_mem_force_pu:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_on:1;
-        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_pd:1;
-        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_pu:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_on:1;
-        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_pd:1;
-        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_pu:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_tag_mem_force_on:1;
-        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l1_cache_tag_mem_force_pd:1;
-        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_tag_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_tag_mem_power_ctrl_reg_t;
-
-/** Type of l2_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l2_cache_tag_mem_force_on:1;
-        /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l2_cache_tag_mem_force_pd:1;
-        /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0;
-         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l2_cache_tag_mem_force_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_tag_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Power Control registers */
-/** Type of l1_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache0_data_mem_force_on:1;
-        /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache0_data_mem_force_pd:1;
-        /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1;
-         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache0_data_mem_force_pu:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache1_data_mem_force_on:1;
-        /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache1_data_mem_force_pd:1;
-        /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1;
-         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache1_data_mem_force_pu:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_on:1;
-        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_pd:1;
-        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_pu:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_on:1;
-        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_pd:1;
-        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_pu:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_data_mem_force_on:1;
-        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_cache_data_mem_force_pd:1;
-        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_data_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_data_mem_power_ctrl_reg_t;
-
-/** Type of l2_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l2_cache_data_mem_force_on:1;
-        /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l2_cache_data_mem_force_pd:1;
-        /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0;
-         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l2_cache_data_mem_force_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_data_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Freeze Control registers */
-/** Type of l1_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache0_freeze_en:1;
-        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache0_freeze_mode:1;
-        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_freeze_done:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache1_freeze_en:1;
-        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache1_freeze_mode:1;
-        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_freeze_done:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_en:1;
-        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_mode:1;
-        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_done:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_en:1;
-        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_mode:1;
-        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_done:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
-         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_cache_freeze_en:1;
-        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_cache_freeze_mode:1;
-        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_freeze_done:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_freeze_ctrl_reg_t;
-
-/** Type of l2_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l2_cache_freeze_en:1;
-        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l2_cache_freeze_mode:1;
-        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_freeze_done:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_freeze_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Access Control and Configuration registers */
-/** Type of l1_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_data_mem_rd_en:1;
-        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache0_data_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_data_mem_rd_en:1;
-        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache1_data_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_rd_en:1;
-        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_rd_en:1;
-        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_rd_en:1;
-        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} extmem_l1_cache_data_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_rd_en:1;
-        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} extmem_l2_cache_data_mem_acs_conf_reg_t;
-
-
-/** Group: Cache Tag Memory Access Control and Configuration registers */
-/** Type of l1_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_rd_en:1;
-        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_rd_en:1;
-        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_rd_en:1;
-        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_rd_en:1;
-        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_rd_en:1;
-        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} extmem_l1_cache_tag_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_rd_en:1;
-        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} extmem_l2_cache_tag_mem_acs_conf_reg_t;
-
-
-/** Group: Prelock Control and configuration registers */
-/** Type of l1_icache0_prelock_conf register
- *  L1 instruction Cache 0 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct0_en:1;
-        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct1_en:1;
-        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 prelock.
-         */
-        uint32_t l1_icache0_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_conf_reg_t;
-
-/** Type of l1_icache0_prelock_sct0_addr register
- *  L1 instruction Cache 0 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache0, which should be used together with
-         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct1_addr register
- *  L1 instruction Cache 0 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache0, which should be used together with
-         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct_size register
- *  L1 instruction Cache 0 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct_size_reg_t;
-
-/** Type of l1_icache1_prelock_conf register
- *  L1 instruction Cache 1 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct0_en:1;
-        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct1_en:1;
-        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 prelock.
-         */
-        uint32_t l1_icache1_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_conf_reg_t;
-
-/** Type of l1_icache1_prelock_sct0_addr register
- *  L1 instruction Cache 1 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache1, which should be used together with
-         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct1_addr register
- *  L1 instruction Cache 1 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache1, which should be used together with
-         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct_size register
- *  L1 instruction Cache 1 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct_size_reg_t;
-
-/** Type of l1_icache2_prelock_conf register
- *  L1 instruction Cache 2 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct0_en:1;
-        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct1_en:1;
-        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 prelock.
-         */
-        uint32_t l1_icache2_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_conf_reg_t;
-
-/** Type of l1_icache2_prelock_sct0_addr register
- *  L1 instruction Cache 2 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache2, which should be used together with
-         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct1_addr register
- *  L1 instruction Cache 2 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache2, which should be used together with
-         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct_size register
- *  L1 instruction Cache 2 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct_size_reg_t;
-
-/** Type of l1_icache3_prelock_conf register
- *  L1 instruction Cache 3 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct0_en:1;
-        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct1_en:1;
-        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 prelock.
-         */
-        uint32_t l1_icache3_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_conf_reg_t;
-
-/** Type of l1_icache3_prelock_sct0_addr register
- *  L1 instruction Cache 3 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache3, which should be used together with
-         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct1_addr register
- *  L1 instruction Cache 3 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache3, which should be used together with
-         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct_size register
- *  L1 instruction Cache 3 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct_size_reg_t;
-
-/** Type of l1_cache_prelock_conf register
- *  L1 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct0_en:1;
-        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct1_en:1;
-        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 cache prelock.
-         */
-        uint32_t l1_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_cache_prelock_conf_reg_t;
-
-/** Type of l1_cache_prelock_sct0_addr register
- *  L1 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct1_addr register
- *  L1 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_prelock_sct1_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct_size register
- *  L1  Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_dcache_prelock_sct_size_reg_t;
-
-/** Type of l2_cache_prelock_conf register
- *  L2 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct0_en:1;
-        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct1_en:1;
-        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l2 cache prelock.
-         */
-        uint32_t l2_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_conf_reg_t;
-
-/** Type of l2_cache_prelock_sct0_addr register
- *  L2 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L2-Cache, which should be used together with
-         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct1_addr register
- *  L2 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L2-Cache, which should be used together with
-         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct1_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct_size register
- *  L2 Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct0_size:16;
-        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct1_size:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct_size_reg_t;
-
-
-/** Group: Lock Control and configuration registers */
-/** Type of cache_lock_ctrl register
- *  Lock-class (manual lock) operation control register
- */
-typedef union {
-    struct {
-        /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
-         *  operation done
-         */
-        uint32_t cache_lock_ena:1;
-        /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable unlock operation. It will be cleared by hardware after
-         *  unlock operation done
-         */
-        uint32_t cache_unlock_ena:1;
-        /** cache_lock_done : RO; bitpos: [2]; default: 1;
-         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
-         *  not finished. 1: finished.
-         */
-        uint32_t cache_lock_done:1;
-        /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of cache lock/unlock.
-         */
-        uint32_t cache_lock_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_cache_lock_ctrl_reg_t;
-
-/** Type of cache_lock_map register
- *  Lock (manual lock) map configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_map : R/W; bitpos: [5:0]; default: 0;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply this lock/unlock operation. [4]: L1-Cache
-         */
-        uint32_t cache_lock_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_cache_lock_map_reg_t;
-
-/** Type of cache_lock_addr register
- *  Lock (manual lock) address configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the lock/unlock
-         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
-         */
-        uint32_t cache_lock_addr:32;
-    };
-    uint32_t val;
-} extmem_cache_lock_addr_reg_t;
-
-/** Type of cache_lock_size register
- *  Lock (manual lock) size configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_size : R/W; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the lock/unlock operation, which
-         *  should be used together with CACHE_LOCK_ADDR_REG
-         */
-        uint32_t cache_lock_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_cache_lock_size_reg_t;
-
-
-/** Group: Sync Control and configuration registers */
-/** Type of cache_sync_ctrl register
- *  Sync-class operation control register
- */
-typedef union {
-    struct {
-        /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
-         *  The bit is used to enable invalidate operation. It will be cleared by hardware
-         *  after invalidate operation done. Note that this bit and the other sync-bits
-         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_invalidate_ena:1;
-        /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable clean operation. It will be cleared by hardware after
-         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
-         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
-         *  bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_clean_ena:1;
-        /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0;
-         *  The bit is used to enable writeback operation. It will be cleared by hardware after
-         *  writeback operation done. Note that this bit and the other sync-bits
-         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_writeback_ena:1;
-        /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
-         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
-         *  hardware after writeback-invalidate operation done. Note that this bit and the
-         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
-         *  that is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_writeback_invalidate_ena:1;
-        /** cache_sync_done : RO; bitpos: [4]; default: 0;
-         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
-         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
-         */
-        uint32_t cache_sync_done:1;
-        /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0;
-         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
-         *  writeback, writeback_invalidate)
-         */
-        uint32_t cache_sync_rgid:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} extmem_cache_sync_ctrl_reg_t;
-
-/** Type of cache_sync_map register
- *  Sync map configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_map : R/W; bitpos: [5:0]; default: 63;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply the sync operation.  [4]: L1-Cache
-         */
-        uint32_t cache_sync_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_cache_sync_map_reg_t;
-
-/** Type of cache_sync_addr register
- *  Sync address configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the sync operation,
-         *  which should be used together with CACHE_SYNC_SIZE_REG
-         */
-        uint32_t cache_sync_addr:32;
-    };
-    uint32_t val;
-} extmem_cache_sync_addr_reg_t;
-
-/** Type of cache_sync_size register
- *  Sync size configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the sync operation, which should be
-         *  used together with CACHE_SYNC_ADDR_REG
-         */
-        uint32_t cache_sync_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} extmem_cache_sync_size_reg_t;
-
-
-/** Group: Preload Control and configuration registers */
-/** Type of l1_icache0_preload_ctrl register
- *  L1 instruction Cache 0 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache0_preload_ena:1;
-        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache0_preload_done:1;
-        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache0_preload_order:1;
-        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 preload.
-         */
-        uint32_t l1_icache0_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_ctrl_reg_t;
-
-/** Type of l1_icache0_preload_addr register
- *  L1 instruction Cache 0 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache0_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_addr_reg_t;
-
-/** Type of l1_icache0_preload_size register
- *  L1 instruction Cache 0 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache0_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_size_reg_t;
-
-/** Type of l1_icache1_preload_ctrl register
- *  L1 instruction Cache 1 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache1_preload_ena:1;
-        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache1_preload_done:1;
-        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache1_preload_order:1;
-        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 preload.
-         */
-        uint32_t l1_icache1_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_ctrl_reg_t;
-
-/** Type of l1_icache1_preload_addr register
- *  L1 instruction Cache 1 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache1_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_addr_reg_t;
-
-/** Type of l1_icache1_preload_size register
- *  L1 instruction Cache 1 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache1_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_size_reg_t;
-
-/** Type of l1_icache2_preload_ctrl register
- *  L1 instruction Cache 2 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache2_preload_ena:1;
-        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache2_preload_done:1;
-        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache2_preload_order:1;
-        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 preload.
-         */
-        uint32_t l1_icache2_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_ctrl_reg_t;
-
-/** Type of l1_icache2_preload_addr register
- *  L1 instruction Cache 2 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache2_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_addr_reg_t;
-
-/** Type of l1_icache2_preload_size register
- *  L1 instruction Cache 2 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache2_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_size_reg_t;
-
-/** Type of l1_icache3_preload_ctrl register
- *  L1 instruction Cache 3 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache3_preload_ena:1;
-        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache3_preload_done:1;
-        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache3_preload_order:1;
-        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 preload.
-         */
-        uint32_t l1_icache3_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_ctrl_reg_t;
-
-/** Type of l1_icache3_preload_addr register
- *  L1 instruction Cache 3 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache3_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_addr_reg_t;
-
-/** Type of l1_icache3_preload_size register
- *  L1 instruction Cache 3 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache3_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_size_reg_t;
-
-/** Type of l1_cache_preload_ctrl register
- *  L1 Cache  preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_cache_preload_ena:1;
-        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_cache_preload_done:1;
-        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_cache_preload_order:1;
-        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 cache preload.
-         */
-        uint32_t l1_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_cache_preload_ctrl_reg_t;
-
-/** Type of l1_dcache_preload_addr register
- *  L1 Cache  preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
-         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_cache_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_preload_addr_reg_t;
-
-/** Type of l1_dcache_preload_size register
- *  L1 Cache  preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_cache_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_dcache_preload_size_reg_t;
-
-/** Type of l2_cache_preload_ctrl register
- *  L2 Cache preload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l2_cache_preload_ena:1;
-        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l2_cache_preload_done:1;
-        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l2_cache_preload_order:1;
-        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l2 cache preload.
-         */
-        uint32_t l2_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_ctrl_reg_t;
-
-/** Type of l2_cache_preload_addr register
- *  L2 Cache preload address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
-         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l2_cache_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_addr_reg_t;
-
-/** Type of l2_cache_preload_size register
- *  L2 Cache preload size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l2_cache_preload_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_size_reg_t;
-
-
-/** Group: Autoload Control and configuration registers */
-/** Type of l1_icache0_autoload_ctrl register
- *  L1 instruction Cache 0 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache0_autoload_ena:1;
-        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_autoload_done:1;
-        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache0_autoload_order:1;
-        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache0_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct0_ena:1;
-        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct1_ena:1;
-        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 autoload.
-         */
-        uint32_t l1_icache0_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_ctrl_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_addr register
- *  L1 instruction Cache 0 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_size register
- *  L1 instruction Cache 0 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_addr register
- *  L1 instruction Cache 0 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_size register
- *  L1 instruction Cache 0 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache1_autoload_ctrl register
- *  L1 instruction Cache 1 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache1_autoload_ena:1;
-        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_autoload_done:1;
-        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache1_autoload_order:1;
-        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache1_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct0_ena:1;
-        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct1_ena:1;
-        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 autoload.
-         */
-        uint32_t l1_icache1_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_ctrl_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_addr register
- *  L1 instruction Cache 1 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_size register
- *  L1 instruction Cache 1 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_addr register
- *  L1 instruction Cache 1 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_size register
- *  L1 instruction Cache 1 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache2_autoload_ctrl register
- *  L1 instruction Cache 2 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache2_autoload_ena:1;
-        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache2_autoload_done:1;
-        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache2_autoload_order:1;
-        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache2_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct0_ena:1;
-        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct1_ena:1;
-        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 autoload.
-         */
-        uint32_t l1_icache2_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_ctrl_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_addr register
- *  L1 instruction Cache 2 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_size register
- *  L1 instruction Cache 2 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_addr register
- *  L1 instruction Cache 2 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_size register
- *  L1 instruction Cache 2 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache3_autoload_ctrl register
- *  L1 instruction Cache 3 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache3_autoload_ena:1;
-        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache3_autoload_done:1;
-        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache3_autoload_order:1;
-        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache3_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct0_ena:1;
-        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct1_ena:1;
-        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 autoload.
-         */
-        uint32_t l1_icache3_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_ctrl_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_addr register
- *  L1 instruction Cache 3 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_size register
- *  L1 instruction Cache 3 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_addr register
- *  L1 instruction Cache 3 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_size register
- *  L1 instruction Cache 3 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_ctrl register
- *  L1 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_cache_autoload_ena:1;
-        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_autoload_done:1;
-        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_cache_autoload_order:1;
-        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct0_ena:1;
-        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct1_ena:1;
-        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct2_ena:1;
-        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct3_ena:1;
-        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l1 cache autoload.
-         */
-        uint32_t l1_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_ctrl_reg_t;
-
-/** Type of l1_cache_autoload_sct0_addr register
- *  L1 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct0_size register
- *  L1 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct0_size_reg_t;
-
-/** Type of l1_cache_autoload_sct1_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct1_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_sct2_addr register
- *  L1 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the third section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct2_size register
- *  L1 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct2_size_reg_t;
-
-/** Type of l1_cache_autoload_sct3_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the fourth section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct3_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct3_size_reg_t;
-
-/** Type of l2_cache_autoload_ctrl register
- *  L2 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l2_cache_autoload_ena:1;
-        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_autoload_done:1;
-        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l2_cache_autoload_order:1;
-        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l2_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct0_ena:1;
-        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct1_ena:1;
-        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct2_ena:1;
-        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct3_ena:1;
-        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l2 cache autoload.
-         */
-        uint32_t l2_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_sct0_addr register
- *  L2 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct0_size register
- *  L2 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct0_size_reg_t;
-
-/** Type of l2_cache_autoload_sct1_addr register
- *  L2 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct1_size register
- *  L2 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct1_size_reg_t;
-
-/** Type of l2_cache_autoload_sct2_addr register
- *  L2 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the third section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct2_size register
- *  L2 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct2_size_reg_t;
-
-/** Type of l2_cache_autoload_sct3_addr register
- *  L2 Cache autoload section 3 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the fourth section
-         *  for autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct3_size register
- *  L2 Cache autoload section 3 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct3_size_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of l1_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_ena:1;
-        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_ena:1;
-        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_ena:1;
-        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_ena:1;
-        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_ena:1;
-        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_ena:1;
-        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_ena:1;
-        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_ena:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
-         *  to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_clr:1;
-        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
-         *  to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_clr:1;
-        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_clr:1;
-        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_clr:1;
-        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_clr:1;
-        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_clr:1;
-        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_clr:1;
-        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_clr:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
-         *  due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_raw:1;
-        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
-         *  due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_raw:1;
-        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
-         *  due to bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_ovf_int_raw:1;
-        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
-         *  due to bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_ovf_int_raw:1;
-        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_raw:1;
-        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_raw:1;
-        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_ovf_int_raw:1;
-        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_ovf_int_raw:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_st:1;
-        /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_st:1;
-        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_st:1;
-        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_st:1;
-        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_st:1;
-        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_st:1;
-        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_st:1;
-        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_st:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l1_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_ena:1;
-        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_ena:1;
-        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_ena:1;
-        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_ena:1;
-        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_ena:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l1_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_clr:1;
-        /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_clr:1;
-        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_clr:1;
-        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_clr:1;
-        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l1_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_raw:1;
-        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_raw:1;
-        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
-         */
-        uint32_t l1_icache2_fail_int_raw:1;
-        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
-         */
-        uint32_t l1_icache3_fail_int_raw:1;
-        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_raw:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l1_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_int_st:1;
-        /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_int_st:1;
-        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_st:1;
-        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_st:1;
-        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
-         *  to cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_st:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_st_reg_t;
-
-/** Type of l1_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache0_pld_done_int_ena:1;
-        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache1_pld_done_int_ena:1;
-        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_ena:1;
-        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_ena:1;
-        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_cache_pld_done_int_ena:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation done.
-         */
-        uint32_t cache_sync_done_int_ena:1;
-        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_ena:1;
-        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_ena:1;
-        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_ena:1;
-        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_ena:1;
-        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_ena:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_ena:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l1_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_clr:1;
-        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_clr:1;
-        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_clr:1;
-        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_clr:1;
-        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l1_cache_pld_done_int_clr:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
-         *  done.
-         */
-        uint32_t cache_sync_done_int_clr:1;
-        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_clr:1;
-        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_clr:1;
-        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_clr:1;
-        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_clr:1;
-        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
-         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_clr:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0;
-         *  The bit is used to clear interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_clr:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l1_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache0_pld_done_int_raw:1;
-        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache1_pld_done_int_raw:1;
-        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_raw:1;
-        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_raw:1;
-        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l1_cache_pld_done_int_raw:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
-         */
-        uint32_t cache_sync_done_int_raw:1;
-        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache0_pld_err_int_raw:1;
-        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache1_pld_err_int_raw:1;
-        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_raw:1;
-        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_raw:1;
-        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_err_int_raw:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
-         *  occurs.
-         */
-        uint32_t cache_sync_err_int_raw:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l1_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_st:1;
-        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_st:1;
-        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_st:1;
-        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_st:1;
-        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l1_cache_pld_done_int_st:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when Cache
-         *  sync-operation is done.
-         */
-        uint32_t cache_sync_done_int_st:1;
-        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_st:1;
-        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_st:1;
-        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_st:1;
-        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_st:1;
-        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_st:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0;
-         *  The bit indicates the status of the interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_st:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_st_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_ena:1;
-        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_ena:1;
-        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_ena:1;
-        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_ena:1;
-        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_ena:1;
-        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_ena:1;
-        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_ena:1;
-        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_clr:1;
-        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_clr:1;
-        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_clr:1;
-        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_clr:1;
-        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_clr:1;
-        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_clr:1;
-        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_clr:1;
-        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-ICache0.
-         */
-        uint32_t l2_ibus0_ovf_int_raw:1;
-        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-ICache1.
-         */
-        uint32_t l2_ibus1_ovf_int_raw:1;
-        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-ICache2.
-         */
-        uint32_t l2_ibus2_ovf_int_raw:1;
-        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-ICache3.
-         */
-        uint32_t l2_ibus3_ovf_int_raw:1;
-        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-DCache.
-         */
-        uint32_t l2_dbus0_ovf_int_raw:1;
-        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-DCache.
-         */
-        uint32_t l2_dbus1_ovf_int_raw:1;
-        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-DCache.
-         */
-        uint32_t l2_dbus2_ovf_int_raw:1;
-        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-DCache.
-         */
-        uint32_t l2_dbus3_ovf_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_st:1;
-        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_st:1;
-        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_st:1;
-        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_st:1;
-        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_st:1;
-        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_st:1;
-        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_st:1;
-        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l2_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
-         *  l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l2_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
-         *  cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l2_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l2_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
-         *  to l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_st_reg_t;
-
-/** Type of l2_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
-         */
-        uint32_t l2_cache_pld_done_int_ena:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_ena:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l2_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l2_cache_pld_done_int_clr:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_clr:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l2_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l2_cache_pld_done_int_raw:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_err_int_raw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l2_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l2_cache_pld_done_int_st:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_st:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_st_reg_t;
-
-
-/** Group: Access Statistics registers */
-/** Type of l1_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_ena:1;
-        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_ena:1;
-        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_ena:1;
-        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_ena:1;
-        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_ena:1;
-        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_ena:1;
-        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_ena:1;
-        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_ena:1;
-        uint32_t reserved_8:8;
-        /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0;
-         *  The bit is used to clear ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_clr:1;
-        /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0;
-         *  The bit is used to clear ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_clr:1;
-        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_clr:1;
-        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_clr:1;
-        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
-         *  The bit is used to clear dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_clr:1;
-        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
-         *  The bit is used to clear dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_clr:1;
-        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_clr:1;
-        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_clr:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l1_ibus0_acs_hit_cnt register
- *  L1-ICache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_miss_cnt register
- *  L1-ICache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_conflict_cnt register
- *  L1-ICache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_nxtlvl_cnt register
- *  L1-ICache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l1_ibus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_hit_cnt register
- *  L1-ICache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_miss_cnt register
- *  L1-ICache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_conflict_cnt register
- *  L1-ICache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_nxtlvl_cnt register
- *  L1-ICache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l1_ibus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_hit_cnt register
- *  L1-ICache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_miss_cnt register
- *  L1-ICache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_conflict_cnt register
- *  L1-ICache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_nxtlvl_cnt register
- *  L1-ICache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l1_ibus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_hit_cnt register
- *  L1-ICache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_miss_cnt register
- *  L1-ICache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_conflict_cnt register
- *  L1-ICache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_nxtlvl_cnt register
- *  L1-ICache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l1_ibus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_bus0_acs_hit_cnt register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus0_acs_miss_cnt register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus0_acs_conflict_cnt register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_bus0_acs_nxtlvl_cnt register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus0 accessing L1-Cache.
-         */
-        uint32_t l1_bus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_bus1_acs_hit_cnt register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus1_acs_miss_cnt register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus1_acs_conflict_cnt register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_bus1_acs_nxtlvl_cnt register
- *  L1-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus1 accessing L1-Cache.
-         */
-        uint32_t l1_bus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_hit_cnt register
- *  L1-DCache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_miss_cnt register
- *  L1-DCache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_conflict_cnt register
- *  L1-DCache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_nxtlvl_cnt register
- *  L1-DCache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l1_dbus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_hit_cnt register
- *  L1-DCache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_miss_cnt register
- *  L1-DCache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_conflict_cnt register
- *  L1-DCache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_nxtlvl_cnt register
- *  L1-DCache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l1_dbus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_ena:1;
-        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_ena:1;
-        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_ena:1;
-        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_ena:1;
-        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_ena:1;
-        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_ena:1;
-        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_ena:1;
-        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_ena:1;
-        uint32_t reserved_16:8;
-        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
-         *  The bit is used to clear ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_clr:1;
-        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
-         *  The bit is used to clear ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_clr:1;
-        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_clr:1;
-        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_clr:1;
-        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
-         *  The bit is used to clear dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_clr:1;
-        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
-         *  The bit is used to clear dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_clr:1;
-        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_clr:1;
-        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_clr:1;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l2_ibus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache0 accesses
-         *  L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_nxtlvl_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache1 accesses
-         *  L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_nxtlvl_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache2 accesses
-         *  L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_nxtlvl_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache3 accesses
-         *  L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_nxtlvl_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_nxtlvl_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_nxtlvl_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_nxtlvl_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_nxtlvl_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t;
-
-
-/** Group: Access Fail Debug registers */
-/** Type of l1_icache0_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_id:16;
-        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache0_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache0_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_acs_fail_addr_reg_t;
-
-/** Type of l1_icache1_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_id:16;
-        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache1_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache1_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_acs_fail_addr_reg_t;
-
-/** Type of l1_icache2_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_id:16;
-        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache2_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache2_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_acs_fail_addr_reg_t;
-
-/** Type of l1_icache3_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_id:16;
-        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache3_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache3_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_acs_fail_addr_reg_t;
-
-/** Type of l1_cache_acs_fail_id_attr register
- *  L1-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_id:16;
-        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l1_dcache_acs_fail_addr register
- *  L1-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_acs_fail_addr_reg_t;
-
-/** Type of l2_cache_acs_fail_id_attr register
- *  L2-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_id:16;
-        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
-         *  due to cache accessing L1-Cache.
-         */
-        uint32_t l2_cache_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l2_cache_acs_fail_addr register
- *  L2-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_addr_reg_t;
-
-
-/** Group: Operation Exception registers */
-/** Type of l1_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache0.
-         */
-        uint32_t l1_icache0_pld_err_code:2;
-        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache1.
-         */
-        uint32_t l1_icache1_pld_err_code:2;
-        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_code:2;
-        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_code:2;
-        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-Cache.
-         */
-        uint32_t l1_cache_pld_err_code:2;
-        uint32_t reserved_10:2;
-        /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0;
-         *  The values 0-2 are available which means sync map, command conflict and size are
-         *  error in Cache System.
-         */
-        uint32_t cache_sync_err_code:2;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_exception_reg_t;
-
-/** Type of l2_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:10;
-        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L2-Cache.
-         */
-        uint32_t l2_cache_pld_err_code:2;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_exception_reg_t;
-
-
-/** Group: Sync Reset control and configuration registers */
-/** Type of l1_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache0_sync_rst:1;
-        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache1_sync_rst:1;
-        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_sync_rst:1;
-        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_sync_rst:1;
-        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_cache_sync_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_rst_ctrl_reg_t;
-
-/** Type of l2_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l2_cache_sync_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_rst_ctrl_reg_t;
-
-
-/** Group: Preload Reset control and configuration registers */
-/** Type of l1_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache0_pld_rst:1;
-        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache1_pld_rst:1;
-        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_rst:1;
-        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_rst:1;
-        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_preload_rst_ctrl_reg_t;
-
-/** Type of l2_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_rst_ctrl_reg_t;
-
-
-/** Group: Autoload buffer clear control and configuration registers */
-/** Type of l1_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
-         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
-         *  works in L1-ICache0.
-         */
-        uint32_t l1_icache0_ald_buf_clr:1;
-        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
-         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
-         *  works in L1-ICache1.
-         */
-        uint32_t l1_icache1_ald_buf_clr:1;
-        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_ald_buf_clr:1;
-        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_ald_buf_clr:1;
-        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
-         *  autoload will not work in L1-Cache. This bit should not be active when autoload
-         *  works in L1-Cache.
-         */
-        uint32_t l1_cache_ald_buf_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
-         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
-         *  autoload will not work in L2-Cache. This bit should not be active when autoload
-         *  works in L2-Cache.
-         */
-        uint32_t l2_cache_ald_buf_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t;
-
-
-/** Group: Unallocate request buffer clear registers */
-/** Type of l1_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache0_unalloc_clr:1;
-        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache1_unalloc_clr:1;
-        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_unalloc_clr:1;
-        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_unalloc_clr:1;
-        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_cache_unalloc_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_unallocate_buffer_clear_reg_t;
-
-/** Type of l2_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l2_cache_unalloc_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_unallocate_buffer_clear_reg_t;
-
-
-/** Group: Tag and Data Memory Access Control and configuration register */
-/** Type of l1_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0;
-         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache0_tag_object:1;
-        /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0;
-         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache1_tag_object:1;
-        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_object:1;
-        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_object:1;
-        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_tag_object:1;
-        uint32_t reserved_5:1;
-        /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0;
-         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache0_mem_object:1;
-        /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0;
-         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache1_mem_object:1;
-        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_mem_object:1;
-        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_mem_object:1;
-        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_mem_object:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} extmem_l1_cache_object_ctrl_reg_t;
-
-/** Type of l1_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l1_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} extmem_l1_cache_way_object_reg_t;
-
-/** Type of l1_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l1_cache_vaddr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_vaddr_reg_t;
-
-/** Type of l1_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l1_cache_debug_bus:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_debug_bus_reg_t;
-
-/** Type of l2_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
-         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_tag_object:1;
-        uint32_t reserved_6:5;
-        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
-         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_mem_object:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l2_cache_object_ctrl_reg_t;
-
-/** Type of l2_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l2_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} extmem_l2_cache_way_object_reg_t;
-
-/** Type of l2_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l2_cache_vaddr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_vaddr_reg_t;
-
-/** Type of l2_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l2_cache_debug_bus:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_debug_bus_reg_t;
-
-
-/** Group: Split L1 and L2 registers */
-/** Type of level_split0 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split0 : HRO; bitpos: [31:0]; default: 600;
-         *  Reserved
-         */
-        uint32_t level_split0:32;
-    };
-    uint32_t val;
-} extmem_level_split0_reg_t;
-
-/** Type of level_split1 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split1 : HRO; bitpos: [31:0]; default: 936;
-         *  Reserved
-         */
-        uint32_t level_split1:32;
-    };
-    uint32_t val;
-} extmem_level_split1_reg_t;
-
-
-/** Group: L2 cache access attribute control register */
-/** Type of l2_cache_access_attr_ctrl register
- *  L1 Cache access Attribute propagation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
-         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
-         *  non-cacheable.
-         */
-        uint32_t l2_cache_access_force_cc:1;
-        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
-         *  write-through.
-         */
-        uint32_t l2_cache_access_force_wb:1;
-        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  write-miss-allocate and write-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_wma:1;
-        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
-         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  read-miss-allocate and read-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_rma:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} extmem_l2_cache_access_attr_ctrl_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  The bit is used to enable clock gate when access all registers in this module.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} extmem_clock_gate_reg_t;
-
-
-/** Group: Redundancy  register (Prepare for ECO) */
-/** Type of redundancy_sig0 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig0:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig0_reg_t;
-
-/** Type of redundancy_sig1 register
- *  Cache redundancy signal 1 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig1:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig1_reg_t;
-
-/** Type of redundancy_sig2 register
- *  Cache redundancy signal 2 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig2:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig2_reg_t;
-
-/** Type of redundancy_sig3 register
- *  Cache redundancy signal 3 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig3:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig3_reg_t;
-
-/** Type of redundancy_sig4 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig4:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} extmem_redundancy_sig4_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35659904;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_date_reg_t;
-
-
-typedef struct extmem_dev_s {
-    volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl;
-    volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl;
-    volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
-    volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
-    volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
-    volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
-    volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
-    volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
-    volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
-    volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
-    volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
-    volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
-    volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
-    volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
-    volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
-    volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
-    volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
-    volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
-    volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
-    volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
-    volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
-    volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
-    volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
-    volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
-    volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
-    volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
-    volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
-    volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
-    volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
-    volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
-    volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
-    volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
-    volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
-    volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
-    volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl;
-    volatile extmem_cache_lock_map_reg_t cache_lock_map;
-    volatile extmem_cache_lock_addr_reg_t cache_lock_addr;
-    volatile extmem_cache_lock_size_reg_t cache_lock_size;
-    volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl;
-    volatile extmem_cache_sync_map_reg_t cache_sync_map;
-    volatile extmem_cache_sync_addr_reg_t cache_sync_addr;
-    volatile extmem_cache_sync_size_reg_t cache_sync_size;
-    volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
-    volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
-    volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
-    volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
-    volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
-    volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
-    volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
-    volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
-    volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
-    volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
-    volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
-    volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
-    volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
-    volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
-    volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
-    volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
-    volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
-    volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
-    volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
-    volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
-    volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
-    volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
-    volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
-    volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
-    volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
-    volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
-    volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
-    volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
-    volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
-    volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
-    volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
-    volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
-    volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
-    volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
-    volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
-    volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
-    volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
-    volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
-    volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
-    volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
-    volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
-    volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
-    volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
-    volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
-    volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
-    volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
-    volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
-    volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
-    volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
-    volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
-    volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
-    volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
-    volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
-    volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
-    volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
-    volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
-    volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
-    volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
-    volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
-    volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
-    volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
-    volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
-    volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
-    volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
-    volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
-    volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt;
-    volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
-    volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
-    volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
-    volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt;
-    volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
-    volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
-    volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
-    volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt;
-    volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
-    volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
-    volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
-    volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt;
-    volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
-    volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
-    volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
-    volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt;
-    volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
-    volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
-    volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
-    volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
-    volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
-    volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
-    volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
-    volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
-    volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr;
-    volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
-    volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
-    volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
-    volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
-    volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
-    volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
-    volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
-    volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
-    volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
-    volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
-    volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
-    volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object;
-    volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr;
-    volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
-    volatile extmem_level_split0_reg_t level_split0;
-    volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl;
-    volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
-    volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
-    volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
-    volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
-    volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
-    volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
-    volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
-    volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
-    volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
-    volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
-    volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
-    volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
-    volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
-    volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
-    volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
-    volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size;
-    volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
-    volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
-    volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
-    volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
-    volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
-    volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
-    volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
-    volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
-    volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
-    volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
-    volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
-    volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
-    volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
-    volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
-    volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
-    volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
-    volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
-    volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
-    volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
-    volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
-    volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
-    volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
-    volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
-    volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
-    volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
-    volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
-    volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
-    volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
-    volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
-    volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
-    volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
-    volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
-    volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
-    volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
-    volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
-    volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
-    volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
-    volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
-    volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
-    volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
-    volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
-    volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
-    volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt;
-    volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
-    volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
-    volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
-    volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
-    volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
-    volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
-    volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
-    volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
-    volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
-    volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
-    volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
-    volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
-    volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
-    volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object;
-    volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr;
-    volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
-    volatile extmem_level_split1_reg_t level_split1;
-    volatile extmem_clock_gate_reg_t clock_gate;
-    volatile extmem_redundancy_sig0_reg_t redundancy_sig0;
-    volatile extmem_redundancy_sig1_reg_t redundancy_sig1;
-    volatile extmem_redundancy_sig2_reg_t redundancy_sig2;
-    volatile extmem_redundancy_sig3_reg_t redundancy_sig3;
-    volatile extmem_redundancy_sig4_reg_t redundancy_sig4;
-    uint32_t reserved_3c4[14];
-    volatile extmem_date_reg_t date;
-} extmem_dev_t;
-
-extern extmem_dev_t EXTMEM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/hp_system_reg.h b/components/soc/esp32c6/include/soc/hp_system_reg.h
deleted file mode 100644
index 898d0fb0e59..00000000000
--- a/components/soc/esp32c6/include/soc/hp_system_reg.h
+++ /dev/null
@@ -1,415 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
- *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
- */
-#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
-/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
- */
-#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
-#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
-#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
-/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
- *  reserved
- */
-#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
-#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
-#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
-/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
- *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
- */
-#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
-#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
-#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
-#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
-/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
- *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
- */
-#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
-#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
-
-/** HP_SYSTEM_SRAM_USAGE_CONF_REG register
- *  HP memory usage configuration register
- */
-#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
-/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
- *  reserved
- */
-#define HP_SYSTEM_CACHE_USAGE    (BIT(0))
-#define HP_SYSTEM_CACHE_USAGE_M  (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
-#define HP_SYSTEM_CACHE_USAGE_V  0x00000001U
-#define HP_SYSTEM_CACHE_USAGE_S  0
-/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0;
- *  0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
- */
-#define HP_SYSTEM_SRAM_USAGE    0x0000000FU
-#define HP_SYSTEM_SRAM_USAGE_M  (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S)
-#define HP_SYSTEM_SRAM_USAGE_V  0x0000000FU
-#define HP_SYSTEM_SRAM_USAGE_S  8
-/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0;
- *  Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
- */
-#define HP_SYSTEM_MAC_DUMP_ALLOC    (BIT(16))
-#define HP_SYSTEM_MAC_DUMP_ALLOC_M  (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S)
-#define HP_SYSTEM_MAC_DUMP_ALLOC_V  0x00000001U
-#define HP_SYSTEM_MAC_DUMP_ALLOC_S  16
-
-/** HP_SYSTEM_SEC_DPA_CONF_REG register
- *  HP anti-DPA security configuration register
- */
-#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
-/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
- *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
- *  the number, the stronger the ability to resist DPA attacks and the higher the
- *  security level, but it will increase the computational overhead of the hardware
- *  crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
- */
-#define HP_SYSTEM_SEC_DPA_LEVEL    0x00000003U
-#define HP_SYSTEM_SEC_DPA_LEVEL_M  (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
-#define HP_SYSTEM_SEC_DPA_LEVEL_V  0x00000003U
-#define HP_SYSTEM_SEC_DPA_LEVEL_S  0
-/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
- *  This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
- *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
- */
-#define HP_SYSTEM_SEC_DPA_CFG_SEL    (BIT(2))
-#define HP_SYSTEM_SEC_DPA_CFG_SEL_M  (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
-#define HP_SYSTEM_SEC_DPA_CFG_SEL_V  0x00000001U
-#define HP_SYSTEM_SEC_DPA_CFG_SEL_S  2
-
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
- *  CPU_PERI_TIMEOUT configuration register
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc)
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
- *  Set the timeout threshold for bus access, corresponding to the number of clock
- *  cycles of the clock domain.
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S  0
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
- *  Set this bit as 1 to clear timeout interrupt
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S  16
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
- *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
- *  registers
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S  17
-
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
- *  CPU_PERI_TIMEOUT_ADDR register
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10)
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Record the address information of abnormal access
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S  0
-
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
- *  CPU_PERI_TIMEOUT_UID register
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14)
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
- *  will be cleared after the interrupt is cleared.
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID    0x0000007FU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V  0x0000007FU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S  0
-
-/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
- *  HP_PERI_TIMEOUT configuration register
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18)
-/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
- *  Set the timeout threshold for bus access, corresponding to the number of clock
- *  cycles of the clock domain.
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S  0
-/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
- *  Set this bit as 1 to clear timeout interrupt
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
-#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S  16
-/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
- *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
-#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S  17
-
-/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
- *  HP_PERI_TIMEOUT_ADDR register
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c)
-/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Record the address information of abnormal access
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S  0
-
-/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
- *  HP_PERI_TIMEOUT_UID register
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20)
-/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
- *  will be cleared after the interrupt is cleared.
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID    0x0000007FU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M  (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V  0x0000007FU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S  0
-
-/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register
- *  MODEM_PERI_TIMEOUT configuration register
- */
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
-/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
- *  Set the timeout threshold for bus access, corresponding to the number of clock
- *  cycles of the clock domain.
- */
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S)
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S  0
-/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
- *  Set this bit as 1 to clear timeout interrupt
- */
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S  16
-/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
- *  Set this bit as 1 to enable timeout protection for accessing modem registers
- */
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S  17
-
-/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register
- *  MODEM_PERI_TIMEOUT_ADDR register
- */
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
-/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Record the address information of abnormal access
- */
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S)
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S  0
-
-/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register
- *  MODEM_PERI_TIMEOUT_UID register
- */
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
-/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
- *  will be cleared after the interrupt is cleared.
- */
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID    0x0000007FU
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S)
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V  0x0000007FU
-#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S  0
-
-/** HP_SYSTEM_SDIO_CTRL_REG register
- *  SDIO Control configuration register
- */
-#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x30)
-/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
- *  Set this bit as 1 to disable SDIO_PROB function. disable by default.
- */
-#define HP_SYSTEM_DIS_SDIO_PROB    (BIT(0))
-#define HP_SYSTEM_DIS_SDIO_PROB_M  (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S)
-#define HP_SYSTEM_DIS_SDIO_PROB_V  0x00000001U
-#define HP_SYSTEM_DIS_SDIO_PROB_S  0
-/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
- *  Enable sdio slave to access other peripherals on the chip
- */
-#define HP_SYSTEM_SDIO_WIN_ACCESS_EN    (BIT(1))
-#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M  (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S)
-#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V  0x00000001U
-#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S  1
-
-/** HP_SYSTEM_RETENTION_CONF_REG register
- *  Retention configuration register
- */
-#define HP_SYSTEM_RETENTION_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x34)
-/** HP_SYSTEM_RETENTION_DISABLE : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to disable retention function. Not disable by default.
- */
-#define HP_SYSTEM_RETENTION_DISABLE    (BIT(0))
-#define HP_SYSTEM_RETENTION_DISABLE_M  (HP_SYSTEM_RETENTION_DISABLE_V << HP_SYSTEM_RETENTION_DISABLE_S)
-#define HP_SYSTEM_RETENTION_DISABLE_V  0x00000001U
-#define HP_SYSTEM_RETENTION_DISABLE_S  0
-
-/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
- *  Rom-Table lock register
- */
-#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x38)
-/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
- *  XXXX
- */
-#define HP_SYSTEM_ROM_TABLE_LOCK    (BIT(0))
-#define HP_SYSTEM_ROM_TABLE_LOCK_M  (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
-#define HP_SYSTEM_ROM_TABLE_LOCK_V  0x00000001U
-#define HP_SYSTEM_ROM_TABLE_LOCK_S  0
-
-/** HP_SYSTEM_ROM_TABLE_REG register
- *  Rom-Table register
- */
-#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x3c)
-/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
- *  XXXX
- */
-#define HP_SYSTEM_ROM_TABLE    0xFFFFFFFFU
-#define HP_SYSTEM_ROM_TABLE_M  (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
-#define HP_SYSTEM_ROM_TABLE_V  0xFFFFFFFFU
-#define HP_SYSTEM_ROM_TABLE_S  0
-
-/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
- *  Core Debug runstall configure register
- */
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x40)
-/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
- */
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S  0
-
-/** HP_SYSTEM_MEM_TEST_CONF_REG register
- *  MEM_TEST configuration register
- */
-#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x44)
-/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
- *  This field controls hp system memory WPULSE parameter.
- */
-#define HP_SYSTEM_HP_MEM_WPULSE    0x00000007U
-#define HP_SYSTEM_HP_MEM_WPULSE_M  (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S)
-#define HP_SYSTEM_HP_MEM_WPULSE_V  0x00000007U
-#define HP_SYSTEM_HP_MEM_WPULSE_S  0
-/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4;
- *  This field controls hp system memory WA parameter.
- */
-#define HP_SYSTEM_HP_MEM_WA    0x00000007U
-#define HP_SYSTEM_HP_MEM_WA_M  (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S)
-#define HP_SYSTEM_HP_MEM_WA_V  0x00000007U
-#define HP_SYSTEM_HP_MEM_WA_S  3
-/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
- *  This field controls hp system memory RA parameter.
- */
-#define HP_SYSTEM_HP_MEM_RA    0x00000003U
-#define HP_SYSTEM_HP_MEM_RA_M  (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S)
-#define HP_SYSTEM_HP_MEM_RA_V  0x00000003U
-#define HP_SYSTEM_HP_MEM_RA_S  6
-
-/** HP_SYSTEM_RND_ECO_REG register
- *  redcy eco register.
- */
-#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0)
-/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYSTEM_REDCY_ENA    (BIT(0))
-#define HP_SYSTEM_REDCY_ENA_M  (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
-#define HP_SYSTEM_REDCY_ENA_V  0x00000001U
-#define HP_SYSTEM_REDCY_ENA_S  0
-/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYSTEM_REDCY_RESULT    (BIT(1))
-#define HP_SYSTEM_REDCY_RESULT_M  (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
-#define HP_SYSTEM_REDCY_RESULT_V  0x00000001U
-#define HP_SYSTEM_REDCY_RESULT_S  1
-
-/** HP_SYSTEM_RND_ECO_LOW_REG register
- *  redcy eco low register.
- */
-#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4)
-/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYSTEM_REDCY_LOW    0xFFFFFFFFU
-#define HP_SYSTEM_REDCY_LOW_M  (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
-#define HP_SYSTEM_REDCY_LOW_V  0xFFFFFFFFU
-#define HP_SYSTEM_REDCY_LOW_S  0
-
-/** HP_SYSTEM_RND_ECO_HIGH_REG register
- *  redcy eco high register.
- */
-#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8)
-/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
- *  Only reserved for ECO.
- */
-#define HP_SYSTEM_REDCY_HIGH    0xFFFFFFFFU
-#define HP_SYSTEM_REDCY_HIGH_M  (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
-#define HP_SYSTEM_REDCY_HIGH_V  0xFFFFFFFFU
-#define HP_SYSTEM_REDCY_HIGH_S  0
-
-/** HP_SYSTEM_CLOCK_GATE_REG register
- *  HP-SYSTEM clock gating configure register
- */
-#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8)
-/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to force on clock gating.
- */
-#define HP_SYSTEM_CLK_EN    (BIT(0))
-#define HP_SYSTEM_CLK_EN_M  (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)
-#define HP_SYSTEM_CLK_EN_V  0x00000001U
-#define HP_SYSTEM_CLK_EN_S  0
-
-/** HP_SYSTEM_DATE_REG register
- *  Date register.
- */
-#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
-/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 35676432;
- *  HP-SYSTEM date information/ HP-SYSTEM version information.
- */
-#define HP_SYSTEM_DATE    0x0FFFFFFFU
-#define HP_SYSTEM_DATE_M  (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
-#define HP_SYSTEM_DATE_V  0x0FFFFFFFU
-#define HP_SYSTEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/hp_system_struct.h b/components/soc/esp32c6/include/soc/hp_system_struct.h
deleted file mode 100644
index b174aa4290a..00000000000
--- a/components/soc/esp32c6/include/soc/hp_system_struct.h
+++ /dev/null
@@ -1,450 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of external_device_encrypt_decrypt_control register
- *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
- */
-typedef union {
-    struct {
-        /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
-         */
-        uint32_t enable_spi_manual_encrypt:1;
-        /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t enable_download_db_encrypt:1;
-        /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
-         *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
-         */
-        uint32_t enable_download_g0cb_decrypt:1;
-        /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
-         *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
-         */
-        uint32_t enable_download_manual_encrypt:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_system_external_device_encrypt_decrypt_control_reg_t;
-
-/** Type of sram_usage_conf register
- *  HP memory usage configuration register
- */
-typedef union {
-    struct {
-        /** cache_usage : HRO; bitpos: [0]; default: 0;
-         *  reserved
-         */
-        uint32_t cache_usage:1;
-        uint32_t reserved_1:7;
-        /** sram_usage : R/W; bitpos: [11:8]; default: 0;
-         *  0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
-         */
-        uint32_t sram_usage:4;
-        uint32_t reserved_12:4;
-        /** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
-         */
-        uint32_t mac_dump_alloc:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} hp_system_sram_usage_conf_reg_t;
-
-/** Type of sec_dpa_conf register
- *  HP anti-DPA security configuration register
- */
-typedef union {
-    struct {
-        /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
-         *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
-         *  the number, the stronger the ability to resist DPA attacks and the higher the
-         *  security level, but it will increase the computational overhead of the hardware
-         *  crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
-         */
-        uint32_t sec_dpa_level:2;
-        /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
-         *  This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
-         *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
-         */
-        uint32_t sec_dpa_cfg_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_sec_dpa_conf_reg_t;
-
-/** Type of sdio_ctrl register
- *  SDIO Control configuration register
- */
-typedef union {
-    struct {
-        /** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
-         *  Set this bit as 1 to disable SDIO_PROB function. disable by default.
-         */
-        uint32_t dis_sdio_prob:1;
-        /** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
-         *  Enable sdio slave to access other peripherals on the chip
-         */
-        uint32_t sdio_win_access_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_sdio_ctrl_reg_t;
-
-/** Type of retention_conf register
- *  Retention configuration register
- */
-typedef union {
-    struct {
-        /** retention_disable : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to disable retention function. Not disable by default.
-         */
-        uint32_t retention_disable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_retention_conf_reg_t;
-
-/** Type of rom_table_lock register
- *  Rom-Table lock register
- */
-typedef union {
-    struct {
-        /** rom_table_lock : R/W; bitpos: [0]; default: 0;
-         *  XXXX
-         */
-        uint32_t rom_table_lock:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_rom_table_lock_reg_t;
-
-/** Type of rom_table register
- *  Rom-Table register
- */
-typedef union {
-    struct {
-        /** rom_table : R/W; bitpos: [31:0]; default: 0;
-         *  XXXX
-         */
-        uint32_t rom_table:32;
-    };
-    uint32_t val;
-} hp_system_rom_table_reg_t;
-
-/** Type of core_debug_runstall_conf register
- *  Core Debug runstall configure register
- */
-typedef union {
-    struct {
-        /** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
-         *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
-         */
-        uint32_t core_debug_runstall_enable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_core_debug_runstall_conf_reg_t;
-
-/** Type of mem_test_conf register
- *  MEM_TEST configuration register
- */
-typedef union {
-    struct {
-        /** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
-         *  This field controls hp system memory WPULSE parameter.
-         */
-        uint32_t hp_mem_wpulse:3;
-        /** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
-         *  This field controls hp system memory WA parameter.
-         */
-        uint32_t hp_mem_wa:3;
-        /** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
-         *  This field controls hp system memory RA parameter.
-         */
-        uint32_t hp_mem_ra:2;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} hp_system_mem_test_conf_reg_t;
-
-/** Type of clock_gate register
- *  HP-SYSTEM clock gating configure register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to force on clock gating.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_clock_gate_reg_t;
-
-
-/** Group: Timeout Register */
-/** Type of cpu_peri_timeout_conf register
- *  CPU_PERI_TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
-         *  Set the timeout threshold for bus access, corresponding to the number of clock
-         *  cycles of the clock domain.
-         */
-        uint32_t cpu_peri_timeout_thres:16;
-        /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to clear timeout interrupt
-         */
-        uint32_t cpu_peri_timeout_int_clear:1;
-        /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
-         *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
-         *  registers
-         */
-        uint32_t cpu_peri_timeout_protect_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} hp_system_cpu_peri_timeout_conf_reg_t;
-
-/** Type of cpu_peri_timeout_addr register
- *  CPU_PERI_TIMEOUT_ADDR register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  Record the address information of abnormal access
-         */
-        uint32_t cpu_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} hp_system_cpu_peri_timeout_addr_reg_t;
-
-/** Type of cpu_peri_timeout_uid register
- *  CPU_PERI_TIMEOUT_UID register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
-         *  will be cleared after the interrupt is cleared.
-         */
-        uint32_t cpu_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hp_system_cpu_peri_timeout_uid_reg_t;
-
-/** Type of hp_peri_timeout_conf register
- *  HP_PERI_TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
-         *  Set the timeout threshold for bus access, corresponding to the number of clock
-         *  cycles of the clock domain.
-         */
-        uint32_t hp_peri_timeout_thres:16;
-        /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to clear timeout interrupt
-         */
-        uint32_t hp_peri_timeout_int_clear:1;
-        /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
-         *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
-         */
-        uint32_t hp_peri_timeout_protect_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} hp_system_hp_peri_timeout_conf_reg_t;
-
-/** Type of hp_peri_timeout_addr register
- *  HP_PERI_TIMEOUT_ADDR register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  Record the address information of abnormal access
-         */
-        uint32_t hp_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} hp_system_hp_peri_timeout_addr_reg_t;
-
-/** Type of hp_peri_timeout_uid register
- *  HP_PERI_TIMEOUT_UID register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
-         *  will be cleared after the interrupt is cleared.
-         */
-        uint32_t hp_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hp_system_hp_peri_timeout_uid_reg_t;
-
-/** Type of modem_peri_timeout_conf register
- *  MODEM_PERI_TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
-         *  Set the timeout threshold for bus access, corresponding to the number of clock
-         *  cycles of the clock domain.
-         */
-        uint32_t modem_peri_timeout_thres:16;
-        /** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to clear timeout interrupt
-         */
-        uint32_t modem_peri_timeout_int_clear:1;
-        /** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
-         *  Set this bit as 1 to enable timeout protection for accessing modem registers
-         */
-        uint32_t modem_peri_timeout_protect_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} hp_system_modem_peri_timeout_conf_reg_t;
-
-/** Type of modem_peri_timeout_addr register
- *  MODEM_PERI_TIMEOUT_ADDR register
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  Record the address information of abnormal access
-         */
-        uint32_t modem_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} hp_system_modem_peri_timeout_addr_reg_t;
-
-/** Type of modem_peri_timeout_uid register
- *  MODEM_PERI_TIMEOUT_UID register
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
-         *  will be cleared after the interrupt is cleared.
-         */
-        uint32_t modem_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hp_system_modem_peri_timeout_uid_reg_t;
-
-
-/** Group: Redcy ECO Registers */
-/** Type of rnd_eco register
- *  redcy eco register.
- */
-typedef union {
-    struct {
-        /** redcy_ena : W/R; bitpos: [0]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_ena:1;
-        /** redcy_result : RO; bitpos: [1]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_rnd_eco_reg_t;
-
-/** Type of rnd_eco_low register
- *  redcy eco low register.
- */
-typedef union {
-    struct {
-        /** redcy_low : W/R; bitpos: [31:0]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_low:32;
-    };
-    uint32_t val;
-} hp_system_rnd_eco_low_reg_t;
-
-/** Type of rnd_eco_high register
- *  redcy eco high register.
- */
-typedef union {
-    struct {
-        /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_high:32;
-    };
-    uint32_t val;
-} hp_system_rnd_eco_high_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35676432;
-         *  HP-SYSTEM date information/ HP-SYSTEM version information.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} hp_system_date_reg_t;
-
-
-typedef struct hp_system_dev_t {
-    volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
-    volatile hp_system_sram_usage_conf_reg_t sram_usage_conf;
-    volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf;
-    volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
-    volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
-    volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
-    volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
-    volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
-    volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
-    volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
-    volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
-    volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
-    volatile hp_system_sdio_ctrl_reg_t sdio_ctrl;
-    volatile hp_system_retention_conf_reg_t retention_conf;
-    volatile hp_system_rom_table_lock_reg_t rom_table_lock;
-    volatile hp_system_rom_table_reg_t rom_table;
-    volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
-    volatile hp_system_mem_test_conf_reg_t mem_test_conf;
-    uint32_t reserved_048[230];
-    volatile hp_system_rnd_eco_reg_t rnd_eco;
-    volatile hp_system_rnd_eco_low_reg_t rnd_eco_low;
-    volatile hp_system_rnd_eco_high_reg_t rnd_eco_high;
-    uint32_t reserved_3ec[3];
-    volatile hp_system_clock_gate_reg_t clock_gate;
-    volatile hp_system_date_reg_t date;
-} hp_system_dev_t;
-
-extern hp_system_dev_t HP_SYSTEM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/i2s_reg.h b/components/soc/esp32c6/include/soc/i2s_reg.h
deleted file mode 100644
index 89fd5eb8444..00000000000
--- a/components/soc/esp32c6/include/soc/i2s_reg.h
+++ /dev/null
@@ -1,1294 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** I2S_INT_RAW_REG register
- *  I2S interrupt raw register, valid in level.
- */
-#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
-/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_RAW    (BIT(0))
-#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
-#define I2S_RX_DONE_INT_RAW_V  0x00000001U
-#define I2S_RX_DONE_INT_RAW_S  0
-/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_RAW    (BIT(1))
-#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
-#define I2S_TX_DONE_INT_RAW_V  0x00000001U
-#define I2S_TX_DONE_INT_RAW_S  1
-/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_RAW    (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
-#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_RX_HUNG_INT_RAW_S  2
-/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_RAW    (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
-#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_TX_HUNG_INT_RAW_S  3
-
-/** I2S_INT_ST_REG register
- *  I2S interrupt status register.
- */
-#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
-/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ST    (BIT(0))
-#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
-#define I2S_RX_DONE_INT_ST_V  0x00000001U
-#define I2S_RX_DONE_INT_ST_S  0
-/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ST    (BIT(1))
-#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
-#define I2S_TX_DONE_INT_ST_V  0x00000001U
-#define I2S_TX_DONE_INT_ST_S  1
-/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ST    (BIT(2))
-#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
-#define I2S_RX_HUNG_INT_ST_V  0x00000001U
-#define I2S_RX_HUNG_INT_ST_S  2
-/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ST    (BIT(3))
-#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
-#define I2S_TX_HUNG_INT_ST_V  0x00000001U
-#define I2S_TX_HUNG_INT_ST_S  3
-
-/** I2S_INT_ENA_REG register
- *  I2S interrupt enable register.
- */
-#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
-/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ENA    (BIT(0))
-#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
-#define I2S_RX_DONE_INT_ENA_V  0x00000001U
-#define I2S_RX_DONE_INT_ENA_S  0
-/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ENA    (BIT(1))
-#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
-#define I2S_TX_DONE_INT_ENA_V  0x00000001U
-#define I2S_TX_DONE_INT_ENA_S  1
-/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ENA    (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
-#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_RX_HUNG_INT_ENA_S  2
-/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ENA    (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
-#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_TX_HUNG_INT_ENA_S  3
-
-/** I2S_INT_CLR_REG register
- *  I2S interrupt clear register.
- */
-#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
-/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_CLR    (BIT(0))
-#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
-#define I2S_RX_DONE_INT_CLR_V  0x00000001U
-#define I2S_RX_DONE_INT_CLR_S  0
-/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_CLR    (BIT(1))
-#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
-#define I2S_TX_DONE_INT_CLR_V  0x00000001U
-#define I2S_TX_DONE_INT_CLR_S  1
-/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_CLR    (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
-#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_RX_HUNG_INT_CLR_S  2
-/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_CLR    (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
-#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_TX_HUNG_INT_CLR_S  3
-
-/** I2S_RX_CONF_REG register
- *  I2S RX configure register
- */
-#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
-/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset receiver
- */
-#define I2S_RX_RESET    (BIT(0))
-#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
-#define I2S_RX_RESET_V  0x00000001U
-#define I2S_RX_RESET_S  0
-/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Rx AFIFO
- */
-#define I2S_RX_FIFO_RESET    (BIT(1))
-#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
-#define I2S_RX_FIFO_RESET_V  0x00000001U
-#define I2S_RX_FIFO_RESET_S  1
-/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start receiving data
- */
-#define I2S_RX_START    (BIT(2))
-#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
-#define I2S_RX_START_V  0x00000001U
-#define I2S_RX_START_S  2
-/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave receiver mode
- */
-#define I2S_RX_SLAVE_MOD    (BIT(3))
-#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
-#define I2S_RX_SLAVE_MOD_V  0x00000001U
-#define I2S_RX_SLAVE_MOD_S  3
-/** I2S_RX_MONO : R/W; bitpos: [5]; default: 0;
- *  Set this bit to enable receiver  in mono mode
- */
-#define I2S_RX_MONO    (BIT(5))
-#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
-#define I2S_RX_MONO_V  0x00000001U
-#define I2S_RX_MONO_S  5
-/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
- */
-#define I2S_RX_BIG_ENDIAN    (BIT(7))
-#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
-#define I2S_RX_BIG_ENDIAN_V  0x00000001U
-#define I2S_RX_BIG_ENDIAN_S  7
-/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_RX_UPDATE    (BIT(8))
-#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
-#define I2S_RX_UPDATE_V  0x00000001U
-#define I2S_RX_UPDATE_S  8
-/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
- *  channel data value is valid in I2S RX mono mode.
- */
-#define I2S_RX_MONO_FST_VLD    (BIT(9))
-#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
-#define I2S_RX_MONO_FST_VLD_V  0x00000001U
-#define I2S_RX_MONO_FST_VLD_S  9
-/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
- *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_RX_PCM_CONF    0x00000003U
-#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
-#define I2S_RX_PCM_CONF_V  0x00000003U
-#define I2S_RX_PCM_CONF_S  10
-/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass Compress/Decompress module for received data.
- */
-#define I2S_RX_PCM_BYPASS    (BIT(12))
-#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
-#define I2S_RX_PCM_BYPASS_V  0x00000001U
-#define I2S_RX_PCM_BYPASS_S  12
-/** I2S_RX_STOP_MODE : R/W; bitpos: [14:13]; default: 0;
- *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
- *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
- */
-#define I2S_RX_STOP_MODE    0x00000003U
-#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
-#define I2S_RX_STOP_MODE_V  0x00000003U
-#define I2S_RX_STOP_MODE_S  13
-/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
- */
-#define I2S_RX_LEFT_ALIGN    (BIT(15))
-#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
-#define I2S_RX_LEFT_ALIGN_V  0x00000001U
-#define I2S_RX_LEFT_ALIGN_S  15
-/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
- */
-#define I2S_RX_24_FILL_EN    (BIT(16))
-#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
-#define I2S_RX_24_FILL_EN_V  0x00000001U
-#define I2S_RX_24_FILL_EN_S  16
-/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
- *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
- */
-#define I2S_RX_WS_IDLE_POL    (BIT(17))
-#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
-#define I2S_RX_WS_IDLE_POL_V  0x00000001U
-#define I2S_RX_WS_IDLE_POL_S  17
-/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
- *  is received first.
- */
-#define I2S_RX_BIT_ORDER    (BIT(18))
-#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
-#define I2S_RX_BIT_ORDER_V  0x00000001U
-#define I2S_RX_BIT_ORDER_S  18
-/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Rx mode . 0: Disable.
- */
-#define I2S_RX_TDM_EN    (BIT(19))
-#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
-#define I2S_RX_TDM_EN_V  0x00000001U
-#define I2S_RX_TDM_EN_S  19
-/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Rx mode . 0: Disable.
- */
-#define I2S_RX_PDM_EN    (BIT(20))
-#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
-#define I2S_RX_PDM_EN_V  0x00000001U
-#define I2S_RX_PDM_EN_S  20
-
-/** I2S_TX_CONF_REG register
- *  I2S TX configure register
- */
-#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
-/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset transmitter
- */
-#define I2S_TX_RESET    (BIT(0))
-#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
-#define I2S_TX_RESET_V  0x00000001U
-#define I2S_TX_RESET_S  0
-/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Tx AFIFO
- */
-#define I2S_TX_FIFO_RESET    (BIT(1))
-#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
-#define I2S_TX_FIFO_RESET_V  0x00000001U
-#define I2S_TX_FIFO_RESET_S  1
-/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start transmitting data
- */
-#define I2S_TX_START    (BIT(2))
-#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
-#define I2S_TX_START_V  0x00000001U
-#define I2S_TX_START_S  2
-/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave transmitter mode
- */
-#define I2S_TX_SLAVE_MOD    (BIT(3))
-#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
-#define I2S_TX_SLAVE_MOD_V  0x00000001U
-#define I2S_TX_SLAVE_MOD_S  3
-/** I2S_TX_MONO : R/W; bitpos: [5]; default: 0;
- *  Set this bit to enable transmitter in mono mode
- */
-#define I2S_TX_MONO    (BIT(5))
-#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
-#define I2S_TX_MONO_V  0x00000001U
-#define I2S_TX_MONO_S  5
-/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [6]; default: 0;
- *  1: The value of Left channel data is equal to the value of right channel data in
- *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
- *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
- */
-#define I2S_TX_CHAN_EQUAL    (BIT(6))
-#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
-#define I2S_TX_CHAN_EQUAL_V  0x00000001U
-#define I2S_TX_CHAN_EQUAL_S  6
-/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
- *  value.
- */
-#define I2S_TX_BIG_ENDIAN    (BIT(7))
-#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
-#define I2S_TX_BIG_ENDIAN_V  0x00000001U
-#define I2S_TX_BIG_ENDIAN_S  7
-/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_TX_UPDATE    (BIT(8))
-#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
-#define I2S_TX_UPDATE_V  0x00000001U
-#define I2S_TX_UPDATE_S  8
-/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
- *  channel data value is valid in I2S TX mono mode.
- */
-#define I2S_TX_MONO_FST_VLD    (BIT(9))
-#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
-#define I2S_TX_MONO_FST_VLD_V  0x00000001U
-#define I2S_TX_MONO_FST_VLD_S  9
-/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
- *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_TX_PCM_CONF    0x00000003U
-#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
-#define I2S_TX_PCM_CONF_V  0x00000003U
-#define I2S_TX_PCM_CONF_S  10
-/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass  Compress/Decompress module for transmitted data.
- */
-#define I2S_TX_PCM_BYPASS    (BIT(12))
-#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
-#define I2S_TX_PCM_BYPASS_V  0x00000001U
-#define I2S_TX_PCM_BYPASS_S  12
-/** I2S_TX_STOP_EN : R/W; bitpos: [13]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
- */
-#define I2S_TX_STOP_EN    (BIT(13))
-#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
-#define I2S_TX_STOP_EN_V  0x00000001U
-#define I2S_TX_STOP_EN_S  13
-/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
- */
-#define I2S_TX_LEFT_ALIGN    (BIT(15))
-#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
-#define I2S_TX_LEFT_ALIGN_V  0x00000001U
-#define I2S_TX_LEFT_ALIGN_S  15
-/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
- */
-#define I2S_TX_24_FILL_EN    (BIT(16))
-#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
-#define I2S_TX_24_FILL_EN_V  0x00000001U
-#define I2S_TX_24_FILL_EN_S  16
-/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
- *  WS should be 1 when sending left channel data, and WS is 0in right channel.
- */
-#define I2S_TX_WS_IDLE_POL    (BIT(17))
-#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
-#define I2S_TX_WS_IDLE_POL_V  0x00000001U
-#define I2S_TX_WS_IDLE_POL_S  17
-/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
- *  sent first.
- */
-#define I2S_TX_BIT_ORDER    (BIT(18))
-#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
-#define I2S_TX_BIT_ORDER_V  0x00000001U
-#define I2S_TX_BIT_ORDER_S  18
-/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Tx mode . 0: Disable.
- */
-#define I2S_TX_TDM_EN    (BIT(19))
-#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
-#define I2S_TX_TDM_EN_V  0x00000001U
-#define I2S_TX_TDM_EN_S  19
-/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Tx mode . 0: Disable.
- */
-#define I2S_TX_PDM_EN    (BIT(20))
-#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
-#define I2S_TX_PDM_EN_V  0x00000001U
-#define I2S_TX_PDM_EN_S  20
-/** I2S_TX_CHAN_MOD : R/W; bitpos: [26:24]; default: 0;
- *  I2S transmitter channel mode configuration bits.
- */
-#define I2S_TX_CHAN_MOD    0x00000007U
-#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
-#define I2S_TX_CHAN_MOD_V  0x00000007U
-#define I2S_TX_CHAN_MOD_S  24
-/** I2S_SIG_LOOPBACK : R/W; bitpos: [27]; default: 0;
- *  Enable signal loop back mode with transmitter module and receiver module sharing
- *  the same WS and BCK signals.
- */
-#define I2S_SIG_LOOPBACK    (BIT(27))
-#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
-#define I2S_SIG_LOOPBACK_V  0x00000001U
-#define I2S_SIG_LOOPBACK_S  27
-
-/** I2S_RX_CONF1_REG register
- *  I2S RX configure register 1
- */
-#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
-/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [6:0]; default: 0;
- *  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
- */
-#define I2S_RX_TDM_WS_WIDTH    0x0000007FU
-#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
-#define I2S_RX_TDM_WS_WIDTH_V  0x0000007FU
-#define I2S_RX_TDM_WS_WIDTH_S  0
-/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [12:7]; default: 6;
- *  Bit clock configuration bits in receiver mode.
- */
-#define I2S_RX_BCK_DIV_NUM    0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
-#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_S  7
-/** I2S_RX_BITS_MOD : R/W; bitpos: [17:13]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
- *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_RX_BITS_MOD    0x0000001FU
-#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
-#define I2S_RX_BITS_MOD_V  0x0000001FU
-#define I2S_RX_BITS_MOD_S  13
-/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [23:18]; default: 15;
- *  I2S Rx half sample bits -1.
- */
-#define I2S_RX_HALF_SAMPLE_BITS    0x0000003FU
-#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
-#define I2S_RX_HALF_SAMPLE_BITS_V  0x0000003FU
-#define I2S_RX_HALF_SAMPLE_BITS_S  18
-/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [28:24]; default: 15;
- *  The Rx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
-#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_S  24
-/** I2S_RX_MSB_SHIFT : R/W; bitpos: [29]; default: 1;
- *  Set this bit to enable receiver in Phillips standard mode
- */
-#define I2S_RX_MSB_SHIFT    (BIT(29))
-#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
-#define I2S_RX_MSB_SHIFT_V  0x00000001U
-#define I2S_RX_MSB_SHIFT_S  29
-
-/** I2S_TX_CONF1_REG register
- *  I2S TX configure register 1
- */
-#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
-/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [6:0]; default: 0;
- *  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
- */
-#define I2S_TX_TDM_WS_WIDTH    0x0000007FU
-#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
-#define I2S_TX_TDM_WS_WIDTH_V  0x0000007FU
-#define I2S_TX_TDM_WS_WIDTH_S  0
-/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [12:7]; default: 6;
- *  Bit clock configuration bits in transmitter mode.
- */
-#define I2S_TX_BCK_DIV_NUM    0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
-#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_S  7
-/** I2S_TX_BITS_MOD : R/W; bitpos: [17:13]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
- *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_TX_BITS_MOD    0x0000001FU
-#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
-#define I2S_TX_BITS_MOD_V  0x0000001FU
-#define I2S_TX_BITS_MOD_S  13
-/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [23:18]; default: 15;
- *  I2S Tx half sample bits -1.
- */
-#define I2S_TX_HALF_SAMPLE_BITS    0x0000003FU
-#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
-#define I2S_TX_HALF_SAMPLE_BITS_V  0x0000003FU
-#define I2S_TX_HALF_SAMPLE_BITS_S  18
-/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [28:24]; default: 15;
- *  The Tx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
-#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_S  24
-/** I2S_TX_MSB_SHIFT : R/W; bitpos: [29]; default: 1;
- *  Set this bit to enable transmitter in Phillips standard mode
- */
-#define I2S_TX_MSB_SHIFT    (BIT(29))
-#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
-#define I2S_TX_MSB_SHIFT_V  0x00000001U
-#define I2S_TX_MSB_SHIFT_S  29
-/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [30]; default: 1;
- *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
- *  generate pos/neg edge in master mode.
- */
-#define I2S_TX_BCK_NO_DLY    (BIT(30))
-#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
-#define I2S_TX_BCK_NO_DLY_V  0x00000001U
-#define I2S_TX_BCK_NO_DLY_S  30
-
-/** I2S_RX_CLKM_CONF_REG register
- *  I2S RX clock configure register
- */
-#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x30)
-/** I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
- *  Integral I2S clock divider value
- */
-#define I2S_RX_CLKM_DIV_NUM    0x000000FFU
-#define I2S_RX_CLKM_DIV_NUM_M  (I2S_RX_CLKM_DIV_NUM_V << I2S_RX_CLKM_DIV_NUM_S)
-#define I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
-#define I2S_RX_CLKM_DIV_NUM_S  0
-/** I2S_RX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0;
- *  I2S Rx module clock enable signal.
- */
-#define I2S_RX_CLK_ACTIVE    (BIT(26))
-#define I2S_RX_CLK_ACTIVE_M  (I2S_RX_CLK_ACTIVE_V << I2S_RX_CLK_ACTIVE_S)
-#define I2S_RX_CLK_ACTIVE_V  0x00000001U
-#define I2S_RX_CLK_ACTIVE_S  26
-/** I2S_RX_CLK_SEL : R/W; bitpos: [28:27]; default: 0;
- *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
- */
-#define I2S_RX_CLK_SEL    0x00000003U
-#define I2S_RX_CLK_SEL_M  (I2S_RX_CLK_SEL_V << I2S_RX_CLK_SEL_S)
-#define I2S_RX_CLK_SEL_V  0x00000003U
-#define I2S_RX_CLK_SEL_S  27
-/** I2S_MCLK_SEL : R/W; bitpos: [29]; default: 0;
- *  0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as
- *  I2S_MCLK_OUT.
- */
-#define I2S_MCLK_SEL    (BIT(29))
-#define I2S_MCLK_SEL_M  (I2S_MCLK_SEL_V << I2S_MCLK_SEL_S)
-#define I2S_MCLK_SEL_V  0x00000001U
-#define I2S_MCLK_SEL_S  29
-
-/** I2S_TX_CLKM_CONF_REG register
- *  I2S TX clock configure register
- */
-#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x34)
-/** I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
- *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
- *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
- *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
- *  (n+1)-div] + y * (n+1)-div.
- */
-#define I2S_TX_CLKM_DIV_NUM    0x000000FFU
-#define I2S_TX_CLKM_DIV_NUM_M  (I2S_TX_CLKM_DIV_NUM_V << I2S_TX_CLKM_DIV_NUM_S)
-#define I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
-#define I2S_TX_CLKM_DIV_NUM_S  0
-/** I2S_TX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0;
- *  I2S Tx module clock enable signal.
- */
-#define I2S_TX_CLK_ACTIVE    (BIT(26))
-#define I2S_TX_CLK_ACTIVE_M  (I2S_TX_CLK_ACTIVE_V << I2S_TX_CLK_ACTIVE_S)
-#define I2S_TX_CLK_ACTIVE_V  0x00000001U
-#define I2S_TX_CLK_ACTIVE_S  26
-/** I2S_TX_CLK_SEL : R/W; bitpos: [28:27]; default: 0;
- *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
- *  I2S_MCLK_in.
- */
-#define I2S_TX_CLK_SEL    0x00000003U
-#define I2S_TX_CLK_SEL_M  (I2S_TX_CLK_SEL_V << I2S_TX_CLK_SEL_S)
-#define I2S_TX_CLK_SEL_V  0x00000003U
-#define I2S_TX_CLK_SEL_S  27
-/** I2S_CLK_EN : R/W; bitpos: [29]; default: 0;
- *  Set this bit to enable clk gate
- */
-#define I2S_CLK_EN    (BIT(29))
-#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
-#define I2S_CLK_EN_V  0x00000001U
-#define I2S_CLK_EN_S  29
-
-/** I2S_RX_CLKM_DIV_CONF_REG register
- *  I2S RX module clock divider configure register
- */
-#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x38)
-/** I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Z is (a-b).
- */
-#define I2S_RX_CLKM_DIV_Z    0x000001FFU
-#define I2S_RX_CLKM_DIV_Z_M  (I2S_RX_CLKM_DIV_Z_V << I2S_RX_CLKM_DIV_Z_S)
-#define I2S_RX_CLKM_DIV_Z_V  0x000001FFU
-#define I2S_RX_CLKM_DIV_Z_S  0
-/** I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define I2S_RX_CLKM_DIV_Y    0x000001FFU
-#define I2S_RX_CLKM_DIV_Y_M  (I2S_RX_CLKM_DIV_Y_V << I2S_RX_CLKM_DIV_Y_S)
-#define I2S_RX_CLKM_DIV_Y_V  0x000001FFU
-#define I2S_RX_CLKM_DIV_Y_S  9
-/** I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define I2S_RX_CLKM_DIV_X    0x000001FFU
-#define I2S_RX_CLKM_DIV_X_M  (I2S_RX_CLKM_DIV_X_V << I2S_RX_CLKM_DIV_X_S)
-#define I2S_RX_CLKM_DIV_X_V  0x000001FFU
-#define I2S_RX_CLKM_DIV_X_S  18
-/** I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_YN1 is 1.
- */
-#define I2S_RX_CLKM_DIV_YN1    (BIT(27))
-#define I2S_RX_CLKM_DIV_YN1_M  (I2S_RX_CLKM_DIV_YN1_V << I2S_RX_CLKM_DIV_YN1_S)
-#define I2S_RX_CLKM_DIV_YN1_V  0x00000001U
-#define I2S_RX_CLKM_DIV_YN1_S  27
-
-/** I2S_TX_CLKM_DIV_CONF_REG register
- *  I2S TX module clock divider configure register
- */
-#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x3c)
-/** I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Z is (a-b).
- */
-#define I2S_TX_CLKM_DIV_Z    0x000001FFU
-#define I2S_TX_CLKM_DIV_Z_M  (I2S_TX_CLKM_DIV_Z_V << I2S_TX_CLKM_DIV_Z_S)
-#define I2S_TX_CLKM_DIV_Z_V  0x000001FFU
-#define I2S_TX_CLKM_DIV_Z_S  0
-/** I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define I2S_TX_CLKM_DIV_Y    0x000001FFU
-#define I2S_TX_CLKM_DIV_Y_M  (I2S_TX_CLKM_DIV_Y_V << I2S_TX_CLKM_DIV_Y_S)
-#define I2S_TX_CLKM_DIV_Y_V  0x000001FFU
-#define I2S_TX_CLKM_DIV_Y_S  9
-/** I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define I2S_TX_CLKM_DIV_X    0x000001FFU
-#define I2S_TX_CLKM_DIV_X_M  (I2S_TX_CLKM_DIV_X_V << I2S_TX_CLKM_DIV_X_S)
-#define I2S_TX_CLKM_DIV_X_V  0x000001FFU
-#define I2S_TX_CLKM_DIV_X_S  18
-/** I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_YN1 is 1.
- */
-#define I2S_TX_CLKM_DIV_YN1    (BIT(27))
-#define I2S_TX_CLKM_DIV_YN1_M  (I2S_TX_CLKM_DIV_YN1_V << I2S_TX_CLKM_DIV_YN1_S)
-#define I2S_TX_CLKM_DIV_YN1_V  0x00000001U
-#define I2S_TX_CLKM_DIV_YN1_S  27
-
-/** I2S_TX_PCM2PDM_CONF_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40)
-/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0;
- *  I2S TX PDM bypass hp filter or not. The option has been removed.
- */
-#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
-#define I2S_TX_PDM_HP_BYPASS_M  (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S)
-#define I2S_TX_PDM_HP_BYPASS_V  0x00000001U
-#define I2S_TX_PDM_HP_BYPASS_S  0
-/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
- *  I2S TX PDM OSR2 value
- */
-#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
-#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_S  1
-/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
- *  I2S TX PDM prescale for sigmadelta
- */
-#define I2S_TX_PDM_PRESCALE    0x000000FFU
-#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
-#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
-#define I2S_TX_PDM_PRESCALE_S  5
-/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
-#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_S  13
-/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
-#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_S  15
-/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
-#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
-/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
-/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
- *  I2S TX PDM sigmadelta dither2 value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
-/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
- *  I2S TX PDM sigmadelta dither value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
-/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
- *  I2S TX PDM dac mode enable
- */
-#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
-#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_2OUT_EN_S  23
-/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
- *  I2S TX PDM dac 2channel enable
- */
-#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
-#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_MODE_EN_S  24
-/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
- *  I2S TX PDM Converter enable
- */
-#define I2S_PCM2PDM_CONV_EN    (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
-#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
-#define I2S_PCM2PDM_CONV_EN_S  25
-
-/** I2S_TX_PCM2PDM_CONF1_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44)
-/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
- *  I2S TX PDM Fp
- */
-#define I2S_TX_PDM_FP    0x000003FFU
-#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
-#define I2S_TX_PDM_FP_V  0x000003FFU
-#define I2S_TX_PDM_FP_S  0
-/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
- *  I2S TX PDM Fs
- */
-#define I2S_TX_PDM_FS    0x000003FFU
-#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
-#define I2S_TX_PDM_FS_V  0x000003FFU
-#define I2S_TX_PDM_FS_S  10
-/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
- *  I2S_TX_IIR_HP_MULT12_5[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
-#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_S  20
-/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
- *  I2S_TX_IIR_HP_MULT12_0[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
-#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_S  23
-
-/** I2S_RX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
-/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
-#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
-/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
-#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
-/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
-#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
-/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
-#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
-/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
-#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
-/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
-#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
-/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
-#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
-/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
-#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
-/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
-#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN8_EN_S  8
-/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
-#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN9_EN_S  9
-/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
-#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN10_EN_S  10
-/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
-#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN11_EN_S  11
-/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
-#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN12_EN_S  12
-/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
-#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN13_EN_S  13
-/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
-#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN14_EN_S  14
-/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
-#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN15_EN_S  15
-/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
-#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
-
-/** I2S_TX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
-/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
-#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN0_EN_S  0
-/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
-#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN1_EN_S  1
-/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
-#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN2_EN_S  2
-/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
-#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN3_EN_S  3
-/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
-#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN4_EN_S  4
-/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
-#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN5_EN_S  5
-/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
-#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN6_EN_S  6
-/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
-#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN7_EN_S  7
-/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
-#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN8_EN_S  8
-/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
-#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN9_EN_S  9
-/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
-#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN10_EN_S  10
-/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
-#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN11_EN_S  11
-/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
-#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN12_EN_S  12
-/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
-#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN13_EN_S  13
-/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
-#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN14_EN_S  14
-/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
-#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN15_EN_S  15
-/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
-#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
-/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
- *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
- *  only the data of the enabled channels is sent, then this bit should be set. Clear
- *  it when all the data stored in DMA TX buffer is for enabled channels.
- */
-#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
-#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
-#define I2S_TX_TDM_SKIP_MSK_EN_S  20
-
-/** I2S_RX_TIMING_REG register
- *  I2S RX timing control register
- */
-#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
-/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD_IN_DM    0x00000003U
-#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
-#define I2S_RX_SD_IN_DM_V  0x00000003U
-#define I2S_RX_SD_IN_DM_S  0
-/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_OUT_DM    0x00000003U
-#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
-#define I2S_RX_WS_OUT_DM_V  0x00000003U
-#define I2S_RX_WS_OUT_DM_S  16
-/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_OUT_DM    0x00000003U
-#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
-#define I2S_RX_BCK_OUT_DM_V  0x00000003U
-#define I2S_RX_BCK_OUT_DM_S  20
-/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_IN_DM    0x00000003U
-#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
-#define I2S_RX_WS_IN_DM_V  0x00000003U
-#define I2S_RX_WS_IN_DM_S  24
-/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_IN_DM    0x00000003U
-#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
-#define I2S_RX_BCK_IN_DM_V  0x00000003U
-#define I2S_RX_BCK_IN_DM_S  28
-
-/** I2S_TX_TIMING_REG register
- *  I2S TX timing control register
- */
-#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
-/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD_OUT_DM    0x00000003U
-#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
-#define I2S_TX_SD_OUT_DM_V  0x00000003U
-#define I2S_TX_SD_OUT_DM_S  0
-/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
- *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD1_OUT_DM    0x00000003U
-#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
-#define I2S_TX_SD1_OUT_DM_V  0x00000003U
-#define I2S_TX_SD1_OUT_DM_S  4
-/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_OUT_DM    0x00000003U
-#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
-#define I2S_TX_WS_OUT_DM_V  0x00000003U
-#define I2S_TX_WS_OUT_DM_S  16
-/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_OUT_DM    0x00000003U
-#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
-#define I2S_TX_BCK_OUT_DM_V  0x00000003U
-#define I2S_TX_BCK_OUT_DM_S  20
-/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_IN_DM    0x00000003U
-#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
-#define I2S_TX_WS_IN_DM_V  0x00000003U
-#define I2S_TX_WS_IN_DM_S  24
-/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_IN_DM    0x00000003U
-#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
-#define I2S_TX_BCK_IN_DM_V  0x00000003U
-#define I2S_TX_BCK_IN_DM_S  28
-
-/** I2S_LC_HUNG_CONF_REG register
- *  I2S HUNG configure register.
- */
-#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
-/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
- *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
- *  when fifo hung counter is equal to this value
- */
-#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
-#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_S  0
-/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
- *  The bits are used to scale tick counter threshold. The tick counter is reset when
- *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
- */
-#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
-/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
- *  The enable bit for FIFO timeout
- */
-#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
-#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
-#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
-
-/** I2S_RXEOF_NUM_REG register
- *  I2S RX data number control register.
- */
-#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
-/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
- *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
- *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
- */
-#define I2S_RX_EOF_NUM    0x00000FFFU
-#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
-#define I2S_RX_EOF_NUM_V  0x00000FFFU
-#define I2S_RX_EOF_NUM_S  0
-
-/** I2S_CONF_SIGLE_DATA_REG register
- *  I2S signal data register
- */
-#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
-/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
- *  The configured constant channel data to be sent out.
- */
-#define I2S_SINGLE_DATA    0xFFFFFFFFU
-#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
-#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
-#define I2S_SINGLE_DATA_S  0
-
-/** I2S_STATE_REG register
- *  I2S TX status register
- */
-#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
-/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
- *  1: i2s_tx is idle state. 0: i2s_tx is working.
- */
-#define I2S_TX_IDLE    (BIT(0))
-#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
-#define I2S_TX_IDLE_V  0x00000001U
-#define I2S_TX_IDLE_S  0
-
-/** I2S_ETM_CONF_REG register
- *  I2S ETM configure register
- */
-#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
-/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
- *  I2S ETM send x words event. When sending word number of
- *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
-#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_S  0
-/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
- *  I2S ETM receive x words event. When receiving word number of
- *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
-
-/** I2S_DATE_REG register
- *  Version control register
- */
-#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80)
-/** I2S_DATE : R/W; bitpos: [27:0]; default: 35655792;
- *  I2S version control register
- */
-#define I2S_DATE    0x0FFFFFFFU
-#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
-#define I2S_DATE_V  0x0FFFFFFFU
-#define I2S_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/i2s_struct.h b/components/soc/esp32c6/include/soc/i2s_struct.h
deleted file mode 100644
index f7b7f069ad9..00000000000
--- a/components/soc/esp32c6/include/soc/i2s_struct.h
+++ /dev/null
@@ -1,902 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  I2S interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_raw:1;
-        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_raw:1;
-        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_raw:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_raw_reg_t;
-
-/** Type of int_st register
- *  I2S interrupt status register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_st:1;
-        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_st:1;
-        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_st:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_st_reg_t;
-
-/** Type of int_ena register
- *  I2S interrupt enable register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_ena:1;
-        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_ena_reg_t;
-
-/** Type of int_clr register
- *  I2S interrupt clear register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_clr:1;
-        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_clr:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of rx_conf register
- *  I2S RX configure register
- */
-typedef union {
-    struct {
-        /** rx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset receiver
-         */
-        uint32_t rx_reset:1;
-        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Rx AFIFO
-         */
-        uint32_t rx_fifo_reset:1;
-        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start receiving data
-         */
-        uint32_t rx_start:1;
-        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave receiver mode
-         */
-        uint32_t rx_slave_mod:1;
-        uint32_t reserved_4:1;
-        /** rx_mono : R/W; bitpos: [5]; default: 0;
-         *  Set this bit to enable receiver  in mono mode
-         */
-        uint32_t rx_mono:1;
-        uint32_t reserved_6:1;
-        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-         */
-        uint32_t rx_big_endian:1;
-        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t rx_update:1;
-        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
-         *  channel data value is valid in I2S RX mono mode.
-         */
-        uint32_t rx_mono_fst_vld:1;
-        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
-         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t rx_pcm_conf:2;
-        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass Compress/Decompress module for received data.
-         */
-        uint32_t rx_pcm_bypass:1;
-        /** rx_stop_mode : R/W; bitpos: [14:13]; default: 0;
-         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
-         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-         */
-        uint32_t rx_stop_mode:2;
-        /** rx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-         */
-        uint32_t rx_left_align:1;
-        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-         */
-        uint32_t rx_24_fill_en:1;
-        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
-         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-         */
-        uint32_t rx_ws_idle_pol:1;
-        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
-         *  is received first.
-         */
-        uint32_t rx_bit_order:1;
-        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_tdm_en:1;
-        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_pdm_en:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} i2s_rx_conf_reg_t;
-
-/** Type of rx_conf1 register
- *  I2S RX configure register 1
- */
-typedef union {
-    struct {
-        /** rx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0;
-         *  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
-         */
-        uint32_t rx_tdm_ws_width:7;
-        /** rx_bck_div_num : R/W; bitpos: [12:7]; default: 6;
-         *  Bit clock configuration bits in receiver mode.
-         */
-        uint32_t rx_bck_div_num:6;
-        /** rx_bits_mod : R/W; bitpos: [17:13]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
-         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t rx_bits_mod:5;
-        /** rx_half_sample_bits : R/W; bitpos: [23:18]; default: 15;
-         *  I2S Rx half sample bits -1.
-         */
-        uint32_t rx_half_sample_bits:6;
-        /** rx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15;
-         *  The Rx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t rx_tdm_chan_bits:5;
-        /** rx_msb_shift : R/W; bitpos: [29]; default: 1;
-         *  Set this bit to enable receiver in Phillips standard mode
-         */
-        uint32_t rx_msb_shift:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_rx_conf1_reg_t;
-
-/** Type of tx_pcm2pdm_conf register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
-         *  I2S TX PDM bypass hp filter or not. The option has been removed.
-         */
-        uint32_t tx_pdm_hp_bypass:1;
-        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
-         *  I2S TX PDM OSR2 value
-         */
-        uint32_t tx_pdm_sinc_osr2:4;
-        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
-         *  I2S TX PDM prescale for sigmadelta
-         */
-        uint32_t tx_pdm_prescale:8;
-        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_hp_in_shift:2;
-        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_lp_in_shift:2;
-        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sinc_in_shift:2;
-        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sigmadelta_in_shift:2;
-        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
-         *  I2S TX PDM sigmadelta dither2 value
-         */
-        uint32_t tx_pdm_sigmadelta_dither2:1;
-        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
-         *  I2S TX PDM sigmadelta dither value
-         */
-        uint32_t tx_pdm_sigmadelta_dither:1;
-        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
-         *  I2S TX PDM dac mode enable
-         */
-        uint32_t tx_pdm_dac_2out_en:1;
-        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
-         *  I2S TX PDM dac 2channel enable
-         */
-        uint32_t tx_pdm_dac_mode_en:1;
-        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
-         *  I2S TX PDM Converter enable
-         */
-        uint32_t pcm2pdm_conv_en:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf_reg_t;
-
-/** Type of tx_pcm2pdm_conf1 register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
-         *  I2S TX PDM Fp
-         */
-        uint32_t tx_pdm_fp:10;
-        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
-         *  I2S TX PDM Fs
-         */
-        uint32_t tx_pdm_fs:10;
-        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_5[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_5:3;
-        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_0[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_0:3;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf1_reg_t;
-
-/** Type of rx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan0_en:1;
-        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan1_en:1;
-        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan2_en:1;
-        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan3_en:1;
-        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan4_en:1;
-        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan5_en:1;
-        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan6_en:1;
-        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan7_en:1;
-        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan8_en:1;
-        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan9_en:1;
-        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan10_en:1;
-        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan11_en:1;
-        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan12_en:1;
-        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan13_en:1;
-        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan14_en:1;
-        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan15_en:1;
-        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t rx_tdm_tot_chan_num:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_rx_tdm_ctrl_reg_t;
-
-/** Type of rx_eof_num register
- *  I2S RX data number control register.
- */
-typedef union {
-    struct {
-        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
-         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
-         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
-         */
-        uint32_t rx_eof_num:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_rx_eof_num_reg_t;
-
-
-/** Group: TX Control and configuration registers */
-/** Type of tx_conf register
- *  I2S TX configure register
- */
-typedef union {
-    struct {
-        /** tx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset transmitter
-         */
-        uint32_t tx_reset:1;
-        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Tx AFIFO
-         */
-        uint32_t tx_fifo_reset:1;
-        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start transmitting data
-         */
-        uint32_t tx_start:1;
-        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave transmitter mode
-         */
-        uint32_t tx_slave_mod:1;
-        uint32_t reserved_4:1;
-        /** tx_mono : R/W; bitpos: [5]; default: 0;
-         *  Set this bit to enable transmitter in mono mode
-         */
-        uint32_t tx_mono:1;
-        /** tx_chan_equal : R/W; bitpos: [6]; default: 0;
-         *  1: The value of Left channel data is equal to the value of right channel data in
-         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
-         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-         */
-        uint32_t tx_chan_equal:1;
-        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
-         *  value.
-         */
-        uint32_t tx_big_endian:1;
-        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t tx_update:1;
-        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
-         *  channel data value is valid in I2S TX mono mode.
-         */
-        uint32_t tx_mono_fst_vld:1;
-        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
-         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t tx_pcm_conf:2;
-        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
-         */
-        uint32_t tx_pcm_bypass:1;
-        /** tx_stop_en : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
-         */
-        uint32_t tx_stop_en:1;
-        uint32_t reserved_14:1;
-        /** tx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-         */
-        uint32_t tx_left_align:1;
-        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-         */
-        uint32_t tx_24_fill_en:1;
-        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
-         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
-         */
-        uint32_t tx_ws_idle_pol:1;
-        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
-         *  sent first.
-         */
-        uint32_t tx_bit_order:1;
-        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_tdm_en:1;
-        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_pdm_en:1;
-        uint32_t reserved_21:3;
-        /** tx_chan_mod : R/W; bitpos: [26:24]; default: 0;
-         *  I2S transmitter channel mode configuration bits.
-         */
-        uint32_t tx_chan_mod:3;
-        /** sig_loopback : R/W; bitpos: [27]; default: 0;
-         *  Enable signal loop back mode with transmitter module and receiver module sharing
-         *  the same WS and BCK signals.
-         */
-        uint32_t sig_loopback:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} i2s_tx_conf_reg_t;
-
-/** Type of tx_conf1 register
- *  I2S TX configure register 1
- */
-typedef union {
-    struct {
-        /** tx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0;
-         *  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
-         */
-        uint32_t tx_tdm_ws_width:7;
-        /** tx_bck_div_num : R/W; bitpos: [12:7]; default: 6;
-         *  Bit clock configuration bits in transmitter mode.
-         */
-        uint32_t tx_bck_div_num:6;
-        /** tx_bits_mod : R/W; bitpos: [17:13]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
-         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t tx_bits_mod:5;
-        /** tx_half_sample_bits : R/W; bitpos: [23:18]; default: 15;
-         *  I2S Tx half sample bits -1.
-         */
-        uint32_t tx_half_sample_bits:6;
-        /** tx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15;
-         *  The Tx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t tx_tdm_chan_bits:5;
-        /** tx_msb_shift : R/W; bitpos: [29]; default: 1;
-         *  Set this bit to enable transmitter in Phillips standard mode
-         */
-        uint32_t tx_msb_shift:1;
-        /** tx_bck_no_dly : R/W; bitpos: [30]; default: 1;
-         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
-         *  generate pos/neg edge in master mode.
-         */
-        uint32_t tx_bck_no_dly:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} i2s_tx_conf1_reg_t;
-
-/** Type of tx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan0_en:1;
-        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan1_en:1;
-        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan2_en:1;
-        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan3_en:1;
-        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan4_en:1;
-        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan5_en:1;
-        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan6_en:1;
-        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan7_en:1;
-        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan8_en:1;
-        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan9_en:1;
-        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan10_en:1;
-        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan11_en:1;
-        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan12_en:1;
-        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan13_en:1;
-        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan14_en:1;
-        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan15_en:1;
-        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t tx_tdm_tot_chan_num:4;
-        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
-         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
-         *  only the data of the enabled channels is sent, then this bit should be set. Clear
-         *  it when all the data stored in DMA TX buffer is for enabled channels.
-         */
-        uint32_t tx_tdm_skip_msk_en:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} i2s_tx_tdm_ctrl_reg_t;
-
-
-/** Group: RX clock and timing registers */
-/** Type of rx_timing register
- *  I2S RX timing control register
- */
-typedef union {
-    struct {
-        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd_in_dm:2;
-        uint32_t reserved_2:14;
-        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_rx_timing_reg_t;
-
-
-/** Group: TX clock and timing registers */
-/** Type of tx_timing register
- *  I2S TX timing control register
- */
-typedef union {
-    struct {
-        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd_out_dm:2;
-        uint32_t reserved_2:2;
-        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
-         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd1_out_dm:2;
-        uint32_t reserved_6:10;
-        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_tx_timing_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of lc_hung_conf register
- *  I2S HUNG configure register.
- */
-typedef union {
-    struct {
-        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
-         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
-         *  when fifo hung counter is equal to this value
-         */
-        uint32_t lc_fifo_timeout:8;
-        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
-         *  The bits are used to scale tick counter threshold. The tick counter is reset when
-         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-         */
-        uint32_t lc_fifo_timeout_shift:3;
-        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
-         *  The enable bit for FIFO timeout
-         */
-        uint32_t lc_fifo_timeout_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_lc_hung_conf_reg_t;
-
-/** Type of conf_single_data register
- *  I2S signal data register
- */
-typedef union {
-    struct {
-        /** single_data : R/W; bitpos: [31:0]; default: 0;
-         *  The configured constant channel data to be sent out.
-         */
-        uint32_t single_data:32;
-    };
-    uint32_t val;
-} i2s_conf_single_data_reg_t;
-
-
-/** Group: TX status registers */
-/** Type of state register
- *  I2S TX status register
- */
-typedef union {
-    struct {
-        /** tx_idle : RO; bitpos: [0]; default: 1;
-         *  1: i2s_tx is idle state. 0: i2s_tx is working.
-         */
-        uint32_t tx_idle:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} i2s_state_reg_t;
-
-
-/** Group: ETM registers */
-/** Type of etm_conf register
- *  I2S ETM configure register
- */
-typedef union {
-    struct {
-        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
-         *  I2S ETM send x words event. When sending word number of
-         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_tx_send_word_num:10;
-        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
-         *  I2S ETM receive x words event. When receiving word number of
-         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_rx_receive_word_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_etm_conf_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35655792;
-         *  I2S version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} i2s_date_reg_t;
-
-
-typedef struct i2s_dev_t {
-    uint32_t reserved_000[3];
-    volatile i2s_int_raw_reg_t int_raw;
-    volatile i2s_int_st_reg_t int_st;
-    volatile i2s_int_ena_reg_t int_ena;
-    volatile i2s_int_clr_reg_t int_clr;
-    uint32_t reserved_01c;
-    volatile i2s_rx_conf_reg_t rx_conf;
-    volatile i2s_tx_conf_reg_t tx_conf;
-    volatile i2s_rx_conf1_reg_t rx_conf1;
-    volatile i2s_tx_conf1_reg_t tx_conf1;
-    uint32_t reserved_030[4];
-    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
-    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
-    uint32_t reserved_048[2];
-    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
-    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
-    volatile i2s_rx_timing_reg_t rx_timing;
-    volatile i2s_tx_timing_reg_t tx_timing;
-    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
-    volatile i2s_rx_eof_num_reg_t rx_eof_num;
-    volatile i2s_conf_single_data_reg_t conf_single_data;
-    volatile i2s_state_reg_t state;
-    volatile i2s_etm_conf_reg_t etm_conf;
-    uint32_t reserved_074[3];
-    volatile i2s_date_reg_t date;
-} i2s_dev_t;
-
-extern i2s_dev_t I2S0;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c6/include/soc/interrupt_matrix_reg.h
deleted file mode 100644
index d5af256a4d0..00000000000
--- a/components/soc/esp32c6/include/soc/interrupt_matrix_reg.h
+++ /dev/null
@@ -1,999 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
-/** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_M  (INTMTX_CORE0_WIFI_MAC_INTR_MAP_V << INTMTX_CORE0_WIFI_MAC_INTR_MAP_S)
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
-/** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP    0x0000001FU
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_M  (INTMTX_CORE0_WIFI_MAC_NMI_MAP_V << INTMTX_CORE0_WIFI_MAC_NMI_MAP_S)
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_V  0x0000001FU
-#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_S  0
-
-/** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
-/** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_M  (INTMTX_CORE0_WIFI_PWR_INTR_MAP_V << INTMTX_CORE0_WIFI_PWR_INTR_MAP_S)
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_S  0
-
-/** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
-/** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP_M  (INTMTX_CORE0_WIFI_BB_INTR_MAP_V << INTMTX_CORE0_WIFI_BB_INTR_MAP_S)
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_WIFI_BB_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
-/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BT_MAC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_M  (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
-/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BT_BB_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_BB_INTR_MAP_M  (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
-#define INTMTX_CORE0_BT_BB_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_BB_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
-/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BT_BB_NMI_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_BB_NMI_MAP_M  (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
-#define INTMTX_CORE0_BT_BB_NMI_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_BB_NMI_MAP_S  0
-
-/** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
-/** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_COEX_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
-/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_COEX_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_COEX_INTR_MAP_M  (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
-#define INTMTX_CORE0_COEX_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_COEX_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
-/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M  (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
-/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M  (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
-/** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_I2C_MST_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2C_MST_INTR_MAP_M  (INTMTX_CORE0_I2C_MST_INTR_MAP_V << INTMTX_CORE0_I2C_MST_INTR_MAP_S)
-#define INTMTX_CORE0_I2C_MST_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2C_MST_INTR_MAP_S  0
-
-/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
-/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M  (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PMU_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
-/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PMU_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PMU_INTR_MAP_M  (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
-#define INTMTX_CORE0_PMU_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PMU_INTR_MAP_S  0
-
-/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
-/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_EFUSE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_EFUSE_INTR_MAP_M  (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
-#define INTMTX_CORE0_EFUSE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_EFUSE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
-/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_UART_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
-/** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_UART_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_UART_INTR_MAP_M  (INTMTX_CORE0_LP_UART_INTR_MAP_V << INTMTX_CORE0_LP_UART_INTR_MAP_S)
-#define INTMTX_CORE0_LP_UART_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_UART_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
-/** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_I2C_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_I2C_INTR_MAP_M  (INTMTX_CORE0_LP_I2C_INTR_MAP_V << INTMTX_CORE0_LP_I2C_INTR_MAP_S)
-#define INTMTX_CORE0_LP_I2C_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_I2C_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
-/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_M  (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
-/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
-/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
-/** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M1_INTR_MAP_V << INTMTX_CORE0_LP_APM_M1_INTR_MAP_S)
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
-
-/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
-/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M  (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
-/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TRACE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TRACE_INTR_MAP_M  (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
-#define INTMTX_CORE0_TRACE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TRACE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
-/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CACHE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CACHE_INTR_MAP_M  (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
-#define INTMTX_CORE0_CACHE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CACHE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
-/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
-
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
-
-/** INTMTX_CORE0_PAU_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
-/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PAU_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PAU_INTR_MAP_M  (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
-#define INTMTX_CORE0_PAU_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PAU_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
-/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
-/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
-/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
-/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
-/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
-/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
-/** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LP_APM0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_APM0_INTR_MAP_M  (INTMTX_CORE0_LP_APM0_INTR_MAP_V << INTMTX_CORE0_LP_APM0_INTR_MAP_S)
-#define INTMTX_CORE0_LP_APM0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_APM0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
-/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_MSPI_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_MSPI_INTR_MAP_M  (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
-#define INTMTX_CORE0_MSPI_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_MSPI_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
-/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_I2S1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2S1_INTR_MAP_M  (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
-#define INTMTX_CORE0_I2S1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2S1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
-/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_UHCI0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UHCI0_INTR_MAP_M  (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
-#define INTMTX_CORE0_UHCI0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UHCI0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UART0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
-/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_UART0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UART0_INTR_MAP_M  (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
-#define INTMTX_CORE0_UART0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UART0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UART1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
-/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_UART1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UART1_INTR_MAP_M  (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
-#define INTMTX_CORE0_UART1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UART1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
-/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_LEDC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LEDC_INTR_MAP_M  (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
-#define INTMTX_CORE0_LEDC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LEDC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
-/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CAN0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CAN0_INTR_MAP_M  (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
-#define INTMTX_CORE0_CAN0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CAN0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CAN1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
-/** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_CAN1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CAN1_INTR_MAP_M  (INTMTX_CORE0_CAN1_INTR_MAP_V << INTMTX_CORE0_CAN1_INTR_MAP_S)
-#define INTMTX_CORE0_CAN1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CAN1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_USB_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
-/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_USB_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_USB_INTR_MAP_M  (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
-#define INTMTX_CORE0_USB_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_USB_INTR_MAP_S  0
-
-/** INTMTX_CORE0_RMT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
-/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_RMT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_RMT_INTR_MAP_M  (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
-#define INTMTX_CORE0_RMT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_RMT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
-/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M  (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
-/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG0_T0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_M  (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
-/** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG0_T1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG0_T1_INTR_MAP_M  (INTMTX_CORE0_TG0_T1_INTR_MAP_V << INTMTX_CORE0_TG0_T1_INTR_MAP_S)
-#define INTMTX_CORE0_TG0_T1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG0_T1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
-/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M  (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
-/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG1_T0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_M  (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
-/** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG1_T1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG1_T1_INTR_MAP_M  (INTMTX_CORE0_TG1_T1_INTR_MAP_V << INTMTX_CORE0_TG1_T1_INTR_MAP_S)
-#define INTMTX_CORE0_TG1_T1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG1_T1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
-/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M  (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
-/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
-/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
-/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
-/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_APB_ADC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_M  (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PWM_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
-/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PWM_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PWM_INTR_MAP_M  (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
-#define INTMTX_CORE0_PWM_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PWM_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
-/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PCNT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PCNT_INTR_MAP_M  (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
-#define INTMTX_CORE0_PCNT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PCNT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
-/** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_PARL_IO_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PARL_IO_INTR_MAP_M  (INTMTX_CORE0_PARL_IO_INTR_MAP_V << INTMTX_CORE0_PARL_IO_INTR_MAP_S)
-#define INTMTX_CORE0_PARL_IO_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PARL_IO_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SLC0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
-/** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SLC0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SLC0_INTR_MAP_M  (INTMTX_CORE0_SLC0_INTR_MAP_V << INTMTX_CORE0_SLC0_INTR_MAP_S)
-#define INTMTX_CORE0_SLC0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SLC0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SLC1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
-/** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SLC1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SLC1_INTR_MAP_M  (INTMTX_CORE0_SLC1_INTR_MAP_V << INTMTX_CORE0_SLC1_INTR_MAP_S)
-#define INTMTX_CORE0_SLC1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SLC1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
-/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
-/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
-/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114)
-/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118)
-/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c)
-/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120)
-/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_GPSPI2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_M  (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_AES_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124)
-/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_AES_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_AES_INTR_MAP_M  (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
-#define INTMTX_CORE0_AES_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_AES_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SHA_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128)
-/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_SHA_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SHA_INTR_MAP_M  (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
-#define INTMTX_CORE0_SHA_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SHA_INTR_MAP_S  0
-
-/** INTMTX_CORE0_RSA_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c)
-/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_RSA_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_RSA_INTR_MAP_M  (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
-#define INTMTX_CORE0_RSA_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_RSA_INTR_MAP_S  0
-
-/** INTMTX_CORE0_ECC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130)
-/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_ECC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ECC_INTR_MAP_M  (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
-#define INTMTX_CORE0_ECC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ECC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134)
-/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_INT_STATUS_0    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_0_M  (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
-#define INTMTX_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_0_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138)
-/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_INT_STATUS_1    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_1_M  (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
-#define INTMTX_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_1_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c)
-/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
- *  Need add description
- */
-#define INTMTX_CORE0_INT_STATUS_2    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_2_M  (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
-#define INTMTX_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_2_S  0
-
-/** INTMTX_CORE0_CLOCK_GATE_REG register
- *  register description
- */
-#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140)
-/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Need add description
- */
-#define INTMTX_CORE0_REG_CLK_EN    (BIT(0))
-#define INTMTX_CORE0_REG_CLK_EN_M  (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
-#define INTMTX_CORE0_REG_CLK_EN_V  0x00000001U
-#define INTMTX_CORE0_REG_CLK_EN_S  0
-
-/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
- *  register description
- */
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
-/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144;
- *  Need add description
- */
-#define INTMTX_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_M  (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c6/include/soc/interrupt_matrix_struct.h
deleted file mode 100644
index 4af30c94933..00000000000
--- a/components/soc/esp32c6/include/soc/interrupt_matrix_struct.h
+++ /dev/null
@@ -1,1254 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of wifi_mac_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** wifi_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t wifi_mac_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_wifi_mac_intr_map_reg_t;
-
-/** Type of wifi_mac_nmi_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** wifi_mac_nmi_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t wifi_mac_nmi_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_wifi_mac_nmi_map_reg_t;
-
-/** Type of wifi_pwr_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** wifi_pwr_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t wifi_pwr_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_wifi_pwr_intr_map_reg_t;
-
-/** Type of wifi_bb_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** wifi_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t wifi_bb_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_wifi_bb_intr_map_reg_t;
-
-/** Type of bt_mac_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t bt_mac_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_bt_mac_intr_map_reg_t;
-
-/** Type of bt_bb_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t bt_bb_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_bt_bb_intr_map_reg_t;
-
-/** Type of bt_bb_nmi_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t bt_bb_nmi_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_bt_bb_nmi_map_reg_t;
-
-/** Type of lp_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_timer_intr_map_reg_t;
-
-/** Type of coex_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** coex_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t coex_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_coex_intr_map_reg_t;
-
-/** Type of ble_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t ble_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_ble_timer_intr_map_reg_t;
-
-/** Type of ble_sec_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t ble_sec_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_ble_sec_intr_map_reg_t;
-
-/** Type of i2c_mst_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2c_mst_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t i2c_mst_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_i2c_mst_intr_map_reg_t;
-
-/** Type of zb_mac_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t zb_mac_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_zb_mac_intr_map_reg_t;
-
-/** Type of pmu_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t pmu_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_pmu_intr_map_reg_t;
-
-/** Type of efuse_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t efuse_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_efuse_intr_map_reg_t;
-
-/** Type of lp_rtc_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_rtc_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_rtc_timer_intr_map_reg_t;
-
-/** Type of lp_uart_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_uart_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_uart_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_uart_intr_map_reg_t;
-
-/** Type of lp_i2c_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_i2c_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_i2c_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_i2c_intr_map_reg_t;
-
-/** Type of lp_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_wdt_intr_map_reg_t;
-
-/** Type of lp_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_peri_timeout_intr_map_reg_t;
-
-/** Type of lp_apm_m0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_apm_m0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_apm_m0_intr_map_reg_t;
-
-/** Type of lp_apm_m1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_apm_m1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_apm_m1_intr_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_0_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_0_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_1_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_1_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_2_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_2_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_3_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_intr_from_cpu_3_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t;
-
-/** Type of assist_debug_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t assist_debug_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_assist_debug_intr_map_reg_t;
-
-/** Type of trace_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** trace_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t trace_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_trace_intr_map_reg_t;
-
-/** Type of cache_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cache_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cache_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cache_intr_map_reg_t;
-
-/** Type of cpu_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t cpu_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t;
-
-/** Type of gpio_interrupt_pro_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t gpio_interrupt_pro_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_gpio_interrupt_pro_map_reg_t;
-
-/** Type of gpio_interrupt_pro_nmi_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t gpio_interrupt_pro_nmi_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t;
-
-/** Type of pau_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pau_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t pau_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_pau_intr_map_reg_t;
-
-/** Type of hp_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_peri_timeout_intr_map_reg_t;
-
-/** Type of modem_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** modem_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t modem_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_modem_peri_timeout_intr_map_reg_t;
-
-/** Type of hp_apm_m0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_apm_m0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_apm_m0_intr_map_reg_t;
-
-/** Type of hp_apm_m1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_apm_m1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_apm_m1_intr_map_reg_t;
-
-/** Type of hp_apm_m2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_apm_m2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_apm_m2_intr_map_reg_t;
-
-/** Type of hp_apm_m3_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t hp_apm_m3_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_hp_apm_m3_intr_map_reg_t;
-
-/** Type of lp_apm0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_apm0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t lp_apm0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_lp_apm0_intr_map_reg_t;
-
-/** Type of mspi_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t mspi_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_mspi_intr_map_reg_t;
-
-/** Type of i2s1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t i2s1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_i2s1_intr_map_reg_t;
-
-/** Type of uhci0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t uhci0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_uhci0_intr_map_reg_t;
-
-/** Type of uart0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t uart0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_uart0_intr_map_reg_t;
-
-/** Type of uart1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t uart1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_uart1_intr_map_reg_t;
-
-/** Type of ledc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t ledc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_ledc_intr_map_reg_t;
-
-/** Type of can0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** can0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t can0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_can0_intr_map_reg_t;
-
-/** Type of can1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** can1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t can1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_can1_intr_map_reg_t;
-
-/** Type of usb_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** usb_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t usb_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_usb_intr_map_reg_t;
-
-/** Type of rmt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t rmt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_rmt_intr_map_reg_t;
-
-/** Type of i2c_ext0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t i2c_ext0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_i2c_ext0_intr_map_reg_t;
-
-/** Type of tg0_t0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg0_t0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg0_t0_intr_map_reg_t;
-
-/** Type of tg0_t1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg0_t1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg0_t1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg0_t1_intr_map_reg_t;
-
-/** Type of tg0_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg0_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg0_wdt_intr_map_reg_t;
-
-/** Type of tg1_t0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg1_t0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg1_t0_intr_map_reg_t;
-
-/** Type of tg1_t1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg1_t1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg1_t1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg1_t1_intr_map_reg_t;
-
-/** Type of tg1_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t tg1_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_tg1_wdt_intr_map_reg_t;
-
-/** Type of systimer_target0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t systimer_target0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_systimer_target0_intr_map_reg_t;
-
-/** Type of systimer_target1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t systimer_target1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_systimer_target1_intr_map_reg_t;
-
-/** Type of systimer_target2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t systimer_target2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_systimer_target2_intr_map_reg_t;
-
-/** Type of apb_adc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t apb_adc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_apb_adc_intr_map_reg_t;
-
-/** Type of pwm_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t pwm_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_pwm_intr_map_reg_t;
-
-/** Type of pcnt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t pcnt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_pcnt_intr_map_reg_t;
-
-/** Type of parl_io_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** parl_io_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t parl_io_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_parl_io_intr_map_reg_t;
-
-/** Type of slc0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** slc0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t slc0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_slc0_intr_map_reg_t;
-
-/** Type of slc1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** slc1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t slc1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_slc1_intr_map_reg_t;
-
-/** Type of dma_in_ch0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_in_ch0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_in_ch0_intr_map_reg_t;
-
-/** Type of dma_in_ch1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_in_ch1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_in_ch1_intr_map_reg_t;
-
-/** Type of dma_in_ch2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_in_ch2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_in_ch2_intr_map_reg_t;
-
-/** Type of dma_out_ch0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_out_ch0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_out_ch0_intr_map_reg_t;
-
-/** Type of dma_out_ch1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_out_ch1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_out_ch1_intr_map_reg_t;
-
-/** Type of dma_out_ch2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t dma_out_ch2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_dma_out_ch2_intr_map_reg_t;
-
-/** Type of gpspi2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t gpspi2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_gpspi2_intr_map_reg_t;
-
-/** Type of aes_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** aes_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t aes_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_aes_intr_map_reg_t;
-
-/** Type of sha_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** sha_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t sha_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_sha_intr_map_reg_t;
-
-/** Type of rsa_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t rsa_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_rsa_intr_map_reg_t;
-
-/** Type of ecc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t ecc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} interrupt_matrix_ecc_intr_map_reg_t;
-
-/** Type of int_status_reg_0 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t int_status_0:32;
-    };
-    uint32_t val;
-} interrupt_matrix_int_status_reg_0_reg_t;
-
-/** Type of int_status_reg_1 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t int_status_1:32;
-    };
-    uint32_t val;
-} interrupt_matrix_int_status_reg_1_reg_t;
-
-/** Type of int_status_reg_2 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
-         *  Need add description
-         */
-        uint32_t int_status_2:32;
-    };
-    uint32_t val;
-} interrupt_matrix_int_status_reg_2_reg_t;
-
-/** Type of clock_gate register
- *  register description
- */
-typedef union {
-    struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Need add description
-         */
-        uint32_t reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} interrupt_matrix_clock_gate_reg_t;
-
-/** Type of interrupt_reg_date register
- *  register description
- */
-typedef union {
-    struct {
-        /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35664144;
-         *  Need add description
-         */
-        uint32_t interrupt_reg_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} interrupt_matrix_interrupt_reg_date_reg_t;
-
-
-typedef struct interrupt_matrix_dev_t {
-    volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map;
-    volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map;
-    volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map;
-    volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map;
-    volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map;
-    volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map;
-    volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map;
-    volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map;
-    volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map;
-    volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map;
-    volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map;
-    volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map;
-    volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map;
-    volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map;
-    volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map;
-    volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
-    volatile interrupt_matrix_lp_uart_intr_map_reg_t lp_uart_intr_map;
-    volatile interrupt_matrix_lp_i2c_intr_map_reg_t lp_i2c_intr_map;
-    volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
-    volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
-    volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
-    volatile interrupt_matrix_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map;
-    volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
-    volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
-    volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
-    volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
-    volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map;
-    volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map;
-    volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map;
-    volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map;
-    volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map;
-    volatile interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map;
-    volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map;
-    volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map;
-    volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map;
-    volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
-    volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
-    volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
-    volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
-    volatile interrupt_matrix_lp_apm0_intr_map_reg_t lp_apm0_intr_map;
-    volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map;
-    volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map;
-    volatile interrupt_matrix_uhci0_intr_map_reg_t uhci0_intr_map;
-    volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map;
-    volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map;
-    volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map;
-    volatile interrupt_matrix_can0_intr_map_reg_t can0_intr_map;
-    volatile interrupt_matrix_can1_intr_map_reg_t can1_intr_map;
-    volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map;
-    volatile interrupt_matrix_rmt_intr_map_reg_t rmt_intr_map;
-    volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map;
-    volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map;
-    volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map;
-    volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map;
-    volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map;
-    volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map;
-    volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map;
-    volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
-    volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
-    volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
-    volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map;
-    volatile interrupt_matrix_pwm_intr_map_reg_t pwm_intr_map;
-    volatile interrupt_matrix_pcnt_intr_map_reg_t pcnt_intr_map;
-    volatile interrupt_matrix_parl_io_intr_map_reg_t parl_io_intr_map;
-    volatile interrupt_matrix_slc0_intr_map_reg_t slc0_intr_map;
-    volatile interrupt_matrix_slc1_intr_map_reg_t slc1_intr_map;
-    volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map;
-    volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map;
-    volatile interrupt_matrix_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map;
-    volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map;
-    volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map;
-    volatile interrupt_matrix_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map;
-    volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map;
-    volatile interrupt_matrix_aes_intr_map_reg_t aes_intr_map;
-    volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map;
-    volatile interrupt_matrix_rsa_intr_map_reg_t rsa_intr_map;
-    volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map;
-    volatile interrupt_matrix_int_status_reg_0_reg_t int_status_reg_0;
-    volatile interrupt_matrix_int_status_reg_1_reg_t int_status_reg_1;
-    volatile interrupt_matrix_int_status_reg_2_reg_t int_status_reg_2;
-    volatile interrupt_matrix_clock_gate_reg_t clock_gate;
-    uint32_t reserved_144[430];
-    volatile interrupt_matrix_interrupt_reg_date_reg_t interrupt_reg_date;
-} interrupt_matrix_dev_t;
-
-extern interrupt_matrix_dev_t INTMTX;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/interrupts.h b/components/soc/esp32c6/include/soc/interrupts.h
index 8eb941cf837..0d1fbc0f41b 100644
--- a/components/soc/esp32c6/include/soc/interrupts.h
+++ b/components/soc/esp32c6/include/soc/interrupts.h
@@ -56,7 +56,7 @@ typedef enum {
     ETS_HP_APM_M3_INTR_SOURCE,
     ETS_LP_APM0_INTR_SOURCE,
     ETS_MSPI_INTR_SOURCE,
-    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
+    ETS_I2S0_INTR_SOURCE,                       /**< interrupt of I2S0, level*/
     ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
     ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
     ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
diff --git a/components/soc/esp32c6/include/soc/io_mux_reg.h b/components/soc/esp32c6/include/soc/io_mux_reg.h
deleted file mode 100644
index 698a2b5785b..00000000000
--- a/components/soc/esp32c6/include/soc/io_mux_reg.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-#include "soc.h"
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Used to enable sleep mode pin functions */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
-#define FILTER_EN (BIT(15))
-#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
-#define FILTER_EN_V 1
-#define FILTER_EN_S 15
-
-#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-
-#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
-
-#define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_XTAL_32K_P_U
-#define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_XTAL_32K_N_U
-#define IO_MUX_GPIO2_REG               PERIPHS_IO_MUX_GPIO2_U
-#define IO_MUX_GPIO3_REG               PERIPHS_IO_MUX_GPIO3_U
-#define IO_MUX_GPIO4_REG               PERIPHS_IO_MUX_MTMS_U
-#define IO_MUX_GPIO5_REG               PERIPHS_IO_MUX_MTDI_U
-#define IO_MUX_GPIO6_REG               PERIPHS_IO_MUX_MTCK_U
-#define IO_MUX_GPIO7_REG               PERIPHS_IO_MUX_MTDO_U
-#define IO_MUX_GPIO8_REG               PERIPHS_IO_MUX_GPIO8_U
-#define IO_MUX_GPIO9_REG               PERIPHS_IO_MUX_GPIO9_U
-#define IO_MUX_GPIO10_REG              PERIPHS_IO_MUX_GPIO10_U
-#define IO_MUX_GPIO11_REG              PERIPHS_IO_MUX_GPIO11_U
-#define IO_MUX_GPIO12_REG              PERIPHS_IO_MUX_GPIO12_U
-#define IO_MUX_GPIO13_REG              PERIPHS_IO_MUX_GPIO13_U
-#define IO_MUX_GPIO14_REG              PERIPHS_IO_MUX_GPIO14_U
-#define IO_MUX_GPIO15_REG              PERIPHS_IO_MUX_GPIO15_U
-#define IO_MUX_GPIO16_REG              PERIPHS_IO_MUX_U0TXD_U
-#define IO_MUX_GPIO17_REG              PERIPHS_IO_MUX_U0RXD_U
-#define IO_MUX_GPIO18_REG              PERIPHS_IO_MUX_SDIO_CMD_U
-#define IO_MUX_GPIO19_REG              PERIPHS_IO_MUX_SDIO_CLK_U
-#define IO_MUX_GPIO20_REG              PERIPHS_IO_MUX_SDIO_DATA0_U
-#define IO_MUX_GPIO21_REG              PERIPHS_IO_MUX_SDIO_DATA1_U
-#define IO_MUX_GPIO22_REG              PERIPHS_IO_MUX_SDIO_DATA2_U
-#define IO_MUX_GPIO23_REG              PERIPHS_IO_MUX_SDIO_DATA3_U
-#define IO_MUX_GPIO24_REG              PERIPHS_IO_MUX_SPICS0_U
-#define IO_MUX_GPIO25_REG              PERIPHS_IO_MUX_SPIQ_U
-#define IO_MUX_GPIO26_REG              PERIPHS_IO_MUX_SPIWP_U
-#define IO_MUX_GPIO27_REG              PERIPHS_IO_MUX_VDD_SPI_U
-#define IO_MUX_GPIO28_REG              PERIPHS_IO_MUX_SPIHD_U
-#define IO_MUX_GPIO29_REG              PERIPHS_IO_MUX_SPICLK_U
-#define IO_MUX_GPIO30_REG              PERIPHS_IO_MUX_SPID_U
-
-#define PIN_FUNC_GPIO								1
-
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
-#define SPI_HD_GPIO_NUM              28
-#define SPI_WP_GPIO_NUM              26
-#define SPI_CS0_GPIO_NUM             24
-#define SPI_CLK_GPIO_NUM             29
-#define SPI_D_GPIO_NUM               30
-#define SPI_Q_GPIO_NUM               25
-
-#define SD_CLK_GPIO_NUM              19
-#define SD_CMD_GPIO_NUM              18
-#define SD_DATA0_GPIO_NUM            20
-#define SD_DATA1_GPIO_NUM            21
-#define SD_DATA2_GPIO_NUM            22
-#define SD_DATA3_GPIO_NUM            23
-
-#define USB_INT_PHY0_DM_GPIO_NUM              12
-#define USB_INT_PHY0_DP_GPIO_NUM              13
-
-#define EXT_OSC_SLOW_GPIO_NUM        0
-
-#define MAX_RTC_GPIO_NUM              7
-#define MAX_PAD_GPIO_NUM             30
-#define MAX_GPIO_NUM                 34
-#define DIG_IO_HOLD_BIT_SHIFT        32
-
-
-#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
-#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
-
-#define CLK_OUT3                                    0x1f
-#define CLK_OUT3_V                                  CLK_OUT3
-#define CLK_OUT3_S                                  10
-#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
-#define CLK_OUT2                                    0x1f
-#define CLK_OUT2_V                                  CLK_OUT2
-#define CLK_OUT2_S                                  5
-#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
-#define CLK_OUT1                                    0x1f
-#define CLK_OUT1_V                                  CLK_OUT1
-#define CLK_OUT1_S                                  0
-#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
-// definitions above are inherited from previous version of code, should double check
-
-// definitions below are generated from pin_txt.csv
-#define PERIPHS_IO_MUX_XTAL_32K_P_U           (REG_IO_MUX_BASE + 0x4)
-#define FUNC_XTAL_32K_P_GPIO0                                       1
-#define FUNC_XTAL_32K_P_GPIO0_0                                     0
-
-#define PERIPHS_IO_MUX_XTAL_32K_N_U           (REG_IO_MUX_BASE + 0x8)
-#define FUNC_XTAL_32K_N_GPIO1                                       1
-#define FUNC_XTAL_32K_N_GPIO1_0                                     0
-
-#define PERIPHS_IO_MUX_GPIO2_U                (REG_IO_MUX_BASE + 0xC)
-#define FUNC_GPIO2_FSPIQ                                            2
-#define FUNC_GPIO2_GPIO2                                            1
-#define FUNC_GPIO2_GPIO2_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO3_U               (REG_IO_MUX_BASE + 0x10)
-#define FUNC_GPIO3_GPIO3                                            1
-#define FUNC_GPIO3_GPIO3_0                                          0
-
-#define PERIPHS_IO_MUX_MTMS_U                (REG_IO_MUX_BASE + 0x14)
-#define FUNC_MTMS_FSPIHD                                            2
-#define FUNC_MTMS_GPIO4                                             1
-#define FUNC_MTMS_MTMS                                              0
-
-#define PERIPHS_IO_MUX_MTDI_U                (REG_IO_MUX_BASE + 0x18)
-#define FUNC_MTDI_FSPIWP                                            2
-#define FUNC_MTDI_GPIO5                                             1
-#define FUNC_MTDI_MTDI                                              0
-
-#define PERIPHS_IO_MUX_MTCK_U                (REG_IO_MUX_BASE + 0x1C)
-#define FUNC_MTCK_FSPICLK                                           2
-#define FUNC_MTCK_GPIO6                                             1
-#define FUNC_MTCK_MTCK                                              0
-
-#define PERIPHS_IO_MUX_MTDO_U                (REG_IO_MUX_BASE + 0x20)
-#define FUNC_MTDO_FSPID                                             2
-#define FUNC_MTDO_GPIO7                                             1
-#define FUNC_MTDO_MTDO                                              0
-
-#define PERIPHS_IO_MUX_GPIO8_U               (REG_IO_MUX_BASE + 0x24)
-#define FUNC_GPIO8_GPIO8                                            1
-#define FUNC_GPIO8_GPIO8_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO9_U               (REG_IO_MUX_BASE + 0x28)
-#define FUNC_GPIO9_GPIO9                                            1
-#define FUNC_GPIO9_GPIO9_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO10_U              (REG_IO_MUX_BASE + 0x2C)
-#define FUNC_GPIO10_GPIO10                                          1
-#define FUNC_GPIO10_GPIO10_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO11_U              (REG_IO_MUX_BASE + 0x30)
-#define FUNC_GPIO11_GPIO11                                          1
-#define FUNC_GPIO11_GPIO11_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO12_U              (REG_IO_MUX_BASE + 0x34)
-#define FUNC_GPIO12_GPIO12                                          1
-#define FUNC_GPIO12_GPIO12_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO13_U              (REG_IO_MUX_BASE + 0x38)
-#define FUNC_GPIO13_GPIO13                                          1
-#define FUNC_GPIO13_GPIO13_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO14_U              (REG_IO_MUX_BASE + 0x3C)
-#define FUNC_GPIO14_GPIO14                                          1
-#define FUNC_GPIO14_GPIO14_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO15_U              (REG_IO_MUX_BASE + 0x40)
-#define FUNC_GPIO15_GPIO15                                          1
-#define FUNC_GPIO15_GPIO15_0                                        0
-
-#define PERIPHS_IO_MUX_U0TXD_U               (REG_IO_MUX_BASE + 0x44)
-#define FUNC_U0TXD_FSPICS0                                          2
-#define FUNC_U0TXD_GPIO16                                           1
-#define FUNC_U0TXD_U0TXD                                            0
-
-#define PERIPHS_IO_MUX_U0RXD_U               (REG_IO_MUX_BASE + 0x48)
-#define FUNC_U0RXD_FSPICS1                                          2
-#define FUNC_U0RXD_GPIO17                                           1
-#define FUNC_U0RXD_U0RXD                                            0
-
-#define PERIPHS_IO_MUX_SDIO_CMD_U            (REG_IO_MUX_BASE + 0x4C)
-#define FUNC_SDIO_CMD_FSPICS2                                       2
-#define FUNC_SDIO_CMD_GPIO18                                        1
-#define FUNC_SDIO_CMD_SDIO_CMD                                      0
-
-#define PERIPHS_IO_MUX_SDIO_CLK_U            (REG_IO_MUX_BASE + 0x50)
-#define FUNC_SDIO_CLK_FSPICS3                                       2
-#define FUNC_SDIO_CLK_GPIO19                                        1
-#define FUNC_SDIO_CLK_SDIO_CLK                                      0
-
-#define PERIPHS_IO_MUX_SDIO_DATA0_U          (REG_IO_MUX_BASE + 0x54)
-#define FUNC_SDIO_DATA0_FSPICS4                                     2
-#define FUNC_SDIO_DATA0_GPIO20                                      1
-#define FUNC_SDIO_DATA0_SDIO_DATA0                                  0
-
-#define PERIPHS_IO_MUX_SDIO_DATA1_U          (REG_IO_MUX_BASE + 0x58)
-#define FUNC_SDIO_DATA1_FSPICS5                                     2
-#define FUNC_SDIO_DATA1_GPIO21                                      1
-#define FUNC_SDIO_DATA1_SDIO_DATA1                                  0
-
-#define PERIPHS_IO_MUX_SDIO_DATA2_U          (REG_IO_MUX_BASE + 0x5C)
-#define FUNC_SDIO_DATA2_GPIO22                                      1
-#define FUNC_SDIO_DATA2_SDIO_DATA2                                  0
-
-#define PERIPHS_IO_MUX_SDIO_DATA3_U          (REG_IO_MUX_BASE + 0x60)
-#define FUNC_SDIO_DATA3_GPIO23                                      1
-#define FUNC_SDIO_DATA3_SDIO_DATA3                                  0
-
-#define PERIPHS_IO_MUX_SPICS0_U              (REG_IO_MUX_BASE + 0x64)
-#define FUNC_SPICS0_GPIO24                                          1
-#define FUNC_SPICS0_SPICS0                                          0
-
-#define PERIPHS_IO_MUX_SPIQ_U                (REG_IO_MUX_BASE + 0x68)
-#define FUNC_SPIQ_GPIO25                                            1
-#define FUNC_SPIQ_SPIQ                                              0
-
-#define PERIPHS_IO_MUX_SPIWP_U               (REG_IO_MUX_BASE + 0x6C)
-#define FUNC_SPIWP_GPIO26                                           1
-#define FUNC_SPIWP_SPIWP                                            0
-
-#define PERIPHS_IO_MUX_VDD_SPI_U             (REG_IO_MUX_BASE + 0x70)
-#define FUNC_VDD_SPI_GPIO27                                         1
-#define FUNC_VDD_SPI_GPIO27_0                                       0
-
-#define PERIPHS_IO_MUX_SPIHD_U               (REG_IO_MUX_BASE + 0x74)
-#define FUNC_SPIHD_GPIO28                                           1
-#define FUNC_SPIHD_SPIHD                                            0
-
-#define PERIPHS_IO_MUX_SPICLK_U              (REG_IO_MUX_BASE + 0x78)
-#define FUNC_SPICLK_GPIO29                                          1
-#define FUNC_SPICLK_SPICLK                                          0
-
-#define PERIPHS_IO_MUX_SPID_U                (REG_IO_MUX_BASE + 0x7C)
-#define FUNC_SPID_GPIO30                                            1
-#define FUNC_SPID_SPID                                              0
-
-/** IO_MUX_PIN_CTRL_REG register
- *  Clock Output Configuration Register
- */
-#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
-/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15;
- *  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
- *  CLK_OUT_out1 can be found in peripheral output signals.
- */
-#define IO_MUX_CLK_OUT1    0x0000001FU
-#define IO_MUX_CLK_OUT1_M  (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
-#define IO_MUX_CLK_OUT1_V  0x0000001FU
-#define IO_MUX_CLK_OUT1_S  0
-/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15;
- *  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
- *  CLK_OUT_out2 can be found in peripheral output signals.
- */
-#define IO_MUX_CLK_OUT2    0x0000001FU
-#define IO_MUX_CLK_OUT2_M  (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
-#define IO_MUX_CLK_OUT2_V  0x0000001FU
-#define IO_MUX_CLK_OUT2_S  5
-/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7;
- *  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
- *  CLK_OUT_out3 can be found in peripheral output signals.
- */
-#define IO_MUX_CLK_OUT3    0x0000001FU
-#define IO_MUX_CLK_OUT3_M  (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
-#define IO_MUX_CLK_OUT3_V  0x0000001FU
-#define IO_MUX_CLK_OUT3_S  10
-
-/** IO_MUX_MODEM_DIAG_EN_REG register
- *  GPIO MATRIX Configure Register for modem diag
- */
-#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
-/** IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [31:0]; default: 0;
- *  bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio
- *  matrix. 0:enable other signals into gpio matrix
- */
-#define IO_MUX_MODEM_DIAG_EN    0xFFFFFFFFU
-#define IO_MUX_MODEM_DIAG_EN_M  (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
-#define IO_MUX_MODEM_DIAG_EN_V  0xFFFFFFFFU
-#define IO_MUX_MODEM_DIAG_EN_S  0
-
-/** IO_MUX_DATE_REG register
- *  IO MUX Version Control Register
- */
-#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
-/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 35655776;
- *  Version control register
- */
-#define IO_MUX_REG_DATE    0x0FFFFFFFU
-#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
-#define IO_MUX_REG_DATE_V  0x0FFFFFFFU
-#define IO_MUX_REG_DATE_S  0
diff --git a/components/soc/esp32c6/include/soc/lp_uart_reg.h b/components/soc/esp32c6/include/soc/lp_uart_reg.h
deleted file mode 100644
index b67fa1b59e8..00000000000
--- a/components/soc/esp32c6/include/soc/lp_uart_reg.h
+++ /dev/null
@@ -1,1381 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_UART_FIFO_REG register
- *  FIFO data register
- */
-#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0)
-/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
- *  UART $n accesses FIFO via this register.
- */
-#define LP_UART_RXFIFO_RD_BYTE    0x000000FFU
-#define LP_UART_RXFIFO_RD_BYTE_M  (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S)
-#define LP_UART_RXFIFO_RD_BYTE_V  0x000000FFU
-#define LP_UART_RXFIFO_RD_BYTE_S  0
-
-/** LP_UART_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4)
-/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  what rxfifo_full_thrhd specifies.
- */
-#define LP_UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_RAW_M  (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S)
-#define LP_UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_RAW_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
- *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- *  less than what txfifo_empty_thrhd specifies .
- */
-#define LP_UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_M  (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S)
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_S  1
-/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error in
- *  the data.
- */
-#define LP_UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_RAW_M  (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S)
-#define LP_UART_PARITY_ERR_INT_RAW_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_RAW_S  2
-/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  .
- */
-#define LP_UART_FRM_ERR_INT_RAW    (BIT(3))
-#define LP_UART_FRM_ERR_INT_RAW_M  (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S)
-#define LP_UART_FRM_ERR_INT_RAW_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_RAW_S  3
-/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  the FIFO can store.
- */
-#define LP_UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_RAW_M  (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S)
-#define LP_UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_RAW_S  4
-/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  DSRn signal.
- */
-#define LP_UART_DSR_CHG_INT_RAW    (BIT(5))
-#define LP_UART_DSR_CHG_INT_RAW_M  (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S)
-#define LP_UART_DSR_CHG_INT_RAW_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_RAW_S  5
-/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  CTSn signal.
- */
-#define LP_UART_CTS_CHG_INT_RAW    (BIT(6))
-#define LP_UART_CTS_CHG_INT_RAW_M  (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S)
-#define LP_UART_CTS_CHG_INT_RAW_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_RAW_S  6
-/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
- *  bit.
- */
-#define LP_UART_BRK_DET_INT_RAW    (BIT(7))
-#define LP_UART_BRK_DET_INT_RAW_M  (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S)
-#define LP_UART_BRK_DET_INT_RAW_V  0x00000001U
-#define LP_UART_BRK_DET_INT_RAW_S  7
-/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  This interrupt raw bit turns to high level when receiver takes more time than
- *  rx_tout_thrhd to receive a byte.
- */
-#define LP_UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_RAW_M  (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S)
-#define LP_UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_RAW_S  8
-/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define LP_UART_SW_XON_INT_RAW    (BIT(9))
-#define LP_UART_SW_XON_INT_RAW_M  (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S)
-#define LP_UART_SW_XON_INT_RAW_V  0x00000001U
-#define LP_UART_SW_XON_INT_RAW_S  9
-/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives Xoff char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define LP_UART_SW_XOFF_INT_RAW    (BIT(10))
-#define LP_UART_SW_XOFF_INT_RAW_M  (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S)
-#define LP_UART_SW_XOFF_INT_RAW_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_RAW_S  10
-/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a glitch in the
- *  middle of a start bit.
- */
-#define LP_UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_RAW_M  (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S)
-#define LP_UART_GLITCH_DET_INT_RAW_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_RAW_S  11
-/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter completes  sending
- *  NULL characters after all data in Tx-FIFO are sent.
- */
-#define LP_UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_RAW_M  (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S)
-#define LP_UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_RAW_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has kept the shortest
- *  duration after sending the  last data.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M  (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has send out all data
- *  in FIFO.
- */
-#define LP_UART_TX_DONE_INT_RAW    (BIT(14))
-#define LP_UART_TX_DONE_INT_RAW_M  (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S)
-#define LP_UART_TX_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_DONE_INT_RAW_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the configured
- *  at_cmd char.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M  (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  This interrupt raw bit turns to high level when input rxd edge changes more times
- *  than what reg_active_threshold specifies in light sleeping mode.
- */
-#define LP_UART_WAKEUP_INT_RAW    (BIT(19))
-#define LP_UART_WAKEUP_INT_RAW_M  (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S)
-#define LP_UART_WAKEUP_INT_RAW_V  0x00000001U
-#define LP_UART_WAKEUP_INT_RAW_S  19
-
-/** LP_UART_INT_ST_REG register
- *  Masked interrupt status
- */
-#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8)
-/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
- *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_ST_M  (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S)
-#define LP_UART_RXFIFO_FULL_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_ST_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
- *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
- *  to 1.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_ST_M  (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S)
-#define LP_UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_ST_S  1
-/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
- *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
- */
-#define LP_UART_PARITY_ERR_INT_ST    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_ST_M  (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S)
-#define LP_UART_PARITY_ERR_INT_ST_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_ST_S  2
-/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
- *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
- */
-#define LP_UART_FRM_ERR_INT_ST    (BIT(3))
-#define LP_UART_FRM_ERR_INT_ST_M  (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S)
-#define LP_UART_FRM_ERR_INT_ST_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_ST_S  3
-/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_ST_M  (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S)
-#define LP_UART_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_ST_S  4
-/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
- */
-#define LP_UART_DSR_CHG_INT_ST    (BIT(5))
-#define LP_UART_DSR_CHG_INT_ST_M  (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S)
-#define LP_UART_DSR_CHG_INT_ST_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_ST_S  5
-/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
- *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
- */
-#define LP_UART_CTS_CHG_INT_ST    (BIT(6))
-#define LP_UART_CTS_CHG_INT_ST_M  (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S)
-#define LP_UART_CTS_CHG_INT_ST_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_ST_S  6
-/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
- *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
- */
-#define LP_UART_BRK_DET_INT_ST    (BIT(7))
-#define LP_UART_BRK_DET_INT_ST_M  (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S)
-#define LP_UART_BRK_DET_INT_ST_V  0x00000001U
-#define LP_UART_BRK_DET_INT_ST_S  7
-/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_ST_M  (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S)
-#define LP_UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_ST_S  8
-/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
- *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
- */
-#define LP_UART_SW_XON_INT_ST    (BIT(9))
-#define LP_UART_SW_XON_INT_ST_M  (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S)
-#define LP_UART_SW_XON_INT_ST_V  0x00000001U
-#define LP_UART_SW_XON_INT_ST_S  9
-/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
- *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
- */
-#define LP_UART_SW_XOFF_INT_ST    (BIT(10))
-#define LP_UART_SW_XOFF_INT_ST_M  (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S)
-#define LP_UART_SW_XOFF_INT_ST_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_ST_S  10
-/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
- *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
- */
-#define LP_UART_GLITCH_DET_INT_ST    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_ST_M  (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S)
-#define LP_UART_GLITCH_DET_INT_ST_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_ST_S  11
-/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
- */
-#define LP_UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_ST_M  (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S)
-#define LP_UART_TX_BRK_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_ST_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- *  is set to 1.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
- */
-#define LP_UART_TX_DONE_INT_ST    (BIT(14))
-#define LP_UART_TX_DONE_INT_ST_M  (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S)
-#define LP_UART_TX_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_DONE_INT_ST_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
- *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
- *  to 1.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M  (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
- *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
- */
-#define LP_UART_WAKEUP_INT_ST    (BIT(19))
-#define LP_UART_WAKEUP_INT_ST_M  (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S)
-#define LP_UART_WAKEUP_INT_ST_V  0x00000001U
-#define LP_UART_WAKEUP_INT_ST_S  19
-
-/** LP_UART_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc)
-/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  This is the enable bit for rxfifo_full_int_st register.
- */
-#define LP_UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_ENA_M  (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S)
-#define LP_UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_ENA_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  This is the enable bit for txfifo_empty_int_st register.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_M  (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S)
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_S  1
-/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  This is the enable bit for parity_err_int_st register.
- */
-#define LP_UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_ENA_M  (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S)
-#define LP_UART_PARITY_ERR_INT_ENA_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_ENA_S  2
-/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  This is the enable bit for frm_err_int_st register.
- */
-#define LP_UART_FRM_ERR_INT_ENA    (BIT(3))
-#define LP_UART_FRM_ERR_INT_ENA_M  (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S)
-#define LP_UART_FRM_ERR_INT_ENA_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_ENA_S  3
-/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  This is the enable bit for rxfifo_ovf_int_st register.
- */
-#define LP_UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_ENA_M  (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S)
-#define LP_UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_ENA_S  4
-/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for dsr_chg_int_st register.
- */
-#define LP_UART_DSR_CHG_INT_ENA    (BIT(5))
-#define LP_UART_DSR_CHG_INT_ENA_M  (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S)
-#define LP_UART_DSR_CHG_INT_ENA_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_ENA_S  5
-/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  This is the enable bit for cts_chg_int_st register.
- */
-#define LP_UART_CTS_CHG_INT_ENA    (BIT(6))
-#define LP_UART_CTS_CHG_INT_ENA_M  (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S)
-#define LP_UART_CTS_CHG_INT_ENA_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_ENA_S  6
-/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  This is the enable bit for brk_det_int_st register.
- */
-#define LP_UART_BRK_DET_INT_ENA    (BIT(7))
-#define LP_UART_BRK_DET_INT_ENA_M  (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S)
-#define LP_UART_BRK_DET_INT_ENA_V  0x00000001U
-#define LP_UART_BRK_DET_INT_ENA_S  7
-/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  This is the enable bit for rxfifo_tout_int_st register.
- */
-#define LP_UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_ENA_M  (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S)
-#define LP_UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_ENA_S  8
-/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  This is the enable bit for sw_xon_int_st register.
- */
-#define LP_UART_SW_XON_INT_ENA    (BIT(9))
-#define LP_UART_SW_XON_INT_ENA_M  (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S)
-#define LP_UART_SW_XON_INT_ENA_V  0x00000001U
-#define LP_UART_SW_XON_INT_ENA_S  9
-/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  This is the enable bit for sw_xoff_int_st register.
- */
-#define LP_UART_SW_XOFF_INT_ENA    (BIT(10))
-#define LP_UART_SW_XOFF_INT_ENA_M  (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S)
-#define LP_UART_SW_XOFF_INT_ENA_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_ENA_S  10
-/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  This is the enable bit for glitch_det_int_st register.
- */
-#define LP_UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_ENA_M  (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S)
-#define LP_UART_GLITCH_DET_INT_ENA_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_ENA_S  11
-/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for tx_brk_done_int_st register.
- */
-#define LP_UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_ENA_M  (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S)
-#define LP_UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_ENA_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit for tx_brk_idle_done_int_st register.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for tx_done_int_st register.
- */
-#define LP_UART_TX_DONE_INT_ENA    (BIT(14))
-#define LP_UART_TX_DONE_INT_ENA_M  (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S)
-#define LP_UART_TX_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_DONE_INT_ENA_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  This is the enable bit for at_cmd_char_det_int_st register.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M  (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for uart_wakeup_int_st register.
- */
-#define LP_UART_WAKEUP_INT_ENA    (BIT(19))
-#define LP_UART_WAKEUP_INT_ENA_M  (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S)
-#define LP_UART_WAKEUP_INT_ENA_V  0x00000001U
-#define LP_UART_WAKEUP_INT_ENA_S  19
-
-/** LP_UART_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10)
-/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the rxfifo_full_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_CLR_M  (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S)
-#define LP_UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_CLR_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear txfifo_empty_int_raw interrupt.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_M  (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S)
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_S  1
-/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear parity_err_int_raw interrupt.
- */
-#define LP_UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_CLR_M  (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S)
-#define LP_UART_PARITY_ERR_INT_CLR_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_CLR_S  2
-/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear frm_err_int_raw interrupt.
- */
-#define LP_UART_FRM_ERR_INT_CLR    (BIT(3))
-#define LP_UART_FRM_ERR_INT_CLR_M  (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S)
-#define LP_UART_FRM_ERR_INT_CLR_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_CLR_S  3
-/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_CLR_M  (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S)
-#define LP_UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_CLR_S  4
-/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the dsr_chg_int_raw interrupt.
- */
-#define LP_UART_DSR_CHG_INT_CLR    (BIT(5))
-#define LP_UART_DSR_CHG_INT_CLR_M  (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S)
-#define LP_UART_DSR_CHG_INT_CLR_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_CLR_S  5
-/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the cts_chg_int_raw interrupt.
- */
-#define LP_UART_CTS_CHG_INT_CLR    (BIT(6))
-#define LP_UART_CTS_CHG_INT_CLR_M  (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S)
-#define LP_UART_CTS_CHG_INT_CLR_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_CLR_S  6
-/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the brk_det_int_raw interrupt.
- */
-#define LP_UART_BRK_DET_INT_CLR    (BIT(7))
-#define LP_UART_BRK_DET_INT_CLR_M  (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S)
-#define LP_UART_BRK_DET_INT_CLR_V  0x00000001U
-#define LP_UART_BRK_DET_INT_CLR_S  7
-/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_CLR_M  (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S)
-#define LP_UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_CLR_S  8
-/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the sw_xon_int_raw interrupt.
- */
-#define LP_UART_SW_XON_INT_CLR    (BIT(9))
-#define LP_UART_SW_XON_INT_CLR_M  (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S)
-#define LP_UART_SW_XON_INT_CLR_V  0x00000001U
-#define LP_UART_SW_XON_INT_CLR_S  9
-/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the sw_xoff_int_raw interrupt.
- */
-#define LP_UART_SW_XOFF_INT_CLR    (BIT(10))
-#define LP_UART_SW_XOFF_INT_CLR_M  (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S)
-#define LP_UART_SW_XOFF_INT_CLR_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_CLR_S  10
-/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the glitch_det_int_raw interrupt.
- */
-#define LP_UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_CLR_M  (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S)
-#define LP_UART_GLITCH_DET_INT_CLR_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_CLR_S  11
-/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the tx_brk_done_int_raw interrupt..
- */
-#define LP_UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_CLR_M  (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S)
-#define LP_UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_CLR_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M  (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the tx_done_int_raw interrupt.
- */
-#define LP_UART_TX_DONE_INT_CLR    (BIT(14))
-#define LP_UART_TX_DONE_INT_CLR_M  (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S)
-#define LP_UART_TX_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_DONE_INT_CLR_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M  (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the uart_wakeup_int_raw interrupt.
- */
-#define LP_UART_WAKEUP_INT_CLR    (BIT(19))
-#define LP_UART_WAKEUP_INT_CLR_M  (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S)
-#define LP_UART_WAKEUP_INT_CLR_V  0x00000001U
-#define LP_UART_WAKEUP_INT_CLR_S  19
-
-/** LP_UART_CLKDIV_SYNC_REG register
- *  Clock divider configuration
- */
-#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14)
-/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
- *  The integral part of the frequency divider factor.
- */
-#define LP_UART_CLKDIV    0x00000FFFU
-#define LP_UART_CLKDIV_M  (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S)
-#define LP_UART_CLKDIV_V  0x00000FFFU
-#define LP_UART_CLKDIV_S  0
-/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
- *  The decimal part of the frequency divider factor.
- */
-#define LP_UART_CLKDIV_FRAG    0x0000000FU
-#define LP_UART_CLKDIV_FRAG_M  (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S)
-#define LP_UART_CLKDIV_FRAG_V  0x0000000FU
-#define LP_UART_CLKDIV_FRAG_S  20
-
-/** LP_UART_RX_FILT_REG register
- *  Rx Filter configuration
- */
-#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18)
-/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
- *  when input pulse width is lower than this value the pulse is ignored.
- */
-#define LP_UART_GLITCH_FILT    0x000000FFU
-#define LP_UART_GLITCH_FILT_M  (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S)
-#define LP_UART_GLITCH_FILT_V  0x000000FFU
-#define LP_UART_GLITCH_FILT_S  0
-/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable Rx signal filter.
- */
-#define LP_UART_GLITCH_FILT_EN    (BIT(8))
-#define LP_UART_GLITCH_FILT_EN_M  (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S)
-#define LP_UART_GLITCH_FILT_EN_V  0x00000001U
-#define LP_UART_GLITCH_FILT_EN_S  8
-
-/** LP_UART_STATUS_REG register
- *  UART status register
- */
-#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c)
-/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0;
- *  Stores the byte number of valid data in Rx-FIFO.
- */
-#define LP_UART_RXFIFO_CNT    0x0000001FU
-#define LP_UART_RXFIFO_CNT_M  (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S)
-#define LP_UART_RXFIFO_CNT_V  0x0000001FU
-#define LP_UART_RXFIFO_CNT_S  3
-/** LP_UART_DSRN : RO; bitpos: [13]; default: 0;
- *  The register represent the level value of the internal uart dsr signal.
- */
-#define LP_UART_DSRN    (BIT(13))
-#define LP_UART_DSRN_M  (LP_UART_DSRN_V << LP_UART_DSRN_S)
-#define LP_UART_DSRN_V  0x00000001U
-#define LP_UART_DSRN_S  13
-/** LP_UART_CTSN : RO; bitpos: [14]; default: 1;
- *  This register represent the level value of the internal uart cts signal.
- */
-#define LP_UART_CTSN    (BIT(14))
-#define LP_UART_CTSN_M  (LP_UART_CTSN_V << LP_UART_CTSN_S)
-#define LP_UART_CTSN_V  0x00000001U
-#define LP_UART_CTSN_S  14
-/** LP_UART_RXD : RO; bitpos: [15]; default: 1;
- *  This register represent the  level value of the internal uart rxd signal.
- */
-#define LP_UART_RXD    (BIT(15))
-#define LP_UART_RXD_M  (LP_UART_RXD_V << LP_UART_RXD_S)
-#define LP_UART_RXD_V  0x00000001U
-#define LP_UART_RXD_S  15
-/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0;
- *  Stores the byte number of data in Tx-FIFO.
- */
-#define LP_UART_TXFIFO_CNT    0x0000001FU
-#define LP_UART_TXFIFO_CNT_M  (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S)
-#define LP_UART_TXFIFO_CNT_V  0x0000001FU
-#define LP_UART_TXFIFO_CNT_S  19
-/** LP_UART_DTRN : RO; bitpos: [29]; default: 1;
- *  This bit represents the level of the internal uart dtr signal.
- */
-#define LP_UART_DTRN    (BIT(29))
-#define LP_UART_DTRN_M  (LP_UART_DTRN_V << LP_UART_DTRN_S)
-#define LP_UART_DTRN_V  0x00000001U
-#define LP_UART_DTRN_S  29
-/** LP_UART_RTSN : RO; bitpos: [30]; default: 1;
- *  This bit represents the level of the internal uart rts signal.
- */
-#define LP_UART_RTSN    (BIT(30))
-#define LP_UART_RTSN_M  (LP_UART_RTSN_V << LP_UART_RTSN_S)
-#define LP_UART_RTSN_V  0x00000001U
-#define LP_UART_RTSN_S  30
-/** LP_UART_TXD : RO; bitpos: [31]; default: 1;
- *  This bit represents the  level of the internal uart txd signal.
- */
-#define LP_UART_TXD    (BIT(31))
-#define LP_UART_TXD_M  (LP_UART_TXD_V << LP_UART_TXD_S)
-#define LP_UART_TXD_V  0x00000001U
-#define LP_UART_TXD_S  31
-
-/** LP_UART_CONF0_SYNC_REG register
- *  Configuration register 0
- */
-#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20)
-/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0;
- *  This register is used to configure the parity check mode.
- */
-#define LP_UART_PARITY    (BIT(0))
-#define LP_UART_PARITY_M  (LP_UART_PARITY_V << LP_UART_PARITY_S)
-#define LP_UART_PARITY_V  0x00000001U
-#define LP_UART_PARITY_S  0
-/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable uart parity check.
- */
-#define LP_UART_PARITY_EN    (BIT(1))
-#define LP_UART_PARITY_EN_M  (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S)
-#define LP_UART_PARITY_EN_V  0x00000001U
-#define LP_UART_PARITY_EN_S  1
-/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
- *  This register is used to set the length of data.
- */
-#define LP_UART_BIT_NUM    0x00000003U
-#define LP_UART_BIT_NUM_M  (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S)
-#define LP_UART_BIT_NUM_V  0x00000003U
-#define LP_UART_BIT_NUM_S  2
-/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
- *  This register is used to set the length of  stop bit.
- */
-#define LP_UART_STOP_BIT_NUM    0x00000003U
-#define LP_UART_STOP_BIT_NUM_M  (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S)
-#define LP_UART_STOP_BIT_NUM_V  0x00000003U
-#define LP_UART_STOP_BIT_NUM_S  4
-/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
- *  is done.
- */
-#define LP_UART_TXD_BRK    (BIT(6))
-#define LP_UART_TXD_BRK_M  (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S)
-#define LP_UART_TXD_BRK_V  0x00000001U
-#define LP_UART_TXD_BRK_S  6
-/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable uart loopback test mode.
- */
-#define LP_UART_LOOPBACK    (BIT(12))
-#define LP_UART_LOOPBACK_M  (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S)
-#define LP_UART_LOOPBACK_V  0x00000001U
-#define LP_UART_LOOPBACK_S  12
-/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
- *  Set this bit to enable flow control function for transmitter.
- */
-#define LP_UART_TX_FLOW_EN    (BIT(13))
-#define LP_UART_TX_FLOW_EN_M  (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S)
-#define LP_UART_TX_FLOW_EN_V  0x00000001U
-#define LP_UART_TX_FLOW_EN_S  13
-/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0;
- *  Set this bit to inverse the level value of uart rxd signal.
- */
-#define LP_UART_RXD_INV    (BIT(15))
-#define LP_UART_RXD_INV_M  (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S)
-#define LP_UART_RXD_INV_V  0x00000001U
-#define LP_UART_RXD_INV_S  15
-/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart txd signal.
- */
-#define LP_UART_TXD_INV    (BIT(16))
-#define LP_UART_TXD_INV_M  (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S)
-#define LP_UART_TXD_INV_V  0x00000001U
-#define LP_UART_TXD_INV_S  16
-/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
- *  Disable UART Rx data overflow detect.
- */
-#define LP_UART_DIS_RX_DAT_OVF    (BIT(17))
-#define LP_UART_DIS_RX_DAT_OVF_M  (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S)
-#define LP_UART_DIS_RX_DAT_OVF_V  0x00000001U
-#define LP_UART_DIS_RX_DAT_OVF_S  17
-/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
- *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
- *  stores the data even if the  received data is wrong.
- */
-#define LP_UART_ERR_WR_MASK    (BIT(18))
-#define LP_UART_ERR_WR_MASK_M  (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S)
-#define LP_UART_ERR_WR_MASK_V  0x00000001U
-#define LP_UART_ERR_WR_MASK_S  18
-/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
- *  UART memory clock gate enable signal.
- */
-#define LP_UART_MEM_CLK_EN    (BIT(20))
-#define LP_UART_MEM_CLK_EN_M  (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S)
-#define LP_UART_MEM_CLK_EN_V  0x00000001U
-#define LP_UART_MEM_CLK_EN_S  20
-/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0;
- *  This register is used to configure the software rts signal which is used in
- *  software flow control.
- */
-#define LP_UART_SW_RTS    (BIT(21))
-#define LP_UART_SW_RTS_M  (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S)
-#define LP_UART_SW_RTS_V  0x00000001U
-#define LP_UART_SW_RTS_S  21
-/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
- *  Set this bit to reset the uart receive-FIFO.
- */
-#define LP_UART_RXFIFO_RST    (BIT(22))
-#define LP_UART_RXFIFO_RST_M  (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S)
-#define LP_UART_RXFIFO_RST_V  0x00000001U
-#define LP_UART_RXFIFO_RST_S  22
-/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
- *  Set this bit to reset the uart transmit-FIFO.
- */
-#define LP_UART_TXFIFO_RST    (BIT(23))
-#define LP_UART_TXFIFO_RST_M  (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S)
-#define LP_UART_TXFIFO_RST_V  0x00000001U
-#define LP_UART_TXFIFO_RST_S  23
-
-/** LP_UART_CONF1_REG register
- *  Configuration register 1
- */
-#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24)
-/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12;
- *  It will produce rxfifo_full_int interrupt when receiver receives more data than
- *  this register value.
- */
-#define LP_UART_RXFIFO_FULL_THRHD    0x0000001FU
-#define LP_UART_RXFIFO_FULL_THRHD_M  (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S)
-#define LP_UART_RXFIFO_FULL_THRHD_V  0x0000001FU
-#define LP_UART_RXFIFO_FULL_THRHD_S  3
-/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12;
- *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
- *  than this register value.
- */
-#define LP_UART_TXFIFO_EMPTY_THRHD    0x0000001FU
-#define LP_UART_TXFIFO_EMPTY_THRHD_M  (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S)
-#define LP_UART_TXFIFO_EMPTY_THRHD_V  0x0000001FU
-#define LP_UART_TXFIFO_EMPTY_THRHD_S  11
-/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart cts signal.
- */
-#define LP_UART_CTS_INV    (BIT(16))
-#define LP_UART_CTS_INV_M  (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S)
-#define LP_UART_CTS_INV_V  0x00000001U
-#define LP_UART_CTS_INV_S  16
-/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0;
- *  Set this bit to inverse the level value of uart dsr signal.
- */
-#define LP_UART_DSR_INV    (BIT(17))
-#define LP_UART_DSR_INV_M  (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S)
-#define LP_UART_DSR_INV_V  0x00000001U
-#define LP_UART_DSR_INV_S  17
-/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0;
- *  Set this bit to inverse the level value of uart rts signal.
- */
-#define LP_UART_RTS_INV    (BIT(18))
-#define LP_UART_RTS_INV_M  (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S)
-#define LP_UART_RTS_INV_V  0x00000001U
-#define LP_UART_RTS_INV_S  18
-/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0;
- *  Set this bit to inverse the level value of uart dtr signal.
- */
-#define LP_UART_DTR_INV    (BIT(19))
-#define LP_UART_DTR_INV_M  (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S)
-#define LP_UART_DTR_INV_V  0x00000001U
-#define LP_UART_DTR_INV_S  19
-/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0;
- *  This register is used to configure the software dtr signal which is used in
- *  software flow control.
- */
-#define LP_UART_SW_DTR    (BIT(20))
-#define LP_UART_SW_DTR_M  (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S)
-#define LP_UART_SW_DTR_V  0x00000001U
-#define LP_UART_SW_DTR_S  20
-/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define LP_UART_CLK_EN    (BIT(21))
-#define LP_UART_CLK_EN_M  (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S)
-#define LP_UART_CLK_EN_V  0x00000001U
-#define LP_UART_CLK_EN_S  21
-
-/** LP_UART_HWFC_CONF_SYNC_REG register
- *  Hardware flow-control configuration
- */
-#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c)
-/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0;
- *  This register is used to configure the maximum amount of data that can be received
- *  when hardware flow control works.
- */
-#define LP_UART_RX_FLOW_THRHD    0x0000001FU
-#define LP_UART_RX_FLOW_THRHD_M  (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S)
-#define LP_UART_RX_FLOW_THRHD_V  0x0000001FU
-#define LP_UART_RX_FLOW_THRHD_S  3
-/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
- *  This is the flow enable bit for UART receiver.
- */
-#define LP_UART_RX_FLOW_EN    (BIT(8))
-#define LP_UART_RX_FLOW_EN_M  (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S)
-#define LP_UART_RX_FLOW_EN_V  0x00000001U
-#define LP_UART_RX_FLOW_EN_S  8
-
-/** LP_UART_SLEEP_CONF0_REG register
- *  UART sleep configure register 0
- */
-#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30)
-/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified wake up char1 to wake up
- */
-#define LP_UART_WK_CHAR1    0x000000FFU
-#define LP_UART_WK_CHAR1_M  (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S)
-#define LP_UART_WK_CHAR1_V  0x000000FFU
-#define LP_UART_WK_CHAR1_S  0
-/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
- *  This register restores the specified wake up char2 to wake up
- */
-#define LP_UART_WK_CHAR2    0x000000FFU
-#define LP_UART_WK_CHAR2_M  (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S)
-#define LP_UART_WK_CHAR2_V  0x000000FFU
-#define LP_UART_WK_CHAR2_S  8
-/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
- *  This register restores the specified wake up char3 to wake up
- */
-#define LP_UART_WK_CHAR3    0x000000FFU
-#define LP_UART_WK_CHAR3_M  (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S)
-#define LP_UART_WK_CHAR3_V  0x000000FFU
-#define LP_UART_WK_CHAR3_S  16
-/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
- *  This register restores the specified wake up char4 to wake up
- */
-#define LP_UART_WK_CHAR4    0x000000FFU
-#define LP_UART_WK_CHAR4_M  (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S)
-#define LP_UART_WK_CHAR4_V  0x000000FFU
-#define LP_UART_WK_CHAR4_S  24
-
-/** LP_UART_SLEEP_CONF1_REG register
- *  UART sleep configure register 1
- */
-#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34)
-/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified char0 to wake up
- */
-#define LP_UART_WK_CHAR0    0x000000FFU
-#define LP_UART_WK_CHAR0_M  (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S)
-#define LP_UART_WK_CHAR0_V  0x000000FFU
-#define LP_UART_WK_CHAR0_S  0
-
-/** LP_UART_SLEEP_CONF2_REG register
- *  UART sleep configure register 2
- */
-#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38)
-/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
- *  The uart is activated from light sleeping mode when the input rxd edge changes more
- *  times than this register value.
- */
-#define LP_UART_ACTIVE_THRESHOLD    0x000003FFU
-#define LP_UART_ACTIVE_THRESHOLD_M  (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S)
-#define LP_UART_ACTIVE_THRESHOLD_V  0x000003FFU
-#define LP_UART_ACTIVE_THRESHOLD_S  0
-/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1;
- *  In wake up mode 1 this field is used to set the received data number threshold to
- *  wake up chip.
- */
-#define LP_UART_RX_WAKE_UP_THRHD    0x0000001FU
-#define LP_UART_RX_WAKE_UP_THRHD_M  (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S)
-#define LP_UART_RX_WAKE_UP_THRHD_V  0x0000001FU
-#define LP_UART_RX_WAKE_UP_THRHD_S  13
-/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
- *  This register is used to select number of wake up char.
- */
-#define LP_UART_WK_CHAR_NUM    0x00000007U
-#define LP_UART_WK_CHAR_NUM_M  (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S)
-#define LP_UART_WK_CHAR_NUM_V  0x00000007U
-#define LP_UART_WK_CHAR_NUM_S  18
-/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
- *  This register is used to mask  wake up char.
- */
-#define LP_UART_WK_CHAR_MASK    0x0000001FU
-#define LP_UART_WK_CHAR_MASK_M  (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S)
-#define LP_UART_WK_CHAR_MASK_V  0x0000001FU
-#define LP_UART_WK_CHAR_MASK_S  21
-/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
- *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
- *  received data number larger than
- */
-#define LP_UART_WK_MODE_SEL    0x00000003U
-#define LP_UART_WK_MODE_SEL_M  (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S)
-#define LP_UART_WK_MODE_SEL_V  0x00000003U
-#define LP_UART_WK_MODE_SEL_S  26
-
-/** LP_UART_SWFC_CONF0_SYNC_REG register
- *  Software flow-control character configuration
- */
-#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c)
-/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
- *  This register stores the Xon flow control char.
- */
-#define LP_UART_XON_CHAR    0x000000FFU
-#define LP_UART_XON_CHAR_M  (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S)
-#define LP_UART_XON_CHAR_V  0x000000FFU
-#define LP_UART_XON_CHAR_S  0
-/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
- *  This register stores the Xoff flow control char.
- */
-#define LP_UART_XOFF_CHAR    0x000000FFU
-#define LP_UART_XOFF_CHAR_M  (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S)
-#define LP_UART_XOFF_CHAR_V  0x000000FFU
-#define LP_UART_XOFF_CHAR_S  8
-/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
- *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
- *  this status, UART Tx can not transmit XOFF even the received data number is larger
- *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
- *  UART Tx is disabled.
- */
-#define LP_UART_XON_XOFF_STILL_SEND    (BIT(16))
-#define LP_UART_XON_XOFF_STILL_SEND_M  (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S)
-#define LP_UART_XON_XOFF_STILL_SEND_V  0x00000001U
-#define LP_UART_XON_XOFF_STILL_SEND_S  16
-/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
- *  Set this bit to enable software flow control. It is used with register sw_xon or
- *  sw_xoff.
- */
-#define LP_UART_SW_FLOW_CON_EN    (BIT(17))
-#define LP_UART_SW_FLOW_CON_EN_M  (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S)
-#define LP_UART_SW_FLOW_CON_EN_V  0x00000001U
-#define LP_UART_SW_FLOW_CON_EN_S  17
-/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
- *  Set this bit to remove flow control char from the received data.
- */
-#define LP_UART_XONOFF_DEL    (BIT(18))
-#define LP_UART_XONOFF_DEL_M  (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S)
-#define LP_UART_XONOFF_DEL_V  0x00000001U
-#define LP_UART_XONOFF_DEL_S  18
-/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
- *  Set this bit to enable the transmitter to go on sending data.
- */
-#define LP_UART_FORCE_XON    (BIT(19))
-#define LP_UART_FORCE_XON_M  (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S)
-#define LP_UART_FORCE_XON_V  0x00000001U
-#define LP_UART_FORCE_XON_S  19
-/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
- *  Set this bit to stop the  transmitter from sending data.
- */
-#define LP_UART_FORCE_XOFF    (BIT(20))
-#define LP_UART_FORCE_XOFF_M  (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S)
-#define LP_UART_FORCE_XOFF_V  0x00000001U
-#define LP_UART_FORCE_XOFF_S  20
-/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
- *  Set this bit to send Xon char. It is cleared by hardware automatically.
- */
-#define LP_UART_SEND_XON    (BIT(21))
-#define LP_UART_SEND_XON_M  (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S)
-#define LP_UART_SEND_XON_V  0x00000001U
-#define LP_UART_SEND_XON_S  21
-/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
- *  Set this bit to send Xoff char. It is cleared by hardware automatically.
- */
-#define LP_UART_SEND_XOFF    (BIT(22))
-#define LP_UART_SEND_XOFF_M  (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S)
-#define LP_UART_SEND_XOFF_V  0x00000001U
-#define LP_UART_SEND_XOFF_S  22
-
-/** LP_UART_SWFC_CONF1_REG register
- *  Software flow-control character configuration
- */
-#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40)
-/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0;
- *  When the data amount in Rx-FIFO is less than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xon char.
- */
-#define LP_UART_XON_THRESHOLD    0x0000001FU
-#define LP_UART_XON_THRESHOLD_M  (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S)
-#define LP_UART_XON_THRESHOLD_V  0x0000001FU
-#define LP_UART_XON_THRESHOLD_S  3
-/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12;
- *  When the data amount in Rx-FIFO is more than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
- */
-#define LP_UART_XOFF_THRESHOLD    0x0000001FU
-#define LP_UART_XOFF_THRESHOLD_M  (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S)
-#define LP_UART_XOFF_THRESHOLD_V  0x0000001FU
-#define LP_UART_XOFF_THRESHOLD_S  11
-
-/** LP_UART_TXBRK_CONF_SYNC_REG register
- *  Tx Break character configuration
- */
-#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44)
-/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
- *  This register is used to configure the number of 0 to be sent after the process of
- *  sending data is done. It is active when txd_brk is set to 1.
- */
-#define LP_UART_TX_BRK_NUM    0x000000FFU
-#define LP_UART_TX_BRK_NUM_M  (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S)
-#define LP_UART_TX_BRK_NUM_V  0x000000FFU
-#define LP_UART_TX_BRK_NUM_S  0
-
-/** LP_UART_IDLE_CONF_SYNC_REG register
- *  Frame-end idle configuration
- */
-#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48)
-/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
- *  It will produce frame end signal when receiver takes more time to receive one byte
- *  data than this register value.
- */
-#define LP_UART_RX_IDLE_THRHD    0x000003FFU
-#define LP_UART_RX_IDLE_THRHD_M  (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S)
-#define LP_UART_RX_IDLE_THRHD_V  0x000003FFU
-#define LP_UART_RX_IDLE_THRHD_S  0
-/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
- *  This register is used to configure the duration time between transfers.
- */
-#define LP_UART_TX_IDLE_NUM    0x000003FFU
-#define LP_UART_TX_IDLE_NUM_M  (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S)
-#define LP_UART_TX_IDLE_NUM_V  0x000003FFU
-#define LP_UART_TX_IDLE_NUM_S  10
-
-/** LP_UART_RS485_CONF_SYNC_REG register
- *  RS485 mode configuration
- */
-#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c)
-/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define LP_UART_DL0_EN    (BIT(1))
-#define LP_UART_DL0_EN_M  (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S)
-#define LP_UART_DL0_EN_V  0x00000001U
-#define LP_UART_DL0_EN_S  1
-/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define LP_UART_DL1_EN    (BIT(2))
-#define LP_UART_DL1_EN_M  (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S)
-#define LP_UART_DL1_EN_V  0x00000001U
-#define LP_UART_DL1_EN_S  2
-
-/** LP_UART_AT_CMD_PRECNT_SYNC_REG register
- *  Pre-sequence timing configuration
- */
-#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50)
-/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the idle duration time before the first at_cmd
- *  is received by receiver.
- */
-#define LP_UART_PRE_IDLE_NUM    0x0000FFFFU
-#define LP_UART_PRE_IDLE_NUM_M  (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S)
-#define LP_UART_PRE_IDLE_NUM_V  0x0000FFFFU
-#define LP_UART_PRE_IDLE_NUM_S  0
-
-/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register
- *  Post-sequence timing configuration
- */
-#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54)
-/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the duration time between the last at_cmd and
- *  the next data.
- */
-#define LP_UART_POST_IDLE_NUM    0x0000FFFFU
-#define LP_UART_POST_IDLE_NUM_M  (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S)
-#define LP_UART_POST_IDLE_NUM_V  0x0000FFFFU
-#define LP_UART_POST_IDLE_NUM_S  0
-
-/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register
- *  Timeout configuration
- */
-#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58)
-/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
- *  This register is used to configure the duration time between the at_cmd chars.
- */
-#define LP_UART_RX_GAP_TOUT    0x0000FFFFU
-#define LP_UART_RX_GAP_TOUT_M  (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S)
-#define LP_UART_RX_GAP_TOUT_V  0x0000FFFFU
-#define LP_UART_RX_GAP_TOUT_S  0
-
-/** LP_UART_AT_CMD_CHAR_SYNC_REG register
- *  AT escape sequence detection configuration
- */
-#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c)
-/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
- *  This register is used to configure the content of at_cmd char.
- */
-#define LP_UART_AT_CMD_CHAR    0x000000FFU
-#define LP_UART_AT_CMD_CHAR_M  (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S)
-#define LP_UART_AT_CMD_CHAR_V  0x000000FFU
-#define LP_UART_AT_CMD_CHAR_S  0
-/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
- *  This register is used to configure the num of continuous at_cmd chars received by
- *  receiver.
- */
-#define LP_UART_CHAR_NUM    0x000000FFU
-#define LP_UART_CHAR_NUM_M  (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S)
-#define LP_UART_CHAR_NUM_V  0x000000FFU
-#define LP_UART_CHAR_NUM_S  8
-
-/** LP_UART_MEM_CONF_REG register
- *  UART memory power configuration
- */
-#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60)
-/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
- *  Set this bit to force power down UART memory.
- */
-#define LP_UART_MEM_FORCE_PD    (BIT(25))
-#define LP_UART_MEM_FORCE_PD_M  (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S)
-#define LP_UART_MEM_FORCE_PD_V  0x00000001U
-#define LP_UART_MEM_FORCE_PD_S  25
-/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
- *  Set this bit to force power up UART memory.
- */
-#define LP_UART_MEM_FORCE_PU    (BIT(26))
-#define LP_UART_MEM_FORCE_PU_M  (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S)
-#define LP_UART_MEM_FORCE_PU_V  0x00000001U
-#define LP_UART_MEM_FORCE_PU_S  26
-
-/** LP_UART_TOUT_CONF_SYNC_REG register
- *  UART threshold and allocation configuration
- */
-#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
-/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
- */
-#define LP_UART_RX_TOUT_EN    (BIT(0))
-#define LP_UART_RX_TOUT_EN_M  (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)
-#define LP_UART_RX_TOUT_EN_V  0x00000001U
-#define LP_UART_RX_TOUT_EN_S  0
-/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
- *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
- */
-#define LP_UART_RX_TOUT_FLOW_DIS    (BIT(1))
-#define LP_UART_RX_TOUT_FLOW_DIS_M  (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S)
-#define LP_UART_RX_TOUT_FLOW_DIS_V  0x00000001U
-#define LP_UART_RX_TOUT_FLOW_DIS_S  1
-/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
- *  This register is used to configure the threshold time that receiver takes to
- *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
- *  takes more time to receive one byte with rx_tout_en set to 1.
- */
-#define LP_UART_RX_TOUT_THRHD    0x000003FFU
-#define LP_UART_RX_TOUT_THRHD_M  (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S)
-#define LP_UART_RX_TOUT_THRHD_V  0x000003FFU
-#define LP_UART_RX_TOUT_THRHD_S  2
-
-/** LP_UART_MEM_TX_STATUS_REG register
- *  Tx-SRAM write and read offset address.
- */
-#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68)
-/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0;
- *  This register stores the offset write address in Tx-SRAM.
- */
-#define LP_UART_TX_SRAM_WADDR    0x0000001FU
-#define LP_UART_TX_SRAM_WADDR_M  (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S)
-#define LP_UART_TX_SRAM_WADDR_V  0x0000001FU
-#define LP_UART_TX_SRAM_WADDR_S  3
-/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0;
- *  This register stores the offset read address in Tx-SRAM.
- */
-#define LP_UART_TX_SRAM_RADDR    0x0000001FU
-#define LP_UART_TX_SRAM_RADDR_M  (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S)
-#define LP_UART_TX_SRAM_RADDR_V  0x0000001FU
-#define LP_UART_TX_SRAM_RADDR_S  12
-
-/** LP_UART_MEM_RX_STATUS_REG register
- *  Rx-SRAM write and read offset address.
- */
-#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c)
-/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16;
- *  This register stores the offset read address in RX-SRAM.
- */
-#define LP_UART_RX_SRAM_RADDR    0x0000001FU
-#define LP_UART_RX_SRAM_RADDR_M  (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S)
-#define LP_UART_RX_SRAM_RADDR_V  0x0000001FU
-#define LP_UART_RX_SRAM_RADDR_S  3
-/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16;
- *  This register stores the offset write address in Rx-SRAM.
- */
-#define LP_UART_RX_SRAM_WADDR    0x0000001FU
-#define LP_UART_RX_SRAM_WADDR_M  (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S)
-#define LP_UART_RX_SRAM_WADDR_V  0x0000001FU
-#define LP_UART_RX_SRAM_WADDR_S  12
-
-/** LP_UART_FSM_STATUS_REG register
- *  UART transmit and receive status.
- */
-#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70)
-/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
- *  This is the status register of receiver.
- */
-#define LP_UART_ST_URX_OUT    0x0000000FU
-#define LP_UART_ST_URX_OUT_M  (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S)
-#define LP_UART_ST_URX_OUT_V  0x0000000FU
-#define LP_UART_ST_URX_OUT_S  0
-/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
- *  This is the status register of transmitter.
- */
-#define LP_UART_ST_UTX_OUT    0x0000000FU
-#define LP_UART_ST_UTX_OUT_M  (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S)
-#define LP_UART_ST_UTX_OUT_V  0x0000000FU
-#define LP_UART_ST_UTX_OUT_S  4
-
-/** LP_UART_CLK_CONF_REG register
- *  UART core clock configuration
- */
-#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
-/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor.
- */
-#define LP_UART_SCLK_DIV_B    0x0000003FU
-#define LP_UART_SCLK_DIV_B_M  (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S)
-#define LP_UART_SCLK_DIV_B_V  0x0000003FU
-#define LP_UART_SCLK_DIV_B_S  0
-/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor.
- */
-#define LP_UART_SCLK_DIV_A    0x0000003FU
-#define LP_UART_SCLK_DIV_A_M  (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S)
-#define LP_UART_SCLK_DIV_A_V  0x0000003FU
-#define LP_UART_SCLK_DIV_A_S  6
-/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
- *  The integral part of the frequency divider factor.
- */
-#define LP_UART_SCLK_DIV_NUM    0x000000FFU
-#define LP_UART_SCLK_DIV_NUM_M  (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S)
-#define LP_UART_SCLK_DIV_NUM_V  0x000000FFU
-#define LP_UART_SCLK_DIV_NUM_S  12
-/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
- */
-#define LP_UART_SCLK_SEL    0x00000003U
-#define LP_UART_SCLK_SEL_M  (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S)
-#define LP_UART_SCLK_SEL_V  0x00000003U
-#define LP_UART_SCLK_SEL_S  20
-/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set this bit to enable UART Tx/Rx clock.
- */
-#define LP_UART_SCLK_EN    (BIT(22))
-#define LP_UART_SCLK_EN_M  (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S)
-#define LP_UART_SCLK_EN_V  0x00000001U
-#define LP_UART_SCLK_EN_S  22
-/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
- */
-#define LP_UART_RST_CORE    (BIT(23))
-#define LP_UART_RST_CORE_M  (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S)
-#define LP_UART_RST_CORE_V  0x00000001U
-#define LP_UART_RST_CORE_S  23
-/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
- *  Set this bit to enable UART Tx clock.
- */
-#define LP_UART_TX_SCLK_EN    (BIT(24))
-#define LP_UART_TX_SCLK_EN_M  (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S)
-#define LP_UART_TX_SCLK_EN_V  0x00000001U
-#define LP_UART_TX_SCLK_EN_S  24
-/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
- *  Set this bit to enable UART Rx clock.
- */
-#define LP_UART_RX_SCLK_EN    (BIT(25))
-#define LP_UART_RX_SCLK_EN_M  (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S)
-#define LP_UART_RX_SCLK_EN_V  0x00000001U
-#define LP_UART_RX_SCLK_EN_S  25
-/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Tx.
- */
-#define LP_UART_TX_RST_CORE    (BIT(26))
-#define LP_UART_TX_RST_CORE_M  (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S)
-#define LP_UART_TX_RST_CORE_V  0x00000001U
-#define LP_UART_TX_RST_CORE_S  26
-/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Rx.
- */
-#define LP_UART_RX_RST_CORE    (BIT(27))
-#define LP_UART_RX_RST_CORE_M  (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S)
-#define LP_UART_RX_RST_CORE_V  0x00000001U
-#define LP_UART_RX_RST_CORE_S  27
-
-/** LP_UART_DATE_REG register
- *  UART Version register
- */
-#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c)
-/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 35656288;
- *  This is the version register.
- */
-#define LP_UART_DATE    0xFFFFFFFFU
-#define LP_UART_DATE_M  (LP_UART_DATE_V << LP_UART_DATE_S)
-#define LP_UART_DATE_V  0xFFFFFFFFU
-#define LP_UART_DATE_S  0
-
-/** LP_UART_AFIFO_STATUS_REG register
- *  UART AFIFO Status
- */
-#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90)
-/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
- *  Full signal of APB TX AFIFO.
- */
-#define LP_UART_TX_AFIFO_FULL    (BIT(0))
-#define LP_UART_TX_AFIFO_FULL_M  (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S)
-#define LP_UART_TX_AFIFO_FULL_V  0x00000001U
-#define LP_UART_TX_AFIFO_FULL_S  0
-/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
- *  Empty signal of APB TX AFIFO.
- */
-#define LP_UART_TX_AFIFO_EMPTY    (BIT(1))
-#define LP_UART_TX_AFIFO_EMPTY_M  (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S)
-#define LP_UART_TX_AFIFO_EMPTY_V  0x00000001U
-#define LP_UART_TX_AFIFO_EMPTY_S  1
-/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
- *  Full signal of APB RX AFIFO.
- */
-#define LP_UART_RX_AFIFO_FULL    (BIT(2))
-#define LP_UART_RX_AFIFO_FULL_M  (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S)
-#define LP_UART_RX_AFIFO_FULL_V  0x00000001U
-#define LP_UART_RX_AFIFO_FULL_S  2
-/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
- *  Empty signal of APB RX AFIFO.
- */
-#define LP_UART_RX_AFIFO_EMPTY    (BIT(3))
-#define LP_UART_RX_AFIFO_EMPTY_M  (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S)
-#define LP_UART_RX_AFIFO_EMPTY_V  0x00000001U
-#define LP_UART_RX_AFIFO_EMPTY_S  3
-
-/** LP_UART_REG_UPDATE_REG register
- *  UART Registers Configuration Update register
- */
-#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98)
-/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
- *  Software write 1 would synchronize registers into UART Core clock domain and would
- *  be cleared by hardware after synchronization is done.
- */
-#define LP_UART_REG_UPDATE    (BIT(0))
-#define LP_UART_REG_UPDATE_M  (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S)
-#define LP_UART_REG_UPDATE_V  0x00000001U
-#define LP_UART_REG_UPDATE_S  0
-
-/** LP_UART_ID_REG register
- *  UART ID register
- */
-#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c)
-/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280;
- *  This register is used to configure the uart_id.
- */
-#define LP_UART_ID    0xFFFFFFFFU
-#define LP_UART_ID_M  (LP_UART_ID_V << LP_UART_ID_S)
-#define LP_UART_ID_V  0xFFFFFFFFU
-#define LP_UART_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/lp_uart_struct.h b/components/soc/esp32c6/include/soc/lp_uart_struct.h
deleted file mode 100644
index 122c7d920a9..00000000000
--- a/components/soc/esp32c6/include/soc/lp_uart_struct.h
+++ /dev/null
@@ -1,1127 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
-         *  UART $n accesses FIFO via this register.
-         */
-        uint32_t rxfifo_rd_byte:32;
-    };
-    uint32_t val;
-} lp_uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} lp_uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  This register is used to configure the threshold time that receiver takes to
-         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
-         *  takes more time to receive one byte with rx_tout_en set to 1.
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  what rxfifo_full_thrhd specifies.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1;
-         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-         *  less than what txfifo_empty_thrhd specifies .
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error in
-         *  the data.
-         */
-        uint32_t parity_err:1;
-        /** frm_err : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  .
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  the FIFO can store.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  DSRn signal.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  CTSn signal.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
-         *  bit.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver takes more time than
-         *  rx_tout_thrhd to receive a byte.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det : R/WTC/SS; bitpos: [11]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
-         *  middle of a start bit.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter completes  sending
-         *  NULL characters after all data in Tx-FIFO are sent.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
-         *  duration after sending the  last data.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done : R/WTC/SS; bitpos: [14]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has send out all data
-         *  in FIFO.
-         */
-        uint32_t tx_done:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the configured
-         *  at_cmd char.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup : R/WTC/SS; bitpos: [19]; default: 0;
-         *  This interrupt raw bit turns to high level when input rxd edge changes more times
-         *  than what reg_active_threshold specifies in light sleeping mode.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full : RO; bitpos: [0]; default: 0;
-         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty : RO; bitpos: [1]; default: 0;
-         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
-         *  to 1.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err : RO; bitpos: [2]; default: 0;
-         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-         */
-        uint32_t parity_err:1;
-        /** frm_err : RO; bitpos: [3]; default: 0;
-         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf : RO; bitpos: [4]; default: 0;
-         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg : RO; bitpos: [5]; default: 0;
-         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg : RO; bitpos: [6]; default: 0;
-         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det : RO; bitpos: [7]; default: 0;
-         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout : RO; bitpos: [8]; default: 0;
-         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon : RO; bitpos: [9]; default: 0;
-         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff : RO; bitpos: [10]; default: 0;
-         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det : RO; bitpos: [11]; default: 0;
-         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done : RO; bitpos: [12]; default: 0;
-         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
-         *  is set to 1.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done : RO; bitpos: [14]; default: 0;
-         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-         */
-        uint32_t tx_done:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det : RO; bitpos: [18]; default: 0;
-         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
-         *  to 1.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup : RO; bitpos: [19]; default: 0;
-         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full : R/W; bitpos: [0]; default: 0;
-         *  This is the enable bit for rxfifo_full_int_st register.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty : R/W; bitpos: [1]; default: 0;
-         *  This is the enable bit for txfifo_empty_int_st register.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err : R/W; bitpos: [2]; default: 0;
-         *  This is the enable bit for parity_err_int_st register.
-         */
-        uint32_t parity_err:1;
-        /** frm_err : R/W; bitpos: [3]; default: 0;
-         *  This is the enable bit for frm_err_int_st register.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf : R/W; bitpos: [4]; default: 0;
-         *  This is the enable bit for rxfifo_ovf_int_st register.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg : R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for dsr_chg_int_st register.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg : R/W; bitpos: [6]; default: 0;
-         *  This is the enable bit for cts_chg_int_st register.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det : R/W; bitpos: [7]; default: 0;
-         *  This is the enable bit for brk_det_int_st register.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout : R/W; bitpos: [8]; default: 0;
-         *  This is the enable bit for rxfifo_tout_int_st register.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon : R/W; bitpos: [9]; default: 0;
-         *  This is the enable bit for sw_xon_int_st register.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff : R/W; bitpos: [10]; default: 0;
-         *  This is the enable bit for sw_xoff_int_st register.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det : R/W; bitpos: [11]; default: 0;
-         *  This is the enable bit for glitch_det_int_st register.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done : R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for tx_brk_done_int_st register.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done : R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit for tx_brk_idle_done_int_st register.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done : R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for tx_done_int_st register.
-         */
-        uint32_t tx_done:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det : R/W; bitpos: [18]; default: 0;
-         *  This is the enable bit for at_cmd_char_det_int_st register.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for uart_wakeup_int_st register.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear txfifo_empty_int_raw interrupt.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear parity_err_int_raw interrupt.
-         */
-        uint32_t parity_err:1;
-        /** frm_err : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear frm_err_int_raw interrupt.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the dsr_chg_int_raw interrupt.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the cts_chg_int_raw interrupt.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the brk_det_int_raw interrupt.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the sw_xon_int_raw interrupt.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the sw_xoff_int_raw interrupt.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the glitch_det_int_raw interrupt.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the tx_done_int_raw interrupt.
-         */
-        uint32_t tx_done:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t clkdiv_int:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  The decimal part of the frequency divider factor.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lp_uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  Rx Filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  when input pulse width is lower than this value the pulse is ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable Rx signal filter.
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  Configuration register 0
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  This register is used to configure the parity check mode.
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable uart parity check.
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  This register is used to set the length of data.
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  This register is used to set the length of  stop bit.
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
-         *  is done.
-         */
-        uint32_t txd_brk:1;
-        uint32_t reserved_7:5;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable uart loopback test mode.
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to enable flow control function for transmitter.
-         */
-        uint32_t tx_flow_en:1;
-        uint32_t reserved_14:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Set this bit to inverse the level value of uart rxd signal.
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart txd signal.
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Disable UART Rx data overflow detect.
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-         *  stores the data even if the  received data is wrong.
-         */
-        uint32_t err_wr_mask:1;
-        uint32_t reserved_19:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 1;
-         *  UART memory clock gate enable signal.
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  This register is used to configure the software rts signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Set this bit to reset the uart receive-FIFO.
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Set this bit to reset the uart transmit-FIFO.
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lp_uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12;
-         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
-         *  this register value.
-         */
-        uint32_t rxfifo_full_thrhd:5;
-        uint32_t reserved_8:3;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12;
-         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
-         *  than this register value.
-         */
-        uint32_t txfifo_empty_thrhd:5;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart cts signal.
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to inverse the level value of uart dsr signal.
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to inverse the level value of uart rts signal.
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to inverse the level value of uart dtr signal.
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  This register is used to configure the software dtr signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} lp_uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow-control configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0;
-         *  This register is used to configure the maximum amount of data that can be received
-         *  when hardware flow control works.
-         */
-        uint32_t rx_flow_thrhd:5;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  This is the flow enable bit for UART receiver.
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configure register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified wake up char1 to wake up
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  This register restores the specified wake up char2 to wake up
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  This register restores the specified wake up char3 to wake up
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  This register restores the specified wake up char4 to wake up
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configure register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified char0 to wake up
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configure register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  The uart is activated from light sleeping mode when the input rxd edge changes more
-         *  times than this register value.
-         */
-        uint32_t active_threshold:10;
-        uint32_t reserved_10:3;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1;
-         *  In wake up mode 1 this field is used to set the received data number threshold to
-         *  wake up chip.
-         */
-        uint32_t rx_wake_up_thrhd:5;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  This register is used to select number of wake up char.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  This register is used to mask  wake up char.
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
-         *  received data number larger than
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  This register stores the Xon flow control char.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  This register stores the Xoff flow control char.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
-         *  this status, UART Tx can not transmit XOFF even the received data number is larger
-         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
-         *  UART Tx is disabled.
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to enable software flow control. It is used with register sw_xon or
-         *  sw_xoff.
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to remove flow control char from the received data.
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to enable the transmitter to go on sending data.
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Set this bit to stop the  transmitter from sending data.
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Set this bit to send Xon char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** xon_threshold : R/W; bitpos: [7:3]; default: 0;
-         *  When the data amount in Rx-FIFO is less than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
-         */
-        uint32_t xon_threshold:5;
-        uint32_t reserved_8:3;
-        /** xoff_threshold : R/W; bitpos: [15:11]; default: 12;
-         *  When the data amount in Rx-FIFO is more than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
-         */
-        uint32_t xoff_threshold:5;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  Tx Break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  This register is used to configure the number of 0 to be sent after the process of
-         *  sending data is done. It is active when txd_brk is set to 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame-end idle configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  It will produce frame end signal when receiver takes more time to receive one byte
-         *  data than this register value.
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  This register is used to configure the duration time between transfers.
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl1_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} lp_uart_rs485_conf_sync_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor.
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor.
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t sclk_div_num:8;
-        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
-         */
-        uint32_t sclk_sel:2;
-        /** sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set this bit to enable UART Tx/Rx clock.
-         */
-        uint32_t sclk_en:1;
-        /** rst_core : R/W; bitpos: [23]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
-         */
-        uint32_t rst_core:1;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Set this bit to enable UART Tx clock.
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Set this bit to enable UART Rx clock.
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Rx.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0;
-         *  Stores the byte number of valid data in Rx-FIFO.
-         */
-        uint32_t rxfifo_cnt:5;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  The register represent the level value of the internal uart dsr signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  This register represent the level value of the internal uart cts signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  This register represent the  level value of the internal uart rxd signal.
-         */
-        uint32_t rxd:1;
-        uint32_t reserved_16:3;
-        /** txfifo_cnt : RO; bitpos: [23:19]; default: 0;
-         *  Stores the byte number of data in Tx-FIFO.
-         */
-        uint32_t txfifo_cnt:5;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  This bit represents the level of the internal uart dtr signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  This bit represents the level of the internal uart rts signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  This bit represents the  level of the internal uart txd signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} lp_uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  Tx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0;
-         *  This register stores the offset write address in Tx-SRAM.
-         */
-        uint32_t tx_sram_waddr:5;
-        uint32_t reserved_8:4;
-        /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0;
-         *  This register stores the offset read address in Tx-SRAM.
-         */
-        uint32_t tx_sram_raddr:5;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16;
-         *  This register stores the offset read address in RX-SRAM.
-         */
-        uint32_t rx_sram_raddr:5;
-        uint32_t reserved_8:4;
-        /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16;
-         *  This register stores the offset write address in Rx-SRAM.
-         */
-        uint32_t rx_sram_waddr:5;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status.
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  This is the status register of receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  This is the status register of transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART AFIFO Status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Full signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Empty signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Full signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Empty signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the idle duration time before the first at_cmd
-         *  is received by receiver.
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the duration time between the last at_cmd and
-         *  the next data.
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  This register is used to configure the duration time between the at_cmd chars.
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** data : R/W; bitpos: [7:0]; default: 43;
-         *  This register is used to configure the content of at_cmd char.
-         */
-        uint32_t data:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  This register is used to configure the num of continuous at_cmd chars received by
-         *  receiver.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35656288;
-         *  This is the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} lp_uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART Registers Configuration Update register
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Software write 1 would synchronize registers into UART Core clock domain and would
-         *  be cleared by hardware after synchronization is done.
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  This register is used to configure the uart_id.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} lp_uart_id_reg_t;
-
-
-typedef struct lp_uart_dev_t {
-    volatile lp_uart_fifo_reg_t fifo;
-    volatile lp_uart_int_raw_reg_t int_raw;
-    volatile lp_uart_int_st_reg_t int_st;
-    volatile lp_uart_int_ena_reg_t int_ena;
-    volatile lp_uart_int_clr_reg_t int_clr;
-    volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile lp_uart_rx_filt_reg_t rx_filt;
-    volatile lp_uart_status_reg_t status;
-    volatile lp_uart_conf0_sync_reg_t conf0_sync;
-    volatile lp_uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile lp_uart_sleep_conf0_reg_t sleep_conf0;
-    volatile lp_uart_sleep_conf1_reg_t sleep_conf1;
-    volatile lp_uart_sleep_conf2_reg_t sleep_conf2;
-    volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile lp_uart_swfc_conf1_reg_t swfc_conf1;
-    volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile lp_uart_mem_conf_reg_t mem_conf;
-    volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile lp_uart_mem_tx_status_reg_t mem_tx_status;
-    volatile lp_uart_mem_rx_status_reg_t mem_rx_status;
-    volatile lp_uart_fsm_status_reg_t fsm_status;
-    uint32_t reserved_074[5];
-    volatile lp_uart_clk_conf_reg_t clk_conf;
-    volatile lp_uart_date_reg_t date;
-    volatile lp_uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile lp_uart_reg_update_reg_t reg_update;
-    volatile lp_uart_id_reg_t id;
-} lp_uart_dev_t;
-
-// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h
-// extern lp_uart_dev_t LP_UART;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/mcpwm_reg.h b/components/soc/esp32c6/include/soc/mcpwm_reg.h
deleted file mode 100644
index 4eacabbc9c5..00000000000
--- a/components/soc/esp32c6/include/soc/mcpwm_reg.h
+++ /dev/null
@@ -1,4137 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MCPWM_CLK_CFG_REG register
- *  PWM clock prescaler register.
- */
-#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0)
-/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
- */
-#define MCPWM_CLK_PRESCALE    0x000000FFU
-#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
-#define MCPWM_CLK_PRESCALE_V  0x000000FFU
-#define MCPWM_CLK_PRESCALE_S  0
-
-/** MCPWM_TIMER0_CFG0_REG register
- *  PWM timer0 period and update method configuration register.
- */
-#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer0
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER0_CFG1_REG register
- *  PWM timer0 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8)
-/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1:
- *  if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0
- *  starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER0_START    0x00000007U
-#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
-#define MCPWM_TIMER0_START_V  0x00000007U
-#define MCPWM_TIMER0_START_S  0
-/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER0_MOD    0x00000003U
-#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
-#define MCPWM_TIMER0_MOD_V  0x00000003U
-#define MCPWM_TIMER0_MOD_S  3
-
-/** MCPWM_TIMER0_SYNC_REG register
- *  PWM timer0 sync function configuration register.
- */
-#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xc)
-/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
-#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER0_SYNCI_EN_S  0
-/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
-#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER0_SYNC_SW_S  1
-/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer0_sync_sw bit
- */
-#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
-#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_S  2
-/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER0_PHASE    0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
-#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_S  4
-/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer0's direction when timer0 mode is up-down mode:
- *  0-increase,1-decrease
- */
-#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
-#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER0_STATUS_REG register
- *  PWM timer0 status register.
- */
-#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10)
-/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer0 counter value
- */
-#define MCPWM_TIMER0_VALUE    0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
-#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_S  0
-/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer0 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER0_DIRECTION    (BIT(16))
-#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
-#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_DIRECTION_S  16
-
-/** MCPWM_TIMER1_CFG0_REG register
- *  PWM timer1 period and update method configuration register.
- */
-#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14)
-/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1)
- */
-#define MCPWM_TIMER1_PRESCALE    0x000000FFU
-#define MCPWM_TIMER1_PRESCALE_M  (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S)
-#define MCPWM_TIMER1_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER1_PRESCALE_S  0
-/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer1
- */
-#define MCPWM_TIMER1_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER1_PERIOD_M  (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S)
-#define MCPWM_TIMER1_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER1_PERIOD_S  8
-/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER1_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER1_CFG1_REG register
- *  PWM timer1 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18)
-/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1:
- *  if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1
- *  starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER1_START    0x00000007U
-#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
-#define MCPWM_TIMER1_START_V  0x00000007U
-#define MCPWM_TIMER1_START_S  0
-/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER1_MOD    0x00000003U
-#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
-#define MCPWM_TIMER1_MOD_V  0x00000003U
-#define MCPWM_TIMER1_MOD_S  3
-
-/** MCPWM_TIMER1_SYNC_REG register
- *  PWM timer1 sync function configuration register.
- */
-#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1c)
-/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
-#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER1_SYNCI_EN_S  0
-/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
-#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER1_SYNC_SW_S  1
-/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer1_sync_sw bit
- */
-#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
-#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_S  2
-/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER1_PHASE    0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
-#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_S  4
-/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer1's direction when timer1 mode is up-down mode:
- *  0-increase,1-decrease
- */
-#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
-#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER1_STATUS_REG register
- *  PWM timer1 status register.
- */
-#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20)
-/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer1 counter value
- */
-#define MCPWM_TIMER1_VALUE    0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
-#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_S  0
-/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer1 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER1_DIRECTION    (BIT(16))
-#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
-#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_DIRECTION_S  16
-
-/** MCPWM_TIMER2_CFG0_REG register
- *  PWM timer2 period and update method configuration register.
- */
-#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24)
-/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1)
- */
-#define MCPWM_TIMER2_PRESCALE    0x000000FFU
-#define MCPWM_TIMER2_PRESCALE_M  (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S)
-#define MCPWM_TIMER2_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER2_PRESCALE_S  0
-/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer2
- */
-#define MCPWM_TIMER2_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER2_PERIOD_M  (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S)
-#define MCPWM_TIMER2_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER2_PERIOD_S  8
-/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER2_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER2_CFG1_REG register
- *  PWM timer2 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28)
-/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1:
- *  if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2
- *  starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER2_START    0x00000007U
-#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
-#define MCPWM_TIMER2_START_V  0x00000007U
-#define MCPWM_TIMER2_START_S  0
-/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER2_MOD    0x00000003U
-#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
-#define MCPWM_TIMER2_MOD_V  0x00000003U
-#define MCPWM_TIMER2_MOD_S  3
-
-/** MCPWM_TIMER2_SYNC_REG register
- *  PWM timer2 sync function configuration register.
- */
-#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2c)
-/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
-#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER2_SYNCI_EN_S  0
-/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
-#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER2_SYNC_SW_S  1
-/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer0_sync_sw bit
- */
-#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
-#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_S  2
-/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER2_PHASE    0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
-#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_S  4
-/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer2's direction when timer2 mode is up-down mode:
- *  0-increase,1-decrease
- */
-#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
-#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER2_STATUS_REG register
- *  PWM timer2 status register.
- */
-#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30)
-/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer2 counter value
- */
-#define MCPWM_TIMER2_VALUE    0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
-#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_S  0
-/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer2 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER2_DIRECTION    (BIT(16))
-#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
-#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_DIRECTION_S  16
-
-/** MCPWM_TIMER_SYNCI_CFG_REG register
- *  Synchronization input selection for three PWM timers.
- */
-#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34)
-/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
- *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER0_SYNCISEL    0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
-#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_S  0
-/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
- *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER1_SYNCISEL    0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
-#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_S  3
-/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
- *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER2_SYNCISEL    0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
-#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_S  6
-/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
- *  invert SYNC0 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
-/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
- *  invert SYNC1 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
-/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
- *  invert SYNC2 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
-
-/** MCPWM_OPERATOR_TIMERSEL_REG register
- *  Select specific timer for PWM operators.
- */
-#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38)
-/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
- *  Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
-#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_S  0
-/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
- *  Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
-#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_S  2
-/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
- *  Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
-#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_S  4
-
-/** MCPWM_GEN0_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3c)
-/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 0 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
-#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_S  0
-/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 0 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
-#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_S  4
-/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
-#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_A_SHDW_FULL_S  8
-/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
-#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN0_TSTMP_A_REG register
- *  Shadow register for register A.
- */
-#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x40)
-/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 0 time stamp A's shadow register
- */
-#define MCPWM_CMPR0_A    0x0000FFFFU
-#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
-#define MCPWM_CMPR0_A_V  0x0000FFFFU
-#define MCPWM_CMPR0_A_S  0
-
-/** MCPWM_GEN0_TSTMP_B_REG register
- *  Shadow register for register B.
- */
-#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x44)
-/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 0 time stamp B's shadow register
- */
-#define MCPWM_CMPR0_B    0x0000FFFFU
-#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
-#define MCPWM_CMPR0_B_V  0x0000FFFFU
-#define MCPWM_CMPR0_B_S  0
-
-/** MCPWM_GEN0_CFG0_REG register
- *  Fault event T0 and T1 handling
- */
-#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48)
-/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 0's active register of configuration. When all bits
- *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
- *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
- */
-#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
-#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_S  0
-/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 0 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN0_T0_SEL    0x00000007U
-#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
-#define MCPWM_GEN0_T0_SEL_V  0x00000007U
-#define MCPWM_GEN0_T0_SEL_S  4
-/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 0 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN0_T1_SEL    0x00000007U
-#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
-#define MCPWM_GEN0_T1_SEL_V  0x00000007U
-#define MCPWM_GEN0_T1_SEL_S  7
-
-/** MCPWM_GEN0_FORCE_REG register
- *  Permissives to force PWM0A and PWM0B outputs by software
- */
-#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4c)
-/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator0. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM0A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
-#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_A_NCIFORCE_S  10
-/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM0B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
-#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_B_NCIFORCE_S  13
-/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN0_A_REG register
- *  Actions triggered by events on PWM0A
- */
-#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50)
-/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM0A triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN0_A_UTEZ    0x00000003U
-#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
-#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_UTEZ_S  0
-/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM0A triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN0_A_UTEP    0x00000003U
-#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
-#define MCPWM_GEN0_A_UTEP_V  0x00000003U
-#define MCPWM_GEN0_A_UTEP_S  2
-/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM0A triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN0_A_UTEA    0x00000003U
-#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
-#define MCPWM_GEN0_A_UTEA_V  0x00000003U
-#define MCPWM_GEN0_A_UTEA_S  4
-/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM0A triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN0_A_UTEB    0x00000003U
-#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
-#define MCPWM_GEN0_A_UTEB_V  0x00000003U
-#define MCPWM_GEN0_A_UTEB_S  6
-/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM0A triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN0_A_UT0    0x00000003U
-#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
-#define MCPWM_GEN0_A_UT0_V  0x00000003U
-#define MCPWM_GEN0_A_UT0_S  8
-/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM0A triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN0_A_UT1    0x00000003U
-#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
-#define MCPWM_GEN0_A_UT1_V  0x00000003U
-#define MCPWM_GEN0_A_UT1_S  10
-/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM0A triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN0_A_DTEZ    0x00000003U
-#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
-#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_DTEZ_S  12
-/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM0A triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN0_A_DTEP    0x00000003U
-#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
-#define MCPWM_GEN0_A_DTEP_V  0x00000003U
-#define MCPWM_GEN0_A_DTEP_S  14
-/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM0A triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN0_A_DTEA    0x00000003U
-#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
-#define MCPWM_GEN0_A_DTEA_V  0x00000003U
-#define MCPWM_GEN0_A_DTEA_S  16
-/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM0A triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN0_A_DTEB    0x00000003U
-#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
-#define MCPWM_GEN0_A_DTEB_V  0x00000003U
-#define MCPWM_GEN0_A_DTEB_S  18
-/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM0A triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN0_A_DT0    0x00000003U
-#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
-#define MCPWM_GEN0_A_DT0_V  0x00000003U
-#define MCPWM_GEN0_A_DT0_S  20
-/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_DT1    0x00000003U
-#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
-#define MCPWM_GEN0_A_DT1_V  0x00000003U
-#define MCPWM_GEN0_A_DT1_S  22
-
-/** MCPWM_GEN0_B_REG register
- *  Actions triggered by events on PWM0B
- */
-#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54)
-/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM0B triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN0_B_UTEZ    0x00000003U
-#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
-#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_UTEZ_S  0
-/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM0B triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN0_B_UTEP    0x00000003U
-#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
-#define MCPWM_GEN0_B_UTEP_V  0x00000003U
-#define MCPWM_GEN0_B_UTEP_S  2
-/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM0B triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN0_B_UTEA    0x00000003U
-#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
-#define MCPWM_GEN0_B_UTEA_V  0x00000003U
-#define MCPWM_GEN0_B_UTEA_S  4
-/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM0B triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN0_B_UTEB    0x00000003U
-#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
-#define MCPWM_GEN0_B_UTEB_V  0x00000003U
-#define MCPWM_GEN0_B_UTEB_S  6
-/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM0B triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN0_B_UT0    0x00000003U
-#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
-#define MCPWM_GEN0_B_UT0_V  0x00000003U
-#define MCPWM_GEN0_B_UT0_S  8
-/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM0B triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN0_B_UT1    0x00000003U
-#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
-#define MCPWM_GEN0_B_UT1_V  0x00000003U
-#define MCPWM_GEN0_B_UT1_S  10
-/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM0B triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN0_B_DTEZ    0x00000003U
-#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
-#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_DTEZ_S  12
-/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM0B triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN0_B_DTEP    0x00000003U
-#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
-#define MCPWM_GEN0_B_DTEP_V  0x00000003U
-#define MCPWM_GEN0_B_DTEP_S  14
-/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM0B triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN0_B_DTEA    0x00000003U
-#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
-#define MCPWM_GEN0_B_DTEA_V  0x00000003U
-#define MCPWM_GEN0_B_DTEA_S  16
-/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM0B triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN0_B_DTEB    0x00000003U
-#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
-#define MCPWM_GEN0_B_DTEB_V  0x00000003U
-#define MCPWM_GEN0_B_DTEB_S  18
-/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM0B triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN0_B_DT0    0x00000003U
-#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
-#define MCPWM_GEN0_B_DT0_V  0x00000003U
-#define MCPWM_GEN0_B_DT0_S  20
-/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_DT1    0x00000003U
-#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
-#define MCPWM_GEN0_B_DT1_V  0x00000003U
-#define MCPWM_GEN0_B_DT1_S  22
-
-/** MCPWM_DT0_CFG_REG register
- *  dead time type selection and configuration
- */
-#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58)
-/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
-#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB0_FED_UPMETHOD_S  0
-/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
-#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB0_RED_UPMETHOD_S  4
-/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB0_DEB_MODE    (BIT(8))
-#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
-#define MCPWM_DB0_DEB_MODE_V  0x00000001U
-#define MCPWM_DB0_DEB_MODE_S  8
-/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
-#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB0_A_OUTSWAP_S  9
-/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
-#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB0_B_OUTSWAP_S  10
-/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DB0_RED_INSEL    (BIT(11))
-#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
-#define MCPWM_DB0_RED_INSEL_V  0x00000001U
-#define MCPWM_DB0_RED_INSEL_S  11
-/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DB0_FED_INSEL    (BIT(12))
-#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
-#define MCPWM_DB0_FED_INSEL_V  0x00000001U
-#define MCPWM_DB0_FED_INSEL_S  12
-/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
-#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB0_RED_OUTINVERT_S  13
-/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
-#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB0_FED_OUTINVERT_S  14
-/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
-#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB0_A_OUTBYPASS_S  15
-/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
-#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB0_B_OUTBYPASS_S  16
-/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DB0_CLK_SEL    (BIT(17))
-#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
-#define MCPWM_DB0_CLK_SEL_V  0x00000001U
-#define MCPWM_DB0_CLK_SEL_S  17
-
-/** MCPWM_DT0_FED_CFG_REG register
- *  Shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c)
-/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DB0_FED    0x0000FFFFU
-#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
-#define MCPWM_DB0_FED_V  0x0000FFFFU
-#define MCPWM_DB0_FED_S  0
-
-/** MCPWM_DT0_RED_CFG_REG register
- *  Shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60)
-/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DB0_RED    0x0000FFFFU
-#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
-#define MCPWM_DB0_RED_V  0x0000FFFFU
-#define MCPWM_DB0_RED_S  0
-
-/** MCPWM_CARRIER0_CFG_REG register
- *  Carrier enable and configuratoin
- */
-#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64)
-/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
- */
-#define MCPWM_CHOPPER0_EN    (BIT(0))
-#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
-#define MCPWM_CHOPPER0_EN_V  0x00000001U
-#define MCPWM_CHOPPER0_EN_S  0
-/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
-#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER0_PRESCALE_S  1
-/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CHOPPER0_DUTY    0x00000007U
-#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
-#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER0_DUTY_S  5
-/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
-#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER0_OSHTWTH_S  8
-/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM0A and PWM0B for this submodule
- */
-#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
-#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER0_OUT_INVERT_S  12
-/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM0A and PWM0B for this submodule
- */
-#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
-#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER0_IN_INVERT_S  13
-
-/** MCPWM_FH0_CFG0_REG register
- *  Actions on PWM0A and PWM0B trip events
- */
-#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68)
-/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_SW_CBC    (BIT(0))
-#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
-#define MCPWM_TZ0_SW_CBC_V  0x00000001U
-#define MCPWM_TZ0_SW_CBC_S  0
-/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F2_CBC    (BIT(1))
-#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
-#define MCPWM_TZ0_F2_CBC_V  0x00000001U
-#define MCPWM_TZ0_F2_CBC_S  1
-/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F1_CBC    (BIT(2))
-#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
-#define MCPWM_TZ0_F1_CBC_V  0x00000001U
-#define MCPWM_TZ0_F1_CBC_S  2
-/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F0_CBC    (BIT(3))
-#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
-#define MCPWM_TZ0_F0_CBC_V  0x00000001U
-#define MCPWM_TZ0_F0_CBC_S  3
-/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_SW_OST    (BIT(4))
-#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
-#define MCPWM_TZ0_SW_OST_V  0x00000001U
-#define MCPWM_TZ0_SW_OST_S  4
-/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
- *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F2_OST    (BIT(5))
-#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
-#define MCPWM_TZ0_F2_OST_V  0x00000001U
-#define MCPWM_TZ0_F2_OST_S  5
-/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
- *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F1_OST    (BIT(6))
-#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
-#define MCPWM_TZ0_F1_OST_V  0x00000001U
-#define MCPWM_TZ0_F1_OST_S  6
-/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
- *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F0_OST    (BIT(7))
-#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
-#define MCPWM_TZ0_F0_OST_V  0x00000001U
-#define MCPWM_TZ0_F0_OST_S  7
-/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_A_CBC_D    0x00000003U
-#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
-#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ0_A_CBC_D_S  8
-/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_A_CBC_U    0x00000003U
-#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
-#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ0_A_CBC_U_S  10
-/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_A_OST_D    0x00000003U
-#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
-#define MCPWM_TZ0_A_OST_D_V  0x00000003U
-#define MCPWM_TZ0_A_OST_D_S  12
-/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_A_OST_U    0x00000003U
-#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
-#define MCPWM_TZ0_A_OST_U_V  0x00000003U
-#define MCPWM_TZ0_A_OST_U_S  14
-/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_B_CBC_D    0x00000003U
-#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
-#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ0_B_CBC_D_S  16
-/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
- *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_B_CBC_U    0x00000003U
-#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
-#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ0_B_CBC_U_S  18
-/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_B_OST_D    0x00000003U
-#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
-#define MCPWM_TZ0_B_OST_D_V  0x00000003U
-#define MCPWM_TZ0_B_OST_D_S  20
-/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_B_OST_U    0x00000003U
-#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
-#define MCPWM_TZ0_B_OST_U_V  0x00000003U
-#define MCPWM_TZ0_B_OST_U_S  22
-
-/** MCPWM_FH0_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6c)
-/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_TZ0_CLR_OST    (BIT(0))
-#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
-#define MCPWM_TZ0_CLR_OST_V  0x00000001U
-#define MCPWM_TZ0_CLR_OST_S  0
-/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP
- */
-#define MCPWM_TZ0_CBCPULSE    0x00000003U
-#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
-#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ0_CBCPULSE_S  1
-/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
-#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ0_FORCE_CBC_S  3
-/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_TZ0_FORCE_OST    (BIT(4))
-#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
-#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ0_FORCE_OST_S  4
-
-/** MCPWM_FH0_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70)
-/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_TZ0_CBC_ON    (BIT(0))
-#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
-#define MCPWM_TZ0_CBC_ON_V  0x00000001U
-#define MCPWM_TZ0_CBC_ON_S  0
-/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_TZ0_OST_ON    (BIT(1))
-#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
-#define MCPWM_TZ0_OST_ON_V  0x00000001U
-#define MCPWM_TZ0_OST_ON_S  1
-
-/** MCPWM_GEN1_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74)
-/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 1 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR1_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR1_A_UPMETHOD_M  (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S)
-#define MCPWM_CMPR1_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR1_A_UPMETHOD_S  0
-/** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 1 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR1_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR1_B_UPMETHOD_M  (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S)
-#define MCPWM_CMPR1_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR1_B_UPMETHOD_S  4
-/** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR1_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR1_A_SHDW_FULL_M  (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S)
-#define MCPWM_CMPR1_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR1_A_SHDW_FULL_S  8
-/** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR1_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR1_B_SHDW_FULL_M  (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S)
-#define MCPWM_CMPR1_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR1_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN1_TSTMP_A_REG register
- *  Shadow register for register A.
- */
-#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x78)
-/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 1 time stamp A's shadow register
- */
-#define MCPWM_CMPR1_A    0x0000FFFFU
-#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
-#define MCPWM_CMPR1_A_V  0x0000FFFFU
-#define MCPWM_CMPR1_A_S  0
-
-/** MCPWM_GEN1_TSTMP_B_REG register
- *  Shadow register for register B.
- */
-#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x7c)
-/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 1 time stamp B's shadow register
- */
-#define MCPWM_CMPR1_B    0x0000FFFFU
-#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
-#define MCPWM_CMPR1_B_V  0x0000FFFFU
-#define MCPWM_CMPR1_B_S  0
-
-/** MCPWM_GEN1_CFG0_REG register
- *  Fault event T0 and T1 handling
- */
-#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80)
-/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 1's active register of configuration. When all bits
- *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
- *  1:sync;when bit3 is set to 1:disable the update.
- */
-#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
-#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_S  0
-/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 1 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN1_T0_SEL    0x00000007U
-#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
-#define MCPWM_GEN1_T0_SEL_V  0x00000007U
-#define MCPWM_GEN1_T0_SEL_S  4
-/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 1 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN1_T1_SEL    0x00000007U
-#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
-#define MCPWM_GEN1_T1_SEL_V  0x00000007U
-#define MCPWM_GEN1_T1_SEL_S  7
-
-/** MCPWM_GEN1_FORCE_REG register
- *  Permissives to force PWM1A and PWM1B outputs by software
- */
-#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84)
-/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator 1. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM1A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
-#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_A_NCIFORCE_S  10
-/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM1B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
-#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_B_NCIFORCE_S  13
-/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN1_A_REG register
- *  Actions triggered by events on PWM1A
- */
-#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88)
-/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM1A triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN1_A_UTEZ    0x00000003U
-#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
-#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_UTEZ_S  0
-/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM1A triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN1_A_UTEP    0x00000003U
-#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
-#define MCPWM_GEN1_A_UTEP_V  0x00000003U
-#define MCPWM_GEN1_A_UTEP_S  2
-/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM1A triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN1_A_UTEA    0x00000003U
-#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
-#define MCPWM_GEN1_A_UTEA_V  0x00000003U
-#define MCPWM_GEN1_A_UTEA_S  4
-/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM1A triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN1_A_UTEB    0x00000003U
-#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
-#define MCPWM_GEN1_A_UTEB_V  0x00000003U
-#define MCPWM_GEN1_A_UTEB_S  6
-/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM1A triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN1_A_UT0    0x00000003U
-#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
-#define MCPWM_GEN1_A_UT0_V  0x00000003U
-#define MCPWM_GEN1_A_UT0_S  8
-/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM1A triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN1_A_UT1    0x00000003U
-#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
-#define MCPWM_GEN1_A_UT1_V  0x00000003U
-#define MCPWM_GEN1_A_UT1_S  10
-/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM1A triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN1_A_DTEZ    0x00000003U
-#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
-#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_DTEZ_S  12
-/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM1A triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN1_A_DTEP    0x00000003U
-#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
-#define MCPWM_GEN1_A_DTEP_V  0x00000003U
-#define MCPWM_GEN1_A_DTEP_S  14
-/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM1A triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN1_A_DTEA    0x00000003U
-#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
-#define MCPWM_GEN1_A_DTEA_V  0x00000003U
-#define MCPWM_GEN1_A_DTEA_S  16
-/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM1A triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN1_A_DTEB    0x00000003U
-#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
-#define MCPWM_GEN1_A_DTEB_V  0x00000003U
-#define MCPWM_GEN1_A_DTEB_S  18
-/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM1A triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN1_A_DT0    0x00000003U
-#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
-#define MCPWM_GEN1_A_DT0_V  0x00000003U
-#define MCPWM_GEN1_A_DT0_S  20
-/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_DT1    0x00000003U
-#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
-#define MCPWM_GEN1_A_DT1_V  0x00000003U
-#define MCPWM_GEN1_A_DT1_S  22
-
-/** MCPWM_GEN1_B_REG register
- *  Actions triggered by events on PWM1B
- */
-#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8c)
-/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM1B triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN1_B_UTEZ    0x00000003U
-#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
-#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_UTEZ_S  0
-/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM1B triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN1_B_UTEP    0x00000003U
-#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
-#define MCPWM_GEN1_B_UTEP_V  0x00000003U
-#define MCPWM_GEN1_B_UTEP_S  2
-/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM1B triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN1_B_UTEA    0x00000003U
-#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
-#define MCPWM_GEN1_B_UTEA_V  0x00000003U
-#define MCPWM_GEN1_B_UTEA_S  4
-/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM1B triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN1_B_UTEB    0x00000003U
-#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
-#define MCPWM_GEN1_B_UTEB_V  0x00000003U
-#define MCPWM_GEN1_B_UTEB_S  6
-/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM1B triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN1_B_UT0    0x00000003U
-#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
-#define MCPWM_GEN1_B_UT0_V  0x00000003U
-#define MCPWM_GEN1_B_UT0_S  8
-/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM1B triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN1_B_UT1    0x00000003U
-#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
-#define MCPWM_GEN1_B_UT1_V  0x00000003U
-#define MCPWM_GEN1_B_UT1_S  10
-/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM1B triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN1_B_DTEZ    0x00000003U
-#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
-#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_DTEZ_S  12
-/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM1B triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN1_B_DTEP    0x00000003U
-#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
-#define MCPWM_GEN1_B_DTEP_V  0x00000003U
-#define MCPWM_GEN1_B_DTEP_S  14
-/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM1B triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN1_B_DTEA    0x00000003U
-#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
-#define MCPWM_GEN1_B_DTEA_V  0x00000003U
-#define MCPWM_GEN1_B_DTEA_S  16
-/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM1B triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN1_B_DTEB    0x00000003U
-#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
-#define MCPWM_GEN1_B_DTEB_V  0x00000003U
-#define MCPWM_GEN1_B_DTEB_S  18
-/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM1B triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN1_B_DT0    0x00000003U
-#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
-#define MCPWM_GEN1_B_DT0_V  0x00000003U
-#define MCPWM_GEN1_B_DT0_S  20
-/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_DT1    0x00000003U
-#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
-#define MCPWM_GEN1_B_DT1_V  0x00000003U
-#define MCPWM_GEN1_B_DT1_S  22
-
-/** MCPWM_DT1_CFG_REG register
- *  dead time type selection and configuration
- */
-#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90)
-/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (falling edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
-#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB1_FED_UPMETHOD_S  0
-/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register. 0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
-#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB1_RED_UPMETHOD_S  4
-/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB1_DEB_MODE    (BIT(8))
-#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
-#define MCPWM_DB1_DEB_MODE_V  0x00000001U
-#define MCPWM_DB1_DEB_MODE_S  8
-/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
-#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB1_A_OUTSWAP_S  9
-/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
-#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB1_B_OUTSWAP_S  10
-/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DB1_RED_INSEL    (BIT(11))
-#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
-#define MCPWM_DB1_RED_INSEL_V  0x00000001U
-#define MCPWM_DB1_RED_INSEL_S  11
-/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DB1_FED_INSEL    (BIT(12))
-#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
-#define MCPWM_DB1_FED_INSEL_V  0x00000001U
-#define MCPWM_DB1_FED_INSEL_S  12
-/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
-#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB1_RED_OUTINVERT_S  13
-/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
-#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB1_FED_OUTINVERT_S  14
-/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
-#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB1_A_OUTBYPASS_S  15
-/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
-#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB1_B_OUTBYPASS_S  16
-/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DB1_CLK_SEL    (BIT(17))
-#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
-#define MCPWM_DB1_CLK_SEL_V  0x00000001U
-#define MCPWM_DB1_CLK_SEL_S  17
-
-/** MCPWM_DT1_FED_CFG_REG register
- *  Shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94)
-/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DB1_FED    0x0000FFFFU
-#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
-#define MCPWM_DB1_FED_V  0x0000FFFFU
-#define MCPWM_DB1_FED_S  0
-
-/** MCPWM_DT1_RED_CFG_REG register
- *  Shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98)
-/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DB1_RED    0x0000FFFFU
-#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
-#define MCPWM_DB1_RED_V  0x0000FFFFU
-#define MCPWM_DB1_RED_S  0
-
-/** MCPWM_CARRIER1_CFG_REG register
- *  Carrier enable and configuratoin
- */
-#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c)
-/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier1 function is enabled. When cleared, carrier1 is bypassed
- */
-#define MCPWM_CHOPPER1_EN    (BIT(0))
-#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
-#define MCPWM_CHOPPER1_EN_V  0x00000001U
-#define MCPWM_CHOPPER1_EN_S  0
-/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
-#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER1_PRESCALE_S  1
-/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CHOPPER1_DUTY    0x00000007U
-#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
-#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER1_DUTY_S  5
-/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
-#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER1_OSHTWTH_S  8
-/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM1A and PWM1B for this submodule
- */
-#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
-#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER1_OUT_INVERT_S  12
-/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM1A and PWM1B for this submodule
- */
-#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
-#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER1_IN_INVERT_S  13
-
-/** MCPWM_FH1_CFG0_REG register
- *  Actions on PWM1A and PWM1B trip events
- */
-#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xa0)
-/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_SW_CBC    (BIT(0))
-#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
-#define MCPWM_TZ1_SW_CBC_V  0x00000001U
-#define MCPWM_TZ1_SW_CBC_S  0
-/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F2_CBC    (BIT(1))
-#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
-#define MCPWM_TZ1_F2_CBC_V  0x00000001U
-#define MCPWM_TZ1_F2_CBC_S  1
-/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F1_CBC    (BIT(2))
-#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
-#define MCPWM_TZ1_F1_CBC_V  0x00000001U
-#define MCPWM_TZ1_F1_CBC_S  2
-/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F0_CBC    (BIT(3))
-#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
-#define MCPWM_TZ1_F0_CBC_V  0x00000001U
-#define MCPWM_TZ1_F0_CBC_S  3
-/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_SW_OST    (BIT(4))
-#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
-#define MCPWM_TZ1_SW_OST_V  0x00000001U
-#define MCPWM_TZ1_SW_OST_S  4
-/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
- *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F2_OST    (BIT(5))
-#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
-#define MCPWM_TZ1_F2_OST_V  0x00000001U
-#define MCPWM_TZ1_F2_OST_S  5
-/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
- *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F1_OST    (BIT(6))
-#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
-#define MCPWM_TZ1_F1_OST_V  0x00000001U
-#define MCPWM_TZ1_F1_OST_S  6
-/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
- *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F0_OST    (BIT(7))
-#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
-#define MCPWM_TZ1_F0_OST_V  0x00000001U
-#define MCPWM_TZ1_F0_OST_S  7
-/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_A_CBC_D    0x00000003U
-#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
-#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ1_A_CBC_D_S  8
-/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_A_CBC_U    0x00000003U
-#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
-#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ1_A_CBC_U_S  10
-/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0:
- *  do nothing,1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_A_OST_D    0x00000003U
-#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
-#define MCPWM_TZ1_A_OST_D_V  0x00000003U
-#define MCPWM_TZ1_A_OST_D_S  12
-/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_A_OST_U    0x00000003U
-#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
-#define MCPWM_TZ1_A_OST_U_V  0x00000003U
-#define MCPWM_TZ1_A_OST_U_S  14
-/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_B_CBC_D    0x00000003U
-#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
-#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ1_B_CBC_D_S  16
-/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_B_CBC_U    0x00000003U
-#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
-#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ1_B_CBC_U_S  18
-/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_B_OST_D    0x00000003U
-#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
-#define MCPWM_TZ1_B_OST_D_V  0x00000003U
-#define MCPWM_TZ1_B_OST_D_S  20
-/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_B_OST_U    0x00000003U
-#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
-#define MCPWM_TZ1_B_OST_U_V  0x00000003U
-#define MCPWM_TZ1_B_OST_U_S  22
-
-/** MCPWM_FH1_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa4)
-/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_TZ1_CLR_OST    (BIT(0))
-#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
-#define MCPWM_TZ1_CLR_OST_V  0x00000001U
-#define MCPWM_TZ1_CLR_OST_S  0
-/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP
- */
-#define MCPWM_TZ1_CBCPULSE    0x00000003U
-#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
-#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ1_CBCPULSE_S  1
-/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
-#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ1_FORCE_CBC_S  3
-/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_TZ1_FORCE_OST    (BIT(4))
-#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
-#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ1_FORCE_OST_S  4
-
-/** MCPWM_FH1_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa8)
-/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_TZ1_CBC_ON    (BIT(0))
-#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
-#define MCPWM_TZ1_CBC_ON_V  0x00000001U
-#define MCPWM_TZ1_CBC_ON_S  0
-/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_TZ1_OST_ON    (BIT(1))
-#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
-#define MCPWM_TZ1_OST_ON_V  0x00000001U
-#define MCPWM_TZ1_OST_ON_S  1
-
-/** MCPWM_GEN2_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xac)
-/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 2 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR2_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR2_A_UPMETHOD_M  (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S)
-#define MCPWM_CMPR2_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR2_A_UPMETHOD_S  0
-/** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 2 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR2_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR2_B_UPMETHOD_M  (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S)
-#define MCPWM_CMPR2_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR2_B_UPMETHOD_S  4
-/** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR2_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR2_A_SHDW_FULL_M  (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S)
-#define MCPWM_CMPR2_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR2_A_SHDW_FULL_S  8
-/** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR2_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR2_B_SHDW_FULL_M  (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S)
-#define MCPWM_CMPR2_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR2_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN2_TSTMP_A_REG register
- *  Shadow register for register A.
- */
-#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xb0)
-/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 2 time stamp A's shadow register
- */
-#define MCPWM_CMPR2_A    0x0000FFFFU
-#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
-#define MCPWM_CMPR2_A_V  0x0000FFFFU
-#define MCPWM_CMPR2_A_S  0
-
-/** MCPWM_GEN2_TSTMP_B_REG register
- *  Shadow register for register B.
- */
-#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb4)
-/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 2 time stamp B's shadow register
- */
-#define MCPWM_CMPR2_B    0x0000FFFFU
-#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
-#define MCPWM_CMPR2_B_V  0x0000FFFFU
-#define MCPWM_CMPR2_B_S  0
-
-/** MCPWM_GEN2_CFG0_REG register
- *  Fault event T0 and T1 handling
- */
-#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb8)
-/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 2's active register of configuration. 0:
- *  immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is
- *  set to 1:disable the update.
- */
-#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
-#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_S  0
-/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 2 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN2_T0_SEL    0x00000007U
-#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
-#define MCPWM_GEN2_T0_SEL_V  0x00000007U
-#define MCPWM_GEN2_T0_SEL_S  4
-/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 2 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN2_T1_SEL    0x00000007U
-#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
-#define MCPWM_GEN2_T1_SEL_V  0x00000007U
-#define MCPWM_GEN2_T1_SEL_S  7
-
-/** MCPWM_GEN2_FORCE_REG register
- *  Permissives to force PWM2A and PWM2B outputs by software
- */
-#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xbc)
-/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator 2. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM2A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
-#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_A_NCIFORCE_S  10
-/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM2B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
-#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_B_NCIFORCE_S  13
-/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN2_A_REG register
- *  Actions triggered by events on PWM2A
- */
-#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xc0)
-/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM2A triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN2_A_UTEZ    0x00000003U
-#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
-#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_UTEZ_S  0
-/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM2A triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN2_A_UTEP    0x00000003U
-#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
-#define MCPWM_GEN2_A_UTEP_V  0x00000003U
-#define MCPWM_GEN2_A_UTEP_S  2
-/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM2A triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN2_A_UTEA    0x00000003U
-#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
-#define MCPWM_GEN2_A_UTEA_V  0x00000003U
-#define MCPWM_GEN2_A_UTEA_S  4
-/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM2A triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN2_A_UTEB    0x00000003U
-#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
-#define MCPWM_GEN2_A_UTEB_V  0x00000003U
-#define MCPWM_GEN2_A_UTEB_S  6
-/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM2A triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN2_A_UT0    0x00000003U
-#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
-#define MCPWM_GEN2_A_UT0_V  0x00000003U
-#define MCPWM_GEN2_A_UT0_S  8
-/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM2A triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN2_A_UT1    0x00000003U
-#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
-#define MCPWM_GEN2_A_UT1_V  0x00000003U
-#define MCPWM_GEN2_A_UT1_S  10
-/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM2A triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN2_A_DTEZ    0x00000003U
-#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
-#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_DTEZ_S  12
-/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM2A triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN2_A_DTEP    0x00000003U
-#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
-#define MCPWM_GEN2_A_DTEP_V  0x00000003U
-#define MCPWM_GEN2_A_DTEP_S  14
-/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM2A triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN2_A_DTEA    0x00000003U
-#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
-#define MCPWM_GEN2_A_DTEA_V  0x00000003U
-#define MCPWM_GEN2_A_DTEA_S  16
-/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM2A triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN2_A_DTEB    0x00000003U
-#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
-#define MCPWM_GEN2_A_DTEB_V  0x00000003U
-#define MCPWM_GEN2_A_DTEB_S  18
-/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM2A triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN2_A_DT0    0x00000003U
-#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
-#define MCPWM_GEN2_A_DT0_V  0x00000003U
-#define MCPWM_GEN2_A_DT0_S  20
-/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_DT1    0x00000003U
-#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
-#define MCPWM_GEN2_A_DT1_V  0x00000003U
-#define MCPWM_GEN2_A_DT1_S  22
-
-/** MCPWM_GEN2_B_REG register
- *  Actions triggered by events on PWM2B
- */
-#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc4)
-/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM2B triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN2_B_UTEZ    0x00000003U
-#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
-#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_UTEZ_S  0
-/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM2B triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN2_B_UTEP    0x00000003U
-#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
-#define MCPWM_GEN2_B_UTEP_V  0x00000003U
-#define MCPWM_GEN2_B_UTEP_S  2
-/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM2B triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN2_B_UTEA    0x00000003U
-#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
-#define MCPWM_GEN2_B_UTEA_V  0x00000003U
-#define MCPWM_GEN2_B_UTEA_S  4
-/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM2B triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN2_B_UTEB    0x00000003U
-#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
-#define MCPWM_GEN2_B_UTEB_V  0x00000003U
-#define MCPWM_GEN2_B_UTEB_S  6
-/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM2B triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN2_B_UT0    0x00000003U
-#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
-#define MCPWM_GEN2_B_UT0_V  0x00000003U
-#define MCPWM_GEN2_B_UT0_S  8
-/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM2B triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN2_B_UT1    0x00000003U
-#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
-#define MCPWM_GEN2_B_UT1_V  0x00000003U
-#define MCPWM_GEN2_B_UT1_S  10
-/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM2B triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN2_B_DTEZ    0x00000003U
-#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
-#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_DTEZ_S  12
-/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM2B triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN2_B_DTEP    0x00000003U
-#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
-#define MCPWM_GEN2_B_DTEP_V  0x00000003U
-#define MCPWM_GEN2_B_DTEP_S  14
-/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM2B triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN2_B_DTEA    0x00000003U
-#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
-#define MCPWM_GEN2_B_DTEA_V  0x00000003U
-#define MCPWM_GEN2_B_DTEA_S  16
-/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM2B triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN2_B_DTEB    0x00000003U
-#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
-#define MCPWM_GEN2_B_DTEB_V  0x00000003U
-#define MCPWM_GEN2_B_DTEB_S  18
-/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM2B triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN2_B_DT0    0x00000003U
-#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
-#define MCPWM_GEN2_B_DT0_V  0x00000003U
-#define MCPWM_GEN2_B_DT0_S  20
-/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_DT1    0x00000003U
-#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
-#define MCPWM_GEN2_B_DT1_V  0x00000003U
-#define MCPWM_GEN2_B_DT1_S  22
-
-/** MCPWM_DT2_CFG_REG register
- *  dead time type selection and configuration
- */
-#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8)
-/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (falling edge delay) active register.  0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
-#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB2_FED_UPMETHOD_S  0
-/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register.  0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
-#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB2_RED_UPMETHOD_S  4
-/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB2_DEB_MODE    (BIT(8))
-#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
-#define MCPWM_DB2_DEB_MODE_V  0x00000001U
-#define MCPWM_DB2_DEB_MODE_S  8
-/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
-#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB2_A_OUTSWAP_S  9
-/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
-#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB2_B_OUTSWAP_S  10
-/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DB2_RED_INSEL    (BIT(11))
-#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
-#define MCPWM_DB2_RED_INSEL_V  0x00000001U
-#define MCPWM_DB2_RED_INSEL_S  11
-/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DB2_FED_INSEL    (BIT(12))
-#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
-#define MCPWM_DB2_FED_INSEL_V  0x00000001U
-#define MCPWM_DB2_FED_INSEL_S  12
-/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
-#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB2_RED_OUTINVERT_S  13
-/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
-#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB2_FED_OUTINVERT_S  14
-/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
-#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB2_A_OUTBYPASS_S  15
-/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
-#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB2_B_OUTBYPASS_S  16
-/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DB2_CLK_SEL    (BIT(17))
-#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
-#define MCPWM_DB2_CLK_SEL_V  0x00000001U
-#define MCPWM_DB2_CLK_SEL_S  17
-
-/** MCPWM_DT2_FED_CFG_REG register
- *  Shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc)
-/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DB2_FED    0x0000FFFFU
-#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
-#define MCPWM_DB2_FED_V  0x0000FFFFU
-#define MCPWM_DB2_FED_S  0
-
-/** MCPWM_DT2_RED_CFG_REG register
- *  Shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0)
-/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DB2_RED    0x0000FFFFU
-#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
-#define MCPWM_DB2_RED_V  0x0000FFFFU
-#define MCPWM_DB2_RED_S  0
-
-/** MCPWM_CARRIER2_CFG_REG register
- *  Carrier enable and configuratoin
- */
-#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4)
-/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier2 function is enabled. When cleared, carrier2 is bypassed
- */
-#define MCPWM_CHOPPER2_EN    (BIT(0))
-#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
-#define MCPWM_CHOPPER2_EN_V  0x00000001U
-#define MCPWM_CHOPPER2_EN_S  0
-/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
-#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER2_PRESCALE_S  1
-/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CHOPPER2_DUTY    0x00000007U
-#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
-#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER2_DUTY_S  5
-/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
-#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER2_OSHTWTH_S  8
-/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM2A and PWM2B for this submodule
- */
-#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
-#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER2_OUT_INVERT_S  12
-/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM2A and PWM2B for this submodule
- */
-#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
-#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER2_IN_INVERT_S  13
-
-/** MCPWM_FH2_CFG0_REG register
- *  Actions on PWM2A and PWM2B trip events
- */
-#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd8)
-/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_SW_CBC    (BIT(0))
-#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
-#define MCPWM_TZ2_SW_CBC_V  0x00000001U
-#define MCPWM_TZ2_SW_CBC_S  0
-/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F2_CBC    (BIT(1))
-#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
-#define MCPWM_TZ2_F2_CBC_V  0x00000001U
-#define MCPWM_TZ2_F2_CBC_S  1
-/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F1_CBC    (BIT(2))
-#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
-#define MCPWM_TZ2_F1_CBC_V  0x00000001U
-#define MCPWM_TZ2_F1_CBC_S  2
-/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F0_CBC    (BIT(3))
-#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
-#define MCPWM_TZ2_F0_CBC_V  0x00000001U
-#define MCPWM_TZ2_F0_CBC_S  3
-/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_SW_OST    (BIT(4))
-#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
-#define MCPWM_TZ2_SW_OST_V  0x00000001U
-#define MCPWM_TZ2_SW_OST_S  4
-/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
- *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F2_OST    (BIT(5))
-#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
-#define MCPWM_TZ2_F2_OST_V  0x00000001U
-#define MCPWM_TZ2_F2_OST_S  5
-/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
- *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F1_OST    (BIT(6))
-#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
-#define MCPWM_TZ2_F1_OST_V  0x00000001U
-#define MCPWM_TZ2_F1_OST_S  6
-/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
- *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F0_OST    (BIT(7))
-#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
-#define MCPWM_TZ2_F0_OST_V  0x00000001U
-#define MCPWM_TZ2_F0_OST_S  7
-/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_A_CBC_D    0x00000003U
-#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
-#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ2_A_CBC_D_S  8
-/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_A_CBC_U    0x00000003U
-#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
-#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ2_A_CBC_U_S  10
-/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_A_OST_D    0x00000003U
-#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
-#define MCPWM_TZ2_A_OST_D_V  0x00000003U
-#define MCPWM_TZ2_A_OST_D_S  12
-/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_A_OST_U    0x00000003U
-#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
-#define MCPWM_TZ2_A_OST_U_V  0x00000003U
-#define MCPWM_TZ2_A_OST_U_S  14
-/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_B_CBC_D    0x00000003U
-#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
-#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ2_B_CBC_D_S  16
-/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_B_CBC_U    0x00000003U
-#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
-#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ2_B_CBC_U_S  18
-/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_B_OST_D    0x00000003U
-#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
-#define MCPWM_TZ2_B_OST_D_V  0x00000003U
-#define MCPWM_TZ2_B_OST_D_S  20
-/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_B_OST_U    0x00000003U
-#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
-#define MCPWM_TZ2_B_OST_U_V  0x00000003U
-#define MCPWM_TZ2_B_OST_U_S  22
-
-/** MCPWM_FH2_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xdc)
-/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_TZ2_CLR_OST    (BIT(0))
-#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
-#define MCPWM_TZ2_CLR_OST_V  0x00000001U
-#define MCPWM_TZ2_CLR_OST_S  0
-/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP
- */
-#define MCPWM_TZ2_CBCPULSE    0x00000003U
-#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
-#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ2_CBCPULSE_S  1
-/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
-#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ2_FORCE_CBC_S  3
-/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_TZ2_FORCE_OST    (BIT(4))
-#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
-#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ2_FORCE_OST_S  4
-
-/** MCPWM_FH2_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xe0)
-/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_TZ2_CBC_ON    (BIT(0))
-#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
-#define MCPWM_TZ2_CBC_ON_V  0x00000001U
-#define MCPWM_TZ2_CBC_ON_S  0
-/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_TZ2_OST_ON    (BIT(1))
-#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
-#define MCPWM_TZ2_OST_ON_V  0x00000001U
-#define MCPWM_TZ2_OST_ON_S  1
-
-/** MCPWM_FAULT_DETECT_REG register
- *  Fault detection configuration and status
- */
-#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe4)
-/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, event_f0 generation is enabled
- */
-#define MCPWM_F0_EN    (BIT(0))
-#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
-#define MCPWM_F0_EN_V  0x00000001U
-#define MCPWM_F0_EN_S  0
-/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
- *  When set, event_f1 generation is enabled
- */
-#define MCPWM_F1_EN    (BIT(1))
-#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
-#define MCPWM_F1_EN_V  0x00000001U
-#define MCPWM_F1_EN_S  1
-/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
- *  When set, event_f2 generation is enabled
- */
-#define MCPWM_F2_EN    (BIT(2))
-#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
-#define MCPWM_F2_EN_V  0x00000001U
-#define MCPWM_F2_EN_S  2
-/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
- *  Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
- *  level high
- */
-#define MCPWM_F0_POLE    (BIT(3))
-#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
-#define MCPWM_F0_POLE_V  0x00000001U
-#define MCPWM_F0_POLE_S  3
-/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
- *  Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
- *  level high
- */
-#define MCPWM_F1_POLE    (BIT(4))
-#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
-#define MCPWM_F1_POLE_V  0x00000001U
-#define MCPWM_F1_POLE_S  4
-/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
- *  Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
- *  level high
- */
-#define MCPWM_F2_POLE    (BIT(5))
-#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
-#define MCPWM_F2_POLE_V  0x00000001U
-#define MCPWM_F2_POLE_S  5
-/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
- *  Set and reset by hardware. If set, event_f0 is on going
- */
-#define MCPWM_EVENT_F0    (BIT(6))
-#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
-#define MCPWM_EVENT_F0_V  0x00000001U
-#define MCPWM_EVENT_F0_S  6
-/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
- *  Set and reset by hardware. If set, event_f1 is on going
- */
-#define MCPWM_EVENT_F1    (BIT(7))
-#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
-#define MCPWM_EVENT_F1_V  0x00000001U
-#define MCPWM_EVENT_F1_S  7
-/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, event_f2 is on going
- */
-#define MCPWM_EVENT_F2    (BIT(8))
-#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
-#define MCPWM_EVENT_F2_V  0x00000001U
-#define MCPWM_EVENT_F2_S  8
-
-/** MCPWM_CAP_TIMER_CFG_REG register
- *  Configure capture timer
- */
-#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe8)
-/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture timer incrementing under APB_clk is enabled.
- */
-#define MCPWM_CAP_TIMER_EN    (BIT(0))
-#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
-#define MCPWM_CAP_TIMER_EN_V  0x00000001U
-#define MCPWM_CAP_TIMER_EN_S  0
-/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
- *  When set, capture timer sync is enabled.
- */
-#define MCPWM_CAP_SYNCI_EN    (BIT(1))
-#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
-#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
-#define MCPWM_CAP_SYNCI_EN_S  1
-/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
- *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
- *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
- *  6: SYNC2 from GPIO matrix
- */
-#define MCPWM_CAP_SYNCI_SEL    0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
-#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_S  2
-/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
- *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
- *  timer is loaded with value in phase register.
- */
-#define MCPWM_CAP_SYNC_SW    (BIT(5))
-#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
-#define MCPWM_CAP_SYNC_SW_V  0x00000001U
-#define MCPWM_CAP_SYNC_SW_S  5
-
-/** MCPWM_CAP_TIMER_PHASE_REG register
- *  Phase for capture timer sync
- */
-#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xec)
-/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
- *  Phase value for capture timer sync operation.
- */
-#define MCPWM_CAP_PHASE    0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
-#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_S  0
-
-/** MCPWM_CAP_CH0_CFG_REG register
- *  Capture channel 0 configuration and enable
- */
-#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 0 is enabled
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
- *  1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP0 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 0
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH1_CFG_REG register
- *  Capture channel 1 configuration and enable
- */
-#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4)
-/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 2 is enabled
- */
-#define MCPWM_CAP1_EN    (BIT(0))
-#define MCPWM_CAP1_EN_M  (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S)
-#define MCPWM_CAP1_EN_V  0x00000001U
-#define MCPWM_CAP1_EN_S  0
-/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP1_MODE    0x00000003U
-#define MCPWM_CAP1_MODE_M  (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S)
-#define MCPWM_CAP1_MODE_V  0x00000003U
-#define MCPWM_CAP1_MODE_S  1
-/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
- *  1
- */
-#define MCPWM_CAP1_PRESCALE    0x000000FFU
-#define MCPWM_CAP1_PRESCALE_M  (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S)
-#define MCPWM_CAP1_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP1_PRESCALE_S  3
-/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP1 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP1_IN_INVERT    (BIT(11))
-#define MCPWM_CAP1_IN_INVERT_M  (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S)
-#define MCPWM_CAP1_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP1_IN_INVERT_S  11
-/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 1
- */
-#define MCPWM_CAP1_SW    (BIT(12))
-#define MCPWM_CAP1_SW_M  (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S)
-#define MCPWM_CAP1_SW_V  0x00000001U
-#define MCPWM_CAP1_SW_S  12
-
-/** MCPWM_CAP_CH2_CFG_REG register
- *  Capture channel 2 configuration and enable
- */
-#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf8)
-/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 2 is enabled
- */
-#define MCPWM_CAP2_EN    (BIT(0))
-#define MCPWM_CAP2_EN_M  (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S)
-#define MCPWM_CAP2_EN_V  0x00000001U
-#define MCPWM_CAP2_EN_S  0
-/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP2_MODE    0x00000003U
-#define MCPWM_CAP2_MODE_M  (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S)
-#define MCPWM_CAP2_MODE_V  0x00000003U
-#define MCPWM_CAP2_MODE_S  1
-/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
- *  1
- */
-#define MCPWM_CAP2_PRESCALE    0x000000FFU
-#define MCPWM_CAP2_PRESCALE_M  (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S)
-#define MCPWM_CAP2_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP2_PRESCALE_S  3
-/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP2 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP2_IN_INVERT    (BIT(11))
-#define MCPWM_CAP2_IN_INVERT_M  (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S)
-#define MCPWM_CAP2_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP2_IN_INVERT_S  11
-/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 2
- */
-#define MCPWM_CAP2_SW    (BIT(12))
-#define MCPWM_CAP2_SW_M  (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S)
-#define MCPWM_CAP2_SW_V  0x00000001U
-#define MCPWM_CAP2_SW_S  12
-
-/** MCPWM_CAP_CH0_REG register
- *  ch0 capture value status register
- */
-#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xfc)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 0
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_CH1_REG register
- *  ch1 capture value status register
- */
-#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100)
-/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 1
- */
-#define MCPWM_CAP1_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP1_VALUE_M  (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S)
-#define MCPWM_CAP1_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP1_VALUE_S  0
-
-/** MCPWM_CAP_CH2_REG register
- *  ch2 capture value status register
- */
-#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104)
-/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 2
- */
-#define MCPWM_CAP2_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP2_VALUE_M  (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S)
-#define MCPWM_CAP2_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP2_VALUE_S  0
-
-/** MCPWM_CAP_STATUS_REG register
- *  Edge of last capture trigger
- */
-#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108)
-/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
- *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP0_EDGE    (BIT(0))
-#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
-#define MCPWM_CAP0_EDGE_V  0x00000001U
-#define MCPWM_CAP0_EDGE_S  0
-/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
- *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP1_EDGE    (BIT(1))
-#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
-#define MCPWM_CAP1_EDGE_V  0x00000001U
-#define MCPWM_CAP1_EDGE_S  1
-/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
- *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP2_EDGE    (BIT(2))
-#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
-#define MCPWM_CAP2_EDGE_V  0x00000001U
-#define MCPWM_CAP2_EDGE_S  2
-
-/** MCPWM_UPDATE_CFG_REG register
- *  Enable update.
- */
-#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10c)
-/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
- *  The global enable of update of all active registers in MCPWM module
- */
-#define MCPWM_GLOBAL_UP_EN    (BIT(0))
-#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
-#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
-#define MCPWM_GLOBAL_UP_EN_S  0
-/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of all active
- *  registers in MCPWM module
- */
-#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
-#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
-#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
-#define MCPWM_GLOBAL_FORCE_UP_S  1
-/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
- *  are enabled
- */
-#define MCPWM_OP0_UP_EN    (BIT(2))
-#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
-#define MCPWM_OP0_UP_EN_V  0x00000001U
-#define MCPWM_OP0_UP_EN_S  2
-/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 0
- */
-#define MCPWM_OP0_FORCE_UP    (BIT(3))
-#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
-#define MCPWM_OP0_FORCE_UP_V  0x00000001U
-#define MCPWM_OP0_FORCE_UP_S  3
-/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
- *  are enabled
- */
-#define MCPWM_OP1_UP_EN    (BIT(4))
-#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
-#define MCPWM_OP1_UP_EN_V  0x00000001U
-#define MCPWM_OP1_UP_EN_S  4
-/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 1
- */
-#define MCPWM_OP1_FORCE_UP    (BIT(5))
-#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
-#define MCPWM_OP1_FORCE_UP_V  0x00000001U
-#define MCPWM_OP1_FORCE_UP_S  5
-/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
- *  are enabled
- */
-#define MCPWM_OP2_UP_EN    (BIT(6))
-#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
-#define MCPWM_OP2_UP_EN_V  0x00000001U
-#define MCPWM_OP2_UP_EN_S  6
-/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 2
- */
-#define MCPWM_OP2_FORCE_UP    (BIT(7))
-#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
-#define MCPWM_OP2_FORCE_UP_V  0x00000001U
-#define MCPWM_OP2_FORCE_UP_S  7
-
-/** MCPWM_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x110)
-/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
-#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ENA_S  0
-/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
-#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ENA_S  1
-/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
-#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ENA_S  2
-/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
-#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
-/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
-#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
-/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
-#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
-/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
-#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ENA_S  6
-/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
-#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ENA_S  7
-/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
-#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ENA_S  8
-/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The enable bit for the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ENA    (BIT(9))
-#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
-#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_INT_ENA_S  9
-/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ENA    (BIT(10))
-#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
-#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_INT_ENA_S  10
-/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The enable bit for the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ENA    (BIT(11))
-#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
-#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_INT_ENA_S  11
-/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The enable bit for the interrupt triggered when event_f0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
-#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ENA_S  12
-/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The enable bit for the interrupt triggered when event_f1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
-#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ENA_S  13
-/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The enable bit for the interrupt triggered when event_f2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
-#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ENA_S  14
-/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
-#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ENA_S  15
-/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
-#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ENA_S  16
-/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
-#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ENA_S  17
-/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
-#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ENA_S  18
-/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
-#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ENA_S  19
-/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
-#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ENA_S  20
-/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
-#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ENA_S  21
-/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
-#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ENA_S  22
-/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
-#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ENA_S  23
-/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
-#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ENA_S  24
-/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
-#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ENA_S  25
-/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
-#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ENA_S  26
-/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_ENA    (BIT(27))
-#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
-#define MCPWM_CAP0_INT_ENA_V  0x00000001U
-#define MCPWM_CAP0_INT_ENA_S  27
-/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_ENA    (BIT(28))
-#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
-#define MCPWM_CAP1_INT_ENA_V  0x00000001U
-#define MCPWM_CAP1_INT_ENA_S  28
-/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_ENA    (BIT(29))
-#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
-#define MCPWM_CAP2_INT_ENA_V  0x00000001U
-#define MCPWM_CAP2_INT_ENA_S  29
-
-/** MCPWM_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x114)
-/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
-#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_RAW_S  0
-/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
-#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_RAW_S  1
-/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
-#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_RAW_S  2
-/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
-#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
-/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
-#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
-/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
-#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
-/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
-#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_RAW_S  6
-/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
-#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_RAW_S  7
-/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
-#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_RAW_S  8
-/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_RAW    (BIT(9))
-#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
-#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_INT_RAW_S  9
-/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_RAW    (BIT(10))
-#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
-#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_INT_RAW_S  10
-/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_RAW    (BIT(11))
-#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
-#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_INT_RAW_S  11
-/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
-#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_RAW_S  12
-/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
-#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_RAW_S  13
-/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
-#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_RAW_S  14
-/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
-#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_RAW_S  15
-/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
-#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_RAW_S  16
-/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
-#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_RAW_S  17
-/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
-#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_RAW_S  18
-/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
-#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_RAW_S  19
-/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
-#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_RAW_S  20
-/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
-#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_RAW_S  21
-/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
-#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_RAW_S  22
-/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
-#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_RAW_S  23
-/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
-#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
-#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_RAW_S  24
-/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
-#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
-#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_RAW_S  25
-/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
-#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
-#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_RAW_S  26
-/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_RAW    (BIT(27))
-#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
-#define MCPWM_CAP0_INT_RAW_V  0x00000001U
-#define MCPWM_CAP0_INT_RAW_S  27
-/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_RAW    (BIT(28))
-#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
-#define MCPWM_CAP1_INT_RAW_V  0x00000001U
-#define MCPWM_CAP1_INT_RAW_S  28
-/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_RAW    (BIT(29))
-#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
-#define MCPWM_CAP2_INT_RAW_V  0x00000001U
-#define MCPWM_CAP2_INT_RAW_S  29
-
-/** MCPWM_INT_ST_REG register
- *  Masked interrupt status
- */
-#define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x118)
-/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
-#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ST_S  0
-/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
-#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ST_S  1
-/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
-#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ST_S  2
-/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
-#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ST_S  3
-/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
-#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ST_S  4
-/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
-#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ST_S  5
-/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
-#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ST_S  6
-/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
-#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ST_S  7
-/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
-#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ST_S  8
-/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ST    (BIT(9))
-#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
-#define MCPWM_FAULT0_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_INT_ST_S  9
-/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ST    (BIT(10))
-#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
-#define MCPWM_FAULT1_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_INT_ST_S  10
-/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ST    (BIT(11))
-#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
-#define MCPWM_FAULT2_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_INT_ST_S  11
-/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
-#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ST_S  12
-/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
-#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ST_S  13
-/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
-#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ST_S  14
-/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
-#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ST_S  15
-/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
-#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ST_S  16
-/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
-#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ST_S  17
-/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
-#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ST_S  18
-/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
-#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ST_S  19
-/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
-#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ST_S  20
-/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
-#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ST_S  21
-/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
-#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ST_S  22
-/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
-#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ST_S  23
-/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
-#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ST_S  24
-/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
-#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ST_S  25
-/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
-#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ST_S  26
-/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_ST    (BIT(27))
-#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
-#define MCPWM_CAP0_INT_ST_V  0x00000001U
-#define MCPWM_CAP0_INT_ST_S  27
-/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_ST    (BIT(28))
-#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
-#define MCPWM_CAP1_INT_ST_V  0x00000001U
-#define MCPWM_CAP1_INT_ST_S  28
-/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_ST    (BIT(29))
-#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
-#define MCPWM_CAP2_INT_ST_V  0x00000001U
-#define MCPWM_CAP2_INT_ST_S  29
-
-/** MCPWM_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x11c)
-/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
-#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_CLR_S  0
-/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
-#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_CLR_S  1
-/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
-#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_CLR_S  2
-/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
-#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
-/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
-#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
-/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
-#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
-/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
-#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_CLR_S  6
-/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
-#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_CLR_S  7
-/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
-#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_CLR_S  8
-/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_CLR    (BIT(9))
-#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
-#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_INT_CLR_S  9
-/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_CLR    (BIT(10))
-#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
-#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_INT_CLR_S  10
-/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_CLR    (BIT(11))
-#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
-#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_INT_CLR_S  11
-/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
-#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_CLR_S  12
-/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
-#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_CLR_S  13
-/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
-#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_CLR_S  14
-/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
-#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_CLR_S  15
-/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
-#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_CLR_S  16
-/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
-#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_CLR_S  17
-/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
-#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_CLR_S  18
-/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
-#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_CLR_S  19
-/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
-#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_CLR_S  20
-/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
-#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_CLR_S  21
-/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
-#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_CLR_S  22
-/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
-#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_CLR_S  23
-/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
-#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
-#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_CLR_S  24
-/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
-#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
-#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_CLR_S  25
-/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
-#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
-#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_CLR_S  26
-/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_CLR    (BIT(27))
-#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
-#define MCPWM_CAP0_INT_CLR_V  0x00000001U
-#define MCPWM_CAP0_INT_CLR_S  27
-/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_CLR    (BIT(28))
-#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
-#define MCPWM_CAP1_INT_CLR_V  0x00000001U
-#define MCPWM_CAP1_INT_CLR_S  28
-/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_CLR    (BIT(29))
-#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
-#define MCPWM_CAP2_INT_CLR_V  0x00000001U
-#define MCPWM_CAP2_INT_CLR_S  29
-
-/** MCPWM_EVT_EN_REG register
- *  MCPWM event enable register
- */
-#define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120)
-/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
- *  set this bit high to enable timer0 stop event generate
- */
-#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
-#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
-#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_STOP_EN_S  0
-/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
- *  set this bit high to enable timer1 stop event generate
- */
-#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
-#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
-#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_STOP_EN_S  1
-/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
- *  set this bit high to enable timer2 stop event generate
- */
-#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
-#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
-#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_STOP_EN_S  2
-/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
- *  set this bit high to enable timer0 equal zero event generate
- */
-#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
-#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
-#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
-/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
- *  set this bit high to enable timer1 equal zero event generate
- */
-#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
-#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
-#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
-/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
- *  set this bit high to enable timer2 equal zero event generate
- */
-#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
-#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
-#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
-/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
- *  set this bit high to enable timer0 equal period event generate
- */
-#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
-#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
-#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEP_EN_S  6
-/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
- *  set this bit high to enable timer1 equal period event generate
- */
-#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
-#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
-#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEP_EN_S  7
-/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
- *  set this bit high to enable timer2 equal period event generate
- */
-#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
-#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
-#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEP_EN_S  8
-/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
- *  set this bit high to enable PWM generator0 timer equal a event generate
- */
-#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
-#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
-#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEA_EN_S  9
-/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
- *  set this bit high to enable PWM generator1 timer equal a event generate
- */
-#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
-#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
-#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEA_EN_S  10
-/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
- *  set this bit high to enable PWM generator2 timer equal a event generate
- */
-#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
-#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
-#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEA_EN_S  11
-/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
- *  set this bit high to enable PWM generator0 timer equal b event generate
- */
-#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
-#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
-#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEB_EN_S  12
-/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
- *  set this bit high to enable PWM generator1 timer equal b event generate
- */
-#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
-#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
-#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEB_EN_S  13
-/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
- *  set this bit high to enable PWM generator2 timer equal b event generate
- */
-#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
-#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
-#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEB_EN_S  14
-/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
- *  set this bit high to enable fault0 event generate
- */
-#define MCPWM_EVT_F0_EN    (BIT(15))
-#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
-#define MCPWM_EVT_F0_EN_V  0x00000001U
-#define MCPWM_EVT_F0_EN_S  15
-/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
- *  set this bit high to enable fault1 event generate
- */
-#define MCPWM_EVT_F1_EN    (BIT(16))
-#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
-#define MCPWM_EVT_F1_EN_V  0x00000001U
-#define MCPWM_EVT_F1_EN_S  16
-/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
- *  set this bit high to enable fault2 event generate
- */
-#define MCPWM_EVT_F2_EN    (BIT(17))
-#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
-#define MCPWM_EVT_F2_EN_V  0x00000001U
-#define MCPWM_EVT_F2_EN_S  17
-/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
- *  set this bit high to enable fault0 clear event generate
- */
-#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
-#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
-#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F0_CLR_EN_S  18
-/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  set this bit high to enable fault1 clear event generate
- */
-#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
-#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
-#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F1_CLR_EN_S  19
-/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  set this bit high to enable fault2 clear event generate
- */
-#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
-#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
-#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F2_CLR_EN_S  20
-/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
- *  set this bit high to enable cycle by cycle trip0 event generate
- */
-#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
-#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
-#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_CBC_EN_S  21
-/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
- *  set this bit high to enable cycle by cycle trip1 event generate
- */
-#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
-#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
-#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_CBC_EN_S  22
-/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
- *  set this bit high to enable cycle by cycle trip2 event generate
- */
-#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
-#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
-#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_CBC_EN_S  23
-/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
- *  set this bit high to enable one shot trip0 event generate
- */
-#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
-#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
-#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_OST_EN_S  24
-/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
- *  set this bit high to enable one shot trip1 event generate
- */
-#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
-#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
-#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_OST_EN_S  25
-/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
- *  set this bit high to enable one shot trip2 event generate
- */
-#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
-#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
-#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_OST_EN_S  26
-/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
- *  set this bit high to enable capture0 event generate
- */
-#define MCPWM_EVT_CAP0_EN    (BIT(27))
-#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
-#define MCPWM_EVT_CAP0_EN_V  0x00000001U
-#define MCPWM_EVT_CAP0_EN_S  27
-/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
- *  set this bit high to enable capture1 event generate
- */
-#define MCPWM_EVT_CAP1_EN    (BIT(28))
-#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
-#define MCPWM_EVT_CAP1_EN_V  0x00000001U
-#define MCPWM_EVT_CAP1_EN_S  28
-/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
- *  set this bit high to enable capture2 event generate
- */
-#define MCPWM_EVT_CAP2_EN    (BIT(29))
-#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
-#define MCPWM_EVT_CAP2_EN_V  0x00000001U
-#define MCPWM_EVT_CAP2_EN_S  29
-
-/** MCPWM_TASK_EN_REG register
- *  MCPWM task enable register
- */
-#define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x124)
-/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
- *  set this bit high to enable PWM generator0 timer stamp A's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
-#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
-#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
-/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
- *  set this bit high to enable PWM generator1 timer stamp A's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
-#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
-#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
-/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
- *  set this bit high to enable PWM generator2 timer stamp A's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
-#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
-#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
-/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
- *  set this bit high to enable PWM generator0 timer stamp B's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
-#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
-#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
-/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
- *  set this bit high to enable PWM generator1 timer stamp B's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
-#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
-#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
-/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
- *  set this bit high to enable PWM generator2 timer stamp B's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
-#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
-#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
-/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
- *  set this bit high to enable all PWM generate stop task receive
- */
-#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
-#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
-#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
-#define MCPWM_TASK_GEN_STOP_EN_S  6
-/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
- *  set this bit high to enable timer0 sync task receive
- */
-#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
-#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
-#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
-/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
- *  set this bit high to enable timer1 sync task receive
- */
-#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
-#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
-#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
-/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
- *  set this bit high to enable timer2 sync task receive
- */
-#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
-#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
-#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
-/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
- *  set this bit high to enable timer0 period update task receive
- */
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
-/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
- *  set this bit high to enable timer1 period update task receive
- */
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
-/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
- *  set this bit high to enable timer2 period update task receive
- */
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
-/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
- *  set this bit high to enable one shot trip0 task receive
- */
-#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
-#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
-#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ0_OST_EN_S  13
-/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
- *  set this bit high to enable one shot trip1 task receive
- */
-#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
-#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
-#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ1_OST_EN_S  14
-/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
- *  set this bit high to enable one shot trip2 task receive
- */
-#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
-#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
-#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ2_OST_EN_S  15
-/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
- *  set this bit high to enable one shot trip0 clear task receive
- */
-#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
-#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
-#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR0_OST_EN_S  16
-/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
- *  set this bit high to enable one shot trip1 clear task receive
- */
-#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
-#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
-#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR1_OST_EN_S  17
-/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
- *  set this bit high to enable one shot trip2 clear task receive
- */
-#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
-#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
-#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR2_OST_EN_S  18
-/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
- *  set this bit high to enable capture0 task receive
- */
-#define MCPWM_TASK_CAP0_EN    (BIT(19))
-#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
-#define MCPWM_TASK_CAP0_EN_V  0x00000001U
-#define MCPWM_TASK_CAP0_EN_S  19
-/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
- *  set this bit high to enable capture1 task receive
- */
-#define MCPWM_TASK_CAP1_EN    (BIT(20))
-#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
-#define MCPWM_TASK_CAP1_EN_V  0x00000001U
-#define MCPWM_TASK_CAP1_EN_S  20
-/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
- *  set this bit high to enable capture2 task receive
- */
-#define MCPWM_TASK_CAP2_EN    (BIT(21))
-#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
-#define MCPWM_TASK_CAP2_EN_V  0x00000001U
-#define MCPWM_TASK_CAP2_EN_S  21
-
-/** MCPWM_CLK_REG register
- *  MCPWM APB configuration register
- */
-#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x128)
-/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Force clock on for this register file
- */
-#define MCPWM_CLK_EN    (BIT(0))
-#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
-#define MCPWM_CLK_EN_V  0x00000001U
-#define MCPWM_CLK_EN_S  0
-
-/** MCPWM_VERSION_REG register
- *  Version register.
- */
-#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x12c)
-/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35656256;
- *  Version of this register file
- */
-#define MCPWM_DATE    0x0FFFFFFFU
-#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
-#define MCPWM_DATE_V  0x0FFFFFFFU
-#define MCPWM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/mcpwm_struct.h b/components/soc/esp32c6/include/soc/mcpwm_struct.h
deleted file mode 100644
index 1a91a623f6b..00000000000
--- a/components/soc/esp32c6/include/soc/mcpwm_struct.h
+++ /dev/null
@@ -1,1694 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Prescaler configuration */
-/** Type of clk_cfg register
- *  PWM clock prescaler register.
- */
-typedef union {
-    struct {
-        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
-         */
-        uint32_t clk_prescale:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_clk_cfg_reg_t;
-
-
-/** Group: MCPWM Timer Configuration and status */
-/** Type of timer_cfg0 register
- *  PWM timer period and update method configuration register.
- */
-typedef union {
-    struct {
-        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1)
-         */
-        uint32_t timer_prescale:8;
-        /** timer_period : R/W; bitpos: [23:8]; default: 255;
-         *  period shadow register of PWM timer
-         */
-        uint32_t timer_period:16;
-        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
-         *  Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2:
-         *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
-         */
-        uint32_t timer_period_upmethod:2;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg0_reg_t;
-
-/** Type of timer_cfg1 register
- *  PWM timer0 working mode and start/stop control configuration register.
- */
-typedef union {
-    struct {
-        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
-         *  PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1:
-         *  if timer0 starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer
-         *  starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP
-         *  here and below means the event that happens when the timer equals to period
-         */
-        uint32_t timer_start:3;
-        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
-         *  PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
-         *  mode
-         */
-        uint32_t timer_mod:2;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg1_reg_t;
-
-/** Type of timer_sync register
- *  PWM timer sync function configuration register.
- */
-typedef union {
-    struct {
-        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
-         *  When set, timer reloading with phase on sync input event is enabled.
-         */
-        uint32_t timer_synci_en:1;
-        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
-         *  Toggling this bit will trigger a software sync.
-         */
-        uint32_t timer_sync_sw:1;
-        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
-         *  PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
-         *  generate when toggling the reg_timer0_sync_sw bit
-         */
-        uint32_t timer_synco_sel:2;
-        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
-         *  phase for timer reload on sync event
-         */
-        uint32_t timer_phase:16;
-        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
-         *  Configure the PWM timer0's direction when timer mode is up-down mode:
-         *  0-increase,1-decrease
-         */
-        uint32_t timer_phase_direction:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} mcpwm_timer_sync_reg_t;
-
-/** Type of timer_status register
- *  PWM timer status register.
- */
-typedef union {
-    struct {
-        /** timer_value : RO; bitpos: [15:0]; default: 0;
-         *  current PWM timer counter value
-         */
-        uint32_t timer_value:16;
-        /** timer_direction : RO; bitpos: [16]; default: 0;
-         *  current PWM timer counter direction, 0: increment 1: decrement
-         */
-        uint32_t timer_direction:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} mcpwm_timer_status_reg_t;
-
-
-/** Group: Common configuration for MCPWM timers */
-/** Type of timer_synci_cfg register
- *  Synchronization input selection for three PWM timers.
- */
-typedef union {
-    struct {
-        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
-         *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer0_syncisel:3;
-        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
-         *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer1_syncisel:3;
-        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
-         *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer2_syncisel:3;
-        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
-         *  invert SYNC0 from GPIO matrix
-         */
-        uint32_t external_synci0_invert:1;
-        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
-         *  invert SYNC1 from GPIO matrix
-         */
-        uint32_t external_synci1_invert:1;
-        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
-         *  invert SYNC2 from GPIO matrix
-         */
-        uint32_t external_synci2_invert:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} mcpwm_timer_synci_cfg_reg_t;
-
-/** Type of operator_timersel register
- *  Select specific timer for PWM operators.
- */
-typedef union {
-    struct {
-        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
-         *  Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator0_timersel:2;
-        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
-         *  Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator1_timersel:2;
-        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
-         *  Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator2_timersel:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_operator_timersel_reg_t;
-
-
-/** Group: MCPWM Operator Configuration and Status */
-/** Type of gen_stmp_cfg register
- *  Transfer status and update method for time stamp registers A and B
- */
-typedef union {
-    struct {
-        /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for PWM generator time stamp A's active register. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
-         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
-         */
-        uint32_t cmpr_a_upmethod:4;
-        /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Update method for PWM generator time stamp B's active register. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
-         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
-         */
-        uint32_t cmpr_b_upmethod:4;
-        /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
-         *  Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is
-         *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
-         *  has been updated with shadow register latest value
-         */
-        uint32_t cmpr_a_shdw_full:1;
-        /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
-         *  Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is
-         *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
-         *  has been updated with shadow register latest value
-         */
-        uint32_t cmpr_b_shdw_full:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_gen_stmp_cfg_reg_t;
-
-/** Type of gen_tstmp register
- *  Shadow register for register B.
- */
-typedef union {
-    struct {
-        /** cmpr : R/W; bitpos: [15:0]; default: 0;
-         *  PWM generator time stamp's shadow register
-         */
-        uint32_t cmpr:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_tstmp_reg_t;
-
-/** Type of gen_cfg0 register
- *  Fault event T0 and T1 handling
- */
-typedef union {
-    struct {
-        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for PWM generator's active register of configuration. When all bits
-         *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
-         *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
-         */
-        uint32_t gen_cfg_upmethod:4;
-        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
-         *  Source selection for PWM generator event_t0, take effect immediately, 0:
-         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
-         */
-        uint32_t gen_t0_sel:3;
-        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
-         *  Source selection for PWM generator event_t1, take effect immediately, 0:
-         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
-         */
-        uint32_t gen_t1_sel:3;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_gen_cfg0_reg_t;
-
-/** Type of gen_force register
- *  Permissives to force PWM0A and PWM0B outputs by software
- */
-typedef union {
-    struct {
-        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
-         *  Updating method for continuous software force of PWM generator. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
-         *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
-         *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
-         *  generated when the timer's value equals to that of register A/B.)
-         */
-        uint32_t gen_cntuforce_upmethod:6;
-        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
-         *  Continuous software force mode for PWMnA. 0: disabled, 1: low, 2: high, 3: disabled
-         */
-        uint32_t gen_a_cntuforce_mode:2;
-        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
-         *  Continuous software force mode for PWMnB. 0: disabled, 1: low, 2: high, 3: disabled
-         */
-        uint32_t gen_b_cntuforce_mode:2;
-        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
-         *  Trigger of non-continuous immediate software-force event for PWMnA, a toggle will
-         *  trigger a force event.
-         */
-        uint32_t gen_a_nciforce:1;
-        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
-         *  non-continuous immediate software force mode for PWMnA, 0: disabled, 1: low, 2:
-         *  high, 3: disabled
-         */
-        uint32_t gen_a_nciforce_mode:2;
-        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
-         *  Trigger of non-continuous immediate software-force event for PWMnB, a toggle will
-         *  trigger a force event.
-         */
-        uint32_t gen_b_nciforce:1;
-        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
-         *  non-continuous immediate software force mode for PWMnB, 0: disabled, 1: low, 2:
-         *  high, 3: disabled
-         */
-        uint32_t gen_b_nciforce_mode:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_force_reg_t;
-
-/** Type of gen register
- *  Actions triggered by events on PWM0B
- */
-typedef union {
-    struct {
-        /** gen_utez : R/W; bitpos: [1:0]; default: 0;
-         *  Action on PWMnA/B triggered by event TEZ when timer increasing
-         */
-        uint32_t gen_utez:2;
-        /** gen_utep : R/W; bitpos: [3:2]; default: 0;
-         *  Action on PWMnA/B triggered by event TEP when timer increasing
-         */
-        uint32_t gen_utep:2;
-        /** gen_utea : R/W; bitpos: [5:4]; default: 0;
-         *  Action on PWMnA/B triggered by event TEA when timer increasing
-         */
-        uint32_t gen_utea:2;
-        /** gen_uteb : R/W; bitpos: [7:6]; default: 0;
-         *  Action on PWMnA/B triggered by event TEB when timer increasing
-         */
-        uint32_t gen_uteb:2;
-        /** gen_ut0 : R/W; bitpos: [9:8]; default: 0;
-         *  Action on PWMnA/B triggered by event_t0 when timer increasing
-         */
-        uint32_t gen_ut0:2;
-        /** gen_ut1 : R/W; bitpos: [11:10]; default: 0;
-         *  Action on PWMnA/B triggered by event_t1 when timer increasing
-         */
-        uint32_t gen_ut1:2;
-        /** gen_dtez : R/W; bitpos: [13:12]; default: 0;
-         *  Action on PWMnA/B triggered by event TEZ when timer decreasing
-         */
-        uint32_t gen_dtez:2;
-        /** gen_dtep : R/W; bitpos: [15:14]; default: 0;
-         *  Action on PWMnA/B triggered by event TEP when timer decreasing
-         */
-        uint32_t gen_dtep:2;
-        /** gen_dtea : R/W; bitpos: [17:16]; default: 0;
-         *  Action on PWMnA/B triggered by event TEA when timer decreasing
-         */
-        uint32_t gen_dtea:2;
-        /** gen_dteb : R/W; bitpos: [19:18]; default: 0;
-         *  Action on PWMnA/B triggered by event TEB when timer decreasing
-         */
-        uint32_t gen_dteb:2;
-        /** gen_dt0 : R/W; bitpos: [21:20]; default: 0;
-         *  Action on PWMnA/B triggered by event_t0 when timer decreasing
-         */
-        uint32_t gen_dt0:2;
-        /** gen_dt1 : R/W; bitpos: [23:22]; default: 0;
-         *  Action on PWMnA/B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_dt1:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_gen_reg_t;
-
-/** Type of dt_cfg register
- *  dead time type selection and configuration
- */
-typedef union {
-    struct {
-        /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
-         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
-         *  bit3 is set to 1: disable the update
-         */
-        uint32_t db_fed_upmethod:4;
-        /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
-         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
-         *  bit3 is set to 1: disable the update
-         */
-        uint32_t db_red_upmethod:4;
-        /** db_deb_mode : R/W; bitpos: [8]; default: 0;
-         *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
-         *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
-         */
-        uint32_t db_deb_mode:1;
-        /** db_a_outswap : R/W; bitpos: [9]; default: 0;
-         *  S6 in table
-         */
-        uint32_t db_a_outswap:1;
-        /** db_b_outswap : R/W; bitpos: [10]; default: 0;
-         *  S7 in table
-         */
-        uint32_t db_b_outswap:1;
-        /** db_red_insel : R/W; bitpos: [11]; default: 0;
-         *  S4 in table
-         */
-        uint32_t db_red_insel:1;
-        /** db_fed_insel : R/W; bitpos: [12]; default: 0;
-         *  S5 in table
-         */
-        uint32_t db_fed_insel:1;
-        /** db_red_outinvert : R/W; bitpos: [13]; default: 0;
-         *  S2 in table
-         */
-        uint32_t db_red_outinvert:1;
-        /** db_fed_outinvert : R/W; bitpos: [14]; default: 0;
-         *  S3 in table
-         */
-        uint32_t db_fed_outinvert:1;
-        /** db_a_outbypass : R/W; bitpos: [15]; default: 1;
-         *  S1 in table
-         */
-        uint32_t db_a_outbypass:1;
-        /** db_b_outbypass : R/W; bitpos: [16]; default: 1;
-         *  S0 in table
-         */
-        uint32_t db_b_outbypass:1;
-        /** db_clk_sel : R/W; bitpos: [17]; default: 0;
-         *  Dead time generator n clock selection. 0: PWM_clk, 1: PT_clk
-         */
-        uint32_t db_clk_sel:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} mcpwm_dt_cfg_reg_t;
-
-/** Type of dt_fed_cfg register
- *  Shadow register for falling edge delay (FED).
- */
-typedef union {
-    struct {
-        /** db_fed : R/W; bitpos: [15:0]; default: 0;
-         *  Shadow register for FED
-         */
-        uint32_t db_fed:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dt_fed_cfg_reg_t;
-
-/** Type of dt_red_cfg register
- *  Shadow register for rising edge delay (RED).
- */
-typedef union {
-    struct {
-        /** db_red : R/W; bitpos: [15:0]; default: 0;
-         *  Shadow register for RED
-         */
-        uint32_t db_red:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dt_red_cfg_reg_t;
-
-/** Type of carrier_cfg register
- *  Carrier enable and configuratoin
- */
-typedef union {
-    struct {
-        /** chopper_en : R/W; bitpos: [0]; default: 0;
-         *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
-         */
-        uint32_t chopper_en:1;
-        /** chopper_prescale : R/W; bitpos: [4:1]; default: 0;
-         *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
-         *  (PWM_CARRIER0_PRESCALE + 1)
-         */
-        uint32_t chopper_prescale:4;
-        /** chopper_duty : R/W; bitpos: [7:5]; default: 0;
-         *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
-         */
-        uint32_t chopper_duty:3;
-        /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0;
-         *  width of the first pulse in number of periods of the carrier
-         */
-        uint32_t chopper_oshtwth:4;
-        /** chopper_out_invert : R/W; bitpos: [12]; default: 0;
-         *  when set, invert the output of PWM0A and PWM0B for this submodule
-         */
-        uint32_t chopper_out_invert:1;
-        /** chopper_in_invert : R/W; bitpos: [13]; default: 0;
-         *  when set, invert the input of PWM0A and PWM0B for this submodule
-         */
-        uint32_t chopper_in_invert:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} mcpwm_carrier_cfg_reg_t;
-
-/** Type of fh_cfg0 register
- *  Actions on PWM0A and PWM0B trip events
- */
-typedef union {
-    struct {
-        /** tz_sw_cbc : R/W; bitpos: [0]; default: 0;
-         *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_sw_cbc:1;
-        /** tz_f2_cbc : R/W; bitpos: [1]; default: 0;
-         *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f2_cbc:1;
-        /** tz_f1_cbc : R/W; bitpos: [2]; default: 0;
-         *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f1_cbc:1;
-        /** tz_f0_cbc : R/W; bitpos: [3]; default: 0;
-         *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f0_cbc:1;
-        /** tz_sw_ost : R/W; bitpos: [4]; default: 0;
-         *  Enable register for software force one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_sw_ost:1;
-        /** tz_f2_ost : R/W; bitpos: [5]; default: 0;
-         *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f2_ost:1;
-        /** tz_f1_ost : R/W; bitpos: [6]; default: 0;
-         *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f1_ost:1;
-        /** tz_f0_ost : R/W; bitpos: [7]; default: 0;
-         *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f0_ost:1;
-        /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
-         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_a_cbc_d:2;
-        /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
-         *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_a_cbc_u:2;
-        /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0;
-         *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_a_ost_d:2;
-        /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0;
-         *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_a_ost_u:2;
-        /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
-         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_b_cbc_d:2;
-        /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
-         *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_b_cbc_u:2;
-        /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0;
-         *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_b_ost_d:2;
-        /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0;
-         *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_b_ost_u:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg0_reg_t;
-
-/** Type of fh_cfg1 register
- *  Software triggers for fault handler actions
- */
-typedef union {
-    struct {
-        /** tz_clr_ost : R/W; bitpos: [0]; default: 0;
-         *  a rising edge will clear on going one-shot mode action
-         */
-        uint32_t tz_clr_ost:1;
-        /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0;
-         *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
-         *  when bit1 is set to 1:TEP
-         */
-        uint32_t tz_cbcpulse:2;
-        /** tz_force_cbc : R/W; bitpos: [3]; default: 0;
-         *  a toggle trigger a cycle-by-cycle mode action
-         */
-        uint32_t tz_force_cbc:1;
-        /** tz_force_ost : R/W; bitpos: [4]; default: 0;
-         *  a toggle (software negate its value) triggers a one-shot mode action
-         */
-        uint32_t tz_force_ost:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg1_reg_t;
-
-/** Type of fh_status register
- *  Status of fault events.
- */
-typedef union {
-    struct {
-        /** tz_cbc_on : RO; bitpos: [0]; default: 0;
-         *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
-         */
-        uint32_t tz_cbc_on:1;
-        /** tz_ost_on : RO; bitpos: [1]; default: 0;
-         *  Set and reset by hardware. If set, an one-shot mode action is on going
-         */
-        uint32_t tz_ost_on:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} mcpwm_fh_status_reg_t;
-
-
-/** Group: Fault Detection Configuration and Status */
-/** Type of fault_detect register
- *  Fault detection configuration and status
- */
-typedef union {
-    struct {
-        /** f0_en : R/W; bitpos: [0]; default: 0;
-         *  When set, event_f0 generation is enabled
-         */
-        uint32_t f0_en:1;
-        /** f1_en : R/W; bitpos: [1]; default: 0;
-         *  When set, event_f1 generation is enabled
-         */
-        uint32_t f1_en:1;
-        /** f2_en : R/W; bitpos: [2]; default: 0;
-         *  When set, event_f2 generation is enabled
-         */
-        uint32_t f2_en:1;
-        /** f0_pole : R/W; bitpos: [3]; default: 0;
-         *  Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
-         *  level high
-         */
-        uint32_t f0_pole:1;
-        /** f1_pole : R/W; bitpos: [4]; default: 0;
-         *  Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
-         *  level high
-         */
-        uint32_t f1_pole:1;
-        /** f2_pole : R/W; bitpos: [5]; default: 0;
-         *  Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
-         *  level high
-         */
-        uint32_t f2_pole:1;
-        /** event_f0 : RO; bitpos: [6]; default: 0;
-         *  Set and reset by hardware. If set, event_f0 is on going
-         */
-        uint32_t event_f0:1;
-        /** event_f1 : RO; bitpos: [7]; default: 0;
-         *  Set and reset by hardware. If set, event_f1 is on going
-         */
-        uint32_t event_f1:1;
-        /** event_f2 : RO; bitpos: [8]; default: 0;
-         *  Set and reset by hardware. If set, event_f2 is on going
-         */
-        uint32_t event_f2:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} mcpwm_fault_detect_reg_t;
-
-
-/** Group: Capture Configuration and Status */
-/** Type of cap_timer_cfg register
- *  Configure capture timer
- */
-typedef union {
-    struct {
-        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
-         *  When set, capture timer incrementing under APB_clk is enabled.
-         */
-        uint32_t cap_timer_en:1;
-        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
-         *  When set, capture timer sync is enabled.
-         */
-        uint32_t cap_synci_en:1;
-        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
-         *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
-         *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
-         *  6: SYNC2 from GPIO matrix
-         */
-        uint32_t cap_synci_sel:3;
-        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
-         *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
-         *  timer is loaded with value in phase register.
-         */
-        uint32_t cap_sync_sw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_cfg_reg_t;
-
-/** Type of cap_timer_phase register
- *  Phase for capture timer sync
- */
-typedef union {
-    struct {
-        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
-         *  Phase value for capture timer sync operation.
-         */
-        uint32_t cap_phase:32;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_phase_reg_t;
-
-/** Type of cap_chn_cfg register
- *  Capture channel n configuration and enable
- */
-typedef union {
-    struct {
-        /** capn_en : R/W; bitpos: [0]; default: 0;
-         *  When set, capture on channel 0 is enabled
-         */
-        uint32_t capn_en:1;
-        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
-         *  Edge of capture on channel n after prescaling. When bit0 is set to 1: enable
-         *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
-         *  edge.
-         */
-        uint32_t capn_mode:2;
-        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
-         *  1
-         */
-        uint32_t capn_prescale:8;
-        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
-         *  when set, CAPn form GPIO matrix is inverted before prescale
-         */
-        uint32_t capn_in_invert:1;
-        /** capn_sw : WT; bitpos: [12]; default: 0;
-         *  Write 1 will trigger a software forced capture on channel n
-         */
-        uint32_t capn_sw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_cfg_reg_t;
-
-/** Type of cap_chn register
- *  chn capture value status register
- */
-typedef union {
-    struct {
-        /** capn_value : RO; bitpos: [31:0]; default: 0;
-         *  Value of last capture on channel n
-         */
-        uint32_t capn_value:32;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_reg_t;
-
-/** Type of cap_status register
- *  Edge of last capture trigger
- */
-typedef union {
-    struct {
-        /** cap0_edge : RO; bitpos: [0]; default: 0;
-         *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
-         */
-        uint32_t cap0_edge:1;
-        /** cap1_edge : RO; bitpos: [1]; default: 0;
-         *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
-         */
-        uint32_t cap1_edge:1;
-        /** cap2_edge : RO; bitpos: [2]; default: 0;
-         *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
-         */
-        uint32_t cap2_edge:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} mcpwm_cap_status_reg_t;
-
-
-/** Group: Enable update of active registers */
-/** Type of update_cfg register
- *  Enable update.
- */
-typedef union {
-    struct {
-        /** global_up_en : R/W; bitpos: [0]; default: 1;
-         *  The global enable of update of all active registers in MCPWM module
-         */
-        uint32_t global_up_en:1;
-        /** global_force_up : R/W; bitpos: [1]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of all active
-         *  registers in MCPWM module
-         */
-        uint32_t global_force_up:1;
-        /** op0_up_en : R/W; bitpos: [2]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
-         *  are enabled
-         */
-        uint32_t op0_up_en:1;
-        /** op0_force_up : R/W; bitpos: [3]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 0
-         */
-        uint32_t op0_force_up:1;
-        /** op1_up_en : R/W; bitpos: [4]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
-         *  are enabled
-         */
-        uint32_t op1_up_en:1;
-        /** op1_force_up : R/W; bitpos: [5]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 1
-         */
-        uint32_t op1_force_up:1;
-        /** op2_up_en : R/W; bitpos: [6]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
-         *  are enabled
-         */
-        uint32_t op2_up_en:1;
-        /** op2_force_up : R/W; bitpos: [7]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 2
-         */
-        uint32_t op2_force_up:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_update_cfg_reg_t;
-
-
-/** Group: Manage Interrupts */
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_ena:1;
-        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_ena:1;
-        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_ena:1;
-        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_ena:1;
-        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_ena:1;
-        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_ena:1;
-        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_ena:1;
-        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_ena:1;
-        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_ena:1;
-        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_ena:1;
-        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_ena:1;
-        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_ena:1;
-        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f0 ends.
-         */
-        uint32_t fault0_clr_int_ena:1;
-        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f1 ends.
-         */
-        uint32_t fault1_clr_int_ena:1;
-        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f2 ends.
-         */
-        uint32_t fault2_clr_int_ena:1;
-        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_ena:1;
-        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_ena:1;
-        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_ena:1;
-        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_ena:1;
-        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_ena:1;
-        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_ena:1;
-        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t tz0_cbc_int_ena:1;
-        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t tz1_cbc_int_ena:1;
-        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t tz2_cbc_int_ena:1;
-        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_ena:1;
-        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_ena:1;
-        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_ena:1;
-        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_ena:1;
-        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_ena:1;
-        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_ena:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_raw:1;
-        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_raw:1;
-        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_raw:1;
-        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_raw:1;
-        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_raw:1;
-        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_raw:1;
-        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_raw:1;
-        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_raw:1;
-        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_raw:1;
-        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_raw:1;
-        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_raw:1;
-        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_raw:1;
-        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f0 ends.
-         */
-        uint32_t fault0_clr_int_raw:1;
-        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f1 ends.
-         */
-        uint32_t fault1_clr_int_raw:1;
-        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f2 ends.
-         */
-        uint32_t fault2_clr_int_raw:1;
-        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_raw:1;
-        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_raw:1;
-        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_raw:1;
-        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_raw:1;
-        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_raw:1;
-        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_raw:1;
-        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_cbc_int_raw:1;
-        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_cbc_int_raw:1;
-        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_cbc_int_raw:1;
-        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_raw:1;
-        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_raw:1;
-        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_raw:1;
-        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_raw:1;
-        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_raw:1;
-        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_raw:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_st:1;
-        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_st:1;
-        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_st:1;
-        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_st:1;
-        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_st:1;
-        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_st:1;
-        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_st:1;
-        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_st:1;
-        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_st:1;
-        /** fault0_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_st:1;
-        /** fault1_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_st:1;
-        /** fault2_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_st:1;
-        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f0 ends.
-         */
-        uint32_t fault0_clr_int_st:1;
-        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f1 ends.
-         */
-        uint32_t fault1_clr_int_st:1;
-        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f2 ends.
-         */
-        uint32_t fault2_clr_int_st:1;
-        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_st:1;
-        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_st:1;
-        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_st:1;
-        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_st:1;
-        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_st:1;
-        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_st:1;
-        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM0.
-         */
-        uint32_t tz0_cbc_int_st:1;
-        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM1.
-         */
-        uint32_t tz1_cbc_int_st:1;
-        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM2.
-         */
-        uint32_t tz2_cbc_int_st:1;
-        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_st:1;
-        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_st:1;
-        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_st:1;
-        /** cap0_int_st : RO; bitpos: [27]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_st:1;
-        /** cap1_int_st : RO; bitpos: [28]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_st:1;
-        /** cap2_int_st : RO; bitpos: [29]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_st:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_st_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_clr:1;
-        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_clr:1;
-        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_clr:1;
-        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_clr:1;
-        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_clr:1;
-        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_clr:1;
-        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_clr:1;
-        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_clr:1;
-        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_clr:1;
-        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_clr:1;
-        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_clr:1;
-        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_clr:1;
-        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f0 ends.
-         */
-        uint32_t fault0_clr_int_clr:1;
-        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f1 ends.
-         */
-        uint32_t fault1_clr_int_clr:1;
-        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f2 ends.
-         */
-        uint32_t fault2_clr_int_clr:1;
-        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_clr:1;
-        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_clr:1;
-        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_clr:1;
-        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_clr:1;
-        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_clr:1;
-        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_clr:1;
-        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_cbc_int_clr:1;
-        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_cbc_int_clr:1;
-        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_cbc_int_clr:1;
-        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_clr:1;
-        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_clr:1;
-        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_clr:1;
-        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_clr:1;
-        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_clr:1;
-        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_clr:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_clr_reg_t;
-
-
-/** Group: MCPWM event enable register */
-/** Type of evt_en register
- *  MCPWM event enable register
- */
-typedef union {
-    struct {
-        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
-         *  set this bit high to enable timer0 stop event generate
-         */
-        uint32_t evt_timer0_stop_en:1;
-        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
-         *  set this bit high to enable timer1 stop event generate
-         */
-        uint32_t evt_timer1_stop_en:1;
-        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
-         *  set this bit high to enable timer2 stop event generate
-         */
-        uint32_t evt_timer2_stop_en:1;
-        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
-         *  set this bit high to enable timer0 equal zero event generate
-         */
-        uint32_t evt_timer0_tez_en:1;
-        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
-         *  set this bit high to enable timer1 equal zero event generate
-         */
-        uint32_t evt_timer1_tez_en:1;
-        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
-         *  set this bit high to enable timer2 equal zero event generate
-         */
-        uint32_t evt_timer2_tez_en:1;
-        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
-         *  set this bit high to enable timer0 equal period event generate
-         */
-        uint32_t evt_timer0_tep_en:1;
-        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
-         *  set this bit high to enable timer1 equal period event generate
-         */
-        uint32_t evt_timer1_tep_en:1;
-        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
-         *  set this bit high to enable timer2 equal period event generate
-         */
-        uint32_t evt_timer2_tep_en:1;
-        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
-         *  set this bit high to enable PWM generator0 timer equal a event generate
-         */
-        uint32_t evt_op0_tea_en:1;
-        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
-         *  set this bit high to enable PWM generator1 timer equal a event generate
-         */
-        uint32_t evt_op1_tea_en:1;
-        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
-         *  set this bit high to enable PWM generator2 timer equal a event generate
-         */
-        uint32_t evt_op2_tea_en:1;
-        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
-         *  set this bit high to enable PWM generator0 timer equal b event generate
-         */
-        uint32_t evt_op0_teb_en:1;
-        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
-         *  set this bit high to enable PWM generator1 timer equal b event generate
-         */
-        uint32_t evt_op1_teb_en:1;
-        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
-         *  set this bit high to enable PWM generator2 timer equal b event generate
-         */
-        uint32_t evt_op2_teb_en:1;
-        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
-         *  set this bit high to enable fault0 event generate
-         */
-        uint32_t evt_f0_en:1;
-        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
-         *  set this bit high to enable fault1 event generate
-         */
-        uint32_t evt_f1_en:1;
-        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
-         *  set this bit high to enable fault2 event generate
-         */
-        uint32_t evt_f2_en:1;
-        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
-         *  set this bit high to enable fault0 clear event generate
-         */
-        uint32_t evt_f0_clr_en:1;
-        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
-         *  set this bit high to enable fault1 clear event generate
-         */
-        uint32_t evt_f1_clr_en:1;
-        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
-         *  set this bit high to enable fault2 clear event generate
-         */
-        uint32_t evt_f2_clr_en:1;
-        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
-         *  set this bit high to enable cycle by cycle trip0 event generate
-         */
-        uint32_t evt_tz0_cbc_en:1;
-        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
-         *  set this bit high to enable cycle by cycle trip1 event generate
-         */
-        uint32_t evt_tz1_cbc_en:1;
-        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
-         *  set this bit high to enable cycle by cycle trip2 event generate
-         */
-        uint32_t evt_tz2_cbc_en:1;
-        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
-         *  set this bit high to enable one shot trip0 event generate
-         */
-        uint32_t evt_tz0_ost_en:1;
-        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
-         *  set this bit high to enable one shot trip1 event generate
-         */
-        uint32_t evt_tz1_ost_en:1;
-        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
-         *  set this bit high to enable one shot trip2 event generate
-         */
-        uint32_t evt_tz2_ost_en:1;
-        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
-         *  set this bit high to enable capture0 event generate
-         */
-        uint32_t evt_cap0_en:1;
-        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
-         *  set this bit high to enable capture1 event generate
-         */
-        uint32_t evt_cap1_en:1;
-        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
-         *  set this bit high to enable capture2 event generate
-         */
-        uint32_t evt_cap2_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_evt_en_reg_t;
-
-
-/** Group: MCPWM task enable register */
-/** Type of task_en register
- *  MCPWM task enable register
- */
-typedef union {
-    struct {
-        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
-         *  set this bit high to enable PWM generator0 timer stamp A's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr0_a_up_en:1;
-        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
-         *  set this bit high to enable PWM generator1 timer stamp A's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr1_a_up_en:1;
-        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
-         *  set this bit high to enable PWM generator2 timer stamp A's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr2_a_up_en:1;
-        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
-         *  set this bit high to enable PWM generator0 timer stamp B's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr0_b_up_en:1;
-        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
-         *  set this bit high to enable PWM generator1 timer stamp B's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr1_b_up_en:1;
-        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
-         *  set this bit high to enable PWM generator2 timer stamp B's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr2_b_up_en:1;
-        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
-         *  set this bit high to enable all PWM generate stop task receive
-         */
-        uint32_t task_gen_stop_en:1;
-        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
-         *  set this bit high to enable timer0 sync task receive
-         */
-        uint32_t task_timer0_sync_en:1;
-        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
-         *  set this bit high to enable timer1 sync task receive
-         */
-        uint32_t task_timer1_sync_en:1;
-        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
-         *  set this bit high to enable timer2 sync task receive
-         */
-        uint32_t task_timer2_sync_en:1;
-        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
-         *  set this bit high to enable timer0 period update task receive
-         */
-        uint32_t task_timer0_period_up_en:1;
-        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
-         *  set this bit high to enable timer1 period update task receive
-         */
-        uint32_t task_timer1_period_up_en:1;
-        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
-         *  set this bit high to enable timer2 period update task receive
-         */
-        uint32_t task_timer2_period_up_en:1;
-        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
-         *  set this bit high to enable one shot trip0 task receive
-         */
-        uint32_t task_tz0_ost_en:1;
-        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
-         *  set this bit high to enable one shot trip1 task receive
-         */
-        uint32_t task_tz1_ost_en:1;
-        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
-         *  set this bit high to enable one shot trip2 task receive
-         */
-        uint32_t task_tz2_ost_en:1;
-        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
-         *  set this bit high to enable one shot trip0 clear task receive
-         */
-        uint32_t task_clr0_ost_en:1;
-        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
-         *  set this bit high to enable one shot trip1 clear task receive
-         */
-        uint32_t task_clr1_ost_en:1;
-        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
-         *  set this bit high to enable one shot trip2 clear task receive
-         */
-        uint32_t task_clr2_ost_en:1;
-        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
-         *  set this bit high to enable capture0 task receive
-         */
-        uint32_t task_cap0_en:1;
-        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
-         *  set this bit high to enable capture1 task receive
-         */
-        uint32_t task_cap1_en:1;
-        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
-         *  set this bit high to enable capture2 task receive
-         */
-        uint32_t task_cap2_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} mcpwm_task_en_reg_t;
-
-
-/** Group: MCPWM APB configuration register */
-/** Type of clk register
- *  MCPWM APB configuration register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Force clock on for this register file
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mcpwm_clk_reg_t;
-
-
-/** Group: Version Register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35656256;
-         *  Version of this register file
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} mcpwm_version_reg_t;
-
-typedef struct {
-    mcpwm_timer_cfg0_reg_t timer_cfg0;
-    mcpwm_timer_cfg1_reg_t timer_cfg1;
-    mcpwm_timer_sync_reg_t timer_sync;
-    mcpwm_timer_status_reg_t timer_status;
-} mcpwm_timer_regs_t;
-
-typedef struct {
-    mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
-    mcpwm_gen_tstmp_reg_t timestamp[2];
-    mcpwm_gen_cfg0_reg_t gen_cfg0;
-    mcpwm_gen_force_reg_t gen_force;
-    mcpwm_gen_reg_t generator[2];
-    mcpwm_dt_cfg_reg_t dt_cfg;
-    mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
-    mcpwm_dt_red_cfg_reg_t dt_red_cfg;
-    mcpwm_carrier_cfg_reg_t carrier_cfg;
-    mcpwm_fh_cfg0_reg_t fh_cfg0;
-    mcpwm_fh_cfg1_reg_t fh_cfg1;
-    mcpwm_fh_status_reg_t fh_status;
-} mcpwm_operator_reg_t;
-
-typedef struct mcpwm_dev_t {
-    volatile mcpwm_clk_cfg_reg_t clk_cfg;
-    volatile mcpwm_timer_regs_t timer[3];
-    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
-    volatile mcpwm_operator_timersel_reg_t operator_timersel;
-    volatile mcpwm_operator_reg_t operators[3];
-    volatile mcpwm_fault_detect_reg_t fault_detect;
-    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
-    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
-    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
-    volatile mcpwm_cap_chn_reg_t cap_chn[3];
-    volatile mcpwm_cap_status_reg_t cap_status;
-    volatile mcpwm_update_cfg_reg_t update_cfg;
-    volatile mcpwm_int_ena_reg_t int_ena;
-    volatile mcpwm_int_raw_reg_t int_raw;
-    volatile mcpwm_int_st_reg_t int_st;
-    volatile mcpwm_int_clr_reg_t int_clr;
-    volatile mcpwm_evt_en_reg_t evt_en;
-    volatile mcpwm_task_en_reg_t task_en;
-    volatile mcpwm_clk_reg_t clk;
-    volatile mcpwm_version_reg_t version;
-} mcpwm_dev_t;
-
-extern mcpwm_dev_t MCPWM0;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mcpwm_dev_t) == 0x130, "Invalid size of mcpwm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/mem_monitor_reg.h b/components/soc/esp32c6/include/soc/mem_monitor_reg.h
deleted file mode 100644
index fccde61ad72..00000000000
--- a/components/soc/esp32c6/include/soc/mem_monitor_reg.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MEM_MONITOR_LOG_SETTING_REG register
- *  log config regsiter
- */
-#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
-/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
- *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.
- */
-#define MEM_MONITOR_LOG_ENA    0x00000007U
-#define MEM_MONITOR_LOG_ENA_M  (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
-#define MEM_MONITOR_LOG_ENA_V  0x00000007U
-#define MEM_MONITOR_LOG_ENA_S  0
-/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
- *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
- *  HALFWORD monitor, 4'b1000: BYTE monitor.
- */
-#define MEM_MONITOR_LOG_MODE    0x0000000FU
-#define MEM_MONITOR_LOG_MODE_M  (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
-#define MEM_MONITOR_LOG_MODE_V  0x0000000FU
-#define MEM_MONITOR_LOG_MODE_S  3
-/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
- *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
- */
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(7))
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
-
-/** MEM_MONITOR_LOG_CHECK_DATA_REG register
- *  check data regsiter
- */
-#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
-/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
- *  The special check data, when write this special data, it will trigger logging.
- */
-#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_CHECK_DATA_M  (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
-#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_CHECK_DATA_S  0
-
-/** MEM_MONITOR_LOG_DATA_MASK_REG register
- *  check data mask register
- */
-#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
-/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
- *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
- *  mask second byte, and so on.
- */
-#define MEM_MONITOR_LOG_DATA_MASK    0x0000000FU
-#define MEM_MONITOR_LOG_DATA_MASK_M  (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
-#define MEM_MONITOR_LOG_DATA_MASK_V  0x0000000FU
-#define MEM_MONITOR_LOG_DATA_MASK_S  0
-
-/** MEM_MONITOR_LOG_MIN_REG register
- *  log boundary regsiter
- */
-#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
-/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
- *  the min address of log range
- */
-#define MEM_MONITOR_LOG_MIN    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MIN_M  (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
-#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MIN_S  0
-
-/** MEM_MONITOR_LOG_MAX_REG register
- *  log boundary regsiter
- */
-#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
-/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
- *  the max address of log range
- */
-#define MEM_MONITOR_LOG_MAX    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MAX_M  (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
-#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MAX_S  0
-
-/** MEM_MONITOR_LOG_MEM_START_REG register
- *  log message store range register
- */
-#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
-/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
- *  the start address of writing logging message
- */
-#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_START_M  (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
-#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_START_S  0
-
-/** MEM_MONITOR_LOG_MEM_END_REG register
- *  log message store range register
- */
-#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
-/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
- *  the end address of writing logging message
- */
-#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_END_M  (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
-#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_END_S  0
-
-/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
- *  current writing address.
- */
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
-/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  means next writing address
- */
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
-
-/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
- *  writing address update
- */
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
-/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
- *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
- *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
- */
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
-
-/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
- *  full flag status register
- */
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
-/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
- *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
- */
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
-/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
- *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
- */
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
-
-/** MEM_MONITOR_CLOCK_GATE_REG register
- *  clock gate force on register
- */
-#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
-/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to force on the clk of mem_monitor register
- */
-#define MEM_MONITOR_CLK_EN    (BIT(0))
-#define MEM_MONITOR_CLK_EN_M  (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
-#define MEM_MONITOR_CLK_EN_V  0x00000001U
-#define MEM_MONITOR_CLK_EN_S  0
-
-/** MEM_MONITOR_DATE_REG register
- *  version register
- */
-#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
-/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096;
- *  version register
- */
-#define MEM_MONITOR_DATE    0x0FFFFFFFU
-#define MEM_MONITOR_DATE_M  (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
-#define MEM_MONITOR_DATE_V  0x0FFFFFFFU
-#define MEM_MONITOR_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/mem_monitor_struct.h b/components/soc/esp32c6/include/soc/mem_monitor_struct.h
deleted file mode 100644
index 6fd735edf54..00000000000
--- a/components/soc/esp32c6/include/soc/mem_monitor_struct.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configuration registers */
-/** Type of log_setting register
- *  log config regsiter
- */
-typedef union {
-    struct {
-        /** log_ena : R/W; bitpos: [2:0]; default: 0;
-         *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.
-         */
-        uint32_t log_ena:3;
-        /** log_mode : R/W; bitpos: [6:3]; default: 0;
-         *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
-         *  HALFWORD monitor, 4'b1000: BYTE monitor.
-         */
-        uint32_t log_mode:4;
-        /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
-         *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
-         */
-        uint32_t log_mem_loop_enable:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mem_monitor_log_setting_reg_t;
-
-/** Type of log_check_data register
- *  check data regsiter
- */
-typedef union {
-    struct {
-        /** log_check_data : R/W; bitpos: [31:0]; default: 0;
-         *  The special check data, when write this special data, it will trigger logging.
-         */
-        uint32_t log_check_data:32;
-    };
-    uint32_t val;
-} mem_monitor_log_check_data_reg_t;
-
-/** Type of log_data_mask register
- *  check data mask register
- */
-typedef union {
-    struct {
-        /** log_data_mask : R/W; bitpos: [3:0]; default: 0;
-         *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
-         *  mask second byte, and so on.
-         */
-        uint32_t log_data_mask:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} mem_monitor_log_data_mask_reg_t;
-
-/** Type of log_min register
- *  log boundary regsiter
- */
-typedef union {
-    struct {
-        /** log_min : R/W; bitpos: [31:0]; default: 0;
-         *  the min address of log range
-         */
-        uint32_t log_min:32;
-    };
-    uint32_t val;
-} mem_monitor_log_min_reg_t;
-
-/** Type of log_max register
- *  log boundary regsiter
- */
-typedef union {
-    struct {
-        /** log_max : R/W; bitpos: [31:0]; default: 0;
-         *  the max address of log range
-         */
-        uint32_t log_max:32;
-    };
-    uint32_t val;
-} mem_monitor_log_max_reg_t;
-
-/** Type of log_mem_start register
- *  log message store range register
- */
-typedef union {
-    struct {
-        /** log_mem_start : R/W; bitpos: [31:0]; default: 0;
-         *  the start address of writing logging message
-         */
-        uint32_t log_mem_start:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_start_reg_t;
-
-/** Type of log_mem_end register
- *  log message store range register
- */
-typedef union {
-    struct {
-        /** log_mem_end : R/W; bitpos: [31:0]; default: 0;
-         *  the end address of writing logging message
-         */
-        uint32_t log_mem_end:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_end_reg_t;
-
-/** Type of log_mem_current_addr register
- *  current writing address.
- */
-typedef union {
-    struct {
-        /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
-         *  means next writing address
-         */
-        uint32_t log_mem_current_addr:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_current_addr_reg_t;
-
-/** Type of log_mem_addr_update register
- *  writing address update
- */
-typedef union {
-    struct {
-        /** log_mem_addr_update : WT; bitpos: [0]; default: 0;
-         *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
-         *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
-         */
-        uint32_t log_mem_addr_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_addr_update_reg_t;
-
-/** Type of log_mem_full_flag register
- *  full flag status register
- */
-typedef union {
-    struct {
-        /** log_mem_full_flag : RO; bitpos: [0]; default: 0;
-         *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
-         */
-        uint32_t log_mem_full_flag:1;
-        /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
-         *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
-         */
-        uint32_t clr_log_mem_full_flag:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_full_flag_reg_t;
-
-
-/** Group: clk register */
-/** Type of clock_gate register
- *  clock gate force on register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to force on the clk of mem_monitor register
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mem_monitor_clock_gate_reg_t;
-
-
-/** Group: version register */
-/** Type of date register
- *  version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35660096;
-         *  version register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} mem_monitor_date_reg_t;
-
-
-typedef struct mem_monitor_dev_t {
-    volatile mem_monitor_log_setting_reg_t log_setting;
-    volatile mem_monitor_log_check_data_reg_t log_check_data;
-    volatile mem_monitor_log_data_mask_reg_t log_data_mask;
-    volatile mem_monitor_log_min_reg_t log_min;
-    volatile mem_monitor_log_max_reg_t log_max;
-    volatile mem_monitor_log_mem_start_reg_t log_mem_start;
-    volatile mem_monitor_log_mem_end_reg_t log_mem_end;
-    volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
-    volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
-    volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
-    volatile mem_monitor_clock_gate_reg_t clock_gate;
-    uint32_t reserved_02c[244];
-    volatile mem_monitor_date_reg_t date;
-} mem_monitor_dev_t;
-
-extern mem_monitor_dev_t MEM_MONITOR;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/parl_io_reg.h b/components/soc/esp32c6/include/soc/parl_io_reg.h
deleted file mode 100644
index 7377e9788b3..00000000000
--- a/components/soc/esp32c6/include/soc/parl_io_reg.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PARL_IO_RX_CFG0_REG register
- *  Parallel RX module configuration register0.
- */
-#define PARL_IO_RX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x0)
-/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [0]; default: 0;
- *  Write 0 to select eof generated manchnism by configured data byte length. Write 1
- *  to select eof generated manchnism by external enable signal.
- */
-#define PARL_IO_RX_EOF_GEN_SEL    (BIT(0))
-#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
-#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
-#define PARL_IO_RX_EOF_GEN_SEL_S  0
-/** PARL_IO_RX_START : R/W; bitpos: [1]; default: 0;
- *  Write 1 to start rx global data sampling.
- */
-#define PARL_IO_RX_START    (BIT(1))
-#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
-#define PARL_IO_RX_START_V  0x00000001U
-#define PARL_IO_RX_START_S  1
-/** PARL_IO_RX_DATA_BYTELEN : R/W; bitpos: [17:2]; default: 0;
- *  Configures rx receieved data byte length.
- */
-#define PARL_IO_RX_DATA_BYTELEN    0x0000FFFFU
-#define PARL_IO_RX_DATA_BYTELEN_M  (PARL_IO_RX_DATA_BYTELEN_V << PARL_IO_RX_DATA_BYTELEN_S)
-#define PARL_IO_RX_DATA_BYTELEN_V  0x0000FFFFU
-#define PARL_IO_RX_DATA_BYTELEN_S  2
-/** PARL_IO_RX_SW_EN : R/W; bitpos: [18]; default: 0;
- *  Write 1 to enable software data sampling.
- */
-#define PARL_IO_RX_SW_EN    (BIT(18))
-#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
-#define PARL_IO_RX_SW_EN_V  0x00000001U
-#define PARL_IO_RX_SW_EN_S  18
-/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [22:19]; default: 0;
- *  Pulse submode selection.
- *  0000: positive pulse start(data bit included) &&  positive pulse end(data bit
- *  included)
- *  0001: positive pulse start(data bit included) && positive pulse end (data bit
- *  excluded)
- *  0010: positive pulse start(data bit excluded) && positive pulse end (data bit
- *  included)
- *  0011: positive pulse start(data bit excluded) && positive pulse end (data bit
- *  excluded)
- *  0100: positive pulse start(data bit included) && length end
- *  0101: positive pulse start(data bit excluded) && length end
- *  0110: negative pulse start(data bit included) &&  negative pulse end(data bit
- *  included)
- *  0111: negative pulse start(data bit included) && negative pulse end (data bit
- *  excluded)
- *  1000: negative pulse start(data bit excluded) && negative pulse end (data bit
- *  included)
- *  1001: negative pulse start(data bit excluded) && negative pulse end (data bit
- *  excluded)
- *  1010: negative pulse start(data bit included) && length end
- *  1011: negative pulse start(data bit excluded) && length end
- */
-#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x0000000FU
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x0000000FU
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  19
-/** PARL_IO_RX_LEVEL_SUBMODE_SEL : R/W; bitpos: [23]; default: 0;
- *  Write 0 to sample data at high level of external enable signal. Write 1 to sample
- *  data at low level of external enable signal.
- */
-#define PARL_IO_RX_LEVEL_SUBMODE_SEL    (BIT(23))
-#define PARL_IO_RX_LEVEL_SUBMODE_SEL_M  (PARL_IO_RX_LEVEL_SUBMODE_SEL_V << PARL_IO_RX_LEVEL_SUBMODE_SEL_S)
-#define PARL_IO_RX_LEVEL_SUBMODE_SEL_V  0x00000001U
-#define PARL_IO_RX_LEVEL_SUBMODE_SEL_S  23
-/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [25:24]; default: 0;
- *  Rx data sampling mode selection.
- *  000: external level enable mode
- *  001: external pulse enable mode
- *  010: internal software enable mode
- */
-#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
-#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
-#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
-#define PARL_IO_RX_SMP_MODE_SEL_S  24
-/** PARL_IO_RX_CLK_EDGE_SEL : R/W; bitpos: [26]; default: 0;
- *  Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable
- *  sampling data on the falling edge of rx clock.
- */
-#define PARL_IO_RX_CLK_EDGE_SEL    (BIT(26))
-#define PARL_IO_RX_CLK_EDGE_SEL_M  (PARL_IO_RX_CLK_EDGE_SEL_V << PARL_IO_RX_CLK_EDGE_SEL_S)
-#define PARL_IO_RX_CLK_EDGE_SEL_V  0x00000001U
-#define PARL_IO_RX_CLK_EDGE_SEL_S  26
-/** PARL_IO_RX_BIT_PACK_ORDER : R/W; bitpos: [27]; default: 0;
- *  Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0
- *  to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.
- */
-#define PARL_IO_RX_BIT_PACK_ORDER    (BIT(27))
-#define PARL_IO_RX_BIT_PACK_ORDER_M  (PARL_IO_RX_BIT_PACK_ORDER_V << PARL_IO_RX_BIT_PACK_ORDER_S)
-#define PARL_IO_RX_BIT_PACK_ORDER_V  0x00000001U
-#define PARL_IO_RX_BIT_PACK_ORDER_S  27
-/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [30:28]; default: 0;
- *  Rx data bus width selection.
- *  100: bus width is 1 bit
- *  011: bus width is 2 bits
- *  010: bus width is 4 bits
- *  001: bus width is 8 bits
- *  000: bus width is 16 bits
- */
-#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
-#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
-#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
-#define PARL_IO_RX_BUS_WID_SEL_S  28
-/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
- *  Write 1 to enable soft reset of async fifo in rx module.
- */
-#define PARL_IO_RX_FIFO_SRST    (BIT(31))
-#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
-#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
-#define PARL_IO_RX_FIFO_SRST_S  31
-
-/** PARL_IO_RX_CFG1_REG register
- *  Parallel RX module configuration register1.
- */
-#define PARL_IO_RX_CFG1_REG (DR_REG_PARL_IO_BASE + 0x4)
-/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [2]; default: 0;
- *  Write 1 to update rx register configuration signals.
- */
-#define PARL_IO_RX_REG_UPDATE    (BIT(2))
-#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
-#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
-#define PARL_IO_RX_REG_UPDATE_S  2
-/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [3]; default: 1;
- *  Write 1 to enable timeout count to generate error eof.
- */
-#define PARL_IO_RX_TIMEOUT_EN    (BIT(3))
-#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
-#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
-#define PARL_IO_RX_TIMEOUT_EN_S  3
-/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [15:12]; default: 15;
- *  Configures rx external enable signal selection from 16 data lines.
- */
-#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
-#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
-#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
-#define PARL_IO_RX_EXT_EN_SEL_S  12
-/** PARL_IO_RX_TIMEOUT_THRESHOLD : R/W; bitpos: [31:16]; default: 4095;
- *  Configures rx threshold of timeout counter.
- */
-#define PARL_IO_RX_TIMEOUT_THRESHOLD    0x0000FFFFU
-#define PARL_IO_RX_TIMEOUT_THRESHOLD_M  (PARL_IO_RX_TIMEOUT_THRESHOLD_V << PARL_IO_RX_TIMEOUT_THRESHOLD_S)
-#define PARL_IO_RX_TIMEOUT_THRESHOLD_V  0x0000FFFFU
-#define PARL_IO_RX_TIMEOUT_THRESHOLD_S  16
-
-/** PARL_IO_TX_CFG0_REG register
- *  Parallel TX module configuration register0.
- */
-#define PARL_IO_TX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x8)
-/** PARL_IO_TX_BYTELEN : R/W; bitpos: [17:2]; default: 0;
- *  Configures tx sending data byte length.
- */
-#define PARL_IO_TX_BYTELEN    0x0000FFFFU
-#define PARL_IO_TX_BYTELEN_M  (PARL_IO_TX_BYTELEN_V << PARL_IO_TX_BYTELEN_S)
-#define PARL_IO_TX_BYTELEN_V  0x0000FFFFU
-#define PARL_IO_TX_BYTELEN_S  2
-/** PARL_IO_TX_GATING_EN : R/W; bitpos: [18]; default: 0;
- *  Write 1 to enable output tx clock gating.
- */
-#define PARL_IO_TX_GATING_EN    (BIT(18))
-#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
-#define PARL_IO_TX_GATING_EN_V  0x00000001U
-#define PARL_IO_TX_GATING_EN_S  18
-/** PARL_IO_TX_START : R/W; bitpos: [19]; default: 0;
- *  Write 1 to start tx global data output.
- */
-#define PARL_IO_TX_START    (BIT(19))
-#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
-#define PARL_IO_TX_START_V  0x00000001U
-#define PARL_IO_TX_START_S  19
-/** PARL_IO_TX_HW_VALID_EN : R/W; bitpos: [20]; default: 0;
- *  Write 1 to enable tx hardware data valid signal.
- */
-#define PARL_IO_TX_HW_VALID_EN    (BIT(20))
-#define PARL_IO_TX_HW_VALID_EN_M  (PARL_IO_TX_HW_VALID_EN_V << PARL_IO_TX_HW_VALID_EN_S)
-#define PARL_IO_TX_HW_VALID_EN_V  0x00000001U
-#define PARL_IO_TX_HW_VALID_EN_S  20
-/** PARL_IO_TX_SMP_EDGE_SEL : R/W; bitpos: [25]; default: 0;
- *  Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable
- *  sampling data on the falling edge of tx clock.
- */
-#define PARL_IO_TX_SMP_EDGE_SEL    (BIT(25))
-#define PARL_IO_TX_SMP_EDGE_SEL_M  (PARL_IO_TX_SMP_EDGE_SEL_V << PARL_IO_TX_SMP_EDGE_SEL_S)
-#define PARL_IO_TX_SMP_EDGE_SEL_V  0x00000001U
-#define PARL_IO_TX_SMP_EDGE_SEL_S  25
-/** PARL_IO_TX_BIT_UNPACK_ORDER : R/W; bitpos: [26]; default: 0;
- *  Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write
- *  0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits.
- */
-#define PARL_IO_TX_BIT_UNPACK_ORDER    (BIT(26))
-#define PARL_IO_TX_BIT_UNPACK_ORDER_M  (PARL_IO_TX_BIT_UNPACK_ORDER_V << PARL_IO_TX_BIT_UNPACK_ORDER_S)
-#define PARL_IO_TX_BIT_UNPACK_ORDER_V  0x00000001U
-#define PARL_IO_TX_BIT_UNPACK_ORDER_S  26
-/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [29:27]; default: 0;
- *  Tx data bus width selection.
- *  100: bus width is 1 bit
- *  011: bus width is 2 bits
- *  010: bus width is 4 bits
- *  001: bus width is 8 bits
- *  000: bus width is 16 bits
- */
-#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
-#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
-#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
-#define PARL_IO_TX_BUS_WID_SEL_S  27
-/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
- *  Write 1 to enable soft reset of async fifo in tx module.
- */
-#define PARL_IO_TX_FIFO_SRST    (BIT(30))
-#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
-#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
-#define PARL_IO_TX_FIFO_SRST_S  30
-
-/** PARL_IO_TX_CFG1_REG register
- *  Parallel TX module configuration register1.
- */
-#define PARL_IO_TX_CFG1_REG (DR_REG_PARL_IO_BASE + 0xc)
-/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [31:16]; default: 0;
- *  Configures data value on tx bus when IDLE state.
- */
-#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
-#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
-#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
-#define PARL_IO_TX_IDLE_VALUE_S  16
-
-/** PARL_IO_ST_REG register
- *  Parallel IO module status register0.
- */
-#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x10)
-/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
- *  Represents the status that tx is ready.
- */
-#define PARL_IO_TX_READY    (BIT(31))
-#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
-#define PARL_IO_TX_READY_V  0x00000001U
-#define PARL_IO_TX_READY_S  31
-
-/** PARL_IO_INT_ENA_REG register
- *  Parallel IO interrupt enable singal configuration register.
- */
-#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x14)
-/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable TX_FIFO_REMPTY_INTR.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
-/** PARL_IO_RX_FIFO_WFULL_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable RX_FIFO_WFULL_INTR.
- */
-#define PARL_IO_RX_FIFO_WFULL_INT_ENA    (BIT(1))
-#define PARL_IO_RX_FIFO_WFULL_INT_ENA_M  (PARL_IO_RX_FIFO_WFULL_INT_ENA_V << PARL_IO_RX_FIFO_WFULL_INT_ENA_S)
-#define PARL_IO_RX_FIFO_WFULL_INT_ENA_V  0x00000001U
-#define PARL_IO_RX_FIFO_WFULL_INT_ENA_S  1
-/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to enable TX_EOF_INTR.
- */
-#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
-#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
-#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_ENA_S  2
-
-/** PARL_IO_INT_RAW_REG register
- *  Parallel IO interrupt raw singal status register.
- */
-#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x18)
-/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status of TX_FIFO_REMPTY_INTR.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
-/** PARL_IO_RX_FIFO_WFULL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status of RX_FIFO_WFULL_INTR.
- */
-#define PARL_IO_RX_FIFO_WFULL_INT_RAW    (BIT(1))
-#define PARL_IO_RX_FIFO_WFULL_INT_RAW_M  (PARL_IO_RX_FIFO_WFULL_INT_RAW_V << PARL_IO_RX_FIFO_WFULL_INT_RAW_S)
-#define PARL_IO_RX_FIFO_WFULL_INT_RAW_V  0x00000001U
-#define PARL_IO_RX_FIFO_WFULL_INT_RAW_S  1
-/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status of TX_EOF_INTR.
- */
-#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
-#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
-#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_RAW_S  2
-
-/** PARL_IO_INT_ST_REG register
- *  Parallel IO interrupt singal status register.
- */
-#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x1c)
-/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status of TX_FIFO_REMPTY_INTR.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
-/** PARL_IO_RX_FIFO_WFULL_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status of RX_FIFO_WFULL_INTR.
- */
-#define PARL_IO_RX_FIFO_WFULL_INT_ST    (BIT(1))
-#define PARL_IO_RX_FIFO_WFULL_INT_ST_M  (PARL_IO_RX_FIFO_WFULL_INT_ST_V << PARL_IO_RX_FIFO_WFULL_INT_ST_S)
-#define PARL_IO_RX_FIFO_WFULL_INT_ST_V  0x00000001U
-#define PARL_IO_RX_FIFO_WFULL_INT_ST_S  1
-/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status of TX_EOF_INTR.
- */
-#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
-#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
-#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_ST_S  2
-
-/** PARL_IO_INT_CLR_REG register
- *  Parallel IO interrupt  clear singal configuration register.
- */
-#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x20)
-/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear TX_FIFO_REMPTY_INTR.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
-/** PARL_IO_RX_FIFO_WFULL_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear RX_FIFO_WFULL_INTR.
- */
-#define PARL_IO_RX_FIFO_WFULL_INT_CLR    (BIT(1))
-#define PARL_IO_RX_FIFO_WFULL_INT_CLR_M  (PARL_IO_RX_FIFO_WFULL_INT_CLR_V << PARL_IO_RX_FIFO_WFULL_INT_CLR_S)
-#define PARL_IO_RX_FIFO_WFULL_INT_CLR_V  0x00000001U
-#define PARL_IO_RX_FIFO_WFULL_INT_CLR_S  1
-/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear TX_EOF_INTR.
- */
-#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
-#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
-#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_CLR_S  2
-
-/** PARL_IO_CLK_REG register
- *  Parallel IO clk configuration register
- */
-#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
-/** PARL_IO_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Force clock on for this register file
- */
-#define PARL_IO_CLK_EN    (BIT(0))
-#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
-#define PARL_IO_CLK_EN_V  0x00000001U
-#define PARL_IO_CLK_EN_S  0
-
-/** PARL_IO_VERSION_REG register
- *  Version register.
- */
-#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
-/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35660352;
- *  Version of this register file
- */
-#define PARL_IO_DATE    0x0FFFFFFFU
-#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
-#define PARL_IO_DATE_V  0x0FFFFFFFU
-#define PARL_IO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/parl_io_struct.h b/components/soc/esp32c6/include/soc/parl_io_struct.h
deleted file mode 100644
index 816a7de3ef1..00000000000
--- a/components/soc/esp32c6/include/soc/parl_io_struct.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PARL_IO RX Configuration0 */
-/** Type of rx_cfg0 register
- *  Parallel RX module configuration register0.
- */
-typedef union {
-    struct {
-        /** rx_eof_gen_sel : R/W; bitpos: [0]; default: 0;
-         *  Write 0 to select eof generated manchnism by configured data byte length. Write 1
-         *  to select eof generated manchnism by external enable signal.
-         */
-        uint32_t rx_eof_gen_sel:1;
-        /** rx_start : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to start rx global data sampling.
-         */
-        uint32_t rx_start:1;
-        /** rx_data_bytelen : R/W; bitpos: [17:2]; default: 0;
-         *  Configures rx receieved data byte length.
-         */
-        uint32_t rx_data_bytelen:16;
-        /** rx_sw_en : R/W; bitpos: [18]; default: 0;
-         *  Write 1 to enable software data sampling.
-         */
-        uint32_t rx_sw_en:1;
-        /** rx_pulse_submode_sel : R/W; bitpos: [22:19]; default: 0;
-         *  Pulse submode selection.
-         *  0000: positive pulse start(data bit included) &&  positive pulse end(data bit
-         *  included)
-         *  0001: positive pulse start(data bit included) && positive pulse end (data bit
-         *  excluded)
-         *  0010: positive pulse start(data bit excluded) && positive pulse end (data bit
-         *  included)
-         *  0011: positive pulse start(data bit excluded) && positive pulse end (data bit
-         *  excluded)
-         *  0100: positive pulse start(data bit included) && length end
-         *  0101: positive pulse start(data bit excluded) && length end
-         *  0110: negative pulse start(data bit included) &&  negative pulse end(data bit
-         *  included)
-         *  0111: negative pulse start(data bit included) && negative pulse end (data bit
-         *  excluded)
-         *  1000: negative pulse start(data bit excluded) && negative pulse end (data bit
-         *  included)
-         *  1001: negative pulse start(data bit excluded) && negative pulse end (data bit
-         *  excluded)
-         *  1010: negative pulse start(data bit included) && length end
-         *  1011: negative pulse start(data bit excluded) && length end
-         */
-        uint32_t rx_pulse_submode_sel:4;
-        /** rx_level_submode_sel : R/W; bitpos: [23]; default: 0;
-         *  Write 0 to sample data at high level of external enable signal. Write 1 to sample
-         *  data at low level of external enable signal.
-         */
-        uint32_t rx_level_submode_sel:1;
-        /** rx_smp_mode_sel : R/W; bitpos: [25:24]; default: 0;
-         *  Rx data sampling mode selection.
-         *  000: external level enable mode
-         *  001: external pulse enable mode
-         *  010: internal software enable mode
-         */
-        uint32_t rx_smp_mode_sel:2;
-        /** rx_clk_edge_sel : R/W; bitpos: [26]; default: 0;
-         *  Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable
-         *  sampling data on the falling edge of rx clock.
-         */
-        uint32_t rx_clk_edge_sel:1;
-        /** rx_bit_pack_order : R/W; bitpos: [27]; default: 0;
-         *  Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0
-         *  to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.
-         */
-        uint32_t rx_bit_pack_order:1;
-        /** rx_bus_wid_sel : R/W; bitpos: [30:28]; default: 0;
-         *  Rx data bus width selection.
-         *  100: bus width is 1 bit
-         *  011: bus width is 2 bits
-         *  010: bus width is 4 bits
-         *  001: bus width is 8 bits
-         *  000: bus width is 16 bits
-         */
-        uint32_t rx_bus_wid_sel:3;
-        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
-         *  Write 1 to enable soft reset of async fifo in rx module.
-         */
-        uint32_t rx_fifo_srst:1;
-    };
-    uint32_t val;
-} parl_io_rx_cfg0_reg_t;
-
-
-/** Group: PARL_IO RX Configuration1 */
-/** Type of rx_cfg1 register
- *  Parallel RX module configuration register1.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** rx_reg_update : WT; bitpos: [2]; default: 0;
-         *  Write 1 to update rx register configuration signals.
-         */
-        uint32_t rx_reg_update:1;
-        /** rx_timeout_en : R/W; bitpos: [3]; default: 1;
-         *  Write 1 to enable timeout count to generate error eof.
-         */
-        uint32_t rx_timeout_en:1;
-        uint32_t reserved_4:8;
-        /** rx_ext_en_sel : R/W; bitpos: [15:12]; default: 15;
-         *  Configures rx external enable signal selection from 16 data lines.
-         */
-        uint32_t rx_ext_en_sel:4;
-        /** rx_timeout_threshold : R/W; bitpos: [31:16]; default: 4095;
-         *  Configures rx threshold of timeout counter.
-         */
-        uint32_t rx_timeout_threshold:16;
-    };
-    uint32_t val;
-} parl_io_rx_cfg1_reg_t;
-
-
-/** Group: PARL_IO TX Configuration0 */
-/** Type of tx_cfg0 register
- *  Parallel TX module configuration register0.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:2;
-        /** tx_bytelen : R/W; bitpos: [17:2]; default: 0;
-         *  Configures tx sending data byte length.
-         */
-        uint32_t tx_bytelen:16;
-        /** tx_gating_en : R/W; bitpos: [18]; default: 0;
-         *  Write 1 to enable output tx clock gating.
-         */
-        uint32_t tx_gating_en:1;
-        /** tx_start : R/W; bitpos: [19]; default: 0;
-         *  Write 1 to start tx global data output.
-         */
-        uint32_t tx_start:1;
-        /** tx_hw_valid_en : R/W; bitpos: [20]; default: 0;
-         *  Write 1 to enable tx hardware data valid signal.
-         */
-        uint32_t tx_hw_valid_en:1;
-        uint32_t reserved_21:4;
-        /** tx_smp_edge_sel : R/W; bitpos: [25]; default: 0;
-         *  Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable
-         *  sampling data on the falling edge of tx clock.
-         */
-        uint32_t tx_smp_edge_sel:1;
-        /** tx_bit_unpack_order : R/W; bitpos: [26]; default: 0;
-         *  Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write
-         *  0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits.
-         */
-        uint32_t tx_bit_unpack_order:1;
-        /** tx_bus_wid_sel : R/W; bitpos: [29:27]; default: 0;
-         *  Tx data bus width selection.
-         *  100: bus width is 1 bit
-         *  011: bus width is 2 bits
-         *  010: bus width is 4 bits
-         *  001: bus width is 8 bits
-         *  000: bus width is 16 bits
-         */
-        uint32_t tx_bus_wid_sel:3;
-        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
-         *  Write 1 to enable soft reset of async fifo in tx module.
-         */
-        uint32_t tx_fifo_srst:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} parl_io_tx_cfg0_reg_t;
-
-
-/** Group: PARL_IO TX Configuration1 */
-/** Type of tx_cfg1 register
- *  Parallel TX module configuration register1.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** tx_idle_value : R/W; bitpos: [31:16]; default: 0;
-         *  Configures data value on tx bus when IDLE state.
-         */
-        uint32_t tx_idle_value:16;
-    };
-    uint32_t val;
-} parl_io_tx_cfg1_reg_t;
-
-
-/** Group: PARL_IO TX Status0 */
-/** Type of st register
- *  Parallel IO module status register0.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_ready : RO; bitpos: [31]; default: 0;
-         *  Represents the status that tx is ready.
-         */
-        uint32_t tx_ready:1;
-    };
-    uint32_t val;
-} parl_io_st_reg_t;
-
-
-/** Group: PARL_IO Interrupt Configuration and Status */
-/** Type of int_ena register
- *  Parallel IO interrupt enable singal configuration register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable TX_FIFO_REMPTY_INTR.
-         */
-        uint32_t tx_fifo_rempty_int_ena:1;
-        /** rx_fifo_wfull_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable RX_FIFO_WFULL_INTR.
-         */
-        uint32_t rx_fifo_wfull_int_ena:1;
-        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable TX_EOF_INTR.
-         */
-        uint32_t tx_eof_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Parallel IO interrupt raw singal status register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status of TX_FIFO_REMPTY_INTR.
-         */
-        uint32_t tx_fifo_rempty_int_raw:1;
-        /** rx_fifo_wfull_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status of RX_FIFO_WFULL_INTR.
-         */
-        uint32_t rx_fifo_wfull_int_raw:1;
-        /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status of TX_EOF_INTR.
-         */
-        uint32_t tx_eof_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_raw_reg_t;
-
-/** Type of int_st register
- *  Parallel IO interrupt singal status register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status of TX_FIFO_REMPTY_INTR.
-         */
-        uint32_t tx_fifo_rempty_int_st:1;
-        /** rx_fifo_wfull_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status of RX_FIFO_WFULL_INTR.
-         */
-        uint32_t rx_fifo_wfull_int_st:1;
-        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status of TX_EOF_INTR.
-         */
-        uint32_t tx_eof_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_st_reg_t;
-
-/** Type of int_clr register
- *  Parallel IO interrupt  clear singal configuration register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear TX_FIFO_REMPTY_INTR.
-         */
-        uint32_t tx_fifo_rempty_int_clr:1;
-        /** rx_fifo_wfull_int_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear RX_FIFO_WFULL_INTR.
-         */
-        uint32_t rx_fifo_wfull_int_clr:1;
-        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear TX_EOF_INTR.
-         */
-        uint32_t tx_eof_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_clr_reg_t;
-
-
-/** Group: PARL_IO Clock Gating Configuration */
-/** Type of clk register
- *  Parallel IO clk configuration register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Force clock on for this register file
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} parl_io_clk_reg_t;
-
-
-/** Group: PARL_IO Version Register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35660352;
-         *  Version of this register file
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} parl_io_version_reg_t;
-
-
-typedef struct parl_io_dev_t {
-    volatile parl_io_rx_cfg0_reg_t rx_cfg0;
-    volatile parl_io_rx_cfg1_reg_t rx_cfg1;
-    volatile parl_io_tx_cfg0_reg_t tx_cfg0;
-    volatile parl_io_tx_cfg1_reg_t tx_cfg1;
-    volatile parl_io_st_reg_t st;
-    volatile parl_io_int_ena_reg_t int_ena;
-    volatile parl_io_int_raw_reg_t int_raw;
-    volatile parl_io_int_st_reg_t int_st;
-    volatile parl_io_int_clr_reg_t int_clr;
-    uint32_t reserved_024[63];
-    volatile parl_io_clk_reg_t clk;
-    uint32_t reserved_124[182];
-    volatile parl_io_version_reg_t version;
-} parl_io_dev_t;
-
-extern parl_io_dev_t PARL_IO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/pcr_reg.h b/components/soc/esp32c6/include/soc/pcr_reg.h
deleted file mode 100644
index 35a77baaab4..00000000000
--- a/components/soc/esp32c6/include/soc/pcr_reg.h
+++ /dev/null
@@ -1,2065 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PCR_UART0_CONF_REG register
- *  UART0 configuration register
- */
-#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)
-/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uart0 apb clock
- */
-#define PCR_UART0_CLK_EN    (BIT(0))
-#define PCR_UART0_CLK_EN_M  (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S)
-#define PCR_UART0_CLK_EN_V  0x00000001U
-#define PCR_UART0_CLK_EN_S  0
-/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uart0 module
- */
-#define PCR_UART0_RST_EN    (BIT(1))
-#define PCR_UART0_RST_EN_M  (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
-#define PCR_UART0_RST_EN_V  0x00000001U
-#define PCR_UART0_RST_EN_S  1
-
-/** PCR_UART0_SCLK_CONF_REG register
- *  UART0_SCLK configuration register
- */
-#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)
-/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_A    0x0000003FU
-#define PCR_UART0_SCLK_DIV_A_M  (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S)
-#define PCR_UART0_SCLK_DIV_A_V  0x0000003FU
-#define PCR_UART0_SCLK_DIV_A_S  0
-/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_B    0x0000003FU
-#define PCR_UART0_SCLK_DIV_B_M  (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S)
-#define PCR_UART0_SCLK_DIV_B_V  0x0000003FU
-#define PCR_UART0_SCLK_DIV_B_S  6
-/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_NUM    0x000000FFU
-#define PCR_UART0_SCLK_DIV_NUM_M  (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S)
-#define PCR_UART0_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_UART0_SCLK_DIV_NUM_S  12
-/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_UART0_SCLK_SEL    0x00000003U
-#define PCR_UART0_SCLK_SEL_M  (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
-#define PCR_UART0_SCLK_SEL_V  0x00000003U
-#define PCR_UART0_SCLK_SEL_S  20
-/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable uart0 function clock
- */
-#define PCR_UART0_SCLK_EN    (BIT(22))
-#define PCR_UART0_SCLK_EN_M  (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S)
-#define PCR_UART0_SCLK_EN_V  0x00000001U
-#define PCR_UART0_SCLK_EN_S  22
-
-/** PCR_UART0_PD_CTRL_REG register
- *  UART0 power control register
- */
-#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)
-/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power down UART0 memory.
- */
-#define PCR_UART0_MEM_FORCE_PU    (BIT(1))
-#define PCR_UART0_MEM_FORCE_PU_M  (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S)
-#define PCR_UART0_MEM_FORCE_PU_V  0x00000001U
-#define PCR_UART0_MEM_FORCE_PU_S  1
-/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power up UART0 memory.
- */
-#define PCR_UART0_MEM_FORCE_PD    (BIT(2))
-#define PCR_UART0_MEM_FORCE_PD_M  (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S)
-#define PCR_UART0_MEM_FORCE_PD_V  0x00000001U
-#define PCR_UART0_MEM_FORCE_PD_S  2
-
-/** PCR_UART1_CONF_REG register
- *  UART1 configuration register
- */
-#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)
-/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uart1 apb clock
- */
-#define PCR_UART1_CLK_EN    (BIT(0))
-#define PCR_UART1_CLK_EN_M  (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S)
-#define PCR_UART1_CLK_EN_V  0x00000001U
-#define PCR_UART1_CLK_EN_S  0
-/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uart1 module
- */
-#define PCR_UART1_RST_EN    (BIT(1))
-#define PCR_UART1_RST_EN_M  (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
-#define PCR_UART1_RST_EN_V  0x00000001U
-#define PCR_UART1_RST_EN_S  1
-
-/** PCR_UART1_SCLK_CONF_REG register
- *  UART1_SCLK configuration register
- */
-#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)
-/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_A    0x0000003FU
-#define PCR_UART1_SCLK_DIV_A_M  (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S)
-#define PCR_UART1_SCLK_DIV_A_V  0x0000003FU
-#define PCR_UART1_SCLK_DIV_A_S  0
-/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_B    0x0000003FU
-#define PCR_UART1_SCLK_DIV_B_M  (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S)
-#define PCR_UART1_SCLK_DIV_B_V  0x0000003FU
-#define PCR_UART1_SCLK_DIV_B_S  6
-/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_NUM    0x000000FFU
-#define PCR_UART1_SCLK_DIV_NUM_M  (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S)
-#define PCR_UART1_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_UART1_SCLK_DIV_NUM_S  12
-/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_UART1_SCLK_SEL    0x00000003U
-#define PCR_UART1_SCLK_SEL_M  (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
-#define PCR_UART1_SCLK_SEL_V  0x00000003U
-#define PCR_UART1_SCLK_SEL_S  20
-/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable uart0 function clock
- */
-#define PCR_UART1_SCLK_EN    (BIT(22))
-#define PCR_UART1_SCLK_EN_M  (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S)
-#define PCR_UART1_SCLK_EN_V  0x00000001U
-#define PCR_UART1_SCLK_EN_S  22
-
-/** PCR_UART1_PD_CTRL_REG register
- *  UART1 power control register
- */
-#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)
-/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power down UART1 memory.
- */
-#define PCR_UART1_MEM_FORCE_PU    (BIT(1))
-#define PCR_UART1_MEM_FORCE_PU_M  (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S)
-#define PCR_UART1_MEM_FORCE_PU_V  0x00000001U
-#define PCR_UART1_MEM_FORCE_PU_S  1
-/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power up UART1 memory.
- */
-#define PCR_UART1_MEM_FORCE_PD    (BIT(2))
-#define PCR_UART1_MEM_FORCE_PD_M  (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S)
-#define PCR_UART1_MEM_FORCE_PD_V  0x00000001U
-#define PCR_UART1_MEM_FORCE_PD_S  2
-
-/** PCR_MSPI_CONF_REG register
- *  MSPI configuration register
- */
-#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)
-/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable mspi clock, include mspi pll clock
- */
-#define PCR_MSPI_CLK_EN    (BIT(0))
-#define PCR_MSPI_CLK_EN_M  (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S)
-#define PCR_MSPI_CLK_EN_V  0x00000001U
-#define PCR_MSPI_CLK_EN_S  0
-/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset mspi module
- */
-#define PCR_MSPI_RST_EN    (BIT(1))
-#define PCR_MSPI_RST_EN_M  (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
-#define PCR_MSPI_RST_EN_V  0x00000001U
-#define PCR_MSPI_RST_EN_S  1
-/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable mspi pll clock
- */
-#define PCR_MSPI_PLL_CLK_EN    (BIT(2))
-#define PCR_MSPI_PLL_CLK_EN_M  (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S)
-#define PCR_MSPI_PLL_CLK_EN_V  0x00000001U
-#define PCR_MSPI_PLL_CLK_EN_S  2
-
-/** PCR_MSPI_CLK_CONF_REG register
- *  MSPI_CLK configuration register
- */
-#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
-/** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
- *  low-speed clock-source such as XTAL/FOSC.
- */
-#define PCR_MSPI_FAST_LS_DIV_NUM    0x000000FFU
-#define PCR_MSPI_FAST_LS_DIV_NUM_M  (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S)
-#define PCR_MSPI_FAST_LS_DIV_NUM_V  0x000000FFU
-#define PCR_MSPI_FAST_LS_DIV_NUM_S  0
-/** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
- *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
- *  high-speed clock-source such as SPLL.
- */
-#define PCR_MSPI_FAST_HS_DIV_NUM    0x000000FFU
-#define PCR_MSPI_FAST_HS_DIV_NUM_M  (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S)
-#define PCR_MSPI_FAST_HS_DIV_NUM_V  0x000000FFU
-#define PCR_MSPI_FAST_HS_DIV_NUM_S  8
-
-/** PCR_I2C_CONF_REG register
- *  I2C configuration register
- */
-#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20)
-/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2c apb clock
- */
-#define PCR_I2C_CLK_EN    (BIT(0))
-#define PCR_I2C_CLK_EN_M  (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S)
-#define PCR_I2C_CLK_EN_V  0x00000001U
-#define PCR_I2C_CLK_EN_S  0
-/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2c module
- */
-#define PCR_I2C_RST_EN    (BIT(1))
-#define PCR_I2C_RST_EN_M  (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S)
-#define PCR_I2C_RST_EN_V  0x00000001U
-#define PCR_I2C_RST_EN_S  1
-
-/** PCR_I2C_SCLK_CONF_REG register
- *  I2C_SCLK configuration register
- */
-#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)
-/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_A    0x0000003FU
-#define PCR_I2C_SCLK_DIV_A_M  (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S)
-#define PCR_I2C_SCLK_DIV_A_V  0x0000003FU
-#define PCR_I2C_SCLK_DIV_A_S  0
-/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_B    0x0000003FU
-#define PCR_I2C_SCLK_DIV_B_M  (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S)
-#define PCR_I2C_SCLK_DIV_B_V  0x0000003FU
-#define PCR_I2C_SCLK_DIV_B_S  6
-/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C_SCLK_DIV_NUM    0x000000FFU
-#define PCR_I2C_SCLK_DIV_NUM_M  (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S)
-#define PCR_I2C_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_I2C_SCLK_DIV_NUM_S  12
-/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_I2C_SCLK_SEL    (BIT(20))
-#define PCR_I2C_SCLK_SEL_M  (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S)
-#define PCR_I2C_SCLK_SEL_V  0x00000001U
-#define PCR_I2C_SCLK_SEL_S  20
-/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2c function clock
- */
-#define PCR_I2C_SCLK_EN    (BIT(22))
-#define PCR_I2C_SCLK_EN_M  (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S)
-#define PCR_I2C_SCLK_EN_V  0x00000001U
-#define PCR_I2C_SCLK_EN_S  22
-
-/** PCR_UHCI_CONF_REG register
- *  UHCI configuration register
- */
-#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28)
-/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uhci clock
- */
-#define PCR_UHCI_CLK_EN    (BIT(0))
-#define PCR_UHCI_CLK_EN_M  (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S)
-#define PCR_UHCI_CLK_EN_V  0x00000001U
-#define PCR_UHCI_CLK_EN_S  0
-/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uhci module
- */
-#define PCR_UHCI_RST_EN    (BIT(1))
-#define PCR_UHCI_RST_EN_M  (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S)
-#define PCR_UHCI_RST_EN_V  0x00000001U
-#define PCR_UHCI_RST_EN_S  1
-
-/** PCR_RMT_CONF_REG register
- *  RMT configuration register
- */
-#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c)
-/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable rmt apb clock
- */
-#define PCR_RMT_CLK_EN    (BIT(0))
-#define PCR_RMT_CLK_EN_M  (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S)
-#define PCR_RMT_CLK_EN_V  0x00000001U
-#define PCR_RMT_CLK_EN_S  0
-/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset rmt module
- */
-#define PCR_RMT_RST_EN    (BIT(1))
-#define PCR_RMT_RST_EN_M  (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S)
-#define PCR_RMT_RST_EN_V  0x00000001U
-#define PCR_RMT_RST_EN_S  1
-
-/** PCR_RMT_SCLK_CONF_REG register
- *  RMT_SCLK configuration register
- */
-#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30)
-/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_A    0x0000003FU
-#define PCR_RMT_SCLK_DIV_A_M  (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S)
-#define PCR_RMT_SCLK_DIV_A_V  0x0000003FU
-#define PCR_RMT_SCLK_DIV_A_S  0
-/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_B    0x0000003FU
-#define PCR_RMT_SCLK_DIV_B_M  (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S)
-#define PCR_RMT_SCLK_DIV_B_V  0x0000003FU
-#define PCR_RMT_SCLK_DIV_B_S  6
-/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
- *  The integral part of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_NUM    0x000000FFU
-#define PCR_RMT_SCLK_DIV_NUM_M  (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S)
-#define PCR_RMT_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_RMT_SCLK_DIV_NUM_S  12
-/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1;
- *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
- *  80MHz, 2: FOSC, 3: XTAL.
- */
-#define PCR_RMT_SCLK_SEL    0x00000003U
-#define PCR_RMT_SCLK_SEL_M  (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S)
-#define PCR_RMT_SCLK_SEL_V  0x00000003U
-#define PCR_RMT_SCLK_SEL_S  20
-/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable rmt function clock
- */
-#define PCR_RMT_SCLK_EN    (BIT(22))
-#define PCR_RMT_SCLK_EN_M  (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S)
-#define PCR_RMT_SCLK_EN_V  0x00000001U
-#define PCR_RMT_SCLK_EN_S  22
-
-/** PCR_LEDC_CONF_REG register
- *  LEDC configuration register
- */
-#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34)
-/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ledc apb clock
- */
-#define PCR_LEDC_CLK_EN    (BIT(0))
-#define PCR_LEDC_CLK_EN_M  (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S)
-#define PCR_LEDC_CLK_EN_V  0x00000001U
-#define PCR_LEDC_CLK_EN_S  0
-/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ledc module
- */
-#define PCR_LEDC_RST_EN    (BIT(1))
-#define PCR_LEDC_RST_EN_M  (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
-#define PCR_LEDC_RST_EN_V  0x00000001U
-#define PCR_LEDC_RST_EN_S  1
-
-/** PCR_LEDC_SCLK_CONF_REG register
- *  LEDC_SCLK configuration register
- */
-#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38)
-/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
- *  80MHz, 2: FOSC, 3: XTAL.
- */
-#define PCR_LEDC_SCLK_SEL    0x00000003U
-#define PCR_LEDC_SCLK_SEL_M  (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
-#define PCR_LEDC_SCLK_SEL_V  0x00000003U
-#define PCR_LEDC_SCLK_SEL_S  20
-/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable ledc function clock
- */
-#define PCR_LEDC_SCLK_EN    (BIT(22))
-#define PCR_LEDC_SCLK_EN_M  (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S)
-#define PCR_LEDC_SCLK_EN_V  0x00000001U
-#define PCR_LEDC_SCLK_EN_S  22
-
-/** PCR_TIMERGROUP0_CONF_REG register
- *  TIMERGROUP0 configuration register
- */
-#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c)
-/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable timer_group0 apb clock
- */
-#define PCR_TG0_CLK_EN    (BIT(0))
-#define PCR_TG0_CLK_EN_M  (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S)
-#define PCR_TG0_CLK_EN_V  0x00000001U
-#define PCR_TG0_CLK_EN_S  0
-/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group0 module
- */
-#define PCR_TG0_RST_EN    (BIT(1))
-#define PCR_TG0_RST_EN_M  (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
-#define PCR_TG0_RST_EN_V  0x00000001U
-#define PCR_TG0_RST_EN_S  1
-
-/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register
- *  TIMERGROUP0_TIMER_CLK configuration register
- */
-#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
-/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG0_TIMER_CLK_SEL    0x00000003U
-#define PCR_TG0_TIMER_CLK_SEL_M  (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
-#define PCR_TG0_TIMER_CLK_SEL_V  0x00000003U
-#define PCR_TG0_TIMER_CLK_SEL_S  20
-/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 timer clock
- */
-#define PCR_TG0_TIMER_CLK_EN    (BIT(22))
-#define PCR_TG0_TIMER_CLK_EN_M  (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S)
-#define PCR_TG0_TIMER_CLK_EN_V  0x00000001U
-#define PCR_TG0_TIMER_CLK_EN_S  22
-
-/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register
- *  TIMERGROUP0_WDT_CLK configuration register
- */
-#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44)
-/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG0_WDT_CLK_SEL    0x00000003U
-#define PCR_TG0_WDT_CLK_SEL_M  (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
-#define PCR_TG0_WDT_CLK_SEL_V  0x00000003U
-#define PCR_TG0_WDT_CLK_SEL_S  20
-/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 wdt clock
- */
-#define PCR_TG0_WDT_CLK_EN    (BIT(22))
-#define PCR_TG0_WDT_CLK_EN_M  (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S)
-#define PCR_TG0_WDT_CLK_EN_V  0x00000001U
-#define PCR_TG0_WDT_CLK_EN_S  22
-
-/** PCR_TIMERGROUP1_CONF_REG register
- *  TIMERGROUP1 configuration register
- */
-#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48)
-/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable timer_group1 apb clock
- */
-#define PCR_TG1_CLK_EN    (BIT(0))
-#define PCR_TG1_CLK_EN_M  (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S)
-#define PCR_TG1_CLK_EN_V  0x00000001U
-#define PCR_TG1_CLK_EN_S  0
-/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group1 module
- */
-#define PCR_TG1_RST_EN    (BIT(1))
-#define PCR_TG1_RST_EN_M  (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
-#define PCR_TG1_RST_EN_V  0x00000001U
-#define PCR_TG1_RST_EN_S  1
-
-/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register
- *  TIMERGROUP1_TIMER_CLK configuration register
- */
-#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c)
-/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG1_TIMER_CLK_SEL    0x00000003U
-#define PCR_TG1_TIMER_CLK_SEL_M  (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
-#define PCR_TG1_TIMER_CLK_SEL_V  0x00000003U
-#define PCR_TG1_TIMER_CLK_SEL_S  20
-/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group1 timer clock
- */
-#define PCR_TG1_TIMER_CLK_EN    (BIT(22))
-#define PCR_TG1_TIMER_CLK_EN_M  (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S)
-#define PCR_TG1_TIMER_CLK_EN_V  0x00000001U
-#define PCR_TG1_TIMER_CLK_EN_S  22
-
-/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register
- *  TIMERGROUP1_WDT_CLK configuration register
- */
-#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50)
-/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG1_WDT_CLK_SEL    0x00000003U
-#define PCR_TG1_WDT_CLK_SEL_M  (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
-#define PCR_TG1_WDT_CLK_SEL_V  0x00000003U
-#define PCR_TG1_WDT_CLK_SEL_S  20
-/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 wdt clock
- */
-#define PCR_TG1_WDT_CLK_EN    (BIT(22))
-#define PCR_TG1_WDT_CLK_EN_M  (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S)
-#define PCR_TG1_WDT_CLK_EN_V  0x00000001U
-#define PCR_TG1_WDT_CLK_EN_S  22
-
-/** PCR_SYSTIMER_CONF_REG register
- *  SYSTIMER configuration register
- */
-#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54)
-/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable systimer apb clock
- */
-#define PCR_SYSTIMER_CLK_EN    (BIT(0))
-#define PCR_SYSTIMER_CLK_EN_M  (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S)
-#define PCR_SYSTIMER_CLK_EN_V  0x00000001U
-#define PCR_SYSTIMER_CLK_EN_S  0
-/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset systimer module
- */
-#define PCR_SYSTIMER_RST_EN    (BIT(1))
-#define PCR_SYSTIMER_RST_EN_M  (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
-#define PCR_SYSTIMER_RST_EN_V  0x00000001U
-#define PCR_SYSTIMER_RST_EN_S  1
-
-/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register
- *  SYSTIMER_FUNC_CLK configuration register
- */
-#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58)
-/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_SYSTIMER_FUNC_CLK_SEL    (BIT(20))
-#define PCR_SYSTIMER_FUNC_CLK_SEL_M  (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
-#define PCR_SYSTIMER_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_SYSTIMER_FUNC_CLK_SEL_S  20
-/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable systimer function clock
- */
-#define PCR_SYSTIMER_FUNC_CLK_EN    (BIT(22))
-#define PCR_SYSTIMER_FUNC_CLK_EN_M  (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S)
-#define PCR_SYSTIMER_FUNC_CLK_EN_V  0x00000001U
-#define PCR_SYSTIMER_FUNC_CLK_EN_S  22
-
-/** PCR_TWAI0_CONF_REG register
- *  TWAI0 configuration register
- */
-#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c)
-/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable twai0 apb clock
- */
-#define PCR_TWAI0_CLK_EN    (BIT(0))
-#define PCR_TWAI0_CLK_EN_M  (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S)
-#define PCR_TWAI0_CLK_EN_V  0x00000001U
-#define PCR_TWAI0_CLK_EN_S  0
-/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset twai0 module
- */
-#define PCR_TWAI0_RST_EN    (BIT(1))
-#define PCR_TWAI0_RST_EN_M  (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S)
-#define PCR_TWAI0_RST_EN_V  0x00000001U
-#define PCR_TWAI0_RST_EN_S  1
-
-/** PCR_TWAI0_FUNC_CLK_CONF_REG register
- *  TWAI0_FUNC_CLK configuration register
- */
-#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60)
-/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_TWAI0_FUNC_CLK_SEL    (BIT(20))
-#define PCR_TWAI0_FUNC_CLK_SEL_M  (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S)
-#define PCR_TWAI0_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_TWAI0_FUNC_CLK_SEL_S  20
-/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable twai0 function clock
- */
-#define PCR_TWAI0_FUNC_CLK_EN    (BIT(22))
-#define PCR_TWAI0_FUNC_CLK_EN_M  (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S)
-#define PCR_TWAI0_FUNC_CLK_EN_V  0x00000001U
-#define PCR_TWAI0_FUNC_CLK_EN_S  22
-
-/** PCR_TWAI1_CONF_REG register
- *  TWAI1 configuration register
- */
-#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64)
-/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable twai1 apb clock
- */
-#define PCR_TWAI1_CLK_EN    (BIT(0))
-#define PCR_TWAI1_CLK_EN_M  (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S)
-#define PCR_TWAI1_CLK_EN_V  0x00000001U
-#define PCR_TWAI1_CLK_EN_S  0
-/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset twai1 module
- */
-#define PCR_TWAI1_RST_EN    (BIT(1))
-#define PCR_TWAI1_RST_EN_M  (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S)
-#define PCR_TWAI1_RST_EN_V  0x00000001U
-#define PCR_TWAI1_RST_EN_S  1
-
-/** PCR_TWAI1_FUNC_CLK_CONF_REG register
- *  TWAI1_FUNC_CLK configuration register
- */
-#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68)
-/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_TWAI1_FUNC_CLK_SEL    (BIT(20))
-#define PCR_TWAI1_FUNC_CLK_SEL_M  (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S)
-#define PCR_TWAI1_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_TWAI1_FUNC_CLK_SEL_S  20
-/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable twai1 function clock
- */
-#define PCR_TWAI1_FUNC_CLK_EN    (BIT(22))
-#define PCR_TWAI1_FUNC_CLK_EN_M  (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S)
-#define PCR_TWAI1_FUNC_CLK_EN_V  0x00000001U
-#define PCR_TWAI1_FUNC_CLK_EN_S  22
-
-/** PCR_I2S_CONF_REG register
- *  I2S configuration register
- */
-#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c)
-/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2s apb clock
- */
-#define PCR_I2S_CLK_EN    (BIT(0))
-#define PCR_I2S_CLK_EN_M  (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S)
-#define PCR_I2S_CLK_EN_V  0x00000001U
-#define PCR_I2S_CLK_EN_S  0
-/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2s module
- */
-#define PCR_I2S_RST_EN    (BIT(1))
-#define PCR_I2S_RST_EN_M  (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
-#define PCR_I2S_RST_EN_V  0x00000001U
-#define PCR_I2S_RST_EN_S  1
-
-/** PCR_I2S_TX_CLKM_CONF_REG register
- *  I2S_TX_CLKM configuration register
- */
-#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70)
-/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
- *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
- *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
- *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
- *  (n+1)-div] + y * (n+1)-div.
- */
-#define PCR_I2S_TX_CLKM_DIV_NUM    0x000000FFU
-#define PCR_I2S_TX_CLKM_DIV_NUM_M  (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S)
-#define PCR_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_I2S_TX_CLKM_DIV_NUM_S  12
-/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
- *  I2S_MCLK_in.
- */
-#define PCR_I2S_TX_CLKM_SEL    0x00000003U
-#define PCR_I2S_TX_CLKM_SEL_M  (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
-#define PCR_I2S_TX_CLKM_SEL_V  0x00000003U
-#define PCR_I2S_TX_CLKM_SEL_S  20
-/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2s_tx function clock
- */
-#define PCR_I2S_TX_CLKM_EN    (BIT(22))
-#define PCR_I2S_TX_CLKM_EN_M  (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S)
-#define PCR_I2S_TX_CLKM_EN_V  0x00000001U
-#define PCR_I2S_TX_CLKM_EN_S  22
-
-/** PCR_I2S_TX_CLKM_DIV_CONF_REG register
- *  I2S_TX_CLKM_DIV configuration register
- */
-#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74)
-/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Z is (a-b).
- */
-#define PCR_I2S_TX_CLKM_DIV_Z    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Z_M  (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S)
-#define PCR_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Z_S  0
-/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define PCR_I2S_TX_CLKM_DIV_Y    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Y_M  (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S)
-#define PCR_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Y_S  9
-/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define PCR_I2S_TX_CLKM_DIV_X    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_X_M  (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S)
-#define PCR_I2S_TX_CLKM_DIV_X_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_X_S  18
-/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_YN1 is 1.
- */
-#define PCR_I2S_TX_CLKM_DIV_YN1    (BIT(27))
-#define PCR_I2S_TX_CLKM_DIV_YN1_M  (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S)
-#define PCR_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
-#define PCR_I2S_TX_CLKM_DIV_YN1_S  27
-
-/** PCR_I2S_RX_CLKM_CONF_REG register
- *  I2S_RX_CLKM configuration register
- */
-#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78)
-/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
- *  Integral I2S clock divider value
- */
-#define PCR_I2S_RX_CLKM_DIV_NUM    0x000000FFU
-#define PCR_I2S_RX_CLKM_DIV_NUM_M  (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S)
-#define PCR_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_I2S_RX_CLKM_DIV_NUM_S  12
-/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
- */
-#define PCR_I2S_RX_CLKM_SEL    0x00000003U
-#define PCR_I2S_RX_CLKM_SEL_M  (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
-#define PCR_I2S_RX_CLKM_SEL_V  0x00000003U
-#define PCR_I2S_RX_CLKM_SEL_S  20
-/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2s_rx function clock
- */
-#define PCR_I2S_RX_CLKM_EN    (BIT(22))
-#define PCR_I2S_RX_CLKM_EN_M  (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S)
-#define PCR_I2S_RX_CLKM_EN_V  0x00000001U
-#define PCR_I2S_RX_CLKM_EN_S  22
-/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
- *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
- */
-#define PCR_I2S_MCLK_SEL    (BIT(23))
-#define PCR_I2S_MCLK_SEL_M  (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
-#define PCR_I2S_MCLK_SEL_V  0x00000001U
-#define PCR_I2S_MCLK_SEL_S  23
-
-/** PCR_I2S_RX_CLKM_DIV_CONF_REG register
- *  I2S_RX_CLKM_DIV configuration register
- */
-#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c)
-/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Z is (a-b).
- */
-#define PCR_I2S_RX_CLKM_DIV_Z    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Z_M  (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S)
-#define PCR_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Z_S  0
-/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define PCR_I2S_RX_CLKM_DIV_Y    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Y_M  (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S)
-#define PCR_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Y_S  9
-/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define PCR_I2S_RX_CLKM_DIV_X    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_X_M  (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S)
-#define PCR_I2S_RX_CLKM_DIV_X_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_X_S  18
-/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_YN1 is 1.
- */
-#define PCR_I2S_RX_CLKM_DIV_YN1    (BIT(27))
-#define PCR_I2S_RX_CLKM_DIV_YN1_M  (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S)
-#define PCR_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
-#define PCR_I2S_RX_CLKM_DIV_YN1_S  27
-
-/** PCR_SARADC_CONF_REG register
- *  SARADC configuration register
- */
-#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80)
-/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  no use
- */
-#define PCR_SARADC_CLK_EN    (BIT(0))
-#define PCR_SARADC_CLK_EN_M  (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S)
-#define PCR_SARADC_CLK_EN_V  0x00000001U
-#define PCR_SARADC_CLK_EN_S  0
-/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset function_register of saradc module
- */
-#define PCR_SARADC_RST_EN    (BIT(1))
-#define PCR_SARADC_RST_EN_M  (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
-#define PCR_SARADC_RST_EN_V  0x00000001U
-#define PCR_SARADC_RST_EN_S  1
-/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable saradc apb clock
- */
-#define PCR_SARADC_REG_CLK_EN    (BIT(2))
-#define PCR_SARADC_REG_CLK_EN_M  (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S)
-#define PCR_SARADC_REG_CLK_EN_V  0x00000001U
-#define PCR_SARADC_REG_CLK_EN_S  2
-/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
- *  Set 0 to reset apb_register of saradc module
- */
-#define PCR_SARADC_REG_RST_EN    (BIT(3))
-#define PCR_SARADC_REG_RST_EN_M  (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
-#define PCR_SARADC_REG_RST_EN_V  0x00000001U
-#define PCR_SARADC_REG_RST_EN_S  3
-
-/** PCR_SARADC_CLKM_CONF_REG register
- *  SARADC_CLKM configuration register
- */
-#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84)
-/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_A    0x0000003FU
-#define PCR_SARADC_CLKM_DIV_A_M  (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S)
-#define PCR_SARADC_CLKM_DIV_A_V  0x0000003FU
-#define PCR_SARADC_CLKM_DIV_A_S  0
-/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_B    0x0000003FU
-#define PCR_SARADC_CLKM_DIV_B_M  (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S)
-#define PCR_SARADC_CLKM_DIV_B_V  0x0000003FU
-#define PCR_SARADC_CLKM_DIV_B_S  6
-/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
- *  The integral part of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_NUM    0x000000FFU
-#define PCR_SARADC_CLKM_DIV_NUM_M  (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S)
-#define PCR_SARADC_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_SARADC_CLKM_DIV_NUM_S  12
-/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_SARADC_CLKM_SEL    0x00000003U
-#define PCR_SARADC_CLKM_SEL_M  (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
-#define PCR_SARADC_CLKM_SEL_V  0x00000003U
-#define PCR_SARADC_CLKM_SEL_S  20
-/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable saradc function clock
- */
-#define PCR_SARADC_CLKM_EN    (BIT(22))
-#define PCR_SARADC_CLKM_EN_M  (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S)
-#define PCR_SARADC_CLKM_EN_V  0x00000001U
-#define PCR_SARADC_CLKM_EN_S  22
-
-/** PCR_TSENS_CLK_CONF_REG register
- *  TSENS_CLK configuration register
- */
-#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88)
-/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
- */
-#define PCR_TSENS_CLK_SEL    (BIT(20))
-#define PCR_TSENS_CLK_SEL_M  (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
-#define PCR_TSENS_CLK_SEL_V  0x00000001U
-#define PCR_TSENS_CLK_SEL_S  20
-/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable tsens clock
- */
-#define PCR_TSENS_CLK_EN    (BIT(22))
-#define PCR_TSENS_CLK_EN_M  (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S)
-#define PCR_TSENS_CLK_EN_V  0x00000001U
-#define PCR_TSENS_CLK_EN_S  22
-/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
- *  Set 0 to reset tsens module
- */
-#define PCR_TSENS_RST_EN    (BIT(23))
-#define PCR_TSENS_RST_EN_M  (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
-#define PCR_TSENS_RST_EN_V  0x00000001U
-#define PCR_TSENS_RST_EN_S  23
-
-/** PCR_USB_DEVICE_CONF_REG register
- *  USB_DEVICE configuration register
- */
-#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c)
-/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable usb_device clock
- */
-#define PCR_USB_DEVICE_CLK_EN    (BIT(0))
-#define PCR_USB_DEVICE_CLK_EN_M  (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S)
-#define PCR_USB_DEVICE_CLK_EN_V  0x00000001U
-#define PCR_USB_DEVICE_CLK_EN_S  0
-/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset usb_device module
- */
-#define PCR_USB_DEVICE_RST_EN    (BIT(1))
-#define PCR_USB_DEVICE_RST_EN_M  (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
-#define PCR_USB_DEVICE_RST_EN_V  0x00000001U
-#define PCR_USB_DEVICE_RST_EN_S  1
-
-/** PCR_INTMTX_CONF_REG register
- *  INTMTX configuration register
- */
-#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90)
-/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable intmtx clock
- */
-#define PCR_INTMTX_CLK_EN    (BIT(0))
-#define PCR_INTMTX_CLK_EN_M  (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S)
-#define PCR_INTMTX_CLK_EN_V  0x00000001U
-#define PCR_INTMTX_CLK_EN_S  0
-/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset intmtx module
- */
-#define PCR_INTMTX_RST_EN    (BIT(1))
-#define PCR_INTMTX_RST_EN_M  (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
-#define PCR_INTMTX_RST_EN_V  0x00000001U
-#define PCR_INTMTX_RST_EN_S  1
-
-/** PCR_PCNT_CONF_REG register
- *  PCNT configuration register
- */
-#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94)
-/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable pcnt clock
- */
-#define PCR_PCNT_CLK_EN    (BIT(0))
-#define PCR_PCNT_CLK_EN_M  (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S)
-#define PCR_PCNT_CLK_EN_V  0x00000001U
-#define PCR_PCNT_CLK_EN_S  0
-/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset pcnt module
- */
-#define PCR_PCNT_RST_EN    (BIT(1))
-#define PCR_PCNT_RST_EN_M  (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S)
-#define PCR_PCNT_RST_EN_V  0x00000001U
-#define PCR_PCNT_RST_EN_S  1
-
-/** PCR_ETM_CONF_REG register
- *  ETM configuration register
- */
-#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98)
-/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable etm clock
- */
-#define PCR_ETM_CLK_EN    (BIT(0))
-#define PCR_ETM_CLK_EN_M  (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S)
-#define PCR_ETM_CLK_EN_V  0x00000001U
-#define PCR_ETM_CLK_EN_S  0
-/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset etm module
- */
-#define PCR_ETM_RST_EN    (BIT(1))
-#define PCR_ETM_RST_EN_M  (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
-#define PCR_ETM_RST_EN_V  0x00000001U
-#define PCR_ETM_RST_EN_S  1
-
-/** PCR_PWM_CONF_REG register
- *  PWM configuration register
- */
-#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c)
-/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable pwm clock
- */
-#define PCR_PWM_CLK_EN    (BIT(0))
-#define PCR_PWM_CLK_EN_M  (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S)
-#define PCR_PWM_CLK_EN_V  0x00000001U
-#define PCR_PWM_CLK_EN_S  0
-/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset pwm module
- */
-#define PCR_PWM_RST_EN    (BIT(1))
-#define PCR_PWM_RST_EN_M  (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S)
-#define PCR_PWM_RST_EN_V  0x00000001U
-#define PCR_PWM_RST_EN_S  1
-
-/** PCR_PWM_CLK_CONF_REG register
- *  PWM_CLK configuration register
- */
-#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0)
-/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
- *  The integral part of the frequency divider factor of the pwm function clock.
- */
-#define PCR_PWM_DIV_NUM    0x000000FFU
-#define PCR_PWM_DIV_NUM_M  (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S)
-#define PCR_PWM_DIV_NUM_V  0x000000FFU
-#define PCR_PWM_DIV_NUM_S  12
-/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
- *  160MHz, 2: XTAL, 3: FOSC.
- */
-#define PCR_PWM_CLKM_SEL    0x00000003U
-#define PCR_PWM_CLKM_SEL_M  (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S)
-#define PCR_PWM_CLKM_SEL_V  0x00000003U
-#define PCR_PWM_CLKM_SEL_S  20
-/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  set this field as 1 to activate pwm clkm.
- */
-#define PCR_PWM_CLKM_EN    (BIT(22))
-#define PCR_PWM_CLKM_EN_M  (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S)
-#define PCR_PWM_CLKM_EN_V  0x00000001U
-#define PCR_PWM_CLKM_EN_S  22
-
-/** PCR_PARL_IO_CONF_REG register
- *  PARL_IO configuration register
- */
-#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4)
-/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable parl apb clock
- */
-#define PCR_PARL_CLK_EN    (BIT(0))
-#define PCR_PARL_CLK_EN_M  (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S)
-#define PCR_PARL_CLK_EN_V  0x00000001U
-#define PCR_PARL_CLK_EN_S  0
-/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset parl apb reg
- */
-#define PCR_PARL_RST_EN    (BIT(1))
-#define PCR_PARL_RST_EN_M  (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S)
-#define PCR_PARL_RST_EN_V  0x00000001U
-#define PCR_PARL_RST_EN_S  1
-
-/** PCR_PARL_CLK_RX_CONF_REG register
- *  PARL_CLK_RX configuration register
- */
-#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8)
-/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
- *  The integral part of the frequency divider factor of the parl rx clock.
- */
-#define PCR_PARL_CLK_RX_DIV_NUM    0x0000FFFFU
-#define PCR_PARL_CLK_RX_DIV_NUM_M  (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S)
-#define PCR_PARL_CLK_RX_DIV_NUM_V  0x0000FFFFU
-#define PCR_PARL_CLK_RX_DIV_NUM_S  0
-/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  user clock from pad.
- */
-#define PCR_PARL_CLK_RX_SEL    0x00000003U
-#define PCR_PARL_CLK_RX_SEL_M  (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S)
-#define PCR_PARL_CLK_RX_SEL_V  0x00000003U
-#define PCR_PARL_CLK_RX_SEL_S  16
-/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1;
- *  Set 1 to enable parl rx clock
- */
-#define PCR_PARL_CLK_RX_EN    (BIT(18))
-#define PCR_PARL_CLK_RX_EN_M  (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S)
-#define PCR_PARL_CLK_RX_EN_V  0x00000001U
-#define PCR_PARL_CLK_RX_EN_S  18
-/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0;
- *  Set 0 to reset parl rx module
- */
-#define PCR_PARL_RX_RST_EN    (BIT(19))
-#define PCR_PARL_RX_RST_EN_M  (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S)
-#define PCR_PARL_RX_RST_EN_V  0x00000001U
-#define PCR_PARL_RX_RST_EN_S  19
-
-/** PCR_PARL_CLK_TX_CONF_REG register
- *  PARL_CLK_TX configuration register
- */
-#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac)
-/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
- *  The integral part of the frequency divider factor of the parl tx clock.
- */
-#define PCR_PARL_CLK_TX_DIV_NUM    0x0000FFFFU
-#define PCR_PARL_CLK_TX_DIV_NUM_M  (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S)
-#define PCR_PARL_CLK_TX_DIV_NUM_V  0x0000FFFFU
-#define PCR_PARL_CLK_TX_DIV_NUM_S  0
-/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  user clock from pad.
- */
-#define PCR_PARL_CLK_TX_SEL    0x00000003U
-#define PCR_PARL_CLK_TX_SEL_M  (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S)
-#define PCR_PARL_CLK_TX_SEL_V  0x00000003U
-#define PCR_PARL_CLK_TX_SEL_S  16
-/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1;
- *  Set 1 to enable parl tx clock
- */
-#define PCR_PARL_CLK_TX_EN    (BIT(18))
-#define PCR_PARL_CLK_TX_EN_M  (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S)
-#define PCR_PARL_CLK_TX_EN_V  0x00000001U
-#define PCR_PARL_CLK_TX_EN_S  18
-/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0;
- *  Set 0 to reset parl tx module
- */
-#define PCR_PARL_TX_RST_EN    (BIT(19))
-#define PCR_PARL_TX_RST_EN_M  (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S)
-#define PCR_PARL_TX_RST_EN_V  0x00000001U
-#define PCR_PARL_TX_RST_EN_S  19
-
-/** PCR_SDIO_SLAVE_CONF_REG register
- *  SDIO_SLAVE configuration register
- */
-#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0)
-/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable sdio_slave clock
- */
-#define PCR_SDIO_SLAVE_CLK_EN    (BIT(0))
-#define PCR_SDIO_SLAVE_CLK_EN_M  (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S)
-#define PCR_SDIO_SLAVE_CLK_EN_V  0x00000001U
-#define PCR_SDIO_SLAVE_CLK_EN_S  0
-/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset sdio_slave module
- */
-#define PCR_SDIO_SLAVE_RST_EN    (BIT(1))
-#define PCR_SDIO_SLAVE_RST_EN_M  (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S)
-#define PCR_SDIO_SLAVE_RST_EN_V  0x00000001U
-#define PCR_SDIO_SLAVE_RST_EN_S  1
-
-/** PCR_PVT_MONITOR_CONF_REG register
- *  PVT_MONITOR configuration register
- */
-#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4)
-/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable apb clock of pvt module
- */
-#define PCR_PVT_MONITOR_CLK_EN    (BIT(0))
-#define PCR_PVT_MONITOR_CLK_EN_M  (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S)
-#define PCR_PVT_MONITOR_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_CLK_EN_S  0
-/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset all pvt monitor module
- */
-#define PCR_PVT_MONITOR_RST_EN    (BIT(1))
-#define PCR_PVT_MONITOR_RST_EN_M  (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S)
-#define PCR_PVT_MONITOR_RST_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_RST_EN_S  1
-/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable function clock of modem pvt module
- */
-#define PCR_PVT_MONITOR_SITE1_CLK_EN    (BIT(2))
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_M  (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_S  2
-/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  Set 1 to enable function clock of cpu pvt module
- */
-#define PCR_PVT_MONITOR_SITE2_CLK_EN    (BIT(3))
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_M  (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_S  3
-/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  Set 1 to enable function clock of hp_peri pvt module
- */
-#define PCR_PVT_MONITOR_SITE3_CLK_EN    (BIT(4))
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_M  (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_S  4
-
-/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register
- *  PVT_MONITOR function clock configuration register
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8)
-/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0;
- *  The integral part of the frequency divider factor of the pvt_monitor function clock.
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM    0x0000000FU
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M  (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
-/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
- *  divided by 3.
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M  (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S  20
-/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable source clock of pvt sitex
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_EN    (BIT(22))
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_M  (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_S  22
-
-/** PCR_GDMA_CONF_REG register
- *  GDMA configuration register
- */
-#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc)
-/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable gdma clock
- */
-#define PCR_GDMA_CLK_EN    (BIT(0))
-#define PCR_GDMA_CLK_EN_M  (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S)
-#define PCR_GDMA_CLK_EN_V  0x00000001U
-#define PCR_GDMA_CLK_EN_S  0
-/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset gdma module
- */
-#define PCR_GDMA_RST_EN    (BIT(1))
-#define PCR_GDMA_RST_EN_M  (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
-#define PCR_GDMA_RST_EN_V  0x00000001U
-#define PCR_GDMA_RST_EN_S  1
-
-/** PCR_SPI2_CONF_REG register
- *  SPI2 configuration register
- */
-#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0)
-/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable spi2 apb clock
- */
-#define PCR_SPI2_CLK_EN    (BIT(0))
-#define PCR_SPI2_CLK_EN_M  (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S)
-#define PCR_SPI2_CLK_EN_V  0x00000001U
-#define PCR_SPI2_CLK_EN_S  0
-/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset spi2 module
- */
-#define PCR_SPI2_RST_EN    (BIT(1))
-#define PCR_SPI2_RST_EN_M  (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
-#define PCR_SPI2_RST_EN_V  0x00000001U
-#define PCR_SPI2_RST_EN_S  1
-
-/** PCR_SPI2_CLKM_CONF_REG register
- *  SPI2_CLKM configuration register
- */
-#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4)
-/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_SPI2_CLKM_SEL    0x00000003U
-#define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
-#define PCR_SPI2_CLKM_SEL_V  0x00000003U
-#define PCR_SPI2_CLKM_SEL_S  20
-/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable spi2 function clock
- */
-#define PCR_SPI2_CLKM_EN    (BIT(22))
-#define PCR_SPI2_CLKM_EN_M  (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S)
-#define PCR_SPI2_CLKM_EN_V  0x00000001U
-#define PCR_SPI2_CLKM_EN_S  22
-
-/** PCR_AES_CONF_REG register
- *  AES configuration register
- */
-#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8)
-/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable aes clock
- */
-#define PCR_AES_CLK_EN    (BIT(0))
-#define PCR_AES_CLK_EN_M  (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
-#define PCR_AES_CLK_EN_V  0x00000001U
-#define PCR_AES_CLK_EN_S  0
-/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset aes module
- */
-#define PCR_AES_RST_EN    (BIT(1))
-#define PCR_AES_RST_EN_M  (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
-#define PCR_AES_RST_EN_V  0x00000001U
-#define PCR_AES_RST_EN_S  1
-
-/** PCR_SHA_CONF_REG register
- *  SHA configuration register
- */
-#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc)
-/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable sha clock
- */
-#define PCR_SHA_CLK_EN    (BIT(0))
-#define PCR_SHA_CLK_EN_M  (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S)
-#define PCR_SHA_CLK_EN_V  0x00000001U
-#define PCR_SHA_CLK_EN_S  0
-/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset sha module
- */
-#define PCR_SHA_RST_EN    (BIT(1))
-#define PCR_SHA_RST_EN_M  (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
-#define PCR_SHA_RST_EN_V  0x00000001U
-#define PCR_SHA_RST_EN_S  1
-
-/** PCR_RSA_CONF_REG register
- *  RSA configuration register
- */
-#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0)
-/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable rsa clock
- */
-#define PCR_RSA_CLK_EN    (BIT(0))
-#define PCR_RSA_CLK_EN_M  (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
-#define PCR_RSA_CLK_EN_V  0x00000001U
-#define PCR_RSA_CLK_EN_S  0
-/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset rsa module
- */
-#define PCR_RSA_RST_EN    (BIT(1))
-#define PCR_RSA_RST_EN_M  (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
-#define PCR_RSA_RST_EN_V  0x00000001U
-#define PCR_RSA_RST_EN_S  1
-
-/** PCR_RSA_PD_CTRL_REG register
- *  RSA power control register
- */
-#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4)
-/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down rsa internal memory.
- */
-#define PCR_RSA_MEM_PD    (BIT(0))
-#define PCR_RSA_MEM_PD_M  (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
-#define PCR_RSA_MEM_PD_V  0x00000001U
-#define PCR_RSA_MEM_PD_S  0
-/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up rsa internal memory
- */
-#define PCR_RSA_MEM_FORCE_PU    (BIT(1))
-#define PCR_RSA_MEM_FORCE_PU_M  (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
-#define PCR_RSA_MEM_FORCE_PU_V  0x00000001U
-#define PCR_RSA_MEM_FORCE_PU_S  1
-/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down rsa internal memory.
- */
-#define PCR_RSA_MEM_FORCE_PD    (BIT(2))
-#define PCR_RSA_MEM_FORCE_PD_M  (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
-#define PCR_RSA_MEM_FORCE_PD_V  0x00000001U
-#define PCR_RSA_MEM_FORCE_PD_S  2
-
-/** PCR_ECC_CONF_REG register
- *  ECC configuration register
- */
-#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8)
-/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ecc clock
- */
-#define PCR_ECC_CLK_EN    (BIT(0))
-#define PCR_ECC_CLK_EN_M  (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S)
-#define PCR_ECC_CLK_EN_V  0x00000001U
-#define PCR_ECC_CLK_EN_S  0
-/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ecc module
- */
-#define PCR_ECC_RST_EN    (BIT(1))
-#define PCR_ECC_RST_EN_M  (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
-#define PCR_ECC_RST_EN_V  0x00000001U
-#define PCR_ECC_RST_EN_S  1
-
-/** PCR_ECC_PD_CTRL_REG register
- *  ECC power control register
- */
-#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc)
-/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down ecc internal memory.
- */
-#define PCR_ECC_MEM_PD    (BIT(0))
-#define PCR_ECC_MEM_PD_M  (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S)
-#define PCR_ECC_MEM_PD_V  0x00000001U
-#define PCR_ECC_MEM_PD_S  0
-/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up ecc internal memory
- */
-#define PCR_ECC_MEM_FORCE_PU    (BIT(1))
-#define PCR_ECC_MEM_FORCE_PU_M  (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S)
-#define PCR_ECC_MEM_FORCE_PU_V  0x00000001U
-#define PCR_ECC_MEM_FORCE_PU_S  1
-/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down ecc internal memory.
- */
-#define PCR_ECC_MEM_FORCE_PD    (BIT(2))
-#define PCR_ECC_MEM_FORCE_PD_M  (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S)
-#define PCR_ECC_MEM_FORCE_PD_V  0x00000001U
-#define PCR_ECC_MEM_FORCE_PD_S  2
-
-/** PCR_DS_CONF_REG register
- *  DS configuration register
- */
-#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0)
-/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ds clock
- */
-#define PCR_DS_CLK_EN    (BIT(0))
-#define PCR_DS_CLK_EN_M  (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
-#define PCR_DS_CLK_EN_V  0x00000001U
-#define PCR_DS_CLK_EN_S  0
-/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ds module
- */
-#define PCR_DS_RST_EN    (BIT(1))
-#define PCR_DS_RST_EN_M  (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
-#define PCR_DS_RST_EN_V  0x00000001U
-#define PCR_DS_RST_EN_S  1
-
-/** PCR_HMAC_CONF_REG register
- *  HMAC configuration register
- */
-#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4)
-/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable hmac clock
- */
-#define PCR_HMAC_CLK_EN    (BIT(0))
-#define PCR_HMAC_CLK_EN_M  (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
-#define PCR_HMAC_CLK_EN_V  0x00000001U
-#define PCR_HMAC_CLK_EN_S  0
-/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset hmac module
- */
-#define PCR_HMAC_RST_EN    (BIT(1))
-#define PCR_HMAC_RST_EN_M  (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
-#define PCR_HMAC_RST_EN_V  0x00000001U
-#define PCR_HMAC_RST_EN_S  1
-
-/** PCR_IOMUX_CONF_REG register
- *  IOMUX configuration register
- */
-#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8)
-/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable iomux apb clock
- */
-#define PCR_IOMUX_CLK_EN    (BIT(0))
-#define PCR_IOMUX_CLK_EN_M  (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S)
-#define PCR_IOMUX_CLK_EN_V  0x00000001U
-#define PCR_IOMUX_CLK_EN_S  0
-/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset iomux module
- */
-#define PCR_IOMUX_RST_EN    (BIT(1))
-#define PCR_IOMUX_RST_EN_M  (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
-#define PCR_IOMUX_RST_EN_V  0x00000001U
-#define PCR_IOMUX_RST_EN_S  1
-
-/** PCR_IOMUX_CLK_CONF_REG register
- *  IOMUX_CLK configuration register
- */
-#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec)
-/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_IOMUX_FUNC_CLK_SEL    0x00000003U
-#define PCR_IOMUX_FUNC_CLK_SEL_M  (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
-#define PCR_IOMUX_FUNC_CLK_SEL_V  0x00000003U
-#define PCR_IOMUX_FUNC_CLK_SEL_S  20
-/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable iomux function clock
- */
-#define PCR_IOMUX_FUNC_CLK_EN    (BIT(22))
-#define PCR_IOMUX_FUNC_CLK_EN_M  (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S)
-#define PCR_IOMUX_FUNC_CLK_EN_V  0x00000001U
-#define PCR_IOMUX_FUNC_CLK_EN_S  22
-
-/** PCR_MEM_MONITOR_CONF_REG register
- *  MEM_MONITOR configuration register
- */
-#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0)
-/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable mem_monitor clock
- */
-#define PCR_MEM_MONITOR_CLK_EN    (BIT(0))
-#define PCR_MEM_MONITOR_CLK_EN_M  (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S)
-#define PCR_MEM_MONITOR_CLK_EN_V  0x00000001U
-#define PCR_MEM_MONITOR_CLK_EN_S  0
-/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset mem_monitor module
- */
-#define PCR_MEM_MONITOR_RST_EN    (BIT(1))
-#define PCR_MEM_MONITOR_RST_EN_M  (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S)
-#define PCR_MEM_MONITOR_RST_EN_V  0x00000001U
-#define PCR_MEM_MONITOR_RST_EN_S  1
-
-/** PCR_REGDMA_CONF_REG register
- *  REGDMA configuration register
- */
-#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4)
-/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable regdma clock
- */
-#define PCR_REGDMA_CLK_EN    (BIT(0))
-#define PCR_REGDMA_CLK_EN_M  (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S)
-#define PCR_REGDMA_CLK_EN_V  0x00000001U
-#define PCR_REGDMA_CLK_EN_S  0
-/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset regdma module
- */
-#define PCR_REGDMA_RST_EN    (BIT(1))
-#define PCR_REGDMA_RST_EN_M  (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
-#define PCR_REGDMA_RST_EN_V  0x00000001U
-#define PCR_REGDMA_RST_EN_S  1
-
-/** PCR_RETENTION_CONF_REG register
- *  retention configuration register
- */
-#define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8)
-/** PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable retention clock
- */
-#define PCR_RETENTION_CLK_EN    (BIT(0))
-#define PCR_RETENTION_CLK_EN_M  (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S)
-#define PCR_RETENTION_CLK_EN_V  0x00000001U
-#define PCR_RETENTION_CLK_EN_S  0
-/** PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset retention module
- */
-#define PCR_RETENTION_RST_EN    (BIT(1))
-#define PCR_RETENTION_RST_EN_M  (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S)
-#define PCR_RETENTION_RST_EN_V  0x00000001U
-#define PCR_RETENTION_RST_EN_S  1
-
-/** PCR_TRACE_CONF_REG register
- *  TRACE configuration register
- */
-#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc)
-/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable trace clock
- */
-#define PCR_TRACE_CLK_EN    (BIT(0))
-#define PCR_TRACE_CLK_EN_M  (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S)
-#define PCR_TRACE_CLK_EN_V  0x00000001U
-#define PCR_TRACE_CLK_EN_S  0
-/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset trace module
- */
-#define PCR_TRACE_RST_EN    (BIT(1))
-#define PCR_TRACE_RST_EN_M  (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
-#define PCR_TRACE_RST_EN_V  0x00000001U
-#define PCR_TRACE_RST_EN_S  1
-
-/** PCR_ASSIST_CONF_REG register
- *  ASSIST configuration register
- */
-#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100)
-/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable assist clock
- */
-#define PCR_ASSIST_CLK_EN    (BIT(0))
-#define PCR_ASSIST_CLK_EN_M  (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S)
-#define PCR_ASSIST_CLK_EN_V  0x00000001U
-#define PCR_ASSIST_CLK_EN_S  0
-/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset assist module
- */
-#define PCR_ASSIST_RST_EN    (BIT(1))
-#define PCR_ASSIST_RST_EN_M  (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
-#define PCR_ASSIST_RST_EN_V  0x00000001U
-#define PCR_ASSIST_RST_EN_S  1
-
-/** PCR_CACHE_CONF_REG register
- *  CACHE configuration register
- */
-#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104)
-/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable cache clock
- */
-#define PCR_CACHE_CLK_EN    (BIT(0))
-#define PCR_CACHE_CLK_EN_M  (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S)
-#define PCR_CACHE_CLK_EN_V  0x00000001U
-#define PCR_CACHE_CLK_EN_S  0
-/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset cache module
- */
-#define PCR_CACHE_RST_EN    (BIT(1))
-#define PCR_CACHE_RST_EN_M  (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
-#define PCR_CACHE_RST_EN_V  0x00000001U
-#define PCR_CACHE_RST_EN_S  1
-
-/** PCR_MODEM_APB_CONF_REG register
- *  MODEM_APB configuration register
- */
-#define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108)
-/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).
- */
-#define PCR_MODEM_APB_CLK_EN    (BIT(0))
-#define PCR_MODEM_APB_CLK_EN_M  (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S)
-#define PCR_MODEM_APB_CLK_EN_V  0x00000001U
-#define PCR_MODEM_APB_CLK_EN_S  0
-/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set this file as 1 to reset modem-subsystem.
- */
-#define PCR_MODEM_RST_EN    (BIT(1))
-#define PCR_MODEM_RST_EN_M  (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S)
-#define PCR_MODEM_RST_EN_V  0x00000001U
-#define PCR_MODEM_RST_EN_S  1
-
-/** PCR_TIMEOUT_CONF_REG register
- *  TIMEOUT configuration register
- */
-#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c)
-/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset cpu_peri timeout module
- */
-#define PCR_CPU_TIMEOUT_RST_EN    (BIT(1))
-#define PCR_CPU_TIMEOUT_RST_EN_M  (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
-#define PCR_CPU_TIMEOUT_RST_EN_V  0x00000001U
-#define PCR_CPU_TIMEOUT_RST_EN_S  1
-/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
- *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
- */
-#define PCR_HP_TIMEOUT_RST_EN    (BIT(2))
-#define PCR_HP_TIMEOUT_RST_EN_M  (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
-#define PCR_HP_TIMEOUT_RST_EN_V  0x00000001U
-#define PCR_HP_TIMEOUT_RST_EN_S  2
-
-/** PCR_SYSCLK_CONF_REG register
- *  SYSCLK configuration register
- */
-#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110)
-/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
- *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
- *  clock-source such as XTAL/FOSC.
- */
-#define PCR_LS_DIV_NUM    0x000000FFU
-#define PCR_LS_DIV_NUM_M  (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
-#define PCR_LS_DIV_NUM_V  0x000000FFU
-#define PCR_LS_DIV_NUM_S  0
-/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
- *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
- */
-#define PCR_HS_DIV_NUM    0x000000FFU
-#define PCR_HS_DIV_NUM_M  (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
-#define PCR_HS_DIV_NUM_V  0x000000FFU
-#define PCR_HS_DIV_NUM_S  8
-/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
- *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
- */
-#define PCR_SOC_CLK_SEL    0x00000003U
-#define PCR_SOC_CLK_SEL_M  (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
-#define PCR_SOC_CLK_SEL_V  0x00000003U
-#define PCR_SOC_CLK_SEL_S  16
-/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40;
- *  This field indicates the frequency(MHz) of XTAL.
- */
-#define PCR_CLK_XTAL_FREQ    0x0000007FU
-#define PCR_CLK_XTAL_FREQ_M  (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S)
-#define PCR_CLK_XTAL_FREQ_V  0x0000007FU
-#define PCR_CLK_XTAL_FREQ_S  24
-
-/** PCR_CPU_WAITI_CONF_REG register
- *  CPU_WAITI configuration register
- */
-#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114)
-/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
- *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
- */
-#define PCR_CPUPERIOD_SEL    0x00000003U
-#define PCR_CPUPERIOD_SEL_M  (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
-#define PCR_CPUPERIOD_SEL_V  0x00000003U
-#define PCR_CPUPERIOD_SEL_S  0
-/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
- *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
- */
-#define PCR_PLL_FREQ_SEL    (BIT(2))
-#define PCR_PLL_FREQ_SEL_M  (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
-#define PCR_PLL_FREQ_SEL_V  0x00000001U
-#define PCR_PLL_FREQ_SEL_S  2
-/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
- *  Set 1 to force cpu_waiti_clk enable.
- */
-#define PCR_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
-#define PCR_CPU_WAIT_MODE_FORCE_ON_M  (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S)
-#define PCR_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
-#define PCR_CPU_WAIT_MODE_FORCE_ON_S  3
-/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
- *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
- *  will close
- */
-#define PCR_CPU_WAITI_DELAY_NUM    0x0000000FU
-#define PCR_CPU_WAITI_DELAY_NUM_M  (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S)
-#define PCR_CPU_WAITI_DELAY_NUM_V  0x0000000FU
-#define PCR_CPU_WAITI_DELAY_NUM_S  4
-
-/** PCR_CPU_FREQ_CONF_REG register
- *  CPU_FREQ configuration register
- */
-#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
-/** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
- *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
- */
-#define PCR_CPU_LS_DIV_NUM    0x000000FFU
-#define PCR_CPU_LS_DIV_NUM_M  (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S)
-#define PCR_CPU_LS_DIV_NUM_V  0x000000FFU
-#define PCR_CPU_LS_DIV_NUM_S  0
-/** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed
- *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
- */
-#define PCR_CPU_HS_DIV_NUM    0x000000FFU
-#define PCR_CPU_HS_DIV_NUM_M  (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S)
-#define PCR_CPU_HS_DIV_NUM_V  0x000000FFU
-#define PCR_CPU_HS_DIV_NUM_S  8
-/** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0;
- *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
- *  Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
- */
-#define PCR_CPU_HS_120M_FORCE    (BIT(16))
-#define PCR_CPU_HS_120M_FORCE_M  (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S)
-#define PCR_CPU_HS_120M_FORCE_V  0x00000001U
-#define PCR_CPU_HS_120M_FORCE_S  16
-
-/** PCR_AHB_FREQ_CONF_REG register
- *  AHB_FREQ configuration register
- */
-#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
-/** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb
- *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
- *  low-speed clock-source such as XTAL/FOSC, and should be used together with
- *  PCR_CPU_LS_DIV_NUM.
- */
-#define PCR_AHB_LS_DIV_NUM    0x000000FFU
-#define PCR_AHB_LS_DIV_NUM_M  (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S)
-#define PCR_AHB_LS_DIV_NUM_V  0x000000FFU
-#define PCR_AHB_LS_DIV_NUM_S  0
-/** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
- *  Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is
- *  div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed
- *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
- */
-#define PCR_AHB_HS_DIV_NUM    0x000000FFU
-#define PCR_AHB_HS_DIV_NUM_M  (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S)
-#define PCR_AHB_HS_DIV_NUM_V  0x000000FFU
-#define PCR_AHB_HS_DIV_NUM_S  8
-
-/** PCR_APB_FREQ_CONF_REG register
- *  APB_FREQ configuration register
- */
-#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120)
-/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
- *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
- *  recover to the previous frequency when a new access appears on apb-bus. Set as one
- *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
- *  that enable this function will reduce performance. Users can set this field as zero
- *  to disable the auto-decrease-apb-freq function. By default, this function is
- *  disable.
- */
-#define PCR_APB_DECREASE_DIV_NUM    0x000000FFU
-#define PCR_APB_DECREASE_DIV_NUM_M  (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S)
-#define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
-#define PCR_APB_DECREASE_DIV_NUM_S  0
-/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
- *  div1(default)/div2/div4 of clk_ahb.
- */
-#define PCR_APB_DIV_NUM    0x000000FFU
-#define PCR_APB_DIV_NUM_M  (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S)
-#define PCR_APB_DIV_NUM_V  0x000000FFU
-#define PCR_APB_DIV_NUM_S  8
-
-/** PCR_SYSCLK_FREQ_QUERY_0_REG register
- *  SYSCLK frequency query 0 register
- */
-#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124)
-/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20;
- *  This field indicates the frequency(MHz) of FOSC.
- */
-#define PCR_FOSC_FREQ    0x000000FFU
-#define PCR_FOSC_FREQ_M  (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S)
-#define PCR_FOSC_FREQ_V  0x000000FFU
-#define PCR_FOSC_FREQ_S  0
-/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480;
- *  This field indicates the frequency(MHz) of SPLL.
- */
-#define PCR_PLL_FREQ    0x000003FFU
-#define PCR_PLL_FREQ_M  (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S)
-#define PCR_PLL_FREQ_V  0x000003FFU
-#define PCR_PLL_FREQ_S  8
-
-/** PCR_PLL_DIV_CLK_EN_REG register
- *  SPLL DIV clock-gating configuration register
- */
-#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128)
-/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_240M_CLK_EN    (BIT(0))
-#define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
-#define PCR_PLL_240M_CLK_EN_V  0x00000001U
-#define PCR_PLL_240M_CLK_EN_S  0
-/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_160M_CLK_EN    (BIT(1))
-#define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
-#define PCR_PLL_160M_CLK_EN_V  0x00000001U
-#define PCR_PLL_160M_CLK_EN_S  1
-/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_120M_CLK_EN    (BIT(2))
-#define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
-#define PCR_PLL_120M_CLK_EN_V  0x00000001U
-#define PCR_PLL_120M_CLK_EN_S  2
-/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_80M_CLK_EN    (BIT(3))
-#define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
-#define PCR_PLL_80M_CLK_EN_V  0x00000001U
-#define PCR_PLL_80M_CLK_EN_S  3
-/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_48M_CLK_EN    (BIT(4))
-#define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
-#define PCR_PLL_48M_CLK_EN_V  0x00000001U
-#define PCR_PLL_48M_CLK_EN_S  4
-/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_40M_CLK_EN    (BIT(5))
-#define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
-#define PCR_PLL_40M_CLK_EN_V  0x00000001U
-#define PCR_PLL_40M_CLK_EN_S  5
-/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1;
- *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_20M_CLK_EN    (BIT(6))
-#define PCR_PLL_20M_CLK_EN_M  (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)
-#define PCR_PLL_20M_CLK_EN_V  0x00000001U
-#define PCR_PLL_20M_CLK_EN_S  6
-
-/** PCR_CTRL_CLK_OUT_EN_REG register
- *  CLK_OUT_EN configuration register
- */
-#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c)
-/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable 20m clock
- */
-#define PCR_CLK20_OEN    (BIT(0))
-#define PCR_CLK20_OEN_M  (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S)
-#define PCR_CLK20_OEN_V  0x00000001U
-#define PCR_CLK20_OEN_S  0
-/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1;
- *  Set 1 to enable 22m clock
- */
-#define PCR_CLK22_OEN    (BIT(1))
-#define PCR_CLK22_OEN_M  (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S)
-#define PCR_CLK22_OEN_V  0x00000001U
-#define PCR_CLK22_OEN_S  1
-/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable 44m clock
- */
-#define PCR_CLK44_OEN    (BIT(2))
-#define PCR_CLK44_OEN_M  (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S)
-#define PCR_CLK44_OEN_V  0x00000001U
-#define PCR_CLK44_OEN_S  2
-/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1;
- *  Set 1 to enable bb clock
- */
-#define PCR_CLK_BB_OEN    (BIT(3))
-#define PCR_CLK_BB_OEN_M  (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S)
-#define PCR_CLK_BB_OEN_V  0x00000001U
-#define PCR_CLK_BB_OEN_S  3
-/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1;
- *  Set 1 to enable 80m clock
- */
-#define PCR_CLK80_OEN    (BIT(4))
-#define PCR_CLK80_OEN_M  (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S)
-#define PCR_CLK80_OEN_V  0x00000001U
-#define PCR_CLK80_OEN_S  4
-/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1;
- *  Set 1 to enable 160m clock
- */
-#define PCR_CLK160_OEN    (BIT(5))
-#define PCR_CLK160_OEN_M  (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S)
-#define PCR_CLK160_OEN_V  0x00000001U
-#define PCR_CLK160_OEN_S  5
-/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1;
- *  Set 1 to enable 320m clock
- */
-#define PCR_CLK_320M_OEN    (BIT(6))
-#define PCR_CLK_320M_OEN_M  (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S)
-#define PCR_CLK_320M_OEN_V  0x00000001U
-#define PCR_CLK_320M_OEN_S  6
-/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_ADC_INF_OEN    (BIT(7))
-#define PCR_CLK_ADC_INF_OEN_M  (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S)
-#define PCR_CLK_ADC_INF_OEN_V  0x00000001U
-#define PCR_CLK_ADC_INF_OEN_S  7
-/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_DAC_CPU_OEN    (BIT(8))
-#define PCR_CLK_DAC_CPU_OEN_M  (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S)
-#define PCR_CLK_DAC_CPU_OEN_V  0x00000001U
-#define PCR_CLK_DAC_CPU_OEN_S  8
-/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1;
- *  Set 1 to enable 40x_bb clock
- */
-#define PCR_CLK40X_BB_OEN    (BIT(9))
-#define PCR_CLK40X_BB_OEN_M  (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S)
-#define PCR_CLK40X_BB_OEN_V  0x00000001U
-#define PCR_CLK40X_BB_OEN_S  9
-/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1;
- *  Set 1 to enable xtal clock
- */
-#define PCR_CLK_XTAL_OEN    (BIT(10))
-#define PCR_CLK_XTAL_OEN_M  (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S)
-#define PCR_CLK_XTAL_OEN_V  0x00000001U
-#define PCR_CLK_XTAL_OEN_S  10
-
-/** PCR_CTRL_TICK_CONF_REG register
- *  TICK configuration register
- */
-#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130)
-/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39;
- *  ******* Description ***********
- */
-#define PCR_XTAL_TICK_NUM    0x000000FFU
-#define PCR_XTAL_TICK_NUM_M  (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S)
-#define PCR_XTAL_TICK_NUM_V  0x000000FFU
-#define PCR_XTAL_TICK_NUM_S  0
-/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7;
- *  ******* Description ***********
- */
-#define PCR_FOSC_TICK_NUM    0x000000FFU
-#define PCR_FOSC_TICK_NUM_M  (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S)
-#define PCR_FOSC_TICK_NUM_V  0x000000FFU
-#define PCR_FOSC_TICK_NUM_S  8
-/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1;
- *  ******* Description ***********
- */
-#define PCR_TICK_ENABLE    (BIT(16))
-#define PCR_TICK_ENABLE_M  (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S)
-#define PCR_TICK_ENABLE_V  0x00000001U
-#define PCR_TICK_ENABLE_S  16
-/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0;
- *  ******* Description ***********
- */
-#define PCR_RST_TICK_CNT    (BIT(17))
-#define PCR_RST_TICK_CNT_M  (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S)
-#define PCR_RST_TICK_CNT_V  0x00000001U
-#define PCR_RST_TICK_CNT_S  17
-
-/** PCR_CTRL_32K_CONF_REG register
- *  32KHz clock configuration register
- */
-#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134)
-/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0;
- *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and
- *  timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
- */
-#define PCR_32K_SEL    0x00000003U
-#define PCR_32K_SEL_M  (PCR_32K_SEL_V << PCR_32K_SEL_S)
-#define PCR_32K_SEL_V  0x00000003U
-#define PCR_32K_SEL_S  0
-
-/** PCR_SRAM_POWER_CONF_REG register
- *  HP SRAM/ROM configuration register
- */
-#define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138)
-/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15;
- *  Set this bit to force power up SRAM
- */
-#define PCR_SRAM_FORCE_PU    0x0000000FU
-#define PCR_SRAM_FORCE_PU_M  (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S)
-#define PCR_SRAM_FORCE_PU_V  0x0000000FU
-#define PCR_SRAM_FORCE_PU_S  0
-/** PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0;
- *  Set this bit to force power down SRAM.
- */
-#define PCR_SRAM_FORCE_PD    0x0000000FU
-#define PCR_SRAM_FORCE_PD_M  (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S)
-#define PCR_SRAM_FORCE_PD_V  0x0000000FU
-#define PCR_SRAM_FORCE_PD_S  4
-/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0;
- *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
- *  gate-clock will be used when accessing the SRAM.
- */
-#define PCR_SRAM_CLKGATE_FORCE_ON    0x0000000FU
-#define PCR_SRAM_CLKGATE_FORCE_ON_M  (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S)
-#define PCR_SRAM_CLKGATE_FORCE_ON_V  0x0000000FU
-#define PCR_SRAM_CLKGATE_FORCE_ON_S  8
-/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7;
- *  Set this bit to force power up ROM
- */
-#define PCR_ROM_FORCE_PU    0x00000007U
-#define PCR_ROM_FORCE_PU_M  (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S)
-#define PCR_ROM_FORCE_PU_V  0x00000007U
-#define PCR_ROM_FORCE_PU_S  12
-/** PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0;
- *  Set this bit to force power down ROM.
- */
-#define PCR_ROM_FORCE_PD    0x00000007U
-#define PCR_ROM_FORCE_PD_M  (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S)
-#define PCR_ROM_FORCE_PD_V  0x00000007U
-#define PCR_ROM_FORCE_PD_S  15
-/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0;
- *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
- *  gate-clock will be used when accessing the ROM.
- */
-#define PCR_ROM_CLKGATE_FORCE_ON    0x00000007U
-#define PCR_ROM_CLKGATE_FORCE_ON_M  (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S)
-#define PCR_ROM_CLKGATE_FORCE_ON_V  0x00000007U
-#define PCR_ROM_CLKGATE_FORCE_ON_S  18
-
-/** PCR_RESET_EVENT_BYPASS_REG register
- *  reset event bypass backdoor configuration register
- */
-#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0)
-/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0;
- *  This field is used to control reset event relationship for
- *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
- *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
- *  will not only be reset by power-reset, but also some reset event.
- */
-#define PCR_RESET_EVENT_BYPASS_APM    (BIT(0))
-#define PCR_RESET_EVENT_BYPASS_APM_M  (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S)
-#define PCR_RESET_EVENT_BYPASS_APM_V  0x00000001U
-#define PCR_RESET_EVENT_BYPASS_APM_S  0
-/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1;
- *  This field is used to control reset event relationship for system-bus. 1: system
- *  bus (including arbiter/router) will only be reset by power-reset. some reset event
- *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
- *  power-reset, but also some reset event.
- */
-#define PCR_RESET_EVENT_BYPASS    (BIT(1))
-#define PCR_RESET_EVENT_BYPASS_M  (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S)
-#define PCR_RESET_EVENT_BYPASS_V  0x00000001U
-#define PCR_RESET_EVENT_BYPASS_S  1
-
-/** PCR_FPGA_DEBUG_REG register
- *  fpga debug register
- */
-#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
-/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
- *  Only used in fpga debug.
- */
-#define PCR_FPGA_DEBUG    0xFFFFFFFFU
-#define PCR_FPGA_DEBUG_M  (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
-#define PCR_FPGA_DEBUG_V  0xFFFFFFFFU
-#define PCR_FPGA_DEBUG_S  0
-
-/** PCR_CLOCK_GATE_REG register
- *  PCR clock gating configure register
- */
-#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
-/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to force on clock gating.
- */
-#define PCR_CLK_EN    (BIT(0))
-#define PCR_CLK_EN_M  (PCR_CLK_EN_V << PCR_CLK_EN_S)
-#define PCR_CLK_EN_V  0x00000001U
-#define PCR_CLK_EN_S  0
-
-/** PCR_DATE_REG register
- *  Date register.
- */
-#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
-/** PCR_DATE : R/W; bitpos: [27:0]; default: 35676496;
- *  PCR version information.
- */
-#define PCR_DATE    0x0FFFFFFFU
-#define PCR_DATE_M  (PCR_DATE_V << PCR_DATE_S)
-#define PCR_DATE_V  0x0FFFFFFFU
-#define PCR_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/pcr_struct.h b/components/soc/esp32c6/include/soc/pcr_struct.h
deleted file mode 100644
index f31e632d865..00000000000
--- a/components/soc/esp32c6/include/soc/pcr_struct.h
+++ /dev/null
@@ -1,1932 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of uart0_conf register
- *  UART0 configuration register
- */
-typedef union {
-    struct {
-        /** uart0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uart0 apb clock
-         */
-        uint32_t uart0_clk_en:1;
-        /** uart0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uart0 module
-         */
-        uint32_t uart0_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_uart0_conf_reg_t;
-
-/** Type of uart0_sclk_conf register
- *  UART0_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_a:6;
-        /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_b:6;
-        /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_num:8;
-        /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
-         *  FOSC, 3(default): XTAL.
-         */
-        uint32_t uart0_sclk_sel:2;
-        /** uart0_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable uart0 function clock
-         */
-        uint32_t uart0_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_uart0_sclk_conf_reg_t;
-
-/** Type of uart0_pd_ctrl register
- *  UART0 power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power down UART0 memory.
-         */
-        uint32_t uart0_mem_force_pu:1;
-        /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power up UART0 memory.
-         */
-        uint32_t uart0_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart0_pd_ctrl_reg_t;
-
-/** Type of uart1_conf register
- *  UART1 configuration register
- */
-typedef union {
-    struct {
-        /** uart1_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uart1 apb clock
-         */
-        uint32_t uart1_clk_en:1;
-        /** uart1_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uart1 module
-         */
-        uint32_t uart1_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_uart1_conf_reg_t;
-
-/** Type of uart1_sclk_conf register
- *  UART1_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_a:6;
-        /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_b:6;
-        /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_num:8;
-        /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
-         *  FOSC, 3(default): XTAL.
-         */
-        uint32_t uart1_sclk_sel:2;
-        /** uart1_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable uart0 function clock
-         */
-        uint32_t uart1_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_uart1_sclk_conf_reg_t;
-
-/** Type of uart1_pd_ctrl register
- *  UART1 power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power down UART1 memory.
-         */
-        uint32_t uart1_mem_force_pu:1;
-        /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power up UART1 memory.
-         */
-        uint32_t uart1_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart1_pd_ctrl_reg_t;
-
-/** Type of mspi_conf register
- *  MSPI configuration register
- */
-typedef union {
-    struct {
-        /** mspi_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable mspi clock, include mspi pll clock
-         */
-        uint32_t mspi_clk_en:1;
-        /** mspi_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset mspi module
-         */
-        uint32_t mspi_rst_en:1;
-        /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable mspi pll clock
-         */
-        uint32_t mspi_pll_clk_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_mspi_conf_reg_t;
-
-/** Type of mspi_clk_conf register
- *  MSPI_CLK configuration register
- */
-typedef union {
-    struct {
-        /** mspi_fast_ls_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
-         *  low-speed clock-source such as XTAL/FOSC.
-         */
-        uint32_t mspi_fast_ls_div_num:8;
-        /** mspi_fast_hs_div_num : R/W; bitpos: [15:8]; default: 3;
-         *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
-         *  high-speed clock-source such as SPLL.
-         */
-        uint32_t mspi_fast_hs_div_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} pcr_mspi_clk_conf_reg_t;
-
-/** Type of i2c_conf register
- *  I2C configuration register
- */
-typedef union {
-    struct {
-        /** i2c_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable i2c apb clock
-         */
-        uint32_t i2c_clk_en:1;
-        /** i2c_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset i2c module
-         */
-        uint32_t i2c_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_i2c_conf_reg_t;
-
-/** Type of i2c_sclk_conf register
- *  I2C_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_a:6;
-        /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_b:6;
-        /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_num:8;
-        /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t i2c_sclk_sel:1;
-        uint32_t reserved_21:1;
-        /** i2c_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2c function clock
-         */
-        uint32_t i2c_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_i2c_sclk_conf_reg_t;
-
-/** Type of uhci_conf register
- *  UHCI configuration register
- */
-typedef union {
-    struct {
-        /** uhci_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uhci clock
-         */
-        uint32_t uhci_clk_en:1;
-        /** uhci_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uhci module
-         */
-        uint32_t uhci_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_uhci_conf_reg_t;
-
-/** Type of rmt_conf register
- *  RMT configuration register
- */
-typedef union {
-    struct {
-        /** rmt_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable rmt apb clock
-         */
-        uint32_t rmt_clk_en:1;
-        /** rmt_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset rmt module
-         */
-        uint32_t rmt_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_rmt_conf_reg_t;
-
-/** Type of rmt_sclk_conf register
- *  RMT_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_a:6;
-        /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_b:6;
-        /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_num:8;
-        /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
-         *  80MHz, 2: FOSC, 3: XTAL.
-         */
-        uint32_t rmt_sclk_sel:2;
-        /** rmt_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable rmt function clock
-         */
-        uint32_t rmt_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_rmt_sclk_conf_reg_t;
-
-/** Type of ledc_conf register
- *  LEDC configuration register
- */
-typedef union {
-    struct {
-        /** ledc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ledc apb clock
-         */
-        uint32_t ledc_clk_en:1;
-        /** ledc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ledc module
-         */
-        uint32_t ledc_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_ledc_conf_reg_t;
-
-/** Type of ledc_sclk_conf register
- *  LEDC_SCLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
-         *  80MHz, 2: FOSC, 3: XTAL.
-         */
-        uint32_t ledc_sclk_sel:2;
-        /** ledc_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable ledc function clock
-         */
-        uint32_t ledc_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_ledc_sclk_conf_reg_t;
-
-/** Type of timergroup0_conf register
- *  TIMERGROUP0 configuration register
- */
-typedef union {
-    struct {
-        /** tg0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable timer_group0 apb clock
-         */
-        uint32_t tg0_clk_en:1;
-        /** tg0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset timer_group0 module
-         */
-        uint32_t tg0_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_timergroup0_conf_reg_t;
-
-/** Type of timergroup0_timer_clk_conf register
- *  TIMERGROUP0_TIMER_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg0_timer_clk_sel:2;
-        /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 timer clock
-         */
-        uint32_t tg0_timer_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup0_timer_clk_conf_reg_t;
-
-/** Type of timergroup0_wdt_clk_conf register
- *  TIMERGROUP0_WDT_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg0_wdt_clk_sel:2;
-        /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 wdt clock
-         */
-        uint32_t tg0_wdt_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup0_wdt_clk_conf_reg_t;
-
-/** Type of timergroup1_conf register
- *  TIMERGROUP1 configuration register
- */
-typedef union {
-    struct {
-        /** tg1_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable timer_group1 apb clock
-         */
-        uint32_t tg1_clk_en:1;
-        /** tg1_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset timer_group1 module
-         */
-        uint32_t tg1_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_timergroup1_conf_reg_t;
-
-/** Type of timergroup1_timer_clk_conf register
- *  TIMERGROUP1_TIMER_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg1_timer_clk_sel:2;
-        /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group1 timer clock
-         */
-        uint32_t tg1_timer_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup1_timer_clk_conf_reg_t;
-
-/** Type of timergroup1_wdt_clk_conf register
- *  TIMERGROUP1_WDT_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg1_wdt_clk_sel:2;
-        /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 wdt clock
-         */
-        uint32_t tg1_wdt_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup1_wdt_clk_conf_reg_t;
-
-/** Type of systimer_conf register
- *  SYSTIMER configuration register
- */
-typedef union {
-    struct {
-        /** systimer_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable systimer apb clock
-         */
-        uint32_t systimer_clk_en:1;
-        /** systimer_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset systimer module
-         */
-        uint32_t systimer_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_systimer_conf_reg_t;
-
-/** Type of systimer_func_clk_conf register
- *  SYSTIMER_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t systimer_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable systimer function clock
-         */
-        uint32_t systimer_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_systimer_func_clk_conf_reg_t;
-
-/** Type of twai0_conf register
- *  TWAI0 configuration register
- */
-typedef union {
-    struct {
-        /** twai0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable twai0 apb clock
-         */
-        uint32_t twai0_clk_en:1;
-        /** twai0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset twai0 module
-         */
-        uint32_t twai0_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_twai0_conf_reg_t;
-
-/** Type of twai0_func_clk_conf register
- *  TWAI0_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t twai0_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable twai0 function clock
-         */
-        uint32_t twai0_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_twai0_func_clk_conf_reg_t;
-
-/** Type of twai1_conf register
- *  TWAI1 configuration register
- */
-typedef union {
-    struct {
-        /** twai1_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable twai1 apb clock
-         */
-        uint32_t twai1_clk_en:1;
-        /** twai1_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset twai1 module
-         */
-        uint32_t twai1_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_twai1_conf_reg_t;
-
-/** Type of twai1_func_clk_conf register
- *  TWAI1_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** twai1_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t twai1_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** twai1_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable twai1 function clock
-         */
-        uint32_t twai1_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_twai1_func_clk_conf_reg_t;
-
-/** Type of i2s_conf register
- *  I2S configuration register
- */
-typedef union {
-    struct {
-        /** i2s_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable i2s apb clock
-         */
-        uint32_t i2s_clk_en:1;
-        /** i2s_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset i2s module
-         */
-        uint32_t i2s_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_i2s_conf_reg_t;
-
-/** Type of i2s_tx_clkm_conf register
- *  I2S_TX_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
-         *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
-         *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
-         *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
-         *  (n+1)-div] + y * (n+1)-div.
-         */
-        uint32_t i2s_tx_clkm_div_num:8;
-        /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
-         *  I2S_MCLK_in.
-         */
-        uint32_t i2s_tx_clkm_sel:2;
-        /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2s_tx function clock
-         */
-        uint32_t i2s_tx_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_i2s_tx_clkm_conf_reg_t;
-
-/** Type of i2s_tx_clkm_div_conf register
- *  I2S_TX_CLKM_DIV configuration register
- */
-typedef union {
-    struct {
-        /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_Z is (a-b).
-         */
-        uint32_t i2s_tx_clkm_div_z:9;
-        /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
-         */
-        uint32_t i2s_tx_clkm_div_y:9;
-        /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
-         *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
-         */
-        uint32_t i2s_tx_clkm_div_x:9;
-        /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_YN1 is 1.
-         */
-        uint32_t i2s_tx_clkm_div_yn1:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_i2s_tx_clkm_div_conf_reg_t;
-
-/** Type of i2s_rx_clkm_conf register
- *  I2S_RX_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
-         *  Integral I2S clock divider value
-         */
-        uint32_t i2s_rx_clkm_div_num:8;
-        /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
-         */
-        uint32_t i2s_rx_clkm_sel:2;
-        /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2s_rx function clock
-         */
-        uint32_t i2s_rx_clkm_en:1;
-        /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0;
-         *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
-         */
-        uint32_t i2s_mclk_sel:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} pcr_i2s_rx_clkm_conf_reg_t;
-
-/** Type of i2s_rx_clkm_div_conf register
- *  I2S_RX_CLKM_DIV configuration register
- */
-typedef union {
-    struct {
-        /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_Z is (a-b).
-         */
-        uint32_t i2s_rx_clkm_div_z:9;
-        /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
-         */
-        uint32_t i2s_rx_clkm_div_y:9;
-        /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
-         *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
-         */
-        uint32_t i2s_rx_clkm_div_x:9;
-        /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_YN1 is 1.
-         */
-        uint32_t i2s_rx_clkm_div_yn1:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_i2s_rx_clkm_div_conf_reg_t;
-
-/** Type of saradc_conf register
- *  SARADC configuration register
- */
-typedef union {
-    struct {
-        /** saradc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  no use
-         */
-        uint32_t saradc_clk_en:1;
-        /** saradc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset function_register of saradc module
-         */
-        uint32_t saradc_rst_en:1;
-        /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable saradc apb clock
-         */
-        uint32_t saradc_reg_clk_en:1;
-        /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0;
-         *  Set 0 to reset apb_register of saradc module
-         */
-        uint32_t saradc_reg_rst_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_saradc_conf_reg_t;
-
-/** Type of saradc_clkm_conf register
- *  SARADC_CLKM configuration register
- */
-typedef union {
-    struct {
-        /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_a:6;
-        /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_b:6;
-        /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4;
-         *  The integral part of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_num:8;
-        /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t saradc_clkm_sel:2;
-        /** saradc_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable saradc function clock
-         */
-        uint32_t saradc_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_saradc_clkm_conf_reg_t;
-
-/** Type of tsens_clk_conf register
- *  TSENS_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tsens_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
-         */
-        uint32_t tsens_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** tsens_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable tsens clock
-         */
-        uint32_t tsens_clk_en:1;
-        /** tsens_rst_en : R/W; bitpos: [23]; default: 0;
-         *  Set 0 to reset tsens module
-         */
-        uint32_t tsens_rst_en:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} pcr_tsens_clk_conf_reg_t;
-
-/** Type of usb_device_conf register
- *  USB_DEVICE configuration register
- */
-typedef union {
-    struct {
-        /** usb_device_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable usb_device clock
-         */
-        uint32_t usb_device_clk_en:1;
-        /** usb_device_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset usb_device module
-         */
-        uint32_t usb_device_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_usb_device_conf_reg_t;
-
-/** Type of intmtx_conf register
- *  INTMTX configuration register
- */
-typedef union {
-    struct {
-        /** intmtx_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable intmtx clock
-         */
-        uint32_t intmtx_clk_en:1;
-        /** intmtx_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset intmtx module
-         */
-        uint32_t intmtx_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_intmtx_conf_reg_t;
-
-/** Type of pcnt_conf register
- *  PCNT configuration register
- */
-typedef union {
-    struct {
-        /** pcnt_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable pcnt clock
-         */
-        uint32_t pcnt_clk_en:1;
-        /** pcnt_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset pcnt module
-         */
-        uint32_t pcnt_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_pcnt_conf_reg_t;
-
-/** Type of etm_conf register
- *  ETM configuration register
- */
-typedef union {
-    struct {
-        /** etm_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable etm clock
-         */
-        uint32_t etm_clk_en:1;
-        /** etm_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset etm module
-         */
-        uint32_t etm_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_etm_conf_reg_t;
-
-/** Type of pwm_conf register
- *  PWM configuration register
- */
-typedef union {
-    struct {
-        /** pwm_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable pwm clock
-         */
-        uint32_t pwm_clk_en:1;
-        /** pwm_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset pwm module
-         */
-        uint32_t pwm_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_pwm_conf_reg_t;
-
-/** Type of pwm_clk_conf register
- *  PWM_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** pwm_div_num : R/W; bitpos: [19:12]; default: 4;
-         *  The integral part of the frequency divider factor of the pwm function clock.
-         */
-        uint32_t pwm_div_num:8;
-        /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
-         *  160MHz, 2: XTAL, 3: FOSC.
-         */
-        uint32_t pwm_clkm_sel:2;
-        /** pwm_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  set this field as 1 to activate pwm clkm.
-         */
-        uint32_t pwm_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_pwm_clk_conf_reg_t;
-
-/** Type of parl_io_conf register
- *  PARL_IO configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable parl apb clock
-         */
-        uint32_t parl_clk_en:1;
-        /** parl_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset parl apb reg
-         */
-        uint32_t parl_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_parl_io_conf_reg_t;
-
-/** Type of parl_clk_rx_conf register
- *  PARL_CLK_RX configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0;
-         *  The integral part of the frequency divider factor of the parl rx clock.
-         */
-        uint32_t parl_clk_rx_div_num:16;
-        /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
-         *  user clock from pad.
-         */
-        uint32_t parl_clk_rx_sel:2;
-        /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1;
-         *  Set 1 to enable parl rx clock
-         */
-        uint32_t parl_clk_rx_en:1;
-        /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0;
-         *  Set 0 to reset parl rx module
-         */
-        uint32_t parl_rx_rst_en:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} pcr_parl_clk_rx_conf_reg_t;
-
-/** Type of parl_clk_tx_conf register
- *  PARL_CLK_TX configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0;
-         *  The integral part of the frequency divider factor of the parl tx clock.
-         */
-        uint32_t parl_clk_tx_div_num:16;
-        /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
-         *  user clock from pad.
-         */
-        uint32_t parl_clk_tx_sel:2;
-        /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1;
-         *  Set 1 to enable parl tx clock
-         */
-        uint32_t parl_clk_tx_en:1;
-        /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0;
-         *  Set 0 to reset parl tx module
-         */
-        uint32_t parl_tx_rst_en:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} pcr_parl_clk_tx_conf_reg_t;
-
-/** Type of sdio_slave_conf register
- *  SDIO_SLAVE configuration register
- */
-typedef union {
-    struct {
-        /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable sdio_slave clock
-         */
-        uint32_t sdio_slave_clk_en:1;
-        /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset sdio_slave module
-         */
-        uint32_t sdio_slave_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_sdio_slave_conf_reg_t;
-
-/** Type of pvt_monitor_conf register
- *  PVT_MONITOR configuration register
- */
-typedef union {
-    struct {
-        /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable apb clock of pvt module
-         */
-        uint32_t pvt_monitor_clk_en:1;
-        /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset all pvt monitor module
-         */
-        uint32_t pvt_monitor_rst_en:1;
-        /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable function clock of modem pvt module
-         */
-        uint32_t pvt_monitor_site1_clk_en:1;
-        /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1;
-         *  Set 1 to enable function clock of cpu pvt module
-         */
-        uint32_t pvt_monitor_site2_clk_en:1;
-        /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1;
-         *  Set 1 to enable function clock of hp_peri pvt module
-         */
-        uint32_t pvt_monitor_site3_clk_en:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} pcr_pvt_monitor_conf_reg_t;
-
-/** Type of pvt_monitor_func_clk_conf register
- *  PVT_MONITOR function clock configuration register
- */
-typedef union {
-    struct {
-        /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0;
-         *  The integral part of the frequency divider factor of the pvt_monitor function clock.
-         */
-        uint32_t pvt_monitor_func_clk_div_num:4;
-        uint32_t reserved_4:16;
-        /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
-         *  divided by 3.
-         */
-        uint32_t pvt_monitor_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable source clock of pvt sitex
-         */
-        uint32_t pvt_monitor_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_pvt_monitor_func_clk_conf_reg_t;
-
-/** Type of gdma_conf register
- *  GDMA configuration register
- */
-typedef union {
-    struct {
-        /** gdma_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable gdma clock
-         */
-        uint32_t gdma_clk_en:1;
-        /** gdma_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset gdma module
-         */
-        uint32_t gdma_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_gdma_conf_reg_t;
-
-/** Type of spi2_conf register
- *  SPI2 configuration register
- */
-typedef union {
-    struct {
-        /** spi2_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable spi2 apb clock
-         */
-        uint32_t spi2_clk_en:1;
-        /** spi2_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset spi2 module
-         */
-        uint32_t spi2_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_spi2_conf_reg_t;
-
-/** Type of spi2_clkm_conf register
- *  SPI2_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t spi2_clkm_sel:2;
-        /** spi2_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable spi2 function clock
-         */
-        uint32_t spi2_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_spi2_clkm_conf_reg_t;
-
-/** Type of aes_conf register
- *  AES configuration register
- */
-typedef union {
-    struct {
-        /** aes_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable aes clock
-         */
-        uint32_t aes_clk_en:1;
-        /** aes_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset aes module
-         */
-        uint32_t aes_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_aes_conf_reg_t;
-
-/** Type of sha_conf register
- *  SHA configuration register
- */
-typedef union {
-    struct {
-        /** sha_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable sha clock
-         */
-        uint32_t sha_clk_en:1;
-        /** sha_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset sha module
-         */
-        uint32_t sha_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_sha_conf_reg_t;
-
-/** Type of rsa_conf register
- *  RSA configuration register
- */
-typedef union {
-    struct {
-        /** rsa_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable rsa clock
-         */
-        uint32_t rsa_clk_en:1;
-        /** rsa_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset rsa module
-         */
-        uint32_t rsa_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_rsa_conf_reg_t;
-
-/** Type of rsa_pd_ctrl register
- *  RSA power control register
- */
-typedef union {
-    struct {
-        /** rsa_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down rsa internal memory.
-         */
-        uint32_t rsa_mem_pd:1;
-        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up rsa internal memory
-         */
-        uint32_t rsa_mem_force_pu:1;
-        /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power down rsa internal memory.
-         */
-        uint32_t rsa_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_rsa_pd_ctrl_reg_t;
-
-/** Type of ecc_conf register
- *  ECC configuration register
- */
-typedef union {
-    struct {
-        /** ecc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ecc clock
-         */
-        uint32_t ecc_clk_en:1;
-        /** ecc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ecc module
-         */
-        uint32_t ecc_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_ecc_conf_reg_t;
-
-/** Type of ecc_pd_ctrl register
- *  ECC power control register
- */
-typedef union {
-    struct {
-        /** ecc_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down ecc internal memory.
-         */
-        uint32_t ecc_mem_pd:1;
-        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up ecc internal memory
-         */
-        uint32_t ecc_mem_force_pu:1;
-        /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power down ecc internal memory.
-         */
-        uint32_t ecc_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ecc_pd_ctrl_reg_t;
-
-/** Type of ds_conf register
- *  DS configuration register
- */
-typedef union {
-    struct {
-        /** ds_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ds clock
-         */
-        uint32_t ds_clk_en:1;
-        /** ds_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ds module
-         */
-        uint32_t ds_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_ds_conf_reg_t;
-
-/** Type of hmac_conf register
- *  HMAC configuration register
- */
-typedef union {
-    struct {
-        /** hmac_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable hmac clock
-         */
-        uint32_t hmac_clk_en:1;
-        /** hmac_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset hmac module
-         */
-        uint32_t hmac_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_hmac_conf_reg_t;
-
-/** Type of iomux_conf register
- *  IOMUX configuration register
- */
-typedef union {
-    struct {
-        /** iomux_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable iomux apb clock
-         */
-        uint32_t iomux_clk_en:1;
-        /** iomux_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset iomux module
-         */
-        uint32_t iomux_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_iomux_conf_reg_t;
-
-/** Type of iomux_clk_conf register
- *  IOMUX_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
-         *  FOSC, 3(default): XTAL.
-         */
-        uint32_t iomux_func_clk_sel:2;
-        /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable iomux function clock
-         */
-        uint32_t iomux_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_iomux_clk_conf_reg_t;
-
-/** Type of mem_monitor_conf register
- *  MEM_MONITOR configuration register
- */
-typedef union {
-    struct {
-        /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable mem_monitor clock
-         */
-        uint32_t mem_monitor_clk_en:1;
-        /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset mem_monitor module
-         */
-        uint32_t mem_monitor_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_mem_monitor_conf_reg_t;
-
-/** Type of regdma_conf register
- *  REGDMA configuration register
- */
-typedef union {
-    struct {
-        /** regdma_clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable regdma clock
-         */
-        uint32_t regdma_clk_en:1;
-        /** regdma_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset regdma module
-         */
-        uint32_t regdma_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_regdma_conf_reg_t;
-
-/** Type of retention_conf register
- *  retention configuration register
- */
-typedef union {
-    struct {
-        /** retention_clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable retention clock
-         */
-        uint32_t retention_clk_en:1;
-        /** retention_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset retention module
-         */
-        uint32_t retention_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_retention_conf_reg_t;
-
-/** Type of trace_conf register
- *  TRACE configuration register
- */
-typedef union {
-    struct {
-        /** trace_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable trace clock
-         */
-        uint32_t trace_clk_en:1;
-        /** trace_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset trace module
-         */
-        uint32_t trace_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_trace_conf_reg_t;
-
-/** Type of assist_conf register
- *  ASSIST configuration register
- */
-typedef union {
-    struct {
-        /** assist_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable assist clock
-         */
-        uint32_t assist_clk_en:1;
-        /** assist_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset assist module
-         */
-        uint32_t assist_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_assist_conf_reg_t;
-
-/** Type of cache_conf register
- *  CACHE configuration register
- */
-typedef union {
-    struct {
-        /** cache_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable cache clock
-         */
-        uint32_t cache_clk_en:1;
-        /** cache_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset cache module
-         */
-        uint32_t cache_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_cache_conf_reg_t;
-
-/** Type of modem_apb_conf register
- *  MODEM_APB configuration register
- */
-typedef union {
-    struct {
-        /** modem_apb_clk_en : R/W; bitpos: [0]; default: 1;
-         *  This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).
-         */
-        uint32_t modem_apb_clk_en:1;
-        /** modem_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set this file as 1 to reset modem-subsystem.
-         */
-        uint32_t modem_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_modem_apb_conf_reg_t;
-
-/** Type of timeout_conf register
- *  TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset cpu_peri timeout module
-         */
-        uint32_t cpu_timeout_rst_en:1;
-        /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0;
-         *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
-         */
-        uint32_t hp_timeout_rst_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_timeout_conf_reg_t;
-
-/** Type of sysclk_conf register
- *  SYSCLK configuration register
- */
-typedef union {
-    struct {
-        /** ls_div_num : HRO; bitpos: [7:0]; default: 0;
-         *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
-         *  clock-source such as XTAL/FOSC.
-         */
-        uint32_t ls_div_num:8;
-        /** hs_div_num : HRO; bitpos: [15:8]; default: 2;
-         *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
-         */
-        uint32_t hs_div_num:8;
-        /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0;
-         *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
-         */
-        uint32_t soc_clk_sel:2;
-        uint32_t reserved_18:6;
-        /** clk_xtal_freq : RO; bitpos: [30:24]; default: 40;
-         *  This field indicates the frequency(MHz) of XTAL.
-         */
-        uint32_t clk_xtal_freq:7;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} pcr_sysclk_conf_reg_t;
-
-/** Type of cpu_waiti_conf register
- *  CPU_WAITI configuration register
- */
-typedef union {
-    struct {
-        /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1;
-         *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
-         */
-        uint32_t cpuperiod_sel:2;
-        /** pll_freq_sel : HRO; bitpos: [2]; default: 1;
-         *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
-         */
-        uint32_t pll_freq_sel:1;
-        /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
-         *  Set 1 to force cpu_waiti_clk enable.
-         */
-        uint32_t cpu_wait_mode_force_on:1;
-        /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0;
-         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
-         *  will close
-         */
-        uint32_t cpu_waiti_delay_num:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} pcr_cpu_waiti_conf_reg_t;
-
-/** Type of cpu_freq_conf register
- *  CPU_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** cpu_ls_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
-         *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
-         */
-        uint32_t cpu_ls_div_num:8;
-        /** cpu_hs_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed
-         *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
-         */
-        uint32_t cpu_hs_div_num:8;
-        /** cpu_hs_120m_force : R/W; bitpos: [16]; default: 0;
-         *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
-         *  Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
-         */
-        uint32_t cpu_hs_120m_force:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} pcr_cpu_freq_conf_reg_t;
-
-/** Type of ahb_freq_conf register
- *  AHB_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** ahb_ls_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb
-         *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
-         *  low-speed clock-source such as XTAL/FOSC, and should be used together with
-         *  PCR_CPU_LS_DIV_NUM.
-         */
-        uint32_t ahb_ls_div_num:8;
-        /** ahb_hs_div_num : R/W; bitpos: [15:8]; default: 3;
-         *  Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is
-         *  div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed
-         *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
-         */
-        uint32_t ahb_hs_div_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} pcr_ahb_freq_conf_reg_t;
-
-/** Type of apb_freq_conf register
- *  APB_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
-         *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
-         *  recover to the previous frequency when a new access appears on apb-bus. Set as one
-         *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
-         *  that enable this function will reduce performance. Users can set this field as zero
-         *  to disable the auto-decrease-apb-freq function. By default, this function is
-         *  disable.
-         */
-        uint32_t apb_decrease_div_num:8;
-        /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
-         *  div1(default)/div2/div4 of clk_ahb.
-         */
-        uint32_t apb_div_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} pcr_apb_freq_conf_reg_t;
-
-/** Type of pll_div_clk_en register
- *  SPLL DIV clock-gating configuration register
- */
-typedef union {
-    struct {
-        /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
-         *  This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_240m_clk_en:1;
-        /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
-         *  This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_160m_clk_en:1;
-        /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
-         *  This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_120m_clk_en:1;
-        /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
-         *  This field is used to open 80 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_80m_clk_en:1;
-        /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_48m_clk_en:1;
-        /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_40m_clk_en:1;
-        /** pll_20m_clk_en : R/W; bitpos: [6]; default: 1;
-         *  This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_20m_clk_en:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} pcr_pll_div_clk_en_reg_t;
-
-/** Type of ctrl_clk_out_en register
- *  CLK_OUT_EN configuration register
- */
-typedef union {
-    struct {
-        /** clk20_oen : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable 20m clock
-         */
-        uint32_t clk20_oen:1;
-        /** clk22_oen : R/W; bitpos: [1]; default: 1;
-         *  Set 1 to enable 22m clock
-         */
-        uint32_t clk22_oen:1;
-        /** clk44_oen : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable 44m clock
-         */
-        uint32_t clk44_oen:1;
-        /** clk_bb_oen : R/W; bitpos: [3]; default: 1;
-         *  Set 1 to enable bb clock
-         */
-        uint32_t clk_bb_oen:1;
-        /** clk80_oen : R/W; bitpos: [4]; default: 1;
-         *  Set 1 to enable 80m clock
-         */
-        uint32_t clk80_oen:1;
-        /** clk160_oen : R/W; bitpos: [5]; default: 1;
-         *  Set 1 to enable 160m clock
-         */
-        uint32_t clk160_oen:1;
-        /** clk_320m_oen : R/W; bitpos: [6]; default: 1;
-         *  Set 1 to enable 320m clock
-         */
-        uint32_t clk_320m_oen:1;
-        /** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1;
-         *  Reserved
-         */
-        uint32_t clk_adc_inf_oen:1;
-        /** clk_dac_cpu_oen : R/W; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t clk_dac_cpu_oen:1;
-        /** clk40x_bb_oen : R/W; bitpos: [9]; default: 1;
-         *  Set 1 to enable 40x_bb clock
-         */
-        uint32_t clk40x_bb_oen:1;
-        /** clk_xtal_oen : R/W; bitpos: [10]; default: 1;
-         *  Set 1 to enable xtal clock
-         */
-        uint32_t clk_xtal_oen:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} pcr_ctrl_clk_out_en_reg_t;
-
-/** Type of ctrl_tick_conf register
- *  TICK configuration register
- */
-typedef union {
-    struct {
-        /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39;
-         *  ******* Description ***********
-         */
-        uint32_t xtal_tick_num:8;
-        /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7;
-         *  ******* Description ***********
-         */
-        uint32_t fosc_tick_num:8;
-        /** tick_enable : R/W; bitpos: [16]; default: 1;
-         *  ******* Description ***********
-         */
-        uint32_t tick_enable:1;
-        /** rst_tick_cnt : R/W; bitpos: [17]; default: 0;
-         *  ******* Description ***********
-         */
-        uint32_t rst_tick_cnt:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} pcr_ctrl_tick_conf_reg_t;
-
-/** Type of ctrl_32k_conf register
- *  32KHz clock configuration register
- */
-typedef union {
-    struct {
-        /** clk_32k_sel : R/W; bitpos: [1:0]; default: 0;
-         *  This field indicates which one 32KHz clock will be used by timergroup.
-         *  0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
-         */
-        uint32_t clk_32k_sel:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_ctrl_32k_conf_reg_t;
-
-/** Type of sram_power_conf register
- *  HP SRAM/ROM configuration register
- */
-typedef union {
-    struct {
-        /** sram_force_pu : R/W; bitpos: [3:0]; default: 15;
-         *  Set this bit to force power up SRAM
-         */
-        uint32_t sram_force_pu:4;
-        /** sram_force_pd : R/W; bitpos: [7:4]; default: 0;
-         *  Set this bit to force power down SRAM.
-         */
-        uint32_t sram_force_pd:4;
-        /** sram_clkgate_force_on : R/W; bitpos: [11:8]; default: 0;
-         *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
-         *  gate-clock will be used when accessing the SRAM.
-         */
-        uint32_t sram_clkgate_force_on:4;
-        /** rom_force_pu : R/W; bitpos: [14:12]; default: 7;
-         *  Set this bit to force power up ROM
-         */
-        uint32_t rom_force_pu:3;
-        /** rom_force_pd : R/W; bitpos: [17:15]; default: 0;
-         *  Set this bit to force power down ROM.
-         */
-        uint32_t rom_force_pd:3;
-        /** rom_clkgate_force_on : R/W; bitpos: [20:18]; default: 0;
-         *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
-         *  gate-clock will be used when accessing the ROM.
-         */
-        uint32_t rom_clkgate_force_on:3;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} pcr_sram_power_conf_reg_t;
-
-/** Type of reset_event_bypass register
- *  reset event bypass backdoor configuration register
- */
-typedef union {
-    struct {
-        /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0;
-         *  This field is used to control reset event relationship for
-         *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
-         *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
-         *  will not only be reset by power-reset, but also some reset event.
-         */
-        uint32_t reset_event_bypass_apm:1;
-        /** reset_event_bypass : R/W; bitpos: [1]; default: 1;
-         *  This field is used to control reset event relationship for system-bus. 1: system
-         *  bus (including arbiter/router) will only be reset by power-reset. some reset event
-         *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
-         *  power-reset, but also some reset event.
-         */
-        uint32_t reset_event_bypass:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_reset_event_bypass_reg_t;
-
-/** Type of clock_gate register
- *  PCR clock gating configure register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to force on clock gating.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} pcr_clock_gate_reg_t;
-
-
-/** Group: Frequency Statistics Register */
-/** Type of sysclk_freq_query_0 register
- *  SYSCLK frequency query 0 register
- */
-typedef union {
-    struct {
-        /** fosc_freq : HRO; bitpos: [7:0]; default: 20;
-         *  This field indicates the frequency(MHz) of FOSC.
-         */
-        uint32_t fosc_freq:8;
-        /** pll_freq : HRO; bitpos: [17:8]; default: 480;
-         *  This field indicates the frequency(MHz) of SPLL.
-         */
-        uint32_t pll_freq:10;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} pcr_sysclk_freq_query_0_reg_t;
-
-
-/** Group: FPGA Debug Register */
-/** Type of fpga_debug register
- *  fpga debug register
- */
-typedef union {
-    struct {
-        /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Only used in fpga debug.
-         */
-        uint32_t fpga_debug:32;
-    };
-    uint32_t val;
-} pcr_fpga_debug_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35676496;
-         *  PCR version information.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_date_reg_t;
-
-
-typedef struct pcr_dev_t {
-    volatile pcr_uart0_conf_reg_t uart0_conf;
-    volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf;
-    volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl;
-    volatile pcr_uart1_conf_reg_t uart1_conf;
-    volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf;
-    volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl;
-    volatile pcr_mspi_conf_reg_t mspi_conf;
-    volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf;
-    volatile pcr_i2c_conf_reg_t i2c_conf;
-    volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
-    volatile pcr_uhci_conf_reg_t uhci_conf;
-    volatile pcr_rmt_conf_reg_t rmt_conf;
-    volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf;
-    volatile pcr_ledc_conf_reg_t ledc_conf;
-    volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf;
-    volatile pcr_timergroup0_conf_reg_t timergroup0_conf;
-    volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf;
-    volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf;
-    volatile pcr_timergroup1_conf_reg_t timergroup1_conf;
-    volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf;
-    volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf;
-    volatile pcr_systimer_conf_reg_t systimer_conf;
-    volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf;
-    volatile pcr_twai0_conf_reg_t twai0_conf;
-    volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf;
-    volatile pcr_twai1_conf_reg_t twai1_conf;
-    volatile pcr_twai1_func_clk_conf_reg_t twai1_func_clk_conf;
-    volatile pcr_i2s_conf_reg_t i2s_conf;
-    volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf;
-    volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf;
-    volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf;
-    volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf;
-    volatile pcr_saradc_conf_reg_t saradc_conf;
-    volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf;
-    volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf;
-    volatile pcr_usb_device_conf_reg_t usb_device_conf;
-    volatile pcr_intmtx_conf_reg_t intmtx_conf;
-    volatile pcr_pcnt_conf_reg_t pcnt_conf;
-    volatile pcr_etm_conf_reg_t etm_conf;
-    volatile pcr_pwm_conf_reg_t pwm_conf;
-    volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf;
-    volatile pcr_parl_io_conf_reg_t parl_io_conf;
-    volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf;
-    volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf;
-    volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf;
-    volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf;
-    volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf;
-    volatile pcr_gdma_conf_reg_t gdma_conf;
-    volatile pcr_spi2_conf_reg_t spi2_conf;
-    volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf;
-    volatile pcr_aes_conf_reg_t aes_conf;
-    volatile pcr_sha_conf_reg_t sha_conf;
-    volatile pcr_rsa_conf_reg_t rsa_conf;
-    volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
-    volatile pcr_ecc_conf_reg_t ecc_conf;
-    volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
-    volatile pcr_ds_conf_reg_t ds_conf;
-    volatile pcr_hmac_conf_reg_t hmac_conf;
-    volatile pcr_iomux_conf_reg_t iomux_conf;
-    volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf;
-    volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf;
-    volatile pcr_regdma_conf_reg_t regdma_conf;
-    volatile pcr_retention_conf_reg_t retention_conf;
-    volatile pcr_trace_conf_reg_t trace_conf;
-    volatile pcr_assist_conf_reg_t assist_conf;
-    volatile pcr_cache_conf_reg_t cache_conf;
-    volatile pcr_modem_apb_conf_reg_t modem_apb_conf;
-    volatile pcr_timeout_conf_reg_t timeout_conf;
-    volatile pcr_sysclk_conf_reg_t sysclk_conf;
-    volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf;
-    volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf;
-    volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf;
-    volatile pcr_apb_freq_conf_reg_t apb_freq_conf;
-    volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0;
-    volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en;
-    volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en;
-    volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf;
-    volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf;
-    volatile pcr_sram_power_conf_reg_t sram_power_conf;
-    uint32_t reserved_13c[941];
-    volatile pcr_reset_event_bypass_reg_t reset_event_bypass;
-    volatile pcr_fpga_debug_reg_t fpga_debug;
-    volatile pcr_clock_gate_reg_t clock_gate;
-    volatile pcr_date_reg_t date;
-} pcr_dev_t;
-
-extern pcr_dev_t PCR;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/periph_defs.h b/components/soc/esp32c6/include/soc/periph_defs.h
index 3fefbbd326c..65cb21953cb 100644
--- a/components/soc/esp32c6/include/soc/periph_defs.h
+++ b/components/soc/esp32c6/include/soc/periph_defs.h
@@ -19,7 +19,7 @@ typedef enum {
     PERIPH_UART1_MODULE,
     PERIPH_USB_DEVICE_MODULE,
     PERIPH_I2C0_MODULE,
-    PERIPH_I2S1_MODULE,
+    PERIPH_I2S0_MODULE,
     PERIPH_TIMG0_MODULE,
     PERIPH_TIMG1_MODULE,
     PERIPH_UHCI0_MODULE,
diff --git a/components/soc/esp32c6/include/soc/pmu_struct.h b/components/soc/esp32c6/include/soc/pmu_struct.h
deleted file mode 100644
index 5d063118955..00000000000
--- a/components/soc/esp32c6/include/soc/pmu_struct.h
+++ /dev/null
@@ -1,756 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include <stddef.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "soc.h"
-#include "soc/pmu_reg.h"
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 21;
-        uint32_t vdd_spi_pd_en: 1;
-        uint32_t mem_dslp     : 1;
-        uint32_t mem_pd_en    : 4;
-        uint32_t wifi_pd_en   : 1;
-        uint32_t reserved1    : 1;
-        uint32_t cpu_pd_en    : 1;
-        uint32_t aon_pd_en    : 1;
-        uint32_t top_pd_en    : 1;
-    };
-    uint32_t val;
-} pmu_hp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 30;
-        uint32_t code     : 2;
-    };
-    uint32_t val;
-} pmu_hp_icg_modem_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 24;
-        uint32_t uart_wakeup_en : 1;
-        uint32_t lp_pad_hold_all: 1;
-        uint32_t hp_pad_hold_all: 1;
-        uint32_t dig_pad_slp_sel: 1;
-        uint32_t dig_pause_wdt  : 1;
-        uint32_t dig_cpu_stall  : 1;
-        uint32_t reserved1      : 2;
-    };
-    uint32_t val;
-} pmu_hp_sys_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 26;
-        uint32_t i2c_iso_en   : 1;
-        uint32_t i2c_retention: 1;
-        uint32_t xpd_bb_i2c   : 1;
-        uint32_t xpd_bbpll_i2c: 1;
-        uint32_t xpd_bbpll    : 1;
-        uint32_t reserved1    : 1;
-    };
-    uint32_t val;
-} pmu_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_hp_bias_reg_t;
-
-typedef union {
-    struct {    /* HP: Active State */
-        uint32_t reserved0                            : 4;
-        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
-        uint32_t hp_modem2active_backup_modem_clk_code: 2;
-        uint32_t reserved1                            : 2;
-        uint32_t hp_active_retention_mode             : 1;
-        uint32_t hp_sleep2active_retention_en         : 1;
-        uint32_t hp_modem2active_retention_en         : 1;
-        uint32_t reserved2                            : 1;
-        uint32_t hp_sleep2active_backup_clk_sel       : 2;
-        uint32_t hp_modem2active_backup_clk_sel       : 2;
-        uint32_t reserved3                            : 2;
-        uint32_t hp_sleep2active_backup_mode          : 3;
-        uint32_t hp_modem2active_backup_mode          : 3;
-        uint32_t reserved4                            : 3;
-        uint32_t hp_sleep2active_backup_en            : 1;
-        uint32_t hp_modem2active_backup_en            : 1;
-        uint32_t reserved5                            : 1;
-    };
-    struct {    /* HP: Modem State */
-        uint32_t reserved6                            : 4;
-        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
-        uint32_t reserved7                            : 4;
-        uint32_t hp_modem_retention_mode              : 1;
-        uint32_t hp_sleep2modem_retention_en          : 1;
-        uint32_t reserved8                            : 2;
-        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
-        uint32_t reserved9                            : 4;
-        uint32_t hp_sleep2modem_backup_mode           : 3;
-        uint32_t reserved10                           : 6;
-        uint32_t hp_sleep2modem_backup_en             : 1;
-        uint32_t reserved11                           : 2;
-    };
-    struct {    /* HP: Sleep State */
-        uint32_t reserved12                           : 6;
-        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
-        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
-        uint32_t hp_sleep_retention_mode              : 1;
-        uint32_t reserved13                           : 1;
-        uint32_t hp_modem2sleep_retention_en          : 1;
-        uint32_t hp_active2sleep_retention_en         : 1;
-        uint32_t reserved14                           : 2;
-        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
-        uint32_t hp_active2sleep_backup_clk_sel       : 2;
-        uint32_t reserved15                           : 3;
-        uint32_t hp_modem2sleep_backup_mode           : 3;
-        uint32_t hp_active2sleep_backup_mode          : 3;
-        uint32_t reserved16                           : 1;
-        uint32_t hp_modem2sleep_backup_en             : 1;
-        uint32_t hp_active2sleep_backup_en            : 1;
-    };
-    uint32_t val;
-} pmu_hp_backup_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0       : 26;
-        uint32_t dig_sysclk_nodiv: 1;
-        uint32_t icg_sysclk_en   : 1;
-        uint32_t sysclk_slp_sel  : 1;
-        uint32_t icg_slp_sel     : 1;
-        uint32_t dig_sysclk_sel  : 2;
-    };
-    uint32_t val;
-} pmu_hp_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t slp_mem_xpd    : 1;
-        uint32_t slp_logic_xpd  : 1;
-        uint32_t xpd            : 1;
-        uint32_t slp_mem_dbias  : 4;
-        uint32_t slp_logic_dbias: 4;
-        uint32_t dbias          : 5;
-    };
-    uint32_t val;
-} pmu_hp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 8;
-        uint32_t drv_b    : 24;
-    };
-    uint32_t val;
-} pmu_hp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_hp_xtal_reg_t;
-
-typedef struct pmu_hp_hw_regmap_t{
-    pmu_hp_dig_power_reg_t     dig_power;
-    uint32_t                   icg_func;
-    uint32_t                   icg_apb;
-    pmu_hp_icg_modem_reg_t     icg_modem;
-    pmu_hp_sys_cntl_reg_t      syscntl;
-    pmu_hp_clk_power_reg_t     clk_power;
-    pmu_hp_bias_reg_t          bias;
-    pmu_hp_backup_reg_t        backup;
-    uint32_t                   backup_clk;
-    pmu_hp_sysclk_reg_t        sysclk;
-    pmu_hp_regulator0_reg_t    regulator0;
-    pmu_hp_regulator1_reg_t    regulator1;
-    pmu_hp_xtal_reg_t          xtal;
-} pmu_hp_hw_regmap_t;
-
-/** */
-typedef union {
-    struct {
-        uint32_t reserved0: 21;
-        uint32_t slp_xpd  : 1;
-        uint32_t xpd	  : 1;
-        uint32_t slp_dbias: 4;
-        uint32_t dbias    : 5;
-    };
-    uint32_t val;
-} pmu_lp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 28;
-        uint32_t drv_b    : 4;
-    };
-    uint32_t val;
-} pmu_lp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_lp_xtal_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 30;
-        uint32_t mem_dslp  : 1;
-        uint32_t peri_pd_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0  : 28;
-        uint32_t xpd_xtal32k: 1;
-        uint32_t xpd_rc32k  : 1;
-        uint32_t xpd_fosc   : 1;
-        uint32_t pd_osc     : 1;
-    };
-    uint32_t val;
-} pmu_lp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_lp_bias_reg_t;
-
-typedef struct pmu_lp_hw_regmap_t{
-    pmu_lp_regulator0_reg_t    regulator0;
-    pmu_lp_regulator1_reg_t    regulator1;
-    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
-    pmu_lp_dig_power_reg_t     dig_power;
-    pmu_lp_clk_power_reg_t     clk_power;
-    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
-} pmu_lp_hw_regmap_t;
-
-
-typedef union {
-    struct {
-        uint32_t tie_low_global_bbpll_icg : 1;
-        uint32_t tie_low_global_xtal_icg  : 1;
-        uint32_t tie_low_i2c_retention    : 1;
-        uint32_t tie_low_xpd_bb_i2c       : 1;
-        uint32_t tie_low_xpd_bbpll_i2c    : 1;
-        uint32_t tie_low_xpd_bbpll        : 1;
-        uint32_t tie_low_xpd_xtal         : 1;
-        uint32_t reserved0                : 18;
-        uint32_t tie_high_global_bbpll_icg: 1;
-        uint32_t tie_high_global_xtal_icg : 1;
-        uint32_t tie_high_i2c_retention   : 1;
-        uint32_t tie_high_xpd_bb_i2c      : 1;
-        uint32_t tie_high_xpd_bbpll_i2c   : 1;
-        uint32_t tie_high_xpd_bbpll       : 1;
-        uint32_t tie_high_xpd_xtal        : 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 28;
-        uint32_t update_dig_icg_switch: 1;
-        uint32_t tie_low_icg_slp_sel  : 1;
-        uint32_t tie_high_icg_slp_sel : 1;
-        uint32_t update_dig_sysclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_sleep_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0             : 31;
-        uint32_t update_dig_icg_func_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_func_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 31;
-        uint32_t update_dig_icg_apb_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_apb_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 31;
-        uint32_t update_dig_icg_modem_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_modem_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 30;
-        uint32_t tie_low_lp_rootclk_sel : 1;
-        uint32_t tie_high_lp_rootclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_lp_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0               : 28;
-        uint32_t tie_high_lp_pad_hold_all: 1;
-        uint32_t tie_low_lp_pad_hold_all : 1;
-        uint32_t tie_high_hp_pad_hold_all: 1;
-        uint32_t tie_low_hp_pad_hold_all : 1;
-    };
-    uint32_t val;
-} pmu_imm_pad_hold_all_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 30;
-        uint32_t tie_high_i2c_iso_en: 1;
-        uint32_t tie_low_i2c_iso_en : 1;
-    };
-    uint32_t val;
-} pmu_imm_i2c_isolate_reg_t;
-
-typedef struct pmu_imm_hw_regmap_t{
-    pmu_imm_hp_clk_power_reg_t     clk_power;
-    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
-    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
-    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
-    pmu_imm_modem_icg_reg_t        modem_icg;
-    pmu_imm_lp_icg_reg_t           lp_icg;
-    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
-    pmu_imm_i2c_isolate_reg_t      i2c_iso;
-} pmu_imm_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 5;
-        uint32_t powerdown_timer: 9;
-        uint32_t powerup_timer  : 9;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 9;
-        uint32_t powerdown_timer: 7;
-        uint32_t powerup_timer  : 7;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_reset   : 1;
-        uint32_t force_iso     : 1;
-        uint32_t force_pu      : 1;
-        uint32_t force_no_reset: 1;
-        uint32_t force_no_iso  : 1;
-        uint32_t force_pd      : 1;
-        uint32_t mask          : 5;     /* Invalid of lp peripherals */
-        uint32_t reserved0     : 16;    /* Invalid of lp peripherals */
-        uint32_t pd_mask       : 5;     /* Invalid of lp peripherals */
-    };
-    uint32_t val;
-} pmu_power_domain_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_mem_iso   : 4;
-        uint32_t force_hp_mem_pd    : 4;
-        uint32_t reserved0          : 16;
-        uint32_t force_hp_mem_no_iso: 4;
-        uint32_t force_hp_mem_pu    : 4;
-    };
-    uint32_t val;
-} pmu_power_memory_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t mem2_pd_mask: 5;
-        uint32_t mem1_pd_mask: 5;
-        uint32_t mem0_pd_mask: 5;
-        uint32_t reserved0   : 2;
-        uint32_t mem2_mask   : 5;
-        uint32_t mem1_mask   : 5;
-        uint32_t mem0_mask   : 5;
-    };
-    uint32_t val;
-} pmu_power_memory_mask_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_pad_no_iso_all: 1;
-        uint32_t force_hp_pad_iso_all   : 1;
-        uint32_t reserved0              : 30;
-    };
-    uint32_t val;
-} pmu_power_hp_pad_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 18;
-        uint32_t pwr_wait  : 11;
-        uint32_t pwr_sw    : 2;
-        uint32_t pwr_sel_sw: 1;
-    };
-    uint32_t val;
-} pmu_power_vdd_spi_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wait_xtal_stable: 16;
-        uint32_t wait_pll_stable : 16;
-    };
-    uint32_t val;
-} pmu_power_clk_wait_cntl_reg_t;
-
-typedef struct pmu_power_hw_regmap_t{
-    pmu_power_wait_timer0_reg_t    wait_timer0;
-    pmu_power_wait_timer1_reg_t    wait_timer1;
-    pmu_power_domain_cntl_reg_t    hp_pd[5];
-    pmu_power_domain_cntl_reg_t    lp_peri;
-    pmu_power_memory_cntl_reg_t    mem_cntl;
-    pmu_power_memory_mask_reg_t    mem_mask;
-    pmu_power_hp_pad_reg_t         hp_pad;
-    pmu_power_vdd_spi_cntl_reg_t   vdd_spi;
-    pmu_power_clk_wait_cntl_reg_t  clk_wait;
-} pmu_power_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t sleep_reject_ena: 31;
-        uint32_t slp_reject_en   : 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_min_slp_val: 8;
-        uint32_t hp_min_slp_val: 8;
-        uint32_t sleep_prt_sel : 2;
-        uint32_t reserved0     : 14;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl3_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0           : 31;
-        uint32_t slp_reject_cause_clr: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl4_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modem_wait_target : 20;
-        uint32_t reserved0         : 4;
-        uint32_t lp_ana_wait_target: 8;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl5_reg_t;
-
-typedef union {
-    struct {
-        uint32_t soc_wakeup_wait    : 20;
-        uint32_t reserved0          : 10;
-        uint32_t soc_wakeup_wait_cfg: 2;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl6_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 16;
-        uint32_t ana_wait_target: 16;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl7_reg_t;
-
-typedef struct pmu_wakeup_hw_regmap_t{
-    pmu_slp_wakeup_cntl0_reg_t     cntl0;
-    pmu_slp_wakeup_cntl1_reg_t     cntl1;
-    uint32_t                       cntl2;
-    pmu_slp_wakeup_cntl3_reg_t     cntl3;
-    pmu_slp_wakeup_cntl4_reg_t     cntl4;
-    pmu_slp_wakeup_cntl5_reg_t     cntl5;
-    pmu_slp_wakeup_cntl6_reg_t     cntl6;
-    pmu_slp_wakeup_cntl7_reg_t     cntl7;
-    uint32_t                       status0;
-    uint32_t                       status1;
-} pmu_wakeup_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t i2c_por_wait_target: 8;
-        uint32_t reserved0          : 24;
-    };
-    uint32_t val;
-} pmu_hp_clk_poweron_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modify_icg_cntl_wait: 8;
-        uint32_t switch_icg_cntl_wait: 8;
-        uint32_t reserved0           : 16;
-    };
-    uint32_t val;
-} pmu_hp_clk_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t por_done : 1;
-    };
-    uint32_t val;
-} pmu_por_status_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0     : 26;
-        uint32_t perif_i2c_rstb: 1;
-        uint32_t xpd_perif_i2c : 1;
-        uint32_t xpd_txrf_i2c  : 1;
-        uint32_t xpd_rfrx_pbus : 1;
-        uint32_t xpd_ckgen_i2c : 1;
-        uint32_t xpd_pll_i2c   : 1;
-    };
-    uint32_t val;
-} pmu_rf_pwc_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 31;
-        uint32_t backup_sysclk_nodiv: 1;
-    };
-    uint32_t val;
-} pmu_backup_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 27;
-        uint32_t lp_cpu_exc: 1;
-        uint32_t sdio_idle : 1;
-        uint32_t sw        : 1;
-        uint32_t reject    : 1;
-        uint32_t wakeup    : 1;
-    };
-    uint32_t val;
-} pmu_hp_intr_reg_t;
-
-typedef struct pmu_hp_ext_hw_regmap_t{
-    pmu_hp_clk_poweron_reg_t   clk_poweron;
-    pmu_hp_clk_cntl_reg_t      clk_cntl;
-    pmu_por_status_reg_t       por_status;
-    pmu_rf_pwc_reg_t           rf_pwc;
-    pmu_backup_cfg_reg_t       backup_cfg;
-    pmu_hp_intr_reg_t          int_raw;
-    pmu_hp_intr_reg_t          int_st;
-    pmu_hp_intr_reg_t          int_ena;
-    pmu_hp_intr_reg_t          int_clr;
-} pmu_hp_ext_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0                : 20;
-        uint32_t lp_cpu_wakeup            : 1;
-        uint32_t modem_switch_active_end  : 1;
-        uint32_t sleep_switch_active_end  : 1;
-        uint32_t sleep_switch_modem_end   : 1;
-        uint32_t modem_switch_sleep_end   : 1;
-        uint32_t active_swtich_sleep_end  : 1;
-        uint32_t modem_switch_active_start: 1;
-        uint32_t sleep_switch_active_start: 1;
-        uint32_t sleep_switch_modem_start : 1;
-        uint32_t modem_switch_sleep_start : 1;
-        uint32_t active_switch_sleep_start: 1;
-        uint32_t sw_trigger               : 1;
-    };
-    uint32_t val;
-} pmu_lp_intr_reg_t;
-
-typedef union {
-    struct {
-        uint32_t waiti_rdy         : 1;
-        uint32_t stall_rdy         : 1;
-        uint32_t reserved0         : 16;
-        uint32_t force_stall       : 1;
-        uint32_t slp_waiti_flag_en : 1;
-        uint32_t slp_stall_flag_en : 1;
-        uint32_t slp_stall_wait    : 8;
-        uint32_t slp_stall_en      : 1;
-        uint32_t slp_reset_en      : 1;
-        uint32_t slp_bypass_intr_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_en: 16;
-        uint32_t reserved0: 15;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr1_reg_t;
-
-typedef struct pmu_lp_ext_hw_regmap_t{
-    pmu_lp_intr_reg_t          int_raw;
-    pmu_lp_intr_reg_t          int_st;
-    pmu_lp_intr_reg_t          int_ena;
-    pmu_lp_intr_reg_t          int_clr;
-    pmu_lp_cpu_pwr0_reg_t      pwr0;
-    pmu_lp_cpu_pwr1_reg_t      pwr1;
-} pmu_lp_ext_hw_regmap_t;
-
-typedef struct pmu_dev_t{
-    volatile pmu_hp_hw_regmap_t     hp_sys[3];
-    volatile pmu_lp_hw_regmap_t     lp_sys[2];
-    volatile pmu_imm_hw_regmap_t    imm;
-    volatile pmu_power_hw_regmap_t  power;
-    volatile pmu_wakeup_hw_regmap_t wakeup;
-    volatile pmu_hp_ext_hw_regmap_t hp_ext;
-    volatile pmu_lp_ext_hw_regmap_t lp_ext;
-
-    union {
-        struct {
-            uint32_t reserved0    : 30;
-            volatile uint32_t lp_trigger_hp: 1;
-            volatile uint32_t hp_trigger_lp: 1;
-        };
-        volatile uint32_t val;
-    } hp_lp_cpu_comm;
-
-    union {
-        struct {
-            uint32_t reserved0           : 31;
-            volatile uint32_t dig_regulator_en_cal: 1;
-        };
-        volatile uint32_t val;
-    } hp_regulator_cfg;
-
-    union {
-        struct {
-            uint32_t reserved0 : 11;
-            volatile uint32_t last_st   : 7;
-            volatile uint32_t target_st : 7;
-            volatile uint32_t current_st: 7;
-        };
-        volatile uint32_t val;
-    } main_state;
-
-    union {
-        struct {
-            uint32_t reserved0: 13;
-            volatile uint32_t backup_st: 5;
-            volatile uint32_t lp_pwr_st: 5;
-            volatile uint32_t hp_pwr_st: 9;
-        };
-        volatile uint32_t val;
-    } pwr_state;
-
-    union {
-        struct {
-            volatile uint32_t stable_xpd_bbpll : 1;
-            volatile uint32_t stable_xpd_xtal  : 1;
-            volatile uint32_t reserved0        : 13;
-            volatile uint32_t sysclk_slp_sel   : 1;
-            volatile uint32_t sysclk_sel       : 2;
-            volatile uint32_t sysclk_nodiv     : 1;
-            volatile uint32_t icg_sysclk_en    : 1;
-            volatile uint32_t icg_modem_switch : 1;
-            volatile uint32_t icg_modem_code   : 2;
-            volatile uint32_t icg_slp_sel      : 1;
-            volatile uint32_t icg_global_xtal  : 1;
-            volatile uint32_t icg_global_pll   : 1;
-            volatile uint32_t ana_i2c_iso_en   : 1;
-            volatile uint32_t ana_i2c_retention: 1;
-            volatile uint32_t ana_xpd_bb_i2c   : 1;
-            volatile uint32_t ana_xpd_bbpll_i2c: 1;
-            volatile uint32_t ana_xpd_bbpll    : 1;
-            volatile uint32_t ana_xpd_xtal     : 1;
-        };
-        volatile uint32_t val;
-    } clk_state0;
-
-    volatile uint32_t clk_state1;
-    volatile uint32_t clk_state2;
-
-    union {
-        struct {
-            uint32_t reserved0             : 31;
-            volatile uint32_t stable_vdd_spi_pwr_drv: 1;
-        };
-        volatile uint32_t val;
-    } vdd_spi_status;
-
-    uint32_t reserved[150];
-
-    union {
-        struct {
-            volatile uint32_t pmu_date: 31;
-            volatile uint32_t clk_en  : 1;
-        };
-        volatile uint32_t val;
-    } date;
-} pmu_dev_t;
-
-extern pmu_dev_t PMU;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
-
-_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/retention_periph_defs.h b/components/soc/esp32c6/include/soc/retention_periph_defs.h
index 5cdbc108e81..89380da1522 100644
--- a/components/soc/esp32c6/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32c6/include/soc/retention_periph_defs.h
@@ -15,6 +15,7 @@ extern "C" {
 
 typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_MIN          = 0,
+    SLEEP_RETENTION_MODULE_NULL         = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
     SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 2,
@@ -37,6 +38,15 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_UART0        = 14,
     SLEEP_RETENTION_MODULE_UART1        = 15,
     SLEEP_RETENTION_MODULE_I2S0         = 16,
+    SLEEP_RETENTION_MODULE_ETM0         = 17,
+    SLEEP_RETENTION_MODULE_TEMP_SENSOR  = 18,
+    SLEEP_RETENTION_MODULE_TWAI0        = 19,
+    SLEEP_RETENTION_MODULE_TWAI1        = 20,
+    SLEEP_RETENTION_MODULE_PARLIO0      = 21,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 22,
+    SLEEP_RETENTION_MODULE_LEDC         = 23,
+    SLEEP_RETENTION_MODULE_PCNT0        = 24,
+    SLEEP_RETENTION_MODULE_MCPWM0       = 25,
 
     /* Modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
@@ -48,6 +58,8 @@ typedef enum periph_retention_module {
 } periph_retention_module_t;
 
 typedef enum periph_retention_module_bitmap {
+    SLEEP_RETENTION_MODULE_BM_NULL = BIT(SLEEP_RETENTION_MODULE_NULL),
+
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
     SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM  = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
@@ -70,6 +82,15 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_UART0        = BIT(SLEEP_RETENTION_MODULE_UART0),
     SLEEP_RETENTION_MODULE_BM_UART1        = BIT(SLEEP_RETENTION_MODULE_UART1),
     SLEEP_RETENTION_MODULE_BM_I2S0         = BIT(SLEEP_RETENTION_MODULE_I2S0),
+    SLEEP_RETENTION_MODULE_BM_ETM0         = BIT(SLEEP_RETENTION_MODULE_ETM0),
+    SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR  = BIT(SLEEP_RETENTION_MODULE_TEMP_SENSOR),
+    SLEEP_RETENTION_MODULE_BM_TWAI0        = BIT(SLEEP_RETENTION_MODULE_TWAI0),
+    SLEEP_RETENTION_MODULE_BM_TWAI1        = BIT(SLEEP_RETENTION_MODULE_TWAI1),
+    SLEEP_RETENTION_MODULE_BM_PARLIO0      = BIT(SLEEP_RETENTION_MODULE_PARLIO0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
+    SLEEP_RETENTION_MODULE_BM_PCNT0        = BIT(SLEEP_RETENTION_MODULE_PCNT0),
+    SLEEP_RETENTION_MODULE_BM_MCPWM0       = BIT(SLEEP_RETENTION_MODULE_MCPWM0),
     /* modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BM_WIFI_MAC     = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
     SLEEP_RETENTION_MODULE_BM_WIFI_BB      = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
@@ -93,6 +114,16 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_UART0       \
                                   | SLEEP_RETENTION_MODULE_BM_UART1       \
                                   | SLEEP_RETENTION_MODULE_BM_I2S0        \
+                                  | SLEEP_RETENTION_MODULE_BM_ETM0        \
+                                  | SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR \
+                                  | SLEEP_RETENTION_MODULE_BM_TWAI0       \
+                                  | SLEEP_RETENTION_MODULE_BM_TWAI1       \
+                                  | SLEEP_RETENTION_MODULE_BM_PARLIO0     \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC        \
+                                  | SLEEP_RETENTION_MODULE_BM_PCNT0       \
+                                  | SLEEP_RETENTION_MODULE_BM_MCPWM0      \
+                                  | SLEEP_RETENTION_MODULE_BM_NULL       \
                                   )
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32c6/include/soc/sha_reg.h b/components/soc/esp32c6/include/soc/sha_reg.h
deleted file mode 100644
index 265f510472a..00000000000
--- a/components/soc/esp32c6/include/soc/sha_reg.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SHA_MODE_REG register
- *  Initial configuration register.
- */
-#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
-/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  Sha mode.
- */
-#define SHA_MODE    0x00000007U
-#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
-#define SHA_MODE_V  0x00000007U
-#define SHA_MODE_S  0
-
-/** SHA_T_STRING_REG register
- *  SHA 512/t configuration register 0.
- */
-#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
-/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
- *  Sha t_string (used if and only if mode == SHA_512/t).
- */
-#define SHA_T_STRING    0xFFFFFFFFU
-#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
-#define SHA_T_STRING_V  0xFFFFFFFFU
-#define SHA_T_STRING_S  0
-
-/** SHA_T_LENGTH_REG register
- *  SHA 512/t configuration register 1.
- */
-#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
-/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
- *  Sha t_length (used if and only if mode == SHA_512/t).
- */
-#define SHA_T_LENGTH    0x0000003FU
-#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
-#define SHA_T_LENGTH_V  0x0000003FU
-#define SHA_T_LENGTH_S  0
-
-/** SHA_DMA_BLOCK_NUM_REG register
- *  DMA configuration register 0.
- */
-#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
-/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
- *  Dma-sha block number.
- */
-#define SHA_DMA_BLOCK_NUM    0x0000003FU
-#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
-#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
-#define SHA_DMA_BLOCK_NUM_S  0
-
-/** SHA_START_REG register
- *  Typical SHA configuration register 0.
- */
-#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
-/** SHA_START : RO; bitpos: [31:1]; default: 0;
- *  Reserved.
- */
-#define SHA_START    0x7FFFFFFFU
-#define SHA_START_M  (SHA_START_V << SHA_START_S)
-#define SHA_START_V  0x7FFFFFFFU
-#define SHA_START_S  1
-
-/** SHA_CONTINUE_REG register
- *  Typical SHA configuration register 1.
- */
-#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
-/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
- *  Reserved.
- */
-#define SHA_CONTINUE    0x7FFFFFFFU
-#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
-#define SHA_CONTINUE_V  0x7FFFFFFFU
-#define SHA_CONTINUE_S  1
-
-/** SHA_BUSY_REG register
- *  Busy register.
- */
-#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
-/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
- *  Sha busy state. 1'b0: idle. 1'b1: busy.
- */
-#define SHA_BUSY_STATE    (BIT(0))
-#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
-#define SHA_BUSY_STATE_V  0x00000001U
-#define SHA_BUSY_STATE_S  0
-
-/** SHA_DMA_START_REG register
- *  DMA configuration register 1.
- */
-#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
-/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
- *  Start dma-sha.
- */
-#define SHA_DMA_START    (BIT(0))
-#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
-#define SHA_DMA_START_V  0x00000001U
-#define SHA_DMA_START_S  0
-
-/** SHA_DMA_CONTINUE_REG register
- *  DMA configuration register 2.
- */
-#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
-/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
- *  Continue dma-sha.
- */
-#define SHA_DMA_CONTINUE    (BIT(0))
-#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
-#define SHA_DMA_CONTINUE_V  0x00000001U
-#define SHA_DMA_CONTINUE_S  0
-
-/** SHA_CLEAR_IRQ_REG register
- *  Interrupt clear register.
- */
-#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
-/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
- *  Clear sha interrupt.
- */
-#define SHA_CLEAR_INTERRUPT    (BIT(0))
-#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
-#define SHA_CLEAR_INTERRUPT_V  0x00000001U
-#define SHA_CLEAR_INTERRUPT_S  0
-
-/** SHA_IRQ_ENA_REG register
- *  Interrupt enable register.
- */
-#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
-/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
- *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
- */
-#define SHA_INTERRUPT_ENA    (BIT(0))
-#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
-#define SHA_INTERRUPT_ENA_V  0x00000001U
-#define SHA_INTERRUPT_ENA_S  0
-
-/** SHA_DATE_REG register
- *  Date register.
- */
-#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
-/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
- *  Sha date information/ sha version information.
- */
-#define SHA_DATE    0x3FFFFFFFU
-#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
-#define SHA_DATE_V  0x3FFFFFFFU
-#define SHA_DATE_S  0
-
-/** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
- */
-#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
-#define SHA_H_MEM_SIZE_BYTES 64
-
-/** SHA_M_MEM register
- *  Sha M memory which contains message.
- */
-#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
-#define SHA_M_MEM_SIZE_BYTES 64
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h
index 6778a1764bc..afd44da86c4 100644
--- a/components/soc/esp32c6/include/soc/soc.h
+++ b/components/soc/esp32c6/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 58463193d0f..54825410295 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -178,6 +178,7 @@
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
 #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
+#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1   // Support sleep retention
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-C6 has 1 GPIO peripheral
@@ -278,12 +279,14 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_SUPPORT_SLEEP_RETENTION    (1)
 
 /*-------------------------- MMU CAPS ----------------------------------------*/
 #define SOC_MMU_PAGE_SIZE_CONFIGURABLE        (1)
@@ -305,6 +308,7 @@
 #define SOC_PCNT_CHANNELS_PER_UNIT            2
 #define SOC_PCNT_THRES_POINT_PER_UNIT         2
 #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
+#define SOC_PCNT_SUPPORT_SLEEP_RETENTION      1  /*!< The sleep retention feature can help back up PCNT registers before sleep */
 
 /*--------------------------- RMT CAPS ---------------------------------------*/
 #define SOC_RMT_GROUPS                        1U /*!< One RMT group */
@@ -337,6 +341,7 @@
 #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE       (1)    ///< Software sync event can be routed to its output
 #define SOC_MCPWM_SUPPORT_ETM                (1)    ///< Support ETM (Event Task Matrix)
 #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP     (1)    ///< Capture timer shares clock with other PWM timers
+#define SOC_MCPWM_SUPPORT_SLEEP_RETENTION    (1)    ///< Support back up registers before sleep
 
 /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
 // #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
@@ -348,6 +353,7 @@
 #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the TX unit */
 #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the RX unit */
 #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT     1   /*!< TX and RX unit share the same interrupt source number */
+#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION   1   /*!< Support back up registers before sleep */
 
 /*--------------------------- MPI CAPS ---------------------------------------*/
 #define SOC_MPI_MEM_BLOCKS_NUM (4)
@@ -395,6 +401,7 @@
 #define SOC_SPI_SUPPORT_CD_SIG              1
 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+#define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
 #define SOC_SPI_SUPPORT_CLK_XTAL            1
 #define SOC_SPI_SUPPORT_CLK_PLL_F80M        1
 #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
@@ -455,11 +462,12 @@
 #define SOC_MWDT_SUPPORT_SLEEP_RETENTION   (1)
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
-#define SOC_TWAI_CONTROLLER_NUM         2
-#define SOC_TWAI_CLK_SUPPORT_XTAL       1
-#define SOC_TWAI_BRP_MIN                2
-#define SOC_TWAI_BRP_MAX                32768
-#define SOC_TWAI_SUPPORTS_RX_STATUS     1
+#define SOC_TWAI_CONTROLLER_NUM             2
+#define SOC_TWAI_CLK_SUPPORT_XTAL           1
+#define SOC_TWAI_BRP_MIN                    2
+#define SOC_TWAI_BRP_MAX                    32768
+#define SOC_TWAI_SUPPORTS_RX_STATUS         1
+#define SOC_TWAI_SUPPORT_SLEEP_RETENTION    1
 
 /*-------------------------- eFuse CAPS----------------------------*/
 #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
@@ -566,13 +574,19 @@
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
 #define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
 
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2           (1)     /*!< Support XTAL_D2 clock as the LP_FAST clock source */
+
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                   (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM                    (1)
+#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION        (1)
+#define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN            (1)
 
 /*--------------------------------- RNG CAPS --------------------------------------------*/
 #define SOC_RNG_CLOCK_IS_INDEPENDENT                          (1)
@@ -610,3 +624,6 @@
 /*------------------------------------- ULP CAPS -------------------------------------*/
 #define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR   (1) /*!< LP Core interrupts all map to a single entry in vector table */
 #define SOC_LP_CORE_SUPPORT_ETM               (1) /*!< LP Core supports ETM */
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
diff --git a/components/soc/esp32c6/include/soc/spi_mem_reg.h b/components/soc/esp32c6/include/soc/spi_mem_reg.h
deleted file mode 100644
index 81a136b8703..00000000000
--- a/components/soc/esp32c6/include/soc/spi_mem_reg.h
+++ /dev/null
@@ -1,3091 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SPI_MEM_CMD_REG register
- *  SPI0 FSM status register
- *  SPI1 memory command register
- */
-#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
-/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (BIT(31))
-#define SPI_MEM_FLASH_READ_V  0x1
-#define SPI_MEM_FLASH_READ_S  31
-/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
-bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (BIT(30))
-#define SPI_MEM_FLASH_WREN_V  0x1
-#define SPI_MEM_FLASH_WREN_S  30
-/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Write flash disable. Write disable command will be sent when the bit is set. The
- bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
-#define SPI_MEM_FLASH_WRDI_V  0x1
-#define SPI_MEM_FLASH_WRDI_S  29
-/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
-e cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (BIT(28))
-#define SPI_MEM_FLASH_RDID_V  0x1
-#define SPI_MEM_FLASH_RDID_S  28
-/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Read status register-1.  Read status operation will be triggered when the bit is
- set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
-#define SPI_MEM_FLASH_RDSR_V  0x1
-#define SPI_MEM_FLASH_RDSR_S  27
-/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write status register enable.   Write status operation  will be triggered when t
-he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
-ble..*/
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
-#define SPI_MEM_FLASH_WRSR_V  0x1
-#define SPI_MEM_FLASH_WRSR_S  26
-/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
-tion  will be triggered when the bit is set. The bit will be cleared once the op
-eration done .1: enable 0: disable..*/
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (BIT(25))
-#define SPI_MEM_FLASH_PP_V  0x1
-#define SPI_MEM_FLASH_PP_S  25
-/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
-is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (BIT(24))
-#define SPI_MEM_FLASH_SE_V  0x1
-#define SPI_MEM_FLASH_SE_S  24
-/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
- is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (BIT(23))
-#define SPI_MEM_FLASH_BE_V  0x1
-#define SPI_MEM_FLASH_BE_S  23
-/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (BIT(22))
-#define SPI_MEM_FLASH_CE_V  0x1
-#define SPI_MEM_FLASH_CE_S  22
-/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
-. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (BIT(21))
-#define SPI_MEM_FLASH_DP_V  0x1
-#define SPI_MEM_FLASH_DP_S  21
-/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
-e or high performance mode and obtains the devices ID. The bit will be cleared o
-nce the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (BIT(20))
-#define SPI_MEM_FLASH_RES_V  0x1
-#define SPI_MEM_FLASH_RES_S  20
-/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
-ion done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (BIT(19))
-#define SPI_MEM_FLASH_HPM_V  0x1
-#define SPI_MEM_FLASH_HPM_S  19
-/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
-ion will be triggered when the bit is set. The bit will be cleared once the oper
-ation done.1: enable 0: disable..*/
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (BIT(18))
-#define SPI_MEM_USR_V  0x1
-#define SPI_MEM_USR_S  18
-/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
-/*description: In user mode, it is set to indicate that program/erase operation will be trigger
-ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
-peration done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (BIT(17))
-#define SPI_MEM_FLASH_PE_V  0x1
-#define SPI_MEM_FLASH_PE_S  17
-/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
-ate, 6:write data state, 7: done state, 8: read data end state..*/
-#define SPI_MEM_SLV_ST    0x0000000F
-#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
-#define SPI_MEM_SLV_ST_V  0xF
-#define SPI_MEM_SLV_ST_S  4
-/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
-, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
-nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
-#define SPI_MEM_MST_ST    0x0000000F
-#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
-#define SPI_MEM_MST_ST_V  0xF
-#define SPI_MEM_MST_ST_S  0
-
-#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
-/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
-address, the bit24-bit31 are the byte length of a transfer..*/
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_S  0
-
-#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
-/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
-lways 1. 0: Others..*/
-#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
-/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
-s 1. 0: Others..*/
-#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
-/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
-ble 0: disable..*/
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (BIT(24))
-#define SPI_MEM_FREAD_QIO_V  0x1
-#define SPI_MEM_FREAD_QIO_S  24
-/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
-ble 0: disable..*/
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (BIT(23))
-#define SPI_MEM_FREAD_DIO_V  0x1
-#define SPI_MEM_FREAD_DIO_S  23
-/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
-isable..*/
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (BIT(22))
-#define SPI_MEM_WRSR_2B_V  0x1
-#define SPI_MEM_WRSR_2B_S  22
-/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (BIT(21))
-#define SPI_MEM_WP_REG_V  0x1
-#define SPI_MEM_WP_REG_S  21
-/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
-#define SPI_MEM_FREAD_QUAD_V  0x1
-#define SPI_MEM_FREAD_QUAD_S  20
-/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (BIT(19))
-#define SPI_MEM_D_POL_V  0x1
-#define SPI_MEM_D_POL_S  19
-/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (BIT(18))
-#define SPI_MEM_Q_POL_V  0x1
-#define SPI_MEM_Q_POL_S  18
-/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-spi_mem_flash_res bit. 1: enable 0: disable..*/
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (BIT(15))
-#define SPI_MEM_RESANDRES_V  0x1
-#define SPI_MEM_RESANDRES_S  15
-/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
-#define SPI_MEM_FREAD_DUAL_V  0x1
-#define SPI_MEM_FREAD_DUAL_S  14
-/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
-UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
-#define SPI_MEM_FASTRD_MODE_V  0x1
-#define SPI_MEM_FASTRD_MODE_S  13
-/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
-e.*/
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
-#define SPI_MEM_TX_CRC_EN_V  0x1
-#define SPI_MEM_TX_CRC_EN_S  11
-/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
-e low..*/
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_V  0x1
-#define SPI_MEM_FCS_CRC_EN_S  10
-/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (BIT(9))
-#define SPI_MEM_FCMD_OCT_V  0x1
-#define SPI_MEM_FCMD_OCT_S  9
-/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
-#define SPI_MEM_FCMD_QUAD_V  0x1
-#define SPI_MEM_FCMD_QUAD_S  8
-/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (BIT(6))
-#define SPI_MEM_FADDR_OCT_V  0x1
-#define SPI_MEM_FADDR_OCT_S  6
-/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (BIT(5))
-#define SPI_MEM_FDIN_OCT_V  0x1
-#define SPI_MEM_FDIN_OCT_S  5
-/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (BIT(4))
-#define SPI_MEM_FDOUT_OCT_V  0x1
-#define SPI_MEM_FDOUT_OCT_S  4
-/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
-is output by the MSPI controller in the second half part of dummy phase. It is u
-sed to pre-drive flash..*/
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_V  0x1
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
-s output by the MSPI controller in the first half part of dummy phase. It is use
-d to mask invalid SPI_DQS in the half part of dummy phase..*/
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_V  0x1
-#define SPI_MEM_FDUMMY_RIN_S  2
-/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_IO[7:0] is output by the MSPI controller..*/
-#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
-/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_DQS is output by the MSPI controller..*/
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
-
-#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
-/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
- send signals to AXI. Set this bit to reset these FIFO..*/
-#define SPI_MEM_TXFIFO_RST    (BIT(31))
-#define SPI_MEM_TXFIFO_RST_M  (BIT(31))
-#define SPI_MEM_TXFIFO_RST_V  0x1
-#define SPI_MEM_TXFIFO_RST_S  31
-/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
- receive signals from AXI.  Set this bit to reset these FIFO..*/
-#define SPI_MEM_RXFIFO_RST    (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
-#define SPI_MEM_RXFIFO_RST_V  0x1
-#define SPI_MEM_RXFIFO_RST_S  30
-/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
-bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
-in  tx_bus_fifo_l2..*/
-#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_M  (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_V  0x1
-#define SPI_MEM_FAST_WRITE_EN_S  29
-/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
-the same time..*/
-#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_M  (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_V  0x1
-#define SPI_MEM_DUAL_RAM_EN_S  28
-/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
-cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
-ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
-cessed at the same time..*/
-#define SPI_MEM_RAM0_EN    (BIT(27))
-#define SPI_MEM_RAM0_EN_M  (BIT(27))
-#define SPI_MEM_RAM0_EN_V  0x1
-#define SPI_MEM_RAM0_EN_S  27
-/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Write Splice-transfer..*/
-#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_M  (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_V  0x1
-#define SPI_MEM_AW_SPLICE_EN_S  26
-/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Read Splice-transfer..*/
-#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_M  (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_V  0x1
-#define SPI_MEM_AR_SPLICE_EN_S  25
-/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
- when there is a ECC error in AXI read data. The ECC error information is record
-ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
-#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x1
-#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
-/* SPI_MEM_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */
-/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
-eply AXI read data to AXI bus when all the read data is available..*/
-#define SPI_MEM_AXI_RDATA_BACK_FAST    (BIT(23))
-#define SPI_MEM_AXI_RDATA_BACK_FAST_M  (BIT(23))
-#define SPI_MEM_AXI_RDATA_BACK_FAST_V  0x1
-#define SPI_MEM_AXI_RDATA_BACK_FAST_S  23
-/* SPI_MEM_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
-#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
-#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
-#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V  0x1
-#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S  22
-/* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
-y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
-#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
-#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
-#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_V  0x1
-#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_S  21
-/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
-/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
-12) SPI_CLK cycles..*/
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
-#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
-/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on..*/
-#define SPI_MEM_CLK_MODE    0x00000003
-#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
-#define SPI_MEM_CLK_MODE_V  0x3
-#define SPI_MEM_CLK_MODE_S  0
-
-#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
-/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (BIT(31))
-#define SPI_MEM_SYNC_RESET_V  0x1
-#define SPI_MEM_SYNC_RESET_S  31
-/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
- clock cycles..*/
-#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_SPLIT_TRANS_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
-fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
-whether there is an ECC region or not..*/
-#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_V  0x1
-#define SPI_MEM_SPLIT_TRANS_EN_S  24
-/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses flash..*/
-#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
-#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */
-/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
-hen accesses flash..*/
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
- mode when accessed flash..*/
-#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
-#define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
-#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
-#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
-/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
-/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
-th SPI_MEM_CS_HOLD bit..*/
-#define SPI_MEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
-#define SPI_MEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
-/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
-M_CS_SETUP bit..*/
-#define SPI_MEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
-#define SPI_MEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_CS_SETUP_TIME_S  0
-
-#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
-/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
- clock..*/
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
-/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- system/(spi_mem_clkcnt_N+1).*/
-#define SPI_MEM_CLKCNT_N    0x000000FF
-#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
-#define SPI_MEM_CLKCNT_N_V  0xFF
-#define SPI_MEM_CLKCNT_N_S  16
-/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define SPI_MEM_CLKCNT_H    0x000000FF
-#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
-#define SPI_MEM_CLKCNT_H_V  0xFF
-#define SPI_MEM_CLKCNT_H_S  8
-/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
-#define SPI_MEM_CLKCNT_L    0x000000FF
-#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
-#define SPI_MEM_CLKCNT_L_V  0xFF
-#define SPI_MEM_CLKCNT_L_S  0
-
-#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
-/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation..*/
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (BIT(31))
-#define SPI_MEM_USR_COMMAND_V  0x1
-#define SPI_MEM_USR_COMMAND_S  31
-/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation..*/
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (BIT(30))
-#define SPI_MEM_USR_ADDR_V  0x1
-#define SPI_MEM_USR_ADDR_S  30
-/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation..*/
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (BIT(29))
-#define SPI_MEM_USR_DUMMY_V  0x1
-#define SPI_MEM_USR_DUMMY_S  29
-/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation..*/
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (BIT(28))
-#define SPI_MEM_USR_MISO_V  0x1
-#define SPI_MEM_USR_MISO_S  28
-/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation..*/
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (BIT(27))
-#define SPI_MEM_USR_MOSI_V  0x1
-#define SPI_MEM_USR_MOSI_S  27
-/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable..*/
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
-1: enable 0: disable..*/
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
-: enable 0: disable..*/
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 4 signals..*/
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
-#define SPI_MEM_FWRITE_QIO_V  0x1
-#define SPI_MEM_FWRITE_QIO_S  15
-/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 2 signals..*/
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
-#define SPI_MEM_FWRITE_DIO_V  0x1
-#define SPI_MEM_FWRITE_DIO_S  14
-/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals.*/
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_V  0x1
-#define SPI_MEM_FWRITE_QUAD_S  13
-/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals.*/
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_V  0x1
-#define SPI_MEM_FWRITE_DUAL_S  12
-/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_V  0x1
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
-#define SPI_MEM_CS_SETUP    (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (BIT(7))
-#define SPI_MEM_CS_SETUP_V  0x1
-#define SPI_MEM_CS_SETUP_S  7
-/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
-#define SPI_MEM_CS_HOLD    (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (BIT(6))
-#define SPI_MEM_CS_HOLD_V  0x1
-#define SPI_MEM_CS_HOLD_S  6
-
-#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
-/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
-/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
-/*description: SPI0 USR_CMD read or write data byte length -1.*/
-#define SPI_MEM_USR_DBYTELEN    0x00000007
-#define SPI_MEM_USR_DBYTELEN_M  ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S))
-#define SPI_MEM_USR_DBYTELEN_V  0x7
-#define SPI_MEM_USR_DBYTELEN_S  6
-/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
-/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
-cle_num-1)..*/
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
-/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
-#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
-/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command..*/
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
-#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
-#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-
-#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
-/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
-
-#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
-/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
-
-#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
-/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
-it..*/
-#define SPI_MEM_WB_MODE    0x000000FF
-#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
-#define SPI_MEM_WB_MODE_V  0xFF
-#define SPI_MEM_WB_MODE_S  16
-/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
-#define SPI_MEM_STATUS    0x0000FFFF
-#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
-#define SPI_MEM_STATUS_V  0xFFFF
-#define SPI_MEM_STATUS_S  0
-
-#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
-/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: SPI_CS line keep low when the bit is set..*/
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
-/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_V  0x1
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0,  sram is connected to SUBPINs..*/
-#define SPI_MEM_SSUB_PIN    (BIT(8))
-#define SPI_MEM_SSUB_PIN_M  (BIT(8))
-#define SPI_MEM_SSUB_PIN_V  0x1
-#define SPI_MEM_SSUB_PIN_S  8
-/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0,  flash is connected to SUBPINs..*/
-#define SPI_MEM_FSUB_PIN    (BIT(7))
-#define SPI_MEM_FSUB_PIN_M  (BIT(7))
-#define SPI_MEM_FSUB_PIN_V  0x1
-#define SPI_MEM_FSUB_PIN_S  7
-/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
-evice, such as flash, external RAM and so on..*/
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (BIT(1))
-#define SPI_MEM_CS1_DIS_V  0x1
-#define SPI_MEM_CS1_DIS_S  1
-/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
-evice, such as flash, external RAM and so on..*/
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (BIT(0))
-#define SPI_MEM_CS0_DIS_V  0x1
-#define SPI_MEM_CS0_DIS_S  0
-
-#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
-/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: For SPI1, the value of crc32..*/
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_S  0
-
-#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
-/* SPI_MEM_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
-_ERR will be replied to BRESP/RRESP..*/
-#define SPI_MEM_CLOSE_AXI_INF_EN    (BIT(31))
-#define SPI_MEM_CLOSE_AXI_INF_EN_M  (BIT(31))
-#define SPI_MEM_CLOSE_AXI_INF_EN_V  0x1
-#define SPI_MEM_CLOSE_AXI_INF_EN_S  31
-/* SPI_MEM_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: Set this bit to check AXI read/write the same address region..*/
-#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
-#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
-#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V  0x1
-#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S  30
-/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_qio..*/
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
-#define SPI_MEM_FADDR_QUAD_V  0x1
-#define SPI_MEM_FADDR_QUAD_S  8
-/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
-e same with spi_mem_fread_qio..*/
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_V  0x1
-#define SPI_MEM_FDOUT_QUAD_S  7
-/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
- same with spi_mem_fread_qio..*/
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
-#define SPI_MEM_FDIN_QUAD_V  0x1
-#define SPI_MEM_FDIN_QUAD_S  6
-/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_dio..*/
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
-#define SPI_MEM_FADDR_DUAL_V  0x1
-#define SPI_MEM_FADDR_DUAL_S  5
-/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
- same with spi_mem_fread_dio..*/
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_V  0x1
-#define SPI_MEM_FDOUT_DUAL_S  4
-/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
-same with spi_mem_fread_dio..*/
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
-#define SPI_MEM_FDIN_DUAL_V  0x1
-#define SPI_MEM_FDIN_DUAL_S  3
-/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
-#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
-/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
-#define SPI_MEM_AXI_REQ_EN    (BIT(0))
-#define SPI_MEM_AXI_REQ_EN_M  (BIT(0))
-#define SPI_MEM_AXI_REQ_EN_V  0x1
-#define SPI_MEM_AXI_REQ_EN_S  0
-
-#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
-/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
-e. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
-/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: reserved.*/
-#define SPI_MEM_SRAM_OCT    (BIT(21))
-#define SPI_MEM_SRAM_OCT_M  (BIT(21))
-#define SPI_MEM_SRAM_OCT_V  0x1
-#define SPI_MEM_SRAM_OCT_S  21
-/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
-#define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
-/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
-he register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
-#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
-/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
-. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
-/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
-nd..*/
-#define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
-/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
- operations..*/
-#define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
-#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
-#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
-#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
-/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
-e operations..*/
-#define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
-#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
-#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
-#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
-/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
-le.*/
-#define SPI_MEM_USR_SRAM_QIO    (BIT(2))
-#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
-#define SPI_MEM_USR_SRAM_QIO_V  0x1
-#define SPI_MEM_USR_SRAM_QIO_S  2
-/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
-le.*/
-#define SPI_MEM_USR_SRAM_DIO    (BIT(1))
-#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
-#define SPI_MEM_USR_SRAM_DIO_V  0x1
-#define SPI_MEM_USR_SRAM_DIO_S  1
-/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
-able, 0:disable..*/
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
-
-#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
-/* SPI_MEM_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
-] are always 1. 0: Others..*/
-#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_S  31
-/* SPI_MEM_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
-e always 1. 0: Others..*/
-#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_S  30
-/* SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_IO[7:0] is output by the MSPI controller..*/
-#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
-#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
-#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_S  25
-/* SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_DQS is output by the MSPI controller..*/
-#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
-#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
-#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
-/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
-the signal level of SPI bus is output by the MSPI controller..*/
-#define SPI_MEM_SDUMMY_WOUT    (BIT(23))
-#define SPI_MEM_SDUMMY_WOUT_M  (BIT(23))
-#define SPI_MEM_SDUMMY_WOUT_V  0x1
-#define SPI_MEM_SDUMMY_WOUT_S  23
-/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
-he signal level of SPI bus is output by the MSPI controller..*/
-#define SPI_MEM_SDUMMY_RIN    (BIT(22))
-#define SPI_MEM_SDUMMY_RIN_M  (BIT(22))
-#define SPI_MEM_SDUMMY_RIN_V  0x1
-#define SPI_MEM_SDUMMY_RIN_S  22
-/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SCMD_OCT    (BIT(21))
-#define SPI_MEM_SCMD_OCT_M  (BIT(21))
-#define SPI_MEM_SCMD_OCT_V  0x1
-#define SPI_MEM_SCMD_OCT_S  21
-/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SADDR_OCT    (BIT(20))
-#define SPI_MEM_SADDR_OCT_M  (BIT(20))
-#define SPI_MEM_SADDR_OCT_V  0x1
-#define SPI_MEM_SADDR_OCT_S  20
-/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SDOUT_OCT    (BIT(19))
-#define SPI_MEM_SDOUT_OCT_M  (BIT(19))
-#define SPI_MEM_SDOUT_OCT_V  0x1
-#define SPI_MEM_SDOUT_OCT_S  19
-/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SDIN_OCT    (BIT(18))
-#define SPI_MEM_SDIN_OCT_M  (BIT(18))
-#define SPI_MEM_SDIN_OCT_V  0x1
-#define SPI_MEM_SDIN_OCT_S  18
-/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SCMD_QUAD    (BIT(17))
-#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
-#define SPI_MEM_SCMD_QUAD_V  0x1
-#define SPI_MEM_SCMD_QUAD_S  17
-/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SADDR_QUAD    (BIT(16))
-#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
-#define SPI_MEM_SADDR_QUAD_V  0x1
-#define SPI_MEM_SADDR_QUAD_S  16
-/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SDOUT_QUAD    (BIT(15))
-#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
-#define SPI_MEM_SDOUT_QUAD_V  0x1
-#define SPI_MEM_SDOUT_QUAD_S  15
-/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SDIN_QUAD    (BIT(14))
-#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
-#define SPI_MEM_SDIN_QUAD_V  0x1
-#define SPI_MEM_SDIN_QUAD_S  14
-/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SADDR_DUAL    (BIT(12))
-#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
-#define SPI_MEM_SADDR_DUAL_V  0x1
-#define SPI_MEM_SADDR_DUAL_S  12
-/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SDOUT_DUAL    (BIT(11))
-#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
-#define SPI_MEM_SDOUT_DUAL_V  0x1
-#define SPI_MEM_SDOUT_DUAL_S  11
-/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SDIN_DUAL    (BIT(10))
-#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
-#define SPI_MEM_SDIN_DUAL_V  0x1
-#define SPI_MEM_SDIN_DUAL_S  10
-/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */
-/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
-_mode bit..*/
-#define SPI_MEM_SWB_MODE    0x000000FF
-#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
-#define SPI_MEM_SWB_MODE_V  0xFF
-#define SPI_MEM_SWB_MODE_S  2
-/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is always on..*/
-#define SPI_MEM_SCLK_MODE    0x00000003
-#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
-#define SPI_MEM_SCLK_MODE_V  0x3
-#define SPI_MEM_SCLK_MODE_S  0
-
-#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
-/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
- sram. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
-/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the read command value of command phase
- for sram..*/
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
-
-#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
-/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
- The register value shall be (bit_num-1)..*/
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
-/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the write command value of command phas
-e for sram..*/
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
-
-#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
-/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
-lk is divided from system clock..*/
-#define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
-/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
-lk frequency is system/(spi_mem_clkcnt_N+1).*/
-#define SPI_MEM_SCLKCNT_N    0x000000FF
-#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
-#define SPI_MEM_SCLKCNT_N_V  0xFF
-#define SPI_MEM_SCLKCNT_N_S  16
-/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define SPI_MEM_SCLKCNT_H    0x000000FF
-#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
-#define SPI_MEM_SCLKCNT_H_V  0xFF
-#define SPI_MEM_SCLKCNT_H_S  8
-/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
-#define SPI_MEM_SCLKCNT_L    0x000000FF
-#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
-#define SPI_MEM_SCLKCNT_L_V  0xFF
-#define SPI_MEM_SCLKCNT_L_S  0
-
-#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
-/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
-/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
-#define SPI_MEM_LOCK_DELAY_TIME    0x0000001F
-#define SPI_MEM_LOCK_DELAY_TIME_M  ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S))
-#define SPI_MEM_LOCK_DELAY_TIME_V  0x1F
-#define SPI_MEM_LOCK_DELAY_TIME_S  7
-
-#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
-/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF0    0xFFFFFFFF
-#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
-#define SPI_MEM_BUF0_V  0xFFFFFFFF
-#define SPI_MEM_BUF0_S  0
-
-#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
-/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF1    0xFFFFFFFF
-#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
-#define SPI_MEM_BUF1_V  0xFFFFFFFF
-#define SPI_MEM_BUF1_S  0
-
-#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
-/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF2    0xFFFFFFFF
-#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
-#define SPI_MEM_BUF2_V  0xFFFFFFFF
-#define SPI_MEM_BUF2_S  0
-
-#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
-/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF3    0xFFFFFFFF
-#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
-#define SPI_MEM_BUF3_V  0xFFFFFFFF
-#define SPI_MEM_BUF3_S  0
-
-#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
-/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF4    0xFFFFFFFF
-#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
-#define SPI_MEM_BUF4_V  0xFFFFFFFF
-#define SPI_MEM_BUF4_S  0
-
-#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
-/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF5    0xFFFFFFFF
-#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
-#define SPI_MEM_BUF5_V  0xFFFFFFFF
-#define SPI_MEM_BUF5_S  0
-
-#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
-/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF6    0xFFFFFFFF
-#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
-#define SPI_MEM_BUF6_V  0xFFFFFFFF
-#define SPI_MEM_BUF6_S  0
-
-#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
-/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF7    0xFFFFFFFF
-#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
-#define SPI_MEM_BUF7_V  0xFFFFFFFF
-#define SPI_MEM_BUF7_S  0
-
-#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
-/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF8    0xFFFFFFFF
-#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
-#define SPI_MEM_BUF8_V  0xFFFFFFFF
-#define SPI_MEM_BUF8_S  0
-
-#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
-/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF9    0xFFFFFFFF
-#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
-#define SPI_MEM_BUF9_V  0xFFFFFFFF
-#define SPI_MEM_BUF9_S  0
-
-#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
-/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF10    0xFFFFFFFF
-#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
-#define SPI_MEM_BUF10_V  0xFFFFFFFF
-#define SPI_MEM_BUF10_S  0
-
-#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
-/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF11    0xFFFFFFFF
-#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
-#define SPI_MEM_BUF11_V  0xFFFFFFFF
-#define SPI_MEM_BUF11_S  0
-
-#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
-/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF12    0xFFFFFFFF
-#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
-#define SPI_MEM_BUF12_V  0xFFFFFFFF
-#define SPI_MEM_BUF12_S  0
-
-#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
-/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF13    0xFFFFFFFF
-#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
-#define SPI_MEM_BUF13_V  0xFFFFFFFF
-#define SPI_MEM_BUF13_S  0
-
-#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
-/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF14    0xFFFFFFFF
-#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
-#define SPI_MEM_BUF14_V  0xFFFFFFFF
-#define SPI_MEM_BUF14_S  0
-
-#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
-/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF15    0xFFFFFFFF
-#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
-#define SPI_MEM_BUF15_V  0xFFFFFFFF
-#define SPI_MEM_BUF15_S  0
-
-#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
-/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
-/*description: The command value to wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_CMD    0x0000FFFF
-#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
-#define SPI_MEM_WAITI_CMD_V  0xFFFF
-#define SPI_MEM_WAITI_CMD_S  16
-/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
-/*description: The dummy cycle length when wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is
- 8..*/
-#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_M  (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_V  0x1
-#define SPI_MEM_WAITI_CMD_2B_S  9
-/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI
-_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
-SPI_MEM_WAITI_ADDR_EN is cleared..*/
-#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S))
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x3
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
-/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out ad
-dress in RDSR or read SUS command transfer..*/
-#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_M  (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_V  0x1
-#define SPI_MEM_WAITI_ADDR_EN_S  2
-/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The dummy phase enable when wait flash idle (RDSR).*/
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_V  0x1
-#define SPI_MEM_WAITI_DUMMY_S  1
-/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
- Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
-Suspend/Resume are not supported..*/
-#define SPI_MEM_WAITI_EN    (BIT(0))
-#define SPI_MEM_WAITI_EN_M  (BIT(0))
-#define SPI_MEM_WAITI_EN_V  0x1
-#define SPI_MEM_WAITI_EN_S  0
-
-#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
-/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
-/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
- it will be treated as check pass..*/
-#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
-/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
-s of flash. 0: Only need to check WIP is 0..*/
-#define SPI_MEM_PES_END_EN    (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (BIT(24))
-#define SPI_MEM_PES_END_EN_V  0x1
-#define SPI_MEM_PES_END_EN_S  24
-/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
- of flash. 0: Only need to check WIP is 0..*/
-#define SPI_MEM_PER_END_EN    (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (BIT(23))
-#define SPI_MEM_PER_END_EN_V  0x1
-#define SPI_MEM_PER_END_EN_S  23
-/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
-hen check flash SUS/SUS1/SUS2 status bit.*/
-#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
-#define SPI_MEM_FMEM_RD_SUS_2B_S  22
-/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
-/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
-status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
-out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
-2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
-#define SPI_MEM_PESR_END_MSK    0x0000FFFF
-#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
-#define SPI_MEM_PESR_END_MSK_V  0xFFFF
-#define SPI_MEM_PESR_END_MSK_S  6
-/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable Auto-suspending function..*/
-#define SPI_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_V  0x1
-#define SPI_MEM_FLASH_PES_EN_S  5
-/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
-pplication should send PER after PES is done..*/
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (BIT(4))
-#define SPI_MEM_PES_PER_EN_V  0x1
-#define SPI_MEM_PES_PER_EN_S  4
-/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-program erase suspend command is sent. 0: SPI1 does not wait after program erase
- suspend command is sent..*/
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-program erase resume command is sent. 0: SPI1 does not wait after program erase
-resume command is sent..*/
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program erase suspend bit, program erase suspend operation will be triggered whe
-n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
-isable..*/
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (BIT(1))
-#define SPI_MEM_FLASH_PES_V  0x1
-#define SPI_MEM_FLASH_PES_S  1
-/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: program erase resume bit, program erase suspend operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: di
-sable..*/
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (BIT(0))
-#define SPI_MEM_FLASH_PER_V  0x1
-#define SPI_MEM_FLASH_PER_S  0
-
-#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
-/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
-/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
-/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
-..*/
-#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
-/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */
-/*description: Program/Erase suspend command..*/
-#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFF
-#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
-#define SPI_MEM_FLASH_PES_COMMAND_V  0xFFFF
-#define SPI_MEM_FLASH_PES_COMMAND_S  0
-
-#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
-/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */
-/*description: Program/Erase resume command..*/
-#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFF
-#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
-#define SPI_MEM_FLASH_PER_COMMAND_V  0xFFFF
-#define SPI_MEM_FLASH_PER_COMMAND_S  16
-/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng
-th of Program/Erase Suspend/Resume command is 8..*/
-#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_M  (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x1
-#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
-/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
-#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_V  0x1
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
-#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
-#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
-mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
-after DP command is sent..*/
-#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after RES command is sent..*/
-#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after HPM command is sent..*/
-#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
-#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The status of flash suspend, only used in SPI1..*/
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (BIT(0))
-#define SPI_MEM_FLASH_SUS_V  0x1
-#define SPI_MEM_FLASH_SUS_S  0
-
-#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
-/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
-/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
-/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
-#define SPI_MEM_ECC_ERR_INT_ENA_S  5
-/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_V  0x1
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_V  0x1
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_V  0x1
-#define SPI_MEM_PER_END_INT_ENA_S  0
-
-#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
-/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
-/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
-/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
-#define SPI_MEM_ECC_ERR_INT_CLR_S  5
-/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_V  0x1
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_V  0x1
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_V  0x1
-#define SPI_MEM_PER_END_INT_CLR_S  0
-
-#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
-/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-chip is loosing power and RTC module sends out brown out close flash request to
-SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
- and MSPI returns to idle state. 0: Others..*/
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
- address is invalid by compared to MMU configuration. 0: Others..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
-ite flash request is received. 0: Others..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
-address is invalid by compared to MMU configuration. 0: Others..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
-/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
-is rejected. 0: Others..*/
-#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
-/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
-et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
- times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
-. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
-his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
-ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
-I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
-of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
-RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
-d, this bit will not be triggered..*/
-#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
-#define SPI_MEM_ECC_ERR_INT_RAW_S  5
-/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
-is changed from non idle state to idle state. 0: Others..*/
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
-is changed from non idle state to idle state. It means that SPI_CS raises high.
-0: Others.*/
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
-E is sent and flash is already idle. 0: Others..*/
-#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_V  0x1
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
-mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_V  0x1
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
-mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_V  0x1
-#define SPI_MEM_PER_END_INT_RAW_S  0
-
-#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
-/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ST_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
-/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_ST_S  6
-/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_V  0x1
-#define SPI_MEM_ECC_ERR_INT_ST_S  5
-/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_V  0x1
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_V  0x1
-#define SPI_MEM_PES_END_INT_ST_S  1
-/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_V  0x1
-#define SPI_MEM_PER_END_INT_ST_S  0
-
-#define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
-/* SPI_MEM_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
-#define SPI_MEM_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_FMEM_HYPERBUS_CA_M  (BIT(30))
-#define SPI_MEM_FMEM_HYPERBUS_CA_V  0x1
-#define SPI_MEM_FMEM_HYPERBUS_CA_S  30
-/* SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
-..*/
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V  0x1
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S  29
-/* SPI_MEM_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
-#define SPI_MEM_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_FMEM_CLK_DIFF_INV_M  (BIT(28))
-#define SPI_MEM_FMEM_CLK_DIFF_INV_V  0x1
-#define SPI_MEM_FMEM_CLK_DIFF_INV_S  28
-/* SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S  27
-/* SPI_MEM_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define SPI_MEM_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_FMEM_DQS_CA_IN_M  (BIT(26))
-#define SPI_MEM_FMEM_DQS_CA_IN_V  0x1
-#define SPI_MEM_FMEM_DQS_CA_IN_S  26
-/* SPI_MEM_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define SPI_MEM_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_FMEM_CLK_DIFF_EN_M  (BIT(24))
-#define SPI_MEM_FMEM_CLK_DIFF_EN_V  0x1
-#define SPI_MEM_FMEM_CLK_DIFF_EN_S  24
-/* SPI_MEM_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define SPI_MEM_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_V  0x1
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_S  21
-/* SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD    0x0000007F
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_FMEM_USR_DDR_DQS_THD_S))
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V  0x7F
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S  14
-/* SPI_MEM_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to flash..*/
-#define SPI_MEM_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_MEM_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define SPI_MEM_FMEM_RX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_FMEM_RX_DDR_MSK_EN_S  13
-/* SPI_MEM_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to flash..*/
-#define SPI_MEM_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_MEM_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define SPI_MEM_FMEM_TX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_FMEM_TX_DDR_MSK_EN_S  12
-/* SPI_MEM_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the panda device..*/
-#define SPI_MEM_FMEM_OUTMINBYTELEN    0x0000007F
-#define SPI_MEM_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_FMEM_OUTMINBYTELEN_S))
-#define SPI_MEM_FMEM_OUTMINBYTELEN_V  0x7F
-#define SPI_MEM_FMEM_OUTMINBYTELEN_S  5
-/* SPI_MEM_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define SPI_MEM_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_FMEM_DDR_CMD_DIS_M  (BIT(4))
-#define SPI_MEM_FMEM_DDR_CMD_DIS_V  0x1
-#define SPI_MEM_FMEM_DDR_CMD_DIS_S  4
-/* SPI_MEM_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define SPI_MEM_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_V  0x1
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_S  3
-/* SPI_MEM_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define SPI_MEM_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_V  0x1
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_S  2
-/* SPI_MEM_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define SPI_MEM_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_FMEM_VAR_DUMMY_M  (BIT(1))
-#define SPI_MEM_FMEM_VAR_DUMMY_V  0x1
-#define SPI_MEM_FMEM_VAR_DUMMY_S  1
-/* SPI_MEM_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define SPI_MEM_FMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_FMEM_DDR_EN_M  (BIT(0))
-#define SPI_MEM_FMEM_DDR_EN_V  0x1
-#define SPI_MEM_FMEM_DDR_EN_S  0
-
-#define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD8)
-/* SPI_MEM_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
-]}..*/
-#define SPI_MEM_SMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_SMEM_HYPERBUS_CA_M  (BIT(30))
-#define SPI_MEM_SMEM_HYPERBUS_CA_V  0x1
-#define SPI_MEM_SMEM_HYPERBUS_CA_S  30
-/* SPI_MEM_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
-, 1'b0}..*/
-#define SPI_MEM_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define SPI_MEM_SMEM_OCTA_RAM_ADDR_V  0x1
-#define SPI_MEM_SMEM_OCTA_RAM_ADDR_S  29
-/* SPI_MEM_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
-#define SPI_MEM_SMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_SMEM_CLK_DIFF_INV_M  (BIT(28))
-#define SPI_MEM_SMEM_CLK_DIFF_INV_V  0x1
-#define SPI_MEM_SMEM_CLK_DIFF_INV_S  28
-/* SPI_MEM_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S  27
-/* SPI_MEM_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define SPI_MEM_SMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_SMEM_DQS_CA_IN_M  (BIT(26))
-#define SPI_MEM_SMEM_DQS_CA_IN_V  0x1
-#define SPI_MEM_SMEM_DQS_CA_IN_S  26
-/* SPI_MEM_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define SPI_MEM_SMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_SMEM_CLK_DIFF_EN_M  (BIT(24))
-#define SPI_MEM_SMEM_CLK_DIFF_EN_V  0x1
-#define SPI_MEM_SMEM_CLK_DIFF_EN_S  24
-/* SPI_MEM_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define SPI_MEM_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_SMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define SPI_MEM_SMEM_DDR_DQS_LOOP_V  0x1
-#define SPI_MEM_SMEM_DDR_DQS_LOOP_S  21
-/* SPI_MEM_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define SPI_MEM_SMEM_USR_DDR_DQS_THD    0x0000007F
-#define SPI_MEM_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SMEM_USR_DDR_DQS_THD_S))
-#define SPI_MEM_SMEM_USR_DDR_DQS_THD_V  0x7F
-#define SPI_MEM_SMEM_USR_DDR_DQS_THD_S  14
-/* SPI_MEM_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to external RAM..*/
-#define SPI_MEM_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_MEM_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define SPI_MEM_SMEM_RX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SMEM_RX_DDR_MSK_EN_S  13
-/* SPI_MEM_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to external RAM..*/
-#define SPI_MEM_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_MEM_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define SPI_MEM_SMEM_TX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SMEM_TX_DDR_MSK_EN_S  12
-/* SPI_MEM_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the DDR psram..*/
-#define SPI_MEM_SMEM_OUTMINBYTELEN    0x0000007F
-#define SPI_MEM_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SMEM_OUTMINBYTELEN_S))
-#define SPI_MEM_SMEM_OUTMINBYTELEN_V  0x7F
-#define SPI_MEM_SMEM_OUTMINBYTELEN_S  5
-/* SPI_MEM_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define SPI_MEM_SMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_SMEM_DDR_CMD_DIS_M  (BIT(4))
-#define SPI_MEM_SMEM_DDR_CMD_DIS_V  0x1
-#define SPI_MEM_SMEM_DDR_CMD_DIS_S  4
-/* SPI_MEM_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define SPI_MEM_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_SMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define SPI_MEM_SMEM_DDR_WDAT_SWP_V  0x1
-#define SPI_MEM_SMEM_DDR_WDAT_SWP_S  3
-/* SPI_MEM_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define SPI_MEM_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_SMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define SPI_MEM_SMEM_DDR_RDAT_SWP_V  0x1
-#define SPI_MEM_SMEM_DDR_RDAT_SWP_S  2
-/* SPI_MEM_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define SPI_MEM_SMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_SMEM_VAR_DUMMY_M  (BIT(1))
-#define SPI_MEM_SMEM_VAR_DUMMY_V  0x1
-#define SPI_MEM_SMEM_VAR_DUMMY_S  1
-/* SPI_MEM_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define SPI_MEM_SMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_SMEM_DDR_EN_M  (BIT(0))
-#define SPI_MEM_SMEM_DDR_EN_V  0x1
-#define SPI_MEM_SMEM_DDR_EN_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x100)
-/* SPI_MEM_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_FMEM_PMS0_ECC    (BIT(2))
-#define SPI_MEM_FMEM_PMS0_ECC_M  (BIT(2))
-#define SPI_MEM_FMEM_PMS0_ECC_V  0x1
-#define SPI_MEM_FMEM_PMS0_ECC_S  2
-/* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_MEM_FMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_FMEM_PMS0_WR_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS0_WR_ATTR_S  1
-/* SPI_MEM_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_MEM_FMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_FMEM_PMS0_RD_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS0_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x104)
-/* SPI_MEM_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_FMEM_PMS1_ECC    (BIT(2))
-#define SPI_MEM_FMEM_PMS1_ECC_M  (BIT(2))
-#define SPI_MEM_FMEM_PMS1_ECC_V  0x1
-#define SPI_MEM_FMEM_PMS1_ECC_S  2
-/* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_MEM_FMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_FMEM_PMS1_WR_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS1_WR_ATTR_S  1
-/* SPI_MEM_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_MEM_FMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_FMEM_PMS1_RD_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS1_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x108)
-/* SPI_MEM_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_FMEM_PMS2_ECC    (BIT(2))
-#define SPI_MEM_FMEM_PMS2_ECC_M  (BIT(2))
-#define SPI_MEM_FMEM_PMS2_ECC_V  0x1
-#define SPI_MEM_FMEM_PMS2_ECC_S  2
-/* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_MEM_FMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_FMEM_PMS2_WR_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS2_WR_ATTR_S  1
-/* SPI_MEM_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_MEM_FMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_FMEM_PMS2_RD_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS2_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10C)
-/* SPI_MEM_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_FMEM_PMS3_ECC    (BIT(2))
-#define SPI_MEM_FMEM_PMS3_ECC_M  (BIT(2))
-#define SPI_MEM_FMEM_PMS3_ECC_V  0x1
-#define SPI_MEM_FMEM_PMS3_ECC_S  2
-/* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_MEM_FMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_FMEM_PMS3_WR_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS3_WR_ATTR_S  1
-/* SPI_MEM_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_MEM_FMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_FMEM_PMS3_RD_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS3_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x110)
-/* SPI_MEM_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: SPI1 flash ACE section $n start address value.*/
-#define SPI_MEM_FMEM_PMS0_ADDR_S    0x03FFFFFF
-#define SPI_MEM_FMEM_PMS0_ADDR_S_M  ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S))
-#define SPI_MEM_FMEM_PMS0_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_FMEM_PMS0_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x114)
-/* SPI_MEM_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
-/*description: SPI1 flash ACE section $n start address value.*/
-#define SPI_MEM_FMEM_PMS1_ADDR_S    0x03FFFFFF
-#define SPI_MEM_FMEM_PMS1_ADDR_S_M  ((SPI_MEM_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_FMEM_PMS1_ADDR_S_S))
-#define SPI_MEM_FMEM_PMS1_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_FMEM_PMS1_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x118)
-/* SPI_MEM_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
-/*description: SPI1 flash ACE section $n start address value.*/
-#define SPI_MEM_FMEM_PMS2_ADDR_S    0x03FFFFFF
-#define SPI_MEM_FMEM_PMS2_ADDR_S_M  ((SPI_MEM_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_FMEM_PMS2_ADDR_S_S))
-#define SPI_MEM_FMEM_PMS2_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_FMEM_PMS2_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x11C)
-/* SPI_MEM_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
-/*description: SPI1 flash ACE section $n start address value.*/
-#define SPI_MEM_FMEM_PMS3_ADDR_S    0x03FFFFFF
-#define SPI_MEM_FMEM_PMS3_ADDR_S_M  ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S))
-#define SPI_MEM_FMEM_PMS3_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_FMEM_PMS3_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x120)
-/* SPI_MEM_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_FMEM_PMS0_SIZE    0x00003FFF
-#define SPI_MEM_FMEM_PMS0_SIZE_M  ((SPI_MEM_FMEM_PMS0_SIZE_V)<<(SPI_MEM_FMEM_PMS0_SIZE_S))
-#define SPI_MEM_FMEM_PMS0_SIZE_V  0x3FFF
-#define SPI_MEM_FMEM_PMS0_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x124)
-/* SPI_MEM_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_FMEM_PMS1_SIZE    0x00003FFF
-#define SPI_MEM_FMEM_PMS1_SIZE_M  ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S))
-#define SPI_MEM_FMEM_PMS1_SIZE_V  0x3FFF
-#define SPI_MEM_FMEM_PMS1_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x128)
-/* SPI_MEM_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_FMEM_PMS2_SIZE    0x00003FFF
-#define SPI_MEM_FMEM_PMS2_SIZE_M  ((SPI_MEM_FMEM_PMS2_SIZE_V)<<(SPI_MEM_FMEM_PMS2_SIZE_S))
-#define SPI_MEM_FMEM_PMS2_SIZE_V  0x3FFF
-#define SPI_MEM_FMEM_PMS2_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x12C)
-/* SPI_MEM_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_FMEM_PMS3_SIZE    0x00003FFF
-#define SPI_MEM_FMEM_PMS3_SIZE_M  ((SPI_MEM_FMEM_PMS3_SIZE_V)<<(SPI_MEM_FMEM_PMS3_SIZE_S))
-#define SPI_MEM_FMEM_PMS3_SIZE_V  0x3FFF
-#define SPI_MEM_FMEM_PMS3_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x130)
-/* SPI_MEM_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SMEM_PMS0_ECC    (BIT(2))
-#define SPI_MEM_SMEM_PMS0_ECC_M  (BIT(2))
-#define SPI_MEM_SMEM_PMS0_ECC_V  0x1
-#define SPI_MEM_SMEM_PMS0_ECC_S  2
-/* SPI_MEM_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_MEM_SMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SMEM_PMS0_WR_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS0_WR_ATTR_S  1
-/* SPI_MEM_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_MEM_SMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SMEM_PMS0_RD_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS0_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x134)
-/* SPI_MEM_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SMEM_PMS1_ECC    (BIT(2))
-#define SPI_MEM_SMEM_PMS1_ECC_M  (BIT(2))
-#define SPI_MEM_SMEM_PMS1_ECC_V  0x1
-#define SPI_MEM_SMEM_PMS1_ECC_S  2
-/* SPI_MEM_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_MEM_SMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SMEM_PMS1_WR_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS1_WR_ATTR_S  1
-/* SPI_MEM_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_MEM_SMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SMEM_PMS1_RD_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS1_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x138)
-/* SPI_MEM_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SMEM_PMS2_ECC    (BIT(2))
-#define SPI_MEM_SMEM_PMS2_ECC_M  (BIT(2))
-#define SPI_MEM_SMEM_PMS2_ECC_V  0x1
-#define SPI_MEM_SMEM_PMS2_ECC_S  2
-/* SPI_MEM_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_MEM_SMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SMEM_PMS2_WR_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS2_WR_ATTR_S  1
-/* SPI_MEM_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_MEM_SMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SMEM_PMS2_RD_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS2_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x13C)
-/* SPI_MEM_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SMEM_PMS3_ECC    (BIT(2))
-#define SPI_MEM_SMEM_PMS3_ECC_M  (BIT(2))
-#define SPI_MEM_SMEM_PMS3_ECC_V  0x1
-#define SPI_MEM_SMEM_PMS3_ECC_S  2
-/* SPI_MEM_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_MEM_SMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SMEM_PMS3_WR_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS3_WR_ATTR_S  1
-/* SPI_MEM_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_MEM_SMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SMEM_PMS3_RD_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS3_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x140)
-/* SPI_MEM_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: SPI1 external RAM ACE section $n start address value.*/
-#define SPI_MEM_SMEM_PMS0_ADDR_S    0x03FFFFFF
-#define SPI_MEM_SMEM_PMS0_ADDR_S_M  ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S))
-#define SPI_MEM_SMEM_PMS0_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_SMEM_PMS0_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x144)
-/* SPI_MEM_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
-/*description: SPI1 external RAM ACE section $n start address value.*/
-#define SPI_MEM_SMEM_PMS1_ADDR_S    0x03FFFFFF
-#define SPI_MEM_SMEM_PMS1_ADDR_S_M  ((SPI_MEM_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SMEM_PMS1_ADDR_S_S))
-#define SPI_MEM_SMEM_PMS1_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_SMEM_PMS1_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x148)
-/* SPI_MEM_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
-/*description: SPI1 external RAM ACE section $n start address value.*/
-#define SPI_MEM_SMEM_PMS2_ADDR_S    0x03FFFFFF
-#define SPI_MEM_SMEM_PMS2_ADDR_S_M  ((SPI_MEM_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SMEM_PMS2_ADDR_S_S))
-#define SPI_MEM_SMEM_PMS2_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_SMEM_PMS2_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14C)
-/* SPI_MEM_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
-/*description: SPI1 external RAM ACE section $n start address value.*/
-#define SPI_MEM_SMEM_PMS3_ADDR_S    0x03FFFFFF
-#define SPI_MEM_SMEM_PMS3_ADDR_S_M  ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S))
-#define SPI_MEM_SMEM_PMS3_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_SMEM_PMS3_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x150)
-/* SPI_MEM_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SMEM_PMS0_SIZE    0x00003FFF
-#define SPI_MEM_SMEM_PMS0_SIZE_M  ((SPI_MEM_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SMEM_PMS0_SIZE_S))
-#define SPI_MEM_SMEM_PMS0_SIZE_V  0x3FFF
-#define SPI_MEM_SMEM_PMS0_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x154)
-/* SPI_MEM_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SMEM_PMS1_SIZE    0x00003FFF
-#define SPI_MEM_SMEM_PMS1_SIZE_M  ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S))
-#define SPI_MEM_SMEM_PMS1_SIZE_V  0x3FFF
-#define SPI_MEM_SMEM_PMS1_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x158)
-/* SPI_MEM_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SMEM_PMS2_SIZE    0x00003FFF
-#define SPI_MEM_SMEM_PMS2_SIZE_M  ((SPI_MEM_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SMEM_PMS2_SIZE_S))
-#define SPI_MEM_SMEM_PMS2_SIZE_V  0x3FFF
-#define SPI_MEM_SMEM_PMS2_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x15C)
-/* SPI_MEM_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SMEM_PMS3_SIZE    0x00003FFF
-#define SPI_MEM_SMEM_PMS3_SIZE_M  ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S))
-#define SPI_MEM_SMEM_PMS3_SIZE_V  0x3FFF
-#define SPI_MEM_SMEM_PMS3_SIZE_S  0
-
-#define SPI_MEM_PMS_REJECT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x164)
-/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
-/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
- error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_IVD    (BIT(31))
-#define SPI_MEM_PMS_IVD_M  (BIT(31))
-#define SPI_MEM_PMS_IVD_V  0x1
-#define SPI_MEM_PMS_IVD_S  31
-/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
- is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_V  0x1
-#define SPI_MEM_PMS_MULTI_HIT_S  30
-/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_ST    (BIT(29))
-#define SPI_MEM_PMS_ST_M  (BIT(29))
-#define SPI_MEM_PMS_ST_V  0x1
-#define SPI_MEM_PMS_ST_S  29
-/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
-_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_LD    (BIT(28))
-#define SPI_MEM_PMS_LD_M  (BIT(28))
-#define SPI_MEM_PMS_LD_V  0x1
-#define SPI_MEM_PMS_LD_S  28
-/* SPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
-#define SPI_MEM_PM_EN    (BIT(26))
-#define SPI_MEM_PM_EN_M  (BIT(26))
-#define SPI_MEM_PM_EN_V  0x1
-#define SPI_MEM_PM_EN_S  26
-/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_REJECT_ADDR    0x03FFFFFF
-#define SPI_MEM_REJECT_ADDR_M  ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S))
-#define SPI_MEM_REJECT_ADDR_V  0x3FFFFFF
-#define SPI_MEM_REJECT_ADDR_S  0
-
-#define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x168)
-/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */
-/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
- to byte 0 bit 0 to byte 15 bit 7).*/
-#define SPI_MEM_ECC_ERR_BITS    0x0000007F
-#define SPI_MEM_ECC_ERR_BITS_M  ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S))
-#define SPI_MEM_ECC_ERR_BITS_V  0x7F
-#define SPI_MEM_ECC_ERR_BITS_S  25
-/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */
-/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
-ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
-R record the first ECC error information..*/
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
-/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */
-/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
-#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_USR_ECC_ADDR_EN_S  21
-/* SPI_MEM_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
-is bit should be 0. Otherwise, this bit should be 1..*/
-#define SPI_MEM_FMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_MEM_FMEM_ECC_ADDR_EN_M  (BIT(20))
-#define SPI_MEM_FMEM_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_FMEM_ECC_ADDR_EN_S  20
-/* SPI_MEM_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
-1024 bytes. 3: 2048 bytes..*/
-#define SPI_MEM_FMEM_PAGE_SIZE    0x00000003
-#define SPI_MEM_FMEM_PAGE_SIZE_M  ((SPI_MEM_FMEM_PAGE_SIZE_V)<<(SPI_MEM_FMEM_PAGE_SIZE_S))
-#define SPI_MEM_FMEM_PAGE_SIZE_V  0x3
-#define SPI_MEM_FMEM_PAGE_SIZE_S  18
-/* SPI_MEM_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
-h..*/
-#define SPI_MEM_FMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_MEM_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define SPI_MEM_FMEM_ECC_ERR_INT_EN_V  0x1
-#define SPI_MEM_FMEM_ECC_ERR_INT_EN_S  17
-/* SPI_MEM_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */
-/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
-upt..*/
-#define SPI_MEM_FMEM_ECC_ERR_INT_NUM    0x0000003F
-#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_FMEM_ECC_ERR_INT_NUM_S))
-#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_V  0x3F
-#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_S  11
-
-#define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x16C)
-/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[31:26] ;default: 6'd0 ; */
-/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define SPI_MEM_ECC_ERR_CNT    0x0000003F
-#define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
-#define SPI_MEM_ECC_ERR_CNT_V  0x3F
-#define SPI_MEM_ECC_ERR_CNT_S  26
-/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define SPI_MEM_ECC_ERR_ADDR    0x03FFFFFF
-#define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
-#define SPI_MEM_ECC_ERR_ADDR_V  0x3FFFFFF
-#define SPI_MEM_ECC_ERR_ADDR_S  0
-
-#define SPI_MEM_AXI_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x170)
-/* SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
-and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
-#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
-#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
-#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
-#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
-/* SPI_MEM_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define SPI_MEM_WBLEN_AFIFO_REMPTY    (BIT(30))
-#define SPI_MEM_WBLEN_AFIFO_REMPTY_M  (BIT(30))
-#define SPI_MEM_WBLEN_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_WBLEN_AFIFO_REMPTY_S  30
-/* SPI_MEM_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
-/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define SPI_MEM_WDATA_AFIFO_REMPTY    (BIT(29))
-#define SPI_MEM_WDATA_AFIFO_REMPTY_M  (BIT(29))
-#define SPI_MEM_WDATA_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_WDATA_AFIFO_REMPTY_S  29
-/* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
-/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define SPI_MEM_RADDR_AFIFO_REMPTY    (BIT(28))
-#define SPI_MEM_RADDR_AFIFO_REMPTY_M  (BIT(28))
-#define SPI_MEM_RADDR_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_RADDR_AFIFO_REMPTY_S  28
-/* SPI_MEM_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define SPI_MEM_RDATA_AFIFO_REMPTY    (BIT(27))
-#define SPI_MEM_RDATA_AFIFO_REMPTY_M  (BIT(27))
-#define SPI_MEM_RDATA_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_RDATA_AFIFO_REMPTY_S  27
-/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
-/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
- and SPI0 transfers are done. 0: Others..*/
-#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_V  0x1
-#define SPI_MEM_ALL_FIFO_EMPTY_S  26
-/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
-ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
-H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
-#define SPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
-#define SPI_MEM_AXI_ERR_ADDR_M  ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S))
-#define SPI_MEM_AXI_ERR_ADDR_V  0x3FFFFFF
-#define SPI_MEM_AXI_ERR_ADDR_S  0
-
-#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x174)
-/* SPI_MEM_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
-ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
-#define SPI_MEM_SMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_MEM_SMEM_ECC_ADDR_EN_M  (BIT(20))
-#define SPI_MEM_SMEM_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_SMEM_ECC_ADDR_EN_S  20
-/* SPI_MEM_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */
-/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
-es. 2: 1024 bytes. 3: 2048 bytes..*/
-#define SPI_MEM_SMEM_PAGE_SIZE    0x00000003
-#define SPI_MEM_SMEM_PAGE_SIZE_M  ((SPI_MEM_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SMEM_PAGE_SIZE_S))
-#define SPI_MEM_SMEM_PAGE_SIZE_V  0x3
-#define SPI_MEM_SMEM_PAGE_SIZE_S  18
-/* SPI_MEM_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
-rnal RAM..*/
-#define SPI_MEM_SMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_MEM_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define SPI_MEM_SMEM_ECC_ERR_INT_EN_V  0x1
-#define SPI_MEM_SMEM_ECC_ERR_INT_EN_S  17
-
-#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x180)
-/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
-#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_V  0x1
-#define SPI_MEM_TIMING_CALI_UPDATE_S  6
-/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
-lash..*/
-#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_V  0x1
-#define SPI_MEM_DLL_TIMING_CALI_S  5
-/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_TIMING_CALI_V  0x1
-#define SPI_MEM_TIMING_CALI_S  1
-/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable timing adjust clock for all reading operations..*/
-#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x184)
-/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DINS_MODE    0x00000007
-#define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
-#define SPI_MEM_DINS_MODE_V  0x7
-#define SPI_MEM_DINS_MODE_S  24
-/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN7_MODE    0x00000007
-#define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
-#define SPI_MEM_DIN7_MODE_V  0x7
-#define SPI_MEM_DIN7_MODE_S  21
-/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN6_MODE    0x00000007
-#define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
-#define SPI_MEM_DIN6_MODE_V  0x7
-#define SPI_MEM_DIN6_MODE_S  18
-/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN5_MODE    0x00000007
-#define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
-#define SPI_MEM_DIN5_MODE_V  0x7
-#define SPI_MEM_DIN5_MODE_S  15
-/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN4_MODE    0x00000007
-#define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
-#define SPI_MEM_DIN4_MODE_V  0x7
-#define SPI_MEM_DIN4_MODE_S  12
-/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN3_MODE    0x00000007
-#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
-#define SPI_MEM_DIN3_MODE_V  0x7
-#define SPI_MEM_DIN3_MODE_S  9
-/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN2_MODE    0x00000007
-#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
-#define SPI_MEM_DIN2_MODE_V  0x7
-#define SPI_MEM_DIN2_MODE_S  6
-/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN1_MODE    0x00000007
-#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
-#define SPI_MEM_DIN1_MODE_V  0x7
-#define SPI_MEM_DIN1_MODE_S  3
-/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN0_MODE    0x00000007
-#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
-#define SPI_MEM_DIN0_MODE_V  0x7
-#define SPI_MEM_DIN0_MODE_S  0
-
-#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x188)
-/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DINS_NUM    0x00000003
-#define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
-#define SPI_MEM_DINS_NUM_V  0x3
-#define SPI_MEM_DINS_NUM_S  16
-/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN7_NUM    0x00000003
-#define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
-#define SPI_MEM_DIN7_NUM_V  0x3
-#define SPI_MEM_DIN7_NUM_S  14
-/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN6_NUM    0x00000003
-#define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
-#define SPI_MEM_DIN6_NUM_V  0x3
-#define SPI_MEM_DIN6_NUM_S  12
-/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN5_NUM    0x00000003
-#define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
-#define SPI_MEM_DIN5_NUM_V  0x3
-#define SPI_MEM_DIN5_NUM_S  10
-/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN4_NUM    0x00000003
-#define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
-#define SPI_MEM_DIN4_NUM_V  0x3
-#define SPI_MEM_DIN4_NUM_S  8
-/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN3_NUM    0x00000003
-#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
-#define SPI_MEM_DIN3_NUM_V  0x3
-#define SPI_MEM_DIN3_NUM_S  6
-/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN2_NUM    0x00000003
-#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
-#define SPI_MEM_DIN2_NUM_V  0x3
-#define SPI_MEM_DIN2_NUM_S  4
-/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN1_NUM    0x00000003
-#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
-#define SPI_MEM_DIN1_NUM_V  0x3
-#define SPI_MEM_DIN1_NUM_S  2
-/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN0_NUM    0x00000003
-#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
-#define SPI_MEM_DIN0_NUM_V  0x3
-#define SPI_MEM_DIN0_NUM_S  0
-
-#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18C)
-/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_DOUTS_MODE_M  (BIT(8))
-#define SPI_MEM_DOUTS_MODE_V  0x1
-#define SPI_MEM_DOUTS_MODE_S  8
-/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_DOUT7_MODE_M  (BIT(7))
-#define SPI_MEM_DOUT7_MODE_V  0x1
-#define SPI_MEM_DOUT7_MODE_S  7
-/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_DOUT6_MODE_M  (BIT(6))
-#define SPI_MEM_DOUT6_MODE_V  0x1
-#define SPI_MEM_DOUT6_MODE_S  6
-/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_DOUT5_MODE_M  (BIT(5))
-#define SPI_MEM_DOUT5_MODE_V  0x1
-#define SPI_MEM_DOUT5_MODE_S  5
-/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_DOUT4_MODE_M  (BIT(4))
-#define SPI_MEM_DOUT4_MODE_V  0x1
-#define SPI_MEM_DOUT4_MODE_S  4
-/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_DOUT3_MODE_S  3
-/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_DOUT2_MODE_S  2
-/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_DOUT1_MODE_S  1
-/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x190)
-/* SPI_MEM_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
-XT_RAM..*/
-#define SPI_MEM_SMEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_SMEM_DLL_TIMING_CALI_M  (BIT(5))
-#define SPI_MEM_SMEM_DLL_TIMING_CALI_V  0x1
-#define SPI_MEM_SMEM_DLL_TIMING_CALI_S  5
-/* SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
-#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
-ations..*/
-#define SPI_MEM_SMEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_SMEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_SMEM_TIMING_CALI_V  0x1
-#define SPI_MEM_SMEM_TIMING_CALI_S  1
-/* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
-ns..*/
-#define SPI_MEM_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_SMEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_SMEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_SMEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x194)
-/* SPI_MEM_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DINS_MODE    0x00000007
-#define SPI_MEM_SMEM_DINS_MODE_M  ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S))
-#define SPI_MEM_SMEM_DINS_MODE_V  0x7
-#define SPI_MEM_SMEM_DINS_MODE_S  24
-/* SPI_MEM_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN7_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN7_MODE_M  ((SPI_MEM_SMEM_DIN7_MODE_V)<<(SPI_MEM_SMEM_DIN7_MODE_S))
-#define SPI_MEM_SMEM_DIN7_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN7_MODE_S  21
-/* SPI_MEM_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN6_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN6_MODE_M  ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S))
-#define SPI_MEM_SMEM_DIN6_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN6_MODE_S  18
-/* SPI_MEM_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN5_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN5_MODE_M  ((SPI_MEM_SMEM_DIN5_MODE_V)<<(SPI_MEM_SMEM_DIN5_MODE_S))
-#define SPI_MEM_SMEM_DIN5_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN5_MODE_S  15
-/* SPI_MEM_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN4_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN4_MODE_M  ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S))
-#define SPI_MEM_SMEM_DIN4_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN4_MODE_S  12
-/* SPI_MEM_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN3_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN3_MODE_M  ((SPI_MEM_SMEM_DIN3_MODE_V)<<(SPI_MEM_SMEM_DIN3_MODE_S))
-#define SPI_MEM_SMEM_DIN3_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN3_MODE_S  9
-/* SPI_MEM_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN2_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN2_MODE_M  ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S))
-#define SPI_MEM_SMEM_DIN2_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN2_MODE_S  6
-/* SPI_MEM_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN1_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN1_MODE_M  ((SPI_MEM_SMEM_DIN1_MODE_V)<<(SPI_MEM_SMEM_DIN1_MODE_S))
-#define SPI_MEM_SMEM_DIN1_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN1_MODE_S  3
-/* SPI_MEM_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN0_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN0_MODE_M  ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S))
-#define SPI_MEM_SMEM_DIN0_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x198)
-/* SPI_MEM_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DINS_NUM    0x00000003
-#define SPI_MEM_SMEM_DINS_NUM_M  ((SPI_MEM_SMEM_DINS_NUM_V)<<(SPI_MEM_SMEM_DINS_NUM_S))
-#define SPI_MEM_SMEM_DINS_NUM_V  0x3
-#define SPI_MEM_SMEM_DINS_NUM_S  16
-/* SPI_MEM_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN7_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN7_NUM_M  ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S))
-#define SPI_MEM_SMEM_DIN7_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN7_NUM_S  14
-/* SPI_MEM_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN6_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN6_NUM_M  ((SPI_MEM_SMEM_DIN6_NUM_V)<<(SPI_MEM_SMEM_DIN6_NUM_S))
-#define SPI_MEM_SMEM_DIN6_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN6_NUM_S  12
-/* SPI_MEM_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN5_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN5_NUM_M  ((SPI_MEM_SMEM_DIN5_NUM_V)<<(SPI_MEM_SMEM_DIN5_NUM_S))
-#define SPI_MEM_SMEM_DIN5_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN5_NUM_S  10
-/* SPI_MEM_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN4_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN4_NUM_M  ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S))
-#define SPI_MEM_SMEM_DIN4_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN4_NUM_S  8
-/* SPI_MEM_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN3_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN3_NUM_M  ((SPI_MEM_SMEM_DIN3_NUM_V)<<(SPI_MEM_SMEM_DIN3_NUM_S))
-#define SPI_MEM_SMEM_DIN3_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN3_NUM_S  6
-/* SPI_MEM_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN2_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN2_NUM_M  ((SPI_MEM_SMEM_DIN2_NUM_V)<<(SPI_MEM_SMEM_DIN2_NUM_S))
-#define SPI_MEM_SMEM_DIN2_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN2_NUM_S  4
-/* SPI_MEM_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN1_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN1_NUM_M  ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S))
-#define SPI_MEM_SMEM_DIN1_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN1_NUM_S  2
-/* SPI_MEM_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN0_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN0_NUM_M  ((SPI_MEM_SMEM_DIN0_NUM_V)<<(SPI_MEM_SMEM_DIN0_NUM_S))
-#define SPI_MEM_SMEM_DIN0_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN0_NUM_S  0
-
-#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x19C)
-/* SPI_MEM_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_SMEM_DOUTS_MODE_M  (BIT(8))
-#define SPI_MEM_SMEM_DOUTS_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUTS_MODE_S  8
-/* SPI_MEM_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_SMEM_DOUT7_MODE_M  (BIT(7))
-#define SPI_MEM_SMEM_DOUT7_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT7_MODE_S  7
-/* SPI_MEM_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_SMEM_DOUT6_MODE_M  (BIT(6))
-#define SPI_MEM_SMEM_DOUT6_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT6_MODE_S  6
-/* SPI_MEM_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_SMEM_DOUT5_MODE_M  (BIT(5))
-#define SPI_MEM_SMEM_DOUT5_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT5_MODE_S  5
-/* SPI_MEM_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_SMEM_DOUT4_MODE_M  (BIT(4))
-#define SPI_MEM_SMEM_DOUT4_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT4_MODE_S  4
-/* SPI_MEM_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_SMEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_SMEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT3_MODE_S  3
-/* SPI_MEM_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_SMEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_SMEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT2_MODE_S  2
-/* SPI_MEM_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_SMEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_SMEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT1_MODE_S  1
-/* SPI_MEM_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_SMEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_SMEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A0)
-/* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
- transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
-er whether there is an ECC region or not..*/
-#define SPI_MEM_SMEM_SPLIT_TRANS_EN    (BIT(31))
-#define SPI_MEM_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
-#define SPI_MEM_SMEM_SPLIT_TRANS_EN_V  0x1
-#define SPI_MEM_SMEM_SPLIT_TRANS_EN_S  31
-/* SPI_MEM_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
-SPI core clock cycles..*/
-#define SPI_MEM_SMEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SMEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_SMEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_SMEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses external RAM..*/
-#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
-#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V  0x1
-#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S  16
-/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */
-/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
-en accesses external RAM..*/
-#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
-#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/* SPI_MEM_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
-ycles in ECC mode when accessed external RAM..*/
-#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME    0x00000007
-#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S))
-#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V  0x7
-#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S  12
-/* SPI_MEM_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */
-/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
-re combined with spi_mem_cs_hold bit..*/
-#define SPI_MEM_SMEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S))
-#define SPI_MEM_SMEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_SMEM_CS_HOLD_TIME_S  7
-/* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */
-/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
-pi_mem_cs_setup bit..*/
-#define SPI_MEM_SMEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SMEM_CS_SETUP_TIME_S))
-#define SPI_MEM_SMEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_SMEM_CS_SETUP_TIME_S  2
-/* SPI_MEM_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
-le..*/
-#define SPI_MEM_SMEM_CS_HOLD    (BIT(1))
-#define SPI_MEM_SMEM_CS_HOLD_M  (BIT(1))
-#define SPI_MEM_SMEM_CS_HOLD_V  0x1
-#define SPI_MEM_SMEM_CS_HOLD_S  1
-/* SPI_MEM_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
-isable..*/
-#define SPI_MEM_SMEM_CS_SETUP    (BIT(0))
-#define SPI_MEM_SMEM_CS_SETUP_M  (BIT(0))
-#define SPI_MEM_SMEM_CS_SETUP_V  0x1
-#define SPI_MEM_SMEM_CS_SETUP_S  0
-
-#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x200)
-/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
-#define SPI_MEM_CLK_EN    (BIT(0))
-#define SPI_MEM_CLK_EN_M  (BIT(0))
-#define SPI_MEM_CLK_EN_V  0x1
-#define SPI_MEM_CLK_EN_S  0
-
-#define SPI_MEM_MMU_ITEM_CONTENT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x37C)
-/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: MSPI-MMU item content.*/
-#define SPI_MEM_MMU_ITEM_CONTENT    0xFFFFFFFF
-#define SPI_MEM_MMU_ITEM_CONTENT_M  ((SPI_MEM_MMU_ITEM_CONTENT_V)<<(SPI_MEM_MMU_ITEM_CONTENT_S))
-#define SPI_MEM_MMU_ITEM_CONTENT_V  0xFFFFFFFF
-#define SPI_MEM_MMU_ITEM_CONTENT_S  0
-
-#define SPI_MEM_MMU_ITEM_INDEX_REG(i)          (REG_SPI_MEM_BASE(i) + 0x380)
-/* SPI_MEM_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: MSPI-MMU item index.*/
-#define SPI_MEM_MMU_ITEM_INDEX    0xFFFFFFFF
-#define SPI_MEM_MMU_ITEM_INDEX_M  ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S))
-#define SPI_MEM_MMU_ITEM_INDEX_V  0xFFFFFFFF
-#define SPI_MEM_MMU_ITEM_INDEX_S  0
-
-#define SPI_MEM_MMU_POWER_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x384)
-/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
-#define SPI_MEM_RDN_RESULT    (BIT(31))
-#define SPI_MEM_RDN_RESULT_M  (BIT(31))
-#define SPI_MEM_RDN_RESULT_V  0x1
-#define SPI_MEM_RDN_RESULT_S  31
-/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: ECO register enable bit.*/
-#define SPI_MEM_RDN_ENA    (BIT(30))
-#define SPI_MEM_RDN_ENA_M  (BIT(30))
-#define SPI_MEM_RDN_ENA_V  0x1
-#define SPI_MEM_RDN_ENA_S  30
-/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */
-/*description: MMU PSRAM aux control register.*/
-#define SPI_MEM_AUX_CTRL    0x00003FFF
-#define SPI_MEM_AUX_CTRL_M  ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S))
-#define SPI_MEM_AUX_CTRL_V  0x3FFF
-#define SPI_MEM_AUX_CTRL_S  16
-/* SPI_MEM_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
-/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/
-#define SPI_MEM_MMU_PAGE_SIZE    0x00000003
-#define SPI_MEM_MMU_PAGE_SIZE_M  ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S))
-#define SPI_MEM_MMU_PAGE_SIZE_V  0x3
-#define SPI_MEM_MMU_PAGE_SIZE_S  3
-/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
- controlled by rtc..*/
-#define SPI_MEM_MMU_MEM_FORCE_PU    (BIT(2))
-#define SPI_MEM_MMU_MEM_FORCE_PU_M  (BIT(2))
-#define SPI_MEM_MMU_MEM_FORCE_PU_V  0x1
-#define SPI_MEM_MMU_MEM_FORCE_PU_S  2
-/* SPI_MEM_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to force mmu-memory powerdown.*/
-#define SPI_MEM_MMU_MEM_FORCE_PD    (BIT(1))
-#define SPI_MEM_MMU_MEM_FORCE_PD_M  (BIT(1))
-#define SPI_MEM_MMU_MEM_FORCE_PD_V  0x1
-#define SPI_MEM_MMU_MEM_FORCE_PD_S  1
-/* SPI_MEM_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable mmu-memory clock force on.*/
-#define SPI_MEM_MMU_MEM_FORCE_ON    (BIT(0))
-#define SPI_MEM_MMU_MEM_FORCE_ON_M  (BIT(0))
-#define SPI_MEM_MMU_MEM_FORCE_ON_V  0x1
-#define SPI_MEM_MMU_MEM_FORCE_ON_S  0
-
-#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F0)
-/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO high register.*/
-#define SPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_HIGH_M  ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S))
-#define SPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_HIGH_S  0
-
-#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F4)
-/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO low register.*/
-#define SPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_LOW_M  ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S))
-#define SPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_LOW_S  0
-
-#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
-/* SPI_MEM_DATE : R/W; bitpos: [27:0] ;default: 35663920; */
-/*description: SPI0 register version..*/
-/* SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128; */
-/*description: SPI1 register version..*/
-#define SPI_MEM_DATE    0x0FFFFFFF
-#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
-#define SPI_MEM_DATE_V  0xFFFFFFF
-#define SPI_MEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/spi_mem_struct.h b/components/soc/esp32c6/include/soc/spi_mem_struct.h
deleted file mode 100644
index 9e2f7c1d3ba..00000000000
--- a/components/soc/esp32c6/include/soc/spi_mem_struct.h
+++ /dev/null
@@ -1,1081 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct spi_mem_dev_s {
-    union {
-        struct {
-            uint32_t mst_st                        :    4;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
-            uint32_t slv_st                        :    4;  /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
-            uint32_t reserved8                     :    9;  /*reserved*/
-            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t usr                           :    1;  /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
-            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/
-            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/
-            uint32_t fdummy_rin                    :    1;  /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/
-            uint32_t fdummy_wout                   :    1;  /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/
-            uint32_t fdout_oct                     :    1;  /*Apply 8 signals during write-data phase 1:enable 0: disable*/
-            uint32_t fdin_oct                      :    1;  /*Apply 8 signals during read-data phase 1:enable 0: disable*/
-            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during address phase 1:enable 0: disable*/
-            uint32_t reserved7                     :    1;  /*reserved*/
-            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
-            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable*/
-            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
-            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
-            uint32_t reserved12                    :    1;  /*reserved*/
-            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
-            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
-            uint32_t reserved16                    :    2;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
-            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
-            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
-            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t reserved25                    :    5;  /*reserved*/
-            uint32_t dqs_ie_always_on              :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
-            uint32_t data_ie_always_on             :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
-            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
-            uint32_t reserved2                     :    9;  /*reserved*/
-            uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
-            uint32_t reg_aw_size0_1_support_en     :    1;  /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/
-            uint32_t reg_axi_rdata_back_fast       :    1;  /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/
-            uint32_t rresp_ecc_err_en              :    1;  /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/
-            uint32_t ar_splice_en                  :    1;  /*Set this bit to enable AXI Read Splice-transfer.*/
-            uint32_t aw_splice_en                  :    1;  /*Set this bit to enable AXI Write Splice-transfer.*/
-            uint32_t ram0_en                       :    1;  /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
-            uint32_t dual_ram_en                   :    1;  /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
-            uint32_t fast_write_en                 :    1;  /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.*/
-            uint32_t rxfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.*/
-            uint32_t txfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/
-        };
-        uint32_t val;
-    } ctrl1;
-    union {
-        struct {
-            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/
-            uint32_t cs_hold_time                  :    5;  /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/
-            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/
-            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
-            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
-            uint32_t reserved15                    :    9;  /*reserved*/
-            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
-            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t sync_reset                    :    1;  /*The spi0_mst_st and spi0_slv_st will be reset.*/
-        };
-        uint32_t val;
-    } ctrl2;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
-            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
-            uint32_t clk_equ_sysclk                :    1;  /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
-            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
-            uint32_t reserved8                     :    1;  /*reserved*/
-            uint32_t ck_out_edge                   :    1;  /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
-            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
-            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
-            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
-            uint32_t reserved16                    :    8;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
-            uint32_t usr_dbytelen                  :    3;  /*SPI0 USR_CMD read or write data byte length -1*/
-            uint32_t reserved9                     :    17;  /*reserved*/
-            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of  command.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } mosi_dlen;
-    union {
-        struct {
-            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } miso_dlen;
-    union {
-        struct {
-            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
-            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t reserved24                    :    8;  /*reserved*/
-        };
-        uint32_t val;
-    } rd_status;
-    uint32_t reserved_30;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t reserved0                     :    5;  /*reserved*/
-            uint32_t fsub_pin                      :    1;  /*For SPI0,  flash is connected to SUBPINs.*/
-            uint32_t ssub_pin                      :    1;  /*For SPI0,  sram is connected to SUBPINs.*/
-            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle     0: spi clk line is low when idle */
-            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } misc;
-    uint32_t tx_crc;
-    union {
-        struct {
-            uint32_t axi_req_en                    :    1;  /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/
-            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
-            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
-            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t reserved9                     :    21;  /*reserved*/
-            uint32_t reg_same_aw_ar_addr_chk_en    :    1;  /*Set this bit to check AXI read/write the same address region.*/
-            uint32_t reg_close_axi_inf_en          :    1;  /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/
-        };
-        uint32_t val;
-    } cache_fctrl;
-    union {
-        struct {
-            uint32_t usr_saddr_4byte               :    1;  /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/
-            uint32_t usr_sram_dio                  :    1;  /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
-            uint32_t usr_sram_qio                  :    1;  /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
-            uint32_t usr_wr_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/
-            uint32_t usr_rd_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/
-            uint32_t sram_usr_rcmd                 :    1;  /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/
-            uint32_t sram_rdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved12                    :    2;  /*reserved*/
-            uint32_t sram_addr_bitlen              :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/
-            uint32_t sram_usr_wcmd                 :    1;  /*For SPI0, In the external RAM mode cache write sram for user define command*/
-            uint32_t sram_oct                      :    1;  /*reserved*/
-            uint32_t sram_wdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } cache_sctrl;
-    union {
-        struct {
-            uint32_t sclk_mode                     :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
-            uint32_t swb_mode                      :    8;  /*Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t sdin_dual                     :    1;  /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t sdout_dual                    :    1;  /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t saddr_dual                    :    1;  /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t reserved13                    :    1;  /*reserved*/
-            uint32_t sdin_quad                     :    1;  /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t sdout_quad                    :    1;  /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t saddr_quad                    :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t scmd_quad                     :    1;  /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t sdin_oct                      :    1;  /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t sdout_oct                     :    1;  /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t saddr_oct                     :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t scmd_oct                      :    1;  /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t sdummy_rin                    :    1;  /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
-            uint32_t sdummy_wout                   :    1;  /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
-            uint32_t reg_smem_wdummy_dqs_always_out:    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/
-            uint32_t reg_smem_wdummy_always_out    :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/
-            uint32_t reserved26                    :    4;  /*reserved*/
-            uint32_t reg_smem_dqs_ie_always_on     :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
-            uint32_t reg_smem_data_ie_always_on    :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
-        };
-        uint32_t val;
-    } sram_cmd;
-    union {
-        struct {
-            uint32_t sram_usr_rd_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t sram_usr_rd_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_drd_cmd;
-    union {
-        struct {
-            uint32_t sram_usr_wr_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t sram_usr_wr_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_dwr_cmd;
-    union {
-        struct {
-            uint32_t sclkcnt_l                     :    8;  /*For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.*/
-            uint32_t sclkcnt_h                     :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t sclkcnt_n                     :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
-        };
-        uint32_t val;
-    } sram_clk;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;  /*reserved*/
-            uint32_t lock_delay_time               :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } fsm;
-    uint32_t data_buf[16];
-    union {
-        struct {
-            uint32_t waiti_en                      :    1;  /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/
-            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
-            uint32_t waiti_addr_en                 :    1;  /*1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/
-            uint32_t waiti_addr_cyclelen           :    2;  /*When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/
-            uint32_t reserved5                     :    4;  /*reserved*/
-            uint32_t waiti_cmd_2b                  :    1;  /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/
-            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
-            uint32_t waiti_cmd                     :    16;  /*The command value to wait flash idle(RDSR).*/
-        };
-        uint32_t val;
-    } flash_waiti_ctrl;
-    union {
-        struct {
-            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
-            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
-            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
-            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
-            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
-            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
-            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
-        };
-        uint32_t val;
-    } flash_sus_ctrl;
-    union {
-        struct {
-            uint32_t flash_pes_command             :    16;  /*Program/Erase suspend command.*/
-            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
-        };
-        uint32_t val;
-    } flash_sus_cmd;
-    union {
-        struct {
-            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
-            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
-            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
-            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
-            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
-            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
-            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
-            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
-            uint32_t reserved8                     :    7;  /*reserved*/
-            uint32_t flash_pesr_cmd_2b             :    1;  /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/
-            uint32_t flash_per_command             :    16;  /*Program/Erase resume command.*/
-        };
-        uint32_t val;
-    } sus_status;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    union {
-        struct {
-            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject_en                 :    1;  /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err_en           :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err                       :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject                    :    1;  /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
-            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
-            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
-            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
-            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/
-            uint32_t ecc_err                       :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
-            uint32_t pms_reject                    :    1;  /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/
-            uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
-            uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err                       :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject                    :    1;  /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    uint32_t reserved_d0;
-    union {
-        struct {
-            uint32_t reg_fmem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
-            uint32_t reg_fmem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
-            uint32_t reg_fmem_outminbytelen        :    7;  /*It is the minimum output data length in the panda device.*/
-            uint32_t reg_fmem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
-            uint32_t reg_fmem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/
-            uint32_t reg_fmem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
-            uint32_t reg_fmem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t reg_fmem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t reserved25                    :    1;  /*reserved*/
-            uint32_t reg_fmem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t reg_fmem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
-            uint32_t reg_fmem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
-            uint32_t reg_fmem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t reg_fmem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } ddr;
-    union {
-        struct {
-            uint32_t reg_smem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
-            uint32_t reg_smem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
-            uint32_t reg_smem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
-            uint32_t reg_smem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
-            uint32_t reg_smem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
-            uint32_t reg_smem_outminbytelen        :    7;  /*It is the minimum output data length in the DDR psram.*/
-            uint32_t reg_smem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/
-            uint32_t reg_smem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/
-            uint32_t reg_smem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
-            uint32_t reg_smem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t reg_smem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t reserved25                    :    1;  /*reserved*/
-            uint32_t reg_smem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t reg_smem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
-            uint32_t reg_smem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
-            uint32_t reg_smem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t reg_smem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ddr;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms0_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms0_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms1_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms1_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms2_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms2_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms3_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms3_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms0_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms0_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms1_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms1_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms2_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms2_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms3_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms3_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_size;
-    uint32_t reserved_160;
-    union {
-        struct {
-            uint32_t reject_addr                   :    26;  /*This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pm_en                         :    1;  /*Set this bit to enable SPI0/1 transfer permission control function.*/
-            uint32_t reserved27                    :    1;  /*reserved*/
-            uint32_t pms_ld                        :    1;  /*1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_st                        :    1;  /*1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_multi_hit                 :    1;  /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_ivd                       :    1;  /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-        };
-        uint32_t val;
-    } pms_reject;
-    union {
-        struct {
-            uint32_t reserved0                     :    11;  /*reserved*/
-            uint32_t ecc_err_int_num               :    6;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t reg_fmem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
-            uint32_t reg_fmem_page_size            :    2;  /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t reg_fmem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/
-            uint32_t usr_ecc_addr_en               :    1;  /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t ecc_continue_record_err_en    :    1;  /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/
-            uint32_t ecc_err_bits                  :    7;  /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/
-        };
-        uint32_t val;
-    } ecc_ctrl;
-    union {
-        struct {
-            uint32_t ecc_err_addr                  :    26;  /*This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-            uint32_t ecc_err_cnt                   :    6;  /*This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-        };
-        uint32_t val;
-    } ecc_err_addr;
-    union {
-        struct {
-            uint32_t axi_err_addr                  :    26;  /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
-            uint32_t all_fifo_empty                :    1;  /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
-            uint32_t reg_rdata_afifo_rempty        :    1;  /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
-            uint32_t reg_raddr_afifo_rempty        :    1;  /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
-            uint32_t reg_wdata_afifo_rempty        :    1;  /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
-            uint32_t reg_wblen_afifo_rempty        :    1;  /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
-            uint32_t reg_all_axi_trans_afifo_empty :    1;  /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/
-        };
-        uint32_t val;
-    } axi_err_addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    17;  /*reserved*/
-            uint32_t reg_smem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
-            uint32_t reg_smem_page_size            :    2;  /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t reg_smem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ecc_ctrl;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    union {
-        struct {
-            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/
-            uint32_t timing_cali_update            :    1;  /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/
-            uint32_t reserved7                     :    25;  /*reserved*/
-        };
-        uint32_t val;
-    } timing_cali;
-    union {
-        struct {
-            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    union {
-        struct {
-            uint32_t reg_smem_timing_clk_ena       :    1;  /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t reg_smem_timing_cali          :    1;  /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t reg_smem_extra_dummy_cyclelen :    3;  /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t reg_smem_dll_timing_cali      :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_timing_cali;
-    union {
-        struct {
-            uint32_t reg_smem_din0_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din1_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din2_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din3_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din4_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din5_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din6_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din7_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_dins_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_mode;
-    union {
-        struct {
-            uint32_t reg_smem_din0_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din1_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din2_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din3_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din4_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din5_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din6_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din7_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_dins_num             :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_num;
-    union {
-        struct {
-            uint32_t reg_smem_dout0_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout1_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout2_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout3_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout4_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout5_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout6_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout7_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_douts_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_dout_mode;
-    union {
-        struct {
-            uint32_t reg_smem_cs_setup             :    1;  /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */
-            uint32_t reg_smem_cs_hold              :    1;  /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
-            uint32_t reg_smem_cs_setup_time        :    5;  /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
-            uint32_t reg_smem_cs_hold_time         :    5;  /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
-            uint32_t reg_smem_ecc_cs_hold_time     :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/
-            uint32_t reg_smem_ecc_skip_page_corner :    1;  /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/
-            uint32_t reg_smem_ecc_16to18_byte_en   :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/
-            uint32_t reserved17                    :    8;  /*reserved*/
-            uint32_t reg_smem_cs_hold_delay        :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t reg_smem_split_trans_en       :    1;  /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
-        };
-        uint32_t val;
-    } spi_smem_ac;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    union {
-        struct {
-            uint32_t reg_clk_en                    :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t xts_plain_base;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    union {
-        struct {
-            uint32_t reg_xts_linesize              :    2;  /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_linesize;
-    union {
-        struct {
-            uint32_t reg_xts_destination           :    1;  /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_destination;
-    union {
-        struct {
-            uint32_t reg_xts_physical_address      :    26;  /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_physical_address;
-    union {
-        struct {
-            uint32_t reg_xts_trigger               :    1;  /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_trigger;
-    union {
-        struct {
-            uint32_t reg_xts_release               :    1;  /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_release;
-    union {
-        struct {
-            uint32_t reg_xts_destroy               :    1;  /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_destroy;
-    union {
-        struct {
-            uint32_t reg_xts_state                 :    2;  /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_state;
-    union {
-        struct {
-            uint32_t reg_xts_date                  :    30;  /*This bits stores the last modified-time of manual encryption feature.*/
-            uint32_t reserved30                    :    2;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_date;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t mmu_item_content;
-    uint32_t mmu_item_index;
-    union {
-        struct {
-            uint32_t reg_mmu_mem_force_on          :    1;  /*Set this bit to enable mmu-memory clock force on*/
-            uint32_t reg_mmu_mem_force_pd          :    1;  /*Set this bit to force mmu-memory powerdown*/
-            uint32_t reg_mmu_mem_force_pu          :    1;  /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/
-            uint32_t reg_mmu_page_size             :    2;  /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/
-            uint32_t reserved5                     :    11;  /*reserved*/
-            uint32_t aux_ctrl                      :    14;  /*MMU PSRAM aux control register*/
-            uint32_t rdn_ena                       :    1;  /*ECO register enable bit*/
-            uint32_t rdn_result                    :    1;  /*MSPI module clock domain and AXI clock domain ECO register result register*/
-        };
-        uint32_t val;
-    } mmu_power_ctrl;
-    union {
-        struct {
-            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
-            uint32_t reg_crypt_calc_d_dpa_en       :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
-            uint32_t reg_crypt_dpa_selectister     :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } dpa_ctrl;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t spi_memisterrnd_eco_high;
-    uint32_t spi_memisterrnd_eco_low;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*SPI0/1 register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_mem_dev_t;
-
-extern spi_mem_dev_t SPIMEM0;
-extern spi_mem_dev_t SPIMEM1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/spi_reg.h b/components/soc/esp32c6/include/soc/spi_reg.h
deleted file mode 100644
index 544b54abd1f..00000000000
--- a/components/soc/esp32c6/include/soc/spi_reg.h
+++ /dev/null
@@ -1,2108 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SPI_CMD_REG register
- *  Command control register
- */
-#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
-/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
- */
-#define SPI_CONF_BITLEN    0x0003FFFFU
-#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
-#define SPI_CONF_BITLEN_V  0x0003FFFFU
-#define SPI_CONF_BITLEN_S  0
-/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
- *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
- *  clock domain, which is only used in SPI master mode.
- */
-#define SPI_UPDATE    (BIT(23))
-#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
-#define SPI_UPDATE_V  0x00000001U
-#define SPI_UPDATE_S  23
-/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
- *  User define command enable.  An operation will be triggered when the bit is set.
- *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
- *  changed by CONF_buf.
- */
-#define SPI_USR    (BIT(24))
-#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
-#define SPI_USR_V  0x00000001U
-#define SPI_USR_S  24
-
-/** SPI_ADDR_REG register
- *  Address value register
- */
-#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
-/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  Address to slave. Can be configured in CONF state.
- */
-#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
-#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_S  0
-
-/** SPI_CTRL_REG register
- *  SPI control register
- */
-#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
-/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
- *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
- *  the FSPI bus signals are output. Can be configured in CONF state.
- */
-#define SPI_DUMMY_OUT    (BIT(3))
-#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
-#define SPI_DUMMY_OUT_V  0x00000001U
-#define SPI_DUMMY_OUT_S  3
-/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
- *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_DUAL    (BIT(5))
-#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
-#define SPI_FADDR_DUAL_V  0x00000001U
-#define SPI_FADDR_DUAL_S  5
-/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
- *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_QUAD    (BIT(6))
-#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
-#define SPI_FADDR_QUAD_V  0x00000001U
-#define SPI_FADDR_QUAD_S  6
-/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0;
- *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_OCT    (BIT(7))
-#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
-#define SPI_FADDR_OCT_V  0x00000001U
-#define SPI_FADDR_OCT_S  7
-/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
- *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_DUAL    (BIT(8))
-#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
-#define SPI_FCMD_DUAL_V  0x00000001U
-#define SPI_FCMD_DUAL_S  8
-/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
- *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_QUAD    (BIT(9))
-#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
-#define SPI_FCMD_QUAD_V  0x00000001U
-#define SPI_FCMD_QUAD_S  9
-/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0;
- *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_OCT    (BIT(10))
-#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
-#define SPI_FCMD_OCT_V  0x00000001U
-#define SPI_FCMD_OCT_S  10
-/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
- *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_DUAL    (BIT(14))
-#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
-#define SPI_FREAD_DUAL_V  0x00000001U
-#define SPI_FREAD_DUAL_S  14
-/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
- *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_QUAD    (BIT(15))
-#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
-#define SPI_FREAD_QUAD_V  0x00000001U
-#define SPI_FREAD_QUAD_S  15
-/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0;
- *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_OCT    (BIT(16))
-#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
-#define SPI_FREAD_OCT_V  0x00000001U
-#define SPI_FREAD_OCT_S  16
-/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
- *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
- *  CONF state.
- */
-#define SPI_Q_POL    (BIT(18))
-#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
-#define SPI_Q_POL_V  0x00000001U
-#define SPI_Q_POL_S  18
-/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
- *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
- *  CONF state.
- */
-#define SPI_D_POL    (BIT(19))
-#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
-#define SPI_D_POL_V  0x00000001U
-#define SPI_D_POL_S  19
-/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
- *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
- *  configured in CONF state.
- */
-#define SPI_HOLD_POL    (BIT(20))
-#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
-#define SPI_HOLD_POL_V  0x00000001U
-#define SPI_HOLD_POL_S  20
-/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
- *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
- *  be configured in CONF state.
- */
-#define SPI_WP_POL    (BIT(21))
-#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
-#define SPI_WP_POL_V  0x00000001U
-#define SPI_WP_POL_S  21
-/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
- *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
- *  state.
- */
-#define SPI_RD_BIT_ORDER    0x00000003U
-#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
-#define SPI_RD_BIT_ORDER_V  0x00000003U
-#define SPI_RD_BIT_ORDER_S  23
-/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
- *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
- *  configured in CONF state.
- */
-#define SPI_WR_BIT_ORDER    0x00000003U
-#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
-#define SPI_WR_BIT_ORDER_V  0x00000003U
-#define SPI_WR_BIT_ORDER_S  25
-
-/** SPI_CLOCK_REG register
- *  SPI clock control register
- */
-#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
-/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
- *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
- *  0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_L    0x0000003FU
-#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
-#define SPI_CLKCNT_L_V  0x0000003FU
-#define SPI_CLKCNT_L_S  0
-/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
- *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
- *  must be 0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_H    0x0000003FU
-#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
-#define SPI_CLKCNT_H_V  0x0000003FU
-#define SPI_CLKCNT_H_S  6
-/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
- *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
- *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
- */
-#define SPI_CLKCNT_N    0x0000003FU
-#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
-#define SPI_CLKCNT_N_V  0x0000003FU
-#define SPI_CLKCNT_N_S  12
-/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
- *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
- */
-#define SPI_CLKDIV_PRE    0x0000000FU
-#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
-#define SPI_CLKDIV_PRE_V  0x0000000FU
-#define SPI_CLKDIV_PRE_S  18
-/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
- *  clock. Can be configured in CONF state.
- */
-#define SPI_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
-#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_CLK_EQU_SYSCLK_S  31
-
-/** SPI_USER_REG register
- *  SPI USER control register
- */
-#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
-/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
- *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUTDIN    (BIT(0))
-#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
-#define SPI_DOUTDIN_V  0x00000001U
-#define SPI_DOUTDIN_S  0
-/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
- *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
- *  Can be configured in CONF state.
- */
-#define SPI_QPI_MODE    (BIT(3))
-#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
-#define SPI_QPI_MODE_V  0x00000001U
-#define SPI_QPI_MODE_S  3
-/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0;
- *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
- *  Can be configured in CONF state.
- */
-#define SPI_OPI_MODE    (BIT(4))
-#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
-#define SPI_OPI_MODE_V  0x00000001U
-#define SPI_OPI_MODE_S  4
-/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
- *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
- *  spi_ck_i. 1:tsck = !spi_ck_i.
- */
-#define SPI_TSCK_I_EDGE    (BIT(5))
-#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
-#define SPI_TSCK_I_EDGE_V  0x00000001U
-#define SPI_TSCK_I_EDGE_S  5
-/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
- *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_CS_HOLD    (BIT(6))
-#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
-#define SPI_CS_HOLD_V  0x00000001U
-#define SPI_CS_HOLD_S  6
-/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
- *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_CS_SETUP    (BIT(7))
-#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
-#define SPI_CS_SETUP_V  0x00000001U
-#define SPI_CS_SETUP_S  7
-/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
- *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
- *  !spi_ck_i. 1:rsck = spi_ck_i.
- */
-#define SPI_RSCK_I_EDGE    (BIT(8))
-#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
-#define SPI_RSCK_I_EDGE_V  0x00000001U
-#define SPI_RSCK_I_EDGE_S  8
-/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
- *  be configured in CONF state.
- */
-#define SPI_CK_OUT_EDGE    (BIT(9))
-#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
-#define SPI_CK_OUT_EDGE_V  0x00000001U
-#define SPI_CK_OUT_EDGE_S  9
-/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
- *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_DUAL    (BIT(12))
-#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
-#define SPI_FWRITE_DUAL_V  0x00000001U
-#define SPI_FWRITE_DUAL_S  12
-/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
- *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_QUAD    (BIT(13))
-#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
-#define SPI_FWRITE_QUAD_V  0x00000001U
-#define SPI_FWRITE_QUAD_S  13
-/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0;
- *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_OCT    (BIT(14))
-#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
-#define SPI_FWRITE_OCT_V  0x00000001U
-#define SPI_FWRITE_OCT_S  14
-/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
- *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
- *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
- *  not seg-trans mode. Can be configured in CONF state.
- */
-#define SPI_USR_CONF_NXT    (BIT(15))
-#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
-#define SPI_USR_CONF_NXT_V  0x00000001U
-#define SPI_USR_CONF_NXT_S  15
-/** SPI_SIO : R/W; bitpos: [17]; default: 0;
- *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
- *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
- */
-#define SPI_SIO    (BIT(17))
-#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
-#define SPI_SIO_V  0x00000001U
-#define SPI_SIO_S  17
-/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
- *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
- *  disable. Can be configured in CONF state.
- */
-#define SPI_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
-#define SPI_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_USR_MISO_HIGHPART_S  24
-/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
- *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
- *  0: disable.  Can be configured in CONF state.
- */
-#define SPI_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
-#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_USR_MOSI_HIGHPART_S  25
-/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
- *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
- *  CONF state.
- */
-#define SPI_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
-#define SPI_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_USR_DUMMY_IDLE_S  26
-/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
- *  This bit enable the write-data phase of an operation. Can be configured in CONF
- *  state.
- */
-#define SPI_USR_MOSI    (BIT(27))
-#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
-#define SPI_USR_MOSI_V  0x00000001U
-#define SPI_USR_MOSI_S  27
-/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
- *  This bit enable the read-data phase of an operation. Can be configured in CONF
- *  state.
- */
-#define SPI_USR_MISO    (BIT(28))
-#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
-#define SPI_USR_MISO_V  0x00000001U
-#define SPI_USR_MISO_S  28
-/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
- *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY    (BIT(29))
-#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
-#define SPI_USR_DUMMY_V  0x00000001U
-#define SPI_USR_DUMMY_S  29
-/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
- *  This bit enable the address phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_ADDR    (BIT(30))
-#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
-#define SPI_USR_ADDR_V  0x00000001U
-#define SPI_USR_ADDR_S  30
-/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
- *  This bit enable the command phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND    (BIT(31))
-#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
-#define SPI_USR_COMMAND_V  0x00000001U
-#define SPI_USR_COMMAND_S  31
-
-/** SPI_USER1_REG register
- *  SPI USER control register 1
- */
-#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
-/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
- *  The length in spi_clk cycles of dummy phase. The register value shall be
- *  (cycle_num-1). Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
-#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
- *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
- *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
- *  GP-SPI master FD/HD-mode.
- */
-#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
-#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
-#define SPI_MST_WFULL_ERR_END_EN_S  16
-/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
- *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
- *  bit. Can be configured in CONF state.
- */
-#define SPI_CS_SETUP_TIME    0x0000001FU
-#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
-#define SPI_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_CS_SETUP_TIME_S  17
-/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
- *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
- *  Can be configured in CONF state.
- */
-#define SPI_CS_HOLD_TIME    0x0000001FU
-#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
-#define SPI_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_CS_HOLD_TIME_S  22
-/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
- *  The length in bits of address phase. The register value shall be (bit_num-1). Can
- *  be configured in CONF state.
- */
-#define SPI_USR_ADDR_BITLEN    0x0000001FU
-#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
-#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
-#define SPI_USR_ADDR_BITLEN_S  27
-
-/** SPI_USER2_REG register
- *  SPI USER control register 2
- */
-#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
-/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
- *  The value of  command. Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
-#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_S  0
-/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
- *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
- *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
- *  is valid in GP-SPI master FD/HD-mode.
- */
-#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
-#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
-#define SPI_MST_REMPTY_ERR_END_EN_S  27
-/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
- *  The length in bits of command phase. The register value shall be (bit_num-1). Can
- *  be configured in CONF state.
- */
-#define SPI_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
-#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_S  28
-
-/** SPI_MS_DLEN_REG register
- *  SPI data bit length control register
- */
-#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
-/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  The value of these bits is the configured SPI transmission data bit length in
- *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
- *  the configured bit length in slave mode DMA RX controlled transfer. The register
- *  value shall be (bit_num-1). Can be configured in CONF state.
- */
-#define SPI_MS_DATA_BITLEN    0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
-#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_S  0
-
-/** SPI_MISC_REG register
- *  SPI misc register
- */
-#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
-/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS0_DIS    (BIT(0))
-#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
-#define SPI_CS0_DIS_V  0x00000001U
-#define SPI_CS0_DIS_S  0
-/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS1_DIS    (BIT(1))
-#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
-#define SPI_CS1_DIS_V  0x00000001U
-#define SPI_CS1_DIS_S  1
-/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS2_DIS    (BIT(2))
-#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
-#define SPI_CS2_DIS_V  0x00000001U
-#define SPI_CS2_DIS_S  2
-/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS3_DIS    (BIT(3))
-#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
-#define SPI_CS3_DIS_V  0x00000001U
-#define SPI_CS3_DIS_S  3
-/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS4_DIS    (BIT(4))
-#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
-#define SPI_CS4_DIS_V  0x00000001U
-#define SPI_CS4_DIS_S  4
-/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS5_DIS    (BIT(5))
-#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
-#define SPI_CS5_DIS_V  0x00000001U
-#define SPI_CS5_DIS_S  5
-/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
- *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
- */
-#define SPI_CK_DIS    (BIT(6))
-#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
-#define SPI_CK_DIS_V  0x00000001U
-#define SPI_CK_DIS_S  6
-/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
- *  In the master mode the bits are the polarity of spi cs line, the value is
- *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
- */
-#define SPI_MASTER_CS_POL    0x0000003FU
-#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
-#define SPI_MASTER_CS_POL_V  0x0000003FU
-#define SPI_MASTER_CS_POL_S  7
-/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0;
- *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
- *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
- */
-#define SPI_CLK_DATA_DTR_EN    (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
-#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
-#define SPI_CLK_DATA_DTR_EN_S  16
-/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0;
- *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
- *  Can be configured in CONF state.
- */
-#define SPI_DATA_DTR_EN    (BIT(17))
-#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
-#define SPI_DATA_DTR_EN_V  0x00000001U
-#define SPI_DATA_DTR_EN_S  17
-/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0;
- *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
- *  configured in CONF state.
- */
-#define SPI_ADDR_DTR_EN    (BIT(18))
-#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
-#define SPI_ADDR_DTR_EN_V  0x00000001U
-#define SPI_ADDR_DTR_EN_S  18
-/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0;
- *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
- *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
- *  configured in CONF state.
- */
-#define SPI_CMD_DTR_EN    (BIT(19))
-#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
-#define SPI_CMD_DTR_EN_V  0x00000001U
-#define SPI_CMD_DTR_EN_S  19
-/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
- *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
- *  CONF state.
- */
-#define SPI_SLAVE_CS_POL    (BIT(23))
-#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
-#define SPI_SLAVE_CS_POL_V  0x00000001U
-#define SPI_SLAVE_CS_POL_S  23
-/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0;
- *  The default value of spi_dqs. Can be configured in CONF state.
- */
-#define SPI_DQS_IDLE_EDGE    (BIT(24))
-#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
-#define SPI_DQS_IDLE_EDGE_V  0x00000001U
-#define SPI_DQS_IDLE_EDGE_S  24
-/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
- *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
- *  configured in CONF state.
- */
-#define SPI_CK_IDLE_EDGE    (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
-#define SPI_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_CK_IDLE_EDGE_S  29
-/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
- *  spi cs line keep low when the bit is set. Can be configured in CONF state.
- */
-#define SPI_CS_KEEP_ACTIVE    (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
-#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_CS_KEEP_ACTIVE_S  30
-/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
- *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
- *  spi quad input swap disable. Can be configured in CONF state.
- */
-#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
-#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
-#define SPI_QUAD_DIN_PIN_SWAP_S  31
-
-/** SPI_DIN_MODE_REG register
- *  SPI input delay mode configuration
- */
-#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
-/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN0_MODE    0x00000003U
-#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
-#define SPI_DIN0_MODE_V  0x00000003U
-#define SPI_DIN0_MODE_S  0
-/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN1_MODE    0x00000003U
-#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
-#define SPI_DIN1_MODE_V  0x00000003U
-#define SPI_DIN1_MODE_S  2
-/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN2_MODE    0x00000003U
-#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
-#define SPI_DIN2_MODE_V  0x00000003U
-#define SPI_DIN2_MODE_S  4
-/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN3_MODE    0x00000003U
-#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
-#define SPI_DIN3_MODE_V  0x00000003U
-#define SPI_DIN3_MODE_S  6
-/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN4_MODE    0x00000003U
-#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
-#define SPI_DIN4_MODE_V  0x00000003U
-#define SPI_DIN4_MODE_S  8
-/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN5_MODE    0x00000003U
-#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
-#define SPI_DIN5_MODE_V  0x00000003U
-#define SPI_DIN5_MODE_S  10
-/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN6_MODE    0x00000003U
-#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
-#define SPI_DIN6_MODE_V  0x00000003U
-#define SPI_DIN6_MODE_S  12
-/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN7_MODE    0x00000003U
-#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
-#define SPI_DIN7_MODE_V  0x00000003U
-#define SPI_DIN7_MODE_S  14
-/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
- *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
- *  state.
- */
-#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
-#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
-#define SPI_TIMING_HCLK_ACTIVE_S  16
-
-/** SPI_DIN_NUM_REG register
- *  SPI input delay number configuration
- */
-#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
-/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN0_NUM    0x00000003U
-#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
-#define SPI_DIN0_NUM_V  0x00000003U
-#define SPI_DIN0_NUM_S  0
-/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN1_NUM    0x00000003U
-#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
-#define SPI_DIN1_NUM_V  0x00000003U
-#define SPI_DIN1_NUM_S  2
-/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN2_NUM    0x00000003U
-#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
-#define SPI_DIN2_NUM_V  0x00000003U
-#define SPI_DIN2_NUM_S  4
-/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN3_NUM    0x00000003U
-#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
-#define SPI_DIN3_NUM_V  0x00000003U
-#define SPI_DIN3_NUM_S  6
-/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN4_NUM    0x00000003U
-#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
-#define SPI_DIN4_NUM_V  0x00000003U
-#define SPI_DIN4_NUM_S  8
-/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN5_NUM    0x00000003U
-#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
-#define SPI_DIN5_NUM_V  0x00000003U
-#define SPI_DIN5_NUM_S  10
-/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN6_NUM    0x00000003U
-#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
-#define SPI_DIN6_NUM_V  0x00000003U
-#define SPI_DIN6_NUM_S  12
-/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN7_NUM    0x00000003U
-#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
-#define SPI_DIN7_NUM_V  0x00000003U
-#define SPI_DIN7_NUM_S  14
-
-/** SPI_DOUT_MODE_REG register
- *  SPI output delay mode configuration
- */
-#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
-/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT0_MODE    (BIT(0))
-#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
-#define SPI_DOUT0_MODE_V  0x00000001U
-#define SPI_DOUT0_MODE_S  0
-/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT1_MODE    (BIT(1))
-#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
-#define SPI_DOUT1_MODE_V  0x00000001U
-#define SPI_DOUT1_MODE_S  1
-/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT2_MODE    (BIT(2))
-#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
-#define SPI_DOUT2_MODE_V  0x00000001U
-#define SPI_DOUT2_MODE_S  2
-/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT3_MODE    (BIT(3))
-#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
-#define SPI_DOUT3_MODE_V  0x00000001U
-#define SPI_DOUT3_MODE_S  3
-/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT4_MODE    (BIT(4))
-#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
-#define SPI_DOUT4_MODE_V  0x00000001U
-#define SPI_DOUT4_MODE_S  4
-/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT5_MODE    (BIT(5))
-#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
-#define SPI_DOUT5_MODE_V  0x00000001U
-#define SPI_DOUT5_MODE_S  5
-/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT6_MODE    (BIT(6))
-#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
-#define SPI_DOUT6_MODE_V  0x00000001U
-#define SPI_DOUT6_MODE_S  6
-/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT7_MODE    (BIT(7))
-#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
-#define SPI_DOUT7_MODE_V  0x00000001U
-#define SPI_DOUT7_MODE_S  7
-/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0;
- *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
- *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_D_DQS_MODE    (BIT(8))
-#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
-#define SPI_D_DQS_MODE_V  0x00000001U
-#define SPI_D_DQS_MODE_S  8
-
-/** SPI_DMA_CONF_REG register
- *  SPI DMA control register
- */
-#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
-/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
- *  DMA TX FIFO is ready for sending data.
- */
-#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
-#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_S  0
-/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
- *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
- *  0: DMA RX FIFO is ready for receiving data.
- */
-#define SPI_DMA_INFIFO_FULL    (BIT(1))
-#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
-#define SPI_DMA_INFIFO_FULL_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_S  1
-/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
- *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
- */
-#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
-#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
-#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
-/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
- *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
- */
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
-/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
- *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
- */
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
-/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
- *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
- *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
- *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
- *  spi_dma_seg_trans_done in seg-trans.
- */
-#define SPI_RX_EOF_EN    (BIT(21))
-#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
-#define SPI_RX_EOF_EN_V  0x00000001U
-#define SPI_RX_EOF_EN_S  21
-/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
- *  Set this bit to enable SPI DMA controlled receive data mode.
- */
-#define SPI_DMA_RX_ENA    (BIT(27))
-#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
-#define SPI_DMA_RX_ENA_V  0x00000001U
-#define SPI_DMA_RX_ENA_S  27
-/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
- *  Set this bit to enable SPI DMA controlled send data mode.
- */
-#define SPI_DMA_TX_ENA    (BIT(28))
-#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
-#define SPI_DMA_TX_ENA_V  0x00000001U
-#define SPI_DMA_TX_ENA_S  28
-/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
- *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
- *  slave mode transfer.
- */
-#define SPI_RX_AFIFO_RST    (BIT(29))
-#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
-#define SPI_RX_AFIFO_RST_V  0x00000001U
-#define SPI_RX_AFIFO_RST_S  29
-/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
- *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
- *  controlled mode transfer and master mode transfer.
- */
-#define SPI_BUF_AFIFO_RST    (BIT(30))
-#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
-#define SPI_BUF_AFIFO_RST_V  0x00000001U
-#define SPI_BUF_AFIFO_RST_S  30
-/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
- *  controlled mode transfer.
- */
-#define SPI_DMA_AFIFO_RST    (BIT(31))
-#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
-#define SPI_DMA_AFIFO_RST_V  0x00000001U
-#define SPI_DMA_AFIFO_RST_S  31
-
-/** SPI_DMA_INT_ENA_REG register
- *  SPI interrupt enable register
- */
-#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
-/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
-#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ENA_S  2
-/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
-#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ENA_S  3
-/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
-#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ENA_S  4
-/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The enable bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
-#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ENA_S  5
-/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
-#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ENA_S  6
-/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
-#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ENA_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
-/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The enable bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
-#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ENA_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
-#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
-/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
-#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ENA_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
-/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  The enable bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ENA    (BIT(19))
-#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
-#define SPI_APP2_INT_ENA_V  0x00000001U
-#define SPI_APP2_INT_ENA_S  19
-/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  The enable bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ENA    (BIT(20))
-#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
-#define SPI_APP1_INT_ENA_V  0x00000001U
-#define SPI_APP1_INT_ENA_S  20
-
-/** SPI_DMA_INT_CLR_REG register
- *  SPI interrupt clear register
- */
-#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
-/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
-#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_CLR_S  2
-/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
-#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_CLR_S  3
-/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
-#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD7_INT_CLR_S  4
-/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The clear bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
-#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD8_INT_CLR_S  5
-/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The clear bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
-#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD9_INT_CLR_S  6
-/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
- *  The clear bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
-#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMDA_INT_CLR_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
- *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
- *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
- *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
-/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  The clear bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
-#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_TRANS_DONE_INT_CLR_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
-/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
-#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
-/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
-#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_CLR_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
- *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
- *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
-/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
- *  The clear bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_CLR    (BIT(19))
-#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
-#define SPI_APP2_INT_CLR_V  0x00000001U
-#define SPI_APP2_INT_CLR_S  19
-/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  The clear bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_CLR    (BIT(20))
-#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
-#define SPI_APP1_INT_CLR_V  0x00000001U
-#define SPI_APP1_INT_CLR_S  20
-
-/** SPI_DMA_INT_RAW_REG register
- *  SPI interrupt raw register
- */
-#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
- *  receive data.  0: Others.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
- *  master mode and send out all 0 in slave mode.  0: Others.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
-/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
- *  is ended. 0: Others.
- */
-#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
-#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_RAW_S  2
-/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
- *  is ended. 0: Others.
- */
-#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
-#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_RAW_S  3
-/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
-#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD7_INT_RAW_S  4
-/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
-#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD8_INT_RAW_S  5
-/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
-#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD9_INT_RAW_S  6
-/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
-#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMDA_INT_RAW_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
-/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
- *  ended. 0: others.
- */
-#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
-#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_TRANS_DONE_INT_RAW_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
- *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
- *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
- *  is not ended or not occurred.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
-/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
- *  is error in the DMA seg-conf-trans. 0: others.
- */
-#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
-#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
- *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
- *  bigger than 63. 0: Others.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
-/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
- *  current SPI slave HD mode transmission is not supported. 0: Others.
- */
-#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
-#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_RAW_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
- *  write-full error when SPI inputs data in master mode. 0: Others.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
- *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
-/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
- */
-#define SPI_APP2_INT_RAW    (BIT(19))
-#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
-#define SPI_APP2_INT_RAW_V  0x00000001U
-#define SPI_APP2_INT_RAW_S  19
-/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
- */
-#define SPI_APP1_INT_RAW    (BIT(20))
-#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
-#define SPI_APP1_INT_RAW_V  0x00000001U
-#define SPI_APP1_INT_RAW_S  20
-
-/** SPI_DMA_INT_ST_REG register
- *  SPI interrupt status register
- */
-#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
-/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
-#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ST_S  2
-/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
-#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ST_S  3
-/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_ST    (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
-#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ST_S  4
-/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
- *  The status bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_ST    (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
-#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ST_S  5
-/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
- *  The status bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_ST    (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
-#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ST_S  6
-/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
- *  The status bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_ST    (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
-#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ST_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
- *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
- *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
- *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
-/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  The status bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ST    (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
-#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ST_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
- *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
-#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
-/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
-#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ST_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
- *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
- *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
-/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
- *  The status bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ST    (BIT(19))
-#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
-#define SPI_APP2_INT_ST_V  0x00000001U
-#define SPI_APP2_INT_ST_S  19
-/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
- *  The status bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ST    (BIT(20))
-#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
-#define SPI_APP1_INT_ST_V  0x00000001U
-#define SPI_APP1_INT_ST_S  20
-
-/** SPI_DMA_INT_SET_REG register
- *  SPI interrupt software set register
- */
-#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
- *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
- *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
-/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
- *  The software set bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
-#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_SET_S  2
-/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
- *  The software set bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
-#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_SET_S  3
-/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
- *  The software set bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_SET    (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
-#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD7_INT_SET_S  4
-/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
- *  The software set bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_SET    (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
-#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD8_INT_SET_S  5
-/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
- *  The software set bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_SET    (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
-#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD9_INT_SET_S  6
-/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
- *  The software set bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_SET    (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
-#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
-#define SPI_SLV_CMDA_INT_SET_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
- *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
-#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
- *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
-#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
- *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
-#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
- *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
-#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
-/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
- *  The software set bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_SET    (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
-#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_TRANS_DONE_INT_SET_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
- *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
-/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
- *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
-#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
- *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
-/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
- *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
-#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_SET_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
- *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
- *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
-/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
- *  The software set bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_SET    (BIT(19))
-#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
-#define SPI_APP2_INT_SET_V  0x00000001U
-#define SPI_APP2_INT_SET_S  19
-/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
- *  The software set bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_SET    (BIT(20))
-#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
-#define SPI_APP1_INT_SET_V  0x00000001U
-#define SPI_APP1_INT_SET_S  20
-
-/** SPI_W0_REG register
- *  SPI CPU-controlled buffer0
- */
-#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
-/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF0    0xFFFFFFFFU
-#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
-#define SPI_BUF0_V  0xFFFFFFFFU
-#define SPI_BUF0_S  0
-
-/** SPI_W1_REG register
- *  SPI CPU-controlled buffer1
- */
-#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
-/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF1    0xFFFFFFFFU
-#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
-#define SPI_BUF1_V  0xFFFFFFFFU
-#define SPI_BUF1_S  0
-
-/** SPI_W2_REG register
- *  SPI CPU-controlled buffer2
- */
-#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
-/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF2    0xFFFFFFFFU
-#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
-#define SPI_BUF2_V  0xFFFFFFFFU
-#define SPI_BUF2_S  0
-
-/** SPI_W3_REG register
- *  SPI CPU-controlled buffer3
- */
-#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
-/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF3    0xFFFFFFFFU
-#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
-#define SPI_BUF3_V  0xFFFFFFFFU
-#define SPI_BUF3_S  0
-
-/** SPI_W4_REG register
- *  SPI CPU-controlled buffer4
- */
-#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
-/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF4    0xFFFFFFFFU
-#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
-#define SPI_BUF4_V  0xFFFFFFFFU
-#define SPI_BUF4_S  0
-
-/** SPI_W5_REG register
- *  SPI CPU-controlled buffer5
- */
-#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
-/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF5    0xFFFFFFFFU
-#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
-#define SPI_BUF5_V  0xFFFFFFFFU
-#define SPI_BUF5_S  0
-
-/** SPI_W6_REG register
- *  SPI CPU-controlled buffer6
- */
-#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
-/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF6    0xFFFFFFFFU
-#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
-#define SPI_BUF6_V  0xFFFFFFFFU
-#define SPI_BUF6_S  0
-
-/** SPI_W7_REG register
- *  SPI CPU-controlled buffer7
- */
-#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
-/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF7    0xFFFFFFFFU
-#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
-#define SPI_BUF7_V  0xFFFFFFFFU
-#define SPI_BUF7_S  0
-
-/** SPI_W8_REG register
- *  SPI CPU-controlled buffer8
- */
-#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
-/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF8    0xFFFFFFFFU
-#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
-#define SPI_BUF8_V  0xFFFFFFFFU
-#define SPI_BUF8_S  0
-
-/** SPI_W9_REG register
- *  SPI CPU-controlled buffer9
- */
-#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
-/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF9    0xFFFFFFFFU
-#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
-#define SPI_BUF9_V  0xFFFFFFFFU
-#define SPI_BUF9_S  0
-
-/** SPI_W10_REG register
- *  SPI CPU-controlled buffer10
- */
-#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
-/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF10    0xFFFFFFFFU
-#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
-#define SPI_BUF10_V  0xFFFFFFFFU
-#define SPI_BUF10_S  0
-
-/** SPI_W11_REG register
- *  SPI CPU-controlled buffer11
- */
-#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
-/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF11    0xFFFFFFFFU
-#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
-#define SPI_BUF11_V  0xFFFFFFFFU
-#define SPI_BUF11_S  0
-
-/** SPI_W12_REG register
- *  SPI CPU-controlled buffer12
- */
-#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
-/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF12    0xFFFFFFFFU
-#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
-#define SPI_BUF12_V  0xFFFFFFFFU
-#define SPI_BUF12_S  0
-
-/** SPI_W13_REG register
- *  SPI CPU-controlled buffer13
- */
-#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
-/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF13    0xFFFFFFFFU
-#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
-#define SPI_BUF13_V  0xFFFFFFFFU
-#define SPI_BUF13_S  0
-
-/** SPI_W14_REG register
- *  SPI CPU-controlled buffer14
- */
-#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
-/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF14    0xFFFFFFFFU
-#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
-#define SPI_BUF14_V  0xFFFFFFFFU
-#define SPI_BUF14_S  0
-
-/** SPI_W15_REG register
- *  SPI CPU-controlled buffer15
- */
-#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
-/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF15    0xFFFFFFFFU
-#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
-#define SPI_BUF15_V  0xFFFFFFFFU
-#define SPI_BUF15_S  0
-
-/** SPI_SLAVE_REG register
- *  SPI slave control register
- */
-#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
-/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
- *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on. Can be configured in CONF state.
- */
-#define SPI_CLK_MODE    0x00000003U
-#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
-#define SPI_CLK_MODE_V  0x00000003U
-#define SPI_CLK_MODE_S  0
-/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
- *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
- *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
- */
-#define SPI_CLK_MODE_13    (BIT(2))
-#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
-#define SPI_CLK_MODE_13_V  0x00000001U
-#define SPI_CLK_MODE_13_S  2
-/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
- *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
- *  0: output data at tsck posedge
- */
-#define SPI_RSCK_DATA_OUT    (BIT(3))
-#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
-#define SPI_RSCK_DATA_OUT_V  0x00000001U
-#define SPI_RSCK_DATA_OUT_S  3
-/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
- *  DMA controlled mode(Rd_DMA). 0: others
- */
-#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
-#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDDMA_BITLEN_EN_S  8
-/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
- *  in DMA controlled mode(Wr_DMA). 0: others
- */
-#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
-#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRDMA_BITLEN_EN_S  9
-/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
- *  CPU controlled mode(Rd_BUF). 0: others
- */
-#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
-#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDBUF_BITLEN_EN_S  10
-/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
- *  in CPU controlled mode(Wr_BUF). 0: others
- */
-#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
-#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRBUF_BITLEN_EN_S  11
-/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
- *  The magic value of BM table in master DMA seg-trans.
- */
-#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
-#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_S  22
-/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
- *  Set SPI work mode. 1: slave mode 0: master mode.
- */
-#define SPI_SLAVE_MODE    (BIT(26))
-#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
-#define SPI_SLAVE_MODE_V  0x00000001U
-#define SPI_SLAVE_MODE_S  26
-/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
- *  Software reset enable, reset the spi clock line cs line and data lines. Can be
- *  configured in CONF state.
- */
-#define SPI_SOFT_RESET    (BIT(27))
-#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
-#define SPI_SOFT_RESET_V  0x00000001U
-#define SPI_SOFT_RESET_S  27
-/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
- *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
- *  will start. 0: This is not seg-trans mode.
- */
-#define SPI_USR_CONF    (BIT(28))
-#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
-#define SPI_USR_CONF_V  0x00000001U
-#define SPI_USR_CONF_S  28
-/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
- *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
- *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
- *  transfer.
- */
-#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
-
-/** SPI_SLAVE1_REG register
- *  SPI slave control register 1
- */
-#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
-/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
- *  The transferred data bit length in SPI slave FD and HD mode.
- */
-#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
-#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_S  0
-/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
- *  In the slave mode it is the value of command.
- */
-#define SPI_SLV_LAST_COMMAND    0x000000FFU
-#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
-#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
-#define SPI_SLV_LAST_COMMAND_S  18
-/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
- *  In the slave mode it is the value of address.
- */
-#define SPI_SLV_LAST_ADDR    0x0000003FU
-#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
-#define SPI_SLV_LAST_ADDR_V  0x0000003FU
-#define SPI_SLV_LAST_ADDR_S  26
-
-/** SPI_CLK_GATE_REG register
- *  SPI module clock and register clock control
- */
-#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
-/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable clk gate
- */
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
-#define SPI_CLK_EN_V  0x00000001U
-#define SPI_CLK_EN_S  0
-/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
- *  Set this bit to power on the SPI module clock.
- */
-#define SPI_MST_CLK_ACTIVE    (BIT(1))
-#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
-#define SPI_MST_CLK_ACTIVE_V  0x00000001U
-#define SPI_MST_CLK_ACTIVE_S  1
-/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
- *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
- *  0: XTAL CLK.
- */
-#define SPI_MST_CLK_SEL    (BIT(2))
-#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
-#define SPI_MST_CLK_SEL_V  0x00000001U
-#define SPI_MST_CLK_SEL_S  2
-
-/** SPI_DATE_REG register
- *  Version control
- */
-#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
-/** SPI_DATE : R/W; bitpos: [27:0]; default: 35656448;
- *  SPI register version.
- */
-#define SPI_DATE    0x0FFFFFFFU
-#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
-#define SPI_DATE_V  0x0FFFFFFFU
-#define SPI_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/spi_struct.h b/components/soc/esp32c6/include/soc/spi_struct.h
deleted file mode 100644
index 14b6be86c14..00000000000
--- a/components/soc/esp32c6/include/soc/spi_struct.h
+++ /dev/null
@@ -1,1400 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: User-defined control registers */
-/** Type of cmd register
- *  Command control register
- */
-typedef union {
-    struct {
-        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
-         */
-        uint32_t conf_bitlen:18;
-        uint32_t reserved_18:5;
-        /** update : WT; bitpos: [23]; default: 0;
-         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
-         *  clock domain, which is only used in SPI master mode.
-         */
-        uint32_t update:1;
-        /** usr : R/W/SC; bitpos: [24]; default: 0;
-         *  User define command enable.  An operation will be triggered when the bit is set.
-         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
-         *  changed by CONF_buf.
-         */
-        uint32_t usr:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} spi_cmd_reg_t;
-
-/** Type of addr register
- *  Address value register
- */
-typedef union {
-    struct {
-        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
-         *  Address to slave. Can be configured in CONF state.
-         */
-        uint32_t usr_addr_value:32;
-    };
-    uint32_t val;
-} spi_addr_reg_t;
-
-/** Type of user register
- *  SPI USER control register
- */
-typedef union {
-    struct {
-        /** doutdin : R/W; bitpos: [0]; default: 0;
-         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t doutdin:1;
-        uint32_t reserved_1:2;
-        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
-         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t qpi_mode:1;
-        /** opi_mode : HRO; bitpos: [4]; default: 0;
-         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t opi_mode:1;
-        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
-         *  spi_ck_i. 1:tsck = !spi_ck_i.
-         */
-        uint32_t tsck_i_edge:1;
-        /** cs_hold : R/W; bitpos: [6]; default: 1;
-         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_hold:1;
-        /** cs_setup : R/W; bitpos: [7]; default: 1;
-         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_setup:1;
-        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
-         *  !spi_ck_i. 1:rsck = spi_ck_i.
-         */
-        uint32_t rsck_i_edge:1;
-        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
-         *  be configured in CONF state.
-         */
-        uint32_t ck_out_edge:1;
-        uint32_t reserved_10:2;
-        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
-         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_dual:1;
-        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
-         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_quad:1;
-        /** fwrite_oct : HRO; bitpos: [14]; default: 0;
-         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_oct:1;
-        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
-         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
-         *  not seg-trans mode. Can be configured in CONF state.
-         */
-        uint32_t usr_conf_nxt:1;
-        uint32_t reserved_16:1;
-        /** sio : R/W; bitpos: [17]; default: 0;
-         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
-         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
-         */
-        uint32_t sio:1;
-        uint32_t reserved_18:6;
-        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
-         *  disable. Can be configured in CONF state.
-         */
-        uint32_t usr_miso_highpart:1;
-        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
-         *  0: disable.  Can be configured in CONF state.
-         */
-        uint32_t usr_mosi_highpart:1;
-        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
-         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
-         *  CONF state.
-         */
-        uint32_t usr_dummy_idle:1;
-        /** usr_mosi : R/W; bitpos: [27]; default: 0;
-         *  This bit enable the write-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_mosi:1;
-        /** usr_miso : R/W; bitpos: [28]; default: 0;
-         *  This bit enable the read-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_miso:1;
-        /** usr_dummy : R/W; bitpos: [29]; default: 0;
-         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_dummy:1;
-        /** usr_addr : R/W; bitpos: [30]; default: 0;
-         *  This bit enable the address phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_addr:1;
-        /** usr_command : R/W; bitpos: [31]; default: 1;
-         *  This bit enable the command phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_command:1;
-    };
-    uint32_t val;
-} spi_user_reg_t;
-
-/** Type of user1 register
- *  SPI USER control register 1
- */
-typedef union {
-    struct {
-        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
-         *  The length in spi_clk cycles of dummy phase. The register value shall be
-         *  (cycle_num-1). Can be configured in CONF state.
-         */
-        uint32_t usr_dummy_cyclelen:8;
-        uint32_t reserved_8:8;
-        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
-         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
-         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
-         *  GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_wfull_err_end_en:1;
-        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
-         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
-         *  bit. Can be configured in CONF state.
-         */
-        uint32_t cs_setup_time:5;
-        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
-         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs_hold_time:5;
-        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
-         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_addr_bitlen:5;
-    };
-    uint32_t val;
-} spi_user1_reg_t;
-
-/** Type of user2 register
- *  SPI USER control register 2
- */
-typedef union {
-    struct {
-        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
-         *  The value of  command. Can be configured in CONF state.
-         */
-        uint32_t usr_command_value:16;
-        uint32_t reserved_16:11;
-        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
-         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
-         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
-         *  is valid in GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_rempty_err_end_en:1;
-        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
-         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_command_bitlen:4;
-    };
-    uint32_t val;
-} spi_user2_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of ctrl register
- *  SPI control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** dummy_out : R/W; bitpos: [3]; default: 0;
-         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
-         *  the FSPI bus signals are output. Can be configured in CONF state.
-         */
-        uint32_t dummy_out:1;
-        uint32_t reserved_4:1;
-        /** faddr_dual : R/W; bitpos: [5]; default: 0;
-         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_dual:1;
-        /** faddr_quad : R/W; bitpos: [6]; default: 0;
-         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_quad:1;
-        /** faddr_oct : HRO; bitpos: [7]; default: 0;
-         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_oct:1;
-        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
-         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_dual:1;
-        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
-         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_quad:1;
-        /** fcmd_oct : HRO; bitpos: [10]; default: 0;
-         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_oct:1;
-        uint32_t reserved_11:3;
-        /** fread_dual : R/W; bitpos: [14]; default: 0;
-         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_dual:1;
-        /** fread_quad : R/W; bitpos: [15]; default: 0;
-         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_quad:1;
-        /** fread_oct : HRO; bitpos: [16]; default: 0;
-         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_oct:1;
-        uint32_t reserved_17:1;
-        /** q_pol : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t q_pol:1;
-        /** d_pol : R/W; bitpos: [19]; default: 1;
-         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t d_pol:1;
-        /** hold_pol : R/W; bitpos: [20]; default: 1;
-         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
-         *  configured in CONF state.
-         */
-        uint32_t hold_pol:1;
-        /** wp_pol : R/W; bitpos: [21]; default: 1;
-         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t wp_pol:1;
-        uint32_t reserved_22:1;
-        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
-         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
-         *  state.
-         */
-        uint32_t rd_bit_order:2;
-        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
-         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
-         *  configured in CONF state.
-         */
-        uint32_t wr_bit_order:2;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} spi_ctrl_reg_t;
-
-/** Type of ms_dlen register
- *  SPI data bit length control register
- */
-typedef union {
-    struct {
-        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  The value of these bits is the configured SPI transmission data bit length in
-         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
-         *  the configured bit length in slave mode DMA RX controlled transfer. The register
-         *  value shall be (bit_num-1). Can be configured in CONF state.
-         */
-        uint32_t ms_data_bitlen:18;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} spi_ms_dlen_reg_t;
-
-/** Type of misc register
- *  SPI misc register
- */
-typedef union {
-    struct {
-        /** cs0_dis : R/W; bitpos: [0]; default: 0;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs0_dis:1;
-        /** cs1_dis : R/W; bitpos: [1]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs1_dis:1;
-        /** cs2_dis : R/W; bitpos: [2]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs2_dis:1;
-        /** cs3_dis : R/W; bitpos: [3]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs3_dis:1;
-        /** cs4_dis : R/W; bitpos: [4]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs4_dis:1;
-        /** cs5_dis : R/W; bitpos: [5]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs5_dis:1;
-        /** ck_dis : R/W; bitpos: [6]; default: 0;
-         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
-         */
-        uint32_t ck_dis:1;
-        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
-         *  In the master mode the bits are the polarity of spi cs line, the value is
-         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-         */
-        uint32_t master_cs_pol:6;
-        uint32_t reserved_13:3;
-        /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0;
-         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
-         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
-         */
-        uint32_t clk_data_dtr_en:1;
-        /** data_dtr_en : HRO; bitpos: [17]; default: 0;
-         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
-         *  Can be configured in CONF state.
-         */
-        uint32_t data_dtr_en:1;
-        /** addr_dtr_en : HRO; bitpos: [18]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t addr_dtr_en:1;
-        /** cmd_dtr_en : HRO; bitpos: [19]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
-         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cmd_dtr_en:1;
-        uint32_t reserved_20:3;
-        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
-         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
-         *  CONF state.
-         */
-        uint32_t slave_cs_pol:1;
-        /** dqs_idle_edge : HRO; bitpos: [24]; default: 0;
-         *  The default value of spi_dqs. Can be configured in CONF state.
-         */
-        uint32_t dqs_idle_edge:1;
-        uint32_t reserved_25:4;
-        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
-         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
-         *  configured in CONF state.
-         */
-        uint32_t ck_idle_edge:1;
-        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
-         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
-         */
-        uint32_t cs_keep_active:1;
-        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
-         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
-         *  spi quad input swap disable. Can be configured in CONF state.
-         */
-        uint32_t quad_din_pin_swap:1;
-    };
-    uint32_t val;
-} spi_misc_reg_t;
-
-/** Type of dma_conf register
- *  SPI DMA control register
- */
-typedef union {
-    struct {
-        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
-         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
-         *  DMA TX FIFO is ready for sending data.
-         */
-        uint32_t dma_outfifo_empty:1;
-        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
-         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
-         *  0: DMA RX FIFO is ready for receiving data.
-         */
-        uint32_t dma_infifo_full:1;
-        uint32_t reserved_2:16;
-        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
-         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-         */
-        uint32_t dma_slv_seg_trans_en:1;
-        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
-         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
-         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_rx_seg_trans_clr_en:1;
-        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
-         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
-         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_tx_seg_trans_clr_en:1;
-        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
-         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
-         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
-         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
-         *  spi_dma_seg_trans_done in seg-trans.
-         */
-        uint32_t rx_eof_en:1;
-        uint32_t reserved_22:5;
-        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
-         *  Set this bit to enable SPI DMA controlled receive data mode.
-         */
-        uint32_t dma_rx_ena:1;
-        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to enable SPI DMA controlled send data mode.
-         */
-        uint32_t dma_tx_ena:1;
-        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
-         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-         *  slave mode transfer.
-         */
-        uint32_t rx_afifo_rst:1;
-        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
-         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
-         *  controlled mode transfer and master mode transfer.
-         */
-        uint32_t buf_afifo_rst:1;
-        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
-         *  controlled mode transfer.
-         */
-        uint32_t dma_afifo_rst:1;
-    };
-    uint32_t val;
-} spi_dma_conf_reg_t;
-
-/** Type of slave register
- *  SPI slave control register
- */
-typedef union {
-    struct {
-        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
-         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
-         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on. Can be configured in CONF state.
-         */
-        uint32_t clk_mode:2;
-        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
-         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
-         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-         */
-        uint32_t clk_mode_13:1;
-        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
-         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
-         *  0: output data at tsck posedge
-         */
-        uint32_t rsck_data_out:1;
-        uint32_t reserved_4:4;
-        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  DMA controlled mode(Rd_DMA). 0: others
-         */
-        uint32_t slv_rddma_bitlen_en:1;
-        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in DMA controlled mode(Wr_DMA). 0: others
-         */
-        uint32_t slv_wrdma_bitlen_en:1;
-        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  CPU controlled mode(Rd_BUF). 0: others
-         */
-        uint32_t slv_rdbuf_bitlen_en:1;
-        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in CPU controlled mode(Wr_BUF). 0: others
-         */
-        uint32_t slv_wrbuf_bitlen_en:1;
-        uint32_t reserved_12:10;
-        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
-         *  The magic value of BM table in master DMA seg-trans.
-         */
-        uint32_t dma_seg_magic_value:4;
-        /** slave_mode : R/W; bitpos: [26]; default: 0;
-         *  Set SPI work mode. 1: slave mode 0: master mode.
-         */
-        uint32_t slave_mode:1;
-        /** soft_reset : WT; bitpos: [27]; default: 0;
-         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
-         *  configured in CONF state.
-         */
-        uint32_t soft_reset:1;
-        /** usr_conf : R/W; bitpos: [28]; default: 0;
-         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
-         *  will start. 0: This is not seg-trans mode.
-         */
-        uint32_t usr_conf:1;
-        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
-         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
-         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
-         *  transfer.
-         */
-        uint32_t mst_fd_wait_dma_tx_data:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} spi_slave_reg_t;
-
-/** Type of slave1 register
- *  SPI slave control register 1
- */
-typedef union {
-    struct {
-        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
-         *  The transferred data bit length in SPI slave FD and HD mode.
-         */
-        uint32_t slv_data_bitlen:18;
-        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
-         *  In the slave mode it is the value of command.
-         */
-        uint32_t slv_last_command:8;
-        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
-         *  In the slave mode it is the value of address.
-         */
-        uint32_t slv_last_addr:6;
-    };
-    uint32_t val;
-} spi_slave1_reg_t;
-
-
-/** Group: Clock control registers */
-/** Type of clock register
- *  SPI clock control register
- */
-typedef union {
-    struct {
-        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
-         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
-         *  0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_l:6;
-        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
-         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-         *  must be 0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_h:6;
-        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
-         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
-         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-         */
-        uint32_t clkcnt_n:6;
-        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
-         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
-         */
-        uint32_t clkdiv_pre:4;
-        uint32_t reserved_22:9;
-        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
-         *  clock. Can be configured in CONF state.
-         */
-        uint32_t clk_equ_sysclk:1;
-    };
-    uint32_t val;
-} spi_clock_reg_t;
-
-/** Type of clk_gate register
- *  SPI module clock and register clock control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable clk gate
-         */
-        uint32_t clk_en:1;
-        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to power on the SPI module clock.
-         */
-        uint32_t mst_clk_active:1;
-        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
-         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
-         *  0: XTAL CLK.
-         */
-        uint32_t mst_clk_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} spi_clk_gate_reg_t;
-
-
-/** Group: Timing registers */
-/** Type of din_mode register
- *  SPI input delay mode configuration
- */
-typedef union {
-    struct {
-        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din0_mode:2;
-        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din1_mode:2;
-        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din2_mode:2;
-        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din3_mode:2;
-        /** din4_mode : HRO; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din4_mode:2;
-        /** din5_mode : HRO; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din5_mode:2;
-        /** din6_mode : HRO; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din6_mode:2;
-        /** din7_mode : HRO; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din7_mode:2;
-        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
-         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
-         *  state.
-         */
-        uint32_t timing_hclk_active:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} spi_din_mode_reg_t;
-
-/** Type of din_num register
- *  SPI input delay number configuration
- */
-typedef union {
-    struct {
-        /** din0_num : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din0_num:2;
-        /** din1_num : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din1_num:2;
-        /** din2_num : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din2_num:2;
-        /** din3_num : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din3_num:2;
-        /** din4_num : HRO; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din4_num:2;
-        /** din5_num : HRO; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din5_num:2;
-        /** din6_num : HRO; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din6_num:2;
-        /** din7_num : HRO; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din7_num:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} spi_din_num_reg_t;
-
-/** Type of dout_mode register
- *  SPI output delay mode configuration
- */
-typedef union {
-    struct {
-        /** dout0_mode : R/W; bitpos: [0]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout0_mode:1;
-        /** dout1_mode : R/W; bitpos: [1]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout1_mode:1;
-        /** dout2_mode : R/W; bitpos: [2]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout2_mode:1;
-        /** dout3_mode : R/W; bitpos: [3]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout3_mode:1;
-        /** dout4_mode : HRO; bitpos: [4]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout4_mode:1;
-        /** dout5_mode : HRO; bitpos: [5]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout5_mode:1;
-        /** dout6_mode : HRO; bitpos: [6]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout6_mode:1;
-        /** dout7_mode : HRO; bitpos: [7]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout7_mode:1;
-        /** d_dqs_mode : HRO; bitpos: [8]; default: 0;
-         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
-         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t d_dqs_mode:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} spi_dout_mode_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of dma_int_ena register
- *  SPI interrupt enable register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : R/W; bitpos: [5]; default: 0;
-         *  The enable bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : R/W; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : R/W; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : R/W; bitpos: [11]; default: 0;
-         *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : R/W; bitpos: [12]; default: 0;
-         *  The enable bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : R/W; bitpos: [13]; default: 0;
-         *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : R/W; bitpos: [14]; default: 0;
-         *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : R/W; bitpos: [15]; default: 0;
-         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : R/W; bitpos: [16]; default: 0;
-         *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : R/W; bitpos: [17]; default: 0;
-         *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : R/W; bitpos: [18]; default: 0;
-         *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : R/W; bitpos: [19]; default: 0;
-         *  The enable bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2:1;
-        /** app1 : R/W; bitpos: [20]; default: 0;
-         *  The enable bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_ena_reg_t;
-
-/** Type of dma_int_clr register
- *  SPI interrupt clear register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : WT; bitpos: [5]; default: 0;
-         *  The clear bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : WT; bitpos: [6]; default: 0;
-         *  The clear bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : WT; bitpos: [7]; default: 0;
-         *  The clear bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : WT; bitpos: [8]; default: 0;
-         *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : WT; bitpos: [9]; default: 0;
-         *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : WT; bitpos: [10]; default: 0;
-         *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : WT; bitpos: [11]; default: 0;
-         *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : WT; bitpos: [12]; default: 0;
-         *  The clear bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : WT; bitpos: [13]; default: 0;
-         *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : WT; bitpos: [14]; default: 0;
-         *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : WT; bitpos: [15]; default: 0;
-         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : WT; bitpos: [16]; default: 0;
-         *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0;
-         *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0;
-         *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : WT; bitpos: [19]; default: 0;
-         *  The clear bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2:1;
-        /** app1 : WT; bitpos: [20]; default: 0;
-         *  The clear bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_clr_reg_t;
-
-/** Type of dma_int_raw register
- *  SPI interrupt raw register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : R/WTC/SS; bitpos: [0]; default: 0;
-         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
-         *  receive data.  0: Others.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : R/WTC/SS; bitpos: [1]; default: 0;
-         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
-         *  master mode and send out all 0 in slave mode.  0: Others.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
-         *  ended. 0: others.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
-         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
-         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
-         *  is not ended or not occurred.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
-         *  is error in the DMA seg-conf-trans. 0: others.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
-         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
-         *  bigger than 63. 0: Others.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
-         *  current SPI slave HD mode transmission is not supported. 0: Others.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
-         *  write-full error when SPI inputs data in master mode. 0: Others.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app2:1;
-        /** app1 : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_raw_reg_t;
-
-/** Type of dma_int_st register
- *  SPI interrupt status register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : RO; bitpos: [5]; default: 0;
-         *  The status bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : RO; bitpos: [6]; default: 0;
-         *  The status bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : RO; bitpos: [7]; default: 0;
-         *  The status bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : RO; bitpos: [8]; default: 0;
-         *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : RO; bitpos: [9]; default: 0;
-         *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : RO; bitpos: [11]; default: 0;
-         *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : RO; bitpos: [12]; default: 0;
-         *  The status bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : RO; bitpos: [13]; default: 0;
-         *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : RO; bitpos: [14]; default: 0;
-         *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : RO; bitpos: [15]; default: 0;
-         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : RO; bitpos: [16]; default: 0;
-         *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : RO; bitpos: [17]; default: 0;
-         *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : RO; bitpos: [18]; default: 0;
-         *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : RO; bitpos: [19]; default: 0;
-         *  The status bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2:1;
-        /** app1 : RO; bitpos: [20]; default: 0;
-         *  The status bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_st_reg_t;
-
-/** Type of dma_int_set register
- *  SPI interrupt software set register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
-         *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_set:1;
-        /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
-         *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_set:1;
-        /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
-         *  The software set bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_set:1;
-        /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
-         *  The software set bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_set:1;
-        /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
-         *  The software set bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_set:1;
-        /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
-         *  The software set bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_set:1;
-        /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
-         *  The software set bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_set:1;
-        /** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
-         *  The software set bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_set:1;
-        /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
-         *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_set:1;
-        /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
-         *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_set:1;
-        /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
-         *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_set:1;
-        /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
-         *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_set:1;
-        /** trans_done_int_set : WT; bitpos: [12]; default: 0;
-         *  The software set bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_set:1;
-        /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
-         *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_set:1;
-        /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
-         *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_set:1;
-        /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
-         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_set:1;
-        /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
-         *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_set:1;
-        /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
-         *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_set:1;
-        /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
-         *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_set:1;
-        /** app2_int_set : WT; bitpos: [19]; default: 0;
-         *  The software set bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_set:1;
-        /** app1_int_set : WT; bitpos: [20]; default: 0;
-         *  The software set bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_set:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_set_reg_t;
-
-
-/** Group: CPU-controlled data buffer */
-/** Type of wn register
- *  SPI CPU-controlled buffer
- */
-typedef union {
-    struct {
-        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf:32;
-    };
-    uint32_t val;
-} spi_wn_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35656448;
-         *  SPI register version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} spi_date_reg_t;
-
-
-typedef struct spi_dev_t {
-    volatile spi_cmd_reg_t cmd;
-    volatile spi_addr_reg_t addr;
-    volatile spi_ctrl_reg_t ctrl;
-    volatile spi_clock_reg_t clock;
-    volatile spi_user_reg_t user;
-    volatile spi_user1_reg_t user1;
-    volatile spi_user2_reg_t user2;
-    volatile spi_ms_dlen_reg_t ms_dlen;
-    volatile spi_misc_reg_t misc;
-    volatile spi_din_mode_reg_t din_mode;
-    volatile spi_din_num_reg_t din_num;
-    volatile spi_dout_mode_reg_t dout_mode;
-    volatile spi_dma_conf_reg_t dma_conf;
-    volatile spi_dma_int_ena_reg_t dma_int_ena;
-    volatile spi_dma_int_clr_reg_t dma_int_clr;
-    volatile spi_dma_int_raw_reg_t dma_int_raw;
-    volatile spi_dma_int_st_reg_t dma_int_st;
-    volatile spi_dma_int_set_reg_t dma_int_set;
-    uint32_t reserved_048[20];
-    volatile spi_wn_reg_t data_buf[16];
-    uint32_t reserved_0d8[2];
-    volatile spi_slave_reg_t slave;
-    volatile spi_slave1_reg_t slave1;
-    volatile spi_clk_gate_reg_t clk_gate;
-    uint32_t reserved_0ec;
-    volatile spi_date_reg_t date;
-} spi_dev_t;
-
-extern spi_dev_t GPSPI2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/system_reg.h b/components/soc/esp32c6/include/soc/system_reg.h
index 4ed6ac2ac25..17cf94805ed 100644
--- a/components/soc/esp32c6/include/soc/system_reg.h
+++ b/components/soc/esp32c6/include/soc/system_reg.h
@@ -7,6 +7,6 @@
 #include "soc/hp_system_reg.h"
 
 // TODO: IDF-5720
-#include "intpri_reg.h"
+#include "soc/intpri_reg.h"
 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
 #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
diff --git a/components/soc/esp32c6/include/soc/trace_reg.h b/components/soc/esp32c6/include/soc/trace_reg.h
deleted file mode 100644
index a5c3eda9dc7..00000000000
--- a/components/soc/esp32c6/include/soc/trace_reg.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TRACE_MEM_START_ADDR_REG register
- *  mem start addr
- */
-#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
-/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  The start address of trace memory
- */
-#define TRACE_MEM_STAET_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_STAET_ADDR_M  (TRACE_MEM_STAET_ADDR_V << TRACE_MEM_STAET_ADDR_S)
-#define TRACE_MEM_STAET_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_STAET_ADDR_S  0
-
-/** TRACE_MEM_END_ADDR_REG register
- *  mem end addr
- */
-#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
-/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  The end address of trace memory
- */
-#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
-#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_END_ADDR_S  0
-
-/** TRACE_MEM_CURRENT_ADDR_REG register
- *  mem current addr
- */
-#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
-/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  current_mem_addr,indicate that next writing addr
- */
-#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
-#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_CURRENT_ADDR_S  0
-
-/** TRACE_MEM_ADDR_UPDATE_REG register
- *  mem addr update
- */
-#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
-/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
- *  when set this reg, the current_mem_addr will update to start_addr
- */
-#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
-
-/** TRACE_FIFO_STATUS_REG register
- *  fifo status register
- */
-#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
-/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  1 indicate that fifo is empty
- */
-#define TRACE_FIFO_EMPTY    (BIT(0))
-#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
-#define TRACE_FIFO_EMPTY_V  0x00000001U
-#define TRACE_FIFO_EMPTY_S  0
-/** TRACE_WORK_STATUS : RO; bitpos: [1]; default: 0;
- *  mem_full interrupt status
- */
-#define TRACE_WORK_STATUS    (BIT(1))
-#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
-#define TRACE_WORK_STATUS_V  0x00000001U
-#define TRACE_WORK_STATUS_S  1
-
-/** TRACE_INTR_ENA_REG register
- *  interrupt enable register
- */
-#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
-/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
- *  Set 1 enable fifo_overflow interrupt
- */
-#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
-/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
- *  Set 1 enable mem_full interrupt
- */
-#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
-#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
-#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_ENA_S  1
-
-/** TRACE_INTR_RAW_REG register
- *  interrupt status register
- */
-#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
-/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
- *  fifo_overflow interrupt status
- */
-#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
-/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
- *  mem_full interrupt status
- */
-#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
-#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
-#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_RAW_S  1
-
-/** TRACE_INTR_CLR_REG register
- *  interrupt clear register
- */
-#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
-/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
- *  Set 1 clr fifo overflow interrupt
- */
-#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
-/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
- *  Set 1 clr mem full interrupt
- */
-#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
-#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
-#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_CLR_S  1
-
-/** TRACE_TRIGGER_REG register
- *  trigger register
- */
-#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
-/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
- *  [0] set 1 start trace.
- */
-#define TRACE_TRIGGER_ON    (BIT(0))
-#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
-#define TRACE_TRIGGER_ON_V  0x00000001U
-#define TRACE_TRIGGER_ON_S  0
-/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
- *  set 1 stop trace.
- */
-#define TRACE_TRIGGER_OFF    (BIT(1))
-#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
-#define TRACE_TRIGGER_OFF_V  0x00000001U
-#define TRACE_TRIGGER_OFF_S  1
-/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
- *  if this reg is 1, trace will loop wrtie trace_mem.  If is 0, when mem_current_addr
- *  at mem_end_addr, it will stop at the mem_end_addr
- */
-#define TRACE_MEM_LOOP    (BIT(2))
-#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
-#define TRACE_MEM_LOOP_V  0x00000001U
-#define TRACE_MEM_LOOP_S  2
-/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
- *  enable encoder auto-restart, when lost package, the encoder will end, if enable
- *  auto-restart, when fifo empty, encoder will restart and send a sync package.
- */
-#define TRACE_RESTART_ENA    (BIT(3))
-#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
-#define TRACE_RESTART_ENA_V  0x00000001U
-#define TRACE_RESTART_ENA_S  3
-
-/** TRACE_RESYNC_PROLONGED_REG register
- *  resync configuration register
- */
-#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24)
-/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
- *  count number, when count to this value, send a sync package
- */
-#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
-#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
-#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
-#define TRACE_RESYNC_PROLONGED_S  0
-/** TRACE_RESYNC_MODE : R/W; bitpos: [24]; default: 0;
- *  resyc mode sel: 0: default, cycle count   1: package num count
- */
-#define TRACE_RESYNC_MODE    (BIT(24))
-#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
-#define TRACE_RESYNC_MODE_V  0x00000001U
-#define TRACE_RESYNC_MODE_S  24
-
-/** TRACE_CLOCK_GATE_REG register
- *  Clock gate control register
- */
-#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x28)
-/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable clock gate when access all registers in this module.
- */
-#define TRACE_CLK_EN    (BIT(0))
-#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
-#define TRACE_CLK_EN_V  0x00000001U
-#define TRACE_CLK_EN_S  0
-
-/** TRACE_DATE_REG register
- *  Version control register
- */
-#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
-/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35663920;
- *  version control register. Note that this default value stored is the latest date
- *  when the hardware logic was updated.
- */
-#define TRACE_DATE    0x0FFFFFFFU
-#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
-#define TRACE_DATE_V  0x0FFFFFFFU
-#define TRACE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/trace_struct.h b/components/soc/esp32c6/include/soc/trace_struct.h
deleted file mode 100644
index 3b8330b6b0e..00000000000
--- a/components/soc/esp32c6/include/soc/trace_struct.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Trace memory configuration registers */
-/** Type of mem_start_addr register
- *  mem start addr
- */
-typedef union {
-    struct {
-        /** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  The start address of trace memory
-         */
-        uint32_t mem_start_addr:32;
-    };
-    uint32_t val;
-} trace_mem_start_addr_reg_t;
-
-/** Type of mem_end_addr register
- *  mem end addr
- */
-typedef union {
-    struct {
-        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  The end address of trace memory
-         */
-        uint32_t mem_end_addr:32;
-    };
-    uint32_t val;
-} trace_mem_end_addr_reg_t;
-
-/** Type of mem_current_addr register
- *  mem current addr
- */
-typedef union {
-    struct {
-        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
-         *  current_mem_addr,indicate that next writing addr
-         */
-        uint32_t mem_current_addr:32;
-    };
-    uint32_t val;
-} trace_mem_current_addr_reg_t;
-
-/** Type of mem_addr_update register
- *  mem addr update
- */
-typedef union {
-    struct {
-        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
-         *  when set this reg, the current_mem_addr will update to start_addr
-         */
-        uint32_t mem_current_addr_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} trace_mem_addr_update_reg_t;
-
-
-/** Group: Trace fifo status register */
-/** Type of fifo_status register
- *  fifo status register
- */
-typedef union {
-    struct {
-        /** fifo_empty : RO; bitpos: [0]; default: 1;
-         *  1 indicate that fifo is empty
-         */
-        uint32_t fifo_empty:1;
-        /** work_status : RO; bitpos: [1]; default: 0;
-         *  mem_full interrupt status
-         */
-        uint32_t work_status:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_fifo_status_reg_t;
-
-
-/** Group: Trace interrupt configuration registers */
-/** Type of intr_ena register
- *  interrupt enable register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
-         *  Set 1 enable fifo_overflow interrupt
-         */
-        uint32_t fifo_overflow_intr_ena:1;
-        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
-         *  Set 1 enable mem_full interrupt
-         */
-        uint32_t mem_full_intr_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_ena_reg_t;
-
-/** Type of intr_raw register
- *  interrupt status register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
-         *  fifo_overflow interrupt status
-         */
-        uint32_t fifo_overflow_intr_raw:1;
-        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
-         *  mem_full interrupt status
-         */
-        uint32_t mem_full_intr_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_raw_reg_t;
-
-/** Type of intr_clr register
- *  interrupt clear register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
-         *  Set 1 clr fifo overflow interrupt
-         */
-        uint32_t fifo_overflow_intr_clr:1;
-        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
-         *  Set 1 clr mem full interrupt
-         */
-        uint32_t mem_full_intr_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_clr_reg_t;
-
-
-/** Group: Trace configuration register */
-/** Type of trigger register
- *  trigger register
- */
-typedef union {
-    struct {
-        /** trigger_on : WT; bitpos: [0]; default: 0;
-         *  [0] set 1 start trace.
-         */
-        uint32_t trigger_on:1;
-        /** trigger_off : WT; bitpos: [1]; default: 0;
-         *  set 1 stop trace.
-         */
-        uint32_t trigger_off:1;
-        /** mem_loop : R/W; bitpos: [2]; default: 1;
-         *  if this reg is 1, trace will loop wrtie trace_mem.  If is 0, when mem_current_addr
-         *  at mem_end_addr, it will stop at the mem_end_addr
-         */
-        uint32_t mem_loop:1;
-        /** restart_ena : R/W; bitpos: [3]; default: 1;
-         *  enable encoder auto-restart, when lost package, the encoder will end, if enable
-         *  auto-restart, when fifo empty, encoder will restart and send a sync package.
-         */
-        uint32_t restart_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} trace_trigger_reg_t;
-
-/** Type of resync_prolonged register
- *  resync configuration register
- */
-typedef union {
-    struct {
-        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
-         *  count number, when count to this value, send a sync package
-         */
-        uint32_t resync_prolonged:24;
-        /** resync_mode : R/W; bitpos: [24]; default: 0;
-         *  resyc mode sel: 0: default, cycle count   1: package num count
-         */
-        uint32_t resync_mode:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} trace_resync_prolonged_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  The bit is used to enable clock gate when access all registers in this module.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} trace_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35663920;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} trace_date_reg_t;
-
-
-typedef struct trace_dev_t {
-    volatile trace_mem_start_addr_reg_t mem_start_addr;
-    volatile trace_mem_end_addr_reg_t mem_end_addr;
-    volatile trace_mem_current_addr_reg_t mem_current_addr;
-    volatile trace_mem_addr_update_reg_t mem_addr_update;
-    volatile trace_fifo_status_reg_t fifo_status;
-    volatile trace_intr_ena_reg_t intr_ena;
-    volatile trace_intr_raw_reg_t intr_raw;
-    volatile trace_intr_clr_reg_t intr_clr;
-    volatile trace_trigger_reg_t trigger;
-    volatile trace_resync_prolonged_reg_t resync_prolonged;
-    volatile trace_clock_gate_reg_t clock_gate;
-    uint32_t reserved_02c[244];
-    volatile trace_date_reg_t date;
-} trace_dev_t;
-
-extern trace_dev_t TRACE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/uart_reg.h b/components/soc/esp32c6/include/soc/uart_reg.h
deleted file mode 100644
index abac8d92b19..00000000000
--- a/components/soc/esp32c6/include/soc/uart_reg.h
+++ /dev/null
@@ -1,1546 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** UART_FIFO_REG register
- *  FIFO data register
- */
-#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
-/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
- *  UART $n accesses FIFO via this register.
- */
-#define UART_RXFIFO_RD_BYTE    0x000000FFU
-#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
-#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
-#define UART_RXFIFO_RD_BYTE_S  0
-
-/** UART_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
-/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  what rxfifo_full_thrhd specifies.
- */
-#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
-#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_RAW_S  0
-/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
- *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- *  less than what txfifo_empty_thrhd specifies .
- */
-#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error in
- *  the data.
- */
-#define UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
-#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_PARITY_ERR_INT_RAW_S  2
-/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  .
- */
-#define UART_FRM_ERR_INT_RAW    (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
-#define UART_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_FRM_ERR_INT_RAW_S  3
-/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  the FIFO can store.
- */
-#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
-#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  DSRn signal.
- */
-#define UART_DSR_CHG_INT_RAW    (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
-#define UART_DSR_CHG_INT_RAW_V  0x00000001U
-#define UART_DSR_CHG_INT_RAW_S  5
-/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  CTSn signal.
- */
-#define UART_CTS_CHG_INT_RAW    (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
-#define UART_CTS_CHG_INT_RAW_V  0x00000001U
-#define UART_CTS_CHG_INT_RAW_S  6
-/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
- *  bit.
- */
-#define UART_BRK_DET_INT_RAW    (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
-#define UART_BRK_DET_INT_RAW_V  0x00000001U
-#define UART_BRK_DET_INT_RAW_S  7
-/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  This interrupt raw bit turns to high level when receiver takes more time than
- *  rx_tout_thrhd to receive a byte.
- */
-#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XON_INT_RAW    (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
-#define UART_SW_XON_INT_RAW_V  0x00000001U
-#define UART_SW_XON_INT_RAW_S  9
-/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives Xoff char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XOFF_INT_RAW    (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
-#define UART_SW_XOFF_INT_RAW_V  0x00000001U
-#define UART_SW_XOFF_INT_RAW_S  10
-/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a glitch in the
- *  middle of a start bit.
- */
-#define UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
-#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
-#define UART_GLITCH_DET_INT_RAW_S  11
-/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter completes  sending
- *  NULL characters after all data in Tx-FIFO are sent.
- */
-#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
-#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has kept the shortest
- *  duration after sending the  last data.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has send out all data
- *  in FIFO.
- */
-#define UART_TX_DONE_INT_RAW    (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
-#define UART_TX_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_DONE_INT_RAW_S  14
-/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  This interrupt raw bit turns to high level when detects a clash between transmitter
- *  and receiver in rs485 mode.
- */
-#define UART_RS485_CLASH_INT_RAW    (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
-#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
-#define UART_RS485_CLASH_INT_RAW_S  17
-/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the configured
- *  at_cmd char.
- */
-#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  This interrupt raw bit turns to high level when input rxd edge changes more times
- *  than what reg_active_threshold specifies in light sleeping mode.
- */
-#define UART_WAKEUP_INT_RAW    (BIT(19))
-#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
-#define UART_WAKEUP_INT_RAW_V  0x00000001U
-#define UART_WAKEUP_INT_RAW_S  19
-
-/** UART_INT_ST_REG register
- *  Masked interrupt status
- */
-#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
-/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
- *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
- */
-#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
-#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ST_S  0
-/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
- *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
- *  to 1.
- */
-#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
- *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
- */
-#define UART_PARITY_ERR_INT_ST    (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
-#define UART_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_PARITY_ERR_INT_ST_S  2
-/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
- *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
- */
-#define UART_FRM_ERR_INT_ST    (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
-#define UART_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_FRM_ERR_INT_ST_S  3
-/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
- */
-#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
-#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
- */
-#define UART_DSR_CHG_INT_ST    (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
-#define UART_DSR_CHG_INT_ST_V  0x00000001U
-#define UART_DSR_CHG_INT_ST_S  5
-/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
- *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
- */
-#define UART_CTS_CHG_INT_ST    (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
-#define UART_CTS_CHG_INT_ST_V  0x00000001U
-#define UART_CTS_CHG_INT_ST_S  6
-/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
- *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
- */
-#define UART_BRK_DET_INT_ST    (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
-#define UART_BRK_DET_INT_ST_V  0x00000001U
-#define UART_BRK_DET_INT_ST_S  7
-/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
- */
-#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
-#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
- *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
- */
-#define UART_SW_XON_INT_ST    (BIT(9))
-#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
-#define UART_SW_XON_INT_ST_V  0x00000001U
-#define UART_SW_XON_INT_ST_S  9
-/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
- *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
- */
-#define UART_SW_XOFF_INT_ST    (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
-#define UART_SW_XOFF_INT_ST_V  0x00000001U
-#define UART_SW_XOFF_INT_ST_S  10
-/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
- *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
- */
-#define UART_GLITCH_DET_INT_ST    (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
-#define UART_GLITCH_DET_INT_ST_V  0x00000001U
-#define UART_GLITCH_DET_INT_ST_S  11
-/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
- */
-#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
-#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- *  is set to 1.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
- */
-#define UART_TX_DONE_INT_ST    (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
-#define UART_TX_DONE_INT_ST_V  0x00000001U
-#define UART_TX_DONE_INT_ST_S  14
-/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
- *  set to 1.
- */
-#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
- *  to 1.
- */
-#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
-#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
- *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
- */
-#define UART_RS485_CLASH_INT_ST    (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
-#define UART_RS485_CLASH_INT_ST_V  0x00000001U
-#define UART_RS485_CLASH_INT_ST_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
- *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
- *  to 1.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
- *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
- */
-#define UART_WAKEUP_INT_ST    (BIT(19))
-#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
-#define UART_WAKEUP_INT_ST_V  0x00000001U
-#define UART_WAKEUP_INT_ST_S  19
-
-/** UART_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
-/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  This is the enable bit for rxfifo_full_int_st register.
- */
-#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
-#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ENA_S  0
-/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  This is the enable bit for txfifo_empty_int_st register.
- */
-#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  This is the enable bit for parity_err_int_st register.
- */
-#define UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
-#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_PARITY_ERR_INT_ENA_S  2
-/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  This is the enable bit for frm_err_int_st register.
- */
-#define UART_FRM_ERR_INT_ENA    (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
-#define UART_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_FRM_ERR_INT_ENA_S  3
-/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  This is the enable bit for rxfifo_ovf_int_st register.
- */
-#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
-#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for dsr_chg_int_st register.
- */
-#define UART_DSR_CHG_INT_ENA    (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
-#define UART_DSR_CHG_INT_ENA_V  0x00000001U
-#define UART_DSR_CHG_INT_ENA_S  5
-/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  This is the enable bit for cts_chg_int_st register.
- */
-#define UART_CTS_CHG_INT_ENA    (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
-#define UART_CTS_CHG_INT_ENA_V  0x00000001U
-#define UART_CTS_CHG_INT_ENA_S  6
-/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  This is the enable bit for brk_det_int_st register.
- */
-#define UART_BRK_DET_INT_ENA    (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
-#define UART_BRK_DET_INT_ENA_V  0x00000001U
-#define UART_BRK_DET_INT_ENA_S  7
-/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  This is the enable bit for rxfifo_tout_int_st register.
- */
-#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  This is the enable bit for sw_xon_int_st register.
- */
-#define UART_SW_XON_INT_ENA    (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
-#define UART_SW_XON_INT_ENA_V  0x00000001U
-#define UART_SW_XON_INT_ENA_S  9
-/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  This is the enable bit for sw_xoff_int_st register.
- */
-#define UART_SW_XOFF_INT_ENA    (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
-#define UART_SW_XOFF_INT_ENA_V  0x00000001U
-#define UART_SW_XOFF_INT_ENA_S  10
-/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  This is the enable bit for glitch_det_int_st register.
- */
-#define UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
-#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
-#define UART_GLITCH_DET_INT_ENA_S  11
-/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for tx_brk_done_int_st register.
- */
-#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
-#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit for tx_brk_idle_done_int_st register.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for tx_done_int_st register.
- */
-#define UART_TX_DONE_INT_ENA    (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
-#define UART_TX_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_DONE_INT_ENA_S  14
-/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  This is the enable bit for rs485_clash_int_st register.
- */
-#define UART_RS485_CLASH_INT_ENA    (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
-#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
-#define UART_RS485_CLASH_INT_ENA_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  This is the enable bit for at_cmd_char_det_int_st register.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for uart_wakeup_int_st register.
- */
-#define UART_WAKEUP_INT_ENA    (BIT(19))
-#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
-#define UART_WAKEUP_INT_ENA_V  0x00000001U
-#define UART_WAKEUP_INT_ENA_S  19
-
-/** UART_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
-/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the rxfifo_full_int_raw interrupt.
- */
-#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
-#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_CLR_S  0
-/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear txfifo_empty_int_raw interrupt.
- */
-#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear parity_err_int_raw interrupt.
- */
-#define UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
-#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_PARITY_ERR_INT_CLR_S  2
-/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear frm_err_int_raw interrupt.
- */
-#define UART_FRM_ERR_INT_CLR    (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
-#define UART_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_FRM_ERR_INT_CLR_S  3
-/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
- */
-#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
-#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the dsr_chg_int_raw interrupt.
- */
-#define UART_DSR_CHG_INT_CLR    (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
-#define UART_DSR_CHG_INT_CLR_V  0x00000001U
-#define UART_DSR_CHG_INT_CLR_S  5
-/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the cts_chg_int_raw interrupt.
- */
-#define UART_CTS_CHG_INT_CLR    (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
-#define UART_CTS_CHG_INT_CLR_V  0x00000001U
-#define UART_CTS_CHG_INT_CLR_S  6
-/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the brk_det_int_raw interrupt.
- */
-#define UART_BRK_DET_INT_CLR    (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
-#define UART_BRK_DET_INT_CLR_V  0x00000001U
-#define UART_BRK_DET_INT_CLR_S  7
-/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
- */
-#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the sw_xon_int_raw interrupt.
- */
-#define UART_SW_XON_INT_CLR    (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
-#define UART_SW_XON_INT_CLR_V  0x00000001U
-#define UART_SW_XON_INT_CLR_S  9
-/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the sw_xoff_int_raw interrupt.
- */
-#define UART_SW_XOFF_INT_CLR    (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
-#define UART_SW_XOFF_INT_CLR_V  0x00000001U
-#define UART_SW_XOFF_INT_CLR_S  10
-/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the glitch_det_int_raw interrupt.
- */
-#define UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
-#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
-#define UART_GLITCH_DET_INT_CLR_S  11
-/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the tx_brk_done_int_raw interrupt..
- */
-#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
-#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the tx_done_int_raw interrupt.
- */
-#define UART_TX_DONE_INT_CLR    (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
-#define UART_TX_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_DONE_INT_CLR_S  14
-/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
- */
-#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
- */
-#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit to clear the rs485_clash_int_raw interrupt.
- */
-#define UART_RS485_CLASH_INT_CLR    (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
-#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
-#define UART_RS485_CLASH_INT_CLR_S  17
-/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
- */
-#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the uart_wakeup_int_raw interrupt.
- */
-#define UART_WAKEUP_INT_CLR    (BIT(19))
-#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
-#define UART_WAKEUP_INT_CLR_V  0x00000001U
-#define UART_WAKEUP_INT_CLR_S  19
-
-/** UART_CLKDIV_SYNC_REG register
- *  Clock divider configuration
- */
-#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
-/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
- *  The integral part of the frequency divider factor.
- */
-#define UART_CLKDIV    0x00000FFFU
-#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
-#define UART_CLKDIV_V  0x00000FFFU
-#define UART_CLKDIV_S  0
-/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
- *  The decimal part of the frequency divider factor.
- */
-#define UART_CLKDIV_FRAG    0x0000000FU
-#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
-#define UART_CLKDIV_FRAG_V  0x0000000FU
-#define UART_CLKDIV_FRAG_S  20
-
-/** UART_RX_FILT_REG register
- *  Rx Filter configuration
- */
-#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
-/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
- *  when input pulse width is lower than this value the pulse is ignored.
- */
-#define UART_GLITCH_FILT    0x000000FFU
-#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
-#define UART_GLITCH_FILT_V  0x000000FFU
-#define UART_GLITCH_FILT_S  0
-/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable Rx signal filter.
- */
-#define UART_GLITCH_FILT_EN    (BIT(8))
-#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
-#define UART_GLITCH_FILT_EN_V  0x00000001U
-#define UART_GLITCH_FILT_EN_S  8
-
-/** UART_STATUS_REG register
- *  UART status register
- */
-#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
-/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
- *  Stores the byte number of valid data in Rx-FIFO.
- */
-#define UART_RXFIFO_CNT    0x000000FFU
-#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
-#define UART_RXFIFO_CNT_V  0x000000FFU
-#define UART_RXFIFO_CNT_S  0
-/** UART_DSRN : RO; bitpos: [13]; default: 0;
- *  The register represent the level value of the internal uart dsr signal.
- */
-#define UART_DSRN    (BIT(13))
-#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
-#define UART_DSRN_V  0x00000001U
-#define UART_DSRN_S  13
-/** UART_CTSN : RO; bitpos: [14]; default: 1;
- *  This register represent the level value of the internal uart cts signal.
- */
-#define UART_CTSN    (BIT(14))
-#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
-#define UART_CTSN_V  0x00000001U
-#define UART_CTSN_S  14
-/** UART_RXD : RO; bitpos: [15]; default: 1;
- *  This register represent the  level value of the internal uart rxd signal.
- */
-#define UART_RXD    (BIT(15))
-#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
-#define UART_RXD_V  0x00000001U
-#define UART_RXD_S  15
-/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
- *  Stores the byte number of data in Tx-FIFO.
- */
-#define UART_TXFIFO_CNT    0x000000FFU
-#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
-#define UART_TXFIFO_CNT_V  0x000000FFU
-#define UART_TXFIFO_CNT_S  16
-/** UART_DTRN : RO; bitpos: [29]; default: 1;
- *  This bit represents the level of the internal uart dtr signal.
- */
-#define UART_DTRN    (BIT(29))
-#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
-#define UART_DTRN_V  0x00000001U
-#define UART_DTRN_S  29
-/** UART_RTSN : RO; bitpos: [30]; default: 1;
- *  This bit represents the level of the internal uart rts signal.
- */
-#define UART_RTSN    (BIT(30))
-#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
-#define UART_RTSN_V  0x00000001U
-#define UART_RTSN_S  30
-/** UART_TXD : RO; bitpos: [31]; default: 1;
- *  This bit represents the  level of the internal uart txd signal.
- */
-#define UART_TXD    (BIT(31))
-#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
-#define UART_TXD_V  0x00000001U
-#define UART_TXD_S  31
-
-/** UART_CONF0_SYNC_REG register
- *  a
- */
-#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
-/** UART_PARITY : R/W; bitpos: [0]; default: 0;
- *  This register is used to configure the parity check mode.
- */
-#define UART_PARITY    (BIT(0))
-#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
-#define UART_PARITY_V  0x00000001U
-#define UART_PARITY_S  0
-/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable uart parity check.
- */
-#define UART_PARITY_EN    (BIT(1))
-#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
-#define UART_PARITY_EN_V  0x00000001U
-#define UART_PARITY_EN_S  1
-/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
- *  This register is used to set the length of data.
- */
-#define UART_BIT_NUM    0x00000003U
-#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
-#define UART_BIT_NUM_V  0x00000003U
-#define UART_BIT_NUM_S  2
-/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
- *  This register is used to set the length of  stop bit.
- */
-#define UART_STOP_BIT_NUM    0x00000003U
-#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
-#define UART_STOP_BIT_NUM_V  0x00000003U
-#define UART_STOP_BIT_NUM_S  4
-/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
- *  is done.
- */
-#define UART_TXD_BRK    (BIT(6))
-#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
-#define UART_TXD_BRK_V  0x00000001U
-#define UART_TXD_BRK_S  6
-/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
- *  Set this bit to enable IrDA loopback mode.
- */
-#define UART_IRDA_DPLX    (BIT(7))
-#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
-#define UART_IRDA_DPLX_V  0x00000001U
-#define UART_IRDA_DPLX_S  7
-/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
- *  This is the start enable bit for IrDA transmitter.
- */
-#define UART_IRDA_TX_EN    (BIT(8))
-#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
-#define UART_IRDA_TX_EN_V  0x00000001U
-#define UART_IRDA_TX_EN_S  8
-/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
- *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
- *  transmitter's 11th bit to 0.
- */
-#define UART_IRDA_WCTL    (BIT(9))
-#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
-#define UART_IRDA_WCTL_V  0x00000001U
-#define UART_IRDA_WCTL_S  9
-/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
- *  Set this bit to invert the level of  IrDA transmitter.
- */
-#define UART_IRDA_TX_INV    (BIT(10))
-#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
-#define UART_IRDA_TX_INV_V  0x00000001U
-#define UART_IRDA_TX_INV_S  10
-/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
- *  Set this bit to invert the level of IrDA receiver.
- */
-#define UART_IRDA_RX_INV    (BIT(11))
-#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
-#define UART_IRDA_RX_INV_V  0x00000001U
-#define UART_IRDA_RX_INV_S  11
-/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable uart loopback test mode.
- */
-#define UART_LOOPBACK    (BIT(12))
-#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
-#define UART_LOOPBACK_V  0x00000001U
-#define UART_LOOPBACK_S  12
-/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
- *  Set this bit to enable flow control function for transmitter.
- */
-#define UART_TX_FLOW_EN    (BIT(13))
-#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
-#define UART_TX_FLOW_EN_V  0x00000001U
-#define UART_TX_FLOW_EN_S  13
-/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
- *  Set this bit to enable IrDA protocol.
- */
-#define UART_IRDA_EN    (BIT(14))
-#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
-#define UART_IRDA_EN_V  0x00000001U
-#define UART_IRDA_EN_S  14
-/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
- *  Set this bit to inverse the level value of uart rxd signal.
- */
-#define UART_RXD_INV    (BIT(15))
-#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
-#define UART_RXD_INV_V  0x00000001U
-#define UART_RXD_INV_S  15
-/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart txd signal.
- */
-#define UART_TXD_INV    (BIT(16))
-#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
-#define UART_TXD_INV_V  0x00000001U
-#define UART_TXD_INV_S  16
-/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
- *  Disable UART Rx data overflow detect.
- */
-#define UART_DIS_RX_DAT_OVF    (BIT(17))
-#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
-#define UART_DIS_RX_DAT_OVF_V  0x00000001U
-#define UART_DIS_RX_DAT_OVF_S  17
-/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
- *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
- *  stores the data even if the  received data is wrong.
- */
-#define UART_ERR_WR_MASK    (BIT(18))
-#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
-#define UART_ERR_WR_MASK_V  0x00000001U
-#define UART_ERR_WR_MASK_S  18
-/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for detecting baudrate.
- */
-#define UART_AUTOBAUD_EN    (BIT(19))
-#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
-#define UART_AUTOBAUD_EN_V  0x00000001U
-#define UART_AUTOBAUD_EN_S  19
-/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
- *  UART memory clock gate enable signal.
- */
-#define UART_MEM_CLK_EN    (BIT(20))
-#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
-#define UART_MEM_CLK_EN_V  0x00000001U
-#define UART_MEM_CLK_EN_S  20
-/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
- *  This register is used to configure the software rts signal which is used in
- *  software flow control.
- */
-#define UART_SW_RTS    (BIT(21))
-#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
-#define UART_SW_RTS_V  0x00000001U
-#define UART_SW_RTS_S  21
-/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
- *  Set this bit to reset the uart receive-FIFO.
- */
-#define UART_RXFIFO_RST    (BIT(22))
-#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
-#define UART_RXFIFO_RST_V  0x00000001U
-#define UART_RXFIFO_RST_S  22
-/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
- *  Set this bit to reset the uart transmit-FIFO.
- */
-#define UART_TXFIFO_RST    (BIT(23))
-#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
-#define UART_TXFIFO_RST_V  0x00000001U
-#define UART_TXFIFO_RST_S  23
-
-/** UART_CONF1_REG register
- *  Configuration register 1
- */
-#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
-/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
- *  It will produce rxfifo_full_int interrupt when receiver receives more data than
- *  this register value.
- */
-#define UART_RXFIFO_FULL_THRHD    0x000000FFU
-#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
-#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
-#define UART_RXFIFO_FULL_THRHD_S  0
-/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
- *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
- *  than this register value.
- */
-#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
-#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
-#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
-#define UART_TXFIFO_EMPTY_THRHD_S  8
-/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart cts signal.
- */
-#define UART_CTS_INV    (BIT(16))
-#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
-#define UART_CTS_INV_V  0x00000001U
-#define UART_CTS_INV_S  16
-/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
- *  Set this bit to inverse the level value of uart dsr signal.
- */
-#define UART_DSR_INV    (BIT(17))
-#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
-#define UART_DSR_INV_V  0x00000001U
-#define UART_DSR_INV_S  17
-/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
- *  Set this bit to inverse the level value of uart rts signal.
- */
-#define UART_RTS_INV    (BIT(18))
-#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
-#define UART_RTS_INV_V  0x00000001U
-#define UART_RTS_INV_S  18
-/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
- *  Set this bit to inverse the level value of uart dtr signal.
- */
-#define UART_DTR_INV    (BIT(19))
-#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
-#define UART_DTR_INV_V  0x00000001U
-#define UART_DTR_INV_S  19
-/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
- *  This register is used to configure the software dtr signal which is used in
- *  software flow control.
- */
-#define UART_SW_DTR    (BIT(20))
-#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
-#define UART_SW_DTR_V  0x00000001U
-#define UART_SW_DTR_S  20
-/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define UART_CLK_EN    (BIT(21))
-#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
-#define UART_CLK_EN_V  0x00000001U
-#define UART_CLK_EN_S  21
-
-/** UART_HWFC_CONF_SYNC_REG register
- *  Hardware flow-control configuration
- */
-#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
-/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
- *  This register is used to configure the maximum amount of data that can be received
- *  when hardware flow control works.
- */
-#define UART_RX_FLOW_THRHD    0x000000FFU
-#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
-#define UART_RX_FLOW_THRHD_V  0x000000FFU
-#define UART_RX_FLOW_THRHD_S  0
-/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
- *  This is the flow enable bit for UART receiver.
- */
-#define UART_RX_FLOW_EN    (BIT(8))
-#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
-#define UART_RX_FLOW_EN_V  0x00000001U
-#define UART_RX_FLOW_EN_S  8
-
-/** UART_SLEEP_CONF0_REG register
- *  UART sleep configure register 0
- */
-#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
-/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified wake up char1 to wake up
- */
-#define UART_WK_CHAR1    0x000000FFU
-#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
-#define UART_WK_CHAR1_V  0x000000FFU
-#define UART_WK_CHAR1_S  0
-/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
- *  This register restores the specified wake up char2 to wake up
- */
-#define UART_WK_CHAR2    0x000000FFU
-#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
-#define UART_WK_CHAR2_V  0x000000FFU
-#define UART_WK_CHAR2_S  8
-/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
- *  This register restores the specified wake up char3 to wake up
- */
-#define UART_WK_CHAR3    0x000000FFU
-#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
-#define UART_WK_CHAR3_V  0x000000FFU
-#define UART_WK_CHAR3_S  16
-/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
- *  This register restores the specified wake up char4 to wake up
- */
-#define UART_WK_CHAR4    0x000000FFU
-#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
-#define UART_WK_CHAR4_V  0x000000FFU
-#define UART_WK_CHAR4_S  24
-
-/** UART_SLEEP_CONF1_REG register
- *  UART sleep configure register 1
- */
-#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
-/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified char0 to wake up
- */
-#define UART_WK_CHAR0    0x000000FFU
-#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
-#define UART_WK_CHAR0_V  0x000000FFU
-#define UART_WK_CHAR0_S  0
-
-/** UART_SLEEP_CONF2_REG register
- *  UART sleep configure register 2
- */
-#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
-/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
- *  The uart is activated from light sleeping mode when the input rxd edge changes more
- *  times than this register value.
- */
-#define UART_ACTIVE_THRESHOLD    0x000003FFU
-#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
-#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
-#define UART_ACTIVE_THRESHOLD_S  0
-/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
- *  In wake up mode 1 this field is used to set the received data number threshold to
- *  wake up chip.
- */
-#define UART_RX_WAKE_UP_THRHD    0x000000FFU
-#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
-#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
-#define UART_RX_WAKE_UP_THRHD_S  10
-/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
- *  This register is used to select number of wake up char.
- */
-#define UART_WK_CHAR_NUM    0x00000007U
-#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
-#define UART_WK_CHAR_NUM_V  0x00000007U
-#define UART_WK_CHAR_NUM_S  18
-/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
- *  This register is used to mask  wake up char.
- */
-#define UART_WK_CHAR_MASK    0x0000001FU
-#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
-#define UART_WK_CHAR_MASK_V  0x0000001FU
-#define UART_WK_CHAR_MASK_S  21
-/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
- *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
- *  received data number larger than
- */
-#define UART_WK_MODE_SEL    0x00000003U
-#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
-#define UART_WK_MODE_SEL_V  0x00000003U
-#define UART_WK_MODE_SEL_S  26
-
-/** UART_SWFC_CONF0_SYNC_REG register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
-/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
- *  This register stores the Xon flow control char.
- */
-#define UART_XON_CHAR    0x000000FFU
-#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
-#define UART_XON_CHAR_V  0x000000FFU
-#define UART_XON_CHAR_S  0
-/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
- *  This register stores the Xoff flow control char.
- */
-#define UART_XOFF_CHAR    0x000000FFU
-#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
-#define UART_XOFF_CHAR_V  0x000000FFU
-#define UART_XOFF_CHAR_S  8
-/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
- *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
- *  this status, UART Tx can not transmit XOFF even the received data number is larger
- *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
- *  UART Tx is disabled.
- */
-#define UART_XON_XOFF_STILL_SEND    (BIT(16))
-#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
-#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
-#define UART_XON_XOFF_STILL_SEND_S  16
-/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
- *  Set this bit to enable software flow control. It is used with register sw_xon or
- *  sw_xoff.
- */
-#define UART_SW_FLOW_CON_EN    (BIT(17))
-#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
-#define UART_SW_FLOW_CON_EN_V  0x00000001U
-#define UART_SW_FLOW_CON_EN_S  17
-/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
- *  Set this bit to remove flow control char from the received data.
- */
-#define UART_XONOFF_DEL    (BIT(18))
-#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
-#define UART_XONOFF_DEL_V  0x00000001U
-#define UART_XONOFF_DEL_S  18
-/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
- *  Set this bit to enable the transmitter to go on sending data.
- */
-#define UART_FORCE_XON    (BIT(19))
-#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
-#define UART_FORCE_XON_V  0x00000001U
-#define UART_FORCE_XON_S  19
-/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
- *  Set this bit to stop the  transmitter from sending data.
- */
-#define UART_FORCE_XOFF    (BIT(20))
-#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
-#define UART_FORCE_XOFF_V  0x00000001U
-#define UART_FORCE_XOFF_S  20
-/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
- *  Set this bit to send Xon char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XON    (BIT(21))
-#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
-#define UART_SEND_XON_V  0x00000001U
-#define UART_SEND_XON_S  21
-/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
- *  Set this bit to send Xoff char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XOFF    (BIT(22))
-#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
-#define UART_SEND_XOFF_V  0x00000001U
-#define UART_SEND_XOFF_S  22
-
-/** UART_SWFC_CONF1_REG register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
-/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
- *  When the data amount in Rx-FIFO is less than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xon char.
- */
-#define UART_XON_THRESHOLD    0x000000FFU
-#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
-#define UART_XON_THRESHOLD_V  0x000000FFU
-#define UART_XON_THRESHOLD_S  0
-/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
- *  When the data amount in Rx-FIFO is more than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
- */
-#define UART_XOFF_THRESHOLD    0x000000FFU
-#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
-#define UART_XOFF_THRESHOLD_V  0x000000FFU
-#define UART_XOFF_THRESHOLD_S  8
-
-/** UART_TXBRK_CONF_SYNC_REG register
- *  Tx Break character configuration
- */
-#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
-/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
- *  This register is used to configure the number of 0 to be sent after the process of
- *  sending data is done. It is active when txd_brk is set to 1.
- */
-#define UART_TX_BRK_NUM    0x000000FFU
-#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
-#define UART_TX_BRK_NUM_V  0x000000FFU
-#define UART_TX_BRK_NUM_S  0
-
-/** UART_IDLE_CONF_SYNC_REG register
- *  Frame-end idle configuration
- */
-#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
-/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
- *  It will produce frame end signal when receiver takes more time to receive one byte
- *  data than this register value.
- */
-#define UART_RX_IDLE_THRHD    0x000003FFU
-#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
-#define UART_RX_IDLE_THRHD_V  0x000003FFU
-#define UART_RX_IDLE_THRHD_S  0
-/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
- *  This register is used to configure the duration time between transfers.
- */
-#define UART_TX_IDLE_NUM    0x000003FFU
-#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
-#define UART_TX_IDLE_NUM_V  0x000003FFU
-#define UART_TX_IDLE_NUM_S  10
-
-/** UART_RS485_CONF_SYNC_REG register
- *  RS485 mode configuration
- */
-#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
-/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to choose the rs485 mode.
- */
-#define UART_RS485_EN    (BIT(0))
-#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
-#define UART_RS485_EN_V  0x00000001U
-#define UART_RS485_EN_S  0
-/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL0_EN    (BIT(1))
-#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
-#define UART_DL0_EN_V  0x00000001U
-#define UART_DL0_EN_S  1
-/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL1_EN    (BIT(2))
-#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
-#define UART_DL1_EN_V  0x00000001U
-#define UART_DL1_EN_S  2
-/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable receiver could receive data when the transmitter is
- *  transmitting data in rs485 mode.
- */
-#define UART_RS485TX_RX_EN    (BIT(3))
-#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
-#define UART_RS485TX_RX_EN_V  0x00000001U
-#define UART_RS485TX_RX_EN_S  3
-/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
- *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
- */
-#define UART_RS485RXBY_TX_EN    (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
-#define UART_RS485RXBY_TX_EN_V  0x00000001U
-#define UART_RS485RXBY_TX_EN_S  4
-/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
- *  This register is used to delay the receiver's internal data signal.
- */
-#define UART_RS485_RX_DLY_NUM    (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
-#define UART_RS485_RX_DLY_NUM_V  0x00000001U
-#define UART_RS485_RX_DLY_NUM_S  5
-/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
- *  This register is used to delay the transmitter's internal data signal.
- */
-#define UART_RS485_TX_DLY_NUM    0x0000000FU
-#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
-#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
-#define UART_RS485_TX_DLY_NUM_S  6
-
-/** UART_AT_CMD_PRECNT_SYNC_REG register
- *  Pre-sequence timing configuration
- */
-#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
-/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the idle duration time before the first at_cmd
- *  is received by receiver.
- */
-#define UART_PRE_IDLE_NUM    0x0000FFFFU
-#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
-#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
-#define UART_PRE_IDLE_NUM_S  0
-
-/** UART_AT_CMD_POSTCNT_SYNC_REG register
- *  Post-sequence timing configuration
- */
-#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
-/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the duration time between the last at_cmd and
- *  the next data.
- */
-#define UART_POST_IDLE_NUM    0x0000FFFFU
-#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
-#define UART_POST_IDLE_NUM_V  0x0000FFFFU
-#define UART_POST_IDLE_NUM_S  0
-
-/** UART_AT_CMD_GAPTOUT_SYNC_REG register
- *  Timeout configuration
- */
-#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
-/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
- *  This register is used to configure the duration time between the at_cmd chars.
- */
-#define UART_RX_GAP_TOUT    0x0000FFFFU
-#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
-#define UART_RX_GAP_TOUT_V  0x0000FFFFU
-#define UART_RX_GAP_TOUT_S  0
-
-/** UART_AT_CMD_CHAR_SYNC_REG register
- *  AT escape sequence detection configuration
- */
-#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
-/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
- *  This register is used to configure the content of at_cmd char.
- */
-#define UART_AT_CMD_CHAR    0x000000FFU
-#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
-#define UART_AT_CMD_CHAR_V  0x000000FFU
-#define UART_AT_CMD_CHAR_S  0
-/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
- *  This register is used to configure the num of continuous at_cmd chars received by
- *  receiver.
- */
-#define UART_CHAR_NUM    0x000000FFU
-#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
-#define UART_CHAR_NUM_V  0x000000FFU
-#define UART_CHAR_NUM_S  8
-
-/** UART_MEM_CONF_REG register
- *  UART memory power configuration
- */
-#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
-/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
- *  Set this bit to force power down UART memory.
- */
-#define UART_MEM_FORCE_PD    (BIT(25))
-#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
-#define UART_MEM_FORCE_PD_V  0x00000001U
-#define UART_MEM_FORCE_PD_S  25
-/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
- *  Set this bit to force power up UART memory.
- */
-#define UART_MEM_FORCE_PU    (BIT(26))
-#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
-#define UART_MEM_FORCE_PU_V  0x00000001U
-#define UART_MEM_FORCE_PU_S  26
-
-/** UART_TOUT_CONF_SYNC_REG register
- *  UART threshold and allocation configuration
- */
-#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
-/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
- */
-#define UART_RX_TOUT_EN    (BIT(0))
-#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
-#define UART_RX_TOUT_EN_V  0x00000001U
-#define UART_RX_TOUT_EN_S  0
-/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
- *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
- */
-#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
-#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
-#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
-#define UART_RX_TOUT_FLOW_DIS_S  1
-/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
- *  This register is used to configure the threshold time that receiver takes to
- *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
- *  takes more time to receive one byte with rx_tout_en set to 1.
- */
-#define UART_RX_TOUT_THRHD    0x000003FFU
-#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
-#define UART_RX_TOUT_THRHD_V  0x000003FFU
-#define UART_RX_TOUT_THRHD_S  2
-
-/** UART_MEM_TX_STATUS_REG register
- *  Tx-SRAM write and read offset address.
- */
-#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
-/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
- *  This register stores the offset write address in Tx-SRAM.
- */
-#define UART_TX_SRAM_WADDR    0x000000FFU
-#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
-#define UART_TX_SRAM_WADDR_V  0x000000FFU
-#define UART_TX_SRAM_WADDR_S  0
-/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
- *  This register stores the offset read address in Tx-SRAM.
- */
-#define UART_TX_SRAM_RADDR    0x000000FFU
-#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
-#define UART_TX_SRAM_RADDR_V  0x000000FFU
-#define UART_TX_SRAM_RADDR_S  9
-
-/** UART_MEM_RX_STATUS_REG register
- *  Rx-SRAM write and read offset address.
- */
-#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
-/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
- *  This register stores the offset read address in RX-SRAM.
- */
-#define UART_RX_SRAM_RADDR    0x000000FFU
-#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
-#define UART_RX_SRAM_RADDR_V  0x000000FFU
-#define UART_RX_SRAM_RADDR_S  0
-/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
- *  This register stores the offset write address in Rx-SRAM.
- */
-#define UART_RX_SRAM_WADDR    0x000000FFU
-#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
-#define UART_RX_SRAM_WADDR_V  0x000000FFU
-#define UART_RX_SRAM_WADDR_S  9
-
-/** UART_FSM_STATUS_REG register
- *  UART transmit and receive status.
- */
-#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
-/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
- *  This is the status register of receiver.
- */
-#define UART_ST_URX_OUT    0x0000000FU
-#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
-#define UART_ST_URX_OUT_V  0x0000000FU
-#define UART_ST_URX_OUT_S  0
-/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
- *  This is the status register of transmitter.
- */
-#define UART_ST_UTX_OUT    0x0000000FU
-#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
-#define UART_ST_UTX_OUT_V  0x0000000FU
-#define UART_ST_UTX_OUT_S  4
-
-/** UART_POSPULSE_REG register
- *  Autobaud high pulse register
- */
-#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
-/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two positive edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_POSEDGE_MIN_CNT    0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
-#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_S  0
-
-/** UART_NEGPULSE_REG register
- *  Autobaud low pulse register
- */
-#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
-/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two negative edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
-#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_S  0
-
-/** UART_LOWPULSE_REG register
- *  Autobaud minimum low pulse duration register
- */
-#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
-/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the value of the minimum duration time of the low level pulse.
- *  It is used in baud rate-detect process.
- */
-#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
-#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_S  0
-
-/** UART_HIGHPULSE_REG register
- *  Autobaud minimum high pulse duration register
- */
-#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
-/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores  the value of the maxinum duration time for the high level
- *  pulse. It is used in baud rate-detect process.
- */
-#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
-#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_S  0
-
-/** UART_RXD_CNT_REG register
- *  Autobaud edge change count register
- */
-#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
-/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
- *  This register stores the count of rxd edge change. It is used in baud rate-detect
- *  process.
- */
-#define UART_RXD_EDGE_CNT    0x000003FFU
-#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
-#define UART_RXD_EDGE_CNT_V  0x000003FFU
-#define UART_RXD_EDGE_CNT_S  0
-
-/** UART_DATE_REG register
- *  UART Version register
- */
-#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
-/** UART_DATE : R/W; bitpos: [31:0]; default: 35656288;
- *  This is the version register.
- */
-#define UART_DATE    0xFFFFFFFFU
-#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
-#define UART_DATE_V  0xFFFFFFFFU
-#define UART_DATE_S  0
-
-/** UART_AFIFO_STATUS_REG register
- *  UART AFIFO Status
- */
-#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
-/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
- *  Full signal of APB TX AFIFO.
- */
-#define UART_TX_AFIFO_FULL    (BIT(0))
-#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
-#define UART_TX_AFIFO_FULL_V  0x00000001U
-#define UART_TX_AFIFO_FULL_S  0
-/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
- *  Empty signal of APB TX AFIFO.
- */
-#define UART_TX_AFIFO_EMPTY    (BIT(1))
-#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
-#define UART_TX_AFIFO_EMPTY_V  0x00000001U
-#define UART_TX_AFIFO_EMPTY_S  1
-/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
- *  Full signal of APB RX AFIFO.
- */
-#define UART_RX_AFIFO_FULL    (BIT(2))
-#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
-#define UART_RX_AFIFO_FULL_V  0x00000001U
-#define UART_RX_AFIFO_FULL_S  2
-/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
- *  Empty signal of APB RX AFIFO.
- */
-#define UART_RX_AFIFO_EMPTY    (BIT(3))
-#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
-#define UART_RX_AFIFO_EMPTY_V  0x00000001U
-#define UART_RX_AFIFO_EMPTY_S  3
-
-/** UART_REG_UPDATE_REG register
- *  UART Registers Configuration Update register
- */
-#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
-/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
- *  Software write 1 would synchronize registers into UART Core clock domain and would
- *  be cleared by hardware after synchronization is done.
- */
-#define UART_REG_UPDATE    (BIT(0))
-#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
-#define UART_REG_UPDATE_V  0x00000001U
-#define UART_REG_UPDATE_S  0
-
-/** UART_ID_REG register
- *  UART ID register
- */
-#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
-/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
- *  This register is used to configure the uart_id.
- */
-#define UART_ID    0xFFFFFFFFU
-#define UART_ID_M  (UART_ID_V << UART_ID_S)
-#define UART_ID_V  0xFFFFFFFFU
-#define UART_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/uart_struct.h b/components/soc/esp32c6/include/soc/uart_struct.h
deleted file mode 100644
index 674af37135c..00000000000
--- a/components/soc/esp32c6/include/soc/uart_struct.h
+++ /dev/null
@@ -1,1294 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
-         *  UART $n accesses FIFO via this register.
-         */
-        uint32_t rxfifo_rd_byte:32;
-    };
-    uint32_t val;
-} uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  This register is used to configure the threshold time that receiver takes to
-         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
-         *  takes more time to receive one byte with rx_tout_en set to 1.
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  what rxfifo_full_thrhd specifies.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1;
-         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-         *  less than what txfifo_empty_thrhd specifies .
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error in
-         *  the data.
-         */
-        uint32_t parity_err:1;
-        /** frm_err : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  .
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  the FIFO can store.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  DSRn signal.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  CTSn signal.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
-         *  bit.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver takes more time than
-         *  rx_tout_thrhd to receive a byte.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det : R/WTC/SS; bitpos: [11]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
-         *  middle of a start bit.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter completes  sending
-         *  NULL characters after all data in Tx-FIFO are sent.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
-         *  duration after sending the  last data.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done : R/WTC/SS; bitpos: [14]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has send out all data
-         *  in FIFO.
-         */
-        uint32_t tx_done:1;
-        /** rs485_parity_err : R/WTC/SS; bitpos: [15]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_parity_err:1;
-        /** rs485_frm_err : R/WTC/SS; bitpos: [16]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_frm_err:1;
-        /** rs485_clash : R/WTC/SS; bitpos: [17]; default: 0;
-         *  This interrupt raw bit turns to high level when detects a clash between transmitter
-         *  and receiver in rs485 mode.
-         */
-        uint32_t rs485_clash:1;
-        /** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the configured
-         *  at_cmd char.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup : R/WTC/SS; bitpos: [19]; default: 0;
-         *  This interrupt raw bit turns to high level when input rxd edge changes more times
-         *  than what reg_active_threshold specifies in light sleeping mode.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full : RO; bitpos: [0]; default: 0;
-         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty : RO; bitpos: [1]; default: 0;
-         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
-         *  to 1.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err : RO; bitpos: [2]; default: 0;
-         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-         */
-        uint32_t parity_err:1;
-        /** frm_err : RO; bitpos: [3]; default: 0;
-         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf : RO; bitpos: [4]; default: 0;
-         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg : RO; bitpos: [5]; default: 0;
-         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg : RO; bitpos: [6]; default: 0;
-         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det : RO; bitpos: [7]; default: 0;
-         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout : RO; bitpos: [8]; default: 0;
-         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon : RO; bitpos: [9]; default: 0;
-         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff : RO; bitpos: [10]; default: 0;
-         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det : RO; bitpos: [11]; default: 0;
-         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done : RO; bitpos: [12]; default: 0;
-         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
-         *  is set to 1.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done : RO; bitpos: [14]; default: 0;
-         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-         */
-        uint32_t tx_done:1;
-        /** rs485_parity_err : RO; bitpos: [15]; default: 0;
-         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-         *  set to 1.
-         */
-        uint32_t rs485_parity_err:1;
-        /** rs485_frm_err : RO; bitpos: [16]; default: 0;
-         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
-         *  to 1.
-         */
-        uint32_t rs485_frm_err:1;
-        /** rs485_clash : RO; bitpos: [17]; default: 0;
-         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
-         */
-        uint32_t rs485_clash:1;
-        /** at_cmd_char_det : RO; bitpos: [18]; default: 0;
-         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
-         *  to 1.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup : RO; bitpos: [19]; default: 0;
-         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full: R/W; bitpos: [0]; default: 0;
-         *  This is the enable bit for rxfifo_full_int_st register.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty: R/W; bitpos: [1]; default: 0;
-         *  This is the enable bit for txfifo_empty_int_st register.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err: R/W; bitpos: [2]; default: 0;
-         *  This is the enable bit for parity_err_int_st register.
-         */
-        uint32_t parity_err:1;
-        /** frm_err: R/W; bitpos: [3]; default: 0;
-         *  This is the enable bit for frm_err_int_st register.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf: R/W; bitpos: [4]; default: 0;
-         *  This is the enable bit for rxfifo_ovf_int_st register.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg: R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for dsr_chg_int_st register.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg: R/W; bitpos: [6]; default: 0;
-         *  This is the enable bit for cts_chg_int_st register.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det: R/W; bitpos: [7]; default: 0;
-         *  This is the enable bit for brk_det_int_st register.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout: R/W; bitpos: [8]; default: 0;
-         *  This is the enable bit for rxfifo_tout_int_st register.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon: R/W; bitpos: [9]; default: 0;
-         *  This is the enable bit for sw_xon_int_st register.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff: R/W; bitpos: [10]; default: 0;
-         *  This is the enable bit for sw_xoff_int_st register.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det: R/W; bitpos: [11]; default: 0;
-         *  This is the enable bit for glitch_det_int_st register.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done: R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for tx_brk_done_int_st register.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done: R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit for tx_brk_idle_done_int_st register.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done: R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for tx_done_int_st register.
-         */
-        uint32_t tx_done:1;
-        /** rs485_parity_err: R/W; bitpos: [15]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_parity_err:1;
-        /** rs485_frm_err: R/W; bitpos: [16]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_frm_err:1;
-        /** rs485_clash: R/W; bitpos: [17]; default: 0;
-         *  This is the enable bit for rs485_clash_int_st register.
-         */
-        uint32_t rs485_clash:1;
-        /** at_cmd_char_det: R/W; bitpos: [18]; default: 0;
-         *  This is the enable bit for at_cmd_char_det_int_st register.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup: R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for uart_wakeup_int_st register.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full: WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty: WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear txfifo_empty_int_raw interrupt.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err: WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear parity_err_int_raw interrupt.
-         */
-        uint32_t parity_err:1;
-        /** frm_err: WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear frm_err_int_raw interrupt.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf: WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg: WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the dsr_chg_int_raw interrupt.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg: WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the cts_chg_int_raw interrupt.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det: WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the brk_det_int_raw interrupt.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout: WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon: WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the sw_xon_int_raw interrupt.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff: WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the sw_xoff_int_raw interrupt.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det: WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the glitch_det_int_raw interrupt.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done: WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done: WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done: WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the tx_done_int_raw interrupt.
-         */
-        uint32_t tx_done:1;
-        /** rs485_parity_err: WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
-         */
-        uint32_t rs485_parity_err:1;
-        /** rs485_frm_err: WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
-         */
-        uint32_t rs485_frm_err:1;
-        /** rs485_clash: WT; bitpos: [17]; default: 0;
-         *  Set this bit to clear the rs485_clash_int_raw interrupt.
-         */
-        uint32_t rs485_clash:1;
-        /** at_cmd_char_det: WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup: WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t clkdiv_int:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  The decimal part of the frequency divider factor.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  Rx Filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  when input pulse width is lower than this value the pulse is ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable Rx signal filter.
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  a
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  This register is used to configure the parity check mode.
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable uart parity check.
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  This register is used to set the length of data.
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  This register is used to set the length of  stop bit.
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
-         *  is done.
-         */
-        uint32_t txd_brk:1;
-        /** irda_dplx : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to enable IrDA loopback mode.
-         */
-        uint32_t irda_dplx:1;
-        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
-         *  This is the start enable bit for IrDA transmitter.
-         */
-        uint32_t irda_tx_en:1;
-        /** irda_wctl : R/W; bitpos: [9]; default: 0;
-         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-         *  transmitter's 11th bit to 0.
-         */
-        uint32_t irda_wctl:1;
-        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to invert the level of  IrDA transmitter.
-         */
-        uint32_t irda_tx_inv:1;
-        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
-         *  Set this bit to invert the level of IrDA receiver.
-         */
-        uint32_t irda_rx_inv:1;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable uart loopback test mode.
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to enable flow control function for transmitter.
-         */
-        uint32_t tx_flow_en:1;
-        /** irda_en : R/W; bitpos: [14]; default: 0;
-         *  Set this bit to enable IrDA protocol.
-         */
-        uint32_t irda_en:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Set this bit to inverse the level value of uart rxd signal.
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart txd signal.
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Disable UART Rx data overflow detect.
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-         *  stores the data even if the  received data is wrong.
-         */
-        uint32_t err_wr_mask:1;
-        /** autobaud_en : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for detecting baudrate.
-         */
-        uint32_t autobaud_en:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 1;
-         *  UART memory clock gate enable signal.
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  This register is used to configure the software rts signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Set this bit to reset the uart receive-FIFO.
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Set this bit to reset the uart transmit-FIFO.
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
-         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
-         *  this register value.
-         */
-        uint32_t rxfifo_full_thrhd:8;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
-         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
-         *  than this register value.
-         */
-        uint32_t txfifo_empty_thrhd:8;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart cts signal.
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to inverse the level value of uart dsr signal.
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to inverse the level value of uart rts signal.
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to inverse the level value of uart dtr signal.
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  This register is used to configure the software dtr signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow-control configuration
- */
-typedef union {
-    struct {
-        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
-         *  This register is used to configure the maximum amount of data that can be received
-         *  when hardware flow control works.
-         */
-        uint32_t rx_flow_thrhd:8;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  This is the flow enable bit for UART receiver.
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configure register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified wake up char1 to wake up
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  This register restores the specified wake up char2 to wake up
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  This register restores the specified wake up char3 to wake up
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  This register restores the specified wake up char4 to wake up
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configure register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified char0 to wake up
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configure register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  The uart is activated from light sleeping mode when the input rxd edge changes more
-         *  times than this register value.
-         */
-        uint32_t active_threshold:10;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
-         *  In wake up mode 1 this field is used to set the received data number threshold to
-         *  wake up chip.
-         */
-        uint32_t rx_wake_up_thrhd:8;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  This register is used to select number of wake up char.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  This register is used to mask  wake up char.
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
-         *  received data number larger than
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  This register stores the Xon flow control char.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  This register stores the Xoff flow control char.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
-         *  this status, UART Tx can not transmit XOFF even the received data number is larger
-         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
-         *  UART Tx is disabled.
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to enable software flow control. It is used with register sw_xon or
-         *  sw_xoff.
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to remove flow control char from the received data.
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to enable the transmitter to go on sending data.
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Set this bit to stop the  transmitter from sending data.
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Set this bit to send Xon char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
-         *  When the data amount in Rx-FIFO is less than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
-         */
-        uint32_t xon_threshold:8;
-        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
-         *  When the data amount in Rx-FIFO is more than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
-         */
-        uint32_t xoff_threshold:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  Tx Break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  This register is used to configure the number of 0 to be sent after the process of
-         *  sending data is done. It is active when txd_brk is set to 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame-end idle configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  It will produce frame end signal when receiver takes more time to receive one byte
-         *  data than this register value.
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  This register is used to configure the duration time between transfers.
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        /** rs485_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to choose the rs485 mode.
-         */
-        uint32_t rs485_en:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl1_en:1;
-        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable receiver could receive data when the transmitter is
-         *  transmitting data in rs485 mode.
-         */
-        uint32_t rs485tx_rx_en:1;
-        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
-         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-         */
-        uint32_t rs485rxby_tx_en:1;
-        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
-         *  This register is used to delay the receiver's internal data signal.
-         */
-        uint32_t rs485_rx_dly_num:1;
-        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
-         *  This register is used to delay the transmitter's internal data signal.
-         */
-        uint32_t rs485_tx_dly_num:4;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rs485_conf_sync_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor.
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor.
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t sclk_div_num:8;
-        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
-         */
-        uint32_t sclk_sel:2;
-        /** sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set this bit to enable UART Tx/Rx clock.
-         */
-        uint32_t sclk_en:1;
-        /** rst_core : R/W; bitpos: [23]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
-         */
-        uint32_t rst_core:1;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Set this bit to enable UART Tx clock.
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Set this bit to enable UART Rx clock.
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Rx.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
-         *  Stores the byte number of valid data in Rx-FIFO.
-         */
-        uint32_t rxfifo_cnt:8;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  The register represent the level value of the internal uart dsr signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  This register represent the level value of the internal uart cts signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  This register represent the  level value of the internal uart rxd signal.
-         */
-        uint32_t rxd:1;
-        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
-         *  Stores the byte number of data in Tx-FIFO.
-         */
-        uint32_t txfifo_cnt:8;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  This bit represents the level of the internal uart dtr signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  This bit represents the level of the internal uart rts signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  This bit represents the  level of the internal uart txd signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  Tx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
-         *  This register stores the offset write address in Tx-SRAM.
-         */
-        uint32_t tx_sram_waddr:8;
-        uint32_t reserved_8:1;
-        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
-         *  This register stores the offset read address in Tx-SRAM.
-         */
-        uint32_t tx_sram_raddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
-         *  This register stores the offset read address in RX-SRAM.
-         */
-        uint32_t rx_sram_raddr:8;
-        uint32_t reserved_8:1;
-        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
-         *  This register stores the offset write address in Rx-SRAM.
-         */
-        uint32_t rx_sram_waddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status.
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  This is the status register of receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  This is the status register of transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART AFIFO Status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Full signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Empty signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Full signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Empty signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the idle duration time before the first at_cmd
-         *  is received by receiver.
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the duration time between the last at_cmd and
-         *  the next data.
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  This register is used to configure the duration time between the at_cmd chars.
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** data : R/W; bitpos: [7:0]; default: 43;
-         *  This register is used to configure the content of at_cmd char.
-         */
-        uint32_t data:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  This register is used to configure the num of continuous at_cmd chars received by
-         *  receiver.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Autobaud Register */
-/** Type of pospulse register
- *  Autobaud high pulse register
- */
-typedef union {
-    struct {
-        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two positive edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t posedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_pospulse_reg_t;
-
-/** Type of negpulse register
- *  Autobaud low pulse register
- */
-typedef union {
-    struct {
-        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two negative edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t negedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_negpulse_reg_t;
-
-/** Type of lowpulse register
- *  Autobaud minimum low pulse duration register
- */
-typedef union {
-    struct {
-        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the value of the minimum duration time of the low level pulse.
-         *  It is used in baud rate-detect process.
-         */
-        uint32_t lowpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_lowpulse_reg_t;
-
-/** Type of highpulse register
- *  Autobaud minimum high pulse duration register
- */
-typedef union {
-    struct {
-        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores  the value of the maxinum duration time for the high level
-         *  pulse. It is used in baud rate-detect process.
-         */
-        uint32_t highpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_highpulse_reg_t;
-
-/** Type of rxd_cnt register
- *  Autobaud edge change count register
- */
-typedef union {
-    struct {
-        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
-         *  This register stores the count of rxd edge change. It is used in baud rate-detect
-         *  process.
-         */
-        uint32_t rxd_edge_cnt:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rxd_cnt_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35656288;
-         *  This is the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART Registers Configuration Update register
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Software write 1 would synchronize registers into UART Core clock domain and would
-         *  be cleared by hardware after synchronization is done.
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  This register is used to configure the uart_id.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} uart_id_reg_t;
-
-
-typedef struct uart_dev_s {
-    volatile uart_fifo_reg_t fifo;
-    volatile uart_int_raw_reg_t int_raw;
-    volatile uart_int_st_reg_t int_st;
-    volatile uart_int_ena_reg_t int_ena;
-    volatile uart_int_clr_reg_t int_clr;
-    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile uart_rx_filt_reg_t rx_filt;
-    volatile uart_status_reg_t status;
-    volatile uart_conf0_sync_reg_t conf0_sync;
-    volatile uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile uart_sleep_conf0_reg_t sleep_conf0;
-    volatile uart_sleep_conf1_reg_t sleep_conf1;
-    volatile uart_sleep_conf2_reg_t sleep_conf2;
-    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile uart_swfc_conf1_reg_t swfc_conf1;
-    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile uart_mem_conf_reg_t mem_conf;
-    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile uart_mem_tx_status_reg_t mem_tx_status;
-    volatile uart_mem_rx_status_reg_t mem_rx_status;
-    volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;      /* LP_UART instance has this register reserved */
-    volatile uart_negpulse_reg_t negpulse;      /* LP_UART instance has this register reserved */
-    volatile uart_lowpulse_reg_t lowpulse;      /* LP_UART instance has this register reserved */
-    volatile uart_highpulse_reg_t highpulse;    /* LP_UART instance has this register reserved */
-    volatile uart_rxd_cnt_reg_t rxd_cnt;        /* LP_UART instance has this register reserved */
-    volatile uart_clk_conf_reg_t clk_conf;      /* UART0/1 instance have this register reserved, configure in corresponding PCR registers */
-    volatile uart_date_reg_t date;
-    volatile uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile uart_reg_update_reg_t reg_update;
-    volatile uart_id_reg_t id;
-} uart_dev_t;
-
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-extern uart_dev_t LP_UART;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h
deleted file mode 100644
index eb4b8a1e039..00000000000
--- a/components/soc/esp32c6/include/soc/usb_serial_jtag_reg.h
+++ /dev/null
@@ -1,1188 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** USB_SERIAL_JTAG_EP1_REG register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
- *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
- *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
- *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
- *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
- *  how many data is received, then read data from UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
- *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
- */
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
-#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
- *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
- *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
- *  USB Host.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
- *  1'b1: Indicate there is data in UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- *  Interrupt raw status register.
- */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when flush cmd is received for IN
- *  endpoint 2 of JTAG.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when SOF frame is received.
- */
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- *  one packet.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
- *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when pid error is detected.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt bit turns to high level when CRC5 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt bit turns to high level when CRC16 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt bit turns to high level when stuff error is detected.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
- *  received.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt bit turns to high level when usb bus reset is detected.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
-
-/** USB_SERIAL_JTAG_INT_ST_REG register
- *  Interrupt status register.
- */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
-
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- *  Interrupt enable status register.
- */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
-
-/** USB_SERIAL_JTAG_INT_CLR_REG register
- *  Interrupt clear status register.
- */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
-
-/** USB_SERIAL_JTAG_CONF0_REG register
- *  PHY hardware configuration.
- */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  Select internal/external PHY
- */
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
- *  Enable software control USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
- *  USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
- *  Control single-end input high threshold,1.76V to 2V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFH    0x00000003U
-#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
-#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFH_S  3
-/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
- *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFL    0x00000003U
-#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
-#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFL_S  5
-/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
- *  Enable software control input  threshold
- */
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
- *  Enable software control USB D+ D- pullup pulldown
- */
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
- *  Control USB D+ pull up.
- */
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
- *  Control USB D+ pull down.
- */
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
- *  Control USB D- pull up.
- */
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
- *  Control USB D- pull down.
- */
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
- *  Control pull up value.
- */
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
- *  Enable USB pad function.
- */
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
- *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
- *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
- *  through GPIO Matrix.
- */
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
-
-/** USB_SERIAL_JTAG_TEST_REG register
- *  Registers used for debugging the PHY.
- */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
-/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Enable test of the USB pad
- */
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad oen in test
- */
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- *  USB D+ tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- *  USB D- tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
- *  USB RCV value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
-#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
-/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
- *  USB D+ rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
-#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
-/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
- *  USB D- rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
-#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
-
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- *  JTAG FIFO status and control registers.
- */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
- *  JTAT in fifo counter.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- *  1: JTAG in fifo is empty.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
- *  1: JTAG in fifo is full.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
- *  JTAT out fifo counter.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
- *  1: JTAG out fifo is empty.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
- *  1: JTAG out fifo is full.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
- *  Write 1 to reset JTAG in fifo.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
- *  Write 1 to reset JTAG out fifo.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- *  Last received SOF frame index register.
- */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
- *  Frame index of received SOF frame.
- */
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- *  Control IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- *  CDC-ACM IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
-/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- *  JTAG IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- *  Control OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- *  CDC-ACM OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
-/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
- *  Data count in OUT endpoint 1 when one packet is received.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- *  JTAG OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- *  Clock enable control
- */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
-#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- *  Memory power control
- */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  1: power down usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  1: Force clock on for usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-
-/** USB_SERIAL_JTAG_CHIP_RST_REG register
- *  CDC-ACM chip reset control.
- */
-#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
-/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
- *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_RTS    (BIT(0))
-#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
-#define USB_SERIAL_JTAG_RTS_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_S  0
-/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
- *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_DTR    (BIT(1))
-#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
-#define USB_SERIAL_JTAG_DTR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_S  1
-/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
- *  Set this bit to disable chip reset from usb serial channel to reset chip.
- */
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
- *  W0 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
-/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
- *  W1 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
-/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
-/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_S  16
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
- *  W0 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
-/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
- *  W1 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
-/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
-/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
-
-/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
- *  Configuration registers' value update
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
-/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
- *  Write 1 to this register would update the value of configure registers from APB
- *  clock domain to 48MHz clock domain.
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
-
-/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
- *  Serial AFIFO configure register
- */
-#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
- *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
-
-/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
- *  USB Bus reset status register
- */
-#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
-/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
- *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
- *  reset is released.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
-
-/** USB_SERIAL_JTAG_DATE_REG register
- *  Date register
- */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416;
- *  register version.
- */
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/include/soc/xts_aes_reg.h b/components/soc/esp32c6/include/soc/xts_aes_reg.h
deleted file mode 100644
index 5d7d7e0b818..00000000000
--- a/components/soc/esp32c6/include/soc/xts_aes_reg.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define XTS_AES_PLAIN_MEM(i)          (REG_SPI_MEM_BASE(i) + 0x300)
-/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This field is only used to generate include file in c case. This field is useles
-s. Please do not use this field..*/
-#define XTS_AES_PLAIN    0xFFFFFFFF
-#define XTS_AES_PLAIN_M  ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
-#define XTS_AES_PLAIN_V  0xFFFFFFFF
-#define XTS_AES_PLAIN_S  0
-
-#define XTS_AES_LINESIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x340)
-/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the line-size parameter which will be used in manual encryption
- calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
- 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
-#define XTS_AES_LINESIZE    0x00000003
-#define XTS_AES_LINESIZE_M  ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
-#define XTS_AES_LINESIZE_V  0x3
-#define XTS_AES_LINESIZE_S  0
-
-#define XTS_AES_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
-/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit stores the destination parameter which will be used in manual encryptio
-n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
-used..*/
-#define XTS_AES_DESTINATION    (BIT(0))
-#define XTS_AES_DESTINATION_M  (BIT(0))
-#define XTS_AES_DESTINATION_V  0x1
-#define XTS_AES_DESTINATION_S  0
-
-#define XTS_AES_PHYSICAL_ADDRESS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x348)
-/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits stores the physical-address parameter which will be used in manual enc
-ryption calculation. This value should aligned with byte number decided by line-
-size parameter..*/
-#define XTS_AES_PHYSICAL_ADDRESS    0x03FFFFFF
-#define XTS_AES_PHYSICAL_ADDRESS_M  ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
-#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFF
-#define XTS_AES_PHYSICAL_ADDRESS_S  0
-
-#define XTS_AES_TRIGGER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34C)
-/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to trigger the process of manual encryption calculation. This actio
-n should only be asserted when manual encryption status is 0. After this action,
- manual encryption status becomes 1. After calculation is done, manual encryptio
-n status becomes 2..*/
-#define XTS_AES_TRIGGER    (BIT(0))
-#define XTS_AES_TRIGGER_M  (BIT(0))
-#define XTS_AES_TRIGGER_V  0x1
-#define XTS_AES_TRIGGER_S  0
-
-#define XTS_AES_RELEASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x350)
-/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to release encrypted result to mspi. This action should only be ass
-erted when manual encryption status is 2. After this action, manual encryption s
-tatus will become 3..*/
-#define XTS_AES_RELEASE    (BIT(0))
-#define XTS_AES_RELEASE_M  (BIT(0))
-#define XTS_AES_RELEASE_V  0x1
-#define XTS_AES_RELEASE_S  0
-
-#define XTS_AES_DESTROY_REG(i)          (REG_SPI_MEM_BASE(i) + 0x354)
-/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
-en manual encryption status is 3. After this action, manual encryption status wi
-ll become 0..*/
-#define XTS_AES_DESTROY    (BIT(0))
-#define XTS_AES_DESTROY_M  (BIT(0))
-#define XTS_AES_DESTROY_V  0x1
-#define XTS_AES_DESTROY_S  0
-
-#define XTS_AES_STATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x358)
-/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
- calculation, 2: encryption calculation is done but the encrypted result is invi
-sible to mspi, 3: the encrypted result is visible to mspi..*/
-#define XTS_AES_STATE    0x00000003
-#define XTS_AES_STATE_M  ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
-#define XTS_AES_STATE_V  0x3
-#define XTS_AES_STATE_S  0
-
-#define XTS_AES_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x35C)
-/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
-/*description: This bits stores the last modified-time of manual encryption feature..*/
-#define XTS_AES_DATE    0x3FFFFFFF
-#define XTS_AES_DATE_M  ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
-#define XTS_AES_DATE_V  0x3FFFFFFF
-
-#define XTS_AES_DPA_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x388)
-/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
-T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V  0x1
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S  4
-/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
-ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
-ing key 1..*/
-#define XTS_AES_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_V  0x1
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_S  3
-/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
-7: The bigger the number is, the more secure the cryption is. (Note that the per
-formance of cryption will decrease together with this number increasing).*/
-#define XTS_AES_CRYPT_SECURITY_LEVEL    0x00000007
-#define XTS_AES_CRYPT_SECURITY_LEVEL_M  ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
-#define XTS_AES_CRYPT_SECURITY_LEVEL_V  0x7
-#define XTS_AES_CRYPT_SECURITY_LEVEL_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c6/interrupts.c b/components/soc/esp32c6/interrupts.c
index 075a674041e..c3a8e0eef9a 100644
--- a/components/soc/esp32c6/interrupts.c
+++ b/components/soc/esp32c6/interrupts.c
@@ -48,7 +48,7 @@ const char *const esp_isr_names[] = {
     [38] = "HP_APM_M3",
     [39] = "LP_APM0",
     [40] = "MSPI",
-    [41] = "I2S1",
+    [41] = "I2S0",
     [42] = "UHCI0",
     [43] = "UART0",
     [44] = "UART1",
diff --git a/components/soc/esp32c6/ledc_periph.c b/components/soc/esp32c6/ledc_periph.c
index b150f9bc991..e20f002e5a3 100644
--- a/components/soc/esp32c6/ledc_periph.c
+++ b/components/soc/esp32c6/ledc_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,3 +15,141 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
 	}
 };
+
+/**
+ * LEDC registers to be saved for sleep retention
+ *
+ * channel:
+ * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
+ *
+ * timer:
+ * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
+ *
+ * common:
+ * LEDC_INT_ENA_REG,
+ * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
+ * LEDC_CONF_REG,
+ *
+ * Note 1: Gamma feature is hard to do hardware retention, will consider to use software to do the backup and restore.
+ * 		   We won't start a fade automatically after wake-up.
+ *         Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep.
+ *
+ * Note 2: For timer/channel registers to get synced, update bits need to be set
+ *
+ * Note 3: Retention backup/restore does not rely on LEDC function clock enabled
+ */
+#define LEDC_COMMON_RETENTION_REGS_CNT  5
+#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
+static const uint32_t ledc_common_regs_map[4] = {0x1, 0x1c00000, 0x400, 0x0};
+static const regdma_entries_config_t ledc_common_regdma_entries[] = {
+	// If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
+    // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
+			 							    LEDC_INT_ENA_REG, 0,
+			 							    (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1),
+		    .owner = LEDC_RETENTION_ENTRY },
+    [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
+                                               LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
+                                               LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
+                                               ledc_common_regs_map[0], ledc_common_regs_map[1],
+                                               ledc_common_regs_map[2], ledc_common_regs_map[3]),
+            .owner = LEDC_RETENTION_ENTRY },
+};
+
+#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
+	[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
+			 								     LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+			 								     LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
+			 							    LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
+static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
+#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
+	[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
+                                               LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
+                                               LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
+                                               ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
+                                               ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+                                                 LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
+			 							    LEDC_DUTY_START_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
+			 							    LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
+			 							    LEDC_PARA_UP_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
+
+static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
+static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
+static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+	.common = {
+		.regdma_entry_array = ledc_common_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
+	},
+	.timer[0] = {
+		.regdma_entry_array = ledc_timer0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
+	},
+	.timer[1] = {
+		.regdma_entry_array = ledc_timer1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
+	},
+	.timer[2] = {
+		.regdma_entry_array = ledc_timer2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
+	},
+	.timer[3] = {
+		.regdma_entry_array = ledc_timer3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
+	},
+	.channel[0] = {
+		.regdma_entry_array = ledc_channel0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
+	},
+	.channel[1] = {
+		.regdma_entry_array = ledc_channel1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
+	},
+	.channel[2] = {
+		.regdma_entry_array = ledc_channel2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
+	},
+	.channel[3] = {
+		.regdma_entry_array = ledc_channel3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
+	},
+	.channel[4] = {
+		.regdma_entry_array = ledc_channel4_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
+	},
+	.channel[5] = {
+		.regdma_entry_array = ledc_channel5_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
+	},
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};
diff --git a/components/soc/esp32c6/mcpwm_periph.c b/components/soc/esp32c6/mcpwm_periph.c
index 25e1b86cc15..ff6b5f993cc 100644
--- a/components/soc/esp32c6/mcpwm_periph.c
+++ b/components/soc/esp32c6/mcpwm_periph.c
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/soc.h"
 #include "soc/mcpwm_periph.h"
+#include "soc/mcpwm_reg.h"
 #include "soc/gpio_sig_map.h"
 
 const mcpwm_signal_conn_t mcpwm_periph_signals = {
@@ -81,3 +82,46 @@ const mcpwm_signal_conn_t mcpwm_periph_signals = {
         },
     }
 };
+
+/**
+ * MCPWM Registers to be saved during sleep retention
+ * - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
+ * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
+ * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
+ *   |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
+ *   |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
+ *   |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
+ *   └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
+ * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
+ * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
+ * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
+ * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
+*/
+#define MCPWM_RETENTION_REGS_CNT 61
+#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
+static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
+static const regdma_entries_config_t mcpwm_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
+                                               MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
+                                               MCPWM_RETENTION_REGS_CNT, 0, 0,
+                                               mcpwm_regs_map[0], mcpwm_regs_map[1],
+                                               mcpwm_regs_map[2], mcpwm_regs_map[3]),
+                                               .owner = ENTRY(0) | ENTRY(2) },
+    // restore stage: trigger a forced update of all active registers
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
+                                                MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
+                                                .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
+                                                MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = mcpwm_regs_retention,
+        .array_size = ARRAY_SIZE(mcpwm_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_MCPWM0
+    },
+};
diff --git a/components/soc/esp32c6/parlio_periph.c b/components/soc/esp32c6/parlio_periph.c
index 40ac06320c2..f060ee1a9ed 100644
--- a/components/soc/esp32c6/parlio_periph.c
+++ b/components/soc/esp32c6/parlio_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -64,3 +64,29 @@ const parlio_signal_conn_t parlio_periph_signals = {
         },
     },
 };
+
+/**
+ * PARLIO Registers to be saved during sleep retention
+ * - Configuration registers, e.g.: PARL_IO_RX_CFG0_REG, PARL_IO_RX_CFG1_REG, PARL_IO_TX_CFG0_REG, PARL_IO_TX_CFG1_REG, PARL_IO_CLK_REG
+ * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG
+*/
+#define PARLIO_RETENTION_REGS_CNT 6
+#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0)
+static const uint32_t parlio_regs_map[4] = {0x2f, 0x0, 0x100, 0x0};
+static const regdma_entries_config_t parlio_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \
+                                               PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \
+                                               PARLIO_RETENTION_REGS_CNT, 0, 0, \
+                                               parlio_regs_map[0], parlio_regs_map[1], \
+                                               parlio_regs_map[2], parlio_regs_map[3]), \
+                                               .owner = ENTRY(0) | ENTRY(2) }, \
+};
+const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = parlio_regs_retention,
+        .array_size = ARRAY_SIZE(parlio_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_PARLIO0
+    },
+};
diff --git a/components/soc/esp32c6/pcnt_periph.c b/components/soc/esp32c6/pcnt_periph.c
index b2b440245b7..14c52fc0d62 100644
--- a/components/soc/esp32c6/pcnt_periph.c
+++ b/components/soc/esp32c6/pcnt_periph.c
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/pcnt_periph.h"
 #include "soc/gpio_sig_map.h"
+#include "soc/pcnt_reg.h"
 
 const pcnt_signal_conn_t pcnt_periph_signals = {
     .groups = {
@@ -64,3 +65,30 @@ const pcnt_signal_conn_t pcnt_periph_signals = {
         }
     }
 };
+
+/**
+ * PCNT Registers to be saved during sleep retention
+ * - Configuration registers, e.g.: PCNT_CTRL_REG, PCNT_U0_CONF0_REG, PCNT_U0_CONF1_REG, PCNT_U0_CONF2_REG, PCNT_U1_CONF0_REG...
+ * - Interrupt enable registers, e.g.: PCNT_INT_ENA_REG
+*/
+#define PCNT_RETENTION_REGS_CNT 14
+#define PCNT_RETENTION_REGS_BASE (DR_REG_PCNT_BASE + 0x0)
+static const uint32_t pcnt_regs_map[4] = {0x1040fff, 0x0, 0x0, 0x0};
+static const regdma_entries_config_t pcnt_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \
+                                               PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \
+                                               PCNT_RETENTION_REGS_CNT, 0, 0, \
+                                               pcnt_regs_map[0], pcnt_regs_map[1], \
+                                               pcnt_regs_map[2], pcnt_regs_map[3]), \
+                                               .owner = ENTRY(0) | ENTRY(2) }, \
+};
+
+const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = pcnt_regs_retention,
+        .array_size = ARRAY_SIZE(pcnt_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_PCNT0
+    },
+};
diff --git a/components/soc/esp32c6/register/soc/.gitkeep b/components/soc/esp32c6/register/soc/.gitkeep
deleted file mode 100644
index e69de29bb2d..00000000000
diff --git a/components/soc/esp32c6/include/soc/aes_reg.h b/components/soc/esp32c6/register/soc/aes_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/aes_reg.h
rename to components/soc/esp32c6/register/soc/aes_reg.h
diff --git a/components/soc/esp32c6/include/soc/aes_struct.h b/components/soc/esp32c6/register/soc/aes_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/aes_struct.h
rename to components/soc/esp32c6/register/soc/aes_struct.h
diff --git a/components/soc/esp32c6/include/soc/apb_saradc_reg.h b/components/soc/esp32c6/register/soc/apb_saradc_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/apb_saradc_reg.h
rename to components/soc/esp32c6/register/soc/apb_saradc_reg.h
diff --git a/components/soc/esp32c6/include/soc/apb_saradc_struct.h b/components/soc/esp32c6/register/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/apb_saradc_struct.h
rename to components/soc/esp32c6/register/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32c6/register/soc/assist_debug_reg.h b/components/soc/esp32c6/register/soc/assist_debug_reg.h
new file mode 100644
index 00000000000..d2b947d9466
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/assist_debug_reg.h
@@ -0,0 +1,777 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
+ *  IBUS busy monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
+ *  DBUS busy monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
+ *  DBUS busy monitor initerrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
+ *  DBUS busy monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
+ *  DBUS busy monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
+ *  core0 area pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  the stackpointer when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
+ *  core0 area sp status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
+/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  the PC when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core0 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core0 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_0
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_1
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CLOCK_GATE_REG register
+ *  clock register
+ */
+#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
+/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 force on the clock gate
+ */
+#define ASSIST_DEBUG_CLK_EN    (BIT(0))
+#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
+#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
+#define ASSIST_DEBUG_CLK_EN_S  0
+
+/** ASSIST_DEBUG_DATE_REG register
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
+/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
+ *  version register
+ */
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/assist_debug_struct.h b/components/soc/esp32c6/register/soc/assist_debug_struct.h
new file mode 100644
index 00000000000..9838880bc8c
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/assist_debug_struct.h
@@ -0,0 +1,717 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: monitor configuration registers */
+/** Type of core_0_intr_ena register
+ *  core0 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor enable
+         */
+        uint32_t core_0_area_dram0_0_rd_ena:1;
+        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor enable
+         */
+        uint32_t core_0_area_dram0_0_wr_ena:1;
+        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor enable
+         */
+        uint32_t core_0_area_dram0_1_rd_ena:1;
+        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor enable
+         */
+        uint32_t core_0_area_dram0_1_wr_ena:1;
+        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor enable
+         */
+        uint32_t core_0_area_pif_0_rd_ena:1;
+        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor enable
+         */
+        uint32_t core_0_area_pif_0_wr_ena:1;
+        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor enable
+         */
+        uint32_t core_0_area_pif_1_rd_ena:1;
+        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor enable
+         */
+        uint32_t core_0_area_pif_1_wr_ena:1;
+        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor enable
+         */
+        uint32_t core_0_sp_spill_min_ena:1;
+        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor enable
+         */
+        uint32_t core_0_sp_spill_max_ena:1;
+        /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
+         *  IBUS busy monitor enable
+         */
+        uint32_t core_0_iram0_exception_monitor_ena:1;
+        /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
+         *  DBUS busy monitor enable
+         */
+        uint32_t core_0_dram0_exception_monitor_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_ena_reg_t;
+
+/** Type of core_0_area_dram0_0_min register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region0 start addr
+         */
+        uint32_t core_0_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_min_reg_t;
+
+/** Type of core_0_area_dram0_0_max register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region0 end addr
+         */
+        uint32_t core_0_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_max_reg_t;
+
+/** Type of core_0_area_dram0_1_min register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region1 start addr
+         */
+        uint32_t core_0_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_min_reg_t;
+
+/** Type of core_0_area_dram0_1_max register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region1 end addr
+         */
+        uint32_t core_0_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_max_reg_t;
+
+/** Type of core_0_area_pif_0_min register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region0 start addr
+         */
+        uint32_t core_0_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_min_reg_t;
+
+/** Type of core_0_area_pif_0_max register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region0 end addr
+         */
+        uint32_t core_0_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_max_reg_t;
+
+/** Type of core_0_area_pif_1_min register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region1 start addr
+         */
+        uint32_t core_0_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_min_reg_t;
+
+/** Type of core_0_area_pif_1_max register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region1 end addr
+         */
+        uint32_t core_0_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_max_reg_t;
+
+/** Type of core_0_area_pc register
+ *  core0 area pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  the stackpointer when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pc_reg_t;
+
+/** Type of core_0_area_sp register
+ *  core0 area sp status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  the PC when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_sp_reg_t;
+
+/** Type of core_0_sp_min register
+ *  stack min value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  core0 sp region configuration register
+         */
+        uint32_t core_0_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_min_reg_t;
+
+/** Type of core_0_sp_max register
+ *  stack max value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  core0 sp pc status register
+         */
+        uint32_t core_0_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_max_reg_t;
+
+/** Type of core_0_sp_pc register
+ *  stack monitor pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the PC when trigger stack monitor.
+         */
+        uint32_t core_0_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_pc_reg_t;
+
+
+/** Group: interrupt configuration register */
+/** Type of core_0_intr_raw register
+ *  core0 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_rd_raw:1;
+        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_wr_raw:1;
+        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_rd_raw:1;
+        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_wr_raw:1;
+        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_rd_raw:1;
+        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_wr_raw:1;
+        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_rd_raw:1;
+        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_wr_raw:1;
+        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_min_raw:1;
+        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_max_raw:1;
+        /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt status
+         */
+        uint32_t core_0_iram0_exception_monitor_raw:1;
+        /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
+         *  DBUS busy monitor initerrupt status
+         */
+        uint32_t core_0_dram0_exception_monitor_raw:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_raw_reg_t;
+
+/** Type of core_0_intr_rls register
+ *  core0 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_rd_rls:1;
+        /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_wr_rls:1;
+        /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_rd_rls:1;
+        /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_wr_rls:1;
+        /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_rd_rls:1;
+        /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_wr_rls:1;
+        /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_rd_rls:1;
+        /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_wr_rls:1;
+        /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_min_rls:1;
+        /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_max_rls:1;
+        /** core_0_iram0_exception_monitor_rls : R/W; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt enable
+         */
+        uint32_t core_0_iram0_exception_monitor_rls:1;
+        /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
+         *  DBUS busy monitor interrupt enable
+         */
+        uint32_t core_0_dram0_exception_monitor_rls:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_rls_reg_t;
+
+/** Type of core_0_intr_clr register
+ *  core0 monitor interrupt clr register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_rd_clr:1;
+        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_wr_clr:1;
+        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_rd_clr:1;
+        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_wr_clr:1;
+        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_rd_clr:1;
+        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_wr_clr:1;
+        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_rd_clr:1;
+        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_wr_clr:1;
+        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_min_clr:1;
+        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_max_clr:1;
+        /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt clr
+         */
+        uint32_t core_0_iram0_exception_monitor_clr:1;
+        /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
+         *  DBUS busy monitor interrupt clr
+         */
+        uint32_t core_0_dram0_exception_monitor_clr:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_clr_reg_t;
+
+
+/** Group: pc recording configuration register */
+/** Type of core_0_rcd_en register
+ *  record enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable record PC
+         */
+        uint32_t core_0_rcd_recorden:1;
+        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+         */
+        uint32_t core_0_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_en_reg_t;
+
+
+/** Group: pc recording status register */
+/** Type of core_0_rcd_pdebugpc register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  recorded PC
+         */
+        uint32_t core_0_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugpc_reg_t;
+
+/** Type of core_0_rcd_pdebugsp register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  recorded sp
+         */
+        uint32_t core_0_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugsp_reg_t;
+
+
+/** Group: exception monitor register */
+/** Type of core_0_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_0
+         */
+        uint32_t core_0_iram0_recording_addr_0:24;
+        /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_0
+         */
+        uint32_t core_0_iram0_recording_wr_0:1;
+        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_0
+         */
+        uint32_t core_0_iram0_recording_loadstore_0:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_1
+         */
+        uint32_t core_0_iram0_recording_addr_1:24;
+        /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_1
+         */
+        uint32_t core_0_iram0_recording_wr_1:1;
+        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_1
+         */
+        uint32_t core_0_iram0_recording_loadstore_1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_0
+         */
+        uint32_t core_0_dram0_recording_addr_0:24;
+        /** core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_dram0_recording_wr_0
+         */
+        uint32_t core_0_dram0_recording_wr_0:1;
+        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_0
+         */
+        uint32_t core_0_dram0_recording_byteen_0:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_0
+         */
+        uint32_t core_0_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_1
+         */
+        uint32_t core_0_dram0_recording_addr_1:24;
+        /** core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_dram0_recording_wr_1
+         */
+        uint32_t core_0_dram0_recording_wr_1:1;
+        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_1
+         */
+        uint32_t core_0_dram0_recording_byteen_1:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_1
+         */
+        uint32_t core_0_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_0 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_0
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_1 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_1
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
+
+
+/** Group: cpu status registers */
+/** Type of core_0_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  cpu's lastpc before exception
+         */
+        uint32_t core_0_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_lastpc_before_exception_reg_t;
+
+/** Type of core_0_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
+         *  cpu debug mode status, 1 means cpu enter debug mode.
+         */
+        uint32_t core_0_debug_mode:1;
+        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  cpu debug_module active status
+         */
+        uint32_t core_0_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_debug_mode_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clock_gate register
+ *  clock register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 force on the clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} assist_debug_clock_gate_reg_t;
+
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
+         *  version register
+         */
+        uint32_t assist_debug_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} assist_debug_date_reg_t;
+
+
+typedef struct assist_debug_dev_t {
+    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
+    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
+    volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
+    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
+    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
+    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
+    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
+    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
+    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
+    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
+    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
+    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
+    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
+    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
+    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
+    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
+    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
+    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
+    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
+    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
+    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
+    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
+    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
+    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
+    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
+    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
+    volatile assist_debug_clock_gate_reg_t clock_gate;
+    uint32_t reserved_07c[224];
+    volatile assist_debug_date_reg_t date;
+} assist_debug_dev_t;
+
+extern assist_debug_dev_t ASSIST_DEBUG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/clint_reg.h b/components/soc/esp32c6/register/soc/clint_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/clint_reg.h
rename to components/soc/esp32c6/register/soc/clint_reg.h
diff --git a/components/soc/esp32c6/include/soc/ds_reg.h b/components/soc/esp32c6/register/soc/ds_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ds_reg.h
rename to components/soc/esp32c6/register/soc/ds_reg.h
diff --git a/components/soc/esp32c6/include/soc/ds_struct.h b/components/soc/esp32c6/register/soc/ds_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ds_struct.h
rename to components/soc/esp32c6/register/soc/ds_struct.h
diff --git a/components/soc/esp32c6/register/soc/ecc_mult_reg.h b/components/soc/esp32c6/register/soc/ecc_mult_reg.h
new file mode 100644
index 00000000000..00846e8ed63
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/ecc_mult_reg.h
@@ -0,0 +1,158 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECC_MULT_INT_RAW_REG register
+ *  ECC interrupt raw register, valid in level.
+ */
+#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
+/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_RAW_S  0
+
+/** ECC_MULT_INT_ST_REG register
+ *  ECC interrupt status register.
+ */
+#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
+/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ST_S  0
+
+/** ECC_MULT_INT_ENA_REG register
+ *  ECC interrupt enable register.
+ */
+#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
+/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ENA_S  0
+
+/** ECC_MULT_INT_CLR_REG register
+ *  ECC interrupt clear register.
+ */
+#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
+/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_CLR_S  0
+
+/** ECC_MULT_CONF_REG register
+ *  ECC configure register
+ */
+#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
+/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
+ *  the caculatrion is done.
+ */
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
+#define ECC_MULT_START_V  0x00000001U
+#define ECC_MULT_START_S  0
+/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
+ *  Write 1 to reset ECC Accelerator.
+ */
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
+#define ECC_MULT_RESET_V  0x00000001U
+#define ECC_MULT_RESET_S  1
+/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
+ *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
+ */
+#define ECC_MULT_KEY_LENGTH    (BIT(2))
+#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
+#define ECC_MULT_KEY_LENGTH_V  0x00000001U
+#define ECC_MULT_KEY_LENGTH_S  2
+/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define ECC_MULT_SECURITY_MODE    (BIT(3))
+#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
+#define ECC_MULT_SECURITY_MODE_V  0x00000001U
+#define ECC_MULT_SECURITY_MODE_S  3
+/** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECC_MULT_CLK_EN    (BIT(4))
+#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
+#define ECC_MULT_CLK_EN_V  0x00000001U
+#define ECC_MULT_CLK_EN_S  4
+/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:5]; default: 0;
+ *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2:
+ *  Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5:
+ *  Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
+ */
+#define ECC_MULT_WORK_MODE    0x00000007U
+#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
+#define ECC_MULT_WORK_MODE_V  0x00000007U
+#define ECC_MULT_WORK_MODE_S  5
+/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [8]; default: 0;
+ *  The verification result bit of ECC Accelerator, only valid when calculation is done.
+ */
+#define ECC_MULT_VERIFICATION_RESULT    (BIT(8))
+#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
+#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
+#define ECC_MULT_VERIFICATION_RESULT_S  8
+/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 1;
+ *  ECC memory clock gate force on register
+ */
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
+
+/** ECC_MULT_DATE_REG register
+ *  Version control register
+ */
+#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
+/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 35656256;
+ *  ECC mult version control register
+ */
+#define ECC_MULT_DATE    0x0FFFFFFFU
+#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
+#define ECC_MULT_DATE_V  0x0FFFFFFFU
+#define ECC_MULT_DATE_S  0
+
+/** ECC_MULT_K_MEM register
+ *  The memory that stores k.
+ */
+#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
+#define ECC_MULT_K_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_PX_MEM register
+ *  The memory that stores Px.
+ */
+#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
+#define ECC_MULT_PX_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_PY_MEM register
+ *  The memory that stores Py.
+ */
+#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
+#define ECC_MULT_PY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/ecc_mult_struct.h b/components/soc/esp32c6/register/soc/ecc_mult_struct.h
new file mode 100644
index 00000000000..89665324365
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/ecc_mult_struct.h
@@ -0,0 +1,158 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECC interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECC interrupt status register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECC interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECC interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of conf register
+ *  ECC configure register
+ */
+typedef union {
+    struct {
+        /** start : R/W/SC; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
+         *  the caculatrion is done.
+         */
+        uint32_t start:1;
+        /** reset : WT; bitpos: [1]; default: 0;
+         *  Write 1 to reset ECC Accelerator.
+         */
+        uint32_t reset:1;
+        /** key_length : R/W; bitpos: [2]; default: 0;
+         *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
+         */
+        uint32_t key_length:1;
+        /** security_mode : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t security_mode:1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_en:1;
+        /** work_mode : R/W; bitpos: [7:5]; default: 0;
+         *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2:
+         *  Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5:
+         *  Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
+         */
+        uint32_t work_mode:3;
+        /** verification_result : RO/SS; bitpos: [8]; default: 0;
+         *  The verification result bit of ECC Accelerator, only valid when calculation is done.
+         */
+        uint32_t verification_result:1;
+        uint32_t reserved_9:22;
+        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 1;
+         *  ECC memory clock gate force on register
+         */
+        uint32_t mem_clock_gate_force_on:1;
+    };
+    uint32_t val;
+} ecc_mult_conf_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35656256;
+         *  ECC mult version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecc_mult_date_reg_t;
+
+
+typedef struct ecc_mult_dev_t {
+    uint32_t reserved_000[3];
+    volatile ecc_mult_int_raw_reg_t int_raw;
+    volatile ecc_mult_int_st_reg_t int_st;
+    volatile ecc_mult_int_ena_reg_t int_ena;
+    volatile ecc_mult_int_clr_reg_t int_clr;
+    volatile ecc_mult_conf_reg_t conf;
+    uint32_t reserved_020[55];
+    volatile ecc_mult_date_reg_t date;
+    volatile uint32_t k[8];
+    volatile uint32_t px[8];
+    volatile uint32_t py[8];
+} ecc_mult_dev_t;
+
+extern ecc_mult_dev_t ECC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecc_mult_dev_t) == 0x160, "Invalid size of ecc_mult_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/efuse_reg.h b/components/soc/esp32c6/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..b91b0b0ff0e
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/efuse_reg.h
@@ -0,0 +1,2727 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/efuse_defs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled or
+ *  enabled. 1: Disabled. 0 Enabled.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_SWAP_UART_SDIO_EN : RO; bitpos: [7]; default: 0;
+ *  Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not
+ *  swapped.
+ */
+#define EFUSE_SWAP_UART_SDIO_EN    (BIT(7))
+#define EFUSE_SWAP_UART_SDIO_EN_M  (EFUSE_SWAP_UART_SDIO_EN_V << EFUSE_SWAP_UART_SDIO_EN_S)
+#define EFUSE_SWAP_UART_SDIO_EN_V  0x00000001U
+#define EFUSE_SWAP_UART_SDIO_EN_S  7
+/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
+ *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_ICACHE    (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
+#define EFUSE_DIS_ICACHE_V  0x00000001U
+#define EFUSE_DIS_ICACHE_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0;
+ *  Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0:
+ *  enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
+ *  Represents whether SPI0 controller during boot_mode_download is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ *  is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+ *  enabled.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+ *  enabled.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode). 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
+ */
+#define EFUSE_USB_DREFH    0x00000003U
+#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
+#define EFUSE_USB_DREFH_V  0x00000003U
+#define EFUSE_USB_DREFH_S  21
+/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
+ *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
+ */
+#define EFUSE_USB_DREFL    0x00000003U
+#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
+#define EFUSE_USB_DREFL_V  0x00000003U
+#define EFUSE_USB_DREFL_S  23
+/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
+ *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.
+ */
+#define EFUSE_USB_EXCHG_PINS    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
+#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_S  25
+/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
+ *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
+ *  functioned.
+ */
+#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
+#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_S  26
+/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_2    0x00000003U
+#define EFUSE_RPT4_RESERVED0_2_M  (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S)
+#define EFUSE_RPT4_RESERVED0_2_V  0x00000003U
+#define EFUSE_RPT4_RESERVED0_2_S  27
+/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_1    (BIT(29))
+#define EFUSE_RPT4_RESERVED0_1_M  (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S)
+#define EFUSE_RPT4_RESERVED0_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED0_1_S  29
+/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_0    0x00000003U
+#define EFUSE_RPT4_RESERVED0_0_M  (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S)
+#define EFUSE_RPT4_RESERVED0_0_V  0x00000003U
+#define EFUSE_RPT4_RESERVED0_0_S  30
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register 2.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_RPT4_RESERVED1_0 : RO; bitpos: [15:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED1_0    0x0000FFFFU
+#define EFUSE_RPT4_RESERVED1_0_M  (EFUSE_RPT4_RESERVED1_0_V << EFUSE_RPT4_RESERVED1_0_S)
+#define EFUSE_RPT4_RESERVED1_0_V  0x0000FFFFU
+#define EFUSE_RPT4_RESERVED1_0_S  0
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+ *  selected. 0: not selected.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+ *  1: enabled. Even number of 1: disabled.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register 3.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Represents the purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  16
+/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [18]; default: 0;
+ *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE    (BIT(18))
+#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
+#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_S  18
+/** EFUSE_RPT4_RESERVED2_1 : RO; bitpos: [19]; default: 1;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_1    (BIT(19))
+#define EFUSE_RPT4_RESERVED2_1_M  (EFUSE_RPT4_RESERVED2_1_V << EFUSE_RPT4_RESERVED2_1_S)
+#define EFUSE_RPT4_RESERVED2_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED2_1_S  19
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_0    0x0000003FU
+#define EFUSE_RPT4_RESERVED2_0_M  (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S)
+#define EFUSE_RPT4_RESERVED2_0_V  0x0000003FU
+#define EFUSE_RPT4_RESERVED2_0_S  22
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+ *  is 2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register 4.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+ *  0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_5    (BIT(3))
+#define EFUSE_RPT4_RESERVED3_5_M  (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S)
+#define EFUSE_RPT4_RESERVED3_5_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_5_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+ *  disabled.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Represents the type of UART printing. 00: force enable printing. 01: enable
+ *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+ *  at high level. 11: force disable printing.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_RPT4_RESERVED3_4 : RO; bitpos: [8]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_4    (BIT(8))
+#define EFUSE_RPT4_RESERVED3_4_M  (EFUSE_RPT4_RESERVED3_4_V << EFUSE_RPT4_RESERVED3_4_S)
+#define EFUSE_RPT4_RESERVED3_4_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_4_S  8
+/** EFUSE_RPT4_RESERVED3_3 : RO; bitpos: [9]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_3    (BIT(9))
+#define EFUSE_RPT4_RESERVED3_3_M  (EFUSE_RPT4_RESERVED3_3_V << EFUSE_RPT4_RESERVED3_3_S)
+#define EFUSE_RPT4_RESERVED3_3_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_3_S  9
+/** EFUSE_RPT4_RESERVED3_2 : RO; bitpos: [11:10]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_2    0x00000003U
+#define EFUSE_RPT4_RESERVED3_2_M  (EFUSE_RPT4_RESERVED3_2_V << EFUSE_RPT4_RESERVED3_2_S)
+#define EFUSE_RPT4_RESERVED3_2_V  0x00000003U
+#define EFUSE_RPT4_RESERVED3_2_S  10
+/** EFUSE_RPT4_RESERVED3_1 : RO; bitpos: [12]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_1    (BIT(12))
+#define EFUSE_RPT4_RESERVED3_1_M  (EFUSE_RPT4_RESERVED3_1_V << EFUSE_RPT4_RESERVED3_1_S)
+#define EFUSE_RPT4_RESERVED3_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_1_S  12
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+ *  forced. 0:not forced.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  14
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [30]; default: 0;
+ *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(30))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  30
+/** EFUSE_RPT4_RESERVED3_0 : RO; bitpos: [31]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_0    (BIT(31))
+#define EFUSE_RPT4_RESERVED3_0_M  (EFUSE_RPT4_RESERVED3_0_V << EFUSE_RPT4_RESERVED3_0_S)
+#define EFUSE_RPT4_RESERVED3_0_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_0_S  31
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register 5.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(0))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  0
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(1))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  1
+/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_0_162    0x003FFFFFU
+#define EFUSE_RESERVED_0_162_M  (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S)
+#define EFUSE_RESERVED_0_162_V  0x003FFFFFU
+#define EFUSE_RESERVED_0_162_S  2
+/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_0    0x000000FFU
+#define EFUSE_RPT4_RESERVED4_0_M  (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S)
+#define EFUSE_RPT4_RESERVED4_0_V  0x000000FFU
+#define EFUSE_RPT4_RESERVED4_0_S  24
+
+/** EFUSE_RD_MAC_SPI_SYS_0_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SPI_SYS_1_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
+ *  Stores the extended bits of MAC address.
+ */
+#define EFUSE_MAC_EXT    0x0000FFFFU
+#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
+#define EFUSE_MAC_EXT_V  0x0000FFFFU
+#define EFUSE_MAC_EXT_S  16
+
+/** EFUSE_RD_MAC_SPI_SYS_2_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [4:0]; default: 0;
+ *  Stores the active hp dbias.
+ */
+#define EFUSE_ACTIVE_HP_DBIAS    0x0000001FU
+#define EFUSE_ACTIVE_HP_DBIAS_M  (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
+#define EFUSE_ACTIVE_HP_DBIAS_V  0x0000001FU
+#define EFUSE_ACTIVE_HP_DBIAS_S  0
+/** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [9:5]; default: 0;
+ *  Stores the active lp dbias.
+ */
+#define EFUSE_ACTIVE_LP_DBIAS    0x0000001FU
+#define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
+#define EFUSE_ACTIVE_LP_DBIAS_V  0x0000001FU
+#define EFUSE_ACTIVE_LP_DBIAS_S  5
+/** EFUSE_LSLP_HP_DBG : RO; bitpos: [11:10]; default: 0;
+ *  Stores the lslp hp dbg.
+ */
+#define EFUSE_LSLP_HP_DBG    0x00000003U
+#define EFUSE_LSLP_HP_DBG_M  (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S)
+#define EFUSE_LSLP_HP_DBG_V  0x00000003U
+#define EFUSE_LSLP_HP_DBG_S  10
+/** EFUSE_LSLP_HP_DBIAS : RO; bitpos: [15:12]; default: 0;
+ *  Stores the lslp hp dbias.
+ */
+#define EFUSE_LSLP_HP_DBIAS    0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_M  (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
+#define EFUSE_LSLP_HP_DBIAS_V  0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_S  12
+/** EFUSE_DSLP_LP_DBG : RO; bitpos: [18:16]; default: 0;
+ *  Stores the dslp lp dbg.
+ */
+#define EFUSE_DSLP_LP_DBG    0x00000007U
+#define EFUSE_DSLP_LP_DBG_M  (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S)
+#define EFUSE_DSLP_LP_DBG_V  0x00000007U
+#define EFUSE_DSLP_LP_DBG_S  16
+/** EFUSE_DSLP_LP_DBIAS : RO; bitpos: [22:19]; default: 0;
+ *  Stores the dslp lp dbias.
+ */
+#define EFUSE_DSLP_LP_DBIAS    0x0000000FU
+#define EFUSE_DSLP_LP_DBIAS_M  (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
+#define EFUSE_DSLP_LP_DBIAS_V  0x0000000FU
+#define EFUSE_DSLP_LP_DBIAS_S  19
+/** EFUSE_DBIAS_VOL_GAP : RO; bitpos: [27:23]; default: 0;
+ *  Stores the hp and lp dbias vol gap.
+ */
+#define EFUSE_DBIAS_VOL_GAP    0x0000001FU
+#define EFUSE_DBIAS_VOL_GAP_M  (EFUSE_DBIAS_VOL_GAP_V << EFUSE_DBIAS_VOL_GAP_S)
+#define EFUSE_DBIAS_VOL_GAP_V  0x0000001FU
+#define EFUSE_DBIAS_VOL_GAP_S  23
+/** EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:28]; default: 0;
+ *  Stores the first part of SPI_PAD_CONF.
+ */
+#define EFUSE_SPI_PAD_CONF_1    0x0000000FU
+#define EFUSE_SPI_PAD_CONF_1_M  (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S)
+#define EFUSE_SPI_PAD_CONF_1_V  0x0000000FU
+#define EFUSE_SPI_PAD_CONF_1_S  28
+
+/** EFUSE_RD_MAC_SPI_SYS_3_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0;
+ *  Stores the second part of SPI_PAD_CONF.
+ */
+#define EFUSE_SPI_PAD_CONF_2    0x0003FFFFU
+#define EFUSE_SPI_PAD_CONF_2_M  (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S)
+#define EFUSE_SPI_PAD_CONF_2_V  0x0003FFFFU
+#define EFUSE_SPI_PAD_CONF_2_S  0
+/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [21:18]; default: 0; */
+#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_S  18
+/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [23:22]; default: 0; */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  22
+/** EFUSE_PKG_VERSION : R; bitpos: [26:24]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  24
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [29:27]; default: 0;
+ *  BLK_VERSION_MINOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  27
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [31:30]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  30
+
+/** EFUSE_RD_MAC_SPI_SYS_4_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_FLASH_CAP : R; bitpos: [2:0]; default: 0; */
+#define EFUSE_FLASH_CAP    0x00000007U
+#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
+#define EFUSE_FLASH_CAP_V  0x00000007U
+#define EFUSE_FLASH_CAP_S  0
+/** EFUSE_FLASH_TEMP : R; bitpos: [4:3]; default: 0; */
+#define EFUSE_FLASH_TEMP    0x00000003U
+#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
+#define EFUSE_FLASH_TEMP_V  0x00000003U
+#define EFUSE_FLASH_TEMP_S  3
+/** EFUSE_FLASH_VENDOR : R; bitpos: [7:5]; default: 0; */
+#define EFUSE_FLASH_VENDOR    0x00000007U
+#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
+#define EFUSE_FLASH_VENDOR_V  0x00000007U
+#define EFUSE_FLASH_VENDOR_S  5
+/** EFUSE_RESERVED_1_136 : R; bitpos: [31:8]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_136    0x00FFFFFFU
+#define EFUSE_RESERVED_1_136_M  (EFUSE_RESERVED_1_136_V << EFUSE_RESERVED_1_136_S)
+#define EFUSE_RESERVED_1_136_V  0x00FFFFFFU
+#define EFUSE_RESERVED_1_136_S  8
+
+/** EFUSE_RD_MAC_SPI_SYS_5_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of the zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_TEMP_CALIB : R; bitpos: [8:0]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMP_CALIB    0x000001FFU
+#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
+#define EFUSE_TEMP_CALIB_V  0x000001FFU
+#define EFUSE_TEMP_CALIB_S  0
+/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
+ *  ADC OCode
+ */
+#define EFUSE_OCODE    0x000000FFU
+#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
+#define EFUSE_OCODE_V  0x000000FFU
+#define EFUSE_OCODE_S  9
+/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
+ *  ADC1 init code at atten0
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_S  17
+/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
+ *  ADC1 init code at atten1
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN1    0x0000001FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_V  0x0000001FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_S  27
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
+ *  ADC1 init code at atten1
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1    0x0000001FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V  0x0000001FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S  0
+/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
+ *  ADC1 init code at atten2
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_M  (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_S  5
+/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
+ *  ADC1 init code at atten3
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_S  15
+/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [31:25]; default: 0;
+ *  ADC1 calibration voltage at atten0
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN0    0x0000007FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_V  0x0000007FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_S  25
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_ADC1_CAL_VOL_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
+ *  ADC1 calibration voltage at atten0
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1    0x00000007U
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_1_V << EFUSE_ADC1_CAL_VOL_ATTEN0_1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_V  0x00000007U
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_1_S  0
+/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [12:3]; default: 0;
+ *  ADC1 calibration voltage at atten1
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_M  (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_S  3
+/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [22:13]; default: 0;
+ *  ADC1 calibration voltage at atten2
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_M  (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_S  13
+/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [31:23]; default: 0;
+ *  ADC1 calibration voltage at atten3
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN3    0x000001FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_V  0x000001FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_S  23
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_ADC1_CAL_VOL_ATTEN3_1 : R; bitpos: [0]; default: 0;
+ *  ADC1 calibration voltage at atten3
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_1    (BIT(0))
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_1_V << EFUSE_ADC1_CAL_VOL_ATTEN3_1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_V  0x00000001U
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_1_S  0
+/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH0 : R; bitpos: [4:1]; default: 0;
+ *  ADC1 init code at atten0 ch0
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0    0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_V  0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH0_S  1
+/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH1 : R; bitpos: [8:5]; default: 0;
+ *  ADC1 init code at atten0 ch1
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1    0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_V  0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH1_S  5
+/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH2 : R; bitpos: [12:9]; default: 0;
+ *  ADC1 init code at atten0 ch2
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2    0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_V  0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH2_S  9
+/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH3 : R; bitpos: [16:13]; default: 0;
+ *  ADC1 init code at atten0 ch3
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3    0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_V  0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH3_S  13
+/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH4 : R; bitpos: [20:17]; default: 0;
+ *  ADC1 init code at atten0 ch4
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4    0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_V  0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH4_S  17
+/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH5 : R; bitpos: [24:21]; default: 0;
+ *  ADC1 init code at atten0 ch5
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5    0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_V  0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH5_S  21
+/** EFUSE_ADC1_INIT_CODE_ATTEN0_CH6 : R; bitpos: [28:25]; default: 0;
+ *  ADC1 init code at atten0 ch6
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6    0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_V << EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_V  0x0000000FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_CH6_S  25
+/** EFUSE_RESERVED_2_253 : R; bitpos: [31:29]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_253    0x00000007U
+#define EFUSE_RESERVED_2_253_M  (EFUSE_RESERVED_2_253_V << EFUSE_RESERVED_2_253_S)
+#define EFUSE_RESERVED_2_253_V  0x00000007U
+#define EFUSE_RESERVED_2_253_S  29
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Indicates a programming error of RD_DIS.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_SWAP_UART_SDIO_EN_ERR : RO; bitpos: [7]; default: 0;
+ *  Indicates a programming error of SWAP_UART_SDIO_EN.
+ */
+#define EFUSE_SWAP_UART_SDIO_EN_ERR    (BIT(7))
+#define EFUSE_SWAP_UART_SDIO_EN_ERR_M  (EFUSE_SWAP_UART_SDIO_EN_ERR_V << EFUSE_SWAP_UART_SDIO_EN_ERR_S)
+#define EFUSE_SWAP_UART_SDIO_EN_ERR_V  0x00000001U
+#define EFUSE_SWAP_UART_SDIO_EN_ERR_S  7
+/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of DIS_ICACHE.
+ */
+#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
+#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_ICACHE_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  Indicates a programming error of DIS_USB_JTAG.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_ICACHE.
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
+ *  Indicates a programming error of DIS_USB_DEVICE.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of DIS_CAN.
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  Indicates a programming error of JTAG_SEL_ENABLE.
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  Indicates a programming error of SOFT_DIS_JTAG.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DIS_PAD_JTAG.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Indicates a programming error of USB_DREFH.
+ */
+#define EFUSE_USB_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
+#define EFUSE_USB_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DREFH_ERR_S  21
+/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
+ *  Indicates a programming error of USB_DREFL.
+ */
+#define EFUSE_USB_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
+#define EFUSE_USB_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DREFL_ERR_S  23
+/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of USB_EXCHG_PINS.
+ */
+#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_ERR_S  25
+/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of VDD_SPI_AS_GPIO.
+ */
+#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
+/** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR_2    0x00000003U
+#define EFUSE_RPT4_RESERVED0_ERR_2_M  (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S)
+#define EFUSE_RPT4_RESERVED0_ERR_2_V  0x00000003U
+#define EFUSE_RPT4_RESERVED0_ERR_2_S  27
+/** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR_1    (BIT(29))
+#define EFUSE_RPT4_RESERVED0_ERR_1_M  (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S)
+#define EFUSE_RPT4_RESERVED0_ERR_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED0_ERR_1_S  29
+/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR_0    0x00000003U
+#define EFUSE_RPT4_RESERVED0_ERR_0_M  (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S)
+#define EFUSE_RPT4_RESERVED0_ERR_0_V  0x00000003U
+#define EFUSE_RPT4_RESERVED0_ERR_0_S  30
+
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED1_ERR_0    0x0000FFFFU
+#define EFUSE_RPT4_RESERVED1_ERR_0_M  (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S)
+#define EFUSE_RPT4_RESERVED1_ERR_0_V  0x0000FFFFU
+#define EFUSE_RPT4_RESERVED1_ERR_0_S  0
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of WDT_DELAY_SEL.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_0.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_1.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_2.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_3.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_4.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_5.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of SEC_DPA_LEVEL.
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
+/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_ERR_1    (BIT(18))
+#define EFUSE_RPT4_RESERVED2_ERR_1_M  (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S)
+#define EFUSE_RPT4_RESERVED2_ERR_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED2_ERR_1_S  18
+/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of CRYPT_DPA_ENABLE.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_EN.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_ERR_0    0x0000003FU
+#define EFUSE_RPT4_RESERVED2_ERR_0_M  (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S)
+#define EFUSE_RPT4_RESERVED2_ERR_0_V  0x0000003FU
+#define EFUSE_RPT4_RESERVED2_ERR_0_S  22
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of FLASH_TPUW.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  Indicates a programming error of DIS_DIRECT_BOOT.
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0;
+ *  Indicates a programming error of UART_PRINT_CHANNEL.
+ */
+#define EFUSE_USB_PRINT_ERR    (BIT(2))
+#define EFUSE_USB_PRINT_ERR_M  (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S)
+#define EFUSE_USB_PRINT_ERR_V  0x00000001U
+#define EFUSE_USB_PRINT_ERR_S  2
+/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR_5    (BIT(3))
+#define EFUSE_RPT4_RESERVED3_ERR_5_M  (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S)
+#define EFUSE_RPT4_RESERVED3_ERR_5_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_ERR_5_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of UART_PRINT_CONTROL.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_RPT4_RESERVED3_ERR_4 : RO; bitpos: [8]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR_4    (BIT(8))
+#define EFUSE_RPT4_RESERVED3_ERR_4_M  (EFUSE_RPT4_RESERVED3_ERR_4_V << EFUSE_RPT4_RESERVED3_ERR_4_S)
+#define EFUSE_RPT4_RESERVED3_ERR_4_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_ERR_4_S  8
+/** EFUSE_RPT4_RESERVED3_ERR_3 : RO; bitpos: [9]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR_3    (BIT(9))
+#define EFUSE_RPT4_RESERVED3_ERR_3_M  (EFUSE_RPT4_RESERVED3_ERR_3_V << EFUSE_RPT4_RESERVED3_ERR_3_S)
+#define EFUSE_RPT4_RESERVED3_ERR_3_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_ERR_3_S  9
+/** EFUSE_RPT4_RESERVED3_ERR_2 : RO; bitpos: [11:10]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR_2    0x00000003U
+#define EFUSE_RPT4_RESERVED3_ERR_2_M  (EFUSE_RPT4_RESERVED3_ERR_2_V << EFUSE_RPT4_RESERVED3_ERR_2_S)
+#define EFUSE_RPT4_RESERVED3_ERR_2_V  0x00000003U
+#define EFUSE_RPT4_RESERVED3_ERR_2_S  10
+/** EFUSE_RPT4_RESERVED3_ERR_1 : RO; bitpos: [12]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR_1    (BIT(12))
+#define EFUSE_RPT4_RESERVED3_ERR_1_M  (EFUSE_RPT4_RESERVED3_ERR_1_V << EFUSE_RPT4_RESERVED3_ERR_1_S)
+#define EFUSE_RPT4_RESERVED3_ERR_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_ERR_1_S  12
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of FORCE_SEND_RESUME.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0;
+ *  Indicates a programming error of SECURE_VERSION.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  14
+/** EFUSE_RPT4_RESERVED3_ERR_0 : RO; bitpos: [31:30]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR_0    0x00000003U
+#define EFUSE_RPT4_RESERVED3_ERR_0_M  (EFUSE_RPT4_RESERVED3_ERR_0_V << EFUSE_RPT4_RESERVED3_ERR_0_S)
+#define EFUSE_RPT4_RESERVED3_ERR_0_V  0x00000003U
+#define EFUSE_RPT4_RESERVED3_ERR_0_S  30
+
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
+/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_ERR_1    0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED4_ERR_1_M  (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S)
+#define EFUSE_RPT4_RESERVED4_ERR_1_V  0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED4_ERR_1_S  0
+/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_ERR_0    0x000000FFU
+#define EFUSE_RPT4_RESERVED4_ERR_0_M  (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S)
+#define EFUSE_RPT4_RESERVED4_ERR_0_V  0x000000FFU
+#define EFUSE_RPT4_RESERVED4_ERR_0_S  24
+
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
+#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
+/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SPI_8M_FAIL    (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
+#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
+#define EFUSE_MAC_SPI_8M_FAIL_S  3
+/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_NUM    0x00000007U
+#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
+#define EFUSE_SYS_PART1_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_NUM_S  4
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+ *  key0 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+ *  key1 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+ *  key2 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+ *  key3 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+ *  key4 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  31
+
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+ *  key5 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART2_FAIL_S  7
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to force enable eFuse register configuration clock signal.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Indicates the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
+ *  Configures the waiting time of reading eFuse memory.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200;
+ *  Configures the active programming time.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to bypass reed solomon correction step.
+ */
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures block number of programming twice operation.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Set this bit to update multi-bit register signals.
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35676928;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/efuse_struct.h b/components/soc/esp32c6/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..c92f02208c4
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/efuse_struct.h
@@ -0,0 +1,2443 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: Read Data Register */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled or
+         *  enabled. 1: Disabled. 0 Enabled.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t rd_dis:7;
+        /** swap_uart_sdio_en : RO; bitpos: [7]; default: 0;
+         *  Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not
+         *  swapped.
+         */
+        uint32_t swap_uart_sdio_en:1;
+        /** dis_icache : RO; bitpos: [8]; default: 0;
+         *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_icache:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** dis_download_icache : RO; bitpos: [10]; default: 0;
+         *  Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0:
+         *  enabled.
+         */
+        uint32_t dis_download_icache:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Represents whether SPI0 controller during boot_mode_download is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         *  is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+         *  enabled.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+         *  enabled.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode). 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
+         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
+         */
+        uint32_t usb_drefh:2;
+        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
+         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
+         */
+        uint32_t usb_drefl:2;
+        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
+         *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.
+         */
+        uint32_t usb_exchg_pins:1;
+        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
+         *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
+         *  functioned.
+         */
+        uint32_t vdd_spi_as_gpio:1;
+        /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_2:2;
+        /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_1:1;
+        /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_0:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register 2.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved1_0 : RO; bitpos: [15:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved1_0:16;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+         *  selected. 0: not selected.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+         *  1: enabled. Even number of 1: disabled.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register 3.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Represents the purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** crypt_dpa_enable : RO; bitpos: [18]; default: 0;
+         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+         */
+        uint32_t crypt_dpa_enable:1;
+        /** rpt4_reserved2_1 : RO; bitpos: [19]; default: 1;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_1:1;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_0:6;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+         *  is 2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register 4.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+         *  0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_5:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+         *  disabled.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Represents the type of UART printing. 00: force enable printing. 01: enable
+         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+         *  at high level. 11: force disable printing.
+         */
+        uint32_t uart_print_control:2;
+        /** rpt4_reserved3_4 : RO; bitpos: [8]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_4:1;
+        /** rpt4_reserved3_3 : RO; bitpos: [9]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_3:1;
+        /** rpt4_reserved3_2 : RO; bitpos: [11:10]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_2:2;
+        /** rpt4_reserved3_1 : RO; bitpos: [12]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_1:1;
+        /** force_send_resume : RO; bitpos: [13]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+         *  forced. 0:not forced.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [29:14]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [30]; default: 0;
+         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** rpt4_reserved3_0 : RO; bitpos: [31]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_0:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register 5.
+ */
+typedef union {
+    struct {
+        /** disable_wafer_version_major : R; bitpos: [0]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [1]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** reserved_0_162 : R; bitpos: [23:2]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_0_162:22;
+        /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_0:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_spi_sys_0 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_0_reg_t;
+
+/** Type of rd_mac_spi_sys_1 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** mac_ext : RO; bitpos: [31:16]; default: 0;
+         *  Stores the extended bits of MAC address.
+         */
+        uint32_t mac_ext:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_1_reg_t;
+
+/** Type of rd_mac_spi_sys_2 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** active_hp_dbias : RO; bitpos: [4:0]; default: 0;
+         *  Stores the active hp dbias.
+         */
+        uint32_t active_hp_dbias:5;
+        /** active_lp_dbias : RO; bitpos: [9:5]; default: 0;
+         *  Stores the active lp dbias.
+         */
+        uint32_t active_lp_dbias:5;
+        /** lslp_hp_dbg : RO; bitpos: [11:10]; default: 0;
+         *  Stores the lslp hp dbg.
+         */
+        uint32_t lslp_hp_dbg:2;
+        /** lslp_hp_dbias : RO; bitpos: [15:12]; default: 0;
+         *  Stores the lslp hp dbias.
+         */
+        uint32_t lslp_hp_dbias:4;
+        /** dslp_lp_dbg : RO; bitpos: [18:16]; default: 0;
+         *  Stores the dslp lp dbg.
+         */
+        uint32_t dslp_lp_dbg:3;
+        /** dslp_lp_dbias : RO; bitpos: [22:19]; default: 0;
+         *  Stores the dslp lp dbias.
+         */
+        uint32_t dslp_lp_dbias:4;
+        /** dbias_vol_gap : RO; bitpos: [27:23]; default: 0;
+         *  Stores the hp and lp dbias vol gap.
+         */
+        uint32_t dbias_vol_gap:5;
+        /** spi_pad_conf_1 : RO; bitpos: [31:28]; default: 0;
+         *  Stores the first part of SPI_PAD_CONF.
+         */
+        uint32_t spi_pad_conf_1:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_2_reg_t;
+
+/** Type of rd_mac_spi_sys_3 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** spi_pad_conf_2 : RO; bitpos: [17:0]; default: 0;
+         *  Stores the second part of SPI_PAD_CONF.
+         */
+        uint32_t spi_pad_conf_2:18;
+        /** wafer_version_minor : R; bitpos: [21:18]; default: 0; */
+        uint32_t wafer_version_minor:4;
+        /** wafer_version_major : R; bitpos: [23:22]; default: 0; */
+        uint32_t wafer_version_major:2;
+        /** pkg_version : R; bitpos: [26:24]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** blk_version_minor : R; bitpos: [29:27]; default: 0;
+         *  BLK_VERSION_MINOR of BLOCK2
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [31:30]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_3_reg_t;
+
+/** Type of rd_mac_spi_sys_4 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** flash_cap : R; bitpos: [2:0]; default: 0; */
+        uint32_t flash_cap:3;
+        /** flash_temp : R; bitpos: [4:3]; default: 0; */
+        uint32_t flash_temp:2;
+        /** flash_vendor : R; bitpos: [7:5]; default: 0; */
+        uint32_t flash_vendor:3;
+        /** reserved_1_136 : R; bitpos: [31:8]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_136:24;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_4_reg_t;
+
+/** Type of rd_mac_spi_sys_5 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of the zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** temp_calib : R; bitpos: [8:0]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temp_calib:9;
+        /** ocode : R; bitpos: [16:9]; default: 0;
+         *  ADC OCode
+         */
+        uint32_t ocode:8;
+        /** adc1_init_code_atten0 : R; bitpos: [26:17]; default: 0;
+         *  ADC1 init code at atten0
+         */
+        uint32_t adc1_init_code_atten0:10;
+        /** adc1_init_code_atten1 : R; bitpos: [31:27]; default: 0;
+         *  ADC1 init code at atten1
+         */
+        uint32_t adc1_init_code_atten1:5;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_init_code_atten1_1 : R; bitpos: [4:0]; default: 0;
+         *  ADC1 init code at atten1
+         */
+        uint32_t adc1_init_code_atten1_1:5;
+        /** adc1_init_code_atten2 : R; bitpos: [14:5]; default: 0;
+         *  ADC1 init code at atten2
+         */
+        uint32_t adc1_init_code_atten2:10;
+        /** adc1_init_code_atten3 : R; bitpos: [24:15]; default: 0;
+         *  ADC1 init code at atten3
+         */
+        uint32_t adc1_init_code_atten3:10;
+        /** adc1_cal_vol_atten0 : R; bitpos: [31:25]; default: 0;
+         *  ADC1 calibration voltage at atten0
+         */
+        uint32_t adc1_cal_vol_atten0:7;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_cal_vol_atten0_1 : R; bitpos: [2:0]; default: 0;
+         *  ADC1 calibration voltage at atten0
+         */
+        uint32_t adc1_cal_vol_atten0_1:3;
+        /** adc1_cal_vol_atten1 : R; bitpos: [12:3]; default: 0;
+         *  ADC1 calibration voltage at atten1
+         */
+        uint32_t adc1_cal_vol_atten1:10;
+        /** adc1_cal_vol_atten2 : R; bitpos: [22:13]; default: 0;
+         *  ADC1 calibration voltage at atten2
+         */
+        uint32_t adc1_cal_vol_atten2:10;
+        /** adc1_cal_vol_atten3 : R; bitpos: [31:23]; default: 0;
+         *  ADC1 calibration voltage at atten3
+         */
+        uint32_t adc1_cal_vol_atten3:9;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_cal_vol_atten3_1 : R; bitpos: [0]; default: 0;
+         *  ADC1 calibration voltage at atten3
+         */
+        uint32_t adc1_cal_vol_atten3_1:1;
+        /** adc1_init_code_atten0_ch0 : R; bitpos: [4:1]; default: 0;
+         *  ADC1 init code at atten0 ch0
+         */
+        uint32_t adc1_init_code_atten0_ch0:4;
+        /** adc1_init_code_atten0_ch1 : R; bitpos: [8:5]; default: 0;
+         *  ADC1 init code at atten0 ch1
+         */
+        uint32_t adc1_init_code_atten0_ch1:4;
+        /** adc1_init_code_atten0_ch2 : R; bitpos: [12:9]; default: 0;
+         *  ADC1 init code at atten0 ch2
+         */
+        uint32_t adc1_init_code_atten0_ch2:4;
+        /** adc1_init_code_atten0_ch3 : R; bitpos: [16:13]; default: 0;
+         *  ADC1 init code at atten0 ch3
+         */
+        uint32_t adc1_init_code_atten0_ch3:4;
+        /** adc1_init_code_atten0_ch4 : R; bitpos: [20:17]; default: 0;
+         *  ADC1 init code at atten0 ch4
+         */
+        uint32_t adc1_init_code_atten0_ch4:4;
+        /** adc1_init_code_atten0_ch5 : R; bitpos: [24:21]; default: 0;
+         *  ADC1 init code at atten0 ch5
+         */
+        uint32_t adc1_init_code_atten0_ch5:4;
+        /** adc1_init_code_atten0_ch6 : R; bitpos: [28:25]; default: 0;
+         *  ADC1 init code at atten0 ch6
+         */
+        uint32_t adc1_init_code_atten0_ch6:4;
+        /** reserved_2_253 : R; bitpos: [31:29]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_253:3;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+
+/** Group: Report Register */
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Indicates a programming error of RD_DIS.
+         */
+        uint32_t rd_dis_err:7;
+        /** swap_uart_sdio_en_err : RO; bitpos: [7]; default: 0;
+         *  Indicates a programming error of SWAP_UART_SDIO_EN.
+         */
+        uint32_t swap_uart_sdio_en_err:1;
+        /** dis_icache_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of DIS_ICACHE.
+         */
+        uint32_t dis_icache_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Indicates a programming error of DIS_USB_JTAG.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** dis_download_icache_err : RO; bitpos: [10]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_ICACHE.
+         */
+        uint32_t dis_download_icache_err:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
+         *  Indicates a programming error of DIS_USB_DEVICE.
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of DIS_CAN.
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Indicates a programming error of JTAG_SEL_ENABLE.
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Indicates a programming error of SOFT_DIS_JTAG.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DIS_PAD_JTAG.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  Indicates a programming error of USB_DREFH.
+         */
+        uint32_t usb_drefh_err:2;
+        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
+         *  Indicates a programming error of USB_DREFL.
+         */
+        uint32_t usb_drefl_err:2;
+        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of USB_EXCHG_PINS.
+         */
+        uint32_t usb_exchg_pins_err:1;
+        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of VDD_SPI_AS_GPIO.
+         */
+        uint32_t vdd_spi_as_gpio_err:1;
+        /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err_2:2;
+        /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err_1:1;
+        /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err_0:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved1_err_0:16;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of WDT_DELAY_SEL.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_0.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_1.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_2.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_3.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_4.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_5.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of SEC_DPA_LEVEL.
+         */
+        uint32_t sec_dpa_level_err:2;
+        /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_err_1:1;
+        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of CRYPT_DPA_ENABLE.
+         */
+        uint32_t crypt_dpa_enable_err:1;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_EN.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_err_0:6;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of FLASH_TPUW.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Indicates a programming error of DIS_DIRECT_BOOT.
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** usb_print_err : RO; bitpos: [2]; default: 0;
+         *  Indicates a programming error of UART_PRINT_CHANNEL.
+         */
+        uint32_t usb_print_err:1;
+        /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err_5:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of UART_PRINT_CONTROL.
+         */
+        uint32_t uart_print_control_err:2;
+        /** rpt4_reserved3_err_4 : RO; bitpos: [8]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err_4:1;
+        /** rpt4_reserved3_err_3 : RO; bitpos: [9]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err_3:1;
+        /** rpt4_reserved3_err_2 : RO; bitpos: [11:10]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err_2:2;
+        /** rpt4_reserved3_err_1 : RO; bitpos: [12]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err_1:1;
+        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of FORCE_SEND_RESUME.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [29:14]; default: 0;
+         *  Indicates a programming error of SECURE_VERSION.
+         */
+        uint32_t secure_version_err:16;
+        /** rpt4_reserved3_err_0 : RO; bitpos: [31:30]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err_0:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved4_err_1 : RO; bitpos: [23:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_err_1:24;
+        /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_err_0:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_spi_8m_err_num:3;
+        /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_spi_8m_fail:1;
+        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_num:3;
+        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** key0_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+         *  key0 failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key1_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+         *  key1 failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key2_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+         *  key2 failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key3_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+         *  key3 failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key4_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+         *  key4 failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key5_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+         *  key5 failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part2_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 200;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WO; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35676928;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0;
+    volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1;
+    volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2;
+    volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3;
+    volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4;
+    volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    uint32_t reserved_18c;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_194[11];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    volatile efuse_date_reg_t date;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/extmem_reg.h b/components/soc/esp32c6/register/soc/extmem_reg.h
new file mode 100644
index 00000000000..08a9daf433c
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/extmem_reg.h
@@ -0,0 +1,871 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define EXTMEM_L1_CACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x4)
+/* EXTMEM_L1_CACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
+#define EXTMEM_L1_CACHE_SHUT_DBUS    (BIT(1))
+#define EXTMEM_L1_CACHE_SHUT_DBUS_M  (BIT(1))
+#define EXTMEM_L1_CACHE_SHUT_DBUS_V  0x1
+#define EXTMEM_L1_CACHE_SHUT_DBUS_S  1
+/* EXTMEM_L1_CACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
+#define EXTMEM_L1_CACHE_SHUT_IBUS    (BIT(0))
+#define EXTMEM_L1_CACHE_SHUT_IBUS_M  (BIT(0))
+#define EXTMEM_L1_CACHE_SHUT_IBUS_V  0x1
+#define EXTMEM_L1_CACHE_SHUT_IBUS_S  0
+
+#define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x20)
+/* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
+#define EXTMEM_L1_CACHE_WRAP    (BIT(4))
+#define EXTMEM_L1_CACHE_WRAP_M  (BIT(4))
+#define EXTMEM_L1_CACHE_WRAP_V  0x1
+#define EXTMEM_L1_CACHE_WRAP_S  4
+
+#define EXTMEM_L1_CACHE_TAG_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x24)
+/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
+/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_M  (BIT(18))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PU_S  18
+/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power
+down.*/
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_M  (BIT(17))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_PD_S  17
+/* EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating,
+0: open clock gating..*/
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_M  (BIT(16))
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_FORCE_ON_S  16
+
+#define EXTMEM_L1_CACHE_DATA_MEM_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x28)
+/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
+/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u
+p.*/
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_M  (BIT(18))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PU_S  18
+/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
+ down.*/
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_M  (BIT(17))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_PD_S  17
+/* EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to close clock gating of  L1-Cache data memory. 1: close gating,
+ 0: open clock gating..*/
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_M  (BIT(16))
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_FORCE_ON_S  16
+
+#define EXTMEM_L1_CACHE_FREEZE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x2C)
+/* EXTMEM_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */
+/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or
+not. 0: not finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_FREEZE_DONE    (BIT(18))
+#define EXTMEM_L1_CACHE_FREEZE_DONE_M  (BIT(18))
+#define EXTMEM_L1_CACHE_FREEZE_DONE_V  0x1
+#define EXTMEM_L1_CACHE_FREEZE_DONE_S  18
+/* EXTMEM_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+ will not stuck. 1: a miss-access will stuck..*/
+#define EXTMEM_L1_CACHE_FREEZE_MODE    (BIT(17))
+#define EXTMEM_L1_CACHE_FREEZE_MODE_M  (BIT(17))
+#define EXTMEM_L1_CACHE_FREEZE_MODE_V  0x1
+#define EXTMEM_L1_CACHE_FREEZE_MODE_S  17
+/* EXTMEM_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof
+tware..*/
+#define EXTMEM_L1_CACHE_FREEZE_EN    (BIT(16))
+#define EXTMEM_L1_CACHE_FREEZE_EN_M  (BIT(16))
+#define EXTMEM_L1_CACHE_FREEZE_EN_V  0x1
+#define EXTMEM_L1_CACHE_FREEZE_EN_S  16
+
+#define EXTMEM_L1_CACHE_DATA_MEM_ACS_CONF_REG          (DR_REG_EXTMEM_BASE + 0x30)
+/* EXTMEM_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable,
+1: enable..*/
+#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
+#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_M  (BIT(17))
+#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_WR_EN_S  17
+/* EXTMEM_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1
+: enable..*/
+#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
+#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_M  (BIT(16))
+#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_V  0x1
+#define EXTMEM_L1_CACHE_DATA_MEM_RD_EN_S  16
+
+#define EXTMEM_L1_CACHE_TAG_MEM_ACS_CONF_REG          (DR_REG_EXTMEM_BASE + 0x34)
+/* EXTMEM_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1
+: enable..*/
+#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
+#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_M  (BIT(17))
+#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_WR_EN_S  17
+/* EXTMEM_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+ enable..*/
+#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
+#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_M  (BIT(16))
+#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_V  0x1
+#define EXTMEM_L1_CACHE_TAG_MEM_RD_EN_S  16
+
+#define EXTMEM_L1_CACHE_PRELOCK_CONF_REG          (DR_REG_EXTMEM_BASE + 0x78)
+/* EXTMEM_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_M  (BIT(1))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_V  0x1
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_EN_S  1
+/* EXTMEM_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_M  (BIT(0))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_V  0x1
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_EN_S  0
+
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x7C)
+/* EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the first section
+of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0
+_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x80)
+/* EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the second section
+ of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT
+1_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x84)
+/* EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */
+/*description: Those bits are used to configure the size of the second section of prelock on L1
+-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x3FFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
+/* EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */
+/*description: Those bits are used to configure the size of the first section of prelock on L1-
+Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S))
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x3FFF
+#define EXTMEM_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x88)
+/* EXTMEM_L1_CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+ not finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_LOCK_DONE    (BIT(2))
+#define EXTMEM_L1_CACHE_LOCK_DONE_M  (BIT(2))
+#define EXTMEM_L1_CACHE_LOCK_DONE_V  0x1
+#define EXTMEM_L1_CACHE_LOCK_DONE_S  2
+/* EXTMEM_L1_CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
+ unlock operation done.*/
+#define EXTMEM_L1_CACHE_UNLOCK_ENA    (BIT(1))
+#define EXTMEM_L1_CACHE_UNLOCK_ENA_M  (BIT(1))
+#define EXTMEM_L1_CACHE_UNLOCK_ENA_V  0x1
+#define EXTMEM_L1_CACHE_UNLOCK_ENA_S  1
+/* EXTMEM_L1_CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
+ock operation done.*/
+#define EXTMEM_L1_CACHE_LOCK_ENA    (BIT(0))
+#define EXTMEM_L1_CACHE_LOCK_ENA_M  (BIT(0))
+#define EXTMEM_L1_CACHE_LOCK_ENA_V  0x1
+#define EXTMEM_L1_CACHE_LOCK_ENA_S  0
+
+#define EXTMEM_L1_CACHE_LOCK_MAP_REG          (DR_REG_EXTMEM_BASE + 0x8C)
+/* EXTMEM_L1_CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: Those bits are used to indicate which caches in the two-level cache structure wi
+ll apply this lock/unlock operation. [4]: L1-Cache.*/
+#define EXTMEM_L1_CACHE_LOCK_MAP    0x0000003F
+#define EXTMEM_L1_CACHE_LOCK_MAP_M  ((EXTMEM_L1_CACHE_LOCK_MAP_V)<<(EXTMEM_L1_CACHE_LOCK_MAP_S))
+#define EXTMEM_L1_CACHE_LOCK_MAP_V  0x3F
+#define EXTMEM_L1_CACHE_LOCK_MAP_S  0
+
+#define EXTMEM_L1_CACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x90)
+/* EXTMEM_L1_CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the lock/unlock op
+eration, which should be used together with CACHE_LOCK_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_LOCK_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_LOCK_ADDR_M  ((EXTMEM_L1_CACHE_LOCK_ADDR_V)<<(EXTMEM_L1_CACHE_LOCK_ADDR_S))
+#define EXTMEM_L1_CACHE_LOCK_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_LOCK_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x94)
+/* EXTMEM_L1_CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Those bits are used to configure the size of the lock/unlock operation, which sh
+ould be used together with CACHE_LOCK_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_LOCK_SIZE    0x0000FFFF
+#define EXTMEM_L1_CACHE_LOCK_SIZE_M  ((EXTMEM_L1_CACHE_LOCK_SIZE_V)<<(EXTMEM_L1_CACHE_LOCK_SIZE_S))
+#define EXTMEM_L1_CACHE_LOCK_SIZE_V  0xFFFF
+#define EXTMEM_L1_CACHE_LOCK_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x98)
+/* EXTMEM_L1_CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback
+, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE    (BIT(4))
+#define EXTMEM_L1_CACHE_SYNC_DONE_M  (BIT(4))
+#define EXTMEM_L1_CACHE_SYNC_DONE_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_S  4
+/* EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
+hardware after writeback-invalidate operation done. Note that this bit and the
+other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
+, that is, those bits can not be set to 1 at the same time..*/
+#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
+#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_V  0x1
+#define EXTMEM_L1_CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/* EXTMEM_L1_CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
+ter writeback operation done. Note that this bit and the other sync-bits (invali
+date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+those bits can not be set to 1 at the same time..*/
+#define EXTMEM_L1_CACHE_WRITEBACK_ENA    (BIT(2))
+#define EXTMEM_L1_CACHE_WRITEBACK_ENA_M  (BIT(2))
+#define EXTMEM_L1_CACHE_WRITEBACK_ENA_V  0x1
+#define EXTMEM_L1_CACHE_WRITEBACK_ENA_S  2
+/* EXTMEM_L1_CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable clean operation. It will be cleared by hardware after
+clean operation done. Note that this bit and the other sync-bits (invalidate_ena
+, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+bits can not be set to 1 at the same time..*/
+#define EXTMEM_L1_CACHE_CLEAN_ENA    (BIT(1))
+#define EXTMEM_L1_CACHE_CLEAN_ENA_M  (BIT(1))
+#define EXTMEM_L1_CACHE_CLEAN_ENA_V  0x1
+#define EXTMEM_L1_CACHE_CLEAN_ENA_S  1
+/* EXTMEM_L1_CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
+/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
+after invalidate operation done. Note that this bit and the other sync-bits (clean_ena,
+writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+ those bits can not be set to 1 at the same time..*/
+#define EXTMEM_L1_CACHE_INVALIDATE_ENA    (BIT(0))
+#define EXTMEM_L1_CACHE_INVALIDATE_ENA_M  (BIT(0))
+#define EXTMEM_L1_CACHE_INVALIDATE_ENA_V  0x1
+#define EXTMEM_L1_CACHE_INVALIDATE_ENA_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_MAP_REG          (DR_REG_EXTMEM_BASE + 0x9C)
+/* EXTMEM_L1_CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
+/*description: Those bits are used to indicate which caches in the two-level cache structure wi
+ll apply the sync operation.  [4]: L1-Cache.*/
+#define EXTMEM_L1_CACHE_SYNC_MAP    0x0000003F
+#define EXTMEM_L1_CACHE_SYNC_MAP_M  ((EXTMEM_L1_CACHE_SYNC_MAP_V)<<(EXTMEM_L1_CACHE_SYNC_MAP_S))
+#define EXTMEM_L1_CACHE_SYNC_MAP_V  0x3F
+#define EXTMEM_L1_CACHE_SYNC_MAP_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xA0)
+/* EXTMEM_L1_CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the sync operation
+, which should be used together with CACHE_SYNC_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_SYNC_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_SYNC_ADDR_M  ((EXTMEM_L1_CACHE_SYNC_ADDR_V)<<(EXTMEM_L1_CACHE_SYNC_ADDR_S))
+#define EXTMEM_L1_CACHE_SYNC_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_SYNC_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xA4)
+/* EXTMEM_L1_CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Those bits are used to configure the size of the sync operation, which should be
+ used together with CACHE_SYNC_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_SYNC_SIZE    0x00FFFFFF
+#define EXTMEM_L1_CACHE_SYNC_SIZE_M  ((EXTMEM_L1_CACHE_SYNC_SIZE_V)<<(EXTMEM_L1_CACHE_SYNC_SIZE_S))
+#define EXTMEM_L1_CACHE_SYNC_SIZE_V  0xFFFFFF
+#define EXTMEM_L1_CACHE_SYNC_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xD8)
+/* EXTMEM_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
+/*description: The bit is used to set  the gid of l1 cache preload..*/
+#define EXTMEM_L1_CACHE_PRELOAD_RGID    0x0000000F
+#define EXTMEM_L1_CACHE_PRELOAD_RGID_M  ((EXTMEM_L1_CACHE_PRELOAD_RGID_V)<<(EXTMEM_L1_CACHE_PRELOAD_RGID_S))
+#define EXTMEM_L1_CACHE_PRELOAD_RGID_V  0xF
+#define EXTMEM_L1_CACHE_PRELOAD_RGID_S  3
+/* EXTMEM_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1
+: descending..*/
+#define EXTMEM_L1_CACHE_PRELOAD_ORDER    (BIT(2))
+#define EXTMEM_L1_CACHE_PRELOAD_ORDER_M  (BIT(2))
+#define EXTMEM_L1_CACHE_PRELOAD_ORDER_V  0x1
+#define EXTMEM_L1_CACHE_PRELOAD_ORDER_S  2
+/* EXTMEM_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether preload operation is finished or not. 0: not
+ finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_PRELOAD_DONE    (BIT(1))
+#define EXTMEM_L1_CACHE_PRELOAD_DONE_M  (BIT(1))
+#define EXTMEM_L1_CACHE_PRELOAD_DONE_V  0x1
+#define EXTMEM_L1_CACHE_PRELOAD_DONE_S  1
+/* EXTMEM_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h
+ardware automatically after preload operation is done..*/
+#define EXTMEM_L1_CACHE_PRELOAD_ENA    (BIT(0))
+#define EXTMEM_L1_CACHE_PRELOAD_ENA_M  (BIT(0))
+#define EXTMEM_L1_CACHE_PRELOAD_ENA_V  0x1
+#define EXTMEM_L1_CACHE_PRELOAD_ENA_S  0
+
+#define EXTMEM_L1_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xDC)
+/* EXTMEM_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of preload on L1-Cach
+e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/
+#define EXTMEM_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOAD_ADDR_M  ((EXTMEM_L1_CACHE_PRELOAD_ADDR_V)<<(EXTMEM_L1_CACHE_PRELOAD_ADDR_S))
+#define EXTMEM_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_PRELOAD_ADDR_S  0
+
+#define EXTMEM_L1_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xE0)
+/* EXTMEM_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: Those bits are used to configure the size of the first section of prelock on L1-
+Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/
+#define EXTMEM_L1_CACHE_PRELOAD_SIZE    0x00003FFF
+#define EXTMEM_L1_CACHE_PRELOAD_SIZE_M  ((EXTMEM_L1_CACHE_PRELOAD_SIZE_V)<<(EXTMEM_L1_CACHE_PRELOAD_SIZE_S))
+#define EXTMEM_L1_CACHE_PRELOAD_SIZE_V  0x3FFF
+#define EXTMEM_L1_CACHE_PRELOAD_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x134)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (BIT(9))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (BIT(8))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/* EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0
+/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003
+#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x3
+#define EXTMEM_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/* EXTMEM_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+ ascending. 1: descending..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_M  (BIT(2))
+#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_ORDER_S  2
+/* EXTMEM_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o
+r not. 0: not finished. 1: finished..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_M  (BIT(1))
+#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_DONE_S  1
+/* EXTMEM_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable and disable autoload operation on L1-Cache.  1: enable
+, 0: disable..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_M  (BIT(0))
+#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_V  0x1
+#define EXTMEM_L1_CACHE_AUTOLOAD_ENA_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x138)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the first section
+for autoload operation on L1-Cache. Note that it should be used together with L1
+_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x13C)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
+/*description: Those bits are used to configure the size of the first section for autoload oper
+ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
+CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x140)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the second section
+ for autoload operation on L1-Cache. Note that it should be used together with L
+1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x144)
+/* EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[27:0] ;default: 28'h0 ; */
+/*description: Those bits are used to configure the size of the second section for autoload ope
+ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
+SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S))
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFFF
+#define EXTMEM_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define EXTMEM_L1_CACHE_ACS_CNT_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x158)
+/* EXTMEM_L1_DBUS_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
+1-DCache due to bus1 accesses L1-DCache..*/
+#define EXTMEM_L1_DBUS_OVF_INT_ENA    (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_ENA_M  (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_ENA_V  0x1
+#define EXTMEM_L1_DBUS_OVF_INT_ENA_S  5
+/* EXTMEM_L1_IBUS_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
+1-DCache due to bus0 accesses L1-DCache..*/
+#define EXTMEM_L1_IBUS_OVF_INT_ENA    (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_ENA_M  (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_ENA_V  0x1
+#define EXTMEM_L1_IBUS_OVF_INT_ENA_S  4
+
+#define EXTMEM_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x15C)
+/* EXTMEM_L1_DBUS_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+to bus1 accesses L1-DCache..*/
+#define EXTMEM_L1_DBUS_OVF_INT_CLR    (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_CLR_M  (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_CLR_V  0x1
+#define EXTMEM_L1_DBUS_OVF_INT_CLR_S  5
+/* EXTMEM_L1_IBUS_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+to bus0 accesses L1-DCache..*/
+#define EXTMEM_L1_IBUS_OVF_INT_CLR    (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_CLR_M  (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_CLR_V  0x1
+#define EXTMEM_L1_IBUS_OVF_INT_CLR_S  4
+
+#define EXTMEM_L1_CACHE_ACS_CNT_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x160)
+/* EXTMEM_L1_DBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
+e due to bus1 accesses L1-DCache..*/
+#define EXTMEM_L1_DBUS_OVF_INT_RAW    (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_RAW_M  (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_RAW_V  0x1
+#define EXTMEM_L1_DBUS_OVF_INT_RAW_S  5
+/* EXTMEM_L1_IBUS_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
+e due to bus0 accesses L1-DCache..*/
+#define EXTMEM_L1_IBUS_OVF_INT_RAW    (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_RAW_M  (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_RAW_V  0x1
+#define EXTMEM_L1_IBUS_OVF_INT_RAW_S  4
+
+#define EXTMEM_L1_CACHE_ACS_CNT_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x164)
+/* EXTMEM_L1_DBUS_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
+n L1-DCache due to bus1 accesses L1-DCache..*/
+#define EXTMEM_L1_DBUS_OVF_INT_ST    (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_ST_M  (BIT(5))
+#define EXTMEM_L1_DBUS_OVF_INT_ST_V  0x1
+#define EXTMEM_L1_DBUS_OVF_INT_ST_S  5
+/* EXTMEM_L1_IBUS_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
+n L1-DCache due to bus0 accesses L1-DCache..*/
+#define EXTMEM_L1_IBUS_OVF_INT_ST    (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_ST_M  (BIT(4))
+#define EXTMEM_L1_IBUS_OVF_INT_ST_V  0x1
+#define EXTMEM_L1_IBUS_OVF_INT_ST_S  4
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x168)
+/* EXTMEM_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due
+to cpu accesses L1-DCache..*/
+#define EXTMEM_L1_CACHE_FAIL_INT_ENA    (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_ENA_M  (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_FAIL_INT_ENA_S  4
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x16C)
+/* EXTMEM_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t
+o cpu accesses L1-DCache..*/
+#define EXTMEM_L1_CACHE_FAIL_INT_CLR    (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_CLR_M  (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_FAIL_INT_CLR_S  4
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x170)
+/* EXTMEM_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/
+#define EXTMEM_L1_CACHE_FAIL_INT_RAW    (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_RAW_M  (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_FAIL_INT_RAW_S  4
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x174)
+/* EXTMEM_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+to cpu accesses L1-DCache..*/
+#define EXTMEM_L1_CACHE_FAIL_INT_ST    (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
+#define EXTMEM_L1_CACHE_FAIL_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_FAIL_INT_ST_S  4
+
+#define EXTMEM_L1_CACHE_ACS_CNT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x178)
+/* EXTMEM_L1_DBUS_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus1 counter in L1-DCache..*/
+#define EXTMEM_L1_DBUS_CNT_CLR    (BIT(21))
+#define EXTMEM_L1_DBUS_CNT_CLR_M  (BIT(21))
+#define EXTMEM_L1_DBUS_CNT_CLR_V  0x1
+#define EXTMEM_L1_DBUS_CNT_CLR_S  21
+/* EXTMEM_L1_IBUS_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
+#define EXTMEM_L1_IBUS_CNT_CLR    (BIT(20))
+#define EXTMEM_L1_IBUS_CNT_CLR_M  (BIT(20))
+#define EXTMEM_L1_IBUS_CNT_CLR_V  0x1
+#define EXTMEM_L1_IBUS_CNT_CLR_S  20
+/* EXTMEM_L1_DBUS_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable dbus1 counter in L1-DCache..*/
+#define EXTMEM_L1_DBUS_CNT_ENA    (BIT(5))
+#define EXTMEM_L1_DBUS_CNT_ENA_M  (BIT(5))
+#define EXTMEM_L1_DBUS_CNT_ENA_V  0x1
+#define EXTMEM_L1_DBUS_CNT_ENA_S  5
+/* EXTMEM_L1_IBUS_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable dbus0 counter in L1-DCache..*/
+#define EXTMEM_L1_IBUS_CNT_ENA    (BIT(4))
+#define EXTMEM_L1_IBUS_CNT_ENA_M  (BIT(4))
+#define EXTMEM_L1_IBUS_CNT_ENA_V  0x1
+#define EXTMEM_L1_IBUS_CNT_ENA_S  4
+
+#define EXTMEM_L1_IBUS_ACS_HIT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1BC)
+/* EXTMEM_L1_IBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of hits when bus0 accesses L1-Cache..*/
+#define EXTMEM_L1_IBUS_HIT_CNT    0xFFFFFFFF
+#define EXTMEM_L1_IBUS_HIT_CNT_M  ((EXTMEM_L1_IBUS_HIT_CNT_V)<<(EXTMEM_L1_IBUS_HIT_CNT_S))
+#define EXTMEM_L1_IBUS_HIT_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_IBUS_HIT_CNT_S  0
+
+#define EXTMEM_L1_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C0)
+/* EXTMEM_L1_IBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of missing when bus0 accesses L1-Cache..*/
+#define EXTMEM_L1_IBUS_MISS_CNT    0xFFFFFFFF
+#define EXTMEM_L1_IBUS_MISS_CNT_M  ((EXTMEM_L1_IBUS_MISS_CNT_V)<<(EXTMEM_L1_IBUS_MISS_CNT_S))
+#define EXTMEM_L1_IBUS_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_IBUS_MISS_CNT_S  0
+
+#define EXTMEM_L1_IBUS_ACS_CONFLICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C4)
+/* EXTMEM_L1_IBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/
+#define EXTMEM_L1_IBUS_CONFLICT_CNT    0xFFFFFFFF
+#define EXTMEM_L1_IBUS_CONFLICT_CNT_M  ((EXTMEM_L1_IBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_IBUS_CONFLICT_CNT_S))
+#define EXTMEM_L1_IBUS_CONFLICT_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_IBUS_CONFLICT_CNT_S  0
+
+#define EXTMEM_L1_IBUS_ACS_NXTLVL_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1C8)
+/* EXTMEM_L1_IBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
+bus0 accessing L1-Cache..*/
+#define EXTMEM_L1_IBUS_NXTLVL_CNT    0xFFFFFFFF
+#define EXTMEM_L1_IBUS_NXTLVL_CNT_M  ((EXTMEM_L1_IBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_IBUS_NXTLVL_CNT_S))
+#define EXTMEM_L1_IBUS_NXTLVL_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_IBUS_NXTLVL_CNT_S  0
+
+#define EXTMEM_L1_DBUS_ACS_HIT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1CC)
+/* EXTMEM_L1_DBUS_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of hits when bus1 accesses L1-Cache..*/
+#define EXTMEM_L1_DBUS_HIT_CNT    0xFFFFFFFF
+#define EXTMEM_L1_DBUS_HIT_CNT_M  ((EXTMEM_L1_DBUS_HIT_CNT_V)<<(EXTMEM_L1_DBUS_HIT_CNT_S))
+#define EXTMEM_L1_DBUS_HIT_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_DBUS_HIT_CNT_S  0
+
+#define EXTMEM_L1_DBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D0)
+/* EXTMEM_L1_DBUS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of missing when bus1 accesses L1-Cache..*/
+#define EXTMEM_L1_DBUS_MISS_CNT    0xFFFFFFFF
+#define EXTMEM_L1_DBUS_MISS_CNT_M  ((EXTMEM_L1_DBUS_MISS_CNT_V)<<(EXTMEM_L1_DBUS_MISS_CNT_S))
+#define EXTMEM_L1_DBUS_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_DBUS_MISS_CNT_S  0
+
+#define EXTMEM_L1_DBUS_ACS_CONFLICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D4)
+/* EXTMEM_L1_DBUS_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/
+#define EXTMEM_L1_DBUS_CONFLICT_CNT    0xFFFFFFFF
+#define EXTMEM_L1_DBUS_CONFLICT_CNT_M  ((EXTMEM_L1_DBUS_CONFLICT_CNT_V)<<(EXTMEM_L1_DBUS_CONFLICT_CNT_S))
+#define EXTMEM_L1_DBUS_CONFLICT_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_DBUS_CONFLICT_CNT_S  0
+
+#define EXTMEM_L1_DBUS_ACS_NXTLVL_CNT_REG          (DR_REG_EXTMEM_BASE + 0x1D8)
+/* EXTMEM_L1_DBUS_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
+bus1 accessing L1-Cache..*/
+#define EXTMEM_L1_DBUS_NXTLVL_CNT    0xFFFFFFFF
+#define EXTMEM_L1_DBUS_NXTLVL_CNT_M  ((EXTMEM_L1_DBUS_NXTLVL_CNT_V)<<(EXTMEM_L1_DBUS_NXTLVL_CNT_S))
+#define EXTMEM_L1_DBUS_NXTLVL_CNT_V  0xFFFFFFFF
+#define EXTMEM_L1_DBUS_NXTLVL_CNT_S  0
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_ID_ATTR_REG          (DR_REG_EXTMEM_BASE + 0x21C)
+/* EXTMEM_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: The register records the attribution of fail-access when cache accesses L1-Cache
+..*/
+#define EXTMEM_L1_CACHE_FAIL_ATTR    0x0000FFFF
+#define EXTMEM_L1_CACHE_FAIL_ATTR_M  ((EXTMEM_L1_CACHE_FAIL_ATTR_V)<<(EXTMEM_L1_CACHE_FAIL_ATTR_S))
+#define EXTMEM_L1_CACHE_FAIL_ATTR_V  0xFFFF
+#define EXTMEM_L1_CACHE_FAIL_ATTR_S  16
+/* EXTMEM_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/
+#define EXTMEM_L1_CACHE_FAIL_ID    0x0000FFFF
+#define EXTMEM_L1_CACHE_FAIL_ID_M  ((EXTMEM_L1_CACHE_FAIL_ID_V)<<(EXTMEM_L1_CACHE_FAIL_ID_S))
+#define EXTMEM_L1_CACHE_FAIL_ID_V  0xFFFF
+#define EXTMEM_L1_CACHE_FAIL_ID_S  0
+
+#define EXTMEM_L1_CACHE_ACS_FAIL_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x220)
+/* EXTMEM_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the address of fail-access when cache accesses L1-Cache..*/
+#define EXTMEM_L1_CACHE_FAIL_ADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_FAIL_ADDR_M  ((EXTMEM_L1_CACHE_FAIL_ADDR_V)<<(EXTMEM_L1_CACHE_FAIL_ADDR_S))
+#define EXTMEM_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_FAIL_ADDR_S  0
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x224)
+/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of Cache sync-operation error..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_M  (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ENA_S  13
+/* EXTMEM_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_M  (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ENA_S  11
+/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of Cache sync-operation done..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_M  (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ENA_S  6
+/* EXTMEM_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op
+eration is done, interrupt occurs..*/
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_V  0x1
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ENA_S  4
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x228)
+/* EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of Cache sync-operation error..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_M  (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_CLR_S  13
+/* EXTMEM_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_M  (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_CLR_S  11
+/* EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ done..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_M  (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_CLR_S  6
+/* EXTMEM_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat
+ion is done..*/
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_V  0x1
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_CLR_S  4
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG          (DR_REG_EXTMEM_BASE + 0x22C)
+/* EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc
+curs..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_M  (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_RAW_S  13
+/* EXTMEM_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er
+ror occurs..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_M  (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_RAW_S  11
+/* EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_M  (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_RAW_S  6
+/* EXTMEM_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+ done..*/
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_V  0x1
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_RAW_S  4
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0x230)
+/* EXTMEM_L1_CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_M  (BIT(13))
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_ERR_INT_ST_S  13
+/* EXTMEM_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation error
+r..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_PLD_ERR_INT_ST_S  11
+/* EXTMEM_L1_CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o
+peration is done..*/
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_M  (BIT(6))
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_DONE_INT_ST_S  6
+/* EXTMEM_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre
+load-operation is done..*/
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_V  0x1
+#define EXTMEM_L1_CACHE_PLD_DONE_INT_ST_S  4
+
+#define EXTMEM_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG          (DR_REG_EXTMEM_BASE + 0x234)
+/* EXTMEM_L1_CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: The values 0-2 are available which means sync map, command conflict and size are
+ error in Cache System..*/
+#define EXTMEM_L1_CACHE_SYNC_ERR_CODE    0x00000003
+#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_M  ((EXTMEM_L1_CACHE_SYNC_ERR_CODE_V)<<(EXTMEM_L1_CACHE_SYNC_ERR_CODE_S))
+#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_V  0x3
+#define EXTMEM_L1_CACHE_SYNC_ERR_CODE_S  12
+/* EXTMEM_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/
+#define EXTMEM_L1_CACHE_PLD_ERR_CODE    0x00000003
+#define EXTMEM_L1_CACHE_PLD_ERR_CODE_M  ((EXTMEM_L1_CACHE_PLD_ERR_CODE_V)<<(EXTMEM_L1_CACHE_PLD_ERR_CODE_S))
+#define EXTMEM_L1_CACHE_PLD_ERR_CODE_V  0x3
+#define EXTMEM_L1_CACHE_PLD_ERR_CODE_S  8
+
+#define EXTMEM_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x238)
+/* EXTMEM_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
+#define EXTMEM_L1_CACHE_SYNC_RST    (BIT(4))
+#define EXTMEM_L1_CACHE_SYNC_RST_M  (BIT(4))
+#define EXTMEM_L1_CACHE_SYNC_RST_V  0x1
+#define EXTMEM_L1_CACHE_SYNC_RST_S  4
+
+#define EXTMEM_L1_CACHE_PRELOAD_RST_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x23C)
+/* EXTMEM_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+only be used to initialize preload-logic when some fatal error of preload-logic
+occurs..*/
+#define EXTMEM_L1_CACHE_PLD_RST    (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_RST_M  (BIT(4))
+#define EXTMEM_L1_CACHE_PLD_RST_V  0x1
+#define EXTMEM_L1_CACHE_PLD_RST_S  4
+
+#define EXTMEM_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x240)
+/* EXTMEM_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au
+toload will not work in L1-Cache. This bit should not be active when autoload wo
+rks in L1-Cache..*/
+#define EXTMEM_L1_CACHE_ALD_BUF_CLR    (BIT(4))
+#define EXTMEM_L1_CACHE_ALD_BUF_CLR_M  (BIT(4))
+#define EXTMEM_L1_CACHE_ALD_BUF_CLR_V  0x1
+#define EXTMEM_L1_CACHE_ALD_BUF_CLR_S  4
+
+#define EXTMEM_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_EXTMEM_BASE + 0x244)
+/* EXTMEM_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
+llocate request is responded but not completed..*/
+#define EXTMEM_L1_CACHE_UNALLOC_CLR    (BIT(4))
+#define EXTMEM_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
+#define EXTMEM_L1_CACHE_UNALLOC_CLR_V  0x1
+#define EXTMEM_L1_CACHE_UNALLOC_CLR_S  4
+
+#define EXTMEM_L1_CACHE_OBJECT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x248)
+/* EXTMEM_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi
+th the others fields inside this register..*/
+#define EXTMEM_L1_CACHE_MEM_OBJECT    (BIT(10))
+#define EXTMEM_L1_CACHE_MEM_OBJECT_M  (BIT(10))
+#define EXTMEM_L1_CACHE_MEM_OBJECT_V  0x1
+#define EXTMEM_L1_CACHE_MEM_OBJECT_S  10
+/* EXTMEM_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+h the others fields inside this register..*/
+#define EXTMEM_L1_CACHE_TAG_OBJECT    (BIT(4))
+#define EXTMEM_L1_CACHE_TAG_OBJECT_M  (BIT(4))
+#define EXTMEM_L1_CACHE_TAG_OBJECT_V  0x1
+#define EXTMEM_L1_CACHE_TAG_OBJECT_S  4
+
+#define EXTMEM_L1_CACHE_WAY_OBJECT_REG          (DR_REG_EXTMEM_BASE + 0x24C)
+/* EXTMEM_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
+: way1, 2: way2, 3: way3, ?, 7: way7..*/
+#define EXTMEM_L1_CACHE_WAY_OBJECT    0x00000007
+#define EXTMEM_L1_CACHE_WAY_OBJECT_M  ((EXTMEM_L1_CACHE_WAY_OBJECT_V)<<(EXTMEM_L1_CACHE_WAY_OBJECT_S))
+#define EXTMEM_L1_CACHE_WAY_OBJECT_V  0x7
+#define EXTMEM_L1_CACHE_WAY_OBJECT_S  0
+
+#define EXTMEM_L1_CACHE_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x250)
+/* EXTMEM_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
+/*description: Those bits stores the virtual address which will decide where inside the specified
+tag memory object will be accessed..*/
+#define EXTMEM_L1_CACHE_VADDR    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_VADDR_M  ((EXTMEM_L1_CACHE_VADDR_V)<<(EXTMEM_L1_CACHE_VADDR_S))
+#define EXTMEM_L1_CACHE_VADDR_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_VADDR_S  0
+
+#define EXTMEM_L1_CACHE_DEBUG_BUS_REG          (DR_REG_EXTMEM_BASE + 0x254)
+/* EXTMEM_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */
+/*description: This is a constant place where we can write data to or read data from the tag/da
+ta memory on the specified cache..*/
+#define EXTMEM_L1_CACHE_DEBUG_BUS    0xFFFFFFFF
+#define EXTMEM_L1_CACHE_DEBUG_BUS_M  ((EXTMEM_L1_CACHE_DEBUG_BUS_V)<<(EXTMEM_L1_CACHE_DEBUG_BUS_S))
+#define EXTMEM_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFF
+#define EXTMEM_L1_CACHE_DEBUG_BUS_S  0
+
+#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
+/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2202080 ; */
+/*description: version control register. Note that this default value stored is the latest date
+ when the hardware logic was updated..*/
+#define EXTMEM_DATE    0x0FFFFFFF
+#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
+#define EXTMEM_DATE_V  0xFFFFFFF
+#define EXTMEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/extmem_struct.h b/components/soc/esp32c6/register/soc/extmem_struct.h
new file mode 100644
index 00000000000..d43c5fcee3d
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/extmem_struct.h
@@ -0,0 +1,5747 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of l1_icache_ctrl register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+typedef union {
+    struct {
+        /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus0:1;
+        /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus1:1;
+        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus2:1;
+        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus3:1;
+        /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_undef_op:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_icache_ctrl_reg_t;
+
+/** Type of l1_cache_ctrl register
+ *  L1 data Cache(L1-Cache) control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus0:1;
+        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus1:1;
+        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus2:1;
+        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus3:1;
+        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_dma:1;
+        uint32_t reserved_5:3;
+        /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_undef_op:4;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l1_cache_ctrl_reg_t;
+
+/** Type of l2_cache_ctrl register
+ *  L2 Cache(L2-Cache) control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+         */
+        uint32_t l2_cache_shut_dma:1;
+        /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_cache_undef_op:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} extmem_l2_cache_ctrl_reg_t;
+
+
+/** Group: Bypass Cache Control and configuration registers */
+/** Type of l1_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache0_en:1;
+        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache1_en:1;
+        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache2_en:1;
+        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache3_en:1;
+        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_dcache_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_bypass_cache_conf_reg_t;
+
+/** Type of l2_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l2_cache_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_bypass_cache_conf_reg_t;
+
+
+/** Group: Cache Atomic Control and configuration registers */
+/** Type of l1_cache_atomic_conf register
+ *  L1 Cache atomic feature configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
+         *  L1-Cache.  1: disable, 1: enable.
+         */
+        uint32_t l1_cache_atomic_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} extmem_l1_cache_atomic_conf_reg_t;
+
+
+/** Group: Cache Mode Control and configuration registers */
+/** Type of l1_icache_cachesize_conf register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1k:1;
+        /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2k:1;
+        /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4k:1;
+        /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_8k:1;
+        /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_16k:1;
+        /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_32k:1;
+        /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_64k:1;
+        /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_128k:1;
+        /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256k:1;
+        /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512k:1;
+        /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1024k:1;
+        /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2048k:1;
+        /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l1_icache_cachesize_conf_reg_t;
+
+/** Type of l1_icache_blocksize_conf register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_8:1;
+        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_16:1;
+        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_32:1;
+        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_64:1;
+        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_128:1;
+        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache_blocksize_conf_reg_t;
+
+/** Type of l1_cache_cachesize_conf register
+ *  L1 data Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1k:1;
+        /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2k:1;
+        /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4k:1;
+        /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_8k:1;
+        /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_16k:1;
+        /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1;
+         *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_32k:1;
+        /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_64k:1;
+        /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_128k:1;
+        /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_256k:1;
+        /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_512k:1;
+        /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1024k:1;
+        /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2048k:1;
+        /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l1_cache_cachesize_conf_reg_t;
+
+/** Type of l1_cache_blocksize_conf register
+ *  L1 data Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_8:1;
+        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_16:1;
+        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
+         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_32:1;
+        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_64:1;
+        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_128:1;
+        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_cache_blocksize_conf_reg_t;
+
+/** Type of l2_cache_cachesize_conf register
+ *  L2 Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1k:1;
+        /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2k:1;
+        /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4k:1;
+        /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_8k:1;
+        /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_16k:1;
+        /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_32k:1;
+        /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_64k:1;
+        /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_128k:1;
+        /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256k:1;
+        /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512k:1;
+        /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1024k:1;
+        /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2048k:1;
+        /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_cachesize_conf_reg_t;
+
+/** Type of l2_cache_blocksize_conf register
+ *  L2 Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_8:1;
+        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_16:1;
+        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_32:1;
+        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_64:1;
+        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_128:1;
+        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_blocksize_conf_reg_t;
+
+
+/** Group: Wrap Mode Control and configuration registers */
+/** Type of l1_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+         */
+        uint32_t l1_icache0_wrap:1;
+        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+         */
+        uint32_t l1_icache1_wrap:1;
+        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_wrap:1;
+        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_wrap:1;
+        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to enable L1-DCache wrap around mode.
+         */
+        uint32_t l1_cache_wrap:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_wrap_around_ctrl_reg_t;
+
+/** Type of l2_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to enable L2-Cache wrap around mode.
+         */
+        uint32_t l2_cache_wrap:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_wrap_around_ctrl_reg_t;
+
+
+/** Group: Cache Tag Memory Power Control registers */
+/** Type of l1_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_tag_mem_force_on:1;
+        /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_tag_mem_force_pd:1;
+        /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_tag_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_tag_mem_force_on:1;
+        /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_tag_mem_force_pd:1;
+        /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_tag_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_on:1;
+        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pd:1;
+        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_on:1;
+        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pd:1;
+        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_cache_tag_mem_force_on:1;
+        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l1_cache_tag_mem_force_pd:1;
+        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_cache_tag_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_tag_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_tag_mem_force_on:1;
+        /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l2_cache_tag_mem_force_pd:1;
+        /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0;
+         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_tag_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_tag_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Power Control registers */
+/** Type of l1_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_data_mem_force_on:1;
+        /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_data_mem_force_pd:1;
+        /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_data_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_data_mem_force_on:1;
+        /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_data_mem_force_pd:1;
+        /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_data_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_on:1;
+        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pd:1;
+        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_on:1;
+        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pd:1;
+        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_cache_data_mem_force_on:1;
+        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_cache_data_mem_force_pd:1;
+        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_cache_data_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_data_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_data_mem_force_on:1;
+        /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l2_cache_data_mem_force_pd:1;
+        /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0;
+         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_data_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_data_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Freeze Control registers */
+/** Type of l1_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache0_freeze_en:1;
+        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache0_freeze_mode:1;
+        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_freeze_done:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache1_freeze_en:1;
+        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache1_freeze_mode:1;
+        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_freeze_done:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_en:1;
+        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_mode:1;
+        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_done:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_en:1;
+        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_mode:1;
+        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_done:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_cache_freeze_en:1;
+        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_cache_freeze_mode:1;
+        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_freeze_done:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_freeze_ctrl_reg_t;
+
+/** Type of l2_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l2_cache_freeze_en:1;
+        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l2_cache_freeze_mode:1;
+        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_freeze_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_freeze_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Access Control and Configuration registers */
+/** Type of l1_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_data_mem_rd_en:1;
+        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache0_data_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_data_mem_rd_en:1;
+        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache1_data_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_rd_en:1;
+        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_rd_en:1;
+        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_rd_en:1;
+        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} extmem_l1_cache_data_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_rd_en:1;
+        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} extmem_l2_cache_data_mem_acs_conf_reg_t;
+
+
+/** Group: Cache Tag Memory Access Control and Configuration registers */
+/** Type of l1_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_rd_en:1;
+        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_rd_en:1;
+        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_rd_en:1;
+        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_rd_en:1;
+        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_rd_en:1;
+        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} extmem_l1_cache_tag_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_rd_en:1;
+        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} extmem_l2_cache_tag_mem_acs_conf_reg_t;
+
+
+/** Group: Prelock Control and configuration registers */
+/** Type of l1_icache0_prelock_conf register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct0_en:1;
+        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct1_en:1;
+        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 prelock.
+         */
+        uint32_t l1_icache0_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_conf_reg_t;
+
+/** Type of l1_icache0_prelock_sct0_addr register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct1_addr register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct_size register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct_size_reg_t;
+
+/** Type of l1_icache1_prelock_conf register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct0_en:1;
+        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct1_en:1;
+        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 prelock.
+         */
+        uint32_t l1_icache1_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_conf_reg_t;
+
+/** Type of l1_icache1_prelock_sct0_addr register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct1_addr register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct_size register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct_size_reg_t;
+
+/** Type of l1_icache2_prelock_conf register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct0_en:1;
+        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct1_en:1;
+        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 prelock.
+         */
+        uint32_t l1_icache2_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_conf_reg_t;
+
+/** Type of l1_icache2_prelock_sct0_addr register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct1_addr register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct_size register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct_size_reg_t;
+
+/** Type of l1_icache3_prelock_conf register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct0_en:1;
+        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct1_en:1;
+        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 prelock.
+         */
+        uint32_t l1_icache3_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_conf_reg_t;
+
+/** Type of l1_icache3_prelock_sct0_addr register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct1_addr register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct_size register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct_size_reg_t;
+
+/** Type of l1_cache_prelock_conf register
+ *  L1 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct0_en:1;
+        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct1_en:1;
+        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 cache prelock.
+         */
+        uint32_t l1_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_cache_prelock_conf_reg_t;
+
+/** Type of l1_cache_prelock_sct0_addr register
+ *  L1 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-Cache, which should be used together with
+         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct1_addr register
+ *  L1 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-Cache, which should be used together with
+         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_prelock_sct1_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct_size register
+ *  L1  Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_dcache_prelock_sct_size_reg_t;
+
+/** Type of l2_cache_prelock_conf register
+ *  L2 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct0_en:1;
+        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct1_en:1;
+        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l2 cache prelock.
+         */
+        uint32_t l2_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_conf_reg_t;
+
+/** Type of l2_cache_prelock_sct0_addr register
+ *  L2 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct1_addr register
+ *  L2 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct1_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct_size register
+ *  L2 Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct0_size:16;
+        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct1_size:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct_size_reg_t;
+
+
+/** Group: Lock Control and configuration registers */
+/** Type of cache_lock_ctrl register
+ *  Lock-class (manual lock) operation control register
+ */
+typedef union {
+    struct {
+        /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+         *  operation done
+         */
+        uint32_t cache_lock_ena:1;
+        /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable unlock operation. It will be cleared by hardware after
+         *  unlock operation done
+         */
+        uint32_t cache_unlock_ena:1;
+        /** cache_lock_done : RO; bitpos: [2]; default: 1;
+         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+         *  not finished. 1: finished.
+         */
+        uint32_t cache_lock_done:1;
+        /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of cache lock/unlock.
+         */
+        uint32_t cache_lock_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_cache_lock_ctrl_reg_t;
+
+/** Type of cache_lock_map register
+ *  Lock (manual lock) map configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_map : R/W; bitpos: [5:0]; default: 0;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply this lock/unlock operation. [4]: L1-Cache
+         */
+        uint32_t cache_lock_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_cache_lock_map_reg_t;
+
+/** Type of cache_lock_addr register
+ *  Lock (manual lock) address configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the lock/unlock
+         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+         */
+        uint32_t cache_lock_addr:32;
+    };
+    uint32_t val;
+} extmem_cache_lock_addr_reg_t;
+
+/** Type of cache_lock_size register
+ *  Lock (manual lock) size configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the lock/unlock operation, which
+         *  should be used together with CACHE_LOCK_ADDR_REG
+         */
+        uint32_t cache_lock_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_cache_lock_size_reg_t;
+
+
+/** Group: Sync Control and configuration registers */
+/** Type of cache_sync_ctrl register
+ *  Sync-class operation control register
+ */
+typedef union {
+    struct {
+        /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
+         *  The bit is used to enable invalidate operation. It will be cleared by hardware
+         *  after invalidate operation done. Note that this bit and the other sync-bits
+         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_invalidate_ena:1;
+        /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable clean operation. It will be cleared by hardware after
+         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+         *  bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_clean_ena:1;
+        /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0;
+         *  The bit is used to enable writeback operation. It will be cleared by hardware after
+         *  writeback operation done. Note that this bit and the other sync-bits
+         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_writeback_ena:1;
+        /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
+         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+         *  hardware after writeback-invalidate operation done. Note that this bit and the
+         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_writeback_invalidate_ena:1;
+        /** cache_sync_done : RO; bitpos: [4]; default: 0;
+         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+         */
+        uint32_t cache_sync_done:1;
+        /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0;
+         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+         *  writeback, writeback_invalidate)
+         */
+        uint32_t cache_sync_rgid:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} extmem_cache_sync_ctrl_reg_t;
+
+/** Type of cache_sync_map register
+ *  Sync map configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_map : R/W; bitpos: [5:0]; default: 63;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply the sync operation.  [4]: L1-Cache
+         */
+        uint32_t cache_sync_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_cache_sync_map_reg_t;
+
+/** Type of cache_sync_addr register
+ *  Sync address configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the sync operation,
+         *  which should be used together with CACHE_SYNC_SIZE_REG
+         */
+        uint32_t cache_sync_addr:32;
+    };
+    uint32_t val;
+} extmem_cache_sync_addr_reg_t;
+
+/** Type of cache_sync_size register
+ *  Sync size configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_size : R/W; bitpos: [23:0]; default: 0;
+         *  Those bits are used to configure the size of the sync operation, which should be
+         *  used together with CACHE_SYNC_ADDR_REG
+         */
+        uint32_t cache_sync_size:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} extmem_cache_sync_size_reg_t;
+
+
+/** Group: Preload Control and configuration registers */
+/** Type of l1_icache0_preload_ctrl register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache0_preload_ena:1;
+        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache0_preload_done:1;
+        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache0_preload_order:1;
+        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 preload.
+         */
+        uint32_t l1_icache0_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_ctrl_reg_t;
+
+/** Type of l1_icache0_preload_addr register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache0_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_addr_reg_t;
+
+/** Type of l1_icache0_preload_size register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache0_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_size_reg_t;
+
+/** Type of l1_icache1_preload_ctrl register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache1_preload_ena:1;
+        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache1_preload_done:1;
+        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache1_preload_order:1;
+        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 preload.
+         */
+        uint32_t l1_icache1_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_ctrl_reg_t;
+
+/** Type of l1_icache1_preload_addr register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache1_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_addr_reg_t;
+
+/** Type of l1_icache1_preload_size register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache1_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_size_reg_t;
+
+/** Type of l1_icache2_preload_ctrl register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache2_preload_ena:1;
+        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache2_preload_done:1;
+        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache2_preload_order:1;
+        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 preload.
+         */
+        uint32_t l1_icache2_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_ctrl_reg_t;
+
+/** Type of l1_icache2_preload_addr register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache2_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_addr_reg_t;
+
+/** Type of l1_icache2_preload_size register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache2_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_size_reg_t;
+
+/** Type of l1_icache3_preload_ctrl register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache3_preload_ena:1;
+        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache3_preload_done:1;
+        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache3_preload_order:1;
+        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 preload.
+         */
+        uint32_t l1_icache3_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_ctrl_reg_t;
+
+/** Type of l1_icache3_preload_addr register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache3_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_addr_reg_t;
+
+/** Type of l1_icache3_preload_size register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache3_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_size_reg_t;
+
+/** Type of l1_cache_preload_ctrl register
+ *  L1 Cache  preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_cache_preload_ena:1;
+        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_cache_preload_done:1;
+        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_cache_preload_order:1;
+        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 cache preload.
+         */
+        uint32_t l1_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_cache_preload_ctrl_reg_t;
+
+/** Type of l1_dcache_preload_addr register
+ *  L1 Cache  preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
+         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_cache_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_preload_addr_reg_t;
+
+/** Type of l1_dcache_preload_size register
+ *  L1 Cache  preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_cache_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_dcache_preload_size_reg_t;
+
+/** Type of l2_cache_preload_ctrl register
+ *  L2 Cache preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l2_cache_preload_ena:1;
+        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l2_cache_preload_done:1;
+        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l2_cache_preload_order:1;
+        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l2 cache preload.
+         */
+        uint32_t l2_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_ctrl_reg_t;
+
+/** Type of l2_cache_preload_addr register
+ *  L2 Cache preload address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l2_cache_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_addr_reg_t;
+
+/** Type of l2_cache_preload_size register
+ *  L2 Cache preload size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l2_cache_preload_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_size_reg_t;
+
+
+/** Group: Autoload Control and configuration registers */
+/** Type of l1_icache0_autoload_ctrl register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache0_autoload_ena:1;
+        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_autoload_done:1;
+        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache0_autoload_order:1;
+        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache0_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct0_ena:1;
+        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct1_ena:1;
+        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 autoload.
+         */
+        uint32_t l1_icache0_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_ctrl_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_addr register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_size register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_addr register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_size register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache1_autoload_ctrl register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache1_autoload_ena:1;
+        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_autoload_done:1;
+        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache1_autoload_order:1;
+        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache1_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct0_ena:1;
+        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct1_ena:1;
+        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 autoload.
+         */
+        uint32_t l1_icache1_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_ctrl_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_addr register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_size register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_addr register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_size register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache2_autoload_ctrl register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache2_autoload_ena:1;
+        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache2_autoload_done:1;
+        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache2_autoload_order:1;
+        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache2_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct0_ena:1;
+        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct1_ena:1;
+        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 autoload.
+         */
+        uint32_t l1_icache2_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_ctrl_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_addr register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_size register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_addr register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_size register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache3_autoload_ctrl register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache3_autoload_ena:1;
+        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache3_autoload_done:1;
+        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache3_autoload_order:1;
+        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache3_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct0_ena:1;
+        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct1_ena:1;
+        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 autoload.
+         */
+        uint32_t l1_icache3_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_ctrl_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_addr register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_size register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_addr register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_size register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_ctrl register
+ *  L1 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_cache_autoload_ena:1;
+        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_autoload_done:1;
+        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_cache_autoload_order:1;
+        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct0_ena:1;
+        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct1_ena:1;
+        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct2_ena:1;
+        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct3_ena:1;
+        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l1 cache autoload.
+         */
+        uint32_t l1_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_ctrl_reg_t;
+
+/** Type of l1_cache_autoload_sct0_addr register
+ *  L1 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct0_size register
+ *  L1 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct0_size_reg_t;
+
+/** Type of l1_cache_autoload_sct1_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct1_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_sct2_addr register
+ *  L1 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct2_size register
+ *  L1 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct2_size_reg_t;
+
+/** Type of l1_cache_autoload_sct3_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct3_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct3_size_reg_t;
+
+/** Type of l2_cache_autoload_ctrl register
+ *  L2 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l2_cache_autoload_ena:1;
+        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_autoload_done:1;
+        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l2_cache_autoload_order:1;
+        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l2_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct0_ena:1;
+        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct1_ena:1;
+        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct2_ena:1;
+        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct3_ena:1;
+        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l2 cache autoload.
+         */
+        uint32_t l2_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_sct0_addr register
+ *  L2 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct0_size register
+ *  L2 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct0_size_reg_t;
+
+/** Type of l2_cache_autoload_sct1_addr register
+ *  L2 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct1_size register
+ *  L2 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct1_size_reg_t;
+
+/** Type of l2_cache_autoload_sct2_addr register
+ *  L2 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct2_size register
+ *  L2 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct2_size_reg_t;
+
+/** Type of l2_cache_autoload_sct3_addr register
+ *  L2 Cache autoload section 3 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct3_size register
+ *  L2 Cache autoload section 3 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct3_size_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of l1_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_ena:1;
+        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_ena:1;
+        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_ena:1;
+        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_ena:1;
+        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_ena:1;
+        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_ena:1;
+        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_ena:1;
+        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+         *  to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_clr:1;
+        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+         *  to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_clr:1;
+        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_clr:1;
+        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_clr:1;
+        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_clr:1;
+        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_clr:1;
+        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_clr:1;
+        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+         *  due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_raw:1;
+        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+         *  due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_raw:1;
+        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+         *  due to bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_ovf_int_raw:1;
+        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+         *  due to bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_ovf_int_raw:1;
+        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_raw:1;
+        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_raw:1;
+        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_ovf_int_raw:1;
+        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_ovf_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_st:1;
+        /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_st:1;
+        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_st:1;
+        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_st:1;
+        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_st:1;
+        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_st:1;
+        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_st:1;
+        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l1_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_ena:1;
+        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_ena:1;
+        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_ena:1;
+        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_ena:1;
+        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l1_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_clr:1;
+        /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_clr:1;
+        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_clr:1;
+        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_clr:1;
+        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l1_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_raw:1;
+        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_raw:1;
+        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+         */
+        uint32_t l1_icache2_fail_int_raw:1;
+        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+         */
+        uint32_t l1_icache3_fail_int_raw:1;
+        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l1_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_int_st:1;
+        /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_int_st:1;
+        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_st:1;
+        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_st:1;
+        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+         *  to cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_st_reg_t;
+
+/** Type of l1_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache0_pld_done_int_ena:1;
+        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache1_pld_done_int_ena:1;
+        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_ena:1;
+        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_ena:1;
+        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_cache_pld_done_int_ena:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation done.
+         */
+        uint32_t cache_sync_done_int_ena:1;
+        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_ena:1;
+        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_ena:1;
+        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_ena:1;
+        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_ena:1;
+        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_ena:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l1_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_clr:1;
+        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_clr:1;
+        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_clr:1;
+        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_clr:1;
+        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l1_cache_pld_done_int_clr:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+         *  done.
+         */
+        uint32_t cache_sync_done_int_clr:1;
+        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_clr:1;
+        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_clr:1;
+        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_clr:1;
+        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_clr:1;
+        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
+         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_clr:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l1_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache0_pld_done_int_raw:1;
+        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache1_pld_done_int_raw:1;
+        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_raw:1;
+        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_raw:1;
+        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l1_cache_pld_done_int_raw:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+         */
+        uint32_t cache_sync_done_int_raw:1;
+        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache0_pld_err_int_raw:1;
+        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache1_pld_err_int_raw:1;
+        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_raw:1;
+        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_raw:1;
+        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_err_int_raw:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+         *  occurs.
+         */
+        uint32_t cache_sync_err_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l1_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_st:1;
+        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_st:1;
+        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_st:1;
+        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_st:1;
+        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l1_cache_pld_done_int_st:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when Cache
+         *  sync-operation is done.
+         */
+        uint32_t cache_sync_done_int_st:1;
+        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_st:1;
+        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_st:1;
+        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_st:1;
+        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_st:1;
+        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_st:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the status of the interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_st_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_ena:1;
+        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_ena:1;
+        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_ena:1;
+        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_ena:1;
+        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_ena:1;
+        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_ena:1;
+        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_ena:1;
+        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_clr:1;
+        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_clr:1;
+        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_clr:1;
+        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_clr:1;
+        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_clr:1;
+        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_clr:1;
+        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_clr:1;
+        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-ICache0.
+         */
+        uint32_t l2_ibus0_ovf_int_raw:1;
+        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-ICache1.
+         */
+        uint32_t l2_ibus1_ovf_int_raw:1;
+        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-ICache2.
+         */
+        uint32_t l2_ibus2_ovf_int_raw:1;
+        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-ICache3.
+         */
+        uint32_t l2_ibus3_ovf_int_raw:1;
+        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-DCache.
+         */
+        uint32_t l2_dbus0_ovf_int_raw:1;
+        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-DCache.
+         */
+        uint32_t l2_dbus1_ovf_int_raw:1;
+        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-DCache.
+         */
+        uint32_t l2_dbus2_ovf_int_raw:1;
+        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-DCache.
+         */
+        uint32_t l2_dbus3_ovf_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_st:1;
+        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_st:1;
+        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_st:1;
+        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_st:1;
+        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_st:1;
+        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_st:1;
+        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_st:1;
+        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l2_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+         *  l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l2_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+         *  cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l2_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l2_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+         *  to l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_st_reg_t;
+
+/** Type of l2_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+         */
+        uint32_t l2_cache_pld_done_int_ena:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l2_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l2_cache_pld_done_int_clr:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l2_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l2_cache_pld_done_int_raw:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_err_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l2_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l2_cache_pld_done_int_st:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_st_reg_t;
+
+
+/** Group: Access Statistics registers */
+/** Type of l1_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_ena:1;
+        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_ena:1;
+        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_ena:1;
+        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_ena:1;
+        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_ena:1;
+        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_ena:1;
+        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_ena:1;
+        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_ena:1;
+        uint32_t reserved_8:8;
+        /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0;
+         *  The bit is used to clear ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_clr:1;
+        /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0;
+         *  The bit is used to clear ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_clr:1;
+        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_clr:1;
+        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_clr:1;
+        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
+         *  The bit is used to clear dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_clr:1;
+        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
+         *  The bit is used to clear dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_clr:1;
+        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_clr:1;
+        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_clr:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l1_ibus0_acs_hit_cnt register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_miss_cnt register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_conflict_cnt register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_nxtlvl_cnt register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l1_ibus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_hit_cnt register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_miss_cnt register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_conflict_cnt register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_nxtlvl_cnt register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l1_ibus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_hit_cnt register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_miss_cnt register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_conflict_cnt register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_nxtlvl_cnt register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l1_ibus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_hit_cnt register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_miss_cnt register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_conflict_cnt register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_nxtlvl_cnt register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l1_ibus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_bus0_acs_hit_cnt register
+ *  L1-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus0_acs_miss_cnt register
+ *  L1-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus0_acs_conflict_cnt register
+ *  L1-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_bus0_acs_nxtlvl_cnt register
+ *  L1-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus0 accessing L1-Cache.
+         */
+        uint32_t l1_bus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_bus1_acs_hit_cnt register
+ *  L1-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus1_acs_miss_cnt register
+ *  L1-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus1_acs_conflict_cnt register
+ *  L1-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_bus1_acs_nxtlvl_cnt register
+ *  L1-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus1 accessing L1-Cache.
+         */
+        uint32_t l1_bus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_hit_cnt register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_miss_cnt register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_conflict_cnt register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_cnt register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_hit_cnt register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_miss_cnt register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_conflict_cnt register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_cnt register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_ena:1;
+        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_ena:1;
+        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_ena:1;
+        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_ena:1;
+        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_ena:1;
+        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_ena:1;
+        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_ena:1;
+        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_ena:1;
+        uint32_t reserved_16:8;
+        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
+         *  The bit is used to clear ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_clr:1;
+        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
+         *  The bit is used to clear ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_clr:1;
+        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_clr:1;
+        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_clr:1;
+        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
+         *  The bit is used to clear dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_clr:1;
+        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
+         *  The bit is used to clear dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_clr:1;
+        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_clr:1;
+        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_clr:1;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l2_ibus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache0 accesses
+         *  L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_nxtlvl_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache1 accesses
+         *  L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_nxtlvl_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache2 accesses
+         *  L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_nxtlvl_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache3 accesses
+         *  L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_nxtlvl_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t;
+
+
+/** Group: Access Fail Debug registers */
+/** Type of l1_icache0_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_id:16;
+        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache0_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache0_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_acs_fail_addr_reg_t;
+
+/** Type of l1_icache1_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_id:16;
+        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache1_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache1_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_acs_fail_addr_reg_t;
+
+/** Type of l1_icache2_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_id:16;
+        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache2_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache2_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_acs_fail_addr_reg_t;
+
+/** Type of l1_icache3_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_id:16;
+        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache3_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache3_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_acs_fail_addr_reg_t;
+
+/** Type of l1_cache_acs_fail_id_attr register
+ *  L1-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_id:16;
+        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l1_dcache_acs_fail_addr register
+ *  L1-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_acs_fail_addr_reg_t;
+
+/** Type of l2_cache_acs_fail_id_attr register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_id:16;
+        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+         *  due to cache accessing L1-Cache.
+         */
+        uint32_t l2_cache_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l2_cache_acs_fail_addr register
+ *  L2-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_addr_reg_t;
+
+
+/** Group: Operation Exception registers */
+/** Type of l1_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache0.
+         */
+        uint32_t l1_icache0_pld_err_code:2;
+        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache1.
+         */
+        uint32_t l1_icache1_pld_err_code:2;
+        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_code:2;
+        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_code:2;
+        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-Cache.
+         */
+        uint32_t l1_cache_pld_err_code:2;
+        uint32_t reserved_10:2;
+        /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0;
+         *  The values 0-2 are available which means sync map, command conflict and size are
+         *  error in Cache System.
+         */
+        uint32_t cache_sync_err_code:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_exception_reg_t;
+
+/** Type of l2_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L2-Cache.
+         */
+        uint32_t l2_cache_pld_err_code:2;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_exception_reg_t;
+
+
+/** Group: Sync Reset control and configuration registers */
+/** Type of l1_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache0_sync_rst:1;
+        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache1_sync_rst:1;
+        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_sync_rst:1;
+        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_sync_rst:1;
+        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_cache_sync_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_rst_ctrl_reg_t;
+
+/** Type of l2_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l2_cache_sync_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_rst_ctrl_reg_t;
+
+
+/** Group: Preload Reset control and configuration registers */
+/** Type of l1_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache0_pld_rst:1;
+        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache1_pld_rst:1;
+        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_rst:1;
+        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_rst:1;
+        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_preload_rst_ctrl_reg_t;
+
+/** Type of l2_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_rst_ctrl_reg_t;
+
+
+/** Group: Autoload buffer clear control and configuration registers */
+/** Type of l1_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+         *  works in L1-ICache0.
+         */
+        uint32_t l1_icache0_ald_buf_clr:1;
+        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+         *  works in L1-ICache1.
+         */
+        uint32_t l1_icache1_ald_buf_clr:1;
+        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_ald_buf_clr:1;
+        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_ald_buf_clr:1;
+        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
+         *  autoload will not work in L1-Cache. This bit should not be active when autoload
+         *  works in L1-Cache.
+         */
+        uint32_t l1_cache_ald_buf_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
+         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+         *  autoload will not work in L2-Cache. This bit should not be active when autoload
+         *  works in L2-Cache.
+         */
+        uint32_t l2_cache_ald_buf_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t;
+
+
+/** Group: Unallocate request buffer clear registers */
+/** Type of l1_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache0_unalloc_clr:1;
+        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache1_unalloc_clr:1;
+        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_unalloc_clr:1;
+        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_unalloc_clr:1;
+        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 cache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_cache_unalloc_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_unallocate_buffer_clear_reg_t;
+
+/** Type of l2_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l2 icache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l2_cache_unalloc_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_unallocate_buffer_clear_reg_t;
+
+
+/** Group: Tag and Data Memory Access Control and configuration register */
+/** Type of l1_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0;
+         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache0_tag_object:1;
+        /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0;
+         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache1_tag_object:1;
+        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_object:1;
+        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_object:1;
+        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_tag_object:1;
+        uint32_t reserved_5:1;
+        /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0;
+         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache0_mem_object:1;
+        /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0;
+         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache1_mem_object:1;
+        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_mem_object:1;
+        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_mem_object:1;
+        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_mem_object:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} extmem_l1_cache_object_ctrl_reg_t;
+
+/** Type of l1_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l1_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} extmem_l1_cache_way_object_reg_t;
+
+/** Type of l1_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l1_cache_vaddr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_vaddr_reg_t;
+
+/** Type of l1_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l1_cache_debug_bus:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_debug_bus_reg_t;
+
+/** Type of l2_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
+         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_tag_object:1;
+        uint32_t reserved_6:5;
+        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
+         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_mem_object:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l2_cache_object_ctrl_reg_t;
+
+/** Type of l2_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l2_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} extmem_l2_cache_way_object_reg_t;
+
+/** Type of l2_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l2_cache_vaddr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_vaddr_reg_t;
+
+/** Type of l2_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l2_cache_debug_bus:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_debug_bus_reg_t;
+
+
+/** Group: Split L1 and L2 registers */
+/** Type of level_split0 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split0 : HRO; bitpos: [31:0]; default: 600;
+         *  Reserved
+         */
+        uint32_t level_split0:32;
+    };
+    uint32_t val;
+} extmem_level_split0_reg_t;
+
+/** Type of level_split1 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split1 : HRO; bitpos: [31:0]; default: 936;
+         *  Reserved
+         */
+        uint32_t level_split1:32;
+    };
+    uint32_t val;
+} extmem_level_split1_reg_t;
+
+
+/** Group: L2 cache access attribute control register */
+/** Type of l2_cache_access_attr_ctrl register
+ *  L1 Cache access Attribute propagation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
+         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+         *  non-cacheable.
+         */
+        uint32_t l2_cache_access_force_cc:1;
+        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+         *  write-through.
+         */
+        uint32_t l2_cache_access_force_wb:1;
+        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  write-miss-allocate and write-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_wma:1;
+        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
+         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  read-miss-allocate and read-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_rma:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} extmem_l2_cache_access_attr_ctrl_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} extmem_clock_gate_reg_t;
+
+
+/** Group: Redundancy  register (Prepare for ECO) */
+/** Type of redundancy_sig0 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig0:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig0_reg_t;
+
+/** Type of redundancy_sig1 register
+ *  Cache redundancy signal 1 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig1:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig1_reg_t;
+
+/** Type of redundancy_sig2 register
+ *  Cache redundancy signal 2 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig2:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig2_reg_t;
+
+/** Type of redundancy_sig3 register
+ *  Cache redundancy signal 3 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig3:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig3_reg_t;
+
+/** Type of redundancy_sig4 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} extmem_redundancy_sig4_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35659904;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_date_reg_t;
+
+
+typedef struct extmem_dev_s {
+    volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl;
+    volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl;
+    volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
+    volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
+    volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
+    volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
+    volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
+    volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
+    volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
+    volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
+    volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
+    volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
+    volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
+    volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
+    volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
+    volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
+    volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
+    volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
+    volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
+    volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
+    volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
+    volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
+    volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
+    volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
+    volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
+    volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
+    volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
+    volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
+    volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
+    volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
+    volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
+    volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
+    volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
+    volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
+    volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl;
+    volatile extmem_cache_lock_map_reg_t cache_lock_map;
+    volatile extmem_cache_lock_addr_reg_t cache_lock_addr;
+    volatile extmem_cache_lock_size_reg_t cache_lock_size;
+    volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl;
+    volatile extmem_cache_sync_map_reg_t cache_sync_map;
+    volatile extmem_cache_sync_addr_reg_t cache_sync_addr;
+    volatile extmem_cache_sync_size_reg_t cache_sync_size;
+    volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
+    volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
+    volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
+    volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
+    volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
+    volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
+    volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
+    volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
+    volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
+    volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
+    volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
+    volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
+    volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
+    volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
+    volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
+    volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
+    volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
+    volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
+    volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
+    volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
+    volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
+    volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
+    volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
+    volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
+    volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
+    volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
+    volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
+    volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
+    volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
+    volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
+    volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
+    volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
+    volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
+    volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
+    volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
+    volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
+    volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
+    volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
+    volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
+    volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
+    volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
+    volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
+    volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
+    volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
+    volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
+    volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
+    volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
+    volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
+    volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
+    volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
+    volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
+    volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
+    volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
+    volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
+    volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
+    volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
+    volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
+    volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
+    volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
+    volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
+    volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
+    volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
+    volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
+    volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
+    volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
+    volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt;
+    volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
+    volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
+    volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
+    volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt;
+    volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
+    volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
+    volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
+    volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt;
+    volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
+    volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
+    volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
+    volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt;
+    volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
+    volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
+    volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
+    volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt;
+    volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
+    volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
+    volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
+    volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
+    volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
+    volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
+    volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
+    volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
+    volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr;
+    volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
+    volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
+    volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
+    volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
+    volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
+    volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
+    volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
+    volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
+    volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
+    volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
+    volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
+    volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object;
+    volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr;
+    volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
+    volatile extmem_level_split0_reg_t level_split0;
+    volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl;
+    volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
+    volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
+    volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
+    volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
+    volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
+    volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
+    volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
+    volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
+    volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
+    volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
+    volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
+    volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
+    volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
+    volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
+    volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
+    volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size;
+    volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
+    volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
+    volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
+    volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
+    volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
+    volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
+    volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
+    volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
+    volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
+    volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
+    volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
+    volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
+    volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
+    volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
+    volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
+    volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
+    volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
+    volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
+    volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
+    volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
+    volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
+    volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
+    volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
+    volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
+    volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
+    volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
+    volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
+    volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
+    volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
+    volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
+    volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
+    volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
+    volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
+    volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
+    volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
+    volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
+    volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
+    volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
+    volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
+    volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
+    volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
+    volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
+    volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt;
+    volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
+    volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
+    volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
+    volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
+    volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
+    volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
+    volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
+    volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
+    volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
+    volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
+    volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
+    volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
+    volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
+    volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object;
+    volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr;
+    volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
+    volatile extmem_level_split1_reg_t level_split1;
+    volatile extmem_clock_gate_reg_t clock_gate;
+    volatile extmem_redundancy_sig0_reg_t redundancy_sig0;
+    volatile extmem_redundancy_sig1_reg_t redundancy_sig1;
+    volatile extmem_redundancy_sig2_reg_t redundancy_sig2;
+    volatile extmem_redundancy_sig3_reg_t redundancy_sig3;
+    volatile extmem_redundancy_sig4_reg_t redundancy_sig4;
+    uint32_t reserved_3c4[14];
+    volatile extmem_date_reg_t date;
+} extmem_dev_t;
+
+extern extmem_dev_t EXTMEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/gdma_reg.h b/components/soc/esp32c6/register/soc/gdma_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gdma_reg.h
rename to components/soc/esp32c6/register/soc/gdma_reg.h
diff --git a/components/soc/esp32c6/include/soc/gdma_struct.h b/components/soc/esp32c6/register/soc/gdma_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gdma_struct.h
rename to components/soc/esp32c6/register/soc/gdma_struct.h
diff --git a/components/soc/esp32c6/include/soc/gpio_ext_reg.h b/components/soc/esp32c6/register/soc/gpio_ext_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gpio_ext_reg.h
rename to components/soc/esp32c6/register/soc/gpio_ext_reg.h
diff --git a/components/soc/esp32c6/include/soc/gpio_ext_struct.h b/components/soc/esp32c6/register/soc/gpio_ext_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gpio_ext_struct.h
rename to components/soc/esp32c6/register/soc/gpio_ext_struct.h
diff --git a/components/soc/esp32c6/include/soc/gpio_reg.h b/components/soc/esp32c6/register/soc/gpio_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gpio_reg.h
rename to components/soc/esp32c6/register/soc/gpio_reg.h
diff --git a/components/soc/esp32c6/include/soc/gpio_struct.h b/components/soc/esp32c6/register/soc/gpio_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/gpio_struct.h
rename to components/soc/esp32c6/register/soc/gpio_struct.h
diff --git a/components/soc/esp32c6/include/soc/hardware_lock_reg.h b/components/soc/esp32c6/register/soc/hardware_lock_reg.h
similarity index 93%
rename from components/soc/esp32c6/include/soc/hardware_lock_reg.h
rename to components/soc/esp32c6/register/soc/hardware_lock_reg.h
index a9fbfb8cb06..a80313138c4 100644
--- a/components/soc/esp32c6/include/soc/hardware_lock_reg.h
+++ b/components/soc/esp32c6/register/soc/hardware_lock_reg.h
@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** ATOMIC_ADDR_LOCK_REG register
- *  hardware lock regsiter
+ *  hardware lock register
  */
 #define ATOMIC_ADDR_LOCK_REG (DR_REG_ATOMIC_BASE + 0x0)
 /** ATOMIC_LOCK : R/W; bitpos: [1:0]; default: 0;
@@ -24,7 +24,7 @@ extern "C" {
 #define ATOMIC_LOCK_S  0
 
 /** ATOMIC_LR_ADDR_REG register
- *  gloable lr address regsiter
+ *  gloable lr address register
  */
 #define ATOMIC_LR_ADDR_REG (DR_REG_ATOMIC_BASE + 0x4)
 /** ATOMIC_GLOABLE_LR_ADDR : R/W; bitpos: [31:0]; default: 0;
@@ -36,7 +36,7 @@ extern "C" {
 #define ATOMIC_GLOABLE_LR_ADDR_S  0
 
 /** ATOMIC_LR_VALUE_REG register
- *  gloable lr value regsiter
+ *  gloable lr value register
  */
 #define ATOMIC_LR_VALUE_REG (DR_REG_ATOMIC_BASE + 0x8)
 /** ATOMIC_GLOABLE_LR_VALUE : R/W; bitpos: [31:0]; default: 0;
@@ -48,11 +48,11 @@ extern "C" {
 #define ATOMIC_GLOABLE_LR_VALUE_S  0
 
 /** ATOMIC_LOCK_STATUS_REG register
- *  lock status regsiter
+ *  lock status register
  */
 #define ATOMIC_LOCK_STATUS_REG (DR_REG_ATOMIC_BASE + 0xc)
 /** ATOMIC_LOCK_STATUS : RO; bitpos: [1:0]; default: 0;
- *  read hareware lock status for debug
+ *  read hardware lock status for debug
  */
 #define ATOMIC_LOCK_STATUS    0x00000003U
 #define ATOMIC_LOCK_STATUS_M  (ATOMIC_LOCK_STATUS_V << ATOMIC_LOCK_STATUS_S)
diff --git a/components/soc/esp32c6/include/soc/hardware_lock_struct.h b/components/soc/esp32c6/register/soc/hardware_lock_struct.h
similarity index 92%
rename from components/soc/esp32c6/include/soc/hardware_lock_struct.h
rename to components/soc/esp32c6/register/soc/hardware_lock_struct.h
index 0430212e50d..cbea0bebea0 100644
--- a/components/soc/esp32c6/include/soc/hardware_lock_struct.h
+++ b/components/soc/esp32c6/register/soc/hardware_lock_struct.h
@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of addr_lock register
- *  hardware lock regsiter
+ *  hardware lock register
  */
 typedef union {
     struct {
@@ -26,7 +26,7 @@ typedef union {
 } atomic_addr_lock_reg_t;
 
 /** Type of lr_addr register
- *  gloable lr address regsiter
+ *  gloable lr address register
  */
 typedef union {
     struct {
@@ -39,7 +39,7 @@ typedef union {
 } atomic_lr_addr_reg_t;
 
 /** Type of lr_value register
- *  gloable lr value regsiter
+ *  gloable lr value register
  */
 typedef union {
     struct {
@@ -52,12 +52,12 @@ typedef union {
 } atomic_lr_value_reg_t;
 
 /** Type of lock_status register
- *  lock status regsiter
+ *  lock status register
  */
 typedef union {
     struct {
         /** lock_status : RO; bitpos: [1:0]; default: 0;
-         *  read hareware lock status for debug
+         *  read hardware lock status for debug
          */
         uint32_t lock_status:2;
         uint32_t reserved_2:30;
diff --git a/components/soc/esp32c6/include/soc/hinf_reg.h b/components/soc/esp32c6/register/soc/hinf_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hinf_reg.h
rename to components/soc/esp32c6/register/soc/hinf_reg.h
diff --git a/components/soc/esp32c6/include/soc/hinf_struct.h b/components/soc/esp32c6/register/soc/hinf_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hinf_struct.h
rename to components/soc/esp32c6/register/soc/hinf_struct.h
diff --git a/components/soc/esp32c6/include/soc/hmac_reg.h b/components/soc/esp32c6/register/soc/hmac_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hmac_reg.h
rename to components/soc/esp32c6/register/soc/hmac_reg.h
diff --git a/components/soc/esp32c6/include/soc/hmac_struct.h b/components/soc/esp32c6/register/soc/hmac_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hmac_struct.h
rename to components/soc/esp32c6/register/soc/hmac_struct.h
diff --git a/components/soc/esp32c6/include/soc/host_reg.h b/components/soc/esp32c6/register/soc/host_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/host_reg.h
rename to components/soc/esp32c6/register/soc/host_reg.h
diff --git a/components/soc/esp32c6/include/soc/host_struct.h b/components/soc/esp32c6/register/soc/host_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/host_struct.h
rename to components/soc/esp32c6/register/soc/host_struct.h
diff --git a/components/soc/esp32c6/include/soc/hp_apm_reg.h b/components/soc/esp32c6/register/soc/hp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hp_apm_reg.h
rename to components/soc/esp32c6/register/soc/hp_apm_reg.h
diff --git a/components/soc/esp32c6/include/soc/hp_apm_struct.h b/components/soc/esp32c6/register/soc/hp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/hp_apm_struct.h
rename to components/soc/esp32c6/register/soc/hp_apm_struct.h
diff --git a/components/soc/esp32c6/register/soc/hp_system_reg.h b/components/soc/esp32c6/register/soc/hp_system_reg.h
new file mode 100644
index 00000000000..f32f280f237
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/hp_system_reg.h
@@ -0,0 +1,415 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
+ *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
+ */
+#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
+/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
+ */
+#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
+#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
+ *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
+ */
+#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
+#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
+#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
+ *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
+ */
+#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+
+/** HP_SYSTEM_SRAM_USAGE_CONF_REG register
+ *  HP memory usage configuration register
+ */
+#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
+/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define HP_SYSTEM_CACHE_USAGE    (BIT(0))
+#define HP_SYSTEM_CACHE_USAGE_M  (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
+#define HP_SYSTEM_CACHE_USAGE_V  0x00000001U
+#define HP_SYSTEM_CACHE_USAGE_S  0
+/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [11:8]; default: 0;
+ *  0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
+ */
+#define HP_SYSTEM_SRAM_USAGE    0x0000000FU
+#define HP_SYSTEM_SRAM_USAGE_M  (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S)
+#define HP_SYSTEM_SRAM_USAGE_V  0x0000000FU
+#define HP_SYSTEM_SRAM_USAGE_S  8
+/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0;
+ *  Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
+ */
+#define HP_SYSTEM_MAC_DUMP_ALLOC    (BIT(16))
+#define HP_SYSTEM_MAC_DUMP_ALLOC_M  (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S)
+#define HP_SYSTEM_MAC_DUMP_ALLOC_V  0x00000001U
+#define HP_SYSTEM_MAC_DUMP_ALLOC_S  16
+
+/** HP_SYSTEM_SEC_DPA_CONF_REG register
+ *  HP anti-DPA security configuration register
+ */
+#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
+/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
+ *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
+ *  the number, the stronger the ability to resist DPA attacks and the higher the
+ *  security level, but it will increase the computational overhead of the hardware
+ *  crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
+ */
+#define HP_SYSTEM_SEC_DPA_LEVEL    0x00000003U
+#define HP_SYSTEM_SEC_DPA_LEVEL_M  (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
+#define HP_SYSTEM_SEC_DPA_LEVEL_V  0x00000003U
+#define HP_SYSTEM_SEC_DPA_LEVEL_S  0
+/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
+ *  This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
+ *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
+ */
+#define HP_SYSTEM_SEC_DPA_CFG_SEL    (BIT(2))
+#define HP_SYSTEM_SEC_DPA_CFG_SEL_M  (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
+#define HP_SYSTEM_SEC_DPA_CFG_SEL_V  0x00000001U
+#define HP_SYSTEM_SEC_DPA_CFG_SEL_S  2
+
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
+ *  CPU_PERI_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc)
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Set the timeout threshold for bus access, corresponding to the number of clock
+ *  cycles of the clock domain.
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
+ *  Set this bit as 1 to clear timeout interrupt
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S  16
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
+ *  registers
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
+ *  CPU_PERI_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10)
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Record the address information of abnormal access
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
+ *  CPU_PERI_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14)
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
+ *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+ *  will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID    0x0000007FU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V  0x0000007FU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
+ *  HP_PERI_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18)
+/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Set the timeout threshold for bus access, corresponding to the number of clock
+ *  cycles of the clock domain.
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
+ *  Set this bit as 1 to clear timeout interrupt
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
+#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
+#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S  16
+/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
+ *  HP_PERI_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c)
+/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Record the address information of abnormal access
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
+ *  HP_PERI_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20)
+/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
+ *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+ *  will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID    0x0000007FU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M  (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V  0x0000007FU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register
+ *  MODEM_PERI_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
+/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Set the timeout threshold for bus access, corresponding to the number of clock
+ *  cycles of the clock domain.
+ */
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S)
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
+ *  Set this bit as 1 to clear timeout interrupt
+ */
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S  16
+/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Set this bit as 1 to enable timeout protection for accessing modem registers
+ */
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register
+ *  MODEM_PERI_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
+/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Record the address information of abnormal access
+ */
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register
+ *  MODEM_PERI_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
+/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
+ *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+ *  will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID    0x0000007FU
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M  (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S)
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V  0x0000007FU
+#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_SDIO_CTRL_REG register
+ *  SDIO Control configuration register
+ */
+#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x30)
+/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1;
+ *  Set this bit as 1 to disable SDIO_PROB function. disable by default.
+ */
+#define HP_SYSTEM_DIS_SDIO_PROB    (BIT(0))
+#define HP_SYSTEM_DIS_SDIO_PROB_M  (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S)
+#define HP_SYSTEM_DIS_SDIO_PROB_V  0x00000001U
+#define HP_SYSTEM_DIS_SDIO_PROB_S  0
+/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1;
+ *  Enable sdio slave to access other peripherals on the chip
+ */
+#define HP_SYSTEM_SDIO_WIN_ACCESS_EN    (BIT(1))
+#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M  (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S)
+#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V  0x00000001U
+#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S  1
+
+/** HP_SYSTEM_RETENTION_CONF_REG register
+ *  Retention configuration register
+ */
+#define HP_SYSTEM_RETENTION_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x34)
+/** HP_SYSTEM_RETENTION_DISABLE : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to disable retention function. Not disable by default.
+ */
+#define HP_SYSTEM_RETENTION_DISABLE    (BIT(0))
+#define HP_SYSTEM_RETENTION_DISABLE_M  (HP_SYSTEM_RETENTION_DISABLE_V << HP_SYSTEM_RETENTION_DISABLE_S)
+#define HP_SYSTEM_RETENTION_DISABLE_V  0x00000001U
+#define HP_SYSTEM_RETENTION_DISABLE_S  0
+
+/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
+ *  Rom-Table lock register
+ */
+#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x38)
+/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
+ *  XXXX
+ */
+#define HP_SYSTEM_ROM_TABLE_LOCK    (BIT(0))
+#define HP_SYSTEM_ROM_TABLE_LOCK_M  (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
+#define HP_SYSTEM_ROM_TABLE_LOCK_V  0x00000001U
+#define HP_SYSTEM_ROM_TABLE_LOCK_S  0
+
+/** HP_SYSTEM_ROM_TABLE_REG register
+ *  Rom-Table register
+ */
+#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x3c)
+/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
+ *  XXXX
+ */
+#define HP_SYSTEM_ROM_TABLE    0xFFFFFFFFU
+#define HP_SYSTEM_ROM_TABLE_M  (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
+#define HP_SYSTEM_ROM_TABLE_V  0xFFFFFFFFU
+#define HP_SYSTEM_ROM_TABLE_S  0
+
+/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
+ *  Core Debug runstall configure register
+ */
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x40)
+/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+ */
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S  0
+
+/** HP_SYSTEM_MEM_TEST_CONF_REG register
+ *  MEM_TEST configuration register
+ */
+#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x44)
+/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
+ *  This field controls hp system memory WPULSE parameter.
+ */
+#define HP_SYSTEM_HP_MEM_WPULSE    0x00000007U
+#define HP_SYSTEM_HP_MEM_WPULSE_M  (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S)
+#define HP_SYSTEM_HP_MEM_WPULSE_V  0x00000007U
+#define HP_SYSTEM_HP_MEM_WPULSE_S  0
+/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 4;
+ *  This field controls hp system memory WA parameter.
+ */
+#define HP_SYSTEM_HP_MEM_WA    0x00000007U
+#define HP_SYSTEM_HP_MEM_WA_M  (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S)
+#define HP_SYSTEM_HP_MEM_WA_V  0x00000007U
+#define HP_SYSTEM_HP_MEM_WA_S  3
+/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
+ *  This field controls hp system memory RA parameter.
+ */
+#define HP_SYSTEM_HP_MEM_RA    0x00000003U
+#define HP_SYSTEM_HP_MEM_RA_M  (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S)
+#define HP_SYSTEM_HP_MEM_RA_V  0x00000003U
+#define HP_SYSTEM_HP_MEM_RA_S  6
+
+/** HP_SYSTEM_RND_ECO_REG register
+ *  redcy eco register.
+ */
+#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0)
+/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define HP_SYSTEM_REDCY_ENA    (BIT(0))
+#define HP_SYSTEM_REDCY_ENA_M  (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
+#define HP_SYSTEM_REDCY_ENA_V  0x00000001U
+#define HP_SYSTEM_REDCY_ENA_S  0
+/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define HP_SYSTEM_REDCY_RESULT    (BIT(1))
+#define HP_SYSTEM_REDCY_RESULT_M  (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
+#define HP_SYSTEM_REDCY_RESULT_V  0x00000001U
+#define HP_SYSTEM_REDCY_RESULT_S  1
+
+/** HP_SYSTEM_RND_ECO_LOW_REG register
+ *  redcy eco low register.
+ */
+#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4)
+/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define HP_SYSTEM_REDCY_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REDCY_LOW_M  (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
+#define HP_SYSTEM_REDCY_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REDCY_LOW_S  0
+
+/** HP_SYSTEM_RND_ECO_HIGH_REG register
+ *  redcy eco high register.
+ */
+#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8)
+/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
+ *  Only reserved for ECO.
+ */
+#define HP_SYSTEM_REDCY_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REDCY_HIGH_M  (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
+#define HP_SYSTEM_REDCY_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REDCY_HIGH_S  0
+
+/** HP_SYSTEM_CLOCK_GATE_REG register
+ *  HP-SYSTEM clock gating configure register
+ */
+#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8)
+/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to force on clock gating.
+ */
+#define HP_SYSTEM_CLK_EN    (BIT(0))
+#define HP_SYSTEM_CLK_EN_M  (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)
+#define HP_SYSTEM_CLK_EN_V  0x00000001U
+#define HP_SYSTEM_CLK_EN_S  0
+
+/** HP_SYSTEM_DATE_REG register
+ *  Date register.
+ */
+#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
+/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 35676432;
+ *  HP-SYSTEM date information/ HP-SYSTEM version information.
+ */
+#define HP_SYSTEM_DATE    0x0FFFFFFFU
+#define HP_SYSTEM_DATE_M  (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
+#define HP_SYSTEM_DATE_V  0x0FFFFFFFU
+#define HP_SYSTEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/hp_system_struct.h b/components/soc/esp32c6/register/soc/hp_system_struct.h
new file mode 100644
index 00000000000..20b8eac2f88
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/hp_system_struct.h
@@ -0,0 +1,450 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of external_device_encrypt_decrypt_control register
+ *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
+ */
+typedef union {
+    struct {
+        /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
+         */
+        uint32_t enable_spi_manual_encrypt:1;
+        /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t enable_download_db_encrypt:1;
+        /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
+         *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
+         */
+        uint32_t enable_download_g0cb_decrypt:1;
+        /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
+         *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
+         */
+        uint32_t enable_download_manual_encrypt:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_external_device_encrypt_decrypt_control_reg_t;
+
+/** Type of sram_usage_conf register
+ *  HP memory usage configuration register
+ */
+typedef union {
+    struct {
+        /** cache_usage : HRO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t cache_usage:1;
+        uint32_t reserved_1:7;
+        /** sram_usage : R/W; bitpos: [11:8]; default: 0;
+         *  0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
+         */
+        uint32_t sram_usage:4;
+        uint32_t reserved_12:4;
+        /** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
+         *  Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
+         */
+        uint32_t mac_dump_alloc:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_system_sram_usage_conf_reg_t;
+
+/** Type of sec_dpa_conf register
+ *  HP anti-DPA security configuration register
+ */
+typedef union {
+    struct {
+        /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
+         *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
+         *  the number, the stronger the ability to resist DPA attacks and the higher the
+         *  security level, but it will increase the computational overhead of the hardware
+         *  crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
+         */
+        uint32_t sec_dpa_level:2;
+        /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
+         *  This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
+         *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
+         */
+        uint32_t sec_dpa_cfg_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_sec_dpa_conf_reg_t;
+
+/** Type of sdio_ctrl register
+ *  SDIO Control configuration register
+ */
+typedef union {
+    struct {
+        /** dis_sdio_prob : R/W; bitpos: [0]; default: 1;
+         *  Set this bit as 1 to disable SDIO_PROB function. disable by default.
+         */
+        uint32_t dis_sdio_prob:1;
+        /** sdio_win_access_en : R/W; bitpos: [1]; default: 1;
+         *  Enable sdio slave to access other peripherals on the chip
+         */
+        uint32_t sdio_win_access_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_sdio_ctrl_reg_t;
+
+/** Type of retention_conf register
+ *  Retention configuration register
+ */
+typedef union {
+    struct {
+        /** retention_disable : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to disable retention function. Not disable by default.
+         */
+        uint32_t retention_disable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_retention_conf_reg_t;
+
+/** Type of rom_table_lock register
+ *  Rom-Table lock register
+ */
+typedef union {
+    struct {
+        /** rom_table_lock : R/W; bitpos: [0]; default: 0;
+         *  XXXX
+         */
+        uint32_t rom_table_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_rom_table_lock_reg_t;
+
+/** Type of rom_table register
+ *  Rom-Table register
+ */
+typedef union {
+    struct {
+        /** rom_table : R/W; bitpos: [31:0]; default: 0;
+         *  XXXX
+         */
+        uint32_t rom_table:32;
+    };
+    uint32_t val;
+} hp_system_rom_table_reg_t;
+
+/** Type of core_debug_runstall_conf register
+ *  Core Debug runstall configure register
+ */
+typedef union {
+    struct {
+        /** core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
+         *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+         */
+        uint32_t core_debug_runstall_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_core_debug_runstall_conf_reg_t;
+
+/** Type of mem_test_conf register
+ *  MEM_TEST configuration register
+ */
+typedef union {
+    struct {
+        /** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
+         *  This field controls hp system memory WPULSE parameter.
+         */
+        uint32_t hp_mem_wpulse:3;
+        /** hp_mem_wa : R/W; bitpos: [5:3]; default: 4;
+         *  This field controls hp system memory WA parameter.
+         */
+        uint32_t hp_mem_wa:3;
+        /** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
+         *  This field controls hp system memory RA parameter.
+         */
+        uint32_t hp_mem_ra:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_system_mem_test_conf_reg_t;
+
+/** Type of clock_gate register
+ *  HP-SYSTEM clock gating configure register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to force on clock gating.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_clock_gate_reg_t;
+
+
+/** Group: Timeout Register */
+/** Type of cpu_peri_timeout_conf register
+ *  CPU_PERI_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Set the timeout threshold for bus access, corresponding to the number of clock
+         *  cycles of the clock domain.
+         */
+        uint32_t cpu_peri_timeout_thres:16;
+        /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
+         *  Set this bit as 1 to clear timeout interrupt
+         */
+        uint32_t cpu_peri_timeout_int_clear:1;
+        /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
+         *  registers
+         */
+        uint32_t cpu_peri_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_system_cpu_peri_timeout_conf_reg_t;
+
+/** Type of cpu_peri_timeout_addr register
+ *  CPU_PERI_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Record the address information of abnormal access
+         */
+        uint32_t cpu_peri_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_system_cpu_peri_timeout_addr_reg_t;
+
+/** Type of cpu_peri_timeout_uid register
+ *  CPU_PERI_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
+         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+         *  will be cleared after the interrupt is cleared.
+         */
+        uint32_t cpu_peri_timeout_uid:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_system_cpu_peri_timeout_uid_reg_t;
+
+/** Type of hp_peri_timeout_conf register
+ *  HP_PERI_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Set the timeout threshold for bus access, corresponding to the number of clock
+         *  cycles of the clock domain.
+         */
+        uint32_t hp_peri_timeout_thres:16;
+        /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
+         *  Set this bit as 1 to clear timeout interrupt
+         */
+        uint32_t hp_peri_timeout_int_clear:1;
+        /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
+         */
+        uint32_t hp_peri_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_system_hp_peri_timeout_conf_reg_t;
+
+/** Type of hp_peri_timeout_addr register
+ *  HP_PERI_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Record the address information of abnormal access
+         */
+        uint32_t hp_peri_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_system_hp_peri_timeout_addr_reg_t;
+
+/** Type of hp_peri_timeout_uid register
+ *  HP_PERI_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
+         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+         *  will be cleared after the interrupt is cleared.
+         */
+        uint32_t hp_peri_timeout_uid:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_system_hp_peri_timeout_uid_reg_t;
+
+/** Type of modem_peri_timeout_conf register
+ *  MODEM_PERI_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Set the timeout threshold for bus access, corresponding to the number of clock
+         *  cycles of the clock domain.
+         */
+        uint32_t modem_peri_timeout_thres:16;
+        /** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
+         *  Set this bit as 1 to clear timeout interrupt
+         */
+        uint32_t modem_peri_timeout_int_clear:1;
+        /** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Set this bit as 1 to enable timeout protection for accessing modem registers
+         */
+        uint32_t modem_peri_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_system_modem_peri_timeout_conf_reg_t;
+
+/** Type of modem_peri_timeout_addr register
+ *  MODEM_PERI_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Record the address information of abnormal access
+         */
+        uint32_t modem_peri_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_system_modem_peri_timeout_addr_reg_t;
+
+/** Type of modem_peri_timeout_uid register
+ *  MODEM_PERI_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
+         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+         *  will be cleared after the interrupt is cleared.
+         */
+        uint32_t modem_peri_timeout_uid:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_system_modem_peri_timeout_uid_reg_t;
+
+
+/** Group: Redcy ECO Registers */
+/** Type of rnd_eco register
+ *  redcy eco register.
+ */
+typedef union {
+    struct {
+        /** redcy_ena : W/R; bitpos: [0]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_ena:1;
+        /** redcy_result : RO; bitpos: [1]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_rnd_eco_reg_t;
+
+/** Type of rnd_eco_low register
+ *  redcy eco low register.
+ */
+typedef union {
+    struct {
+        /** redcy_low : W/R; bitpos: [31:0]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_low:32;
+    };
+    uint32_t val;
+} hp_system_rnd_eco_low_reg_t;
+
+/** Type of rnd_eco_high register
+ *  redcy eco high register.
+ */
+typedef union {
+    struct {
+        /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_high:32;
+    };
+    uint32_t val;
+} hp_system_rnd_eco_high_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35676432;
+         *  HP-SYSTEM date information/ HP-SYSTEM version information.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_system_date_reg_t;
+
+
+typedef struct hp_system_dev_t {
+    volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
+    volatile hp_system_sram_usage_conf_reg_t sram_usage_conf;
+    volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf;
+    volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
+    volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
+    volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
+    volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
+    volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
+    volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
+    volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
+    volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
+    volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
+    volatile hp_system_sdio_ctrl_reg_t sdio_ctrl;
+    volatile hp_system_retention_conf_reg_t retention_conf;
+    volatile hp_system_rom_table_lock_reg_t rom_table_lock;
+    volatile hp_system_rom_table_reg_t rom_table;
+    volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
+    volatile hp_system_mem_test_conf_reg_t mem_test_conf;
+    uint32_t reserved_048[230];
+    volatile hp_system_rnd_eco_reg_t rnd_eco;
+    volatile hp_system_rnd_eco_low_reg_t rnd_eco_low;
+    volatile hp_system_rnd_eco_high_reg_t rnd_eco_high;
+    uint32_t reserved_3ec[3];
+    volatile hp_system_clock_gate_reg_t clock_gate;
+    volatile hp_system_date_reg_t date;
+} hp_system_dev_t;
+
+extern hp_system_dev_t HP_SYSTEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h
rename to components/soc/esp32c6/register/soc/i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c6/include/soc/i2c_reg.h b/components/soc/esp32c6/register/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/i2c_reg.h
rename to components/soc/esp32c6/register/soc/i2c_reg.h
diff --git a/components/soc/esp32c6/include/soc/i2c_struct.h b/components/soc/esp32c6/register/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/i2c_struct.h
rename to components/soc/esp32c6/register/soc/i2c_struct.h
diff --git a/components/soc/esp32c6/register/soc/i2s_reg.h b/components/soc/esp32c6/register/soc/i2s_reg.h
new file mode 100644
index 00000000000..4f259c1131c
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/i2s_reg.h
@@ -0,0 +1,1294 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2S_INT_RAW_REG register
+ *  I2S interrupt raw register, valid in level.
+ */
+#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
+/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_RAW    (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
+#define I2S_RX_DONE_INT_RAW_V  0x00000001U
+#define I2S_RX_DONE_INT_RAW_S  0
+/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_RAW    (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
+#define I2S_TX_DONE_INT_RAW_V  0x00000001U
+#define I2S_TX_DONE_INT_RAW_S  1
+/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_RAW    (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
+#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_RX_HUNG_INT_RAW_S  2
+/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_RAW    (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
+#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_TX_HUNG_INT_RAW_S  3
+
+/** I2S_INT_ST_REG register
+ *  I2S interrupt status register.
+ */
+#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
+/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ST    (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
+#define I2S_RX_DONE_INT_ST_V  0x00000001U
+#define I2S_RX_DONE_INT_ST_S  0
+/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ST    (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
+#define I2S_TX_DONE_INT_ST_V  0x00000001U
+#define I2S_TX_DONE_INT_ST_S  1
+/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ST    (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
+#define I2S_RX_HUNG_INT_ST_V  0x00000001U
+#define I2S_RX_HUNG_INT_ST_S  2
+/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ST    (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
+#define I2S_TX_HUNG_INT_ST_V  0x00000001U
+#define I2S_TX_HUNG_INT_ST_S  3
+
+/** I2S_INT_ENA_REG register
+ *  I2S interrupt enable register.
+ */
+#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
+/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ENA    (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
+#define I2S_RX_DONE_INT_ENA_V  0x00000001U
+#define I2S_RX_DONE_INT_ENA_S  0
+/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ENA    (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
+#define I2S_TX_DONE_INT_ENA_V  0x00000001U
+#define I2S_TX_DONE_INT_ENA_S  1
+/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ENA    (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
+#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_RX_HUNG_INT_ENA_S  2
+/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ENA    (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
+#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_TX_HUNG_INT_ENA_S  3
+
+/** I2S_INT_CLR_REG register
+ *  I2S interrupt clear register.
+ */
+#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
+/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_CLR    (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
+#define I2S_RX_DONE_INT_CLR_V  0x00000001U
+#define I2S_RX_DONE_INT_CLR_S  0
+/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_CLR    (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
+#define I2S_TX_DONE_INT_CLR_V  0x00000001U
+#define I2S_TX_DONE_INT_CLR_S  1
+/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_CLR    (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
+#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_RX_HUNG_INT_CLR_S  2
+/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_CLR    (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
+#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_TX_HUNG_INT_CLR_S  3
+
+/** I2S_RX_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
+/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset receiver
+ */
+#define I2S_RX_RESET    (BIT(0))
+#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
+#define I2S_RX_RESET_V  0x00000001U
+#define I2S_RX_RESET_S  0
+/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Rx AFIFO
+ */
+#define I2S_RX_FIFO_RESET    (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
+#define I2S_RX_FIFO_RESET_V  0x00000001U
+#define I2S_RX_FIFO_RESET_S  1
+/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start receiving data
+ */
+#define I2S_RX_START    (BIT(2))
+#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
+#define I2S_RX_START_V  0x00000001U
+#define I2S_RX_START_S  2
+/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave receiver mode
+ */
+#define I2S_RX_SLAVE_MOD    (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
+#define I2S_RX_SLAVE_MOD_V  0x00000001U
+#define I2S_RX_SLAVE_MOD_S  3
+/** I2S_RX_MONO : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable receiver  in mono mode
+ */
+#define I2S_RX_MONO    (BIT(5))
+#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
+#define I2S_RX_MONO_V  0x00000001U
+#define I2S_RX_MONO_S  5
+/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+ */
+#define I2S_RX_BIG_ENDIAN    (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
+#define I2S_RX_BIG_ENDIAN_V  0x00000001U
+#define I2S_RX_BIG_ENDIAN_S  7
+/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_RX_UPDATE    (BIT(8))
+#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
+#define I2S_RX_UPDATE_V  0x00000001U
+#define I2S_RX_UPDATE_S  8
+/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+ *  channel data value is valid in I2S RX mono mode.
+ */
+#define I2S_RX_MONO_FST_VLD    (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
+#define I2S_RX_MONO_FST_VLD_V  0x00000001U
+#define I2S_RX_MONO_FST_VLD_S  9
+/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
+ *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_RX_PCM_CONF    0x00000003U
+#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
+#define I2S_RX_PCM_CONF_V  0x00000003U
+#define I2S_RX_PCM_CONF_S  10
+/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass Compress/Decompress module for received data.
+ */
+#define I2S_RX_PCM_BYPASS    (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
+#define I2S_RX_PCM_BYPASS_V  0x00000001U
+#define I2S_RX_PCM_BYPASS_S  12
+/** I2S_RX_STOP_MODE : R/W; bitpos: [14:13]; default: 0;
+ *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+ *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+ */
+#define I2S_RX_STOP_MODE    0x00000003U
+#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
+#define I2S_RX_STOP_MODE_V  0x00000003U
+#define I2S_RX_STOP_MODE_S  13
+/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+ */
+#define I2S_RX_LEFT_ALIGN    (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
+#define I2S_RX_LEFT_ALIGN_V  0x00000001U
+#define I2S_RX_LEFT_ALIGN_S  15
+/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+ */
+#define I2S_RX_24_FILL_EN    (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
+#define I2S_RX_24_FILL_EN_V  0x00000001U
+#define I2S_RX_24_FILL_EN_S  16
+/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+ *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+ */
+#define I2S_RX_WS_IDLE_POL    (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
+#define I2S_RX_WS_IDLE_POL_V  0x00000001U
+#define I2S_RX_WS_IDLE_POL_S  17
+/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+ *  is received first.
+ */
+#define I2S_RX_BIT_ORDER    (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
+#define I2S_RX_BIT_ORDER_V  0x00000001U
+#define I2S_RX_BIT_ORDER_S  18
+/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_TDM_EN    (BIT(19))
+#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
+#define I2S_RX_TDM_EN_V  0x00000001U
+#define I2S_RX_TDM_EN_S  19
+/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_PDM_EN    (BIT(20))
+#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
+#define I2S_RX_PDM_EN_V  0x00000001U
+#define I2S_RX_PDM_EN_S  20
+
+/** I2S_TX_CONF_REG register
+ *  I2S TX configure register
+ */
+#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
+/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset transmitter
+ */
+#define I2S_TX_RESET    (BIT(0))
+#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
+#define I2S_TX_RESET_V  0x00000001U
+#define I2S_TX_RESET_S  0
+/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Tx AFIFO
+ */
+#define I2S_TX_FIFO_RESET    (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
+#define I2S_TX_FIFO_RESET_V  0x00000001U
+#define I2S_TX_FIFO_RESET_S  1
+/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start transmitting data
+ */
+#define I2S_TX_START    (BIT(2))
+#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
+#define I2S_TX_START_V  0x00000001U
+#define I2S_TX_START_S  2
+/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave transmitter mode
+ */
+#define I2S_TX_SLAVE_MOD    (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
+#define I2S_TX_SLAVE_MOD_V  0x00000001U
+#define I2S_TX_SLAVE_MOD_S  3
+/** I2S_TX_MONO : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to enable transmitter in mono mode
+ */
+#define I2S_TX_MONO    (BIT(5))
+#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
+#define I2S_TX_MONO_V  0x00000001U
+#define I2S_TX_MONO_S  5
+/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [6]; default: 0;
+ *  1: The value of Left channel data is equal to the value of right channel data in
+ *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+ *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+ */
+#define I2S_TX_CHAN_EQUAL    (BIT(6))
+#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
+#define I2S_TX_CHAN_EQUAL_V  0x00000001U
+#define I2S_TX_CHAN_EQUAL_S  6
+/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+ *  value.
+ */
+#define I2S_TX_BIG_ENDIAN    (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
+#define I2S_TX_BIG_ENDIAN_V  0x00000001U
+#define I2S_TX_BIG_ENDIAN_S  7
+/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_TX_UPDATE    (BIT(8))
+#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
+#define I2S_TX_UPDATE_V  0x00000001U
+#define I2S_TX_UPDATE_S  8
+/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+ *  channel data value is valid in I2S TX mono mode.
+ */
+#define I2S_TX_MONO_FST_VLD    (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
+#define I2S_TX_MONO_FST_VLD_V  0x00000001U
+#define I2S_TX_MONO_FST_VLD_S  9
+/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
+ *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_TX_PCM_CONF    0x00000003U
+#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
+#define I2S_TX_PCM_CONF_V  0x00000003U
+#define I2S_TX_PCM_CONF_S  10
+/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+ */
+#define I2S_TX_PCM_BYPASS    (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
+#define I2S_TX_PCM_BYPASS_V  0x00000001U
+#define I2S_TX_PCM_BYPASS_S  12
+/** I2S_TX_STOP_EN : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+ */
+#define I2S_TX_STOP_EN    (BIT(13))
+#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
+#define I2S_TX_STOP_EN_V  0x00000001U
+#define I2S_TX_STOP_EN_S  13
+/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+ */
+#define I2S_TX_LEFT_ALIGN    (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
+#define I2S_TX_LEFT_ALIGN_V  0x00000001U
+#define I2S_TX_LEFT_ALIGN_S  15
+/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+ */
+#define I2S_TX_24_FILL_EN    (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
+#define I2S_TX_24_FILL_EN_V  0x00000001U
+#define I2S_TX_24_FILL_EN_S  16
+/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+ *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+ */
+#define I2S_TX_WS_IDLE_POL    (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
+#define I2S_TX_WS_IDLE_POL_V  0x00000001U
+#define I2S_TX_WS_IDLE_POL_S  17
+/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+ *  sent first.
+ */
+#define I2S_TX_BIT_ORDER    (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
+#define I2S_TX_BIT_ORDER_V  0x00000001U
+#define I2S_TX_BIT_ORDER_S  18
+/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_TDM_EN    (BIT(19))
+#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
+#define I2S_TX_TDM_EN_V  0x00000001U
+#define I2S_TX_TDM_EN_S  19
+/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_PDM_EN    (BIT(20))
+#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
+#define I2S_TX_PDM_EN_V  0x00000001U
+#define I2S_TX_PDM_EN_S  20
+/** I2S_TX_CHAN_MOD : R/W; bitpos: [26:24]; default: 0;
+ *  I2S transmitter channel mode configuration bits.
+ */
+#define I2S_TX_CHAN_MOD    0x00000007U
+#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
+#define I2S_TX_CHAN_MOD_V  0x00000007U
+#define I2S_TX_CHAN_MOD_S  24
+/** I2S_SIG_LOOPBACK : R/W; bitpos: [27]; default: 0;
+ *  Enable signal loop back mode with transmitter module and receiver module sharing
+ *  the same WS and BCK signals.
+ */
+#define I2S_SIG_LOOPBACK    (BIT(27))
+#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
+#define I2S_SIG_LOOPBACK_V  0x00000001U
+#define I2S_SIG_LOOPBACK_S  27
+
+/** I2S_RX_CONF1_REG register
+ *  I2S RX configure register 1
+ */
+#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
+/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [6:0]; default: 0;
+ *  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+ */
+#define I2S_RX_TDM_WS_WIDTH    0x0000007FU
+#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
+#define I2S_RX_TDM_WS_WIDTH_V  0x0000007FU
+#define I2S_RX_TDM_WS_WIDTH_S  0
+/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [12:7]; default: 6;
+ *  Bit clock configuration bits in receiver mode.
+ */
+#define I2S_RX_BCK_DIV_NUM    0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
+#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_S  7
+/** I2S_RX_BITS_MOD : R/W; bitpos: [17:13]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+ *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_RX_BITS_MOD    0x0000001FU
+#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
+#define I2S_RX_BITS_MOD_V  0x0000001FU
+#define I2S_RX_BITS_MOD_S  13
+/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [23:18]; default: 15;
+ *  I2S Rx half sample bits -1.
+ */
+#define I2S_RX_HALF_SAMPLE_BITS    0x0000003FU
+#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x0000003FU
+#define I2S_RX_HALF_SAMPLE_BITS_S  18
+/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [28:24]; default: 15;
+ *  The Rx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
+#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_S  24
+/** I2S_RX_MSB_SHIFT : R/W; bitpos: [29]; default: 1;
+ *  Set this bit to enable receiver in Phillips standard mode
+ */
+#define I2S_RX_MSB_SHIFT    (BIT(29))
+#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
+#define I2S_RX_MSB_SHIFT_V  0x00000001U
+#define I2S_RX_MSB_SHIFT_S  29
+
+/** I2S_TX_CONF1_REG register
+ *  I2S TX configure register 1
+ */
+#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
+/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [6:0]; default: 0;
+ *  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
+ */
+#define I2S_TX_TDM_WS_WIDTH    0x0000007FU
+#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
+#define I2S_TX_TDM_WS_WIDTH_V  0x0000007FU
+#define I2S_TX_TDM_WS_WIDTH_S  0
+/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [12:7]; default: 6;
+ *  Bit clock configuration bits in transmitter mode.
+ */
+#define I2S_TX_BCK_DIV_NUM    0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
+#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_S  7
+/** I2S_TX_BITS_MOD : R/W; bitpos: [17:13]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+ *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_TX_BITS_MOD    0x0000001FU
+#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
+#define I2S_TX_BITS_MOD_V  0x0000001FU
+#define I2S_TX_BITS_MOD_S  13
+/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [23:18]; default: 15;
+ *  I2S Tx half sample bits -1.
+ */
+#define I2S_TX_HALF_SAMPLE_BITS    0x0000003FU
+#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x0000003FU
+#define I2S_TX_HALF_SAMPLE_BITS_S  18
+/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [28:24]; default: 15;
+ *  The Tx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
+#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_S  24
+/** I2S_TX_MSB_SHIFT : R/W; bitpos: [29]; default: 1;
+ *  Set this bit to enable transmitter in Phillips standard mode
+ */
+#define I2S_TX_MSB_SHIFT    (BIT(29))
+#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
+#define I2S_TX_MSB_SHIFT_V  0x00000001U
+#define I2S_TX_MSB_SHIFT_S  29
+/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [30]; default: 1;
+ *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+ *  generate pos/neg edge in master mode.
+ */
+#define I2S_TX_BCK_NO_DLY    (BIT(30))
+#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
+#define I2S_TX_BCK_NO_DLY_V  0x00000001U
+#define I2S_TX_BCK_NO_DLY_S  30
+
+/** I2S_RX_CLKM_CONF_REG register
+ *  I2S RX clock configure register
+ */
+#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x30)
+/** I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
+ *  Integral I2S clock divider value
+ */
+#define I2S_RX_CLKM_DIV_NUM    0x000000FFU
+#define I2S_RX_CLKM_DIV_NUM_M  (I2S_RX_CLKM_DIV_NUM_V << I2S_RX_CLKM_DIV_NUM_S)
+#define I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
+#define I2S_RX_CLKM_DIV_NUM_S  0
+/** I2S_RX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0;
+ *  I2S Rx module clock enable signal.
+ */
+#define I2S_RX_CLK_ACTIVE    (BIT(26))
+#define I2S_RX_CLK_ACTIVE_M  (I2S_RX_CLK_ACTIVE_V << I2S_RX_CLK_ACTIVE_S)
+#define I2S_RX_CLK_ACTIVE_V  0x00000001U
+#define I2S_RX_CLK_ACTIVE_S  26
+/** I2S_RX_CLK_SEL : R/W; bitpos: [28:27]; default: 0;
+ *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+ */
+#define I2S_RX_CLK_SEL    0x00000003U
+#define I2S_RX_CLK_SEL_M  (I2S_RX_CLK_SEL_V << I2S_RX_CLK_SEL_S)
+#define I2S_RX_CLK_SEL_V  0x00000003U
+#define I2S_RX_CLK_SEL_S  27
+/** I2S_MCLK_SEL : R/W; bitpos: [29]; default: 0;
+ *  0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as
+ *  I2S_MCLK_OUT.
+ */
+#define I2S_MCLK_SEL    (BIT(29))
+#define I2S_MCLK_SEL_M  (I2S_MCLK_SEL_V << I2S_MCLK_SEL_S)
+#define I2S_MCLK_SEL_V  0x00000001U
+#define I2S_MCLK_SEL_S  29
+
+/** I2S_TX_CLKM_CONF_REG register
+ *  I2S TX clock configure register
+ */
+#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x34)
+/** I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
+ *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
+ *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
+ *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+ *  (n+1)-div] + y * (n+1)-div.
+ */
+#define I2S_TX_CLKM_DIV_NUM    0x000000FFU
+#define I2S_TX_CLKM_DIV_NUM_M  (I2S_TX_CLKM_DIV_NUM_V << I2S_TX_CLKM_DIV_NUM_S)
+#define I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
+#define I2S_TX_CLKM_DIV_NUM_S  0
+/** I2S_TX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0;
+ *  I2S Tx module clock enable signal.
+ */
+#define I2S_TX_CLK_ACTIVE    (BIT(26))
+#define I2S_TX_CLK_ACTIVE_M  (I2S_TX_CLK_ACTIVE_V << I2S_TX_CLK_ACTIVE_S)
+#define I2S_TX_CLK_ACTIVE_V  0x00000001U
+#define I2S_TX_CLK_ACTIVE_S  26
+/** I2S_TX_CLK_SEL : R/W; bitpos: [28:27]; default: 0;
+ *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+ *  I2S_MCLK_in.
+ */
+#define I2S_TX_CLK_SEL    0x00000003U
+#define I2S_TX_CLK_SEL_M  (I2S_TX_CLK_SEL_V << I2S_TX_CLK_SEL_S)
+#define I2S_TX_CLK_SEL_V  0x00000003U
+#define I2S_TX_CLK_SEL_S  27
+/** I2S_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define I2S_CLK_EN    (BIT(29))
+#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
+#define I2S_CLK_EN_V  0x00000001U
+#define I2S_CLK_EN_S  29
+
+/** I2S_RX_CLKM_DIV_CONF_REG register
+ *  I2S RX module clock divider configure register
+ */
+#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x38)
+/** I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Z is (a-b).
+ */
+#define I2S_RX_CLKM_DIV_Z    0x000001FFU
+#define I2S_RX_CLKM_DIV_Z_M  (I2S_RX_CLKM_DIV_Z_V << I2S_RX_CLKM_DIV_Z_S)
+#define I2S_RX_CLKM_DIV_Z_V  0x000001FFU
+#define I2S_RX_CLKM_DIV_Z_S  0
+/** I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define I2S_RX_CLKM_DIV_Y    0x000001FFU
+#define I2S_RX_CLKM_DIV_Y_M  (I2S_RX_CLKM_DIV_Y_V << I2S_RX_CLKM_DIV_Y_S)
+#define I2S_RX_CLKM_DIV_Y_V  0x000001FFU
+#define I2S_RX_CLKM_DIV_Y_S  9
+/** I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define I2S_RX_CLKM_DIV_X    0x000001FFU
+#define I2S_RX_CLKM_DIV_X_M  (I2S_RX_CLKM_DIV_X_V << I2S_RX_CLKM_DIV_X_S)
+#define I2S_RX_CLKM_DIV_X_V  0x000001FFU
+#define I2S_RX_CLKM_DIV_X_S  18
+/** I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_YN1 is 1.
+ */
+#define I2S_RX_CLKM_DIV_YN1    (BIT(27))
+#define I2S_RX_CLKM_DIV_YN1_M  (I2S_RX_CLKM_DIV_YN1_V << I2S_RX_CLKM_DIV_YN1_S)
+#define I2S_RX_CLKM_DIV_YN1_V  0x00000001U
+#define I2S_RX_CLKM_DIV_YN1_S  27
+
+/** I2S_TX_CLKM_DIV_CONF_REG register
+ *  I2S TX module clock divider configure register
+ */
+#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x3c)
+/** I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Z is (a-b).
+ */
+#define I2S_TX_CLKM_DIV_Z    0x000001FFU
+#define I2S_TX_CLKM_DIV_Z_M  (I2S_TX_CLKM_DIV_Z_V << I2S_TX_CLKM_DIV_Z_S)
+#define I2S_TX_CLKM_DIV_Z_V  0x000001FFU
+#define I2S_TX_CLKM_DIV_Z_S  0
+/** I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define I2S_TX_CLKM_DIV_Y    0x000001FFU
+#define I2S_TX_CLKM_DIV_Y_M  (I2S_TX_CLKM_DIV_Y_V << I2S_TX_CLKM_DIV_Y_S)
+#define I2S_TX_CLKM_DIV_Y_V  0x000001FFU
+#define I2S_TX_CLKM_DIV_Y_S  9
+/** I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define I2S_TX_CLKM_DIV_X    0x000001FFU
+#define I2S_TX_CLKM_DIV_X_M  (I2S_TX_CLKM_DIV_X_V << I2S_TX_CLKM_DIV_X_S)
+#define I2S_TX_CLKM_DIV_X_V  0x000001FFU
+#define I2S_TX_CLKM_DIV_X_S  18
+/** I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_YN1 is 1.
+ */
+#define I2S_TX_CLKM_DIV_YN1    (BIT(27))
+#define I2S_TX_CLKM_DIV_YN1_M  (I2S_TX_CLKM_DIV_YN1_V << I2S_TX_CLKM_DIV_YN1_S)
+#define I2S_TX_CLKM_DIV_YN1_V  0x00000001U
+#define I2S_TX_CLKM_DIV_YN1_S  27
+
+/** I2S_TX_PCM2PDM_CONF_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40)
+/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0;
+ *  I2S TX PDM bypass hp filter or not. The option has been removed.
+ */
+#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_M  (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S)
+#define I2S_TX_PDM_HP_BYPASS_V  0x00000001U
+#define I2S_TX_PDM_HP_BYPASS_S  0
+/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
+ *  I2S TX PDM OSR2 value
+ */
+#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
+#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
+ *  I2S TX PDM prescale for sigmadelta
+ */
+#define I2S_TX_PDM_PRESCALE    0x000000FFU
+#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
+#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
+#define I2S_TX_PDM_PRESCALE_S  5
+/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
+ *  I2S TX PDM sigmadelta dither2 value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
+ *  I2S TX PDM sigmadelta dither value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
+ *  I2S TX PDM dac mode enable
+ */
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
+ *  I2S TX PDM dac 2channel enable
+ */
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
+ *  I2S TX PDM Converter enable
+ */
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
+#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
+#define I2S_PCM2PDM_CONV_EN_S  25
+
+/** I2S_TX_PCM2PDM_CONF1_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44)
+/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
+ *  I2S TX PDM Fp
+ */
+#define I2S_TX_PDM_FP    0x000003FFU
+#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
+#define I2S_TX_PDM_FP_V  0x000003FFU
+#define I2S_TX_PDM_FP_S  0
+/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
+ *  I2S TX PDM Fs
+ */
+#define I2S_TX_PDM_FS    0x000003FFU
+#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
+#define I2S_TX_PDM_FS_V  0x000003FFU
+#define I2S_TX_PDM_FS_S  10
+/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
+#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
+#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+
+/** I2S_RX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
+/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
+#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
+#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
+#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
+#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
+#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
+#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
+#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
+#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+
+/** I2S_TX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
+/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
+#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN0_EN_S  0
+/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
+#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
+#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
+#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
+#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
+#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
+#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
+#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
+#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
+#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
+#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
+#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
+#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
+#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
+#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
+#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
+ *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+ *  only the data of the enabled channels is sent, then this bit should be set. Clear
+ *  it when all the data stored in DMA TX buffer is for enabled channels.
+ */
+#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+
+/** I2S_RX_TIMING_REG register
+ *  I2S RX timing control register
+ */
+#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
+/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD_IN_DM    0x00000003U
+#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
+#define I2S_RX_SD_IN_DM_V  0x00000003U
+#define I2S_RX_SD_IN_DM_S  0
+/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_OUT_DM    0x00000003U
+#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
+#define I2S_RX_WS_OUT_DM_V  0x00000003U
+#define I2S_RX_WS_OUT_DM_S  16
+/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_OUT_DM    0x00000003U
+#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
+#define I2S_RX_BCK_OUT_DM_V  0x00000003U
+#define I2S_RX_BCK_OUT_DM_S  20
+/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_IN_DM    0x00000003U
+#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
+#define I2S_RX_WS_IN_DM_V  0x00000003U
+#define I2S_RX_WS_IN_DM_S  24
+/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_IN_DM    0x00000003U
+#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
+#define I2S_RX_BCK_IN_DM_V  0x00000003U
+#define I2S_RX_BCK_IN_DM_S  28
+
+/** I2S_TX_TIMING_REG register
+ *  I2S TX timing control register
+ */
+#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
+/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD_OUT_DM    0x00000003U
+#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
+#define I2S_TX_SD_OUT_DM_V  0x00000003U
+#define I2S_TX_SD_OUT_DM_S  0
+/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD1_OUT_DM    0x00000003U
+#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
+#define I2S_TX_SD1_OUT_DM_V  0x00000003U
+#define I2S_TX_SD1_OUT_DM_S  4
+/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_OUT_DM    0x00000003U
+#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
+#define I2S_TX_WS_OUT_DM_V  0x00000003U
+#define I2S_TX_WS_OUT_DM_S  16
+/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_OUT_DM    0x00000003U
+#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
+#define I2S_TX_BCK_OUT_DM_V  0x00000003U
+#define I2S_TX_BCK_OUT_DM_S  20
+/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_IN_DM    0x00000003U
+#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
+#define I2S_TX_WS_IN_DM_V  0x00000003U
+#define I2S_TX_WS_IN_DM_S  24
+/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_IN_DM    0x00000003U
+#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
+#define I2S_TX_BCK_IN_DM_V  0x00000003U
+#define I2S_TX_BCK_IN_DM_S  28
+
+/** I2S_LC_HUNG_CONF_REG register
+ *  I2S HUNG configure register.
+ */
+#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
+/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ *  when fifo hung counter is equal to this value
+ */
+#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
+#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_S  0
+/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  The bits are used to scale tick counter threshold. The tick counter is reset when
+ *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+ */
+#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  The enable bit for FIFO timeout
+ */
+#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+
+/** I2S_RXEOF_NUM_REG register
+ *  I2S RX data number control register.
+ */
+#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
+/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
+ *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+ *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+ */
+#define I2S_RX_EOF_NUM    0x00000FFFU
+#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
+#define I2S_RX_EOF_NUM_V  0x00000FFFU
+#define I2S_RX_EOF_NUM_S  0
+
+/** I2S_CONF_SIGLE_DATA_REG register
+ *  I2S signal data register
+ */
+#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
+/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The configured constant channel data to be sent out.
+ */
+#define I2S_SINGLE_DATA    0xFFFFFFFFU
+#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
+#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
+#define I2S_SINGLE_DATA_S  0
+
+/** I2S_STATE_REG register
+ *  I2S TX status register
+ */
+#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
+/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
+ *  1: i2s_tx is idle state. 0: i2s_tx is working.
+ */
+#define I2S_TX_IDLE    (BIT(0))
+#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
+#define I2S_TX_IDLE_V  0x00000001U
+#define I2S_TX_IDLE_S  0
+
+/** I2S_ETM_CONF_REG register
+ *  I2S ETM configure register
+ */
+#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
+/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
+ *  I2S ETM send x words event. When sending word number of
+ *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
+#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_S  0
+/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
+ *  I2S ETM receive x words event. When receiving word number of
+ *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
+
+/** I2S_DATE_REG register
+ *  Version control register
+ */
+#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80)
+/** I2S_DATE : R/W; bitpos: [27:0]; default: 35655792;
+ *  I2S version control register
+ */
+#define I2S_DATE    0x0FFFFFFFU
+#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
+#define I2S_DATE_V  0x0FFFFFFFU
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/i2s_struct.h b/components/soc/esp32c6/register/soc/i2s_struct.h
new file mode 100644
index 00000000000..b7629e4c989
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/i2s_struct.h
@@ -0,0 +1,902 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        uint32_t reserved_4:1;
+        /** rx_mono : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        uint32_t reserved_6:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_stop_mode : R/W; bitpos: [14:13]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0;
+         *  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+         */
+        uint32_t rx_tdm_ws_width:7;
+        /** rx_bck_div_num : R/W; bitpos: [12:7]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        /** rx_bits_mod : R/W; bitpos: [17:13]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [23:18]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:6;
+        /** rx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+        /** rx_msb_shift : R/W; bitpos: [29]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
+         *  I2S TX PDM bypass hp filter or not. The option has been removed.
+         */
+        uint32_t tx_pdm_hp_bypass:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rx_eof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_rx_eof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        uint32_t reserved_4:1;
+        /** tx_mono : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_chan_equal : R/W; bitpos: [6]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_stop_en : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        uint32_t reserved_14:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        uint32_t reserved_21:3;
+        /** tx_chan_mod : R/W; bitpos: [26:24]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [27]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [6:0]; default: 0;
+         *  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
+         */
+        uint32_t tx_tdm_ws_width:7;
+        /** tx_bck_div_num : R/W; bitpos: [12:7]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_bits_mod : R/W; bitpos: [17:13]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [23:18]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:6;
+        /** tx_tdm_chan_bits : R/W; bitpos: [28:24]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+        /** tx_msb_shift : R/W; bitpos: [29]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [30]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:14;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_single_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_single_data_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:10;
+        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35655792;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct i2s_dev_t {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    uint32_t reserved_030[4];
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    uint32_t reserved_048[2];
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rx_eof_num_reg_t rx_eof_num;
+    volatile i2s_conf_single_data_reg_t conf_single_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    uint32_t reserved_074[3];
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+extern i2s_dev_t I2S0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/ieee802154_reg.h b/components/soc/esp32c6/register/soc/ieee802154_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ieee802154_reg.h
rename to components/soc/esp32c6/register/soc/ieee802154_reg.h
diff --git a/components/soc/esp32c6/include/soc/ieee802154_struct.h b/components/soc/esp32c6/register/soc/ieee802154_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ieee802154_struct.h
rename to components/soc/esp32c6/register/soc/ieee802154_struct.h
diff --git a/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h b/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h
new file mode 100644
index 00000000000..a2e729de2b7
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/interrupt_matrix_reg.h
@@ -0,0 +1,999 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
+/** INTMTX_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_M  (INTMTX_CORE0_WIFI_MAC_INTR_MAP_V << INTMTX_CORE0_WIFI_MAC_INTR_MAP_S)
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_WIFI_MAC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
+/** INTMTX_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP    0x0000001FU
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_M  (INTMTX_CORE0_WIFI_MAC_NMI_MAP_V << INTMTX_CORE0_WIFI_MAC_NMI_MAP_S)
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_V  0x0000001FU
+#define INTMTX_CORE0_WIFI_MAC_NMI_MAP_S  0
+
+/** INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
+/** INTMTX_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_M  (INTMTX_CORE0_WIFI_PWR_INTR_MAP_V << INTMTX_CORE0_WIFI_PWR_INTR_MAP_S)
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_WIFI_PWR_INTR_MAP_S  0
+
+/** INTMTX_CORE0_WIFI_BB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
+/** INTMTX_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP_M  (INTMTX_CORE0_WIFI_BB_INTR_MAP_V << INTMTX_CORE0_WIFI_BB_INTR_MAP_S)
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_WIFI_BB_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
+/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BT_MAC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_M  (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
+/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BT_BB_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_BB_INTR_MAP_M  (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
+#define INTMTX_CORE0_BT_BB_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_BB_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
+/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BT_BB_NMI_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_BB_NMI_MAP_M  (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
+#define INTMTX_CORE0_BT_BB_NMI_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_BB_NMI_MAP_S  0
+
+/** INTMTX_CORE0_LP_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
+/** INTMTX_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_COEX_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
+/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_COEX_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_COEX_INTR_MAP_M  (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
+#define INTMTX_CORE0_COEX_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_COEX_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
+/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M  (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
+/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M  (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2C_MST_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
+/** INTMTX_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_I2C_MST_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2C_MST_INTR_MAP_M  (INTMTX_CORE0_I2C_MST_INTR_MAP_V << INTMTX_CORE0_I2C_MST_INTR_MAP_S)
+#define INTMTX_CORE0_I2C_MST_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2C_MST_INTR_MAP_S  0
+
+/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
+/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M  (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PMU_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
+/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PMU_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PMU_INTR_MAP_M  (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
+#define INTMTX_CORE0_PMU_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PMU_INTR_MAP_S  0
+
+/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
+/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_EFUSE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_EFUSE_INTR_MAP_M  (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
+#define INTMTX_CORE0_EFUSE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_EFUSE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
+/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_UART_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
+/** INTMTX_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_UART_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_UART_INTR_MAP_M  (INTMTX_CORE0_LP_UART_INTR_MAP_V << INTMTX_CORE0_LP_UART_INTR_MAP_S)
+#define INTMTX_CORE0_LP_UART_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_UART_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_I2C_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
+/** INTMTX_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_I2C_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_I2C_INTR_MAP_M  (INTMTX_CORE0_LP_I2C_INTR_MAP_V << INTMTX_CORE0_LP_I2C_INTR_MAP_S)
+#define INTMTX_CORE0_LP_I2C_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_I2C_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
+/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_M  (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
+/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
+/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
+/** INTMTX_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M1_INTR_MAP_V << INTMTX_CORE0_LP_APM_M1_INTR_MAP_S)
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_APM_M1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
+
+/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
+/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M  (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
+/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TRACE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TRACE_INTR_MAP_M  (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
+#define INTMTX_CORE0_TRACE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TRACE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
+/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CACHE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CACHE_INTR_MAP_M  (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
+#define INTMTX_CORE0_CACHE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CACHE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
+/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
+
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
+
+/** INTMTX_CORE0_PAU_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
+/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PAU_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PAU_INTR_MAP_M  (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
+#define INTMTX_CORE0_PAU_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PAU_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
+/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
+/** INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
+/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
+/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
+/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
+/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_APM0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_APM0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
+/** INTMTX_CORE0_LP_APM0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LP_APM0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_APM0_INTR_MAP_M  (INTMTX_CORE0_LP_APM0_INTR_MAP_V << INTMTX_CORE0_LP_APM0_INTR_MAP_S)
+#define INTMTX_CORE0_LP_APM0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_APM0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
+/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_MSPI_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_MSPI_INTR_MAP_M  (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
+#define INTMTX_CORE0_MSPI_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_MSPI_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2S_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
+/** INTMTX_CORE0_I2S_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_I2S_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2S_INTR_MAP_M  (INTMTX_CORE0_I2S_INTR_MAP_V << INTMTX_CORE0_I2S_INTR_MAP_S)
+#define INTMTX_CORE0_I2S_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2S_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
+/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_UHCI0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UHCI0_INTR_MAP_M  (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
+#define INTMTX_CORE0_UHCI0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UHCI0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UART0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
+/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_UART0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UART0_INTR_MAP_M  (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
+#define INTMTX_CORE0_UART0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UART0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UART1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
+/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_UART1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UART1_INTR_MAP_M  (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
+#define INTMTX_CORE0_UART1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UART1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
+/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_LEDC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LEDC_INTR_MAP_M  (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
+#define INTMTX_CORE0_LEDC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LEDC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
+/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CAN0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CAN0_INTR_MAP_M  (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
+#define INTMTX_CORE0_CAN0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CAN0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CAN1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
+/** INTMTX_CORE0_CAN1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_CAN1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CAN1_INTR_MAP_M  (INTMTX_CORE0_CAN1_INTR_MAP_V << INTMTX_CORE0_CAN1_INTR_MAP_S)
+#define INTMTX_CORE0_CAN1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CAN1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_USB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
+/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_USB_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_USB_INTR_MAP_M  (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
+#define INTMTX_CORE0_USB_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_USB_INTR_MAP_S  0
+
+/** INTMTX_CORE0_RMT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
+/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_RMT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_RMT_INTR_MAP_M  (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
+#define INTMTX_CORE0_RMT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_RMT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
+/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M  (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
+/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG0_T0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_M  (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG0_T1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
+/** INTMTX_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG0_T1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG0_T1_INTR_MAP_M  (INTMTX_CORE0_TG0_T1_INTR_MAP_V << INTMTX_CORE0_TG0_T1_INTR_MAP_S)
+#define INTMTX_CORE0_TG0_T1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG0_T1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
+/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M  (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
+/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG1_T0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_M  (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG1_T1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
+/** INTMTX_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG1_T1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG1_T1_INTR_MAP_M  (INTMTX_CORE0_TG1_T1_INTR_MAP_V << INTMTX_CORE0_TG1_T1_INTR_MAP_S)
+#define INTMTX_CORE0_TG1_T1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG1_T1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
+/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M  (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
+/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
+/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
+/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
+/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_APB_ADC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_M  (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PWM_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
+/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PWM_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PWM_INTR_MAP_M  (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
+#define INTMTX_CORE0_PWM_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PWM_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
+/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PCNT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PCNT_INTR_MAP_M  (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
+#define INTMTX_CORE0_PCNT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PCNT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PARL_IO_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PARL_IO_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
+/** INTMTX_CORE0_PARL_IO_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_PARL_IO_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PARL_IO_INTR_MAP_M  (INTMTX_CORE0_PARL_IO_INTR_MAP_V << INTMTX_CORE0_PARL_IO_INTR_MAP_S)
+#define INTMTX_CORE0_PARL_IO_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PARL_IO_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SLC0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
+/** INTMTX_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SLC0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SLC0_INTR_MAP_M  (INTMTX_CORE0_SLC0_INTR_MAP_V << INTMTX_CORE0_SLC0_INTR_MAP_S)
+#define INTMTX_CORE0_SLC0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SLC0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SLC1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
+/** INTMTX_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SLC1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SLC1_INTR_MAP_M  (INTMTX_CORE0_SLC1_INTR_MAP_V << INTMTX_CORE0_SLC1_INTR_MAP_S)
+#define INTMTX_CORE0_SLC1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SLC1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
+/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
+/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
+/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x114)
+/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x118)
+/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x11c)
+/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x120)
+/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_GPSPI2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_M  (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_AES_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x124)
+/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_AES_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_AES_INTR_MAP_M  (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
+#define INTMTX_CORE0_AES_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_AES_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SHA_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x128)
+/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_SHA_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SHA_INTR_MAP_M  (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
+#define INTMTX_CORE0_SHA_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SHA_INTR_MAP_S  0
+
+/** INTMTX_CORE0_RSA_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x12c)
+/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_RSA_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_RSA_INTR_MAP_M  (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
+#define INTMTX_CORE0_RSA_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_RSA_INTR_MAP_S  0
+
+/** INTMTX_CORE0_ECC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x130)
+/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_ECC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ECC_INTR_MAP_M  (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
+#define INTMTX_CORE0_ECC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ECC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x134)
+/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_INT_STATUS_0    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_0_M  (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
+#define INTMTX_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_0_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x138)
+/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_INT_STATUS_1    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_1_M  (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
+#define INTMTX_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_1_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x13c)
+/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTMTX_CORE0_INT_STATUS_2    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_2_M  (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
+#define INTMTX_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_2_S  0
+
+/** INTMTX_CORE0_CLOCK_GATE_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x140)
+/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define INTMTX_CORE0_REG_CLK_EN    (BIT(0))
+#define INTMTX_CORE0_REG_CLK_EN_M  (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
+#define INTMTX_CORE0_REG_CLK_EN_V  0x00000001U
+#define INTMTX_CORE0_REG_CLK_EN_S  0
+
+/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
+/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35664144;
+ *  Need add description
+ */
+#define INTMTX_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_M  (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/interrupt_matrix_struct.h b/components/soc/esp32c6/register/soc/interrupt_matrix_struct.h
new file mode 100644
index 00000000000..89d4859ad67
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/interrupt_matrix_struct.h
@@ -0,0 +1,1254 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of wifi_mac_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_mac_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_wifi_mac_intr_map_reg_t;
+
+/** Type of wifi_mac_nmi_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_mac_nmi_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_mac_nmi_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_wifi_mac_nmi_map_reg_t;
+
+/** Type of wifi_pwr_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_pwr_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_pwr_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_wifi_pwr_intr_map_reg_t;
+
+/** Type of wifi_bb_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_bb_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_wifi_bb_intr_map_reg_t;
+
+/** Type of bt_mac_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_mac_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_bt_mac_intr_map_reg_t;
+
+/** Type of bt_bb_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_bb_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_bt_bb_intr_map_reg_t;
+
+/** Type of bt_bb_nmi_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_bb_nmi_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_bt_bb_nmi_map_reg_t;
+
+/** Type of lp_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_timer_intr_map_reg_t;
+
+/** Type of coex_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** coex_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t coex_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_coex_intr_map_reg_t;
+
+/** Type of ble_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ble_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_ble_timer_intr_map_reg_t;
+
+/** Type of ble_sec_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ble_sec_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_ble_sec_intr_map_reg_t;
+
+/** Type of i2c_mst_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2c_mst_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t i2c_mst_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_i2c_mst_intr_map_reg_t;
+
+/** Type of zb_mac_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t zb_mac_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_zb_mac_intr_map_reg_t;
+
+/** Type of pmu_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t pmu_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_pmu_intr_map_reg_t;
+
+/** Type of efuse_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t efuse_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_efuse_intr_map_reg_t;
+
+/** Type of lp_rtc_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_rtc_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_rtc_timer_intr_map_reg_t;
+
+/** Type of lp_uart_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_uart_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_uart_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_uart_intr_map_reg_t;
+
+/** Type of lp_i2c_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_i2c_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_i2c_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_i2c_intr_map_reg_t;
+
+/** Type of lp_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_wdt_intr_map_reg_t;
+
+/** Type of lp_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_peri_timeout_intr_map_reg_t;
+
+/** Type of lp_apm_m0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_apm_m0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_apm_m0_intr_map_reg_t;
+
+/** Type of lp_apm_m1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_apm_m1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_apm_m1_intr_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_0_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_0_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_1_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_1_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_2_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_2_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_3_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_3_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t;
+
+/** Type of assist_debug_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t assist_debug_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_assist_debug_intr_map_reg_t;
+
+/** Type of trace_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** trace_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t trace_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_trace_intr_map_reg_t;
+
+/** Type of cache_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cache_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cache_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cache_intr_map_reg_t;
+
+/** Type of cpu_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t;
+
+/** Type of gpio_interrupt_pro_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t gpio_interrupt_pro_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_gpio_interrupt_pro_map_reg_t;
+
+/** Type of gpio_interrupt_pro_nmi_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t gpio_interrupt_pro_nmi_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t;
+
+/** Type of pau_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pau_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t pau_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_pau_intr_map_reg_t;
+
+/** Type of hp_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_peri_timeout_intr_map_reg_t;
+
+/** Type of modem_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** modem_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t modem_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_modem_peri_timeout_intr_map_reg_t;
+
+/** Type of hp_apm_m0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_apm_m0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_apm_m0_intr_map_reg_t;
+
+/** Type of hp_apm_m1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_apm_m1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_apm_m1_intr_map_reg_t;
+
+/** Type of hp_apm_m2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_apm_m2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_apm_m2_intr_map_reg_t;
+
+/** Type of hp_apm_m3_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t hp_apm_m3_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_hp_apm_m3_intr_map_reg_t;
+
+/** Type of lp_apm0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_apm0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t lp_apm0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_lp_apm0_intr_map_reg_t;
+
+/** Type of mspi_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t mspi_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_mspi_intr_map_reg_t;
+
+/** Type of i2s_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2s_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t i2s_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_i2s_intr_map_reg_t;
+
+/** Type of uhci0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t uhci0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_uhci0_intr_map_reg_t;
+
+/** Type of uart0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t uart0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_uart0_intr_map_reg_t;
+
+/** Type of uart1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t uart1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_uart1_intr_map_reg_t;
+
+/** Type of ledc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ledc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_ledc_intr_map_reg_t;
+
+/** Type of can0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** can0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t can0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_can0_intr_map_reg_t;
+
+/** Type of can1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** can1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t can1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_can1_intr_map_reg_t;
+
+/** Type of usb_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** usb_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t usb_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_usb_intr_map_reg_t;
+
+/** Type of rmt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rmt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_rmt_intr_map_reg_t;
+
+/** Type of i2c_ext0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t i2c_ext0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_i2c_ext0_intr_map_reg_t;
+
+/** Type of tg0_t0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg0_t0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg0_t0_intr_map_reg_t;
+
+/** Type of tg0_t1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg0_t1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg0_t1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg0_t1_intr_map_reg_t;
+
+/** Type of tg0_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg0_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg0_wdt_intr_map_reg_t;
+
+/** Type of tg1_t0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg1_t0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg1_t0_intr_map_reg_t;
+
+/** Type of tg1_t1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg1_t1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg1_t1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg1_t1_intr_map_reg_t;
+
+/** Type of tg1_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t tg1_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_tg1_wdt_intr_map_reg_t;
+
+/** Type of systimer_target0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t systimer_target0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_systimer_target0_intr_map_reg_t;
+
+/** Type of systimer_target1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t systimer_target1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_systimer_target1_intr_map_reg_t;
+
+/** Type of systimer_target2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t systimer_target2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_systimer_target2_intr_map_reg_t;
+
+/** Type of apb_adc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t apb_adc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_apb_adc_intr_map_reg_t;
+
+/** Type of pwm_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t pwm_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_pwm_intr_map_reg_t;
+
+/** Type of pcnt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t pcnt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_pcnt_intr_map_reg_t;
+
+/** Type of parl_io_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** parl_io_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t parl_io_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_parl_io_intr_map_reg_t;
+
+/** Type of slc0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slc0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t slc0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_slc0_intr_map_reg_t;
+
+/** Type of slc1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slc1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t slc1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_slc1_intr_map_reg_t;
+
+/** Type of dma_in_ch0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_in_ch0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_in_ch0_intr_map_reg_t;
+
+/** Type of dma_in_ch1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_in_ch1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_in_ch1_intr_map_reg_t;
+
+/** Type of dma_in_ch2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_in_ch2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_in_ch2_intr_map_reg_t;
+
+/** Type of dma_out_ch0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_out_ch0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_out_ch0_intr_map_reg_t;
+
+/** Type of dma_out_ch1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_out_ch1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_out_ch1_intr_map_reg_t;
+
+/** Type of dma_out_ch2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_out_ch2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_dma_out_ch2_intr_map_reg_t;
+
+/** Type of gpspi2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t gpspi2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_gpspi2_intr_map_reg_t;
+
+/** Type of aes_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** aes_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t aes_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_aes_intr_map_reg_t;
+
+/** Type of sha_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** sha_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t sha_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_sha_intr_map_reg_t;
+
+/** Type of rsa_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rsa_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_rsa_intr_map_reg_t;
+
+/** Type of ecc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ecc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} interrupt_matrix_ecc_intr_map_reg_t;
+
+/** Type of int_status_reg_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t int_status_0:32;
+    };
+    uint32_t val;
+} interrupt_matrix_int_status_reg_0_reg_t;
+
+/** Type of int_status_reg_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t int_status_1:32;
+    };
+    uint32_t val;
+} interrupt_matrix_int_status_reg_1_reg_t;
+
+/** Type of int_status_reg_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t int_status_2:32;
+    };
+    uint32_t val;
+} interrupt_matrix_int_status_reg_2_reg_t;
+
+/** Type of clock_gate register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} interrupt_matrix_clock_gate_reg_t;
+
+/** Type of interrupt_reg_date register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35664144;
+         *  Need add description
+         */
+        uint32_t interrupt_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} interrupt_matrix_interrupt_reg_date_reg_t;
+
+
+typedef struct interrupt_matrix_dev_t {
+    volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map;
+    volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map;
+    volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map;
+    volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map;
+    volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map;
+    volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map;
+    volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map;
+    volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map;
+    volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map;
+    volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map;
+    volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map;
+    volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map;
+    volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map;
+    volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map;
+    volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map;
+    volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
+    volatile interrupt_matrix_lp_uart_intr_map_reg_t lp_uart_intr_map;
+    volatile interrupt_matrix_lp_i2c_intr_map_reg_t lp_i2c_intr_map;
+    volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
+    volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
+    volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
+    volatile interrupt_matrix_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map;
+    volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
+    volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
+    volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
+    volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
+    volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map;
+    volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map;
+    volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map;
+    volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map;
+    volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map;
+    volatile interrupt_matrix_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map;
+    volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map;
+    volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map;
+    volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map;
+    volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
+    volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
+    volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
+    volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
+    volatile interrupt_matrix_lp_apm0_intr_map_reg_t lp_apm0_intr_map;
+    volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map;
+    volatile interrupt_matrix_i2s_intr_map_reg_t i2s_intr_map;
+    volatile interrupt_matrix_uhci0_intr_map_reg_t uhci0_intr_map;
+    volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map;
+    volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map;
+    volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map;
+    volatile interrupt_matrix_can0_intr_map_reg_t can0_intr_map;
+    volatile interrupt_matrix_can1_intr_map_reg_t can1_intr_map;
+    volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map;
+    volatile interrupt_matrix_rmt_intr_map_reg_t rmt_intr_map;
+    volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map;
+    volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map;
+    volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map;
+    volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map;
+    volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map;
+    volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map;
+    volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map;
+    volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
+    volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
+    volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
+    volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map;
+    volatile interrupt_matrix_pwm_intr_map_reg_t pwm_intr_map;
+    volatile interrupt_matrix_pcnt_intr_map_reg_t pcnt_intr_map;
+    volatile interrupt_matrix_parl_io_intr_map_reg_t parl_io_intr_map;
+    volatile interrupt_matrix_slc0_intr_map_reg_t slc0_intr_map;
+    volatile interrupt_matrix_slc1_intr_map_reg_t slc1_intr_map;
+    volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map;
+    volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map;
+    volatile interrupt_matrix_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map;
+    volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map;
+    volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map;
+    volatile interrupt_matrix_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map;
+    volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map;
+    volatile interrupt_matrix_aes_intr_map_reg_t aes_intr_map;
+    volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map;
+    volatile interrupt_matrix_rsa_intr_map_reg_t rsa_intr_map;
+    volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map;
+    volatile interrupt_matrix_int_status_reg_0_reg_t int_status_reg_0;
+    volatile interrupt_matrix_int_status_reg_1_reg_t int_status_reg_1;
+    volatile interrupt_matrix_int_status_reg_2_reg_t int_status_reg_2;
+    volatile interrupt_matrix_clock_gate_reg_t clock_gate;
+    uint32_t reserved_144[430];
+    volatile interrupt_matrix_interrupt_reg_date_reg_t interrupt_reg_date;
+} interrupt_matrix_dev_t;
+
+extern interrupt_matrix_dev_t INTMTX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/intpri_reg.h b/components/soc/esp32c6/register/soc/intpri_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/intpri_reg.h
rename to components/soc/esp32c6/register/soc/intpri_reg.h
diff --git a/components/soc/esp32c6/include/soc/intpri_struct.h b/components/soc/esp32c6/register/soc/intpri_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/intpri_struct.h
rename to components/soc/esp32c6/register/soc/intpri_struct.h
diff --git a/components/soc/esp32c6/register/soc/io_mux_reg.h b/components/soc/esp32c6/register/soc/io_mux_reg.h
new file mode 100644
index 00000000000..0adf0203ef1
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/io_mux_reg.h
@@ -0,0 +1,362 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "soc/soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Used to enable sleep mode pin functions */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+
+#define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO2_REG               PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG               PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG               PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO5_REG               PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO6_REG               PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO7_REG               PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO8_REG               PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG               PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG              PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG              PERIPHS_IO_MUX_GPIO11_U
+#define IO_MUX_GPIO12_REG              PERIPHS_IO_MUX_GPIO12_U
+#define IO_MUX_GPIO13_REG              PERIPHS_IO_MUX_GPIO13_U
+#define IO_MUX_GPIO14_REG              PERIPHS_IO_MUX_GPIO14_U
+#define IO_MUX_GPIO15_REG              PERIPHS_IO_MUX_GPIO15_U
+#define IO_MUX_GPIO16_REG              PERIPHS_IO_MUX_U0TXD_U
+#define IO_MUX_GPIO17_REG              PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO18_REG              PERIPHS_IO_MUX_SDIO_CMD_U
+#define IO_MUX_GPIO19_REG              PERIPHS_IO_MUX_SDIO_CLK_U
+#define IO_MUX_GPIO20_REG              PERIPHS_IO_MUX_SDIO_DATA0_U
+#define IO_MUX_GPIO21_REG              PERIPHS_IO_MUX_SDIO_DATA1_U
+#define IO_MUX_GPIO22_REG              PERIPHS_IO_MUX_SDIO_DATA2_U
+#define IO_MUX_GPIO23_REG              PERIPHS_IO_MUX_SDIO_DATA3_U
+#define IO_MUX_GPIO24_REG              PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO25_REG              PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO26_REG              PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO27_REG              PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO28_REG              PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO29_REG              PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO30_REG              PERIPHS_IO_MUX_SPID_U
+
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define SPI_HD_GPIO_NUM              28
+#define SPI_WP_GPIO_NUM              26
+#define SPI_CS0_GPIO_NUM             24
+#define SPI_CLK_GPIO_NUM             29
+#define SPI_D_GPIO_NUM               30
+#define SPI_Q_GPIO_NUM               25
+
+#define SD_CLK_GPIO_NUM              19
+#define SD_CMD_GPIO_NUM              18
+#define SD_DATA0_GPIO_NUM            20
+#define SD_DATA1_GPIO_NUM            21
+#define SD_DATA2_GPIO_NUM            22
+#define SD_DATA3_GPIO_NUM            23
+
+#define USB_INT_PHY0_DM_GPIO_NUM              12
+#define USB_INT_PHY0_DP_GPIO_NUM              13
+
+#define EXT_OSC_SLOW_GPIO_NUM        0
+
+#define MAX_RTC_GPIO_NUM              7
+#define MAX_PAD_GPIO_NUM             30
+#define MAX_GPIO_NUM                 34
+#define DIG_IO_HOLD_BIT_SHIFT        32
+
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
+
+#define CLK_OUT3                                    0x1f
+#define CLK_OUT3_V                                  CLK_OUT3
+#define CLK_OUT3_S                                  10
+#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2                                    0x1f
+#define CLK_OUT2_V                                  CLK_OUT2
+#define CLK_OUT2_S                                  5
+#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1                                    0x1f
+#define CLK_OUT1_V                                  CLK_OUT1
+#define CLK_OUT1_S                                  0
+#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
+// definitions above are inherited from previous version of code, should double check
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_XTAL_32K_P_U           (REG_IO_MUX_BASE + 0x4)
+#define FUNC_XTAL_32K_P_GPIO0                                       1
+#define FUNC_XTAL_32K_P_GPIO0_0                                     0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U           (REG_IO_MUX_BASE + 0x8)
+#define FUNC_XTAL_32K_N_GPIO1                                       1
+#define FUNC_XTAL_32K_N_GPIO1_0                                     0
+
+#define PERIPHS_IO_MUX_GPIO2_U                (REG_IO_MUX_BASE + 0xC)
+#define FUNC_GPIO2_FSPIQ                                            2
+#define FUNC_GPIO2_GPIO2                                            1
+#define FUNC_GPIO2_GPIO2_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO3_U               (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO3_GPIO3                                            1
+#define FUNC_GPIO3_GPIO3_0                                          0
+
+#define PERIPHS_IO_MUX_MTMS_U                (REG_IO_MUX_BASE + 0x14)
+#define FUNC_MTMS_FSPIHD                                            2
+#define FUNC_MTMS_GPIO4                                             1
+#define FUNC_MTMS_MTMS                                              0
+
+#define PERIPHS_IO_MUX_MTDI_U                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_MTDI_FSPIWP                                            2
+#define FUNC_MTDI_GPIO5                                             1
+#define FUNC_MTDI_MTDI                                              0
+
+#define PERIPHS_IO_MUX_MTCK_U                (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_MTCK_FSPICLK                                           2
+#define FUNC_MTCK_GPIO6                                             1
+#define FUNC_MTCK_MTCK                                              0
+
+#define PERIPHS_IO_MUX_MTDO_U                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_MTDO_FSPID                                             2
+#define FUNC_MTDO_GPIO7                                             1
+#define FUNC_MTDO_MTDO                                              0
+
+#define PERIPHS_IO_MUX_GPIO8_U               (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_GPIO8                                            1
+#define FUNC_GPIO8_GPIO8_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO9_U               (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_GPIO9                                            1
+#define FUNC_GPIO9_GPIO9_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO10_U              (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_GPIO10_GPIO10                                          1
+#define FUNC_GPIO10_GPIO10_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO11_U              (REG_IO_MUX_BASE + 0x30)
+#define FUNC_GPIO11_GPIO11                                          1
+#define FUNC_GPIO11_GPIO11_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO12_U              (REG_IO_MUX_BASE + 0x34)
+#define FUNC_GPIO12_GPIO12                                          1
+#define FUNC_GPIO12_GPIO12_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO13_U              (REG_IO_MUX_BASE + 0x38)
+#define FUNC_GPIO13_GPIO13                                          1
+#define FUNC_GPIO13_GPIO13_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO14_U              (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_GPIO14_GPIO14                                          1
+#define FUNC_GPIO14_GPIO14_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO15_U              (REG_IO_MUX_BASE + 0x40)
+#define FUNC_GPIO15_GPIO15                                          1
+#define FUNC_GPIO15_GPIO15_0                                        0
+
+#define PERIPHS_IO_MUX_U0TXD_U               (REG_IO_MUX_BASE + 0x44)
+#define FUNC_U0TXD_FSPICS0                                          2
+#define FUNC_U0TXD_GPIO16                                           1
+#define FUNC_U0TXD_U0TXD                                            0
+
+#define PERIPHS_IO_MUX_U0RXD_U               (REG_IO_MUX_BASE + 0x48)
+#define FUNC_U0RXD_FSPICS1                                          2
+#define FUNC_U0RXD_GPIO17                                           1
+#define FUNC_U0RXD_U0RXD                                            0
+
+#define PERIPHS_IO_MUX_SDIO_CMD_U            (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_SDIO_CMD_FSPICS2                                       2
+#define FUNC_SDIO_CMD_GPIO18                                        1
+#define FUNC_SDIO_CMD_SDIO_CMD                                      0
+
+#define PERIPHS_IO_MUX_SDIO_CLK_U            (REG_IO_MUX_BASE + 0x50)
+#define FUNC_SDIO_CLK_FSPICS3                                       2
+#define FUNC_SDIO_CLK_GPIO19                                        1
+#define FUNC_SDIO_CLK_SDIO_CLK                                      0
+
+#define PERIPHS_IO_MUX_SDIO_DATA0_U          (REG_IO_MUX_BASE + 0x54)
+#define FUNC_SDIO_DATA0_FSPICS4                                     2
+#define FUNC_SDIO_DATA0_GPIO20                                      1
+#define FUNC_SDIO_DATA0_SDIO_DATA0                                  0
+
+#define PERIPHS_IO_MUX_SDIO_DATA1_U          (REG_IO_MUX_BASE + 0x58)
+#define FUNC_SDIO_DATA1_FSPICS5                                     2
+#define FUNC_SDIO_DATA1_GPIO21                                      1
+#define FUNC_SDIO_DATA1_SDIO_DATA1                                  0
+
+#define PERIPHS_IO_MUX_SDIO_DATA2_U          (REG_IO_MUX_BASE + 0x5C)
+#define FUNC_SDIO_DATA2_GPIO22                                      1
+#define FUNC_SDIO_DATA2_SDIO_DATA2                                  0
+
+#define PERIPHS_IO_MUX_SDIO_DATA3_U          (REG_IO_MUX_BASE + 0x60)
+#define FUNC_SDIO_DATA3_GPIO23                                      1
+#define FUNC_SDIO_DATA3_SDIO_DATA3                                  0
+
+#define PERIPHS_IO_MUX_SPICS0_U              (REG_IO_MUX_BASE + 0x64)
+#define FUNC_SPICS0_GPIO24                                          1
+#define FUNC_SPICS0_SPICS0                                          0
+
+#define PERIPHS_IO_MUX_SPIQ_U                (REG_IO_MUX_BASE + 0x68)
+#define FUNC_SPIQ_GPIO25                                            1
+#define FUNC_SPIQ_SPIQ                                              0
+
+#define PERIPHS_IO_MUX_SPIWP_U               (REG_IO_MUX_BASE + 0x6C)
+#define FUNC_SPIWP_GPIO26                                           1
+#define FUNC_SPIWP_SPIWP                                            0
+
+#define PERIPHS_IO_MUX_VDD_SPI_U             (REG_IO_MUX_BASE + 0x70)
+#define FUNC_VDD_SPI_GPIO27                                         1
+#define FUNC_VDD_SPI_GPIO27_0                                       0
+
+#define PERIPHS_IO_MUX_SPIHD_U               (REG_IO_MUX_BASE + 0x74)
+#define FUNC_SPIHD_GPIO28                                           1
+#define FUNC_SPIHD_SPIHD                                            0
+
+#define PERIPHS_IO_MUX_SPICLK_U              (REG_IO_MUX_BASE + 0x78)
+#define FUNC_SPICLK_GPIO29                                          1
+#define FUNC_SPICLK_SPICLK                                          0
+
+#define PERIPHS_IO_MUX_SPID_U                (REG_IO_MUX_BASE + 0x7C)
+#define FUNC_SPID_GPIO30                                            1
+#define FUNC_SPID_SPID                                              0
+
+/** IO_MUX_PIN_CTRL_REG register
+ *  Clock Output Configuration Register
+ */
+#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
+/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15;
+ *  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
+ *  CLK_OUT_out1 can be found in peripheral output signals.
+ */
+#define IO_MUX_CLK_OUT1    0x0000001FU
+#define IO_MUX_CLK_OUT1_M  (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
+#define IO_MUX_CLK_OUT1_V  0x0000001FU
+#define IO_MUX_CLK_OUT1_S  0
+/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15;
+ *  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
+ *  CLK_OUT_out2 can be found in peripheral output signals.
+ */
+#define IO_MUX_CLK_OUT2    0x0000001FU
+#define IO_MUX_CLK_OUT2_M  (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
+#define IO_MUX_CLK_OUT2_V  0x0000001FU
+#define IO_MUX_CLK_OUT2_S  5
+/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7;
+ *  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
+ *  CLK_OUT_out3 can be found in peripheral output signals.
+ */
+#define IO_MUX_CLK_OUT3    0x0000001FU
+#define IO_MUX_CLK_OUT3_M  (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
+#define IO_MUX_CLK_OUT3_V  0x0000001FU
+#define IO_MUX_CLK_OUT3_S  10
+
+/** IO_MUX_MODEM_DIAG_EN_REG register
+ *  GPIO MATRIX Configure Register for modem diag
+ */
+#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
+/** IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [31:0]; default: 0;
+ *  bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio
+ *  matrix. 0:enable other signals into gpio matrix
+ */
+#define IO_MUX_MODEM_DIAG_EN    0xFFFFFFFFU
+#define IO_MUX_MODEM_DIAG_EN_M  (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
+#define IO_MUX_MODEM_DIAG_EN_V  0xFFFFFFFFU
+#define IO_MUX_MODEM_DIAG_EN_S  0
+
+/** IO_MUX_DATE_REG register
+ *  IO MUX Version Control Register
+ */
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 35655776;
+ *  Version control register
+ */
+#define IO_MUX_REG_DATE    0x0FFFFFFFU
+#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
+#define IO_MUX_REG_DATE_V  0x0FFFFFFFU
+#define IO_MUX_REG_DATE_S  0
diff --git a/components/soc/esp32c6/include/soc/ledc_reg.h b/components/soc/esp32c6/register/soc/ledc_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ledc_reg.h
rename to components/soc/esp32c6/register/soc/ledc_reg.h
diff --git a/components/soc/esp32c6/include/soc/ledc_struct.h b/components/soc/esp32c6/register/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/ledc_struct.h
rename to components/soc/esp32c6/register/soc/ledc_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c6/register/soc/lp_analog_peri_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_analog_peri_reg.h
rename to components/soc/esp32c6/register/soc/lp_analog_peri_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c6/register/soc/lp_analog_peri_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_analog_peri_struct.h
rename to components/soc/esp32c6/register/soc/lp_analog_peri_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_aon_reg.h b/components/soc/esp32c6/register/soc/lp_aon_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_aon_reg.h
rename to components/soc/esp32c6/register/soc/lp_aon_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_aon_struct.h b/components/soc/esp32c6/register/soc/lp_aon_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_aon_struct.h
rename to components/soc/esp32c6/register/soc/lp_aon_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_apm0_reg.h b/components/soc/esp32c6/register/soc/lp_apm0_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_apm0_reg.h
rename to components/soc/esp32c6/register/soc/lp_apm0_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_apm0_struct.h b/components/soc/esp32c6/register/soc/lp_apm0_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_apm0_struct.h
rename to components/soc/esp32c6/register/soc/lp_apm0_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_apm_reg.h b/components/soc/esp32c6/register/soc/lp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_apm_reg.h
rename to components/soc/esp32c6/register/soc/lp_apm_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_apm_struct.h b/components/soc/esp32c6/register/soc/lp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_apm_struct.h
rename to components/soc/esp32c6/register/soc/lp_apm_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_clkrst_reg.h b/components/soc/esp32c6/register/soc/lp_clkrst_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_clkrst_reg.h
rename to components/soc/esp32c6/register/soc/lp_clkrst_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_clkrst_struct.h b/components/soc/esp32c6/register/soc/lp_clkrst_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_clkrst_struct.h
rename to components/soc/esp32c6/register/soc/lp_clkrst_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h b/components/soc/esp32c6/register/soc/lp_i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_i2c_ana_mst_reg.h
rename to components/soc/esp32c6/register/soc/lp_i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h b/components/soc/esp32c6/register/soc/lp_i2c_ana_mst_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_i2c_ana_mst_struct.h
rename to components/soc/esp32c6/register/soc/lp_i2c_ana_mst_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_i2c_reg.h b/components/soc/esp32c6/register/soc/lp_i2c_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_i2c_reg.h
rename to components/soc/esp32c6/register/soc/lp_i2c_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_i2c_struct.h b/components/soc/esp32c6/register/soc/lp_i2c_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_i2c_struct.h
rename to components/soc/esp32c6/register/soc/lp_i2c_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_io_reg.h b/components/soc/esp32c6/register/soc/lp_io_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_io_reg.h
rename to components/soc/esp32c6/register/soc/lp_io_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_io_struct.h b/components/soc/esp32c6/register/soc/lp_io_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_io_struct.h
rename to components/soc/esp32c6/register/soc/lp_io_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_tee_reg.h b/components/soc/esp32c6/register/soc/lp_tee_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_tee_reg.h
rename to components/soc/esp32c6/register/soc/lp_tee_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_tee_struct.h b/components/soc/esp32c6/register/soc/lp_tee_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_tee_struct.h
rename to components/soc/esp32c6/register/soc/lp_tee_struct.h
diff --git a/components/soc/esp32c6/include/soc/lp_timer_reg.h b/components/soc/esp32c6/register/soc/lp_timer_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_timer_reg.h
rename to components/soc/esp32c6/register/soc/lp_timer_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_timer_struct.h b/components/soc/esp32c6/register/soc/lp_timer_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_timer_struct.h
rename to components/soc/esp32c6/register/soc/lp_timer_struct.h
diff --git a/components/soc/esp32c6/register/soc/lp_uart_reg.h b/components/soc/esp32c6/register/soc/lp_uart_reg.h
new file mode 100644
index 00000000000..017abf55f8e
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/lp_uart_reg.h
@@ -0,0 +1,1381 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0)
+/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define LP_UART_RXFIFO_RD_BYTE    0x000000FFU
+#define LP_UART_RXFIFO_RD_BYTE_M  (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S)
+#define LP_UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define LP_UART_RXFIFO_RD_BYTE_S  0
+
+/** LP_UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4)
+/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define LP_UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_RAW_M  (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S)
+#define LP_UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_RAW_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_M  (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S)
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define LP_UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_RAW_M  (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S)
+#define LP_UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_RAW_S  2
+/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define LP_UART_FRM_ERR_INT_RAW    (BIT(3))
+#define LP_UART_FRM_ERR_INT_RAW_M  (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S)
+#define LP_UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_RAW_S  3
+/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define LP_UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_RAW_M  (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S)
+#define LP_UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_RAW_S  4
+/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define LP_UART_DSR_CHG_INT_RAW    (BIT(5))
+#define LP_UART_DSR_CHG_INT_RAW_M  (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S)
+#define LP_UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_RAW_S  5
+/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define LP_UART_CTS_CHG_INT_RAW    (BIT(6))
+#define LP_UART_CTS_CHG_INT_RAW_M  (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S)
+#define LP_UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_RAW_S  6
+/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define LP_UART_BRK_DET_INT_RAW    (BIT(7))
+#define LP_UART_BRK_DET_INT_RAW_M  (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S)
+#define LP_UART_BRK_DET_INT_RAW_V  0x00000001U
+#define LP_UART_BRK_DET_INT_RAW_S  7
+/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_RAW_M  (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S)
+#define LP_UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_RAW_S  8
+/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define LP_UART_SW_XON_INT_RAW    (BIT(9))
+#define LP_UART_SW_XON_INT_RAW_M  (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S)
+#define LP_UART_SW_XON_INT_RAW_V  0x00000001U
+#define LP_UART_SW_XON_INT_RAW_S  9
+/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define LP_UART_SW_XOFF_INT_RAW    (BIT(10))
+#define LP_UART_SW_XOFF_INT_RAW_M  (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S)
+#define LP_UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_RAW_S  10
+/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define LP_UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_RAW_M  (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S)
+#define LP_UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_RAW_S  11
+/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define LP_UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_RAW_M  (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S)
+#define LP_UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_RAW_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M  (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define LP_UART_TX_DONE_INT_RAW    (BIT(14))
+#define LP_UART_TX_DONE_INT_RAW_M  (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S)
+#define LP_UART_TX_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_DONE_INT_RAW_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M  (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define LP_UART_WAKEUP_INT_RAW    (BIT(19))
+#define LP_UART_WAKEUP_INT_RAW_M  (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S)
+#define LP_UART_WAKEUP_INT_RAW_V  0x00000001U
+#define LP_UART_WAKEUP_INT_RAW_S  19
+
+/** LP_UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8)
+/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_ST_M  (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S)
+#define LP_UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_ST_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_ST_M  (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S)
+#define LP_UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_ST_S  1
+/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define LP_UART_PARITY_ERR_INT_ST    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_ST_M  (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S)
+#define LP_UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_ST_S  2
+/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define LP_UART_FRM_ERR_INT_ST    (BIT(3))
+#define LP_UART_FRM_ERR_INT_ST_M  (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S)
+#define LP_UART_FRM_ERR_INT_ST_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_ST_S  3
+/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_ST_M  (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S)
+#define LP_UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_ST_S  4
+/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define LP_UART_DSR_CHG_INT_ST    (BIT(5))
+#define LP_UART_DSR_CHG_INT_ST_M  (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S)
+#define LP_UART_DSR_CHG_INT_ST_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_ST_S  5
+/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define LP_UART_CTS_CHG_INT_ST    (BIT(6))
+#define LP_UART_CTS_CHG_INT_ST_M  (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S)
+#define LP_UART_CTS_CHG_INT_ST_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_ST_S  6
+/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define LP_UART_BRK_DET_INT_ST    (BIT(7))
+#define LP_UART_BRK_DET_INT_ST_M  (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S)
+#define LP_UART_BRK_DET_INT_ST_V  0x00000001U
+#define LP_UART_BRK_DET_INT_ST_S  7
+/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_ST_M  (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S)
+#define LP_UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_ST_S  8
+/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define LP_UART_SW_XON_INT_ST    (BIT(9))
+#define LP_UART_SW_XON_INT_ST_M  (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S)
+#define LP_UART_SW_XON_INT_ST_V  0x00000001U
+#define LP_UART_SW_XON_INT_ST_S  9
+/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define LP_UART_SW_XOFF_INT_ST    (BIT(10))
+#define LP_UART_SW_XOFF_INT_ST_M  (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S)
+#define LP_UART_SW_XOFF_INT_ST_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_ST_S  10
+/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define LP_UART_GLITCH_DET_INT_ST    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_ST_M  (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S)
+#define LP_UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_ST_S  11
+/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define LP_UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_ST_M  (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S)
+#define LP_UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_ST_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define LP_UART_TX_DONE_INT_ST    (BIT(14))
+#define LP_UART_TX_DONE_INT_ST_M  (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S)
+#define LP_UART_TX_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_DONE_INT_ST_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M  (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define LP_UART_WAKEUP_INT_ST    (BIT(19))
+#define LP_UART_WAKEUP_INT_ST_M  (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S)
+#define LP_UART_WAKEUP_INT_ST_V  0x00000001U
+#define LP_UART_WAKEUP_INT_ST_S  19
+
+/** LP_UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc)
+/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define LP_UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_ENA_M  (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S)
+#define LP_UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_ENA_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_M  (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S)
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define LP_UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_ENA_M  (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S)
+#define LP_UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_ENA_S  2
+/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define LP_UART_FRM_ERR_INT_ENA    (BIT(3))
+#define LP_UART_FRM_ERR_INT_ENA_M  (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S)
+#define LP_UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_ENA_S  3
+/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define LP_UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_ENA_M  (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S)
+#define LP_UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_ENA_S  4
+/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define LP_UART_DSR_CHG_INT_ENA    (BIT(5))
+#define LP_UART_DSR_CHG_INT_ENA_M  (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S)
+#define LP_UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_ENA_S  5
+/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define LP_UART_CTS_CHG_INT_ENA    (BIT(6))
+#define LP_UART_CTS_CHG_INT_ENA_M  (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S)
+#define LP_UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_ENA_S  6
+/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define LP_UART_BRK_DET_INT_ENA    (BIT(7))
+#define LP_UART_BRK_DET_INT_ENA_M  (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S)
+#define LP_UART_BRK_DET_INT_ENA_V  0x00000001U
+#define LP_UART_BRK_DET_INT_ENA_S  7
+/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_ENA_M  (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S)
+#define LP_UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_ENA_S  8
+/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define LP_UART_SW_XON_INT_ENA    (BIT(9))
+#define LP_UART_SW_XON_INT_ENA_M  (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S)
+#define LP_UART_SW_XON_INT_ENA_V  0x00000001U
+#define LP_UART_SW_XON_INT_ENA_S  9
+/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define LP_UART_SW_XOFF_INT_ENA    (BIT(10))
+#define LP_UART_SW_XOFF_INT_ENA_M  (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S)
+#define LP_UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_ENA_S  10
+/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define LP_UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_ENA_M  (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S)
+#define LP_UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_ENA_S  11
+/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define LP_UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_ENA_M  (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S)
+#define LP_UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_ENA_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define LP_UART_TX_DONE_INT_ENA    (BIT(14))
+#define LP_UART_TX_DONE_INT_ENA_M  (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S)
+#define LP_UART_TX_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_DONE_INT_ENA_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M  (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define LP_UART_WAKEUP_INT_ENA    (BIT(19))
+#define LP_UART_WAKEUP_INT_ENA_M  (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S)
+#define LP_UART_WAKEUP_INT_ENA_V  0x00000001U
+#define LP_UART_WAKEUP_INT_ENA_S  19
+
+/** LP_UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10)
+/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_CLR_M  (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S)
+#define LP_UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_CLR_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_M  (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S)
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define LP_UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_CLR_M  (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S)
+#define LP_UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_CLR_S  2
+/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define LP_UART_FRM_ERR_INT_CLR    (BIT(3))
+#define LP_UART_FRM_ERR_INT_CLR_M  (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S)
+#define LP_UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_CLR_S  3
+/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_CLR_M  (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S)
+#define LP_UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_CLR_S  4
+/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define LP_UART_DSR_CHG_INT_CLR    (BIT(5))
+#define LP_UART_DSR_CHG_INT_CLR_M  (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S)
+#define LP_UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_CLR_S  5
+/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define LP_UART_CTS_CHG_INT_CLR    (BIT(6))
+#define LP_UART_CTS_CHG_INT_CLR_M  (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S)
+#define LP_UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_CLR_S  6
+/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define LP_UART_BRK_DET_INT_CLR    (BIT(7))
+#define LP_UART_BRK_DET_INT_CLR_M  (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S)
+#define LP_UART_BRK_DET_INT_CLR_V  0x00000001U
+#define LP_UART_BRK_DET_INT_CLR_S  7
+/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_CLR_M  (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S)
+#define LP_UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_CLR_S  8
+/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define LP_UART_SW_XON_INT_CLR    (BIT(9))
+#define LP_UART_SW_XON_INT_CLR_M  (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S)
+#define LP_UART_SW_XON_INT_CLR_V  0x00000001U
+#define LP_UART_SW_XON_INT_CLR_S  9
+/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define LP_UART_SW_XOFF_INT_CLR    (BIT(10))
+#define LP_UART_SW_XOFF_INT_CLR_M  (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S)
+#define LP_UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_CLR_S  10
+/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define LP_UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_CLR_M  (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S)
+#define LP_UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_CLR_S  11
+/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define LP_UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_CLR_M  (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S)
+#define LP_UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_CLR_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M  (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define LP_UART_TX_DONE_INT_CLR    (BIT(14))
+#define LP_UART_TX_DONE_INT_CLR_M  (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S)
+#define LP_UART_TX_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_DONE_INT_CLR_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M  (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define LP_UART_WAKEUP_INT_CLR    (BIT(19))
+#define LP_UART_WAKEUP_INT_CLR_M  (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S)
+#define LP_UART_WAKEUP_INT_CLR_V  0x00000001U
+#define LP_UART_WAKEUP_INT_CLR_S  19
+
+/** LP_UART_CLKDIV_SYNC_REG register
+ *  Clock divider configuration
+ */
+#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14)
+/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define LP_UART_CLKDIV    0x00000FFFU
+#define LP_UART_CLKDIV_M  (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S)
+#define LP_UART_CLKDIV_V  0x00000FFFU
+#define LP_UART_CLKDIV_S  0
+/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define LP_UART_CLKDIV_FRAG    0x0000000FU
+#define LP_UART_CLKDIV_FRAG_M  (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S)
+#define LP_UART_CLKDIV_FRAG_V  0x0000000FU
+#define LP_UART_CLKDIV_FRAG_S  20
+
+/** LP_UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18)
+/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define LP_UART_GLITCH_FILT    0x000000FFU
+#define LP_UART_GLITCH_FILT_M  (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S)
+#define LP_UART_GLITCH_FILT_V  0x000000FFU
+#define LP_UART_GLITCH_FILT_S  0
+/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define LP_UART_GLITCH_FILT_EN    (BIT(8))
+#define LP_UART_GLITCH_FILT_EN_M  (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S)
+#define LP_UART_GLITCH_FILT_EN_V  0x00000001U
+#define LP_UART_GLITCH_FILT_EN_S  8
+
+/** LP_UART_STATUS_REG register
+ *  UART status register
+ */
+#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c)
+/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define LP_UART_RXFIFO_CNT    0x0000001FU
+#define LP_UART_RXFIFO_CNT_M  (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S)
+#define LP_UART_RXFIFO_CNT_V  0x0000001FU
+#define LP_UART_RXFIFO_CNT_S  3
+/** LP_UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define LP_UART_DSRN    (BIT(13))
+#define LP_UART_DSRN_M  (LP_UART_DSRN_V << LP_UART_DSRN_S)
+#define LP_UART_DSRN_V  0x00000001U
+#define LP_UART_DSRN_S  13
+/** LP_UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define LP_UART_CTSN    (BIT(14))
+#define LP_UART_CTSN_M  (LP_UART_CTSN_V << LP_UART_CTSN_S)
+#define LP_UART_CTSN_V  0x00000001U
+#define LP_UART_CTSN_S  14
+/** LP_UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define LP_UART_RXD    (BIT(15))
+#define LP_UART_RXD_M  (LP_UART_RXD_V << LP_UART_RXD_S)
+#define LP_UART_RXD_V  0x00000001U
+#define LP_UART_RXD_S  15
+/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define LP_UART_TXFIFO_CNT    0x0000001FU
+#define LP_UART_TXFIFO_CNT_M  (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S)
+#define LP_UART_TXFIFO_CNT_V  0x0000001FU
+#define LP_UART_TXFIFO_CNT_S  19
+/** LP_UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define LP_UART_DTRN    (BIT(29))
+#define LP_UART_DTRN_M  (LP_UART_DTRN_V << LP_UART_DTRN_S)
+#define LP_UART_DTRN_V  0x00000001U
+#define LP_UART_DTRN_S  29
+/** LP_UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define LP_UART_RTSN    (BIT(30))
+#define LP_UART_RTSN_M  (LP_UART_RTSN_V << LP_UART_RTSN_S)
+#define LP_UART_RTSN_V  0x00000001U
+#define LP_UART_RTSN_S  30
+/** LP_UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define LP_UART_TXD    (BIT(31))
+#define LP_UART_TXD_M  (LP_UART_TXD_V << LP_UART_TXD_S)
+#define LP_UART_TXD_V  0x00000001U
+#define LP_UART_TXD_S  31
+
+/** LP_UART_CONF0_SYNC_REG register
+ *  Configuration register 0
+ */
+#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20)
+/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define LP_UART_PARITY    (BIT(0))
+#define LP_UART_PARITY_M  (LP_UART_PARITY_V << LP_UART_PARITY_S)
+#define LP_UART_PARITY_V  0x00000001U
+#define LP_UART_PARITY_S  0
+/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define LP_UART_PARITY_EN    (BIT(1))
+#define LP_UART_PARITY_EN_M  (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S)
+#define LP_UART_PARITY_EN_V  0x00000001U
+#define LP_UART_PARITY_EN_S  1
+/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define LP_UART_BIT_NUM    0x00000003U
+#define LP_UART_BIT_NUM_M  (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S)
+#define LP_UART_BIT_NUM_V  0x00000003U
+#define LP_UART_BIT_NUM_S  2
+/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define LP_UART_STOP_BIT_NUM    0x00000003U
+#define LP_UART_STOP_BIT_NUM_M  (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S)
+#define LP_UART_STOP_BIT_NUM_V  0x00000003U
+#define LP_UART_STOP_BIT_NUM_S  4
+/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define LP_UART_TXD_BRK    (BIT(6))
+#define LP_UART_TXD_BRK_M  (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S)
+#define LP_UART_TXD_BRK_V  0x00000001U
+#define LP_UART_TXD_BRK_S  6
+/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define LP_UART_LOOPBACK    (BIT(12))
+#define LP_UART_LOOPBACK_M  (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S)
+#define LP_UART_LOOPBACK_V  0x00000001U
+#define LP_UART_LOOPBACK_S  12
+/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define LP_UART_TX_FLOW_EN    (BIT(13))
+#define LP_UART_TX_FLOW_EN_M  (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S)
+#define LP_UART_TX_FLOW_EN_V  0x00000001U
+#define LP_UART_TX_FLOW_EN_S  13
+/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define LP_UART_RXD_INV    (BIT(15))
+#define LP_UART_RXD_INV_M  (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S)
+#define LP_UART_RXD_INV_V  0x00000001U
+#define LP_UART_RXD_INV_S  15
+/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define LP_UART_TXD_INV    (BIT(16))
+#define LP_UART_TXD_INV_M  (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S)
+#define LP_UART_TXD_INV_V  0x00000001U
+#define LP_UART_TXD_INV_S  16
+/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define LP_UART_DIS_RX_DAT_OVF    (BIT(17))
+#define LP_UART_DIS_RX_DAT_OVF_M  (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S)
+#define LP_UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define LP_UART_DIS_RX_DAT_OVF_S  17
+/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define LP_UART_ERR_WR_MASK    (BIT(18))
+#define LP_UART_ERR_WR_MASK_M  (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S)
+#define LP_UART_ERR_WR_MASK_V  0x00000001U
+#define LP_UART_ERR_WR_MASK_S  18
+/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  UART memory clock gate enable signal.
+ */
+#define LP_UART_MEM_CLK_EN    (BIT(20))
+#define LP_UART_MEM_CLK_EN_M  (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S)
+#define LP_UART_MEM_CLK_EN_V  0x00000001U
+#define LP_UART_MEM_CLK_EN_S  20
+/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define LP_UART_SW_RTS    (BIT(21))
+#define LP_UART_SW_RTS_M  (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S)
+#define LP_UART_SW_RTS_V  0x00000001U
+#define LP_UART_SW_RTS_S  21
+/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define LP_UART_RXFIFO_RST    (BIT(22))
+#define LP_UART_RXFIFO_RST_M  (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S)
+#define LP_UART_RXFIFO_RST_V  0x00000001U
+#define LP_UART_RXFIFO_RST_S  22
+/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define LP_UART_TXFIFO_RST    (BIT(23))
+#define LP_UART_TXFIFO_RST_M  (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S)
+#define LP_UART_TXFIFO_RST_V  0x00000001U
+#define LP_UART_TXFIFO_RST_S  23
+
+/** LP_UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24)
+/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define LP_UART_RXFIFO_FULL_THRHD    0x0000001FU
+#define LP_UART_RXFIFO_FULL_THRHD_M  (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S)
+#define LP_UART_RXFIFO_FULL_THRHD_V  0x0000001FU
+#define LP_UART_RXFIFO_FULL_THRHD_S  3
+/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define LP_UART_TXFIFO_EMPTY_THRHD    0x0000001FU
+#define LP_UART_TXFIFO_EMPTY_THRHD_M  (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S)
+#define LP_UART_TXFIFO_EMPTY_THRHD_V  0x0000001FU
+#define LP_UART_TXFIFO_EMPTY_THRHD_S  11
+/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define LP_UART_CTS_INV    (BIT(16))
+#define LP_UART_CTS_INV_M  (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S)
+#define LP_UART_CTS_INV_V  0x00000001U
+#define LP_UART_CTS_INV_S  16
+/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define LP_UART_DSR_INV    (BIT(17))
+#define LP_UART_DSR_INV_M  (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S)
+#define LP_UART_DSR_INV_V  0x00000001U
+#define LP_UART_DSR_INV_S  17
+/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define LP_UART_RTS_INV    (BIT(18))
+#define LP_UART_RTS_INV_M  (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S)
+#define LP_UART_RTS_INV_V  0x00000001U
+#define LP_UART_RTS_INV_S  18
+/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define LP_UART_DTR_INV    (BIT(19))
+#define LP_UART_DTR_INV_M  (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S)
+#define LP_UART_DTR_INV_V  0x00000001U
+#define LP_UART_DTR_INV_S  19
+/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define LP_UART_SW_DTR    (BIT(20))
+#define LP_UART_SW_DTR_M  (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S)
+#define LP_UART_SW_DTR_V  0x00000001U
+#define LP_UART_SW_DTR_S  20
+/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define LP_UART_CLK_EN    (BIT(21))
+#define LP_UART_CLK_EN_M  (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S)
+#define LP_UART_CLK_EN_V  0x00000001U
+#define LP_UART_CLK_EN_S  21
+
+/** LP_UART_HWFC_CONF_SYNC_REG register
+ *  Hardware flow-control configuration
+ */
+#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c)
+/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define LP_UART_RX_FLOW_THRHD    0x0000001FU
+#define LP_UART_RX_FLOW_THRHD_M  (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S)
+#define LP_UART_RX_FLOW_THRHD_V  0x0000001FU
+#define LP_UART_RX_FLOW_THRHD_S  3
+/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define LP_UART_RX_FLOW_EN    (BIT(8))
+#define LP_UART_RX_FLOW_EN_M  (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S)
+#define LP_UART_RX_FLOW_EN_V  0x00000001U
+#define LP_UART_RX_FLOW_EN_S  8
+
+/** LP_UART_SLEEP_CONF0_REG register
+ *  UART sleep configure register 0
+ */
+#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30)
+/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define LP_UART_WK_CHAR1    0x000000FFU
+#define LP_UART_WK_CHAR1_M  (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S)
+#define LP_UART_WK_CHAR1_V  0x000000FFU
+#define LP_UART_WK_CHAR1_S  0
+/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define LP_UART_WK_CHAR2    0x000000FFU
+#define LP_UART_WK_CHAR2_M  (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S)
+#define LP_UART_WK_CHAR2_V  0x000000FFU
+#define LP_UART_WK_CHAR2_S  8
+/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define LP_UART_WK_CHAR3    0x000000FFU
+#define LP_UART_WK_CHAR3_M  (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S)
+#define LP_UART_WK_CHAR3_V  0x000000FFU
+#define LP_UART_WK_CHAR3_S  16
+/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define LP_UART_WK_CHAR4    0x000000FFU
+#define LP_UART_WK_CHAR4_M  (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S)
+#define LP_UART_WK_CHAR4_V  0x000000FFU
+#define LP_UART_WK_CHAR4_S  24
+
+/** LP_UART_SLEEP_CONF1_REG register
+ *  UART sleep configure register 1
+ */
+#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34)
+/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define LP_UART_WK_CHAR0    0x000000FFU
+#define LP_UART_WK_CHAR0_M  (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S)
+#define LP_UART_WK_CHAR0_V  0x000000FFU
+#define LP_UART_WK_CHAR0_S  0
+
+/** LP_UART_SLEEP_CONF2_REG register
+ *  UART sleep configure register 2
+ */
+#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38)
+/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define LP_UART_ACTIVE_THRESHOLD    0x000003FFU
+#define LP_UART_ACTIVE_THRESHOLD_M  (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S)
+#define LP_UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define LP_UART_ACTIVE_THRESHOLD_S  0
+/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define LP_UART_RX_WAKE_UP_THRHD    0x0000001FU
+#define LP_UART_RX_WAKE_UP_THRHD_M  (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S)
+#define LP_UART_RX_WAKE_UP_THRHD_V  0x0000001FU
+#define LP_UART_RX_WAKE_UP_THRHD_S  13
+/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define LP_UART_WK_CHAR_NUM    0x00000007U
+#define LP_UART_WK_CHAR_NUM_M  (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S)
+#define LP_UART_WK_CHAR_NUM_V  0x00000007U
+#define LP_UART_WK_CHAR_NUM_S  18
+/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define LP_UART_WK_CHAR_MASK    0x0000001FU
+#define LP_UART_WK_CHAR_MASK_M  (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S)
+#define LP_UART_WK_CHAR_MASK_V  0x0000001FU
+#define LP_UART_WK_CHAR_MASK_S  21
+/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define LP_UART_WK_MODE_SEL    0x00000003U
+#define LP_UART_WK_MODE_SEL_M  (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S)
+#define LP_UART_WK_MODE_SEL_V  0x00000003U
+#define LP_UART_WK_MODE_SEL_S  26
+
+/** LP_UART_SWFC_CONF0_SYNC_REG register
+ *  Software flow-control character configuration
+ */
+#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c)
+/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define LP_UART_XON_CHAR    0x000000FFU
+#define LP_UART_XON_CHAR_M  (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S)
+#define LP_UART_XON_CHAR_V  0x000000FFU
+#define LP_UART_XON_CHAR_S  0
+/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define LP_UART_XOFF_CHAR    0x000000FFU
+#define LP_UART_XOFF_CHAR_M  (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S)
+#define LP_UART_XOFF_CHAR_V  0x000000FFU
+#define LP_UART_XOFF_CHAR_S  8
+/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define LP_UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define LP_UART_XON_XOFF_STILL_SEND_M  (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S)
+#define LP_UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define LP_UART_XON_XOFF_STILL_SEND_S  16
+/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define LP_UART_SW_FLOW_CON_EN    (BIT(17))
+#define LP_UART_SW_FLOW_CON_EN_M  (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S)
+#define LP_UART_SW_FLOW_CON_EN_V  0x00000001U
+#define LP_UART_SW_FLOW_CON_EN_S  17
+/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define LP_UART_XONOFF_DEL    (BIT(18))
+#define LP_UART_XONOFF_DEL_M  (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S)
+#define LP_UART_XONOFF_DEL_V  0x00000001U
+#define LP_UART_XONOFF_DEL_S  18
+/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define LP_UART_FORCE_XON    (BIT(19))
+#define LP_UART_FORCE_XON_M  (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S)
+#define LP_UART_FORCE_XON_V  0x00000001U
+#define LP_UART_FORCE_XON_S  19
+/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define LP_UART_FORCE_XOFF    (BIT(20))
+#define LP_UART_FORCE_XOFF_M  (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S)
+#define LP_UART_FORCE_XOFF_V  0x00000001U
+#define LP_UART_FORCE_XOFF_S  20
+/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define LP_UART_SEND_XON    (BIT(21))
+#define LP_UART_SEND_XON_M  (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S)
+#define LP_UART_SEND_XON_V  0x00000001U
+#define LP_UART_SEND_XON_S  21
+/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define LP_UART_SEND_XOFF    (BIT(22))
+#define LP_UART_SEND_XOFF_M  (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S)
+#define LP_UART_SEND_XOFF_V  0x00000001U
+#define LP_UART_SEND_XOFF_S  22
+
+/** LP_UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40)
+/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define LP_UART_XON_THRESHOLD    0x0000001FU
+#define LP_UART_XON_THRESHOLD_M  (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S)
+#define LP_UART_XON_THRESHOLD_V  0x0000001FU
+#define LP_UART_XON_THRESHOLD_S  3
+/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define LP_UART_XOFF_THRESHOLD    0x0000001FU
+#define LP_UART_XOFF_THRESHOLD_M  (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S)
+#define LP_UART_XOFF_THRESHOLD_V  0x0000001FU
+#define LP_UART_XOFF_THRESHOLD_S  11
+
+/** LP_UART_TXBRK_CONF_SYNC_REG register
+ *  Tx Break character configuration
+ */
+#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44)
+/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define LP_UART_TX_BRK_NUM    0x000000FFU
+#define LP_UART_TX_BRK_NUM_M  (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S)
+#define LP_UART_TX_BRK_NUM_V  0x000000FFU
+#define LP_UART_TX_BRK_NUM_S  0
+
+/** LP_UART_IDLE_CONF_SYNC_REG register
+ *  Frame-end idle configuration
+ */
+#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48)
+/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define LP_UART_RX_IDLE_THRHD    0x000003FFU
+#define LP_UART_RX_IDLE_THRHD_M  (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S)
+#define LP_UART_RX_IDLE_THRHD_V  0x000003FFU
+#define LP_UART_RX_IDLE_THRHD_S  0
+/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define LP_UART_TX_IDLE_NUM    0x000003FFU
+#define LP_UART_TX_IDLE_NUM_M  (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S)
+#define LP_UART_TX_IDLE_NUM_V  0x000003FFU
+#define LP_UART_TX_IDLE_NUM_S  10
+
+/** LP_UART_RS485_CONF_SYNC_REG register
+ *  RS485 mode configuration
+ */
+#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c)
+/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define LP_UART_DL0_EN    (BIT(1))
+#define LP_UART_DL0_EN_M  (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S)
+#define LP_UART_DL0_EN_V  0x00000001U
+#define LP_UART_DL0_EN_S  1
+/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define LP_UART_DL1_EN    (BIT(2))
+#define LP_UART_DL1_EN_M  (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S)
+#define LP_UART_DL1_EN_V  0x00000001U
+#define LP_UART_DL1_EN_S  2
+
+/** LP_UART_AT_CMD_PRECNT_SYNC_REG register
+ *  Pre-sequence timing configuration
+ */
+#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50)
+/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define LP_UART_PRE_IDLE_NUM    0x0000FFFFU
+#define LP_UART_PRE_IDLE_NUM_M  (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S)
+#define LP_UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define LP_UART_PRE_IDLE_NUM_S  0
+
+/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register
+ *  Post-sequence timing configuration
+ */
+#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54)
+/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define LP_UART_POST_IDLE_NUM    0x0000FFFFU
+#define LP_UART_POST_IDLE_NUM_M  (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S)
+#define LP_UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define LP_UART_POST_IDLE_NUM_S  0
+
+/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register
+ *  Timeout configuration
+ */
+#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58)
+/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define LP_UART_RX_GAP_TOUT    0x0000FFFFU
+#define LP_UART_RX_GAP_TOUT_M  (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S)
+#define LP_UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define LP_UART_RX_GAP_TOUT_S  0
+
+/** LP_UART_AT_CMD_CHAR_SYNC_REG register
+ *  AT escape sequence detection configuration
+ */
+#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c)
+/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define LP_UART_AT_CMD_CHAR    0x000000FFU
+#define LP_UART_AT_CMD_CHAR_M  (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S)
+#define LP_UART_AT_CMD_CHAR_V  0x000000FFU
+#define LP_UART_AT_CMD_CHAR_S  0
+/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define LP_UART_CHAR_NUM    0x000000FFU
+#define LP_UART_CHAR_NUM_M  (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S)
+#define LP_UART_CHAR_NUM_V  0x000000FFU
+#define LP_UART_CHAR_NUM_S  8
+
+/** LP_UART_MEM_CONF_REG register
+ *  UART memory power configuration
+ */
+#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60)
+/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define LP_UART_MEM_FORCE_PD    (BIT(25))
+#define LP_UART_MEM_FORCE_PD_M  (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S)
+#define LP_UART_MEM_FORCE_PD_V  0x00000001U
+#define LP_UART_MEM_FORCE_PD_S  25
+/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define LP_UART_MEM_FORCE_PU    (BIT(26))
+#define LP_UART_MEM_FORCE_PU_M  (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S)
+#define LP_UART_MEM_FORCE_PU_V  0x00000001U
+#define LP_UART_MEM_FORCE_PU_S  26
+
+/** LP_UART_TOUT_CONF_SYNC_REG register
+ *  UART threshold and allocation configuration
+ */
+#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
+/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define LP_UART_RX_TOUT_EN    (BIT(0))
+#define LP_UART_RX_TOUT_EN_M  (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)
+#define LP_UART_RX_TOUT_EN_V  0x00000001U
+#define LP_UART_RX_TOUT_EN_S  0
+/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define LP_UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define LP_UART_RX_TOUT_FLOW_DIS_M  (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S)
+#define LP_UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define LP_UART_RX_TOUT_FLOW_DIS_S  1
+/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define LP_UART_RX_TOUT_THRHD    0x000003FFU
+#define LP_UART_RX_TOUT_THRHD_M  (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S)
+#define LP_UART_RX_TOUT_THRHD_V  0x000003FFU
+#define LP_UART_RX_TOUT_THRHD_S  2
+
+/** LP_UART_MEM_TX_STATUS_REG register
+ *  Tx-SRAM write and read offset address.
+ */
+#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68)
+/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define LP_UART_TX_SRAM_WADDR    0x0000001FU
+#define LP_UART_TX_SRAM_WADDR_M  (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S)
+#define LP_UART_TX_SRAM_WADDR_V  0x0000001FU
+#define LP_UART_TX_SRAM_WADDR_S  3
+/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define LP_UART_TX_SRAM_RADDR    0x0000001FU
+#define LP_UART_TX_SRAM_RADDR_M  (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S)
+#define LP_UART_TX_SRAM_RADDR_V  0x0000001FU
+#define LP_UART_TX_SRAM_RADDR_S  12
+
+/** LP_UART_MEM_RX_STATUS_REG register
+ *  Rx-SRAM write and read offset address.
+ */
+#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c)
+/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define LP_UART_RX_SRAM_RADDR    0x0000001FU
+#define LP_UART_RX_SRAM_RADDR_M  (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S)
+#define LP_UART_RX_SRAM_RADDR_V  0x0000001FU
+#define LP_UART_RX_SRAM_RADDR_S  3
+/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define LP_UART_RX_SRAM_WADDR    0x0000001FU
+#define LP_UART_RX_SRAM_WADDR_M  (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S)
+#define LP_UART_RX_SRAM_WADDR_V  0x0000001FU
+#define LP_UART_RX_SRAM_WADDR_S  12
+
+/** LP_UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70)
+/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define LP_UART_ST_URX_OUT    0x0000000FU
+#define LP_UART_ST_URX_OUT_M  (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S)
+#define LP_UART_ST_URX_OUT_V  0x0000000FU
+#define LP_UART_ST_URX_OUT_S  0
+/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define LP_UART_ST_UTX_OUT    0x0000000FU
+#define LP_UART_ST_UTX_OUT_M  (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S)
+#define LP_UART_ST_UTX_OUT_V  0x0000000FU
+#define LP_UART_ST_UTX_OUT_S  4
+
+/** LP_UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
+/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor.
+ */
+#define LP_UART_SCLK_DIV_B    0x0000003FU
+#define LP_UART_SCLK_DIV_B_M  (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S)
+#define LP_UART_SCLK_DIV_B_V  0x0000003FU
+#define LP_UART_SCLK_DIV_B_S  0
+/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor.
+ */
+#define LP_UART_SCLK_DIV_A    0x0000003FU
+#define LP_UART_SCLK_DIV_A_M  (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S)
+#define LP_UART_SCLK_DIV_A_V  0x0000003FU
+#define LP_UART_SCLK_DIV_A_S  6
+/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
+ *  The integral part of the frequency divider factor.
+ */
+#define LP_UART_SCLK_DIV_NUM    0x000000FFU
+#define LP_UART_SCLK_DIV_NUM_M  (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S)
+#define LP_UART_SCLK_DIV_NUM_V  0x000000FFU
+#define LP_UART_SCLK_DIV_NUM_S  12
+/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
+ */
+#define LP_UART_SCLK_SEL    0x00000003U
+#define LP_UART_SCLK_SEL_M  (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S)
+#define LP_UART_SCLK_SEL_V  0x00000003U
+#define LP_UART_SCLK_SEL_S  20
+/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set this bit to enable UART Tx/Rx clock.
+ */
+#define LP_UART_SCLK_EN    (BIT(22))
+#define LP_UART_SCLK_EN_M  (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S)
+#define LP_UART_SCLK_EN_V  0x00000001U
+#define LP_UART_SCLK_EN_S  22
+/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
+ */
+#define LP_UART_RST_CORE    (BIT(23))
+#define LP_UART_RST_CORE_M  (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S)
+#define LP_UART_RST_CORE_V  0x00000001U
+#define LP_UART_RST_CORE_S  23
+/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define LP_UART_TX_SCLK_EN    (BIT(24))
+#define LP_UART_TX_SCLK_EN_M  (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S)
+#define LP_UART_TX_SCLK_EN_V  0x00000001U
+#define LP_UART_TX_SCLK_EN_S  24
+/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define LP_UART_RX_SCLK_EN    (BIT(25))
+#define LP_UART_RX_SCLK_EN_M  (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S)
+#define LP_UART_RX_SCLK_EN_V  0x00000001U
+#define LP_UART_RX_SCLK_EN_S  25
+/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx.
+ */
+#define LP_UART_TX_RST_CORE    (BIT(26))
+#define LP_UART_TX_RST_CORE_M  (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S)
+#define LP_UART_TX_RST_CORE_V  0x00000001U
+#define LP_UART_TX_RST_CORE_S  26
+/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Rx.
+ */
+#define LP_UART_RX_RST_CORE    (BIT(27))
+#define LP_UART_RX_RST_CORE_M  (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S)
+#define LP_UART_RX_RST_CORE_V  0x00000001U
+#define LP_UART_RX_RST_CORE_S  27
+
+/** LP_UART_DATE_REG register
+ *  UART Version register
+ */
+#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c)
+/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 35656288;
+ *  This is the version register.
+ */
+#define LP_UART_DATE    0xFFFFFFFFU
+#define LP_UART_DATE_M  (LP_UART_DATE_V << LP_UART_DATE_S)
+#define LP_UART_DATE_V  0xFFFFFFFFU
+#define LP_UART_DATE_S  0
+
+/** LP_UART_AFIFO_STATUS_REG register
+ *  UART AFIFO Status
+ */
+#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90)
+/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define LP_UART_TX_AFIFO_FULL    (BIT(0))
+#define LP_UART_TX_AFIFO_FULL_M  (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S)
+#define LP_UART_TX_AFIFO_FULL_V  0x00000001U
+#define LP_UART_TX_AFIFO_FULL_S  0
+/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define LP_UART_TX_AFIFO_EMPTY    (BIT(1))
+#define LP_UART_TX_AFIFO_EMPTY_M  (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S)
+#define LP_UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define LP_UART_TX_AFIFO_EMPTY_S  1
+/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define LP_UART_RX_AFIFO_FULL    (BIT(2))
+#define LP_UART_RX_AFIFO_FULL_M  (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S)
+#define LP_UART_RX_AFIFO_FULL_V  0x00000001U
+#define LP_UART_RX_AFIFO_FULL_S  2
+/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define LP_UART_RX_AFIFO_EMPTY    (BIT(3))
+#define LP_UART_RX_AFIFO_EMPTY_M  (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S)
+#define LP_UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define LP_UART_RX_AFIFO_EMPTY_S  3
+
+/** LP_UART_REG_UPDATE_REG register
+ *  UART Registers Configuration Update register
+ */
+#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98)
+/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define LP_UART_REG_UPDATE    (BIT(0))
+#define LP_UART_REG_UPDATE_M  (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S)
+#define LP_UART_REG_UPDATE_V  0x00000001U
+#define LP_UART_REG_UPDATE_S  0
+
+/** LP_UART_ID_REG register
+ *  UART ID register
+ */
+#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c)
+/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define LP_UART_ID    0xFFFFFFFFU
+#define LP_UART_ID_M  (LP_UART_ID_V << LP_UART_ID_S)
+#define LP_UART_ID_V  0xFFFFFFFFU
+#define LP_UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/lp_uart_struct.h b/components/soc/esp32c6/register/soc/lp_uart_struct.h
new file mode 100644
index 00000000000..bc9993276f3
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/lp_uart_struct.h
@@ -0,0 +1,1127 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:32;
+    };
+    uint32_t val;
+} lp_uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} lp_uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err:1;
+        /** frm_err : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err:1;
+        /** frm_err : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err:1;
+        /** frm_err : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err:1;
+        /** frm_err : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv_int:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lp_uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} lp_uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  Configuration register 0
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        uint32_t reserved_7:5;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        uint32_t reserved_14:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        uint32_t reserved_19:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 1;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lp_uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:5;
+        uint32_t reserved_8:3;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:5;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} lp_uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:5;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} lp_uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        uint32_t reserved_10:3;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:5;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_char : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_char:8;
+        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_char:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** xon_threshold : R/W; bitpos: [7:3]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:5;
+        uint32_t reserved_8:3;
+        /** xoff_threshold : R/W; bitpos: [15:11]; default: 12;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:5;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t sclk_div_num:8;
+        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
+         */
+        uint32_t sclk_sel:2;
+        /** sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set this bit to enable UART Tx/Rx clock.
+         */
+        uint32_t sclk_en:1;
+        /** rst_core : R/W; bitpos: [23]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
+         */
+        uint32_t rst_core:1;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:5;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        uint32_t reserved_16:3;
+        /** txfifo_cnt : RO; bitpos: [23:19]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:5;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} lp_uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:5;
+        uint32_t reserved_8:4;
+        /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:5;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:5;
+        uint32_t reserved_8:4;
+        /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:5;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** data : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t data:8;
+        /** char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35656288;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} lp_uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} lp_uart_id_reg_t;
+
+
+typedef struct lp_uart_dev_t {
+    volatile lp_uart_fifo_reg_t fifo;
+    volatile lp_uart_int_raw_reg_t int_raw;
+    volatile lp_uart_int_st_reg_t int_st;
+    volatile lp_uart_int_ena_reg_t int_ena;
+    volatile lp_uart_int_clr_reg_t int_clr;
+    volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile lp_uart_rx_filt_reg_t rx_filt;
+    volatile lp_uart_status_reg_t status;
+    volatile lp_uart_conf0_sync_reg_t conf0_sync;
+    volatile lp_uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile lp_uart_sleep_conf0_reg_t sleep_conf0;
+    volatile lp_uart_sleep_conf1_reg_t sleep_conf1;
+    volatile lp_uart_sleep_conf2_reg_t sleep_conf2;
+    volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile lp_uart_swfc_conf1_reg_t swfc_conf1;
+    volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile lp_uart_mem_conf_reg_t mem_conf;
+    volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile lp_uart_mem_tx_status_reg_t mem_tx_status;
+    volatile lp_uart_mem_rx_status_reg_t mem_rx_status;
+    volatile lp_uart_fsm_status_reg_t fsm_status;
+    uint32_t reserved_074[5];
+    volatile lp_uart_clk_conf_reg_t clk_conf;
+    volatile lp_uart_date_reg_t date;
+    volatile lp_uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile lp_uart_reg_update_reg_t reg_update;
+    volatile lp_uart_id_reg_t id;
+} lp_uart_dev_t;
+
+// We map the LP_UART instance to the uart_dev_t struct for convenience of using the same HAL/LL. See soc/uart_struct.h
+// extern lp_uart_dev_t LP_UART;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/lp_wdt_reg.h b/components/soc/esp32c6/register/soc/lp_wdt_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_wdt_reg.h
rename to components/soc/esp32c6/register/soc/lp_wdt_reg.h
diff --git a/components/soc/esp32c6/include/soc/lp_wdt_struct.h b/components/soc/esp32c6/register/soc/lp_wdt_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lp_wdt_struct.h
rename to components/soc/esp32c6/register/soc/lp_wdt_struct.h
diff --git a/components/soc/esp32c6/include/soc/lpperi_reg.h b/components/soc/esp32c6/register/soc/lpperi_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lpperi_reg.h
rename to components/soc/esp32c6/register/soc/lpperi_reg.h
diff --git a/components/soc/esp32c6/include/soc/lpperi_struct.h b/components/soc/esp32c6/register/soc/lpperi_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/lpperi_struct.h
rename to components/soc/esp32c6/register/soc/lpperi_struct.h
diff --git a/components/soc/esp32c6/register/soc/mcpwm_reg.h b/components/soc/esp32c6/register/soc/mcpwm_reg.h
new file mode 100644
index 00000000000..4de6f5b9f7f
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/mcpwm_reg.h
@@ -0,0 +1,4137 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MCPWM_CLK_CFG_REG register
+ *  PWM clock prescaler register.
+ */
+#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0)
+/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
+ */
+#define MCPWM_CLK_PRESCALE    0x000000FFU
+#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
+#define MCPWM_CLK_PRESCALE_V  0x000000FFU
+#define MCPWM_CLK_PRESCALE_S  0
+
+/** MCPWM_TIMER0_CFG0_REG register
+ *  PWM timer0 period and update method configuration register.
+ */
+#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer0
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER0_CFG1_REG register
+ *  PWM timer0 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8)
+/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1:
+ *  if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0
+ *  starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER0_START    0x00000007U
+#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
+#define MCPWM_TIMER0_START_V  0x00000007U
+#define MCPWM_TIMER0_START_S  0
+/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER0_MOD    0x00000003U
+#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
+#define MCPWM_TIMER0_MOD_V  0x00000003U
+#define MCPWM_TIMER0_MOD_S  3
+
+/** MCPWM_TIMER0_SYNC_REG register
+ *  PWM timer0 sync function configuration register.
+ */
+#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xc)
+/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
+#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
+#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer0_sync_sw bit
+ */
+#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER0_PHASE    0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
+#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_S  4
+/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer0's direction when timer0 mode is up-down mode:
+ *  0-increase,1-decrease
+ */
+#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
+#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER0_STATUS_REG register
+ *  PWM timer0 status register.
+ */
+#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10)
+/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer0 counter value
+ */
+#define MCPWM_TIMER0_VALUE    0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
+#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_S  0
+/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer0 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER0_DIRECTION    (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
+#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_DIRECTION_S  16
+
+/** MCPWM_TIMER1_CFG0_REG register
+ *  PWM timer1 period and update method configuration register.
+ */
+#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14)
+/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1)
+ */
+#define MCPWM_TIMER1_PRESCALE    0x000000FFU
+#define MCPWM_TIMER1_PRESCALE_M  (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S)
+#define MCPWM_TIMER1_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER1_PRESCALE_S  0
+/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer1
+ */
+#define MCPWM_TIMER1_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER1_PERIOD_M  (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S)
+#define MCPWM_TIMER1_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER1_PERIOD_S  8
+/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER1_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER1_CFG1_REG register
+ *  PWM timer1 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18)
+/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1:
+ *  if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1
+ *  starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER1_START    0x00000007U
+#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
+#define MCPWM_TIMER1_START_V  0x00000007U
+#define MCPWM_TIMER1_START_S  0
+/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER1_MOD    0x00000003U
+#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
+#define MCPWM_TIMER1_MOD_V  0x00000003U
+#define MCPWM_TIMER1_MOD_S  3
+
+/** MCPWM_TIMER1_SYNC_REG register
+ *  PWM timer1 sync function configuration register.
+ */
+#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1c)
+/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
+#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
+#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer1_sync_sw bit
+ */
+#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER1_PHASE    0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
+#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_S  4
+/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer1's direction when timer1 mode is up-down mode:
+ *  0-increase,1-decrease
+ */
+#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
+#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER1_STATUS_REG register
+ *  PWM timer1 status register.
+ */
+#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20)
+/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer1 counter value
+ */
+#define MCPWM_TIMER1_VALUE    0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
+#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_S  0
+/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer1 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER1_DIRECTION    (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
+#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_DIRECTION_S  16
+
+/** MCPWM_TIMER2_CFG0_REG register
+ *  PWM timer2 period and update method configuration register.
+ */
+#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24)
+/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1)
+ */
+#define MCPWM_TIMER2_PRESCALE    0x000000FFU
+#define MCPWM_TIMER2_PRESCALE_M  (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S)
+#define MCPWM_TIMER2_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER2_PRESCALE_S  0
+/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer2
+ */
+#define MCPWM_TIMER2_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER2_PERIOD_M  (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S)
+#define MCPWM_TIMER2_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER2_PERIOD_S  8
+/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER2_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER2_CFG1_REG register
+ *  PWM timer2 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28)
+/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1:
+ *  if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2
+ *  starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER2_START    0x00000007U
+#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
+#define MCPWM_TIMER2_START_V  0x00000007U
+#define MCPWM_TIMER2_START_S  0
+/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER2_MOD    0x00000003U
+#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
+#define MCPWM_TIMER2_MOD_V  0x00000003U
+#define MCPWM_TIMER2_MOD_S  3
+
+/** MCPWM_TIMER2_SYNC_REG register
+ *  PWM timer2 sync function configuration register.
+ */
+#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2c)
+/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
+#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
+#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer0_sync_sw bit
+ */
+#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER2_PHASE    0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
+#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_S  4
+/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer2's direction when timer2 mode is up-down mode:
+ *  0-increase,1-decrease
+ */
+#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
+#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER2_STATUS_REG register
+ *  PWM timer2 status register.
+ */
+#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30)
+/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer2 counter value
+ */
+#define MCPWM_TIMER2_VALUE    0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
+#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_S  0
+/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer2 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER2_DIRECTION    (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
+#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_DIRECTION_S  16
+
+/** MCPWM_TIMER_SYNCI_CFG_REG register
+ *  Synchronization input selection for three PWM timers.
+ */
+#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34)
+/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
+ *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER0_SYNCISEL    0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
+#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_S  0
+/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
+ *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER1_SYNCISEL    0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
+#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
+ *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER2_SYNCISEL    0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
+#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
+ *  invert SYNC0 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
+ *  invert SYNC1 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
+ *  invert SYNC2 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+
+/** MCPWM_OPERATOR_TIMERSEL_REG register
+ *  Select specific timer for PWM operators.
+ */
+#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38)
+/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
+ *  Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
+ *  Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
+ *  Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+
+/** MCPWM_GEN0_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3c)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 0 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 0 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN0_TSTMP_A_REG register
+ *  Shadow register for register A.
+ */
+#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x40)
+/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 0 time stamp A's shadow register
+ */
+#define MCPWM_CMPR0_A    0x0000FFFFU
+#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
+#define MCPWM_CMPR0_A_V  0x0000FFFFU
+#define MCPWM_CMPR0_A_S  0
+
+/** MCPWM_GEN0_TSTMP_B_REG register
+ *  Shadow register for register B.
+ */
+#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x44)
+/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 0 time stamp B's shadow register
+ */
+#define MCPWM_CMPR0_B    0x0000FFFFU
+#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
+#define MCPWM_CMPR0_B_V  0x0000FFFFU
+#define MCPWM_CMPR0_B_S  0
+
+/** MCPWM_GEN0_CFG0_REG register
+ *  Fault event T0 and T1 handling
+ */
+#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48)
+/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 0's active register of configuration. When all bits
+ *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+ *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
+ */
+#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 0 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN0_T0_SEL    0x00000007U
+#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
+#define MCPWM_GEN0_T0_SEL_V  0x00000007U
+#define MCPWM_GEN0_T0_SEL_S  4
+/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 0 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN0_T1_SEL    0x00000007U
+#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
+#define MCPWM_GEN0_T1_SEL_V  0x00000007U
+#define MCPWM_GEN0_T1_SEL_S  7
+
+/** MCPWM_GEN0_FORCE_REG register
+ *  Permissives to force PWM0A and PWM0B outputs by software
+ */
+#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4c)
+/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator0. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM0A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
+#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM0B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
+#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN0_A_REG register
+ *  Actions triggered by events on PWM0A
+ */
+#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50)
+/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM0A triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN0_A_UTEZ    0x00000003U
+#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
+#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_UTEZ_S  0
+/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM0A triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN0_A_UTEP    0x00000003U
+#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
+#define MCPWM_GEN0_A_UTEP_V  0x00000003U
+#define MCPWM_GEN0_A_UTEP_S  2
+/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM0A triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN0_A_UTEA    0x00000003U
+#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
+#define MCPWM_GEN0_A_UTEA_V  0x00000003U
+#define MCPWM_GEN0_A_UTEA_S  4
+/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM0A triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN0_A_UTEB    0x00000003U
+#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
+#define MCPWM_GEN0_A_UTEB_V  0x00000003U
+#define MCPWM_GEN0_A_UTEB_S  6
+/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM0A triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN0_A_UT0    0x00000003U
+#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
+#define MCPWM_GEN0_A_UT0_V  0x00000003U
+#define MCPWM_GEN0_A_UT0_S  8
+/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM0A triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN0_A_UT1    0x00000003U
+#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
+#define MCPWM_GEN0_A_UT1_V  0x00000003U
+#define MCPWM_GEN0_A_UT1_S  10
+/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM0A triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN0_A_DTEZ    0x00000003U
+#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
+#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_DTEZ_S  12
+/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM0A triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN0_A_DTEP    0x00000003U
+#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
+#define MCPWM_GEN0_A_DTEP_V  0x00000003U
+#define MCPWM_GEN0_A_DTEP_S  14
+/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM0A triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN0_A_DTEA    0x00000003U
+#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
+#define MCPWM_GEN0_A_DTEA_V  0x00000003U
+#define MCPWM_GEN0_A_DTEA_S  16
+/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM0A triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN0_A_DTEB    0x00000003U
+#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
+#define MCPWM_GEN0_A_DTEB_V  0x00000003U
+#define MCPWM_GEN0_A_DTEB_S  18
+/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM0A triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN0_A_DT0    0x00000003U
+#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
+#define MCPWM_GEN0_A_DT0_V  0x00000003U
+#define MCPWM_GEN0_A_DT0_S  20
+/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_DT1    0x00000003U
+#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
+#define MCPWM_GEN0_A_DT1_V  0x00000003U
+#define MCPWM_GEN0_A_DT1_S  22
+
+/** MCPWM_GEN0_B_REG register
+ *  Actions triggered by events on PWM0B
+ */
+#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54)
+/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM0B triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN0_B_UTEZ    0x00000003U
+#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
+#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_UTEZ_S  0
+/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM0B triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN0_B_UTEP    0x00000003U
+#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
+#define MCPWM_GEN0_B_UTEP_V  0x00000003U
+#define MCPWM_GEN0_B_UTEP_S  2
+/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM0B triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN0_B_UTEA    0x00000003U
+#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
+#define MCPWM_GEN0_B_UTEA_V  0x00000003U
+#define MCPWM_GEN0_B_UTEA_S  4
+/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM0B triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN0_B_UTEB    0x00000003U
+#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
+#define MCPWM_GEN0_B_UTEB_V  0x00000003U
+#define MCPWM_GEN0_B_UTEB_S  6
+/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM0B triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN0_B_UT0    0x00000003U
+#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
+#define MCPWM_GEN0_B_UT0_V  0x00000003U
+#define MCPWM_GEN0_B_UT0_S  8
+/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM0B triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN0_B_UT1    0x00000003U
+#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
+#define MCPWM_GEN0_B_UT1_V  0x00000003U
+#define MCPWM_GEN0_B_UT1_S  10
+/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM0B triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN0_B_DTEZ    0x00000003U
+#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
+#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_DTEZ_S  12
+/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM0B triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN0_B_DTEP    0x00000003U
+#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
+#define MCPWM_GEN0_B_DTEP_V  0x00000003U
+#define MCPWM_GEN0_B_DTEP_S  14
+/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM0B triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN0_B_DTEA    0x00000003U
+#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
+#define MCPWM_GEN0_B_DTEA_V  0x00000003U
+#define MCPWM_GEN0_B_DTEA_S  16
+/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM0B triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN0_B_DTEB    0x00000003U
+#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
+#define MCPWM_GEN0_B_DTEB_V  0x00000003U
+#define MCPWM_GEN0_B_DTEB_S  18
+/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM0B triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN0_B_DT0    0x00000003U
+#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
+#define MCPWM_GEN0_B_DT0_V  0x00000003U
+#define MCPWM_GEN0_B_DT0_S  20
+/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_DT1    0x00000003U
+#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
+#define MCPWM_GEN0_B_DT1_V  0x00000003U
+#define MCPWM_GEN0_B_DT1_S  22
+
+/** MCPWM_DT0_CFG_REG register
+ *  dead time type selection and configuration
+ */
+#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58)
+/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
+#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_S  0
+/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
+#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_S  4
+/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB0_DEB_MODE    (BIT(8))
+#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
+#define MCPWM_DB0_DEB_MODE_V  0x00000001U
+#define MCPWM_DB0_DEB_MODE_S  8
+/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
+#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_A_OUTSWAP_S  9
+/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
+#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_B_OUTSWAP_S  10
+/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DB0_RED_INSEL    (BIT(11))
+#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
+#define MCPWM_DB0_RED_INSEL_V  0x00000001U
+#define MCPWM_DB0_RED_INSEL_S  11
+/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DB0_FED_INSEL    (BIT(12))
+#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
+#define MCPWM_DB0_FED_INSEL_V  0x00000001U
+#define MCPWM_DB0_FED_INSEL_S  12
+/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
+#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_RED_OUTINVERT_S  13
+/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
+#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_FED_OUTINVERT_S  14
+/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
+#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_A_OUTBYPASS_S  15
+/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
+#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_B_OUTBYPASS_S  16
+/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DB0_CLK_SEL    (BIT(17))
+#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
+#define MCPWM_DB0_CLK_SEL_V  0x00000001U
+#define MCPWM_DB0_CLK_SEL_S  17
+
+/** MCPWM_DT0_FED_CFG_REG register
+ *  Shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c)
+/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DB0_FED    0x0000FFFFU
+#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
+#define MCPWM_DB0_FED_V  0x0000FFFFU
+#define MCPWM_DB0_FED_S  0
+
+/** MCPWM_DT0_RED_CFG_REG register
+ *  Shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60)
+/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DB0_RED    0x0000FFFFU
+#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
+#define MCPWM_DB0_RED_V  0x0000FFFFU
+#define MCPWM_DB0_RED_S  0
+
+/** MCPWM_CARRIER0_CFG_REG register
+ *  Carrier enable and configuration
+ */
+#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64)
+/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
+ */
+#define MCPWM_CHOPPER0_EN    (BIT(0))
+#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
+#define MCPWM_CHOPPER0_EN_V  0x00000001U
+#define MCPWM_CHOPPER0_EN_S  0
+/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
+#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_S  1
+/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CHOPPER0_DUTY    0x00000007U
+#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
+#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER0_DUTY_S  5
+/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
+#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_S  8
+/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM0A and PWM0B for this submodule
+ */
+#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
+#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_OUT_INVERT_S  12
+/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM0A and PWM0B for this submodule
+ */
+#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
+#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_IN_INVERT_S  13
+
+/** MCPWM_FH0_CFG0_REG register
+ *  Actions on PWM0A and PWM0B trip events
+ */
+#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68)
+/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_SW_CBC    (BIT(0))
+#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
+#define MCPWM_TZ0_SW_CBC_V  0x00000001U
+#define MCPWM_TZ0_SW_CBC_S  0
+/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F2_CBC    (BIT(1))
+#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
+#define MCPWM_TZ0_F2_CBC_V  0x00000001U
+#define MCPWM_TZ0_F2_CBC_S  1
+/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F1_CBC    (BIT(2))
+#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
+#define MCPWM_TZ0_F1_CBC_V  0x00000001U
+#define MCPWM_TZ0_F1_CBC_S  2
+/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F0_CBC    (BIT(3))
+#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
+#define MCPWM_TZ0_F0_CBC_V  0x00000001U
+#define MCPWM_TZ0_F0_CBC_S  3
+/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_SW_OST    (BIT(4))
+#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
+#define MCPWM_TZ0_SW_OST_V  0x00000001U
+#define MCPWM_TZ0_SW_OST_S  4
+/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F2_OST    (BIT(5))
+#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
+#define MCPWM_TZ0_F2_OST_V  0x00000001U
+#define MCPWM_TZ0_F2_OST_S  5
+/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F1_OST    (BIT(6))
+#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
+#define MCPWM_TZ0_F1_OST_V  0x00000001U
+#define MCPWM_TZ0_F1_OST_S  6
+/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F0_OST    (BIT(7))
+#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
+#define MCPWM_TZ0_F0_OST_V  0x00000001U
+#define MCPWM_TZ0_F0_OST_S  7
+/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_A_CBC_D    0x00000003U
+#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
+#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_D_S  8
+/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_A_CBC_U    0x00000003U
+#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
+#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_U_S  10
+/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_A_OST_D    0x00000003U
+#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
+#define MCPWM_TZ0_A_OST_D_V  0x00000003U
+#define MCPWM_TZ0_A_OST_D_S  12
+/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_A_OST_U    0x00000003U
+#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
+#define MCPWM_TZ0_A_OST_U_V  0x00000003U
+#define MCPWM_TZ0_A_OST_U_S  14
+/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_B_CBC_D    0x00000003U
+#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
+#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_D_S  16
+/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+ *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_B_CBC_U    0x00000003U
+#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
+#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_U_S  18
+/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_B_OST_D    0x00000003U
+#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
+#define MCPWM_TZ0_B_OST_D_V  0x00000003U
+#define MCPWM_TZ0_B_OST_D_S  20
+/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_B_OST_U    0x00000003U
+#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
+#define MCPWM_TZ0_B_OST_U_V  0x00000003U
+#define MCPWM_TZ0_B_OST_U_S  22
+
+/** MCPWM_FH0_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6c)
+/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_TZ0_CLR_OST    (BIT(0))
+#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
+#define MCPWM_TZ0_CLR_OST_V  0x00000001U
+#define MCPWM_TZ0_CLR_OST_S  0
+/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP
+ */
+#define MCPWM_TZ0_CBCPULSE    0x00000003U
+#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
+#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ0_CBCPULSE_S  1
+/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
+#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ0_FORCE_CBC_S  3
+/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_TZ0_FORCE_OST    (BIT(4))
+#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
+#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ0_FORCE_OST_S  4
+
+/** MCPWM_FH0_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70)
+/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_TZ0_CBC_ON    (BIT(0))
+#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
+#define MCPWM_TZ0_CBC_ON_V  0x00000001U
+#define MCPWM_TZ0_CBC_ON_S  0
+/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_TZ0_OST_ON    (BIT(1))
+#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
+#define MCPWM_TZ0_OST_ON_V  0x00000001U
+#define MCPWM_TZ0_OST_ON_S  1
+
+/** MCPWM_GEN1_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74)
+/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 1 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR1_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR1_A_UPMETHOD_M  (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S)
+#define MCPWM_CMPR1_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR1_A_UPMETHOD_S  0
+/** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 1 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR1_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR1_B_UPMETHOD_M  (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S)
+#define MCPWM_CMPR1_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR1_B_UPMETHOD_S  4
+/** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR1_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR1_A_SHDW_FULL_M  (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S)
+#define MCPWM_CMPR1_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR1_A_SHDW_FULL_S  8
+/** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR1_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR1_B_SHDW_FULL_M  (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S)
+#define MCPWM_CMPR1_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR1_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN1_TSTMP_A_REG register
+ *  Shadow register for register A.
+ */
+#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x78)
+/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 1 time stamp A's shadow register
+ */
+#define MCPWM_CMPR1_A    0x0000FFFFU
+#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
+#define MCPWM_CMPR1_A_V  0x0000FFFFU
+#define MCPWM_CMPR1_A_S  0
+
+/** MCPWM_GEN1_TSTMP_B_REG register
+ *  Shadow register for register B.
+ */
+#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x7c)
+/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 1 time stamp B's shadow register
+ */
+#define MCPWM_CMPR1_B    0x0000FFFFU
+#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
+#define MCPWM_CMPR1_B_V  0x0000FFFFU
+#define MCPWM_CMPR1_B_S  0
+
+/** MCPWM_GEN1_CFG0_REG register
+ *  Fault event T0 and T1 handling
+ */
+#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80)
+/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 1's active register of configuration. When all bits
+ *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+ *  1:sync;when bit3 is set to 1:disable the update.
+ */
+#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 1 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN1_T0_SEL    0x00000007U
+#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
+#define MCPWM_GEN1_T0_SEL_V  0x00000007U
+#define MCPWM_GEN1_T0_SEL_S  4
+/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 1 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN1_T1_SEL    0x00000007U
+#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
+#define MCPWM_GEN1_T1_SEL_V  0x00000007U
+#define MCPWM_GEN1_T1_SEL_S  7
+
+/** MCPWM_GEN1_FORCE_REG register
+ *  Permissives to force PWM1A and PWM1B outputs by software
+ */
+#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84)
+/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator 1. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM1A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
+#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM1B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
+#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN1_A_REG register
+ *  Actions triggered by events on PWM1A
+ */
+#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88)
+/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM1A triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN1_A_UTEZ    0x00000003U
+#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
+#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_UTEZ_S  0
+/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM1A triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN1_A_UTEP    0x00000003U
+#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
+#define MCPWM_GEN1_A_UTEP_V  0x00000003U
+#define MCPWM_GEN1_A_UTEP_S  2
+/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM1A triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN1_A_UTEA    0x00000003U
+#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
+#define MCPWM_GEN1_A_UTEA_V  0x00000003U
+#define MCPWM_GEN1_A_UTEA_S  4
+/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM1A triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN1_A_UTEB    0x00000003U
+#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
+#define MCPWM_GEN1_A_UTEB_V  0x00000003U
+#define MCPWM_GEN1_A_UTEB_S  6
+/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM1A triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN1_A_UT0    0x00000003U
+#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
+#define MCPWM_GEN1_A_UT0_V  0x00000003U
+#define MCPWM_GEN1_A_UT0_S  8
+/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM1A triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN1_A_UT1    0x00000003U
+#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
+#define MCPWM_GEN1_A_UT1_V  0x00000003U
+#define MCPWM_GEN1_A_UT1_S  10
+/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM1A triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN1_A_DTEZ    0x00000003U
+#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
+#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_DTEZ_S  12
+/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM1A triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN1_A_DTEP    0x00000003U
+#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
+#define MCPWM_GEN1_A_DTEP_V  0x00000003U
+#define MCPWM_GEN1_A_DTEP_S  14
+/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM1A triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN1_A_DTEA    0x00000003U
+#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
+#define MCPWM_GEN1_A_DTEA_V  0x00000003U
+#define MCPWM_GEN1_A_DTEA_S  16
+/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM1A triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN1_A_DTEB    0x00000003U
+#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
+#define MCPWM_GEN1_A_DTEB_V  0x00000003U
+#define MCPWM_GEN1_A_DTEB_S  18
+/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM1A triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN1_A_DT0    0x00000003U
+#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
+#define MCPWM_GEN1_A_DT0_V  0x00000003U
+#define MCPWM_GEN1_A_DT0_S  20
+/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_DT1    0x00000003U
+#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
+#define MCPWM_GEN1_A_DT1_V  0x00000003U
+#define MCPWM_GEN1_A_DT1_S  22
+
+/** MCPWM_GEN1_B_REG register
+ *  Actions triggered by events on PWM1B
+ */
+#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8c)
+/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM1B triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN1_B_UTEZ    0x00000003U
+#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
+#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_UTEZ_S  0
+/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM1B triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN1_B_UTEP    0x00000003U
+#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
+#define MCPWM_GEN1_B_UTEP_V  0x00000003U
+#define MCPWM_GEN1_B_UTEP_S  2
+/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM1B triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN1_B_UTEA    0x00000003U
+#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
+#define MCPWM_GEN1_B_UTEA_V  0x00000003U
+#define MCPWM_GEN1_B_UTEA_S  4
+/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM1B triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN1_B_UTEB    0x00000003U
+#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
+#define MCPWM_GEN1_B_UTEB_V  0x00000003U
+#define MCPWM_GEN1_B_UTEB_S  6
+/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM1B triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN1_B_UT0    0x00000003U
+#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
+#define MCPWM_GEN1_B_UT0_V  0x00000003U
+#define MCPWM_GEN1_B_UT0_S  8
+/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM1B triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN1_B_UT1    0x00000003U
+#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
+#define MCPWM_GEN1_B_UT1_V  0x00000003U
+#define MCPWM_GEN1_B_UT1_S  10
+/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM1B triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN1_B_DTEZ    0x00000003U
+#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
+#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_DTEZ_S  12
+/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM1B triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN1_B_DTEP    0x00000003U
+#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
+#define MCPWM_GEN1_B_DTEP_V  0x00000003U
+#define MCPWM_GEN1_B_DTEP_S  14
+/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM1B triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN1_B_DTEA    0x00000003U
+#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
+#define MCPWM_GEN1_B_DTEA_V  0x00000003U
+#define MCPWM_GEN1_B_DTEA_S  16
+/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM1B triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN1_B_DTEB    0x00000003U
+#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
+#define MCPWM_GEN1_B_DTEB_V  0x00000003U
+#define MCPWM_GEN1_B_DTEB_S  18
+/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM1B triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN1_B_DT0    0x00000003U
+#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
+#define MCPWM_GEN1_B_DT0_V  0x00000003U
+#define MCPWM_GEN1_B_DT0_S  20
+/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_DT1    0x00000003U
+#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
+#define MCPWM_GEN1_B_DT1_V  0x00000003U
+#define MCPWM_GEN1_B_DT1_S  22
+
+/** MCPWM_DT1_CFG_REG register
+ *  dead time type selection and configuration
+ */
+#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90)
+/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (falling edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
+#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_S  0
+/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register. 0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
+#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_S  4
+/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB1_DEB_MODE    (BIT(8))
+#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
+#define MCPWM_DB1_DEB_MODE_V  0x00000001U
+#define MCPWM_DB1_DEB_MODE_S  8
+/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
+#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_A_OUTSWAP_S  9
+/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
+#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_B_OUTSWAP_S  10
+/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DB1_RED_INSEL    (BIT(11))
+#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
+#define MCPWM_DB1_RED_INSEL_V  0x00000001U
+#define MCPWM_DB1_RED_INSEL_S  11
+/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DB1_FED_INSEL    (BIT(12))
+#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
+#define MCPWM_DB1_FED_INSEL_V  0x00000001U
+#define MCPWM_DB1_FED_INSEL_S  12
+/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
+#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_RED_OUTINVERT_S  13
+/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
+#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_FED_OUTINVERT_S  14
+/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
+#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_A_OUTBYPASS_S  15
+/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
+#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_B_OUTBYPASS_S  16
+/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DB1_CLK_SEL    (BIT(17))
+#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
+#define MCPWM_DB1_CLK_SEL_V  0x00000001U
+#define MCPWM_DB1_CLK_SEL_S  17
+
+/** MCPWM_DT1_FED_CFG_REG register
+ *  Shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94)
+/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DB1_FED    0x0000FFFFU
+#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
+#define MCPWM_DB1_FED_V  0x0000FFFFU
+#define MCPWM_DB1_FED_S  0
+
+/** MCPWM_DT1_RED_CFG_REG register
+ *  Shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98)
+/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DB1_RED    0x0000FFFFU
+#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
+#define MCPWM_DB1_RED_V  0x0000FFFFU
+#define MCPWM_DB1_RED_S  0
+
+/** MCPWM_CARRIER1_CFG_REG register
+ *  Carrier enable and configuration
+ */
+#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c)
+/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier1 function is enabled. When cleared, carrier1 is bypassed
+ */
+#define MCPWM_CHOPPER1_EN    (BIT(0))
+#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
+#define MCPWM_CHOPPER1_EN_V  0x00000001U
+#define MCPWM_CHOPPER1_EN_S  0
+/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
+#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_S  1
+/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CHOPPER1_DUTY    0x00000007U
+#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
+#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER1_DUTY_S  5
+/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
+#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_S  8
+/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM1A and PWM1B for this submodule
+ */
+#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
+#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_OUT_INVERT_S  12
+/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM1A and PWM1B for this submodule
+ */
+#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
+#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_IN_INVERT_S  13
+
+/** MCPWM_FH1_CFG0_REG register
+ *  Actions on PWM1A and PWM1B trip events
+ */
+#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xa0)
+/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_SW_CBC    (BIT(0))
+#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
+#define MCPWM_TZ1_SW_CBC_V  0x00000001U
+#define MCPWM_TZ1_SW_CBC_S  0
+/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F2_CBC    (BIT(1))
+#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
+#define MCPWM_TZ1_F2_CBC_V  0x00000001U
+#define MCPWM_TZ1_F2_CBC_S  1
+/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F1_CBC    (BIT(2))
+#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
+#define MCPWM_TZ1_F1_CBC_V  0x00000001U
+#define MCPWM_TZ1_F1_CBC_S  2
+/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F0_CBC    (BIT(3))
+#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
+#define MCPWM_TZ1_F0_CBC_V  0x00000001U
+#define MCPWM_TZ1_F0_CBC_S  3
+/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_SW_OST    (BIT(4))
+#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
+#define MCPWM_TZ1_SW_OST_V  0x00000001U
+#define MCPWM_TZ1_SW_OST_S  4
+/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F2_OST    (BIT(5))
+#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
+#define MCPWM_TZ1_F2_OST_V  0x00000001U
+#define MCPWM_TZ1_F2_OST_S  5
+/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F1_OST    (BIT(6))
+#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
+#define MCPWM_TZ1_F1_OST_V  0x00000001U
+#define MCPWM_TZ1_F1_OST_S  6
+/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F0_OST    (BIT(7))
+#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
+#define MCPWM_TZ1_F0_OST_V  0x00000001U
+#define MCPWM_TZ1_F0_OST_S  7
+/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_A_CBC_D    0x00000003U
+#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
+#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_D_S  8
+/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_A_CBC_U    0x00000003U
+#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
+#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_U_S  10
+/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0:
+ *  do nothing,1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_A_OST_D    0x00000003U
+#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
+#define MCPWM_TZ1_A_OST_D_V  0x00000003U
+#define MCPWM_TZ1_A_OST_D_S  12
+/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_A_OST_U    0x00000003U
+#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
+#define MCPWM_TZ1_A_OST_U_V  0x00000003U
+#define MCPWM_TZ1_A_OST_U_S  14
+/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_B_CBC_D    0x00000003U
+#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
+#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_D_S  16
+/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_B_CBC_U    0x00000003U
+#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
+#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_U_S  18
+/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_B_OST_D    0x00000003U
+#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
+#define MCPWM_TZ1_B_OST_D_V  0x00000003U
+#define MCPWM_TZ1_B_OST_D_S  20
+/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_B_OST_U    0x00000003U
+#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
+#define MCPWM_TZ1_B_OST_U_V  0x00000003U
+#define MCPWM_TZ1_B_OST_U_S  22
+
+/** MCPWM_FH1_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa4)
+/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_TZ1_CLR_OST    (BIT(0))
+#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
+#define MCPWM_TZ1_CLR_OST_V  0x00000001U
+#define MCPWM_TZ1_CLR_OST_S  0
+/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP
+ */
+#define MCPWM_TZ1_CBCPULSE    0x00000003U
+#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
+#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ1_CBCPULSE_S  1
+/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
+#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ1_FORCE_CBC_S  3
+/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_TZ1_FORCE_OST    (BIT(4))
+#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
+#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ1_FORCE_OST_S  4
+
+/** MCPWM_FH1_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa8)
+/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_TZ1_CBC_ON    (BIT(0))
+#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
+#define MCPWM_TZ1_CBC_ON_V  0x00000001U
+#define MCPWM_TZ1_CBC_ON_S  0
+/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_TZ1_OST_ON    (BIT(1))
+#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
+#define MCPWM_TZ1_OST_ON_V  0x00000001U
+#define MCPWM_TZ1_OST_ON_S  1
+
+/** MCPWM_GEN2_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xac)
+/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 2 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR2_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR2_A_UPMETHOD_M  (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S)
+#define MCPWM_CMPR2_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR2_A_UPMETHOD_S  0
+/** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 2 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR2_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR2_B_UPMETHOD_M  (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S)
+#define MCPWM_CMPR2_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR2_B_UPMETHOD_S  4
+/** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR2_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR2_A_SHDW_FULL_M  (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S)
+#define MCPWM_CMPR2_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR2_A_SHDW_FULL_S  8
+/** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR2_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR2_B_SHDW_FULL_M  (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S)
+#define MCPWM_CMPR2_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR2_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN2_TSTMP_A_REG register
+ *  Shadow register for register A.
+ */
+#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xb0)
+/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 2 time stamp A's shadow register
+ */
+#define MCPWM_CMPR2_A    0x0000FFFFU
+#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
+#define MCPWM_CMPR2_A_V  0x0000FFFFU
+#define MCPWM_CMPR2_A_S  0
+
+/** MCPWM_GEN2_TSTMP_B_REG register
+ *  Shadow register for register B.
+ */
+#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb4)
+/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 2 time stamp B's shadow register
+ */
+#define MCPWM_CMPR2_B    0x0000FFFFU
+#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
+#define MCPWM_CMPR2_B_V  0x0000FFFFU
+#define MCPWM_CMPR2_B_S  0
+
+/** MCPWM_GEN2_CFG0_REG register
+ *  Fault event T0 and T1 handling
+ */
+#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb8)
+/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 2's active register of configuration. 0:
+ *  immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is
+ *  set to 1:disable the update.
+ */
+#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 2 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN2_T0_SEL    0x00000007U
+#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
+#define MCPWM_GEN2_T0_SEL_V  0x00000007U
+#define MCPWM_GEN2_T0_SEL_S  4
+/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 2 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN2_T1_SEL    0x00000007U
+#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
+#define MCPWM_GEN2_T1_SEL_V  0x00000007U
+#define MCPWM_GEN2_T1_SEL_S  7
+
+/** MCPWM_GEN2_FORCE_REG register
+ *  Permissives to force PWM2A and PWM2B outputs by software
+ */
+#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xbc)
+/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator 2. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM2A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
+#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM2B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
+#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN2_A_REG register
+ *  Actions triggered by events on PWM2A
+ */
+#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xc0)
+/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM2A triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN2_A_UTEZ    0x00000003U
+#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
+#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_UTEZ_S  0
+/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM2A triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN2_A_UTEP    0x00000003U
+#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
+#define MCPWM_GEN2_A_UTEP_V  0x00000003U
+#define MCPWM_GEN2_A_UTEP_S  2
+/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM2A triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN2_A_UTEA    0x00000003U
+#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
+#define MCPWM_GEN2_A_UTEA_V  0x00000003U
+#define MCPWM_GEN2_A_UTEA_S  4
+/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM2A triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN2_A_UTEB    0x00000003U
+#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
+#define MCPWM_GEN2_A_UTEB_V  0x00000003U
+#define MCPWM_GEN2_A_UTEB_S  6
+/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM2A triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN2_A_UT0    0x00000003U
+#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
+#define MCPWM_GEN2_A_UT0_V  0x00000003U
+#define MCPWM_GEN2_A_UT0_S  8
+/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM2A triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN2_A_UT1    0x00000003U
+#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
+#define MCPWM_GEN2_A_UT1_V  0x00000003U
+#define MCPWM_GEN2_A_UT1_S  10
+/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM2A triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN2_A_DTEZ    0x00000003U
+#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
+#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_DTEZ_S  12
+/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM2A triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN2_A_DTEP    0x00000003U
+#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
+#define MCPWM_GEN2_A_DTEP_V  0x00000003U
+#define MCPWM_GEN2_A_DTEP_S  14
+/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM2A triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN2_A_DTEA    0x00000003U
+#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
+#define MCPWM_GEN2_A_DTEA_V  0x00000003U
+#define MCPWM_GEN2_A_DTEA_S  16
+/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM2A triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN2_A_DTEB    0x00000003U
+#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
+#define MCPWM_GEN2_A_DTEB_V  0x00000003U
+#define MCPWM_GEN2_A_DTEB_S  18
+/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM2A triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN2_A_DT0    0x00000003U
+#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
+#define MCPWM_GEN2_A_DT0_V  0x00000003U
+#define MCPWM_GEN2_A_DT0_S  20
+/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_DT1    0x00000003U
+#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
+#define MCPWM_GEN2_A_DT1_V  0x00000003U
+#define MCPWM_GEN2_A_DT1_S  22
+
+/** MCPWM_GEN2_B_REG register
+ *  Actions triggered by events on PWM2B
+ */
+#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc4)
+/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM2B triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN2_B_UTEZ    0x00000003U
+#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
+#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_UTEZ_S  0
+/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM2B triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN2_B_UTEP    0x00000003U
+#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
+#define MCPWM_GEN2_B_UTEP_V  0x00000003U
+#define MCPWM_GEN2_B_UTEP_S  2
+/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM2B triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN2_B_UTEA    0x00000003U
+#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
+#define MCPWM_GEN2_B_UTEA_V  0x00000003U
+#define MCPWM_GEN2_B_UTEA_S  4
+/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM2B triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN2_B_UTEB    0x00000003U
+#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
+#define MCPWM_GEN2_B_UTEB_V  0x00000003U
+#define MCPWM_GEN2_B_UTEB_S  6
+/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM2B triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN2_B_UT0    0x00000003U
+#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
+#define MCPWM_GEN2_B_UT0_V  0x00000003U
+#define MCPWM_GEN2_B_UT0_S  8
+/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM2B triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN2_B_UT1    0x00000003U
+#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
+#define MCPWM_GEN2_B_UT1_V  0x00000003U
+#define MCPWM_GEN2_B_UT1_S  10
+/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM2B triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN2_B_DTEZ    0x00000003U
+#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
+#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_DTEZ_S  12
+/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM2B triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN2_B_DTEP    0x00000003U
+#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
+#define MCPWM_GEN2_B_DTEP_V  0x00000003U
+#define MCPWM_GEN2_B_DTEP_S  14
+/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM2B triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN2_B_DTEA    0x00000003U
+#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
+#define MCPWM_GEN2_B_DTEA_V  0x00000003U
+#define MCPWM_GEN2_B_DTEA_S  16
+/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM2B triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN2_B_DTEB    0x00000003U
+#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
+#define MCPWM_GEN2_B_DTEB_V  0x00000003U
+#define MCPWM_GEN2_B_DTEB_S  18
+/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM2B triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN2_B_DT0    0x00000003U
+#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
+#define MCPWM_GEN2_B_DT0_V  0x00000003U
+#define MCPWM_GEN2_B_DT0_S  20
+/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_DT1    0x00000003U
+#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
+#define MCPWM_GEN2_B_DT1_V  0x00000003U
+#define MCPWM_GEN2_B_DT1_S  22
+
+/** MCPWM_DT2_CFG_REG register
+ *  dead time type selection and configuration
+ */
+#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8)
+/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (falling edge delay) active register.  0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
+#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_S  0
+/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register.  0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
+#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_S  4
+/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB2_DEB_MODE    (BIT(8))
+#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
+#define MCPWM_DB2_DEB_MODE_V  0x00000001U
+#define MCPWM_DB2_DEB_MODE_S  8
+/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
+#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_A_OUTSWAP_S  9
+/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
+#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_B_OUTSWAP_S  10
+/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DB2_RED_INSEL    (BIT(11))
+#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
+#define MCPWM_DB2_RED_INSEL_V  0x00000001U
+#define MCPWM_DB2_RED_INSEL_S  11
+/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DB2_FED_INSEL    (BIT(12))
+#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
+#define MCPWM_DB2_FED_INSEL_V  0x00000001U
+#define MCPWM_DB2_FED_INSEL_S  12
+/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
+#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_RED_OUTINVERT_S  13
+/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
+#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_FED_OUTINVERT_S  14
+/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
+#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_A_OUTBYPASS_S  15
+/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
+#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_B_OUTBYPASS_S  16
+/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DB2_CLK_SEL    (BIT(17))
+#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
+#define MCPWM_DB2_CLK_SEL_V  0x00000001U
+#define MCPWM_DB2_CLK_SEL_S  17
+
+/** MCPWM_DT2_FED_CFG_REG register
+ *  Shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc)
+/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DB2_FED    0x0000FFFFU
+#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
+#define MCPWM_DB2_FED_V  0x0000FFFFU
+#define MCPWM_DB2_FED_S  0
+
+/** MCPWM_DT2_RED_CFG_REG register
+ *  Shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0)
+/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DB2_RED    0x0000FFFFU
+#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
+#define MCPWM_DB2_RED_V  0x0000FFFFU
+#define MCPWM_DB2_RED_S  0
+
+/** MCPWM_CARRIER2_CFG_REG register
+ *  Carrier enable and configuration
+ */
+#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4)
+/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier2 function is enabled. When cleared, carrier2 is bypassed
+ */
+#define MCPWM_CHOPPER2_EN    (BIT(0))
+#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
+#define MCPWM_CHOPPER2_EN_V  0x00000001U
+#define MCPWM_CHOPPER2_EN_S  0
+/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
+#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_S  1
+/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CHOPPER2_DUTY    0x00000007U
+#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
+#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER2_DUTY_S  5
+/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
+#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_S  8
+/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM2A and PWM2B for this submodule
+ */
+#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
+#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_OUT_INVERT_S  12
+/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM2A and PWM2B for this submodule
+ */
+#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
+#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_IN_INVERT_S  13
+
+/** MCPWM_FH2_CFG0_REG register
+ *  Actions on PWM2A and PWM2B trip events
+ */
+#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd8)
+/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_SW_CBC    (BIT(0))
+#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
+#define MCPWM_TZ2_SW_CBC_V  0x00000001U
+#define MCPWM_TZ2_SW_CBC_S  0
+/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F2_CBC    (BIT(1))
+#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
+#define MCPWM_TZ2_F2_CBC_V  0x00000001U
+#define MCPWM_TZ2_F2_CBC_S  1
+/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F1_CBC    (BIT(2))
+#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
+#define MCPWM_TZ2_F1_CBC_V  0x00000001U
+#define MCPWM_TZ2_F1_CBC_S  2
+/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F0_CBC    (BIT(3))
+#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
+#define MCPWM_TZ2_F0_CBC_V  0x00000001U
+#define MCPWM_TZ2_F0_CBC_S  3
+/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_SW_OST    (BIT(4))
+#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
+#define MCPWM_TZ2_SW_OST_V  0x00000001U
+#define MCPWM_TZ2_SW_OST_S  4
+/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F2_OST    (BIT(5))
+#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
+#define MCPWM_TZ2_F2_OST_V  0x00000001U
+#define MCPWM_TZ2_F2_OST_S  5
+/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F1_OST    (BIT(6))
+#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
+#define MCPWM_TZ2_F1_OST_V  0x00000001U
+#define MCPWM_TZ2_F1_OST_S  6
+/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F0_OST    (BIT(7))
+#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
+#define MCPWM_TZ2_F0_OST_V  0x00000001U
+#define MCPWM_TZ2_F0_OST_S  7
+/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_A_CBC_D    0x00000003U
+#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
+#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_D_S  8
+/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_A_CBC_U    0x00000003U
+#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
+#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_U_S  10
+/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_A_OST_D    0x00000003U
+#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
+#define MCPWM_TZ2_A_OST_D_V  0x00000003U
+#define MCPWM_TZ2_A_OST_D_S  12
+/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_A_OST_U    0x00000003U
+#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
+#define MCPWM_TZ2_A_OST_U_V  0x00000003U
+#define MCPWM_TZ2_A_OST_U_S  14
+/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_B_CBC_D    0x00000003U
+#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
+#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_D_S  16
+/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_B_CBC_U    0x00000003U
+#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
+#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_U_S  18
+/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_B_OST_D    0x00000003U
+#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
+#define MCPWM_TZ2_B_OST_D_V  0x00000003U
+#define MCPWM_TZ2_B_OST_D_S  20
+/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_B_OST_U    0x00000003U
+#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
+#define MCPWM_TZ2_B_OST_U_V  0x00000003U
+#define MCPWM_TZ2_B_OST_U_S  22
+
+/** MCPWM_FH2_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xdc)
+/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_TZ2_CLR_OST    (BIT(0))
+#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
+#define MCPWM_TZ2_CLR_OST_V  0x00000001U
+#define MCPWM_TZ2_CLR_OST_S  0
+/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP
+ */
+#define MCPWM_TZ2_CBCPULSE    0x00000003U
+#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
+#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ2_CBCPULSE_S  1
+/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
+#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ2_FORCE_CBC_S  3
+/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_TZ2_FORCE_OST    (BIT(4))
+#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
+#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ2_FORCE_OST_S  4
+
+/** MCPWM_FH2_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xe0)
+/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_TZ2_CBC_ON    (BIT(0))
+#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
+#define MCPWM_TZ2_CBC_ON_V  0x00000001U
+#define MCPWM_TZ2_CBC_ON_S  0
+/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_TZ2_OST_ON    (BIT(1))
+#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
+#define MCPWM_TZ2_OST_ON_V  0x00000001U
+#define MCPWM_TZ2_OST_ON_S  1
+
+/** MCPWM_FAULT_DETECT_REG register
+ *  Fault detection configuration and status
+ */
+#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe4)
+/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, event_f0 generation is enabled
+ */
+#define MCPWM_F0_EN    (BIT(0))
+#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
+#define MCPWM_F0_EN_V  0x00000001U
+#define MCPWM_F0_EN_S  0
+/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
+ *  When set, event_f1 generation is enabled
+ */
+#define MCPWM_F1_EN    (BIT(1))
+#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
+#define MCPWM_F1_EN_V  0x00000001U
+#define MCPWM_F1_EN_S  1
+/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
+ *  When set, event_f2 generation is enabled
+ */
+#define MCPWM_F2_EN    (BIT(2))
+#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
+#define MCPWM_F2_EN_V  0x00000001U
+#define MCPWM_F2_EN_S  2
+/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
+ *  Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+ *  level high
+ */
+#define MCPWM_F0_POLE    (BIT(3))
+#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
+#define MCPWM_F0_POLE_V  0x00000001U
+#define MCPWM_F0_POLE_S  3
+/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
+ *  Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+ *  level high
+ */
+#define MCPWM_F1_POLE    (BIT(4))
+#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
+#define MCPWM_F1_POLE_V  0x00000001U
+#define MCPWM_F1_POLE_S  4
+/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
+ *  Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+ *  level high
+ */
+#define MCPWM_F2_POLE    (BIT(5))
+#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
+#define MCPWM_F2_POLE_V  0x00000001U
+#define MCPWM_F2_POLE_S  5
+/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
+ *  Set and reset by hardware. If set, event_f0 is on going
+ */
+#define MCPWM_EVENT_F0    (BIT(6))
+#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
+#define MCPWM_EVENT_F0_V  0x00000001U
+#define MCPWM_EVENT_F0_S  6
+/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
+ *  Set and reset by hardware. If set, event_f1 is on going
+ */
+#define MCPWM_EVENT_F1    (BIT(7))
+#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
+#define MCPWM_EVENT_F1_V  0x00000001U
+#define MCPWM_EVENT_F1_S  7
+/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, event_f2 is on going
+ */
+#define MCPWM_EVENT_F2    (BIT(8))
+#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
+#define MCPWM_EVENT_F2_V  0x00000001U
+#define MCPWM_EVENT_F2_S  8
+
+/** MCPWM_CAP_TIMER_CFG_REG register
+ *  Configure capture timer
+ */
+#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe8)
+/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture timer incrementing under APB_clk is enabled.
+ */
+#define MCPWM_CAP_TIMER_EN    (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
+#define MCPWM_CAP_TIMER_EN_V  0x00000001U
+#define MCPWM_CAP_TIMER_EN_S  0
+/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
+ *  When set, capture timer sync is enabled.
+ */
+#define MCPWM_CAP_SYNCI_EN    (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
+#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
+#define MCPWM_CAP_SYNCI_EN_S  1
+/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
+ *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
+ *  6: SYNC2 from GPIO matrix
+ */
+#define MCPWM_CAP_SYNCI_SEL    0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
+#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
+ *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
+ *  timer is loaded with value in phase register.
+ */
+#define MCPWM_CAP_SYNC_SW    (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
+#define MCPWM_CAP_SYNC_SW_V  0x00000001U
+#define MCPWM_CAP_SYNC_SW_S  5
+
+/** MCPWM_CAP_TIMER_PHASE_REG register
+ *  Phase for capture timer sync
+ */
+#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xec)
+/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
+ *  Phase value for capture timer sync operation.
+ */
+#define MCPWM_CAP_PHASE    0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
+#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_S  0
+
+/** MCPWM_CAP_CH0_CFG_REG register
+ *  Capture channel 0 configuration and enable
+ */
+#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 0 is enabled
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP0 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 0
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH1_CFG_REG register
+ *  Capture channel 1 configuration and enable
+ */
+#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4)
+/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 2 is enabled
+ */
+#define MCPWM_CAP1_EN    (BIT(0))
+#define MCPWM_CAP1_EN_M  (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S)
+#define MCPWM_CAP1_EN_V  0x00000001U
+#define MCPWM_CAP1_EN_S  0
+/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP1_MODE    0x00000003U
+#define MCPWM_CAP1_MODE_M  (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S)
+#define MCPWM_CAP1_MODE_V  0x00000003U
+#define MCPWM_CAP1_MODE_S  1
+/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP1_PRESCALE    0x000000FFU
+#define MCPWM_CAP1_PRESCALE_M  (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S)
+#define MCPWM_CAP1_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP1_PRESCALE_S  3
+/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP1 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP1_IN_INVERT    (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_M  (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S)
+#define MCPWM_CAP1_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP1_IN_INVERT_S  11
+/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 1
+ */
+#define MCPWM_CAP1_SW    (BIT(12))
+#define MCPWM_CAP1_SW_M  (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S)
+#define MCPWM_CAP1_SW_V  0x00000001U
+#define MCPWM_CAP1_SW_S  12
+
+/** MCPWM_CAP_CH2_CFG_REG register
+ *  Capture channel 2 configuration and enable
+ */
+#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf8)
+/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 2 is enabled
+ */
+#define MCPWM_CAP2_EN    (BIT(0))
+#define MCPWM_CAP2_EN_M  (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S)
+#define MCPWM_CAP2_EN_V  0x00000001U
+#define MCPWM_CAP2_EN_S  0
+/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP2_MODE    0x00000003U
+#define MCPWM_CAP2_MODE_M  (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S)
+#define MCPWM_CAP2_MODE_V  0x00000003U
+#define MCPWM_CAP2_MODE_S  1
+/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP2_PRESCALE    0x000000FFU
+#define MCPWM_CAP2_PRESCALE_M  (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S)
+#define MCPWM_CAP2_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP2_PRESCALE_S  3
+/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP2 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP2_IN_INVERT    (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_M  (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S)
+#define MCPWM_CAP2_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP2_IN_INVERT_S  11
+/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 2
+ */
+#define MCPWM_CAP2_SW    (BIT(12))
+#define MCPWM_CAP2_SW_M  (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S)
+#define MCPWM_CAP2_SW_V  0x00000001U
+#define MCPWM_CAP2_SW_S  12
+
+/** MCPWM_CAP_CH0_REG register
+ *  ch0 capture value status register
+ */
+#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xfc)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 0
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_CH1_REG register
+ *  ch1 capture value status register
+ */
+#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100)
+/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 1
+ */
+#define MCPWM_CAP1_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP1_VALUE_M  (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S)
+#define MCPWM_CAP1_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP1_VALUE_S  0
+
+/** MCPWM_CAP_CH2_REG register
+ *  ch2 capture value status register
+ */
+#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104)
+/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 2
+ */
+#define MCPWM_CAP2_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP2_VALUE_M  (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S)
+#define MCPWM_CAP2_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP2_VALUE_S  0
+
+/** MCPWM_CAP_STATUS_REG register
+ *  Edge of last capture trigger
+ */
+#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108)
+/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
+ *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP0_EDGE    (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
+#define MCPWM_CAP0_EDGE_V  0x00000001U
+#define MCPWM_CAP0_EDGE_S  0
+/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
+ *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP1_EDGE    (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
+#define MCPWM_CAP1_EDGE_V  0x00000001U
+#define MCPWM_CAP1_EDGE_S  1
+/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
+ *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP2_EDGE    (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
+#define MCPWM_CAP2_EDGE_V  0x00000001U
+#define MCPWM_CAP2_EDGE_S  2
+
+/** MCPWM_UPDATE_CFG_REG register
+ *  Enable update.
+ */
+#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10c)
+/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
+ *  The global enable of update of all active registers in MCPWM module
+ */
+#define MCPWM_GLOBAL_UP_EN    (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
+#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
+#define MCPWM_GLOBAL_UP_EN_S  0
+/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of all active
+ *  registers in MCPWM module
+ */
+#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
+#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
+ *  are enabled
+ */
+#define MCPWM_OP0_UP_EN    (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
+#define MCPWM_OP0_UP_EN_V  0x00000001U
+#define MCPWM_OP0_UP_EN_S  2
+/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 0
+ */
+#define MCPWM_OP0_FORCE_UP    (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
+#define MCPWM_OP0_FORCE_UP_V  0x00000001U
+#define MCPWM_OP0_FORCE_UP_S  3
+/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
+ *  are enabled
+ */
+#define MCPWM_OP1_UP_EN    (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
+#define MCPWM_OP1_UP_EN_V  0x00000001U
+#define MCPWM_OP1_UP_EN_S  4
+/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 1
+ */
+#define MCPWM_OP1_FORCE_UP    (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
+#define MCPWM_OP1_FORCE_UP_V  0x00000001U
+#define MCPWM_OP1_FORCE_UP_S  5
+/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
+ *  are enabled
+ */
+#define MCPWM_OP2_UP_EN    (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
+#define MCPWM_OP2_UP_EN_V  0x00000001U
+#define MCPWM_OP2_UP_EN_S  6
+/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 2
+ */
+#define MCPWM_OP2_FORCE_UP    (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
+#define MCPWM_OP2_FORCE_UP_V  0x00000001U
+#define MCPWM_OP2_FORCE_UP_S  7
+
+/** MCPWM_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x110)
+/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ENA    (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
+#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_INT_ENA_S  9
+/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ENA    (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
+#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_INT_ENA_S  10
+/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ENA    (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
+#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_INT_ENA_S  11
+/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
+#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ENA_S  15
+/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
+#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ENA_S  16
+/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
+#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ENA_S  17
+/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
+#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ENA_S  18
+/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
+#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ENA_S  19
+/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
+#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ENA_S  20
+/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
+#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ENA_S  21
+/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
+#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ENA_S  22
+/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
+#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ENA_S  23
+/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
+#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ENA_S  24
+/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
+#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ENA_S  25
+/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
+#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ENA_S  26
+/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_ENA    (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
+#define MCPWM_CAP0_INT_ENA_V  0x00000001U
+#define MCPWM_CAP0_INT_ENA_S  27
+/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_ENA    (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
+#define MCPWM_CAP1_INT_ENA_V  0x00000001U
+#define MCPWM_CAP1_INT_ENA_S  28
+/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_ENA    (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
+#define MCPWM_CAP2_INT_ENA_V  0x00000001U
+#define MCPWM_CAP2_INT_ENA_S  29
+
+/** MCPWM_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x114)
+/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_RAW    (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
+#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_INT_RAW_S  9
+/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_RAW    (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
+#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_INT_RAW_S  10
+/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_RAW    (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
+#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_INT_RAW_S  11
+/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
+#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_RAW_S  15
+/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
+#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_RAW_S  16
+/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
+#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_RAW_S  17
+/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
+#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_RAW_S  18
+/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
+#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_RAW_S  19
+/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
+#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_RAW_S  20
+/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
+#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_RAW_S  21
+/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
+#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_RAW_S  22
+/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
+#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_RAW_S  23
+/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
+#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
+#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_RAW_S  24
+/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
+#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
+#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_RAW_S  25
+/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
+#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
+#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_RAW_S  26
+/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_RAW    (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
+#define MCPWM_CAP0_INT_RAW_V  0x00000001U
+#define MCPWM_CAP0_INT_RAW_S  27
+/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_RAW    (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
+#define MCPWM_CAP1_INT_RAW_V  0x00000001U
+#define MCPWM_CAP1_INT_RAW_S  28
+/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_RAW    (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
+#define MCPWM_CAP2_INT_RAW_V  0x00000001U
+#define MCPWM_CAP2_INT_RAW_S  29
+
+/** MCPWM_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x118)
+/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ST    (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
+#define MCPWM_FAULT0_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_INT_ST_S  9
+/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ST    (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
+#define MCPWM_FAULT1_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_INT_ST_S  10
+/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ST    (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
+#define MCPWM_FAULT2_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_INT_ST_S  11
+/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
+#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ST_S  15
+/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
+#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ST_S  16
+/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
+#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ST_S  17
+/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
+#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ST_S  18
+/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
+#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ST_S  19
+/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
+#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ST_S  20
+/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
+#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ST_S  21
+/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
+#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ST_S  22
+/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
+#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ST_S  23
+/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
+#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ST_S  24
+/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
+#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ST_S  25
+/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
+#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ST_S  26
+/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_ST    (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
+#define MCPWM_CAP0_INT_ST_V  0x00000001U
+#define MCPWM_CAP0_INT_ST_S  27
+/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_ST    (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
+#define MCPWM_CAP1_INT_ST_V  0x00000001U
+#define MCPWM_CAP1_INT_ST_S  28
+/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_ST    (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
+#define MCPWM_CAP2_INT_ST_V  0x00000001U
+#define MCPWM_CAP2_INT_ST_S  29
+
+/** MCPWM_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x11c)
+/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_CLR    (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
+#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_INT_CLR_S  9
+/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_CLR    (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
+#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_INT_CLR_S  10
+/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_CLR    (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
+#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_INT_CLR_S  11
+/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
+#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_CLR_S  15
+/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
+#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_CLR_S  16
+/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
+#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_CLR_S  17
+/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
+#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_CLR_S  18
+/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
+#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_CLR_S  19
+/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
+#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_CLR_S  20
+/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
+#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_CLR_S  21
+/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
+#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_CLR_S  22
+/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
+#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_CLR_S  23
+/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
+#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
+#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_CLR_S  24
+/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
+#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
+#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_CLR_S  25
+/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
+#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
+#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_CLR_S  26
+/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_CLR    (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
+#define MCPWM_CAP0_INT_CLR_V  0x00000001U
+#define MCPWM_CAP0_INT_CLR_S  27
+/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_CLR    (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
+#define MCPWM_CAP1_INT_CLR_V  0x00000001U
+#define MCPWM_CAP1_INT_CLR_S  28
+/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_CLR    (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
+#define MCPWM_CAP2_INT_CLR_V  0x00000001U
+#define MCPWM_CAP2_INT_CLR_S  29
+
+/** MCPWM_EVT_EN_REG register
+ *  MCPWM event enable register
+ */
+#define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120)
+/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit high to enable timer0 stop event generate
+ */
+#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
+#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
+#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_STOP_EN_S  0
+/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
+ *  set this bit high to enable timer1 stop event generate
+ */
+#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
+#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
+#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_STOP_EN_S  1
+/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
+ *  set this bit high to enable timer2 stop event generate
+ */
+#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
+#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
+#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_STOP_EN_S  2
+/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
+ *  set this bit high to enable timer0 equal zero event generate
+ */
+#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
+#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
+#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
+/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
+ *  set this bit high to enable timer1 equal zero event generate
+ */
+#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
+#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
+#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
+/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
+ *  set this bit high to enable timer2 equal zero event generate
+ */
+#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
+#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
+#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
+/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
+ *  set this bit high to enable timer0 equal period event generate
+ */
+#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
+#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
+#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEP_EN_S  6
+/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
+ *  set this bit high to enable timer1 equal period event generate
+ */
+#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
+#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
+#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEP_EN_S  7
+/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
+ *  set this bit high to enable timer2 equal period event generate
+ */
+#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
+#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
+#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEP_EN_S  8
+/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
+ *  set this bit high to enable PWM generator0 timer equal a event generate
+ */
+#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
+#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
+#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEA_EN_S  9
+/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
+ *  set this bit high to enable PWM generator1 timer equal a event generate
+ */
+#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
+#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
+#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEA_EN_S  10
+/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
+ *  set this bit high to enable PWM generator2 timer equal a event generate
+ */
+#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
+#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
+#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEA_EN_S  11
+/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
+ *  set this bit high to enable PWM generator0 timer equal b event generate
+ */
+#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
+#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
+#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEB_EN_S  12
+/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
+ *  set this bit high to enable PWM generator1 timer equal b event generate
+ */
+#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
+#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
+#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEB_EN_S  13
+/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
+ *  set this bit high to enable PWM generator2 timer equal b event generate
+ */
+#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
+#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
+#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEB_EN_S  14
+/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
+ *  set this bit high to enable fault0 event generate
+ */
+#define MCPWM_EVT_F0_EN    (BIT(15))
+#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
+#define MCPWM_EVT_F0_EN_V  0x00000001U
+#define MCPWM_EVT_F0_EN_S  15
+/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
+ *  set this bit high to enable fault1 event generate
+ */
+#define MCPWM_EVT_F1_EN    (BIT(16))
+#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
+#define MCPWM_EVT_F1_EN_V  0x00000001U
+#define MCPWM_EVT_F1_EN_S  16
+/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
+ *  set this bit high to enable fault2 event generate
+ */
+#define MCPWM_EVT_F2_EN    (BIT(17))
+#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
+#define MCPWM_EVT_F2_EN_V  0x00000001U
+#define MCPWM_EVT_F2_EN_S  17
+/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
+ *  set this bit high to enable fault0 clear event generate
+ */
+#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
+#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
+#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F0_CLR_EN_S  18
+/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  set this bit high to enable fault1 clear event generate
+ */
+#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
+#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
+#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F1_CLR_EN_S  19
+/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  set this bit high to enable fault2 clear event generate
+ */
+#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
+#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
+#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F2_CLR_EN_S  20
+/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
+ *  set this bit high to enable cycle by cycle trip0 event generate
+ */
+#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
+#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
+#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_CBC_EN_S  21
+/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
+ *  set this bit high to enable cycle by cycle trip1 event generate
+ */
+#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
+#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
+#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_CBC_EN_S  22
+/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
+ *  set this bit high to enable cycle by cycle trip2 event generate
+ */
+#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
+#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
+#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_CBC_EN_S  23
+/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
+ *  set this bit high to enable one shot trip0 event generate
+ */
+#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
+#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
+#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_OST_EN_S  24
+/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
+ *  set this bit high to enable one shot trip1 event generate
+ */
+#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
+#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
+#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_OST_EN_S  25
+/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
+ *  set this bit high to enable one shot trip2 event generate
+ */
+#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
+#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
+#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_OST_EN_S  26
+/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
+ *  set this bit high to enable capture0 event generate
+ */
+#define MCPWM_EVT_CAP0_EN    (BIT(27))
+#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
+#define MCPWM_EVT_CAP0_EN_V  0x00000001U
+#define MCPWM_EVT_CAP0_EN_S  27
+/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
+ *  set this bit high to enable capture1 event generate
+ */
+#define MCPWM_EVT_CAP1_EN    (BIT(28))
+#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
+#define MCPWM_EVT_CAP1_EN_V  0x00000001U
+#define MCPWM_EVT_CAP1_EN_S  28
+/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
+ *  set this bit high to enable capture2 event generate
+ */
+#define MCPWM_EVT_CAP2_EN    (BIT(29))
+#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
+#define MCPWM_EVT_CAP2_EN_V  0x00000001U
+#define MCPWM_EVT_CAP2_EN_S  29
+
+/** MCPWM_TASK_EN_REG register
+ *  MCPWM task enable register
+ */
+#define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x124)
+/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit high to enable PWM generator0 timer stamp A's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
+#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
+#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
+/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
+ *  set this bit high to enable PWM generator1 timer stamp A's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
+#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
+#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
+/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
+ *  set this bit high to enable PWM generator2 timer stamp A's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
+#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
+#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
+/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
+ *  set this bit high to enable PWM generator0 timer stamp B's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
+#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
+#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
+/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
+ *  set this bit high to enable PWM generator1 timer stamp B's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
+#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
+#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
+/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
+ *  set this bit high to enable PWM generator2 timer stamp B's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
+#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
+#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
+/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
+ *  set this bit high to enable all PWM generate stop task receive
+ */
+#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
+#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
+#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
+#define MCPWM_TASK_GEN_STOP_EN_S  6
+/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
+ *  set this bit high to enable timer0 sync task receive
+ */
+#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
+#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
+#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
+/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
+ *  set this bit high to enable timer1 sync task receive
+ */
+#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
+#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
+#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
+/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
+ *  set this bit high to enable timer2 sync task receive
+ */
+#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
+#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
+#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
+/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
+ *  set this bit high to enable timer0 period update task receive
+ */
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
+/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
+ *  set this bit high to enable timer1 period update task receive
+ */
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
+/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
+ *  set this bit high to enable timer2 period update task receive
+ */
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
+/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
+ *  set this bit high to enable one shot trip0 task receive
+ */
+#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
+#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
+#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ0_OST_EN_S  13
+/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
+ *  set this bit high to enable one shot trip1 task receive
+ */
+#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
+#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
+#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ1_OST_EN_S  14
+/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
+ *  set this bit high to enable one shot trip2 task receive
+ */
+#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
+#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
+#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ2_OST_EN_S  15
+/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
+ *  set this bit high to enable one shot trip0 clear task receive
+ */
+#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
+#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
+#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR0_OST_EN_S  16
+/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
+ *  set this bit high to enable one shot trip1 clear task receive
+ */
+#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
+#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
+#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR1_OST_EN_S  17
+/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
+ *  set this bit high to enable one shot trip2 clear task receive
+ */
+#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
+#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
+#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR2_OST_EN_S  18
+/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
+ *  set this bit high to enable capture0 task receive
+ */
+#define MCPWM_TASK_CAP0_EN    (BIT(19))
+#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
+#define MCPWM_TASK_CAP0_EN_V  0x00000001U
+#define MCPWM_TASK_CAP0_EN_S  19
+/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
+ *  set this bit high to enable capture1 task receive
+ */
+#define MCPWM_TASK_CAP1_EN    (BIT(20))
+#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
+#define MCPWM_TASK_CAP1_EN_V  0x00000001U
+#define MCPWM_TASK_CAP1_EN_S  20
+/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
+ *  set this bit high to enable capture2 task receive
+ */
+#define MCPWM_TASK_CAP2_EN    (BIT(21))
+#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
+#define MCPWM_TASK_CAP2_EN_V  0x00000001U
+#define MCPWM_TASK_CAP2_EN_S  21
+
+/** MCPWM_CLK_REG register
+ *  MCPWM APB configuration register
+ */
+#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x128)
+/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Force clock on for this register file
+ */
+#define MCPWM_CLK_EN    (BIT(0))
+#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
+#define MCPWM_CLK_EN_V  0x00000001U
+#define MCPWM_CLK_EN_S  0
+
+/** MCPWM_VERSION_REG register
+ *  Version register.
+ */
+#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x12c)
+/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35656256;
+ *  Version of this register file
+ */
+#define MCPWM_DATE    0x0FFFFFFFU
+#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
+#define MCPWM_DATE_V  0x0FFFFFFFU
+#define MCPWM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/mcpwm_struct.h b/components/soc/esp32c6/register/soc/mcpwm_struct.h
new file mode 100644
index 00000000000..5fe75f3c99e
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/mcpwm_struct.h
@@ -0,0 +1,1694 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Prescaler configuration */
+/** Type of clk_cfg register
+ *  PWM clock prescaler register.
+ */
+typedef union {
+    struct {
+        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
+         */
+        uint32_t clk_prescale:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_clk_cfg_reg_t;
+
+
+/** Group: MCPWM Timer Configuration and status */
+/** Type of timer_cfg0 register
+ *  PWM timer period and update method configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1)
+         */
+        uint32_t timer_prescale:8;
+        /** timer_period : R/W; bitpos: [23:8]; default: 255;
+         *  period shadow register of PWM timer
+         */
+        uint32_t timer_period:16;
+        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
+         *  Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2:
+         *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+         */
+        uint32_t timer_period_upmethod:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg0_reg_t;
+
+/** Type of timer_cfg1 register
+ *  PWM timer0 working mode and start/stop control configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1:
+         *  if timer0 starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer
+         *  starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP
+         *  here and below means the event that happens when the timer equals to period
+         */
+        uint32_t timer_start:3;
+        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
+         *  PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+         *  mode
+         */
+        uint32_t timer_mod:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg1_reg_t;
+
+/** Type of timer_sync register
+ *  PWM timer sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
+         *  When set, timer reloading with phase on sync input event is enabled.
+         */
+        uint32_t timer_synci_en:1;
+        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Toggling this bit will trigger a software sync.
+         */
+        uint32_t timer_sync_sw:1;
+        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+         *  generate when toggling the reg_timer0_sync_sw bit
+         */
+        uint32_t timer_synco_sel:2;
+        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
+         *  phase for timer reload on sync event
+         */
+        uint32_t timer_phase:16;
+        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configure the PWM timer0's direction when timer mode is up-down mode:
+         *  0-increase,1-decrease
+         */
+        uint32_t timer_phase_direction:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} mcpwm_timer_sync_reg_t;
+
+/** Type of timer_status register
+ *  PWM timer status register.
+ */
+typedef union {
+    struct {
+        /** timer_value : RO; bitpos: [15:0]; default: 0;
+         *  current PWM timer counter value
+         */
+        uint32_t timer_value:16;
+        /** timer_direction : RO; bitpos: [16]; default: 0;
+         *  current PWM timer counter direction, 0: increment 1: decrement
+         */
+        uint32_t timer_direction:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} mcpwm_timer_status_reg_t;
+
+
+/** Group: Common configuration for MCPWM timers */
+/** Type of timer_synci_cfg register
+ *  Synchronization input selection for three PWM timers.
+ */
+typedef union {
+    struct {
+        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
+         *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer0_syncisel:3;
+        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
+         *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer1_syncisel:3;
+        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
+         *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer2_syncisel:3;
+        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
+         *  invert SYNC0 from GPIO matrix
+         */
+        uint32_t external_synci0_invert:1;
+        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
+         *  invert SYNC1 from GPIO matrix
+         */
+        uint32_t external_synci1_invert:1;
+        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
+         *  invert SYNC2 from GPIO matrix
+         */
+        uint32_t external_synci2_invert:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} mcpwm_timer_synci_cfg_reg_t;
+
+/** Type of operator_timersel register
+ *  Select specific timer for PWM operators.
+ */
+typedef union {
+    struct {
+        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
+         *  Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator0_timersel:2;
+        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
+         *  Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator1_timersel:2;
+        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
+         *  Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator2_timersel:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_operator_timersel_reg_t;
+
+
+/** Group: MCPWM Operator Configuration and Status */
+/** Type of gen_stmp_cfg register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+typedef union {
+    struct {
+        /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for PWM generator time stamp A's active register. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+         */
+        uint32_t cmpr_a_upmethod:4;
+        /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Update method for PWM generator time stamp B's active register. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+         */
+        uint32_t cmpr_b_upmethod:4;
+        /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
+         *  Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is
+         *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+         *  has been updated with shadow register latest value
+         */
+        uint32_t cmpr_a_shdw_full:1;
+        /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
+         *  Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is
+         *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+         *  has been updated with shadow register latest value
+         */
+        uint32_t cmpr_b_shdw_full:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_stmp_cfg_reg_t;
+
+/** Type of gen_tstmp register
+ *  Shadow register for register B.
+ */
+typedef union {
+    struct {
+        /** cmpr : R/W; bitpos: [15:0]; default: 0;
+         *  PWM generator time stamp's shadow register
+         */
+        uint32_t cmpr:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_tstmp_reg_t;
+
+/** Type of gen_cfg0 register
+ *  Fault event T0 and T1 handling
+ */
+typedef union {
+    struct {
+        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for PWM generator's active register of configuration. When all bits
+         *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+         *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
+         */
+        uint32_t gen_cfg_upmethod:4;
+        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
+         *  Source selection for PWM generator event_t0, take effect immediately, 0:
+         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+         */
+        uint32_t gen_t0_sel:3;
+        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
+         *  Source selection for PWM generator event_t1, take effect immediately, 0:
+         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+         */
+        uint32_t gen_t1_sel:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_cfg0_reg_t;
+
+/** Type of gen_force register
+ *  Permissives to force PWM0A and PWM0B outputs by software
+ */
+typedef union {
+    struct {
+        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
+         *  Updating method for continuous software force of PWM generator. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
+         *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+         *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+         *  generated when the timer's value equals to that of register A/B.)
+         */
+        uint32_t gen_cntuforce_upmethod:6;
+        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
+         *  Continuous software force mode for PWMnA. 0: disabled, 1: low, 2: high, 3: disabled
+         */
+        uint32_t gen_a_cntuforce_mode:2;
+        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
+         *  Continuous software force mode for PWMnB. 0: disabled, 1: low, 2: high, 3: disabled
+         */
+        uint32_t gen_b_cntuforce_mode:2;
+        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
+         *  Trigger of non-continuous immediate software-force event for PWMnA, a toggle will
+         *  trigger a force event.
+         */
+        uint32_t gen_a_nciforce:1;
+        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
+         *  non-continuous immediate software force mode for PWMnA, 0: disabled, 1: low, 2:
+         *  high, 3: disabled
+         */
+        uint32_t gen_a_nciforce_mode:2;
+        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
+         *  Trigger of non-continuous immediate software-force event for PWMnB, a toggle will
+         *  trigger a force event.
+         */
+        uint32_t gen_b_nciforce:1;
+        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
+         *  non-continuous immediate software force mode for PWMnB, 0: disabled, 1: low, 2:
+         *  high, 3: disabled
+         */
+        uint32_t gen_b_nciforce_mode:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_force_reg_t;
+
+/** Type of gen register
+ *  Actions triggered by events on PWM0B
+ */
+typedef union {
+    struct {
+        /** gen_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Action on PWMnA/B triggered by event TEZ when timer increasing
+         */
+        uint32_t gen_utez:2;
+        /** gen_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Action on PWMnA/B triggered by event TEP when timer increasing
+         */
+        uint32_t gen_utep:2;
+        /** gen_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Action on PWMnA/B triggered by event TEA when timer increasing
+         */
+        uint32_t gen_utea:2;
+        /** gen_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Action on PWMnA/B triggered by event TEB when timer increasing
+         */
+        uint32_t gen_uteb:2;
+        /** gen_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Action on PWMnA/B triggered by event_t0 when timer increasing
+         */
+        uint32_t gen_ut0:2;
+        /** gen_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Action on PWMnA/B triggered by event_t1 when timer increasing
+         */
+        uint32_t gen_ut1:2;
+        /** gen_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Action on PWMnA/B triggered by event TEZ when timer decreasing
+         */
+        uint32_t gen_dtez:2;
+        /** gen_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Action on PWMnA/B triggered by event TEP when timer decreasing
+         */
+        uint32_t gen_dtep:2;
+        /** gen_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Action on PWMnA/B triggered by event TEA when timer decreasing
+         */
+        uint32_t gen_dtea:2;
+        /** gen_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Action on PWMnA/B triggered by event TEB when timer decreasing
+         */
+        uint32_t gen_dteb:2;
+        /** gen_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Action on PWMnA/B triggered by event_t0 when timer decreasing
+         */
+        uint32_t gen_dt0:2;
+        /** gen_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Action on PWMnA/B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_dt1:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_gen_reg_t;
+
+/** Type of dt_cfg register
+ *  dead time type selection and configuration
+ */
+typedef union {
+    struct {
+        /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
+         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+         *  bit3 is set to 1: disable the update
+         */
+        uint32_t db_fed_upmethod:4;
+        /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
+         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+         *  bit3 is set to 1: disable the update
+         */
+        uint32_t db_red_upmethod:4;
+        /** db_deb_mode : R/W; bitpos: [8]; default: 0;
+         *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+         *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+         */
+        uint32_t db_deb_mode:1;
+        /** db_a_outswap : R/W; bitpos: [9]; default: 0;
+         *  S6 in table
+         */
+        uint32_t db_a_outswap:1;
+        /** db_b_outswap : R/W; bitpos: [10]; default: 0;
+         *  S7 in table
+         */
+        uint32_t db_b_outswap:1;
+        /** db_red_insel : R/W; bitpos: [11]; default: 0;
+         *  S4 in table
+         */
+        uint32_t db_red_insel:1;
+        /** db_fed_insel : R/W; bitpos: [12]; default: 0;
+         *  S5 in table
+         */
+        uint32_t db_fed_insel:1;
+        /** db_red_outinvert : R/W; bitpos: [13]; default: 0;
+         *  S2 in table
+         */
+        uint32_t db_red_outinvert:1;
+        /** db_fed_outinvert : R/W; bitpos: [14]; default: 0;
+         *  S3 in table
+         */
+        uint32_t db_fed_outinvert:1;
+        /** db_a_outbypass : R/W; bitpos: [15]; default: 1;
+         *  S1 in table
+         */
+        uint32_t db_a_outbypass:1;
+        /** db_b_outbypass : R/W; bitpos: [16]; default: 1;
+         *  S0 in table
+         */
+        uint32_t db_b_outbypass:1;
+        /** db_clk_sel : R/W; bitpos: [17]; default: 0;
+         *  Dead time generator n clock selection. 0: PWM_clk, 1: PT_clk
+         */
+        uint32_t db_clk_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} mcpwm_dt_cfg_reg_t;
+
+/** Type of dt_fed_cfg register
+ *  Shadow register for falling edge delay (FED).
+ */
+typedef union {
+    struct {
+        /** db_fed : R/W; bitpos: [15:0]; default: 0;
+         *  Shadow register for FED
+         */
+        uint32_t db_fed:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_fed_cfg_reg_t;
+
+/** Type of dt_red_cfg register
+ *  Shadow register for rising edge delay (RED).
+ */
+typedef union {
+    struct {
+        /** db_red : R/W; bitpos: [15:0]; default: 0;
+         *  Shadow register for RED
+         */
+        uint32_t db_red:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_red_cfg_reg_t;
+
+/** Type of carrier_cfg register
+ *  Carrier enable and configuration
+ */
+typedef union {
+    struct {
+        /** chopper_en : R/W; bitpos: [0]; default: 0;
+         *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
+         */
+        uint32_t chopper_en:1;
+        /** chopper_prescale : R/W; bitpos: [4:1]; default: 0;
+         *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+         *  (PWM_CARRIER0_PRESCALE + 1)
+         */
+        uint32_t chopper_prescale:4;
+        /** chopper_duty : R/W; bitpos: [7:5]; default: 0;
+         *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+         */
+        uint32_t chopper_duty:3;
+        /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0;
+         *  width of the first pulse in number of periods of the carrier
+         */
+        uint32_t chopper_oshtwth:4;
+        /** chopper_out_invert : R/W; bitpos: [12]; default: 0;
+         *  when set, invert the output of PWM0A and PWM0B for this submodule
+         */
+        uint32_t chopper_out_invert:1;
+        /** chopper_in_invert : R/W; bitpos: [13]; default: 0;
+         *  when set, invert the input of PWM0A and PWM0B for this submodule
+         */
+        uint32_t chopper_in_invert:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} mcpwm_carrier_cfg_reg_t;
+
+/** Type of fh_cfg0 register
+ *  Actions on PWM0A and PWM0B trip events
+ */
+typedef union {
+    struct {
+        /** tz_sw_cbc : R/W; bitpos: [0]; default: 0;
+         *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_sw_cbc:1;
+        /** tz_f2_cbc : R/W; bitpos: [1]; default: 0;
+         *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f2_cbc:1;
+        /** tz_f1_cbc : R/W; bitpos: [2]; default: 0;
+         *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f1_cbc:1;
+        /** tz_f0_cbc : R/W; bitpos: [3]; default: 0;
+         *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f0_cbc:1;
+        /** tz_sw_ost : R/W; bitpos: [4]; default: 0;
+         *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_sw_ost:1;
+        /** tz_f2_ost : R/W; bitpos: [5]; default: 0;
+         *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f2_ost:1;
+        /** tz_f1_ost : R/W; bitpos: [6]; default: 0;
+         *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f1_ost:1;
+        /** tz_f0_ost : R/W; bitpos: [7]; default: 0;
+         *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f0_ost:1;
+        /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_a_cbc_d:2;
+        /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+         *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_a_cbc_u:2;
+        /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0;
+         *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_a_ost_d:2;
+        /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0;
+         *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_a_ost_u:2;
+        /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_b_cbc_d:2;
+        /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+         *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_b_cbc_u:2;
+        /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0;
+         *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_b_ost_d:2;
+        /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0;
+         *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_b_ost_u:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg0_reg_t;
+
+/** Type of fh_cfg1 register
+ *  Software triggers for fault handler actions
+ */
+typedef union {
+    struct {
+        /** tz_clr_ost : R/W; bitpos: [0]; default: 0;
+         *  a rising edge will clear on going one-shot mode action
+         */
+        uint32_t tz_clr_ost:1;
+        /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0;
+         *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+         *  when bit1 is set to 1:TEP
+         */
+        uint32_t tz_cbcpulse:2;
+        /** tz_force_cbc : R/W; bitpos: [3]; default: 0;
+         *  a toggle trigger a cycle-by-cycle mode action
+         */
+        uint32_t tz_force_cbc:1;
+        /** tz_force_ost : R/W; bitpos: [4]; default: 0;
+         *  a toggle (software negate its value) triggers a one-shot mode action
+         */
+        uint32_t tz_force_ost:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg1_reg_t;
+
+/** Type of fh_status register
+ *  Status of fault events.
+ */
+typedef union {
+    struct {
+        /** tz_cbc_on : RO; bitpos: [0]; default: 0;
+         *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+         */
+        uint32_t tz_cbc_on:1;
+        /** tz_ost_on : RO; bitpos: [1]; default: 0;
+         *  Set and reset by hardware. If set, an one-shot mode action is on going
+         */
+        uint32_t tz_ost_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mcpwm_fh_status_reg_t;
+
+
+/** Group: Fault Detection Configuration and Status */
+/** Type of fault_detect register
+ *  Fault detection configuration and status
+ */
+typedef union {
+    struct {
+        /** f0_en : R/W; bitpos: [0]; default: 0;
+         *  When set, event_f0 generation is enabled
+         */
+        uint32_t f0_en:1;
+        /** f1_en : R/W; bitpos: [1]; default: 0;
+         *  When set, event_f1 generation is enabled
+         */
+        uint32_t f1_en:1;
+        /** f2_en : R/W; bitpos: [2]; default: 0;
+         *  When set, event_f2 generation is enabled
+         */
+        uint32_t f2_en:1;
+        /** f0_pole : R/W; bitpos: [3]; default: 0;
+         *  Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+         *  level high
+         */
+        uint32_t f0_pole:1;
+        /** f1_pole : R/W; bitpos: [4]; default: 0;
+         *  Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+         *  level high
+         */
+        uint32_t f1_pole:1;
+        /** f2_pole : R/W; bitpos: [5]; default: 0;
+         *  Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+         *  level high
+         */
+        uint32_t f2_pole:1;
+        /** event_f0 : RO; bitpos: [6]; default: 0;
+         *  Set and reset by hardware. If set, event_f0 is on going
+         */
+        uint32_t event_f0:1;
+        /** event_f1 : RO; bitpos: [7]; default: 0;
+         *  Set and reset by hardware. If set, event_f1 is on going
+         */
+        uint32_t event_f1:1;
+        /** event_f2 : RO; bitpos: [8]; default: 0;
+         *  Set and reset by hardware. If set, event_f2 is on going
+         */
+        uint32_t event_f2:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} mcpwm_fault_detect_reg_t;
+
+
+/** Group: Capture Configuration and Status */
+/** Type of cap_timer_cfg register
+ *  Configure capture timer
+ */
+typedef union {
+    struct {
+        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
+         *  When set, capture timer incrementing under APB_clk is enabled.
+         */
+        uint32_t cap_timer_en:1;
+        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
+         *  When set, capture timer sync is enabled.
+         */
+        uint32_t cap_synci_en:1;
+        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
+         *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
+         *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
+         *  6: SYNC2 from GPIO matrix
+         */
+        uint32_t cap_synci_sel:3;
+        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
+         *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
+         *  timer is loaded with value in phase register.
+         */
+        uint32_t cap_sync_sw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_cfg_reg_t;
+
+/** Type of cap_timer_phase register
+ *  Phase for capture timer sync
+ */
+typedef union {
+    struct {
+        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
+         *  Phase value for capture timer sync operation.
+         */
+        uint32_t cap_phase:32;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_phase_reg_t;
+
+/** Type of cap_chn_cfg register
+ *  Capture channel n configuration and enable
+ */
+typedef union {
+    struct {
+        /** capn_en : R/W; bitpos: [0]; default: 0;
+         *  When set, capture on channel 0 is enabled
+         */
+        uint32_t capn_en:1;
+        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
+         *  Edge of capture on channel n after prescaling. When bit0 is set to 1: enable
+         *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+         *  edge.
+         */
+        uint32_t capn_mode:2;
+        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
+         *  Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
+         *  1
+         */
+        uint32_t capn_prescale:8;
+        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
+         *  when set, CAPn form GPIO matrix is inverted before prescale
+         */
+        uint32_t capn_in_invert:1;
+        /** capn_sw : WT; bitpos: [12]; default: 0;
+         *  Write 1 will trigger a software forced capture on channel n
+         */
+        uint32_t capn_sw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_cfg_reg_t;
+
+/** Type of cap_chn register
+ *  chn capture value status register
+ */
+typedef union {
+    struct {
+        /** capn_value : RO; bitpos: [31:0]; default: 0;
+         *  Value of last capture on channel n
+         */
+        uint32_t capn_value:32;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_reg_t;
+
+/** Type of cap_status register
+ *  Edge of last capture trigger
+ */
+typedef union {
+    struct {
+        /** cap0_edge : RO; bitpos: [0]; default: 0;
+         *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
+         */
+        uint32_t cap0_edge:1;
+        /** cap1_edge : RO; bitpos: [1]; default: 0;
+         *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
+         */
+        uint32_t cap1_edge:1;
+        /** cap2_edge : RO; bitpos: [2]; default: 0;
+         *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
+         */
+        uint32_t cap2_edge:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} mcpwm_cap_status_reg_t;
+
+
+/** Group: Enable update of active registers */
+/** Type of update_cfg register
+ *  Enable update.
+ */
+typedef union {
+    struct {
+        /** global_up_en : R/W; bitpos: [0]; default: 1;
+         *  The global enable of update of all active registers in MCPWM module
+         */
+        uint32_t global_up_en:1;
+        /** global_force_up : R/W; bitpos: [1]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of all active
+         *  registers in MCPWM module
+         */
+        uint32_t global_force_up:1;
+        /** op0_up_en : R/W; bitpos: [2]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
+         *  are enabled
+         */
+        uint32_t op0_up_en:1;
+        /** op0_force_up : R/W; bitpos: [3]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 0
+         */
+        uint32_t op0_force_up:1;
+        /** op1_up_en : R/W; bitpos: [4]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
+         *  are enabled
+         */
+        uint32_t op1_up_en:1;
+        /** op1_force_up : R/W; bitpos: [5]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 1
+         */
+        uint32_t op1_force_up:1;
+        /** op2_up_en : R/W; bitpos: [6]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
+         *  are enabled
+         */
+        uint32_t op2_up_en:1;
+        /** op2_force_up : R/W; bitpos: [7]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 2
+         */
+        uint32_t op2_force_up:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_update_cfg_reg_t;
+
+
+/** Group: Manage Interrupts */
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_ena:1;
+        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_ena:1;
+        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_ena:1;
+        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_ena:1;
+        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_ena:1;
+        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_ena:1;
+        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_ena:1;
+        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_ena:1;
+        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_ena:1;
+        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_ena:1;
+        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_ena:1;
+        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_ena:1;
+        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f0 ends.
+         */
+        uint32_t fault0_clr_int_ena:1;
+        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f1 ends.
+         */
+        uint32_t fault1_clr_int_ena:1;
+        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f2 ends.
+         */
+        uint32_t fault2_clr_int_ena:1;
+        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_ena:1;
+        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_ena:1;
+        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_ena:1;
+        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_ena:1;
+        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_ena:1;
+        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_ena:1;
+        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_ena:1;
+        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_ena:1;
+        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_ena:1;
+        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_ena:1;
+        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_ena:1;
+        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_ena:1;
+        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_ena:1;
+        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_ena:1;
+        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_ena:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_raw:1;
+        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_raw:1;
+        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_raw:1;
+        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_raw:1;
+        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_raw:1;
+        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_raw:1;
+        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_raw:1;
+        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_raw:1;
+        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_raw:1;
+        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_raw:1;
+        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_raw:1;
+        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_raw:1;
+        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f0 ends.
+         */
+        uint32_t fault0_clr_int_raw:1;
+        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f1 ends.
+         */
+        uint32_t fault1_clr_int_raw:1;
+        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f2 ends.
+         */
+        uint32_t fault2_clr_int_raw:1;
+        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_raw:1;
+        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_raw:1;
+        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_raw:1;
+        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_raw:1;
+        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_raw:1;
+        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_raw:1;
+        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_cbc_int_raw:1;
+        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_cbc_int_raw:1;
+        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_cbc_int_raw:1;
+        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_raw:1;
+        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_raw:1;
+        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_raw:1;
+        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_raw:1;
+        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_raw:1;
+        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_raw:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_st:1;
+        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_st:1;
+        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_st:1;
+        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_st:1;
+        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_st:1;
+        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_st:1;
+        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_st:1;
+        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_st:1;
+        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_st:1;
+        /** fault0_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_st:1;
+        /** fault1_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_st:1;
+        /** fault2_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_st:1;
+        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f0 ends.
+         */
+        uint32_t fault0_clr_int_st:1;
+        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f1 ends.
+         */
+        uint32_t fault1_clr_int_st:1;
+        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f2 ends.
+         */
+        uint32_t fault2_clr_int_st:1;
+        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_st:1;
+        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_st:1;
+        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_st:1;
+        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_st:1;
+        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_st:1;
+        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_st:1;
+        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM0.
+         */
+        uint32_t tz0_cbc_int_st:1;
+        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM1.
+         */
+        uint32_t tz1_cbc_int_st:1;
+        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM2.
+         */
+        uint32_t tz2_cbc_int_st:1;
+        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_st:1;
+        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_st:1;
+        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_st:1;
+        /** cap0_int_st : RO; bitpos: [27]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_st:1;
+        /** cap1_int_st : RO; bitpos: [28]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_st:1;
+        /** cap2_int_st : RO; bitpos: [29]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_st:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_clr:1;
+        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_clr:1;
+        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_clr:1;
+        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_clr:1;
+        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_clr:1;
+        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_clr:1;
+        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_clr:1;
+        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_clr:1;
+        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_clr:1;
+        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_clr:1;
+        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_clr:1;
+        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_clr:1;
+        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f0 ends.
+         */
+        uint32_t fault0_clr_int_clr:1;
+        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f1 ends.
+         */
+        uint32_t fault1_clr_int_clr:1;
+        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f2 ends.
+         */
+        uint32_t fault2_clr_int_clr:1;
+        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_clr:1;
+        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_clr:1;
+        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_clr:1;
+        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_clr:1;
+        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_clr:1;
+        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_clr:1;
+        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_cbc_int_clr:1;
+        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_cbc_int_clr:1;
+        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_cbc_int_clr:1;
+        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_clr:1;
+        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_clr:1;
+        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_clr:1;
+        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_clr:1;
+        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_clr:1;
+        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_clr:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_clr_reg_t;
+
+
+/** Group: MCPWM event enable register */
+/** Type of evt_en register
+ *  MCPWM event enable register
+ */
+typedef union {
+    struct {
+        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit high to enable timer0 stop event generate
+         */
+        uint32_t evt_timer0_stop_en:1;
+        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
+         *  set this bit high to enable timer1 stop event generate
+         */
+        uint32_t evt_timer1_stop_en:1;
+        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
+         *  set this bit high to enable timer2 stop event generate
+         */
+        uint32_t evt_timer2_stop_en:1;
+        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
+         *  set this bit high to enable timer0 equal zero event generate
+         */
+        uint32_t evt_timer0_tez_en:1;
+        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
+         *  set this bit high to enable timer1 equal zero event generate
+         */
+        uint32_t evt_timer1_tez_en:1;
+        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
+         *  set this bit high to enable timer2 equal zero event generate
+         */
+        uint32_t evt_timer2_tez_en:1;
+        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
+         *  set this bit high to enable timer0 equal period event generate
+         */
+        uint32_t evt_timer0_tep_en:1;
+        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
+         *  set this bit high to enable timer1 equal period event generate
+         */
+        uint32_t evt_timer1_tep_en:1;
+        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
+         *  set this bit high to enable timer2 equal period event generate
+         */
+        uint32_t evt_timer2_tep_en:1;
+        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
+         *  set this bit high to enable PWM generator0 timer equal a event generate
+         */
+        uint32_t evt_op0_tea_en:1;
+        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
+         *  set this bit high to enable PWM generator1 timer equal a event generate
+         */
+        uint32_t evt_op1_tea_en:1;
+        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
+         *  set this bit high to enable PWM generator2 timer equal a event generate
+         */
+        uint32_t evt_op2_tea_en:1;
+        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
+         *  set this bit high to enable PWM generator0 timer equal b event generate
+         */
+        uint32_t evt_op0_teb_en:1;
+        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
+         *  set this bit high to enable PWM generator1 timer equal b event generate
+         */
+        uint32_t evt_op1_teb_en:1;
+        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
+         *  set this bit high to enable PWM generator2 timer equal b event generate
+         */
+        uint32_t evt_op2_teb_en:1;
+        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
+         *  set this bit high to enable fault0 event generate
+         */
+        uint32_t evt_f0_en:1;
+        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
+         *  set this bit high to enable fault1 event generate
+         */
+        uint32_t evt_f1_en:1;
+        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
+         *  set this bit high to enable fault2 event generate
+         */
+        uint32_t evt_f2_en:1;
+        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
+         *  set this bit high to enable fault0 clear event generate
+         */
+        uint32_t evt_f0_clr_en:1;
+        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
+         *  set this bit high to enable fault1 clear event generate
+         */
+        uint32_t evt_f1_clr_en:1;
+        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
+         *  set this bit high to enable fault2 clear event generate
+         */
+        uint32_t evt_f2_clr_en:1;
+        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
+         *  set this bit high to enable cycle by cycle trip0 event generate
+         */
+        uint32_t evt_tz0_cbc_en:1;
+        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
+         *  set this bit high to enable cycle by cycle trip1 event generate
+         */
+        uint32_t evt_tz1_cbc_en:1;
+        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
+         *  set this bit high to enable cycle by cycle trip2 event generate
+         */
+        uint32_t evt_tz2_cbc_en:1;
+        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
+         *  set this bit high to enable one shot trip0 event generate
+         */
+        uint32_t evt_tz0_ost_en:1;
+        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
+         *  set this bit high to enable one shot trip1 event generate
+         */
+        uint32_t evt_tz1_ost_en:1;
+        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
+         *  set this bit high to enable one shot trip2 event generate
+         */
+        uint32_t evt_tz2_ost_en:1;
+        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
+         *  set this bit high to enable capture0 event generate
+         */
+        uint32_t evt_cap0_en:1;
+        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
+         *  set this bit high to enable capture1 event generate
+         */
+        uint32_t evt_cap1_en:1;
+        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
+         *  set this bit high to enable capture2 event generate
+         */
+        uint32_t evt_cap2_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_evt_en_reg_t;
+
+
+/** Group: MCPWM task enable register */
+/** Type of task_en register
+ *  MCPWM task enable register
+ */
+typedef union {
+    struct {
+        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit high to enable PWM generator0 timer stamp A's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr0_a_up_en:1;
+        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
+         *  set this bit high to enable PWM generator1 timer stamp A's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr1_a_up_en:1;
+        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
+         *  set this bit high to enable PWM generator2 timer stamp A's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr2_a_up_en:1;
+        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
+         *  set this bit high to enable PWM generator0 timer stamp B's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr0_b_up_en:1;
+        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
+         *  set this bit high to enable PWM generator1 timer stamp B's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr1_b_up_en:1;
+        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
+         *  set this bit high to enable PWM generator2 timer stamp B's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr2_b_up_en:1;
+        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
+         *  set this bit high to enable all PWM generate stop task receive
+         */
+        uint32_t task_gen_stop_en:1;
+        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
+         *  set this bit high to enable timer0 sync task receive
+         */
+        uint32_t task_timer0_sync_en:1;
+        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
+         *  set this bit high to enable timer1 sync task receive
+         */
+        uint32_t task_timer1_sync_en:1;
+        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
+         *  set this bit high to enable timer2 sync task receive
+         */
+        uint32_t task_timer2_sync_en:1;
+        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
+         *  set this bit high to enable timer0 period update task receive
+         */
+        uint32_t task_timer0_period_up_en:1;
+        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
+         *  set this bit high to enable timer1 period update task receive
+         */
+        uint32_t task_timer1_period_up_en:1;
+        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
+         *  set this bit high to enable timer2 period update task receive
+         */
+        uint32_t task_timer2_period_up_en:1;
+        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
+         *  set this bit high to enable one shot trip0 task receive
+         */
+        uint32_t task_tz0_ost_en:1;
+        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
+         *  set this bit high to enable one shot trip1 task receive
+         */
+        uint32_t task_tz1_ost_en:1;
+        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
+         *  set this bit high to enable one shot trip2 task receive
+         */
+        uint32_t task_tz2_ost_en:1;
+        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
+         *  set this bit high to enable one shot trip0 clear task receive
+         */
+        uint32_t task_clr0_ost_en:1;
+        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
+         *  set this bit high to enable one shot trip1 clear task receive
+         */
+        uint32_t task_clr1_ost_en:1;
+        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
+         *  set this bit high to enable one shot trip2 clear task receive
+         */
+        uint32_t task_clr2_ost_en:1;
+        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
+         *  set this bit high to enable capture0 task receive
+         */
+        uint32_t task_cap0_en:1;
+        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
+         *  set this bit high to enable capture1 task receive
+         */
+        uint32_t task_cap1_en:1;
+        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
+         *  set this bit high to enable capture2 task receive
+         */
+        uint32_t task_cap2_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} mcpwm_task_en_reg_t;
+
+
+/** Group: MCPWM APB configuration register */
+/** Type of clk register
+ *  MCPWM APB configuration register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mcpwm_clk_reg_t;
+
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35656256;
+         *  Version of this register file
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mcpwm_version_reg_t;
+
+typedef struct {
+    mcpwm_timer_cfg0_reg_t timer_cfg0;
+    mcpwm_timer_cfg1_reg_t timer_cfg1;
+    mcpwm_timer_sync_reg_t timer_sync;
+    mcpwm_timer_status_reg_t timer_status;
+} mcpwm_timer_regs_t;
+
+typedef struct {
+    mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
+    mcpwm_gen_tstmp_reg_t timestamp[2];
+    mcpwm_gen_cfg0_reg_t gen_cfg0;
+    mcpwm_gen_force_reg_t gen_force;
+    mcpwm_gen_reg_t generator[2];
+    mcpwm_dt_cfg_reg_t dt_cfg;
+    mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
+    mcpwm_dt_red_cfg_reg_t dt_red_cfg;
+    mcpwm_carrier_cfg_reg_t carrier_cfg;
+    mcpwm_fh_cfg0_reg_t fh_cfg0;
+    mcpwm_fh_cfg1_reg_t fh_cfg1;
+    mcpwm_fh_status_reg_t fh_status;
+} mcpwm_operator_reg_t;
+
+typedef struct mcpwm_dev_t {
+    volatile mcpwm_clk_cfg_reg_t clk_cfg;
+    volatile mcpwm_timer_regs_t timer[3];
+    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
+    volatile mcpwm_operator_timersel_reg_t operator_timersel;
+    volatile mcpwm_operator_reg_t operators[3];
+    volatile mcpwm_fault_detect_reg_t fault_detect;
+    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
+    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
+    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
+    volatile mcpwm_cap_chn_reg_t cap_chn[3];
+    volatile mcpwm_cap_status_reg_t cap_status;
+    volatile mcpwm_update_cfg_reg_t update_cfg;
+    volatile mcpwm_int_ena_reg_t int_ena;
+    volatile mcpwm_int_raw_reg_t int_raw;
+    volatile mcpwm_int_st_reg_t int_st;
+    volatile mcpwm_int_clr_reg_t int_clr;
+    volatile mcpwm_evt_en_reg_t evt_en;
+    volatile mcpwm_task_en_reg_t task_en;
+    volatile mcpwm_clk_reg_t clk;
+    volatile mcpwm_version_reg_t version;
+} mcpwm_dev_t;
+
+extern mcpwm_dev_t MCPWM0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mcpwm_dev_t) == 0x130, "Invalid size of mcpwm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/mem_monitor_reg.h b/components/soc/esp32c6/register/soc/mem_monitor_reg.h
new file mode 100644
index 00000000000..b75a52af212
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/mem_monitor_reg.h
@@ -0,0 +1,184 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MEM_MONITOR_LOG_SETTING_REG register
+ *  log config register
+ */
+#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
+/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
+ *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.
+ */
+#define MEM_MONITOR_LOG_ENA    0x00000007U
+#define MEM_MONITOR_LOG_ENA_M  (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
+#define MEM_MONITOR_LOG_ENA_V  0x00000007U
+#define MEM_MONITOR_LOG_ENA_S  0
+/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
+ *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
+ *  HALFWORD monitor, 4'b1000: BYTE monitor.
+ */
+#define MEM_MONITOR_LOG_MODE    0x0000000FU
+#define MEM_MONITOR_LOG_MODE_M  (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
+#define MEM_MONITOR_LOG_MODE_V  0x0000000FU
+#define MEM_MONITOR_LOG_MODE_S  3
+/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
+ *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
+ */
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(7))
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
+
+/** MEM_MONITOR_LOG_CHECK_DATA_REG register
+ *  check data register
+ */
+#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
+/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The special check data, when write this special data, it will trigger logging.
+ */
+#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_CHECK_DATA_M  (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
+#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_CHECK_DATA_S  0
+
+/** MEM_MONITOR_LOG_DATA_MASK_REG register
+ *  check data mask register
+ */
+#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
+/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
+ *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
+ *  mask second byte, and so on.
+ */
+#define MEM_MONITOR_LOG_DATA_MASK    0x0000000FU
+#define MEM_MONITOR_LOG_DATA_MASK_M  (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
+#define MEM_MONITOR_LOG_DATA_MASK_V  0x0000000FU
+#define MEM_MONITOR_LOG_DATA_MASK_S  0
+
+/** MEM_MONITOR_LOG_MIN_REG register
+ *  log boundary register
+ */
+#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
+/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  the min address of log range
+ */
+#define MEM_MONITOR_LOG_MIN    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MIN_M  (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
+#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MIN_S  0
+
+/** MEM_MONITOR_LOG_MAX_REG register
+ *  log boundary register
+ */
+#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
+/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  the max address of log range
+ */
+#define MEM_MONITOR_LOG_MAX    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MAX_M  (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
+#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MAX_S  0
+
+/** MEM_MONITOR_LOG_MEM_START_REG register
+ *  log message store range register
+ */
+#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
+/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
+ *  the start address of writing logging message
+ */
+#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_START_M  (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
+#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_START_S  0
+
+/** MEM_MONITOR_LOG_MEM_END_REG register
+ *  log message store range register
+ */
+#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
+/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
+ *  the end address of writing logging message
+ */
+#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_END_M  (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
+#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_END_S  0
+
+/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
+ *  current writing address.
+ */
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
+/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  means next writing address
+ */
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
+
+/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
+ *  writing address update
+ */
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
+/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
+ *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
+ */
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
+
+/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
+ *  full flag status register
+ */
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
+/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
+ *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
+ */
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
+/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
+ *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
+ */
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
+
+/** MEM_MONITOR_CLOCK_GATE_REG register
+ *  clock gate force on register
+ */
+#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
+/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to force on the clk of mem_monitor register
+ */
+#define MEM_MONITOR_CLK_EN    (BIT(0))
+#define MEM_MONITOR_CLK_EN_M  (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
+#define MEM_MONITOR_CLK_EN_V  0x00000001U
+#define MEM_MONITOR_CLK_EN_S  0
+
+/** MEM_MONITOR_DATE_REG register
+ *  version register
+ */
+#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
+/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096;
+ *  version register
+ */
+#define MEM_MONITOR_DATE    0x0FFFFFFFU
+#define MEM_MONITOR_DATE_M  (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
+#define MEM_MONITOR_DATE_V  0x0FFFFFFFU
+#define MEM_MONITOR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/mem_monitor_struct.h b/components/soc/esp32c6/register/soc/mem_monitor_struct.h
new file mode 100644
index 00000000000..862959b9494
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/mem_monitor_struct.h
@@ -0,0 +1,220 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration registers */
+/** Type of log_setting register
+ *  log config register
+ */
+typedef union {
+    struct {
+        /** log_ena : R/W; bitpos: [2:0]; default: 0;
+         *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.
+         */
+        uint32_t log_ena:3;
+        /** log_mode : R/W; bitpos: [6:3]; default: 0;
+         *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
+         *  HALFWORD monitor, 4'b1000: BYTE monitor.
+         */
+        uint32_t log_mode:4;
+        /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
+         *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
+         */
+        uint32_t log_mem_loop_enable:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mem_monitor_log_setting_reg_t;
+
+/** Type of log_check_data register
+ *  check data register
+ */
+typedef union {
+    struct {
+        /** log_check_data : R/W; bitpos: [31:0]; default: 0;
+         *  The special check data, when write this special data, it will trigger logging.
+         */
+        uint32_t log_check_data:32;
+    };
+    uint32_t val;
+} mem_monitor_log_check_data_reg_t;
+
+/** Type of log_data_mask register
+ *  check data mask register
+ */
+typedef union {
+    struct {
+        /** log_data_mask : R/W; bitpos: [3:0]; default: 0;
+         *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
+         *  mask second byte, and so on.
+         */
+        uint32_t log_data_mask:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} mem_monitor_log_data_mask_reg_t;
+
+/** Type of log_min register
+ *  log boundary register
+ */
+typedef union {
+    struct {
+        /** log_min : R/W; bitpos: [31:0]; default: 0;
+         *  the min address of log range
+         */
+        uint32_t log_min:32;
+    };
+    uint32_t val;
+} mem_monitor_log_min_reg_t;
+
+/** Type of log_max register
+ *  log boundary register
+ */
+typedef union {
+    struct {
+        /** log_max : R/W; bitpos: [31:0]; default: 0;
+         *  the max address of log range
+         */
+        uint32_t log_max:32;
+    };
+    uint32_t val;
+} mem_monitor_log_max_reg_t;
+
+/** Type of log_mem_start register
+ *  log message store range register
+ */
+typedef union {
+    struct {
+        /** log_mem_start : R/W; bitpos: [31:0]; default: 0;
+         *  the start address of writing logging message
+         */
+        uint32_t log_mem_start:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_start_reg_t;
+
+/** Type of log_mem_end register
+ *  log message store range register
+ */
+typedef union {
+    struct {
+        /** log_mem_end : R/W; bitpos: [31:0]; default: 0;
+         *  the end address of writing logging message
+         */
+        uint32_t log_mem_end:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_end_reg_t;
+
+/** Type of log_mem_current_addr register
+ *  current writing address.
+ */
+typedef union {
+    struct {
+        /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  means next writing address
+         */
+        uint32_t log_mem_current_addr:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_current_addr_reg_t;
+
+/** Type of log_mem_addr_update register
+ *  writing address update
+ */
+typedef union {
+    struct {
+        /** log_mem_addr_update : WT; bitpos: [0]; default: 0;
+         *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
+         *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
+         */
+        uint32_t log_mem_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_addr_update_reg_t;
+
+/** Type of log_mem_full_flag register
+ *  full flag status register
+ */
+typedef union {
+    struct {
+        /** log_mem_full_flag : RO; bitpos: [0]; default: 0;
+         *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
+         */
+        uint32_t log_mem_full_flag:1;
+        /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
+         *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
+         */
+        uint32_t clr_log_mem_full_flag:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_full_flag_reg_t;
+
+
+/** Group: clk register */
+/** Type of clock_gate register
+ *  clock gate force on register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to force on the clk of mem_monitor register
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mem_monitor_clock_gate_reg_t;
+
+
+/** Group: version register */
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35660096;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mem_monitor_date_reg_t;
+
+
+typedef struct mem_monitor_dev_t {
+    volatile mem_monitor_log_setting_reg_t log_setting;
+    volatile mem_monitor_log_check_data_reg_t log_check_data;
+    volatile mem_monitor_log_data_mask_reg_t log_data_mask;
+    volatile mem_monitor_log_min_reg_t log_min;
+    volatile mem_monitor_log_max_reg_t log_max;
+    volatile mem_monitor_log_mem_start_reg_t log_mem_start;
+    volatile mem_monitor_log_mem_end_reg_t log_mem_end;
+    volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
+    volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
+    volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
+    volatile mem_monitor_clock_gate_reg_t clock_gate;
+    uint32_t reserved_02c[244];
+    volatile mem_monitor_date_reg_t date;
+} mem_monitor_dev_t;
+
+extern mem_monitor_dev_t MEM_MONITOR;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/otp_debug_reg.h b/components/soc/esp32c6/register/soc/otp_debug_reg.h
similarity index 91%
rename from components/soc/esp32c6/include/soc/otp_debug_reg.h
rename to components/soc/esp32c6/register/soc/otp_debug_reg.h
index 6d0e84c69f1..49d1754d4f5 100644
--- a/components/soc/esp32c6/include/soc/otp_debug_reg.h
+++ b/components/soc/esp32c6/register/soc/otp_debug_reg.h
@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** OTP_DEBUG_WR_DIS_REG register
- *  Otp debuger block0 data register1.
+ *  Otp debugger block0 data register1.
  */
 #define OTP_DEBUG_WR_DIS_REG (DR_REG_OTP_DEBUG_BASE + 0x0)
 /** OTP_DEBUG_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
@@ -24,7 +24,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_WR_DIS_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W1_REG register
- *  Otp debuger block0 data register2.
+ *  Otp debugger block0 data register2.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x4)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
@@ -36,7 +36,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W1_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W2_REG register
- *  Otp debuger block0 data register3.
+ *  Otp debugger block0 data register3.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x8)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
@@ -48,7 +48,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W2_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W3_REG register
- *  Otp debuger block0 data register4.
+ *  Otp debugger block0 data register4.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xc)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
@@ -60,7 +60,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W3_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W4_REG register
- *  Otp debuger block0 data register5.
+ *  Otp debugger block0 data register5.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x10)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
@@ -72,7 +72,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W4_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP1_W5_REG register
- *  Otp debuger block0 data register6.
+ *  Otp debugger block0 data register6.
  */
 #define OTP_DEBUG_BLK0_BACKUP1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x14)
 /** OTP_DEBUG_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
@@ -84,7 +84,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP1_W5_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W1_REG register
- *  Otp debuger block0 data register7.
+ *  Otp debugger block0 data register7.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x18)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
@@ -96,7 +96,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W1_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W2_REG register
- *  Otp debuger block0 data register8.
+ *  Otp debugger block0 data register8.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1c)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
@@ -108,7 +108,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W2_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W3_REG register
- *  Otp debuger block0 data register9.
+ *  Otp debugger block0 data register9.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x20)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
@@ -120,7 +120,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W3_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W4_REG register
- *  Otp debuger block0 data register10.
+ *  Otp debugger block0 data register10.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x24)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
@@ -132,7 +132,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W4_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP2_W5_REG register
- *  Otp debuger block0 data register11.
+ *  Otp debugger block0 data register11.
  */
 #define OTP_DEBUG_BLK0_BACKUP2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x28)
 /** OTP_DEBUG_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
@@ -144,7 +144,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP2_W5_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W1_REG register
- *  Otp debuger block0 data register12.
+ *  Otp debugger block0 data register12.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x2c)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
@@ -156,7 +156,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W1_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W2_REG register
- *  Otp debuger block0 data register13.
+ *  Otp debugger block0 data register13.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x30)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
@@ -168,7 +168,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W2_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W3_REG register
- *  Otp debuger block0 data register14.
+ *  Otp debugger block0 data register14.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x34)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
@@ -180,7 +180,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W3_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W4_REG register
- *  Otp debuger block0 data register15.
+ *  Otp debugger block0 data register15.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x38)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
@@ -192,7 +192,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W4_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP3_W5_REG register
- *  Otp debuger block0 data register16.
+ *  Otp debugger block0 data register16.
  */
 #define OTP_DEBUG_BLK0_BACKUP3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x3c)
 /** OTP_DEBUG_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
@@ -204,7 +204,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP3_W5_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W1_REG register
- *  Otp debuger block0 data register17.
+ *  Otp debugger block0 data register17.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x40)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
@@ -216,7 +216,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W1_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W2_REG register
- *  Otp debuger block0 data register18.
+ *  Otp debugger block0 data register18.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x44)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
@@ -228,7 +228,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W2_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W3_REG register
- *  Otp debuger block0 data register19.
+ *  Otp debugger block0 data register19.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x48)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
@@ -240,7 +240,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W3_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W4_REG register
- *  Otp debuger block0 data register20.
+ *  Otp debugger block0 data register20.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x4c)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
@@ -252,7 +252,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W4_S  0
 
 /** OTP_DEBUG_BLK0_BACKUP4_W5_REG register
- *  Otp debuger block0 data register21.
+ *  Otp debugger block0 data register21.
  */
 #define OTP_DEBUG_BLK0_BACKUP4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x50)
 /** OTP_DEBUG_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
@@ -264,7 +264,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK0_BACKUP4_W5_S  0
 
 /** OTP_DEBUG_BLK1_W1_REG register
- *  Otp debuger block1 data register1.
+ *  Otp debugger block1 data register1.
  */
 #define OTP_DEBUG_BLK1_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x54)
 /** OTP_DEBUG_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
@@ -276,7 +276,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W1_S  0
 
 /** OTP_DEBUG_BLK1_W2_REG register
- *  Otp debuger block1 data register2.
+ *  Otp debugger block1 data register2.
  */
 #define OTP_DEBUG_BLK1_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x58)
 /** OTP_DEBUG_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
@@ -288,7 +288,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W2_S  0
 
 /** OTP_DEBUG_BLK1_W3_REG register
- *  Otp debuger block1 data register3.
+ *  Otp debugger block1 data register3.
  */
 #define OTP_DEBUG_BLK1_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x5c)
 /** OTP_DEBUG_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
@@ -300,7 +300,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W3_S  0
 
 /** OTP_DEBUG_BLK1_W4_REG register
- *  Otp debuger block1 data register4.
+ *  Otp debugger block1 data register4.
  */
 #define OTP_DEBUG_BLK1_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x60)
 /** OTP_DEBUG_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
@@ -312,7 +312,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W4_S  0
 
 /** OTP_DEBUG_BLK1_W5_REG register
- *  Otp debuger block1 data register5.
+ *  Otp debugger block1 data register5.
  */
 #define OTP_DEBUG_BLK1_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x64)
 /** OTP_DEBUG_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
@@ -324,7 +324,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W5_S  0
 
 /** OTP_DEBUG_BLK1_W6_REG register
- *  Otp debuger block1 data register6.
+ *  Otp debugger block1 data register6.
  */
 #define OTP_DEBUG_BLK1_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x68)
 /** OTP_DEBUG_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
@@ -336,7 +336,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W6_S  0
 
 /** OTP_DEBUG_BLK1_W7_REG register
- *  Otp debuger block1 data register7.
+ *  Otp debugger block1 data register7.
  */
 #define OTP_DEBUG_BLK1_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x6c)
 /** OTP_DEBUG_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
@@ -348,7 +348,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W7_S  0
 
 /** OTP_DEBUG_BLK1_W8_REG register
- *  Otp debuger block1 data register8.
+ *  Otp debugger block1 data register8.
  */
 #define OTP_DEBUG_BLK1_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x70)
 /** OTP_DEBUG_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
@@ -360,7 +360,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W8_S  0
 
 /** OTP_DEBUG_BLK1_W9_REG register
- *  Otp debuger block1 data register9.
+ *  Otp debugger block1 data register9.
  */
 #define OTP_DEBUG_BLK1_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x74)
 /** OTP_DEBUG_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
@@ -372,7 +372,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK1_W9_S  0
 
 /** OTP_DEBUG_BLK2_W1_REG register
- *  Otp debuger block2 data register1.
+ *  Otp debugger block2 data register1.
  */
 #define OTP_DEBUG_BLK2_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x78)
 /** OTP_DEBUG_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
@@ -384,7 +384,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W1_S  0
 
 /** OTP_DEBUG_BLK2_W2_REG register
- *  Otp debuger block2 data register2.
+ *  Otp debugger block2 data register2.
  */
 #define OTP_DEBUG_BLK2_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x7c)
 /** OTP_DEBUG_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
@@ -396,7 +396,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W2_S  0
 
 /** OTP_DEBUG_BLK2_W3_REG register
- *  Otp debuger block2 data register3.
+ *  Otp debugger block2 data register3.
  */
 #define OTP_DEBUG_BLK2_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x80)
 /** OTP_DEBUG_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
@@ -408,7 +408,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W3_S  0
 
 /** OTP_DEBUG_BLK2_W4_REG register
- *  Otp debuger block2 data register4.
+ *  Otp debugger block2 data register4.
  */
 #define OTP_DEBUG_BLK2_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x84)
 /** OTP_DEBUG_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
@@ -420,7 +420,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W4_S  0
 
 /** OTP_DEBUG_BLK2_W5_REG register
- *  Otp debuger block2 data register5.
+ *  Otp debugger block2 data register5.
  */
 #define OTP_DEBUG_BLK2_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x88)
 /** OTP_DEBUG_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
@@ -432,7 +432,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W5_S  0
 
 /** OTP_DEBUG_BLK2_W6_REG register
- *  Otp debuger block2 data register6.
+ *  Otp debugger block2 data register6.
  */
 #define OTP_DEBUG_BLK2_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x8c)
 /** OTP_DEBUG_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
@@ -444,7 +444,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W6_S  0
 
 /** OTP_DEBUG_BLK2_W7_REG register
- *  Otp debuger block2 data register7.
+ *  Otp debugger block2 data register7.
  */
 #define OTP_DEBUG_BLK2_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x90)
 /** OTP_DEBUG_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
@@ -456,7 +456,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W7_S  0
 
 /** OTP_DEBUG_BLK2_W8_REG register
- *  Otp debuger block2 data register8.
+ *  Otp debugger block2 data register8.
  */
 #define OTP_DEBUG_BLK2_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x94)
 /** OTP_DEBUG_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
@@ -468,7 +468,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W8_S  0
 
 /** OTP_DEBUG_BLK2_W9_REG register
- *  Otp debuger block2 data register9.
+ *  Otp debugger block2 data register9.
  */
 #define OTP_DEBUG_BLK2_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x98)
 /** OTP_DEBUG_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
@@ -480,7 +480,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W9_S  0
 
 /** OTP_DEBUG_BLK2_W10_REG register
- *  Otp debuger block2 data register10.
+ *  Otp debugger block2 data register10.
  */
 #define OTP_DEBUG_BLK2_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x9c)
 /** OTP_DEBUG_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
@@ -492,7 +492,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W10_S  0
 
 /** OTP_DEBUG_BLK2_W11_REG register
- *  Otp debuger block2 data register11.
+ *  Otp debugger block2 data register11.
  */
 #define OTP_DEBUG_BLK2_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xa0)
 /** OTP_DEBUG_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
@@ -504,7 +504,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK2_W11_S  0
 
 /** OTP_DEBUG_BLK3_W1_REG register
- *  Otp debuger block3 data register1.
+ *  Otp debugger block3 data register1.
  */
 #define OTP_DEBUG_BLK3_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xa4)
 /** OTP_DEBUG_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
@@ -516,7 +516,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W1_S  0
 
 /** OTP_DEBUG_BLK3_W2_REG register
- *  Otp debuger block3 data register2.
+ *  Otp debugger block3 data register2.
  */
 #define OTP_DEBUG_BLK3_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xa8)
 /** OTP_DEBUG_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
@@ -528,7 +528,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W2_S  0
 
 /** OTP_DEBUG_BLK3_W3_REG register
- *  Otp debuger block3 data register3.
+ *  Otp debugger block3 data register3.
  */
 #define OTP_DEBUG_BLK3_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xac)
 /** OTP_DEBUG_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
@@ -540,7 +540,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W3_S  0
 
 /** OTP_DEBUG_BLK3_W4_REG register
- *  Otp debuger block3 data register4.
+ *  Otp debugger block3 data register4.
  */
 #define OTP_DEBUG_BLK3_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xb0)
 /** OTP_DEBUG_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
@@ -552,7 +552,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W4_S  0
 
 /** OTP_DEBUG_BLK3_W5_REG register
- *  Otp debuger block3 data register5.
+ *  Otp debugger block3 data register5.
  */
 #define OTP_DEBUG_BLK3_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xb4)
 /** OTP_DEBUG_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
@@ -564,7 +564,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W5_S  0
 
 /** OTP_DEBUG_BLK3_W6_REG register
- *  Otp debuger block3 data register6.
+ *  Otp debugger block3 data register6.
  */
 #define OTP_DEBUG_BLK3_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xb8)
 /** OTP_DEBUG_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
@@ -576,7 +576,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W6_S  0
 
 /** OTP_DEBUG_BLK3_W7_REG register
- *  Otp debuger block3 data register7.
+ *  Otp debugger block3 data register7.
  */
 #define OTP_DEBUG_BLK3_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xbc)
 /** OTP_DEBUG_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
@@ -588,7 +588,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W7_S  0
 
 /** OTP_DEBUG_BLK3_W8_REG register
- *  Otp debuger block3 data register8.
+ *  Otp debugger block3 data register8.
  */
 #define OTP_DEBUG_BLK3_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xc0)
 /** OTP_DEBUG_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
@@ -600,7 +600,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W8_S  0
 
 /** OTP_DEBUG_BLK3_W9_REG register
- *  Otp debuger block3 data register9.
+ *  Otp debugger block3 data register9.
  */
 #define OTP_DEBUG_BLK3_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xc4)
 /** OTP_DEBUG_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
@@ -612,7 +612,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W9_S  0
 
 /** OTP_DEBUG_BLK3_W10_REG register
- *  Otp debuger block3 data register10.
+ *  Otp debugger block3 data register10.
  */
 #define OTP_DEBUG_BLK3_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xc8)
 /** OTP_DEBUG_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
@@ -624,7 +624,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W10_S  0
 
 /** OTP_DEBUG_BLK3_W11_REG register
- *  Otp debuger block3 data register11.
+ *  Otp debugger block3 data register11.
  */
 #define OTP_DEBUG_BLK3_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xcc)
 /** OTP_DEBUG_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
@@ -636,7 +636,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK3_W11_S  0
 
 /** OTP_DEBUG_BLK4_W1_REG register
- *  Otp debuger block4 data register1.
+ *  Otp debugger block4 data register1.
  */
 #define OTP_DEBUG_BLK4_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xd0)
 /** OTP_DEBUG_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
@@ -648,7 +648,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W1_S  0
 
 /** OTP_DEBUG_BLK4_W2_REG register
- *  Otp debuger block4 data register2.
+ *  Otp debugger block4 data register2.
  */
 #define OTP_DEBUG_BLK4_W2_REG (DR_REG_OTP_DEBUG_BASE + 0xd4)
 /** OTP_DEBUG_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
@@ -660,7 +660,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W2_S  0
 
 /** OTP_DEBUG_BLK4_W3_REG register
- *  Otp debuger block4 data register3.
+ *  Otp debugger block4 data register3.
  */
 #define OTP_DEBUG_BLK4_W3_REG (DR_REG_OTP_DEBUG_BASE + 0xd8)
 /** OTP_DEBUG_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
@@ -672,7 +672,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W3_S  0
 
 /** OTP_DEBUG_BLK4_W4_REG register
- *  Otp debuger block4 data register4.
+ *  Otp debugger block4 data register4.
  */
 #define OTP_DEBUG_BLK4_W4_REG (DR_REG_OTP_DEBUG_BASE + 0xdc)
 /** OTP_DEBUG_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
@@ -684,7 +684,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W4_S  0
 
 /** OTP_DEBUG_BLK4_W5_REG register
- *  Otp debuger block4 data register5.
+ *  Otp debugger block4 data register5.
  */
 #define OTP_DEBUG_BLK4_W5_REG (DR_REG_OTP_DEBUG_BASE + 0xe0)
 /** OTP_DEBUG_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
@@ -696,7 +696,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W5_S  0
 
 /** OTP_DEBUG_BLK4_W6_REG register
- *  Otp debuger block4 data register6.
+ *  Otp debugger block4 data register6.
  */
 #define OTP_DEBUG_BLK4_W6_REG (DR_REG_OTP_DEBUG_BASE + 0xe4)
 /** OTP_DEBUG_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
@@ -708,7 +708,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W6_S  0
 
 /** OTP_DEBUG_BLK4_W7_REG register
- *  Otp debuger block4 data register7.
+ *  Otp debugger block4 data register7.
  */
 #define OTP_DEBUG_BLK4_W7_REG (DR_REG_OTP_DEBUG_BASE + 0xe8)
 /** OTP_DEBUG_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
@@ -720,7 +720,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W7_S  0
 
 /** OTP_DEBUG_BLK4_W8_REG register
- *  Otp debuger block4 data register8.
+ *  Otp debugger block4 data register8.
  */
 #define OTP_DEBUG_BLK4_W8_REG (DR_REG_OTP_DEBUG_BASE + 0xec)
 /** OTP_DEBUG_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
@@ -732,7 +732,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W8_S  0
 
 /** OTP_DEBUG_BLK4_W9_REG register
- *  Otp debuger block4 data register9.
+ *  Otp debugger block4 data register9.
  */
 #define OTP_DEBUG_BLK4_W9_REG (DR_REG_OTP_DEBUG_BASE + 0xf0)
 /** OTP_DEBUG_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
@@ -744,7 +744,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W9_S  0
 
 /** OTP_DEBUG_BLK4_W10_REG register
- *  Otp debuger block4 data registe10.
+ *  Otp debugger block4 data registe10.
  */
 #define OTP_DEBUG_BLK4_W10_REG (DR_REG_OTP_DEBUG_BASE + 0xf4)
 /** OTP_DEBUG_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
@@ -756,7 +756,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W10_S  0
 
 /** OTP_DEBUG_BLK4_W11_REG register
- *  Otp debuger block4 data register11.
+ *  Otp debugger block4 data register11.
  */
 #define OTP_DEBUG_BLK4_W11_REG (DR_REG_OTP_DEBUG_BASE + 0xf8)
 /** OTP_DEBUG_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
@@ -768,7 +768,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK4_W11_S  0
 
 /** OTP_DEBUG_BLK5_W1_REG register
- *  Otp debuger block5 data register1.
+ *  Otp debugger block5 data register1.
  */
 #define OTP_DEBUG_BLK5_W1_REG (DR_REG_OTP_DEBUG_BASE + 0xfc)
 /** OTP_DEBUG_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
@@ -780,7 +780,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W1_S  0
 
 /** OTP_DEBUG_BLK5_W2_REG register
- *  Otp debuger block5 data register2.
+ *  Otp debugger block5 data register2.
  */
 #define OTP_DEBUG_BLK5_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x100)
 /** OTP_DEBUG_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
@@ -792,7 +792,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W2_S  0
 
 /** OTP_DEBUG_BLK5_W3_REG register
- *  Otp debuger block5 data register3.
+ *  Otp debugger block5 data register3.
  */
 #define OTP_DEBUG_BLK5_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x104)
 /** OTP_DEBUG_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
@@ -804,7 +804,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W3_S  0
 
 /** OTP_DEBUG_BLK5_W4_REG register
- *  Otp debuger block5 data register4.
+ *  Otp debugger block5 data register4.
  */
 #define OTP_DEBUG_BLK5_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x108)
 /** OTP_DEBUG_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
@@ -816,7 +816,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W4_S  0
 
 /** OTP_DEBUG_BLK5_W5_REG register
- *  Otp debuger block5 data register5.
+ *  Otp debugger block5 data register5.
  */
 #define OTP_DEBUG_BLK5_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x10c)
 /** OTP_DEBUG_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
@@ -828,7 +828,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W5_S  0
 
 /** OTP_DEBUG_BLK5_W6_REG register
- *  Otp debuger block5 data register6.
+ *  Otp debugger block5 data register6.
  */
 #define OTP_DEBUG_BLK5_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x110)
 /** OTP_DEBUG_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
@@ -840,7 +840,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W6_S  0
 
 /** OTP_DEBUG_BLK5_W7_REG register
- *  Otp debuger block5 data register7.
+ *  Otp debugger block5 data register7.
  */
 #define OTP_DEBUG_BLK5_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x114)
 /** OTP_DEBUG_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
@@ -852,7 +852,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W7_S  0
 
 /** OTP_DEBUG_BLK5_W8_REG register
- *  Otp debuger block5 data register8.
+ *  Otp debugger block5 data register8.
  */
 #define OTP_DEBUG_BLK5_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x118)
 /** OTP_DEBUG_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
@@ -864,7 +864,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W8_S  0
 
 /** OTP_DEBUG_BLK5_W9_REG register
- *  Otp debuger block5 data register9.
+ *  Otp debugger block5 data register9.
  */
 #define OTP_DEBUG_BLK5_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x11c)
 /** OTP_DEBUG_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
@@ -876,7 +876,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W9_S  0
 
 /** OTP_DEBUG_BLK5_W10_REG register
- *  Otp debuger block5 data register10.
+ *  Otp debugger block5 data register10.
  */
 #define OTP_DEBUG_BLK5_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x120)
 /** OTP_DEBUG_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
@@ -888,7 +888,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W10_S  0
 
 /** OTP_DEBUG_BLK5_W11_REG register
- *  Otp debuger block5 data register11.
+ *  Otp debugger block5 data register11.
  */
 #define OTP_DEBUG_BLK5_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x124)
 /** OTP_DEBUG_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
@@ -900,7 +900,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK5_W11_S  0
 
 /** OTP_DEBUG_BLK6_W1_REG register
- *  Otp debuger block6 data register1.
+ *  Otp debugger block6 data register1.
  */
 #define OTP_DEBUG_BLK6_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x128)
 /** OTP_DEBUG_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
@@ -912,7 +912,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W1_S  0
 
 /** OTP_DEBUG_BLK6_W2_REG register
- *  Otp debuger block6 data register2.
+ *  Otp debugger block6 data register2.
  */
 #define OTP_DEBUG_BLK6_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x12c)
 /** OTP_DEBUG_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
@@ -924,7 +924,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W2_S  0
 
 /** OTP_DEBUG_BLK6_W3_REG register
- *  Otp debuger block6 data register3.
+ *  Otp debugger block6 data register3.
  */
 #define OTP_DEBUG_BLK6_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x130)
 /** OTP_DEBUG_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
@@ -936,7 +936,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W3_S  0
 
 /** OTP_DEBUG_BLK6_W4_REG register
- *  Otp debuger block6 data register4.
+ *  Otp debugger block6 data register4.
  */
 #define OTP_DEBUG_BLK6_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x134)
 /** OTP_DEBUG_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
@@ -948,7 +948,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W4_S  0
 
 /** OTP_DEBUG_BLK6_W5_REG register
- *  Otp debuger block6 data register5.
+ *  Otp debugger block6 data register5.
  */
 #define OTP_DEBUG_BLK6_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x138)
 /** OTP_DEBUG_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
@@ -960,7 +960,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W5_S  0
 
 /** OTP_DEBUG_BLK6_W6_REG register
- *  Otp debuger block6 data register6.
+ *  Otp debugger block6 data register6.
  */
 #define OTP_DEBUG_BLK6_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x13c)
 /** OTP_DEBUG_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
@@ -972,7 +972,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W6_S  0
 
 /** OTP_DEBUG_BLK6_W7_REG register
- *  Otp debuger block6 data register7.
+ *  Otp debugger block6 data register7.
  */
 #define OTP_DEBUG_BLK6_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x140)
 /** OTP_DEBUG_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
@@ -984,7 +984,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W7_S  0
 
 /** OTP_DEBUG_BLK6_W8_REG register
- *  Otp debuger block6 data register8.
+ *  Otp debugger block6 data register8.
  */
 #define OTP_DEBUG_BLK6_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x144)
 /** OTP_DEBUG_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
@@ -996,7 +996,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W8_S  0
 
 /** OTP_DEBUG_BLK6_W9_REG register
- *  Otp debuger block6 data register9.
+ *  Otp debugger block6 data register9.
  */
 #define OTP_DEBUG_BLK6_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x148)
 /** OTP_DEBUG_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1008,7 +1008,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W9_S  0
 
 /** OTP_DEBUG_BLK6_W10_REG register
- *  Otp debuger block6 data register10.
+ *  Otp debugger block6 data register10.
  */
 #define OTP_DEBUG_BLK6_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x14c)
 /** OTP_DEBUG_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1020,7 +1020,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W10_S  0
 
 /** OTP_DEBUG_BLK6_W11_REG register
- *  Otp debuger block6 data register11.
+ *  Otp debugger block6 data register11.
  */
 #define OTP_DEBUG_BLK6_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x150)
 /** OTP_DEBUG_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1032,7 +1032,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK6_W11_S  0
 
 /** OTP_DEBUG_BLK7_W1_REG register
- *  Otp debuger block7 data register1.
+ *  Otp debugger block7 data register1.
  */
 #define OTP_DEBUG_BLK7_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x154)
 /** OTP_DEBUG_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
@@ -1044,7 +1044,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W1_S  0
 
 /** OTP_DEBUG_BLK7_W2_REG register
- *  Otp debuger block7 data register2.
+ *  Otp debugger block7 data register2.
  */
 #define OTP_DEBUG_BLK7_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x158)
 /** OTP_DEBUG_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
@@ -1056,7 +1056,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W2_S  0
 
 /** OTP_DEBUG_BLK7_W3_REG register
- *  Otp debuger block7 data register3.
+ *  Otp debugger block7 data register3.
  */
 #define OTP_DEBUG_BLK7_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x15c)
 /** OTP_DEBUG_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
@@ -1068,7 +1068,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W3_S  0
 
 /** OTP_DEBUG_BLK7_W4_REG register
- *  Otp debuger block7 data register4.
+ *  Otp debugger block7 data register4.
  */
 #define OTP_DEBUG_BLK7_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x160)
 /** OTP_DEBUG_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
@@ -1080,7 +1080,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W4_S  0
 
 /** OTP_DEBUG_BLK7_W5_REG register
- *  Otp debuger block7 data register5.
+ *  Otp debugger block7 data register5.
  */
 #define OTP_DEBUG_BLK7_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x164)
 /** OTP_DEBUG_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
@@ -1092,7 +1092,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W5_S  0
 
 /** OTP_DEBUG_BLK7_W6_REG register
- *  Otp debuger block7 data register6.
+ *  Otp debugger block7 data register6.
  */
 #define OTP_DEBUG_BLK7_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x168)
 /** OTP_DEBUG_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
@@ -1104,7 +1104,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W6_S  0
 
 /** OTP_DEBUG_BLK7_W7_REG register
- *  Otp debuger block7 data register7.
+ *  Otp debugger block7 data register7.
  */
 #define OTP_DEBUG_BLK7_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x16c)
 /** OTP_DEBUG_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
@@ -1116,7 +1116,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W7_S  0
 
 /** OTP_DEBUG_BLK7_W8_REG register
- *  Otp debuger block7 data register8.
+ *  Otp debugger block7 data register8.
  */
 #define OTP_DEBUG_BLK7_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x170)
 /** OTP_DEBUG_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
@@ -1128,7 +1128,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W8_S  0
 
 /** OTP_DEBUG_BLK7_W9_REG register
- *  Otp debuger block7 data register9.
+ *  Otp debugger block7 data register9.
  */
 #define OTP_DEBUG_BLK7_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x174)
 /** OTP_DEBUG_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1140,7 +1140,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W9_S  0
 
 /** OTP_DEBUG_BLK7_W10_REG register
- *  Otp debuger block7 data register10.
+ *  Otp debugger block7 data register10.
  */
 #define OTP_DEBUG_BLK7_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x178)
 /** OTP_DEBUG_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1152,7 +1152,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W10_S  0
 
 /** OTP_DEBUG_BLK7_W11_REG register
- *  Otp debuger block7 data register11.
+ *  Otp debugger block7 data register11.
  */
 #define OTP_DEBUG_BLK7_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x17c)
 /** OTP_DEBUG_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1164,7 +1164,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK7_W11_S  0
 
 /** OTP_DEBUG_BLK8_W1_REG register
- *  Otp debuger block8 data register1.
+ *  Otp debugger block8 data register1.
  */
 #define OTP_DEBUG_BLK8_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x180)
 /** OTP_DEBUG_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
@@ -1176,7 +1176,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W1_S  0
 
 /** OTP_DEBUG_BLK8_W2_REG register
- *  Otp debuger block8 data register2.
+ *  Otp debugger block8 data register2.
  */
 #define OTP_DEBUG_BLK8_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x184)
 /** OTP_DEBUG_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
@@ -1188,7 +1188,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W2_S  0
 
 /** OTP_DEBUG_BLK8_W3_REG register
- *  Otp debuger block8 data register3.
+ *  Otp debugger block8 data register3.
  */
 #define OTP_DEBUG_BLK8_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x188)
 /** OTP_DEBUG_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
@@ -1200,7 +1200,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W3_S  0
 
 /** OTP_DEBUG_BLK8_W4_REG register
- *  Otp debuger block8 data register4.
+ *  Otp debugger block8 data register4.
  */
 #define OTP_DEBUG_BLK8_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x18c)
 /** OTP_DEBUG_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
@@ -1212,7 +1212,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W4_S  0
 
 /** OTP_DEBUG_BLK8_W5_REG register
- *  Otp debuger block8 data register5.
+ *  Otp debugger block8 data register5.
  */
 #define OTP_DEBUG_BLK8_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x190)
 /** OTP_DEBUG_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
@@ -1224,7 +1224,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W5_S  0
 
 /** OTP_DEBUG_BLK8_W6_REG register
- *  Otp debuger block8 data register6.
+ *  Otp debugger block8 data register6.
  */
 #define OTP_DEBUG_BLK8_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x194)
 /** OTP_DEBUG_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
@@ -1236,7 +1236,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W6_S  0
 
 /** OTP_DEBUG_BLK8_W7_REG register
- *  Otp debuger block8 data register7.
+ *  Otp debugger block8 data register7.
  */
 #define OTP_DEBUG_BLK8_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x198)
 /** OTP_DEBUG_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
@@ -1248,7 +1248,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W7_S  0
 
 /** OTP_DEBUG_BLK8_W8_REG register
- *  Otp debuger block8 data register8.
+ *  Otp debugger block8 data register8.
  */
 #define OTP_DEBUG_BLK8_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x19c)
 /** OTP_DEBUG_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
@@ -1260,7 +1260,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W8_S  0
 
 /** OTP_DEBUG_BLK8_W9_REG register
- *  Otp debuger block8 data register9.
+ *  Otp debugger block8 data register9.
  */
 #define OTP_DEBUG_BLK8_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1a0)
 /** OTP_DEBUG_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1272,7 +1272,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W9_S  0
 
 /** OTP_DEBUG_BLK8_W10_REG register
- *  Otp debuger block8 data register10.
+ *  Otp debugger block8 data register10.
  */
 #define OTP_DEBUG_BLK8_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1a4)
 /** OTP_DEBUG_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1284,7 +1284,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W10_S  0
 
 /** OTP_DEBUG_BLK8_W11_REG register
- *  Otp debuger block8 data register11.
+ *  Otp debugger block8 data register11.
  */
 #define OTP_DEBUG_BLK8_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1a8)
 /** OTP_DEBUG_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1296,7 +1296,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK8_W11_S  0
 
 /** OTP_DEBUG_BLK9_W1_REG register
- *  Otp debuger block9 data register1.
+ *  Otp debugger block9 data register1.
  */
 #define OTP_DEBUG_BLK9_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1ac)
 /** OTP_DEBUG_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
@@ -1308,7 +1308,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W1_S  0
 
 /** OTP_DEBUG_BLK9_W2_REG register
- *  Otp debuger block9 data register2.
+ *  Otp debugger block9 data register2.
  */
 #define OTP_DEBUG_BLK9_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1b0)
 /** OTP_DEBUG_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
@@ -1320,7 +1320,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W2_S  0
 
 /** OTP_DEBUG_BLK9_W3_REG register
- *  Otp debuger block9 data register3.
+ *  Otp debugger block9 data register3.
  */
 #define OTP_DEBUG_BLK9_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1b4)
 /** OTP_DEBUG_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
@@ -1332,7 +1332,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W3_S  0
 
 /** OTP_DEBUG_BLK9_W4_REG register
- *  Otp debuger block9 data register4.
+ *  Otp debugger block9 data register4.
  */
 #define OTP_DEBUG_BLK9_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1b8)
 /** OTP_DEBUG_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
@@ -1344,7 +1344,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W4_S  0
 
 /** OTP_DEBUG_BLK9_W5_REG register
- *  Otp debuger block9 data register5.
+ *  Otp debugger block9 data register5.
  */
 #define OTP_DEBUG_BLK9_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1bc)
 /** OTP_DEBUG_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
@@ -1356,7 +1356,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W5_S  0
 
 /** OTP_DEBUG_BLK9_W6_REG register
- *  Otp debuger block9 data register6.
+ *  Otp debugger block9 data register6.
  */
 #define OTP_DEBUG_BLK9_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1c0)
 /** OTP_DEBUG_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
@@ -1368,7 +1368,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W6_S  0
 
 /** OTP_DEBUG_BLK9_W7_REG register
- *  Otp debuger block9 data register7.
+ *  Otp debugger block9 data register7.
  */
 #define OTP_DEBUG_BLK9_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1c4)
 /** OTP_DEBUG_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
@@ -1380,7 +1380,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W7_S  0
 
 /** OTP_DEBUG_BLK9_W8_REG register
- *  Otp debuger block9 data register8.
+ *  Otp debugger block9 data register8.
  */
 #define OTP_DEBUG_BLK9_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1c8)
 /** OTP_DEBUG_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
@@ -1392,7 +1392,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W8_S  0
 
 /** OTP_DEBUG_BLK9_W9_REG register
- *  Otp debuger block9 data register9.
+ *  Otp debugger block9 data register9.
  */
 #define OTP_DEBUG_BLK9_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1cc)
 /** OTP_DEBUG_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1404,7 +1404,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W9_S  0
 
 /** OTP_DEBUG_BLK9_W10_REG register
- *  Otp debuger block9 data register10.
+ *  Otp debugger block9 data register10.
  */
 #define OTP_DEBUG_BLK9_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1d0)
 /** OTP_DEBUG_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1416,7 +1416,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W10_S  0
 
 /** OTP_DEBUG_BLK9_W11_REG register
- *  Otp debuger block9 data register11.
+ *  Otp debugger block9 data register11.
  */
 #define OTP_DEBUG_BLK9_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x1d4)
 /** OTP_DEBUG_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1428,7 +1428,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK9_W11_S  0
 
 /** OTP_DEBUG_BLK10_W1_REG register
- *  Otp debuger block10 data register1.
+ *  Otp debugger block10 data register1.
  */
 #define OTP_DEBUG_BLK10_W1_REG (DR_REG_OTP_DEBUG_BASE + 0x1d8)
 /** OTP_DEBUG_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
@@ -1440,7 +1440,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W1_S  0
 
 /** OTP_DEBUG_BLK10_W2_REG register
- *  Otp debuger block10 data register2.
+ *  Otp debugger block10 data register2.
  */
 #define OTP_DEBUG_BLK10_W2_REG (DR_REG_OTP_DEBUG_BASE + 0x1dc)
 /** OTP_DEBUG_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
@@ -1452,7 +1452,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W2_S  0
 
 /** OTP_DEBUG_BLK10_W3_REG register
- *  Otp debuger block10 data register3.
+ *  Otp debugger block10 data register3.
  */
 #define OTP_DEBUG_BLK10_W3_REG (DR_REG_OTP_DEBUG_BASE + 0x1e0)
 /** OTP_DEBUG_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
@@ -1464,7 +1464,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W3_S  0
 
 /** OTP_DEBUG_BLK10_W4_REG register
- *  Otp debuger block10 data register4.
+ *  Otp debugger block10 data register4.
  */
 #define OTP_DEBUG_BLK10_W4_REG (DR_REG_OTP_DEBUG_BASE + 0x1e4)
 /** OTP_DEBUG_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
@@ -1476,7 +1476,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W4_S  0
 
 /** OTP_DEBUG_BLK10_W5_REG register
- *  Otp debuger block10 data register5.
+ *  Otp debugger block10 data register5.
  */
 #define OTP_DEBUG_BLK10_W5_REG (DR_REG_OTP_DEBUG_BASE + 0x1e8)
 /** OTP_DEBUG_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
@@ -1488,7 +1488,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W5_S  0
 
 /** OTP_DEBUG_BLK10_W6_REG register
- *  Otp debuger block10 data register6.
+ *  Otp debugger block10 data register6.
  */
 #define OTP_DEBUG_BLK10_W6_REG (DR_REG_OTP_DEBUG_BASE + 0x1ec)
 /** OTP_DEBUG_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
@@ -1500,7 +1500,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W6_S  0
 
 /** OTP_DEBUG_BLK10_W7_REG register
- *  Otp debuger block10 data register7.
+ *  Otp debugger block10 data register7.
  */
 #define OTP_DEBUG_BLK10_W7_REG (DR_REG_OTP_DEBUG_BASE + 0x1f0)
 /** OTP_DEBUG_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
@@ -1512,7 +1512,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W7_S  0
 
 /** OTP_DEBUG_BLK10_W8_REG register
- *  Otp debuger block10 data register8.
+ *  Otp debugger block10 data register8.
  */
 #define OTP_DEBUG_BLK10_W8_REG (DR_REG_OTP_DEBUG_BASE + 0x1f4)
 /** OTP_DEBUG_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
@@ -1524,7 +1524,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W8_S  0
 
 /** OTP_DEBUG_BLK10_W9_REG register
- *  Otp debuger block10 data register9.
+ *  Otp debugger block10 data register9.
  */
 #define OTP_DEBUG_BLK10_W9_REG (DR_REG_OTP_DEBUG_BASE + 0x1f8)
 /** OTP_DEBUG_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
@@ -1536,7 +1536,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W9_S  0
 
 /** OTP_DEBUG_BLK10_W10_REG register
- *  Otp debuger block10 data register10.
+ *  Otp debugger block10 data register10.
  */
 #define OTP_DEBUG_BLK10_W10_REG (DR_REG_OTP_DEBUG_BASE + 0x1fc)
 /** OTP_DEBUG_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
@@ -1548,7 +1548,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK19_W10_S  0
 
 /** OTP_DEBUG_BLK10_W11_REG register
- *  Otp debuger block10 data register11.
+ *  Otp debugger block10 data register11.
  */
 #define OTP_DEBUG_BLK10_W11_REG (DR_REG_OTP_DEBUG_BASE + 0x200)
 /** OTP_DEBUG_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
@@ -1560,7 +1560,7 @@ extern "C" {
 #define OTP_DEBUG_BLOCK10_W11_S  0
 
 /** OTP_DEBUG_CLK_REG register
- *  Otp debuger clk_en configuration register.
+ *  Otp debugger clk_en configuration register.
  */
 #define OTP_DEBUG_CLK_REG (DR_REG_OTP_DEBUG_BASE + 0x204)
 /** OTP_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 0;
diff --git a/components/soc/esp32c6/include/soc/otp_debug_struct.h b/components/soc/esp32c6/register/soc/otp_debug_struct.h
similarity index 89%
rename from components/soc/esp32c6/include/soc/otp_debug_struct.h
rename to components/soc/esp32c6/register/soc/otp_debug_struct.h
index 5b0737475f7..8ed1fe28029 100644
--- a/components/soc/esp32c6/include/soc/otp_debug_struct.h
+++ b/components/soc/esp32c6/register/soc/otp_debug_struct.h
@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: OTP_DEBUG Block0 Write Disable Data */
 /** Type of wr_dis register
- *  Otp debuger block0 data register1.
+ *  Otp debugger block0 data register1.
  */
 typedef union {
     struct {
@@ -27,7 +27,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word1 Data */
 /** Type of blk0_backup1_w1 register
- *  Otp debuger block0 data register2.
+ *  Otp debugger block0 data register2.
  */
 typedef union {
     struct {
@@ -42,7 +42,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word2 Data */
 /** Type of blk0_backup1_w2 register
- *  Otp debuger block0 data register3.
+ *  Otp debugger block0 data register3.
  */
 typedef union {
     struct {
@@ -57,7 +57,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word3 Data */
 /** Type of blk0_backup1_w3 register
- *  Otp debuger block0 data register4.
+ *  Otp debugger block0 data register4.
  */
 typedef union {
     struct {
@@ -72,7 +72,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word4 Data */
 /** Type of blk0_backup1_w4 register
- *  Otp debuger block0 data register5.
+ *  Otp debugger block0 data register5.
  */
 typedef union {
     struct {
@@ -87,7 +87,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup1 Word5 Data */
 /** Type of blk0_backup1_w5 register
- *  Otp debuger block0 data register6.
+ *  Otp debugger block0 data register6.
  */
 typedef union {
     struct {
@@ -102,7 +102,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word1 Data */
 /** Type of blk0_backup2_w1 register
- *  Otp debuger block0 data register7.
+ *  Otp debugger block0 data register7.
  */
 typedef union {
     struct {
@@ -117,7 +117,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word2 Data */
 /** Type of blk0_backup2_w2 register
- *  Otp debuger block0 data register8.
+ *  Otp debugger block0 data register8.
  */
 typedef union {
     struct {
@@ -132,7 +132,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word3 Data */
 /** Type of blk0_backup2_w3 register
- *  Otp debuger block0 data register9.
+ *  Otp debugger block0 data register9.
  */
 typedef union {
     struct {
@@ -147,7 +147,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word4 Data */
 /** Type of blk0_backup2_w4 register
- *  Otp debuger block0 data register10.
+ *  Otp debugger block0 data register10.
  */
 typedef union {
     struct {
@@ -162,7 +162,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup2 Word5 Data */
 /** Type of blk0_backup2_w5 register
- *  Otp debuger block0 data register11.
+ *  Otp debugger block0 data register11.
  */
 typedef union {
     struct {
@@ -177,7 +177,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word1 Data */
 /** Type of blk0_backup3_w1 register
- *  Otp debuger block0 data register12.
+ *  Otp debugger block0 data register12.
  */
 typedef union {
     struct {
@@ -192,7 +192,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word2 Data */
 /** Type of blk0_backup3_w2 register
- *  Otp debuger block0 data register13.
+ *  Otp debugger block0 data register13.
  */
 typedef union {
     struct {
@@ -207,7 +207,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word3 Data */
 /** Type of blk0_backup3_w3 register
- *  Otp debuger block0 data register14.
+ *  Otp debugger block0 data register14.
  */
 typedef union {
     struct {
@@ -222,7 +222,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word4 Data */
 /** Type of blk0_backup3_w4 register
- *  Otp debuger block0 data register15.
+ *  Otp debugger block0 data register15.
  */
 typedef union {
     struct {
@@ -237,7 +237,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup3 Word5 Data */
 /** Type of blk0_backup3_w5 register
- *  Otp debuger block0 data register16.
+ *  Otp debugger block0 data register16.
  */
 typedef union {
     struct {
@@ -252,7 +252,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word1 Data */
 /** Type of blk0_backup4_w1 register
- *  Otp debuger block0 data register17.
+ *  Otp debugger block0 data register17.
  */
 typedef union {
     struct {
@@ -267,7 +267,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word2 Data */
 /** Type of blk0_backup4_w2 register
- *  Otp debuger block0 data register18.
+ *  Otp debugger block0 data register18.
  */
 typedef union {
     struct {
@@ -282,7 +282,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word3 Data */
 /** Type of blk0_backup4_w3 register
- *  Otp debuger block0 data register19.
+ *  Otp debugger block0 data register19.
  */
 typedef union {
     struct {
@@ -297,7 +297,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word4 Data */
 /** Type of blk0_backup4_w4 register
- *  Otp debuger block0 data register20.
+ *  Otp debugger block0 data register20.
  */
 typedef union {
     struct {
@@ -312,7 +312,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block0 Backup4 Word5 Data */
 /** Type of blk0_backup4_w5 register
- *  Otp debuger block0 data register21.
+ *  Otp debugger block0 data register21.
  */
 typedef union {
     struct {
@@ -327,7 +327,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word1 Data */
 /** Type of blk1_w1 register
- *  Otp debuger block1 data register1.
+ *  Otp debugger block1 data register1.
  */
 typedef union {
     struct {
@@ -342,7 +342,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word2 Data */
 /** Type of blk1_w2 register
- *  Otp debuger block1 data register2.
+ *  Otp debugger block1 data register2.
  */
 typedef union {
     struct {
@@ -357,7 +357,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word3 Data */
 /** Type of blk1_w3 register
- *  Otp debuger block1 data register3.
+ *  Otp debugger block1 data register3.
  */
 typedef union {
     struct {
@@ -372,7 +372,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word4 Data */
 /** Type of blk1_w4 register
- *  Otp debuger block1 data register4.
+ *  Otp debugger block1 data register4.
  */
 typedef union {
     struct {
@@ -387,7 +387,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word5 Data */
 /** Type of blk1_w5 register
- *  Otp debuger block1 data register5.
+ *  Otp debugger block1 data register5.
  */
 typedef union {
     struct {
@@ -402,7 +402,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word6 Data */
 /** Type of blk1_w6 register
- *  Otp debuger block1 data register6.
+ *  Otp debugger block1 data register6.
  */
 typedef union {
     struct {
@@ -417,7 +417,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word7 Data */
 /** Type of blk1_w7 register
- *  Otp debuger block1 data register7.
+ *  Otp debugger block1 data register7.
  */
 typedef union {
     struct {
@@ -432,7 +432,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word8 Data */
 /** Type of blk1_w8 register
- *  Otp debuger block1 data register8.
+ *  Otp debugger block1 data register8.
  */
 typedef union {
     struct {
@@ -447,7 +447,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block1 Word9 Data */
 /** Type of blk1_w9 register
- *  Otp debuger block1 data register9.
+ *  Otp debugger block1 data register9.
  */
 typedef union {
     struct {
@@ -462,7 +462,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word1 Data */
 /** Type of blk2_w1 register
- *  Otp debuger block2 data register1.
+ *  Otp debugger block2 data register1.
  */
 typedef union {
     struct {
@@ -477,7 +477,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word2 Data */
 /** Type of blk2_w2 register
- *  Otp debuger block2 data register2.
+ *  Otp debugger block2 data register2.
  */
 typedef union {
     struct {
@@ -492,7 +492,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word3 Data */
 /** Type of blk2_w3 register
- *  Otp debuger block2 data register3.
+ *  Otp debugger block2 data register3.
  */
 typedef union {
     struct {
@@ -507,7 +507,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word4 Data */
 /** Type of blk2_w4 register
- *  Otp debuger block2 data register4.
+ *  Otp debugger block2 data register4.
  */
 typedef union {
     struct {
@@ -522,7 +522,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word5 Data */
 /** Type of blk2_w5 register
- *  Otp debuger block2 data register5.
+ *  Otp debugger block2 data register5.
  */
 typedef union {
     struct {
@@ -537,7 +537,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word6 Data */
 /** Type of blk2_w6 register
- *  Otp debuger block2 data register6.
+ *  Otp debugger block2 data register6.
  */
 typedef union {
     struct {
@@ -552,7 +552,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word7 Data */
 /** Type of blk2_w7 register
- *  Otp debuger block2 data register7.
+ *  Otp debugger block2 data register7.
  */
 typedef union {
     struct {
@@ -567,7 +567,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word8 Data */
 /** Type of blk2_w8 register
- *  Otp debuger block2 data register8.
+ *  Otp debugger block2 data register8.
  */
 typedef union {
     struct {
@@ -582,7 +582,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word9 Data */
 /** Type of blk2_w9 register
- *  Otp debuger block2 data register9.
+ *  Otp debugger block2 data register9.
  */
 typedef union {
     struct {
@@ -597,7 +597,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word10 Data */
 /** Type of blk2_w10 register
- *  Otp debuger block2 data register10.
+ *  Otp debugger block2 data register10.
  */
 typedef union {
     struct {
@@ -612,7 +612,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block2 Word11 Data */
 /** Type of blk2_w11 register
- *  Otp debuger block2 data register11.
+ *  Otp debugger block2 data register11.
  */
 typedef union {
     struct {
@@ -625,7 +625,7 @@ typedef union {
 } otp_debug_blk2_w11_reg_t;
 
 /** Type of blk10_w11 register
- *  Otp debuger block10 data register11.
+ *  Otp debugger block10 data register11.
  */
 typedef union {
     struct {
@@ -640,7 +640,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word1 Data */
 /** Type of blk3_w1 register
- *  Otp debuger block3 data register1.
+ *  Otp debugger block3 data register1.
  */
 typedef union {
     struct {
@@ -655,7 +655,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word2 Data */
 /** Type of blk3_w2 register
- *  Otp debuger block3 data register2.
+ *  Otp debugger block3 data register2.
  */
 typedef union {
     struct {
@@ -670,7 +670,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word3 Data */
 /** Type of blk3_w3 register
- *  Otp debuger block3 data register3.
+ *  Otp debugger block3 data register3.
  */
 typedef union {
     struct {
@@ -685,7 +685,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word4 Data */
 /** Type of blk3_w4 register
- *  Otp debuger block3 data register4.
+ *  Otp debugger block3 data register4.
  */
 typedef union {
     struct {
@@ -700,7 +700,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word5 Data */
 /** Type of blk3_w5 register
- *  Otp debuger block3 data register5.
+ *  Otp debugger block3 data register5.
  */
 typedef union {
     struct {
@@ -715,7 +715,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word6 Data */
 /** Type of blk3_w6 register
- *  Otp debuger block3 data register6.
+ *  Otp debugger block3 data register6.
  */
 typedef union {
     struct {
@@ -730,7 +730,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word7 Data */
 /** Type of blk3_w7 register
- *  Otp debuger block3 data register7.
+ *  Otp debugger block3 data register7.
  */
 typedef union {
     struct {
@@ -745,7 +745,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word8 Data */
 /** Type of blk3_w8 register
- *  Otp debuger block3 data register8.
+ *  Otp debugger block3 data register8.
  */
 typedef union {
     struct {
@@ -760,7 +760,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word9 Data */
 /** Type of blk3_w9 register
- *  Otp debuger block3 data register9.
+ *  Otp debugger block3 data register9.
  */
 typedef union {
     struct {
@@ -775,7 +775,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word10 Data */
 /** Type of blk3_w10 register
- *  Otp debuger block3 data register10.
+ *  Otp debugger block3 data register10.
  */
 typedef union {
     struct {
@@ -790,7 +790,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block3 Word11 Data */
 /** Type of blk3_w11 register
- *  Otp debuger block3 data register11.
+ *  Otp debugger block3 data register11.
  */
 typedef union {
     struct {
@@ -805,7 +805,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word1 Data */
 /** Type of blk4_w1 register
- *  Otp debuger block4 data register1.
+ *  Otp debugger block4 data register1.
  */
 typedef union {
     struct {
@@ -820,7 +820,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word2 Data */
 /** Type of blk4_w2 register
- *  Otp debuger block4 data register2.
+ *  Otp debugger block4 data register2.
  */
 typedef union {
     struct {
@@ -835,7 +835,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word3 Data */
 /** Type of blk4_w3 register
- *  Otp debuger block4 data register3.
+ *  Otp debugger block4 data register3.
  */
 typedef union {
     struct {
@@ -850,7 +850,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word4 Data */
 /** Type of blk4_w4 register
- *  Otp debuger block4 data register4.
+ *  Otp debugger block4 data register4.
  */
 typedef union {
     struct {
@@ -865,7 +865,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word5 Data */
 /** Type of blk4_w5 register
- *  Otp debuger block4 data register5.
+ *  Otp debugger block4 data register5.
  */
 typedef union {
     struct {
@@ -880,7 +880,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word6 Data */
 /** Type of blk4_w6 register
- *  Otp debuger block4 data register6.
+ *  Otp debugger block4 data register6.
  */
 typedef union {
     struct {
@@ -895,7 +895,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word7 Data */
 /** Type of blk4_w7 register
- *  Otp debuger block4 data register7.
+ *  Otp debugger block4 data register7.
  */
 typedef union {
     struct {
@@ -910,7 +910,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word8 Data */
 /** Type of blk4_w8 register
- *  Otp debuger block4 data register8.
+ *  Otp debugger block4 data register8.
  */
 typedef union {
     struct {
@@ -925,7 +925,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word9 Data */
 /** Type of blk4_w9 register
- *  Otp debuger block4 data register9.
+ *  Otp debugger block4 data register9.
  */
 typedef union {
     struct {
@@ -940,7 +940,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word10 Data */
 /** Type of blk4_w10 register
- *  Otp debuger block4 data registe10.
+ *  Otp debugger block4 data registe10.
  */
 typedef union {
     struct {
@@ -955,7 +955,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block4 Word11 Data */
 /** Type of blk4_w11 register
- *  Otp debuger block4 data register11.
+ *  Otp debugger block4 data register11.
  */
 typedef union {
     struct {
@@ -970,7 +970,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word1 Data */
 /** Type of blk5_w1 register
- *  Otp debuger block5 data register1.
+ *  Otp debugger block5 data register1.
  */
 typedef union {
     struct {
@@ -985,7 +985,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word2 Data */
 /** Type of blk5_w2 register
- *  Otp debuger block5 data register2.
+ *  Otp debugger block5 data register2.
  */
 typedef union {
     struct {
@@ -1000,7 +1000,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word3 Data */
 /** Type of blk5_w3 register
- *  Otp debuger block5 data register3.
+ *  Otp debugger block5 data register3.
  */
 typedef union {
     struct {
@@ -1015,7 +1015,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word4 Data */
 /** Type of blk5_w4 register
- *  Otp debuger block5 data register4.
+ *  Otp debugger block5 data register4.
  */
 typedef union {
     struct {
@@ -1030,7 +1030,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word5 Data */
 /** Type of blk5_w5 register
- *  Otp debuger block5 data register5.
+ *  Otp debugger block5 data register5.
  */
 typedef union {
     struct {
@@ -1045,7 +1045,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word6 Data */
 /** Type of blk5_w6 register
- *  Otp debuger block5 data register6.
+ *  Otp debugger block5 data register6.
  */
 typedef union {
     struct {
@@ -1060,7 +1060,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word7 Data */
 /** Type of blk5_w7 register
- *  Otp debuger block5 data register7.
+ *  Otp debugger block5 data register7.
  */
 typedef union {
     struct {
@@ -1075,7 +1075,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word8 Data */
 /** Type of blk5_w8 register
- *  Otp debuger block5 data register8.
+ *  Otp debugger block5 data register8.
  */
 typedef union {
     struct {
@@ -1090,7 +1090,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word9 Data */
 /** Type of blk5_w9 register
- *  Otp debuger block5 data register9.
+ *  Otp debugger block5 data register9.
  */
 typedef union {
     struct {
@@ -1105,7 +1105,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word10 Data */
 /** Type of blk5_w10 register
- *  Otp debuger block5 data register10.
+ *  Otp debugger block5 data register10.
  */
 typedef union {
     struct {
@@ -1120,7 +1120,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block5 Word11 Data */
 /** Type of blk5_w11 register
- *  Otp debuger block5 data register11.
+ *  Otp debugger block5 data register11.
  */
 typedef union {
     struct {
@@ -1135,7 +1135,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word1 Data */
 /** Type of blk6_w1 register
- *  Otp debuger block6 data register1.
+ *  Otp debugger block6 data register1.
  */
 typedef union {
     struct {
@@ -1150,7 +1150,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word2 Data */
 /** Type of blk6_w2 register
- *  Otp debuger block6 data register2.
+ *  Otp debugger block6 data register2.
  */
 typedef union {
     struct {
@@ -1165,7 +1165,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word3 Data */
 /** Type of blk6_w3 register
- *  Otp debuger block6 data register3.
+ *  Otp debugger block6 data register3.
  */
 typedef union {
     struct {
@@ -1180,7 +1180,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word4 Data */
 /** Type of blk6_w4 register
- *  Otp debuger block6 data register4.
+ *  Otp debugger block6 data register4.
  */
 typedef union {
     struct {
@@ -1195,7 +1195,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word5 Data */
 /** Type of blk6_w5 register
- *  Otp debuger block6 data register5.
+ *  Otp debugger block6 data register5.
  */
 typedef union {
     struct {
@@ -1210,7 +1210,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word6 Data */
 /** Type of blk6_w6 register
- *  Otp debuger block6 data register6.
+ *  Otp debugger block6 data register6.
  */
 typedef union {
     struct {
@@ -1225,7 +1225,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word7 Data */
 /** Type of blk6_w7 register
- *  Otp debuger block6 data register7.
+ *  Otp debugger block6 data register7.
  */
 typedef union {
     struct {
@@ -1240,7 +1240,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word8 Data */
 /** Type of blk6_w8 register
- *  Otp debuger block6 data register8.
+ *  Otp debugger block6 data register8.
  */
 typedef union {
     struct {
@@ -1255,7 +1255,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word9 Data */
 /** Type of blk6_w9 register
- *  Otp debuger block6 data register9.
+ *  Otp debugger block6 data register9.
  */
 typedef union {
     struct {
@@ -1270,7 +1270,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word10 Data */
 /** Type of blk6_w10 register
- *  Otp debuger block6 data register10.
+ *  Otp debugger block6 data register10.
  */
 typedef union {
     struct {
@@ -1285,7 +1285,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block6 Word11 Data */
 /** Type of blk6_w11 register
- *  Otp debuger block6 data register11.
+ *  Otp debugger block6 data register11.
  */
 typedef union {
     struct {
@@ -1300,7 +1300,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word1 Data */
 /** Type of blk7_w1 register
- *  Otp debuger block7 data register1.
+ *  Otp debugger block7 data register1.
  */
 typedef union {
     struct {
@@ -1315,7 +1315,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word2 Data */
 /** Type of blk7_w2 register
- *  Otp debuger block7 data register2.
+ *  Otp debugger block7 data register2.
  */
 typedef union {
     struct {
@@ -1330,7 +1330,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word3 Data */
 /** Type of blk7_w3 register
- *  Otp debuger block7 data register3.
+ *  Otp debugger block7 data register3.
  */
 typedef union {
     struct {
@@ -1345,7 +1345,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word4 Data */
 /** Type of blk7_w4 register
- *  Otp debuger block7 data register4.
+ *  Otp debugger block7 data register4.
  */
 typedef union {
     struct {
@@ -1360,7 +1360,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word5 Data */
 /** Type of blk7_w5 register
- *  Otp debuger block7 data register5.
+ *  Otp debugger block7 data register5.
  */
 typedef union {
     struct {
@@ -1375,7 +1375,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word6 Data */
 /** Type of blk7_w6 register
- *  Otp debuger block7 data register6.
+ *  Otp debugger block7 data register6.
  */
 typedef union {
     struct {
@@ -1390,7 +1390,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word7 Data */
 /** Type of blk7_w7 register
- *  Otp debuger block7 data register7.
+ *  Otp debugger block7 data register7.
  */
 typedef union {
     struct {
@@ -1405,7 +1405,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word8 Data */
 /** Type of blk7_w8 register
- *  Otp debuger block7 data register8.
+ *  Otp debugger block7 data register8.
  */
 typedef union {
     struct {
@@ -1420,7 +1420,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word9 Data */
 /** Type of blk7_w9 register
- *  Otp debuger block7 data register9.
+ *  Otp debugger block7 data register9.
  */
 typedef union {
     struct {
@@ -1435,7 +1435,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word10 Data */
 /** Type of blk7_w10 register
- *  Otp debuger block7 data register10.
+ *  Otp debugger block7 data register10.
  */
 typedef union {
     struct {
@@ -1450,7 +1450,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block7 Word11 Data */
 /** Type of blk7_w11 register
- *  Otp debuger block7 data register11.
+ *  Otp debugger block7 data register11.
  */
 typedef union {
     struct {
@@ -1465,7 +1465,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word1 Data */
 /** Type of blk8_w1 register
- *  Otp debuger block8 data register1.
+ *  Otp debugger block8 data register1.
  */
 typedef union {
     struct {
@@ -1480,7 +1480,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word2 Data */
 /** Type of blk8_w2 register
- *  Otp debuger block8 data register2.
+ *  Otp debugger block8 data register2.
  */
 typedef union {
     struct {
@@ -1495,7 +1495,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word3 Data */
 /** Type of blk8_w3 register
- *  Otp debuger block8 data register3.
+ *  Otp debugger block8 data register3.
  */
 typedef union {
     struct {
@@ -1510,7 +1510,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word4 Data */
 /** Type of blk8_w4 register
- *  Otp debuger block8 data register4.
+ *  Otp debugger block8 data register4.
  */
 typedef union {
     struct {
@@ -1525,7 +1525,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word5 Data */
 /** Type of blk8_w5 register
- *  Otp debuger block8 data register5.
+ *  Otp debugger block8 data register5.
  */
 typedef union {
     struct {
@@ -1540,7 +1540,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word6 Data */
 /** Type of blk8_w6 register
- *  Otp debuger block8 data register6.
+ *  Otp debugger block8 data register6.
  */
 typedef union {
     struct {
@@ -1555,7 +1555,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word7 Data */
 /** Type of blk8_w7 register
- *  Otp debuger block8 data register7.
+ *  Otp debugger block8 data register7.
  */
 typedef union {
     struct {
@@ -1570,7 +1570,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word8 Data */
 /** Type of blk8_w8 register
- *  Otp debuger block8 data register8.
+ *  Otp debugger block8 data register8.
  */
 typedef union {
     struct {
@@ -1585,7 +1585,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word9 Data */
 /** Type of blk8_w9 register
- *  Otp debuger block8 data register9.
+ *  Otp debugger block8 data register9.
  */
 typedef union {
     struct {
@@ -1600,7 +1600,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word10 Data */
 /** Type of blk8_w10 register
- *  Otp debuger block8 data register10.
+ *  Otp debugger block8 data register10.
  */
 typedef union {
     struct {
@@ -1615,7 +1615,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block8 Word11 Data */
 /** Type of blk8_w11 register
- *  Otp debuger block8 data register11.
+ *  Otp debugger block8 data register11.
  */
 typedef union {
     struct {
@@ -1630,7 +1630,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word1 Data */
 /** Type of blk9_w1 register
- *  Otp debuger block9 data register1.
+ *  Otp debugger block9 data register1.
  */
 typedef union {
     struct {
@@ -1645,7 +1645,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word2 Data */
 /** Type of blk9_w2 register
- *  Otp debuger block9 data register2.
+ *  Otp debugger block9 data register2.
  */
 typedef union {
     struct {
@@ -1660,7 +1660,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word3 Data */
 /** Type of blk9_w3 register
- *  Otp debuger block9 data register3.
+ *  Otp debugger block9 data register3.
  */
 typedef union {
     struct {
@@ -1675,7 +1675,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word4 Data */
 /** Type of blk9_w4 register
- *  Otp debuger block9 data register4.
+ *  Otp debugger block9 data register4.
  */
 typedef union {
     struct {
@@ -1690,7 +1690,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word5 Data */
 /** Type of blk9_w5 register
- *  Otp debuger block9 data register5.
+ *  Otp debugger block9 data register5.
  */
 typedef union {
     struct {
@@ -1705,7 +1705,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word6 Data */
 /** Type of blk9_w6 register
- *  Otp debuger block9 data register6.
+ *  Otp debugger block9 data register6.
  */
 typedef union {
     struct {
@@ -1720,7 +1720,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word7 Data */
 /** Type of blk9_w7 register
- *  Otp debuger block9 data register7.
+ *  Otp debugger block9 data register7.
  */
 typedef union {
     struct {
@@ -1735,7 +1735,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word8 Data */
 /** Type of blk9_w8 register
- *  Otp debuger block9 data register8.
+ *  Otp debugger block9 data register8.
  */
 typedef union {
     struct {
@@ -1750,7 +1750,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word9 Data */
 /** Type of blk9_w9 register
- *  Otp debuger block9 data register9.
+ *  Otp debugger block9 data register9.
  */
 typedef union {
     struct {
@@ -1765,7 +1765,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word10 Data */
 /** Type of blk9_w10 register
- *  Otp debuger block9 data register10.
+ *  Otp debugger block9 data register10.
  */
 typedef union {
     struct {
@@ -1780,7 +1780,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block9 Word11 Data */
 /** Type of blk9_w11 register
- *  Otp debuger block9 data register11.
+ *  Otp debugger block9 data register11.
  */
 typedef union {
     struct {
@@ -1795,7 +1795,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word1 Data */
 /** Type of blk10_w1 register
- *  Otp debuger block10 data register1.
+ *  Otp debugger block10 data register1.
  */
 typedef union {
     struct {
@@ -1810,7 +1810,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word2 Data */
 /** Type of blk10_w2 register
- *  Otp debuger block10 data register2.
+ *  Otp debugger block10 data register2.
  */
 typedef union {
     struct {
@@ -1825,7 +1825,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word3 Data */
 /** Type of blk10_w3 register
- *  Otp debuger block10 data register3.
+ *  Otp debugger block10 data register3.
  */
 typedef union {
     struct {
@@ -1840,7 +1840,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word4 Data */
 /** Type of blk10_w4 register
- *  Otp debuger block10 data register4.
+ *  Otp debugger block10 data register4.
  */
 typedef union {
     struct {
@@ -1855,7 +1855,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word5 Data */
 /** Type of blk10_w5 register
- *  Otp debuger block10 data register5.
+ *  Otp debugger block10 data register5.
  */
 typedef union {
     struct {
@@ -1870,7 +1870,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word6 Data */
 /** Type of blk10_w6 register
- *  Otp debuger block10 data register6.
+ *  Otp debugger block10 data register6.
  */
 typedef union {
     struct {
@@ -1885,7 +1885,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word7 Data */
 /** Type of blk10_w7 register
- *  Otp debuger block10 data register7.
+ *  Otp debugger block10 data register7.
  */
 typedef union {
     struct {
@@ -1900,7 +1900,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word8 Data */
 /** Type of blk10_w8 register
- *  Otp debuger block10 data register8.
+ *  Otp debugger block10 data register8.
  */
 typedef union {
     struct {
@@ -1915,7 +1915,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word9 Data */
 /** Type of blk10_w9 register
- *  Otp debuger block10 data register9.
+ *  Otp debugger block10 data register9.
  */
 typedef union {
     struct {
@@ -1930,7 +1930,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Block10 Word10 Data */
 /** Type of blk10_w10 register
- *  Otp debuger block10 data register10.
+ *  Otp debugger block10 data register10.
  */
 typedef union {
     struct {
@@ -1945,7 +1945,7 @@ typedef union {
 
 /** Group: OTP_DEBUG Clock_en Configuration Register */
 /** Type of clk register
- *  Otp debuger clk_en configuration register.
+ *  Otp debugger clk_en configuration register.
  */
 typedef union {
     struct {
@@ -1959,7 +1959,7 @@ typedef union {
 } otp_debug_clk_reg_t;
 
 
-/** Group: OTP_DEBUG Apb2otp Enable Singal */
+/** Group: OTP_DEBUG Apb2otp Enable Signal */
 /** Type of apb2otp_en register
  *  Otp_debuger apb2otp enable configuration register.
  */
diff --git a/components/soc/esp32c6/register/soc/parl_io_reg.h b/components/soc/esp32c6/register/soc/parl_io_reg.h
new file mode 100644
index 00000000000..191656298c4
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/parl_io_reg.h
@@ -0,0 +1,383 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PARL_IO_RX_CFG0_REG register
+ *  Parallel RX module configuration register0.
+ */
+#define PARL_IO_RX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x0)
+/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [0]; default: 0;
+ *  Write 0 to select eof generated manchnism by configured data byte length. Write 1
+ *  to select eof generated manchnism by external enable signal.
+ */
+#define PARL_IO_RX_EOF_GEN_SEL    (BIT(0))
+#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
+#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
+#define PARL_IO_RX_EOF_GEN_SEL_S  0
+/** PARL_IO_RX_START : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to start rx global data sampling.
+ */
+#define PARL_IO_RX_START    (BIT(1))
+#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
+#define PARL_IO_RX_START_V  0x00000001U
+#define PARL_IO_RX_START_S  1
+/** PARL_IO_RX_DATA_BYTELEN : R/W; bitpos: [17:2]; default: 0;
+ *  Configures rx received data byte length.
+ */
+#define PARL_IO_RX_DATA_BYTELEN    0x0000FFFFU
+#define PARL_IO_RX_DATA_BYTELEN_M  (PARL_IO_RX_DATA_BYTELEN_V << PARL_IO_RX_DATA_BYTELEN_S)
+#define PARL_IO_RX_DATA_BYTELEN_V  0x0000FFFFU
+#define PARL_IO_RX_DATA_BYTELEN_S  2
+/** PARL_IO_RX_SW_EN : R/W; bitpos: [18]; default: 0;
+ *  Write 1 to enable software data sampling.
+ */
+#define PARL_IO_RX_SW_EN    (BIT(18))
+#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
+#define PARL_IO_RX_SW_EN_V  0x00000001U
+#define PARL_IO_RX_SW_EN_S  18
+/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [22:19]; default: 0;
+ *  Pulse submode selection.
+ *  0000: positive pulse start(data bit included) &&  positive pulse end(data bit
+ *  included)
+ *  0001: positive pulse start(data bit included) && positive pulse end (data bit
+ *  excluded)
+ *  0010: positive pulse start(data bit excluded) && positive pulse end (data bit
+ *  included)
+ *  0011: positive pulse start(data bit excluded) && positive pulse end (data bit
+ *  excluded)
+ *  0100: positive pulse start(data bit included) && length end
+ *  0101: positive pulse start(data bit excluded) && length end
+ *  0110: negative pulse start(data bit included) &&  negative pulse end(data bit
+ *  included)
+ *  0111: negative pulse start(data bit included) && negative pulse end (data bit
+ *  excluded)
+ *  1000: negative pulse start(data bit excluded) && negative pulse end (data bit
+ *  included)
+ *  1001: negative pulse start(data bit excluded) && negative pulse end (data bit
+ *  excluded)
+ *  1010: negative pulse start(data bit included) && length end
+ *  1011: negative pulse start(data bit excluded) && length end
+ */
+#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x0000000FU
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x0000000FU
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  19
+/** PARL_IO_RX_LEVEL_SUBMODE_SEL : R/W; bitpos: [23]; default: 0;
+ *  Write 0 to sample data at high level of external enable signal. Write 1 to sample
+ *  data at low level of external enable signal.
+ */
+#define PARL_IO_RX_LEVEL_SUBMODE_SEL    (BIT(23))
+#define PARL_IO_RX_LEVEL_SUBMODE_SEL_M  (PARL_IO_RX_LEVEL_SUBMODE_SEL_V << PARL_IO_RX_LEVEL_SUBMODE_SEL_S)
+#define PARL_IO_RX_LEVEL_SUBMODE_SEL_V  0x00000001U
+#define PARL_IO_RX_LEVEL_SUBMODE_SEL_S  23
+/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  Rx data sampling mode selection.
+ *  000: external level enable mode
+ *  001: external pulse enable mode
+ *  010: internal software enable mode
+ */
+#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
+#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_S  24
+/** PARL_IO_RX_CLK_EDGE_SEL : R/W; bitpos: [26]; default: 0;
+ *  Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable
+ *  sampling data on the falling edge of rx clock.
+ */
+#define PARL_IO_RX_CLK_EDGE_SEL    (BIT(26))
+#define PARL_IO_RX_CLK_EDGE_SEL_M  (PARL_IO_RX_CLK_EDGE_SEL_V << PARL_IO_RX_CLK_EDGE_SEL_S)
+#define PARL_IO_RX_CLK_EDGE_SEL_V  0x00000001U
+#define PARL_IO_RX_CLK_EDGE_SEL_S  26
+/** PARL_IO_RX_BIT_PACK_ORDER : R/W; bitpos: [27]; default: 0;
+ *  Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0
+ *  to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.
+ */
+#define PARL_IO_RX_BIT_PACK_ORDER    (BIT(27))
+#define PARL_IO_RX_BIT_PACK_ORDER_M  (PARL_IO_RX_BIT_PACK_ORDER_V << PARL_IO_RX_BIT_PACK_ORDER_S)
+#define PARL_IO_RX_BIT_PACK_ORDER_V  0x00000001U
+#define PARL_IO_RX_BIT_PACK_ORDER_S  27
+/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [30:28]; default: 0;
+ *  Rx data bus width selection.
+ *  100: bus width is 1 bit
+ *  011: bus width is 2 bits
+ *  010: bus width is 4 bits
+ *  001: bus width is 8 bits
+ *  000: bus width is 16 bits
+ */
+#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
+#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_S  28
+/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to enable soft reset of async fifo in rx module.
+ */
+#define PARL_IO_RX_FIFO_SRST    (BIT(31))
+#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
+#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_RX_FIFO_SRST_S  31
+
+/** PARL_IO_RX_CFG1_REG register
+ *  Parallel RX module configuration register1.
+ */
+#define PARL_IO_RX_CFG1_REG (DR_REG_PARL_IO_BASE + 0x4)
+/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to update rx register configuration signals.
+ */
+#define PARL_IO_RX_REG_UPDATE    (BIT(2))
+#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
+#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
+#define PARL_IO_RX_REG_UPDATE_S  2
+/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [3]; default: 1;
+ *  Write 1 to enable timeout count to generate error eof.
+ */
+#define PARL_IO_RX_TIMEOUT_EN    (BIT(3))
+#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
+#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
+#define PARL_IO_RX_TIMEOUT_EN_S  3
+/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [15:12]; default: 15;
+ *  Configures rx external enable signal selection from 16 data lines.
+ */
+#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
+#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_S  12
+/** PARL_IO_RX_TIMEOUT_THRESHOLD : R/W; bitpos: [31:16]; default: 4095;
+ *  Configures rx threshold of timeout counter.
+ */
+#define PARL_IO_RX_TIMEOUT_THRESHOLD    0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRESHOLD_M  (PARL_IO_RX_TIMEOUT_THRESHOLD_V << PARL_IO_RX_TIMEOUT_THRESHOLD_S)
+#define PARL_IO_RX_TIMEOUT_THRESHOLD_V  0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRESHOLD_S  16
+
+/** PARL_IO_TX_CFG0_REG register
+ *  Parallel TX module configuration register0.
+ */
+#define PARL_IO_TX_CFG0_REG (DR_REG_PARL_IO_BASE + 0x8)
+/** PARL_IO_TX_BYTELEN : R/W; bitpos: [17:2]; default: 0;
+ *  Configures tx sending data byte length.
+ */
+#define PARL_IO_TX_BYTELEN    0x0000FFFFU
+#define PARL_IO_TX_BYTELEN_M  (PARL_IO_TX_BYTELEN_V << PARL_IO_TX_BYTELEN_S)
+#define PARL_IO_TX_BYTELEN_V  0x0000FFFFU
+#define PARL_IO_TX_BYTELEN_S  2
+/** PARL_IO_TX_GATING_EN : R/W; bitpos: [18]; default: 0;
+ *  Write 1 to enable output tx clock gating.
+ */
+#define PARL_IO_TX_GATING_EN    (BIT(18))
+#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
+#define PARL_IO_TX_GATING_EN_V  0x00000001U
+#define PARL_IO_TX_GATING_EN_S  18
+/** PARL_IO_TX_START : R/W; bitpos: [19]; default: 0;
+ *  Write 1 to start tx global data output.
+ */
+#define PARL_IO_TX_START    (BIT(19))
+#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
+#define PARL_IO_TX_START_V  0x00000001U
+#define PARL_IO_TX_START_S  19
+/** PARL_IO_TX_HW_VALID_EN : R/W; bitpos: [20]; default: 0;
+ *  Write 1 to enable tx hardware data valid signal.
+ */
+#define PARL_IO_TX_HW_VALID_EN    (BIT(20))
+#define PARL_IO_TX_HW_VALID_EN_M  (PARL_IO_TX_HW_VALID_EN_V << PARL_IO_TX_HW_VALID_EN_S)
+#define PARL_IO_TX_HW_VALID_EN_V  0x00000001U
+#define PARL_IO_TX_HW_VALID_EN_S  20
+/** PARL_IO_TX_SMP_EDGE_SEL : R/W; bitpos: [25]; default: 0;
+ *  Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable
+ *  sampling data on the falling edge of tx clock.
+ */
+#define PARL_IO_TX_SMP_EDGE_SEL    (BIT(25))
+#define PARL_IO_TX_SMP_EDGE_SEL_M  (PARL_IO_TX_SMP_EDGE_SEL_V << PARL_IO_TX_SMP_EDGE_SEL_S)
+#define PARL_IO_TX_SMP_EDGE_SEL_V  0x00000001U
+#define PARL_IO_TX_SMP_EDGE_SEL_S  25
+/** PARL_IO_TX_BIT_UNPACK_ORDER : R/W; bitpos: [26]; default: 0;
+ *  Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write
+ *  0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits.
+ */
+#define PARL_IO_TX_BIT_UNPACK_ORDER    (BIT(26))
+#define PARL_IO_TX_BIT_UNPACK_ORDER_M  (PARL_IO_TX_BIT_UNPACK_ORDER_V << PARL_IO_TX_BIT_UNPACK_ORDER_S)
+#define PARL_IO_TX_BIT_UNPACK_ORDER_V  0x00000001U
+#define PARL_IO_TX_BIT_UNPACK_ORDER_S  26
+/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [29:27]; default: 0;
+ *  Tx data bus width selection.
+ *  100: bus width is 1 bit
+ *  011: bus width is 2 bits
+ *  010: bus width is 4 bits
+ *  001: bus width is 8 bits
+ *  000: bus width is 16 bits
+ */
+#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
+#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_S  27
+/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to enable soft reset of async fifo in tx module.
+ */
+#define PARL_IO_TX_FIFO_SRST    (BIT(30))
+#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
+#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_TX_FIFO_SRST_S  30
+
+/** PARL_IO_TX_CFG1_REG register
+ *  Parallel TX module configuration register1.
+ */
+#define PARL_IO_TX_CFG1_REG (DR_REG_PARL_IO_BASE + 0xc)
+/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [31:16]; default: 0;
+ *  Configures data value on tx bus when IDLE state.
+ */
+#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
+#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_S  16
+
+/** PARL_IO_ST_REG register
+ *  Parallel IO module status register0.
+ */
+#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x10)
+/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
+ *  Represents the status that tx is ready.
+ */
+#define PARL_IO_TX_READY    (BIT(31))
+#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
+#define PARL_IO_TX_READY_V  0x00000001U
+#define PARL_IO_TX_READY_S  31
+
+/** PARL_IO_INT_ENA_REG register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x14)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable TX_FIFO_REMPTY_INTR.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
+/** PARL_IO_RX_FIFO_WFULL_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable RX_FIFO_WFULL_INTR.
+ */
+#define PARL_IO_RX_FIFO_WFULL_INT_ENA    (BIT(1))
+#define PARL_IO_RX_FIFO_WFULL_INT_ENA_M  (PARL_IO_RX_FIFO_WFULL_INT_ENA_V << PARL_IO_RX_FIFO_WFULL_INT_ENA_S)
+#define PARL_IO_RX_FIFO_WFULL_INT_ENA_V  0x00000001U
+#define PARL_IO_RX_FIFO_WFULL_INT_ENA_S  1
+/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable TX_EOF_INTR.
+ */
+#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
+#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ENA_S  2
+
+/** PARL_IO_INT_RAW_REG register
+ *  Parallel IO interrupt raw signal status register.
+ */
+#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x18)
+/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of TX_FIFO_REMPTY_INTR.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
+/** PARL_IO_RX_FIFO_WFULL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of RX_FIFO_WFULL_INTR.
+ */
+#define PARL_IO_RX_FIFO_WFULL_INT_RAW    (BIT(1))
+#define PARL_IO_RX_FIFO_WFULL_INT_RAW_M  (PARL_IO_RX_FIFO_WFULL_INT_RAW_V << PARL_IO_RX_FIFO_WFULL_INT_RAW_S)
+#define PARL_IO_RX_FIFO_WFULL_INT_RAW_V  0x00000001U
+#define PARL_IO_RX_FIFO_WFULL_INT_RAW_S  1
+/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of TX_EOF_INTR.
+ */
+#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
+#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
+#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_RAW_S  2
+
+/** PARL_IO_INT_ST_REG register
+ *  Parallel IO interrupt signal status register.
+ */
+#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x1c)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of TX_FIFO_REMPTY_INTR.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
+/** PARL_IO_RX_FIFO_WFULL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of RX_FIFO_WFULL_INTR.
+ */
+#define PARL_IO_RX_FIFO_WFULL_INT_ST    (BIT(1))
+#define PARL_IO_RX_FIFO_WFULL_INT_ST_M  (PARL_IO_RX_FIFO_WFULL_INT_ST_V << PARL_IO_RX_FIFO_WFULL_INT_ST_S)
+#define PARL_IO_RX_FIFO_WFULL_INT_ST_V  0x00000001U
+#define PARL_IO_RX_FIFO_WFULL_INT_ST_S  1
+/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of TX_EOF_INTR.
+ */
+#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
+#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ST_S  2
+
+/** PARL_IO_INT_CLR_REG register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x20)
+/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear TX_FIFO_REMPTY_INTR.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
+/** PARL_IO_RX_FIFO_WFULL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear RX_FIFO_WFULL_INTR.
+ */
+#define PARL_IO_RX_FIFO_WFULL_INT_CLR    (BIT(1))
+#define PARL_IO_RX_FIFO_WFULL_INT_CLR_M  (PARL_IO_RX_FIFO_WFULL_INT_CLR_V << PARL_IO_RX_FIFO_WFULL_INT_CLR_S)
+#define PARL_IO_RX_FIFO_WFULL_INT_CLR_V  0x00000001U
+#define PARL_IO_RX_FIFO_WFULL_INT_CLR_S  1
+/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear TX_EOF_INTR.
+ */
+#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
+#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
+#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_CLR_S  2
+
+/** PARL_IO_CLK_REG register
+ *  Parallel IO clk configuration register
+ */
+#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
+/** PARL_IO_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Force clock on for this register file
+ */
+#define PARL_IO_CLK_EN    (BIT(0))
+#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
+#define PARL_IO_CLK_EN_V  0x00000001U
+#define PARL_IO_CLK_EN_S  0
+
+/** PARL_IO_VERSION_REG register
+ *  Version register.
+ */
+#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
+/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35660352;
+ *  Version of this register file
+ */
+#define PARL_IO_DATE    0x0FFFFFFFU
+#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
+#define PARL_IO_DATE_V  0x0FFFFFFFU
+#define PARL_IO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/parl_io_struct.h b/components/soc/esp32c6/register/soc/parl_io_struct.h
new file mode 100644
index 00000000000..e0000ebc56b
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/parl_io_struct.h
@@ -0,0 +1,360 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PARL_IO RX Configuration0 */
+/** Type of rx_cfg0 register
+ *  Parallel RX module configuration register0.
+ */
+typedef union {
+    struct {
+        /** rx_eof_gen_sel : R/W; bitpos: [0]; default: 0;
+         *  Write 0 to select eof generated manchnism by configured data byte length. Write 1
+         *  to select eof generated manchnism by external enable signal.
+         */
+        uint32_t rx_eof_gen_sel:1;
+        /** rx_start : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to start rx global data sampling.
+         */
+        uint32_t rx_start:1;
+        /** rx_data_bytelen : R/W; bitpos: [17:2]; default: 0;
+         *  Configures rx received data byte length.
+         */
+        uint32_t rx_data_bytelen:16;
+        /** rx_sw_en : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable software data sampling.
+         */
+        uint32_t rx_sw_en:1;
+        /** rx_pulse_submode_sel : R/W; bitpos: [22:19]; default: 0;
+         *  Pulse submode selection.
+         *  0000: positive pulse start(data bit included) &&  positive pulse end(data bit
+         *  included)
+         *  0001: positive pulse start(data bit included) && positive pulse end (data bit
+         *  excluded)
+         *  0010: positive pulse start(data bit excluded) && positive pulse end (data bit
+         *  included)
+         *  0011: positive pulse start(data bit excluded) && positive pulse end (data bit
+         *  excluded)
+         *  0100: positive pulse start(data bit included) && length end
+         *  0101: positive pulse start(data bit excluded) && length end
+         *  0110: negative pulse start(data bit included) &&  negative pulse end(data bit
+         *  included)
+         *  0111: negative pulse start(data bit included) && negative pulse end (data bit
+         *  excluded)
+         *  1000: negative pulse start(data bit excluded) && negative pulse end (data bit
+         *  included)
+         *  1001: negative pulse start(data bit excluded) && negative pulse end (data bit
+         *  excluded)
+         *  1010: negative pulse start(data bit included) && length end
+         *  1011: negative pulse start(data bit excluded) && length end
+         */
+        uint32_t rx_pulse_submode_sel:4;
+        /** rx_level_submode_sel : R/W; bitpos: [23]; default: 0;
+         *  Write 0 to sample data at high level of external enable signal. Write 1 to sample
+         *  data at low level of external enable signal.
+         */
+        uint32_t rx_level_submode_sel:1;
+        /** rx_smp_mode_sel : R/W; bitpos: [25:24]; default: 0;
+         *  Rx data sampling mode selection.
+         *  000: external level enable mode
+         *  001: external pulse enable mode
+         *  010: internal software enable mode
+         */
+        uint32_t rx_smp_mode_sel:2;
+        /** rx_clk_edge_sel : R/W; bitpos: [26]; default: 0;
+         *  Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable
+         *  sampling data on the falling edge of rx clock.
+         */
+        uint32_t rx_clk_edge_sel:1;
+        /** rx_bit_pack_order : R/W; bitpos: [27]; default: 0;
+         *  Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0
+         *  to pack bits into 1byte from LSB when data bus width is 4/2/1 bits.
+         */
+        uint32_t rx_bit_pack_order:1;
+        /** rx_bus_wid_sel : R/W; bitpos: [30:28]; default: 0;
+         *  Rx data bus width selection.
+         *  100: bus width is 1 bit
+         *  011: bus width is 2 bits
+         *  010: bus width is 4 bits
+         *  001: bus width is 8 bits
+         *  000: bus width is 16 bits
+         */
+        uint32_t rx_bus_wid_sel:3;
+        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to enable soft reset of async fifo in rx module.
+         */
+        uint32_t rx_fifo_srst:1;
+    };
+    uint32_t val;
+} parl_io_rx_cfg0_reg_t;
+
+
+/** Group: PARL_IO RX Configuration1 */
+/** Type of rx_cfg1 register
+ *  Parallel RX module configuration register1.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** rx_reg_update : WT; bitpos: [2]; default: 0;
+         *  Write 1 to update rx register configuration signals.
+         */
+        uint32_t rx_reg_update:1;
+        /** rx_timeout_en : R/W; bitpos: [3]; default: 1;
+         *  Write 1 to enable timeout count to generate error eof.
+         */
+        uint32_t rx_timeout_en:1;
+        uint32_t reserved_4:8;
+        /** rx_ext_en_sel : R/W; bitpos: [15:12]; default: 15;
+         *  Configures rx external enable signal selection from 16 data lines.
+         */
+        uint32_t rx_ext_en_sel:4;
+        /** rx_timeout_threshold : R/W; bitpos: [31:16]; default: 4095;
+         *  Configures rx threshold of timeout counter.
+         */
+        uint32_t rx_timeout_threshold:16;
+    };
+    uint32_t val;
+} parl_io_rx_cfg1_reg_t;
+
+
+/** Group: PARL_IO TX Configuration0 */
+/** Type of tx_cfg0 register
+ *  Parallel TX module configuration register0.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** tx_bytelen : R/W; bitpos: [17:2]; default: 0;
+         *  Configures tx sending data byte length.
+         */
+        uint32_t tx_bytelen:16;
+        /** tx_gating_en : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable output tx clock gating.
+         */
+        uint32_t tx_gating_en:1;
+        /** tx_start : R/W; bitpos: [19]; default: 0;
+         *  Write 1 to start tx global data output.
+         */
+        uint32_t tx_start:1;
+        /** tx_hw_valid_en : R/W; bitpos: [20]; default: 0;
+         *  Write 1 to enable tx hardware data valid signal.
+         */
+        uint32_t tx_hw_valid_en:1;
+        uint32_t reserved_21:4;
+        /** tx_smp_edge_sel : R/W; bitpos: [25]; default: 0;
+         *  Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable
+         *  sampling data on the falling edge of tx clock.
+         */
+        uint32_t tx_smp_edge_sel:1;
+        /** tx_bit_unpack_order : R/W; bitpos: [26]; default: 0;
+         *  Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write
+         *  0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits.
+         */
+        uint32_t tx_bit_unpack_order:1;
+        /** tx_bus_wid_sel : R/W; bitpos: [29:27]; default: 0;
+         *  Tx data bus width selection.
+         *  100: bus width is 1 bit
+         *  011: bus width is 2 bits
+         *  010: bus width is 4 bits
+         *  001: bus width is 8 bits
+         *  000: bus width is 16 bits
+         */
+        uint32_t tx_bus_wid_sel:3;
+        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to enable soft reset of async fifo in tx module.
+         */
+        uint32_t tx_fifo_srst:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} parl_io_tx_cfg0_reg_t;
+
+
+/** Group: PARL_IO TX Configuration1 */
+/** Type of tx_cfg1 register
+ *  Parallel TX module configuration register1.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** tx_idle_value : R/W; bitpos: [31:16]; default: 0;
+         *  Configures data value on tx bus when IDLE state.
+         */
+        uint32_t tx_idle_value:16;
+    };
+    uint32_t val;
+} parl_io_tx_cfg1_reg_t;
+
+
+/** Group: PARL_IO TX Status0 */
+/** Type of st register
+ *  Parallel IO module status register0.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_ready : RO; bitpos: [31]; default: 0;
+         *  Represents the status that tx is ready.
+         */
+        uint32_t tx_ready:1;
+    };
+    uint32_t val;
+} parl_io_st_reg_t;
+
+
+/** Group: PARL_IO Interrupt Configuration and Status */
+/** Type of int_ena register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable TX_FIFO_REMPTY_INTR.
+         */
+        uint32_t tx_fifo_rempty_int_ena:1;
+        /** rx_fifo_wfull_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable RX_FIFO_WFULL_INTR.
+         */
+        uint32_t rx_fifo_wfull_int_ena:1;
+        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable TX_EOF_INTR.
+         */
+        uint32_t tx_eof_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Parallel IO interrupt raw signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of TX_FIFO_REMPTY_INTR.
+         */
+        uint32_t tx_fifo_rempty_int_raw:1;
+        /** rx_fifo_wfull_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of RX_FIFO_WFULL_INTR.
+         */
+        uint32_t rx_fifo_wfull_int_raw:1;
+        /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of TX_EOF_INTR.
+         */
+        uint32_t tx_eof_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Parallel IO interrupt signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of TX_FIFO_REMPTY_INTR.
+         */
+        uint32_t tx_fifo_rempty_int_st:1;
+        /** rx_fifo_wfull_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of RX_FIFO_WFULL_INTR.
+         */
+        uint32_t rx_fifo_wfull_int_st:1;
+        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of TX_EOF_INTR.
+         */
+        uint32_t tx_eof_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear TX_FIFO_REMPTY_INTR.
+         */
+        uint32_t tx_fifo_rempty_int_clr:1;
+        /** rx_fifo_wfull_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear RX_FIFO_WFULL_INTR.
+         */
+        uint32_t rx_fifo_wfull_int_clr:1;
+        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear TX_EOF_INTR.
+         */
+        uint32_t tx_eof_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_clr_reg_t;
+
+
+/** Group: PARL_IO Clock Gating Configuration */
+/** Type of clk register
+ *  Parallel IO clk configuration register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} parl_io_clk_reg_t;
+
+
+/** Group: PARL_IO Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35660352;
+         *  Version of this register file
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} parl_io_version_reg_t;
+
+
+typedef struct parl_io_dev_t {
+    volatile parl_io_rx_cfg0_reg_t rx_cfg0;
+    volatile parl_io_rx_cfg1_reg_t rx_cfg1;
+    volatile parl_io_tx_cfg0_reg_t tx_cfg0;
+    volatile parl_io_tx_cfg1_reg_t tx_cfg1;
+    volatile parl_io_st_reg_t st;
+    volatile parl_io_int_ena_reg_t int_ena;
+    volatile parl_io_int_raw_reg_t int_raw;
+    volatile parl_io_int_st_reg_t int_st;
+    volatile parl_io_int_clr_reg_t int_clr;
+    uint32_t reserved_024[63];
+    volatile parl_io_clk_reg_t clk;
+    uint32_t reserved_124[182];
+    volatile parl_io_version_reg_t version;
+} parl_io_dev_t;
+
+extern parl_io_dev_t PARL_IO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/pau_reg.h b/components/soc/esp32c6/register/soc/pau_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pau_reg.h
rename to components/soc/esp32c6/register/soc/pau_reg.h
diff --git a/components/soc/esp32c6/include/soc/pau_struct.h b/components/soc/esp32c6/register/soc/pau_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pau_struct.h
rename to components/soc/esp32c6/register/soc/pau_struct.h
diff --git a/components/soc/esp32c6/include/soc/pcnt_reg.h b/components/soc/esp32c6/register/soc/pcnt_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pcnt_reg.h
rename to components/soc/esp32c6/register/soc/pcnt_reg.h
diff --git a/components/soc/esp32c6/include/soc/pcnt_struct.h b/components/soc/esp32c6/register/soc/pcnt_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pcnt_struct.h
rename to components/soc/esp32c6/register/soc/pcnt_struct.h
diff --git a/components/soc/esp32c6/register/soc/pcr_reg.h b/components/soc/esp32c6/register/soc/pcr_reg.h
new file mode 100644
index 00000000000..466b25f0201
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/pcr_reg.h
@@ -0,0 +1,2065 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PCR_UART0_CONF_REG register
+ *  UART0 configuration register
+ */
+#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)
+/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uart0 apb clock
+ */
+#define PCR_UART0_CLK_EN    (BIT(0))
+#define PCR_UART0_CLK_EN_M  (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S)
+#define PCR_UART0_CLK_EN_V  0x00000001U
+#define PCR_UART0_CLK_EN_S  0
+/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uart0 module
+ */
+#define PCR_UART0_RST_EN    (BIT(1))
+#define PCR_UART0_RST_EN_M  (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
+#define PCR_UART0_RST_EN_V  0x00000001U
+#define PCR_UART0_RST_EN_S  1
+
+/** PCR_UART0_SCLK_CONF_REG register
+ *  UART0_SCLK configuration register
+ */
+#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)
+/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_A    0x0000003FU
+#define PCR_UART0_SCLK_DIV_A_M  (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S)
+#define PCR_UART0_SCLK_DIV_A_V  0x0000003FU
+#define PCR_UART0_SCLK_DIV_A_S  0
+/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_B    0x0000003FU
+#define PCR_UART0_SCLK_DIV_B_M  (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S)
+#define PCR_UART0_SCLK_DIV_B_V  0x0000003FU
+#define PCR_UART0_SCLK_DIV_B_S  6
+/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_NUM    0x000000FFU
+#define PCR_UART0_SCLK_DIV_NUM_M  (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S)
+#define PCR_UART0_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_UART0_SCLK_DIV_NUM_S  12
+/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_UART0_SCLK_SEL    0x00000003U
+#define PCR_UART0_SCLK_SEL_M  (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
+#define PCR_UART0_SCLK_SEL_V  0x00000003U
+#define PCR_UART0_SCLK_SEL_S  20
+/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable uart0 function clock
+ */
+#define PCR_UART0_SCLK_EN    (BIT(22))
+#define PCR_UART0_SCLK_EN_M  (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S)
+#define PCR_UART0_SCLK_EN_V  0x00000001U
+#define PCR_UART0_SCLK_EN_S  22
+
+/** PCR_UART0_PD_CTRL_REG register
+ *  UART0 power control register
+ */
+#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)
+/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power down UART0 memory.
+ */
+#define PCR_UART0_MEM_FORCE_PU    (BIT(1))
+#define PCR_UART0_MEM_FORCE_PU_M  (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S)
+#define PCR_UART0_MEM_FORCE_PU_V  0x00000001U
+#define PCR_UART0_MEM_FORCE_PU_S  1
+/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power up UART0 memory.
+ */
+#define PCR_UART0_MEM_FORCE_PD    (BIT(2))
+#define PCR_UART0_MEM_FORCE_PD_M  (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S)
+#define PCR_UART0_MEM_FORCE_PD_V  0x00000001U
+#define PCR_UART0_MEM_FORCE_PD_S  2
+
+/** PCR_UART1_CONF_REG register
+ *  UART1 configuration register
+ */
+#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)
+/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uart1 apb clock
+ */
+#define PCR_UART1_CLK_EN    (BIT(0))
+#define PCR_UART1_CLK_EN_M  (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S)
+#define PCR_UART1_CLK_EN_V  0x00000001U
+#define PCR_UART1_CLK_EN_S  0
+/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uart1 module
+ */
+#define PCR_UART1_RST_EN    (BIT(1))
+#define PCR_UART1_RST_EN_M  (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
+#define PCR_UART1_RST_EN_V  0x00000001U
+#define PCR_UART1_RST_EN_S  1
+
+/** PCR_UART1_SCLK_CONF_REG register
+ *  UART1_SCLK configuration register
+ */
+#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)
+/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_A    0x0000003FU
+#define PCR_UART1_SCLK_DIV_A_M  (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S)
+#define PCR_UART1_SCLK_DIV_A_V  0x0000003FU
+#define PCR_UART1_SCLK_DIV_A_S  0
+/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_B    0x0000003FU
+#define PCR_UART1_SCLK_DIV_B_M  (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S)
+#define PCR_UART1_SCLK_DIV_B_V  0x0000003FU
+#define PCR_UART1_SCLK_DIV_B_S  6
+/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_NUM    0x000000FFU
+#define PCR_UART1_SCLK_DIV_NUM_M  (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S)
+#define PCR_UART1_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_UART1_SCLK_DIV_NUM_S  12
+/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_UART1_SCLK_SEL    0x00000003U
+#define PCR_UART1_SCLK_SEL_M  (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
+#define PCR_UART1_SCLK_SEL_V  0x00000003U
+#define PCR_UART1_SCLK_SEL_S  20
+/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable uart0 function clock
+ */
+#define PCR_UART1_SCLK_EN    (BIT(22))
+#define PCR_UART1_SCLK_EN_M  (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S)
+#define PCR_UART1_SCLK_EN_V  0x00000001U
+#define PCR_UART1_SCLK_EN_S  22
+
+/** PCR_UART1_PD_CTRL_REG register
+ *  UART1 power control register
+ */
+#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)
+/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power down UART1 memory.
+ */
+#define PCR_UART1_MEM_FORCE_PU    (BIT(1))
+#define PCR_UART1_MEM_FORCE_PU_M  (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S)
+#define PCR_UART1_MEM_FORCE_PU_V  0x00000001U
+#define PCR_UART1_MEM_FORCE_PU_S  1
+/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power up UART1 memory.
+ */
+#define PCR_UART1_MEM_FORCE_PD    (BIT(2))
+#define PCR_UART1_MEM_FORCE_PD_M  (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S)
+#define PCR_UART1_MEM_FORCE_PD_V  0x00000001U
+#define PCR_UART1_MEM_FORCE_PD_S  2
+
+/** PCR_MSPI_CONF_REG register
+ *  MSPI configuration register
+ */
+#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)
+/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable mspi clock, include mspi pll clock
+ */
+#define PCR_MSPI_CLK_EN    (BIT(0))
+#define PCR_MSPI_CLK_EN_M  (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S)
+#define PCR_MSPI_CLK_EN_V  0x00000001U
+#define PCR_MSPI_CLK_EN_S  0
+/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset mspi module
+ */
+#define PCR_MSPI_RST_EN    (BIT(1))
+#define PCR_MSPI_RST_EN_M  (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
+#define PCR_MSPI_RST_EN_V  0x00000001U
+#define PCR_MSPI_RST_EN_S  1
+/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable mspi pll clock
+ */
+#define PCR_MSPI_PLL_CLK_EN    (BIT(2))
+#define PCR_MSPI_PLL_CLK_EN_M  (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S)
+#define PCR_MSPI_PLL_CLK_EN_V  0x00000001U
+#define PCR_MSPI_PLL_CLK_EN_S  2
+
+/** PCR_MSPI_CLK_CONF_REG register
+ *  MSPI_CLK configuration register
+ */
+#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
+/** PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
+ *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
+ *  low-speed clock-source such as XTAL/FOSC.
+ */
+#define PCR_MSPI_FAST_LS_DIV_NUM    0x000000FFU
+#define PCR_MSPI_FAST_LS_DIV_NUM_M  (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S)
+#define PCR_MSPI_FAST_LS_DIV_NUM_V  0x000000FFU
+#define PCR_MSPI_FAST_LS_DIV_NUM_S  0
+/** PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
+ *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
+ *  high-speed clock-source such as SPLL.
+ */
+#define PCR_MSPI_FAST_HS_DIV_NUM    0x000000FFU
+#define PCR_MSPI_FAST_HS_DIV_NUM_M  (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S)
+#define PCR_MSPI_FAST_HS_DIV_NUM_V  0x000000FFU
+#define PCR_MSPI_FAST_HS_DIV_NUM_S  8
+
+/** PCR_I2C_CONF_REG register
+ *  I2C configuration register
+ */
+#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20)
+/** PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable i2c apb clock
+ */
+#define PCR_I2C_CLK_EN    (BIT(0))
+#define PCR_I2C_CLK_EN_M  (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S)
+#define PCR_I2C_CLK_EN_V  0x00000001U
+#define PCR_I2C_CLK_EN_S  0
+/** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset i2c module
+ */
+#define PCR_I2C_RST_EN    (BIT(1))
+#define PCR_I2C_RST_EN_M  (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S)
+#define PCR_I2C_RST_EN_V  0x00000001U
+#define PCR_I2C_RST_EN_S  1
+
+/** PCR_I2C_SCLK_CONF_REG register
+ *  I2C_SCLK configuration register
+ */
+#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)
+/** PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C_SCLK_DIV_A    0x0000003FU
+#define PCR_I2C_SCLK_DIV_A_M  (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S)
+#define PCR_I2C_SCLK_DIV_A_V  0x0000003FU
+#define PCR_I2C_SCLK_DIV_A_S  0
+/** PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C_SCLK_DIV_B    0x0000003FU
+#define PCR_I2C_SCLK_DIV_B_M  (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S)
+#define PCR_I2C_SCLK_DIV_B_V  0x0000003FU
+#define PCR_I2C_SCLK_DIV_B_S  6
+/** PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C_SCLK_DIV_NUM    0x000000FFU
+#define PCR_I2C_SCLK_DIV_NUM_M  (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S)
+#define PCR_I2C_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_I2C_SCLK_DIV_NUM_S  12
+/** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_I2C_SCLK_SEL    (BIT(20))
+#define PCR_I2C_SCLK_SEL_M  (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S)
+#define PCR_I2C_SCLK_SEL_V  0x00000001U
+#define PCR_I2C_SCLK_SEL_S  20
+/** PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2c function clock
+ */
+#define PCR_I2C_SCLK_EN    (BIT(22))
+#define PCR_I2C_SCLK_EN_M  (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S)
+#define PCR_I2C_SCLK_EN_V  0x00000001U
+#define PCR_I2C_SCLK_EN_S  22
+
+/** PCR_UHCI_CONF_REG register
+ *  UHCI configuration register
+ */
+#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28)
+/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uhci clock
+ */
+#define PCR_UHCI_CLK_EN    (BIT(0))
+#define PCR_UHCI_CLK_EN_M  (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S)
+#define PCR_UHCI_CLK_EN_V  0x00000001U
+#define PCR_UHCI_CLK_EN_S  0
+/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uhci module
+ */
+#define PCR_UHCI_RST_EN    (BIT(1))
+#define PCR_UHCI_RST_EN_M  (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S)
+#define PCR_UHCI_RST_EN_V  0x00000001U
+#define PCR_UHCI_RST_EN_S  1
+
+/** PCR_RMT_CONF_REG register
+ *  RMT configuration register
+ */
+#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c)
+/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable rmt apb clock
+ */
+#define PCR_RMT_CLK_EN    (BIT(0))
+#define PCR_RMT_CLK_EN_M  (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S)
+#define PCR_RMT_CLK_EN_V  0x00000001U
+#define PCR_RMT_CLK_EN_S  0
+/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset rmt module
+ */
+#define PCR_RMT_RST_EN    (BIT(1))
+#define PCR_RMT_RST_EN_M  (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S)
+#define PCR_RMT_RST_EN_V  0x00000001U
+#define PCR_RMT_RST_EN_S  1
+
+/** PCR_RMT_SCLK_CONF_REG register
+ *  RMT_SCLK configuration register
+ */
+#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30)
+/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_A    0x0000003FU
+#define PCR_RMT_SCLK_DIV_A_M  (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S)
+#define PCR_RMT_SCLK_DIV_A_V  0x0000003FU
+#define PCR_RMT_SCLK_DIV_A_S  0
+/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_B    0x0000003FU
+#define PCR_RMT_SCLK_DIV_B_M  (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S)
+#define PCR_RMT_SCLK_DIV_B_V  0x0000003FU
+#define PCR_RMT_SCLK_DIV_B_S  6
+/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
+ *  The integral part of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_NUM    0x000000FFU
+#define PCR_RMT_SCLK_DIV_NUM_M  (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S)
+#define PCR_RMT_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_RMT_SCLK_DIV_NUM_S  12
+/** PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
+ *  80MHz, 2: FOSC, 3: XTAL.
+ */
+#define PCR_RMT_SCLK_SEL    0x00000003U
+#define PCR_RMT_SCLK_SEL_M  (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S)
+#define PCR_RMT_SCLK_SEL_V  0x00000003U
+#define PCR_RMT_SCLK_SEL_S  20
+/** PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable rmt function clock
+ */
+#define PCR_RMT_SCLK_EN    (BIT(22))
+#define PCR_RMT_SCLK_EN_M  (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S)
+#define PCR_RMT_SCLK_EN_V  0x00000001U
+#define PCR_RMT_SCLK_EN_S  22
+
+/** PCR_LEDC_CONF_REG register
+ *  LEDC configuration register
+ */
+#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34)
+/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ledc apb clock
+ */
+#define PCR_LEDC_CLK_EN    (BIT(0))
+#define PCR_LEDC_CLK_EN_M  (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S)
+#define PCR_LEDC_CLK_EN_V  0x00000001U
+#define PCR_LEDC_CLK_EN_S  0
+/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ledc module
+ */
+#define PCR_LEDC_RST_EN    (BIT(1))
+#define PCR_LEDC_RST_EN_M  (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
+#define PCR_LEDC_RST_EN_V  0x00000001U
+#define PCR_LEDC_RST_EN_S  1
+
+/** PCR_LEDC_SCLK_CONF_REG register
+ *  LEDC_SCLK configuration register
+ */
+#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38)
+/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+ *  80MHz, 2: FOSC, 3: XTAL.
+ */
+#define PCR_LEDC_SCLK_SEL    0x00000003U
+#define PCR_LEDC_SCLK_SEL_M  (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
+#define PCR_LEDC_SCLK_SEL_V  0x00000003U
+#define PCR_LEDC_SCLK_SEL_S  20
+/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable ledc function clock
+ */
+#define PCR_LEDC_SCLK_EN    (BIT(22))
+#define PCR_LEDC_SCLK_EN_M  (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S)
+#define PCR_LEDC_SCLK_EN_V  0x00000001U
+#define PCR_LEDC_SCLK_EN_S  22
+
+/** PCR_TIMERGROUP0_CONF_REG register
+ *  TIMERGROUP0 configuration register
+ */
+#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c)
+/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable timer_group0 apb clock
+ */
+#define PCR_TG0_CLK_EN    (BIT(0))
+#define PCR_TG0_CLK_EN_M  (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S)
+#define PCR_TG0_CLK_EN_V  0x00000001U
+#define PCR_TG0_CLK_EN_S  0
+/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset timer_group0 module
+ */
+#define PCR_TG0_RST_EN    (BIT(1))
+#define PCR_TG0_RST_EN_M  (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
+#define PCR_TG0_RST_EN_V  0x00000001U
+#define PCR_TG0_RST_EN_S  1
+
+/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register
+ *  TIMERGROUP0_TIMER_CLK configuration register
+ */
+#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
+/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG0_TIMER_CLK_SEL    0x00000003U
+#define PCR_TG0_TIMER_CLK_SEL_M  (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
+#define PCR_TG0_TIMER_CLK_SEL_V  0x00000003U
+#define PCR_TG0_TIMER_CLK_SEL_S  20
+/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 timer clock
+ */
+#define PCR_TG0_TIMER_CLK_EN    (BIT(22))
+#define PCR_TG0_TIMER_CLK_EN_M  (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S)
+#define PCR_TG0_TIMER_CLK_EN_V  0x00000001U
+#define PCR_TG0_TIMER_CLK_EN_S  22
+
+/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register
+ *  TIMERGROUP0_WDT_CLK configuration register
+ */
+#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44)
+/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG0_WDT_CLK_SEL    0x00000003U
+#define PCR_TG0_WDT_CLK_SEL_M  (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
+#define PCR_TG0_WDT_CLK_SEL_V  0x00000003U
+#define PCR_TG0_WDT_CLK_SEL_S  20
+/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 wdt clock
+ */
+#define PCR_TG0_WDT_CLK_EN    (BIT(22))
+#define PCR_TG0_WDT_CLK_EN_M  (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S)
+#define PCR_TG0_WDT_CLK_EN_V  0x00000001U
+#define PCR_TG0_WDT_CLK_EN_S  22
+
+/** PCR_TIMERGROUP1_CONF_REG register
+ *  TIMERGROUP1 configuration register
+ */
+#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48)
+/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable timer_group1 apb clock
+ */
+#define PCR_TG1_CLK_EN    (BIT(0))
+#define PCR_TG1_CLK_EN_M  (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S)
+#define PCR_TG1_CLK_EN_V  0x00000001U
+#define PCR_TG1_CLK_EN_S  0
+/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset timer_group1 module
+ */
+#define PCR_TG1_RST_EN    (BIT(1))
+#define PCR_TG1_RST_EN_M  (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
+#define PCR_TG1_RST_EN_V  0x00000001U
+#define PCR_TG1_RST_EN_S  1
+
+/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register
+ *  TIMERGROUP1_TIMER_CLK configuration register
+ */
+#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c)
+/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG1_TIMER_CLK_SEL    0x00000003U
+#define PCR_TG1_TIMER_CLK_SEL_M  (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
+#define PCR_TG1_TIMER_CLK_SEL_V  0x00000003U
+#define PCR_TG1_TIMER_CLK_SEL_S  20
+/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group1 timer clock
+ */
+#define PCR_TG1_TIMER_CLK_EN    (BIT(22))
+#define PCR_TG1_TIMER_CLK_EN_M  (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S)
+#define PCR_TG1_TIMER_CLK_EN_V  0x00000001U
+#define PCR_TG1_TIMER_CLK_EN_S  22
+
+/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register
+ *  TIMERGROUP1_WDT_CLK configuration register
+ */
+#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50)
+/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG1_WDT_CLK_SEL    0x00000003U
+#define PCR_TG1_WDT_CLK_SEL_M  (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
+#define PCR_TG1_WDT_CLK_SEL_V  0x00000003U
+#define PCR_TG1_WDT_CLK_SEL_S  20
+/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 wdt clock
+ */
+#define PCR_TG1_WDT_CLK_EN    (BIT(22))
+#define PCR_TG1_WDT_CLK_EN_M  (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S)
+#define PCR_TG1_WDT_CLK_EN_V  0x00000001U
+#define PCR_TG1_WDT_CLK_EN_S  22
+
+/** PCR_SYSTIMER_CONF_REG register
+ *  SYSTIMER configuration register
+ */
+#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54)
+/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable systimer apb clock
+ */
+#define PCR_SYSTIMER_CLK_EN    (BIT(0))
+#define PCR_SYSTIMER_CLK_EN_M  (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S)
+#define PCR_SYSTIMER_CLK_EN_V  0x00000001U
+#define PCR_SYSTIMER_CLK_EN_S  0
+/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset systimer module
+ */
+#define PCR_SYSTIMER_RST_EN    (BIT(1))
+#define PCR_SYSTIMER_RST_EN_M  (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
+#define PCR_SYSTIMER_RST_EN_V  0x00000001U
+#define PCR_SYSTIMER_RST_EN_S  1
+
+/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register
+ *  SYSTIMER_FUNC_CLK configuration register
+ */
+#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58)
+/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_SYSTIMER_FUNC_CLK_SEL    (BIT(20))
+#define PCR_SYSTIMER_FUNC_CLK_SEL_M  (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
+#define PCR_SYSTIMER_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_SYSTIMER_FUNC_CLK_SEL_S  20
+/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable systimer function clock
+ */
+#define PCR_SYSTIMER_FUNC_CLK_EN    (BIT(22))
+#define PCR_SYSTIMER_FUNC_CLK_EN_M  (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S)
+#define PCR_SYSTIMER_FUNC_CLK_EN_V  0x00000001U
+#define PCR_SYSTIMER_FUNC_CLK_EN_S  22
+
+/** PCR_TWAI0_CONF_REG register
+ *  TWAI0 configuration register
+ */
+#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c)
+/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable twai0 apb clock
+ */
+#define PCR_TWAI0_CLK_EN    (BIT(0))
+#define PCR_TWAI0_CLK_EN_M  (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S)
+#define PCR_TWAI0_CLK_EN_V  0x00000001U
+#define PCR_TWAI0_CLK_EN_S  0
+/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset twai0 module
+ */
+#define PCR_TWAI0_RST_EN    (BIT(1))
+#define PCR_TWAI0_RST_EN_M  (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S)
+#define PCR_TWAI0_RST_EN_V  0x00000001U
+#define PCR_TWAI0_RST_EN_S  1
+
+/** PCR_TWAI0_FUNC_CLK_CONF_REG register
+ *  TWAI0_FUNC_CLK configuration register
+ */
+#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60)
+/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_TWAI0_FUNC_CLK_SEL    (BIT(20))
+#define PCR_TWAI0_FUNC_CLK_SEL_M  (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S)
+#define PCR_TWAI0_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_TWAI0_FUNC_CLK_SEL_S  20
+/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable twai0 function clock
+ */
+#define PCR_TWAI0_FUNC_CLK_EN    (BIT(22))
+#define PCR_TWAI0_FUNC_CLK_EN_M  (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S)
+#define PCR_TWAI0_FUNC_CLK_EN_V  0x00000001U
+#define PCR_TWAI0_FUNC_CLK_EN_S  22
+
+/** PCR_TWAI1_CONF_REG register
+ *  TWAI1 configuration register
+ */
+#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64)
+/** PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable twai1 apb clock
+ */
+#define PCR_TWAI1_CLK_EN    (BIT(0))
+#define PCR_TWAI1_CLK_EN_M  (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S)
+#define PCR_TWAI1_CLK_EN_V  0x00000001U
+#define PCR_TWAI1_CLK_EN_S  0
+/** PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset twai1 module
+ */
+#define PCR_TWAI1_RST_EN    (BIT(1))
+#define PCR_TWAI1_RST_EN_M  (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S)
+#define PCR_TWAI1_RST_EN_V  0x00000001U
+#define PCR_TWAI1_RST_EN_S  1
+
+/** PCR_TWAI1_FUNC_CLK_CONF_REG register
+ *  TWAI1_FUNC_CLK configuration register
+ */
+#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68)
+/** PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_TWAI1_FUNC_CLK_SEL    (BIT(20))
+#define PCR_TWAI1_FUNC_CLK_SEL_M  (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S)
+#define PCR_TWAI1_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_TWAI1_FUNC_CLK_SEL_S  20
+/** PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable twai1 function clock
+ */
+#define PCR_TWAI1_FUNC_CLK_EN    (BIT(22))
+#define PCR_TWAI1_FUNC_CLK_EN_M  (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S)
+#define PCR_TWAI1_FUNC_CLK_EN_V  0x00000001U
+#define PCR_TWAI1_FUNC_CLK_EN_S  22
+
+/** PCR_I2S_CONF_REG register
+ *  I2S configuration register
+ */
+#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c)
+/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable i2s apb clock
+ */
+#define PCR_I2S_CLK_EN    (BIT(0))
+#define PCR_I2S_CLK_EN_M  (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S)
+#define PCR_I2S_CLK_EN_V  0x00000001U
+#define PCR_I2S_CLK_EN_S  0
+/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset i2s module
+ */
+#define PCR_I2S_RST_EN    (BIT(1))
+#define PCR_I2S_RST_EN_M  (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
+#define PCR_I2S_RST_EN_V  0x00000001U
+#define PCR_I2S_RST_EN_S  1
+
+/** PCR_I2S_TX_CLKM_CONF_REG register
+ *  I2S_TX_CLKM configuration register
+ */
+#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70)
+/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
+ *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
+ *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
+ *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+ *  (n+1)-div] + y * (n+1)-div.
+ */
+#define PCR_I2S_TX_CLKM_DIV_NUM    0x000000FFU
+#define PCR_I2S_TX_CLKM_DIV_NUM_M  (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S)
+#define PCR_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_I2S_TX_CLKM_DIV_NUM_S  12
+/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+ *  I2S_MCLK_in.
+ */
+#define PCR_I2S_TX_CLKM_SEL    0x00000003U
+#define PCR_I2S_TX_CLKM_SEL_M  (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
+#define PCR_I2S_TX_CLKM_SEL_V  0x00000003U
+#define PCR_I2S_TX_CLKM_SEL_S  20
+/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2s_tx function clock
+ */
+#define PCR_I2S_TX_CLKM_EN    (BIT(22))
+#define PCR_I2S_TX_CLKM_EN_M  (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S)
+#define PCR_I2S_TX_CLKM_EN_V  0x00000001U
+#define PCR_I2S_TX_CLKM_EN_S  22
+
+/** PCR_I2S_TX_CLKM_DIV_CONF_REG register
+ *  I2S_TX_CLKM_DIV configuration register
+ */
+#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74)
+/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Z is (a-b).
+ */
+#define PCR_I2S_TX_CLKM_DIV_Z    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Z_M  (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S)
+#define PCR_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Z_S  0
+/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define PCR_I2S_TX_CLKM_DIV_Y    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Y_M  (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S)
+#define PCR_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Y_S  9
+/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define PCR_I2S_TX_CLKM_DIV_X    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_X_M  (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S)
+#define PCR_I2S_TX_CLKM_DIV_X_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_X_S  18
+/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_YN1 is 1.
+ */
+#define PCR_I2S_TX_CLKM_DIV_YN1    (BIT(27))
+#define PCR_I2S_TX_CLKM_DIV_YN1_M  (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S)
+#define PCR_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
+#define PCR_I2S_TX_CLKM_DIV_YN1_S  27
+
+/** PCR_I2S_RX_CLKM_CONF_REG register
+ *  I2S_RX_CLKM configuration register
+ */
+#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78)
+/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
+ *  Integral I2S clock divider value
+ */
+#define PCR_I2S_RX_CLKM_DIV_NUM    0x000000FFU
+#define PCR_I2S_RX_CLKM_DIV_NUM_M  (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S)
+#define PCR_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_I2S_RX_CLKM_DIV_NUM_S  12
+/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+ */
+#define PCR_I2S_RX_CLKM_SEL    0x00000003U
+#define PCR_I2S_RX_CLKM_SEL_M  (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
+#define PCR_I2S_RX_CLKM_SEL_V  0x00000003U
+#define PCR_I2S_RX_CLKM_SEL_S  20
+/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2s_rx function clock
+ */
+#define PCR_I2S_RX_CLKM_EN    (BIT(22))
+#define PCR_I2S_RX_CLKM_EN_M  (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S)
+#define PCR_I2S_RX_CLKM_EN_V  0x00000001U
+#define PCR_I2S_RX_CLKM_EN_S  22
+/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
+ *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
+ */
+#define PCR_I2S_MCLK_SEL    (BIT(23))
+#define PCR_I2S_MCLK_SEL_M  (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
+#define PCR_I2S_MCLK_SEL_V  0x00000001U
+#define PCR_I2S_MCLK_SEL_S  23
+
+/** PCR_I2S_RX_CLKM_DIV_CONF_REG register
+ *  I2S_RX_CLKM_DIV configuration register
+ */
+#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c)
+/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Z is (a-b).
+ */
+#define PCR_I2S_RX_CLKM_DIV_Z    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Z_M  (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S)
+#define PCR_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Z_S  0
+/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define PCR_I2S_RX_CLKM_DIV_Y    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Y_M  (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S)
+#define PCR_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Y_S  9
+/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define PCR_I2S_RX_CLKM_DIV_X    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_X_M  (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S)
+#define PCR_I2S_RX_CLKM_DIV_X_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_X_S  18
+/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_YN1 is 1.
+ */
+#define PCR_I2S_RX_CLKM_DIV_YN1    (BIT(27))
+#define PCR_I2S_RX_CLKM_DIV_YN1_M  (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S)
+#define PCR_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
+#define PCR_I2S_RX_CLKM_DIV_YN1_S  27
+
+/** PCR_SARADC_CONF_REG register
+ *  SARADC configuration register
+ */
+#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80)
+/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  no use
+ */
+#define PCR_SARADC_CLK_EN    (BIT(0))
+#define PCR_SARADC_CLK_EN_M  (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S)
+#define PCR_SARADC_CLK_EN_V  0x00000001U
+#define PCR_SARADC_CLK_EN_S  0
+/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset function_register of saradc module
+ */
+#define PCR_SARADC_RST_EN    (BIT(1))
+#define PCR_SARADC_RST_EN_M  (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
+#define PCR_SARADC_RST_EN_V  0x00000001U
+#define PCR_SARADC_RST_EN_S  1
+/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable saradc apb clock
+ */
+#define PCR_SARADC_REG_CLK_EN    (BIT(2))
+#define PCR_SARADC_REG_CLK_EN_M  (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S)
+#define PCR_SARADC_REG_CLK_EN_V  0x00000001U
+#define PCR_SARADC_REG_CLK_EN_S  2
+/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  Set 0 to reset apb_register of saradc module
+ */
+#define PCR_SARADC_REG_RST_EN    (BIT(3))
+#define PCR_SARADC_REG_RST_EN_M  (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
+#define PCR_SARADC_REG_RST_EN_V  0x00000001U
+#define PCR_SARADC_REG_RST_EN_S  3
+
+/** PCR_SARADC_CLKM_CONF_REG register
+ *  SARADC_CLKM configuration register
+ */
+#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84)
+/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_A    0x0000003FU
+#define PCR_SARADC_CLKM_DIV_A_M  (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S)
+#define PCR_SARADC_CLKM_DIV_A_V  0x0000003FU
+#define PCR_SARADC_CLKM_DIV_A_S  0
+/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_B    0x0000003FU
+#define PCR_SARADC_CLKM_DIV_B_M  (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S)
+#define PCR_SARADC_CLKM_DIV_B_V  0x0000003FU
+#define PCR_SARADC_CLKM_DIV_B_S  6
+/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
+ *  The integral part of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_NUM    0x000000FFU
+#define PCR_SARADC_CLKM_DIV_NUM_M  (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S)
+#define PCR_SARADC_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_SARADC_CLKM_DIV_NUM_S  12
+/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_SARADC_CLKM_SEL    0x00000003U
+#define PCR_SARADC_CLKM_SEL_M  (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
+#define PCR_SARADC_CLKM_SEL_V  0x00000003U
+#define PCR_SARADC_CLKM_SEL_S  20
+/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable saradc function clock
+ */
+#define PCR_SARADC_CLKM_EN    (BIT(22))
+#define PCR_SARADC_CLKM_EN_M  (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S)
+#define PCR_SARADC_CLKM_EN_V  0x00000001U
+#define PCR_SARADC_CLKM_EN_S  22
+
+/** PCR_TSENS_CLK_CONF_REG register
+ *  TSENS_CLK configuration register
+ */
+#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88)
+/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
+ */
+#define PCR_TSENS_CLK_SEL    (BIT(20))
+#define PCR_TSENS_CLK_SEL_M  (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
+#define PCR_TSENS_CLK_SEL_V  0x00000001U
+#define PCR_TSENS_CLK_SEL_S  20
+/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable tsens clock
+ */
+#define PCR_TSENS_CLK_EN    (BIT(22))
+#define PCR_TSENS_CLK_EN_M  (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S)
+#define PCR_TSENS_CLK_EN_V  0x00000001U
+#define PCR_TSENS_CLK_EN_S  22
+/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
+ *  Set 0 to reset tsens module
+ */
+#define PCR_TSENS_RST_EN    (BIT(23))
+#define PCR_TSENS_RST_EN_M  (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
+#define PCR_TSENS_RST_EN_V  0x00000001U
+#define PCR_TSENS_RST_EN_S  23
+
+/** PCR_USB_DEVICE_CONF_REG register
+ *  USB_DEVICE configuration register
+ */
+#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c)
+/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable usb_device clock
+ */
+#define PCR_USB_DEVICE_CLK_EN    (BIT(0))
+#define PCR_USB_DEVICE_CLK_EN_M  (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S)
+#define PCR_USB_DEVICE_CLK_EN_V  0x00000001U
+#define PCR_USB_DEVICE_CLK_EN_S  0
+/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset usb_device module
+ */
+#define PCR_USB_DEVICE_RST_EN    (BIT(1))
+#define PCR_USB_DEVICE_RST_EN_M  (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
+#define PCR_USB_DEVICE_RST_EN_V  0x00000001U
+#define PCR_USB_DEVICE_RST_EN_S  1
+
+/** PCR_INTMTX_CONF_REG register
+ *  INTMTX configuration register
+ */
+#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90)
+/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable intmtx clock
+ */
+#define PCR_INTMTX_CLK_EN    (BIT(0))
+#define PCR_INTMTX_CLK_EN_M  (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S)
+#define PCR_INTMTX_CLK_EN_V  0x00000001U
+#define PCR_INTMTX_CLK_EN_S  0
+/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset intmtx module
+ */
+#define PCR_INTMTX_RST_EN    (BIT(1))
+#define PCR_INTMTX_RST_EN_M  (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
+#define PCR_INTMTX_RST_EN_V  0x00000001U
+#define PCR_INTMTX_RST_EN_S  1
+
+/** PCR_PCNT_CONF_REG register
+ *  PCNT configuration register
+ */
+#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94)
+/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable pcnt clock
+ */
+#define PCR_PCNT_CLK_EN    (BIT(0))
+#define PCR_PCNT_CLK_EN_M  (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S)
+#define PCR_PCNT_CLK_EN_V  0x00000001U
+#define PCR_PCNT_CLK_EN_S  0
+/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset pcnt module
+ */
+#define PCR_PCNT_RST_EN    (BIT(1))
+#define PCR_PCNT_RST_EN_M  (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S)
+#define PCR_PCNT_RST_EN_V  0x00000001U
+#define PCR_PCNT_RST_EN_S  1
+
+/** PCR_ETM_CONF_REG register
+ *  ETM configuration register
+ */
+#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98)
+/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable etm clock
+ */
+#define PCR_ETM_CLK_EN    (BIT(0))
+#define PCR_ETM_CLK_EN_M  (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S)
+#define PCR_ETM_CLK_EN_V  0x00000001U
+#define PCR_ETM_CLK_EN_S  0
+/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset etm module
+ */
+#define PCR_ETM_RST_EN    (BIT(1))
+#define PCR_ETM_RST_EN_M  (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
+#define PCR_ETM_RST_EN_V  0x00000001U
+#define PCR_ETM_RST_EN_S  1
+
+/** PCR_PWM_CONF_REG register
+ *  PWM configuration register
+ */
+#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c)
+/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable pwm clock
+ */
+#define PCR_PWM_CLK_EN    (BIT(0))
+#define PCR_PWM_CLK_EN_M  (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S)
+#define PCR_PWM_CLK_EN_V  0x00000001U
+#define PCR_PWM_CLK_EN_S  0
+/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset pwm module
+ */
+#define PCR_PWM_RST_EN    (BIT(1))
+#define PCR_PWM_RST_EN_M  (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S)
+#define PCR_PWM_RST_EN_V  0x00000001U
+#define PCR_PWM_RST_EN_S  1
+
+/** PCR_PWM_CLK_CONF_REG register
+ *  PWM_CLK configuration register
+ */
+#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0)
+/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
+ *  The integral part of the frequency divider factor of the pwm function clock.
+ */
+#define PCR_PWM_DIV_NUM    0x000000FFU
+#define PCR_PWM_DIV_NUM_M  (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S)
+#define PCR_PWM_DIV_NUM_V  0x000000FFU
+#define PCR_PWM_DIV_NUM_S  12
+/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+ *  160MHz, 2: XTAL, 3: FOSC.
+ */
+#define PCR_PWM_CLKM_SEL    0x00000003U
+#define PCR_PWM_CLKM_SEL_M  (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S)
+#define PCR_PWM_CLKM_SEL_V  0x00000003U
+#define PCR_PWM_CLKM_SEL_S  20
+/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  set this field as 1 to activate pwm clkm.
+ */
+#define PCR_PWM_CLKM_EN    (BIT(22))
+#define PCR_PWM_CLKM_EN_M  (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S)
+#define PCR_PWM_CLKM_EN_V  0x00000001U
+#define PCR_PWM_CLKM_EN_S  22
+
+/** PCR_PARL_IO_CONF_REG register
+ *  PARL_IO configuration register
+ */
+#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4)
+/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable parl apb clock
+ */
+#define PCR_PARL_CLK_EN    (BIT(0))
+#define PCR_PARL_CLK_EN_M  (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S)
+#define PCR_PARL_CLK_EN_V  0x00000001U
+#define PCR_PARL_CLK_EN_S  0
+/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset parl apb reg
+ */
+#define PCR_PARL_RST_EN    (BIT(1))
+#define PCR_PARL_RST_EN_M  (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S)
+#define PCR_PARL_RST_EN_V  0x00000001U
+#define PCR_PARL_RST_EN_S  1
+
+/** PCR_PARL_CLK_RX_CONF_REG register
+ *  PARL_CLK_RX configuration register
+ */
+#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8)
+/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  The integral part of the frequency divider factor of the parl rx clock.
+ */
+#define PCR_PARL_CLK_RX_DIV_NUM    0x0000FFFFU
+#define PCR_PARL_CLK_RX_DIV_NUM_M  (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S)
+#define PCR_PARL_CLK_RX_DIV_NUM_V  0x0000FFFFU
+#define PCR_PARL_CLK_RX_DIV_NUM_S  0
+/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  user clock from pad.
+ */
+#define PCR_PARL_CLK_RX_SEL    0x00000003U
+#define PCR_PARL_CLK_RX_SEL_M  (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S)
+#define PCR_PARL_CLK_RX_SEL_V  0x00000003U
+#define PCR_PARL_CLK_RX_SEL_S  16
+/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1;
+ *  Set 1 to enable parl rx clock
+ */
+#define PCR_PARL_CLK_RX_EN    (BIT(18))
+#define PCR_PARL_CLK_RX_EN_M  (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S)
+#define PCR_PARL_CLK_RX_EN_V  0x00000001U
+#define PCR_PARL_CLK_RX_EN_S  18
+/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0;
+ *  Set 0 to reset parl rx module
+ */
+#define PCR_PARL_RX_RST_EN    (BIT(19))
+#define PCR_PARL_RX_RST_EN_M  (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S)
+#define PCR_PARL_RX_RST_EN_V  0x00000001U
+#define PCR_PARL_RX_RST_EN_S  19
+
+/** PCR_PARL_CLK_TX_CONF_REG register
+ *  PARL_CLK_TX configuration register
+ */
+#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac)
+/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  The integral part of the frequency divider factor of the parl tx clock.
+ */
+#define PCR_PARL_CLK_TX_DIV_NUM    0x0000FFFFU
+#define PCR_PARL_CLK_TX_DIV_NUM_M  (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S)
+#define PCR_PARL_CLK_TX_DIV_NUM_V  0x0000FFFFU
+#define PCR_PARL_CLK_TX_DIV_NUM_S  0
+/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  user clock from pad.
+ */
+#define PCR_PARL_CLK_TX_SEL    0x00000003U
+#define PCR_PARL_CLK_TX_SEL_M  (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S)
+#define PCR_PARL_CLK_TX_SEL_V  0x00000003U
+#define PCR_PARL_CLK_TX_SEL_S  16
+/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1;
+ *  Set 1 to enable parl tx clock
+ */
+#define PCR_PARL_CLK_TX_EN    (BIT(18))
+#define PCR_PARL_CLK_TX_EN_M  (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S)
+#define PCR_PARL_CLK_TX_EN_V  0x00000001U
+#define PCR_PARL_CLK_TX_EN_S  18
+/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0;
+ *  Set 0 to reset parl tx module
+ */
+#define PCR_PARL_TX_RST_EN    (BIT(19))
+#define PCR_PARL_TX_RST_EN_M  (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S)
+#define PCR_PARL_TX_RST_EN_V  0x00000001U
+#define PCR_PARL_TX_RST_EN_S  19
+
+/** PCR_SDIO_SLAVE_CONF_REG register
+ *  SDIO_SLAVE configuration register
+ */
+#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0)
+/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable sdio_slave clock
+ */
+#define PCR_SDIO_SLAVE_CLK_EN    (BIT(0))
+#define PCR_SDIO_SLAVE_CLK_EN_M  (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S)
+#define PCR_SDIO_SLAVE_CLK_EN_V  0x00000001U
+#define PCR_SDIO_SLAVE_CLK_EN_S  0
+/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset sdio_slave module
+ */
+#define PCR_SDIO_SLAVE_RST_EN    (BIT(1))
+#define PCR_SDIO_SLAVE_RST_EN_M  (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S)
+#define PCR_SDIO_SLAVE_RST_EN_V  0x00000001U
+#define PCR_SDIO_SLAVE_RST_EN_S  1
+
+/** PCR_PVT_MONITOR_CONF_REG register
+ *  PVT_MONITOR configuration register
+ */
+#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4)
+/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable apb clock of pvt module
+ */
+#define PCR_PVT_MONITOR_CLK_EN    (BIT(0))
+#define PCR_PVT_MONITOR_CLK_EN_M  (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S)
+#define PCR_PVT_MONITOR_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_CLK_EN_S  0
+/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset all pvt monitor module
+ */
+#define PCR_PVT_MONITOR_RST_EN    (BIT(1))
+#define PCR_PVT_MONITOR_RST_EN_M  (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S)
+#define PCR_PVT_MONITOR_RST_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_RST_EN_S  1
+/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable function clock of modem pvt module
+ */
+#define PCR_PVT_MONITOR_SITE1_CLK_EN    (BIT(2))
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_M  (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_S  2
+/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to enable function clock of cpu pvt module
+ */
+#define PCR_PVT_MONITOR_SITE2_CLK_EN    (BIT(3))
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_M  (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_S  3
+/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Set 1 to enable function clock of hp_peri pvt module
+ */
+#define PCR_PVT_MONITOR_SITE3_CLK_EN    (BIT(4))
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_M  (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_S  4
+
+/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register
+ *  PVT_MONITOR function clock configuration register
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8)
+/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0;
+ *  The integral part of the frequency divider factor of the pvt_monitor function clock.
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM    0x0000000FU
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M  (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
+/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
+ *  divided by 3.
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M  (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S  20
+/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable source clock of pvt sitex
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_EN    (BIT(22))
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_M  (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_S  22
+
+/** PCR_GDMA_CONF_REG register
+ *  GDMA configuration register
+ */
+#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc)
+/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable gdma clock
+ */
+#define PCR_GDMA_CLK_EN    (BIT(0))
+#define PCR_GDMA_CLK_EN_M  (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S)
+#define PCR_GDMA_CLK_EN_V  0x00000001U
+#define PCR_GDMA_CLK_EN_S  0
+/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset gdma module
+ */
+#define PCR_GDMA_RST_EN    (BIT(1))
+#define PCR_GDMA_RST_EN_M  (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
+#define PCR_GDMA_RST_EN_V  0x00000001U
+#define PCR_GDMA_RST_EN_S  1
+
+/** PCR_SPI2_CONF_REG register
+ *  SPI2 configuration register
+ */
+#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0)
+/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable spi2 apb clock
+ */
+#define PCR_SPI2_CLK_EN    (BIT(0))
+#define PCR_SPI2_CLK_EN_M  (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S)
+#define PCR_SPI2_CLK_EN_V  0x00000001U
+#define PCR_SPI2_CLK_EN_S  0
+/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset spi2 module
+ */
+#define PCR_SPI2_RST_EN    (BIT(1))
+#define PCR_SPI2_RST_EN_M  (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
+#define PCR_SPI2_RST_EN_V  0x00000001U
+#define PCR_SPI2_RST_EN_S  1
+
+/** PCR_SPI2_CLKM_CONF_REG register
+ *  SPI2_CLKM configuration register
+ */
+#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4)
+/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_SPI2_CLKM_SEL    0x00000003U
+#define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
+#define PCR_SPI2_CLKM_SEL_V  0x00000003U
+#define PCR_SPI2_CLKM_SEL_S  20
+/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable spi2 function clock
+ */
+#define PCR_SPI2_CLKM_EN    (BIT(22))
+#define PCR_SPI2_CLKM_EN_M  (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S)
+#define PCR_SPI2_CLKM_EN_V  0x00000001U
+#define PCR_SPI2_CLKM_EN_S  22
+
+/** PCR_AES_CONF_REG register
+ *  AES configuration register
+ */
+#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8)
+/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable aes clock
+ */
+#define PCR_AES_CLK_EN    (BIT(0))
+#define PCR_AES_CLK_EN_M  (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
+#define PCR_AES_CLK_EN_V  0x00000001U
+#define PCR_AES_CLK_EN_S  0
+/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset aes module
+ */
+#define PCR_AES_RST_EN    (BIT(1))
+#define PCR_AES_RST_EN_M  (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
+#define PCR_AES_RST_EN_V  0x00000001U
+#define PCR_AES_RST_EN_S  1
+
+/** PCR_SHA_CONF_REG register
+ *  SHA configuration register
+ */
+#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc)
+/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable sha clock
+ */
+#define PCR_SHA_CLK_EN    (BIT(0))
+#define PCR_SHA_CLK_EN_M  (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S)
+#define PCR_SHA_CLK_EN_V  0x00000001U
+#define PCR_SHA_CLK_EN_S  0
+/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset sha module
+ */
+#define PCR_SHA_RST_EN    (BIT(1))
+#define PCR_SHA_RST_EN_M  (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
+#define PCR_SHA_RST_EN_V  0x00000001U
+#define PCR_SHA_RST_EN_S  1
+
+/** PCR_RSA_CONF_REG register
+ *  RSA configuration register
+ */
+#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0)
+/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable rsa clock
+ */
+#define PCR_RSA_CLK_EN    (BIT(0))
+#define PCR_RSA_CLK_EN_M  (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
+#define PCR_RSA_CLK_EN_V  0x00000001U
+#define PCR_RSA_CLK_EN_S  0
+/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset rsa module
+ */
+#define PCR_RSA_RST_EN    (BIT(1))
+#define PCR_RSA_RST_EN_M  (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
+#define PCR_RSA_RST_EN_V  0x00000001U
+#define PCR_RSA_RST_EN_S  1
+
+/** PCR_RSA_PD_CTRL_REG register
+ *  RSA power control register
+ */
+#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4)
+/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down rsa internal memory.
+ */
+#define PCR_RSA_MEM_PD    (BIT(0))
+#define PCR_RSA_MEM_PD_M  (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
+#define PCR_RSA_MEM_PD_V  0x00000001U
+#define PCR_RSA_MEM_PD_S  0
+/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up rsa internal memory
+ */
+#define PCR_RSA_MEM_FORCE_PU    (BIT(1))
+#define PCR_RSA_MEM_FORCE_PU_M  (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
+#define PCR_RSA_MEM_FORCE_PU_V  0x00000001U
+#define PCR_RSA_MEM_FORCE_PU_S  1
+/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down rsa internal memory.
+ */
+#define PCR_RSA_MEM_FORCE_PD    (BIT(2))
+#define PCR_RSA_MEM_FORCE_PD_M  (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
+#define PCR_RSA_MEM_FORCE_PD_V  0x00000001U
+#define PCR_RSA_MEM_FORCE_PD_S  2
+
+/** PCR_ECC_CONF_REG register
+ *  ECC configuration register
+ */
+#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8)
+/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ecc clock
+ */
+#define PCR_ECC_CLK_EN    (BIT(0))
+#define PCR_ECC_CLK_EN_M  (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S)
+#define PCR_ECC_CLK_EN_V  0x00000001U
+#define PCR_ECC_CLK_EN_S  0
+/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ecc module
+ */
+#define PCR_ECC_RST_EN    (BIT(1))
+#define PCR_ECC_RST_EN_M  (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
+#define PCR_ECC_RST_EN_V  0x00000001U
+#define PCR_ECC_RST_EN_S  1
+
+/** PCR_ECC_PD_CTRL_REG register
+ *  ECC power control register
+ */
+#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc)
+/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down ecc internal memory.
+ */
+#define PCR_ECC_MEM_PD    (BIT(0))
+#define PCR_ECC_MEM_PD_M  (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S)
+#define PCR_ECC_MEM_PD_V  0x00000001U
+#define PCR_ECC_MEM_PD_S  0
+/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up ecc internal memory
+ */
+#define PCR_ECC_MEM_FORCE_PU    (BIT(1))
+#define PCR_ECC_MEM_FORCE_PU_M  (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S)
+#define PCR_ECC_MEM_FORCE_PU_V  0x00000001U
+#define PCR_ECC_MEM_FORCE_PU_S  1
+/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down ecc internal memory.
+ */
+#define PCR_ECC_MEM_FORCE_PD    (BIT(2))
+#define PCR_ECC_MEM_FORCE_PD_M  (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S)
+#define PCR_ECC_MEM_FORCE_PD_V  0x00000001U
+#define PCR_ECC_MEM_FORCE_PD_S  2
+
+/** PCR_DS_CONF_REG register
+ *  DS configuration register
+ */
+#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0)
+/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ds clock
+ */
+#define PCR_DS_CLK_EN    (BIT(0))
+#define PCR_DS_CLK_EN_M  (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
+#define PCR_DS_CLK_EN_V  0x00000001U
+#define PCR_DS_CLK_EN_S  0
+/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ds module
+ */
+#define PCR_DS_RST_EN    (BIT(1))
+#define PCR_DS_RST_EN_M  (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
+#define PCR_DS_RST_EN_V  0x00000001U
+#define PCR_DS_RST_EN_S  1
+
+/** PCR_HMAC_CONF_REG register
+ *  HMAC configuration register
+ */
+#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4)
+/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable hmac clock
+ */
+#define PCR_HMAC_CLK_EN    (BIT(0))
+#define PCR_HMAC_CLK_EN_M  (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
+#define PCR_HMAC_CLK_EN_V  0x00000001U
+#define PCR_HMAC_CLK_EN_S  0
+/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset hmac module
+ */
+#define PCR_HMAC_RST_EN    (BIT(1))
+#define PCR_HMAC_RST_EN_M  (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
+#define PCR_HMAC_RST_EN_V  0x00000001U
+#define PCR_HMAC_RST_EN_S  1
+
+/** PCR_IOMUX_CONF_REG register
+ *  IOMUX configuration register
+ */
+#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8)
+/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable iomux apb clock
+ */
+#define PCR_IOMUX_CLK_EN    (BIT(0))
+#define PCR_IOMUX_CLK_EN_M  (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S)
+#define PCR_IOMUX_CLK_EN_V  0x00000001U
+#define PCR_IOMUX_CLK_EN_S  0
+/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset iomux module
+ */
+#define PCR_IOMUX_RST_EN    (BIT(1))
+#define PCR_IOMUX_RST_EN_M  (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
+#define PCR_IOMUX_RST_EN_V  0x00000001U
+#define PCR_IOMUX_RST_EN_S  1
+
+/** PCR_IOMUX_CLK_CONF_REG register
+ *  IOMUX_CLK configuration register
+ */
+#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec)
+/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_IOMUX_FUNC_CLK_SEL    0x00000003U
+#define PCR_IOMUX_FUNC_CLK_SEL_M  (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
+#define PCR_IOMUX_FUNC_CLK_SEL_V  0x00000003U
+#define PCR_IOMUX_FUNC_CLK_SEL_S  20
+/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable iomux function clock
+ */
+#define PCR_IOMUX_FUNC_CLK_EN    (BIT(22))
+#define PCR_IOMUX_FUNC_CLK_EN_M  (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S)
+#define PCR_IOMUX_FUNC_CLK_EN_V  0x00000001U
+#define PCR_IOMUX_FUNC_CLK_EN_S  22
+
+/** PCR_MEM_MONITOR_CONF_REG register
+ *  MEM_MONITOR configuration register
+ */
+#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0)
+/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable mem_monitor clock
+ */
+#define PCR_MEM_MONITOR_CLK_EN    (BIT(0))
+#define PCR_MEM_MONITOR_CLK_EN_M  (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S)
+#define PCR_MEM_MONITOR_CLK_EN_V  0x00000001U
+#define PCR_MEM_MONITOR_CLK_EN_S  0
+/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset mem_monitor module
+ */
+#define PCR_MEM_MONITOR_RST_EN    (BIT(1))
+#define PCR_MEM_MONITOR_RST_EN_M  (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S)
+#define PCR_MEM_MONITOR_RST_EN_V  0x00000001U
+#define PCR_MEM_MONITOR_RST_EN_S  1
+
+/** PCR_REGDMA_CONF_REG register
+ *  REGDMA configuration register
+ */
+#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4)
+/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable regdma clock
+ */
+#define PCR_REGDMA_CLK_EN    (BIT(0))
+#define PCR_REGDMA_CLK_EN_M  (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S)
+#define PCR_REGDMA_CLK_EN_V  0x00000001U
+#define PCR_REGDMA_CLK_EN_S  0
+/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset regdma module
+ */
+#define PCR_REGDMA_RST_EN    (BIT(1))
+#define PCR_REGDMA_RST_EN_M  (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
+#define PCR_REGDMA_RST_EN_V  0x00000001U
+#define PCR_REGDMA_RST_EN_S  1
+
+/** PCR_RETENTION_CONF_REG register
+ *  retention configuration register
+ */
+#define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8)
+/** PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable retention clock
+ */
+#define PCR_RETENTION_CLK_EN    (BIT(0))
+#define PCR_RETENTION_CLK_EN_M  (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S)
+#define PCR_RETENTION_CLK_EN_V  0x00000001U
+#define PCR_RETENTION_CLK_EN_S  0
+/** PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset retention module
+ */
+#define PCR_RETENTION_RST_EN    (BIT(1))
+#define PCR_RETENTION_RST_EN_M  (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S)
+#define PCR_RETENTION_RST_EN_V  0x00000001U
+#define PCR_RETENTION_RST_EN_S  1
+
+/** PCR_TRACE_CONF_REG register
+ *  TRACE configuration register
+ */
+#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc)
+/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable trace clock
+ */
+#define PCR_TRACE_CLK_EN    (BIT(0))
+#define PCR_TRACE_CLK_EN_M  (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S)
+#define PCR_TRACE_CLK_EN_V  0x00000001U
+#define PCR_TRACE_CLK_EN_S  0
+/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset trace module
+ */
+#define PCR_TRACE_RST_EN    (BIT(1))
+#define PCR_TRACE_RST_EN_M  (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
+#define PCR_TRACE_RST_EN_V  0x00000001U
+#define PCR_TRACE_RST_EN_S  1
+
+/** PCR_ASSIST_CONF_REG register
+ *  ASSIST configuration register
+ */
+#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100)
+/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable assist clock
+ */
+#define PCR_ASSIST_CLK_EN    (BIT(0))
+#define PCR_ASSIST_CLK_EN_M  (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S)
+#define PCR_ASSIST_CLK_EN_V  0x00000001U
+#define PCR_ASSIST_CLK_EN_S  0
+/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset assist module
+ */
+#define PCR_ASSIST_RST_EN    (BIT(1))
+#define PCR_ASSIST_RST_EN_M  (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
+#define PCR_ASSIST_RST_EN_V  0x00000001U
+#define PCR_ASSIST_RST_EN_S  1
+
+/** PCR_CACHE_CONF_REG register
+ *  CACHE configuration register
+ */
+#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104)
+/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable cache clock
+ */
+#define PCR_CACHE_CLK_EN    (BIT(0))
+#define PCR_CACHE_CLK_EN_M  (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S)
+#define PCR_CACHE_CLK_EN_V  0x00000001U
+#define PCR_CACHE_CLK_EN_S  0
+/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset cache module
+ */
+#define PCR_CACHE_RST_EN    (BIT(1))
+#define PCR_CACHE_RST_EN_M  (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
+#define PCR_CACHE_RST_EN_V  0x00000001U
+#define PCR_CACHE_RST_EN_S  1
+
+/** PCR_MODEM_APB_CONF_REG register
+ *  MODEM_APB configuration register
+ */
+#define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108)
+/** PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).
+ */
+#define PCR_MODEM_APB_CLK_EN    (BIT(0))
+#define PCR_MODEM_APB_CLK_EN_M  (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S)
+#define PCR_MODEM_APB_CLK_EN_V  0x00000001U
+#define PCR_MODEM_APB_CLK_EN_S  0
+/** PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this file as 1 to reset modem-subsystem.
+ */
+#define PCR_MODEM_RST_EN    (BIT(1))
+#define PCR_MODEM_RST_EN_M  (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S)
+#define PCR_MODEM_RST_EN_V  0x00000001U
+#define PCR_MODEM_RST_EN_S  1
+
+/** PCR_TIMEOUT_CONF_REG register
+ *  TIMEOUT configuration register
+ */
+#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c)
+/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset cpu_peri timeout module
+ */
+#define PCR_CPU_TIMEOUT_RST_EN    (BIT(1))
+#define PCR_CPU_TIMEOUT_RST_EN_M  (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
+#define PCR_CPU_TIMEOUT_RST_EN_V  0x00000001U
+#define PCR_CPU_TIMEOUT_RST_EN_S  1
+/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
+ */
+#define PCR_HP_TIMEOUT_RST_EN    (BIT(2))
+#define PCR_HP_TIMEOUT_RST_EN_M  (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
+#define PCR_HP_TIMEOUT_RST_EN_V  0x00000001U
+#define PCR_HP_TIMEOUT_RST_EN_S  2
+
+/** PCR_SYSCLK_CONF_REG register
+ *  SYSCLK configuration register
+ */
+#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110)
+/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
+ *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
+ *  clock-source such as XTAL/FOSC.
+ */
+#define PCR_LS_DIV_NUM    0x000000FFU
+#define PCR_LS_DIV_NUM_M  (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
+#define PCR_LS_DIV_NUM_V  0x000000FFU
+#define PCR_LS_DIV_NUM_S  0
+/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
+ *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
+ */
+#define PCR_HS_DIV_NUM    0x000000FFU
+#define PCR_HS_DIV_NUM_M  (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
+#define PCR_HS_DIV_NUM_V  0x000000FFU
+#define PCR_HS_DIV_NUM_S  8
+/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
+ */
+#define PCR_SOC_CLK_SEL    0x00000003U
+#define PCR_SOC_CLK_SEL_M  (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
+#define PCR_SOC_CLK_SEL_V  0x00000003U
+#define PCR_SOC_CLK_SEL_S  16
+/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40;
+ *  This field indicates the frequency(MHz) of XTAL.
+ */
+#define PCR_CLK_XTAL_FREQ    0x0000007FU
+#define PCR_CLK_XTAL_FREQ_M  (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S)
+#define PCR_CLK_XTAL_FREQ_V  0x0000007FU
+#define PCR_CLK_XTAL_FREQ_S  24
+
+/** PCR_CPU_WAITI_CONF_REG register
+ *  CPU_WAITI configuration register
+ */
+#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114)
+/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
+ *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
+ */
+#define PCR_CPUPERIOD_SEL    0x00000003U
+#define PCR_CPUPERIOD_SEL_M  (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
+#define PCR_CPUPERIOD_SEL_V  0x00000003U
+#define PCR_CPUPERIOD_SEL_S  0
+/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
+ *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
+ */
+#define PCR_PLL_FREQ_SEL    (BIT(2))
+#define PCR_PLL_FREQ_SEL_M  (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
+#define PCR_PLL_FREQ_SEL_V  0x00000001U
+#define PCR_PLL_FREQ_SEL_S  2
+/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to force cpu_waiti_clk enable.
+ */
+#define PCR_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
+#define PCR_CPU_WAIT_MODE_FORCE_ON_M  (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S)
+#define PCR_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
+#define PCR_CPU_WAIT_MODE_FORCE_ON_S  3
+/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
+ *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+ *  will close
+ */
+#define PCR_CPU_WAITI_DELAY_NUM    0x0000000FU
+#define PCR_CPU_WAITI_DELAY_NUM_M  (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S)
+#define PCR_CPU_WAITI_DELAY_NUM_V  0x0000000FU
+#define PCR_CPU_WAITI_DELAY_NUM_S  4
+
+/** PCR_CPU_FREQ_CONF_REG register
+ *  CPU_FREQ configuration register
+ */
+#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
+/** PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
+ *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
+ */
+#define PCR_CPU_LS_DIV_NUM    0x000000FFU
+#define PCR_CPU_LS_DIV_NUM_M  (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S)
+#define PCR_CPU_LS_DIV_NUM_V  0x000000FFU
+#define PCR_CPU_LS_DIV_NUM_S  0
+/** PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed
+ *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
+ */
+#define PCR_CPU_HS_DIV_NUM    0x000000FFU
+#define PCR_CPU_HS_DIV_NUM_M  (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S)
+#define PCR_CPU_HS_DIV_NUM_V  0x000000FFU
+#define PCR_CPU_HS_DIV_NUM_S  8
+/** PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0;
+ *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
+ *  Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
+ */
+#define PCR_CPU_HS_120M_FORCE    (BIT(16))
+#define PCR_CPU_HS_120M_FORCE_M  (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S)
+#define PCR_CPU_HS_120M_FORCE_V  0x00000001U
+#define PCR_CPU_HS_120M_FORCE_S  16
+
+/** PCR_AHB_FREQ_CONF_REG register
+ *  AHB_FREQ configuration register
+ */
+#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
+/** PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb
+ *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
+ *  low-speed clock-source such as XTAL/FOSC, and should be used together with
+ *  PCR_CPU_LS_DIV_NUM.
+ */
+#define PCR_AHB_LS_DIV_NUM    0x000000FFU
+#define PCR_AHB_LS_DIV_NUM_M  (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S)
+#define PCR_AHB_LS_DIV_NUM_V  0x000000FFU
+#define PCR_AHB_LS_DIV_NUM_S  0
+/** PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is
+ *  div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed
+ *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
+ */
+#define PCR_AHB_HS_DIV_NUM    0x000000FFU
+#define PCR_AHB_HS_DIV_NUM_M  (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S)
+#define PCR_AHB_HS_DIV_NUM_V  0x000000FFU
+#define PCR_AHB_HS_DIV_NUM_S  8
+
+/** PCR_APB_FREQ_CONF_REG register
+ *  APB_FREQ configuration register
+ */
+#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120)
+/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
+ *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
+ *  recover to the previous frequency when a new access appears on apb-bus. Set as one
+ *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
+ *  that enable this function will reduce performance. Users can set this field as zero
+ *  to disable the auto-decrease-apb-freq function. By default, this function is
+ *  disable.
+ */
+#define PCR_APB_DECREASE_DIV_NUM    0x000000FFU
+#define PCR_APB_DECREASE_DIV_NUM_M  (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S)
+#define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
+#define PCR_APB_DECREASE_DIV_NUM_S  0
+/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
+ *  div1(default)/div2/div4 of clk_ahb.
+ */
+#define PCR_APB_DIV_NUM    0x000000FFU
+#define PCR_APB_DIV_NUM_M  (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S)
+#define PCR_APB_DIV_NUM_V  0x000000FFU
+#define PCR_APB_DIV_NUM_S  8
+
+/** PCR_SYSCLK_FREQ_QUERY_0_REG register
+ *  SYSCLK frequency query 0 register
+ */
+#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124)
+/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20;
+ *  This field indicates the frequency(MHz) of FOSC.
+ */
+#define PCR_FOSC_FREQ    0x000000FFU
+#define PCR_FOSC_FREQ_M  (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S)
+#define PCR_FOSC_FREQ_V  0x000000FFU
+#define PCR_FOSC_FREQ_S  0
+/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480;
+ *  This field indicates the frequency(MHz) of SPLL.
+ */
+#define PCR_PLL_FREQ    0x000003FFU
+#define PCR_PLL_FREQ_M  (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S)
+#define PCR_PLL_FREQ_V  0x000003FFU
+#define PCR_PLL_FREQ_S  8
+
+/** PCR_PLL_DIV_CLK_EN_REG register
+ *  SPLL DIV clock-gating configuration register
+ */
+#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128)
+/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_240M_CLK_EN    (BIT(0))
+#define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
+#define PCR_PLL_240M_CLK_EN_V  0x00000001U
+#define PCR_PLL_240M_CLK_EN_S  0
+/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_160M_CLK_EN    (BIT(1))
+#define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
+#define PCR_PLL_160M_CLK_EN_V  0x00000001U
+#define PCR_PLL_160M_CLK_EN_S  1
+/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_120M_CLK_EN    (BIT(2))
+#define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
+#define PCR_PLL_120M_CLK_EN_V  0x00000001U
+#define PCR_PLL_120M_CLK_EN_S  2
+/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  This field is used to open 80 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_80M_CLK_EN    (BIT(3))
+#define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
+#define PCR_PLL_80M_CLK_EN_V  0x00000001U
+#define PCR_PLL_80M_CLK_EN_S  3
+/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_48M_CLK_EN    (BIT(4))
+#define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
+#define PCR_PLL_48M_CLK_EN_V  0x00000001U
+#define PCR_PLL_48M_CLK_EN_S  4
+/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_40M_CLK_EN    (BIT(5))
+#define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
+#define PCR_PLL_40M_CLK_EN_V  0x00000001U
+#define PCR_PLL_40M_CLK_EN_S  5
+/** PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_20M_CLK_EN    (BIT(6))
+#define PCR_PLL_20M_CLK_EN_M  (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S)
+#define PCR_PLL_20M_CLK_EN_V  0x00000001U
+#define PCR_PLL_20M_CLK_EN_S  6
+
+/** PCR_CTRL_CLK_OUT_EN_REG register
+ *  CLK_OUT_EN configuration register
+ */
+#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c)
+/** PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable 20m clock
+ */
+#define PCR_CLK20_OEN    (BIT(0))
+#define PCR_CLK20_OEN_M  (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S)
+#define PCR_CLK20_OEN_V  0x00000001U
+#define PCR_CLK20_OEN_S  0
+/** PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1;
+ *  Set 1 to enable 22m clock
+ */
+#define PCR_CLK22_OEN    (BIT(1))
+#define PCR_CLK22_OEN_M  (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S)
+#define PCR_CLK22_OEN_V  0x00000001U
+#define PCR_CLK22_OEN_S  1
+/** PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable 44m clock
+ */
+#define PCR_CLK44_OEN    (BIT(2))
+#define PCR_CLK44_OEN_M  (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S)
+#define PCR_CLK44_OEN_V  0x00000001U
+#define PCR_CLK44_OEN_S  2
+/** PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to enable bb clock
+ */
+#define PCR_CLK_BB_OEN    (BIT(3))
+#define PCR_CLK_BB_OEN_M  (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S)
+#define PCR_CLK_BB_OEN_V  0x00000001U
+#define PCR_CLK_BB_OEN_S  3
+/** PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1;
+ *  Set 1 to enable 80m clock
+ */
+#define PCR_CLK80_OEN    (BIT(4))
+#define PCR_CLK80_OEN_M  (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S)
+#define PCR_CLK80_OEN_V  0x00000001U
+#define PCR_CLK80_OEN_S  4
+/** PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1;
+ *  Set 1 to enable 160m clock
+ */
+#define PCR_CLK160_OEN    (BIT(5))
+#define PCR_CLK160_OEN_M  (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S)
+#define PCR_CLK160_OEN_V  0x00000001U
+#define PCR_CLK160_OEN_S  5
+/** PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1;
+ *  Set 1 to enable 320m clock
+ */
+#define PCR_CLK_320M_OEN    (BIT(6))
+#define PCR_CLK_320M_OEN_M  (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S)
+#define PCR_CLK_320M_OEN_V  0x00000001U
+#define PCR_CLK_320M_OEN_S  6
+/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1;
+ *  Reserved
+ */
+#define PCR_CLK_ADC_INF_OEN    (BIT(7))
+#define PCR_CLK_ADC_INF_OEN_M  (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S)
+#define PCR_CLK_ADC_INF_OEN_V  0x00000001U
+#define PCR_CLK_ADC_INF_OEN_S  7
+/** PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define PCR_CLK_DAC_CPU_OEN    (BIT(8))
+#define PCR_CLK_DAC_CPU_OEN_M  (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S)
+#define PCR_CLK_DAC_CPU_OEN_V  0x00000001U
+#define PCR_CLK_DAC_CPU_OEN_S  8
+/** PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1;
+ *  Set 1 to enable 40x_bb clock
+ */
+#define PCR_CLK40X_BB_OEN    (BIT(9))
+#define PCR_CLK40X_BB_OEN_M  (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S)
+#define PCR_CLK40X_BB_OEN_V  0x00000001U
+#define PCR_CLK40X_BB_OEN_S  9
+/** PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1;
+ *  Set 1 to enable xtal clock
+ */
+#define PCR_CLK_XTAL_OEN    (BIT(10))
+#define PCR_CLK_XTAL_OEN_M  (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S)
+#define PCR_CLK_XTAL_OEN_V  0x00000001U
+#define PCR_CLK_XTAL_OEN_S  10
+
+/** PCR_CTRL_TICK_CONF_REG register
+ *  TICK configuration register
+ */
+#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130)
+/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39;
+ *  ******* Description ***********
+ */
+#define PCR_XTAL_TICK_NUM    0x000000FFU
+#define PCR_XTAL_TICK_NUM_M  (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S)
+#define PCR_XTAL_TICK_NUM_V  0x000000FFU
+#define PCR_XTAL_TICK_NUM_S  0
+/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7;
+ *  ******* Description ***********
+ */
+#define PCR_FOSC_TICK_NUM    0x000000FFU
+#define PCR_FOSC_TICK_NUM_M  (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S)
+#define PCR_FOSC_TICK_NUM_V  0x000000FFU
+#define PCR_FOSC_TICK_NUM_S  8
+/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1;
+ *  ******* Description ***********
+ */
+#define PCR_TICK_ENABLE    (BIT(16))
+#define PCR_TICK_ENABLE_M  (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S)
+#define PCR_TICK_ENABLE_V  0x00000001U
+#define PCR_TICK_ENABLE_S  16
+/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0;
+ *  ******* Description ***********
+ */
+#define PCR_RST_TICK_CNT    (BIT(17))
+#define PCR_RST_TICK_CNT_M  (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S)
+#define PCR_RST_TICK_CNT_V  0x00000001U
+#define PCR_RST_TICK_CNT_S  17
+
+/** PCR_CTRL_32K_CONF_REG register
+ *  32KHz clock configuration register
+ */
+#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134)
+/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and
+ *  timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
+ */
+#define PCR_32K_SEL    0x00000003U
+#define PCR_32K_SEL_M  (PCR_32K_SEL_V << PCR_32K_SEL_S)
+#define PCR_32K_SEL_V  0x00000003U
+#define PCR_32K_SEL_S  0
+
+/** PCR_SRAM_POWER_CONF_REG register
+ *  HP SRAM/ROM configuration register
+ */
+#define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138)
+/** PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15;
+ *  Set this bit to force power up SRAM
+ */
+#define PCR_SRAM_FORCE_PU    0x0000000FU
+#define PCR_SRAM_FORCE_PU_M  (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S)
+#define PCR_SRAM_FORCE_PU_V  0x0000000FU
+#define PCR_SRAM_FORCE_PU_S  0
+/** PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0;
+ *  Set this bit to force power down SRAM.
+ */
+#define PCR_SRAM_FORCE_PD    0x0000000FU
+#define PCR_SRAM_FORCE_PD_M  (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S)
+#define PCR_SRAM_FORCE_PD_V  0x0000000FU
+#define PCR_SRAM_FORCE_PD_S  4
+/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
+ *  gate-clock will be used when accessing the SRAM.
+ */
+#define PCR_SRAM_CLKGATE_FORCE_ON    0x0000000FU
+#define PCR_SRAM_CLKGATE_FORCE_ON_M  (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S)
+#define PCR_SRAM_CLKGATE_FORCE_ON_V  0x0000000FU
+#define PCR_SRAM_CLKGATE_FORCE_ON_S  8
+/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7;
+ *  Set this bit to force power up ROM
+ */
+#define PCR_ROM_FORCE_PU    0x00000007U
+#define PCR_ROM_FORCE_PU_M  (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S)
+#define PCR_ROM_FORCE_PU_V  0x00000007U
+#define PCR_ROM_FORCE_PU_S  12
+/** PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0;
+ *  Set this bit to force power down ROM.
+ */
+#define PCR_ROM_FORCE_PD    0x00000007U
+#define PCR_ROM_FORCE_PD_M  (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S)
+#define PCR_ROM_FORCE_PD_V  0x00000007U
+#define PCR_ROM_FORCE_PD_S  15
+/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
+ *  gate-clock will be used when accessing the ROM.
+ */
+#define PCR_ROM_CLKGATE_FORCE_ON    0x00000007U
+#define PCR_ROM_CLKGATE_FORCE_ON_M  (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S)
+#define PCR_ROM_CLKGATE_FORCE_ON_V  0x00000007U
+#define PCR_ROM_CLKGATE_FORCE_ON_S  18
+
+/** PCR_RESET_EVENT_BYPASS_REG register
+ *  reset event bypass backdoor configuration register
+ */
+#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0)
+/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0;
+ *  This field is used to control reset event relationship for
+ *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
+ *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
+ *  will not only be reset by power-reset, but also some reset event.
+ */
+#define PCR_RESET_EVENT_BYPASS_APM    (BIT(0))
+#define PCR_RESET_EVENT_BYPASS_APM_M  (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S)
+#define PCR_RESET_EVENT_BYPASS_APM_V  0x00000001U
+#define PCR_RESET_EVENT_BYPASS_APM_S  0
+/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  This field is used to control reset event relationship for system-bus. 1: system
+ *  bus (including arbiter/router) will only be reset by power-reset. some reset event
+ *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
+ *  power-reset, but also some reset event.
+ */
+#define PCR_RESET_EVENT_BYPASS    (BIT(1))
+#define PCR_RESET_EVENT_BYPASS_M  (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S)
+#define PCR_RESET_EVENT_BYPASS_V  0x00000001U
+#define PCR_RESET_EVENT_BYPASS_S  1
+
+/** PCR_FPGA_DEBUG_REG register
+ *  fpga debug register
+ */
+#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
+/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Only used in fpga debug.
+ */
+#define PCR_FPGA_DEBUG    0xFFFFFFFFU
+#define PCR_FPGA_DEBUG_M  (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
+#define PCR_FPGA_DEBUG_V  0xFFFFFFFFU
+#define PCR_FPGA_DEBUG_S  0
+
+/** PCR_CLOCK_GATE_REG register
+ *  PCR clock gating configure register
+ */
+#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
+/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to force on clock gating.
+ */
+#define PCR_CLK_EN    (BIT(0))
+#define PCR_CLK_EN_M  (PCR_CLK_EN_V << PCR_CLK_EN_S)
+#define PCR_CLK_EN_V  0x00000001U
+#define PCR_CLK_EN_S  0
+
+/** PCR_DATE_REG register
+ *  Date register.
+ */
+#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
+/** PCR_DATE : R/W; bitpos: [27:0]; default: 35676496;
+ *  PCR version information.
+ */
+#define PCR_DATE    0x0FFFFFFFU
+#define PCR_DATE_M  (PCR_DATE_V << PCR_DATE_S)
+#define PCR_DATE_V  0x0FFFFFFFU
+#define PCR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/pcr_struct.h b/components/soc/esp32c6/register/soc/pcr_struct.h
new file mode 100644
index 00000000000..ee74db8ff14
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/pcr_struct.h
@@ -0,0 +1,1932 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of uart0_conf register
+ *  UART0 configuration register
+ */
+typedef union {
+    struct {
+        /** uart0_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable uart0 apb clock
+         */
+        uint32_t uart0_clk_en:1;
+        /** uart0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset uart0 module
+         */
+        uint32_t uart0_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_uart0_conf_reg_t;
+
+/** Type of uart0_sclk_conf register
+ *  UART0_SCLK configuration register
+ */
+typedef union {
+    struct {
+        /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the uart0 function clock.
+         */
+        uint32_t uart0_sclk_div_a:6;
+        /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the uart0 function clock.
+         */
+        uint32_t uart0_sclk_div_b:6;
+        /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
+         *  The integral part of the frequency divider factor of the uart0 function clock.
+         */
+        uint32_t uart0_sclk_div_num:8;
+        /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+         *  FOSC, 3(default): XTAL.
+         */
+        uint32_t uart0_sclk_sel:2;
+        /** uart0_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable uart0 function clock
+         */
+        uint32_t uart0_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_uart0_sclk_conf_reg_t;
+
+/** Type of uart0_pd_ctrl register
+ *  UART0 power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power down UART0 memory.
+         */
+        uint32_t uart0_mem_force_pu:1;
+        /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power up UART0 memory.
+         */
+        uint32_t uart0_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_uart0_pd_ctrl_reg_t;
+
+/** Type of uart1_conf register
+ *  UART1 configuration register
+ */
+typedef union {
+    struct {
+        /** uart1_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable uart1 apb clock
+         */
+        uint32_t uart1_clk_en:1;
+        /** uart1_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset uart1 module
+         */
+        uint32_t uart1_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_uart1_conf_reg_t;
+
+/** Type of uart1_sclk_conf register
+ *  UART1_SCLK configuration register
+ */
+typedef union {
+    struct {
+        /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the uart1 function clock.
+         */
+        uint32_t uart1_sclk_div_a:6;
+        /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the uart1 function clock.
+         */
+        uint32_t uart1_sclk_div_b:6;
+        /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
+         *  The integral part of the frequency divider factor of the uart1 function clock.
+         */
+        uint32_t uart1_sclk_div_num:8;
+        /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+         *  FOSC, 3(default): XTAL.
+         */
+        uint32_t uart1_sclk_sel:2;
+        /** uart1_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable uart0 function clock
+         */
+        uint32_t uart1_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_uart1_sclk_conf_reg_t;
+
+/** Type of uart1_pd_ctrl register
+ *  UART1 power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power down UART1 memory.
+         */
+        uint32_t uart1_mem_force_pu:1;
+        /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power up UART1 memory.
+         */
+        uint32_t uart1_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_uart1_pd_ctrl_reg_t;
+
+/** Type of mspi_conf register
+ *  MSPI configuration register
+ */
+typedef union {
+    struct {
+        /** mspi_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable mspi clock, include mspi pll clock
+         */
+        uint32_t mspi_clk_en:1;
+        /** mspi_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset mspi module
+         */
+        uint32_t mspi_rst_en:1;
+        /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to enable mspi pll clock
+         */
+        uint32_t mspi_pll_clk_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_mspi_conf_reg_t;
+
+/** Type of mspi_clk_conf register
+ *  MSPI_CLK configuration register
+ */
+typedef union {
+    struct {
+        /** mspi_fast_ls_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
+         *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
+         *  low-speed clock-source such as XTAL/FOSC.
+         */
+        uint32_t mspi_fast_ls_div_num:8;
+        /** mspi_fast_hs_div_num : R/W; bitpos: [15:8]; default: 3;
+         *  Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed
+         *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
+         *  high-speed clock-source such as SPLL.
+         */
+        uint32_t mspi_fast_hs_div_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcr_mspi_clk_conf_reg_t;
+
+/** Type of i2c_conf register
+ *  I2C configuration register
+ */
+typedef union {
+    struct {
+        /** i2c_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable i2c apb clock
+         */
+        uint32_t i2c_clk_en:1;
+        /** i2c_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset i2c module
+         */
+        uint32_t i2c_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_i2c_conf_reg_t;
+
+/** Type of i2c_sclk_conf register
+ *  I2C_SCLK configuration register
+ */
+typedef union {
+    struct {
+        /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the i2c function clock.
+         */
+        uint32_t i2c_sclk_div_a:6;
+        /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the i2c function clock.
+         */
+        uint32_t i2c_sclk_div_b:6;
+        /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
+         *  The integral part of the frequency divider factor of the i2c function clock.
+         */
+        uint32_t i2c_sclk_div_num:8;
+        /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+         */
+        uint32_t i2c_sclk_sel:1;
+        uint32_t reserved_21:1;
+        /** i2c_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable i2c function clock
+         */
+        uint32_t i2c_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_i2c_sclk_conf_reg_t;
+
+/** Type of uhci_conf register
+ *  UHCI configuration register
+ */
+typedef union {
+    struct {
+        /** uhci_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable uhci clock
+         */
+        uint32_t uhci_clk_en:1;
+        /** uhci_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset uhci module
+         */
+        uint32_t uhci_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_uhci_conf_reg_t;
+
+/** Type of rmt_conf register
+ *  RMT configuration register
+ */
+typedef union {
+    struct {
+        /** rmt_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable rmt apb clock
+         */
+        uint32_t rmt_clk_en:1;
+        /** rmt_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset rmt module
+         */
+        uint32_t rmt_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_rmt_conf_reg_t;
+
+/** Type of rmt_sclk_conf register
+ *  RMT_SCLK configuration register
+ */
+typedef union {
+    struct {
+        /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the rmt function clock.
+         */
+        uint32_t rmt_sclk_div_a:6;
+        /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the rmt function clock.
+         */
+        uint32_t rmt_sclk_div_b:6;
+        /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor of the rmt function clock.
+         */
+        uint32_t rmt_sclk_div_num:8;
+        /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1;
+         *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
+         *  80MHz, 2: FOSC, 3: XTAL.
+         */
+        uint32_t rmt_sclk_sel:2;
+        /** rmt_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable rmt function clock
+         */
+        uint32_t rmt_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_rmt_sclk_conf_reg_t;
+
+/** Type of ledc_conf register
+ *  LEDC configuration register
+ */
+typedef union {
+    struct {
+        /** ledc_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable ledc apb clock
+         */
+        uint32_t ledc_clk_en:1;
+        /** ledc_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset ledc module
+         */
+        uint32_t ledc_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_ledc_conf_reg_t;
+
+/** Type of ledc_sclk_conf register
+ *  LEDC_SCLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+         *  80MHz, 2: FOSC, 3: XTAL.
+         */
+        uint32_t ledc_sclk_sel:2;
+        /** ledc_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable ledc function clock
+         */
+        uint32_t ledc_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_ledc_sclk_conf_reg_t;
+
+/** Type of timergroup0_conf register
+ *  TIMERGROUP0 configuration register
+ */
+typedef union {
+    struct {
+        /** tg0_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable timer_group0 apb clock
+         */
+        uint32_t tg0_clk_en:1;
+        /** tg0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset timer_group0 module
+         */
+        uint32_t tg0_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_timergroup0_conf_reg_t;
+
+/** Type of timergroup0_timer_clk_conf register
+ *  TIMERGROUP0_TIMER_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t tg0_timer_clk_sel:2;
+        /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable timer_group0 timer clock
+         */
+        uint32_t tg0_timer_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_timergroup0_timer_clk_conf_reg_t;
+
+/** Type of timergroup0_wdt_clk_conf register
+ *  TIMERGROUP0_WDT_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t tg0_wdt_clk_sel:2;
+        /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable timer_group0 wdt clock
+         */
+        uint32_t tg0_wdt_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_timergroup0_wdt_clk_conf_reg_t;
+
+/** Type of timergroup1_conf register
+ *  TIMERGROUP1 configuration register
+ */
+typedef union {
+    struct {
+        /** tg1_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable timer_group1 apb clock
+         */
+        uint32_t tg1_clk_en:1;
+        /** tg1_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset timer_group1 module
+         */
+        uint32_t tg1_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_timergroup1_conf_reg_t;
+
+/** Type of timergroup1_timer_clk_conf register
+ *  TIMERGROUP1_TIMER_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t tg1_timer_clk_sel:2;
+        /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable timer_group1 timer clock
+         */
+        uint32_t tg1_timer_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_timergroup1_timer_clk_conf_reg_t;
+
+/** Type of timergroup1_wdt_clk_conf register
+ *  TIMERGROUP1_WDT_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t tg1_wdt_clk_sel:2;
+        /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable timer_group0 wdt clock
+         */
+        uint32_t tg1_wdt_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_timergroup1_wdt_clk_conf_reg_t;
+
+/** Type of systimer_conf register
+ *  SYSTIMER configuration register
+ */
+typedef union {
+    struct {
+        /** systimer_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable systimer apb clock
+         */
+        uint32_t systimer_clk_en:1;
+        /** systimer_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset systimer module
+         */
+        uint32_t systimer_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_systimer_conf_reg_t;
+
+/** Type of systimer_func_clk_conf register
+ *  SYSTIMER_FUNC_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+         */
+        uint32_t systimer_func_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable systimer function clock
+         */
+        uint32_t systimer_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_systimer_func_clk_conf_reg_t;
+
+/** Type of twai0_conf register
+ *  TWAI0 configuration register
+ */
+typedef union {
+    struct {
+        /** twai0_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable twai0 apb clock
+         */
+        uint32_t twai0_clk_en:1;
+        /** twai0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset twai0 module
+         */
+        uint32_t twai0_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_twai0_conf_reg_t;
+
+/** Type of twai0_func_clk_conf register
+ *  TWAI0_FUNC_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+         */
+        uint32_t twai0_func_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable twai0 function clock
+         */
+        uint32_t twai0_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_twai0_func_clk_conf_reg_t;
+
+/** Type of twai1_conf register
+ *  TWAI1 configuration register
+ */
+typedef union {
+    struct {
+        /** twai1_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable twai1 apb clock
+         */
+        uint32_t twai1_clk_en:1;
+        /** twai1_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset twai1 module
+         */
+        uint32_t twai1_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_twai1_conf_reg_t;
+
+/** Type of twai1_func_clk_conf register
+ *  TWAI1_FUNC_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** twai1_func_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+         */
+        uint32_t twai1_func_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** twai1_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable twai1 function clock
+         */
+        uint32_t twai1_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_twai1_func_clk_conf_reg_t;
+
+/** Type of i2s_conf register
+ *  I2S configuration register
+ */
+typedef union {
+    struct {
+        /** i2s_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable i2s apb clock
+         */
+        uint32_t i2s_clk_en:1;
+        /** i2s_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset i2s module
+         */
+        uint32_t i2s_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_i2s_conf_reg_t;
+
+/** Type of i2s_tx_clkm_conf register
+ *  I2S_TX_CLKM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
+         *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
+         *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
+         *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+         *  (n+1)-div] + y * (n+1)-div.
+         */
+        uint32_t i2s_tx_clkm_div_num:8;
+        /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3:
+         *  I2S_MCLK_in.
+         */
+        uint32_t i2s_tx_clkm_sel:2;
+        /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable i2s_tx function clock
+         */
+        uint32_t i2s_tx_clkm_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_i2s_tx_clkm_conf_reg_t;
+
+/** Type of i2s_tx_clkm_div_conf register
+ *  I2S_TX_CLKM_DIV configuration register
+ */
+typedef union {
+    struct {
+        /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
+         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+         *  I2S_TX_CLKM_DIV_Z is (a-b).
+         */
+        uint32_t i2s_tx_clkm_div_z:9;
+        /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
+         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+         *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+         */
+        uint32_t i2s_tx_clkm_div_y:9;
+        /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
+         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+         *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+         */
+        uint32_t i2s_tx_clkm_div_x:9;
+        /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+         *  I2S_TX_CLKM_DIV_YN1 is 1.
+         */
+        uint32_t i2s_tx_clkm_div_yn1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} pcr_i2s_tx_clkm_div_conf_reg_t;
+
+/** Type of i2s_rx_clkm_conf register
+ *  I2S_RX_CLKM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
+         *  Integral I2S clock divider value
+         */
+        uint32_t i2s_rx_clkm_div_num:8;
+        /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.
+         */
+        uint32_t i2s_rx_clkm_sel:2;
+        /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable i2s_rx function clock
+         */
+        uint32_t i2s_rx_clkm_en:1;
+        /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0;
+         *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
+         */
+        uint32_t i2s_mclk_sel:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} pcr_i2s_rx_clkm_conf_reg_t;
+
+/** Type of i2s_rx_clkm_div_conf register
+ *  I2S_RX_CLKM_DIV configuration register
+ */
+typedef union {
+    struct {
+        /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
+         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+         *  I2S_RX_CLKM_DIV_Z is (a-b).
+         */
+        uint32_t i2s_rx_clkm_div_z:9;
+        /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
+         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+         *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+         */
+        uint32_t i2s_rx_clkm_div_y:9;
+        /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
+         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+         *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+         */
+        uint32_t i2s_rx_clkm_div_x:9;
+        /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+         *  I2S_RX_CLKM_DIV_YN1 is 1.
+         */
+        uint32_t i2s_rx_clkm_div_yn1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} pcr_i2s_rx_clkm_div_conf_reg_t;
+
+/** Type of saradc_conf register
+ *  SARADC configuration register
+ */
+typedef union {
+    struct {
+        /** saradc_clk_en : R/W; bitpos: [0]; default: 1;
+         *  no use
+         */
+        uint32_t saradc_clk_en:1;
+        /** saradc_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset function_register of saradc module
+         */
+        uint32_t saradc_rst_en:1;
+        /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to enable saradc apb clock
+         */
+        uint32_t saradc_reg_clk_en:1;
+        /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0;
+         *  Set 0 to reset apb_register of saradc module
+         */
+        uint32_t saradc_reg_rst_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcr_saradc_conf_reg_t;
+
+/** Type of saradc_clkm_conf register
+ *  SARADC_CLKM configuration register
+ */
+typedef union {
+    struct {
+        /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the saradc function clock.
+         */
+        uint32_t saradc_clkm_div_a:6;
+        /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the saradc function clock.
+         */
+        uint32_t saradc_clkm_div_b:6;
+        /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4;
+         *  The integral part of the frequency divider factor of the saradc function clock.
+         */
+        uint32_t saradc_clkm_div_num:8;
+        /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t saradc_clkm_sel:2;
+        /** saradc_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable saradc function clock
+         */
+        uint32_t saradc_clkm_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_saradc_clkm_conf_reg_t;
+
+/** Type of tsens_clk_conf register
+ *  TSENS_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tsens_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
+         */
+        uint32_t tsens_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** tsens_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable tsens clock
+         */
+        uint32_t tsens_clk_en:1;
+        /** tsens_rst_en : R/W; bitpos: [23]; default: 0;
+         *  Set 0 to reset tsens module
+         */
+        uint32_t tsens_rst_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} pcr_tsens_clk_conf_reg_t;
+
+/** Type of usb_device_conf register
+ *  USB_DEVICE configuration register
+ */
+typedef union {
+    struct {
+        /** usb_device_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable usb_device clock
+         */
+        uint32_t usb_device_clk_en:1;
+        /** usb_device_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset usb_device module
+         */
+        uint32_t usb_device_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_usb_device_conf_reg_t;
+
+/** Type of intmtx_conf register
+ *  INTMTX configuration register
+ */
+typedef union {
+    struct {
+        /** intmtx_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable intmtx clock
+         */
+        uint32_t intmtx_clk_en:1;
+        /** intmtx_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset intmtx module
+         */
+        uint32_t intmtx_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_intmtx_conf_reg_t;
+
+/** Type of pcnt_conf register
+ *  PCNT configuration register
+ */
+typedef union {
+    struct {
+        /** pcnt_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable pcnt clock
+         */
+        uint32_t pcnt_clk_en:1;
+        /** pcnt_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset pcnt module
+         */
+        uint32_t pcnt_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_pcnt_conf_reg_t;
+
+/** Type of etm_conf register
+ *  ETM configuration register
+ */
+typedef union {
+    struct {
+        /** etm_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable etm clock
+         */
+        uint32_t etm_clk_en:1;
+        /** etm_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset etm module
+         */
+        uint32_t etm_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_etm_conf_reg_t;
+
+/** Type of pwm_conf register
+ *  PWM configuration register
+ */
+typedef union {
+    struct {
+        /** pwm_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable pwm clock
+         */
+        uint32_t pwm_clk_en:1;
+        /** pwm_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset pwm module
+         */
+        uint32_t pwm_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_pwm_conf_reg_t;
+
+/** Type of pwm_clk_conf register
+ *  PWM_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** pwm_div_num : R/W; bitpos: [19:12]; default: 4;
+         *  The integral part of the frequency divider factor of the pwm function clock.
+         */
+        uint32_t pwm_div_num:8;
+        /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+         *  160MHz, 2: XTAL, 3: FOSC.
+         */
+        uint32_t pwm_clkm_sel:2;
+        /** pwm_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  set this field as 1 to activate pwm clkm.
+         */
+        uint32_t pwm_clkm_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_pwm_clk_conf_reg_t;
+
+/** Type of parl_io_conf register
+ *  PARL_IO configuration register
+ */
+typedef union {
+    struct {
+        /** parl_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable parl apb clock
+         */
+        uint32_t parl_clk_en:1;
+        /** parl_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset parl apb reg
+         */
+        uint32_t parl_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_parl_io_conf_reg_t;
+
+/** Type of parl_clk_rx_conf register
+ *  PARL_CLK_RX configuration register
+ */
+typedef union {
+    struct {
+        /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0;
+         *  The integral part of the frequency divider factor of the parl rx clock.
+         */
+        uint32_t parl_clk_rx_div_num:16;
+        /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+         *  user clock from pad.
+         */
+        uint32_t parl_clk_rx_sel:2;
+        /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1;
+         *  Set 1 to enable parl rx clock
+         */
+        uint32_t parl_clk_rx_en:1;
+        /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0;
+         *  Set 0 to reset parl rx module
+         */
+        uint32_t parl_rx_rst_en:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} pcr_parl_clk_rx_conf_reg_t;
+
+/** Type of parl_clk_tx_conf register
+ *  PARL_CLK_TX configuration register
+ */
+typedef union {
+    struct {
+        /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0;
+         *  The integral part of the frequency divider factor of the parl tx clock.
+         */
+        uint32_t parl_clk_tx_div_num:16;
+        /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+         *  user clock from pad.
+         */
+        uint32_t parl_clk_tx_sel:2;
+        /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1;
+         *  Set 1 to enable parl tx clock
+         */
+        uint32_t parl_clk_tx_en:1;
+        /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0;
+         *  Set 0 to reset parl tx module
+         */
+        uint32_t parl_tx_rst_en:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} pcr_parl_clk_tx_conf_reg_t;
+
+/** Type of sdio_slave_conf register
+ *  SDIO_SLAVE configuration register
+ */
+typedef union {
+    struct {
+        /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable sdio_slave clock
+         */
+        uint32_t sdio_slave_clk_en:1;
+        /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset sdio_slave module
+         */
+        uint32_t sdio_slave_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_sdio_slave_conf_reg_t;
+
+/** Type of pvt_monitor_conf register
+ *  PVT_MONITOR configuration register
+ */
+typedef union {
+    struct {
+        /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable apb clock of pvt module
+         */
+        uint32_t pvt_monitor_clk_en:1;
+        /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset all pvt monitor module
+         */
+        uint32_t pvt_monitor_rst_en:1;
+        /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to enable function clock of modem pvt module
+         */
+        uint32_t pvt_monitor_site1_clk_en:1;
+        /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Set 1 to enable function clock of cpu pvt module
+         */
+        uint32_t pvt_monitor_site2_clk_en:1;
+        /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Set 1 to enable function clock of hp_peri pvt module
+         */
+        uint32_t pvt_monitor_site3_clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} pcr_pvt_monitor_conf_reg_t;
+
+/** Type of pvt_monitor_func_clk_conf register
+ *  PVT_MONITOR function clock configuration register
+ */
+typedef union {
+    struct {
+        /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0;
+         *  The integral part of the frequency divider factor of the pvt_monitor function clock.
+         */
+        uint32_t pvt_monitor_func_clk_div_num:4;
+        uint32_t reserved_4:16;
+        /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
+         *  divided by 3.
+         */
+        uint32_t pvt_monitor_func_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable source clock of pvt sitex
+         */
+        uint32_t pvt_monitor_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_pvt_monitor_func_clk_conf_reg_t;
+
+/** Type of gdma_conf register
+ *  GDMA configuration register
+ */
+typedef union {
+    struct {
+        /** gdma_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable gdma clock
+         */
+        uint32_t gdma_clk_en:1;
+        /** gdma_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset gdma module
+         */
+        uint32_t gdma_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_gdma_conf_reg_t;
+
+/** Type of spi2_conf register
+ *  SPI2 configuration register
+ */
+typedef union {
+    struct {
+        /** spi2_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable spi2 apb clock
+         */
+        uint32_t spi2_clk_en:1;
+        /** spi2_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset spi2 module
+         */
+        uint32_t spi2_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_spi2_conf_reg_t;
+
+/** Type of spi2_clkm_conf register
+ *  SPI2_CLKM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t spi2_clkm_sel:2;
+        /** spi2_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable spi2 function clock
+         */
+        uint32_t spi2_clkm_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_spi2_clkm_conf_reg_t;
+
+/** Type of aes_conf register
+ *  AES configuration register
+ */
+typedef union {
+    struct {
+        /** aes_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable aes clock
+         */
+        uint32_t aes_clk_en:1;
+        /** aes_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset aes module
+         */
+        uint32_t aes_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_aes_conf_reg_t;
+
+/** Type of sha_conf register
+ *  SHA configuration register
+ */
+typedef union {
+    struct {
+        /** sha_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable sha clock
+         */
+        uint32_t sha_clk_en:1;
+        /** sha_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset sha module
+         */
+        uint32_t sha_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_sha_conf_reg_t;
+
+/** Type of rsa_conf register
+ *  RSA configuration register
+ */
+typedef union {
+    struct {
+        /** rsa_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable rsa clock
+         */
+        uint32_t rsa_clk_en:1;
+        /** rsa_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset rsa module
+         */
+        uint32_t rsa_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_rsa_conf_reg_t;
+
+/** Type of rsa_pd_ctrl register
+ *  RSA power control register
+ */
+typedef union {
+    struct {
+        /** rsa_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down rsa internal memory.
+         */
+        uint32_t rsa_mem_pd:1;
+        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up rsa internal memory
+         */
+        uint32_t rsa_mem_force_pu:1;
+        /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down rsa internal memory.
+         */
+        uint32_t rsa_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_rsa_pd_ctrl_reg_t;
+
+/** Type of ecc_conf register
+ *  ECC configuration register
+ */
+typedef union {
+    struct {
+        /** ecc_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable ecc clock
+         */
+        uint32_t ecc_clk_en:1;
+        /** ecc_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset ecc module
+         */
+        uint32_t ecc_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_ecc_conf_reg_t;
+
+/** Type of ecc_pd_ctrl register
+ *  ECC power control register
+ */
+typedef union {
+    struct {
+        /** ecc_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down ecc internal memory.
+         */
+        uint32_t ecc_mem_pd:1;
+        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up ecc internal memory
+         */
+        uint32_t ecc_mem_force_pu:1;
+        /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down ecc internal memory.
+         */
+        uint32_t ecc_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_ecc_pd_ctrl_reg_t;
+
+/** Type of ds_conf register
+ *  DS configuration register
+ */
+typedef union {
+    struct {
+        /** ds_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable ds clock
+         */
+        uint32_t ds_clk_en:1;
+        /** ds_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset ds module
+         */
+        uint32_t ds_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_ds_conf_reg_t;
+
+/** Type of hmac_conf register
+ *  HMAC configuration register
+ */
+typedef union {
+    struct {
+        /** hmac_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable hmac clock
+         */
+        uint32_t hmac_clk_en:1;
+        /** hmac_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset hmac module
+         */
+        uint32_t hmac_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_hmac_conf_reg_t;
+
+/** Type of iomux_conf register
+ *  IOMUX configuration register
+ */
+typedef union {
+    struct {
+        /** iomux_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable iomux apb clock
+         */
+        uint32_t iomux_clk_en:1;
+        /** iomux_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset iomux module
+         */
+        uint32_t iomux_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_iomux_conf_reg_t;
+
+/** Type of iomux_clk_conf register
+ *  IOMUX_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+         *  FOSC, 3(default): XTAL.
+         */
+        uint32_t iomux_func_clk_sel:2;
+        /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable iomux function clock
+         */
+        uint32_t iomux_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_iomux_clk_conf_reg_t;
+
+/** Type of mem_monitor_conf register
+ *  MEM_MONITOR configuration register
+ */
+typedef union {
+    struct {
+        /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable mem_monitor clock
+         */
+        uint32_t mem_monitor_clk_en:1;
+        /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset mem_monitor module
+         */
+        uint32_t mem_monitor_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_mem_monitor_conf_reg_t;
+
+/** Type of regdma_conf register
+ *  REGDMA configuration register
+ */
+typedef union {
+    struct {
+        /** regdma_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable regdma clock
+         */
+        uint32_t regdma_clk_en:1;
+        /** regdma_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset regdma module
+         */
+        uint32_t regdma_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_regdma_conf_reg_t;
+
+/** Type of retention_conf register
+ *  retention configuration register
+ */
+typedef union {
+    struct {
+        /** retention_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable retention clock
+         */
+        uint32_t retention_clk_en:1;
+        /** retention_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset retention module
+         */
+        uint32_t retention_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_retention_conf_reg_t;
+
+/** Type of trace_conf register
+ *  TRACE configuration register
+ */
+typedef union {
+    struct {
+        /** trace_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable trace clock
+         */
+        uint32_t trace_clk_en:1;
+        /** trace_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset trace module
+         */
+        uint32_t trace_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_trace_conf_reg_t;
+
+/** Type of assist_conf register
+ *  ASSIST configuration register
+ */
+typedef union {
+    struct {
+        /** assist_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable assist clock
+         */
+        uint32_t assist_clk_en:1;
+        /** assist_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset assist module
+         */
+        uint32_t assist_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_assist_conf_reg_t;
+
+/** Type of cache_conf register
+ *  CACHE configuration register
+ */
+typedef union {
+    struct {
+        /** cache_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable cache clock
+         */
+        uint32_t cache_clk_en:1;
+        /** cache_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset cache module
+         */
+        uint32_t cache_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_cache_conf_reg_t;
+
+/** Type of modem_apb_conf register
+ *  MODEM_APB configuration register
+ */
+typedef union {
+    struct {
+        /** modem_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).
+         */
+        uint32_t modem_apb_clk_en:1;
+        /** modem_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set this file as 1 to reset modem-subsystem.
+         */
+        uint32_t modem_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_modem_apb_conf_reg_t;
+
+/** Type of timeout_conf register
+ *  TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset cpu_peri timeout module
+         */
+        uint32_t cpu_timeout_rst_en:1;
+        /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0;
+         *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
+         */
+        uint32_t hp_timeout_rst_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_timeout_conf_reg_t;
+
+/** Type of sysclk_conf register
+ *  SYSCLK configuration register
+ */
+typedef union {
+    struct {
+        /** ls_div_num : HRO; bitpos: [7:0]; default: 0;
+         *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
+         *  clock-source such as XTAL/FOSC.
+         */
+        uint32_t ls_div_num:8;
+        /** hs_div_num : HRO; bitpos: [15:8]; default: 2;
+         *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
+         */
+        uint32_t hs_div_num:8;
+        /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0;
+         *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
+         */
+        uint32_t soc_clk_sel:2;
+        uint32_t reserved_18:6;
+        /** clk_xtal_freq : RO; bitpos: [30:24]; default: 40;
+         *  This field indicates the frequency(MHz) of XTAL.
+         */
+        uint32_t clk_xtal_freq:7;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pcr_sysclk_conf_reg_t;
+
+/** Type of cpu_waiti_conf register
+ *  CPU_WAITI configuration register
+ */
+typedef union {
+    struct {
+        /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1;
+         *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
+         */
+        uint32_t cpuperiod_sel:2;
+        /** pll_freq_sel : HRO; bitpos: [2]; default: 1;
+         *  Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM
+         */
+        uint32_t pll_freq_sel:1;
+        /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
+         *  Set 1 to force cpu_waiti_clk enable.
+         */
+        uint32_t cpu_wait_mode_force_on:1;
+        /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0;
+         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+         *  will close
+         */
+        uint32_t cpu_waiti_delay_num:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} pcr_cpu_waiti_conf_reg_t;
+
+/** Type of cpu_freq_conf register
+ *  CPU_FREQ configuration register
+ */
+typedef union {
+    struct {
+        /** cpu_ls_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
+         *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM.
+         */
+        uint32_t cpu_ls_div_num:8;
+        /** cpu_hs_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set as one within (0,1,3) to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for high-speed
+         *  clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM.
+         */
+        uint32_t cpu_hs_div_num:8;
+        /** cpu_hs_120m_force : R/W; bitpos: [16]; default: 0;
+         *  Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz.
+         *  Only available when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL.
+         */
+        uint32_t cpu_hs_120m_force:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} pcr_cpu_freq_conf_reg_t;
+
+/** Type of ahb_freq_conf register
+ *  AHB_FREQ configuration register
+ */
+typedef union {
+    struct {
+        /** ahb_ls_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set as one within (0,1,3,7) to generate clk_ahb driven by clk_hproot. The clk_ahb
+         *  is div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
+         *  low-speed clock-source such as XTAL/FOSC, and should be used together with
+         *  PCR_CPU_LS_DIV_NUM.
+         */
+        uint32_t ahb_ls_div_num:8;
+        /** ahb_hs_div_num : R/W; bitpos: [15:8]; default: 3;
+         *  Set as one within (3,7,15) to generate clk_ahb driven by clk_hproot. The clk_ahb is
+         *  div4(default)/div8/div16 of clk_hproot. This field is only available for high-speed
+         *  clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM.
+         */
+        uint32_t ahb_hs_div_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcr_ahb_freq_conf_reg_t;
+
+/** Type of apb_freq_conf register
+ *  APB_FREQ configuration register
+ */
+typedef union {
+    struct {
+        /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
+         *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
+         *  recover to the previous frequency when a new access appears on apb-bus. Set as one
+         *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
+         *  that enable this function will reduce performance. Users can set this field as zero
+         *  to disable the auto-decrease-apb-freq function. By default, this function is
+         *  disable.
+         */
+        uint32_t apb_decrease_div_num:8;
+        /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
+         *  div1(default)/div2/div4 of clk_ahb.
+         */
+        uint32_t apb_div_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcr_apb_freq_conf_reg_t;
+
+/** Type of pll_div_clk_en register
+ *  SPLL DIV clock-gating configuration register
+ */
+typedef union {
+    struct {
+        /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
+         *  This field is used to open 240 MHz clock (div2 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_240m_clk_en:1;
+        /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
+         *  This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_160m_clk_en:1;
+        /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
+         *  This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_120m_clk_en:1;
+        /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
+         *  This field is used to open 80 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_80m_clk_en:1;
+        /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1;
+         *  This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_48m_clk_en:1;
+        /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1;
+         *  This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_40m_clk_en:1;
+        /** pll_20m_clk_en : R/W; bitpos: [6]; default: 1;
+         *  This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_20m_clk_en:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} pcr_pll_div_clk_en_reg_t;
+
+/** Type of ctrl_clk_out_en register
+ *  CLK_OUT_EN configuration register
+ */
+typedef union {
+    struct {
+        /** clk20_oen : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable 20m clock
+         */
+        uint32_t clk20_oen:1;
+        /** clk22_oen : R/W; bitpos: [1]; default: 1;
+         *  Set 1 to enable 22m clock
+         */
+        uint32_t clk22_oen:1;
+        /** clk44_oen : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to enable 44m clock
+         */
+        uint32_t clk44_oen:1;
+        /** clk_bb_oen : R/W; bitpos: [3]; default: 1;
+         *  Set 1 to enable bb clock
+         */
+        uint32_t clk_bb_oen:1;
+        /** clk80_oen : R/W; bitpos: [4]; default: 1;
+         *  Set 1 to enable 80m clock
+         */
+        uint32_t clk80_oen:1;
+        /** clk160_oen : R/W; bitpos: [5]; default: 1;
+         *  Set 1 to enable 160m clock
+         */
+        uint32_t clk160_oen:1;
+        /** clk_320m_oen : R/W; bitpos: [6]; default: 1;
+         *  Set 1 to enable 320m clock
+         */
+        uint32_t clk_320m_oen:1;
+        /** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1;
+         *  Reserved
+         */
+        uint32_t clk_adc_inf_oen:1;
+        /** clk_dac_cpu_oen : R/W; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t clk_dac_cpu_oen:1;
+        /** clk40x_bb_oen : R/W; bitpos: [9]; default: 1;
+         *  Set 1 to enable 40x_bb clock
+         */
+        uint32_t clk40x_bb_oen:1;
+        /** clk_xtal_oen : R/W; bitpos: [10]; default: 1;
+         *  Set 1 to enable xtal clock
+         */
+        uint32_t clk_xtal_oen:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} pcr_ctrl_clk_out_en_reg_t;
+
+/** Type of ctrl_tick_conf register
+ *  TICK configuration register
+ */
+typedef union {
+    struct {
+        /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39;
+         *  ******* Description ***********
+         */
+        uint32_t xtal_tick_num:8;
+        /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7;
+         *  ******* Description ***********
+         */
+        uint32_t fosc_tick_num:8;
+        /** tick_enable : R/W; bitpos: [16]; default: 1;
+         *  ******* Description ***********
+         */
+        uint32_t tick_enable:1;
+        /** rst_tick_cnt : R/W; bitpos: [17]; default: 0;
+         *  ******* Description ***********
+         */
+        uint32_t rst_tick_cnt:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} pcr_ctrl_tick_conf_reg_t;
+
+/** Type of ctrl_32k_conf register
+ *  32KHz clock configuration register
+ */
+typedef union {
+    struct {
+        /** clk_32k_sel : R/W; bitpos: [1:0]; default: 0;
+         *  This field indicates which one 32KHz clock will be used by timergroup.
+         *  0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
+         */
+        uint32_t clk_32k_sel:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_ctrl_32k_conf_reg_t;
+
+/** Type of sram_power_conf register
+ *  HP SRAM/ROM configuration register
+ */
+typedef union {
+    struct {
+        /** sram_force_pu : R/W; bitpos: [3:0]; default: 15;
+         *  Set this bit to force power up SRAM
+         */
+        uint32_t sram_force_pu:4;
+        /** sram_force_pd : R/W; bitpos: [7:4]; default: 0;
+         *  Set this bit to force power down SRAM.
+         */
+        uint32_t sram_force_pd:4;
+        /** sram_clkgate_force_on : R/W; bitpos: [11:8]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
+         *  gate-clock will be used when accessing the SRAM.
+         */
+        uint32_t sram_clkgate_force_on:4;
+        /** rom_force_pu : R/W; bitpos: [14:12]; default: 7;
+         *  Set this bit to force power up ROM
+         */
+        uint32_t rom_force_pu:3;
+        /** rom_force_pd : R/W; bitpos: [17:15]; default: 0;
+         *  Set this bit to force power down ROM.
+         */
+        uint32_t rom_force_pd:3;
+        /** rom_clkgate_force_on : R/W; bitpos: [20:18]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
+         *  gate-clock will be used when accessing the ROM.
+         */
+        uint32_t rom_clkgate_force_on:3;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} pcr_sram_power_conf_reg_t;
+
+/** Type of reset_event_bypass register
+ *  reset event bypass backdoor configuration register
+ */
+typedef union {
+    struct {
+        /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0;
+         *  This field is used to control reset event relationship for
+         *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
+         *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
+         *  will not only be reset by power-reset, but also some reset event.
+         */
+        uint32_t reset_event_bypass_apm:1;
+        /** reset_event_bypass : R/W; bitpos: [1]; default: 1;
+         *  This field is used to control reset event relationship for system-bus. 1: system
+         *  bus (including arbiter/router) will only be reset by power-reset. some reset event
+         *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
+         *  power-reset, but also some reset event.
+         */
+        uint32_t reset_event_bypass:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_reset_event_bypass_reg_t;
+
+/** Type of clock_gate register
+ *  PCR clock gating configure register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to force on clock gating.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} pcr_clock_gate_reg_t;
+
+
+/** Group: Frequency Statistics Register */
+/** Type of sysclk_freq_query_0 register
+ *  SYSCLK frequency query 0 register
+ */
+typedef union {
+    struct {
+        /** fosc_freq : HRO; bitpos: [7:0]; default: 20;
+         *  This field indicates the frequency(MHz) of FOSC.
+         */
+        uint32_t fosc_freq:8;
+        /** pll_freq : HRO; bitpos: [17:8]; default: 480;
+         *  This field indicates the frequency(MHz) of SPLL.
+         */
+        uint32_t pll_freq:10;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} pcr_sysclk_freq_query_0_reg_t;
+
+
+/** Group: FPGA Debug Register */
+/** Type of fpga_debug register
+ *  fpga debug register
+ */
+typedef union {
+    struct {
+        /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Only used in fpga debug.
+         */
+        uint32_t fpga_debug:32;
+    };
+    uint32_t val;
+} pcr_fpga_debug_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35676496;
+         *  PCR version information.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} pcr_date_reg_t;
+
+
+typedef struct pcr_dev_t {
+    volatile pcr_uart0_conf_reg_t uart0_conf;
+    volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf;
+    volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl;
+    volatile pcr_uart1_conf_reg_t uart1_conf;
+    volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf;
+    volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl;
+    volatile pcr_mspi_conf_reg_t mspi_conf;
+    volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf;
+    volatile pcr_i2c_conf_reg_t i2c_conf;
+    volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
+    volatile pcr_uhci_conf_reg_t uhci_conf;
+    volatile pcr_rmt_conf_reg_t rmt_conf;
+    volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf;
+    volatile pcr_ledc_conf_reg_t ledc_conf;
+    volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf;
+    volatile pcr_timergroup0_conf_reg_t timergroup0_conf;
+    volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf;
+    volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf;
+    volatile pcr_timergroup1_conf_reg_t timergroup1_conf;
+    volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf;
+    volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf;
+    volatile pcr_systimer_conf_reg_t systimer_conf;
+    volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf;
+    volatile pcr_twai0_conf_reg_t twai0_conf;
+    volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf;
+    volatile pcr_twai1_conf_reg_t twai1_conf;
+    volatile pcr_twai1_func_clk_conf_reg_t twai1_func_clk_conf;
+    volatile pcr_i2s_conf_reg_t i2s_conf;
+    volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf;
+    volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf;
+    volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf;
+    volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf;
+    volatile pcr_saradc_conf_reg_t saradc_conf;
+    volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf;
+    volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf;
+    volatile pcr_usb_device_conf_reg_t usb_device_conf;
+    volatile pcr_intmtx_conf_reg_t intmtx_conf;
+    volatile pcr_pcnt_conf_reg_t pcnt_conf;
+    volatile pcr_etm_conf_reg_t etm_conf;
+    volatile pcr_pwm_conf_reg_t pwm_conf;
+    volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf;
+    volatile pcr_parl_io_conf_reg_t parl_io_conf;
+    volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf;
+    volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf;
+    volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf;
+    volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf;
+    volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf;
+    volatile pcr_gdma_conf_reg_t gdma_conf;
+    volatile pcr_spi2_conf_reg_t spi2_conf;
+    volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf;
+    volatile pcr_aes_conf_reg_t aes_conf;
+    volatile pcr_sha_conf_reg_t sha_conf;
+    volatile pcr_rsa_conf_reg_t rsa_conf;
+    volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
+    volatile pcr_ecc_conf_reg_t ecc_conf;
+    volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
+    volatile pcr_ds_conf_reg_t ds_conf;
+    volatile pcr_hmac_conf_reg_t hmac_conf;
+    volatile pcr_iomux_conf_reg_t iomux_conf;
+    volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf;
+    volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf;
+    volatile pcr_regdma_conf_reg_t regdma_conf;
+    volatile pcr_retention_conf_reg_t retention_conf;
+    volatile pcr_trace_conf_reg_t trace_conf;
+    volatile pcr_assist_conf_reg_t assist_conf;
+    volatile pcr_cache_conf_reg_t cache_conf;
+    volatile pcr_modem_apb_conf_reg_t modem_apb_conf;
+    volatile pcr_timeout_conf_reg_t timeout_conf;
+    volatile pcr_sysclk_conf_reg_t sysclk_conf;
+    volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf;
+    volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf;
+    volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf;
+    volatile pcr_apb_freq_conf_reg_t apb_freq_conf;
+    volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0;
+    volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en;
+    volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en;
+    volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf;
+    volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf;
+    volatile pcr_sram_power_conf_reg_t sram_power_conf;
+    uint32_t reserved_13c[941];
+    volatile pcr_reset_event_bypass_reg_t reset_event_bypass;
+    volatile pcr_fpga_debug_reg_t fpga_debug;
+    volatile pcr_clock_gate_reg_t clock_gate;
+    volatile pcr_date_reg_t date;
+} pcr_dev_t;
+
+extern pcr_dev_t PCR;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/plic_reg.h b/components/soc/esp32c6/register/soc/plic_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/plic_reg.h
rename to components/soc/esp32c6/register/soc/plic_reg.h
diff --git a/components/soc/esp32c6/include/soc/pmu_reg.h b/components/soc/esp32c6/register/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/pmu_reg.h
rename to components/soc/esp32c6/register/soc/pmu_reg.h
diff --git a/components/soc/esp32c6/register/soc/pmu_struct.h b/components/soc/esp32c6/register/soc/pmu_struct.h
new file mode 100644
index 00000000000..db545cfbc58
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/pmu_struct.h
@@ -0,0 +1,756 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "soc/soc.h"
+#include "soc/pmu_reg.h"
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t vdd_spi_pd_en: 1;
+        uint32_t mem_dslp     : 1;
+        uint32_t mem_pd_en    : 4;
+        uint32_t wifi_pd_en   : 1;
+        uint32_t reserved1    : 1;
+        uint32_t cpu_pd_en    : 1;
+        uint32_t aon_pd_en    : 1;
+        uint32_t top_pd_en    : 1;
+    };
+    uint32_t val;
+} pmu_hp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 30;
+        uint32_t code     : 2;
+    };
+    uint32_t val;
+} pmu_hp_icg_modem_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 24;
+        uint32_t uart_wakeup_en : 1;
+        uint32_t lp_pad_hold_all: 1;
+        uint32_t hp_pad_hold_all: 1;
+        uint32_t dig_pad_slp_sel: 1;
+        uint32_t dig_pause_wdt  : 1;
+        uint32_t dig_cpu_stall  : 1;
+        uint32_t reserved1      : 2;
+    };
+    uint32_t val;
+} pmu_hp_sys_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 26;
+        uint32_t i2c_iso_en   : 1;
+        uint32_t i2c_retention: 1;
+        uint32_t xpd_bb_i2c   : 1;
+        uint32_t xpd_bbpll_i2c: 1;
+        uint32_t xpd_bbpll    : 1;
+        uint32_t reserved1    : 1;
+    };
+    uint32_t val;
+} pmu_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_hp_bias_reg_t;
+
+typedef union {
+    struct {    /* HP: Active State */
+        uint32_t reserved0                            : 4;
+        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
+        uint32_t hp_modem2active_backup_modem_clk_code: 2;
+        uint32_t reserved1                            : 2;
+        uint32_t hp_active_retention_mode             : 1;
+        uint32_t hp_sleep2active_retention_en         : 1;
+        uint32_t hp_modem2active_retention_en         : 1;
+        uint32_t reserved2                            : 1;
+        uint32_t hp_sleep2active_backup_clk_sel       : 2;
+        uint32_t hp_modem2active_backup_clk_sel       : 2;
+        uint32_t reserved3                            : 2;
+        uint32_t hp_sleep2active_backup_mode          : 3;
+        uint32_t hp_modem2active_backup_mode          : 3;
+        uint32_t reserved4                            : 3;
+        uint32_t hp_sleep2active_backup_en            : 1;
+        uint32_t hp_modem2active_backup_en            : 1;
+        uint32_t reserved5                            : 1;
+    };
+    struct {    /* HP: Modem State */
+        uint32_t reserved6                            : 4;
+        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
+        uint32_t reserved7                            : 4;
+        uint32_t hp_modem_retention_mode              : 1;
+        uint32_t hp_sleep2modem_retention_en          : 1;
+        uint32_t reserved8                            : 2;
+        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
+        uint32_t reserved9                            : 4;
+        uint32_t hp_sleep2modem_backup_mode           : 3;
+        uint32_t reserved10                           : 6;
+        uint32_t hp_sleep2modem_backup_en             : 1;
+        uint32_t reserved11                           : 2;
+    };
+    struct {    /* HP: Sleep State */
+        uint32_t reserved12                           : 6;
+        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
+        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
+        uint32_t hp_sleep_retention_mode              : 1;
+        uint32_t reserved13                           : 1;
+        uint32_t hp_modem2sleep_retention_en          : 1;
+        uint32_t hp_active2sleep_retention_en         : 1;
+        uint32_t reserved14                           : 2;
+        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
+        uint32_t hp_active2sleep_backup_clk_sel       : 2;
+        uint32_t reserved15                           : 3;
+        uint32_t hp_modem2sleep_backup_mode           : 3;
+        uint32_t hp_active2sleep_backup_mode          : 3;
+        uint32_t reserved16                           : 1;
+        uint32_t hp_modem2sleep_backup_en             : 1;
+        uint32_t hp_active2sleep_backup_en            : 1;
+    };
+    uint32_t val;
+} pmu_hp_backup_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0       : 26;
+        uint32_t dig_sysclk_nodiv: 1;
+        uint32_t icg_sysclk_en   : 1;
+        uint32_t sysclk_slp_sel  : 1;
+        uint32_t icg_slp_sel     : 1;
+        uint32_t dig_sysclk_sel  : 2;
+    };
+    uint32_t val;
+} pmu_hp_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t slp_mem_xpd    : 1;
+        uint32_t slp_logic_xpd  : 1;
+        uint32_t xpd            : 1;
+        uint32_t slp_mem_dbias  : 4;
+        uint32_t slp_logic_dbias: 4;
+        uint32_t dbias          : 5;
+    };
+    uint32_t val;
+} pmu_hp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 8;
+        uint32_t drv_b    : 24;
+    };
+    uint32_t val;
+} pmu_hp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_hp_xtal_reg_t;
+
+typedef struct pmu_hp_hw_regmap_t{
+    pmu_hp_dig_power_reg_t     dig_power;
+    uint32_t                   icg_func;
+    uint32_t                   icg_apb;
+    pmu_hp_icg_modem_reg_t     icg_modem;
+    pmu_hp_sys_cntl_reg_t      syscntl;
+    pmu_hp_clk_power_reg_t     clk_power;
+    pmu_hp_bias_reg_t          bias;
+    pmu_hp_backup_reg_t        backup;
+    uint32_t                   backup_clk;
+    pmu_hp_sysclk_reg_t        sysclk;
+    pmu_hp_regulator0_reg_t    regulator0;
+    pmu_hp_regulator1_reg_t    regulator1;
+    pmu_hp_xtal_reg_t          xtal;
+} pmu_hp_hw_regmap_t;
+
+/** */
+typedef union {
+    struct {
+        uint32_t reserved0: 21;
+        uint32_t slp_xpd  : 1;
+        uint32_t xpd	  : 1;
+        uint32_t slp_dbias: 4;
+        uint32_t dbias    : 5;
+    };
+    uint32_t val;
+} pmu_lp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 28;
+        uint32_t drv_b    : 4;
+    };
+    uint32_t val;
+} pmu_lp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_lp_xtal_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 30;
+        uint32_t mem_dslp  : 1;
+        uint32_t peri_pd_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0  : 28;
+        uint32_t xpd_xtal32k: 1;
+        uint32_t xpd_rc32k  : 1;
+        uint32_t xpd_fosc   : 1;
+        uint32_t pd_osc     : 1;
+    };
+    uint32_t val;
+} pmu_lp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_lp_bias_reg_t;
+
+typedef struct pmu_lp_hw_regmap_t{
+    pmu_lp_regulator0_reg_t    regulator0;
+    pmu_lp_regulator1_reg_t    regulator1;
+    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
+    pmu_lp_dig_power_reg_t     dig_power;
+    pmu_lp_clk_power_reg_t     clk_power;
+    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
+} pmu_lp_hw_regmap_t;
+
+
+typedef union {
+    struct {
+        uint32_t tie_low_global_bbpll_icg : 1;
+        uint32_t tie_low_global_xtal_icg  : 1;
+        uint32_t tie_low_i2c_retention    : 1;
+        uint32_t tie_low_xpd_bb_i2c       : 1;
+        uint32_t tie_low_xpd_bbpll_i2c    : 1;
+        uint32_t tie_low_xpd_bbpll        : 1;
+        uint32_t tie_low_xpd_xtal         : 1;
+        uint32_t reserved0                : 18;
+        uint32_t tie_high_global_bbpll_icg: 1;
+        uint32_t tie_high_global_xtal_icg : 1;
+        uint32_t tie_high_i2c_retention   : 1;
+        uint32_t tie_high_xpd_bb_i2c      : 1;
+        uint32_t tie_high_xpd_bbpll_i2c   : 1;
+        uint32_t tie_high_xpd_bbpll       : 1;
+        uint32_t tie_high_xpd_xtal        : 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 28;
+        uint32_t update_dig_icg_switch: 1;
+        uint32_t tie_low_icg_slp_sel  : 1;
+        uint32_t tie_high_icg_slp_sel : 1;
+        uint32_t update_dig_sysclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_sleep_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0             : 31;
+        uint32_t update_dig_icg_func_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_func_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 31;
+        uint32_t update_dig_icg_apb_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_apb_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 31;
+        uint32_t update_dig_icg_modem_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_modem_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 30;
+        uint32_t tie_low_lp_rootclk_sel : 1;
+        uint32_t tie_high_lp_rootclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_lp_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0               : 28;
+        uint32_t tie_high_lp_pad_hold_all: 1;
+        uint32_t tie_low_lp_pad_hold_all : 1;
+        uint32_t tie_high_hp_pad_hold_all: 1;
+        uint32_t tie_low_hp_pad_hold_all : 1;
+    };
+    uint32_t val;
+} pmu_imm_pad_hold_all_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 30;
+        uint32_t tie_high_i2c_iso_en: 1;
+        uint32_t tie_low_i2c_iso_en : 1;
+    };
+    uint32_t val;
+} pmu_imm_i2c_isolate_reg_t;
+
+typedef struct pmu_imm_hw_regmap_t{
+    pmu_imm_hp_clk_power_reg_t     clk_power;
+    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
+    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
+    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
+    pmu_imm_modem_icg_reg_t        modem_icg;
+    pmu_imm_lp_icg_reg_t           lp_icg;
+    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
+    pmu_imm_i2c_isolate_reg_t      i2c_iso;
+} pmu_imm_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 9;
+        uint32_t powerdown_timer: 7;
+        uint32_t powerup_timer  : 7;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_reset   : 1;
+        uint32_t force_iso     : 1;
+        uint32_t force_pu      : 1;
+        uint32_t force_no_reset: 1;
+        uint32_t force_no_iso  : 1;
+        uint32_t force_pd      : 1;
+        uint32_t mask          : 5;     /* Invalid of lp peripherals */
+        uint32_t reserved0     : 16;    /* Invalid of lp peripherals */
+        uint32_t pd_mask       : 5;     /* Invalid of lp peripherals */
+    };
+    uint32_t val;
+} pmu_power_domain_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_mem_iso   : 4;
+        uint32_t force_hp_mem_pd    : 4;
+        uint32_t reserved0          : 16;
+        uint32_t force_hp_mem_no_iso: 4;
+        uint32_t force_hp_mem_pu    : 4;
+    };
+    uint32_t val;
+} pmu_power_memory_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t mem2_pd_mask: 5;
+        uint32_t mem1_pd_mask: 5;
+        uint32_t mem0_pd_mask: 5;
+        uint32_t reserved0   : 2;
+        uint32_t mem2_mask   : 5;
+        uint32_t mem1_mask   : 5;
+        uint32_t mem0_mask   : 5;
+    };
+    uint32_t val;
+} pmu_power_memory_mask_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_pad_no_iso_all: 1;
+        uint32_t force_hp_pad_iso_all   : 1;
+        uint32_t reserved0              : 30;
+    };
+    uint32_t val;
+} pmu_power_hp_pad_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 18;
+        uint32_t pwr_wait  : 11;
+        uint32_t pwr_sw    : 2;
+        uint32_t pwr_sel_sw: 1;
+    };
+    uint32_t val;
+} pmu_power_vdd_spi_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wait_xtal_stable: 16;
+        uint32_t wait_pll_stable : 16;
+    };
+    uint32_t val;
+} pmu_power_clk_wait_cntl_reg_t;
+
+typedef struct pmu_power_hw_regmap_t{
+    pmu_power_wait_timer0_reg_t    wait_timer0;
+    pmu_power_wait_timer1_reg_t    wait_timer1;
+    pmu_power_domain_cntl_reg_t    hp_pd[5];
+    pmu_power_domain_cntl_reg_t    lp_peri;
+    pmu_power_memory_cntl_reg_t    mem_cntl;
+    pmu_power_memory_mask_reg_t    mem_mask;
+    pmu_power_hp_pad_reg_t         hp_pad;
+    pmu_power_vdd_spi_cntl_reg_t   vdd_spi;
+    pmu_power_clk_wait_cntl_reg_t  clk_wait;
+} pmu_power_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_ena: 31;
+        uint32_t slp_reject_en   : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t lp_min_slp_val: 8;
+        uint32_t hp_min_slp_val: 8;
+        uint32_t sleep_prt_sel : 2;
+        uint32_t reserved0     : 14;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0           : 31;
+        uint32_t slp_reject_cause_clr: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modem_wait_target : 20;
+        uint32_t reserved0         : 4;
+        uint32_t lp_ana_wait_target: 8;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl5_reg_t;
+
+typedef union {
+    struct {
+        uint32_t soc_wakeup_wait    : 20;
+        uint32_t reserved0          : 10;
+        uint32_t soc_wakeup_wait_cfg: 2;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl6_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 16;
+        uint32_t ana_wait_target: 16;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl7_reg_t;
+
+typedef struct pmu_wakeup_hw_regmap_t{
+    pmu_slp_wakeup_cntl0_reg_t     cntl0;
+    pmu_slp_wakeup_cntl1_reg_t     cntl1;
+    uint32_t                       cntl2;
+    pmu_slp_wakeup_cntl3_reg_t     cntl3;
+    pmu_slp_wakeup_cntl4_reg_t     cntl4;
+    pmu_slp_wakeup_cntl5_reg_t     cntl5;
+    pmu_slp_wakeup_cntl6_reg_t     cntl6;
+    pmu_slp_wakeup_cntl7_reg_t     cntl7;
+    uint32_t                       status0;
+    uint32_t                       status1;
+} pmu_wakeup_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t i2c_por_wait_target: 8;
+        uint32_t reserved0          : 24;
+    };
+    uint32_t val;
+} pmu_hp_clk_poweron_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modify_icg_cntl_wait: 8;
+        uint32_t switch_icg_cntl_wait: 8;
+        uint32_t reserved0           : 16;
+    };
+    uint32_t val;
+} pmu_hp_clk_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t por_done : 1;
+    };
+    uint32_t val;
+} pmu_por_status_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0     : 26;
+        uint32_t perif_i2c_rstb: 1;
+        uint32_t xpd_perif_i2c : 1;
+        uint32_t xpd_txrf_i2c  : 1;
+        uint32_t xpd_rfrx_pbus : 1;
+        uint32_t xpd_ckgen_i2c : 1;
+        uint32_t xpd_pll_i2c   : 1;
+    };
+    uint32_t val;
+} pmu_rf_pwc_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t backup_sysclk_nodiv: 1;
+    };
+    uint32_t val;
+} pmu_backup_cfg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 27;
+        uint32_t lp_cpu_exc: 1;
+        uint32_t sdio_idle : 1;
+        uint32_t sw        : 1;
+        uint32_t reject    : 1;
+        uint32_t wakeup    : 1;
+    };
+    uint32_t val;
+} pmu_hp_intr_reg_t;
+
+typedef struct pmu_hp_ext_hw_regmap_t{
+    pmu_hp_clk_poweron_reg_t   clk_poweron;
+    pmu_hp_clk_cntl_reg_t      clk_cntl;
+    pmu_por_status_reg_t       por_status;
+    pmu_rf_pwc_reg_t           rf_pwc;
+    pmu_backup_cfg_reg_t       backup_cfg;
+    pmu_hp_intr_reg_t          int_raw;
+    pmu_hp_intr_reg_t          int_st;
+    pmu_hp_intr_reg_t          int_ena;
+    pmu_hp_intr_reg_t          int_clr;
+} pmu_hp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0                : 20;
+        uint32_t lp_cpu_wakeup            : 1;
+        uint32_t modem_switch_active_end  : 1;
+        uint32_t sleep_switch_active_end  : 1;
+        uint32_t sleep_switch_modem_end   : 1;
+        uint32_t modem_switch_sleep_end   : 1;
+        uint32_t active_swtich_sleep_end  : 1;
+        uint32_t modem_switch_active_start: 1;
+        uint32_t sleep_switch_active_start: 1;
+        uint32_t sleep_switch_modem_start : 1;
+        uint32_t modem_switch_sleep_start : 1;
+        uint32_t active_switch_sleep_start: 1;
+        uint32_t sw_trigger               : 1;
+    };
+    uint32_t val;
+} pmu_lp_intr_reg_t;
+
+typedef union {
+    struct {
+        uint32_t waiti_rdy         : 1;
+        uint32_t stall_rdy         : 1;
+        uint32_t reserved0         : 16;
+        uint32_t force_stall       : 1;
+        uint32_t slp_waiti_flag_en : 1;
+        uint32_t slp_stall_flag_en : 1;
+        uint32_t slp_stall_wait    : 8;
+        uint32_t slp_stall_en      : 1;
+        uint32_t slp_reset_en      : 1;
+        uint32_t slp_bypass_intr_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_en: 16;
+        uint32_t reserved0: 15;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr1_reg_t;
+
+typedef struct pmu_lp_ext_hw_regmap_t{
+    pmu_lp_intr_reg_t          int_raw;
+    pmu_lp_intr_reg_t          int_st;
+    pmu_lp_intr_reg_t          int_ena;
+    pmu_lp_intr_reg_t          int_clr;
+    pmu_lp_cpu_pwr0_reg_t      pwr0;
+    pmu_lp_cpu_pwr1_reg_t      pwr1;
+} pmu_lp_ext_hw_regmap_t;
+
+typedef struct pmu_dev_t{
+    volatile pmu_hp_hw_regmap_t     hp_sys[3];
+    volatile pmu_lp_hw_regmap_t     lp_sys[2];
+    volatile pmu_imm_hw_regmap_t    imm;
+    volatile pmu_power_hw_regmap_t  power;
+    volatile pmu_wakeup_hw_regmap_t wakeup;
+    volatile pmu_hp_ext_hw_regmap_t hp_ext;
+    volatile pmu_lp_ext_hw_regmap_t lp_ext;
+
+    union {
+        struct {
+            uint32_t reserved0    : 30;
+            volatile uint32_t lp_trigger_hp: 1;
+            volatile uint32_t hp_trigger_lp: 1;
+        };
+        volatile uint32_t val;
+    } hp_lp_cpu_comm;
+
+    union {
+        struct {
+            uint32_t reserved0           : 31;
+            volatile uint32_t dig_regulator_en_cal: 1;
+        };
+        volatile uint32_t val;
+    } hp_regulator_cfg;
+
+    union {
+        struct {
+            uint32_t reserved0 : 11;
+            volatile uint32_t last_st   : 7;
+            volatile uint32_t target_st : 7;
+            volatile uint32_t current_st: 7;
+        };
+        volatile uint32_t val;
+    } main_state;
+
+    union {
+        struct {
+            uint32_t reserved0: 13;
+            volatile uint32_t backup_st: 5;
+            volatile uint32_t lp_pwr_st: 5;
+            volatile uint32_t hp_pwr_st: 9;
+        };
+        volatile uint32_t val;
+    } pwr_state;
+
+    union {
+        struct {
+            volatile uint32_t stable_xpd_bbpll : 1;
+            volatile uint32_t stable_xpd_xtal  : 1;
+            volatile uint32_t reserved0        : 13;
+            volatile uint32_t sysclk_slp_sel   : 1;
+            volatile uint32_t sysclk_sel       : 2;
+            volatile uint32_t sysclk_nodiv     : 1;
+            volatile uint32_t icg_sysclk_en    : 1;
+            volatile uint32_t icg_modem_switch : 1;
+            volatile uint32_t icg_modem_code   : 2;
+            volatile uint32_t icg_slp_sel      : 1;
+            volatile uint32_t icg_global_xtal  : 1;
+            volatile uint32_t icg_global_pll   : 1;
+            volatile uint32_t ana_i2c_iso_en   : 1;
+            volatile uint32_t ana_i2c_retention: 1;
+            volatile uint32_t ana_xpd_bb_i2c   : 1;
+            volatile uint32_t ana_xpd_bbpll_i2c: 1;
+            volatile uint32_t ana_xpd_bbpll    : 1;
+            volatile uint32_t ana_xpd_xtal     : 1;
+        };
+        volatile uint32_t val;
+    } clk_state0;
+
+    volatile uint32_t clk_state1;
+    volatile uint32_t clk_state2;
+
+    union {
+        struct {
+            uint32_t reserved0             : 31;
+            volatile uint32_t stable_vdd_spi_pwr_drv: 1;
+        };
+        volatile uint32_t val;
+    } vdd_spi_status;
+
+    uint32_t reserved[150];
+
+    union {
+        struct {
+            volatile uint32_t pmu_date: 31;
+            volatile uint32_t clk_en  : 1;
+        };
+        volatile uint32_t val;
+    } date;
+} pmu_dev_t;
+
+extern pmu_dev_t PMU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
+
+_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/reg_base.h b/components/soc/esp32c6/register/soc/reg_base.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/reg_base.h
rename to components/soc/esp32c6/register/soc/reg_base.h
diff --git a/components/soc/esp32c6/include/soc/rmt_reg.h b/components/soc/esp32c6/register/soc/rmt_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/rmt_reg.h
rename to components/soc/esp32c6/register/soc/rmt_reg.h
diff --git a/components/soc/esp32c6/include/soc/rmt_struct.h b/components/soc/esp32c6/register/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/rmt_struct.h
rename to components/soc/esp32c6/register/soc/rmt_struct.h
diff --git a/components/soc/esp32c6/include/soc/rsa_reg.h b/components/soc/esp32c6/register/soc/rsa_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/rsa_reg.h
rename to components/soc/esp32c6/register/soc/rsa_reg.h
diff --git a/components/soc/esp32c6/include/soc/rsa_struct.h b/components/soc/esp32c6/register/soc/rsa_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/rsa_struct.h
rename to components/soc/esp32c6/register/soc/rsa_struct.h
diff --git a/components/soc/esp32c6/register/soc/sha_reg.h b/components/soc/esp32c6/register/soc/sha_reg.h
new file mode 100644
index 00000000000..46955176e5a
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/sha_reg.h
@@ -0,0 +1,172 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SHA_MODE_REG register
+ *  Initial configuration register.
+ */
+#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
+/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Sha mode.
+ */
+#define SHA_MODE    0x00000007U
+#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
+#define SHA_MODE_V  0x00000007U
+#define SHA_MODE_S  0
+
+/** SHA_T_STRING_REG register
+ *  SHA 512/t configuration register 0.
+ */
+#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
+/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
+ *  Sha t_string (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_STRING    0xFFFFFFFFU
+#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
+#define SHA_T_STRING_V  0xFFFFFFFFU
+#define SHA_T_STRING_S  0
+
+/** SHA_T_LENGTH_REG register
+ *  SHA 512/t configuration register 1.
+ */
+#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
+/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
+ *  Sha t_length (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_LENGTH    0x0000003FU
+#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
+#define SHA_T_LENGTH_V  0x0000003FU
+#define SHA_T_LENGTH_S  0
+
+/** SHA_DMA_BLOCK_NUM_REG register
+ *  DMA configuration register 0.
+ */
+#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
+/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
+ *  Dma-sha block number.
+ */
+#define SHA_DMA_BLOCK_NUM    0x0000003FU
+#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
+#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
+#define SHA_DMA_BLOCK_NUM_S  0
+
+/** SHA_START_REG register
+ *  Typical SHA configuration register 0.
+ */
+#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
+/** SHA_START : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_START    0x7FFFFFFFU
+#define SHA_START_M  (SHA_START_V << SHA_START_S)
+#define SHA_START_V  0x7FFFFFFFU
+#define SHA_START_S  1
+
+/** SHA_CONTINUE_REG register
+ *  Typical SHA configuration register 1.
+ */
+#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
+/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_CONTINUE    0x7FFFFFFFU
+#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
+#define SHA_CONTINUE_V  0x7FFFFFFFU
+#define SHA_CONTINUE_S  1
+
+/** SHA_BUSY_REG register
+ *  Busy register.
+ */
+#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
+/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Sha busy state. 1'b0: idle. 1'b1: busy.
+ */
+#define SHA_BUSY_STATE    (BIT(0))
+#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
+#define SHA_BUSY_STATE_V  0x00000001U
+#define SHA_BUSY_STATE_S  0
+
+/** SHA_DMA_START_REG register
+ *  DMA configuration register 1.
+ */
+#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
+/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
+ *  Start dma-sha.
+ */
+#define SHA_DMA_START    (BIT(0))
+#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
+#define SHA_DMA_START_V  0x00000001U
+#define SHA_DMA_START_S  0
+
+/** SHA_DMA_CONTINUE_REG register
+ *  DMA configuration register 2.
+ */
+#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
+/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Continue dma-sha.
+ */
+#define SHA_DMA_CONTINUE    (BIT(0))
+#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
+#define SHA_DMA_CONTINUE_V  0x00000001U
+#define SHA_DMA_CONTINUE_S  0
+
+/** SHA_CLEAR_IRQ_REG register
+ *  Interrupt clear register.
+ */
+#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
+/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
+ *  Clear sha interrupt.
+ */
+#define SHA_CLEAR_INTERRUPT    (BIT(0))
+#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
+#define SHA_CLEAR_INTERRUPT_V  0x00000001U
+#define SHA_CLEAR_INTERRUPT_S  0
+
+/** SHA_IRQ_ENA_REG register
+ *  Interrupt enable register.
+ */
+#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
+/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+ */
+#define SHA_INTERRUPT_ENA    (BIT(0))
+#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
+#define SHA_INTERRUPT_ENA_V  0x00000001U
+#define SHA_INTERRUPT_ENA_S  0
+
+/** SHA_DATE_REG register
+ *  Date register.
+ */
+#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
+/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
+ *  Sha date information/ sha version information.
+ */
+#define SHA_DATE    0x3FFFFFFFU
+#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
+#define SHA_DATE_V  0x3FFFFFFFU
+#define SHA_DATE_S  0
+
+/** SHA_H_MEM register
+ *  Sha H memory which contains intermediate hash or final hash.
+ */
+#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
+#define SHA_H_MEM_SIZE_BYTES 64
+
+/** SHA_M_MEM register
+ *  Sha M memory which contains message.
+ */
+#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
+#define SHA_M_MEM_SIZE_BYTES 64
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/sha_struct.h b/components/soc/esp32c6/register/soc/sha_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/sha_struct.h
rename to components/soc/esp32c6/register/soc/sha_struct.h
diff --git a/components/soc/esp32c6/include/soc/slc_reg.h b/components/soc/esp32c6/register/soc/slc_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/slc_reg.h
rename to components/soc/esp32c6/register/soc/slc_reg.h
diff --git a/components/soc/esp32c6/include/soc/slc_struct.h b/components/soc/esp32c6/register/soc/slc_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/slc_struct.h
rename to components/soc/esp32c6/register/soc/slc_struct.h
diff --git a/components/soc/esp32c6/include/soc/soc_etm_reg.h b/components/soc/esp32c6/register/soc/soc_etm_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/soc_etm_reg.h
rename to components/soc/esp32c6/register/soc/soc_etm_reg.h
diff --git a/components/soc/esp32c6/include/soc/soc_etm_struct.h b/components/soc/esp32c6/register/soc/soc_etm_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/soc_etm_struct.h
rename to components/soc/esp32c6/register/soc/soc_etm_struct.h
diff --git a/components/soc/esp32c6/register/soc/spi_mem_reg.h b/components/soc/esp32c6/register/soc/spi_mem_reg.h
new file mode 100644
index 00000000000..56ada6dc461
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/spi_mem_reg.h
@@ -0,0 +1,3091 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI_MEM_CMD_REG register
+ *  SPI0 FSM status register
+ *  SPI1 memory command register
+ */
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
+/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_READ    (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
+bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WREN    (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when the bit is set. The
+ bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WRDI    (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
+e cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDID    (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered when the bit is
+ set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDSR    (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will be triggered when t
+he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
+ble..*/
+#define SPI_MEM_FLASH_WRSR    (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
+tion  will be triggered when the bit is set. The bit will be cleared once the op
+eration done .1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PP    (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
+is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_SE    (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
+ is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_BE    (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_CE    (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
+. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_DP    (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
+e or high performance mode and obtains the devices ID. The bit will be cleared once
+ the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RES    (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
+ion done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_HPM    (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
+ion will be triggered when the bit is set. The bit will be cleared once the oper
+ation done.1: enable 0: disable..*/
+#define SPI_MEM_USR    (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode, it is set to indicate that program/erase operation will be trigger
+ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
+peration done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PE    (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state,
+2: send command state, 3: send address state, 4: wait state, 5: read data state
+, 6:write data state, 7: done state, 8: read data end state..*/
+#define SPI_MEM_SLV_ST    0x0000000F
+#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
+#define SPI_MEM_SLV_ST_V  0xF
+#define SPI_MEM_SLV_ST_S  4
+/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
+, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
+nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
+#define SPI_MEM_MST_ST    0x0000000F
+#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
+#define SPI_MEM_MST_ST_V  0xF
+#define SPI_MEM_MST_ST_S  0
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
+address, the bit24-bit31 are the byte length of a transfer..*/
+#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
+/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
+lways 1. 0: Others..*/
+#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
+#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
+/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
+s 1. 0: Others..*/
+#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
+#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_QIO    (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_DIO    (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
+isable..*/
+#define SPI_MEM_WRSR_2B    (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
+#define SPI_MEM_WP_REG    (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
+#define SPI_MEM_D_POL    (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
+#define SPI_MEM_Q_POL    (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
+spi_mem_flash_res bit. 1: enable 0: disable..*/
+#define SPI_MEM_RESANDRES    (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
+UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
+#define SPI_MEM_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+e.*/
+#define SPI_MEM_TX_CRC_EN    (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
+e low..*/
+#define SPI_MEM_FCS_CRC_EN    (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_OCT    (BIT(9))
+#define SPI_MEM_FCMD_OCT_M  (BIT(9))
+#define SPI_MEM_FCMD_OCT_V  0x1
+#define SPI_MEM_FCMD_OCT_S  9
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
+#define SPI_MEM_FADDR_OCT    (BIT(6))
+#define SPI_MEM_FADDR_OCT_M  (BIT(6))
+#define SPI_MEM_FADDR_OCT_V  0x1
+#define SPI_MEM_FADDR_OCT_S  6
+/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
+#define SPI_MEM_FDIN_OCT    (BIT(5))
+#define SPI_MEM_FDIN_OCT_M  (BIT(5))
+#define SPI_MEM_FDIN_OCT_V  0x1
+#define SPI_MEM_FDIN_OCT_S  5
+/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
+#define SPI_MEM_FDOUT_OCT    (BIT(4))
+#define SPI_MEM_FDOUT_OCT_M  (BIT(4))
+#define SPI_MEM_FDOUT_OCT_V  0x1
+#define SPI_MEM_FDOUT_OCT_S  4
+/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
+is output by the MSPI controller in the second half part of dummy phase. It is u
+sed to pre-drive flash..*/
+#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
+#define SPI_MEM_FDUMMY_WOUT_M  (BIT(3))
+#define SPI_MEM_FDUMMY_WOUT_V  0x1
+#define SPI_MEM_FDUMMY_WOUT_S  3
+/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
+s output by the MSPI controller in the first half part of dummy phase. It is use
+d to mask invalid SPI_DQS in the half part of dummy phase..*/
+#define SPI_MEM_FDUMMY_RIN    (BIT(2))
+#define SPI_MEM_FDUMMY_RIN_M  (BIT(2))
+#define SPI_MEM_FDUMMY_RIN_V  0x1
+#define SPI_MEM_FDUMMY_RIN_S  2
+/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
+vel of SPI_IO[7:0] is output by the MSPI controller..*/
+#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
+/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
+vel of SPI_DQS is output by the MSPI controller..*/
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
+/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
+ send signals to AXI. Set this bit to reset these FIFO..*/
+#define SPI_MEM_TXFIFO_RST    (BIT(31))
+#define SPI_MEM_TXFIFO_RST_M  (BIT(31))
+#define SPI_MEM_TXFIFO_RST_V  0x1
+#define SPI_MEM_TXFIFO_RST_S  31
+/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
+ receive signals from AXI.  Set this bit to reset these FIFO..*/
+#define SPI_MEM_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_V  0x1
+#define SPI_MEM_RXFIFO_RST_S  30
+/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
+bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
+in  tx_bus_fifo_l2..*/
+#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
+#define SPI_MEM_FAST_WRITE_EN_M  (BIT(29))
+#define SPI_MEM_FAST_WRITE_EN_V  0x1
+#define SPI_MEM_FAST_WRITE_EN_S  29
+/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
+the same time..*/
+#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
+#define SPI_MEM_DUAL_RAM_EN_M  (BIT(28))
+#define SPI_MEM_DUAL_RAM_EN_V  0x1
+#define SPI_MEM_DUAL_RAM_EN_S  28
+/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
+/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
+cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
+ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
+cessed at the same time..*/
+#define SPI_MEM_RAM0_EN    (BIT(27))
+#define SPI_MEM_RAM0_EN_M  (BIT(27))
+#define SPI_MEM_RAM0_EN_V  0x1
+#define SPI_MEM_RAM0_EN_S  27
+/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable AXI Write Splice-transfer..*/
+#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
+#define SPI_MEM_AW_SPLICE_EN_M  (BIT(26))
+#define SPI_MEM_AW_SPLICE_EN_V  0x1
+#define SPI_MEM_AW_SPLICE_EN_S  26
+/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to enable AXI Read Splice-transfer..*/
+#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
+#define SPI_MEM_AR_SPLICE_EN_M  (BIT(25))
+#define SPI_MEM_AR_SPLICE_EN_V  0x1
+#define SPI_MEM_AR_SPLICE_EN_S  25
+/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
+ when there is a ECC error in AXI read data. The ECC error information is record
+ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
+#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
+#define SPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
+#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x1
+#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
+/* SPI_MEM_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
+eply AXI read data to AXI bus when all the read data is available..*/
+#define SPI_MEM_AXI_RDATA_BACK_FAST    (BIT(23))
+#define SPI_MEM_AXI_RDATA_BACK_FAST_M  (BIT(23))
+#define SPI_MEM_AXI_RDATA_BACK_FAST_V  0x1
+#define SPI_MEM_AXI_RDATA_BACK_FAST_S  23
+/* SPI_MEM_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
+#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
+#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
+#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V  0x1
+#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S  22
+/* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
+y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
+#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
+#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
+#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_V  0x1
+#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_S  21
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
+/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
+12) SPI_CLK cycles..*/
+#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on..*/
+#define SPI_MEM_CLK_MODE    0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
+/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
+#define SPI_MEM_SYNC_RESET    (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
+ clock cycles..*/
+#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_SPLIT_TRANS_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
+fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
+whether there is an ECC region or not..*/
+#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
+#define SPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
+#define SPI_MEM_SPLIT_TRANS_EN_V  0x1
+#define SPI_MEM_SPLIT_TRANS_EN_S  24
+/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+ accesses flash..*/
+#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
+#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
+#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
+#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
+/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */
+/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
+hen accesses flash..*/
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
+/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+ mode when accessed flash..*/
+#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
+#define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
+#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
+#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
+th SPI_MEM_CS_HOLD bit..*/
+#define SPI_MEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_CS_HOLD_TIME_S  5
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
+M_CS_SETUP bit..*/
+#define SPI_MEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
+ clock..*/
+#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+ system/(spi_mem_clkcnt_N+1).*/
+#define SPI_MEM_CLKCNT_N    0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define SPI_MEM_CLKCNT_H    0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
+#define SPI_MEM_CLKCNT_L    0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation..*/
+#define SPI_MEM_USR_COMMAND    (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation..*/
+#define SPI_MEM_USR_ADDR    (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation..*/
+#define SPI_MEM_USR_DUMMY    (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation..*/
+#define SPI_MEM_USR_MISO    (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation..*/
+#define SPI_MEM_USR_MOSI    (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable..*/
+#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+1: enable 0: disable..*/
+#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
+: enable 0: disable..*/
+#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals..*/
+#define SPI_MEM_FWRITE_QIO    (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals..*/
+#define SPI_MEM_FWRITE_DIO    (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals.*/
+#define SPI_MEM_FWRITE_QUAD    (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals.*/
+#define SPI_MEM_FWRITE_DUAL    (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
+#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_SETUP    (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_HOLD    (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
+/*description: SPI0 USR_CMD read or write data byte length -1.*/
+#define SPI_MEM_USR_DBYTELEN    0x00000007
+#define SPI_MEM_USR_DBYTELEN_M  ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S))
+#define SPI_MEM_USR_DBYTELEN_V  0x7
+#define SPI_MEM_USR_DBYTELEN_S  6
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
+cle_num-1)..*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command..*/
+#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
+it..*/
+#define SPI_MEM_WB_MODE    0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
+#define SPI_MEM_STATUS    0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: SPI_CS line keep low when the bit is set..*/
+#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
+#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0,  sram is connected to SUBPINs..*/
+#define SPI_MEM_SSUB_PIN    (BIT(8))
+#define SPI_MEM_SSUB_PIN_M  (BIT(8))
+#define SPI_MEM_SSUB_PIN_V  0x1
+#define SPI_MEM_SSUB_PIN_S  8
+/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0,  flash is connected to SUBPINs..*/
+#define SPI_MEM_FSUB_PIN    (BIT(7))
+#define SPI_MEM_FSUB_PIN_M  (BIT(7))
+#define SPI_MEM_FSUB_PIN_V  0x1
+#define SPI_MEM_FSUB_PIN_S  7
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS1_DIS    (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS0_DIS    (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: For SPI1, the value of crc32..*/
+#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
+/* SPI_MEM_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
+_ERR will be replied to BRESP/RRESP..*/
+#define SPI_MEM_CLOSE_AXI_INF_EN    (BIT(31))
+#define SPI_MEM_CLOSE_AXI_INF_EN_M  (BIT(31))
+#define SPI_MEM_CLOSE_AXI_INF_EN_V  0x1
+#define SPI_MEM_CLOSE_AXI_INF_EN_S  31
+/* SPI_MEM_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: Set this bit to check AXI read/write the same address region..*/
+#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
+#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
+#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V  0x1
+#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S  30
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_qio..*/
+#define SPI_MEM_FADDR_QUAD    (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
+e same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDOUT_QUAD    (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
+ same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDIN_QUAD    (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_dio..*/
+#define SPI_MEM_FADDR_DUAL    (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+ same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDOUT_DUAL    (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDIN_DUAL    (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
+/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
+#define SPI_MEM_AXI_REQ_EN    (BIT(0))
+#define SPI_MEM_AXI_REQ_EN_M  (BIT(0))
+#define SPI_MEM_AXI_REQ_EN_V  0x1
+#define SPI_MEM_AXI_REQ_EN_S  0
+
+#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
+/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
+e. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
+/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: reserved.*/
+#define SPI_MEM_SRAM_OCT    (BIT(21))
+#define SPI_MEM_SRAM_OCT_M  (BIT(21))
+#define SPI_MEM_SRAM_OCT_V  0x1
+#define SPI_MEM_SRAM_OCT_S  21
+/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
+#define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
+/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
+he register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
+#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
+/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
+. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
+/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode cache read external RAM for user define command
+..*/
+#define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
+/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
+ operations..*/
+#define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
+/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
+e operations..*/
+#define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
+/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
+le.*/
+#define SPI_MEM_USR_SRAM_QIO    (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_V  0x1
+#define SPI_MEM_USR_SRAM_QIO_S  2
+/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
+le.*/
+#define SPI_MEM_USR_SRAM_DIO    (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_V  0x1
+#define SPI_MEM_USR_SRAM_DIO_S  1
+/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
+able, 0:disable..*/
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
+
+#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
+/* SPI_MEM_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
+] are always 1. 0: Others..*/
+#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
+#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_S  31
+/* SPI_MEM_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
+e always 1. 0: Others..*/
+#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
+#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_S  30
+/* SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ the level of SPI_IO[7:0] is output by the MSPI controller..*/
+#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
+#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
+#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
+#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_S  25
+/* SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ the level of SPI_DQS is output by the MSPI controller..*/
+#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
+#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
+#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
+#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
+/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
+the signal level of SPI bus is output by the MSPI controller..*/
+#define SPI_MEM_SDUMMY_WOUT    (BIT(23))
+#define SPI_MEM_SDUMMY_WOUT_M  (BIT(23))
+#define SPI_MEM_SDUMMY_WOUT_V  0x1
+#define SPI_MEM_SDUMMY_WOUT_S  23
+/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
+he signal level of SPI bus is output by the MSPI controller..*/
+#define SPI_MEM_SDUMMY_RIN    (BIT(22))
+#define SPI_MEM_SDUMMY_RIN_M  (BIT(22))
+#define SPI_MEM_SDUMMY_RIN_V  0x1
+#define SPI_MEM_SDUMMY_RIN_S  22
+/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SCMD_OCT    (BIT(21))
+#define SPI_MEM_SCMD_OCT_M  (BIT(21))
+#define SPI_MEM_SCMD_OCT_V  0x1
+#define SPI_MEM_SCMD_OCT_S  21
+/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SADDR_OCT    (BIT(20))
+#define SPI_MEM_SADDR_OCT_M  (BIT(20))
+#define SPI_MEM_SADDR_OCT_V  0x1
+#define SPI_MEM_SADDR_OCT_S  20
+/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SDOUT_OCT    (BIT(19))
+#define SPI_MEM_SDOUT_OCT_M  (BIT(19))
+#define SPI_MEM_SDOUT_OCT_V  0x1
+#define SPI_MEM_SDOUT_OCT_S  19
+/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SDIN_OCT    (BIT(18))
+#define SPI_MEM_SDIN_OCT_M  (BIT(18))
+#define SPI_MEM_SDIN_OCT_V  0x1
+#define SPI_MEM_SDIN_OCT_S  18
+/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SCMD_QUAD    (BIT(17))
+#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
+#define SPI_MEM_SCMD_QUAD_V  0x1
+#define SPI_MEM_SCMD_QUAD_S  17
+/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SADDR_QUAD    (BIT(16))
+#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
+#define SPI_MEM_SADDR_QUAD_V  0x1
+#define SPI_MEM_SADDR_QUAD_S  16
+/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
+t is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SDOUT_QUAD    (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_V  0x1
+#define SPI_MEM_SDOUT_QUAD_S  15
+/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SDIN_QUAD    (BIT(14))
+#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
+#define SPI_MEM_SDIN_QUAD_V  0x1
+#define SPI_MEM_SDIN_QUAD_S  14
+/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SADDR_DUAL    (BIT(12))
+#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
+#define SPI_MEM_SADDR_DUAL_V  0x1
+#define SPI_MEM_SADDR_DUAL_S  12
+/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
+t is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SDOUT_DUAL    (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_V  0x1
+#define SPI_MEM_SDOUT_DUAL_S  11
+/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SDIN_DUAL    (BIT(10))
+#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
+#define SPI_MEM_SDIN_DUAL_V  0x1
+#define SPI_MEM_SDIN_DUAL_S  10
+/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */
+/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
+_mode bit..*/
+#define SPI_MEM_SWB_MODE    0x000000FF
+#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
+#define SPI_MEM_SWB_MODE_V  0xFF
+#define SPI_MEM_SWB_MODE_S  2
+/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on..*/
+#define SPI_MEM_SCLK_MODE    0x00000003
+#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
+#define SPI_MEM_SCLK_MODE_V  0x3
+#define SPI_MEM_SCLK_MODE_S  0
+
+#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
+ sram. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the read command value of command phase
+ for sram..*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
+ The register value shall be (bit_num-1)..*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the write command value of command phas
+e for sram..*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
+/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_c
+lk is divided from system clock..*/
+#define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
+/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
+lk frequency is system/(spi_mem_clkcnt_N+1).*/
+#define SPI_MEM_SCLKCNT_N    0x000000FF
+#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
+#define SPI_MEM_SCLKCNT_N_V  0xFF
+#define SPI_MEM_SCLKCNT_N_S  16
+/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define SPI_MEM_SCLKCNT_H    0x000000FF
+#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
+#define SPI_MEM_SCLKCNT_H_V  0xFF
+#define SPI_MEM_SCLKCNT_H_S  8
+/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
+#define SPI_MEM_SCLKCNT_L    0x000000FF
+#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
+#define SPI_MEM_SCLKCNT_L_V  0xFF
+#define SPI_MEM_SCLKCNT_L_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
+/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
+/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
+#define SPI_MEM_LOCK_DELAY_TIME    0x0000001F
+#define SPI_MEM_LOCK_DELAY_TIME_M  ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S))
+#define SPI_MEM_LOCK_DELAY_TIME_V  0x1F
+#define SPI_MEM_LOCK_DELAY_TIME_S  7
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
+/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF0    0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
+/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF1    0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
+/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF2    0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
+/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF3    0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
+/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF4    0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
+/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF5    0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
+/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF6    0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
+/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF7    0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
+/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF8    0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
+/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF9    0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
+/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF10    0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
+/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF11    0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
+/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF12    0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
+/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF13    0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
+/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF14    0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
+/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF15    0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: The command value to wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_CMD    0x0000FFFF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFFFF
+#define SPI_MEM_WAITI_CMD_S  16
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: The dummy cycle length when wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is
+ 8..*/
+#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
+#define SPI_MEM_WAITI_CMD_2B_M  (BIT(9))
+#define SPI_MEM_WAITI_CMD_2B_V  0x1
+#define SPI_MEM_WAITI_CMD_2B_S  9
+/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI
+_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+SPI_MEM_WAITI_ADDR_EN is cleared..*/
+#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S))
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x3
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
+/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out ad
+dress in RDSR or read SUS command transfer..*/
+#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
+#define SPI_MEM_WAITI_ADDR_EN_M  (BIT(2))
+#define SPI_MEM_WAITI_ADDR_EN_V  0x1
+#define SPI_MEM_WAITI_ADDR_EN_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The dummy phase enable when wait flash idle (RDSR).*/
+#define SPI_MEM_WAITI_DUMMY    (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
+ Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
+Suspend/Resume are not supported..*/
+#define SPI_MEM_WAITI_EN    (BIT(0))
+#define SPI_MEM_WAITI_EN_M  (BIT(0))
+#define SPI_MEM_WAITI_EN_V  0x1
+#define SPI_MEM_WAITI_EN_S  0
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
+/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
+/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
+ it will be treated as check pass..*/
+#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
+#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
+#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
+#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
+s of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PES_END_EN    (BIT(24))
+#define SPI_MEM_PES_END_EN_M  (BIT(24))
+#define SPI_MEM_PES_END_EN_V  0x1
+#define SPI_MEM_PES_END_EN_S  24
+/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
+ of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PER_END_EN    (BIT(23))
+#define SPI_MEM_PER_END_EN_M  (BIT(23))
+#define SPI_MEM_PER_END_EN_V  0x1
+#define SPI_MEM_PER_END_EN_S  23
+/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
+hen check flash SUS/SUS1/SUS2 status bit.*/
+#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
+#define SPI_MEM_FMEM_RD_SUS_2B_S  22
+/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
+/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
+2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
+#define SPI_MEM_PESR_END_MSK    0x0000FFFF
+#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
+#define SPI_MEM_PESR_END_MSK_V  0xFFFF
+#define SPI_MEM_PESR_END_MSK_S  6
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable Auto-suspending function..*/
+#define SPI_MEM_FLASH_PES_EN    (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  5
+/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
+application should send PER after PES is done..*/
+#define SPI_MEM_PES_PER_EN    (BIT(4))
+#define SPI_MEM_PES_PER_EN_M  (BIT(4))
+#define SPI_MEM_PES_PER_EN_V  0x1
+#define SPI_MEM_PES_PER_EN_S  4
+/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase suspend command is sent. 0: SPI1 does not wait after program erase
+ suspend command is sent..*/
+#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
+/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase resume command is sent. 0: SPI1 does not wait after program erase
+resume command is sent..*/
+#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
+/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit, program erase suspend operation will be triggered when
+the bit is set. The bit will be cleared once the operation done.1: enable 0: d
+isable..*/
+#define SPI_MEM_FLASH_PES    (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit, program erase suspend operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: di
+sable..*/
+#define SPI_MEM_FLASH_PER    (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
+/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
+/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
+..*/
+#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
+#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */
+/*description: Program/Erase suspend command..*/
+#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFFFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */
+/*description: Program/Erase resume command..*/
+#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFFFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  16
+/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng
+th of Program/Erase Suspend/Resume command is 8..*/
+#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI_MEM_FLASH_PESR_CMD_2B_M  (BIT(15))
+#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x1
+#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
+/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
+#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_V  0x1
+#define SPI_MEM_SPI0_LOCK_EN_S  7
+/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
+#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PES_DLY_128_S  6
+/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
+#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PER_DLY_128_S  5
+/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
+mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+after DP command is sent..*/
+#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
+#define SPI_MEM_FLASH_DP_DLY_128_S  4
+/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after RES command is sent..*/
+#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_RES_DLY_128_S  3
+/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after HPM command is sent..*/
+#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
+#define SPI_MEM_FLASH_HPM_DLY_128_S  2
+/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
+#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
+#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
+/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend, only used in SPI1..*/
+#define SPI_MEM_FLASH_SUS    (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
+/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT__ENA    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
+/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
+/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
+#define SPI_MEM_ECC_ERR_INT_ENA_S  5
+/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ENA_S  4
+/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
+/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_V  0x1
+#define SPI_MEM_WPE_END_INT_ENA_S  2
+/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_V  0x1
+#define SPI_MEM_PES_END_INT_ENA_S  1
+/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_V  0x1
+#define SPI_MEM_PER_END_INT_ENA_S  0
+
+#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
+/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
+/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
+/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
+#define SPI_MEM_ECC_ERR_INT_CLR_S  5
+/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_MST_ST_END_INT_CLR_S  4
+/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
+/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_V  0x1
+#define SPI_MEM_WPE_END_INT_CLR_S  2
+/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_V  0x1
+#define SPI_MEM_PES_END_INT_CLR_S  1
+/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_V  0x1
+#define SPI_MEM_PER_END_INT_CLR_S  0
+
+#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
+/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+chip is losing power and RTC module sends out brown out close flash request to
+SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+ and MSPI returns to idle state. 0: Others..*/
+#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+ address is invalid by compared to MMU configuration. 0: Others..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
+ite flash request is received. 0: Others..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+address is invalid by compared to MMU configuration. 0: Others..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
+/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
+is rejected. 0: Others..*/
+#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
+/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
+et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
+ times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
+. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
+his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
+ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
+I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM.
+When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared,
+this bit will not be triggered..*/
+#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
+#define SPI_MEM_ECC_ERR_INT_RAW_S  5
+/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
+is changed from non idle state to idle state. 0: Others..*/
+#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_MST_ST_END_INT_RAW_S  4
+/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
+is changed from non idle state to idle state. It means that SPI_CS raises high.
+0: Others.*/
+#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
+/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
+E is sent and flash is already idle. 0: Others..*/
+#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_V  0x1
+#define SPI_MEM_WPE_END_INT_RAW_S  2
+/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
+mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
+#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_V  0x1
+#define SPI_MEM_PES_END_INT_RAW_S  1
+/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
+mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
+#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_V  0x1
+#define SPI_MEM_PER_END_INT_RAW_S  0
+
+#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
+/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ST_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
+/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ST_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_ST_S  6
+/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ST_V  0x1
+#define SPI_MEM_ECC_ERR_INT_ST_S  5
+/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ST_S  4
+/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ST_S  3
+/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_V  0x1
+#define SPI_MEM_WPE_END_INT_ST_S  2
+/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ST    (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_V  0x1
+#define SPI_MEM_PES_END_INT_ST_S  1
+/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ST    (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_V  0x1
+#define SPI_MEM_PER_END_INT_ST_S  0
+
+#define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
+/* SPI_MEM_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
+#define SPI_MEM_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_FMEM_HYPERBUS_CA_M  (BIT(30))
+#define SPI_MEM_FMEM_HYPERBUS_CA_V  0x1
+#define SPI_MEM_FMEM_HYPERBUS_CA_S  30
+/* SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
+..*/
+#define SPI_MEM_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V  0x1
+#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S  29
+/* SPI_MEM_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
+#define SPI_MEM_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_FMEM_CLK_DIFF_INV_M  (BIT(28))
+#define SPI_MEM_FMEM_CLK_DIFF_INV_V  0x1
+#define SPI_MEM_FMEM_CLK_DIFF_INV_S  28
+/* SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S  27
+/* SPI_MEM_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define SPI_MEM_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_FMEM_DQS_CA_IN_M  (BIT(26))
+#define SPI_MEM_FMEM_DQS_CA_IN_V  0x1
+#define SPI_MEM_FMEM_DQS_CA_IN_S  26
+/* SPI_MEM_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define SPI_MEM_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_FMEM_CLK_DIFF_EN_M  (BIT(24))
+#define SPI_MEM_FMEM_CLK_DIFF_EN_V  0x1
+#define SPI_MEM_FMEM_CLK_DIFF_EN_S  24
+/* SPI_MEM_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
+0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
+egative edge of SPI_DQS..*/
+#define SPI_MEM_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_FMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define SPI_MEM_FMEM_DDR_DQS_LOOP_V  0x1
+#define SPI_MEM_FMEM_DDR_DQS_LOOP_S  21
+/* SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI clock..*/
+#define SPI_MEM_FMEM_USR_DDR_DQS_THD    0x0000007F
+#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_FMEM_USR_DDR_DQS_THD_S))
+#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V  0x7F
+#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S  14
+/* SPI_MEM_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+accesses to flash..*/
+#define SPI_MEM_FMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define SPI_MEM_FMEM_RX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_FMEM_RX_DDR_MSK_EN_S  13
+/* SPI_MEM_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ accesses to flash..*/
+#define SPI_MEM_FMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define SPI_MEM_FMEM_TX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_FMEM_TX_DDR_MSK_EN_S  12
+/* SPI_MEM_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the panda device..*/
+#define SPI_MEM_FMEM_OUTMINBYTELEN    0x0000007F
+#define SPI_MEM_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_FMEM_OUTMINBYTELEN_S))
+#define SPI_MEM_FMEM_OUTMINBYTELEN_V  0x7F
+#define SPI_MEM_FMEM_OUTMINBYTELEN_S  5
+/* SPI_MEM_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define SPI_MEM_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_FMEM_DDR_CMD_DIS_M  (BIT(4))
+#define SPI_MEM_FMEM_DDR_CMD_DIS_V  0x1
+#define SPI_MEM_FMEM_DDR_CMD_DIS_S  4
+/* SPI_MEM_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
+#define SPI_MEM_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_FMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define SPI_MEM_FMEM_DDR_WDAT_SWP_V  0x1
+#define SPI_MEM_FMEM_DDR_WDAT_SWP_S  3
+/* SPI_MEM_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
+#define SPI_MEM_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_FMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define SPI_MEM_FMEM_DDR_RDAT_SWP_V  0x1
+#define SPI_MEM_FMEM_DDR_RDAT_SWP_S  2
+/* SPI_MEM_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
+#define SPI_MEM_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_FMEM_VAR_DUMMY_M  (BIT(1))
+#define SPI_MEM_FMEM_VAR_DUMMY_V  0x1
+#define SPI_MEM_FMEM_VAR_DUMMY_S  1
+/* SPI_MEM_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0 in SDR mode.*/
+#define SPI_MEM_FMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_FMEM_DDR_EN_M  (BIT(0))
+#define SPI_MEM_FMEM_DDR_EN_V  0x1
+#define SPI_MEM_FMEM_DDR_EN_S  0
+
+#define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD8)
+/* SPI_MEM_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
+]}..*/
+#define SPI_MEM_SMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_SMEM_HYPERBUS_CA_M  (BIT(30))
+#define SPI_MEM_SMEM_HYPERBUS_CA_V  0x1
+#define SPI_MEM_SMEM_HYPERBUS_CA_S  30
+/* SPI_MEM_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
+, 1'b0}..*/
+#define SPI_MEM_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define SPI_MEM_SMEM_OCTA_RAM_ADDR_V  0x1
+#define SPI_MEM_SMEM_OCTA_RAM_ADDR_S  29
+/* SPI_MEM_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
+#define SPI_MEM_SMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_SMEM_CLK_DIFF_INV_M  (BIT(28))
+#define SPI_MEM_SMEM_CLK_DIFF_INV_V  0x1
+#define SPI_MEM_SMEM_CLK_DIFF_INV_S  28
+/* SPI_MEM_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S  27
+/* SPI_MEM_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define SPI_MEM_SMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_SMEM_DQS_CA_IN_M  (BIT(26))
+#define SPI_MEM_SMEM_DQS_CA_IN_V  0x1
+#define SPI_MEM_SMEM_DQS_CA_IN_S  26
+/* SPI_MEM_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define SPI_MEM_SMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_SMEM_CLK_DIFF_EN_M  (BIT(24))
+#define SPI_MEM_SMEM_CLK_DIFF_EN_V  0x1
+#define SPI_MEM_SMEM_CLK_DIFF_EN_S  24
+/* SPI_MEM_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
+0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
+egative edge of SPI_DQS..*/
+#define SPI_MEM_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_SMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define SPI_MEM_SMEM_DDR_DQS_LOOP_V  0x1
+#define SPI_MEM_SMEM_DDR_DQS_LOOP_S  21
+/* SPI_MEM_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI clock..*/
+#define SPI_MEM_SMEM_USR_DDR_DQS_THD    0x0000007F
+#define SPI_MEM_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SMEM_USR_DDR_DQS_THD_S))
+#define SPI_MEM_SMEM_USR_DDR_DQS_THD_V  0x7F
+#define SPI_MEM_SMEM_USR_DDR_DQS_THD_S  14
+/* SPI_MEM_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+accesses to external RAM..*/
+#define SPI_MEM_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define SPI_MEM_SMEM_RX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SMEM_RX_DDR_MSK_EN_S  13
+/* SPI_MEM_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ accesses to external RAM..*/
+#define SPI_MEM_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define SPI_MEM_SMEM_TX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SMEM_TX_DDR_MSK_EN_S  12
+/* SPI_MEM_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the DDR psram..*/
+#define SPI_MEM_SMEM_OUTMINBYTELEN    0x0000007F
+#define SPI_MEM_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SMEM_OUTMINBYTELEN_S))
+#define SPI_MEM_SMEM_OUTMINBYTELEN_V  0x7F
+#define SPI_MEM_SMEM_OUTMINBYTELEN_S  5
+/* SPI_MEM_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define SPI_MEM_SMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_SMEM_DDR_CMD_DIS_M  (BIT(4))
+#define SPI_MEM_SMEM_DDR_CMD_DIS_V  0x1
+#define SPI_MEM_SMEM_DDR_CMD_DIS_S  4
+/* SPI_MEM_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
+#define SPI_MEM_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_SMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define SPI_MEM_SMEM_DDR_WDAT_SWP_V  0x1
+#define SPI_MEM_SMEM_DDR_WDAT_SWP_S  3
+/* SPI_MEM_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
+#define SPI_MEM_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_SMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define SPI_MEM_SMEM_DDR_RDAT_SWP_V  0x1
+#define SPI_MEM_SMEM_DDR_RDAT_SWP_S  2
+/* SPI_MEM_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
+#define SPI_MEM_SMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_SMEM_VAR_DUMMY_M  (BIT(1))
+#define SPI_MEM_SMEM_VAR_DUMMY_V  0x1
+#define SPI_MEM_SMEM_VAR_DUMMY_S  1
+/* SPI_MEM_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0 in SDR mode.*/
+#define SPI_MEM_SMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_SMEM_DDR_EN_M  (BIT(0))
+#define SPI_MEM_SMEM_DDR_EN_V  0x1
+#define SPI_MEM_SMEM_DDR_EN_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x100)
+/* SPI_MEM_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_FMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_FMEM_PMS0_ECC_M  (BIT(2))
+#define SPI_MEM_FMEM_PMS0_ECC_V  0x1
+#define SPI_MEM_FMEM_PMS0_ECC_S  2
+/* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_FMEM_PMS0_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_FMEM_PMS0_WR_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS0_WR_ATTR_S  1
+/* SPI_MEM_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_FMEM_PMS0_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_FMEM_PMS0_RD_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS0_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x104)
+/* SPI_MEM_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_FMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_FMEM_PMS1_ECC_M  (BIT(2))
+#define SPI_MEM_FMEM_PMS1_ECC_V  0x1
+#define SPI_MEM_FMEM_PMS1_ECC_S  2
+/* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_FMEM_PMS1_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_FMEM_PMS1_WR_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS1_WR_ATTR_S  1
+/* SPI_MEM_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_FMEM_PMS1_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_FMEM_PMS1_RD_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS1_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x108)
+/* SPI_MEM_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_FMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_FMEM_PMS2_ECC_M  (BIT(2))
+#define SPI_MEM_FMEM_PMS2_ECC_V  0x1
+#define SPI_MEM_FMEM_PMS2_ECC_S  2
+/* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_FMEM_PMS2_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_FMEM_PMS2_WR_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS2_WR_ATTR_S  1
+/* SPI_MEM_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_FMEM_PMS2_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_FMEM_PMS2_RD_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS2_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10C)
+/* SPI_MEM_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_FMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_FMEM_PMS3_ECC_M  (BIT(2))
+#define SPI_MEM_FMEM_PMS3_ECC_V  0x1
+#define SPI_MEM_FMEM_PMS3_ECC_S  2
+/* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_FMEM_PMS3_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_FMEM_PMS3_WR_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS3_WR_ATTR_S  1
+/* SPI_MEM_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_FMEM_PMS3_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_FMEM_PMS3_RD_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS3_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x110)
+/* SPI_MEM_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: SPI1 flash ACE section $n start address value.*/
+#define SPI_MEM_FMEM_PMS0_ADDR_S    0x03FFFFFF
+#define SPI_MEM_FMEM_PMS0_ADDR_S_M  ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S))
+#define SPI_MEM_FMEM_PMS0_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_FMEM_PMS0_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x114)
+/* SPI_MEM_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
+/*description: SPI1 flash ACE section $n start address value.*/
+#define SPI_MEM_FMEM_PMS1_ADDR_S    0x03FFFFFF
+#define SPI_MEM_FMEM_PMS1_ADDR_S_M  ((SPI_MEM_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_FMEM_PMS1_ADDR_S_S))
+#define SPI_MEM_FMEM_PMS1_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_FMEM_PMS1_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x118)
+/* SPI_MEM_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
+/*description: SPI1 flash ACE section $n start address value.*/
+#define SPI_MEM_FMEM_PMS2_ADDR_S    0x03FFFFFF
+#define SPI_MEM_FMEM_PMS2_ADDR_S_M  ((SPI_MEM_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_FMEM_PMS2_ADDR_S_S))
+#define SPI_MEM_FMEM_PMS2_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_FMEM_PMS2_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x11C)
+/* SPI_MEM_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
+/*description: SPI1 flash ACE section $n start address value.*/
+#define SPI_MEM_FMEM_PMS3_ADDR_S    0x03FFFFFF
+#define SPI_MEM_FMEM_PMS3_ADDR_S_M  ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S))
+#define SPI_MEM_FMEM_PMS3_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_FMEM_PMS3_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x120)
+/* SPI_MEM_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_FMEM_PMS0_SIZE    0x00003FFF
+#define SPI_MEM_FMEM_PMS0_SIZE_M  ((SPI_MEM_FMEM_PMS0_SIZE_V)<<(SPI_MEM_FMEM_PMS0_SIZE_S))
+#define SPI_MEM_FMEM_PMS0_SIZE_V  0x3FFF
+#define SPI_MEM_FMEM_PMS0_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x124)
+/* SPI_MEM_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_FMEM_PMS1_SIZE    0x00003FFF
+#define SPI_MEM_FMEM_PMS1_SIZE_M  ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S))
+#define SPI_MEM_FMEM_PMS1_SIZE_V  0x3FFF
+#define SPI_MEM_FMEM_PMS1_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x128)
+/* SPI_MEM_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_FMEM_PMS2_SIZE    0x00003FFF
+#define SPI_MEM_FMEM_PMS2_SIZE_M  ((SPI_MEM_FMEM_PMS2_SIZE_V)<<(SPI_MEM_FMEM_PMS2_SIZE_S))
+#define SPI_MEM_FMEM_PMS2_SIZE_V  0x3FFF
+#define SPI_MEM_FMEM_PMS2_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x12C)
+/* SPI_MEM_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_FMEM_PMS3_SIZE    0x00003FFF
+#define SPI_MEM_FMEM_PMS3_SIZE_M  ((SPI_MEM_FMEM_PMS3_SIZE_V)<<(SPI_MEM_FMEM_PMS3_SIZE_S))
+#define SPI_MEM_FMEM_PMS3_SIZE_V  0x3FFF
+#define SPI_MEM_FMEM_PMS3_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x130)
+/* SPI_MEM_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_SMEM_PMS0_ECC_M  (BIT(2))
+#define SPI_MEM_SMEM_PMS0_ECC_V  0x1
+#define SPI_MEM_SMEM_PMS0_ECC_S  2
+/* SPI_MEM_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_SMEM_PMS0_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SMEM_PMS0_WR_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS0_WR_ATTR_S  1
+/* SPI_MEM_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_SMEM_PMS0_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SMEM_PMS0_RD_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS0_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x134)
+/* SPI_MEM_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_SMEM_PMS1_ECC_M  (BIT(2))
+#define SPI_MEM_SMEM_PMS1_ECC_V  0x1
+#define SPI_MEM_SMEM_PMS1_ECC_S  2
+/* SPI_MEM_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_SMEM_PMS1_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SMEM_PMS1_WR_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS1_WR_ATTR_S  1
+/* SPI_MEM_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_SMEM_PMS1_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SMEM_PMS1_RD_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS1_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x138)
+/* SPI_MEM_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_SMEM_PMS2_ECC_M  (BIT(2))
+#define SPI_MEM_SMEM_PMS2_ECC_V  0x1
+#define SPI_MEM_SMEM_PMS2_ECC_S  2
+/* SPI_MEM_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_SMEM_PMS2_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SMEM_PMS2_WR_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS2_WR_ATTR_S  1
+/* SPI_MEM_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_SMEM_PMS2_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SMEM_PMS2_RD_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS2_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x13C)
+/* SPI_MEM_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_SMEM_PMS3_ECC_M  (BIT(2))
+#define SPI_MEM_SMEM_PMS3_ECC_V  0x1
+#define SPI_MEM_SMEM_PMS3_ECC_S  2
+/* SPI_MEM_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_SMEM_PMS3_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SMEM_PMS3_WR_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS3_WR_ATTR_S  1
+/* SPI_MEM_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_SMEM_PMS3_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SMEM_PMS3_RD_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS3_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x140)
+/* SPI_MEM_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: SPI1 external RAM ACE section $n start address value.*/
+#define SPI_MEM_SMEM_PMS0_ADDR_S    0x03FFFFFF
+#define SPI_MEM_SMEM_PMS0_ADDR_S_M  ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S))
+#define SPI_MEM_SMEM_PMS0_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_SMEM_PMS0_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x144)
+/* SPI_MEM_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
+/*description: SPI1 external RAM ACE section $n start address value.*/
+#define SPI_MEM_SMEM_PMS1_ADDR_S    0x03FFFFFF
+#define SPI_MEM_SMEM_PMS1_ADDR_S_M  ((SPI_MEM_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SMEM_PMS1_ADDR_S_S))
+#define SPI_MEM_SMEM_PMS1_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_SMEM_PMS1_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x148)
+/* SPI_MEM_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
+/*description: SPI1 external RAM ACE section $n start address value.*/
+#define SPI_MEM_SMEM_PMS2_ADDR_S    0x03FFFFFF
+#define SPI_MEM_SMEM_PMS2_ADDR_S_M  ((SPI_MEM_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SMEM_PMS2_ADDR_S_S))
+#define SPI_MEM_SMEM_PMS2_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_SMEM_PMS2_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14C)
+/* SPI_MEM_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
+/*description: SPI1 external RAM ACE section $n start address value.*/
+#define SPI_MEM_SMEM_PMS3_ADDR_S    0x03FFFFFF
+#define SPI_MEM_SMEM_PMS3_ADDR_S_M  ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S))
+#define SPI_MEM_SMEM_PMS3_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_SMEM_PMS3_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x150)
+/* SPI_MEM_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SMEM_PMS0_SIZE    0x00003FFF
+#define SPI_MEM_SMEM_PMS0_SIZE_M  ((SPI_MEM_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SMEM_PMS0_SIZE_S))
+#define SPI_MEM_SMEM_PMS0_SIZE_V  0x3FFF
+#define SPI_MEM_SMEM_PMS0_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x154)
+/* SPI_MEM_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SMEM_PMS1_SIZE    0x00003FFF
+#define SPI_MEM_SMEM_PMS1_SIZE_M  ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S))
+#define SPI_MEM_SMEM_PMS1_SIZE_V  0x3FFF
+#define SPI_MEM_SMEM_PMS1_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x158)
+/* SPI_MEM_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SMEM_PMS2_SIZE    0x00003FFF
+#define SPI_MEM_SMEM_PMS2_SIZE_M  ((SPI_MEM_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SMEM_PMS2_SIZE_S))
+#define SPI_MEM_SMEM_PMS2_SIZE_V  0x3FFF
+#define SPI_MEM_SMEM_PMS2_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x15C)
+/* SPI_MEM_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SMEM_PMS3_SIZE    0x00003FFF
+#define SPI_MEM_SMEM_PMS3_SIZE_M  ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S))
+#define SPI_MEM_SMEM_PMS3_SIZE_V  0x3FFF
+#define SPI_MEM_SMEM_PMS3_SIZE_S  0
+
+#define SPI_MEM_PMS_REJECT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x164)
+/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
+/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
+ error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_IVD    (BIT(31))
+#define SPI_MEM_PMS_IVD_M  (BIT(31))
+#define SPI_MEM_PMS_IVD_V  0x1
+#define SPI_MEM_PMS_IVD_S  31
+/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
+ is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
+#define SPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
+#define SPI_MEM_PMS_MULTI_HIT_V  0x1
+#define SPI_MEM_PMS_MULTI_HIT_S  30
+/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
+EM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_ST    (BIT(29))
+#define SPI_MEM_PMS_ST_M  (BIT(29))
+#define SPI_MEM_PMS_ST_V  0x1
+#define SPI_MEM_PMS_ST_S  29
+/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
+_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_LD    (BIT(28))
+#define SPI_MEM_PMS_LD_M  (BIT(28))
+#define SPI_MEM_PMS_LD_V  0x1
+#define SPI_MEM_PMS_LD_S  28
+/* SPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
+#define SPI_MEM_PM_EN    (BIT(26))
+#define SPI_MEM_PM_EN_M  (BIT(26))
+#define SPI_MEM_PM_EN_V  0x1
+#define SPI_MEM_PM_EN_S  26
+/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
+EM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_REJECT_ADDR    0x03FFFFFF
+#define SPI_MEM_REJECT_ADDR_M  ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S))
+#define SPI_MEM_REJECT_ADDR_V  0x3FFFFFF
+#define SPI_MEM_REJECT_ADDR_S  0
+
+#define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x168)
+/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */
+/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
+ to byte 0 bit 0 to byte 15 bit 7).*/
+#define SPI_MEM_ECC_ERR_BITS    0x0000007F
+#define SPI_MEM_ECC_ERR_BITS_M  ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S))
+#define SPI_MEM_ECC_ERR_BITS_V  0x7F
+#define SPI_MEM_ECC_ERR_BITS_S  25
+/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
+ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
+R record the first ECC error information..*/
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
+/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
+#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
+#define SPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
+#define SPI_MEM_USR_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_USR_ECC_ADDR_EN_S  21
+/* SPI_MEM_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
+he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
+is bit should be 0. Otherwise, this bit should be 1..*/
+#define SPI_MEM_FMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_FMEM_ECC_ADDR_EN_M  (BIT(20))
+#define SPI_MEM_FMEM_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_FMEM_ECC_ADDR_EN_S  20
+/* SPI_MEM_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
+1024 bytes. 3: 2048 bytes..*/
+#define SPI_MEM_FMEM_PAGE_SIZE    0x00000003
+#define SPI_MEM_FMEM_PAGE_SIZE_M  ((SPI_MEM_FMEM_PAGE_SIZE_V)<<(SPI_MEM_FMEM_PAGE_SIZE_S))
+#define SPI_MEM_FMEM_PAGE_SIZE_V  0x3
+#define SPI_MEM_FMEM_PAGE_SIZE_S  18
+/* SPI_MEM_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
+h..*/
+#define SPI_MEM_FMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
+#define SPI_MEM_FMEM_ECC_ERR_INT_EN_V  0x1
+#define SPI_MEM_FMEM_ECC_ERR_INT_EN_S  17
+/* SPI_MEM_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */
+/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
+upt..*/
+#define SPI_MEM_FMEM_ECC_ERR_INT_NUM    0x0000003F
+#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_FMEM_ECC_ERR_INT_NUM_S))
+#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_V  0x3F
+#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_S  11
+
+#define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x16C)
+/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[31:26] ;default: 6'd0 ; */
+/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
+ECC_ERR_INT_CLR bit is set..*/
+#define SPI_MEM_ECC_ERR_CNT    0x0000003F
+#define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
+#define SPI_MEM_ECC_ERR_CNT_V  0x3F
+#define SPI_MEM_ECC_ERR_CNT_S  26
+/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
+ECC_ERR_INT_CLR bit is set..*/
+#define SPI_MEM_ECC_ERR_ADDR    0x03FFFFFF
+#define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
+#define SPI_MEM_ECC_ERR_ADDR_V  0x3FFFFFF
+#define SPI_MEM_ECC_ERR_ADDR_S  0
+
+#define SPI_MEM_AXI_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x170)
+/* SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
+and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
+#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
+#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
+#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
+#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
+/* SPI_MEM_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
+#define SPI_MEM_WBLEN_AFIFO_REMPTY    (BIT(30))
+#define SPI_MEM_WBLEN_AFIFO_REMPTY_M  (BIT(30))
+#define SPI_MEM_WBLEN_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_WBLEN_AFIFO_REMPTY_S  30
+/* SPI_MEM_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
+/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
+#define SPI_MEM_WDATA_AFIFO_REMPTY    (BIT(29))
+#define SPI_MEM_WDATA_AFIFO_REMPTY_M  (BIT(29))
+#define SPI_MEM_WDATA_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_WDATA_AFIFO_REMPTY_S  29
+/* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
+/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
+#define SPI_MEM_RADDR_AFIFO_REMPTY    (BIT(28))
+#define SPI_MEM_RADDR_AFIFO_REMPTY_M  (BIT(28))
+#define SPI_MEM_RADDR_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_RADDR_AFIFO_REMPTY_S  28
+/* SPI_MEM_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
+#define SPI_MEM_RDATA_AFIFO_REMPTY    (BIT(27))
+#define SPI_MEM_RDATA_AFIFO_REMPTY_M  (BIT(27))
+#define SPI_MEM_RDATA_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_RDATA_AFIFO_REMPTY_S  27
+/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
+ and SPI0 transfers are done. 0: Others..*/
+#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
+#define SPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
+#define SPI_MEM_ALL_FIFO_EMPTY_V  0x1
+#define SPI_MEM_ALL_FIFO_EMPTY_S  26
+/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first AXI write/read invalid error or AXI write flash error
+address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
+H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
+#define SPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
+#define SPI_MEM_AXI_ERR_ADDR_M  ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S))
+#define SPI_MEM_AXI_ERR_ADDR_V  0x3FFFFFF
+#define SPI_MEM_AXI_ERR_ADDR_S  0
+
+#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x174)
+/* SPI_MEM_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
+he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
+ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
+#define SPI_MEM_SMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_SMEM_ECC_ADDR_EN_M  (BIT(20))
+#define SPI_MEM_SMEM_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_SMEM_ECC_ADDR_EN_S  20
+/* SPI_MEM_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */
+/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
+es. 2: 1024 bytes. 3: 2048 bytes..*/
+#define SPI_MEM_SMEM_PAGE_SIZE    0x00000003
+#define SPI_MEM_SMEM_PAGE_SIZE_M  ((SPI_MEM_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SMEM_PAGE_SIZE_S))
+#define SPI_MEM_SMEM_PAGE_SIZE_V  0x3
+#define SPI_MEM_SMEM_PAGE_SIZE_S  18
+/* SPI_MEM_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
+rnal RAM..*/
+#define SPI_MEM_SMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
+#define SPI_MEM_SMEM_ECC_ERR_INT_EN_V  0x1
+#define SPI_MEM_SMEM_ECC_ERR_INT_EN_S  17
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x180)
+/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
+#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
+#define SPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
+#define SPI_MEM_TIMING_CALI_UPDATE_V  0x1
+#define SPI_MEM_TIMING_CALI_UPDATE_S  6
+/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
+lash..*/
+#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
+#define SPI_MEM_DLL_TIMING_CALI_V  0x1
+#define SPI_MEM_DLL_TIMING_CALI_S  5
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
+#define SPI_MEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations..*/
+#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x184)
+/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DINS_MODE    0x00000007
+#define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
+#define SPI_MEM_DINS_MODE_V  0x7
+#define SPI_MEM_DINS_MODE_S  24
+/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN7_MODE    0x00000007
+#define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
+#define SPI_MEM_DIN7_MODE_V  0x7
+#define SPI_MEM_DIN7_MODE_S  21
+/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN6_MODE    0x00000007
+#define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
+#define SPI_MEM_DIN6_MODE_V  0x7
+#define SPI_MEM_DIN6_MODE_S  18
+/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN5_MODE    0x00000007
+#define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
+#define SPI_MEM_DIN5_MODE_V  0x7
+#define SPI_MEM_DIN5_MODE_S  15
+/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN4_MODE    0x00000007
+#define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
+#define SPI_MEM_DIN4_MODE_V  0x7
+#define SPI_MEM_DIN4_MODE_S  12
+/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN3_MODE    0x00000007
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x7
+#define SPI_MEM_DIN3_MODE_S  9
+/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN2_MODE    0x00000007
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x7
+#define SPI_MEM_DIN2_MODE_S  6
+/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN1_MODE    0x00000007
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x7
+#define SPI_MEM_DIN1_MODE_S  3
+/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN0_MODE    0x00000007
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x7
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x188)
+/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DINS_NUM    0x00000003
+#define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
+#define SPI_MEM_DINS_NUM_V  0x3
+#define SPI_MEM_DINS_NUM_S  16
+/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN7_NUM    0x00000003
+#define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
+#define SPI_MEM_DIN7_NUM_V  0x3
+#define SPI_MEM_DIN7_NUM_S  14
+/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN6_NUM    0x00000003
+#define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
+#define SPI_MEM_DIN6_NUM_V  0x3
+#define SPI_MEM_DIN6_NUM_S  12
+/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN5_NUM    0x00000003
+#define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
+#define SPI_MEM_DIN5_NUM_V  0x3
+#define SPI_MEM_DIN5_NUM_S  10
+/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN4_NUM    0x00000003
+#define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
+#define SPI_MEM_DIN4_NUM_V  0x3
+#define SPI_MEM_DIN4_NUM_S  8
+/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN3_NUM    0x00000003
+#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
+#define SPI_MEM_DIN3_NUM_V  0x3
+#define SPI_MEM_DIN3_NUM_S  6
+/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN2_NUM    0x00000003
+#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
+#define SPI_MEM_DIN2_NUM_V  0x3
+#define SPI_MEM_DIN2_NUM_S  4
+/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN1_NUM    0x00000003
+#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
+#define SPI_MEM_DIN1_NUM_V  0x3
+#define SPI_MEM_DIN1_NUM_S  2
+/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN0_NUM    0x00000003
+#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
+#define SPI_MEM_DIN0_NUM_V  0x3
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18C)
+/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_DOUTS_MODE_M  (BIT(8))
+#define SPI_MEM_DOUTS_MODE_V  0x1
+#define SPI_MEM_DOUTS_MODE_S  8
+/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_DOUT7_MODE_M  (BIT(7))
+#define SPI_MEM_DOUT7_MODE_V  0x1
+#define SPI_MEM_DOUT7_MODE_S  7
+/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_DOUT6_MODE_M  (BIT(6))
+#define SPI_MEM_DOUT6_MODE_V  0x1
+#define SPI_MEM_DOUT6_MODE_S  6
+/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_DOUT5_MODE_M  (BIT(5))
+#define SPI_MEM_DOUT5_MODE_V  0x1
+#define SPI_MEM_DOUT5_MODE_S  5
+/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_DOUT4_MODE_M  (BIT(4))
+#define SPI_MEM_DOUT4_MODE_V  0x1
+#define SPI_MEM_DOUT4_MODE_S  4
+/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_DOUT3_MODE_S  3
+/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_DOUT2_MODE_S  2
+/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_DOUT1_MODE_S  1
+/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x190)
+/* SPI_MEM_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
+XT_RAM..*/
+#define SPI_MEM_SMEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_SMEM_DLL_TIMING_CALI_M  (BIT(5))
+#define SPI_MEM_SMEM_DLL_TIMING_CALI_V  0x1
+#define SPI_MEM_SMEM_DLL_TIMING_CALI_S  5
+/* SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
+#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
+ations..*/
+#define SPI_MEM_SMEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_SMEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_SMEM_TIMING_CALI_V  0x1
+#define SPI_MEM_SMEM_TIMING_CALI_S  1
+/* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: For sram, the bit is used to enable timing adjust clock for all reading operation
+ns..*/
+#define SPI_MEM_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_SMEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_SMEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_SMEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x194)
+/* SPI_MEM_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DINS_MODE    0x00000007
+#define SPI_MEM_SMEM_DINS_MODE_M  ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S))
+#define SPI_MEM_SMEM_DINS_MODE_V  0x7
+#define SPI_MEM_SMEM_DINS_MODE_S  24
+/* SPI_MEM_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN7_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN7_MODE_M  ((SPI_MEM_SMEM_DIN7_MODE_V)<<(SPI_MEM_SMEM_DIN7_MODE_S))
+#define SPI_MEM_SMEM_DIN7_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN7_MODE_S  21
+/* SPI_MEM_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN6_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN6_MODE_M  ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S))
+#define SPI_MEM_SMEM_DIN6_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN6_MODE_S  18
+/* SPI_MEM_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN5_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN5_MODE_M  ((SPI_MEM_SMEM_DIN5_MODE_V)<<(SPI_MEM_SMEM_DIN5_MODE_S))
+#define SPI_MEM_SMEM_DIN5_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN5_MODE_S  15
+/* SPI_MEM_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN4_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN4_MODE_M  ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S))
+#define SPI_MEM_SMEM_DIN4_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN4_MODE_S  12
+/* SPI_MEM_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN3_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN3_MODE_M  ((SPI_MEM_SMEM_DIN3_MODE_V)<<(SPI_MEM_SMEM_DIN3_MODE_S))
+#define SPI_MEM_SMEM_DIN3_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN3_MODE_S  9
+/* SPI_MEM_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN2_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN2_MODE_M  ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S))
+#define SPI_MEM_SMEM_DIN2_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN2_MODE_S  6
+/* SPI_MEM_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN1_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN1_MODE_M  ((SPI_MEM_SMEM_DIN1_MODE_V)<<(SPI_MEM_SMEM_DIN1_MODE_S))
+#define SPI_MEM_SMEM_DIN1_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN1_MODE_S  3
+/* SPI_MEM_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN0_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN0_MODE_M  ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S))
+#define SPI_MEM_SMEM_DIN0_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x198)
+/* SPI_MEM_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DINS_NUM    0x00000003
+#define SPI_MEM_SMEM_DINS_NUM_M  ((SPI_MEM_SMEM_DINS_NUM_V)<<(SPI_MEM_SMEM_DINS_NUM_S))
+#define SPI_MEM_SMEM_DINS_NUM_V  0x3
+#define SPI_MEM_SMEM_DINS_NUM_S  16
+/* SPI_MEM_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN7_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN7_NUM_M  ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S))
+#define SPI_MEM_SMEM_DIN7_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN7_NUM_S  14
+/* SPI_MEM_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN6_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN6_NUM_M  ((SPI_MEM_SMEM_DIN6_NUM_V)<<(SPI_MEM_SMEM_DIN6_NUM_S))
+#define SPI_MEM_SMEM_DIN6_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN6_NUM_S  12
+/* SPI_MEM_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN5_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN5_NUM_M  ((SPI_MEM_SMEM_DIN5_NUM_V)<<(SPI_MEM_SMEM_DIN5_NUM_S))
+#define SPI_MEM_SMEM_DIN5_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN5_NUM_S  10
+/* SPI_MEM_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN4_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN4_NUM_M  ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S))
+#define SPI_MEM_SMEM_DIN4_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN4_NUM_S  8
+/* SPI_MEM_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN3_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN3_NUM_M  ((SPI_MEM_SMEM_DIN3_NUM_V)<<(SPI_MEM_SMEM_DIN3_NUM_S))
+#define SPI_MEM_SMEM_DIN3_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN3_NUM_S  6
+/* SPI_MEM_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN2_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN2_NUM_M  ((SPI_MEM_SMEM_DIN2_NUM_V)<<(SPI_MEM_SMEM_DIN2_NUM_S))
+#define SPI_MEM_SMEM_DIN2_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN2_NUM_S  4
+/* SPI_MEM_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN1_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN1_NUM_M  ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S))
+#define SPI_MEM_SMEM_DIN1_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN1_NUM_S  2
+/* SPI_MEM_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN0_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN0_NUM_M  ((SPI_MEM_SMEM_DIN0_NUM_V)<<(SPI_MEM_SMEM_DIN0_NUM_S))
+#define SPI_MEM_SMEM_DIN0_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN0_NUM_S  0
+
+#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x19C)
+/* SPI_MEM_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_SMEM_DOUTS_MODE_M  (BIT(8))
+#define SPI_MEM_SMEM_DOUTS_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUTS_MODE_S  8
+/* SPI_MEM_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_SMEM_DOUT7_MODE_M  (BIT(7))
+#define SPI_MEM_SMEM_DOUT7_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT7_MODE_S  7
+/* SPI_MEM_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_SMEM_DOUT6_MODE_M  (BIT(6))
+#define SPI_MEM_SMEM_DOUT6_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT6_MODE_S  6
+/* SPI_MEM_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_SMEM_DOUT5_MODE_M  (BIT(5))
+#define SPI_MEM_SMEM_DOUT5_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT5_MODE_S  5
+/* SPI_MEM_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_SMEM_DOUT4_MODE_M  (BIT(4))
+#define SPI_MEM_SMEM_DOUT4_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT4_MODE_S  4
+/* SPI_MEM_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_SMEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_SMEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT3_MODE_S  3
+/* SPI_MEM_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_SMEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_SMEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT2_MODE_S  2
+/* SPI_MEM_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_SMEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_SMEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT1_MODE_S  1
+/* SPI_MEM_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_SMEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_SMEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A0)
+/* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
+ transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
+er whether there is an ECC region or not..*/
+#define SPI_MEM_SMEM_SPLIT_TRANS_EN    (BIT(31))
+#define SPI_MEM_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
+#define SPI_MEM_SMEM_SPLIT_TRANS_EN_V  0x1
+#define SPI_MEM_SMEM_SPLIT_TRANS_EN_S  31
+/* SPI_MEM_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
+SPI core clock cycles..*/
+#define SPI_MEM_SMEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SMEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_SMEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_SMEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+accesses external RAM..*/
+#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
+#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V  0x1
+#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S  16
+/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */
+/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
+en accesses external RAM..*/
+#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
+#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/* SPI_MEM_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
+ycles in ECC mode when accessed external RAM..*/
+#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME    0x00000007
+#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S))
+#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V  0x7
+#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S  12
+/* SPI_MEM_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */
+/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
+re combined with spi_mem_cs_hold bit..*/
+#define SPI_MEM_SMEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S))
+#define SPI_MEM_SMEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_SMEM_CS_HOLD_TIME_S  7
+/* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */
+/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
+pi_mem_cs_setup bit..*/
+#define SPI_MEM_SMEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SMEM_CS_SETUP_TIME_S))
+#define SPI_MEM_SMEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_SMEM_CS_SETUP_TIME_S  2
+/* SPI_MEM_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
+le..*/
+#define SPI_MEM_SMEM_CS_HOLD    (BIT(1))
+#define SPI_MEM_SMEM_CS_HOLD_M  (BIT(1))
+#define SPI_MEM_SMEM_CS_HOLD_V  0x1
+#define SPI_MEM_SMEM_CS_HOLD_S  1
+/* SPI_MEM_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
+isable..*/
+#define SPI_MEM_SMEM_CS_SETUP    (BIT(0))
+#define SPI_MEM_SMEM_CS_SETUP_M  (BIT(0))
+#define SPI_MEM_SMEM_CS_SETUP_V  0x1
+#define SPI_MEM_SMEM_CS_SETUP_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x200)
+/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
+#define SPI_MEM_CLK_EN    (BIT(0))
+#define SPI_MEM_CLK_EN_M  (BIT(0))
+#define SPI_MEM_CLK_EN_V  0x1
+#define SPI_MEM_CLK_EN_S  0
+
+#define SPI_MEM_MMU_ITEM_CONTENT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x37C)
+/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: MSPI-MMU item content.*/
+#define SPI_MEM_MMU_ITEM_CONTENT    0xFFFFFFFF
+#define SPI_MEM_MMU_ITEM_CONTENT_M  ((SPI_MEM_MMU_ITEM_CONTENT_V)<<(SPI_MEM_MMU_ITEM_CONTENT_S))
+#define SPI_MEM_MMU_ITEM_CONTENT_V  0xFFFFFFFF
+#define SPI_MEM_MMU_ITEM_CONTENT_S  0
+
+#define SPI_MEM_MMU_ITEM_INDEX_REG(i)          (REG_SPI_MEM_BASE(i) + 0x380)
+/* SPI_MEM_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: MSPI-MMU item index.*/
+#define SPI_MEM_MMU_ITEM_INDEX    0xFFFFFFFF
+#define SPI_MEM_MMU_ITEM_INDEX_M  ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S))
+#define SPI_MEM_MMU_ITEM_INDEX_V  0xFFFFFFFF
+#define SPI_MEM_MMU_ITEM_INDEX_S  0
+
+#define SPI_MEM_MMU_POWER_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x384)
+/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
+#define SPI_MEM_RDN_RESULT    (BIT(31))
+#define SPI_MEM_RDN_RESULT_M  (BIT(31))
+#define SPI_MEM_RDN_RESULT_V  0x1
+#define SPI_MEM_RDN_RESULT_S  31
+/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: ECO register enable bit.*/
+#define SPI_MEM_RDN_ENA    (BIT(30))
+#define SPI_MEM_RDN_ENA_M  (BIT(30))
+#define SPI_MEM_RDN_ENA_V  0x1
+#define SPI_MEM_RDN_ENA_S  30
+/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */
+/*description: MMU PSRAM aux control register.*/
+#define SPI_MEM_AUX_CTRL    0x00003FFF
+#define SPI_MEM_AUX_CTRL_M  ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S))
+#define SPI_MEM_AUX_CTRL_V  0x3FFF
+#define SPI_MEM_AUX_CTRL_S  16
+/* SPI_MEM_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
+/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/
+#define SPI_MEM_MMU_PAGE_SIZE    0x00000003
+#define SPI_MEM_MMU_PAGE_SIZE_M  ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S))
+#define SPI_MEM_MMU_PAGE_SIZE_V  0x3
+#define SPI_MEM_MMU_PAGE_SIZE_S  3
+/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
+ controlled by rtc..*/
+#define SPI_MEM_MMU_MEM_FORCE_PU    (BIT(2))
+#define SPI_MEM_MMU_MEM_FORCE_PU_M  (BIT(2))
+#define SPI_MEM_MMU_MEM_FORCE_PU_V  0x1
+#define SPI_MEM_MMU_MEM_FORCE_PU_S  2
+/* SPI_MEM_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to force mmu-memory powerdown.*/
+#define SPI_MEM_MMU_MEM_FORCE_PD    (BIT(1))
+#define SPI_MEM_MMU_MEM_FORCE_PD_M  (BIT(1))
+#define SPI_MEM_MMU_MEM_FORCE_PD_V  0x1
+#define SPI_MEM_MMU_MEM_FORCE_PD_S  1
+/* SPI_MEM_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable mmu-memory clock force on.*/
+#define SPI_MEM_MMU_MEM_FORCE_ON    (BIT(0))
+#define SPI_MEM_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define SPI_MEM_MMU_MEM_FORCE_ON_V  0x1
+#define SPI_MEM_MMU_MEM_FORCE_ON_S  0
+
+#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F0)
+/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: ECO high register.*/
+#define SPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_HIGH_M  ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S))
+#define SPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_HIGH_S  0
+
+#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F4)
+/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: ECO low register.*/
+#define SPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_LOW_M  ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S))
+#define SPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_LOW_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W; bitpos: [27:0] ;default: 35663920; */
+/*description: SPI0 register version..*/
+/* SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 35660128; */
+/*description: SPI1 register version..*/
+#define SPI_MEM_DATE    0x0FFFFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0xFFFFFFF
+#define SPI_MEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/spi_mem_struct.h b/components/soc/esp32c6/register/soc/spi_mem_struct.h
new file mode 100644
index 00000000000..74588ee0277
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/spi_mem_struct.h
@@ -0,0 +1,1081 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct spi_mem_dev_s {
+    union {
+        struct {
+            uint32_t mst_st                        :    4;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
+            uint32_t slv_st                        :    4;  /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
+            uint32_t reserved8                     :    9;  /*reserved*/
+            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t usr                           :    1;  /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
+            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/
+            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/
+            uint32_t fdummy_rin                    :    1;  /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/
+            uint32_t fdummy_wout                   :    1;  /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/
+            uint32_t fdout_oct                     :    1;  /*Apply 8 signals during write-data phase 1:enable 0: disable*/
+            uint32_t fdin_oct                      :    1;  /*Apply 8 signals during read-data phase 1:enable 0: disable*/
+            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during address phase 1:enable 0: disable*/
+            uint32_t reserved7                     :    1;  /*reserved*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable*/
+            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12                    :    1;  /*reserved*/
+            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
+            uint32_t reserved16                    :    2;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
+            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
+            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t reserved25                    :    5;  /*reserved*/
+            uint32_t dqs_ie_always_on              :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
+            uint32_t data_ie_always_on             :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
+            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
+            uint32_t reserved2                     :    9;  /*reserved*/
+            uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
+            uint32_t reg_aw_size0_1_support_en     :    1;  /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/
+            uint32_t reg_axi_rdata_back_fast       :    1;  /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/
+            uint32_t rresp_ecc_err_en              :    1;  /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/
+            uint32_t ar_splice_en                  :    1;  /*Set this bit to enable AXI Read Splice-transfer.*/
+            uint32_t aw_splice_en                  :    1;  /*Set this bit to enable AXI Write Splice-transfer.*/
+            uint32_t ram0_en                       :    1;  /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
+            uint32_t dual_ram_en                   :    1;  /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
+            uint32_t fast_write_en                 :    1;  /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.*/
+            uint32_t rxfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.*/
+            uint32_t txfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/
+            uint32_t cs_hold_time                  :    5;  /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/
+            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/
+            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
+            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
+            uint32_t reserved15                    :    9;  /*reserved*/
+            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
+            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t sync_reset                    :    1;  /*The spi0_mst_st and spi0_slv_st will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
+            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
+            uint32_t clk_equ_sysclk                :    1;  /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t ck_out_edge                   :    1;  /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
+            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
+            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
+            uint32_t reserved16                    :    8;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t usr_dbytelen                  :    3;  /*SPI0 USR_CMD read or write data byte length -1*/
+            uint32_t reserved9                     :    17;  /*reserved*/
+            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t reserved_30;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t reserved0                     :    5;  /*reserved*/
+            uint32_t fsub_pin                      :    1;  /*For SPI0,  flash is connected to SUBPINs.*/
+            uint32_t ssub_pin                      :    1;  /*For SPI0,  sram is connected to SUBPINs.*/
+            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle     0: spi clk line is low when idle */
+            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;
+    union {
+        struct {
+            uint32_t axi_req_en                    :    1;  /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/
+            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
+            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
+            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t reserved9                     :    21;  /*reserved*/
+            uint32_t reg_same_aw_ar_addr_chk_en    :    1;  /*Set this bit to check AXI read/write the same address region.*/
+            uint32_t reg_close_axi_inf_en          :    1;  /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    union {
+        struct {
+            uint32_t usr_saddr_4byte               :    1;  /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/
+            uint32_t usr_sram_dio                  :    1;  /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
+            uint32_t usr_sram_qio                  :    1;  /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
+            uint32_t usr_wr_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/
+            uint32_t usr_rd_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/
+            uint32_t sram_usr_rcmd                 :    1;  /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/
+            uint32_t sram_rdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved12                    :    2;  /*reserved*/
+            uint32_t sram_addr_bitlen              :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/
+            uint32_t sram_usr_wcmd                 :    1;  /*For SPI0, In the external RAM mode cache write sram for user define command*/
+            uint32_t sram_oct                      :    1;  /*reserved*/
+            uint32_t sram_wdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_sctrl;
+    union {
+        struct {
+            uint32_t sclk_mode                     :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
+            uint32_t swb_mode                      :    8;  /*Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t sdin_dual                     :    1;  /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t sdout_dual                    :    1;  /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t saddr_dual                    :    1;  /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t reserved13                    :    1;  /*reserved*/
+            uint32_t sdin_quad                     :    1;  /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t sdout_quad                    :    1;  /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t saddr_quad                    :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t scmd_quad                     :    1;  /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t sdin_oct                      :    1;  /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t sdout_oct                     :    1;  /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t saddr_oct                     :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t scmd_oct                      :    1;  /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t sdummy_rin                    :    1;  /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
+            uint32_t sdummy_wout                   :    1;  /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
+            uint32_t reg_smem_wdummy_dqs_always_out:    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/
+            uint32_t reg_smem_wdummy_always_out    :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/
+            uint32_t reserved26                    :    4;  /*reserved*/
+            uint32_t reg_smem_dqs_ie_always_on     :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
+            uint32_t reg_smem_data_ie_always_on    :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
+        };
+        uint32_t val;
+    } sram_cmd;
+    union {
+        struct {
+            uint32_t sram_usr_rd_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t sram_usr_rd_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_drd_cmd;
+    union {
+        struct {
+            uint32_t sram_usr_wr_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t sram_usr_wr_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_dwr_cmd;
+    union {
+        struct {
+            uint32_t sclkcnt_l                     :    8;  /*For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.*/
+            uint32_t sclkcnt_h                     :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t sclkcnt_n                     :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24                    :    7;  /*reserved*/
+            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/
+        };
+        uint32_t val;
+    } sram_clk;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;  /*reserved*/
+            uint32_t lock_delay_time               :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    uint32_t data_buf[16];
+    union {
+        struct {
+            uint32_t waiti_en                      :    1;  /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/
+            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
+            uint32_t waiti_addr_en                 :    1;  /*1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/
+            uint32_t waiti_addr_cyclelen           :    2;  /*When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/
+            uint32_t reserved5                     :    4;  /*reserved*/
+            uint32_t waiti_cmd_2b                  :    1;  /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/
+            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
+            uint32_t waiti_cmd                     :    16;  /*The command value to wait flash idle(RDSR).*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
+            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
+            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
+            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
+            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t flash_pes_command             :    16;  /*Program/Erase suspend command.*/
+            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
+            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
+            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
+            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
+            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
+            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
+            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
+            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
+            uint32_t reserved8                     :    7;  /*reserved*/
+            uint32_t flash_pesr_cmd_2b             :    1;  /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/
+            uint32_t flash_per_command             :    16;  /*Program/Erase resume command.*/
+        };
+        uint32_t val;
+    } sus_status;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    union {
+        struct {
+            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject_en                 :    1;  /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err_en           :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err                       :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject                    :    1;  /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
+            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
+            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/
+            uint32_t ecc_err                       :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
+            uint32_t pms_reject                    :    1;  /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/
+            uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
+            uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
+            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err                       :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject                    :    1;  /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_d0;
+    union {
+        struct {
+            uint32_t reg_fmem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
+            uint32_t reg_fmem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
+            uint32_t reg_fmem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
+            uint32_t reg_fmem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
+            uint32_t reg_fmem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
+            uint32_t reg_fmem_outminbytelen        :    7;  /*It is the minimum output data length in the panda device.*/
+            uint32_t reg_fmem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
+            uint32_t reg_fmem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/
+            uint32_t reg_fmem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
+            uint32_t reg_fmem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t reg_fmem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
+            uint32_t reserved25                    :    1;  /*reserved*/
+            uint32_t reg_fmem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
+            uint32_t reg_fmem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
+            uint32_t reg_fmem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
+            uint32_t reg_fmem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
+            uint32_t reg_fmem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } ddr;
+    union {
+        struct {
+            uint32_t reg_smem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
+            uint32_t reg_smem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
+            uint32_t reg_smem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
+            uint32_t reg_smem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
+            uint32_t reg_smem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
+            uint32_t reg_smem_outminbytelen        :    7;  /*It is the minimum output data length in the DDR psram.*/
+            uint32_t reg_smem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/
+            uint32_t reg_smem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/
+            uint32_t reg_smem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
+            uint32_t reg_smem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t reg_smem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
+            uint32_t reserved25                    :    1;  /*reserved*/
+            uint32_t reg_smem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
+            uint32_t reg_smem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
+            uint32_t reg_smem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
+            uint32_t reg_smem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
+            uint32_t reg_smem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_ddr;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    union {
+        struct {
+            uint32_t reg_fmem_pms0_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms0_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms0_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_attr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms1_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms1_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms1_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_attr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms2_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms2_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms2_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_attr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms3_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms3_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms3_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_attr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms0_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_addr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms1_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_addr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms2_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_addr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms3_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_addr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms0_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_size;
+    union {
+        struct {
+            uint32_t reg_fmem_pms1_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_size;
+    union {
+        struct {
+            uint32_t reg_fmem_pms2_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_size;
+    union {
+        struct {
+            uint32_t reg_fmem_pms3_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_size;
+    union {
+        struct {
+            uint32_t reg_smem_pms0_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms0_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms0_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_attr;
+    union {
+        struct {
+            uint32_t reg_smem_pms1_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms1_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms1_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_attr;
+    union {
+        struct {
+            uint32_t reg_smem_pms2_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms2_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms2_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_attr;
+    union {
+        struct {
+            uint32_t reg_smem_pms3_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms3_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms3_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_attr;
+    union {
+        struct {
+            uint32_t reg_smem_pms0_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_addr;
+    union {
+        struct {
+            uint32_t reg_smem_pms1_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_addr;
+    union {
+        struct {
+            uint32_t reg_smem_pms2_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_addr;
+    union {
+        struct {
+            uint32_t reg_smem_pms3_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_addr;
+    union {
+        struct {
+            uint32_t reg_smem_pms0_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_size;
+    union {
+        struct {
+            uint32_t reg_smem_pms1_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_size;
+    union {
+        struct {
+            uint32_t reg_smem_pms2_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_size;
+    union {
+        struct {
+            uint32_t reg_smem_pms3_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_size;
+    uint32_t reserved_160;
+    union {
+        struct {
+            uint32_t reject_addr                   :    26;  /*This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pm_en                         :    1;  /*Set this bit to enable SPI0/1 transfer permission control function.*/
+            uint32_t reserved27                    :    1;  /*reserved*/
+            uint32_t pms_ld                        :    1;  /*1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_st                        :    1;  /*1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_multi_hit                 :    1;  /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_ivd                       :    1;  /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+        };
+        uint32_t val;
+    } pms_reject;
+    union {
+        struct {
+            uint32_t reserved0                     :    11;  /*reserved*/
+            uint32_t ecc_err_int_num               :    6;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t reg_fmem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
+            uint32_t reg_fmem_page_size            :    2;  /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
+            uint32_t reg_fmem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/
+            uint32_t usr_ecc_addr_en               :    1;  /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t ecc_continue_record_err_en    :    1;  /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/
+            uint32_t ecc_err_bits                  :    7;  /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/
+        };
+        uint32_t val;
+    } ecc_ctrl;
+    union {
+        struct {
+            uint32_t ecc_err_addr                  :    26;  /*This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
+            uint32_t ecc_err_cnt                   :    6;  /*This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
+        };
+        uint32_t val;
+    } ecc_err_addr;
+    union {
+        struct {
+            uint32_t axi_err_addr                  :    26;  /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
+            uint32_t all_fifo_empty                :    1;  /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
+            uint32_t reg_rdata_afifo_rempty        :    1;  /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
+            uint32_t reg_raddr_afifo_rempty        :    1;  /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
+            uint32_t reg_wdata_afifo_rempty        :    1;  /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
+            uint32_t reg_wblen_afifo_rempty        :    1;  /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
+            uint32_t reg_all_axi_trans_afifo_empty :    1;  /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/
+        };
+        uint32_t val;
+    } axi_err_addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    17;  /*reserved*/
+            uint32_t reg_smem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
+            uint32_t reg_smem_page_size            :    2;  /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
+            uint32_t reg_smem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_ecc_ctrl;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    union {
+        struct {
+            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/
+            uint32_t timing_cali_update            :    1;  /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/
+            uint32_t reserved7                     :    25;  /*reserved*/
+        };
+        uint32_t val;
+    } timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t reg_smem_timing_clk_ena       :    1;  /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t reg_smem_timing_cali          :    1;  /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t reg_smem_extra_dummy_cyclelen :    3;  /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t reg_smem_dll_timing_cali      :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_timing_cali;
+    union {
+        struct {
+            uint32_t reg_smem_din0_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din1_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din2_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din3_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din4_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din5_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din6_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din7_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_dins_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_mode;
+    union {
+        struct {
+            uint32_t reg_smem_din0_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din1_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din2_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din3_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din4_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din5_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din6_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din7_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_dins_num             :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_num;
+    union {
+        struct {
+            uint32_t reg_smem_dout0_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout1_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout2_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout3_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout4_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout5_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout6_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout7_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_douts_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_dout_mode;
+    union {
+        struct {
+            uint32_t reg_smem_cs_setup             :    1;  /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */
+            uint32_t reg_smem_cs_hold              :    1;  /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
+            uint32_t reg_smem_cs_setup_time        :    5;  /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
+            uint32_t reg_smem_cs_hold_time         :    5;  /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
+            uint32_t reg_smem_ecc_cs_hold_time     :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/
+            uint32_t reg_smem_ecc_skip_page_corner :    1;  /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/
+            uint32_t reg_smem_ecc_16to18_byte_en   :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/
+            uint32_t reserved17                    :    8;  /*reserved*/
+            uint32_t reg_smem_cs_hold_delay        :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t reg_smem_split_trans_en       :    1;  /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
+        };
+        uint32_t val;
+    } spi_smem_ac;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t xts_plain_base;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    union {
+        struct {
+            uint32_t reg_xts_linesize              :    2;  /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_linesize;
+    union {
+        struct {
+            uint32_t reg_xts_destination           :    1;  /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_destination;
+    union {
+        struct {
+            uint32_t reg_xts_physical_address      :    26;  /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_physical_address;
+    union {
+        struct {
+            uint32_t reg_xts_trigger               :    1;  /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_trigger;
+    union {
+        struct {
+            uint32_t reg_xts_release               :    1;  /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_release;
+    union {
+        struct {
+            uint32_t reg_xts_destroy               :    1;  /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_destroy;
+    union {
+        struct {
+            uint32_t reg_xts_state                 :    2;  /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_state;
+    union {
+        struct {
+            uint32_t reg_xts_date                  :    30;  /*This bits stores the last modified-time of manual encryption feature.*/
+            uint32_t reserved30                    :    2;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_date;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t mmu_item_content;
+    uint32_t mmu_item_index;
+    union {
+        struct {
+            uint32_t reg_mmu_mem_force_on          :    1;  /*Set this bit to enable mmu-memory clock force on*/
+            uint32_t reg_mmu_mem_force_pd          :    1;  /*Set this bit to force mmu-memory powerdown*/
+            uint32_t reg_mmu_mem_force_pu          :    1;  /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/
+            uint32_t reg_mmu_page_size             :    2;  /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/
+            uint32_t reserved5                     :    11;  /*reserved*/
+            uint32_t aux_ctrl                      :    14;  /*MMU PSRAM aux control register*/
+            uint32_t rdn_ena                       :    1;  /*ECO register enable bit*/
+            uint32_t rdn_result                    :    1;  /*MSPI module clock domain and AXI clock domain ECO register result register*/
+        };
+        uint32_t val;
+    } mmu_power_ctrl;
+    union {
+        struct {
+            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
+            uint32_t reg_crypt_calc_d_dpa_en       :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
+            uint32_t reg_crypt_dpa_selectister     :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } dpa_ctrl;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t spi_memisterrnd_eco_high;
+    uint32_t spi_memisterrnd_eco_low;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI0/1 register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "Invalid size of spi_mem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/spi_reg.h b/components/soc/esp32c6/register/soc/spi_reg.h
new file mode 100644
index 00000000000..8da5868eaac
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/spi_reg.h
@@ -0,0 +1,2108 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI_CMD_REG register
+ *  Command control register
+ */
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
+/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+ */
+#define SPI_CONF_BITLEN    0x0003FFFFU
+#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
+#define SPI_CONF_BITLEN_V  0x0003FFFFU
+#define SPI_CONF_BITLEN_S  0
+/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
+ *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+ *  clock domain, which is only used in SPI master mode.
+ */
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
+#define SPI_UPDATE_V  0x00000001U
+#define SPI_UPDATE_S  23
+/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
+ *  User define command enable.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+ *  changed by CONF_buf.
+ */
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
+#define SPI_USR_V  0x00000001U
+#define SPI_USR_S  24
+
+/** SPI_ADDR_REG register
+ *  Address value register
+ */
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
+/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  Address to slave. Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_S  0
+
+/** SPI_CTRL_REG register
+ *  SPI control register
+ */
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
+/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
+ *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+ *  the FSPI bus signals are output. Can be configured in CONF state.
+ */
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
+#define SPI_DUMMY_OUT_V  0x00000001U
+#define SPI_DUMMY_OUT_S  3
+/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+ *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
+#define SPI_FADDR_DUAL_V  0x00000001U
+#define SPI_FADDR_DUAL_S  5
+/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
+ *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
+#define SPI_FADDR_QUAD_V  0x00000001U
+#define SPI_FADDR_QUAD_S  6
+/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0;
+ *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_OCT    (BIT(7))
+#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
+#define SPI_FADDR_OCT_V  0x00000001U
+#define SPI_FADDR_OCT_S  7
+/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
+ *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
+#define SPI_FCMD_DUAL_V  0x00000001U
+#define SPI_FCMD_DUAL_S  8
+/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
+ *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
+#define SPI_FCMD_QUAD_V  0x00000001U
+#define SPI_FCMD_QUAD_S  9
+/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0;
+ *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_OCT    (BIT(10))
+#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
+#define SPI_FCMD_OCT_V  0x00000001U
+#define SPI_FCMD_OCT_S  10
+/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
+#define SPI_FREAD_DUAL_V  0x00000001U
+#define SPI_FREAD_DUAL_S  14
+/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
+ *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
+#define SPI_FREAD_QUAD_V  0x00000001U
+#define SPI_FREAD_QUAD_S  15
+/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0;
+ *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_OCT    (BIT(16))
+#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
+#define SPI_FREAD_OCT_V  0x00000001U
+#define SPI_FREAD_OCT_S  16
+/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
+#define SPI_Q_POL_V  0x00000001U
+#define SPI_Q_POL_S  18
+/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
+#define SPI_D_POL_V  0x00000001U
+#define SPI_D_POL_S  19
+/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
+ *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+ *  configured in CONF state.
+ */
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
+#define SPI_HOLD_POL_V  0x00000001U
+#define SPI_HOLD_POL_S  20
+/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
+ *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
+#define SPI_WP_POL_V  0x00000001U
+#define SPI_WP_POL_S  21
+/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
+ *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+ *  state.
+ */
+#define SPI_RD_BIT_ORDER    0x00000003U
+#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
+#define SPI_RD_BIT_ORDER_V  0x00000003U
+#define SPI_RD_BIT_ORDER_S  23
+/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
+ *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+ *  configured in CONF state.
+ */
+#define SPI_WR_BIT_ORDER    0x00000003U
+#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
+#define SPI_WR_BIT_ORDER_V  0x00000003U
+#define SPI_WR_BIT_ORDER_S  25
+
+/** SPI_CLOCK_REG register
+ *  SPI clock control register
+ */
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
+/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
+ *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+ *  0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_L    0x0000003FU
+#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
+#define SPI_CLKCNT_L_V  0x0000003FU
+#define SPI_CLKCNT_L_S  0
+/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
+ *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+ *  must be 0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_H    0x0000003FU
+#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
+#define SPI_CLKCNT_H_V  0x0000003FU
+#define SPI_CLKCNT_H_S  6
+/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
+ *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+ *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_N    0x0000003FU
+#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
+#define SPI_CLKCNT_N_V  0x0000003FU
+#define SPI_CLKCNT_N_S  12
+/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
+ *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+ */
+#define SPI_CLKDIV_PRE    0x0000000FU
+#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
+#define SPI_CLKDIV_PRE_V  0x0000000FU
+#define SPI_CLKDIV_PRE_S  18
+/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
+ *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+ *  clock. Can be configured in CONF state.
+ */
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
+#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_CLK_EQU_SYSCLK_S  31
+
+/** SPI_USER_REG register
+ *  SPI USER control register
+ */
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
+/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
+ *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
+#define SPI_DOUTDIN_V  0x00000001U
+#define SPI_DOUTDIN_S  0
+/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
+ *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+ *  Can be configured in CONF state.
+ */
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
+#define SPI_QPI_MODE_V  0x00000001U
+#define SPI_QPI_MODE_S  3
+/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0;
+ *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+ *  Can be configured in CONF state.
+ */
+#define SPI_OPI_MODE    (BIT(4))
+#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
+#define SPI_OPI_MODE_V  0x00000001U
+#define SPI_OPI_MODE_S  4
+/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+ *  spi_ck_i. 1:tsck = !spi_ck_i.
+ */
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
+#define SPI_TSCK_I_EDGE_V  0x00000001U
+#define SPI_TSCK_I_EDGE_S  5
+/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
+ *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
+#define SPI_CS_HOLD_V  0x00000001U
+#define SPI_CS_HOLD_S  6
+/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
+ *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
+#define SPI_CS_SETUP_V  0x00000001U
+#define SPI_CS_SETUP_S  7
+/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+ *  !spi_ck_i. 1:rsck = spi_ck_i.
+ */
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
+#define SPI_RSCK_I_EDGE_V  0x00000001U
+#define SPI_RSCK_I_EDGE_S  8
+/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
+#define SPI_CK_OUT_EDGE_V  0x00000001U
+#define SPI_CK_OUT_EDGE_S  9
+/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+ *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
+#define SPI_FWRITE_DUAL_V  0x00000001U
+#define SPI_FWRITE_DUAL_S  12
+/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+ *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
+#define SPI_FWRITE_QUAD_V  0x00000001U
+#define SPI_FWRITE_QUAD_S  13
+/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0;
+ *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_OCT    (BIT(14))
+#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
+#define SPI_FWRITE_OCT_V  0x00000001U
+#define SPI_FWRITE_OCT_S  14
+/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
+ *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+ *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+ *  not seg-trans mode. Can be configured in CONF state.
+ */
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
+#define SPI_USR_CONF_NXT_V  0x00000001U
+#define SPI_USR_CONF_NXT_S  15
+/** SPI_SIO : R/W; bitpos: [17]; default: 0;
+ *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+ *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+ */
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
+#define SPI_SIO_V  0x00000001U
+#define SPI_SIO_S  17
+/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+ *  disable. Can be configured in CONF state.
+ */
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
+#define SPI_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI_USR_MISO_HIGHPART_S  24
+/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ *  0: disable.  Can be configured in CONF state.
+ */
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
+#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI_USR_MOSI_HIGHPART_S  25
+/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ *  CONF state.
+ */
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
+#define SPI_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_USR_DUMMY_IDLE_S  26
+/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
+ *  This bit enable the write-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
+#define SPI_USR_MOSI_V  0x00000001U
+#define SPI_USR_MOSI_S  27
+/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
+ *  This bit enable the read-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
+#define SPI_USR_MISO_V  0x00000001U
+#define SPI_USR_MISO_S  28
+/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
+#define SPI_USR_DUMMY_V  0x00000001U
+#define SPI_USR_DUMMY_S  29
+/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
+ *  This bit enable the address phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
+#define SPI_USR_ADDR_V  0x00000001U
+#define SPI_USR_ADDR_S  30
+/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+ *  This bit enable the command phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
+#define SPI_USR_COMMAND_V  0x00000001U
+#define SPI_USR_COMMAND_S  31
+
+/** SPI_USER1_REG register
+ *  SPI USER control register 1
+ */
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
+/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
+ *  The length in spi_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1). Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
+#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
+ *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+ *  GP-SPI master FD/HD-mode.
+ */
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
+#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
+ *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+ *  bit. Can be configured in CONF state.
+ */
+#define SPI_CS_SETUP_TIME    0x0000001FU
+#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
+#define SPI_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_CS_SETUP_TIME_S  17
+/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
+ *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS_HOLD_TIME    0x0000001FU
+#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
+#define SPI_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_CS_HOLD_TIME_S  22
+/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define SPI_USR_ADDR_BITLEN    0x0000001FU
+#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
+#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
+#define SPI_USR_ADDR_BITLEN_S  27
+
+/** SPI_USER2_REG register
+ *  SPI USER control register 2
+ */
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
+/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command. Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
+#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_S  0
+/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
+ *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+ *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+ *  is valid in GP-SPI master FD/HD-mode.
+ */
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
+#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_S  28
+
+/** SPI_MS_DLEN_REG register
+ *  SPI data bit length control register
+ */
+#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
+/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  The value of these bits is the configured SPI transmission data bit length in
+ *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+ *  the configured bit length in slave mode DMA RX controlled transfer. The register
+ *  value shall be (bit_num-1). Can be configured in CONF state.
+ */
+#define SPI_MS_DATA_BITLEN    0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
+#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_S  0
+
+/** SPI_MISC_REG register
+ *  SPI misc register
+ */
+#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
+/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
+#define SPI_CS0_DIS_V  0x00000001U
+#define SPI_CS0_DIS_S  0
+/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
+#define SPI_CS1_DIS_V  0x00000001U
+#define SPI_CS1_DIS_S  1
+/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
+#define SPI_CS2_DIS_V  0x00000001U
+#define SPI_CS2_DIS_S  2
+/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
+#define SPI_CS3_DIS_V  0x00000001U
+#define SPI_CS3_DIS_S  3
+/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
+#define SPI_CS4_DIS_V  0x00000001U
+#define SPI_CS4_DIS_S  4
+/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
+#define SPI_CS5_DIS_V  0x00000001U
+#define SPI_CS5_DIS_S  5
+/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
+ *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+ */
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
+#define SPI_CK_DIS_V  0x00000001U
+#define SPI_CK_DIS_S  6
+/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
+ *  In the master mode the bits are the polarity of spi cs line, the value is
+ *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+ */
+#define SPI_MASTER_CS_POL    0x0000003FU
+#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
+#define SPI_MASTER_CS_POL_V  0x0000003FU
+#define SPI_MASTER_CS_POL_S  7
+/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0;
+ *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+ *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+ */
+#define SPI_CLK_DATA_DTR_EN    (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
+#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
+#define SPI_CLK_DATA_DTR_EN_S  16
+/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0;
+ *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+ *  Can be configured in CONF state.
+ */
+#define SPI_DATA_DTR_EN    (BIT(17))
+#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
+#define SPI_DATA_DTR_EN_V  0x00000001U
+#define SPI_DATA_DTR_EN_S  17
+/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+#define SPI_ADDR_DTR_EN    (BIT(18))
+#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
+#define SPI_ADDR_DTR_EN_V  0x00000001U
+#define SPI_ADDR_DTR_EN_S  18
+/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+ *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CMD_DTR_EN    (BIT(19))
+#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
+#define SPI_CMD_DTR_EN_V  0x00000001U
+#define SPI_CMD_DTR_EN_S  19
+/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
+ *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+ *  CONF state.
+ */
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
+#define SPI_SLAVE_CS_POL_V  0x00000001U
+#define SPI_SLAVE_CS_POL_S  23
+/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0;
+ *  The default value of spi_dqs. Can be configured in CONF state.
+ */
+#define SPI_DQS_IDLE_EDGE    (BIT(24))
+#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
+#define SPI_DQS_IDLE_EDGE_V  0x00000001U
+#define SPI_DQS_IDLE_EDGE_S  24
+/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
+ *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
+#define SPI_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_CK_IDLE_EDGE_S  29
+/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
+ *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+ */
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
+#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_CS_KEEP_ACTIVE_S  30
+/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
+ *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+ *  spi quad input swap disable. Can be configured in CONF state.
+ */
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+
+/** SPI_DIN_MODE_REG register
+ *  SPI input delay mode configuration
+ */
+#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
+/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN0_MODE    0x00000003U
+#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
+#define SPI_DIN0_MODE_V  0x00000003U
+#define SPI_DIN0_MODE_S  0
+/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN1_MODE    0x00000003U
+#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
+#define SPI_DIN1_MODE_V  0x00000003U
+#define SPI_DIN1_MODE_S  2
+/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN2_MODE    0x00000003U
+#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
+#define SPI_DIN2_MODE_V  0x00000003U
+#define SPI_DIN2_MODE_S  4
+/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN3_MODE    0x00000003U
+#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
+#define SPI_DIN3_MODE_V  0x00000003U
+#define SPI_DIN3_MODE_S  6
+/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN4_MODE    0x00000003U
+#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
+#define SPI_DIN4_MODE_V  0x00000003U
+#define SPI_DIN4_MODE_S  8
+/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN5_MODE    0x00000003U
+#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
+#define SPI_DIN5_MODE_V  0x00000003U
+#define SPI_DIN5_MODE_S  10
+/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN6_MODE    0x00000003U
+#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
+#define SPI_DIN6_MODE_V  0x00000003U
+#define SPI_DIN6_MODE_S  12
+/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN7_MODE    0x00000003U
+#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
+#define SPI_DIN7_MODE_V  0x00000003U
+#define SPI_DIN7_MODE_S  14
+/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
+ *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+ *  state.
+ */
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
+#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+
+/** SPI_DIN_NUM_REG register
+ *  SPI input delay number configuration
+ */
+#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
+/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN0_NUM    0x00000003U
+#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
+#define SPI_DIN0_NUM_V  0x00000003U
+#define SPI_DIN0_NUM_S  0
+/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN1_NUM    0x00000003U
+#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
+#define SPI_DIN1_NUM_V  0x00000003U
+#define SPI_DIN1_NUM_S  2
+/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN2_NUM    0x00000003U
+#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
+#define SPI_DIN2_NUM_V  0x00000003U
+#define SPI_DIN2_NUM_S  4
+/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN3_NUM    0x00000003U
+#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
+#define SPI_DIN3_NUM_V  0x00000003U
+#define SPI_DIN3_NUM_S  6
+/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN4_NUM    0x00000003U
+#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
+#define SPI_DIN4_NUM_V  0x00000003U
+#define SPI_DIN4_NUM_S  8
+/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN5_NUM    0x00000003U
+#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
+#define SPI_DIN5_NUM_V  0x00000003U
+#define SPI_DIN5_NUM_S  10
+/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN6_NUM    0x00000003U
+#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
+#define SPI_DIN6_NUM_V  0x00000003U
+#define SPI_DIN6_NUM_S  12
+/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN7_NUM    0x00000003U
+#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
+#define SPI_DIN7_NUM_V  0x00000003U
+#define SPI_DIN7_NUM_S  14
+
+/** SPI_DOUT_MODE_REG register
+ *  SPI output delay mode configuration
+ */
+#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
+/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
+#define SPI_DOUT0_MODE_V  0x00000001U
+#define SPI_DOUT0_MODE_S  0
+/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
+#define SPI_DOUT1_MODE_V  0x00000001U
+#define SPI_DOUT1_MODE_S  1
+/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
+#define SPI_DOUT2_MODE_V  0x00000001U
+#define SPI_DOUT2_MODE_S  2
+/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
+#define SPI_DOUT3_MODE_V  0x00000001U
+#define SPI_DOUT3_MODE_S  3
+/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT4_MODE    (BIT(4))
+#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
+#define SPI_DOUT4_MODE_V  0x00000001U
+#define SPI_DOUT4_MODE_S  4
+/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT5_MODE    (BIT(5))
+#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
+#define SPI_DOUT5_MODE_V  0x00000001U
+#define SPI_DOUT5_MODE_S  5
+/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT6_MODE    (BIT(6))
+#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
+#define SPI_DOUT6_MODE_V  0x00000001U
+#define SPI_DOUT6_MODE_S  6
+/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT7_MODE    (BIT(7))
+#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
+#define SPI_DOUT7_MODE_V  0x00000001U
+#define SPI_DOUT7_MODE_S  7
+/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0;
+ *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+ *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_D_DQS_MODE    (BIT(8))
+#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
+#define SPI_D_DQS_MODE_V  0x00000001U
+#define SPI_D_DQS_MODE_S  8
+
+/** SPI_DMA_CONF_REG register
+ *  SPI DMA control register
+ */
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
+/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+ *  DMA TX FIFO is ready for sending data.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
+/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
+ *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+ *  0: DMA RX FIFO is ready for receiving data.
+ */
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
+#define SPI_DMA_INFIFO_FULL_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_S  1
+/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
+ *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+ */
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+ *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+ */
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+ *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+ */
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
+ *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+ *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+ *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+ *  spi_dma_seg_trans_done in seg-trans.
+ */
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
+#define SPI_RX_EOF_EN_V  0x00000001U
+#define SPI_RX_EOF_EN_S  21
+/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable SPI DMA controlled receive data mode.
+ */
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
+#define SPI_DMA_RX_ENA_V  0x00000001U
+#define SPI_DMA_RX_ENA_S  27
+/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to enable SPI DMA controlled send data mode.
+ */
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
+#define SPI_DMA_TX_ENA_V  0x00000001U
+#define SPI_DMA_TX_ENA_S  28
+/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
+ *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+ *  slave mode transfer.
+ */
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
+#define SPI_RX_AFIFO_RST_V  0x00000001U
+#define SPI_RX_AFIFO_RST_S  29
+/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
+ *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ *  controlled mode transfer and master mode transfer.
+ */
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
+#define SPI_BUF_AFIFO_RST_V  0x00000001U
+#define SPI_BUF_AFIFO_RST_S  30
+/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+ *  controlled mode transfer.
+ */
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
+#define SPI_DMA_AFIFO_RST_V  0x00000001U
+#define SPI_DMA_AFIFO_RST_S  31
+
+/** SPI_DMA_INT_ENA_REG register
+ *  SPI interrupt enable register
+ */
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
+#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
+#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
+#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
+#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
+#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
+#define SPI_APP2_INT_ENA_V  0x00000001U
+#define SPI_APP2_INT_ENA_S  19
+/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
+#define SPI_APP1_INT_ENA_V  0x00000001U
+#define SPI_APP1_INT_ENA_S  20
+
+/** SPI_DMA_INT_CLR_REG register
+ *  SPI interrupt clear register
+ */
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
+#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The clear bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
+#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
+#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
+#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
+#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  The clear bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
+#define SPI_APP2_INT_CLR_V  0x00000001U
+#define SPI_APP2_INT_CLR_S  19
+/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  The clear bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
+#define SPI_APP1_INT_CLR_V  0x00000001U
+#define SPI_APP1_INT_CLR_S  20
+
+/** SPI_DMA_INT_RAW_REG register
+ *  SPI interrupt raw register
+ */
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+ *  receive data.  0: Others.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ *  master mode and send out all 0 in slave mode.  0: Others.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+ *  is ended. 0: Others.
+ */
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+ *  is ended. 0: Others.
+ */
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
+#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
+#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
+#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
+#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ *  ended. 0: others.
+ */
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
+#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+ *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+ *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+ *  is not ended or not occurred.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+ *  is error in the DMA seg-conf-trans. 0: others.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+ *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+ *  bigger than 63. 0: Others.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ *  current SPI slave HD mode transmission is not supported. 0: Others.
+ */
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ *  write-full error when SPI inputs data in master mode. 0: Others.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+ *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+ */
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
+#define SPI_APP2_INT_RAW_V  0x00000001U
+#define SPI_APP2_INT_RAW_S  19
+/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+ */
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
+#define SPI_APP1_INT_RAW_V  0x00000001U
+#define SPI_APP1_INT_RAW_S  20
+
+/** SPI_DMA_INT_ST_REG register
+ *  SPI interrupt status register
+ */
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
+#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
+#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
+#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ST_S  4
+/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The status bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
+#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ST_S  5
+/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
+#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ST_S  6
+/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The status bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
+#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ST_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The status bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
+#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ST_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The status bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
+#define SPI_APP2_INT_ST_V  0x00000001U
+#define SPI_APP2_INT_ST_S  19
+/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The status bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
+#define SPI_APP1_INT_ST_V  0x00000001U
+#define SPI_APP1_INT_ST_S  20
+
+/** SPI_DMA_INT_SET_REG register
+ *  SPI interrupt software set register
+ */
+#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
+ *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
+ *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
+/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
+ *  The software set bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
+#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_SET_S  2
+/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
+ *  The software set bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
+#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_SET_S  3
+/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
+ *  The software set bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_SET    (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
+#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD7_INT_SET_S  4
+/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
+ *  The software set bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_SET    (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
+#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD8_INT_SET_S  5
+/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
+ *  The software set bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_SET    (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
+#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD9_INT_SET_S  6
+/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
+ *  The software set bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_SET    (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
+#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
+#define SPI_SLV_CMDA_INT_SET_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
+ *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
+#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
+ *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
+#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
+ *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
+#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
+ *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
+#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
+ *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
+#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_TRANS_DONE_INT_SET_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
+ *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
+/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
+ *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
+#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
+ *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
+ *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
+#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_SET_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
+ *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
+ *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
+ *  The software set bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_SET    (BIT(19))
+#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
+#define SPI_APP2_INT_SET_V  0x00000001U
+#define SPI_APP2_INT_SET_S  19
+/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
+ *  The software set bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_SET    (BIT(20))
+#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
+#define SPI_APP1_INT_SET_V  0x00000001U
+#define SPI_APP1_INT_SET_S  20
+
+/** SPI_W0_REG register
+ *  SPI CPU-controlled buffer0
+ */
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
+/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF0    0xFFFFFFFFU
+#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
+#define SPI_BUF0_V  0xFFFFFFFFU
+#define SPI_BUF0_S  0
+
+/** SPI_W1_REG register
+ *  SPI CPU-controlled buffer1
+ */
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
+/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF1    0xFFFFFFFFU
+#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
+#define SPI_BUF1_V  0xFFFFFFFFU
+#define SPI_BUF1_S  0
+
+/** SPI_W2_REG register
+ *  SPI CPU-controlled buffer2
+ */
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
+/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF2    0xFFFFFFFFU
+#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
+#define SPI_BUF2_V  0xFFFFFFFFU
+#define SPI_BUF2_S  0
+
+/** SPI_W3_REG register
+ *  SPI CPU-controlled buffer3
+ */
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
+/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF3    0xFFFFFFFFU
+#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
+#define SPI_BUF3_V  0xFFFFFFFFU
+#define SPI_BUF3_S  0
+
+/** SPI_W4_REG register
+ *  SPI CPU-controlled buffer4
+ */
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
+/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF4    0xFFFFFFFFU
+#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
+#define SPI_BUF4_V  0xFFFFFFFFU
+#define SPI_BUF4_S  0
+
+/** SPI_W5_REG register
+ *  SPI CPU-controlled buffer5
+ */
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
+/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF5    0xFFFFFFFFU
+#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
+#define SPI_BUF5_V  0xFFFFFFFFU
+#define SPI_BUF5_S  0
+
+/** SPI_W6_REG register
+ *  SPI CPU-controlled buffer6
+ */
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
+/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF6    0xFFFFFFFFU
+#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
+#define SPI_BUF6_V  0xFFFFFFFFU
+#define SPI_BUF6_S  0
+
+/** SPI_W7_REG register
+ *  SPI CPU-controlled buffer7
+ */
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
+/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF7    0xFFFFFFFFU
+#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
+#define SPI_BUF7_V  0xFFFFFFFFU
+#define SPI_BUF7_S  0
+
+/** SPI_W8_REG register
+ *  SPI CPU-controlled buffer8
+ */
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
+/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF8    0xFFFFFFFFU
+#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
+#define SPI_BUF8_V  0xFFFFFFFFU
+#define SPI_BUF8_S  0
+
+/** SPI_W9_REG register
+ *  SPI CPU-controlled buffer9
+ */
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
+/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF9    0xFFFFFFFFU
+#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
+#define SPI_BUF9_V  0xFFFFFFFFU
+#define SPI_BUF9_S  0
+
+/** SPI_W10_REG register
+ *  SPI CPU-controlled buffer10
+ */
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
+/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF10    0xFFFFFFFFU
+#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
+#define SPI_BUF10_V  0xFFFFFFFFU
+#define SPI_BUF10_S  0
+
+/** SPI_W11_REG register
+ *  SPI CPU-controlled buffer11
+ */
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
+/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF11    0xFFFFFFFFU
+#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
+#define SPI_BUF11_V  0xFFFFFFFFU
+#define SPI_BUF11_S  0
+
+/** SPI_W12_REG register
+ *  SPI CPU-controlled buffer12
+ */
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
+/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF12    0xFFFFFFFFU
+#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
+#define SPI_BUF12_V  0xFFFFFFFFU
+#define SPI_BUF12_S  0
+
+/** SPI_W13_REG register
+ *  SPI CPU-controlled buffer13
+ */
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
+/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF13    0xFFFFFFFFU
+#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
+#define SPI_BUF13_V  0xFFFFFFFFU
+#define SPI_BUF13_S  0
+
+/** SPI_W14_REG register
+ *  SPI CPU-controlled buffer14
+ */
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
+/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF14    0xFFFFFFFFU
+#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
+#define SPI_BUF14_V  0xFFFFFFFFU
+#define SPI_BUF14_S  0
+
+/** SPI_W15_REG register
+ *  SPI CPU-controlled buffer15
+ */
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
+/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF15    0xFFFFFFFFU
+#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
+#define SPI_BUF15_V  0xFFFFFFFFU
+#define SPI_BUF15_S  0
+
+/** SPI_SLAVE_REG register
+ *  SPI slave control register
+ */
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
+/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on. Can be configured in CONF state.
+ */
+#define SPI_CLK_MODE    0x00000003U
+#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
+#define SPI_CLK_MODE_V  0x00000003U
+#define SPI_CLK_MODE_S  0
+/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
+ *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+ *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+ */
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
+#define SPI_CLK_MODE_13_V  0x00000001U
+#define SPI_CLK_MODE_13_S  2
+/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
+ *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+ *  0: output data at tsck posedge
+ */
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
+#define SPI_RSCK_DATA_OUT_V  0x00000001U
+#define SPI_RSCK_DATA_OUT_S  3
+/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  DMA controlled mode(Rd_DMA). 0: others
+ */
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in DMA controlled mode(Wr_DMA). 0: others
+ */
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  CPU controlled mode(Rd_BUF). 0: others
+ */
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in CPU controlled mode(Wr_BUF). 0: others
+ */
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
+ *  The magic value of BM table in master DMA seg-trans.
+ */
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
+ *  Set SPI work mode. 1: slave mode 0: master mode.
+ */
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
+#define SPI_SLAVE_MODE_V  0x00000001U
+#define SPI_SLAVE_MODE_S  26
+/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
+ *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+ *  configured in CONF state.
+ */
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
+#define SPI_SOFT_RESET_V  0x00000001U
+#define SPI_SOFT_RESET_S  27
+/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
+ *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+ *  will start. 0: This is not seg-trans mode.
+ */
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
+#define SPI_USR_CONF_V  0x00000001U
+#define SPI_USR_CONF_S  28
+/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
+ *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+ *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+ *  transfer.
+ */
+#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
+
+/** SPI_SLAVE1_REG register
+ *  SPI slave control register 1
+ */
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
+/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
+ *  The transferred data bit length in SPI slave FD and HD mode.
+ */
+#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
+#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_S  0
+/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
+ *  In the slave mode it is the value of command.
+ */
+#define SPI_SLV_LAST_COMMAND    0x000000FFU
+#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
+#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
+#define SPI_SLV_LAST_COMMAND_S  18
+/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
+ *  In the slave mode it is the value of address.
+ */
+#define SPI_SLV_LAST_ADDR    0x0000003FU
+#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
+#define SPI_SLV_LAST_ADDR_V  0x0000003FU
+#define SPI_SLV_LAST_ADDR_S  26
+
+/** SPI_CLK_GATE_REG register
+ *  SPI module clock and register clock control
+ */
+#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
+/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
+#define SPI_CLK_EN_V  0x00000001U
+#define SPI_CLK_EN_S  0
+/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to power on the SPI module clock.
+ */
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
+#define SPI_MST_CLK_ACTIVE_V  0x00000001U
+#define SPI_MST_CLK_ACTIVE_S  1
+/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+ *  0: XTAL CLK.
+ */
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
+#define SPI_MST_CLK_SEL_V  0x00000001U
+#define SPI_MST_CLK_SEL_S  2
+
+/** SPI_DATE_REG register
+ *  Version control
+ */
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
+/** SPI_DATE : R/W; bitpos: [27:0]; default: 35656448;
+ *  SPI register version.
+ */
+#define SPI_DATE    0x0FFFFFFFU
+#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
+#define SPI_DATE_V  0x0FFFFFFFU
+#define SPI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/spi_struct.h b/components/soc/esp32c6/register/soc/spi_struct.h
new file mode 100644
index 00000000000..52076bb16c8
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/spi_struct.h
@@ -0,0 +1,1400 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: User-defined control registers */
+/** Type of cmd register
+ *  Command control register
+ */
+typedef union {
+    struct {
+        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+         */
+        uint32_t conf_bitlen:18;
+        uint32_t reserved_18:5;
+        /** update : WT; bitpos: [23]; default: 0;
+         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+         *  clock domain, which is only used in SPI master mode.
+         */
+        uint32_t update:1;
+        /** usr : R/W/SC; bitpos: [24]; default: 0;
+         *  User define command enable.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+         *  changed by CONF_buf.
+         */
+        uint32_t usr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} spi_cmd_reg_t;
+
+/** Type of addr register
+ *  Address value register
+ */
+typedef union {
+    struct {
+        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  Address to slave. Can be configured in CONF state.
+         */
+        uint32_t usr_addr_value:32;
+    };
+    uint32_t val;
+} spi_addr_reg_t;
+
+/** Type of user register
+ *  SPI USER control register
+ */
+typedef union {
+    struct {
+        /** doutdin : R/W; bitpos: [0]; default: 0;
+         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t doutdin:1;
+        uint32_t reserved_1:2;
+        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
+         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t qpi_mode:1;
+        /** opi_mode : HRO; bitpos: [4]; default: 0;
+         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t opi_mode:1;
+        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+         *  spi_ck_i. 1:tsck = !spi_ck_i.
+         */
+        uint32_t tsck_i_edge:1;
+        /** cs_hold : R/W; bitpos: [6]; default: 1;
+         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_hold:1;
+        /** cs_setup : R/W; bitpos: [7]; default: 1;
+         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_setup:1;
+        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+         *  !spi_ck_i. 1:rsck = spi_ck_i.
+         */
+        uint32_t rsck_i_edge:1;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+         *  be configured in CONF state.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:2;
+        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
+         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_dual:1;
+        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
+         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_quad:1;
+        /** fwrite_oct : HRO; bitpos: [14]; default: 0;
+         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_oct:1;
+        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
+         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+         *  not seg-trans mode. Can be configured in CONF state.
+         */
+        uint32_t usr_conf_nxt:1;
+        uint32_t reserved_16:1;
+        /** sio : R/W; bitpos: [17]; default: 0;
+         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+         */
+        uint32_t sio:1;
+        uint32_t reserved_18:6;
+        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
+         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+         *  disable. Can be configured in CONF state.
+         */
+        uint32_t usr_miso_highpart:1;
+        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
+         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+         *  0: disable.  Can be configured in CONF state.
+         */
+        uint32_t usr_mosi_highpart:1;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+         *  CONF state.
+         */
+        uint32_t usr_dummy_idle:1;
+        /** usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  This bit enable the write-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_mosi:1;
+        /** usr_miso : R/W; bitpos: [28]; default: 0;
+         *  This bit enable the read-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_miso:1;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_dummy:1;
+        /** usr_addr : R/W; bitpos: [30]; default: 0;
+         *  This bit enable the address phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_addr:1;
+        /** usr_command : R/W; bitpos: [31]; default: 1;
+         *  This bit enable the command phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_command:1;
+    };
+    uint32_t val;
+} spi_user_reg_t;
+
+/** Type of user1 register
+ *  SPI USER control register 1
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
+         *  The length in spi_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1). Can be configured in CONF state.
+         */
+        uint32_t usr_dummy_cyclelen:8;
+        uint32_t reserved_8:8;
+        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
+         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+         *  GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_wfull_err_end_en:1;
+        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
+         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+         *  bit. Can be configured in CONF state.
+         */
+        uint32_t cs_setup_time:5;
+        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
+         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs_hold_time:5;
+        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_addr_bitlen:5;
+    };
+    uint32_t val;
+} spi_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI USER control register 2
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command. Can be configured in CONF state.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:11;
+        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
+         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+         *  is valid in GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_rempty_err_end_en:1;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi_user2_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of ctrl register
+ *  SPI control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** dummy_out : R/W; bitpos: [3]; default: 0;
+         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+         *  the FSPI bus signals are output. Can be configured in CONF state.
+         */
+        uint32_t dummy_out:1;
+        uint32_t reserved_4:1;
+        /** faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_dual:1;
+        /** faddr_quad : R/W; bitpos: [6]; default: 0;
+         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_quad:1;
+        /** faddr_oct : HRO; bitpos: [7]; default: 0;
+         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_oct:1;
+        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
+         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_dual:1;
+        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : HRO; bitpos: [10]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_oct:1;
+        uint32_t reserved_11:3;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_dual:1;
+        /** fread_quad : R/W; bitpos: [15]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_quad:1;
+        /** fread_oct : HRO; bitpos: [16]; default: 0;
+         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_oct:1;
+        uint32_t reserved_17:1;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t d_pol:1;
+        /** hold_pol : R/W; bitpos: [20]; default: 1;
+         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+         *  configured in CONF state.
+         */
+        uint32_t hold_pol:1;
+        /** wp_pol : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t wp_pol:1;
+        uint32_t reserved_22:1;
+        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
+         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+         *  state.
+         */
+        uint32_t rd_bit_order:2;
+        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
+         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+         *  configured in CONF state.
+         */
+        uint32_t wr_bit_order:2;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_ctrl_reg_t;
+
+/** Type of ms_dlen register
+ *  SPI data bit length control register
+ */
+typedef union {
+    struct {
+        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  The value of these bits is the configured SPI transmission data bit length in
+         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+         *  the configured bit length in slave mode DMA RX controlled transfer. The register
+         *  value shall be (bit_num-1). Can be configured in CONF state.
+         */
+        uint32_t ms_data_bitlen:18;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_ms_dlen_reg_t;
+
+/** Type of misc register
+ *  SPI misc register
+ */
+typedef union {
+    struct {
+        /** cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs0_dis:1;
+        /** cs1_dis : R/W; bitpos: [1]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs1_dis:1;
+        /** cs2_dis : R/W; bitpos: [2]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs2_dis:1;
+        /** cs3_dis : R/W; bitpos: [3]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs3_dis:1;
+        /** cs4_dis : R/W; bitpos: [4]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs4_dis:1;
+        /** cs5_dis : R/W; bitpos: [5]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs5_dis:1;
+        /** ck_dis : R/W; bitpos: [6]; default: 0;
+         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+         */
+        uint32_t ck_dis:1;
+        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
+         *  In the master mode the bits are the polarity of spi cs line, the value is
+         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+         */
+        uint32_t master_cs_pol:6;
+        uint32_t reserved_13:3;
+        /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0;
+         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+         */
+        uint32_t clk_data_dtr_en:1;
+        /** data_dtr_en : HRO; bitpos: [17]; default: 0;
+         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+         *  Can be configured in CONF state.
+         */
+        uint32_t data_dtr_en:1;
+        /** addr_dtr_en : HRO; bitpos: [18]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t addr_dtr_en:1;
+        /** cmd_dtr_en : HRO; bitpos: [19]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cmd_dtr_en:1;
+        uint32_t reserved_20:3;
+        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
+         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+         *  CONF state.
+         */
+        uint32_t slave_cs_pol:1;
+        /** dqs_idle_edge : HRO; bitpos: [24]; default: 0;
+         *  The default value of spi_dqs. Can be configured in CONF state.
+         */
+        uint32_t dqs_idle_edge:1;
+        uint32_t reserved_25:4;
+        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
+         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+         *  configured in CONF state.
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
+         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+         */
+        uint32_t cs_keep_active:1;
+        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
+         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+         *  spi quad input swap disable. Can be configured in CONF state.
+         */
+        uint32_t quad_din_pin_swap:1;
+    };
+    uint32_t val;
+} spi_misc_reg_t;
+
+/** Type of dma_conf register
+ *  SPI DMA control register
+ */
+typedef union {
+    struct {
+        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
+         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+         *  DMA TX FIFO is ready for sending data.
+         */
+        uint32_t dma_outfifo_empty:1;
+        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
+         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+         *  0: DMA RX FIFO is ready for receiving data.
+         */
+        uint32_t dma_infifo_full:1;
+        uint32_t reserved_2:16;
+        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
+         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+         */
+        uint32_t dma_slv_seg_trans_en:1;
+        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
+         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_rx_seg_trans_clr_en:1;
+        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
+         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_tx_seg_trans_clr_en:1;
+        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
+         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+         *  spi_dma_seg_trans_done in seg-trans.
+         */
+        uint32_t rx_eof_en:1;
+        uint32_t reserved_22:5;
+        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable SPI DMA controlled receive data mode.
+         */
+        uint32_t dma_rx_ena:1;
+        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable SPI DMA controlled send data mode.
+         */
+        uint32_t dma_tx_ena:1;
+        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
+         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+         *  slave mode transfer.
+         */
+        uint32_t rx_afifo_rst:1;
+        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
+         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+         *  controlled mode transfer and master mode transfer.
+         */
+        uint32_t buf_afifo_rst:1;
+        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+         *  controlled mode transfer.
+         */
+        uint32_t dma_afifo_rst:1;
+    };
+    uint32_t val;
+} spi_dma_conf_reg_t;
+
+/** Type of slave register
+ *  SPI slave control register
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on. Can be configured in CONF state.
+         */
+        uint32_t clk_mode:2;
+        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
+         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+         */
+        uint32_t clk_mode_13:1;
+        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
+         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+         *  0: output data at tsck posedge
+         */
+        uint32_t rsck_data_out:1;
+        uint32_t reserved_4:4;
+        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  DMA controlled mode(Rd_DMA). 0: others
+         */
+        uint32_t slv_rddma_bitlen_en:1;
+        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in DMA controlled mode(Wr_DMA). 0: others
+         */
+        uint32_t slv_wrdma_bitlen_en:1;
+        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  CPU controlled mode(Rd_BUF). 0: others
+         */
+        uint32_t slv_rdbuf_bitlen_en:1;
+        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in CPU controlled mode(Wr_BUF). 0: others
+         */
+        uint32_t slv_wrbuf_bitlen_en:1;
+        uint32_t reserved_12:10;
+        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
+         *  The magic value of BM table in master DMA seg-trans.
+         */
+        uint32_t dma_seg_magic_value:4;
+        /** slave_mode : R/W; bitpos: [26]; default: 0;
+         *  Set SPI work mode. 1: slave mode 0: master mode.
+         */
+        uint32_t slave_mode:1;
+        /** soft_reset : WT; bitpos: [27]; default: 0;
+         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+         *  configured in CONF state.
+         */
+        uint32_t soft_reset:1;
+        /** usr_conf : R/W; bitpos: [28]; default: 0;
+         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+         *  will start. 0: This is not seg-trans mode.
+         */
+        uint32_t usr_conf:1;
+        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
+         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+         *  transfer.
+         */
+        uint32_t mst_fd_wait_dma_tx_data:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_slave_reg_t;
+
+/** Type of slave1 register
+ *  SPI slave control register 1
+ */
+typedef union {
+    struct {
+        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
+         *  The transferred data bit length in SPI slave FD and HD mode.
+         */
+        uint32_t slv_data_bitlen:18;
+        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
+         *  In the slave mode it is the value of command.
+         */
+        uint32_t slv_last_command:8;
+        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
+         *  In the slave mode it is the value of address.
+         */
+        uint32_t slv_last_addr:6;
+    };
+    uint32_t val;
+} spi_slave1_reg_t;
+
+
+/** Group: Clock control registers */
+/** Type of clock register
+ *  SPI clock control register
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
+         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+         *  0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_l:6;
+        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
+         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+         *  must be 0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_h:6;
+        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
+         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+         */
+        uint32_t clkcnt_n:6;
+        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
+         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+         */
+        uint32_t clkdiv_pre:4;
+        uint32_t reserved_22:9;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+         *  clock. Can be configured in CONF state.
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_clock_reg_t;
+
+/** Type of clk_gate register
+ *  SPI module clock and register clock control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to power on the SPI module clock.
+         */
+        uint32_t mst_clk_active:1;
+        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+         *  0: XTAL CLK.
+         */
+        uint32_t mst_clk_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_clk_gate_reg_t;
+
+
+/** Group: Timing registers */
+/** Type of din_mode register
+ *  SPI input delay mode configuration
+ */
+typedef union {
+    struct {
+        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din0_mode:2;
+        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din1_mode:2;
+        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din2_mode:2;
+        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din3_mode:2;
+        /** din4_mode : HRO; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din4_mode:2;
+        /** din5_mode : HRO; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din5_mode:2;
+        /** din6_mode : HRO; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din6_mode:2;
+        /** din7_mode : HRO; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din7_mode:2;
+        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
+         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+         *  state.
+         */
+        uint32_t timing_hclk_active:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} spi_din_mode_reg_t;
+
+/** Type of din_num register
+ *  SPI input delay number configuration
+ */
+typedef union {
+    struct {
+        /** din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din0_num:2;
+        /** din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din1_num:2;
+        /** din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din2_num:2;
+        /** din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din3_num:2;
+        /** din4_num : HRO; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din4_num:2;
+        /** din5_num : HRO; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din5_num:2;
+        /** din6_num : HRO; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din6_num:2;
+        /** din7_num : HRO; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din7_num:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} spi_din_num_reg_t;
+
+/** Type of dout_mode register
+ *  SPI output delay mode configuration
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout0_mode:1;
+        /** dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout1_mode:1;
+        /** dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout2_mode:1;
+        /** dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout3_mode:1;
+        /** dout4_mode : HRO; bitpos: [4]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout4_mode:1;
+        /** dout5_mode : HRO; bitpos: [5]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout5_mode:1;
+        /** dout6_mode : HRO; bitpos: [6]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout6_mode:1;
+        /** dout7_mode : HRO; bitpos: [7]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout7_mode:1;
+        /** d_dqs_mode : HRO; bitpos: [8]; default: 0;
+         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t d_dqs_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_dout_mode_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of dma_int_ena register
+ *  SPI interrupt enable register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : R/W; bitpos: [5]; default: 0;
+         *  The enable bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : R/W; bitpos: [6]; default: 0;
+         *  The enable bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : R/W; bitpos: [7]; default: 0;
+         *  The enable bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : R/W; bitpos: [8]; default: 0;
+         *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : R/W; bitpos: [9]; default: 0;
+         *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : R/W; bitpos: [11]; default: 0;
+         *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : R/W; bitpos: [12]; default: 0;
+         *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : R/W; bitpos: [13]; default: 0;
+         *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : R/W; bitpos: [14]; default: 0;
+         *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : R/W; bitpos: [15]; default: 0;
+         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : R/W; bitpos: [16]; default: 0;
+         *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : R/W; bitpos: [17]; default: 0;
+         *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : R/W; bitpos: [18]; default: 0;
+         *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : R/W; bitpos: [19]; default: 0;
+         *  The enable bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2:1;
+        /** app1 : R/W; bitpos: [20]; default: 0;
+         *  The enable bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_ena_reg_t;
+
+/** Type of dma_int_clr register
+ *  SPI interrupt clear register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : WT; bitpos: [0]; default: 0;
+         *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0;
+         *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : WT; bitpos: [2]; default: 0;
+         *  The clear bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : WT; bitpos: [3]; default: 0;
+         *  The clear bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : WT; bitpos: [4]; default: 0;
+         *  The clear bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : WT; bitpos: [5]; default: 0;
+         *  The clear bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : WT; bitpos: [6]; default: 0;
+         *  The clear bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : WT; bitpos: [7]; default: 0;
+         *  The clear bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : WT; bitpos: [8]; default: 0;
+         *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : WT; bitpos: [9]; default: 0;
+         *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : WT; bitpos: [10]; default: 0;
+         *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : WT; bitpos: [11]; default: 0;
+         *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : WT; bitpos: [12]; default: 0;
+         *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : WT; bitpos: [13]; default: 0;
+         *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : WT; bitpos: [14]; default: 0;
+         *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : WT; bitpos: [15]; default: 0;
+         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : WT; bitpos: [16]; default: 0;
+         *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0;
+         *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0;
+         *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : WT; bitpos: [19]; default: 0;
+         *  The clear bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2:1;
+        /** app1 : WT; bitpos: [20]; default: 0;
+         *  The clear bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_clr_reg_t;
+
+/** Type of dma_int_raw register
+ *  SPI interrupt raw register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : R/WTC/SS; bitpos: [0]; default: 0;
+         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+         *  receive data.  0: Others.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : R/WTC/SS; bitpos: [1]; default: 0;
+         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+         *  master mode and send out all 0 in slave mode.  0: Others.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+         *  ended. 0: others.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+         *  is not ended or not occurred.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+         *  is error in the DMA seg-conf-trans. 0: others.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+         *  bigger than 63. 0: Others.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+         *  current SPI slave HD mode transmission is not supported. 0: Others.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+         *  write-full error when SPI inputs data in master mode. 0: Others.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app2:1;
+        /** app1 : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_raw_reg_t;
+
+/** Type of dma_int_st register
+ *  SPI interrupt status register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : RO; bitpos: [0]; default: 0;
+         *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : RO; bitpos: [1]; default: 0;
+         *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : RO; bitpos: [2]; default: 0;
+         *  The status bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : RO; bitpos: [3]; default: 0;
+         *  The status bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : RO; bitpos: [4]; default: 0;
+         *  The status bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : RO; bitpos: [5]; default: 0;
+         *  The status bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : RO; bitpos: [6]; default: 0;
+         *  The status bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : RO; bitpos: [7]; default: 0;
+         *  The status bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : RO; bitpos: [8]; default: 0;
+         *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : RO; bitpos: [9]; default: 0;
+         *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : RO; bitpos: [10]; default: 0;
+         *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : RO; bitpos: [11]; default: 0;
+         *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : RO; bitpos: [12]; default: 0;
+         *  The status bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : RO; bitpos: [13]; default: 0;
+         *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : RO; bitpos: [14]; default: 0;
+         *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : RO; bitpos: [15]; default: 0;
+         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : RO; bitpos: [16]; default: 0;
+         *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : RO; bitpos: [17]; default: 0;
+         *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : RO; bitpos: [18]; default: 0;
+         *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : RO; bitpos: [19]; default: 0;
+         *  The status bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2:1;
+        /** app1 : RO; bitpos: [20]; default: 0;
+         *  The status bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_st_reg_t;
+
+/** Type of dma_int_set register
+ *  SPI interrupt software set register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
+         *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_set:1;
+        /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
+         *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_set:1;
+        /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
+         *  The software set bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_set:1;
+        /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
+         *  The software set bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_set:1;
+        /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
+         *  The software set bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_set:1;
+        /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
+         *  The software set bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_set:1;
+        /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
+         *  The software set bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_set:1;
+        /** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
+         *  The software set bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_set:1;
+        /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
+         *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_set:1;
+        /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
+         *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_set:1;
+        /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
+         *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_set:1;
+        /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
+         *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_set:1;
+        /** trans_done_int_set : WT; bitpos: [12]; default: 0;
+         *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_set:1;
+        /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
+         *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_set:1;
+        /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
+         *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_set:1;
+        /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
+         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_set:1;
+        /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
+         *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_set:1;
+        /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
+         *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_set:1;
+        /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
+         *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_set:1;
+        /** app2_int_set : WT; bitpos: [19]; default: 0;
+         *  The software set bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_set:1;
+        /** app1_int_set : WT; bitpos: [20]; default: 0;
+         *  The software set bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_set:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_set_reg_t;
+
+
+/** Group: CPU-controlled data buffer */
+/** Type of wn register
+ *  SPI CPU-controlled buffer
+ */
+typedef union {
+    struct {
+        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf:32;
+    };
+    uint32_t val;
+} spi_wn_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35656448;
+         *  SPI register version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_date_reg_t;
+
+
+typedef struct spi_dev_t {
+    volatile spi_cmd_reg_t cmd;
+    volatile spi_addr_reg_t addr;
+    volatile spi_ctrl_reg_t ctrl;
+    volatile spi_clock_reg_t clock;
+    volatile spi_user_reg_t user;
+    volatile spi_user1_reg_t user1;
+    volatile spi_user2_reg_t user2;
+    volatile spi_ms_dlen_reg_t ms_dlen;
+    volatile spi_misc_reg_t misc;
+    volatile spi_din_mode_reg_t din_mode;
+    volatile spi_din_num_reg_t din_num;
+    volatile spi_dout_mode_reg_t dout_mode;
+    volatile spi_dma_conf_reg_t dma_conf;
+    volatile spi_dma_int_ena_reg_t dma_int_ena;
+    volatile spi_dma_int_clr_reg_t dma_int_clr;
+    volatile spi_dma_int_raw_reg_t dma_int_raw;
+    volatile spi_dma_int_st_reg_t dma_int_st;
+    volatile spi_dma_int_set_reg_t dma_int_set;
+    uint32_t reserved_048[20];
+    volatile spi_wn_reg_t data_buf[16];
+    uint32_t reserved_0d8[2];
+    volatile spi_slave_reg_t slave;
+    volatile spi_slave1_reg_t slave1;
+    volatile spi_clk_gate_reg_t clk_gate;
+    uint32_t reserved_0ec;
+    volatile spi_date_reg_t date;
+} spi_dev_t;
+
+extern spi_dev_t GPSPI2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/systimer_reg.h b/components/soc/esp32c6/register/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/systimer_reg.h
rename to components/soc/esp32c6/register/soc/systimer_reg.h
diff --git a/components/soc/esp32c6/include/soc/systimer_struct.h b/components/soc/esp32c6/register/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/systimer_struct.h
rename to components/soc/esp32c6/register/soc/systimer_struct.h
diff --git a/components/soc/esp32c6/include/soc/tee_reg.h b/components/soc/esp32c6/register/soc/tee_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/tee_reg.h
rename to components/soc/esp32c6/register/soc/tee_reg.h
diff --git a/components/soc/esp32c6/include/soc/tee_struct.h b/components/soc/esp32c6/register/soc/tee_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/tee_struct.h
rename to components/soc/esp32c6/register/soc/tee_struct.h
diff --git a/components/soc/esp32c6/include/soc/timer_group_reg.h b/components/soc/esp32c6/register/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/timer_group_reg.h
rename to components/soc/esp32c6/register/soc/timer_group_reg.h
diff --git a/components/soc/esp32c6/include/soc/timer_group_struct.h b/components/soc/esp32c6/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/timer_group_struct.h
rename to components/soc/esp32c6/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32c6/register/soc/trace_reg.h b/components/soc/esp32c6/register/soc/trace_reg.h
new file mode 100644
index 00000000000..b363fbd1f8e
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/trace_reg.h
@@ -0,0 +1,219 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TRACE_MEM_START_ADDR_REG register
+ *  mem start addr
+ */
+#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
+/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of trace memory
+ */
+#define TRACE_MEM_STAET_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_STAET_ADDR_M  (TRACE_MEM_STAET_ADDR_V << TRACE_MEM_STAET_ADDR_S)
+#define TRACE_MEM_STAET_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_STAET_ADDR_S  0
+
+/** TRACE_MEM_END_ADDR_REG register
+ *  mem end addr
+ */
+#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
+/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The end address of trace memory
+ */
+#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
+#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_S  0
+
+/** TRACE_MEM_CURRENT_ADDR_REG register
+ *  mem current addr
+ */
+#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
+/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  current_mem_addr,indicate that next writing addr
+ */
+#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
+#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_S  0
+
+/** TRACE_MEM_ADDR_UPDATE_REG register
+ *  mem addr update
+ */
+#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
+/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  when set this reg, the current_mem_addr will update to start_addr
+ */
+#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
+
+/** TRACE_FIFO_STATUS_REG register
+ *  fifo status register
+ */
+#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
+/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  1 indicate that fifo is empty
+ */
+#define TRACE_FIFO_EMPTY    (BIT(0))
+#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
+#define TRACE_FIFO_EMPTY_V  0x00000001U
+#define TRACE_FIFO_EMPTY_S  0
+/** TRACE_WORK_STATUS : RO; bitpos: [1]; default: 0;
+ *  mem_full interrupt status
+ */
+#define TRACE_WORK_STATUS    (BIT(1))
+#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
+#define TRACE_WORK_STATUS_V  0x00000001U
+#define TRACE_WORK_STATUS_S  1
+
+/** TRACE_INTR_ENA_REG register
+ *  interrupt enable register
+ */
+#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
+/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set 1 enable fifo_overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
+/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set 1 enable mem_full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
+#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
+#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_ENA_S  1
+
+/** TRACE_INTR_RAW_REG register
+ *  interrupt status register
+ */
+#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
+/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
+ *  fifo_overflow interrupt status
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
+/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
+ *  mem_full interrupt status
+ */
+#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
+#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
+#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_RAW_S  1
+
+/** TRACE_INTR_CLR_REG register
+ *  interrupt clear register
+ */
+#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
+/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
+ *  Set 1 clr fifo overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
+/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
+ *  Set 1 clr mem full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
+#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
+#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_CLR_S  1
+
+/** TRACE_TRIGGER_REG register
+ *  trigger register
+ */
+#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
+/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
+ *  [0] set 1 start trace.
+ */
+#define TRACE_TRIGGER_ON    (BIT(0))
+#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
+#define TRACE_TRIGGER_ON_V  0x00000001U
+#define TRACE_TRIGGER_ON_S  0
+/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
+ *  set 1 stop trace.
+ */
+#define TRACE_TRIGGER_OFF    (BIT(1))
+#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
+#define TRACE_TRIGGER_OFF_V  0x00000001U
+#define TRACE_TRIGGER_OFF_S  1
+/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
+ *  if this reg is 1, trace will loop write trace_mem.  If is 0, when mem_current_addr
+ *  at mem_end_addr, it will stop at the mem_end_addr
+ */
+#define TRACE_MEM_LOOP    (BIT(2))
+#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
+#define TRACE_MEM_LOOP_V  0x00000001U
+#define TRACE_MEM_LOOP_S  2
+/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
+ *  enable encoder auto-restart, when lost package, the encoder will end, if enable
+ *  auto-restart, when fifo empty, encoder will restart and send a sync package.
+ */
+#define TRACE_RESTART_ENA    (BIT(3))
+#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
+#define TRACE_RESTART_ENA_V  0x00000001U
+#define TRACE_RESTART_ENA_S  3
+
+/** TRACE_RESYNC_PROLONGED_REG register
+ *  resync configuration register
+ */
+#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24)
+/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
+ *  count number, when count to this value, send a sync package
+ */
+#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
+#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_S  0
+/** TRACE_RESYNC_MODE : R/W; bitpos: [24]; default: 0;
+ *  resyc mode sel: 0: default, cycle count   1: package num count
+ */
+#define TRACE_RESYNC_MODE    (BIT(24))
+#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
+#define TRACE_RESYNC_MODE_V  0x00000001U
+#define TRACE_RESYNC_MODE_S  24
+
+/** TRACE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x28)
+/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define TRACE_CLK_EN    (BIT(0))
+#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
+#define TRACE_CLK_EN_V  0x00000001U
+#define TRACE_CLK_EN_S  0
+
+/** TRACE_DATE_REG register
+ *  Version control register
+ */
+#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
+/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35663920;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define TRACE_DATE    0x0FFFFFFFU
+#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
+#define TRACE_DATE_V  0x0FFFFFFFU
+#define TRACE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/trace_struct.h b/components/soc/esp32c6/register/soc/trace_struct.h
new file mode 100644
index 00000000000..e5bb04d46d5
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/trace_struct.h
@@ -0,0 +1,249 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Trace memory configuration registers */
+/** Type of mem_start_addr register
+ *  mem start addr
+ */
+typedef union {
+    struct {
+        /** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of trace memory
+         */
+        uint32_t mem_start_addr:32;
+    };
+    uint32_t val;
+} trace_mem_start_addr_reg_t;
+
+/** Type of mem_end_addr register
+ *  mem end addr
+ */
+typedef union {
+    struct {
+        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of trace memory
+         */
+        uint32_t mem_end_addr:32;
+    };
+    uint32_t val;
+} trace_mem_end_addr_reg_t;
+
+/** Type of mem_current_addr register
+ *  mem current addr
+ */
+typedef union {
+    struct {
+        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  current_mem_addr,indicate that next writing addr
+         */
+        uint32_t mem_current_addr:32;
+    };
+    uint32_t val;
+} trace_mem_current_addr_reg_t;
+
+/** Type of mem_addr_update register
+ *  mem addr update
+ */
+typedef union {
+    struct {
+        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
+         *  when set this reg, the current_mem_addr will update to start_addr
+         */
+        uint32_t mem_current_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_mem_addr_update_reg_t;
+
+
+/** Group: Trace fifo status register */
+/** Type of fifo_status register
+ *  fifo status register
+ */
+typedef union {
+    struct {
+        /** fifo_empty : RO; bitpos: [0]; default: 1;
+         *  1 indicate that fifo is empty
+         */
+        uint32_t fifo_empty:1;
+        /** work_status : RO; bitpos: [1]; default: 0;
+         *  mem_full interrupt status
+         */
+        uint32_t work_status:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_fifo_status_reg_t;
+
+
+/** Group: Trace interrupt configuration registers */
+/** Type of intr_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Set 1 enable fifo_overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_ena:1;
+        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Set 1 enable mem_full interrupt
+         */
+        uint32_t mem_full_intr_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_ena_reg_t;
+
+/** Type of intr_raw register
+ *  interrupt status register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
+         *  fifo_overflow interrupt status
+         */
+        uint32_t fifo_overflow_intr_raw:1;
+        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
+         *  mem_full interrupt status
+         */
+        uint32_t mem_full_intr_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_raw_reg_t;
+
+/** Type of intr_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
+         *  Set 1 clr fifo overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_clr:1;
+        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
+         *  Set 1 clr mem full interrupt
+         */
+        uint32_t mem_full_intr_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_clr_reg_t;
+
+
+/** Group: Trace configuration register */
+/** Type of trigger register
+ *  trigger register
+ */
+typedef union {
+    struct {
+        /** trigger_on : WT; bitpos: [0]; default: 0;
+         *  [0] set 1 start trace.
+         */
+        uint32_t trigger_on:1;
+        /** trigger_off : WT; bitpos: [1]; default: 0;
+         *  set 1 stop trace.
+         */
+        uint32_t trigger_off:1;
+        /** mem_loop : R/W; bitpos: [2]; default: 1;
+         *  if this reg is 1, trace will loop write trace_mem.  If is 0, when mem_current_addr
+         *  at mem_end_addr, it will stop at the mem_end_addr
+         */
+        uint32_t mem_loop:1;
+        /** restart_ena : R/W; bitpos: [3]; default: 1;
+         *  enable encoder auto-restart, when lost package, the encoder will end, if enable
+         *  auto-restart, when fifo empty, encoder will restart and send a sync package.
+         */
+        uint32_t restart_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} trace_trigger_reg_t;
+
+/** Type of resync_prolonged register
+ *  resync configuration register
+ */
+typedef union {
+    struct {
+        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
+         *  count number, when count to this value, send a sync package
+         */
+        uint32_t resync_prolonged:24;
+        /** resync_mode : R/W; bitpos: [24]; default: 0;
+         *  resyc mode sel: 0: default, cycle count   1: package num count
+         */
+        uint32_t resync_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} trace_resync_prolonged_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35663920;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} trace_date_reg_t;
+
+
+typedef struct trace_dev_t {
+    volatile trace_mem_start_addr_reg_t mem_start_addr;
+    volatile trace_mem_end_addr_reg_t mem_end_addr;
+    volatile trace_mem_current_addr_reg_t mem_current_addr;
+    volatile trace_mem_addr_update_reg_t mem_addr_update;
+    volatile trace_fifo_status_reg_t fifo_status;
+    volatile trace_intr_ena_reg_t intr_ena;
+    volatile trace_intr_raw_reg_t intr_raw;
+    volatile trace_intr_clr_reg_t intr_clr;
+    volatile trace_trigger_reg_t trigger;
+    volatile trace_resync_prolonged_reg_t resync_prolonged;
+    volatile trace_clock_gate_reg_t clock_gate;
+    uint32_t reserved_02c[244];
+    volatile trace_date_reg_t date;
+} trace_dev_t;
+
+extern trace_dev_t TRACE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/twai_reg.h b/components/soc/esp32c6/register/soc/twai_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/twai_reg.h
rename to components/soc/esp32c6/register/soc/twai_reg.h
diff --git a/components/soc/esp32c6/include/soc/twai_struct.h b/components/soc/esp32c6/register/soc/twai_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/twai_struct.h
rename to components/soc/esp32c6/register/soc/twai_struct.h
diff --git a/components/soc/esp32c6/register/soc/uart_reg.h b/components/soc/esp32c6/register/soc/uart_reg.h
new file mode 100644
index 00000000000..d85004fcc1d
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/uart_reg.h
@@ -0,0 +1,1546 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define UART_RXFIFO_RD_BYTE    0x000000FFU
+#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define UART_RXFIFO_RD_BYTE_S  0
+
+/** UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
+#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
+#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_PARITY_ERR_INT_RAW_S  2
+/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
+#define UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_FRM_ERR_INT_RAW_S  3
+/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
+#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
+#define UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define UART_DSR_CHG_INT_RAW_S  5
+/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
+#define UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define UART_CTS_CHG_INT_RAW_S  6
+/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
+#define UART_BRK_DET_INT_RAW_V  0x00000001U
+#define UART_BRK_DET_INT_RAW_S  7
+/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
+#define UART_SW_XON_INT_RAW_V  0x00000001U
+#define UART_SW_XON_INT_RAW_S  9
+/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
+#define UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define UART_SW_XOFF_INT_RAW_S  10
+/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
+#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define UART_GLITCH_DET_INT_RAW_S  11
+/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
+#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
+#define UART_TX_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_DONE_INT_RAW_S  14
+/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  This interrupt raw bit turns to high level when detects a clash between transmitter
+ *  and receiver in rs485 mode.
+ */
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
+#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
+#define UART_RS485_CLASH_INT_RAW_S  17
+/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
+#define UART_WAKEUP_INT_RAW_V  0x00000001U
+#define UART_WAKEUP_INT_RAW_S  19
+
+/** UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
+/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
+#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ST_S  0
+/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
+#define UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_PARITY_ERR_INT_ST_S  2
+/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
+#define UART_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_FRM_ERR_INT_ST_S  3
+/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
+#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
+#define UART_DSR_CHG_INT_ST_V  0x00000001U
+#define UART_DSR_CHG_INT_ST_S  5
+/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
+#define UART_CTS_CHG_INT_ST_V  0x00000001U
+#define UART_CTS_CHG_INT_ST_S  6
+/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
+#define UART_BRK_DET_INT_ST_V  0x00000001U
+#define UART_BRK_DET_INT_ST_S  7
+/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
+#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
+#define UART_SW_XON_INT_ST_V  0x00000001U
+#define UART_SW_XON_INT_ST_S  9
+/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
+#define UART_SW_XOFF_INT_ST_V  0x00000001U
+#define UART_SW_XOFF_INT_ST_S  10
+/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
+#define UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define UART_GLITCH_DET_INT_ST_S  11
+/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
+#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
+#define UART_TX_DONE_INT_ST_V  0x00000001U
+#define UART_TX_DONE_INT_ST_S  14
+/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ *  set to 1.
+ */
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+ *  to 1.
+ */
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
+#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
+ *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+ */
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
+#define UART_RS485_CLASH_INT_ST_V  0x00000001U
+#define UART_RS485_CLASH_INT_ST_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
+#define UART_WAKEUP_INT_ST_V  0x00000001U
+#define UART_WAKEUP_INT_ST_S  19
+
+/** UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
+/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
+#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
+#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_PARITY_ERR_INT_ENA_S  2
+/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
+#define UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_FRM_ERR_INT_ENA_S  3
+/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
+#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
+#define UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define UART_DSR_CHG_INT_ENA_S  5
+/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
+#define UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define UART_CTS_CHG_INT_ENA_S  6
+/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
+#define UART_BRK_DET_INT_ENA_V  0x00000001U
+#define UART_BRK_DET_INT_ENA_S  7
+/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
+#define UART_SW_XON_INT_ENA_V  0x00000001U
+#define UART_SW_XON_INT_ENA_S  9
+/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
+#define UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define UART_SW_XOFF_INT_ENA_S  10
+/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
+#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define UART_GLITCH_DET_INT_ENA_S  11
+/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
+#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
+#define UART_TX_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_DONE_INT_ENA_S  14
+/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  This is the enable bit for rs485_clash_int_st register.
+ */
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
+#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
+#define UART_RS485_CLASH_INT_ENA_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
+#define UART_WAKEUP_INT_ENA_V  0x00000001U
+#define UART_WAKEUP_INT_ENA_S  19
+
+/** UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
+/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
+#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
+#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_PARITY_ERR_INT_CLR_S  2
+/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
+#define UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_FRM_ERR_INT_CLR_S  3
+/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
+#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
+#define UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define UART_DSR_CHG_INT_CLR_S  5
+/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
+#define UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define UART_CTS_CHG_INT_CLR_S  6
+/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
+#define UART_BRK_DET_INT_CLR_V  0x00000001U
+#define UART_BRK_DET_INT_CLR_S  7
+/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
+#define UART_SW_XON_INT_CLR_V  0x00000001U
+#define UART_SW_XON_INT_CLR_S  9
+/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
+#define UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define UART_SW_XOFF_INT_CLR_S  10
+/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
+#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define UART_GLITCH_DET_INT_CLR_S  11
+/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
+#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
+#define UART_TX_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_DONE_INT_CLR_S  14
+/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+ */
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+ */
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the rs485_clash_int_raw interrupt.
+ */
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
+#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
+#define UART_RS485_CLASH_INT_CLR_S  17
+/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
+#define UART_WAKEUP_INT_CLR_V  0x00000001U
+#define UART_WAKEUP_INT_CLR_S  19
+
+/** UART_CLKDIV_SYNC_REG register
+ *  Clock divider configuration
+ */
+#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
+/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_CLKDIV    0x00000FFFU
+#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
+#define UART_CLKDIV_V  0x00000FFFU
+#define UART_CLKDIV_S  0
+/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define UART_CLKDIV_FRAG    0x0000000FU
+#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
+#define UART_CLKDIV_FRAG_V  0x0000000FU
+#define UART_CLKDIV_FRAG_S  20
+
+/** UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
+/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define UART_GLITCH_FILT    0x000000FFU
+#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
+#define UART_GLITCH_FILT_V  0x000000FFU
+#define UART_GLITCH_FILT_S  0
+/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
+#define UART_GLITCH_FILT_EN_V  0x00000001U
+#define UART_GLITCH_FILT_EN_S  8
+
+/** UART_STATUS_REG register
+ *  UART status register
+ */
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
+/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define UART_RXFIFO_CNT    0x000000FFU
+#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
+#define UART_RXFIFO_CNT_V  0x000000FFU
+#define UART_RXFIFO_CNT_S  0
+/** UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
+#define UART_DSRN_V  0x00000001U
+#define UART_DSRN_S  13
+/** UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
+#define UART_CTSN_V  0x00000001U
+#define UART_CTSN_S  14
+/** UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
+#define UART_RXD_V  0x00000001U
+#define UART_RXD_S  15
+/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define UART_TXFIFO_CNT    0x000000FFU
+#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
+#define UART_TXFIFO_CNT_V  0x000000FFU
+#define UART_TXFIFO_CNT_S  16
+/** UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
+#define UART_DTRN_V  0x00000001U
+#define UART_DTRN_S  29
+/** UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
+#define UART_RTSN_V  0x00000001U
+#define UART_RTSN_S  30
+/** UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
+#define UART_TXD_V  0x00000001U
+#define UART_TXD_S  31
+
+/** UART_CONF0_SYNC_REG register
+ *  a
+ */
+#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
+/** UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
+#define UART_PARITY_V  0x00000001U
+#define UART_PARITY_S  0
+/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
+#define UART_PARITY_EN_V  0x00000001U
+#define UART_PARITY_EN_S  1
+/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define UART_BIT_NUM    0x00000003U
+#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
+#define UART_BIT_NUM_V  0x00000003U
+#define UART_BIT_NUM_S  2
+/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define UART_STOP_BIT_NUM    0x00000003U
+#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
+#define UART_STOP_BIT_NUM_V  0x00000003U
+#define UART_STOP_BIT_NUM_S  4
+/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define UART_TXD_BRK    (BIT(6))
+#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
+#define UART_TXD_BRK_V  0x00000001U
+#define UART_TXD_BRK_S  6
+/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable IrDA loopback mode.
+ */
+#define UART_IRDA_DPLX    (BIT(7))
+#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
+#define UART_IRDA_DPLX_V  0x00000001U
+#define UART_IRDA_DPLX_S  7
+/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the start enable bit for IrDA transmitter.
+ */
+#define UART_IRDA_TX_EN    (BIT(8))
+#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
+#define UART_IRDA_TX_EN_V  0x00000001U
+#define UART_IRDA_TX_EN_S  8
+/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
+ *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+ *  transmitter's 11th bit to 0.
+ */
+#define UART_IRDA_WCTL    (BIT(9))
+#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
+#define UART_IRDA_WCTL_V  0x00000001U
+#define UART_IRDA_WCTL_S  9
+/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to invert the level of  IrDA transmitter.
+ */
+#define UART_IRDA_TX_INV    (BIT(10))
+#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
+#define UART_IRDA_TX_INV_V  0x00000001U
+#define UART_IRDA_TX_INV_S  10
+/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to invert the level of IrDA receiver.
+ */
+#define UART_IRDA_RX_INV    (BIT(11))
+#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
+#define UART_IRDA_RX_INV_V  0x00000001U
+#define UART_IRDA_RX_INV_S  11
+/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define UART_LOOPBACK    (BIT(12))
+#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
+#define UART_LOOPBACK_V  0x00000001U
+#define UART_LOOPBACK_S  12
+/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define UART_TX_FLOW_EN    (BIT(13))
+#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
+#define UART_TX_FLOW_EN_V  0x00000001U
+#define UART_TX_FLOW_EN_S  13
+/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable IrDA protocol.
+ */
+#define UART_IRDA_EN    (BIT(14))
+#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
+#define UART_IRDA_EN_V  0x00000001U
+#define UART_IRDA_EN_S  14
+/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define UART_RXD_INV    (BIT(15))
+#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
+#define UART_RXD_INV_V  0x00000001U
+#define UART_RXD_INV_S  15
+/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define UART_TXD_INV    (BIT(16))
+#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
+#define UART_TXD_INV_V  0x00000001U
+#define UART_TXD_INV_S  16
+/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define UART_DIS_RX_DAT_OVF    (BIT(17))
+#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
+#define UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define UART_DIS_RX_DAT_OVF_S  17
+/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define UART_ERR_WR_MASK    (BIT(18))
+#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
+#define UART_ERR_WR_MASK_V  0x00000001U
+#define UART_ERR_WR_MASK_S  18
+/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for detecting baudrate.
+ */
+#define UART_AUTOBAUD_EN    (BIT(19))
+#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
+#define UART_AUTOBAUD_EN_V  0x00000001U
+#define UART_AUTOBAUD_EN_S  19
+/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  UART memory clock gate enable signal.
+ */
+#define UART_MEM_CLK_EN    (BIT(20))
+#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
+#define UART_MEM_CLK_EN_V  0x00000001U
+#define UART_MEM_CLK_EN_S  20
+/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_RTS    (BIT(21))
+#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
+#define UART_SW_RTS_V  0x00000001U
+#define UART_SW_RTS_S  21
+/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define UART_RXFIFO_RST    (BIT(22))
+#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
+#define UART_RXFIFO_RST_V  0x00000001U
+#define UART_RXFIFO_RST_S  22
+/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define UART_TXFIFO_RST    (BIT(23))
+#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
+#define UART_TXFIFO_RST_V  0x00000001U
+#define UART_TXFIFO_RST_S  23
+
+/** UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
+/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define UART_RXFIFO_FULL_THRHD    0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
+#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
+#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_S  8
+/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define UART_CTS_INV    (BIT(16))
+#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
+#define UART_CTS_INV_V  0x00000001U
+#define UART_CTS_INV_S  16
+/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define UART_DSR_INV    (BIT(17))
+#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
+#define UART_DSR_INV_V  0x00000001U
+#define UART_DSR_INV_S  17
+/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define UART_RTS_INV    (BIT(18))
+#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
+#define UART_RTS_INV_V  0x00000001U
+#define UART_RTS_INV_S  18
+/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define UART_DTR_INV    (BIT(19))
+#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
+#define UART_DTR_INV_V  0x00000001U
+#define UART_DTR_INV_S  19
+/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_DTR    (BIT(20))
+#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
+#define UART_SW_DTR_V  0x00000001U
+#define UART_SW_DTR_S  20
+/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define UART_CLK_EN    (BIT(21))
+#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
+#define UART_CLK_EN_V  0x00000001U
+#define UART_CLK_EN_S  21
+
+/** UART_HWFC_CONF_SYNC_REG register
+ *  Hardware flow-control configuration
+ */
+#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
+/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define UART_RX_FLOW_THRHD    0x000000FFU
+#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
+#define UART_RX_FLOW_THRHD_V  0x000000FFU
+#define UART_RX_FLOW_THRHD_S  0
+/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define UART_RX_FLOW_EN    (BIT(8))
+#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
+#define UART_RX_FLOW_EN_V  0x00000001U
+#define UART_RX_FLOW_EN_S  8
+
+/** UART_SLEEP_CONF0_REG register
+ *  UART sleep configure register 0
+ */
+#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
+/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define UART_WK_CHAR1    0x000000FFU
+#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
+#define UART_WK_CHAR1_V  0x000000FFU
+#define UART_WK_CHAR1_S  0
+/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define UART_WK_CHAR2    0x000000FFU
+#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
+#define UART_WK_CHAR2_V  0x000000FFU
+#define UART_WK_CHAR2_S  8
+/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define UART_WK_CHAR3    0x000000FFU
+#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
+#define UART_WK_CHAR3_V  0x000000FFU
+#define UART_WK_CHAR3_S  16
+/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define UART_WK_CHAR4    0x000000FFU
+#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
+#define UART_WK_CHAR4_V  0x000000FFU
+#define UART_WK_CHAR4_S  24
+
+/** UART_SLEEP_CONF1_REG register
+ *  UART sleep configure register 1
+ */
+#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
+/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define UART_WK_CHAR0    0x000000FFU
+#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
+#define UART_WK_CHAR0_V  0x000000FFU
+#define UART_WK_CHAR0_S  0
+
+/** UART_SLEEP_CONF2_REG register
+ *  UART sleep configure register 2
+ */
+#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
+/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define UART_ACTIVE_THRESHOLD    0x000003FFU
+#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
+#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define UART_ACTIVE_THRESHOLD_S  0
+/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define UART_RX_WAKE_UP_THRHD    0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
+#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_S  10
+/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define UART_WK_CHAR_NUM    0x00000007U
+#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
+#define UART_WK_CHAR_NUM_V  0x00000007U
+#define UART_WK_CHAR_NUM_S  18
+/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define UART_WK_CHAR_MASK    0x0000001FU
+#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
+#define UART_WK_CHAR_MASK_V  0x0000001FU
+#define UART_WK_CHAR_MASK_S  21
+/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define UART_WK_MODE_SEL    0x00000003U
+#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
+#define UART_WK_MODE_SEL_V  0x00000003U
+#define UART_WK_MODE_SEL_S  26
+
+/** UART_SWFC_CONF0_SYNC_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
+/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define UART_XON_CHAR    0x000000FFU
+#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
+#define UART_XON_CHAR_V  0x000000FFU
+#define UART_XON_CHAR_S  0
+/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define UART_XOFF_CHAR    0x000000FFU
+#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
+#define UART_XOFF_CHAR_V  0x000000FFU
+#define UART_XOFF_CHAR_S  8
+/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
+#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define UART_XON_XOFF_STILL_SEND_S  16
+/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define UART_SW_FLOW_CON_EN    (BIT(17))
+#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
+#define UART_SW_FLOW_CON_EN_V  0x00000001U
+#define UART_SW_FLOW_CON_EN_S  17
+/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define UART_XONOFF_DEL    (BIT(18))
+#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
+#define UART_XONOFF_DEL_V  0x00000001U
+#define UART_XONOFF_DEL_S  18
+/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define UART_FORCE_XON    (BIT(19))
+#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
+#define UART_FORCE_XON_V  0x00000001U
+#define UART_FORCE_XON_S  19
+/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define UART_FORCE_XOFF    (BIT(20))
+#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
+#define UART_FORCE_XOFF_V  0x00000001U
+#define UART_FORCE_XOFF_S  20
+/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XON    (BIT(21))
+#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
+#define UART_SEND_XON_V  0x00000001U
+#define UART_SEND_XON_S  21
+/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XOFF    (BIT(22))
+#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
+#define UART_SEND_XOFF_V  0x00000001U
+#define UART_SEND_XOFF_S  22
+
+/** UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
+/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define UART_XON_THRESHOLD    0x000000FFU
+#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
+#define UART_XON_THRESHOLD_V  0x000000FFU
+#define UART_XON_THRESHOLD_S  0
+/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define UART_XOFF_THRESHOLD    0x000000FFU
+#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
+#define UART_XOFF_THRESHOLD_V  0x000000FFU
+#define UART_XOFF_THRESHOLD_S  8
+
+/** UART_TXBRK_CONF_SYNC_REG register
+ *  Tx Break character configuration
+ */
+#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
+/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define UART_TX_BRK_NUM    0x000000FFU
+#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
+#define UART_TX_BRK_NUM_V  0x000000FFU
+#define UART_TX_BRK_NUM_S  0
+
+/** UART_IDLE_CONF_SYNC_REG register
+ *  Frame-end idle configuration
+ */
+#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
+/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define UART_RX_IDLE_THRHD    0x000003FFU
+#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
+#define UART_RX_IDLE_THRHD_V  0x000003FFU
+#define UART_RX_IDLE_THRHD_S  0
+/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define UART_TX_IDLE_NUM    0x000003FFU
+#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
+#define UART_TX_IDLE_NUM_V  0x000003FFU
+#define UART_TX_IDLE_NUM_S  10
+
+/** UART_RS485_CONF_SYNC_REG register
+ *  RS485 mode configuration
+ */
+#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
+/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to choose the rs485 mode.
+ */
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
+#define UART_RS485_EN_V  0x00000001U
+#define UART_RS485_EN_S  0
+/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
+#define UART_DL0_EN_V  0x00000001U
+#define UART_DL0_EN_S  1
+/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
+#define UART_DL1_EN_V  0x00000001U
+#define UART_DL1_EN_S  2
+/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable receiver could receive data when the transmitter is
+ *  transmitting data in rs485 mode.
+ */
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
+#define UART_RS485TX_RX_EN_V  0x00000001U
+#define UART_RS485TX_RX_EN_S  3
+/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+ */
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
+#define UART_RS485RXBY_TX_EN_V  0x00000001U
+#define UART_RS485RXBY_TX_EN_S  4
+/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
+ *  This register is used to delay the receiver's internal data signal.
+ */
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
+#define UART_RS485_RX_DLY_NUM_V  0x00000001U
+#define UART_RS485_RX_DLY_NUM_S  5
+/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
+ *  This register is used to delay the transmitter's internal data signal.
+ */
+#define UART_RS485_TX_DLY_NUM    0x0000000FU
+#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
+#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
+#define UART_RS485_TX_DLY_NUM_S  6
+
+/** UART_AT_CMD_PRECNT_SYNC_REG register
+ *  Pre-sequence timing configuration
+ */
+#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
+/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define UART_PRE_IDLE_NUM    0x0000FFFFU
+#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
+#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define UART_PRE_IDLE_NUM_S  0
+
+/** UART_AT_CMD_POSTCNT_SYNC_REG register
+ *  Post-sequence timing configuration
+ */
+#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
+/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define UART_POST_IDLE_NUM    0x0000FFFFU
+#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
+#define UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define UART_POST_IDLE_NUM_S  0
+
+/** UART_AT_CMD_GAPTOUT_SYNC_REG register
+ *  Timeout configuration
+ */
+#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
+/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define UART_RX_GAP_TOUT    0x0000FFFFU
+#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
+#define UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define UART_RX_GAP_TOUT_S  0
+
+/** UART_AT_CMD_CHAR_SYNC_REG register
+ *  AT escape sequence detection configuration
+ */
+#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
+/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define UART_AT_CMD_CHAR    0x000000FFU
+#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
+#define UART_AT_CMD_CHAR_V  0x000000FFU
+#define UART_AT_CMD_CHAR_S  0
+/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define UART_CHAR_NUM    0x000000FFU
+#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
+#define UART_CHAR_NUM_V  0x000000FFU
+#define UART_CHAR_NUM_S  8
+
+/** UART_MEM_CONF_REG register
+ *  UART memory power configuration
+ */
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
+/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define UART_MEM_FORCE_PD    (BIT(25))
+#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
+#define UART_MEM_FORCE_PD_V  0x00000001U
+#define UART_MEM_FORCE_PD_S  25
+/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define UART_MEM_FORCE_PU    (BIT(26))
+#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
+#define UART_MEM_FORCE_PU_V  0x00000001U
+#define UART_MEM_FORCE_PU_S  26
+
+/** UART_TOUT_CONF_SYNC_REG register
+ *  UART threshold and allocation configuration
+ */
+#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
+/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define UART_RX_TOUT_EN    (BIT(0))
+#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
+#define UART_RX_TOUT_EN_V  0x00000001U
+#define UART_RX_TOUT_EN_S  0
+/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
+#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define UART_RX_TOUT_FLOW_DIS_S  1
+/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define UART_RX_TOUT_THRHD    0x000003FFU
+#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
+#define UART_RX_TOUT_THRHD_V  0x000003FFU
+#define UART_RX_TOUT_THRHD_S  2
+
+/** UART_MEM_TX_STATUS_REG register
+ *  Tx-SRAM write and read offset address.
+ */
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
+/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_WADDR    0x000000FFU
+#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
+#define UART_TX_SRAM_WADDR_V  0x000000FFU
+#define UART_TX_SRAM_WADDR_S  0
+/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_RADDR    0x000000FFU
+#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
+#define UART_TX_SRAM_RADDR_V  0x000000FFU
+#define UART_TX_SRAM_RADDR_S  9
+
+/** UART_MEM_RX_STATUS_REG register
+ *  Rx-SRAM write and read offset address.
+ */
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
+/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define UART_RX_SRAM_RADDR    0x000000FFU
+#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
+#define UART_RX_SRAM_RADDR_V  0x000000FFU
+#define UART_RX_SRAM_RADDR_S  0
+/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define UART_RX_SRAM_WADDR    0x000000FFU
+#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
+#define UART_RX_SRAM_WADDR_V  0x000000FFU
+#define UART_RX_SRAM_WADDR_S  9
+
+/** UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
+/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define UART_ST_URX_OUT    0x0000000FU
+#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
+#define UART_ST_URX_OUT_V  0x0000000FU
+#define UART_ST_URX_OUT_S  0
+/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define UART_ST_UTX_OUT    0x0000000FU
+#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
+#define UART_ST_UTX_OUT_V  0x0000000FU
+#define UART_ST_UTX_OUT_S  4
+
+/** UART_POSPULSE_REG register
+ *  Autobaud high pulse register
+ */
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
+/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two positive edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_POSEDGE_MIN_CNT    0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
+#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_S  0
+
+/** UART_NEGPULSE_REG register
+ *  Autobaud low pulse register
+ */
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
+/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two negative edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
+#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+/** UART_LOWPULSE_REG register
+ *  Autobaud minimum low pulse duration register
+ */
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
+/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the value of the minimum duration time of the low level pulse.
+ *  It is used in baud rate-detect process.
+ */
+#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
+#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+/** UART_HIGHPULSE_REG register
+ *  Autobaud minimum high pulse duration register
+ */
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
+/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores  the value of the maximum duration time for the high level
+ *  pulse. It is used in baud rate-detect process.
+ */
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
+#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+/** UART_RXD_CNT_REG register
+ *  Autobaud edge change count register
+ */
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
+/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the count of rxd edge change. It is used in baud rate-detect
+ *  process.
+ */
+#define UART_RXD_EDGE_CNT    0x000003FFU
+#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
+#define UART_RXD_EDGE_CNT_V  0x000003FFU
+#define UART_RXD_EDGE_CNT_S  0
+
+/** UART_DATE_REG register
+ *  UART Version register
+ */
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
+/** UART_DATE : R/W; bitpos: [31:0]; default: 35656288;
+ *  This is the version register.
+ */
+#define UART_DATE    0xFFFFFFFFU
+#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
+#define UART_DATE_V  0xFFFFFFFFU
+#define UART_DATE_S  0
+
+/** UART_AFIFO_STATUS_REG register
+ *  UART AFIFO Status
+ */
+#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
+/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_FULL    (BIT(0))
+#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
+#define UART_TX_AFIFO_FULL_V  0x00000001U
+#define UART_TX_AFIFO_FULL_S  0
+/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_EMPTY    (BIT(1))
+#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
+#define UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define UART_TX_AFIFO_EMPTY_S  1
+/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_FULL    (BIT(2))
+#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
+#define UART_RX_AFIFO_FULL_V  0x00000001U
+#define UART_RX_AFIFO_FULL_S  2
+/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_EMPTY    (BIT(3))
+#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
+#define UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define UART_RX_AFIFO_EMPTY_S  3
+
+/** UART_REG_UPDATE_REG register
+ *  UART Registers Configuration Update register
+ */
+#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
+/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define UART_REG_UPDATE    (BIT(0))
+#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
+#define UART_REG_UPDATE_V  0x00000001U
+#define UART_REG_UPDATE_S  0
+
+/** UART_ID_REG register
+ *  UART ID register
+ */
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
+/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define UART_ID    0xFFFFFFFFU
+#define UART_ID_M  (UART_ID_V << UART_ID_S)
+#define UART_ID_V  0xFFFFFFFFU
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/register/soc/uart_struct.h b/components/soc/esp32c6/register/soc/uart_struct.h
new file mode 100644
index 00000000000..62421c0241d
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/uart_struct.h
@@ -0,0 +1,1294 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:32;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err:1;
+        /** frm_err : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done:1;
+        /** rs485_parity_err : R/WTC/SS; bitpos: [15]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_parity_err:1;
+        /** rs485_frm_err : R/WTC/SS; bitpos: [16]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_frm_err:1;
+        /** rs485_clash : R/WTC/SS; bitpos: [17]; default: 0;
+         *  This interrupt raw bit turns to high level when detects a clash between transmitter
+         *  and receiver in rs485 mode.
+         */
+        uint32_t rs485_clash:1;
+        /** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err:1;
+        /** frm_err : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done:1;
+        /** rs485_parity_err : RO; bitpos: [15]; default: 0;
+         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+         *  set to 1.
+         */
+        uint32_t rs485_parity_err:1;
+        /** rs485_frm_err : RO; bitpos: [16]; default: 0;
+         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+         *  to 1.
+         */
+        uint32_t rs485_frm_err:1;
+        /** rs485_clash : RO; bitpos: [17]; default: 0;
+         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+         */
+        uint32_t rs485_clash:1;
+        /** at_cmd_char_det : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full: R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty: R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err: R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err:1;
+        /** frm_err: R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf: R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg: R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg: R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det: R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout: R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon: R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff: R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det: R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done: R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done: R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done: R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done:1;
+        /** rs485_parity_err: R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_parity_err:1;
+        /** rs485_frm_err: R/W; bitpos: [16]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_frm_err:1;
+        /** rs485_clash: R/W; bitpos: [17]; default: 0;
+         *  This is the enable bit for rs485_clash_int_st register.
+         */
+        uint32_t rs485_clash:1;
+        /** at_cmd_char_det: R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup: R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full: WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty: WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err: WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err:1;
+        /** frm_err: WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf: WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg: WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg: WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det: WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout: WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon: WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff: WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det: WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done: WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done: WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done: WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done:1;
+        /** rs485_parity_err: WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+         */
+        uint32_t rs485_parity_err:1;
+        /** rs485_frm_err: WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+         */
+        uint32_t rs485_frm_err:1;
+        /** rs485_clash: WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the rs485_clash_int_raw interrupt.
+         */
+        uint32_t rs485_clash:1;
+        /** at_cmd_char_det: WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup: WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv_int:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  a
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable IrDA loopback mode.
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
+         *  This is the start enable bit for IrDA transmitter.
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [9]; default: 0;
+         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+         *  transmitter's 11th bit to 0.
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the level of  IrDA transmitter.
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to invert the level of IrDA receiver.
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable IrDA protocol.
+         */
+        uint32_t irda_en:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for detecting baudrate.
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 1;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:8;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:8;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:8;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:8;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_character : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_character:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_threshold:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to choose the rs485 mode.
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable receiver could receive data when the transmitter is
+         *  transmitting data in rs485 mode.
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  This register is used to delay the receiver's internal data signal.
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  This register is used to delay the transmitter's internal data signal.
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t sclk_div_num:8;
+        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  UART clock source select. 1: 80Mhz.  2: 8Mhz.  3: XTAL.
+         */
+        uint32_t sclk_sel:2;
+        /** sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set this bit to enable UART Tx/Rx clock.
+         */
+        uint32_t sclk_en:1;
+        /** rst_core : R/W; bitpos: [23]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx/Rx.
+         */
+        uint32_t rst_core:1;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:8;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:8;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:8;
+        uint32_t reserved_8:1;
+        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:8;
+        uint32_t reserved_8:1;
+        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** data : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t data:8;
+        /** at_char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t at_char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two positive edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two negative edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the value of the minimum duration time of the low level pulse.
+         *  It is used in baud rate-detect process.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores  the value of the maximum duration time for the high level
+         *  pulse. It is used in baud rate-detect process.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the count of rxd edge change. It is used in baud rate-detect
+         *  process.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35656288;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct uart_dev_s {
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_sync_reg_t conf0_sync;
+    volatile uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile uart_sleep_conf0_reg_t sleep_conf0;
+    volatile uart_sleep_conf1_reg_t sleep_conf1;
+    volatile uart_sleep_conf2_reg_t sleep_conf2;
+    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;      /* LP_UART instance has this register reserved */
+    volatile uart_negpulse_reg_t negpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_lowpulse_reg_t lowpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_highpulse_reg_t highpulse;    /* LP_UART instance has this register reserved */
+    volatile uart_rxd_cnt_reg_t rxd_cnt;        /* LP_UART instance has this register reserved */
+    volatile uart_clk_conf_reg_t clk_conf;      /* UART0/1 instance have this register reserved, configure in corresponding PCR registers */
+    volatile uart_date_reg_t date;
+    volatile uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile uart_reg_update_reg_t reg_update;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+extern uart_dev_t LP_UART;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/uhci_reg.h b/components/soc/esp32c6/register/soc/uhci_reg.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/uhci_reg.h
rename to components/soc/esp32c6/register/soc/uhci_reg.h
diff --git a/components/soc/esp32c6/include/soc/uhci_struct.h b/components/soc/esp32c6/register/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/uhci_struct.h
rename to components/soc/esp32c6/register/soc/uhci_struct.h
diff --git a/components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h
new file mode 100644
index 00000000000..e188eea9111
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,1188 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
+ *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
+ *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
+ *  how many data is received, then read data from UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
+ *  USB Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFH_S  3
+/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFL_S  5
+/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+ *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+ *  through GPIO Matrix.
+ */
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
+ *  USB RCV value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
+ *  USB D+ rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_SERIAL_JTAG_CHIP_RST_REG register
+ *  CDC-ACM chip reset control.
+ */
+#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
+/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
+ *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_RTS    (BIT(0))
+#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
+#define USB_SERIAL_JTAG_RTS_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_S  0
+/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
+ *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_DTR    (BIT(1))
+#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
+#define USB_SERIAL_JTAG_DTR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_S  1
+/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable chip reset from usb serial channel to reset chip.
+ */
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
+ *  W0 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
+/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
+ *  W1 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
+/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
+/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_S  16
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
+ *  W0 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
+/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
+ *  W1 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
+/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
+/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
+
+/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
+ *  Configuration registers' value update
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
+/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this register would update the value of configure registers from APB
+ *  clock domain to 48MHz clock domain.
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
+
+/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
+ *  Serial AFIFO configure register
+ */
+#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
+ *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
+
+/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
+ *  USB Bus reset status register
+ */
+#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
+/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
+ *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+ *  reset is released.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  Date register
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416;
+ *  register version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c6/register/soc/usb_serial_jtag_struct.h
similarity index 100%
rename from components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h
rename to components/soc/esp32c6/register/soc/usb_serial_jtag_struct.h
diff --git a/components/soc/esp32c6/register/soc/xts_aes_reg.h b/components/soc/esp32c6/register/soc/xts_aes_reg.h
new file mode 100644
index 00000000000..6e7cba263a7
--- /dev/null
+++ b/components/soc/esp32c6/register/soc/xts_aes_reg.h
@@ -0,0 +1,128 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define XTS_AES_PLAIN_MEM(i)          (REG_SPI_MEM_BASE(i) + 0x300)
+/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This field is only used to generate include file in c case. This field is useles
+s. Please do not use this field..*/
+#define XTS_AES_PLAIN    0xFFFFFFFF
+#define XTS_AES_PLAIN_M  ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
+#define XTS_AES_PLAIN_V  0xFFFFFFFF
+#define XTS_AES_PLAIN_S  0
+
+#define XTS_AES_LINESIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x340)
+/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the line-size parameter which will be used in manual encryption
+ calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
+ 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
+#define XTS_AES_LINESIZE    0x00000003
+#define XTS_AES_LINESIZE_M  ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
+#define XTS_AES_LINESIZE_V  0x3
+#define XTS_AES_LINESIZE_S  0
+
+#define XTS_AES_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
+/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit stores the destination parameter which will be used in manual encryption
+n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
+used..*/
+#define XTS_AES_DESTINATION    (BIT(0))
+#define XTS_AES_DESTINATION_M  (BIT(0))
+#define XTS_AES_DESTINATION_V  0x1
+#define XTS_AES_DESTINATION_S  0
+
+#define XTS_AES_PHYSICAL_ADDRESS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x348)
+/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits stores the physical-address parameter which will be used in manual enc
+ryption calculation. This value should aligned with byte number decided by line-
+size parameter..*/
+#define XTS_AES_PHYSICAL_ADDRESS    0x03FFFFFF
+#define XTS_AES_PHYSICAL_ADDRESS_M  ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
+#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFF
+#define XTS_AES_PHYSICAL_ADDRESS_S  0
+
+#define XTS_AES_TRIGGER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34C)
+/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to trigger the process of manual encryption calculation. This actio
+n should only be asserted when manual encryption status is 0. After this action,
+ manual encryption status becomes 1. After calculation is done, manual encryption
+n status becomes 2..*/
+#define XTS_AES_TRIGGER    (BIT(0))
+#define XTS_AES_TRIGGER_M  (BIT(0))
+#define XTS_AES_TRIGGER_V  0x1
+#define XTS_AES_TRIGGER_S  0
+
+#define XTS_AES_RELEASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x350)
+/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to release encrypted result to mspi. This action should only be ass
+erted when manual encryption status is 2. After this action, manual encryption s
+tatus will become 3..*/
+#define XTS_AES_RELEASE    (BIT(0))
+#define XTS_AES_RELEASE_M  (BIT(0))
+#define XTS_AES_RELEASE_V  0x1
+#define XTS_AES_RELEASE_S  0
+
+#define XTS_AES_DESTROY_REG(i)          (REG_SPI_MEM_BASE(i) + 0x354)
+/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
+en manual encryption status is 3. After this action, manual encryption status wi
+ll become 0..*/
+#define XTS_AES_DESTROY    (BIT(0))
+#define XTS_AES_DESTROY_M  (BIT(0))
+#define XTS_AES_DESTROY_V  0x1
+#define XTS_AES_DESTROY_S  0
+
+#define XTS_AES_STATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x358)
+/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+ calculation, 2: encryption calculation is done but the encrypted result is invi
+sible to mspi, 3: the encrypted result is visible to mspi..*/
+#define XTS_AES_STATE    0x00000003
+#define XTS_AES_STATE_M  ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
+#define XTS_AES_STATE_V  0x3
+#define XTS_AES_STATE_S  0
+
+#define XTS_AES_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x35C)
+/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
+/*description: This bits stores the last modified-time of manual encryption feature..*/
+#define XTS_AES_DATE    0x3FFFFFFF
+#define XTS_AES_DATE_M  ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
+#define XTS_AES_DATE_V  0x3FFFFFFF
+
+#define XTS_AES_DPA_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x388)
+/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
+T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V  0x1
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S  4
+/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
+ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
+ing key 1..*/
+#define XTS_AES_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_V  0x1
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_S  3
+/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-
+7: The bigger the number is, the more secure the cryption is. (Note that the per
+formance of cryption will decrease together with this number increasing).*/
+#define XTS_AES_CRYPT_SECURITY_LEVEL    0x00000007
+#define XTS_AES_CRYPT_SECURITY_LEVEL_M  ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
+#define XTS_AES_CRYPT_SECURITY_LEVEL_V  0x7
+#define XTS_AES_CRYPT_SECURITY_LEVEL_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c6/rmt_periph.c b/components/soc/esp32c6/rmt_periph.c
index 7ca8a5ddcbd..c08da463f29 100644
--- a/components/soc/esp32c6/rmt_periph.c
+++ b/components/soc/esp32c6/rmt_periph.c
@@ -60,6 +60,7 @@ static const regdma_entries_config_t rmt_regdma_entries[] = {
 
 const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_RMT0,
         .regdma_entry_array = rmt_regdma_entries,
         .array_size = ARRAY_SIZE(rmt_regdma_entries)
     },
diff --git a/components/soc/esp32c6/spi_periph.c b/components/soc/esp32c6/spi_periph.c
index ea10937f582..1a3696a27fd 100644
--- a/components/soc/esp32c6/spi_periph.c
+++ b/components/soc/esp32c6/spi_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,29 +13,6 @@
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
     {
         // MSPI has dedicated iomux pins
-        .spiclk_out = -1,
-        .spiclk_in = -1,
-        .spid_out = -1,
-        .spiq_out = -1,
-        .spiwp_out = -1,
-        .spihd_out = -1,
-        .spid_in = -1,
-        .spiq_in = -1,
-        .spiwp_in = -1,
-        .spihd_in = -1,
-        .spics_out = {-1},
-        .spics_in = -1,
-        .spiclk_iomux_pin = -1,
-        .spid_iomux_pin = -1,
-        .spiq_iomux_pin = -1,
-        .spiwp_iomux_pin = -1,
-        .spihd_iomux_pin = -1,
-        .spics0_iomux_pin = -1,
-        .irq = -1,
-        .irq_dma = -1,
-        .module = -1,
-        .hw = NULL,
-        .func = -1,
     }, {
         .spiclk_out = FSPICLK_OUT_IDX,
         .spiclk_in = FSPICLK_IN_IDX,
@@ -57,8 +34,51 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
         .irq = ETS_GSPI2_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_SPI2_MODULE,
         .hw = &GPSPI2,
         .func = SPI2_FUNC_NUM,
     }
 };
+
+
+/**
+ * Backup registers in Light sleep: (total cnt 12)
+ *
+ * cmd
+ * addr
+ * ctrl
+ * clock
+ * user
+ * user1
+ * user2
+ * ms_dlen
+ * misc
+ * dma_conf
+ * dma_int_ena
+ * slave
+ */
+#define SPI_RETENTION_REGS_CNT 12
+static const uint32_t spi_regs_map[4] = {0x31ff, 0x1000000, 0x0, 0x0};
+#define SPI_REG_RETENTION_ENTRIES(num) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
+                                               REG_SPI_BASE(num), REG_SPI_BASE(num), \
+                                               SPI_RETENTION_REGS_CNT, 0, 0, \
+                                               spi_regs_map[0], spi_regs_map[1], \
+                                               spi_regs_map[2], spi_regs_map[3]), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+    /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
+                                            SPI_DMA_INT_SET_REG(num), \
+                                            SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET , \
+                                            UINT32_MAX, 1, 0), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2);   // '2' for GPSPI2
+
+const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = {   // '-1' to except mspi
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI2,
+        .entry_array = spi2_regs_retention,
+        .array_size = ARRAY_SIZE(spi2_regs_retention),
+    },
+};
diff --git a/components/soc/esp32c6/temperature_sensor_periph.c b/components/soc/esp32c6/temperature_sensor_periph.c
index f5ad36f5a9f..b1a189fe9b4 100644
--- a/components/soc/esp32c6/temperature_sensor_periph.c
+++ b/components/soc/esp32c6/temperature_sensor_periph.c
@@ -1,10 +1,13 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
+#include "soc/regdma.h"
 #include "soc/temperature_sensor_periph.h"
+#include "soc/apb_saradc_reg.h"
 
 const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
     /*Offset   reg_val  min  max  error */
@@ -14,3 +17,24 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S
     { 1,    11,   -30,   50,   2},
     { 2,    10,   -40,   20,   3},
 };
+
+// Temperature sensor sleep retention entries
+// Temperature sensor registers require set the reg_update bit to make the configuration take effect
+
+/* Temperature sensor Registers Context
+   Include: APB_SARADC_INT_ENA_REG /
+            APB_SARADC_APB_TSENS_CTRL_REG / APB_SARADC_TSENS_CTRL2_REG / APB_TSENS_WAKE_REG / APB_TSENS_SAMPLE_REG
+*/
+#define TEMPERATURE_SENSOR_RETENTION_REGS_CNT  5
+#define TEMPERATURE_SENSOR_RETENTION_MAP_BASE  APB_SARADC_INT_ENA_REG
+static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0};
+static const regdma_entries_config_t temperature_sensor_regs_entries[] = {
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+};
+
+const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = {
+    .link_list = temperature_sensor_regs_entries,
+    .link_num = ARRAY_SIZE(temperature_sensor_regs_entries),
+    .module_id = SLEEP_RETENTION_MODULE_TEMP_SENSOR,
+};
diff --git a/components/soc/esp32c6/twai_periph.c b/components/soc/esp32c6/twai_periph.c
index 712102bf145..3066be7bf8d 100644
--- a/components/soc/esp32c6/twai_periph.c
+++ b/components/soc/esp32c6/twai_periph.c
@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/twai_periph.h"
+#include "soc/twai_reg.h"
 #include "soc/gpio_sig_map.h"
 
 const twai_controller_signal_conn_t twai_controller_periph_signals = {
@@ -29,3 +30,49 @@ const twai_controller_signal_conn_t twai_controller_periph_signals = {
         }
     }
 };
+
+/**
+ * TWAI Registers to be saved during sleep retention
+ * - TWAI_MODE_REG
+ * - TWAI_INTERRUPT_ENABLE_REG
+ * - TWAI_BUS_TIMING_0_REG / TWAI_BUS_TIMING_1_REG
+ * - TWAI_ERR_WARNING_LIMIT_REG
+ * - TWAI_RX_ERR_CNT_REG
+ * - TWAI_TX_ERR_CNT_REG
+ * - TWAI_DATA_x_REG
+ * - TWAI_CLOCK_DIVIDER_REG
+ * - TWAI_SW_STANDBY_CFG_REG
+ * - TWAI_HW_CFG_REG
+ * - TWAI_HW_STANDBY_CNT_REG
+ * - TWAI_IDLE_INTR_CNT_REG
+ * - TWAI_ECO_CFG_REG
+ * - TWAI_TIMESTAMP_PRESCALER_REG
+ * - TWAI_TIMESTAMP_CFG_REG
+*/
+#define TWAI_RETENTION_REGS_CNT 28
+#define TWAI_RETENTION_REGS_BASE(i) REG_TWAI_BASE(i)
+static const uint32_t twai_regs_map[4] = {0x9fffe0d1, 0xdf, 0x0, 0x0};
+#define TWAI_SLEEP_RETENTION_ENTRIES(id) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TWAI_LINK(0x00), \
+                                               TWAI_RETENTION_REGS_BASE(id), TWAI_RETENTION_REGS_BASE(id), \
+                                               TWAI_RETENTION_REGS_CNT, 0, 0, \
+                                               twai_regs_map[0], twai_regs_map[1], \
+                                               twai_regs_map[2], twai_regs_map[3]), \
+                                               .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t twai0_regs_retention[] = TWAI_SLEEP_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t twai1_regs_retention[] = TWAI_SLEEP_RETENTION_ENTRIES(1);
+
+const twai_reg_retention_info_t twai_reg_retention_info[SOC_TWAI_CONTROLLER_NUM] = {
+    [0] = {
+        .module_id = SLEEP_RETENTION_MODULE_TWAI0,
+        .entry_array = twai0_regs_retention,
+        .array_size = ARRAY_SIZE(twai0_regs_retention)
+    },
+    [1] = {
+        .module_id = SLEEP_RETENTION_MODULE_TWAI1,
+        .entry_array = twai1_regs_retention,
+        .array_size = ARRAY_SIZE(twai1_regs_retention)
+    },
+};
diff --git a/components/soc/esp32c6/uart_periph.c b/components/soc/esp32c6/uart_periph.c
index 22c7f99d119..287e394df3b 100644
--- a/components/soc/esp32c6/uart_periph.c
+++ b/components/soc/esp32c6/uart_periph.c
@@ -151,10 +151,12 @@ static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTI
 
 const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_UART0,
         .regdma_entry_array = uart0_regdma_entries,
         .array_size = ARRAY_SIZE(uart0_regdma_entries),
     },
     [1] = {
+        .module = SLEEP_RETENTION_MODULE_UART1,
         .regdma_entry_array = uart1_regdma_entries,
         .array_size = ARRAY_SIZE(uart1_regdma_entries),
     },
diff --git a/components/soc/esp32c61/adc_periph.c b/components/soc/esp32c61/adc_periph.c
new file mode 100644
index 00000000000..a0819f8db12
--- /dev/null
+++ b/components/soc/esp32c61/adc_periph.c
@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/adc_periph.h"
+
+/* Store IO number corresponding to the ADC channel number. */
+const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
+    /* ADC1 */
+    {
+        ADC1_CHANNEL_0_GPIO_NUM,
+        ADC1_CHANNEL_1_GPIO_NUM,
+        ADC1_CHANNEL_2_GPIO_NUM,
+        ADC1_CHANNEL_3_GPIO_NUM,
+    },
+};
diff --git a/components/soc/esp32c61/etm_periph.c b/components/soc/esp32c61/etm_periph.c
new file mode 100644
index 00000000000..7b268c443a5
--- /dev/null
+++ b/components/soc/esp32c61/etm_periph.c
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/etm_periph.h"
+#include "soc/soc_etm_reg.h"
+
+/**
+ * ETM Registers to be saved during sleep retention
+ * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
+*/
+#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
+
+static const regdma_entries_config_t etm_regdma_entries[] = {
+    // backup stage: save the status of enabled channels
+    // restore stage: store the enabled channels
+    [0] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
+        SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    [1] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
+        SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
+        SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+};
+
+const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = {
+    [0] = {
+        .module = SLEEP_RETENTION_MODULE_ETM0,
+        .regdma_entry_array = etm_regdma_entries,
+        .array_size = ARRAY_SIZE(etm_regdma_entries)
+    },
+};
diff --git a/components/soc/esp32c61/gpio_periph.c b/components/soc/esp32c61/gpio_periph.c
index 45ca3280d33..573c99dc07d 100644
--- a/components/soc/esp32c61/gpio_periph.c
+++ b/components/soc/esp32c61/gpio_periph.c
@@ -29,6 +29,9 @@ const uint32_t GPIO_HOLD_MASK[] = {
     BIT(19),         //GPIO19
     BIT(20),         //GPIO20
     BIT(21),         //GPIO21
+    BIT(22),         //GPIO22
+    BIT(23),         //GPIO23
+    BIT(24),         //GPIO24
 };
 
 _Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
diff --git a/components/soc/esp32c61/i2c_periph.c b/components/soc/esp32c61/i2c_periph.c
index cc11ee808f5..f86531948d2 100644
--- a/components/soc/esp32c61/i2c_periph.c
+++ b/components/soc/esp32c61/i2c_periph.c
@@ -21,3 +21,32 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
         .irq = ETS_I2C_EXT0_INTR_SOURCE,
     },
 };
+
+// I2C sleep retention entries
+// I2C registers require set the reg_update bit to make the configuration take effect
+
+/* I2C Registers Context
+   Include: I2C_SCL_LOW_PERIOD_REG /
+            I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
+            I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
+            I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
+*/
+#define I2C0_RETENTION_REGS_CNT  18
+#define I2C0_RETENTION_MAP_BASE  I2C_SCL_LOW_PERIOD_REG
+static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
+static const regdma_entries_config_t i2c0_regs_retention[] = {
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG, I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG, 0x0, I2C_FSM_RST_M, 1, 0), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG, I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+    [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG, 0x0, I2C_CONF_UPGATE_M, 1, 0), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+};
+
+const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
+    {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
+};
diff --git a/components/soc/esp32c61/i2s_periph.c b/components/soc/esp32c61/i2s_periph.c
new file mode 100644
index 00000000000..667c4d3e9f0
--- /dev/null
+++ b/components/soc/esp32c61/i2s_periph.c
@@ -0,0 +1,73 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/i2s_periph.h"
+#include "soc/i2s_reg.h"
+#include "soc/gpio_sig_map.h"
+
+/*
+ Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
+    {
+        .mck_out_sig  = I2S_MCLK_OUT_IDX,
+        .mck_in_sig   = I2S_MCLK_IN_IDX,
+
+        .m_tx_bck_sig = I2SO_BCK_OUT_IDX,
+        .m_rx_bck_sig = I2SI_BCK_OUT_IDX,
+        .m_tx_ws_sig  = I2SO_WS_OUT_IDX,
+        .m_rx_ws_sig  = I2SI_WS_OUT_IDX,
+
+        .s_tx_bck_sig = I2SO_BCK_IN_IDX,
+        .s_rx_bck_sig = I2SI_BCK_IN_IDX,
+        .s_tx_ws_sig  = I2SO_WS_IN_IDX,
+        .s_rx_ws_sig  = I2SI_WS_IN_IDX,
+
+        .data_out_sigs[0] = I2SO_SD_OUT_IDX,
+        .data_out_sigs[1] = I2SO_SD1_OUT_IDX,
+        .data_in_sig  = I2SI_SD_IN_IDX,
+
+        .irq          = ETS_I2S0_INTR_SOURCE,
+    }
+};
+
+/**
+ * I2S Registers to be saved during sleep retention
+ * - I2S_RX_CONF_REG
+ * - I2S_TX_CONF_REG
+ * - I2S_RX_CONF1_REG
+ * - I2S_TX_CONF1_REG
+ * - I2S_TX_PCM2PDM_CONF_REG
+ * - I2S_TX_PCM2PDM_CONF1_REG
+ * - I2S_RX_TDM_CTRL_REG
+ * - I2S_TX_TDM_CTRL_REG
+ * - I2S_RXEOF_NUM_REG
+ * - I2S_ETM_CONF_REG
+*/
+#define I2S_RETENTION_REGS_CNT 10
+#define I2S_RETENTION_REGS_BASE(i) I2S_RX_CONF_REG
+static const uint32_t i2s_regs_map[4] = {0x12360f, 0x0, 0x0, 0x0};
+#define I2S_SLEEP_RETENTION_ENTRIES(i2s_port) {  \
+    /* Save/restore the register values */  \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(  \
+                REGDMA_I2S_LINK(0x00), \
+                I2S_RETENTION_REGS_BASE(i2s_port),  \
+                I2S_RETENTION_REGS_BASE(i2s_port), \
+                I2S_RETENTION_REGS_CNT, 0, 0, \
+                i2s_regs_map[0], i2s_regs_map[1], \
+                i2s_regs_map[2], i2s_regs_map[3]), \
+            .owner = ENTRY(0) | ENTRY(2)}, \
+};
+
+static const regdma_entries_config_t i2s0_regs_retention[] = I2S_SLEEP_RETENTION_ENTRIES(0);
+
+const i2s_reg_retention_info_t i2s_reg_retention_info[SOC_I2S_NUM] = {
+    [0] = {
+        .retention_module = SLEEP_RETENTION_MODULE_I2S0,
+        .entry_array = i2s0_regs_retention,
+        .array_size = ARRAY_SIZE(i2s0_regs_retention)
+    },
+};
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index 2572350a643..a55c7719210 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -3,6 +3,10 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
+config SOC_ADC_SUPPORTED
+    bool
+    default y
+
 config SOC_DEDICATED_GPIO_SUPPORTED
     bool
     default y
@@ -55,6 +59,10 @@ config SOC_EFUSE_SUPPORTED
     bool
     default y
 
+config SOC_I2S_SUPPORTED
+    bool
+    default y
+
 config SOC_GPSPI_SUPPORTED
     bool
     default y
@@ -131,6 +139,10 @@ config SOC_REG_I2C_SUPPORTED
     bool
     default y
 
+config SOC_ETM_SUPPORTED
+    bool
+    default y
+
 config SOC_PAU_SUPPORTED
     bool
     default y
@@ -159,18 +171,90 @@ config SOC_XTAL_SUPPORT_40M
     bool
     default y
 
+config SOC_ADC_DIG_CTRL_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_DIG_IIR_FILTER_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_MONITOR_SUPPORTED
+    bool
+    default y
+
+config SOC_ADC_DMA_SUPPORTED
+    bool
+    default y
+
 config SOC_ADC_PERIPH_NUM
+    bool
+    default y
+
+config SOC_ADC_MAX_CHANNEL_NUM
+    int
+    default 4
+
+config SOC_ADC_ATTEN_NUM
+    int
+    default 4
+
+config SOC_ADC_DIGI_CONTROLLER_NUM
     int
     default 1
 
-config SOC_ADC_MAX_CHANNEL_NUM
+config SOC_ADC_PATT_LEN_MAX
     int
-    default 7
+    default 8
+
+config SOC_ADC_DIGI_MAX_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_DIGI_MIN_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_DIGI_IIR_FILTER_NUM
+    int
+    default 2
+
+config SOC_ADC_DIGI_MONITOR_NUM
+    int
+    default 2
+
+config SOC_ADC_DIGI_RESULT_BYTES
+    int
+    default 4
+
+config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
+    int
+    default 4
+
+config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
+    int
+    default 83333
+
+config SOC_ADC_SAMPLE_FREQ_THRES_LOW
+    int
+    default 611
+
+config SOC_ADC_RTC_MIN_BITWIDTH
+    int
+    default 12
+
+config SOC_ADC_RTC_MAX_BITWIDTH
+    int
+    default 12
 
 config SOC_ADC_TEMPERATURE_SHARE_INTR
     bool
     default y
 
+config SOC_ADC_SHARED_POWER
+    bool
+    default y
+
 config SOC_APB_BACKUP_DMA
     bool
     default n
@@ -267,6 +351,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
     int
     default 2
 
+config SOC_GDMA_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_GDMA_SUPPORT_SLEEP_RETENTION
     bool
     default y
@@ -279,13 +367,17 @@ config SOC_ETM_CHANNELS_PER_GROUP
     int
     default 50
 
+config SOC_ETM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_GPIO_PORT
     int
     default 1
 
 config SOC_GPIO_PIN_COUNT
     int
-    default 22
+    default 25
 
 config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
     bool
@@ -295,6 +387,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
     bool
     default y
 
+config SOC_GPIO_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
     bool
     default y
@@ -305,11 +401,11 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
 
 config SOC_GPIO_IN_RANGE_MAX
     int
-    default 21
+    default 24
 
 config SOC_GPIO_OUT_RANGE_MAX
     int
-    default 21
+    default 24
 
 config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
     bool
@@ -325,7 +421,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
 
 config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
     hex
-    default 0x00000000003FFF80
+    default 0x1FFFF80
 
 config SOC_GPIO_SUPPORT_FORCE_HOLD
     bool
@@ -423,6 +519,62 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
+config SOC_I2S_NUM
+    int
+    default 1
+
+config SOC_I2S_HW_VERSION_2
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_ETM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_TX_SYNC_CNT
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_XTAL
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PLL_F160M
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PLL_F120M
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PCM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM
+    bool
+    default y
+
+config SOC_I2S_SUPPORTS_PDM_TX
+    bool
+    default y
+
+config SOC_I2S_PDM_MAX_TX_LINES
+    int
+    default 2
+
+config SOC_I2S_SUPPORTS_TDM
+    bool
+    default y
+
+config SOC_I2S_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
     bool
     default y
@@ -431,6 +583,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6
@@ -455,6 +611,10 @@ config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
     int
     default 10
 
+config SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MMU_PAGE_SIZE_CONFIGURABLE
     bool
     default y
@@ -555,6 +715,10 @@ config SOC_SPI_SUPPORT_SLAVE_HD_VER2
     bool
     default y
 
+config SOC_SPI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_SPI_SUPPORT_CLK_XTAL
     bool
     default y
@@ -651,6 +815,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
     bool
     default y
 
+config SOC_SYSTIMER_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_LP_TIMER_BIT_WIDTH_LO
     int
     default 32
@@ -687,6 +855,10 @@ config SOC_TIMER_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
+config SOC_TIMER_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_MWDT_SUPPORT_SLEEP_RETENTION
     bool
     default y
@@ -935,10 +1107,18 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    bool
+    default y
+
 config SOC_RCC_IS_INDEPENDENT
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_WIFI_HW_TSF
     bool
     default y
@@ -975,6 +1155,10 @@ config SOC_BLE_SUPPORTED
     bool
     default y
 
+config SOC_BLE_MESH_SUPPORTED
+    bool
+    default y
+
 config SOC_ESP_NIMBLE_CONTROLLER
     bool
     default y
diff --git a/components/soc/esp32c61/include/soc/adc_channel.h b/components/soc/esp32c61/include/soc/adc_channel.h
index c3a9f1c7487..27d45a98ade 100644
--- a/components/soc/esp32c61/include/soc/adc_channel.h
+++ b/components/soc/esp32c61/include/soc/adc_channel.h
@@ -6,24 +6,14 @@
 
 #pragma once
 
-// TODO: [ESP32-C61] IDF-9302 Check the channel
-#define ADC1_GPIO0_CHANNEL      0
-#define ADC1_CHANNEL_0_GPIO_NUM 0
+#define ADC1_GPIO1_CHANNEL      0
+#define ADC1_CHANNEL_0_GPIO_NUM 1
 
-#define ADC1_GPIO1_CHANNEL      1
-#define ADC1_CHANNEL_1_GPIO_NUM 1
+#define ADC1_GPIO3_CHANNEL      1
+#define ADC1_CHANNEL_1_GPIO_NUM 3
 
-#define ADC1_GPIO2_CHANNEL      2
-#define ADC1_CHANNEL_2_GPIO_NUM 2
+#define ADC1_GPIO4_CHANNEL      2
+#define ADC1_CHANNEL_2_GPIO_NUM 4
 
-#define ADC1_GPIO3_CHANNEL      3
-#define ADC1_CHANNEL_3_GPIO_NUM 3
-
-#define ADC1_GPIO4_CHANNEL      4
-#define ADC1_CHANNEL_4_GPIO_NUM 4
-
-#define ADC1_GPIO5_CHANNEL      5
-#define ADC1_CHANNEL_5_GPIO_NUM 5
-
-#define ADC1_GPIO6_CHANNEL      6
-#define ADC1_CHANNEL_6_GPIO_NUM 6
+#define ADC1_GPIO5_CHANNEL      3
+#define ADC1_CHANNEL_3_GPIO_NUM 5
diff --git a/components/soc/esp32c61/include/soc/assist_debug_reg.h b/components/soc/esp32c61/include/soc/assist_debug_reg.h
deleted file mode 100644
index 4b7e6b6ff55..00000000000
--- a/components/soc/esp32c61/include/soc/assist_debug_reg.h
+++ /dev/null
@@ -1,824 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register
- *  core0 monitor enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
- *  Configures whether to monitor read operations in region 0 by the Data bus. \\
- *  0: Not monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
- *  Configures whether to monitor write operations in region 0 by the Data bus.\\
- *  0: Not monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
- *  Configures whether to monitor read operations in region 1 by the Data bus.\\
- *  0: Not Monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
- *  Configures whether to monitor write operations in region 1 by the Data bus.\\
- *  0: Not Monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
- *  Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
- *  0: Not Monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
- *  Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
- *  0: Not Monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
- *  Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
- *  0: Not Monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
- *  Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
- *  0: Not Monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
- *  Configures whether to monitor SP exceeding the lower bound address of SP monitored
- *  region.\\
- *  0: Not Monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
- *  Configures whether to monitor SP exceeding the upper bound address of SP monitored
- *  region.\\
- *  0: Not Monitor\\
- *  1: Monitor\\
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
- *  IBUS busy monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor enbale
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
- *  core0 monitor interrupt status register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status of read operations in region 0 by Data bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status of write operations in region 0 by Data bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status of read operations in region 1 by Data bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status of write operations in region 1 by Data bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status of read operations in region 0 by Peripheral bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status of write operations in region 0 by Peripheral bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status of read operations in region 1 by Peripheral bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
- *  The raw interrupt status of write operations in region 1 by Peripheral bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
- *  The raw interrupt status of SP exceeding the lower bound address of SP monitored
- *  region.
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
- *  The raw interrupt status of SP exceeding the upper bound address of SP monitored
- *  region.
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
- *  DBUS busy monitor initerrupt status
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
- *  core0 monitor interrupt enable register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt enbale
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
- *  core0 monitor interrupt clear register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear the interrupt for read operations in region 0 by Data bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear the interrupt for write operations in region 0 by Data bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear the interrupt for read operations in region 1 by Data bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear the interrupt for write operations in region 1 by Data bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
- *  Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
- *  Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
- *  Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
- *  Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
- *  monitored region.
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
- *  Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
- *  monitored region.
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
- *  Configures lower boundary address of region 0 monitored on Data bus
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configures the lower bound address of Data bus region 0.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
- *  Configures upper boundary address of region 0 monitored on Data bus
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Configures the upper bound address of Data bus region 0.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
- *  Configures lower boundary address of region 1 monitored on Data bus
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configures the lower bound address of Data bus region 1.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
- *  Configures upper boundary address of region 1 monitored on Data bus
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Configures the upper bound address of Data bus region 1.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
- *  Configures lower boundary address of region 0 monitored on Peripheral bus
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configures the lower bound address of Peripheral bus region 0.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
- *  Configures upper boundary address of region 0 monitored on Peripheral bus
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Configures the upper bound address of Peripheral bus region 0.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
- *  Configures lower boundary address of region 1 monitored on Peripheral bus
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configures the lower bound address of Peripheral bus region 1.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
- *  Configures upper boundary address of region 1 monitored on Peripheral bus
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Configures the upper bound address of Peripheral bus region 1.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
- *  Region monitoring HP CPU PC status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
-/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
- *  Represents the PC value when an interrupt is triggered during region monitoring.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
- *  Region monitoring HP CPU SP status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
-/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
- *  Represents the SP value when an interrupt is triggered during region monitoring.
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
- *  Configures stack monitoring lower boundary address
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
-/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  Configures the lower bound address of SP.
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
- *  Configures stack monitoring upper boundary address
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
-/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configures the upper bound address of SP.
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
- *  Stack monitoring HP CPU PC status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
-/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  Represents the PC value during stack monitoring.
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
- *  HP CPU PC logging enable register
- */
-#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
-/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
- *  Configures whether to enable PC logging.\\
- *  0: Disable\\
- *  1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
- */
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
- *  Configures whether to enable HP CPU debugging.\\
- *  0: Disable\\
- *  1: HP CPU outputs PC\\
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  PC logging register
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
- *  Represents the PC value at HP CPU reset.
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  PC logging register
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
- *  Represents SP.
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
-
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0;
- *  reg_core_0_iram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x3FFFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x3FFFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [30]; default: 0;
- *  reg_core_0_iram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(30))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  30
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [31]; default: 0;
- *  reg_core_0_iram0_recording_loadstore_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(31))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  31
-
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0;
- *  reg_core_0_iram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x3FFFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x3FFFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [30]; default: 0;
- *  reg_core_0_iram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(30))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  30
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [31]; default: 0;
- *  reg_core_0_iram0_recording_loadstore_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(31))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  31
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register2
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
- *  reg_core_0_dram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  0
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [4:1]; default: 0;
- *  reg_core_0_dram0_recording_byteen_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  1
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register3
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0;
- *  reg_core_0_dram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x3FFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x3FFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
- *  exception monitor status register4
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_0_dram0_recording_pc_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
- *  exception monitor status register5
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
- *  reg_core_0_dram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  0
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [4:1]; default: 0;
- *  reg_core_0_dram0_recording_byteen_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  1
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register
- *  exception monitor status register6
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0;
- *  reg_core_0_dram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x3FFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x3FFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register
- *  exception monitor status register7
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_0_dram0_recording_pc_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
-
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
- *  Represents the PC of the last command before the HP CPU enters exception.
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
-
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
- *  1: In debugging mode\\
- *  0: Not in debugging mode\\
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
- *  Represents the status of the RISC-V CPU (HP CPU) debug module.\\
- *  1: Active status\\
- *  Other: Inactive status\\
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
-
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register8
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
- *  reg_core_x_iram0_dram0_limit_cycle_0
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
-
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register9
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
- *  reg_core_x_iram0_dram0_limit_cycle_1
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
-
-/** ASSIST_DEBUG_CLOCK_GATE_REG register
- *  Register clock control
- */
-#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
-/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Configures whether to enable the register clock gating. \\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define ASSIST_DEBUG_CLK_EN    (BIT(0))
-#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
-#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
-#define ASSIST_DEBUG_CLK_EN_S  0
-
-/** ASSIST_DEBUG_DATE_REG register
- *  Version control register
- */
-#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
-/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
- *  version register
- */
-#define ASSIST_DEBUG_DATE    0x0FFFFFFFU
-#define ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
-#define ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
-#define ASSIST_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/assist_debug_struct.h b/components/soc/esp32c61/include/soc/assist_debug_struct.h
deleted file mode 100644
index 243b6959aa0..00000000000
--- a/components/soc/esp32c61/include/soc/assist_debug_struct.h
+++ /dev/null
@@ -1,774 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: monitor configuration registers */
-/** Type of core_0_montr_ena register
- *  core0 monitor enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
-         *  Configures whether to monitor read operations in region 0 by the Data bus. \\
-         *  0: Not monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_area_dram0_0_rd_ena:1;
-        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
-         *  Configures whether to monitor write operations in region 0 by the Data bus.\\
-         *  0: Not monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_area_dram0_0_wr_ena:1;
-        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
-         *  Configures whether to monitor read operations in region 1 by the Data bus.\\
-         *  0: Not Monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_area_dram0_1_rd_ena:1;
-        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
-         *  Configures whether to monitor write operations in region 1 by the Data bus.\\
-         *  0: Not Monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_area_dram0_1_wr_ena:1;
-        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
-         *  Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
-         *  0: Not Monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_area_pif_0_rd_ena:1;
-        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
-         *  Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
-         *  0: Not Monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_area_pif_0_wr_ena:1;
-        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
-         *  Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
-         *  0: Not Monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_area_pif_1_rd_ena:1;
-        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
-         *  Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
-         *  0: Not Monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_area_pif_1_wr_ena:1;
-        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
-         *  Configures whether to monitor SP exceeding the lower bound address of SP monitored
-         *  region.\\
-         *  0: Not Monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_sp_spill_min_ena:1;
-        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
-         *  Configures whether to monitor SP exceeding the upper bound address of SP monitored
-         *  region.\\
-         *  0: Not Monitor\\
-         *  1: Monitor\\
-         */
-        uint32_t core_0_sp_spill_max_ena:1;
-        /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
-         *  IBUS busy monitor enable
-         */
-        uint32_t core_0_iram0_exception_monitor_ena:1;
-        /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor enbale
-         */
-        uint32_t core_0_dram0_exception_monitor_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_montr_ena_reg_t;
-
-/** Type of core_0_area_dram0_0_min register
- *  Configures lower boundary address of region 0 monitored on Data bus
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configures the lower bound address of Data bus region 0.
-         */
-        uint32_t core_0_area_dram0_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_min_reg_t;
-
-/** Type of core_0_area_dram0_0_max register
- *  Configures upper boundary address of region 0 monitored on Data bus
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the upper bound address of Data bus region 0.
-         */
-        uint32_t core_0_area_dram0_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_max_reg_t;
-
-/** Type of core_0_area_dram0_1_min register
- *  Configures lower boundary address of region 1 monitored on Data bus
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configures the lower bound address of Data bus region 1.
-         */
-        uint32_t core_0_area_dram0_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_min_reg_t;
-
-/** Type of core_0_area_dram0_1_max register
- *  Configures upper boundary address of region 1 monitored on Data bus
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the upper bound address of Data bus region 1.
-         */
-        uint32_t core_0_area_dram0_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_max_reg_t;
-
-/** Type of core_0_area_pif_0_min register
- *  Configures lower boundary address of region 0 monitored on Peripheral bus
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configures the lower bound address of Peripheral bus region 0.
-         */
-        uint32_t core_0_area_pif_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_min_reg_t;
-
-/** Type of core_0_area_pif_0_max register
- *  Configures upper boundary address of region 0 monitored on Peripheral bus
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the upper bound address of Peripheral bus region 0.
-         */
-        uint32_t core_0_area_pif_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_max_reg_t;
-
-/** Type of core_0_area_pif_1_min register
- *  Configures lower boundary address of region 1 monitored on Peripheral bus
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configures the lower bound address of Peripheral bus region 1.
-         */
-        uint32_t core_0_area_pif_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_min_reg_t;
-
-/** Type of core_0_area_pif_1_max register
- *  Configures upper boundary address of region 1 monitored on Peripheral bus
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the upper bound address of Peripheral bus region 1.
-         */
-        uint32_t core_0_area_pif_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_max_reg_t;
-
-/** Type of core_0_area_pc register
- *  Region monitoring HP CPU PC status register
- */
-typedef union {
-    struct {
-        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
-         *  Represents the PC value when an interrupt is triggered during region monitoring.
-         */
-        uint32_t core_0_area_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pc_reg_t;
-
-/** Type of core_0_area_sp register
- *  Region monitoring HP CPU SP status register
- */
-typedef union {
-    struct {
-        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
-         *  Represents the SP value when an interrupt is triggered during region monitoring.
-         */
-        uint32_t core_0_area_sp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_sp_reg_t;
-
-/** Type of core_0_sp_min register
- *  Configures stack monitoring lower boundary address
- */
-typedef union {
-    struct {
-        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the lower bound address of SP.
-         */
-        uint32_t core_0_sp_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_min_reg_t;
-
-/** Type of core_0_sp_max register
- *  Configures stack monitoring upper boundary address
- */
-typedef union {
-    struct {
-        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configures the upper bound address of SP.
-         */
-        uint32_t core_0_sp_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_max_reg_t;
-
-/** Type of core_0_sp_pc register
- *  Stack monitoring HP CPU PC status register
- */
-typedef union {
-    struct {
-        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  Represents the PC value during stack monitoring.
-         */
-        uint32_t core_0_sp_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_pc_reg_t;
-
-
-/** Group: interrupt configuration register */
-/** Type of core_0_intr_raw register
- *  core0 monitor interrupt status register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status of read operations in region 0 by Data bus.
-         */
-        uint32_t core_0_area_dram0_0_rd_raw:1;
-        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status of write operations in region 0 by Data bus.
-         */
-        uint32_t core_0_area_dram0_0_wr_raw:1;
-        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
-         *  The raw interrupt status of read operations in region 1 by Data bus.
-         */
-        uint32_t core_0_area_dram0_1_rd_raw:1;
-        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
-         *  The raw interrupt status of write operations in region 1 by Data bus.
-         */
-        uint32_t core_0_area_dram0_1_wr_raw:1;
-        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
-         *  The raw interrupt status of read operations in region 0 by Peripheral bus.
-         */
-        uint32_t core_0_area_pif_0_rd_raw:1;
-        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
-         *  The raw interrupt status of write operations in region 0 by Peripheral bus.
-         */
-        uint32_t core_0_area_pif_0_wr_raw:1;
-        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
-         *  The raw interrupt status of read operations in region 1 by Peripheral bus.
-         */
-        uint32_t core_0_area_pif_1_rd_raw:1;
-        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
-         *  The raw interrupt status of write operations in region 1 by Peripheral bus.
-         */
-        uint32_t core_0_area_pif_1_wr_raw:1;
-        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
-         *  The raw interrupt status of SP exceeding the lower bound address of SP monitored
-         *  region.
-         */
-        uint32_t core_0_sp_spill_min_raw:1;
-        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
-         *  The raw interrupt status of SP exceeding the upper bound address of SP monitored
-         *  region.
-         */
-        uint32_t core_0_sp_spill_max_raw:1;
-        /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt status
-         */
-        uint32_t core_0_iram0_exception_monitor_raw:1;
-        /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
-         *  DBUS busy monitor initerrupt status
-         */
-        uint32_t core_0_dram0_exception_monitor_raw:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_raw_reg_t;
-
-/** Type of core_0_intr_ena register
- *  core0 monitor interrupt enable register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_rd_intr_ena:1;
-        /** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_wr_intr_ena:1;
-        /** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_rd_intr_ena:1;
-        /** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_wr_intr_ena:1;
-        /** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_rd_intr_ena:1;
-        /** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_wr_intr_ena:1;
-        /** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_rd_intr_ena:1;
-        /** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_wr_intr_ena:1;
-        /** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_min_intr_ena:1;
-        /** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_max_intr_ena:1;
-        /** core_0_iram0_exception_monitor_intr_ena : R/W; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt enable
-         */
-        uint32_t core_0_iram0_exception_monitor_intr_ena:1;
-        /** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt enbale
-         */
-        uint32_t core_0_dram0_exception_monitor_intr_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_ena_reg_t;
-
-/** Type of core_0_intr_clr register
- *  core0 monitor interrupt clear register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear the interrupt for read operations in region 0 by Data bus.
-         */
-        uint32_t core_0_area_dram0_0_rd_clr:1;
-        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear the interrupt for write operations in region 0 by Data bus.
-         */
-        uint32_t core_0_area_dram0_0_wr_clr:1;
-        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear the interrupt for read operations in region 1 by Data bus.
-         */
-        uint32_t core_0_area_dram0_1_rd_clr:1;
-        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear the interrupt for write operations in region 1 by Data bus.
-         */
-        uint32_t core_0_area_dram0_1_wr_clr:1;
-        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
-         */
-        uint32_t core_0_area_pif_0_rd_clr:1;
-        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
-         */
-        uint32_t core_0_area_pif_0_wr_clr:1;
-        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
-         */
-        uint32_t core_0_area_pif_1_rd_clr:1;
-        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
-         *  Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
-         */
-        uint32_t core_0_area_pif_1_wr_clr:1;
-        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
-         *  Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
-         *  monitored region.
-         */
-        uint32_t core_0_sp_spill_min_clr:1;
-        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
-         *  Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
-         *  monitored region.
-         */
-        uint32_t core_0_sp_spill_max_clr:1;
-        /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt clr
-         */
-        uint32_t core_0_iram0_exception_monitor_clr:1;
-        /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt clr
-         */
-        uint32_t core_0_dram0_exception_monitor_clr:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_clr_reg_t;
-
-
-/** Group: pc reording configuration register */
-/** Type of core_0_rcd_en register
- *  HP CPU PC logging enable register
- */
-typedef union {
-    struct {
-        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
-         *  Configures whether to enable PC logging.\\
-         *  0: Disable\\
-         *  1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
-         */
-        uint32_t core_0_rcd_recorden:1;
-        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
-         *  Configures whether to enable HP CPU debugging.\\
-         *  0: Disable\\
-         *  1: HP CPU outputs PC\\
-         */
-        uint32_t core_0_rcd_pdebugen:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_en_reg_t;
-
-
-/** Group: pc reording status register */
-/** Type of core_0_rcd_pdebugpc register
- *  PC logging register
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
-         *  Represents the PC value at HP CPU reset.
-         */
-        uint32_t core_0_rcd_pdebugpc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugpc_reg_t;
-
-/** Type of core_0_rcd_pdebugsp register
- *  PC logging register
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
-         *  Represents SP.
-         */
-        uint32_t core_0_rcd_pdebugsp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugsp_reg_t;
-
-
-/** Group: exception monitor regsiter */
-/** Type of core_0_iram0_exception_monitor_0 register
- *  exception monitor status register0
- */
-typedef union {
-    struct {
-        /** core_0_iram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
-         *  reg_core_0_iram0_recording_addr_0
-         */
-        uint32_t core_0_iram0_recording_addr_0:30;
-        /** core_0_iram0_recording_wr_0 : RO; bitpos: [30]; default: 0;
-         *  reg_core_0_iram0_recording_wr_0
-         */
-        uint32_t core_0_iram0_recording_wr_0:1;
-        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [31]; default: 0;
-         *  reg_core_0_iram0_recording_loadstore_0
-         */
-        uint32_t core_0_iram0_recording_loadstore_0:1;
-    };
-    uint32_t val;
-} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
-
-/** Type of core_0_iram0_exception_monitor_1 register
- *  exception monitor status register1
- */
-typedef union {
-    struct {
-        /** core_0_iram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
-         *  reg_core_0_iram0_recording_addr_1
-         */
-        uint32_t core_0_iram0_recording_addr_1:30;
-        /** core_0_iram0_recording_wr_1 : RO; bitpos: [30]; default: 0;
-         *  reg_core_0_iram0_recording_wr_1
-         */
-        uint32_t core_0_iram0_recording_wr_1:1;
-        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [31]; default: 0;
-         *  reg_core_0_iram0_recording_loadstore_1
-         */
-        uint32_t core_0_iram0_recording_loadstore_1:1;
-    };
-    uint32_t val;
-} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_0 register
- *  exception monitor status register2
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
-         *  reg_core_0_dram0_recording_wr_0
-         */
-        uint32_t core_0_dram0_recording_wr_0:1;
-        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [4:1]; default: 0;
-         *  reg_core_0_dram0_recording_byteen_0
-         */
-        uint32_t core_0_dram0_recording_byteen_0:4;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_1 register
- *  exception monitor status register3
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
-         *  reg_core_0_dram0_recording_addr_0
-         */
-        uint32_t core_0_dram0_recording_addr_0:30;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_2 register
- *  exception monitor status register4
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_0_dram0_recording_pc_0
-         */
-        uint32_t core_0_dram0_recording_pc_0:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_3 register
- *  exception monitor status register5
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
-         *  reg_core_0_dram0_recording_wr_1
-         */
-        uint32_t core_0_dram0_recording_wr_1:1;
-        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [4:1]; default: 0;
-         *  reg_core_0_dram0_recording_byteen_1
-         */
-        uint32_t core_0_dram0_recording_byteen_1:4;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_4 register
- *  exception monitor status register6
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
-         *  reg_core_0_dram0_recording_addr_1
-         */
-        uint32_t core_0_dram0_recording_addr_1:30;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_5 register
- *  exception monitor status register7
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_0_dram0_recording_pc_1
-         */
-        uint32_t core_0_dram0_recording_pc_1:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
-
-/** Type of core_x_iram0_dram0_exception_monitor_0 register
- *  exception monitor status register8
- */
-typedef union {
-    struct {
-        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
-         *  reg_core_x_iram0_dram0_limit_cycle_0
-         */
-        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_x_iram0_dram0_exception_monitor_1 register
- *  exception monitor status register9
- */
-typedef union {
-    struct {
-        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
-         *  reg_core_x_iram0_dram0_limit_cycle_1
-         */
-        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
-
-
-/** Group: cpu status registers */
-/** Type of core_0_lastpc_before_exception register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
-         *  Represents the PC of the last command before the HP CPU enters exception.
-         */
-        uint32_t core_0_lastpc_before_exc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_lastpc_before_exception_reg_t;
-
-/** Type of core_0_debug_mode register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
-         *  1: In debugging mode\\
-         *  0: Not in debugging mode\\
-         */
-        uint32_t core_0_debug_mode:1;
-        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
-         *  Represents the status of the RISC-V CPU (HP CPU) debug module.\\
-         *  1: Active status\\
-         *  Other: Inactive status\\
-         */
-        uint32_t core_0_debug_module_active:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_debug_mode_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of clock_gate register
- *  Register clock control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Configures whether to enable the register clock gating. \\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} assist_debug_clock_gate_reg_t;
-
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 34640176;
-         *  version register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} assist_debug_date_reg_t;
-
-
-typedef struct {
-    volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
-    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
-    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
-    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
-    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
-    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
-    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
-    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
-    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
-    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
-    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
-    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
-    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
-    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
-    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
-    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
-    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
-    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
-    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
-    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
-    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
-    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
-    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
-    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
-    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
-    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
-    volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
-    volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
-    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
-    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
-    uint32_t reserved_078[34];
-    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
-    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
-    volatile assist_debug_clock_gate_reg_t clock_gate;
-    uint32_t reserved_10c[188];
-    volatile assist_debug_date_reg_t date;
-} assist_debug_dev_t;
-
-extern assist_debug_dev_t ASSIST_DEBUG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/cache_reg.h b/components/soc/esp32c61/include/soc/cache_reg.h
deleted file mode 100644
index 98390f8e1ae..00000000000
--- a/components/soc/esp32c61/include/soc/cache_reg.h
+++ /dev/null
@@ -1,6166 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** CACHE_L1_ICACHE_CTRL_REG register
- *  L1 instruction Cache(L1-ICache) control register
- */
-#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
-/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0;
- *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
-#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
-/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0;
- *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
-#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
-/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
-#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
-/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
-#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
-/** CACHE_L1_ICACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE_UNDEF_OP    0x000000FFU
-#define CACHE_L1_ICACHE_UNDEF_OP_M  (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S)
-#define CACHE_L1_ICACHE_UNDEF_OP_V  0x000000FFU
-#define CACHE_L1_ICACHE_UNDEF_OP_S  8
-
-/** CACHE_L1_CACHE_CTRL_REG register
- *  L1 data Cache(L1-Cache) control register
- */
-#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
-/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0;
- *  The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable
- */
-#define CACHE_L1_CACHE_SHUT_BUS0    (BIT(0))
-#define CACHE_L1_CACHE_SHUT_BUS0_M  (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S)
-#define CACHE_L1_CACHE_SHUT_BUS0_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_BUS0_S  0
-/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0;
- *  The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable
- */
-#define CACHE_L1_CACHE_SHUT_BUS1    (BIT(1))
-#define CACHE_L1_CACHE_SHUT_BUS1_M  (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S)
-#define CACHE_L1_CACHE_SHUT_BUS1_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_BUS1_S  1
-/** CACHE_L1_CACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_CACHE_SHUT_DBUS2    (BIT(2))
-#define CACHE_L1_CACHE_SHUT_DBUS2_M  (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S)
-#define CACHE_L1_CACHE_SHUT_DBUS2_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_DBUS2_S  2
-/** CACHE_L1_CACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_CACHE_SHUT_DBUS3    (BIT(3))
-#define CACHE_L1_CACHE_SHUT_DBUS3_M  (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S)
-#define CACHE_L1_CACHE_SHUT_DBUS3_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_DBUS3_S  3
-/** CACHE_L1_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0;
- *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
- */
-#define CACHE_L1_CACHE_SHUT_DMA    (BIT(4))
-#define CACHE_L1_CACHE_SHUT_DMA_M  (CACHE_L1_CACHE_SHUT_DMA_V << CACHE_L1_CACHE_SHUT_DMA_S)
-#define CACHE_L1_CACHE_SHUT_DMA_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_DMA_S  4
-/** CACHE_L1_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_CACHE_UNDEF_OP    0x000000FFU
-#define CACHE_L1_CACHE_UNDEF_OP_M  (CACHE_L1_CACHE_UNDEF_OP_V << CACHE_L1_CACHE_UNDEF_OP_S)
-#define CACHE_L1_CACHE_UNDEF_OP_V  0x000000FFU
-#define CACHE_L1_CACHE_UNDEF_OP_S  8
-
-/** CACHE_L1_BYPASS_CACHE_CONF_REG register
- *  Bypass Cache configure register
- */
-#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
-/** CACHE_BYPASS_L1_ICACHE0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
-#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
-#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
-/** CACHE_BYPASS_L1_ICACHE1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
-#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
-#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
-/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
-#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
-#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
-/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
-#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
-#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
-/** CACHE_BYPASS_L1_DCACHE_EN : HRO; bitpos: [4]; default: 0;
- *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
-#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
-#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_DCACHE_EN_S  4
-
-/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
- *  L1 Cache atomic feature configure register
- */
-#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
-/** CACHE_L1_CACHE_ATOMIC_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
- *  L1-Cache.  1: disable, 1: enable.
- */
-#define CACHE_L1_CACHE_ATOMIC_EN    (BIT(0))
-#define CACHE_L1_CACHE_ATOMIC_EN_M  (CACHE_L1_CACHE_ATOMIC_EN_V << CACHE_L1_CACHE_ATOMIC_EN_S)
-#define CACHE_L1_CACHE_ATOMIC_EN_V  0x00000001U
-#define CACHE_L1_CACHE_ATOMIC_EN_S  0
-
-/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
- *  L1 instruction Cache CacheSize mode configure register
- */
-#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
-/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_256    (BIT(0))
-#define CACHE_L1_ICACHE_CACHESIZE_256_M  (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S)
-#define CACHE_L1_ICACHE_CACHESIZE_256_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_256_S  0
-/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_512    (BIT(1))
-#define CACHE_L1_ICACHE_CACHESIZE_512_M  (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S)
-#define CACHE_L1_ICACHE_CACHESIZE_512_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_512_S  1
-/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(2))
-#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_1K_S  2
-/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(3))
-#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_2K_S  3
-/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(4))
-#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_4K_S  4
-/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(5))
-#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_8K_S  5
-/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(6))
-#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_16K_S  6
-/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(7))
-#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_32K_S  7
-/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(8))
-#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_64K_S  8
-/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(9))
-#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_128K_S  9
-/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(10))
-#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_256K_S  10
-/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(11))
-#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_512K_S  11
-/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
- *  and all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(12))
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  12
-
-/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
- *  L1 instruction Cache BlockSize mode configure register
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
-/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
-/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
-/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
-/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
-/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
-/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L1_CACHE_CACHESIZE_CONF_REG register
- *  L1 data Cache CacheSize mode configure register
- */
-#define CACHE_L1_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
-/** CACHE_L1_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_256    (BIT(0))
-#define CACHE_L1_CACHE_CACHESIZE_256_M  (CACHE_L1_CACHE_CACHESIZE_256_V << CACHE_L1_CACHE_CACHESIZE_256_S)
-#define CACHE_L1_CACHE_CACHESIZE_256_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_256_S  0
-/** CACHE_L1_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_512    (BIT(1))
-#define CACHE_L1_CACHE_CACHESIZE_512_M  (CACHE_L1_CACHE_CACHESIZE_512_V << CACHE_L1_CACHE_CACHESIZE_512_S)
-#define CACHE_L1_CACHE_CACHESIZE_512_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_512_S  1
-/** CACHE_L1_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_1K    (BIT(2))
-#define CACHE_L1_CACHE_CACHESIZE_1K_M  (CACHE_L1_CACHE_CACHESIZE_1K_V << CACHE_L1_CACHE_CACHESIZE_1K_S)
-#define CACHE_L1_CACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_1K_S  2
-/** CACHE_L1_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_2K    (BIT(3))
-#define CACHE_L1_CACHE_CACHESIZE_2K_M  (CACHE_L1_CACHE_CACHESIZE_2K_V << CACHE_L1_CACHE_CACHESIZE_2K_S)
-#define CACHE_L1_CACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_2K_S  3
-/** CACHE_L1_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_4K    (BIT(4))
-#define CACHE_L1_CACHE_CACHESIZE_4K_M  (CACHE_L1_CACHE_CACHESIZE_4K_V << CACHE_L1_CACHE_CACHESIZE_4K_S)
-#define CACHE_L1_CACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_4K_S  4
-/** CACHE_L1_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_8K    (BIT(5))
-#define CACHE_L1_CACHE_CACHESIZE_8K_M  (CACHE_L1_CACHE_CACHESIZE_8K_V << CACHE_L1_CACHE_CACHESIZE_8K_S)
-#define CACHE_L1_CACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_8K_S  5
-/** CACHE_L1_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_16K    (BIT(6))
-#define CACHE_L1_CACHE_CACHESIZE_16K_M  (CACHE_L1_CACHE_CACHESIZE_16K_V << CACHE_L1_CACHE_CACHESIZE_16K_S)
-#define CACHE_L1_CACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_16K_S  6
-/** CACHE_L1_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 1;
- *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_32K    (BIT(7))
-#define CACHE_L1_CACHE_CACHESIZE_32K_M  (CACHE_L1_CACHE_CACHESIZE_32K_V << CACHE_L1_CACHE_CACHESIZE_32K_S)
-#define CACHE_L1_CACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_32K_S  7
-/** CACHE_L1_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_64K    (BIT(8))
-#define CACHE_L1_CACHE_CACHESIZE_64K_M  (CACHE_L1_CACHE_CACHESIZE_64K_V << CACHE_L1_CACHE_CACHESIZE_64K_S)
-#define CACHE_L1_CACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_64K_S  8
-/** CACHE_L1_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_128K    (BIT(9))
-#define CACHE_L1_CACHE_CACHESIZE_128K_M  (CACHE_L1_CACHE_CACHESIZE_128K_V << CACHE_L1_CACHE_CACHESIZE_128K_S)
-#define CACHE_L1_CACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_128K_S  9
-/** CACHE_L1_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_256K    (BIT(10))
-#define CACHE_L1_CACHE_CACHESIZE_256K_M  (CACHE_L1_CACHE_CACHESIZE_256K_V << CACHE_L1_CACHE_CACHESIZE_256K_S)
-#define CACHE_L1_CACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_256K_S  10
-/** CACHE_L1_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_512K    (BIT(11))
-#define CACHE_L1_CACHE_CACHESIZE_512K_M  (CACHE_L1_CACHE_CACHESIZE_512K_V << CACHE_L1_CACHE_CACHESIZE_512K_S)
-#define CACHE_L1_CACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_512K_S  11
-/** CACHE_L1_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
- *  and all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_1024K    (BIT(12))
-#define CACHE_L1_CACHE_CACHESIZE_1024K_M  (CACHE_L1_CACHE_CACHESIZE_1024K_V << CACHE_L1_CACHE_CACHESIZE_1024K_S)
-#define CACHE_L1_CACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_1024K_S  12
-
-/** CACHE_L1_CACHE_BLOCKSIZE_CONF_REG register
- *  L1 data Cache BlockSize mode configure register
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
-/** CACHE_L1_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L1_CACHE_BLOCKSIZE_8_M  (CACHE_L1_CACHE_BLOCKSIZE_8_V << CACHE_L1_CACHE_BLOCKSIZE_8_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_8_S  0
-/** CACHE_L1_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L1_CACHE_BLOCKSIZE_16_M  (CACHE_L1_CACHE_BLOCKSIZE_16_V << CACHE_L1_CACHE_BLOCKSIZE_16_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_16_S  1
-/** CACHE_L1_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 1;
- *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L1_CACHE_BLOCKSIZE_32_M  (CACHE_L1_CACHE_BLOCKSIZE_32_V << CACHE_L1_CACHE_BLOCKSIZE_32_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_32_S  2
-/** CACHE_L1_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L1_CACHE_BLOCKSIZE_64_M  (CACHE_L1_CACHE_BLOCKSIZE_64_V << CACHE_L1_CACHE_BLOCKSIZE_64_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_64_S  3
-/** CACHE_L1_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L1_CACHE_BLOCKSIZE_128_M  (CACHE_L1_CACHE_BLOCKSIZE_128_V << CACHE_L1_CACHE_BLOCKSIZE_128_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_128_S  4
-/** CACHE_L1_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L1_CACHE_BLOCKSIZE_256_M  (CACHE_L1_CACHE_BLOCKSIZE_256_V << CACHE_L1_CACHE_BLOCKSIZE_256_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
-/** CACHE_L1_ICACHE0_WRAP : HRO; bitpos: [0]; default: 0;
- *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
- */
-#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
-#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
-#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE0_WRAP_S  0
-/** CACHE_L1_ICACHE1_WRAP : HRO; bitpos: [1]; default: 0;
- *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
- */
-#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
-#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
-#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE1_WRAP_S  1
-/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
-#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
-#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE2_WRAP_S  2
-/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
-#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
-#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE3_WRAP_S  3
-/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0;
- *  Set this bit as 1 to enable L1-DCache wrap around mode.
- */
-#define CACHE_L1_CACHE_WRAP    (BIT(4))
-#define CACHE_L1_CACHE_WRAP_M  (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S)
-#define CACHE_L1_CACHE_WRAP_V  0x00000001U
-#define CACHE_L1_CACHE_WRAP_S  4
-
-/** CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
-/** CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS : HRO; bitpos: [0]; default: 0;
- *  Set this bit as 1 to disable early restart of  L1-ICache0
- */
-#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS    (BIT(0))
-#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S)
-#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V  0x00000001U
-#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S  0
-/** CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS : HRO; bitpos: [1]; default: 0;
- *  Set this bit as 1 to disable early restart of  L1-ICache1
- */
-#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS    (BIT(1))
-#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S)
-#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V  0x00000001U
-#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S  1
-/** CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS    (BIT(2))
-#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S)
-#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V  0x00000001U
-#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S  2
-/** CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS    (BIT(3))
-#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S)
-#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V  0x00000001U
-#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S  3
-/** CACHE_L1_CACHE_MISS_DISABLE_ACCESS : R/W; bitpos: [4]; default: 0;
- *  Set this bit as 1 to disable early restart of L1-DCache
- */
-#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS    (BIT(4))
-#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_M  (CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S)
-#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V  0x00000001U
-#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S  4
-
-/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
- *  Cache Freeze control register
- */
-#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
-/** CACHE_L1_ICACHE0_FREEZE_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
- *  software.
- */
-#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
-#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
-/** CACHE_L1_ICACHE0_FREEZE_MODE : HRO; bitpos: [1]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
-#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
-/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
-#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
-/** CACHE_L1_ICACHE1_FREEZE_EN : HRO; bitpos: [4]; default: 0;
- *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
- *  software.
- */
-#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
-#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
-/** CACHE_L1_ICACHE1_FREEZE_MODE : HRO; bitpos: [5]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
-#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
-/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
-#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
-/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
-#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
-/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
-#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
-/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
-#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
-/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
-#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
-/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
-#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
-/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
-#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
-/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
- *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
- *  software.
- */
-#define CACHE_L1_CACHE_FREEZE_EN    (BIT(16))
-#define CACHE_L1_CACHE_FREEZE_EN_M  (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S)
-#define CACHE_L1_CACHE_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_EN_S  16
-/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_CACHE_FREEZE_MODE    (BIT(17))
-#define CACHE_L1_CACHE_FREEZE_MODE_M  (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S)
-#define CACHE_L1_CACHE_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_MODE_S  17
-/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_CACHE_FREEZE_DONE    (BIT(18))
-#define CACHE_L1_CACHE_FREEZE_DONE_M  (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S)
-#define CACHE_L1_CACHE_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_DONE_S  18
-
-/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
- *  Cache data memory access configure register
- */
-#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x2c)
-/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
-/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
- *  1: enable.
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
-/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : HRO; bitpos: [4]; default: 0;
- *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
-/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : HRO; bitpos: [5]; default: 0;
- *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
- *  1: enable.
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
-/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
-/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
-/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
-/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
-/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 0;
- *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M  (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S)
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S  16
-/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 0;
- *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M  (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S)
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S  17
-
-/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
- *  Cache tag memory access configure register
- */
-#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
-/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
-/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
-/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : HRO; bitpos: [4]; default: 0;
- *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
-/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : HRO; bitpos: [5]; default: 0;
- *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
-/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
-/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
-/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
-/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
-/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 0;
- *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M  (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S)
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S  16
-/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 0;
- *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M  (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S)
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S  17
-
-/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
- *  L1 instruction Cache 0 prelock configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x34)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE0_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 prelock.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 0 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x38)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section of prelock
- *  on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 0 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x3c)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section of prelock
- *  on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 0 prelock section size configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x40)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
- *  L1 instruction Cache 1 prelock configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x44)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE1_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 prelock.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 1 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x48)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section of prelock
- *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 1 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x4c)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section of prelock
- *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 1 prelock section size configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x50)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
- *  L1 instruction Cache 2 prelock configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x54)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 prelock.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 2 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x58)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section of prelock
- *  on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 2 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x5c)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section of prelock
- *  on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 2 prelock section size configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x60)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
- *  L1 instruction Cache 3 prelock configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x64)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 prelock.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 3 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x68)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section of prelock
- *  on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 3 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x6c)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section of prelock
- *  on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 3 prelock section size configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x70)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_CACHE_PRELOCK_CONF_REG register
- *  L1 Cache prelock configure register
- */
-#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x74)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-Cache.
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-Cache.
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 cache prelock.
- */
-#define CACHE_L1_CACHE_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_CACHE_PRELOCK_RGID_M  (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S)
-#define CACHE_L1_CACHE_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_CACHE_PRELOCK_RGID_S  2
-
-/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register
- *  L1 Cache prelock section0 address configure register
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x78)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section of prelock
- *  on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
- *  L1 Cache prelock section1 address configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
-/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section of prelock
- *  on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
- *  L1  Cache prelock section size configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x80)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_LOCK_CTRL_REG register
- *  Lock-class (manual lock) operation control register
- */
-#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x84)
-/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable lock operation. It will be cleared by hardware after lock
- *  operation done
- */
-#define CACHE_LOCK_ENA    (BIT(0))
-#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
-#define CACHE_LOCK_ENA_V  0x00000001U
-#define CACHE_LOCK_ENA_S  0
-/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
- *  The bit is used to enable unlock operation. It will be cleared by hardware after
- *  unlock operation done
- */
-#define CACHE_UNLOCK_ENA    (BIT(1))
-#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
-#define CACHE_UNLOCK_ENA_V  0x00000001U
-#define CACHE_UNLOCK_ENA_S  1
-/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
- *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
- *  not finished. 1: finished.
- */
-#define CACHE_LOCK_DONE    (BIT(2))
-#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
-#define CACHE_LOCK_DONE_V  0x00000001U
-#define CACHE_LOCK_DONE_S  2
-/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of cache lock/unlock.
- */
-#define CACHE_LOCK_RGID    0x0000000FU
-#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
-#define CACHE_LOCK_RGID_V  0x0000000FU
-#define CACHE_LOCK_RGID_S  3
-
-/** CACHE_LOCK_MAP_REG register
- *  Lock (manual lock) map configure register
- */
-#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x88)
-/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Those bits are used to indicate which caches in the two-level cache structure will
- *  apply this lock/unlock operation. [4]: L1-Cache
- */
-#define CACHE_LOCK_MAP    0x0000003FU
-#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
-#define CACHE_LOCK_MAP_V  0x0000003FU
-#define CACHE_LOCK_MAP_S  0
-
-/** CACHE_LOCK_ADDR_REG register
- *  Lock (manual lock) address configure register
- */
-#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x8c)
-/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the lock/unlock operation,
- *  which should be used together with CACHE_LOCK_SIZE_REG
- */
-#define CACHE_LOCK_ADDR    0xFFFFFFFFU
-#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
-#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
-#define CACHE_LOCK_ADDR_S  0
-
-/** CACHE_LOCK_SIZE_REG register
- *  Lock (manual lock) size configure register
- */
-#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x90)
-/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
- *  Those bits are used to configure the size of the lock/unlock operation, which
- *  should be used together with CACHE_LOCK_ADDR_REG
- */
-#define CACHE_LOCK_SIZE    0x0000FFFFU
-#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
-#define CACHE_LOCK_SIZE_V  0x0000FFFFU
-#define CACHE_LOCK_SIZE_S  0
-
-/** CACHE_SYNC_CTRL_REG register
- *  Sync-class operation control register
- */
-#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x94)
-/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
- *  The bit is used to enable invalidate operation. It will be cleared by hardware
- *  after invalidate operation done. Note that this bit and the other sync-bits
- *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
- *  is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_INVALIDATE_ENA    (BIT(0))
-#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
-#define CACHE_INVALIDATE_ENA_V  0x00000001U
-#define CACHE_INVALIDATE_ENA_S  0
-/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
- *  The bit is used to enable clean operation. It will be cleared by hardware after
- *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
- *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
- *  bits can not be set to 1 at the same time.
- */
-#define CACHE_CLEAN_ENA    (BIT(1))
-#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
-#define CACHE_CLEAN_ENA_V  0x00000001U
-#define CACHE_CLEAN_ENA_S  1
-/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
- *  The bit is used to enable writeback operation. It will be cleared by hardware after
- *  writeback operation done. Note that this bit and the other sync-bits
- *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
- *  is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_WRITEBACK_ENA    (BIT(2))
-#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
-#define CACHE_WRITEBACK_ENA_V  0x00000001U
-#define CACHE_WRITEBACK_ENA_S  2
-/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
- *  The bit is used to enable writeback-invalidate operation. It will be cleared by
- *  hardware after writeback-invalidate operation done. Note that this bit and the
- *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
- *  that is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
-#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
-#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
-#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
-/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
- *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
- *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
- */
-#define CACHE_SYNC_DONE    (BIT(4))
-#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
-#define CACHE_SYNC_DONE_V  0x00000001U
-#define CACHE_SYNC_DONE_S  4
-/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0;
- *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
- *  writeback, writeback_invalidate)
- */
-#define CACHE_SYNC_RGID    0x0000000FU
-#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
-#define CACHE_SYNC_RGID_V  0x0000000FU
-#define CACHE_SYNC_RGID_S  5
-
-/** CACHE_SYNC_MAP_REG register
- *  Sync map configure register
- */
-#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x98)
-/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63;
- *  Those bits are used to indicate which caches in the two-level cache structure will
- *  apply the sync operation.  [4]: L1-Cache
- */
-#define CACHE_SYNC_MAP    0x0000003FU
-#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
-#define CACHE_SYNC_MAP_V  0x0000003FU
-#define CACHE_SYNC_MAP_S  0
-
-/** CACHE_SYNC_ADDR_REG register
- *  Sync address configure register
- */
-#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0x9c)
-/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the sync operation, which
- *  should be used together with CACHE_SYNC_SIZE_REG
- */
-#define CACHE_SYNC_ADDR    0xFFFFFFFFU
-#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
-#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
-#define CACHE_SYNC_ADDR_S  0
-
-/** CACHE_SYNC_SIZE_REG register
- *  Sync size configure register
- */
-#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa0)
-/** CACHE_SYNC_SIZE : R/W; bitpos: [24:0]; default: 0;
- *  Those bits are used to configure the size of the sync operation, which should be
- *  used together with CACHE_SYNC_ADDR_REG
- */
-#define CACHE_SYNC_SIZE    0x01FFFFFFU
-#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
-#define CACHE_SYNC_SIZE_V  0x01FFFFFFU
-#define CACHE_SYNC_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 0 preload-operation control register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa4)
-/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE0_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE0_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 preload.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 0 preload address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xa8)
-/** CACHE_L1_ICACHE0_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of preload on L1-ICache0, which
- *  should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 0 preload size configure register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xac)
-/** CACHE_L1_ICACHE0_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 1 preload-operation control register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb0)
-/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE1_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE1_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 preload.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 1 preload address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb4)
-/** CACHE_L1_ICACHE1_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of preload on L1-ICache1, which
- *  should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 1 preload size configure register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb8)
-/** CACHE_L1_ICACHE1_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 2 preload-operation control register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xbc)
-/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 preload.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 2 preload address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc0)
-/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of preload on L1-ICache2, which
- *  should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 2 preload size configure register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc4)
-/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 3 preload-operation control register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc8)
-/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 preload.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 3 preload address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xcc)
-/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of preload on L1-ICache3, which
- *  should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 3 preload size configure register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd0)
-/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register
- *  L1 Cache  preload-operation control register
- */
-#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd4)
-/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_CACHE_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_CACHE_PRELOAD_ENA_M  (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S)
-#define CACHE_L1_CACHE_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_ENA_S  0
-/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_CACHE_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_CACHE_PRELOAD_DONE_M  (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S)
-#define CACHE_L1_CACHE_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_DONE_S  1
-/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_CACHE_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_CACHE_PRELOAD_ORDER_M  (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S)
-#define CACHE_L1_CACHE_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_ORDER_S  2
-/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 cache preload.
- */
-#define CACHE_L1_CACHE_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_CACHE_PRELOAD_RGID_M  (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S)
-#define CACHE_L1_CACHE_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_CACHE_PRELOAD_RGID_S  3
-
-/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
- *  L1 Cache  preload address configure register
- */
-#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd8)
-/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of preload on L1-Cache, which
- *  should be used together with L1_CACHE_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOAD_ADDR_M  (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S)
-#define CACHE_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
- *  L1 Cache  preload size configure register
- */
-#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xdc)
-/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOAD_SIZE_M  (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S)
-#define CACHE_L1_CACHE_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 0 autoload-operation control register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe0)
-/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 autoload.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 0 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe4)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section for
- *  autoload operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 0 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xe8)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 0 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xec)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section for
- *  autoload operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 0 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf0)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 1 autoload-operation control register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf4)
-/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 autoload.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 1 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xf8)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section for
- *  autoload operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 1 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xfc)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 1 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x100)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section for
- *  autoload operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 1 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x104)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 2 autoload-operation control register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x108)
-/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 autoload.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 2 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x10c)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section for
- *  autoload operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 2 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x110)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 2 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x114)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section for
- *  autoload operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 2 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x118)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 3 autoload-operation control register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x11c)
-/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 autoload.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 3 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x120)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section for
- *  autoload operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 3 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x124)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 3 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x128)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section for
- *  autoload operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 3 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x12c)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register
- *  L1 Cache autoload-operation control register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x130)
-/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_S  0
-/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_M  (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_S  1
-/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M  (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S)
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
- *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
- *  The bit is used to enable the third section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S  10
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
- *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S  11
-/** CACHE_L1_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
- *  The bit is used to set  the gid of l1 cache autoload.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_CACHE_AUTOLOAD_RGID_M  (CACHE_L1_CACHE_AUTOLOAD_RGID_V << CACHE_L1_CACHE_AUTOLOAD_RGID_S)
-#define CACHE_L1_CACHE_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_CACHE_AUTOLOAD_RGID_S  12
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 Cache autoload section 0 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x134)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section for
- *  autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 Cache autoload section 0 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x138)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [24:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x01FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0x01FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 Cache autoload section 1 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x13c)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section for
- *  autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 Cache autoload section 1 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x140)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [24:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x01FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0x01FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG register
- *  L1 Cache autoload section 2 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x144)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the third section for
- *  autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG register
- *  L1 Cache autoload section 2 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x148)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [24:0]; default: 0;
- *  Those bits are used to configure the size of the third section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE    0x01FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V  0x01FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG register
- *  L1 Cache autoload section 1 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x14c)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the fourth section for
- *  autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG register
- *  L1 Cache autoload section 1 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x150)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [24:0]; default: 0;
- *  Those bits are used to configure the size of the fourth section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE    0x01FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V  0x01FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S  0
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
- *  Cache Access Counter Interrupt enable register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x154)
-/** CACHE_L1_IBUS0_OVF_INT_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-ICache0 due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
-/** CACHE_L1_IBUS1_OVF_INT_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-ICache1 due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
-/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
-/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
-/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-DCache due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_ENA    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ENA_M  (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S)
-#define CACHE_L1_BUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_ENA_S  4
-/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-DCache due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_ENA    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ENA_M  (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S)
-#define CACHE_L1_BUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_ENA_S  5
-/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
-#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
-/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
-#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
- *  Cache Access Counter Interrupt clear register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x158)
-/** CACHE_L1_IBUS0_OVF_INT_CLR : HRO; bitpos: [0]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
- *  to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
-/** CACHE_L1_IBUS1_OVF_INT_CLR : HRO; bitpos: [1]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
- *  to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
-/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
-/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
-/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
- *  to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_CLR    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_CLR_M  (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S)
-#define CACHE_L1_BUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_CLR_S  4
-/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
- *  to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_CLR    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_CLR_M  (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S)
-#define CACHE_L1_BUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_CLR_S  5
-/** CACHE_L1_DBUS2_OVF_INT_CLR : R/W; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
-#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
-/** CACHE_L1_DBUS3_OVF_INT_CLR : R/W; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
-#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
- *  Cache Access Counter Interrupt raw register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x15c)
-/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
- *  due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
-/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
- *  due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
-/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
- *  due to bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
-/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
- *  due to bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
-/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_RAW    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_RAW_M  (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S)
-#define CACHE_L1_BUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_RAW_S  4
-/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_RAW    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_RAW_M  (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S)
-#define CACHE_L1_BUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_RAW_S  5
-/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
-#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
-/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
-#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
- *  Cache Access Counter Interrupt status register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x160)
-/** CACHE_L1_IBUS0_OVF_INT_ST : HRO; bitpos: [0]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-ICache0 due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
-#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
-/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-ICache1 due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
-#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
-/** CACHE_L1_IBUS2_OVF_INT_ST : RO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
-#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
-/** CACHE_L1_IBUS3_OVF_INT_ST : RO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
-#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
-/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-DCache due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_ST    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ST_M  (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S)
-#define CACHE_L1_BUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_ST_S  4
-/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-DCache due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_ST    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ST_M  (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S)
-#define CACHE_L1_BUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_ST_S  5
-/** CACHE_L1_DBUS2_OVF_INT_ST : RO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
-#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
-/** CACHE_L1_DBUS3_OVF_INT_ST : RO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
-#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
-
-/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register
- *  Cache Access Fail Configuration register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x164)
-/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0;
- *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE    (BIT(0))
-#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S  0
-/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : HRO; bitpos: [1]; default: 0;
- *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE    (BIT(1))
-#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S  1
-/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE    (BIT(2))
-#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S  2
-/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : HRO; bitpos: [3]; default: 0;
- *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE    (BIT(3))
-#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S  3
-/** CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0;
- *  The bit is used to configure l1 cache access fail check mode. 0: the access fail is
- *  not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE    (BIT(4))
-#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
- *  Cache Access Fail Interrupt enable register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168)
-/** CACHE_L1_ICACHE0_FAIL_INT_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
- *  cpu accesses L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
- *  cpu accesses L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
-/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
- *  cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_ENA    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ENA_M  (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S)
-#define CACHE_L1_CACHE_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_ENA_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
- *  L1-Cache Access Fail Interrupt clear register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16c)
-/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
- *  cpu accesses L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
- *  cpu accesses L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
-/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
- *  cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_CLR    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_CLR_M  (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S)
-#define CACHE_L1_CACHE_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_CLR_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
- *  Cache Access Fail Interrupt raw register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170)
-/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
-/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_RAW    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_RAW_M  (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S)
-#define CACHE_L1_CACHE_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_RAW_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
- *  Cache Access Fail Interrupt status register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174)
-/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
- *  to cpu accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
- *  to cpu accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_ST : RO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_ST : RO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
-/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
- *  to cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_ST    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ST_M  (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S)
-#define CACHE_L1_CACHE_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_ST_S  4
-
-/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
- *  Cache Access Counter enable and clear register
- */
-#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178)
-/** CACHE_L1_IBUS0_CNT_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable ibus0 counter in L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
-#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
-#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS0_CNT_ENA_S  0
-/** CACHE_L1_IBUS1_CNT_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable ibus1 counter in L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
-#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
-#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS1_CNT_ENA_S  1
-/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
-#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
-#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS2_CNT_ENA_S  2
-/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
-#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
-#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS3_CNT_ENA_S  3
-/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable dbus0 counter in L1-DCache.
- */
-#define CACHE_L1_BUS0_CNT_ENA    (BIT(4))
-#define CACHE_L1_BUS0_CNT_ENA_M  (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S)
-#define CACHE_L1_BUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L1_BUS0_CNT_ENA_S  4
-/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable dbus1 counter in L1-DCache.
- */
-#define CACHE_L1_BUS1_CNT_ENA    (BIT(5))
-#define CACHE_L1_BUS1_CNT_ENA_M  (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S)
-#define CACHE_L1_BUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L1_BUS1_CNT_ENA_S  5
-/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
-#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
-#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS2_CNT_ENA_S  6
-/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
-#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
-#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS3_CNT_ENA_S  7
-/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0;
- *  The bit is used to clear ibus0 counter in L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
-#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
-#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS0_CNT_CLR_S  16
-/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0;
- *  The bit is used to clear ibus1 counter in L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
-#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
-#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS1_CNT_CLR_S  17
-/** CACHE_L1_IBUS2_CNT_CLR : WT; bitpos: [18]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
-#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
-#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS2_CNT_CLR_S  18
-/** CACHE_L1_IBUS3_CNT_CLR : WT; bitpos: [19]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
-#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
-#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS3_CNT_CLR_S  19
-/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
- *  The bit is used to clear dbus0 counter in L1-DCache.
- */
-#define CACHE_L1_BUS0_CNT_CLR    (BIT(20))
-#define CACHE_L1_BUS0_CNT_CLR_M  (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S)
-#define CACHE_L1_BUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L1_BUS0_CNT_CLR_S  20
-/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
- *  The bit is used to clear dbus1 counter in L1-DCache.
- */
-#define CACHE_L1_BUS1_CNT_CLR    (BIT(21))
-#define CACHE_L1_BUS1_CNT_CLR_M  (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S)
-#define CACHE_L1_BUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L1_BUS1_CNT_CLR_S  21
-/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
-#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
-#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS2_CNT_CLR_S  22
-/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
-#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
-#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS3_CNT_CLR_S  23
-
-/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
- *  L1-ICache bus0 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x17c)
-/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
-#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
- *  L1-ICache bus0 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x180)
-/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
-#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus0 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x184)
-/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L1-ICache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x188)
-/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L1_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
- *  L1-ICache bus1 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
-/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
-#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
- *  L1-ICache bus1 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x190)
-/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
-#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus1 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x194)
-/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L1-ICache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x198)
-/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L1_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
- *  L1-ICache bus2 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
-/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
-#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
- *  L1-ICache bus2 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
-/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
-#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus2 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
-/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register
- *  L1-ICache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
-/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L1_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S)
-#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
- *  L1-ICache bus3 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
-/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
-#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
- *  L1-ICache bus3 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
-/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
-#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus3 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
-/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register
- *  L1-ICache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
-/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L1_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S)
-#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
-/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_HIT_CNT_M  (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S)
-#define CACHE_L1_BUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_HIT_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
-/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_MISS_CNT_M  (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S)
-#define CACHE_L1_BUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_MISS_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
-/** CACHE_L1_BUS0_CONFLICT_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_CONFLICT_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_CONFLICT_RD_CNT_M  (CACHE_L1_BUS0_CONFLICT_RD_CNT_V << CACHE_L1_BUS0_CONFLICT_RD_CNT_S)
-#define CACHE_L1_BUS0_CONFLICT_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_CONFLICT_RD_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
-/** CACHE_L1_BUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-Cache accesses L2-Cache due to
- *  bus0 accessing L1-Cache.
- */
-#define CACHE_L1_BUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_RD_CNT_M  (CACHE_L1_BUS0_NXTLVL_RD_CNT_V << CACHE_L1_BUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L1_BUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus0 WB-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
-/** CACHE_L1_BUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_WR_CNT_M  (CACHE_L1_BUS0_NXTLVL_WR_CNT_V << CACHE_L1_BUS0_NXTLVL_WR_CNT_S)
-#define CACHE_L1_BUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
-/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_HIT_CNT_M  (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S)
-#define CACHE_L1_BUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_HIT_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
-/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_MISS_CNT_M  (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S)
-#define CACHE_L1_BUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_MISS_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
-/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_CONFLICT_CNT_M  (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S)
-#define CACHE_L1_BUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L1-DCache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
-/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-Cache accesses L2-Cache due to
- *  bus1 accessing L1-Cache.
- */
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus1 WB-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
-/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S)
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
- *  L1-DCache bus2 Hit-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
-/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
-#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_HIT_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
- *  L1-DCache bus2 Miss-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
-/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
-#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_MISS_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
- *  L1-DCache bus2 Conflict-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
-/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
-#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register
- *  L1-DCache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
-/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-Cache accesses L2-Cache due to
- *  bus2 accessing L1-Cache.
- */
-#define CACHE_L1_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S)
-#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus2 WB-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
-/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus2 accesses L1-Cache.
- */
-#define CACHE_L1_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S)
-#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
- *  L1-DCache bus3 Hit-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
-/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
-#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_HIT_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
- *  L1-DCache bus3 Miss-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1fc)
-/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
-#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_MISS_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
- *  L1-DCache bus3 Conflict-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x200)
-/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
-#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register
- *  L1-DCache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x204)
-/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-Cache accesses L2-Cache due to
- *  bus3 accessing L1-Cache.
- */
-#define CACHE_L1_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S)
-#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus3 WB-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x208)
-/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S)
-#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x20c)
-/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
-#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ID_S  0
-/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x210)
-/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214)
-/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
-#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ID_S  0
-/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218)
-/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c)
-/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
-#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ID_S  0
-/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220)
-/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x224)
-/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
-#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ID_S  0
-/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x228)
-/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
-
-/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register
- *  L1-Cache Access Fail ID/attribution information register
- */
-#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x22c)
-/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ID_M  (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S)
-#define CACHE_L1_CACHE_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ID_S  0
-/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ATTR_M  (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S)
-#define CACHE_L1_CACHE_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ATTR_S  16
-
-/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
- *  L1-Cache Access Fail Address information register
- */
-#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x230)
-/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_FAIL_ADDR_M  (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S)
-#define CACHE_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_FAIL_ADDR_S  0
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register
- *  L1-Cache Access Fail Interrupt enable register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x234)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
-/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S  4
-/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The bit is used to enable interrupt of Cache sync-operation done.
- */
-#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
-#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_ENA_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : HRO; bitpos: [7]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
-/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The bit is used to enable interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S  11
-/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The bit is used to enable interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
-#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_ENA_S  13
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register
- *  Sync Preload operation Interrupt clear register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x238)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : HRO; bitpos: [0]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-ICache0
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : HRO; bitpos: [1]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-ICache1
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
-/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
- *  is done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S  4
-/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
- *  done.
- */
-#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
-#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
-#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_CLR_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : HRO; bitpos: [7]; default: 0;
- *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : HRO; bitpos: [8]; default: 0;
- *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
-/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
- *  The bit is used to clear interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S  11
-/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The bit is used to clear interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
-#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
-#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_CLR_S  13
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register
- *  Sync Preload operation Interrupt raw register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x23c)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
- *  done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
- *  done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
-/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
- *  done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S  4
-/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
- */
-#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
-#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
-#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_RAW_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
- *  error occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
- *  error occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
-/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
- *  occurs.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S  11
-/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit of the interrupt that occurs only when Cache sync-operation error
- *  occurs.
- */
-#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
-#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
-#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_RAW_S  13
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register
- *  L1-Cache Access Fail Interrupt status register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x240)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : HRO; bitpos: [0]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : HRO; bitpos: [1]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
-/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-Cache
- *  preload-operation is done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M  (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S  4
-/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when Cache
- *  sync-operation is done.
- */
-#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
-#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_ST_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : HRO; bitpos: [7]; default: 0;
- *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : HRO; bitpos: [8]; default: 0;
- *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
-/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
- *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M  (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S  11
-/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
- *  The bit indicates the status of the interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
-#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_ST_S  13
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
- *  Cache Sync/Preload Operation exception register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x244)
-/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
-/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
-/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
-/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
-/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-Cache.
- */
-#define CACHE_L1_CACHE_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_CACHE_PLD_ERR_CODE_M  (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S)
-#define CACHE_L1_CACHE_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_CACHE_PLD_ERR_CODE_S  8
-/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
- *  The values 0-2 are available which means sync map, command conflict and size are
- *  error in Cache System.
- */
-#define CACHE_SYNC_ERR_CODE    0x00000003U
-#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
-#define CACHE_SYNC_ERR_CODE_V  0x00000003U
-#define CACHE_SYNC_ERR_CODE_S  12
-
-/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
- *  Cache Sync Reset control register
- */
-#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x248)
-/** CACHE_L1_ICACHE0_SYNC_RST : HRO; bitpos: [0]; default: 0;
- *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
-#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
-#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE0_SYNC_RST_S  0
-/** CACHE_L1_ICACHE1_SYNC_RST : HRO; bitpos: [1]; default: 0;
- *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
-#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
-#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE1_SYNC_RST_S  1
-/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
-#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
-#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE2_SYNC_RST_S  2
-/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
-#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
-#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE3_SYNC_RST_S  3
-/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
- *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_CACHE_SYNC_RST    (BIT(4))
-#define CACHE_L1_CACHE_SYNC_RST_M  (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S)
-#define CACHE_L1_CACHE_SYNC_RST_V  0x00000001U
-#define CACHE_L1_CACHE_SYNC_RST_S  4
-
-/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
- *  Cache Preload Reset control register
- */
-#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c)
-/** CACHE_L1_ICACHE0_PLD_RST : HRO; bitpos: [0]; default: 0;
- *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
-#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_RST_S  0
-/** CACHE_L1_ICACHE1_PLD_RST : HRO; bitpos: [1]; default: 0;
- *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
-#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_RST_S  1
-/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
-#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_RST_S  2
-/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
-#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_RST_S  3
-/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
- *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_CACHE_PLD_RST    (BIT(4))
-#define CACHE_L1_CACHE_PLD_RST_M  (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S)
-#define CACHE_L1_CACHE_PLD_RST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_RST_S  4
-
-/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
- *  Cache Autoload buffer clear control register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x250)
-/** CACHE_L1_ICACHE0_ALD_BUF_CLR : HRO; bitpos: [0]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
- *  autoload will not work in L1-ICache0. This bit should not be active when autoload
- *  works in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
-/** CACHE_L1_ICACHE1_ALD_BUF_CLR : HRO; bitpos: [1]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
- *  autoload will not work in L1-ICache1. This bit should not be active when autoload
- *  works in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
-/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
-/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
-/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
- *  autoload will not work in L1-Cache. This bit should not be active when autoload
- *  works in L1-Cache.
- */
-#define CACHE_L1_CACHE_ALD_BUF_CLR    (BIT(4))
-#define CACHE_L1_CACHE_ALD_BUF_CLR_M  (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S)
-#define CACHE_L1_CACHE_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_ALD_BUF_CLR_S  4
-
-/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
- *  Unallocate request buffer clear registers
- */
-#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x254)
-/** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
-/** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
-/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
-/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
-/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 cache where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
-#define CACHE_L1_CACHE_UNALLOC_CLR_M  (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S)
-#define CACHE_L1_CACHE_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_UNALLOC_CLR_S  4
-
-/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
- *  Cache Tag and Data memory Object control register
- */
-#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x258)
-/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0;
- *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
-#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
-/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0;
- *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
-#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
-/** CACHE_L1_ICACHE2_TAG_OBJECT : R/W; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
-#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
-/** CACHE_L1_ICACHE3_TAG_OBJECT : R/W; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
-#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
-/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
- *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_CACHE_TAG_OBJECT    (BIT(4))
-#define CACHE_L1_CACHE_TAG_OBJECT_M  (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S)
-#define CACHE_L1_CACHE_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_OBJECT_S  4
-/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0;
- *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
- *  with the others fields inside this register.
- */
-#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
-#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
-/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0;
- *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
- *  with the others fields inside this register.
- */
-#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
-#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
-/** CACHE_L1_ICACHE2_MEM_OBJECT : R/W; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
-#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
-/** CACHE_L1_ICACHE3_MEM_OBJECT : R/W; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
-#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
-/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
- *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_CACHE_MEM_OBJECT    (BIT(10))
-#define CACHE_L1_CACHE_MEM_OBJECT_M  (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S)
-#define CACHE_L1_CACHE_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_CACHE_MEM_OBJECT_S  10
-
-/** CACHE_L1_CACHE_WAY_OBJECT_REG register
- *  Cache Tag and Data memory way register
- */
-#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x25c)
-/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
- *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
- *  way1, 2: way2, 3: way3, ?, 7: way7.
- */
-#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
-#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
-#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
-#define CACHE_L1_CACHE_WAY_OBJECT_S  0
-
-/** CACHE_L1_CACHE_ADDR_REG register
- *  Cache address register
- */
-#define CACHE_L1_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x260)
-/** CACHE_L1_CACHE_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits stores the address which will decide where inside the specified tag
- *  memory object will be accessed.
- */
-#define CACHE_L1_CACHE_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_ADDR_M  (CACHE_L1_CACHE_ADDR_V << CACHE_L1_CACHE_ADDR_S)
-#define CACHE_L1_CACHE_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_ADDR_S  0
-
-/** CACHE_L1_CACHE_DEBUG_BUS_REG register
- *  Cache Tag/data memory content register
- */
-#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x264)
-/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 612;
- *  This is a constant place where we can write data to or read data from the tag/data
- *  memory on the specified cache.
- */
-#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
-#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
-#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_DEBUG_BUS_S  0
-
-/** CACHE_LEVEL_SPLIT0_REG register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x268)
-/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 616;
- *  Reserved
- */
-#define CACHE_LEVEL_SPLIT0    0xFFFFFFFFU
-#define CACHE_LEVEL_SPLIT0_M  (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S)
-#define CACHE_LEVEL_SPLIT0_V  0xFFFFFFFFU
-#define CACHE_LEVEL_SPLIT0_S  0
-
-/** CACHE_L2_CACHE_CTRL_REG register
- *  L2 Cache(L2-Cache) control register
- */
-#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x26c)
-/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0;
- *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
- */
-#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
-#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
-#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
-#define CACHE_L2_CACHE_SHUT_DMA_S  4
-/** CACHE_L2_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_CACHE_UNDEF_OP    0x000000FFU
-#define CACHE_L2_CACHE_UNDEF_OP_M  (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S)
-#define CACHE_L2_CACHE_UNDEF_OP_V  0x000000FFU
-#define CACHE_L2_CACHE_UNDEF_OP_S  8
-
-/** CACHE_L2_BYPASS_CACHE_CONF_REG register
- *  Bypass Cache configure register
- */
-#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x270)
-/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0;
- *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
-#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
-#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
-#define CACHE_BYPASS_L2_CACHE_EN_S  5
-
-/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
- *  L2 Cache CacheSize mode configure register
- */
-#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x274)
-/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_256    (BIT(0))
-#define CACHE_L2_CACHE_CACHESIZE_256_M  (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S)
-#define CACHE_L2_CACHE_CACHESIZE_256_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_256_S  0
-/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_512    (BIT(1))
-#define CACHE_L2_CACHE_CACHESIZE_512_M  (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S)
-#define CACHE_L2_CACHE_CACHESIZE_512_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_512_S  1
-/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(2))
-#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
-#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_1K_S  2
-/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(3))
-#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
-#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_2K_S  3
-/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(4))
-#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
-#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_4K_S  4
-/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(5))
-#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
-#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_8K_S  5
-/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(6))
-#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
-#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_16K_S  6
-/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(7))
-#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
-#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_32K_S  7
-/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(8))
-#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
-#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_64K_S  8
-/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(9))
-#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
-#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_128K_S  9
-/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(10))
-#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
-#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_256K_S  10
-/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(11))
-#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
-#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_512K_S  11
-/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(12))
-#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
-#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_1024K_S  12
-
-/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
- *  L2 Cache BlockSize mode configure register
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278)
-/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
-/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
-/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
-/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
-/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
-/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x27c)
-/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0;
- *  Set this bit as 1 to enable L2-Cache wrap around mode.
- */
-#define CACHE_L2_CACHE_WRAP    (BIT(5))
-#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
-#define CACHE_L2_CACHE_WRAP_V  0x00000001U
-#define CACHE_L2_CACHE_WRAP_S  5
-
-/** CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x280)
-/** CACHE_L2_CACHE_MISS_DISABLE_ACCESS : HRO; bitpos: [5]; default: 0;
- *  Set this bit as 1 to disable early restart of  L2-Cache
- */
-#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS    (BIT(5))
-#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_M  (CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S)
-#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V  0x00000001U
-#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S  5
-
-/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
- *  Cache Freeze control register
- */
-#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x284)
-/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0;
- *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
- *  software.
- */
-#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
-#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
-#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_EN_S  20
-/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0;
- *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
-#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
-#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_MODE_S  21
-/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
- *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
-#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
-#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_DONE_S  22
-
-/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
- *  Cache data memory access configure register
- */
-#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x288)
-/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 0;
- *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
-/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 0;
- *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
-
-/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
- *  Cache tag memory access configure register
- */
-#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x28c)
-/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 0;
- *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
-/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 0;
- *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
-
-/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
- *  L2 Cache prelock configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x290)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L2-Cache.
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
-/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L2-Cache.
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
-/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l2 cache prelock.
- */
-#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
-#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
-#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
-
-/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
- *  L2 Cache prelock section0 address configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x294)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section of prelock
- *  on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
- *  L2 Cache prelock section1 address configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x298)
-/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section of prelock
- *  on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
- *  L2 Cache prelock section size configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x29c)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
- *  L2 Cache preload-operation control register
- */
-#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a0)
-/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
-#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
-#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
-/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
-#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
-#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
-/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
-#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
-/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l2 cache preload.
- */
-#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
-#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
-#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
-
-/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
- *  L2 Cache preload address configure register
- */
-#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2a4)
-/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of preload on L2-Cache, which
- *  should be used together with L2_CACHE_PRELOAD_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
-#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
- *  L2 Cache preload size configure register
- */
-#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2a8)
-/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
-#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
- *  L2 Cache autoload-operation control register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2ac)
-/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
- *  0: disable.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
-/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
-/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
-/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
- *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
- *  The bit is used to enable the third section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
- *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
-/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
- *  The bit is used to set  the gid of l2 cache autoload.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
- *  L2 Cache autoload section 0 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b0)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the first section for
- *  autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
- *  L2 Cache autoload section 0 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2b4)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
- *  L2 Cache autoload section 1 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the second section for
- *  autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
- *  L2 Cache autoload section 1 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
- *  L2 Cache autoload section 2 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the third section for
- *  autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
- *  L2 Cache autoload section 2 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the third section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
- *  L2 Cache autoload section 3 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start address of the fourth section for
- *  autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
- *  L2 Cache autoload section 3 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the fourth section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
- *  Cache Access Counter Interrupt enable register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d0)
-/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
-/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
-/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
-/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
-/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
-/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
-/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
-/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
- *  Cache Access Counter Interrupt clear register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2d4)
-/** CACHE_L2_IBUS0_OVF_INT_CLR : HRO; bitpos: [8]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
-/** CACHE_L2_IBUS1_OVF_INT_CLR : HRO; bitpos: [9]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
-/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
-/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
-/** CACHE_L2_DBUS0_OVF_INT_CLR : HRO; bitpos: [12]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
-/** CACHE_L2_DBUS1_OVF_INT_CLR : HRO; bitpos: [13]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
-/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
-/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
- *  Cache Access Counter Interrupt raw register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2d8)
-/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus0 accesses L2-ICache0.
- */
-#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
-/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus1 accesses L2-ICache1.
- */
-#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
-/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus2 accesses L2-ICache2.
- */
-#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
-/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus3 accesses L2-ICache3.
- */
-#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
-/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus0 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
-/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus1 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
-/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus2 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
-/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus3 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
- *  Cache Access Counter Interrupt status register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2dc)
-/** CACHE_L2_IBUS0_OVF_INT_ST : HRO; bitpos: [8]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
-#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
-/** CACHE_L2_IBUS1_OVF_INT_ST : HRO; bitpos: [9]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
-#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
-/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
-#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
-/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
-#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
-/** CACHE_L2_DBUS0_OVF_INT_ST : HRO; bitpos: [12]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
-#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
-/** CACHE_L2_DBUS1_OVF_INT_ST : HRO; bitpos: [13]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
-#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
-/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
-#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
-/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
-#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
-
-/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register
- *  Cache Access Fail Configuration register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e0)
-/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0;
- *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
- *  not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE    (BIT(0))
-#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S  0
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
- *  Cache Access Fail Interrupt enable register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2e4)
-/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
- *  l1 cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
-#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
- *  L1-Cache Access Fail Interrupt clear register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2e8)
-/** CACHE_L2_CACHE_FAIL_INT_CLR : HRO; bitpos: [5]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
- *  cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
-#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
- *  Cache Access Fail Interrupt raw register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2ec)
-/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
-#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
- *  Cache Access Fail Interrupt status register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f0)
-/** CACHE_L2_CACHE_FAIL_INT_ST : HRO; bitpos: [5]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
- *  to l1 cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
-#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
-
-/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
- *  Cache Access Counter enable and clear register
- */
-#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2f4)
-/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable ibus0 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
-#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
-#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS0_CNT_ENA_S  8
-/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable ibus1 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
-#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
-#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS1_CNT_ENA_S  9
-/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
-#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
-#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS2_CNT_ENA_S  10
-/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
-#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
-#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS3_CNT_ENA_S  11
-/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0;
- *  The bit is used to enable dbus0 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
-#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
-#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS0_CNT_ENA_S  12
-/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0;
- *  The bit is used to enable dbus1 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
-#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
-#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS1_CNT_ENA_S  13
-/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
-#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
-#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS2_CNT_ENA_S  14
-/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
-#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
-#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS3_CNT_ENA_S  15
-/** CACHE_L2_IBUS0_CNT_CLR : HRO; bitpos: [24]; default: 0;
- *  The bit is used to clear ibus0 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
-#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
-#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS0_CNT_CLR_S  24
-/** CACHE_L2_IBUS1_CNT_CLR : HRO; bitpos: [25]; default: 0;
- *  The bit is used to clear ibus1 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
-#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
-#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS1_CNT_CLR_S  25
-/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
-#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
-#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS2_CNT_CLR_S  26
-/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
-#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
-#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS3_CNT_CLR_S  27
-/** CACHE_L2_DBUS0_CNT_CLR : HRO; bitpos: [28]; default: 0;
- *  The bit is used to clear dbus0 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
-#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
-#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS0_CNT_CLR_S  28
-/** CACHE_L2_DBUS1_CNT_CLR : HRO; bitpos: [29]; default: 0;
- *  The bit is used to clear dbus1 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
-#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
-#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS1_CNT_CLR_S  29
-/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
-#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
-#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS2_CNT_CLR_S  30
-/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
-#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
-#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS3_CNT_CLR_S  31
-
-/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2f8)
-/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
-#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2fc)
-/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
-#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
-/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache0 accesses
- *  L2-Cache due to bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x304)
-/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
-/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
-#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
-/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
-#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
-/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache1 accesses
- *  L2-Cache due to bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x314)
-/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
-/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
-#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
-/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
-#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
-/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache2 accesses
- *  L2-Cache due to bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x324)
-/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S)
-#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
-/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
-#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
-/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
-#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
-/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache3 accesses
- *  L2-Cache due to bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x334)
-/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S)
-#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
-/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
-#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
-/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
-#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
-/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x344)
-/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register
- *  L2-Cache bus0 WB-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x348)
-/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when L1-DCache accesses L2-Cache due
- *  to bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S)
-#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
-/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
-#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x350)
-/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
-#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x354)
-/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x358)
-/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register
- *  L2-Cache bus1 WB-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
-/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when L1-DCache accesses L2-Cache due
- *  to bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S)
-#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x360)
-/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
-#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x364)
-/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
-#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x368)
-/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x36c)
-/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S)
-#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register
- *  L2-Cache bus2 WB-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x370)
-/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when L1-DCache accesses L2-Cache due
- *  to bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S)
-#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x374)
-/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
-#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x378)
-/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
-#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x37c)
-/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x380)
-/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S)
-#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register
- *  L2-Cache bus3 WB-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x384)
-/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when L1-DCache accesses L2-Cache due
- *  to bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S)
-#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
- *  L2-Cache Access Fail ID/attribution information register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x388)
-/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
-#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ID_S  0
-/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
- *  due to cache accessing L1-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
-#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ATTR_S  16
-
-/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
- *  L2-Cache Access Fail Address information register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x38c)
-/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
-#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_FAIL_ADDR_S  0
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
- *  L1-Cache Access Fail Interrupt enable register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x390)
-/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of L2-Cache preload-operation done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0;
- *  The bit is used to enable interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
- *  Sync Preload operation Interrupt clear register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x394)
-/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : HRO; bitpos: [5]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
- *  is done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : HRO; bitpos: [12]; default: 0;
- *  The bit is used to clear interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
- *  Sync Preload operation Interrupt raw register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x398)
-/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
- *  done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
- *  occurs.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
- *  L1-Cache Access Fail Interrupt status register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x39c)
-/** CACHE_L2_CACHE_PLD_DONE_INT_ST : HRO; bitpos: [5]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L2-Cache
- *  preload-operation is done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_ST : HRO; bitpos: [12]; default: 0;
- *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
- *  Cache Sync/Preload Operation exception register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a0)
-/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
- *  The value 2 is Only available which means preload size is error in L2-Cache.
- */
-#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
-#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
-#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
-
-/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
- *  Cache Sync Reset control register
- */
-#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a4)
-/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0;
- *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
-#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
-#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
-#define CACHE_L2_CACHE_SYNC_RST_S  5
-
-/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
- *  Cache Preload Reset control register
- */
-#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a8)
-/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0;
- *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
-#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
-#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_RST_S  5
-
-/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
- *  Cache Autoload buffer clear control register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac)
-/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0;
- *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
- *  autoload will not work in L2-Cache. This bit should not be active when autoload
- *  works in L2-Cache.
- */
-#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
-#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
-#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
-
-/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
- *  Unallocate request buffer clear registers
- */
-#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b0)
-/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l2 icache where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
-#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
-#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
-
-/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
- *  L2 cache access attribute control register
- */
-#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4)
-/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1;
- *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
- *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
- *  non-cacheable.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
-/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1;
- *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
- *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
- *  write-through.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
-/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1;
- *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
- *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
- *  write-miss-allocate and write-miss-no-allocate.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
-/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1;
- *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
- *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
- *  read-miss-allocate and read-miss-no-allocate.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
-
-/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
- *  Cache Tag and Data memory Object control register
- */
-#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3b8)
-/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0;
- *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
-#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
-#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_OBJECT_S  5
-/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0;
- *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
-#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
-#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
-#define CACHE_L2_CACHE_MEM_OBJECT_S  11
-
-/** CACHE_L2_CACHE_WAY_OBJECT_REG register
- *  Cache Tag and Data memory way register
- */
-#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3bc)
-/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0;
- *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
- *  way1, 2: way2, 3: way3, ?, 7: way7.
- */
-#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
-#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
-#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
-#define CACHE_L2_CACHE_WAY_OBJECT_S  0
-
-/** CACHE_L2_CACHE_ADDR_REG register
- *  Cache address register
- */
-#define CACHE_L2_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x3c0)
-/** CACHE_L2_CACHE_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits stores the address which will decide where inside the specified tag
- *  memory object will be accessed.
- */
-#define CACHE_L2_CACHE_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_ADDR_M  (CACHE_L2_CACHE_ADDR_V << CACHE_L2_CACHE_ADDR_S)
-#define CACHE_L2_CACHE_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_ADDR_S  0
-
-/** CACHE_L2_CACHE_DEBUG_BUS_REG register
- *  Cache Tag/data memory content register
- */
-#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3c4)
-/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 964;
- *  This is a constant place where we can write data to or read data from the tag/data
- *  memory on the specified cache.
- */
-#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
-#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
-#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_DEBUG_BUS_S  0
-
-/** CACHE_LEVEL_SPLIT1_REG register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3c8)
-/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 968;
- *  Reserved
- */
-#define CACHE_LEVEL_SPLIT1    0xFFFFFFFFU
-#define CACHE_LEVEL_SPLIT1_M  (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S)
-#define CACHE_LEVEL_SPLIT1_V  0xFFFFFFFFU
-#define CACHE_LEVEL_SPLIT1_S  0
-
-/** CACHE_CLOCK_GATE_REG register
- *  Clock gate control register
- */
-#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3cc)
-/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable clock gate when access all registers in this module.
- */
-#define CACHE_CLK_EN    (BIT(0))
-#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
-#define CACHE_CLK_EN_V  0x00000001U
-#define CACHE_CLK_EN_S  0
-
-/** CACHE_TRACE_ENA_REG register
- *  Clock gate control register
- */
-#define CACHE_TRACE_ENA_REG (DR_REG_CACHE_BASE + 0x3d0)
-/** CACHE_L1_CACHE_TRACE_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable L1-Cache trace for the performance counter and fail tracer
- */
-#define CACHE_L1_CACHE_TRACE_ENA    (BIT(0))
-#define CACHE_L1_CACHE_TRACE_ENA_M  (CACHE_L1_CACHE_TRACE_ENA_V << CACHE_L1_CACHE_TRACE_ENA_S)
-#define CACHE_L1_CACHE_TRACE_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_TRACE_ENA_S  0
-/** CACHE_L2_CACHE_TRACE_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable L2-Cache trace for the performance counter and fail tracer
- */
-#define CACHE_L2_CACHE_TRACE_ENA    (BIT(1))
-#define CACHE_L2_CACHE_TRACE_ENA_M  (CACHE_L2_CACHE_TRACE_ENA_V << CACHE_L2_CACHE_TRACE_ENA_S)
-#define CACHE_L2_CACHE_TRACE_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_TRACE_ENA_S  1
-
-/** CACHE_REDUNDANCY_SIG0_REG register
- *  Cache redundancy signal 0 register
- */
-#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3d4)
-/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG0    0xFFFFFFFFU
-#define CACHE_REDCY_SIG0_M  (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S)
-#define CACHE_REDCY_SIG0_V  0xFFFFFFFFU
-#define CACHE_REDCY_SIG0_S  0
-
-/** CACHE_REDUNDANCY_SIG1_REG register
- *  Cache redundancy signal 1 register
- */
-#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3d8)
-/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG1    0xFFFFFFFFU
-#define CACHE_REDCY_SIG1_M  (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S)
-#define CACHE_REDCY_SIG1_V  0xFFFFFFFFU
-#define CACHE_REDCY_SIG1_S  0
-
-/** CACHE_REDUNDANCY_SIG2_REG register
- *  Cache redundancy signal 2 register
- */
-#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3dc)
-/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG2    0xFFFFFFFFU
-#define CACHE_REDCY_SIG2_M  (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S)
-#define CACHE_REDCY_SIG2_V  0xFFFFFFFFU
-#define CACHE_REDCY_SIG2_S  0
-
-/** CACHE_REDUNDANCY_SIG3_REG register
- *  Cache redundancy signal 3 register
- */
-#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3e0)
-/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG3    0xFFFFFFFFU
-#define CACHE_REDCY_SIG3_M  (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S)
-#define CACHE_REDCY_SIG3_V  0xFFFFFFFFU
-#define CACHE_REDCY_SIG3_S  0
-
-/** CACHE_REDUNDANCY_SIG4_REG register
- *  Cache redundancy signal 0 register
- */
-#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3e4)
-/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG4    0x0000000FU
-#define CACHE_REDCY_SIG4_M  (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S)
-#define CACHE_REDCY_SIG4_V  0x0000000FU
-#define CACHE_REDCY_SIG4_S  0
-
-/** CACHE_DATE_REG register
- *  Version control register
- */
-#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
-/** CACHE_DATE : R/W; bitpos: [27:0]; default: 36774432;
- *  version control register. Note that this default value stored is the latest date
- *  when the hardware logic was updated.
- */
-#define CACHE_DATE    0x0FFFFFFFU
-#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
-#define CACHE_DATE_V  0x0FFFFFFFU
-#define CACHE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/cache_struct.h b/components/soc/esp32c61/include/soc/cache_struct.h
deleted file mode 100644
index f98620a26b3..00000000000
--- a/components/soc/esp32c61/include/soc/cache_struct.h
+++ /dev/null
@@ -1,5761 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Control and configuration registers */
-/** Type of l1_icache_ctrl register
- *  L1 instruction Cache(L1-ICache) control register
- */
-typedef union {
-    struct {
-        /** l1_icache_shut_ibus0 : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus0:1;
-        /** l1_icache_shut_ibus1 : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus1:1;
-        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus2:1;
-        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus3:1;
-        uint32_t reserved_4:4;
-        /** l1_icache_undef_op : R/W; bitpos: [15:8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_undef_op:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l1_icache_ctrl_reg_t;
-
-/** Type of l1_cache_ctrl register
- *  L1 data Cache(L1-Cache) control register
- */
-typedef union {
-    struct {
-        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus0:1;
-        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus1:1;
-        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus2:1;
-        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus3:1;
-        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_dma:1;
-        uint32_t reserved_5:3;
-        /** l1_cache_undef_op : R/W; bitpos: [15:8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_undef_op:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l1_cache_ctrl_reg_t;
-
-/** Type of l2_cache_ctrl register
- *  L2 Cache(L2-Cache) control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
-         */
-        uint32_t l2_cache_shut_dma:1;
-        uint32_t reserved_5:3;
-        /** l2_cache_undef_op : R/W; bitpos: [15:8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_cache_undef_op:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_ctrl_reg_t;
-
-
-/** Group: Bypass Cache Control and configuration registers */
-/** Type of l1_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache0_en:1;
-        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache1_en:1;
-        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache2_en:1;
-        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache3_en:1;
-        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_dcache_en:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_bypass_cache_conf_reg_t;
-
-/** Type of l2_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l2_cache_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_bypass_cache_conf_reg_t;
-
-
-/** Group: Cache Atomic Control and configuration registers */
-/** Type of l1_cache_atomic_conf register
- *  L1 Cache atomic feature configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
-         *  L1-Cache.  1: disable, 1: enable.
-         */
-        uint32_t l1_cache_atomic_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cache_l1_cache_atomic_conf_reg_t;
-
-
-/** Group: Cache Mode Control and configuration registers */
-/** Type of l1_icache_cachesize_conf register
- *  L1 instruction Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_cachesize_256 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_256:1;
-        /** l1_icache_cachesize_512 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_512:1;
-        /** l1_icache_cachesize_1k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1k:1;
-        /** l1_icache_cachesize_2k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2k:1;
-        /** l1_icache_cachesize_4k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4k:1;
-        /** l1_icache_cachesize_8k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_8k:1;
-        /** l1_icache_cachesize_16k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_16k:1;
-        /** l1_icache_cachesize_32k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_32k:1;
-        /** l1_icache_cachesize_64k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_64k:1;
-        /** l1_icache_cachesize_128k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_128k:1;
-        /** l1_icache_cachesize_256k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_256k:1;
-        /** l1_icache_cachesize_512k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_512k:1;
-        /** l1_icache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1024k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l1_icache_cachesize_conf_reg_t;
-
-/** Type of l1_icache_blocksize_conf register
- *  L1 instruction Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_8:1;
-        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_16:1;
-        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_32:1;
-        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_64:1;
-        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_128:1;
-        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache_blocksize_conf_reg_t;
-
-/** Type of l1_cache_cachesize_conf register
- *  L1 data Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_cachesize_256 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_256:1;
-        /** l1_cache_cachesize_512 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_512:1;
-        /** l1_cache_cachesize_1k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1k:1;
-        /** l1_cache_cachesize_2k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2k:1;
-        /** l1_cache_cachesize_4k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4k:1;
-        /** l1_cache_cachesize_8k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_8k:1;
-        /** l1_cache_cachesize_16k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_16k:1;
-        /** l1_cache_cachesize_32k : HRO; bitpos: [7]; default: 1;
-         *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_32k:1;
-        /** l1_cache_cachesize_64k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_64k:1;
-        /** l1_cache_cachesize_128k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_128k:1;
-        /** l1_cache_cachesize_256k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_256k:1;
-        /** l1_cache_cachesize_512k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_512k:1;
-        /** l1_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1024k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l1_cache_cachesize_conf_reg_t;
-
-/** Type of l1_cache_blocksize_conf register
- *  L1 data Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_8:1;
-        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_16:1;
-        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
-         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_32:1;
-        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_64:1;
-        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_128:1;
-        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_blocksize_conf_reg_t;
-
-/** Type of l2_cache_cachesize_conf register
- *  L2 Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_cachesize_256 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_256:1;
-        /** l2_cache_cachesize_512 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_512:1;
-        /** l2_cache_cachesize_1k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1k:1;
-        /** l2_cache_cachesize_2k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2k:1;
-        /** l2_cache_cachesize_4k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4k:1;
-        /** l2_cache_cachesize_8k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_8k:1;
-        /** l2_cache_cachesize_16k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_16k:1;
-        /** l2_cache_cachesize_32k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_32k:1;
-        /** l2_cache_cachesize_64k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_64k:1;
-        /** l2_cache_cachesize_128k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_128k:1;
-        /** l2_cache_cachesize_256k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_256k:1;
-        /** l2_cache_cachesize_512k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_512k:1;
-        /** l2_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1024k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_cachesize_conf_reg_t;
-
-/** Type of l2_cache_blocksize_conf register
- *  L2 Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_8:1;
-        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_16:1;
-        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_32:1;
-        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_64:1;
-        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_128:1;
-        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_blocksize_conf_reg_t;
-
-
-/** Group: Wrap Mode Control and configuration registers */
-/** Type of l1_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
-         */
-        uint32_t l1_icache0_wrap:1;
-        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
-         */
-        uint32_t l1_icache1_wrap:1;
-        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_wrap:1;
-        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_wrap:1;
-        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
-         *  Set this bit as 1 to enable L1-DCache wrap around mode.
-         */
-        uint32_t l1_cache_wrap:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_wrap_around_ctrl_reg_t;
-
-/** Type of l2_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
-         *  Set this bit as 1 to enable L2-Cache wrap around mode.
-         */
-        uint32_t l2_cache_wrap:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_wrap_around_ctrl_reg_t;
-
-
-/** Group: Early Restart Control registers */
-/** Type of l1_cache_miss_access_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_miss_disable_access : HRO; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to disable early restart of  L1-ICache0
-         */
-        uint32_t l1_icache0_miss_disable_access:1;
-        /** l1_icache1_miss_disable_access : HRO; bitpos: [1]; default: 0;
-         *  Set this bit as 1 to disable early restart of  L1-ICache1
-         */
-        uint32_t l1_icache1_miss_disable_access:1;
-        /** l1_icache2_miss_disable_access : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_miss_disable_access:1;
-        /** l1_icache3_miss_disable_access : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_miss_disable_access:1;
-        /** l1_cache_miss_disable_access : R/W; bitpos: [4]; default: 0;
-         *  Set this bit as 1 to disable early restart of L1-DCache
-         */
-        uint32_t l1_cache_miss_disable_access:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_miss_access_ctrl_reg_t;
-
-/** Type of l2_cache_miss_access_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_miss_disable_access : HRO; bitpos: [5]; default: 0;
-         *  Set this bit as 1 to disable early restart of  L2-Cache
-         */
-        uint32_t l2_cache_miss_disable_access:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_miss_access_ctrl_reg_t;
-
-
-/** Group: Cache Freeze Control registers */
-/** Type of l1_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache0_freeze_en:1;
-        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache0_freeze_mode:1;
-        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_freeze_done:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache1_freeze_en:1;
-        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache1_freeze_mode:1;
-        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_freeze_done:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_en:1;
-        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_mode:1;
-        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_done:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_en:1;
-        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_mode:1;
-        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_done:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
-         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_cache_freeze_en:1;
-        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_cache_freeze_mode:1;
-        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_freeze_done:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} cache_l1_cache_freeze_ctrl_reg_t;
-
-/** Type of l2_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l2_cache_freeze_en:1;
-        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l2_cache_freeze_mode:1;
-        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_freeze_done:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} cache_l2_cache_freeze_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Access Control and Configuration registers */
-/** Type of l1_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_data_mem_rd_en:1;
-        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache0_data_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_data_mem_rd_en:1;
-        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache1_data_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_rd_en:1;
-        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_rd_en:1;
-        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 0;
-         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_rd_en:1;
-        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} cache_l1_cache_data_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_rd_en:1;
-        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} cache_l2_cache_data_mem_acs_conf_reg_t;
-
-
-/** Group: Cache Tag Memory Access Control and Configuration registers */
-/** Type of l1_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_rd_en:1;
-        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_rd_en:1;
-        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_rd_en:1;
-        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_rd_en:1;
-        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 0;
-         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_rd_en:1;
-        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} cache_l1_cache_tag_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_rd_en:1;
-        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} cache_l2_cache_tag_mem_acs_conf_reg_t;
-
-
-/** Group: Prelock Control and configuration registers */
-/** Type of l1_icache0_prelock_conf register
- *  L1 instruction Cache 0 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct0_en:1;
-        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct1_en:1;
-        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 prelock.
-         */
-        uint32_t l1_icache0_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache0_prelock_conf_reg_t;
-
-/** Type of l1_icache0_prelock_sct0_addr register
- *  L1 instruction Cache 0 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section of prelock
-         *  on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct1_addr register
- *  L1 instruction Cache 0 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section of prelock
-         *  on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct_size register
- *  L1 instruction Cache 0 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_icache0_prelock_sct_size_reg_t;
-
-/** Type of l1_icache1_prelock_conf register
- *  L1 instruction Cache 1 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct0_en:1;
-        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct1_en:1;
-        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 prelock.
-         */
-        uint32_t l1_icache1_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache1_prelock_conf_reg_t;
-
-/** Type of l1_icache1_prelock_sct0_addr register
- *  L1 instruction Cache 1 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section of prelock
-         *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct1_addr register
- *  L1 instruction Cache 1 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section of prelock
-         *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct_size register
- *  L1 instruction Cache 1 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_icache1_prelock_sct_size_reg_t;
-
-/** Type of l1_icache2_prelock_conf register
- *  L1 instruction Cache 2 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct0_en:1;
-        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct1_en:1;
-        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 prelock.
-         */
-        uint32_t l1_icache2_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache2_prelock_conf_reg_t;
-
-/** Type of l1_icache2_prelock_sct0_addr register
- *  L1 instruction Cache 2 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section of prelock
-         *  on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct1_addr register
- *  L1 instruction Cache 2 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section of prelock
-         *  on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct_size register
- *  L1 instruction Cache 2 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_icache2_prelock_sct_size_reg_t;
-
-/** Type of l1_icache3_prelock_conf register
- *  L1 instruction Cache 3 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct0_en:1;
-        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct1_en:1;
-        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 prelock.
-         */
-        uint32_t l1_icache3_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache3_prelock_conf_reg_t;
-
-/** Type of l1_icache3_prelock_sct0_addr register
- *  L1 instruction Cache 3 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section of prelock
-         *  on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct1_addr register
- *  L1 instruction Cache 3 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section of prelock
-         *  on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct_size register
- *  L1 instruction Cache 3 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_icache3_prelock_sct_size_reg_t;
-
-/** Type of l1_cache_prelock_conf register
- *  L1 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct0_en:1;
-        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct1_en:1;
-        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 cache prelock.
-         */
-        uint32_t l1_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_prelock_conf_reg_t;
-
-/** Type of l1_cache_prelock_sct0_addr register
- *  L1 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section of prelock
-         *  on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct1_addr register
- *  L1 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section of prelock
-         *  on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_prelock_sct1_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct_size register
- *  L1  Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_dcache_prelock_sct_size_reg_t;
-
-/** Type of l2_cache_prelock_conf register
- *  L2 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct0_en:1;
-        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct1_en:1;
-        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l2 cache prelock.
-         */
-        uint32_t l2_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_prelock_conf_reg_t;
-
-/** Type of l2_cache_prelock_sct0_addr register
- *  L2 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section of prelock
-         *  on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct1_addr register
- *  L2 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section of prelock
-         *  on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_prelock_sct1_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct_size register
- *  L2 Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct0_size:16;
-        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct1_size:16;
-    };
-    uint32_t val;
-} cache_l2_cache_prelock_sct_size_reg_t;
-
-
-/** Group: Lock Control and configuration registers */
-/** Type of lock_ctrl register
- *  Lock-class (manual lock) operation control register
- */
-typedef union {
-    struct {
-        /** lock_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
-         *  operation done
-         */
-        uint32_t lock_ena:1;
-        /** unlock_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable unlock operation. It will be cleared by hardware after
-         *  unlock operation done
-         */
-        uint32_t unlock_ena:1;
-        /** lock_done : RO; bitpos: [2]; default: 1;
-         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
-         *  not finished. 1: finished.
-         */
-        uint32_t lock_done:1;
-        /** lock_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of cache lock/unlock.
-         */
-        uint32_t lock_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_lock_ctrl_reg_t;
-
-/** Type of lock_map register
- *  Lock (manual lock) map configure register
- */
-typedef union {
-    struct {
-        /** lock_map : R/W; bitpos: [5:0]; default: 0;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply this lock/unlock operation. [4]: L1-Cache
-         */
-        uint32_t lock_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_lock_map_reg_t;
-
-/** Type of lock_addr register
- *  Lock (manual lock) address configure register
- */
-typedef union {
-    struct {
-        /** lock_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the lock/unlock operation,
-         *  which should be used together with CACHE_LOCK_SIZE_REG
-         */
-        uint32_t lock_addr:32;
-    };
-    uint32_t val;
-} cache_lock_addr_reg_t;
-
-/** Type of lock_size register
- *  Lock (manual lock) size configure register
- */
-typedef union {
-    struct {
-        /** lock_size : R/W; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the lock/unlock operation, which
-         *  should be used together with CACHE_LOCK_ADDR_REG
-         */
-        uint32_t lock_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_lock_size_reg_t;
-
-
-/** Group: Sync Control and configuration registers */
-/** Type of sync_ctrl register
- *  Sync-class operation control register
- */
-typedef union {
-    struct {
-        /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
-         *  The bit is used to enable invalidate operation. It will be cleared by hardware
-         *  after invalidate operation done. Note that this bit and the other sync-bits
-         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t invalidate_ena:1;
-        /** clean_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable clean operation. It will be cleared by hardware after
-         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
-         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
-         *  bits can not be set to 1 at the same time.
-         */
-        uint32_t clean_ena:1;
-        /** writeback_ena : R/W/SC; bitpos: [2]; default: 0;
-         *  The bit is used to enable writeback operation. It will be cleared by hardware after
-         *  writeback operation done. Note that this bit and the other sync-bits
-         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t writeback_ena:1;
-        /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
-         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
-         *  hardware after writeback-invalidate operation done. Note that this bit and the
-         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
-         *  that is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t writeback_invalidate_ena:1;
-        /** sync_done : RO; bitpos: [4]; default: 0;
-         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
-         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
-         */
-        uint32_t sync_done:1;
-        /** sync_rgid : HRO; bitpos: [8:5]; default: 0;
-         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
-         *  writeback, writeback_invalidate)
-         */
-        uint32_t sync_rgid:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} cache_sync_ctrl_reg_t;
-
-/** Type of sync_map register
- *  Sync map configure register
- */
-typedef union {
-    struct {
-        /** sync_map : R/W; bitpos: [5:0]; default: 63;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply the sync operation.  [4]: L1-Cache
-         */
-        uint32_t sync_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_sync_map_reg_t;
-
-/** Type of sync_addr register
- *  Sync address configure register
- */
-typedef union {
-    struct {
-        /** sync_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the sync operation, which
-         *  should be used together with CACHE_SYNC_SIZE_REG
-         */
-        uint32_t sync_addr:32;
-    };
-    uint32_t val;
-} cache_sync_addr_reg_t;
-
-/** Type of sync_size register
- *  Sync size configure register
- */
-typedef union {
-    struct {
-        /** sync_size : R/W; bitpos: [24:0]; default: 0;
-         *  Those bits are used to configure the size of the sync operation, which should be
-         *  used together with CACHE_SYNC_ADDR_REG
-         */
-        uint32_t sync_size:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} cache_sync_size_reg_t;
-
-
-/** Group: Preload Control and configuration registers */
-/** Type of l1_icache0_preload_ctrl register
- *  L1 instruction Cache 0 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache0_preload_ena:1;
-        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache0_preload_done:1;
-        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache0_preload_order:1;
-        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 preload.
-         */
-        uint32_t l1_icache0_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_icache0_preload_ctrl_reg_t;
-
-/** Type of l1_icache0_preload_addr register
- *  L1 instruction Cache 0 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of preload on L1-ICache0, which
-         *  should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache0_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_preload_addr_reg_t;
-
-/** Type of l1_icache0_preload_size register
- *  L1 instruction Cache 0 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache0_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache0_preload_size_reg_t;
-
-/** Type of l1_icache1_preload_ctrl register
- *  L1 instruction Cache 1 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache1_preload_ena:1;
-        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache1_preload_done:1;
-        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache1_preload_order:1;
-        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 preload.
-         */
-        uint32_t l1_icache1_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_icache1_preload_ctrl_reg_t;
-
-/** Type of l1_icache1_preload_addr register
- *  L1 instruction Cache 1 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of preload on L1-ICache1, which
-         *  should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache1_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_preload_addr_reg_t;
-
-/** Type of l1_icache1_preload_size register
- *  L1 instruction Cache 1 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache1_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache1_preload_size_reg_t;
-
-/** Type of l1_icache2_preload_ctrl register
- *  L1 instruction Cache 2 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache2_preload_ena:1;
-        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache2_preload_done:1;
-        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache2_preload_order:1;
-        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 preload.
-         */
-        uint32_t l1_icache2_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_icache2_preload_ctrl_reg_t;
-
-/** Type of l1_icache2_preload_addr register
- *  L1 instruction Cache 2 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of preload on L1-ICache2, which
-         *  should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache2_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_preload_addr_reg_t;
-
-/** Type of l1_icache2_preload_size register
- *  L1 instruction Cache 2 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache2_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache2_preload_size_reg_t;
-
-/** Type of l1_icache3_preload_ctrl register
- *  L1 instruction Cache 3 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache3_preload_ena:1;
-        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache3_preload_done:1;
-        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache3_preload_order:1;
-        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 preload.
-         */
-        uint32_t l1_icache3_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_icache3_preload_ctrl_reg_t;
-
-/** Type of l1_icache3_preload_addr register
- *  L1 instruction Cache 3 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of preload on L1-ICache3, which
-         *  should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache3_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_preload_addr_reg_t;
-
-/** Type of l1_icache3_preload_size register
- *  L1 instruction Cache 3 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache3_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache3_preload_size_reg_t;
-
-/** Type of l1_cache_preload_ctrl register
- *  L1 Cache  preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_cache_preload_ena:1;
-        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_cache_preload_done:1;
-        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_cache_preload_order:1;
-        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 cache preload.
-         */
-        uint32_t l1_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_cache_preload_ctrl_reg_t;
-
-/** Type of l1_dcache_preload_addr register
- *  L1 Cache  preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of preload on L1-Cache, which
-         *  should be used together with L1_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_cache_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_preload_addr_reg_t;
-
-/** Type of l1_dcache_preload_size register
- *  L1 Cache  preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_cache_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_dcache_preload_size_reg_t;
-
-/** Type of l2_cache_preload_ctrl register
- *  L2 Cache preload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l2_cache_preload_ena:1;
-        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l2_cache_preload_done:1;
-        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l2_cache_preload_order:1;
-        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l2 cache preload.
-         */
-        uint32_t l2_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l2_cache_preload_ctrl_reg_t;
-
-/** Type of l2_cache_preload_addr register
- *  L2 Cache preload address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of preload on L2-Cache, which
-         *  should be used together with L2_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l2_cache_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_preload_addr_reg_t;
-
-/** Type of l2_cache_preload_size register
- *  L2 Cache preload size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l2_cache_preload_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_preload_size_reg_t;
-
-
-/** Group: Autoload Control and configuration registers */
-/** Type of l1_icache0_autoload_ctrl register
- *  L1 instruction Cache 0 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache0_autoload_ena:1;
-        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_autoload_done:1;
-        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache0_autoload_order:1;
-        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache0_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct0_ena:1;
-        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct1_ena:1;
-        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 autoload.
-         */
-        uint32_t l1_icache0_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_ctrl_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_addr register
- *  L1 instruction Cache 0 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section for
-         *  autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_size register
- *  L1 instruction Cache 0 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_addr register
- *  L1 instruction Cache 0 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section for
-         *  autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_size register
- *  L1 instruction Cache 0 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache1_autoload_ctrl register
- *  L1 instruction Cache 1 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache1_autoload_ena:1;
-        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_autoload_done:1;
-        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache1_autoload_order:1;
-        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache1_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct0_ena:1;
-        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct1_ena:1;
-        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 autoload.
-         */
-        uint32_t l1_icache1_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_ctrl_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_addr register
- *  L1 instruction Cache 1 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section for
-         *  autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_size register
- *  L1 instruction Cache 1 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_addr register
- *  L1 instruction Cache 1 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section for
-         *  autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_size register
- *  L1 instruction Cache 1 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache2_autoload_ctrl register
- *  L1 instruction Cache 2 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache2_autoload_ena:1;
-        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache2_autoload_done:1;
-        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache2_autoload_order:1;
-        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache2_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct0_ena:1;
-        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct1_ena:1;
-        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 autoload.
-         */
-        uint32_t l1_icache2_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_ctrl_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_addr register
- *  L1 instruction Cache 2 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section for
-         *  autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_size register
- *  L1 instruction Cache 2 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_addr register
- *  L1 instruction Cache 2 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section for
-         *  autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_size register
- *  L1 instruction Cache 2 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache3_autoload_ctrl register
- *  L1 instruction Cache 3 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache3_autoload_ena:1;
-        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache3_autoload_done:1;
-        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache3_autoload_order:1;
-        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache3_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct0_ena:1;
-        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct1_ena:1;
-        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 autoload.
-         */
-        uint32_t l1_icache3_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_ctrl_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_addr register
- *  L1 instruction Cache 3 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section for
-         *  autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_size register
- *  L1 instruction Cache 3 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_addr register
- *  L1 instruction Cache 3 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section for
-         *  autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_size register
- *  L1 instruction Cache 3 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_ctrl register
- *  L1 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_cache_autoload_ena:1;
-        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_autoload_done:1;
-        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_cache_autoload_order:1;
-        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct0_ena:1;
-        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct1_ena:1;
-        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct2_ena:1;
-        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct3_ena:1;
-        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l1 cache autoload.
-         */
-        uint32_t l1_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_ctrl_reg_t;
-
-/** Type of l1_cache_autoload_sct0_addr register
- *  L1 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct0_size register
- *  L1 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_size : R/W; bitpos: [24:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_size:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct0_size_reg_t;
-
-/** Type of l1_cache_autoload_sct1_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct1_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_size : R/W; bitpos: [24:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_size:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_sct2_addr register
- *  L1 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the third section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct2_size register
- *  L1 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_size : HRO; bitpos: [24:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_size:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct2_size_reg_t;
-
-/** Type of l1_cache_autoload_sct3_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the fourth section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct3_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_size : HRO; bitpos: [24:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_size:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct3_size_reg_t;
-
-/** Type of l2_cache_autoload_ctrl register
- *  L2 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l2_cache_autoload_ena:1;
-        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_autoload_done:1;
-        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l2_cache_autoload_order:1;
-        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l2_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct0_ena:1;
-        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct1_ena:1;
-        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct2_ena:1;
-        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct3_ena:1;
-        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l2 cache autoload.
-         */
-        uint32_t l2_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_sct0_addr register
- *  L2 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the first section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct0_size register
- *  L2 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct0_size_reg_t;
-
-/** Type of l2_cache_autoload_sct1_addr register
- *  L2 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the second section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct1_size register
- *  L2 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct1_size_reg_t;
-
-/** Type of l2_cache_autoload_sct2_addr register
- *  L2 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the third section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct2_size register
- *  L2 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct2_size_reg_t;
-
-/** Type of l2_cache_autoload_sct3_addr register
- *  L2 Cache autoload section 3 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start address of the fourth section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct3_size register
- *  L2 Cache autoload section 3 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct3_size_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of l1_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_ena:1;
-        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_ena:1;
-        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_ena:1;
-        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_ena:1;
-        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_ena:1;
-        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_ena:1;
-        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_ena:1;
-        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_ena:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
-         *  to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_clr:1;
-        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
-         *  to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_clr:1;
-        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_clr:1;
-        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_clr:1;
-        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_clr:1;
-        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_clr:1;
-        /** l1_dbus2_ovf_int_clr : R/W; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_clr:1;
-        /** l1_dbus3_ovf_int_clr : R/W; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_clr:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
-         *  due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_raw:1;
-        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
-         *  due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_raw:1;
-        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
-         *  due to bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_ovf_int_raw:1;
-        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
-         *  due to bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_ovf_int_raw:1;
-        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_raw:1;
-        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_raw:1;
-        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_ovf_int_raw:1;
-        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_ovf_int_raw:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_st:1;
-        /** l1_ibus1_ovf_int_st : RO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_st:1;
-        /** l1_ibus2_ovf_int_st : RO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_st:1;
-        /** l1_ibus3_ovf_int_st : RO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_st:1;
-        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_st:1;
-        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_st:1;
-        /** l1_dbus2_ovf_int_st : RO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_st:1;
-        /** l1_dbus3_ovf_int_st : RO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_st:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l1_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_ena:1;
-        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_ena:1;
-        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_ena:1;
-        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_ena:1;
-        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_ena:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l1_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_clr : WT; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_clr:1;
-        /** l1_icache1_fail_int_clr : WT; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_clr:1;
-        /** l1_icache2_fail_int_clr : WT; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_clr:1;
-        /** l1_icache3_fail_int_clr : WT; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_clr:1;
-        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l1_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_raw:1;
-        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_raw:1;
-        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
-         */
-        uint32_t l1_icache2_fail_int_raw:1;
-        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
-         */
-        uint32_t l1_icache3_fail_int_raw:1;
-        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_raw:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l1_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_st : RO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_int_st:1;
-        /** l1_icache1_fail_int_st : RO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_int_st:1;
-        /** l1_icache2_fail_int_st : RO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_st:1;
-        /** l1_icache3_fail_int_st : RO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_st:1;
-        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
-         *  to cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_st:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_st_reg_t;
-
-/** Type of l1_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache0_pld_done_int_ena:1;
-        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache1_pld_done_int_ena:1;
-        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_ena:1;
-        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_ena:1;
-        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_cache_pld_done_int_ena:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation done.
-         */
-        uint32_t sync_done_int_ena:1;
-        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_ena:1;
-        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_ena:1;
-        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_ena:1;
-        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_ena:1;
-        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_ena:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_ena:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l1_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_clr:1;
-        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_clr:1;
-        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_clr:1;
-        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_clr:1;
-        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l1_cache_pld_done_int_clr:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_clr : WT; bitpos: [6]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
-         *  done.
-         */
-        uint32_t sync_done_int_clr:1;
-        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_clr:1;
-        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_clr:1;
-        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_clr:1;
-        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_clr:1;
-        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
-         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_clr:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_clr : WT; bitpos: [13]; default: 0;
-         *  The bit is used to clear interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_clr:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l1_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache0_pld_done_int_raw:1;
-        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache1_pld_done_int_raw:1;
-        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_raw:1;
-        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_raw:1;
-        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l1_cache_pld_done_int_raw:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
-         */
-        uint32_t sync_done_int_raw:1;
-        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache0_pld_err_int_raw:1;
-        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache1_pld_err_int_raw:1;
-        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_raw:1;
-        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_raw:1;
-        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_err_int_raw:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
-         *  occurs.
-         */
-        uint32_t sync_err_int_raw:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l1_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_st:1;
-        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_st:1;
-        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_st:1;
-        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_st:1;
-        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l1_cache_pld_done_int_st:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_st : RO; bitpos: [6]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when Cache
-         *  sync-operation is done.
-         */
-        uint32_t sync_done_int_st:1;
-        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_st:1;
-        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_st:1;
-        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_st:1;
-        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_st:1;
-        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_st:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_st : RO; bitpos: [13]; default: 0;
-         *  The bit indicates the status of the interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_st:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_int_st_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_ena:1;
-        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_ena:1;
-        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_ena:1;
-        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_ena:1;
-        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_ena:1;
-        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_ena:1;
-        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_ena:1;
-        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_clr:1;
-        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_clr:1;
-        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_clr:1;
-        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_clr:1;
-        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_clr:1;
-        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_clr:1;
-        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_clr:1;
-        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-ICache0.
-         */
-        uint32_t l2_ibus0_ovf_int_raw:1;
-        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-ICache1.
-         */
-        uint32_t l2_ibus1_ovf_int_raw:1;
-        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-ICache2.
-         */
-        uint32_t l2_ibus2_ovf_int_raw:1;
-        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-ICache3.
-         */
-        uint32_t l2_ibus3_ovf_int_raw:1;
-        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-DCache.
-         */
-        uint32_t l2_dbus0_ovf_int_raw:1;
-        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-DCache.
-         */
-        uint32_t l2_dbus1_ovf_int_raw:1;
-        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-DCache.
-         */
-        uint32_t l2_dbus2_ovf_int_raw:1;
-        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-DCache.
-         */
-        uint32_t l2_dbus3_ovf_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_st:1;
-        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_st:1;
-        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_st:1;
-        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_st:1;
-        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_st:1;
-        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_st:1;
-        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_st:1;
-        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l2_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
-         *  l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l2_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
-         *  cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l2_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l2_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
-         *  to l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_int_st_reg_t;
-
-/** Type of l2_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
-         */
-        uint32_t l2_cache_pld_done_int_ena:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_ena:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l2_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l2_cache_pld_done_int_clr:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_clr:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l2_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l2_cache_pld_done_int_raw:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_err_int_raw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l2_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l2_cache_pld_done_int_st:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_st:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_int_st_reg_t;
-
-
-/** Group: Cache Access Fail Configuration register */
-/** Type of l1_cache_acs_fail_ctrl register
- *  Cache Access Fail Configuration register
- */
-typedef union {
-    struct {
-        /** l1_icache0_acs_fail_check_mode : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
-         *  is not propagated to the request, 1: the access fail is propagated to the request
-         */
-        uint32_t l1_icache0_acs_fail_check_mode:1;
-        /** l1_icache1_acs_fail_check_mode : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
-         *  is not propagated to the request, 1: the access fail is propagated to the request
-         */
-        uint32_t l1_icache1_acs_fail_check_mode:1;
-        /** l1_icache2_acs_fail_check_mode : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
-         *  is not propagated to the request, 1: the access fail is propagated to the request
-         */
-        uint32_t l1_icache2_acs_fail_check_mode:1;
-        /** l1_icache3_acs_fail_check_mode : HRO; bitpos: [3]; default: 0;
-         *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
-         *  is not propagated to the request, 1: the access fail is propagated to the request
-         */
-        uint32_t l1_icache3_acs_fail_check_mode:1;
-        /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to configure l1 cache access fail check mode. 0: the access fail is
-         *  not propagated to the request, 1: the access fail is propagated to the request
-         */
-        uint32_t l1_cache_acs_fail_check_mode:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_ctrl_reg_t;
-
-/** Type of l2_cache_acs_fail_ctrl register
- *  Cache Access Fail Configuration register
- */
-typedef union {
-    struct {
-        /** l2_cache_acs_fail_check_mode : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
-         *  not propagated to the request, 1: the access fail is propagated to the request
-         */
-        uint32_t l2_cache_acs_fail_check_mode:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_ctrl_reg_t;
-
-
-/** Group: Access Statistics registers */
-/** Type of l1_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_ena:1;
-        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_ena:1;
-        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_ena:1;
-        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_ena:1;
-        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_ena:1;
-        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_ena:1;
-        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_ena:1;
-        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_ena:1;
-        uint32_t reserved_8:8;
-        /** l1_ibus0_cnt_clr : WT; bitpos: [16]; default: 0;
-         *  The bit is used to clear ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_clr:1;
-        /** l1_ibus1_cnt_clr : WT; bitpos: [17]; default: 0;
-         *  The bit is used to clear ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_clr:1;
-        /** l1_ibus2_cnt_clr : WT; bitpos: [18]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_clr:1;
-        /** l1_ibus3_cnt_clr : WT; bitpos: [19]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_clr:1;
-        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
-         *  The bit is used to clear dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_clr:1;
-        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
-         *  The bit is used to clear dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_clr:1;
-        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_clr:1;
-        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_clr:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l1_ibus0_acs_hit_cnt register
- *  L1-ICache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_miss_cnt register
- *  L1-ICache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_conflict_cnt register
- *  L1-ICache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_nxtlvl_rd_cnt register
- *  L1-ICache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l1_ibus0_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_hit_cnt register
- *  L1-ICache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_miss_cnt register
- *  L1-ICache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_conflict_cnt register
- *  L1-ICache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_nxtlvl_rd_cnt register
- *  L1-ICache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l1_ibus1_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_hit_cnt register
- *  L1-ICache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_miss_cnt register
- *  L1-ICache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_conflict_cnt register
- *  L1-ICache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_nxtlvl_rd_cnt register
- *  L1-ICache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l1_ibus2_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_hit_cnt register
- *  L1-ICache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_miss_cnt register
- *  L1-ICache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_conflict_cnt register
- *  L1-ICache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_nxtlvl_rd_cnt register
- *  L1-ICache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l1_ibus3_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_bus0_acs_hit_cnt register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus0_acs_miss_cnt register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus0_acs_conflict_cnt register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_conflict_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_conflict_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus0 accessing L1-Cache.
-         */
-        uint32_t l1_bus0_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register
- *  L1-DCache bus0 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t;
-
-/** Type of l1_bus1_acs_hit_cnt register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus1_acs_miss_cnt register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus1_acs_conflict_cnt register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register
- *  L1-DCache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus1 accessing L1-Cache.
-         */
-        uint32_t l1_dbus1_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register
- *  L1-DCache bus1 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_dbus1_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_hit_cnt register
- *  L1-DCache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_miss_cnt register
- *  L1-DCache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_conflict_cnt register
- *  L1-DCache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_nxtlvl_rd_cnt register
- *  L1-DCache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus2 accessing L1-Cache.
-         */
-        uint32_t l1_dbus2_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_nxtlvl_wr_cnt register
- *  L1-DCache bus2 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when bus2 accesses L1-Cache.
-         */
-        uint32_t l1_dbus2_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_hit_cnt register
- *  L1-DCache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_miss_cnt register
- *  L1-DCache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_conflict_cnt register
- *  L1-DCache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_nxtlvl_rd_cnt register
- *  L1-DCache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus3 accessing L1-Cache.
-         */
-        uint32_t l1_dbus3_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_nxtlvl_wr_cnt register
- *  L1-DCache bus3 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_dbus3_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t;
-
-/** Type of l2_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_ena:1;
-        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_ena:1;
-        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_ena:1;
-        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_ena:1;
-        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_ena:1;
-        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_ena:1;
-        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_ena:1;
-        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_ena:1;
-        uint32_t reserved_16:8;
-        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
-         *  The bit is used to clear ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_clr:1;
-        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
-         *  The bit is used to clear ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_clr:1;
-        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_clr:1;
-        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_clr:1;
-        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
-         *  The bit is used to clear dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_clr:1;
-        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
-         *  The bit is used to clear dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_clr:1;
-        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_clr:1;
-        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_clr:1;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l2_ibus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache0 accesses
-         *  L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_nxtlvl_rd_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache1 accesses
-         *  L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_nxtlvl_rd_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache2 accesses
-         *  L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_nxtlvl_rd_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache3 accesses
-         *  L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_nxtlvl_rd_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_nxtlvl_rd_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_nxtlvl_wr_cnt register
- *  L2-Cache bus0 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when L1-DCache accesses L2-Cache due
-         *  to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_nxtlvl_rd_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_nxtlvl_wr_cnt register
- *  L2-Cache bus1 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when L1-DCache accesses L2-Cache due
-         *  to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_nxtlvl_rd_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_nxtlvl_wr_cnt register
- *  L2-Cache bus2 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when L1-DCache accesses L2-Cache due
-         *  to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_nxtlvl_rd_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_nxtlvl_rd_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_nxtlvl_wr_cnt register
- *  L2-Cache bus3 WB-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of write back when L1-DCache accesses L2-Cache due
-         *  to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_nxtlvl_wr_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t;
-
-
-/** Group: Access Fail Debug registers */
-/** Type of l1_icache0_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_id:16;
-        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache0_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache0_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_acs_fail_addr_reg_t;
-
-/** Type of l1_icache1_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_id:16;
-        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache1_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache1_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_acs_fail_addr_reg_t;
-
-/** Type of l1_icache2_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_id:16;
-        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache2_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache2_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_acs_fail_addr_reg_t;
-
-/** Type of l1_icache3_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_id:16;
-        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache3_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache3_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_acs_fail_addr_reg_t;
-
-/** Type of l1_dcache_acs_fail_id_attr register
- *  L1-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_id:16;
-        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_dcache_acs_fail_id_attr_reg_t;
-
-/** Type of l1_dcache_acs_fail_addr register
- *  L1-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_acs_fail_addr_reg_t;
-
-/** Type of l2_cache_acs_fail_id_attr register
- *  L2-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_id:16;
-        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
-         *  due to cache accessing L1-Cache.
-         */
-        uint32_t l2_cache_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l2_cache_acs_fail_addr register
- *  L2-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_addr_reg_t;
-
-
-/** Group: Operation Exception registers */
-/** Type of l1_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache0.
-         */
-        uint32_t l1_icache0_pld_err_code:2;
-        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache1.
-         */
-        uint32_t l1_icache1_pld_err_code:2;
-        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_code:2;
-        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_code:2;
-        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-Cache.
-         */
-        uint32_t l1_cache_pld_err_code:2;
-        uint32_t reserved_10:2;
-        /** sync_err_code : RO; bitpos: [13:12]; default: 0;
-         *  The values 0-2 are available which means sync map, command conflict and size are
-         *  error in Cache System.
-         */
-        uint32_t sync_err_code:2;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_exception_reg_t;
-
-/** Type of l2_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:10;
-        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L2-Cache.
-         */
-        uint32_t l2_cache_pld_err_code:2;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_exception_reg_t;
-
-
-/** Group: Sync Reset control and configuration registers */
-/** Type of l1_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache0_sync_rst:1;
-        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache1_sync_rst:1;
-        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_sync_rst:1;
-        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_sync_rst:1;
-        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_cache_sync_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_rst_ctrl_reg_t;
-
-/** Type of l2_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l2_cache_sync_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_rst_ctrl_reg_t;
-
-
-/** Group: Preload Reset control and configuration registers */
-/** Type of l1_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache0_pld_rst:1;
-        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache1_pld_rst:1;
-        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_rst:1;
-        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_rst:1;
-        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_preload_rst_ctrl_reg_t;
-
-/** Type of l2_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_preload_rst_ctrl_reg_t;
-
-
-/** Group: Autoload buffer clear control and configuration registers */
-/** Type of l1_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
-         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
-         *  works in L1-ICache0.
-         */
-        uint32_t l1_icache0_ald_buf_clr:1;
-        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
-         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
-         *  works in L1-ICache1.
-         */
-        uint32_t l1_icache1_ald_buf_clr:1;
-        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_ald_buf_clr:1;
-        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_ald_buf_clr:1;
-        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
-         *  autoload will not work in L1-Cache. This bit should not be active when autoload
-         *  works in L1-Cache.
-         */
-        uint32_t l1_cache_ald_buf_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_buf_clr_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
-         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
-         *  autoload will not work in L2-Cache. This bit should not be active when autoload
-         *  works in L2-Cache.
-         */
-        uint32_t l2_cache_ald_buf_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_buf_clr_ctrl_reg_t;
-
-
-/** Group: Unallocate request buffer clear registers */
-/** Type of l1_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache0_unalloc_clr:1;
-        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache1_unalloc_clr:1;
-        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_unalloc_clr:1;
-        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_unalloc_clr:1;
-        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_cache_unalloc_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_unallocate_buffer_clear_reg_t;
-
-/** Type of l2_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l2_cache_unalloc_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_unallocate_buffer_clear_reg_t;
-
-
-/** Group: Tag and Data Memory Access Control and configuration register */
-/** Type of l1_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_object : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache0_tag_object:1;
-        /** l1_icache1_tag_object : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache1_tag_object:1;
-        /** l1_icache2_tag_object : R/W; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_object:1;
-        /** l1_icache3_tag_object : R/W; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_object:1;
-        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_tag_object:1;
-        uint32_t reserved_5:1;
-        /** l1_icache0_mem_object : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache0_mem_object:1;
-        /** l1_icache1_mem_object : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache1_mem_object:1;
-        /** l1_icache2_mem_object : R/W; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_mem_object:1;
-        /** l1_icache3_mem_object : R/W; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_mem_object:1;
-        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_mem_object:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} cache_l1_cache_object_ctrl_reg_t;
-
-/** Type of l1_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l1_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} cache_l1_cache_way_object_reg_t;
-
-/** Type of l1_cache_addr register
- *  Cache address register
- */
-typedef union {
-    struct {
-        /** l1_cache_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits stores the address which will decide where inside the specified tag
-         *  memory object will be accessed.
-         */
-        uint32_t l1_cache_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_addr_reg_t;
-
-/** Type of l1_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 612;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l1_cache_debug_bus:32;
-    };
-    uint32_t val;
-} cache_l1_cache_debug_bus_reg_t;
-
-/** Type of l2_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
-         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_tag_object:1;
-        uint32_t reserved_6:5;
-        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
-         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_mem_object:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} cache_l2_cache_object_ctrl_reg_t;
-
-/** Type of l2_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l2_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} cache_l2_cache_way_object_reg_t;
-
-/** Type of l2_cache_addr register
- *  Cache address register
- */
-typedef union {
-    struct {
-        /** l2_cache_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits stores the address which will decide where inside the specified tag
-         *  memory object will be accessed.
-         */
-        uint32_t l2_cache_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_addr_reg_t;
-
-/** Type of l2_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l2_cache_debug_bus : R/W; bitpos: [31:0]; default: 964;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l2_cache_debug_bus:32;
-    };
-    uint32_t val;
-} cache_l2_cache_debug_bus_reg_t;
-
-
-/** Group: Split L1 and L2 registers */
-/** Type of level_split0 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split0 : HRO; bitpos: [31:0]; default: 616;
-         *  Reserved
-         */
-        uint32_t level_split0:32;
-    };
-    uint32_t val;
-} cache_level_split0_reg_t;
-
-/** Type of level_split1 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split1 : HRO; bitpos: [31:0]; default: 968;
-         *  Reserved
-         */
-        uint32_t level_split1:32;
-    };
-    uint32_t val;
-} cache_level_split1_reg_t;
-
-
-/** Group: L2 cache access attribute control register */
-/** Type of l2_cache_access_attr_ctrl register
- *  L2 cache access attribute control register
- */
-typedef union {
-    struct {
-        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
-         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
-         *  non-cacheable.
-         */
-        uint32_t l2_cache_access_force_cc:1;
-        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
-         *  write-through.
-         */
-        uint32_t l2_cache_access_force_wb:1;
-        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  write-miss-allocate and write-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_wma:1;
-        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
-         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  read-miss-allocate and read-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_rma:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} cache_l2_cache_access_attr_ctrl_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable clock gate when access all registers in this module.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cache_clock_gate_reg_t;
-
-
-/** Group: Cache Trace Control register */
-/** Type of trace_ena register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** l1_cache_trace_ena : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable L1-Cache trace for the performance counter and fail tracer
-         */
-        uint32_t l1_cache_trace_ena:1;
-        /** l2_cache_trace_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable L2-Cache trace for the performance counter and fail tracer
-         */
-        uint32_t l2_cache_trace_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} cache_trace_ena_reg_t;
-
-
-/** Group: Redundancy  register (Prepare for ECO) */
-/** Type of redundancy_sig0 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig0:32;
-    };
-    uint32_t val;
-} cache_redundancy_sig0_reg_t;
-
-/** Type of redundancy_sig1 register
- *  Cache redundancy signal 1 register
- */
-typedef union {
-    struct {
-        /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig1:32;
-    };
-    uint32_t val;
-} cache_redundancy_sig1_reg_t;
-
-/** Type of redundancy_sig2 register
- *  Cache redundancy signal 2 register
- */
-typedef union {
-    struct {
-        /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig2:32;
-    };
-    uint32_t val;
-} cache_redundancy_sig2_reg_t;
-
-/** Type of redundancy_sig3 register
- *  Cache redundancy signal 3 register
- */
-typedef union {
-    struct {
-        /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig3:32;
-    };
-    uint32_t val;
-} cache_redundancy_sig3_reg_t;
-
-/** Type of redundancy_sig4 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** redcy_sig4 : RO; bitpos: [3:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig4:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} cache_redundancy_sig4_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36774432;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_date_reg_t;
-
-
-typedef struct {
-    volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl;
-    volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl;
-    volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
-    volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
-    volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
-    volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
-    volatile cache_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
-    volatile cache_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
-    volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
-    volatile cache_l1_cache_miss_access_ctrl_reg_t l1_cache_miss_access_ctrl;
-    volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
-    volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
-    volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
-    volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
-    volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
-    volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
-    volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
-    volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
-    volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
-    volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
-    volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
-    volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
-    volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
-    volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
-    volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
-    volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
-    volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
-    volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
-    volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
-    volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
-    volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
-    volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
-    volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
-    volatile cache_lock_ctrl_reg_t lock_ctrl;
-    volatile cache_lock_map_reg_t lock_map;
-    volatile cache_lock_addr_reg_t lock_addr;
-    volatile cache_lock_size_reg_t lock_size;
-    volatile cache_sync_ctrl_reg_t sync_ctrl;
-    volatile cache_sync_map_reg_t sync_map;
-    volatile cache_sync_addr_reg_t sync_addr;
-    volatile cache_sync_size_reg_t sync_size;
-    volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
-    volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
-    volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
-    volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
-    volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
-    volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
-    volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
-    volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
-    volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
-    volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
-    volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
-    volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
-    volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
-    volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
-    volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
-    volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
-    volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
-    volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
-    volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
-    volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
-    volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
-    volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
-    volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
-    volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
-    volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
-    volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
-    volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
-    volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
-    volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
-    volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
-    volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
-    volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
-    volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
-    volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
-    volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
-    volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
-    volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
-    volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
-    volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
-    volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
-    volatile cache_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
-    volatile cache_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
-    volatile cache_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
-    volatile cache_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
-    volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
-    volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
-    volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
-    volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
-    volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl;
-    volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
-    volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
-    volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
-    volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
-    volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
-    volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
-    volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
-    volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
-    volatile cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t l1_ibus0_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
-    volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
-    volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
-    volatile cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t l1_ibus1_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
-    volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
-    volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
-    volatile cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t l1_ibus2_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
-    volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
-    volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
-    volatile cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t l1_ibus3_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
-    volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
-    volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
-    volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt;
-    volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
-    volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
-    volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
-    volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt;
-    volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
-    volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
-    volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
-    volatile cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t l1_dbus2_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t l1_dbus2_acs_nxtlvl_wr_cnt;
-    volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
-    volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
-    volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
-    volatile cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t l1_dbus3_acs_nxtlvl_rd_cnt;
-    volatile cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t l1_dbus3_acs_nxtlvl_wr_cnt;
-    volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
-    volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
-    volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
-    volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
-    volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
-    volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
-    volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
-    volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
-    volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr;
-    volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
-    volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
-    volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
-    volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
-    volatile cache_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
-    volatile cache_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
-    volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
-    volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
-    volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
-    volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
-    volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
-    volatile cache_l1_cache_way_object_reg_t l1_cache_way_object;
-    volatile cache_l1_cache_addr_reg_t l1_cache_addr;
-    volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
-    volatile cache_level_split0_reg_t level_split0;
-    volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl;
-    volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
-    volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
-    volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
-    volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
-    volatile cache_l2_cache_miss_access_ctrl_reg_t l2_cache_miss_access_ctrl;
-    volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
-    volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
-    volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
-    volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
-    volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
-    volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
-    volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
-    volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
-    volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
-    volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size;
-    volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
-    volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
-    volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
-    volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
-    volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
-    volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
-    volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
-    volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
-    volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
-    volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
-    volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
-    volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
-    volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
-    volatile cache_l2_cache_acs_fail_ctrl_reg_t l2_cache_acs_fail_ctrl;
-    volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
-    volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
-    volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
-    volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
-    volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
-    volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
-    volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
-    volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
-    volatile cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t l2_ibus0_acs_nxtlvl_rd_cnt;
-    volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
-    volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
-    volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
-    volatile cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t l2_ibus1_acs_nxtlvl_rd_cnt;
-    volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
-    volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
-    volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
-    volatile cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t l2_ibus2_acs_nxtlvl_rd_cnt;
-    volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
-    volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
-    volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
-    volatile cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t l2_ibus3_acs_nxtlvl_rd_cnt;
-    volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
-    volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
-    volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
-    volatile cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t l2_dbus0_acs_nxtlvl_rd_cnt;
-    volatile cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t l2_dbus0_acs_nxtlvl_wr_cnt;
-    volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
-    volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
-    volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
-    volatile cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t l2_dbus1_acs_nxtlvl_rd_cnt;
-    volatile cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t l2_dbus1_acs_nxtlvl_wr_cnt;
-    volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
-    volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
-    volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
-    volatile cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t l2_dbus2_acs_nxtlvl_rd_cnt;
-    volatile cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t l2_dbus2_acs_nxtlvl_wr_cnt;
-    volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
-    volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
-    volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
-    volatile cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t l2_dbus3_acs_nxtlvl_rd_cnt;
-    volatile cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t l2_dbus3_acs_nxtlvl_wr_cnt;
-    volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
-    volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
-    volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
-    volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
-    volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
-    volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
-    volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
-    volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
-    volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
-    volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
-    volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
-    volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
-    volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
-    volatile cache_l2_cache_way_object_reg_t l2_cache_way_object;
-    volatile cache_l2_cache_addr_reg_t l2_cache_addr;
-    volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
-    volatile cache_level_split1_reg_t level_split1;
-    volatile cache_clock_gate_reg_t clock_gate;
-    volatile cache_trace_ena_reg_t trace_ena;
-    volatile cache_redundancy_sig0_reg_t redundancy_sig0;
-    volatile cache_redundancy_sig1_reg_t redundancy_sig1;
-    volatile cache_redundancy_sig2_reg_t redundancy_sig2;
-    volatile cache_redundancy_sig3_reg_t redundancy_sig3;
-    volatile cache_redundancy_sig4_reg_t redundancy_sig4;
-    uint32_t reserved_3e8[5];
-    volatile cache_date_reg_t date;
-} cache_dev_t;
-
-extern cache_dev_t CACHE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/clk_tree_defs.h b/components/soc/esp32c61/include/soc/clk_tree_defs.h
index dcc5c77717c..fec2e781d5b 100644
--- a/components/soc/esp32c61/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32c61/include/soc/clk_tree_defs.h
@@ -89,9 +89,10 @@ typedef enum {
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1,      /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
     SOC_RTC_FAST_CLK_SRC_XTAL = 2,         /*!< Select XTAL_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
 } soc_rtc_fast_clk_src_t;
 
 /**
@@ -120,6 +121,7 @@ typedef enum {
     SOC_MOD_CLK_RTC_SLOW,                      /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
     // For digital domain: peripherals, WIFI, BLE
     SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
+    SOC_MOD_CLK_PLL_F120M,                     /*!< PLL_F120M_CLK is derived from PLL (clock gating + fixed divider of 4), it has a fixed frequency of 120MHz */
     SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
     SOC_MOD_CLK_SPLL,                          /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */
     SOC_MOD_CLK_XTAL32K,                       /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
@@ -213,13 +215,14 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of I2S
  */
-#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
+#define SOC_I2S_CLKS {I2S_CLK_SRC_PLL_120M, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
 
 /**
  * @brief I2S clock source enum
  */
 typedef enum {
     I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,                /*!< Select PLL_F160M as the default source clock  */
+    I2S_CLK_SRC_PLL_120M = SOC_MOD_CLK_PLL_F120M,               /*!< Select PLL_F120M as the source clock */
     I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M,               /*!< Select PLL_F160M as the source clock */
     I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
     I2S_CLK_SRC_EXTERNAL = -1,                                  /*!< Select external clock as source clock */
diff --git a/components/soc/esp32c61/include/soc/dport_access.h b/components/soc/esp32c61/include/soc/dport_access.h
index 85bdb9e6b8f..feacddca468 100644
--- a/components/soc/esp32c61/include/soc/dport_access.h
+++ b/components/soc/esp32c61/include/soc/dport_access.h
@@ -9,7 +9,6 @@
 
 #include <stdint.h>
 #include "soc.h"
-#include "uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32c61/include/soc/ecdsa_reg.h b/components/soc/esp32c61/include/soc/ecdsa_reg.h
deleted file mode 100644
index aca4b64b199..00000000000
--- a/components/soc/esp32c61/include/soc/ecdsa_reg.h
+++ /dev/null
@@ -1,374 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ECDSA_CONF_REG register
- *  ECDSA configure register
- */
-#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
-/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
- *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
- */
-#define ECDSA_WORK_MODE    0x00000003U
-#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
-#define ECDSA_WORK_MODE_V  0x00000003U
-#define ECDSA_WORK_MODE_S  0
-/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
- *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
- */
-#define ECDSA_ECC_CURVE    (BIT(2))
-#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
-#define ECDSA_ECC_CURVE_V  0x00000001U
-#define ECDSA_ECC_CURVE_S  2
-/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
- *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
- *  written by software.
- */
-#define ECDSA_SOFTWARE_SET_K    (BIT(3))
-#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
-#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
-#define ECDSA_SOFTWARE_SET_K_S  3
-/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
- *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
- *  software.
- */
-#define ECDSA_SOFTWARE_SET_Z    (BIT(4))
-#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
-#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
-#define ECDSA_SOFTWARE_SET_Z_S  4
-/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
- *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
- *  deterministic derivation algorithm.
- */
-#define ECDSA_DETERMINISTIC_K    (BIT(5))
-#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
-#define ECDSA_DETERMINISTIC_K_V  0x00000001U
-#define ECDSA_DETERMINISTIC_K_S  5
-/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
- *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
- */
-#define ECDSA_DETERMINISTIC_LOOP    0x0000FFFFU
-#define ECDSA_DETERMINISTIC_LOOP_M  (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
-#define ECDSA_DETERMINISTIC_LOOP_V  0x0000FFFFU
-#define ECDSA_DETERMINISTIC_LOOP_S  6
-
-/** ECDSA_CLK_REG register
- *  ECDSA clock gate register
- */
-#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
-/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  Write 1 to force on register clock gate.
- */
-#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
-#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
-#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
-#define ECDSA_CLK_GATE_FORCE_ON_S  0
-
-/** ECDSA_INT_RAW_REG register
- *  ECDSA interrupt raw register, valid in level.
- */
-#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
-/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
- */
-#define ECDSA_PREP_DONE_INT_RAW    (BIT(0))
-#define ECDSA_PREP_DONE_INT_RAW_M  (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
-#define ECDSA_PREP_DONE_INT_RAW_V  0x00000001U
-#define ECDSA_PREP_DONE_INT_RAW_S  0
-/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
- */
-#define ECDSA_PROC_DONE_INT_RAW    (BIT(1))
-#define ECDSA_PROC_DONE_INT_RAW_M  (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
-#define ECDSA_PROC_DONE_INT_RAW_V  0x00000001U
-#define ECDSA_PROC_DONE_INT_RAW_S  1
-/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
- */
-#define ECDSA_POST_DONE_INT_RAW    (BIT(2))
-#define ECDSA_POST_DONE_INT_RAW_M  (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
-#define ECDSA_POST_DONE_INT_RAW_V  0x00000001U
-#define ECDSA_POST_DONE_INT_RAW_S  2
-/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(3))
-#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
-#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_RAW_S  3
-
-/** ECDSA_INT_ST_REG register
- *  ECDSA interrupt status register.
- */
-#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
-/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
- */
-#define ECDSA_PREP_DONE_INT_ST    (BIT(0))
-#define ECDSA_PREP_DONE_INT_ST_M  (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
-#define ECDSA_PREP_DONE_INT_ST_V  0x00000001U
-#define ECDSA_PREP_DONE_INT_ST_S  0
-/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
- */
-#define ECDSA_PROC_DONE_INT_ST    (BIT(1))
-#define ECDSA_PROC_DONE_INT_ST_M  (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
-#define ECDSA_PROC_DONE_INT_ST_V  0x00000001U
-#define ECDSA_PROC_DONE_INT_ST_S  1
-/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
- */
-#define ECDSA_POST_DONE_INT_ST    (BIT(2))
-#define ECDSA_POST_DONE_INT_ST_M  (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
-#define ECDSA_POST_DONE_INT_ST_V  0x00000001U
-#define ECDSA_POST_DONE_INT_ST_S  2
-/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_ST    (BIT(3))
-#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
-#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_ST_S  3
-
-/** ECDSA_INT_ENA_REG register
- *  ECDSA interrupt enable register.
- */
-#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
-/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
- */
-#define ECDSA_PREP_DONE_INT_ENA    (BIT(0))
-#define ECDSA_PREP_DONE_INT_ENA_M  (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
-#define ECDSA_PREP_DONE_INT_ENA_V  0x00000001U
-#define ECDSA_PREP_DONE_INT_ENA_S  0
-/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
- */
-#define ECDSA_PROC_DONE_INT_ENA    (BIT(1))
-#define ECDSA_PROC_DONE_INT_ENA_M  (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
-#define ECDSA_PROC_DONE_INT_ENA_V  0x00000001U
-#define ECDSA_PROC_DONE_INT_ENA_S  1
-/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
- */
-#define ECDSA_POST_DONE_INT_ENA    (BIT(2))
-#define ECDSA_POST_DONE_INT_ENA_M  (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
-#define ECDSA_POST_DONE_INT_ENA_V  0x00000001U
-#define ECDSA_POST_DONE_INT_ENA_S  2
-/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(3))
-#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
-#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_ENA_S  3
-
-/** ECDSA_INT_CLR_REG register
- *  ECDSA interrupt clear register.
- */
-#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
-/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecdsa_prep_done_int interrupt
- */
-#define ECDSA_PREP_DONE_INT_CLR    (BIT(0))
-#define ECDSA_PREP_DONE_INT_CLR_M  (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
-#define ECDSA_PREP_DONE_INT_CLR_V  0x00000001U
-#define ECDSA_PREP_DONE_INT_CLR_S  0
-/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the ecdsa_proc_done_int interrupt
- */
-#define ECDSA_PROC_DONE_INT_CLR    (BIT(1))
-#define ECDSA_PROC_DONE_INT_CLR_M  (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
-#define ECDSA_PROC_DONE_INT_CLR_V  0x00000001U
-#define ECDSA_PROC_DONE_INT_CLR_S  1
-/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the ecdsa_post_done_int interrupt
- */
-#define ECDSA_POST_DONE_INT_CLR    (BIT(2))
-#define ECDSA_POST_DONE_INT_CLR_M  (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
-#define ECDSA_POST_DONE_INT_CLR_V  0x00000001U
-#define ECDSA_POST_DONE_INT_CLR_S  2
-/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(3))
-#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
-#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_CLR_S  3
-
-/** ECDSA_START_REG register
- *  ECDSA start register
- */
-#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
-/** ECDSA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
- *  after configuration.
- */
-#define ECDSA_START    (BIT(0))
-#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
-#define ECDSA_START_V  0x00000001U
-#define ECDSA_START_S  0
-/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
- *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
- *  self-cleared after configuration.
- */
-#define ECDSA_LOAD_DONE    (BIT(1))
-#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
-#define ECDSA_LOAD_DONE_V  0x00000001U
-#define ECDSA_LOAD_DONE_S  1
-/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
- *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
- *  self-cleared after configuration.
- */
-#define ECDSA_GET_DONE    (BIT(2))
-#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
-#define ECDSA_GET_DONE_V  0x00000001U
-#define ECDSA_GET_DONE_S  2
-
-/** ECDSA_STATE_REG register
- *  ECDSA status register
- */
-#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
-/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
- *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
- *  state.
- */
-#define ECDSA_BUSY    0x00000003U
-#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
-#define ECDSA_BUSY_V  0x00000003U
-#define ECDSA_BUSY_S  0
-
-/** ECDSA_RESULT_REG register
- *  ECDSA result register
- */
-#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
-/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
- *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
- *  done.
- */
-#define ECDSA_OPERATION_RESULT    (BIT(0))
-#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
-#define ECDSA_OPERATION_RESULT_V  0x00000001U
-#define ECDSA_OPERATION_RESULT_S  0
-/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
- *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
- *  curve order, then actually taken k = k mod n.
- */
-#define ECDSA_K_VALUE_WARNING    (BIT(1))
-#define ECDSA_K_VALUE_WARNING_M  (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
-#define ECDSA_K_VALUE_WARNING_V  0x00000001U
-#define ECDSA_K_VALUE_WARNING_S  1
-
-/** ECDSA_DATE_REG register
- *  Version control register
- */
-#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
-/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36725040;
- *  ECDSA version control register
- */
-#define ECDSA_DATE    0x0FFFFFFFU
-#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
-#define ECDSA_DATE_V  0x0FFFFFFFU
-#define ECDSA_DATE_S  0
-
-/** ECDSA_SHA_MODE_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
-/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
- *  Others: invalid.
- */
-#define ECDSA_SHA_MODE    0x00000007U
-#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
-#define ECDSA_SHA_MODE_V  0x00000007U
-#define ECDSA_SHA_MODE_S  0
-
-/** ECDSA_SHA_START_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
-/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
- *  bit will be self-cleared after configuration.
- */
-#define ECDSA_SHA_START    (BIT(0))
-#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
-#define ECDSA_SHA_START_V  0x00000001U
-#define ECDSA_SHA_START_S  0
-
-/** ECDSA_SHA_CONTINUE_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
-/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
- *  bit will be self-cleared after configuration.
- */
-#define ECDSA_SHA_CONTINUE    (BIT(0))
-#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
-#define ECDSA_SHA_CONTINUE_V  0x00000001U
-#define ECDSA_SHA_CONTINUE_S  0
-
-/** ECDSA_SHA_BUSY_REG register
- *  ECDSA status register
- */
-#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
-/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
- *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
- *  calculation. 0: SHA is idle.
- */
-#define ECDSA_SHA_BUSY    (BIT(0))
-#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
-#define ECDSA_SHA_BUSY_V  0x00000001U
-#define ECDSA_SHA_BUSY_S  0
-
-/** ECDSA_MESSAGE_MEM register
- *  The memory that stores message.
- */
-#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
-#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
-
-/** ECDSA_R_MEM register
- *  The memory that stores r.
- */
-#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x340)
-#define ECDSA_R_MEM_SIZE_BYTES 32
-
-/** ECDSA_S_MEM register
- *  The memory that stores s.
- */
-#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x360)
-#define ECDSA_S_MEM_SIZE_BYTES 32
-
-/** ECDSA_Z_MEM register
- *  The memory that stores software written z.
- */
-#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x380)
-#define ECDSA_Z_MEM_SIZE_BYTES 32
-
-/** ECDSA_QAX_MEM register
- *  The memory that stores x coordinates of QA or software written k.
- */
-#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x3a0)
-#define ECDSA_QAX_MEM_SIZE_BYTES 32
-
-/** ECDSA_QAY_MEM register
- *  The memory that stores y coordinates of QA.
- */
-#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x3c0)
-#define ECDSA_QAY_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/ecdsa_struct.h b/components/soc/esp32c61/include/soc/ecdsa_struct.h
deleted file mode 100644
index bed383c9da0..00000000000
--- a/components/soc/esp32c61/include/soc/ecdsa_struct.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Data Memory */
-
-/** Group: Configuration registers */
-/** Type of conf register
- *  ECDSA configure register
- */
-typedef union {
-    struct {
-        /** work_mode : R/W; bitpos: [1:0]; default: 0;
-         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
-         *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
-         */
-        uint32_t work_mode:2;
-        /** ecc_curve : R/W; bitpos: [2]; default: 0;
-         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
-         */
-        uint32_t ecc_curve:1;
-        /** software_set_k : R/W; bitpos: [3]; default: 0;
-         *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
-         *  written by software.
-         */
-        uint32_t software_set_k:1;
-        /** software_set_z : R/W; bitpos: [4]; default: 0;
-         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
-         *  software.
-         */
-        uint32_t software_set_z:1;
-        /** deterministic_k : R/W; bitpos: [5]; default: 0;
-         *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
-         *  deterministic derivation algorithm.
-         */
-        uint32_t deterministic_k:1;
-        /** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
-         *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
-         */
-        uint32_t deterministic_loop:16;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} ecdsa_conf_reg_t;
-
-/** Type of start register
- *  ECDSA start register
- */
-typedef union {
-    struct {
-        /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
-         *  after configuration.
-         */
-        uint32_t start:1;
-        /** load_done : WT; bitpos: [1]; default: 0;
-         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
-         *  self-cleared after configuration.
-         */
-        uint32_t load_done:1;
-        /** get_done : WT; bitpos: [2]; default: 0;
-         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
-         *  self-cleared after configuration.
-         */
-        uint32_t get_done:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} ecdsa_start_reg_t;
-
-
-/** Group: Clock and reset registers */
-/** Type of clk register
- *  ECDSA clock gate register
- */
-typedef union {
-    struct {
-        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_gate_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_clk_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  ECDSA interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_raw:1;
-        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_raw:1;
-        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
-         */
-        uint32_t post_done_int_raw:1;
-        /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_raw:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} ecdsa_int_raw_reg_t;
-
-/** Type of int_st register
- *  ECDSA interrupt status register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_st:1;
-        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_st:1;
-        /** post_done_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
-         */
-        uint32_t post_done_int_st:1;
-        /** sha_release_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_st:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} ecdsa_int_st_reg_t;
-
-/** Type of int_ena register
- *  ECDSA interrupt enable register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_ena:1;
-        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_ena:1;
-        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
-         */
-        uint32_t post_done_int_ena:1;
-        /** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} ecdsa_int_ena_reg_t;
-
-/** Type of int_clr register
- *  ECDSA interrupt clear register.
- */
-typedef union {
-    struct {
-        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the ecdsa_prep_done_int interrupt
-         */
-        uint32_t prep_done_int_clr:1;
-        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the ecdsa_proc_done_int interrupt
-         */
-        uint32_t proc_done_int_clr:1;
-        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the ecdsa_post_done_int interrupt
-         */
-        uint32_t post_done_int_clr:1;
-        /** sha_release_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_clr:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} ecdsa_int_clr_reg_t;
-
-
-/** Group: Status registers */
-/** Type of state register
- *  ECDSA status register
- */
-typedef union {
-    struct {
-        /** busy : RO; bitpos: [1:0]; default: 0;
-         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
-         *  state.
-         */
-        uint32_t busy:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_state_reg_t;
-
-
-/** Group: Result registers */
-/** Type of result register
- *  ECDSA result register
- */
-typedef union {
-    struct {
-        /** operation_result : RO/SS; bitpos: [0]; default: 0;
-         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
-         *  done.
-         */
-        uint32_t operation_result:1;
-        /** k_value_warning : RO/SS; bitpos: [1]; default: 0;
-         *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
-         *  curve order, then actually taken k = k mod n.
-         */
-        uint32_t k_value_warning:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_result_reg_t;
-
-
-/** Group: SHA register */
-/** Type of sha_mode register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
-         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
-         *  Others: invalid.
-         */
-        uint32_t sha_mode:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} ecdsa_sha_mode_reg_t;
-
-/** Type of sha_start register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
-         *  bit will be self-cleared after configuration.
-         */
-        uint32_t sha_start:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_start_reg_t;
-
-/** Type of sha_continue register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_continue : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
-         *  bit will be self-cleared after configuration.
-         */
-        uint32_t sha_continue:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_continue_reg_t;
-
-/** Type of sha_busy register
- *  ECDSA status register
- */
-typedef union {
-    struct {
-        /** sha_busy : RO; bitpos: [0]; default: 0;
-         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
-         *  calculation. 0: SHA is idle.
-         */
-        uint32_t sha_busy:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_busy_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36725040;
-         *  ECDSA version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ecdsa_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000;
-    volatile ecdsa_conf_reg_t conf;
-    volatile ecdsa_clk_reg_t clk;
-    volatile ecdsa_int_raw_reg_t int_raw;
-    volatile ecdsa_int_st_reg_t int_st;
-    volatile ecdsa_int_ena_reg_t int_ena;
-    volatile ecdsa_int_clr_reg_t int_clr;
-    volatile ecdsa_start_reg_t start;
-    volatile ecdsa_state_reg_t state;
-    volatile ecdsa_result_reg_t result;
-    uint32_t reserved_028[53];
-    volatile ecdsa_date_reg_t date;
-    uint32_t reserved_100[64];
-    volatile ecdsa_sha_mode_reg_t sha_mode;
-    uint32_t reserved_204[3];
-    volatile ecdsa_sha_start_reg_t sha_start;
-    volatile ecdsa_sha_continue_reg_t sha_continue;
-    volatile ecdsa_sha_busy_reg_t sha_busy;
-    uint32_t reserved_21c[25];
-    volatile uint32_t message[8];
-    uint32_t reserved_2a0[40];
-    volatile uint32_t r[8];
-    volatile uint32_t s[8];
-    volatile uint32_t z[8];
-    volatile uint32_t qax[8];
-    volatile uint32_t qay[8];
-} ecdsa_dev_t;
-
-extern ecdsa_dev_t ECDSA;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ecdsa_dev_t) == 0x3e0, "Invalid size of ecdsa_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/efuse_reg.h b/components/soc/esp32c61/include/soc/efuse_reg.h
deleted file mode 100644
index c1eac845a8e..00000000000
--- a/components/soc/esp32c61/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,4047 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Represents pgm_data0
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE0_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Represents pgm_data1
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE0_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Represents pgm_data2
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE0_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Represents pgm_data3
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE0_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Represents pgm_data4
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE0_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Represents pgm_data5
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE0_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Represents pgm_data6
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE0_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Represents pgm_data7
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE0_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Represents pgm_check_value0
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE0_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Represents pgm_check_value1
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE0_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Represents pgm_check_value2
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE0_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS0_REG register
- *  Represents rd_wr_dis
- */
-#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE0_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Represents whether programming of individual eFuse memory bit is disabled or
- *  enabled.\\ 1: Disabled\\ 0: Enabled\\
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE0_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
- *  enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_DIS_ICACHE : RO; bitpos: [7]; default: 0;
- *  Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_ICACHE    (BIT(7))
-#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
-#define EFUSE_DIS_ICACHE_V  0x00000001U
-#define EFUSE_DIS_ICACHE_S  7
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [8]; default: 0;
- *  Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
- *  disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(8))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  8
-/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [9]; default: 0;
- *  Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
- *  enabled\\
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  9
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [10]; default: 0;
- *  Represents whether the function that forces chip into download mode is disabled or
- *  enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(10))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  10
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [11]; default: 0;
- *  Represents whether SPI0 controller during boot_mode_download is disabled or
- *  enabled.\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(11))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  11
-/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [12]; default: 0;
- *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- *  is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
- */
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(12))
-#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
-#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_S  12
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [13]; default: 0;
- *  Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
- *  0: enabled\\
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(13))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  13
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [14]; default: 0;
- *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
- *  mode).\\ 1: disabled\\ 0: enabled\\
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(14))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  14
-/** EFUSE_USB_DREFH : RO; bitpos: [16:15]; default: 0;
- *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFH    0x00000003U
-#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
-#define EFUSE_USB_DREFH_V  0x00000003U
-#define EFUSE_USB_DREFH_S  15
-/** EFUSE_USB_DREFL : RO; bitpos: [18:17]; default: 0;
- *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFL    0x00000003U
-#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
-#define EFUSE_USB_DREFL_V  0x00000003U
-#define EFUSE_USB_DREFL_S  17
-/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [19]; default: 0;
- *  Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not
- *  exchanged\\
- */
-#define EFUSE_USB_EXCHG_PINS    (BIT(19))
-#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
-#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_S  19
-/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [20]; default: 0;
- *  Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not
- *  functioned\\
- */
-#define EFUSE_VDD_SPI_AS_GPIO    (BIT(20))
-#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
-#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_S  20
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [22:21]; default: 0;
- *  Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original
- *  threshold configuration value of STG0 *2 \\1: Original threshold configuration
- *  value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3:
- *  Original threshold configuration value of STG0 *16 \\
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  21
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [25:23]; default: 0;
- *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
- *  1: enabled\\ Even number of 1: disabled\\
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  23
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [26]; default: 0;
- *  Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
- *  enabled\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(26))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  26
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [27]; default: 0;
- *  Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
- *  enabled\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(27))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  27
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [28]; default: 0;
- *  Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
- *  enabled\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(28))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  28
-/** EFUSE_RD_RESERVE_0_61 : RW; bitpos: [31:29]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_61    0x00000007U
-#define EFUSE_RD_RESERVE_0_61_M  (EFUSE_RD_RESERVE_0_61_V << EFUSE_RD_RESERVE_0_61_S)
-#define EFUSE_RD_RESERVE_0_61_V  0x00000007U
-#define EFUSE_RD_RESERVE_0_61_S  29
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE0_BASE + 0x34)
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [3:0]; default: 0;
- *  Represents the purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  0
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [7:4]; default: 0;
- *  Represents the purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  4
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [11:8]; default: 0;
- *  Represents the purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  8
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [15:12]; default: 0;
- *  Represents the purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  12
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [19:16]; default: 0;
- *  Represents the purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  16
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [23:20]; default: 0;
- *  Represents the purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  20
-/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [25:24]; default: 0;
- *  Represents the spa secure level by configuring the clock random divide mode.
- */
-#define EFUSE_SEC_DPA_LEVEL    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
-#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_S  24
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [26]; default: 0;
- *  Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(26))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  26
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [27]; default: 0;
- *  Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
- *  enabled.\\ 0: disabled\\
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(27))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  27
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Represents the flash waiting time after power-up, in unit of ms. When the value
- *  less than 15, the waiting time is programmed value. Otherwise, the waiting time is
- *  2 times the programmed value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE0_BASE + 0x38)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0:
- *  Enable\\
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1.
- *  Disable\\ 0: Enable\\
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [3]; default: 0;
- *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
- *  1: Disable\\ 0: Enable\\
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(3))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  3
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [4]; default: 0;
- *  Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0:
- *  Disable\\
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(4))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  4
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [6:5]; default: 0;
- *  Represents the types of UART printing.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  5
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [7]; default: 0;
- *  Represents whether ROM code is forced to send a resume command during SPI boot.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(7))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  7
-/** EFUSE_SECURE_VERSION : RO; bitpos: [23:8]; default: 0;
- *  Represents the version used by ESP-IDF anti-rollback feature.
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  8
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [24]; default: 0;
- *  Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is
- *  enable.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(24))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  24
-/** EFUSE_HYS_EN_PAD : RO; bitpos: [25]; default: 0;
- *  Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
- *  enabled\\ 0:disabled\\
- */
-#define EFUSE_HYS_EN_PAD    (BIT(25))
-#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
-#define EFUSE_HYS_EN_PAD_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_S  25
-/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [26]; default: 0;
- *  Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0:
- *  Disable\\
- */
-#define EFUSE_XTS_DPA_CLK_ENABLE    (BIT(26))
-#define EFUSE_XTS_DPA_CLK_ENABLE_M  (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S)
-#define EFUSE_XTS_DPA_CLK_ENABLE_V  0x00000001U
-#define EFUSE_XTS_DPA_CLK_ENABLE_S  26
-/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0;
- *  Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1:
- *  Low\\ 0: Decided by register configuration\\
- */
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL    0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S)
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V  0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S  27
-/** EFUSE_DIS_WIFI6 : RO; bitpos: [29]; default: 0;
- *  Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is
- *  disable\\ 0: WiFi 6 is enabled.\\
- */
-#define EFUSE_DIS_WIFI6    (BIT(29))
-#define EFUSE_DIS_WIFI6_M  (EFUSE_DIS_WIFI6_V << EFUSE_DIS_WIFI6_S)
-#define EFUSE_DIS_WIFI6_V  0x00000001U
-#define EFUSE_DIS_WIFI6_S  29
-/** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [30]; default: 0;
- *  Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable.
- */
-#define EFUSE_ECDSA_DISABLE_P192    (BIT(30))
-#define EFUSE_ECDSA_DISABLE_P192_M  (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S)
-#define EFUSE_ECDSA_DISABLE_P192_V  0x00000001U
-#define EFUSE_ECDSA_DISABLE_P192_S  30
-/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [31]; default: 0;
- *  Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
- *  \\ 0: Disable.
- */
-#define EFUSE_ECC_FORCE_CONST_TIME    (BIT(31))
-#define EFUSE_ECC_FORCE_CONST_TIME_M  (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S)
-#define EFUSE_ECC_FORCE_CONST_TIME_V  0x00000001U
-#define EFUSE_ECC_FORCE_CONST_TIME_S  31
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE0_BASE + 0x3c)
-/** EFUSE_RD_REPEAT_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RD_REPEAT_DATA3    0xFFFFFFFFU
-#define EFUSE_RD_REPEAT_DATA3_M  (EFUSE_RD_REPEAT_DATA3_V << EFUSE_RD_REPEAT_DATA3_S)
-#define EFUSE_RD_REPEAT_DATA3_V  0xFFFFFFFFU
-#define EFUSE_RD_REPEAT_DATA3_S  0
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  Represents rd_repeat_data
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE0_BASE + 0x40)
-/** EFUSE_RD_REPEAT_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RD_REPEAT_DATA4    0xFFFFFFFFU
-#define EFUSE_RD_REPEAT_DATA4_M  (EFUSE_RD_REPEAT_DATA4_V << EFUSE_RD_REPEAT_DATA4_S)
-#define EFUSE_RD_REPEAT_DATA4_V  0xFFFFFFFFU
-#define EFUSE_RD_REPEAT_DATA4_S  0
-
-/** EFUSE_RD_MAC_SYS0_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE0_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents MAC address. Low 32-bit.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SYS1_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE0_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Represents MAC address. High 16-bit.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_C61_NO_EXTENTION : R; bitpos: [31:16]; default: 0;
- *  Reserved
- */
-#define EFUSE_C61_NO_EXTENTION    0x0000FFFFU
-#define EFUSE_C61_NO_EXTENTION_M  (EFUSE_C61_NO_EXTENTION_V << EFUSE_C61_NO_EXTENTION_S)
-#define EFUSE_C61_NO_EXTENTION_V  0x0000FFFFU
-#define EFUSE_C61_NO_EXTENTION_S  16
-
-/** EFUSE_RD_MAC_SYS2_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE0_BASE + 0x4c)
-/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
- *  Minor chip version
- */
-#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
-#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_S  0
-/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
- *  Major chip version
- */
-#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_S  4
-/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
- *  Disables check of wafer version major
- */
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(6))
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  6
-/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
- *  Disables check of blk version major
- */
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
-/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
- *  BLK_VERSION_MINOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MINOR    0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
-#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_S  8
-/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
- *  BLK_VERSION_MAJOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
-#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_S  11
-/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
- *  Flash capacity
- */
-#define EFUSE_FLASH_CAP    0x00000007U
-#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
-#define EFUSE_FLASH_CAP_V  0x00000007U
-#define EFUSE_FLASH_CAP_S  13
-/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0;
- *  Flash vendor
- */
-#define EFUSE_FLASH_VENDOR    0x00000007U
-#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
-#define EFUSE_FLASH_VENDOR_V  0x00000007U
-#define EFUSE_FLASH_VENDOR_S  16
-/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0;
- *  PSRAM capacity
- */
-#define EFUSE_PSRAM_CAP    0x00000007U
-#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
-#define EFUSE_PSRAM_CAP_V  0x00000007U
-#define EFUSE_PSRAM_CAP_S  19
-/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0;
- *  PSRAM vendor
- */
-#define EFUSE_PSRAM_VENDOR    0x00000003U
-#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
-#define EFUSE_PSRAM_VENDOR_V  0x00000003U
-#define EFUSE_PSRAM_VENDOR_S  22
-/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0;
- *  Temperature
- */
-#define EFUSE_TEMP    0x00000003U
-#define EFUSE_TEMP_M  (EFUSE_TEMP_V << EFUSE_TEMP_S)
-#define EFUSE_TEMP_V  0x00000003U
-#define EFUSE_TEMP_S  24
-/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0;
- *  Package version
- */
-#define EFUSE_PKG_VERSION    0x00000007U
-#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
-#define EFUSE_PKG_VERSION_V  0x00000007U
-#define EFUSE_PKG_VERSION_S  26
-/** EFUSE_RESERVED_1_93 : R; bitpos: [31:29]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_93    0x00000007U
-#define EFUSE_RESERVED_1_93_M  (EFUSE_RESERVED_1_93_V << EFUSE_RESERVED_1_93_S)
-#define EFUSE_RESERVED_1_93_V  0x00000007U
-#define EFUSE_RESERVED_1_93_S  29
-
-/** EFUSE_RD_MAC_SYS3_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE0_BASE + 0x50)
-/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_2    0x0003FFFFU
-#define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
-#define EFUSE_MAC_RESERVED_2_V  0x0003FFFFU
-#define EFUSE_MAC_RESERVED_2_S  0
-/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
- *  Represents the first 14-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
-#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_S  18
-
-/** EFUSE_RD_MAC_SYS4_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE0_BASE + 0x54)
-/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the first 14-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
-#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_S  0
-
-/** EFUSE_RD_MAC_SYS5_REG register
- *  Represents rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE0_BASE + 0x58)
-/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the second 32-bit of zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
-#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Represents rd_sys_part1_data0
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE0_BASE + 0x5c)
-/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Represents rd_sys_part1_data1
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE0_BASE + 0x60)
-/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Represents rd_sys_part1_data2
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE0_BASE + 0x64)
-/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Represents rd_sys_part1_data3
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE0_BASE + 0x68)
-/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Represents rd_sys_part1_data4
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE0_BASE + 0x6c)
-/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_M  (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
-#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Represents rd_sys_part1_data5
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE0_BASE + 0x70)
-/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
-#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Represents rd_sys_part1_data6
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE0_BASE + 0x74)
-/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
-#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Represents rd_sys_part1_data7
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE0_BASE + 0x78)
-/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
-#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_S  0
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Represents rd_usr_data0
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE0_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Represents rd_usr_data1
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE0_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Represents rd_usr_data2
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE0_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Represents rd_usr_data3
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE0_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Represents rd_usr_data4
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE0_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Represents rd_usr_data5
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE0_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of block3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Represents rd_usr_data6
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE0_BASE + 0x94)
-/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_192    0x000000FFU
-#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
-#define EFUSE_RESERVED_3_192_V  0x000000FFU
-#define EFUSE_RESERVED_3_192_S  0
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_S  8
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Represents rd_usr_data7
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE0_BASE + 0x98)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_248    0x000000FFU
-#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
-#define EFUSE_RESERVED_3_248_V  0x000000FFU
-#define EFUSE_RESERVED_3_248_S  24
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Represents rd_key0_data0
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE0_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Represents rd_key0_data1
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE0_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Represents rd_key0_data2
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE0_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Represents rd_key0_data3
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE0_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Represents rd_key0_data4
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE0_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Represents rd_key0_data5
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE0_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Represents rd_key0_data6
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE0_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Represents rd_key0_data7
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE0_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Represents rd_key1_data0
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE0_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Represents rd_key1_data1
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE0_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Represents rd_key1_data2
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE0_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Represents rd_key1_data3
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE0_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Represents rd_key1_data4
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE0_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Represents rd_key1_data5
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE0_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Represents rd_key1_data6
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE0_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Represents rd_key1_data7
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE0_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Represents rd_key2_data0
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE0_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Represents rd_key2_data1
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE0_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Represents rd_key2_data2
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE0_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Represents rd_key2_data3
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE0_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Represents rd_key2_data4
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE0_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Represents rd_key2_data5
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE0_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Represents rd_key2_data6
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE0_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Represents rd_key2_data7
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE0_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Represents rd_key3_data0
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE0_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Represents rd_key3_data1
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE0_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Represents rd_key3_data2
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE0_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Represents rd_key3_data3
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE0_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Represents rd_key3_data4
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE0_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Represents rd_key3_data5
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE0_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Represents rd_key3_data6
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE0_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Represents rd_key3_data7
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE0_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Represents rd_key4_data0
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE0_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Represents rd_key4_data1
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE0_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Represents rd_key4_data2
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE0_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Represents rd_key4_data3
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE0_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Represents rd_key4_data4
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE0_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Represents rd_key4_data5
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE0_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Represents rd_key4_data6
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE0_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Represents rd_key4_data7
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE0_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Represents rd_key5_data0
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE0_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Represents rd_key5_data1
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE0_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Represents rd_key5_data2
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE0_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Represents rd_key5_data3
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE0_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Represents rd_key5_data4
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE0_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Represents rd_key5_data5
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE0_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Represents rd_key5_data6
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE0_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Represents rd_key5_data7
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE0_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of key5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Represents rd_sys_part2_data0
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE0_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Represents rd_sys_part2_data1
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE0_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Represents rd_sys_part2_data2
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE0_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Represents rd_sys_part2_data3
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE0_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Represents rd_sys_part2_data4
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE0_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Represents rd_sys_part2_data5
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE0_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Represents rd_sys_part2_data6
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE0_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Represents rd_sys_part2_data7
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE0_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Represents the zeroth 32-bit of second part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_DATA_ERR0_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE0_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  Represents the programming error of EFUSE_RD_DIS
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [7]; default: 0;
- *  Represents the programming error of EFUSE_DIS_ICACHE
- */
-#define EFUSE_DIS_ICACHE_ERR    (BIT(7))
-#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
-#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_ICACHE_ERR_S  7
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [8]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_JTAG
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(8))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  8
-/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  9
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [10]; default: 0;
- *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(10))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  10
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [11]; default: 0;
- *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(11))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  11
-/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [12]; default: 0;
- *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
- */
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(12))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  12
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [13]; default: 0;
- *  Represents the programming error of EFUSE_DIS_PAD_JTAG
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(13))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  13
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [14]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(14))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  14
-/** EFUSE_USB_DREFH_ERR : RO; bitpos: [16:15]; default: 0;
- *  Represents the programming error of EFUSE_USB_DREFH
- */
-#define EFUSE_USB_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
-#define EFUSE_USB_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DREFH_ERR_S  15
-/** EFUSE_USB_DREFL_ERR : RO; bitpos: [18:17]; default: 0;
- *  Represents the programming error of EFUSE_USB_DREFL
- */
-#define EFUSE_USB_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
-#define EFUSE_USB_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DREFL_ERR_S  17
-/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [19]; default: 0;
- *  Represents the programming error of EFUSE_USB_EXCHG_PINS
- */
-#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(19))
-#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
-#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_ERR_S  19
-/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [20]; default: 0;
- *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
- */
-#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(20))
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  20
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [22:21]; default: 0;
- *  Represents the programming error of EFUSE_WDT_DELAY_SEL
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  21
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [25:23]; default: 0;
- *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  23
-/** EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR : RO; bitpos: [26]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_0
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR    (BIT(26))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_S  26
-/** EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR : RO; bitpos: [27]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_1
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR    (BIT(27))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_S  27
-/** EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR : RO; bitpos: [28]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_2
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR    (BIT(28))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_S  28
-
-/** EFUSE_RD_REPEAT_DATA_ERR1_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE0_BASE + 0x180)
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [3:0]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_0
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  0
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [7:4]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_1
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  4
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [11:8]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_2
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  8
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [15:12]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_3
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  12
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [19:16]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_4
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  16
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [23:20]; default: 0;
- *  Represents the programming error of EFUSE_KEY_PURPOSE_5
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  20
-/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [25:24]; default: 0;
- *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
- */
-#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
-#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_S  24
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [26]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_EN
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(26))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  26
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [27]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(27))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  27
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  Represents the programming error of EFUSE_FLASH_TPUW
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_DATA_ERR2_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE0_BASE + 0x184)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
- */
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [3]; default: 0;
- *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(3))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  3
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [4]; default: 0;
- *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(4))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  4
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [6:5]; default: 0;
- *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  5
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [7]; default: 0;
- *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(7))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  7
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [23:8]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_VERSION
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  8
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [24]; default: 0;
- *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(24))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  24
-/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [25]; default: 0;
- *  Represents the programming error of EFUSE_HYS_EN_PAD
- */
-#define EFUSE_HYS_EN_PAD_ERR    (BIT(25))
-#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
-#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_ERR_S  25
-/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [26]; default: 0;
- *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
- */
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR    (BIT(26))
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M  (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S)
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V  0x00000001U
-#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S  26
-/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0;
- *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
- */
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR    0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S)
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V  0x00000003U
-#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S  27
-/** EFUSE_DIS_WIFI6_ERR : RO; bitpos: [29]; default: 0;
- *  Represents the programming error of EFUSE_DIS_WIFI6
- */
-#define EFUSE_DIS_WIFI6_ERR    (BIT(29))
-#define EFUSE_DIS_WIFI6_ERR_M  (EFUSE_DIS_WIFI6_ERR_V << EFUSE_DIS_WIFI6_ERR_S)
-#define EFUSE_DIS_WIFI6_ERR_V  0x00000001U
-#define EFUSE_DIS_WIFI6_ERR_S  29
-/** EFUSE_ECDSA_DISABLE_P192_ERR : RO; bitpos: [30]; default: 0;
- *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
- */
-#define EFUSE_ECDSA_DISABLE_P192_ERR    (BIT(30))
-#define EFUSE_ECDSA_DISABLE_P192_ERR_M  (EFUSE_ECDSA_DISABLE_P192_ERR_V << EFUSE_ECDSA_DISABLE_P192_ERR_S)
-#define EFUSE_ECDSA_DISABLE_P192_ERR_V  0x00000001U
-#define EFUSE_ECDSA_DISABLE_P192_ERR_S  30
-/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [31]; default: 0;
- *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
- */
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR    (BIT(31))
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M  (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S)
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V  0x00000001U
-#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S  31
-
-/** EFUSE_RD_REPEAT_DATA_ERR3_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE0_BASE + 0x188)
-/** EFUSE_RD_REPEAT_DATA_ERR3 : RO; bitpos: [31:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RD_REPEAT_DATA_ERR3    0xFFFFFFFFU
-#define EFUSE_RD_REPEAT_DATA_ERR3_M  (EFUSE_RD_REPEAT_DATA_ERR3_V << EFUSE_RD_REPEAT_DATA_ERR3_S)
-#define EFUSE_RD_REPEAT_DATA_ERR3_V  0xFFFFFFFFU
-#define EFUSE_RD_REPEAT_DATA_ERR3_S  0
-
-/** EFUSE_RD_REPEAT_DATA_ERR4_REG register
- *  Represents rd_repeat_data_err
- */
-#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE0_BASE + 0x18c)
-/** EFUSE_RD_REPEAT_DATA_ERR4 : RO; bitpos: [31:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RD_REPEAT_DATA_ERR4    0xFFFFFFFFU
-#define EFUSE_RD_REPEAT_DATA_ERR4_M  (EFUSE_RD_REPEAT_DATA_ERR4_V << EFUSE_RD_REPEAT_DATA_ERR4_S)
-#define EFUSE_RD_REPEAT_DATA_ERR4_V  0xFFFFFFFFU
-#define EFUSE_RD_REPEAT_DATA_ERR4_S  0
-
-/** EFUSE_RD_RS_DATA_ERR0_REG register
- *  Represents rd_rs_data_err
- */
-#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE0_BASE + 0x190)
-/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_mac_sys
- */
-#define EFUSE_RD_MAC_SYS_ERR_NUM    0x00000007U
-#define EFUSE_RD_MAC_SYS_ERR_NUM_M  (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S)
-#define EFUSE_RD_MAC_SYS_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_MAC_SYS_ERR_NUM_S  0
-/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
- *  of error bytes is over 6.
- */
-#define EFUSE_RD_MAC_SYS_FAIL    (BIT(3))
-#define EFUSE_RD_MAC_SYS_FAIL_M  (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S)
-#define EFUSE_RD_MAC_SYS_FAIL_V  0x00000001U
-#define EFUSE_RD_MAC_SYS_FAIL_S  3
-/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_sys_part1_data
- */
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S)
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S  4
-/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
- *  and the number of error bytes is over 6.
- */
-#define EFUSE_RD_SYS_PART1_DATA_FAIL    (BIT(7))
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_M  (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S)
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_SYS_PART1_DATA_FAIL_S  7
-/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_usr_data
- */
-#define EFUSE_RD_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_USR_DATA_ERR_NUM_M  (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S)
-#define EFUSE_RD_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_USR_DATA_ERR_NUM_S  8
-/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_RD_USR_DATA_FAIL_M  (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S)
-#define EFUSE_RD_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_USR_DATA_FAIL_S  11
-/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key0_data
- */
-#define EFUSE_RD_KEY0_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_M  (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY0_DATA_ERR_NUM_S  12
-/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY0_DATA_FAIL    (BIT(15))
-#define EFUSE_RD_KEY0_DATA_FAIL_M  (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S)
-#define EFUSE_RD_KEY0_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY0_DATA_FAIL_S  15
-/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key1_data
- */
-#define EFUSE_RD_KEY1_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_M  (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY1_DATA_ERR_NUM_S  16
-/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY1_DATA_FAIL    (BIT(19))
-#define EFUSE_RD_KEY1_DATA_FAIL_M  (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S)
-#define EFUSE_RD_KEY1_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY1_DATA_FAIL_S  19
-/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key2_data
- */
-#define EFUSE_RD_KEY2_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_M  (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY2_DATA_ERR_NUM_S  20
-/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY2_DATA_FAIL    (BIT(23))
-#define EFUSE_RD_KEY2_DATA_FAIL_M  (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S)
-#define EFUSE_RD_KEY2_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY2_DATA_FAIL_S  23
-/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key3_data
- */
-#define EFUSE_RD_KEY3_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_M  (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY3_DATA_ERR_NUM_S  24
-/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY3_DATA_FAIL    (BIT(27))
-#define EFUSE_RD_KEY3_DATA_FAIL_M  (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S)
-#define EFUSE_RD_KEY3_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY3_DATA_FAIL_S  27
-/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key4_data
- */
-#define EFUSE_RD_KEY4_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_M  (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY4_DATA_ERR_NUM_S  28
-/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY4_DATA_FAIL    (BIT(31))
-#define EFUSE_RD_KEY4_DATA_FAIL_M  (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S)
-#define EFUSE_RD_KEY4_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY4_DATA_FAIL_S  31
-
-/** EFUSE_RD_RS_DATA_ERR1_REG register
- *  Represents rd_rs_data_err
- */
-#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE0_BASE + 0x194)
-/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_key5_data
- */
-#define EFUSE_RD_KEY5_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_M  (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S)
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_KEY5_DATA_ERR_NUM_S  0
-/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
- *  number of error bytes is over 6.
- */
-#define EFUSE_RD_KEY5_DATA_FAIL    (BIT(3))
-#define EFUSE_RD_KEY5_DATA_FAIL_M  (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S)
-#define EFUSE_RD_KEY5_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_KEY5_DATA_FAIL_S  3
-/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  Represents the error number of registers.\\The value of this signal means the
- *  number of error bytes in rd_sys_part2_data
- */
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM    0x00000007U
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S)
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S  4
-/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0;
- *  Represents error status of register.\\0: Means no failure and that the data of
- *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
- *  and the number of error bytes is over 6.
- */
-#define EFUSE_RD_SYS_PART2_DATA_FAIL    (BIT(7))
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_M  (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S)
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_V  0x00000001U
-#define EFUSE_RD_SYS_PART2_DATA_FAIL_S  7
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE0_BASE + 0x198)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37753088;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE0_BASE + 0x1c8)
-/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit to force enable eFuse register configuration clock signal.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuration register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE0_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A:  programming operation command 0x5AA5: read operation command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
- *  Configures which block to use for ECDSA key output.
- */
-#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
-#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_S  16
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE0_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
- *  The value of OTP_LOAD_SW.
- */
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
-#define EFUSE_OTP_LOAD_SW_V  0x00000001U
-#define EFUSE_OTP_LOAD_SW_S  4
-/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
- *  The value of OTP_VDDQ_C_SYNC2.
- */
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
- *  The value of OTP_STROBE_SW.
- */
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
-#define EFUSE_OTP_STROBE_SW_V  0x00000001U
-#define EFUSE_OTP_STROBE_SW_S  6
-/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
- *  The value of OTP_CSB_SW.
- */
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
-#define EFUSE_OTP_CSB_SW_V  0x00000001U
-#define EFUSE_OTP_CSB_SW_S  7
-/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
- *  The value of OTP_PGENB_SW.
- */
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
-#define EFUSE_OTP_PGENB_SW_V  0x00000001U
-#define EFUSE_OTP_PGENB_SW_S  8
-/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
- *  The value of OTP_VDDQ_IS_SW.
- */
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
- *  Indicates the number of block valid bit.
- */
-#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
- *  Indicates which block is used for ECDSA key output.
- */
-#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
-#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_S  20
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE0_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE0_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE0_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE0_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE0_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE0_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE0_BASE + 0x1ec)
-/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the read hold time.
- */
-#define EFUSE_THR_A    0x000000FFU
-#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
-#define EFUSE_THR_A_V  0x000000FFU
-#define EFUSE_THR_A_S  0
-/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
- *  Configures the read time.
- */
-#define EFUSE_TRD    0x000000FFU
-#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
-#define EFUSE_TRD_V  0x000000FFU
-#define EFUSE_TRD_S  8
-/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
- *  Configures the read setup time.
- */
-#define EFUSE_TSUR_A    0x000000FFU
-#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
-#define EFUSE_TSUR_A_V  0x000000FFU
-#define EFUSE_TSUR_A_S  16
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
- *  Configures the waiting time of reading eFuse memory.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE0_BASE + 0x1f0)
-/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the programming setup time.
- */
-#define EFUSE_TSUP_A    0x000000FFU
-#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
-#define EFUSE_TSUP_A_V  0x000000FFU
-#define EFUSE_TSUP_A_S  0
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
- *  Configures the programming hold time.
- */
-#define EFUSE_THP_A    0x000000FFU
-#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
-#define EFUSE_THP_A_V  0x000000FFU
-#define EFUSE_THP_A_S  24
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE0_BASE + 0x1f4)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200;
- *  Configures the active programming time.
- */
-#define EFUSE_TPGM    0x0000FFFFU
-#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
-#define EFUSE_TPGM_V  0x0000FFFFU
-#define EFUSE_TPGM_S  16
-
-/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE0_BASE + 0x1f8)
-/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
- *  Set this bit to bypass reed solomon correction step.
- */
-#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
-#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
-#define EFUSE_BYPASS_RS_CORRECTION_S  0
-/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
- *  Configures block number of programming twice operation.
- */
-#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
-#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_S  1
-/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
- *  Set this bit to update multi-bit register signals.
- */
-#define EFUSE_UPDATE    (BIT(12))
-#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
-#define EFUSE_UPDATE_V  0x00000001U
-#define EFUSE_UPDATE_S  12
-/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
- *  Configures the inactive programming time.
- */
-#define EFUSE_TPGM_INACTIVE    0x000000FFU
-#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
-#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
-#define EFUSE_TPGM_INACTIVE_S  13
-
-/** EFUSE_APB2OTP_WR_DIS_REG register
- *  eFuse apb2otp block0 data register1.
- */
-#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE0_BASE + 0x500)
-/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 write disable data.
- */
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
- *  eFuse apb2otp block0 data register2.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE0_BASE + 0x504)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
- *  eFuse apb2otp block0 data register3.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE0_BASE + 0x508)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
- *  eFuse apb2otp block0 data register4.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE0_BASE + 0x50c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
- *  eFuse apb2otp block0 data register5.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE0_BASE + 0x510)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
- *  eFuse apb2otp block0 data register6.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE0_BASE + 0x514)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
- *  eFuse apb2otp block0 data register7.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE0_BASE + 0x518)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
- *  eFuse apb2otp block0 data register8.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE0_BASE + 0x51c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
- *  eFuse apb2otp block0 data register9.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE0_BASE + 0x520)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
- *  eFuse apb2otp block0 data register10.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE0_BASE + 0x524)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
- *  eFuse apb2otp block0 data register11.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE0_BASE + 0x528)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
- *  eFuse apb2otp block0 data register12.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE0_BASE + 0x52c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
- *  eFuse apb2otp block0 data register13.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE0_BASE + 0x530)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
- *  eFuse apb2otp block0 data register14.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE0_BASE + 0x534)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
- *  eFuse apb2otp block0 data register15.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE0_BASE + 0x538)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
- *  eFuse apb2otp block0 data register16.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE0_BASE + 0x53c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
- *  eFuse apb2otp block0 data register17.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE0_BASE + 0x540)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
- *  eFuse apb2otp block0 data register18.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE0_BASE + 0x544)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
- *  eFuse apb2otp block0 data register19.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE0_BASE + 0x548)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
- *  eFuse apb2otp block0 data register20.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE0_BASE + 0x54c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
- *  eFuse apb2otp block0 data register21.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE0_BASE + 0x550)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
-
-/** EFUSE_APB2OTP_BLK1_W1_REG register
- *  eFuse apb2otp block1 data register1.
- */
-#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE0_BASE + 0x554)
-/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
-#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W1_S  0
-
-/** EFUSE_APB2OTP_BLK1_W2_REG register
- *  eFuse apb2otp block1 data register2.
- */
-#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE0_BASE + 0x558)
-/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
-#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W2_S  0
-
-/** EFUSE_APB2OTP_BLK1_W3_REG register
- *  eFuse apb2otp block1 data register3.
- */
-#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE0_BASE + 0x55c)
-/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
-#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W3_S  0
-
-/** EFUSE_APB2OTP_BLK1_W4_REG register
- *  eFuse apb2otp block1 data register4.
- */
-#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE0_BASE + 0x560)
-/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
-#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W4_S  0
-
-/** EFUSE_APB2OTP_BLK1_W5_REG register
- *  eFuse apb2otp block1 data register5.
- */
-#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE0_BASE + 0x564)
-/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
-#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W5_S  0
-
-/** EFUSE_APB2OTP_BLK1_W6_REG register
- *  eFuse apb2otp block1 data register6.
- */
-#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE0_BASE + 0x568)
-/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
-#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W6_S  0
-
-/** EFUSE_APB2OTP_BLK1_W7_REG register
- *  eFuse apb2otp block1 data register7.
- */
-#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE0_BASE + 0x56c)
-/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
-#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W7_S  0
-
-/** EFUSE_APB2OTP_BLK1_W8_REG register
- *  eFuse apb2otp block1 data register8.
- */
-#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE0_BASE + 0x570)
-/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
-#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W8_S  0
-
-/** EFUSE_APB2OTP_BLK1_W9_REG register
- *  eFuse apb2otp block1 data register9.
- */
-#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE0_BASE + 0x574)
-/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
-#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W9_S  0
-
-/** EFUSE_APB2OTP_BLK2_W1_REG register
- *  eFuse apb2otp block2 data register1.
- */
-#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE0_BASE + 0x578)
-/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
-#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W1_S  0
-
-/** EFUSE_APB2OTP_BLK2_W2_REG register
- *  eFuse apb2otp block2 data register2.
- */
-#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE0_BASE + 0x57c)
-/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
-#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W2_S  0
-
-/** EFUSE_APB2OTP_BLK2_W3_REG register
- *  eFuse apb2otp block2 data register3.
- */
-#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE0_BASE + 0x580)
-/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
-#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W3_S  0
-
-/** EFUSE_APB2OTP_BLK2_W4_REG register
- *  eFuse apb2otp block2 data register4.
- */
-#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE0_BASE + 0x584)
-/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
-#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W4_S  0
-
-/** EFUSE_APB2OTP_BLK2_W5_REG register
- *  eFuse apb2otp block2 data register5.
- */
-#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE0_BASE + 0x588)
-/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
-#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W5_S  0
-
-/** EFUSE_APB2OTP_BLK2_W6_REG register
- *  eFuse apb2otp block2 data register6.
- */
-#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE0_BASE + 0x58c)
-/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
-#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W6_S  0
-
-/** EFUSE_APB2OTP_BLK2_W7_REG register
- *  eFuse apb2otp block2 data register7.
- */
-#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE0_BASE + 0x590)
-/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
-#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W7_S  0
-
-/** EFUSE_APB2OTP_BLK2_W8_REG register
- *  eFuse apb2otp block2 data register8.
- */
-#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE0_BASE + 0x594)
-/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
-#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W8_S  0
-
-/** EFUSE_APB2OTP_BLK2_W9_REG register
- *  eFuse apb2otp block2 data register9.
- */
-#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE0_BASE + 0x598)
-/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
-#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W9_S  0
-
-/** EFUSE_APB2OTP_BLK2_W10_REG register
- *  eFuse apb2otp block2 data register10.
- */
-#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE0_BASE + 0x59c)
-/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
-#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W10_S  0
-
-/** EFUSE_APB2OTP_BLK2_W11_REG register
- *  eFuse apb2otp block2 data register11.
- */
-#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE0_BASE + 0x5a0)
-/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
-#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W11_S  0
-
-/** EFUSE_APB2OTP_BLK3_W1_REG register
- *  eFuse apb2otp block3 data register1.
- */
-#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE0_BASE + 0x5a4)
-/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
-#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W1_S  0
-
-/** EFUSE_APB2OTP_BLK3_W2_REG register
- *  eFuse apb2otp block3 data register2.
- */
-#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE0_BASE + 0x5a8)
-/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
-#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W2_S  0
-
-/** EFUSE_APB2OTP_BLK3_W3_REG register
- *  eFuse apb2otp block3 data register3.
- */
-#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE0_BASE + 0x5ac)
-/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
-#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W3_S  0
-
-/** EFUSE_APB2OTP_BLK3_W4_REG register
- *  eFuse apb2otp block3 data register4.
- */
-#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE0_BASE + 0x5b0)
-/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
-#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W4_S  0
-
-/** EFUSE_APB2OTP_BLK3_W5_REG register
- *  eFuse apb2otp block3 data register5.
- */
-#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE0_BASE + 0x5b4)
-/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
-#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W5_S  0
-
-/** EFUSE_APB2OTP_BLK3_W6_REG register
- *  eFuse apb2otp block3 data register6.
- */
-#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE0_BASE + 0x5b8)
-/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
-#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W6_S  0
-
-/** EFUSE_APB2OTP_BLK3_W7_REG register
- *  eFuse apb2otp block3 data register7.
- */
-#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE0_BASE + 0x5bc)
-/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
-#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W7_S  0
-
-/** EFUSE_APB2OTP_BLK3_W8_REG register
- *  eFuse apb2otp block3 data register8.
- */
-#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE0_BASE + 0x5c0)
-/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
-#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W8_S  0
-
-/** EFUSE_APB2OTP_BLK3_W9_REG register
- *  eFuse apb2otp block3 data register9.
- */
-#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE0_BASE + 0x5c4)
-/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
-#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W9_S  0
-
-/** EFUSE_APB2OTP_BLK3_W10_REG register
- *  eFuse apb2otp block3 data register10.
- */
-#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE0_BASE + 0x5c8)
-/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
-#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W10_S  0
-
-/** EFUSE_APB2OTP_BLK3_W11_REG register
- *  eFuse apb2otp block3 data register11.
- */
-#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE0_BASE + 0x5cc)
-/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
-#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W11_S  0
-
-/** EFUSE_APB2OTP_BLK4_W1_REG register
- *  eFuse apb2otp BLOCK7 data register1.
- */
-#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE0_BASE + 0x5d0)
-/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
-#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W1_S  0
-
-/** EFUSE_APB2OTP_BLK4_W2_REG register
- *  eFuse apb2otp block4 data register2.
- */
-#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE0_BASE + 0x5d4)
-/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
-#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W2_S  0
-
-/** EFUSE_APB2OTP_BLK4_W3_REG register
- *  eFuse apb2otp block4 data register3.
- */
-#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE0_BASE + 0x5d8)
-/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
-#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W3_S  0
-
-/** EFUSE_APB2OTP_BLK4_W4_REG register
- *  eFuse apb2otp block4 data register4.
- */
-#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE0_BASE + 0x5dc)
-/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
-#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W4_S  0
-
-/** EFUSE_APB2OTP_BLK4_W5_REG register
- *  eFuse apb2otp block4 data register5.
- */
-#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE0_BASE + 0x5e0)
-/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
-#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W5_S  0
-
-/** EFUSE_APB2OTP_BLK4_W6_REG register
- *  eFuse apb2otp block4 data register6.
- */
-#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE0_BASE + 0x5e4)
-/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
-#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W6_S  0
-
-/** EFUSE_APB2OTP_BLK4_W7_REG register
- *  eFuse apb2otp block4 data register7.
- */
-#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE0_BASE + 0x5e8)
-/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
-#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W7_S  0
-
-/** EFUSE_APB2OTP_BLK4_W8_REG register
- *  eFuse apb2otp block4 data register8.
- */
-#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE0_BASE + 0x5ec)
-/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
-#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W8_S  0
-
-/** EFUSE_APB2OTP_BLK4_W9_REG register
- *  eFuse apb2otp block4 data register9.
- */
-#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE0_BASE + 0x5f0)
-/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
-#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W9_S  0
-
-/** EFUSE_APB2OTP_BLK4_W10_REG register
- *  eFuse apb2otp block4 data registe10.
- */
-#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE0_BASE + 0x5f4)
-/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
-#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W10_S  0
-
-/** EFUSE_APB2OTP_BLK4_W11_REG register
- *  eFuse apb2otp block4 data register11.
- */
-#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE0_BASE + 0x5f8)
-/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
-#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W11_S  0
-
-/** EFUSE_APB2OTP_BLK5_W1_REG register
- *  eFuse apb2otp block5 data register1.
- */
-#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE0_BASE + 0x5fc)
-/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
-#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W1_S  0
-
-/** EFUSE_APB2OTP_BLK5_W2_REG register
- *  eFuse apb2otp block5 data register2.
- */
-#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE0_BASE + 0x600)
-/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
-#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W2_S  0
-
-/** EFUSE_APB2OTP_BLK5_W3_REG register
- *  eFuse apb2otp block5 data register3.
- */
-#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE0_BASE + 0x604)
-/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
-#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W3_S  0
-
-/** EFUSE_APB2OTP_BLK5_W4_REG register
- *  eFuse apb2otp block5 data register4.
- */
-#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE0_BASE + 0x608)
-/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
-#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W4_S  0
-
-/** EFUSE_APB2OTP_BLK5_W5_REG register
- *  eFuse apb2otp block5 data register5.
- */
-#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE0_BASE + 0x60c)
-/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
-#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W5_S  0
-
-/** EFUSE_APB2OTP_BLK5_W6_REG register
- *  eFuse apb2otp block5 data register6.
- */
-#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE0_BASE + 0x610)
-/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
-#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W6_S  0
-
-/** EFUSE_APB2OTP_BLK5_W7_REG register
- *  eFuse apb2otp block5 data register7.
- */
-#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE0_BASE + 0x614)
-/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
-#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W7_S  0
-
-/** EFUSE_APB2OTP_BLK5_W8_REG register
- *  eFuse apb2otp block5 data register8.
- */
-#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE0_BASE + 0x618)
-/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
-#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W8_S  0
-
-/** EFUSE_APB2OTP_BLK5_W9_REG register
- *  eFuse apb2otp block5 data register9.
- */
-#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE0_BASE + 0x61c)
-/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
-#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W9_S  0
-
-/** EFUSE_APB2OTP_BLK5_W10_REG register
- *  eFuse apb2otp block5 data register10.
- */
-#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE0_BASE + 0x620)
-/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
-#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W10_S  0
-
-/** EFUSE_APB2OTP_BLK5_W11_REG register
- *  eFuse apb2otp block5 data register11.
- */
-#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE0_BASE + 0x624)
-/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
-#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W11_S  0
-
-/** EFUSE_APB2OTP_BLK6_W1_REG register
- *  eFuse apb2otp block6 data register1.
- */
-#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE0_BASE + 0x628)
-/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
-#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W1_S  0
-
-/** EFUSE_APB2OTP_BLK6_W2_REG register
- *  eFuse apb2otp block6 data register2.
- */
-#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE0_BASE + 0x62c)
-/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
-#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W2_S  0
-
-/** EFUSE_APB2OTP_BLK6_W3_REG register
- *  eFuse apb2otp block6 data register3.
- */
-#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE0_BASE + 0x630)
-/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
-#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W3_S  0
-
-/** EFUSE_APB2OTP_BLK6_W4_REG register
- *  eFuse apb2otp block6 data register4.
- */
-#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE0_BASE + 0x634)
-/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
-#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W4_S  0
-
-/** EFUSE_APB2OTP_BLK6_W5_REG register
- *  eFuse apb2otp block6 data register5.
- */
-#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE0_BASE + 0x638)
-/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
-#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W5_S  0
-
-/** EFUSE_APB2OTP_BLK6_W6_REG register
- *  eFuse apb2otp block6 data register6.
- */
-#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE0_BASE + 0x63c)
-/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
-#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W6_S  0
-
-/** EFUSE_APB2OTP_BLK6_W7_REG register
- *  eFuse apb2otp block6 data register7.
- */
-#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE0_BASE + 0x640)
-/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
-#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W7_S  0
-
-/** EFUSE_APB2OTP_BLK6_W8_REG register
- *  eFuse apb2otp block6 data register8.
- */
-#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE0_BASE + 0x644)
-/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
-#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W8_S  0
-
-/** EFUSE_APB2OTP_BLK6_W9_REG register
- *  eFuse apb2otp block6 data register9.
- */
-#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE0_BASE + 0x648)
-/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
-#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W9_S  0
-
-/** EFUSE_APB2OTP_BLK6_W10_REG register
- *  eFuse apb2otp block6 data register10.
- */
-#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE0_BASE + 0x64c)
-/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
-#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W10_S  0
-
-/** EFUSE_APB2OTP_BLK6_W11_REG register
- *  eFuse apb2otp block6 data register11.
- */
-#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE0_BASE + 0x650)
-/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
-#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W11_S  0
-
-/** EFUSE_APB2OTP_BLK7_W1_REG register
- *  eFuse apb2otp block7 data register1.
- */
-#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE0_BASE + 0x654)
-/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
-#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W1_S  0
-
-/** EFUSE_APB2OTP_BLK7_W2_REG register
- *  eFuse apb2otp block7 data register2.
- */
-#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE0_BASE + 0x658)
-/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
-#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W2_S  0
-
-/** EFUSE_APB2OTP_BLK7_W3_REG register
- *  eFuse apb2otp block7 data register3.
- */
-#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE0_BASE + 0x65c)
-/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
-#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W3_S  0
-
-/** EFUSE_APB2OTP_BLK7_W4_REG register
- *  eFuse apb2otp block7 data register4.
- */
-#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE0_BASE + 0x660)
-/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
-#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W4_S  0
-
-/** EFUSE_APB2OTP_BLK7_W5_REG register
- *  eFuse apb2otp block7 data register5.
- */
-#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE0_BASE + 0x664)
-/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
-#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W5_S  0
-
-/** EFUSE_APB2OTP_BLK7_W6_REG register
- *  eFuse apb2otp block7 data register6.
- */
-#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE0_BASE + 0x668)
-/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
-#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W6_S  0
-
-/** EFUSE_APB2OTP_BLK7_W7_REG register
- *  eFuse apb2otp block7 data register7.
- */
-#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE0_BASE + 0x66c)
-/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
-#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W7_S  0
-
-/** EFUSE_APB2OTP_BLK7_W8_REG register
- *  eFuse apb2otp block7 data register8.
- */
-#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE0_BASE + 0x670)
-/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
-#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W8_S  0
-
-/** EFUSE_APB2OTP_BLK7_W9_REG register
- *  eFuse apb2otp block7 data register9.
- */
-#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE0_BASE + 0x674)
-/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
-#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W9_S  0
-
-/** EFUSE_APB2OTP_BLK7_W10_REG register
- *  eFuse apb2otp block7 data register10.
- */
-#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE0_BASE + 0x678)
-/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
-#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W10_S  0
-
-/** EFUSE_APB2OTP_BLK7_W11_REG register
- *  eFuse apb2otp block7 data register11.
- */
-#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE0_BASE + 0x67c)
-/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
-#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W11_S  0
-
-/** EFUSE_APB2OTP_BLK8_W1_REG register
- *  eFuse apb2otp block8 data register1.
- */
-#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE0_BASE + 0x680)
-/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
-#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W1_S  0
-
-/** EFUSE_APB2OTP_BLK8_W2_REG register
- *  eFuse apb2otp block8 data register2.
- */
-#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE0_BASE + 0x684)
-/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
-#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W2_S  0
-
-/** EFUSE_APB2OTP_BLK8_W3_REG register
- *  eFuse apb2otp block8 data register3.
- */
-#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE0_BASE + 0x688)
-/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
-#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W3_S  0
-
-/** EFUSE_APB2OTP_BLK8_W4_REG register
- *  eFuse apb2otp block8 data register4.
- */
-#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE0_BASE + 0x68c)
-/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
-#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W4_S  0
-
-/** EFUSE_APB2OTP_BLK8_W5_REG register
- *  eFuse apb2otp block8 data register5.
- */
-#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE0_BASE + 0x690)
-/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
-#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W5_S  0
-
-/** EFUSE_APB2OTP_BLK8_W6_REG register
- *  eFuse apb2otp block8 data register6.
- */
-#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE0_BASE + 0x694)
-/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
-#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W6_S  0
-
-/** EFUSE_APB2OTP_BLK8_W7_REG register
- *  eFuse apb2otp block8 data register7.
- */
-#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE0_BASE + 0x698)
-/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
-#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W7_S  0
-
-/** EFUSE_APB2OTP_BLK8_W8_REG register
- *  eFuse apb2otp block8 data register8.
- */
-#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE0_BASE + 0x69c)
-/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
-#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W8_S  0
-
-/** EFUSE_APB2OTP_BLK8_W9_REG register
- *  eFuse apb2otp block8 data register9.
- */
-#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE0_BASE + 0x6a0)
-/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
-#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W9_S  0
-
-/** EFUSE_APB2OTP_BLK8_W10_REG register
- *  eFuse apb2otp block8 data register10.
- */
-#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE0_BASE + 0x6a4)
-/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
-#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W10_S  0
-
-/** EFUSE_APB2OTP_BLK8_W11_REG register
- *  eFuse apb2otp block8 data register11.
- */
-#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE0_BASE + 0x6a8)
-/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
-#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W11_S  0
-
-/** EFUSE_APB2OTP_BLK9_W1_REG register
- *  eFuse apb2otp block9 data register1.
- */
-#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE0_BASE + 0x6ac)
-/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
-#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W1_S  0
-
-/** EFUSE_APB2OTP_BLK9_W2_REG register
- *  eFuse apb2otp block9 data register2.
- */
-#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE0_BASE + 0x6b0)
-/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
-#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W2_S  0
-
-/** EFUSE_APB2OTP_BLK9_W3_REG register
- *  eFuse apb2otp block9 data register3.
- */
-#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE0_BASE + 0x6b4)
-/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
-#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W3_S  0
-
-/** EFUSE_APB2OTP_BLK9_W4_REG register
- *  eFuse apb2otp block9 data register4.
- */
-#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE0_BASE + 0x6b8)
-/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
-#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W4_S  0
-
-/** EFUSE_APB2OTP_BLK9_W5_REG register
- *  eFuse apb2otp block9 data register5.
- */
-#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE0_BASE + 0x6bc)
-/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
-#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W5_S  0
-
-/** EFUSE_APB2OTP_BLK9_W6_REG register
- *  eFuse apb2otp block9 data register6.
- */
-#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE0_BASE + 0x6c0)
-/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
-#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W6_S  0
-
-/** EFUSE_APB2OTP_BLK9_W7_REG register
- *  eFuse apb2otp block9 data register7.
- */
-#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE0_BASE + 0x6c4)
-/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
-#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W7_S  0
-
-/** EFUSE_APB2OTP_BLK9_W8_REG register
- *  eFuse apb2otp block9 data register8.
- */
-#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE0_BASE + 0x6c8)
-/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
-#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W8_S  0
-
-/** EFUSE_APB2OTP_BLK9_W9_REG register
- *  eFuse apb2otp block9 data register9.
- */
-#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE0_BASE + 0x6cc)
-/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
-#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W9_S  0
-
-/** EFUSE_APB2OTP_BLK9_W10_REG register
- *  eFuse apb2otp block9 data register10.
- */
-#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE0_BASE + 0x6d0)
-/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
-#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W10_S  0
-
-/** EFUSE_APB2OTP_BLK9_W11_REG register
- *  eFuse apb2otp block9 data register11.
- */
-#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE0_BASE + 0x6d4)
-/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
-#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W11_S  0
-
-/** EFUSE_APB2OTP_BLK10_W1_REG register
- *  eFuse apb2otp block10 data register1.
- */
-#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE0_BASE + 0x6d8)
-/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
-#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W1_S  0
-
-/** EFUSE_APB2OTP_BLK10_W2_REG register
- *  eFuse apb2otp block10 data register2.
- */
-#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE0_BASE + 0x6dc)
-/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
-#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W2_S  0
-
-/** EFUSE_APB2OTP_BLK10_W3_REG register
- *  eFuse apb2otp block10 data register3.
- */
-#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE0_BASE + 0x6e0)
-/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
-#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W3_S  0
-
-/** EFUSE_APB2OTP_BLK10_W4_REG register
- *  eFuse apb2otp block10 data register4.
- */
-#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE0_BASE + 0x6e4)
-/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
-#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W4_S  0
-
-/** EFUSE_APB2OTP_BLK10_W5_REG register
- *  eFuse apb2otp block10 data register5.
- */
-#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE0_BASE + 0x6e8)
-/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
-#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W5_S  0
-
-/** EFUSE_APB2OTP_BLK10_W6_REG register
- *  eFuse apb2otp block10 data register6.
- */
-#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE0_BASE + 0x6ec)
-/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
-#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W6_S  0
-
-/** EFUSE_APB2OTP_BLK10_W7_REG register
- *  eFuse apb2otp block10 data register7.
- */
-#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE0_BASE + 0x6f0)
-/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
-#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W7_S  0
-
-/** EFUSE_APB2OTP_BLK10_W8_REG register
- *  eFuse apb2otp block10 data register8.
- */
-#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE0_BASE + 0x6f4)
-/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
-#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W8_S  0
-
-/** EFUSE_APB2OTP_BLK10_W9_REG register
- *  eFuse apb2otp block10 data register9.
- */
-#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE0_BASE + 0x6f8)
-/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
-#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W9_S  0
-
-/** EFUSE_APB2OTP_BLK10_W10_REG register
- *  eFuse apb2otp block10 data register10.
- */
-#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE0_BASE + 0x6fc)
-/** EFUSE_APB2OTP_BLOCK10_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W10_M  (EFUSE_APB2OTP_BLOCK10_W10_V << EFUSE_APB2OTP_BLOCK10_W10_S)
-#define EFUSE_APB2OTP_BLOCK10_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W10_S  0
-
-/** EFUSE_APB2OTP_BLK10_W11_REG register
- *  eFuse apb2otp block10 data register11.
- */
-#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE0_BASE + 0x700)
-/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
-#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W11_S  0
-
-/** EFUSE_APB2OTP_EN_REG register
- *  eFuse apb2otp enable configuration register.
- */
-#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE0_BASE + 0x708)
-/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
- *  Apb2otp mode enable signal.
- */
-#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
-#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
-#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
-#define EFUSE_APB2OTP_APB2OTP_EN_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/efuse_struct.h b/components/soc/esp32c61/include/soc/efuse_struct.h
deleted file mode 100644
index 1ae0eb37c39..00000000000
--- a/components/soc/esp32c61/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,4435 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: buffer0 registers */
-/** Type of pgm_data0 register
- *  Represents pgm_data0
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Represents pgm_data1
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Represents pgm_data2
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Represents pgm_data3
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Represents pgm_data4
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Represents pgm_data5
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Represents pgm_data6
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Represents pgm_data7
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-
-/** Group: buffer1 registers */
-/** Type of pgm_check_value0 register
- *  Represents pgm_check_value0
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Represents pgm_check_value1
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Represents pgm_check_value2
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: block0 registers */
-/** Type of rd_wr_dis0 register
- *  Represents rd_wr_dis
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled or
-         *  enabled.\\ 1: Disabled\\ 0: Enabled\\
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis0_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t rd_dis:7;
-        /** dis_icache : RO; bitpos: [7]; default: 0;
-         *  Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t dis_icache:1;
-        /** dis_usb_jtag : RO; bitpos: [8]; default: 0;
-         *  Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
-         *  disabled\\ 0: enabled\\
-         */
-        uint32_t dis_usb_jtag:1;
-        /** dis_usb_serial_jtag : RO; bitpos: [9]; default: 0;
-         *  Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
-         *  enabled\\
-         */
-        uint32_t dis_usb_serial_jtag:1;
-        /** dis_force_download : RO; bitpos: [10]; default: 0;
-         *  Represents whether the function that forces chip into download mode is disabled or
-         *  enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t dis_force_download:1;
-        /** spi_download_mspi_dis : RO; bitpos: [11]; default: 0;
-         *  Represents whether SPI0 controller during boot_mode_download is disabled or
-         *  enabled.\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t spi_download_mspi_dis:1;
-        /** jtag_sel_enable : RO; bitpos: [12]; default: 0;
-         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         *  is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
-         */
-        uint32_t jtag_sel_enable:1;
-        /** dis_pad_jtag : RO; bitpos: [13]; default: 0;
-         *  Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
-         *  0: enabled\\
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [14]; default: 0;
-         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
-         *  mode).\\ 1: disabled\\ 0: enabled\\
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** usb_drefh : RO; bitpos: [16:15]; default: 0;
-         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefh:2;
-        /** usb_drefl : RO; bitpos: [18:17]; default: 0;
-         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefl:2;
-        /** usb_exchg_pins : RO; bitpos: [19]; default: 0;
-         *  Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not
-         *  exchanged\\
-         */
-        uint32_t usb_exchg_pins:1;
-        /** vdd_spi_as_gpio : RO; bitpos: [20]; default: 0;
-         *  Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not
-         *  functioned\\
-         */
-        uint32_t vdd_spi_as_gpio:1;
-        /** wdt_delay_sel : RO; bitpos: [22:21]; default: 0;
-         *  Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original
-         *  threshold configuration value of STG0 *2 \\1: Original threshold configuration
-         *  value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3:
-         *  Original threshold configuration value of STG0 *16 \\
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [25:23]; default: 0;
-         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
-         *  1: enabled\\ Even number of 1: disabled\\
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [26]; default: 0;
-         *  Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
-         *  enabled\\ 0: disabled\\
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [27]; default: 0;
-         *  Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
-         *  enabled\\ 0: disabled\\
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [28]; default: 0;
-         *  Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
-         *  enabled\\ 0: disabled\\
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** rd_reserve_0_61 : RW; bitpos: [31:29]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_61:3;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** key_purpose_0 : RO; bitpos: [3:0]; default: 0;
-         *  Represents the purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [7:4]; default: 0;
-         *  Represents the purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-        /** key_purpose_2 : RO; bitpos: [11:8]; default: 0;
-         *  Represents the purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [15:12]; default: 0;
-         *  Represents the purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [19:16]; default: 0;
-         *  Represents the purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [23:20]; default: 0;
-         *  Represents the purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** sec_dpa_level : RO; bitpos: [25:24]; default: 0;
-         *  Represents the spa secure level by configuring the clock random divide mode.
-         */
-        uint32_t sec_dpa_level:2;
-        /** secure_boot_en : RO; bitpos: [26]; default: 0;
-         *  Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [27]; default: 0;
-         *  Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
-         *  enabled.\\ 0: disabled\\
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Represents the flash waiting time after power-up, in unit of ms. When the value
-         *  less than 15, the waiting time is programmed value. Otherwise, the waiting time is
-         *  2 times the programmed value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0:
-         *  Enable\\
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1.
-         *  Disable\\ 0: Enable\\
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [3]; default: 0;
-         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
-         *  1: Disable\\ 0: Enable\\
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [4]; default: 0;
-         *  Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0:
-         *  Disable\\
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [6:5]; default: 0;
-         *  Represents the types of UART printing.
-         */
-        uint32_t uart_print_control:2;
-        /** force_send_resume : RO; bitpos: [7]; default: 0;
-         *  Represents whether ROM code is forced to send a resume command during SPI boot.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [23:8]; default: 0;
-         *  Represents the version used by ESP-IDF anti-rollback feature.
-         */
-        uint32_t secure_version:16;
-        /** secure_boot_disable_fast_wake : RO; bitpos: [24]; default: 0;
-         *  Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is
-         *  enable.
-         */
-        uint32_t secure_boot_disable_fast_wake:1;
-        /** hys_en_pad : RO; bitpos: [25]; default: 0;
-         *  Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
-         *  enabled\\ 0:disabled\\
-         */
-        uint32_t hys_en_pad:1;
-        /** xts_dpa_clk_enable : RO; bitpos: [26]; default: 0;
-         *  Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0:
-         *  Disable\\
-         */
-        uint32_t xts_dpa_clk_enable:1;
-        /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0;
-         *  Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1:
-         *  Low\\ 0: Decided by register configuration\\
-         */
-        uint32_t xts_dpa_pseudo_level:2;
-        /** dis_wifi6 : RO; bitpos: [29]; default: 0;
-         *  Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is
-         *  disable\\ 0: WiFi 6 is enabled.\\
-         */
-        uint32_t dis_wifi6:1;
-        /** ecdsa_disable_p192 : RO; bitpos: [30]; default: 0;
-         *  Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable.
-         */
-        uint32_t ecdsa_disable_p192:1;
-        /** ecc_force_const_time : RO; bitpos: [31]; default: 0;
-         *  Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
-         *  \\ 0: Disable.
-         */
-        uint32_t ecc_force_const_time:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** rd_repeat_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rd_repeat_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  Represents rd_repeat_data
- */
-typedef union {
-    struct {
-        /** rd_repeat_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rd_repeat_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-
-/** Group: block1 registers */
-/** Type of rd_mac_sys0 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents MAC address. Low 32-bit.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys0_reg_t;
-
-/** Type of rd_mac_sys1 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Represents MAC address. High 16-bit.
-         */
-        uint32_t mac_1:16;
-        /** c61_no_extention : R; bitpos: [31:16]; default: 0;
-         *  Reserved
-         */
-        uint32_t c61_no_extention:16;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys1_reg_t;
-
-/** Type of rd_mac_sys2 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** wafer_version_minor : R; bitpos: [3:0]; default: 0;
-         *  Minor chip version
-         */
-        uint32_t wafer_version_minor:4;
-        /** wafer_version_major : R; bitpos: [5:4]; default: 0;
-         *  Major chip version
-         */
-        uint32_t wafer_version_major:2;
-        /** disable_wafer_version_major : R; bitpos: [6]; default: 0;
-         *  Disables check of wafer version major
-         */
-        uint32_t disable_wafer_version_major:1;
-        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
-         *  Disables check of blk version major
-         */
-        uint32_t disable_blk_version_major:1;
-        /** blk_version_minor : R; bitpos: [10:8]; default: 0;
-         *  BLK_VERSION_MINOR of BLOCK2
-         */
-        uint32_t blk_version_minor:3;
-        /** blk_version_major : R; bitpos: [12:11]; default: 0;
-         *  BLK_VERSION_MAJOR of BLOCK2
-         */
-        uint32_t blk_version_major:2;
-        /** flash_cap : R; bitpos: [15:13]; default: 0;
-         *  Flash capacity
-         */
-        uint32_t flash_cap:3;
-        /** flash_vendor : R; bitpos: [18:16]; default: 0;
-         *  Flash vendor
-         */
-        uint32_t flash_vendor:3;
-        /** psram_cap : R; bitpos: [21:19]; default: 0;
-         *  PSRAM capacity
-         */
-        uint32_t psram_cap:3;
-        /** psram_vendor : R; bitpos: [23:22]; default: 0;
-         *  PSRAM vendor
-         */
-        uint32_t psram_vendor:2;
-        /** temp : R; bitpos: [25:24]; default: 0;
-         *  Temperature
-         */
-        uint32_t temp:2;
-        /** pkg_version : R; bitpos: [28:26]; default: 0;
-         *  Package version
-         */
-        uint32_t pkg_version:3;
-        /** reserved_1_93 : R; bitpos: [31:29]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_93:3;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys2_reg_t;
-
-/** Type of rd_mac_sys3 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_2:18;
-        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
-         *  Represents the first 14-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_0:14;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys3_reg_t;
-
-/** Type of rd_mac_sys4 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the first 14-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_1:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys4_reg_t;
-
-/** Type of rd_mac_sys5 register
- *  Represents rd_mac_sys
- */
-typedef union {
-    struct {
-        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the second 32-bit of zeroth part of system data.
-         */
-        uint32_t sys_data_part0_2:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys5_reg_t;
-
-
-/** Group: block2 registers */
-/** Type of rd_sys_part1_data0 register
- *  Represents rd_sys_part1_data0
- */
-typedef union {
-    struct {
-        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Represents rd_sys_part1_data1
- */
-typedef union {
-    struct {
-        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Represents rd_sys_part1_data2
- */
-typedef union {
-    struct {
-        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Represents rd_sys_part1_data3
- */
-typedef union {
-    struct {
-        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Represents rd_sys_part1_data4
- */
-typedef union {
-    struct {
-        /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Represents rd_sys_part1_data5
- */
-typedef union {
-    struct {
-        /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Represents rd_sys_part1_data6
- */
-typedef union {
-    struct {
-        /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Represents rd_sys_part1_data7
- */
-typedef union {
-    struct {
-        /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of first part of system data.
-         */
-        uint32_t sys_data_part1_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-
-/** Group: block3 registers */
-/** Type of rd_usr_data0 register
- *  Represents rd_usr_data0
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Represents rd_usr_data1
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Represents rd_usr_data2
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Represents rd_usr_data3
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Represents rd_usr_data4
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Represents rd_usr_data5
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of block3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Represents rd_usr_data6
- */
-typedef union {
-    struct {
-        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_192:8;
-        /** custom_mac : R; bitpos: [31:8]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac:24;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Represents rd_usr_data7
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac_1:24;
-        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_248:8;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-
-/** Group: block4 registers */
-/** Type of rd_key0_data0 register
- *  Represents rd_key0_data0
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Represents rd_key0_data1
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Represents rd_key0_data2
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Represents rd_key0_data3
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Represents rd_key0_data4
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Represents rd_key0_data5
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Represents rd_key0_data6
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Represents rd_key0_data7
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-
-/** Group: block5 registers */
-/** Type of rd_key1_data0 register
- *  Represents rd_key1_data0
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Represents rd_key1_data1
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Represents rd_key1_data2
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Represents rd_key1_data3
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Represents rd_key1_data4
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Represents rd_key1_data5
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Represents rd_key1_data6
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Represents rd_key1_data7
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-
-/** Group: block6 registers */
-/** Type of rd_key2_data0 register
- *  Represents rd_key2_data0
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Represents rd_key2_data1
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Represents rd_key2_data2
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Represents rd_key2_data3
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Represents rd_key2_data4
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Represents rd_key2_data5
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Represents rd_key2_data6
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Represents rd_key2_data7
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-
-/** Group: block7 registers */
-/** Type of rd_key3_data0 register
- *  Represents rd_key3_data0
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Represents rd_key3_data1
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Represents rd_key3_data2
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Represents rd_key3_data3
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Represents rd_key3_data4
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Represents rd_key3_data5
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Represents rd_key3_data6
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Represents rd_key3_data7
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-
-/** Group: block8 registers */
-/** Type of rd_key4_data0 register
- *  Represents rd_key4_data0
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Represents rd_key4_data1
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Represents rd_key4_data2
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Represents rd_key4_data3
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Represents rd_key4_data4
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Represents rd_key4_data5
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Represents rd_key4_data6
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Represents rd_key4_data7
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-
-/** Group: block9 registers */
-/** Type of rd_key5_data0 register
- *  Represents rd_key5_data0
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Represents rd_key5_data1
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Represents rd_key5_data2
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Represents rd_key5_data3
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Represents rd_key5_data4
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Represents rd_key5_data5
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Represents rd_key5_data6
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Represents rd_key5_data7
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of key5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-
-/** Group: block10 registers */
-/** Type of rd_sys_part2_data0 register
- *  Represents rd_sys_part2_data0
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Represents rd_sys_part2_data1
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Represents rd_sys_part2_data2
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Represents rd_sys_part2_data3
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Represents rd_sys_part2_data4
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Represents rd_sys_part2_data5
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Represents rd_sys_part2_data6
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Represents rd_sys_part2_data7
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Represents the zeroth 32-bit of second part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-
-/** Group: block0 error report registers */
-/** Type of rd_repeat_data_err0 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Represents the programming error of EFUSE_RD_DIS
-         */
-        uint32_t rd_dis_err:7;
-        /** dis_icache_err : RO; bitpos: [7]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_ICACHE
-         */
-        uint32_t dis_icache_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [8]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_JTAG
-         */
-        uint32_t dis_usb_jtag_err:1;
-        /** dis_usb_serial_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
-         */
-        uint32_t dis_usb_serial_jtag_err:1;
-        /** dis_force_download_err : RO; bitpos: [10]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
-         */
-        uint32_t dis_force_download_err:1;
-        /** spi_download_mspi_dis_err : RO; bitpos: [11]; default: 0;
-         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
-         */
-        uint32_t spi_download_mspi_dis_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [12]; default: 0;
-         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** dis_pad_jtag_err : RO; bitpos: [13]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [14]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_drefh_err : RO; bitpos: [16:15]; default: 0;
-         *  Represents the programming error of EFUSE_USB_DREFH
-         */
-        uint32_t usb_drefh_err:2;
-        /** usb_drefl_err : RO; bitpos: [18:17]; default: 0;
-         *  Represents the programming error of EFUSE_USB_DREFL
-         */
-        uint32_t usb_drefl_err:2;
-        /** usb_exchg_pins_err : RO; bitpos: [19]; default: 0;
-         *  Represents the programming error of EFUSE_USB_EXCHG_PINS
-         */
-        uint32_t usb_exchg_pins_err:1;
-        /** vdd_spi_as_gpio_err : RO; bitpos: [20]; default: 0;
-         *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
-         */
-        uint32_t vdd_spi_as_gpio_err:1;
-        /** wdt_delay_sel_err : RO; bitpos: [22:21]; default: 0;
-         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [25:23]; default: 0;
-         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke_0_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_0
-         */
-        uint32_t secure_boot_key_revoke_0_err:1;
-        /** secure_boot_key_revoke_1_err : RO; bitpos: [27]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_1
-         */
-        uint32_t secure_boot_key_revoke_1_err:1;
-        /** secure_boot_key_revoke_2_err : RO; bitpos: [28]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_2
-         */
-        uint32_t secure_boot_key_revoke_2_err:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err0_reg_t;
-
-/** Type of rd_repeat_data_err1 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** key_purpose_0_err : RO; bitpos: [3:0]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [7:4]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
-         */
-        uint32_t key_purpose_1_err:4;
-        /** key_purpose_2_err : RO; bitpos: [11:8]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [15:12]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [19:16]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [23:20]; default: 0;
-         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
-         */
-        uint32_t key_purpose_5_err:4;
-        /** sec_dpa_level_err : RO; bitpos: [25:24]; default: 0;
-         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
-         */
-        uint32_t sec_dpa_level_err:2;
-        /** secure_boot_en_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [27]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Represents the programming error of EFUSE_FLASH_TPUW
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err1_reg_t;
-
-/** Type of rd_repeat_data_err2 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
-         */
-        uint32_t dis_usb_serial_jtag_rom_print_err:1;
-        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [3]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
-         */
-        uint32_t dis_usb_serial_jtag_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [4]; default: 0;
-         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [6:5]; default: 0;
-         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
-         */
-        uint32_t uart_print_control_err:2;
-        /** force_send_resume_err : RO; bitpos: [7]; default: 0;
-         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [23:8]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_VERSION
-         */
-        uint32_t secure_version_err:16;
-        /** secure_boot_disable_fast_wake_err : RO; bitpos: [24]; default: 0;
-         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
-         */
-        uint32_t secure_boot_disable_fast_wake_err:1;
-        /** hys_en_pad_err : RO; bitpos: [25]; default: 0;
-         *  Represents the programming error of EFUSE_HYS_EN_PAD
-         */
-        uint32_t hys_en_pad_err:1;
-        /** xts_dpa_clk_enable_err : RO; bitpos: [26]; default: 0;
-         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
-         */
-        uint32_t xts_dpa_clk_enable_err:1;
-        /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0;
-         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
-         */
-        uint32_t xts_dpa_pseudo_level_err:2;
-        /** dis_wifi6_err : RO; bitpos: [29]; default: 0;
-         *  Represents the programming error of EFUSE_DIS_WIFI6
-         */
-        uint32_t dis_wifi6_err:1;
-        /** ecdsa_disable_p192_err : RO; bitpos: [30]; default: 0;
-         *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
-         */
-        uint32_t ecdsa_disable_p192_err:1;
-        /** ecc_force_const_time_err : RO; bitpos: [31]; default: 0;
-         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
-         */
-        uint32_t ecc_force_const_time_err:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err2_reg_t;
-
-/** Type of rd_repeat_data_err3 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** rd_repeat_data_err3 : RO; bitpos: [31:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rd_repeat_data_err3:32;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err3_reg_t;
-
-/** Type of rd_repeat_data_err4 register
- *  Represents rd_repeat_data_err
- */
-typedef union {
-    struct {
-        /** rd_repeat_data_err4 : RO; bitpos: [31:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rd_repeat_data_err4:32;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data_err4_reg_t;
-
-
-/** Group: RS block error report registers */
-/** Type of rd_rs_data_err0 register
- *  Represents rd_rs_data_err
- */
-typedef union {
-    struct {
-        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_mac_sys
-         */
-        uint32_t rd_mac_sys_err_num:3;
-        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
-         *  of error bytes is over 6.
-         */
-        uint32_t rd_mac_sys_fail:1;
-        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_sys_part1_data
-         */
-        uint32_t rd_sys_part1_data_err_num:3;
-        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
-         *  and the number of error bytes is over 6.
-         */
-        uint32_t rd_sys_part1_data_fail:1;
-        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_usr_data
-         */
-        uint32_t rd_usr_data_err_num:3;
-        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_usr_data_fail:1;
-        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key0_data
-         */
-        uint32_t rd_key0_data_err_num:3;
-        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key0_data_fail:1;
-        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key1_data
-         */
-        uint32_t rd_key1_data_err_num:3;
-        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key1_data_fail:1;
-        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key2_data
-         */
-        uint32_t rd_key2_data_err_num:3;
-        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key2_data_fail:1;
-        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key3_data
-         */
-        uint32_t rd_key3_data_err_num:3;
-        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key3_data_fail:1;
-        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key4_data
-         */
-        uint32_t rd_key4_data_err_num:3;
-        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key4_data_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_data_err0_reg_t;
-
-/** Type of rd_rs_data_err1 register
- *  Represents rd_rs_data_err
- */
-typedef union {
-    struct {
-        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_key5_data
-         */
-        uint32_t rd_key5_data_err_num:3;
-        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
-         *  number of error bytes is over 6.
-         */
-        uint32_t rd_key5_data_fail:1;
-        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
-         *  Represents the error number of registers.\\The value of this signal means the
-         *  number of error bytes in rd_sys_part2_data
-         */
-        uint32_t rd_sys_part2_data_err_num:3;
-        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
-         *  Represents error status of register.\\0: Means no failure and that the data of
-         *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
-         *  and the number of error bytes is over 6.
-         */
-        uint32_t rd_sys_part2_data_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_data_err1_reg_t;
-
-
-/** Group: EFUSE Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 37753088;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-/** Group: EFUSE Clock Registers */
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to force enable eFuse register configuration clock signal.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-
-/** Group: EFUSE Configure Registers */
-/** Type of conf register
- *  eFuse operation mode configuration register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
-         */
-        uint32_t op_code:16;
-        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
-         *  Configures which block to use for ECDSA key output.
-         */
-        uint32_t cfg_ecdsa_blk:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-
-/** Group: EFUSE Status Registers */
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
-         *  Indicates which block is used for ECDSA key output.
-         */
-        uint32_t cur_ecdsa_blk:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-
-/** Group: EFUSE Command Registers */
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-
-/** Group: EFUSE Configure Registers */
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the read hold time.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures the read time.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures the read setup time.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
-         *  Configures the waiting time of reading eFuse memory.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the programming setup time.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        /** thp_a : R/W; bitpos: [31:24]; default: 1;
-         *  Configures the programming hold time.
-         */
-        uint32_t thp_a:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        /** tpgm : R/W; bitpos: [31:16]; default: 200;
-         *  Configures the active programming time.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-/** Type of wr_tim_conf0_rs_bypass register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-typedef union {
-    struct {
-        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to bypass reed solomon correction step.
-         */
-        uint32_t bypass_rs_correction:1;
-        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
-         *  Configures block number of programming twice operation.
-         */
-        uint32_t bypass_rs_blk_num:11;
-        /** update : WT; bitpos: [12]; default: 0;
-         *  Set this bit to update multi-bit register signals.
-         */
-        uint32_t update:1;
-        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
-         *  Configures the inactive programming time.
-         */
-        uint32_t tpgm_inactive:8;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_rs_bypass_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
-/** Type of apb2otp_wr_dis register
- *  eFuse apb2otp block0 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 write disable data.
-         */
-        uint32_t apb2otp_block0_wr_dis:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_wr_dis_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
-/** Type of apb2otp_blk0_backup1_w1 register
- *  eFuse apb2otp block0 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word1 data.
-         */
-        uint32_t apb2otp_block0_backup1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
-/** Type of apb2otp_blk0_backup1_w2 register
- *  eFuse apb2otp block0 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word2 data.
-         */
-        uint32_t apb2otp_block0_backup1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
-/** Type of apb2otp_blk0_backup1_w3 register
- *  eFuse apb2otp block0 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word3 data.
-         */
-        uint32_t apb2otp_block0_backup1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
-/** Type of apb2otp_blk0_backup1_w4 register
- *  eFuse apb2otp block0 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word4 data.
-         */
-        uint32_t apb2otp_block0_backup1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
-/** Type of apb2otp_blk0_backup1_w5 register
- *  eFuse apb2otp block0 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word5 data.
-         */
-        uint32_t apb2otp_block0_backup1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
-/** Type of apb2otp_blk0_backup2_w1 register
- *  eFuse apb2otp block0 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word1 data.
-         */
-        uint32_t apb2otp_block0_backup2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
-/** Type of apb2otp_blk0_backup2_w2 register
- *  eFuse apb2otp block0 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word2 data.
-         */
-        uint32_t apb2otp_block0_backup2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
-/** Type of apb2otp_blk0_backup2_w3 register
- *  eFuse apb2otp block0 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word3 data.
-         */
-        uint32_t apb2otp_block0_backup2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
-/** Type of apb2otp_blk0_backup2_w4 register
- *  eFuse apb2otp block0 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word4 data.
-         */
-        uint32_t apb2otp_block0_backup2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
-/** Type of apb2otp_blk0_backup2_w5 register
- *  eFuse apb2otp block0 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word5 data.
-         */
-        uint32_t apb2otp_block0_backup2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
-/** Type of apb2otp_blk0_backup3_w1 register
- *  eFuse apb2otp block0 data register12.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word1 data.
-         */
-        uint32_t apb2otp_block0_backup3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
-/** Type of apb2otp_blk0_backup3_w2 register
- *  eFuse apb2otp block0 data register13.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word2 data.
-         */
-        uint32_t apb2otp_block0_backup3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
-/** Type of apb2otp_blk0_backup3_w3 register
- *  eFuse apb2otp block0 data register14.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word3 data.
-         */
-        uint32_t apb2otp_block0_backup3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
-/** Type of apb2otp_blk0_backup3_w4 register
- *  eFuse apb2otp block0 data register15.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word4 data.
-         */
-        uint32_t apb2otp_block0_backup3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
-/** Type of apb2otp_blk0_backup3_w5 register
- *  eFuse apb2otp block0 data register16.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word5 data.
-         */
-        uint32_t apb2otp_block0_backup3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
-/** Type of apb2otp_blk0_backup4_w1 register
- *  eFuse apb2otp block0 data register17.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word1 data.
-         */
-        uint32_t apb2otp_block0_backup4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
-/** Type of apb2otp_blk0_backup4_w2 register
- *  eFuse apb2otp block0 data register18.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word2 data.
-         */
-        uint32_t apb2otp_block0_backup4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
-/** Type of apb2otp_blk0_backup4_w3 register
- *  eFuse apb2otp block0 data register19.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word3 data.
-         */
-        uint32_t apb2otp_block0_backup4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
-/** Type of apb2otp_blk0_backup4_w4 register
- *  eFuse apb2otp block0 data register20.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word4 data.
-         */
-        uint32_t apb2otp_block0_backup4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
-/** Type of apb2otp_blk0_backup4_w5 register
- *  eFuse apb2otp block0 data register21.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word5 data.
-         */
-        uint32_t apb2otp_block0_backup4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word1 Data */
-/** Type of apb2otp_blk1_w1 register
- *  eFuse apb2otp block1 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word1 data.
-         */
-        uint32_t apb2otp_block1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word2 Data */
-/** Type of apb2otp_blk1_w2 register
- *  eFuse apb2otp block1 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word2 data.
-         */
-        uint32_t apb2otp_block1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word3 Data */
-/** Type of apb2otp_blk1_w3 register
- *  eFuse apb2otp block1 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word3 data.
-         */
-        uint32_t apb2otp_block1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word4 Data */
-/** Type of apb2otp_blk1_w4 register
- *  eFuse apb2otp block1 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word4 data.
-         */
-        uint32_t apb2otp_block1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word5 Data */
-/** Type of apb2otp_blk1_w5 register
- *  eFuse apb2otp block1 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word5 data.
-         */
-        uint32_t apb2otp_block1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word6 Data */
-/** Type of apb2otp_blk1_w6 register
- *  eFuse apb2otp block1 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word6 data.
-         */
-        uint32_t apb2otp_block1_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word7 Data */
-/** Type of apb2otp_blk1_w7 register
- *  eFuse apb2otp block1 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word7 data.
-         */
-        uint32_t apb2otp_block1_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word8 Data */
-/** Type of apb2otp_blk1_w8 register
- *  eFuse apb2otp block1 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word8 data.
-         */
-        uint32_t apb2otp_block1_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word9 Data */
-/** Type of apb2otp_blk1_w9 register
- *  eFuse apb2otp block1 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word9 data.
-         */
-        uint32_t apb2otp_block1_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word1 Data */
-/** Type of apb2otp_blk2_w1 register
- *  eFuse apb2otp block2 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word1 data.
-         */
-        uint32_t apb2otp_block2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word2 Data */
-/** Type of apb2otp_blk2_w2 register
- *  eFuse apb2otp block2 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word2 data.
-         */
-        uint32_t apb2otp_block2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word3 Data */
-/** Type of apb2otp_blk2_w3 register
- *  eFuse apb2otp block2 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word3 data.
-         */
-        uint32_t apb2otp_block2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word4 Data */
-/** Type of apb2otp_blk2_w4 register
- *  eFuse apb2otp block2 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word4 data.
-         */
-        uint32_t apb2otp_block2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word5 Data */
-/** Type of apb2otp_blk2_w5 register
- *  eFuse apb2otp block2 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word5 data.
-         */
-        uint32_t apb2otp_block2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word6 Data */
-/** Type of apb2otp_blk2_w6 register
- *  eFuse apb2otp block2 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word6 data.
-         */
-        uint32_t apb2otp_block2_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word7 Data */
-/** Type of apb2otp_blk2_w7 register
- *  eFuse apb2otp block2 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word7 data.
-         */
-        uint32_t apb2otp_block2_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word8 Data */
-/** Type of apb2otp_blk2_w8 register
- *  eFuse apb2otp block2 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word8 data.
-         */
-        uint32_t apb2otp_block2_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word9 Data */
-/** Type of apb2otp_blk2_w9 register
- *  eFuse apb2otp block2 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word9 data.
-         */
-        uint32_t apb2otp_block2_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word10 Data */
-/** Type of apb2otp_blk2_w10 register
- *  eFuse apb2otp block2 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word10 data.
-         */
-        uint32_t apb2otp_block2_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word11 Data */
-/** Type of apb2otp_blk2_w11 register
- *  eFuse apb2otp block2 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word11 data.
-         */
-        uint32_t apb2otp_block2_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word1 Data */
-/** Type of apb2otp_blk3_w1 register
- *  eFuse apb2otp block3 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word1 data.
-         */
-        uint32_t apb2otp_block3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word2 Data */
-/** Type of apb2otp_blk3_w2 register
- *  eFuse apb2otp block3 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word2 data.
-         */
-        uint32_t apb2otp_block3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word3 Data */
-/** Type of apb2otp_blk3_w3 register
- *  eFuse apb2otp block3 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word3 data.
-         */
-        uint32_t apb2otp_block3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word4 Data */
-/** Type of apb2otp_blk3_w4 register
- *  eFuse apb2otp block3 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word4 data.
-         */
-        uint32_t apb2otp_block3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word5 Data */
-/** Type of apb2otp_blk3_w5 register
- *  eFuse apb2otp block3 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word5 data.
-         */
-        uint32_t apb2otp_block3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word6 Data */
-/** Type of apb2otp_blk3_w6 register
- *  eFuse apb2otp block3 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word6 data.
-         */
-        uint32_t apb2otp_block3_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word7 Data */
-/** Type of apb2otp_blk3_w7 register
- *  eFuse apb2otp block3 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word7 data.
-         */
-        uint32_t apb2otp_block3_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word8 Data */
-/** Type of apb2otp_blk3_w8 register
- *  eFuse apb2otp block3 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word8 data.
-         */
-        uint32_t apb2otp_block3_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word9 Data */
-/** Type of apb2otp_blk3_w9 register
- *  eFuse apb2otp block3 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word9 data.
-         */
-        uint32_t apb2otp_block3_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word10 Data */
-/** Type of apb2otp_blk3_w10 register
- *  eFuse apb2otp block3 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word10 data.
-         */
-        uint32_t apb2otp_block3_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word11 Data */
-/** Type of apb2otp_blk3_w11 register
- *  eFuse apb2otp block3 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word11 data.
-         */
-        uint32_t apb2otp_block3_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word1 Data */
-/** Type of apb2otp_blk4_w1 register
- *  eFuse apb2otp BLOCK7 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word1 data.
-         */
-        uint32_t apb2otp_block4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word2 Data */
-/** Type of apb2otp_blk4_w2 register
- *  eFuse apb2otp block4 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word2 data.
-         */
-        uint32_t apb2otp_block4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word3 Data */
-/** Type of apb2otp_blk4_w3 register
- *  eFuse apb2otp block4 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word3 data.
-         */
-        uint32_t apb2otp_block4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word4 Data */
-/** Type of apb2otp_blk4_w4 register
- *  eFuse apb2otp block4 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word4 data.
-         */
-        uint32_t apb2otp_block4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word5 Data */
-/** Type of apb2otp_blk4_w5 register
- *  eFuse apb2otp block4 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word5 data.
-         */
-        uint32_t apb2otp_block4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word6 Data */
-/** Type of apb2otp_blk4_w6 register
- *  eFuse apb2otp block4 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word6 data.
-         */
-        uint32_t apb2otp_block4_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word7 Data */
-/** Type of apb2otp_blk4_w7 register
- *  eFuse apb2otp block4 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word7 data.
-         */
-        uint32_t apb2otp_block4_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word8 Data */
-/** Type of apb2otp_blk4_w8 register
- *  eFuse apb2otp block4 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word8 data.
-         */
-        uint32_t apb2otp_block4_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word9 Data */
-/** Type of apb2otp_blk4_w9 register
- *  eFuse apb2otp block4 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word9 data.
-         */
-        uint32_t apb2otp_block4_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word10 Data */
-/** Type of apb2otp_blk4_w10 register
- *  eFuse apb2otp block4 data registe10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word10 data.
-         */
-        uint32_t apb2otp_block4_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP BLOCK7 Word11 Data */
-/** Type of apb2otp_blk4_w11 register
- *  eFuse apb2otp block4 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word11 data.
-         */
-        uint32_t apb2otp_block4_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word1 Data */
-/** Type of apb2otp_blk5_w1 register
- *  eFuse apb2otp block5 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word1 data.
-         */
-        uint32_t apb2otp_block5_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word2 Data */
-/** Type of apb2otp_blk5_w2 register
- *  eFuse apb2otp block5 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word2 data.
-         */
-        uint32_t apb2otp_block5_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word3 Data */
-/** Type of apb2otp_blk5_w3 register
- *  eFuse apb2otp block5 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word3 data.
-         */
-        uint32_t apb2otp_block5_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word4 Data */
-/** Type of apb2otp_blk5_w4 register
- *  eFuse apb2otp block5 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word4 data.
-         */
-        uint32_t apb2otp_block5_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word5 Data */
-/** Type of apb2otp_blk5_w5 register
- *  eFuse apb2otp block5 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word5 data.
-         */
-        uint32_t apb2otp_block5_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word6 Data */
-/** Type of apb2otp_blk5_w6 register
- *  eFuse apb2otp block5 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word6 data.
-         */
-        uint32_t apb2otp_block5_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word7 Data */
-/** Type of apb2otp_blk5_w7 register
- *  eFuse apb2otp block5 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word7 data.
-         */
-        uint32_t apb2otp_block5_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word8 Data */
-/** Type of apb2otp_blk5_w8 register
- *  eFuse apb2otp block5 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word8 data.
-         */
-        uint32_t apb2otp_block5_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word9 Data */
-/** Type of apb2otp_blk5_w9 register
- *  eFuse apb2otp block5 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word9 data.
-         */
-        uint32_t apb2otp_block5_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word10 Data */
-/** Type of apb2otp_blk5_w10 register
- *  eFuse apb2otp block5 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word10 data.
-         */
-        uint32_t apb2otp_block5_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word11 Data */
-/** Type of apb2otp_blk5_w11 register
- *  eFuse apb2otp block5 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word11 data.
-         */
-        uint32_t apb2otp_block5_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word1 Data */
-/** Type of apb2otp_blk6_w1 register
- *  eFuse apb2otp block6 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word1 data.
-         */
-        uint32_t apb2otp_block6_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word2 Data */
-/** Type of apb2otp_blk6_w2 register
- *  eFuse apb2otp block6 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word2 data.
-         */
-        uint32_t apb2otp_block6_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word3 Data */
-/** Type of apb2otp_blk6_w3 register
- *  eFuse apb2otp block6 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word3 data.
-         */
-        uint32_t apb2otp_block6_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word4 Data */
-/** Type of apb2otp_blk6_w4 register
- *  eFuse apb2otp block6 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word4 data.
-         */
-        uint32_t apb2otp_block6_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word5 Data */
-/** Type of apb2otp_blk6_w5 register
- *  eFuse apb2otp block6 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word5 data.
-         */
-        uint32_t apb2otp_block6_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word6 Data */
-/** Type of apb2otp_blk6_w6 register
- *  eFuse apb2otp block6 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word6 data.
-         */
-        uint32_t apb2otp_block6_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word7 Data */
-/** Type of apb2otp_blk6_w7 register
- *  eFuse apb2otp block6 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word7 data.
-         */
-        uint32_t apb2otp_block6_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word8 Data */
-/** Type of apb2otp_blk6_w8 register
- *  eFuse apb2otp block6 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word8 data.
-         */
-        uint32_t apb2otp_block6_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word9 Data */
-/** Type of apb2otp_blk6_w9 register
- *  eFuse apb2otp block6 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word9 data.
-         */
-        uint32_t apb2otp_block6_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word10 Data */
-/** Type of apb2otp_blk6_w10 register
- *  eFuse apb2otp block6 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word10 data.
-         */
-        uint32_t apb2otp_block6_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word11 Data */
-/** Type of apb2otp_blk6_w11 register
- *  eFuse apb2otp block6 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word11 data.
-         */
-        uint32_t apb2otp_block6_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word1 Data */
-/** Type of apb2otp_blk7_w1 register
- *  eFuse apb2otp block7 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word1 data.
-         */
-        uint32_t apb2otp_block7_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word2 Data */
-/** Type of apb2otp_blk7_w2 register
- *  eFuse apb2otp block7 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word2 data.
-         */
-        uint32_t apb2otp_block7_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word3 Data */
-/** Type of apb2otp_blk7_w3 register
- *  eFuse apb2otp block7 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word3 data.
-         */
-        uint32_t apb2otp_block7_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word4 Data */
-/** Type of apb2otp_blk7_w4 register
- *  eFuse apb2otp block7 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word4 data.
-         */
-        uint32_t apb2otp_block7_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word5 Data */
-/** Type of apb2otp_blk7_w5 register
- *  eFuse apb2otp block7 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word5 data.
-         */
-        uint32_t apb2otp_block7_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word6 Data */
-/** Type of apb2otp_blk7_w6 register
- *  eFuse apb2otp block7 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word6 data.
-         */
-        uint32_t apb2otp_block7_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word7 Data */
-/** Type of apb2otp_blk7_w7 register
- *  eFuse apb2otp block7 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word7 data.
-         */
-        uint32_t apb2otp_block7_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word8 Data */
-/** Type of apb2otp_blk7_w8 register
- *  eFuse apb2otp block7 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word8 data.
-         */
-        uint32_t apb2otp_block7_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word9 Data */
-/** Type of apb2otp_blk7_w9 register
- *  eFuse apb2otp block7 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word9 data.
-         */
-        uint32_t apb2otp_block7_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word10 Data */
-/** Type of apb2otp_blk7_w10 register
- *  eFuse apb2otp block7 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word10 data.
-         */
-        uint32_t apb2otp_block7_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word11 Data */
-/** Type of apb2otp_blk7_w11 register
- *  eFuse apb2otp block7 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word11 data.
-         */
-        uint32_t apb2otp_block7_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word1 Data */
-/** Type of apb2otp_blk8_w1 register
- *  eFuse apb2otp block8 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word1 data.
-         */
-        uint32_t apb2otp_block8_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word2 Data */
-/** Type of apb2otp_blk8_w2 register
- *  eFuse apb2otp block8 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word2 data.
-         */
-        uint32_t apb2otp_block8_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word3 Data */
-/** Type of apb2otp_blk8_w3 register
- *  eFuse apb2otp block8 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word3 data.
-         */
-        uint32_t apb2otp_block8_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word4 Data */
-/** Type of apb2otp_blk8_w4 register
- *  eFuse apb2otp block8 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word4 data.
-         */
-        uint32_t apb2otp_block8_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word5 Data */
-/** Type of apb2otp_blk8_w5 register
- *  eFuse apb2otp block8 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word5 data.
-         */
-        uint32_t apb2otp_block8_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word6 Data */
-/** Type of apb2otp_blk8_w6 register
- *  eFuse apb2otp block8 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word6 data.
-         */
-        uint32_t apb2otp_block8_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word7 Data */
-/** Type of apb2otp_blk8_w7 register
- *  eFuse apb2otp block8 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word7 data.
-         */
-        uint32_t apb2otp_block8_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word8 Data */
-/** Type of apb2otp_blk8_w8 register
- *  eFuse apb2otp block8 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word8 data.
-         */
-        uint32_t apb2otp_block8_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word9 Data */
-/** Type of apb2otp_blk8_w9 register
- *  eFuse apb2otp block8 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word9 data.
-         */
-        uint32_t apb2otp_block8_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word10 Data */
-/** Type of apb2otp_blk8_w10 register
- *  eFuse apb2otp block8 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word10 data.
-         */
-        uint32_t apb2otp_block8_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word11 Data */
-/** Type of apb2otp_blk8_w11 register
- *  eFuse apb2otp block8 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word11 data.
-         */
-        uint32_t apb2otp_block8_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word1 Data */
-/** Type of apb2otp_blk9_w1 register
- *  eFuse apb2otp block9 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word1 data.
-         */
-        uint32_t apb2otp_block9_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word2 Data */
-/** Type of apb2otp_blk9_w2 register
- *  eFuse apb2otp block9 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word2 data.
-         */
-        uint32_t apb2otp_block9_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word3 Data */
-/** Type of apb2otp_blk9_w3 register
- *  eFuse apb2otp block9 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word3 data.
-         */
-        uint32_t apb2otp_block9_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word4 Data */
-/** Type of apb2otp_blk9_w4 register
- *  eFuse apb2otp block9 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word4 data.
-         */
-        uint32_t apb2otp_block9_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word5 Data */
-/** Type of apb2otp_blk9_w5 register
- *  eFuse apb2otp block9 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word5 data.
-         */
-        uint32_t apb2otp_block9_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word6 Data */
-/** Type of apb2otp_blk9_w6 register
- *  eFuse apb2otp block9 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word6 data.
-         */
-        uint32_t apb2otp_block9_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word7 Data */
-/** Type of apb2otp_blk9_w7 register
- *  eFuse apb2otp block9 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word7 data.
-         */
-        uint32_t apb2otp_block9_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word8 Data */
-/** Type of apb2otp_blk9_w8 register
- *  eFuse apb2otp block9 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word8 data.
-         */
-        uint32_t apb2otp_block9_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word9 Data */
-/** Type of apb2otp_blk9_w9 register
- *  eFuse apb2otp block9 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word9 data.
-         */
-        uint32_t apb2otp_block9_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word10 Data */
-/** Type of apb2otp_blk9_w10 register
- *  eFuse apb2otp block9 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word10 data.
-         */
-        uint32_t apb2otp_block9_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word11 Data */
-/** Type of apb2otp_blk9_w11 register
- *  eFuse apb2otp block9 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word11 data.
-         */
-        uint32_t apb2otp_block9_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word1 Data */
-/** Type of apb2otp_blk10_w1 register
- *  eFuse apb2otp block10 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word1 data.
-         */
-        uint32_t apb2otp_block10_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word2 Data */
-/** Type of apb2otp_blk10_w2 register
- *  eFuse apb2otp block10 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word2 data.
-         */
-        uint32_t apb2otp_block10_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word3 Data */
-/** Type of apb2otp_blk10_w3 register
- *  eFuse apb2otp block10 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word3 data.
-         */
-        uint32_t apb2otp_block10_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word4 Data */
-/** Type of apb2otp_blk10_w4 register
- *  eFuse apb2otp block10 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word4 data.
-         */
-        uint32_t apb2otp_block10_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word5 Data */
-/** Type of apb2otp_blk10_w5 register
- *  eFuse apb2otp block10 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word5 data.
-         */
-        uint32_t apb2otp_block10_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word6 Data */
-/** Type of apb2otp_blk10_w6 register
- *  eFuse apb2otp block10 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word6 data.
-         */
-        uint32_t apb2otp_block10_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word7 Data */
-/** Type of apb2otp_blk10_w7 register
- *  eFuse apb2otp block10 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word7 data.
-         */
-        uint32_t apb2otp_block10_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word8 Data */
-/** Type of apb2otp_blk10_w8 register
- *  eFuse apb2otp block10 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word8 data.
-         */
-        uint32_t apb2otp_block10_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word9 Data */
-/** Type of apb2otp_blk10_w9 register
- *  eFuse apb2otp block10 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word9 data.
-         */
-        uint32_t apb2otp_block10_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word10 Data */
-/** Type of apb2otp_blk10_w10 register
- *  eFuse apb2otp block10 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word10 data.
-         */
-        uint32_t apb2otp_block10_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word11 Data */
-/** Type of apb2otp_blk10_w11 register
- *  eFuse apb2otp block10 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word11 data.
-         */
-        uint32_t apb2otp_block10_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Function Enable Signal */
-/** Type of apb2otp_en register
- *  eFuse apb2otp enable configuration register.
- */
-typedef union {
-    struct {
-        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
-         *  Apb2otp mode enable signal.
-         */
-        uint32_t apb2otp_apb2otp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} efuse_apb2otp_en_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
-    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
-    volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2;
-    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
-    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
-    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
-    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
-    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
-    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
-    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
-    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
-    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
-    volatile efuse_date_reg_t date;
-    uint32_t reserved_19c[11];
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
-    uint32_t reserved_1fc[193];
-    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
-    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
-    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
-    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
-    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
-    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
-    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
-    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
-    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
-    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
-    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
-    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
-    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
-    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
-    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
-    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
-    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
-    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
-    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
-    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
-    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
-    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
-    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
-    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
-    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
-    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
-    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
-    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
-    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
-    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
-    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
-    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
-    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
-    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
-    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
-    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
-    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
-    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
-    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
-    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
-    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
-    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
-    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
-    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
-    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
-    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
-    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
-    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
-    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
-    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
-    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
-    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
-    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
-    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
-    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
-    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
-    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
-    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
-    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
-    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
-    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
-    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
-    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
-    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
-    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
-    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
-    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
-    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
-    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
-    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
-    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
-    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
-    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
-    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
-    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
-    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
-    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
-    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
-    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
-    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
-    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
-    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
-    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
-    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
-    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
-    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
-    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
-    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
-    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
-    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
-    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
-    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
-    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
-    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
-    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
-    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
-    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
-    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
-    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
-    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
-    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
-    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
-    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
-    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
-    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
-    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
-    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
-    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
-    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
-    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
-    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
-    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
-    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
-    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
-    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
-    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
-    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
-    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
-    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
-    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
-    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
-    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
-    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
-    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
-    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
-    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
-    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
-    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
-    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
-    uint32_t reserved_704;
-    volatile efuse_apb2otp_en_reg_t apb2otp_en;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE0;
-extern efuse_dev_t EFUSE1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/gpio_num.h b/components/soc/esp32c61/include/soc/gpio_num.h
index 37639ac867a..c92151b7f8f 100644
--- a/components/soc/esp32c61/include/soc/gpio_num.h
+++ b/components/soc/esp32c61/include/soc/gpio_num.h
@@ -37,6 +37,9 @@ typedef enum {
     GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
     GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
     GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
+    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
+    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
+    GPIO_NUM_24 = 24,   /*!< GPIO24, input and output */
     GPIO_NUM_MAX,
 } gpio_num_t;
 
diff --git a/components/soc/esp32c61/include/soc/gpio_reg.h b/components/soc/esp32c61/include/soc/gpio_reg.h
deleted file mode 100644
index 5a46884fb6f..00000000000
--- a/components/soc/esp32c61/include/soc/gpio_reg.h
+++ /dev/null
@@ -1,4813 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** GPIO_STRAP_REG register
- *  Strapping pin register
- */
-#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0)
-/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
- *  Represents the values of GPIO strapping pins.
- *
- *  - bit0 ~ bit1: invalid
- *  - bit2: GPIO8
- *  - bit3: GPIO9
- *  - bit4: GPIO7
- *  - bit5 ~ bit15: invalid
- */
-#define GPIO_STRAPPING    0x0000FFFFU
-#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
-#define GPIO_STRAPPING_V  0x0000FFFFU
-#define GPIO_STRAPPING_S  0
-
-/** GPIO_OUT_REG register
- *  GPIO output register
- */
-#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
-/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [28:0]; default: 0;
- *  Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\
- *  0: Low level\\
- *  1: High level\\
- *  The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24
- *  respectively. Bit25 ~ bit31 are invalid.\\
- */
-#define GPIO_OUT_DATA_ORIG    0x1FFFFFFFU
-#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
-#define GPIO_OUT_DATA_ORIG_V  0x1FFFFFFFU
-#define GPIO_OUT_DATA_ORIG_S  0
-
-/** GPIO_OUT_W1TS_REG register
- *  GPIO output set register
- */
-#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
-/** GPIO_OUT_W1TS : WT; bitpos: [28:0]; default: 0;
- *  Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~
- *  GPIO24.\\
- *  0: Not set\\
- *  1: The corresponding bit in GPIO_OUT_REG will be set to 1\\
- *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
- *  Recommended operation: use this register to set GPIO_OUT_REG. \\
- */
-#define GPIO_OUT_W1TS    0x1FFFFFFFU
-#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
-#define GPIO_OUT_W1TS_V  0x1FFFFFFFU
-#define GPIO_OUT_W1TS_S  0
-
-/** GPIO_OUT_W1TC_REG register
- *  GPIO output clear register
- */
-#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
-/** GPIO_OUT_W1TC : WT; bitpos: [28:0]; default: 0;
- *  Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
- *  GPIO24 output.\\
- *  0: Not clear\\
- *  1: The corresponding bit in GPIO_OUT_REG will be cleared.\\
- *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
- *  Recommended operation: use this register to clear GPIO_OUT_REG. \\
- */
-#define GPIO_OUT_W1TC    0x1FFFFFFFU
-#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
-#define GPIO_OUT_W1TC_V  0x1FFFFFFFU
-#define GPIO_OUT_W1TC_S  0
-
-/** GPIO_ENABLE_REG register
- *  GPIO output enable register
- */
-#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x34)
-/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [28:0]; default: 0;
- *  Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\
- *  0: Not enable\\
- *  1: Enable\\
- *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
- */
-#define GPIO_ENABLE_DATA    0x1FFFFFFFU
-#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
-#define GPIO_ENABLE_DATA_V  0x1FFFFFFFU
-#define GPIO_ENABLE_DATA_S  0
-
-/** GPIO_ENABLE_W1TS_REG register
- *  GPIO output enable set register
- */
-#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x38)
-/** GPIO_ENABLE_W1TS : WT; bitpos: [28:0]; default: 0;
- *  Configures whether or not to set the output enable register GPIO_ENABLE_REG of
- *  GPIO0 ~ GPIO24.\\
- *  0: Not set\\
- *  1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\
- *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
- *  Recommended operation: use this register to set GPIO_ENABLE_REG.\\
- */
-#define GPIO_ENABLE_W1TS    0x1FFFFFFFU
-#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
-#define GPIO_ENABLE_W1TS_V  0x1FFFFFFFU
-#define GPIO_ENABLE_W1TS_S  0
-
-/** GPIO_ENABLE_W1TC_REG register
- *  GPIO output enable clear register
- */
-#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x3c)
-/** GPIO_ENABLE_W1TC : WT; bitpos: [28:0]; default: 0;
- *  Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
- *  GPIO0 ~ GPIO24. \\
- *  0: Not clear\\
- *  1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\
- *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
- *  Recommended operation: use this register to clear GPIO_ENABLE_REG.\\
- */
-#define GPIO_ENABLE_W1TC    0x1FFFFFFFU
-#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
-#define GPIO_ENABLE_W1TC_V  0x1FFFFFFFU
-#define GPIO_ENABLE_W1TC_S  0
-
-/** GPIO_IN_REG register
- *  GPIO input register
- */
-#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x64)
-/** GPIO_IN_DATA_NEXT : RO; bitpos: [28:0]; default: 0;
- *  Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input
- *  value:\\
- *  0: Low level\\
- *  1: High level\\
- *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
- */
-#define GPIO_IN_DATA_NEXT    0x1FFFFFFFU
-#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
-#define GPIO_IN_DATA_NEXT_V  0x1FFFFFFFU
-#define GPIO_IN_DATA_NEXT_S  0
-
-/** GPIO_STATUS_REG register
- *  GPIO interrupt status register
- */
-#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x74)
-/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [28:0]; default: 0;
- *  The interrupt status of GPIO0 ~ GPIO24, can be configured by the software.
- *
- *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
- *  - Each bit represents the status of its corresponding GPIO:
- *
- *  - 0: Represents the GPIO does not generate the interrupt configured by
- *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
- *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
- *  or this bit is configured to 1 by the software.
- *
- */
-#define GPIO_STATUS_INTERRUPT    0x1FFFFFFFU
-#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
-#define GPIO_STATUS_INTERRUPT_V  0x1FFFFFFFU
-#define GPIO_STATUS_INTERRUPT_S  0
-
-/** GPIO_STATUS_W1TS_REG register
- *  GPIO interrupt status set register
- */
-#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x78)
-/** GPIO_STATUS_W1TS : WT; bitpos: [28:0]; default: 0;
- *  Configures whether or not to set the interrupt status register
- *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
- *
- *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
- *  - If the value 1 is written to a bit here, the corresponding bit in
- *  GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
- *  register to set GPIO_STATUS_INTERRUPT.
- */
-#define GPIO_STATUS_W1TS    0x1FFFFFFFU
-#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
-#define GPIO_STATUS_W1TS_V  0x1FFFFFFFU
-#define GPIO_STATUS_W1TS_S  0
-
-/** GPIO_STATUS_W1TC_REG register
- *  GPIO interrupt status clear register
- */
-#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x7c)
-/** GPIO_STATUS_W1TC : WT; bitpos: [28:0]; default: 0;
- *  Configures whether or not to clear the interrupt status register
- *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
- *
- *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
- *  - If the value 1 is written to a bit here, the corresponding bit in
- *  GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
- *  register to clear GPIO_STATUS_INTERRUPT.
- */
-#define GPIO_STATUS_W1TC    0x1FFFFFFFU
-#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
-#define GPIO_STATUS_W1TC_V  0x1FFFFFFFU
-#define GPIO_STATUS_W1TC_S  0
-
-/** GPIO_PROCPU_INT_REG register
- *  CPU interrupt status register
- */
-#define GPIO_PROCPU_INT_REG (DR_REG_GPIO_BASE + 0xa4)
-/** GPIO_PROCPU_INT : RO; bitpos: [28:0]; default: 0;
- *  Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\
- *  0: Represents CPU interrupt is not enabled, or the GPIO does not generate the
- *  interrupt configured by GPIO_PIN$n_INT_TYPE.\\
- *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
- *  after the CPU interrupt is enabled.\\
- *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This
- *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
- *  enable signal (bit13 of GPIO_PIN$n_REG). \\
- */
-#define GPIO_PROCPU_INT    0x1FFFFFFFU
-#define GPIO_PROCPU_INT_M  (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S)
-#define GPIO_PROCPU_INT_V  0x1FFFFFFFU
-#define GPIO_PROCPU_INT_S  0
-
-/** GPIO_STATUS_NEXT_REG register
- *  GPIO interrupt source register
- */
-#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xb4)
-/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [28:0]; default: 0;
- *  Represents the interrupt source signal of GPIO0 ~ GPIO24.\\
- *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each
- *  bit represents:\\
- *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\
- *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\
- *  The interrupt could be rising edge interrupt, falling edge interrupt, level
- *  sensitive interrupt and any edge interrupt.\\
- */
-#define GPIO_STATUS_INTERRUPT_NEXT    0x1FFFFFFFU
-#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
-#define GPIO_STATUS_INTERRUPT_NEXT_V  0x1FFFFFFFU
-#define GPIO_STATUS_INTERRUPT_NEXT_S  0
-
-/** GPIO_PIN0_REG register
- *  GPIO0 configuration register
- */
-#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xc4)
-/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
-#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN0_SYNC2_BYPASS_S  0
-/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
-#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN0_PAD_DRIVER_S  2
-/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
-#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN0_SYNC1_BYPASS_S  3
-/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN0_INT_TYPE    0x00000007U
-#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
-#define GPIO_PIN0_INT_TYPE_V  0x00000007U
-#define GPIO_PIN0_INT_TYPE_S  7
-/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
-#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN0_WAKEUP_ENABLE_S  10
-/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN0_INT_ENA    0x0000001FU
-#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
-#define GPIO_PIN0_INT_ENA_V  0x0000001FU
-#define GPIO_PIN0_INT_ENA_S  13
-
-/** GPIO_PIN1_REG register
- *  GPIO1 configuration register
- */
-#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xc8)
-/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
-#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN1_SYNC2_BYPASS_S  0
-/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
-#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN1_PAD_DRIVER_S  2
-/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
-#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN1_SYNC1_BYPASS_S  3
-/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN1_INT_TYPE    0x00000007U
-#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
-#define GPIO_PIN1_INT_TYPE_V  0x00000007U
-#define GPIO_PIN1_INT_TYPE_S  7
-/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
-#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN1_WAKEUP_ENABLE_S  10
-/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN1_INT_ENA    0x0000001FU
-#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
-#define GPIO_PIN1_INT_ENA_V  0x0000001FU
-#define GPIO_PIN1_INT_ENA_S  13
-
-/** GPIO_PIN2_REG register
- *  GPIO2 configuration register
- */
-#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xcc)
-/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
-#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN2_SYNC2_BYPASS_S  0
-/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
-#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN2_PAD_DRIVER_S  2
-/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
-#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN2_SYNC1_BYPASS_S  3
-/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN2_INT_TYPE    0x00000007U
-#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
-#define GPIO_PIN2_INT_TYPE_V  0x00000007U
-#define GPIO_PIN2_INT_TYPE_S  7
-/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
-#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN2_WAKEUP_ENABLE_S  10
-/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN2_INT_ENA    0x0000001FU
-#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
-#define GPIO_PIN2_INT_ENA_V  0x0000001FU
-#define GPIO_PIN2_INT_ENA_S  13
-
-/** GPIO_PIN3_REG register
- *  GPIO3 configuration register
- */
-#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xd0)
-/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
-#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN3_SYNC2_BYPASS_S  0
-/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
-#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN3_PAD_DRIVER_S  2
-/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
-#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN3_SYNC1_BYPASS_S  3
-/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN3_INT_TYPE    0x00000007U
-#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
-#define GPIO_PIN3_INT_TYPE_V  0x00000007U
-#define GPIO_PIN3_INT_TYPE_S  7
-/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
-#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN3_WAKEUP_ENABLE_S  10
-/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN3_INT_ENA    0x0000001FU
-#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
-#define GPIO_PIN3_INT_ENA_V  0x0000001FU
-#define GPIO_PIN3_INT_ENA_S  13
-
-/** GPIO_PIN4_REG register
- *  GPIO4 configuration register
- */
-#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xd4)
-/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
-#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN4_SYNC2_BYPASS_S  0
-/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
-#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN4_PAD_DRIVER_S  2
-/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
-#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN4_SYNC1_BYPASS_S  3
-/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN4_INT_TYPE    0x00000007U
-#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
-#define GPIO_PIN4_INT_TYPE_V  0x00000007U
-#define GPIO_PIN4_INT_TYPE_S  7
-/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
-#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN4_WAKEUP_ENABLE_S  10
-/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN4_INT_ENA    0x0000001FU
-#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
-#define GPIO_PIN4_INT_ENA_V  0x0000001FU
-#define GPIO_PIN4_INT_ENA_S  13
-
-/** GPIO_PIN5_REG register
- *  GPIO5 configuration register
- */
-#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xd8)
-/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
-#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN5_SYNC2_BYPASS_S  0
-/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
-#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN5_PAD_DRIVER_S  2
-/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
-#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN5_SYNC1_BYPASS_S  3
-/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN5_INT_TYPE    0x00000007U
-#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
-#define GPIO_PIN5_INT_TYPE_V  0x00000007U
-#define GPIO_PIN5_INT_TYPE_S  7
-/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
-#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN5_WAKEUP_ENABLE_S  10
-/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN5_INT_ENA    0x0000001FU
-#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
-#define GPIO_PIN5_INT_ENA_V  0x0000001FU
-#define GPIO_PIN5_INT_ENA_S  13
-
-/** GPIO_PIN6_REG register
- *  GPIO6 configuration register
- */
-#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xdc)
-/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
-#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN6_SYNC2_BYPASS_S  0
-/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
-#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN6_PAD_DRIVER_S  2
-/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
-#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN6_SYNC1_BYPASS_S  3
-/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN6_INT_TYPE    0x00000007U
-#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
-#define GPIO_PIN6_INT_TYPE_V  0x00000007U
-#define GPIO_PIN6_INT_TYPE_S  7
-/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
-#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN6_WAKEUP_ENABLE_S  10
-/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN6_INT_ENA    0x0000001FU
-#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
-#define GPIO_PIN6_INT_ENA_V  0x0000001FU
-#define GPIO_PIN6_INT_ENA_S  13
-
-/** GPIO_PIN7_REG register
- *  GPIO7 configuration register
- */
-#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xe0)
-/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
-#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN7_SYNC2_BYPASS_S  0
-/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
-#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN7_PAD_DRIVER_S  2
-/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
-#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN7_SYNC1_BYPASS_S  3
-/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN7_INT_TYPE    0x00000007U
-#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
-#define GPIO_PIN7_INT_TYPE_V  0x00000007U
-#define GPIO_PIN7_INT_TYPE_S  7
-/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
-#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN7_WAKEUP_ENABLE_S  10
-/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN7_INT_ENA    0x0000001FU
-#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
-#define GPIO_PIN7_INT_ENA_V  0x0000001FU
-#define GPIO_PIN7_INT_ENA_S  13
-
-/** GPIO_PIN8_REG register
- *  GPIO8 configuration register
- */
-#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xe4)
-/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
-#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN8_SYNC2_BYPASS_S  0
-/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
-#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN8_PAD_DRIVER_S  2
-/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
-#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN8_SYNC1_BYPASS_S  3
-/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN8_INT_TYPE    0x00000007U
-#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
-#define GPIO_PIN8_INT_TYPE_V  0x00000007U
-#define GPIO_PIN8_INT_TYPE_S  7
-/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
-#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN8_WAKEUP_ENABLE_S  10
-/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN8_INT_ENA    0x0000001FU
-#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
-#define GPIO_PIN8_INT_ENA_V  0x0000001FU
-#define GPIO_PIN8_INT_ENA_S  13
-
-/** GPIO_PIN9_REG register
- *  GPIO9 configuration register
- */
-#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xe8)
-/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
-#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN9_SYNC2_BYPASS_S  0
-/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
-#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN9_PAD_DRIVER_S  2
-/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
-#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN9_SYNC1_BYPASS_S  3
-/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN9_INT_TYPE    0x00000007U
-#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
-#define GPIO_PIN9_INT_TYPE_V  0x00000007U
-#define GPIO_PIN9_INT_TYPE_S  7
-/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
-#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN9_WAKEUP_ENABLE_S  10
-/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN9_INT_ENA    0x0000001FU
-#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
-#define GPIO_PIN9_INT_ENA_V  0x0000001FU
-#define GPIO_PIN9_INT_ENA_S  13
-
-/** GPIO_PIN10_REG register
- *  GPIO10 configuration register
- */
-#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xec)
-/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
-#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN10_SYNC2_BYPASS_S  0
-/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
-#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN10_PAD_DRIVER_S  2
-/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
-#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN10_SYNC1_BYPASS_S  3
-/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN10_INT_TYPE    0x00000007U
-#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
-#define GPIO_PIN10_INT_TYPE_V  0x00000007U
-#define GPIO_PIN10_INT_TYPE_S  7
-/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
-#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN10_WAKEUP_ENABLE_S  10
-/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN10_INT_ENA    0x0000001FU
-#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
-#define GPIO_PIN10_INT_ENA_V  0x0000001FU
-#define GPIO_PIN10_INT_ENA_S  13
-
-/** GPIO_PIN11_REG register
- *  GPIO11 configuration register
- */
-#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xf0)
-/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
-#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN11_SYNC2_BYPASS_S  0
-/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
-#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN11_PAD_DRIVER_S  2
-/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
-#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN11_SYNC1_BYPASS_S  3
-/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN11_INT_TYPE    0x00000007U
-#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
-#define GPIO_PIN11_INT_TYPE_V  0x00000007U
-#define GPIO_PIN11_INT_TYPE_S  7
-/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
-#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN11_WAKEUP_ENABLE_S  10
-/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN11_INT_ENA    0x0000001FU
-#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
-#define GPIO_PIN11_INT_ENA_V  0x0000001FU
-#define GPIO_PIN11_INT_ENA_S  13
-
-/** GPIO_PIN12_REG register
- *  GPIO12 configuration register
- */
-#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xf4)
-/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
-#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN12_SYNC2_BYPASS_S  0
-/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
-#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN12_PAD_DRIVER_S  2
-/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
-#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN12_SYNC1_BYPASS_S  3
-/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN12_INT_TYPE    0x00000007U
-#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
-#define GPIO_PIN12_INT_TYPE_V  0x00000007U
-#define GPIO_PIN12_INT_TYPE_S  7
-/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
-#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN12_WAKEUP_ENABLE_S  10
-/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN12_INT_ENA    0x0000001FU
-#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
-#define GPIO_PIN12_INT_ENA_V  0x0000001FU
-#define GPIO_PIN12_INT_ENA_S  13
-
-/** GPIO_PIN13_REG register
- *  GPIO13 configuration register
- */
-#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xf8)
-/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
-#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN13_SYNC2_BYPASS_S  0
-/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
-#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN13_PAD_DRIVER_S  2
-/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
-#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN13_SYNC1_BYPASS_S  3
-/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN13_INT_TYPE    0x00000007U
-#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
-#define GPIO_PIN13_INT_TYPE_V  0x00000007U
-#define GPIO_PIN13_INT_TYPE_S  7
-/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
-#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN13_WAKEUP_ENABLE_S  10
-/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN13_INT_ENA    0x0000001FU
-#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
-#define GPIO_PIN13_INT_ENA_V  0x0000001FU
-#define GPIO_PIN13_INT_ENA_S  13
-
-/** GPIO_PIN14_REG register
- *  GPIO14 configuration register
- */
-#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xfc)
-/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
-#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN14_SYNC2_BYPASS_S  0
-/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
-#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN14_PAD_DRIVER_S  2
-/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
-#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN14_SYNC1_BYPASS_S  3
-/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN14_INT_TYPE    0x00000007U
-#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
-#define GPIO_PIN14_INT_TYPE_V  0x00000007U
-#define GPIO_PIN14_INT_TYPE_S  7
-/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
-#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN14_WAKEUP_ENABLE_S  10
-/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN14_INT_ENA    0x0000001FU
-#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
-#define GPIO_PIN14_INT_ENA_V  0x0000001FU
-#define GPIO_PIN14_INT_ENA_S  13
-
-/** GPIO_PIN15_REG register
- *  GPIO15 configuration register
- */
-#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x100)
-/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
-#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN15_SYNC2_BYPASS_S  0
-/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
-#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN15_PAD_DRIVER_S  2
-/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
-#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN15_SYNC1_BYPASS_S  3
-/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN15_INT_TYPE    0x00000007U
-#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
-#define GPIO_PIN15_INT_TYPE_V  0x00000007U
-#define GPIO_PIN15_INT_TYPE_S  7
-/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
-#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN15_WAKEUP_ENABLE_S  10
-/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN15_INT_ENA    0x0000001FU
-#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
-#define GPIO_PIN15_INT_ENA_V  0x0000001FU
-#define GPIO_PIN15_INT_ENA_S  13
-
-/** GPIO_PIN16_REG register
- *  GPIO16 configuration register
- */
-#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x104)
-/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
-#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN16_SYNC2_BYPASS_S  0
-/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
-#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN16_PAD_DRIVER_S  2
-/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
-#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN16_SYNC1_BYPASS_S  3
-/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN16_INT_TYPE    0x00000007U
-#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
-#define GPIO_PIN16_INT_TYPE_V  0x00000007U
-#define GPIO_PIN16_INT_TYPE_S  7
-/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
-#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN16_WAKEUP_ENABLE_S  10
-/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN16_INT_ENA    0x0000001FU
-#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
-#define GPIO_PIN16_INT_ENA_V  0x0000001FU
-#define GPIO_PIN16_INT_ENA_S  13
-
-/** GPIO_PIN17_REG register
- *  GPIO17 configuration register
- */
-#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x108)
-/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
-#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN17_SYNC2_BYPASS_S  0
-/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
-#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN17_PAD_DRIVER_S  2
-/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
-#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN17_SYNC1_BYPASS_S  3
-/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN17_INT_TYPE    0x00000007U
-#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
-#define GPIO_PIN17_INT_TYPE_V  0x00000007U
-#define GPIO_PIN17_INT_TYPE_S  7
-/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
-#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN17_WAKEUP_ENABLE_S  10
-/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN17_INT_ENA    0x0000001FU
-#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
-#define GPIO_PIN17_INT_ENA_V  0x0000001FU
-#define GPIO_PIN17_INT_ENA_S  13
-
-/** GPIO_PIN18_REG register
- *  GPIO18 configuration register
- */
-#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x10c)
-/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
-#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN18_SYNC2_BYPASS_S  0
-/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
-#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN18_PAD_DRIVER_S  2
-/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
-#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN18_SYNC1_BYPASS_S  3
-/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN18_INT_TYPE    0x00000007U
-#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
-#define GPIO_PIN18_INT_TYPE_V  0x00000007U
-#define GPIO_PIN18_INT_TYPE_S  7
-/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
-#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN18_WAKEUP_ENABLE_S  10
-/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN18_INT_ENA    0x0000001FU
-#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
-#define GPIO_PIN18_INT_ENA_V  0x0000001FU
-#define GPIO_PIN18_INT_ENA_S  13
-
-/** GPIO_PIN19_REG register
- *  GPIO19 configuration register
- */
-#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x110)
-/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
-#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN19_SYNC2_BYPASS_S  0
-/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
-#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN19_PAD_DRIVER_S  2
-/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
-#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN19_SYNC1_BYPASS_S  3
-/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN19_INT_TYPE    0x00000007U
-#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
-#define GPIO_PIN19_INT_TYPE_V  0x00000007U
-#define GPIO_PIN19_INT_TYPE_S  7
-/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
-#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN19_WAKEUP_ENABLE_S  10
-/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN19_INT_ENA    0x0000001FU
-#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
-#define GPIO_PIN19_INT_ENA_V  0x0000001FU
-#define GPIO_PIN19_INT_ENA_S  13
-
-/** GPIO_PIN20_REG register
- *  GPIO20 configuration register
- */
-#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x114)
-/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
-#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN20_SYNC2_BYPASS_S  0
-/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
-#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN20_PAD_DRIVER_S  2
-/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
-#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN20_SYNC1_BYPASS_S  3
-/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN20_INT_TYPE    0x00000007U
-#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
-#define GPIO_PIN20_INT_TYPE_V  0x00000007U
-#define GPIO_PIN20_INT_TYPE_S  7
-/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
-#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN20_WAKEUP_ENABLE_S  10
-/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN20_INT_ENA    0x0000001FU
-#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
-#define GPIO_PIN20_INT_ENA_V  0x0000001FU
-#define GPIO_PIN20_INT_ENA_S  13
-
-/** GPIO_PIN21_REG register
- *  GPIO21 configuration register
- */
-#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x118)
-/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the second-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
-#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN21_SYNC2_BYPASS_S  0
-/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  Configures to select pin drive mode. \\
- *  0: Normal output\\
- *  1: Open drain output \\
- */
-#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
-#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN21_PAD_DRIVER_S  2
-/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
- *  operating clock for the first-level synchronization.\\
- *  0: Not synchronize\\
- *  1: Synchronize on falling edge\\
- *  2: Synchronize on rising edge\\
- *  3: Synchronize on rising edge\\
- */
-#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
-#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN21_SYNC1_BYPASS_S  3
-/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  Configures GPIO interrupt type.\\
- *  0: GPIO interrupt disabled\\
- *  1: Rising edge trigger\\
- *  2: Falling edge trigger\\
- *  3: Any edge trigger\\
- *  4: Low level trigger\\
- *  5: High level trigger\\
- */
-#define GPIO_PIN21_INT_TYPE    0x00000007U
-#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
-#define GPIO_PIN21_INT_TYPE_V  0x00000007U
-#define GPIO_PIN21_INT_TYPE_S  7
-/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable GPIO wake-up function.\\
- *  0: Disable\\
- *  1: Enable\\
- *  This function only wakes up the CPU from Light-sleep. \\
- */
-#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
-#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN21_WAKEUP_ENABLE_S  10
-/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  Configures whether or not to enable CPU interrupt.
- *
- *  - bit13: Configures whether or not to enable CPU interrupt:\\
- *  0: Disable\\
- *  1: Enable\\
- *  - bit14 ~ bit17: invalid
- */
-#define GPIO_PIN21_INT_ENA    0x0000001FU
-#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
-#define GPIO_PIN21_INT_ENA_V  0x0000001FU
-#define GPIO_PIN21_INT_ENA_S  13
-
-/** GPIO_FUNC0_IN_SEL_CFG_REG register
- *  Configuration register for input signal 0
- */
-#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
-/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC0_IN_SEL    0x0000003FU
-#define GPIO_FUNC0_IN_SEL_M  (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S)
-#define GPIO_FUNC0_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC0_IN_SEL_S  0
-/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC0_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC0_IN_INV_SEL_M  (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S)
-#define GPIO_FUNC0_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC0_IN_INV_SEL_S  6
-/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG0_IN_SEL    (BIT(7))
-#define GPIO_SIG0_IN_SEL_M  (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S)
-#define GPIO_SIG0_IN_SEL_V  0x00000001U
-#define GPIO_SIG0_IN_SEL_S  7
-
-/** GPIO_FUNC6_IN_SEL_CFG_REG register
- *  Configuration register for input signal 6
- */
-#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
-/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 6.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC6_IN_SEL    0x0000003FU
-#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
-#define GPIO_FUNC6_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC6_IN_SEL_S  0
-/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
-#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_IN_INV_SEL_S  6
-/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG6_IN_SEL    (BIT(7))
-#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
-#define GPIO_SIG6_IN_SEL_V  0x00000001U
-#define GPIO_SIG6_IN_SEL_S  7
-
-/** GPIO_FUNC7_IN_SEL_CFG_REG register
- *  Configuration register for input signal 7
- */
-#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
-/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 7.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC7_IN_SEL    0x0000003FU
-#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
-#define GPIO_FUNC7_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC7_IN_SEL_S  0
-/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
-#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_IN_INV_SEL_S  6
-/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG7_IN_SEL    (BIT(7))
-#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
-#define GPIO_SIG7_IN_SEL_V  0x00000001U
-#define GPIO_SIG7_IN_SEL_S  7
-
-/** GPIO_FUNC8_IN_SEL_CFG_REG register
- *  Configuration register for input signal 8
- */
-#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
-/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 8.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC8_IN_SEL    0x0000003FU
-#define GPIO_FUNC8_IN_SEL_M  (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S)
-#define GPIO_FUNC8_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC8_IN_SEL_S  0
-/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC8_IN_INV_SEL_M  (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S)
-#define GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_IN_INV_SEL_S  6
-/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG8_IN_SEL    (BIT(7))
-#define GPIO_SIG8_IN_SEL_M  (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S)
-#define GPIO_SIG8_IN_SEL_V  0x00000001U
-#define GPIO_SIG8_IN_SEL_S  7
-
-/** GPIO_FUNC9_IN_SEL_CFG_REG register
- *  Configuration register for input signal 9
- */
-#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
-/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 9.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC9_IN_SEL    0x0000003FU
-#define GPIO_FUNC9_IN_SEL_M  (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S)
-#define GPIO_FUNC9_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC9_IN_SEL_S  0
-/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC9_IN_INV_SEL_M  (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S)
-#define GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_IN_INV_SEL_S  6
-/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG9_IN_SEL    (BIT(7))
-#define GPIO_SIG9_IN_SEL_M  (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S)
-#define GPIO_SIG9_IN_SEL_V  0x00000001U
-#define GPIO_SIG9_IN_SEL_S  7
-
-/** GPIO_FUNC10_IN_SEL_CFG_REG register
- *  Configuration register for input signal 10
- */
-#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
-/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 10.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC10_IN_SEL    0x0000003FU
-#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
-#define GPIO_FUNC10_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC10_IN_SEL_S  0
-/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
-#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_IN_INV_SEL_S  6
-/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG10_IN_SEL    (BIT(7))
-#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
-#define GPIO_SIG10_IN_SEL_V  0x00000001U
-#define GPIO_SIG10_IN_SEL_S  7
-
-/** GPIO_FUNC11_IN_SEL_CFG_REG register
- *  Configuration register for input signal 11
- */
-#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
-/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 11.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC11_IN_SEL    0x0000003FU
-#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
-#define GPIO_FUNC11_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC11_IN_SEL_S  0
-/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
-#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_IN_INV_SEL_S  6
-/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG11_IN_SEL    (BIT(7))
-#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
-#define GPIO_SIG11_IN_SEL_V  0x00000001U
-#define GPIO_SIG11_IN_SEL_S  7
-
-/** GPIO_FUNC12_IN_SEL_CFG_REG register
- *  Configuration register for input signal 12
- */
-#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
-/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 12.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC12_IN_SEL    0x0000003FU
-#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
-#define GPIO_FUNC12_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC12_IN_SEL_S  0
-/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
-#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_IN_INV_SEL_S  6
-/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG12_IN_SEL    (BIT(7))
-#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
-#define GPIO_SIG12_IN_SEL_V  0x00000001U
-#define GPIO_SIG12_IN_SEL_S  7
-
-/** GPIO_FUNC13_IN_SEL_CFG_REG register
- *  Configuration register for input signal 13
- */
-#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
-/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 13.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC13_IN_SEL    0x0000003FU
-#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
-#define GPIO_FUNC13_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC13_IN_SEL_S  0
-/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
-#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_IN_INV_SEL_S  6
-/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG13_IN_SEL    (BIT(7))
-#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
-#define GPIO_SIG13_IN_SEL_V  0x00000001U
-#define GPIO_SIG13_IN_SEL_S  7
-
-/** GPIO_FUNC14_IN_SEL_CFG_REG register
- *  Configuration register for input signal 14
- */
-#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
-/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 14.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC14_IN_SEL    0x0000003FU
-#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
-#define GPIO_FUNC14_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC14_IN_SEL_S  0
-/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
-#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_IN_INV_SEL_S  6
-/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG14_IN_SEL    (BIT(7))
-#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
-#define GPIO_SIG14_IN_SEL_V  0x00000001U
-#define GPIO_SIG14_IN_SEL_S  7
-
-/** GPIO_FUNC15_IN_SEL_CFG_REG register
- *  Configuration register for input signal 15
- */
-#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
-/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 15.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC15_IN_SEL    0x0000003FU
-#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
-#define GPIO_FUNC15_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC15_IN_SEL_S  0
-/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
-#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_IN_INV_SEL_S  6
-/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG15_IN_SEL    (BIT(7))
-#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
-#define GPIO_SIG15_IN_SEL_V  0x00000001U
-#define GPIO_SIG15_IN_SEL_S  7
-
-/** GPIO_FUNC16_IN_SEL_CFG_REG register
- *  Configuration register for input signal 16
- */
-#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
-/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 16.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC16_IN_SEL    0x0000003FU
-#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
-#define GPIO_FUNC16_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC16_IN_SEL_S  0
-/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
-#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_IN_INV_SEL_S  6
-/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG16_IN_SEL    (BIT(7))
-#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
-#define GPIO_SIG16_IN_SEL_V  0x00000001U
-#define GPIO_SIG16_IN_SEL_S  7
-
-/** GPIO_FUNC17_IN_SEL_CFG_REG register
- *  Configuration register for input signal 17
- */
-#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
-/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 17.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC17_IN_SEL    0x0000003FU
-#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
-#define GPIO_FUNC17_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC17_IN_SEL_S  0
-/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
-#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_IN_INV_SEL_S  6
-/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG17_IN_SEL    (BIT(7))
-#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
-#define GPIO_SIG17_IN_SEL_V  0x00000001U
-#define GPIO_SIG17_IN_SEL_S  7
-
-/** GPIO_FUNC27_IN_SEL_CFG_REG register
- *  Configuration register for input signal 27
- */
-#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
-/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 27.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC27_IN_SEL    0x0000003FU
-#define GPIO_FUNC27_IN_SEL_M  (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S)
-#define GPIO_FUNC27_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC27_IN_SEL_S  0
-/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC27_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC27_IN_INV_SEL_M  (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S)
-#define GPIO_FUNC27_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC27_IN_INV_SEL_S  6
-/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG27_IN_SEL    (BIT(7))
-#define GPIO_SIG27_IN_SEL_M  (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S)
-#define GPIO_SIG27_IN_SEL_V  0x00000001U
-#define GPIO_SIG27_IN_SEL_S  7
-
-/** GPIO_FUNC28_IN_SEL_CFG_REG register
- *  Configuration register for input signal 28
- */
-#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334)
-/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 28.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC28_IN_SEL    0x0000003FU
-#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
-#define GPIO_FUNC28_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC28_IN_SEL_S  0
-/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
-#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC28_IN_INV_SEL_S  6
-/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG28_IN_SEL    (BIT(7))
-#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
-#define GPIO_SIG28_IN_SEL_V  0x00000001U
-#define GPIO_SIG28_IN_SEL_S  7
-
-/** GPIO_FUNC29_IN_SEL_CFG_REG register
- *  Configuration register for input signal 29
- */
-#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338)
-/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 29.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC29_IN_SEL    0x0000003FU
-#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
-#define GPIO_FUNC29_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC29_IN_SEL_S  0
-/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
-#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC29_IN_INV_SEL_S  6
-/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG29_IN_SEL    (BIT(7))
-#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
-#define GPIO_SIG29_IN_SEL_V  0x00000001U
-#define GPIO_SIG29_IN_SEL_S  7
-
-/** GPIO_FUNC30_IN_SEL_CFG_REG register
- *  Configuration register for input signal 30
- */
-#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c)
-/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 30.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC30_IN_SEL    0x0000003FU
-#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
-#define GPIO_FUNC30_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC30_IN_SEL_S  0
-/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
-#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC30_IN_INV_SEL_S  6
-/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG30_IN_SEL    (BIT(7))
-#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
-#define GPIO_SIG30_IN_SEL_V  0x00000001U
-#define GPIO_SIG30_IN_SEL_S  7
-
-/** GPIO_FUNC31_IN_SEL_CFG_REG register
- *  Configuration register for input signal 31
- */
-#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340)
-/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 31.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC31_IN_SEL    0x0000003FU
-#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
-#define GPIO_FUNC31_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC31_IN_SEL_S  0
-/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
-#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC31_IN_INV_SEL_S  6
-/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG31_IN_SEL    (BIT(7))
-#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
-#define GPIO_SIG31_IN_SEL_V  0x00000001U
-#define GPIO_SIG31_IN_SEL_S  7
-
-/** GPIO_FUNC32_IN_SEL_CFG_REG register
- *  Configuration register for input signal 32
- */
-#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344)
-/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 32.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC32_IN_SEL    0x0000003FU
-#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
-#define GPIO_FUNC32_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC32_IN_SEL_S  0
-/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
-#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC32_IN_INV_SEL_S  6
-/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG32_IN_SEL    (BIT(7))
-#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
-#define GPIO_SIG32_IN_SEL_V  0x00000001U
-#define GPIO_SIG32_IN_SEL_S  7
-
-/** GPIO_FUNC33_IN_SEL_CFG_REG register
- *  Configuration register for input signal 33
- */
-#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348)
-/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 33.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC33_IN_SEL    0x0000003FU
-#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
-#define GPIO_FUNC33_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC33_IN_SEL_S  0
-/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
-#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC33_IN_INV_SEL_S  6
-/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG33_IN_SEL    (BIT(7))
-#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
-#define GPIO_SIG33_IN_SEL_V  0x00000001U
-#define GPIO_SIG33_IN_SEL_S  7
-
-/** GPIO_FUNC34_IN_SEL_CFG_REG register
- *  Configuration register for input signal 34
- */
-#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c)
-/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 34.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC34_IN_SEL    0x0000003FU
-#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
-#define GPIO_FUNC34_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC34_IN_SEL_S  0
-/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
-#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC34_IN_INV_SEL_S  6
-/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG34_IN_SEL    (BIT(7))
-#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
-#define GPIO_SIG34_IN_SEL_V  0x00000001U
-#define GPIO_SIG34_IN_SEL_S  7
-
-/** GPIO_FUNC35_IN_SEL_CFG_REG register
- *  Configuration register for input signal 35
- */
-#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
-/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 35.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC35_IN_SEL    0x0000003FU
-#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
-#define GPIO_FUNC35_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC35_IN_SEL_S  0
-/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
-#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC35_IN_INV_SEL_S  6
-/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG35_IN_SEL    (BIT(7))
-#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
-#define GPIO_SIG35_IN_SEL_V  0x00000001U
-#define GPIO_SIG35_IN_SEL_S  7
-
-/** GPIO_FUNC41_IN_SEL_CFG_REG register
- *  Configuration register for input signal 41
- */
-#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368)
-/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 41.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC41_IN_SEL    0x0000003FU
-#define GPIO_FUNC41_IN_SEL_M  (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S)
-#define GPIO_FUNC41_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC41_IN_SEL_S  0
-/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC41_IN_INV_SEL_M  (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S)
-#define GPIO_FUNC41_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC41_IN_INV_SEL_S  6
-/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG41_IN_SEL    (BIT(7))
-#define GPIO_SIG41_IN_SEL_M  (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S)
-#define GPIO_SIG41_IN_SEL_V  0x00000001U
-#define GPIO_SIG41_IN_SEL_S  7
-
-/** GPIO_FUNC42_IN_SEL_CFG_REG register
- *  Configuration register for input signal 42
- */
-#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c)
-/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 42.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC42_IN_SEL    0x0000003FU
-#define GPIO_FUNC42_IN_SEL_M  (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S)
-#define GPIO_FUNC42_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC42_IN_SEL_S  0
-/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC42_IN_INV_SEL_M  (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S)
-#define GPIO_FUNC42_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC42_IN_INV_SEL_S  6
-/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG42_IN_SEL    (BIT(7))
-#define GPIO_SIG42_IN_SEL_M  (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S)
-#define GPIO_SIG42_IN_SEL_V  0x00000001U
-#define GPIO_SIG42_IN_SEL_S  7
-
-/** GPIO_FUNC43_IN_SEL_CFG_REG register
- *  Configuration register for input signal 43
- */
-#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370)
-/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 43.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC43_IN_SEL    0x0000003FU
-#define GPIO_FUNC43_IN_SEL_M  (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S)
-#define GPIO_FUNC43_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC43_IN_SEL_S  0
-/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC43_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC43_IN_INV_SEL_M  (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S)
-#define GPIO_FUNC43_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC43_IN_INV_SEL_S  6
-/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG43_IN_SEL    (BIT(7))
-#define GPIO_SIG43_IN_SEL_M  (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S)
-#define GPIO_SIG43_IN_SEL_V  0x00000001U
-#define GPIO_SIG43_IN_SEL_S  7
-
-/** GPIO_FUNC46_IN_SEL_CFG_REG register
- *  Configuration register for input signal 46
- */
-#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c)
-/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 32;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 46.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC46_IN_SEL    0x0000003FU
-#define GPIO_FUNC46_IN_SEL_M  (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S)
-#define GPIO_FUNC46_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC46_IN_SEL_S  0
-/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC46_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC46_IN_INV_SEL_M  (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S)
-#define GPIO_FUNC46_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC46_IN_INV_SEL_S  6
-/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG46_IN_SEL    (BIT(7))
-#define GPIO_SIG46_IN_SEL_M  (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S)
-#define GPIO_SIG46_IN_SEL_V  0x00000001U
-#define GPIO_SIG46_IN_SEL_S  7
-
-/** GPIO_FUNC47_IN_SEL_CFG_REG register
- *  Configuration register for input signal 47
- */
-#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380)
-/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 32;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 47.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC47_IN_SEL    0x0000003FU
-#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
-#define GPIO_FUNC47_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC47_IN_SEL_S  0
-/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
-#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC47_IN_INV_SEL_S  6
-/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG47_IN_SEL    (BIT(7))
-#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
-#define GPIO_SIG47_IN_SEL_V  0x00000001U
-#define GPIO_SIG47_IN_SEL_S  7
-
-/** GPIO_FUNC64_IN_SEL_CFG_REG register
- *  Configuration register for input signal 64
- */
-#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4)
-/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 64.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC64_IN_SEL    0x0000003FU
-#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
-#define GPIO_FUNC64_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC64_IN_SEL_S  0
-/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
-#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC64_IN_INV_SEL_S  6
-/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG64_IN_SEL    (BIT(7))
-#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
-#define GPIO_SIG64_IN_SEL_V  0x00000001U
-#define GPIO_SIG64_IN_SEL_S  7
-
-/** GPIO_FUNC65_IN_SEL_CFG_REG register
- *  Configuration register for input signal 65
- */
-#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8)
-/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 65.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC65_IN_SEL    0x0000003FU
-#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
-#define GPIO_FUNC65_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC65_IN_SEL_S  0
-/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
-#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC65_IN_INV_SEL_S  6
-/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG65_IN_SEL    (BIT(7))
-#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
-#define GPIO_SIG65_IN_SEL_V  0x00000001U
-#define GPIO_SIG65_IN_SEL_S  7
-
-/** GPIO_FUNC66_IN_SEL_CFG_REG register
- *  Configuration register for input signal 66
- */
-#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc)
-/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 66.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC66_IN_SEL    0x0000003FU
-#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
-#define GPIO_FUNC66_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC66_IN_SEL_S  0
-/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
-#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC66_IN_INV_SEL_S  6
-/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG66_IN_SEL    (BIT(7))
-#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
-#define GPIO_SIG66_IN_SEL_V  0x00000001U
-#define GPIO_SIG66_IN_SEL_S  7
-
-/** GPIO_FUNC67_IN_SEL_CFG_REG register
- *  Configuration register for input signal 67
- */
-#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0)
-/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 67.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC67_IN_SEL    0x0000003FU
-#define GPIO_FUNC67_IN_SEL_M  (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S)
-#define GPIO_FUNC67_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC67_IN_SEL_S  0
-/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC67_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC67_IN_INV_SEL_M  (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S)
-#define GPIO_FUNC67_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC67_IN_INV_SEL_S  6
-/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG67_IN_SEL    (BIT(7))
-#define GPIO_SIG67_IN_SEL_M  (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S)
-#define GPIO_SIG67_IN_SEL_V  0x00000001U
-#define GPIO_SIG67_IN_SEL_S  7
-
-/** GPIO_FUNC68_IN_SEL_CFG_REG register
- *  Configuration register for input signal 68
- */
-#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4)
-/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 68.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC68_IN_SEL    0x0000003FU
-#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
-#define GPIO_FUNC68_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC68_IN_SEL_S  0
-/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
-#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC68_IN_INV_SEL_S  6
-/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG68_IN_SEL    (BIT(7))
-#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
-#define GPIO_SIG68_IN_SEL_V  0x00000001U
-#define GPIO_SIG68_IN_SEL_S  7
-
-/** GPIO_FUNC69_IN_SEL_CFG_REG register
- *  Configuration register for input signal 69
- */
-#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8)
-/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 69.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC69_IN_SEL    0x0000003FU
-#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
-#define GPIO_FUNC69_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC69_IN_SEL_S  0
-/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
-#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC69_IN_INV_SEL_S  6
-/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG69_IN_SEL    (BIT(7))
-#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
-#define GPIO_SIG69_IN_SEL_V  0x00000001U
-#define GPIO_SIG69_IN_SEL_S  7
-
-/** GPIO_FUNC72_IN_SEL_CFG_REG register
- *  Configuration register for input signal 72
- */
-#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4)
-/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 32;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 72.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC72_IN_SEL    0x0000003FU
-#define GPIO_FUNC72_IN_SEL_M  (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S)
-#define GPIO_FUNC72_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC72_IN_SEL_S  0
-/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC72_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC72_IN_INV_SEL_M  (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S)
-#define GPIO_FUNC72_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC72_IN_INV_SEL_S  6
-/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG72_IN_SEL    (BIT(7))
-#define GPIO_SIG72_IN_SEL_M  (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S)
-#define GPIO_SIG72_IN_SEL_V  0x00000001U
-#define GPIO_SIG72_IN_SEL_S  7
-
-/** GPIO_FUNC73_IN_SEL_CFG_REG register
- *  Configuration register for input signal 73
- */
-#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8)
-/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 32;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 73.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC73_IN_SEL    0x0000003FU
-#define GPIO_FUNC73_IN_SEL_M  (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S)
-#define GPIO_FUNC73_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC73_IN_SEL_S  0
-/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC73_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC73_IN_INV_SEL_M  (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S)
-#define GPIO_FUNC73_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC73_IN_INV_SEL_S  6
-/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG73_IN_SEL    (BIT(7))
-#define GPIO_SIG73_IN_SEL_M  (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S)
-#define GPIO_SIG73_IN_SEL_V  0x00000001U
-#define GPIO_SIG73_IN_SEL_S  7
-
-/** GPIO_FUNC74_IN_SEL_CFG_REG register
- *  Configuration register for input signal 74
- */
-#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec)
-/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 32;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 74.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC74_IN_SEL    0x0000003FU
-#define GPIO_FUNC74_IN_SEL_M  (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S)
-#define GPIO_FUNC74_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC74_IN_SEL_S  0
-/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC74_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC74_IN_INV_SEL_M  (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S)
-#define GPIO_FUNC74_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC74_IN_INV_SEL_S  6
-/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG74_IN_SEL    (BIT(7))
-#define GPIO_SIG74_IN_SEL_M  (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S)
-#define GPIO_SIG74_IN_SEL_V  0x00000001U
-#define GPIO_SIG74_IN_SEL_S  7
-
-/** GPIO_FUNC82_IN_SEL_CFG_REG register
- *  Configuration register for input signal 82
- */
-#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c)
-/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 82.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC82_IN_SEL    0x0000003FU
-#define GPIO_FUNC82_IN_SEL_M  (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S)
-#define GPIO_FUNC82_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC82_IN_SEL_S  0
-/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC82_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC82_IN_INV_SEL_M  (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S)
-#define GPIO_FUNC82_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC82_IN_INV_SEL_S  6
-/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG82_IN_SEL    (BIT(7))
-#define GPIO_SIG82_IN_SEL_M  (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S)
-#define GPIO_SIG82_IN_SEL_V  0x00000001U
-#define GPIO_SIG82_IN_SEL_S  7
-
-/** GPIO_FUNC83_IN_SEL_CFG_REG register
- *  Configuration register for input signal 83
- */
-#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410)
-/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 83.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC83_IN_SEL    0x0000003FU
-#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
-#define GPIO_FUNC83_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC83_IN_SEL_S  0
-/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
-#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC83_IN_INV_SEL_S  6
-/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG83_IN_SEL    (BIT(7))
-#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
-#define GPIO_SIG83_IN_SEL_V  0x00000001U
-#define GPIO_SIG83_IN_SEL_S  7
-
-/** GPIO_FUNC97_IN_SEL_CFG_REG register
- *  Configuration register for input signal 97
- */
-#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448)
-/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 97.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC97_IN_SEL    0x0000003FU
-#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
-#define GPIO_FUNC97_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC97_IN_SEL_S  0
-/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
-#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC97_IN_INV_SEL_S  6
-/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG97_IN_SEL    (BIT(7))
-#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
-#define GPIO_SIG97_IN_SEL_V  0x00000001U
-#define GPIO_SIG97_IN_SEL_S  7
-
-/** GPIO_FUNC98_IN_SEL_CFG_REG register
- *  Configuration register for input signal 98
- */
-#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c)
-/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 98.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC98_IN_SEL    0x0000003FU
-#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
-#define GPIO_FUNC98_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC98_IN_SEL_S  0
-/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
-#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC98_IN_INV_SEL_S  6
-/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG98_IN_SEL    (BIT(7))
-#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
-#define GPIO_SIG98_IN_SEL_V  0x00000001U
-#define GPIO_SIG98_IN_SEL_S  7
-
-/** GPIO_FUNC99_IN_SEL_CFG_REG register
- *  Configuration register for input signal 99
- */
-#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450)
-/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 99.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC99_IN_SEL    0x0000003FU
-#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
-#define GPIO_FUNC99_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC99_IN_SEL_S  0
-/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
-#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC99_IN_INV_SEL_S  6
-/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG99_IN_SEL    (BIT(7))
-#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
-#define GPIO_SIG99_IN_SEL_V  0x00000001U
-#define GPIO_SIG99_IN_SEL_S  7
-
-/** GPIO_FUNC100_IN_SEL_CFG_REG register
- *  Configuration register for input signal 100
- */
-#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454)
-/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 100.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC100_IN_SEL    0x0000003FU
-#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
-#define GPIO_FUNC100_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC100_IN_SEL_S  0
-/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
-#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC100_IN_INV_SEL_S  6
-/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG100_IN_SEL    (BIT(7))
-#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
-#define GPIO_SIG100_IN_SEL_V  0x00000001U
-#define GPIO_SIG100_IN_SEL_S  7
-
-/** GPIO_FUNC118_IN_SEL_CFG_REG register
- *  Configuration register for input signal 118
- */
-#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c)
-/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 118.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC118_IN_SEL    0x0000003FU
-#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
-#define GPIO_FUNC118_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC118_IN_SEL_S  0
-/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
-#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC118_IN_INV_SEL_S  6
-/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG118_IN_SEL    (BIT(7))
-#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
-#define GPIO_SIG118_IN_SEL_V  0x00000001U
-#define GPIO_SIG118_IN_SEL_S  7
-
-/** GPIO_FUNC119_IN_SEL_CFG_REG register
- *  Configuration register for input signal 119
- */
-#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0)
-/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 119.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC119_IN_SEL    0x0000003FU
-#define GPIO_FUNC119_IN_SEL_M  (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S)
-#define GPIO_FUNC119_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC119_IN_SEL_S  0
-/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC119_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC119_IN_INV_SEL_M  (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S)
-#define GPIO_FUNC119_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC119_IN_INV_SEL_S  6
-/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG119_IN_SEL    (BIT(7))
-#define GPIO_SIG119_IN_SEL_M  (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S)
-#define GPIO_SIG119_IN_SEL_V  0x00000001U
-#define GPIO_SIG119_IN_SEL_S  7
-
-/** GPIO_FUNC120_IN_SEL_CFG_REG register
- *  Configuration register for input signal 120
- */
-#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4)
-/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 120.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC120_IN_SEL    0x0000003FU
-#define GPIO_FUNC120_IN_SEL_M  (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S)
-#define GPIO_FUNC120_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC120_IN_SEL_S  0
-/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC120_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC120_IN_INV_SEL_M  (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S)
-#define GPIO_FUNC120_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC120_IN_INV_SEL_S  6
-/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG120_IN_SEL    (BIT(7))
-#define GPIO_SIG120_IN_SEL_M  (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S)
-#define GPIO_SIG120_IN_SEL_V  0x00000001U
-#define GPIO_SIG120_IN_SEL_S  7
-
-/** GPIO_FUNC121_IN_SEL_CFG_REG register
- *  Configuration register for input signal 121
- */
-#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a8)
-/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 48;
- *  Configures to select a pin from the 25 GPIO pins to connect the input signal 121.\\
- *  0: Select GPIO0\\
- *  1: Select GPIO1\\
- *  ......\\
- *  23: Select GPIO23\\
- *  24: Select GPIO24\\
- *  Or\\
- *  0x20: A constantly high input\\
- *  0x30: A constantly low input\\
- */
-#define GPIO_FUNC121_IN_SEL    0x0000003FU
-#define GPIO_FUNC121_IN_SEL_M  (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S)
-#define GPIO_FUNC121_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC121_IN_SEL_S  0
-/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to invert the input value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC121_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC121_IN_INV_SEL_M  (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S)
-#define GPIO_FUNC121_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC121_IN_INV_SEL_S  6
-/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to route signals via GPIO matrix.\\
- *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
- *  IO MUX.\\
- *  1: Route signals via GPIO matrix.\\
- */
-#define GPIO_SIG121_IN_SEL    (BIT(7))
-#define GPIO_SIG121_IN_SEL_M  (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S)
-#define GPIO_SIG121_IN_SEL_V  0x00000001U
-#define GPIO_SIG121_IN_SEL_S  7
-
-/** GPIO_FUNC0_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO0 output
- */
-#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac4)
-/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO0.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 0 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC0_OUT_SEL    0x000001FFU
-#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
-#define GPIO_FUNC0_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC0_OUT_SEL_S  0
-/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
-#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC0_OUT_INV_SEL_S  9
-/** GPIO_FUNC0_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 0 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC0_OE_SEL    (BIT(10))
-#define GPIO_FUNC0_OE_SEL_M  (GPIO_FUNC0_OE_SEL_V << GPIO_FUNC0_OE_SEL_S)
-#define GPIO_FUNC0_OE_SEL_V  0x00000001U
-#define GPIO_FUNC0_OE_SEL_S  10
-/** GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC0_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC0_OE_INV_SEL_M  (GPIO_FUNC0_OE_INV_SEL_V << GPIO_FUNC0_OE_INV_SEL_S)
-#define GPIO_FUNC0_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC0_OE_INV_SEL_S  11
-
-/** GPIO_FUNC1_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO1 output
- */
-#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac8)
-/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO1.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 1 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC1_OUT_SEL    0x000001FFU
-#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
-#define GPIO_FUNC1_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC1_OUT_SEL_S  0
-/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
-#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC1_OUT_INV_SEL_S  9
-/** GPIO_FUNC1_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 1 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC1_OE_SEL    (BIT(10))
-#define GPIO_FUNC1_OE_SEL_M  (GPIO_FUNC1_OE_SEL_V << GPIO_FUNC1_OE_SEL_S)
-#define GPIO_FUNC1_OE_SEL_V  0x00000001U
-#define GPIO_FUNC1_OE_SEL_S  10
-/** GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC1_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC1_OE_INV_SEL_M  (GPIO_FUNC1_OE_INV_SEL_V << GPIO_FUNC1_OE_INV_SEL_S)
-#define GPIO_FUNC1_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC1_OE_INV_SEL_S  11
-
-/** GPIO_FUNC2_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO2 output
- */
-#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xacc)
-/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO2.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 2 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC2_OUT_SEL    0x000001FFU
-#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
-#define GPIO_FUNC2_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC2_OUT_SEL_S  0
-/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
-#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC2_OUT_INV_SEL_S  9
-/** GPIO_FUNC2_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 2 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC2_OE_SEL    (BIT(10))
-#define GPIO_FUNC2_OE_SEL_M  (GPIO_FUNC2_OE_SEL_V << GPIO_FUNC2_OE_SEL_S)
-#define GPIO_FUNC2_OE_SEL_V  0x00000001U
-#define GPIO_FUNC2_OE_SEL_S  10
-/** GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC2_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC2_OE_INV_SEL_M  (GPIO_FUNC2_OE_INV_SEL_V << GPIO_FUNC2_OE_INV_SEL_S)
-#define GPIO_FUNC2_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC2_OE_INV_SEL_S  11
-
-/** GPIO_FUNC3_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO3 output
- */
-#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad0)
-/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO3.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 3 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC3_OUT_SEL    0x000001FFU
-#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
-#define GPIO_FUNC3_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC3_OUT_SEL_S  0
-/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
-#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC3_OUT_INV_SEL_S  9
-/** GPIO_FUNC3_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 3 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC3_OE_SEL    (BIT(10))
-#define GPIO_FUNC3_OE_SEL_M  (GPIO_FUNC3_OE_SEL_V << GPIO_FUNC3_OE_SEL_S)
-#define GPIO_FUNC3_OE_SEL_V  0x00000001U
-#define GPIO_FUNC3_OE_SEL_S  10
-/** GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC3_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC3_OE_INV_SEL_M  (GPIO_FUNC3_OE_INV_SEL_V << GPIO_FUNC3_OE_INV_SEL_S)
-#define GPIO_FUNC3_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC3_OE_INV_SEL_S  11
-
-/** GPIO_FUNC4_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO4 output
- */
-#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4)
-/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO4.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 4 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC4_OUT_SEL    0x000001FFU
-#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
-#define GPIO_FUNC4_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC4_OUT_SEL_S  0
-/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
-#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC4_OUT_INV_SEL_S  9
-/** GPIO_FUNC4_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 4 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC4_OE_SEL    (BIT(10))
-#define GPIO_FUNC4_OE_SEL_M  (GPIO_FUNC4_OE_SEL_V << GPIO_FUNC4_OE_SEL_S)
-#define GPIO_FUNC4_OE_SEL_V  0x00000001U
-#define GPIO_FUNC4_OE_SEL_S  10
-/** GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC4_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC4_OE_INV_SEL_M  (GPIO_FUNC4_OE_INV_SEL_V << GPIO_FUNC4_OE_INV_SEL_S)
-#define GPIO_FUNC4_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC4_OE_INV_SEL_S  11
-
-/** GPIO_FUNC5_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO5 output
- */
-#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8)
-/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO5.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 5 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC5_OUT_SEL    0x000001FFU
-#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
-#define GPIO_FUNC5_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC5_OUT_SEL_S  0
-/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
-#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC5_OUT_INV_SEL_S  9
-/** GPIO_FUNC5_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 5 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC5_OE_SEL    (BIT(10))
-#define GPIO_FUNC5_OE_SEL_M  (GPIO_FUNC5_OE_SEL_V << GPIO_FUNC5_OE_SEL_S)
-#define GPIO_FUNC5_OE_SEL_V  0x00000001U
-#define GPIO_FUNC5_OE_SEL_S  10
-/** GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC5_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC5_OE_INV_SEL_M  (GPIO_FUNC5_OE_INV_SEL_V << GPIO_FUNC5_OE_INV_SEL_S)
-#define GPIO_FUNC5_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC5_OE_INV_SEL_S  11
-
-/** GPIO_FUNC6_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO6 output
- */
-#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc)
-/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO6.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 6 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC6_OUT_SEL    0x000001FFU
-#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
-#define GPIO_FUNC6_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC6_OUT_SEL_S  0
-/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
-#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_OUT_INV_SEL_S  9
-/** GPIO_FUNC6_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 6 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC6_OE_SEL    (BIT(10))
-#define GPIO_FUNC6_OE_SEL_M  (GPIO_FUNC6_OE_SEL_V << GPIO_FUNC6_OE_SEL_S)
-#define GPIO_FUNC6_OE_SEL_V  0x00000001U
-#define GPIO_FUNC6_OE_SEL_S  10
-/** GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC6_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC6_OE_INV_SEL_M  (GPIO_FUNC6_OE_INV_SEL_V << GPIO_FUNC6_OE_INV_SEL_S)
-#define GPIO_FUNC6_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_OE_INV_SEL_S  11
-
-/** GPIO_FUNC7_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO7 output
- */
-#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0)
-/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO7.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 7 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC7_OUT_SEL    0x000001FFU
-#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
-#define GPIO_FUNC7_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC7_OUT_SEL_S  0
-/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
-#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_OUT_INV_SEL_S  9
-/** GPIO_FUNC7_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 7 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC7_OE_SEL    (BIT(10))
-#define GPIO_FUNC7_OE_SEL_M  (GPIO_FUNC7_OE_SEL_V << GPIO_FUNC7_OE_SEL_S)
-#define GPIO_FUNC7_OE_SEL_V  0x00000001U
-#define GPIO_FUNC7_OE_SEL_S  10
-/** GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC7_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC7_OE_INV_SEL_M  (GPIO_FUNC7_OE_INV_SEL_V << GPIO_FUNC7_OE_INV_SEL_S)
-#define GPIO_FUNC7_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_OE_INV_SEL_S  11
-
-/** GPIO_FUNC8_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO8 output
- */
-#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4)
-/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO8.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 8 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC8_OUT_SEL    0x000001FFU
-#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
-#define GPIO_FUNC8_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC8_OUT_SEL_S  0
-/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
-#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_OUT_INV_SEL_S  9
-/** GPIO_FUNC8_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 8 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC8_OE_SEL    (BIT(10))
-#define GPIO_FUNC8_OE_SEL_M  (GPIO_FUNC8_OE_SEL_V << GPIO_FUNC8_OE_SEL_S)
-#define GPIO_FUNC8_OE_SEL_V  0x00000001U
-#define GPIO_FUNC8_OE_SEL_S  10
-/** GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC8_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC8_OE_INV_SEL_M  (GPIO_FUNC8_OE_INV_SEL_V << GPIO_FUNC8_OE_INV_SEL_S)
-#define GPIO_FUNC8_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_OE_INV_SEL_S  11
-
-/** GPIO_FUNC9_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO9 output
- */
-#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8)
-/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO9.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 9 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
- *  output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC9_OUT_SEL    0x000001FFU
-#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
-#define GPIO_FUNC9_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC9_OUT_SEL_S  0
-/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
-#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_OUT_INV_SEL_S  9
-/** GPIO_FUNC9_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 9 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC9_OE_SEL    (BIT(10))
-#define GPIO_FUNC9_OE_SEL_M  (GPIO_FUNC9_OE_SEL_V << GPIO_FUNC9_OE_SEL_S)
-#define GPIO_FUNC9_OE_SEL_V  0x00000001U
-#define GPIO_FUNC9_OE_SEL_S  10
-/** GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC9_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC9_OE_INV_SEL_M  (GPIO_FUNC9_OE_INV_SEL_V << GPIO_FUNC9_OE_INV_SEL_S)
-#define GPIO_FUNC9_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_OE_INV_SEL_S  11
-
-/** GPIO_FUNC10_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO10 output
- */
-#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec)
-/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO10.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 10 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC10_OUT_SEL    0x000001FFU
-#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
-#define GPIO_FUNC10_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC10_OUT_SEL_S  0
-/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
-#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_OUT_INV_SEL_S  9
-/** GPIO_FUNC10_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 10 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC10_OE_SEL    (BIT(10))
-#define GPIO_FUNC10_OE_SEL_M  (GPIO_FUNC10_OE_SEL_V << GPIO_FUNC10_OE_SEL_S)
-#define GPIO_FUNC10_OE_SEL_V  0x00000001U
-#define GPIO_FUNC10_OE_SEL_S  10
-/** GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC10_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC10_OE_INV_SEL_M  (GPIO_FUNC10_OE_INV_SEL_V << GPIO_FUNC10_OE_INV_SEL_S)
-#define GPIO_FUNC10_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_OE_INV_SEL_S  11
-
-/** GPIO_FUNC11_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO11 output
- */
-#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0)
-/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO11.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 11 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC11_OUT_SEL    0x000001FFU
-#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
-#define GPIO_FUNC11_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC11_OUT_SEL_S  0
-/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
-#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_OUT_INV_SEL_S  9
-/** GPIO_FUNC11_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 11 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC11_OE_SEL    (BIT(10))
-#define GPIO_FUNC11_OE_SEL_M  (GPIO_FUNC11_OE_SEL_V << GPIO_FUNC11_OE_SEL_S)
-#define GPIO_FUNC11_OE_SEL_V  0x00000001U
-#define GPIO_FUNC11_OE_SEL_S  10
-/** GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC11_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC11_OE_INV_SEL_M  (GPIO_FUNC11_OE_INV_SEL_V << GPIO_FUNC11_OE_INV_SEL_S)
-#define GPIO_FUNC11_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_OE_INV_SEL_S  11
-
-/** GPIO_FUNC12_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO12 output
- */
-#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4)
-/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO12.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 12 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC12_OUT_SEL    0x000001FFU
-#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
-#define GPIO_FUNC12_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC12_OUT_SEL_S  0
-/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
-#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_OUT_INV_SEL_S  9
-/** GPIO_FUNC12_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 12 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC12_OE_SEL    (BIT(10))
-#define GPIO_FUNC12_OE_SEL_M  (GPIO_FUNC12_OE_SEL_V << GPIO_FUNC12_OE_SEL_S)
-#define GPIO_FUNC12_OE_SEL_V  0x00000001U
-#define GPIO_FUNC12_OE_SEL_S  10
-/** GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC12_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC12_OE_INV_SEL_M  (GPIO_FUNC12_OE_INV_SEL_V << GPIO_FUNC12_OE_INV_SEL_S)
-#define GPIO_FUNC12_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_OE_INV_SEL_S  11
-
-/** GPIO_FUNC13_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO13 output
- */
-#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8)
-/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO13.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 13 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC13_OUT_SEL    0x000001FFU
-#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
-#define GPIO_FUNC13_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC13_OUT_SEL_S  0
-/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
-#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_OUT_INV_SEL_S  9
-/** GPIO_FUNC13_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 13 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC13_OE_SEL    (BIT(10))
-#define GPIO_FUNC13_OE_SEL_M  (GPIO_FUNC13_OE_SEL_V << GPIO_FUNC13_OE_SEL_S)
-#define GPIO_FUNC13_OE_SEL_V  0x00000001U
-#define GPIO_FUNC13_OE_SEL_S  10
-/** GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC13_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC13_OE_INV_SEL_M  (GPIO_FUNC13_OE_INV_SEL_V << GPIO_FUNC13_OE_INV_SEL_S)
-#define GPIO_FUNC13_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_OE_INV_SEL_S  11
-
-/** GPIO_FUNC14_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO14 output
- */
-#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc)
-/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO14.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 14 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC14_OUT_SEL    0x000001FFU
-#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
-#define GPIO_FUNC14_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC14_OUT_SEL_S  0
-/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
-#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_OUT_INV_SEL_S  9
-/** GPIO_FUNC14_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 14 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC14_OE_SEL    (BIT(10))
-#define GPIO_FUNC14_OE_SEL_M  (GPIO_FUNC14_OE_SEL_V << GPIO_FUNC14_OE_SEL_S)
-#define GPIO_FUNC14_OE_SEL_V  0x00000001U
-#define GPIO_FUNC14_OE_SEL_S  10
-/** GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC14_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC14_OE_INV_SEL_M  (GPIO_FUNC14_OE_INV_SEL_V << GPIO_FUNC14_OE_INV_SEL_S)
-#define GPIO_FUNC14_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_OE_INV_SEL_S  11
-
-/** GPIO_FUNC15_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO15 output
- */
-#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00)
-/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO15.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 15 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC15_OUT_SEL    0x000001FFU
-#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
-#define GPIO_FUNC15_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC15_OUT_SEL_S  0
-/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
-#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_OUT_INV_SEL_S  9
-/** GPIO_FUNC15_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 15 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC15_OE_SEL    (BIT(10))
-#define GPIO_FUNC15_OE_SEL_M  (GPIO_FUNC15_OE_SEL_V << GPIO_FUNC15_OE_SEL_S)
-#define GPIO_FUNC15_OE_SEL_V  0x00000001U
-#define GPIO_FUNC15_OE_SEL_S  10
-/** GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC15_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC15_OE_INV_SEL_M  (GPIO_FUNC15_OE_INV_SEL_V << GPIO_FUNC15_OE_INV_SEL_S)
-#define GPIO_FUNC15_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_OE_INV_SEL_S  11
-
-/** GPIO_FUNC16_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO16 output
- */
-#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04)
-/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO16.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 16 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC16_OUT_SEL    0x000001FFU
-#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
-#define GPIO_FUNC16_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC16_OUT_SEL_S  0
-/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
-#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_OUT_INV_SEL_S  9
-/** GPIO_FUNC16_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 16 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC16_OE_SEL    (BIT(10))
-#define GPIO_FUNC16_OE_SEL_M  (GPIO_FUNC16_OE_SEL_V << GPIO_FUNC16_OE_SEL_S)
-#define GPIO_FUNC16_OE_SEL_V  0x00000001U
-#define GPIO_FUNC16_OE_SEL_S  10
-/** GPIO_FUNC16_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC16_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC16_OE_INV_SEL_M  (GPIO_FUNC16_OE_INV_SEL_V << GPIO_FUNC16_OE_INV_SEL_S)
-#define GPIO_FUNC16_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_OE_INV_SEL_S  11
-
-/** GPIO_FUNC17_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO17 output
- */
-#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08)
-/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO17.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 17 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC17_OUT_SEL    0x000001FFU
-#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
-#define GPIO_FUNC17_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC17_OUT_SEL_S  0
-/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
-#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_OUT_INV_SEL_S  9
-/** GPIO_FUNC17_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 17 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC17_OE_SEL    (BIT(10))
-#define GPIO_FUNC17_OE_SEL_M  (GPIO_FUNC17_OE_SEL_V << GPIO_FUNC17_OE_SEL_S)
-#define GPIO_FUNC17_OE_SEL_V  0x00000001U
-#define GPIO_FUNC17_OE_SEL_S  10
-/** GPIO_FUNC17_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC17_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC17_OE_INV_SEL_M  (GPIO_FUNC17_OE_INV_SEL_V << GPIO_FUNC17_OE_INV_SEL_S)
-#define GPIO_FUNC17_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_OE_INV_SEL_S  11
-
-/** GPIO_FUNC18_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO18 output
- */
-#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c)
-/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO18.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 18 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC18_OUT_SEL    0x000001FFU
-#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
-#define GPIO_FUNC18_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC18_OUT_SEL_S  0
-/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
-#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC18_OUT_INV_SEL_S  9
-/** GPIO_FUNC18_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 18 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC18_OE_SEL    (BIT(10))
-#define GPIO_FUNC18_OE_SEL_M  (GPIO_FUNC18_OE_SEL_V << GPIO_FUNC18_OE_SEL_S)
-#define GPIO_FUNC18_OE_SEL_V  0x00000001U
-#define GPIO_FUNC18_OE_SEL_S  10
-/** GPIO_FUNC18_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC18_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC18_OE_INV_SEL_M  (GPIO_FUNC18_OE_INV_SEL_V << GPIO_FUNC18_OE_INV_SEL_S)
-#define GPIO_FUNC18_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC18_OE_INV_SEL_S  11
-
-/** GPIO_FUNC19_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO19 output
- */
-#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10)
-/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO19.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 19 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC19_OUT_SEL    0x000001FFU
-#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
-#define GPIO_FUNC19_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC19_OUT_SEL_S  0
-/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
-#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC19_OUT_INV_SEL_S  9
-/** GPIO_FUNC19_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 19 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC19_OE_SEL    (BIT(10))
-#define GPIO_FUNC19_OE_SEL_M  (GPIO_FUNC19_OE_SEL_V << GPIO_FUNC19_OE_SEL_S)
-#define GPIO_FUNC19_OE_SEL_V  0x00000001U
-#define GPIO_FUNC19_OE_SEL_S  10
-/** GPIO_FUNC19_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC19_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC19_OE_INV_SEL_M  (GPIO_FUNC19_OE_INV_SEL_V << GPIO_FUNC19_OE_INV_SEL_S)
-#define GPIO_FUNC19_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC19_OE_INV_SEL_S  11
-
-/** GPIO_FUNC20_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO20 output
- */
-#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14)
-/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO20.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 20 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC20_OUT_SEL    0x000001FFU
-#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
-#define GPIO_FUNC20_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC20_OUT_SEL_S  0
-/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
-#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC20_OUT_INV_SEL_S  9
-/** GPIO_FUNC20_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 20 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC20_OE_SEL    (BIT(10))
-#define GPIO_FUNC20_OE_SEL_M  (GPIO_FUNC20_OE_SEL_V << GPIO_FUNC20_OE_SEL_S)
-#define GPIO_FUNC20_OE_SEL_V  0x00000001U
-#define GPIO_FUNC20_OE_SEL_S  10
-/** GPIO_FUNC20_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC20_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC20_OE_INV_SEL_M  (GPIO_FUNC20_OE_INV_SEL_V << GPIO_FUNC20_OE_INV_SEL_S)
-#define GPIO_FUNC20_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC20_OE_INV_SEL_S  11
-
-/** GPIO_FUNC21_OUT_SEL_CFG_REG register
- *  Configuration register for GPIO21 output
- */
-#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18)
-/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
- *  output from GPIO21.\\
- *  0: Select signal 0\\
- *  1: Select signal 1\\
- *  ......\\
- *  254: Select signal 254\\
- *  255: Select signal 255\\
- *  Or\\
- *  256: Bit 21 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
- *  and output enable.
- *
- *  For the detailed signal list, see Table <a
- *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
- *  "
- */
-#define GPIO_FUNC21_OUT_SEL    0x000001FFU
-#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
-#define GPIO_FUNC21_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC21_OUT_SEL_S  0
-/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  Configures whether or not to invert the output value.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
-#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC21_OUT_INV_SEL_S  9
-/** GPIO_FUNC21_OE_SEL : R/W; bitpos: [10]; default: 0;
- *  Configures to select the source of output enable signal.\\
- *  0: Use output enable signal from peripheral.\\
- *  1: Force the output enable signal to be sourced from bit 21 of GPIO_ENABLE_REG. \\
- */
-#define GPIO_FUNC21_OE_SEL    (BIT(10))
-#define GPIO_FUNC21_OE_SEL_M  (GPIO_FUNC21_OE_SEL_V << GPIO_FUNC21_OE_SEL_S)
-#define GPIO_FUNC21_OE_SEL_V  0x00000001U
-#define GPIO_FUNC21_OE_SEL_S  10
-/** GPIO_FUNC21_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert the output enable signal.\\
- *  0: Not invert\\
- *  1: Invert\\
- */
-#define GPIO_FUNC21_OE_INV_SEL    (BIT(11))
-#define GPIO_FUNC21_OE_INV_SEL_M  (GPIO_FUNC21_OE_INV_SEL_V << GPIO_FUNC21_OE_INV_SEL_S)
-#define GPIO_FUNC21_OE_INV_SEL_V  0x00000001U
-#define GPIO_FUNC21_OE_INV_SEL_S  11
-
-/** GPIO_CLOCK_GATE_REG register
- *  GPIO clock gate register
- */
-#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0xdf8)
-/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Configures whether or not to enable clock gate.\\
- *  0: Not enable\\
- *  1: Enable, the clock is free running. \\
- */
-#define GPIO_CLK_EN    (BIT(0))
-#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
-#define GPIO_CLK_EN_V  0x00000001U
-#define GPIO_CLK_EN_S  0
-
-/** GPIO_DATE_REG register
- *  GPIO version register
- */
-#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0xdfc)
-/** GPIO_DATE : R/W; bitpos: [27:0]; default: 37753392;
- *  Version control register. \\
- */
-#define GPIO_DATE    0x0FFFFFFFU
-#define GPIO_DATE_M  (GPIO_DATE_V << GPIO_DATE_S)
-#define GPIO_DATE_V  0x0FFFFFFFU
-#define GPIO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/gpio_struct.h b/components/soc/esp32c61/include/soc/gpio_struct.h
deleted file mode 100644
index 853d209c9e2..00000000000
--- a/components/soc/esp32c61/include/soc/gpio_struct.h
+++ /dev/null
@@ -1,489 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of strap register
- *  Strapping pin register
- */
-typedef union {
-    struct {
-        /** strapping : RO; bitpos: [15:0]; default: 0;
-         *  Represents the values of GPIO strapping pins.
-         *
-         *  - bit0 ~ bit1: invalid
-         *  - bit2: GPIO8
-         *  - bit3: GPIO9
-         *  - bit4: GPIO7
-         *  - bit5 ~ bit15: invalid
-         */
-        uint32_t strapping:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} gpio_strap_reg_t;
-
-/** Type of out register
- *  GPIO output register
- */
-typedef union {
-    struct {
-        /** out_data_orig : R/W/SC/WTC; bitpos: [28:0]; default: 0;
-         *  Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\
-         *  0: Low level\\
-         *  1: High level\\
-         *  The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24
-         *  respectively. Bit25 ~ bit31 are invalid.\\
-         */
-        uint32_t out_data_orig:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_out_reg_t;
-
-/** Type of out_w1ts register
- *  GPIO output set register
- */
-typedef union {
-    struct {
-        /** out_w1ts : WT; bitpos: [28:0]; default: 0;
-         *  Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~
-         *  GPIO24.\\
-         *  0: Not set\\
-         *  1: The corresponding bit in GPIO_OUT_REG will be set to 1\\
-         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
-         *  Recommended operation: use this register to set GPIO_OUT_REG. \\
-         */
-        uint32_t out_w1ts:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_out_w1ts_reg_t;
-
-/** Type of out_w1tc register
- *  GPIO output clear register
- */
-typedef union {
-    struct {
-        /** out_w1tc : WT; bitpos: [28:0]; default: 0;
-         *  Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
-         *  GPIO24 output.\\
-         *  0: Not clear\\
-         *  1: The corresponding bit in GPIO_OUT_REG will be cleared.\\
-         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
-         *  Recommended operation: use this register to clear GPIO_OUT_REG. \\
-         */
-        uint32_t out_w1tc:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_out_w1tc_reg_t;
-
-/** Type of enable register
- *  GPIO output enable register
- */
-typedef union {
-    struct {
-        /** enable_data : R/W/WTC; bitpos: [28:0]; default: 0;
-         *  Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\
-         *  0: Not enable\\
-         *  1: Enable\\
-         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
-         */
-        uint32_t enable_data:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_enable_reg_t;
-
-/** Type of enable_w1ts register
- *  GPIO output enable set register
- */
-typedef union {
-    struct {
-        /** enable_w1ts : WT; bitpos: [28:0]; default: 0;
-         *  Configures whether or not to set the output enable register GPIO_ENABLE_REG of
-         *  GPIO0 ~ GPIO24.\\
-         *  0: Not set\\
-         *  1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\
-         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
-         *  Recommended operation: use this register to set GPIO_ENABLE_REG.\\
-         */
-        uint32_t enable_w1ts:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_enable_w1ts_reg_t;
-
-/** Type of enable_w1tc register
- *  GPIO output enable clear register
- */
-typedef union {
-    struct {
-        /** enable_w1tc : WT; bitpos: [28:0]; default: 0;
-         *  Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
-         *  GPIO0 ~ GPIO24. \\
-         *  0: Not clear\\
-         *  1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\
-         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
-         *  Recommended operation: use this register to clear GPIO_ENABLE_REG.\\
-         */
-        uint32_t enable_w1tc:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_enable_w1tc_reg_t;
-
-/** Type of in register
- *  GPIO input register
- */
-typedef union {
-    struct {
-        /** in_data_next : RO; bitpos: [28:0]; default: 0;
-         *  Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input
-         *  value:\\
-         *  0: Low level\\
-         *  1: High level\\
-         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
-         */
-        uint32_t in_data_next:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_in_reg_t;
-
-
-/** Group: Interrupt Status Registers */
-/** Type of status register
- *  GPIO interrupt status register
- */
-typedef union {
-    struct {
-        /** status_interrupt : R/W/WTC; bitpos: [28:0]; default: 0;
-         *  The interrupt status of GPIO0 ~ GPIO24, can be configured by the software.
-         *
-         *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
-         *  - Each bit represents the status of its corresponding GPIO:
-         *
-         *  - 0: Represents the GPIO does not generate the interrupt configured by
-         *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
-         *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
-         *  or this bit is configured to 1 by the software.
-         *
-         */
-        uint32_t status_interrupt:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_status_reg_t;
-
-/** Type of status_w1ts register
- *  GPIO interrupt status set register
- */
-typedef union {
-    struct {
-        /** status_w1ts : WT; bitpos: [28:0]; default: 0;
-         *  Configures whether or not to set the interrupt status register
-         *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
-         *
-         *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
-         *  - If the value 1 is written to a bit here, the corresponding bit in
-         *  GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
-         *  register to set GPIO_STATUS_INTERRUPT.
-         */
-        uint32_t status_w1ts:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_status_w1ts_reg_t;
-
-/** Type of status_w1tc register
- *  GPIO interrupt status clear register
- */
-typedef union {
-    struct {
-        /** status_w1tc : WT; bitpos: [28:0]; default: 0;
-         *  Configures whether or not to clear the interrupt status register
-         *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
-         *
-         *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
-         *  - If the value 1 is written to a bit here, the corresponding bit in
-         *  GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
-         *  register to clear GPIO_STATUS_INTERRUPT.
-         */
-        uint32_t status_w1tc:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_status_w1tc_reg_t;
-
-/** Type of procpu_int register
- *  CPU interrupt status register
- */
-typedef union {
-    struct {
-        /** procpu_int : RO; bitpos: [28:0]; default: 0;
-         *  Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\
-         *  0: Represents CPU interrupt is not enabled, or the GPIO does not generate the
-         *  interrupt configured by GPIO_PIN$n_INT_TYPE.\\
-         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
-         *  after the CPU interrupt is enabled.\\
-         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This
-         *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
-         *  enable signal (bit13 of GPIO_PIN$n_REG). \\
-         */
-        uint32_t procpu_int:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_procpu_int_reg_t;
-
-/** Type of status_next register
- *  GPIO interrupt source register
- */
-typedef union {
-    struct {
-        /** status_interrupt_next : RO; bitpos: [28:0]; default: 0;
-         *  Represents the interrupt source signal of GPIO0 ~ GPIO24.\\
-         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each
-         *  bit represents:\\
-         *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\
-         *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\
-         *  The interrupt could be rising edge interrupt, falling edge interrupt, level
-         *  sensitive interrupt and any edge interrupt.\\
-         */
-        uint32_t status_interrupt_next:29;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} gpio_status_next_reg_t;
-
-
-/** Group: Pin Configuration Registers */
-/** Type of pinn register
- *  GPIOn configuration register
- */
-typedef union {
-    struct {
-        /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
-         *  operating clock for the second-level synchronization.\\
-         *  0: Not synchronize\\
-         *  1: Synchronize on falling edge\\
-         *  2: Synchronize on rising edge\\
-         *  3: Synchronize on rising edge\\
-         */
-        uint32_t pinn_sync2_bypass:2;
-        /** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
-         *  Configures to select pin drive mode. \\
-         *  0: Normal output\\
-         *  1: Open drain output \\
-         */
-        uint32_t pinn_pad_driver:1;
-        /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
-         *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
-         *  operating clock for the first-level synchronization.\\
-         *  0: Not synchronize\\
-         *  1: Synchronize on falling edge\\
-         *  2: Synchronize on rising edge\\
-         *  3: Synchronize on rising edge\\
-         */
-        uint32_t pinn_sync1_bypass:2;
-        uint32_t reserved_5:2;
-        /** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
-         *  Configures GPIO interrupt type.\\
-         *  0: GPIO interrupt disabled\\
-         *  1: Rising edge trigger\\
-         *  2: Falling edge trigger\\
-         *  3: Any edge trigger\\
-         *  4: Low level trigger\\
-         *  5: High level trigger\\
-         */
-        uint32_t pinn_int_type:3;
-        /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable GPIO wake-up function.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         *  This function only wakes up the CPU from Light-sleep. \\
-         */
-        uint32_t pinn_wakeup_enable:1;
-        uint32_t reserved_11:2;
-        /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0;
-         *  Configures whether or not to enable CPU interrupt.
-         *
-         *  - bit13: Configures whether or not to enable CPU interrupt:\\
-         *  0: Disable\\
-         *  1: Enable\\
-         *  - bit14 ~ bit17: invalid
-         */
-        uint32_t pinn_int_ena:5;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} gpio_pinn_reg_t;
-
-
-/** Group: Input Configuration Registers */
-/** Type of func0_in_sel_cfg register
- *  Configuration register for input signal 0
- */
-typedef union {
-    struct {
-        /** func_in_sel : R/W; bitpos: [5:0]; default: 48;
-         *  Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\
-         *  0: Select GPIO0\\
-         *  1: Select GPIO1\\
-         *  ......\\
-         *  23: Select GPIO23\\
-         *  24: Select GPIO24\\
-         *  Or\\
-         *  0x20: A constantly high input\\
-         *  0x30: A constantly low input\\
-         */
-        uint32_t func_in_sel:6;
-        /** func_in_inv_sel : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to invert the input value.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t func_in_inv_sel:1;
-        /** sig_in_sel : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to route signals via GPIO matrix.\\
-         *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
-         *  IO MUX.\\
-         *  1: Route signals via GPIO matrix.\\
-         */
-        uint32_t sig_in_sel:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_func_in_sel_cfg_reg_t;
-
-/** Group: Output Configuration Registers */
-/** Type of funcn_out_sel_cfg register
- *  Configuration register for GPIOn output
- */
-typedef union {
-    struct {
-        /** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
-         *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
-         *  output from GPIOn.\\
-         *  0: Select signal 0\\
-         *  1: Select signal 1\\
-         *  ......\\
-         *  254: Select signal 254\\
-         *  255: Select signal 255\\
-         *  Or\\
-         *  256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
-         *  output enable.
-         *
-         *  For the detailed signal list, see Table <a
-         *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
-         *  "
-         */
-        uint32_t funcn_out_sel:9;
-        /** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
-         *  Configures whether or not to invert the output value.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t funcn_out_inv_sel:1;
-        /** funcn_oe_sel : R/W; bitpos: [10]; default: 0;
-         *  Configures to select the source of output enable signal.\\
-         *  0: Use output enable signal from peripheral.\\
-         *  1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\
-         */
-        uint32_t funcn_oe_sel:1;
-        /** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert the output enable signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t funcn_oe_inv_sel:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} gpio_funcn_out_sel_cfg_reg_t;
-
-
-/** Group: Clock Gate Register */
-/** Type of clock_gate register
- *  GPIO clock gate register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Configures whether or not to enable clock gate.\\
-         *  0: Not enable\\
-         *  1: Enable, the clock is free running. \\
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} gpio_clock_gate_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  GPIO version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 37753392;
-         *  Version control register. \\
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_date_reg_t;
-
-
-typedef struct {
-    volatile gpio_strap_reg_t strap;
-    volatile gpio_out_reg_t out;
-    volatile gpio_out_w1ts_reg_t out_w1ts;
-    volatile gpio_out_w1tc_reg_t out_w1tc;
-    uint32_t reserved_010[9];
-    volatile gpio_enable_reg_t enable;
-    volatile gpio_enable_w1ts_reg_t enable_w1ts;
-    volatile gpio_enable_w1tc_reg_t enable_w1tc;
-    uint32_t reserved_040[9];
-    volatile gpio_in_reg_t in;
-    uint32_t reserved_068[3];
-    volatile gpio_status_reg_t status;
-    volatile gpio_status_w1ts_reg_t status_w1ts;
-    volatile gpio_status_w1tc_reg_t status_w1tc;
-    uint32_t reserved_080[9];
-    volatile gpio_procpu_int_reg_t procpu_int;
-    uint32_t reserved_0a8[3];
-    volatile gpio_status_next_reg_t status_next;
-    uint32_t reserved_0b8[3];
-    volatile gpio_pinn_reg_t pinn[22];  // 0-21 are fanned out, 22-24 are not fanned out but padded out, 25-28 are not padded out. Only 0-21 are available.
-    uint32_t reserved_11c[106];
-    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256];  //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
-    uint32_t reserved_4ac[256];
-    volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[22];
-    uint32_t reserved_b1c[183];
-    volatile gpio_clock_gate_reg_t clock_gate;
-    volatile gpio_date_reg_t date;
-} gpio_dev_t;
-
-extern gpio_dev_t GPIO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(gpio_dev_t) == 0xe00, "Invalid size of gpio_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/i2s_reg.h b/components/soc/esp32c61/include/soc/i2s_reg.h
deleted file mode 100644
index a7f16f4d612..00000000000
--- a/components/soc/esp32c61/include/soc/i2s_reg.h
+++ /dev/null
@@ -1,1275 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** I2S_INT_RAW_REG register
- *  I2S interrupt raw register, valid in level.
- */
-#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
-/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_RAW    (BIT(0))
-#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
-#define I2S_RX_DONE_INT_RAW_V  0x00000001U
-#define I2S_RX_DONE_INT_RAW_S  0
-/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_RAW    (BIT(1))
-#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
-#define I2S_TX_DONE_INT_RAW_V  0x00000001U
-#define I2S_TX_DONE_INT_RAW_S  1
-/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_RAW    (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
-#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_RX_HUNG_INT_RAW_S  2
-/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_RAW    (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
-#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_TX_HUNG_INT_RAW_S  3
-
-/** I2S_INT_ST_REG register
- *  I2S interrupt status register.
- */
-#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
-/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ST    (BIT(0))
-#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
-#define I2S_RX_DONE_INT_ST_V  0x00000001U
-#define I2S_RX_DONE_INT_ST_S  0
-/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ST    (BIT(1))
-#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
-#define I2S_TX_DONE_INT_ST_V  0x00000001U
-#define I2S_TX_DONE_INT_ST_S  1
-/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ST    (BIT(2))
-#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
-#define I2S_RX_HUNG_INT_ST_V  0x00000001U
-#define I2S_RX_HUNG_INT_ST_S  2
-/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ST    (BIT(3))
-#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
-#define I2S_TX_HUNG_INT_ST_V  0x00000001U
-#define I2S_TX_HUNG_INT_ST_S  3
-
-/** I2S_INT_ENA_REG register
- *  I2S interrupt enable register.
- */
-#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
-/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ENA    (BIT(0))
-#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
-#define I2S_RX_DONE_INT_ENA_V  0x00000001U
-#define I2S_RX_DONE_INT_ENA_S  0
-/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ENA    (BIT(1))
-#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
-#define I2S_TX_DONE_INT_ENA_V  0x00000001U
-#define I2S_TX_DONE_INT_ENA_S  1
-/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ENA    (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
-#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_RX_HUNG_INT_ENA_S  2
-/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ENA    (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
-#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_TX_HUNG_INT_ENA_S  3
-
-/** I2S_INT_CLR_REG register
- *  I2S interrupt clear register.
- */
-#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
-/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_CLR    (BIT(0))
-#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
-#define I2S_RX_DONE_INT_CLR_V  0x00000001U
-#define I2S_RX_DONE_INT_CLR_S  0
-/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_CLR    (BIT(1))
-#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
-#define I2S_TX_DONE_INT_CLR_V  0x00000001U
-#define I2S_TX_DONE_INT_CLR_S  1
-/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_CLR    (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
-#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_RX_HUNG_INT_CLR_S  2
-/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_CLR    (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
-#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_TX_HUNG_INT_CLR_S  3
-
-/** I2S_RX_CONF_REG register
- *  I2S RX configure register
- */
-#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
-/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset receiver
- */
-#define I2S_RX_RESET    (BIT(0))
-#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
-#define I2S_RX_RESET_V  0x00000001U
-#define I2S_RX_RESET_S  0
-/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Rx AFIFO
- */
-#define I2S_RX_FIFO_RESET    (BIT(1))
-#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
-#define I2S_RX_FIFO_RESET_V  0x00000001U
-#define I2S_RX_FIFO_RESET_S  1
-/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start receiving data
- */
-#define I2S_RX_START    (BIT(2))
-#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
-#define I2S_RX_START_V  0x00000001U
-#define I2S_RX_START_S  2
-/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave receiver mode
- */
-#define I2S_RX_SLAVE_MOD    (BIT(3))
-#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
-#define I2S_RX_SLAVE_MOD_V  0x00000001U
-#define I2S_RX_SLAVE_MOD_S  3
-/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
- *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
- *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
- */
-#define I2S_RX_STOP_MODE    0x00000003U
-#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
-#define I2S_RX_STOP_MODE_V  0x00000003U
-#define I2S_RX_STOP_MODE_S  4
-/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable receiver  in mono mode
- */
-#define I2S_RX_MONO    (BIT(6))
-#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
-#define I2S_RX_MONO_V  0x00000001U
-#define I2S_RX_MONO_S  6
-/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
- */
-#define I2S_RX_BIG_ENDIAN    (BIT(7))
-#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
-#define I2S_RX_BIG_ENDIAN_V  0x00000001U
-#define I2S_RX_BIG_ENDIAN_S  7
-/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_RX_UPDATE    (BIT(8))
-#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
-#define I2S_RX_UPDATE_V  0x00000001U
-#define I2S_RX_UPDATE_S  8
-/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
- *  channel data value is valid in I2S RX mono mode.
- */
-#define I2S_RX_MONO_FST_VLD    (BIT(9))
-#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
-#define I2S_RX_MONO_FST_VLD_V  0x00000001U
-#define I2S_RX_MONO_FST_VLD_S  9
-/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
- *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_RX_PCM_CONF    0x00000003U
-#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
-#define I2S_RX_PCM_CONF_V  0x00000003U
-#define I2S_RX_PCM_CONF_S  10
-/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass Compress/Decompress module for received data.
- */
-#define I2S_RX_PCM_BYPASS    (BIT(12))
-#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
-#define I2S_RX_PCM_BYPASS_V  0x00000001U
-#define I2S_RX_PCM_BYPASS_S  12
-/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
- *  Set this bit to enable receiver in Phillips standard mode
- */
-#define I2S_RX_MSB_SHIFT    (BIT(13))
-#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
-#define I2S_RX_MSB_SHIFT_V  0x00000001U
-#define I2S_RX_MSB_SHIFT_S  13
-/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
- */
-#define I2S_RX_LEFT_ALIGN    (BIT(15))
-#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
-#define I2S_RX_LEFT_ALIGN_V  0x00000001U
-#define I2S_RX_LEFT_ALIGN_S  15
-/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
- */
-#define I2S_RX_24_FILL_EN    (BIT(16))
-#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
-#define I2S_RX_24_FILL_EN_V  0x00000001U
-#define I2S_RX_24_FILL_EN_S  16
-/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
- *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
- */
-#define I2S_RX_WS_IDLE_POL    (BIT(17))
-#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
-#define I2S_RX_WS_IDLE_POL_V  0x00000001U
-#define I2S_RX_WS_IDLE_POL_S  17
-/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
- *  is received first.
- */
-#define I2S_RX_BIT_ORDER    (BIT(18))
-#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
-#define I2S_RX_BIT_ORDER_V  0x00000001U
-#define I2S_RX_BIT_ORDER_S  18
-/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Rx mode . 0: Disable.
- */
-#define I2S_RX_TDM_EN    (BIT(19))
-#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
-#define I2S_RX_TDM_EN_V  0x00000001U
-#define I2S_RX_TDM_EN_S  19
-/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Rx mode . 0: Disable.
- */
-#define I2S_RX_PDM_EN    (BIT(20))
-#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
-#define I2S_RX_PDM_EN_V  0x00000001U
-#define I2S_RX_PDM_EN_S  20
-/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
- *  Bit clock configuration bits in receiver mode.
- */
-#define I2S_RX_BCK_DIV_NUM    0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
-#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_S  21
-
-/** I2S_TX_CONF_REG register
- *  I2S TX configure register
- */
-#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
-/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset transmitter
- */
-#define I2S_TX_RESET    (BIT(0))
-#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
-#define I2S_TX_RESET_V  0x00000001U
-#define I2S_TX_RESET_S  0
-/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Tx AFIFO
- */
-#define I2S_TX_FIFO_RESET    (BIT(1))
-#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
-#define I2S_TX_FIFO_RESET_V  0x00000001U
-#define I2S_TX_FIFO_RESET_S  1
-/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start transmitting data
- */
-#define I2S_TX_START    (BIT(2))
-#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
-#define I2S_TX_START_V  0x00000001U
-#define I2S_TX_START_S  2
-/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave transmitter mode
- */
-#define I2S_TX_SLAVE_MOD    (BIT(3))
-#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
-#define I2S_TX_SLAVE_MOD_V  0x00000001U
-#define I2S_TX_SLAVE_MOD_S  3
-/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
- */
-#define I2S_TX_STOP_EN    (BIT(4))
-#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
-#define I2S_TX_STOP_EN_V  0x00000001U
-#define I2S_TX_STOP_EN_S  4
-/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
- *  1: The value of Left channel data is equal to the value of right channel data in
- *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
- *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
- */
-#define I2S_TX_CHAN_EQUAL    (BIT(5))
-#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
-#define I2S_TX_CHAN_EQUAL_V  0x00000001U
-#define I2S_TX_CHAN_EQUAL_S  5
-/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable transmitter in mono mode
- */
-#define I2S_TX_MONO    (BIT(6))
-#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
-#define I2S_TX_MONO_V  0x00000001U
-#define I2S_TX_MONO_S  6
-/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
- *  value.
- */
-#define I2S_TX_BIG_ENDIAN    (BIT(7))
-#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
-#define I2S_TX_BIG_ENDIAN_V  0x00000001U
-#define I2S_TX_BIG_ENDIAN_S  7
-/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_TX_UPDATE    (BIT(8))
-#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
-#define I2S_TX_UPDATE_V  0x00000001U
-#define I2S_TX_UPDATE_S  8
-/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
- *  channel data value is valid in I2S TX mono mode.
- */
-#define I2S_TX_MONO_FST_VLD    (BIT(9))
-#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
-#define I2S_TX_MONO_FST_VLD_V  0x00000001U
-#define I2S_TX_MONO_FST_VLD_S  9
-/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
- *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_TX_PCM_CONF    0x00000003U
-#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
-#define I2S_TX_PCM_CONF_V  0x00000003U
-#define I2S_TX_PCM_CONF_S  10
-/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass  Compress/Decompress module for transmitted data.
- */
-#define I2S_TX_PCM_BYPASS    (BIT(12))
-#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
-#define I2S_TX_PCM_BYPASS_V  0x00000001U
-#define I2S_TX_PCM_BYPASS_S  12
-/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
- *  Set this bit to enable transmitter in Phillips standard mode
- */
-#define I2S_TX_MSB_SHIFT    (BIT(13))
-#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
-#define I2S_TX_MSB_SHIFT_V  0x00000001U
-#define I2S_TX_MSB_SHIFT_S  13
-/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
- *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
- *  generate pos/neg edge in master mode.
- */
-#define I2S_TX_BCK_NO_DLY    (BIT(14))
-#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
-#define I2S_TX_BCK_NO_DLY_V  0x00000001U
-#define I2S_TX_BCK_NO_DLY_S  14
-/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
- */
-#define I2S_TX_LEFT_ALIGN    (BIT(15))
-#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
-#define I2S_TX_LEFT_ALIGN_V  0x00000001U
-#define I2S_TX_LEFT_ALIGN_S  15
-/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
- */
-#define I2S_TX_24_FILL_EN    (BIT(16))
-#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
-#define I2S_TX_24_FILL_EN_V  0x00000001U
-#define I2S_TX_24_FILL_EN_S  16
-/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
- *  WS should be 1 when sending left channel data, and WS is 0in right channel.
- */
-#define I2S_TX_WS_IDLE_POL    (BIT(17))
-#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
-#define I2S_TX_WS_IDLE_POL_V  0x00000001U
-#define I2S_TX_WS_IDLE_POL_S  17
-/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
- *  sent first.
- */
-#define I2S_TX_BIT_ORDER    (BIT(18))
-#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
-#define I2S_TX_BIT_ORDER_V  0x00000001U
-#define I2S_TX_BIT_ORDER_S  18
-/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Tx mode . 0: Disable.
- */
-#define I2S_TX_TDM_EN    (BIT(19))
-#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
-#define I2S_TX_TDM_EN_V  0x00000001U
-#define I2S_TX_TDM_EN_S  19
-/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Tx mode . 0: Disable.
- */
-#define I2S_TX_PDM_EN    (BIT(20))
-#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
-#define I2S_TX_PDM_EN_V  0x00000001U
-#define I2S_TX_PDM_EN_S  20
-/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
- *  Bit clock configuration bits in transmitter mode.
- */
-#define I2S_TX_BCK_DIV_NUM    0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
-#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_S  21
-/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
- *  I2S transmitter channel mode configuration bits.
- */
-#define I2S_TX_CHAN_MOD    0x00000007U
-#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
-#define I2S_TX_CHAN_MOD_V  0x00000007U
-#define I2S_TX_CHAN_MOD_S  27
-/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
- *  Enable signal loop back mode with transmitter module and receiver module sharing
- *  the same WS and BCK signals.
- */
-#define I2S_SIG_LOOPBACK    (BIT(30))
-#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
-#define I2S_SIG_LOOPBACK_V  0x00000001U
-#define I2S_SIG_LOOPBACK_S  30
-
-/** I2S_RX_CONF1_REG register
- *  I2S RX configure register 1
- */
-#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
-/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
- *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
- *  T_bck
- */
-#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
-#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
-#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
-#define I2S_RX_TDM_WS_WIDTH_S  0
-/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
- *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_RX_BITS_MOD    0x0000001FU
-#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
-#define I2S_RX_BITS_MOD_V  0x0000001FU
-#define I2S_RX_BITS_MOD_S  14
-/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
- *  I2S Rx half sample bits -1.
- */
-#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
-#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
-#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
-#define I2S_RX_HALF_SAMPLE_BITS_S  19
-/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
- *  The Rx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
-#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_S  27
-
-/** I2S_TX_CONF1_REG register
- *  I2S TX configure register 1
- */
-#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
-/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
- *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
- *  T_bck
- */
-#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
-#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
-#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
-#define I2S_TX_TDM_WS_WIDTH_S  0
-/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
- *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_TX_BITS_MOD    0x0000001FU
-#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
-#define I2S_TX_BITS_MOD_V  0x0000001FU
-#define I2S_TX_BITS_MOD_S  14
-/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
- *  I2S Tx half sample bits -1.
- */
-#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
-#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
-#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
-#define I2S_TX_HALF_SAMPLE_BITS_S  19
-/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
- *  The Tx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
-#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_S  27
-
-/** I2S_TX_PCM2PDM_CONF_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40)
-/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0;
- *  I2S TX PDM bypass hp filter or not. The option has been removed.
- */
-#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
-#define I2S_TX_PDM_HP_BYPASS_M  (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S)
-#define I2S_TX_PDM_HP_BYPASS_V  0x00000001U
-#define I2S_TX_PDM_HP_BYPASS_S  0
-/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
- *  I2S TX PDM OSR2 value
- */
-#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
-#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_S  1
-/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
- *  I2S TX PDM prescale for sigmadelta
- */
-#define I2S_TX_PDM_PRESCALE    0x000000FFU
-#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
-#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
-#define I2S_TX_PDM_PRESCALE_S  5
-/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
-#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_S  13
-/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
-#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_S  15
-/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
-#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
-/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
-/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
- *  I2S TX PDM sigmadelta dither2 value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
-/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
- *  I2S TX PDM sigmadelta dither value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
-/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
- *  I2S TX PDM dac mode enable
- */
-#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
-#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_2OUT_EN_S  23
-/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
- *  I2S TX PDM dac 2channel enable
- */
-#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
-#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_MODE_EN_S  24
-/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
- *  I2S TX PDM Converter enable
- */
-#define I2S_PCM2PDM_CONV_EN    (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
-#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
-#define I2S_PCM2PDM_CONV_EN_S  25
-
-/** I2S_TX_PCM2PDM_CONF1_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44)
-/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
- *  I2S TX PDM Fp
- */
-#define I2S_TX_PDM_FP    0x000003FFU
-#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
-#define I2S_TX_PDM_FP_V  0x000003FFU
-#define I2S_TX_PDM_FP_S  0
-/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
- *  I2S TX PDM Fs
- */
-#define I2S_TX_PDM_FS    0x000003FFU
-#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
-#define I2S_TX_PDM_FS_V  0x000003FFU
-#define I2S_TX_PDM_FS_S  10
-/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
- *  I2S_TX_IIR_HP_MULT12_5[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
-#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_S  20
-/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
- *  I2S_TX_IIR_HP_MULT12_0[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
-#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_S  23
-
-/** I2S_RX_PDM2PCM_CONF_REG register
- *  I2S RX configure register
- */
-#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x48)
-/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable PDM2PCM RX mode. 0: DIsable.
- */
-#define I2S_RX_PDM2PCM_EN    (BIT(19))
-#define I2S_RX_PDM2PCM_EN_M  (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
-#define I2S_RX_PDM2PCM_EN_V  0x00000001U
-#define I2S_RX_PDM2PCM_EN_S  19
-/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
- *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
- *  sampling rate is 128. 0: down sampling rate is 64.
- */
-#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
-#define I2S_RX_PDM_SINC_DSR_16_EN_M  (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
-#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
-#define I2S_RX_PDM_SINC_DSR_16_EN_S  20
-/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
- *  Configure PDM RX amplify number.
- */
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
-/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
- *  I2S PDM RX bypass hp filter or not.
- */
-#define I2S_RX_PDM_HP_BYPASS    (BIT(25))
-#define I2S_RX_PDM_HP_BYPASS_M  (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
-#define I2S_RX_PDM_HP_BYPASS_V  0x00000001U
-#define I2S_RX_PDM_HP_BYPASS_S  25
-/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
- *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
- *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
- */
-#define I2S_RX_IIR_HP_MULT12_5    0x00000007U
-#define I2S_RX_IIR_HP_MULT12_5_M  (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
-#define I2S_RX_IIR_HP_MULT12_5_V  0x00000007U
-#define I2S_RX_IIR_HP_MULT12_5_S  26
-/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
- *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
- *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
- */
-#define I2S_RX_IIR_HP_MULT12_0    0x00000007U
-#define I2S_RX_IIR_HP_MULT12_0_M  (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
-#define I2S_RX_IIR_HP_MULT12_0_V  0x00000007U
-#define I2S_RX_IIR_HP_MULT12_0_S  29
-
-/** I2S_RX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
-/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
-#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
-/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
-#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
-/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
-#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
-/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
-#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
-/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
-#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
-/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
-#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
-/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
-#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
-/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
-#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
-/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
-#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN8_EN_S  8
-/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
-#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN9_EN_S  9
-/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
-#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN10_EN_S  10
-/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
-#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN11_EN_S  11
-/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
-#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN12_EN_S  12
-/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
-#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN13_EN_S  13
-/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
-#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN14_EN_S  14
-/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
-#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN15_EN_S  15
-/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
-#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
-
-/** I2S_TX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
-/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
-#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN0_EN_S  0
-/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
-#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN1_EN_S  1
-/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
-#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN2_EN_S  2
-/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
-#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN3_EN_S  3
-/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
-#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN4_EN_S  4
-/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
-#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN5_EN_S  5
-/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
-#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN6_EN_S  6
-/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
-#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN7_EN_S  7
-/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
-#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN8_EN_S  8
-/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
-#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN9_EN_S  9
-/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
-#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN10_EN_S  10
-/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
-#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN11_EN_S  11
-/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
-#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN12_EN_S  12
-/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
-#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN13_EN_S  13
-/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
-#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN14_EN_S  14
-/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
-#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN15_EN_S  15
-/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
-#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
-/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
- *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
- *  only the data of the enabled channels is sent, then this bit should be set. Clear
- *  it when all the data stored in DMA TX buffer is for enabled channels.
- */
-#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
-#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
-#define I2S_TX_TDM_SKIP_MSK_EN_S  20
-
-/** I2S_RX_TIMING_REG register
- *  I2S RX timing control register
- */
-#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
-/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD_IN_DM    0x00000003U
-#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
-#define I2S_RX_SD_IN_DM_V  0x00000003U
-#define I2S_RX_SD_IN_DM_S  0
-/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0;
- *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD1_IN_DM    0x00000003U
-#define I2S_RX_SD1_IN_DM_M  (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S)
-#define I2S_RX_SD1_IN_DM_V  0x00000003U
-#define I2S_RX_SD1_IN_DM_S  4
-/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0;
- *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD2_IN_DM    0x00000003U
-#define I2S_RX_SD2_IN_DM_M  (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S)
-#define I2S_RX_SD2_IN_DM_V  0x00000003U
-#define I2S_RX_SD2_IN_DM_S  8
-/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0;
- *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD3_IN_DM    0x00000003U
-#define I2S_RX_SD3_IN_DM_M  (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S)
-#define I2S_RX_SD3_IN_DM_V  0x00000003U
-#define I2S_RX_SD3_IN_DM_S  12
-/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_OUT_DM    0x00000003U
-#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
-#define I2S_RX_WS_OUT_DM_V  0x00000003U
-#define I2S_RX_WS_OUT_DM_S  16
-/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_OUT_DM    0x00000003U
-#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
-#define I2S_RX_BCK_OUT_DM_V  0x00000003U
-#define I2S_RX_BCK_OUT_DM_S  20
-/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_IN_DM    0x00000003U
-#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
-#define I2S_RX_WS_IN_DM_V  0x00000003U
-#define I2S_RX_WS_IN_DM_S  24
-/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_IN_DM    0x00000003U
-#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
-#define I2S_RX_BCK_IN_DM_V  0x00000003U
-#define I2S_RX_BCK_IN_DM_S  28
-
-/** I2S_TX_TIMING_REG register
- *  I2S TX timing control register
- */
-#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
-/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD_OUT_DM    0x00000003U
-#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
-#define I2S_TX_SD_OUT_DM_V  0x00000003U
-#define I2S_TX_SD_OUT_DM_S  0
-/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
- *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD1_OUT_DM    0x00000003U
-#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
-#define I2S_TX_SD1_OUT_DM_V  0x00000003U
-#define I2S_TX_SD1_OUT_DM_S  4
-/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_OUT_DM    0x00000003U
-#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
-#define I2S_TX_WS_OUT_DM_V  0x00000003U
-#define I2S_TX_WS_OUT_DM_S  16
-/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_OUT_DM    0x00000003U
-#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
-#define I2S_TX_BCK_OUT_DM_V  0x00000003U
-#define I2S_TX_BCK_OUT_DM_S  20
-/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_IN_DM    0x00000003U
-#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
-#define I2S_TX_WS_IN_DM_V  0x00000003U
-#define I2S_TX_WS_IN_DM_S  24
-/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_IN_DM    0x00000003U
-#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
-#define I2S_TX_BCK_IN_DM_V  0x00000003U
-#define I2S_TX_BCK_IN_DM_S  28
-
-/** I2S_LC_HUNG_CONF_REG register
- *  I2S HUNG configure register.
- */
-#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
-/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
- *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
- *  when fifo hung counter is equal to this value
- */
-#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
-#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_S  0
-/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
- *  The bits are used to scale tick counter threshold. The tick counter is reset when
- *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
- */
-#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
-/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
- *  The enable bit for FIFO timeout
- */
-#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
-#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
-#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
-
-/** I2S_RXEOF_NUM_REG register
- *  I2S RX data number control register.
- */
-#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
-/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
- *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
- *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
- */
-#define I2S_RX_EOF_NUM    0x00000FFFU
-#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
-#define I2S_RX_EOF_NUM_V  0x00000FFFU
-#define I2S_RX_EOF_NUM_S  0
-
-/** I2S_CONF_SIGLE_DATA_REG register
- *  I2S signal data register
- */
-#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
-/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
- *  The configured constant channel data to be sent out.
- */
-#define I2S_SINGLE_DATA    0xFFFFFFFFU
-#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
-#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
-#define I2S_SINGLE_DATA_S  0
-
-/** I2S_STATE_REG register
- *  I2S TX status register
- */
-#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
-/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
- *  1: i2s_tx is idle state. 0: i2s_tx is working.
- */
-#define I2S_TX_IDLE    (BIT(0))
-#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
-#define I2S_TX_IDLE_V  0x00000001U
-#define I2S_TX_IDLE_S  0
-
-/** I2S_ETM_CONF_REG register
- *  I2S ETM configure register
- */
-#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
-/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
- *  I2S ETM send x words event. When sending word number of
- *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
-#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_S  0
-/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
- *  I2S ETM receive x words event. When receiving word number of
- *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
-
-/** I2S_FIFO_CNT_REG register
- *  I2S sync counter register
- */
-#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x74)
-/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
- *  tx fifo counter value.
- */
-#define I2S_TX_FIFO_CNT    0x7FFFFFFFU
-#define I2S_TX_FIFO_CNT_M  (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S)
-#define I2S_TX_FIFO_CNT_V  0x7FFFFFFFU
-#define I2S_TX_FIFO_CNT_S  0
-/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset tx fifo counter.
- */
-#define I2S_TX_FIFO_CNT_RST    (BIT(31))
-#define I2S_TX_FIFO_CNT_RST_M  (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S)
-#define I2S_TX_FIFO_CNT_RST_V  0x00000001U
-#define I2S_TX_FIFO_CNT_RST_S  31
-
-/** I2S_BCK_CNT_REG register
- *  I2S sync counter register
- */
-#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x78)
-/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
- *  tx bck counter value.
- */
-#define I2S_TX_BCK_CNT    0x7FFFFFFFU
-#define I2S_TX_BCK_CNT_M  (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S)
-#define I2S_TX_BCK_CNT_V  0x7FFFFFFFU
-#define I2S_TX_BCK_CNT_S  0
-/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset tx bck counter.
- */
-#define I2S_TX_BCK_CNT_RST    (BIT(31))
-#define I2S_TX_BCK_CNT_RST_M  (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S)
-#define I2S_TX_BCK_CNT_RST_V  0x00000001U
-#define I2S_TX_BCK_CNT_RST_S  31
-
-/** I2S_CLK_GATE_REG register
- *  Clock gate register
- */
-#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0x7c)
-/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  set this bit to enable clock gate
- */
-#define I2S_CLK_EN    (BIT(0))
-#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
-#define I2S_CLK_EN_V  0x00000001U
-#define I2S_CLK_EN_S  0
-
-/** I2S_DATE_REG register
- *  Version control register
- */
-#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80)
-/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024;
- *  I2S version control register
- */
-#define I2S_DATE    0x0FFFFFFFU
-#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
-#define I2S_DATE_V  0x0FFFFFFFU
-#define I2S_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/i2s_struct.h b/components/soc/esp32c61/include/soc/i2s_struct.h
deleted file mode 100644
index a0ff42939e7..00000000000
--- a/components/soc/esp32c61/include/soc/i2s_struct.h
+++ /dev/null
@@ -1,1010 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  I2S interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_raw:1;
-        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_raw:1;
-        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_raw:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_raw_reg_t;
-
-/** Type of int_st register
- *  I2S interrupt status register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_st:1;
-        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_st:1;
-        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_st:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_st_reg_t;
-
-/** Type of int_ena register
- *  I2S interrupt enable register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_ena:1;
-        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_ena_reg_t;
-
-/** Type of int_clr register
- *  I2S interrupt clear register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_clr:1;
-        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_clr:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of rx_conf register
- *  I2S RX configure register
- */
-typedef union {
-    struct {
-        /** rx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset receiver
-         */
-        uint32_t rx_reset:1;
-        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Rx AFIFO
-         */
-        uint32_t rx_fifo_reset:1;
-        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start receiving data
-         */
-        uint32_t rx_start:1;
-        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave receiver mode
-         */
-        uint32_t rx_slave_mod:1;
-        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
-         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
-         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-         */
-        uint32_t rx_stop_mode:2;
-        /** rx_mono : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable receiver  in mono mode
-         */
-        uint32_t rx_mono:1;
-        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-         */
-        uint32_t rx_big_endian:1;
-        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t rx_update:1;
-        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
-         *  channel data value is valid in I2S RX mono mode.
-         */
-        uint32_t rx_mono_fst_vld:1;
-        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
-         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t rx_pcm_conf:2;
-        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass Compress/Decompress module for received data.
-         */
-        uint32_t rx_pcm_bypass:1;
-        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to enable receiver in Phillips standard mode
-         */
-        uint32_t rx_msb_shift:1;
-        uint32_t reserved_14:1;
-        /** rx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-         */
-        uint32_t rx_left_align:1;
-        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-         */
-        uint32_t rx_24_fill_en:1;
-        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
-         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-         */
-        uint32_t rx_ws_idle_pol:1;
-        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
-         *  is received first.
-         */
-        uint32_t rx_bit_order:1;
-        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_tdm_en:1;
-        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_pdm_en:1;
-        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
-         *  Bit clock configuration bits in receiver mode.
-         */
-        uint32_t rx_bck_div_num:6;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} i2s_rx_conf_reg_t;
-
-/** Type of rx_conf1 register
- *  I2S RX configure register 1
- */
-typedef union {
-    struct {
-        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
-         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
-         *  T_bck
-         */
-        uint32_t rx_tdm_ws_width:9;
-        uint32_t reserved_9:5;
-        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
-         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t rx_bits_mod:5;
-        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
-         *  I2S Rx half sample bits -1.
-         */
-        uint32_t rx_half_sample_bits:8;
-        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
-         *  The Rx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t rx_tdm_chan_bits:5;
-    };
-    uint32_t val;
-} i2s_rx_conf1_reg_t;
-
-/** Type of rx_pdm2pcm_conf register
- *  I2S RX configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:19;
-        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable PDM2PCM RX mode. 0: DIsable.
-         */
-        uint32_t rx_pdm2pcm_en:1;
-        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
-         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
-         *  sampling rate is 128. 0: down sampling rate is 64.
-         */
-        uint32_t rx_pdm_sinc_dsr_16_en:1;
-        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
-         *  Configure PDM RX amplify number.
-         */
-        uint32_t rx_pdm2pcm_amplify_num:4;
-        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
-         *  I2S PDM RX bypass hp filter or not.
-         */
-        uint32_t rx_pdm_hp_bypass:1;
-        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
-         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
-         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
-         */
-        uint32_t rx_iir_hp_mult12_5:3;
-        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
-         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
-         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
-         */
-        uint32_t rx_iir_hp_mult12_0:3;
-    };
-    uint32_t val;
-} i2s_rx_pdm2pcm_conf_reg_t;
-
-/** Type of rx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan0_en:1;
-        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan1_en:1;
-        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan2_en:1;
-        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan3_en:1;
-        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan4_en:1;
-        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan5_en:1;
-        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan6_en:1;
-        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan7_en:1;
-        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan8_en:1;
-        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan9_en:1;
-        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan10_en:1;
-        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan11_en:1;
-        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan12_en:1;
-        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan13_en:1;
-        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan14_en:1;
-        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan15_en:1;
-        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t rx_tdm_tot_chan_num:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_rx_tdm_ctrl_reg_t;
-
-/** Type of rxeof_num register
- *  I2S RX data number control register.
- */
-typedef union {
-    struct {
-        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
-         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
-         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
-         */
-        uint32_t rx_eof_num:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_rxeof_num_reg_t;
-
-
-/** Group: TX Control and configuration registers */
-/** Type of tx_conf register
- *  I2S TX configure register
- */
-typedef union {
-    struct {
-        /** tx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset transmitter
-         */
-        uint32_t tx_reset:1;
-        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Tx AFIFO
-         */
-        uint32_t tx_fifo_reset:1;
-        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start transmitting data
-         */
-        uint32_t tx_start:1;
-        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave transmitter mode
-         */
-        uint32_t tx_slave_mod:1;
-        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
-         */
-        uint32_t tx_stop_en:1;
-        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
-         *  1: The value of Left channel data is equal to the value of right channel data in
-         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
-         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-         */
-        uint32_t tx_chan_equal:1;
-        /** tx_mono : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable transmitter in mono mode
-         */
-        uint32_t tx_mono:1;
-        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
-         *  value.
-         */
-        uint32_t tx_big_endian:1;
-        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t tx_update:1;
-        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
-         *  channel data value is valid in I2S TX mono mode.
-         */
-        uint32_t tx_mono_fst_vld:1;
-        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
-         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t tx_pcm_conf:2;
-        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
-         */
-        uint32_t tx_pcm_bypass:1;
-        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to enable transmitter in Phillips standard mode
-         */
-        uint32_t tx_msb_shift:1;
-        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
-         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
-         *  generate pos/neg edge in master mode.
-         */
-        uint32_t tx_bck_no_dly:1;
-        /** tx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-         */
-        uint32_t tx_left_align:1;
-        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-         */
-        uint32_t tx_24_fill_en:1;
-        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
-         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
-         */
-        uint32_t tx_ws_idle_pol:1;
-        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
-         *  sent first.
-         */
-        uint32_t tx_bit_order:1;
-        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_tdm_en:1;
-        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_pdm_en:1;
-        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
-         *  Bit clock configuration bits in transmitter mode.
-         */
-        uint32_t tx_bck_div_num:6;
-        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
-         *  I2S transmitter channel mode configuration bits.
-         */
-        uint32_t tx_chan_mod:3;
-        /** sig_loopback : R/W; bitpos: [30]; default: 0;
-         *  Enable signal loop back mode with transmitter module and receiver module sharing
-         *  the same WS and BCK signals.
-         */
-        uint32_t sig_loopback:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} i2s_tx_conf_reg_t;
-
-/** Type of tx_conf1 register
- *  I2S TX configure register 1
- */
-typedef union {
-    struct {
-        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
-         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
-         *  T_bck
-         */
-        uint32_t tx_tdm_ws_width:9;
-        uint32_t reserved_9:5;
-        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
-         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t tx_bits_mod:5;
-        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
-         *  I2S Tx half sample bits -1.
-         */
-        uint32_t tx_half_sample_bits:8;
-        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
-         *  The Tx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t tx_tdm_chan_bits:5;
-    };
-    uint32_t val;
-} i2s_tx_conf1_reg_t;
-
-/** Type of tx_pcm2pdm_conf register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
-         *  I2S TX PDM bypass hp filter or not. The option has been removed.
-         */
-        uint32_t tx_pdm_hp_bypass:1;
-        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
-         *  I2S TX PDM OSR2 value
-         */
-        uint32_t tx_pdm_sinc_osr2:4;
-        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
-         *  I2S TX PDM prescale for sigmadelta
-         */
-        uint32_t tx_pdm_prescale:8;
-        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_hp_in_shift:2;
-        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_lp_in_shift:2;
-        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sinc_in_shift:2;
-        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sigmadelta_in_shift:2;
-        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
-         *  I2S TX PDM sigmadelta dither2 value
-         */
-        uint32_t tx_pdm_sigmadelta_dither2:1;
-        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
-         *  I2S TX PDM sigmadelta dither value
-         */
-        uint32_t tx_pdm_sigmadelta_dither:1;
-        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
-         *  I2S TX PDM dac mode enable
-         */
-        uint32_t tx_pdm_dac_2out_en:1;
-        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
-         *  I2S TX PDM dac 2channel enable
-         */
-        uint32_t tx_pdm_dac_mode_en:1;
-        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
-         *  I2S TX PDM Converter enable
-         */
-        uint32_t pcm2pdm_conv_en:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf_reg_t;
-
-/** Type of tx_pcm2pdm_conf1 register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
-         *  I2S TX PDM Fp
-         */
-        uint32_t tx_pdm_fp:10;
-        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
-         *  I2S TX PDM Fs
-         */
-        uint32_t tx_pdm_fs:10;
-        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_5[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_5:3;
-        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_0[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_0:3;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf1_reg_t;
-
-/** Type of tx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan0_en:1;
-        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan1_en:1;
-        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan2_en:1;
-        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan3_en:1;
-        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan4_en:1;
-        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan5_en:1;
-        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan6_en:1;
-        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan7_en:1;
-        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan8_en:1;
-        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan9_en:1;
-        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan10_en:1;
-        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan11_en:1;
-        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan12_en:1;
-        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan13_en:1;
-        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan14_en:1;
-        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan15_en:1;
-        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t tx_tdm_tot_chan_num:4;
-        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
-         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
-         *  only the data of the enabled channels is sent, then this bit should be set. Clear
-         *  it when all the data stored in DMA TX buffer is for enabled channels.
-         */
-        uint32_t tx_tdm_skip_msk_en:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} i2s_tx_tdm_ctrl_reg_t;
-
-
-/** Group: RX clock and timing registers */
-/** Type of rx_timing register
- *  I2S RX timing control register
- */
-typedef union {
-    struct {
-        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd_in_dm:2;
-        uint32_t reserved_2:2;
-        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
-         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd1_in_dm:2;
-        uint32_t reserved_6:2;
-        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
-         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd2_in_dm:2;
-        uint32_t reserved_10:2;
-        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
-         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd3_in_dm:2;
-        uint32_t reserved_14:2;
-        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_rx_timing_reg_t;
-
-
-/** Group: TX clock and timing registers */
-/** Type of tx_timing register
- *  I2S TX timing control register
- */
-typedef union {
-    struct {
-        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd_out_dm:2;
-        uint32_t reserved_2:2;
-        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
-         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd1_out_dm:2;
-        uint32_t reserved_6:10;
-        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_tx_timing_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of lc_hung_conf register
- *  I2S HUNG configure register.
- */
-typedef union {
-    struct {
-        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
-         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
-         *  when fifo hung counter is equal to this value
-         */
-        uint32_t lc_fifo_timeout:8;
-        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
-         *  The bits are used to scale tick counter threshold. The tick counter is reset when
-         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-         */
-        uint32_t lc_fifo_timeout_shift:3;
-        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
-         *  The enable bit for FIFO timeout
-         */
-        uint32_t lc_fifo_timeout_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_lc_hung_conf_reg_t;
-
-/** Type of conf_sigle_data register
- *  I2S signal data register
- */
-typedef union {
-    struct {
-        /** single_data : R/W; bitpos: [31:0]; default: 0;
-         *  The configured constant channel data to be sent out.
-         */
-        uint32_t single_data:32;
-    };
-    uint32_t val;
-} i2s_conf_sigle_data_reg_t;
-
-
-/** Group: TX status registers */
-/** Type of state register
- *  I2S TX status register
- */
-typedef union {
-    struct {
-        /** tx_idle : RO; bitpos: [0]; default: 1;
-         *  1: i2s_tx is idle state. 0: i2s_tx is working.
-         */
-        uint32_t tx_idle:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} i2s_state_reg_t;
-
-
-/** Group: ETM registers */
-/** Type of etm_conf register
- *  I2S ETM configure register
- */
-typedef union {
-    struct {
-        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
-         *  I2S ETM send x words event. When sending word number of
-         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_tx_send_word_num:10;
-        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
-         *  I2S ETM receive x words event. When receiving word number of
-         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_rx_receive_word_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_etm_conf_reg_t;
-
-
-/** Group: Sync counter registers */
-/** Type of fifo_cnt register
- *  I2S sync counter register
- */
-typedef union {
-    struct {
-        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
-         *  tx fifo counter value.
-         */
-        uint32_t tx_fifo_cnt:31;
-        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset tx fifo counter.
-         */
-        uint32_t tx_fifo_cnt_rst:1;
-    };
-    uint32_t val;
-} i2s_fifo_cnt_reg_t;
-
-/** Type of bck_cnt register
- *  I2S sync counter register
- */
-typedef union {
-    struct {
-        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
-         *  tx bck counter value.
-         */
-        uint32_t tx_bck_cnt:31;
-        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset tx bck counter.
-         */
-        uint32_t tx_bck_cnt_rst:1;
-    };
-    uint32_t val;
-} i2s_bck_cnt_reg_t;
-
-
-/** Group: Clock registers */
-/** Type of clk_gate register
- *  Clock gate register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  set this bit to enable clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} i2s_clk_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36713024;
-         *  I2S version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} i2s_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000[3];
-    volatile i2s_int_raw_reg_t int_raw;
-    volatile i2s_int_st_reg_t int_st;
-    volatile i2s_int_ena_reg_t int_ena;
-    volatile i2s_int_clr_reg_t int_clr;
-    uint32_t reserved_01c;
-    volatile i2s_rx_conf_reg_t rx_conf;
-    volatile i2s_tx_conf_reg_t tx_conf;
-    volatile i2s_rx_conf1_reg_t rx_conf1;
-    volatile i2s_tx_conf1_reg_t tx_conf1;
-    uint32_t reserved_030[4];
-    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
-    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
-    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
-    uint32_t reserved_04c;
-    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
-    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
-    volatile i2s_rx_timing_reg_t rx_timing;
-    volatile i2s_tx_timing_reg_t tx_timing;
-    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
-    volatile i2s_rxeof_num_reg_t rxeof_num;
-    volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
-    volatile i2s_state_reg_t state;
-    volatile i2s_etm_conf_reg_t etm_conf;
-    volatile i2s_fifo_cnt_reg_t fifo_cnt;
-    volatile i2s_bck_cnt_reg_t bck_cnt;
-    volatile i2s_clk_gate_reg_t clk_gate;
-    volatile i2s_date_reg_t date;
-} i2s_dev_t;
-
-extern i2s_dev_t I2S;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/interrupts.h b/components/soc/esp32c61/include/soc/interrupts.h
index 105f5f78341..e74342e6e9c 100644
--- a/components/soc/esp32c61/include/soc/interrupts.h
+++ b/components/soc/esp32c61/include/soc/interrupts.h
@@ -53,7 +53,7 @@ typedef enum {
     ETS_HP_APM_M2_INTR_SOURCE,
     ETS_HP_APM_M3_INTR_SOURCE,
     ETS_MSPI_INTR_SOURCE,
-    ETS_I2S1_INTR_SOURCE,
+    ETS_I2S0_INTR_SOURCE,
     ETS_UART0_INTR_SOURCE,
     ETS_UART1_INTR_SOURCE,
     ETS_UART2_INTR_SOURCE,
diff --git a/components/soc/esp32c61/include/soc/io_mux_reg.h b/components/soc/esp32c61/include/soc/io_mux_reg.h
deleted file mode 100644
index 1c330bcfdf5..00000000000
--- a/components/soc/esp32c61/include/soc/io_mux_reg.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Pin used for wakeup from sleep */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
-#define FILTER_EN (BIT(15))
-#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
-#define FILTER_EN_V 1
-#define FILTER_EN_S 15
-
-#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-
-#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
-
-#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
-#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
-#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_PAD_GPIO2
-#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_PAD_MTMS
-#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_PAD_MTDI
-#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_PAD_MTCK
-#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_PAD_MTDO
-#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_PAD_GPIO7
-#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_PAD_GPIO8
-#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_PAD_GPIO9
-#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_PAD_U0RXD
-#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_PAD_U0TXD
-#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_PAD_GPIO12
-#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_PAD_GPIO13
-#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_PAD_SPICS1
-#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_PAD_SPICS0
-#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_PAD_SPIQ
-#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_PAD_SPIWP
-#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_PAD_VDD_SPI
-#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_PAD_SPIHD
-#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_PAD_SPICLK
-#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_PAD_SPID
-
-#define PIN_FUNC_GPIO								1
-
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
-#define USB_INT_PHY0_DM_GPIO_NUM     12
-#define USB_INT_PHY0_DP_GPIO_NUM     13
-
-#define EXT_OSC_SLOW_GPIO_NUM        0
-
-#define MAX_RTC_GPIO_NUM              6
-#define MAX_PAD_GPIO_NUM             21
-#define MAX_GPIO_NUM                 28
-#define HIGH_IO_HOLD_BIT_SHIFT       32
-
-#define REG_IO_MUX_BASE                             DR_REG_IO_MUX_BASE
-// definitions above are inherited from previous version of code, should double check
-
-// definitions below are generated from pin_txt.csv
-#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P            (REG_IO_MUX_BASE + 0x0)
-#define FUNC_XTAL_32K_P_GPIO0                                            1
-#define FUNC_XTAL_32K_P_GPIO0_0                                          0
-
-#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N            (REG_IO_MUX_BASE + 0x4)
-#define FUNC_XTAL_32K_N_GPIO1                                            1
-#define FUNC_XTAL_32K_N_GPIO1_0                                          0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO2                 (REG_IO_MUX_BASE + 0x8)
-#define FUNC_GPIO2_FSPIQ                                                 2
-#define FUNC_GPIO2_GPIO2                                                 1
-#define FUNC_GPIO2_GPIO2_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_MTMS                  (REG_IO_MUX_BASE + 0xC)
-#define FUNC_MTMS_FSPIHD                                                 2
-#define FUNC_MTMS_GPIO3                                                  1
-#define FUNC_MTMS_MTMS                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_MTDI                 (REG_IO_MUX_BASE + 0x10)
-#define FUNC_MTDI_FSPIWP                                                 2
-#define FUNC_MTDI_GPIO4                                                  1
-#define FUNC_MTDI_MTDI                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_MTCK                 (REG_IO_MUX_BASE + 0x14)
-#define FUNC_MTCK_GPIO5                                                  1
-#define FUNC_MTCK_MTCK                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_MTDO                 (REG_IO_MUX_BASE + 0x18)
-#define FUNC_MTDO_FSPICLK                                                2
-#define FUNC_MTDO_GPIO6                                                  1
-#define FUNC_MTDO_MTDO                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO7                (REG_IO_MUX_BASE + 0x1C)
-#define FUNC_GPIO7_FSPID                                                 2
-#define FUNC_GPIO7_GPIO7                                                 1
-#define FUNC_GPIO7_GPIO7_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO8                (REG_IO_MUX_BASE + 0x20)
-#define FUNC_GPIO8_FSPICS0                                               2
-#define FUNC_GPIO8_GPIO8                                                 1
-#define FUNC_GPIO8_GPIO8_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO9                (REG_IO_MUX_BASE + 0x24)
-#define FUNC_GPIO9_GPIO9                                                 1
-#define FUNC_GPIO9_GPIO9_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_U0RXD                (REG_IO_MUX_BASE + 0x28)
-#define FUNC_U0RXD_GPIO10                                                1
-#define FUNC_U0RXD_U0RXD                                                 0
-
-#define PERIPHS_IO_MUX_U_PAD_U0TXD                (REG_IO_MUX_BASE + 0x2C)
-#define FUNC_U0TXD_GPIO11                                                1
-#define FUNC_U0TXD_U0TXD                                                 0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO12               (REG_IO_MUX_BASE + 0x30)
-#define FUNC_GPIO12_GPIO12                                               1
-#define FUNC_GPIO12_GPIO12_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO13               (REG_IO_MUX_BASE + 0x34)
-#define FUNC_GPIO13_GPIO13                                               1
-#define FUNC_GPIO13_GPIO13_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_SPICS1               (REG_IO_MUX_BASE + 0x38)
-#define FUNC_SPICS1_GPIO14                                               1
-#define FUNC_SPICS1_SPICS1                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_SPICS0               (REG_IO_MUX_BASE + 0x3C)
-#define FUNC_SPICS0_GPIO15                                               1
-#define FUNC_SPICS0_SPICS0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_SPIQ                 (REG_IO_MUX_BASE + 0x40)
-#define FUNC_SPIQ_GPIO16                                                 1
-#define FUNC_SPIQ_SPIQ                                                   0
-
-#define PERIPHS_IO_MUX_U_PAD_SPIWP                (REG_IO_MUX_BASE + 0x44)
-#define FUNC_SPIWP_GPIO17                                                1
-#define FUNC_SPIWP_SPIWP                                                 0
-
-#define PERIPHS_IO_MUX_U_PAD_VDD_SPI              (REG_IO_MUX_BASE + 0x48)
-#define FUNC_VDD_SPI_GPIO18                                              1
-#define FUNC_VDD_SPI_GPIO18_0                                            0
-
-#define PERIPHS_IO_MUX_U_PAD_SPIHD                (REG_IO_MUX_BASE + 0x4C)
-#define FUNC_SPIHD_GPIO19                                                1
-#define FUNC_SPIHD_SPIHD                                                 0
-
-#define PERIPHS_IO_MUX_U_PAD_SPICLK               (REG_IO_MUX_BASE + 0x50)
-#define FUNC_SPICLK_GPIO20                                               1
-#define FUNC_SPICLK_SPICLK                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_SPID                 (REG_IO_MUX_BASE + 0x54)
-#define FUNC_SPID_GPIO21                                                 1
-#define FUNC_SPID_SPID                                                   0
-
-/** IO_MUX_DATE_REG register
- *  Version control register
- */
-#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x1fc)
-/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36774288;
- *  Version control register
- */
-#define IO_MUX_REG_DATE    0x0FFFFFFFU
-#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
-#define IO_MUX_REG_DATE_V  0x0FFFFFFFU
-#define IO_MUX_REG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h b/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h
deleted file mode 100644
index cea0165480b..00000000000
--- a/components/soc/esp32c61/include/soc/lp_analog_peri_reg.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_ANA_BOD_MODE0_CNTL_REG register
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
-/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA    (BIT(6))
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M  (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S  6
-/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_PD_RF_ENA    (BIT(7))
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_M  (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_PD_RF_ENA_S  7
-/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INTR_WAIT    0x000003FFU
-#define LP_ANA_BOD_MODE0_INTR_WAIT_M  (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
-#define LP_ANA_BOD_MODE0_INTR_WAIT_V  0x000003FFU
-#define LP_ANA_BOD_MODE0_INTR_WAIT_S  8
-/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_RESET_WAIT    0x000003FFU
-#define LP_ANA_BOD_MODE0_RESET_WAIT_M  (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
-#define LP_ANA_BOD_MODE0_RESET_WAIT_V  0x000003FFU
-#define LP_ANA_BOD_MODE0_RESET_WAIT_S  18
-/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_CNT_CLR    (BIT(28))
-#define LP_ANA_BOD_MODE0_CNT_CLR_M  (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
-#define LP_ANA_BOD_MODE0_CNT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_CNT_CLR_S  28
-/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INTR_ENA    (BIT(29))
-#define LP_ANA_BOD_MODE0_INTR_ENA_M  (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
-#define LP_ANA_BOD_MODE0_INTR_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INTR_ENA_S  29
-/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_RESET_SEL    (BIT(30))
-#define LP_ANA_BOD_MODE0_RESET_SEL_M  (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
-#define LP_ANA_BOD_MODE0_RESET_SEL_V  0x00000001U
-#define LP_ANA_BOD_MODE0_RESET_SEL_S  30
-/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_RESET_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_RESET_ENA_M  (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
-#define LP_ANA_BOD_MODE0_RESET_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_RESET_ENA_S  31
-
-/** LP_ANA_BOD_MODE1_CNTL_REG register
- *  need_des
- */
-#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
-/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE1_RESET_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE1_RESET_ENA_M  (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
-#define LP_ANA_BOD_MODE1_RESET_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE1_RESET_ENA_S  31
-
-/** LP_ANA_POWER_GLITCH_CNTL_REG register
- *  need_des
- */
-#define LP_ANA_POWER_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
-/** LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31:28]; default: 0;
- *  need_des
- */
-#define LP_ANA_POWER_GLITCH_RESET_ENA    0x0000000FU
-#define LP_ANA_POWER_GLITCH_RESET_ENA_M  (LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANA_POWER_GLITCH_RESET_ENA_S)
-#define LP_ANA_POWER_GLITCH_RESET_ENA_V  0x0000000FU
-#define LP_ANA_POWER_GLITCH_RESET_ENA_S  28
-
-/** LP_ANA_FIB_ENABLE_REG register
- *  need_des
- */
-#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
-/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
- *  need_des
- */
-#define LP_ANA_ANA_FIB_ENA    0xFFFFFFFFU
-#define LP_ANA_ANA_FIB_ENA_M  (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
-#define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
-#define LP_ANA_ANA_FIB_ENA_S  0
-
-/** LP_ANA_INT_RAW_REG register
- *  need_des
- */
-#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
-/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INT_RAW    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_RAW_M  (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
-#define LP_ANA_BOD_MODE0_INT_RAW_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_RAW_S  31
-
-/** LP_ANA_INT_ST_REG register
- *  need_des
- */
-#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
-/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INT_ST    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_ST_M  (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
-#define LP_ANA_BOD_MODE0_INT_ST_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_ST_S  31
-
-/** LP_ANA_INT_ENA_REG register
- *  need_des
- */
-#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
-/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INT_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_ENA_M  (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
-#define LP_ANA_BOD_MODE0_INT_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_ENA_S  31
-
-/** LP_ANA_INT_CLR_REG register
- *  need_des
- */
-#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
-/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_INT_CLR    (BIT(31))
-#define LP_ANA_BOD_MODE0_INT_CLR_M  (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
-#define LP_ANA_BOD_MODE0_INT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_INT_CLR_S  31
-
-/** LP_ANA_LP_INT_RAW_REG register
- *  need_des
- */
-#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
-/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_LP_INT_RAW    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_M  (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_RAW_S  31
-
-/** LP_ANA_LP_INT_ST_REG register
- *  need_des
- */
-#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
-/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_LP_INT_ST    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_ST_M  (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
-#define LP_ANA_BOD_MODE0_LP_INT_ST_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_ST_S  31
-
-/** LP_ANA_LP_INT_ENA_REG register
- *  need_des
- */
-#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
-/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_LP_INT_ENA    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_M  (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_ENA_S  31
-
-/** LP_ANA_LP_INT_CLR_REG register
- *  need_des
- */
-#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
-/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_BOD_MODE0_LP_INT_CLR    (BIT(31))
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_M  (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_V  0x00000001U
-#define LP_ANA_BOD_MODE0_LP_INT_CLR_S  31
-
-/** LP_ANA_DATE_REG register
- *  need_des
- */
-#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
-/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 37752896;
- *  need_des
- */
-#define LP_ANA_LP_ANA_DATE    0x7FFFFFFFU
-#define LP_ANA_LP_ANA_DATE_M  (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
-#define LP_ANA_LP_ANA_DATE_V  0x7FFFFFFFU
-#define LP_ANA_LP_ANA_DATE_S  0
-/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_ANA_CLK_EN    (BIT(31))
-#define LP_ANA_CLK_EN_M  (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
-#define LP_ANA_CLK_EN_V  0x00000001U
-#define LP_ANA_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/lp_clkrst_reg.h b/components/soc/esp32c61/include/soc/lp_clkrst_reg.h
deleted file mode 100644
index 55d2fb2315f..00000000000
--- a/components/soc/esp32c61/include/soc/lp_clkrst_reg.h
+++ /dev/null
@@ -1,438 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_CLKRST_LP_CLK_CONF_REG register
- *  Configures the root clk of LP system
- */
-#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
-/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
- *  Configures the source of LP_SLOW_CLK.
- *  0: RC_SLOW_CLK
- *  1: XTAL32K_CLK
- *  2: RC32K_CLK
- *  3:OSC_SLOW_CLK
- */
-#define LP_CLKRST_SLOW_CLK_SEL    0x00000003U
-#define LP_CLKRST_SLOW_CLK_SEL_M  (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
-#define LP_CLKRST_SLOW_CLK_SEL_V  0x00000003U
-#define LP_CLKRST_SLOW_CLK_SEL_S  0
-/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
- *  configures the source of LP_FAST_CLK.
- *  0: RC_FAST_CLK
- *  1: XTAL_D2_CLK
- *  2: XTAL_CLK
- */
-#define LP_CLKRST_FAST_CLK_SEL    0x00000003U
-#define LP_CLKRST_FAST_CLK_SEL_M  (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
-#define LP_CLKRST_FAST_CLK_SEL_V  0x00000003U
-#define LP_CLKRST_FAST_CLK_SEL_S  2
-/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
- *  reserved
- */
-#define LP_CLKRST_LP_PERI_DIV_NUM    0x000000FFU
-#define LP_CLKRST_LP_PERI_DIV_NUM_M  (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
-#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x000000FFU
-#define LP_CLKRST_LP_PERI_DIV_NUM_S  4
-
-/** LP_CLKRST_LP_CLK_PO_EN_REG register
- *  Configures the clk gate to pad
- */
-#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
-/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
- *  Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_AON_SLOW_OEN    (BIT(0))
-#define LP_CLKRST_AON_SLOW_OEN_M  (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
-#define LP_CLKRST_AON_SLOW_OEN_V  0x00000001U
-#define LP_CLKRST_AON_SLOW_OEN_S  0
-/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
- *  Configures the clock gate to pad of the LP_DYN_FAST_CLK.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_AON_FAST_OEN    (BIT(1))
-#define LP_CLKRST_AON_FAST_OEN_M  (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
-#define LP_CLKRST_AON_FAST_OEN_V  0x00000001U
-#define LP_CLKRST_AON_FAST_OEN_S  1
-/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
- *  Configures the clock gate to pad of the OSC_SLOW_CLK.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_SOSC_OEN    (BIT(2))
-#define LP_CLKRST_SOSC_OEN_M  (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
-#define LP_CLKRST_SOSC_OEN_V  0x00000001U
-#define LP_CLKRST_SOSC_OEN_S  2
-/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
- *  Configures the clock gate to pad of the RC_FAST_CLK.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_FOSC_OEN    (BIT(3))
-#define LP_CLKRST_FOSC_OEN_M  (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
-#define LP_CLKRST_FOSC_OEN_V  0x00000001U
-#define LP_CLKRST_FOSC_OEN_S  3
-/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
- *  Configures the clock gate to pad of the RC32K_CLK.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_OSC32K_OEN    (BIT(4))
-#define LP_CLKRST_OSC32K_OEN_M  (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
-#define LP_CLKRST_OSC32K_OEN_V  0x00000001U
-#define LP_CLKRST_OSC32K_OEN_S  4
-/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
- *  Configures the clock gate to pad of the XTAL32K_CLK.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_XTAL32K_OEN    (BIT(5))
-#define LP_CLKRST_XTAL32K_OEN_M  (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
-#define LP_CLKRST_XTAL32K_OEN_V  0x00000001U
-#define LP_CLKRST_XTAL32K_OEN_S  5
-/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
- *  Configures the clock gate to pad of the EFUSE_CTRL clock.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_CORE_EFUSE_OEN    (BIT(6))
-#define LP_CLKRST_CORE_EFUSE_OEN_M  (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
-#define LP_CLKRST_CORE_EFUSE_OEN_V  0x00000001U
-#define LP_CLKRST_CORE_EFUSE_OEN_S  6
-/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
- *  Configures the clock gate to pad of the LP_SLOW_CLK.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_SLOW_OEN    (BIT(7))
-#define LP_CLKRST_SLOW_OEN_M  (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
-#define LP_CLKRST_SLOW_OEN_V  0x00000001U
-#define LP_CLKRST_SLOW_OEN_S  7
-/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
- *  Configures the clock gate to pad of the LP_FAST_CLK.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_FAST_OEN    (BIT(8))
-#define LP_CLKRST_FAST_OEN_M  (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
-#define LP_CLKRST_FAST_OEN_V  0x00000001U
-#define LP_CLKRST_FAST_OEN_S  8
-/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
- *  Configures the clock gate to pad of the RNG clk.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_RNG_OEN    (BIT(9))
-#define LP_CLKRST_RNG_OEN_M  (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
-#define LP_CLKRST_RNG_OEN_V  0x00000001U
-#define LP_CLKRST_RNG_OEN_S  9
-/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
- *  Configures the clock gate to pad of the LP bus clk.
- *  0: Disable the clk pass clock gate
- *  1: Enable the clk pass clock gate
- */
-#define LP_CLKRST_LPBUS_OEN    (BIT(10))
-#define LP_CLKRST_LPBUS_OEN_M  (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
-#define LP_CLKRST_LPBUS_OEN_V  0x00000001U
-#define LP_CLKRST_LPBUS_OEN_S  10
-
-/** LP_CLKRST_LP_CLK_EN_REG register
- *  Configure LP root clk source gate
- */
-#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
-/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
- *  Configures the clock gate to LP_FAST_CLK
- *  0: Invalid. The clock gate controlled by hardware fsm
- *  1: Force the clk pass clock gate
- */
-#define LP_CLKRST_FAST_ORI_GATE    (BIT(31))
-#define LP_CLKRST_FAST_ORI_GATE_M  (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
-#define LP_CLKRST_FAST_ORI_GATE_V  0x00000001U
-#define LP_CLKRST_FAST_ORI_GATE_S  31
-
-/** LP_CLKRST_LP_RST_EN_REG register
- *  Configures the peri of LP system software reset
- */
-#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
-/** LP_CLKRST_POR_ST_WAIT_FORCE_EN : R/W; bitpos: [27]; default: 0;
- *  reserved
- */
-#define LP_CLKRST_POR_ST_WAIT_FORCE_EN    (BIT(27))
-#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_M  (LP_CLKRST_POR_ST_WAIT_FORCE_EN_V << LP_CLKRST_POR_ST_WAIT_FORCE_EN_S)
-#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_V  0x00000001U
-#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_S  27
-/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to reset  EFUSE_CTRL always-on part
- *  0: Invalid.No effect
- *  1: Reset
- */
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN    (BIT(28))
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M  (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V  0x00000001U
-#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S  28
-/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
- *  Configures whether or not to reset  LP_TIMER
- *  0: Invalid.No effect
- *  1: Reset
- */
-#define LP_CLKRST_LP_TIMER_RESET_EN    (BIT(29))
-#define LP_CLKRST_LP_TIMER_RESET_EN_M  (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
-#define LP_CLKRST_LP_TIMER_RESET_EN_V  0x00000001U
-#define LP_CLKRST_LP_TIMER_RESET_EN_S  29
-/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
- *  Configures whether or not to reset LP_WDT and super watch dog
- *  0: Invalid.No effect
- *  1: Reset
- */
-#define LP_CLKRST_WDT_RESET_EN    (BIT(30))
-#define LP_CLKRST_WDT_RESET_EN_M  (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
-#define LP_CLKRST_WDT_RESET_EN_V  0x00000001U
-#define LP_CLKRST_WDT_RESET_EN_S  30
-/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
- *  Configures whether or not to reset analog peri, include brownout controller
- *  0: Invalid.No effect
- *  1: Reset
- */
-#define LP_CLKRST_ANA_PERI_RESET_EN    (BIT(31))
-#define LP_CLKRST_ANA_PERI_RESET_EN_M  (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
-#define LP_CLKRST_ANA_PERI_RESET_EN_V  0x00000001U
-#define LP_CLKRST_ANA_PERI_RESET_EN_S  31
-
-/** LP_CLKRST_RESET_CAUSE_REG register
- *  Represents the reset casue
- */
-#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
-/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
- *  Represents the reset cause
- */
-#define LP_CLKRST_RESET_CAUSE    0x0000001FU
-#define LP_CLKRST_RESET_CAUSE_M  (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
-#define LP_CLKRST_RESET_CAUSE_V  0x0000001FU
-#define LP_CLKRST_RESET_CAUSE_S  0
-/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
- *  Represents the reset flag
- */
-#define LP_CLKRST_CORE0_RESET_FLAG    (BIT(5))
-#define LP_CLKRST_CORE0_RESET_FLAG_M  (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_S  5
-/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
- *  0: no operation
- */
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR    (BIT(29))
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S  29
-/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
- *  configure set reset flag
- */
-#define LP_CLKRST_CORE0_RESET_FLAG_SET    (BIT(30))
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_M  (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_SET_S  30
-/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
- *  configure clear reset flag
- *  0: no operation
- *  1: clear flag to 0
- */
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR    (BIT(31))
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M  (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V  0x00000001U
-#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S  31
-
-/** LP_CLKRST_CPU_RESET_REG register
- *  Configures CPU reset
- */
-#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
-/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
- *  configure the hpcore0 luckup reset enable
- *  0: disable
- *  1:enable
- */
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(21))
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S  21
-/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
- *  configures the reset length of LP_WDT reset CPU
- *  Measurement unit: LP_DYN_FAST_CLK
- */
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH    0x00000007U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M  (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V  0x00000007U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S  22
-/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
- *  Configures whether or not LP_WDT can reset CPU
- *  0: LP_WDT could not reset CPU when LP_WDT timeout
- *  1: LP_WDT could reset CPU when LP_WDT timeout
- */
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN    (BIT(25))
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M  (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V  0x00000001U
-#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S  25
-/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
- *  configure the time between CPU stall and reset
- *  Measurement unit: LP_DYN_FAST_CLK
- */
-#define LP_CLKRST_CPU_STALL_WAIT    0x0000001FU
-#define LP_CLKRST_CPU_STALL_WAIT_M  (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
-#define LP_CLKRST_CPU_STALL_WAIT_V  0x0000001FU
-#define LP_CLKRST_CPU_STALL_WAIT_S  26
-/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
- *  Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
- *  0: CPU will not entry stall state before LP_WDT and software reset CPU
- *  1: CPU will entry stall state before LP_WDT and software reset CPU
- */
-#define LP_CLKRST_CPU_STALL_EN    (BIT(31))
-#define LP_CLKRST_CPU_STALL_EN_M  (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
-#define LP_CLKRST_CPU_STALL_EN_V  0x00000001U
-#define LP_CLKRST_CPU_STALL_EN_S  31
-
-/** LP_CLKRST_FOSC_CNTL_REG register
- *  Configures the RC_FAST_CLK frequency
- */
-#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
-/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
- *  Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
- *  field
- */
-#define LP_CLKRST_FOSC_DFREQ    0x000003FFU
-#define LP_CLKRST_FOSC_DFREQ_M  (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
-#define LP_CLKRST_FOSC_DFREQ_V  0x000003FFU
-#define LP_CLKRST_FOSC_DFREQ_S  22
-
-/** LP_CLKRST_RC32K_CNTL_REG register
- *  Configures the RC32K_CLK frequency
- */
-#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
-/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
- *  Configures the RC32K_CLK frequency, the clock frequency will increase with this
- *  field
- */
-#define LP_CLKRST_RC32K_DFREQ    0x000003FFU
-#define LP_CLKRST_RC32K_DFREQ_M  (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
-#define LP_CLKRST_RC32K_DFREQ_V  0x000003FFU
-#define LP_CLKRST_RC32K_DFREQ_S  22
-
-/** LP_CLKRST_CLK_TO_HP_REG register
- *  Configures the clk gate of LP clk to HP system
- */
-#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
-/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
- *  Configures the clk gate of XTAL32K_CLK to HP system
- *  0: The clk could not pass to HP system
- *  1: The clk could pass to HP system
- */
-#define LP_CLKRST_ICG_HP_XTAL32K    (BIT(28))
-#define LP_CLKRST_ICG_HP_XTAL32K_M  (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
-#define LP_CLKRST_ICG_HP_XTAL32K_V  0x00000001U
-#define LP_CLKRST_ICG_HP_XTAL32K_S  28
-/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
- *  Configures the clk gate of RC_SLOW_CLK to HP system
- *  0: The clk could not pass to HP system
- *  1: The clk could pass to HP system
- */
-#define LP_CLKRST_ICG_HP_SOSC    (BIT(29))
-#define LP_CLKRST_ICG_HP_SOSC_M  (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
-#define LP_CLKRST_ICG_HP_SOSC_V  0x00000001U
-#define LP_CLKRST_ICG_HP_SOSC_S  29
-/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
- *  Configures the clk gate of RC32K_CLK to HP system
- *  0: The clk could not pass to HP system
- *  1: The clk could pass to HP system
- */
-#define LP_CLKRST_ICG_HP_OSC32K    (BIT(30))
-#define LP_CLKRST_ICG_HP_OSC32K_M  (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
-#define LP_CLKRST_ICG_HP_OSC32K_V  0x00000001U
-#define LP_CLKRST_ICG_HP_OSC32K_S  30
-/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
- *  Configures the clk gate of RC_FAST_CLK to HP system
- *  0: The clk could not pass to HP system
- *  1: The clk could pass to HP system
- */
-#define LP_CLKRST_ICG_HP_FOSC    (BIT(31))
-#define LP_CLKRST_ICG_HP_FOSC_M  (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
-#define LP_CLKRST_ICG_HP_FOSC_V  0x00000001U
-#define LP_CLKRST_ICG_HP_FOSC_S  31
-
-/** LP_CLKRST_LPMEM_FORCE_REG register
- *  Configures the LP_MEM clk gate force parameter
- */
-#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
-/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  Configures whether ot not force open the clock gate of LP MEM
- *  0: Invalid. The clock gate controlled by hardware FSM
- *  1: Force open clock gate of LP MEM
- */
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M  (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S  31
-
-/** LP_CLKRST_XTAL32K_REG register
- *  Configures the XTAL32K parameter
- */
-#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
-/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
- *  Configures DRES
- */
-#define LP_CLKRST_DRES_XTAL32K    0x00000007U
-#define LP_CLKRST_DRES_XTAL32K_M  (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
-#define LP_CLKRST_DRES_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DRES_XTAL32K_S  22
-/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
- *  Configures DGM
- */
-#define LP_CLKRST_DGM_XTAL32K    0x00000007U
-#define LP_CLKRST_DGM_XTAL32K_M  (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
-#define LP_CLKRST_DGM_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DGM_XTAL32K_S  25
-/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
- *  Configures DBUF
- */
-#define LP_CLKRST_DBUF_XTAL32K    (BIT(28))
-#define LP_CLKRST_DBUF_XTAL32K_M  (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
-#define LP_CLKRST_DBUF_XTAL32K_V  0x00000001U
-#define LP_CLKRST_DBUF_XTAL32K_S  28
-/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
- *  Configures DAC
- */
-#define LP_CLKRST_DAC_XTAL32K    0x00000007U
-#define LP_CLKRST_DAC_XTAL32K_M  (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
-#define LP_CLKRST_DAC_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DAC_XTAL32K_S  29
-
-/** LP_CLKRST_DATE_REG register
- *  Version control register
- */
-#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
-/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36766288;
- *  Version control register
- */
-#define LP_CLKRST_CLKRST_DATE    0x7FFFFFFFU
-#define LP_CLKRST_CLKRST_DATE_M  (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
-#define LP_CLKRST_CLKRST_DATE_V  0x7FFFFFFFU
-#define LP_CLKRST_CLKRST_DATE_S  0
-/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  configure register clk bypass clk gate
- */
-#define LP_CLKRST_CLK_EN    (BIT(31))
-#define LP_CLKRST_CLK_EN_M  (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
-#define LP_CLKRST_CLK_EN_V  0x00000001U
-#define LP_CLKRST_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/lp_clkrst_struct.h b/components/soc/esp32c61/include/soc/lp_clkrst_struct.h
deleted file mode 100644
index 685b5245872..00000000000
--- a/components/soc/esp32c61/include/soc/lp_clkrst_struct.h
+++ /dev/null
@@ -1,392 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of lp_clk_conf register
- *  Configures the root clk of LP system
- */
-typedef union {
-    struct {
-        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
-         *  Configures the source of LP_SLOW_CLK.
-         *  0: RC_SLOW_CLK
-         *  1: XTAL32K_CLK
-         *  2: RC32K_CLK
-         *  3:OSC_SLOW_CLK
-         */
-        uint32_t slow_clk_sel:2;
-        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
-         *  configures the source of LP_FAST_CLK.
-         *  0: RC_FAST_CLK
-         *  1: XTAL_D2_CLK
-         *  2: XTAL_CLK
-         */
-        uint32_t fast_clk_sel:2;
-        /** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0;
-         *  reserved
-         */
-        uint32_t lp_peri_div_num:8;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_conf_reg_t;
-
-/** Type of lp_clk_po_en register
- *  Configures the clk gate to pad
- */
-typedef union {
-    struct {
-        /** aon_slow_oen : R/W; bitpos: [0]; default: 1;
-         *  Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t aon_slow_oen:1;
-        /** aon_fast_oen : R/W; bitpos: [1]; default: 1;
-         *  Configures the clock gate to pad of the LP_DYN_FAST_CLK.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t aon_fast_oen:1;
-        /** sosc_oen : R/W; bitpos: [2]; default: 1;
-         *  Configures the clock gate to pad of the OSC_SLOW_CLK.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t sosc_oen:1;
-        /** fosc_oen : R/W; bitpos: [3]; default: 1;
-         *  Configures the clock gate to pad of the RC_FAST_CLK.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t fosc_oen:1;
-        /** osc32k_oen : R/W; bitpos: [4]; default: 1;
-         *  Configures the clock gate to pad of the RC32K_CLK.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t osc32k_oen:1;
-        /** xtal32k_oen : R/W; bitpos: [5]; default: 1;
-         *  Configures the clock gate to pad of the XTAL32K_CLK.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t xtal32k_oen:1;
-        /** core_efuse_oen : R/W; bitpos: [6]; default: 1;
-         *  Configures the clock gate to pad of the EFUSE_CTRL clock.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t core_efuse_oen:1;
-        /** slow_oen : R/W; bitpos: [7]; default: 1;
-         *  Configures the clock gate to pad of the LP_SLOW_CLK.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t slow_oen:1;
-        /** fast_oen : R/W; bitpos: [8]; default: 1;
-         *  Configures the clock gate to pad of the LP_FAST_CLK.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t fast_oen:1;
-        /** rng_oen : R/W; bitpos: [9]; default: 1;
-         *  Configures the clock gate to pad of the RNG clk.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t rng_oen:1;
-        /** lpbus_oen : R/W; bitpos: [10]; default: 1;
-         *  Configures the clock gate to pad of the LP bus clk.
-         *  0: Disable the clk pass clock gate
-         *  1: Enable the clk pass clock gate
-         */
-        uint32_t lpbus_oen:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_po_en_reg_t;
-
-/** Type of lp_clk_en register
- *  Configure LP root clk source gate
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** fast_ori_gate : R/W; bitpos: [31]; default: 0;
-         *  Configures the clock gate to LP_FAST_CLK
-         *  0: Invalid. The clock gate controlled by hardware fsm
-         *  1: Force the clk pass clock gate
-         */
-        uint32_t fast_ori_gate:1;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_en_reg_t;
-
-/** Type of lp_rst_en register
- *  Configures the peri of LP system software reset
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:27;
-        /** por_st_wait_force_en : R/W; bitpos: [27]; default: 0;
-         *  reserved
-         */
-        uint32_t por_st_wait_force_en:1;
-        /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to reset  EFUSE_CTRL always-on part
-         *  0: Invalid.No effect
-         *  1: Reset
-         */
-        uint32_t aon_efuse_core_reset_en:1;
-        /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
-         *  Configures whether or not to reset  LP_TIMER
-         *  0: Invalid.No effect
-         *  1: Reset
-         */
-        uint32_t lp_timer_reset_en:1;
-        /** wdt_reset_en : R/W; bitpos: [30]; default: 0;
-         *  Configures whether or not to reset LP_WDT and super watch dog
-         *  0: Invalid.No effect
-         *  1: Reset
-         */
-        uint32_t wdt_reset_en:1;
-        /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
-         *  Configures whether or not to reset analog peri, include brownout controller
-         *  0: Invalid.No effect
-         *  1: Reset
-         */
-        uint32_t ana_peri_reset_en:1;
-    };
-    uint32_t val;
-} lp_clkrst_lp_rst_en_reg_t;
-
-/** Type of reset_cause register
- *  Represents the reset casue
- */
-typedef union {
-    struct {
-        /** reset_cause : RO; bitpos: [4:0]; default: 0;
-         *  Represents the reset cause
-         */
-        uint32_t reset_cause:5;
-        /** core0_reset_flag : RO; bitpos: [5]; default: 1;
-         *  Represents the reset flag
-         */
-        uint32_t core0_reset_flag:1;
-        uint32_t reserved_6:23;
-        /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
-         *  0: no operation
-         */
-        uint32_t core0_reset_cause_clr:1;
-        /** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
-         *  configure set reset flag
-         */
-        uint32_t core0_reset_flag_set:1;
-        /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
-         *  configure clear reset flag
-         *  0: no operation
-         *  1: clear flag to 0
-         */
-        uint32_t core0_reset_flag_clr:1;
-    };
-    uint32_t val;
-} lp_clkrst_reset_cause_reg_t;
-
-/** Type of cpu_reset register
- *  Configures CPU reset
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1;
-         *  configure the hpcore0 luckup reset enable
-         *  0: disable
-         *  1:enable
-         */
-        uint32_t hpcore0_lockup_reset_en:1;
-        /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
-         *  configures the reset length of LP_WDT reset CPU
-         *  Measurement unit: LP_DYN_FAST_CLK
-         */
-        uint32_t rtc_wdt_cpu_reset_length:3;
-        /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
-         *  Configures whether or not LP_WDT can reset CPU
-         *  0: LP_WDT could not reset CPU when LP_WDT timeout
-         *  1: LP_WDT could reset CPU when LP_WDT timeout
-         */
-        uint32_t rtc_wdt_cpu_reset_en:1;
-        /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
-         *  configure the time between CPU stall and reset
-         *  Measurement unit: LP_DYN_FAST_CLK
-         */
-        uint32_t cpu_stall_wait:5;
-        /** cpu_stall_en : R/W; bitpos: [31]; default: 0;
-         *  Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
-         *  0: CPU will not entry stall state before LP_WDT and software reset CPU
-         *  1: CPU will entry stall state before LP_WDT and software reset CPU
-         */
-        uint32_t cpu_stall_en:1;
-    };
-    uint32_t val;
-} lp_clkrst_cpu_reset_reg_t;
-
-/** Type of fosc_cntl register
- *  Configures the RC_FAST_CLK frequency
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
-         *  Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
-         *  field
-         */
-        uint32_t fosc_dfreq:10;
-    };
-    uint32_t val;
-} lp_clkrst_fosc_cntl_reg_t;
-
-/** Type of rc32k_cntl register
- *  Configures the RC32K_CLK frequency
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
-         *  Configures the RC32K_CLK frequency, the clock frequency will increase with this
-         *  field
-         */
-        uint32_t rc32k_dfreq:10;
-    };
-    uint32_t val;
-} lp_clkrst_rc32k_cntl_reg_t;
-
-/** Type of clk_to_hp register
- *  Configures the clk gate of LP clk to HP system
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
-         *  Configures the clk gate of XTAL32K_CLK to HP system
-         *  0: The clk could not pass to HP system
-         *  1: The clk could pass to HP system
-         */
-        uint32_t icg_hp_xtal32k:1;
-        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
-         *  Configures the clk gate of RC_SLOW_CLK to HP system
-         *  0: The clk could not pass to HP system
-         *  1: The clk could pass to HP system
-         */
-        uint32_t icg_hp_sosc:1;
-        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
-         *  Configures the clk gate of RC32K_CLK to HP system
-         *  0: The clk could not pass to HP system
-         *  1: The clk could pass to HP system
-         */
-        uint32_t icg_hp_osc32k:1;
-        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
-         *  Configures the clk gate of RC_FAST_CLK to HP system
-         *  0: The clk could not pass to HP system
-         *  1: The clk could pass to HP system
-         */
-        uint32_t icg_hp_fosc:1;
-    };
-    uint32_t val;
-} lp_clkrst_clk_to_hp_reg_t;
-
-/** Type of lpmem_force register
- *  Configures the LP_MEM clk gate force parameter
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
-         *  Configures whether ot not force open the clock gate of LP MEM
-         *  0: Invalid. The clock gate controlled by hardware FSM
-         *  1: Force open clock gate of LP MEM
-         */
-        uint32_t lpmem_clk_force_on:1;
-    };
-    uint32_t val;
-} lp_clkrst_lpmem_force_reg_t;
-
-/** Type of xtal32k register
- *  Configures the XTAL32K parameter
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
-         *  Configures DRES
-         */
-        uint32_t dres_xtal32k:3;
-        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
-         *  Configures DGM
-         */
-        uint32_t dgm_xtal32k:3;
-        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
-         *  Configures DBUF
-         */
-        uint32_t dbuf_xtal32k:1;
-        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
-         *  Configures DAC
-         */
-        uint32_t dac_xtal32k:3;
-    };
-    uint32_t val;
-} lp_clkrst_xtal32k_reg_t;
-
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** clkrst_date : R/W; bitpos: [30:0]; default: 36766288;
-         *  Version control register
-         */
-        uint32_t clkrst_date:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  configure register clk bypass clk gate
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_clkrst_date_reg_t;
-
-
-typedef struct {
-    volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
-    volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
-    volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
-    volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
-    volatile lp_clkrst_reset_cause_reg_t reset_cause;
-    volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
-    volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
-    volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
-    volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
-    volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
-    uint32_t reserved_028;
-    volatile lp_clkrst_xtal32k_reg_t xtal32k;
-    uint32_t reserved_030[243];
-    volatile lp_clkrst_date_reg_t date;
-} lp_clkrst_dev_t;
-
-extern lp_clkrst_dev_t LP_CLKRST;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/pmu_icg_mapping.h b/components/soc/esp32c61/include/soc/pmu_icg_mapping.h
index 4ca8294bd15..a71ee0a8da8 100644
--- a/components/soc/esp32c61/include/soc/pmu_icg_mapping.h
+++ b/components/soc/esp32c61/include/soc/pmu_icg_mapping.h
@@ -5,54 +5,49 @@
  */
 
 #pragma once
-
+#define PMU_ICG_APB_ENA_SEC                     0
 #define PMU_ICG_APB_ENA_GDMA                    1
-#define PMU_ICG_APB_ENA_I2C                     13
-#define PMU_ICG_APB_ENA_I2S                     4
+#define PMU_ICG_APB_ENA_SPI2                    2
 #define PMU_ICG_APB_ENA_INTMTX                  3
-#define PMU_ICG_APB_ENA_IOMUX                   26
-#define PMU_ICG_APB_ENA_LEDC                    14
-#define PMU_ICG_APB_ENA_MEM_MONITOR             25
+#define PMU_ICG_APB_ENA_I2S                     4
 #define PMU_ICG_APB_ENA_MSPI                    5
-#define PMU_ICG_APB_ENA_PARL                    23
-#define PMU_ICG_APB_ENA_PVT_MONITOR             27
-#define PMU_ICG_APB_ENA_REGDMA                  24
+#define PMU_ICG_APB_ENA_UART0                   6
+#define PMU_ICG_APB_ENA_UART1                   7
 #define PMU_ICG_APB_ENA_SARADC                  9
-#define PMU_ICG_APB_ENA_SEC                     0
-#define PMU_ICG_APB_ENA_SOC_ETM                 22
-#define PMU_ICG_APB_ENA_SPI2                    2
-#define PMU_ICG_APB_ENA_SYSTIMER                16
 #define PMU_ICG_APB_ENA_TG0                     11
 #define PMU_ICG_APB_ENA_TG1                     12
-#define PMU_ICG_APB_ENA_UART0                   6
-#define PMU_ICG_APB_ENA_UART1                   7
-#define PMU_ICG_APB_ENA_UHCI                    8
+#define PMU_ICG_APB_ENA_I2C                     13
+#define PMU_ICG_APB_ENA_LEDC                    14
+#define PMU_ICG_APB_ENA_SYSTIMER                16
 #define PMU_ICG_APB_ENA_USB_DEVICE              17
-#define PMU_ICG_FUNC_ENA_I2C                    29
-#define PMU_ICG_FUNC_ENA_I2S_RX                 2
-#define PMU_ICG_FUNC_ENA_I2S_TX                 7
-#define PMU_ICG_FUNC_ENA_IOMUX                  28
-#define PMU_ICG_FUNC_ENA_LEDC                   27
-#define PMU_ICG_FUNC_ENA_MEM_MONITOR            10
-#define PMU_ICG_FUNC_ENA_MSPI                   26
-#define PMU_ICG_FUNC_ENA_PARL_RX                25
-#define PMU_ICG_FUNC_ENA_PARL_TX                24
-#define PMU_ICG_FUNC_ENA_PVT_MONITOR            23
-#define PMU_ICG_FUNC_ENA_SARADC                 20
-#define PMU_ICG_FUNC_ENA_SEC                    19
+#define PMU_ICG_APB_ENA_SOC_ETM                 22
+#define PMU_ICG_APB_ENA_REGDMA                  24
+#define PMU_ICG_APB_ENA_MEM_MONITOR             25
+#define PMU_ICG_APB_ENA_IOMUX                   26
+#define PMU_ICG_APB_ENA_PVT_MONITOR             27
+#define PMU_ICG_APB_ENA_UART2                   29
+#define PMU_ICG_FUNC_ENA_GDMA                   0
 #define PMU_ICG_FUNC_ENA_SPI2                   1
-#define PMU_ICG_FUNC_ENA_SYSTIMER               18
-#define PMU_ICG_FUNC_ENA_TG0                    14
-#define PMU_ICG_FUNC_ENA_TG1                    13
-#define PMU_ICG_FUNC_ENA_TSENS                  12
+#define PMU_ICG_FUNC_ENA_I2S_RX                 2
 #define PMU_ICG_FUNC_ENA_UART0                  3
 #define PMU_ICG_FUNC_ENA_UART1                  4
 #define PMU_ICG_FUNC_ENA_USB_DEVICE             6
-#define PMU_ICG_FUNC_ENA_GDMA                   0
-#define PMU_ICG_FUNC_ENA_SOC_ETM                16
+#define PMU_ICG_FUNC_ENA_I2S_TX                 7
 #define PMU_ICG_FUNC_ENA_REGDMA                 8
-#define PMU_ICG_FUNC_ENA_RETENTION              9
-#define PMU_ICG_FUNC_ENA_SDIO_SLAVE             11
-#define PMU_ICG_FUNC_ENA_UHCI                   5
-#define PMU_ICG_FUNC_ENA_HPCORE                 17
+#define PMU_ICG_FUNC_ENA_MEM_MONITOR            10
+#define PMU_ICG_FUNC_ENA_TSENS                  12
+#define PMU_ICG_FUNC_ENA_TG1                    13
+#define PMU_ICG_FUNC_ENA_TG0                    14
 #define PMU_ICG_FUNC_ENA_HPBUS                  15
+#define PMU_ICG_FUNC_ENA_HPMEM                  15
+#define PMU_ICG_FUNC_ENA_SOC_ETM                16
+#define PMU_ICG_FUNC_ENA_HPCORE                 17
+#define PMU_ICG_FUNC_ENA_SYSTIMER               18
+#define PMU_ICG_FUNC_ENA_SEC                    19
+#define PMU_ICG_FUNC_ENA_SARADC                 20
+#define PMU_ICG_FUNC_ENA_UART2                  22
+#define PMU_ICG_FUNC_ENA_PVT_MONITOR            23
+#define PMU_ICG_FUNC_ENA_MSPI                   26
+#define PMU_ICG_FUNC_ENA_LEDC                   27
+#define PMU_ICG_FUNC_ENA_IOMUX                  28
+#define PMU_ICG_FUNC_ENA_I2C                    29
diff --git a/components/soc/esp32c61/include/soc/pmu_struct.h b/components/soc/esp32c61/include/soc/pmu_struct.h
deleted file mode 100644
index 3e2f9fb16f6..00000000000
--- a/components/soc/esp32c61/include/soc/pmu_struct.h
+++ /dev/null
@@ -1,769 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include <stddef.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "soc.h"
-#include "soc/pmu_reg.h"
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 21;
-        uint32_t vdd_spi_pd_en: 1;
-        uint32_t mem_dslp     : 1;
-        uint32_t mem_pd_en    : 4;
-        uint32_t wifi_pd_en   : 1;
-        uint32_t reserved1    : 1;
-        uint32_t cpu_pd_en    : 1;
-        uint32_t aon_pd_en    : 1;
-        uint32_t top_pd_en    : 1;
-    };
-    uint32_t val;
-} pmu_hp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 30;
-        uint32_t code     : 2;
-    };
-    uint32_t val;
-} pmu_hp_icg_modem_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 24;
-        uint32_t uart_wakeup_en : 1;
-        uint32_t lp_pad_hold_all: 1;
-        uint32_t hp_pad_hold_all: 1;
-        uint32_t dig_pad_slp_sel: 1;
-        uint32_t dig_pause_wdt  : 1;
-        uint32_t dig_cpu_stall  : 1;
-        uint32_t reserved1      : 2;
-    };
-    uint32_t val;
-} pmu_hp_sys_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 26;
-        uint32_t i2c_iso_en   : 1;
-        uint32_t i2c_retention: 1;
-        uint32_t xpd_bb_i2c   : 1;
-        uint32_t xpd_bbpll_i2c: 1;
-        uint32_t xpd_bbpll    : 1;
-        uint32_t reserved1    : 1;
-    };
-    uint32_t val;
-} pmu_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_hp_bias_reg_t;
-
-typedef union {
-    struct {    /* HP: Active State */
-        uint32_t reserved0                            : 4;
-        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
-        uint32_t hp_modem2active_backup_modem_clk_code: 2;
-        uint32_t reserved1                            : 2;
-        uint32_t hp_active_retention_mode             : 1;
-        uint32_t hp_sleep2active_retention_en         : 1;
-        uint32_t hp_modem2active_retention_en         : 1;
-        uint32_t reserved2                            : 1;
-        uint32_t hp_sleep2active_backup_clk_sel       : 2;
-        uint32_t hp_modem2active_backup_clk_sel       : 2;
-        uint32_t reserved3                            : 2;
-        uint32_t hp_sleep2active_backup_mode          : 3;
-        uint32_t hp_modem2active_backup_mode          : 3;
-        uint32_t reserved4                            : 3;
-        uint32_t hp_sleep2active_backup_en            : 1;
-        uint32_t hp_modem2active_backup_en            : 1;
-        uint32_t reserved5                            : 1;
-    };
-    struct {    /* HP: Modem State */
-        uint32_t reserved6                            : 4;
-        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
-        uint32_t reserved7                            : 4;
-        uint32_t hp_modem_retention_mode              : 1;
-        uint32_t hp_sleep2modem_retention_en          : 1;
-        uint32_t reserved8                            : 2;
-        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
-        uint32_t reserved9                            : 4;
-        uint32_t hp_sleep2modem_backup_mode           : 3;
-        uint32_t reserved10                           : 6;
-        uint32_t hp_sleep2modem_backup_en             : 1;
-        uint32_t reserved11                           : 2;
-    };
-    struct {    /* HP: Sleep State */
-        uint32_t reserved12                           : 6;
-        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
-        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
-        uint32_t hp_sleep_retention_mode              : 1;
-        uint32_t reserved13                           : 1;
-        uint32_t hp_modem2sleep_retention_en          : 1;
-        uint32_t hp_active2sleep_retention_en         : 1;
-        uint32_t reserved14                           : 2;
-        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
-        uint32_t hp_active2sleep_backup_clk_sel       : 2;
-        uint32_t reserved15                           : 3;
-        uint32_t hp_modem2sleep_backup_mode           : 3;
-        uint32_t hp_active2sleep_backup_mode          : 3;
-        uint32_t reserved16                           : 1;
-        uint32_t hp_modem2sleep_backup_en             : 1;
-        uint32_t hp_active2sleep_backup_en            : 1;
-    };
-    uint32_t val;
-} pmu_hp_backup_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0       : 26;
-        uint32_t dig_sysclk_nodiv: 1;
-        uint32_t icg_sysclk_en   : 1;
-        uint32_t sysclk_slp_sel  : 1;
-        uint32_t icg_slp_sel     : 1;
-        uint32_t dig_sysclk_sel  : 2;
-    };
-    uint32_t val;
-} pmu_hp_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t slp_mem_xpd    : 1;
-        uint32_t slp_logic_xpd  : 1;
-        uint32_t xpd            : 1;
-        uint32_t slp_mem_dbias  : 4;
-        uint32_t slp_logic_dbias: 4;
-        uint32_t dbias          : 5;
-    };
-    uint32_t val;
-} pmu_hp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 8;
-        uint32_t drv_b    : 24;
-    };
-    uint32_t val;
-} pmu_hp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_hp_xtal_reg_t;
-
-typedef struct pmu_hp_hw_regmap_t{
-    pmu_hp_dig_power_reg_t     dig_power;
-    uint32_t                   icg_func;
-    uint32_t                   icg_apb;
-    pmu_hp_icg_modem_reg_t     icg_modem;
-    pmu_hp_sys_cntl_reg_t      syscntl;
-    pmu_hp_clk_power_reg_t     clk_power;
-    pmu_hp_bias_reg_t          bias;
-    pmu_hp_backup_reg_t        backup;
-    uint32_t                   backup_clk;
-    pmu_hp_sysclk_reg_t        sysclk;
-    pmu_hp_regulator0_reg_t    regulator0;
-    pmu_hp_regulator1_reg_t    regulator1;
-    pmu_hp_xtal_reg_t          xtal;
-} pmu_hp_hw_regmap_t;
-
-/** */
-typedef union {
-    struct {
-        uint32_t reserved0: 21;
-        uint32_t slp_xpd  : 1;
-        uint32_t xpd	  : 1;
-        uint32_t slp_dbias: 4;
-        uint32_t dbias    : 5;
-    };
-    uint32_t val;
-} pmu_lp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 28;
-        uint32_t drv_b    : 4;
-    };
-    uint32_t val;
-} pmu_lp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_lp_xtal_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 30;
-        uint32_t mem_dslp  : 1;
-        uint32_t peri_pd_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0  : 28;
-        uint32_t xpd_xtal32k: 1;
-        uint32_t xpd_rc32k  : 1;
-        uint32_t xpd_fosc   : 1;
-        uint32_t pd_osc     : 1;
-    };
-    uint32_t val;
-} pmu_lp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_lp_bias_reg_t;
-
-typedef struct pmu_lp_hw_regmap_t{
-    pmu_lp_regulator0_reg_t    regulator0;
-    pmu_lp_regulator1_reg_t    regulator1;
-    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
-    pmu_lp_dig_power_reg_t     dig_power;
-    pmu_lp_clk_power_reg_t     clk_power;
-    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
-} pmu_lp_hw_regmap_t;
-
-
-typedef union {
-    struct {
-        uint32_t tie_low_global_bbpll_icg : 1;
-        uint32_t tie_low_global_xtal_icg  : 1;
-        uint32_t tie_low_i2c_retention    : 1;
-        uint32_t tie_low_xpd_bb_i2c       : 1;
-        uint32_t tie_low_xpd_bbpll_i2c    : 1;
-        uint32_t tie_low_xpd_bbpll        : 1;
-        uint32_t tie_low_xpd_xtal         : 1;
-        uint32_t reserved0                : 18;
-        uint32_t tie_high_global_bbpll_icg: 1;
-        uint32_t tie_high_global_xtal_icg : 1;
-        uint32_t tie_high_i2c_retention   : 1;
-        uint32_t tie_high_xpd_bb_i2c      : 1;
-        uint32_t tie_high_xpd_bbpll_i2c   : 1;
-        uint32_t tie_high_xpd_bbpll       : 1;
-        uint32_t tie_high_xpd_xtal        : 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 28;
-        uint32_t update_dig_icg_switch: 1;
-        uint32_t tie_low_icg_slp_sel  : 1;
-        uint32_t tie_high_icg_slp_sel : 1;
-        uint32_t update_dig_sysclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_sleep_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0             : 31;
-        uint32_t update_dig_icg_func_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_func_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 31;
-        uint32_t update_dig_icg_apb_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_apb_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 31;
-        uint32_t update_dig_icg_modem_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_modem_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 30;
-        uint32_t tie_low_lp_rootclk_sel : 1;
-        uint32_t tie_high_lp_rootclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_lp_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0               : 28;
-        uint32_t tie_high_lp_pad_hold_all: 1;
-        uint32_t tie_low_lp_pad_hold_all : 1;
-        uint32_t tie_high_hp_pad_hold_all: 1;
-        uint32_t tie_low_hp_pad_hold_all : 1;
-    };
-    uint32_t val;
-} pmu_imm_pad_hold_all_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 30;
-        uint32_t tie_high_i2c_iso_en: 1;
-        uint32_t tie_low_i2c_iso_en : 1;
-    };
-    uint32_t val;
-} pmu_imm_i2c_isolate_reg_t;
-
-typedef struct pmu_imm_hw_regmap_t{
-    pmu_imm_hp_clk_power_reg_t     clk_power;
-    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
-    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
-    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
-    pmu_imm_modem_icg_reg_t        modem_icg;
-    pmu_imm_lp_icg_reg_t           lp_icg;
-    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
-    pmu_imm_i2c_isolate_reg_t      i2c_iso;
-} pmu_imm_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 5;
-        uint32_t powerdown_timer: 9;
-        uint32_t powerup_timer  : 9;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 9;
-        uint32_t powerdown_timer: 7;
-        uint32_t powerup_timer  : 7;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_iso_wait_timer: 8;
-        uint32_t lp_rst_wait_timer: 8;
-        uint32_t hp_iso_wait_timer: 8;
-        uint32_t hp_rst_wait_timer: 8;
-    };
-    uint32_t val;
-} pmu_power_wait_timer2_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_reset   : 1;
-        uint32_t force_iso     : 1;
-        uint32_t force_pu      : 1;
-        uint32_t force_no_reset: 1;
-        uint32_t force_no_iso  : 1;
-        uint32_t force_pd      : 1;
-        uint32_t mask          : 5;     /* Invalid of lp peripherals */
-        uint32_t reserved0     : 16;    /* Invalid of lp peripherals */
-        uint32_t pd_mask       : 5;     /* Invalid of lp peripherals */
-    };
-    uint32_t val;
-} pmu_power_domain_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_mem_iso   : 4;
-        uint32_t force_hp_mem_pd    : 4;
-        uint32_t reserved0          : 16;
-        uint32_t force_hp_mem_no_iso: 4;
-        uint32_t force_hp_mem_pu    : 4;
-    };
-    uint32_t val;
-} pmu_power_memory_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t mem2_pd_mask: 5;
-        uint32_t mem1_pd_mask: 5;
-        uint32_t mem0_pd_mask: 5;
-        uint32_t reserved0   : 2;
-        uint32_t mem2_mask   : 5;
-        uint32_t mem1_mask   : 5;
-        uint32_t mem0_mask   : 5;
-    };
-    uint32_t val;
-} pmu_power_memory_mask_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_pad_no_iso_all: 1;
-        uint32_t force_hp_pad_iso_all   : 1;
-        uint32_t reserved0              : 30;
-    };
-    uint32_t val;
-} pmu_power_hp_pad_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 18;
-        uint32_t pwr_wait  : 11;
-        uint32_t pwr_sw    : 2;
-        uint32_t pwr_sel_sw: 1;
-    };
-    uint32_t val;
-} pmu_power_vdd_spi_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wait_xtal_stable: 16;
-        uint32_t wait_pll_stable : 16;
-    };
-    uint32_t val;
-} pmu_power_clk_wait_cntl_reg_t;
-
-typedef struct pmu_power_hw_regmap_t{
-    pmu_power_wait_timer0_reg_t    wait_timer0;
-    pmu_power_wait_timer1_reg_t    wait_timer1;
-    pmu_power_wait_timer2_reg_t    wait_timer2;
-    pmu_power_domain_cntl_reg_t    hp_pd[5];
-    pmu_power_domain_cntl_reg_t    lp_peri;
-    pmu_power_memory_cntl_reg_t    mem_cntl;
-    pmu_power_memory_mask_reg_t    mem_mask;
-    pmu_power_hp_pad_reg_t         hp_pad;
-    pmu_power_vdd_spi_cntl_reg_t   vdd_spi;
-    pmu_power_clk_wait_cntl_reg_t  clk_wait;
-} pmu_power_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t sleep_reject_ena: 31;
-        uint32_t slp_reject_en   : 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_min_slp_val: 8;
-        uint32_t hp_min_slp_val: 8;
-        uint32_t sleep_prt_sel : 2;
-        uint32_t reserved0     : 14;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl3_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0           : 31;
-        uint32_t slp_reject_cause_clr: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl4_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modem_wait_target : 20;
-        uint32_t reserved0         : 4;
-        uint32_t lp_ana_wait_target: 8;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl5_reg_t;
-
-typedef union {
-    struct {
-        uint32_t soc_wakeup_wait    : 20;
-        uint32_t reserved0          : 10;
-        uint32_t soc_wakeup_wait_cfg: 2;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl6_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 16;
-        uint32_t ana_wait_target: 16;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl7_reg_t;
-
-typedef struct pmu_wakeup_hw_regmap_t{
-    pmu_slp_wakeup_cntl0_reg_t     cntl0;
-    pmu_slp_wakeup_cntl1_reg_t     cntl1;
-    uint32_t                       cntl2;
-    pmu_slp_wakeup_cntl3_reg_t     cntl3;
-    pmu_slp_wakeup_cntl4_reg_t     cntl4;
-    pmu_slp_wakeup_cntl5_reg_t     cntl5;
-    pmu_slp_wakeup_cntl6_reg_t     cntl6;
-    pmu_slp_wakeup_cntl7_reg_t     cntl7;
-    uint32_t                       status0;
-    uint32_t                       status1;
-} pmu_wakeup_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t i2c_por_wait_target: 8;
-        uint32_t reserved0          : 24;
-    };
-    uint32_t val;
-} pmu_hp_clk_poweron_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modify_icg_cntl_wait: 8;
-        uint32_t switch_icg_cntl_wait: 8;
-        uint32_t reserved0           : 16;
-    };
-    uint32_t val;
-} pmu_hp_clk_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t por_done : 1;
-    };
-    uint32_t val;
-} pmu_por_status_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0     : 24;
-        uint32_t xpd_tc5g_i2c  : 1;
-        uint32_t xpd_rx5g_i2c  : 1;
-        uint32_t perif_i2c_rstb: 1;
-        uint32_t xpd_perif_i2c : 1;
-        uint32_t xpd_txrf_i2c  : 1;
-        uint32_t xpd_rfrx_pbus : 1;
-        uint32_t xpd_ckgen_i2c : 1;
-        uint32_t xpd_pll_i2c   : 1;
-    };
-    uint32_t val;
-} pmu_rf_pwc_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 31;
-        uint32_t backup_sysclk_nodiv: 1;
-    };
-    uint32_t val;
-} pmu_backup_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 27;
-        uint32_t lp_cpu_exc: 1;
-        uint32_t sdio_idle : 1;
-        uint32_t sw        : 1;
-        uint32_t reject    : 1;
-        uint32_t wakeup    : 1;
-    };
-    uint32_t val;
-} pmu_hp_intr_reg_t;
-
-typedef struct pmu_hp_ext_hw_regmap_t{
-    pmu_hp_clk_poweron_reg_t   clk_poweron;
-    pmu_hp_clk_cntl_reg_t      clk_cntl;
-    pmu_por_status_reg_t       por_status;
-    pmu_rf_pwc_reg_t           rf_pwc;
-    pmu_backup_cfg_reg_t       backup_cfg;
-    pmu_hp_intr_reg_t          int_raw;
-    pmu_hp_intr_reg_t          int_st;
-    pmu_hp_intr_reg_t          int_ena;
-    pmu_hp_intr_reg_t          int_clr;
-} pmu_hp_ext_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0                : 20;
-        uint32_t lp_cpu_wakeup            : 1;
-        uint32_t modem_switch_active_end  : 1;
-        uint32_t sleep_switch_active_end  : 1;
-        uint32_t sleep_switch_modem_end   : 1;
-        uint32_t modem_switch_sleep_end   : 1;
-        uint32_t active_swtich_sleep_end  : 1;
-        uint32_t modem_switch_active_start: 1;
-        uint32_t sleep_switch_active_start: 1;
-        uint32_t sleep_switch_modem_start : 1;
-        uint32_t modem_switch_sleep_start : 1;
-        uint32_t active_switch_sleep_start: 1;
-        uint32_t sw_trigger               : 1;
-    };
-    uint32_t val;
-} pmu_lp_intr_reg_t;
-
-typedef union {
-    struct {
-        uint32_t waiti_rdy         : 1;
-        uint32_t stall_rdy         : 1;
-        uint32_t reserved0         : 16;
-        uint32_t force_stall       : 1;
-        uint32_t slp_waiti_flag_en : 1;
-        uint32_t slp_stall_flag_en : 1;
-        uint32_t slp_stall_wait    : 8;
-        uint32_t slp_stall_en      : 1;
-        uint32_t slp_reset_en      : 1;
-        uint32_t slp_bypass_intr_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_en: 16;
-        uint32_t reserved0: 15;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr1_reg_t;
-
-typedef struct pmu_lp_ext_hw_regmap_t{
-    pmu_lp_intr_reg_t          int_raw;
-    pmu_lp_intr_reg_t          int_st;
-    pmu_lp_intr_reg_t          int_ena;
-    pmu_lp_intr_reg_t          int_clr;
-    pmu_lp_cpu_pwr0_reg_t      pwr0;
-    pmu_lp_cpu_pwr1_reg_t      pwr1;
-} pmu_lp_ext_hw_regmap_t;
-
-typedef struct pmu_dev_t{
-    volatile pmu_hp_hw_regmap_t     hp_sys[3];
-    volatile pmu_lp_hw_regmap_t     lp_sys[2];
-    volatile pmu_imm_hw_regmap_t    imm;
-    volatile pmu_power_hw_regmap_t  power;
-    volatile pmu_wakeup_hw_regmap_t wakeup;
-    volatile pmu_hp_ext_hw_regmap_t hp_ext;
-    volatile pmu_lp_ext_hw_regmap_t lp_ext;
-
-    union {
-        struct {
-            uint32_t reserved0    : 30;
-            volatile uint32_t lp_trigger_hp: 1;
-            volatile uint32_t hp_trigger_lp: 1;
-        };
-        volatile uint32_t val;
-    } hp_lp_cpu_comm;
-
-    union {
-        struct {
-            uint32_t reserved0           : 31;
-            volatile uint32_t dig_regulator_en_cal: 1;
-        };
-        volatile uint32_t val;
-    } hp_regulator_cfg;
-
-    union {
-        struct {
-            uint32_t reserved0 : 11;
-            volatile uint32_t last_st   : 7;
-            volatile uint32_t target_st : 7;
-            volatile uint32_t current_st: 7;
-        };
-        volatile uint32_t val;
-    } main_state;
-
-    union {
-        struct {
-            uint32_t reserved0: 13;
-            volatile uint32_t backup_st: 5;
-            volatile uint32_t lp_pwr_st: 5;
-            volatile uint32_t hp_pwr_st: 9;
-        };
-        volatile uint32_t val;
-    } pwr_state;
-
-    union {
-        struct {
-            volatile uint32_t stable_xpd_bbpll : 1;
-            volatile uint32_t stable_xpd_xtal  : 1;
-            volatile uint32_t reserved0        : 13;
-            volatile uint32_t sysclk_slp_sel   : 1;
-            volatile uint32_t sysclk_sel       : 2;
-            volatile uint32_t sysclk_nodiv     : 1;
-            volatile uint32_t icg_sysclk_en    : 1;
-            volatile uint32_t icg_modem_switch : 1;
-            volatile uint32_t icg_modem_code   : 2;
-            volatile uint32_t icg_slp_sel      : 1;
-            volatile uint32_t icg_global_xtal  : 1;
-            volatile uint32_t icg_global_pll   : 1;
-            volatile uint32_t ana_i2c_iso_en   : 1;
-            volatile uint32_t ana_i2c_retention: 1;
-            volatile uint32_t ana_xpd_bb_i2c   : 1;
-            volatile uint32_t ana_xpd_bbpll_i2c: 1;
-            volatile uint32_t ana_xpd_bbpll    : 1;
-            volatile uint32_t ana_xpd_xtal     : 1;
-        };
-        volatile uint32_t val;
-    } clk_state0;
-
-    volatile uint32_t clk_state1;
-    volatile uint32_t clk_state2;
-
-    union {
-        struct {
-            uint32_t reserved0             : 31;
-            volatile uint32_t stable_vdd_spi_pwr_drv: 1;
-        };
-        volatile uint32_t val;
-    } vdd_spi_status;
-
-    uint32_t reserved[0];
-
-    union {
-        struct {
-            volatile uint32_t pmu_date: 31;
-            volatile uint32_t clk_en  : 1;
-        };
-        volatile uint32_t val;
-    } date;
-} pmu_dev_t;
-
-extern pmu_dev_t PMU;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pmu_dev_t) == 0x1AC, "Invalid size of pmu_dev_t structure");
-
-_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/reg_base.h b/components/soc/esp32c61/include/soc/reg_base.h
deleted file mode 100644
index e092f8726b6..00000000000
--- a/components/soc/esp32c61/include/soc/reg_base.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#define DR_REG_UART0_BASE                       0x60000000
-#define DR_REG_UART1_BASE                       0x60001000
-#define DR_REG_MSPI0_BASE                       0x60002000
-#define DR_REG_MSPI1_BASE                       0x60003000
-#define DR_REG_I2C_BASE                         0x60004000
-#define DR_REG_UART2_BASE                       0x60006000
-#define DR_REG_LEDC_BASE                        0x60007000
-#define DR_REG_TIMG0_BASE                       0x60008000
-#define DR_REG_TIMG1_BASE                       0x60009000
-#define DR_REG_SYSTIMER_BASE                    0x6000A000
-#define DR_REG_I2S_BASE                         0x6000C000
-#define DR_REG_SARADC_BASE                      0x6000E000
-#define DR_REG_USB_SERIAL_JTAG_BASE             0x6000F000
-#define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
-#define DR_REG_SOC_ETM_BASE                     0x60013000
-#define DR_REG_PVT_MONITOR_BASE                 0x60019000
-#define DR_REG_PSRAM_MEM_MONITOR_BASE           0x6001A000
-#define DR_REG_AHB_DMA_BASE                     0x60080000
-#define DR_REG_GPSPI_BASE                       0x60081000
-#define DR_REG_SHA_BASE                         0x60089000
-#define DR_REG_ECC_MULT_BASE                    0x6008B000
-#define DR_REG_ECDSA_BASE                       0x6008E000
-#define DR_REG_IO_MUX_BASE                      0x60090000
-#define DR_REG_GPIO_BASE                        0x60091000
-#define DR_REG_GPIO_EXT_BASE                    0x60091E00
-#define DR_REG_TCM_MEM_MONITOR_BASE             0x60092000
-#define DR_REG_PAU_BASE                         0x60093000
-#define DR_REG_HP_SYSTEM_BASE                   0x60095000
-#define DR_REG_PCR_BASE                         0x60096000
-#define DR_REG_TEE_BASE                         0x60098000
-#define DR_REG_HP_APM_BASE                      0x60099000
-#define DR_REG_MISC_BASE                        0x6009F000
-#define DR_REG_MODEM0_BASE                      0x600A0000
-#define DR_REG_MODEM1_BASE                      0x600AC000
-#define DR_REG_MODEM_PWR0_BASE                  0x600AD000
-#define DR_REG_MODEM_PWR1_BASE                  0x600AF000
-#define DR_REG_I2C_ANA_MST_BASE                 0x600AF800
-#define DR_REG_PMU_BASE                         0x600B0000
-#define DR_REG_LP_CLKRST_BASE                   0x600B0400
-#define DR_REG_LP_TIMER_BASE                    0x600B0C00
-#define DR_REG_LP_AON_BASE                      0x600B1000
-#define DR_REG_LP_WDT_BASE                      0x600B1C00
-#define DR_REG_LPPERI_BASE                      0x600B2800
-#define DR_REG_LP_ANA_BASE                      0x600B2C00
-#define DR_REG_LP_TEE_BASE                      0x600B3400
-#define DR_REG_LP_APM_BASE                      0x600B3800
-#define DR_REG_LP_IO_MUX_BASE                   0x600B4000
-#define DR_REG_LP_GPIO_BASE                     0x600B4400
-#define DR_REG_EFUSE0_BASE                      0x600B4800
-#define DR_REG_EFUSE1_BASE                      0x600B4C00
-#define DR_REG_TRACE_BASE                       0x600C0000
-#define DR_REG_ASSIST_DEBUG_BASE                0x600C2000
-#define DR_REG_INTPRI_BASE                      0x600C5000
-#define DR_REG_CACHE_BASE                       0x600C8000
-#define DR_REG_CLINT_M_BASE                     0x20000000
diff --git a/components/soc/esp32c61/include/soc/regi2c_saradc.h b/components/soc/esp32c61/include/soc/regi2c_saradc.h
index c7137f3bb00..0a80bbbc539 100644
--- a/components/soc/esp32c61/include/soc/regi2c_saradc.h
+++ b/components/soc/esp32c61/include/soc/regi2c_saradc.h
@@ -18,41 +18,39 @@
 #define I2C_SAR_ADC            0X69
 #define I2C_SAR_ADC_HOSTID     0
 
-#define ADC_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
 
-#define ADC_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
+
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
+#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
 
 #define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
 #define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
 #define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
 
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
+#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
 
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
+#define ADC_SAR1_DREF_ADDR  0x2
+#define ADC_SAR1_DREF_ADDR_MSB  0x6
+#define ADC_SAR1_DREF_ADDR_LSB  0x4
 
 #define ADC_SAR2_INITIAL_CODE_LOW_ADDR  0x3
 #define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
 #define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
 
-#define ADC_SAR1_DREF_ADDR  0x2
-#define ADC_SAR1_DREF_ADDR_MSB  0x6
-#define ADC_SAR1_DREF_ADDR_LSB  0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
+#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
 
 #define ADC_SAR2_DREF_ADDR  0x5
 #define ADC_SAR2_DREF_ADDR_MSB  0x6
 #define ADC_SAR2_DREF_ADDR_LSB  0x4
 
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
+#define I2C_SARADC_TSENS_DAC 0x6
+#define I2C_SARADC_TSENS_DAC_MSB 3
+#define I2C_SARADC_TSENS_DAC_LSB 0
 
 #define ADC_SARADC_DTEST_RTC_ADDR 0x7
 #define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
@@ -70,10 +68,31 @@
 #define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
 #define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
 
+#define ADC_SAR1_ENCAL_GND_ADDR 0x7
+#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
+#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
+
 #define ADC_SARADC2_ENCAL_REF_ADDR 0x7
 #define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
 #define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
 
-#define I2C_SARADC_TSENS_DAC 0x6
-#define I2C_SARADC_TSENS_DAC_MSB 3
-#define I2C_SARADC_TSENS_DAC_LSB 0
+#define ADC_SAR2_ENCAL_GND_ADDR 0x7
+#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
+#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
+
+
+#define POWER_GLITCH_DREF_VDET_PERIF         11
+#define POWER_GLITCH_DREF_VDET_PERIF_MSB     2
+#define POWER_GLITCH_DREF_VDET_PERIF_LSB     0
+
+#define POWER_GLITCH_DREF_VDET_VDDPST        11
+#define POWER_GLITCH_DREF_VDET_VDDPST_MSB    6
+#define POWER_GLITCH_DREF_VDET_VDDPST_LSB    4
+
+#define POWER_GLITCH_DREF_VDET_PLLBB         12
+#define POWER_GLITCH_DREF_VDET_PLLBB_MSB      2
+#define POWER_GLITCH_DREF_VDET_PLLBB_LSB      0
+
+#define POWER_GLITCH_DREF_VDET_PLL           12
+#define POWER_GLITCH_DREF_VDET_PLL_MSB       6
+#define POWER_GLITCH_DREF_VDET_PLL_LSB       4
diff --git a/components/soc/esp32c61/include/soc/retention_periph_defs.h b/components/soc/esp32c61/include/soc/retention_periph_defs.h
index 5bc404860b7..dec99dd071e 100644
--- a/components/soc/esp32c61/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32c61/include/soc/retention_periph_defs.h
@@ -15,6 +15,7 @@ extern "C" {
 
 typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_MIN          = 0,
+    SLEEP_RETENTION_MODULE_NULL         = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
     SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 2,
@@ -33,6 +34,10 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_I2C0         = 12,
     SLEEP_RETENTION_MODULE_UART0        = 14,
     SLEEP_RETENTION_MODULE_UART1        = 15,
+    SLEEP_RETENTION_MODULE_ETM0         = 16,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 17,
+    SLEEP_RETENTION_MODULE_LEDC         = 18,
+    SLEEP_RETENTION_MODULE_I2S0         = 19,
 
     /* Modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_WIFI_MAC     = 26,
@@ -44,6 +49,8 @@ typedef enum periph_retention_module {
 } periph_retention_module_t;
 
 typedef enum periph_retention_module_bitmap {
+    SLEEP_RETENTION_MODULE_BM_NULL = BIT(SLEEP_RETENTION_MODULE_NULL),
+
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
     SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM  = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
@@ -62,6 +69,10 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_I2C0         = BIT(SLEEP_RETENTION_MODULE_I2C0),
     SLEEP_RETENTION_MODULE_BM_UART0        = BIT(SLEEP_RETENTION_MODULE_UART0),
     SLEEP_RETENTION_MODULE_BM_UART1        = BIT(SLEEP_RETENTION_MODULE_UART1),
+    SLEEP_RETENTION_MODULE_BM_ETM0         = BIT(SLEEP_RETENTION_MODULE_ETM0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
+    SLEEP_RETENTION_MODULE_BM_I2S0         = BIT(SLEEP_RETENTION_MODULE_I2S0),
     /* modem module, which includes WiFi, BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BM_WIFI_MAC     = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
     SLEEP_RETENTION_MODULE_BM_WIFI_BB      = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
@@ -81,6 +92,11 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_I2C0        \
                                   | SLEEP_RETENTION_MODULE_BM_UART0       \
                                   | SLEEP_RETENTION_MODULE_BM_UART1       \
+                                  | SLEEP_RETENTION_MODULE_BM_ETM0        \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC        \
+                                  | SLEEP_RETENTION_MODULE_BM_I2S0        \
+                                  | SLEEP_RETENTION_MODULE_BM_NULL       \
                                   )
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32c61/include/soc/sha_reg.h b/components/soc/esp32c61/include/soc/sha_reg.h
deleted file mode 100644
index ab9f346e774..00000000000
--- a/components/soc/esp32c61/include/soc/sha_reg.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SHA_MODE_REG register
- *  Configures SHA algorithm
- */
-#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
-/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  Configures the SHA algorithm. \\
- *  0: SHA-1\\
- *  1: SHA-224\\
- *  2: SHA-256\\
- */
-#define SHA_MODE    0x00000007U
-#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
-#define SHA_MODE_V  0x00000007U
-#define SHA_MODE_S  0
-
-/** SHA_T_STRING_REG register
- *  SHA 512/t configuration register 0.
- */
-#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
-/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
- *  Sha t_string (used if and only if mode == SHA_512/t).
- */
-#define SHA_T_STRING    0xFFFFFFFFU
-#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
-#define SHA_T_STRING_V  0xFFFFFFFFU
-#define SHA_T_STRING_S  0
-
-/** SHA_T_LENGTH_REG register
- *  SHA 512/t configuration register 1.
- */
-#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
-/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
- *  Sha t_length (used if and only if mode == SHA_512/t).
- */
-#define SHA_T_LENGTH    0x0000003FU
-#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
-#define SHA_T_LENGTH_V  0x0000003FU
-#define SHA_T_LENGTH_S  0
-
-/** SHA_DMA_BLOCK_NUM_REG register
- *  Block number register (only effective for DMA-SHA)
- */
-#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
-/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
- *  Configures the DMA-SHA block number.
- */
-#define SHA_DMA_BLOCK_NUM    0x0000003FU
-#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
-#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
-#define SHA_DMA_BLOCK_NUM_S  0
-
-/** SHA_START_REG register
- *  Starts the SHA accelerator for Typical SHA operation
- */
-#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
-/** SHA_START : RO; bitpos: [31:1]; default: 0;
- *  Write 1 to start Typical SHA calculation.
- */
-#define SHA_START    0x7FFFFFFFU
-#define SHA_START_M  (SHA_START_V << SHA_START_S)
-#define SHA_START_V  0x7FFFFFFFU
-#define SHA_START_S  1
-
-/** SHA_CONTINUE_REG register
- *  Continues SHA operation (only effective in Typical SHA mode)
- */
-#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
-/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
- *  Write 1 to continue Typical SHA calculation.
- */
-#define SHA_CONTINUE    0x7FFFFFFFU
-#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
-#define SHA_CONTINUE_V  0x7FFFFFFFU
-#define SHA_CONTINUE_S  1
-
-/** SHA_BUSY_REG register
- *  Represents if SHA Accelerator is busy or not
- */
-#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
-/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
- *  Represents the states of SHA accelerator. \\
- *  0: idle\\
- *  1: busy\\
- */
-#define SHA_BUSY_STATE    (BIT(0))
-#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
-#define SHA_BUSY_STATE_V  0x00000001U
-#define SHA_BUSY_STATE_S  0
-
-/** SHA_DMA_START_REG register
- *  Starts the SHA accelerator for DMA-SHA operation
- */
-#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
-/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
- *  Write 1 to start DMA-SHA calculation.
- */
-#define SHA_DMA_START    (BIT(0))
-#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
-#define SHA_DMA_START_V  0x00000001U
-#define SHA_DMA_START_S  0
-
-/** SHA_DMA_CONTINUE_REG register
- *  Continues SHA operation (only effective in DMA-SHA mode)
- */
-#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
-/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
- *  Write 1 to continue DMA-SHA calculation.
- */
-#define SHA_DMA_CONTINUE    (BIT(0))
-#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
-#define SHA_DMA_CONTINUE_V  0x00000001U
-#define SHA_DMA_CONTINUE_S  0
-
-/** SHA_CLEAR_IRQ_REG register
- *  DMA-SHA interrupt clear register
- */
-#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
-/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
- *  Write 1 to clear DMA-SHA interrupt.
- */
-#define SHA_CLEAR_INTERRUPT    (BIT(0))
-#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
-#define SHA_CLEAR_INTERRUPT_V  0x00000001U
-#define SHA_CLEAR_INTERRUPT_S  0
-
-/** SHA_IRQ_ENA_REG register
- *  DMA-SHA interrupt enable register
- */
-#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
-/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable DMA-SHA interrupt.
- */
-#define SHA_INTERRUPT_ENA    (BIT(0))
-#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
-#define SHA_INTERRUPT_ENA_V  0x00000001U
-#define SHA_INTERRUPT_ENA_S  0
-
-/** SHA_DATE_REG register
- *  Version control register
- */
-#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
-/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
- *  Version control register.
- */
-#define SHA_DATE    0x3FFFFFFFU
-#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
-#define SHA_DATE_V  0x3FFFFFFFU
-#define SHA_DATE_S  0
-
-/** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
- */
-#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
-#define SHA_H_MEM_SIZE_BYTES 64
-
-/** SHA_M_MEM register
- *  Sha M memory which contains message.
- */
-#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
-#define SHA_M_MEM_SIZE_BYTES 64
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h
index cd1b6e7537f..ca6ee32e031 100644
--- a/components/soc/esp32c61/include/soc/soc.h
+++ b/components/soc/esp32c61/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index bf1fab84d33..202f604b307 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -17,7 +17,7 @@
 #pragma once
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
-//  \#define SOC_ADC_SUPPORTED               1    //TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
+#define SOC_ADC_SUPPORTED               1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_UART_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
@@ -33,7 +33,7 @@
 #define SOC_SUPPORTS_SECURE_DL_MODE     1
 #define SOC_EFUSE_KEY_PURPOSE_FIELD     1
 #define SOC_EFUSE_SUPPORTED             1
-//  \#define SOC_I2S_SUPPORTED               1    //TODO: [ESP32C61] IDF-9312, IDF-9313
+#define SOC_I2S_SUPPORTED               1
 #define SOC_GPSPI_SUPPORTED             1
 #define SOC_I2C_SUPPORTED               1
 #define SOC_LEDC_SUPPORTED              1
@@ -56,7 +56,7 @@
 //  \#define SOC_RNG_SUPPORTED               1    //TODO: [ESP32C61] IDF-9236
 #define SOC_MODEM_CLOCK_SUPPORTED       1
 #define SOC_REG_I2C_SUPPORTED           1
-//  \#define SOC_ETM_SUPPORTED               0
+#define SOC_ETM_SUPPORTED               1
 //  \#define SOC_SDIO_SLAVE_SUPPORTED        0
 #define SOC_PAU_SUPPORTED               1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
@@ -67,35 +67,34 @@
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
 
-//TODO: [ESP32C61] IDF-9302, IDF-9303, IDF-9304
 /*-------------------------- ADC CAPS -------------------------------*/
 /*!< SAR ADC Module*/
-//  \#define SOC_ADC_DIG_CTRL_SUPPORTED              1
-//  \#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED        1
-//  \#define SOC_ADC_MONITOR_SUPPORTED               1
-//  \#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        1    //Digital controller supported ADC unit
-//  \#define SOC_ADC_DMA_SUPPORTED                   1
-#define SOC_ADC_PERIPH_NUM                      (1U)
-#define SOC_ADC_MAX_CHANNEL_NUM                 (7)
-//  \#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         (7)
-//  \#define SOC_ADC_ATTEN_NUM                       (4)
-
-// /*!< Digital */
-//  \#define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
-//  \#define SOC_ADC_PATT_LEN_MAX                    (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
-//  \#define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
-//  \#define SOC_ADC_DIGI_MIN_BITWIDTH               (12)
-//  \#define SOC_ADC_DIGI_IIR_FILTER_NUM             (2)
-//  \#define SOC_ADC_DIGI_MONITOR_NUM                (2)
-//  \#define SOC_ADC_DIGI_RESULT_BYTES               (4)
-//  \#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
-// /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
-//  \#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
-//  \#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
-
-// /*!< RTC */
-//  \#define SOC_ADC_RTC_MIN_BITWIDTH                (12)
-//  \#define SOC_ADC_RTC_MAX_BITWIDTH                (12)
+#define SOC_ADC_DIG_CTRL_SUPPORTED              1
+#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED        1
+#define SOC_ADC_MONITOR_SUPPORTED               1
+#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        1    //Digital controller supported ADC unit
+#define SOC_ADC_DMA_SUPPORTED                   1
+#define SOC_ADC_PERIPH_NUM                      (1)
+#define SOC_ADC_MAX_CHANNEL_NUM                 (4)
+#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         (4)
+#define SOC_ADC_ATTEN_NUM                       (4)
+
+/*!< Digital */
+#define SOC_ADC_DIGI_CONTROLLER_NUM             (1U)
+#define SOC_ADC_PATT_LEN_MAX                    (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
+#define SOC_ADC_DIGI_MAX_BITWIDTH               (12)
+#define SOC_ADC_DIGI_MIN_BITWIDTH               (12)
+#define SOC_ADC_DIGI_IIR_FILTER_NUM             (2)
+#define SOC_ADC_DIGI_MONITOR_NUM                (2)
+#define SOC_ADC_DIGI_RESULT_BYTES               (4)
+#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV        (4)
+/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
+#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
+#define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
+
+/*!< RTC */
+#define SOC_ADC_RTC_MIN_BITWIDTH                (12)
+#define SOC_ADC_RTC_MAX_BITWIDTH                (12)
 
 // /*!< Calibration */  // TODO: [ESP32C61] IDF-9303
 //  \#define SOC_ADC_CALIBRATION_V1_SUPPORTED        (1) /*!< support HW offset calibration version 1*/
@@ -106,7 +105,7 @@
 #define SOC_ADC_TEMPERATURE_SHARE_INTR          (1)
 
 /*!< ADC power control is shared by PWDET */
-//  \#define SOC_ADC_SHARED_POWER                    1
+#define SOC_ADC_SHARED_POWER                    1
 
 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
 #define SOC_APB_BACKUP_DMA              (0)
@@ -148,22 +147,23 @@
 #define SOC_AHB_GDMA_VERSION            2U
 #define SOC_GDMA_NUM_GROUPS_MAX         1U
 #define SOC_GDMA_PAIRS_PER_GROUP_MAX    2
-// \#define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule TODO: IDF-9964
+#define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1
 
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
 #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
+#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1   // Support sleep retention
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-C61 has 1 GPIO peripheral
 #define SOC_GPIO_PORT                      1U
-#define SOC_GPIO_PIN_COUNT                 22
+#define SOC_GPIO_PIN_COUNT                 25
 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
 #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER    1
 
 // GPIO peripheral has the ETM extension
-//  \#define SOC_GPIO_SUPPORT_ETM          1  //TODO: [ESP32C61] IDF-9318
+#define SOC_GPIO_SUPPORT_ETM          1
 
 // Target has the full LP IO subsystem
 // On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
@@ -172,19 +172,19 @@
 // LP IO peripherals have independent clock gating to manage
 #define SOC_LP_IO_CLOCK_IS_INDEPENDENT      (1)
 
-#define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
+#define SOC_GPIO_VALID_GPIO_MASK        ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
 
-#define SOC_GPIO_IN_RANGE_MAX           21
-#define SOC_GPIO_OUT_RANGE_MAX          21
+#define SOC_GPIO_IN_RANGE_MAX           24
+#define SOC_GPIO_OUT_RANGE_MAX          24
 
 // GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
 #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
 #define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT      (7)
 
-// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_21)
-#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFF80ULL
+// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_24)
+#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x1FFFF80ULL
 
 // Support to force hold all IOs
 #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
@@ -228,27 +228,34 @@
 #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
 #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
 #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION        (1)
 
 // /*-------------------------- I2S CAPS ----------------------------------------*/
-// #define SOC_I2S_NUM                 (1U)
-// #define SOC_I2S_HW_VERSION_2        (1)
-// #define SOC_I2S_SUPPORTS_XTAL       (1)
-// #define SOC_I2S_SUPPORTS_PLL_F160M  (1)
-// #define SOC_I2S_SUPPORTS_PCM        (1)
-// #define SOC_I2S_SUPPORTS_PDM        (1)
-// #define SOC_I2S_SUPPORTS_PDM_TX     (1)
-// #define SOC_I2S_PDM_MAX_TX_LINES    (2)
-// #define SOC_I2S_SUPPORTS_TDM        (1)
+#define SOC_I2S_NUM                     (1U)
+#define SOC_I2S_HW_VERSION_2            (1)
+#define SOC_I2S_SUPPORTS_ETM            (1)
+#define SOC_I2S_SUPPORTS_TX_SYNC_CNT    (1)
+#define SOC_I2S_SUPPORTS_XTAL           (1)
+#define SOC_I2S_SUPPORTS_PLL_F160M      (1)
+#define SOC_I2S_SUPPORTS_PLL_F120M      (1)
+#define SOC_I2S_SUPPORTS_PCM            (1)
+#define SOC_I2S_SUPPORTS_PDM            (1)
+#define SOC_I2S_SUPPORTS_PDM_TX         (1)
+#define SOC_I2S_PDM_MAX_TX_LINES        (2)
+#define SOC_I2S_SUPPORTS_TDM            (1)
+#define SOC_I2S_SUPPORT_SLEEP_RETENTION (1)
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_SUPPORT_SLEEP_RETENTION    (1)
 
 /*-------------------------- MMU CAPS ----------------------------------------*/
 #define SOC_MMU_PAGE_SIZE_CONFIGURABLE        (1)
@@ -303,6 +310,7 @@
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
 
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+#define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
 #define SOC_SPI_SUPPORT_CLK_XTAL            1
 #define SOC_SPI_SUPPORT_CLK_PLL             1
 #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
@@ -338,7 +346,7 @@
 #define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
 #define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
-// #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event
+#define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event
 
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
@@ -352,7 +360,7 @@
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
 #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
-// #define SOC_TIMER_SUPPORT_ETM             (1)
+#define SOC_TIMER_SUPPORT_ETM             (1)
 
 /*--------------------------- WATCHDOG CAPS ---------------------------------------*/
 // #define SOC_MWDT_SUPPORT_XTAL              (1)
@@ -454,8 +462,12 @@
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
 #define SOC_CLK_LP_FAST_SUPPORT_XTAL              (1)     /*!< Support XTAL clock as the LP_FAST clock source */
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2           (1)     /*!< Support XTAL_D2 clock as the LP_FAST clock source */
+
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 // #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 // #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)
@@ -473,7 +485,7 @@
 
 /*---------------------------------- Bluetooth CAPS ----------------------------------*/
 #define SOC_BLE_SUPPORTED                   (1)    /*!< Support Bluetooth Low Energy hardware */
-// #define SOC_BLE_MESH_SUPPORTED              (1)    /*!< Support BLE MESH */
+#define SOC_BLE_MESH_SUPPORTED              (1)    /*!< Support BLE MESH */
 #define SOC_ESP_NIMBLE_CONTROLLER           (1)    /*!< Support BLE EMBEDDED controller V1 */
 #define SOC_BLE_50_SUPPORTED                (1)    /*!< Support Bluetooth 5.0 */
 #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED    (1)   /*!< Support BLE device privacy mode */
diff --git a/components/soc/esp32c61/include/soc/spi_reg.h b/components/soc/esp32c61/include/soc/spi_reg.h
deleted file mode 100644
index 66a09daf9f3..00000000000
--- a/components/soc/esp32c61/include/soc/spi_reg.h
+++ /dev/null
@@ -1,2336 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SPI_CMD_REG register
- *  Command control register
- */
-#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0)
-/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  Configures the SPI_CLK cycles of SPI CONF state.
- *  Measurement unit: SPI_CLK clock cycle.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CONF_BITLEN    0x0003FFFFU
-#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
-#define SPI_CONF_BITLEN_V  0x0003FFFFU
-#define SPI_CONF_BITLEN_S  0
-/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
- *  Configures whether or not to synchronize SPI registers from APB clock domain into
- *  SPI module clock domain. \\
- *  0: Not synchronize \\
- *  1: Synchronize \\
- *  This bit is only used in SPI master transfer.
- */
-#define SPI_UPDATE    (BIT(23))
-#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
-#define SPI_UPDATE_V  0x00000001U
-#define SPI_UPDATE_S  23
-/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
- *  Configures whether or not to enable user-defined command. \\
- *  0: Not enable \\
- *  1: Enable \\
- *  An SPI operation will be triggered when the bit is set. This bit will be cleared
- *  once the operation is done. Can not be changed by CONF_buf.
- */
-#define SPI_USR    (BIT(24))
-#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
-#define SPI_USR_V  0x00000001U
-#define SPI_USR_S  24
-
-/** SPI_ADDR_REG register
- *  Address value register
- */
-#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4)
-/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  Configures the address to slave.
- *  Can be configured in CONF state.
- */
-#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
-#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_S  0
-
-/** SPI_CTRL_REG register
- *  SPI control register
- */
-#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8)
-/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to output the FSPI bus signals in DUMMY state. \\
- *  0: Not output \\
- *  1: Output \\
- *  Can be configured in CONF state.
- */
-#define SPI_DUMMY_OUT    (BIT(3))
-#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
-#define SPI_DUMMY_OUT_V  0x00000001U
-#define SPI_DUMMY_OUT_S  3
-/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable 2-bit mode during address (ADDR) state.\\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FADDR_DUAL    (BIT(5))
-#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
-#define SPI_FADDR_DUAL_V  0x00000001U
-#define SPI_FADDR_DUAL_S  5
-/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to enable 4-bit mode during address (ADDR) state. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FADDR_QUAD    (BIT(6))
-#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
-#define SPI_FADDR_QUAD_V  0x00000001U
-#define SPI_FADDR_QUAD_S  6
-/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0;
- *  Configures whether or not to enable 8-bit mode during address (ADDR) state. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FADDR_OCT    (BIT(7))
-#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
-#define SPI_FADDR_OCT_V  0x00000001U
-#define SPI_FADDR_OCT_S  7
-/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable 2-bit mode during command (CMD) state. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FCMD_DUAL    (BIT(8))
-#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
-#define SPI_FCMD_DUAL_V  0x00000001U
-#define SPI_FCMD_DUAL_S  8
-/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable 4-bit mode during command (CMD) state. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FCMD_QUAD    (BIT(9))
-#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
-#define SPI_FCMD_QUAD_V  0x00000001U
-#define SPI_FCMD_QUAD_S  9
-/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0;
- *  Configures whether or not to enable 8-bit mode during command (CMD) state. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FCMD_OCT    (BIT(10))
-#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
-#define SPI_FCMD_OCT_V  0x00000001U
-#define SPI_FCMD_OCT_S  10
-/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
- *  Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read
- *  operations. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FREAD_DUAL    (BIT(14))
-#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
-#define SPI_FREAD_DUAL_V  0x00000001U
-#define SPI_FREAD_DUAL_S  14
-/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read
- *  operations. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FREAD_QUAD    (BIT(15))
-#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
-#define SPI_FREAD_QUAD_V  0x00000001U
-#define SPI_FREAD_QUAD_S  15
-/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0;
- *  Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read
- *  operations. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FREAD_OCT    (BIT(16))
-#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
-#define SPI_FREAD_OCT_V  0x00000001U
-#define SPI_FREAD_OCT_S  16
-/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
- *  Configures MISO line polarity. \\
- *  0: Low \\
- *  1: High \\
- *  Can be configured in CONF state.
- */
-#define SPI_Q_POL    (BIT(18))
-#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
-#define SPI_Q_POL_V  0x00000001U
-#define SPI_Q_POL_S  18
-/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
- *  Configures MOSI line polarity. \\
- *  0: Low \\
- *  1: High \\
- *  Can be configured in CONF state.
- */
-#define SPI_D_POL    (BIT(19))
-#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
-#define SPI_D_POL_V  0x00000001U
-#define SPI_D_POL_S  19
-/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
- *  Configures SPI_HOLD output value when SPI is in idle. \\
- *  0: Output low \\
- *  1: Output high \\
- *  Can be configured in CONF state.
- */
-#define SPI_HOLD_POL    (BIT(20))
-#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
-#define SPI_HOLD_POL_V  0x00000001U
-#define SPI_HOLD_POL_S  20
-/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
- *  Configures the output value of write-protect signal when SPI is in idle. \\
- *  0: Output low \\
- *  1: Output high \\
- *  Can be configured in CONF state.
- */
-#define SPI_WP_POL    (BIT(21))
-#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
-#define SPI_WP_POL_V  0x00000001U
-#define SPI_WP_POL_S  21
-/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
- *  Configures the bit order in read-data (MISO) state. \\
- *  0: MSB first \\
- *  1: LSB first \\
- *  Can be configured in CONF state.
- */
-#define SPI_RD_BIT_ORDER    0x00000003U
-#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
-#define SPI_RD_BIT_ORDER_V  0x00000003U
-#define SPI_RD_BIT_ORDER_S  23
-/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
- *  Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI)
- *  states. \\
- *  0: MSB first \\
- *  1: LSB first \\
- *  Can be configured in CONF state.
- */
-#define SPI_WR_BIT_ORDER    0x00000003U
-#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
-#define SPI_WR_BIT_ORDER_V  0x00000003U
-#define SPI_WR_BIT_ORDER_S  25
-
-/** SPI_CLOCK_REG register
- *  SPI clock control register
- */
-#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc)
-/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
- *  In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it
- *  must be 0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_L    0x0000003FU
-#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
-#define SPI_CLKCNT_L_V  0x0000003FU
-#define SPI_CLKCNT_L_S  0
-/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
- *  Configures the duty cycle of SPI_CLK (high level) in master transfer.
- *  It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1).
- *  floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it
- *  must be 0. \\
- *  Can be configured in CONF state.
- */
-#define SPI_CLKCNT_H    0x0000003FU
-#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
-#define SPI_CLKCNT_H_V  0x0000003FU
-#define SPI_CLKCNT_H_S  6
-/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
- *  Configures the divider of SPI_CLK in master transfer.
- *  SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N +
- *  1). \\
- *  Can be configured in CONF state.
- */
-#define SPI_CLKCNT_N    0x0000003FU
-#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
-#define SPI_CLKCNT_N_V  0x0000003FU
-#define SPI_CLKCNT_N_S  12
-/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
- *  Configures the pre-divider of SPI_CLK in master transfer.
- *  Can be configured in CONF state.
- */
-#define SPI_CLKDIV_PRE    0x0000000FU
-#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
-#define SPI_CLKDIV_PRE_V  0x0000000FU
-#define SPI_CLKDIV_PRE_S  18
-/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- *  Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\
- *  0: SPI_CLK is divided from APB_CLK.\\
- *  1: SPI_CLK is eqaul to APB_CLK.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
-#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_CLK_EQU_SYSCLK_S  31
-
-/** SPI_USER_REG register
- *  SPI USER control register
- */
-#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10)
-/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable full-duplex communication. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_DOUTDIN    (BIT(0))
-#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
-#define SPI_DOUTDIN_V  0x00000001U
-#define SPI_DOUTDIN_S  0
-/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
- *  Configures whether or not to enable QPI mode. \\
- *  0: Disable \\
- *  1: Enable \\
- *  This configuration is applicable when the SPI controller works as master or slave.
- *  Can be configured in CONF state.
- */
-#define SPI_QPI_MODE    (BIT(3))
-#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
-#define SPI_QPI_MODE_V  0x00000001U
-#define SPI_QPI_MODE_S  3
-/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0;
- *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
- *  Can be configured in CONF state.
- */
-#define SPI_OPI_MODE    (BIT(4))
-#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
-#define SPI_OPI_MODE_V  0x00000001U
-#define SPI_OPI_MODE_S  4
-/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to change the polarity of TSCK in slave transfer. \\
- *  0: TSCK = SPI_CK_I \\
- *  1: TSCK = !SPI_CK_I \\
- */
-#define SPI_TSCK_I_EDGE    (BIT(5))
-#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
-#define SPI_TSCK_I_EDGE_V  0x00000001U
-#define SPI_TSCK_I_EDGE_S  5
-/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
- *  Configures whether or not to keep SPI CS low when SPI is in DONE state. \\
- *  0: Not keep low \\
- *  1: Keep low \\
- *  Can be configured in CONF state.
- */
-#define SPI_CS_HOLD    (BIT(6))
-#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
-#define SPI_CS_HOLD_V  0x00000001U
-#define SPI_CS_HOLD_S  6
-/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
- *  Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_CS_SETUP    (BIT(7))
-#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
-#define SPI_CS_SETUP_V  0x00000001U
-#define SPI_CS_SETUP_S  7
-/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to change the polarity of RSCK in slave transfer. \\
- *  0: RSCK = !SPI_CK_I \\
- *  1: RSCK = SPI_CK_I \\
- */
-#define SPI_RSCK_I_EDGE    (BIT(8))
-#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
-#define SPI_RSCK_I_EDGE_V  0x00000001U
-#define SPI_RSCK_I_EDGE_S  8
-/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  Configures SPI clock mode together with SPI_CK_IDLE_EDGE.
- *  Can be configured in CONF state. For more information, see Section <a href="GP-SPI2
- *  master clock control">link</a>.
- */
-#define SPI_CK_OUT_EDGE    (BIT(9))
-#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
-#define SPI_CK_OUT_EDGE_V  0x00000001U
-#define SPI_CK_OUT_EDGE_S  9
-/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable the 2-bit mode of read-data phase in write
- *  operations.\\
- *  0: Not enable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FWRITE_DUAL    (BIT(12))
-#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
-#define SPI_FWRITE_DUAL_V  0x00000001U
-#define SPI_FWRITE_DUAL_S  12
-/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable the 4-bit mode of read-data phase in write
- *  operations. \\
- *  0: Not enable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_FWRITE_QUAD    (BIT(13))
-#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
-#define SPI_FWRITE_QUAD_V  0x00000001U
-#define SPI_FWRITE_QUAD_S  13
-/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0;
- *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_OCT    (BIT(14))
-#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
-#define SPI_FWRITE_OCT_V  0x00000001U
-#define SPI_FWRITE_OCT_S  14
-/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable the CONF state for the next transaction
- *  (segment) in a configurable segmented transfer. \\
- *  0: this transfer will end after the current transaction (segment) is finished. Or
- *  this is not a configurable segmented transfer. \\
- *  1: this configurable segmented transfer will continue its next transaction
- *  (segment). \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_CONF_NXT    (BIT(15))
-#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
-#define SPI_USR_CONF_NXT_V  0x00000001U
-#define SPI_USR_CONF_NXT_S  15
-/** SPI_SIO : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable 3-line half-duplex communication, where MOSI
- *  and MISO signals share the same pin.\\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_SIO    (BIT(17))
-#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
-#define SPI_SIO_V  0x00000001U
-#define SPI_SIO_S  17
-/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
- *  Configures whether or not to enable high part mode, i.e., only access to high part
- *  of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
-#define SPI_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_USR_MISO_HIGHPART_S  24
-/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
- *  Configures whether or not to enable high part mode, i.e., only access to high part
- *  of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
-#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_USR_MOSI_HIGHPART_S  25
-/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
- *  Configures whether or not to disable SPI clock in DUMMY state. \\
- *  0: Not disable \\
- *  1: Disable \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
-#define SPI_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_USR_DUMMY_IDLE_S  26
-/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
- *  Configures whether or not to enable the write-data (DOUT) state of an operation. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_MOSI    (BIT(27))
-#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
-#define SPI_USR_MOSI_V  0x00000001U
-#define SPI_USR_MOSI_S  27
-/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to enable the read-data (DIN) state of an operation. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_MISO    (BIT(28))
-#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
-#define SPI_USR_MISO_V  0x00000001U
-#define SPI_USR_MISO_S  28
-/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
- *  Configures whether or not to enable the DUMMY state of an operation. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY    (BIT(29))
-#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
-#define SPI_USR_DUMMY_V  0x00000001U
-#define SPI_USR_DUMMY_S  29
-/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
- *  Configures whether or not to enable the address (ADDR) state of an operation. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_ADDR    (BIT(30))
-#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
-#define SPI_USR_ADDR_V  0x00000001U
-#define SPI_USR_ADDR_S  30
-/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
- *  Configures whether or not to enable the command (CMD) state of an operation. \\
- *  0: Disable \\
- *  1: Enable \\
- *  Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND    (BIT(31))
-#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
-#define SPI_USR_COMMAND_V  0x00000001U
-#define SPI_USR_COMMAND_S  31
-
-/** SPI_USER1_REG register
- *  SPI USER control register 1
- */
-#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14)
-/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
- *  Configures the length of DUMMY state.
- *  Measurement unit: SPI_CLK clock cycles.\\
- *  This value is (the expected cycle number - 1). Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
-#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
- *  Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error
- *  occurs in master full-/half-duplex transfers. \\
- *  0: Not end \\
- *  1: End \\
- */
-#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
-#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
-#define SPI_MST_WFULL_ERR_END_EN_S  16
-/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
- *  Configures the length of prepare (PREP) state.
- *  Measurement unit: SPI_CLK clock cycles.\\
- *  This value is equal to the expected cycles - 1. This field is used together with
- *  SPI_CS_SETUP. Can be configured in CONF state.
- */
-#define SPI_CS_SETUP_TIME    0x0000001FU
-#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
-#define SPI_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_CS_SETUP_TIME_S  17
-/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
- *  Configures the delay cycles of CS pin.
- *  Measurement unit: SPI_CLK clock cycles. \\
- *  This field is used together with SPI_CS_HOLD. Can be configured in CONF state.
- */
-#define SPI_CS_HOLD_TIME    0x0000001FU
-#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
-#define SPI_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_CS_HOLD_TIME_S  22
-/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
- *  Configures the bit length in address state.
- *  This value is (expected bit number - 1). Can be configured in CONF state.
- */
-#define SPI_USR_ADDR_BITLEN    0x0000001FU
-#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
-#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
-#define SPI_USR_ADDR_BITLEN_S  27
-
-/** SPI_USER2_REG register
- *  SPI USER control register 2
- */
-#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18)
-/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
- *  Configures the command value.
- *  Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
-#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_S  0
-/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
- *  Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty
- *  error occurs in master full-/half-duplex transfers. \\
- *  0: Not end \\
- *  1: End \\
- */
-#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
-#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
-#define SPI_MST_REMPTY_ERR_END_EN_S  27
-/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
- *  Configures the bit length of command state.
- *  This value is (expected bit number - 1). Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
-#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_S  28
-
-/** SPI_MS_DLEN_REG register
- *  SPI data bit length control register
- */
-#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c)
-/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  Configures the data bit length of SPI transfer in DMA-controlled master transfer or
- *  in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer
- *  in DMA-controlled slave transfer.
- *  This value shall be (expected bit_num - 1). Can be configured in CONF state.
- */
-#define SPI_MS_DATA_BITLEN    0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
-#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_S  0
-
-/** SPI_MISC_REG register
- *  SPI misc register
- */
-#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20)
-/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to disable SPI_CS$n pin.\\
- *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
- *  1: Disable SPI_CS$n pin.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CS0_DIS    (BIT(0))
-#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
-#define SPI_CS0_DIS_V  0x00000001U
-#define SPI_CS0_DIS_S  0
-/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
- *  Configures whether or not to disable SPI_CS$n pin.\\
- *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
- *  1: Disable SPI_CS$n pin.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CS1_DIS    (BIT(1))
-#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
-#define SPI_CS1_DIS_V  0x00000001U
-#define SPI_CS1_DIS_S  1
-/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
- *  Configures whether or not to disable SPI_CS$n pin.\\
- *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
- *  1: Disable SPI_CS$n pin.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CS2_DIS    (BIT(2))
-#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
-#define SPI_CS2_DIS_V  0x00000001U
-#define SPI_CS2_DIS_S  2
-/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
- *  Configures whether or not to disable SPI_CS$n pin.\\
- *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
- *  1: Disable SPI_CS$n pin.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CS3_DIS    (BIT(3))
-#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
-#define SPI_CS3_DIS_V  0x00000001U
-#define SPI_CS3_DIS_S  3
-/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
- *  Configures whether or not to disable SPI_CS$n pin.\\
- *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
- *  1: Disable SPI_CS$n pin.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CS4_DIS    (BIT(4))
-#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
-#define SPI_CS4_DIS_V  0x00000001U
-#define SPI_CS4_DIS_S  4
-/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
- *  Configures whether or not to disable SPI_CS$n pin.\\
- *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
- *  1: Disable SPI_CS$n pin.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CS5_DIS    (BIT(5))
-#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
-#define SPI_CS5_DIS_V  0x00000001U
-#define SPI_CS5_DIS_S  5
-/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to disable SPI_CLK output.\\
- *  0: Enable\\
- *  1: Disable\\
- *  Can be configured in CONF state.
- */
-#define SPI_CK_DIS    (BIT(6))
-#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
-#define SPI_CK_DIS_V  0x00000001U
-#define SPI_CK_DIS_S  6
-/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
- *  Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\
- *  0: SPI_CS$n is low active.\\
- *  1: SPI_CS$n is high active.\\
- *  Can be configured in CONF state.
- */
-#define SPI_MASTER_CS_POL    0x0000003FU
-#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
-#define SPI_MASTER_CS_POL_V  0x0000003FU
-#define SPI_MASTER_CS_POL_S  7
-/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0;
- *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
- *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
- */
-#define SPI_CLK_DATA_DTR_EN    (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
-#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
-#define SPI_CLK_DATA_DTR_EN_S  16
-/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0;
- *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
- *  Can be configured in CONF state.
- */
-#define SPI_DATA_DTR_EN    (BIT(17))
-#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
-#define SPI_DATA_DTR_EN_V  0x00000001U
-#define SPI_DATA_DTR_EN_S  17
-/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0;
- *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
- *  configured in CONF state.
- */
-#define SPI_ADDR_DTR_EN    (BIT(18))
-#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
-#define SPI_ADDR_DTR_EN_V  0x00000001U
-#define SPI_ADDR_DTR_EN_S  18
-/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0;
- *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
- *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
- *  configured in CONF state.
- */
-#define SPI_CMD_DTR_EN    (BIT(19))
-#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
-#define SPI_CMD_DTR_EN_V  0x00000001U
-#define SPI_CMD_DTR_EN_S  19
-/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not invert SPI slave input CS polarity.\\
- *  0: Not change\\
- *  1: Invert\\
- *  Can be configured in CONF state.
- */
-#define SPI_SLAVE_CS_POL    (BIT(23))
-#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
-#define SPI_SLAVE_CS_POL_V  0x00000001U
-#define SPI_SLAVE_CS_POL_S  23
-/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0;
- *  The default value of spi_dqs. Can be configured in CONF state.
- */
-#define SPI_DQS_IDLE_EDGE    (BIT(24))
-#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
-#define SPI_DQS_IDLE_EDGE_V  0x00000001U
-#define SPI_DQS_IDLE_EDGE_S  24
-/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
- *  Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\
- *  0: Low\\
- *  1: High\\
- *  Can be configured in CONF state.
- */
-#define SPI_CK_IDLE_EDGE    (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
-#define SPI_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_CK_IDLE_EDGE_S  29
-/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
- *  Configures whether or not to keep the SPI_CS line low.\\
- *  0: Not keep low\\
- *  1: Keep low\\
- *  Can be configured in CONF state.
- */
-#define SPI_CS_KEEP_ACTIVE    (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
-#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_CS_KEEP_ACTIVE_S  30
-/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
- *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
- *  spi quad input swap disable. Can be configured in CONF state.
- */
-#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
-#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
-#define SPI_QUAD_DIN_PIN_SWAP_S  31
-
-/** SPI_DIN_MODE_REG register
- *  SPI input delay mode configuration
- */
-#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24)
-/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures the input mode for FSPID signal.\\
- *  0: Input without delay\\
- *  1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\
- *  2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
- *  rising edge cycle\\
- *  3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
- *  falling edge cycle\\
- *  Can be configured in CONF state.
- */
-#define SPI_DIN0_MODE    0x00000003U
-#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
-#define SPI_DIN0_MODE_V  0x00000003U
-#define SPI_DIN0_MODE_S  0
-/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
- *  Configures the input mode for FSPIQ signal.\\
- *  0: Input without delay\\
- *  1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\
- *  2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
- *  rising edge cycle\\
- *  3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
- *  falling edge cycle\\
- *  Can be configured in CONF state.
- */
-#define SPI_DIN1_MODE    0x00000003U
-#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
-#define SPI_DIN1_MODE_V  0x00000003U
-#define SPI_DIN1_MODE_S  2
-/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
- *  Configures the input mode for FSPIWP signal.\\
- *  0: Input without delay\\
- *  1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\
- *  2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
- *  rising edge cycle\\
- *  3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
- *  falling edge cycle\\
- *  Can be configured in CONF state.
- */
-#define SPI_DIN2_MODE    0x00000003U
-#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
-#define SPI_DIN2_MODE_V  0x00000003U
-#define SPI_DIN2_MODE_S  4
-/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures the input mode for FSPIHD signal.\\
- *  0: Input without delay\\
- *  1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\
- *  2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
- *  rising edge cycle\\
- *  3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
- *  falling edge cycle\\
- *  Can be configured in CONF state.
- *
- */
-#define SPI_DIN3_MODE    0x00000003U
-#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
-#define SPI_DIN3_MODE_V  0x00000003U
-#define SPI_DIN3_MODE_S  6
-/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN4_MODE    0x00000003U
-#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
-#define SPI_DIN4_MODE_V  0x00000003U
-#define SPI_DIN4_MODE_S  8
-/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN5_MODE    0x00000003U
-#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
-#define SPI_DIN5_MODE_V  0x00000003U
-#define SPI_DIN5_MODE_S  10
-/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN6_MODE    0x00000003U
-#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
-#define SPI_DIN6_MODE_V  0x00000003U
-#define SPI_DIN6_MODE_S  12
-/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN7_MODE    0x00000003U
-#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
-#define SPI_DIN7_MODE_V  0x00000003U
-#define SPI_DIN7_MODE_S  14
-/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing
- *  module.\\
- *  0: Disable\\
- *  1: Enable\\
- *  Can be configured in CONF state.
- */
-#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
-#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
-#define SPI_TIMING_HCLK_ACTIVE_S  16
-
-/** SPI_DIN_NUM_REG register
- *  SPI input delay number configuration
- */
-#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28)
-/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
- *  Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\
- *  0: Delayed by 1 clock cycle\\
- *  1: Delayed by 2 clock cycles\\
- *  2: Delayed by 3 clock cycles\\
- *  3: Delayed by 4 clock cycles\\
- *  Can be configured in CONF state.
- */
-#define SPI_DIN0_NUM    0x00000003U
-#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
-#define SPI_DIN0_NUM_V  0x00000003U
-#define SPI_DIN0_NUM_S  0
-/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
- *  Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\
- *  0: Delayed by 1 clock cycle\\
- *  1: Delayed by 2 clock cycles\\
- *  2: Delayed by 3 clock cycles\\
- *  3: Delayed by 4 clock cycles\\
- *  Can be configured in CONF state.
- */
-#define SPI_DIN1_NUM    0x00000003U
-#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
-#define SPI_DIN1_NUM_V  0x00000003U
-#define SPI_DIN1_NUM_S  2
-/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
- *  Configures the delays to input signal FSPIWP based on the setting of
- *  SPI_DIN2_MODE.\\
- *  0: Delayed by 1 clock cycle\\
- *  1: Delayed by 2 clock cycles\\
- *  2: Delayed by 3 clock cycles\\
- *  3: Delayed by 4 clock cycles\\
- *  Can be configured in CONF state.
- */
-#define SPI_DIN2_NUM    0x00000003U
-#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
-#define SPI_DIN2_NUM_V  0x00000003U
-#define SPI_DIN2_NUM_S  4
-/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
- *  Configures the delays to input signal FSPIHD based on the setting of
- *  SPI_DIN3_MODE.\\
- *  0: Delayed by 1 clock cycle\\
- *  1: Delayed by 2 clock cycles\\
- *  2: Delayed by 3 clock cycles\\
- *  3: Delayed by 4 clock cycles\\
- *  Can be configured in CONF state.
- */
-#define SPI_DIN3_NUM    0x00000003U
-#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
-#define SPI_DIN3_NUM_V  0x00000003U
-#define SPI_DIN3_NUM_S  6
-/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN4_NUM    0x00000003U
-#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
-#define SPI_DIN4_NUM_V  0x00000003U
-#define SPI_DIN4_NUM_S  8
-/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN5_NUM    0x00000003U
-#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
-#define SPI_DIN5_NUM_V  0x00000003U
-#define SPI_DIN5_NUM_S  10
-/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN6_NUM    0x00000003U
-#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
-#define SPI_DIN6_NUM_V  0x00000003U
-#define SPI_DIN6_NUM_S  12
-/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN7_NUM    0x00000003U
-#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
-#define SPI_DIN7_NUM_V  0x00000003U
-#define SPI_DIN7_NUM_S  14
-
-/** SPI_DOUT_MODE_REG register
- *  SPI output delay mode configuration
- */
-#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c)
-/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
- *  Configures the output mode for FSPID signal.\\
- *  0: Output without delay\\
- *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
- *  Can be configured in CONF state.
- */
-#define SPI_DOUT0_MODE    (BIT(0))
-#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
-#define SPI_DOUT0_MODE_V  0x00000001U
-#define SPI_DOUT0_MODE_S  0
-/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
- *  Configures the output mode for FSPIQ signal.\\
- *  0: Output without delay\\
- *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
- *  Can be configured in CONF state.
- */
-#define SPI_DOUT1_MODE    (BIT(1))
-#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
-#define SPI_DOUT1_MODE_V  0x00000001U
-#define SPI_DOUT1_MODE_S  1
-/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
- *  Configures the output mode for FSPIWP signal.\\
- *  0: Output without delay\\
- *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
- *  Can be configured in CONF state.
- */
-#define SPI_DOUT2_MODE    (BIT(2))
-#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
-#define SPI_DOUT2_MODE_V  0x00000001U
-#define SPI_DOUT2_MODE_S  2
-/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
- *  Configures the output mode for FSPIHD signal.\\
- *  0: Output without delay\\
- *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
- *  Can be configured in CONF state.
- */
-#define SPI_DOUT3_MODE    (BIT(3))
-#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
-#define SPI_DOUT3_MODE_V  0x00000001U
-#define SPI_DOUT3_MODE_S  3
-/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT4_MODE    (BIT(4))
-#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
-#define SPI_DOUT4_MODE_V  0x00000001U
-#define SPI_DOUT4_MODE_S  4
-/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT5_MODE    (BIT(5))
-#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
-#define SPI_DOUT5_MODE_V  0x00000001U
-#define SPI_DOUT5_MODE_S  5
-/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT6_MODE    (BIT(6))
-#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
-#define SPI_DOUT6_MODE_V  0x00000001U
-#define SPI_DOUT6_MODE_S  6
-/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT7_MODE    (BIT(7))
-#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
-#define SPI_DOUT7_MODE_V  0x00000001U
-#define SPI_DOUT7_MODE_S  7
-/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0;
- *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
- *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_D_DQS_MODE    (BIT(8))
-#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
-#define SPI_D_DQS_MODE_V  0x00000001U
-#define SPI_D_DQS_MODE_S  8
-
-/** SPI_DMA_CONF_REG register
- *  SPI DMA control register
- */
-#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30)
-/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  Represents whether or not the DMA TX FIFO is ready for sending data.\\
- *  0: Ready\\
- *  1: Not ready\\
- */
-#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
-#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_S  0
-/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
- *  Represents whether or not the DMA RX FIFO is ready for receiving data.\\
- *  0: Ready\\
- *  1: Not ready\\
- */
-#define SPI_DMA_INFIFO_FULL    (BIT(1))
-#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
-#define SPI_DMA_INFIFO_FULL_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_S  1
-/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable DMA-controlled segmented transfer in slave
- *  half-duplex communication.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
-#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
-#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
-/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  In slave segmented transfer, if the size of the DMA RX buffer is smaller than the
- *  size of the received data, \\1: the data in all the following Wr_DMA transactions
- *  will not be received\\ 0: the data in this Wr_DMA transaction will not be received,
- *  but in the following transactions,\\
- *
- *  - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions
- *  will be received.
- *  - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will
- *  not be received.
- */
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
-/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  In slave segmented transfer, if the size of the DMA TX buffer is smaller than the
- *  size of the transmitted data,\\
- *  1: the data in the following transactions will not be updated, i.e. the old data is
- *  transmitted repeatedly.\\
- *  0: the data in this transaction will not be updated. But in the following
- *  transactions,\\
- *
- *  - if new data is filled in DMA TX FIFO, new data will be transmitted.
- *  - if no new data is filled in DMA TX FIFO, no new data will be transmitted.
- */
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
-/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
- *  1: In a DAM-controlled transfer, if the bit number of transferred data is equal to
- *  (SPI_MS_DATA_BITLEN + 1), then GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW will be set by
- *  hardware. 0: GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW is set by SPI_TRANS_DONE_INT event in
- *  a single transfer, or by an SPI_DMA_SEG_TRANS_DONE_INT event in a segmented
- *  transfer.
- */
-#define SPI_RX_EOF_EN    (BIT(21))
-#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
-#define SPI_RX_EOF_EN_V  0x00000001U
-#define SPI_RX_EOF_EN_S  21
-/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
- *  Configures whether or not to enable DMA-controlled receive data transfer.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define SPI_DMA_RX_ENA    (BIT(27))
-#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
-#define SPI_DMA_RX_ENA_V  0x00000001U
-#define SPI_DMA_RX_ENA_S  27
-/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to enable DMA-controlled send data transfer.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define SPI_DMA_TX_ENA    (BIT(28))
-#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
-#define SPI_DMA_TX_ENA_V  0x00000001U
-#define SPI_DMA_TX_ENA_S  28
-/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
- *  Configures whether or not to reset spi_rx_afifo as shown in Figure <a
- *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
- *  href="fig:spi-slave-data-flow-control">link</a>.\\
- *  0: Not reset\\
- *  1: Reset\\
- *  spi_rx_afifo is used to receive data in SPI master and slave transfer.
- */
-#define SPI_RX_AFIFO_RST    (BIT(29))
-#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
-#define SPI_RX_AFIFO_RST_V  0x00000001U
-#define SPI_RX_AFIFO_RST_S  29
-/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
- *  Configures whether or not to reset buf_tx_afifo as shown in Figure <a
- *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
- *  href="fig:spi-slave-data-flow-control">link</a>.\\
- *  0: Not reset\\
- *  1: Reset\\
- *  buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer.
- */
-#define SPI_BUF_AFIFO_RST    (BIT(30))
-#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
-#define SPI_BUF_AFIFO_RST_V  0x00000001U
-#define SPI_BUF_AFIFO_RST_S  30
-/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
- *  Configures whether or not to reset dma_tx_afifo as shown in Figure <a
- *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
- *  href="fig:spi-slave-data-flow-control">link</a>.\\
- *  0: Not reset\\
- *  1: Reset\\
- *  dma_tx_afifo is used to send data out in DMA-controlled slave transfer.
- */
-#define SPI_DMA_AFIFO_RST    (BIT(31))
-#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
-#define SPI_DMA_AFIFO_RST_V  0x00000001U
-#define SPI_DMA_AFIFO_RST_S  31
-
-/** SPI_DMA_INT_ENA_REG register
- *  SPI interrupt enable register
- */
-#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
-/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to enable SPI_SLV_EX_QPI_INT interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
-#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ENA_S  2
-/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Write 1 to enable SPI_SLV_EN_QPI_INT interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
-#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ENA_S  3
-/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Write 1 to enable SPI_SLV_CMD7_INT interrupt.
- */
-#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
-#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ENA_S  4
-/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Write 1 to enable SPI_SLV_CMD8_INT interrupt.
- */
-#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
-#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ENA_S  5
-/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Write 1 to enable SPI_SLV_CMD9_INT interrupt.
- */
-#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
-#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ENA_S  6
-/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Write 1 to enable SPI_SLV_CMDA_INT interrupt.
- */
-#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
-#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ENA_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Write 1 to enable SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Write 1 to enable SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  Write 1 to enable SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  Write 1 to enable SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
-/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Write 1 to enable SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
-#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ENA_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  Write 1 to enable SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  Write 1 to enable SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
-#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
-/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  Write 1 to enable SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
-#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ENA_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  Write 1 to enable SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  Write 1 to enable SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
-/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  Write 1 to enable SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ENA    (BIT(19))
-#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
-#define SPI_APP2_INT_ENA_V  0x00000001U
-#define SPI_APP2_INT_ENA_S  19
-/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  Write 1 to enable SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ENA    (BIT(20))
-#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
-#define SPI_APP1_INT_ENA_V  0x00000001U
-#define SPI_APP1_INT_ENA_S  20
-
-/** SPI_DMA_INT_CLR_REG register
- *  SPI interrupt clear register
- */
-#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
-/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear SPI_SLV_EX_QPI_INT interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
-#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_CLR_S  2
-/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear SPI_SLV_EN_QPI_INT interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
-#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_CLR_S  3
-/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Write 1 to clear SPI_SLV_CMD7_INT interrupt.
- */
-#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
-#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD7_INT_CLR_S  4
-/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear SPI_SLV_CMD8_INT interrupt.
- */
-#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
-#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD8_INT_CLR_S  5
-/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Write 1 to clear SPI_SLV_CMD9_INT interrupt.
- */
-#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
-#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD9_INT_CLR_S  6
-/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Write 1 to clear SPI_SLV_CMDA_INT interrupt.
- */
-#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
-#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMDA_INT_CLR_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Write 1 to clear SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Write 1 to clear SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Write 1 to clear SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Write 1 to clear SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
-/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Write 1 to clear SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
-#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_TRANS_DONE_INT_CLR_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Write 1 to clear SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
-/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Write 1 to clear SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
-#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
-/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Write 1 to clear SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
-#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_CLR_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Write 1 to clear SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Write 1 to clear SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
-/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Write 1 to clear SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_CLR    (BIT(19))
-#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
-#define SPI_APP2_INT_CLR_V  0x00000001U
-#define SPI_APP2_INT_CLR_S  19
-/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  Write 1 to clear SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_CLR    (BIT(20))
-#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
-#define SPI_APP1_INT_CLR_V  0x00000001U
-#define SPI_APP1_INT_CLR_S  20
-
-/** SPI_DMA_INT_RAW_REG register
- *  SPI interrupt raw register
- */
-#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
-/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status of SPI_SLV_EX_QPI_INT interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
-#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_RAW_S  2
-/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status of SPI_SLV_EN_QPI_INT interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
-#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_RAW_S  3
-/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt status of SPI_SLV_CMD7_INT interrupt.
- */
-#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
-#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD7_INT_RAW_S  4
-/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt status of SPI_SLV_CMD8_INT interrupt.
- */
-#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
-#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD8_INT_RAW_S  5
-/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt status of SPI_SLV_CMD9_INT interrupt.
- */
-#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
-#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD9_INT_RAW_S  6
-/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt status of SPI_SLV_CMDA_INT interrupt.
- */
-#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
-#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMDA_INT_RAW_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
-/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt status of SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
-#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_TRANS_DONE_INT_RAW_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
-/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
-#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
- *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
- *  bigger than 63. 0: Others.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
-/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
-#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_RAW_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
-/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw interrupt status of SPI_APP2_INT interrupt. The value is only controlled by
- *  the application.
- */
-#define SPI_APP2_INT_RAW    (BIT(19))
-#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
-#define SPI_APP2_INT_RAW_V  0x00000001U
-#define SPI_APP2_INT_RAW_S  19
-/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw interrupt status of SPI_APP1_INT interrupt. The value is only controlled by
- *  the application.
- */
-#define SPI_APP1_INT_RAW    (BIT(20))
-#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
-#define SPI_APP1_INT_RAW_V  0x00000001U
-#define SPI_APP1_INT_RAW_S  20
-
-/** SPI_DMA_INT_ST_REG register
- *  SPI interrupt status register
- */
-#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
- *  The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
- *  The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
-/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
- *  The interrupt status of SPI_SLV_EX_QPI_INT interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
-#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ST_S  2
-/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
- *  The interrupt status of SPI_SLV_EN_QPI_INT interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
-#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ST_S  3
-/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
- *  The interrupt status of SPI_SLV_CMD7_INT interrupt.
- */
-#define SPI_SLV_CMD7_INT_ST    (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
-#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ST_S  4
-/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
- *  The interrupt status of SPI_SLV_CMD8_INT interrupt.
- */
-#define SPI_SLV_CMD8_INT_ST    (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
-#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ST_S  5
-/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
- *  The interrupt status of SPI_SLV_CMD9_INT interrupt.
- */
-#define SPI_SLV_CMD9_INT_ST    (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
-#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ST_S  6
-/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
- *  The interrupt status of SPI_SLV_CMDA_INT interrupt.
- */
-#define SPI_SLV_CMDA_INT_ST    (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
-#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ST_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
- *  The interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
- *  The interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
- *  The interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
- *  The interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
-/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  The interrupt status of SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ST    (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
-#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ST_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
- *  The interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
-#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
-/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  The interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
-#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ST_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
- *  The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
- *  The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
-/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
- *  The interrupt status of SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ST    (BIT(19))
-#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
-#define SPI_APP2_INT_ST_V  0x00000001U
-#define SPI_APP2_INT_ST_S  19
-/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
- *  The interrupt status of SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ST    (BIT(20))
-#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
-#define SPI_APP1_INT_ST_V  0x00000001U
-#define SPI_APP1_INT_ST_S  20
-
-/** SPI_DMA_INT_SET_REG register
- *  SPI interrupt software set register
- */
-#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
- *  Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
- *  Write 1 to set SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
-/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
- *  Write 1 to set SPI_SLV_EX_QPI_INT interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
-#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_SET_S  2
-/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
- *  Write 1 to set SPI_SLV_EN_QPI_INT interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
-#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_SET_S  3
-/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
- *  Write 1 to set SPI_SLV_CMD7_INT interrupt.
- */
-#define SPI_SLV_CMD7_INT_SET    (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
-#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD7_INT_SET_S  4
-/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
- *  Write 1 to set SPI_SLV_CMD8_INT interrupt.
- */
-#define SPI_SLV_CMD8_INT_SET    (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
-#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD8_INT_SET_S  5
-/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
- *  Write 1 to set SPI_SLV_CMD9_INT interrupt.
- */
-#define SPI_SLV_CMD9_INT_SET    (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
-#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD9_INT_SET_S  6
-/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
- *  Write 1 to set SPI_SLV_CMDA_INT interrupt.
- */
-#define SPI_SLV_CMDA_INT_SET    (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
-#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
-#define SPI_SLV_CMDA_INT_SET_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
- *  Write 1 to set SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
-#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
- *  Write 1 to set SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
-#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
- *  Write 1 to set SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
-#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
- *  Write 1 to set SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
-#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
-/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
- *  Write 1 to set SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_SET    (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
-#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_TRANS_DONE_INT_SET_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
- *  Write 1 to set SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
-/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
- *  Write 1 to set SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
-#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
- *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
-/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
- *  Write 1 to set SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
-#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_SET_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
- *  Write 1 to set SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
- *  Write 1 to set SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
-/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
- *  Write 1 to set SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_SET    (BIT(19))
-#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
-#define SPI_APP2_INT_SET_V  0x00000001U
-#define SPI_APP2_INT_SET_S  19
-/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
- *  Write 1 to set SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_SET    (BIT(20))
-#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
-#define SPI_APP1_INT_SET_V  0x00000001U
-#define SPI_APP1_INT_SET_S  20
-
-/** SPI_W0_REG register
- *  SPI CPU-controlled buffer0
- */
-#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98)
-/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF0    0xFFFFFFFFU
-#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
-#define SPI_BUF0_V  0xFFFFFFFFU
-#define SPI_BUF0_S  0
-
-/** SPI_W1_REG register
- *  SPI CPU-controlled buffer1
- */
-#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c)
-/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF1    0xFFFFFFFFU
-#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
-#define SPI_BUF1_V  0xFFFFFFFFU
-#define SPI_BUF1_S  0
-
-/** SPI_W2_REG register
- *  SPI CPU-controlled buffer2
- */
-#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0)
-/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF2    0xFFFFFFFFU
-#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
-#define SPI_BUF2_V  0xFFFFFFFFU
-#define SPI_BUF2_S  0
-
-/** SPI_W3_REG register
- *  SPI CPU-controlled buffer3
- */
-#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4)
-/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF3    0xFFFFFFFFU
-#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
-#define SPI_BUF3_V  0xFFFFFFFFU
-#define SPI_BUF3_S  0
-
-/** SPI_W4_REG register
- *  SPI CPU-controlled buffer4
- */
-#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8)
-/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF4    0xFFFFFFFFU
-#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
-#define SPI_BUF4_V  0xFFFFFFFFU
-#define SPI_BUF4_S  0
-
-/** SPI_W5_REG register
- *  SPI CPU-controlled buffer5
- */
-#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac)
-/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF5    0xFFFFFFFFU
-#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
-#define SPI_BUF5_V  0xFFFFFFFFU
-#define SPI_BUF5_S  0
-
-/** SPI_W6_REG register
- *  SPI CPU-controlled buffer6
- */
-#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0)
-/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF6    0xFFFFFFFFU
-#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
-#define SPI_BUF6_V  0xFFFFFFFFU
-#define SPI_BUF6_S  0
-
-/** SPI_W7_REG register
- *  SPI CPU-controlled buffer7
- */
-#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4)
-/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF7    0xFFFFFFFFU
-#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
-#define SPI_BUF7_V  0xFFFFFFFFU
-#define SPI_BUF7_S  0
-
-/** SPI_W8_REG register
- *  SPI CPU-controlled buffer8
- */
-#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8)
-/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF8    0xFFFFFFFFU
-#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
-#define SPI_BUF8_V  0xFFFFFFFFU
-#define SPI_BUF8_S  0
-
-/** SPI_W9_REG register
- *  SPI CPU-controlled buffer9
- */
-#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc)
-/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF9    0xFFFFFFFFU
-#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
-#define SPI_BUF9_V  0xFFFFFFFFU
-#define SPI_BUF9_S  0
-
-/** SPI_W10_REG register
- *  SPI CPU-controlled buffer10
- */
-#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0)
-/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF10    0xFFFFFFFFU
-#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
-#define SPI_BUF10_V  0xFFFFFFFFU
-#define SPI_BUF10_S  0
-
-/** SPI_W11_REG register
- *  SPI CPU-controlled buffer11
- */
-#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4)
-/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF11    0xFFFFFFFFU
-#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
-#define SPI_BUF11_V  0xFFFFFFFFU
-#define SPI_BUF11_S  0
-
-/** SPI_W12_REG register
- *  SPI CPU-controlled buffer12
- */
-#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8)
-/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF12    0xFFFFFFFFU
-#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
-#define SPI_BUF12_V  0xFFFFFFFFU
-#define SPI_BUF12_S  0
-
-/** SPI_W13_REG register
- *  SPI CPU-controlled buffer13
- */
-#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc)
-/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF13    0xFFFFFFFFU
-#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
-#define SPI_BUF13_V  0xFFFFFFFFU
-#define SPI_BUF13_S  0
-
-/** SPI_W14_REG register
- *  SPI CPU-controlled buffer14
- */
-#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0)
-/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF14    0xFFFFFFFFU
-#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
-#define SPI_BUF14_V  0xFFFFFFFFU
-#define SPI_BUF14_S  0
-
-/** SPI_W15_REG register
- *  SPI CPU-controlled buffer15
- */
-#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4)
-/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
- *  32-bit data buffer $n.
- */
-#define SPI_BUF15    0xFFFFFFFFU
-#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
-#define SPI_BUF15_V  0xFFFFFFFFU
-#define SPI_BUF15_S  0
-
-/** SPI_SLAVE_REG register
- *  SPI slave control register
- */
-#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0)
-/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  Configures SPI clock mode.\\
- *  0: SPI clock is off when CS becomes inactive.\\
- *  1: SPI clock is delayed one cycle after CS becomes inactive.\\
- *  2: SPI clock is delayed two cycles after CS becomes inactive.\\
- *  3: SPI clock is always on.\\
- *  Can be configured in CONF state.
- */
-#define SPI_CLK_MODE    0x00000003U
-#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
-#define SPI_CLK_MODE_V  0x00000003U
-#define SPI_CLK_MODE_S  0
-/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
- *  Configure clock mode.\\
- *  0: Support SPI clock mode 0 or 2. See Table <a
- *  href="table:clock_pol_slave">link</a>.\\
- *  1: Support SPI clock mode 1 or 3. See Table <a
- *  href="table:clock_pol_slave">link</a>.\\
- */
-#define SPI_CLK_MODE_13    (BIT(2))
-#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
-#define SPI_CLK_MODE_13_V  0x00000001U
-#define SPI_CLK_MODE_13_S  2
-/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
- *  Configures the edge of output data.\\
- *  0: Output data at TSCK rising edge.\\
- *  1: Output data at RSCK rising edge.\\
- */
-#define SPI_RSCK_DATA_OUT    (BIT(3))
-#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
-#define SPI_RSCK_DATA_OUT_V  0x00000001U
-#define SPI_RSCK_DATA_OUT_S  3
-/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
- *  of Rd_DMA transfer.\\
- *  0: Not use\\
- *  1: Use\\
- */
-#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
-#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDDMA_BITLEN_EN_S  8
-/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
- *  of Wr_DMA transfer.\\
- *  0: Not use\\
- *  1: Use\\
- */
-#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
-#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRDMA_BITLEN_EN_S  9
-/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
- *  of Rd_BUF transfer.\\
- *  0: Not use\\
- *  1: Use\\
- */
-#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
-#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDBUF_BITLEN_EN_S  10
-/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
- *  of Wr_BUF transfer.\\
- *  0: Not use\\
- *  1: Use\\
- */
-#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
-#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRBUF_BITLEN_EN_S  11
-/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0;
- *  Represents the effective bit of the last received data byte in SPI slave FD and HD
- *  mode.
- */
-#define SPI_SLV_LAST_BYTE_STRB    0x000000FFU
-#define SPI_SLV_LAST_BYTE_STRB_M  (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S)
-#define SPI_SLV_LAST_BYTE_STRB_V  0x000000FFU
-#define SPI_SLV_LAST_BYTE_STRB_S  12
-/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
- *  Configures the magic value of BM table in DMA-controlled configurable segmented
- *  transfer.
- */
-#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
-#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_S  22
-/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
- *  Configures SPI work mode.\\
- *  0: Master\\
- *  1: Slave\\
- */
-#define SPI_SLAVE_MODE    (BIT(26))
-#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
-#define SPI_SLAVE_MODE_V  0x00000001U
-#define SPI_SLAVE_MODE_S  26
-/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
- *  Configures whether to reset the SPI clock line, CS line, and data line via
- *  software.\\
- *  0: Not reset\\
- *  1: Reset\\
- *  Can be configured in CONF state.
- */
-#define SPI_SOFT_RESET    (BIT(27))
-#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
-#define SPI_SOFT_RESET_V  0x00000001U
-#define SPI_SOFT_RESET_S  27
-/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to enable the CONF state of current DMA-controlled
- *  configurable segmented transfer.\\
- *  0: No effect, which means the current transfer is not a configurable segmented
- *  transfer.\\
- *  1: Enable, which means a configurable segmented transfer is started.\\
- */
-#define SPI_USR_CONF    (BIT(28))
-#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
-#define SPI_USR_CONF_V  0x00000001U
-#define SPI_USR_CONF_S  28
-/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
- *  Configures whether or not to wait DMA TX data gets ready before starting SPI
- *  transfer in master full-duplex transfer.\\
- *  0: Not wait\\
- *  1: Wait\\
- */
-#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
-
-/** SPI_SLAVE1_REG register
- *  SPI slave control register 1
- */
-#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4)
-/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
- *  Configures the transferred data bit length in SPI slave full-/half-duplex modes.
- */
-#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
-#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_S  0
-/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
- *  Configures the command value in slave mode.
- */
-#define SPI_SLV_LAST_COMMAND    0x000000FFU
-#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
-#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
-#define SPI_SLV_LAST_COMMAND_S  18
-/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
- *  Configures the address value in slave mode.
- */
-#define SPI_SLV_LAST_ADDR    0x0000003FU
-#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
-#define SPI_SLV_LAST_ADDR_V  0x0000003FU
-#define SPI_SLV_LAST_ADDR_S  26
-
-/** SPI_CLK_GATE_REG register
- *  SPI module clock and register clock control
- */
-#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8)
-/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable clock gate.\\
- *  0: Disable\\
- *  1: Enable\\
- */
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
-#define SPI_CLK_EN_V  0x00000001U
-#define SPI_CLK_EN_S  0
-/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
- *  Set this bit to power on the SPI module clock.
- */
-#define SPI_MST_CLK_ACTIVE    (BIT(1))
-#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
-#define SPI_MST_CLK_ACTIVE_V  0x00000001U
-#define SPI_MST_CLK_ACTIVE_S  1
-/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
- *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
- *  0: XTAL CLK.
- */
-#define SPI_MST_CLK_SEL    (BIT(2))
-#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
-#define SPI_MST_CLK_SEL_V  0x00000001U
-#define SPI_MST_CLK_SEL_S  2
-
-/** SPI_DATE_REG register
- *  Version control
- */
-#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0)
-/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931;
- *  Version control register.
- */
-#define SPI_DATE    0x0FFFFFFFU
-#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
-#define SPI_DATE_V  0x0FFFFFFFU
-#define SPI_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/spi_struct.h b/components/soc/esp32c61/include/soc/spi_struct.h
deleted file mode 100644
index 7b84c9d658d..00000000000
--- a/components/soc/esp32c61/include/soc/spi_struct.h
+++ /dev/null
@@ -1,1625 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: User-defined control registers */
-/** Type of cmd register
- *  Command control register
- */
-typedef union {
-    struct {
-        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  Configures the SPI_CLK cycles of SPI CONF state.
-         *  Measurement unit: SPI_CLK clock cycle.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t conf_bitlen:18;
-        uint32_t reserved_18:5;
-        /** update : WT; bitpos: [23]; default: 0;
-         *  Configures whether or not to synchronize SPI registers from APB clock domain into
-         *  SPI module clock domain. \\
-         *  0: Not synchronize \\
-         *  1: Synchronize \\
-         *  This bit is only used in SPI master transfer.
-         */
-        uint32_t update:1;
-        /** usr : R/W/SC; bitpos: [24]; default: 0;
-         *  Configures whether or not to enable user-defined command. \\
-         *  0: Not enable \\
-         *  1: Enable \\
-         *  An SPI operation will be triggered when the bit is set. This bit will be cleared
-         *  once the operation is done. Can not be changed by CONF_buf.
-         */
-        uint32_t usr:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} spi_cmd_reg_t;
-
-/** Type of addr register
- *  Address value register
- */
-typedef union {
-    struct {
-        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the address to slave.
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_addr_value:32;
-    };
-    uint32_t val;
-} spi_addr_reg_t;
-
-/** Type of user register
- *  SPI USER control register
- */
-typedef union {
-    struct {
-        /** doutdin : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable full-duplex communication. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t doutdin:1;
-        uint32_t reserved_1:2;
-        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable QPI mode. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  This configuration is applicable when the SPI controller works as master or slave.
-         *  Can be configured in CONF state.
-         */
-        uint32_t qpi_mode:1;
-        /** opi_mode : HRO; bitpos: [4]; default: 0;
-         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t opi_mode:1;
-        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to change the polarity of TSCK in slave transfer. \\
-         *  0: TSCK = SPI_CK_I \\
-         *  1: TSCK = !SPI_CK_I \\
-         */
-        uint32_t tsck_i_edge:1;
-        /** cs_hold : R/W; bitpos: [6]; default: 1;
-         *  Configures whether or not to keep SPI CS low when SPI is in DONE state. \\
-         *  0: Not keep low \\
-         *  1: Keep low \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs_hold:1;
-        /** cs_setup : R/W; bitpos: [7]; default: 1;
-         *  Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs_setup:1;
-        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to change the polarity of RSCK in slave transfer. \\
-         *  0: RSCK = !SPI_CK_I \\
-         *  1: RSCK = SPI_CK_I \\
-         */
-        uint32_t rsck_i_edge:1;
-        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  Configures SPI clock mode together with SPI_CK_IDLE_EDGE.
-         *  Can be configured in CONF state. For more information, see Section <a href="GP-SPI2
-         *  master clock control">link</a>.
-         */
-        uint32_t ck_out_edge:1;
-        uint32_t reserved_10:2;
-        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable the 2-bit mode of read-data phase in write
-         *  operations.\\
-         *  0: Not enable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t fwrite_dual:1;
-        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable the 4-bit mode of read-data phase in write
-         *  operations. \\
-         *  0: Not enable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t fwrite_quad:1;
-        /** fwrite_oct : HRO; bitpos: [14]; default: 0;
-         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_oct:1;
-        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable the CONF state for the next transaction
-         *  (segment) in a configurable segmented transfer. \\
-         *  0: this transfer will end after the current transaction (segment) is finished. Or
-         *  this is not a configurable segmented transfer. \\
-         *  1: this configurable segmented transfer will continue its next transaction
-         *  (segment). \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_conf_nxt:1;
-        uint32_t reserved_16:1;
-        /** sio : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable 3-line half-duplex communication, where MOSI
-         *  and MISO signals share the same pin.\\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t sio:1;
-        uint32_t reserved_18:6;
-        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
-         *  Configures whether or not to enable high part mode, i.e., only access to high part
-         *  of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_miso_highpart:1;
-        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
-         *  Configures whether or not to enable high part mode, i.e., only access to high part
-         *  of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_mosi_highpart:1;
-        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
-         *  Configures whether or not to disable SPI clock in DUMMY state. \\
-         *  0: Not disable \\
-         *  1: Disable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_dummy_idle:1;
-        /** usr_mosi : R/W; bitpos: [27]; default: 0;
-         *  Configures whether or not to enable the write-data (DOUT) state of an operation. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_mosi:1;
-        /** usr_miso : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable the read-data (DIN) state of an operation. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_miso:1;
-        /** usr_dummy : R/W; bitpos: [29]; default: 0;
-         *  Configures whether or not to enable the DUMMY state of an operation. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_dummy:1;
-        /** usr_addr : R/W; bitpos: [30]; default: 0;
-         *  Configures whether or not to enable the address (ADDR) state of an operation. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_addr:1;
-        /** usr_command : R/W; bitpos: [31]; default: 1;
-         *  Configures whether or not to enable the command (CMD) state of an operation. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_command:1;
-    };
-    uint32_t val;
-} spi_user_reg_t;
-
-/** Type of user1 register
- *  SPI USER control register 1
- */
-typedef union {
-    struct {
-        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
-         *  Configures the length of DUMMY state.
-         *  Measurement unit: SPI_CLK clock cycles.\\
-         *  This value is (the expected cycle number - 1). Can be configured in CONF state.
-         */
-        uint32_t usr_dummy_cyclelen:8;
-        uint32_t reserved_8:8;
-        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
-         *  Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error
-         *  occurs in master full-/half-duplex transfers. \\
-         *  0: Not end \\
-         *  1: End \\
-         */
-        uint32_t mst_wfull_err_end_en:1;
-        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
-         *  Configures the length of prepare (PREP) state.
-         *  Measurement unit: SPI_CLK clock cycles.\\
-         *  This value is equal to the expected cycles - 1. This field is used together with
-         *  SPI_CS_SETUP. Can be configured in CONF state.
-         */
-        uint32_t cs_setup_time:5;
-        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
-         *  Configures the delay cycles of CS pin.
-         *  Measurement unit: SPI_CLK clock cycles. \\
-         *  This field is used together with SPI_CS_HOLD. Can be configured in CONF state.
-         */
-        uint32_t cs_hold_time:5;
-        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
-         *  Configures the bit length in address state.
-         *  This value is (expected bit number - 1). Can be configured in CONF state.
-         */
-        uint32_t usr_addr_bitlen:5;
-    };
-    uint32_t val;
-} spi_user1_reg_t;
-
-/** Type of user2 register
- *  SPI USER control register 2
- */
-typedef union {
-    struct {
-        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the command value.
-         *  Can be configured in CONF state.
-         */
-        uint32_t usr_command_value:16;
-        uint32_t reserved_16:11;
-        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
-         *  Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty
-         *  error occurs in master full-/half-duplex transfers. \\
-         *  0: Not end \\
-         *  1: End \\
-         */
-        uint32_t mst_rempty_err_end_en:1;
-        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
-         *  Configures the bit length of command state.
-         *  This value is (expected bit number - 1). Can be configured in CONF state.
-         */
-        uint32_t usr_command_bitlen:4;
-    };
-    uint32_t val;
-} spi_user2_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of ctrl register
- *  SPI control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** dummy_out : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to output the FSPI bus signals in DUMMY state. \\
-         *  0: Not output \\
-         *  1: Output \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t dummy_out:1;
-        uint32_t reserved_4:1;
-        /** faddr_dual : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable 2-bit mode during address (ADDR) state.\\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t faddr_dual:1;
-        /** faddr_quad : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable 4-bit mode during address (ADDR) state. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t faddr_quad:1;
-        /** faddr_oct : HRO; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable 8-bit mode during address (ADDR) state. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t faddr_oct:1;
-        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable 2-bit mode during command (CMD) state. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t fcmd_dual:1;
-        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable 4-bit mode during command (CMD) state. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t fcmd_quad:1;
-        /** fcmd_oct : HRO; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable 8-bit mode during command (CMD) state. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t fcmd_oct:1;
-        uint32_t reserved_11:3;
-        /** fread_dual : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read
-         *  operations. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t fread_dual:1;
-        /** fread_quad : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read
-         *  operations. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t fread_quad:1;
-        /** fread_oct : HRO; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read
-         *  operations. \\
-         *  0: Disable \\
-         *  1: Enable \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t fread_oct:1;
-        uint32_t reserved_17:1;
-        /** q_pol : R/W; bitpos: [18]; default: 1;
-         *  Configures MISO line polarity. \\
-         *  0: Low \\
-         *  1: High \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t q_pol:1;
-        /** d_pol : R/W; bitpos: [19]; default: 1;
-         *  Configures MOSI line polarity. \\
-         *  0: Low \\
-         *  1: High \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t d_pol:1;
-        /** hold_pol : R/W; bitpos: [20]; default: 1;
-         *  Configures SPI_HOLD output value when SPI is in idle. \\
-         *  0: Output low \\
-         *  1: Output high \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t hold_pol:1;
-        /** wp_pol : R/W; bitpos: [21]; default: 1;
-         *  Configures the output value of write-protect signal when SPI is in idle. \\
-         *  0: Output low \\
-         *  1: Output high \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t wp_pol:1;
-        uint32_t reserved_22:1;
-        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
-         *  Configures the bit order in read-data (MISO) state. \\
-         *  0: MSB first \\
-         *  1: LSB first \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t rd_bit_order:2;
-        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
-         *  Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI)
-         *  states. \\
-         *  0: MSB first \\
-         *  1: LSB first \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t wr_bit_order:2;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} spi_ctrl_reg_t;
-
-/** Type of ms_dlen register
- *  SPI data bit length control register
- */
-typedef union {
-    struct {
-        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  Configures the data bit length of SPI transfer in DMA-controlled master transfer or
-         *  in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer
-         *  in DMA-controlled slave transfer.
-         *  This value shall be (expected bit_num - 1). Can be configured in CONF state.
-         */
-        uint32_t ms_data_bitlen:18;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} spi_ms_dlen_reg_t;
-
-/** Type of misc register
- *  SPI misc register
- */
-typedef union {
-    struct {
-        /** cs0_dis : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to disable SPI_CS$n pin.\\
-         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
-         *  1: Disable SPI_CS$n pin.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs0_dis:1;
-        /** cs1_dis : R/W; bitpos: [1]; default: 1;
-         *  Configures whether or not to disable SPI_CS$n pin.\\
-         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
-         *  1: Disable SPI_CS$n pin.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs1_dis:1;
-        /** cs2_dis : R/W; bitpos: [2]; default: 1;
-         *  Configures whether or not to disable SPI_CS$n pin.\\
-         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
-         *  1: Disable SPI_CS$n pin.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs2_dis:1;
-        /** cs3_dis : R/W; bitpos: [3]; default: 1;
-         *  Configures whether or not to disable SPI_CS$n pin.\\
-         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
-         *  1: Disable SPI_CS$n pin.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs3_dis:1;
-        /** cs4_dis : R/W; bitpos: [4]; default: 1;
-         *  Configures whether or not to disable SPI_CS$n pin.\\
-         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
-         *  1: Disable SPI_CS$n pin.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs4_dis:1;
-        /** cs5_dis : R/W; bitpos: [5]; default: 1;
-         *  Configures whether or not to disable SPI_CS$n pin.\\
-         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
-         *  1: Disable SPI_CS$n pin.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs5_dis:1;
-        /** ck_dis : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to disable SPI_CLK output.\\
-         *  0: Enable\\
-         *  1: Disable\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t ck_dis:1;
-        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
-         *  Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\
-         *  0: SPI_CS$n is low active.\\
-         *  1: SPI_CS$n is high active.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t master_cs_pol:6;
-        uint32_t reserved_13:3;
-        /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0;
-         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
-         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
-         */
-        uint32_t clk_data_dtr_en:1;
-        /** data_dtr_en : HRO; bitpos: [17]; default: 0;
-         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
-         *  Can be configured in CONF state.
-         */
-        uint32_t data_dtr_en:1;
-        /** addr_dtr_en : HRO; bitpos: [18]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t addr_dtr_en:1;
-        /** cmd_dtr_en : HRO; bitpos: [19]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
-         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cmd_dtr_en:1;
-        uint32_t reserved_20:3;
-        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
-         *  Configures whether or not invert SPI slave input CS polarity.\\
-         *  0: Not change\\
-         *  1: Invert\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t slave_cs_pol:1;
-        /** dqs_idle_edge : HRO; bitpos: [24]; default: 0;
-         *  The default value of spi_dqs. Can be configured in CONF state.
-         */
-        uint32_t dqs_idle_edge:1;
-        uint32_t reserved_25:4;
-        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
-         *  Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\
-         *  0: Low\\
-         *  1: High\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t ck_idle_edge:1;
-        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
-         *  Configures whether or not to keep the SPI_CS line low.\\
-         *  0: Not keep low\\
-         *  1: Keep low\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs_keep_active:1;
-        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
-         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
-         *  spi quad input swap disable. Can be configured in CONF state.
-         */
-        uint32_t quad_din_pin_swap:1;
-    };
-    uint32_t val;
-} spi_misc_reg_t;
-
-/** Type of dma_conf register
- *  SPI DMA control register
- */
-typedef union {
-    struct {
-        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
-         *  Represents whether or not the DMA TX FIFO is ready for sending data.\\
-         *  0: Ready\\
-         *  1: Not ready\\
-         */
-        uint32_t dma_outfifo_empty:1;
-        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
-         *  Represents whether or not the DMA RX FIFO is ready for receiving data.\\
-         *  0: Ready\\
-         *  1: Not ready\\
-         */
-        uint32_t dma_infifo_full:1;
-        uint32_t reserved_2:16;
-        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable DMA-controlled segmented transfer in slave
-         *  half-duplex communication.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t dma_slv_seg_trans_en:1;
-        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
-         *  In slave segmented transfer, if the size of the DMA RX buffer is smaller than the
-         *  size of the received data, \\1: the data in all the following Wr_DMA transactions
-         *  will not be received\\ 0: the data in this Wr_DMA transaction will not be received,
-         *  but in the following transactions,\\
-         *
-         *  - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions
-         *  will be received.
-         *  - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will
-         *  not be received.
-         */
-        uint32_t slv_rx_seg_trans_clr_en:1;
-        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
-         *  In slave segmented transfer, if the size of the DMA TX buffer is smaller than the
-         *  size of the transmitted data,\\
-         *  1: the data in the following transactions will not be updated, i.e. the old data is
-         *  transmitted repeatedly.\\
-         *  0: the data in this transaction will not be updated. But in the following
-         *  transactions,\\
-         *
-         *  - if new data is filled in DMA TX FIFO, new data will be transmitted.
-         *  - if no new data is filled in DMA TX FIFO, no new data will be transmitted.
-         */
-        uint32_t slv_tx_seg_trans_clr_en:1;
-        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
-         *  1: In a DAM-controlled transfer, if the bit number of transferred data is equal to
-         *  (SPI_MS_DATA_BITLEN + 1), then GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW will be set by
-         *  hardware. 0: GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW is set by SPI_TRANS_DONE_INT event in
-         *  a single transfer, or by an SPI_DMA_SEG_TRANS_DONE_INT event in a segmented
-         *  transfer.
-         */
-        uint32_t rx_eof_en:1;
-        uint32_t reserved_22:5;
-        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
-         *  Configures whether or not to enable DMA-controlled receive data transfer.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t dma_rx_ena:1;
-        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable DMA-controlled send data transfer.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t dma_tx_ena:1;
-        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
-         *  Configures whether or not to reset spi_rx_afifo as shown in Figure <a
-         *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
-         *  href="fig:spi-slave-data-flow-control">link</a>.\\
-         *  0: Not reset\\
-         *  1: Reset\\
-         *  spi_rx_afifo is used to receive data in SPI master and slave transfer.
-         */
-        uint32_t rx_afifo_rst:1;
-        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
-         *  Configures whether or not to reset buf_tx_afifo as shown in Figure <a
-         *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
-         *  href="fig:spi-slave-data-flow-control">link</a>.\\
-         *  0: Not reset\\
-         *  1: Reset\\
-         *  buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer.
-         */
-        uint32_t buf_afifo_rst:1;
-        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
-         *  Configures whether or not to reset dma_tx_afifo as shown in Figure <a
-         *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
-         *  href="fig:spi-slave-data-flow-control">link</a>.\\
-         *  0: Not reset\\
-         *  1: Reset\\
-         *  dma_tx_afifo is used to send data out in DMA-controlled slave transfer.
-         */
-        uint32_t dma_afifo_rst:1;
-    };
-    uint32_t val;
-} spi_dma_conf_reg_t;
-
-/** Type of slave register
- *  SPI slave control register
- */
-typedef union {
-    struct {
-        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
-         *  Configures SPI clock mode.\\
-         *  0: SPI clock is off when CS becomes inactive.\\
-         *  1: SPI clock is delayed one cycle after CS becomes inactive.\\
-         *  2: SPI clock is delayed two cycles after CS becomes inactive.\\
-         *  3: SPI clock is always on.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t clk_mode:2;
-        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
-         *  Configure clock mode.\\
-         *  0: Support SPI clock mode 0 or 2. See Table <a
-         *  href="table:clock_pol_slave">link</a>.\\
-         *  1: Support SPI clock mode 1 or 3. See Table <a
-         *  href="table:clock_pol_slave">link</a>.\\
-         */
-        uint32_t clk_mode_13:1;
-        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
-         *  Configures the edge of output data.\\
-         *  0: Output data at TSCK rising edge.\\
-         *  1: Output data at RSCK rising edge.\\
-         */
-        uint32_t rsck_data_out:1;
-        uint32_t reserved_4:4;
-        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
-         *  of Rd_DMA transfer.\\
-         *  0: Not use\\
-         *  1: Use\\
-         */
-        uint32_t slv_rddma_bitlen_en:1;
-        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
-         *  of Wr_DMA transfer.\\
-         *  0: Not use\\
-         *  1: Use\\
-         */
-        uint32_t slv_wrdma_bitlen_en:1;
-        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
-         *  of Rd_BUF transfer.\\
-         *  0: Not use\\
-         *  1: Use\\
-         */
-        uint32_t slv_rdbuf_bitlen_en:1;
-        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
-         *  of Wr_BUF transfer.\\
-         *  0: Not use\\
-         *  1: Use\\
-         */
-        uint32_t slv_wrbuf_bitlen_en:1;
-        /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0;
-         *  Represents the effective bit of the last received data byte in SPI slave FD and HD
-         *  mode.
-         */
-        uint32_t slv_last_byte_strb:8;
-        uint32_t reserved_20:2;
-        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
-         *  Configures the magic value of BM table in DMA-controlled configurable segmented
-         *  transfer.
-         */
-        uint32_t dma_seg_magic_value:4;
-        /** slave_mode : R/W; bitpos: [26]; default: 0;
-         *  Configures SPI work mode.\\
-         *  0: Master\\
-         *  1: Slave\\
-         */
-        uint32_t slave_mode:1;
-        /** soft_reset : WT; bitpos: [27]; default: 0;
-         *  Configures whether to reset the SPI clock line, CS line, and data line via
-         *  software.\\
-         *  0: Not reset\\
-         *  1: Reset\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t soft_reset:1;
-        /** usr_conf : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable the CONF state of current DMA-controlled
-         *  configurable segmented transfer.\\
-         *  0: No effect, which means the current transfer is not a configurable segmented
-         *  transfer.\\
-         *  1: Enable, which means a configurable segmented transfer is started.\\
-         */
-        uint32_t usr_conf:1;
-        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
-         *  Configures whether or not to wait DMA TX data gets ready before starting SPI
-         *  transfer in master full-duplex transfer.\\
-         *  0: Not wait\\
-         *  1: Wait\\
-         */
-        uint32_t mst_fd_wait_dma_tx_data:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} spi_slave_reg_t;
-
-/** Type of slave1 register
- *  SPI slave control register 1
- */
-typedef union {
-    struct {
-        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
-         *  Configures the transferred data bit length in SPI slave full-/half-duplex modes.
-         */
-        uint32_t slv_data_bitlen:18;
-        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
-         *  Configures the command value in slave mode.
-         */
-        uint32_t slv_last_command:8;
-        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
-         *  Configures the address value in slave mode.
-         */
-        uint32_t slv_last_addr:6;
-    };
-    uint32_t val;
-} spi_slave1_reg_t;
-
-
-/** Group: Clock control registers */
-/** Type of clock register
- *  SPI clock control register
- */
-typedef union {
-    struct {
-        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
-         *  In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it
-         *  must be 0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_l:6;
-        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
-         *  Configures the duty cycle of SPI_CLK (high level) in master transfer.
-         *  It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1).
-         *  floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it
-         *  must be 0. \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t clkcnt_h:6;
-        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
-         *  Configures the divider of SPI_CLK in master transfer.
-         *  SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N +
-         *  1). \\
-         *  Can be configured in CONF state.
-         */
-        uint32_t clkcnt_n:6;
-        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
-         *  Configures the pre-divider of SPI_CLK in master transfer.
-         *  Can be configured in CONF state.
-         */
-        uint32_t clkdiv_pre:4;
-        uint32_t reserved_22:9;
-        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\
-         *  0: SPI_CLK is divided from APB_CLK.\\
-         *  1: SPI_CLK is eqaul to APB_CLK.\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t clk_equ_sysclk:1;
-    };
-    uint32_t val;
-} spi_clock_reg_t;
-
-/** Type of clk_gate register
- *  SPI module clock and register clock control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable clock gate.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t clk_en:1;
-        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to power on the SPI module clock.
-         */
-        uint32_t mst_clk_active:1;
-        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
-         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
-         *  0: XTAL CLK.
-         */
-        uint32_t mst_clk_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} spi_clk_gate_reg_t;
-
-
-/** Group: Timing registers */
-/** Type of din_mode register
- *  SPI input delay mode configuration
- */
-typedef union {
-    struct {
-        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  Configures the input mode for FSPID signal.\\
-         *  0: Input without delay\\
-         *  1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\
-         *  2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  rising edge cycle\\
-         *  3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  falling edge cycle\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t din0_mode:2;
-        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
-         *  Configures the input mode for FSPIQ signal.\\
-         *  0: Input without delay\\
-         *  1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\
-         *  2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  rising edge cycle\\
-         *  3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  falling edge cycle\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t din1_mode:2;
-        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
-         *  Configures the input mode for FSPIWP signal.\\
-         *  0: Input without delay\\
-         *  1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\
-         *  2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  rising edge cycle\\
-         *  3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  falling edge cycle\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t din2_mode:2;
-        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
-         *  Configures the input mode for FSPIHD signal.\\
-         *  0: Input without delay\\
-         *  1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\
-         *  2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  rising edge cycle\\
-         *  3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  falling edge cycle\\
-         *  Can be configured in CONF state.
-         *
-         */
-        uint32_t din3_mode:2;
-        /** din4_mode : HRO; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din4_mode:2;
-        /** din5_mode : HRO; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din5_mode:2;
-        /** din6_mode : HRO; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din6_mode:2;
-        /** din7_mode : HRO; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din7_mode:2;
-        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing
-         *  module.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t timing_hclk_active:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} spi_din_mode_reg_t;
-
-/** Type of din_num register
- *  SPI input delay number configuration
- */
-typedef union {
-    struct {
-        /** din0_num : R/W; bitpos: [1:0]; default: 0;
-         *  Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\
-         *  0: Delayed by 1 clock cycle\\
-         *  1: Delayed by 2 clock cycles\\
-         *  2: Delayed by 3 clock cycles\\
-         *  3: Delayed by 4 clock cycles\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t din0_num:2;
-        /** din1_num : R/W; bitpos: [3:2]; default: 0;
-         *  Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\
-         *  0: Delayed by 1 clock cycle\\
-         *  1: Delayed by 2 clock cycles\\
-         *  2: Delayed by 3 clock cycles\\
-         *  3: Delayed by 4 clock cycles\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t din1_num:2;
-        /** din2_num : R/W; bitpos: [5:4]; default: 0;
-         *  Configures the delays to input signal FSPIWP based on the setting of
-         *  SPI_DIN2_MODE.\\
-         *  0: Delayed by 1 clock cycle\\
-         *  1: Delayed by 2 clock cycles\\
-         *  2: Delayed by 3 clock cycles\\
-         *  3: Delayed by 4 clock cycles\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t din2_num:2;
-        /** din3_num : R/W; bitpos: [7:6]; default: 0;
-         *  Configures the delays to input signal FSPIHD based on the setting of
-         *  SPI_DIN3_MODE.\\
-         *  0: Delayed by 1 clock cycle\\
-         *  1: Delayed by 2 clock cycles\\
-         *  2: Delayed by 3 clock cycles\\
-         *  3: Delayed by 4 clock cycles\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t din3_num:2;
-        /** din4_num : HRO; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din4_num:2;
-        /** din5_num : HRO; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din5_num:2;
-        /** din6_num : HRO; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din6_num:2;
-        /** din7_num : HRO; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din7_num:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} spi_din_num_reg_t;
-
-/** Type of dout_mode register
- *  SPI output delay mode configuration
- */
-typedef union {
-    struct {
-        /** dout0_mode : R/W; bitpos: [0]; default: 0;
-         *  Configures the output mode for FSPID signal.\\
-         *  0: Output without delay\\
-         *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t dout0_mode:1;
-        /** dout1_mode : R/W; bitpos: [1]; default: 0;
-         *  Configures the output mode for FSPIQ signal.\\
-         *  0: Output without delay\\
-         *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t dout1_mode:1;
-        /** dout2_mode : R/W; bitpos: [2]; default: 0;
-         *  Configures the output mode for FSPIWP signal.\\
-         *  0: Output without delay\\
-         *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t dout2_mode:1;
-        /** dout3_mode : R/W; bitpos: [3]; default: 0;
-         *  Configures the output mode for FSPIHD signal.\\
-         *  0: Output without delay\\
-         *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
-         *  Can be configured in CONF state.
-         */
-        uint32_t dout3_mode:1;
-        /** dout4_mode : HRO; bitpos: [4]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout4_mode:1;
-        /** dout5_mode : HRO; bitpos: [5]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout5_mode:1;
-        /** dout6_mode : HRO; bitpos: [6]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout6_mode:1;
-        /** dout7_mode : HRO; bitpos: [7]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout7_mode:1;
-        /** d_dqs_mode : HRO; bitpos: [8]; default: 0;
-         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
-         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t d_dqs_mode:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} spi_dout_mode_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of dma_int_ena register
- *  SPI interrupt enable register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable SPI_SLV_EX_QPI_INT interrupt.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to enable SPI_SLV_EN_QPI_INT interrupt.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to enable SPI_SLV_CMD7_INT interrupt.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to enable SPI_SLV_CMD8_INT interrupt.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : R/W; bitpos: [6]; default: 0;
-         *  Write 1 to enable SPI_SLV_CMD9_INT interrupt.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : R/W; bitpos: [7]; default: 0;
-         *  Write 1 to enable SPI_SLV_CMDA_INT interrupt.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to enable SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to enable SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : R/W; bitpos: [10]; default: 0;
-         *  Write 1 to enable SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : R/W; bitpos: [11]; default: 0;
-         *  Write 1 to enable SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : R/W; bitpos: [12]; default: 0;
-         *  Write 1 to enable SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : R/W; bitpos: [13]; default: 0;
-         *  Write 1 to enable SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : R/W; bitpos: [14]; default: 0;
-         *  Write 1 to enable SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : R/W; bitpos: [15]; default: 0;
-         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : R/W; bitpos: [16]; default: 0;
-         *  Write 1 to enable SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : R/W; bitpos: [17]; default: 0;
-         *  Write 1 to enable SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : R/W; bitpos: [18]; default: 0;
-         *  Write 1 to enable SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : R/W; bitpos: [19]; default: 0;
-         *  Write 1 to enable SPI_APP2_INT interrupt.
-         */
-        uint32_t app2:1;
-        /** app1 : R/W; bitpos: [20]; default: 0;
-         *  Write 1 to enable SPI_APP1_INT interrupt.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_ena_reg_t;
-
-/** Type of dma_int_clr register
- *  SPI interrupt clear register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear SPI_SLV_EX_QPI_INT interrupt.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear SPI_SLV_EN_QPI_INT interrupt.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear SPI_SLV_CMD7_INT interrupt.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear SPI_SLV_CMD8_INT interrupt.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear SPI_SLV_CMD9_INT interrupt.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : WT; bitpos: [7]; default: 0;
-         *  Write 1 to clear SPI_SLV_CMDA_INT interrupt.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : WT; bitpos: [8]; default: 0;
-         *  Write 1 to clear SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : WT; bitpos: [9]; default: 0;
-         *  Write 1 to clear SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : WT; bitpos: [10]; default: 0;
-         *  Write 1 to clear SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : WT; bitpos: [11]; default: 0;
-         *  Write 1 to clear SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : WT; bitpos: [12]; default: 0;
-         *  Write 1 to clear SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : WT; bitpos: [13]; default: 0;
-         *  Write 1 to clear SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : WT; bitpos: [14]; default: 0;
-         *  Write 1 to clear SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : WT; bitpos: [15]; default: 0;
-         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : WT; bitpos: [16]; default: 0;
-         *  Write 1 to clear SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0;
-         *  Write 1 to clear SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0;
-         *  Write 1 to clear SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : WT; bitpos: [19]; default: 0;
-         *  Write 1 to clear SPI_APP2_INT interrupt.
-         */
-        uint32_t app2:1;
-        /** app1 : WT; bitpos: [20]; default: 0;
-         *  Write 1 to clear SPI_APP1_INT interrupt.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_clr_reg_t;
-
-/** Type of dma_int_raw register
- *  SPI interrupt raw register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status of SPI_SLV_EX_QPI_INT interrupt.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status of SPI_SLV_EN_QPI_INT interrupt.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt status of SPI_SLV_CMD7_INT interrupt.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt status of SPI_SLV_CMD8_INT interrupt.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt status of SPI_SLV_CMD9_INT interrupt.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt status of SPI_SLV_CMDA_INT interrupt.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw interrupt status of SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
-         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
-         *  bigger than 63. 0: Others.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw interrupt status of SPI_APP2_INT interrupt. The value is only controlled by
-         *  the application.
-         */
-        uint32_t app2:1;
-        /** app1 : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw interrupt status of SPI_APP1_INT interrupt. The value is only controlled by
-         *  the application.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_raw_reg_t;
-
-/** Type of dma_int_st register
- *  SPI interrupt status register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : RO; bitpos: [0]; default: 0;
-         *  The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : RO; bitpos: [1]; default: 0;
-         *  The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : RO; bitpos: [2]; default: 0;
-         *  The interrupt status of SPI_SLV_EX_QPI_INT interrupt.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : RO; bitpos: [3]; default: 0;
-         *  The interrupt status of SPI_SLV_EN_QPI_INT interrupt.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : RO; bitpos: [4]; default: 0;
-         *  The interrupt status of SPI_SLV_CMD7_INT interrupt.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : RO; bitpos: [5]; default: 0;
-         *  The interrupt status of SPI_SLV_CMD8_INT interrupt.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : RO; bitpos: [6]; default: 0;
-         *  The interrupt status of SPI_SLV_CMD9_INT interrupt.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : RO; bitpos: [7]; default: 0;
-         *  The interrupt status of SPI_SLV_CMDA_INT interrupt.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : RO; bitpos: [8]; default: 0;
-         *  The interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : RO; bitpos: [9]; default: 0;
-         *  The interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : RO; bitpos: [10]; default: 0;
-         *  The interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : RO; bitpos: [11]; default: 0;
-         *  The interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : RO; bitpos: [12]; default: 0;
-         *  The interrupt status of SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : RO; bitpos: [13]; default: 0;
-         *  The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : RO; bitpos: [14]; default: 0;
-         *  The interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : RO; bitpos: [15]; default: 0;
-         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : RO; bitpos: [16]; default: 0;
-         *  The interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : RO; bitpos: [17]; default: 0;
-         *  The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : RO; bitpos: [18]; default: 0;
-         *  The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : RO; bitpos: [19]; default: 0;
-         *  The interrupt status of SPI_APP2_INT interrupt.
-         */
-        uint32_t app2:1;
-        /** app1 : RO; bitpos: [20]; default: 0;
-         *  The interrupt status of SPI_APP1_INT interrupt.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_st_reg_t;
-
-/** Type of dma_int_set register
- *  SPI interrupt software set register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err : WT; bitpos: [0]; default: 0;
-         *  Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err:1;
-        /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0;
-         *  Write 1 to set SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err:1;
-        /** slv_ex_qpi : WT; bitpos: [2]; default: 0;
-         *  Write 1 to set SPI_SLV_EX_QPI_INT interrupt.
-         */
-        uint32_t slv_ex_qpi:1;
-        /** slv_en_qpi : WT; bitpos: [3]; default: 0;
-         *  Write 1 to set SPI_SLV_EN_QPI_INT interrupt.
-         */
-        uint32_t slv_en_qpi:1;
-        /** slv_cmd7 : WT; bitpos: [4]; default: 0;
-         *  Write 1 to set SPI_SLV_CMD7_INT interrupt.
-         */
-        uint32_t slv_cmd7:1;
-        /** slv_cmd8 : WT; bitpos: [5]; default: 0;
-         *  Write 1 to set SPI_SLV_CMD8_INT interrupt.
-         */
-        uint32_t slv_cmd8:1;
-        /** slv_cmd9 : WT; bitpos: [6]; default: 0;
-         *  Write 1 to set SPI_SLV_CMD9_INT interrupt.
-         */
-        uint32_t slv_cmd9:1;
-        /** slv_cmda : WT; bitpos: [7]; default: 0;
-         *  Write 1 to set SPI_SLV_CMDA_INT interrupt.
-         */
-        uint32_t slv_cmda:1;
-        /** slv_rd_dma_done : WT; bitpos: [8]; default: 0;
-         *  Write 1 to set SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done:1;
-        /** slv_wr_dma_done : WT; bitpos: [9]; default: 0;
-         *  Write 1 to set SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done:1;
-        /** slv_rd_buf_done : WT; bitpos: [10]; default: 0;
-         *  Write 1 to set SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done:1;
-        /** slv_wr_buf_done : WT; bitpos: [11]; default: 0;
-         *  Write 1 to set SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done:1;
-        /** trans_done : WT; bitpos: [12]; default: 0;
-         *  Write 1 to set SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done:1;
-        /** dma_seg_trans_done : WT; bitpos: [13]; default: 0;
-         *  Write 1 to set SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done:1;
-        /** seg_magic_err : WT; bitpos: [14]; default: 0;
-         *  Write 1 to set SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err:1;
-        /** slv_buf_addr_err : WT; bitpos: [15]; default: 0;
-         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err:1;
-        /** slv_cmd_err : WT; bitpos: [16]; default: 0;
-         *  Write 1 to set SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err:1;
-        /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0;
-         *  Write 1 to set SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err:1;
-        /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0;
-         *  Write 1 to set SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err:1;
-        /** app2 : WT; bitpos: [19]; default: 0;
-         *  Write 1 to set SPI_APP2_INT interrupt.
-         */
-        uint32_t app2:1;
-        /** app1 : WT; bitpos: [20]; default: 0;
-         *  Write 1 to set SPI_APP1_INT interrupt.
-         */
-        uint32_t app1:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_set_reg_t;
-
-
-/** Group: CPU-controlled data buffer */
-/** Type of wn register
- *  SPI CPU-controlled buffer n
- */
-typedef union {
-    struct {
-        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf:32;
-    };
-    uint32_t val;
-} spi_wn_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36716931;
-         *  Version control register.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} spi_date_reg_t;
-
-
-typedef struct {
-    volatile spi_cmd_reg_t cmd;
-    volatile spi_addr_reg_t addr;
-    volatile spi_ctrl_reg_t ctrl;
-    volatile spi_clock_reg_t clock;
-    volatile spi_user_reg_t user;
-    volatile spi_user1_reg_t user1;
-    volatile spi_user2_reg_t user2;
-    volatile spi_ms_dlen_reg_t ms_dlen;
-    volatile spi_misc_reg_t misc;
-    volatile spi_din_mode_reg_t din_mode;
-    volatile spi_din_num_reg_t din_num;
-    volatile spi_dout_mode_reg_t dout_mode;
-    volatile spi_dma_conf_reg_t dma_conf;
-    volatile spi_dma_int_ena_reg_t dma_int_ena;
-    volatile spi_dma_int_clr_reg_t dma_int_clr;
-    volatile spi_dma_int_raw_reg_t dma_int_raw;
-    volatile spi_dma_int_st_reg_t dma_int_st;
-    volatile spi_dma_int_set_reg_t dma_int_set;
-    uint32_t reserved_048[20];
-    volatile spi_wn_reg_t data_buf[16];
-    uint32_t reserved_0d8[2];
-    volatile spi_slave_reg_t slave;
-    volatile spi_slave1_reg_t slave1;
-    volatile spi_clk_gate_reg_t clk_gate;
-    uint32_t reserved_0ec;
-    volatile spi_date_reg_t date;
-} spi_dev_t;
-
-extern spi_dev_t GPSPI2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/system_reg.h b/components/soc/esp32c61/include/soc/system_reg.h
index 4577fecbeb7..690bb496eb8 100644
--- a/components/soc/esp32c61/include/soc/system_reg.h
+++ b/components/soc/esp32c61/include/soc/system_reg.h
@@ -6,6 +6,6 @@
 
 #include "soc/hp_system_reg.h"
 
-#include "intpri_reg.h"
+#include "soc/intpri_reg.h"
 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
 #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0
diff --git a/components/soc/esp32c61/include/soc/trace_reg.h b/components/soc/esp32c61/include/soc/trace_reg.h
deleted file mode 100644
index 1abfbbcd045..00000000000
--- a/components/soc/esp32c61/include/soc/trace_reg.h
+++ /dev/null
@@ -1,464 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TRACE_MEM_START_ADDR_REG register
- *  Memory start address
- */
-#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
-/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Configures the start address of the trace memory
- */
-#define TRACE_MEM_START_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_START_ADDR_M  (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S)
-#define TRACE_MEM_START_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_START_ADDR_S  0
-
-/** TRACE_MEM_END_ADDR_REG register
- *  Memory end address
- */
-#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
-/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  Configures the end address of the trace memory.
- */
-#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
-#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_END_ADDR_S  0
-
-/** TRACE_MEM_CURRENT_ADDR_REG register
- *  Memory current addr
- */
-#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
-/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Represents the current memory address for writing.
- */
-#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
-#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_CURRENT_ADDR_S  0
-
-/** TRACE_MEM_ADDR_UPDATE_REG register
- *  Memory address update
- */
-#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
-/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
- *  Configures whether to update the value of
- *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
- *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\
- *  0: Not update\\
- *  1: Update\\
- */
-#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
-
-/** TRACE_FIFO_STATUS_REG register
- *  FIFO status register
- */
-#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
-/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  Represent whether the FIFO is empty. \\1: Empty \\0: Not empty
- */
-#define TRACE_FIFO_EMPTY    (BIT(0))
-#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
-#define TRACE_FIFO_EMPTY_V  0x00000001U
-#define TRACE_FIFO_EMPTY_S  0
-/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
- *  Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
- *  state becasue hart is halted or in reset \\3: Lost state\\
- */
-#define TRACE_WORK_STATUS    0x00000003U
-#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
-#define TRACE_WORK_STATUS_V  0x00000003U
-#define TRACE_WORK_STATUS_S  1
-
-/** TRACE_INTR_ENA_REG register
- *  Interrupt enable register
- */
-#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
-/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable TRACE_FIFO_OVERFLOW_INTR
- */
-#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
-/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable TRACE_MEM_FULL_INTR
- */
-#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
-#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
-#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_ENA_S  1
-
-/** TRACE_INTR_RAW_REG register
- *  Interrupt raw status register
- */
-#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
-/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR.
- */
-#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
-/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status of TRACE_MEM_FULL_INTR
- */
-#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
-#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
-#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_RAW_S  1
-
-/** TRACE_INTR_CLR_REG register
- *  Interrupt clear register
- */
-#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
-/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear TRACE_FIFO_OVERFLOW_INTR
- */
-#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
-/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear TRACE_MEM_FULL_INTR
- */
-#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
-#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
-#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_CLR_S  1
-
-/** TRACE_TRIGGER_REG register
- *  Trace enable register
- */
-#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
-/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
- *  Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\
- */
-#define TRACE_TRIGGER_ON    (BIT(0))
-#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
-#define TRACE_TRIGGER_ON_V  0x00000001U
-#define TRACE_TRIGGER_ON_S  0
-/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
- *  Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\
- */
-#define TRACE_TRIGGER_OFF    (BIT(1))
-#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
-#define TRACE_TRIGGER_OFF_V  0x00000001U
-#define TRACE_TRIGGER_OFF_S  1
-/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
- *  Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\
- */
-#define TRACE_MEM_LOOP    (BIT(2))
-#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
-#define TRACE_MEM_LOOP_V  0x00000001U
-#define TRACE_MEM_LOOP_S  2
-/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
- *  Configure whether or not enable automatic restart function for the encoder.\\0:
- *  Disable\\1: Enable\\
- */
-#define TRACE_RESTART_ENA    (BIT(3))
-#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
-#define TRACE_RESTART_ENA_V  0x00000001U
-#define TRACE_RESTART_ENA_S  3
-
-/** TRACE_CONFIG_REG register
- *  trace configuration register
- */
-#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24)
-/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
- *  Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\
- */
-#define TRACE_DM_TRIGGER_ENA    (BIT(0))
-#define TRACE_DM_TRIGGER_ENA_M  (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
-#define TRACE_DM_TRIGGER_ENA_V  0x00000001U
-#define TRACE_DM_TRIGGER_ENA_S  0
-/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
- *  Configure whether to reset, when enabeld, if cpu have reset, the encoder will
- *  output a packet to report the address of the last instruction, and upon reset
- *  deassertion, the encoder start again.\\0: Disable\\0: Enable\\
- */
-#define TRACE_RESET_ENA    (BIT(1))
-#define TRACE_RESET_ENA_M  (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
-#define TRACE_RESET_ENA_V  0x00000001U
-#define TRACE_RESET_ENA_S  1
-/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
- *  Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\
- */
-#define TRACE_HALT_ENA    (BIT(2))
-#define TRACE_HALT_ENA_M  (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
-#define TRACE_HALT_ENA_V  0x00000001U
-#define TRACE_HALT_ENA_S  2
-/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
- *  Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\
- */
-#define TRACE_STALL_ENA    (BIT(3))
-#define TRACE_STALL_ENA_M  (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
-#define TRACE_STALL_ENA_V  0x00000001U
-#define TRACE_STALL_ENA_S  3
-/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
- *  Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\
- */
-#define TRACE_FULL_ADDRESS    (BIT(4))
-#define TRACE_FULL_ADDRESS_M  (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
-#define TRACE_FULL_ADDRESS_V  0x00000001U
-#define TRACE_FULL_ADDRESS_S  4
-/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
- *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
- *  exception address, only exception cause in exception packets.\\1: enabled\\0:
- *  disabled\\
- */
-#define TRACE_IMPLICIT_EXCEPT    (BIT(5))
-#define TRACE_IMPLICIT_EXCEPT_M  (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
-#define TRACE_IMPLICIT_EXCEPT_V  0x00000001U
-#define TRACE_IMPLICIT_EXCEPT_S  5
-
-/** TRACE_FILTER_CONTROL_REG register
- *  filter control register
- */
-#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28)
-/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
- *  Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable
- */
-#define TRACE_FILTER_EN    (BIT(0))
-#define TRACE_FILTER_EN_M  (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
-#define TRACE_FILTER_EN_V  0x00000001U
-#define TRACE_FILTER_EN_S  0
-/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
- *  Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable,
- *  the comparator must be high in order for the filter to match
- */
-#define TRACE_MATCH_COMP    (BIT(1))
-#define TRACE_MATCH_COMP_M  (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
-#define TRACE_MATCH_COMP_V  0x00000001U
-#define TRACE_MATCH_COMP_S  1
-/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
- *  Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable,
- *  match privilege levels specified by
- *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
- */
-#define TRACE_MATCH_PRIVILEGE    (BIT(2))
-#define TRACE_MATCH_PRIVILEGE_M  (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S)
-#define TRACE_MATCH_PRIVILEGE_V  0x00000001U
-#define TRACE_MATCH_PRIVILEGE_S  2
-/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
- *  Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start
- *  matching from exception cause codes specified by
- *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
- *  matching upon return from the 1st matching exception.
- */
-#define TRACE_MATCH_ECAUSE    (BIT(3))
-#define TRACE_MATCH_ECAUSE_M  (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S)
-#define TRACE_MATCH_ECAUSE_V  0x00000001U
-#define TRACE_MATCH_ECAUSE_S  3
-/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
- *  Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable,
- *  start matching from a trap with the interrupt level codes specified by
- *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
- *  stop matching upon return from the 1st matching trap.
- */
-#define TRACE_MATCH_INTERRUPT    (BIT(4))
-#define TRACE_MATCH_INTERRUPT_M  (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S)
-#define TRACE_MATCH_INTERRUPT_V  0x00000001U
-#define TRACE_MATCH_INTERRUPT_S  4
-
-/** TRACE_FILTER_MATCH_CONTROL_REG register
- *  filter match control register
- */
-#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c)
-/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
- *  Configures the privilege level for matching. Valid only when
- *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User
- *  mode. \\1: Machine mode
- */
-#define TRACE_MATCH_CHOICE_PRIVILEGE    (BIT(0))
-#define TRACE_MATCH_CHOICE_PRIVILEGE_M  (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
-#define TRACE_MATCH_CHOICE_PRIVILEGE_V  0x00000001U
-#define TRACE_MATCH_CHOICE_PRIVILEGE_S  0
-/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
- *  Configures the interrupt level for match. Valid only when when
- *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0:
- *  itype=2. \\0: itype=2.
- */
-#define TRACE_MATCH_VALUE_INTERRUPT    (BIT(1))
-#define TRACE_MATCH_VALUE_INTERRUPT_M  (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
-#define TRACE_MATCH_VALUE_INTERRUPT_V  0x00000001U
-#define TRACE_MATCH_VALUE_INTERRUPT_S  1
-/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0;
- *  Configures the ecause code for matching.
- */
-#define TRACE_MATCH_CHOICE_ECAUSE    0x0000003FU
-#define TRACE_MATCH_CHOICE_ECAUSE_M  (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S)
-#define TRACE_MATCH_CHOICE_ECAUSE_V  0x0000003FU
-#define TRACE_MATCH_CHOICE_ECAUSE_S  2
-
-/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
- *  filter comparator match control register
- */
-#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30)
-/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
- *  Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\
- */
-#define TRACE_P_INPUT    (BIT(0))
-#define TRACE_P_INPUT_M  (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
-#define TRACE_P_INPUT_V  0x00000001U
-#define TRACE_P_INPUT_S  0
-/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
- *  Configures the function for the primary comparator. \\0: Equal, \\1: Not equal,
- *  \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
- *  equal, \\Other: Always match
- */
-#define TRACE_P_FUNCTION    0x00000007U
-#define TRACE_P_FUNCTION_M  (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
-#define TRACE_P_FUNCTION_V  0x00000007U
-#define TRACE_P_FUNCTION_S  2
-/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
- *  Configure whether to explicitly report an instruction address matched against the
- *  primary comparator. \\0:Not report \\1:Report
- */
-#define TRACE_P_NOTIFY    (BIT(5))
-#define TRACE_P_NOTIFY_M  (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
-#define TRACE_P_NOTIFY_V  0x00000001U
-#define TRACE_P_NOTIFY_S  5
-/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
- *  Configures the input of the secondary comparator for matching: \\0: iaddr \\1:
- *  tval\\
- */
-#define TRACE_S_INPUT    (BIT(8))
-#define TRACE_S_INPUT_M  (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
-#define TRACE_S_INPUT_V  0x00000001U
-#define TRACE_S_INPUT_S  8
-/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
- *  Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal,
- *  \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
- *  equal, \\Other: Always match
- */
-#define TRACE_S_FUNCTION    0x00000007U
-#define TRACE_S_FUNCTION_M  (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
-#define TRACE_S_FUNCTION_V  0x00000007U
-#define TRACE_S_FUNCTION_S  10
-/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0;
- *  Generate a trace packet explicitly reporting the address that cause the secondary
- *  match
- */
-#define TRACE_S_NOTIFY    (BIT(13))
-#define TRACE_S_NOTIFY_M  (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S)
-#define TRACE_S_NOTIFY_V  0x00000001U
-#define TRACE_S_NOTIFY_S  13
-/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
- *  Configures the comparator match mode: \\0: Only the primary comparator matches \\1:
- *  Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or
- *  secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary
- *  comparator matches and stop filtering when the secondary comparator matches\\
- */
-#define TRACE_MATCH_MODE    0x00000003U
-#define TRACE_MATCH_MODE_M  (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
-#define TRACE_MATCH_MODE_V  0x00000003U
-#define TRACE_MATCH_MODE_S  16
-
-/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
- *  primary comparator match value
- */
-#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34)
-/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
- *  Configures the match value for the primary comparator
- */
-#define TRACE_P_MATCH    0xFFFFFFFFU
-#define TRACE_P_MATCH_M  (TRACE_P_MATCH_V << TRACE_P_MATCH_S)
-#define TRACE_P_MATCH_V  0xFFFFFFFFU
-#define TRACE_P_MATCH_S  0
-
-/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
- *  secondary comparator match value
- */
-#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38)
-/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
- *  Configures the match value for the secondary comparator
- */
-#define TRACE_S_MATCH    0xFFFFFFFFU
-#define TRACE_S_MATCH_M  (TRACE_S_MATCH_V << TRACE_S_MATCH_S)
-#define TRACE_S_MATCH_V  0xFFFFFFFFU
-#define TRACE_S_MATCH_S  0
-
-/** TRACE_RESYNC_PROLONGED_REG register
- *  Resync configuration register
- */
-#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c)
-/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
- *  Configures the threshold for synchronization counter
- */
-#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
-#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
-#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
-#define TRACE_RESYNC_PROLONGED_S  0
-/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
- *  Configures the synchronization mode: \\0: Disable the synchronization counter \\1:
- *  Invalid \\2: Synchronization counter counts by packet  \\3: Synchronization counter
- *  counts by cycle\\
- */
-#define TRACE_RESYNC_MODE    0x00000003U
-#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
-#define TRACE_RESYNC_MODE_V  0x00000003U
-#define TRACE_RESYNC_MODE_S  24
-
-/** TRACE_AHB_CONFIG_REG register
- *  AHB config register
- */
-#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40)
-/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
- *  Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4
- *  \\4:INCR8 \\Others:Invalid
- */
-#define TRACE_HBURST    0x00000007U
-#define TRACE_HBURST_M  (TRACE_HBURST_V << TRACE_HBURST_S)
-#define TRACE_HBURST_V  0x00000007U
-#define TRACE_HBURST_S  0
-/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0;
- *  Configures the maximum burst length for INCR mode
- */
-#define TRACE_MAX_INCR    0x00000007U
-#define TRACE_MAX_INCR_M  (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S)
-#define TRACE_MAX_INCR_V  0x00000007U
-#define TRACE_MAX_INCR_S  3
-
-/** TRACE_CLOCK_GATE_REG register
- *  Clock gate control register
- */
-#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44)
-/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Configures register clock gating. \\0: Support clock only when the application
- *  writes registers to save power. \\1:Always force the clock on for registers \\ This
- *  bit does't affect register access.
- */
-#define TRACE_CLK_EN    (BIT(0))
-#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
-#define TRACE_CLK_EN_V  0x00000001U
-#define TRACE_CLK_EN_S  0
-
-/** TRACE_DATE_REG register
- *  Version control register
- */
-#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
-/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
- *  Version control register.
- */
-#define TRACE_DATE    0x0FFFFFFFU
-#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
-#define TRACE_DATE_V  0x0FFFFFFFU
-#define TRACE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/trace_struct.h b/components/soc/esp32c61/include/soc/trace_struct.h
deleted file mode 100644
index a8337ed0fdb..00000000000
--- a/components/soc/esp32c61/include/soc/trace_struct.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Memory configuration registers */
-/** Type of mem_start_addr register
- *  Memory start address
- */
-typedef union {
-    struct {
-        /** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the start address of the trace memory
-         */
-        uint32_t mem_start_addr:32;
-    };
-    uint32_t val;
-} trace_mem_start_addr_reg_t;
-
-/** Type of mem_end_addr register
- *  Memory end address
- */
-typedef union {
-    struct {
-        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Configures the end address of the trace memory.
-         */
-        uint32_t mem_end_addr:32;
-    };
-    uint32_t val;
-} trace_mem_end_addr_reg_t;
-
-/** Type of mem_current_addr register
- *  Memory current addr
- */
-typedef union {
-    struct {
-        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
-         *  Represents the current memory address for writing.
-         */
-        uint32_t mem_current_addr:32;
-    };
-    uint32_t val;
-} trace_mem_current_addr_reg_t;
-
-/** Type of mem_addr_update register
- *  Memory address update
- */
-typedef union {
-    struct {
-        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
-         *  Configures whether to update the value of
-         *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
-         *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\
-         *  0: Not update\\
-         *  1: Update\\
-         */
-        uint32_t mem_current_addr_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} trace_mem_addr_update_reg_t;
-
-
-/** Group: Trace fifo status register */
-/** Type of fifo_status register
- *  FIFO status register
- */
-typedef union {
-    struct {
-        /** fifo_empty : RO; bitpos: [0]; default: 1;
-         *  Represent whether the FIFO is empty. \\1: Empty \\0: Not empty
-         */
-        uint32_t fifo_empty:1;
-        /** work_status : RO; bitpos: [2:1]; default: 0;
-         *  Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
-         *  state becasue hart is halted or in reset \\3: Lost state\\
-         */
-        uint32_t work_status:2;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} trace_fifo_status_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of intr_ena register
- *  Interrupt enable register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable TRACE_FIFO_OVERFLOW_INTR
-         */
-        uint32_t fifo_overflow_intr_ena:1;
-        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable TRACE_MEM_FULL_INTR
-         */
-        uint32_t mem_full_intr_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_ena_reg_t;
-
-/** Type of intr_raw register
- *  Interrupt raw status register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
-         *  The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR.
-         */
-        uint32_t fifo_overflow_intr_raw:1;
-        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
-         *  The raw interrupt status of TRACE_MEM_FULL_INTR
-         */
-        uint32_t mem_full_intr_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_raw_reg_t;
-
-/** Type of intr_clr register
- *  Interrupt clear register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear TRACE_FIFO_OVERFLOW_INTR
-         */
-        uint32_t fifo_overflow_intr_clr:1;
-        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear TRACE_MEM_FULL_INTR
-         */
-        uint32_t mem_full_intr_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_clr_reg_t;
-
-
-/** Group: Trace configuration register */
-/** Type of trigger register
- *  Trace enable register
- */
-typedef union {
-    struct {
-        /** trigger_on : WT; bitpos: [0]; default: 0;
-         *  Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\
-         */
-        uint32_t trigger_on:1;
-        /** trigger_off : WT; bitpos: [1]; default: 0;
-         *  Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\
-         */
-        uint32_t trigger_off:1;
-        /** mem_loop : R/W; bitpos: [2]; default: 1;
-         *  Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\
-         */
-        uint32_t mem_loop:1;
-        /** restart_ena : R/W; bitpos: [3]; default: 1;
-         *  Configure whether or not enable automatic restart function for the encoder.\\0:
-         *  Disable\\1: Enable\\
-         */
-        uint32_t restart_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} trace_trigger_reg_t;
-
-/** Type of config register
- *  trace configuration register
- */
-typedef union {
-    struct {
-        /** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
-         *  Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\
-         */
-        uint32_t dm_trigger_ena:1;
-        /** reset_ena : R/W; bitpos: [1]; default: 0;
-         *  Configure whether to reset, when enabeld, if cpu have reset, the encoder will
-         *  output a packet to report the address of the last instruction, and upon reset
-         *  deassertion, the encoder start again.\\0: Disable\\0: Enable\\
-         */
-        uint32_t reset_ena:1;
-        /** halt_ena : R/W; bitpos: [2]; default: 0;
-         *  Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\
-         */
-        uint32_t halt_ena:1;
-        /** stall_ena : R/W; bitpos: [3]; default: 0;
-         *  Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\
-         */
-        uint32_t stall_ena:1;
-        /** full_address : R/W; bitpos: [4]; default: 0;
-         *  Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\
-         */
-        uint32_t full_address:1;
-        /** implicit_except : R/W; bitpos: [5]; default: 0;
-         *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
-         *  exception address, only exception cause in exception packets.\\1: enabled\\0:
-         *  disabled\\
-         */
-        uint32_t implicit_except:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} trace_config_reg_t;
-
-/** Type of filter_control register
- *  filter control register
- */
-typedef union {
-    struct {
-        /** filter_en : R/W; bitpos: [0]; default: 0;
-         *  Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable
-         */
-        uint32_t filter_en:1;
-        /** match_comp : R/W; bitpos: [1]; default: 0;
-         *  Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable,
-         *  the comparator must be high in order for the filter to match
-         */
-        uint32_t match_comp:1;
-        /** match_privilege : R/W; bitpos: [2]; default: 0;
-         *  Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable,
-         *  match privilege levels specified by
-         *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
-         */
-        uint32_t match_privilege:1;
-        /** match_ecause : R/W; bitpos: [3]; default: 0;
-         *  Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start
-         *  matching from exception cause codes specified by
-         *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
-         *  matching upon return from the 1st matching exception.
-         */
-        uint32_t match_ecause:1;
-        /** match_interrupt : R/W; bitpos: [4]; default: 0;
-         *  Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable,
-         *  start matching from a trap with the interrupt level codes specified by
-         *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
-         *  stop matching upon return from the 1st matching trap.
-         */
-        uint32_t match_interrupt:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} trace_filter_control_reg_t;
-
-/** Type of filter_match_control register
- *  filter match control register
- */
-typedef union {
-    struct {
-        /** match_choice_privilege : R/W; bitpos: [0]; default: 0;
-         *  Configures the privilege level for matching. Valid only when
-         *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User
-         *  mode. \\1: Machine mode
-         */
-        uint32_t match_choice_privilege:1;
-        /** match_value_interrupt : R/W; bitpos: [1]; default: 0;
-         *  Configures the interrupt level for match. Valid only when when
-         *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0:
-         *  itype=2. \\0: itype=2.
-         */
-        uint32_t match_value_interrupt:1;
-        /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
-         *  Configures the ecause code for matching.
-         */
-        uint32_t match_choice_ecause:6;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} trace_filter_match_control_reg_t;
-
-/** Type of filter_comparator_control register
- *  filter comparator match control register
- */
-typedef union {
-    struct {
-        /** p_input : R/W; bitpos: [0]; default: 0;
-         *  Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\
-         */
-        uint32_t p_input:1;
-        uint32_t reserved_1:1;
-        /** p_function : R/W; bitpos: [4:2]; default: 0;
-         *  Configures the function for the primary comparator. \\0: Equal, \\1: Not equal,
-         *  \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
-         *  equal, \\Other: Always match
-         */
-        uint32_t p_function:3;
-        /** p_notify : R/W; bitpos: [5]; default: 0;
-         *  Configure whether to explicitly report an instruction address matched against the
-         *  primary comparator. \\0:Not report \\1:Report
-         */
-        uint32_t p_notify:1;
-        uint32_t reserved_6:2;
-        /** s_input : R/W; bitpos: [8]; default: 0;
-         *  Configures the input of the secondary comparator for matching: \\0: iaddr \\1:
-         *  tval\\
-         */
-        uint32_t s_input:1;
-        uint32_t reserved_9:1;
-        /** s_function : R/W; bitpos: [12:10]; default: 0;
-         *  Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal,
-         *  \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
-         *  equal, \\Other: Always match
-         */
-        uint32_t s_function:3;
-        /** s_notify : R/W; bitpos: [13]; default: 0;
-         *  Generate a trace packet explicitly reporting the address that cause the secondary
-         *  match
-         */
-        uint32_t s_notify:1;
-        uint32_t reserved_14:2;
-        /** match_mode : R/W; bitpos: [17:16]; default: 0;
-         *  Configures the comparator match mode: \\0: Only the primary comparator matches \\1:
-         *  Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or
-         *  secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary
-         *  comparator matches and stop filtering when the secondary comparator matches\\
-         */
-        uint32_t match_mode:2;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} trace_filter_comparator_control_reg_t;
-
-/** Type of filter_p_comparator_match register
- *  primary comparator match value
- */
-typedef union {
-    struct {
-        /** p_match : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the match value for the primary comparator
-         */
-        uint32_t p_match:32;
-    };
-    uint32_t val;
-} trace_filter_p_comparator_match_reg_t;
-
-/** Type of filter_s_comparator_match register
- *  secondary comparator match value
- */
-typedef union {
-    struct {
-        /** s_match : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the match value for the secondary comparator
-         */
-        uint32_t s_match:32;
-    };
-    uint32_t val;
-} trace_filter_s_comparator_match_reg_t;
-
-/** Type of resync_prolonged register
- *  Resync configuration register
- */
-typedef union {
-    struct {
-        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
-         *  Configures the threshold for synchronization counter
-         */
-        uint32_t resync_prolonged:24;
-        /** resync_mode : R/W; bitpos: [25:24]; default: 0;
-         *  Configures the synchronization mode: \\0: Disable the synchronization counter \\1:
-         *  Invalid \\2: Synchronization counter counts by packet  \\3: Synchronization counter
-         *  counts by cycle\\
-         */
-        uint32_t resync_mode:2;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} trace_resync_prolonged_reg_t;
-
-/** Type of ahb_config register
- *  AHB config register
- */
-typedef union {
-    struct {
-        /** hburst : R/W; bitpos: [2:0]; default: 0;
-         *  Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4
-         *  \\4:INCR8 \\Others:Invalid
-         */
-        uint32_t hburst:3;
-        /** max_incr : R/W; bitpos: [5:3]; default: 0;
-         *  Configures the maximum burst length for INCR mode
-         */
-        uint32_t max_incr:3;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} trace_ahb_config_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Configures register clock gating. \\0: Support clock only when the application
-         *  writes registers to save power. \\1:Always force the clock on for registers \\ This
-         *  bit does't affect register access.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} trace_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35721984;
-         *  Version control register.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} trace_date_reg_t;
-
-
-typedef struct {
-    volatile trace_mem_start_addr_reg_t mem_start_addr;
-    volatile trace_mem_end_addr_reg_t mem_end_addr;
-    volatile trace_mem_current_addr_reg_t mem_current_addr;
-    volatile trace_mem_addr_update_reg_t mem_addr_update;
-    volatile trace_fifo_status_reg_t fifo_status;
-    volatile trace_intr_ena_reg_t intr_ena;
-    volatile trace_intr_raw_reg_t intr_raw;
-    volatile trace_intr_clr_reg_t intr_clr;
-    volatile trace_trigger_reg_t trigger;
-    volatile trace_config_reg_t config;
-    volatile trace_filter_control_reg_t filter_control;
-    volatile trace_filter_match_control_reg_t filter_match_control;
-    volatile trace_filter_comparator_control_reg_t filter_comparator_control;
-    volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match;
-    volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match;
-    volatile trace_resync_prolonged_reg_t resync_prolonged;
-    volatile trace_ahb_config_reg_t ahb_config;
-    volatile trace_clock_gate_reg_t clock_gate;
-    uint32_t reserved_048[237];
-    volatile trace_date_reg_t date;
-} trace_dev_t;
-
-extern trace_dev_t TRACE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/uart_struct.h b/components/soc/esp32c61/include/soc/uart_struct.h
deleted file mode 100644
index 0dfffb1a286..00000000000
--- a/components/soc/esp32c61/include/soc/uart_struct.h
+++ /dev/null
@@ -1,1349 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
-         *  Represents the data UART $n read from FIFO.\\
-         *  Measurement unit: byte.
-         */
-        uint32_t rxfifo_rd_byte:32;
-    };
-    uint32_t val;
-} uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable UART receiver's timeout function.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  Configures the amount of time that the bus can remain idle before timeout.\\
-         *  Measurement unit: bit time (the time to transmit 1 bit).
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status of UART_RXFIFO_FULL_INT.
-         */
-        uint32_t rxfifo_full_int_raw:1;
-        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
-         *  The raw interrupt status of UART_TXFIFO_EMPTY_INT.
-         */
-        uint32_t txfifo_empty_int_raw:1;
-        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status of UART_PARITY_ERR_INT.
-         */
-        uint32_t parity_err_int_raw:1;
-        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status of UART_FRM_ERR_INT.
-         */
-        uint32_t frm_err_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw interrupt status of UART_RXFIFO_OVF_INT.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw interrupt status of UART_DSR_CHG_INT.
-         */
-        uint32_t dsr_chg_int_raw:1;
-        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw interrupt status of UART_CTS_CHG_INT.
-         */
-        uint32_t cts_chg_int_raw:1;
-        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw interrupt status of UART_BRK_DET_INT.
-         */
-        uint32_t brk_det_int_raw:1;
-        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw interrupt status of UART_RXFIFO_TOUT_INT.
-         */
-        uint32_t rxfifo_tout_int_raw:1;
-        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw interrupt status of UART_SW_XON_INT.
-         */
-        uint32_t sw_xon_int_raw:1;
-        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  UART_SW_XOFF_INT.
-         */
-        uint32_t sw_xoff_int_raw:1;
-        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw interrupt status of UART_GLITCH_DET_INT.
-         */
-        uint32_t glitch_det_int_raw:1;
-        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw interrupt status of UART_TX_BRK_DONE_INT.
-         */
-        uint32_t tx_brk_done_int_raw:1;
-        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw interrupt status of UART_TX_BRK_IDLE_DONE_INT.
-         */
-        uint32_t tx_brk_idle_done_int_raw:1;
-        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw interrupt status of UART_TX_DONE_INT.
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw interrupt status of UART_RS485_PARITY_ERR_INT.
-         */
-        uint32_t rs485_parity_err_int_raw:1;
-        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw interrupt status of UART_RS485_FRM_ERR_INT.
-         */
-        uint32_t rs485_frm_err_int_raw:1;
-        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw interrupt status of UART_RS485_CLASH_INT.
-         */
-        uint32_t rs485_clash_int_raw:1;
-        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw interrupt status of UART_AT_CMD_CHAR_DET_INT.
-         */
-        uint32_t at_cmd_char_det_int_raw:1;
-        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw interrupt status of UART_WAKEUP_INT.
-         */
-        uint32_t wakeup_int_raw:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status of UART_RXFIFO_FULL_INT.
-         */
-        uint32_t rxfifo_full_int_st:1;
-        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status of UART_TXFIFO_EMPTY_INT.
-         */
-        uint32_t txfifo_empty_int_st:1;
-        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status of UART_PARITY_ERR_INT.
-         */
-        uint32_t parity_err_int_st:1;
-        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status of UART_FRM_ERR_INT.
-         */
-        uint32_t frm_err_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked interrupt status of UART_RXFIFO_OVF_INT.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked interrupt status of UART_DSR_CHG_INT.
-         */
-        uint32_t dsr_chg_int_st:1;
-        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked interrupt status of UART_CTS_CHG_INT.
-         */
-        uint32_t cts_chg_int_st:1;
-        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked interrupt status of UART_BRK_DET_INT.
-         */
-        uint32_t brk_det_int_st:1;
-        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked interrupt status of UART_RXFIFO_TOUT_INT.
-         */
-        uint32_t rxfifo_tout_int_st:1;
-        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked interrupt status of UART_SW_XON_INT.
-         */
-        uint32_t sw_xon_int_st:1;
-        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked interrupt status of UART_SW_XOFF_INT.
-         */
-        uint32_t sw_xoff_int_st:1;
-        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked interrupt status of UART_GLITCH_DET_INT.
-         */
-        uint32_t glitch_det_int_st:1;
-        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked interrupt status of UART_TX_BRK_DONE_INT.
-         */
-        uint32_t tx_brk_done_int_st:1;
-        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked interrupt status of UART_TX_BRK_IDLE_DONE_INT.
-         */
-        uint32_t tx_brk_idle_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked interrupt status of UART_TX_DONE_INT.
-         */
-        uint32_t tx_done_int_st:1;
-        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked interrupt status of UART_RS485_PARITY_ERR_INT.
-         */
-        uint32_t rs485_parity_err_int_st:1;
-        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
-         *  The masked interrupt status of UART_RS485_FRM_ERR_INT.
-         */
-        uint32_t rs485_frm_err_int_st:1;
-        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
-         *  The masked interrupt status of UART_RS485_CLASH_INT.
-         */
-        uint32_t rs485_clash_int_st:1;
-        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
-         *  The masked interrupt status of UART_AT_CMD_CHAR_DET_INT.
-         */
-        uint32_t at_cmd_char_det_int_st:1;
-        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
-         *  The masked interrupt status of UART_WAKEUP_INT.
-         */
-        uint32_t wakeup_int_st:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable UART_RXFIFO_FULL_INT.
-         */
-        uint32_t rxfifo_full_int_ena:1;
-        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable UART_TXFIFO_EMPTY_INT.
-         */
-        uint32_t txfifo_empty_int_ena:1;
-        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable UART_PARITY_ERR_INT.
-         */
-        uint32_t parity_err_int_ena:1;
-        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to enable UART_FRM_ERR_INT.
-         */
-        uint32_t frm_err_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to enable UART_RXFIFO_OVF_INT.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to enable UART_DSR_CHG_INT.
-         */
-        uint32_t dsr_chg_int_ena:1;
-        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Write 1 to enable UART_CTS_CHG_INT.
-         */
-        uint32_t cts_chg_int_ena:1;
-        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Write 1 to enable UART_BRK_DET_INT.
-         */
-        uint32_t brk_det_int_ena:1;
-        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Write 1 to enable UART_RXFIFO_TOUT_INT.
-         */
-        uint32_t rxfifo_tout_int_ena:1;
-        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Write 1 to enable UART_SW_XON_INT.
-         */
-        uint32_t sw_xon_int_ena:1;
-        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Write 1 to enable UART_SW_XOFF_INT.
-         */
-        uint32_t sw_xoff_int_ena:1;
-        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Write 1 to enable UART_GLITCH_DET_INT.
-         */
-        uint32_t glitch_det_int_ena:1;
-        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Write 1 to enable UART_TX_BRK_DONE_INT.
-         */
-        uint32_t tx_brk_done_int_ena:1;
-        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Write 1 to enable UART_TX_BRK_IDLE_DONE_INT.
-         */
-        uint32_t tx_brk_idle_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Write 1 to enable UART_TX_DONE_INT.
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Write 1 to enable UART_RS485_PARITY_ERR_INT.
-         */
-        uint32_t rs485_parity_err_int_ena:1;
-        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
-         *  Write 1 to enable UART_RS485_FRM_ERR_INT.
-         */
-        uint32_t rs485_frm_err_int_ena:1;
-        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
-         *  Write 1 to enable UART_RS485_CLASH_INT.
-         */
-        uint32_t rs485_clash_int_ena:1;
-        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
-         *  Write 1 to enable UART_AT_CMD_CHAR_DET_INT.
-         */
-        uint32_t at_cmd_char_det_int_ena:1;
-        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
-         *  Write 1 to enable UART_WAKEUP_INT.
-         */
-        uint32_t wakeup_int_ena:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear UART_RXFIFO_FULL_INT.
-         */
-        uint32_t rxfifo_full_int_clr:1;
-        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear UART_TXFIFO_EMPTY_INT.
-         */
-        uint32_t txfifo_empty_int_clr:1;
-        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear UART_PARITY_ERR_INT.
-         */
-        uint32_t parity_err_int_clr:1;
-        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear UART_FRM_ERR_INT.
-         */
-        uint32_t frm_err_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear UART_RXFIFO_OVF_INT.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear UART_DSR_CHG_INT.
-         */
-        uint32_t dsr_chg_int_clr:1;
-        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
-         *  Write 1 to clear UART_CTS_CHG_INT.
-         */
-        uint32_t cts_chg_int_clr:1;
-        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
-         *  Write 1 to clear UART_BRK_DET_INT.
-         */
-        uint32_t brk_det_int_clr:1;
-        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
-         *  Write 1 to clear UART_RXFIFO_TOUT_INT.
-         */
-        uint32_t rxfifo_tout_int_clr:1;
-        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
-         *  Write 1 to clear UART_SW_XON_INT.
-         */
-        uint32_t sw_xon_int_clr:1;
-        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
-         *  Write 1 to clear UART_SW_XOFF_INT.
-         */
-        uint32_t sw_xoff_int_clr:1;
-        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
-         *  Write 1 to clear UART_GLITCH_DET_INT.
-         */
-        uint32_t glitch_det_int_clr:1;
-        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  Write 1 to clear UART_TX_BRK_DONE_INT.
-         */
-        uint32_t tx_brk_done_int_clr:1;
-        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  Write 1 to clear UART_TX_BRK_IDLE_DONE_INT.
-         */
-        uint32_t tx_brk_idle_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  Write 1 to clear UART_TX_DONE_INT.
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
-         *  Write 1 to clear UART_RS485_PARITY_ERR_INT.
-         */
-        uint32_t rs485_parity_err_int_clr:1;
-        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
-         *  Write 1 to clear UART_RS485_FRM_ERR_INT.
-         */
-        uint32_t rs485_frm_err_int_clr:1;
-        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
-         *  Write 1 to clear UART_RS485_CLASH_INT.
-         */
-        uint32_t rs485_clash_int_clr:1;
-        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
-         *  Write 1 to clear UART_AT_CMD_CHAR_DET_INT.
-         */
-        uint32_t at_cmd_char_det_int_clr:1;
-        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
-         *  Write 1 to clear UART_WAKEUP_INT.
-         */
-        uint32_t wakeup_int_clr:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
-         *  Configures the integral part of the divisor for baud rate generation.
-         */
-        uint32_t clkdiv_int:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  Configures the fractional part of the divisor for baud rate generation.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  RX filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's
-         *  clock cycle.\\Pulses whose width is lower than this value will be ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable RX signal filter.\\
-         *  0: Disable\\
-         *  1: Enable
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  Configuration register 0
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  Configures the parity check mode.\\
-         *  0: Even parity\\
-         *  1: Odd parity\\
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable UART parity check.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  Configures the number of data bits.\\
-         *  0: 5 bits\\
-         *  1: 6 bits\\
-         *  2: 7 bits\\
-         *  3: 8 bits\\
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  Configures the number of stop bits.\\
-         *  0: Invalid. No effect\\
-         *  1: 1 bits\\
-         *  2: 1.5 bits\\
-         *  3: 2 bits\\
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to send NULL characters when finishing data
-         *  transmission.\\
-         *  0: Not send\\
-         *  1: Send\\
-         */
-        uint32_t txd_brk:1;
-        /** irda_dplx : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable IrDA loopback test.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t irda_dplx:1;
-        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable the IrDA transmitter.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t irda_tx_en:1;
-        /** irda_wctl : R/W; bitpos: [9]; default: 0;
-         *  Configures the 11th bit of the IrDA transmitter.\\
-         *  0: This bit is 0.\\
-         *  1: This bit is the same as the 10th bit.\\
-         */
-        uint32_t irda_wctl:1;
-        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to invert the level of the IrDA transmitter.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t irda_tx_inv:1;
-        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert the level of the IrDA receiver.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t irda_rx_inv:1;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable UART loopback test.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable flow control for the transmitter.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t tx_flow_en:1;
-        /** irda_en : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable IrDA protocol.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t irda_en:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to invert the level of UART RXD signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to invert the level of UART TXD signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to disable data overflow detection for the UART
-         *  receiver.\\
-         *  0: Enable\\
-         *  1: Disable\\
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to store the received data with errors into FIFO.\\
-         *  0: Store\\
-         *  1: Not store\\
-         */
-        uint32_t err_wr_mask:1;
-        /** autobaud_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable baud rate detection.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t autobaud_en:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable clock gating for UART memory.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  Configures the RTS signal used in software flow control.\\
-         *  0: The UART transmitter is allowed to send data.\\
-         *  1: The UART transmitted is not allowed to send data.\\
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Configures whether or not to reset the UART RX FIFO.\\
-         *  0: Not reset\\
-         *  1: Reset\\
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Configures whether or not to reset the UART TX FIFO.\\
-         *  0: Not reset\\
-         *  1: Reset\\
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
-         *  Configures the threshold for RX FIFO being full.\\Measurement unit: byte.
-         */
-        uint32_t rxfifo_full_thrhd:8;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
-         *  Configures the threshold for TX FIFO being empty.\\Measurement unit: byte.
-         */
-        uint32_t txfifo_empty_thrhd:8;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to invert the level of UART CTS signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to invert the level of UART DSR signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to invert the level of UART RTS signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to invert the level of UART DTR signal.\\
-         *  0: Not invert\\
-         *  1: Invert\\
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  Configures the DTR signal used in software flow control.\\
-         *  0: Data to be transmitted is not ready.\\
-         *  1: Data to be transmitted is ready.\\
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  Configures clock gating.\\
-         *  0: Support clock only when the application writes registers.\\
-         *  1: Always force the clock on for registers.\\
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow control configuration
- */
-typedef union {
-    struct {
-        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the maximum number of data bytes that can be received  during hardware
-         *  flow control.\\Measurement unit: byte.
-         */
-        uint32_t rx_flow_thrhd:8;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable the UART receiver.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configuration register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  Configures wakeup character 1.
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  Configures wakeup character 2.
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  Configures wakeup character 3.
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  Configures wakeup character 4.
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configuration register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  Configures wakeup character 0.
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configuration register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  Configures the number of RXD edge changes to wake up the chip in wakeup mode 0.
-         */
-        uint32_t active_threshold:10;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
-         *  Configures the number of received data bytes to wake up the chip in wakeup mode 1.
-         */
-        uint32_t rx_wake_up_thrhd:8;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  Configures the number of wakeup characters.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  Configures whether or not to mask wakeup characters.\\
-         *  0: Not mask\\
-         *  1: Mask\\
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  Configures which wakeup mode to select.\\
-         *  0: Mode 0\\
-         *  1: Mode 1\\
-         *  2: Mode 2\\
-         *  3: Mode 3\\
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  Configures the XON character for flow control.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  Configures the XOFF character for flow control.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  Configures whether the UART transmitter can send XON or XOFF characters when it is
-         *  disabled.\\
-         *  0: Cannot send\\
-         *  1: Can send\\
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable software flow control.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to remove flow control characters from the received
-         *  data.\\
-         *  0: Not move\\
-         *  1: Move\\
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Configures whether the transmitter continues to sending data.\\
-         *  0: Not send\\
-         *  1: Send\\
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to stop the transmitter from sending data.\\
-         *  0: Not stop\\
-         *  1: Stop\\
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Configures whether or not to send XON characters.\\
-         *  0: Not send\\
-         *  1: Send\\
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Configures whether or not to send XOFF characters.\\
-         *  0: Not send\\
-         *  1: Send\\
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow control character configuration
- */
-typedef union {
-    struct {
-        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the threshold for data in RX FIFO to send XON characters in software
-         *  flow control.\\Measurement unit: byte.
-         */
-        uint32_t xon_threshold:8;
-        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
-         *  Configures the threshold for data in RX FIFO to send XOFF characters in software
-         *  flow control.\\Measurement unit: byte.
-         */
-        uint32_t xoff_threshold:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  TX break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  Configures the number of NULL characters to be sent after finishing data
-         *  transmission.\\Valid only when UART_TXD_BRK is 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame end idle time configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  Configures the threshold to generate a frame end signal when the receiver takes
-         *  more time to receive one data byte data.\\Measurement unit: bit time (the time to
-         *  transmit 1 bit).
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  Configures the interval between two data transfers.\\Measurement unit: bit time
-         *  (the time to transmit 1 bit).
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        /** rs485_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable RS485 mode.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rs485_en:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\
-         *  0: Not add\\
-         *  1: Add\\
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\
-         *  0: Not add\\
-         *  1: Add\\
-         */
-        uint32_t dl1_en:1;
-        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable the receiver for data reception when the
-         *  transmitter is transmitting data in RS485 mode.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rs485tx_rx_en:1;
-        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether to enable the RS485 transmitter for data transmission when the
-         *  RS485 receiver is busy.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rs485rxby_tx_en:1;
-        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
-         *  Configures the delay of internal data signals in the receiver.\\Measurement unit:
-         *  bit time (the time to transmit 1 bit)..
-         */
-        uint32_t rs485_rx_dly_num:1;
-        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
-         *  Configures the delay of internal data signals in the transmitter.\\Measurement
-         *  unit: bit time (the time to transmit 1 bit).
-         */
-        uint32_t rs485_tx_dly_num:4;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rs485_conf_sync_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Configures whether or not to enable UART TX clock.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Configures whether or not to enable UART RX clock.\\
-         *  0: Disable\\
-         *  1: Enable\\
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 and then write 0 to reset UART TX.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 and then write 0 to reset UART RX.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
-         *  Represents the number of valid data bytes in RX FIFO.
-         */
-        uint32_t rxfifo_cnt:8;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  Represents the level of the internal UART DSR signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  Represents the level of the internal UART CTS signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  Represents the  level of the internal UART RXD signal.
-         */
-        uint32_t rxd:1;
-        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
-         *  Represents the number of valid data bytes in RX FIFO.
-         */
-        uint32_t txfifo_cnt:8;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  Represents the level of the internal UART DTR signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  Represents the level of the internal UART RTS signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  Represents the  level of the internal UART TXD signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  TX FIFO write and read offset address
- */
-typedef union {
-    struct {
-        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
-         *  Represents the offset address to write TX FIFO.
-         */
-        uint32_t tx_sram_waddr:8;
-        uint32_t reserved_8:1;
-        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
-         *  Represents the offset address to read TX FIFO.
-         */
-        uint32_t tx_sram_raddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx FIFO write and read offset address
- */
-typedef union {
-    struct {
-        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
-         *  Represents the offset address to read RX FIFO.
-         */
-        uint32_t rx_sram_raddr:8;
-        uint32_t reserved_8:1;
-        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
-         *  Represents the offset address to write RX FIFO.
-         */
-        uint32_t rx_sram_waddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  Represents the status of the receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  Represents the status of the transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART asynchronous FIFO status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not the APB TX asynchronous FIFO is full.\\
-         *  0: Not full\\
-         *  1: Full\\
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Represents whether or not the APB TX asynchronous FIFO is empty.\\
-         *  0: Not empty\\
-         *  1: Empty\\
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Represents whether or not the APB RX asynchronous FIFO is full.\\
-         *  0: Not full\\
-         *  1: Full\\
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Represents whether or not the APB RX asynchronous FIFO is empty.\\
-         *  0: Not empty\\
-         *  1: Empty\\
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  Configures the idle time before the receiver receives the first
-         *  AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit).
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  Configures the interval between the last AT_CMD and subsequent data.\\Measurement
-         *  unit: bit time (the time to transmit 1 bit).
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  Configures the interval between two AT_CMD characters.\\Measurement unit: bit time
-         *  (the time to transmit 1 bit).
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
-         *  Configures the AT_CMD character.
-         */
-        uint32_t at_cmd_char:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  Configures the number of continuous AT_CMD characters a receiver can receive.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Autobaud Register */
-/** Type of pospulse register
- *  Autobaud high pulse register
- */
-typedef union {
-    struct {
-        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  Represents the minimal input clock counter value between two positive edges. It is
-         *  used for baud rate detection.
-         */
-        uint32_t posedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_pospulse_reg_t;
-
-/** Type of negpulse register
- *  Autobaud low pulse register
- */
-typedef union {
-    struct {
-        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  Represents the minimal input clock counter value between two negative edges. It is
-         *  used for baud rate detection.
-         */
-        uint32_t negedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_negpulse_reg_t;
-
-/** Type of lowpulse register
- *  Autobaud minimum low pulse duration register
- */
-typedef union {
-    struct {
-        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  Represents the minimum duration time of a low-level pulse. It is used for baud rate
-         *  detection.\\Measurement unit: APB_CLK clock cycle.
-         */
-        uint32_t lowpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_lowpulse_reg_t;
-
-/** Type of highpulse register
- *  Autobaud minimum high pulse duration register
- */
-typedef union {
-    struct {
-        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  Represents  the maximum duration time for a high-level pulse. It is used for baud
-         *  rate detection.\\Measurement unit: APB_CLK clock cycle.
-         */
-        uint32_t highpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_highpulse_reg_t;
-
-/** Type of rxd_cnt register
- *  Autobaud edge change count register
- */
-typedef union {
-    struct {
-        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
-         *  Represents the number of RXD edge changes. It is used for baud rate detection.
-         */
-        uint32_t rxd_edge_cnt:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rxd_cnt_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 36774432;
-         *  Version control register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART register configuration update
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Configures whether or not to synchronize registers.\\
-         *  0: Not synchronize\\
-         *  1: Synchronize\\
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  Configures the UART ID.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} uart_id_reg_t;
-
-
-typedef struct uart_dev_s {
-    volatile uart_fifo_reg_t fifo;
-    volatile uart_int_raw_reg_t int_raw;
-    volatile uart_int_st_reg_t int_st;
-    volatile uart_int_ena_reg_t int_ena;
-    volatile uart_int_clr_reg_t int_clr;
-    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile uart_rx_filt_reg_t rx_filt;
-    volatile uart_status_reg_t status;
-    volatile uart_conf0_sync_reg_t conf0_sync;
-    volatile uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile uart_sleep_conf0_reg_t sleep_conf0;
-    volatile uart_sleep_conf1_reg_t sleep_conf1;
-    volatile uart_sleep_conf2_reg_t sleep_conf2;
-    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile uart_swfc_conf1_reg_t swfc_conf1;
-    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile uart_mem_conf_reg_t mem_conf;
-    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile uart_mem_tx_status_reg_t mem_tx_status;
-    volatile uart_mem_rx_status_reg_t mem_rx_status;
-    volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;
-    volatile uart_negpulse_reg_t negpulse;
-    volatile uart_lowpulse_reg_t lowpulse;
-    volatile uart_highpulse_reg_t highpulse;
-    volatile uart_rxd_cnt_reg_t rxd_cnt;
-    volatile uart_clk_conf_reg_t clk_conf;
-    volatile uart_date_reg_t date;
-    volatile uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile uart_reg_update_reg_t reg_update;
-    volatile uart_id_reg_t id;
-} uart_dev_t;
-
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-extern uart_dev_t UART2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h
deleted file mode 100644
index e9e9b833733..00000000000
--- a/components/soc/esp32c61/include/soc/usb_serial_jtag_reg.h
+++ /dev/null
@@ -1,1228 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** USB_SERIAL_JTAG_EP1_REG register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
- *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
- *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
- *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
- *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
- *  how many data is received, then read data from UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
- *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
- */
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
-#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
- *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
- *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
- *  USB Host.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
- *  1'b1: Indicate there is data in UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- *  Interrupt raw status register.
- */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when flush cmd is received for IN
- *  endpoint 2 of JTAG.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when SOF frame is received.
- */
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- *  one packet.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
- *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when pid error is detected.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt bit turns to high level when CRC5 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt bit turns to high level when CRC16 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt bit turns to high level when stuff error is detected.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
- *  received.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt bit turns to high level when usb bus reset is detected.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
-
-/** USB_SERIAL_JTAG_INT_ST_REG register
- *  Interrupt status register.
- */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
-
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- *  Interrupt enable status register.
- */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
-
-/** USB_SERIAL_JTAG_INT_CLR_REG register
- *  Interrupt clear status register.
- */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
-
-/** USB_SERIAL_JTAG_CONF0_REG register
- *  PHY hardware configuration.
- */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  Select internal/external PHY
- */
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
- *  Enable software control USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
- *  USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
- *  Control single-end input high threshold,1.76V to 2V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFH    0x00000003U
-#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
-#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFH_S  3
-/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
- *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFL    0x00000003U
-#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
-#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFL_S  5
-/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
- *  Enable software control input  threshold
- */
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
- *  Enable software control USB D+ D- pullup pulldown
- */
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
- *  Control USB D+ pull up.
- */
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
- *  Control USB D+ pull down.
- */
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
- *  Control USB D- pull up.
- */
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
- *  Control USB D- pull down.
- */
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
- *  Control pull up value.
- */
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
- *  Enable USB pad function.
- */
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
- *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
- *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
- *  through GPIO Matrix.
- */
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
-
-/** USB_SERIAL_JTAG_TEST_REG register
- *  Registers used for debugging the PHY.
- */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
-/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Enable test of the USB pad
- */
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad oen in test
- */
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- *  USB D+ tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- *  USB D- tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
- *  USB RCV value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
-#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
-/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
- *  USB D+ rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
-#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
-/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
- *  USB D- rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
-#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
-
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- *  JTAG FIFO status and control registers.
- */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
- *  JTAT in fifo counter.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- *  1: JTAG in fifo is empty.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
- *  1: JTAG in fifo is full.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
- *  JTAT out fifo counter.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
- *  1: JTAG out fifo is empty.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
- *  1: JTAG out fifo is full.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
- *  Write 1 to reset JTAG in fifo.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
- *  Write 1 to reset JTAG out fifo.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- *  Last received SOF frame index register.
- */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
- *  Frame index of received SOF frame.
- */
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- *  Control IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- *  CDC-ACM IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
-/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- *  JTAG IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- *  Control OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- *  CDC-ACM OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
-/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
- *  Data count in OUT endpoint 1 when one packet is received.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- *  JTAG OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- *  Clock enable control
- */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
-#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- *  Memory power control
- */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  1: power down usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  1: Force clock on for usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-
-/** USB_SERIAL_JTAG_CHIP_RST_REG register
- *  CDC-ACM chip reset control.
- */
-#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
-/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
- *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_RTS    (BIT(0))
-#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
-#define USB_SERIAL_JTAG_RTS_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_S  0
-/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
- *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_DTR    (BIT(1))
-#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
-#define USB_SERIAL_JTAG_DTR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_S  1
-/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
- *  Set this bit to disable chip reset from usb serial channel to reset chip.
- */
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
- *  W0 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
-/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
- *  W1 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
-/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
-/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_S  16
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
- *  W0 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
-/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
- *  W1 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
-/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
-/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
-
-/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
- *  Configuration registers' value update
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
-/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
- *  Write 1 to this register would update the value of configure registers from APB
- *  clock domain to 48MHz clock domain.
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
-
-/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
- *  Serial AFIFO configure register
- */
-#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
- *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
-
-/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
- *  USB Bus reset status register
- */
-#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
-/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
- *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
- *  reset is released.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
-
-/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG register
- *  USB uart out endpoint timeout configuration.
- */
-#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
-/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN : R/W; bitpos: [0]; default: 0;
- *  USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
- *  is automatically cleared and reg_serial_timeout_status is asserted.
- */
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S)
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S  0
-/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS : R/WTC/SS; bitpos: [1]; default: 0;
- *  Serial out ep triggers a timeout event.
- */
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S)
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S  1
-/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear reg_serial_timeout_status.
- */
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S  2
-
-/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG register
- *  USB uart out endpoint timeout configuration.
- */
-#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
-/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX : R/W; bitpos: [31:0]; default: 4800768;
- *  USB serial out ep timeout max threshold value, indicates the maximum time that
- *  waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
- */
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S)
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S  0
-
-/** USB_SERIAL_JTAG_DATE_REG register
- *  Date register
- */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368;
- *  register version.
- */
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/include/soc/xts_aes_reg.h b/components/soc/esp32c61/include/soc/xts_aes_reg.h
deleted file mode 100644
index 55e0e19beb1..00000000000
--- a/components/soc/esp32c61/include/soc/xts_aes_reg.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define XTS_AES_PLAIN_MEM(i)          (REG_SPI_MEM_BASE(i) + 0x300)
-/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This field is only used to generate include file in c case. This field is useles
-s. Please do not use this field..*/
-#define XTS_AES_PLAIN    0xFFFFFFFF
-#define XTS_AES_PLAIN_M  ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
-#define XTS_AES_PLAIN_V  0xFFFFFFFF
-#define XTS_AES_PLAIN_S  0
-
-#define XTS_AES_LINESIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x340)
-/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the line-size parameter which will be used in manual encryption
- calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
- 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
-#define XTS_AES_LINESIZE    0x00000003
-#define XTS_AES_LINESIZE_M  ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
-#define XTS_AES_LINESIZE_V  0x3
-#define XTS_AES_LINESIZE_S  0
-
-#define XTS_AES_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
-/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit stores the destination parameter which will be used in manual encryptio
-n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
-used..*/
-#define XTS_AES_DESTINATION    (BIT(0))
-#define XTS_AES_DESTINATION_M  (BIT(0))
-#define XTS_AES_DESTINATION_V  0x1
-#define XTS_AES_DESTINATION_S  0
-
-#define XTS_AES_PHYSICAL_ADDRESS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x348)
-/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits stores the physical-address parameter which will be used in manual enc
-ryption calculation. This value should aligned with byte number decided by line-
-size parameter..*/
-#define XTS_AES_PHYSICAL_ADDRESS    0x03FFFFFF
-#define XTS_AES_PHYSICAL_ADDRESS_M  ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
-#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFF
-#define XTS_AES_PHYSICAL_ADDRESS_S  0
-
-#define XTS_AES_TRIGGER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34C)
-/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to trigger the process of manual encryption calculation. This actio
-n should only be asserted when manual encryption status is 0. After this action,
- manual encryption status becomes 1. After calculation is done, manual encryptio
-n status becomes 2..*/
-#define XTS_AES_TRIGGER    (BIT(0))
-#define XTS_AES_TRIGGER_M  (BIT(0))
-#define XTS_AES_TRIGGER_V  0x1
-#define XTS_AES_TRIGGER_S  0
-
-#define XTS_AES_RELEASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x350)
-/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to release encrypted result to mspi. This action should only be ass
-erted when manual encryption status is 2. After this action, manual encryption s
-tatus will become 3..*/
-#define XTS_AES_RELEASE    (BIT(0))
-#define XTS_AES_RELEASE_M  (BIT(0))
-#define XTS_AES_RELEASE_V  0x1
-#define XTS_AES_RELEASE_S  0
-
-#define XTS_AES_DESTROY_REG(i)          (REG_SPI_MEM_BASE(i) + 0x354)
-/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
-en manual encryption status is 3. After this action, manual encryption status wi
-ll become 0..*/
-#define XTS_AES_DESTROY    (BIT(0))
-#define XTS_AES_DESTROY_M  (BIT(0))
-#define XTS_AES_DESTROY_V  0x1
-#define XTS_AES_DESTROY_S  0
-
-#define XTS_AES_STATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x358)
-/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
- calculation, 2: encryption calculation is done but the encrypted result is invi
-sible to mspi, 3: the encrypted result is visible to mspi..*/
-#define XTS_AES_STATE    0x00000003
-#define XTS_AES_STATE_M  ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
-#define XTS_AES_STATE_V  0x3
-#define XTS_AES_STATE_S  0
-
-#define XTS_AES_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x35C)
-/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
-/*description: This bits stores the last modified-time of manual encryption feature..*/
-#define XTS_AES_DATE    0x3FFFFFFF
-#define XTS_AES_DATE_M  ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
-#define XTS_AES_DATE_V  0x3FFFFFFF
-
-#define XTS_AES_DPA_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x388)
-/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
-T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V  0x1
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S  4
-/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
-ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
-ing key 1..*/
-#define XTS_AES_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_V  0x1
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_S  3
-/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
-7: The bigger the number is, the more secure the cryption is. (Note that the per
-formance of cryption will decrease together with this number increasing).*/
-#define XTS_AES_CRYPT_SECURITY_LEVEL    0x00000007
-#define XTS_AES_CRYPT_SECURITY_LEVEL_M  ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
-#define XTS_AES_CRYPT_SECURITY_LEVEL_V  0x7
-#define XTS_AES_CRYPT_SECURITY_LEVEL_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32c61/ld/esp32c61.peripherals.ld b/components/soc/esp32c61/ld/esp32c61.peripherals.ld
index 6d5ca8d8c3b..8490671b17b 100644
--- a/components/soc/esp32c61/ld/esp32c61.peripherals.ld
+++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld
@@ -15,7 +15,7 @@ PROVIDE ( LEDC_GAMMA_RAM      = 0x60007400 );
 PROVIDE ( TIMERG0             = 0x60008000 );
 PROVIDE ( TIMERG1             = 0x60009000 );
 PROVIDE ( SYSTIMER            = 0x6000A000 );
-PROVIDE ( I2S                 = 0x6000C000 );
+PROVIDE ( I2S0                = 0x6000C000 );
 PROVIDE ( ADC                 = 0x6000E000 );
 PROVIDE ( USB_SERIAL_JTAG     = 0x6000F000 );
 PROVIDE ( INTMTX              = 0x60010000 );
@@ -29,6 +29,8 @@ PROVIDE ( ECC                 = 0x6008B000 );
 PROVIDE ( ECDSA               = 0x6008E000 );
 PROVIDE ( IO_MUX              = 0x60090000 );
 PROVIDE ( GPIO                = 0x60091000 );
+PROVIDE ( GPIO_EXT            = 0x60091e00 );
+PROVIDE ( GPIO_ETM            = 0x60091f18 );
 PROVIDE ( TCM_MEM_MONITOR     = 0x60092000 );
 PROVIDE ( PAU                 = 0x60093000 );
 PROVIDE ( HP_SYSTEM           = 0x60095000 );
diff --git a/components/soc/esp32c61/ledc_periph.c b/components/soc/esp32c61/ledc_periph.c
index 867e469ac4e..3fed785c271 100644
--- a/components/soc/esp32c61/ledc_periph.c
+++ b/components/soc/esp32c61/ledc_periph.c
@@ -15,3 +15,152 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
     }
 };
+
+/**
+ * LEDC registers to be saved for sleep retention
+ *
+ * channel:
+ * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
+ * LEDC_CHx_GAMMA_CONF_REG, LEDC_CHx_GAMMA_RANGEi_REG
+ *
+ * timer:
+ * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
+ *
+ * common:
+ * LEDC_INT_ENA_REG,
+ * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
+ * LEDC_CONF_REG,
+ *
+ * Note 1: Gamma parameter registers are backuped and restored. But we won't start a fade automatically after wake-up.
+ *         Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep.
+ *
+ * Note 2: For timer/channel registers to get synced, update bits need to be set
+ *
+ * Note 3: Gamma RAM registers R/W relies both APB and function clock, therefore, retention requires the existence of function clock
+ */
+#define LEDC_COMMON_RETENTION_REGS_CNT  5
+#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
+static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x400, 0x0, 0x0};
+static const regdma_entries_config_t ledc_common_regdma_entries[] = {
+    // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
+    // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
+			 							    LEDC_INT_ENA_REG, 0,
+			 							    (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1),
+		    .owner = LEDC_RETENTION_ENTRY },
+    [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
+                                               LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
+                                               LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
+                                               ledc_common_regs_map[0], ledc_common_regs_map[1],
+                                               ledc_common_regs_map[2], ledc_common_regs_map[3]),
+            .owner = LEDC_RETENTION_ENTRY },
+};
+
+#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
+	[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
+			 								     LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+			 								     LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
+			 							    LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
+static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
+static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0};
+#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
+	[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
+                                               LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
+                                               LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
+                                               ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
+                                               ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+                                                 LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
+			 							    LEDC_DUTY_START_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
+			 							    LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
+			 							    LEDC_PARA_UP_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \
+                                                 LEDC_CH##chan##_GAMMA_CONF_REG, LEDC_CH##chan##_GAMMA_CONF_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+    [5] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x05), \
+                                               LEDC_CH##chan##_GAMMA_RANGE0_REG, LEDC_CH##chan##_GAMMA_RANGE0_REG, \
+                                               SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX, 0, 0, \
+                                               ledc_channel_gamma_regs_map[0], ledc_channel_gamma_regs_map[1], \
+                                               ledc_channel_gamma_regs_map[2], ledc_channel_gamma_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
+
+static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
+static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
+static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+    .common = {
+		.regdma_entry_array = ledc_common_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
+	},
+	.timer[0] = {
+		.regdma_entry_array = ledc_timer0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
+	},
+	.timer[1] = {
+		.regdma_entry_array = ledc_timer1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
+	},
+	.timer[2] = {
+		.regdma_entry_array = ledc_timer2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
+	},
+	.timer[3] = {
+		.regdma_entry_array = ledc_timer3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
+	},
+	.channel[0] = {
+		.regdma_entry_array = ledc_channel0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
+	},
+	.channel[1] = {
+		.regdma_entry_array = ledc_channel1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
+	},
+	.channel[2] = {
+		.regdma_entry_array = ledc_channel2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
+	},
+	.channel[3] = {
+		.regdma_entry_array = ledc_channel3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
+	},
+	.channel[4] = {
+		.regdma_entry_array = ledc_channel4_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
+	},
+	.channel[5] = {
+		.regdma_entry_array = ledc_channel5_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
+	},
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};
diff --git a/components/soc/esp32c61/register/soc/.gitkeep b/components/soc/esp32c61/register/soc/.gitkeep
deleted file mode 100644
index e69de29bb2d..00000000000
diff --git a/components/soc/esp32c61/include/soc/ahb_dma_reg.h b/components/soc/esp32c61/register/soc/ahb_dma_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/ahb_dma_reg.h
rename to components/soc/esp32c61/register/soc/ahb_dma_reg.h
diff --git a/components/soc/esp32c61/include/soc/ahb_dma_struct.h b/components/soc/esp32c61/register/soc/ahb_dma_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/ahb_dma_struct.h
rename to components/soc/esp32c61/register/soc/ahb_dma_struct.h
diff --git a/components/soc/esp32c61/include/soc/apb_saradc_reg.h b/components/soc/esp32c61/register/soc/apb_saradc_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/apb_saradc_reg.h
rename to components/soc/esp32c61/register/soc/apb_saradc_reg.h
diff --git a/components/soc/esp32c61/include/soc/apb_saradc_struct.h b/components/soc/esp32c61/register/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/apb_saradc_struct.h
rename to components/soc/esp32c61/register/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32c61/register/soc/assist_debug_reg.h b/components/soc/esp32c61/register/soc/assist_debug_reg.h
new file mode 100644
index 00000000000..042490974ba
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/assist_debug_reg.h
@@ -0,0 +1,824 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to monitor read operations in region 0 by the Data bus. \\
+ *  0: Not monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to monitor write operations in region 0 by the Data bus.\\
+ *  0: Not monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to monitor read operations in region 1 by the Data bus.\\
+ *  0: Not Monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Configures whether to monitor write operations in region 1 by the Data bus.\\
+ *  0: Not Monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
+ *  0: Not Monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
+ *  0: Not Monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
+ *  0: Not Monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
+ *  0: Not Monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to monitor SP exceeding the lower bound address of SP monitored
+ *  region.\\
+ *  0: Not Monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Configures whether to monitor SP exceeding the upper bound address of SP monitored
+ *  region.\\
+ *  0: Not Monitor\\
+ *  1: Monitor\\
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
+ *  IBUS busy monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
+ *  DBUS busy monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status of read operations in region 0 by Data bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status of write operations in region 0 by Data bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status of read operations in region 1 by Data bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status of write operations in region 1 by Data bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status of read operations in region 0 by Peripheral bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status of write operations in region 0 by Peripheral bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status of read operations in region 1 by Peripheral bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status of write operations in region 1 by Peripheral bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status of SP exceeding the lower bound address of SP monitored
+ *  region.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status of SP exceeding the upper bound address of SP monitored
+ *  region.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
+ *  DBUS busy monitor initerrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0;
+ *  DBUS busy monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clear register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 0 by Data bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 0 by Data bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 1 by Data bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 1 by Data bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
+ *  monitored region.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
+ *  monitored region.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
+ *  DBUS busy monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
+ *  Configures lower boundary address of region 0 monitored on Data bus
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Data bus region 0.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
+ *  Configures upper boundary address of region 0 monitored on Data bus
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Data bus region 0.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
+ *  Configures lower boundary address of region 1 monitored on Data bus
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Data bus region 1.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
+ *  Configures upper boundary address of region 1 monitored on Data bus
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Data bus region 1.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
+ *  Configures lower boundary address of region 0 monitored on Peripheral bus
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Peripheral bus region 0.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
+ *  Configures upper boundary address of region 0 monitored on Peripheral bus
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Peripheral bus region 0.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
+ *  Configures lower boundary address of region 1 monitored on Peripheral bus
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Peripheral bus region 1.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
+ *  Configures upper boundary address of region 1 monitored on Peripheral bus
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Peripheral bus region 1.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
+ *  Region monitoring HP CPU PC status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value when an interrupt is triggered during region monitoring.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
+ *  Region monitoring HP CPU SP status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
+/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  Represents the SP value when an interrupt is triggered during region monitoring.
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  Configures stack monitoring lower boundary address
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the lower bound address of SP.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  Configures stack monitoring upper boundary address
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the upper bound address of SP.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  Stack monitoring HP CPU PC status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value during stack monitoring.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  HP CPU PC logging enable register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable PC logging.\\
+ *  0: Disable\\
+ *  1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable HP CPU debugging.\\
+ *  0: Disable\\
+ *  1: HP CPU outputs PC\\
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  PC logging register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value at HP CPU reset.
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  PC logging register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  Represents SP.
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x3FFFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x3FFFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [30]; default: 0;
+ *  reg_core_0_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(30))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  30
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [31]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(31))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  31
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x3FFFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x3FFFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [30]; default: 0;
+ *  reg_core_0_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(30))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  30
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [31]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(31))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  31
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
+ *  reg_core_0_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [4:1]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  1
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x3FFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x3FFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
+ *  reg_core_0_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [4:1]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  1
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x3FFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x3FFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC of the last command before the HP CPU enters exception.
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
+ *  1: In debugging mode\\
+ *  0: Not in debugging mode\\
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  Represents the status of the RISC-V CPU (HP CPU) debug module.\\
+ *  1: Active status\\
+ *  Other: Inactive status\\
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register8
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_0
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register9
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_1
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+/** ASSIST_DEBUG_CLOCK_GATE_REG register
+ *  Register clock control
+ */
+#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
+/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to enable the register clock gating. \\
+ *  0: Disable\\
+ *  1: Enable\\
+ */
+#define ASSIST_DEBUG_CLK_EN    (BIT(0))
+#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
+#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
+#define ASSIST_DEBUG_CLK_EN_S  0
+
+/** ASSIST_DEBUG_DATE_REG register
+ *  Version control register
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
+/** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/assist_debug_struct.h b/components/soc/esp32c61/register/soc/assist_debug_struct.h
new file mode 100644
index 00000000000..ca55d0cb8f6
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/assist_debug_struct.h
@@ -0,0 +1,774 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: monitor configuration registers */
+/** Type of core_0_montr_ena register
+ *  core0 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to monitor read operations in region 0 by the Data bus. \\
+         *  0: Not monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_area_dram0_0_rd_ena:1;
+        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to monitor write operations in region 0 by the Data bus.\\
+         *  0: Not monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_area_dram0_0_wr_ena:1;
+        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to monitor read operations in region 1 by the Data bus.\\
+         *  0: Not Monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_area_dram0_1_rd_ena:1;
+        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Configures whether to monitor write operations in region 1 by the Data bus.\\
+         *  0: Not Monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_area_dram0_1_wr_ena:1;
+        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to monitor read operations in region 0 by the Peripheral bus.\\
+         *  0: Not Monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_area_pif_0_rd_ena:1;
+        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to monitor write operations in region 0 by the Peripheral bus.\\
+         *  0: Not Monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_area_pif_0_wr_ena:1;
+        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to monitor read operations in region 1 by the Peripheral bus.\\
+         *  0: Not Monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_area_pif_1_rd_ena:1;
+        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Configures whether to monitor write operations in region 1 by the Peripheral bus.\\
+         *  0: Not Monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_area_pif_1_wr_ena:1;
+        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to monitor SP exceeding the lower bound address of SP monitored
+         *  region.\\
+         *  0: Not Monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_sp_spill_min_ena:1;
+        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Configures whether to monitor SP exceeding the upper bound address of SP monitored
+         *  region.\\
+         *  0: Not Monitor\\
+         *  1: Monitor\\
+         */
+        uint32_t core_0_sp_spill_max_ena:1;
+        /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
+         *  IBUS busy monitor enable
+         */
+        uint32_t core_0_iram0_exception_monitor_ena:1;
+        /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
+         *  DBUS busy monitor enable
+         */
+        uint32_t core_0_dram0_exception_monitor_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_montr_ena_reg_t;
+
+/** Type of core_0_area_dram0_0_min register
+ *  Configures lower boundary address of region 0 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Data bus region 0.
+         */
+        uint32_t core_0_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_min_reg_t;
+
+/** Type of core_0_area_dram0_0_max register
+ *  Configures upper boundary address of region 0 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Data bus region 0.
+         */
+        uint32_t core_0_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_max_reg_t;
+
+/** Type of core_0_area_dram0_1_min register
+ *  Configures lower boundary address of region 1 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Data bus region 1.
+         */
+        uint32_t core_0_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_min_reg_t;
+
+/** Type of core_0_area_dram0_1_max register
+ *  Configures upper boundary address of region 1 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Data bus region 1.
+         */
+        uint32_t core_0_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_max_reg_t;
+
+/** Type of core_0_area_pif_0_min register
+ *  Configures lower boundary address of region 0 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Peripheral bus region 0.
+         */
+        uint32_t core_0_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_min_reg_t;
+
+/** Type of core_0_area_pif_0_max register
+ *  Configures upper boundary address of region 0 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Peripheral bus region 0.
+         */
+        uint32_t core_0_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_max_reg_t;
+
+/** Type of core_0_area_pif_1_min register
+ *  Configures lower boundary address of region 1 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Peripheral bus region 1.
+         */
+        uint32_t core_0_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_min_reg_t;
+
+/** Type of core_0_area_pif_1_max register
+ *  Configures upper boundary address of region 1 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Peripheral bus region 1.
+         */
+        uint32_t core_0_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_max_reg_t;
+
+/** Type of core_0_area_pc register
+ *  Region monitoring HP CPU PC status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value when an interrupt is triggered during region monitoring.
+         */
+        uint32_t core_0_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pc_reg_t;
+
+/** Type of core_0_area_sp register
+ *  Region monitoring HP CPU SP status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  Represents the SP value when an interrupt is triggered during region monitoring.
+         */
+        uint32_t core_0_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_sp_reg_t;
+
+/** Type of core_0_sp_min register
+ *  Configures stack monitoring lower boundary address
+ */
+typedef union {
+    struct {
+        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the lower bound address of SP.
+         */
+        uint32_t core_0_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_min_reg_t;
+
+/** Type of core_0_sp_max register
+ *  Configures stack monitoring upper boundary address
+ */
+typedef union {
+    struct {
+        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the upper bound address of SP.
+         */
+        uint32_t core_0_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_max_reg_t;
+
+/** Type of core_0_sp_pc register
+ *  Stack monitoring HP CPU PC status register
+ */
+typedef union {
+    struct {
+        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value during stack monitoring.
+         */
+        uint32_t core_0_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_pc_reg_t;
+
+
+/** Group: interrupt configuration register */
+/** Type of core_0_intr_raw register
+ *  core0 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status of read operations in region 0 by Data bus.
+         */
+        uint32_t core_0_area_dram0_0_rd_raw:1;
+        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status of write operations in region 0 by Data bus.
+         */
+        uint32_t core_0_area_dram0_0_wr_raw:1;
+        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status of read operations in region 1 by Data bus.
+         */
+        uint32_t core_0_area_dram0_1_rd_raw:1;
+        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status of write operations in region 1 by Data bus.
+         */
+        uint32_t core_0_area_dram0_1_wr_raw:1;
+        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status of read operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_0_rd_raw:1;
+        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status of write operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_0_wr_raw:1;
+        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status of read operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_1_rd_raw:1;
+        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status of write operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_1_wr_raw:1;
+        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status of SP exceeding the lower bound address of SP monitored
+         *  region.
+         */
+        uint32_t core_0_sp_spill_min_raw:1;
+        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status of SP exceeding the upper bound address of SP monitored
+         *  region.
+         */
+        uint32_t core_0_sp_spill_max_raw:1;
+        /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt status
+         */
+        uint32_t core_0_iram0_exception_monitor_raw:1;
+        /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
+         *  DBUS busy monitor initerrupt status
+         */
+        uint32_t core_0_dram0_exception_monitor_raw:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_raw_reg_t;
+
+/** Type of core_0_intr_ena register
+ *  core0 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_rd_intr_ena:1;
+        /** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_wr_intr_ena:1;
+        /** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_rd_intr_ena:1;
+        /** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_wr_intr_ena:1;
+        /** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_rd_intr_ena:1;
+        /** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_wr_intr_ena:1;
+        /** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_rd_intr_ena:1;
+        /** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_wr_intr_ena:1;
+        /** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_min_intr_ena:1;
+        /** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_max_intr_ena:1;
+        /** core_0_iram0_exception_monitor_intr_ena : R/W; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt enable
+         */
+        uint32_t core_0_iram0_exception_monitor_intr_ena:1;
+        /** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0;
+         *  DBUS busy monitor interrupt enable
+         */
+        uint32_t core_0_dram0_exception_monitor_intr_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_ena_reg_t;
+
+/** Type of core_0_intr_clr register
+ *  core0 monitor interrupt clear register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 0 by Data bus.
+         */
+        uint32_t core_0_area_dram0_0_rd_clr:1;
+        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 0 by Data bus.
+         */
+        uint32_t core_0_area_dram0_0_wr_clr:1;
+        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 1 by Data bus.
+         */
+        uint32_t core_0_area_dram0_1_rd_clr:1;
+        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 1 by Data bus.
+         */
+        uint32_t core_0_area_dram0_1_wr_clr:1;
+        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_0_rd_clr:1;
+        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_0_wr_clr:1;
+        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_1_rd_clr:1;
+        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_1_wr_clr:1;
+        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
+         *  monitored region.
+         */
+        uint32_t core_0_sp_spill_min_clr:1;
+        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
+         *  monitored region.
+         */
+        uint32_t core_0_sp_spill_max_clr:1;
+        /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt clr
+         */
+        uint32_t core_0_iram0_exception_monitor_clr:1;
+        /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
+         *  DBUS busy monitor interrupt clr
+         */
+        uint32_t core_0_dram0_exception_monitor_clr:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_clr_reg_t;
+
+
+/** Group: pc recording configuration register */
+/** Type of core_0_rcd_en register
+ *  HP CPU PC logging enable register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable PC logging.\\
+         *  0: Disable\\
+         *  1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\
+         */
+        uint32_t core_0_rcd_recorden:1;
+        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable HP CPU debugging.\\
+         *  0: Disable\\
+         *  1: HP CPU outputs PC\\
+         */
+        uint32_t core_0_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_en_reg_t;
+
+
+/** Group: pc recording status register */
+/** Type of core_0_rcd_pdebugpc register
+ *  PC logging register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value at HP CPU reset.
+         */
+        uint32_t core_0_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugpc_reg_t;
+
+/** Type of core_0_rcd_pdebugsp register
+ *  PC logging register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  Represents SP.
+         */
+        uint32_t core_0_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugsp_reg_t;
+
+
+/** Group: exception monitor register */
+/** Type of core_0_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_0
+         */
+        uint32_t core_0_iram0_recording_addr_0:30;
+        /** core_0_iram0_recording_wr_0 : RO; bitpos: [30]; default: 0;
+         *  reg_core_0_iram0_recording_wr_0
+         */
+        uint32_t core_0_iram0_recording_wr_0:1;
+        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [31]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_0
+         */
+        uint32_t core_0_iram0_recording_loadstore_0:1;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_1
+         */
+        uint32_t core_0_iram0_recording_addr_1:30;
+        /** core_0_iram0_recording_wr_1 : RO; bitpos: [30]; default: 0;
+         *  reg_core_0_iram0_recording_wr_1
+         */
+        uint32_t core_0_iram0_recording_wr_1:1;
+        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [31]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_1
+         */
+        uint32_t core_0_iram0_recording_loadstore_1:1;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
+         *  reg_core_0_dram0_recording_wr_0
+         */
+        uint32_t core_0_dram0_recording_wr_0:1;
+        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [4:1]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_0
+         */
+        uint32_t core_0_dram0_recording_byteen_0:4;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_0 : RO; bitpos: [29:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_0
+         */
+        uint32_t core_0_dram0_recording_addr_0:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_0
+         */
+        uint32_t core_0_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
+         *  reg_core_0_dram0_recording_wr_1
+         */
+        uint32_t core_0_dram0_recording_wr_1:1;
+        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [4:1]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_1
+         */
+        uint32_t core_0_dram0_recording_byteen_1:4;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_4 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_1 : RO; bitpos: [29:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_1
+         */
+        uint32_t core_0_dram0_recording_addr_1:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_5 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_1
+         */
+        uint32_t core_0_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_0 register
+ *  exception monitor status register8
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_0
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_1 register
+ *  exception monitor status register9
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_1
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
+
+
+/** Group: cpu status registers */
+/** Type of core_0_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC of the last command before the HP CPU enters exception.
+         */
+        uint32_t core_0_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_lastpc_before_exception_reg_t;
+
+/** Type of core_0_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\
+         *  1: In debugging mode\\
+         *  0: Not in debugging mode\\
+         */
+        uint32_t core_0_debug_mode:1;
+        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  Represents the status of the RISC-V CPU (HP CPU) debug module.\\
+         *  1: Active status\\
+         *  Other: Inactive status\\
+         */
+        uint32_t core_0_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_debug_mode_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clock_gate register
+ *  Register clock control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to enable the register clock gating. \\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} assist_debug_clock_gate_reg_t;
+
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 34640176;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} assist_debug_date_reg_t;
+
+
+typedef struct {
+    volatile assist_debug_core_0_montr_ena_reg_t core_0_montr_ena;
+    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
+    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
+    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
+    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
+    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
+    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
+    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
+    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
+    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
+    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
+    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
+    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
+    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
+    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
+    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
+    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
+    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
+    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
+    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
+    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
+    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
+    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
+    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
+    volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
+    volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
+    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
+    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
+    uint32_t reserved_078[34];
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
+    volatile assist_debug_clock_gate_reg_t clock_gate;
+    uint32_t reserved_10c[188];
+    volatile assist_debug_date_reg_t date;
+} assist_debug_dev_t;
+
+extern assist_debug_dev_t ASSIST_DEBUG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/cache_reg.h b/components/soc/esp32c61/register/soc/cache_reg.h
new file mode 100644
index 00000000000..d0e294a28cb
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/cache_reg.h
@@ -0,0 +1,6166 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CACHE_L1_ICACHE_CTRL_REG register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
+/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
+#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
+/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
+#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
+/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
+#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
+/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
+#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
+/** CACHE_L1_ICACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_UNDEF_OP    0x000000FFU
+#define CACHE_L1_ICACHE_UNDEF_OP_M  (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S)
+#define CACHE_L1_ICACHE_UNDEF_OP_V  0x000000FFU
+#define CACHE_L1_ICACHE_UNDEF_OP_S  8
+
+/** CACHE_L1_CACHE_CTRL_REG register
+ *  L1 data Cache(L1-Cache) control register
+ */
+#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
+/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L1_CACHE_SHUT_BUS0    (BIT(0))
+#define CACHE_L1_CACHE_SHUT_BUS0_M  (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S)
+#define CACHE_L1_CACHE_SHUT_BUS0_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_BUS0_S  0
+/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L1_CACHE_SHUT_BUS1    (BIT(1))
+#define CACHE_L1_CACHE_SHUT_BUS1_M  (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S)
+#define CACHE_L1_CACHE_SHUT_BUS1_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_BUS1_S  1
+/** CACHE_L1_CACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_CACHE_SHUT_DBUS2    (BIT(2))
+#define CACHE_L1_CACHE_SHUT_DBUS2_M  (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S)
+#define CACHE_L1_CACHE_SHUT_DBUS2_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_DBUS2_S  2
+/** CACHE_L1_CACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_CACHE_SHUT_DBUS3    (BIT(3))
+#define CACHE_L1_CACHE_SHUT_DBUS3_M  (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S)
+#define CACHE_L1_CACHE_SHUT_DBUS3_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_DBUS3_S  3
+/** CACHE_L1_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L1_CACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L1_CACHE_SHUT_DMA_M  (CACHE_L1_CACHE_SHUT_DMA_V << CACHE_L1_CACHE_SHUT_DMA_S)
+#define CACHE_L1_CACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_DMA_S  4
+/** CACHE_L1_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_CACHE_UNDEF_OP    0x000000FFU
+#define CACHE_L1_CACHE_UNDEF_OP_M  (CACHE_L1_CACHE_UNDEF_OP_V << CACHE_L1_CACHE_UNDEF_OP_S)
+#define CACHE_L1_CACHE_UNDEF_OP_V  0x000000FFU
+#define CACHE_L1_CACHE_UNDEF_OP_S  8
+
+/** CACHE_L1_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
+/** CACHE_BYPASS_L1_ICACHE0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
+#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
+#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
+/** CACHE_BYPASS_L1_ICACHE1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
+#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
+#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
+/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
+#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
+#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
+/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
+#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
+#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
+/** CACHE_BYPASS_L1_DCACHE_EN : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
+#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
+#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_DCACHE_EN_S  4
+
+/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
+ *  L1 Cache atomic feature configure register
+ */
+#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
+/** CACHE_L1_CACHE_ATOMIC_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
+ *  L1-Cache.  1: disable, 1: enable.
+ */
+#define CACHE_L1_CACHE_ATOMIC_EN    (BIT(0))
+#define CACHE_L1_CACHE_ATOMIC_EN_M  (CACHE_L1_CACHE_ATOMIC_EN_V << CACHE_L1_CACHE_ATOMIC_EN_S)
+#define CACHE_L1_CACHE_ATOMIC_EN_V  0x00000001U
+#define CACHE_L1_CACHE_ATOMIC_EN_S  0
+
+/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
+/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_ICACHE_CACHESIZE_256_M  (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256_S  0
+/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_ICACHE_CACHESIZE_512_M  (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512_S  1
+/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
+/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_CACHE_CACHESIZE_CONF_REG register
+ *  L1 data Cache CacheSize mode configure register
+ */
+#define CACHE_L1_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
+/** CACHE_L1_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_CACHE_CACHESIZE_256_M  (CACHE_L1_CACHE_CACHESIZE_256_V << CACHE_L1_CACHE_CACHESIZE_256_S)
+#define CACHE_L1_CACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_256_S  0
+/** CACHE_L1_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_CACHE_CACHESIZE_512_M  (CACHE_L1_CACHE_CACHESIZE_512_V << CACHE_L1_CACHE_CACHESIZE_512_S)
+#define CACHE_L1_CACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_512_S  1
+/** CACHE_L1_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_CACHE_CACHESIZE_1K_M  (CACHE_L1_CACHE_CACHESIZE_1K_V << CACHE_L1_CACHE_CACHESIZE_1K_S)
+#define CACHE_L1_CACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_CACHE_CACHESIZE_2K_M  (CACHE_L1_CACHE_CACHESIZE_2K_V << CACHE_L1_CACHE_CACHESIZE_2K_S)
+#define CACHE_L1_CACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_CACHE_CACHESIZE_4K_M  (CACHE_L1_CACHE_CACHESIZE_4K_V << CACHE_L1_CACHE_CACHESIZE_4K_S)
+#define CACHE_L1_CACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_CACHE_CACHESIZE_8K_M  (CACHE_L1_CACHE_CACHESIZE_8K_V << CACHE_L1_CACHE_CACHESIZE_8K_S)
+#define CACHE_L1_CACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_CACHE_CACHESIZE_16K_M  (CACHE_L1_CACHE_CACHESIZE_16K_V << CACHE_L1_CACHE_CACHESIZE_16K_S)
+#define CACHE_L1_CACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 1;
+ *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_CACHE_CACHESIZE_32K_M  (CACHE_L1_CACHE_CACHESIZE_32K_V << CACHE_L1_CACHE_CACHESIZE_32K_S)
+#define CACHE_L1_CACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_CACHE_CACHESIZE_64K_M  (CACHE_L1_CACHE_CACHESIZE_64K_V << CACHE_L1_CACHE_CACHESIZE_64K_S)
+#define CACHE_L1_CACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_CACHE_CACHESIZE_128K_M  (CACHE_L1_CACHE_CACHESIZE_128K_V << CACHE_L1_CACHE_CACHESIZE_128K_S)
+#define CACHE_L1_CACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_CACHE_CACHESIZE_256K_M  (CACHE_L1_CACHE_CACHESIZE_256K_V << CACHE_L1_CACHE_CACHESIZE_256K_S)
+#define CACHE_L1_CACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_CACHE_CACHESIZE_512K_M  (CACHE_L1_CACHE_CACHESIZE_512K_V << CACHE_L1_CACHE_CACHESIZE_512K_S)
+#define CACHE_L1_CACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_CACHE_CACHESIZE_1024K_M  (CACHE_L1_CACHE_CACHESIZE_1024K_V << CACHE_L1_CACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_CACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_CACHE_BLOCKSIZE_CONF_REG register
+ *  L1 data Cache BlockSize mode configure register
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
+/** CACHE_L1_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_CACHE_BLOCKSIZE_8_M  (CACHE_L1_CACHE_BLOCKSIZE_8_V << CACHE_L1_CACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_CACHE_BLOCKSIZE_16_M  (CACHE_L1_CACHE_BLOCKSIZE_16_V << CACHE_L1_CACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 1;
+ *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_CACHE_BLOCKSIZE_32_M  (CACHE_L1_CACHE_BLOCKSIZE_32_V << CACHE_L1_CACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_CACHE_BLOCKSIZE_64_M  (CACHE_L1_CACHE_BLOCKSIZE_64_V << CACHE_L1_CACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_CACHE_BLOCKSIZE_128_M  (CACHE_L1_CACHE_BLOCKSIZE_128_V << CACHE_L1_CACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_CACHE_BLOCKSIZE_256_M  (CACHE_L1_CACHE_BLOCKSIZE_256_V << CACHE_L1_CACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
+/** CACHE_L1_ICACHE0_WRAP : HRO; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+ */
+#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
+#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
+#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE0_WRAP_S  0
+/** CACHE_L1_ICACHE1_WRAP : HRO; bitpos: [1]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+ */
+#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
+#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
+#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE1_WRAP_S  1
+/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
+#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
+#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE2_WRAP_S  2
+/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
+#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
+#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE3_WRAP_S  3
+/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0;
+ *  Set this bit as 1 to enable L1-DCache wrap around mode.
+ */
+#define CACHE_L1_CACHE_WRAP    (BIT(4))
+#define CACHE_L1_CACHE_WRAP_M  (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S)
+#define CACHE_L1_CACHE_WRAP_V  0x00000001U
+#define CACHE_L1_CACHE_WRAP_S  4
+
+/** CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
+/** CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS : HRO; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to disable early restart of  L1-ICache0
+ */
+#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS    (BIT(0))
+#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S  0
+/** CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS : HRO; bitpos: [1]; default: 0;
+ *  Set this bit as 1 to disable early restart of  L1-ICache1
+ */
+#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS    (BIT(1))
+#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S  1
+/** CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS    (BIT(2))
+#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S  2
+/** CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS    (BIT(3))
+#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S  3
+/** CACHE_L1_CACHE_MISS_DISABLE_ACCESS : R/W; bitpos: [4]; default: 0;
+ *  Set this bit as 1 to disable early restart of L1-DCache
+ */
+#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS    (BIT(4))
+#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_M  (CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S  4
+
+/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
+/** CACHE_L1_ICACHE0_FREEZE_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
+#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
+/** CACHE_L1_ICACHE0_FREEZE_MODE : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
+#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
+/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
+#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
+/** CACHE_L1_ICACHE1_FREEZE_EN : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
+#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
+/** CACHE_L1_ICACHE1_FREEZE_MODE : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
+#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
+/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
+#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
+/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
+#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
+/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
+#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
+/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
+#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
+/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
+#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
+/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
+#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
+/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
+#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
+/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
+ *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_CACHE_FREEZE_EN    (BIT(16))
+#define CACHE_L1_CACHE_FREEZE_EN_M  (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S)
+#define CACHE_L1_CACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_CACHE_FREEZE_EN_S  16
+/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_CACHE_FREEZE_MODE    (BIT(17))
+#define CACHE_L1_CACHE_FREEZE_MODE_M  (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S)
+#define CACHE_L1_CACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_CACHE_FREEZE_MODE_S  17
+/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_CACHE_FREEZE_DONE    (BIT(18))
+#define CACHE_L1_CACHE_FREEZE_DONE_M  (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S)
+#define CACHE_L1_CACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_CACHE_FREEZE_DONE_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x2c)
+/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
+/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 0;
+ *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M  (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S  16
+/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M  (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S  17
+
+/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
+/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
+/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 0;
+ *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M  (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S  16
+/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M  (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S  17
+
+/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x34)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE0_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 prelock.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x38)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section of prelock
+ *  on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x3c)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section of prelock
+ *  on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x40)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x44)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE1_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 prelock.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x48)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section of prelock
+ *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x4c)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section of prelock
+ *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x50)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x54)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 prelock.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x58)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section of prelock
+ *  on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x5c)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section of prelock
+ *  on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x60)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x64)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 prelock.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x68)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section of prelock
+ *  on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x6c)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section of prelock
+ *  on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x70)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_CACHE_PRELOCK_CONF_REG register
+ *  L1 Cache prelock configure register
+ */
+#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x74)
+/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-Cache.
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-Cache.
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 cache prelock.
+ */
+#define CACHE_L1_CACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_CACHE_PRELOCK_RGID_M  (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S)
+#define CACHE_L1_CACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_CACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L1 Cache prelock section0 address configure register
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x78)
+/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section of prelock
+ *  on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L1 Cache prelock section1 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
+/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section of prelock
+ *  on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
+ *  L1  Cache prelock section size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x80)
+/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_LOCK_CTRL_REG register
+ *  Lock-class (manual lock) operation control register
+ */
+#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x84)
+/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+ *  operation done
+ */
+#define CACHE_LOCK_ENA    (BIT(0))
+#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
+#define CACHE_LOCK_ENA_V  0x00000001U
+#define CACHE_LOCK_ENA_S  0
+/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable unlock operation. It will be cleared by hardware after
+ *  unlock operation done
+ */
+#define CACHE_UNLOCK_ENA    (BIT(1))
+#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
+#define CACHE_UNLOCK_ENA_V  0x00000001U
+#define CACHE_UNLOCK_ENA_S  1
+/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
+ *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+ *  not finished. 1: finished.
+ */
+#define CACHE_LOCK_DONE    (BIT(2))
+#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
+#define CACHE_LOCK_DONE_V  0x00000001U
+#define CACHE_LOCK_DONE_S  2
+/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of cache lock/unlock.
+ */
+#define CACHE_LOCK_RGID    0x0000000FU
+#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
+#define CACHE_LOCK_RGID_V  0x0000000FU
+#define CACHE_LOCK_RGID_S  3
+
+/** CACHE_LOCK_MAP_REG register
+ *  Lock (manual lock) map configure register
+ */
+#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x88)
+/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply this lock/unlock operation. [4]: L1-Cache
+ */
+#define CACHE_LOCK_MAP    0x0000003FU
+#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
+#define CACHE_LOCK_MAP_V  0x0000003FU
+#define CACHE_LOCK_MAP_S  0
+
+/** CACHE_LOCK_ADDR_REG register
+ *  Lock (manual lock) address configure register
+ */
+#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x8c)
+/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the lock/unlock operation,
+ *  which should be used together with CACHE_LOCK_SIZE_REG
+ */
+#define CACHE_LOCK_ADDR    0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
+#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_S  0
+
+/** CACHE_LOCK_SIZE_REG register
+ *  Lock (manual lock) size configure register
+ */
+#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x90)
+/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the lock/unlock operation, which
+ *  should be used together with CACHE_LOCK_ADDR_REG
+ */
+#define CACHE_LOCK_SIZE    0x0000FFFFU
+#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
+#define CACHE_LOCK_SIZE_V  0x0000FFFFU
+#define CACHE_LOCK_SIZE_S  0
+
+/** CACHE_SYNC_CTRL_REG register
+ *  Sync-class operation control register
+ */
+#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x94)
+/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
+ *  The bit is used to enable invalidate operation. It will be cleared by hardware
+ *  after invalidate operation done. Note that this bit and the other sync-bits
+ *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_INVALIDATE_ENA    (BIT(0))
+#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
+#define CACHE_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_INVALIDATE_ENA_S  0
+/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable clean operation. It will be cleared by hardware after
+ *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+ *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+ *  bits can not be set to 1 at the same time.
+ */
+#define CACHE_CLEAN_ENA    (BIT(1))
+#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
+#define CACHE_CLEAN_ENA_V  0x00000001U
+#define CACHE_CLEAN_ENA_S  1
+/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
+ *  The bit is used to enable writeback operation. It will be cleared by hardware after
+ *  writeback operation done. Note that this bit and the other sync-bits
+ *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_ENA    (BIT(2))
+#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
+#define CACHE_WRITEBACK_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_ENA_S  2
+/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
+ *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+ *  hardware after writeback-invalidate operation done. Note that this bit and the
+ *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+ *  that is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
+#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
+ *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+ *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+ */
+#define CACHE_SYNC_DONE    (BIT(4))
+#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
+#define CACHE_SYNC_DONE_V  0x00000001U
+#define CACHE_SYNC_DONE_S  4
+/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0;
+ *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+ *  writeback, writeback_invalidate)
+ */
+#define CACHE_SYNC_RGID    0x0000000FU
+#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
+#define CACHE_SYNC_RGID_V  0x0000000FU
+#define CACHE_SYNC_RGID_S  5
+
+/** CACHE_SYNC_MAP_REG register
+ *  Sync map configure register
+ */
+#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x98)
+/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply the sync operation.  [4]: L1-Cache
+ */
+#define CACHE_SYNC_MAP    0x0000003FU
+#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
+#define CACHE_SYNC_MAP_V  0x0000003FU
+#define CACHE_SYNC_MAP_S  0
+
+/** CACHE_SYNC_ADDR_REG register
+ *  Sync address configure register
+ */
+#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0x9c)
+/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the sync operation, which
+ *  should be used together with CACHE_SYNC_SIZE_REG
+ */
+#define CACHE_SYNC_ADDR    0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
+#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_S  0
+
+/** CACHE_SYNC_SIZE_REG register
+ *  Sync size configure register
+ */
+#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa0)
+/** CACHE_SYNC_SIZE : R/W; bitpos: [24:0]; default: 0;
+ *  Those bits are used to configure the size of the sync operation, which should be
+ *  used together with CACHE_SYNC_ADDR_REG
+ */
+#define CACHE_SYNC_SIZE    0x01FFFFFFU
+#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
+#define CACHE_SYNC_SIZE_V  0x01FFFFFFU
+#define CACHE_SYNC_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa4)
+/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 preload.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xa8)
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of preload on L1-ICache0, which
+ *  should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xac)
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb0)
+/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 preload.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb4)
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of preload on L1-ICache1, which
+ *  should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb8)
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xbc)
+/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 preload.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc0)
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of preload on L1-ICache2, which
+ *  should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc4)
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc8)
+/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 preload.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xcc)
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of preload on L1-ICache3, which
+ *  should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd0)
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register
+ *  L1 Cache  preload-operation control register
+ */
+#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd4)
+/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_CACHE_PRELOAD_ENA_M  (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S)
+#define CACHE_L1_CACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOAD_ENA_S  0
+/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_CACHE_PRELOAD_DONE_M  (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S)
+#define CACHE_L1_CACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOAD_DONE_S  1
+/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_CACHE_PRELOAD_ORDER_M  (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S)
+#define CACHE_L1_CACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOAD_ORDER_S  2
+/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 cache preload.
+ */
+#define CACHE_L1_CACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_CACHE_PRELOAD_RGID_M  (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S)
+#define CACHE_L1_CACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_CACHE_PRELOAD_RGID_S  3
+
+/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
+ *  L1 Cache  preload address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd8)
+/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of preload on L1-Cache, which
+ *  should be used together with L1_CACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOAD_ADDR_M  (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S)
+#define CACHE_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
+ *  L1 Cache  preload size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xdc)
+/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_CACHE_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_CACHE_PRELOAD_SIZE_M  (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S)
+#define CACHE_L1_CACHE_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_CACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe0)
+/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 autoload.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section for
+ *  autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xe8)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xec)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section for
+ *  autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf0)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf4)
+/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 autoload.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xf8)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section for
+ *  autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xfc)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x100)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section for
+ *  autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x104)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x108)
+/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 autoload.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x10c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section for
+ *  autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x110)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x114)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section for
+ *  autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x118)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x11c)
+/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 autoload.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x120)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section for
+ *  autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x124)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x128)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section for
+ *  autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x12c)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register
+ *  L1 Cache autoload-operation control register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x130)
+/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_M  (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M  (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
+ *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-Cache.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-Cache.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L1-Cache.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L1_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l1 cache autoload.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_CACHE_AUTOLOAD_RGID_M  (CACHE_L1_CACHE_AUTOLOAD_RGID_V << CACHE_L1_CACHE_AUTOLOAD_RGID_S)
+#define CACHE_L1_CACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_CACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 Cache autoload section 0 address configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x134)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section for
+ *  autoload operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 Cache autoload section 0 size configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x138)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [24:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x01FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0x01FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x13c)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section for
+ *  autoload operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x140)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [24:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x01FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0x01FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L1 Cache autoload section 2 address configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x144)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the third section for
+ *  autoload operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L1 Cache autoload section 2 size configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x148)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [24:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE    0x01FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V  0x01FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L1 Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x14c)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the fourth section for
+ *  autoload operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L1 Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x150)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [24:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE    0x01FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V  0x01FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x154)
+/** CACHE_L1_IBUS0_OVF_INT_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
+/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS0_OVF_INT_ENA    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_ENA_M  (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S)
+#define CACHE_L1_BUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_BUS0_OVF_INT_ENA_S  4
+/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS1_OVF_INT_ENA    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_ENA_M  (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S)
+#define CACHE_L1_BUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_BUS1_OVF_INT_ENA_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x158)
+/** CACHE_L1_IBUS0_OVF_INT_CLR : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+ *  to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
+/** CACHE_L1_IBUS1_OVF_INT_CLR : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+ *  to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
+/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
+/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
+/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS0_OVF_INT_CLR    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_CLR_M  (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S)
+#define CACHE_L1_BUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_BUS0_OVF_INT_CLR_S  4
+/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS1_OVF_INT_CLR    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_CLR_M  (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S)
+#define CACHE_L1_BUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_BUS1_OVF_INT_CLR_S  5
+/** CACHE_L1_DBUS2_OVF_INT_CLR : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
+/** CACHE_L1_DBUS3_OVF_INT_CLR : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x15c)
+/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+ *  due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
+/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+ *  due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
+/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+ *  due to bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
+/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+ *  due to bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
+/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS0_OVF_INT_RAW    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_RAW_M  (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S)
+#define CACHE_L1_BUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_BUS0_OVF_INT_RAW_S  4
+/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS1_OVF_INT_RAW    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_RAW_M  (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S)
+#define CACHE_L1_BUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_BUS1_OVF_INT_RAW_S  5
+/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
+/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x160)
+/** CACHE_L1_IBUS0_OVF_INT_ST : HRO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
+#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
+#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
+#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
+#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
+/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS0_OVF_INT_ST    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_ST_M  (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S)
+#define CACHE_L1_BUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_BUS0_OVF_INT_ST_S  4
+/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS1_OVF_INT_ST    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_ST_M  (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S)
+#define CACHE_L1_BUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_BUS1_OVF_INT_ST_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
+#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
+#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
+
+/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x164)
+/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S  0
+/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE    (BIT(1))
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S  1
+/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE    (BIT(2))
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S  2
+/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : HRO; bitpos: [3]; default: 0;
+ *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE    (BIT(3))
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S  3
+/** CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to configure l1 cache access fail check mode. 0: the access fail is
+ *  not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE    (BIT(4))
+#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_CACHE_ACS_FAIL_CHECK_MODE_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168)
+/** CACHE_L1_ICACHE0_FAIL_INT_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
+/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_CACHE_FAIL_INT_ENA    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_ENA_M  (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S)
+#define CACHE_L1_CACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_FAIL_INT_ENA_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16c)
+/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
+/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_CACHE_FAIL_INT_CLR    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_CLR_M  (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S)
+#define CACHE_L1_CACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_FAIL_INT_CLR_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170)
+/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
+/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+ */
+#define CACHE_L1_CACHE_FAIL_INT_RAW    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_RAW_M  (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S)
+#define CACHE_L1_CACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_CACHE_FAIL_INT_RAW_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174)
+/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
+/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+ *  to cpu accesses L1-DCache.
+ */
+#define CACHE_L1_CACHE_FAIL_INT_ST    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_ST_M  (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S)
+#define CACHE_L1_CACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_CACHE_FAIL_INT_ST_S  4
+
+/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178)
+/** CACHE_L1_IBUS0_CNT_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
+#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_ENA_S  0
+/** CACHE_L1_IBUS1_CNT_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
+#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_ENA_S  1
+/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
+#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_ENA_S  2
+/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
+#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_ENA_S  3
+/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_BUS0_CNT_ENA    (BIT(4))
+#define CACHE_L1_BUS0_CNT_ENA_M  (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S)
+#define CACHE_L1_BUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_BUS0_CNT_ENA_S  4
+/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_BUS1_CNT_ENA    (BIT(5))
+#define CACHE_L1_BUS1_CNT_ENA_M  (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S)
+#define CACHE_L1_BUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_BUS1_CNT_ENA_S  5
+/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
+#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_ENA_S  6
+/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
+#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_ENA_S  7
+/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0;
+ *  The bit is used to clear ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
+#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
+#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_CLR_S  16
+/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0;
+ *  The bit is used to clear ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
+#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
+#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_CLR_S  17
+/** CACHE_L1_IBUS2_CNT_CLR : WT; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
+#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
+#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_CLR_S  18
+/** CACHE_L1_IBUS3_CNT_CLR : WT; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
+#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
+#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_CLR_S  19
+/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
+ *  The bit is used to clear dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_BUS0_CNT_CLR    (BIT(20))
+#define CACHE_L1_BUS0_CNT_CLR_M  (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S)
+#define CACHE_L1_BUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_BUS0_CNT_CLR_S  20
+/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
+ *  The bit is used to clear dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_BUS1_CNT_CLR    (BIT(21))
+#define CACHE_L1_BUS1_CNT_CLR_M  (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S)
+#define CACHE_L1_BUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_BUS1_CNT_CLR_S  21
+/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
+#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
+#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_CLR_S  22
+/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
+#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
+#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_CLR_S  23
+
+/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x17c)
+/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
+#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x180)
+/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
+#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x184)
+/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x188)
+/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
+/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
+#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x190)
+/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
+#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x194)
+/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x198)
+/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
+/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
+#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
+/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
+#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
+/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
+/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
+/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
+#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
+/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
+#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
+/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
+/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register
+ *  L1-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
+/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_HIT_CNT_M  (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S)
+#define CACHE_L1_BUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_HIT_CNT_S  0
+
+/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register
+ *  L1-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
+/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_MISS_CNT_M  (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S)
+#define CACHE_L1_BUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_MISS_CNT_S  0
+
+/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
+/** CACHE_L1_BUS0_CONFLICT_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS0_CONFLICT_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_CONFLICT_RD_CNT_M  (CACHE_L1_BUS0_CONFLICT_RD_CNT_V << CACHE_L1_BUS0_CONFLICT_RD_CNT_S)
+#define CACHE_L1_BUS0_CONFLICT_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_CONFLICT_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
+/** CACHE_L1_BUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-Cache accesses L2-Cache due to
+ *  bus0 accessing L1-Cache.
+ */
+#define CACHE_L1_BUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_NXTLVL_RD_CNT_M  (CACHE_L1_BUS0_NXTLVL_RD_CNT_V << CACHE_L1_BUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_BUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
+/** CACHE_L1_BUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_NXTLVL_WR_CNT_M  (CACHE_L1_BUS0_NXTLVL_WR_CNT_V << CACHE_L1_BUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L1_BUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register
+ *  L1-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
+/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS1_HIT_CNT_M  (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S)
+#define CACHE_L1_BUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS1_HIT_CNT_S  0
+
+/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register
+ *  L1-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
+/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS1_MISS_CNT_M  (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S)
+#define CACHE_L1_BUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS1_MISS_CNT_S  0
+
+/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
+/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS1_CONFLICT_CNT_M  (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S)
+#define CACHE_L1_BUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
+/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-Cache accesses L2-Cache due to
+ *  bus1 accessing L1-Cache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
+/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus1 accesses L1-Cache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
+/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
+#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
+/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
+#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
+/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
+/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-Cache accesses L2-Cache due to
+ *  bus2 accessing L1-Cache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
+/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus2 accesses L1-Cache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
+/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
+#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1fc)
+/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
+#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x200)
+/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x204)
+/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-Cache accesses L2-Cache due to
+ *  bus3 accessing L1-Cache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x208)
+/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-Cache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x20c)
+/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
+#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_S  0
+/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x210)
+/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214)
+/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
+#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_S  0
+/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218)
+/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c)
+/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
+#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_S  0
+/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220)
+/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x224)
+/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
+#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_S  0
+/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x228)
+/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L1-Cache Access Fail ID/attribution information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x22c)
+/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache accesses L1-Cache.
+ */
+#define CACHE_L1_CACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_CACHE_FAIL_ID_M  (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S)
+#define CACHE_L1_CACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_CACHE_FAIL_ID_S  0
+/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache accesses L1-Cache.
+ */
+#define CACHE_L1_CACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_CACHE_FAIL_ATTR_M  (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S)
+#define CACHE_L1_CACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_CACHE_FAIL_ATTR_S  16
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
+ *  L1-Cache Access Fail Address information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x230)
+/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache accesses L1-Cache.
+ */
+#define CACHE_L1_CACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_FAIL_ADDR_M  (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S)
+#define CACHE_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_FAIL_ADDR_S  0
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x234)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
+/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S  4
+/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation done.
+ */
+#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
+#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ENA_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : HRO; bitpos: [7]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
+/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable interrupt of L1-Cache preload-operation error.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S  11
+/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
+#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ENA_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x238)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
+/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
+ *  is done.
+ */
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S  4
+/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ *  done.
+ */
+#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
+#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_CLR_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : HRO; bitpos: [7]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
+/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The bit is used to clear interrupt of L1-Cache preload-operation error.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S  11
+/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
+#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_CLR_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x23c)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
+/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+ *  done.
+ */
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S  4
+/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
+#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_RAW_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
+/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
+ *  occurs.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S  11
+/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+ *  occurs.
+ */
+#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
+#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_RAW_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x240)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : HRO; bitpos: [0]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : HRO; bitpos: [1]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
+/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-Cache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M  (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S  4
+/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when Cache
+ *  sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
+#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ST_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : HRO; bitpos: [7]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : HRO; bitpos: [8]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
+/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M  (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S  11
+/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the status of the interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
+#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ST_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x244)
+/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
+/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
+/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
+/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
+/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-Cache.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_CACHE_PLD_ERR_CODE_M  (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S)
+#define CACHE_L1_CACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_CACHE_PLD_ERR_CODE_S  8
+/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
+ *  The values 0-2 are available which means sync map, command conflict and size are
+ *  error in Cache System.
+ */
+#define CACHE_SYNC_ERR_CODE    0x00000003U
+#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
+#define CACHE_SYNC_ERR_CODE_V  0x00000003U
+#define CACHE_SYNC_ERR_CODE_S  12
+
+/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x248)
+/** CACHE_L1_ICACHE0_SYNC_RST : HRO; bitpos: [0]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
+#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_SYNC_RST_S  0
+/** CACHE_L1_ICACHE1_SYNC_RST : HRO; bitpos: [1]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
+#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_SYNC_RST_S  1
+/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
+#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_SYNC_RST_S  2
+/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
+#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_SYNC_RST_S  3
+/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_CACHE_SYNC_RST    (BIT(4))
+#define CACHE_L1_CACHE_SYNC_RST_M  (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S)
+#define CACHE_L1_CACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L1_CACHE_SYNC_RST_S  4
+
+/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c)
+/** CACHE_L1_ICACHE0_PLD_RST : HRO; bitpos: [0]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
+#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_RST_S  0
+/** CACHE_L1_ICACHE1_PLD_RST : HRO; bitpos: [1]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
+#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_RST_S  1
+/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
+#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_RST_S  2
+/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
+#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_RST_S  3
+/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_CACHE_PLD_RST    (BIT(4))
+#define CACHE_L1_CACHE_PLD_RST_M  (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S)
+#define CACHE_L1_CACHE_PLD_RST_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_RST_S  4
+
+/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x250)
+/** CACHE_L1_ICACHE0_ALD_BUF_CLR : HRO; bitpos: [0]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+ *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+ *  works in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
+/** CACHE_L1_ICACHE1_ALD_BUF_CLR : HRO; bitpos: [1]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+ *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+ *  works in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
+/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
+/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
+/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
+ *  autoload will not work in L1-Cache. This bit should not be active when autoload
+ *  works in L1-Cache.
+ */
+#define CACHE_L1_CACHE_ALD_BUF_CLR    (BIT(4))
+#define CACHE_L1_CACHE_ALD_BUF_CLR_M  (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S)
+#define CACHE_L1_CACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_ALD_BUF_CLR_S  4
+
+/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x254)
+/** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
+/** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
+/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
+/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
+/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 cache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
+#define CACHE_L1_CACHE_UNALLOC_CLR_M  (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S)
+#define CACHE_L1_CACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_UNALLOC_CLR_S  4
+
+/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x258)
+/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
+/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
+#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
+/** CACHE_L1_ICACHE2_TAG_OBJECT : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
+#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
+/** CACHE_L1_ICACHE3_TAG_OBJECT : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
+#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
+/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_CACHE_TAG_OBJECT    (BIT(4))
+#define CACHE_L1_CACHE_TAG_OBJECT_M  (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S)
+#define CACHE_L1_CACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_OBJECT_S  4
+/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
+#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
+/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
+#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
+/** CACHE_L1_ICACHE2_MEM_OBJECT : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
+#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
+/** CACHE_L1_ICACHE3_MEM_OBJECT : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
+#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
+/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_CACHE_MEM_OBJECT    (BIT(10))
+#define CACHE_L1_CACHE_MEM_OBJECT_M  (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S)
+#define CACHE_L1_CACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_CACHE_MEM_OBJECT_S  10
+
+/** CACHE_L1_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x25c)
+/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
+#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L1_CACHE_ADDR_REG register
+ *  Cache address register
+ */
+#define CACHE_L1_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x260)
+/** CACHE_L1_CACHE_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits stores the address which will decide where inside the specified tag
+ *  memory object will be accessed.
+ */
+#define CACHE_L1_CACHE_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_ADDR_M  (CACHE_L1_CACHE_ADDR_V << CACHE_L1_CACHE_ADDR_S)
+#define CACHE_L1_CACHE_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_ADDR_S  0
+
+/** CACHE_L1_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x264)
+/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 612;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
+#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_LEVEL_SPLIT0_REG register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x268)
+/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 616;
+ *  Reserved
+ */
+#define CACHE_LEVEL_SPLIT0    0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT0_M  (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S)
+#define CACHE_LEVEL_SPLIT0_V  0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT0_S  0
+
+/** CACHE_L2_CACHE_CTRL_REG register
+ *  L2 Cache(L2-Cache) control register
+ */
+#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x26c)
+/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
+#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L2_CACHE_SHUT_DMA_S  4
+/** CACHE_L2_CACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_CACHE_UNDEF_OP    0x000000FFU
+#define CACHE_L2_CACHE_UNDEF_OP_M  (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S)
+#define CACHE_L2_CACHE_UNDEF_OP_V  0x000000FFU
+#define CACHE_L2_CACHE_UNDEF_OP_S  8
+
+/** CACHE_L2_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x270)
+/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
+#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
+#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L2_CACHE_EN_S  5
+
+/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
+ *  L2 Cache CacheSize mode configure register
+ */
+#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x274)
+/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L2_CACHE_CACHESIZE_256_M  (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S)
+#define CACHE_L2_CACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256_S  0
+/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L2_CACHE_CACHESIZE_512_M  (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S)
+#define CACHE_L2_CACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512_S  1
+/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1K_S  2
+/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
+#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_2K_S  3
+/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
+#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_4K_S  4
+/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
+#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_8K_S  5
+/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
+#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_16K_S  6
+/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
+#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_32K_S  7
+/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
+#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_64K_S  8
+/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
+#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_128K_S  9
+/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
+#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256K_S  10
+/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
+#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512K_S  11
+/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
+ *  L2 Cache BlockSize mode configure register
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278)
+/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
+/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
+/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
+/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
+/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
+/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x27c)
+/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0;
+ *  Set this bit as 1 to enable L2-Cache wrap around mode.
+ */
+#define CACHE_L2_CACHE_WRAP    (BIT(5))
+#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
+#define CACHE_L2_CACHE_WRAP_V  0x00000001U
+#define CACHE_L2_CACHE_WRAP_S  5
+
+/** CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x280)
+/** CACHE_L2_CACHE_MISS_DISABLE_ACCESS : HRO; bitpos: [5]; default: 0;
+ *  Set this bit as 1 to disable early restart of  L2-Cache
+ */
+#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS    (BIT(5))
+#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_M  (CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S)
+#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S  5
+
+/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x284)
+/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0;
+ *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
+#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
+#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_EN_S  20
+/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0;
+ *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
+#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
+#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_MODE_S  21
+/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
+#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
+#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_DONE_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x288)
+/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 0;
+ *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 0;
+ *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x28c)
+/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 0;
+ *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 0;
+ *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
+ *  L2 Cache prelock configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x290)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l2 cache prelock.
+ */
+#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
+#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L2 Cache prelock section0 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x294)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section of prelock
+ *  on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L2 Cache prelock section1 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x298)
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section of prelock
+ *  on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
+ *  L2 Cache prelock section size configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x29c)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
+ *  L2 Cache preload-operation control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a0)
+/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
+#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
+/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
+#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
+/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
+#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
+/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l2 cache preload.
+ */
+#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
+#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
+
+/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
+ *  L2 Cache preload address configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2a4)
+/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of preload on L2-Cache, which
+ *  should be used together with L2_CACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
+#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
+ *  L2 Cache preload size configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2a8)
+/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
+#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
+ *  L2 Cache autoload-operation control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2ac)
+/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+ *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l2 cache autoload.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L2 Cache autoload section 0 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L2 Cache autoload section 0 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2b4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L2 Cache autoload section 1 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the second section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L2 Cache autoload section 1 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L2 Cache autoload section 2 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the third section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L2 Cache autoload section 2 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L2 Cache autoload section 3 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the fourth section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L2 Cache autoload section 3 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d0)
+/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2d4)
+/** CACHE_L2_IBUS0_OVF_INT_CLR : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
+/** CACHE_L2_IBUS1_OVF_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
+/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
+/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
+/** CACHE_L2_DBUS0_OVF_INT_CLR : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
+/** CACHE_L2_DBUS1_OVF_INT_CLR : HRO; bitpos: [13]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
+/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
+/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2d8)
+/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-ICache0.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
+/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-ICache1.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
+/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-ICache2.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
+/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-ICache3.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
+/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
+/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
+/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
+/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2dc)
+/** CACHE_L2_IBUS0_OVF_INT_ST : HRO; bitpos: [8]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
+#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ST : HRO; bitpos: [9]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
+#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
+#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
+#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ST : HRO; bitpos: [12]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
+#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ST : HRO; bitpos: [13]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
+#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
+#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
+#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
+
+/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e0)
+/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
+ *  not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2e4)
+/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+ *  l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
+#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2e8)
+/** CACHE_L2_CACHE_FAIL_INT_CLR : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+ *  cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
+#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2ec)
+/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
+#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f0)
+/** CACHE_L2_CACHE_FAIL_INT_ST : HRO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+ *  to l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
+#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
+
+/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2f4)
+/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
+#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_ENA_S  8
+/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
+#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_ENA_S  9
+/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
+#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_ENA_S  10
+/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
+#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_ENA_S  11
+/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to enable dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
+#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_ENA_S  12
+/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0;
+ *  The bit is used to enable dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
+#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_ENA_S  13
+/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
+#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_ENA_S  14
+/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
+#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_ENA_S  15
+/** CACHE_L2_IBUS0_CNT_CLR : HRO; bitpos: [24]; default: 0;
+ *  The bit is used to clear ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
+#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
+#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_CLR_S  24
+/** CACHE_L2_IBUS1_CNT_CLR : HRO; bitpos: [25]; default: 0;
+ *  The bit is used to clear ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
+#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
+#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_CLR_S  25
+/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
+#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
+#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_CLR_S  26
+/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
+#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
+#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_CLR_S  27
+/** CACHE_L2_DBUS0_CNT_CLR : HRO; bitpos: [28]; default: 0;
+ *  The bit is used to clear dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
+#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
+#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_CLR_S  28
+/** CACHE_L2_DBUS1_CNT_CLR : HRO; bitpos: [29]; default: 0;
+ *  The bit is used to clear dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
+#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
+#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_CLR_S  29
+/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
+#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
+#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_CLR_S  30
+/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
+#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
+#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_CLR_S  31
+
+/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2f8)
+/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
+#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2fc)
+/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
+#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
+/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache0 accesses
+ *  L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x304)
+/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
+/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
+#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
+/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
+#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
+/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache1 accesses
+ *  L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x314)
+/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
+/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
+#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
+/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
+#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
+/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache2 accesses
+ *  L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x324)
+/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
+/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
+#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
+/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
+#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
+/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache3 accesses
+ *  L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x334)
+/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
+/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
+#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
+/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
+#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
+/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x344)
+/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus0 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x348)
+/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
+/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
+#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x350)
+/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
+#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x354)
+/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x358)
+/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus1 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
+/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x360)
+/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
+#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x364)
+/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
+#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x368)
+/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x36c)
+/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus2 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x370)
+/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x374)
+/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
+#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x378)
+/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
+#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x37c)
+/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x380)
+/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus3 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x384)
+/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x388)
+/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
+#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_S  0
+/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+ *  due to cache accessing L1-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
+#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_S  16
+
+/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
+ *  L2-Cache Access Fail Address information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x38c)
+/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
+#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_S  0
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x390)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x394)
+/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+ *  is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x398)
+/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+ *  done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x39c)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ST : HRO; bitpos: [5]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+ *  preload-operation is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ST : HRO; bitpos: [12]; default: 0;
+ *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a0)
+/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L2-Cache.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
+#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
+
+/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a4)
+/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0;
+ *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
+#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
+#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L2_CACHE_SYNC_RST_S  5
+
+/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3a8)
+/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0;
+ *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
+#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_RST_S  5
+
+/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac)
+/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0;
+ *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+ *  autoload will not work in L2-Cache. This bit should not be active when autoload
+ *  works in L2-Cache.
+ */
+#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
+#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
+#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
+
+/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b0)
+/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l2 icache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
+#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
+#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
+
+/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
+ *  L2 cache access attribute control register
+ */
+#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4)
+/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1;
+ *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+ *  non-cacheable.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
+/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+ *  write-through.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
+/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  write-miss-allocate and write-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
+/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1;
+ *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  read-miss-allocate and read-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
+
+/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3b8)
+/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0;
+ *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
+#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
+#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_OBJECT_S  5
+/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0;
+ *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
+#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
+#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_MEM_OBJECT_S  11
+
+/** CACHE_L2_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3bc)
+/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
+#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L2_CACHE_ADDR_REG register
+ *  Cache address register
+ */
+#define CACHE_L2_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x3c0)
+/** CACHE_L2_CACHE_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits stores the address which will decide where inside the specified tag
+ *  memory object will be accessed.
+ */
+#define CACHE_L2_CACHE_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_ADDR_M  (CACHE_L2_CACHE_ADDR_V << CACHE_L2_CACHE_ADDR_S)
+#define CACHE_L2_CACHE_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_ADDR_S  0
+
+/** CACHE_L2_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3c4)
+/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 964;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
+#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_LEVEL_SPLIT1_REG register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3c8)
+/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 968;
+ *  Reserved
+ */
+#define CACHE_LEVEL_SPLIT1    0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT1_M  (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S)
+#define CACHE_LEVEL_SPLIT1_V  0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT1_S  0
+
+/** CACHE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3cc)
+/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define CACHE_CLK_EN    (BIT(0))
+#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
+#define CACHE_CLK_EN_V  0x00000001U
+#define CACHE_CLK_EN_S  0
+
+/** CACHE_TRACE_ENA_REG register
+ *  Clock gate control register
+ */
+#define CACHE_TRACE_ENA_REG (DR_REG_CACHE_BASE + 0x3d0)
+/** CACHE_L1_CACHE_TRACE_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable L1-Cache trace for the performance counter and fail tracer
+ */
+#define CACHE_L1_CACHE_TRACE_ENA    (BIT(0))
+#define CACHE_L1_CACHE_TRACE_ENA_M  (CACHE_L1_CACHE_TRACE_ENA_V << CACHE_L1_CACHE_TRACE_ENA_S)
+#define CACHE_L1_CACHE_TRACE_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_TRACE_ENA_S  0
+/** CACHE_L2_CACHE_TRACE_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable L2-Cache trace for the performance counter and fail tracer
+ */
+#define CACHE_L2_CACHE_TRACE_ENA    (BIT(1))
+#define CACHE_L2_CACHE_TRACE_ENA_M  (CACHE_L2_CACHE_TRACE_ENA_V << CACHE_L2_CACHE_TRACE_ENA_S)
+#define CACHE_L2_CACHE_TRACE_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_TRACE_ENA_S  1
+
+/** CACHE_REDUNDANCY_SIG0_REG register
+ *  Cache redundancy signal 0 register
+ */
+#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3d4)
+/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG0    0xFFFFFFFFU
+#define CACHE_REDCY_SIG0_M  (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S)
+#define CACHE_REDCY_SIG0_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG0_S  0
+
+/** CACHE_REDUNDANCY_SIG1_REG register
+ *  Cache redundancy signal 1 register
+ */
+#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3d8)
+/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG1    0xFFFFFFFFU
+#define CACHE_REDCY_SIG1_M  (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S)
+#define CACHE_REDCY_SIG1_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG1_S  0
+
+/** CACHE_REDUNDANCY_SIG2_REG register
+ *  Cache redundancy signal 2 register
+ */
+#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3dc)
+/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG2    0xFFFFFFFFU
+#define CACHE_REDCY_SIG2_M  (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S)
+#define CACHE_REDCY_SIG2_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG2_S  0
+
+/** CACHE_REDUNDANCY_SIG3_REG register
+ *  Cache redundancy signal 3 register
+ */
+#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3e0)
+/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG3    0xFFFFFFFFU
+#define CACHE_REDCY_SIG3_M  (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S)
+#define CACHE_REDCY_SIG3_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG3_S  0
+
+/** CACHE_REDUNDANCY_SIG4_REG register
+ *  Cache redundancy signal 0 register
+ */
+#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3e4)
+/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG4    0x0000000FU
+#define CACHE_REDCY_SIG4_M  (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S)
+#define CACHE_REDCY_SIG4_V  0x0000000FU
+#define CACHE_REDCY_SIG4_S  0
+
+/** CACHE_DATE_REG register
+ *  Version control register
+ */
+#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
+/** CACHE_DATE : R/W; bitpos: [27:0]; default: 36774432;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define CACHE_DATE    0x0FFFFFFFU
+#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
+#define CACHE_DATE_V  0x0FFFFFFFU
+#define CACHE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/cache_struct.h b/components/soc/esp32c61/register/soc/cache_struct.h
new file mode 100644
index 00000000000..408c01c2c78
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/cache_struct.h
@@ -0,0 +1,5761 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of l1_icache_ctrl register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+typedef union {
+    struct {
+        /** l1_icache_shut_ibus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus0:1;
+        /** l1_icache_shut_ibus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus1:1;
+        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus2:1;
+        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus3:1;
+        uint32_t reserved_4:4;
+        /** l1_icache_undef_op : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_undef_op:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_icache_ctrl_reg_t;
+
+/** Type of l1_cache_ctrl register
+ *  L1 data Cache(L1-Cache) control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 bus0 access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus0:1;
+        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core0 bus1 access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus1:1;
+        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus2:1;
+        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus3:1;
+        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_dma:1;
+        uint32_t reserved_5:3;
+        /** l1_cache_undef_op : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_undef_op:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_cache_ctrl_reg_t;
+
+/** Type of l2_cache_ctrl register
+ *  L2 Cache(L2-Cache) control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+         */
+        uint32_t l2_cache_shut_dma:1;
+        uint32_t reserved_5:3;
+        /** l2_cache_undef_op : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_cache_undef_op:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_ctrl_reg_t;
+
+
+/** Group: Bypass Cache Control and configuration registers */
+/** Type of l1_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache0_en:1;
+        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache1_en:1;
+        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache2_en:1;
+        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache3_en:1;
+        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_dcache_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_bypass_cache_conf_reg_t;
+
+/** Type of l2_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l2_cache_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_bypass_cache_conf_reg_t;
+
+
+/** Group: Cache Atomic Control and configuration registers */
+/** Type of l1_cache_atomic_conf register
+ *  L1 Cache atomic feature configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
+         *  L1-Cache.  1: disable, 1: enable.
+         */
+        uint32_t l1_cache_atomic_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l1_cache_atomic_conf_reg_t;
+
+
+/** Group: Cache Mode Control and configuration registers */
+/** Type of l1_icache_cachesize_conf register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256:1;
+        /** l1_icache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512:1;
+        /** l1_icache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1k:1;
+        /** l1_icache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2k:1;
+        /** l1_icache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4k:1;
+        /** l1_icache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_8k:1;
+        /** l1_icache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_16k:1;
+        /** l1_icache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_32k:1;
+        /** l1_icache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_64k:1;
+        /** l1_icache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_128k:1;
+        /** l1_icache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256k:1;
+        /** l1_icache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512k:1;
+        /** l1_icache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_icache_cachesize_conf_reg_t;
+
+/** Type of l1_icache_blocksize_conf register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_8:1;
+        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_16:1;
+        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_32:1;
+        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_64:1;
+        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_128:1;
+        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache_blocksize_conf_reg_t;
+
+/** Type of l1_cache_cachesize_conf register
+ *  L1 data Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_256:1;
+        /** l1_cache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_512:1;
+        /** l1_cache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1k:1;
+        /** l1_cache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2k:1;
+        /** l1_cache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4k:1;
+        /** l1_cache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_8k:1;
+        /** l1_cache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_16k:1;
+        /** l1_cache_cachesize_32k : HRO; bitpos: [7]; default: 1;
+         *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_32k:1;
+        /** l1_cache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_64k:1;
+        /** l1_cache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_128k:1;
+        /** l1_cache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_256k:1;
+        /** l1_cache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_512k:1;
+        /** l1_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_cache_cachesize_conf_reg_t;
+
+/** Type of l1_cache_blocksize_conf register
+ *  L1 data Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_8:1;
+        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_16:1;
+        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
+         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_32:1;
+        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_64:1;
+        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_128:1;
+        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_cache_blocksize_conf_reg_t;
+
+/** Type of l2_cache_cachesize_conf register
+ *  L2 Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256:1;
+        /** l2_cache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512:1;
+        /** l2_cache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1k:1;
+        /** l2_cache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2k:1;
+        /** l2_cache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4k:1;
+        /** l2_cache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_8k:1;
+        /** l2_cache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_16k:1;
+        /** l2_cache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_32k:1;
+        /** l2_cache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_64k:1;
+        /** l2_cache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_128k:1;
+        /** l2_cache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256k:1;
+        /** l2_cache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512k:1;
+        /** l2_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_cachesize_conf_reg_t;
+
+/** Type of l2_cache_blocksize_conf register
+ *  L2 Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_8:1;
+        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_16:1;
+        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_32:1;
+        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_64:1;
+        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_128:1;
+        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_blocksize_conf_reg_t;
+
+
+/** Group: Wrap Mode Control and configuration registers */
+/** Type of l1_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+         */
+        uint32_t l1_icache0_wrap:1;
+        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+         */
+        uint32_t l1_icache1_wrap:1;
+        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_wrap:1;
+        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_wrap:1;
+        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to enable L1-DCache wrap around mode.
+         */
+        uint32_t l1_cache_wrap:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_wrap_around_ctrl_reg_t;
+
+/** Type of l2_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to enable L2-Cache wrap around mode.
+         */
+        uint32_t l2_cache_wrap:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_wrap_around_ctrl_reg_t;
+
+
+/** Group: Early Restart Control registers */
+/** Type of l1_cache_miss_access_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_miss_disable_access : HRO; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to disable early restart of  L1-ICache0
+         */
+        uint32_t l1_icache0_miss_disable_access:1;
+        /** l1_icache1_miss_disable_access : HRO; bitpos: [1]; default: 0;
+         *  Set this bit as 1 to disable early restart of  L1-ICache1
+         */
+        uint32_t l1_icache1_miss_disable_access:1;
+        /** l1_icache2_miss_disable_access : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_miss_disable_access:1;
+        /** l1_icache3_miss_disable_access : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_miss_disable_access:1;
+        /** l1_cache_miss_disable_access : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to disable early restart of L1-DCache
+         */
+        uint32_t l1_cache_miss_disable_access:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_miss_access_ctrl_reg_t;
+
+/** Type of l2_cache_miss_access_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_miss_disable_access : HRO; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to disable early restart of  L2-Cache
+         */
+        uint32_t l2_cache_miss_disable_access:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_miss_access_ctrl_reg_t;
+
+
+/** Group: Cache Freeze Control registers */
+/** Type of l1_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache0_freeze_en:1;
+        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache0_freeze_mode:1;
+        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_freeze_done:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache1_freeze_en:1;
+        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache1_freeze_mode:1;
+        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_freeze_done:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_en:1;
+        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_mode:1;
+        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_done:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_en:1;
+        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_mode:1;
+        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_done:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_cache_freeze_en:1;
+        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_cache_freeze_mode:1;
+        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_freeze_done:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_freeze_ctrl_reg_t;
+
+/** Type of l2_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l2_cache_freeze_en:1;
+        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l2_cache_freeze_mode:1;
+        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_freeze_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_freeze_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Access Control and Configuration registers */
+/** Type of l1_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_data_mem_rd_en:1;
+        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache0_data_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_data_mem_rd_en:1;
+        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache1_data_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_rd_en:1;
+        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_rd_en:1;
+        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_rd_en:1;
+        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_data_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_rd_en:1;
+        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_data_mem_acs_conf_reg_t;
+
+
+/** Group: Cache Tag Memory Access Control and Configuration registers */
+/** Type of l1_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_rd_en:1;
+        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_rd_en:1;
+        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_rd_en:1;
+        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_rd_en:1;
+        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_rd_en:1;
+        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_tag_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_rd_en:1;
+        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_tag_mem_acs_conf_reg_t;
+
+
+/** Group: Prelock Control and configuration registers */
+/** Type of l1_icache0_prelock_conf register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct0_en:1;
+        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct1_en:1;
+        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 prelock.
+         */
+        uint32_t l1_icache0_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_conf_reg_t;
+
+/** Type of l1_icache0_prelock_sct0_addr register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section of prelock
+         *  on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct1_addr register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section of prelock
+         *  on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct_size register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct_size_reg_t;
+
+/** Type of l1_icache1_prelock_conf register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct0_en:1;
+        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct1_en:1;
+        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 prelock.
+         */
+        uint32_t l1_icache1_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_conf_reg_t;
+
+/** Type of l1_icache1_prelock_sct0_addr register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section of prelock
+         *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct1_addr register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section of prelock
+         *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct_size register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct_size_reg_t;
+
+/** Type of l1_icache2_prelock_conf register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct0_en:1;
+        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct1_en:1;
+        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 prelock.
+         */
+        uint32_t l1_icache2_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_conf_reg_t;
+
+/** Type of l1_icache2_prelock_sct0_addr register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section of prelock
+         *  on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct1_addr register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section of prelock
+         *  on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct_size register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct_size_reg_t;
+
+/** Type of l1_icache3_prelock_conf register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct0_en:1;
+        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct1_en:1;
+        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 prelock.
+         */
+        uint32_t l1_icache3_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_conf_reg_t;
+
+/** Type of l1_icache3_prelock_sct0_addr register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section of prelock
+         *  on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct1_addr register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section of prelock
+         *  on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct_size register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct_size_reg_t;
+
+/** Type of l1_cache_prelock_conf register
+ *  L1 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct0_en:1;
+        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct1_en:1;
+        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 cache prelock.
+         */
+        uint32_t l1_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_cache_prelock_conf_reg_t;
+
+/** Type of l1_cache_prelock_sct0_addr register
+ *  L1 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section of prelock
+         *  on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct1_addr register
+ *  L1 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section of prelock
+         *  on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct1_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct_size register
+ *  L1  Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct_size_reg_t;
+
+/** Type of l2_cache_prelock_conf register
+ *  L2 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct0_en:1;
+        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct1_en:1;
+        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l2 cache prelock.
+         */
+        uint32_t l2_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_conf_reg_t;
+
+/** Type of l2_cache_prelock_sct0_addr register
+ *  L2 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section of prelock
+         *  on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct1_addr register
+ *  L2 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section of prelock
+         *  on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct1_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct_size register
+ *  L2 Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct0_size:16;
+        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct1_size:16;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct_size_reg_t;
+
+
+/** Group: Lock Control and configuration registers */
+/** Type of lock_ctrl register
+ *  Lock-class (manual lock) operation control register
+ */
+typedef union {
+    struct {
+        /** lock_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+         *  operation done
+         */
+        uint32_t lock_ena:1;
+        /** unlock_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable unlock operation. It will be cleared by hardware after
+         *  unlock operation done
+         */
+        uint32_t unlock_ena:1;
+        /** lock_done : RO; bitpos: [2]; default: 1;
+         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+         *  not finished. 1: finished.
+         */
+        uint32_t lock_done:1;
+        /** lock_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of cache lock/unlock.
+         */
+        uint32_t lock_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_lock_ctrl_reg_t;
+
+/** Type of lock_map register
+ *  Lock (manual lock) map configure register
+ */
+typedef union {
+    struct {
+        /** lock_map : R/W; bitpos: [5:0]; default: 0;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply this lock/unlock operation. [4]: L1-Cache
+         */
+        uint32_t lock_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_lock_map_reg_t;
+
+/** Type of lock_addr register
+ *  Lock (manual lock) address configure register
+ */
+typedef union {
+    struct {
+        /** lock_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the lock/unlock operation,
+         *  which should be used together with CACHE_LOCK_SIZE_REG
+         */
+        uint32_t lock_addr:32;
+    };
+    uint32_t val;
+} cache_lock_addr_reg_t;
+
+/** Type of lock_size register
+ *  Lock (manual lock) size configure register
+ */
+typedef union {
+    struct {
+        /** lock_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the lock/unlock operation, which
+         *  should be used together with CACHE_LOCK_ADDR_REG
+         */
+        uint32_t lock_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_lock_size_reg_t;
+
+
+/** Group: Sync Control and configuration registers */
+/** Type of sync_ctrl register
+ *  Sync-class operation control register
+ */
+typedef union {
+    struct {
+        /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
+         *  The bit is used to enable invalidate operation. It will be cleared by hardware
+         *  after invalidate operation done. Note that this bit and the other sync-bits
+         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t invalidate_ena:1;
+        /** clean_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable clean operation. It will be cleared by hardware after
+         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+         *  bits can not be set to 1 at the same time.
+         */
+        uint32_t clean_ena:1;
+        /** writeback_ena : R/W/SC; bitpos: [2]; default: 0;
+         *  The bit is used to enable writeback operation. It will be cleared by hardware after
+         *  writeback operation done. Note that this bit and the other sync-bits
+         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t writeback_ena:1;
+        /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
+         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+         *  hardware after writeback-invalidate operation done. Note that this bit and the
+         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t writeback_invalidate_ena:1;
+        /** sync_done : RO; bitpos: [4]; default: 0;
+         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+         */
+        uint32_t sync_done:1;
+        /** sync_rgid : HRO; bitpos: [8:5]; default: 0;
+         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+         *  writeback, writeback_invalidate)
+         */
+        uint32_t sync_rgid:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} cache_sync_ctrl_reg_t;
+
+/** Type of sync_map register
+ *  Sync map configure register
+ */
+typedef union {
+    struct {
+        /** sync_map : R/W; bitpos: [5:0]; default: 63;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply the sync operation.  [4]: L1-Cache
+         */
+        uint32_t sync_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_sync_map_reg_t;
+
+/** Type of sync_addr register
+ *  Sync address configure register
+ */
+typedef union {
+    struct {
+        /** sync_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the sync operation, which
+         *  should be used together with CACHE_SYNC_SIZE_REG
+         */
+        uint32_t sync_addr:32;
+    };
+    uint32_t val;
+} cache_sync_addr_reg_t;
+
+/** Type of sync_size register
+ *  Sync size configure register
+ */
+typedef union {
+    struct {
+        /** sync_size : R/W; bitpos: [24:0]; default: 0;
+         *  Those bits are used to configure the size of the sync operation, which should be
+         *  used together with CACHE_SYNC_ADDR_REG
+         */
+        uint32_t sync_size:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} cache_sync_size_reg_t;
+
+
+/** Group: Preload Control and configuration registers */
+/** Type of l1_icache0_preload_ctrl register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache0_preload_ena:1;
+        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache0_preload_done:1;
+        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache0_preload_order:1;
+        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 preload.
+         */
+        uint32_t l1_icache0_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_ctrl_reg_t;
+
+/** Type of l1_icache0_preload_addr register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of preload on L1-ICache0, which
+         *  should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache0_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_addr_reg_t;
+
+/** Type of l1_icache0_preload_size register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache0_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_size_reg_t;
+
+/** Type of l1_icache1_preload_ctrl register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache1_preload_ena:1;
+        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache1_preload_done:1;
+        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache1_preload_order:1;
+        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 preload.
+         */
+        uint32_t l1_icache1_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_ctrl_reg_t;
+
+/** Type of l1_icache1_preload_addr register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of preload on L1-ICache1, which
+         *  should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache1_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_addr_reg_t;
+
+/** Type of l1_icache1_preload_size register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache1_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_size_reg_t;
+
+/** Type of l1_icache2_preload_ctrl register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache2_preload_ena:1;
+        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache2_preload_done:1;
+        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache2_preload_order:1;
+        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 preload.
+         */
+        uint32_t l1_icache2_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_ctrl_reg_t;
+
+/** Type of l1_icache2_preload_addr register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of preload on L1-ICache2, which
+         *  should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache2_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_addr_reg_t;
+
+/** Type of l1_icache2_preload_size register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache2_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_size_reg_t;
+
+/** Type of l1_icache3_preload_ctrl register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache3_preload_ena:1;
+        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache3_preload_done:1;
+        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache3_preload_order:1;
+        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 preload.
+         */
+        uint32_t l1_icache3_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_ctrl_reg_t;
+
+/** Type of l1_icache3_preload_addr register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of preload on L1-ICache3, which
+         *  should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache3_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_addr_reg_t;
+
+/** Type of l1_icache3_preload_size register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache3_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_size_reg_t;
+
+/** Type of l1_cache_preload_ctrl register
+ *  L1 Cache  preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_cache_preload_ena:1;
+        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_cache_preload_done:1;
+        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_cache_preload_order:1;
+        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 cache preload.
+         */
+        uint32_t l1_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_cache_preload_ctrl_reg_t;
+
+/** Type of l1_dcache_preload_addr register
+ *  L1 Cache  preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of preload on L1-Cache, which
+         *  should be used together with L1_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_cache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_addr_reg_t;
+
+/** Type of l1_dcache_preload_size register
+ *  L1 Cache  preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_cache_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_size_reg_t;
+
+/** Type of l2_cache_preload_ctrl register
+ *  L2 Cache preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l2_cache_preload_ena:1;
+        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l2_cache_preload_done:1;
+        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l2_cache_preload_order:1;
+        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l2 cache preload.
+         */
+        uint32_t l2_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_ctrl_reg_t;
+
+/** Type of l2_cache_preload_addr register
+ *  L2 Cache preload address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of preload on L2-Cache, which
+         *  should be used together with L2_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l2_cache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_addr_reg_t;
+
+/** Type of l2_cache_preload_size register
+ *  L2 Cache preload size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l2_cache_preload_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_size_reg_t;
+
+
+/** Group: Autoload Control and configuration registers */
+/** Type of l1_icache0_autoload_ctrl register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache0_autoload_ena:1;
+        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_autoload_done:1;
+        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache0_autoload_order:1;
+        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache0_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct0_ena:1;
+        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct1_ena:1;
+        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 autoload.
+         */
+        uint32_t l1_icache0_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_ctrl_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_addr register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section for
+         *  autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_size register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_addr register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section for
+         *  autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_size register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache1_autoload_ctrl register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache1_autoload_ena:1;
+        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_autoload_done:1;
+        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache1_autoload_order:1;
+        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache1_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct0_ena:1;
+        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct1_ena:1;
+        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 autoload.
+         */
+        uint32_t l1_icache1_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_ctrl_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_addr register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section for
+         *  autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_size register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_addr register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section for
+         *  autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_size register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache2_autoload_ctrl register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache2_autoload_ena:1;
+        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache2_autoload_done:1;
+        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache2_autoload_order:1;
+        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache2_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct0_ena:1;
+        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct1_ena:1;
+        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 autoload.
+         */
+        uint32_t l1_icache2_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_ctrl_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_addr register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section for
+         *  autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_size register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_addr register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section for
+         *  autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_size register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache3_autoload_ctrl register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache3_autoload_ena:1;
+        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache3_autoload_done:1;
+        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache3_autoload_order:1;
+        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache3_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct0_ena:1;
+        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct1_ena:1;
+        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 autoload.
+         */
+        uint32_t l1_icache3_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_ctrl_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_addr register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section for
+         *  autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_size register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_addr register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section for
+         *  autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_size register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_ctrl register
+ *  L1 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_cache_autoload_ena:1;
+        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_autoload_done:1;
+        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_cache_autoload_order:1;
+        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct0_ena:1;
+        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct1_ena:1;
+        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct2_ena:1;
+        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct3_ena:1;
+        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l1 cache autoload.
+         */
+        uint32_t l1_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_ctrl_reg_t;
+
+/** Type of l1_cache_autoload_sct0_addr register
+ *  L1 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct0_size register
+ *  L1 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_size : R/W; bitpos: [24:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_size:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct0_size_reg_t;
+
+/** Type of l1_cache_autoload_sct1_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct1_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_size : R/W; bitpos: [24:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_size:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_sct2_addr register
+ *  L1 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the third section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct2_size register
+ *  L1 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_size : HRO; bitpos: [24:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_size:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct2_size_reg_t;
+
+/** Type of l1_cache_autoload_sct3_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the fourth section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct3_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_size : HRO; bitpos: [24:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_size:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct3_size_reg_t;
+
+/** Type of l2_cache_autoload_ctrl register
+ *  L2 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l2_cache_autoload_ena:1;
+        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_autoload_done:1;
+        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l2_cache_autoload_order:1;
+        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l2_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct0_ena:1;
+        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct1_ena:1;
+        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct2_ena:1;
+        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct3_ena:1;
+        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l2 cache autoload.
+         */
+        uint32_t l2_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_sct0_addr register
+ *  L2 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct0_size register
+ *  L2 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_size_reg_t;
+
+/** Type of l2_cache_autoload_sct1_addr register
+ *  L2 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the second section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct1_size register
+ *  L2 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_size_reg_t;
+
+/** Type of l2_cache_autoload_sct2_addr register
+ *  L2 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the third section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct2_size register
+ *  L2 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_size_reg_t;
+
+/** Type of l2_cache_autoload_sct3_addr register
+ *  L2 Cache autoload section 3 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the fourth section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct3_size register
+ *  L2 Cache autoload section 3 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_size_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of l1_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_ena:1;
+        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_ena:1;
+        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_ena:1;
+        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_ena:1;
+        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_ena:1;
+        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_ena:1;
+        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_ena:1;
+        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+         *  to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_clr:1;
+        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+         *  to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_clr:1;
+        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_clr:1;
+        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_clr:1;
+        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_clr:1;
+        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_clr:1;
+        /** l1_dbus2_ovf_int_clr : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_clr:1;
+        /** l1_dbus3_ovf_int_clr : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+         *  due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_raw:1;
+        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+         *  due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_raw:1;
+        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+         *  due to bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_ovf_int_raw:1;
+        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+         *  due to bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_ovf_int_raw:1;
+        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_raw:1;
+        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_raw:1;
+        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_ovf_int_raw:1;
+        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_ovf_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_st:1;
+        /** l1_ibus1_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_st:1;
+        /** l1_ibus2_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_st:1;
+        /** l1_ibus3_ovf_int_st : RO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_st:1;
+        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_st:1;
+        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_st:1;
+        /** l1_dbus2_ovf_int_st : RO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_st:1;
+        /** l1_dbus3_ovf_int_st : RO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l1_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_ena:1;
+        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_ena:1;
+        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_ena:1;
+        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_ena:1;
+        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l1_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_clr:1;
+        /** l1_icache1_fail_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_clr:1;
+        /** l1_icache2_fail_int_clr : WT; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_clr:1;
+        /** l1_icache3_fail_int_clr : WT; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_clr:1;
+        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l1_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_raw:1;
+        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_raw:1;
+        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+         */
+        uint32_t l1_icache2_fail_int_raw:1;
+        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+         */
+        uint32_t l1_icache3_fail_int_raw:1;
+        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l1_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_int_st:1;
+        /** l1_icache1_fail_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_int_st:1;
+        /** l1_icache2_fail_int_st : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_st:1;
+        /** l1_icache3_fail_int_st : RO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_st:1;
+        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+         *  to cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_st_reg_t;
+
+/** Type of l1_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache0_pld_done_int_ena:1;
+        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache1_pld_done_int_ena:1;
+        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_ena:1;
+        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_ena:1;
+        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_cache_pld_done_int_ena:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation done.
+         */
+        uint32_t sync_done_int_ena:1;
+        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_ena:1;
+        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_ena:1;
+        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_ena:1;
+        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_ena:1;
+        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_ena:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l1_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_clr:1;
+        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_clr:1;
+        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_clr:1;
+        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_clr:1;
+        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l1_cache_pld_done_int_clr:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+         *  done.
+         */
+        uint32_t sync_done_int_clr:1;
+        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_clr:1;
+        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_clr:1;
+        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_clr:1;
+        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_clr:1;
+        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
+         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_clr:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l1_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache0_pld_done_int_raw:1;
+        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache1_pld_done_int_raw:1;
+        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_raw:1;
+        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_raw:1;
+        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l1_cache_pld_done_int_raw:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+         */
+        uint32_t sync_done_int_raw:1;
+        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache0_pld_err_int_raw:1;
+        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache1_pld_err_int_raw:1;
+        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_raw:1;
+        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_raw:1;
+        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_err_int_raw:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+         *  occurs.
+         */
+        uint32_t sync_err_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l1_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_st:1;
+        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_st:1;
+        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_st:1;
+        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_st:1;
+        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l1_cache_pld_done_int_st:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_st : RO; bitpos: [6]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when Cache
+         *  sync-operation is done.
+         */
+        uint32_t sync_done_int_st:1;
+        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_st:1;
+        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_st:1;
+        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_st:1;
+        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_st:1;
+        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_st:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the status of the interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_st_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_ena:1;
+        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_ena:1;
+        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_ena:1;
+        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_ena:1;
+        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_ena:1;
+        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_ena:1;
+        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_ena:1;
+        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_clr:1;
+        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_clr:1;
+        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_clr:1;
+        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_clr:1;
+        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_clr:1;
+        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_clr:1;
+        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_clr:1;
+        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-ICache0.
+         */
+        uint32_t l2_ibus0_ovf_int_raw:1;
+        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-ICache1.
+         */
+        uint32_t l2_ibus1_ovf_int_raw:1;
+        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-ICache2.
+         */
+        uint32_t l2_ibus2_ovf_int_raw:1;
+        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-ICache3.
+         */
+        uint32_t l2_ibus3_ovf_int_raw:1;
+        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-DCache.
+         */
+        uint32_t l2_dbus0_ovf_int_raw:1;
+        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-DCache.
+         */
+        uint32_t l2_dbus1_ovf_int_raw:1;
+        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-DCache.
+         */
+        uint32_t l2_dbus2_ovf_int_raw:1;
+        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-DCache.
+         */
+        uint32_t l2_dbus3_ovf_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_st:1;
+        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_st:1;
+        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_st:1;
+        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_st:1;
+        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_st:1;
+        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_st:1;
+        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_st:1;
+        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l2_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+         *  l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l2_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+         *  cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l2_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l2_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+         *  to l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_st_reg_t;
+
+/** Type of l2_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+         */
+        uint32_t l2_cache_pld_done_int_ena:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l2_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l2_cache_pld_done_int_clr:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l2_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l2_cache_pld_done_int_raw:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_err_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l2_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l2_cache_pld_done_int_st:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_st_reg_t;
+
+
+/** Group: Cache Access Fail Configuration register */
+/** Type of l1_cache_acs_fail_ctrl register
+ *  Cache Access Fail Configuration register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_acs_fail_check_mode : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache0_acs_fail_check_mode:1;
+        /** l1_icache1_acs_fail_check_mode : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache1_acs_fail_check_mode:1;
+        /** l1_icache2_acs_fail_check_mode : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache2_acs_fail_check_mode:1;
+        /** l1_icache3_acs_fail_check_mode : HRO; bitpos: [3]; default: 0;
+         *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
+         *  is not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache3_acs_fail_check_mode:1;
+        /** l1_cache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to configure l1 cache access fail check mode. 0: the access fail is
+         *  not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_cache_acs_fail_check_mode:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_ctrl_reg_t;
+
+/** Type of l2_cache_acs_fail_ctrl register
+ *  Cache Access Fail Configuration register
+ */
+typedef union {
+    struct {
+        /** l2_cache_acs_fail_check_mode : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
+         *  not propagated to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l2_cache_acs_fail_check_mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_ctrl_reg_t;
+
+
+/** Group: Access Statistics registers */
+/** Type of l1_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_ena:1;
+        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_ena:1;
+        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_ena:1;
+        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_ena:1;
+        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_ena:1;
+        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_ena:1;
+        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_ena:1;
+        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_ena:1;
+        uint32_t reserved_8:8;
+        /** l1_ibus0_cnt_clr : WT; bitpos: [16]; default: 0;
+         *  The bit is used to clear ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_clr:1;
+        /** l1_ibus1_cnt_clr : WT; bitpos: [17]; default: 0;
+         *  The bit is used to clear ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_clr:1;
+        /** l1_ibus2_cnt_clr : WT; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_clr:1;
+        /** l1_ibus3_cnt_clr : WT; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_clr:1;
+        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
+         *  The bit is used to clear dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_clr:1;
+        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
+         *  The bit is used to clear dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_clr:1;
+        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_clr:1;
+        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_clr:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l1_ibus0_acs_hit_cnt register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_miss_cnt register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_conflict_cnt register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l1_ibus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_hit_cnt register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_miss_cnt register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_conflict_cnt register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l1_ibus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_hit_cnt register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_miss_cnt register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_conflict_cnt register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l1_ibus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_hit_cnt register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_miss_cnt register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_conflict_cnt register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l1_ibus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_bus0_acs_hit_cnt register
+ *  L1-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus0_acs_miss_cnt register
+ *  L1-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus0_acs_conflict_cnt register
+ *  L1-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_conflict_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_conflict_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register
+ *  L1-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus0 accessing L1-Cache.
+         */
+        uint32_t l1_bus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_bus1_acs_hit_cnt register
+ *  L1-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus1_acs_miss_cnt register
+ *  L1-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus1_acs_conflict_cnt register
+ *  L1-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus1 accessing L1-Cache.
+         */
+        uint32_t l1_dbus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_dbus1_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_hit_cnt register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_miss_cnt register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_conflict_cnt register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus2 accessing L1-Cache.
+         */
+        uint32_t l1_dbus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus2 accesses L1-Cache.
+         */
+        uint32_t l1_dbus2_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_hit_cnt register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_miss_cnt register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_conflict_cnt register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus3 accessing L1-Cache.
+         */
+        uint32_t l1_dbus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_dbus3_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_ena:1;
+        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_ena:1;
+        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_ena:1;
+        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_ena:1;
+        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_ena:1;
+        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_ena:1;
+        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_ena:1;
+        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_ena:1;
+        uint32_t reserved_16:8;
+        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
+         *  The bit is used to clear ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_clr:1;
+        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
+         *  The bit is used to clear ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_clr:1;
+        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_clr:1;
+        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_clr:1;
+        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
+         *  The bit is used to clear dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_clr:1;
+        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
+         *  The bit is used to clear dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_clr:1;
+        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_clr:1;
+        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_clr:1;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l2_ibus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache0 accesses
+         *  L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache1 accesses
+         *  L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache2 accesses
+         *  L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache3 accesses
+         *  L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus0 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus1 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus2 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus3 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t;
+
+
+/** Group: Access Fail Debug registers */
+/** Type of l1_icache0_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_id:16;
+        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache0_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_addr_reg_t;
+
+/** Type of l1_icache1_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_id:16;
+        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache1_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_addr_reg_t;
+
+/** Type of l1_icache2_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_id:16;
+        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache2_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_addr_reg_t;
+
+/** Type of l1_icache3_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_id:16;
+        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache3_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_addr_reg_t;
+
+/** Type of l1_dcache_acs_fail_id_attr register
+ *  L1-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_id:16;
+        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_id_attr_reg_t;
+
+/** Type of l1_dcache_acs_fail_addr register
+ *  L1-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_addr_reg_t;
+
+/** Type of l2_cache_acs_fail_id_attr register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_id:16;
+        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+         *  due to cache accessing L1-Cache.
+         */
+        uint32_t l2_cache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l2_cache_acs_fail_addr register
+ *  L2-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_addr_reg_t;
+
+
+/** Group: Operation Exception registers */
+/** Type of l1_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache0.
+         */
+        uint32_t l1_icache0_pld_err_code:2;
+        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache1.
+         */
+        uint32_t l1_icache1_pld_err_code:2;
+        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_code:2;
+        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_code:2;
+        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-Cache.
+         */
+        uint32_t l1_cache_pld_err_code:2;
+        uint32_t reserved_10:2;
+        /** sync_err_code : RO; bitpos: [13:12]; default: 0;
+         *  The values 0-2 are available which means sync map, command conflict and size are
+         *  error in Cache System.
+         */
+        uint32_t sync_err_code:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_exception_reg_t;
+
+/** Type of l2_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L2-Cache.
+         */
+        uint32_t l2_cache_pld_err_code:2;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_exception_reg_t;
+
+
+/** Group: Sync Reset control and configuration registers */
+/** Type of l1_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache0_sync_rst:1;
+        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache1_sync_rst:1;
+        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_sync_rst:1;
+        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_sync_rst:1;
+        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_cache_sync_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_rst_ctrl_reg_t;
+
+/** Type of l2_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l2_cache_sync_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_rst_ctrl_reg_t;
+
+
+/** Group: Preload Reset control and configuration registers */
+/** Type of l1_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache0_pld_rst:1;
+        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache1_pld_rst:1;
+        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_rst:1;
+        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_rst:1;
+        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_preload_rst_ctrl_reg_t;
+
+/** Type of l2_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_rst_ctrl_reg_t;
+
+
+/** Group: Autoload buffer clear control and configuration registers */
+/** Type of l1_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+         *  works in L1-ICache0.
+         */
+        uint32_t l1_icache0_ald_buf_clr:1;
+        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+         *  works in L1-ICache1.
+         */
+        uint32_t l1_icache1_ald_buf_clr:1;
+        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_ald_buf_clr:1;
+        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_ald_buf_clr:1;
+        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
+         *  autoload will not work in L1-Cache. This bit should not be active when autoload
+         *  works in L1-Cache.
+         */
+        uint32_t l1_cache_ald_buf_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_buf_clr_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
+         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+         *  autoload will not work in L2-Cache. This bit should not be active when autoload
+         *  works in L2-Cache.
+         */
+        uint32_t l2_cache_ald_buf_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_buf_clr_ctrl_reg_t;
+
+
+/** Group: Unallocate request buffer clear registers */
+/** Type of l1_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache0_unalloc_clr:1;
+        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache1_unalloc_clr:1;
+        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_unalloc_clr:1;
+        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_unalloc_clr:1;
+        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 cache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_cache_unalloc_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_unallocate_buffer_clear_reg_t;
+
+/** Type of l2_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l2 icache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l2_cache_unalloc_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_unallocate_buffer_clear_reg_t;
+
+
+/** Group: Tag and Data Memory Access Control and configuration register */
+/** Type of l1_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_object : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache0_tag_object:1;
+        /** l1_icache1_tag_object : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache1_tag_object:1;
+        /** l1_icache2_tag_object : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_object:1;
+        /** l1_icache3_tag_object : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_object:1;
+        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_tag_object:1;
+        uint32_t reserved_5:1;
+        /** l1_icache0_mem_object : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache0_mem_object:1;
+        /** l1_icache1_mem_object : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache1_mem_object:1;
+        /** l1_icache2_mem_object : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_mem_object:1;
+        /** l1_icache3_mem_object : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_mem_object:1;
+        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_mem_object:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} cache_l1_cache_object_ctrl_reg_t;
+
+/** Type of l1_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l1_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l1_cache_way_object_reg_t;
+
+/** Type of l1_cache_addr register
+ *  Cache address register
+ */
+typedef union {
+    struct {
+        /** l1_cache_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits stores the address which will decide where inside the specified tag
+         *  memory object will be accessed.
+         */
+        uint32_t l1_cache_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_addr_reg_t;
+
+/** Type of l1_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 612;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l1_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l1_cache_debug_bus_reg_t;
+
+/** Type of l2_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
+         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_tag_object:1;
+        uint32_t reserved_6:5;
+        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
+         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_mem_object:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_object_ctrl_reg_t;
+
+/** Type of l2_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l2_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l2_cache_way_object_reg_t;
+
+/** Type of l2_cache_addr register
+ *  Cache address register
+ */
+typedef union {
+    struct {
+        /** l2_cache_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits stores the address which will decide where inside the specified tag
+         *  memory object will be accessed.
+         */
+        uint32_t l2_cache_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_addr_reg_t;
+
+/** Type of l2_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l2_cache_debug_bus : R/W; bitpos: [31:0]; default: 964;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l2_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l2_cache_debug_bus_reg_t;
+
+
+/** Group: Split L1 and L2 registers */
+/** Type of level_split0 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split0 : HRO; bitpos: [31:0]; default: 616;
+         *  Reserved
+         */
+        uint32_t level_split0:32;
+    };
+    uint32_t val;
+} cache_level_split0_reg_t;
+
+/** Type of level_split1 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split1 : HRO; bitpos: [31:0]; default: 968;
+         *  Reserved
+         */
+        uint32_t level_split1:32;
+    };
+    uint32_t val;
+} cache_level_split1_reg_t;
+
+
+/** Group: L2 cache access attribute control register */
+/** Type of l2_cache_access_attr_ctrl register
+ *  L2 cache access attribute control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
+         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+         *  non-cacheable.
+         */
+        uint32_t l2_cache_access_force_cc:1;
+        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+         *  write-through.
+         */
+        uint32_t l2_cache_access_force_wb:1;
+        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  write-miss-allocate and write-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_wma:1;
+        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
+         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  read-miss-allocate and read-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_rma:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_l2_cache_access_attr_ctrl_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_clock_gate_reg_t;
+
+
+/** Group: Cache Trace Control register */
+/** Type of trace_ena register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_trace_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable L1-Cache trace for the performance counter and fail tracer
+         */
+        uint32_t l1_cache_trace_ena:1;
+        /** l2_cache_trace_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable L2-Cache trace for the performance counter and fail tracer
+         */
+        uint32_t l2_cache_trace_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cache_trace_ena_reg_t;
+
+
+/** Group: Redundancy  register (Prepare for ECO) */
+/** Type of redundancy_sig0 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig0:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig0_reg_t;
+
+/** Type of redundancy_sig1 register
+ *  Cache redundancy signal 1 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig1:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig1_reg_t;
+
+/** Type of redundancy_sig2 register
+ *  Cache redundancy signal 2 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig2:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig2_reg_t;
+
+/** Type of redundancy_sig3 register
+ *  Cache redundancy signal 3 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig3:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig3_reg_t;
+
+/** Type of redundancy_sig4 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig4 : RO; bitpos: [3:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_redundancy_sig4_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36774432;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_date_reg_t;
+
+
+typedef struct {
+    volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl;
+    volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl;
+    volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
+    volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
+    volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
+    volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
+    volatile cache_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
+    volatile cache_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
+    volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
+    volatile cache_l1_cache_miss_access_ctrl_reg_t l1_cache_miss_access_ctrl;
+    volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
+    volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
+    volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
+    volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
+    volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
+    volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
+    volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
+    volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
+    volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
+    volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
+    volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
+    volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
+    volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
+    volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
+    volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
+    volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
+    volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
+    volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
+    volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
+    volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
+    volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
+    volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
+    volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
+    volatile cache_lock_ctrl_reg_t lock_ctrl;
+    volatile cache_lock_map_reg_t lock_map;
+    volatile cache_lock_addr_reg_t lock_addr;
+    volatile cache_lock_size_reg_t lock_size;
+    volatile cache_sync_ctrl_reg_t sync_ctrl;
+    volatile cache_sync_map_reg_t sync_map;
+    volatile cache_sync_addr_reg_t sync_addr;
+    volatile cache_sync_size_reg_t sync_size;
+    volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
+    volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
+    volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
+    volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
+    volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
+    volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
+    volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
+    volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
+    volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
+    volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
+    volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
+    volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
+    volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
+    volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
+    volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
+    volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
+    volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
+    volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
+    volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
+    volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
+    volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
+    volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
+    volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
+    volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
+    volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
+    volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
+    volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
+    volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
+    volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
+    volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
+    volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
+    volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
+    volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
+    volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
+    volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
+    volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
+    volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
+    volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
+    volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
+    volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
+    volatile cache_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
+    volatile cache_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
+    volatile cache_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
+    volatile cache_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
+    volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
+    volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
+    volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
+    volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
+    volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl;
+    volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
+    volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
+    volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
+    volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
+    volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
+    volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
+    volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
+    volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
+    volatile cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t l1_ibus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
+    volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
+    volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
+    volatile cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t l1_ibus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
+    volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
+    volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
+    volatile cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t l1_ibus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
+    volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
+    volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
+    volatile cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t l1_ibus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
+    volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
+    volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
+    volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
+    volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
+    volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
+    volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
+    volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
+    volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t l1_dbus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t l1_dbus2_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
+    volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
+    volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t l1_dbus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t l1_dbus3_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
+    volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
+    volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
+    volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
+    volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
+    volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
+    volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
+    volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
+    volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr;
+    volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
+    volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
+    volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
+    volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
+    volatile cache_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
+    volatile cache_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
+    volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
+    volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
+    volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
+    volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
+    volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
+    volatile cache_l1_cache_way_object_reg_t l1_cache_way_object;
+    volatile cache_l1_cache_addr_reg_t l1_cache_addr;
+    volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
+    volatile cache_level_split0_reg_t level_split0;
+    volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl;
+    volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
+    volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
+    volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
+    volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
+    volatile cache_l2_cache_miss_access_ctrl_reg_t l2_cache_miss_access_ctrl;
+    volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
+    volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
+    volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
+    volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
+    volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
+    volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
+    volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
+    volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
+    volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
+    volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size;
+    volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
+    volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
+    volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
+    volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
+    volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
+    volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
+    volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
+    volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
+    volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
+    volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
+    volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
+    volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
+    volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
+    volatile cache_l2_cache_acs_fail_ctrl_reg_t l2_cache_acs_fail_ctrl;
+    volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
+    volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
+    volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
+    volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
+    volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
+    volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
+    volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
+    volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
+    volatile cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t l2_ibus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
+    volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
+    volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
+    volatile cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t l2_ibus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
+    volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
+    volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
+    volatile cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t l2_ibus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
+    volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
+    volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
+    volatile cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t l2_ibus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
+    volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
+    volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t l2_dbus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t l2_dbus0_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
+    volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
+    volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t l2_dbus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t l2_dbus1_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
+    volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
+    volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t l2_dbus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t l2_dbus2_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
+    volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
+    volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t l2_dbus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t l2_dbus3_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
+    volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
+    volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
+    volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
+    volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
+    volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
+    volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
+    volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
+    volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
+    volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
+    volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
+    volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
+    volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
+    volatile cache_l2_cache_way_object_reg_t l2_cache_way_object;
+    volatile cache_l2_cache_addr_reg_t l2_cache_addr;
+    volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
+    volatile cache_level_split1_reg_t level_split1;
+    volatile cache_clock_gate_reg_t clock_gate;
+    volatile cache_trace_ena_reg_t trace_ena;
+    volatile cache_redundancy_sig0_reg_t redundancy_sig0;
+    volatile cache_redundancy_sig1_reg_t redundancy_sig1;
+    volatile cache_redundancy_sig2_reg_t redundancy_sig2;
+    volatile cache_redundancy_sig3_reg_t redundancy_sig3;
+    volatile cache_redundancy_sig4_reg_t redundancy_sig4;
+    uint32_t reserved_3e8[5];
+    volatile cache_date_reg_t date;
+} cache_dev_t;
+
+extern cache_dev_t CACHE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/clic_reg.h b/components/soc/esp32c61/register/soc/clic_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/clic_reg.h
rename to components/soc/esp32c61/register/soc/clic_reg.h
diff --git a/components/soc/esp32c61/include/soc/clint_reg.h b/components/soc/esp32c61/register/soc/clint_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/clint_reg.h
rename to components/soc/esp32c61/register/soc/clint_reg.h
diff --git a/components/soc/esp32c61/include/soc/ecc_mult_reg.h b/components/soc/esp32c61/register/soc/ecc_mult_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/ecc_mult_reg.h
rename to components/soc/esp32c61/register/soc/ecc_mult_reg.h
diff --git a/components/soc/esp32c61/include/soc/ecc_mult_struct.h b/components/soc/esp32c61/register/soc/ecc_mult_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/ecc_mult_struct.h
rename to components/soc/esp32c61/register/soc/ecc_mult_struct.h
diff --git a/components/soc/esp32c61/register/soc/ecdsa_reg.h b/components/soc/esp32c61/register/soc/ecdsa_reg.h
new file mode 100644
index 00000000000..4893390ced6
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/ecdsa_reg.h
@@ -0,0 +1,374 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECDSA_CONF_REG register
+ *  ECDSA configure register
+ */
+#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
+/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+ *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+ */
+#define ECDSA_WORK_MODE    0x00000003U
+#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
+#define ECDSA_WORK_MODE_V  0x00000003U
+#define ECDSA_WORK_MODE_S  0
+/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
+ *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
+ */
+#define ECDSA_ECC_CURVE    (BIT(2))
+#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
+#define ECDSA_ECC_CURVE_V  0x00000001U
+#define ECDSA_ECC_CURVE_S  2
+/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
+ *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+ *  written by software.
+ */
+#define ECDSA_SOFTWARE_SET_K    (BIT(3))
+#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
+#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_K_S  3
+/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
+ *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+ *  software.
+ */
+#define ECDSA_SOFTWARE_SET_Z    (BIT(4))
+#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
+#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_Z_S  4
+/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
+ *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+ *  deterministic derivation algorithm.
+ */
+#define ECDSA_DETERMINISTIC_K    (BIT(5))
+#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
+#define ECDSA_DETERMINISTIC_K_V  0x00000001U
+#define ECDSA_DETERMINISTIC_K_S  5
+/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
+ *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
+ */
+#define ECDSA_DETERMINISTIC_LOOP    0x0000FFFFU
+#define ECDSA_DETERMINISTIC_LOOP_M  (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
+#define ECDSA_DETERMINISTIC_LOOP_V  0x0000FFFFU
+#define ECDSA_DETERMINISTIC_LOOP_S  6
+
+/** ECDSA_CLK_REG register
+ *  ECDSA clock gate register
+ */
+#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
+/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
+#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
+#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
+#define ECDSA_CLK_GATE_FORCE_ON_S  0
+
+/** ECDSA_INT_RAW_REG register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
+/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_RAW    (BIT(0))
+#define ECDSA_PREP_DONE_INT_RAW_M  (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
+#define ECDSA_PREP_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_RAW_S  0
+/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_RAW    (BIT(1))
+#define ECDSA_PROC_DONE_INT_RAW_M  (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
+#define ECDSA_PROC_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_RAW_S  1
+/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_RAW    (BIT(2))
+#define ECDSA_POST_DONE_INT_RAW_M  (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
+#define ECDSA_POST_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_POST_DONE_INT_RAW_S  2
+/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
+#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_RAW_S  3
+
+/** ECDSA_INT_ST_REG register
+ *  ECDSA interrupt status register.
+ */
+#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
+/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_ST    (BIT(0))
+#define ECDSA_PREP_DONE_INT_ST_M  (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
+#define ECDSA_PREP_DONE_INT_ST_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_ST_S  0
+/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_ST    (BIT(1))
+#define ECDSA_PROC_DONE_INT_ST_M  (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
+#define ECDSA_PROC_DONE_INT_ST_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_ST_S  1
+/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_ST    (BIT(2))
+#define ECDSA_POST_DONE_INT_ST_M  (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
+#define ECDSA_POST_DONE_INT_ST_V  0x00000001U
+#define ECDSA_POST_DONE_INT_ST_S  2
+/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ST    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
+#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ST_S  3
+
+/** ECDSA_INT_ENA_REG register
+ *  ECDSA interrupt enable register.
+ */
+#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
+/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_ENA    (BIT(0))
+#define ECDSA_PREP_DONE_INT_ENA_M  (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
+#define ECDSA_PREP_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_ENA_S  0
+/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_ENA    (BIT(1))
+#define ECDSA_PROC_DONE_INT_ENA_M  (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
+#define ECDSA_PROC_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_ENA_S  1
+/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_ENA    (BIT(2))
+#define ECDSA_POST_DONE_INT_ENA_M  (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
+#define ECDSA_POST_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_POST_DONE_INT_ENA_S  2
+/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
+#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ENA_S  3
+
+/** ECDSA_INT_CLR_REG register
+ *  ECDSA interrupt clear register.
+ */
+#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
+/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_CLR    (BIT(0))
+#define ECDSA_PREP_DONE_INT_CLR_M  (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
+#define ECDSA_PREP_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_CLR_S  0
+/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_CLR    (BIT(1))
+#define ECDSA_PROC_DONE_INT_CLR_M  (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
+#define ECDSA_PROC_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_CLR_S  1
+/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_CLR    (BIT(2))
+#define ECDSA_POST_DONE_INT_CLR_M  (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
+#define ECDSA_POST_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_POST_DONE_INT_CLR_S  2
+/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
+#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_CLR_S  3
+
+/** ECDSA_START_REG register
+ *  ECDSA start register
+ */
+#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
+/** ECDSA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+ *  after configuration.
+ */
+#define ECDSA_START    (BIT(0))
+#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
+#define ECDSA_START_V  0x00000001U
+#define ECDSA_START_S  0
+/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_LOAD_DONE    (BIT(1))
+#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
+#define ECDSA_LOAD_DONE_V  0x00000001U
+#define ECDSA_LOAD_DONE_S  1
+/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_GET_DONE    (BIT(2))
+#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
+#define ECDSA_GET_DONE_V  0x00000001U
+#define ECDSA_GET_DONE_S  2
+
+/** ECDSA_STATE_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
+/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
+ *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+ *  state.
+ */
+#define ECDSA_BUSY    0x00000003U
+#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
+#define ECDSA_BUSY_V  0x00000003U
+#define ECDSA_BUSY_S  0
+
+/** ECDSA_RESULT_REG register
+ *  ECDSA result register
+ */
+#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
+/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+ *  done.
+ */
+#define ECDSA_OPERATION_RESULT    (BIT(0))
+#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
+#define ECDSA_OPERATION_RESULT_V  0x00000001U
+#define ECDSA_OPERATION_RESULT_S  0
+/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
+ *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
+ *  curve order, then actually taken k = k mod n.
+ */
+#define ECDSA_K_VALUE_WARNING    (BIT(1))
+#define ECDSA_K_VALUE_WARNING_M  (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
+#define ECDSA_K_VALUE_WARNING_V  0x00000001U
+#define ECDSA_K_VALUE_WARNING_S  1
+
+/** ECDSA_DATE_REG register
+ *  Version control register
+ */
+#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
+/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36725040;
+ *  ECDSA version control register
+ */
+#define ECDSA_DATE    0x0FFFFFFFU
+#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
+#define ECDSA_DATE_V  0x0FFFFFFFU
+#define ECDSA_DATE_S  0
+
+/** ECDSA_SHA_MODE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
+/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
+ *  Others: invalid.
+ */
+#define ECDSA_SHA_MODE    0x00000007U
+#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
+#define ECDSA_SHA_MODE_V  0x00000007U
+#define ECDSA_SHA_MODE_S  0
+
+/** ECDSA_SHA_START_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
+/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_START    (BIT(0))
+#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
+#define ECDSA_SHA_START_V  0x00000001U
+#define ECDSA_SHA_START_S  0
+
+/** ECDSA_SHA_CONTINUE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
+/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_CONTINUE    (BIT(0))
+#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
+#define ECDSA_SHA_CONTINUE_V  0x00000001U
+#define ECDSA_SHA_CONTINUE_S  0
+
+/** ECDSA_SHA_BUSY_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
+/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
+ *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+ *  calculation. 0: SHA is idle.
+ */
+#define ECDSA_SHA_BUSY    (BIT(0))
+#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
+#define ECDSA_SHA_BUSY_V  0x00000001U
+#define ECDSA_SHA_BUSY_S  0
+
+/** ECDSA_MESSAGE_MEM register
+ *  The memory that stores message.
+ */
+#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
+#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
+
+/** ECDSA_R_MEM register
+ *  The memory that stores r.
+ */
+#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x340)
+#define ECDSA_R_MEM_SIZE_BYTES 32
+
+/** ECDSA_S_MEM register
+ *  The memory that stores s.
+ */
+#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x360)
+#define ECDSA_S_MEM_SIZE_BYTES 32
+
+/** ECDSA_Z_MEM register
+ *  The memory that stores software written z.
+ */
+#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x380)
+#define ECDSA_Z_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAX_MEM register
+ *  The memory that stores x coordinates of QA or software written k.
+ */
+#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x3a0)
+#define ECDSA_QAX_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAY_MEM register
+ *  The memory that stores y coordinates of QA.
+ */
+#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x3c0)
+#define ECDSA_QAY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/ecdsa_struct.h b/components/soc/esp32c61/register/soc/ecdsa_struct.h
new file mode 100644
index 00000000000..858a4ffc5f8
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/ecdsa_struct.h
@@ -0,0 +1,356 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Data Memory */
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  ECDSA configure register
+ */
+typedef union {
+    struct {
+        /** work_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+         *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+         */
+        uint32_t work_mode:2;
+        /** ecc_curve : R/W; bitpos: [2]; default: 0;
+         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
+         */
+        uint32_t ecc_curve:1;
+        /** software_set_k : R/W; bitpos: [3]; default: 0;
+         *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+         *  written by software.
+         */
+        uint32_t software_set_k:1;
+        /** software_set_z : R/W; bitpos: [4]; default: 0;
+         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+         *  software.
+         */
+        uint32_t software_set_z:1;
+        /** deterministic_k : R/W; bitpos: [5]; default: 0;
+         *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+         *  deterministic derivation algorithm.
+         */
+        uint32_t deterministic_k:1;
+        /** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
+         *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
+         */
+        uint32_t deterministic_loop:16;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} ecdsa_conf_reg_t;
+
+/** Type of start register
+ *  ECDSA start register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+         *  after configuration.
+         */
+        uint32_t start:1;
+        /** load_done : WT; bitpos: [1]; default: 0;
+         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t load_done:1;
+        /** get_done : WT; bitpos: [2]; default: 0;
+         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t get_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_start_reg_t;
+
+
+/** Group: Clock and reset registers */
+/** Type of clk register
+ *  ECDSA clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_gate_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECDSA interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        /** sha_release_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECDSA interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        /** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECDSA interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        /** sha_release_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_clr_reg_t;
+
+
+/** Group: Status registers */
+/** Type of state register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** busy : RO; bitpos: [1:0]; default: 0;
+         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+         *  state.
+         */
+        uint32_t busy:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of result register
+ *  ECDSA result register
+ */
+typedef union {
+    struct {
+        /** operation_result : RO/SS; bitpos: [0]; default: 0;
+         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+         *  done.
+         */
+        uint32_t operation_result:1;
+        /** k_value_warning : RO/SS; bitpos: [1]; default: 0;
+         *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
+         *  curve order, then actually taken k = k mod n.
+         */
+        uint32_t k_value_warning:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_result_reg_t;
+
+
+/** Group: SHA register */
+/** Type of sha_mode register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
+         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
+         *  Others: invalid.
+         */
+        uint32_t sha_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_sha_mode_reg_t;
+
+/** Type of sha_start register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_start_reg_t;
+
+/** Type of sha_continue register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_continue : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_continue_reg_t;
+
+/** Type of sha_busy register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** sha_busy : RO; bitpos: [0]; default: 0;
+         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+         *  calculation. 0: SHA is idle.
+         */
+        uint32_t sha_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_busy_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36725040;
+         *  ECDSA version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecdsa_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile ecdsa_conf_reg_t conf;
+    volatile ecdsa_clk_reg_t clk;
+    volatile ecdsa_int_raw_reg_t int_raw;
+    volatile ecdsa_int_st_reg_t int_st;
+    volatile ecdsa_int_ena_reg_t int_ena;
+    volatile ecdsa_int_clr_reg_t int_clr;
+    volatile ecdsa_start_reg_t start;
+    volatile ecdsa_state_reg_t state;
+    volatile ecdsa_result_reg_t result;
+    uint32_t reserved_028[53];
+    volatile ecdsa_date_reg_t date;
+    uint32_t reserved_100[64];
+    volatile ecdsa_sha_mode_reg_t sha_mode;
+    uint32_t reserved_204[3];
+    volatile ecdsa_sha_start_reg_t sha_start;
+    volatile ecdsa_sha_continue_reg_t sha_continue;
+    volatile ecdsa_sha_busy_reg_t sha_busy;
+    uint32_t reserved_21c[25];
+    volatile uint32_t message[8];
+    uint32_t reserved_2a0[40];
+    volatile uint32_t r[8];
+    volatile uint32_t s[8];
+    volatile uint32_t z[8];
+    volatile uint32_t qax[8];
+    volatile uint32_t qay[8];
+} ecdsa_dev_t;
+
+extern ecdsa_dev_t ECDSA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecdsa_dev_t) == 0x3e0, "Invalid size of ecdsa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/efuse_reg.h b/components/soc/esp32c61/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..fa1866d0239
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/efuse_reg.h
@@ -0,0 +1,4145 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Represents pgm_data0
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE0_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Represents pgm_data1
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE0_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Represents pgm_data2
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE0_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Represents pgm_data3
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE0_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Represents pgm_data4
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE0_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Represents pgm_data5
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE0_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Represents pgm_data6
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE0_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Represents pgm_data7
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE0_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Represents pgm_check_value0
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE0_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Represents pgm_check_value1
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE0_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Represents pgm_check_value2
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE0_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS0_REG register
+ *  Represents rd_wr_dis
+ */
+#define EFUSE_RD_WR_DIS0_REG (DR_REG_EFUSE0_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled or
+ *  enabled.\\ 1: Disabled\\ 0: Enabled\\
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE0_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+ *  enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_DIS_ICACHE : RO; bitpos: [7]; default: 0;
+ *  Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_ICACHE    (BIT(7))
+#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
+#define EFUSE_DIS_ICACHE_V  0x00000001U
+#define EFUSE_DIS_ICACHE_S  7
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [8]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
+ *  disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(8))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  8
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [9]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
+ *  enabled\\
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  9
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [10]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(10))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  10
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [11]; default: 0;
+ *  Represents whether SPI0 controller during boot_mode_download is disabled or
+ *  enabled.\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(11))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  11
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [12]; default: 0;
+ *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ *  is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(12))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  12
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [13]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
+ *  0: enabled\\
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(13))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  13
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [14]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode).\\ 1: disabled\\ 0: enabled\\
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(14))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  14
+/** EFUSE_USB_DREFH : RO; bitpos: [16:15]; default: 0;
+ *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
+ */
+#define EFUSE_USB_DREFH    0x00000003U
+#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
+#define EFUSE_USB_DREFH_V  0x00000003U
+#define EFUSE_USB_DREFH_S  15
+/** EFUSE_USB_DREFL : RO; bitpos: [18:17]; default: 0;
+ *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
+ */
+#define EFUSE_USB_DREFL    0x00000003U
+#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
+#define EFUSE_USB_DREFL_V  0x00000003U
+#define EFUSE_USB_DREFL_S  17
+/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [19]; default: 0;
+ *  Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not
+ *  exchanged\\
+ */
+#define EFUSE_USB_EXCHG_PINS    (BIT(19))
+#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
+#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_S  19
+/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [20]; default: 0;
+ *  Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not
+ *  functioned\\
+ */
+#define EFUSE_VDD_SPI_AS_GPIO    (BIT(20))
+#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
+#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_S  20
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [22:21]; default: 0;
+ *  Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original
+ *  threshold configuration value of STG0 *2 \\1: Original threshold configuration
+ *  value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3:
+ *  Original threshold configuration value of STG0 *16 \\
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  21
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [25:23]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
+ *  1: enabled\\ Even number of 1: disabled\\
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  23
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [26]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
+ *  enabled\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(26))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  26
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [27]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
+ *  enabled\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(27))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  27
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [28]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
+ *  enabled\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(28))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  28
+/** EFUSE_RD_RESERVE_0_61 : RW; bitpos: [31:29]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_61    0x00000007U
+#define EFUSE_RD_RESERVE_0_61_M  (EFUSE_RD_RESERVE_0_61_V << EFUSE_RD_RESERVE_0_61_S)
+#define EFUSE_RD_RESERVE_0_61_V  0x00000007U
+#define EFUSE_RD_RESERVE_0_61_S  29
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE0_BASE + 0x34)
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [3:0]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  0
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [7:4]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  4
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [11:8]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  8
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [15:12]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  12
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [19:16]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  16
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [23:20]; default: 0;
+ *  Represents the purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  20
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [25:24]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  24
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [26]; default: 0;
+ *  Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(26))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  26
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [27]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
+ *  enabled.\\ 0: disabled\\
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(27))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  27
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is programmed value. Otherwise, the waiting time is
+ *  2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE0_BASE + 0x38)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0:
+ *  Enable\\
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1.
+ *  Disable\\ 0: Enable\\
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [3]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
+ *  1: Disable\\ 0: Enable\\
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(3))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  3
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [4]; default: 0;
+ *  Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0:
+ *  Disable\\
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(4))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  4
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [6:5]; default: 0;
+ *  Represents the types of UART printing.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  5
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [7]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(7))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  7
+/** EFUSE_SECURE_VERSION : RO; bitpos: [23:8]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  8
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [24]; default: 0;
+ *  Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is
+ *  enable.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(24))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  24
+/** EFUSE_HYS_EN_PAD : RO; bitpos: [25]; default: 0;
+ *  Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
+ *  enabled\\ 0:disabled\\
+ */
+#define EFUSE_HYS_EN_PAD    (BIT(25))
+#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
+#define EFUSE_HYS_EN_PAD_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_S  25
+/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [26]; default: 0;
+ *  Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0:
+ *  Disable\\
+ */
+#define EFUSE_XTS_DPA_CLK_ENABLE    (BIT(26))
+#define EFUSE_XTS_DPA_CLK_ENABLE_M  (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S)
+#define EFUSE_XTS_DPA_CLK_ENABLE_V  0x00000001U
+#define EFUSE_XTS_DPA_CLK_ENABLE_S  26
+/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0;
+ *  Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1:
+ *  Low\\ 0: Decided by register configuration\\
+ */
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL    0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S)
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V  0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S  27
+/** EFUSE_DIS_WIFI6 : RO; bitpos: [29]; default: 0;
+ *  Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is
+ *  disable\\ 0: WiFi 6 is enabled.\\
+ */
+#define EFUSE_DIS_WIFI6    (BIT(29))
+#define EFUSE_DIS_WIFI6_M  (EFUSE_DIS_WIFI6_V << EFUSE_DIS_WIFI6_S)
+#define EFUSE_DIS_WIFI6_V  0x00000001U
+#define EFUSE_DIS_WIFI6_S  29
+/** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [30]; default: 0;
+ *  Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable.
+ */
+#define EFUSE_ECDSA_DISABLE_P192    (BIT(30))
+#define EFUSE_ECDSA_DISABLE_P192_M  (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S)
+#define EFUSE_ECDSA_DISABLE_P192_V  0x00000001U
+#define EFUSE_ECDSA_DISABLE_P192_S  30
+/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [31]; default: 0;
+ *  Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
+ *  \\ 0: Disable.
+ */
+#define EFUSE_ECC_FORCE_CONST_TIME    (BIT(31))
+#define EFUSE_ECC_FORCE_CONST_TIME_M  (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S)
+#define EFUSE_ECC_FORCE_CONST_TIME_V  0x00000001U
+#define EFUSE_ECC_FORCE_CONST_TIME_S  31
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE0_BASE + 0x3c)
+/** EFUSE_RD_REPEAT_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RD_REPEAT_DATA3    0xFFFFFFFFU
+#define EFUSE_RD_REPEAT_DATA3_M  (EFUSE_RD_REPEAT_DATA3_V << EFUSE_RD_REPEAT_DATA3_S)
+#define EFUSE_RD_REPEAT_DATA3_V  0xFFFFFFFFU
+#define EFUSE_RD_REPEAT_DATA3_S  0
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE0_BASE + 0x40)
+/** EFUSE_RD_REPEAT_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RD_REPEAT_DATA4    0xFFFFFFFFU
+#define EFUSE_RD_REPEAT_DATA4_M  (EFUSE_RD_REPEAT_DATA4_V << EFUSE_RD_REPEAT_DATA4_S)
+#define EFUSE_RD_REPEAT_DATA4_V  0xFFFFFFFFU
+#define EFUSE_RD_REPEAT_DATA4_S  0
+
+/** EFUSE_RD_MAC_SYS0_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE0_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents MAC address. Low 32-bit.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SYS1_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE0_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Represents MAC address. High 16-bit.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_RD_RESERVE_1_48 : RW; bitpos: [31:16]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_1_48    0x0000FFFFU
+#define EFUSE_RD_RESERVE_1_48_M  (EFUSE_RD_RESERVE_1_48_V << EFUSE_RD_RESERVE_1_48_S)
+#define EFUSE_RD_RESERVE_1_48_V  0x0000FFFFU
+#define EFUSE_RD_RESERVE_1_48_S  16
+
+/** EFUSE_RD_MAC_SYS2_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE0_BASE + 0x4c)
+/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
+ *  Minor chip version
+ */
+#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_S  0
+/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
+ *  Major chip version
+ */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  4
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(6))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  6
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
+ *  BLK_VERSION_MINOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  8
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  11
+/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0;
+ *  Flash capacity
+ */
+#define EFUSE_FLASH_CAP    0x00000007U
+#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
+#define EFUSE_FLASH_CAP_V  0x00000007U
+#define EFUSE_FLASH_CAP_S  13
+/** EFUSE_FLASH_VENDOR : R; bitpos: [18:16]; default: 0;
+ *  Flash vendor
+ */
+#define EFUSE_FLASH_VENDOR    0x00000007U
+#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
+#define EFUSE_FLASH_VENDOR_V  0x00000007U
+#define EFUSE_FLASH_VENDOR_S  16
+/** EFUSE_PSRAM_CAP : R; bitpos: [21:19]; default: 0;
+ *  PSRAM capacity
+ */
+#define EFUSE_PSRAM_CAP    0x00000007U
+#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
+#define EFUSE_PSRAM_CAP_V  0x00000007U
+#define EFUSE_PSRAM_CAP_S  19
+/** EFUSE_PSRAM_VENDOR : R; bitpos: [23:22]; default: 0;
+ *  PSRAM vendor
+ */
+#define EFUSE_PSRAM_VENDOR    0x00000003U
+#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
+#define EFUSE_PSRAM_VENDOR_V  0x00000003U
+#define EFUSE_PSRAM_VENDOR_S  22
+/** EFUSE_TEMP : R; bitpos: [25:24]; default: 0;
+ *  Temperature
+ */
+#define EFUSE_TEMP    0x00000003U
+#define EFUSE_TEMP_M  (EFUSE_TEMP_V << EFUSE_TEMP_S)
+#define EFUSE_TEMP_V  0x00000003U
+#define EFUSE_TEMP_S  24
+/** EFUSE_PKG_VERSION : R; bitpos: [28:26]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  26
+/** EFUSE_RESERVED_1_93 : R; bitpos: [31:29]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_93    0x00000007U
+#define EFUSE_RESERVED_1_93_M  (EFUSE_RESERVED_1_93_V << EFUSE_RESERVED_1_93_S)
+#define EFUSE_RESERVED_1_93_V  0x00000007U
+#define EFUSE_RESERVED_1_93_S  29
+
+/** EFUSE_RD_MAC_SYS3_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE0_BASE + 0x50)
+/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_MAC_RESERVED_2    0x0003FFFFU
+#define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
+#define EFUSE_MAC_RESERVED_2_V  0x0003FFFFU
+#define EFUSE_MAC_RESERVED_2_S  0
+/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
+ *  Represents the first 14-bit of zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
+#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
+#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
+#define EFUSE_SYS_DATA_PART0_0_S  18
+
+/** EFUSE_RD_MAC_SYS4_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE0_BASE + 0x54)
+/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the first 14-bit of zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
+#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_1_S  0
+
+/** EFUSE_RD_MAC_SYS5_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE0_BASE + 0x58)
+/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the second 32-bit of zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Represents rd_sys_part1_data0
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE0_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Represents rd_sys_part1_data1
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE0_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Represents rd_sys_part1_data2
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE0_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Represents rd_sys_part1_data3
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE0_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Represents rd_sys_part1_data4
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE0_BASE + 0x6c)
+/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMPERATURE_SENSOR    0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_M  (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
+#define EFUSE_TEMPERATURE_SENSOR_V  0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_S  0
+/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
+ *  ADC OCode calibration
+ */
+#define EFUSE_OCODE    0x000000FFU
+#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
+#define EFUSE_OCODE_V  0x000000FFU
+#define EFUSE_OCODE_S  9
+/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_S)
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_S  17
+/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
+ *  Average initcode of ADC1 atten1
+ */
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1    0x0000001FU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_M  (EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_S)
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_V  0x0000001FU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_S  27
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Represents rd_sys_part1_data5
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE0_BASE + 0x70)
+/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
+ *  Average initcode of ADC1 atten1
+ */
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1    0x0000001FU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_M  (EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_S)
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_V  0x0000001FU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_S  0
+/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
+ *  Average initcode of ADC1 atten2
+ */
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_M  (EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_S)
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_S  5
+/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
+ *  Average initcode of ADC1 atten3
+ */
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_S)
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_S  15
+/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
+ *  HI_DOUT of ADC1 atten0
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0    0x0000007FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_V  0x0000007FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_S  25
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Represents rd_sys_part1_data6
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE0_BASE + 0x74)
+/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
+ *  HI_DOUT of ADC1 atten0
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1    0x00000007U
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V  0x00000007U
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S  0
+/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
+ *  HI_DOUT of ADC1 atten1
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_S  3
+/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
+ *  HI_DOUT of ADC1 atten2
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_M  (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_S  13
+/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
+ *  HI_DOUT of ADC1 atten3
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3    0x000001FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_V  0x000001FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_S  23
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Represents rd_sys_part1_data7
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE0_BASE + 0x78)
+/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
+ *  HI_DOUT of ADC1 atten3
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1    (BIT(0))
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V  0x00000001U
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S  0
+/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
+ *  Gap between ADC1 CH0 and average initcode
+ */
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S  1
+/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
+ *  Gap between ADC1 CH1 and average initcode
+ */
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S  5
+/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
+ *  Gap between ADC1 CH2 and average initcode
+ */
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S  9
+/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
+ *  Gap between ADC1 CH3 and average initcode
+ */
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S  13
+/** EFUSE_RESERVED_2_241 : R; bitpos: [31:17]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_241    0x00007FFFU
+#define EFUSE_RESERVED_2_241_M  (EFUSE_RESERVED_2_241_V << EFUSE_RESERVED_2_241_S)
+#define EFUSE_RESERVED_2_241_V  0x00007FFFU
+#define EFUSE_RESERVED_2_241_S  17
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Represents rd_usr_data0
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE0_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Represents rd_usr_data1
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE0_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Represents rd_usr_data2
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE0_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Represents rd_usr_data3
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE0_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Represents rd_usr_data4
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE0_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Represents rd_usr_data5
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE0_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Represents rd_usr_data6
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE0_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Represents rd_usr_data7
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE0_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Represents rd_key0_data0
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE0_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Represents rd_key0_data1
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE0_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Represents rd_key0_data2
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE0_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Represents rd_key0_data3
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE0_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Represents rd_key0_data4
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE0_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Represents rd_key0_data5
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE0_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Represents rd_key0_data6
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE0_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Represents rd_key0_data7
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE0_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Represents rd_key1_data0
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE0_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Represents rd_key1_data1
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE0_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Represents rd_key1_data2
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE0_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Represents rd_key1_data3
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE0_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Represents rd_key1_data4
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE0_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Represents rd_key1_data5
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE0_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Represents rd_key1_data6
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE0_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Represents rd_key1_data7
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE0_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Represents rd_key2_data0
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE0_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Represents rd_key2_data1
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE0_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Represents rd_key2_data2
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE0_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Represents rd_key2_data3
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE0_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Represents rd_key2_data4
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE0_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Represents rd_key2_data5
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE0_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Represents rd_key2_data6
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE0_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Represents rd_key2_data7
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE0_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Represents rd_key3_data0
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE0_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Represents rd_key3_data1
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE0_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Represents rd_key3_data2
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE0_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Represents rd_key3_data3
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE0_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Represents rd_key3_data4
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE0_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Represents rd_key3_data5
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE0_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Represents rd_key3_data6
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE0_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Represents rd_key3_data7
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE0_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Represents rd_key4_data0
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE0_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Represents rd_key4_data1
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE0_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Represents rd_key4_data2
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE0_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Represents rd_key4_data3
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE0_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Represents rd_key4_data4
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE0_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Represents rd_key4_data5
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE0_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Represents rd_key4_data6
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE0_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Represents rd_key4_data7
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE0_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Represents rd_key5_data0
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE0_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Represents rd_key5_data1
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE0_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Represents rd_key5_data2
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE0_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Represents rd_key5_data3
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE0_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Represents rd_key5_data4
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE0_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Represents rd_key5_data5
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE0_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Represents rd_key5_data6
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE0_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Represents rd_key5_data7
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE0_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Represents rd_sys_part2_data0
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE0_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Represents rd_sys_part2_data1
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE0_BASE + 0x160)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Represents rd_sys_part2_data2
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE0_BASE + 0x164)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Represents rd_sys_part2_data3
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE0_BASE + 0x168)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Represents rd_sys_part2_data4
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE0_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Represents rd_sys_part2_data5
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE0_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Represents rd_sys_part2_data6
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE0_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Represents rd_sys_part2_data7
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE0_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_DATA_ERR0_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE0_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Represents the programming error of EFUSE_RD_DIS
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [7]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_ICACHE
+ */
+#define EFUSE_DIS_ICACHE_ERR    (BIT(7))
+#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
+#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_ICACHE_ERR_S  7
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [8]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_JTAG
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(8))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  8
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  9
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [10]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(10))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  10
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [11]; default: 0;
+ *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(11))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  11
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [12]; default: 0;
+ *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(12))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  12
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [13]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_PAD_JTAG
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(13))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  13
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [14]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(14))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  14
+/** EFUSE_USB_DREFH_ERR : RO; bitpos: [16:15]; default: 0;
+ *  Represents the programming error of EFUSE_USB_DREFH
+ */
+#define EFUSE_USB_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
+#define EFUSE_USB_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DREFH_ERR_S  15
+/** EFUSE_USB_DREFL_ERR : RO; bitpos: [18:17]; default: 0;
+ *  Represents the programming error of EFUSE_USB_DREFL
+ */
+#define EFUSE_USB_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
+#define EFUSE_USB_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DREFL_ERR_S  17
+/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [19]; default: 0;
+ *  Represents the programming error of EFUSE_USB_EXCHG_PINS
+ */
+#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(19))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_ERR_S  19
+/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [20]; default: 0;
+ *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
+ */
+#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(20))
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  20
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  21
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [25:23]; default: 0;
+ *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  23
+/** EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR : RO; bitpos: [26]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_0
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR    (BIT(26))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_0_ERR_S  26
+/** EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR : RO; bitpos: [27]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_1
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR    (BIT(27))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_1_ERR_S  27
+/** EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR : RO; bitpos: [28]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_2
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR    (BIT(28))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE_2_ERR_S  28
+
+/** EFUSE_RD_REPEAT_DATA_ERR1_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE0_BASE + 0x180)
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_0
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  0
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [7:4]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_1
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  4
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [11:8]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_2
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  8
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_3
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  12
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [19:16]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_4
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  16
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [23:20]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_5
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  20
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [25:24]; default: 0;
+ *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  24
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [26]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_EN
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(26))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  26
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [27]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(27))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  27
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Represents the programming error of EFUSE_FLASH_TPUW
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_DATA_ERR2_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE0_BASE + 0x184)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [3]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(3))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  3
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [4]; default: 0;
+ *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(4))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  4
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [6:5]; default: 0;
+ *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  5
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [7]; default: 0;
+ *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(7))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  7
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [23:8]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_VERSION
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  8
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [24]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(24))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  24
+/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [25]; default: 0;
+ *  Represents the programming error of EFUSE_HYS_EN_PAD
+ */
+#define EFUSE_HYS_EN_PAD_ERR    (BIT(25))
+#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
+#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_ERR_S  25
+/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [26]; default: 0;
+ *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+ */
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR    (BIT(26))
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M  (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S)
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V  0x00000001U
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S  26
+/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [28:27]; default: 0;
+ *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+ */
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR    0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S)
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V  0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S  27
+/** EFUSE_DIS_WIFI6_ERR : RO; bitpos: [29]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_WIFI6
+ */
+#define EFUSE_DIS_WIFI6_ERR    (BIT(29))
+#define EFUSE_DIS_WIFI6_ERR_M  (EFUSE_DIS_WIFI6_ERR_V << EFUSE_DIS_WIFI6_ERR_S)
+#define EFUSE_DIS_WIFI6_ERR_V  0x00000001U
+#define EFUSE_DIS_WIFI6_ERR_S  29
+/** EFUSE_ECDSA_DISABLE_P192_ERR : RO; bitpos: [30]; default: 0;
+ *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
+ */
+#define EFUSE_ECDSA_DISABLE_P192_ERR    (BIT(30))
+#define EFUSE_ECDSA_DISABLE_P192_ERR_M  (EFUSE_ECDSA_DISABLE_P192_ERR_V << EFUSE_ECDSA_DISABLE_P192_ERR_S)
+#define EFUSE_ECDSA_DISABLE_P192_ERR_V  0x00000001U
+#define EFUSE_ECDSA_DISABLE_P192_ERR_S  30
+/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [31]; default: 0;
+ *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+ */
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR    (BIT(31))
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M  (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S)
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V  0x00000001U
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S  31
+
+/** EFUSE_RD_REPEAT_DATA_ERR3_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE0_BASE + 0x188)
+/** EFUSE_RD_REPEAT_DATA_ERR3 : RO; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR3    0xFFFFFFFFU
+#define EFUSE_RD_REPEAT_DATA_ERR3_M  (EFUSE_RD_REPEAT_DATA_ERR3_V << EFUSE_RD_REPEAT_DATA_ERR3_S)
+#define EFUSE_RD_REPEAT_DATA_ERR3_V  0xFFFFFFFFU
+#define EFUSE_RD_REPEAT_DATA_ERR3_S  0
+
+/** EFUSE_RD_REPEAT_DATA_ERR4_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE0_BASE + 0x18c)
+/** EFUSE_RD_REPEAT_DATA_ERR4 : RO; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR4    0xFFFFFFFFU
+#define EFUSE_RD_REPEAT_DATA_ERR4_M  (EFUSE_RD_REPEAT_DATA_ERR4_V << EFUSE_RD_REPEAT_DATA_ERR4_S)
+#define EFUSE_RD_REPEAT_DATA_ERR4_V  0xFFFFFFFFU
+#define EFUSE_RD_REPEAT_DATA_ERR4_S  0
+
+/** EFUSE_RD_RS_DATA_ERR0_REG register
+ *  Represents rd_rs_data_err
+ */
+#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE0_BASE + 0x190)
+/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS_ERR_NUM    0x00000007U
+#define EFUSE_RD_MAC_SYS_ERR_NUM_M  (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S)
+#define EFUSE_RD_MAC_SYS_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_MAC_SYS_ERR_NUM_S  0
+/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
+ *  of error bytes is over 6.
+ */
+#define EFUSE_RD_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_RD_MAC_SYS_FAIL_M  (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S)
+#define EFUSE_RD_MAC_SYS_FAIL_V  0x00000001U
+#define EFUSE_RD_MAC_SYS_FAIL_S  3
+/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_sys_part1_data
+ */
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S)
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S  4
+/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
+ *  and the number of error bytes is over 6.
+ */
+#define EFUSE_RD_SYS_PART1_DATA_FAIL    (BIT(7))
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_M  (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S)
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_S  7
+/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_usr_data
+ */
+#define EFUSE_RD_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_USR_DATA_ERR_NUM_M  (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S)
+#define EFUSE_RD_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_USR_DATA_ERR_NUM_S  8
+/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_RD_USR_DATA_FAIL_M  (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S)
+#define EFUSE_RD_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_USR_DATA_FAIL_S  11
+/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key0_data
+ */
+#define EFUSE_RD_KEY0_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_M  (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_S  12
+/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY0_DATA_FAIL    (BIT(15))
+#define EFUSE_RD_KEY0_DATA_FAIL_M  (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S)
+#define EFUSE_RD_KEY0_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY0_DATA_FAIL_S  15
+/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key1_data
+ */
+#define EFUSE_RD_KEY1_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_M  (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_S  16
+/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY1_DATA_FAIL    (BIT(19))
+#define EFUSE_RD_KEY1_DATA_FAIL_M  (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S)
+#define EFUSE_RD_KEY1_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY1_DATA_FAIL_S  19
+/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key2_data
+ */
+#define EFUSE_RD_KEY2_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_M  (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_S  20
+/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY2_DATA_FAIL    (BIT(23))
+#define EFUSE_RD_KEY2_DATA_FAIL_M  (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S)
+#define EFUSE_RD_KEY2_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY2_DATA_FAIL_S  23
+/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key3_data
+ */
+#define EFUSE_RD_KEY3_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_M  (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_S  24
+/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY3_DATA_FAIL    (BIT(27))
+#define EFUSE_RD_KEY3_DATA_FAIL_M  (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S)
+#define EFUSE_RD_KEY3_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY3_DATA_FAIL_S  27
+/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key4_data
+ */
+#define EFUSE_RD_KEY4_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_M  (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_S  28
+/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY4_DATA_FAIL    (BIT(31))
+#define EFUSE_RD_KEY4_DATA_FAIL_M  (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S)
+#define EFUSE_RD_KEY4_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY4_DATA_FAIL_S  31
+
+/** EFUSE_RD_RS_DATA_ERR1_REG register
+ *  Represents rd_rs_data_err
+ */
+#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE0_BASE + 0x194)
+/** EFUSE_RD_KEY5_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_key5_data
+ */
+#define EFUSE_RD_KEY5_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_M  (EFUSE_RD_KEY5_DATA_ERR_NUM_V << EFUSE_RD_KEY5_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY5_DATA_ERR_NUM_S  0
+/** EFUSE_RD_KEY5_DATA_FAIL : RO; bitpos: [3]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
+ *  number of error bytes is over 6.
+ */
+#define EFUSE_RD_KEY5_DATA_FAIL    (BIT(3))
+#define EFUSE_RD_KEY5_DATA_FAIL_M  (EFUSE_RD_KEY5_DATA_FAIL_V << EFUSE_RD_KEY5_DATA_FAIL_S)
+#define EFUSE_RD_KEY5_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY5_DATA_FAIL_S  3
+/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  Represents the error number of registers.\\The value of this signal means the
+ *  number of error bytes in rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S)
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S  4
+/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [7]; default: 0;
+ *  Represents error status of register.\\0: Means no failure and that the data of
+ *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
+ *  and the number of error bytes is over 6.
+ */
+#define EFUSE_RD_SYS_PART2_DATA_FAIL    (BIT(7))
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_M  (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S)
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_S  7
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE0_BASE + 0x198)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37753088;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE0_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to force enable eFuse register configuration clock signal.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE0_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
+ *  Configures which block to use for ECDSA key output.
+ */
+#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
+#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_S  16
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE0_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Indicates the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Indicates which block is used for ECDSA key output.
+ */
+#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
+#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_S  20
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE0_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE0_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE0_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE0_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE0_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE0_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE0_BASE + 0x1ec)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
+ *  Configures the waiting time of reading eFuse memory.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE0_BASE + 0x1f0)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 12288;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE0_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200;
+ *  Configures the active programming time.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE0_BASE + 0x1f8)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to bypass reed solomon correction step.
+ */
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures block number of programming twice operation.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Set this bit to update multi-bit register signals.
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
+
+/** EFUSE_APB2OTP_WR_DIS_REG register
+ *  eFuse apb2otp block0 data register1.
+ */
+#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE0_BASE + 0x500)
+/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 write disable data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
+ *  eFuse apb2otp block0 data register2.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE0_BASE + 0x504)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
+ *  eFuse apb2otp block0 data register3.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE0_BASE + 0x508)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
+ *  eFuse apb2otp block0 data register4.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE0_BASE + 0x50c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
+ *  eFuse apb2otp block0 data register5.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE0_BASE + 0x510)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
+ *  eFuse apb2otp block0 data register6.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE0_BASE + 0x514)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
+ *  eFuse apb2otp block0 data register7.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE0_BASE + 0x518)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
+ *  eFuse apb2otp block0 data register8.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE0_BASE + 0x51c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
+ *  eFuse apb2otp block0 data register9.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE0_BASE + 0x520)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
+ *  eFuse apb2otp block0 data register10.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE0_BASE + 0x524)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
+ *  eFuse apb2otp block0 data register11.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE0_BASE + 0x528)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
+ *  eFuse apb2otp block0 data register12.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE0_BASE + 0x52c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
+ *  eFuse apb2otp block0 data register13.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE0_BASE + 0x530)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
+ *  eFuse apb2otp block0 data register14.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE0_BASE + 0x534)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
+ *  eFuse apb2otp block0 data register15.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE0_BASE + 0x538)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
+ *  eFuse apb2otp block0 data register16.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE0_BASE + 0x53c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
+ *  eFuse apb2otp block0 data register17.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE0_BASE + 0x540)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
+ *  eFuse apb2otp block0 data register18.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE0_BASE + 0x544)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
+ *  eFuse apb2otp block0 data register19.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE0_BASE + 0x548)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
+ *  eFuse apb2otp block0 data register20.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE0_BASE + 0x54c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
+ *  eFuse apb2otp block0 data register21.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE0_BASE + 0x550)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W1_REG register
+ *  eFuse apb2otp block1 data register1.
+ */
+#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE0_BASE + 0x554)
+/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
+#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK1_W2_REG register
+ *  eFuse apb2otp block1 data register2.
+ */
+#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE0_BASE + 0x558)
+/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
+#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK1_W3_REG register
+ *  eFuse apb2otp block1 data register3.
+ */
+#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE0_BASE + 0x55c)
+/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
+#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK1_W4_REG register
+ *  eFuse apb2otp block1 data register4.
+ */
+#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE0_BASE + 0x560)
+/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
+#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK1_W5_REG register
+ *  eFuse apb2otp block1 data register5.
+ */
+#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE0_BASE + 0x564)
+/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
+#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W6_REG register
+ *  eFuse apb2otp block1 data register6.
+ */
+#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE0_BASE + 0x568)
+/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
+#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_S  0
+
+/** EFUSE_APB2OTP_BLK1_W7_REG register
+ *  eFuse apb2otp block1 data register7.
+ */
+#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE0_BASE + 0x56c)
+/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
+#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_S  0
+
+/** EFUSE_APB2OTP_BLK1_W8_REG register
+ *  eFuse apb2otp block1 data register8.
+ */
+#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE0_BASE + 0x570)
+/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
+#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_S  0
+
+/** EFUSE_APB2OTP_BLK1_W9_REG register
+ *  eFuse apb2otp block1 data register9.
+ */
+#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE0_BASE + 0x574)
+/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
+#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W1_REG register
+ *  eFuse apb2otp block2 data register1.
+ */
+#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE0_BASE + 0x578)
+/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
+#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK2_W2_REG register
+ *  eFuse apb2otp block2 data register2.
+ */
+#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE0_BASE + 0x57c)
+/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
+#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK2_W3_REG register
+ *  eFuse apb2otp block2 data register3.
+ */
+#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE0_BASE + 0x580)
+/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
+#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK2_W4_REG register
+ *  eFuse apb2otp block2 data register4.
+ */
+#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE0_BASE + 0x584)
+/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
+#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK2_W5_REG register
+ *  eFuse apb2otp block2 data register5.
+ */
+#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE0_BASE + 0x588)
+/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
+#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK2_W6_REG register
+ *  eFuse apb2otp block2 data register6.
+ */
+#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE0_BASE + 0x58c)
+/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
+#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_S  0
+
+/** EFUSE_APB2OTP_BLK2_W7_REG register
+ *  eFuse apb2otp block2 data register7.
+ */
+#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE0_BASE + 0x590)
+/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
+#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_S  0
+
+/** EFUSE_APB2OTP_BLK2_W8_REG register
+ *  eFuse apb2otp block2 data register8.
+ */
+#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE0_BASE + 0x594)
+/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
+#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_S  0
+
+/** EFUSE_APB2OTP_BLK2_W9_REG register
+ *  eFuse apb2otp block2 data register9.
+ */
+#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE0_BASE + 0x598)
+/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
+#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W10_REG register
+ *  eFuse apb2otp block2 data register10.
+ */
+#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE0_BASE + 0x59c)
+/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
+#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_S  0
+
+/** EFUSE_APB2OTP_BLK2_W11_REG register
+ *  eFuse apb2otp block2 data register11.
+ */
+#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE0_BASE + 0x5a0)
+/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
+#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_S  0
+
+/** EFUSE_APB2OTP_BLK3_W1_REG register
+ *  eFuse apb2otp block3 data register1.
+ */
+#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE0_BASE + 0x5a4)
+/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
+#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK3_W2_REG register
+ *  eFuse apb2otp block3 data register2.
+ */
+#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE0_BASE + 0x5a8)
+/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
+#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK3_W3_REG register
+ *  eFuse apb2otp block3 data register3.
+ */
+#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE0_BASE + 0x5ac)
+/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
+#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK3_W4_REG register
+ *  eFuse apb2otp block3 data register4.
+ */
+#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE0_BASE + 0x5b0)
+/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
+#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK3_W5_REG register
+ *  eFuse apb2otp block3 data register5.
+ */
+#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE0_BASE + 0x5b4)
+/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
+#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK3_W6_REG register
+ *  eFuse apb2otp block3 data register6.
+ */
+#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE0_BASE + 0x5b8)
+/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
+#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_S  0
+
+/** EFUSE_APB2OTP_BLK3_W7_REG register
+ *  eFuse apb2otp block3 data register7.
+ */
+#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE0_BASE + 0x5bc)
+/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
+#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_S  0
+
+/** EFUSE_APB2OTP_BLK3_W8_REG register
+ *  eFuse apb2otp block3 data register8.
+ */
+#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE0_BASE + 0x5c0)
+/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
+#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_S  0
+
+/** EFUSE_APB2OTP_BLK3_W9_REG register
+ *  eFuse apb2otp block3 data register9.
+ */
+#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE0_BASE + 0x5c4)
+/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
+#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_S  0
+
+/** EFUSE_APB2OTP_BLK3_W10_REG register
+ *  eFuse apb2otp block3 data register10.
+ */
+#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE0_BASE + 0x5c8)
+/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
+#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_S  0
+
+/** EFUSE_APB2OTP_BLK3_W11_REG register
+ *  eFuse apb2otp block3 data register11.
+ */
+#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE0_BASE + 0x5cc)
+/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
+#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_S  0
+
+/** EFUSE_APB2OTP_BLK4_W1_REG register
+ *  eFuse apb2otp BLOCK7 data register1.
+ */
+#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE0_BASE + 0x5d0)
+/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
+#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK4_W2_REG register
+ *  eFuse apb2otp block4 data register2.
+ */
+#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE0_BASE + 0x5d4)
+/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
+#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK4_W3_REG register
+ *  eFuse apb2otp block4 data register3.
+ */
+#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE0_BASE + 0x5d8)
+/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
+#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK4_W4_REG register
+ *  eFuse apb2otp block4 data register4.
+ */
+#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE0_BASE + 0x5dc)
+/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
+#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK4_W5_REG register
+ *  eFuse apb2otp block4 data register5.
+ */
+#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE0_BASE + 0x5e0)
+/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
+#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK4_W6_REG register
+ *  eFuse apb2otp block4 data register6.
+ */
+#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE0_BASE + 0x5e4)
+/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
+#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_S  0
+
+/** EFUSE_APB2OTP_BLK4_W7_REG register
+ *  eFuse apb2otp block4 data register7.
+ */
+#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE0_BASE + 0x5e8)
+/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
+#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_S  0
+
+/** EFUSE_APB2OTP_BLK4_W8_REG register
+ *  eFuse apb2otp block4 data register8.
+ */
+#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE0_BASE + 0x5ec)
+/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
+#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_S  0
+
+/** EFUSE_APB2OTP_BLK4_W9_REG register
+ *  eFuse apb2otp block4 data register9.
+ */
+#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE0_BASE + 0x5f0)
+/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
+#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_S  0
+
+/** EFUSE_APB2OTP_BLK4_W10_REG register
+ *  eFuse apb2otp block4 data registe10.
+ */
+#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE0_BASE + 0x5f4)
+/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
+#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_S  0
+
+/** EFUSE_APB2OTP_BLK4_W11_REG register
+ *  eFuse apb2otp block4 data register11.
+ */
+#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE0_BASE + 0x5f8)
+/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
+#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_S  0
+
+/** EFUSE_APB2OTP_BLK5_W1_REG register
+ *  eFuse apb2otp block5 data register1.
+ */
+#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE0_BASE + 0x5fc)
+/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
+#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_S  0
+
+/** EFUSE_APB2OTP_BLK5_W2_REG register
+ *  eFuse apb2otp block5 data register2.
+ */
+#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE0_BASE + 0x600)
+/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
+#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_S  0
+
+/** EFUSE_APB2OTP_BLK5_W3_REG register
+ *  eFuse apb2otp block5 data register3.
+ */
+#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE0_BASE + 0x604)
+/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
+#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_S  0
+
+/** EFUSE_APB2OTP_BLK5_W4_REG register
+ *  eFuse apb2otp block5 data register4.
+ */
+#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE0_BASE + 0x608)
+/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
+#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_S  0
+
+/** EFUSE_APB2OTP_BLK5_W5_REG register
+ *  eFuse apb2otp block5 data register5.
+ */
+#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE0_BASE + 0x60c)
+/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
+#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_S  0
+
+/** EFUSE_APB2OTP_BLK5_W6_REG register
+ *  eFuse apb2otp block5 data register6.
+ */
+#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE0_BASE + 0x610)
+/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
+#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_S  0
+
+/** EFUSE_APB2OTP_BLK5_W7_REG register
+ *  eFuse apb2otp block5 data register7.
+ */
+#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE0_BASE + 0x614)
+/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
+#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_S  0
+
+/** EFUSE_APB2OTP_BLK5_W8_REG register
+ *  eFuse apb2otp block5 data register8.
+ */
+#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE0_BASE + 0x618)
+/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
+#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_S  0
+
+/** EFUSE_APB2OTP_BLK5_W9_REG register
+ *  eFuse apb2otp block5 data register9.
+ */
+#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE0_BASE + 0x61c)
+/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
+#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_S  0
+
+/** EFUSE_APB2OTP_BLK5_W10_REG register
+ *  eFuse apb2otp block5 data register10.
+ */
+#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE0_BASE + 0x620)
+/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
+#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_S  0
+
+/** EFUSE_APB2OTP_BLK5_W11_REG register
+ *  eFuse apb2otp block5 data register11.
+ */
+#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE0_BASE + 0x624)
+/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
+#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_S  0
+
+/** EFUSE_APB2OTP_BLK6_W1_REG register
+ *  eFuse apb2otp block6 data register1.
+ */
+#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE0_BASE + 0x628)
+/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
+#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_S  0
+
+/** EFUSE_APB2OTP_BLK6_W2_REG register
+ *  eFuse apb2otp block6 data register2.
+ */
+#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE0_BASE + 0x62c)
+/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
+#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_S  0
+
+/** EFUSE_APB2OTP_BLK6_W3_REG register
+ *  eFuse apb2otp block6 data register3.
+ */
+#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE0_BASE + 0x630)
+/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
+#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_S  0
+
+/** EFUSE_APB2OTP_BLK6_W4_REG register
+ *  eFuse apb2otp block6 data register4.
+ */
+#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE0_BASE + 0x634)
+/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
+#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_S  0
+
+/** EFUSE_APB2OTP_BLK6_W5_REG register
+ *  eFuse apb2otp block6 data register5.
+ */
+#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE0_BASE + 0x638)
+/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
+#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_S  0
+
+/** EFUSE_APB2OTP_BLK6_W6_REG register
+ *  eFuse apb2otp block6 data register6.
+ */
+#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE0_BASE + 0x63c)
+/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
+#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_S  0
+
+/** EFUSE_APB2OTP_BLK6_W7_REG register
+ *  eFuse apb2otp block6 data register7.
+ */
+#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE0_BASE + 0x640)
+/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
+#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_S  0
+
+/** EFUSE_APB2OTP_BLK6_W8_REG register
+ *  eFuse apb2otp block6 data register8.
+ */
+#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE0_BASE + 0x644)
+/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
+#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_S  0
+
+/** EFUSE_APB2OTP_BLK6_W9_REG register
+ *  eFuse apb2otp block6 data register9.
+ */
+#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE0_BASE + 0x648)
+/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
+#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_S  0
+
+/** EFUSE_APB2OTP_BLK6_W10_REG register
+ *  eFuse apb2otp block6 data register10.
+ */
+#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE0_BASE + 0x64c)
+/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
+#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_S  0
+
+/** EFUSE_APB2OTP_BLK6_W11_REG register
+ *  eFuse apb2otp block6 data register11.
+ */
+#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE0_BASE + 0x650)
+/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
+#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_S  0
+
+/** EFUSE_APB2OTP_BLK7_W1_REG register
+ *  eFuse apb2otp block7 data register1.
+ */
+#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE0_BASE + 0x654)
+/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
+#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_S  0
+
+/** EFUSE_APB2OTP_BLK7_W2_REG register
+ *  eFuse apb2otp block7 data register2.
+ */
+#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE0_BASE + 0x658)
+/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
+#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_S  0
+
+/** EFUSE_APB2OTP_BLK7_W3_REG register
+ *  eFuse apb2otp block7 data register3.
+ */
+#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE0_BASE + 0x65c)
+/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
+#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_S  0
+
+/** EFUSE_APB2OTP_BLK7_W4_REG register
+ *  eFuse apb2otp block7 data register4.
+ */
+#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE0_BASE + 0x660)
+/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
+#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_S  0
+
+/** EFUSE_APB2OTP_BLK7_W5_REG register
+ *  eFuse apb2otp block7 data register5.
+ */
+#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE0_BASE + 0x664)
+/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
+#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_S  0
+
+/** EFUSE_APB2OTP_BLK7_W6_REG register
+ *  eFuse apb2otp block7 data register6.
+ */
+#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE0_BASE + 0x668)
+/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
+#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_S  0
+
+/** EFUSE_APB2OTP_BLK7_W7_REG register
+ *  eFuse apb2otp block7 data register7.
+ */
+#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE0_BASE + 0x66c)
+/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
+#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_S  0
+
+/** EFUSE_APB2OTP_BLK7_W8_REG register
+ *  eFuse apb2otp block7 data register8.
+ */
+#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE0_BASE + 0x670)
+/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
+#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_S  0
+
+/** EFUSE_APB2OTP_BLK7_W9_REG register
+ *  eFuse apb2otp block7 data register9.
+ */
+#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE0_BASE + 0x674)
+/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
+#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_S  0
+
+/** EFUSE_APB2OTP_BLK7_W10_REG register
+ *  eFuse apb2otp block7 data register10.
+ */
+#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE0_BASE + 0x678)
+/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
+#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_S  0
+
+/** EFUSE_APB2OTP_BLK7_W11_REG register
+ *  eFuse apb2otp block7 data register11.
+ */
+#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE0_BASE + 0x67c)
+/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
+#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_S  0
+
+/** EFUSE_APB2OTP_BLK8_W1_REG register
+ *  eFuse apb2otp block8 data register1.
+ */
+#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE0_BASE + 0x680)
+/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
+#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_S  0
+
+/** EFUSE_APB2OTP_BLK8_W2_REG register
+ *  eFuse apb2otp block8 data register2.
+ */
+#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE0_BASE + 0x684)
+/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
+#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_S  0
+
+/** EFUSE_APB2OTP_BLK8_W3_REG register
+ *  eFuse apb2otp block8 data register3.
+ */
+#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE0_BASE + 0x688)
+/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
+#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_S  0
+
+/** EFUSE_APB2OTP_BLK8_W4_REG register
+ *  eFuse apb2otp block8 data register4.
+ */
+#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE0_BASE + 0x68c)
+/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
+#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_S  0
+
+/** EFUSE_APB2OTP_BLK8_W5_REG register
+ *  eFuse apb2otp block8 data register5.
+ */
+#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE0_BASE + 0x690)
+/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
+#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_S  0
+
+/** EFUSE_APB2OTP_BLK8_W6_REG register
+ *  eFuse apb2otp block8 data register6.
+ */
+#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE0_BASE + 0x694)
+/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
+#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_S  0
+
+/** EFUSE_APB2OTP_BLK8_W7_REG register
+ *  eFuse apb2otp block8 data register7.
+ */
+#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE0_BASE + 0x698)
+/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
+#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_S  0
+
+/** EFUSE_APB2OTP_BLK8_W8_REG register
+ *  eFuse apb2otp block8 data register8.
+ */
+#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE0_BASE + 0x69c)
+/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
+#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_S  0
+
+/** EFUSE_APB2OTP_BLK8_W9_REG register
+ *  eFuse apb2otp block8 data register9.
+ */
+#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE0_BASE + 0x6a0)
+/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
+#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_S  0
+
+/** EFUSE_APB2OTP_BLK8_W10_REG register
+ *  eFuse apb2otp block8 data register10.
+ */
+#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE0_BASE + 0x6a4)
+/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
+#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_S  0
+
+/** EFUSE_APB2OTP_BLK8_W11_REG register
+ *  eFuse apb2otp block8 data register11.
+ */
+#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE0_BASE + 0x6a8)
+/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
+#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_S  0
+
+/** EFUSE_APB2OTP_BLK9_W1_REG register
+ *  eFuse apb2otp block9 data register1.
+ */
+#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE0_BASE + 0x6ac)
+/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
+#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_S  0
+
+/** EFUSE_APB2OTP_BLK9_W2_REG register
+ *  eFuse apb2otp block9 data register2.
+ */
+#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE0_BASE + 0x6b0)
+/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
+#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_S  0
+
+/** EFUSE_APB2OTP_BLK9_W3_REG register
+ *  eFuse apb2otp block9 data register3.
+ */
+#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE0_BASE + 0x6b4)
+/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
+#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_S  0
+
+/** EFUSE_APB2OTP_BLK9_W4_REG register
+ *  eFuse apb2otp block9 data register4.
+ */
+#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE0_BASE + 0x6b8)
+/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
+#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_S  0
+
+/** EFUSE_APB2OTP_BLK9_W5_REG register
+ *  eFuse apb2otp block9 data register5.
+ */
+#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE0_BASE + 0x6bc)
+/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
+#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_S  0
+
+/** EFUSE_APB2OTP_BLK9_W6_REG register
+ *  eFuse apb2otp block9 data register6.
+ */
+#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE0_BASE + 0x6c0)
+/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
+#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_S  0
+
+/** EFUSE_APB2OTP_BLK9_W7_REG register
+ *  eFuse apb2otp block9 data register7.
+ */
+#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE0_BASE + 0x6c4)
+/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
+#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_S  0
+
+/** EFUSE_APB2OTP_BLK9_W8_REG register
+ *  eFuse apb2otp block9 data register8.
+ */
+#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE0_BASE + 0x6c8)
+/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
+#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_S  0
+
+/** EFUSE_APB2OTP_BLK9_W9_REG register
+ *  eFuse apb2otp block9 data register9.
+ */
+#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE0_BASE + 0x6cc)
+/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
+#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_S  0
+
+/** EFUSE_APB2OTP_BLK9_W10_REG register
+ *  eFuse apb2otp block9 data register10.
+ */
+#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE0_BASE + 0x6d0)
+/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
+#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_S  0
+
+/** EFUSE_APB2OTP_BLK9_W11_REG register
+ *  eFuse apb2otp block9 data register11.
+ */
+#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE0_BASE + 0x6d4)
+/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
+#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_S  0
+
+/** EFUSE_APB2OTP_BLK10_W1_REG register
+ *  eFuse apb2otp block10 data register1.
+ */
+#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE0_BASE + 0x6d8)
+/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
+#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_S  0
+
+/** EFUSE_APB2OTP_BLK10_W2_REG register
+ *  eFuse apb2otp block10 data register2.
+ */
+#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE0_BASE + 0x6dc)
+/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
+#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_S  0
+
+/** EFUSE_APB2OTP_BLK10_W3_REG register
+ *  eFuse apb2otp block10 data register3.
+ */
+#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE0_BASE + 0x6e0)
+/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
+#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_S  0
+
+/** EFUSE_APB2OTP_BLK10_W4_REG register
+ *  eFuse apb2otp block10 data register4.
+ */
+#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE0_BASE + 0x6e4)
+/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
+#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_S  0
+
+/** EFUSE_APB2OTP_BLK10_W5_REG register
+ *  eFuse apb2otp block10 data register5.
+ */
+#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE0_BASE + 0x6e8)
+/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
+#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_S  0
+
+/** EFUSE_APB2OTP_BLK10_W6_REG register
+ *  eFuse apb2otp block10 data register6.
+ */
+#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE0_BASE + 0x6ec)
+/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
+#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_S  0
+
+/** EFUSE_APB2OTP_BLK10_W7_REG register
+ *  eFuse apb2otp block10 data register7.
+ */
+#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE0_BASE + 0x6f0)
+/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
+#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_S  0
+
+/** EFUSE_APB2OTP_BLK10_W8_REG register
+ *  eFuse apb2otp block10 data register8.
+ */
+#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE0_BASE + 0x6f4)
+/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
+#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_S  0
+
+/** EFUSE_APB2OTP_BLK10_W9_REG register
+ *  eFuse apb2otp block10 data register9.
+ */
+#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE0_BASE + 0x6f8)
+/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
+#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_S  0
+
+/** EFUSE_APB2OTP_BLK10_W10_REG register
+ *  eFuse apb2otp block10 data register10.
+ */
+#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE0_BASE + 0x6fc)
+/** EFUSE_APB2OTP_BLOCK10_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W10_M  (EFUSE_APB2OTP_BLOCK10_W10_V << EFUSE_APB2OTP_BLOCK10_W10_S)
+#define EFUSE_APB2OTP_BLOCK10_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W10_S  0
+
+/** EFUSE_APB2OTP_BLK10_W11_REG register
+ *  eFuse apb2otp block10 data register11.
+ */
+#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE0_BASE + 0x700)
+/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
+#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_S  0
+
+/** EFUSE_APB2OTP_EN_REG register
+ *  eFuse apb2otp enable configuration register.
+ */
+#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE0_BASE + 0x708)
+/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
+ *  Apb2otp mode enable signal.
+ */
+#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
+#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
+#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
+#define EFUSE_APB2OTP_APB2OTP_EN_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/efuse_struct.h b/components/soc/esp32c61/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..291d8b45651
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/efuse_struct.h
@@ -0,0 +1,4491 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: buffer0 registers */
+/** Type of pgm_data0 register
+ *  Represents pgm_data0
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Represents pgm_data1
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Represents pgm_data2
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Represents pgm_data3
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Represents pgm_data4
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Represents pgm_data5
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Represents pgm_data6
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Represents pgm_data7
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+
+/** Group: buffer1 registers */
+/** Type of pgm_check_value0 register
+ *  Represents pgm_check_value0
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Represents pgm_check_value1
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Represents pgm_check_value2
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: block0 registers */
+/** Type of rd_wr_dis0 register
+ *  Represents rd_wr_dis
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled or
+         *  enabled.\\ 1: Disabled\\ 0: Enabled\\
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis0_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t rd_dis:7;
+        /** dis_icache : RO; bitpos: [7]; default: 0;
+         *  Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t dis_icache:1;
+        /** dis_usb_jtag : RO; bitpos: [8]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
+         *  disabled\\ 0: enabled\\
+         */
+        uint32_t dis_usb_jtag:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [9]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
+         *  enabled\\
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** dis_force_download : RO; bitpos: [10]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [11]; default: 0;
+         *  Represents whether SPI0 controller during boot_mode_download is disabled or
+         *  enabled.\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** jtag_sel_enable : RO; bitpos: [12]; default: 0;
+         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         *  is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
+         */
+        uint32_t jtag_sel_enable:1;
+        /** dis_pad_jtag : RO; bitpos: [13]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
+         *  0: enabled\\
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [14]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode).\\ 1: disabled\\ 0: enabled\\
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_drefh : RO; bitpos: [16:15]; default: 0;
+         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
+         */
+        uint32_t usb_drefh:2;
+        /** usb_drefl : RO; bitpos: [18:17]; default: 0;
+         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
+         */
+        uint32_t usb_drefl:2;
+        /** usb_exchg_pins : RO; bitpos: [19]; default: 0;
+         *  Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not
+         *  exchanged\\
+         */
+        uint32_t usb_exchg_pins:1;
+        /** vdd_spi_as_gpio : RO; bitpos: [20]; default: 0;
+         *  Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not
+         *  functioned\\
+         */
+        uint32_t vdd_spi_as_gpio:1;
+        /** wdt_delay_sel : RO; bitpos: [22:21]; default: 0;
+         *  Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original
+         *  threshold configuration value of STG0 *2 \\1: Original threshold configuration
+         *  value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3:
+         *  Original threshold configuration value of STG0 *16 \\
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [25:23]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
+         *  1: enabled\\ Even number of 1: disabled\\
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [26]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
+         *  enabled\\ 0: disabled\\
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [27]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
+         *  enabled\\ 0: disabled\\
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [28]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
+         *  enabled\\ 0: disabled\\
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** rd_reserve_0_61 : RW; bitpos: [31:29]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_61:3;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** key_purpose_0 : RO; bitpos: [3:0]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [7:4]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+        /** key_purpose_2 : RO; bitpos: [11:8]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [15:12]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [19:16]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [23:20]; default: 0;
+         *  Represents the purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [25:24]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** secure_boot_en : RO; bitpos: [26]; default: 0;
+         *  Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [27]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
+         *  enabled.\\ 0: disabled\\
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is programmed value. Otherwise, the waiting time is
+         *  2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0:
+         *  Enable\\
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1.
+         *  Disable\\ 0: Enable\\
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [3]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
+         *  1: Disable\\ 0: Enable\\
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [4]; default: 0;
+         *  Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0:
+         *  Disable\\
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [6:5]; default: 0;
+         *  Represents the types of UART printing.
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [7]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [23:8]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [24]; default: 0;
+         *  Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is
+         *  enable.
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [25]; default: 0;
+         *  Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
+         *  enabled\\ 0:disabled\\
+         */
+        uint32_t hys_en_pad:1;
+        /** xts_dpa_clk_enable : RO; bitpos: [26]; default: 0;
+         *  Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0:
+         *  Disable\\
+         */
+        uint32_t xts_dpa_clk_enable:1;
+        /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0;
+         *  Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1:
+         *  Low\\ 0: Decided by register configuration\\
+         */
+        uint32_t xts_dpa_pseudo_level:2;
+        /** dis_wifi6 : RO; bitpos: [29]; default: 0;
+         *  Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is
+         *  disable\\ 0: WiFi 6 is enabled.\\
+         */
+        uint32_t dis_wifi6:1;
+        /** ecdsa_disable_p192 : RO; bitpos: [30]; default: 0;
+         *  Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable.
+         */
+        uint32_t ecdsa_disable_p192:1;
+        /** ecc_force_const_time : RO; bitpos: [31]; default: 0;
+         *  Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
+         *  \\ 0: Disable.
+         */
+        uint32_t ecc_force_const_time:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** rd_repeat_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rd_repeat_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** rd_repeat_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rd_repeat_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+
+/** Group: block1 registers */
+/** Type of rd_mac_sys0 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents MAC address. Low 32-bit.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys0_reg_t;
+
+/** Type of rd_mac_sys1 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Represents MAC address. High 16-bit.
+         */
+        uint32_t mac_1:16;
+        /** rd_reserve_1_48 : RW; bitpos: [31:16]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_1_48:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys1_reg_t;
+
+/** Type of rd_mac_sys2 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** wafer_version_minor : R; bitpos: [3:0]; default: 0;
+         *  Minor chip version
+         */
+        uint32_t wafer_version_minor:4;
+        /** wafer_version_major : R; bitpos: [5:4]; default: 0;
+         *  Major chip version
+         */
+        uint32_t wafer_version_major:2;
+        /** disable_wafer_version_major : R; bitpos: [6]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** blk_version_minor : R; bitpos: [10:8]; default: 0;
+         *  BLK_VERSION_MINOR of BLOCK2
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [12:11]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+        /** flash_cap : R; bitpos: [15:13]; default: 0;
+         *  Flash capacity
+         */
+        uint32_t flash_cap:3;
+        /** flash_vendor : R; bitpos: [18:16]; default: 0;
+         *  Flash vendor
+         */
+        uint32_t flash_vendor:3;
+        /** psram_cap : R; bitpos: [21:19]; default: 0;
+         *  PSRAM capacity
+         */
+        uint32_t psram_cap:3;
+        /** psram_vendor : R; bitpos: [23:22]; default: 0;
+         *  PSRAM vendor
+         */
+        uint32_t psram_vendor:2;
+        /** temp : R; bitpos: [25:24]; default: 0;
+         *  Temperature
+         */
+        uint32_t temp:2;
+        /** pkg_version : R; bitpos: [28:26]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** reserved_1_93 : R; bitpos: [31:29]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_93:3;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys2_reg_t;
+
+/** Type of rd_mac_sys3 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t mac_reserved_2:18;
+        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
+         *  Represents the first 14-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_0:14;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys3_reg_t;
+
+/** Type of rd_mac_sys4 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the first 14-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_1:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys4_reg_t;
+
+/** Type of rd_mac_sys5 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the second 32-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys5_reg_t;
+
+
+/** Group: block2 registers */
+/** Type of rd_sys_part1_data0 register
+ *  Represents rd_sys_part1_data0
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Represents rd_sys_part1_data1
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Represents rd_sys_part1_data2
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Represents rd_sys_part1_data3
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Represents rd_sys_part1_data4
+ */
+typedef union {
+    struct {
+        /** temperature_sensor : R; bitpos: [8:0]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temperature_sensor:9;
+        /** ocode : R; bitpos: [16:9]; default: 0;
+         *  ADC OCode calibration
+         */
+        uint32_t ocode:8;
+        /** adc1_ave_init_code_atten0 : R; bitpos: [26:17]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_init_code_atten0:10;
+        /** adc1_ave_init_code_atten1 : R; bitpos: [31:27]; default: 0;
+         *  Average initcode of ADC1 atten1
+         */
+        uint32_t adc1_ave_init_code_atten1:5;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Represents rd_sys_part1_data5
+ */
+typedef union {
+    struct {
+        /** adc1_ave_init_code_atten1_1 : R; bitpos: [4:0]; default: 0;
+         *  Average initcode of ADC1 atten1
+         */
+        uint32_t adc1_ave_init_code_atten1_1:5;
+        /** adc1_ave_init_code_atten2 : R; bitpos: [14:5]; default: 0;
+         *  Average initcode of ADC1 atten2
+         */
+        uint32_t adc1_ave_init_code_atten2:10;
+        /** adc1_ave_init_code_atten3 : R; bitpos: [24:15]; default: 0;
+         *  Average initcode of ADC1 atten3
+         */
+        uint32_t adc1_ave_init_code_atten3:10;
+        /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
+         *  HI_DOUT of ADC1 atten0
+         */
+        uint32_t adc1_hi_dout_atten0:7;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Represents rd_sys_part1_data6
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
+         *  HI_DOUT of ADC1 atten0
+         */
+        uint32_t adc1_hi_dout_atten0_1:3;
+        /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
+         *  HI_DOUT of ADC1 atten1
+         */
+        uint32_t adc1_hi_dout_atten1:10;
+        /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
+         *  HI_DOUT of ADC1 atten2
+         */
+        uint32_t adc1_hi_dout_atten2:10;
+        /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
+         *  HI_DOUT of ADC1 atten3
+         */
+        uint32_t adc1_hi_dout_atten3:9;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Represents rd_sys_part1_data7
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
+         *  HI_DOUT of ADC1 atten3
+         */
+        uint32_t adc1_hi_dout_atten3_1:1;
+        /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
+         *  Gap between ADC1 CH0 and average initcode
+         */
+        uint32_t adc1_ch0_atten0_initcode_diff:4;
+        /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
+         *  Gap between ADC1 CH1 and average initcode
+         */
+        uint32_t adc1_ch1_atten0_initcode_diff:4;
+        /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
+         *  Gap between ADC1 CH2 and average initcode
+         */
+        uint32_t adc1_ch2_atten0_initcode_diff:4;
+        /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
+         *  Gap between ADC1 CH3 and average initcode
+         */
+        uint32_t adc1_ch3_atten0_initcode_diff:4;
+        /** reserved_2_241 : R; bitpos: [31:17]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_241:15;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+
+/** Group: block3 registers */
+/** Type of rd_usr_data0 register
+ *  Represents rd_usr_data0
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Represents rd_usr_data1
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Represents rd_usr_data2
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Represents rd_usr_data3
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Represents rd_usr_data4
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Represents rd_usr_data5
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Represents rd_usr_data6
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Represents rd_usr_data7
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+
+/** Group: block4 registers */
+/** Type of rd_key0_data0 register
+ *  Represents rd_key0_data0
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Represents rd_key0_data1
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Represents rd_key0_data2
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Represents rd_key0_data3
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Represents rd_key0_data4
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Represents rd_key0_data5
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Represents rd_key0_data6
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Represents rd_key0_data7
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+
+/** Group: block5 registers */
+/** Type of rd_key1_data0 register
+ *  Represents rd_key1_data0
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Represents rd_key1_data1
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Represents rd_key1_data2
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Represents rd_key1_data3
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Represents rd_key1_data4
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Represents rd_key1_data5
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Represents rd_key1_data6
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Represents rd_key1_data7
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+
+/** Group: block6 registers */
+/** Type of rd_key2_data0 register
+ *  Represents rd_key2_data0
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Represents rd_key2_data1
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Represents rd_key2_data2
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Represents rd_key2_data3
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Represents rd_key2_data4
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Represents rd_key2_data5
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Represents rd_key2_data6
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Represents rd_key2_data7
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+
+/** Group: block7 registers */
+/** Type of rd_key3_data0 register
+ *  Represents rd_key3_data0
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Represents rd_key3_data1
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Represents rd_key3_data2
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Represents rd_key3_data3
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Represents rd_key3_data4
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Represents rd_key3_data5
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Represents rd_key3_data6
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Represents rd_key3_data7
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+
+/** Group: block8 registers */
+/** Type of rd_key4_data0 register
+ *  Represents rd_key4_data0
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Represents rd_key4_data1
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Represents rd_key4_data2
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Represents rd_key4_data3
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Represents rd_key4_data4
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Represents rd_key4_data5
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Represents rd_key4_data6
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Represents rd_key4_data7
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+
+/** Group: block9 registers */
+/** Type of rd_key5_data0 register
+ *  Represents rd_key5_data0
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Represents rd_key5_data1
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Represents rd_key5_data2
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Represents rd_key5_data3
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Represents rd_key5_data4
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Represents rd_key5_data5
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Represents rd_key5_data6
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Represents rd_key5_data7
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+
+/** Group: block10 registers */
+/** Type of rd_sys_part2_data0 register
+ *  Represents rd_sys_part2_data0
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Represents rd_sys_part2_data1
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Represents rd_sys_part2_data2
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Represents rd_sys_part2_data3
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Represents rd_sys_part2_data4
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Represents rd_sys_part2_data5
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Represents rd_sys_part2_data6
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Represents rd_sys_part2_data7
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+
+/** Group: block0 error report registers */
+/** Type of rd_repeat_data_err0 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Represents the programming error of EFUSE_RD_DIS
+         */
+        uint32_t rd_dis_err:7;
+        /** dis_icache_err : RO; bitpos: [7]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_ICACHE
+         */
+        uint32_t dis_icache_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [8]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_JTAG
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
+        /** dis_force_download_err : RO; bitpos: [10]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [11]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [12]; default: 0;
+         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** dis_pad_jtag_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_drefh_err : RO; bitpos: [16:15]; default: 0;
+         *  Represents the programming error of EFUSE_USB_DREFH
+         */
+        uint32_t usb_drefh_err:2;
+        /** usb_drefl_err : RO; bitpos: [18:17]; default: 0;
+         *  Represents the programming error of EFUSE_USB_DREFL
+         */
+        uint32_t usb_drefl_err:2;
+        /** usb_exchg_pins_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_USB_EXCHG_PINS
+         */
+        uint32_t usb_exchg_pins_err:1;
+        /** vdd_spi_as_gpio_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_VDD_SPI_AS_GPIO
+         */
+        uint32_t vdd_spi_as_gpio_err:1;
+        /** wdt_delay_sel_err : RO; bitpos: [22:21]; default: 0;
+         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [25:23]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke_0_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_0
+         */
+        uint32_t secure_boot_key_revoke_0_err:1;
+        /** secure_boot_key_revoke_1_err : RO; bitpos: [27]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_1
+         */
+        uint32_t secure_boot_key_revoke_1_err:1;
+        /** secure_boot_key_revoke_2_err : RO; bitpos: [28]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE_2
+         */
+        uint32_t secure_boot_key_revoke_2_err:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err0_reg_t;
+
+/** Type of rd_repeat_data_err1 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** key_purpose_0_err : RO; bitpos: [3:0]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [7:4]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
+         */
+        uint32_t key_purpose_1_err:4;
+        /** key_purpose_2_err : RO; bitpos: [11:8]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [15:12]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [19:16]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [23:20]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_5
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [25:24]; default: 0;
+         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
+         */
+        uint32_t sec_dpa_level_err:2;
+        /** secure_boot_en_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [27]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Represents the programming error of EFUSE_FLASH_TPUW
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err1_reg_t;
+
+/** Type of rd_repeat_data_err2 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [6:5]; default: 0;
+         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [7]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [23:8]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_VERSION
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [24]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_HYS_EN_PAD
+         */
+        uint32_t hys_en_pad_err:1;
+        /** xts_dpa_clk_enable_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+         */
+        uint32_t xts_dpa_clk_enable_err:1;
+        /** xts_dpa_pseudo_level_err : RO; bitpos: [28:27]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+         */
+        uint32_t xts_dpa_pseudo_level_err:2;
+        /** dis_wifi6_err : RO; bitpos: [29]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_WIFI6
+         */
+        uint32_t dis_wifi6_err:1;
+        /** ecdsa_disable_p192_err : RO; bitpos: [30]; default: 0;
+         *  Represents the programming error of EFUSE_ECDSA_DISABLE_P192
+         */
+        uint32_t ecdsa_disable_p192_err:1;
+        /** ecc_force_const_time_err : RO; bitpos: [31]; default: 0;
+         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+         */
+        uint32_t ecc_force_const_time_err:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err2_reg_t;
+
+/** Type of rd_repeat_data_err3 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** rd_repeat_data_err3 : RO; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rd_repeat_data_err3:32;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err3_reg_t;
+
+/** Type of rd_repeat_data_err4 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** rd_repeat_data_err4 : RO; bitpos: [31:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rd_repeat_data_err4:32;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err4_reg_t;
+
+
+/** Group: RS block error report registers */
+/** Type of rd_rs_data_err0 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_mac_sys
+         */
+        uint32_t rd_mac_sys_err_num:3;
+        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number
+         *  of error bytes is over 6.
+         */
+        uint32_t rd_mac_sys_fail:1;
+        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_sys_part1_data
+         */
+        uint32_t rd_sys_part1_data_err_num:3;
+        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed
+         *  and the number of error bytes is over 6.
+         */
+        uint32_t rd_sys_part1_data_fail:1;
+        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_usr_data
+         */
+        uint32_t rd_usr_data_err_num:3;
+        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_usr_data_fail:1;
+        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key0_data
+         */
+        uint32_t rd_key0_data_err_num:3;
+        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key0_data_fail:1;
+        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key1_data
+         */
+        uint32_t rd_key1_data_err_num:3;
+        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key1_data_fail:1;
+        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key2_data
+         */
+        uint32_t rd_key2_data_err_num:3;
+        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key2_data_fail:1;
+        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key3_data
+         */
+        uint32_t rd_key3_data_err_num:3;
+        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key3_data_fail:1;
+        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key4_data
+         */
+        uint32_t rd_key4_data_err_num:3;
+        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key4_data_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err0_reg_t;
+
+/** Type of rd_rs_data_err1 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_key5_data_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_key5_data
+         */
+        uint32_t rd_key5_data_err_num:3;
+        /** rd_key5_data_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_key5_data is reliable\\ 1: Means that programming rd_key5_data failed and the
+         *  number of error bytes is over 6.
+         */
+        uint32_t rd_key5_data_fail:1;
+        /** rd_sys_part2_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.\\The value of this signal means the
+         *  number of error bytes in rd_sys_part2_data
+         */
+        uint32_t rd_sys_part2_data_err_num:3;
+        /** rd_sys_part2_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.\\0: Means no failure and that the data of
+         *  rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed
+         *  and the number of error bytes is over 6.
+         */
+        uint32_t rd_sys_part2_data_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err1_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37753088;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE Clock Registers */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+
+/** Group: EFUSE Configure Registers */
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
+         *  Configures which block to use for ECDSA key output.
+         */
+        uint32_t cfg_ecdsa_blk:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+
+/** Group: EFUSE Status Registers */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
+         *  Indicates which block is used for ECDSA key output.
+         */
+        uint32_t cur_ecdsa_blk:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: EFUSE Command Registers */
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+/** Group: EFUSE Configure Registers */
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 200;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
+/** Type of apb2otp_wr_dis register
+ *  eFuse apb2otp block0 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t apb2otp_block0_wr_dis:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_wr_dis_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
+/** Type of apb2otp_blk0_backup1_w1 register
+ *  eFuse apb2otp block0 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t apb2otp_block0_backup1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
+/** Type of apb2otp_blk0_backup1_w2 register
+ *  eFuse apb2otp block0 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t apb2otp_block0_backup1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
+/** Type of apb2otp_blk0_backup1_w3 register
+ *  eFuse apb2otp block0 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t apb2otp_block0_backup1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
+/** Type of apb2otp_blk0_backup1_w4 register
+ *  eFuse apb2otp block0 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t apb2otp_block0_backup1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
+/** Type of apb2otp_blk0_backup1_w5 register
+ *  eFuse apb2otp block0 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t apb2otp_block0_backup1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
+/** Type of apb2otp_blk0_backup2_w1 register
+ *  eFuse apb2otp block0 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t apb2otp_block0_backup2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
+/** Type of apb2otp_blk0_backup2_w2 register
+ *  eFuse apb2otp block0 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t apb2otp_block0_backup2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
+/** Type of apb2otp_blk0_backup2_w3 register
+ *  eFuse apb2otp block0 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t apb2otp_block0_backup2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
+/** Type of apb2otp_blk0_backup2_w4 register
+ *  eFuse apb2otp block0 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t apb2otp_block0_backup2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
+/** Type of apb2otp_blk0_backup2_w5 register
+ *  eFuse apb2otp block0 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t apb2otp_block0_backup2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
+/** Type of apb2otp_blk0_backup3_w1 register
+ *  eFuse apb2otp block0 data register12.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t apb2otp_block0_backup3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
+/** Type of apb2otp_blk0_backup3_w2 register
+ *  eFuse apb2otp block0 data register13.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t apb2otp_block0_backup3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
+/** Type of apb2otp_blk0_backup3_w3 register
+ *  eFuse apb2otp block0 data register14.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t apb2otp_block0_backup3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
+/** Type of apb2otp_blk0_backup3_w4 register
+ *  eFuse apb2otp block0 data register15.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t apb2otp_block0_backup3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
+/** Type of apb2otp_blk0_backup3_w5 register
+ *  eFuse apb2otp block0 data register16.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t apb2otp_block0_backup3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
+/** Type of apb2otp_blk0_backup4_w1 register
+ *  eFuse apb2otp block0 data register17.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t apb2otp_block0_backup4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
+/** Type of apb2otp_blk0_backup4_w2 register
+ *  eFuse apb2otp block0 data register18.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t apb2otp_block0_backup4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
+/** Type of apb2otp_blk0_backup4_w3 register
+ *  eFuse apb2otp block0 data register19.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t apb2otp_block0_backup4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
+/** Type of apb2otp_blk0_backup4_w4 register
+ *  eFuse apb2otp block0 data register20.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t apb2otp_block0_backup4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
+/** Type of apb2otp_blk0_backup4_w5 register
+ *  eFuse apb2otp block0 data register21.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t apb2otp_block0_backup4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word1 Data */
+/** Type of apb2otp_blk1_w1 register
+ *  eFuse apb2otp block1 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t apb2otp_block1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word2 Data */
+/** Type of apb2otp_blk1_w2 register
+ *  eFuse apb2otp block1 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t apb2otp_block1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word3 Data */
+/** Type of apb2otp_blk1_w3 register
+ *  eFuse apb2otp block1 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t apb2otp_block1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word4 Data */
+/** Type of apb2otp_blk1_w4 register
+ *  eFuse apb2otp block1 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t apb2otp_block1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word5 Data */
+/** Type of apb2otp_blk1_w5 register
+ *  eFuse apb2otp block1 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t apb2otp_block1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word6 Data */
+/** Type of apb2otp_blk1_w6 register
+ *  eFuse apb2otp block1 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t apb2otp_block1_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word7 Data */
+/** Type of apb2otp_blk1_w7 register
+ *  eFuse apb2otp block1 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t apb2otp_block1_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word8 Data */
+/** Type of apb2otp_blk1_w8 register
+ *  eFuse apb2otp block1 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t apb2otp_block1_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word9 Data */
+/** Type of apb2otp_blk1_w9 register
+ *  eFuse apb2otp block1 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t apb2otp_block1_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word1 Data */
+/** Type of apb2otp_blk2_w1 register
+ *  eFuse apb2otp block2 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t apb2otp_block2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word2 Data */
+/** Type of apb2otp_blk2_w2 register
+ *  eFuse apb2otp block2 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t apb2otp_block2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word3 Data */
+/** Type of apb2otp_blk2_w3 register
+ *  eFuse apb2otp block2 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t apb2otp_block2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word4 Data */
+/** Type of apb2otp_blk2_w4 register
+ *  eFuse apb2otp block2 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t apb2otp_block2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word5 Data */
+/** Type of apb2otp_blk2_w5 register
+ *  eFuse apb2otp block2 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t apb2otp_block2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word6 Data */
+/** Type of apb2otp_blk2_w6 register
+ *  eFuse apb2otp block2 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t apb2otp_block2_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word7 Data */
+/** Type of apb2otp_blk2_w7 register
+ *  eFuse apb2otp block2 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t apb2otp_block2_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word8 Data */
+/** Type of apb2otp_blk2_w8 register
+ *  eFuse apb2otp block2 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t apb2otp_block2_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word9 Data */
+/** Type of apb2otp_blk2_w9 register
+ *  eFuse apb2otp block2 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t apb2otp_block2_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word10 Data */
+/** Type of apb2otp_blk2_w10 register
+ *  eFuse apb2otp block2 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t apb2otp_block2_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk2_w11 register
+ *  eFuse apb2otp block2 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t apb2otp_block2_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word1 Data */
+/** Type of apb2otp_blk3_w1 register
+ *  eFuse apb2otp block3 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t apb2otp_block3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word2 Data */
+/** Type of apb2otp_blk3_w2 register
+ *  eFuse apb2otp block3 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t apb2otp_block3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word3 Data */
+/** Type of apb2otp_blk3_w3 register
+ *  eFuse apb2otp block3 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t apb2otp_block3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word4 Data */
+/** Type of apb2otp_blk3_w4 register
+ *  eFuse apb2otp block3 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t apb2otp_block3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word5 Data */
+/** Type of apb2otp_blk3_w5 register
+ *  eFuse apb2otp block3 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t apb2otp_block3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word6 Data */
+/** Type of apb2otp_blk3_w6 register
+ *  eFuse apb2otp block3 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t apb2otp_block3_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word7 Data */
+/** Type of apb2otp_blk3_w7 register
+ *  eFuse apb2otp block3 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t apb2otp_block3_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word8 Data */
+/** Type of apb2otp_blk3_w8 register
+ *  eFuse apb2otp block3 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t apb2otp_block3_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word9 Data */
+/** Type of apb2otp_blk3_w9 register
+ *  eFuse apb2otp block3 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t apb2otp_block3_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word10 Data */
+/** Type of apb2otp_blk3_w10 register
+ *  eFuse apb2otp block3 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t apb2otp_block3_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word11 Data */
+/** Type of apb2otp_blk3_w11 register
+ *  eFuse apb2otp block3 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t apb2otp_block3_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word1 Data */
+/** Type of apb2otp_blk4_w1 register
+ *  eFuse apb2otp BLOCK7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t apb2otp_block4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word2 Data */
+/** Type of apb2otp_blk4_w2 register
+ *  eFuse apb2otp block4 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t apb2otp_block4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word3 Data */
+/** Type of apb2otp_blk4_w3 register
+ *  eFuse apb2otp block4 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t apb2otp_block4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word4 Data */
+/** Type of apb2otp_blk4_w4 register
+ *  eFuse apb2otp block4 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t apb2otp_block4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word5 Data */
+/** Type of apb2otp_blk4_w5 register
+ *  eFuse apb2otp block4 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t apb2otp_block4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word6 Data */
+/** Type of apb2otp_blk4_w6 register
+ *  eFuse apb2otp block4 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t apb2otp_block4_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word7 Data */
+/** Type of apb2otp_blk4_w7 register
+ *  eFuse apb2otp block4 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t apb2otp_block4_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word8 Data */
+/** Type of apb2otp_blk4_w8 register
+ *  eFuse apb2otp block4 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t apb2otp_block4_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word9 Data */
+/** Type of apb2otp_blk4_w9 register
+ *  eFuse apb2otp block4 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t apb2otp_block4_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word10 Data */
+/** Type of apb2otp_blk4_w10 register
+ *  eFuse apb2otp block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t apb2otp_block4_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP BLOCK7 Word11 Data */
+/** Type of apb2otp_blk4_w11 register
+ *  eFuse apb2otp block4 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t apb2otp_block4_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word1 Data */
+/** Type of apb2otp_blk5_w1 register
+ *  eFuse apb2otp block5 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t apb2otp_block5_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word2 Data */
+/** Type of apb2otp_blk5_w2 register
+ *  eFuse apb2otp block5 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t apb2otp_block5_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word3 Data */
+/** Type of apb2otp_blk5_w3 register
+ *  eFuse apb2otp block5 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t apb2otp_block5_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word4 Data */
+/** Type of apb2otp_blk5_w4 register
+ *  eFuse apb2otp block5 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t apb2otp_block5_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word5 Data */
+/** Type of apb2otp_blk5_w5 register
+ *  eFuse apb2otp block5 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t apb2otp_block5_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word6 Data */
+/** Type of apb2otp_blk5_w6 register
+ *  eFuse apb2otp block5 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t apb2otp_block5_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word7 Data */
+/** Type of apb2otp_blk5_w7 register
+ *  eFuse apb2otp block5 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t apb2otp_block5_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word8 Data */
+/** Type of apb2otp_blk5_w8 register
+ *  eFuse apb2otp block5 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t apb2otp_block5_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word9 Data */
+/** Type of apb2otp_blk5_w9 register
+ *  eFuse apb2otp block5 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t apb2otp_block5_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word10 Data */
+/** Type of apb2otp_blk5_w10 register
+ *  eFuse apb2otp block5 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t apb2otp_block5_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word11 Data */
+/** Type of apb2otp_blk5_w11 register
+ *  eFuse apb2otp block5 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t apb2otp_block5_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word1 Data */
+/** Type of apb2otp_blk6_w1 register
+ *  eFuse apb2otp block6 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t apb2otp_block6_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word2 Data */
+/** Type of apb2otp_blk6_w2 register
+ *  eFuse apb2otp block6 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t apb2otp_block6_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word3 Data */
+/** Type of apb2otp_blk6_w3 register
+ *  eFuse apb2otp block6 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t apb2otp_block6_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word4 Data */
+/** Type of apb2otp_blk6_w4 register
+ *  eFuse apb2otp block6 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t apb2otp_block6_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word5 Data */
+/** Type of apb2otp_blk6_w5 register
+ *  eFuse apb2otp block6 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t apb2otp_block6_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word6 Data */
+/** Type of apb2otp_blk6_w6 register
+ *  eFuse apb2otp block6 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t apb2otp_block6_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word7 Data */
+/** Type of apb2otp_blk6_w7 register
+ *  eFuse apb2otp block6 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t apb2otp_block6_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word8 Data */
+/** Type of apb2otp_blk6_w8 register
+ *  eFuse apb2otp block6 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t apb2otp_block6_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word9 Data */
+/** Type of apb2otp_blk6_w9 register
+ *  eFuse apb2otp block6 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t apb2otp_block6_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word10 Data */
+/** Type of apb2otp_blk6_w10 register
+ *  eFuse apb2otp block6 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t apb2otp_block6_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word11 Data */
+/** Type of apb2otp_blk6_w11 register
+ *  eFuse apb2otp block6 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t apb2otp_block6_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word1 Data */
+/** Type of apb2otp_blk7_w1 register
+ *  eFuse apb2otp block7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t apb2otp_block7_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word2 Data */
+/** Type of apb2otp_blk7_w2 register
+ *  eFuse apb2otp block7 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t apb2otp_block7_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word3 Data */
+/** Type of apb2otp_blk7_w3 register
+ *  eFuse apb2otp block7 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t apb2otp_block7_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word4 Data */
+/** Type of apb2otp_blk7_w4 register
+ *  eFuse apb2otp block7 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t apb2otp_block7_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word5 Data */
+/** Type of apb2otp_blk7_w5 register
+ *  eFuse apb2otp block7 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t apb2otp_block7_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word6 Data */
+/** Type of apb2otp_blk7_w6 register
+ *  eFuse apb2otp block7 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t apb2otp_block7_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word7 Data */
+/** Type of apb2otp_blk7_w7 register
+ *  eFuse apb2otp block7 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t apb2otp_block7_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word8 Data */
+/** Type of apb2otp_blk7_w8 register
+ *  eFuse apb2otp block7 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t apb2otp_block7_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word9 Data */
+/** Type of apb2otp_blk7_w9 register
+ *  eFuse apb2otp block7 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t apb2otp_block7_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word10 Data */
+/** Type of apb2otp_blk7_w10 register
+ *  eFuse apb2otp block7 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t apb2otp_block7_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word11 Data */
+/** Type of apb2otp_blk7_w11 register
+ *  eFuse apb2otp block7 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t apb2otp_block7_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word1 Data */
+/** Type of apb2otp_blk8_w1 register
+ *  eFuse apb2otp block8 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t apb2otp_block8_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word2 Data */
+/** Type of apb2otp_blk8_w2 register
+ *  eFuse apb2otp block8 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t apb2otp_block8_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word3 Data */
+/** Type of apb2otp_blk8_w3 register
+ *  eFuse apb2otp block8 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t apb2otp_block8_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word4 Data */
+/** Type of apb2otp_blk8_w4 register
+ *  eFuse apb2otp block8 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t apb2otp_block8_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word5 Data */
+/** Type of apb2otp_blk8_w5 register
+ *  eFuse apb2otp block8 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t apb2otp_block8_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word6 Data */
+/** Type of apb2otp_blk8_w6 register
+ *  eFuse apb2otp block8 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t apb2otp_block8_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word7 Data */
+/** Type of apb2otp_blk8_w7 register
+ *  eFuse apb2otp block8 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t apb2otp_block8_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word8 Data */
+/** Type of apb2otp_blk8_w8 register
+ *  eFuse apb2otp block8 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t apb2otp_block8_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word9 Data */
+/** Type of apb2otp_blk8_w9 register
+ *  eFuse apb2otp block8 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t apb2otp_block8_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word10 Data */
+/** Type of apb2otp_blk8_w10 register
+ *  eFuse apb2otp block8 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t apb2otp_block8_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word11 Data */
+/** Type of apb2otp_blk8_w11 register
+ *  eFuse apb2otp block8 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t apb2otp_block8_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word1 Data */
+/** Type of apb2otp_blk9_w1 register
+ *  eFuse apb2otp block9 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t apb2otp_block9_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word2 Data */
+/** Type of apb2otp_blk9_w2 register
+ *  eFuse apb2otp block9 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t apb2otp_block9_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word3 Data */
+/** Type of apb2otp_blk9_w3 register
+ *  eFuse apb2otp block9 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t apb2otp_block9_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word4 Data */
+/** Type of apb2otp_blk9_w4 register
+ *  eFuse apb2otp block9 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t apb2otp_block9_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word5 Data */
+/** Type of apb2otp_blk9_w5 register
+ *  eFuse apb2otp block9 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t apb2otp_block9_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word6 Data */
+/** Type of apb2otp_blk9_w6 register
+ *  eFuse apb2otp block9 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t apb2otp_block9_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word7 Data */
+/** Type of apb2otp_blk9_w7 register
+ *  eFuse apb2otp block9 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t apb2otp_block9_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word8 Data */
+/** Type of apb2otp_blk9_w8 register
+ *  eFuse apb2otp block9 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t apb2otp_block9_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word9 Data */
+/** Type of apb2otp_blk9_w9 register
+ *  eFuse apb2otp block9 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t apb2otp_block9_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word10 Data */
+/** Type of apb2otp_blk9_w10 register
+ *  eFuse apb2otp block9 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t apb2otp_block9_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word11 Data */
+/** Type of apb2otp_blk9_w11 register
+ *  eFuse apb2otp block9 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t apb2otp_block9_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word1 Data */
+/** Type of apb2otp_blk10_w1 register
+ *  eFuse apb2otp block10 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t apb2otp_block10_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word2 Data */
+/** Type of apb2otp_blk10_w2 register
+ *  eFuse apb2otp block10 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t apb2otp_block10_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word3 Data */
+/** Type of apb2otp_blk10_w3 register
+ *  eFuse apb2otp block10 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t apb2otp_block10_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word4 Data */
+/** Type of apb2otp_blk10_w4 register
+ *  eFuse apb2otp block10 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t apb2otp_block10_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word5 Data */
+/** Type of apb2otp_blk10_w5 register
+ *  eFuse apb2otp block10 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t apb2otp_block10_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word6 Data */
+/** Type of apb2otp_blk10_w6 register
+ *  eFuse apb2otp block10 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t apb2otp_block10_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word7 Data */
+/** Type of apb2otp_blk10_w7 register
+ *  eFuse apb2otp block10 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t apb2otp_block10_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word8 Data */
+/** Type of apb2otp_blk10_w8 register
+ *  eFuse apb2otp block10 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t apb2otp_block10_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word9 Data */
+/** Type of apb2otp_blk10_w9 register
+ *  eFuse apb2otp block10 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t apb2otp_block10_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word10 Data */
+/** Type of apb2otp_blk10_w10 register
+ *  eFuse apb2otp block10 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t apb2otp_block10_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk10_w11 register
+ *  eFuse apb2otp block10 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t apb2otp_block10_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Function Enable Signal */
+/** Type of apb2otp_en register
+ *  eFuse apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Apb2otp mode enable signal.
+         */
+        uint32_t apb2otp_apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_apb2otp_en_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis0_reg_t rd_wr_dis0;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
+    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
+    volatile efuse_rd_mac_sys2_reg_t rd_mac_sys2;
+    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
+    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
+    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
+    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
+    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
+    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
+    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
+    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
+    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_19c[11];
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    uint32_t reserved_1fc[193];
+    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
+    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
+    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
+    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
+    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
+    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
+    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
+    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
+    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
+    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
+    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
+    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
+    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
+    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
+    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
+    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
+    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
+    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
+    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
+    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
+    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
+    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
+    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
+    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
+    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
+    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
+    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
+    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
+    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
+    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
+    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
+    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
+    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
+    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
+    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
+    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
+    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
+    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
+    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
+    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
+    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
+    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
+    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
+    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
+    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
+    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
+    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
+    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
+    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
+    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
+    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
+    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
+    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
+    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
+    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
+    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
+    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
+    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
+    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
+    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
+    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
+    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
+    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
+    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
+    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
+    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
+    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
+    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
+    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
+    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
+    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
+    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
+    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
+    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
+    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
+    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
+    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
+    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
+    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
+    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
+    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
+    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
+    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
+    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
+    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
+    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
+    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
+    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
+    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
+    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
+    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
+    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
+    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
+    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
+    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
+    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
+    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
+    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
+    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
+    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
+    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
+    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
+    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
+    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
+    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
+    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
+    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
+    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
+    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
+    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
+    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
+    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
+    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
+    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
+    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
+    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
+    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
+    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
+    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
+    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
+    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
+    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
+    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
+    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
+    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
+    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
+    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
+    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
+    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
+    uint32_t reserved_704;
+    volatile efuse_apb2otp_en_reg_t apb2otp_en;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE0;
+extern efuse_dev_t EFUSE1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x70c, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/gpio_ext_reg.h b/components/soc/esp32c61/register/soc/gpio_ext_reg.h
similarity index 99%
rename from components/soc/esp32c61/include/soc/gpio_ext_reg.h
rename to components/soc/esp32c61/register/soc/gpio_ext_reg.h
index 26effdee28f..2385576c333 100644
--- a/components/soc/esp32c61/include/soc/gpio_ext_reg.h
+++ b/components/soc/esp32c61/register/soc/gpio_ext_reg.h
@@ -37,7 +37,7 @@ extern "C" {
 #define GPIO_EXT_XPD_COMP_0_V  0x00000001U
 #define GPIO_EXT_XPD_COMP_0_S  0
 /** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0;
- *  Configures the reference voltage for analog PAD voltage comparater.. \\
+ *  Configures the reference voltage for analog PAD voltage comparator.. \\
  *  0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
  *  used as a regular GPIO\\
  *  1: Reference voltage is the voltage on the GPIO8 PAD\\
diff --git a/components/soc/esp32c61/include/soc/gpio_ext_struct.h b/components/soc/esp32c61/register/soc/gpio_ext_struct.h
similarity index 97%
rename from components/soc/esp32c61/include/soc/gpio_ext_struct.h
rename to components/soc/esp32c61/register/soc/gpio_ext_struct.h
index f02a5fec8a1..1f7f58950e2 100644
--- a/components/soc/esp32c61/include/soc/gpio_ext_struct.h
+++ b/components/soc/esp32c61/register/soc/gpio_ext_struct.h
@@ -39,7 +39,7 @@ typedef union {
          */
         uint32_t xpd_comp_0:1;
         /** mode_comp_0 : R/W; bitpos: [1]; default: 0;
-         *  Configures the reference voltage for analog PAD voltage comparater.. \\
+         *  Configures the reference voltage for analog PAD voltage comparator.. \\
          *  0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
          *  used as a regular GPIO\\
          *  1: Reference voltage is the voltage on the GPIO8 PAD\\
@@ -128,6 +128,15 @@ typedef union {
     uint32_t val;
 } gpio_ext_etm_event_chn_cfg_reg_t;
 
+/** Type of etm_task_pn_cfg register
+ *  GPIO selection register for ETM.
+ *  This register is an abstraction of the following registers:
+ *  gpio_ext_etm_task_p0_cfg_reg_t ~ gpio_ext_etm_task_p4_cfg_reg_t
+ */
+typedef union {
+    uint32_t val;
+} gpio_ext_etm_task_pn_cfg_reg_t;
+
 /** Type of etm_task_p0_cfg register
  *  GPIO selection register 0 for ETM
  */
@@ -659,6 +668,11 @@ typedef union {
     uint32_t val;
 } gpio_ext_version_reg_t;
 
+typedef struct gpio_etm_dev_t {
+    volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
+    uint32_t reserved_138[8];
+    volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[5];
+} gpio_etm_dev_t;
 
 typedef struct {
     volatile gpio_ext_clock_gate_reg_t clock_gate;
@@ -666,13 +680,7 @@ typedef struct {
     volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0;
     volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0;
     uint32_t reserved_060[46];
-    volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
-    uint32_t reserved_138[8];
-    volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
-    volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
-    volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
-    volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
-    volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
+    volatile gpio_etm_dev_t etm;
     uint32_t reserved_16c[25];
     volatile gpio_ext_int_raw_reg_t int_raw;
     volatile gpio_ext_int_st_reg_t int_st;
@@ -683,6 +691,8 @@ typedef struct {
     volatile gpio_ext_version_reg_t version;
 } gpio_ext_dev_t;
 
+extern gpio_etm_dev_t GPIO_ETM;
+extern gpio_ext_dev_t GPIO_EXT;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
diff --git a/components/soc/esp32c61/register/soc/gpio_reg.h b/components/soc/esp32c61/register/soc/gpio_reg.h
new file mode 100644
index 00000000000..f9eaeac424c
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/gpio_reg.h
@@ -0,0 +1,5188 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO_STRAP_REG register
+ *  Strapping pin register
+ */
+#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0)
+/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
+ *  Represents the values of GPIO strapping pins.
+ *
+ *  - bit0 ~ bit1: invalid
+ *  - bit2: GPIO8
+ *  - bit3: GPIO9
+ *  - bit4: GPIO7
+ *  - bit5 ~ bit15: invalid
+ */
+#define GPIO_STRAPPING    0x0000FFFFU
+#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
+#define GPIO_STRAPPING_V  0x0000FFFFU
+#define GPIO_STRAPPING_S  0
+
+/** GPIO_OUT_REG register
+ *  GPIO output register
+ */
+#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
+/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [28:0]; default: 0;
+ *  Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\
+ *  0: Low level\\
+ *  1: High level\\
+ *  The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24
+ *  respectively. Bit25 ~ bit31 are invalid.\\
+ */
+#define GPIO_OUT_DATA_ORIG    0x1FFFFFFFU
+#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
+#define GPIO_OUT_DATA_ORIG_V  0x1FFFFFFFU
+#define GPIO_OUT_DATA_ORIG_S  0
+
+/** GPIO_OUT_W1TS_REG register
+ *  GPIO output set register
+ */
+#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
+/** GPIO_OUT_W1TS : WT; bitpos: [28:0]; default: 0;
+ *  Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~
+ *  GPIO24.\\
+ *  0: Not set\\
+ *  1: The corresponding bit in GPIO_OUT_REG will be set to 1\\
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
+ *  Recommended operation: use this register to set GPIO_OUT_REG. \\
+ */
+#define GPIO_OUT_W1TS    0x1FFFFFFFU
+#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
+#define GPIO_OUT_W1TS_V  0x1FFFFFFFU
+#define GPIO_OUT_W1TS_S  0
+
+/** GPIO_OUT_W1TC_REG register
+ *  GPIO output clear register
+ */
+#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
+/** GPIO_OUT_W1TC : WT; bitpos: [28:0]; default: 0;
+ *  Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
+ *  GPIO24 output.\\
+ *  0: Not clear\\
+ *  1: The corresponding bit in GPIO_OUT_REG will be cleared.\\
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
+ *  Recommended operation: use this register to clear GPIO_OUT_REG. \\
+ */
+#define GPIO_OUT_W1TC    0x1FFFFFFFU
+#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
+#define GPIO_OUT_W1TC_V  0x1FFFFFFFU
+#define GPIO_OUT_W1TC_S  0
+
+/** GPIO_ENABLE_REG register
+ *  GPIO output enable register
+ */
+#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x34)
+/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [28:0]; default: 0;
+ *  Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\
+ *  0: Not enable\\
+ *  1: Enable\\
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
+ */
+#define GPIO_ENABLE_DATA    0x1FFFFFFFU
+#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
+#define GPIO_ENABLE_DATA_V  0x1FFFFFFFU
+#define GPIO_ENABLE_DATA_S  0
+
+/** GPIO_ENABLE_W1TS_REG register
+ *  GPIO output enable set register
+ */
+#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x38)
+/** GPIO_ENABLE_W1TS : WT; bitpos: [28:0]; default: 0;
+ *  Configures whether or not to set the output enable register GPIO_ENABLE_REG of
+ *  GPIO0 ~ GPIO24.\\
+ *  0: Not set\\
+ *  1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
+ *  Recommended operation: use this register to set GPIO_ENABLE_REG.\\
+ */
+#define GPIO_ENABLE_W1TS    0x1FFFFFFFU
+#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
+#define GPIO_ENABLE_W1TS_V  0x1FFFFFFFU
+#define GPIO_ENABLE_W1TS_S  0
+
+/** GPIO_ENABLE_W1TC_REG register
+ *  GPIO output enable clear register
+ */
+#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x3c)
+/** GPIO_ENABLE_W1TC : WT; bitpos: [28:0]; default: 0;
+ *  Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
+ *  GPIO0 ~ GPIO24. \\
+ *  0: Not clear\\
+ *  1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
+ *  Recommended operation: use this register to clear GPIO_ENABLE_REG.\\
+ */
+#define GPIO_ENABLE_W1TC    0x1FFFFFFFU
+#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
+#define GPIO_ENABLE_W1TC_V  0x1FFFFFFFU
+#define GPIO_ENABLE_W1TC_S  0
+
+/** GPIO_IN_REG register
+ *  GPIO input register
+ */
+#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x64)
+/** GPIO_IN_DATA_NEXT : RO; bitpos: [28:0]; default: 0;
+ *  Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input
+ *  value:\\
+ *  0: Low level\\
+ *  1: High level\\
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
+ */
+#define GPIO_IN_DATA_NEXT    0x1FFFFFFFU
+#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
+#define GPIO_IN_DATA_NEXT_V  0x1FFFFFFFU
+#define GPIO_IN_DATA_NEXT_S  0
+
+/** GPIO_STATUS_REG register
+ *  GPIO interrupt status register
+ */
+#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x74)
+/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [28:0]; default: 0;
+ *  The interrupt status of GPIO0 ~ GPIO24, can be configured by the software.
+ *
+ *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
+ *  - Each bit represents the status of its corresponding GPIO:
+ *
+ *  - 0: Represents the GPIO does not generate the interrupt configured by
+ *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
+ *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
+ *  or this bit is configured to 1 by the software.
+ *
+ */
+#define GPIO_STATUS_INTERRUPT    0x1FFFFFFFU
+#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
+#define GPIO_STATUS_INTERRUPT_V  0x1FFFFFFFU
+#define GPIO_STATUS_INTERRUPT_S  0
+
+/** GPIO_STATUS_W1TS_REG register
+ *  GPIO interrupt status set register
+ */
+#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x78)
+/** GPIO_STATUS_W1TS : WT; bitpos: [28:0]; default: 0;
+ *  Configures whether or not to set the interrupt status register
+ *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
+ *
+ *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
+ *  - If the value 1 is written to a bit here, the corresponding bit in
+ *  GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
+ *  register to set GPIO_STATUS_INTERRUPT.
+ */
+#define GPIO_STATUS_W1TS    0x1FFFFFFFU
+#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
+#define GPIO_STATUS_W1TS_V  0x1FFFFFFFU
+#define GPIO_STATUS_W1TS_S  0
+
+/** GPIO_STATUS_W1TC_REG register
+ *  GPIO interrupt status clear register
+ */
+#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x7c)
+/** GPIO_STATUS_W1TC : WT; bitpos: [28:0]; default: 0;
+ *  Configures whether or not to clear the interrupt status register
+ *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
+ *
+ *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
+ *  - If the value 1 is written to a bit here, the corresponding bit in
+ *  GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
+ *  register to clear GPIO_STATUS_INTERRUPT.
+ */
+#define GPIO_STATUS_W1TC    0x1FFFFFFFU
+#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
+#define GPIO_STATUS_W1TC_V  0x1FFFFFFFU
+#define GPIO_STATUS_W1TC_S  0
+
+/** GPIO_PROCPU_INT_REG register
+ *  CPU interrupt status register
+ */
+#define GPIO_PROCPU_INT_REG (DR_REG_GPIO_BASE + 0xa4)
+/** GPIO_PROCPU_INT : RO; bitpos: [28:0]; default: 0;
+ *  Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\
+ *  0: Represents CPU interrupt is not enabled, or the GPIO does not generate the
+ *  interrupt configured by GPIO_PIN$n_INT_TYPE.\\
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the CPU interrupt is enabled.\\
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG). \\
+ */
+#define GPIO_PROCPU_INT    0x1FFFFFFFU
+#define GPIO_PROCPU_INT_M  (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S)
+#define GPIO_PROCPU_INT_V  0x1FFFFFFFU
+#define GPIO_PROCPU_INT_S  0
+
+/** GPIO_STATUS_NEXT_REG register
+ *  GPIO interrupt source register
+ */
+#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xb4)
+/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [28:0]; default: 0;
+ *  Represents the interrupt source signal of GPIO0 ~ GPIO24.\\
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each
+ *  bit represents:\\
+ *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\
+ *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\
+ *  The interrupt could be rising edge interrupt, falling edge interrupt, level
+ *  sensitive interrupt and any edge interrupt.\\
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT    0x1FFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0x1FFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+/** GPIO_PIN0_REG register
+ *  GPIO0 configuration register
+ */
+#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xc4)
+/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
+#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN0_INT_TYPE    0x00000007U
+#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
+#define GPIO_PIN0_INT_TYPE_V  0x00000007U
+#define GPIO_PIN0_INT_TYPE_S  7
+/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN0_INT_ENA    0x0000001FU
+#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
+#define GPIO_PIN0_INT_ENA_V  0x0000001FU
+#define GPIO_PIN0_INT_ENA_S  13
+
+/** GPIO_PIN1_REG register
+ *  GPIO1 configuration register
+ */
+#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xc8)
+/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
+#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN1_INT_TYPE    0x00000007U
+#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
+#define GPIO_PIN1_INT_TYPE_V  0x00000007U
+#define GPIO_PIN1_INT_TYPE_S  7
+/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN1_INT_ENA    0x0000001FU
+#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
+#define GPIO_PIN1_INT_ENA_V  0x0000001FU
+#define GPIO_PIN1_INT_ENA_S  13
+
+/** GPIO_PIN2_REG register
+ *  GPIO2 configuration register
+ */
+#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xcc)
+/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
+#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN2_INT_TYPE    0x00000007U
+#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
+#define GPIO_PIN2_INT_TYPE_V  0x00000007U
+#define GPIO_PIN2_INT_TYPE_S  7
+/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN2_INT_ENA    0x0000001FU
+#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
+#define GPIO_PIN2_INT_ENA_V  0x0000001FU
+#define GPIO_PIN2_INT_ENA_S  13
+
+/** GPIO_PIN3_REG register
+ *  GPIO3 configuration register
+ */
+#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xd0)
+/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
+#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN3_INT_TYPE    0x00000007U
+#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
+#define GPIO_PIN3_INT_TYPE_V  0x00000007U
+#define GPIO_PIN3_INT_TYPE_S  7
+/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN3_INT_ENA    0x0000001FU
+#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
+#define GPIO_PIN3_INT_ENA_V  0x0000001FU
+#define GPIO_PIN3_INT_ENA_S  13
+
+/** GPIO_PIN4_REG register
+ *  GPIO4 configuration register
+ */
+#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xd4)
+/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
+#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN4_INT_TYPE    0x00000007U
+#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
+#define GPIO_PIN4_INT_TYPE_V  0x00000007U
+#define GPIO_PIN4_INT_TYPE_S  7
+/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN4_INT_ENA    0x0000001FU
+#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
+#define GPIO_PIN4_INT_ENA_V  0x0000001FU
+#define GPIO_PIN4_INT_ENA_S  13
+
+/** GPIO_PIN5_REG register
+ *  GPIO5 configuration register
+ */
+#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xd8)
+/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
+#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN5_INT_TYPE    0x00000007U
+#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
+#define GPIO_PIN5_INT_TYPE_V  0x00000007U
+#define GPIO_PIN5_INT_TYPE_S  7
+/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN5_INT_ENA    0x0000001FU
+#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
+#define GPIO_PIN5_INT_ENA_V  0x0000001FU
+#define GPIO_PIN5_INT_ENA_S  13
+
+/** GPIO_PIN6_REG register
+ *  GPIO6 configuration register
+ */
+#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xdc)
+/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
+#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN6_INT_TYPE    0x00000007U
+#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
+#define GPIO_PIN6_INT_TYPE_V  0x00000007U
+#define GPIO_PIN6_INT_TYPE_S  7
+/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN6_INT_ENA    0x0000001FU
+#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
+#define GPIO_PIN6_INT_ENA_V  0x0000001FU
+#define GPIO_PIN6_INT_ENA_S  13
+
+/** GPIO_PIN7_REG register
+ *  GPIO7 configuration register
+ */
+#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xe0)
+/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
+#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN7_INT_TYPE    0x00000007U
+#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
+#define GPIO_PIN7_INT_TYPE_V  0x00000007U
+#define GPIO_PIN7_INT_TYPE_S  7
+/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN7_INT_ENA    0x0000001FU
+#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
+#define GPIO_PIN7_INT_ENA_V  0x0000001FU
+#define GPIO_PIN7_INT_ENA_S  13
+
+/** GPIO_PIN8_REG register
+ *  GPIO8 configuration register
+ */
+#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xe4)
+/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
+#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN8_INT_TYPE    0x00000007U
+#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
+#define GPIO_PIN8_INT_TYPE_V  0x00000007U
+#define GPIO_PIN8_INT_TYPE_S  7
+/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN8_INT_ENA    0x0000001FU
+#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
+#define GPIO_PIN8_INT_ENA_V  0x0000001FU
+#define GPIO_PIN8_INT_ENA_S  13
+
+/** GPIO_PIN9_REG register
+ *  GPIO9 configuration register
+ */
+#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xe8)
+/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
+#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN9_INT_TYPE    0x00000007U
+#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
+#define GPIO_PIN9_INT_TYPE_V  0x00000007U
+#define GPIO_PIN9_INT_TYPE_S  7
+/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN9_INT_ENA    0x0000001FU
+#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
+#define GPIO_PIN9_INT_ENA_V  0x0000001FU
+#define GPIO_PIN9_INT_ENA_S  13
+
+/** GPIO_PIN10_REG register
+ *  GPIO10 configuration register
+ */
+#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xec)
+/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
+#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN10_INT_TYPE    0x00000007U
+#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
+#define GPIO_PIN10_INT_TYPE_V  0x00000007U
+#define GPIO_PIN10_INT_TYPE_S  7
+/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN10_INT_ENA    0x0000001FU
+#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
+#define GPIO_PIN10_INT_ENA_V  0x0000001FU
+#define GPIO_PIN10_INT_ENA_S  13
+
+/** GPIO_PIN11_REG register
+ *  GPIO11 configuration register
+ */
+#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xf0)
+/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
+#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN11_INT_TYPE    0x00000007U
+#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
+#define GPIO_PIN11_INT_TYPE_V  0x00000007U
+#define GPIO_PIN11_INT_TYPE_S  7
+/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN11_INT_ENA    0x0000001FU
+#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
+#define GPIO_PIN11_INT_ENA_V  0x0000001FU
+#define GPIO_PIN11_INT_ENA_S  13
+
+/** GPIO_PIN12_REG register
+ *  GPIO12 configuration register
+ */
+#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xf4)
+/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
+#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN12_INT_TYPE    0x00000007U
+#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
+#define GPIO_PIN12_INT_TYPE_V  0x00000007U
+#define GPIO_PIN12_INT_TYPE_S  7
+/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN12_INT_ENA    0x0000001FU
+#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
+#define GPIO_PIN12_INT_ENA_V  0x0000001FU
+#define GPIO_PIN12_INT_ENA_S  13
+
+/** GPIO_PIN13_REG register
+ *  GPIO13 configuration register
+ */
+#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xf8)
+/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
+#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN13_INT_TYPE    0x00000007U
+#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
+#define GPIO_PIN13_INT_TYPE_V  0x00000007U
+#define GPIO_PIN13_INT_TYPE_S  7
+/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN13_INT_ENA    0x0000001FU
+#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
+#define GPIO_PIN13_INT_ENA_V  0x0000001FU
+#define GPIO_PIN13_INT_ENA_S  13
+
+/** GPIO_PIN14_REG register
+ *  GPIO14 configuration register
+ */
+#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xfc)
+/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
+#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN14_INT_TYPE    0x00000007U
+#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
+#define GPIO_PIN14_INT_TYPE_V  0x00000007U
+#define GPIO_PIN14_INT_TYPE_S  7
+/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN14_INT_ENA    0x0000001FU
+#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
+#define GPIO_PIN14_INT_ENA_V  0x0000001FU
+#define GPIO_PIN14_INT_ENA_S  13
+
+/** GPIO_PIN15_REG register
+ *  GPIO15 configuration register
+ */
+#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x100)
+/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
+#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN15_INT_TYPE    0x00000007U
+#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
+#define GPIO_PIN15_INT_TYPE_V  0x00000007U
+#define GPIO_PIN15_INT_TYPE_S  7
+/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN15_INT_ENA    0x0000001FU
+#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
+#define GPIO_PIN15_INT_ENA_V  0x0000001FU
+#define GPIO_PIN15_INT_ENA_S  13
+
+/** GPIO_PIN16_REG register
+ *  GPIO16 configuration register
+ */
+#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x104)
+/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
+#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN16_INT_TYPE    0x00000007U
+#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
+#define GPIO_PIN16_INT_TYPE_V  0x00000007U
+#define GPIO_PIN16_INT_TYPE_S  7
+/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN16_INT_ENA    0x0000001FU
+#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
+#define GPIO_PIN16_INT_ENA_V  0x0000001FU
+#define GPIO_PIN16_INT_ENA_S  13
+
+/** GPIO_PIN17_REG register
+ *  GPIO17 configuration register
+ */
+#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x108)
+/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
+#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN17_INT_TYPE    0x00000007U
+#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
+#define GPIO_PIN17_INT_TYPE_V  0x00000007U
+#define GPIO_PIN17_INT_TYPE_S  7
+/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN17_INT_ENA    0x0000001FU
+#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
+#define GPIO_PIN17_INT_ENA_V  0x0000001FU
+#define GPIO_PIN17_INT_ENA_S  13
+
+/** GPIO_PIN18_REG register
+ *  GPIO18 configuration register
+ */
+#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x10c)
+/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
+#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN18_INT_TYPE    0x00000007U
+#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
+#define GPIO_PIN18_INT_TYPE_V  0x00000007U
+#define GPIO_PIN18_INT_TYPE_S  7
+/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN18_INT_ENA    0x0000001FU
+#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
+#define GPIO_PIN18_INT_ENA_V  0x0000001FU
+#define GPIO_PIN18_INT_ENA_S  13
+
+/** GPIO_PIN19_REG register
+ *  GPIO19 configuration register
+ */
+#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x110)
+/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
+#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN19_INT_TYPE    0x00000007U
+#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
+#define GPIO_PIN19_INT_TYPE_V  0x00000007U
+#define GPIO_PIN19_INT_TYPE_S  7
+/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN19_INT_ENA    0x0000001FU
+#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
+#define GPIO_PIN19_INT_ENA_V  0x0000001FU
+#define GPIO_PIN19_INT_ENA_S  13
+
+/** GPIO_PIN20_REG register
+ *  GPIO20 configuration register
+ */
+#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x114)
+/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
+#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN20_INT_TYPE    0x00000007U
+#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
+#define GPIO_PIN20_INT_TYPE_V  0x00000007U
+#define GPIO_PIN20_INT_TYPE_S  7
+/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN20_INT_ENA    0x0000001FU
+#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
+#define GPIO_PIN20_INT_ENA_V  0x0000001FU
+#define GPIO_PIN20_INT_ENA_S  13
+
+/** GPIO_PIN21_REG register
+ *  GPIO21 configuration register
+ */
+#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x118)
+/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
+#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN21_INT_TYPE    0x00000007U
+#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
+#define GPIO_PIN21_INT_TYPE_V  0x00000007U
+#define GPIO_PIN21_INT_TYPE_S  7
+/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN21_INT_ENA    0x0000001FU
+#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
+#define GPIO_PIN21_INT_ENA_V  0x0000001FU
+#define GPIO_PIN21_INT_ENA_S  13
+
+/** GPIO_PIN22_REG register
+ *  GPIO22 configuration register
+ */
+#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c)
+/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN22_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_M  (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
+#define GPIO_PIN22_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN22_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_M  (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN22_INT_TYPE    0x00000007U
+#define GPIO_PIN22_INT_TYPE_M  (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
+#define GPIO_PIN22_INT_TYPE_V  0x00000007U
+#define GPIO_PIN22_INT_TYPE_S  7
+/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN22_INT_ENA    0x0000001FU
+#define GPIO_PIN22_INT_ENA_M  (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
+#define GPIO_PIN22_INT_ENA_V  0x0000001FU
+#define GPIO_PIN22_INT_ENA_S  13
+
+/** GPIO_PIN23_REG register
+ *  GPIO23 configuration register
+ */
+#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120)
+/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN23_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_M  (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
+#define GPIO_PIN23_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN23_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_M  (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN23_INT_TYPE    0x00000007U
+#define GPIO_PIN23_INT_TYPE_M  (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
+#define GPIO_PIN23_INT_TYPE_V  0x00000007U
+#define GPIO_PIN23_INT_TYPE_S  7
+/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN23_INT_ENA    0x0000001FU
+#define GPIO_PIN23_INT_ENA_M  (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
+#define GPIO_PIN23_INT_ENA_V  0x0000001FU
+#define GPIO_PIN23_INT_ENA_S  13
+
+/** GPIO_PIN24_REG register
+ *  GPIO24 configuration register
+ */
+#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124)
+/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN24_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_M  (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode. \\
+ *  0: Normal output\\
+ *  1: Open drain output \\
+ */
+#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
+#define GPIO_PIN24_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.\\
+ *  0: Not synchronize\\
+ *  1: Synchronize on falling edge\\
+ *  2: Synchronize on rising edge\\
+ *  3: Synchronize on rising edge\\
+ */
+#define GPIO_PIN24_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_M  (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.\\
+ *  0: GPIO interrupt disabled\\
+ *  1: Rising edge trigger\\
+ *  2: Falling edge trigger\\
+ *  3: Any edge trigger\\
+ *  4: Low level trigger\\
+ *  5: High level trigger\\
+ */
+#define GPIO_PIN24_INT_TYPE    0x00000007U
+#define GPIO_PIN24_INT_TYPE_M  (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
+#define GPIO_PIN24_INT_TYPE_V  0x00000007U
+#define GPIO_PIN24_INT_TYPE_S  7
+/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  This function only wakes up the CPU from Light-sleep. \\
+ */
+#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable CPU interrupt.
+ *
+ *  - bit13: Configures whether or not to enable CPU interrupt:\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  - bit14 ~ bit17: invalid
+ */
+#define GPIO_PIN24_INT_ENA    0x0000001FU
+#define GPIO_PIN24_INT_ENA_M  (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
+#define GPIO_PIN24_INT_ENA_V  0x0000001FU
+#define GPIO_PIN24_INT_ENA_S  13
+
+/** GPIO_FUNC0_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 0
+ */
+#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
+/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC0_IN_SEL    0x0000003FU
+#define GPIO_FUNC0_IN_SEL_M  (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S)
+#define GPIO_FUNC0_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC0_IN_SEL_S  0
+/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC0_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC0_IN_INV_SEL_M  (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S)
+#define GPIO_FUNC0_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_IN_INV_SEL_S  6
+/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG0_IN_SEL    (BIT(7))
+#define GPIO_SIG0_IN_SEL_M  (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S)
+#define GPIO_SIG0_IN_SEL_V  0x00000001U
+#define GPIO_SIG0_IN_SEL_S  7
+
+/** GPIO_FUNC6_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 6
+ */
+#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
+/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 6.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC6_IN_SEL    0x0000003FU
+#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
+#define GPIO_FUNC6_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC6_IN_SEL_S  0
+/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
+#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_IN_INV_SEL_S  6
+/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG6_IN_SEL    (BIT(7))
+#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
+#define GPIO_SIG6_IN_SEL_V  0x00000001U
+#define GPIO_SIG6_IN_SEL_S  7
+
+/** GPIO_FUNC7_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 7
+ */
+#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
+/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 7.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC7_IN_SEL    0x0000003FU
+#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
+#define GPIO_FUNC7_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC7_IN_SEL_S  0
+/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
+#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_IN_INV_SEL_S  6
+/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG7_IN_SEL    (BIT(7))
+#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
+#define GPIO_SIG7_IN_SEL_V  0x00000001U
+#define GPIO_SIG7_IN_SEL_S  7
+
+/** GPIO_FUNC8_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 8
+ */
+#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
+/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 8.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC8_IN_SEL    0x0000003FU
+#define GPIO_FUNC8_IN_SEL_M  (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S)
+#define GPIO_FUNC8_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC8_IN_SEL_S  0
+/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_M  (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S)
+#define GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_IN_INV_SEL_S  6
+/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG8_IN_SEL    (BIT(7))
+#define GPIO_SIG8_IN_SEL_M  (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S)
+#define GPIO_SIG8_IN_SEL_V  0x00000001U
+#define GPIO_SIG8_IN_SEL_S  7
+
+/** GPIO_FUNC9_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 9
+ */
+#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
+/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 9.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC9_IN_SEL    0x0000003FU
+#define GPIO_FUNC9_IN_SEL_M  (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S)
+#define GPIO_FUNC9_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC9_IN_SEL_S  0
+/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_M  (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S)
+#define GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_IN_INV_SEL_S  6
+/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG9_IN_SEL    (BIT(7))
+#define GPIO_SIG9_IN_SEL_M  (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S)
+#define GPIO_SIG9_IN_SEL_V  0x00000001U
+#define GPIO_SIG9_IN_SEL_S  7
+
+/** GPIO_FUNC10_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 10
+ */
+#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
+/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 10.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC10_IN_SEL    0x0000003FU
+#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
+#define GPIO_FUNC10_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC10_IN_SEL_S  0
+/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
+#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_IN_INV_SEL_S  6
+/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG10_IN_SEL    (BIT(7))
+#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
+#define GPIO_SIG10_IN_SEL_V  0x00000001U
+#define GPIO_SIG10_IN_SEL_S  7
+
+/** GPIO_FUNC11_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 11
+ */
+#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
+/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 11.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC11_IN_SEL    0x0000003FU
+#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
+#define GPIO_FUNC11_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC11_IN_SEL_S  0
+/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
+#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_IN_INV_SEL_S  6
+/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG11_IN_SEL    (BIT(7))
+#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
+#define GPIO_SIG11_IN_SEL_V  0x00000001U
+#define GPIO_SIG11_IN_SEL_S  7
+
+/** GPIO_FUNC12_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 12
+ */
+#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
+/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 12.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC12_IN_SEL    0x0000003FU
+#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
+#define GPIO_FUNC12_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC12_IN_SEL_S  0
+/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
+#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_IN_INV_SEL_S  6
+/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG12_IN_SEL    (BIT(7))
+#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
+#define GPIO_SIG12_IN_SEL_V  0x00000001U
+#define GPIO_SIG12_IN_SEL_S  7
+
+/** GPIO_FUNC13_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 13
+ */
+#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
+/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 13.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC13_IN_SEL    0x0000003FU
+#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
+#define GPIO_FUNC13_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC13_IN_SEL_S  0
+/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
+#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_IN_INV_SEL_S  6
+/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG13_IN_SEL    (BIT(7))
+#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
+#define GPIO_SIG13_IN_SEL_V  0x00000001U
+#define GPIO_SIG13_IN_SEL_S  7
+
+/** GPIO_FUNC14_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 14
+ */
+#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
+/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 14.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC14_IN_SEL    0x0000003FU
+#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
+#define GPIO_FUNC14_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC14_IN_SEL_S  0
+/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
+#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_IN_INV_SEL_S  6
+/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG14_IN_SEL    (BIT(7))
+#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
+#define GPIO_SIG14_IN_SEL_V  0x00000001U
+#define GPIO_SIG14_IN_SEL_S  7
+
+/** GPIO_FUNC15_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 15
+ */
+#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
+/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 15.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC15_IN_SEL    0x0000003FU
+#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
+#define GPIO_FUNC15_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC15_IN_SEL_S  0
+/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
+#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_IN_INV_SEL_S  6
+/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG15_IN_SEL    (BIT(7))
+#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
+#define GPIO_SIG15_IN_SEL_V  0x00000001U
+#define GPIO_SIG15_IN_SEL_S  7
+
+/** GPIO_FUNC16_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 16
+ */
+#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
+/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 16.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC16_IN_SEL    0x0000003FU
+#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
+#define GPIO_FUNC16_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC16_IN_SEL_S  0
+/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
+#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_IN_INV_SEL_S  6
+/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG16_IN_SEL    (BIT(7))
+#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
+#define GPIO_SIG16_IN_SEL_V  0x00000001U
+#define GPIO_SIG16_IN_SEL_S  7
+
+/** GPIO_FUNC17_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 17
+ */
+#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
+/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 17.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC17_IN_SEL    0x0000003FU
+#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
+#define GPIO_FUNC17_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC17_IN_SEL_S  0
+/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
+#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_IN_INV_SEL_S  6
+/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG17_IN_SEL    (BIT(7))
+#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
+#define GPIO_SIG17_IN_SEL_V  0x00000001U
+#define GPIO_SIG17_IN_SEL_S  7
+
+/** GPIO_FUNC27_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 27
+ */
+#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
+/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 27.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC27_IN_SEL    0x0000003FU
+#define GPIO_FUNC27_IN_SEL_M  (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S)
+#define GPIO_FUNC27_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC27_IN_SEL_S  0
+/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC27_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_M  (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S)
+#define GPIO_FUNC27_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_IN_INV_SEL_S  6
+/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG27_IN_SEL    (BIT(7))
+#define GPIO_SIG27_IN_SEL_M  (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S)
+#define GPIO_SIG27_IN_SEL_V  0x00000001U
+#define GPIO_SIG27_IN_SEL_S  7
+
+/** GPIO_FUNC28_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 28
+ */
+#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334)
+/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 28.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC28_IN_SEL    0x0000003FU
+#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
+#define GPIO_FUNC28_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC28_IN_SEL_S  0
+/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
+#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_IN_INV_SEL_S  6
+/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG28_IN_SEL    (BIT(7))
+#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
+#define GPIO_SIG28_IN_SEL_V  0x00000001U
+#define GPIO_SIG28_IN_SEL_S  7
+
+/** GPIO_FUNC29_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 29
+ */
+#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338)
+/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 29.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC29_IN_SEL    0x0000003FU
+#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
+#define GPIO_FUNC29_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC29_IN_SEL_S  0
+/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
+#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_IN_INV_SEL_S  6
+/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG29_IN_SEL    (BIT(7))
+#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
+#define GPIO_SIG29_IN_SEL_V  0x00000001U
+#define GPIO_SIG29_IN_SEL_S  7
+
+/** GPIO_FUNC30_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 30
+ */
+#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c)
+/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 30.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC30_IN_SEL    0x0000003FU
+#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
+#define GPIO_FUNC30_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC30_IN_SEL_S  0
+/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
+#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_IN_INV_SEL_S  6
+/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG30_IN_SEL    (BIT(7))
+#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
+#define GPIO_SIG30_IN_SEL_V  0x00000001U
+#define GPIO_SIG30_IN_SEL_S  7
+
+/** GPIO_FUNC31_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 31
+ */
+#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340)
+/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 31.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC31_IN_SEL    0x0000003FU
+#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
+#define GPIO_FUNC31_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC31_IN_SEL_S  0
+/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
+#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_IN_INV_SEL_S  6
+/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG31_IN_SEL    (BIT(7))
+#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
+#define GPIO_SIG31_IN_SEL_V  0x00000001U
+#define GPIO_SIG31_IN_SEL_S  7
+
+/** GPIO_FUNC32_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 32
+ */
+#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344)
+/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 32.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC32_IN_SEL    0x0000003FU
+#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
+#define GPIO_FUNC32_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC32_IN_SEL_S  0
+/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
+#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_IN_INV_SEL_S  6
+/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG32_IN_SEL    (BIT(7))
+#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
+#define GPIO_SIG32_IN_SEL_V  0x00000001U
+#define GPIO_SIG32_IN_SEL_S  7
+
+/** GPIO_FUNC33_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 33
+ */
+#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348)
+/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 33.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC33_IN_SEL    0x0000003FU
+#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
+#define GPIO_FUNC33_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC33_IN_SEL_S  0
+/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
+#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_IN_INV_SEL_S  6
+/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG33_IN_SEL    (BIT(7))
+#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
+#define GPIO_SIG33_IN_SEL_V  0x00000001U
+#define GPIO_SIG33_IN_SEL_S  7
+
+/** GPIO_FUNC34_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 34
+ */
+#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c)
+/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 34.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC34_IN_SEL    0x0000003FU
+#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
+#define GPIO_FUNC34_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC34_IN_SEL_S  0
+/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
+#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_IN_INV_SEL_S  6
+/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG34_IN_SEL    (BIT(7))
+#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
+#define GPIO_SIG34_IN_SEL_V  0x00000001U
+#define GPIO_SIG34_IN_SEL_S  7
+
+/** GPIO_FUNC35_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 35
+ */
+#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
+/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 35.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC35_IN_SEL    0x0000003FU
+#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
+#define GPIO_FUNC35_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC35_IN_SEL_S  0
+/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
+#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_IN_INV_SEL_S  6
+/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG35_IN_SEL    (BIT(7))
+#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
+#define GPIO_SIG35_IN_SEL_V  0x00000001U
+#define GPIO_SIG35_IN_SEL_S  7
+
+/** GPIO_FUNC41_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 41
+ */
+#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368)
+/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 41.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC41_IN_SEL    0x0000003FU
+#define GPIO_FUNC41_IN_SEL_M  (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S)
+#define GPIO_FUNC41_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC41_IN_SEL_S  0
+/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_M  (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S)
+#define GPIO_FUNC41_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_IN_INV_SEL_S  6
+/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG41_IN_SEL    (BIT(7))
+#define GPIO_SIG41_IN_SEL_M  (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S)
+#define GPIO_SIG41_IN_SEL_V  0x00000001U
+#define GPIO_SIG41_IN_SEL_S  7
+
+/** GPIO_FUNC42_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 42
+ */
+#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c)
+/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 42.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC42_IN_SEL    0x0000003FU
+#define GPIO_FUNC42_IN_SEL_M  (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S)
+#define GPIO_FUNC42_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC42_IN_SEL_S  0
+/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_M  (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S)
+#define GPIO_FUNC42_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_IN_INV_SEL_S  6
+/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG42_IN_SEL    (BIT(7))
+#define GPIO_SIG42_IN_SEL_M  (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S)
+#define GPIO_SIG42_IN_SEL_V  0x00000001U
+#define GPIO_SIG42_IN_SEL_S  7
+
+/** GPIO_FUNC43_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 43
+ */
+#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370)
+/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 43.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC43_IN_SEL    0x0000003FU
+#define GPIO_FUNC43_IN_SEL_M  (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S)
+#define GPIO_FUNC43_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC43_IN_SEL_S  0
+/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC43_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_M  (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S)
+#define GPIO_FUNC43_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_IN_INV_SEL_S  6
+/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG43_IN_SEL    (BIT(7))
+#define GPIO_SIG43_IN_SEL_M  (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S)
+#define GPIO_SIG43_IN_SEL_V  0x00000001U
+#define GPIO_SIG43_IN_SEL_S  7
+
+/** GPIO_FUNC46_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 46
+ */
+#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c)
+/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 32;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 46.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC46_IN_SEL    0x0000003FU
+#define GPIO_FUNC46_IN_SEL_M  (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S)
+#define GPIO_FUNC46_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC46_IN_SEL_S  0
+/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC46_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC46_IN_INV_SEL_M  (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S)
+#define GPIO_FUNC46_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_IN_INV_SEL_S  6
+/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG46_IN_SEL    (BIT(7))
+#define GPIO_SIG46_IN_SEL_M  (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S)
+#define GPIO_SIG46_IN_SEL_V  0x00000001U
+#define GPIO_SIG46_IN_SEL_S  7
+
+/** GPIO_FUNC47_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 47
+ */
+#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380)
+/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 32;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 47.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC47_IN_SEL    0x0000003FU
+#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
+#define GPIO_FUNC47_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC47_IN_SEL_S  0
+/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
+#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_IN_INV_SEL_S  6
+/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG47_IN_SEL    (BIT(7))
+#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
+#define GPIO_SIG47_IN_SEL_V  0x00000001U
+#define GPIO_SIG47_IN_SEL_S  7
+
+/** GPIO_FUNC64_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 64
+ */
+#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4)
+/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 64.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC64_IN_SEL    0x0000003FU
+#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
+#define GPIO_FUNC64_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC64_IN_SEL_S  0
+/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
+#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC64_IN_INV_SEL_S  6
+/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG64_IN_SEL    (BIT(7))
+#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
+#define GPIO_SIG64_IN_SEL_V  0x00000001U
+#define GPIO_SIG64_IN_SEL_S  7
+
+/** GPIO_FUNC65_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 65
+ */
+#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8)
+/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 65.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC65_IN_SEL    0x0000003FU
+#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
+#define GPIO_FUNC65_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC65_IN_SEL_S  0
+/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
+#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC65_IN_INV_SEL_S  6
+/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG65_IN_SEL    (BIT(7))
+#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
+#define GPIO_SIG65_IN_SEL_V  0x00000001U
+#define GPIO_SIG65_IN_SEL_S  7
+
+/** GPIO_FUNC66_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 66
+ */
+#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc)
+/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 66.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC66_IN_SEL    0x0000003FU
+#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
+#define GPIO_FUNC66_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC66_IN_SEL_S  0
+/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
+#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC66_IN_INV_SEL_S  6
+/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG66_IN_SEL    (BIT(7))
+#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
+#define GPIO_SIG66_IN_SEL_V  0x00000001U
+#define GPIO_SIG66_IN_SEL_S  7
+
+/** GPIO_FUNC67_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 67
+ */
+#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0)
+/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 67.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC67_IN_SEL    0x0000003FU
+#define GPIO_FUNC67_IN_SEL_M  (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S)
+#define GPIO_FUNC67_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC67_IN_SEL_S  0
+/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC67_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC67_IN_INV_SEL_M  (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S)
+#define GPIO_FUNC67_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC67_IN_INV_SEL_S  6
+/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG67_IN_SEL    (BIT(7))
+#define GPIO_SIG67_IN_SEL_M  (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S)
+#define GPIO_SIG67_IN_SEL_V  0x00000001U
+#define GPIO_SIG67_IN_SEL_S  7
+
+/** GPIO_FUNC68_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 68
+ */
+#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4)
+/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 68.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC68_IN_SEL    0x0000003FU
+#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
+#define GPIO_FUNC68_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC68_IN_SEL_S  0
+/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
+#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC68_IN_INV_SEL_S  6
+/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG68_IN_SEL    (BIT(7))
+#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
+#define GPIO_SIG68_IN_SEL_V  0x00000001U
+#define GPIO_SIG68_IN_SEL_S  7
+
+/** GPIO_FUNC69_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 69
+ */
+#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8)
+/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 69.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC69_IN_SEL    0x0000003FU
+#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
+#define GPIO_FUNC69_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC69_IN_SEL_S  0
+/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
+#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC69_IN_INV_SEL_S  6
+/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG69_IN_SEL    (BIT(7))
+#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
+#define GPIO_SIG69_IN_SEL_V  0x00000001U
+#define GPIO_SIG69_IN_SEL_S  7
+
+/** GPIO_FUNC72_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 72
+ */
+#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4)
+/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 32;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 72.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC72_IN_SEL    0x0000003FU
+#define GPIO_FUNC72_IN_SEL_M  (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S)
+#define GPIO_FUNC72_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC72_IN_SEL_S  0
+/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC72_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC72_IN_INV_SEL_M  (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S)
+#define GPIO_FUNC72_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC72_IN_INV_SEL_S  6
+/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG72_IN_SEL    (BIT(7))
+#define GPIO_SIG72_IN_SEL_M  (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S)
+#define GPIO_SIG72_IN_SEL_V  0x00000001U
+#define GPIO_SIG72_IN_SEL_S  7
+
+/** GPIO_FUNC73_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 73
+ */
+#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8)
+/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 32;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 73.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC73_IN_SEL    0x0000003FU
+#define GPIO_FUNC73_IN_SEL_M  (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S)
+#define GPIO_FUNC73_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC73_IN_SEL_S  0
+/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC73_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC73_IN_INV_SEL_M  (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S)
+#define GPIO_FUNC73_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC73_IN_INV_SEL_S  6
+/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG73_IN_SEL    (BIT(7))
+#define GPIO_SIG73_IN_SEL_M  (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S)
+#define GPIO_SIG73_IN_SEL_V  0x00000001U
+#define GPIO_SIG73_IN_SEL_S  7
+
+/** GPIO_FUNC74_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 74
+ */
+#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec)
+/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 32;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 74.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC74_IN_SEL    0x0000003FU
+#define GPIO_FUNC74_IN_SEL_M  (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S)
+#define GPIO_FUNC74_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC74_IN_SEL_S  0
+/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC74_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_M  (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S)
+#define GPIO_FUNC74_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC74_IN_INV_SEL_S  6
+/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG74_IN_SEL    (BIT(7))
+#define GPIO_SIG74_IN_SEL_M  (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S)
+#define GPIO_SIG74_IN_SEL_V  0x00000001U
+#define GPIO_SIG74_IN_SEL_S  7
+
+/** GPIO_FUNC82_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 82
+ */
+#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c)
+/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 82.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC82_IN_SEL    0x0000003FU
+#define GPIO_FUNC82_IN_SEL_M  (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S)
+#define GPIO_FUNC82_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC82_IN_SEL_S  0
+/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC82_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC82_IN_INV_SEL_M  (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S)
+#define GPIO_FUNC82_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC82_IN_INV_SEL_S  6
+/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG82_IN_SEL    (BIT(7))
+#define GPIO_SIG82_IN_SEL_M  (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S)
+#define GPIO_SIG82_IN_SEL_V  0x00000001U
+#define GPIO_SIG82_IN_SEL_S  7
+
+/** GPIO_FUNC83_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 83
+ */
+#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410)
+/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 83.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC83_IN_SEL    0x0000003FU
+#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
+#define GPIO_FUNC83_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC83_IN_SEL_S  0
+/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
+#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC83_IN_INV_SEL_S  6
+/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG83_IN_SEL    (BIT(7))
+#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
+#define GPIO_SIG83_IN_SEL_V  0x00000001U
+#define GPIO_SIG83_IN_SEL_S  7
+
+/** GPIO_FUNC97_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 97
+ */
+#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448)
+/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 97.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC97_IN_SEL    0x0000003FU
+#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
+#define GPIO_FUNC97_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC97_IN_SEL_S  0
+/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
+#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC97_IN_INV_SEL_S  6
+/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG97_IN_SEL    (BIT(7))
+#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
+#define GPIO_SIG97_IN_SEL_V  0x00000001U
+#define GPIO_SIG97_IN_SEL_S  7
+
+/** GPIO_FUNC98_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 98
+ */
+#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c)
+/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 98.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC98_IN_SEL    0x0000003FU
+#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
+#define GPIO_FUNC98_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC98_IN_SEL_S  0
+/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
+#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC98_IN_INV_SEL_S  6
+/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG98_IN_SEL    (BIT(7))
+#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
+#define GPIO_SIG98_IN_SEL_V  0x00000001U
+#define GPIO_SIG98_IN_SEL_S  7
+
+/** GPIO_FUNC99_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 99
+ */
+#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450)
+/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 99.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC99_IN_SEL    0x0000003FU
+#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
+#define GPIO_FUNC99_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC99_IN_SEL_S  0
+/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
+#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC99_IN_INV_SEL_S  6
+/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG99_IN_SEL    (BIT(7))
+#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
+#define GPIO_SIG99_IN_SEL_V  0x00000001U
+#define GPIO_SIG99_IN_SEL_S  7
+
+/** GPIO_FUNC100_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 100
+ */
+#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454)
+/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 100.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC100_IN_SEL    0x0000003FU
+#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
+#define GPIO_FUNC100_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC100_IN_SEL_S  0
+/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
+#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC100_IN_INV_SEL_S  6
+/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG100_IN_SEL    (BIT(7))
+#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
+#define GPIO_SIG100_IN_SEL_V  0x00000001U
+#define GPIO_SIG100_IN_SEL_S  7
+
+/** GPIO_FUNC118_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 118
+ */
+#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c)
+/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 118.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC118_IN_SEL    0x0000003FU
+#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
+#define GPIO_FUNC118_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC118_IN_SEL_S  0
+/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
+#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC118_IN_INV_SEL_S  6
+/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG118_IN_SEL    (BIT(7))
+#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
+#define GPIO_SIG118_IN_SEL_V  0x00000001U
+#define GPIO_SIG118_IN_SEL_S  7
+
+/** GPIO_FUNC119_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 119
+ */
+#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0)
+/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 119.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC119_IN_SEL    0x0000003FU
+#define GPIO_FUNC119_IN_SEL_M  (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S)
+#define GPIO_FUNC119_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC119_IN_SEL_S  0
+/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC119_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC119_IN_INV_SEL_M  (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S)
+#define GPIO_FUNC119_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC119_IN_INV_SEL_S  6
+/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG119_IN_SEL    (BIT(7))
+#define GPIO_SIG119_IN_SEL_M  (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S)
+#define GPIO_SIG119_IN_SEL_V  0x00000001U
+#define GPIO_SIG119_IN_SEL_S  7
+
+/** GPIO_FUNC120_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 120
+ */
+#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4)
+/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 120.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC120_IN_SEL    0x0000003FU
+#define GPIO_FUNC120_IN_SEL_M  (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S)
+#define GPIO_FUNC120_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC120_IN_SEL_S  0
+/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC120_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC120_IN_INV_SEL_M  (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S)
+#define GPIO_FUNC120_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC120_IN_INV_SEL_S  6
+/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG120_IN_SEL    (BIT(7))
+#define GPIO_SIG120_IN_SEL_M  (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S)
+#define GPIO_SIG120_IN_SEL_V  0x00000001U
+#define GPIO_SIG120_IN_SEL_S  7
+
+/** GPIO_FUNC121_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 121
+ */
+#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a8)
+/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 48;
+ *  Configures to select a pin from the 25 GPIO pins to connect the input signal 121.\\
+ *  0: Select GPIO0\\
+ *  1: Select GPIO1\\
+ *  ......\\
+ *  23: Select GPIO23\\
+ *  24: Select GPIO24\\
+ *  Or\\
+ *  0x20: A constantly high input\\
+ *  0x30: A constantly low input\\
+ */
+#define GPIO_FUNC121_IN_SEL    0x0000003FU
+#define GPIO_FUNC121_IN_SEL_M  (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S)
+#define GPIO_FUNC121_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC121_IN_SEL_S  0
+/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to invert the input value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC121_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC121_IN_INV_SEL_M  (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S)
+#define GPIO_FUNC121_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC121_IN_INV_SEL_S  6
+/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.\\
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.\\
+ *  1: Route signals via GPIO matrix.\\
+ */
+#define GPIO_SIG121_IN_SEL    (BIT(7))
+#define GPIO_SIG121_IN_SEL_M  (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S)
+#define GPIO_SIG121_IN_SEL_V  0x00000001U
+#define GPIO_SIG121_IN_SEL_S  7
+
+/** GPIO_FUNC0_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO0 output
+ */
+#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac4)
+/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO0.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 0 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC0_OUT_SEL    0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
+#define GPIO_FUNC0_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_S  0
+/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OUT_INV_SEL_S  9
+/** GPIO_FUNC0_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 0 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC0_OE_SEL    (BIT(10))
+#define GPIO_FUNC0_OE_SEL_M  (GPIO_FUNC0_OE_SEL_V << GPIO_FUNC0_OE_SEL_S)
+#define GPIO_FUNC0_OE_SEL_V  0x00000001U
+#define GPIO_FUNC0_OE_SEL_S  10
+/** GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC0_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC0_OE_INV_SEL_M  (GPIO_FUNC0_OE_INV_SEL_V << GPIO_FUNC0_OE_INV_SEL_S)
+#define GPIO_FUNC0_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OE_INV_SEL_S  11
+
+/** GPIO_FUNC1_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO1 output
+ */
+#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac8)
+/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO1.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 1 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC1_OUT_SEL    0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
+#define GPIO_FUNC1_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_S  0
+/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OUT_INV_SEL_S  9
+/** GPIO_FUNC1_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 1 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC1_OE_SEL    (BIT(10))
+#define GPIO_FUNC1_OE_SEL_M  (GPIO_FUNC1_OE_SEL_V << GPIO_FUNC1_OE_SEL_S)
+#define GPIO_FUNC1_OE_SEL_V  0x00000001U
+#define GPIO_FUNC1_OE_SEL_S  10
+/** GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC1_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC1_OE_INV_SEL_M  (GPIO_FUNC1_OE_INV_SEL_V << GPIO_FUNC1_OE_INV_SEL_S)
+#define GPIO_FUNC1_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OE_INV_SEL_S  11
+
+/** GPIO_FUNC2_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO2 output
+ */
+#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xacc)
+/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO2.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 2 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC2_OUT_SEL    0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
+#define GPIO_FUNC2_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_S  0
+/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OUT_INV_SEL_S  9
+/** GPIO_FUNC2_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 2 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC2_OE_SEL    (BIT(10))
+#define GPIO_FUNC2_OE_SEL_M  (GPIO_FUNC2_OE_SEL_V << GPIO_FUNC2_OE_SEL_S)
+#define GPIO_FUNC2_OE_SEL_V  0x00000001U
+#define GPIO_FUNC2_OE_SEL_S  10
+/** GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC2_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC2_OE_INV_SEL_M  (GPIO_FUNC2_OE_INV_SEL_V << GPIO_FUNC2_OE_INV_SEL_S)
+#define GPIO_FUNC2_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OE_INV_SEL_S  11
+
+/** GPIO_FUNC3_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO3 output
+ */
+#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad0)
+/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO3.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 3 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC3_OUT_SEL    0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
+#define GPIO_FUNC3_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_S  0
+/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OUT_INV_SEL_S  9
+/** GPIO_FUNC3_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 3 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC3_OE_SEL    (BIT(10))
+#define GPIO_FUNC3_OE_SEL_M  (GPIO_FUNC3_OE_SEL_V << GPIO_FUNC3_OE_SEL_S)
+#define GPIO_FUNC3_OE_SEL_V  0x00000001U
+#define GPIO_FUNC3_OE_SEL_S  10
+/** GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC3_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC3_OE_INV_SEL_M  (GPIO_FUNC3_OE_INV_SEL_V << GPIO_FUNC3_OE_INV_SEL_S)
+#define GPIO_FUNC3_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OE_INV_SEL_S  11
+
+/** GPIO_FUNC4_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO4 output
+ */
+#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4)
+/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO4.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 4 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC4_OUT_SEL    0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
+#define GPIO_FUNC4_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_S  0
+/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OUT_INV_SEL_S  9
+/** GPIO_FUNC4_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 4 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC4_OE_SEL    (BIT(10))
+#define GPIO_FUNC4_OE_SEL_M  (GPIO_FUNC4_OE_SEL_V << GPIO_FUNC4_OE_SEL_S)
+#define GPIO_FUNC4_OE_SEL_V  0x00000001U
+#define GPIO_FUNC4_OE_SEL_S  10
+/** GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC4_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC4_OE_INV_SEL_M  (GPIO_FUNC4_OE_INV_SEL_V << GPIO_FUNC4_OE_INV_SEL_S)
+#define GPIO_FUNC4_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OE_INV_SEL_S  11
+
+/** GPIO_FUNC5_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO5 output
+ */
+#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8)
+/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO5.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 5 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC5_OUT_SEL    0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
+#define GPIO_FUNC5_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_S  0
+/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OUT_INV_SEL_S  9
+/** GPIO_FUNC5_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 5 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC5_OE_SEL    (BIT(10))
+#define GPIO_FUNC5_OE_SEL_M  (GPIO_FUNC5_OE_SEL_V << GPIO_FUNC5_OE_SEL_S)
+#define GPIO_FUNC5_OE_SEL_V  0x00000001U
+#define GPIO_FUNC5_OE_SEL_S  10
+/** GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC5_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC5_OE_INV_SEL_M  (GPIO_FUNC5_OE_INV_SEL_V << GPIO_FUNC5_OE_INV_SEL_S)
+#define GPIO_FUNC5_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OE_INV_SEL_S  11
+
+/** GPIO_FUNC6_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO6 output
+ */
+#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc)
+/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO6.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 6 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC6_OUT_SEL    0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
+#define GPIO_FUNC6_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_S  0
+/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OUT_INV_SEL_S  9
+/** GPIO_FUNC6_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 6 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC6_OE_SEL    (BIT(10))
+#define GPIO_FUNC6_OE_SEL_M  (GPIO_FUNC6_OE_SEL_V << GPIO_FUNC6_OE_SEL_S)
+#define GPIO_FUNC6_OE_SEL_V  0x00000001U
+#define GPIO_FUNC6_OE_SEL_S  10
+/** GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC6_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC6_OE_INV_SEL_M  (GPIO_FUNC6_OE_INV_SEL_V << GPIO_FUNC6_OE_INV_SEL_S)
+#define GPIO_FUNC6_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OE_INV_SEL_S  11
+
+/** GPIO_FUNC7_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO7 output
+ */
+#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0)
+/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO7.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 7 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC7_OUT_SEL    0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
+#define GPIO_FUNC7_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_S  0
+/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OUT_INV_SEL_S  9
+/** GPIO_FUNC7_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 7 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC7_OE_SEL    (BIT(10))
+#define GPIO_FUNC7_OE_SEL_M  (GPIO_FUNC7_OE_SEL_V << GPIO_FUNC7_OE_SEL_S)
+#define GPIO_FUNC7_OE_SEL_V  0x00000001U
+#define GPIO_FUNC7_OE_SEL_S  10
+/** GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC7_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC7_OE_INV_SEL_M  (GPIO_FUNC7_OE_INV_SEL_V << GPIO_FUNC7_OE_INV_SEL_S)
+#define GPIO_FUNC7_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OE_INV_SEL_S  11
+
+/** GPIO_FUNC8_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO8 output
+ */
+#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4)
+/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO8.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 8 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC8_OUT_SEL    0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
+#define GPIO_FUNC8_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_S  0
+/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OUT_INV_SEL_S  9
+/** GPIO_FUNC8_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 8 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC8_OE_SEL    (BIT(10))
+#define GPIO_FUNC8_OE_SEL_M  (GPIO_FUNC8_OE_SEL_V << GPIO_FUNC8_OE_SEL_S)
+#define GPIO_FUNC8_OE_SEL_V  0x00000001U
+#define GPIO_FUNC8_OE_SEL_S  10
+/** GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC8_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC8_OE_INV_SEL_M  (GPIO_FUNC8_OE_INV_SEL_V << GPIO_FUNC8_OE_INV_SEL_S)
+#define GPIO_FUNC8_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OE_INV_SEL_S  11
+
+/** GPIO_FUNC9_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO9 output
+ */
+#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8)
+/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO9.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 9 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC9_OUT_SEL    0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
+#define GPIO_FUNC9_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_S  0
+/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OUT_INV_SEL_S  9
+/** GPIO_FUNC9_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 9 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC9_OE_SEL    (BIT(10))
+#define GPIO_FUNC9_OE_SEL_M  (GPIO_FUNC9_OE_SEL_V << GPIO_FUNC9_OE_SEL_S)
+#define GPIO_FUNC9_OE_SEL_V  0x00000001U
+#define GPIO_FUNC9_OE_SEL_S  10
+/** GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC9_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC9_OE_INV_SEL_M  (GPIO_FUNC9_OE_INV_SEL_V << GPIO_FUNC9_OE_INV_SEL_S)
+#define GPIO_FUNC9_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OE_INV_SEL_S  11
+
+/** GPIO_FUNC10_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO10 output
+ */
+#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec)
+/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO10.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 10 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC10_OUT_SEL    0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
+#define GPIO_FUNC10_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_S  0
+/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OUT_INV_SEL_S  9
+/** GPIO_FUNC10_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 10 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC10_OE_SEL    (BIT(10))
+#define GPIO_FUNC10_OE_SEL_M  (GPIO_FUNC10_OE_SEL_V << GPIO_FUNC10_OE_SEL_S)
+#define GPIO_FUNC10_OE_SEL_V  0x00000001U
+#define GPIO_FUNC10_OE_SEL_S  10
+/** GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC10_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC10_OE_INV_SEL_M  (GPIO_FUNC10_OE_INV_SEL_V << GPIO_FUNC10_OE_INV_SEL_S)
+#define GPIO_FUNC10_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OE_INV_SEL_S  11
+
+/** GPIO_FUNC11_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO11 output
+ */
+#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0)
+/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO11.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 11 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC11_OUT_SEL    0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
+#define GPIO_FUNC11_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_S  0
+/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OUT_INV_SEL_S  9
+/** GPIO_FUNC11_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 11 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC11_OE_SEL    (BIT(10))
+#define GPIO_FUNC11_OE_SEL_M  (GPIO_FUNC11_OE_SEL_V << GPIO_FUNC11_OE_SEL_S)
+#define GPIO_FUNC11_OE_SEL_V  0x00000001U
+#define GPIO_FUNC11_OE_SEL_S  10
+/** GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC11_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC11_OE_INV_SEL_M  (GPIO_FUNC11_OE_INV_SEL_V << GPIO_FUNC11_OE_INV_SEL_S)
+#define GPIO_FUNC11_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OE_INV_SEL_S  11
+
+/** GPIO_FUNC12_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO12 output
+ */
+#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4)
+/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO12.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 12 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC12_OUT_SEL    0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
+#define GPIO_FUNC12_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_S  0
+/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OUT_INV_SEL_S  9
+/** GPIO_FUNC12_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 12 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC12_OE_SEL    (BIT(10))
+#define GPIO_FUNC12_OE_SEL_M  (GPIO_FUNC12_OE_SEL_V << GPIO_FUNC12_OE_SEL_S)
+#define GPIO_FUNC12_OE_SEL_V  0x00000001U
+#define GPIO_FUNC12_OE_SEL_S  10
+/** GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC12_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC12_OE_INV_SEL_M  (GPIO_FUNC12_OE_INV_SEL_V << GPIO_FUNC12_OE_INV_SEL_S)
+#define GPIO_FUNC12_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OE_INV_SEL_S  11
+
+/** GPIO_FUNC13_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO13 output
+ */
+#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8)
+/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO13.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 13 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC13_OUT_SEL    0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
+#define GPIO_FUNC13_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_S  0
+/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OUT_INV_SEL_S  9
+/** GPIO_FUNC13_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 13 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC13_OE_SEL    (BIT(10))
+#define GPIO_FUNC13_OE_SEL_M  (GPIO_FUNC13_OE_SEL_V << GPIO_FUNC13_OE_SEL_S)
+#define GPIO_FUNC13_OE_SEL_V  0x00000001U
+#define GPIO_FUNC13_OE_SEL_S  10
+/** GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC13_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC13_OE_INV_SEL_M  (GPIO_FUNC13_OE_INV_SEL_V << GPIO_FUNC13_OE_INV_SEL_S)
+#define GPIO_FUNC13_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OE_INV_SEL_S  11
+
+/** GPIO_FUNC14_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO14 output
+ */
+#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc)
+/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO14.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 14 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC14_OUT_SEL    0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
+#define GPIO_FUNC14_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_S  0
+/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OUT_INV_SEL_S  9
+/** GPIO_FUNC14_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 14 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC14_OE_SEL    (BIT(10))
+#define GPIO_FUNC14_OE_SEL_M  (GPIO_FUNC14_OE_SEL_V << GPIO_FUNC14_OE_SEL_S)
+#define GPIO_FUNC14_OE_SEL_V  0x00000001U
+#define GPIO_FUNC14_OE_SEL_S  10
+/** GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC14_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC14_OE_INV_SEL_M  (GPIO_FUNC14_OE_INV_SEL_V << GPIO_FUNC14_OE_INV_SEL_S)
+#define GPIO_FUNC14_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OE_INV_SEL_S  11
+
+/** GPIO_FUNC15_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO15 output
+ */
+#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00)
+/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO15.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 15 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC15_OUT_SEL    0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
+#define GPIO_FUNC15_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_S  0
+/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OUT_INV_SEL_S  9
+/** GPIO_FUNC15_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 15 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC15_OE_SEL    (BIT(10))
+#define GPIO_FUNC15_OE_SEL_M  (GPIO_FUNC15_OE_SEL_V << GPIO_FUNC15_OE_SEL_S)
+#define GPIO_FUNC15_OE_SEL_V  0x00000001U
+#define GPIO_FUNC15_OE_SEL_S  10
+/** GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC15_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC15_OE_INV_SEL_M  (GPIO_FUNC15_OE_INV_SEL_V << GPIO_FUNC15_OE_INV_SEL_S)
+#define GPIO_FUNC15_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OE_INV_SEL_S  11
+
+/** GPIO_FUNC16_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO16 output
+ */
+#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04)
+/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO16.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 16 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC16_OUT_SEL    0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
+#define GPIO_FUNC16_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_S  0
+/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OUT_INV_SEL_S  9
+/** GPIO_FUNC16_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 16 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC16_OE_SEL    (BIT(10))
+#define GPIO_FUNC16_OE_SEL_M  (GPIO_FUNC16_OE_SEL_V << GPIO_FUNC16_OE_SEL_S)
+#define GPIO_FUNC16_OE_SEL_V  0x00000001U
+#define GPIO_FUNC16_OE_SEL_S  10
+/** GPIO_FUNC16_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC16_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC16_OE_INV_SEL_M  (GPIO_FUNC16_OE_INV_SEL_V << GPIO_FUNC16_OE_INV_SEL_S)
+#define GPIO_FUNC16_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OE_INV_SEL_S  11
+
+/** GPIO_FUNC17_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO17 output
+ */
+#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08)
+/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO17.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 17 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC17_OUT_SEL    0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
+#define GPIO_FUNC17_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_S  0
+/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OUT_INV_SEL_S  9
+/** GPIO_FUNC17_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 17 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC17_OE_SEL    (BIT(10))
+#define GPIO_FUNC17_OE_SEL_M  (GPIO_FUNC17_OE_SEL_V << GPIO_FUNC17_OE_SEL_S)
+#define GPIO_FUNC17_OE_SEL_V  0x00000001U
+#define GPIO_FUNC17_OE_SEL_S  10
+/** GPIO_FUNC17_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC17_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC17_OE_INV_SEL_M  (GPIO_FUNC17_OE_INV_SEL_V << GPIO_FUNC17_OE_INV_SEL_S)
+#define GPIO_FUNC17_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OE_INV_SEL_S  11
+
+/** GPIO_FUNC18_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO18 output
+ */
+#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c)
+/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO18.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 18 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC18_OUT_SEL    0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
+#define GPIO_FUNC18_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_S  0
+/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OUT_INV_SEL_S  9
+/** GPIO_FUNC18_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 18 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC18_OE_SEL    (BIT(10))
+#define GPIO_FUNC18_OE_SEL_M  (GPIO_FUNC18_OE_SEL_V << GPIO_FUNC18_OE_SEL_S)
+#define GPIO_FUNC18_OE_SEL_V  0x00000001U
+#define GPIO_FUNC18_OE_SEL_S  10
+/** GPIO_FUNC18_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC18_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC18_OE_INV_SEL_M  (GPIO_FUNC18_OE_INV_SEL_V << GPIO_FUNC18_OE_INV_SEL_S)
+#define GPIO_FUNC18_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OE_INV_SEL_S  11
+
+/** GPIO_FUNC19_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO19 output
+ */
+#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10)
+/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO19.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 19 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC19_OUT_SEL    0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
+#define GPIO_FUNC19_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_S  0
+/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OUT_INV_SEL_S  9
+/** GPIO_FUNC19_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 19 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC19_OE_SEL    (BIT(10))
+#define GPIO_FUNC19_OE_SEL_M  (GPIO_FUNC19_OE_SEL_V << GPIO_FUNC19_OE_SEL_S)
+#define GPIO_FUNC19_OE_SEL_V  0x00000001U
+#define GPIO_FUNC19_OE_SEL_S  10
+/** GPIO_FUNC19_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC19_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC19_OE_INV_SEL_M  (GPIO_FUNC19_OE_INV_SEL_V << GPIO_FUNC19_OE_INV_SEL_S)
+#define GPIO_FUNC19_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OE_INV_SEL_S  11
+
+/** GPIO_FUNC20_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO20 output
+ */
+#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14)
+/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO20.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 20 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC20_OUT_SEL    0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
+#define GPIO_FUNC20_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_S  0
+/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OUT_INV_SEL_S  9
+/** GPIO_FUNC20_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 20 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC20_OE_SEL    (BIT(10))
+#define GPIO_FUNC20_OE_SEL_M  (GPIO_FUNC20_OE_SEL_V << GPIO_FUNC20_OE_SEL_S)
+#define GPIO_FUNC20_OE_SEL_V  0x00000001U
+#define GPIO_FUNC20_OE_SEL_S  10
+/** GPIO_FUNC20_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC20_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC20_OE_INV_SEL_M  (GPIO_FUNC20_OE_INV_SEL_V << GPIO_FUNC20_OE_INV_SEL_S)
+#define GPIO_FUNC20_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OE_INV_SEL_S  11
+
+/** GPIO_FUNC21_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO21 output
+ */
+#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18)
+/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO21.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 21 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC21_OUT_SEL    0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
+#define GPIO_FUNC21_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_S  0
+/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OUT_INV_SEL_S  9
+/** GPIO_FUNC21_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 21 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC21_OE_SEL    (BIT(10))
+#define GPIO_FUNC21_OE_SEL_M  (GPIO_FUNC21_OE_SEL_V << GPIO_FUNC21_OE_SEL_S)
+#define GPIO_FUNC21_OE_SEL_V  0x00000001U
+#define GPIO_FUNC21_OE_SEL_S  10
+/** GPIO_FUNC21_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC21_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC21_OE_INV_SEL_M  (GPIO_FUNC21_OE_INV_SEL_V << GPIO_FUNC21_OE_INV_SEL_S)
+#define GPIO_FUNC21_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OE_INV_SEL_S  11
+
+/** GPIO_FUNC22_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO22 output
+ */
+#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c)
+/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO22.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC22_OUT_SEL    0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_M  (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
+#define GPIO_FUNC22_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_S  0
+/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC22_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OUT_INV_SEL_S  9
+/** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC22_OE_SEL    (BIT(10))
+#define GPIO_FUNC22_OE_SEL_M  (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S)
+#define GPIO_FUNC22_OE_SEL_V  0x00000001U
+#define GPIO_FUNC22_OE_SEL_S  10
+/** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC22_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC22_OE_INV_SEL_M  (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S)
+#define GPIO_FUNC22_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OE_INV_SEL_S  11
+
+/** GPIO_FUNC23_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO23 output
+ */
+#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20)
+/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO23.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC23_OUT_SEL    0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_M  (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
+#define GPIO_FUNC23_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_S  0
+/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC23_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OUT_INV_SEL_S  9
+/** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC23_OE_SEL    (BIT(10))
+#define GPIO_FUNC23_OE_SEL_M  (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S)
+#define GPIO_FUNC23_OE_SEL_V  0x00000001U
+#define GPIO_FUNC23_OE_SEL_S  10
+/** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC23_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC23_OE_INV_SEL_M  (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S)
+#define GPIO_FUNC23_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OE_INV_SEL_S  11
+
+/** GPIO_FUNC24_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO24 output
+ */
+#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24)
+/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO24.\\
+ *  0: Select signal 0\\
+ *  1: Select signal 1\\
+ *  ......\\
+ *  254: Select signal 254\\
+ *  255: Select signal 255\\
+ *  Or\\
+ *  256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table <a
+ *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+ *  "
+ */
+#define GPIO_FUNC24_OUT_SEL    0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_M  (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
+#define GPIO_FUNC24_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_S  0
+/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC24_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OUT_INV_SEL_S  9
+/** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.\\
+ *  0: Use output enable signal from peripheral.\\
+ *  1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\
+ */
+#define GPIO_FUNC24_OE_SEL    (BIT(10))
+#define GPIO_FUNC24_OE_SEL_M  (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S)
+#define GPIO_FUNC24_OE_SEL_V  0x00000001U
+#define GPIO_FUNC24_OE_SEL_S  10
+/** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.\\
+ *  0: Not invert\\
+ *  1: Invert\\
+ */
+#define GPIO_FUNC24_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC24_OE_INV_SEL_M  (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S)
+#define GPIO_FUNC24_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OE_INV_SEL_S  11
+
+/** GPIO_CLOCK_GATE_REG register
+ *  GPIO clock gate register
+ */
+#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0xdf8)
+/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether or not to enable clock gate.\\
+ *  0: Not enable\\
+ *  1: Enable, the clock is free running. \\
+ */
+#define GPIO_CLK_EN    (BIT(0))
+#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
+#define GPIO_CLK_EN_V  0x00000001U
+#define GPIO_CLK_EN_S  0
+
+/** GPIO_DATE_REG register
+ *  GPIO version register
+ */
+#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0xdfc)
+/** GPIO_DATE : R/W; bitpos: [27:0]; default: 37753392;
+ *  Version control register. \\
+ */
+#define GPIO_DATE    0x0FFFFFFFU
+#define GPIO_DATE_M  (GPIO_DATE_V << GPIO_DATE_S)
+#define GPIO_DATE_V  0x0FFFFFFFU
+#define GPIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/gpio_struct.h b/components/soc/esp32c61/register/soc/gpio_struct.h
new file mode 100644
index 00000000000..d37ed33d567
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/gpio_struct.h
@@ -0,0 +1,489 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of strap register
+ *  Strapping pin register
+ */
+typedef union {
+    struct {
+        /** strapping : RO; bitpos: [15:0]; default: 0;
+         *  Represents the values of GPIO strapping pins.
+         *
+         *  - bit0 ~ bit1: invalid
+         *  - bit2: GPIO8
+         *  - bit3: GPIO9
+         *  - bit4: GPIO7
+         *  - bit5 ~ bit15: invalid
+         */
+        uint32_t strapping:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_strap_reg_t;
+
+/** Type of out register
+ *  GPIO output register
+ */
+typedef union {
+    struct {
+        /** out_data_orig : R/W/SC/WTC; bitpos: [28:0]; default: 0;
+         *  Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\
+         *  0: Low level\\
+         *  1: High level\\
+         *  The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24
+         *  respectively. Bit25 ~ bit31 are invalid.\\
+         */
+        uint32_t out_data_orig:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_out_reg_t;
+
+/** Type of out_w1ts register
+ *  GPIO output set register
+ */
+typedef union {
+    struct {
+        /** out_w1ts : WT; bitpos: [28:0]; default: 0;
+         *  Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~
+         *  GPIO24.\\
+         *  0: Not set\\
+         *  1: The corresponding bit in GPIO_OUT_REG will be set to 1\\
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
+         *  Recommended operation: use this register to set GPIO_OUT_REG. \\
+         */
+        uint32_t out_w1ts:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_out_w1ts_reg_t;
+
+/** Type of out_w1tc register
+ *  GPIO output clear register
+ */
+typedef union {
+    struct {
+        /** out_w1tc : WT; bitpos: [28:0]; default: 0;
+         *  Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
+         *  GPIO24 output.\\
+         *  0: Not clear\\
+         *  1: The corresponding bit in GPIO_OUT_REG will be cleared.\\
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
+         *  Recommended operation: use this register to clear GPIO_OUT_REG. \\
+         */
+        uint32_t out_w1tc:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_out_w1tc_reg_t;
+
+/** Type of enable register
+ *  GPIO output enable register
+ */
+typedef union {
+    struct {
+        /** enable_data : R/W/WTC; bitpos: [28:0]; default: 0;
+         *  Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\
+         *  0: Not enable\\
+         *  1: Enable\\
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
+         */
+        uint32_t enable_data:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_enable_reg_t;
+
+/** Type of enable_w1ts register
+ *  GPIO output enable set register
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [28:0]; default: 0;
+         *  Configures whether or not to set the output enable register GPIO_ENABLE_REG of
+         *  GPIO0 ~ GPIO24.\\
+         *  0: Not set\\
+         *  1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
+         *  Recommended operation: use this register to set GPIO_ENABLE_REG.\\
+         */
+        uint32_t enable_w1ts:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_enable_w1ts_reg_t;
+
+/** Type of enable_w1tc register
+ *  GPIO output enable clear register
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [28:0]; default: 0;
+         *  Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
+         *  GPIO0 ~ GPIO24. \\
+         *  0: Not clear\\
+         *  1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\
+         *  Recommended operation: use this register to clear GPIO_ENABLE_REG.\\
+         */
+        uint32_t enable_w1tc:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_enable_w1tc_reg_t;
+
+/** Type of in register
+ *  GPIO input register
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [28:0]; default: 0;
+         *  Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input
+         *  value:\\
+         *  0: Low level\\
+         *  1: High level\\
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\
+         */
+        uint32_t in_data_next:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_in_reg_t;
+
+
+/** Group: Interrupt Status Registers */
+/** Type of status register
+ *  GPIO interrupt status register
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/WTC; bitpos: [28:0]; default: 0;
+         *  The interrupt status of GPIO0 ~ GPIO24, can be configured by the software.
+         *
+         *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
+         *  - Each bit represents the status of its corresponding GPIO:
+         *
+         *  - 0: Represents the GPIO does not generate the interrupt configured by
+         *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
+         *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
+         *  or this bit is configured to 1 by the software.
+         *
+         */
+        uint32_t status_interrupt:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_status_reg_t;
+
+/** Type of status_w1ts register
+ *  GPIO interrupt status set register
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [28:0]; default: 0;
+         *  Configures whether or not to set the interrupt status register
+         *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
+         *
+         *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
+         *  - If the value 1 is written to a bit here, the corresponding bit in
+         *  GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
+         *  register to set GPIO_STATUS_INTERRUPT.
+         */
+        uint32_t status_w1ts:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  GPIO interrupt status clear register
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [28:0]; default: 0;
+         *  Configures whether or not to clear the interrupt status register
+         *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24.
+         *
+         *  - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.
+         *  - If the value 1 is written to a bit here, the corresponding bit in
+         *  GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
+         *  register to clear GPIO_STATUS_INTERRUPT.
+         */
+        uint32_t status_w1tc:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_status_w1tc_reg_t;
+
+/** Type of procpu_int register
+ *  CPU interrupt status register
+ */
+typedef union {
+    struct {
+        /** procpu_int : RO; bitpos: [28:0]; default: 0;
+         *  Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\
+         *  0: Represents CPU interrupt is not enabled, or the GPIO does not generate the
+         *  interrupt configured by GPIO_PIN$n_INT_TYPE.\\
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the CPU interrupt is enabled.\\
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG). \\
+         */
+        uint32_t procpu_int:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_procpu_int_reg_t;
+
+/** Type of status_next register
+ *  GPIO interrupt source register
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [28:0]; default: 0;
+         *  Represents the interrupt source signal of GPIO0 ~ GPIO24.\\
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each
+         *  bit represents:\\
+         *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\
+         *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\
+         *  The interrupt could be rising edge interrupt, falling edge interrupt, level
+         *  sensitive interrupt and any edge interrupt.\\
+         */
+        uint32_t status_interrupt_next:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gpio_status_next_reg_t;
+
+
+/** Group: Pin Configuration Registers */
+/** Type of pinn register
+ *  GPIOn configuration register
+ */
+typedef union {
+    struct {
+        /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+         *  operating clock for the second-level synchronization.\\
+         *  0: Not synchronize\\
+         *  1: Synchronize on falling edge\\
+         *  2: Synchronize on rising edge\\
+         *  3: Synchronize on rising edge\\
+         */
+        uint32_t pinn_sync2_bypass:2;
+        /** pinn_pad_driver : R/W; bitpos: [2]; default: 0;
+         *  Configures to select pin drive mode. \\
+         *  0: Normal output\\
+         *  1: Open drain output \\
+         */
+        uint32_t pinn_pad_driver:1;
+        /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
+         *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+         *  operating clock for the first-level synchronization.\\
+         *  0: Not synchronize\\
+         *  1: Synchronize on falling edge\\
+         *  2: Synchronize on rising edge\\
+         *  3: Synchronize on rising edge\\
+         */
+        uint32_t pinn_sync1_bypass:2;
+        uint32_t reserved_5:2;
+        /** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
+         *  Configures GPIO interrupt type.\\
+         *  0: GPIO interrupt disabled\\
+         *  1: Rising edge trigger\\
+         *  2: Falling edge trigger\\
+         *  3: Any edge trigger\\
+         *  4: Low level trigger\\
+         *  5: High level trigger\\
+         */
+        uint32_t pinn_int_type:3;
+        /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable GPIO wake-up function.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         *  This function only wakes up the CPU from Light-sleep. \\
+         */
+        uint32_t pinn_wakeup_enable:1;
+        uint32_t reserved_11:2;
+        /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0;
+         *  Configures whether or not to enable CPU interrupt.
+         *
+         *  - bit13: Configures whether or not to enable CPU interrupt:\\
+         *  0: Disable\\
+         *  1: Enable\\
+         *  - bit14 ~ bit17: invalid
+         */
+        uint32_t pinn_int_ena:5;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_pinn_reg_t;
+
+
+/** Group: Input Configuration Registers */
+/** Type of func0_in_sel_cfg register
+ *  Configuration register for input signal 0
+ */
+typedef union {
+    struct {
+        /** func_in_sel : R/W; bitpos: [5:0]; default: 48;
+         *  Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\
+         *  0: Select GPIO0\\
+         *  1: Select GPIO1\\
+         *  ......\\
+         *  23: Select GPIO23\\
+         *  24: Select GPIO24\\
+         *  Or\\
+         *  0x20: A constantly high input\\
+         *  0x30: A constantly low input\\
+         */
+        uint32_t func_in_sel:6;
+        /** func_in_inv_sel : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to invert the input value.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t func_in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to route signals via GPIO matrix.\\
+         *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+         *  IO MUX.\\
+         *  1: Route signals via GPIO matrix.\\
+         */
+        uint32_t sig_in_sel:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_func_in_sel_cfg_reg_t;
+
+/** Group: Output Configuration Registers */
+/** Type of funcn_out_sel_cfg register
+ *  Configuration register for GPIOn output
+ */
+typedef union {
+    struct {
+        /** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
+         *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+         *  output from GPIOn.\\
+         *  0: Select signal 0\\
+         *  1: Select signal 1\\
+         *  ......\\
+         *  254: Select signal 254\\
+         *  255: Select signal 255\\
+         *  Or\\
+         *  256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+         *  output enable.
+         *
+         *  For the detailed signal list, see Table <a
+         *  href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
+         *  "
+         */
+        uint32_t funcn_out_sel:9;
+        /** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
+         *  Configures whether or not to invert the output value.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t funcn_out_inv_sel:1;
+        /** funcn_oe_sel : R/W; bitpos: [10]; default: 0;
+         *  Configures to select the source of output enable signal.\\
+         *  0: Use output enable signal from peripheral.\\
+         *  1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\
+         */
+        uint32_t funcn_oe_sel:1;
+        /** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert the output enable signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t funcn_oe_inv_sel:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} gpio_funcn_out_sel_cfg_reg_t;
+
+
+/** Group: Clock Gate Register */
+/** Type of clock_gate register
+ *  GPIO clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether or not to enable clock gate.\\
+         *  0: Not enable\\
+         *  1: Enable, the clock is free running. \\
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_clock_gate_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  GPIO version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37753392;
+         *  Version control register. \\
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_date_reg_t;
+
+
+typedef struct {
+    volatile gpio_strap_reg_t strap;
+    volatile gpio_out_reg_t out;
+    volatile gpio_out_w1ts_reg_t out_w1ts;
+    volatile gpio_out_w1tc_reg_t out_w1tc;
+    uint32_t reserved_010[9];
+    volatile gpio_enable_reg_t enable;
+    volatile gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile gpio_enable_w1tc_reg_t enable_w1tc;
+    uint32_t reserved_040[9];
+    volatile gpio_in_reg_t in;
+    uint32_t reserved_068[3];
+    volatile gpio_status_reg_t status;
+    volatile gpio_status_w1ts_reg_t status_w1ts;
+    volatile gpio_status_w1tc_reg_t status_w1tc;
+    uint32_t reserved_080[9];
+    volatile gpio_procpu_int_reg_t procpu_int;
+    uint32_t reserved_0a8[3];
+    volatile gpio_status_next_reg_t status_next;
+    uint32_t reserved_0b8[3];
+    volatile gpio_pinn_reg_t pinn[25];  // 0-24 are fanned out, 25-28 are not padded out. Only 0-24 are available.
+    uint32_t reserved_128[103];
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256];  //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
+    uint32_t reserved_4ac[256];
+    volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25];
+    uint32_t reserved_b28[180];
+    volatile gpio_clock_gate_reg_t clock_gate;
+    volatile gpio_date_reg_t date;
+} gpio_dev_t;
+
+extern gpio_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_dev_t) == 0xe00, "Invalid size of gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/hp_apm_reg.h b/components/soc/esp32c61/register/soc/hp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/hp_apm_reg.h
rename to components/soc/esp32c61/register/soc/hp_apm_reg.h
diff --git a/components/soc/esp32c61/include/soc/hp_apm_struct.h b/components/soc/esp32c61/register/soc/hp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/hp_apm_struct.h
rename to components/soc/esp32c61/register/soc/hp_apm_struct.h
diff --git a/components/soc/esp32c61/include/soc/hp_system_reg.h b/components/soc/esp32c61/register/soc/hp_system_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/hp_system_reg.h
rename to components/soc/esp32c61/register/soc/hp_system_reg.h
diff --git a/components/soc/esp32c61/include/soc/hp_system_struct.h b/components/soc/esp32c61/register/soc/hp_system_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/hp_system_struct.h
rename to components/soc/esp32c61/register/soc/hp_system_struct.h
diff --git a/components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/i2c_ana_mst_reg.h
rename to components/soc/esp32c61/register/soc/i2c_ana_mst_reg.h
diff --git a/components/soc/esp32c61/include/soc/i2c_reg.h b/components/soc/esp32c61/register/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/i2c_reg.h
rename to components/soc/esp32c61/register/soc/i2c_reg.h
diff --git a/components/soc/esp32c61/include/soc/i2c_struct.h b/components/soc/esp32c61/register/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/i2c_struct.h
rename to components/soc/esp32c61/register/soc/i2c_struct.h
diff --git a/components/soc/esp32c61/register/soc/i2s_reg.h b/components/soc/esp32c61/register/soc/i2s_reg.h
new file mode 100644
index 00000000000..cea489c0bc2
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/i2s_reg.h
@@ -0,0 +1,1259 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2S_INT_RAW_REG register
+ *  I2S interrupt raw register, valid in level.
+ */
+#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
+/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_RAW    (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
+#define I2S_RX_DONE_INT_RAW_V  0x00000001U
+#define I2S_RX_DONE_INT_RAW_S  0
+/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_RAW    (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
+#define I2S_TX_DONE_INT_RAW_V  0x00000001U
+#define I2S_TX_DONE_INT_RAW_S  1
+/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_RAW    (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
+#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_RX_HUNG_INT_RAW_S  2
+/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_RAW    (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
+#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_TX_HUNG_INT_RAW_S  3
+
+/** I2S_INT_ST_REG register
+ *  I2S interrupt status register.
+ */
+#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
+/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ST    (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
+#define I2S_RX_DONE_INT_ST_V  0x00000001U
+#define I2S_RX_DONE_INT_ST_S  0
+/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ST    (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
+#define I2S_TX_DONE_INT_ST_V  0x00000001U
+#define I2S_TX_DONE_INT_ST_S  1
+/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ST    (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
+#define I2S_RX_HUNG_INT_ST_V  0x00000001U
+#define I2S_RX_HUNG_INT_ST_S  2
+/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ST    (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
+#define I2S_TX_HUNG_INT_ST_V  0x00000001U
+#define I2S_TX_HUNG_INT_ST_S  3
+
+/** I2S_INT_ENA_REG register
+ *  I2S interrupt enable register.
+ */
+#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
+/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ENA    (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
+#define I2S_RX_DONE_INT_ENA_V  0x00000001U
+#define I2S_RX_DONE_INT_ENA_S  0
+/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ENA    (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
+#define I2S_TX_DONE_INT_ENA_V  0x00000001U
+#define I2S_TX_DONE_INT_ENA_S  1
+/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ENA    (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
+#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_RX_HUNG_INT_ENA_S  2
+/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ENA    (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
+#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_TX_HUNG_INT_ENA_S  3
+
+/** I2S_INT_CLR_REG register
+ *  I2S interrupt clear register.
+ */
+#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
+/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_CLR    (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
+#define I2S_RX_DONE_INT_CLR_V  0x00000001U
+#define I2S_RX_DONE_INT_CLR_S  0
+/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_CLR    (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
+#define I2S_TX_DONE_INT_CLR_V  0x00000001U
+#define I2S_TX_DONE_INT_CLR_S  1
+/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_CLR    (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
+#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_RX_HUNG_INT_CLR_S  2
+/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_CLR    (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
+#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_TX_HUNG_INT_CLR_S  3
+
+/** I2S_RX_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
+/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset receiver
+ */
+#define I2S_RX_RESET    (BIT(0))
+#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
+#define I2S_RX_RESET_V  0x00000001U
+#define I2S_RX_RESET_S  0
+/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Rx AFIFO
+ */
+#define I2S_RX_FIFO_RESET    (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
+#define I2S_RX_FIFO_RESET_V  0x00000001U
+#define I2S_RX_FIFO_RESET_S  1
+/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start receiving data
+ */
+#define I2S_RX_START    (BIT(2))
+#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
+#define I2S_RX_START_V  0x00000001U
+#define I2S_RX_START_S  2
+/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave receiver mode
+ */
+#define I2S_RX_SLAVE_MOD    (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
+#define I2S_RX_SLAVE_MOD_V  0x00000001U
+#define I2S_RX_SLAVE_MOD_S  3
+/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+ *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+ */
+#define I2S_RX_STOP_MODE    0x00000003U
+#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
+#define I2S_RX_STOP_MODE_V  0x00000003U
+#define I2S_RX_STOP_MODE_S  4
+/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable receiver  in mono mode
+ */
+#define I2S_RX_MONO    (BIT(6))
+#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
+#define I2S_RX_MONO_V  0x00000001U
+#define I2S_RX_MONO_S  6
+/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+ */
+#define I2S_RX_BIG_ENDIAN    (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
+#define I2S_RX_BIG_ENDIAN_V  0x00000001U
+#define I2S_RX_BIG_ENDIAN_S  7
+/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_RX_UPDATE    (BIT(8))
+#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
+#define I2S_RX_UPDATE_V  0x00000001U
+#define I2S_RX_UPDATE_S  8
+/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+ *  channel data value is valid in I2S RX mono mode.
+ */
+#define I2S_RX_MONO_FST_VLD    (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
+#define I2S_RX_MONO_FST_VLD_V  0x00000001U
+#define I2S_RX_MONO_FST_VLD_S  9
+/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
+ *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_RX_PCM_CONF    0x00000003U
+#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
+#define I2S_RX_PCM_CONF_V  0x00000003U
+#define I2S_RX_PCM_CONF_S  10
+/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass Compress/Decompress module for received data.
+ */
+#define I2S_RX_PCM_BYPASS    (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
+#define I2S_RX_PCM_BYPASS_V  0x00000001U
+#define I2S_RX_PCM_BYPASS_S  12
+/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable receiver in Phillips standard mode
+ */
+#define I2S_RX_MSB_SHIFT    (BIT(13))
+#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
+#define I2S_RX_MSB_SHIFT_V  0x00000001U
+#define I2S_RX_MSB_SHIFT_S  13
+/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+ */
+#define I2S_RX_LEFT_ALIGN    (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
+#define I2S_RX_LEFT_ALIGN_V  0x00000001U
+#define I2S_RX_LEFT_ALIGN_S  15
+/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+ */
+#define I2S_RX_24_FILL_EN    (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
+#define I2S_RX_24_FILL_EN_V  0x00000001U
+#define I2S_RX_24_FILL_EN_S  16
+/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+ *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+ */
+#define I2S_RX_WS_IDLE_POL    (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
+#define I2S_RX_WS_IDLE_POL_V  0x00000001U
+#define I2S_RX_WS_IDLE_POL_S  17
+/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+ *  is received first.
+ */
+#define I2S_RX_BIT_ORDER    (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
+#define I2S_RX_BIT_ORDER_V  0x00000001U
+#define I2S_RX_BIT_ORDER_S  18
+/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_TDM_EN    (BIT(19))
+#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
+#define I2S_RX_TDM_EN_V  0x00000001U
+#define I2S_RX_TDM_EN_S  19
+/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_PDM_EN    (BIT(20))
+#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
+#define I2S_RX_PDM_EN_V  0x00000001U
+#define I2S_RX_PDM_EN_S  20
+/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in receiver mode.
+ */
+#define I2S_RX_BCK_DIV_NUM    0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
+#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_S  21
+
+/** I2S_TX_CONF_REG register
+ *  I2S TX configure register
+ */
+#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
+/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset transmitter
+ */
+#define I2S_TX_RESET    (BIT(0))
+#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
+#define I2S_TX_RESET_V  0x00000001U
+#define I2S_TX_RESET_S  0
+/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Tx AFIFO
+ */
+#define I2S_TX_FIFO_RESET    (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
+#define I2S_TX_FIFO_RESET_V  0x00000001U
+#define I2S_TX_FIFO_RESET_S  1
+/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start transmitting data
+ */
+#define I2S_TX_START    (BIT(2))
+#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
+#define I2S_TX_START_V  0x00000001U
+#define I2S_TX_START_S  2
+/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave transmitter mode
+ */
+#define I2S_TX_SLAVE_MOD    (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
+#define I2S_TX_SLAVE_MOD_V  0x00000001U
+#define I2S_TX_SLAVE_MOD_S  3
+/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+ */
+#define I2S_TX_STOP_EN    (BIT(4))
+#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
+#define I2S_TX_STOP_EN_V  0x00000001U
+#define I2S_TX_STOP_EN_S  4
+/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
+ *  1: The value of Left channel data is equal to the value of right channel data in
+ *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+ *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+ */
+#define I2S_TX_CHAN_EQUAL    (BIT(5))
+#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
+#define I2S_TX_CHAN_EQUAL_V  0x00000001U
+#define I2S_TX_CHAN_EQUAL_S  5
+/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter in mono mode
+ */
+#define I2S_TX_MONO    (BIT(6))
+#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
+#define I2S_TX_MONO_V  0x00000001U
+#define I2S_TX_MONO_S  6
+/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+ *  value.
+ */
+#define I2S_TX_BIG_ENDIAN    (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
+#define I2S_TX_BIG_ENDIAN_V  0x00000001U
+#define I2S_TX_BIG_ENDIAN_S  7
+/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_TX_UPDATE    (BIT(8))
+#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
+#define I2S_TX_UPDATE_V  0x00000001U
+#define I2S_TX_UPDATE_S  8
+/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+ *  channel data value is valid in I2S TX mono mode.
+ */
+#define I2S_TX_MONO_FST_VLD    (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
+#define I2S_TX_MONO_FST_VLD_V  0x00000001U
+#define I2S_TX_MONO_FST_VLD_S  9
+/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
+ *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_TX_PCM_CONF    0x00000003U
+#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
+#define I2S_TX_PCM_CONF_V  0x00000003U
+#define I2S_TX_PCM_CONF_S  10
+/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+ */
+#define I2S_TX_PCM_BYPASS    (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
+#define I2S_TX_PCM_BYPASS_V  0x00000001U
+#define I2S_TX_PCM_BYPASS_S  12
+/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable transmitter in Phillips standard mode
+ */
+#define I2S_TX_MSB_SHIFT    (BIT(13))
+#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
+#define I2S_TX_MSB_SHIFT_V  0x00000001U
+#define I2S_TX_MSB_SHIFT_S  13
+/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
+ *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+ *  generate pos/neg edge in master mode.
+ */
+#define I2S_TX_BCK_NO_DLY    (BIT(14))
+#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
+#define I2S_TX_BCK_NO_DLY_V  0x00000001U
+#define I2S_TX_BCK_NO_DLY_S  14
+/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+ */
+#define I2S_TX_LEFT_ALIGN    (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
+#define I2S_TX_LEFT_ALIGN_V  0x00000001U
+#define I2S_TX_LEFT_ALIGN_S  15
+/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+ */
+#define I2S_TX_24_FILL_EN    (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
+#define I2S_TX_24_FILL_EN_V  0x00000001U
+#define I2S_TX_24_FILL_EN_S  16
+/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+ *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+ */
+#define I2S_TX_WS_IDLE_POL    (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
+#define I2S_TX_WS_IDLE_POL_V  0x00000001U
+#define I2S_TX_WS_IDLE_POL_S  17
+/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+ *  sent first.
+ */
+#define I2S_TX_BIT_ORDER    (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
+#define I2S_TX_BIT_ORDER_V  0x00000001U
+#define I2S_TX_BIT_ORDER_S  18
+/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_TDM_EN    (BIT(19))
+#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
+#define I2S_TX_TDM_EN_V  0x00000001U
+#define I2S_TX_TDM_EN_S  19
+/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_PDM_EN    (BIT(20))
+#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
+#define I2S_TX_PDM_EN_V  0x00000001U
+#define I2S_TX_PDM_EN_S  20
+/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in transmitter mode.
+ */
+#define I2S_TX_BCK_DIV_NUM    0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
+#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_S  21
+/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
+ *  I2S transmitter channel mode configuration bits.
+ */
+#define I2S_TX_CHAN_MOD    0x00000007U
+#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
+#define I2S_TX_CHAN_MOD_V  0x00000007U
+#define I2S_TX_CHAN_MOD_S  27
+/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
+ *  Enable signal loop back mode with transmitter module and receiver module sharing
+ *  the same WS and BCK signals.
+ */
+#define I2S_SIG_LOOPBACK    (BIT(30))
+#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
+#define I2S_SIG_LOOPBACK_V  0x00000001U
+#define I2S_SIG_LOOPBACK_S  30
+
+/** I2S_RX_CONF1_REG register
+ *  I2S RX configure register 1
+ */
+#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
+/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
+#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_S  0
+/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+ *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_RX_BITS_MOD    0x0000001FU
+#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
+#define I2S_RX_BITS_MOD_V  0x0000001FU
+#define I2S_RX_BITS_MOD_S  14
+/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Rx half sample bits -1.
+ */
+#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_S  19
+/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Rx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
+#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_CONF1_REG register
+ *  I2S TX configure register 1
+ */
+#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
+/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
+#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_S  0
+/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+ *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_TX_BITS_MOD    0x0000001FU
+#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
+#define I2S_TX_BITS_MOD_V  0x0000001FU
+#define I2S_TX_BITS_MOD_S  14
+/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Tx half sample bits -1.
+ */
+#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_S  19
+/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Tx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
+#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_PCM2PDM_CONF_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40)
+/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0;
+ *  I2S TX PDM bypass hp filter or not. The option has been removed.
+ */
+#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_M  (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S)
+#define I2S_TX_PDM_HP_BYPASS_V  0x00000001U
+#define I2S_TX_PDM_HP_BYPASS_S  0
+/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
+ *  I2S TX PDM OSR2 value
+ */
+#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
+#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
+ *  I2S TX PDM prescale for sigmadelta
+ */
+#define I2S_TX_PDM_PRESCALE    0x000000FFU
+#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
+#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
+#define I2S_TX_PDM_PRESCALE_S  5
+/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
+ *  I2S TX PDM sigmadelta dither2 value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
+ *  I2S TX PDM sigmadelta dither value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
+ *  I2S TX PDM dac mode enable
+ */
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
+ *  I2S TX PDM dac 2channel enable
+ */
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
+ *  I2S TX PDM Converter enable
+ */
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
+#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
+#define I2S_PCM2PDM_CONV_EN_S  25
+
+/** I2S_TX_PCM2PDM_CONF1_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44)
+/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
+ *  I2S TX PDM Fp
+ */
+#define I2S_TX_PDM_FP    0x000003FFU
+#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
+#define I2S_TX_PDM_FP_V  0x000003FFU
+#define I2S_TX_PDM_FP_S  0
+/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
+ *  I2S TX PDM Fs
+ */
+#define I2S_TX_PDM_FS    0x000003FFU
+#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
+#define I2S_TX_PDM_FS_V  0x000003FFU
+#define I2S_TX_PDM_FS_S  10
+/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
+#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
+#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+
+/** I2S_RX_PDM2PCM_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x48)
+/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable PDM2PCM RX mode. 0: DIsable.
+ */
+#define I2S_RX_PDM2PCM_EN    (BIT(19))
+#define I2S_RX_PDM2PCM_EN_M  (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
+#define I2S_RX_PDM2PCM_EN_V  0x00000001U
+#define I2S_RX_PDM2PCM_EN_S  19
+/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
+ *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+ *  sampling rate is 128. 0: down sampling rate is 64.
+ */
+#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
+#define I2S_RX_PDM_SINC_DSR_16_EN_M  (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
+#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
+#define I2S_RX_PDM_SINC_DSR_16_EN_S  20
+/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
+ *  Configure PDM RX amplify number.
+ */
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
+/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
+ *  I2S PDM RX bypass hp filter or not.
+ */
+#define I2S_RX_PDM_HP_BYPASS    (BIT(25))
+#define I2S_RX_PDM_HP_BYPASS_M  (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
+#define I2S_RX_PDM_HP_BYPASS_V  0x00000001U
+#define I2S_RX_PDM_HP_BYPASS_S  25
+
+/** I2S_RX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
+/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
+#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
+#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
+#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
+#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
+#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
+#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
+#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
+#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+
+/** I2S_TX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
+/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
+#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN0_EN_S  0
+/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
+#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
+#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
+#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
+#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
+#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
+#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
+#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
+#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
+#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
+#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
+#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
+#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
+#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
+#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
+#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
+ *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+ *  only the data of the enabled channels is sent, then this bit should be set. Clear
+ *  it when all the data stored in DMA TX buffer is for enabled channels.
+ */
+#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+
+/** I2S_RX_TIMING_REG register
+ *  I2S RX timing control register
+ */
+#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
+/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD_IN_DM    0x00000003U
+#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
+#define I2S_RX_SD_IN_DM_V  0x00000003U
+#define I2S_RX_SD_IN_DM_S  0
+/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD1_IN_DM    0x00000003U
+#define I2S_RX_SD1_IN_DM_M  (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S)
+#define I2S_RX_SD1_IN_DM_V  0x00000003U
+#define I2S_RX_SD1_IN_DM_S  4
+/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0;
+ *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD2_IN_DM    0x00000003U
+#define I2S_RX_SD2_IN_DM_M  (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S)
+#define I2S_RX_SD2_IN_DM_V  0x00000003U
+#define I2S_RX_SD2_IN_DM_S  8
+/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0;
+ *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD3_IN_DM    0x00000003U
+#define I2S_RX_SD3_IN_DM_M  (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S)
+#define I2S_RX_SD3_IN_DM_V  0x00000003U
+#define I2S_RX_SD3_IN_DM_S  12
+/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_OUT_DM    0x00000003U
+#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
+#define I2S_RX_WS_OUT_DM_V  0x00000003U
+#define I2S_RX_WS_OUT_DM_S  16
+/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_OUT_DM    0x00000003U
+#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
+#define I2S_RX_BCK_OUT_DM_V  0x00000003U
+#define I2S_RX_BCK_OUT_DM_S  20
+/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_IN_DM    0x00000003U
+#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
+#define I2S_RX_WS_IN_DM_V  0x00000003U
+#define I2S_RX_WS_IN_DM_S  24
+/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_IN_DM    0x00000003U
+#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
+#define I2S_RX_BCK_IN_DM_V  0x00000003U
+#define I2S_RX_BCK_IN_DM_S  28
+
+/** I2S_TX_TIMING_REG register
+ *  I2S TX timing control register
+ */
+#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
+/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD_OUT_DM    0x00000003U
+#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
+#define I2S_TX_SD_OUT_DM_V  0x00000003U
+#define I2S_TX_SD_OUT_DM_S  0
+/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD1_OUT_DM    0x00000003U
+#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
+#define I2S_TX_SD1_OUT_DM_V  0x00000003U
+#define I2S_TX_SD1_OUT_DM_S  4
+/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_OUT_DM    0x00000003U
+#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
+#define I2S_TX_WS_OUT_DM_V  0x00000003U
+#define I2S_TX_WS_OUT_DM_S  16
+/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_OUT_DM    0x00000003U
+#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
+#define I2S_TX_BCK_OUT_DM_V  0x00000003U
+#define I2S_TX_BCK_OUT_DM_S  20
+/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_IN_DM    0x00000003U
+#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
+#define I2S_TX_WS_IN_DM_V  0x00000003U
+#define I2S_TX_WS_IN_DM_S  24
+/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_IN_DM    0x00000003U
+#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
+#define I2S_TX_BCK_IN_DM_V  0x00000003U
+#define I2S_TX_BCK_IN_DM_S  28
+
+/** I2S_LC_HUNG_CONF_REG register
+ *  I2S HUNG configure register.
+ */
+#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
+/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ *  when fifo hung counter is equal to this value
+ */
+#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
+#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_S  0
+/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  The bits are used to scale tick counter threshold. The tick counter is reset when
+ *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+ */
+#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  The enable bit for FIFO timeout
+ */
+#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+
+/** I2S_RXEOF_NUM_REG register
+ *  I2S RX data number control register.
+ */
+#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
+/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
+ *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+ *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+ */
+#define I2S_RX_EOF_NUM    0x00000FFFU
+#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
+#define I2S_RX_EOF_NUM_V  0x00000FFFU
+#define I2S_RX_EOF_NUM_S  0
+
+/** I2S_CONF_SIGLE_DATA_REG register
+ *  I2S signal data register
+ */
+#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
+/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The configured constant channel data to be sent out.
+ */
+#define I2S_SINGLE_DATA    0xFFFFFFFFU
+#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
+#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
+#define I2S_SINGLE_DATA_S  0
+
+/** I2S_STATE_REG register
+ *  I2S TX status register
+ */
+#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
+/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
+ *  1: i2s_tx is idle state. 0: i2s_tx is working.
+ */
+#define I2S_TX_IDLE    (BIT(0))
+#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
+#define I2S_TX_IDLE_V  0x00000001U
+#define I2S_TX_IDLE_S  0
+
+/** I2S_ETM_CONF_REG register
+ *  I2S ETM configure register
+ */
+#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
+/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
+ *  I2S ETM send x words event. When sending word number of
+ *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
+#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_S  0
+/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
+ *  I2S ETM receive x words event. When receiving word number of
+ *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
+
+/** I2S_FIFO_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x74)
+/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx fifo counter value.
+ */
+#define I2S_TX_FIFO_CNT    0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_M  (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S)
+#define I2S_TX_FIFO_CNT_V  0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_S  0
+/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx fifo counter.
+ */
+#define I2S_TX_FIFO_CNT_RST    (BIT(31))
+#define I2S_TX_FIFO_CNT_RST_M  (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S)
+#define I2S_TX_FIFO_CNT_RST_V  0x00000001U
+#define I2S_TX_FIFO_CNT_RST_S  31
+
+/** I2S_BCK_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x78)
+/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx bck counter value.
+ */
+#define I2S_TX_BCK_CNT    0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_M  (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S)
+#define I2S_TX_BCK_CNT_V  0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_S  0
+/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx bck counter.
+ */
+#define I2S_TX_BCK_CNT_RST    (BIT(31))
+#define I2S_TX_BCK_CNT_RST_M  (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S)
+#define I2S_TX_BCK_CNT_RST_V  0x00000001U
+#define I2S_TX_BCK_CNT_RST_S  31
+
+/** I2S_CLK_GATE_REG register
+ *  Clock gate register
+ */
+#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0x7c)
+/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit to enable clock gate
+ */
+#define I2S_CLK_EN    (BIT(0))
+#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
+#define I2S_CLK_EN_V  0x00000001U
+#define I2S_CLK_EN_S  0
+
+/** I2S_DATE_REG register
+ *  Version control register
+ */
+#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80)
+/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024;
+ *  I2S version control register
+ */
+#define I2S_DATE    0x0FFFFFFFU
+#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
+#define I2S_DATE_V  0x0FFFFFFFU
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/i2s_struct.h b/components/soc/esp32c61/register/soc/i2s_struct.h
new file mode 100644
index 00000000000..e9afdbf28b7
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/i2s_struct.h
@@ -0,0 +1,1001 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_14:1;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t rx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:8;
+        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of rx_pdm2pcm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_rx_pdm2pcm_conf_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rxeof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_rxeof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [30]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t tx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:8;
+        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
+         *  I2S TX PDM bypass hp filter or not. The option has been removed.
+         */
+        uint32_t tx_pdm_hp_bypass:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:2;
+        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd1_in_dm:2;
+        uint32_t reserved_6:2;
+        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
+         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd2_in_dm:2;
+        uint32_t reserved_10:2;
+        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
+         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd3_in_dm:2;
+        uint32_t reserved_14:2;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_sigle_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_single_data_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:10;
+        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: Sync counter registers */
+/** Type of fifo_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx fifo counter value.
+         */
+        uint32_t tx_fifo_cnt:31;
+        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx fifo counter.
+         */
+        uint32_t tx_fifo_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_fifo_cnt_reg_t;
+
+/** Type of bck_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx bck counter value.
+         */
+        uint32_t tx_bck_cnt:31;
+        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx bck counter.
+         */
+        uint32_t tx_bck_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_bck_cnt_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36713024;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    uint32_t reserved_030[4];
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
+    uint32_t reserved_04c;
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rxeof_num_reg_t rx_eof_num;
+    volatile i2s_conf_single_data_reg_t conf_single_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    volatile i2s_fifo_cnt_reg_t fifo_cnt;
+    volatile i2s_bck_cnt_reg_t bck_cnt;
+    volatile i2s_clk_gate_reg_t clk_gate;
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+extern i2s_dev_t I2S0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/interrupt_matrix_reg.h b/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/interrupt_matrix_reg.h
rename to components/soc/esp32c61/register/soc/interrupt_matrix_reg.h
diff --git a/components/soc/esp32c61/include/soc/interrupt_matrix_struct.h b/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/interrupt_matrix_struct.h
rename to components/soc/esp32c61/register/soc/interrupt_matrix_struct.h
diff --git a/components/soc/esp32c61/include/soc/intpri_reg.h b/components/soc/esp32c61/register/soc/intpri_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/intpri_reg.h
rename to components/soc/esp32c61/register/soc/intpri_reg.h
diff --git a/components/soc/esp32c61/include/soc/intpri_struct.h b/components/soc/esp32c61/register/soc/intpri_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/intpri_struct.h
rename to components/soc/esp32c61/register/soc/intpri_struct.h
diff --git a/components/soc/esp32c61/register/soc/io_mux_reg.h b/components/soc/esp32c61/register/soc/io_mux_reg.h
new file mode 100644
index 00000000000..78c9face386
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/io_mux_reg.h
@@ -0,0 +1,264 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+
+#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
+#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
+#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_PAD_GPIO2
+#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_PAD_MTMS
+#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_PAD_MTDI
+#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_PAD_MTCK
+#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_PAD_MTDO
+#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_PAD_GPIO7
+#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_PAD_GPIO8
+#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_PAD_GPIO9
+#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_PAD_U0RXD
+#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_PAD_U0TXD
+#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_PAD_GPIO12
+#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_PAD_GPIO13
+#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_PAD_SPICS1
+#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_PAD_SPICS0
+#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_PAD_SPIQ
+#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_PAD_SPIWP
+#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_PAD_VDD_SPI
+#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_PAD_SPIHD
+#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_PAD_SPICLK
+#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_PAD_SPID
+#define IO_MUX_GPIO22_REG                   PERIPHS_IO_MUX_U_PAD_GPIO22
+#define IO_MUX_GPIO23_REG                   PERIPHS_IO_MUX_U_PAD_GPIO23
+#define IO_MUX_GPIO24_REG                   PERIPHS_IO_MUX_U_PAD_GPIO24
+
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define USB_INT_PHY0_DM_GPIO_NUM     12
+#define USB_INT_PHY0_DP_GPIO_NUM     13
+
+#define EXT_OSC_SLOW_GPIO_NUM        0
+
+#define MAX_RTC_GPIO_NUM              6
+#define MAX_PAD_GPIO_NUM             24
+#define MAX_GPIO_NUM                 28
+#define HIGH_IO_HOLD_BIT_SHIFT       32
+
+#define REG_IO_MUX_BASE                             DR_REG_IO_MUX_BASE
+// definitions above are inherited from previous version of code, should double check
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P            (REG_IO_MUX_BASE + 0x0)
+#define FUNC_XTAL_32K_P_GPIO0                                            1
+#define FUNC_XTAL_32K_P_GPIO0_0                                          0
+
+#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N            (REG_IO_MUX_BASE + 0x4)
+#define FUNC_XTAL_32K_N_GPIO1                                            1
+#define FUNC_XTAL_32K_N_GPIO1_0                                          0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO2                 (REG_IO_MUX_BASE + 0x8)
+#define FUNC_GPIO2_FSPIQ                                                 2
+#define FUNC_GPIO2_GPIO2                                                 1
+#define FUNC_GPIO2_GPIO2_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_MTMS                  (REG_IO_MUX_BASE + 0xC)
+#define FUNC_MTMS_FSPIHD                                                 2
+#define FUNC_MTMS_GPIO3                                                  1
+#define FUNC_MTMS_MTMS                                                   0
+
+#define PERIPHS_IO_MUX_U_PAD_MTDI                 (REG_IO_MUX_BASE + 0x10)
+#define FUNC_MTDI_FSPIWP                                                 2
+#define FUNC_MTDI_GPIO4                                                  1
+#define FUNC_MTDI_MTDI                                                   0
+
+#define PERIPHS_IO_MUX_U_PAD_MTCK                 (REG_IO_MUX_BASE + 0x14)
+#define FUNC_MTCK_GPIO5                                                  1
+#define FUNC_MTCK_MTCK                                                   0
+
+#define PERIPHS_IO_MUX_U_PAD_MTDO                 (REG_IO_MUX_BASE + 0x18)
+#define FUNC_MTDO_FSPICLK                                                2
+#define FUNC_MTDO_GPIO6                                                  1
+#define FUNC_MTDO_MTDO                                                   0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO7                (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_GPIO7_FSPID                                                 2
+#define FUNC_GPIO7_GPIO7                                                 1
+#define FUNC_GPIO7_GPIO7_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO8                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_GPIO8_FSPICS0                                               2
+#define FUNC_GPIO8_GPIO8                                                 1
+#define FUNC_GPIO8_GPIO8_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO9                (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO9_GPIO9                                                 1
+#define FUNC_GPIO9_GPIO9_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_U0RXD                (REG_IO_MUX_BASE + 0x28)
+#define FUNC_U0RXD_GPIO10                                                1
+#define FUNC_U0RXD_U0RXD                                                 0
+
+#define PERIPHS_IO_MUX_U_PAD_U0TXD                (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_U0TXD_GPIO11                                                1
+#define FUNC_U0TXD_U0TXD                                                 0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO12               (REG_IO_MUX_BASE + 0x30)
+#define FUNC_GPIO12_GPIO12                                               1
+#define FUNC_GPIO12_GPIO12_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO13               (REG_IO_MUX_BASE + 0x34)
+#define FUNC_GPIO13_GPIO13                                               1
+#define FUNC_GPIO13_GPIO13_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_SPICS1               (REG_IO_MUX_BASE + 0x38)
+#define FUNC_SPICS1_GPIO14                                               1
+#define FUNC_SPICS1_SPICS1                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_SPICS0               (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_SPICS0_GPIO15                                               1
+#define FUNC_SPICS0_SPICS0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_SPIQ                 (REG_IO_MUX_BASE + 0x40)
+#define FUNC_SPIQ_GPIO16                                                 1
+#define FUNC_SPIQ_SPIQ                                                   0
+
+#define PERIPHS_IO_MUX_U_PAD_SPIWP                (REG_IO_MUX_BASE + 0x44)
+#define FUNC_SPIWP_GPIO17                                                1
+#define FUNC_SPIWP_SPIWP                                                 0
+
+#define PERIPHS_IO_MUX_U_PAD_VDD_SPI              (REG_IO_MUX_BASE + 0x48)
+#define FUNC_VDD_SPI_GPIO18                                              1
+#define FUNC_VDD_SPI_GPIO18_0                                            0
+
+#define PERIPHS_IO_MUX_U_PAD_SPIHD                (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_SPIHD_GPIO19                                                1
+#define FUNC_SPIHD_SPIHD                                                 0
+
+#define PERIPHS_IO_MUX_U_PAD_SPICLK               (REG_IO_MUX_BASE + 0x50)
+#define FUNC_SPICLK_GPIO20                                               1
+#define FUNC_SPICLK_SPICLK                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_SPID                 (REG_IO_MUX_BASE + 0x54)
+#define FUNC_SPID_GPIO21                                                 1
+#define FUNC_SPID_SPID                                                   0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO22               (REG_IO_MUX_BASE + 0x58)
+#define FUNC_GPIO22_GPIO22                                               1
+#define FUNC_GPIO22_GPIO22_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO23               (REG_IO_MUX_BASE + 0x5C)
+#define FUNC_GPIO23_GPIO23                                               1
+#define FUNC_GPIO23_GPIO23_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO24               (REG_IO_MUX_BASE + 0x60)
+#define FUNC_GPIO24_GPIO24                                               1
+#define FUNC_GPIO24_GPIO24_0                                             0
+
+/** IO_MUX_DATE_REG register
+ *  Version control register
+ */
+#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x1fc)
+/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36774288;
+ *  Version control register
+ */
+#define IO_MUX_REG_DATE    0x0FFFFFFFU
+#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
+#define IO_MUX_REG_DATE_V  0x0FFFFFFFU
+#define IO_MUX_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/io_mux_struct.h b/components/soc/esp32c61/register/soc/io_mux_struct.h
similarity index 98%
rename from components/soc/esp32c61/include/soc/io_mux_struct.h
rename to components/soc/esp32c61/register/soc/io_mux_struct.h
index 3f2fec54529..b4091d4d987 100644
--- a/components/soc/esp32c61/include/soc/io_mux_struct.h
+++ b/components/soc/esp32c61/register/soc/io_mux_struct.h
@@ -129,8 +129,8 @@ typedef union {
 
 
 typedef struct {
-    volatile io_mux_gpion_reg_t gpion[22];
-    uint32_t reserved_058[105];
+    volatile io_mux_gpion_reg_t gpion[25];
+    uint32_t reserved_064[102];
     volatile io_mux_date_reg_t date;
 } io_mux_dev_t;
 
diff --git a/components/soc/esp32c61/include/soc/ledc_reg.h b/components/soc/esp32c61/register/soc/ledc_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/ledc_reg.h
rename to components/soc/esp32c61/register/soc/ledc_reg.h
diff --git a/components/soc/esp32c61/include/soc/ledc_struct.h b/components/soc/esp32c61/register/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/ledc_struct.h
rename to components/soc/esp32c61/register/soc/ledc_struct.h
diff --git a/components/soc/esp32c61/register/soc/lp_analog_peri_reg.h b/components/soc/esp32c61/register/soc/lp_analog_peri_reg.h
new file mode 100644
index 00000000000..d7398ecbda4
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/lp_analog_peri_reg.h
@@ -0,0 +1,233 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_ANA_BOD_MODE0_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
+/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA    (BIT(6))
+#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M  (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
+#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S  6
+/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_PD_RF_ENA    (BIT(7))
+#define LP_ANA_BOD_MODE0_PD_RF_ENA_M  (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
+#define LP_ANA_BOD_MODE0_PD_RF_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_PD_RF_ENA_S  7
+/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_INTR_WAIT    0x000003FFU
+#define LP_ANA_BOD_MODE0_INTR_WAIT_M  (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
+#define LP_ANA_BOD_MODE0_INTR_WAIT_V  0x000003FFU
+#define LP_ANA_BOD_MODE0_INTR_WAIT_S  8
+/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_RESET_WAIT    0x000003FFU
+#define LP_ANA_BOD_MODE0_RESET_WAIT_M  (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
+#define LP_ANA_BOD_MODE0_RESET_WAIT_V  0x000003FFU
+#define LP_ANA_BOD_MODE0_RESET_WAIT_S  18
+/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_CNT_CLR    (BIT(28))
+#define LP_ANA_BOD_MODE0_CNT_CLR_M  (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
+#define LP_ANA_BOD_MODE0_CNT_CLR_V  0x00000001U
+#define LP_ANA_BOD_MODE0_CNT_CLR_S  28
+/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_INTR_ENA    (BIT(29))
+#define LP_ANA_BOD_MODE0_INTR_ENA_M  (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
+#define LP_ANA_BOD_MODE0_INTR_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INTR_ENA_S  29
+/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_RESET_SEL    (BIT(30))
+#define LP_ANA_BOD_MODE0_RESET_SEL_M  (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
+#define LP_ANA_BOD_MODE0_RESET_SEL_V  0x00000001U
+#define LP_ANA_BOD_MODE0_RESET_SEL_S  30
+/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_RESET_ENA    (BIT(31))
+#define LP_ANA_BOD_MODE0_RESET_ENA_M  (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
+#define LP_ANA_BOD_MODE0_RESET_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_RESET_ENA_S  31
+
+/** LP_ANA_BOD_MODE1_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
+/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE1_RESET_ENA    (BIT(31))
+#define LP_ANA_BOD_MODE1_RESET_ENA_M  (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
+#define LP_ANA_BOD_MODE1_RESET_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE1_RESET_ENA_S  31
+
+/** LP_ANA_POWER_GLITCH_CNTL_REG register
+ *  need_des
+ */
+#define LP_ANA_POWER_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
+/** LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31:28]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_POWER_GLITCH_RESET_ENA    0x0000000FU
+#define LP_ANA_POWER_GLITCH_RESET_ENA_M  (LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANA_POWER_GLITCH_RESET_ENA_S)
+#define LP_ANA_POWER_GLITCH_RESET_ENA_V  0x0000000FU
+#define LP_ANA_POWER_GLITCH_RESET_ENA_S  28
+
+/** LP_ANA_FIB_ENABLE_REG register
+ *  need_des
+ */
+#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
+/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
+ *  need_des
+ */
+#define LP_ANA_ANA_FIB_ENA    0xFFFFFFFFU
+#define LP_ANA_ANA_FIB_ENA_M  (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
+#define LP_ANA_ANA_FIB_ENA_V  0xFFFFFFFFU
+#define LP_ANA_ANA_FIB_ENA_S  0
+
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA    0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M  (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S)
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V  0x0000000FU
+#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S  2
+
+/** LP_ANA_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
+/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_INT_RAW    (BIT(31))
+#define LP_ANA_BOD_MODE0_INT_RAW_M  (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
+#define LP_ANA_BOD_MODE0_INT_RAW_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INT_RAW_S  31
+
+/** LP_ANA_INT_ST_REG register
+ *  need_des
+ */
+#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
+/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_INT_ST    (BIT(31))
+#define LP_ANA_BOD_MODE0_INT_ST_M  (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
+#define LP_ANA_BOD_MODE0_INT_ST_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INT_ST_S  31
+
+/** LP_ANA_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
+/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_INT_ENA    (BIT(31))
+#define LP_ANA_BOD_MODE0_INT_ENA_M  (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
+#define LP_ANA_BOD_MODE0_INT_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INT_ENA_S  31
+
+/** LP_ANA_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
+/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_INT_CLR    (BIT(31))
+#define LP_ANA_BOD_MODE0_INT_CLR_M  (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
+#define LP_ANA_BOD_MODE0_INT_CLR_V  0x00000001U
+#define LP_ANA_BOD_MODE0_INT_CLR_S  31
+
+/** LP_ANA_LP_INT_RAW_REG register
+ *  need_des
+ */
+#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
+/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_LP_INT_RAW    (BIT(31))
+#define LP_ANA_BOD_MODE0_LP_INT_RAW_M  (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
+#define LP_ANA_BOD_MODE0_LP_INT_RAW_V  0x00000001U
+#define LP_ANA_BOD_MODE0_LP_INT_RAW_S  31
+
+/** LP_ANA_LP_INT_ST_REG register
+ *  need_des
+ */
+#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
+/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_LP_INT_ST    (BIT(31))
+#define LP_ANA_BOD_MODE0_LP_INT_ST_M  (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
+#define LP_ANA_BOD_MODE0_LP_INT_ST_V  0x00000001U
+#define LP_ANA_BOD_MODE0_LP_INT_ST_S  31
+
+/** LP_ANA_LP_INT_ENA_REG register
+ *  need_des
+ */
+#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
+/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_LP_INT_ENA    (BIT(31))
+#define LP_ANA_BOD_MODE0_LP_INT_ENA_M  (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
+#define LP_ANA_BOD_MODE0_LP_INT_ENA_V  0x00000001U
+#define LP_ANA_BOD_MODE0_LP_INT_ENA_S  31
+
+/** LP_ANA_LP_INT_CLR_REG register
+ *  need_des
+ */
+#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
+/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_BOD_MODE0_LP_INT_CLR    (BIT(31))
+#define LP_ANA_BOD_MODE0_LP_INT_CLR_M  (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
+#define LP_ANA_BOD_MODE0_LP_INT_CLR_V  0x00000001U
+#define LP_ANA_BOD_MODE0_LP_INT_CLR_S  31
+
+/** LP_ANA_DATE_REG register
+ *  need_des
+ */
+#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
+/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 37752896;
+ *  need_des
+ */
+#define LP_ANA_LP_ANA_DATE    0x7FFFFFFFU
+#define LP_ANA_LP_ANA_DATE_M  (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
+#define LP_ANA_LP_ANA_DATE_V  0x7FFFFFFFU
+#define LP_ANA_LP_ANA_DATE_S  0
+/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_ANA_CLK_EN    (BIT(31))
+#define LP_ANA_CLK_EN_M  (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
+#define LP_ANA_CLK_EN_V  0x00000001U
+#define LP_ANA_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/lp_analog_peri_struct.h b/components/soc/esp32c61/register/soc/lp_analog_peri_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_analog_peri_struct.h
rename to components/soc/esp32c61/register/soc/lp_analog_peri_struct.h
diff --git a/components/soc/esp32c61/include/soc/lp_aon_reg.h b/components/soc/esp32c61/register/soc/lp_aon_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_aon_reg.h
rename to components/soc/esp32c61/register/soc/lp_aon_reg.h
diff --git a/components/soc/esp32c61/include/soc/lp_aon_struct.h b/components/soc/esp32c61/register/soc/lp_aon_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_aon_struct.h
rename to components/soc/esp32c61/register/soc/lp_aon_struct.h
diff --git a/components/soc/esp32c61/include/soc/lp_apm_reg.h b/components/soc/esp32c61/register/soc/lp_apm_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_apm_reg.h
rename to components/soc/esp32c61/register/soc/lp_apm_reg.h
diff --git a/components/soc/esp32c61/include/soc/lp_apm_struct.h b/components/soc/esp32c61/register/soc/lp_apm_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_apm_struct.h
rename to components/soc/esp32c61/register/soc/lp_apm_struct.h
diff --git a/components/soc/esp32c61/register/soc/lp_clkrst_reg.h b/components/soc/esp32c61/register/soc/lp_clkrst_reg.h
new file mode 100644
index 00000000000..755a7c3c635
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/lp_clkrst_reg.h
@@ -0,0 +1,438 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_CLKRST_LP_CLK_CONF_REG register
+ *  Configures the root clk of LP system
+ */
+#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
+/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Configures the source of LP_SLOW_CLK.
+ *  0: RC_SLOW_CLK
+ *  1: XTAL32K_CLK
+ *  2: RC32K_CLK
+ *  3:OSC_SLOW_CLK
+ */
+#define LP_CLKRST_SLOW_CLK_SEL    0x00000003U
+#define LP_CLKRST_SLOW_CLK_SEL_M  (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
+#define LP_CLKRST_SLOW_CLK_SEL_V  0x00000003U
+#define LP_CLKRST_SLOW_CLK_SEL_S  0
+/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
+ *  configures the source of LP_FAST_CLK.
+ *  0: RC_FAST_CLK
+ *  1: XTAL_D2_CLK
+ *  2: XTAL_CLK
+ */
+#define LP_CLKRST_FAST_CLK_SEL    0x00000003U
+#define LP_CLKRST_FAST_CLK_SEL_M  (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
+#define LP_CLKRST_FAST_CLK_SEL_V  0x00000003U
+#define LP_CLKRST_FAST_CLK_SEL_S  2
+/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
+ *  reserved
+ */
+#define LP_CLKRST_LP_PERI_DIV_NUM    0x000000FFU
+#define LP_CLKRST_LP_PERI_DIV_NUM_M  (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
+#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_LP_PERI_DIV_NUM_S  4
+
+/** LP_CLKRST_LP_CLK_PO_EN_REG register
+ *  Configures the clk gate to pad
+ */
+#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
+/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
+ *  Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_AON_SLOW_OEN    (BIT(0))
+#define LP_CLKRST_AON_SLOW_OEN_M  (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
+#define LP_CLKRST_AON_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_AON_SLOW_OEN_S  0
+/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
+ *  Configures the clock gate to pad of the LP_DYN_FAST_CLK.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_AON_FAST_OEN    (BIT(1))
+#define LP_CLKRST_AON_FAST_OEN_M  (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
+#define LP_CLKRST_AON_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_AON_FAST_OEN_S  1
+/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
+ *  Configures the clock gate to pad of the OSC_SLOW_CLK.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_SOSC_OEN    (BIT(2))
+#define LP_CLKRST_SOSC_OEN_M  (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
+#define LP_CLKRST_SOSC_OEN_V  0x00000001U
+#define LP_CLKRST_SOSC_OEN_S  2
+/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
+ *  Configures the clock gate to pad of the RC_FAST_CLK.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_FOSC_OEN    (BIT(3))
+#define LP_CLKRST_FOSC_OEN_M  (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
+#define LP_CLKRST_FOSC_OEN_V  0x00000001U
+#define LP_CLKRST_FOSC_OEN_S  3
+/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
+ *  Configures the clock gate to pad of the RC32K_CLK.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_OSC32K_OEN    (BIT(4))
+#define LP_CLKRST_OSC32K_OEN_M  (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
+#define LP_CLKRST_OSC32K_OEN_V  0x00000001U
+#define LP_CLKRST_OSC32K_OEN_S  4
+/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
+ *  Configures the clock gate to pad of the XTAL32K_CLK.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_XTAL32K_OEN    (BIT(5))
+#define LP_CLKRST_XTAL32K_OEN_M  (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
+#define LP_CLKRST_XTAL32K_OEN_V  0x00000001U
+#define LP_CLKRST_XTAL32K_OEN_S  5
+/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
+ *  Configures the clock gate to pad of the EFUSE_CTRL clock.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_CORE_EFUSE_OEN    (BIT(6))
+#define LP_CLKRST_CORE_EFUSE_OEN_M  (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
+#define LP_CLKRST_CORE_EFUSE_OEN_V  0x00000001U
+#define LP_CLKRST_CORE_EFUSE_OEN_S  6
+/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
+ *  Configures the clock gate to pad of the LP_SLOW_CLK.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_SLOW_OEN    (BIT(7))
+#define LP_CLKRST_SLOW_OEN_M  (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
+#define LP_CLKRST_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_SLOW_OEN_S  7
+/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
+ *  Configures the clock gate to pad of the LP_FAST_CLK.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_FAST_OEN    (BIT(8))
+#define LP_CLKRST_FAST_OEN_M  (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
+#define LP_CLKRST_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_FAST_OEN_S  8
+/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
+ *  Configures the clock gate to pad of the RNG clk.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_RNG_OEN    (BIT(9))
+#define LP_CLKRST_RNG_OEN_M  (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
+#define LP_CLKRST_RNG_OEN_V  0x00000001U
+#define LP_CLKRST_RNG_OEN_S  9
+/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
+ *  Configures the clock gate to pad of the LP bus clk.
+ *  0: Disable the clk pass clock gate
+ *  1: Enable the clk pass clock gate
+ */
+#define LP_CLKRST_LPBUS_OEN    (BIT(10))
+#define LP_CLKRST_LPBUS_OEN_M  (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
+#define LP_CLKRST_LPBUS_OEN_V  0x00000001U
+#define LP_CLKRST_LPBUS_OEN_S  10
+
+/** LP_CLKRST_LP_CLK_EN_REG register
+ *  Configure LP root clk source gate
+ */
+#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
+/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
+ *  Configures the clock gate to LP_FAST_CLK
+ *  0: Invalid. The clock gate controlled by hardware fsm
+ *  1: Force the clk pass clock gate
+ */
+#define LP_CLKRST_FAST_ORI_GATE    (BIT(31))
+#define LP_CLKRST_FAST_ORI_GATE_M  (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
+#define LP_CLKRST_FAST_ORI_GATE_V  0x00000001U
+#define LP_CLKRST_FAST_ORI_GATE_S  31
+
+/** LP_CLKRST_LP_RST_EN_REG register
+ *  Configures the peri of LP system software reset
+ */
+#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
+/** LP_CLKRST_POR_ST_WAIT_FORCE_EN : R/W; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define LP_CLKRST_POR_ST_WAIT_FORCE_EN    (BIT(27))
+#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_M  (LP_CLKRST_POR_ST_WAIT_FORCE_EN_V << LP_CLKRST_POR_ST_WAIT_FORCE_EN_S)
+#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_V  0x00000001U
+#define LP_CLKRST_POR_ST_WAIT_FORCE_EN_S  27
+/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to reset  EFUSE_CTRL always-on part
+ *  0: Invalid.No effect
+ *  1: Reset
+ */
+#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN    (BIT(28))
+#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M  (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
+#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V  0x00000001U
+#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S  28
+/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to reset  LP_TIMER
+ *  0: Invalid.No effect
+ *  1: Reset
+ */
+#define LP_CLKRST_LP_TIMER_RESET_EN    (BIT(29))
+#define LP_CLKRST_LP_TIMER_RESET_EN_M  (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
+#define LP_CLKRST_LP_TIMER_RESET_EN_V  0x00000001U
+#define LP_CLKRST_LP_TIMER_RESET_EN_S  29
+/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures whether or not to reset LP_WDT and super watch dog
+ *  0: Invalid.No effect
+ *  1: Reset
+ */
+#define LP_CLKRST_WDT_RESET_EN    (BIT(30))
+#define LP_CLKRST_WDT_RESET_EN_M  (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
+#define LP_CLKRST_WDT_RESET_EN_V  0x00000001U
+#define LP_CLKRST_WDT_RESET_EN_S  30
+/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether or not to reset analog peri, include brownout controller
+ *  0: Invalid.No effect
+ *  1: Reset
+ */
+#define LP_CLKRST_ANA_PERI_RESET_EN    (BIT(31))
+#define LP_CLKRST_ANA_PERI_RESET_EN_M  (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
+#define LP_CLKRST_ANA_PERI_RESET_EN_V  0x00000001U
+#define LP_CLKRST_ANA_PERI_RESET_EN_S  31
+
+/** LP_CLKRST_RESET_CAUSE_REG register
+ *  Represents the reset cause
+ */
+#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
+/** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
+ *  Represents the reset cause
+ */
+#define LP_CLKRST_RESET_CAUSE    0x0000001FU
+#define LP_CLKRST_RESET_CAUSE_M  (LP_CLKRST_RESET_CAUSE_V << LP_CLKRST_RESET_CAUSE_S)
+#define LP_CLKRST_RESET_CAUSE_V  0x0000001FU
+#define LP_CLKRST_RESET_CAUSE_S  0
+/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
+ *  Represents the reset flag
+ */
+#define LP_CLKRST_CORE0_RESET_FLAG    (BIT(5))
+#define LP_CLKRST_CORE0_RESET_FLAG_M  (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
+#define LP_CLKRST_CORE0_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_CORE0_RESET_FLAG_S  5
+/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
+ *  0: no operation
+ */
+#define LP_CLKRST_CORE0_RESET_CAUSE_CLR    (BIT(29))
+#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S  29
+/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
+ *  configure set reset flag
+ */
+#define LP_CLKRST_CORE0_RESET_FLAG_SET    (BIT(30))
+#define LP_CLKRST_CORE0_RESET_FLAG_SET_M  (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
+#define LP_CLKRST_CORE0_RESET_FLAG_SET_V  0x00000001U
+#define LP_CLKRST_CORE0_RESET_FLAG_SET_S  30
+/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
+ *  configure clear reset flag
+ *  0: no operation
+ *  1: clear flag to 0
+ */
+#define LP_CLKRST_CORE0_RESET_FLAG_CLR    (BIT(31))
+#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M  (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
+#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S  31
+
+/** LP_CLKRST_CPU_RESET_REG register
+ *  Configures CPU reset
+ */
+#define LP_CLKRST_CPU_RESET_REG (DR_REG_LP_CLKRST_BASE + 0x14)
+/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
+ *  configure the hpcore0 luckup reset enable
+ *  0: disable
+ *  1:enable
+ */
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(21))
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S  21
+/** LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
+ *  configures the reset length of LP_WDT reset CPU
+ *  Measurement unit: LP_DYN_FAST_CLK
+ */
+#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH    0x00000007U
+#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_M  (LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S)
+#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_V  0x00000007U
+#define LP_CLKRST_RTC_WDT_CPU_RESET_LENGTH_S  22
+/** LP_CLKRST_RTC_WDT_CPU_RESET_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not LP_WDT can reset CPU
+ *  0: LP_WDT could not reset CPU when LP_WDT timeout
+ *  1: LP_WDT could reset CPU when LP_WDT timeout
+ */
+#define LP_CLKRST_RTC_WDT_CPU_RESET_EN    (BIT(25))
+#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_M  (LP_CLKRST_RTC_WDT_CPU_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_RESET_EN_S)
+#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_V  0x00000001U
+#define LP_CLKRST_RTC_WDT_CPU_RESET_EN_S  25
+/** LP_CLKRST_CPU_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
+ *  configure the time between CPU stall and reset
+ *  Measurement unit: LP_DYN_FAST_CLK
+ */
+#define LP_CLKRST_CPU_STALL_WAIT    0x0000001FU
+#define LP_CLKRST_CPU_STALL_WAIT_M  (LP_CLKRST_CPU_STALL_WAIT_V << LP_CLKRST_CPU_STALL_WAIT_S)
+#define LP_CLKRST_CPU_STALL_WAIT_V  0x0000001FU
+#define LP_CLKRST_CPU_STALL_WAIT_S  26
+/** LP_CLKRST_CPU_STALL_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
+ *  0: CPU will not entry stall state before LP_WDT and software reset CPU
+ *  1: CPU will entry stall state before LP_WDT and software reset CPU
+ */
+#define LP_CLKRST_CPU_STALL_EN    (BIT(31))
+#define LP_CLKRST_CPU_STALL_EN_M  (LP_CLKRST_CPU_STALL_EN_V << LP_CLKRST_CPU_STALL_EN_S)
+#define LP_CLKRST_CPU_STALL_EN_V  0x00000001U
+#define LP_CLKRST_CPU_STALL_EN_S  31
+
+/** LP_CLKRST_FOSC_CNTL_REG register
+ *  Configures the RC_FAST_CLK frequency
+ */
+#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x18)
+/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
+ *  Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
+ *  field
+ */
+#define LP_CLKRST_FOSC_DFREQ    0x000003FFU
+#define LP_CLKRST_FOSC_DFREQ_M  (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
+#define LP_CLKRST_FOSC_DFREQ_V  0x000003FFU
+#define LP_CLKRST_FOSC_DFREQ_S  22
+
+/** LP_CLKRST_RC32K_CNTL_REG register
+ *  Configures the RC32K_CLK frequency
+ */
+#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
+/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
+ *  Configures the RC32K_CLK frequency, the clock frequency will increase with this
+ *  field
+ */
+#define LP_CLKRST_RC32K_DFREQ    0x000003FFU
+#define LP_CLKRST_RC32K_DFREQ_M  (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
+#define LP_CLKRST_RC32K_DFREQ_V  0x000003FFU
+#define LP_CLKRST_RC32K_DFREQ_S  22
+
+/** LP_CLKRST_CLK_TO_HP_REG register
+ *  Configures the clk gate of LP clk to HP system
+ */
+#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x20)
+/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
+ *  Configures the clk gate of XTAL32K_CLK to HP system
+ *  0: The clk could not pass to HP system
+ *  1: The clk could pass to HP system
+ */
+#define LP_CLKRST_ICG_HP_XTAL32K    (BIT(28))
+#define LP_CLKRST_ICG_HP_XTAL32K_M  (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
+#define LP_CLKRST_ICG_HP_XTAL32K_V  0x00000001U
+#define LP_CLKRST_ICG_HP_XTAL32K_S  28
+/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
+ *  Configures the clk gate of RC_SLOW_CLK to HP system
+ *  0: The clk could not pass to HP system
+ *  1: The clk could pass to HP system
+ */
+#define LP_CLKRST_ICG_HP_SOSC    (BIT(29))
+#define LP_CLKRST_ICG_HP_SOSC_M  (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
+#define LP_CLKRST_ICG_HP_SOSC_V  0x00000001U
+#define LP_CLKRST_ICG_HP_SOSC_S  29
+/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
+ *  Configures the clk gate of RC32K_CLK to HP system
+ *  0: The clk could not pass to HP system
+ *  1: The clk could pass to HP system
+ */
+#define LP_CLKRST_ICG_HP_OSC32K    (BIT(30))
+#define LP_CLKRST_ICG_HP_OSC32K_M  (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
+#define LP_CLKRST_ICG_HP_OSC32K_V  0x00000001U
+#define LP_CLKRST_ICG_HP_OSC32K_S  30
+/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
+ *  Configures the clk gate of RC_FAST_CLK to HP system
+ *  0: The clk could not pass to HP system
+ *  1: The clk could pass to HP system
+ */
+#define LP_CLKRST_ICG_HP_FOSC    (BIT(31))
+#define LP_CLKRST_ICG_HP_FOSC_M  (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
+#define LP_CLKRST_ICG_HP_FOSC_V  0x00000001U
+#define LP_CLKRST_ICG_HP_FOSC_S  31
+
+/** LP_CLKRST_LPMEM_FORCE_REG register
+ *  Configures the LP_MEM clk gate force parameter
+ */
+#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x24)
+/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  Configures whether ot not force open the clock gate of LP MEM
+ *  0: Invalid. The clock gate controlled by hardware FSM
+ *  1: Force open clock gate of LP MEM
+ */
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M  (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S  31
+
+/** LP_CLKRST_XTAL32K_REG register
+ *  Configures the XTAL32K parameter
+ */
+#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
+/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
+ *  Configures DRES
+ */
+#define LP_CLKRST_DRES_XTAL32K    0x00000007U
+#define LP_CLKRST_DRES_XTAL32K_M  (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
+#define LP_CLKRST_DRES_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DRES_XTAL32K_S  22
+/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
+ *  Configures DGM
+ */
+#define LP_CLKRST_DGM_XTAL32K    0x00000007U
+#define LP_CLKRST_DGM_XTAL32K_M  (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
+#define LP_CLKRST_DGM_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DGM_XTAL32K_S  25
+/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
+ *  Configures DBUF
+ */
+#define LP_CLKRST_DBUF_XTAL32K    (BIT(28))
+#define LP_CLKRST_DBUF_XTAL32K_M  (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
+#define LP_CLKRST_DBUF_XTAL32K_V  0x00000001U
+#define LP_CLKRST_DBUF_XTAL32K_S  28
+/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
+ *  Configures DAC
+ */
+#define LP_CLKRST_DAC_XTAL32K    0x00000007U
+#define LP_CLKRST_DAC_XTAL32K_M  (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
+#define LP_CLKRST_DAC_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DAC_XTAL32K_S  29
+
+/** LP_CLKRST_DATE_REG register
+ *  Version control register
+ */
+#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
+/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 36766288;
+ *  Version control register
+ */
+#define LP_CLKRST_CLKRST_DATE    0x7FFFFFFFU
+#define LP_CLKRST_CLKRST_DATE_M  (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
+#define LP_CLKRST_CLKRST_DATE_V  0x7FFFFFFFU
+#define LP_CLKRST_CLKRST_DATE_S  0
+/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  configure register clk bypass clk gate
+ */
+#define LP_CLKRST_CLK_EN    (BIT(31))
+#define LP_CLKRST_CLK_EN_M  (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
+#define LP_CLKRST_CLK_EN_V  0x00000001U
+#define LP_CLKRST_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/lp_clkrst_struct.h b/components/soc/esp32c61/register/soc/lp_clkrst_struct.h
new file mode 100644
index 00000000000..2c69f169a57
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/lp_clkrst_struct.h
@@ -0,0 +1,392 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_clk_conf register
+ *  Configures the root clk of LP system
+ */
+typedef union {
+    struct {
+        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures the source of LP_SLOW_CLK.
+         *  0: RC_SLOW_CLK
+         *  1: XTAL32K_CLK
+         *  2: RC32K_CLK
+         *  3:OSC_SLOW_CLK
+         */
+        uint32_t slow_clk_sel:2;
+        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
+         *  configures the source of LP_FAST_CLK.
+         *  0: RC_FAST_CLK
+         *  1: XTAL_D2_CLK
+         *  2: XTAL_CLK
+         */
+        uint32_t fast_clk_sel:2;
+        /** lp_peri_div_num : R/W; bitpos: [11:4]; default: 0;
+         *  reserved
+         */
+        uint32_t lp_peri_div_num:8;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_conf_reg_t;
+
+/** Type of lp_clk_po_en register
+ *  Configures the clk gate to pad
+ */
+typedef union {
+    struct {
+        /** aon_slow_oen : R/W; bitpos: [0]; default: 1;
+         *  Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t aon_slow_oen:1;
+        /** aon_fast_oen : R/W; bitpos: [1]; default: 1;
+         *  Configures the clock gate to pad of the LP_DYN_FAST_CLK.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t aon_fast_oen:1;
+        /** sosc_oen : R/W; bitpos: [2]; default: 1;
+         *  Configures the clock gate to pad of the OSC_SLOW_CLK.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t sosc_oen:1;
+        /** fosc_oen : R/W; bitpos: [3]; default: 1;
+         *  Configures the clock gate to pad of the RC_FAST_CLK.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t fosc_oen:1;
+        /** osc32k_oen : R/W; bitpos: [4]; default: 1;
+         *  Configures the clock gate to pad of the RC32K_CLK.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t osc32k_oen:1;
+        /** xtal32k_oen : R/W; bitpos: [5]; default: 1;
+         *  Configures the clock gate to pad of the XTAL32K_CLK.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t xtal32k_oen:1;
+        /** core_efuse_oen : R/W; bitpos: [6]; default: 1;
+         *  Configures the clock gate to pad of the EFUSE_CTRL clock.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t core_efuse_oen:1;
+        /** slow_oen : R/W; bitpos: [7]; default: 1;
+         *  Configures the clock gate to pad of the LP_SLOW_CLK.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t slow_oen:1;
+        /** fast_oen : R/W; bitpos: [8]; default: 1;
+         *  Configures the clock gate to pad of the LP_FAST_CLK.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t fast_oen:1;
+        /** rng_oen : R/W; bitpos: [9]; default: 1;
+         *  Configures the clock gate to pad of the RNG clk.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t rng_oen:1;
+        /** lpbus_oen : R/W; bitpos: [10]; default: 1;
+         *  Configures the clock gate to pad of the LP bus clk.
+         *  0: Disable the clk pass clock gate
+         *  1: Enable the clk pass clock gate
+         */
+        uint32_t lpbus_oen:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_po_en_reg_t;
+
+/** Type of lp_clk_en register
+ *  Configure LP root clk source gate
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** fast_ori_gate : R/W; bitpos: [31]; default: 0;
+         *  Configures the clock gate to LP_FAST_CLK
+         *  0: Invalid. The clock gate controlled by hardware fsm
+         *  1: Force the clk pass clock gate
+         */
+        uint32_t fast_ori_gate:1;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_en_reg_t;
+
+/** Type of lp_rst_en register
+ *  Configures the peri of LP system software reset
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** por_st_wait_force_en : R/W; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t por_st_wait_force_en:1;
+        /** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to reset  EFUSE_CTRL always-on part
+         *  0: Invalid.No effect
+         *  1: Reset
+         */
+        uint32_t aon_efuse_core_reset_en:1;
+        /** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to reset  LP_TIMER
+         *  0: Invalid.No effect
+         *  1: Reset
+         */
+        uint32_t lp_timer_reset_en:1;
+        /** wdt_reset_en : R/W; bitpos: [30]; default: 0;
+         *  Configures whether or not to reset LP_WDT and super watch dog
+         *  0: Invalid.No effect
+         *  1: Reset
+         */
+        uint32_t wdt_reset_en:1;
+        /** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether or not to reset analog peri, include brownout controller
+         *  0: Invalid.No effect
+         *  1: Reset
+         */
+        uint32_t ana_peri_reset_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_lp_rst_en_reg_t;
+
+/** Type of reset_cause register
+ *  Represents the reset cause
+ */
+typedef union {
+    struct {
+        /** reset_cause : RO; bitpos: [4:0]; default: 0;
+         *  Represents the reset cause
+         */
+        uint32_t reset_cause:5;
+        /** core0_reset_flag : RO; bitpos: [5]; default: 1;
+         *  Represents the reset flag
+         */
+        uint32_t core0_reset_flag:1;
+        uint32_t reserved_6:23;
+        /** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
+         *  0: no operation
+         */
+        uint32_t core0_reset_cause_clr:1;
+        /** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
+         *  configure set reset flag
+         */
+        uint32_t core0_reset_flag_set:1;
+        /** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
+         *  configure clear reset flag
+         *  0: no operation
+         *  1: clear flag to 0
+         */
+        uint32_t core0_reset_flag_clr:1;
+    };
+    uint32_t val;
+} lp_clkrst_reset_cause_reg_t;
+
+/** Type of cpu_reset register
+ *  Configures CPU reset
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1;
+         *  configure the hpcore0 luckup reset enable
+         *  0: disable
+         *  1:enable
+         */
+        uint32_t hpcore0_lockup_reset_en:1;
+        /** rtc_wdt_cpu_reset_length : R/W; bitpos: [24:22]; default: 1;
+         *  configures the reset length of LP_WDT reset CPU
+         *  Measurement unit: LP_DYN_FAST_CLK
+         */
+        uint32_t rtc_wdt_cpu_reset_length:3;
+        /** rtc_wdt_cpu_reset_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not LP_WDT can reset CPU
+         *  0: LP_WDT could not reset CPU when LP_WDT timeout
+         *  1: LP_WDT could reset CPU when LP_WDT timeout
+         */
+        uint32_t rtc_wdt_cpu_reset_en:1;
+        /** cpu_stall_wait : R/W; bitpos: [30:26]; default: 1;
+         *  configure the time between CPU stall and reset
+         *  Measurement unit: LP_DYN_FAST_CLK
+         */
+        uint32_t cpu_stall_wait:5;
+        /** cpu_stall_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
+         *  0: CPU will not entry stall state before LP_WDT and software reset CPU
+         *  1: CPU will entry stall state before LP_WDT and software reset CPU
+         */
+        uint32_t cpu_stall_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_cpu_reset_reg_t;
+
+/** Type of fosc_cntl register
+ *  Configures the RC_FAST_CLK frequency
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 172;
+         *  Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
+         *  field
+         */
+        uint32_t fosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_clkrst_fosc_cntl_reg_t;
+
+/** Type of rc32k_cntl register
+ *  Configures the RC32K_CLK frequency
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
+         *  Configures the RC32K_CLK frequency, the clock frequency will increase with this
+         *  field
+         */
+        uint32_t rc32k_dfreq:10;
+    };
+    uint32_t val;
+} lp_clkrst_rc32k_cntl_reg_t;
+
+/** Type of clk_to_hp register
+ *  Configures the clk gate of LP clk to HP system
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
+         *  Configures the clk gate of XTAL32K_CLK to HP system
+         *  0: The clk could not pass to HP system
+         *  1: The clk could pass to HP system
+         */
+        uint32_t icg_hp_xtal32k:1;
+        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
+         *  Configures the clk gate of RC_SLOW_CLK to HP system
+         *  0: The clk could not pass to HP system
+         *  1: The clk could pass to HP system
+         */
+        uint32_t icg_hp_sosc:1;
+        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
+         *  Configures the clk gate of RC32K_CLK to HP system
+         *  0: The clk could not pass to HP system
+         *  1: The clk could pass to HP system
+         */
+        uint32_t icg_hp_osc32k:1;
+        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
+         *  Configures the clk gate of RC_FAST_CLK to HP system
+         *  0: The clk could not pass to HP system
+         *  1: The clk could pass to HP system
+         */
+        uint32_t icg_hp_fosc:1;
+    };
+    uint32_t val;
+} lp_clkrst_clk_to_hp_reg_t;
+
+/** Type of lpmem_force register
+ *  Configures the LP_MEM clk gate force parameter
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  Configures whether ot not force open the clock gate of LP MEM
+         *  0: Invalid. The clock gate controlled by hardware FSM
+         *  1: Force open clock gate of LP MEM
+         */
+        uint32_t lpmem_clk_force_on:1;
+    };
+    uint32_t val;
+} lp_clkrst_lpmem_force_reg_t;
+
+/** Type of xtal32k register
+ *  Configures the XTAL32K parameter
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
+         *  Configures DRES
+         */
+        uint32_t dres_xtal32k:3;
+        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
+         *  Configures DGM
+         */
+        uint32_t dgm_xtal32k:3;
+        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
+         *  Configures DBUF
+         */
+        uint32_t dbuf_xtal32k:1;
+        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
+         *  Configures DAC
+         */
+        uint32_t dac_xtal32k:3;
+    };
+    uint32_t val;
+} lp_clkrst_xtal32k_reg_t;
+
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** clkrst_date : R/W; bitpos: [30:0]; default: 36766288;
+         *  Version control register
+         */
+        uint32_t clkrst_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  configure register clk bypass clk gate
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_date_reg_t;
+
+
+typedef struct {
+    volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
+    volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
+    volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
+    volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
+    volatile lp_clkrst_reset_cause_reg_t reset_cause;
+    volatile lp_clkrst_cpu_reset_reg_t cpu_reset;
+    volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
+    volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
+    volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
+    volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
+    uint32_t reserved_028;
+    volatile lp_clkrst_xtal32k_reg_t xtal32k;
+    uint32_t reserved_030[243];
+    volatile lp_clkrst_date_reg_t date;
+} lp_clkrst_dev_t;
+
+extern lp_clkrst_dev_t LP_CLKRST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/lp_gpio_reg.h b/components/soc/esp32c61/register/soc/lp_gpio_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_gpio_reg.h
rename to components/soc/esp32c61/register/soc/lp_gpio_reg.h
diff --git a/components/soc/esp32c61/include/soc/lp_gpio_struct.h b/components/soc/esp32c61/register/soc/lp_gpio_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_gpio_struct.h
rename to components/soc/esp32c61/register/soc/lp_gpio_struct.h
diff --git a/components/soc/esp32c61/include/soc/lp_iomux_reg.h b/components/soc/esp32c61/register/soc/lp_iomux_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_iomux_reg.h
rename to components/soc/esp32c61/register/soc/lp_iomux_reg.h
diff --git a/components/soc/esp32c61/include/soc/lp_iomux_struct.h b/components/soc/esp32c61/register/soc/lp_iomux_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_iomux_struct.h
rename to components/soc/esp32c61/register/soc/lp_iomux_struct.h
diff --git a/components/soc/esp32c61/include/soc/lp_tee_reg.h b/components/soc/esp32c61/register/soc/lp_tee_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_tee_reg.h
rename to components/soc/esp32c61/register/soc/lp_tee_reg.h
diff --git a/components/soc/esp32c61/include/soc/lp_tee_struct.h b/components/soc/esp32c61/register/soc/lp_tee_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_tee_struct.h
rename to components/soc/esp32c61/register/soc/lp_tee_struct.h
diff --git a/components/soc/esp32c61/include/soc/lp_timer_reg.h b/components/soc/esp32c61/register/soc/lp_timer_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_timer_reg.h
rename to components/soc/esp32c61/register/soc/lp_timer_reg.h
diff --git a/components/soc/esp32c61/include/soc/lp_timer_struct.h b/components/soc/esp32c61/register/soc/lp_timer_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_timer_struct.h
rename to components/soc/esp32c61/register/soc/lp_timer_struct.h
diff --git a/components/soc/esp32c61/include/soc/lp_wdt_reg.h b/components/soc/esp32c61/register/soc/lp_wdt_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_wdt_reg.h
rename to components/soc/esp32c61/register/soc/lp_wdt_reg.h
diff --git a/components/soc/esp32c61/include/soc/lp_wdt_struct.h b/components/soc/esp32c61/register/soc/lp_wdt_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lp_wdt_struct.h
rename to components/soc/esp32c61/register/soc/lp_wdt_struct.h
diff --git a/components/soc/esp32c61/include/soc/lpperi_reg.h b/components/soc/esp32c61/register/soc/lpperi_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lpperi_reg.h
rename to components/soc/esp32c61/register/soc/lpperi_reg.h
diff --git a/components/soc/esp32c61/include/soc/lpperi_struct.h b/components/soc/esp32c61/register/soc/lpperi_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/lpperi_struct.h
rename to components/soc/esp32c61/register/soc/lpperi_struct.h
diff --git a/components/soc/esp32c61/include/soc/mem_monitor_reg.h b/components/soc/esp32c61/register/soc/mem_monitor_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/mem_monitor_reg.h
rename to components/soc/esp32c61/register/soc/mem_monitor_reg.h
diff --git a/components/soc/esp32c61/include/soc/mem_monitor_struct.h b/components/soc/esp32c61/register/soc/mem_monitor_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/mem_monitor_struct.h
rename to components/soc/esp32c61/register/soc/mem_monitor_struct.h
diff --git a/components/soc/esp32c61/include/soc/pau_reg.h b/components/soc/esp32c61/register/soc/pau_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/pau_reg.h
rename to components/soc/esp32c61/register/soc/pau_reg.h
diff --git a/components/soc/esp32c61/include/soc/pau_struct.h b/components/soc/esp32c61/register/soc/pau_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/pau_struct.h
rename to components/soc/esp32c61/register/soc/pau_struct.h
diff --git a/components/soc/esp32c61/include/soc/pcr_reg.h b/components/soc/esp32c61/register/soc/pcr_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/pcr_reg.h
rename to components/soc/esp32c61/register/soc/pcr_reg.h
diff --git a/components/soc/esp32c61/include/soc/pcr_struct.h b/components/soc/esp32c61/register/soc/pcr_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/pcr_struct.h
rename to components/soc/esp32c61/register/soc/pcr_struct.h
diff --git a/components/soc/esp32c61/include/soc/pmu_reg.h b/components/soc/esp32c61/register/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/pmu_reg.h
rename to components/soc/esp32c61/register/soc/pmu_reg.h
diff --git a/components/soc/esp32c61/register/soc/pmu_struct.h b/components/soc/esp32c61/register/soc/pmu_struct.h
new file mode 100644
index 00000000000..e59470be4e9
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/pmu_struct.h
@@ -0,0 +1,769 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "soc/soc.h"
+#include "soc/pmu_reg.h"
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t vdd_spi_pd_en: 1;
+        uint32_t mem_dslp     : 1;
+        uint32_t mem_pd_en    : 4;
+        uint32_t wifi_pd_en   : 1;
+        uint32_t reserved1    : 1;
+        uint32_t cpu_pd_en    : 1;
+        uint32_t aon_pd_en    : 1;
+        uint32_t top_pd_en    : 1;
+    };
+    uint32_t val;
+} pmu_hp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 30;
+        uint32_t code     : 2;
+    };
+    uint32_t val;
+} pmu_hp_icg_modem_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 24;
+        uint32_t uart_wakeup_en : 1;
+        uint32_t lp_pad_hold_all: 1;
+        uint32_t hp_pad_hold_all: 1;
+        uint32_t dig_pad_slp_sel: 1;
+        uint32_t dig_pause_wdt  : 1;
+        uint32_t dig_cpu_stall  : 1;
+        uint32_t reserved1      : 2;
+    };
+    uint32_t val;
+} pmu_hp_sys_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 26;
+        uint32_t i2c_iso_en   : 1;
+        uint32_t i2c_retention: 1;
+        uint32_t xpd_bb_i2c   : 1;
+        uint32_t xpd_bbpll_i2c: 1;
+        uint32_t xpd_bbpll    : 1;
+        uint32_t reserved1    : 1;
+    };
+    uint32_t val;
+} pmu_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_hp_bias_reg_t;
+
+typedef union {
+    struct {    /* HP: Active State */
+        uint32_t reserved0                            : 4;
+        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
+        uint32_t hp_modem2active_backup_modem_clk_code: 2;
+        uint32_t reserved1                            : 2;
+        uint32_t hp_active_retention_mode             : 1;
+        uint32_t hp_sleep2active_retention_en         : 1;
+        uint32_t hp_modem2active_retention_en         : 1;
+        uint32_t reserved2                            : 1;
+        uint32_t hp_sleep2active_backup_clk_sel       : 2;
+        uint32_t hp_modem2active_backup_clk_sel       : 2;
+        uint32_t reserved3                            : 2;
+        uint32_t hp_sleep2active_backup_mode          : 3;
+        uint32_t hp_modem2active_backup_mode          : 3;
+        uint32_t reserved4                            : 3;
+        uint32_t hp_sleep2active_backup_en            : 1;
+        uint32_t hp_modem2active_backup_en            : 1;
+        uint32_t reserved5                            : 1;
+    };
+    struct {    /* HP: Modem State */
+        uint32_t reserved6                            : 4;
+        uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
+        uint32_t reserved7                            : 4;
+        uint32_t hp_modem_retention_mode              : 1;
+        uint32_t hp_sleep2modem_retention_en          : 1;
+        uint32_t reserved8                            : 2;
+        uint32_t hp_sleep2modem_backup_clk_sel        : 2;
+        uint32_t reserved9                            : 4;
+        uint32_t hp_sleep2modem_backup_mode           : 3;
+        uint32_t reserved10                           : 6;
+        uint32_t hp_sleep2modem_backup_en             : 1;
+        uint32_t reserved11                           : 2;
+    };
+    struct {    /* HP: Sleep State */
+        uint32_t reserved12                           : 6;
+        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
+        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
+        uint32_t hp_sleep_retention_mode              : 1;
+        uint32_t reserved13                           : 1;
+        uint32_t hp_modem2sleep_retention_en          : 1;
+        uint32_t hp_active2sleep_retention_en         : 1;
+        uint32_t reserved14                           : 2;
+        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
+        uint32_t hp_active2sleep_backup_clk_sel       : 2;
+        uint32_t reserved15                           : 3;
+        uint32_t hp_modem2sleep_backup_mode           : 3;
+        uint32_t hp_active2sleep_backup_mode          : 3;
+        uint32_t reserved16                           : 1;
+        uint32_t hp_modem2sleep_backup_en             : 1;
+        uint32_t hp_active2sleep_backup_en            : 1;
+    };
+    uint32_t val;
+} pmu_hp_backup_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0       : 26;
+        uint32_t dig_sysclk_nodiv: 1;
+        uint32_t icg_sysclk_en   : 1;
+        uint32_t sysclk_slp_sel  : 1;
+        uint32_t icg_slp_sel     : 1;
+        uint32_t dig_sysclk_sel  : 2;
+    };
+    uint32_t val;
+} pmu_hp_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t slp_mem_xpd    : 1;
+        uint32_t slp_logic_xpd  : 1;
+        uint32_t xpd            : 1;
+        uint32_t slp_mem_dbias  : 4;
+        uint32_t slp_logic_dbias: 4;
+        uint32_t dbias          : 5;
+    };
+    uint32_t val;
+} pmu_hp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 8;
+        uint32_t drv_b    : 24;
+    };
+    uint32_t val;
+} pmu_hp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_hp_xtal_reg_t;
+
+typedef struct pmu_hp_hw_regmap_t{
+    pmu_hp_dig_power_reg_t     dig_power;
+    uint32_t                   icg_func;
+    uint32_t                   icg_apb;
+    pmu_hp_icg_modem_reg_t     icg_modem;
+    pmu_hp_sys_cntl_reg_t      syscntl;
+    pmu_hp_clk_power_reg_t     clk_power;
+    pmu_hp_bias_reg_t          bias;
+    pmu_hp_backup_reg_t        backup;
+    uint32_t                   backup_clk;
+    pmu_hp_sysclk_reg_t        sysclk;
+    pmu_hp_regulator0_reg_t    regulator0;
+    pmu_hp_regulator1_reg_t    regulator1;
+    pmu_hp_xtal_reg_t          xtal;
+} pmu_hp_hw_regmap_t;
+
+/** */
+typedef union {
+    struct {
+        uint32_t reserved0: 21;
+        uint32_t slp_xpd  : 1;
+        uint32_t xpd	  : 1;
+        uint32_t slp_dbias: 4;
+        uint32_t dbias    : 5;
+    };
+    uint32_t val;
+} pmu_lp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 28;
+        uint32_t drv_b    : 4;
+    };
+    uint32_t val;
+} pmu_lp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_lp_xtal_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 30;
+        uint32_t mem_dslp  : 1;
+        uint32_t peri_pd_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0  : 28;
+        uint32_t xpd_xtal32k: 1;
+        uint32_t xpd_rc32k  : 1;
+        uint32_t xpd_fosc   : 1;
+        uint32_t pd_osc     : 1;
+    };
+    uint32_t val;
+} pmu_lp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_lp_bias_reg_t;
+
+typedef struct pmu_lp_hw_regmap_t{
+    pmu_lp_regulator0_reg_t    regulator0;
+    pmu_lp_regulator1_reg_t    regulator1;
+    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
+    pmu_lp_dig_power_reg_t     dig_power;
+    pmu_lp_clk_power_reg_t     clk_power;
+    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
+} pmu_lp_hw_regmap_t;
+
+
+typedef union {
+    struct {
+        uint32_t tie_low_global_bbpll_icg : 1;
+        uint32_t tie_low_global_xtal_icg  : 1;
+        uint32_t tie_low_i2c_retention    : 1;
+        uint32_t tie_low_xpd_bb_i2c       : 1;
+        uint32_t tie_low_xpd_bbpll_i2c    : 1;
+        uint32_t tie_low_xpd_bbpll        : 1;
+        uint32_t tie_low_xpd_xtal         : 1;
+        uint32_t reserved0                : 18;
+        uint32_t tie_high_global_bbpll_icg: 1;
+        uint32_t tie_high_global_xtal_icg : 1;
+        uint32_t tie_high_i2c_retention   : 1;
+        uint32_t tie_high_xpd_bb_i2c      : 1;
+        uint32_t tie_high_xpd_bbpll_i2c   : 1;
+        uint32_t tie_high_xpd_bbpll       : 1;
+        uint32_t tie_high_xpd_xtal        : 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 28;
+        uint32_t update_dig_icg_switch: 1;
+        uint32_t tie_low_icg_slp_sel  : 1;
+        uint32_t tie_high_icg_slp_sel : 1;
+        uint32_t update_dig_sysclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_sleep_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0             : 31;
+        uint32_t update_dig_icg_func_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_func_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 31;
+        uint32_t update_dig_icg_apb_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_apb_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 31;
+        uint32_t update_dig_icg_modem_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_modem_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 30;
+        uint32_t tie_low_lp_rootclk_sel : 1;
+        uint32_t tie_high_lp_rootclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_lp_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0               : 28;
+        uint32_t tie_high_lp_pad_hold_all: 1;
+        uint32_t tie_low_lp_pad_hold_all : 1;
+        uint32_t tie_high_hp_pad_hold_all: 1;
+        uint32_t tie_low_hp_pad_hold_all : 1;
+    };
+    uint32_t val;
+} pmu_imm_pad_hold_all_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 30;
+        uint32_t tie_high_i2c_iso_en: 1;
+        uint32_t tie_low_i2c_iso_en : 1;
+    };
+    uint32_t val;
+} pmu_imm_i2c_isolate_reg_t;
+
+typedef struct pmu_imm_hw_regmap_t{
+    pmu_imm_hp_clk_power_reg_t     clk_power;
+    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
+    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
+    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
+    pmu_imm_modem_icg_reg_t        modem_icg;
+    pmu_imm_lp_icg_reg_t           lp_icg;
+    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
+    pmu_imm_i2c_isolate_reg_t      i2c_iso;
+} pmu_imm_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 9;
+        uint32_t powerdown_timer: 7;
+        uint32_t powerup_timer  : 7;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t lp_iso_wait_timer: 8;
+        uint32_t lp_rst_wait_timer: 8;
+        uint32_t hp_iso_wait_timer: 8;
+        uint32_t hp_rst_wait_timer: 8;
+    };
+    uint32_t val;
+} pmu_power_wait_timer2_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_reset   : 1;
+        uint32_t force_iso     : 1;
+        uint32_t force_pu      : 1;
+        uint32_t force_no_reset: 1;
+        uint32_t force_no_iso  : 1;
+        uint32_t force_pd      : 1;
+        uint32_t mask          : 5;     /* Invalid of lp peripherals */
+        uint32_t reserved0     : 16;    /* Invalid of lp peripherals */
+        uint32_t pd_mask       : 5;     /* Invalid of lp peripherals */
+    };
+    uint32_t val;
+} pmu_power_domain_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_mem_iso   : 4;
+        uint32_t force_hp_mem_pd    : 4;
+        uint32_t reserved0          : 16;
+        uint32_t force_hp_mem_no_iso: 4;
+        uint32_t force_hp_mem_pu    : 4;
+    };
+    uint32_t val;
+} pmu_power_memory_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t mem2_pd_mask: 5;
+        uint32_t mem1_pd_mask: 5;
+        uint32_t mem0_pd_mask: 5;
+        uint32_t reserved0   : 2;
+        uint32_t mem2_mask   : 5;
+        uint32_t mem1_mask   : 5;
+        uint32_t mem0_mask   : 5;
+    };
+    uint32_t val;
+} pmu_power_memory_mask_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_pad_no_iso_all: 1;
+        uint32_t force_hp_pad_iso_all   : 1;
+        uint32_t reserved0              : 30;
+    };
+    uint32_t val;
+} pmu_power_hp_pad_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 18;
+        uint32_t pwr_wait  : 11;
+        uint32_t pwr_sw    : 2;
+        uint32_t pwr_sel_sw: 1;
+    };
+    uint32_t val;
+} pmu_power_vdd_spi_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wait_xtal_stable: 16;
+        uint32_t wait_pll_stable : 16;
+    };
+    uint32_t val;
+} pmu_power_clk_wait_cntl_reg_t;
+
+typedef struct pmu_power_hw_regmap_t{
+    pmu_power_wait_timer0_reg_t    wait_timer0;
+    pmu_power_wait_timer1_reg_t    wait_timer1;
+    pmu_power_wait_timer2_reg_t    wait_timer2;
+    pmu_power_domain_cntl_reg_t    hp_pd[5];
+    pmu_power_domain_cntl_reg_t    lp_peri;
+    pmu_power_memory_cntl_reg_t    mem_cntl;
+    pmu_power_memory_mask_reg_t    mem_mask;
+    pmu_power_hp_pad_reg_t         hp_pad;
+    pmu_power_vdd_spi_cntl_reg_t   vdd_spi;
+    pmu_power_clk_wait_cntl_reg_t  clk_wait;
+} pmu_power_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_ena: 31;
+        uint32_t slp_reject_en   : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t lp_min_slp_val: 8;
+        uint32_t hp_min_slp_val: 8;
+        uint32_t sleep_prt_sel : 2;
+        uint32_t reserved0     : 14;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0           : 31;
+        uint32_t slp_reject_cause_clr: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modem_wait_target : 20;
+        uint32_t reserved0         : 4;
+        uint32_t lp_ana_wait_target: 8;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl5_reg_t;
+
+typedef union {
+    struct {
+        uint32_t soc_wakeup_wait    : 20;
+        uint32_t reserved0          : 10;
+        uint32_t soc_wakeup_wait_cfg: 2;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl6_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 16;
+        uint32_t ana_wait_target: 16;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl7_reg_t;
+
+typedef struct pmu_wakeup_hw_regmap_t{
+    pmu_slp_wakeup_cntl0_reg_t     cntl0;
+    pmu_slp_wakeup_cntl1_reg_t     cntl1;
+    uint32_t                       cntl2;
+    pmu_slp_wakeup_cntl3_reg_t     cntl3;
+    pmu_slp_wakeup_cntl4_reg_t     cntl4;
+    pmu_slp_wakeup_cntl5_reg_t     cntl5;
+    pmu_slp_wakeup_cntl6_reg_t     cntl6;
+    pmu_slp_wakeup_cntl7_reg_t     cntl7;
+    uint32_t                       status0;
+    uint32_t                       status1;
+} pmu_wakeup_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t i2c_por_wait_target: 8;
+        uint32_t reserved0          : 24;
+    };
+    uint32_t val;
+} pmu_hp_clk_poweron_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modify_icg_cntl_wait: 8;
+        uint32_t switch_icg_cntl_wait: 8;
+        uint32_t reserved0           : 16;
+    };
+    uint32_t val;
+} pmu_hp_clk_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t por_done : 1;
+    };
+    uint32_t val;
+} pmu_por_status_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0     : 24;
+        uint32_t xpd_tc5g_i2c  : 1;
+        uint32_t xpd_rx5g_i2c  : 1;
+        uint32_t perif_i2c_rstb: 1;
+        uint32_t xpd_perif_i2c : 1;
+        uint32_t xpd_txrf_i2c  : 1;
+        uint32_t xpd_rfrx_pbus : 1;
+        uint32_t xpd_ckgen_i2c : 1;
+        uint32_t xpd_pll_i2c   : 1;
+    };
+    uint32_t val;
+} pmu_rf_pwc_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t backup_sysclk_nodiv: 1;
+    };
+    uint32_t val;
+} pmu_backup_cfg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 27;
+        uint32_t lp_cpu_exc: 1;
+        uint32_t sdio_idle : 1;
+        uint32_t sw        : 1;
+        uint32_t reject    : 1;
+        uint32_t wakeup    : 1;
+    };
+    uint32_t val;
+} pmu_hp_intr_reg_t;
+
+typedef struct pmu_hp_ext_hw_regmap_t{
+    pmu_hp_clk_poweron_reg_t   clk_poweron;
+    pmu_hp_clk_cntl_reg_t      clk_cntl;
+    pmu_por_status_reg_t       por_status;
+    pmu_rf_pwc_reg_t           rf_pwc;
+    pmu_backup_cfg_reg_t       backup_cfg;
+    pmu_hp_intr_reg_t          int_raw;
+    pmu_hp_intr_reg_t          int_st;
+    pmu_hp_intr_reg_t          int_ena;
+    pmu_hp_intr_reg_t          int_clr;
+} pmu_hp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0                : 20;
+        uint32_t lp_cpu_wakeup            : 1;
+        uint32_t modem_switch_active_end  : 1;
+        uint32_t sleep_switch_active_end  : 1;
+        uint32_t sleep_switch_modem_end   : 1;
+        uint32_t modem_switch_sleep_end   : 1;
+        uint32_t active_swtich_sleep_end  : 1;
+        uint32_t modem_switch_active_start: 1;
+        uint32_t sleep_switch_active_start: 1;
+        uint32_t sleep_switch_modem_start : 1;
+        uint32_t modem_switch_sleep_start : 1;
+        uint32_t active_switch_sleep_start: 1;
+        uint32_t sw_trigger               : 1;
+    };
+    uint32_t val;
+} pmu_lp_intr_reg_t;
+
+typedef union {
+    struct {
+        uint32_t waiti_rdy         : 1;
+        uint32_t stall_rdy         : 1;
+        uint32_t reserved0         : 16;
+        uint32_t force_stall       : 1;
+        uint32_t slp_waiti_flag_en : 1;
+        uint32_t slp_stall_flag_en : 1;
+        uint32_t slp_stall_wait    : 8;
+        uint32_t slp_stall_en      : 1;
+        uint32_t slp_reset_en      : 1;
+        uint32_t slp_bypass_intr_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_en: 16;
+        uint32_t reserved0: 15;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr1_reg_t;
+
+typedef struct pmu_lp_ext_hw_regmap_t{
+    pmu_lp_intr_reg_t          int_raw;
+    pmu_lp_intr_reg_t          int_st;
+    pmu_lp_intr_reg_t          int_ena;
+    pmu_lp_intr_reg_t          int_clr;
+    pmu_lp_cpu_pwr0_reg_t      pwr0;
+    pmu_lp_cpu_pwr1_reg_t      pwr1;
+} pmu_lp_ext_hw_regmap_t;
+
+typedef struct pmu_dev_t{
+    volatile pmu_hp_hw_regmap_t     hp_sys[3];
+    volatile pmu_lp_hw_regmap_t     lp_sys[2];
+    volatile pmu_imm_hw_regmap_t    imm;
+    volatile pmu_power_hw_regmap_t  power;
+    volatile pmu_wakeup_hw_regmap_t wakeup;
+    volatile pmu_hp_ext_hw_regmap_t hp_ext;
+    volatile pmu_lp_ext_hw_regmap_t lp_ext;
+
+    union {
+        struct {
+            uint32_t reserved0    : 30;
+            volatile uint32_t lp_trigger_hp: 1;
+            volatile uint32_t hp_trigger_lp: 1;
+        };
+        volatile uint32_t val;
+    } hp_lp_cpu_comm;
+
+    union {
+        struct {
+            uint32_t reserved0           : 31;
+            volatile uint32_t dig_regulator_en_cal: 1;
+        };
+        volatile uint32_t val;
+    } hp_regulator_cfg;
+
+    union {
+        struct {
+            uint32_t reserved0 : 11;
+            volatile uint32_t last_st   : 7;
+            volatile uint32_t target_st : 7;
+            volatile uint32_t current_st: 7;
+        };
+        volatile uint32_t val;
+    } main_state;
+
+    union {
+        struct {
+            uint32_t reserved0: 13;
+            volatile uint32_t backup_st: 5;
+            volatile uint32_t lp_pwr_st: 5;
+            volatile uint32_t hp_pwr_st: 9;
+        };
+        volatile uint32_t val;
+    } pwr_state;
+
+    union {
+        struct {
+            volatile uint32_t stable_xpd_bbpll : 1;
+            volatile uint32_t stable_xpd_xtal  : 1;
+            volatile uint32_t reserved0        : 13;
+            volatile uint32_t sysclk_slp_sel   : 1;
+            volatile uint32_t sysclk_sel       : 2;
+            volatile uint32_t sysclk_nodiv     : 1;
+            volatile uint32_t icg_sysclk_en    : 1;
+            volatile uint32_t icg_modem_switch : 1;
+            volatile uint32_t icg_modem_code   : 2;
+            volatile uint32_t icg_slp_sel      : 1;
+            volatile uint32_t icg_global_xtal  : 1;
+            volatile uint32_t icg_global_pll   : 1;
+            volatile uint32_t ana_i2c_iso_en   : 1;
+            volatile uint32_t ana_i2c_retention: 1;
+            volatile uint32_t ana_xpd_bb_i2c   : 1;
+            volatile uint32_t ana_xpd_bbpll_i2c: 1;
+            volatile uint32_t ana_xpd_bbpll    : 1;
+            volatile uint32_t ana_xpd_xtal     : 1;
+        };
+        volatile uint32_t val;
+    } clk_state0;
+
+    volatile uint32_t clk_state1;
+    volatile uint32_t clk_state2;
+
+    union {
+        struct {
+            uint32_t reserved0             : 31;
+            volatile uint32_t stable_vdd_spi_pwr_drv: 1;
+        };
+        volatile uint32_t val;
+    } vdd_spi_status;
+
+    uint32_t reserved[0];
+
+    union {
+        struct {
+            volatile uint32_t pmu_date: 31;
+            volatile uint32_t clk_en  : 1;
+        };
+        volatile uint32_t val;
+    } date;
+} pmu_dev_t;
+
+extern pmu_dev_t PMU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pmu_dev_t) == 0x1AC, "Invalid size of pmu_dev_t structure");
+
+_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/pvt_reg.h b/components/soc/esp32c61/register/soc/pvt_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/pvt_reg.h
rename to components/soc/esp32c61/register/soc/pvt_reg.h
diff --git a/components/soc/esp32c61/include/soc/pvt_struct.h b/components/soc/esp32c61/register/soc/pvt_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/pvt_struct.h
rename to components/soc/esp32c61/register/soc/pvt_struct.h
diff --git a/components/soc/esp32c61/register/soc/reg_base.h b/components/soc/esp32c61/register/soc/reg_base.h
new file mode 100644
index 00000000000..67732ccf6a3
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/reg_base.h
@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define DR_REG_UART0_BASE                       0x60000000
+#define DR_REG_UART1_BASE                       0x60001000
+#define DR_REG_MSPI0_BASE                       0x60002000
+#define DR_REG_MSPI1_BASE                       0x60003000
+#define DR_REG_I2C_BASE                         0x60004000
+#define DR_REG_UART2_BASE                       0x60006000
+#define DR_REG_LEDC_BASE                        0x60007000
+#define DR_REG_TIMG0_BASE                       0x60008000
+#define DR_REG_TIMG1_BASE                       0x60009000
+#define DR_REG_SYSTIMER_BASE                    0x6000A000
+#define DR_REG_I2S_BASE                         0x6000C000
+#define DR_REG_SARADC_BASE                      0x6000E000
+#define DR_REG_USB_SERIAL_JTAG_BASE             0x6000F000
+#define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
+#define DR_REG_SOC_ETM_BASE                     0x60013000
+#define DR_REG_PVT_MONITOR_BASE                 0x60019000
+#define DR_REG_PSRAM_MEM_MONITOR_BASE           0x6001A000
+#define DR_REG_AHB_DMA_BASE                     0x60080000
+#define DR_REG_SPI2_BASE                        0x60081000
+#define DR_REG_SHA_BASE                         0x60089000
+#define DR_REG_ECC_MULT_BASE                    0x6008B000
+#define DR_REG_ECDSA_BASE                       0x6008E000
+#define DR_REG_IO_MUX_BASE                      0x60090000
+#define DR_REG_GPIO_BASE                        0x60091000
+#define DR_REG_GPIO_EXT_BASE                    0x60091E00
+#define DR_REG_TCM_MEM_MONITOR_BASE             0x60092000
+#define DR_REG_PAU_BASE                         0x60093000
+#define DR_REG_HP_SYSTEM_BASE                   0x60095000
+#define DR_REG_PCR_BASE                         0x60096000
+#define DR_REG_TEE_BASE                         0x60098000
+#define DR_REG_HP_APM_BASE                      0x60099000
+#define DR_REG_MISC_BASE                        0x6009F000
+#define DR_REG_MODEM0_BASE                      0x600A0000
+#define DR_REG_MODEM1_BASE                      0x600AC000
+#define DR_REG_MODEM_PWR0_BASE                  0x600AD000
+#define DR_REG_MODEM_PWR1_BASE                  0x600AF000
+#define DR_REG_I2C_ANA_MST_BASE                 0x600AF800
+#define DR_REG_PMU_BASE                         0x600B0000
+#define DR_REG_LP_CLKRST_BASE                   0x600B0400
+#define DR_REG_LP_TIMER_BASE                    0x600B0C00
+#define DR_REG_LP_AON_BASE                      0x600B1000
+#define DR_REG_LP_WDT_BASE                      0x600B1C00
+#define DR_REG_LPPERI_BASE                      0x600B2800
+#define DR_REG_LP_ANA_BASE                      0x600B2C00
+#define DR_REG_LP_TEE_BASE                      0x600B3400
+#define DR_REG_LP_APM_BASE                      0x600B3800
+#define DR_REG_LP_IO_MUX_BASE                   0x600B4000
+#define DR_REG_LP_GPIO_BASE                     0x600B4400
+#define DR_REG_EFUSE0_BASE                      0x600B4800
+#define DR_REG_EFUSE1_BASE                      0x600B4C00
+#define DR_REG_TRACE_BASE                       0x600C0000
+#define DR_REG_ASSIST_DEBUG_BASE                0x600C2000
+#define DR_REG_INTPRI_BASE                      0x600C5000
+#define DR_REG_CACHE_BASE                       0x600C8000
+#define DR_REG_CLINT_M_BASE                     0x20000000
+#define PWDET_CONF_REG                          0x600A0808
diff --git a/components/soc/esp32c61/register/soc/sha_reg.h b/components/soc/esp32c61/register/soc/sha_reg.h
new file mode 100644
index 00000000000..4dd7f4a2d9d
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/sha_reg.h
@@ -0,0 +1,177 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SHA_MODE_REG register
+ *  Configures SHA algorithm
+ */
+#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
+/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the SHA algorithm. \\
+ *  0: SHA-1\\
+ *  1: SHA-224\\
+ *  2: SHA-256\\
+ */
+#define SHA_MODE    0x00000007U
+#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
+#define SHA_MODE_V  0x00000007U
+#define SHA_MODE_S  0
+
+/** SHA_T_STRING_REG register
+ *  SHA 512/t configuration register 0.
+ */
+#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
+/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
+ *  Sha t_string (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_STRING    0xFFFFFFFFU
+#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
+#define SHA_T_STRING_V  0xFFFFFFFFU
+#define SHA_T_STRING_S  0
+
+/** SHA_T_LENGTH_REG register
+ *  SHA 512/t configuration register 1.
+ */
+#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
+/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
+ *  Sha t_length (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_LENGTH    0x0000003FU
+#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
+#define SHA_T_LENGTH_V  0x0000003FU
+#define SHA_T_LENGTH_S  0
+
+/** SHA_DMA_BLOCK_NUM_REG register
+ *  Block number register (only effective for DMA-SHA)
+ */
+#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
+/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the DMA-SHA block number.
+ */
+#define SHA_DMA_BLOCK_NUM    0x0000003FU
+#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
+#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
+#define SHA_DMA_BLOCK_NUM_S  0
+
+/** SHA_START_REG register
+ *  Starts the SHA accelerator for Typical SHA operation
+ */
+#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
+/** SHA_START : RO; bitpos: [31:1]; default: 0;
+ *  Write 1 to start Typical SHA calculation.
+ */
+#define SHA_START    0x7FFFFFFFU
+#define SHA_START_M  (SHA_START_V << SHA_START_S)
+#define SHA_START_V  0x7FFFFFFFU
+#define SHA_START_S  1
+
+/** SHA_CONTINUE_REG register
+ *  Continues SHA operation (only effective in Typical SHA mode)
+ */
+#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
+/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
+ *  Write 1 to continue Typical SHA calculation.
+ */
+#define SHA_CONTINUE    0x7FFFFFFFU
+#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
+#define SHA_CONTINUE_V  0x7FFFFFFFU
+#define SHA_CONTINUE_S  1
+
+/** SHA_BUSY_REG register
+ *  Represents if SHA Accelerator is busy or not
+ */
+#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
+/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Represents the states of SHA accelerator. \\
+ *  0: idle\\
+ *  1: busy\\
+ */
+#define SHA_BUSY_STATE    (BIT(0))
+#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
+#define SHA_BUSY_STATE_V  0x00000001U
+#define SHA_BUSY_STATE_S  0
+
+/** SHA_DMA_START_REG register
+ *  Starts the SHA accelerator for DMA-SHA operation
+ */
+#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
+/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
+ *  Write 1 to start DMA-SHA calculation.
+ */
+#define SHA_DMA_START    (BIT(0))
+#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
+#define SHA_DMA_START_V  0x00000001U
+#define SHA_DMA_START_S  0
+
+/** SHA_DMA_CONTINUE_REG register
+ *  Continues SHA operation (only effective in DMA-SHA mode)
+ */
+#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
+/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Write 1 to continue DMA-SHA calculation.
+ */
+#define SHA_DMA_CONTINUE    (BIT(0))
+#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
+#define SHA_DMA_CONTINUE_V  0x00000001U
+#define SHA_DMA_CONTINUE_S  0
+
+/** SHA_CLEAR_IRQ_REG register
+ *  DMA-SHA interrupt clear register
+ */
+#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
+/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
+ *  Write 1 to clear DMA-SHA interrupt.
+ */
+#define SHA_CLEAR_INTERRUPT    (BIT(0))
+#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
+#define SHA_CLEAR_INTERRUPT_V  0x00000001U
+#define SHA_CLEAR_INTERRUPT_S  0
+
+/** SHA_IRQ_ENA_REG register
+ *  DMA-SHA interrupt enable register
+ */
+#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
+/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable DMA-SHA interrupt.
+ */
+#define SHA_INTERRUPT_ENA    (BIT(0))
+#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
+#define SHA_INTERRUPT_ENA_V  0x00000001U
+#define SHA_INTERRUPT_ENA_S  0
+
+/** SHA_DATE_REG register
+ *  Version control register
+ */
+#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
+/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
+ *  Version control register.
+ */
+#define SHA_DATE    0x3FFFFFFFU
+#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
+#define SHA_DATE_V  0x3FFFFFFFU
+#define SHA_DATE_S  0
+
+/** SHA_H_MEM register
+ *  Sha H memory which contains intermediate hash or final hash.
+ */
+#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
+#define SHA_H_MEM_SIZE_BYTES 64
+
+/** SHA_M_MEM register
+ *  Sha M memory which contains message.
+ */
+#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
+#define SHA_M_MEM_SIZE_BYTES 64
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/sha_struct.h b/components/soc/esp32c61/register/soc/sha_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/sha_struct.h
rename to components/soc/esp32c61/register/soc/sha_struct.h
diff --git a/components/soc/esp32c61/include/soc/soc_etm_reg.h b/components/soc/esp32c61/register/soc/soc_etm_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/soc_etm_reg.h
rename to components/soc/esp32c61/register/soc/soc_etm_reg.h
diff --git a/components/soc/esp32c61/include/soc/soc_etm_struct.h b/components/soc/esp32c61/register/soc/soc_etm_struct.h
similarity index 96%
rename from components/soc/esp32c61/include/soc/soc_etm_struct.h
rename to components/soc/esp32c61/register/soc/soc_etm_struct.h
index 464ab7f33e1..2cb80d7c280 100644
--- a/components/soc/esp32c61/include/soc/soc_etm_struct.h
+++ b/components/soc/esp32c61/register/soc/soc_etm_struct.h
@@ -3161,113 +3161,17 @@ typedef union {
 } soc_etm_date_reg_t;
 
 
-typedef struct {
+typedef struct soc_etm_dev_t {
     volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
     volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
     volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
     volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
     volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
     volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
-    volatile soc_etm_chn_evt_id_reg_t ch0_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch0_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch1_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch1_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch2_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch2_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch3_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch3_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch4_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch4_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch5_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch5_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch6_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch6_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch7_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch7_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch8_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch8_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch9_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch9_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch10_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch10_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch11_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch11_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch12_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch12_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch13_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch13_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch14_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch14_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch15_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch15_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch16_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch16_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch17_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch17_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch18_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch18_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch19_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch19_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch20_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch20_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch21_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch21_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch22_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch22_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch23_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch23_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch24_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch24_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch25_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch25_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch26_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch26_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch27_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch27_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch28_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch28_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch29_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch29_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch30_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch30_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch31_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch31_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch32_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch32_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch33_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch33_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch34_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch34_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch35_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch35_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch36_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch36_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch37_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch37_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch38_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch38_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch39_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch39_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch40_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch40_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch41_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch41_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch42_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch42_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch43_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch43_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch44_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch44_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch45_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch45_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch46_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch46_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch47_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch47_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch48_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch48_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch49_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch49_task_id;
+    volatile struct {
+        soc_etm_chn_evt_id_reg_t eid;
+        soc_etm_chn_task_id_reg_t tid;
+    } channel[50];
     volatile soc_etm_evt_st0_reg_t evt_st0;
     volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;
     volatile soc_etm_evt_st1_reg_t evt_st1;
diff --git a/components/soc/esp32c61/include/soc/spi1_mem_reg.h b/components/soc/esp32c61/register/soc/spi1_mem_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/spi1_mem_reg.h
rename to components/soc/esp32c61/register/soc/spi1_mem_reg.h
diff --git a/components/soc/esp32c61/include/soc/spi1_mem_struct.h b/components/soc/esp32c61/register/soc/spi1_mem_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/spi1_mem_struct.h
rename to components/soc/esp32c61/register/soc/spi1_mem_struct.h
diff --git a/components/soc/esp32c61/include/soc/spi_mem_c_reg.h b/components/soc/esp32c61/register/soc/spi_mem_c_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/spi_mem_c_reg.h
rename to components/soc/esp32c61/register/soc/spi_mem_c_reg.h
diff --git a/components/soc/esp32c61/include/soc/spi_mem_c_struct.h b/components/soc/esp32c61/register/soc/spi_mem_c_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/spi_mem_c_struct.h
rename to components/soc/esp32c61/register/soc/spi_mem_c_struct.h
diff --git a/components/soc/esp32c61/register/soc/spi_reg.h b/components/soc/esp32c61/register/soc/spi_reg.h
new file mode 100644
index 00000000000..cce0834349a
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/spi_reg.h
@@ -0,0 +1,2336 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI_CMD_REG register
+ *  Command control register
+ */
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
+/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  Configures the SPI_CLK cycles of SPI CONF state.
+ *  Measurement unit: SPI_CLK clock cycle.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CONF_BITLEN    0x0003FFFFU
+#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
+#define SPI_CONF_BITLEN_V  0x0003FFFFU
+#define SPI_CONF_BITLEN_S  0
+/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
+ *  Configures whether or not to synchronize SPI registers from APB clock domain into
+ *  SPI module clock domain. \\
+ *  0: Not synchronize \\
+ *  1: Synchronize \\
+ *  This bit is only used in SPI master transfer.
+ */
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
+#define SPI_UPDATE_V  0x00000001U
+#define SPI_UPDATE_S  23
+/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable user-defined command. \\
+ *  0: Not enable \\
+ *  1: Enable \\
+ *  An SPI operation will be triggered when the bit is set. This bit will be cleared
+ *  once the operation is done. Can not be changed by CONF_buf.
+ */
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
+#define SPI_USR_V  0x00000001U
+#define SPI_USR_S  24
+
+/** SPI_ADDR_REG register
+ *  Address value register
+ */
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
+/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the address to slave.
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_S  0
+
+/** SPI_CTRL_REG register
+ *  SPI control register
+ */
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
+/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to output the FSPI bus signals in DUMMY state. \\
+ *  0: Not output \\
+ *  1: Output \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
+#define SPI_DUMMY_OUT_V  0x00000001U
+#define SPI_DUMMY_OUT_S  3
+/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable 2-bit mode during address (ADDR) state.\\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
+#define SPI_FADDR_DUAL_V  0x00000001U
+#define SPI_FADDR_DUAL_S  5
+/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable 4-bit mode during address (ADDR) state. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
+#define SPI_FADDR_QUAD_V  0x00000001U
+#define SPI_FADDR_QUAD_S  6
+/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable 8-bit mode during address (ADDR) state. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FADDR_OCT    (BIT(7))
+#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
+#define SPI_FADDR_OCT_V  0x00000001U
+#define SPI_FADDR_OCT_S  7
+/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable 2-bit mode during command (CMD) state. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
+#define SPI_FCMD_DUAL_V  0x00000001U
+#define SPI_FCMD_DUAL_S  8
+/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable 4-bit mode during command (CMD) state. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
+#define SPI_FCMD_QUAD_V  0x00000001U
+#define SPI_FCMD_QUAD_S  9
+/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable 8-bit mode during command (CMD) state. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FCMD_OCT    (BIT(10))
+#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
+#define SPI_FCMD_OCT_V  0x00000001U
+#define SPI_FCMD_OCT_S  10
+/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read
+ *  operations. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
+#define SPI_FREAD_DUAL_V  0x00000001U
+#define SPI_FREAD_DUAL_S  14
+/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read
+ *  operations. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
+#define SPI_FREAD_QUAD_V  0x00000001U
+#define SPI_FREAD_QUAD_S  15
+/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read
+ *  operations. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FREAD_OCT    (BIT(16))
+#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
+#define SPI_FREAD_OCT_V  0x00000001U
+#define SPI_FREAD_OCT_S  16
+/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  Configures MISO line polarity. \\
+ *  0: Low \\
+ *  1: High \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
+#define SPI_Q_POL_V  0x00000001U
+#define SPI_Q_POL_S  18
+/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
+ *  Configures MOSI line polarity. \\
+ *  0: Low \\
+ *  1: High \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
+#define SPI_D_POL_V  0x00000001U
+#define SPI_D_POL_S  19
+/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
+ *  Configures SPI_HOLD output value when SPI is in idle. \\
+ *  0: Output low \\
+ *  1: Output high \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
+#define SPI_HOLD_POL_V  0x00000001U
+#define SPI_HOLD_POL_S  20
+/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
+ *  Configures the output value of write-protect signal when SPI is in idle. \\
+ *  0: Output low \\
+ *  1: Output high \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
+#define SPI_WP_POL_V  0x00000001U
+#define SPI_WP_POL_S  21
+/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
+ *  Configures the bit order in read-data (MISO) state. \\
+ *  0: MSB first \\
+ *  1: LSB first \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_RD_BIT_ORDER    0x00000003U
+#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
+#define SPI_RD_BIT_ORDER_V  0x00000003U
+#define SPI_RD_BIT_ORDER_S  23
+/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
+ *  Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI)
+ *  states. \\
+ *  0: MSB first \\
+ *  1: LSB first \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_WR_BIT_ORDER    0x00000003U
+#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
+#define SPI_WR_BIT_ORDER_V  0x00000003U
+#define SPI_WR_BIT_ORDER_S  25
+
+/** SPI_CLOCK_REG register
+ *  SPI clock control register
+ */
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
+/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
+ *  In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it
+ *  must be 0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_L    0x0000003FU
+#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
+#define SPI_CLKCNT_L_V  0x0000003FU
+#define SPI_CLKCNT_L_S  0
+/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
+ *  Configures the duty cycle of SPI_CLK (high level) in master transfer.
+ *  It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1).
+ *  floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it
+ *  must be 0. \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_H    0x0000003FU
+#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
+#define SPI_CLKCNT_H_V  0x0000003FU
+#define SPI_CLKCNT_H_S  6
+/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
+ *  Configures the divider of SPI_CLK in master transfer.
+ *  SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N +
+ *  1). \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_N    0x0000003FU
+#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
+#define SPI_CLKCNT_N_V  0x0000003FU
+#define SPI_CLKCNT_N_S  12
+/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
+ *  Configures the pre-divider of SPI_CLK in master transfer.
+ *  Can be configured in CONF state.
+ */
+#define SPI_CLKDIV_PRE    0x0000000FU
+#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
+#define SPI_CLKDIV_PRE_V  0x0000000FU
+#define SPI_CLKDIV_PRE_S  18
+/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
+ *  Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\
+ *  0: SPI_CLK is divided from APB_CLK.\\
+ *  1: SPI_CLK is equal to APB_CLK.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
+#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_CLK_EQU_SYSCLK_S  31
+
+/** SPI_USER_REG register
+ *  SPI USER control register
+ */
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
+/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable full-duplex communication. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
+#define SPI_DOUTDIN_V  0x00000001U
+#define SPI_DOUTDIN_S  0
+/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable QPI mode. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  This configuration is applicable when the SPI controller works as master or slave.
+ *  Can be configured in CONF state.
+ */
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
+#define SPI_QPI_MODE_V  0x00000001U
+#define SPI_QPI_MODE_S  3
+/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0;
+ *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+ *  Can be configured in CONF state.
+ */
+#define SPI_OPI_MODE    (BIT(4))
+#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
+#define SPI_OPI_MODE_V  0x00000001U
+#define SPI_OPI_MODE_S  4
+/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to change the polarity of TSCK in slave transfer. \\
+ *  0: TSCK = SPI_CK_I \\
+ *  1: TSCK = !SPI_CK_I \\
+ */
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
+#define SPI_TSCK_I_EDGE_V  0x00000001U
+#define SPI_TSCK_I_EDGE_S  5
+/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
+ *  Configures whether or not to keep SPI CS low when SPI is in DONE state. \\
+ *  0: Not keep low \\
+ *  1: Keep low \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
+#define SPI_CS_HOLD_V  0x00000001U
+#define SPI_CS_HOLD_S  6
+/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
+ *  Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
+#define SPI_CS_SETUP_V  0x00000001U
+#define SPI_CS_SETUP_S  7
+/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to change the polarity of RSCK in slave transfer. \\
+ *  0: RSCK = !SPI_CK_I \\
+ *  1: RSCK = SPI_CK_I \\
+ */
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
+#define SPI_RSCK_I_EDGE_V  0x00000001U
+#define SPI_RSCK_I_EDGE_S  8
+/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  Configures SPI clock mode together with SPI_CK_IDLE_EDGE.
+ *  Can be configured in CONF state. For more information, see Section <a href="GP-SPI2
+ *  master clock control">link</a>.
+ */
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
+#define SPI_CK_OUT_EDGE_V  0x00000001U
+#define SPI_CK_OUT_EDGE_S  9
+/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable the 2-bit mode of read-data phase in write
+ *  operations.\\
+ *  0: Not enable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
+#define SPI_FWRITE_DUAL_V  0x00000001U
+#define SPI_FWRITE_DUAL_S  12
+/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable the 4-bit mode of read-data phase in write
+ *  operations. \\
+ *  0: Not enable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
+#define SPI_FWRITE_QUAD_V  0x00000001U
+#define SPI_FWRITE_QUAD_S  13
+/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0;
+ *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_OCT    (BIT(14))
+#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
+#define SPI_FWRITE_OCT_V  0x00000001U
+#define SPI_FWRITE_OCT_S  14
+/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable the CONF state for the next transaction
+ *  (segment) in a configurable segmented transfer. \\
+ *  0: this transfer will end after the current transaction (segment) is finished. Or
+ *  this is not a configurable segmented transfer. \\
+ *  1: this configurable segmented transfer will continue its next transaction
+ *  (segment). \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
+#define SPI_USR_CONF_NXT_V  0x00000001U
+#define SPI_USR_CONF_NXT_S  15
+/** SPI_SIO : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable 3-line half-duplex communication, where MOSI
+ *  and MISO signals share the same pin.\\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
+#define SPI_SIO_V  0x00000001U
+#define SPI_SIO_S  17
+/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable high part mode, i.e., only access to high part
+ *  of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
+#define SPI_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI_USR_MISO_HIGHPART_S  24
+/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable high part mode, i.e., only access to high part
+ *  of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
+#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI_USR_MOSI_HIGHPART_S  25
+/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to disable SPI clock in DUMMY state. \\
+ *  0: Not disable \\
+ *  1: Disable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
+#define SPI_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_USR_DUMMY_IDLE_S  26
+/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable the write-data (DOUT) state of an operation. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
+#define SPI_USR_MOSI_V  0x00000001U
+#define SPI_USR_MOSI_S  27
+/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable the read-data (DIN) state of an operation. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
+#define SPI_USR_MISO_V  0x00000001U
+#define SPI_USR_MISO_S  28
+/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable the DUMMY state of an operation. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
+#define SPI_USR_DUMMY_V  0x00000001U
+#define SPI_USR_DUMMY_S  29
+/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
+ *  Configures whether or not to enable the address (ADDR) state of an operation. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
+#define SPI_USR_ADDR_V  0x00000001U
+#define SPI_USR_ADDR_S  30
+/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+ *  Configures whether or not to enable the command (CMD) state of an operation. \\
+ *  0: Disable \\
+ *  1: Enable \\
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
+#define SPI_USR_COMMAND_V  0x00000001U
+#define SPI_USR_COMMAND_S  31
+
+/** SPI_USER1_REG register
+ *  SPI USER control register 1
+ */
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
+/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
+ *  Configures the length of DUMMY state.
+ *  Measurement unit: SPI_CLK clock cycles.\\
+ *  This value is (the expected cycle number - 1). Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
+#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
+ *  Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error
+ *  occurs in master full-/half-duplex transfers. \\
+ *  0: Not end \\
+ *  1: End \\
+ */
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
+#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
+ *  Configures the length of prepare (PREP) state.
+ *  Measurement unit: SPI_CLK clock cycles.\\
+ *  This value is equal to the expected cycles - 1. This field is used together with
+ *  SPI_CS_SETUP. Can be configured in CONF state.
+ */
+#define SPI_CS_SETUP_TIME    0x0000001FU
+#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
+#define SPI_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_CS_SETUP_TIME_S  17
+/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
+ *  Configures the delay cycles of CS pin.
+ *  Measurement unit: SPI_CLK clock cycles. \\
+ *  This field is used together with SPI_CS_HOLD. Can be configured in CONF state.
+ */
+#define SPI_CS_HOLD_TIME    0x0000001FU
+#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
+#define SPI_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_CS_HOLD_TIME_S  22
+/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
+ *  Configures the bit length in address state.
+ *  This value is (expected bit number - 1). Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR_BITLEN    0x0000001FU
+#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
+#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
+#define SPI_USR_ADDR_BITLEN_S  27
+
+/** SPI_USER2_REG register
+ *  SPI USER control register 2
+ */
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
+/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the command value.
+ *  Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
+#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_S  0
+/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
+ *  Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty
+ *  error occurs in master full-/half-duplex transfers. \\
+ *  0: Not end \\
+ *  1: End \\
+ */
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  Configures the bit length of command state.
+ *  This value is (expected bit number - 1). Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
+#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_S  28
+
+/** SPI_MS_DLEN_REG register
+ *  SPI data bit length control register
+ */
+#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
+/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  Configures the data bit length of SPI transfer in DMA-controlled master transfer or
+ *  in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer
+ *  in DMA-controlled slave transfer.
+ *  This value shall be (expected bit_num - 1). Can be configured in CONF state.
+ */
+#define SPI_MS_DATA_BITLEN    0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
+#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_S  0
+
+/** SPI_MISC_REG register
+ *  SPI misc register
+ */
+#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
+/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to disable SPI_CS$n pin.\\
+ *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+ *  1: Disable SPI_CS$n pin.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
+#define SPI_CS0_DIS_V  0x00000001U
+#define SPI_CS0_DIS_S  0
+/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
+ *  Configures whether or not to disable SPI_CS$n pin.\\
+ *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+ *  1: Disable SPI_CS$n pin.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
+#define SPI_CS1_DIS_V  0x00000001U
+#define SPI_CS1_DIS_S  1
+/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to disable SPI_CS$n pin.\\
+ *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+ *  1: Disable SPI_CS$n pin.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
+#define SPI_CS2_DIS_V  0x00000001U
+#define SPI_CS2_DIS_S  2
+/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to disable SPI_CS$n pin.\\
+ *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+ *  1: Disable SPI_CS$n pin.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
+#define SPI_CS3_DIS_V  0x00000001U
+#define SPI_CS3_DIS_S  3
+/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
+ *  Configures whether or not to disable SPI_CS$n pin.\\
+ *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+ *  1: Disable SPI_CS$n pin.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
+#define SPI_CS4_DIS_V  0x00000001U
+#define SPI_CS4_DIS_S  4
+/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
+ *  Configures whether or not to disable SPI_CS$n pin.\\
+ *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+ *  1: Disable SPI_CS$n pin.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
+#define SPI_CS5_DIS_V  0x00000001U
+#define SPI_CS5_DIS_S  5
+/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to disable SPI_CLK output.\\
+ *  0: Enable\\
+ *  1: Disable\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
+#define SPI_CK_DIS_V  0x00000001U
+#define SPI_CK_DIS_S  6
+/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
+ *  Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\
+ *  0: SPI_CS$n is low active.\\
+ *  1: SPI_CS$n is high active.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_MASTER_CS_POL    0x0000003FU
+#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
+#define SPI_MASTER_CS_POL_V  0x0000003FU
+#define SPI_MASTER_CS_POL_S  7
+/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0;
+ *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+ *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+ */
+#define SPI_CLK_DATA_DTR_EN    (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
+#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
+#define SPI_CLK_DATA_DTR_EN_S  16
+/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0;
+ *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+ *  Can be configured in CONF state.
+ */
+#define SPI_DATA_DTR_EN    (BIT(17))
+#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
+#define SPI_DATA_DTR_EN_V  0x00000001U
+#define SPI_DATA_DTR_EN_S  17
+/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+#define SPI_ADDR_DTR_EN    (BIT(18))
+#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
+#define SPI_ADDR_DTR_EN_V  0x00000001U
+#define SPI_ADDR_DTR_EN_S  18
+/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+ *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CMD_DTR_EN    (BIT(19))
+#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
+#define SPI_CMD_DTR_EN_V  0x00000001U
+#define SPI_CMD_DTR_EN_S  19
+/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not invert SPI slave input CS polarity.\\
+ *  0: Not change\\
+ *  1: Invert\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
+#define SPI_SLAVE_CS_POL_V  0x00000001U
+#define SPI_SLAVE_CS_POL_S  23
+/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0;
+ *  The default value of spi_dqs. Can be configured in CONF state.
+ */
+#define SPI_DQS_IDLE_EDGE    (BIT(24))
+#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
+#define SPI_DQS_IDLE_EDGE_V  0x00000001U
+#define SPI_DQS_IDLE_EDGE_S  24
+/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
+ *  Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\
+ *  0: Low\\
+ *  1: High\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
+#define SPI_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_CK_IDLE_EDGE_S  29
+/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
+ *  Configures whether or not to keep the SPI_CS line low.\\
+ *  0: Not keep low\\
+ *  1: Keep low\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
+#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_CS_KEEP_ACTIVE_S  30
+/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
+ *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+ *  spi quad input swap disable. Can be configured in CONF state.
+ */
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+
+/** SPI_DIN_MODE_REG register
+ *  SPI input delay mode configuration
+ */
+#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
+/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Configures the input mode for FSPID signal.\\
+ *  0: Input without delay\\
+ *  1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\
+ *  2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  rising edge cycle\\
+ *  3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  falling edge cycle\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DIN0_MODE    0x00000003U
+#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
+#define SPI_DIN0_MODE_V  0x00000003U
+#define SPI_DIN0_MODE_S  0
+/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the input mode for FSPIQ signal.\\
+ *  0: Input without delay\\
+ *  1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\
+ *  2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  rising edge cycle\\
+ *  3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  falling edge cycle\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DIN1_MODE    0x00000003U
+#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
+#define SPI_DIN1_MODE_V  0x00000003U
+#define SPI_DIN1_MODE_S  2
+/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  Configures the input mode for FSPIWP signal.\\
+ *  0: Input without delay\\
+ *  1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\
+ *  2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  rising edge cycle\\
+ *  3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  falling edge cycle\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DIN2_MODE    0x00000003U
+#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
+#define SPI_DIN2_MODE_V  0x00000003U
+#define SPI_DIN2_MODE_S  4
+/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures the input mode for FSPIHD signal.\\
+ *  0: Input without delay\\
+ *  1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\
+ *  2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  rising edge cycle\\
+ *  3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  falling edge cycle\\
+ *  Can be configured in CONF state.
+ *
+ */
+#define SPI_DIN3_MODE    0x00000003U
+#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
+#define SPI_DIN3_MODE_V  0x00000003U
+#define SPI_DIN3_MODE_S  6
+/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN4_MODE    0x00000003U
+#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
+#define SPI_DIN4_MODE_V  0x00000003U
+#define SPI_DIN4_MODE_S  8
+/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN5_MODE    0x00000003U
+#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
+#define SPI_DIN5_MODE_V  0x00000003U
+#define SPI_DIN5_MODE_S  10
+/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN6_MODE    0x00000003U
+#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
+#define SPI_DIN6_MODE_V  0x00000003U
+#define SPI_DIN6_MODE_S  12
+/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN7_MODE    0x00000003U
+#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
+#define SPI_DIN7_MODE_V  0x00000003U
+#define SPI_DIN7_MODE_S  14
+/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing
+ *  module.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
+#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+
+/** SPI_DIN_NUM_REG register
+ *  SPI input delay number configuration
+ */
+#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
+/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\
+ *  0: Delayed by 1 clock cycle\\
+ *  1: Delayed by 2 clock cycles\\
+ *  2: Delayed by 3 clock cycles\\
+ *  3: Delayed by 4 clock cycles\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DIN0_NUM    0x00000003U
+#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
+#define SPI_DIN0_NUM_V  0x00000003U
+#define SPI_DIN0_NUM_S  0
+/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\
+ *  0: Delayed by 1 clock cycle\\
+ *  1: Delayed by 2 clock cycles\\
+ *  2: Delayed by 3 clock cycles\\
+ *  3: Delayed by 4 clock cycles\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DIN1_NUM    0x00000003U
+#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
+#define SPI_DIN1_NUM_V  0x00000003U
+#define SPI_DIN1_NUM_S  2
+/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  Configures the delays to input signal FSPIWP based on the setting of
+ *  SPI_DIN2_MODE.\\
+ *  0: Delayed by 1 clock cycle\\
+ *  1: Delayed by 2 clock cycles\\
+ *  2: Delayed by 3 clock cycles\\
+ *  3: Delayed by 4 clock cycles\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DIN2_NUM    0x00000003U
+#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
+#define SPI_DIN2_NUM_V  0x00000003U
+#define SPI_DIN2_NUM_S  4
+/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  Configures the delays to input signal FSPIHD based on the setting of
+ *  SPI_DIN3_MODE.\\
+ *  0: Delayed by 1 clock cycle\\
+ *  1: Delayed by 2 clock cycles\\
+ *  2: Delayed by 3 clock cycles\\
+ *  3: Delayed by 4 clock cycles\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DIN3_NUM    0x00000003U
+#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
+#define SPI_DIN3_NUM_V  0x00000003U
+#define SPI_DIN3_NUM_S  6
+/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN4_NUM    0x00000003U
+#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
+#define SPI_DIN4_NUM_V  0x00000003U
+#define SPI_DIN4_NUM_S  8
+/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN5_NUM    0x00000003U
+#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
+#define SPI_DIN5_NUM_V  0x00000003U
+#define SPI_DIN5_NUM_S  10
+/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN6_NUM    0x00000003U
+#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
+#define SPI_DIN6_NUM_V  0x00000003U
+#define SPI_DIN6_NUM_S  12
+/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN7_NUM    0x00000003U
+#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
+#define SPI_DIN7_NUM_V  0x00000003U
+#define SPI_DIN7_NUM_S  14
+
+/** SPI_DOUT_MODE_REG register
+ *  SPI output delay mode configuration
+ */
+#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
+/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  Configures the output mode for FSPID signal.\\
+ *  0: Output without delay\\
+ *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
+#define SPI_DOUT0_MODE_V  0x00000001U
+#define SPI_DOUT0_MODE_S  0
+/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  Configures the output mode for FSPIQ signal.\\
+ *  0: Output without delay\\
+ *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
+#define SPI_DOUT1_MODE_V  0x00000001U
+#define SPI_DOUT1_MODE_S  1
+/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  Configures the output mode for FSPIWP signal.\\
+ *  0: Output without delay\\
+ *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
+#define SPI_DOUT2_MODE_V  0x00000001U
+#define SPI_DOUT2_MODE_S  2
+/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  Configures the output mode for FSPIHD signal.\\
+ *  0: Output without delay\\
+ *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
+#define SPI_DOUT3_MODE_V  0x00000001U
+#define SPI_DOUT3_MODE_S  3
+/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT4_MODE    (BIT(4))
+#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
+#define SPI_DOUT4_MODE_V  0x00000001U
+#define SPI_DOUT4_MODE_S  4
+/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT5_MODE    (BIT(5))
+#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
+#define SPI_DOUT5_MODE_V  0x00000001U
+#define SPI_DOUT5_MODE_S  5
+/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT6_MODE    (BIT(6))
+#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
+#define SPI_DOUT6_MODE_V  0x00000001U
+#define SPI_DOUT6_MODE_S  6
+/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT7_MODE    (BIT(7))
+#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
+#define SPI_DOUT7_MODE_V  0x00000001U
+#define SPI_DOUT7_MODE_S  7
+/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0;
+ *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+ *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_D_DQS_MODE    (BIT(8))
+#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
+#define SPI_D_DQS_MODE_V  0x00000001U
+#define SPI_D_DQS_MODE_S  8
+
+/** SPI_DMA_CONF_REG register
+ *  SPI DMA control register
+ */
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
+/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Represents whether or not the DMA TX FIFO is ready for sending data.\\
+ *  0: Ready\\
+ *  1: Not ready\\
+ */
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
+/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
+ *  Represents whether or not the DMA RX FIFO is ready for receiving data.\\
+ *  0: Ready\\
+ *  1: Not ready\\
+ */
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
+#define SPI_DMA_INFIFO_FULL_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_S  1
+/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable DMA-controlled segmented transfer in slave
+ *  half-duplex communication.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ */
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  In slave segmented transfer, if the size of the DMA RX buffer is smaller than the
+ *  size of the received data, \\1: the data in all the following Wr_DMA transactions
+ *  will not be received\\ 0: the data in this Wr_DMA transaction will not be received,
+ *  but in the following transactions,\\
+ *
+ *  - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions
+ *  will be received.
+ *  - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will
+ *  not be received.
+ */
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  In slave segmented transfer, if the size of the DMA TX buffer is smaller than the
+ *  size of the transmitted data,\\
+ *  1: the data in the following transactions will not be updated, i.e. the old data is
+ *  transmitted repeatedly.\\
+ *  0: the data in this transaction will not be updated. But in the following
+ *  transactions,\\
+ *
+ *  - if new data is filled in DMA TX FIFO, new data will be transmitted.
+ *  - if no new data is filled in DMA TX FIFO, no new data will be transmitted.
+ */
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
+ *  1: In a DAM-controlled transfer, if the bit number of transferred data is equal to
+ *  (SPI_MS_DATA_BITLEN + 1), then GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW will be set by
+ *  hardware. 0: GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW is set by SPI_TRANS_DONE_INT event in
+ *  a single transfer, or by an SPI_DMA_SEG_TRANS_DONE_INT event in a segmented
+ *  transfer.
+ */
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
+#define SPI_RX_EOF_EN_V  0x00000001U
+#define SPI_RX_EOF_EN_S  21
+/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable DMA-controlled receive data transfer.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ */
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
+#define SPI_DMA_RX_ENA_V  0x00000001U
+#define SPI_DMA_RX_ENA_S  27
+/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable DMA-controlled send data transfer.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ */
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
+#define SPI_DMA_TX_ENA_V  0x00000001U
+#define SPI_DMA_TX_ENA_S  28
+/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
+ *  Configures whether or not to reset spi_rx_afifo as shown in Figure <a
+ *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
+ *  href="fig:spi-slave-data-flow-control">link</a>.\\
+ *  0: Not reset\\
+ *  1: Reset\\
+ *  spi_rx_afifo is used to receive data in SPI master and slave transfer.
+ */
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
+#define SPI_RX_AFIFO_RST_V  0x00000001U
+#define SPI_RX_AFIFO_RST_S  29
+/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
+ *  Configures whether or not to reset buf_tx_afifo as shown in Figure <a
+ *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
+ *  href="fig:spi-slave-data-flow-control">link</a>.\\
+ *  0: Not reset\\
+ *  1: Reset\\
+ *  buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer.
+ */
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
+#define SPI_BUF_AFIFO_RST_V  0x00000001U
+#define SPI_BUF_AFIFO_RST_S  30
+/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
+ *  Configures whether or not to reset dma_tx_afifo as shown in Figure <a
+ *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
+ *  href="fig:spi-slave-data-flow-control">link</a>.\\
+ *  0: Not reset\\
+ *  1: Reset\\
+ *  dma_tx_afifo is used to send data out in DMA-controlled slave transfer.
+ */
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
+#define SPI_DMA_AFIFO_RST_V  0x00000001U
+#define SPI_DMA_AFIFO_RST_S  31
+
+/** SPI_DMA_INT_ENA_REG register
+ *  SPI interrupt enable register
+ */
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable SPI_SLV_EX_QPI_INT interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable SPI_SLV_EN_QPI_INT interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable SPI_SLV_CMD7_INT interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
+#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable SPI_SLV_CMD8_INT interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
+#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable SPI_SLV_CMD9_INT interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
+#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable SPI_SLV_CMDA_INT interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
+#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to enable SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to enable SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Write 1 to enable SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Write 1 to enable SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Write 1 to enable SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
+#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Write 1 to enable SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Write 1 to enable SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Write 1 to enable SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Write 1 to enable SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Write 1 to enable SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  Write 1 to enable SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
+#define SPI_APP2_INT_ENA_V  0x00000001U
+#define SPI_APP2_INT_ENA_S  19
+/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  Write 1 to enable SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
+#define SPI_APP1_INT_ENA_V  0x00000001U
+#define SPI_APP1_INT_ENA_S  20
+
+/** SPI_DMA_INT_CLR_REG register
+ *  SPI interrupt clear register
+ */
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear SPI_SLV_EX_QPI_INT interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear SPI_SLV_EN_QPI_INT interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear SPI_SLV_CMD7_INT interrupt.
+ */
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
+#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear SPI_SLV_CMD8_INT interrupt.
+ */
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
+#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear SPI_SLV_CMD9_INT interrupt.
+ */
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
+#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear SPI_SLV_CMDA_INT interrupt.
+ */
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
+#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Write 1 to clear SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Write 1 to clear SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Write 1 to clear SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
+#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Write 1 to clear SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Write 1 to clear SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Write 1 to clear SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Write 1 to clear SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Write 1 to clear SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
+#define SPI_APP2_INT_CLR_V  0x00000001U
+#define SPI_APP2_INT_CLR_S  19
+/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  Write 1 to clear SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
+#define SPI_APP1_INT_CLR_V  0x00000001U
+#define SPI_APP1_INT_CLR_S  20
+
+/** SPI_DMA_INT_RAW_REG register
+ *  SPI interrupt raw register
+ */
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of SPI_SLV_EX_QPI_INT interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of SPI_SLV_EN_QPI_INT interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of SPI_SLV_CMD7_INT interrupt.
+ */
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
+#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of SPI_SLV_CMD8_INT interrupt.
+ */
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
+#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of SPI_SLV_CMD9_INT interrupt.
+ */
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
+#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of SPI_SLV_CMDA_INT interrupt.
+ */
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
+#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt status of SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
+#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+ *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+ *  bigger than 63. 0: Others.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw interrupt status of SPI_APP2_INT interrupt. The value is only controlled by
+ *  the application.
+ */
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
+#define SPI_APP2_INT_RAW_V  0x00000001U
+#define SPI_APP2_INT_RAW_S  19
+/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw interrupt status of SPI_APP1_INT interrupt. The value is only controlled by
+ *  the application.
+ */
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
+#define SPI_APP1_INT_RAW_V  0x00000001U
+#define SPI_APP1_INT_RAW_S  20
+
+/** SPI_DMA_INT_ST_REG register
+ *  SPI interrupt status register
+ */
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The interrupt status of SPI_SLV_EX_QPI_INT interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
+#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The interrupt status of SPI_SLV_EN_QPI_INT interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
+#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The interrupt status of SPI_SLV_CMD7_INT interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
+#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ST_S  4
+/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The interrupt status of SPI_SLV_CMD8_INT interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
+#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ST_S  5
+/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The interrupt status of SPI_SLV_CMD9_INT interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
+#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ST_S  6
+/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The interrupt status of SPI_SLV_CMDA_INT interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
+#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ST_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The interrupt status of SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
+#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ST_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The interrupt status of SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
+#define SPI_APP2_INT_ST_V  0x00000001U
+#define SPI_APP2_INT_ST_S  19
+/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The interrupt status of SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
+#define SPI_APP1_INT_ST_V  0x00000001U
+#define SPI_APP1_INT_ST_S  20
+
+/** SPI_DMA_INT_SET_REG register
+ *  SPI interrupt software set register
+ */
+#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
+ *  Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
+ *  Write 1 to set SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
+/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
+ *  Write 1 to set SPI_SLV_EX_QPI_INT interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
+#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_SET_S  2
+/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
+ *  Write 1 to set SPI_SLV_EN_QPI_INT interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
+#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_SET_S  3
+/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
+ *  Write 1 to set SPI_SLV_CMD7_INT interrupt.
+ */
+#define SPI_SLV_CMD7_INT_SET    (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
+#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD7_INT_SET_S  4
+/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
+ *  Write 1 to set SPI_SLV_CMD8_INT interrupt.
+ */
+#define SPI_SLV_CMD8_INT_SET    (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
+#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD8_INT_SET_S  5
+/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
+ *  Write 1 to set SPI_SLV_CMD9_INT interrupt.
+ */
+#define SPI_SLV_CMD9_INT_SET    (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
+#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD9_INT_SET_S  6
+/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
+ *  Write 1 to set SPI_SLV_CMDA_INT interrupt.
+ */
+#define SPI_SLV_CMDA_INT_SET    (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
+#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
+#define SPI_SLV_CMDA_INT_SET_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
+ *  Write 1 to set SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
+#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
+ *  Write 1 to set SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
+#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
+ *  Write 1 to set SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
+#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
+ *  Write 1 to set SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
+#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
+ *  Write 1 to set SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
+#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_TRANS_DONE_INT_SET_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
+ *  Write 1 to set SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
+/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
+ *  Write 1 to set SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
+#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
+ *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
+ *  Write 1 to set SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
+#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_SET_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
+ *  Write 1 to set SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
+ *  Write 1 to set SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
+ *  Write 1 to set SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_SET    (BIT(19))
+#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
+#define SPI_APP2_INT_SET_V  0x00000001U
+#define SPI_APP2_INT_SET_S  19
+/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
+ *  Write 1 to set SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_SET    (BIT(20))
+#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
+#define SPI_APP1_INT_SET_V  0x00000001U
+#define SPI_APP1_INT_SET_S  20
+
+/** SPI_W0_REG register
+ *  SPI CPU-controlled buffer0
+ */
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
+/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF0    0xFFFFFFFFU
+#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
+#define SPI_BUF0_V  0xFFFFFFFFU
+#define SPI_BUF0_S  0
+
+/** SPI_W1_REG register
+ *  SPI CPU-controlled buffer1
+ */
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
+/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF1    0xFFFFFFFFU
+#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
+#define SPI_BUF1_V  0xFFFFFFFFU
+#define SPI_BUF1_S  0
+
+/** SPI_W2_REG register
+ *  SPI CPU-controlled buffer2
+ */
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
+/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF2    0xFFFFFFFFU
+#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
+#define SPI_BUF2_V  0xFFFFFFFFU
+#define SPI_BUF2_S  0
+
+/** SPI_W3_REG register
+ *  SPI CPU-controlled buffer3
+ */
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
+/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF3    0xFFFFFFFFU
+#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
+#define SPI_BUF3_V  0xFFFFFFFFU
+#define SPI_BUF3_S  0
+
+/** SPI_W4_REG register
+ *  SPI CPU-controlled buffer4
+ */
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
+/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF4    0xFFFFFFFFU
+#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
+#define SPI_BUF4_V  0xFFFFFFFFU
+#define SPI_BUF4_S  0
+
+/** SPI_W5_REG register
+ *  SPI CPU-controlled buffer5
+ */
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
+/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF5    0xFFFFFFFFU
+#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
+#define SPI_BUF5_V  0xFFFFFFFFU
+#define SPI_BUF5_S  0
+
+/** SPI_W6_REG register
+ *  SPI CPU-controlled buffer6
+ */
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
+/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF6    0xFFFFFFFFU
+#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
+#define SPI_BUF6_V  0xFFFFFFFFU
+#define SPI_BUF6_S  0
+
+/** SPI_W7_REG register
+ *  SPI CPU-controlled buffer7
+ */
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
+/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF7    0xFFFFFFFFU
+#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
+#define SPI_BUF7_V  0xFFFFFFFFU
+#define SPI_BUF7_S  0
+
+/** SPI_W8_REG register
+ *  SPI CPU-controlled buffer8
+ */
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
+/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF8    0xFFFFFFFFU
+#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
+#define SPI_BUF8_V  0xFFFFFFFFU
+#define SPI_BUF8_S  0
+
+/** SPI_W9_REG register
+ *  SPI CPU-controlled buffer9
+ */
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
+/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF9    0xFFFFFFFFU
+#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
+#define SPI_BUF9_V  0xFFFFFFFFU
+#define SPI_BUF9_S  0
+
+/** SPI_W10_REG register
+ *  SPI CPU-controlled buffer10
+ */
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
+/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF10    0xFFFFFFFFU
+#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
+#define SPI_BUF10_V  0xFFFFFFFFU
+#define SPI_BUF10_S  0
+
+/** SPI_W11_REG register
+ *  SPI CPU-controlled buffer11
+ */
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
+/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF11    0xFFFFFFFFU
+#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
+#define SPI_BUF11_V  0xFFFFFFFFU
+#define SPI_BUF11_S  0
+
+/** SPI_W12_REG register
+ *  SPI CPU-controlled buffer12
+ */
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
+/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF12    0xFFFFFFFFU
+#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
+#define SPI_BUF12_V  0xFFFFFFFFU
+#define SPI_BUF12_S  0
+
+/** SPI_W13_REG register
+ *  SPI CPU-controlled buffer13
+ */
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
+/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF13    0xFFFFFFFFU
+#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
+#define SPI_BUF13_V  0xFFFFFFFFU
+#define SPI_BUF13_S  0
+
+/** SPI_W14_REG register
+ *  SPI CPU-controlled buffer14
+ */
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
+/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF14    0xFFFFFFFFU
+#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
+#define SPI_BUF14_V  0xFFFFFFFFU
+#define SPI_BUF14_S  0
+
+/** SPI_W15_REG register
+ *  SPI CPU-controlled buffer15
+ */
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
+/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  32-bit data buffer $n.
+ */
+#define SPI_BUF15    0xFFFFFFFFU
+#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
+#define SPI_BUF15_V  0xFFFFFFFFU
+#define SPI_BUF15_S  0
+
+/** SPI_SLAVE_REG register
+ *  SPI slave control register
+ */
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
+/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Configures SPI clock mode.\\
+ *  0: SPI clock is off when CS becomes inactive.\\
+ *  1: SPI clock is delayed one cycle after CS becomes inactive.\\
+ *  2: SPI clock is delayed two cycles after CS becomes inactive.\\
+ *  3: SPI clock is always on.\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_CLK_MODE    0x00000003U
+#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
+#define SPI_CLK_MODE_V  0x00000003U
+#define SPI_CLK_MODE_S  0
+/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
+ *  Configure clock mode.\\
+ *  0: Support SPI clock mode 0 or 2. See Table <a
+ *  href="table:clock_pol_slave">link</a>.\\
+ *  1: Support SPI clock mode 1 or 3. See Table <a
+ *  href="table:clock_pol_slave">link</a>.\\
+ */
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
+#define SPI_CLK_MODE_13_V  0x00000001U
+#define SPI_CLK_MODE_13_S  2
+/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
+ *  Configures the edge of output data.\\
+ *  0: Output data at TSCK rising edge.\\
+ *  1: Output data at RSCK rising edge.\\
+ */
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
+#define SPI_RSCK_DATA_OUT_V  0x00000001U
+#define SPI_RSCK_DATA_OUT_S  3
+/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
+ *  of Rd_DMA transfer.\\
+ *  0: Not use\\
+ *  1: Use\\
+ */
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
+ *  of Wr_DMA transfer.\\
+ *  0: Not use\\
+ *  1: Use\\
+ */
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
+ *  of Rd_BUF transfer.\\
+ *  0: Not use\\
+ *  1: Use\\
+ */
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
+ *  of Wr_BUF transfer.\\
+ *  0: Not use\\
+ *  1: Use\\
+ */
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0;
+ *  Represents the effective bit of the last received data byte in SPI slave FD and HD
+ *  mode.
+ */
+#define SPI_SLV_LAST_BYTE_STRB    0x000000FFU
+#define SPI_SLV_LAST_BYTE_STRB_M  (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S)
+#define SPI_SLV_LAST_BYTE_STRB_V  0x000000FFU
+#define SPI_SLV_LAST_BYTE_STRB_S  12
+/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
+ *  Configures the magic value of BM table in DMA-controlled configurable segmented
+ *  transfer.
+ */
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
+ *  Configures SPI work mode.\\
+ *  0: Master\\
+ *  1: Slave\\
+ */
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
+#define SPI_SLAVE_MODE_V  0x00000001U
+#define SPI_SLAVE_MODE_S  26
+/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
+ *  Configures whether to reset the SPI clock line, CS line, and data line via
+ *  software.\\
+ *  0: Not reset\\
+ *  1: Reset\\
+ *  Can be configured in CONF state.
+ */
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
+#define SPI_SOFT_RESET_V  0x00000001U
+#define SPI_SOFT_RESET_S  27
+/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable the CONF state of current DMA-controlled
+ *  configurable segmented transfer.\\
+ *  0: No effect, which means the current transfer is not a configurable segmented
+ *  transfer.\\
+ *  1: Enable, which means a configurable segmented transfer is started.\\
+ */
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
+#define SPI_USR_CONF_V  0x00000001U
+#define SPI_USR_CONF_S  28
+/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to wait DMA TX data gets ready before starting SPI
+ *  transfer in master full-duplex transfer.\\
+ *  0: Not wait\\
+ *  1: Wait\\
+ */
+#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
+
+/** SPI_SLAVE1_REG register
+ *  SPI slave control register 1
+ */
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
+/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
+ *  Configures the transferred data bit length in SPI slave full-/half-duplex modes.
+ */
+#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
+#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_S  0
+/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
+ *  Configures the command value in slave mode.
+ */
+#define SPI_SLV_LAST_COMMAND    0x000000FFU
+#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
+#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
+#define SPI_SLV_LAST_COMMAND_S  18
+/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
+ *  Configures the address value in slave mode.
+ */
+#define SPI_SLV_LAST_ADDR    0x0000003FU
+#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
+#define SPI_SLV_LAST_ADDR_V  0x0000003FU
+#define SPI_SLV_LAST_ADDR_S  26
+
+/** SPI_CLK_GATE_REG register
+ *  SPI module clock and register clock control
+ */
+#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
+/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable clock gate.\\
+ *  0: Disable\\
+ *  1: Enable\\
+ */
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
+#define SPI_CLK_EN_V  0x00000001U
+#define SPI_CLK_EN_S  0
+/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to power on the SPI module clock.
+ */
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
+#define SPI_MST_CLK_ACTIVE_V  0x00000001U
+#define SPI_MST_CLK_ACTIVE_S  1
+/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+ *  0: XTAL CLK.
+ */
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
+#define SPI_MST_CLK_SEL_V  0x00000001U
+#define SPI_MST_CLK_SEL_S  2
+
+/** SPI_DATE_REG register
+ *  Version control
+ */
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
+/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931;
+ *  Version control register.
+ */
+#define SPI_DATE    0x0FFFFFFFU
+#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
+#define SPI_DATE_V  0x0FFFFFFFU
+#define SPI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/spi_struct.h b/components/soc/esp32c61/register/soc/spi_struct.h
new file mode 100644
index 00000000000..88690647ed5
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/spi_struct.h
@@ -0,0 +1,1625 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: User-defined control registers */
+/** Type of cmd register
+ *  Command control register
+ */
+typedef union {
+    struct {
+        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  Configures the SPI_CLK cycles of SPI CONF state.
+         *  Measurement unit: SPI_CLK clock cycle.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t conf_bitlen:18;
+        uint32_t reserved_18:5;
+        /** update : WT; bitpos: [23]; default: 0;
+         *  Configures whether or not to synchronize SPI registers from APB clock domain into
+         *  SPI module clock domain. \\
+         *  0: Not synchronize \\
+         *  1: Synchronize \\
+         *  This bit is only used in SPI master transfer.
+         */
+        uint32_t update:1;
+        /** usr : R/W/SC; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable user-defined command. \\
+         *  0: Not enable \\
+         *  1: Enable \\
+         *  An SPI operation will be triggered when the bit is set. This bit will be cleared
+         *  once the operation is done. Can not be changed by CONF_buf.
+         */
+        uint32_t usr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} spi_cmd_reg_t;
+
+/** Type of addr register
+ *  Address value register
+ */
+typedef union {
+    struct {
+        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the address to slave.
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_addr_value:32;
+    };
+    uint32_t val;
+} spi_addr_reg_t;
+
+/** Type of user register
+ *  SPI USER control register
+ */
+typedef union {
+    struct {
+        /** doutdin : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable full-duplex communication. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t doutdin:1;
+        uint32_t reserved_1:2;
+        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable QPI mode. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  This configuration is applicable when the SPI controller works as master or slave.
+         *  Can be configured in CONF state.
+         */
+        uint32_t qpi_mode:1;
+        /** opi_mode : HRO; bitpos: [4]; default: 0;
+         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t opi_mode:1;
+        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to change the polarity of TSCK in slave transfer. \\
+         *  0: TSCK = SPI_CK_I \\
+         *  1: TSCK = !SPI_CK_I \\
+         */
+        uint32_t tsck_i_edge:1;
+        /** cs_hold : R/W; bitpos: [6]; default: 1;
+         *  Configures whether or not to keep SPI CS low when SPI is in DONE state. \\
+         *  0: Not keep low \\
+         *  1: Keep low \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs_hold:1;
+        /** cs_setup : R/W; bitpos: [7]; default: 1;
+         *  Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs_setup:1;
+        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to change the polarity of RSCK in slave transfer. \\
+         *  0: RSCK = !SPI_CK_I \\
+         *  1: RSCK = SPI_CK_I \\
+         */
+        uint32_t rsck_i_edge:1;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  Configures SPI clock mode together with SPI_CK_IDLE_EDGE.
+         *  Can be configured in CONF state. For more information, see Section <a href="GP-SPI2
+         *  master clock control">link</a>.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:2;
+        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable the 2-bit mode of read-data phase in write
+         *  operations.\\
+         *  0: Not enable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t fwrite_dual:1;
+        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable the 4-bit mode of read-data phase in write
+         *  operations. \\
+         *  0: Not enable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t fwrite_quad:1;
+        /** fwrite_oct : HRO; bitpos: [14]; default: 0;
+         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_oct:1;
+        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable the CONF state for the next transaction
+         *  (segment) in a configurable segmented transfer. \\
+         *  0: this transfer will end after the current transaction (segment) is finished. Or
+         *  this is not a configurable segmented transfer. \\
+         *  1: this configurable segmented transfer will continue its next transaction
+         *  (segment). \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_conf_nxt:1;
+        uint32_t reserved_16:1;
+        /** sio : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable 3-line half-duplex communication, where MOSI
+         *  and MISO signals share the same pin.\\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t sio:1;
+        uint32_t reserved_18:6;
+        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable high part mode, i.e., only access to high part
+         *  of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_miso_highpart:1;
+        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable high part mode, i.e., only access to high part
+         *  of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_mosi_highpart:1;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to disable SPI clock in DUMMY state. \\
+         *  0: Not disable \\
+         *  1: Disable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_dummy_idle:1;
+        /** usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable the write-data (DOUT) state of an operation. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_mosi:1;
+        /** usr_miso : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable the read-data (DIN) state of an operation. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_miso:1;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable the DUMMY state of an operation. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_dummy:1;
+        /** usr_addr : R/W; bitpos: [30]; default: 0;
+         *  Configures whether or not to enable the address (ADDR) state of an operation. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_addr:1;
+        /** usr_command : R/W; bitpos: [31]; default: 1;
+         *  Configures whether or not to enable the command (CMD) state of an operation. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_command:1;
+    };
+    uint32_t val;
+} spi_user_reg_t;
+
+/** Type of user1 register
+ *  SPI USER control register 1
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
+         *  Configures the length of DUMMY state.
+         *  Measurement unit: SPI_CLK clock cycles.\\
+         *  This value is (the expected cycle number - 1). Can be configured in CONF state.
+         */
+        uint32_t usr_dummy_cyclelen:8;
+        uint32_t reserved_8:8;
+        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
+         *  Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error
+         *  occurs in master full-/half-duplex transfers. \\
+         *  0: Not end \\
+         *  1: End \\
+         */
+        uint32_t mst_wfull_err_end_en:1;
+        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
+         *  Configures the length of prepare (PREP) state.
+         *  Measurement unit: SPI_CLK clock cycles.\\
+         *  This value is equal to the expected cycles - 1. This field is used together with
+         *  SPI_CS_SETUP. Can be configured in CONF state.
+         */
+        uint32_t cs_setup_time:5;
+        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
+         *  Configures the delay cycles of CS pin.
+         *  Measurement unit: SPI_CLK clock cycles. \\
+         *  This field is used together with SPI_CS_HOLD. Can be configured in CONF state.
+         */
+        uint32_t cs_hold_time:5;
+        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
+         *  Configures the bit length in address state.
+         *  This value is (expected bit number - 1). Can be configured in CONF state.
+         */
+        uint32_t usr_addr_bitlen:5;
+    };
+    uint32_t val;
+} spi_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI USER control register 2
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the command value.
+         *  Can be configured in CONF state.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:11;
+        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
+         *  Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty
+         *  error occurs in master full-/half-duplex transfers. \\
+         *  0: Not end \\
+         *  1: End \\
+         */
+        uint32_t mst_rempty_err_end_en:1;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  Configures the bit length of command state.
+         *  This value is (expected bit number - 1). Can be configured in CONF state.
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi_user2_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of ctrl register
+ *  SPI control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** dummy_out : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to output the FSPI bus signals in DUMMY state. \\
+         *  0: Not output \\
+         *  1: Output \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t dummy_out:1;
+        uint32_t reserved_4:1;
+        /** faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable 2-bit mode during address (ADDR) state.\\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t faddr_dual:1;
+        /** faddr_quad : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable 4-bit mode during address (ADDR) state. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t faddr_quad:1;
+        /** faddr_oct : HRO; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable 8-bit mode during address (ADDR) state. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t faddr_oct:1;
+        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable 2-bit mode during command (CMD) state. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t fcmd_dual:1;
+        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable 4-bit mode during command (CMD) state. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : HRO; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable 8-bit mode during command (CMD) state. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t fcmd_oct:1;
+        uint32_t reserved_11:3;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read
+         *  operations. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t fread_dual:1;
+        /** fread_quad : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read
+         *  operations. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t fread_quad:1;
+        /** fread_oct : HRO; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read
+         *  operations. \\
+         *  0: Disable \\
+         *  1: Enable \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t fread_oct:1;
+        uint32_t reserved_17:1;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  Configures MISO line polarity. \\
+         *  0: Low \\
+         *  1: High \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  Configures MOSI line polarity. \\
+         *  0: Low \\
+         *  1: High \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t d_pol:1;
+        /** hold_pol : R/W; bitpos: [20]; default: 1;
+         *  Configures SPI_HOLD output value when SPI is in idle. \\
+         *  0: Output low \\
+         *  1: Output high \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t hold_pol:1;
+        /** wp_pol : R/W; bitpos: [21]; default: 1;
+         *  Configures the output value of write-protect signal when SPI is in idle. \\
+         *  0: Output low \\
+         *  1: Output high \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t wp_pol:1;
+        uint32_t reserved_22:1;
+        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
+         *  Configures the bit order in read-data (MISO) state. \\
+         *  0: MSB first \\
+         *  1: LSB first \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t rd_bit_order:2;
+        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
+         *  Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI)
+         *  states. \\
+         *  0: MSB first \\
+         *  1: LSB first \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t wr_bit_order:2;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_ctrl_reg_t;
+
+/** Type of ms_dlen register
+ *  SPI data bit length control register
+ */
+typedef union {
+    struct {
+        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  Configures the data bit length of SPI transfer in DMA-controlled master transfer or
+         *  in CPU-controlled master transfer. Or configures the bit length of SPI RX transfer
+         *  in DMA-controlled slave transfer.
+         *  This value shall be (expected bit_num - 1). Can be configured in CONF state.
+         */
+        uint32_t ms_data_bitlen:18;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_ms_dlen_reg_t;
+
+/** Type of misc register
+ *  SPI misc register
+ */
+typedef union {
+    struct {
+        /** cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to disable SPI_CS$n pin.\\
+         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+         *  1: Disable SPI_CS$n pin.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs0_dis:1;
+        /** cs1_dis : R/W; bitpos: [1]; default: 1;
+         *  Configures whether or not to disable SPI_CS$n pin.\\
+         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+         *  1: Disable SPI_CS$n pin.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs1_dis:1;
+        /** cs2_dis : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to disable SPI_CS$n pin.\\
+         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+         *  1: Disable SPI_CS$n pin.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs2_dis:1;
+        /** cs3_dis : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to disable SPI_CS$n pin.\\
+         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+         *  1: Disable SPI_CS$n pin.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs3_dis:1;
+        /** cs4_dis : R/W; bitpos: [4]; default: 1;
+         *  Configures whether or not to disable SPI_CS$n pin.\\
+         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+         *  1: Disable SPI_CS$n pin.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs4_dis:1;
+        /** cs5_dis : R/W; bitpos: [5]; default: 1;
+         *  Configures whether or not to disable SPI_CS$n pin.\\
+         *  0: SPI_CS$n signal is from/to SPI_CS$n pin.\\
+         *  1: Disable SPI_CS$n pin.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs5_dis:1;
+        /** ck_dis : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to disable SPI_CLK output.\\
+         *  0: Enable\\
+         *  1: Disable\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t ck_dis:1;
+        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
+         *  Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\
+         *  0: SPI_CS$n is low active.\\
+         *  1: SPI_CS$n is high active.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t master_cs_pol:6;
+        uint32_t reserved_13:3;
+        /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0;
+         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+         */
+        uint32_t clk_data_dtr_en:1;
+        /** data_dtr_en : HRO; bitpos: [17]; default: 0;
+         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+         *  Can be configured in CONF state.
+         */
+        uint32_t data_dtr_en:1;
+        /** addr_dtr_en : HRO; bitpos: [18]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t addr_dtr_en:1;
+        /** cmd_dtr_en : HRO; bitpos: [19]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cmd_dtr_en:1;
+        uint32_t reserved_20:3;
+        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not invert SPI slave input CS polarity.\\
+         *  0: Not change\\
+         *  1: Invert\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t slave_cs_pol:1;
+        /** dqs_idle_edge : HRO; bitpos: [24]; default: 0;
+         *  The default value of spi_dqs. Can be configured in CONF state.
+         */
+        uint32_t dqs_idle_edge:1;
+        uint32_t reserved_25:4;
+        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
+         *  Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\
+         *  0: Low\\
+         *  1: High\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
+         *  Configures whether or not to keep the SPI_CS line low.\\
+         *  0: Not keep low\\
+         *  1: Keep low\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs_keep_active:1;
+        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
+         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+         *  spi quad input swap disable. Can be configured in CONF state.
+         */
+        uint32_t quad_din_pin_swap:1;
+    };
+    uint32_t val;
+} spi_misc_reg_t;
+
+/** Type of dma_conf register
+ *  SPI DMA control register
+ */
+typedef union {
+    struct {
+        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
+         *  Represents whether or not the DMA TX FIFO is ready for sending data.\\
+         *  0: Ready\\
+         *  1: Not ready\\
+         */
+        uint32_t dma_outfifo_empty:1;
+        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
+         *  Represents whether or not the DMA RX FIFO is ready for receiving data.\\
+         *  0: Ready\\
+         *  1: Not ready\\
+         */
+        uint32_t dma_infifo_full:1;
+        uint32_t reserved_2:16;
+        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable DMA-controlled segmented transfer in slave
+         *  half-duplex communication.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t dma_slv_seg_trans_en:1;
+        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
+         *  In slave segmented transfer, if the size of the DMA RX buffer is smaller than the
+         *  size of the received data, \\1: the data in all the following Wr_DMA transactions
+         *  will not be received\\ 0: the data in this Wr_DMA transaction will not be received,
+         *  but in the following transactions,\\
+         *
+         *  - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions
+         *  will be received.
+         *  - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will
+         *  not be received.
+         */
+        uint32_t slv_rx_seg_trans_clr_en:1;
+        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
+         *  In slave segmented transfer, if the size of the DMA TX buffer is smaller than the
+         *  size of the transmitted data,\\
+         *  1: the data in the following transactions will not be updated, i.e. the old data is
+         *  transmitted repeatedly.\\
+         *  0: the data in this transaction will not be updated. But in the following
+         *  transactions,\\
+         *
+         *  - if new data is filled in DMA TX FIFO, new data will be transmitted.
+         *  - if no new data is filled in DMA TX FIFO, no new data will be transmitted.
+         */
+        uint32_t slv_tx_seg_trans_clr_en:1;
+        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
+         *  1: In a DAM-controlled transfer, if the bit number of transferred data is equal to
+         *  (SPI_MS_DATA_BITLEN + 1), then GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW will be set by
+         *  hardware. 0: GDMA_IN_SUC_EOF_CH\it{n}_INT_RAW is set by SPI_TRANS_DONE_INT event in
+         *  a single transfer, or by an SPI_DMA_SEG_TRANS_DONE_INT event in a segmented
+         *  transfer.
+         */
+        uint32_t rx_eof_en:1;
+        uint32_t reserved_22:5;
+        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable DMA-controlled receive data transfer.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t dma_rx_ena:1;
+        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable DMA-controlled send data transfer.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t dma_tx_ena:1;
+        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
+         *  Configures whether or not to reset spi_rx_afifo as shown in Figure <a
+         *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
+         *  href="fig:spi-slave-data-flow-control">link</a>.\\
+         *  0: Not reset\\
+         *  1: Reset\\
+         *  spi_rx_afifo is used to receive data in SPI master and slave transfer.
+         */
+        uint32_t rx_afifo_rst:1;
+        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
+         *  Configures whether or not to reset buf_tx_afifo as shown in Figure <a
+         *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
+         *  href="fig:spi-slave-data-flow-control">link</a>.\\
+         *  0: Not reset\\
+         *  1: Reset\\
+         *  buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer.
+         */
+        uint32_t buf_afifo_rst:1;
+        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
+         *  Configures whether or not to reset dma_tx_afifo as shown in Figure <a
+         *  href="fig:spi-master-data-flow-control">link</a> and in Figure  <a
+         *  href="fig:spi-slave-data-flow-control">link</a>.\\
+         *  0: Not reset\\
+         *  1: Reset\\
+         *  dma_tx_afifo is used to send data out in DMA-controlled slave transfer.
+         */
+        uint32_t dma_afifo_rst:1;
+    };
+    uint32_t val;
+} spi_dma_conf_reg_t;
+
+/** Type of slave register
+ *  SPI slave control register
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Configures SPI clock mode.\\
+         *  0: SPI clock is off when CS becomes inactive.\\
+         *  1: SPI clock is delayed one cycle after CS becomes inactive.\\
+         *  2: SPI clock is delayed two cycles after CS becomes inactive.\\
+         *  3: SPI clock is always on.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t clk_mode:2;
+        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
+         *  Configure clock mode.\\
+         *  0: Support SPI clock mode 0 or 2. See Table <a
+         *  href="table:clock_pol_slave">link</a>.\\
+         *  1: Support SPI clock mode 1 or 3. See Table <a
+         *  href="table:clock_pol_slave">link</a>.\\
+         */
+        uint32_t clk_mode_13:1;
+        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
+         *  Configures the edge of output data.\\
+         *  0: Output data at TSCK rising edge.\\
+         *  1: Output data at RSCK rising edge.\\
+         */
+        uint32_t rsck_data_out:1;
+        uint32_t reserved_4:4;
+        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
+         *  of Rd_DMA transfer.\\
+         *  0: Not use\\
+         *  1: Use\\
+         */
+        uint32_t slv_rddma_bitlen_en:1;
+        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
+         *  of Wr_DMA transfer.\\
+         *  0: Not use\\
+         *  1: Use\\
+         */
+        uint32_t slv_wrdma_bitlen_en:1;
+        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
+         *  of Rd_BUF transfer.\\
+         *  0: Not use\\
+         *  1: Use\\
+         */
+        uint32_t slv_rdbuf_bitlen_en:1;
+        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length
+         *  of Wr_BUF transfer.\\
+         *  0: Not use\\
+         *  1: Use\\
+         */
+        uint32_t slv_wrbuf_bitlen_en:1;
+        /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0;
+         *  Represents the effective bit of the last received data byte in SPI slave FD and HD
+         *  mode.
+         */
+        uint32_t slv_last_byte_strb:8;
+        uint32_t reserved_20:2;
+        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
+         *  Configures the magic value of BM table in DMA-controlled configurable segmented
+         *  transfer.
+         */
+        uint32_t dma_seg_magic_value:4;
+        /** slave_mode : R/W; bitpos: [26]; default: 0;
+         *  Configures SPI work mode.\\
+         *  0: Master\\
+         *  1: Slave\\
+         */
+        uint32_t slave_mode:1;
+        /** soft_reset : WT; bitpos: [27]; default: 0;
+         *  Configures whether to reset the SPI clock line, CS line, and data line via
+         *  software.\\
+         *  0: Not reset\\
+         *  1: Reset\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t soft_reset:1;
+        /** usr_conf : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable the CONF state of current DMA-controlled
+         *  configurable segmented transfer.\\
+         *  0: No effect, which means the current transfer is not a configurable segmented
+         *  transfer.\\
+         *  1: Enable, which means a configurable segmented transfer is started.\\
+         */
+        uint32_t usr_conf:1;
+        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to wait DMA TX data gets ready before starting SPI
+         *  transfer in master full-duplex transfer.\\
+         *  0: Not wait\\
+         *  1: Wait\\
+         */
+        uint32_t mst_fd_wait_dma_tx_data:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_slave_reg_t;
+
+/** Type of slave1 register
+ *  SPI slave control register 1
+ */
+typedef union {
+    struct {
+        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
+         *  Configures the transferred data bit length in SPI slave full-/half-duplex modes.
+         */
+        uint32_t slv_data_bitlen:18;
+        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
+         *  Configures the command value in slave mode.
+         */
+        uint32_t slv_last_command:8;
+        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
+         *  Configures the address value in slave mode.
+         */
+        uint32_t slv_last_addr:6;
+    };
+    uint32_t val;
+} spi_slave1_reg_t;
+
+
+/** Group: Clock control registers */
+/** Type of clock register
+ *  SPI clock control register
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
+         *  In master transfer, this field must be equal to SPI_CLKCNT_N. In slave mode, it
+         *  must be 0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_l:6;
+        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
+         *  Configures the duty cycle of SPI_CLK (high level) in master transfer.
+         *  It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1).
+         *  floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it
+         *  must be 0. \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t clkcnt_h:6;
+        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
+         *  Configures the divider of SPI_CLK in master transfer.
+         *  SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N +
+         *  1). \\
+         *  Can be configured in CONF state.
+         */
+        uint32_t clkcnt_n:6;
+        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
+         *  Configures the pre-divider of SPI_CLK in master transfer.
+         *  Can be configured in CONF state.
+         */
+        uint32_t clkdiv_pre:4;
+        uint32_t reserved_22:9;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
+         *  Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\
+         *  0: SPI_CLK is divided from APB_CLK.\\
+         *  1: SPI_CLK is equal to APB_CLK.\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_clock_reg_t;
+
+/** Type of clk_gate register
+ *  SPI module clock and register clock control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable clock gate.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t clk_en:1;
+        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to power on the SPI module clock.
+         */
+        uint32_t mst_clk_active:1;
+        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+         *  0: XTAL CLK.
+         */
+        uint32_t mst_clk_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_clk_gate_reg_t;
+
+
+/** Group: Timing registers */
+/** Type of din_mode register
+ *  SPI input delay mode configuration
+ */
+typedef union {
+    struct {
+        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Configures the input mode for FSPID signal.\\
+         *  0: Input without delay\\
+         *  1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\
+         *  2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  rising edge cycle\\
+         *  3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  falling edge cycle\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t din0_mode:2;
+        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the input mode for FSPIQ signal.\\
+         *  0: Input without delay\\
+         *  1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\
+         *  2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  rising edge cycle\\
+         *  3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  falling edge cycle\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t din1_mode:2;
+        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  Configures the input mode for FSPIWP signal.\\
+         *  0: Input without delay\\
+         *  1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\
+         *  2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  rising edge cycle\\
+         *  3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  falling edge cycle\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t din2_mode:2;
+        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  Configures the input mode for FSPIHD signal.\\
+         *  0: Input without delay\\
+         *  1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\
+         *  2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  rising edge cycle\\
+         *  3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  falling edge cycle\\
+         *  Can be configured in CONF state.
+         *
+         */
+        uint32_t din3_mode:2;
+        /** din4_mode : HRO; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din4_mode:2;
+        /** din5_mode : HRO; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din5_mode:2;
+        /** din6_mode : HRO; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din6_mode:2;
+        /** din7_mode : HRO; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din7_mode:2;
+        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing
+         *  module.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t timing_hclk_active:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} spi_din_mode_reg_t;
+
+/** Type of din_num register
+ *  SPI input delay number configuration
+ */
+typedef union {
+    struct {
+        /** din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\
+         *  0: Delayed by 1 clock cycle\\
+         *  1: Delayed by 2 clock cycles\\
+         *  2: Delayed by 3 clock cycles\\
+         *  3: Delayed by 4 clock cycles\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t din0_num:2;
+        /** din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\
+         *  0: Delayed by 1 clock cycle\\
+         *  1: Delayed by 2 clock cycles\\
+         *  2: Delayed by 3 clock cycles\\
+         *  3: Delayed by 4 clock cycles\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t din1_num:2;
+        /** din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  Configures the delays to input signal FSPIWP based on the setting of
+         *  SPI_DIN2_MODE.\\
+         *  0: Delayed by 1 clock cycle\\
+         *  1: Delayed by 2 clock cycles\\
+         *  2: Delayed by 3 clock cycles\\
+         *  3: Delayed by 4 clock cycles\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t din2_num:2;
+        /** din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  Configures the delays to input signal FSPIHD based on the setting of
+         *  SPI_DIN3_MODE.\\
+         *  0: Delayed by 1 clock cycle\\
+         *  1: Delayed by 2 clock cycles\\
+         *  2: Delayed by 3 clock cycles\\
+         *  3: Delayed by 4 clock cycles\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t din3_num:2;
+        /** din4_num : HRO; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din4_num:2;
+        /** din5_num : HRO; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din5_num:2;
+        /** din6_num : HRO; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din6_num:2;
+        /** din7_num : HRO; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din7_num:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} spi_din_num_reg_t;
+
+/** Type of dout_mode register
+ *  SPI output delay mode configuration
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  Configures the output mode for FSPID signal.\\
+         *  0: Output without delay\\
+         *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t dout0_mode:1;
+        /** dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  Configures the output mode for FSPIQ signal.\\
+         *  0: Output without delay\\
+         *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t dout1_mode:1;
+        /** dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  Configures the output mode for FSPIWP signal.\\
+         *  0: Output without delay\\
+         *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t dout2_mode:1;
+        /** dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  Configures the output mode for FSPIHD signal.\\
+         *  0: Output without delay\\
+         *  1: Output with a delay of a SPI module clock cycle at its falling edge\\
+         *  Can be configured in CONF state.
+         */
+        uint32_t dout3_mode:1;
+        /** dout4_mode : HRO; bitpos: [4]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout4_mode:1;
+        /** dout5_mode : HRO; bitpos: [5]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout5_mode:1;
+        /** dout6_mode : HRO; bitpos: [6]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout6_mode:1;
+        /** dout7_mode : HRO; bitpos: [7]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout7_mode:1;
+        /** d_dqs_mode : HRO; bitpos: [8]; default: 0;
+         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t d_dqs_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_dout_mode_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of dma_int_ena register
+ *  SPI interrupt enable register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable SPI_SLV_EX_QPI_INT interrupt.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable SPI_SLV_EN_QPI_INT interrupt.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable SPI_SLV_CMD7_INT interrupt.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable SPI_SLV_CMD8_INT interrupt.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable SPI_SLV_CMD9_INT interrupt.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable SPI_SLV_CMDA_INT interrupt.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : R/W; bitpos: [15]; default: 0;
+         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : R/W; bitpos: [19]; default: 0;
+         *  Write 1 to enable SPI_APP2_INT interrupt.
+         */
+        uint32_t app2:1;
+        /** app1 : R/W; bitpos: [20]; default: 0;
+         *  Write 1 to enable SPI_APP1_INT interrupt.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_ena_reg_t;
+
+/** Type of dma_int_clr register
+ *  SPI interrupt clear register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear SPI_SLV_EX_QPI_INT interrupt.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear SPI_SLV_EN_QPI_INT interrupt.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear SPI_SLV_CMD7_INT interrupt.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear SPI_SLV_CMD8_INT interrupt.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear SPI_SLV_CMD9_INT interrupt.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear SPI_SLV_CMDA_INT interrupt.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : WT; bitpos: [15]; default: 0;
+         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : WT; bitpos: [19]; default: 0;
+         *  Write 1 to clear SPI_APP2_INT interrupt.
+         */
+        uint32_t app2:1;
+        /** app1 : WT; bitpos: [20]; default: 0;
+         *  Write 1 to clear SPI_APP1_INT interrupt.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_clr_reg_t;
+
+/** Type of dma_int_raw register
+ *  SPI interrupt raw register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of SPI_SLV_EX_QPI_INT interrupt.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of SPI_SLV_EN_QPI_INT interrupt.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of SPI_SLV_CMD7_INT interrupt.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of SPI_SLV_CMD8_INT interrupt.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of SPI_SLV_CMD9_INT interrupt.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of SPI_SLV_CMDA_INT interrupt.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt status of SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+         *  bigger than 63. 0: Others.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw interrupt status of SPI_APP2_INT interrupt. The value is only controlled by
+         *  the application.
+         */
+        uint32_t app2:1;
+        /** app1 : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw interrupt status of SPI_APP1_INT interrupt. The value is only controlled by
+         *  the application.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_raw_reg_t;
+
+/** Type of dma_int_st register
+ *  SPI interrupt status register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : RO; bitpos: [0]; default: 0;
+         *  The interrupt status of SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : RO; bitpos: [1]; default: 0;
+         *  The interrupt status of SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : RO; bitpos: [2]; default: 0;
+         *  The interrupt status of SPI_SLV_EX_QPI_INT interrupt.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : RO; bitpos: [3]; default: 0;
+         *  The interrupt status of SPI_SLV_EN_QPI_INT interrupt.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : RO; bitpos: [4]; default: 0;
+         *  The interrupt status of SPI_SLV_CMD7_INT interrupt.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : RO; bitpos: [5]; default: 0;
+         *  The interrupt status of SPI_SLV_CMD8_INT interrupt.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : RO; bitpos: [6]; default: 0;
+         *  The interrupt status of SPI_SLV_CMD9_INT interrupt.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : RO; bitpos: [7]; default: 0;
+         *  The interrupt status of SPI_SLV_CMDA_INT interrupt.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : RO; bitpos: [8]; default: 0;
+         *  The interrupt status of SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : RO; bitpos: [9]; default: 0;
+         *  The interrupt status of SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : RO; bitpos: [10]; default: 0;
+         *  The interrupt status of SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : RO; bitpos: [11]; default: 0;
+         *  The interrupt status of SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : RO; bitpos: [12]; default: 0;
+         *  The interrupt status of SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : RO; bitpos: [13]; default: 0;
+         *  The interrupt status of SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : RO; bitpos: [14]; default: 0;
+         *  The interrupt status of SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : RO; bitpos: [15]; default: 0;
+         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : RO; bitpos: [16]; default: 0;
+         *  The interrupt status of SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : RO; bitpos: [17]; default: 0;
+         *  The interrupt status of SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : RO; bitpos: [18]; default: 0;
+         *  The interrupt status of SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : RO; bitpos: [19]; default: 0;
+         *  The interrupt status of SPI_APP2_INT interrupt.
+         */
+        uint32_t app2:1;
+        /** app1 : RO; bitpos: [20]; default: 0;
+         *  The interrupt status of SPI_APP1_INT interrupt.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_st_reg_t;
+
+/** Type of dma_int_set register
+ *  SPI interrupt software set register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err : WT; bitpos: [0]; default: 0;
+         *  Write 1 to set SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err:1;
+        /** dma_outfifo_empty_err : WT; bitpos: [1]; default: 0;
+         *  Write 1 to set SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err:1;
+        /** slv_ex_qpi : WT; bitpos: [2]; default: 0;
+         *  Write 1 to set SPI_SLV_EX_QPI_INT interrupt.
+         */
+        uint32_t slv_ex_qpi:1;
+        /** slv_en_qpi : WT; bitpos: [3]; default: 0;
+         *  Write 1 to set SPI_SLV_EN_QPI_INT interrupt.
+         */
+        uint32_t slv_en_qpi:1;
+        /** slv_cmd7 : WT; bitpos: [4]; default: 0;
+         *  Write 1 to set SPI_SLV_CMD7_INT interrupt.
+         */
+        uint32_t slv_cmd7:1;
+        /** slv_cmd8 : WT; bitpos: [5]; default: 0;
+         *  Write 1 to set SPI_SLV_CMD8_INT interrupt.
+         */
+        uint32_t slv_cmd8:1;
+        /** slv_cmd9 : WT; bitpos: [6]; default: 0;
+         *  Write 1 to set SPI_SLV_CMD9_INT interrupt.
+         */
+        uint32_t slv_cmd9:1;
+        /** slv_cmda : WT; bitpos: [7]; default: 0;
+         *  Write 1 to set SPI_SLV_CMDA_INT interrupt.
+         */
+        uint32_t slv_cmda:1;
+        /** slv_rd_dma_done : WT; bitpos: [8]; default: 0;
+         *  Write 1 to set SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done:1;
+        /** slv_wr_dma_done : WT; bitpos: [9]; default: 0;
+         *  Write 1 to set SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done:1;
+        /** slv_rd_buf_done : WT; bitpos: [10]; default: 0;
+         *  Write 1 to set SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done:1;
+        /** slv_wr_buf_done : WT; bitpos: [11]; default: 0;
+         *  Write 1 to set SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done:1;
+        /** trans_done : WT; bitpos: [12]; default: 0;
+         *  Write 1 to set SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done:1;
+        /** dma_seg_trans_done : WT; bitpos: [13]; default: 0;
+         *  Write 1 to set SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done:1;
+        /** seg_magic_err : WT; bitpos: [14]; default: 0;
+         *  Write 1 to set SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err:1;
+        /** slv_buf_addr_err : WT; bitpos: [15]; default: 0;
+         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err:1;
+        /** slv_cmd_err : WT; bitpos: [16]; default: 0;
+         *  Write 1 to set SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err:1;
+        /** mst_rx_afifo_wfull_err : WT; bitpos: [17]; default: 0;
+         *  Write 1 to set SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err:1;
+        /** mst_tx_afifo_rempty_err : WT; bitpos: [18]; default: 0;
+         *  Write 1 to set SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err:1;
+        /** app2 : WT; bitpos: [19]; default: 0;
+         *  Write 1 to set SPI_APP2_INT interrupt.
+         */
+        uint32_t app2:1;
+        /** app1 : WT; bitpos: [20]; default: 0;
+         *  Write 1 to set SPI_APP1_INT interrupt.
+         */
+        uint32_t app1:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_set_reg_t;
+
+
+/** Group: CPU-controlled data buffer */
+/** Type of wn register
+ *  SPI CPU-controlled buffer n
+ */
+typedef union {
+    struct {
+        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf:32;
+    };
+    uint32_t val;
+} spi_wn_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36716931;
+         *  Version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_date_reg_t;
+
+
+typedef struct {
+    volatile spi_cmd_reg_t cmd;
+    volatile spi_addr_reg_t addr;
+    volatile spi_ctrl_reg_t ctrl;
+    volatile spi_clock_reg_t clock;
+    volatile spi_user_reg_t user;
+    volatile spi_user1_reg_t user1;
+    volatile spi_user2_reg_t user2;
+    volatile spi_ms_dlen_reg_t ms_dlen;
+    volatile spi_misc_reg_t misc;
+    volatile spi_din_mode_reg_t din_mode;
+    volatile spi_din_num_reg_t din_num;
+    volatile spi_dout_mode_reg_t dout_mode;
+    volatile spi_dma_conf_reg_t dma_conf;
+    volatile spi_dma_int_ena_reg_t dma_int_ena;
+    volatile spi_dma_int_clr_reg_t dma_int_clr;
+    volatile spi_dma_int_raw_reg_t dma_int_raw;
+    volatile spi_dma_int_st_reg_t dma_int_st;
+    volatile spi_dma_int_set_reg_t dma_int_set;
+    uint32_t reserved_048[20];
+    volatile spi_wn_reg_t data_buf[16];
+    uint32_t reserved_0d8[2];
+    volatile spi_slave_reg_t slave;
+    volatile spi_slave1_reg_t slave1;
+    volatile spi_clk_gate_reg_t clk_gate;
+    uint32_t reserved_0ec;
+    volatile spi_date_reg_t date;
+} spi_dev_t;
+
+extern spi_dev_t GPSPI2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/systimer_reg.h b/components/soc/esp32c61/register/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/systimer_reg.h
rename to components/soc/esp32c61/register/soc/systimer_reg.h
diff --git a/components/soc/esp32c61/include/soc/systimer_struct.h b/components/soc/esp32c61/register/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/systimer_struct.h
rename to components/soc/esp32c61/register/soc/systimer_struct.h
diff --git a/components/soc/esp32c61/include/soc/tee_reg.h b/components/soc/esp32c61/register/soc/tee_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/tee_reg.h
rename to components/soc/esp32c61/register/soc/tee_reg.h
diff --git a/components/soc/esp32c61/include/soc/tee_struct.h b/components/soc/esp32c61/register/soc/tee_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/tee_struct.h
rename to components/soc/esp32c61/register/soc/tee_struct.h
diff --git a/components/soc/esp32c61/include/soc/timer_group_reg.h b/components/soc/esp32c61/register/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/timer_group_reg.h
rename to components/soc/esp32c61/register/soc/timer_group_reg.h
diff --git a/components/soc/esp32c61/include/soc/timer_group_struct.h b/components/soc/esp32c61/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/timer_group_struct.h
rename to components/soc/esp32c61/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32c61/register/soc/trace_reg.h b/components/soc/esp32c61/register/soc/trace_reg.h
new file mode 100644
index 00000000000..785965af2c7
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/trace_reg.h
@@ -0,0 +1,464 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TRACE_MEM_START_ADDR_REG register
+ *  Memory start address
+ */
+#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
+/** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the trace memory
+ */
+#define TRACE_MEM_START_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_START_ADDR_M  (TRACE_MEM_START_ADDR_V << TRACE_MEM_START_ADDR_S)
+#define TRACE_MEM_START_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_START_ADDR_S  0
+
+/** TRACE_MEM_END_ADDR_REG register
+ *  Memory end address
+ */
+#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
+/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the end address of the trace memory.
+ */
+#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
+#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_S  0
+
+/** TRACE_MEM_CURRENT_ADDR_REG register
+ *  Memory current addr
+ */
+#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
+/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents the current memory address for writing.
+ */
+#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
+#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_S  0
+
+/** TRACE_MEM_ADDR_UPDATE_REG register
+ *  Memory address update
+ */
+#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
+/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Configures whether to update the value of
+ *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
+ *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\
+ *  0: Not update\\
+ *  1: Update\\
+ */
+#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
+
+/** TRACE_FIFO_STATUS_REG register
+ *  FIFO status register
+ */
+#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
+/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Represent whether the FIFO is empty. \\1: Empty \\0: Not empty
+ */
+#define TRACE_FIFO_EMPTY    (BIT(0))
+#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
+#define TRACE_FIFO_EMPTY_V  0x00000001U
+#define TRACE_FIFO_EMPTY_S  0
+/** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
+ *  Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
+ *  state because hart is halted or in reset \\3: Lost state\\
+ */
+#define TRACE_WORK_STATUS    0x00000003U
+#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
+#define TRACE_WORK_STATUS_V  0x00000003U
+#define TRACE_WORK_STATUS_S  1
+
+/** TRACE_INTR_ENA_REG register
+ *  Interrupt enable register
+ */
+#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
+/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable TRACE_FIFO_OVERFLOW_INTR
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
+/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable TRACE_MEM_FULL_INTR
+ */
+#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
+#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
+#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_ENA_S  1
+
+/** TRACE_INTR_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
+/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR.
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
+/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status of TRACE_MEM_FULL_INTR
+ */
+#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
+#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
+#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_RAW_S  1
+
+/** TRACE_INTR_CLR_REG register
+ *  Interrupt clear register
+ */
+#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
+/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear TRACE_FIFO_OVERFLOW_INTR
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
+/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear TRACE_MEM_FULL_INTR
+ */
+#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
+#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
+#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_CLR_S  1
+
+/** TRACE_TRIGGER_REG register
+ *  Trace enable register
+ */
+#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
+/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
+ *  Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\
+ */
+#define TRACE_TRIGGER_ON    (BIT(0))
+#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
+#define TRACE_TRIGGER_ON_V  0x00000001U
+#define TRACE_TRIGGER_ON_S  0
+/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
+ *  Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\
+ */
+#define TRACE_TRIGGER_OFF    (BIT(1))
+#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
+#define TRACE_TRIGGER_OFF_V  0x00000001U
+#define TRACE_TRIGGER_OFF_S  1
+/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
+ *  Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\
+ */
+#define TRACE_MEM_LOOP    (BIT(2))
+#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
+#define TRACE_MEM_LOOP_V  0x00000001U
+#define TRACE_MEM_LOOP_S  2
+/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
+ *  Configure whether or not enable automatic restart function for the encoder.\\0:
+ *  Disable\\1: Enable\\
+ */
+#define TRACE_RESTART_ENA    (BIT(3))
+#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
+#define TRACE_RESTART_ENA_V  0x00000001U
+#define TRACE_RESTART_ENA_S  3
+
+/** TRACE_CONFIG_REG register
+ *  trace configuration register
+ */
+#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24)
+/** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\
+ */
+#define TRACE_DM_TRIGGER_ENA    (BIT(0))
+#define TRACE_DM_TRIGGER_ENA_M  (TRACE_DM_TRIGGER_ENA_V << TRACE_DM_TRIGGER_ENA_S)
+#define TRACE_DM_TRIGGER_ENA_V  0x00000001U
+#define TRACE_DM_TRIGGER_ENA_S  0
+/** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configure whether to reset, when enabled, if cpu have reset, the encoder will
+ *  output a packet to report the address of the last instruction, and upon reset
+ *  deassertion, the encoder start again.\\0: Disable\\0: Enable\\
+ */
+#define TRACE_RESET_ENA    (BIT(1))
+#define TRACE_RESET_ENA_M  (TRACE_RESET_ENA_V << TRACE_RESET_ENA_S)
+#define TRACE_RESET_ENA_V  0x00000001U
+#define TRACE_RESET_ENA_S  1
+/** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\
+ */
+#define TRACE_HALT_ENA    (BIT(2))
+#define TRACE_HALT_ENA_M  (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S)
+#define TRACE_HALT_ENA_V  0x00000001U
+#define TRACE_HALT_ENA_S  2
+/** TRACE_STALL_ENA : R/W; bitpos: [3]; default: 0;
+ *  Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\
+ */
+#define TRACE_STALL_ENA    (BIT(3))
+#define TRACE_STALL_ENA_M  (TRACE_STALL_ENA_V << TRACE_STALL_ENA_S)
+#define TRACE_STALL_ENA_V  0x00000001U
+#define TRACE_STALL_ENA_S  3
+/** TRACE_FULL_ADDRESS : R/W; bitpos: [4]; default: 0;
+ *  Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\
+ */
+#define TRACE_FULL_ADDRESS    (BIT(4))
+#define TRACE_FULL_ADDRESS_M  (TRACE_FULL_ADDRESS_V << TRACE_FULL_ADDRESS_S)
+#define TRACE_FULL_ADDRESS_V  0x00000001U
+#define TRACE_FULL_ADDRESS_S  4
+/** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
+ *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
+ *  exception address, only exception cause in exception packets.\\1: enabled\\0:
+ *  disabled\\
+ */
+#define TRACE_IMPLICIT_EXCEPT    (BIT(5))
+#define TRACE_IMPLICIT_EXCEPT_M  (TRACE_IMPLICIT_EXCEPT_V << TRACE_IMPLICIT_EXCEPT_S)
+#define TRACE_IMPLICIT_EXCEPT_V  0x00000001U
+#define TRACE_IMPLICIT_EXCEPT_S  5
+
+/** TRACE_FILTER_CONTROL_REG register
+ *  filter control register
+ */
+#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28)
+/** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable
+ */
+#define TRACE_FILTER_EN    (BIT(0))
+#define TRACE_FILTER_EN_M  (TRACE_FILTER_EN_V << TRACE_FILTER_EN_S)
+#define TRACE_FILTER_EN_V  0x00000001U
+#define TRACE_FILTER_EN_S  0
+/** TRACE_MATCH_COMP : R/W; bitpos: [1]; default: 0;
+ *  Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable,
+ *  the comparator must be high in order for the filter to match
+ */
+#define TRACE_MATCH_COMP    (BIT(1))
+#define TRACE_MATCH_COMP_M  (TRACE_MATCH_COMP_V << TRACE_MATCH_COMP_S)
+#define TRACE_MATCH_COMP_V  0x00000001U
+#define TRACE_MATCH_COMP_S  1
+/** TRACE_MATCH_PRIVILEGE : R/W; bitpos: [2]; default: 0;
+ *  Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable,
+ *  match privilege levels specified by
+ *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
+ */
+#define TRACE_MATCH_PRIVILEGE    (BIT(2))
+#define TRACE_MATCH_PRIVILEGE_M  (TRACE_MATCH_PRIVILEGE_V << TRACE_MATCH_PRIVILEGE_S)
+#define TRACE_MATCH_PRIVILEGE_V  0x00000001U
+#define TRACE_MATCH_PRIVILEGE_S  2
+/** TRACE_MATCH_ECAUSE : R/W; bitpos: [3]; default: 0;
+ *  Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start
+ *  matching from exception cause codes specified by
+ *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
+ *  matching upon return from the 1st matching exception.
+ */
+#define TRACE_MATCH_ECAUSE    (BIT(3))
+#define TRACE_MATCH_ECAUSE_M  (TRACE_MATCH_ECAUSE_V << TRACE_MATCH_ECAUSE_S)
+#define TRACE_MATCH_ECAUSE_V  0x00000001U
+#define TRACE_MATCH_ECAUSE_S  3
+/** TRACE_MATCH_INTERRUPT : R/W; bitpos: [4]; default: 0;
+ *  Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable,
+ *  start matching from a trap with the interrupt level codes specified by
+ *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
+ *  stop matching upon return from the 1st matching trap.
+ */
+#define TRACE_MATCH_INTERRUPT    (BIT(4))
+#define TRACE_MATCH_INTERRUPT_M  (TRACE_MATCH_INTERRUPT_V << TRACE_MATCH_INTERRUPT_S)
+#define TRACE_MATCH_INTERRUPT_V  0x00000001U
+#define TRACE_MATCH_INTERRUPT_S  4
+
+/** TRACE_FILTER_MATCH_CONTROL_REG register
+ *  filter match control register
+ */
+#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c)
+/** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0;
+ *  Configures the privilege level for matching. Valid only when
+ *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User
+ *  mode. \\1: Machine mode
+ */
+#define TRACE_MATCH_CHOICE_PRIVILEGE    (BIT(0))
+#define TRACE_MATCH_CHOICE_PRIVILEGE_M  (TRACE_MATCH_CHOICE_PRIVILEGE_V << TRACE_MATCH_CHOICE_PRIVILEGE_S)
+#define TRACE_MATCH_CHOICE_PRIVILEGE_V  0x00000001U
+#define TRACE_MATCH_CHOICE_PRIVILEGE_S  0
+/** TRACE_MATCH_VALUE_INTERRUPT : R/W; bitpos: [1]; default: 0;
+ *  Configures the interrupt level for match. Valid only when when
+ *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0:
+ *  itype=2. \\0: itype=2.
+ */
+#define TRACE_MATCH_VALUE_INTERRUPT    (BIT(1))
+#define TRACE_MATCH_VALUE_INTERRUPT_M  (TRACE_MATCH_VALUE_INTERRUPT_V << TRACE_MATCH_VALUE_INTERRUPT_S)
+#define TRACE_MATCH_VALUE_INTERRUPT_V  0x00000001U
+#define TRACE_MATCH_VALUE_INTERRUPT_S  1
+/** TRACE_MATCH_CHOICE_ECAUSE : R/W; bitpos: [7:2]; default: 0;
+ *  Configures the ecause code for matching.
+ */
+#define TRACE_MATCH_CHOICE_ECAUSE    0x0000003FU
+#define TRACE_MATCH_CHOICE_ECAUSE_M  (TRACE_MATCH_CHOICE_ECAUSE_V << TRACE_MATCH_CHOICE_ECAUSE_S)
+#define TRACE_MATCH_CHOICE_ECAUSE_V  0x0000003FU
+#define TRACE_MATCH_CHOICE_ECAUSE_S  2
+
+/** TRACE_FILTER_COMPARATOR_CONTROL_REG register
+ *  filter comparator match control register
+ */
+#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30)
+/** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0;
+ *  Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\
+ */
+#define TRACE_P_INPUT    (BIT(0))
+#define TRACE_P_INPUT_M  (TRACE_P_INPUT_V << TRACE_P_INPUT_S)
+#define TRACE_P_INPUT_V  0x00000001U
+#define TRACE_P_INPUT_S  0
+/** TRACE_P_FUNCTION : R/W; bitpos: [4:2]; default: 0;
+ *  Configures the function for the primary comparator. \\0: Equal, \\1: Not equal,
+ *  \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
+ *  equal, \\Other: Always match
+ */
+#define TRACE_P_FUNCTION    0x00000007U
+#define TRACE_P_FUNCTION_M  (TRACE_P_FUNCTION_V << TRACE_P_FUNCTION_S)
+#define TRACE_P_FUNCTION_V  0x00000007U
+#define TRACE_P_FUNCTION_S  2
+/** TRACE_P_NOTIFY : R/W; bitpos: [5]; default: 0;
+ *  Configure whether to explicitly report an instruction address matched against the
+ *  primary comparator. \\0:Not report \\1:Report
+ */
+#define TRACE_P_NOTIFY    (BIT(5))
+#define TRACE_P_NOTIFY_M  (TRACE_P_NOTIFY_V << TRACE_P_NOTIFY_S)
+#define TRACE_P_NOTIFY_V  0x00000001U
+#define TRACE_P_NOTIFY_S  5
+/** TRACE_S_INPUT : R/W; bitpos: [8]; default: 0;
+ *  Configures the input of the secondary comparator for matching: \\0: iaddr \\1:
+ *  tval\\
+ */
+#define TRACE_S_INPUT    (BIT(8))
+#define TRACE_S_INPUT_M  (TRACE_S_INPUT_V << TRACE_S_INPUT_S)
+#define TRACE_S_INPUT_V  0x00000001U
+#define TRACE_S_INPUT_S  8
+/** TRACE_S_FUNCTION : R/W; bitpos: [12:10]; default: 0;
+ *  Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal,
+ *  \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
+ *  equal, \\Other: Always match
+ */
+#define TRACE_S_FUNCTION    0x00000007U
+#define TRACE_S_FUNCTION_M  (TRACE_S_FUNCTION_V << TRACE_S_FUNCTION_S)
+#define TRACE_S_FUNCTION_V  0x00000007U
+#define TRACE_S_FUNCTION_S  10
+/** TRACE_S_NOTIFY : R/W; bitpos: [13]; default: 0;
+ *  Generate a trace packet explicitly reporting the address that cause the secondary
+ *  match
+ */
+#define TRACE_S_NOTIFY    (BIT(13))
+#define TRACE_S_NOTIFY_M  (TRACE_S_NOTIFY_V << TRACE_S_NOTIFY_S)
+#define TRACE_S_NOTIFY_V  0x00000001U
+#define TRACE_S_NOTIFY_S  13
+/** TRACE_MATCH_MODE : R/W; bitpos: [17:16]; default: 0;
+ *  Configures the comparator match mode: \\0: Only the primary comparator matches \\1:
+ *  Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or
+ *  secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary
+ *  comparator matches and stop filtering when the secondary comparator matches\\
+ */
+#define TRACE_MATCH_MODE    0x00000003U
+#define TRACE_MATCH_MODE_M  (TRACE_MATCH_MODE_V << TRACE_MATCH_MODE_S)
+#define TRACE_MATCH_MODE_V  0x00000003U
+#define TRACE_MATCH_MODE_S  16
+
+/** TRACE_FILTER_P_COMPARATOR_MATCH_REG register
+ *  primary comparator match value
+ */
+#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34)
+/** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the match value for the primary comparator
+ */
+#define TRACE_P_MATCH    0xFFFFFFFFU
+#define TRACE_P_MATCH_M  (TRACE_P_MATCH_V << TRACE_P_MATCH_S)
+#define TRACE_P_MATCH_V  0xFFFFFFFFU
+#define TRACE_P_MATCH_S  0
+
+/** TRACE_FILTER_S_COMPARATOR_MATCH_REG register
+ *  secondary comparator match value
+ */
+#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38)
+/** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the match value for the secondary comparator
+ */
+#define TRACE_S_MATCH    0xFFFFFFFFU
+#define TRACE_S_MATCH_M  (TRACE_S_MATCH_V << TRACE_S_MATCH_S)
+#define TRACE_S_MATCH_V  0xFFFFFFFFU
+#define TRACE_S_MATCH_S  0
+
+/** TRACE_RESYNC_PROLONGED_REG register
+ *  Resync configuration register
+ */
+#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c)
+/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
+ *  Configures the threshold for synchronization counter
+ */
+#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
+#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_S  0
+/** TRACE_RESYNC_MODE : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the synchronization mode: \\0: Disable the synchronization counter \\1:
+ *  Invalid \\2: Synchronization counter counts by packet  \\3: Synchronization counter
+ *  counts by cycle\\
+ */
+#define TRACE_RESYNC_MODE    0x00000003U
+#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
+#define TRACE_RESYNC_MODE_V  0x00000003U
+#define TRACE_RESYNC_MODE_S  24
+
+/** TRACE_AHB_CONFIG_REG register
+ *  AHB config register
+ */
+#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40)
+/** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4
+ *  \\4:INCR8 \\Others:Invalid
+ */
+#define TRACE_HBURST    0x00000007U
+#define TRACE_HBURST_M  (TRACE_HBURST_V << TRACE_HBURST_S)
+#define TRACE_HBURST_V  0x00000007U
+#define TRACE_HBURST_S  0
+/** TRACE_MAX_INCR : R/W; bitpos: [5:3]; default: 0;
+ *  Configures the maximum burst length for INCR mode
+ */
+#define TRACE_MAX_INCR    0x00000007U
+#define TRACE_MAX_INCR_M  (TRACE_MAX_INCR_V << TRACE_MAX_INCR_S)
+#define TRACE_MAX_INCR_V  0x00000007U
+#define TRACE_MAX_INCR_S  3
+
+/** TRACE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44)
+/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures register clock gating. \\0: Support clock only when the application
+ *  writes registers to save power. \\1:Always force the clock on for registers \\ This
+ *  bit doesn't affect register access.
+ */
+#define TRACE_CLK_EN    (BIT(0))
+#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
+#define TRACE_CLK_EN_V  0x00000001U
+#define TRACE_CLK_EN_S  0
+
+/** TRACE_DATE_REG register
+ *  Version control register
+ */
+#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
+/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984;
+ *  Version control register.
+ */
+#define TRACE_DATE    0x0FFFFFFFU
+#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
+#define TRACE_DATE_V  0x0FFFFFFFU
+#define TRACE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/trace_struct.h b/components/soc/esp32c61/register/soc/trace_struct.h
new file mode 100644
index 00000000000..1b73fe2666f
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/trace_struct.h
@@ -0,0 +1,463 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory configuration registers */
+/** Type of mem_start_addr register
+ *  Memory start address
+ */
+typedef union {
+    struct {
+        /** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the trace memory
+         */
+        uint32_t mem_start_addr:32;
+    };
+    uint32_t val;
+} trace_mem_start_addr_reg_t;
+
+/** Type of mem_end_addr register
+ *  Memory end address
+ */
+typedef union {
+    struct {
+        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the end address of the trace memory.
+         */
+        uint32_t mem_end_addr:32;
+    };
+    uint32_t val;
+} trace_mem_end_addr_reg_t;
+
+/** Type of mem_current_addr register
+ *  Memory current addr
+ */
+typedef union {
+    struct {
+        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents the current memory address for writing.
+         */
+        uint32_t mem_current_addr:32;
+    };
+    uint32_t val;
+} trace_mem_current_addr_reg_t;
+
+/** Type of mem_addr_update register
+ *  Memory address update
+ */
+typedef union {
+    struct {
+        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
+         *  Configures whether to update the value of
+         *  \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} to
+         *  \hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}.\\
+         *  0: Not update\\
+         *  1: Update\\
+         */
+        uint32_t mem_current_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_mem_addr_update_reg_t;
+
+
+/** Group: Trace fifo status register */
+/** Type of fifo_status register
+ *  FIFO status register
+ */
+typedef union {
+    struct {
+        /** fifo_empty : RO; bitpos: [0]; default: 1;
+         *  Represent whether the FIFO is empty. \\1: Empty \\0: Not empty
+         */
+        uint32_t fifo_empty:1;
+        /** work_status : RO; bitpos: [2:1]; default: 0;
+         *  Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
+         *  state because hart is halted or in reset \\3: Lost state\\
+         */
+        uint32_t work_status:2;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} trace_fifo_status_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of intr_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable TRACE_FIFO_OVERFLOW_INTR
+         */
+        uint32_t fifo_overflow_intr_ena:1;
+        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable TRACE_MEM_FULL_INTR
+         */
+        uint32_t mem_full_intr_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_ena_reg_t;
+
+/** Type of intr_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status of TRACE_FIFO_OVERFLOW_INTR.
+         */
+        uint32_t fifo_overflow_intr_raw:1;
+        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status of TRACE_MEM_FULL_INTR
+         */
+        uint32_t mem_full_intr_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_raw_reg_t;
+
+/** Type of intr_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear TRACE_FIFO_OVERFLOW_INTR
+         */
+        uint32_t fifo_overflow_intr_clr:1;
+        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear TRACE_MEM_FULL_INTR
+         */
+        uint32_t mem_full_intr_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_clr_reg_t;
+
+
+/** Group: Trace configuration register */
+/** Type of trigger register
+ *  Trace enable register
+ */
+typedef union {
+    struct {
+        /** trigger_on : WT; bitpos: [0]; default: 0;
+         *  Configure whether to enable the encoder.\\0: Invalid \\1: Enable\\
+         */
+        uint32_t trigger_on:1;
+        /** trigger_off : WT; bitpos: [1]; default: 0;
+         *  Configure whether to disable the encoder.\\0: Invalid \\1: Disable\\
+         */
+        uint32_t trigger_off:1;
+        /** mem_loop : R/W; bitpos: [2]; default: 1;
+         *  Configure the memory writing mode. \\0: Non-loop mode. \\1: Loop mode\\
+         */
+        uint32_t mem_loop:1;
+        /** restart_ena : R/W; bitpos: [3]; default: 1;
+         *  Configure whether or not enable automatic restart function for the encoder.\\0:
+         *  Disable\\1: Enable\\
+         */
+        uint32_t restart_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} trace_trigger_reg_t;
+
+/** Type of config register
+ *  trace configuration register
+ */
+typedef union {
+    struct {
+        /** dm_trigger_ena : R/W; bitpos: [0]; default: 0;
+         *  Configure whether to enable the trigger signal.\\0: Disable\\1:enable\\
+         */
+        uint32_t dm_trigger_ena:1;
+        /** reset_ena : R/W; bitpos: [1]; default: 0;
+         *  Configure whether to reset, when enabled, if cpu have reset, the encoder will
+         *  output a packet to report the address of the last instruction, and upon reset
+         *  deassertion, the encoder start again.\\0: Disable\\0: Enable\\
+         */
+        uint32_t reset_ena:1;
+        /** halt_ena : R/W; bitpos: [2]; default: 0;
+         *  Configure whether to enable the halt signal. \\1: Disable\\1: Enable\\
+         */
+        uint32_t halt_ena:1;
+        /** stall_ena : R/W; bitpos: [3]; default: 0;
+         *  Configure whether to enable the stall signal. \\0: Disable.\\1: Enable\\
+         */
+        uint32_t stall_ena:1;
+        /** full_address : R/W; bitpos: [4]; default: 0;
+         *  Configure the address mode.\\0: Delta address mode.\\1: Full address mode.\\
+         */
+        uint32_t full_address:1;
+        /** implicit_except : R/W; bitpos: [5]; default: 0;
+         *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
+         *  exception address, only exception cause in exception packets.\\1: enabled\\0:
+         *  disabled\\
+         */
+        uint32_t implicit_except:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} trace_config_reg_t;
+
+/** Type of filter_control register
+ *  filter control register
+ */
+typedef union {
+    struct {
+        /** filter_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether to enable filtering. \\0: Disable, always match.\\ 1: Enable
+         */
+        uint32_t filter_en:1;
+        /** match_comp : R/W; bitpos: [1]; default: 0;
+         *  Configure whether to enable the comparator match mode. \\0: Disable \\1: Enable,
+         *  the comparator must be high in order for the filter to match
+         */
+        uint32_t match_comp:1;
+        /** match_privilege : R/W; bitpos: [2]; default: 0;
+         *  Configure whether to enable the privilege match mode. \\0: Disable \\1: Enable,
+         *  match privilege levels specified by
+         *  \hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}.
+         */
+        uint32_t match_privilege:1;
+        /** match_ecause : R/W; bitpos: [3]; default: 0;
+         *  Configure whether to enable ecause match mode. \\0: Disable \\1: Enable, start
+         *  matching from exception cause codes specified by
+         *  \hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop
+         *  matching upon return from the 1st matching exception.
+         */
+        uint32_t match_ecause:1;
+        /** match_interrupt : R/W; bitpos: [4]; default: 0;
+         *  Configure whether to enable the interrupt match mode. \\0: Disable \\1: Enable,
+         *  start matching from a trap with the interrupt level codes specified by
+         *  \hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and
+         *  stop matching upon return from the 1st matching trap.
+         */
+        uint32_t match_interrupt:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} trace_filter_control_reg_t;
+
+/** Type of filter_match_control register
+ *  filter match control register
+ */
+typedef union {
+    struct {
+        /** match_choice_privilege : R/W; bitpos: [0]; default: 0;
+         *  Configures the privilege level for matching. Valid only when
+         *  \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\0: User
+         *  mode. \\1: Machine mode
+         */
+        uint32_t match_choice_privilege:1;
+        /** match_value_interrupt : R/W; bitpos: [1]; default: 0;
+         *  Configures the interrupt level for match. Valid only when when
+         *  \hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\0:
+         *  itype=2. \\0: itype=2.
+         */
+        uint32_t match_value_interrupt:1;
+        /** match_choice_ecause : R/W; bitpos: [7:2]; default: 0;
+         *  Configures the ecause code for matching.
+         */
+        uint32_t match_choice_ecause:6;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} trace_filter_match_control_reg_t;
+
+/** Type of filter_comparator_control register
+ *  filter comparator match control register
+ */
+typedef union {
+    struct {
+        /** p_input : R/W; bitpos: [0]; default: 0;
+         *  Configures the input of the primary comparator for matching: \\0: iaddr \\1: tval\\
+         */
+        uint32_t p_input:1;
+        uint32_t reserved_1:1;
+        /** p_function : R/W; bitpos: [4:2]; default: 0;
+         *  Configures the function for the primary comparator. \\0: Equal, \\1: Not equal,
+         *  \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
+         *  equal, \\Other: Always match
+         */
+        uint32_t p_function:3;
+        /** p_notify : R/W; bitpos: [5]; default: 0;
+         *  Configure whether to explicitly report an instruction address matched against the
+         *  primary comparator. \\0:Not report \\1:Report
+         */
+        uint32_t p_notify:1;
+        uint32_t reserved_6:2;
+        /** s_input : R/W; bitpos: [8]; default: 0;
+         *  Configures the input of the secondary comparator for matching: \\0: iaddr \\1:
+         *  tval\\
+         */
+        uint32_t s_input:1;
+        uint32_t reserved_9:1;
+        /** s_function : R/W; bitpos: [12:10]; default: 0;
+         *  Configures the function for the secondary comparator. \\0: Equal, \\1: Not equal,
+         *  \\2: Less than, \\3: Less than or equal, \\4: Greater than, \\5: Greater than or
+         *  equal, \\Other: Always match
+         */
+        uint32_t s_function:3;
+        /** s_notify : R/W; bitpos: [13]; default: 0;
+         *  Generate a trace packet explicitly reporting the address that cause the secondary
+         *  match
+         */
+        uint32_t s_notify:1;
+        uint32_t reserved_14:2;
+        /** match_mode : R/W; bitpos: [17:16]; default: 0;
+         *  Configures the comparator match mode: \\0: Only the primary comparator matches \\1:
+         *  Both primary and secondary comparator matches(P\&\&S) \\ 2:Neither primary or
+         *  secondary comparator matches !(P\&\&S) \\3: Start filtering when the primary
+         *  comparator matches and stop filtering when the secondary comparator matches\\
+         */
+        uint32_t match_mode:2;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} trace_filter_comparator_control_reg_t;
+
+/** Type of filter_p_comparator_match register
+ *  primary comparator match value
+ */
+typedef union {
+    struct {
+        /** p_match : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the match value for the primary comparator
+         */
+        uint32_t p_match:32;
+    };
+    uint32_t val;
+} trace_filter_p_comparator_match_reg_t;
+
+/** Type of filter_s_comparator_match register
+ *  secondary comparator match value
+ */
+typedef union {
+    struct {
+        /** s_match : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the match value for the secondary comparator
+         */
+        uint32_t s_match:32;
+    };
+    uint32_t val;
+} trace_filter_s_comparator_match_reg_t;
+
+/** Type of resync_prolonged register
+ *  Resync configuration register
+ */
+typedef union {
+    struct {
+        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
+         *  Configures the threshold for synchronization counter
+         */
+        uint32_t resync_prolonged:24;
+        /** resync_mode : R/W; bitpos: [25:24]; default: 0;
+         *  Configures the synchronization mode: \\0: Disable the synchronization counter \\1:
+         *  Invalid \\2: Synchronization counter counts by packet  \\3: Synchronization counter
+         *  counts by cycle\\
+         */
+        uint32_t resync_mode:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} trace_resync_prolonged_reg_t;
+
+/** Type of ahb_config register
+ *  AHB config register
+ */
+typedef union {
+    struct {
+        /** hburst : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4
+         *  \\4:INCR8 \\Others:Invalid
+         */
+        uint32_t hburst:3;
+        /** max_incr : R/W; bitpos: [5:3]; default: 0;
+         *  Configures the maximum burst length for INCR mode
+         */
+        uint32_t max_incr:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} trace_ahb_config_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures register clock gating. \\0: Support clock only when the application
+         *  writes registers to save power. \\1:Always force the clock on for registers \\ This
+         *  bit doesn't affect register access.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35721984;
+         *  Version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} trace_date_reg_t;
+
+
+typedef struct {
+    volatile trace_mem_start_addr_reg_t mem_start_addr;
+    volatile trace_mem_end_addr_reg_t mem_end_addr;
+    volatile trace_mem_current_addr_reg_t mem_current_addr;
+    volatile trace_mem_addr_update_reg_t mem_addr_update;
+    volatile trace_fifo_status_reg_t fifo_status;
+    volatile trace_intr_ena_reg_t intr_ena;
+    volatile trace_intr_raw_reg_t intr_raw;
+    volatile trace_intr_clr_reg_t intr_clr;
+    volatile trace_trigger_reg_t trigger;
+    volatile trace_config_reg_t config;
+    volatile trace_filter_control_reg_t filter_control;
+    volatile trace_filter_match_control_reg_t filter_match_control;
+    volatile trace_filter_comparator_control_reg_t filter_comparator_control;
+    volatile trace_filter_p_comparator_match_reg_t filter_p_comparator_match;
+    volatile trace_filter_s_comparator_match_reg_t filter_s_comparator_match;
+    volatile trace_resync_prolonged_reg_t resync_prolonged;
+    volatile trace_ahb_config_reg_t ahb_config;
+    volatile trace_clock_gate_reg_t clock_gate;
+    uint32_t reserved_048[237];
+    volatile trace_date_reg_t date;
+} trace_dev_t;
+
+extern trace_dev_t TRACE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/uart_reg.h b/components/soc/esp32c61/register/soc/uart_reg.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/uart_reg.h
rename to components/soc/esp32c61/register/soc/uart_reg.h
diff --git a/components/soc/esp32c61/register/soc/uart_struct.h b/components/soc/esp32c61/register/soc/uart_struct.h
new file mode 100644
index 00000000000..1ed669c6f1c
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/uart_struct.h
@@ -0,0 +1,1349 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
+         *  Represents the data UART $n read from FIFO.\\
+         *  Measurement unit: byte.
+         */
+        uint32_t rxfifo_rd_byte:32;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable UART receiver's timeout function.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  Configures the amount of time that the bus can remain idle before timeout.\\
+         *  Measurement unit: bit time (the time to transmit 1 bit).
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of UART_RXFIFO_FULL_INT.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  The raw interrupt status of UART_TXFIFO_EMPTY_INT.
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of UART_PARITY_ERR_INT.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of UART_FRM_ERR_INT.
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of UART_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of UART_DSR_CHG_INT.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of UART_CTS_CHG_INT.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of UART_BRK_DET_INT.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt status of UART_RXFIFO_TOUT_INT.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt status of UART_SW_XON_INT.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  UART_SW_XOFF_INT.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt status of UART_GLITCH_DET_INT.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt status of UART_TX_BRK_DONE_INT.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt status of UART_TX_BRK_IDLE_DONE_INT.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw interrupt status of UART_TX_DONE_INT.
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw interrupt status of UART_RS485_PARITY_ERR_INT.
+         */
+        uint32_t rs485_parity_err_int_raw:1;
+        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw interrupt status of UART_RS485_FRM_ERR_INT.
+         */
+        uint32_t rs485_frm_err_int_raw:1;
+        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw interrupt status of UART_RS485_CLASH_INT.
+         */
+        uint32_t rs485_clash_int_raw:1;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw interrupt status of UART_AT_CMD_CHAR_DET_INT.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw interrupt status of UART_WAKEUP_INT.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of UART_RXFIFO_FULL_INT.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of UART_TXFIFO_EMPTY_INT.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of UART_PARITY_ERR_INT.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of UART_FRM_ERR_INT.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of UART_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of UART_DSR_CHG_INT.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of UART_CTS_CHG_INT.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of UART_BRK_DET_INT.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status of UART_RXFIFO_TOUT_INT.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status of UART_SW_XON_INT.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status of UART_SW_XOFF_INT.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status of UART_GLITCH_DET_INT.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status of UART_TX_BRK_DONE_INT.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status of UART_TX_BRK_IDLE_DONE_INT.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status of UART_TX_DONE_INT.
+         */
+        uint32_t tx_done_int_st:1;
+        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status of UART_RS485_PARITY_ERR_INT.
+         */
+        uint32_t rs485_parity_err_int_st:1;
+        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status of UART_RS485_FRM_ERR_INT.
+         */
+        uint32_t rs485_frm_err_int_st:1;
+        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status of UART_RS485_CLASH_INT.
+         */
+        uint32_t rs485_clash_int_st:1;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status of UART_AT_CMD_CHAR_DET_INT.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  The masked interrupt status of UART_WAKEUP_INT.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable UART_RXFIFO_FULL_INT.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable UART_TXFIFO_EMPTY_INT.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable UART_PARITY_ERR_INT.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable UART_FRM_ERR_INT.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable UART_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable UART_DSR_CHG_INT.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable UART_CTS_CHG_INT.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable UART_BRK_DET_INT.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable UART_RXFIFO_TOUT_INT.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable UART_SW_XON_INT.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable UART_SW_XOFF_INT.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable UART_GLITCH_DET_INT.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable UART_TX_BRK_DONE_INT.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable UART_TX_BRK_IDLE_DONE_INT.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable UART_TX_DONE_INT.
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Write 1 to enable UART_RS485_PARITY_ERR_INT.
+         */
+        uint32_t rs485_parity_err_int_ena:1;
+        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable UART_RS485_FRM_ERR_INT.
+         */
+        uint32_t rs485_frm_err_int_ena:1;
+        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable UART_RS485_CLASH_INT.
+         */
+        uint32_t rs485_clash_int_ena:1;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable UART_AT_CMD_CHAR_DET_INT.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  Write 1 to enable UART_WAKEUP_INT.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear UART_RXFIFO_FULL_INT.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear UART_TXFIFO_EMPTY_INT.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear UART_PARITY_ERR_INT.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear UART_FRM_ERR_INT.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear UART_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear UART_DSR_CHG_INT.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear UART_CTS_CHG_INT.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear UART_BRK_DET_INT.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear UART_RXFIFO_TOUT_INT.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear UART_SW_XON_INT.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear UART_SW_XOFF_INT.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear UART_GLITCH_DET_INT.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear UART_TX_BRK_DONE_INT.
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear UART_TX_BRK_IDLE_DONE_INT.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear UART_TX_DONE_INT.
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  Write 1 to clear UART_RS485_PARITY_ERR_INT.
+         */
+        uint32_t rs485_parity_err_int_clr:1;
+        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear UART_RS485_FRM_ERR_INT.
+         */
+        uint32_t rs485_frm_err_int_clr:1;
+        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear UART_RS485_CLASH_INT.
+         */
+        uint32_t rs485_clash_int_clr:1;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear UART_AT_CMD_CHAR_DET_INT.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Write 1 to clear UART_WAKEUP_INT.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  Configures the integral part of the divisor for baud rate generation.
+         */
+        uint32_t clkdiv_int:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  Configures the fractional part of the divisor for baud rate generation.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  RX filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  Configures the width of a pulse to be filtered.\\Measurement unit: UART Core's
+         *  clock cycle.\\Pulses whose width is lower than this value will be ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable RX signal filter.\\
+         *  0: Disable\\
+         *  1: Enable
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  Configuration register 0
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  Configures the parity check mode.\\
+         *  0: Even parity\\
+         *  1: Odd parity\\
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable UART parity check.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  Configures the number of data bits.\\
+         *  0: 5 bits\\
+         *  1: 6 bits\\
+         *  2: 7 bits\\
+         *  3: 8 bits\\
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  Configures the number of stop bits.\\
+         *  0: Invalid. No effect\\
+         *  1: 1 bits\\
+         *  2: 1.5 bits\\
+         *  3: 2 bits\\
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to send NULL characters when finishing data
+         *  transmission.\\
+         *  0: Not send\\
+         *  1: Send\\
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable IrDA loopback test.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable the IrDA transmitter.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [9]; default: 0;
+         *  Configures the 11th bit of the IrDA transmitter.\\
+         *  0: This bit is 0.\\
+         *  1: This bit is the same as the 10th bit.\\
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to invert the level of the IrDA transmitter.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert the level of the IrDA receiver.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable UART loopback test.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable flow control for the transmitter.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable IrDA protocol.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t irda_en:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to invert the level of UART RXD signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to invert the level of UART TXD signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to disable data overflow detection for the UART
+         *  receiver.\\
+         *  0: Enable\\
+         *  1: Disable\\
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to store the received data with errors into FIFO.\\
+         *  0: Store\\
+         *  1: Not store\\
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable baud rate detection.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable clock gating for UART memory.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  Configures the RTS signal used in software flow control.\\
+         *  0: The UART transmitter is allowed to send data.\\
+         *  1: The UART transmitted is not allowed to send data.\\
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to reset the UART RX FIFO.\\
+         *  0: Not reset\\
+         *  1: Reset\\
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to reset the UART TX FIFO.\\
+         *  0: Not reset\\
+         *  1: Reset\\
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
+         *  Configures the threshold for RX FIFO being full.\\Measurement unit: byte.
+         */
+        uint32_t rxfifo_full_thrhd:8;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
+         *  Configures the threshold for TX FIFO being empty.\\Measurement unit: byte.
+         */
+        uint32_t txfifo_empty_thrhd:8;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to invert the level of UART CTS signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to invert the level of UART DSR signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to invert the level of UART RTS signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to invert the level of UART DTR signal.\\
+         *  0: Not invert\\
+         *  1: Invert\\
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  Configures the DTR signal used in software flow control.\\
+         *  0: Data to be transmitted is not ready.\\
+         *  1: Data to be transmitted is ready.\\
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  Configures clock gating.\\
+         *  0: Support clock only when the application writes registers.\\
+         *  1: Always force the clock on for registers.\\
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow control configuration
+ */
+typedef union {
+    struct {
+        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the maximum number of data bytes that can be received  during hardware
+         *  flow control.\\Measurement unit: byte.
+         */
+        uint32_t rx_flow_thrhd:8;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable the UART receiver.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configuration register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  Configures wakeup character 1.
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  Configures wakeup character 2.
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  Configures wakeup character 3.
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  Configures wakeup character 4.
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configuration register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  Configures wakeup character 0.
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configuration register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  Configures the number of RXD edge changes to wake up the chip in wakeup mode 0.
+         */
+        uint32_t active_threshold:10;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
+         *  Configures the number of received data bytes to wake up the chip in wakeup mode 1.
+         */
+        uint32_t rx_wake_up_thrhd:8;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  Configures the number of wakeup characters.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  Configures whether or not to mask wakeup characters.\\
+         *  0: Not mask\\
+         *  1: Mask\\
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  Configures which wakeup mode to select.\\
+         *  0: Mode 0\\
+         *  1: Mode 1\\
+         *  2: Mode 2\\
+         *  3: Mode 3\\
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_character : R/W; bitpos: [7:0]; default: 17;
+         *  Configures the XON character for flow control.
+         */
+        uint32_t xon_character:8;
+        /** xoff_character : R/W; bitpos: [15:8]; default: 19;
+         *  Configures the XOFF character for flow control.
+         */
+        uint32_t xoff_character:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  Configures whether the UART transmitter can send XON or XOFF characters when it is
+         *  disabled.\\
+         *  0: Cannot send\\
+         *  1: Can send\\
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable software flow control.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to remove flow control characters from the received
+         *  data.\\
+         *  0: Not move\\
+         *  1: Move\\
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Configures whether the transmitter continues to sending data.\\
+         *  0: Not send\\
+         *  1: Send\\
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to stop the transmitter from sending data.\\
+         *  0: Not stop\\
+         *  1: Stop\\
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Configures whether or not to send XON characters.\\
+         *  0: Not send\\
+         *  1: Send\\
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Configures whether or not to send XOFF characters.\\
+         *  0: Not send\\
+         *  1: Send\\
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the threshold for data in RX FIFO to send XON characters in software
+         *  flow control.\\Measurement unit: byte.
+         */
+        uint32_t xon_threshold:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
+         *  Configures the threshold for data in RX FIFO to send XOFF characters in software
+         *  flow control.\\Measurement unit: byte.
+         */
+        uint32_t xoff_threshold:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  TX break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  Configures the number of NULL characters to be sent after finishing data
+         *  transmission.\\Valid only when UART_TXD_BRK is 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame end idle time configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  Configures the threshold to generate a frame end signal when the receiver takes
+         *  more time to receive one data byte data.\\Measurement unit: bit time (the time to
+         *  transmit 1 bit).
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  Configures the interval between two data transfers.\\Measurement unit: bit time
+         *  (the time to transmit 1 bit).
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable RS485 mode.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to add a turnaround delay of 1 bit before the start bit.\\
+         *  0: Not add\\
+         *  1: Add\\
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to add a turnaround delay of 1 bit after the stop bit.\\
+         *  0: Not add\\
+         *  1: Add\\
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable the receiver for data reception when the
+         *  transmitter is transmitting data in RS485 mode.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable the RS485 transmitter for data transmission when the
+         *  RS485 receiver is busy.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  Configures the delay of internal data signals in the receiver.\\Measurement unit:
+         *  bit time (the time to transmit 1 bit)..
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  Configures the delay of internal data signals in the transmitter.\\Measurement
+         *  unit: bit time (the time to transmit 1 bit).
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Configures whether or not to enable UART TX clock.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Configures whether or not to enable UART RX clock.\\
+         *  0: Disable\\
+         *  1: Enable\\
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 and then write 0 to reset UART TX.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 and then write 0 to reset UART RX.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
+         *  Represents the number of valid data bytes in RX FIFO.
+         */
+        uint32_t rxfifo_cnt:8;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  Represents the level of the internal UART DSR signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  Represents the level of the internal UART CTS signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  Represents the  level of the internal UART RXD signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
+         *  Represents the number of valid data bytes in RX FIFO.
+         */
+        uint32_t txfifo_cnt:8;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  Represents the level of the internal UART DTR signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  Represents the level of the internal UART RTS signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  Represents the  level of the internal UART TXD signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  TX FIFO write and read offset address
+ */
+typedef union {
+    struct {
+        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
+         *  Represents the offset address to write TX FIFO.
+         */
+        uint32_t tx_sram_waddr:8;
+        uint32_t reserved_8:1;
+        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
+         *  Represents the offset address to read TX FIFO.
+         */
+        uint32_t tx_sram_raddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx FIFO write and read offset address
+ */
+typedef union {
+    struct {
+        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
+         *  Represents the offset address to read RX FIFO.
+         */
+        uint32_t rx_sram_raddr:8;
+        uint32_t reserved_8:1;
+        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
+         *  Represents the offset address to write RX FIFO.
+         */
+        uint32_t rx_sram_waddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  Represents the status of the receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  Represents the status of the transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART asynchronous FIFO status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the APB TX asynchronous FIFO is full.\\
+         *  0: Not full\\
+         *  1: Full\\
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Represents whether or not the APB TX asynchronous FIFO is empty.\\
+         *  0: Not empty\\
+         *  1: Empty\\
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Represents whether or not the APB RX asynchronous FIFO is full.\\
+         *  0: Not full\\
+         *  1: Full\\
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Represents whether or not the APB RX asynchronous FIFO is empty.\\
+         *  0: Not empty\\
+         *  1: Empty\\
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  Configures the idle time before the receiver receives the first
+         *  AT_CMD.\\Measurement unit: bit time (the time to transmit 1 bit).
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  Configures the interval between the last AT_CMD and subsequent data.\\Measurement
+         *  unit: bit time (the time to transmit 1 bit).
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  Configures the interval between two AT_CMD characters.\\Measurement unit: bit time
+         *  (the time to transmit 1 bit).
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  Configures the AT_CMD character.
+         */
+        uint32_t at_cmd_char:8;
+        /** at_char_num : R/W; bitpos: [15:8]; default: 3;
+         *  Configures the number of continuous AT_CMD characters a receiver can receive.
+         */
+        uint32_t at_char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  Represents the minimal input clock counter value between two positive edges. It is
+         *  used for baud rate detection.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  Represents the minimal input clock counter value between two negative edges. It is
+         *  used for baud rate detection.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  Represents the minimum duration time of a low-level pulse. It is used for baud rate
+         *  detection.\\Measurement unit: APB_CLK clock cycle.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  Represents  the maximum duration time for a high-level pulse. It is used for baud
+         *  rate detection.\\Measurement unit: APB_CLK clock cycle.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  Represents the number of RXD edge changes. It is used for baud rate detection.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36774432;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART register configuration update
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether or not to synchronize registers.\\
+         *  0: Not synchronize\\
+         *  1: Synchronize\\
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  Configures the UART ID.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct uart_dev_s {
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_sync_reg_t conf0_sync;
+    volatile uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile uart_sleep_conf0_reg_t sleep_conf0;
+    volatile uart_sleep_conf1_reg_t sleep_conf1;
+    volatile uart_sleep_conf2_reg_t sleep_conf2;
+    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;
+    volatile uart_negpulse_reg_t negpulse;
+    volatile uart_lowpulse_reg_t lowpulse;
+    volatile uart_highpulse_reg_t highpulse;
+    volatile uart_rxd_cnt_reg_t rxd_cnt;
+    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_date_reg_t date;
+    volatile uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile uart_reg_update_reg_t reg_update;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+extern uart_dev_t UART2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h
new file mode 100644
index 00000000000..255d08ed4bb
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,1228 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
+ *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
+ *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
+ *  how many data is received, then read data from UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
+ *  USB Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFH_S  3
+/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFL_S  5
+/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+ *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+ *  through GPIO Matrix.
+ */
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
+ *  USB RCV value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
+ *  USB D+ rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_SERIAL_JTAG_CHIP_RST_REG register
+ *  CDC-ACM chip reset control.
+ */
+#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
+/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
+ *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_RTS    (BIT(0))
+#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
+#define USB_SERIAL_JTAG_RTS_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_S  0
+/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
+ *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_DTR    (BIT(1))
+#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
+#define USB_SERIAL_JTAG_DTR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_S  1
+/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable chip reset from usb serial channel to reset chip.
+ */
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
+ *  W0 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
+/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
+ *  W1 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
+/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
+/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_S  16
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
+ *  W0 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
+/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
+ *  W1 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
+/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
+/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
+
+/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
+ *  Configuration registers' value update
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
+/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this register would update the value of configure registers from APB
+ *  clock domain to 48MHz clock domain.
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
+
+/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
+ *  Serial AFIFO configure register
+ */
+#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
+ *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
+
+/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
+ *  USB Bus reset status register
+ */
+#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
+/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
+ *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+ *  reset is released.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
+
+/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG register
+ *  USB uart out endpoint timeout configuration.
+ */
+#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
+/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
+ *  is automatically cleared and reg_serial_timeout_status is asserted.
+ */
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S)
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_EN_S  0
+/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Serial out ep triggers a timeout event.
+ */
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S)
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_S  1
+/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear reg_serial_timeout_status.
+ */
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_STATUS_CLR_S  2
+
+/** USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG register
+ *  USB uart out endpoint timeout configuration.
+ */
+#define USB_SERIAL_JTAG_SERIAL_EP_TIMEOUT1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
+/** USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX : R/W; bitpos: [31:0]; default: 4800768;
+ *  USB serial out ep timeout max threshold value, indicates the maximum time that
+ *  waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
+ */
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_M  (USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V << USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S)
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_SERIAL_TIMEOUT_MAX_S  0
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  Date register
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368;
+ *  register version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h
similarity index 100%
rename from components/soc/esp32c61/include/soc/usb_serial_jtag_struct.h
rename to components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h
diff --git a/components/soc/esp32c61/register/soc/xts_aes_reg.h b/components/soc/esp32c61/register/soc/xts_aes_reg.h
new file mode 100644
index 00000000000..c3e08778d13
--- /dev/null
+++ b/components/soc/esp32c61/register/soc/xts_aes_reg.h
@@ -0,0 +1,128 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define XTS_AES_PLAIN_MEM(i)          (REG_SPI_MEM_BASE(i) + 0x300)
+/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This field is only used to generate include file in c case. This field is useles
+s. Please do not use this field..*/
+#define XTS_AES_PLAIN    0xFFFFFFFF
+#define XTS_AES_PLAIN_M  ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
+#define XTS_AES_PLAIN_V  0xFFFFFFFF
+#define XTS_AES_PLAIN_S  0
+
+#define XTS_AES_LINESIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x340)
+/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the line-size parameter which will be used in manual encryption
+ calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
+ 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
+#define XTS_AES_LINESIZE    0x00000003
+#define XTS_AES_LINESIZE_M  ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
+#define XTS_AES_LINESIZE_V  0x3
+#define XTS_AES_LINESIZE_S  0
+
+#define XTS_AES_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
+/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit stores the destination parameter which will be used in manual encryption
+n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
+used..*/
+#define XTS_AES_DESTINATION    (BIT(0))
+#define XTS_AES_DESTINATION_M  (BIT(0))
+#define XTS_AES_DESTINATION_V  0x1
+#define XTS_AES_DESTINATION_S  0
+
+#define XTS_AES_PHYSICAL_ADDRESS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x348)
+/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits stores the physical-address parameter which will be used in manual enc
+ryption calculation. This value should aligned with byte number decided by line-
+size parameter..*/
+#define XTS_AES_PHYSICAL_ADDRESS    0x03FFFFFF
+#define XTS_AES_PHYSICAL_ADDRESS_M  ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
+#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFF
+#define XTS_AES_PHYSICAL_ADDRESS_S  0
+
+#define XTS_AES_TRIGGER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34C)
+/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to trigger the process of manual encryption calculation. This actio
+n should only be asserted when manual encryption status is 0. After this action,
+ manual encryption status becomes 1. After calculation is done, manual encryption
+n status becomes 2..*/
+#define XTS_AES_TRIGGER    (BIT(0))
+#define XTS_AES_TRIGGER_M  (BIT(0))
+#define XTS_AES_TRIGGER_V  0x1
+#define XTS_AES_TRIGGER_S  0
+
+#define XTS_AES_RELEASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x350)
+/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to release encrypted result to mspi. This action should only be ass
+erted when manual encryption status is 2. After this action, manual encryption s
+tatus will become 3..*/
+#define XTS_AES_RELEASE    (BIT(0))
+#define XTS_AES_RELEASE_M  (BIT(0))
+#define XTS_AES_RELEASE_V  0x1
+#define XTS_AES_RELEASE_S  0
+
+#define XTS_AES_DESTROY_REG(i)          (REG_SPI_MEM_BASE(i) + 0x354)
+/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
+en manual encryption status is 3. After this action, manual encryption status wi
+ll become 0..*/
+#define XTS_AES_DESTROY    (BIT(0))
+#define XTS_AES_DESTROY_M  (BIT(0))
+#define XTS_AES_DESTROY_V  0x1
+#define XTS_AES_DESTROY_S  0
+
+#define XTS_AES_STATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x358)
+/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+ calculation, 2: encryption calculation is done but the encrypted result is invi
+sible to mspi, 3: the encrypted result is visible to mspi..*/
+#define XTS_AES_STATE    0x00000003
+#define XTS_AES_STATE_M  ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
+#define XTS_AES_STATE_V  0x3
+#define XTS_AES_STATE_S  0
+
+#define XTS_AES_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x35C)
+/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
+/*description: This bits stores the last modified-time of manual encryption feature..*/
+#define XTS_AES_DATE    0x3FFFFFFF
+#define XTS_AES_DATE_M  ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
+#define XTS_AES_DATE_V  0x3FFFFFFF
+
+#define XTS_AES_DPA_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x388)
+/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
+T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V  0x1
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S  4
+/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
+ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
+ing key 1..*/
+#define XTS_AES_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_V  0x1
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_S  3
+/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-
+7: The bigger the number is, the more secure the cryption is. (Note that the per
+formance of cryption will decrease together with this number increasing).*/
+#define XTS_AES_CRYPT_SECURITY_LEVEL    0x00000007
+#define XTS_AES_CRYPT_SECURITY_LEVEL_M  ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
+#define XTS_AES_CRYPT_SECURITY_LEVEL_V  0x7
+#define XTS_AES_CRYPT_SECURITY_LEVEL_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32c61/rtc_io_periph.c b/components/soc/esp32c61/rtc_io_periph.c
index 3bf421a892b..d997a25da74 100644
--- a/components/soc/esp32c61/rtc_io_periph.c
+++ b/components/soc/esp32c61/rtc_io_periph.c
@@ -29,4 +29,7 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
     -1,//GPIO19
     -1,//GPIO20
     -1,//GPIO21
+    -1,//GPIO22
+    -1,//GPIO23
+    -1,//GPIO24
 };
diff --git a/components/soc/esp32c61/spi_periph.c b/components/soc/esp32c61/spi_periph.c
index dc15ae60eaa..67fa9fdcb95 100644
--- a/components/soc/esp32c61/spi_periph.c
+++ b/components/soc/esp32c61/spi_periph.c
@@ -13,29 +13,6 @@
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
     {
         // MSPI has dedicated iomux pins
-        .spiclk_out = -1,
-        .spiclk_in = -1,
-        .spid_out = -1,
-        .spiq_out = -1,
-        .spiwp_out = -1,
-        .spihd_out = -1,
-        .spid_in = -1,
-        .spiq_in = -1,
-        .spiwp_in = -1,
-        .spihd_in = -1,
-        .spics_out = {-1},
-        .spics_in = -1,
-        .spiclk_iomux_pin = -1,
-        .spid_iomux_pin = -1,
-        .spiq_iomux_pin = -1,
-        .spiwp_iomux_pin = -1,
-        .spihd_iomux_pin = -1,
-        .spics0_iomux_pin = -1,
-        .irq = -1,
-        .irq_dma = -1,
-        .module = -1,
-        .hw = NULL,
-        .func = -1,
     }, {
         .spiclk_out = FSPICLK_OUT_IDX,
         .spiclk_in = FSPICLK_IN_IDX,
@@ -57,8 +34,50 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
         .irq = ETS_GPSPI2_INTR_SOURCE,
         .irq_dma = -1,
-        .module = -1,
         .hw = &GPSPI2,
         .func = SPI2_FUNC_NUM,
     },
 };
+
+/**
+ * Backup registers in Light sleep: (total cnt 12)
+ *
+ * cmd
+ * addr
+ * ctrl
+ * clock
+ * user
+ * user1
+ * user2
+ * ms_dlen
+ * misc
+ * dma_conf
+ * dma_int_ena
+ * slave
+ */
+#define SPI_RETENTION_REGS_CNT 12
+static const uint32_t spi_regs_map[4] = {0x31ff, 0x1000000, 0x0, 0x0};
+#define SPI_REG_RETENTION_ENTRIES(num) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
+                                               REG_SPI_BASE(num), REG_SPI_BASE(num), \
+                                               SPI_RETENTION_REGS_CNT, 0, 0, \
+                                               spi_regs_map[0], spi_regs_map[1], \
+                                               spi_regs_map[2], spi_regs_map[3]), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+    /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
+                                            SPI_DMA_INT_SET_REG(num), \
+                                            SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET , \
+                                            UINT32_MAX, 1, 0), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2);   // '2' for GPSPI2
+
+const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = {   // '-1' to except mspi
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI2,
+        .entry_array = spi2_regs_retention,
+        .array_size = ARRAY_SIZE(spi2_regs_retention),
+    },
+};
diff --git a/components/soc/esp32c61/uart_periph.c b/components/soc/esp32c61/uart_periph.c
index be396c4321f..a4e8c508411 100644
--- a/components/soc/esp32c61/uart_periph.c
+++ b/components/soc/esp32c61/uart_periph.c
@@ -150,10 +150,12 @@ static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTI
 
 const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_UART0,
         .regdma_entry_array = uart0_regdma_entries,
         .array_size = ARRAY_SIZE(uart0_regdma_entries),
     },
     [1] = {
+        .module = SLEEP_RETENTION_MODULE_UART1,
         .regdma_entry_array = uart1_regdma_entries,
         .array_size = ARRAY_SIZE(uart1_regdma_entries),
     },
diff --git a/components/soc/esp32h2/etm_periph.c b/components/soc/esp32h2/etm_periph.c
new file mode 100644
index 00000000000..7b268c443a5
--- /dev/null
+++ b/components/soc/esp32h2/etm_periph.c
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/etm_periph.h"
+#include "soc/soc_etm_reg.h"
+
+/**
+ * ETM Registers to be saved during sleep retention
+ * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
+*/
+#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
+
+static const regdma_entries_config_t etm_regdma_entries[] = {
+    // backup stage: save the status of enabled channels
+    // restore stage: store the enabled channels
+    [0] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
+        SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    [1] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
+        SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
+        SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+};
+
+const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = {
+    [0] = {
+        .module = SLEEP_RETENTION_MODULE_ETM0,
+        .regdma_entry_array = etm_regdma_entries,
+        .array_size = ARRAY_SIZE(etm_regdma_entries)
+    },
+};
diff --git a/components/soc/esp32h2/i2c_periph.c b/components/soc/esp32h2/i2c_periph.c
index f1fd089056a..5afb3995eb3 100644
--- a/components/soc/esp32h2/i2c_periph.c
+++ b/components/soc/esp32h2/i2c_periph.c
@@ -47,7 +47,7 @@ static const regdma_entries_config_t i2c0_regs_retention[] = {
     [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
            .owner = ENTRY(0) | ENTRY(2) }, \
     [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
-    .owner = ENTRY(0) | ENTRY(2) }, \
+           .owner = ENTRY(0) | ENTRY(2) }, \
     [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
            .owner = ENTRY(0) | ENTRY(2) }, \
     [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
@@ -71,6 +71,6 @@ static const regdma_entries_config_t i2c1_regs_retention[] = {
 };
 
 const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
-    {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention)},
-    {i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention)},
+    {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
+    {i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention), SLEEP_RETENTION_MODULE_I2C1},
 };
diff --git a/components/soc/esp32h2/i2s_periph.c b/components/soc/esp32h2/i2s_periph.c
index 6e9b12c4879..818b4e1080a 100644
--- a/components/soc/esp32h2/i2s_periph.c
+++ b/components/soc/esp32h2/i2s_periph.c
@@ -29,7 +29,7 @@ const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
         .data_out_sig = I2SO_SD_OUT_IDX,
         .data_in_sig  = I2SI_SD_IN_IDX,
 
-        .irq          = ETS_I2S1_INTR_SOURCE,
+        .irq          = ETS_I2S0_INTR_SOURCE,
     }
 };
 
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index ab711151065..1d1006f26ba 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -467,6 +467,10 @@ config SOC_ETM_CHANNELS_PER_GROUP
     int
     default 50
 
+config SOC_ETM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_GPIO_PORT
     int
     default 1
@@ -687,6 +691,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 6
@@ -711,6 +719,10 @@ config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
     int
     default 10
 
+config SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED
     bool
     default n
@@ -751,6 +763,10 @@ config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
     bool
     default y
 
+config SOC_PCNT_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_RMT_GROUPS
     int
     default 1
@@ -863,6 +879,10 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
     bool
     default y
 
+config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_PARLIO_GROUPS
     int
     default 1
@@ -899,6 +919,10 @@ config SOC_PARLIO_TRANS_BIT_ALIGN
     bool
     default y
 
+config SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MPI_MEM_BLOCKS_NUM
     int
     default 4
@@ -987,6 +1011,10 @@ config SOC_SPI_SUPPORT_SLAVE_HD_VER2
     bool
     default y
 
+config SOC_SPI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_SPI_SUPPORT_CLK_XTAL
     bool
     default y
@@ -1171,6 +1199,10 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
     bool
     default y
 
+config SOC_TWAI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_EFUSE_DIS_PAD_JTAG
     bool
     default y
@@ -1395,6 +1427,10 @@ config SOC_CLK_LP_FAST_SUPPORT_LP_PLL
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    bool
+    default y
+
 config SOC_MODEM_CLOCK_IS_INDEPENDENT
     bool
     default y
@@ -1403,6 +1439,10 @@ config SOC_RCC_IS_INDEPENDENT
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y
@@ -1419,6 +1459,14 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM
     bool
     default y
 
+config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
+config SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN
+    bool
+    default y
+
 config SOC_RNG_CLOCK_IS_INDEPENDENT
     bool
     default y
@@ -1454,3 +1502,7 @@ config SOC_BLE_MULTI_CONN_OPTIMIZATION
 config SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED
     bool
     default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
diff --git a/components/soc/esp32h2/include/soc/assist_debug_reg.h b/components/soc/esp32h2/include/soc/assist_debug_reg.h
deleted file mode 100644
index 8e0426dc6f5..00000000000
--- a/components/soc/esp32h2/include/soc/assist_debug_reg.h
+++ /dev/null
@@ -1,777 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
- *  core0 monitor enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
- *  IBUS busy monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor enbale
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
- *  core0 monitor interrupt status register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
- *  DBUS busy monitor initerrupt status
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
- *  core0 monitor interrupt enable register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt enbale
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
-
-/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
- *  core0 monitor interrupt clr register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
- *  IBUS busy monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
- *  core0 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 dram0 region0 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
- *  core0 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 dram0 region0 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
- *  core0 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 dram0 region1 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
- *  core0 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 dram0 region1 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
- *  core0 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 PIF region0 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
- *  core0 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 PIF region0 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
- *  core0 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 PIF region1 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
- *  core0 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 PIF region1 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
- *  core0 area pc status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
-/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
- *  the stackpointer when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
- *  core0 area sp status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
-/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
- *  the PC when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
- *  stack min value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
-/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
- *  stack max value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
-/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
- *  core0 sp pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
- *  stack monitor pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
-/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
- *  record enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
-/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable record PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
- *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
- *  recorded PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
- *  recorded sp
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
-
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_iram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_iram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
- *  reg_core_0_iram0_recording_loadstore_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
-
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_iram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_iram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
- *  reg_core_0_iram0_recording_loadstore_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register2
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_dram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_dram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  24
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
- *  reg_core_0_dram0_recording_byteen_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register3
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_0_dram0_recording_pc_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
- *  exception monitor status register4
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_dram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_dram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  24
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
- *  reg_core_0_dram0_recording_byteen_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000000FU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
- *  exception monitor status register5
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_0_dram0_recording_pc_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
-
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register6
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
- *  reg_core_x_iram0_dram0_limit_cycle_0
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
-
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register7
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
- *  reg_core_x_iram0_dram0_limit_cycle_1
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
-
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
- *  cpu's lastpc before exception
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
-
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
- *  cpu debug mode status, 1 means cpu enter debug mode.
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
- *  cpu debug_module active status
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
-
-/** ASSIST_DEBUG_CLOCK_GATE_REG register
- *  clock register
- */
-#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
-/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 force on the clock gate
- */
-#define ASSIST_DEBUG_CLK_EN    (BIT(0))
-#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
-#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
-#define ASSIST_DEBUG_CLK_EN_S  0
-
-/** ASSIST_DEBUG_DATE_REG register
- *  version register
- */
-#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
-/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
- *  version register
- */
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/assist_debug_struct.h b/components/soc/esp32h2/include/soc/assist_debug_struct.h
deleted file mode 100644
index c03f5792292..00000000000
--- a/components/soc/esp32h2/include/soc/assist_debug_struct.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: monitor configuration registers */
-/** Type of core_0_intr_ena register
- *  core0 monitor enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor enable
-         */
-        uint32_t core_0_area_dram0_0_rd_ena:1;
-        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor enable
-         */
-        uint32_t core_0_area_dram0_0_wr_ena:1;
-        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor enable
-         */
-        uint32_t core_0_area_dram0_1_rd_ena:1;
-        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor enable
-         */
-        uint32_t core_0_area_dram0_1_wr_ena:1;
-        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor enable
-         */
-        uint32_t core_0_area_pif_0_rd_ena:1;
-        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor enable
-         */
-        uint32_t core_0_area_pif_0_wr_ena:1;
-        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor enable
-         */
-        uint32_t core_0_area_pif_1_rd_ena:1;
-        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor enable
-         */
-        uint32_t core_0_area_pif_1_wr_ena:1;
-        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor enable
-         */
-        uint32_t core_0_sp_spill_min_ena:1;
-        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor enable
-         */
-        uint32_t core_0_sp_spill_max_ena:1;
-        /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
-         *  IBUS busy monitor enable
-         */
-        uint32_t core_0_iram0_exception_monitor_ena:1;
-        /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor enbale
-         */
-        uint32_t core_0_dram0_exception_monitor_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_ena_reg_t;
-
-/** Type of core_0_area_dram0_0_min register
- *  core0 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 dram0 region0 start addr
-         */
-        uint32_t core_0_area_dram0_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_min_reg_t;
-
-/** Type of core_0_area_dram0_0_max register
- *  core0 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 dram0 region0 end addr
-         */
-        uint32_t core_0_area_dram0_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_max_reg_t;
-
-/** Type of core_0_area_dram0_1_min register
- *  core0 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 dram0 region1 start addr
-         */
-        uint32_t core_0_area_dram0_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_min_reg_t;
-
-/** Type of core_0_area_dram0_1_max register
- *  core0 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 dram0 region1 end addr
-         */
-        uint32_t core_0_area_dram0_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_max_reg_t;
-
-/** Type of core_0_area_pif_0_min register
- *  core0 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 PIF region0 start addr
-         */
-        uint32_t core_0_area_pif_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_min_reg_t;
-
-/** Type of core_0_area_pif_0_max register
- *  core0 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 PIF region0 end addr
-         */
-        uint32_t core_0_area_pif_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_max_reg_t;
-
-/** Type of core_0_area_pif_1_min register
- *  core0 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 PIF region1 start addr
-         */
-        uint32_t core_0_area_pif_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_min_reg_t;
-
-/** Type of core_0_area_pif_1_max register
- *  core0 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 PIF region1 end addr
-         */
-        uint32_t core_0_area_pif_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_max_reg_t;
-
-/** Type of core_0_area_pc register
- *  core0 area pc status register
- */
-typedef union {
-    struct {
-        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
-         *  the stackpointer when first touch region monitor interrupt
-         */
-        uint32_t core_0_area_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pc_reg_t;
-
-/** Type of core_0_area_sp register
- *  core0 area sp status register
- */
-typedef union {
-    struct {
-        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
-         *  the PC when first touch region monitor interrupt
-         */
-        uint32_t core_0_area_sp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_sp_reg_t;
-
-/** Type of core_0_sp_min register
- *  stack min value
- */
-typedef union {
-    struct {
-        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core0 sp region configuration regsiter
-         */
-        uint32_t core_0_sp_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_min_reg_t;
-
-/** Type of core_0_sp_max register
- *  stack max value
- */
-typedef union {
-    struct {
-        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
-         *  core0 sp pc status register
-         */
-        uint32_t core_0_sp_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_max_reg_t;
-
-/** Type of core_0_sp_pc register
- *  stack monitor pc status register
- */
-typedef union {
-    struct {
-        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
-         */
-        uint32_t core_0_sp_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_pc_reg_t;
-
-
-/** Group: interrupt configuration register */
-/** Type of core_0_intr_raw register
- *  core0 monitor interrupt status register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_0_rd_raw:1;
-        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_0_wr_raw:1;
-        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_1_rd_raw:1;
-        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_1_wr_raw:1;
-        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt status
-         */
-        uint32_t core_0_area_pif_0_rd_raw:1;
-        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt status
-         */
-        uint32_t core_0_area_pif_0_wr_raw:1;
-        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt status
-         */
-        uint32_t core_0_area_pif_1_rd_raw:1;
-        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt status
-         */
-        uint32_t core_0_area_pif_1_wr_raw:1;
-        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt status
-         */
-        uint32_t core_0_sp_spill_min_raw:1;
-        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt status
-         */
-        uint32_t core_0_sp_spill_max_raw:1;
-        /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt status
-         */
-        uint32_t core_0_iram0_exception_monitor_raw:1;
-        /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
-         *  DBUS busy monitor initerrupt status
-         */
-        uint32_t core_0_dram0_exception_monitor_raw:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_raw_reg_t;
-
-/** Type of core_0_intr_rls register
- *  core0 monitor interrupt enable register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_rd_rls:1;
-        /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_wr_rls:1;
-        /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_rd_rls:1;
-        /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_wr_rls:1;
-        /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_rd_rls:1;
-        /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_wr_rls:1;
-        /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_rd_rls:1;
-        /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_wr_rls:1;
-        /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_min_rls:1;
-        /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_max_rls:1;
-        /** core_0_iram0_exception_monitor_rls : R/W; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt enable
-         */
-        uint32_t core_0_iram0_exception_monitor_rls:1;
-        /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt enbale
-         */
-        uint32_t core_0_dram0_exception_monitor_rls:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_rls_reg_t;
-
-/** Type of core_0_intr_clr register
- *  core0 monitor interrupt clr register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_0_rd_clr:1;
-        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_0_wr_clr:1;
-        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_1_rd_clr:1;
-        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_1_wr_clr:1;
-        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_0_rd_clr:1;
-        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_0_wr_clr:1;
-        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_1_rd_clr:1;
-        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_1_wr_clr:1;
-        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt clr
-         */
-        uint32_t core_0_sp_spill_min_clr:1;
-        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt clr
-         */
-        uint32_t core_0_sp_spill_max_clr:1;
-        /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
-         *  IBUS busy monitor interrupt clr
-         */
-        uint32_t core_0_iram0_exception_monitor_clr:1;
-        /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt clr
-         */
-        uint32_t core_0_dram0_exception_monitor_clr:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_clr_reg_t;
-
-
-/** Group: pc reording configuration register */
-/** Type of core_0_rcd_en register
- *  record enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable record PC
-         */
-        uint32_t core_0_rcd_recorden:1;
-        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
-         */
-        uint32_t core_0_rcd_pdebugen:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_en_reg_t;
-
-
-/** Group: pc reording status register */
-/** Type of core_0_rcd_pdebugpc register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
-         *  recorded PC
-         */
-        uint32_t core_0_rcd_pdebugpc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugpc_reg_t;
-
-/** Type of core_0_rcd_pdebugsp register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
-         *  recorded sp
-         */
-        uint32_t core_0_rcd_pdebugsp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugsp_reg_t;
-
-
-/** Group: exception monitor regsiter */
-/** Type of core_0_iram0_exception_monitor_0 register
- *  exception monitor status register0
- */
-typedef union {
-    struct {
-        /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_iram0_recording_addr_0
-         */
-        uint32_t core_0_iram0_recording_addr_0:24;
-        /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_iram0_recording_wr_0
-         */
-        uint32_t core_0_iram0_recording_wr_0:1;
-        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
-         *  reg_core_0_iram0_recording_loadstore_0
-         */
-        uint32_t core_0_iram0_recording_loadstore_0:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
-
-/** Type of core_0_iram0_exception_monitor_1 register
- *  exception monitor status register1
- */
-typedef union {
-    struct {
-        /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_iram0_recording_addr_1
-         */
-        uint32_t core_0_iram0_recording_addr_1:24;
-        /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_iram0_recording_wr_1
-         */
-        uint32_t core_0_iram0_recording_wr_1:1;
-        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
-         *  reg_core_0_iram0_recording_loadstore_1
-         */
-        uint32_t core_0_iram0_recording_loadstore_1:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_0 register
- *  exception monitor status register2
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_dram0_recording_addr_0
-         */
-        uint32_t core_0_dram0_recording_addr_0:24;
-        /** core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_dram0_recording_wr_0
-         */
-        uint32_t core_0_dram0_recording_wr_0:1;
-        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0;
-         *  reg_core_0_dram0_recording_byteen_0
-         */
-        uint32_t core_0_dram0_recording_byteen_0:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_1 register
- *  exception monitor status register3
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_0_dram0_recording_pc_0
-         */
-        uint32_t core_0_dram0_recording_pc_0:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_2 register
- *  exception monitor status register4
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_dram0_recording_addr_1
-         */
-        uint32_t core_0_dram0_recording_addr_1:24;
-        /** core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_dram0_recording_wr_1
-         */
-        uint32_t core_0_dram0_recording_wr_1:1;
-        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0;
-         *  reg_core_0_dram0_recording_byteen_1
-         */
-        uint32_t core_0_dram0_recording_byteen_1:4;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_3 register
- *  exception monitor status register5
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_0_dram0_recording_pc_1
-         */
-        uint32_t core_0_dram0_recording_pc_1:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
-
-/** Type of core_x_iram0_dram0_exception_monitor_0 register
- *  exception monitor status register6
- */
-typedef union {
-    struct {
-        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
-         *  reg_core_x_iram0_dram0_limit_cycle_0
-         */
-        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_x_iram0_dram0_exception_monitor_1 register
- *  exception monitor status register7
- */
-typedef union {
-    struct {
-        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
-         *  reg_core_x_iram0_dram0_limit_cycle_1
-         */
-        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
-
-
-/** Group: cpu status registers */
-/** Type of core_0_lastpc_before_exception register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
-         *  cpu's lastpc before exception
-         */
-        uint32_t core_0_lastpc_before_exc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_lastpc_before_exception_reg_t;
-
-/** Type of core_0_debug_mode register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
-         *  cpu debug mode status, 1 means cpu enter debug mode.
-         */
-        uint32_t core_0_debug_mode:1;
-        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
-         *  cpu debug_module active status
-         */
-        uint32_t core_0_debug_module_active:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_debug_mode_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of clock_gate register
- *  clock register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 force on the clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} assist_debug_clock_gate_reg_t;
-
-/** Type of date register
- *  version register
- */
-typedef union {
-    struct {
-        /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
-         *  version register
-         */
-        uint32_t assist_debug_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} assist_debug_date_reg_t;
-
-
-typedef struct {
-    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
-    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
-    volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
-    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
-    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
-    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
-    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
-    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
-    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
-    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
-    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
-    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
-    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
-    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
-    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
-    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
-    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
-    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
-    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
-    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
-    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
-    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
-    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
-    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
-    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
-    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
-    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
-    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
-    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
-    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
-    volatile assist_debug_clock_gate_reg_t clock_gate;
-    uint32_t reserved_07c[224];
-    volatile assist_debug_date_reg_t date;
-} assist_debug_dev_t;
-
-extern assist_debug_dev_t ASSIST_DEBUG;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/cache_reg.h b/components/soc/esp32h2/include/soc/cache_reg.h
deleted file mode 100644
index d811eda10af..00000000000
--- a/components/soc/esp32h2/include/soc/cache_reg.h
+++ /dev/null
@@ -1,6235 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** CACHE_L1_ICACHE_CTRL_REG register
- *  L1 instruction Cache(L1-ICache) control register
- */
-#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
-/** CACHE_L1_ICACHE_SHUT_IBUS0 : HRO; bitpos: [0]; default: 0;
- *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
-#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
-/** CACHE_L1_ICACHE_SHUT_IBUS1 : HRO; bitpos: [1]; default: 0;
- *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
-#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
-/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
-#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
-/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
-#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
-/** CACHE_L1_ICACHE_UNDEF_OP : HRO; bitpos: [7:4]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE_UNDEF_OP    0x0000000FU
-#define CACHE_L1_ICACHE_UNDEF_OP_M  (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S)
-#define CACHE_L1_ICACHE_UNDEF_OP_V  0x0000000FU
-#define CACHE_L1_ICACHE_UNDEF_OP_S  4
-
-/** CACHE_L1_CACHE_CTRL_REG register
- *  L1 data Cache(L1-Cache) control register
- */
-#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
-/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0;
- *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
- */
-#define CACHE_L1_CACHE_SHUT_BUS0    (BIT(0))
-#define CACHE_L1_CACHE_SHUT_BUS0_M  (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S)
-#define CACHE_L1_CACHE_SHUT_BUS0_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_BUS0_S  0
-/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0;
- *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
- */
-#define CACHE_L1_CACHE_SHUT_BUS1    (BIT(1))
-#define CACHE_L1_CACHE_SHUT_BUS1_M  (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S)
-#define CACHE_L1_CACHE_SHUT_BUS1_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_BUS1_S  1
-/** CACHE_L1_CACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_CACHE_SHUT_DBUS2    (BIT(2))
-#define CACHE_L1_CACHE_SHUT_DBUS2_M  (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S)
-#define CACHE_L1_CACHE_SHUT_DBUS2_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_DBUS2_S  2
-/** CACHE_L1_CACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_CACHE_SHUT_DBUS3    (BIT(3))
-#define CACHE_L1_CACHE_SHUT_DBUS3_M  (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S)
-#define CACHE_L1_CACHE_SHUT_DBUS3_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_DBUS3_S  3
-/** CACHE_L1_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0;
- *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
- */
-#define CACHE_L1_CACHE_SHUT_DMA    (BIT(4))
-#define CACHE_L1_CACHE_SHUT_DMA_M  (CACHE_L1_CACHE_SHUT_DMA_V << CACHE_L1_CACHE_SHUT_DMA_S)
-#define CACHE_L1_CACHE_SHUT_DMA_V  0x00000001U
-#define CACHE_L1_CACHE_SHUT_DMA_S  4
-/** CACHE_L1_CACHE_UNDEF_OP : R/W; bitpos: [11:8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_CACHE_UNDEF_OP    0x0000000FU
-#define CACHE_L1_CACHE_UNDEF_OP_M  (CACHE_L1_CACHE_UNDEF_OP_V << CACHE_L1_CACHE_UNDEF_OP_S)
-#define CACHE_L1_CACHE_UNDEF_OP_V  0x0000000FU
-#define CACHE_L1_CACHE_UNDEF_OP_S  8
-
-/** CACHE_L1_BYPASS_CACHE_CONF_REG register
- *  Bypass Cache configure register
- */
-#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
-/** CACHE_BYPASS_L1_ICACHE0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
-#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
-#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
-/** CACHE_BYPASS_L1_ICACHE1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
-#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
-#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
-/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
-#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
-#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
-/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
-#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
-#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
-/** CACHE_BYPASS_L1_DCACHE_EN : HRO; bitpos: [4]; default: 0;
- *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
-#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
-#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_DCACHE_EN_S  4
-
-/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
- *  L1 Cache atomic feature configure register
- */
-#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
-/** CACHE_L1_CACHE_ATOMIC_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
- *  L1-Cache.  1: disable, 1: enable.
- */
-#define CACHE_L1_CACHE_ATOMIC_EN    (BIT(0))
-#define CACHE_L1_CACHE_ATOMIC_EN_M  (CACHE_L1_CACHE_ATOMIC_EN_V << CACHE_L1_CACHE_ATOMIC_EN_S)
-#define CACHE_L1_CACHE_ATOMIC_EN_V  0x00000001U
-#define CACHE_L1_CACHE_ATOMIC_EN_S  0
-
-/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
- *  L1 instruction Cache CacheSize mode configure register
- */
-#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
-/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(0))
-#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_1K_S  0
-/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(1))
-#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_2K_S  1
-/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(2))
-#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_4K_S  2
-/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(3))
-#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_8K_S  3
-/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(4))
-#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_16K_S  4
-/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(5))
-#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_32K_S  5
-/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(6))
-#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_64K_S  6
-/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(7))
-#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_128K_S  7
-/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(8))
-#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_256K_S  8
-/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(9))
-#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_512K_S  9
-/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
- *  and all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(10))
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  10
-/** CACHE_L1_ICACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
- *  and all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_2048K    (BIT(11))
-#define CACHE_L1_ICACHE_CACHESIZE_2048K_M  (CACHE_L1_ICACHE_CACHESIZE_2048K_V << CACHE_L1_ICACHE_CACHESIZE_2048K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_2048K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_2048K_S  11
-/** CACHE_L1_ICACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
- *  and all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_4096K    (BIT(12))
-#define CACHE_L1_ICACHE_CACHESIZE_4096K_M  (CACHE_L1_ICACHE_CACHESIZE_4096K_V << CACHE_L1_ICACHE_CACHESIZE_4096K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_4096K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_4096K_S  12
-
-/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
- *  L1 instruction Cache BlockSize mode configure register
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
-/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
-/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
-/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
-/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
-/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
-/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L1_CACHE_CACHESIZE_CONF_REG register
- *  L1 data Cache CacheSize mode configure register
- */
-#define CACHE_L1_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
-/** CACHE_L1_CACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_1K    (BIT(0))
-#define CACHE_L1_CACHE_CACHESIZE_1K_M  (CACHE_L1_CACHE_CACHESIZE_1K_V << CACHE_L1_CACHE_CACHESIZE_1K_S)
-#define CACHE_L1_CACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_1K_S  0
-/** CACHE_L1_CACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_2K    (BIT(1))
-#define CACHE_L1_CACHE_CACHESIZE_2K_M  (CACHE_L1_CACHE_CACHESIZE_2K_V << CACHE_L1_CACHE_CACHESIZE_2K_S)
-#define CACHE_L1_CACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_2K_S  1
-/** CACHE_L1_CACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_4K    (BIT(2))
-#define CACHE_L1_CACHE_CACHESIZE_4K_M  (CACHE_L1_CACHE_CACHESIZE_4K_V << CACHE_L1_CACHE_CACHESIZE_4K_S)
-#define CACHE_L1_CACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_4K_S  2
-/** CACHE_L1_CACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_8K    (BIT(3))
-#define CACHE_L1_CACHE_CACHESIZE_8K_M  (CACHE_L1_CACHE_CACHESIZE_8K_V << CACHE_L1_CACHE_CACHESIZE_8K_S)
-#define CACHE_L1_CACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_8K_S  3
-/** CACHE_L1_CACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 1;
- *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_16K    (BIT(4))
-#define CACHE_L1_CACHE_CACHESIZE_16K_M  (CACHE_L1_CACHE_CACHESIZE_16K_V << CACHE_L1_CACHE_CACHESIZE_16K_S)
-#define CACHE_L1_CACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_16K_S  4
-/** CACHE_L1_CACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_32K    (BIT(5))
-#define CACHE_L1_CACHE_CACHESIZE_32K_M  (CACHE_L1_CACHE_CACHESIZE_32K_V << CACHE_L1_CACHE_CACHESIZE_32K_S)
-#define CACHE_L1_CACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_32K_S  5
-/** CACHE_L1_CACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_64K    (BIT(6))
-#define CACHE_L1_CACHE_CACHESIZE_64K_M  (CACHE_L1_CACHE_CACHESIZE_64K_V << CACHE_L1_CACHE_CACHESIZE_64K_S)
-#define CACHE_L1_CACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_64K_S  6
-/** CACHE_L1_CACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_128K    (BIT(7))
-#define CACHE_L1_CACHE_CACHESIZE_128K_M  (CACHE_L1_CACHE_CACHESIZE_128K_V << CACHE_L1_CACHE_CACHESIZE_128K_S)
-#define CACHE_L1_CACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_128K_S  7
-/** CACHE_L1_CACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_256K    (BIT(8))
-#define CACHE_L1_CACHE_CACHESIZE_256K_M  (CACHE_L1_CACHE_CACHESIZE_256K_V << CACHE_L1_CACHE_CACHESIZE_256K_S)
-#define CACHE_L1_CACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_256K_S  8
-/** CACHE_L1_CACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_512K    (BIT(9))
-#define CACHE_L1_CACHE_CACHESIZE_512K_M  (CACHE_L1_CACHE_CACHESIZE_512K_V << CACHE_L1_CACHE_CACHESIZE_512K_S)
-#define CACHE_L1_CACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_512K_S  9
-/** CACHE_L1_CACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_1024K    (BIT(10))
-#define CACHE_L1_CACHE_CACHESIZE_1024K_M  (CACHE_L1_CACHE_CACHESIZE_1024K_V << CACHE_L1_CACHE_CACHESIZE_1024K_S)
-#define CACHE_L1_CACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_1024K_S  10
-/** CACHE_L1_CACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_2048K    (BIT(11))
-#define CACHE_L1_CACHE_CACHESIZE_2048K_M  (CACHE_L1_CACHE_CACHESIZE_2048K_V << CACHE_L1_CACHE_CACHESIZE_2048K_S)
-#define CACHE_L1_CACHE_CACHESIZE_2048K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_2048K_S  11
-/** CACHE_L1_CACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_CACHESIZE_4096K    (BIT(12))
-#define CACHE_L1_CACHE_CACHESIZE_4096K_M  (CACHE_L1_CACHE_CACHESIZE_4096K_V << CACHE_L1_CACHE_CACHESIZE_4096K_S)
-#define CACHE_L1_CACHE_CACHESIZE_4096K_V  0x00000001U
-#define CACHE_L1_CACHE_CACHESIZE_4096K_S  12
-
-/** CACHE_L1_CACHE_BLOCKSIZE_CONF_REG register
- *  L1 data Cache BlockSize mode configure register
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
-/** CACHE_L1_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L1_CACHE_BLOCKSIZE_8_M  (CACHE_L1_CACHE_BLOCKSIZE_8_V << CACHE_L1_CACHE_BLOCKSIZE_8_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_8_S  0
-/** CACHE_L1_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L1_CACHE_BLOCKSIZE_16_M  (CACHE_L1_CACHE_BLOCKSIZE_16_V << CACHE_L1_CACHE_BLOCKSIZE_16_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_16_S  1
-/** CACHE_L1_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 1;
- *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L1_CACHE_BLOCKSIZE_32_M  (CACHE_L1_CACHE_BLOCKSIZE_32_V << CACHE_L1_CACHE_BLOCKSIZE_32_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_32_S  2
-/** CACHE_L1_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L1_CACHE_BLOCKSIZE_64_M  (CACHE_L1_CACHE_BLOCKSIZE_64_V << CACHE_L1_CACHE_BLOCKSIZE_64_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_64_S  3
-/** CACHE_L1_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L1_CACHE_BLOCKSIZE_128_M  (CACHE_L1_CACHE_BLOCKSIZE_128_V << CACHE_L1_CACHE_BLOCKSIZE_128_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_128_S  4
-/** CACHE_L1_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_CACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L1_CACHE_BLOCKSIZE_256_M  (CACHE_L1_CACHE_BLOCKSIZE_256_V << CACHE_L1_CACHE_BLOCKSIZE_256_S)
-#define CACHE_L1_CACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L1_CACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
-/** CACHE_L1_ICACHE0_WRAP : HRO; bitpos: [0]; default: 0;
- *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
- */
-#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
-#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
-#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE0_WRAP_S  0
-/** CACHE_L1_ICACHE1_WRAP : HRO; bitpos: [1]; default: 0;
- *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
- */
-#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
-#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
-#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE1_WRAP_S  1
-/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
-#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
-#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE2_WRAP_S  2
-/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
-#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
-#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE3_WRAP_S  3
-/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0;
- *  Set this bit as 1 to enable L1-DCache wrap around mode.
- */
-#define CACHE_L1_CACHE_WRAP    (BIT(4))
-#define CACHE_L1_CACHE_WRAP_M  (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S)
-#define CACHE_L1_CACHE_WRAP_V  0x00000001U
-#define CACHE_L1_CACHE_WRAP_S  4
-
-/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register
- *  Cache tag memory power control register
- */
-#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
-/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON : HRO; bitpos: [0]; default: 1;
- *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON    (BIT(0))
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S  0
-/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD : HRO; bitpos: [1]; default: 0;
- *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD    (BIT(1))
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S  1
-/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU : HRO; bitpos: [2]; default: 1;
- *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU    (BIT(2))
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S  2
-/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON : HRO; bitpos: [4]; default: 1;
- *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON    (BIT(4))
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S  4
-/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD : HRO; bitpos: [5]; default: 0;
- *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD    (BIT(5))
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S  5
-/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU : HRO; bitpos: [6]; default: 1;
- *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU    (BIT(6))
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S  6
-/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON    (BIT(8))
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S  8
-/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD    (BIT(9))
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S  9
-/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU    (BIT(10))
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S  10
-/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON    (BIT(12))
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S  12
-/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD    (BIT(13))
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S  13
-/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU    (BIT(14))
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S  14
-/** CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
- *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S  16
-/** CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
- *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
- */
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S  17
-/** CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
- *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S  18
-
-/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register
- *  Cache data memory power control register
- */
-#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
-/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON : HRO; bitpos: [0]; default: 1;
- *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON    (BIT(0))
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S  0
-/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD : HRO; bitpos: [1]; default: 0;
- *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD    (BIT(1))
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S  1
-/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU : HRO; bitpos: [2]; default: 1;
- *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU    (BIT(2))
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S  2
-/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON : HRO; bitpos: [4]; default: 1;
- *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON    (BIT(4))
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S  4
-/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD : HRO; bitpos: [5]; default: 0;
- *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD    (BIT(5))
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S  5
-/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU : HRO; bitpos: [6]; default: 1;
- *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU    (BIT(6))
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S  6
-/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON    (BIT(8))
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S  8
-/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD    (BIT(9))
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S  9
-/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU    (BIT(10))
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S  10
-/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON    (BIT(12))
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S  12
-/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD    (BIT(13))
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S  13
-/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU    (BIT(14))
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S  14
-/** CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
- *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S  16
-/** CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
- *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S  17
-/** CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
- *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S  18
-
-/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
- *  Cache Freeze control register
- */
-#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c)
-/** CACHE_L1_ICACHE0_FREEZE_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
- *  software.
- */
-#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
-#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
-/** CACHE_L1_ICACHE0_FREEZE_MODE : HRO; bitpos: [1]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
-#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
-/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
-#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
-/** CACHE_L1_ICACHE1_FREEZE_EN : HRO; bitpos: [4]; default: 0;
- *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
- *  software.
- */
-#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
-#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
-/** CACHE_L1_ICACHE1_FREEZE_MODE : HRO; bitpos: [5]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
-#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
-/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
-#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
-/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
-#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
-/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
-#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
-/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
-#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
-/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
-#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
-/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
-#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
-/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
-#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
-/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
- *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
- *  software.
- */
-#define CACHE_L1_CACHE_FREEZE_EN    (BIT(16))
-#define CACHE_L1_CACHE_FREEZE_EN_M  (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S)
-#define CACHE_L1_CACHE_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_EN_S  16
-/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_CACHE_FREEZE_MODE    (BIT(17))
-#define CACHE_L1_CACHE_FREEZE_MODE_M  (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S)
-#define CACHE_L1_CACHE_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_MODE_S  17
-/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_CACHE_FREEZE_DONE    (BIT(18))
-#define CACHE_L1_CACHE_FREEZE_DONE_M  (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S)
-#define CACHE_L1_CACHE_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_FREEZE_DONE_S  18
-
-/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
- *  Cache data memory access configure register
- */
-#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
-/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : HRO; bitpos: [0]; default: 1;
- *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
-/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : HRO; bitpos: [1]; default: 1;
- *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
- *  1: enable.
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
-/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : HRO; bitpos: [4]; default: 1;
- *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
-/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : HRO; bitpos: [5]; default: 1;
- *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
- *  1: enable.
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
-/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
-/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
-/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
-/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
-/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
- *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M  (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S)
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S  16
-/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
- *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M  (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S)
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S  17
-
-/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
- *  Cache tag memory access configure register
- */
-#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34)
-/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : HRO; bitpos: [0]; default: 1;
- *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
-/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : HRO; bitpos: [1]; default: 1;
- *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
-/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : HRO; bitpos: [4]; default: 1;
- *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
-/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : HRO; bitpos: [5]; default: 1;
- *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
-/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
-/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
-/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
-/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
-/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
- *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M  (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S)
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S  16
-/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
- *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M  (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S)
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S  17
-
-/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
- *  L1 instruction Cache 0 prelock configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x38)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE0_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 prelock.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 0 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x3c)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-ICache0, which should be used together with
- *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 0 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x40)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-ICache0, which should be used together with
- *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 0 prelock section size configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x44)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
- *  L1 instruction Cache 1 prelock configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x48)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE1_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 prelock.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 1 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x4c)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-ICache1, which should be used together with
- *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 1 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x50)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-ICache1, which should be used together with
- *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 1 prelock section size configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x54)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
- *  L1 instruction Cache 2 prelock configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x58)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 prelock.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 2 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x5c)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-ICache2, which should be used together with
- *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 2 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x60)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-ICache2, which should be used together with
- *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 2 prelock section size configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x64)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
- *  L1 instruction Cache 3 prelock configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x68)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 prelock.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 3 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x6c)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-ICache3, which should be used together with
- *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 3 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x70)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-ICache3, which should be used together with
- *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 3 prelock section size configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x74)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_CACHE_PRELOCK_CONF_REG register
- *  L1 Cache prelock configure register
- */
-#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-Cache.
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-Cache.
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 cache prelock.
- */
-#define CACHE_L1_CACHE_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_CACHE_PRELOCK_RGID_M  (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S)
-#define CACHE_L1_CACHE_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_CACHE_PRELOCK_RGID_S  2
-
-/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register
- *  L1 Cache prelock section0 address configure register
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-Cache, which should be used together with
- *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
- *  L1 Cache prelock section1 address configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80)
-/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-Cache, which should be used together with
- *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
- *  L1  Cache prelock section size configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84)
-/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_LOCK_CTRL_REG register
- *  Lock-class (manual lock) operation control register
- */
-#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88)
-/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable lock operation. It will be cleared by hardware after lock
- *  operation done
- */
-#define CACHE_LOCK_ENA    (BIT(0))
-#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
-#define CACHE_LOCK_ENA_V  0x00000001U
-#define CACHE_LOCK_ENA_S  0
-/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
- *  The bit is used to enable unlock operation. It will be cleared by hardware after
- *  unlock operation done
- */
-#define CACHE_UNLOCK_ENA    (BIT(1))
-#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
-#define CACHE_UNLOCK_ENA_V  0x00000001U
-#define CACHE_UNLOCK_ENA_S  1
-/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
- *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
- *  not finished. 1: finished.
- */
-#define CACHE_LOCK_DONE    (BIT(2))
-#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
-#define CACHE_LOCK_DONE_V  0x00000001U
-#define CACHE_LOCK_DONE_S  2
-/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of cache lock/unlock.
- */
-#define CACHE_LOCK_RGID    0x0000000FU
-#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
-#define CACHE_LOCK_RGID_V  0x0000000FU
-#define CACHE_LOCK_RGID_S  3
-
-/** CACHE_LOCK_MAP_REG register
- *  Lock (manual lock) map configure register
- */
-#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c)
-/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Those bits are used to indicate which caches in the two-level cache structure will
- *  apply this lock/unlock operation. [4]: L1-Cache
- */
-#define CACHE_LOCK_MAP    0x0000003FU
-#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
-#define CACHE_LOCK_MAP_V  0x0000003FU
-#define CACHE_LOCK_MAP_S  0
-
-/** CACHE_LOCK_ADDR_REG register
- *  Lock (manual lock) address configure register
- */
-#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90)
-/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the lock/unlock
- *  operation, which should be used together with CACHE_LOCK_SIZE_REG
- */
-#define CACHE_LOCK_ADDR    0xFFFFFFFFU
-#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
-#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
-#define CACHE_LOCK_ADDR_S  0
-
-/** CACHE_LOCK_SIZE_REG register
- *  Lock (manual lock) size configure register
- */
-#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94)
-/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
- *  Those bits are used to configure the size of the lock/unlock operation, which
- *  should be used together with CACHE_LOCK_ADDR_REG
- */
-#define CACHE_LOCK_SIZE    0x0000FFFFU
-#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
-#define CACHE_LOCK_SIZE_V  0x0000FFFFU
-#define CACHE_LOCK_SIZE_S  0
-
-/** CACHE_SYNC_CTRL_REG register
- *  Sync-class operation control register
- */
-#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98)
-/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
- *  The bit is used to enable invalidate operation. It will be cleared by hardware
- *  after invalidate operation done. Note that this bit and the other sync-bits
- *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
- *  is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_INVALIDATE_ENA    (BIT(0))
-#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
-#define CACHE_INVALIDATE_ENA_V  0x00000001U
-#define CACHE_INVALIDATE_ENA_S  0
-/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
- *  The bit is used to enable clean operation. It will be cleared by hardware after
- *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
- *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
- *  bits can not be set to 1 at the same time.
- */
-#define CACHE_CLEAN_ENA    (BIT(1))
-#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
-#define CACHE_CLEAN_ENA_V  0x00000001U
-#define CACHE_CLEAN_ENA_S  1
-/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
- *  The bit is used to enable writeback operation. It will be cleared by hardware after
- *  writeback operation done. Note that this bit and the other sync-bits
- *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
- *  is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_WRITEBACK_ENA    (BIT(2))
-#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
-#define CACHE_WRITEBACK_ENA_V  0x00000001U
-#define CACHE_WRITEBACK_ENA_S  2
-/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
- *  The bit is used to enable writeback-invalidate operation. It will be cleared by
- *  hardware after writeback-invalidate operation done. Note that this bit and the
- *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
- *  that is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
-#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
-#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
-#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
-/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
- *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
- *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
- */
-#define CACHE_SYNC_DONE    (BIT(4))
-#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
-#define CACHE_SYNC_DONE_V  0x00000001U
-#define CACHE_SYNC_DONE_S  4
-/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0;
- *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
- *  writeback, writeback_invalidate)
- */
-#define CACHE_SYNC_RGID    0x0000000FU
-#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
-#define CACHE_SYNC_RGID_V  0x0000000FU
-#define CACHE_SYNC_RGID_S  5
-
-/** CACHE_SYNC_MAP_REG register
- *  Sync map configure register
- */
-#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c)
-/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63;
- *  Those bits are used to indicate which caches in the two-level cache structure will
- *  apply the sync operation.  [4]: L1-Cache
- */
-#define CACHE_SYNC_MAP    0x0000003FU
-#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
-#define CACHE_SYNC_MAP_V  0x0000003FU
-#define CACHE_SYNC_MAP_S  0
-
-/** CACHE_SYNC_ADDR_REG register
- *  Sync address configure register
- */
-#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0)
-/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the sync operation,
- *  which should be used together with CACHE_SYNC_SIZE_REG
- */
-#define CACHE_SYNC_ADDR    0xFFFFFFFFU
-#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
-#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
-#define CACHE_SYNC_ADDR_S  0
-
-/** CACHE_SYNC_SIZE_REG register
- *  Sync size configure register
- */
-#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4)
-/** CACHE_SYNC_SIZE : R/W; bitpos: [23:0]; default: 0;
- *  Those bits are used to configure the size of the sync operation, which should be
- *  used together with CACHE_SYNC_ADDR_REG
- */
-#define CACHE_SYNC_SIZE    0x00FFFFFFU
-#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
-#define CACHE_SYNC_SIZE_V  0x00FFFFFFU
-#define CACHE_SYNC_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 0 preload-operation control register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa8)
-/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE0_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE0_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 preload.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 0 preload address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xac)
-/** CACHE_L1_ICACHE0_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 0 preload size configure register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb0)
-/** CACHE_L1_ICACHE0_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 1 preload-operation control register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb4)
-/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE1_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE1_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 preload.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 1 preload address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb8)
-/** CACHE_L1_ICACHE1_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 1 preload size configure register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xbc)
-/** CACHE_L1_ICACHE1_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 2 preload-operation control register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc0)
-/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 preload.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 2 preload address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc4)
-/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 2 preload size configure register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc8)
-/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 3 preload-operation control register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xcc)
-/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 preload.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 3 preload address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd0)
-/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 3 preload size configure register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd4)
-/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register
- *  L1 Cache  preload-operation control register
- */
-#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8)
-/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_CACHE_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_CACHE_PRELOAD_ENA_M  (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S)
-#define CACHE_L1_CACHE_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_ENA_S  0
-/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_CACHE_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_CACHE_PRELOAD_DONE_M  (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S)
-#define CACHE_L1_CACHE_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_DONE_S  1
-/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_CACHE_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_CACHE_PRELOAD_ORDER_M  (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S)
-#define CACHE_L1_CACHE_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_CACHE_PRELOAD_ORDER_S  2
-/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 cache preload.
- */
-#define CACHE_L1_CACHE_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_CACHE_PRELOAD_RGID_M  (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S)
-#define CACHE_L1_CACHE_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_CACHE_PRELOAD_RGID_S  3
-
-/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
- *  L1 Cache  preload address configure register
- */
-#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc)
-/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on L1-Cache,
- *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOAD_ADDR_M  (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S)
-#define CACHE_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
- *  L1 Cache  preload size configure register
- */
-#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0)
-/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_CACHE_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_CACHE_PRELOAD_SIZE_M  (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S)
-#define CACHE_L1_CACHE_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_CACHE_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 0 autoload-operation control register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe4)
-/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 autoload.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 0 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe8)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 0 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xec)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 0 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xf0)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 0 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf4)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 1 autoload-operation control register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf8)
-/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 autoload.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 1 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xfc)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 1 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x100)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 1 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x104)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 1 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x108)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 2 autoload-operation control register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x10c)
-/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 autoload.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 2 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x110)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 2 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x114)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 2 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x118)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 2 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x11c)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 3 autoload-operation control register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x120)
-/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 autoload.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 3 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x124)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 3 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x128)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 3 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x12c)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 3 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x130)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register
- *  L1 Cache autoload-operation control register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134)
-/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_S  0
-/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_M  (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_S  1
-/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M  (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S)
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
- *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
- *  The bit is used to enable the third section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S  10
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
- *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S  11
-/** CACHE_L1_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
- *  The bit is used to set  the gid of l1 cache autoload.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_CACHE_AUTOLOAD_RGID_M  (CACHE_L1_CACHE_AUTOLOAD_RGID_V << CACHE_L1_CACHE_AUTOLOAD_RGID_S)
-#define CACHE_L1_CACHE_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_CACHE_AUTOLOAD_RGID_S  12
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 Cache autoload section 0 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 Cache autoload section 0 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 Cache autoload section 1 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 Cache autoload section 1 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG register
- *  L1 Cache autoload section 2 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x148)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the third section for
- *  autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG register
- *  L1 Cache autoload section 2 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x14c)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [23:0]; default: 0;
- *  Those bits are used to configure the size of the third section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE    0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V  0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG register
- *  L1 Cache autoload section 1 address configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x150)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the fourth section
- *  for autoload operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S  0
-
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG register
- *  L1 Cache autoload section 1 size configure register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x154)
-/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [23:0]; default: 0;
- *  Those bits are used to configure the size of the fourth section for autoload
- *  operation on L1-Cache. Note that it should be used together with
- *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE    0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S)
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V  0x00FFFFFFU
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S  0
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
- *  Cache Access Counter Interrupt enable register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158)
-/** CACHE_L1_IBUS0_OVF_INT_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-ICache0 due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
-/** CACHE_L1_IBUS1_OVF_INT_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-ICache1 due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
-/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
-/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
-/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-DCache due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_ENA    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ENA_M  (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S)
-#define CACHE_L1_BUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_ENA_S  4
-/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-DCache due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_ENA    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ENA_M  (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S)
-#define CACHE_L1_BUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_ENA_S  5
-/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
-#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
-/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
-#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
- *  Cache Access Counter Interrupt clear register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c)
-/** CACHE_L1_IBUS0_OVF_INT_CLR : HRO; bitpos: [0]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
- *  to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
-/** CACHE_L1_IBUS1_OVF_INT_CLR : HRO; bitpos: [1]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
- *  to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
-/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
-/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
-/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
- *  to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_CLR    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_CLR_M  (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S)
-#define CACHE_L1_BUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_CLR_S  4
-/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
- *  to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_CLR    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_CLR_M  (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S)
-#define CACHE_L1_BUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_CLR_S  5
-/** CACHE_L1_DBUS2_OVF_INT_CLR : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
-#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
-/** CACHE_L1_DBUS3_OVF_INT_CLR : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
-#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
- *  Cache Access Counter Interrupt raw register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160)
-/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
- *  due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
-/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
- *  due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
-/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
- *  due to bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
-/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
- *  due to bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
-/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_RAW    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_RAW_M  (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S)
-#define CACHE_L1_BUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_RAW_S  4
-/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_RAW    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_RAW_M  (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S)
-#define CACHE_L1_BUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_RAW_S  5
-/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
-#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
-/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
-#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
- *  Cache Access Counter Interrupt status register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164)
-/** CACHE_L1_IBUS0_OVF_INT_ST : HRO; bitpos: [0]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-ICache0 due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
-#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
-/** CACHE_L1_IBUS1_OVF_INT_ST : HRO; bitpos: [1]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-ICache1 due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
-#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
-/** CACHE_L1_IBUS2_OVF_INT_ST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
-#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
-/** CACHE_L1_IBUS3_OVF_INT_ST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
-#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
-/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-DCache due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_BUS0_OVF_INT_ST    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ST_M  (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S)
-#define CACHE_L1_BUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_BUS0_OVF_INT_ST_S  4
-/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-DCache due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_BUS1_OVF_INT_ST    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ST_M  (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S)
-#define CACHE_L1_BUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_BUS1_OVF_INT_ST_S  5
-/** CACHE_L1_DBUS2_OVF_INT_ST : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
-#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
-/** CACHE_L1_DBUS3_OVF_INT_ST : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
-#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
- *  Cache Access Fail Interrupt enable register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168)
-/** CACHE_L1_ICACHE0_FAIL_INT_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
- *  cpu accesses L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
- *  cpu accesses L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
-/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
- *  cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_ENA    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ENA_M  (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S)
-#define CACHE_L1_CACHE_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_ENA_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
- *  L1-Cache Access Fail Interrupt clear register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16c)
-/** CACHE_L1_ICACHE0_FAIL_INT_CLR : HRO; bitpos: [0]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
- *  cpu accesses L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_CLR : HRO; bitpos: [1]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
- *  cpu accesses L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
-/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
- *  cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_CLR    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_CLR_M  (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S)
-#define CACHE_L1_CACHE_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_CLR_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
- *  Cache Access Fail Interrupt raw register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170)
-/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
-/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_RAW    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_RAW_M  (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S)
-#define CACHE_L1_CACHE_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_RAW_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
- *  Cache Access Fail Interrupt status register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174)
-/** CACHE_L1_ICACHE0_FAIL_INT_ST : HRO; bitpos: [0]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
- *  to cpu accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_ST : HRO; bitpos: [1]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
- *  to cpu accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_ST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_ST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
-/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
- *  to cpu accesses L1-DCache.
- */
-#define CACHE_L1_CACHE_FAIL_INT_ST    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ST_M  (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S)
-#define CACHE_L1_CACHE_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_FAIL_INT_ST_S  4
-
-/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
- *  Cache Access Counter enable and clear register
- */
-#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178)
-/** CACHE_L1_IBUS0_CNT_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable ibus0 counter in L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
-#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
-#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS0_CNT_ENA_S  0
-/** CACHE_L1_IBUS1_CNT_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable ibus1 counter in L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
-#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
-#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS1_CNT_ENA_S  1
-/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
-#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
-#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS2_CNT_ENA_S  2
-/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
-#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
-#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS3_CNT_ENA_S  3
-/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable dbus0 counter in L1-DCache.
- */
-#define CACHE_L1_BUS0_CNT_ENA    (BIT(4))
-#define CACHE_L1_BUS0_CNT_ENA_M  (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S)
-#define CACHE_L1_BUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L1_BUS0_CNT_ENA_S  4
-/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable dbus1 counter in L1-DCache.
- */
-#define CACHE_L1_BUS1_CNT_ENA    (BIT(5))
-#define CACHE_L1_BUS1_CNT_ENA_M  (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S)
-#define CACHE_L1_BUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L1_BUS1_CNT_ENA_S  5
-/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
-#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
-#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS2_CNT_ENA_S  6
-/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
-#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
-#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS3_CNT_ENA_S  7
-/** CACHE_L1_IBUS0_CNT_CLR : HRO; bitpos: [16]; default: 0;
- *  The bit is used to clear ibus0 counter in L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
-#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
-#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS0_CNT_CLR_S  16
-/** CACHE_L1_IBUS1_CNT_CLR : HRO; bitpos: [17]; default: 0;
- *  The bit is used to clear ibus1 counter in L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
-#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
-#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS1_CNT_CLR_S  17
-/** CACHE_L1_IBUS2_CNT_CLR : HRO; bitpos: [18]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
-#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
-#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS2_CNT_CLR_S  18
-/** CACHE_L1_IBUS3_CNT_CLR : HRO; bitpos: [19]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
-#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
-#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS3_CNT_CLR_S  19
-/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
- *  The bit is used to clear dbus0 counter in L1-DCache.
- */
-#define CACHE_L1_BUS0_CNT_CLR    (BIT(20))
-#define CACHE_L1_BUS0_CNT_CLR_M  (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S)
-#define CACHE_L1_BUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L1_BUS0_CNT_CLR_S  20
-/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
- *  The bit is used to clear dbus1 counter in L1-DCache.
- */
-#define CACHE_L1_BUS1_CNT_CLR    (BIT(21))
-#define CACHE_L1_BUS1_CNT_CLR_M  (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S)
-#define CACHE_L1_BUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L1_BUS1_CNT_CLR_S  21
-/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
-#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
-#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS2_CNT_CLR_S  22
-/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
-#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
-#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS3_CNT_CLR_S  23
-
-/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
- *  L1-ICache bus0 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x17c)
-/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
-#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
- *  L1-ICache bus0 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x180)
-/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
-#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus0 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x184)
-/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_NXTLVL_CNT_REG register
- *  L1-ICache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x188)
-/** CACHE_L1_IBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L1_IBUS0_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_NXTLVL_CNT_M  (CACHE_L1_IBUS0_NXTLVL_CNT_V << CACHE_L1_IBUS0_NXTLVL_CNT_S)
-#define CACHE_L1_IBUS0_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_NXTLVL_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
- *  L1-ICache bus1 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
-/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
-#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
- *  L1-ICache bus1 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x190)
-/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
-#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus1 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x194)
-/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_NXTLVL_CNT_REG register
- *  L1-ICache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x198)
-/** CACHE_L1_IBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L1_IBUS1_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_NXTLVL_CNT_M  (CACHE_L1_IBUS1_NXTLVL_CNT_V << CACHE_L1_IBUS1_NXTLVL_CNT_S)
-#define CACHE_L1_IBUS1_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_NXTLVL_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
- *  L1-ICache bus2 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
-/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
-#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
- *  L1-ICache bus2 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
-/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
-#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus2 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
-/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_NXTLVL_CNT_REG register
- *  L1-ICache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
-/** CACHE_L1_IBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L1_IBUS2_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_NXTLVL_CNT_M  (CACHE_L1_IBUS2_NXTLVL_CNT_V << CACHE_L1_IBUS2_NXTLVL_CNT_S)
-#define CACHE_L1_IBUS2_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_NXTLVL_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
- *  L1-ICache bus3 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
-/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
-#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
- *  L1-ICache bus3 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
-/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
-#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus3 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
-/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_NXTLVL_CNT_REG register
- *  L1-ICache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
-/** CACHE_L1_IBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L1_IBUS3_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_NXTLVL_CNT_M  (CACHE_L1_IBUS3_NXTLVL_CNT_V << CACHE_L1_IBUS3_NXTLVL_CNT_S)
-#define CACHE_L1_IBUS3_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_NXTLVL_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
-/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_HIT_CNT_M  (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S)
-#define CACHE_L1_BUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_HIT_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
-/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_MISS_CNT_M  (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S)
-#define CACHE_L1_BUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_MISS_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
-/** CACHE_L1_BUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
- */
-#define CACHE_L1_BUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_CONFLICT_CNT_M  (CACHE_L1_BUS0_CONFLICT_CNT_V << CACHE_L1_BUS0_CONFLICT_CNT_S)
-#define CACHE_L1_BUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
-/** CACHE_L1_BUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-Cache accesses L2-Cache due to
- *  bus0 accessing L1-Cache.
- */
-#define CACHE_L1_BUS0_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_CNT_M  (CACHE_L1_BUS0_NXTLVL_CNT_V << CACHE_L1_BUS0_NXTLVL_CNT_S)
-#define CACHE_L1_BUS0_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS0_NXTLVL_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
-/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_HIT_CNT_M  (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S)
-#define CACHE_L1_BUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_HIT_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
-/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_MISS_CNT_M  (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S)
-#define CACHE_L1_BUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_MISS_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
-/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
- */
-#define CACHE_L1_BUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_CONFLICT_CNT_M  (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S)
-#define CACHE_L1_BUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG register
- *  L1-Cache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
-/** CACHE_L1_BUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-Cache accesses L2-Cache due to
- *  bus1 accessing L1-Cache.
- */
-#define CACHE_L1_BUS1_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L1_BUS1_NXTLVL_CNT_M  (CACHE_L1_BUS1_NXTLVL_CNT_V << CACHE_L1_BUS1_NXTLVL_CNT_S)
-#define CACHE_L1_BUS1_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_BUS1_NXTLVL_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
- *  L1-DCache bus2 Hit-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
-/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
-#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_HIT_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
- *  L1-DCache bus2 Miss-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
-/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
-#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_MISS_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
- *  L1-DCache bus2 Conflict-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
-/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
-#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_NXTLVL_CNT_REG register
- *  L1-DCache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
-/** CACHE_L1_DBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-DCache accesses L2-Cache due to
- *  bus2 accessing L1-DCache.
- */
-#define CACHE_L1_DBUS2_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_CNT_M  (CACHE_L1_DBUS2_NXTLVL_CNT_V << CACHE_L1_DBUS2_NXTLVL_CNT_S)
-#define CACHE_L1_DBUS2_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
- *  L1-DCache bus3 Hit-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
-/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
-#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_HIT_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
- *  L1-DCache bus3 Miss-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
-/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
-#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_MISS_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
- *  L1-DCache bus3 Conflict-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
-/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
-#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_NXTLVL_CNT_REG register
- *  L1-DCache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
-/** CACHE_L1_DBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-DCache accesses L2-Cache due to
- *  bus3 accessing L1-DCache.
- */
-#define CACHE_L1_DBUS3_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_CNT_M  (CACHE_L1_DBUS3_NXTLVL_CNT_V << CACHE_L1_DBUS3_NXTLVL_CNT_S)
-#define CACHE_L1_DBUS3_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_CNT_S  0
-
-/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x1fc)
-/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
-#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ID_S  0
-/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x200)
-/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x204)
-/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
-#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ID_S  0
-/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x208)
-/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x20c)
-/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
-#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ID_S  0
-/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x210)
-/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214)
-/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
-#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ID_S  0
-/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218)
-/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
-
-/** CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG register
- *  L1-Cache Access Fail ID/attribution information register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c)
-/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ID_M  (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S)
-#define CACHE_L1_CACHE_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ID_S  0
-/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ATTR_M  (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S)
-#define CACHE_L1_CACHE_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_CACHE_FAIL_ATTR_S  16
-
-/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
- *  L1-Cache Access Fail Address information register
- */
-#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220)
-/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache accesses L1-Cache.
- */
-#define CACHE_L1_CACHE_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_FAIL_ADDR_M  (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S)
-#define CACHE_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_FAIL_ADDR_S  0
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register
- *  L1-Cache Access Fail Interrupt enable register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x224)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
-/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S  4
-/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The bit is used to enable interrupt of Cache sync-operation done.
- */
-#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
-#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_ENA_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : HRO; bitpos: [7]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
-/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The bit is used to enable interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S  11
-/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The bit is used to enable interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
-#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_ENA_S  13
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register
- *  Sync Preload operation Interrupt clear register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x228)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : HRO; bitpos: [0]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-ICache0
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : HRO; bitpos: [1]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-ICache1
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
-/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
- *  is done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S  4
-/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
- *  done.
- */
-#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
-#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
-#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_CLR_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : HRO; bitpos: [7]; default: 0;
- *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : HRO; bitpos: [8]; default: 0;
- *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
-/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
- *  The bit is used to clear interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S  11
-/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The bit is used to clear interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
-#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
-#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_CLR_S  13
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register
- *  Sync Preload operation Interrupt raw register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x22c)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
- *  done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
- *  done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
-/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
- *  done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S  4
-/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
- */
-#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
-#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
-#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_RAW_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
- *  error occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
- *  error occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
-/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
- *  occurs.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S  11
-/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit of the interrupt that occurs only when Cache sync-operation error
- *  occurs.
- */
-#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
-#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
-#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_RAW_S  13
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register
- *  L1-Cache Access Fail Interrupt status register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x230)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : HRO; bitpos: [0]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : HRO; bitpos: [1]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
-/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-Cache
- *  preload-operation is done.
- */
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M  (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S)
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S  4
-/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when Cache
- *  sync-operation is done.
- */
-#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
-#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_ST_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : HRO; bitpos: [7]; default: 0;
- *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : HRO; bitpos: [8]; default: 0;
- *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
-/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
- *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
- */
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M  (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S)
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S  11
-/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
- *  The bit indicates the status of the interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
-#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_ST_S  13
-
-/** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
- *  Cache Sync/Preload Operation exception register
- */
-#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x234)
-/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
-/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
-/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
-/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
-/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-Cache.
- */
-#define CACHE_L1_CACHE_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_CACHE_PLD_ERR_CODE_M  (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S)
-#define CACHE_L1_CACHE_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_CACHE_PLD_ERR_CODE_S  8
-/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
- *  The values 0-2 are available which means sync map, command conflict and size are
- *  error in Cache System.
- */
-#define CACHE_SYNC_ERR_CODE    0x00000003U
-#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
-#define CACHE_SYNC_ERR_CODE_V  0x00000003U
-#define CACHE_SYNC_ERR_CODE_S  12
-
-/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
- *  Cache Sync Reset control register
- */
-#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x238)
-/** CACHE_L1_ICACHE0_SYNC_RST : HRO; bitpos: [0]; default: 0;
- *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
-#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
-#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE0_SYNC_RST_S  0
-/** CACHE_L1_ICACHE1_SYNC_RST : HRO; bitpos: [1]; default: 0;
- *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
-#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
-#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE1_SYNC_RST_S  1
-/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
-#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
-#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE2_SYNC_RST_S  2
-/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
-#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
-#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE3_SYNC_RST_S  3
-/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
- *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_CACHE_SYNC_RST    (BIT(4))
-#define CACHE_L1_CACHE_SYNC_RST_M  (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S)
-#define CACHE_L1_CACHE_SYNC_RST_V  0x00000001U
-#define CACHE_L1_CACHE_SYNC_RST_S  4
-
-/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
- *  Cache Preload Reset control register
- */
-#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x23c)
-/** CACHE_L1_ICACHE0_PLD_RST : HRO; bitpos: [0]; default: 0;
- *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
-#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_RST_S  0
-/** CACHE_L1_ICACHE1_PLD_RST : HRO; bitpos: [1]; default: 0;
- *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
-#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_RST_S  1
-/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
-#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_RST_S  2
-/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
-#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_RST_S  3
-/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
- *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_CACHE_PLD_RST    (BIT(4))
-#define CACHE_L1_CACHE_PLD_RST_M  (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S)
-#define CACHE_L1_CACHE_PLD_RST_V  0x00000001U
-#define CACHE_L1_CACHE_PLD_RST_S  4
-
-/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
- *  Cache Autoload buffer clear control register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x240)
-/** CACHE_L1_ICACHE0_ALD_BUF_CLR : HRO; bitpos: [0]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
- *  autoload will not work in L1-ICache0. This bit should not be active when autoload
- *  works in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
-/** CACHE_L1_ICACHE1_ALD_BUF_CLR : HRO; bitpos: [1]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
- *  autoload will not work in L1-ICache1. This bit should not be active when autoload
- *  works in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
-/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
-/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
-/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
- *  autoload will not work in L1-Cache. This bit should not be active when autoload
- *  works in L1-Cache.
- */
-#define CACHE_L1_CACHE_ALD_BUF_CLR    (BIT(4))
-#define CACHE_L1_CACHE_ALD_BUF_CLR_M  (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S)
-#define CACHE_L1_CACHE_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_ALD_BUF_CLR_S  4
-
-/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
- *  Unallocate request buffer clear registers
- */
-#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x244)
-/** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
-/** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
-/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
-/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
-/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 cache where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
-#define CACHE_L1_CACHE_UNALLOC_CLR_M  (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S)
-#define CACHE_L1_CACHE_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_CACHE_UNALLOC_CLR_S  4
-
-/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
- *  Cache Tag and Data memory Object control register
- */
-#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x248)
-/** CACHE_L1_ICACHE0_TAG_OBJECT : HRO; bitpos: [0]; default: 0;
- *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
-#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
-/** CACHE_L1_ICACHE1_TAG_OBJECT : HRO; bitpos: [1]; default: 0;
- *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
-#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
-/** CACHE_L1_ICACHE2_TAG_OBJECT : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
-#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
-/** CACHE_L1_ICACHE3_TAG_OBJECT : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
-#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
-/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
- *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_CACHE_TAG_OBJECT    (BIT(4))
-#define CACHE_L1_CACHE_TAG_OBJECT_M  (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S)
-#define CACHE_L1_CACHE_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_CACHE_TAG_OBJECT_S  4
-/** CACHE_L1_ICACHE0_MEM_OBJECT : HRO; bitpos: [6]; default: 0;
- *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
- *  with the others fields inside this register.
- */
-#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
-#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
-/** CACHE_L1_ICACHE1_MEM_OBJECT : HRO; bitpos: [7]; default: 0;
- *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
- *  with the others fields inside this register.
- */
-#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
-#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
-/** CACHE_L1_ICACHE2_MEM_OBJECT : HRO; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
-#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
-/** CACHE_L1_ICACHE3_MEM_OBJECT : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
-#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
-/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
- *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_CACHE_MEM_OBJECT    (BIT(10))
-#define CACHE_L1_CACHE_MEM_OBJECT_M  (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S)
-#define CACHE_L1_CACHE_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_CACHE_MEM_OBJECT_S  10
-
-/** CACHE_L1_CACHE_WAY_OBJECT_REG register
- *  Cache Tag and Data memory way register
- */
-#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x24c)
-/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
- *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
- *  way1, 2: way2, 3: way3, ?, 7: way7.
- */
-#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
-#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
-#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
-#define CACHE_L1_CACHE_WAY_OBJECT_S  0
-
-/** CACHE_L1_CACHE_VADDR_REG register
- *  Cache Vaddr register
- */
-#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x250)
-/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
- *  Those bits stores the virtual address which will decide where inside the specified
- *  tag memory object will be accessed.
- */
-#define CACHE_L1_CACHE_VADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_VADDR_M  (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S)
-#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_VADDR_S  0
-
-/** CACHE_L1_CACHE_DEBUG_BUS_REG register
- *  Cache Tag/data memory content register
- */
-#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x254)
-/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 596;
- *  This is a constant place where we can write data to or read data from the tag/data
- *  memory on the specified cache.
- */
-#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
-#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
-#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_DEBUG_BUS_S  0
-
-/** CACHE_LEVEL_SPLIT0_REG register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x258)
-/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 600;
- *  Reserved
- */
-#define CACHE_LEVEL_SPLIT0    0xFFFFFFFFU
-#define CACHE_LEVEL_SPLIT0_M  (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S)
-#define CACHE_LEVEL_SPLIT0_V  0xFFFFFFFFU
-#define CACHE_LEVEL_SPLIT0_S  0
-
-/** CACHE_L2_CACHE_CTRL_REG register
- *  L2 Cache(L2-Cache) control register
- */
-#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x25c)
-/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0;
- *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
- */
-#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
-#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
-#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
-#define CACHE_L2_CACHE_SHUT_DMA_S  4
-/** CACHE_L2_CACHE_UNDEF_OP : HRO; bitpos: [8:5]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_CACHE_UNDEF_OP    0x0000000FU
-#define CACHE_L2_CACHE_UNDEF_OP_M  (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S)
-#define CACHE_L2_CACHE_UNDEF_OP_V  0x0000000FU
-#define CACHE_L2_CACHE_UNDEF_OP_S  5
-
-/** CACHE_L2_BYPASS_CACHE_CONF_REG register
- *  Bypass Cache configure register
- */
-#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x260)
-/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0;
- *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
-#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
-#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
-#define CACHE_BYPASS_L2_CACHE_EN_S  5
-
-/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
- *  L2 Cache CacheSize mode configure register
- */
-#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x264)
-/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(0))
-#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
-#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_1K_S  0
-/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(1))
-#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
-#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_2K_S  1
-/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(2))
-#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
-#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_4K_S  2
-/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(3))
-#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
-#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_8K_S  3
-/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(4))
-#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
-#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_16K_S  4
-/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(5))
-#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
-#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_32K_S  5
-/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(6))
-#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
-#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_64K_S  6
-/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(7))
-#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
-#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_128K_S  7
-/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(8))
-#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
-#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_256K_S  8
-/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(9))
-#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
-#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_512K_S  9
-/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(10))
-#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
-#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_1024K_S  10
-/** CACHE_L2_CACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_2048K    (BIT(11))
-#define CACHE_L2_CACHE_CACHESIZE_2048K_M  (CACHE_L2_CACHE_CACHESIZE_2048K_V << CACHE_L2_CACHE_CACHESIZE_2048K_S)
-#define CACHE_L2_CACHE_CACHESIZE_2048K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_2048K_S  11
-/** CACHE_L2_CACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_4096K    (BIT(12))
-#define CACHE_L2_CACHE_CACHESIZE_4096K_M  (CACHE_L2_CACHE_CACHESIZE_4096K_V << CACHE_L2_CACHE_CACHESIZE_4096K_S)
-#define CACHE_L2_CACHE_CACHESIZE_4096K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_4096K_S  12
-
-/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
- *  L2 Cache BlockSize mode configure register
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x268)
-/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
-/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
-/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
-/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
-/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
-/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x26c)
-/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0;
- *  Set this bit as 1 to enable L2-Cache wrap around mode.
- */
-#define CACHE_L2_CACHE_WRAP    (BIT(5))
-#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
-#define CACHE_L2_CACHE_WRAP_V  0x00000001U
-#define CACHE_L2_CACHE_WRAP_S  5
-
-/** CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG register
- *  Cache tag memory power control register
- */
-#define CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x270)
-/** CACHE_L2_CACHE_TAG_MEM_FORCE_ON : HRO; bitpos: [20]; default: 0;
- *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON    (BIT(20))
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S)
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S  20
-/** CACHE_L2_CACHE_TAG_MEM_FORCE_PD : HRO; bitpos: [21]; default: 0;
- *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
- */
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD    (BIT(21))
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S)
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S  21
-/** CACHE_L2_CACHE_TAG_MEM_FORCE_PU : HRO; bitpos: [22]; default: 0;
- *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU    (BIT(22))
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S)
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S  22
-
-/** CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG register
- *  Cache data memory power control register
- */
-#define CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x274)
-/** CACHE_L2_CACHE_DATA_MEM_FORCE_ON : HRO; bitpos: [20]; default: 0;
- *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON    (BIT(20))
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S)
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S  20
-/** CACHE_L2_CACHE_DATA_MEM_FORCE_PD : HRO; bitpos: [21]; default: 0;
- *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD    (BIT(21))
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S)
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S  21
-/** CACHE_L2_CACHE_DATA_MEM_FORCE_PU : HRO; bitpos: [22]; default: 0;
- *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU    (BIT(22))
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S)
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S  22
-
-/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
- *  Cache Freeze control register
- */
-#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x278)
-/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0;
- *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
- *  software.
- */
-#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
-#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
-#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_EN_S  20
-/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0;
- *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
-#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
-#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_MODE_S  21
-/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
- *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
-#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
-#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_DONE_S  22
-
-/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
- *  Cache data memory access configure register
- */
-#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x27c)
-/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 0;
- *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
-/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 0;
- *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
-
-/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
- *  Cache tag memory access configure register
- */
-#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x280)
-/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 0;
- *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
-/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 0;
- *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
-
-/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
- *  L2 Cache prelock configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x284)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L2-Cache.
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
-/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L2-Cache.
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
-/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l2 cache prelock.
- */
-#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
-#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
-#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
-
-/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
- *  L2 Cache prelock section0 address configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x288)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L2-Cache, which should be used together with
- *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
- *  L2 Cache prelock section1 address configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x28c)
-/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L2-Cache, which should be used together with
- *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
- *  L2 Cache prelock section size configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x290)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
- *  L2 Cache preload-operation control register
- */
-#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x294)
-/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
-#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
-#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
-/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
-#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
-#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
-/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
-#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
-/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l2 cache preload.
- */
-#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
-#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
-#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
-
-/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
- *  L2 Cache preload address configure register
- */
-#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x298)
-/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on L2-Cache,
- *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
-#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
- *  L2 Cache preload size configure register
- */
-#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x29c)
-/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
-#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
- *  L2 Cache autoload-operation control register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a0)
-/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
- *  0: disable.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
-/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
-/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
-/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
- *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
- *  The bit is used to enable the third section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
- *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
-/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
- *  The bit is used to set  the gid of l2 cache autoload.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
- *  L2 Cache autoload section 0 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2a4)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
- *  L2 Cache autoload section 0 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2a8)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
- *  L2 Cache autoload section 1 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2ac)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
- *  L2 Cache autoload section 1 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2b0)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
- *  L2 Cache autoload section 2 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2b4)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the third section for
- *  autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
- *  L2 Cache autoload section 2 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2b8)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the third section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
- *  L2 Cache autoload section 3 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2bc)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the fourth section
- *  for autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
- *  L2 Cache autoload section 3 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2c0)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the fourth section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
- *  Cache Access Counter Interrupt enable register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2c4)
-/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
-/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
-/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
-/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
-/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
-/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
-/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
-/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
- *  Cache Access Counter Interrupt clear register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2c8)
-/** CACHE_L2_IBUS0_OVF_INT_CLR : HRO; bitpos: [8]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
-/** CACHE_L2_IBUS1_OVF_INT_CLR : HRO; bitpos: [9]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
-/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
-/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
-/** CACHE_L2_DBUS0_OVF_INT_CLR : HRO; bitpos: [12]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
-/** CACHE_L2_DBUS1_OVF_INT_CLR : HRO; bitpos: [13]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
-/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
-/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
- *  Cache Access Counter Interrupt raw register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2cc)
-/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus0 accesses L2-ICache0.
- */
-#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
-/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus1 accesses L2-ICache1.
- */
-#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
-/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus2 accesses L2-ICache2.
- */
-#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
-/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus3 accesses L2-ICache3.
- */
-#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
-/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus0 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
-/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus1 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
-/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus2 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
-/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus3 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
- *  Cache Access Counter Interrupt status register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2d0)
-/** CACHE_L2_IBUS0_OVF_INT_ST : HRO; bitpos: [8]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
-#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
-/** CACHE_L2_IBUS1_OVF_INT_ST : HRO; bitpos: [9]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
-#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
-/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
-#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
-/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
-#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
-/** CACHE_L2_DBUS0_OVF_INT_ST : HRO; bitpos: [12]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
-#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
-/** CACHE_L2_DBUS1_OVF_INT_ST : HRO; bitpos: [13]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
-#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
-/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
-#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
-/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
-#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
- *  Cache Access Fail Interrupt enable register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d4)
-/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
- *  l1 cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
-#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
- *  L1-Cache Access Fail Interrupt clear register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2d8)
-/** CACHE_L2_CACHE_FAIL_INT_CLR : HRO; bitpos: [5]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
- *  cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
-#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
- *  Cache Access Fail Interrupt raw register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2dc)
-/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
-#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
- *  Cache Access Fail Interrupt status register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2e0)
-/** CACHE_L2_CACHE_FAIL_INT_ST : HRO; bitpos: [5]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
- *  to l1 cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
-#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
-
-/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
- *  Cache Access Counter enable and clear register
- */
-#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2e4)
-/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable ibus0 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
-#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
-#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS0_CNT_ENA_S  8
-/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable ibus1 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
-#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
-#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS1_CNT_ENA_S  9
-/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
-#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
-#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS2_CNT_ENA_S  10
-/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
-#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
-#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS3_CNT_ENA_S  11
-/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0;
- *  The bit is used to enable dbus0 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
-#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
-#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS0_CNT_ENA_S  12
-/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0;
- *  The bit is used to enable dbus1 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
-#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
-#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS1_CNT_ENA_S  13
-/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
-#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
-#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS2_CNT_ENA_S  14
-/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
-#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
-#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS3_CNT_ENA_S  15
-/** CACHE_L2_IBUS0_CNT_CLR : HRO; bitpos: [24]; default: 0;
- *  The bit is used to clear ibus0 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
-#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
-#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS0_CNT_CLR_S  24
-/** CACHE_L2_IBUS1_CNT_CLR : HRO; bitpos: [25]; default: 0;
- *  The bit is used to clear ibus1 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
-#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
-#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS1_CNT_CLR_S  25
-/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
-#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
-#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS2_CNT_CLR_S  26
-/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
-#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
-#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS3_CNT_CLR_S  27
-/** CACHE_L2_DBUS0_CNT_CLR : HRO; bitpos: [28]; default: 0;
- *  The bit is used to clear dbus0 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
-#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
-#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS0_CNT_CLR_S  28
-/** CACHE_L2_DBUS1_CNT_CLR : HRO; bitpos: [29]; default: 0;
- *  The bit is used to clear dbus1 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
-#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
-#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS1_CNT_CLR_S  29
-/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
-#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
-#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS2_CNT_CLR_S  30
-/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
-#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
-#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS3_CNT_CLR_S  31
-
-/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2e8)
-/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
-#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2ec)
-/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
-#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x2f0)
-/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache0 accesses
- *  L2-Cache due to bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_NXTLVL_CNT_REG register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x2f4)
-/** CACHE_L2_IBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_NXTLVL_CNT_M  (CACHE_L2_IBUS0_NXTLVL_CNT_V << CACHE_L2_IBUS0_NXTLVL_CNT_S)
-#define CACHE_L2_IBUS0_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_NXTLVL_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2f8)
-/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
-#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2fc)
-/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
-#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
-/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache1 accesses
- *  L2-Cache due to bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_NXTLVL_CNT_REG register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x304)
-/** CACHE_L2_IBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_NXTLVL_CNT_M  (CACHE_L2_IBUS1_NXTLVL_CNT_V << CACHE_L2_IBUS1_NXTLVL_CNT_S)
-#define CACHE_L2_IBUS1_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_NXTLVL_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
-/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
-#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
-/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
-#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
-/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache2 accesses
- *  L2-Cache due to bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_NXTLVL_CNT_REG register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x314)
-/** CACHE_L2_IBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_NXTLVL_CNT_M  (CACHE_L2_IBUS2_NXTLVL_CNT_V << CACHE_L2_IBUS2_NXTLVL_CNT_S)
-#define CACHE_L2_IBUS2_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_NXTLVL_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
-/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
-#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
-/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
-#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
-/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache3 accesses
- *  L2-Cache due to bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_NXTLVL_CNT_REG register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x324)
-/** CACHE_L2_IBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_NXTLVL_CNT_M  (CACHE_L2_IBUS3_NXTLVL_CNT_V << CACHE_L2_IBUS3_NXTLVL_CNT_S)
-#define CACHE_L2_IBUS3_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_NXTLVL_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
-/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
-#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
-/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
-#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
-/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_NXTLVL_CNT_REG register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x334)
-/** CACHE_L2_DBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_CNT_M  (CACHE_L2_DBUS0_NXTLVL_CNT_V << CACHE_L2_DBUS0_NXTLVL_CNT_S)
-#define CACHE_L2_DBUS0_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
-/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
-#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
-/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
-#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
-/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_NXTLVL_CNT_REG register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x344)
-/** CACHE_L2_DBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_CNT_M  (CACHE_L2_DBUS1_NXTLVL_CNT_V << CACHE_L2_DBUS1_NXTLVL_CNT_S)
-#define CACHE_L2_DBUS1_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x348)
-/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
-#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
-/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
-#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x350)
-/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_NXTLVL_CNT_REG register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x354)
-/** CACHE_L2_DBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_CNT_M  (CACHE_L2_DBUS2_NXTLVL_CNT_V << CACHE_L2_DBUS2_NXTLVL_CNT_S)
-#define CACHE_L2_DBUS2_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x358)
-/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
-#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
-/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
-#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x360)
-/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_NXTLVL_CNT_REG register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x364)
-/** CACHE_L2_DBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_NXTLVL_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_CNT_M  (CACHE_L2_DBUS3_NXTLVL_CNT_V << CACHE_L2_DBUS3_NXTLVL_CNT_S)
-#define CACHE_L2_DBUS3_NXTLVL_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_CNT_S  0
-
-/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
- *  L2-Cache Access Fail ID/attribution information register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x368)
-/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
-#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ID_S  0
-/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
- *  due to cache accessing L1-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
-#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ATTR_S  16
-
-/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
- *  L2-Cache Access Fail Address information register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x36c)
-/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
-#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_FAIL_ADDR_S  0
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
- *  L1-Cache Access Fail Interrupt enable register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x370)
-/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of L2-Cache preload-operation done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0;
- *  The bit is used to enable interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
- *  Sync Preload operation Interrupt clear register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x374)
-/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : HRO; bitpos: [5]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
- *  is done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : HRO; bitpos: [12]; default: 0;
- *  The bit is used to clear interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
- *  Sync Preload operation Interrupt raw register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x378)
-/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
- *  done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
- *  occurs.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
- *  L1-Cache Access Fail Interrupt status register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x37c)
-/** CACHE_L2_CACHE_PLD_DONE_INT_ST : HRO; bitpos: [5]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L2-Cache
- *  preload-operation is done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_ST : HRO; bitpos: [12]; default: 0;
- *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
- *  Cache Sync/Preload Operation exception register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x380)
-/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
- *  The value 2 is Only available which means preload size is error in L2-Cache.
- */
-#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
-#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
-#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
-
-/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
- *  Cache Sync Reset control register
- */
-#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x384)
-/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0;
- *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
-#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
-#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
-#define CACHE_L2_CACHE_SYNC_RST_S  5
-
-/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
- *  Cache Preload Reset control register
- */
-#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x388)
-/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0;
- *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
-#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
-#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_RST_S  5
-
-/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
- *  Cache Autoload buffer clear control register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x38c)
-/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0;
- *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
- *  autoload will not work in L2-Cache. This bit should not be active when autoload
- *  works in L2-Cache.
- */
-#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
-#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
-#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
-
-/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
- *  Unallocate request buffer clear registers
- */
-#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x390)
-/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l2 icache where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
-#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
-#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
-
-/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
- *  L1 Cache access Attribute propagation control register
- */
-#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x394)
-/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1;
- *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
- *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
- *  non-cacheable.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
-/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1;
- *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
- *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
- *  write-through.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
-/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1;
- *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
- *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
- *  write-miss-allocate and write-miss-no-allocate.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
-/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1;
- *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
- *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
- *  read-miss-allocate and read-miss-no-allocate.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
-
-/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
- *  Cache Tag and Data memory Object control register
- */
-#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x398)
-/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0;
- *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
-#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
-#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_OBJECT_S  5
-/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0;
- *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
-#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
-#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
-#define CACHE_L2_CACHE_MEM_OBJECT_S  11
-
-/** CACHE_L2_CACHE_WAY_OBJECT_REG register
- *  Cache Tag and Data memory way register
- */
-#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x39c)
-/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0;
- *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
- *  way1, 2: way2, 3: way3, ?, 7: way7.
- */
-#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
-#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
-#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
-#define CACHE_L2_CACHE_WAY_OBJECT_S  0
-
-/** CACHE_L2_CACHE_VADDR_REG register
- *  Cache Vaddr register
- */
-#define CACHE_L2_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x3a0)
-/** CACHE_L2_CACHE_VADDR : HRO; bitpos: [31:0]; default: 1073741824;
- *  Those bits stores the virtual address which will decide where inside the specified
- *  tag memory object will be accessed.
- */
-#define CACHE_L2_CACHE_VADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_VADDR_M  (CACHE_L2_CACHE_VADDR_V << CACHE_L2_CACHE_VADDR_S)
-#define CACHE_L2_CACHE_VADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_VADDR_S  0
-
-/** CACHE_L2_CACHE_DEBUG_BUS_REG register
- *  Cache Tag/data memory content register
- */
-#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3a4)
-/** CACHE_L2_CACHE_DEBUG_BUS : HRO; bitpos: [31:0]; default: 932;
- *  This is a constant place where we can write data to or read data from the tag/data
- *  memory on the specified cache.
- */
-#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
-#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
-#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_DEBUG_BUS_S  0
-
-/** CACHE_LEVEL_SPLIT1_REG register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3a8)
-/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 936;
- *  Reserved
- */
-#define CACHE_LEVEL_SPLIT1    0xFFFFFFFFU
-#define CACHE_LEVEL_SPLIT1_M  (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S)
-#define CACHE_LEVEL_SPLIT1_V  0xFFFFFFFFU
-#define CACHE_LEVEL_SPLIT1_S  0
-
-/** CACHE_CLOCK_GATE_REG register
- *  Clock gate control register
- */
-#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3ac)
-/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable clock gate when access all registers in this module.
- */
-#define CACHE_CLK_EN    (BIT(0))
-#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
-#define CACHE_CLK_EN_V  0x00000001U
-#define CACHE_CLK_EN_S  0
-
-/** CACHE_REDUNDANCY_SIG0_REG register
- *  Cache redundancy signal 0 register
- */
-#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3b0)
-/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG0    0xFFFFFFFFU
-#define CACHE_REDCY_SIG0_M  (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S)
-#define CACHE_REDCY_SIG0_V  0xFFFFFFFFU
-#define CACHE_REDCY_SIG0_S  0
-
-/** CACHE_REDUNDANCY_SIG1_REG register
- *  Cache redundancy signal 1 register
- */
-#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3b4)
-/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG1    0xFFFFFFFFU
-#define CACHE_REDCY_SIG1_M  (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S)
-#define CACHE_REDCY_SIG1_V  0xFFFFFFFFU
-#define CACHE_REDCY_SIG1_S  0
-
-/** CACHE_REDUNDANCY_SIG2_REG register
- *  Cache redundancy signal 2 register
- */
-#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3b8)
-/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG2    0xFFFFFFFFU
-#define CACHE_REDCY_SIG2_M  (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S)
-#define CACHE_REDCY_SIG2_V  0xFFFFFFFFU
-#define CACHE_REDCY_SIG2_S  0
-
-/** CACHE_REDUNDANCY_SIG3_REG register
- *  Cache redundancy signal 3 register
- */
-#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3bc)
-/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG3    0xFFFFFFFFU
-#define CACHE_REDCY_SIG3_M  (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S)
-#define CACHE_REDCY_SIG3_V  0xFFFFFFFFU
-#define CACHE_REDCY_SIG3_S  0
-
-/** CACHE_REDUNDANCY_SIG4_REG register
- *  Cache redundancy signal 0 register
- */
-#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3c0)
-/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0;
- *  Those bits are prepared for ECO.
- */
-#define CACHE_REDCY_SIG4    0x0000000FU
-#define CACHE_REDCY_SIG4_M  (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S)
-#define CACHE_REDCY_SIG4_V  0x0000000FU
-#define CACHE_REDCY_SIG4_S  0
-
-/** CACHE_DATE_REG register
- *  Version control register
- */
-#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
-/** CACHE_DATE : R/W; bitpos: [27:0]; default: 35680848;
- *  version control register. Note that this default value stored is the latest date
- *  when the hardware logic was updated.
- */
-#define CACHE_DATE    0x0FFFFFFFU
-#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
-#define CACHE_DATE_V  0x0FFFFFFFU
-#define CACHE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/cache_struct.h b/components/soc/esp32h2/include/soc/cache_struct.h
deleted file mode 100644
index 7398f887ab6..00000000000
--- a/components/soc/esp32h2/include/soc/cache_struct.h
+++ /dev/null
@@ -1,5747 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Control and configuration registers */
-/** Type of l1_icache_ctrl register
- *  L1 instruction Cache(L1-ICache) control register
- */
-typedef union {
-    struct {
-        /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus0:1;
-        /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus1:1;
-        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus2:1;
-        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus3:1;
-        /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_undef_op:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_icache_ctrl_reg_t;
-
-/** Type of l1_cache_ctrl register
- *  L1 data Cache(L1-Cache) control register
- */
-typedef union {
-    struct {
-        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus0:1;
-        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus1:1;
-        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus2:1;
-        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus3:1;
-        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_dma:1;
-        uint32_t reserved_5:3;
-        /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_undef_op:4;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} cache_l1_cache_ctrl_reg_t;
-
-/** Type of l2_cache_ctrl register
- *  L2 Cache(L2-Cache) control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
-         */
-        uint32_t l2_cache_shut_dma:1;
-        /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_cache_undef_op:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} cache_l2_cache_ctrl_reg_t;
-
-
-/** Group: Bypass Cache Control and configuration registers */
-/** Type of l1_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache0_en:1;
-        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache1_en:1;
-        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache2_en:1;
-        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache3_en:1;
-        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_dcache_en:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_bypass_cache_conf_reg_t;
-
-/** Type of l2_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l2_cache_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_bypass_cache_conf_reg_t;
-
-
-/** Group: Cache Atomic Control and configuration registers */
-/** Type of l1_cache_atomic_conf register
- *  L1 Cache atomic feature configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
-         *  L1-Cache.  1: disable, 1: enable.
-         */
-        uint32_t l1_cache_atomic_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cache_l1_cache_atomic_conf_reg_t;
-
-
-/** Group: Cache Mode Control and configuration registers */
-/** Type of l1_icache_cachesize_conf register
- *  L1 instruction Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1k:1;
-        /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2k:1;
-        /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4k:1;
-        /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_8k:1;
-        /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_16k:1;
-        /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_32k:1;
-        /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_64k:1;
-        /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_128k:1;
-        /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_256k:1;
-        /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_512k:1;
-        /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1024k:1;
-        /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2048k:1;
-        /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l1_icache_cachesize_conf_reg_t;
-
-/** Type of l1_icache_blocksize_conf register
- *  L1 instruction Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_8:1;
-        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_16:1;
-        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_32:1;
-        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_64:1;
-        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_128:1;
-        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache_blocksize_conf_reg_t;
-
-/** Type of l1_cache_cachesize_conf register
- *  L1 data Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1k:1;
-        /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2k:1;
-        /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4k:1;
-        /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_8k:1;
-        /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 1;
-         *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_16k:1;
-        /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_32k:1;
-        /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_64k:1;
-        /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_128k:1;
-        /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_256k:1;
-        /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_512k:1;
-        /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1024k:1;
-        /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2048k:1;
-        /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l1_cache_cachesize_conf_reg_t;
-
-/** Type of l1_cache_blocksize_conf register
- *  L1 data Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_8:1;
-        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_16:1;
-        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
-         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_32:1;
-        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_64:1;
-        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_128:1;
-        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_blocksize_conf_reg_t;
-
-/** Type of l2_cache_cachesize_conf register
- *  L2 Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1k:1;
-        /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2k:1;
-        /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4k:1;
-        /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_8k:1;
-        /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_16k:1;
-        /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_32k:1;
-        /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_64k:1;
-        /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_128k:1;
-        /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_256k:1;
-        /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_512k:1;
-        /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1024k:1;
-        /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2048k:1;
-        /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_cachesize_conf_reg_t;
-
-/** Type of l2_cache_blocksize_conf register
- *  L2 Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_8:1;
-        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_16:1;
-        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_32:1;
-        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_64:1;
-        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_128:1;
-        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_blocksize_conf_reg_t;
-
-
-/** Group: Wrap Mode Control and configuration registers */
-/** Type of l1_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
-         */
-        uint32_t l1_icache0_wrap:1;
-        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
-         */
-        uint32_t l1_icache1_wrap:1;
-        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_wrap:1;
-        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_wrap:1;
-        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
-         *  Set this bit as 1 to enable L1-DCache wrap around mode.
-         */
-        uint32_t l1_cache_wrap:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_wrap_around_ctrl_reg_t;
-
-/** Type of l2_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
-         *  Set this bit as 1 to enable L2-Cache wrap around mode.
-         */
-        uint32_t l2_cache_wrap:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_wrap_around_ctrl_reg_t;
-
-
-/** Group: Cache Tag Memory Power Control registers */
-/** Type of l1_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache0_tag_mem_force_on:1;
-        /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache0_tag_mem_force_pd:1;
-        /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1;
-         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache0_tag_mem_force_pu:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache1_tag_mem_force_on:1;
-        /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache1_tag_mem_force_pd:1;
-        /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1;
-         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache1_tag_mem_force_pu:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_on:1;
-        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_pd:1;
-        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_pu:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_on:1;
-        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_pd:1;
-        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_pu:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_tag_mem_force_on:1;
-        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l1_cache_tag_mem_force_pd:1;
-        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_tag_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} cache_l1_cache_tag_mem_power_ctrl_reg_t;
-
-/** Type of l2_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l2_cache_tag_mem_force_on:1;
-        /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l2_cache_tag_mem_force_pd:1;
-        /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0;
-         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l2_cache_tag_mem_force_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} cache_l2_cache_tag_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Power Control registers */
-/** Type of l1_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache0_data_mem_force_on:1;
-        /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache0_data_mem_force_pd:1;
-        /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1;
-         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache0_data_mem_force_pu:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache1_data_mem_force_on:1;
-        /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache1_data_mem_force_pd:1;
-        /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1;
-         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache1_data_mem_force_pu:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_on:1;
-        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_pd:1;
-        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_pu:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_on:1;
-        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_pd:1;
-        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_pu:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_data_mem_force_on:1;
-        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_cache_data_mem_force_pd:1;
-        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_data_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} cache_l1_cache_data_mem_power_ctrl_reg_t;
-
-/** Type of l2_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l2_cache_data_mem_force_on:1;
-        /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l2_cache_data_mem_force_pd:1;
-        /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0;
-         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l2_cache_data_mem_force_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} cache_l2_cache_data_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Freeze Control registers */
-/** Type of l1_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache0_freeze_en:1;
-        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache0_freeze_mode:1;
-        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_freeze_done:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache1_freeze_en:1;
-        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache1_freeze_mode:1;
-        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_freeze_done:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_en:1;
-        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_mode:1;
-        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_done:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_en:1;
-        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_mode:1;
-        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_done:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
-         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_cache_freeze_en:1;
-        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_cache_freeze_mode:1;
-        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_freeze_done:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} cache_l1_cache_freeze_ctrl_reg_t;
-
-/** Type of l2_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l2_cache_freeze_en:1;
-        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l2_cache_freeze_mode:1;
-        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_freeze_done:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} cache_l2_cache_freeze_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Access Control and Configuration registers */
-/** Type of l1_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_data_mem_rd_en:1;
-        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache0_data_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_data_mem_rd_en:1;
-        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache1_data_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_rd_en:1;
-        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_rd_en:1;
-        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_rd_en:1;
-        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} cache_l1_cache_data_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_rd_en:1;
-        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} cache_l2_cache_data_mem_acs_conf_reg_t;
-
-
-/** Group: Cache Tag Memory Access Control and Configuration registers */
-/** Type of l1_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_rd_en:1;
-        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_rd_en:1;
-        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_rd_en:1;
-        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_rd_en:1;
-        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_rd_en:1;
-        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} cache_l1_cache_tag_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_rd_en:1;
-        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} cache_l2_cache_tag_mem_acs_conf_reg_t;
-
-
-/** Group: Prelock Control and configuration registers */
-/** Type of l1_icache0_prelock_conf register
- *  L1 instruction Cache 0 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct0_en:1;
-        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct1_en:1;
-        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 prelock.
-         */
-        uint32_t l1_icache0_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache0_prelock_conf_reg_t;
-
-/** Type of l1_icache0_prelock_sct0_addr register
- *  L1 instruction Cache 0 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache0, which should be used together with
-         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct1_addr register
- *  L1 instruction Cache 0 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache0, which should be used together with
-         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct_size register
- *  L1 instruction Cache 0 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_icache0_prelock_sct_size_reg_t;
-
-/** Type of l1_icache1_prelock_conf register
- *  L1 instruction Cache 1 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct0_en:1;
-        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct1_en:1;
-        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 prelock.
-         */
-        uint32_t l1_icache1_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache1_prelock_conf_reg_t;
-
-/** Type of l1_icache1_prelock_sct0_addr register
- *  L1 instruction Cache 1 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache1, which should be used together with
-         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct1_addr register
- *  L1 instruction Cache 1 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache1, which should be used together with
-         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct_size register
- *  L1 instruction Cache 1 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_icache1_prelock_sct_size_reg_t;
-
-/** Type of l1_icache2_prelock_conf register
- *  L1 instruction Cache 2 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct0_en:1;
-        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct1_en:1;
-        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 prelock.
-         */
-        uint32_t l1_icache2_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache2_prelock_conf_reg_t;
-
-/** Type of l1_icache2_prelock_sct0_addr register
- *  L1 instruction Cache 2 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache2, which should be used together with
-         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct1_addr register
- *  L1 instruction Cache 2 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache2, which should be used together with
-         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct_size register
- *  L1 instruction Cache 2 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_icache2_prelock_sct_size_reg_t;
-
-/** Type of l1_icache3_prelock_conf register
- *  L1 instruction Cache 3 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct0_en:1;
-        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct1_en:1;
-        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 prelock.
-         */
-        uint32_t l1_icache3_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_icache3_prelock_conf_reg_t;
-
-/** Type of l1_icache3_prelock_sct0_addr register
- *  L1 instruction Cache 3 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache3, which should be used together with
-         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct1_addr register
- *  L1 instruction Cache 3 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache3, which should be used together with
-         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct_size register
- *  L1 instruction Cache 3 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_icache3_prelock_sct_size_reg_t;
-
-/** Type of l1_cache_prelock_conf register
- *  L1 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct0_en:1;
-        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct1_en:1;
-        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 cache prelock.
-         */
-        uint32_t l1_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l1_cache_prelock_conf_reg_t;
-
-/** Type of l1_cache_prelock_sct0_addr register
- *  L1 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct1_addr register
- *  L1 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_prelock_sct1_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct_size register
- *  L1  Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} cache_l1_dcache_prelock_sct_size_reg_t;
-
-/** Type of l2_cache_prelock_conf register
- *  L2 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct0_en:1;
-        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct1_en:1;
-        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l2 cache prelock.
-         */
-        uint32_t l2_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_prelock_conf_reg_t;
-
-/** Type of l2_cache_prelock_sct0_addr register
- *  L2 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L2-Cache, which should be used together with
-         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct1_addr register
- *  L2 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L2-Cache, which should be used together with
-         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_prelock_sct1_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct_size register
- *  L2 Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct0_size:16;
-        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct1_size:16;
-    };
-    uint32_t val;
-} cache_l2_cache_prelock_sct_size_reg_t;
-
-
-/** Group: Lock Control and configuration registers */
-/** Type of lock_ctrl register
- *  Lock-class (manual lock) operation control register
- */
-typedef union {
-    struct {
-        /** lock_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
-         *  operation done
-         */
-        uint32_t lock_ena:1;
-        /** unlock_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable unlock operation. It will be cleared by hardware after
-         *  unlock operation done
-         */
-        uint32_t unlock_ena:1;
-        /** lock_done : RO; bitpos: [2]; default: 1;
-         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
-         *  not finished. 1: finished.
-         */
-        uint32_t lock_done:1;
-        /** lock_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of cache lock/unlock.
-         */
-        uint32_t lock_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_lock_ctrl_reg_t;
-
-/** Type of lock_map register
- *  Lock (manual lock) map configure register
- */
-typedef union {
-    struct {
-        /** lock_map : R/W; bitpos: [5:0]; default: 0;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply this lock/unlock operation. [4]: L1-Cache
-         */
-        uint32_t lock_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_lock_map_reg_t;
-
-/** Type of lock_addr register
- *  Lock (manual lock) address configure register
- */
-typedef union {
-    struct {
-        /** lock_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the lock/unlock
-         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
-         */
-        uint32_t lock_addr:32;
-    };
-    uint32_t val;
-} cache_lock_addr_reg_t;
-
-/** Type of lock_size register
- *  Lock (manual lock) size configure register
- */
-typedef union {
-    struct {
-        /** lock_size : R/W; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the lock/unlock operation, which
-         *  should be used together with CACHE_LOCK_ADDR_REG
-         */
-        uint32_t lock_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_lock_size_reg_t;
-
-
-/** Group: Sync Control and configuration registers */
-/** Type of sync_ctrl register
- *  Sync-class operation control register
- */
-typedef union {
-    struct {
-        /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
-         *  The bit is used to enable invalidate operation. It will be cleared by hardware
-         *  after invalidate operation done. Note that this bit and the other sync-bits
-         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t invalidate_ena:1;
-        /** clean_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable clean operation. It will be cleared by hardware after
-         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
-         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
-         *  bits can not be set to 1 at the same time.
-         */
-        uint32_t clean_ena:1;
-        /** writeback_ena : R/W/SC; bitpos: [2]; default: 0;
-         *  The bit is used to enable writeback operation. It will be cleared by hardware after
-         *  writeback operation done. Note that this bit and the other sync-bits
-         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t writeback_ena:1;
-        /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
-         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
-         *  hardware after writeback-invalidate operation done. Note that this bit and the
-         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
-         *  that is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t writeback_invalidate_ena:1;
-        /** sync_done : RO; bitpos: [4]; default: 0;
-         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
-         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
-         */
-        uint32_t sync_done:1;
-        /** sync_rgid : HRO; bitpos: [8:5]; default: 0;
-         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
-         *  writeback, writeback_invalidate)
-         */
-        uint32_t sync_rgid:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} cache_sync_ctrl_reg_t;
-
-/** Type of sync_map register
- *  Sync map configure register
- */
-typedef union {
-    struct {
-        /** sync_map : R/W; bitpos: [5:0]; default: 63;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply the sync operation.  [4]: L1-Cache
-         */
-        uint32_t sync_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_sync_map_reg_t;
-
-/** Type of sync_addr register
- *  Sync address configure register
- */
-typedef union {
-    struct {
-        /** sync_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the sync operation,
-         *  which should be used together with CACHE_SYNC_SIZE_REG
-         */
-        uint32_t sync_addr:32;
-    };
-    uint32_t val;
-} cache_sync_addr_reg_t;
-
-/** Type of sync_size register
- *  Sync size configure register
- */
-typedef union {
-    struct {
-        /** sync_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the sync operation, which should be
-         *  used together with CACHE_SYNC_ADDR_REG
-         */
-        uint32_t sync_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_sync_size_reg_t;
-
-
-/** Group: Preload Control and configuration registers */
-/** Type of l1_icache0_preload_ctrl register
- *  L1 instruction Cache 0 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache0_preload_ena:1;
-        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache0_preload_done:1;
-        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache0_preload_order:1;
-        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 preload.
-         */
-        uint32_t l1_icache0_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_icache0_preload_ctrl_reg_t;
-
-/** Type of l1_icache0_preload_addr register
- *  L1 instruction Cache 0 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache0_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_preload_addr_reg_t;
-
-/** Type of l1_icache0_preload_size register
- *  L1 instruction Cache 0 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache0_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache0_preload_size_reg_t;
-
-/** Type of l1_icache1_preload_ctrl register
- *  L1 instruction Cache 1 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache1_preload_ena:1;
-        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache1_preload_done:1;
-        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache1_preload_order:1;
-        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 preload.
-         */
-        uint32_t l1_icache1_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_icache1_preload_ctrl_reg_t;
-
-/** Type of l1_icache1_preload_addr register
- *  L1 instruction Cache 1 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache1_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_preload_addr_reg_t;
-
-/** Type of l1_icache1_preload_size register
- *  L1 instruction Cache 1 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache1_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache1_preload_size_reg_t;
-
-/** Type of l1_icache2_preload_ctrl register
- *  L1 instruction Cache 2 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache2_preload_ena:1;
-        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache2_preload_done:1;
-        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache2_preload_order:1;
-        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 preload.
-         */
-        uint32_t l1_icache2_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_icache2_preload_ctrl_reg_t;
-
-/** Type of l1_icache2_preload_addr register
- *  L1 instruction Cache 2 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache2_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_preload_addr_reg_t;
-
-/** Type of l1_icache2_preload_size register
- *  L1 instruction Cache 2 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache2_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache2_preload_size_reg_t;
-
-/** Type of l1_icache3_preload_ctrl register
- *  L1 instruction Cache 3 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache3_preload_ena:1;
-        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache3_preload_done:1;
-        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache3_preload_order:1;
-        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 preload.
-         */
-        uint32_t l1_icache3_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_icache3_preload_ctrl_reg_t;
-
-/** Type of l1_icache3_preload_addr register
- *  L1 instruction Cache 3 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache3_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_preload_addr_reg_t;
-
-/** Type of l1_icache3_preload_size register
- *  L1 instruction Cache 3 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache3_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache3_preload_size_reg_t;
-
-/** Type of l1_cache_preload_ctrl register
- *  L1 Cache  preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_cache_preload_ena:1;
-        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_cache_preload_done:1;
-        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_cache_preload_order:1;
-        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 cache preload.
-         */
-        uint32_t l1_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l1_cache_preload_ctrl_reg_t;
-
-/** Type of l1_dcache_preload_addr register
- *  L1 Cache  preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
-         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_cache_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_preload_addr_reg_t;
-
-/** Type of l1_dcache_preload_size register
- *  L1 Cache  preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_cache_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_dcache_preload_size_reg_t;
-
-/** Type of l2_cache_preload_ctrl register
- *  L2 Cache preload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l2_cache_preload_ena:1;
-        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l2_cache_preload_done:1;
-        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l2_cache_preload_order:1;
-        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l2 cache preload.
-         */
-        uint32_t l2_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} cache_l2_cache_preload_ctrl_reg_t;
-
-/** Type of l2_cache_preload_addr register
- *  L2 Cache preload address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
-         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l2_cache_preload_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_preload_addr_reg_t;
-
-/** Type of l2_cache_preload_size register
- *  L2 Cache preload size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l2_cache_preload_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_preload_size_reg_t;
-
-
-/** Group: Autoload Control and configuration registers */
-/** Type of l1_icache0_autoload_ctrl register
- *  L1 instruction Cache 0 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache0_autoload_ena:1;
-        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_autoload_done:1;
-        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache0_autoload_order:1;
-        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache0_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct0_ena:1;
-        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct1_ena:1;
-        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 autoload.
-         */
-        uint32_t l1_icache0_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_ctrl_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_addr register
- *  L1 instruction Cache 0 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_size register
- *  L1 instruction Cache 0 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_addr register
- *  L1 instruction Cache 0 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_size register
- *  L1 instruction Cache 0 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache0_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache1_autoload_ctrl register
- *  L1 instruction Cache 1 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache1_autoload_ena:1;
-        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_autoload_done:1;
-        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache1_autoload_order:1;
-        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache1_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct0_ena:1;
-        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct1_ena:1;
-        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 autoload.
-         */
-        uint32_t l1_icache1_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_ctrl_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_addr register
- *  L1 instruction Cache 1 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_size register
- *  L1 instruction Cache 1 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_addr register
- *  L1 instruction Cache 1 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_size register
- *  L1 instruction Cache 1 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache1_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache2_autoload_ctrl register
- *  L1 instruction Cache 2 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache2_autoload_ena:1;
-        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache2_autoload_done:1;
-        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache2_autoload_order:1;
-        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache2_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct0_ena:1;
-        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct1_ena:1;
-        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 autoload.
-         */
-        uint32_t l1_icache2_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_ctrl_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_addr register
- *  L1 instruction Cache 2 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_size register
- *  L1 instruction Cache 2 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_addr register
- *  L1 instruction Cache 2 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_size register
- *  L1 instruction Cache 2 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache2_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache3_autoload_ctrl register
- *  L1 instruction Cache 3 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache3_autoload_ena:1;
-        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache3_autoload_done:1;
-        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache3_autoload_order:1;
-        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache3_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct0_ena:1;
-        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct1_ena:1;
-        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 autoload.
-         */
-        uint32_t l1_icache3_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_ctrl_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_addr register
- *  L1 instruction Cache 3 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_size register
- *  L1 instruction Cache 3 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_addr register
- *  L1 instruction Cache 3 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_size register
- *  L1 instruction Cache 3 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l1_icache3_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_ctrl register
- *  L1 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_cache_autoload_ena:1;
-        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_autoload_done:1;
-        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_cache_autoload_order:1;
-        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct0_ena:1;
-        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct1_ena:1;
-        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct2_ena:1;
-        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct3_ena:1;
-        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l1 cache autoload.
-         */
-        uint32_t l1_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_ctrl_reg_t;
-
-/** Type of l1_cache_autoload_sct0_addr register
- *  L1 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct0_size register
- *  L1 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct0_size_reg_t;
-
-/** Type of l1_cache_autoload_sct1_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct1_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_sct2_addr register
- *  L1 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the third section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct2_size register
- *  L1 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_size : HRO; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct2_size_reg_t;
-
-/** Type of l1_cache_autoload_sct3_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the fourth section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct3_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_size : HRO; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_sct3_size_reg_t;
-
-/** Type of l2_cache_autoload_ctrl register
- *  L2 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l2_cache_autoload_ena:1;
-        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_autoload_done:1;
-        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l2_cache_autoload_order:1;
-        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l2_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct0_ena:1;
-        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct1_ena:1;
-        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct2_ena:1;
-        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct3_ena:1;
-        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l2 cache autoload.
-         */
-        uint32_t l2_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_sct0_addr register
- *  L2 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct0_size register
- *  L2 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct0_size_reg_t;
-
-/** Type of l2_cache_autoload_sct1_addr register
- *  L2 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct1_size register
- *  L2 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct1_size_reg_t;
-
-/** Type of l2_cache_autoload_sct2_addr register
- *  L2 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the third section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct2_size register
- *  L2 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct2_size_reg_t;
-
-/** Type of l2_cache_autoload_sct3_addr register
- *  L2 Cache autoload section 3 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the fourth section
-         *  for autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct3_size register
- *  L2 Cache autoload section 3 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_sct3_size_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of l1_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_ena:1;
-        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_ena:1;
-        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_ena:1;
-        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_ena:1;
-        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_ena:1;
-        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_ena:1;
-        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_ena:1;
-        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_ena:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
-         *  to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_clr:1;
-        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
-         *  to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_clr:1;
-        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_clr:1;
-        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_clr:1;
-        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_clr:1;
-        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_clr:1;
-        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_clr:1;
-        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_clr:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
-         *  due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_raw:1;
-        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
-         *  due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_raw:1;
-        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
-         *  due to bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_ovf_int_raw:1;
-        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
-         *  due to bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_ovf_int_raw:1;
-        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_raw:1;
-        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_raw:1;
-        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_ovf_int_raw:1;
-        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_ovf_int_raw:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_st:1;
-        /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_st:1;
-        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_st:1;
-        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_st:1;
-        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_st:1;
-        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_st:1;
-        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_st:1;
-        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_st:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l1_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_ena:1;
-        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_ena:1;
-        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_ena:1;
-        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_ena:1;
-        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_ena:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l1_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_clr:1;
-        /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_clr:1;
-        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_clr:1;
-        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_clr:1;
-        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l1_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_raw:1;
-        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_raw:1;
-        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
-         */
-        uint32_t l1_icache2_fail_int_raw:1;
-        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
-         */
-        uint32_t l1_icache3_fail_int_raw:1;
-        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_raw:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l1_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_int_st:1;
-        /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_int_st:1;
-        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_st:1;
-        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_st:1;
-        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
-         *  to cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_st:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_int_st_reg_t;
-
-/** Type of l1_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache0_pld_done_int_ena:1;
-        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache1_pld_done_int_ena:1;
-        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_ena:1;
-        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_ena:1;
-        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_cache_pld_done_int_ena:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation done.
-         */
-        uint32_t sync_done_int_ena:1;
-        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_ena:1;
-        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_ena:1;
-        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_ena:1;
-        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_ena:1;
-        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_ena:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_ena:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l1_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_clr:1;
-        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_clr:1;
-        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_clr:1;
-        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_clr:1;
-        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l1_cache_pld_done_int_clr:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_clr : WT; bitpos: [6]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
-         *  done.
-         */
-        uint32_t sync_done_int_clr:1;
-        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_clr:1;
-        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_clr:1;
-        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_clr:1;
-        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_clr:1;
-        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
-         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_clr:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_clr : WT; bitpos: [13]; default: 0;
-         *  The bit is used to clear interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_clr:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l1_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache0_pld_done_int_raw:1;
-        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache1_pld_done_int_raw:1;
-        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_raw:1;
-        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_raw:1;
-        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l1_cache_pld_done_int_raw:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
-         */
-        uint32_t sync_done_int_raw:1;
-        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache0_pld_err_int_raw:1;
-        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache1_pld_err_int_raw:1;
-        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_raw:1;
-        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_raw:1;
-        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_err_int_raw:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
-         *  occurs.
-         */
-        uint32_t sync_err_int_raw:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l1_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_st:1;
-        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_st:1;
-        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_st:1;
-        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_st:1;
-        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l1_cache_pld_done_int_st:1;
-        uint32_t reserved_5:1;
-        /** sync_done_int_st : RO; bitpos: [6]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when Cache
-         *  sync-operation is done.
-         */
-        uint32_t sync_done_int_st:1;
-        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_st:1;
-        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_st:1;
-        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_st:1;
-        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_st:1;
-        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_st:1;
-        uint32_t reserved_12:1;
-        /** sync_err_int_st : RO; bitpos: [13]; default: 0;
-         *  The bit indicates the status of the interrupt of Cache sync-operation error.
-         */
-        uint32_t sync_err_int_st:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_int_st_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_ena:1;
-        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_ena:1;
-        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_ena:1;
-        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_ena:1;
-        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_ena:1;
-        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_ena:1;
-        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_ena:1;
-        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_clr:1;
-        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_clr:1;
-        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_clr:1;
-        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_clr:1;
-        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_clr:1;
-        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_clr:1;
-        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_clr:1;
-        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-ICache0.
-         */
-        uint32_t l2_ibus0_ovf_int_raw:1;
-        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-ICache1.
-         */
-        uint32_t l2_ibus1_ovf_int_raw:1;
-        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-ICache2.
-         */
-        uint32_t l2_ibus2_ovf_int_raw:1;
-        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-ICache3.
-         */
-        uint32_t l2_ibus3_ovf_int_raw:1;
-        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-DCache.
-         */
-        uint32_t l2_dbus0_ovf_int_raw:1;
-        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-DCache.
-         */
-        uint32_t l2_dbus1_ovf_int_raw:1;
-        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-DCache.
-         */
-        uint32_t l2_dbus2_ovf_int_raw:1;
-        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-DCache.
-         */
-        uint32_t l2_dbus3_ovf_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_st:1;
-        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_st:1;
-        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_st:1;
-        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_st:1;
-        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_st:1;
-        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_st:1;
-        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_st:1;
-        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l2_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
-         *  l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l2_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
-         *  cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l2_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l2_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
-         *  to l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_int_st_reg_t;
-
-/** Type of l2_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
-         */
-        uint32_t l2_cache_pld_done_int_ena:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_ena:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l2_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l2_cache_pld_done_int_clr:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_clr:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l2_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l2_cache_pld_done_int_raw:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_err_int_raw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l2_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l2_cache_pld_done_int_st:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_st:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_int_st_reg_t;
-
-
-/** Group: Access Statistics registers */
-/** Type of l1_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_ena:1;
-        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_ena:1;
-        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_ena:1;
-        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_ena:1;
-        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_ena:1;
-        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_ena:1;
-        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_ena:1;
-        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_ena:1;
-        uint32_t reserved_8:8;
-        /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0;
-         *  The bit is used to clear ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_clr:1;
-        /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0;
-         *  The bit is used to clear ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_clr:1;
-        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_clr:1;
-        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_clr:1;
-        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
-         *  The bit is used to clear dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_clr:1;
-        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
-         *  The bit is used to clear dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_clr:1;
-        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_clr:1;
-        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_clr:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l1_ibus0_acs_hit_cnt register
- *  L1-ICache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_miss_cnt register
- *  L1-ICache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_conflict_cnt register
- *  L1-ICache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_nxtlvl_cnt register
- *  L1-ICache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l1_ibus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_hit_cnt register
- *  L1-ICache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_miss_cnt register
- *  L1-ICache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_conflict_cnt register
- *  L1-ICache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_nxtlvl_cnt register
- *  L1-ICache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l1_ibus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_hit_cnt register
- *  L1-ICache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_miss_cnt register
- *  L1-ICache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_conflict_cnt register
- *  L1-ICache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_nxtlvl_cnt register
- *  L1-ICache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l1_ibus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_hit_cnt register
- *  L1-ICache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_miss_cnt register
- *  L1-ICache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_conflict_cnt register
- *  L1-ICache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_nxtlvl_cnt register
- *  L1-ICache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l1_ibus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_ibus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_bus0_acs_hit_cnt register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus0_acs_miss_cnt register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus0_acs_conflict_cnt register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_bus0_acs_nxtlvl_cnt register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus0 accessing L1-Cache.
-         */
-        uint32_t l1_bus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_bus1_acs_hit_cnt register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus1_acs_miss_cnt register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus1_acs_conflict_cnt register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_bus1_acs_nxtlvl_cnt register
- *  L1-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus1 accessing L1-Cache.
-         */
-        uint32_t l1_bus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_bus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_hit_cnt register
- *  L1-DCache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_miss_cnt register
- *  L1-DCache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_conflict_cnt register
- *  L1-DCache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_nxtlvl_cnt register
- *  L1-DCache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l1_dbus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_hit_cnt register
- *  L1-DCache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_miss_cnt register
- *  L1-DCache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_conflict_cnt register
- *  L1-DCache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_nxtlvl_cnt register
- *  L1-DCache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l1_dbus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l1_dbus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_ena:1;
-        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_ena:1;
-        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_ena:1;
-        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_ena:1;
-        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_ena:1;
-        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_ena:1;
-        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_ena:1;
-        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_ena:1;
-        uint32_t reserved_16:8;
-        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
-         *  The bit is used to clear ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_clr:1;
-        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
-         *  The bit is used to clear ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_clr:1;
-        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_clr:1;
-        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_clr:1;
-        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
-         *  The bit is used to clear dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_clr:1;
-        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
-         *  The bit is used to clear dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_clr:1;
-        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_clr:1;
-        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_clr:1;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l2_ibus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache0 accesses
-         *  L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_nxtlvl_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache1 accesses
-         *  L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_nxtlvl_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache2 accesses
-         *  L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_nxtlvl_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache3 accesses
-         *  L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_nxtlvl_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_ibus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_nxtlvl_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_nxtlvl_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_nxtlvl_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_nxtlvl_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} cache_l2_dbus3_acs_nxtlvl_cnt_reg_t;
-
-
-/** Group: Access Fail Debug registers */
-/** Type of l1_icache0_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_id:16;
-        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache0_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache0_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache0_acs_fail_addr_reg_t;
-
-/** Type of l1_icache1_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_id:16;
-        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache1_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache1_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache1_acs_fail_addr_reg_t;
-
-/** Type of l1_icache2_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_id:16;
-        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache2_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache2_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache2_acs_fail_addr_reg_t;
-
-/** Type of l1_icache3_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_id:16;
-        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_icache3_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache3_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_icache3_acs_fail_addr_reg_t;
-
-/** Type of l1_cache_acs_fail_id_attr register
- *  L1-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_id:16;
-        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l1_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l1_dcache_acs_fail_addr register
- *  L1-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l1_dcache_acs_fail_addr_reg_t;
-
-/** Type of l2_cache_acs_fail_id_attr register
- *  L2-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_id:16;
-        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
-         *  due to cache accessing L1-Cache.
-         */
-        uint32_t l2_cache_fail_attr:16;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l2_cache_acs_fail_addr register
- *  L2-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_addr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_acs_fail_addr_reg_t;
-
-
-/** Group: Operation Exception registers */
-/** Type of l1_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache0.
-         */
-        uint32_t l1_icache0_pld_err_code:2;
-        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache1.
-         */
-        uint32_t l1_icache1_pld_err_code:2;
-        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_code:2;
-        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_code:2;
-        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-Cache.
-         */
-        uint32_t l1_cache_pld_err_code:2;
-        uint32_t reserved_10:2;
-        /** sync_err_code : RO; bitpos: [13:12]; default: 0;
-         *  The values 0-2 are available which means sync map, command conflict and size are
-         *  error in Cache System.
-         */
-        uint32_t sync_err_code:2;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_preload_exception_reg_t;
-
-/** Type of l2_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:10;
-        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L2-Cache.
-         */
-        uint32_t l2_cache_pld_err_code:2;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_preload_exception_reg_t;
-
-
-/** Group: Sync Reset control and configuration registers */
-/** Type of l1_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache0_sync_rst:1;
-        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache1_sync_rst:1;
-        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_sync_rst:1;
-        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_sync_rst:1;
-        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_cache_sync_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_sync_rst_ctrl_reg_t;
-
-/** Type of l2_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l2_cache_sync_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_sync_rst_ctrl_reg_t;
-
-
-/** Group: Preload Reset control and configuration registers */
-/** Type of l1_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache0_pld_rst:1;
-        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache1_pld_rst:1;
-        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_rst:1;
-        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_rst:1;
-        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_preload_rst_ctrl_reg_t;
-
-/** Type of l2_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_preload_rst_ctrl_reg_t;
-
-
-/** Group: Autoload buffer clear control and configuration registers */
-/** Type of l1_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
-         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
-         *  works in L1-ICache0.
-         */
-        uint32_t l1_icache0_ald_buf_clr:1;
-        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
-         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
-         *  works in L1-ICache1.
-         */
-        uint32_t l1_icache1_ald_buf_clr:1;
-        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_ald_buf_clr:1;
-        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_ald_buf_clr:1;
-        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
-         *  autoload will not work in L1-Cache. This bit should not be active when autoload
-         *  works in L1-Cache.
-         */
-        uint32_t l1_cache_ald_buf_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_cache_autoload_buf_clr_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
-         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
-         *  autoload will not work in L2-Cache. This bit should not be active when autoload
-         *  works in L2-Cache.
-         */
-        uint32_t l2_cache_ald_buf_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_cache_autoload_buf_clr_ctrl_reg_t;
-
-
-/** Group: Unallocate request buffer clear registers */
-/** Type of l1_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache0_unalloc_clr:1;
-        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache1_unalloc_clr:1;
-        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_unalloc_clr:1;
-        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_unalloc_clr:1;
-        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_cache_unalloc_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} cache_l1_unallocate_buffer_clear_reg_t;
-
-/** Type of l2_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l2_cache_unalloc_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} cache_l2_unallocate_buffer_clear_reg_t;
-
-
-/** Group: Tag and Data Memory Access Control and configuration register */
-/** Type of l1_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0;
-         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache0_tag_object:1;
-        /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0;
-         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache1_tag_object:1;
-        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_object:1;
-        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_object:1;
-        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_tag_object:1;
-        uint32_t reserved_5:1;
-        /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0;
-         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache0_mem_object:1;
-        /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0;
-         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache1_mem_object:1;
-        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_mem_object:1;
-        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_mem_object:1;
-        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_mem_object:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} cache_l1_cache_object_ctrl_reg_t;
-
-/** Type of l1_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l1_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} cache_l1_cache_way_object_reg_t;
-
-/** Type of l1_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l1_cache_vaddr:32;
-    };
-    uint32_t val;
-} cache_l1_cache_vaddr_reg_t;
-
-/** Type of l1_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l1_cache_debug_bus:32;
-    };
-    uint32_t val;
-} cache_l1_cache_debug_bus_reg_t;
-
-/** Type of l2_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
-         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_tag_object:1;
-        uint32_t reserved_6:5;
-        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
-         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_mem_object:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} cache_l2_cache_object_ctrl_reg_t;
-
-/** Type of l2_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l2_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} cache_l2_cache_way_object_reg_t;
-
-/** Type of l2_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l2_cache_vaddr:32;
-    };
-    uint32_t val;
-} cache_l2_cache_vaddr_reg_t;
-
-/** Type of l2_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l2_cache_debug_bus:32;
-    };
-    uint32_t val;
-} cache_l2_cache_debug_bus_reg_t;
-
-
-/** Group: Split L1 and L2 registers */
-/** Type of level_split0 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split0 : HRO; bitpos: [31:0]; default: 600;
-         *  Reserved
-         */
-        uint32_t level_split0:32;
-    };
-    uint32_t val;
-} cache_level_split0_reg_t;
-
-/** Type of level_split1 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split1 : HRO; bitpos: [31:0]; default: 936;
-         *  Reserved
-         */
-        uint32_t level_split1:32;
-    };
-    uint32_t val;
-} cache_level_split1_reg_t;
-
-
-/** Group: L2 cache access attribute control register */
-/** Type of l2_cache_access_attr_ctrl register
- *  L1 Cache access Attribute propagation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
-         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
-         *  non-cacheable.
-         */
-        uint32_t l2_cache_access_force_cc:1;
-        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
-         *  write-through.
-         */
-        uint32_t l2_cache_access_force_wb:1;
-        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  write-miss-allocate and write-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_wma:1;
-        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
-         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  read-miss-allocate and read-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_rma:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} cache_l2_cache_access_attr_ctrl_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  The bit is used to enable clock gate when access all registers in this module.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} cache_clock_gate_reg_t;
-
-
-/** Group: Redundancy  register (Prepare for ECO) */
-/** Type of redundancy_sig0 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig0:32;
-    };
-    uint32_t val;
-} cache_redundancy_sig0_reg_t;
-
-/** Type of redundancy_sig1 register
- *  Cache redundancy signal 1 register
- */
-typedef union {
-    struct {
-        /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig1:32;
-    };
-    uint32_t val;
-} cache_redundancy_sig1_reg_t;
-
-/** Type of redundancy_sig2 register
- *  Cache redundancy signal 2 register
- */
-typedef union {
-    struct {
-        /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig2:32;
-    };
-    uint32_t val;
-} cache_redundancy_sig2_reg_t;
-
-/** Type of redundancy_sig3 register
- *  Cache redundancy signal 3 register
- */
-typedef union {
-    struct {
-        /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig3:32;
-    };
-    uint32_t val;
-} cache_redundancy_sig3_reg_t;
-
-/** Type of redundancy_sig4 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** redcy_sig4 : RO; bitpos: [3:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t redcy_sig4:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} cache_redundancy_sig4_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35680848;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} cache_date_reg_t;
-
-
-typedef struct {
-    volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl;
-    volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl;
-    volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
-    volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
-    volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
-    volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
-    volatile cache_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
-    volatile cache_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
-    volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
-    volatile cache_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
-    volatile cache_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
-    volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
-    volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
-    volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
-    volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
-    volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
-    volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
-    volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
-    volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
-    volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
-    volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
-    volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
-    volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
-    volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
-    volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
-    volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
-    volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
-    volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
-    volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
-    volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
-    volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
-    volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
-    volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
-    volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
-    volatile cache_lock_ctrl_reg_t lock_ctrl;
-    volatile cache_lock_map_reg_t lock_map;
-    volatile cache_lock_addr_reg_t lock_addr;
-    volatile cache_lock_size_reg_t lock_size;
-    volatile cache_sync_ctrl_reg_t sync_ctrl;
-    volatile cache_sync_map_reg_t sync_map;
-    volatile cache_sync_addr_reg_t sync_addr;
-    volatile cache_sync_size_reg_t sync_size;
-    volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
-    volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
-    volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
-    volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
-    volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
-    volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
-    volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
-    volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
-    volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
-    volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
-    volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
-    volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
-    volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
-    volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
-    volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
-    volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
-    volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
-    volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
-    volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
-    volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
-    volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
-    volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
-    volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
-    volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
-    volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
-    volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
-    volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
-    volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
-    volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
-    volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
-    volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
-    volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
-    volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
-    volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
-    volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
-    volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
-    volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
-    volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
-    volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
-    volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
-    volatile cache_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
-    volatile cache_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
-    volatile cache_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
-    volatile cache_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
-    volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
-    volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
-    volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
-    volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
-    volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
-    volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
-    volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
-    volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
-    volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
-    volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
-    volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
-    volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
-    volatile cache_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt;
-    volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
-    volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
-    volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
-    volatile cache_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt;
-    volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
-    volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
-    volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
-    volatile cache_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt;
-    volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
-    volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
-    volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
-    volatile cache_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt;
-    volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
-    volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
-    volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
-    volatile cache_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt;
-    volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
-    volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
-    volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
-    volatile cache_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt;
-    volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
-    volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
-    volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
-    volatile cache_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt;
-    volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
-    volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
-    volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
-    volatile cache_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt;
-    volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
-    volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
-    volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
-    volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
-    volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
-    volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
-    volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
-    volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
-    volatile cache_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr;
-    volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
-    volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
-    volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
-    volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
-    volatile cache_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
-    volatile cache_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
-    volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
-    volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
-    volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
-    volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
-    volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
-    volatile cache_l1_cache_way_object_reg_t l1_cache_way_object;
-    volatile cache_l1_cache_vaddr_reg_t l1_cache_vaddr;
-    volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
-    volatile cache_level_split0_reg_t level_split0;
-    volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl;
-    volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
-    volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
-    volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
-    volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
-    volatile cache_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
-    volatile cache_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
-    volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
-    volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
-    volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
-    volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
-    volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
-    volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
-    volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
-    volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
-    volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
-    volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size;
-    volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
-    volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
-    volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
-    volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
-    volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
-    volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
-    volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
-    volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
-    volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
-    volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
-    volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
-    volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
-    volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
-    volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
-    volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
-    volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
-    volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
-    volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
-    volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
-    volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
-    volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
-    volatile cache_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt;
-    volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
-    volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
-    volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
-    volatile cache_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt;
-    volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
-    volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
-    volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
-    volatile cache_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt;
-    volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
-    volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
-    volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
-    volatile cache_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt;
-    volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
-    volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
-    volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
-    volatile cache_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt;
-    volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
-    volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
-    volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
-    volatile cache_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt;
-    volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
-    volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
-    volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
-    volatile cache_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt;
-    volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
-    volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
-    volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
-    volatile cache_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt;
-    volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
-    volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
-    volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
-    volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
-    volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
-    volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
-    volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
-    volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
-    volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
-    volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
-    volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
-    volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
-    volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
-    volatile cache_l2_cache_way_object_reg_t l2_cache_way_object;
-    volatile cache_l2_cache_vaddr_reg_t l2_cache_vaddr;
-    volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
-    volatile cache_level_split1_reg_t level_split1;
-    volatile cache_clock_gate_reg_t clock_gate;
-    volatile cache_redundancy_sig0_reg_t redundancy_sig0;
-    volatile cache_redundancy_sig1_reg_t redundancy_sig1;
-    volatile cache_redundancy_sig2_reg_t redundancy_sig2;
-    volatile cache_redundancy_sig3_reg_t redundancy_sig3;
-    volatile cache_redundancy_sig4_reg_t redundancy_sig4;
-    uint32_t reserved_3c4[14];
-    volatile cache_date_reg_t date;
-} cache_dev_t;
-
-extern cache_dev_t CACHE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h
index 52b69c6f19b..22ea0a6bf04 100644
--- a/components/soc/esp32h2/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h
@@ -97,9 +97,12 @@ typedef enum {
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1,      /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
     SOC_RTC_FAST_CLK_SRC_LP_PLL = 2,       /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K)*/
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
 } soc_rtc_fast_clk_src_t;
 
 /**
diff --git a/components/soc/esp32h2/include/soc/dport_access.h b/components/soc/esp32h2/include/soc/dport_access.h
index bc42aa9fecc..70f97e86b48 100644
--- a/components/soc/esp32h2/include/soc/dport_access.h
+++ b/components/soc/esp32h2/include/soc/dport_access.h
@@ -7,8 +7,7 @@
 #pragma once
 
 #include <stdint.h>
-#include "soc.h"
-#include "uart_reg.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32h2/include/soc/ecc_mult_reg.h b/components/soc/esp32h2/include/soc/ecc_mult_reg.h
deleted file mode 100644
index 5d7fa6c1c30..00000000000
--- a/components/soc/esp32h2/include/soc/ecc_mult_reg.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ECC_MULT_INT_RAW_REG register
- *  ECC interrupt raw register, valid in level.
- */
-#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
-/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
-#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_RAW_S  0
-
-/** ECC_MULT_INT_ST_REG register
- *  ECC interrupt status register.
- */
-#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
-/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
-#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_ST_S  0
-
-/** ECC_MULT_INT_ENA_REG register
- *  ECC interrupt enable register.
- */
-#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
-/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
-#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_ENA_S  0
-
-/** ECC_MULT_INT_CLR_REG register
- *  ECC interrupt clear register.
- */
-#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
-/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
-#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_CLR_S  0
-
-/** ECC_MULT_CONF_REG register
- *  ECC configure register
- */
-#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
-/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
- *  the caculatrion is done.
- */
-#define ECC_MULT_START    (BIT(0))
-#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
-#define ECC_MULT_START_V  0x00000001U
-#define ECC_MULT_START_S  0
-/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
- *  Write 1 to reset ECC Accelerator.
- */
-#define ECC_MULT_RESET    (BIT(1))
-#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
-#define ECC_MULT_RESET_V  0x00000001U
-#define ECC_MULT_RESET_S  1
-/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
- *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
- */
-#define ECC_MULT_KEY_LENGTH    (BIT(2))
-#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
-#define ECC_MULT_KEY_LENGTH_V  0x00000001U
-#define ECC_MULT_KEY_LENGTH_S  2
-/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
- *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
- *  1: p(mod base of curve)
- */
-#define ECC_MULT_MOD_BASE    (BIT(3))
-#define ECC_MULT_MOD_BASE_M  (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
-#define ECC_MULT_MOD_BASE_V  0x00000001U
-#define ECC_MULT_MOD_BASE_S  3
-/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
- *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
- *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
- *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
- *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
- */
-#define ECC_MULT_WORK_MODE    0x0000000FU
-#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
-#define ECC_MULT_WORK_MODE_V  0x0000000FU
-#define ECC_MULT_WORK_MODE_S  4
-/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define ECC_MULT_SECURITY_MODE    (BIT(8))
-#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
-#define ECC_MULT_SECURITY_MODE_V  0x00000001U
-#define ECC_MULT_SECURITY_MODE_S  8
-/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
- *  The verification result bit of ECC Accelerator, only valid when calculation is done.
- */
-#define ECC_MULT_VERIFICATION_RESULT    (BIT(29))
-#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
-#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
-#define ECC_MULT_VERIFICATION_RESULT_S  29
-/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
- *  Write 1 to force on register clock gate.
- */
-#define ECC_MULT_CLK_EN    (BIT(30))
-#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
-#define ECC_MULT_CLK_EN_V  0x00000001U
-#define ECC_MULT_CLK_EN_S  30
-/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 1;
- *  ECC memory clock gate force on register
- */
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
-
-/** ECC_MULT_DATE_REG register
- *  Version control register
- */
-#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
-/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 35680640;
- *  ECC mult version control register
- */
-#define ECC_MULT_DATE    0x0FFFFFFFU
-#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
-#define ECC_MULT_DATE_V  0x0FFFFFFFU
-#define ECC_MULT_DATE_S  0
-
-/** ECC_MULT_K_MEM register
- *  The memory that stores k.
- */
-#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
-#define ECC_MULT_K_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_PX_MEM register
- *  The memory that stores Px.
- */
-#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
-#define ECC_MULT_PX_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_PY_MEM register
- *  The memory that stores Py.
- */
-#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
-#define ECC_MULT_PY_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QX_MEM register
- *  The memory that stores Qx.
- */
-#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
-#define ECC_MULT_QX_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QY_MEM register
- *  The memory that stores Qy.
- */
-#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
-#define ECC_MULT_QY_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QZ_MEM register
- *  The memory that stores Qz.
- */
-#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0)
-#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/ecc_mult_struct.h b/components/soc/esp32h2/include/soc/ecc_mult_struct.h
deleted file mode 100644
index f1596693a8d..00000000000
--- a/components/soc/esp32h2/include/soc/ecc_mult_struct.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "esp_assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Memory data */
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  ECC interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_raw:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_raw_reg_t;
-
-/** Type of int_st register
- *  ECC interrupt status register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_st:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_st_reg_t;
-
-/** Type of int_ena register
- *  ECC interrupt enable register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_ena:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_ena_reg_t;
-
-/** Type of int_clr register
- *  ECC interrupt clear register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of conf register
- *  ECC configure register
- */
-typedef union {
-    struct {
-        /** start : R/W/SC; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
-         *  the caculatrion is done.
-         */
-        uint32_t start:1;
-        /** reset : WT; bitpos: [1]; default: 0;
-         *  Write 1 to reset ECC Accelerator.
-         */
-        uint32_t reset:1;
-        /** key_length : R/W; bitpos: [2]; default: 0;
-         *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
-         */
-        uint32_t key_length:1;
-        /** mod_base : R/W; bitpos: [3]; default: 0;
-         *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
-         *  1: p(mod base of curve)
-         */
-        uint32_t mod_base:1;
-        /** work_mode : R/W; bitpos: [7:4]; default: 0;
-         *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
-         *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
-         *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
-         *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
-         */
-        uint32_t work_mode:4;
-        /** security_mode : R/W; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t security_mode:1;
-        uint32_t reserved_9:20;
-        /** verification_result : RO/SS; bitpos: [29]; default: 0;
-         *  The verification result bit of ECC Accelerator, only valid when calculation is done.
-         */
-        uint32_t verification_result:1;
-        /** clk_en : R/W; bitpos: [30]; default: 0;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_en:1;
-        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 1;
-         *  ECC memory clock gate force on register
-         */
-        uint32_t mem_clock_gate_force_on:1;
-    };
-    uint32_t val;
-} ecc_mult_conf_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35680640;
-         *  ECC mult version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ecc_mult_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000[3];
-    volatile ecc_mult_int_raw_reg_t int_raw;
-    volatile ecc_mult_int_st_reg_t int_st;
-    volatile ecc_mult_int_ena_reg_t int_ena;
-    volatile ecc_mult_int_clr_reg_t int_clr;
-    volatile ecc_mult_conf_reg_t conf;
-    uint32_t reserved_020[55];
-    volatile ecc_mult_date_reg_t date;
-    volatile uint32_t k[8];
-    volatile uint32_t px[8];
-    volatile uint32_t py[8];
-    volatile uint32_t qx[8];
-    volatile uint32_t qy[8];
-    volatile uint32_t qz[8];
-} ecc_mult_dev_t;
-
-extern ecc_mult_dev_t ECC;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ecc_mult_dev_t) == 0x1C0, "Invalid size of ecc_mult_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/ecdsa_reg.h b/components/soc/esp32h2/include/soc/ecdsa_reg.h
deleted file mode 100644
index 62f2e1ad96d..00000000000
--- a/components/soc/esp32h2/include/soc/ecdsa_reg.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ECDSA_CONF_REG register
- *  ECDSA configure register
- */
-#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
-/** ECDSA_WORK_MODE : R/W; bitpos: [0]; default: 0;
- *  The work mode bits of ECDSA Accelerator. 0: Signature Verify mode. 1: Signature
- *  Generate Mode.
- */
-#define ECDSA_WORK_MODE    (BIT(0))
-#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
-#define ECDSA_WORK_MODE_V  0x00000001U
-#define ECDSA_WORK_MODE_S  0
-/** ECDSA_ECC_CURVE : R/W; bitpos: [1]; default: 0;
- *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
- */
-#define ECDSA_ECC_CURVE    (BIT(1))
-#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
-#define ECDSA_ECC_CURVE_V  0x00000001U
-#define ECDSA_ECC_CURVE_S  1
-/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [2]; default: 0;
- *  The source of k select bit. 0: k is automatically generated by TRNG. 1: k is
- *  written by software.
- */
-#define ECDSA_SOFTWARE_SET_K    (BIT(2))
-#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
-#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
-#define ECDSA_SOFTWARE_SET_K_S  2
-/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [3]; default: 0;
- *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
- *  software.
- */
-#define ECDSA_SOFTWARE_SET_Z    (BIT(3))
-#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
-#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
-#define ECDSA_SOFTWARE_SET_Z_S  3
-
-/** ECDSA_CLK_REG register
- *  ECDSA clock gate register
- */
-#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
-/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  Write 1 to force on register clock gate.
- */
-#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
-#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
-#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
-#define ECDSA_CLK_GATE_FORCE_ON_S  0
-
-/** ECDSA_INT_RAW_REG register
- *  ECDSA interrupt raw register, valid in level.
- */
-#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
-/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_RAW    (BIT(0))
-#define ECDSA_CALC_DONE_INT_RAW_M  (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
-#define ECDSA_CALC_DONE_INT_RAW_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_RAW_S  0
-/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
-#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_RAW_S  1
-
-/** ECDSA_INT_ST_REG register
- *  ECDSA interrupt status register.
- */
-#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
-/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_ST    (BIT(0))
-#define ECDSA_CALC_DONE_INT_ST_M  (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
-#define ECDSA_CALC_DONE_INT_ST_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_ST_S  0
-/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_ST    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
-#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_ST_S  1
-
-/** ECDSA_INT_ENA_REG register
- *  ECDSA interrupt enable register.
- */
-#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
-/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_ENA    (BIT(0))
-#define ECDSA_CALC_DONE_INT_ENA_M  (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
-#define ECDSA_CALC_DONE_INT_ENA_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_ENA_S  0
-/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
-#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_ENA_S  1
-
-/** ECDSA_INT_CLR_REG register
- *  ECDSA interrupt clear register.
- */
-#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
-/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_CLR    (BIT(0))
-#define ECDSA_CALC_DONE_INT_CLR_M  (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
-#define ECDSA_CALC_DONE_INT_CLR_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_CLR_S  0
-/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
-#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_CLR_S  1
-
-/** ECDSA_START_REG register
- *  ECDSA start register
- */
-#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
-/** ECDSA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
- *  after configuration.
- */
-#define ECDSA_START    (BIT(0))
-#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
-#define ECDSA_START_V  0x00000001U
-#define ECDSA_START_S  0
-/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
- *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
- *  self-cleared after configuration.
- */
-#define ECDSA_LOAD_DONE    (BIT(1))
-#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
-#define ECDSA_LOAD_DONE_V  0x00000001U
-#define ECDSA_LOAD_DONE_S  1
-/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
- *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
- *  self-cleared after configuration.
- */
-#define ECDSA_GET_DONE    (BIT(2))
-#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
-#define ECDSA_GET_DONE_V  0x00000001U
-#define ECDSA_GET_DONE_S  2
-
-/** ECDSA_STATE_REG register
- *  ECDSA status register
- */
-#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
-/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
- *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
- *  state.
- */
-#define ECDSA_BUSY    0x00000003U
-#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
-#define ECDSA_BUSY_V  0x00000003U
-#define ECDSA_BUSY_S  0
-
-/** ECDSA_RESULT_REG register
- *  ECDSA result register
- */
-#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
-/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
- *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
- *  done.
- */
-#define ECDSA_OPERATION_RESULT    (BIT(0))
-#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
-#define ECDSA_OPERATION_RESULT_V  0x00000001U
-#define ECDSA_OPERATION_RESULT_S  0
-
-/** ECDSA_DATE_REG register
- *  Version control register
- */
-#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
-/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 35684752;
- *  ECDSA version control register
- */
-#define ECDSA_DATE    0x0FFFFFFFU
-#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
-#define ECDSA_DATE_V  0x0FFFFFFFU
-#define ECDSA_DATE_S  0
-
-/** ECDSA_SHA_MODE_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
-/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
- *  Others: invalid.
- */
-#define ECDSA_SHA_MODE    0x00000007U
-#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
-#define ECDSA_SHA_MODE_V  0x00000007U
-#define ECDSA_SHA_MODE_S  0
-
-/** ECDSA_SHA_START_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
-/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
- *  bit will be self-cleared after configuration.
- */
-#define ECDSA_SHA_START    (BIT(0))
-#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
-#define ECDSA_SHA_START_V  0x00000001U
-#define ECDSA_SHA_START_S  0
-
-/** ECDSA_SHA_CONTINUE_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
-/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
- *  bit will be self-cleared after configuration.
- */
-#define ECDSA_SHA_CONTINUE    (BIT(0))
-#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
-#define ECDSA_SHA_CONTINUE_V  0x00000001U
-#define ECDSA_SHA_CONTINUE_S  0
-
-/** ECDSA_SHA_BUSY_REG register
- *  ECDSA status register
- */
-#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
-/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
- *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
- *  calculation. 0: SHA is idle.
- */
-#define ECDSA_SHA_BUSY    (BIT(0))
-#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
-#define ECDSA_SHA_BUSY_V  0x00000001U
-#define ECDSA_SHA_BUSY_S  0
-
-/** ECDSA_MESSAGE_MEM register
- *  The memory that stores message.
- */
-#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
-#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
-
-/** ECDSA_R_MEM register
- *  The memory that stores r.
- */
-#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
-#define ECDSA_R_MEM_SIZE_BYTES 32
-
-/** ECDSA_S_MEM register
- *  The memory that stores s.
- */
-#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
-#define ECDSA_S_MEM_SIZE_BYTES 32
-
-/** ECDSA_Z_MEM register
- *  The memory that stores software written z.
- */
-#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
-#define ECDSA_Z_MEM_SIZE_BYTES 32
-
-/** ECDSA_QAX_MEM register
- *  The memory that stores x coordinates of QA or software written k.
- */
-#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
-#define ECDSA_QAX_MEM_SIZE_BYTES 32
-
-/** ECDSA_QAY_MEM register
- *  The memory that stores y coordinates of QA.
- */
-#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
-#define ECDSA_QAY_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/ecdsa_struct.h b/components/soc/esp32h2/include/soc/ecdsa_struct.h
deleted file mode 100644
index dcdd806f8ff..00000000000
--- a/components/soc/esp32h2/include/soc/ecdsa_struct.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Data Memory */
-
-/** Group: Configuration registers */
-/** Type of conf register
- *  ECDSA configure register
- */
-typedef union {
-    struct {
-        /** work_mode : R/W; bitpos: [0]; default: 0;
-         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
-         *  Generate Mode.
-         */
-        uint32_t work_mode:1;
-        /** ecc_curve : R/W; bitpos: [1]; default: 0;
-         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
-         */
-        uint32_t ecc_curve:1;
-        /** software_set_k : R/W; bitpos: [2]; default: 0;
-         *  The source of k select bit. 0: k is automatically generated by TRNG. 1: k is
-         *  written by software.
-         */
-        uint32_t software_set_k:1;
-        /** software_set_z : R/W; bitpos: [3]; default: 0;
-         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
-         *  software.
-         */
-        uint32_t software_set_z:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} ecdsa_conf_reg_t;
-
-/** Type of start register
- *  ECDSA start register
- */
-typedef union {
-    struct {
-        /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
-         *  after configuration.
-         */
-        uint32_t start:1;
-        /** load_done : WT; bitpos: [1]; default: 0;
-         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
-         *  self-cleared after configuration.
-         */
-        uint32_t load_done:1;
-        /** get_done : WT; bitpos: [2]; default: 0;
-         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
-         *  self-cleared after configuration.
-         */
-        uint32_t get_done:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} ecdsa_start_reg_t;
-
-
-/** Group: Clock and reset registers */
-/** Type of clk register
- *  ECDSA clock gate register
- */
-typedef union {
-    struct {
-        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_gate_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_clk_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  ECDSA interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_raw:1;
-        /** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_raw_reg_t;
-
-/** Type of int_st register
- *  ECDSA interrupt status register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_st:1;
-        /** sha_release_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_st_reg_t;
-
-/** Type of int_ena register
- *  ECDSA interrupt enable register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_ena:1;
-        /** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_ena_reg_t;
-
-/** Type of int_clr register
- *  ECDSA interrupt clear register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_clr:1;
-        /** sha_release_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_clr_reg_t;
-
-
-/** Group: Status registers */
-/** Type of state register
- *  ECDSA status register
- */
-typedef union {
-    struct {
-        /** busy : RO; bitpos: [1:0]; default: 0;
-         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
-         *  state.
-         */
-        uint32_t busy:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_state_reg_t;
-
-
-/** Group: Result registers */
-/** Type of result register
- *  ECDSA result register
- */
-typedef union {
-    struct {
-        /** operation_result : RO/SS; bitpos: [0]; default: 0;
-         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
-         *  done.
-         */
-        uint32_t operation_result:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_result_reg_t;
-
-
-/** Group: SHA register */
-/** Type of sha_mode register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
-         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
-         *  Others: invalid.
-         */
-        uint32_t sha_mode:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} ecdsa_sha_mode_reg_t;
-
-/** Type of sha_start register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
-         *  bit will be self-cleared after configuration.
-         */
-        uint32_t sha_start:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_start_reg_t;
-
-/** Type of sha_continue register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_continue : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
-         *  bit will be self-cleared after configuration.
-         */
-        uint32_t sha_continue:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_continue_reg_t;
-
-/** Type of sha_busy register
- *  ECDSA status register
- */
-typedef union {
-    struct {
-        /** sha_busy : RO; bitpos: [0]; default: 0;
-         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
-         *  calculation. 0: SHA is idle.
-         */
-        uint32_t sha_busy:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_busy_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35684752;
-         *  ECDSA version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ecdsa_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000;
-    volatile ecdsa_conf_reg_t conf;
-    volatile ecdsa_clk_reg_t clk;
-    volatile ecdsa_int_raw_reg_t int_raw;
-    volatile ecdsa_int_st_reg_t int_st;
-    volatile ecdsa_int_ena_reg_t int_ena;
-    volatile ecdsa_int_clr_reg_t int_clr;
-    volatile ecdsa_start_reg_t start;
-    volatile ecdsa_state_reg_t state;
-    volatile ecdsa_result_reg_t result;
-    uint32_t reserved_028[53];
-    volatile ecdsa_date_reg_t date;
-    uint32_t reserved_100[64];
-    volatile ecdsa_sha_mode_reg_t sha_mode;
-    uint32_t reserved_204[3];
-    volatile ecdsa_sha_start_reg_t sha_start;
-    volatile ecdsa_sha_continue_reg_t sha_continue;
-    volatile ecdsa_sha_busy_reg_t sha_busy;
-    uint32_t reserved_21c[25];
-    volatile uint32_t message[8];
-    uint32_t reserved_2a0[472];
-    volatile uint32_t r[8];
-    volatile uint32_t s[8];
-    volatile uint32_t z[8];
-    volatile uint32_t qax[8];
-    volatile uint32_t qay[8];
-} ecdsa_dev_t;
-
-extern ecdsa_dev_t ECDSA;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/efuse_reg.h b/components/soc/esp32h2/include/soc/efuse_reg.h
deleted file mode 100644
index 532514d5876..00000000000
--- a/components/soc/esp32h2/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,2706 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#include "efuse_defs.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 3rd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS_REG register
- *  BLOCK0 data register 0.
- */
-#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Represents whether programming of individual eFuse memory bit is disabled or
- *  enabled. 1: Disabled. 0 Enabled.
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  BLOCK0 data register 1.
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_RPT4_RESERVED0_4 : RO; bitpos: [7]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_4    (BIT(7))
-#define EFUSE_RPT4_RESERVED0_4_M  (EFUSE_RPT4_RESERVED0_4_V << EFUSE_RPT4_RESERVED0_4_S)
-#define EFUSE_RPT4_RESERVED0_4_V  0x00000001U
-#define EFUSE_RPT4_RESERVED0_4_S  7
-/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
- *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_ICACHE    (BIT(8))
-#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
-#define EFUSE_DIS_ICACHE_V  0x00000001U
-#define EFUSE_DIS_ICACHE_S  8
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
- *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  9
-/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
- *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_POWERGLITCH_EN    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
-#define EFUSE_POWERGLITCH_EN_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
- *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Represents whether the function that forces chip into download mode is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
- *  Represents whether SPI0 controller during boot_mode_download is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
-/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
-#define EFUSE_DIS_TWAI_V  0x00000001U
-#define EFUSE_DIS_TWAI_S  14
-/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- */
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
-#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_S  15
-/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
- *  enabled.
- */
-#define EFUSE_SOFT_DIS_JTAG    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
-#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
- *  enabled.
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
- *  mode). 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFH    0x00000003U
-#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
-#define EFUSE_USB_DREFH_V  0x00000003U
-#define EFUSE_USB_DREFH_S  21
-/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
- */
-#define EFUSE_USB_DREFL    0x00000003U
-#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
-#define EFUSE_USB_DREFL_V  0x00000003U
-#define EFUSE_USB_DREFL_S  23
-/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
- *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.
- */
-#define EFUSE_USB_EXCHG_PINS    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
-#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_S  25
-/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
- *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
- *  functioned.
- */
-#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
-#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_S  26
-/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_2    0x00000003U
-#define EFUSE_RPT4_RESERVED0_2_M  (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S)
-#define EFUSE_RPT4_RESERVED0_2_V  0x00000003U
-#define EFUSE_RPT4_RESERVED0_2_S  27
-/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_1    (BIT(29))
-#define EFUSE_RPT4_RESERVED0_1_M  (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S)
-#define EFUSE_RPT4_RESERVED0_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED0_1_S  29
-/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_0    0x00000003U
-#define EFUSE_RPT4_RESERVED0_0_M  (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S)
-#define EFUSE_RPT4_RESERVED0_0_V  0x00000003U
-#define EFUSE_RPT4_RESERVED0_0_S  30
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  BLOCK0 data register 2.
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_RPT4_RESERVED1_1 : RO; bitpos: [15:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED1_1    0x0000FFFFU
-#define EFUSE_RPT4_RESERVED1_1_M  (EFUSE_RPT4_RESERVED1_1_V << EFUSE_RPT4_RESERVED1_1_S)
-#define EFUSE_RPT4_RESERVED1_1_V  0x0000FFFFU
-#define EFUSE_RPT4_RESERVED1_1_S  0
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
- *  selected. 0: not selected.
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
- *  1: enabled. Even number of 1: disabled.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking first secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Represents whether revoking second secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Represents whether revoking third secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Represents the purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  24
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Represents the purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  BLOCK0 data register 3.
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Represents the purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  0
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Represents the purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  4
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Represents the purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  8
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Represents the purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  12
-/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the spa secure level by configuring the clock random divide mode.
- */
-#define EFUSE_SEC_DPA_LEVEL    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
-#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_S  16
-/** EFUSE_ECDSA_FORCE_USE_HARDWARE_K : RO; bitpos: [18]; default: 1;
- *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
- *  0: not force used.
- */
-#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K    (BIT(18))
-#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_M  (EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V << EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S)
-#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V  0x00000001U
-#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S  18
-/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
- *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
- */
-#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
-#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_S  19
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED2_0    0x0000003FU
-#define EFUSE_RPT4_RESERVED2_0_M  (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S)
-#define EFUSE_RPT4_RESERVED2_0_V  0x0000003FU
-#define EFUSE_RPT4_RESERVED2_0_S  22
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Represents the flash waiting time after power-up, in unit of ms. When the value
- *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
- *  is 2 times the programmed value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  BLOCK0 data register 4.
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Set this bit to disable USB-Serial-JTAG print during rom boot.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_5    (BIT(3))
-#define EFUSE_RPT4_RESERVED3_5_M  (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S)
-#define EFUSE_RPT4_RESERVED3_5_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_5_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Represents whether security download is enabled or disabled. 1: enabled. 0:
- *  disabled.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Represents the type of UART printing. 00: force enable printing. 01: enable
- *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
- *  at high level. 11: force disable printing.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
- *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
- *  forced. 0:not forced.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  8
-/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
- *  Represents the version used by ESP-IDF anti-rollback feature.
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
- *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
-/** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0;
- *  Set bits to enable hysteresis function of PAD0~5
- */
-#define EFUSE_HYS_EN_PAD0    0x0000003FU
-#define EFUSE_HYS_EN_PAD0_M  (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S)
-#define EFUSE_HYS_EN_PAD0_V  0x0000003FU
-#define EFUSE_HYS_EN_PAD0_S  26
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  BLOCK0 data register 5.
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0;
- *  Set bits to enable hysteresis function of PAD6~27
- */
-#define EFUSE_HYS_EN_PAD1    0x003FFFFFU
-#define EFUSE_HYS_EN_PAD1_M  (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S)
-#define EFUSE_HYS_EN_PAD1_V  0x003FFFFFU
-#define EFUSE_HYS_EN_PAD1_S  0
-/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:22]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED4_1    0x00000003U
-#define EFUSE_RPT4_RESERVED4_1_M  (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S)
-#define EFUSE_RPT4_RESERVED4_1_V  0x00000003U
-#define EFUSE_RPT4_RESERVED4_1_S  22
-/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED4_0    0x000000FFU
-#define EFUSE_RPT4_RESERVED4_0_M  (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S)
-#define EFUSE_RPT4_RESERVED4_0_V  0x000000FFU
-#define EFUSE_RPT4_RESERVED4_0_S  24
-
-/** EFUSE_RD_MAC_SYS_0_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the low 32 bits of MAC address.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SYS_1_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Stores the high 16 bits of MAC address.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
- *  Stores the extended bits of MAC address.
- */
-#define EFUSE_MAC_EXT    0x0000FFFFU
-#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
-#define EFUSE_MAC_EXT_V  0x0000FFFFU
-#define EFUSE_MAC_EXT_S  16
-
-/** EFUSE_RD_MAC_SYS_2_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
-/** EFUSE_RXIQ_VERSION : RO; bitpos: [2:0]; default: 0;
- *  Stores RF Calibration data. RXIQ version.
- */
-#define EFUSE_RXIQ_VERSION    0x00000007U
-#define EFUSE_RXIQ_VERSION_M  (EFUSE_RXIQ_VERSION_V << EFUSE_RXIQ_VERSION_S)
-#define EFUSE_RXIQ_VERSION_V  0x00000007U
-#define EFUSE_RXIQ_VERSION_S  0
-/** EFUSE_RXIQ_0 : RO; bitpos: [9:3]; default: 0;
- *  Stores RF Calibration data. RXIQ data 0.
- */
-#define EFUSE_RXIQ_0    0x0000007FU
-#define EFUSE_RXIQ_0_M  (EFUSE_RXIQ_0_V << EFUSE_RXIQ_0_S)
-#define EFUSE_RXIQ_0_V  0x0000007FU
-#define EFUSE_RXIQ_0_S  3
-/** EFUSE_RXIQ_1 : RO; bitpos: [16:10]; default: 0;
- *  Stores RF Calibration data. RXIQ data 1.
- */
-#define EFUSE_RXIQ_1    0x0000007FU
-#define EFUSE_RXIQ_1_M  (EFUSE_RXIQ_1_V << EFUSE_RXIQ_1_S)
-#define EFUSE_RXIQ_1_V  0x0000007FU
-#define EFUSE_RXIQ_1_S  10
-/** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [21:17]; default: 0;
- *  Stores the PMU active hp dbias.
- */
-#define EFUSE_ACTIVE_HP_DBIAS    0x0000001FU
-#define EFUSE_ACTIVE_HP_DBIAS_M  (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
-#define EFUSE_ACTIVE_HP_DBIAS_V  0x0000001FU
-#define EFUSE_ACTIVE_HP_DBIAS_S  17
-/** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [26:22]; default: 0;
- *  Stores the PMU active lp dbias.
- */
-#define EFUSE_ACTIVE_LP_DBIAS    0x0000001FU
-#define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
-#define EFUSE_ACTIVE_LP_DBIAS_V  0x0000001FU
-#define EFUSE_ACTIVE_LP_DBIAS_S  22
-/** EFUSE_DSLP_DBIAS : RO; bitpos: [30:27]; default: 0;
- *  Stores the PMU sleep dbias.
- */
-#define EFUSE_DSLP_DBIAS    0x0000000FU
-#define EFUSE_DSLP_DBIAS_M  (EFUSE_DSLP_DBIAS_V << EFUSE_DSLP_DBIAS_S)
-#define EFUSE_DSLP_DBIAS_V  0x0000000FU
-#define EFUSE_DSLP_DBIAS_S  27
-/** EFUSE_DBIAS_VOL_GAP_VALUE1 : RO; bitpos: [31]; default: 0;
- *  Stores the low 1 bit of dbias_vol_gap.
- */
-#define EFUSE_DBIAS_VOL_GAP_VALUE1    (BIT(31))
-#define EFUSE_DBIAS_VOL_GAP_VALUE1_M  (EFUSE_DBIAS_VOL_GAP_VALUE1_V << EFUSE_DBIAS_VOL_GAP_VALUE1_S)
-#define EFUSE_DBIAS_VOL_GAP_VALUE1_V  0x00000001U
-#define EFUSE_DBIAS_VOL_GAP_VALUE1_S  31
-
-/** EFUSE_RD_MAC_SYS_3_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_DBIAS_VOL_GAP_VALUE2 : RO; bitpos: [2:0]; default: 0;
- *  Stores the high 3 bits of dbias_vol_gap.
- */
-#define EFUSE_DBIAS_VOL_GAP_VALUE2    0x00000007U
-#define EFUSE_DBIAS_VOL_GAP_VALUE2_M  (EFUSE_DBIAS_VOL_GAP_VALUE2_V << EFUSE_DBIAS_VOL_GAP_VALUE2_S)
-#define EFUSE_DBIAS_VOL_GAP_VALUE2_V  0x00000007U
-#define EFUSE_DBIAS_VOL_GAP_VALUE2_S  0
-/** EFUSE_DBIAS_VOL_GAP_SIGN : RO; bitpos: [3]; default: 0;
- *  Stores the sign bit of dbias_vol_gap.
- */
-#define EFUSE_DBIAS_VOL_GAP_SIGN    (BIT(3))
-#define EFUSE_DBIAS_VOL_GAP_SIGN_M  (EFUSE_DBIAS_VOL_GAP_SIGN_V << EFUSE_DBIAS_VOL_GAP_SIGN_S)
-#define EFUSE_DBIAS_VOL_GAP_SIGN_V  0x00000001U
-#define EFUSE_DBIAS_VOL_GAP_SIGN_S  3
-/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:4]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_2    0x00003FFFU
-#define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
-#define EFUSE_MAC_RESERVED_2_V  0x00003FFFU
-#define EFUSE_MAC_RESERVED_2_S  4
-/** EFUSE_WAFER_VERSION_MINOR : RO; bitpos: [20:18]; default: 0;
- *  Stores the wafer version minor.
- */
-#define EFUSE_WAFER_VERSION_MINOR    0x00000007U
-#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
-#define EFUSE_WAFER_VERSION_MINOR_V  0x00000007U
-#define EFUSE_WAFER_VERSION_MINOR_S  18
-/** EFUSE_WAFER_VERSION_MAJOR : RO; bitpos: [22:21]; default: 0;
- *  Stores the wafer version major.
- */
-#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_S  21
-/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : RO; bitpos: [23]; default: 0;
- *  Disables check of wafer version major.
- */
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(23))
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  23
-/** EFUSE_FLASH_CAP : RO; bitpos: [26:24]; default: 0;
- *  Stores the flash cap.
- */
-#define EFUSE_FLASH_CAP    0x00000007U
-#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
-#define EFUSE_FLASH_CAP_V  0x00000007U
-#define EFUSE_FLASH_CAP_S  24
-/** EFUSE_FLASH_TEMP : RO; bitpos: [28:27]; default: 0;
- *  Stores the flash temp.
- */
-#define EFUSE_FLASH_TEMP    0x00000003U
-#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
-#define EFUSE_FLASH_TEMP_V  0x00000003U
-#define EFUSE_FLASH_TEMP_S  27
-/** EFUSE_FLASH_VENDOR : RO; bitpos: [31:29]; default: 0;
- *  Stores the flash vendor.
- */
-#define EFUSE_FLASH_VENDOR    0x00000007U
-#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
-#define EFUSE_FLASH_VENDOR_V  0x00000007U
-#define EFUSE_FLASH_VENDOR_S  29
-
-/** EFUSE_RD_MAC_SYS_4_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_PKG_VERSION : R; bitpos: [2:0]; default: 0;
- *  Package version
- */
-#define EFUSE_PKG_VERSION    0x00000007U
-#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
-#define EFUSE_PKG_VERSION_V  0x00000007U
-#define EFUSE_PKG_VERSION_S  0
-/** EFUSE_RESERVED_1_131 : R; bitpos: [31:3]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_131    0x1FFFFFFFU
-#define EFUSE_RESERVED_1_131_M  (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S)
-#define EFUSE_RESERVED_1_131_V  0x1FFFFFFFU
-#define EFUSE_RESERVED_1_131_S  3
-
-/** EFUSE_RD_MAC_SYS_5_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
-#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_RESERVED_2_128 : R; bitpos: [1:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_128    0x00000003U
-#define EFUSE_RESERVED_2_128_M  (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
-#define EFUSE_RESERVED_2_128_V  0x00000003U
-#define EFUSE_RESERVED_2_128_S  0
-/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [4:2]; default: 0;
- *  BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1
- */
-#define EFUSE_BLK_VERSION_MINOR    0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
-#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_S  2
-/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [6:5]; default: 0;
- *  BLK_VERSION_MAJOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
-#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_S  5
-/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
- *  Disables check of blk version major
- */
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
-/** EFUSE_TEMP_CALIB : R; bitpos: [16:8]; default: 0;
- *  Temperature calibration data
- */
-#define EFUSE_TEMP_CALIB    0x000001FFU
-#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
-#define EFUSE_TEMP_CALIB_V  0x000001FFU
-#define EFUSE_TEMP_CALIB_S  8
-/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN0    0x000003FFU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V  0x000003FFU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S  17
-/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN1    0x0000001FU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V  0x0000001FU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S  27
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1    0x0000001FU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S)
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V  0x0000001FU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S  0
-/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN2    0x000003FFU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V  0x000003FFU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S  5
-/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN3    0x000003FFU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V  0x000003FFU
-#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S  15
-/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_HI_DOUT_ATTEN0    0x0000007FU
-#define EFUSE_ADC1_HI_DOUT_ATTEN0_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
-#define EFUSE_ADC1_HI_DOUT_ATTEN0_V  0x0000007FU
-#define EFUSE_ADC1_HI_DOUT_ATTEN0_S  25
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_HI_DOUT_ATTEN0_1    0x00000007U
-#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
-#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V  0x00000007U
-#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S  0
-/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_HI_DOUT_ATTEN1    0x000003FFU
-#define EFUSE_ADC1_HI_DOUT_ATTEN1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
-#define EFUSE_ADC1_HI_DOUT_ATTEN1_V  0x000003FFU
-#define EFUSE_ADC1_HI_DOUT_ATTEN1_S  3
-/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_HI_DOUT_ATTEN2    0x000003FFU
-#define EFUSE_ADC1_HI_DOUT_ATTEN2_M  (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
-#define EFUSE_ADC1_HI_DOUT_ATTEN2_V  0x000003FFU
-#define EFUSE_ADC1_HI_DOUT_ATTEN2_S  13
-/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_HI_DOUT_ATTEN3    0x000001FFU
-#define EFUSE_ADC1_HI_DOUT_ATTEN3_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
-#define EFUSE_ADC1_HI_DOUT_ATTEN3_V  0x000001FFU
-#define EFUSE_ADC1_HI_DOUT_ATTEN3_S  23
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_HI_DOUT_ATTEN3_1    (BIT(0))
-#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
-#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V  0x00000001U
-#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S  0
-/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
-#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
-#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
-#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S  1
-/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
-#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
-#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
-#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S  5
-/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
-#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
-#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
-#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S  9
-/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
-#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
-#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
-#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S  13
-/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0;
- *  ADC1 calibration data
- */
-#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
-#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
-#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
-#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S  17
-/** EFUSE_RESERVED_2_245 : R; bitpos: [31:21]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_245    0x000007FFU
-#define EFUSE_RESERVED_2_245_M  (EFUSE_RESERVED_2_245_V << EFUSE_RESERVED_2_245_S)
-#define EFUSE_RESERVED_2_245_V  0x000007FFU
-#define EFUSE_RESERVED_2_245_S  21
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_192    0x000000FFU
-#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
-#define EFUSE_RESERVED_3_192_V  0x000000FFU
-#define EFUSE_RESERVED_3_192_S  0
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_S  8
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_248    0x000000FFU
-#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
-#define EFUSE_RESERVED_3_248_V  0x000000FFU
-#define EFUSE_RESERVED_3_248_S  24
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_ERR0_REG register
- *  Programming error record register 0 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  Indicates a programming error of RD_DIS.
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_RPT4_RESERVED0_ERR_4 : RO; bitpos: [7]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_ERR_4    (BIT(7))
-#define EFUSE_RPT4_RESERVED0_ERR_4_M  (EFUSE_RPT4_RESERVED0_ERR_4_V << EFUSE_RPT4_RESERVED0_ERR_4_S)
-#define EFUSE_RPT4_RESERVED0_ERR_4_V  0x00000001U
-#define EFUSE_RPT4_RESERVED0_ERR_4_S  7
-/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of DIS_ICACHE.
- */
-#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
-#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
-#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_ICACHE_ERR_S  8
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  Indicates a programming error of DIS_USB_JTAG.
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  9
-/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
- *  Indicates a programming error of POWERGLITCH_EN.
- */
-#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
-#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_ERR_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
- *  Indicates a programming error of DIS_USB_DEVICE.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
-/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
- *  Indicates a programming error of DIS_CAN.
- */
-#define EFUSE_DIS_TWAI_ERR    (BIT(14))
-#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
-#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
-#define EFUSE_DIS_TWAI_ERR_S  14
-/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
- *  Indicates a programming error of JTAG_SEL_ENABLE.
- */
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
-/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  Indicates a programming error of SOFT_DIS_JTAG.
- */
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of DIS_PAD_JTAG.
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
- *  Indicates a programming error of USB_DREFH.
- */
-#define EFUSE_USB_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
-#define EFUSE_USB_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DREFH_ERR_S  21
-/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
- *  Indicates a programming error of USB_DREFL.
- */
-#define EFUSE_USB_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
-#define EFUSE_USB_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DREFL_ERR_S  23
-/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of USB_EXCHG_PINS.
- */
-#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
-#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_ERR_S  25
-/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
- *  Indicates a programming error of VDD_SPI_AS_GPIO.
- */
-#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
-/** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_ERR_2    0x00000003U
-#define EFUSE_RPT4_RESERVED0_ERR_2_M  (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S)
-#define EFUSE_RPT4_RESERVED0_ERR_2_V  0x00000003U
-#define EFUSE_RPT4_RESERVED0_ERR_2_S  27
-/** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_ERR_1    (BIT(29))
-#define EFUSE_RPT4_RESERVED0_ERR_1_M  (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S)
-#define EFUSE_RPT4_RESERVED0_ERR_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED0_ERR_1_S  29
-/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED0_ERR_0    0x00000003U
-#define EFUSE_RPT4_RESERVED0_ERR_0_M  (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S)
-#define EFUSE_RPT4_RESERVED0_ERR_0_V  0x00000003U
-#define EFUSE_RPT4_RESERVED0_ERR_0_S  30
-
-/** EFUSE_RD_REPEAT_ERR1_REG register
- *  Programming error record register 1 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED1_ERR_0    0x0000FFFFU
-#define EFUSE_RPT4_RESERVED1_ERR_0_M  (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S)
-#define EFUSE_RPT4_RESERVED1_ERR_0_V  0x0000FFFFU
-#define EFUSE_RPT4_RESERVED1_ERR_0_S  0
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of WDT_DELAY_SEL.
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_0.
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_1.
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR2_REG register
- *  Programming error record register 2 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_2.
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  0
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_3.
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_4.
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_5.
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of SEC_DPA_LEVEL.
- */
-#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
-#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
-/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED2_ERR_1    (BIT(18))
-#define EFUSE_RPT4_RESERVED2_ERR_1_M  (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S)
-#define EFUSE_RPT4_RESERVED2_ERR_1_V  0x00000001U
-#define EFUSE_RPT4_RESERVED2_ERR_1_S  18
-/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of CRYPT_DPA_ENABLE.
- */
-#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_EN.
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED2_ERR_0    0x0000003FU
-#define EFUSE_RPT4_RESERVED2_ERR_0_M  (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S)
-#define EFUSE_RPT4_RESERVED2_ERR_0_V  0x0000003FU
-#define EFUSE_RPT4_RESERVED2_ERR_0_S  22
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of FLASH_TPUW.
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR3_REG register
- *  Programming error record register 3 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  Indicates a programming error of DIS_DIRECT_BOOT.
- */
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
-/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0;
- *  Indicates a programming error of UART_PRINT_CHANNEL.
- */
-#define EFUSE_USB_PRINT_ERR    (BIT(2))
-#define EFUSE_USB_PRINT_ERR_M  (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S)
-#define EFUSE_USB_PRINT_ERR_V  0x00000001U
-#define EFUSE_USB_PRINT_ERR_S  2
-/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED3_ERR_5    (BIT(3))
-#define EFUSE_RPT4_RESERVED3_ERR_5_M  (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S)
-#define EFUSE_RPT4_RESERVED3_ERR_5_V  0x00000001U
-#define EFUSE_RPT4_RESERVED3_ERR_5_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  Indicates a programming error of UART_PRINT_CONTROL.
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of FORCE_SEND_RESUME.
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
- *  Indicates a programming error of SECURE VERSION.
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
-/** EFUSE_HYS_EN_PAD0_ERR : RO; bitpos: [31:26]; default: 0;
- *  Indicates a programming error of HYS_EN_PAD0.
- */
-#define EFUSE_HYS_EN_PAD0_ERR    0x0000003FU
-#define EFUSE_HYS_EN_PAD0_ERR_M  (EFUSE_HYS_EN_PAD0_ERR_V << EFUSE_HYS_EN_PAD0_ERR_S)
-#define EFUSE_HYS_EN_PAD0_ERR_V  0x0000003FU
-#define EFUSE_HYS_EN_PAD0_ERR_S  26
-
-/** EFUSE_RD_REPEAT_ERR4_REG register
- *  Programming error record register 4 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
-/** EFUSE_HYS_EN_PAD1_ERR : RO; bitpos: [21:0]; default: 0;
- *  Indicates a programming error of HYS_EN_PAD1.
- */
-#define EFUSE_HYS_EN_PAD1_ERR    0x003FFFFFU
-#define EFUSE_HYS_EN_PAD1_ERR_M  (EFUSE_HYS_EN_PAD1_ERR_V << EFUSE_HYS_EN_PAD1_ERR_S)
-#define EFUSE_HYS_EN_PAD1_ERR_V  0x003FFFFFU
-#define EFUSE_HYS_EN_PAD1_ERR_S  0
-/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:22]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED4_ERR_1    0x00000003U
-#define EFUSE_RPT4_RESERVED4_ERR_1_M  (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S)
-#define EFUSE_RPT4_RESERVED4_ERR_1_V  0x00000003U
-#define EFUSE_RPT4_RESERVED4_ERR_1_S  22
-/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED4_ERR_0    0x000000FFU
-#define EFUSE_RPT4_RESERVED4_ERR_0_M  (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S)
-#define EFUSE_RPT4_RESERVED4_ERR_0_V  0x000000FFU
-#define EFUSE_RPT4_RESERVED4_ERR_0_S  24
-
-/** EFUSE_RD_RS_ERR0_REG register
- *  Programming error record register 0 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
-#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
-#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
-#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
-/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_MAC_SPI_8M_FAIL    (BIT(3))
-#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
-#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
-#define EFUSE_MAC_SPI_8M_FAIL_S  3
-/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART1_NUM    0x00000007U
-#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
-#define EFUSE_SYS_PART1_NUM_V  0x00000007U
-#define EFUSE_SYS_PART1_NUM_S  4
-/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part1 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART1_FAIL    (BIT(7))
-#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
-#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART1_FAIL_S  7
-/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
-#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_S  8
-/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  0: Means no failure and that the user data is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
-#define EFUSE_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_USR_DATA_FAIL_S  11
-/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY0_ERR_NUM    0x00000007U
-#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
-#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY0_ERR_NUM_S  12
-/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
- *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
- *  key0 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY0_FAIL    (BIT(15))
-#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
-#define EFUSE_KEY0_FAIL_V  0x00000001U
-#define EFUSE_KEY0_FAIL_S  15
-/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY1_ERR_NUM    0x00000007U
-#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
-#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY1_ERR_NUM_S  16
-/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
- *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
- *  key1 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY1_FAIL    (BIT(19))
-#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
-#define EFUSE_KEY1_FAIL_V  0x00000001U
-#define EFUSE_KEY1_FAIL_S  19
-/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY2_ERR_NUM    0x00000007U
-#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
-#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY2_ERR_NUM_S  20
-/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
- *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
- *  key2 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY2_FAIL    (BIT(23))
-#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
-#define EFUSE_KEY2_FAIL_V  0x00000001U
-#define EFUSE_KEY2_FAIL_S  23
-/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY3_ERR_NUM    0x00000007U
-#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
-#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY3_ERR_NUM_S  24
-/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
- *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
- *  key3 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY3_FAIL    (BIT(27))
-#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
-#define EFUSE_KEY3_FAIL_V  0x00000001U
-#define EFUSE_KEY3_FAIL_S  27
-/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY4_ERR_NUM    0x00000007U
-#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
-#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY4_ERR_NUM_S  28
-/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
- *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
- *  key4 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY4_FAIL    (BIT(31))
-#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
-#define EFUSE_KEY4_FAIL_V  0x00000001U
-#define EFUSE_KEY4_FAIL_S  31
-
-/** EFUSE_RD_RS_ERR1_REG register
- *  Programming error record register 1 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY5_ERR_NUM    0x00000007U
-#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
-#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY5_ERR_NUM_S  0
-/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
- *  key5 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY5_FAIL    (BIT(3))
-#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
-#define EFUSE_KEY5_FAIL_V  0x00000001U
-#define EFUSE_KEY5_FAIL_S  3
-/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
-#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_S  4
-/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part2 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART2_FAIL    (BIT(7))
-#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
-#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART2_FAIL_S  7
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
-/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit to force enable eFuse register configuration clock signal.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A:  programming operation command 0x5AA5: read operation command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
- *  Configures which block to use for ECDSA key output.
- */
-#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
-#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_S  16
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
- *  The value of OTP_LOAD_SW.
- */
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
-#define EFUSE_OTP_LOAD_SW_V  0x00000001U
-#define EFUSE_OTP_LOAD_SW_S  4
-/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
- *  The value of OTP_VDDQ_C_SYNC2.
- */
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
- *  The value of OTP_STROBE_SW.
- */
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
-#define EFUSE_OTP_STROBE_SW_V  0x00000001U
-#define EFUSE_OTP_STROBE_SW_S  6
-/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
- *  The value of OTP_CSB_SW.
- */
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
-#define EFUSE_OTP_CSB_SW_V  0x00000001U
-#define EFUSE_OTP_CSB_SW_S  7
-/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
- *  The value of OTP_PGENB_SW.
- */
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
-#define EFUSE_OTP_PGENB_SW_V  0x00000001U
-#define EFUSE_OTP_PGENB_SW_S  8
-/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
- *  The value of OTP_VDDQ_IS_SW.
- */
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
- *  Indicates the number of block valid bit.
- */
-#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
- *  Indicates which block is used for ECDSA key output.
- */
-#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
-#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_S  20
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
-/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the read hold time.
- */
-#define EFUSE_THR_A    0x000000FFU
-#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
-#define EFUSE_THR_A_V  0x000000FFU
-#define EFUSE_THR_A_S  0
-/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
- *  Configures the read time.
- */
-#define EFUSE_TRD    0x000000FFU
-#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
-#define EFUSE_TRD_V  0x000000FFU
-#define EFUSE_TRD_S  8
-/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
- *  Configures the read setup time.
- */
-#define EFUSE_TSUR_A    0x000000FFU
-#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
-#define EFUSE_TSUR_A_V  0x000000FFU
-#define EFUSE_TSUR_A_S  16
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
- *  Configures the waiting time of reading eFuse memory.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
-/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the programming setup time.
- */
-#define EFUSE_TSUP_A    0x000000FFU
-#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
-#define EFUSE_TSUP_A_V  0x000000FFU
-#define EFUSE_TSUP_A_S  0
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
- *  Configures the programming hold time.
- */
-#define EFUSE_THP_A    0x000000FFU
-#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
-#define EFUSE_THP_A_V  0x000000FFU
-#define EFUSE_THP_A_S  24
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
- *  Configures the active programming time.
- */
-#define EFUSE_TPGM    0x0000FFFFU
-#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
-#define EFUSE_TPGM_V  0x0000FFFFU
-#define EFUSE_TPGM_S  16
-
-/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
-/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
- *  Set this bit to bypass reed solomon correction step.
- */
-#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
-#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
-#define EFUSE_BYPASS_RS_CORRECTION_S  0
-/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
- *  Configures block number of programming twice operation.
- */
-#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
-#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_S  1
-/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
- *  Set this bit to update multi-bit register signals.
- */
-#define EFUSE_UPDATE    (BIT(12))
-#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
-#define EFUSE_UPDATE_V  0x00000001U
-#define EFUSE_UPDATE_S  12
-/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
- *  Configures the inactive programming time.
- */
-#define EFUSE_TPGM_INACTIVE    0x000000FFU
-#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
-#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
-#define EFUSE_TPGM_INACTIVE_S  13
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/efuse_struct.h b/components/soc/esp32h2/include/soc/efuse_struct.h
deleted file mode 100644
index c64eaa140c8..00000000000
--- a/components/soc/esp32h2/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,2433 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PGM Data Register */
-/** Type of pgm_data0 register
- *  Register 0 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Register 1 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Register 2 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Register 3 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 3rd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Register 4 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 4th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Register 5 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 5th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Register 6 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 6th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Register 7 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 7th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-/** Type of pgm_check_value0 register
- *  Register 0 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Register 1 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Register 2 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: Read Data Register */
-/** Type of rd_wr_dis register
- *  BLOCK0 data register 0.
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled or
-         *  enabled. 1: Disabled. 0 Enabled.
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  BLOCK0 data register 1.
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t rd_dis:7;
-        /** rpt4_reserved0_4 : RO; bitpos: [7]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_4:1;
-        /** dis_icache : RO; bitpos: [8]; default: 0;
-         *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_icache:1;
-        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_jtag:1;
-        /** powerglitch_en : RO; bitpos: [10]; default: 0;
-         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
-         */
-        uint32_t powerglitch_en:1;
-        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
-         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Represents whether the function that forces chip into download mode is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_force_download:1;
-        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
-         *  Represents whether SPI0 controller during boot_mode_download is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t spi_download_mspi_dis:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_twai:1;
-        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         */
-        uint32_t jtag_sel_enable:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
-         *  enabled.
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
-         *  mode). 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefh:2;
-        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
-         */
-        uint32_t usb_drefl:2;
-        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
-         *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.
-         */
-        uint32_t usb_exchg_pins:1;
-        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
-         *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
-         *  functioned.
-         */
-        uint32_t vdd_spi_as_gpio:1;
-        /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_2:2;
-        /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_1:1;
-        /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_0:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  BLOCK0 data register 2.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved1_1 : RO; bitpos: [15:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved1_1:16;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
-         *  selected. 0: not selected.
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
-         *  1: enabled. Even number of 1: disabled.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Represents the purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Represents the purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  BLOCK0 data register 3.
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Represents the purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Represents the purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Represents the purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Represents the purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
-         *  Represents the spa secure level by configuring the clock random divide mode.
-         */
-        uint32_t sec_dpa_level:2;
-        /** ecdsa_force_use_hardware_k : RO; bitpos: [18]; default: 1;
-         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
-         *  0: not force used.
-         */
-        uint32_t ecdsa_force_use_hardware_k:1;
-        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
-         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
-         */
-        uint32_t crypt_dpa_enable:1;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved2_0:6;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Represents the flash waiting time after power-up, in unit of ms. When the value
-         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
-         *  is 2 times the programmed value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  BLOCK0 data register 4.
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Set this bit to disable USB-Serial-JTAG print during rom boot.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_5:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
-         *  disabled.
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Represents the type of UART printing. 00: force enable printing. 01: enable
-         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
-         *  at high level. 11: force disable printing.
-         */
-        uint32_t uart_print_control:2;
-        /** force_send_resume : RO; bitpos: [8]; default: 0;
-         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
-         *  forced. 0:not forced.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [24:9]; default: 0;
-         *  Represents the version used by ESP-IDF anti-rollback feature.
-         */
-        uint32_t secure_version:16;
-        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
-         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t secure_boot_disable_fast_wake:1;
-        /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0;
-         *  Set bits to enable hysteresis function of PAD0~5
-         */
-        uint32_t hys_en_pad0:6;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  BLOCK0 data register 5.
- */
-typedef union {
-    struct {
-        /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0;
-         *  Set bits to enable hysteresis function of PAD6~27
-         */
-        uint32_t hys_en_pad1:22;
-        /** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved4_1:2;
-        /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved4_0:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-/** Type of rd_mac_sys_0 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the low 32 bits of MAC address.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_0_reg_t;
-
-/** Type of rd_mac_sys_1 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Stores the high 16 bits of MAC address.
-         */
-        uint32_t mac_1:16;
-        /** mac_ext : RO; bitpos: [31:16]; default: 0;
-         *  Stores the extended bits of MAC address.
-         */
-        uint32_t mac_ext:16;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_1_reg_t;
-
-/** Type of rd_mac_sys_2 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** rxiq_version : RO; bitpos: [2:0]; default: 0;
-         *  Stores RF Calibration data. RXIQ version.
-         */
-        uint32_t rxiq_version:3;
-        /** rxiq_0 : RO; bitpos: [9:3]; default: 0;
-         *  Stores RF Calibration data. RXIQ data 0.
-         */
-        uint32_t rxiq_0:7;
-        /** rxiq_1 : RO; bitpos: [16:10]; default: 0;
-         *  Stores RF Calibration data. RXIQ data 1.
-         */
-        uint32_t rxiq_1:7;
-        /** active_hp_dbias : RO; bitpos: [21:17]; default: 0;
-         *  Stores the PMU active hp dbias.
-         */
-        uint32_t active_hp_dbias:5;
-        /** active_lp_dbias : RO; bitpos: [26:22]; default: 0;
-         *  Stores the PMU active lp dbias.
-         */
-        uint32_t active_lp_dbias:5;
-        /** dslp_dbias : RO; bitpos: [30:27]; default: 0;
-         *  Stores the PMU sleep dbias.
-         */
-        uint32_t dslp_dbias:4;
-        /** dbias_vol_gap_value1 : RO; bitpos: [31]; default: 0;
-         *  Stores the low 1 bit of dbias_vol_gap.
-         */
-        uint32_t dbias_vol_gap_value1:1;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_2_reg_t;
-
-/** Type of rd_mac_sys_3 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** dbias_vol_gap_value2 : RO; bitpos: [2:0]; default: 0;
-         *  Stores the high 3 bits of dbias_vol_gap.
-         */
-        uint32_t dbias_vol_gap_value2:3;
-        /** dbias_vol_gap_sign : RO; bitpos: [3]; default: 0;
-         *  Stores the sign bit of dbias_vol_gap.
-         */
-        uint32_t dbias_vol_gap_sign:1;
-        /** mac_reserved_2 : RO; bitpos: [17:4]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_2:14;
-        /** wafer_version_minor : RO; bitpos: [20:18]; default: 0;
-         *  Stores the wafer version minor.
-         */
-        uint32_t wafer_version_minor:3;
-        /** wafer_version_major : RO; bitpos: [22:21]; default: 0;
-         *  Stores the wafer version major.
-         */
-        uint32_t wafer_version_major:2;
-        /** disable_wafer_version_major : RO; bitpos: [23]; default: 0;
-         *  Disables check of wafer version major.
-         */
-        uint32_t disable_wafer_version_major:1;
-        /** flash_cap : RO; bitpos: [26:24]; default: 0;
-         *  Stores the flash cap.
-         */
-        uint32_t flash_cap:3;
-        /** flash_temp : RO; bitpos: [28:27]; default: 0;
-         *  Stores the flash temp.
-         */
-        uint32_t flash_temp:2;
-        /** flash_vendor : RO; bitpos: [31:29]; default: 0;
-         *  Stores the flash vendor.
-         */
-        uint32_t flash_vendor:3;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_3_reg_t;
-
-/** Type of rd_mac_sys_4 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** pkg_version : R; bitpos: [2:0]; default: 0;
-         *  Package version
-         */
-        uint32_t pkg_version:3;
-        /** reserved_1_131 : R; bitpos: [31:3]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_131:29;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_4_reg_t;
-
-/** Type of rd_mac_sys_5 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_2:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_5_reg_t;
-
-/** Type of rd_sys_part1_data0 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** reserved_2_128 : R; bitpos: [1:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_128:2;
-        /** blk_version_minor : R; bitpos: [4:2]; default: 0;
-         *  BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1
-         */
-        uint32_t blk_version_minor:3;
-        /** blk_version_major : R; bitpos: [6:5]; default: 0;
-         *  BLK_VERSION_MAJOR of BLOCK2
-         */
-        uint32_t blk_version_major:2;
-        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
-         *  Disables check of blk version major
-         */
-        uint32_t disable_blk_version_major:1;
-        /** temp_calib : R; bitpos: [16:8]; default: 0;
-         *  Temperature calibration data
-         */
-        uint32_t temp_calib:9;
-        /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ave_initcode_atten0:10;
-        /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ave_initcode_atten1:5;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ave_initcode_atten1_1:5;
-        /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ave_initcode_atten2:10;
-        /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ave_initcode_atten3:10;
-        /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_hi_dout_atten0:7;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_hi_dout_atten0_1:3;
-        /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_hi_dout_atten1:10;
-        /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_hi_dout_atten2:10;
-        /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_hi_dout_atten3:9;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_hi_dout_atten3_1:1;
-        /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ch0_atten0_initcode_diff:4;
-        /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ch1_atten0_initcode_diff:4;
-        /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ch2_atten0_initcode_diff:4;
-        /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ch3_atten0_initcode_diff:4;
-        /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0;
-         *  ADC1 calibration data
-         */
-        uint32_t adc1_ch4_atten0_initcode_diff:4;
-        /** reserved_2_245 : R; bitpos: [31:21]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_245:11;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-/** Type of rd_usr_data0 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_192:8;
-        /** custom_mac : R; bitpos: [31:8]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac:24;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac_1:24;
-        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_248:8;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-/** Type of rd_key0_data0 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-/** Type of rd_key1_data0 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-/** Type of rd_key2_data0 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-/** Type of rd_key3_data0 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-/** Type of rd_key4_data0 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-/** Type of rd_key5_data0 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-/** Type of rd_sys_part2_data0 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-
-/** Group: Report Register */
-/** Type of rd_repeat_err0 register
- *  Programming error record register 0 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Indicates a programming error of RD_DIS.
-         */
-        uint32_t rd_dis_err:7;
-        /** rpt4_reserved0_err_4 : RO; bitpos: [7]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_err_4:1;
-        /** dis_icache_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of DIS_ICACHE.
-         */
-        uint32_t dis_icache_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Indicates a programming error of DIS_USB_JTAG.
-         */
-        uint32_t dis_usb_jtag_err:1;
-        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
-         *  Indicates a programming error of POWERGLITCH_EN.
-         */
-        uint32_t powerglitch_en_err:1;
-        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
-         *  Indicates a programming error of DIS_USB_DEVICE.
-         */
-        uint32_t dis_usb_serial_jtag_err:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
-         */
-        uint32_t dis_force_download_err:1;
-        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
-         */
-        uint32_t spi_download_mspi_dis_err:1;
-        /** dis_twai_err : RO; bitpos: [14]; default: 0;
-         *  Indicates a programming error of DIS_CAN.
-         */
-        uint32_t dis_twai_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  Indicates a programming error of JTAG_SEL_ENABLE.
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  Indicates a programming error of SOFT_DIS_JTAG.
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of DIS_PAD_JTAG.
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
-         *  Indicates a programming error of USB_DREFH.
-         */
-        uint32_t usb_drefh_err:2;
-        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
-         *  Indicates a programming error of USB_DREFL.
-         */
-        uint32_t usb_drefl_err:2;
-        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of USB_EXCHG_PINS.
-         */
-        uint32_t usb_exchg_pins_err:1;
-        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
-         *  Indicates a programming error of VDD_SPI_AS_GPIO.
-         */
-        uint32_t vdd_spi_as_gpio_err:1;
-        /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_err_2:2;
-        /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_err_1:1;
-        /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved0_err_0:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err0_reg_t;
-
-/** Type of rd_repeat_err1 register
- *  Programming error record register 1 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved1_err_0:16;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of WDT_DELAY_SEL.
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_0.
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_1.
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err1_reg_t;
-
-/** Type of rd_repeat_err2 register
- *  Programming error record register 2 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_2.
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_3.
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_4.
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_5.
-         */
-        uint32_t key_purpose_5_err:4;
-        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of SEC_DPA_LEVEL.
-         */
-        uint32_t sec_dpa_level_err:2;
-        /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved2_err_1:1;
-        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of CRYPT_DPA_ENABLE.
-         */
-        uint32_t crypt_dpa_enable_err:1;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_EN.
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved2_err_0:6;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of FLASH_TPUW.
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err2_reg_t;
-
-/** Type of rd_repeat_err3 register
- *  Programming error record register 3 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Indicates a programming error of DIS_DIRECT_BOOT.
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** usb_print_err : RO; bitpos: [2]; default: 0;
-         *  Indicates a programming error of UART_PRINT_CHANNEL.
-         */
-        uint32_t usb_print_err:1;
-        /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved3_err_5:1;
-        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  Indicates a programming error of UART_PRINT_CONTROL.
-         */
-        uint32_t uart_print_control_err:2;
-        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of FORCE_SEND_RESUME.
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
-         *  Indicates a programming error of SECURE VERSION.
-         */
-        uint32_t secure_version_err:16;
-        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
-         */
-        uint32_t secure_boot_disable_fast_wake_err:1;
-        /** hys_en_pad0_err : RO; bitpos: [31:26]; default: 0;
-         *  Indicates a programming error of HYS_EN_PAD0.
-         */
-        uint32_t hys_en_pad0_err:6;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err3_reg_t;
-
-/** Type of rd_repeat_err4 register
- *  Programming error record register 4 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** hys_en_pad1_err : RO; bitpos: [21:0]; default: 0;
-         *  Indicates a programming error of HYS_EN_PAD1.
-         */
-        uint32_t hys_en_pad1_err:22;
-        /** rpt4_reserved4_err_1 : RO; bitpos: [23:22]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved4_err_1:2;
-        /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved4_err_0:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err4_reg_t;
-
-/** Type of rd_rs_err0 register
- *  Programming error record register 0 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t mac_spi_8m_err_num:3;
-        /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t mac_spi_8m_fail:1;
-        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part1_num:3;
-        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part1_fail:1;
-        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t usr_data_err_num:3;
-        /** usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  0: Means no failure and that the user data is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t usr_data_fail:1;
-        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key0_err_num:3;
-        /** key0_fail : RO; bitpos: [15]; default: 0;
-         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
-         *  key0 failed and the number of error bytes is over 6.
-         */
-        uint32_t key0_fail:1;
-        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key1_err_num:3;
-        /** key1_fail : RO; bitpos: [19]; default: 0;
-         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
-         *  key1 failed and the number of error bytes is over 6.
-         */
-        uint32_t key1_fail:1;
-        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key2_err_num:3;
-        /** key2_fail : RO; bitpos: [23]; default: 0;
-         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
-         *  key2 failed and the number of error bytes is over 6.
-         */
-        uint32_t key2_fail:1;
-        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key3_err_num:3;
-        /** key3_fail : RO; bitpos: [27]; default: 0;
-         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
-         *  key3 failed and the number of error bytes is over 6.
-         */
-        uint32_t key3_fail:1;
-        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key4_err_num:3;
-        /** key4_fail : RO; bitpos: [31]; default: 0;
-         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
-         *  key4 failed and the number of error bytes is over 6.
-         */
-        uint32_t key4_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_err0_reg_t;
-
-/** Type of rd_rs_err1 register
- *  Programming error record register 1 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key5_err_num:3;
-        /** key5_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
-         *  key5 failed and the number of error bytes is over 6.
-         */
-        uint32_t key5_fail:1;
-        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part2_err_num:3;
-        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part2_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_err1_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to force enable eFuse register configuration clock signal.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuraiton register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
-         */
-        uint32_t op_code:16;
-        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
-         *  Configures which block to use for ECDSA key output.
-         */
-        uint32_t cfg_ecdsa_blk:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the read hold time.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures the read time.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures the read setup time.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
-         *  Configures the waiting time of reading eFuse memory.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the programming setup time.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        /** thp_a : R/W; bitpos: [31:24]; default: 1;
-         *  Configures the programming hold time.
-         */
-        uint32_t thp_a:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        /** tpgm : R/W; bitpos: [31:16]; default: 160;
-         *  Configures the active programming time.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-/** Type of wr_tim_conf0_rs_bypass register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-typedef union {
-    struct {
-        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to bypass reed solomon correction step.
-         */
-        uint32_t bypass_rs_correction:1;
-        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
-         *  Configures block number of programming twice operation.
-         */
-        uint32_t bypass_rs_blk_num:11;
-        /** update : WT; bitpos: [12]; default: 0;
-         *  Set this bit to update multi-bit register signals.
-         */
-        uint32_t update:1;
-        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
-         *  Configures the inactive programming time.
-         */
-        uint32_t tpgm_inactive:8;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_rs_bypass_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
-         *  Indicates which block is used for ECDSA key output.
-         */
-        uint32_t cur_ecdsa_blk:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35684640;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
-    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
-    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
-    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
-    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
-    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
-    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
-    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
-    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
-    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
-    uint32_t reserved_190[12];
-    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
-    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
-    volatile efuse_date_reg_t date;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/extmem_reg.h b/components/soc/esp32h2/include/soc/extmem_reg.h
deleted file mode 100644
index b53ab467314..00000000000
--- a/components/soc/esp32h2/include/soc/extmem_reg.h
+++ /dev/null
@@ -1,971 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_CACHE_REG_H_
-#define _SOC_CACHE_REG_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define CACHE_L1_CACHE_CTRL_REG          (DR_REG_CACHE_BASE + 0x4)
-/* CACHE_L1_CACHE_SHUT_BUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable.*/
-#define CACHE_L1_CACHE_SHUT_BUS1    (BIT(1))
-#define CACHE_L1_CACHE_SHUT_BUS1_M  (BIT(1))
-#define CACHE_L1_CACHE_SHUT_BUS1_V  0x1
-#define CACHE_L1_CACHE_SHUT_BUS1_S  1
-/* CACHE_L1_CACHE_SHUT_BUS0 : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
-#define CACHE_L1_CACHE_SHUT_BUS0    (BIT(0))
-#define CACHE_L1_CACHE_SHUT_BUS0_M  (BIT(0))
-#define CACHE_L1_CACHE_SHUT_BUS0_V  0x1
-#define CACHE_L1_CACHE_SHUT_BUS0_S  0
-
-#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_CACHE_BASE + 0x20)
-/* CACHE_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
-#define CACHE_L1_CACHE_WRAP    (BIT(4))
-#define CACHE_L1_CACHE_WRAP_M  (BIT(4))
-#define CACHE_L1_CACHE_WRAP_V  0x1
-#define CACHE_L1_CACHE_WRAP_S  4
-
-#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG          (DR_REG_CACHE_BASE + 0x24)
-/* CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
-/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M  (BIT(18))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V  0x1
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S  18
-/* CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power
-down.*/
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M  (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V  0x1
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S  17
-/* CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating,
-0: open clock gating..*/
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M  (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V  0x1
-#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S  16
-
-#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG          (DR_REG_CACHE_BASE + 0x28)
-/* CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
-/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u
-p.*/
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M  (BIT(18))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V  0x1
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S  18
-/* CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
- down.*/
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M  (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V  0x1
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S  17
-/* CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to close clock gating of  L1-Cache data memory. 1: close gating,
- 0: open clock gating..*/
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M  (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V  0x1
-#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S  16
-
-#define CACHE_L1_CACHE_FREEZE_CTRL_REG          (DR_REG_CACHE_BASE + 0x2C)
-/* CACHE_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */
-/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or
-not. 0: not finished. 1: finished..*/
-#define CACHE_L1_CACHE_FREEZE_DONE    (BIT(18))
-#define CACHE_L1_CACHE_FREEZE_DONE_M  (BIT(18))
-#define CACHE_L1_CACHE_FREEZE_DONE_V  0x1
-#define CACHE_L1_CACHE_FREEZE_DONE_S  18
-/* CACHE_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
- will not stuck. 1: a miss-access will stuck..*/
-#define CACHE_L1_CACHE_FREEZE_MODE    (BIT(17))
-#define CACHE_L1_CACHE_FREEZE_MODE_M  (BIT(17))
-#define CACHE_L1_CACHE_FREEZE_MODE_V  0x1
-#define CACHE_L1_CACHE_FREEZE_MODE_S  17
-/* CACHE_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof
-tware..*/
-#define CACHE_L1_CACHE_FREEZE_EN    (BIT(16))
-#define CACHE_L1_CACHE_FREEZE_EN_M  (BIT(16))
-#define CACHE_L1_CACHE_FREEZE_EN_V  0x1
-#define CACHE_L1_CACHE_FREEZE_EN_S  16
-
-#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG          (DR_REG_CACHE_BASE + 0x30)
-/* CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable,
-1: enable..*/
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M  (BIT(17))
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V  0x1
-#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S  17
-/* CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1
-: enable..*/
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M  (BIT(16))
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V  0x1
-#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S  16
-
-#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG          (DR_REG_CACHE_BASE + 0x34)
-/* CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1
-: enable..*/
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M  (BIT(17))
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V  0x1
-#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S  17
-/* CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
-/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
- enable..*/
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M  (BIT(16))
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V  0x1
-#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S  16
-
-#define CACHE_L1_CACHE_PRELOCK_CONF_REG          (DR_REG_CACHE_BASE + 0x78)
-/* CACHE_L1_CACHE_PRELOCK_RGID : HRO ;bitpos:[5:2] ;default: 4'h0 ; */
-/*description: The bit is used to set  the gid of l1 cache prelock..*/
-#define CACHE_L1_CACHE_PRELOCK_RGID    0x0000000F
-#define CACHE_L1_CACHE_PRELOCK_RGID_M  ((CACHE_L1_CACHE_PRELOCK_RGID_V)<<(CACHE_L1_CACHE_PRELOCK_RGID_S))
-#define CACHE_L1_CACHE_PRELOCK_RGID_V  0xF
-#define CACHE_L1_CACHE_PRELOCK_RGID_S  2
-/* CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M  (BIT(1))
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V  0x1
-#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S  1
-/* CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M  (BIT(0))
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V  0x1
-#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S  0
-
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_CACHE_BASE + 0x7C)
-/* CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the first section
-of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0
-_SIZE_REG.*/
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M  ((CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S))
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_CACHE_BASE + 0x80)
-/* CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the second section
- of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT
-1_SIZE_REG.*/
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M  ((CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S))
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-#define CACHE_L1_CACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_CACHE_BASE + 0x84)
-/* CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */
-/*description: Those bits are used to configure the size of the second section of prelock on L1
--Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFF
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M  ((CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S))
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x3FFF
-#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
-/* CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */
-/*description: Those bits are used to configure the size of the first section of prelock on L1-
-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFF
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M  ((CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S))
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x3FFF
-#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
-
-#define CACHE_LOCK_CTRL_REG          (DR_REG_CACHE_BASE + 0x88)
-/* CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0:
- not finished. 1: finished..*/
-#define CACHE_LOCK_DONE    (BIT(2))
-#define CACHE_LOCK_DONE_M  (BIT(2))
-#define CACHE_LOCK_DONE_V  0x1
-#define CACHE_LOCK_DONE_S  2
-/* CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
- unlock operation done.*/
-#define CACHE_UNLOCK_ENA    (BIT(1))
-#define CACHE_UNLOCK_ENA_M  (BIT(1))
-#define CACHE_UNLOCK_ENA_V  0x1
-#define CACHE_UNLOCK_ENA_S  1
-/* CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
-ock operation done.*/
-#define CACHE_LOCK_ENA    (BIT(0))
-#define CACHE_LOCK_ENA_M  (BIT(0))
-#define CACHE_LOCK_ENA_V  0x1
-#define CACHE_LOCK_ENA_S  0
-
-#define CACHE_LOCK_MAP_REG          (DR_REG_CACHE_BASE + 0x8C)
-/* CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: Those bits are used to indicate which caches in the two-level cache structure wi
-ll apply this lock/unlock operation. [4]: L1-Cache.*/
-#define CACHE_LOCK_MAP    0x0000003F
-#define CACHE_LOCK_MAP_M  ((CACHE_LOCK_MAP_V)<<(CACHE_LOCK_MAP_S))
-#define CACHE_LOCK_MAP_V  0x3F
-#define CACHE_LOCK_MAP_S  0
-
-#define CACHE_LOCK_ADDR_REG          (DR_REG_CACHE_BASE + 0x90)
-/* CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the lock/unlock op
-eration, which should be used together with CACHE_LOCK_SIZE_REG.*/
-#define CACHE_LOCK_ADDR    0xFFFFFFFF
-#define CACHE_LOCK_ADDR_M  ((CACHE_LOCK_ADDR_V)<<(CACHE_LOCK_ADDR_S))
-#define CACHE_LOCK_ADDR_V  0xFFFFFFFF
-#define CACHE_LOCK_ADDR_S  0
-
-#define CACHE_LOCK_SIZE_REG          (DR_REG_CACHE_BASE + 0x94)
-/* CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: Those bits are used to configure the size of the lock/unlock operation, which sh
-ould be used together with CACHE_LOCK_ADDR_REG.*/
-#define CACHE_LOCK_SIZE    0x0000FFFF
-#define CACHE_LOCK_SIZE_M  ((CACHE_LOCK_SIZE_V)<<(CACHE_LOCK_SIZE_S))
-#define CACHE_LOCK_SIZE_V  0xFFFF
-#define CACHE_LOCK_SIZE_S  0
-
-#define CACHE_SYNC_CTRL_REG          (DR_REG_CACHE_BASE + 0x98)
-/* CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback
-, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/
-#define CACHE_SYNC_DONE    (BIT(4))
-#define CACHE_SYNC_DONE_M  (BIT(4))
-#define CACHE_SYNC_DONE_V  0x1
-#define CACHE_SYNC_DONE_S  4
-/* CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
-/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
-hardware after writeback-invalidate operation done. Note that this bit and the o
-ther sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
-, that is, those bits can not be set to 1 at the same time..*/
-#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
-#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
-#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x1
-#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
-/* CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
-ter writeback operation done. Note that this bit and the other sync-bits (invali
-date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
-those bits can not be set to 1 at the same time..*/
-#define CACHE_WRITEBACK_ENA    (BIT(2))
-#define CACHE_WRITEBACK_ENA_M  (BIT(2))
-#define CACHE_WRITEBACK_ENA_V  0x1
-#define CACHE_WRITEBACK_ENA_S  2
-/* CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable clean operation. It will be cleared by hardware after
-clean operation done. Note that this bit and the other sync-bits (invalidate_ena
-, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, thos
-e bits can not be set to 1 at the same time..*/
-#define CACHE_CLEAN_ENA    (BIT(1))
-#define CACHE_CLEAN_ENA_M  (BIT(1))
-#define CACHE_CLEAN_ENA_V  0x1
-#define CACHE_CLEAN_ENA_S  1
-/* CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
-/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
-fter invalidate operation done. Note that this bit and the other sync-bits (clea
-n_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
- those bits can not be set to 1 at the same time..*/
-#define CACHE_INVALIDATE_ENA    (BIT(0))
-#define CACHE_INVALIDATE_ENA_M  (BIT(0))
-#define CACHE_INVALIDATE_ENA_V  0x1
-#define CACHE_INVALIDATE_ENA_S  0
-
-#define CACHE_SYNC_MAP_REG          (DR_REG_CACHE_BASE + 0x9C)
-/* CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
-/*description: Those bits are used to indicate which caches in the two-level cache structure wi
-ll apply the sync operation.  [4]: L1-Cache.*/
-#define CACHE_SYNC_MAP    0x0000003F
-#define CACHE_SYNC_MAP_M  ((CACHE_SYNC_MAP_V)<<(CACHE_SYNC_MAP_S))
-#define CACHE_SYNC_MAP_V  0x3F
-#define CACHE_SYNC_MAP_S  0
-
-#define CACHE_SYNC_ADDR_REG          (DR_REG_CACHE_BASE + 0xA0)
-/* CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the sync operation
-, which should be used together with CACHE_SYNC_SIZE_REG.*/
-#define CACHE_SYNC_ADDR    0xFFFFFFFF
-#define CACHE_SYNC_ADDR_M  ((CACHE_SYNC_ADDR_V)<<(CACHE_SYNC_ADDR_S))
-#define CACHE_SYNC_ADDR_V  0xFFFFFFFF
-#define CACHE_SYNC_ADDR_S  0
-
-#define CACHE_SYNC_SIZE_REG          (DR_REG_CACHE_BASE + 0xA4)
-/* CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Those bits are used to configure the size of the sync operation, which should be
- used together with CACHE_SYNC_ADDR_REG.*/
-#define CACHE_SYNC_SIZE    0x00FFFFFF
-#define CACHE_SYNC_SIZE_M  ((CACHE_SYNC_SIZE_V)<<(CACHE_SYNC_SIZE_S))
-#define CACHE_SYNC_SIZE_V  0xFFFFFF
-#define CACHE_SYNC_SIZE_S  0
-
-#define CACHE_L1_CACHE_PRELOAD_CTRL_REG          (DR_REG_CACHE_BASE + 0xD8)
-/* CACHE_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
-/*description: The bit is used to set  the gid of l1 cache preload..*/
-#define CACHE_L1_CACHE_PRELOAD_RGID    0x0000000F
-#define CACHE_L1_CACHE_PRELOAD_RGID_M  ((CACHE_L1_CACHE_PRELOAD_RGID_V)<<(CACHE_L1_CACHE_PRELOAD_RGID_S))
-#define CACHE_L1_CACHE_PRELOAD_RGID_V  0xF
-#define CACHE_L1_CACHE_PRELOAD_RGID_S  3
-/* CACHE_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1
-: descending..*/
-#define CACHE_L1_CACHE_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_CACHE_PRELOAD_ORDER_M  (BIT(2))
-#define CACHE_L1_CACHE_PRELOAD_ORDER_V  0x1
-#define CACHE_L1_CACHE_PRELOAD_ORDER_S  2
-/* CACHE_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether preload operation is finished or not. 0: not
- finished. 1: finished..*/
-#define CACHE_L1_CACHE_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_CACHE_PRELOAD_DONE_M  (BIT(1))
-#define CACHE_L1_CACHE_PRELOAD_DONE_V  0x1
-#define CACHE_L1_CACHE_PRELOAD_DONE_S  1
-/* CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h
-ardware automatically after preload operation is done..*/
-#define CACHE_L1_CACHE_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_CACHE_PRELOAD_ENA_M  (BIT(0))
-#define CACHE_L1_CACHE_PRELOAD_ENA_V  0x1
-#define CACHE_L1_CACHE_PRELOAD_ENA_S  0
-
-#define CACHE_L1_CACHE_PRELOAD_ADDR_REG          (DR_REG_CACHE_BASE + 0xDC)
-/* CACHE_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of preload on L1-Cach
-e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/
-#define CACHE_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_PRELOAD_ADDR_M  ((CACHE_L1_CACHE_PRELOAD_ADDR_V)<<(CACHE_L1_CACHE_PRELOAD_ADDR_S))
-#define CACHE_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_PRELOAD_ADDR_S  0
-
-#define CACHE_L1_CACHE_PRELOAD_SIZE_REG          (DR_REG_CACHE_BASE + 0xE0)
-/* CACHE_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: Those bits are used to configure the size of the first section of prelock on L1-
-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/
-#define CACHE_L1_CACHE_PRELOAD_SIZE    0x00003FFF
-#define CACHE_L1_CACHE_PRELOAD_SIZE_M  ((CACHE_L1_CACHE_PRELOAD_SIZE_V)<<(CACHE_L1_CACHE_PRELOAD_SIZE_S))
-#define CACHE_L1_CACHE_PRELOAD_SIZE_V  0x3FFF
-#define CACHE_L1_CACHE_PRELOAD_SIZE_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG          (DR_REG_CACHE_BASE + 0x134)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (BIT(9))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x1
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
-/* CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (BIT(8))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x1
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/* CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0
-/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  ((CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S))
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x3
-#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/* CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0:
- ascending. 1: descending..*/
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M  (BIT(2))
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V  0x1
-#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S  2
-/* CACHE_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
-/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o
-r not. 0: not finished. 1: finished..*/
-#define CACHE_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_M  (BIT(1))
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_V  0x1
-#define CACHE_L1_CACHE_AUTOLOAD_DONE_S  1
-/* CACHE_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable and disable autoload operation on L1-Cache.  1: enable
-, 0: disable..*/
-#define CACHE_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_M  (BIT(0))
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_V  0x1
-#define CACHE_L1_CACHE_AUTOLOAD_ENA_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_CACHE_BASE + 0x138)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the first section
-for autoload operation on L1-Cache. Note that it should be used together with L1
-_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_CACHE_BASE + 0x13C)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Those bits are used to configure the size of the first section for autoload oper
-ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
-CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x00FFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_CACHE_BASE + 0x140)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the second section
- for autoload operation on L1-Cache. Note that it should be used together with L
-1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_CACHE_BASE + 0x144)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Those bits are used to configure the size of the second section for autoload ope
-ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
-SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x00FFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG          (DR_REG_CACHE_BASE + 0x148)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the third section
-for autoload operation on L1-Cache. Note that it should be used together with L1
-_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG          (DR_REG_CACHE_BASE + 0x14C)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Those bits are used to configure the size of the third section for autoload oper
-ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
-CT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE    0x00FFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V  0xFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG          (DR_REG_CACHE_BASE + 0x150)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are used to configure the start virtual address of the fourth section
- for autoload operation on L1-Cache. Note that it should be used together with L
-1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S  0
-
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG          (DR_REG_CACHE_BASE + 0x154)
-/* CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Those bits are used to configure the size of the fourth section for autoload ope
-ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
-SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA..*/
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE    0x00FFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S))
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V  0xFFFFFF
-#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S  0
-
-#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG          (DR_REG_CACHE_BASE + 0x158)
-/* CACHE_L1_BUS1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
-1-DCache due to bus1 accesses L1-DCache..*/
-#define CACHE_L1_BUS1_OVF_INT_ENA    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ENA_M  (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ENA_V  0x1
-#define CACHE_L1_BUS1_OVF_INT_ENA_S  5
-/* CACHE_L1_BUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
-1-DCache due to bus0 accesses L1-DCache..*/
-#define CACHE_L1_BUS0_OVF_INT_ENA    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ENA_M  (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ENA_V  0x1
-#define CACHE_L1_BUS0_OVF_INT_ENA_S  4
-
-#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_CACHE_BASE + 0x15C)
-/* CACHE_L1_BUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus1 accesses L1-DCache..*/
-#define CACHE_L1_BUS1_OVF_INT_CLR    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_CLR_M  (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_CLR_V  0x1
-#define CACHE_L1_BUS1_OVF_INT_CLR_S  5
-/* CACHE_L1_BUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache d
-ue to bus0 accesses L1-DCache..*/
-#define CACHE_L1_BUS0_OVF_INT_CLR    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_CLR_M  (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_CLR_V  0x1
-#define CACHE_L1_BUS0_OVF_INT_CLR_S  4
-
-#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG          (DR_REG_CACHE_BASE + 0x160)
-/* CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
-e due to bus1 accesses L1-DCache..*/
-#define CACHE_L1_BUS1_OVF_INT_RAW    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_RAW_M  (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_RAW_V  0x1
-#define CACHE_L1_BUS1_OVF_INT_RAW_S  5
-/* CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
-e due to bus0 accesses L1-DCache..*/
-#define CACHE_L1_BUS0_OVF_INT_RAW    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_RAW_M  (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_RAW_V  0x1
-#define CACHE_L1_BUS0_OVF_INT_RAW_S  4
-
-#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG          (DR_REG_CACHE_BASE + 0x164)
-/* CACHE_L1_BUS1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
-n L1-DCache due to bus1 accesses L1-DCache..*/
-#define CACHE_L1_BUS1_OVF_INT_ST    (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ST_M  (BIT(5))
-#define CACHE_L1_BUS1_OVF_INT_ST_V  0x1
-#define CACHE_L1_BUS1_OVF_INT_ST_S  5
-/* CACHE_L1_BUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
-n L1-DCache due to bus0 accesses L1-DCache..*/
-#define CACHE_L1_BUS0_OVF_INT_ST    (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ST_M  (BIT(4))
-#define CACHE_L1_BUS0_OVF_INT_ST_V  0x1
-#define CACHE_L1_BUS0_OVF_INT_ST_S  4
-
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG          (DR_REG_CACHE_BASE + 0x168)
-/* CACHE_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due
-to cpu accesses L1-DCache..*/
-#define CACHE_L1_CACHE_FAIL_INT_ENA    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ENA_M  (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ENA_V  0x1
-#define CACHE_L1_CACHE_FAIL_INT_ENA_S  4
-
-#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG          (DR_REG_CACHE_BASE + 0x16C)
-/* CACHE_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t
-o cpu accesses L1-DCache..*/
-#define CACHE_L1_CACHE_FAIL_INT_CLR    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_CLR_M  (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_CLR_V  0x1
-#define CACHE_L1_CACHE_FAIL_INT_CLR_S  4
-
-#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG          (DR_REG_CACHE_BASE + 0x170)
-/* CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/
-#define CACHE_L1_CACHE_FAIL_INT_RAW    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_RAW_M  (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_RAW_V  0x1
-#define CACHE_L1_CACHE_FAIL_INT_RAW_S  4
-
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_CACHE_BASE + 0x174)
-/* CACHE_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache d
-ue to cpu accesses L1-DCache..*/
-#define CACHE_L1_CACHE_FAIL_INT_ST    (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
-#define CACHE_L1_CACHE_FAIL_INT_ST_V  0x1
-#define CACHE_L1_CACHE_FAIL_INT_ST_S  4
-
-#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG          (DR_REG_CACHE_BASE + 0x178)
-/* CACHE_L1_BUS1_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */
-/*description: The bit is used to clear dbus1 counter in L1-DCache..*/
-#define CACHE_L1_BUS1_CNT_CLR    (BIT(21))
-#define CACHE_L1_BUS1_CNT_CLR_M  (BIT(21))
-#define CACHE_L1_BUS1_CNT_CLR_V  0x1
-#define CACHE_L1_BUS1_CNT_CLR_S  21
-/* CACHE_L1_BUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
-#define CACHE_L1_BUS0_CNT_CLR    (BIT(20))
-#define CACHE_L1_BUS0_CNT_CLR_M  (BIT(20))
-#define CACHE_L1_BUS0_CNT_CLR_V  0x1
-#define CACHE_L1_BUS0_CNT_CLR_S  20
-/* CACHE_L1_BUS1_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable dbus1 counter in L1-DCache..*/
-#define CACHE_L1_BUS1_CNT_ENA    (BIT(5))
-#define CACHE_L1_BUS1_CNT_ENA_M  (BIT(5))
-#define CACHE_L1_BUS1_CNT_ENA_V  0x1
-#define CACHE_L1_BUS1_CNT_ENA_S  5
-/* CACHE_L1_BUS0_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable dbus0 counter in L1-DCache..*/
-#define CACHE_L1_BUS0_CNT_ENA    (BIT(4))
-#define CACHE_L1_BUS0_CNT_ENA_M  (BIT(4))
-#define CACHE_L1_BUS0_CNT_ENA_V  0x1
-#define CACHE_L1_BUS0_CNT_ENA_S  4
-
-#define CACHE_L1_BUS0_ACS_HIT_CNT_REG          (DR_REG_CACHE_BASE + 0x1BC)
-/* CACHE_L1_BUS0_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of hits when bus0 accesses L1-Cache..*/
-#define CACHE_L1_BUS0_HIT_CNT    0xFFFFFFFF
-#define CACHE_L1_BUS0_HIT_CNT_M  ((CACHE_L1_BUS0_HIT_CNT_V)<<(CACHE_L1_BUS0_HIT_CNT_S))
-#define CACHE_L1_BUS0_HIT_CNT_V  0xFFFFFFFF
-#define CACHE_L1_BUS0_HIT_CNT_S  0
-
-#define CACHE_L1_BUS0_ACS_MISS_CNT_REG          (DR_REG_CACHE_BASE + 0x1C0)
-/* CACHE_L1_BUS0_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of missing when bus0 accesses L1-Cache..*/
-#define CACHE_L1_BUS0_MISS_CNT    0xFFFFFFFF
-#define CACHE_L1_BUS0_MISS_CNT_M  ((CACHE_L1_BUS0_MISS_CNT_V)<<(CACHE_L1_BUS0_MISS_CNT_S))
-#define CACHE_L1_BUS0_MISS_CNT_V  0xFFFFFFFF
-#define CACHE_L1_BUS0_MISS_CNT_S  0
-
-#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG          (DR_REG_CACHE_BASE + 0x1C4)
-/* CACHE_L1_BUS0_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/
-#define CACHE_L1_BUS0_CONFLICT_CNT    0xFFFFFFFF
-#define CACHE_L1_BUS0_CONFLICT_CNT_M  ((CACHE_L1_BUS0_CONFLICT_CNT_V)<<(CACHE_L1_BUS0_CONFLICT_CNT_S))
-#define CACHE_L1_BUS0_CONFLICT_CNT_V  0xFFFFFFFF
-#define CACHE_L1_BUS0_CONFLICT_CNT_S  0
-
-#define CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG          (DR_REG_CACHE_BASE + 0x1C8)
-/* CACHE_L1_BUS0_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
-bus0 accessing L1-Cache..*/
-#define CACHE_L1_BUS0_NXTLVL_CNT    0xFFFFFFFF
-#define CACHE_L1_BUS0_NXTLVL_CNT_M  ((CACHE_L1_BUS0_NXTLVL_CNT_V)<<(CACHE_L1_BUS0_NXTLVL_CNT_S))
-#define CACHE_L1_BUS0_NXTLVL_CNT_V  0xFFFFFFFF
-#define CACHE_L1_BUS0_NXTLVL_CNT_S  0
-
-#define CACHE_L1_BUS1_ACS_HIT_CNT_REG          (DR_REG_CACHE_BASE + 0x1CC)
-/* CACHE_L1_BUS1_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of hits when bus1 accesses L1-Cache..*/
-#define CACHE_L1_BUS1_HIT_CNT    0xFFFFFFFF
-#define CACHE_L1_BUS1_HIT_CNT_M  ((CACHE_L1_BUS1_HIT_CNT_V)<<(CACHE_L1_BUS1_HIT_CNT_S))
-#define CACHE_L1_BUS1_HIT_CNT_V  0xFFFFFFFF
-#define CACHE_L1_BUS1_HIT_CNT_S  0
-
-#define CACHE_L1_BUS1_ACS_MISS_CNT_REG          (DR_REG_CACHE_BASE + 0x1D0)
-/* CACHE_L1_BUS1_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of missing when bus1 accesses L1-Cache..*/
-#define CACHE_L1_BUS1_MISS_CNT    0xFFFFFFFF
-#define CACHE_L1_BUS1_MISS_CNT_M  ((CACHE_L1_BUS1_MISS_CNT_V)<<(CACHE_L1_BUS1_MISS_CNT_S))
-#define CACHE_L1_BUS1_MISS_CNT_V  0xFFFFFFFF
-#define CACHE_L1_BUS1_MISS_CNT_S  0
-
-#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG          (DR_REG_CACHE_BASE + 0x1D4)
-/* CACHE_L1_BUS1_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/
-#define CACHE_L1_BUS1_CONFLICT_CNT    0xFFFFFFFF
-#define CACHE_L1_BUS1_CONFLICT_CNT_M  ((CACHE_L1_BUS1_CONFLICT_CNT_V)<<(CACHE_L1_BUS1_CONFLICT_CNT_S))
-#define CACHE_L1_BUS1_CONFLICT_CNT_V  0xFFFFFFFF
-#define CACHE_L1_BUS1_CONFLICT_CNT_S  0
-
-#define CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG          (DR_REG_CACHE_BASE + 0x1D8)
-/* CACHE_L1_BUS1_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
-bus1 accessing L1-Cache..*/
-#define CACHE_L1_BUS1_NXTLVL_CNT    0xFFFFFFFF
-#define CACHE_L1_BUS1_NXTLVL_CNT_M  ((CACHE_L1_BUS1_NXTLVL_CNT_V)<<(CACHE_L1_BUS1_NXTLVL_CNT_S))
-#define CACHE_L1_BUS1_NXTLVL_CNT_V  0xFFFFFFFF
-#define CACHE_L1_BUS1_NXTLVL_CNT_S  0
-
-#define CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG          (DR_REG_CACHE_BASE + 0x21C)
-/* CACHE_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: The register records the attribution of fail-access when cache accesses L1-Cache
-..*/
-#define CACHE_L1_CACHE_FAIL_ATTR    0x0000FFFF
-#define CACHE_L1_CACHE_FAIL_ATTR_M  ((CACHE_L1_CACHE_FAIL_ATTR_V)<<(CACHE_L1_CACHE_FAIL_ATTR_S))
-#define CACHE_L1_CACHE_FAIL_ATTR_V  0xFFFF
-#define CACHE_L1_CACHE_FAIL_ATTR_S  16
-/* CACHE_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/
-#define CACHE_L1_CACHE_FAIL_ID    0x0000FFFF
-#define CACHE_L1_CACHE_FAIL_ID_M  ((CACHE_L1_CACHE_FAIL_ID_V)<<(CACHE_L1_CACHE_FAIL_ID_S))
-#define CACHE_L1_CACHE_FAIL_ID_V  0xFFFF
-#define CACHE_L1_CACHE_FAIL_ID_S  0
-
-#define CACHE_L1_CACHE_ACS_FAIL_ADDR_REG          (DR_REG_CACHE_BASE + 0x220)
-/* CACHE_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The register records the address of fail-access when cache accesses L1-Cache..*/
-#define CACHE_L1_CACHE_FAIL_ADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_FAIL_ADDR_M  ((CACHE_L1_CACHE_FAIL_ADDR_V)<<(CACHE_L1_CACHE_FAIL_ADDR_S))
-#define CACHE_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_FAIL_ADDR_S  0
-
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG          (DR_REG_CACHE_BASE + 0x224)
-/* CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of Cache sync-operation error..*/
-#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ENA_M  (BIT(13))
-#define CACHE_SYNC_ERR_INT_ENA_V  0x1
-#define CACHE_SYNC_ERR_INT_ENA_S  13
-/* CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M  (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V  0x1
-#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S  11
-/* CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of Cache sync-operation done..*/
-#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ENA_M  (BIT(6))
-#define CACHE_SYNC_DONE_INT_ENA_V  0x1
-#define CACHE_SYNC_DONE_INT_ENA_S  6
-/* CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op
-eration is done, interrupt occurs..*/
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M  (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V  0x1
-#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S  4
-
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG          (DR_REG_CACHE_BASE + 0x228)
-/* CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of Cache sync-operation error..*/
-#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
-#define CACHE_SYNC_ERR_INT_CLR_M  (BIT(13))
-#define CACHE_SYNC_ERR_INT_CLR_V  0x1
-#define CACHE_SYNC_ERR_INT_CLR_S  13
-/* CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M  (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V  0x1
-#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S  11
-/* CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is
- done..*/
-#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
-#define CACHE_SYNC_DONE_INT_CLR_M  (BIT(6))
-#define CACHE_SYNC_DONE_INT_CLR_V  0x1
-#define CACHE_SYNC_DONE_INT_CLR_S  6
-/* CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat
-ion is done..*/
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M  (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V  0x1
-#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S  4
-
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG          (DR_REG_CACHE_BASE + 0x22C)
-/* CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc
-curs..*/
-#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
-#define CACHE_SYNC_ERR_INT_RAW_M  (BIT(13))
-#define CACHE_SYNC_ERR_INT_RAW_V  0x1
-#define CACHE_SYNC_ERR_INT_RAW_S  13
-/* CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er
-ror occurs..*/
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M  (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V  0x1
-#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S  11
-/* CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/
-#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
-#define CACHE_SYNC_DONE_INT_RAW_M  (BIT(6))
-#define CACHE_SYNC_DONE_INT_RAW_V  0x1
-#define CACHE_SYNC_DONE_INT_RAW_S  6
-/* CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
- done..*/
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M  (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V  0x1
-#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S  4
-
-#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG          (DR_REG_CACHE_BASE + 0x230)
-/* CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/
-#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ST_M  (BIT(13))
-#define CACHE_SYNC_ERR_INT_ST_V  0x1
-#define CACHE_SYNC_ERR_INT_ST_S  13
-/* CACHE_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation erro
-r..*/
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V  0x1
-#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S  11
-/* CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o
-peration is done..*/
-#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ST_M  (BIT(6))
-#define CACHE_SYNC_DONE_INT_ST_V  0x1
-#define CACHE_SYNC_DONE_INT_ST_S  6
-/* CACHE_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre
-load-operation is done..*/
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M  (BIT(4))
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V  0x1
-#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S  4
-
-#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG          (DR_REG_CACHE_BASE + 0x234)
-/* CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: The values 0-2 are available which means sync map, command conflict and size are
- error in Cache System..*/
-#define CACHE_SYNC_ERR_CODE    0x00000003
-#define CACHE_SYNC_ERR_CODE_M  ((CACHE_SYNC_ERR_CODE_V)<<(CACHE_SYNC_ERR_CODE_S))
-#define CACHE_SYNC_ERR_CODE_V  0x3
-#define CACHE_SYNC_ERR_CODE_S  12
-/* CACHE_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/
-#define CACHE_L1_CACHE_PLD_ERR_CODE    0x00000003
-#define CACHE_L1_CACHE_PLD_ERR_CODE_M  ((CACHE_L1_CACHE_PLD_ERR_CODE_V)<<(CACHE_L1_CACHE_PLD_ERR_CODE_S))
-#define CACHE_L1_CACHE_PLD_ERR_CODE_V  0x3
-#define CACHE_L1_CACHE_PLD_ERR_CODE_S  8
-
-#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_CACHE_BASE + 0x238)
-/* CACHE_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should onl
-y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
-#define CACHE_L1_CACHE_SYNC_RST    (BIT(4))
-#define CACHE_L1_CACHE_SYNC_RST_M  (BIT(4))
-#define CACHE_L1_CACHE_SYNC_RST_V  0x1
-#define CACHE_L1_CACHE_SYNC_RST_S  4
-
-#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG          (DR_REG_CACHE_BASE + 0x23C)
-/* CACHE_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-only be used to initialize preload-logic when some fatal error of preload-logic
-occurs..*/
-#define CACHE_L1_CACHE_PLD_RST    (BIT(4))
-#define CACHE_L1_CACHE_PLD_RST_M  (BIT(4))
-#define CACHE_L1_CACHE_PLD_RST_V  0x1
-#define CACHE_L1_CACHE_PLD_RST_S  4
-
-#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG          (DR_REG_CACHE_BASE + 0x240)
-/* CACHE_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au
-toload will not work in L1-Cache. This bit should not be active when autoload wo
-rks in L1-Cache..*/
-#define CACHE_L1_CACHE_ALD_BUF_CLR    (BIT(4))
-#define CACHE_L1_CACHE_ALD_BUF_CLR_M  (BIT(4))
-#define CACHE_L1_CACHE_ALD_BUF_CLR_V  0x1
-#define CACHE_L1_CACHE_ALD_BUF_CLR_S  4
-
-#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_CACHE_BASE + 0x244)
-/* CACHE_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
-llocate request is responsed but not completed..*/
-#define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
-#define CACHE_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
-#define CACHE_L1_CACHE_UNALLOC_CLR_V  0x1
-#define CACHE_L1_CACHE_UNALLOC_CLR_S  4
-
-#define CACHE_L1_CACHE_OBJECT_CTRL_REG          (DR_REG_CACHE_BASE + 0x248)
-/* CACHE_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi
-th the others fields inside this register..*/
-#define CACHE_L1_CACHE_MEM_OBJECT    (BIT(10))
-#define CACHE_L1_CACHE_MEM_OBJECT_M  (BIT(10))
-#define CACHE_L1_CACHE_MEM_OBJECT_V  0x1
-#define CACHE_L1_CACHE_MEM_OBJECT_S  10
-/* CACHE_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot wit
-h the others fields inside this register..*/
-#define CACHE_L1_CACHE_TAG_OBJECT    (BIT(4))
-#define CACHE_L1_CACHE_TAG_OBJECT_M  (BIT(4))
-#define CACHE_L1_CACHE_TAG_OBJECT_V  0x1
-#define CACHE_L1_CACHE_TAG_OBJECT_S  4
-
-#define CACHE_L1_CACHE_WAY_OBJECT_REG          (DR_REG_CACHE_BASE + 0x24C)
-/* CACHE_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
-: way1, 2: way2, 3: way3, ?, 7: way7..*/
-#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007
-#define CACHE_L1_CACHE_WAY_OBJECT_M  ((CACHE_L1_CACHE_WAY_OBJECT_V)<<(CACHE_L1_CACHE_WAY_OBJECT_S))
-#define CACHE_L1_CACHE_WAY_OBJECT_V  0x7
-#define CACHE_L1_CACHE_WAY_OBJECT_S  0
-
-#define CACHE_L1_CACHE_VADDR_REG          (DR_REG_CACHE_BASE + 0x250)
-/* CACHE_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
-/*description: Those bits stores the virtual address which will decide where inside the specifi
-ed tag memory object will be accessed..*/
-#define CACHE_L1_CACHE_VADDR    0xFFFFFFFF
-#define CACHE_L1_CACHE_VADDR_M  ((CACHE_L1_CACHE_VADDR_V)<<(CACHE_L1_CACHE_VADDR_S))
-#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_VADDR_S  0
-
-#define CACHE_L1_CACHE_DEBUG_BUS_REG          (DR_REG_CACHE_BASE + 0x254)
-/* CACHE_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */
-/*description: This is a constant place where we can write data to or read data from the tag/da
-ta memory on the specified cache..*/
-#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFF
-#define CACHE_L1_CACHE_DEBUG_BUS_M  ((CACHE_L1_CACHE_DEBUG_BUS_V)<<(CACHE_L1_CACHE_DEBUG_BUS_S))
-#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFF
-#define CACHE_L1_CACHE_DEBUG_BUS_S  0
-
-#define CACHE_CLOCK_GATE_REG          (DR_REG_CACHE_BASE + 0x3AC)
-/* CACHE_CLK_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: The bit is used to enable clock gate when access all registers in this module..*/
-#define CACHE_CLK_EN    (BIT(0))
-#define CACHE_CLK_EN_M  (BIT(0))
-#define CACHE_CLK_EN_V  0x1
-#define CACHE_CLK_EN_S  0
-
-#define CACHE_REDUNDANCY_SIG0_REG          (DR_REG_CACHE_BASE + 0x3B0)
-/* CACHE_REDCY_SIG0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are prepared for ECO..*/
-#define CACHE_REDCY_SIG0    0xFFFFFFFF
-#define CACHE_REDCY_SIG0_M  ((CACHE_REDCY_SIG0_V)<<(CACHE_REDCY_SIG0_S))
-#define CACHE_REDCY_SIG0_V  0xFFFFFFFF
-#define CACHE_REDCY_SIG0_S  0
-
-#define CACHE_REDUNDANCY_SIG1_REG          (DR_REG_CACHE_BASE + 0x3B4)
-/* CACHE_REDCY_SIG1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are prepared for ECO..*/
-#define CACHE_REDCY_SIG1    0xFFFFFFFF
-#define CACHE_REDCY_SIG1_M  ((CACHE_REDCY_SIG1_V)<<(CACHE_REDCY_SIG1_S))
-#define CACHE_REDCY_SIG1_V  0xFFFFFFFF
-#define CACHE_REDCY_SIG1_S  0
-
-#define CACHE_REDUNDANCY_SIG2_REG          (DR_REG_CACHE_BASE + 0x3B8)
-/* CACHE_REDCY_SIG2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are prepared for ECO..*/
-#define CACHE_REDCY_SIG2    0xFFFFFFFF
-#define CACHE_REDCY_SIG2_M  ((CACHE_REDCY_SIG2_V)<<(CACHE_REDCY_SIG2_S))
-#define CACHE_REDCY_SIG2_V  0xFFFFFFFF
-#define CACHE_REDCY_SIG2_S  0
-
-#define CACHE_REDUNDANCY_SIG3_REG          (DR_REG_CACHE_BASE + 0x3BC)
-/* CACHE_REDCY_SIG3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Those bits are prepared for ECO..*/
-#define CACHE_REDCY_SIG3    0xFFFFFFFF
-#define CACHE_REDCY_SIG3_M  ((CACHE_REDCY_SIG3_V)<<(CACHE_REDCY_SIG3_S))
-#define CACHE_REDCY_SIG3_V  0xFFFFFFFF
-#define CACHE_REDCY_SIG3_S  0
-
-#define CACHE_REDUNDANCY_SIG4_REG          (DR_REG_CACHE_BASE + 0x3C0)
-/* CACHE_REDCY_SIG4 : RO ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: Those bits are prepared for ECO..*/
-#define CACHE_REDCY_SIG4    0x0000000F
-#define CACHE_REDCY_SIG4_M  ((CACHE_REDCY_SIG4_V)<<(CACHE_REDCY_SIG4_S))
-#define CACHE_REDCY_SIG4_V  0xF
-#define CACHE_REDCY_SIG4_S  0
-
-#define CACHE_DATE_REG          (DR_REG_CACHE_BASE + 0x3FC)
-/* CACHE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2207250 ; */
-/*description: version control register. Note that this default value stored is the latest date
- when the hardware logic was updated..*/
-#define CACHE_DATE    0x0FFFFFFF
-#define CACHE_DATE_M  ((CACHE_DATE_V)<<(CACHE_DATE_S))
-#define CACHE_DATE_V  0xFFFFFFF
-#define CACHE_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_CACHE_REG_H_ */
diff --git a/components/soc/esp32h2/include/soc/extmem_struct.h b/components/soc/esp32h2/include/soc/extmem_struct.h
deleted file mode 100644
index d309e09235e..00000000000
--- a/components/soc/esp32h2/include/soc/extmem_struct.h
+++ /dev/null
@@ -1,5747 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Control and configuration registers */
-/** Type of l1_icache_ctrl register
- *  L1 instruction Cache(L1-ICache) control register
- */
-typedef union {
-    struct {
-        /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus0:1;
-        /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
-         */
-        uint32_t l1_icache_shut_ibus1:1;
-        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus2:1;
-        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_shut_ibus3:1;
-        /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache_undef_op:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_icache_ctrl_reg_t;
-
-/** Type of l1_cache_ctrl register
- *  L1 data Cache(L1-Cache) control register
- */
-typedef union {
-    struct {
-        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus0:1;
-        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_bus1:1;
-        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus2:1;
-        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_shut_dbus3:1;
-        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
-         */
-        uint32_t l1_cache_shut_dma:1;
-        uint32_t reserved_5:3;
-        /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_cache_undef_op:4;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l1_cache_ctrl_reg_t;
-
-/** Type of l2_cache_ctrl register
- *  L2 Cache(L2-Cache) control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
-         */
-        uint32_t l2_cache_shut_dma:1;
-        /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_cache_undef_op:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} extmem_l2_cache_ctrl_reg_t;
-
-
-/** Group: Bypass Cache Control and configuration registers */
-/** Type of l1_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache0_en:1;
-        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_icache1_en:1;
-        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache2_en:1;
-        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t bypass_l1_icache3_en:1;
-        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l1_dcache_en:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_bypass_cache_conf_reg_t;
-
-/** Type of l2_bypass_cache_conf register
- *  Bypass Cache configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
-         */
-        uint32_t bypass_l2_cache_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_bypass_cache_conf_reg_t;
-
-
-/** Group: Cache Atomic Control and configuration registers */
-/** Type of l1_cache_atomic_conf register
- *  L1 Cache atomic feature configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
-         *  L1-Cache.  1: disable, 1: enable.
-         */
-        uint32_t l1_cache_atomic_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} extmem_l1_cache_atomic_conf_reg_t;
-
-
-/** Group: Cache Mode Control and configuration registers */
-/** Type of l1_icache_cachesize_conf register
- *  L1 instruction Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1k:1;
-        /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2k:1;
-        /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4k:1;
-        /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_8k:1;
-        /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_16k:1;
-        /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_32k:1;
-        /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_64k:1;
-        /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_128k:1;
-        /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_256k:1;
-        /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_512k:1;
-        /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_1024k:1;
-        /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_2048k:1;
-        /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
-         *  and all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l1_icache_cachesize_conf_reg_t;
-
-/** Type of l1_icache_blocksize_conf register
- *  L1 instruction Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_8:1;
-        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_16:1;
-        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_32:1;
-        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_64:1;
-        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_128:1;
-        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_icache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache_blocksize_conf_reg_t;
-
-/** Type of l1_cache_cachesize_conf register
- *  L1 data Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1k:1;
-        /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2k:1;
-        /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4k:1;
-        /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_8k:1;
-        /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_16k:1;
-        /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1;
-         *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_32k:1;
-        /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_64k:1;
-        /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_128k:1;
-        /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_256k:1;
-        /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_512k:1;
-        /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_1024k:1;
-        /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_2048k:1;
-        /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l1_cache_cachesize_conf_reg_t;
-
-/** Type of l1_cache_blocksize_conf register
- *  L1 data Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_8:1;
-        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_16:1;
-        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
-         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_32:1;
-        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_64:1;
-        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_128:1;
-        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l1_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_cache_blocksize_conf_reg_t;
-
-/** Type of l2_cache_cachesize_conf register
- *  L2 Cache CacheSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1k:1;
-        /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2k:1;
-        /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4k:1;
-        /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_8k:1;
-        /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_16k:1;
-        /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_32k:1;
-        /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_64k:1;
-        /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_128k:1;
-        /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_256k:1;
-        /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_512k:1;
-        /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_1024k:1;
-        /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_2048k:1;
-        /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
-         *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_cachesize_4096k:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_cachesize_conf_reg_t;
-
-/** Type of l2_cache_blocksize_conf register
- *  L2 Cache BlockSize mode configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_8:1;
-        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_16:1;
-        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_32:1;
-        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
-         *  other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_64:1;
-        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_128:1;
-        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
-         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
-         *  all other fields within this register is onehot.
-         */
-        uint32_t l2_cache_blocksize_256:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_blocksize_conf_reg_t;
-
-
-/** Group: Wrap Mode Control and configuration registers */
-/** Type of l1_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
-         */
-        uint32_t l1_icache0_wrap:1;
-        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
-         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
-         */
-        uint32_t l1_icache1_wrap:1;
-        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_wrap:1;
-        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_wrap:1;
-        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
-         *  Set this bit as 1 to enable L1-DCache wrap around mode.
-         */
-        uint32_t l1_cache_wrap:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_wrap_around_ctrl_reg_t;
-
-/** Type of l2_cache_wrap_around_ctrl register
- *  Cache wrap around control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
-         *  Set this bit as 1 to enable L2-Cache wrap around mode.
-         */
-        uint32_t l2_cache_wrap:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_wrap_around_ctrl_reg_t;
-
-
-/** Group: Cache Tag Memory Power Control registers */
-/** Type of l1_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache0_tag_mem_force_on:1;
-        /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache0_tag_mem_force_pd:1;
-        /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1;
-         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache0_tag_mem_force_pu:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache1_tag_mem_force_on:1;
-        /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache1_tag_mem_force_pd:1;
-        /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1;
-         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache1_tag_mem_force_pu:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_on:1;
-        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_pd:1;
-        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_force_pu:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_on:1;
-        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_pd:1;
-        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_force_pu:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_tag_mem_force_on:1;
-        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l1_cache_tag_mem_force_pd:1;
-        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_tag_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_tag_mem_power_ctrl_reg_t;
-
-/** Type of l2_cache_tag_mem_power_ctrl register
- *  Cache tag memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l2_cache_tag_mem_force_on:1;
-        /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
-         */
-        uint32_t l2_cache_tag_mem_force_pd:1;
-        /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0;
-         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l2_cache_tag_mem_force_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_tag_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Power Control registers */
-/** Type of l1_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache0_data_mem_force_on:1;
-        /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache0_data_mem_force_pd:1;
-        /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1;
-         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache0_data_mem_force_pu:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
-         *  0: open clock gating.
-         */
-        uint32_t l1_icache1_data_mem_force_on:1;
-        /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_icache1_data_mem_force_pd:1;
-        /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1;
-         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_icache1_data_mem_force_pu:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_on:1;
-        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_pd:1;
-        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_force_pu:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_on:1;
-        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_pd:1;
-        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_force_pu:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l1_cache_data_mem_force_on:1;
-        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l1_cache_data_mem_force_pd:1;
-        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l1_cache_data_mem_force_pu:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_data_mem_power_ctrl_reg_t;
-
-/** Type of l2_cache_data_mem_power_ctrl register
- *  Cache data memory power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
-         *  open clock gating.
-         */
-        uint32_t l2_cache_data_mem_force_on:1;
-        /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
-         *  down
-         */
-        uint32_t l2_cache_data_mem_force_pd:1;
-        /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0;
-         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
-         */
-        uint32_t l2_cache_data_mem_force_pu:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_data_mem_power_ctrl_reg_t;
-
-
-/** Group: Cache Freeze Control registers */
-/** Type of l1_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache0_freeze_en:1;
-        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache0_freeze_mode:1;
-        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_freeze_done:1;
-        uint32_t reserved_3:1;
-        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
-         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_icache1_freeze_en:1;
-        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_icache1_freeze_mode:1;
-        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_freeze_done:1;
-        uint32_t reserved_7:1;
-        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_en:1;
-        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_mode:1;
-        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_freeze_done:1;
-        uint32_t reserved_11:1;
-        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_en:1;
-        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_mode:1;
-        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_freeze_done:1;
-        uint32_t reserved_15:1;
-        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
-         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l1_cache_freeze_en:1;
-        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
-         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l1_cache_freeze_mode:1;
-        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_freeze_done:1;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} extmem_l1_cache_freeze_ctrl_reg_t;
-
-/** Type of l2_cache_freeze_ctrl register
- *  Cache Freeze control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
-         *  software.
-         */
-        uint32_t l2_cache_freeze_en:1;
-        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
-         *  will not stuck. 1: a miss-access will stuck.
-         */
-        uint32_t l2_cache_freeze_mode:1;
-        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
-         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_freeze_done:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} extmem_l2_cache_freeze_ctrl_reg_t;
-
-
-/** Group: Cache Data Memory Access Control and Configuration registers */
-/** Type of l1_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_data_mem_rd_en:1;
-        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache0_data_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_data_mem_rd_en:1;
-        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
-         *  1: enable.
-         */
-        uint32_t l1_icache1_data_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_rd_en:1;
-        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_data_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_rd_en:1;
-        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_data_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_rd_en:1;
-        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_data_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} extmem_l1_cache_data_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_data_mem_acs_conf register
- *  Cache data memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_rd_en:1;
-        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_data_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} extmem_l2_cache_data_mem_acs_conf_reg_t;
-
-
-/** Group: Cache Tag Memory Access Control and Configuration registers */
-/** Type of l1_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_rd_en:1;
-        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache0_tag_mem_wr_en:1;
-        uint32_t reserved_2:2;
-        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1;
-         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_rd_en:1;
-        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1;
-         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_icache1_tag_mem_wr_en:1;
-        uint32_t reserved_6:2;
-        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_rd_en:1;
-        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_mem_wr_en:1;
-        uint32_t reserved_10:2;
-        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_rd_en:1;
-        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_mem_wr_en:1;
-        uint32_t reserved_14:2;
-        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
-         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_rd_en:1;
-        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
-         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l1_cache_tag_mem_wr_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} extmem_l1_cache_tag_mem_acs_conf_reg_t;
-
-/** Type of l2_cache_tag_mem_acs_conf register
- *  Cache tag memory access configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
-         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_rd_en:1;
-        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
-         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
-         *  enable.
-         */
-        uint32_t l2_cache_tag_mem_wr_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} extmem_l2_cache_tag_mem_acs_conf_reg_t;
-
-
-/** Group: Prelock Control and configuration registers */
-/** Type of l1_icache0_prelock_conf register
- *  L1 instruction Cache 0 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct0_en:1;
-        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache0.
-         */
-        uint32_t l1_icache0_prelock_sct1_en:1;
-        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 prelock.
-         */
-        uint32_t l1_icache0_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_conf_reg_t;
-
-/** Type of l1_icache0_prelock_sct0_addr register
- *  L1 instruction Cache 0 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache0, which should be used together with
-         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct1_addr register
- *  L1 instruction Cache 0 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache0, which should be used together with
-         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache0_prelock_sct_size register
- *  L1 instruction Cache 0 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache0_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache0_prelock_sct_size_reg_t;
-
-/** Type of l1_icache1_prelock_conf register
- *  L1 instruction Cache 1 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct0_en:1;
-        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache1.
-         */
-        uint32_t l1_icache1_prelock_sct1_en:1;
-        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 prelock.
-         */
-        uint32_t l1_icache1_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_conf_reg_t;
-
-/** Type of l1_icache1_prelock_sct0_addr register
- *  L1 instruction Cache 1 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache1, which should be used together with
-         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct1_addr register
- *  L1 instruction Cache 1 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache1, which should be used together with
-         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache1_prelock_sct_size register
- *  L1 instruction Cache 1 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache1_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache1_prelock_sct_size_reg_t;
-
-/** Type of l1_icache2_prelock_conf register
- *  L1 instruction Cache 2 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct0_en:1;
-        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache2.
-         */
-        uint32_t l1_icache2_prelock_sct1_en:1;
-        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 prelock.
-         */
-        uint32_t l1_icache2_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_conf_reg_t;
-
-/** Type of l1_icache2_prelock_sct0_addr register
- *  L1 instruction Cache 2 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache2, which should be used together with
-         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct1_addr register
- *  L1 instruction Cache 2 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache2, which should be used together with
-         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache2_prelock_sct_size register
- *  L1 instruction Cache 2 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache2_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache2_prelock_sct_size_reg_t;
-
-/** Type of l1_icache3_prelock_conf register
- *  L1 instruction Cache 3 prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct0_en:1;
-        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-ICache3.
-         */
-        uint32_t l1_icache3_prelock_sct1_en:1;
-        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 prelock.
-         */
-        uint32_t l1_icache3_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_conf_reg_t;
-
-/** Type of l1_icache3_prelock_sct0_addr register
- *  L1 instruction Cache 3 prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-ICache3, which should be used together with
-         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct0_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct1_addr register
- *  L1 instruction Cache 3 prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-ICache3, which should be used together with
-         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct1_addr_reg_t;
-
-/** Type of l1_icache3_prelock_sct_size register
- *  L1 instruction Cache 3 prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_icache3_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_icache3_prelock_sct_size_reg_t;
-
-/** Type of l1_cache_prelock_conf register
- *  L1 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct0_en:1;
-        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L1-Cache.
-         */
-        uint32_t l1_cache_prelock_sct1_en:1;
-        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l1 cache prelock.
-         */
-        uint32_t l1_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l1_cache_prelock_conf_reg_t;
-
-/** Type of l1_cache_prelock_sct0_addr register
- *  L1 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct1_addr register
- *  L1 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L1-Cache, which should be used together with
-         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l1_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_prelock_sct1_addr_reg_t;
-
-/** Type of l1_dcache_prelock_sct_size register
- *  L1  Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct0_size:14;
-        uint32_t reserved_14:2;
-        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l1_cache_prelock_sct1_size:14;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} extmem_l1_dcache_prelock_sct_size_reg_t;
-
-/** Type of l2_cache_prelock_conf register
- *  L2 Cache prelock configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable the first section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct0_en:1;
-        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable the second section of prelock function on L2-Cache.
-         */
-        uint32_t l2_cache_prelock_sct1_en:1;
-        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
-         *  The bit is used to set  the gid of l2 cache prelock.
-         */
-        uint32_t l2_cache_prelock_rgid:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_conf_reg_t;
-
-/** Type of l2_cache_prelock_sct0_addr register
- *  L2 Cache prelock section0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section of
-         *  prelock on L2-Cache, which should be used together with
-         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct0_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct1_addr register
- *  L2 Cache prelock section1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section of
-         *  prelock on L2-Cache, which should be used together with
-         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
-         */
-        uint32_t l2_cache_prelock_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct1_addr_reg_t;
-
-/** Type of l2_cache_prelock_sct_size register
- *  L2 Cache prelock section size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct0_size:16;
-        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
-         *  Those bits are used to configure the size of the second section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
-         */
-        uint32_t l2_cache_prelock_sct1_size:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_prelock_sct_size_reg_t;
-
-
-/** Group: Lock Control and configuration registers */
-/** Type of cache_lock_ctrl register
- *  Lock-class (manual lock) operation control register
- */
-typedef union {
-    struct {
-        /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
-         *  operation done
-         */
-        uint32_t cache_lock_ena:1;
-        /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable unlock operation. It will be cleared by hardware after
-         *  unlock operation done
-         */
-        uint32_t cache_unlock_ena:1;
-        /** cache_lock_done : RO; bitpos: [2]; default: 1;
-         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
-         *  not finished. 1: finished.
-         */
-        uint32_t cache_lock_done:1;
-        /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of cache lock/unlock.
-         */
-        uint32_t cache_lock_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_cache_lock_ctrl_reg_t;
-
-/** Type of cache_lock_map register
- *  Lock (manual lock) map configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_map : R/W; bitpos: [5:0]; default: 0;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply this lock/unlock operation. [4]: L1-Cache
-         */
-        uint32_t cache_lock_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_cache_lock_map_reg_t;
-
-/** Type of cache_lock_addr register
- *  Lock (manual lock) address configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the lock/unlock
-         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
-         */
-        uint32_t cache_lock_addr:32;
-    };
-    uint32_t val;
-} extmem_cache_lock_addr_reg_t;
-
-/** Type of cache_lock_size register
- *  Lock (manual lock) size configure register
- */
-typedef union {
-    struct {
-        /** cache_lock_size : R/W; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the lock/unlock operation, which
-         *  should be used together with CACHE_LOCK_ADDR_REG
-         */
-        uint32_t cache_lock_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_cache_lock_size_reg_t;
-
-
-/** Group: Sync Control and configuration registers */
-/** Type of cache_sync_ctrl register
- *  Sync-class operation control register
- */
-typedef union {
-    struct {
-        /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
-         *  The bit is used to enable invalidate operation. It will be cleared by hardware
-         *  after invalidate operation done. Note that this bit and the other sync-bits
-         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_invalidate_ena:1;
-        /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0;
-         *  The bit is used to enable clean operation. It will be cleared by hardware after
-         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
-         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
-         *  bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_clean_ena:1;
-        /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0;
-         *  The bit is used to enable writeback operation. It will be cleared by hardware after
-         *  writeback operation done. Note that this bit and the other sync-bits
-         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
-         *  is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_writeback_ena:1;
-        /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
-         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
-         *  hardware after writeback-invalidate operation done. Note that this bit and the
-         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
-         *  that is, those bits can not be set to 1 at the same time.
-         */
-        uint32_t cache_writeback_invalidate_ena:1;
-        /** cache_sync_done : RO; bitpos: [4]; default: 0;
-         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
-         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
-         */
-        uint32_t cache_sync_done:1;
-        /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0;
-         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
-         *  writeback, writeback_invalidate)
-         */
-        uint32_t cache_sync_rgid:4;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} extmem_cache_sync_ctrl_reg_t;
-
-/** Type of cache_sync_map register
- *  Sync map configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_map : R/W; bitpos: [5:0]; default: 63;
-         *  Those bits are used to indicate which caches in the two-level cache structure will
-         *  apply the sync operation.  [4]: L1-Cache
-         */
-        uint32_t cache_sync_map:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_cache_sync_map_reg_t;
-
-/** Type of cache_sync_addr register
- *  Sync address configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the sync operation,
-         *  which should be used together with CACHE_SYNC_SIZE_REG
-         */
-        uint32_t cache_sync_addr:32;
-    };
-    uint32_t val;
-} extmem_cache_sync_addr_reg_t;
-
-/** Type of cache_sync_size register
- *  Sync size configure register
- */
-typedef union {
-    struct {
-        /** cache_sync_size : R/W; bitpos: [23:0]; default: 0;
-         *  Those bits are used to configure the size of the sync operation, which should be
-         *  used together with CACHE_SYNC_ADDR_REG
-         */
-        uint32_t cache_sync_size:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} extmem_cache_sync_size_reg_t;
-
-
-/** Group: Preload Control and configuration registers */
-/** Type of l1_icache0_preload_ctrl register
- *  L1 instruction Cache 0 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache0_preload_ena:1;
-        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache0_preload_done:1;
-        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache0_preload_order:1;
-        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 preload.
-         */
-        uint32_t l1_icache0_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_ctrl_reg_t;
-
-/** Type of l1_icache0_preload_addr register
- *  L1 instruction Cache 0 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache0_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_addr_reg_t;
-
-/** Type of l1_icache0_preload_size register
- *  L1 instruction Cache 0 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache0_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache0_preload_size_reg_t;
-
-/** Type of l1_icache1_preload_ctrl register
- *  L1 instruction Cache 1 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache1_preload_ena:1;
-        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache1_preload_done:1;
-        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache1_preload_order:1;
-        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 preload.
-         */
-        uint32_t l1_icache1_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_ctrl_reg_t;
-
-/** Type of l1_icache1_preload_addr register
- *  L1 instruction Cache 1 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache1_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_addr_reg_t;
-
-/** Type of l1_icache1_preload_size register
- *  L1 instruction Cache 1 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache1_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache1_preload_size_reg_t;
-
-/** Type of l1_icache2_preload_ctrl register
- *  L1 instruction Cache 2 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache2_preload_ena:1;
-        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache2_preload_done:1;
-        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache2_preload_order:1;
-        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 preload.
-         */
-        uint32_t l1_icache2_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_ctrl_reg_t;
-
-/** Type of l1_icache2_preload_addr register
- *  L1 instruction Cache 2 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache2_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_addr_reg_t;
-
-/** Type of l1_icache2_preload_size register
- *  L1 instruction Cache 2 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache2_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache2_preload_size_reg_t;
-
-/** Type of l1_icache3_preload_ctrl register
- *  L1 instruction Cache 3 preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_icache3_preload_ena:1;
-        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_icache3_preload_done:1;
-        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_icache3_preload_order:1;
-        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 preload.
-         */
-        uint32_t l1_icache3_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_ctrl_reg_t;
-
-/** Type of l1_icache3_preload_addr register
- *  L1 instruction Cache 3 preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_icache3_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_addr_reg_t;
-
-/** Type of l1_icache3_preload_size register
- *  L1 instruction Cache 3 preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_icache3_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache3_preload_size_reg_t;
-
-/** Type of l1_cache_preload_ctrl register
- *  L1 Cache  preload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l1_cache_preload_ena:1;
-        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l1_cache_preload_done:1;
-        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l1_cache_preload_order:1;
-        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l1 cache preload.
-         */
-        uint32_t l1_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l1_cache_preload_ctrl_reg_t;
-
-/** Type of l1_dcache_preload_addr register
- *  L1 Cache  preload address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
-         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l1_cache_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_preload_addr_reg_t;
-
-/** Type of l1_dcache_preload_size register
- *  L1 Cache  preload size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l1_cache_preload_size:14;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_dcache_preload_size_reg_t;
-
-/** Type of l2_cache_preload_ctrl register
- *  L2 Cache preload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
-         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
-         *  hardware automatically after preload operation is done.
-         */
-        uint32_t l2_cache_preload_ena:1;
-        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether preload operation is finished or not. 0: not
-         *  finished. 1: finished.
-         */
-        uint32_t l2_cache_preload_done:1;
-        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
-         *  descending.
-         */
-        uint32_t l2_cache_preload_order:1;
-        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
-         *  The bit is used to set  the gid of l2 cache preload.
-         */
-        uint32_t l2_cache_preload_rgid:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_ctrl_reg_t;
-
-/** Type of l2_cache_preload_addr register
- *  L2 Cache preload address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
-         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
-         */
-        uint32_t l2_cache_preload_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_addr_reg_t;
-
-/** Type of l2_cache_preload_size register
- *  L2 Cache preload size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
-         *  Those bits are used to configure the size of the first section of prelock on
-         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
-         */
-        uint32_t l2_cache_preload_size:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_size_reg_t;
-
-
-/** Group: Autoload Control and configuration registers */
-/** Type of l1_icache0_autoload_ctrl register
- *  L1 instruction Cache 0 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache0_autoload_ena:1;
-        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache0_autoload_done:1;
-        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache0_autoload_order:1;
-        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache0_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct0_ena:1;
-        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
-         */
-        uint32_t l1_icache0_autoload_sct1_ena:1;
-        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache0 autoload.
-         */
-        uint32_t l1_icache0_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_ctrl_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_addr register
- *  L1 instruction Cache 0 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct0_size register
- *  L1 instruction Cache 0 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_addr register
- *  L1 instruction Cache 0 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache0_autoload_sct1_size register
- *  L1 instruction Cache 0 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache0. Note that it should be used together with
-         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache0_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache0_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache1_autoload_ctrl register
- *  L1 instruction Cache 1 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache1_autoload_ena:1;
-        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache1_autoload_done:1;
-        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache1_autoload_order:1;
-        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache1_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct0_ena:1;
-        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
-         */
-        uint32_t l1_icache1_autoload_sct1_ena:1;
-        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache1 autoload.
-         */
-        uint32_t l1_icache1_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_ctrl_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_addr register
- *  L1 instruction Cache 1 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct0_size register
- *  L1 instruction Cache 1 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_addr register
- *  L1 instruction Cache 1 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache1_autoload_sct1_size register
- *  L1 instruction Cache 1 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache1. Note that it should be used together with
-         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache1_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache1_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache2_autoload_ctrl register
- *  L1 instruction Cache 2 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache2_autoload_ena:1;
-        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache2_autoload_done:1;
-        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache2_autoload_order:1;
-        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache2_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct0_ena:1;
-        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
-         */
-        uint32_t l1_icache2_autoload_sct1_ena:1;
-        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache2 autoload.
-         */
-        uint32_t l1_icache2_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_ctrl_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_addr register
- *  L1 instruction Cache 2 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct0_size register
- *  L1 instruction Cache 2 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_addr register
- *  L1 instruction Cache 2 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache2_autoload_sct1_size register
- *  L1 instruction Cache 2 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-ICache2. Note that it should be used together with
-         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache2_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache2_autoload_sct1_size_reg_t;
-
-/** Type of l1_icache3_autoload_ctrl register
- *  L1 instruction Cache 3 autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_icache3_autoload_ena:1;
-        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_icache3_autoload_done:1;
-        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_icache3_autoload_order:1;
-        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
-         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_icache3_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct0_ena:1;
-        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
-         */
-        uint32_t l1_icache3_autoload_sct1_ena:1;
-        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
-         *  The bit is used to set  the gid of l1 icache3 autoload.
-         */
-        uint32_t l1_icache3_autoload_rgid:4;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_ctrl_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_addr register
- *  L1 instruction Cache 3 autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct0_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct0_size register
- *  L1 instruction Cache 3 autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct0_size_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_addr register
- *  L1 instruction Cache 3 autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-ICache3. Note that it should be used together with
-         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_icache3_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct1_addr_reg_t;
-
-/** Type of l1_icache3_autoload_sct1_size register
- *  L1 instruction Cache 3 autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_icache3_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_ctrl register
- *  L1 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l1_cache_autoload_ena:1;
-        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l1_cache_autoload_done:1;
-        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l1_cache_autoload_order:1;
-        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l1_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct0_ena:1;
-        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct1_ena:1;
-        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct2_ena:1;
-        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
-         */
-        uint32_t l1_cache_autoload_sct3_ena:1;
-        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l1 cache autoload.
-         */
-        uint32_t l1_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_ctrl_reg_t;
-
-/** Type of l1_cache_autoload_sct0_addr register
- *  L1 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct0_size register
- *  L1 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l1_cache_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct0_size_reg_t;
-
-/** Type of l1_cache_autoload_sct1_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct1_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l1_cache_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct1_size_reg_t;
-
-/** Type of l1_cache_autoload_sct2_addr register
- *  L1 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the third section for
-         *  autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct2_size register
- *  L1 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l1_cache_autoload_sct2_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct2_size_reg_t;
-
-/** Type of l1_cache_autoload_sct3_addr register
- *  L1 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the fourth section
-         *  for autoload operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l1_cache_autoload_sct3_size register
- *  L1 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L1-Cache. Note that it should be used together with
-         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l1_cache_autoload_sct3_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_sct3_size_reg_t;
-
-/** Type of l2_cache_autoload_ctrl register
- *  L2 Cache autoload-operation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
-         *  0: disable.
-         */
-        uint32_t l2_cache_autoload_ena:1;
-        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
-         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
-         *  not. 0: not finished. 1: finished.
-         */
-        uint32_t l2_cache_autoload_done:1;
-        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
-         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
-         *  ascending. 1: descending.
-         */
-        uint32_t l2_cache_autoload_order:1;
-        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
-         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
-         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
-         */
-        uint32_t l2_cache_autoload_trigger_mode:2;
-        uint32_t reserved_5:3;
-        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable the first section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct0_ena:1;
-        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable the second section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct1_ena:1;
-        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
-         *  The bit is used to enable the third section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct2_ena:1;
-        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
-         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
-         */
-        uint32_t l2_cache_autoload_sct3_ena:1;
-        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
-         *  The bit is used to set  the gid of l2 cache autoload.
-         */
-        uint32_t l2_cache_autoload_rgid:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_sct0_addr register
- *  L2 Cache autoload section 0 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the first section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct0_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct0_size register
- *  L2 Cache autoload section 0 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the first section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
-         */
-        uint32_t l2_cache_autoload_sct0_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct0_size_reg_t;
-
-/** Type of l2_cache_autoload_sct1_addr register
- *  L2 Cache autoload section 1 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the second section
-         *  for autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct1_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct1_size register
- *  L2 Cache autoload section 1 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the second section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
-         */
-        uint32_t l2_cache_autoload_sct1_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct1_size_reg_t;
-
-/** Type of l2_cache_autoload_sct2_addr register
- *  L2 Cache autoload section 2 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the third section for
-         *  autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct2_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct2_size register
- *  L2 Cache autoload section 2 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the third section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
-         */
-        uint32_t l2_cache_autoload_sct2_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct2_size_reg_t;
-
-/** Type of l2_cache_autoload_sct3_addr register
- *  L2 Cache autoload section 3 address configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
-         *  Those bits are used to configure the start virtual address of the fourth section
-         *  for autoload operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct3_addr_reg_t;
-
-/** Type of l2_cache_autoload_sct3_size register
- *  L2 Cache autoload section 3 size configure register
- */
-typedef union {
-    struct {
-        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
-         *  Those bits are used to configure the size of the fourth section for autoload
-         *  operation on L2-Cache. Note that it should be used together with
-         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
-         */
-        uint32_t l2_cache_autoload_sct3_size:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_sct3_size_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of l1_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_ena:1;
-        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_ena:1;
-        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_ena:1;
-        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_ena:1;
-        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_ena:1;
-        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_ena:1;
-        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_ena:1;
-        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_ena:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
-         *  to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_clr:1;
-        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
-         *  to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_clr:1;
-        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_clr:1;
-        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_clr:1;
-        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_clr:1;
-        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
-         *  to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_clr:1;
-        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_clr:1;
-        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_clr:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
-         *  due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_raw:1;
-        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
-         *  due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_raw:1;
-        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
-         *  due to bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_ovf_int_raw:1;
-        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
-         *  due to bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_ovf_int_raw:1;
-        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_raw:1;
-        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_raw:1;
-        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_ovf_int_raw:1;
-        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
-         *  due to bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_ovf_int_raw:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l1_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache0 due to bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_ovf_int_st:1;
-        /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-ICache1 due to bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_ovf_int_st:1;
-        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_ovf_int_st:1;
-        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_ovf_int_st:1;
-        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus0 accesses L1-DCache.
-         */
-        uint32_t l1_bus0_ovf_int_st:1;
-        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L1-DCache due to bus1 accesses L1-DCache.
-         */
-        uint32_t l1_bus1_ovf_int_st:1;
-        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_ovf_int_st:1;
-        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_ovf_int_st:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l1_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_ena:1;
-        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_ena:1;
-        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_ena:1;
-        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_ena:1;
-        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_ena:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l1_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
-         *  cpu accesses L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_clr:1;
-        /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
-         *  cpu accesses L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_clr:1;
-        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_clr:1;
-        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_clr:1;
-        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
-         *  cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l1_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
-         */
-        uint32_t l1_icache0_fail_int_raw:1;
-        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
-         */
-        uint32_t l1_icache1_fail_int_raw:1;
-        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
-         */
-        uint32_t l1_icache2_fail_int_raw:1;
-        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
-         */
-        uint32_t l1_icache3_fail_int_raw:1;
-        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_raw:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l1_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_int_st:1;
-        /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
-         *  to cpu accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_int_st:1;
-        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_fail_int_st:1;
-        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_fail_int_st:1;
-        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
-         *  to cpu accesses L1-DCache.
-         */
-        uint32_t l1_cache_fail_int_st:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_int_st_reg_t;
-
-/** Type of l1_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache0_pld_done_int_ena:1;
-        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_icache1_pld_done_int_ena:1;
-        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_ena:1;
-        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_ena:1;
-        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
-         *  operation is done, interrupt occurs.
-         */
-        uint32_t l1_cache_pld_done_int_ena:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation done.
-         */
-        uint32_t cache_sync_done_int_ena:1;
-        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_ena:1;
-        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_ena:1;
-        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_ena:1;
-        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_ena:1;
-        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_ena:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_ena:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l1_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_clr:1;
-        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_clr:1;
-        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_clr:1;
-        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_clr:1;
-        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l1_cache_pld_done_int_clr:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
-         *  done.
-         */
-        uint32_t cache_sync_done_int_clr:1;
-        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_clr:1;
-        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_clr:1;
-        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_clr:1;
-        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_clr:1;
-        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
-         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_clr:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0;
-         *  The bit is used to clear interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_clr:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l1_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache0_pld_done_int_raw:1;
-        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
-         *  done.
-         */
-        uint32_t l1_icache1_pld_done_int_raw:1;
-        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_raw:1;
-        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_raw:1;
-        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l1_cache_pld_done_int_raw:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
-         */
-        uint32_t cache_sync_done_int_raw:1;
-        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache0_pld_err_int_raw:1;
-        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
-         *  error occurs.
-         */
-        uint32_t l1_icache1_pld_err_int_raw:1;
-        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_raw:1;
-        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_raw:1;
-        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_err_int_raw:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
-         *  occurs.
-         */
-        uint32_t cache_sync_err_int_raw:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l1_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache0_pld_done_int_st:1;
-        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
-         *  preload-operation is done.
-         */
-        uint32_t l1_icache1_pld_done_int_st:1;
-        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_done_int_st:1;
-        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_done_int_st:1;
-        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l1_cache_pld_done_int_st:1;
-        uint32_t reserved_5:1;
-        /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when Cache
-         *  sync-operation is done.
-         */
-        uint32_t cache_sync_done_int_st:1;
-        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
-         */
-        uint32_t l1_icache0_pld_err_int_st:1;
-        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
-         */
-        uint32_t l1_icache1_pld_err_int_st:1;
-        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_int_st:1;
-        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_int_st:1;
-        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
-         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
-         */
-        uint32_t l1_cache_pld_err_int_st:1;
-        uint32_t reserved_12:1;
-        /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0;
-         *  The bit indicates the status of the interrupt of Cache sync-operation error.
-         */
-        uint32_t cache_sync_err_int_st:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_int_st_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_ena register
- *  Cache Access Counter Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_ena:1;
-        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_ena:1;
-        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_ena:1;
-        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_ena:1;
-        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_ena:1;
-        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable interrupt of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_ena:1;
-        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_ena:1;
-        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_ena:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_ena_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_clr register
- *  Cache Access Counter Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_clr:1;
-        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_clr:1;
-        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_clr:1;
-        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_clr:1;
-        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_clr:1;
-        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
-         *  to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_clr:1;
-        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_clr:1;
-        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_clr:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_clr_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_raw register
- *  Cache Access Counter Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-ICache0.
-         */
-        uint32_t l2_ibus0_ovf_int_raw:1;
-        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-ICache1.
-         */
-        uint32_t l2_ibus1_ovf_int_raw:1;
-        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-ICache2.
-         */
-        uint32_t l2_ibus2_ovf_int_raw:1;
-        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-ICache3.
-         */
-        uint32_t l2_ibus3_ovf_int_raw:1;
-        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus0 accesses L2-DCache.
-         */
-        uint32_t l2_dbus0_ovf_int_raw:1;
-        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus1 accesses L2-DCache.
-         */
-        uint32_t l2_dbus1_ovf_int_raw:1;
-        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus2 accesses L2-DCache.
-         */
-        uint32_t l2_dbus2_ovf_int_raw:1;
-        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
-         *  due to bus3 accesses L2-DCache.
-         */
-        uint32_t l2_dbus3_ovf_int_raw:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_raw_reg_t;
-
-/** Type of l2_cache_acs_cnt_int_st register
- *  Cache Access Counter Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_ibus0_ovf_int_st:1;
-        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_ibus1_ovf_int_st:1;
-        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_ovf_int_st:1;
-        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_ovf_int_st:1;
-        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus0 accesses L2-Cache.
-         */
-        uint32_t l2_dbus0_ovf_int_st:1;
-        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
-         *  The bit indicates the interrupt status of one of counters overflow that occurs in
-         *  L2-Cache due to bus1 accesses L2-Cache.
-         */
-        uint32_t l2_dbus1_ovf_int_st:1;
-        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_ovf_int_st:1;
-        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_ovf_int_st:1;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_int_st_reg_t;
-
-/** Type of l2_cache_acs_fail_int_ena register
- *  Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
-         *  l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_ena_reg_t;
-
-/** Type of l2_cache_acs_fail_int_clr register
- *  L1-Cache Access Fail Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
-         *  cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_clr_reg_t;
-
-/** Type of l2_cache_acs_fail_int_raw register
- *  Cache Access Fail Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_raw_reg_t;
-
-/** Type of l2_cache_acs_fail_int_st register
- *  Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
-         *  to l1 cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_int_st_reg_t;
-
-/** Type of l2_cache_sync_preload_int_ena register
- *  L1-Cache Access Fail Interrupt enable register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
-         */
-        uint32_t l2_cache_pld_done_int_ena:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_ena:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_ena_reg_t;
-
-/** Type of l2_cache_sync_preload_int_clr register
- *  Sync Preload operation Interrupt clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
-         *  is done.
-         */
-        uint32_t l2_cache_pld_done_int_clr:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_clr:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_clr_reg_t;
-
-/** Type of l2_cache_sync_preload_int_raw register
- *  Sync Preload operation Interrupt raw register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
-         *  done.
-         */
-        uint32_t l2_cache_pld_done_int_raw:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_err_int_raw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_raw_reg_t;
-
-/** Type of l2_cache_sync_preload_int_st register
- *  L1-Cache Access Fail Interrupt status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
-         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
-         *  preload-operation is done.
-         */
-        uint32_t l2_cache_pld_done_int_st:1;
-        uint32_t reserved_6:6;
-        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
-         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
-         */
-        uint32_t l2_cache_pld_err_int_st:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_int_st_reg_t;
-
-
-/** Group: Access Statistics registers */
-/** Type of l1_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to enable ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_ena:1;
-        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to enable ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_ena:1;
-        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_ena:1;
-        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_ena:1;
-        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to enable dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_ena:1;
-        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
-         *  The bit is used to enable dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_ena:1;
-        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_ena:1;
-        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_ena:1;
-        uint32_t reserved_8:8;
-        /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0;
-         *  The bit is used to clear ibus0 counter in L1-ICache0.
-         */
-        uint32_t l1_ibus0_cnt_clr:1;
-        /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0;
-         *  The bit is used to clear ibus1 counter in L1-ICache1.
-         */
-        uint32_t l1_ibus1_cnt_clr:1;
-        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus2_cnt_clr:1;
-        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_ibus3_cnt_clr:1;
-        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
-         *  The bit is used to clear dbus0 counter in L1-DCache.
-         */
-        uint32_t l1_bus0_cnt_clr:1;
-        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
-         *  The bit is used to clear dbus1 counter in L1-DCache.
-         */
-        uint32_t l1_bus1_cnt_clr:1;
-        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus2_cnt_clr:1;
-        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_dbus3_cnt_clr:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l1_ibus0_acs_hit_cnt register
- *  L1-ICache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_miss_cnt register
- *  L1-ICache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_conflict_cnt register
- *  L1-ICache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
-         */
-        uint32_t l1_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus0_acs_nxtlvl_cnt register
- *  L1-ICache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l1_ibus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_hit_cnt register
- *  L1-ICache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_miss_cnt register
- *  L1-ICache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_conflict_cnt register
- *  L1-ICache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
-         */
-        uint32_t l1_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus1_acs_nxtlvl_cnt register
- *  L1-ICache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l1_ibus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_hit_cnt register
- *  L1-ICache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_miss_cnt register
- *  L1-ICache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_conflict_cnt register
- *  L1-ICache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
-         */
-        uint32_t l1_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus2_acs_nxtlvl_cnt register
- *  L1-ICache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l1_ibus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_hit_cnt register
- *  L1-ICache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_miss_cnt register
- *  L1-ICache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_conflict_cnt register
- *  L1-ICache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
-         */
-        uint32_t l1_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_ibus3_acs_nxtlvl_cnt register
- *  L1-ICache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-ICache accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l1_ibus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_bus0_acs_hit_cnt register
- *  L1-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus0_acs_miss_cnt register
- *  L1-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus0_acs_conflict_cnt register
- *  L1-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
-         */
-        uint32_t l1_bus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_conflict_cnt_reg_t;
-
-/** Type of l1_bus0_acs_nxtlvl_cnt register
- *  L1-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus0 accessing L1-Cache.
-         */
-        uint32_t l1_bus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_bus1_acs_hit_cnt register
- *  L1-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_hit_cnt_reg_t;
-
-/** Type of l1_bus1_acs_miss_cnt register
- *  L1-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_miss_cnt_reg_t;
-
-/** Type of l1_bus1_acs_conflict_cnt register
- *  L1-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
-         */
-        uint32_t l1_bus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_conflict_cnt_reg_t;
-
-/** Type of l1_bus1_acs_nxtlvl_cnt register
- *  L1-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-Cache accesses L2-Cache due to
-         *  bus1 accessing L1-Cache.
-         */
-        uint32_t l1_bus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_hit_cnt register
- *  L1-DCache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_miss_cnt register
- *  L1-DCache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_conflict_cnt register
- *  L1-DCache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
-         */
-        uint32_t l1_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus2_acs_nxtlvl_cnt register
- *  L1-DCache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l1_dbus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_hit_cnt register
- *  L1-DCache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_miss_cnt register
- *  L1-DCache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_conflict_cnt register
- *  L1-DCache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
-         */
-        uint32_t l1_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l1_dbus3_acs_nxtlvl_cnt register
- *  L1-DCache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l1_dbus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_cache_acs_cnt_ctrl register
- *  Cache Access Counter enable and clear register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
-         *  The bit is used to enable ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_ena:1;
-        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
-         *  The bit is used to enable ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_ena:1;
-        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_ena:1;
-        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_ena:1;
-        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
-         *  The bit is used to enable dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_ena:1;
-        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
-         *  The bit is used to enable dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_ena:1;
-        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_ena:1;
-        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_ena:1;
-        uint32_t reserved_16:8;
-        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
-         *  The bit is used to clear ibus0 counter in L2-Cache.
-         */
-        uint32_t l2_ibus0_cnt_clr:1;
-        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
-         *  The bit is used to clear ibus1 counter in L2-Cache.
-         */
-        uint32_t l2_ibus1_cnt_clr:1;
-        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus2_cnt_clr:1;
-        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_ibus3_cnt_clr:1;
-        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
-         *  The bit is used to clear dbus0 counter in L2-Cache.
-         */
-        uint32_t l2_dbus0_cnt_clr:1;
-        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
-         *  The bit is used to clear dbus1 counter in L2-Cache.
-         */
-        uint32_t l2_dbus1_cnt_clr:1;
-        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus2_cnt_clr:1;
-        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
-         *  Reserved
-         */
-        uint32_t l2_dbus3_cnt_clr:1;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_cnt_ctrl_reg_t;
-
-/** Type of l2_ibus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
-         *  bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache0 accesses
-         *  L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus0_acs_nxtlvl_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
-         */
-        uint32_t l2_ibus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
-         *  bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache1 accesses
-         *  L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus1_acs_nxtlvl_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
-         */
-        uint32_t l2_ibus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
-         *  bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache2 accesses
-         *  L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus2_acs_nxtlvl_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
-         */
-        uint32_t l2_ibus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
-         *  bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-ICache3 accesses
-         *  L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_ibus3_acs_nxtlvl_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
-         */
-        uint32_t l2_ibus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_hit_cnt register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_miss_cnt register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_conflict_cnt register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus0_acs_nxtlvl_cnt register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
-         */
-        uint32_t l2_dbus0_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_hit_cnt register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_miss_cnt register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_conflict_cnt register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus1_acs_nxtlvl_cnt register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
-         */
-        uint32_t l2_dbus1_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_hit_cnt register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_miss_cnt register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_conflict_cnt register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus2_acs_nxtlvl_cnt register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
-         */
-        uint32_t l2_dbus2_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_hit_cnt register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_hit_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_hit_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_miss_cnt register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
-         *  bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_miss_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_miss_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_conflict_cnt register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of access-conflicts when L1-DCache accesses
-         *  L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_conflict_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_conflict_cnt_reg_t;
-
-/** Type of l2_dbus3_acs_nxtlvl_cnt register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-typedef union {
-    struct {
-        /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
-         *  The register records the number of times that L2-Cache accesses external memory due
-         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
-         */
-        uint32_t l2_dbus3_nxtlvl_cnt:32;
-    };
-    uint32_t val;
-} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t;
-
-
-/** Group: Access Fail Debug registers */
-/** Type of l1_icache0_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_id:16;
-        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache0_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache0_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache0 accesses L1-ICache.
-         */
-        uint32_t l1_icache0_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache0_acs_fail_addr_reg_t;
-
-/** Type of l1_icache1_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_id:16;
-        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache1_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache1_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache1 accesses L1-ICache.
-         */
-        uint32_t l1_icache1_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache1_acs_fail_addr_reg_t;
-
-/** Type of l1_icache2_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_id:16;
-        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache2_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache2_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache2 accesses L1-ICache.
-         */
-        uint32_t l1_icache2_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache2_acs_fail_addr_reg_t;
-
-/** Type of l1_icache3_acs_fail_id_attr register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_id:16;
-        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_icache3_acs_fail_id_attr_reg_t;
-
-/** Type of l1_icache3_acs_fail_addr register
- *  L1-ICache0 Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache3 accesses L1-ICache.
-         */
-        uint32_t l1_icache3_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_icache3_acs_fail_addr_reg_t;
-
-/** Type of l1_cache_acs_fail_id_attr register
- *  L1-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_id:16;
-        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l1_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l1_dcache_acs_fail_addr register
- *  L1-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when cache accesses L1-Cache.
-         */
-        uint32_t l1_cache_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l1_dcache_acs_fail_addr_reg_t;
-
-/** Type of l2_cache_acs_fail_id_attr register
- *  L2-Cache Access Fail ID/attribution information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
-         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_id:16;
-        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
-         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
-         *  due to cache accessing L1-Cache.
-         */
-        uint32_t l2_cache_fail_attr:16;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_id_attr_reg_t;
-
-/** Type of l2_cache_acs_fail_addr register
- *  L2-Cache Access Fail Address information register
- */
-typedef union {
-    struct {
-        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
-         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
-         */
-        uint32_t l2_cache_fail_addr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_acs_fail_addr_reg_t;
-
-
-/** Group: Operation Exception registers */
-/** Type of l1_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache0.
-         */
-        uint32_t l1_icache0_pld_err_code:2;
-        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-ICache1.
-         */
-        uint32_t l1_icache1_pld_err_code:2;
-        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_err_code:2;
-        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_err_code:2;
-        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L1-Cache.
-         */
-        uint32_t l1_cache_pld_err_code:2;
-        uint32_t reserved_10:2;
-        /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0;
-         *  The values 0-2 are available which means sync map, command conflict and size are
-         *  error in Cache System.
-         */
-        uint32_t cache_sync_err_code:2;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_preload_exception_reg_t;
-
-/** Type of l2_cache_sync_preload_exception register
- *  Cache Sync/Preload Operation exception register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:10;
-        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
-         *  The value 2 is Only available which means preload size is error in L2-Cache.
-         */
-        uint32_t l2_cache_pld_err_code:2;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_preload_exception_reg_t;
-
-
-/** Group: Sync Reset control and configuration registers */
-/** Type of l1_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache0_sync_rst:1;
-        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_icache1_sync_rst:1;
-        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_sync_rst:1;
-        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_sync_rst:1;
-        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l1_cache_sync_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_sync_rst_ctrl_reg_t;
-
-/** Type of l2_cache_sync_rst_ctrl register
- *  Cache Sync Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
-         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
-         */
-        uint32_t l2_cache_sync_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_sync_rst_ctrl_reg_t;
-
-
-/** Group: Preload Reset control and configuration registers */
-/** Type of l1_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache0_pld_rst:1;
-        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
-         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_icache1_pld_rst:1;
-        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_pld_rst:1;
-        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_pld_rst:1;
-        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
-         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l1_cache_pld_rst:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_preload_rst_ctrl_reg_t;
-
-/** Type of l2_cache_preload_rst_ctrl register
- *  Cache Preload Reset control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
-         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
-         *  only be used to initialize preload-logic when some fatal error of preload-logic
-         *  occurs.
-         */
-        uint32_t l2_cache_pld_rst:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_preload_rst_ctrl_reg_t;
-
-
-/** Group: Autoload buffer clear control and configuration registers */
-/** Type of l1_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
-         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
-         *  works in L1-ICache0.
-         */
-        uint32_t l1_icache0_ald_buf_clr:1;
-        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
-         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
-         *  works in L1-ICache1.
-         */
-        uint32_t l1_icache1_ald_buf_clr:1;
-        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_ald_buf_clr:1;
-        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_ald_buf_clr:1;
-        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
-         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
-         *  autoload will not work in L1-Cache. This bit should not be active when autoload
-         *  works in L1-Cache.
-         */
-        uint32_t l1_cache_ald_buf_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t;
-
-/** Type of l2_cache_autoload_buf_clr_ctrl register
- *  Cache Autoload buffer clear control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
-         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
-         *  autoload will not work in L2-Cache. This bit should not be active when autoload
-         *  works in L2-Cache.
-         */
-        uint32_t l2_cache_ald_buf_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t;
-
-
-/** Group: Unallocate request buffer clear registers */
-/** Type of l1_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache0_unalloc_clr:1;
-        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_icache1_unalloc_clr:1;
-        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_unalloc_clr:1;
-        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_unalloc_clr:1;
-        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l1_cache_unalloc_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} extmem_l1_unallocate_buffer_clear_reg_t;
-
-/** Type of l2_unallocate_buffer_clear register
- *  Unallocate request buffer clear registers
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
-         *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
-         */
-        uint32_t l2_cache_unalloc_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} extmem_l2_unallocate_buffer_clear_reg_t;
-
-
-/** Group: Tag and Data Memory Access Control and configuration register */
-/** Type of l1_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0;
-         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache0_tag_object:1;
-        /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0;
-         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_icache1_tag_object:1;
-        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_tag_object:1;
-        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_tag_object:1;
-        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_tag_object:1;
-        uint32_t reserved_5:1;
-        /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0;
-         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache0_mem_object:1;
-        /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0;
-         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
-         *  with the others fields inside this register.
-         */
-        uint32_t l1_icache1_mem_object:1;
-        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache2_mem_object:1;
-        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
-         *  Reserved
-         */
-        uint32_t l1_icache3_mem_object:1;
-        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l1_cache_mem_object:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} extmem_l1_cache_object_ctrl_reg_t;
-
-/** Type of l1_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l1_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} extmem_l1_cache_way_object_reg_t;
-
-/** Type of l1_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l1_cache_vaddr:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_vaddr_reg_t;
-
-/** Type of l1_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l1_cache_debug_bus:32;
-    };
-    uint32_t val;
-} extmem_l1_cache_debug_bus_reg_t;
-
-/** Type of l2_cache_object_ctrl register
- *  Cache Tag and Data memory Object control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:5;
-        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
-         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_tag_object:1;
-        uint32_t reserved_6:5;
-        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
-         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
-         *  the others fields inside this register.
-         */
-        uint32_t l2_cache_mem_object:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} extmem_l2_cache_object_ctrl_reg_t;
-
-/** Type of l2_cache_way_object register
- *  Cache Tag and Data memory way register
- */
-typedef union {
-    struct {
-        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
-         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
-         *  way1, 2: way2, 3: way3, ?, 7: way7.
-         */
-        uint32_t l2_cache_way_object:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} extmem_l2_cache_way_object_reg_t;
-
-/** Type of l2_cache_vaddr register
- *  Cache Vaddr register
- */
-typedef union {
-    struct {
-        /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824;
-         *  Those bits stores the virtual address which will decide where inside the specified
-         *  tag memory object will be accessed.
-         */
-        uint32_t l2_cache_vaddr:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_vaddr_reg_t;
-
-/** Type of l2_cache_debug_bus register
- *  Cache Tag/data memory content register
- */
-typedef union {
-    struct {
-        /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932;
-         *  This is a constant place where we can write data to or read data from the tag/data
-         *  memory on the specified cache.
-         */
-        uint32_t l2_cache_debug_bus:32;
-    };
-    uint32_t val;
-} extmem_l2_cache_debug_bus_reg_t;
-
-
-/** Group: Split L1 and L2 registers */
-/** Type of level_split0 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split0 : HRO; bitpos: [31:0]; default: 600;
-         *  Reserved
-         */
-        uint32_t level_split0:32;
-    };
-    uint32_t val;
-} extmem_level_split0_reg_t;
-
-/** Type of level_split1 register
- *  USED TO SPLIT L1 CACHE AND L2 CACHE
- */
-typedef union {
-    struct {
-        /** level_split1 : HRO; bitpos: [31:0]; default: 936;
-         *  Reserved
-         */
-        uint32_t level_split1:32;
-    };
-    uint32_t val;
-} extmem_level_split1_reg_t;
-
-
-/** Group: L2 cache access attribute control register */
-/** Type of l2_cache_access_attr_ctrl register
- *  L1 Cache access Attribute propagation control register
- */
-typedef union {
-    struct {
-        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
-         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
-         *  non-cacheable.
-         */
-        uint32_t l2_cache_access_force_cc:1;
-        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
-         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
-         *  write-through.
-         */
-        uint32_t l2_cache_access_force_wb:1;
-        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
-         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  write-miss-allocate and write-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_wma:1;
-        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
-         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
-         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
-         *  read-miss-allocate and read-miss-no-allocate.
-         */
-        uint32_t l2_cache_access_force_rma:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} extmem_l2_cache_access_attr_ctrl_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  The bit is used to enable clock gate when access all registers in this module.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} extmem_clock_gate_reg_t;
-
-
-/** Group: Redundancy  register (Prepare for ECO) */
-/** Type of redundancy_sig0 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig0:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig0_reg_t;
-
-/** Type of redundancy_sig1 register
- *  Cache redundancy signal 1 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig1:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig1_reg_t;
-
-/** Type of redundancy_sig2 register
- *  Cache redundancy signal 2 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig2:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig2_reg_t;
-
-/** Type of redundancy_sig3 register
- *  Cache redundancy signal 3 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig3:32;
-    };
-    uint32_t val;
-} extmem_redundancy_sig3_reg_t;
-
-/** Type of redundancy_sig4 register
- *  Cache redundancy signal 0 register
- */
-typedef union {
-    struct {
-        /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0;
-         *  Those bits are prepared for ECO.
-         */
-        uint32_t cache_redcy_sig4:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} extmem_redundancy_sig4_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35659904;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} extmem_date_reg_t;
-
-
-typedef struct extmem_dev_s {
-    volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl;
-    volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl;
-    volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
-    volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
-    volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
-    volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
-    volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
-    volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
-    volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
-    volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
-    volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
-    volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
-    volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
-    volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
-    volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
-    volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
-    volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
-    volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
-    volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
-    volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
-    volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
-    volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
-    volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
-    volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
-    volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
-    volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
-    volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
-    volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
-    volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
-    volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
-    volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
-    volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
-    volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
-    volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
-    volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl;
-    volatile extmem_cache_lock_map_reg_t cache_lock_map;
-    volatile extmem_cache_lock_addr_reg_t cache_lock_addr;
-    volatile extmem_cache_lock_size_reg_t cache_lock_size;
-    volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl;
-    volatile extmem_cache_sync_map_reg_t cache_sync_map;
-    volatile extmem_cache_sync_addr_reg_t cache_sync_addr;
-    volatile extmem_cache_sync_size_reg_t cache_sync_size;
-    volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
-    volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
-    volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
-    volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
-    volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
-    volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
-    volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
-    volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
-    volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
-    volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
-    volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
-    volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
-    volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
-    volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
-    volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
-    volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
-    volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
-    volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
-    volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
-    volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
-    volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
-    volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
-    volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
-    volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
-    volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
-    volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
-    volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
-    volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
-    volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
-    volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
-    volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
-    volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
-    volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
-    volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
-    volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
-    volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
-    volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
-    volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
-    volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
-    volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
-    volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
-    volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
-    volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
-    volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
-    volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
-    volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
-    volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
-    volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
-    volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
-    volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
-    volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
-    volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
-    volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
-    volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
-    volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
-    volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
-    volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
-    volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
-    volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
-    volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
-    volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
-    volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
-    volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt;
-    volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
-    volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
-    volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
-    volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt;
-    volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
-    volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
-    volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
-    volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt;
-    volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
-    volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
-    volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
-    volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt;
-    volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
-    volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
-    volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
-    volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt;
-    volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
-    volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
-    volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
-    volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt;
-    volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
-    volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
-    volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
-    volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
-    volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
-    volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
-    volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
-    volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
-    volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr;
-    volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
-    volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
-    volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
-    volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
-    volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
-    volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
-    volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
-    volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
-    volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
-    volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
-    volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
-    volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object;
-    volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr;
-    volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
-    volatile extmem_level_split0_reg_t level_split0;
-    volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl;
-    volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
-    volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
-    volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
-    volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
-    volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
-    volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
-    volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
-    volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
-    volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
-    volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
-    volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
-    volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
-    volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
-    volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
-    volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
-    volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size;
-    volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
-    volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
-    volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
-    volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
-    volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
-    volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
-    volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
-    volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
-    volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
-    volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
-    volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
-    volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
-    volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
-    volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
-    volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
-    volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
-    volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
-    volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
-    volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
-    volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
-    volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
-    volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
-    volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
-    volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
-    volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
-    volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
-    volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
-    volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt;
-    volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
-    volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
-    volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
-    volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
-    volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
-    volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
-    volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
-    volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
-    volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
-    volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
-    volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
-    volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
-    volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt;
-    volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
-    volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
-    volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
-    volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt;
-    volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
-    volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
-    volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
-    volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
-    volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
-    volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
-    volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
-    volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
-    volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
-    volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
-    volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
-    volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
-    volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
-    volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object;
-    volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr;
-    volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
-    volatile extmem_level_split1_reg_t level_split1;
-    volatile extmem_clock_gate_reg_t clock_gate;
-    volatile extmem_redundancy_sig0_reg_t redundancy_sig0;
-    volatile extmem_redundancy_sig1_reg_t redundancy_sig1;
-    volatile extmem_redundancy_sig2_reg_t redundancy_sig2;
-    volatile extmem_redundancy_sig3_reg_t redundancy_sig3;
-    volatile extmem_redundancy_sig4_reg_t redundancy_sig4;
-    uint32_t reserved_3c4[14];
-    volatile extmem_date_reg_t date;
-} extmem_dev_t;
-
-extern extmem_dev_t EXTMEM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/hp_system_reg.h b/components/soc/esp32h2/include/soc/hp_system_reg.h
deleted file mode 100644
index 1660509115e..00000000000
--- a/components/soc/esp32h2/include/soc/hp_system_reg.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
- *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
- */
-#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
-/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
- */
-#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
-#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
-#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
-/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : HRO; bitpos: [1]; default: 0;
- *  reserved
- */
-#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
-#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
-#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
-/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
- *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
- */
-#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
-#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
-#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
-#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
-/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
- *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
- */
-#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
-#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
-
-/** HP_SYSTEM_SRAM_USAGE_CONF_REG register
- *  HP memory usage configuration register
- */
-#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
-/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [14:10]; default: 0;
- *  0: cpu use hp-memory. 1: mac-dump accessing hp-memory.
- */
-#define HP_SYSTEM_SRAM_USAGE    0x0000001FU
-#define HP_SYSTEM_SRAM_USAGE_M  (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S)
-#define HP_SYSTEM_SRAM_USAGE_V  0x0000001FU
-#define HP_SYSTEM_SRAM_USAGE_S  10
-/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [24:20]; default: 0;
- *  reserved.
- */
-#define HP_SYSTEM_MAC_DUMP_ALLOC    0x0000001FU
-#define HP_SYSTEM_MAC_DUMP_ALLOC_M  (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S)
-#define HP_SYSTEM_MAC_DUMP_ALLOC_V  0x0000001FU
-#define HP_SYSTEM_MAC_DUMP_ALLOC_S  20
-/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [31]; default: 0;
- *  reserved
- */
-#define HP_SYSTEM_CACHE_USAGE    (BIT(31))
-#define HP_SYSTEM_CACHE_USAGE_M  (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
-#define HP_SYSTEM_CACHE_USAGE_V  0x00000001U
-#define HP_SYSTEM_CACHE_USAGE_S  31
-
-/** HP_SYSTEM_SEC_DPA_CONF_REG register
- *  HP anti-DPA security configuration register
- */
-#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
-/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
- *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
- *  the number, the stronger the ability to resist DPA attacks and the higher the
- *  security level, but it will increase the computational overhead of the hardware
- *  crypto-accelerators. Only avaliable if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
- */
-#define HP_SYSTEM_SEC_DPA_LEVEL    0x00000003U
-#define HP_SYSTEM_SEC_DPA_LEVEL_M  (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
-#define HP_SYSTEM_SEC_DPA_LEVEL_V  0x00000003U
-#define HP_SYSTEM_SEC_DPA_LEVEL_S  0
-/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
- *  This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
- *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
- */
-#define HP_SYSTEM_SEC_DPA_CFG_SEL    (BIT(2))
-#define HP_SYSTEM_SEC_DPA_CFG_SEL_M  (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
-#define HP_SYSTEM_SEC_DPA_CFG_SEL_V  0x00000001U
-#define HP_SYSTEM_SEC_DPA_CFG_SEL_S  2
-
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
- *  CPU_PERI_TIMEOUT configuration register
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc)
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
- *  Set the timeout threshold for bus access, corresponding to the number of clock
- *  cycles of the clock domain.
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S  0
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
- *  Set this bit as 1 to clear timeout interrupt
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S  16
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
- *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
- *  registers
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S  17
-
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
- *  CPU_PERI_TIMEOUT_ADDR register
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10)
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Record the address information of abnormal access
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S  0
-
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
- *  CPU_PERI_TIMEOUT_UID register
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14)
-/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
- *  will be cleared after the interrupt is cleared.
- */
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID    0x0000007FU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V  0x0000007FU
-#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S  0
-
-/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
- *  HP_PERI_TIMEOUT configuration register
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18)
-/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
- *  Set the timeout threshold for bus access, corresponding to the number of clock
- *  cycles of the clock domain.
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S  0
-/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
- *  Set this bit as 1 to clear timeout interrupt
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
-#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
-#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S  16
-/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
- *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
-#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
-#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S  17
-
-/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
- *  HP_PERI_TIMEOUT_ADDR register
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c)
-/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  Record the address information of abnormal access
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S  0
-
-/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
- *  HP_PERI_TIMEOUT_UID register
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20)
-/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
- *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
- *  will be cleared after the interrupt is cleared.
- */
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID    0x0000007FU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M  (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V  0x0000007FU
-#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S  0
-
-/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
- *  Rom-Table lock register
- */
-#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
-/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
- *  XXXX
- */
-#define HP_SYSTEM_ROM_TABLE_LOCK    (BIT(0))
-#define HP_SYSTEM_ROM_TABLE_LOCK_M  (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
-#define HP_SYSTEM_ROM_TABLE_LOCK_V  0x00000001U
-#define HP_SYSTEM_ROM_TABLE_LOCK_S  0
-
-/** HP_SYSTEM_ROM_TABLE_REG register
- *  Rom-Table register
- */
-#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
-/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
- *  XXXX
- */
-#define HP_SYSTEM_ROM_TABLE    0xFFFFFFFFU
-#define HP_SYSTEM_ROM_TABLE_M  (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
-#define HP_SYSTEM_ROM_TABLE_V  0xFFFFFFFFU
-#define HP_SYSTEM_ROM_TABLE_S  0
-
-/** HP_SYSTEM_MEM_TEST_CONF_REG register
- *  MEM_TEST configuration register
- */
-#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
-/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
- *  This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V
- *  operating Voltage.
- */
-#define HP_SYSTEM_HP_MEM_WPULSE    0x00000007U
-#define HP_SYSTEM_HP_MEM_WPULSE_M  (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S)
-#define HP_SYSTEM_HP_MEM_WPULSE_V  0x00000007U
-#define HP_SYSTEM_HP_MEM_WPULSE_S  0
-/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 5;
- *  This field controls hp system memory WA parameter. 0b100 for 1.1V operating
- *  Voltage, 0b101 for 1.0V, 0b110 for 0.9V.
- */
-#define HP_SYSTEM_HP_MEM_WA    0x00000007U
-#define HP_SYSTEM_HP_MEM_WA_M  (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S)
-#define HP_SYSTEM_HP_MEM_WA_V  0x00000007U
-#define HP_SYSTEM_HP_MEM_WA_S  3
-/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
- *  This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating
- *  Voltage, 0b01 for 0.9V.
- */
-#define HP_SYSTEM_HP_MEM_RA    0x00000003U
-#define HP_SYSTEM_HP_MEM_RA_M  (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S)
-#define HP_SYSTEM_HP_MEM_RA_V  0x00000003U
-#define HP_SYSTEM_HP_MEM_RA_S  6
-/** HP_SYSTEM_HP_MEM_RM : R/W; bitpos: [11:8]; default: 2;
- *  This field controls hp system memory RM parameter. 0b0011 for 1.1V operating
- *  Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V.
- */
-#define HP_SYSTEM_HP_MEM_RM    0x0000000FU
-#define HP_SYSTEM_HP_MEM_RM_M  (HP_SYSTEM_HP_MEM_RM_V << HP_SYSTEM_HP_MEM_RM_S)
-#define HP_SYSTEM_HP_MEM_RM_V  0x0000000FU
-#define HP_SYSTEM_HP_MEM_RM_S  8
-/** HP_SYSTEM_ROM_RM : R/W; bitpos: [15:12]; default: 2;
- *  This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for
- *  1.0V, 0b0010(default) or 0b0001(slow) for 0.9V.
- */
-#define HP_SYSTEM_ROM_RM    0x0000000FU
-#define HP_SYSTEM_ROM_RM_M  (HP_SYSTEM_ROM_RM_V << HP_SYSTEM_ROM_RM_S)
-#define HP_SYSTEM_ROM_RM_V  0x0000000FU
-#define HP_SYSTEM_ROM_RM_S  12
-
-/** HP_SYSTEM_RND_ECO_REG register
- *  redcy eco register.
- */
-#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0)
-/** HP_SYSTEM_REDCY_ENA : R/W; bitpos: [0]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYSTEM_REDCY_ENA    (BIT(0))
-#define HP_SYSTEM_REDCY_ENA_M  (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
-#define HP_SYSTEM_REDCY_ENA_V  0x00000001U
-#define HP_SYSTEM_REDCY_ENA_S  0
-/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYSTEM_REDCY_RESULT    (BIT(1))
-#define HP_SYSTEM_REDCY_RESULT_M  (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
-#define HP_SYSTEM_REDCY_RESULT_V  0x00000001U
-#define HP_SYSTEM_REDCY_RESULT_S  1
-
-/** HP_SYSTEM_RND_ECO_LOW_REG register
- *  redcy eco low register.
- */
-#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4)
-/** HP_SYSTEM_REDCY_LOW : R/W; bitpos: [31:0]; default: 0;
- *  Only reserved for ECO.
- */
-#define HP_SYSTEM_REDCY_LOW    0xFFFFFFFFU
-#define HP_SYSTEM_REDCY_LOW_M  (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
-#define HP_SYSTEM_REDCY_LOW_V  0xFFFFFFFFU
-#define HP_SYSTEM_REDCY_LOW_S  0
-
-/** HP_SYSTEM_RND_ECO_HIGH_REG register
- *  redcy eco high register.
- */
-#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8)
-/** HP_SYSTEM_REDCY_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  Only reserved for ECO.
- */
-#define HP_SYSTEM_REDCY_HIGH    0xFFFFFFFFU
-#define HP_SYSTEM_REDCY_HIGH_M  (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
-#define HP_SYSTEM_REDCY_HIGH_V  0xFFFFFFFFU
-#define HP_SYSTEM_REDCY_HIGH_S  0
-
-/** HP_SYSTEM_CLOCK_GATE_REG register
- *  HP-SYSTEM clock gating configure register
- */
-#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8)
-/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to force on clock gating.
- */
-#define HP_SYSTEM_CLK_EN    (BIT(0))
-#define HP_SYSTEM_CLK_EN_M  (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)
-#define HP_SYSTEM_CLK_EN_V  0x00000001U
-#define HP_SYSTEM_CLK_EN_S  0
-
-/** HP_SYSTEM_DATE_REG register
- *  Date register.
- */
-#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
-/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 35689073;
- *  HP-SYSTEM date information/ HP-SYSTEM version information.
- */
-#define HP_SYSTEM_DATE    0x0FFFFFFFU
-#define HP_SYSTEM_DATE_M  (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
-#define HP_SYSTEM_DATE_V  0x0FFFFFFFU
-#define HP_SYSTEM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/hp_system_struct.h b/components/soc/esp32h2/include/soc/hp_system_struct.h
deleted file mode 100644
index 575349312bc..00000000000
--- a/components/soc/esp32h2/include/soc/hp_system_struct.h
+++ /dev/null
@@ -1,360 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of external_device_encrypt_decrypt_control register
- *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
- */
-typedef union {
-    struct {
-        /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
-         */
-        uint32_t enable_spi_manual_encrypt:1;
-        /** enable_download_db_encrypt : HRO; bitpos: [1]; default: 0;
-         *  reserved
-         */
-        uint32_t enable_download_db_encrypt:1;
-        /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
-         *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
-         */
-        uint32_t enable_download_g0cb_decrypt:1;
-        /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
-         *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
-         */
-        uint32_t enable_download_manual_encrypt:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_sys_external_device_encrypt_decrypt_control_reg_t;
-
-/** Type of sram_usage_conf register
- *  HP memory usage configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:10;
-        /** sram_usage : R/W; bitpos: [14:10]; default: 0;
-         *  0: cpu use hp-memory. 1: mac-dump accessing hp-memory.
-         */
-        uint32_t sram_usage:5;
-        uint32_t reserved_15:5;
-        /** mac_dump_alloc : R/W; bitpos: [24:20]; default: 0;
-         *  reserved.
-         */
-        uint32_t mac_dump_alloc:5;
-        uint32_t reserved_25:6;
-        /** cache_usage : HRO; bitpos: [31]; default: 0;
-         *  reserved
-         */
-        uint32_t cache_usage:1;
-    };
-    uint32_t val;
-} hp_sys_sram_usage_conf_reg_t;
-
-/** Type of sec_dpa_conf register
- *  HP anti-DPA security configuration register
- */
-typedef union {
-    struct {
-        /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
-         *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
-         *  the number, the stronger the ability to resist DPA attacks and the higher the
-         *  security level, but it will increase the computational overhead of the hardware
-         *  crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0.
-         */
-        uint32_t sec_dpa_level:2;
-        /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
-         *  This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
-         *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
-         */
-        uint32_t sec_dpa_cfg_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_sys_sec_dpa_conf_reg_t;
-
-/** Type of rom_table_lock register
- *  Rom-Table lock register
- */
-typedef union {
-    struct {
-        /** rom_table_lock : R/W; bitpos: [0]; default: 0;
-         *  XXXX
-         */
-        uint32_t rom_table_lock:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_sys_rom_table_lock_reg_t;
-
-/** Type of rom_table register
- *  Rom-Table register
- */
-typedef union {
-    struct {
-        /** rom_table : R/W; bitpos: [31:0]; default: 0;
-         *  XXXX
-         */
-        uint32_t rom_table:32;
-    };
-    uint32_t val;
-} hp_sys_rom_table_reg_t;
-
-/** Type of mem_test_conf register
- *  MEM_TEST configuration register
- */
-typedef union {
-    struct {
-        /** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
-         *  This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V
-         *  operating Voltage.
-         */
-        uint32_t hp_mem_wpulse:3;
-        /** hp_mem_wa : R/W; bitpos: [5:3]; default: 5;
-         *  This field controls hp system memory WA parameter. 0b100 for 1.1V operating
-         *  Voltage, 0b101 for 1.0V, 0b110 for 0.9V.
-         */
-        uint32_t hp_mem_wa:3;
-        /** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
-         *  This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating
-         *  Voltage, 0b01 for 0.9V.
-         */
-        uint32_t hp_mem_ra:2;
-        /** hp_mem_rm : R/W; bitpos: [11:8]; default: 2;
-         *  This field controls hp system memory RM parameter. 0b0011 for 1.1V operating
-         *  Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V.
-         */
-        uint32_t hp_mem_rm:4;
-        /** rom_rm : R/W; bitpos: [15:12]; default: 2;
-         *  This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for
-         *  1.0V, 0b0010(default) or 0b0001(slow) for 0.9V.
-         */
-        uint32_t rom_rm:4;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} hp_sys_mem_test_conf_reg_t;
-
-/** Type of clock_gate register
- *  HP-SYSTEM clock gating configure register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to force on clock gating.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_sys_clock_gate_reg_t;
-
-
-/** Group: Timeout Register */
-/** Type of cpu_peri_timeout_conf register
- *  CPU_PERI_TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
-         *  Set the timeout threshold for bus access, corresponding to the number of clock
-         *  cycles of the clock domain.
-         */
-        uint32_t cpu_peri_timeout_thres:16;
-        /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to clear timeout interrupt
-         */
-        uint32_t cpu_peri_timeout_int_clear:1;
-        /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
-         *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
-         *  registers
-         */
-        uint32_t cpu_peri_timeout_protect_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} hp_sys_cpu_peri_timeout_conf_reg_t;
-
-/** Type of cpu_peri_timeout_addr register
- *  CPU_PERI_TIMEOUT_ADDR register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  Record the address information of abnormal access
-         */
-        uint32_t cpu_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} hp_sys_cpu_peri_timeout_addr_reg_t;
-
-/** Type of cpu_peri_timeout_uid register
- *  CPU_PERI_TIMEOUT_UID register
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
-         *  will be cleared after the interrupt is cleared.
-         */
-        uint32_t cpu_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hp_sys_cpu_peri_timeout_uid_reg_t;
-
-/** Type of hp_peri_timeout_conf register
- *  HP_PERI_TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
-         *  Set the timeout threshold for bus access, corresponding to the number of clock
-         *  cycles of the clock domain.
-         */
-        uint32_t hp_peri_timeout_thres:16;
-        /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
-         *  Set this bit as 1 to clear timeout interrupt
-         */
-        uint32_t hp_peri_timeout_int_clear:1;
-        /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
-         *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
-         */
-        uint32_t hp_peri_timeout_protect_en:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} hp_sys_hp_peri_timeout_conf_reg_t;
-
-/** Type of hp_peri_timeout_addr register
- *  HP_PERI_TIMEOUT_ADDR register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
-         *  Record the address information of abnormal access
-         */
-        uint32_t hp_peri_timeout_addr:32;
-    };
-    uint32_t val;
-} hp_sys_hp_peri_timeout_addr_reg_t;
-
-/** Type of hp_peri_timeout_uid register
- *  HP_PERI_TIMEOUT_UID register
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
-         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
-         *  will be cleared after the interrupt is cleared.
-         */
-        uint32_t hp_peri_timeout_uid:7;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} hp_sys_hp_peri_timeout_uid_reg_t;
-
-
-/** Group: Redcy ECO Registers */
-/** Type of rnd_eco register
- *  redcy eco register.
- */
-typedef union {
-    struct {
-        /** redcy_ena : R/W; bitpos: [0]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_ena:1;
-        /** redcy_result : RO; bitpos: [1]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_sys_rnd_eco_reg_t;
-
-/** Type of rnd_eco_low register
- *  redcy eco low register.
- */
-typedef union {
-    struct {
-        /** redcy_low : R/W; bitpos: [31:0]; default: 0;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_low:32;
-    };
-    uint32_t val;
-} hp_sys_rnd_eco_low_reg_t;
-
-/** Type of rnd_eco_high register
- *  redcy eco high register.
- */
-typedef union {
-    struct {
-        /** redcy_high : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Only reserved for ECO.
-         */
-        uint32_t redcy_high:32;
-    };
-    uint32_t val;
-} hp_sys_rnd_eco_high_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35689073;
-         *  HP-SYSTEM date information/ HP-SYSTEM version information.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} hp_sys_date_reg_t;
-
-
-typedef struct {
-    volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
-    volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf;
-    volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf;
-    volatile hp_sys_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
-    volatile hp_sys_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
-    volatile hp_sys_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
-    volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
-    volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
-    volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
-    volatile hp_sys_rom_table_lock_reg_t rom_table_lock;
-    volatile hp_sys_rom_table_reg_t rom_table;
-    volatile hp_sys_mem_test_conf_reg_t mem_test_conf;
-    uint32_t reserved_030[236];
-    volatile hp_sys_rnd_eco_reg_t rnd_eco;
-    volatile hp_sys_rnd_eco_low_reg_t rnd_eco_low;
-    volatile hp_sys_rnd_eco_high_reg_t rnd_eco_high;
-    uint32_t reserved_3ec[3];
-    volatile hp_sys_clock_gate_reg_t clock_gate;
-    volatile hp_sys_date_reg_t date;
-} hp_sys_dev_t;
-
-extern hp_sys_dev_t HP_SYSTEM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hp_sys_dev_t) == 0x400, "Invalid size of hp_sys_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/i2s_reg.h b/components/soc/esp32h2/include/soc/i2s_reg.h
deleted file mode 100644
index b79bdd298c3..00000000000
--- a/components/soc/esp32h2/include/soc/i2s_reg.h
+++ /dev/null
@@ -1,1296 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** I2S_INT_RAW_REG register
- *  I2S interrupt raw register, valid in level.
- */
-#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
-/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_RAW    (BIT(0))
-#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
-#define I2S_RX_DONE_INT_RAW_V  0x00000001U
-#define I2S_RX_DONE_INT_RAW_S  0
-/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_RAW    (BIT(1))
-#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
-#define I2S_TX_DONE_INT_RAW_V  0x00000001U
-#define I2S_TX_DONE_INT_RAW_S  1
-/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_RAW    (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
-#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_RX_HUNG_INT_RAW_S  2
-/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_RAW    (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
-#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_TX_HUNG_INT_RAW_S  3
-
-/** I2S_INT_ST_REG register
- *  I2S interrupt status register.
- */
-#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
-/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ST    (BIT(0))
-#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
-#define I2S_RX_DONE_INT_ST_V  0x00000001U
-#define I2S_RX_DONE_INT_ST_S  0
-/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ST    (BIT(1))
-#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
-#define I2S_TX_DONE_INT_ST_V  0x00000001U
-#define I2S_TX_DONE_INT_ST_S  1
-/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ST    (BIT(2))
-#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
-#define I2S_RX_HUNG_INT_ST_V  0x00000001U
-#define I2S_RX_HUNG_INT_ST_S  2
-/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ST    (BIT(3))
-#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
-#define I2S_TX_HUNG_INT_ST_V  0x00000001U
-#define I2S_TX_HUNG_INT_ST_S  3
-
-/** I2S_INT_ENA_REG register
- *  I2S interrupt enable register.
- */
-#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
-/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ENA    (BIT(0))
-#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
-#define I2S_RX_DONE_INT_ENA_V  0x00000001U
-#define I2S_RX_DONE_INT_ENA_S  0
-/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ENA    (BIT(1))
-#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
-#define I2S_TX_DONE_INT_ENA_V  0x00000001U
-#define I2S_TX_DONE_INT_ENA_S  1
-/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ENA    (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
-#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_RX_HUNG_INT_ENA_S  2
-/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ENA    (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
-#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_TX_HUNG_INT_ENA_S  3
-
-/** I2S_INT_CLR_REG register
- *  I2S interrupt clear register.
- */
-#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
-/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_CLR    (BIT(0))
-#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
-#define I2S_RX_DONE_INT_CLR_V  0x00000001U
-#define I2S_RX_DONE_INT_CLR_S  0
-/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_CLR    (BIT(1))
-#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
-#define I2S_TX_DONE_INT_CLR_V  0x00000001U
-#define I2S_TX_DONE_INT_CLR_S  1
-/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_CLR    (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
-#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_RX_HUNG_INT_CLR_S  2
-/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_CLR    (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
-#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_TX_HUNG_INT_CLR_S  3
-
-/** I2S_RX_CONF_REG register
- *  I2S RX configure register
- */
-#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
-/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset receiver
- */
-#define I2S_RX_RESET    (BIT(0))
-#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
-#define I2S_RX_RESET_V  0x00000001U
-#define I2S_RX_RESET_S  0
-/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Rx AFIFO
- */
-#define I2S_RX_FIFO_RESET    (BIT(1))
-#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
-#define I2S_RX_FIFO_RESET_V  0x00000001U
-#define I2S_RX_FIFO_RESET_S  1
-/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start receiving data
- */
-#define I2S_RX_START    (BIT(2))
-#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
-#define I2S_RX_START_V  0x00000001U
-#define I2S_RX_START_S  2
-/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave receiver mode
- */
-#define I2S_RX_SLAVE_MOD    (BIT(3))
-#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
-#define I2S_RX_SLAVE_MOD_V  0x00000001U
-#define I2S_RX_SLAVE_MOD_S  3
-/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
- *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
- *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
- */
-#define I2S_RX_STOP_MODE    0x00000003U
-#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
-#define I2S_RX_STOP_MODE_V  0x00000003U
-#define I2S_RX_STOP_MODE_S  4
-/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable receiver  in mono mode
- */
-#define I2S_RX_MONO    (BIT(6))
-#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
-#define I2S_RX_MONO_V  0x00000001U
-#define I2S_RX_MONO_S  6
-/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
- */
-#define I2S_RX_BIG_ENDIAN    (BIT(7))
-#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
-#define I2S_RX_BIG_ENDIAN_V  0x00000001U
-#define I2S_RX_BIG_ENDIAN_S  7
-/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_RX_UPDATE    (BIT(8))
-#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
-#define I2S_RX_UPDATE_V  0x00000001U
-#define I2S_RX_UPDATE_S  8
-/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
- *  channel data value is valid in I2S RX mono mode.
- */
-#define I2S_RX_MONO_FST_VLD    (BIT(9))
-#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
-#define I2S_RX_MONO_FST_VLD_V  0x00000001U
-#define I2S_RX_MONO_FST_VLD_S  9
-/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
- *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_RX_PCM_CONF    0x00000003U
-#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
-#define I2S_RX_PCM_CONF_V  0x00000003U
-#define I2S_RX_PCM_CONF_S  10
-/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass Compress/Decompress module for received data.
- */
-#define I2S_RX_PCM_BYPASS    (BIT(12))
-#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
-#define I2S_RX_PCM_BYPASS_V  0x00000001U
-#define I2S_RX_PCM_BYPASS_S  12
-/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
- *  Set this bit to enable receiver in Phillips standard mode
- */
-#define I2S_RX_MSB_SHIFT    (BIT(13))
-#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
-#define I2S_RX_MSB_SHIFT_V  0x00000001U
-#define I2S_RX_MSB_SHIFT_S  13
-/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
- */
-#define I2S_RX_LEFT_ALIGN    (BIT(15))
-#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
-#define I2S_RX_LEFT_ALIGN_V  0x00000001U
-#define I2S_RX_LEFT_ALIGN_S  15
-/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
- */
-#define I2S_RX_24_FILL_EN    (BIT(16))
-#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
-#define I2S_RX_24_FILL_EN_V  0x00000001U
-#define I2S_RX_24_FILL_EN_S  16
-/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
- *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
- */
-#define I2S_RX_WS_IDLE_POL    (BIT(17))
-#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
-#define I2S_RX_WS_IDLE_POL_V  0x00000001U
-#define I2S_RX_WS_IDLE_POL_S  17
-/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
- *  is received first.
- */
-#define I2S_RX_BIT_ORDER    (BIT(18))
-#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
-#define I2S_RX_BIT_ORDER_V  0x00000001U
-#define I2S_RX_BIT_ORDER_S  18
-/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Rx mode . 0: Disable.
- */
-#define I2S_RX_TDM_EN    (BIT(19))
-#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
-#define I2S_RX_TDM_EN_V  0x00000001U
-#define I2S_RX_TDM_EN_S  19
-/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Rx mode . 0: Disable.
- */
-#define I2S_RX_PDM_EN    (BIT(20))
-#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
-#define I2S_RX_PDM_EN_V  0x00000001U
-#define I2S_RX_PDM_EN_S  20
-/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
- *  Bit clock configuration bits in receiver mode.
- */
-#define I2S_RX_BCK_DIV_NUM    0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
-#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_S  21
-
-/** I2S_TX_CONF_REG register
- *  I2S TX configure register
- */
-#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
-/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset transmitter
- */
-#define I2S_TX_RESET    (BIT(0))
-#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
-#define I2S_TX_RESET_V  0x00000001U
-#define I2S_TX_RESET_S  0
-/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Tx AFIFO
- */
-#define I2S_TX_FIFO_RESET    (BIT(1))
-#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
-#define I2S_TX_FIFO_RESET_V  0x00000001U
-#define I2S_TX_FIFO_RESET_S  1
-/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start transmitting data
- */
-#define I2S_TX_START    (BIT(2))
-#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
-#define I2S_TX_START_V  0x00000001U
-#define I2S_TX_START_S  2
-/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave transmitter mode
- */
-#define I2S_TX_SLAVE_MOD    (BIT(3))
-#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
-#define I2S_TX_SLAVE_MOD_V  0x00000001U
-#define I2S_TX_SLAVE_MOD_S  3
-/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
- */
-#define I2S_TX_STOP_EN    (BIT(4))
-#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
-#define I2S_TX_STOP_EN_V  0x00000001U
-#define I2S_TX_STOP_EN_S  4
-/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
- *  1: The value of Left channel data is equal to the value of right channel data in
- *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
- *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
- */
-#define I2S_TX_CHAN_EQUAL    (BIT(5))
-#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
-#define I2S_TX_CHAN_EQUAL_V  0x00000001U
-#define I2S_TX_CHAN_EQUAL_S  5
-/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable transmitter in mono mode
- */
-#define I2S_TX_MONO    (BIT(6))
-#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
-#define I2S_TX_MONO_V  0x00000001U
-#define I2S_TX_MONO_S  6
-/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
- *  value.
- */
-#define I2S_TX_BIG_ENDIAN    (BIT(7))
-#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
-#define I2S_TX_BIG_ENDIAN_V  0x00000001U
-#define I2S_TX_BIG_ENDIAN_S  7
-/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_TX_UPDATE    (BIT(8))
-#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
-#define I2S_TX_UPDATE_V  0x00000001U
-#define I2S_TX_UPDATE_S  8
-/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
- *  channel data value is valid in I2S TX mono mode.
- */
-#define I2S_TX_MONO_FST_VLD    (BIT(9))
-#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
-#define I2S_TX_MONO_FST_VLD_V  0x00000001U
-#define I2S_TX_MONO_FST_VLD_S  9
-/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
- *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_TX_PCM_CONF    0x00000003U
-#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
-#define I2S_TX_PCM_CONF_V  0x00000003U
-#define I2S_TX_PCM_CONF_S  10
-/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass  Compress/Decompress module for transmitted data.
- */
-#define I2S_TX_PCM_BYPASS    (BIT(12))
-#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
-#define I2S_TX_PCM_BYPASS_V  0x00000001U
-#define I2S_TX_PCM_BYPASS_S  12
-/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
- *  Set this bit to enable transmitter in Phillips standard mode
- */
-#define I2S_TX_MSB_SHIFT    (BIT(13))
-#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
-#define I2S_TX_MSB_SHIFT_V  0x00000001U
-#define I2S_TX_MSB_SHIFT_S  13
-/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
- *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
- *  generate pos/neg edge in master mode.
- */
-#define I2S_TX_BCK_NO_DLY    (BIT(14))
-#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
-#define I2S_TX_BCK_NO_DLY_V  0x00000001U
-#define I2S_TX_BCK_NO_DLY_S  14
-/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
- */
-#define I2S_TX_LEFT_ALIGN    (BIT(15))
-#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
-#define I2S_TX_LEFT_ALIGN_V  0x00000001U
-#define I2S_TX_LEFT_ALIGN_S  15
-/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
- */
-#define I2S_TX_24_FILL_EN    (BIT(16))
-#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
-#define I2S_TX_24_FILL_EN_V  0x00000001U
-#define I2S_TX_24_FILL_EN_S  16
-/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
- *  WS should be 1 when sending left channel data, and WS is 0in right channel.
- */
-#define I2S_TX_WS_IDLE_POL    (BIT(17))
-#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
-#define I2S_TX_WS_IDLE_POL_V  0x00000001U
-#define I2S_TX_WS_IDLE_POL_S  17
-/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
- *  sent first.
- */
-#define I2S_TX_BIT_ORDER    (BIT(18))
-#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
-#define I2S_TX_BIT_ORDER_V  0x00000001U
-#define I2S_TX_BIT_ORDER_S  18
-/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Tx mode . 0: Disable.
- */
-#define I2S_TX_TDM_EN    (BIT(19))
-#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
-#define I2S_TX_TDM_EN_V  0x00000001U
-#define I2S_TX_TDM_EN_S  19
-/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Tx mode . 0: Disable.
- */
-#define I2S_TX_PDM_EN    (BIT(20))
-#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
-#define I2S_TX_PDM_EN_V  0x00000001U
-#define I2S_TX_PDM_EN_S  20
-/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
- *  Bit clock configuration bits in transmitter mode.
- */
-#define I2S_TX_BCK_DIV_NUM    0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
-#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_S  21
-/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
- *  I2S transmitter channel mode configuration bits.
- */
-#define I2S_TX_CHAN_MOD    0x00000007U
-#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
-#define I2S_TX_CHAN_MOD_V  0x00000007U
-#define I2S_TX_CHAN_MOD_S  27
-/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
- *  Enable signal loop back mode with transmitter module and receiver module sharing
- *  the same WS and BCK signals.
- */
-#define I2S_SIG_LOOPBACK    (BIT(30))
-#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
-#define I2S_SIG_LOOPBACK_V  0x00000001U
-#define I2S_SIG_LOOPBACK_S  30
-
-/** I2S_RX_CONF1_REG register
- *  I2S RX configure register 1
- */
-#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
-/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
- *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
- *  T_bck
- */
-#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
-#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
-#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
-#define I2S_RX_TDM_WS_WIDTH_S  0
-/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
- *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_RX_BITS_MOD    0x0000001FU
-#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
-#define I2S_RX_BITS_MOD_V  0x0000001FU
-#define I2S_RX_BITS_MOD_S  14
-/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
- *  I2S Rx half sample bits -1.
- */
-#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
-#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
-#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
-#define I2S_RX_HALF_SAMPLE_BITS_S  19
-/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
- *  The Rx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
-#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_S  27
-
-/** I2S_TX_CONF1_REG register
- *  I2S TX configure register 1
- */
-#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
-/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
- *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
- *  T_bck
- */
-#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
-#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
-#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
-#define I2S_TX_TDM_WS_WIDTH_S  0
-/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
- *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_TX_BITS_MOD    0x0000001FU
-#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
-#define I2S_TX_BITS_MOD_V  0x0000001FU
-#define I2S_TX_BITS_MOD_S  14
-/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
- *  I2S Tx half sample bits -1.
- */
-#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
-#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
-#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
-#define I2S_TX_HALF_SAMPLE_BITS_S  19
-/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
- *  The Tx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
-#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_S  27
-
-/** I2S_RX_CLKM_CONF_REG register
- *  I2S RX clock configure register
- */
-#define I2S_RX_CLKM_CONF_REG (DR_REG_I2S_BASE + 0x30)
-/** I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
- *  Integral I2S clock divider value
- */
-#define I2S_RX_CLKM_DIV_NUM    0x000000FFU
-#define I2S_RX_CLKM_DIV_NUM_M  (I2S_RX_CLKM_DIV_NUM_V << I2S_RX_CLKM_DIV_NUM_S)
-#define I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
-#define I2S_RX_CLKM_DIV_NUM_S  0
-/** I2S_RX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0;
- *  I2S Rx module clock enable signal.
- */
-#define I2S_RX_CLK_ACTIVE    (BIT(26))
-#define I2S_RX_CLK_ACTIVE_M  (I2S_RX_CLK_ACTIVE_V << I2S_RX_CLK_ACTIVE_S)
-#define I2S_RX_CLK_ACTIVE_V  0x00000001U
-#define I2S_RX_CLK_ACTIVE_S  26
-/** I2S_RX_CLK_SEL : R/W; bitpos: [28:27]; default: 0;
- *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
- */
-#define I2S_RX_CLK_SEL    0x00000003U
-#define I2S_RX_CLK_SEL_M  (I2S_RX_CLK_SEL_V << I2S_RX_CLK_SEL_S)
-#define I2S_RX_CLK_SEL_V  0x00000003U
-#define I2S_RX_CLK_SEL_S  27
-/** I2S_MCLK_SEL : R/W; bitpos: [29]; default: 0;
- *  0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as
- *  I2S_MCLK_OUT.
- */
-#define I2S_MCLK_SEL    (BIT(29))
-#define I2S_MCLK_SEL_M  (I2S_MCLK_SEL_V << I2S_MCLK_SEL_S)
-#define I2S_MCLK_SEL_V  0x00000001U
-#define I2S_MCLK_SEL_S  29
-
-/** I2S_TX_CLKM_CONF_REG register
- *  I2S TX clock configure register
- */
-#define I2S_TX_CLKM_CONF_REG (DR_REG_I2S_BASE + 0x34)
-/** I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
- *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
- *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
- *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
- *  (n+1)-div] + y * (n+1)-div.
- */
-#define I2S_TX_CLKM_DIV_NUM    0x000000FFU
-#define I2S_TX_CLKM_DIV_NUM_M  (I2S_TX_CLKM_DIV_NUM_V << I2S_TX_CLKM_DIV_NUM_S)
-#define I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
-#define I2S_TX_CLKM_DIV_NUM_S  0
-/** I2S_TX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0;
- *  I2S Tx module clock enable signal.
- */
-#define I2S_TX_CLK_ACTIVE    (BIT(26))
-#define I2S_TX_CLK_ACTIVE_M  (I2S_TX_CLK_ACTIVE_V << I2S_TX_CLK_ACTIVE_S)
-#define I2S_TX_CLK_ACTIVE_V  0x00000001U
-#define I2S_TX_CLK_ACTIVE_S  26
-/** I2S_TX_CLK_SEL : R/W; bitpos: [28:27]; default: 0;
- *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
- *  I2S_MCLK_in.
- */
-#define I2S_TX_CLK_SEL    0x00000003U
-#define I2S_TX_CLK_SEL_M  (I2S_TX_CLK_SEL_V << I2S_TX_CLK_SEL_S)
-#define I2S_TX_CLK_SEL_V  0x00000003U
-#define I2S_TX_CLK_SEL_S  27
-/** I2S_CLK_EN : R/W; bitpos: [29]; default: 0;
- *  Set this bit to enable clk gate
- */
-#define I2S_CLK_EN    (BIT(29))
-#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
-#define I2S_CLK_EN_V  0x00000001U
-#define I2S_CLK_EN_S  29
-
-/** I2S_RX_CLKM_DIV_CONF_REG register
- *  I2S RX module clock divider configure register
- */
-#define I2S_RX_CLKM_DIV_CONF_REG (DR_REG_I2S_BASE + 0x38)
-/** I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Z is (a-b).
- */
-#define I2S_RX_CLKM_DIV_Z    0x000001FFU
-#define I2S_RX_CLKM_DIV_Z_M  (I2S_RX_CLKM_DIV_Z_V << I2S_RX_CLKM_DIV_Z_S)
-#define I2S_RX_CLKM_DIV_Z_V  0x000001FFU
-#define I2S_RX_CLKM_DIV_Z_S  0
-/** I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define I2S_RX_CLKM_DIV_Y    0x000001FFU
-#define I2S_RX_CLKM_DIV_Y_M  (I2S_RX_CLKM_DIV_Y_V << I2S_RX_CLKM_DIV_Y_S)
-#define I2S_RX_CLKM_DIV_Y_V  0x000001FFU
-#define I2S_RX_CLKM_DIV_Y_S  9
-/** I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define I2S_RX_CLKM_DIV_X    0x000001FFU
-#define I2S_RX_CLKM_DIV_X_M  (I2S_RX_CLKM_DIV_X_V << I2S_RX_CLKM_DIV_X_S)
-#define I2S_RX_CLKM_DIV_X_V  0x000001FFU
-#define I2S_RX_CLKM_DIV_X_S  18
-/** I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_YN1 is 1.
- */
-#define I2S_RX_CLKM_DIV_YN1    (BIT(27))
-#define I2S_RX_CLKM_DIV_YN1_M  (I2S_RX_CLKM_DIV_YN1_V << I2S_RX_CLKM_DIV_YN1_S)
-#define I2S_RX_CLKM_DIV_YN1_V  0x00000001U
-#define I2S_RX_CLKM_DIV_YN1_S  27
-
-/** I2S_TX_CLKM_DIV_CONF_REG register
- *  I2S TX module clock divider configure register
- */
-#define I2S_TX_CLKM_DIV_CONF_REG (DR_REG_I2S_BASE + 0x3c)
-/** I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Z is (a-b).
- */
-#define I2S_TX_CLKM_DIV_Z    0x000001FFU
-#define I2S_TX_CLKM_DIV_Z_M  (I2S_TX_CLKM_DIV_Z_V << I2S_TX_CLKM_DIV_Z_S)
-#define I2S_TX_CLKM_DIV_Z_V  0x000001FFU
-#define I2S_TX_CLKM_DIV_Z_S  0
-/** I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define I2S_TX_CLKM_DIV_Y    0x000001FFU
-#define I2S_TX_CLKM_DIV_Y_M  (I2S_TX_CLKM_DIV_Y_V << I2S_TX_CLKM_DIV_Y_S)
-#define I2S_TX_CLKM_DIV_Y_V  0x000001FFU
-#define I2S_TX_CLKM_DIV_Y_S  9
-/** I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define I2S_TX_CLKM_DIV_X    0x000001FFU
-#define I2S_TX_CLKM_DIV_X_M  (I2S_TX_CLKM_DIV_X_V << I2S_TX_CLKM_DIV_X_S)
-#define I2S_TX_CLKM_DIV_X_V  0x000001FFU
-#define I2S_TX_CLKM_DIV_X_S  18
-/** I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_YN1 is 1.
- */
-#define I2S_TX_CLKM_DIV_YN1    (BIT(27))
-#define I2S_TX_CLKM_DIV_YN1_M  (I2S_TX_CLKM_DIV_YN1_V << I2S_TX_CLKM_DIV_YN1_S)
-#define I2S_TX_CLKM_DIV_YN1_V  0x00000001U
-#define I2S_TX_CLKM_DIV_YN1_S  27
-
-/** I2S_TX_PCM2PDM_CONF_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40)
-/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0;
- *  I2S TX PDM bypass hp filter or not. The option has been removed.
- */
-#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
-#define I2S_TX_PDM_HP_BYPASS_M  (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S)
-#define I2S_TX_PDM_HP_BYPASS_V  0x00000001U
-#define I2S_TX_PDM_HP_BYPASS_S  0
-/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
- *  I2S TX PDM OSR2 value
- */
-#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
-#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_S  1
-/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
- *  I2S TX PDM prescale for sigmadelta
- */
-#define I2S_TX_PDM_PRESCALE    0x000000FFU
-#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
-#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
-#define I2S_TX_PDM_PRESCALE_S  5
-/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
-#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_S  13
-/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
-#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_S  15
-/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
-#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
-/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
-/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
- *  I2S TX PDM sigmadelta dither2 value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
-/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
- *  I2S TX PDM sigmadelta dither value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
-/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
- *  I2S TX PDM dac mode enable
- */
-#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
-#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_2OUT_EN_S  23
-/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
- *  I2S TX PDM dac 2channel enable
- */
-#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
-#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_MODE_EN_S  24
-/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
- *  I2S TX PDM Converter enable
- */
-#define I2S_PCM2PDM_CONV_EN    (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
-#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
-#define I2S_PCM2PDM_CONV_EN_S  25
-
-/** I2S_TX_PCM2PDM_CONF1_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44)
-/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
- *  I2S TX PDM Fp
- */
-#define I2S_TX_PDM_FP    0x000003FFU
-#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
-#define I2S_TX_PDM_FP_V  0x000003FFU
-#define I2S_TX_PDM_FP_S  0
-/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
- *  I2S TX PDM Fs
- */
-#define I2S_TX_PDM_FS    0x000003FFU
-#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
-#define I2S_TX_PDM_FS_V  0x000003FFU
-#define I2S_TX_PDM_FS_S  10
-/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
- *  I2S_TX_IIR_HP_MULT12_5[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
-#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_S  20
-/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
- *  I2S_TX_IIR_HP_MULT12_0[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
-#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_S  23
-
-/** I2S_RX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
-/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
-#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
-/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
-#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
-/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
-#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
-/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
-#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
-/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
-#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
-/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
-#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
-/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
-#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
-/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
-#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
-/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
-#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN8_EN_S  8
-/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
-#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN9_EN_S  9
-/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
-#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN10_EN_S  10
-/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
-#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN11_EN_S  11
-/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
-#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN12_EN_S  12
-/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
-#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN13_EN_S  13
-/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
-#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN14_EN_S  14
-/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
-#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN15_EN_S  15
-/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
-#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
-
-/** I2S_TX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
-/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
-#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN0_EN_S  0
-/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
-#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN1_EN_S  1
-/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
-#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN2_EN_S  2
-/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
-#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN3_EN_S  3
-/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
-#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN4_EN_S  4
-/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
-#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN5_EN_S  5
-/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
-#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN6_EN_S  6
-/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
-#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN7_EN_S  7
-/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
-#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN8_EN_S  8
-/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
-#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN9_EN_S  9
-/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
-#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN10_EN_S  10
-/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
-#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN11_EN_S  11
-/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
-#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN12_EN_S  12
-/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
-#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN13_EN_S  13
-/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
-#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN14_EN_S  14
-/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
-#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN15_EN_S  15
-/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
-#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
-/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
- *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
- *  only the data of the enabled channels is sent, then this bit should be set. Clear
- *  it when all the data stored in DMA TX buffer is for enabled channels.
- */
-#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
-#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
-#define I2S_TX_TDM_SKIP_MSK_EN_S  20
-
-/** I2S_RX_TIMING_REG register
- *  I2S RX timing control register
- */
-#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
-/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD_IN_DM    0x00000003U
-#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
-#define I2S_RX_SD_IN_DM_V  0x00000003U
-#define I2S_RX_SD_IN_DM_S  0
-/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_OUT_DM    0x00000003U
-#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
-#define I2S_RX_WS_OUT_DM_V  0x00000003U
-#define I2S_RX_WS_OUT_DM_S  16
-/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_OUT_DM    0x00000003U
-#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
-#define I2S_RX_BCK_OUT_DM_V  0x00000003U
-#define I2S_RX_BCK_OUT_DM_S  20
-/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_IN_DM    0x00000003U
-#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
-#define I2S_RX_WS_IN_DM_V  0x00000003U
-#define I2S_RX_WS_IN_DM_S  24
-/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_IN_DM    0x00000003U
-#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
-#define I2S_RX_BCK_IN_DM_V  0x00000003U
-#define I2S_RX_BCK_IN_DM_S  28
-
-/** I2S_TX_TIMING_REG register
- *  I2S TX timing control register
- */
-#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
-/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD_OUT_DM    0x00000003U
-#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
-#define I2S_TX_SD_OUT_DM_V  0x00000003U
-#define I2S_TX_SD_OUT_DM_S  0
-/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
- *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD1_OUT_DM    0x00000003U
-#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
-#define I2S_TX_SD1_OUT_DM_V  0x00000003U
-#define I2S_TX_SD1_OUT_DM_S  4
-/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_OUT_DM    0x00000003U
-#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
-#define I2S_TX_WS_OUT_DM_V  0x00000003U
-#define I2S_TX_WS_OUT_DM_S  16
-/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_OUT_DM    0x00000003U
-#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
-#define I2S_TX_BCK_OUT_DM_V  0x00000003U
-#define I2S_TX_BCK_OUT_DM_S  20
-/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_IN_DM    0x00000003U
-#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
-#define I2S_TX_WS_IN_DM_V  0x00000003U
-#define I2S_TX_WS_IN_DM_S  24
-/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_IN_DM    0x00000003U
-#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
-#define I2S_TX_BCK_IN_DM_V  0x00000003U
-#define I2S_TX_BCK_IN_DM_S  28
-
-/** I2S_LC_HUNG_CONF_REG register
- *  I2S HUNG configure register.
- */
-#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
-/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
- *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
- *  when fifo hung counter is equal to this value
- */
-#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
-#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_S  0
-/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
- *  The bits are used to scale tick counter threshold. The tick counter is reset when
- *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
- */
-#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
-/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
- *  The enable bit for FIFO timeout
- */
-#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
-#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
-#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
-
-/** I2S_RXEOF_NUM_REG register
- *  I2S RX data number control register.
- */
-#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
-/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
- *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
- *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
- */
-#define I2S_RX_EOF_NUM    0x00000FFFU
-#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
-#define I2S_RX_EOF_NUM_V  0x00000FFFU
-#define I2S_RX_EOF_NUM_S  0
-
-/** I2S_CONF_SIGLE_DATA_REG register
- *  I2S signal data register
- */
-#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
-/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
- *  The configured constant channel data to be sent out.
- */
-#define I2S_SINGLE_DATA    0xFFFFFFFFU
-#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
-#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
-#define I2S_SINGLE_DATA_S  0
-
-/** I2S_STATE_REG register
- *  I2S TX status register
- */
-#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
-/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
- *  1: i2s_tx is idle state. 0: i2s_tx is working.
- */
-#define I2S_TX_IDLE    (BIT(0))
-#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
-#define I2S_TX_IDLE_V  0x00000001U
-#define I2S_TX_IDLE_S  0
-
-/** I2S_ETM_CONF_REG register
- *  I2S ETM configure register
- */
-#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
-/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
- *  I2S ETM send x words event. When sending word number of
- *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
-#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_S  0
-/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
- *  I2S ETM receive x words event. When receiving word number of
- *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
-
-/** I2S_DATE_REG register
- *  Version control register
- */
-#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80)
-/** I2S_DATE : R/W; bitpos: [27:0]; default: 35684944;
- *  I2S version control register
- */
-#define I2S_DATE    0x0FFFFFFFU
-#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
-#define I2S_DATE_V  0x0FFFFFFFU
-#define I2S_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/i2s_struct.h b/components/soc/esp32h2/include/soc/i2s_struct.h
deleted file mode 100644
index 34f876838f8..00000000000
--- a/components/soc/esp32h2/include/soc/i2s_struct.h
+++ /dev/null
@@ -1,900 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  I2S interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_raw:1;
-        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_raw:1;
-        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_raw:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_raw_reg_t;
-
-/** Type of int_st register
- *  I2S interrupt status register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_st:1;
-        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_st:1;
-        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_st:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_st_reg_t;
-
-/** Type of int_ena register
- *  I2S interrupt enable register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_ena:1;
-        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_ena_reg_t;
-
-/** Type of int_clr register
- *  I2S interrupt clear register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_clr:1;
-        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_clr:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of rx_conf register
- *  I2S RX configure register
- */
-typedef union {
-    struct {
-        /** rx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset receiver
-         */
-        uint32_t rx_reset:1;
-        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Rx AFIFO
-         */
-        uint32_t rx_fifo_reset:1;
-        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start receiving data
-         */
-        uint32_t rx_start:1;
-        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave receiver mode
-         */
-        uint32_t rx_slave_mod:1;
-        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
-         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
-         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-         */
-        uint32_t rx_stop_mode:2;
-        /** rx_mono : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable receiver  in mono mode
-         */
-        uint32_t rx_mono:1;
-        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-         */
-        uint32_t rx_big_endian:1;
-        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t rx_update:1;
-        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
-         *  channel data value is valid in I2S RX mono mode.
-         */
-        uint32_t rx_mono_fst_vld:1;
-        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
-         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t rx_pcm_conf:2;
-        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass Compress/Decompress module for received data.
-         */
-        uint32_t rx_pcm_bypass:1;
-        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to enable receiver in Phillips standard mode
-         */
-        uint32_t rx_msb_shift:1;
-        uint32_t reserved_14:1;
-        /** rx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-         */
-        uint32_t rx_left_align:1;
-        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-         */
-        uint32_t rx_24_fill_en:1;
-        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
-         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-         */
-        uint32_t rx_ws_idle_pol:1;
-        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
-         *  is received first.
-         */
-        uint32_t rx_bit_order:1;
-        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_tdm_en:1;
-        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_pdm_en:1;
-        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
-         *  Bit clock configuration bits in receiver mode.
-         */
-        uint32_t rx_bck_div_num:6;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} i2s_rx_conf_reg_t;
-
-/** Type of rx_conf1 register
- *  I2S RX configure register 1
- */
-typedef union {
-    struct {
-        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
-         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
-         *  T_bck
-         */
-        uint32_t rx_tdm_ws_width:9;
-        uint32_t reserved_9:5;
-        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
-         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t rx_bits_mod:5;
-        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
-         *  I2S Rx half sample bits -1.
-         */
-        uint32_t rx_half_sample_bits:8;
-        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
-         *  The Rx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t rx_tdm_chan_bits:5;
-    };
-    uint32_t val;
-} i2s_rx_conf1_reg_t;
-
-/** Type of tx_pcm2pdm_conf register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
-         *  I2S TX PDM bypass hp filter or not. The option has been removed.
-         */
-        uint32_t tx_pdm_hp_bypass:1;
-        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
-         *  I2S TX PDM OSR2 value
-         */
-        uint32_t tx_pdm_sinc_osr2:4;
-        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
-         *  I2S TX PDM prescale for sigmadelta
-         */
-        uint32_t tx_pdm_prescale:8;
-        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_hp_in_shift:2;
-        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_lp_in_shift:2;
-        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sinc_in_shift:2;
-        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sigmadelta_in_shift:2;
-        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
-         *  I2S TX PDM sigmadelta dither2 value
-         */
-        uint32_t tx_pdm_sigmadelta_dither2:1;
-        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
-         *  I2S TX PDM sigmadelta dither value
-         */
-        uint32_t tx_pdm_sigmadelta_dither:1;
-        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
-         *  I2S TX PDM dac mode enable
-         */
-        uint32_t tx_pdm_dac_2out_en:1;
-        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
-         *  I2S TX PDM dac 2channel enable
-         */
-        uint32_t tx_pdm_dac_mode_en:1;
-        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
-         *  I2S TX PDM Converter enable
-         */
-        uint32_t pcm2pdm_conv_en:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf_reg_t;
-
-/** Type of tx_pcm2pdm_conf1 register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
-         *  I2S TX PDM Fp
-         */
-        uint32_t tx_pdm_fp:10;
-        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
-         *  I2S TX PDM Fs
-         */
-        uint32_t tx_pdm_fs:10;
-        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_5[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_5:3;
-        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_0[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_0:3;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf1_reg_t;
-
-/** Type of rx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan0_en:1;
-        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan1_en:1;
-        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan2_en:1;
-        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan3_en:1;
-        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan4_en:1;
-        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan5_en:1;
-        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan6_en:1;
-        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan7_en:1;
-        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan8_en:1;
-        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan9_en:1;
-        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan10_en:1;
-        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan11_en:1;
-        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan12_en:1;
-        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan13_en:1;
-        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan14_en:1;
-        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan15_en:1;
-        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t rx_tdm_tot_chan_num:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_rx_tdm_ctrl_reg_t;
-
-/** Type of rx_eof_num register
- *  I2S RX data number control register.
- */
-typedef union {
-    struct {
-        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
-         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
-         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
-         */
-        uint32_t rx_eof_num:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_rx_eof_num_reg_t;
-
-
-/** Group: TX Control and configuration registers */
-/** Type of tx_conf register
- *  I2S TX configure register
- */
-typedef union {
-    struct {
-        /** tx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset transmitter
-         */
-        uint32_t tx_reset:1;
-        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Tx AFIFO
-         */
-        uint32_t tx_fifo_reset:1;
-        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start transmitting data
-         */
-        uint32_t tx_start:1;
-        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave transmitter mode
-         */
-        uint32_t tx_slave_mod:1;
-        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
-         */
-        uint32_t tx_stop_en:1;
-        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
-         *  1: The value of Left channel data is equal to the value of right channel data in
-         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
-         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-         */
-        uint32_t tx_chan_equal:1;
-        /** tx_mono : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable transmitter in mono mode
-         */
-        uint32_t tx_mono:1;
-        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
-         *  value.
-         */
-        uint32_t tx_big_endian:1;
-        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t tx_update:1;
-        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
-         *  channel data value is valid in I2S TX mono mode.
-         */
-        uint32_t tx_mono_fst_vld:1;
-        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
-         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t tx_pcm_conf:2;
-        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
-         */
-        uint32_t tx_pcm_bypass:1;
-        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to enable transmitter in Phillips standard mode
-         */
-        uint32_t tx_msb_shift:1;
-        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
-         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
-         *  generate pos/neg edge in master mode.
-         */
-        uint32_t tx_bck_no_dly:1;
-        /** tx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-         */
-        uint32_t tx_left_align:1;
-        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-         */
-        uint32_t tx_24_fill_en:1;
-        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
-         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
-         */
-        uint32_t tx_ws_idle_pol:1;
-        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
-         *  sent first.
-         */
-        uint32_t tx_bit_order:1;
-        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_tdm_en:1;
-        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_pdm_en:1;
-        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
-         *  Bit clock configuration bits in transmitter mode.
-         */
-        uint32_t tx_bck_div_num:6;
-        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
-         *  I2S transmitter channel mode configuration bits.
-         */
-        uint32_t tx_chan_mod:3;
-        /** sig_loopback : R/W; bitpos: [30]; default: 0;
-         *  Enable signal loop back mode with transmitter module and receiver module sharing
-         *  the same WS and BCK signals.
-         */
-        uint32_t sig_loopback:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} i2s_tx_conf_reg_t;
-
-/** Type of tx_conf1 register
- *  I2S TX configure register 1
- */
-typedef union {
-    struct {
-        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
-         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
-         *  T_bck
-         */
-        uint32_t tx_tdm_ws_width:9;
-        uint32_t reserved_9:5;
-        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
-         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t tx_bits_mod:5;
-        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
-         *  I2S Tx half sample bits -1.
-         */
-        uint32_t tx_half_sample_bits:8;
-        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
-         *  The Tx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t tx_tdm_chan_bits:5;
-    };
-    uint32_t val;
-} i2s_tx_conf1_reg_t;
-
-/** Type of tx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan0_en:1;
-        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan1_en:1;
-        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan2_en:1;
-        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan3_en:1;
-        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan4_en:1;
-        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan5_en:1;
-        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan6_en:1;
-        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan7_en:1;
-        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan8_en:1;
-        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan9_en:1;
-        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan10_en:1;
-        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan11_en:1;
-        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan12_en:1;
-        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan13_en:1;
-        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan14_en:1;
-        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan15_en:1;
-        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t tx_tdm_tot_chan_num:4;
-        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
-         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
-         *  only the data of the enabled channels is sent, then this bit should be set. Clear
-         *  it when all the data stored in DMA TX buffer is for enabled channels.
-         */
-        uint32_t tx_tdm_skip_msk_en:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} i2s_tx_tdm_ctrl_reg_t;
-
-
-/** Group: RX clock and timing registers */
-/** Type of rx_timing register
- *  I2S RX timing control register
- */
-typedef union {
-    struct {
-        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd_in_dm:2;
-        uint32_t reserved_2:14;
-        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_rx_timing_reg_t;
-
-
-/** Group: TX clock and timing registers */
-/** Type of tx_timing register
- *  I2S TX timing control register
- */
-typedef union {
-    struct {
-        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd_out_dm:2;
-        uint32_t reserved_2:2;
-        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
-         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd1_out_dm:2;
-        uint32_t reserved_6:10;
-        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_tx_timing_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of lc_hung_conf register
- *  I2S HUNG configure register.
- */
-typedef union {
-    struct {
-        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
-         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
-         *  when fifo hung counter is equal to this value
-         */
-        uint32_t lc_fifo_timeout:8;
-        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
-         *  The bits are used to scale tick counter threshold. The tick counter is reset when
-         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-         */
-        uint32_t lc_fifo_timeout_shift:3;
-        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
-         *  The enable bit for FIFO timeout
-         */
-        uint32_t lc_fifo_timeout_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_lc_hung_conf_reg_t;
-
-/** Type of conf_single_data register
- *  I2S signal data register
- */
-typedef union {
-    struct {
-        /** single_data : R/W; bitpos: [31:0]; default: 0;
-         *  The configured constant channel data to be sent out.
-         */
-        uint32_t single_data:32;
-    };
-    uint32_t val;
-} i2s_conf_single_data_reg_t;
-
-
-/** Group: TX status registers */
-/** Type of state register
- *  I2S TX status register
- */
-typedef union {
-    struct {
-        /** tx_idle : RO; bitpos: [0]; default: 1;
-         *  1: i2s_tx is idle state. 0: i2s_tx is working.
-         */
-        uint32_t tx_idle:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} i2s_state_reg_t;
-
-
-/** Group: ETM registers */
-/** Type of etm_conf register
- *  I2S ETM configure register
- */
-typedef union {
-    struct {
-        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
-         *  I2S ETM send x words event. When sending word number of
-         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_tx_send_word_num:10;
-        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
-         *  I2S ETM receive x words event. When receiving word number of
-         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_rx_receive_word_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_etm_conf_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35684944;
-         *  I2S version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} i2s_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000[3];
-    volatile i2s_int_raw_reg_t int_raw;
-    volatile i2s_int_st_reg_t int_st;
-    volatile i2s_int_ena_reg_t int_ena;
-    volatile i2s_int_clr_reg_t int_clr;
-    uint32_t reserved_01c;
-    volatile i2s_rx_conf_reg_t rx_conf;
-    volatile i2s_tx_conf_reg_t tx_conf;
-    volatile i2s_rx_conf1_reg_t rx_conf1;
-    volatile i2s_tx_conf1_reg_t tx_conf1;
-    uint32_t reserved_030[4];
-    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
-    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
-    uint32_t reserved_048[2];
-    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
-    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
-    volatile i2s_rx_timing_reg_t rx_timing;
-    volatile i2s_tx_timing_reg_t tx_timing;
-    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
-    volatile i2s_rx_eof_num_reg_t rx_eof_num;
-    volatile i2s_conf_single_data_reg_t conf_single_data;
-    volatile i2s_state_reg_t state;
-    volatile i2s_etm_conf_reg_t etm_conf;
-    uint32_t reserved_074[3];
-    volatile i2s_date_reg_t date;
-} i2s_dev_t;
-
-extern i2s_dev_t I2S0;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/interrupt_matrix_reg.h b/components/soc/esp32h2/include/soc/interrupt_matrix_reg.h
deleted file mode 100644
index 26f76cfb8eb..00000000000
--- a/components/soc/esp32h2/include/soc/interrupt_matrix_reg.h
+++ /dev/null
@@ -1,856 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-// #include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** INTMTX_CORE0_PMU_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
-/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_PMU_INTR mapping register
- */
-#define INTMTX_CORE0_PMU_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PMU_INTR_MAP_M  (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
-#define INTMTX_CORE0_PMU_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PMU_INTR_MAP_S  0
-
-/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
-/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_EFUSE_INTR mapping register
- */
-#define INTMTX_CORE0_EFUSE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_EFUSE_INTR_MAP_M  (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
-#define INTMTX_CORE0_EFUSE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_EFUSE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
-/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_LP_RTC_TIMER_INTR mapping register
- */
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
-/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_LP_BLE_TIMER_INTR mapping register
- */
-#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
-/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_LP_WDT_INTR mapping register
- */
-#define INTMTX_CORE0_LP_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_M  (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
-/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_LP_PERI_TIMEOUT_INTR mapping register
- */
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
-/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_LP_APM_M0_INTR mapping register
- */
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_CPU_INTR_FROM_CPU_0 mapping register
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_CPU_INTR_FROM_CPU_1 mapping register
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_CPU_INTR_FROM_CPU_2 mapping register
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
-
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
-/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_CPU_INTR_FROM_CPU_3 mapping register
- */
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
-
-/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
-/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_ASSIST_DEBUG_INTR mapping register
- */
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M  (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
-/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_TRACE_INTR mapping register
- */
-#define INTMTX_CORE0_TRACE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TRACE_INTR_MAP_M  (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
-#define INTMTX_CORE0_TRACE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TRACE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
-/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_CACHE_INTR mapping register
- */
-#define INTMTX_CORE0_CACHE_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CACHE_INTR_MAP_M  (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
-#define INTMTX_CORE0_CACHE_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CACHE_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
-/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_CPU_PERI_TIMEOUT_INTR mapping register
- */
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
-/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_BT_MAC_INTR mapping register
- */
-#define INTMTX_CORE0_BT_MAC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_M  (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_MAC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
-/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_BT_BB_INTR mapping register
- */
-#define INTMTX_CORE0_BT_BB_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_BB_INTR_MAP_M  (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
-#define INTMTX_CORE0_BT_BB_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_BB_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
-/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_BT_BB_NMI mapping register
- */
-#define INTMTX_CORE0_BT_BB_NMI_MAP    0x0000001FU
-#define INTMTX_CORE0_BT_BB_NMI_MAP_M  (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
-#define INTMTX_CORE0_BT_BB_NMI_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BT_BB_NMI_MAP_S  0
-
-/** INTMTX_CORE0_COEX_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
-/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_COEX_INTR mapping register
- */
-#define INTMTX_CORE0_COEX_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_COEX_INTR_MAP_M  (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
-#define INTMTX_CORE0_COEX_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_COEX_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
-/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_BLE_TIMER_INTR mapping register
- */
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M  (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S  0
-
-/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
-/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_BLE_SEC_INTR mapping register
- */
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M  (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
-/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_ZB_MAC_INTR mapping register
- */
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M  (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_GPIO_INTERRUPT_PRO mapping register
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
-
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
-/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_GPIO_INTERRUPT_PRO_NMI mapping register
- */
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
-
-/** INTMTX_CORE0_PAU_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
-/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_PAU_INTR mapping register
- */
-#define INTMTX_CORE0_PAU_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PAU_INTR_MAP_M  (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
-#define INTMTX_CORE0_PAU_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PAU_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
-/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_HP_PERI_TIMEOUT_INTR mapping register
- */
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
-/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_HP_APM_M0_INTR mapping register
- */
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
-/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_HP_APM_M1_INTR mapping register
- */
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
-/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_HP_APM_M2_INTR mapping register
- */
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
-/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_HP_APM_M3_INTR mapping register
- */
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S  0
-
-/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
-/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_MSPI_INTR mapping register
- */
-#define INTMTX_CORE0_MSPI_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_MSPI_INTR_MAP_M  (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
-#define INTMTX_CORE0_MSPI_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_MSPI_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2S1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
-/** INTMTX_CORE0_I2S1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_I2S1_INTR mapping register
- */
-#define INTMTX_CORE0_I2S1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2S1_INTR_MAP_M  (INTMTX_CORE0_I2S1_INTR_MAP_V << INTMTX_CORE0_I2S1_INTR_MAP_S)
-#define INTMTX_CORE0_I2S1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2S1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
-/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_UHCI0_INTR mapping register
- */
-#define INTMTX_CORE0_UHCI0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UHCI0_INTR_MAP_M  (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
-#define INTMTX_CORE0_UHCI0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UHCI0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UART0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
-/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_UART0_INTR mapping register
- */
-#define INTMTX_CORE0_UART0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UART0_INTR_MAP_M  (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
-#define INTMTX_CORE0_UART0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UART0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_UART1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
-/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_UART1_INTR mapping register
- */
-#define INTMTX_CORE0_UART1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_UART1_INTR_MAP_M  (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
-#define INTMTX_CORE0_UART1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_UART1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
-/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_LEDC_INTR mapping register
- */
-#define INTMTX_CORE0_LEDC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_LEDC_INTR_MAP_M  (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
-#define INTMTX_CORE0_LEDC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_LEDC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
-/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_CAN0_INTR mapping register
- */
-#define INTMTX_CORE0_CAN0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_CAN0_INTR_MAP_M  (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
-#define INTMTX_CORE0_CAN0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_CAN0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_USB_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
-/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_USB_INTR mapping register
- */
-#define INTMTX_CORE0_USB_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_USB_INTR_MAP_M  (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
-#define INTMTX_CORE0_USB_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_USB_INTR_MAP_S  0
-
-/** INTMTX_CORE0_RMT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
-/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_RMT_INTR mapping register
- */
-#define INTMTX_CORE0_RMT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_RMT_INTR_MAP_M  (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
-#define INTMTX_CORE0_RMT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_RMT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
-/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_I2C_EXT0_INTR mapping register
- */
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M  (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
-/** INTMTX_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_I2C_EXT1_INTR mapping register
- */
-#define INTMTX_CORE0_I2C_EXT1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_M  (INTMTX_CORE0_I2C_EXT1_INTR_MAP_V << INTMTX_CORE0_I2C_EXT1_INTR_MAP_S)
-#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
-/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_TG0_T0_INTR mapping register
- */
-#define INTMTX_CORE0_TG0_T0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_M  (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG0_T0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
-/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_TG0_WDT_INTR mapping register
- */
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M  (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
-/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_TG1_T0_INTR mapping register
- */
-#define INTMTX_CORE0_TG1_T0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_M  (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG1_T0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
-/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_TG1_WDT_INTR mapping register
- */
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M  (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
-/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_SYSTIMER_TARGET0_INTR mapping register
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
-/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_SYSTIMER_TARGET1_INTR mapping register
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
-/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_SYSTIMER_TARGET2_INTR mapping register
- */
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
-/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_APB_ADC_INTR mapping register
- */
-#define INTMTX_CORE0_APB_ADC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_M  (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_APB_ADC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PWM_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
-/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_PWM_INTR mapping register
- */
-#define INTMTX_CORE0_PWM_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PWM_INTR_MAP_M  (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
-#define INTMTX_CORE0_PWM_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PWM_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
-/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_PCNT_INTR mapping register
- */
-#define INTMTX_CORE0_PCNT_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PCNT_INTR_MAP_M  (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
-#define INTMTX_CORE0_PCNT_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PCNT_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
-/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_PARL_IO_TX_INTR mapping register
- */
-#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_M  (INTMTX_CORE0_PARL_IO_TX_INTR_MAP_V << INTMTX_CORE0_PARL_IO_TX_INTR_MAP_S)
-#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_S  0
-
-/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
-/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_PARL_IO_RX_INTR mapping register
- */
-#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_M  (INTMTX_CORE0_PARL_IO_RX_INTR_MAP_V << INTMTX_CORE0_PARL_IO_RX_INTR_MAP_S)
-#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
-/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_DMA_IN_CH0_INTR mapping register
- */
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
-/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_DMA_IN_CH1_INTR mapping register
- */
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
-/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_DMA_IN_CH2_INTR mapping register
- */
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
-/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_DMA_OUT_CH0_INTR mapping register
- */
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
-/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_DMA_OUT_CH1_INTR mapping register
- */
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S  0
-
-/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
-/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_DMA_OUT_CH2_INTR mapping register
- */
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
-/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_GPSPI2_INTR mapping register
- */
-#define INTMTX_CORE0_GPSPI2_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_M  (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_GPSPI2_INTR_MAP_S  0
-
-/** INTMTX_CORE0_AES_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
-/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_AES_INTR mapping register
- */
-#define INTMTX_CORE0_AES_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_AES_INTR_MAP_M  (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
-#define INTMTX_CORE0_AES_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_AES_INTR_MAP_S  0
-
-/** INTMTX_CORE0_SHA_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
-/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_SHA_INTR mapping register
- */
-#define INTMTX_CORE0_SHA_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_SHA_INTR_MAP_M  (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
-#define INTMTX_CORE0_SHA_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_SHA_INTR_MAP_S  0
-
-/** INTMTX_CORE0_RSA_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
-/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_RSA_INTR mapping register
- */
-#define INTMTX_CORE0_RSA_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_RSA_INTR_MAP_M  (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
-#define INTMTX_CORE0_RSA_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_RSA_INTR_MAP_S  0
-
-/** INTMTX_CORE0_ECC_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
-/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_ECC_INTR mapping register
- */
-#define INTMTX_CORE0_ECC_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ECC_INTR_MAP_M  (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
-#define INTMTX_CORE0_ECC_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ECC_INTR_MAP_S  0
-
-/** INTMTX_CORE0_ECDSA_INTR_MAP_REG register
- *  register description
- */
-#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
-/** INTMTX_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
- *  CORE0_ECDSA_INTR mapping register
- */
-#define INTMTX_CORE0_ECDSA_INTR_MAP    0x0000001FU
-#define INTMTX_CORE0_ECDSA_INTR_MAP_M  (INTMTX_CORE0_ECDSA_INTR_MAP_V << INTMTX_CORE0_ECDSA_INTR_MAP_S)
-#define INTMTX_CORE0_ECDSA_INTR_MAP_V  0x0000001FU
-#define INTMTX_CORE0_ECDSA_INTR_MAP_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
-/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
- *  Status register for interrupt sources 0~31 mapping register
- */
-#define INTMTX_CORE0_INT_STATUS_0    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_0_M  (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
-#define INTMTX_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_0_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
-/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
- *  Status register for interrupt sources 32~63 mapping register
- */
-#define INTMTX_CORE0_INT_STATUS_1    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_1_M  (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
-#define INTMTX_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_1_S  0
-
-/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
- *  register description
- */
-#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
-/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
- *  Status register for interrupt sources 64~95 mapping register
- */
-#define INTMTX_CORE0_INT_STATUS_2    0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_2_M  (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
-#define INTMTX_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
-#define INTMTX_CORE0_INT_STATUS_2_S  0
-
-/** INTMTX_CORE0_CLOCK_GATE_REG register
- *  register description
- */
-#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
-/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Clock register
- */
-#define INTMTX_CORE0_REG_CLK_EN    (BIT(0))
-#define INTMTX_CORE0_REG_CLK_EN_M  (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
-#define INTMTX_CORE0_REG_CLK_EN_V  0x00000001U
-#define INTMTX_CORE0_REG_CLK_EN_S  0
-
-/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
- *  register description
- */
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
-/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35688784;
- *  Version control register
- */
-#define INTMTX_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_M  (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
-#define INTMTX_CORE0_INTERRUPT_REG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/interrupt_matrix_struct.h b/components/soc/esp32h2/include/soc/interrupt_matrix_struct.h
deleted file mode 100644
index 7105872f357..00000000000
--- a/components/soc/esp32h2/include/soc/interrupt_matrix_struct.h
+++ /dev/null
@@ -1,1074 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Registers */
-/** Type of pmu_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_PMU_INTR mapping register
-         */
-        uint32_t pmu_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_pmu_intr_map_reg_t;
-
-/** Type of efuse_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_EFUSE_INTR mapping register
-         */
-        uint32_t efuse_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_efuse_intr_map_reg_t;
-
-/** Type of lp_rtc_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_LP_RTC_TIMER_INTR mapping register
-         */
-        uint32_t lp_rtc_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_lp_rtc_timer_intr_map_reg_t;
-
-/** Type of lp_ble_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_LP_BLE_TIMER_INTR mapping register
-         */
-        uint32_t lp_ble_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_lp_ble_timer_intr_map_reg_t;
-
-/** Type of lp_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_LP_WDT_INTR mapping register
-         */
-        uint32_t lp_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_lp_wdt_intr_map_reg_t;
-
-/** Type of lp_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_LP_PERI_TIMEOUT_INTR mapping register
-         */
-        uint32_t lp_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_lp_peri_timeout_intr_map_reg_t;
-
-/** Type of lp_apm_m0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_LP_APM_M0_INTR mapping register
-         */
-        uint32_t lp_apm_m0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_lp_apm_m0_intr_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_0_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_CPU_INTR_FROM_CPU_0 mapping register
-         */
-        uint32_t cpu_intr_from_cpu_0_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_cpu_intr_from_cpu_0_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_1_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_CPU_INTR_FROM_CPU_1 mapping register
-         */
-        uint32_t cpu_intr_from_cpu_1_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_cpu_intr_from_cpu_1_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_2_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_CPU_INTR_FROM_CPU_2 mapping register
-         */
-        uint32_t cpu_intr_from_cpu_2_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_cpu_intr_from_cpu_2_map_reg_t;
-
-/** Type of cpu_intr_from_cpu_3_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_CPU_INTR_FROM_CPU_3 mapping register
-         */
-        uint32_t cpu_intr_from_cpu_3_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_cpu_intr_from_cpu_3_map_reg_t;
-
-/** Type of assist_debug_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_ASSIST_DEBUG_INTR mapping register
-         */
-        uint32_t assist_debug_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_assist_debug_intr_map_reg_t;
-
-/** Type of trace_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** trace_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_TRACE_INTR mapping register
-         */
-        uint32_t trace_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_trace_intr_map_reg_t;
-
-/** Type of cache_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cache_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_CACHE_INTR mapping register
-         */
-        uint32_t cache_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_cache_intr_map_reg_t;
-
-/** Type of cpu_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_CPU_PERI_TIMEOUT_INTR mapping register
-         */
-        uint32_t cpu_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_cpu_peri_timeout_intr_map_reg_t;
-
-/** Type of bt_mac_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_BT_MAC_INTR mapping register
-         */
-        uint32_t bt_mac_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_bt_mac_intr_map_reg_t;
-
-/** Type of bt_bb_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_BT_BB_INTR mapping register
-         */
-        uint32_t bt_bb_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_bt_bb_intr_map_reg_t;
-
-/** Type of bt_bb_nmi_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_BT_BB_NMI mapping register
-         */
-        uint32_t bt_bb_nmi_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_bt_bb_nmi_map_reg_t;
-
-/** Type of coex_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** coex_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_COEX_INTR mapping register
-         */
-        uint32_t coex_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_coex_intr_map_reg_t;
-
-/** Type of ble_timer_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_BLE_TIMER_INTR mapping register
-         */
-        uint32_t ble_timer_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_ble_timer_intr_map_reg_t;
-
-/** Type of ble_sec_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_BLE_SEC_INTR mapping register
-         */
-        uint32_t ble_sec_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_ble_sec_intr_map_reg_t;
-
-/** Type of zb_mac_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_ZB_MAC_INTR mapping register
-         */
-        uint32_t zb_mac_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_zb_mac_intr_map_reg_t;
-
-/** Type of gpio_interrupt_pro_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_GPIO_INTERRUPT_PRO mapping register
-         */
-        uint32_t gpio_interrupt_pro_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_gpio_interrupt_pro_map_reg_t;
-
-/** Type of gpio_interrupt_pro_nmi_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_GPIO_INTERRUPT_PRO_NMI mapping register
-         */
-        uint32_t gpio_interrupt_pro_nmi_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_gpio_interrupt_pro_nmi_map_reg_t;
-
-/** Type of pau_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pau_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_PAU_INTR mapping register
-         */
-        uint32_t pau_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_pau_intr_map_reg_t;
-
-/** Type of hp_peri_timeout_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_HP_PERI_TIMEOUT_INTR mapping register
-         */
-        uint32_t hp_peri_timeout_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_hp_peri_timeout_intr_map_reg_t;
-
-/** Type of hp_apm_m0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_HP_APM_M0_INTR mapping register
-         */
-        uint32_t hp_apm_m0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_hp_apm_m0_intr_map_reg_t;
-
-/** Type of hp_apm_m1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_HP_APM_M1_INTR mapping register
-         */
-        uint32_t hp_apm_m1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_hp_apm_m1_intr_map_reg_t;
-
-/** Type of hp_apm_m2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_HP_APM_M2_INTR mapping register
-         */
-        uint32_t hp_apm_m2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_hp_apm_m2_intr_map_reg_t;
-
-/** Type of hp_apm_m3_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_HP_APM_M3_INTR mapping register
-         */
-        uint32_t hp_apm_m3_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_hp_apm_m3_intr_map_reg_t;
-
-/** Type of mspi_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_MSPI_INTR mapping register
-         */
-        uint32_t mspi_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_mspi_intr_map_reg_t;
-
-/** Type of i2s1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2s1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_I2S1_INTR mapping register
-         */
-        uint32_t i2s1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_i2s1_intr_map_reg_t;
-
-/** Type of uhci0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_UHCI0_INTR mapping register
-         */
-        uint32_t uhci0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_uhci0_intr_map_reg_t;
-
-/** Type of uart0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_UART0_INTR mapping register
-         */
-        uint32_t uart0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_uart0_intr_map_reg_t;
-
-/** Type of uart1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_UART1_INTR mapping register
-         */
-        uint32_t uart1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_uart1_intr_map_reg_t;
-
-/** Type of ledc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_LEDC_INTR mapping register
-         */
-        uint32_t ledc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_ledc_intr_map_reg_t;
-
-/** Type of can0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** can0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_CAN0_INTR mapping register
-         */
-        uint32_t can0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_can0_intr_map_reg_t;
-
-/** Type of usb_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** usb_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_USB_INTR mapping register
-         */
-        uint32_t usb_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_usb_intr_map_reg_t;
-
-/** Type of rmt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_RMT_INTR mapping register
-         */
-        uint32_t rmt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_rmt_intr_map_reg_t;
-
-/** Type of i2c_ext0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_I2C_EXT0_INTR mapping register
-         */
-        uint32_t i2c_ext0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_i2c_ext0_intr_map_reg_t;
-
-/** Type of i2c_ext1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** i2c_ext1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_I2C_EXT1_INTR mapping register
-         */
-        uint32_t i2c_ext1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_i2c_ext1_intr_map_reg_t;
-
-/** Type of tg0_t0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_TG0_T0_INTR mapping register
-         */
-        uint32_t tg0_t0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_tg0_t0_intr_map_reg_t;
-
-/** Type of tg0_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_TG0_WDT_INTR mapping register
-         */
-        uint32_t tg0_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_tg0_wdt_intr_map_reg_t;
-
-/** Type of tg1_t0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_TG1_T0_INTR mapping register
-         */
-        uint32_t tg1_t0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_tg1_t0_intr_map_reg_t;
-
-/** Type of tg1_wdt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_TG1_WDT_INTR mapping register
-         */
-        uint32_t tg1_wdt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_tg1_wdt_intr_map_reg_t;
-
-/** Type of systimer_target0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_SYSTIMER_TARGET0_INTR mapping register
-         */
-        uint32_t systimer_target0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_systimer_target0_intr_map_reg_t;
-
-/** Type of systimer_target1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_SYSTIMER_TARGET1_INTR mapping register
-         */
-        uint32_t systimer_target1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_systimer_target1_intr_map_reg_t;
-
-/** Type of systimer_target2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_SYSTIMER_TARGET2_INTR mapping register
-         */
-        uint32_t systimer_target2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_systimer_target2_intr_map_reg_t;
-
-/** Type of apb_adc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_APB_ADC_INTR mapping register
-         */
-        uint32_t apb_adc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_apb_adc_intr_map_reg_t;
-
-/** Type of pwm_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_PWM_INTR mapping register
-         */
-        uint32_t pwm_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_pwm_intr_map_reg_t;
-
-/** Type of pcnt_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_PCNT_INTR mapping register
-         */
-        uint32_t pcnt_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_pcnt_intr_map_reg_t;
-
-/** Type of parl_io_tx_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** parl_io_tx_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_PARL_IO_TX_INTR mapping register
-         */
-        uint32_t parl_io_tx_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_parl_io_tx_intr_map_reg_t;
-
-/** Type of parl_io_rx_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** parl_io_rx_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_PARL_IO_RX_INTR mapping register
-         */
-        uint32_t parl_io_rx_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_parl_io_rx_intr_map_reg_t;
-
-/** Type of dma_in_ch0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_DMA_IN_CH0_INTR mapping register
-         */
-        uint32_t dma_in_ch0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_dma_in_ch0_intr_map_reg_t;
-
-/** Type of dma_in_ch1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_DMA_IN_CH1_INTR mapping register
-         */
-        uint32_t dma_in_ch1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_dma_in_ch1_intr_map_reg_t;
-
-/** Type of dma_in_ch2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_DMA_IN_CH2_INTR mapping register
-         */
-        uint32_t dma_in_ch2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_dma_in_ch2_intr_map_reg_t;
-
-/** Type of dma_out_ch0_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_DMA_OUT_CH0_INTR mapping register
-         */
-        uint32_t dma_out_ch0_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_dma_out_ch0_intr_map_reg_t;
-
-/** Type of dma_out_ch1_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_DMA_OUT_CH1_INTR mapping register
-         */
-        uint32_t dma_out_ch1_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_dma_out_ch1_intr_map_reg_t;
-
-/** Type of dma_out_ch2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_DMA_OUT_CH2_INTR mapping register
-         */
-        uint32_t dma_out_ch2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_dma_out_ch2_intr_map_reg_t;
-
-/** Type of gpspi2_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_GPSPI2_INTR mapping register
-         */
-        uint32_t gpspi2_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_gpspi2_intr_map_reg_t;
-
-/** Type of aes_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** aes_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_AES_INTR mapping register
-         */
-        uint32_t aes_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_aes_intr_map_reg_t;
-
-/** Type of sha_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** sha_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_SHA_INTR mapping register
-         */
-        uint32_t sha_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_sha_intr_map_reg_t;
-
-/** Type of rsa_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_RSA_INTR mapping register
-         */
-        uint32_t rsa_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_rsa_intr_map_reg_t;
-
-/** Type of ecc_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_ECC_INTR mapping register
-         */
-        uint32_t ecc_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_ecc_intr_map_reg_t;
-
-/** Type of ecdsa_intr_map register
- *  register description
- */
-typedef union {
-    struct {
-        /** ecdsa_intr_map : R/W; bitpos: [4:0]; default: 0;
-         *  CORE0_ECDSA_INTR mapping register
-         */
-        uint32_t ecdsa_intr_map:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} intmtx_core0_ecdsa_intr_map_reg_t;
-
-/** Type of int_status_reg_0 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
-         *  Status register for interrupt sources 0~31 mapping register
-         */
-        uint32_t int_status_0:32;
-    };
-    uint32_t val;
-} intmtx_core0_int_status_reg_0_reg_t;
-
-/** Type of int_status_reg_1 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
-         *  Status register for interrupt sources 32~63 mapping register
-         */
-        uint32_t int_status_1:32;
-    };
-    uint32_t val;
-} intmtx_core0_int_status_reg_1_reg_t;
-
-/** Type of int_status_reg_2 register
- *  register description
- */
-typedef union {
-    struct {
-        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
-         *  Status register for interrupt sources 64~95 mapping register
-         */
-        uint32_t int_status_2:32;
-    };
-    uint32_t val;
-} intmtx_core0_int_status_reg_2_reg_t;
-
-/** Type of clock_gate register
- *  register description
- */
-typedef union {
-    struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Clock register
-         */
-        uint32_t reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} intmtx_core0_clock_gate_reg_t;
-
-/** Type of interrupt_reg_date register
- *  register description
- */
-typedef union {
-    struct {
-        /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35688784;
-         *  Version control register
-         */
-        uint32_t interrupt_reg_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} intmtx_core0_interrupt_reg_date_reg_t;
-
-
-typedef struct interrupt_matrix_dev_t {
-    volatile intmtx_core0_pmu_intr_map_reg_t pmu_intr_map;
-    volatile intmtx_core0_efuse_intr_map_reg_t efuse_intr_map;
-    volatile intmtx_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
-    volatile intmtx_core0_lp_ble_timer_intr_map_reg_t lp_ble_timer_intr_map;
-    volatile intmtx_core0_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
-    volatile intmtx_core0_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
-    volatile intmtx_core0_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
-    volatile intmtx_core0_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
-    volatile intmtx_core0_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
-    volatile intmtx_core0_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
-    volatile intmtx_core0_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
-    volatile intmtx_core0_assist_debug_intr_map_reg_t assist_debug_intr_map;
-    volatile intmtx_core0_trace_intr_map_reg_t trace_intr_map;
-    volatile intmtx_core0_cache_intr_map_reg_t cache_intr_map;
-    volatile intmtx_core0_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map;
-    volatile intmtx_core0_bt_mac_intr_map_reg_t bt_mac_intr_map;
-    volatile intmtx_core0_bt_bb_intr_map_reg_t bt_bb_intr_map;
-    volatile intmtx_core0_bt_bb_nmi_map_reg_t bt_bb_nmi_map;
-    volatile intmtx_core0_coex_intr_map_reg_t coex_intr_map;
-    volatile intmtx_core0_ble_timer_intr_map_reg_t ble_timer_intr_map;
-    volatile intmtx_core0_ble_sec_intr_map_reg_t ble_sec_intr_map;
-    volatile intmtx_core0_zb_mac_intr_map_reg_t zb_mac_intr_map;
-    volatile intmtx_core0_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map;
-    volatile intmtx_core0_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map;
-    volatile intmtx_core0_pau_intr_map_reg_t pau_intr_map;
-    volatile intmtx_core0_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map;
-    volatile intmtx_core0_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
-    volatile intmtx_core0_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
-    volatile intmtx_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
-    volatile intmtx_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
-    volatile intmtx_core0_mspi_intr_map_reg_t mspi_intr_map;
-    volatile intmtx_core0_i2s1_intr_map_reg_t i2s1_intr_map;
-    volatile intmtx_core0_uhci0_intr_map_reg_t uhci0_intr_map;
-    volatile intmtx_core0_uart0_intr_map_reg_t uart0_intr_map;
-    volatile intmtx_core0_uart1_intr_map_reg_t uart1_intr_map;
-    volatile intmtx_core0_ledc_intr_map_reg_t ledc_intr_map;
-    volatile intmtx_core0_can0_intr_map_reg_t can0_intr_map;
-    volatile intmtx_core0_usb_intr_map_reg_t usb_intr_map;
-    volatile intmtx_core0_rmt_intr_map_reg_t rmt_intr_map;
-    volatile intmtx_core0_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map;
-    volatile intmtx_core0_i2c_ext1_intr_map_reg_t i2c_ext1_intr_map;
-    volatile intmtx_core0_tg0_t0_intr_map_reg_t tg0_t0_intr_map;
-    volatile intmtx_core0_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map;
-    volatile intmtx_core0_tg1_t0_intr_map_reg_t tg1_t0_intr_map;
-    volatile intmtx_core0_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map;
-    volatile intmtx_core0_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
-    volatile intmtx_core0_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
-    volatile intmtx_core0_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
-    volatile intmtx_core0_apb_adc_intr_map_reg_t apb_adc_intr_map;
-    volatile intmtx_core0_pwm_intr_map_reg_t pwm_intr_map;
-    volatile intmtx_core0_pcnt_intr_map_reg_t pcnt_intr_map;
-    volatile intmtx_core0_parl_io_tx_intr_map_reg_t parl_io_tx_intr_map;
-    volatile intmtx_core0_parl_io_rx_intr_map_reg_t parl_io_rx_intr_map;
-    volatile intmtx_core0_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map;
-    volatile intmtx_core0_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map;
-    volatile intmtx_core0_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map;
-    volatile intmtx_core0_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map;
-    volatile intmtx_core0_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map;
-    volatile intmtx_core0_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map;
-    volatile intmtx_core0_gpspi2_intr_map_reg_t gpspi2_intr_map;
-    volatile intmtx_core0_aes_intr_map_reg_t aes_intr_map;
-    volatile intmtx_core0_sha_intr_map_reg_t sha_intr_map;
-    volatile intmtx_core0_rsa_intr_map_reg_t rsa_intr_map;
-    volatile intmtx_core0_ecc_intr_map_reg_t ecc_intr_map;
-    volatile intmtx_core0_ecdsa_intr_map_reg_t ecdsa_intr_map;
-    volatile intmtx_core0_int_status_reg_0_reg_t int_status_reg_0;
-    volatile intmtx_core0_int_status_reg_1_reg_t int_status_reg_1;
-    volatile intmtx_core0_int_status_reg_2_reg_t int_status_reg_2;
-    volatile intmtx_core0_clock_gate_reg_t clock_gate;
-    uint32_t reserved_114[442];
-    volatile intmtx_core0_interrupt_reg_date_reg_t interrupt_reg_date;
-} interrupt_matrix_dev_t;
-
-extern interrupt_matrix_dev_t INTMTX;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/interrupt_reg.h b/components/soc/esp32h2/include/soc/interrupt_reg.h
index 1eb4721c840..4faef7949b9 100644
--- a/components/soc/esp32h2/include/soc/interrupt_reg.h
+++ b/components/soc/esp32h2/include/soc/interrupt_reg.h
@@ -5,8 +5,8 @@
  */
 #pragma once
 
-#include "interrupt_matrix_reg.h"
-#include "plic_reg.h"
+#include "soc/interrupt_matrix_reg.h"
+#include "soc/plic_reg.h"
 #include "soc/soc_caps.h"
 
 #define INTERRUPT_PRIO_REG(n)                   (PLIC_MXINT0_PRI_REG + (n)*4)
diff --git a/components/soc/esp32h2/include/soc/interrupts.h b/components/soc/esp32h2/include/soc/interrupts.h
index cac8f027768..491d0df3512 100644
--- a/components/soc/esp32h2/include/soc/interrupts.h
+++ b/components/soc/esp32h2/include/soc/interrupts.h
@@ -46,7 +46,7 @@ typedef enum {
     ETS_HP_APM_M2_INTR_SOURCE,
     ETS_HP_APM_M3_INTR_SOURCE,
     ETS_MSPI_INTR_SOURCE,
-    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
+    ETS_I2S0_INTR_SOURCE,                       /**< interrupt of I2S0, level*/
     ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
     ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
     ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
diff --git a/components/soc/esp32h2/include/soc/io_mux_reg.h b/components/soc/esp32h2/include/soc/io_mux_reg.h
deleted file mode 100644
index 5db79e1673a..00000000000
--- a/components/soc/esp32h2/include/soc/io_mux_reg.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-#include "soc.h"
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Pin used for wakeup from sleep */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
-#define FILTER_EN (BIT(15))
-#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
-#define FILTER_EN_V 1
-#define FILTER_EN_S 15
-
-/* HYS_EN : R/W; bitpos: [16]; default: 0;
- * Software enables hysteresis function for the pad.
- * 1: Hysteresis enabled. 0: Hysteresis disabled.
- */
-#define HYS_EN    (BIT(16))
-#define HYS_EN_M  (HYS_EN_V << HYS_EN_S)
-#define HYS_EN_V  0x00000001
-#define HYS_EN_S  16
-/* HYS_SEL : R/W; bitpos: [17]; default: 0;
- * Select enabling signals of the pad from software and efuse hardware.
- * 1: Select enabling siganl from software.
- * 0: Select enabling signal from efuse hardware.
- */
-#define HYS_SEL    (BIT(17))
-#define HYS_SEL_M  (HYS_SEL_V << HYS_SEL_S)
-#define HYS_SEL_V  0x00000001
-#define HYS_SEL_S  17
-
-#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-
-#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
-#define PIN_HYS_EN_SEL_EFUSE(PIN_NAME)      REG_CLR_BIT(PIN_NAME, HYS_SEL)
-#define PIN_HYS_EN_SEL_SOFT(PIN_NAME)       REG_SET_BIT(PIN_NAME, HYS_SEL)
-#define PIN_HYS_SOFT_ENABLE(PIN_NAME)       REG_SET_BIT(PIN_NAME, HYS_EN)
-#define PIN_HYS_SOFT_DISABLE(PIN_NAME)      REG_CLR_BIT(PIN_NAME, HYS_EN)
-
-#define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_GPIO0_U
-#define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_GPIO1_U
-#define IO_MUX_GPIO2_REG               PERIPHS_IO_MUX_MTMS_U
-#define IO_MUX_GPIO3_REG               PERIPHS_IO_MUX_MTDO_U
-#define IO_MUX_GPIO4_REG               PERIPHS_IO_MUX_MTCK_U
-#define IO_MUX_GPIO5_REG               PERIPHS_IO_MUX_MTDI_U
-#define IO_MUX_GPIO6_REG               PERIPHS_IO_MUX_GPIO6_U
-#define IO_MUX_GPIO7_REG               PERIPHS_IO_MUX_GPIO7_U
-#define IO_MUX_GPIO8_REG               PERIPHS_IO_MUX_GPIO8_U
-#define IO_MUX_GPIO9_REG               PERIPHS_IO_MUX_GPIO9_U
-#define IO_MUX_GPIO10_REG              PERIPHS_IO_MUX_GPIO10_U
-#define IO_MUX_GPIO11_REG              PERIPHS_IO_MUX_GPIO11_U
-#define IO_MUX_GPIO12_REG              PERIPHS_IO_MUX_GPIO12_U
-#define IO_MUX_GPIO13_REG              PERIPHS_IO_MUX_XTAL_32K_P_U
-#define IO_MUX_GPIO14_REG              PERIPHS_IO_MUX_XTAL_32K_N_U
-#define IO_MUX_GPIO15_REG              PERIPHS_IO_MUX_SPICS0_U
-#define IO_MUX_GPIO16_REG              PERIPHS_IO_MUX_SPIQ_U
-#define IO_MUX_GPIO17_REG              PERIPHS_IO_MUX_SPIWP_U
-#define IO_MUX_GPIO18_REG              PERIPHS_IO_MUX_SPIHD_U
-#define IO_MUX_GPIO19_REG              PERIPHS_IO_MUX_SPICLK_U
-#define IO_MUX_GPIO20_REG              PERIPHS_IO_MUX_SPID_U
-#define IO_MUX_GPIO21_REG              PERIPHS_IO_MUX_VDD_SPI_U
-#define IO_MUX_GPIO22_REG              PERIPHS_IO_MUX_GPIO22_U
-#define IO_MUX_GPIO23_REG              PERIPHS_IO_MUX_U0RXD_U
-#define IO_MUX_GPIO24_REG              PERIPHS_IO_MUX_U0TXD_U
-#define IO_MUX_GPIO25_REG              PERIPHS_IO_MUX_GPIO25_U
-#define IO_MUX_GPIO26_REG              PERIPHS_IO_MUX_GPIO26_U
-#define IO_MUX_GPIO27_REG              PERIPHS_IO_MUX_GPIO27_U
-
-#define PIN_FUNC_GPIO								1
-
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
-#define SPI_HD_GPIO_NUM              18
-#define SPI_WP_GPIO_NUM              17
-#define SPI_CS0_GPIO_NUM             15
-#define SPI_CLK_GPIO_NUM             19
-#define SPI_D_GPIO_NUM               20
-#define SPI_Q_GPIO_NUM               16
-
-#define USB_INT_PHY0_DM_GPIO_NUM              26
-#define USB_INT_PHY0_DP_GPIO_NUM              27
-
-#define EXT_OSC_SLOW_GPIO_NUM        13
-
-#define MAX_RTC_GPIO_NUM             14            // GPIO7~14 are the pads with LP function
-#define MAX_PAD_GPIO_NUM             27
-#define MAX_GPIO_NUM                 31
-#define HIGH_IO_HOLD_BIT_SHIFT       32
-
-
-#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
-#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
-
-#define CLK_OUT3                                    IO_MUX_CLK_OUT3
-#define CLK_OUT3_V                                  IO_MUX_CLK_OUT3_V
-#define CLK_OUT3_S                                  IO_MUX_CLK_OUT3_S
-#define CLK_OUT3_M                                  IO_MUX_CLK_OUT3_M
-#define CLK_OUT2                                    IO_MUX_CLK_OUT2
-#define CLK_OUT2_V                                  IO_MUX_CLK_OUT2_V
-#define CLK_OUT2_S                                  IO_MUX_CLK_OUT2_S
-#define CLK_OUT2_M                                  IO_MUX_CLK_OUT2_M
-#define CLK_OUT1                                    IO_MUX_CLK_OUT1
-#define CLK_OUT1_V                                  IO_MUX_CLK_OUT1_V
-#define CLK_OUT1_S                                  IO_MUX_CLK_OUT1_S
-#define CLK_OUT1_M                                  IO_MUX_CLK_OUT1_M
-// definitions above are inherited from previous version of code, should double check
-
-// definitions below are generated from pin_txt.csv
-#define PERIPHS_IO_MUX_GPIO0_U                (REG_IO_MUX_BASE + 0x4)
-#define FUNC_GPIO0_FSPIQ                                            2
-#define FUNC_GPIO0_GPIO0                                            1
-#define FUNC_GPIO0_GPIO0_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO1_U                (REG_IO_MUX_BASE + 0x8)
-#define FUNC_GPIO1_FSPICS0                                          2
-#define FUNC_GPIO1_GPIO1                                            1
-#define FUNC_GPIO1_GPIO1_0                                          0
-
-#define PERIPHS_IO_MUX_MTMS_U                 (REG_IO_MUX_BASE + 0xC)
-#define FUNC_MTMS_FSPIWP                                            2
-#define FUNC_MTMS_GPIO2                                             1
-#define FUNC_MTMS_MTMS                                              0
-
-#define PERIPHS_IO_MUX_MTDO_U                (REG_IO_MUX_BASE + 0x10)
-#define FUNC_MTDO_FSPIHD                                            2
-#define FUNC_MTDO_GPIO3                                             1
-#define FUNC_MTDO_MTDO                                              0
-
-#define PERIPHS_IO_MUX_MTCK_U                (REG_IO_MUX_BASE + 0x14)
-#define FUNC_MTCK_FSPICLK                                           2
-#define FUNC_MTCK_GPIO4                                             1
-#define FUNC_MTCK_MTCK                                              0
-
-#define PERIPHS_IO_MUX_MTDI_U                (REG_IO_MUX_BASE + 0x18)
-#define FUNC_MTDI_FSPID                                             2
-#define FUNC_MTDI_GPIO5                                             1
-#define FUNC_MTDI_MTDI                                              0
-
-#define PERIPHS_IO_MUX_GPIO6_U               (REG_IO_MUX_BASE + 0x1C)
-#define FUNC_GPIO6_GPIO6                                            1
-#define FUNC_GPIO6_GPIO6_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO7_U               (REG_IO_MUX_BASE + 0x20)
-#define FUNC_GPIO7_GPIO7                                            1
-#define FUNC_GPIO7_GPIO7_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO8_U               (REG_IO_MUX_BASE + 0x24)
-#define FUNC_GPIO8_GPIO8                                            1
-#define FUNC_GPIO8_GPIO8_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO9_U               (REG_IO_MUX_BASE + 0x28)
-#define FUNC_GPIO9_GPIO9                                            1
-#define FUNC_GPIO9_GPIO9_0                                          0
-
-#define PERIPHS_IO_MUX_GPIO10_U              (REG_IO_MUX_BASE + 0x2C)
-#define FUNC_GPIO10_GPIO10                                          1
-#define FUNC_GPIO10_GPIO10_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO11_U              (REG_IO_MUX_BASE + 0x30)
-#define FUNC_GPIO11_GPIO11                                          1
-#define FUNC_GPIO11_GPIO11_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO12_U              (REG_IO_MUX_BASE + 0x34)
-#define FUNC_GPIO12_GPIO12                                          1
-#define FUNC_GPIO12_GPIO12_0                                        0
-
-#define PERIPHS_IO_MUX_XTAL_32K_P_U          (REG_IO_MUX_BASE + 0x38)
-#define FUNC_XTAL_32K_P_GPIO13                                      1
-#define FUNC_XTAL_32K_P_GPIO13_0                                    0
-
-#define PERIPHS_IO_MUX_XTAL_32K_N_U          (REG_IO_MUX_BASE + 0x3C)
-#define FUNC_XTAL_32K_N_GPIO14                                      1
-#define FUNC_XTAL_32K_N_GPIO14_0                                    0
-
-#define PERIPHS_IO_MUX_SPICS0_U              (REG_IO_MUX_BASE + 0x40)
-#define FUNC_SPICS0_GPIO15                                          1
-#define FUNC_SPICS0_SPICS0                                          0
-
-#define PERIPHS_IO_MUX_SPIQ_U                (REG_IO_MUX_BASE + 0x44)
-#define FUNC_SPIQ_GPIO16                                            1
-#define FUNC_SPIQ_SPIQ                                              0
-
-#define PERIPHS_IO_MUX_SPIWP_U               (REG_IO_MUX_BASE + 0x48)
-#define FUNC_SPIWP_GPIO17                                           1
-#define FUNC_SPIWP_SPIWP                                            0
-
-#define PERIPHS_IO_MUX_SPIHD_U               (REG_IO_MUX_BASE + 0x4C)
-#define FUNC_SPIHD_GPIO18                                           1
-#define FUNC_SPIHD_SPIHD                                            0
-
-#define PERIPHS_IO_MUX_SPICLK_U              (REG_IO_MUX_BASE + 0x50)
-#define FUNC_SPICLK_GPIO19                                          1
-#define FUNC_SPICLK_SPICLK                                          0
-
-#define PERIPHS_IO_MUX_SPID_U                (REG_IO_MUX_BASE + 0x54)
-#define FUNC_SPID_GPIO20                                            1
-#define FUNC_SPID_SPID                                              0
-
-#define PERIPHS_IO_MUX_VDD_SPI_U             (REG_IO_MUX_BASE + 0x58)
-#define FUNC_VDD_SPI_GPIO21                                         1
-#define FUNC_VDD_SPI_GPIO21_0                                       0
-
-#define PERIPHS_IO_MUX_GPIO22_U              (REG_IO_MUX_BASE + 0x5C)
-#define FUNC_GPIO22_GPIO22                                          1
-#define FUNC_GPIO22_GPIO22_0                                        0
-
-#define PERIPHS_IO_MUX_U0RXD_U               (REG_IO_MUX_BASE + 0x60)
-#define FUNC_U0RXD_FSPICS1                                          2
-#define FUNC_U0RXD_GPIO23                                           1
-#define FUNC_U0RXD_U0RXD                                            0
-
-#define PERIPHS_IO_MUX_U0TXD_U               (REG_IO_MUX_BASE + 0x64)
-#define FUNC_U0TXD_FSPICS2                                          2
-#define FUNC_U0TXD_GPIO24                                           1
-#define FUNC_U0TXD_U0TXD                                            0
-
-#define PERIPHS_IO_MUX_GPIO25_U              (REG_IO_MUX_BASE + 0x68)
-#define FUNC_GPIO25_FSPICS3                                         2
-#define FUNC_GPIO25_GPIO25                                          1
-#define FUNC_GPIO25_GPIO25_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO26_U              (REG_IO_MUX_BASE + 0x6C)
-#define FUNC_GPIO26_FSPICS4                                         2
-#define FUNC_GPIO26_GPIO26                                          1
-#define FUNC_GPIO26_GPIO26_0                                        0
-
-#define PERIPHS_IO_MUX_GPIO27_U              (REG_IO_MUX_BASE + 0x70)
-#define FUNC_GPIO27_FSPICS5                                         2
-#define FUNC_GPIO27_GPIO27                                          1
-#define FUNC_GPIO27_GPIO27_0                                        0
-
-/** IO_MUX_PIN_CTRL_REG register
- *  Clock Output Configuration
- *  Register
- */
-#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
-/* IO_MUX_CLK_OUT1 : R/W; bitpos: [5:0]; default: 15;
- * If you want to output clock for I2S to CLK_OUT_out1, set this register
- * to 0x0. CLK_OUT_out1 can be found in peripheral output
- * signals.
- */
-#define IO_MUX_CLK_OUT1    0x0000001F
-#define IO_MUX_CLK_OUT1_M  (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
-#define IO_MUX_CLK_OUT1_V  0x0000001F
-#define IO_MUX_CLK_OUT1_S  0
-/* IO_MUX_CLK_OUT2 : R/W; bitpos: [10:5]; default: 15;
- * If you want to output clock for I2S to CLK_OUT_out2, set this register
- * to 0x0. CLK_OUT_out2 can be found in peripheral output
- * signals.
- */
-#define IO_MUX_CLK_OUT2    0x0000001F
-#define IO_MUX_CLK_OUT2_M  (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
-#define IO_MUX_CLK_OUT2_V  0x0000001F
-#define IO_MUX_CLK_OUT2_S  5
-/* IO_MUX_CLK_OUT3 : R/W; bitpos: [15:10]; default: 7;
- * If you want to output clock for I2S to CLK_OUT_out3, set this register
- * to 0x0. CLK_OUT_out3 can be found in peripheral output
- * signals.
- */
-#define IO_MUX_CLK_OUT3    0x0000001F
-#define IO_MUX_CLK_OUT3_M  (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
-#define IO_MUX_CLK_OUT3_V  0x0000001F
-#define IO_MUX_CLK_OUT3_S  10
-
-/** IO_MUX_MODEM_DIAG_EN_REG register
- *  GPIO MATRIX Configure Register for modem
- *  diag
- */
-#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
-/* IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [32:0]; default: 0;
- * bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i]
- * into gpio matrix. 0:enable other signals into gpio
- * matrix
- */
-#define IO_MUX_MODEM_DIAG_EN    0xFFFFFFFF
-#define IO_MUX_MODEM_DIAG_EN_M  (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
-#define IO_MUX_MODEM_DIAG_EN_V  0xFFFFFFFF
-#define IO_MUX_MODEM_DIAG_EN_S  0
-
-/** IO_MUX_DATE_REG register
- *  IO MUX Version Control
- *  Register
- */
-#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
-/* IO_MUX_REG_DATE : R/W; bitpos: [28:0]; default: 35680880;
- * Version control
- * register
- */
-#define IO_MUX_REG_DATE    0x0FFFFFFF
-#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
-#define IO_MUX_REG_DATE_V  0x0FFFFFFF
-#define IO_MUX_REG_DATE_S  0
diff --git a/components/soc/esp32h2/include/soc/mcpwm_reg.h b/components/soc/esp32h2/include/soc/mcpwm_reg.h
deleted file mode 100644
index f851de75cee..00000000000
--- a/components/soc/esp32h2/include/soc/mcpwm_reg.h
+++ /dev/null
@@ -1,4137 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MCPWM_CLK_CFG_REG register
- *  PWM clock prescaler register.
- */
-#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0)
-/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
- */
-#define MCPWM_CLK_PRESCALE    0x000000FFU
-#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
-#define MCPWM_CLK_PRESCALE_V  0x000000FFU
-#define MCPWM_CLK_PRESCALE_S  0
-
-/** MCPWM_TIMER0_CFG0_REG register
- *  PWM timer0 period and update method configuration register.
- */
-#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer0
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER0_CFG1_REG register
- *  PWM timer0 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8)
-/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1:
- *  if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0
- *  starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER0_START    0x00000007U
-#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
-#define MCPWM_TIMER0_START_V  0x00000007U
-#define MCPWM_TIMER0_START_S  0
-/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER0_MOD    0x00000003U
-#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
-#define MCPWM_TIMER0_MOD_V  0x00000003U
-#define MCPWM_TIMER0_MOD_S  3
-
-/** MCPWM_TIMER0_SYNC_REG register
- *  PWM timer0 sync function configuration register.
- */
-#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc)
-/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
-#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER0_SYNCI_EN_S  0
-/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
-#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER0_SYNC_SW_S  1
-/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer0_sync_sw bit
- */
-#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
-#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_S  2
-/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER0_PHASE    0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
-#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_S  4
-/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer0's direction when timer0 mode is up-down mode:
- *  0-increase,1-decrease
- */
-#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
-#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER0_STATUS_REG register
- *  PWM timer0 status register.
- */
-#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10)
-/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer0 counter value
- */
-#define MCPWM_TIMER0_VALUE    0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
-#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_S  0
-/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer0 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER0_DIRECTION    (BIT(16))
-#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
-#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_DIRECTION_S  16
-
-/** MCPWM_TIMER1_CFG0_REG register
- *  PWM timer1 period and update method configuration register.
- */
-#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14)
-/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1)
- */
-#define MCPWM_TIMER1_PRESCALE    0x000000FFU
-#define MCPWM_TIMER1_PRESCALE_M  (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S)
-#define MCPWM_TIMER1_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER1_PRESCALE_S  0
-/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer1
- */
-#define MCPWM_TIMER1_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER1_PERIOD_M  (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S)
-#define MCPWM_TIMER1_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER1_PERIOD_S  8
-/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER1_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER1_CFG1_REG register
- *  PWM timer1 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18)
-/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1:
- *  if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1
- *  starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER1_START    0x00000007U
-#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
-#define MCPWM_TIMER1_START_V  0x00000007U
-#define MCPWM_TIMER1_START_S  0
-/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER1_MOD    0x00000003U
-#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
-#define MCPWM_TIMER1_MOD_V  0x00000003U
-#define MCPWM_TIMER1_MOD_S  3
-
-/** MCPWM_TIMER1_SYNC_REG register
- *  PWM timer1 sync function configuration register.
- */
-#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c)
-/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
-#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER1_SYNCI_EN_S  0
-/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
-#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER1_SYNC_SW_S  1
-/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer1_sync_sw bit
- */
-#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
-#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_S  2
-/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER1_PHASE    0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
-#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_S  4
-/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer1's direction when timer1 mode is up-down mode:
- *  0-increase,1-decrease
- */
-#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
-#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER1_STATUS_REG register
- *  PWM timer1 status register.
- */
-#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20)
-/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer1 counter value
- */
-#define MCPWM_TIMER1_VALUE    0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
-#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_S  0
-/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer1 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER1_DIRECTION    (BIT(16))
-#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
-#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_DIRECTION_S  16
-
-/** MCPWM_TIMER2_CFG0_REG register
- *  PWM timer2 period and update method configuration register.
- */
-#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24)
-/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1)
- */
-#define MCPWM_TIMER2_PRESCALE    0x000000FFU
-#define MCPWM_TIMER2_PRESCALE_M  (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S)
-#define MCPWM_TIMER2_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER2_PRESCALE_S  0
-/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer2
- */
-#define MCPWM_TIMER2_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER2_PERIOD_M  (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S)
-#define MCPWM_TIMER2_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER2_PERIOD_S  8
-/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER2_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER2_CFG1_REG register
- *  PWM timer2 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28)
-/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1:
- *  if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2
- *  starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER2_START    0x00000007U
-#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
-#define MCPWM_TIMER2_START_V  0x00000007U
-#define MCPWM_TIMER2_START_S  0
-/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER2_MOD    0x00000003U
-#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
-#define MCPWM_TIMER2_MOD_V  0x00000003U
-#define MCPWM_TIMER2_MOD_S  3
-
-/** MCPWM_TIMER2_SYNC_REG register
- *  PWM timer2 sync function configuration register.
- */
-#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c)
-/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
-#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER2_SYNCI_EN_S  0
-/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
-#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER2_SYNC_SW_S  1
-/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer0_sync_sw bit
- */
-#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
-#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_S  2
-/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER2_PHASE    0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
-#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_S  4
-/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer2's direction when timer2 mode is up-down mode:
- *  0-increase,1-decrease
- */
-#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
-#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER2_STATUS_REG register
- *  PWM timer2 status register.
- */
-#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30)
-/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer2 counter value
- */
-#define MCPWM_TIMER2_VALUE    0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
-#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_S  0
-/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer2 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER2_DIRECTION    (BIT(16))
-#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
-#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_DIRECTION_S  16
-
-/** MCPWM_TIMER_SYNCI_CFG_REG register
- *  Synchronization input selection for three PWM timers.
- */
-#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34)
-/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
- *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER0_SYNCISEL    0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
-#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_S  0
-/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
- *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER1_SYNCISEL    0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
-#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_S  3
-/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
- *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER2_SYNCISEL    0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
-#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_S  6
-/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
- *  invert SYNC0 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
-/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
- *  invert SYNC1 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
-/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
- *  invert SYNC2 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
-
-/** MCPWM_OPERATOR_TIMERSEL_REG register
- *  Select specific timer for PWM operators.
- */
-#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38)
-/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
- *  Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
-#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_S  0
-/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
- *  Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
-#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_S  2
-/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
- *  Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
-#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_S  4
-
-/** MCPWM_GEN0_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c)
-/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 0 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
-#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_S  0
-/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 0 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
-#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_S  4
-/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
-#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_A_SHDW_FULL_S  8
-/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
-#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN0_TSTMP_A_REG register
- *  Shadow register for register A.
- */
-#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40)
-/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 0 time stamp A's shadow register
- */
-#define MCPWM_CMPR0_A    0x0000FFFFU
-#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
-#define MCPWM_CMPR0_A_V  0x0000FFFFU
-#define MCPWM_CMPR0_A_S  0
-
-/** MCPWM_GEN0_TSTMP_B_REG register
- *  Shadow register for register B.
- */
-#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44)
-/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 0 time stamp B's shadow register
- */
-#define MCPWM_CMPR0_B    0x0000FFFFU
-#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
-#define MCPWM_CMPR0_B_V  0x0000FFFFU
-#define MCPWM_CMPR0_B_S  0
-
-/** MCPWM_GEN0_CFG0_REG register
- *  Fault event T0 and T1 handling
- */
-#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48)
-/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 0's active register of configuration. When all bits
- *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
- *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
- */
-#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
-#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_S  0
-/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 0 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN0_T0_SEL    0x00000007U
-#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
-#define MCPWM_GEN0_T0_SEL_V  0x00000007U
-#define MCPWM_GEN0_T0_SEL_S  4
-/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 0 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN0_T1_SEL    0x00000007U
-#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
-#define MCPWM_GEN0_T1_SEL_V  0x00000007U
-#define MCPWM_GEN0_T1_SEL_S  7
-
-/** MCPWM_GEN0_FORCE_REG register
- *  Permissives to force PWM0A and PWM0B outputs by software
- */
-#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c)
-/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator0. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM0A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
-#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_A_NCIFORCE_S  10
-/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM0B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
-#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_B_NCIFORCE_S  13
-/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN0_A_REG register
- *  Actions triggered by events on PWM0A
- */
-#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50)
-/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM0A triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN0_A_UTEZ    0x00000003U
-#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
-#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_UTEZ_S  0
-/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM0A triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN0_A_UTEP    0x00000003U
-#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
-#define MCPWM_GEN0_A_UTEP_V  0x00000003U
-#define MCPWM_GEN0_A_UTEP_S  2
-/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM0A triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN0_A_UTEA    0x00000003U
-#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
-#define MCPWM_GEN0_A_UTEA_V  0x00000003U
-#define MCPWM_GEN0_A_UTEA_S  4
-/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM0A triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN0_A_UTEB    0x00000003U
-#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
-#define MCPWM_GEN0_A_UTEB_V  0x00000003U
-#define MCPWM_GEN0_A_UTEB_S  6
-/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM0A triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN0_A_UT0    0x00000003U
-#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
-#define MCPWM_GEN0_A_UT0_V  0x00000003U
-#define MCPWM_GEN0_A_UT0_S  8
-/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM0A triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN0_A_UT1    0x00000003U
-#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
-#define MCPWM_GEN0_A_UT1_V  0x00000003U
-#define MCPWM_GEN0_A_UT1_S  10
-/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM0A triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN0_A_DTEZ    0x00000003U
-#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
-#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_DTEZ_S  12
-/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM0A triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN0_A_DTEP    0x00000003U
-#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
-#define MCPWM_GEN0_A_DTEP_V  0x00000003U
-#define MCPWM_GEN0_A_DTEP_S  14
-/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM0A triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN0_A_DTEA    0x00000003U
-#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
-#define MCPWM_GEN0_A_DTEA_V  0x00000003U
-#define MCPWM_GEN0_A_DTEA_S  16
-/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM0A triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN0_A_DTEB    0x00000003U
-#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
-#define MCPWM_GEN0_A_DTEB_V  0x00000003U
-#define MCPWM_GEN0_A_DTEB_S  18
-/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM0A triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN0_A_DT0    0x00000003U
-#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
-#define MCPWM_GEN0_A_DT0_V  0x00000003U
-#define MCPWM_GEN0_A_DT0_S  20
-/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_DT1    0x00000003U
-#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
-#define MCPWM_GEN0_A_DT1_V  0x00000003U
-#define MCPWM_GEN0_A_DT1_S  22
-
-/** MCPWM_GEN0_B_REG register
- *  Actions triggered by events on PWM0B
- */
-#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54)
-/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM0B triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN0_B_UTEZ    0x00000003U
-#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
-#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_UTEZ_S  0
-/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM0B triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN0_B_UTEP    0x00000003U
-#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
-#define MCPWM_GEN0_B_UTEP_V  0x00000003U
-#define MCPWM_GEN0_B_UTEP_S  2
-/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM0B triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN0_B_UTEA    0x00000003U
-#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
-#define MCPWM_GEN0_B_UTEA_V  0x00000003U
-#define MCPWM_GEN0_B_UTEA_S  4
-/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM0B triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN0_B_UTEB    0x00000003U
-#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
-#define MCPWM_GEN0_B_UTEB_V  0x00000003U
-#define MCPWM_GEN0_B_UTEB_S  6
-/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM0B triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN0_B_UT0    0x00000003U
-#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
-#define MCPWM_GEN0_B_UT0_V  0x00000003U
-#define MCPWM_GEN0_B_UT0_S  8
-/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM0B triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN0_B_UT1    0x00000003U
-#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
-#define MCPWM_GEN0_B_UT1_V  0x00000003U
-#define MCPWM_GEN0_B_UT1_S  10
-/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM0B triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN0_B_DTEZ    0x00000003U
-#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
-#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_DTEZ_S  12
-/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM0B triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN0_B_DTEP    0x00000003U
-#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
-#define MCPWM_GEN0_B_DTEP_V  0x00000003U
-#define MCPWM_GEN0_B_DTEP_S  14
-/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM0B triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN0_B_DTEA    0x00000003U
-#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
-#define MCPWM_GEN0_B_DTEA_V  0x00000003U
-#define MCPWM_GEN0_B_DTEA_S  16
-/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM0B triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN0_B_DTEB    0x00000003U
-#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
-#define MCPWM_GEN0_B_DTEB_V  0x00000003U
-#define MCPWM_GEN0_B_DTEB_S  18
-/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM0B triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN0_B_DT0    0x00000003U
-#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
-#define MCPWM_GEN0_B_DT0_V  0x00000003U
-#define MCPWM_GEN0_B_DT0_S  20
-/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_DT1    0x00000003U
-#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
-#define MCPWM_GEN0_B_DT1_V  0x00000003U
-#define MCPWM_GEN0_B_DT1_S  22
-
-/** MCPWM_DT0_CFG_REG register
- *  dead time type selection and configuration
- */
-#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58)
-/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
-#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB0_FED_UPMETHOD_S  0
-/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
-#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB0_RED_UPMETHOD_S  4
-/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB0_DEB_MODE    (BIT(8))
-#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
-#define MCPWM_DB0_DEB_MODE_V  0x00000001U
-#define MCPWM_DB0_DEB_MODE_S  8
-/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
-#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB0_A_OUTSWAP_S  9
-/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
-#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB0_B_OUTSWAP_S  10
-/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DB0_RED_INSEL    (BIT(11))
-#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
-#define MCPWM_DB0_RED_INSEL_V  0x00000001U
-#define MCPWM_DB0_RED_INSEL_S  11
-/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DB0_FED_INSEL    (BIT(12))
-#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
-#define MCPWM_DB0_FED_INSEL_V  0x00000001U
-#define MCPWM_DB0_FED_INSEL_S  12
-/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
-#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB0_RED_OUTINVERT_S  13
-/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
-#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB0_FED_OUTINVERT_S  14
-/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
-#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB0_A_OUTBYPASS_S  15
-/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
-#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB0_B_OUTBYPASS_S  16
-/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DB0_CLK_SEL    (BIT(17))
-#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
-#define MCPWM_DB0_CLK_SEL_V  0x00000001U
-#define MCPWM_DB0_CLK_SEL_S  17
-
-/** MCPWM_DT0_FED_CFG_REG register
- *  Shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c)
-/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DB0_FED    0x0000FFFFU
-#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
-#define MCPWM_DB0_FED_V  0x0000FFFFU
-#define MCPWM_DB0_FED_S  0
-
-/** MCPWM_DT0_RED_CFG_REG register
- *  Shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60)
-/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DB0_RED    0x0000FFFFU
-#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
-#define MCPWM_DB0_RED_V  0x0000FFFFU
-#define MCPWM_DB0_RED_S  0
-
-/** MCPWM_CARRIER0_CFG_REG register
- *  Carrier enable and configuratoin
- */
-#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64)
-/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
- */
-#define MCPWM_CHOPPER0_EN    (BIT(0))
-#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
-#define MCPWM_CHOPPER0_EN_V  0x00000001U
-#define MCPWM_CHOPPER0_EN_S  0
-/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
-#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER0_PRESCALE_S  1
-/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CHOPPER0_DUTY    0x00000007U
-#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
-#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER0_DUTY_S  5
-/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
-#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER0_OSHTWTH_S  8
-/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM0A and PWM0B for this submodule
- */
-#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
-#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER0_OUT_INVERT_S  12
-/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM0A and PWM0B for this submodule
- */
-#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
-#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER0_IN_INVERT_S  13
-
-/** MCPWM_FH0_CFG0_REG register
- *  Actions on PWM0A and PWM0B trip events
- */
-#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68)
-/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_SW_CBC    (BIT(0))
-#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
-#define MCPWM_TZ0_SW_CBC_V  0x00000001U
-#define MCPWM_TZ0_SW_CBC_S  0
-/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F2_CBC    (BIT(1))
-#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
-#define MCPWM_TZ0_F2_CBC_V  0x00000001U
-#define MCPWM_TZ0_F2_CBC_S  1
-/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F1_CBC    (BIT(2))
-#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
-#define MCPWM_TZ0_F1_CBC_V  0x00000001U
-#define MCPWM_TZ0_F1_CBC_S  2
-/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F0_CBC    (BIT(3))
-#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
-#define MCPWM_TZ0_F0_CBC_V  0x00000001U
-#define MCPWM_TZ0_F0_CBC_S  3
-/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_SW_OST    (BIT(4))
-#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
-#define MCPWM_TZ0_SW_OST_V  0x00000001U
-#define MCPWM_TZ0_SW_OST_S  4
-/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
- *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F2_OST    (BIT(5))
-#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
-#define MCPWM_TZ0_F2_OST_V  0x00000001U
-#define MCPWM_TZ0_F2_OST_S  5
-/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
- *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F1_OST    (BIT(6))
-#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
-#define MCPWM_TZ0_F1_OST_V  0x00000001U
-#define MCPWM_TZ0_F1_OST_S  6
-/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
- *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ0_F0_OST    (BIT(7))
-#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
-#define MCPWM_TZ0_F0_OST_V  0x00000001U
-#define MCPWM_TZ0_F0_OST_S  7
-/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_A_CBC_D    0x00000003U
-#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
-#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ0_A_CBC_D_S  8
-/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_A_CBC_U    0x00000003U
-#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
-#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ0_A_CBC_U_S  10
-/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_A_OST_D    0x00000003U
-#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
-#define MCPWM_TZ0_A_OST_D_V  0x00000003U
-#define MCPWM_TZ0_A_OST_D_S  12
-/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_A_OST_U    0x00000003U
-#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
-#define MCPWM_TZ0_A_OST_U_V  0x00000003U
-#define MCPWM_TZ0_A_OST_U_S  14
-/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_B_CBC_D    0x00000003U
-#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
-#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ0_B_CBC_D_S  16
-/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
- *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_B_CBC_U    0x00000003U
-#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
-#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ0_B_CBC_U_S  18
-/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_B_OST_D    0x00000003U
-#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
-#define MCPWM_TZ0_B_OST_D_V  0x00000003U
-#define MCPWM_TZ0_B_OST_D_S  20
-/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ0_B_OST_U    0x00000003U
-#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
-#define MCPWM_TZ0_B_OST_U_V  0x00000003U
-#define MCPWM_TZ0_B_OST_U_S  22
-
-/** MCPWM_FH0_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c)
-/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_TZ0_CLR_OST    (BIT(0))
-#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
-#define MCPWM_TZ0_CLR_OST_V  0x00000001U
-#define MCPWM_TZ0_CLR_OST_S  0
-/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP
- */
-#define MCPWM_TZ0_CBCPULSE    0x00000003U
-#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
-#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ0_CBCPULSE_S  1
-/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
-#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ0_FORCE_CBC_S  3
-/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_TZ0_FORCE_OST    (BIT(4))
-#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
-#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ0_FORCE_OST_S  4
-
-/** MCPWM_FH0_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70)
-/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_TZ0_CBC_ON    (BIT(0))
-#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
-#define MCPWM_TZ0_CBC_ON_V  0x00000001U
-#define MCPWM_TZ0_CBC_ON_S  0
-/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_TZ0_OST_ON    (BIT(1))
-#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
-#define MCPWM_TZ0_OST_ON_V  0x00000001U
-#define MCPWM_TZ0_OST_ON_S  1
-
-/** MCPWM_GEN1_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74)
-/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 1 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR1_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR1_A_UPMETHOD_M  (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S)
-#define MCPWM_CMPR1_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR1_A_UPMETHOD_S  0
-/** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 1 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR1_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR1_B_UPMETHOD_M  (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S)
-#define MCPWM_CMPR1_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR1_B_UPMETHOD_S  4
-/** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR1_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR1_A_SHDW_FULL_M  (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S)
-#define MCPWM_CMPR1_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR1_A_SHDW_FULL_S  8
-/** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR1_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR1_B_SHDW_FULL_M  (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S)
-#define MCPWM_CMPR1_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR1_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN1_TSTMP_A_REG register
- *  Shadow register for register A.
- */
-#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78)
-/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 1 time stamp A's shadow register
- */
-#define MCPWM_CMPR1_A    0x0000FFFFU
-#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
-#define MCPWM_CMPR1_A_V  0x0000FFFFU
-#define MCPWM_CMPR1_A_S  0
-
-/** MCPWM_GEN1_TSTMP_B_REG register
- *  Shadow register for register B.
- */
-#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c)
-/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 1 time stamp B's shadow register
- */
-#define MCPWM_CMPR1_B    0x0000FFFFU
-#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
-#define MCPWM_CMPR1_B_V  0x0000FFFFU
-#define MCPWM_CMPR1_B_S  0
-
-/** MCPWM_GEN1_CFG0_REG register
- *  Fault event T0 and T1 handling
- */
-#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80)
-/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 1's active register of configuration. When all bits
- *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
- *  1:sync;when bit3 is set to 1:disable the update.
- */
-#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
-#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_S  0
-/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 1 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN1_T0_SEL    0x00000007U
-#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
-#define MCPWM_GEN1_T0_SEL_V  0x00000007U
-#define MCPWM_GEN1_T0_SEL_S  4
-/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 1 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN1_T1_SEL    0x00000007U
-#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
-#define MCPWM_GEN1_T1_SEL_V  0x00000007U
-#define MCPWM_GEN1_T1_SEL_S  7
-
-/** MCPWM_GEN1_FORCE_REG register
- *  Permissives to force PWM1A and PWM1B outputs by software
- */
-#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84)
-/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator 1. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM1A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
-#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_A_NCIFORCE_S  10
-/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM1B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
-#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_B_NCIFORCE_S  13
-/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN1_A_REG register
- *  Actions triggered by events on PWM1A
- */
-#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88)
-/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM1A triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN1_A_UTEZ    0x00000003U
-#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
-#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_UTEZ_S  0
-/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM1A triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN1_A_UTEP    0x00000003U
-#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
-#define MCPWM_GEN1_A_UTEP_V  0x00000003U
-#define MCPWM_GEN1_A_UTEP_S  2
-/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM1A triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN1_A_UTEA    0x00000003U
-#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
-#define MCPWM_GEN1_A_UTEA_V  0x00000003U
-#define MCPWM_GEN1_A_UTEA_S  4
-/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM1A triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN1_A_UTEB    0x00000003U
-#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
-#define MCPWM_GEN1_A_UTEB_V  0x00000003U
-#define MCPWM_GEN1_A_UTEB_S  6
-/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM1A triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN1_A_UT0    0x00000003U
-#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
-#define MCPWM_GEN1_A_UT0_V  0x00000003U
-#define MCPWM_GEN1_A_UT0_S  8
-/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM1A triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN1_A_UT1    0x00000003U
-#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
-#define MCPWM_GEN1_A_UT1_V  0x00000003U
-#define MCPWM_GEN1_A_UT1_S  10
-/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM1A triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN1_A_DTEZ    0x00000003U
-#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
-#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_DTEZ_S  12
-/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM1A triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN1_A_DTEP    0x00000003U
-#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
-#define MCPWM_GEN1_A_DTEP_V  0x00000003U
-#define MCPWM_GEN1_A_DTEP_S  14
-/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM1A triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN1_A_DTEA    0x00000003U
-#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
-#define MCPWM_GEN1_A_DTEA_V  0x00000003U
-#define MCPWM_GEN1_A_DTEA_S  16
-/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM1A triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN1_A_DTEB    0x00000003U
-#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
-#define MCPWM_GEN1_A_DTEB_V  0x00000003U
-#define MCPWM_GEN1_A_DTEB_S  18
-/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM1A triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN1_A_DT0    0x00000003U
-#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
-#define MCPWM_GEN1_A_DT0_V  0x00000003U
-#define MCPWM_GEN1_A_DT0_S  20
-/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_DT1    0x00000003U
-#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
-#define MCPWM_GEN1_A_DT1_V  0x00000003U
-#define MCPWM_GEN1_A_DT1_S  22
-
-/** MCPWM_GEN1_B_REG register
- *  Actions triggered by events on PWM1B
- */
-#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c)
-/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM1B triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN1_B_UTEZ    0x00000003U
-#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
-#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_UTEZ_S  0
-/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM1B triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN1_B_UTEP    0x00000003U
-#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
-#define MCPWM_GEN1_B_UTEP_V  0x00000003U
-#define MCPWM_GEN1_B_UTEP_S  2
-/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM1B triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN1_B_UTEA    0x00000003U
-#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
-#define MCPWM_GEN1_B_UTEA_V  0x00000003U
-#define MCPWM_GEN1_B_UTEA_S  4
-/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM1B triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN1_B_UTEB    0x00000003U
-#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
-#define MCPWM_GEN1_B_UTEB_V  0x00000003U
-#define MCPWM_GEN1_B_UTEB_S  6
-/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM1B triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN1_B_UT0    0x00000003U
-#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
-#define MCPWM_GEN1_B_UT0_V  0x00000003U
-#define MCPWM_GEN1_B_UT0_S  8
-/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM1B triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN1_B_UT1    0x00000003U
-#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
-#define MCPWM_GEN1_B_UT1_V  0x00000003U
-#define MCPWM_GEN1_B_UT1_S  10
-/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM1B triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN1_B_DTEZ    0x00000003U
-#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
-#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_DTEZ_S  12
-/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM1B triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN1_B_DTEP    0x00000003U
-#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
-#define MCPWM_GEN1_B_DTEP_V  0x00000003U
-#define MCPWM_GEN1_B_DTEP_S  14
-/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM1B triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN1_B_DTEA    0x00000003U
-#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
-#define MCPWM_GEN1_B_DTEA_V  0x00000003U
-#define MCPWM_GEN1_B_DTEA_S  16
-/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM1B triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN1_B_DTEB    0x00000003U
-#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
-#define MCPWM_GEN1_B_DTEB_V  0x00000003U
-#define MCPWM_GEN1_B_DTEB_S  18
-/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM1B triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN1_B_DT0    0x00000003U
-#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
-#define MCPWM_GEN1_B_DT0_V  0x00000003U
-#define MCPWM_GEN1_B_DT0_S  20
-/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_DT1    0x00000003U
-#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
-#define MCPWM_GEN1_B_DT1_V  0x00000003U
-#define MCPWM_GEN1_B_DT1_S  22
-
-/** MCPWM_DT1_CFG_REG register
- *  dead time type selection and configuration
- */
-#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90)
-/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (falling edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
-#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB1_FED_UPMETHOD_S  0
-/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register. 0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
-#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB1_RED_UPMETHOD_S  4
-/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB1_DEB_MODE    (BIT(8))
-#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
-#define MCPWM_DB1_DEB_MODE_V  0x00000001U
-#define MCPWM_DB1_DEB_MODE_S  8
-/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
-#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB1_A_OUTSWAP_S  9
-/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
-#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB1_B_OUTSWAP_S  10
-/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DB1_RED_INSEL    (BIT(11))
-#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
-#define MCPWM_DB1_RED_INSEL_V  0x00000001U
-#define MCPWM_DB1_RED_INSEL_S  11
-/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DB1_FED_INSEL    (BIT(12))
-#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
-#define MCPWM_DB1_FED_INSEL_V  0x00000001U
-#define MCPWM_DB1_FED_INSEL_S  12
-/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
-#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB1_RED_OUTINVERT_S  13
-/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
-#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB1_FED_OUTINVERT_S  14
-/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
-#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB1_A_OUTBYPASS_S  15
-/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
-#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB1_B_OUTBYPASS_S  16
-/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DB1_CLK_SEL    (BIT(17))
-#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
-#define MCPWM_DB1_CLK_SEL_V  0x00000001U
-#define MCPWM_DB1_CLK_SEL_S  17
-
-/** MCPWM_DT1_FED_CFG_REG register
- *  Shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94)
-/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DB1_FED    0x0000FFFFU
-#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
-#define MCPWM_DB1_FED_V  0x0000FFFFU
-#define MCPWM_DB1_FED_S  0
-
-/** MCPWM_DT1_RED_CFG_REG register
- *  Shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98)
-/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DB1_RED    0x0000FFFFU
-#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
-#define MCPWM_DB1_RED_V  0x0000FFFFU
-#define MCPWM_DB1_RED_S  0
-
-/** MCPWM_CARRIER1_CFG_REG register
- *  Carrier enable and configuratoin
- */
-#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c)
-/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier1 function is enabled. When cleared, carrier1 is bypassed
- */
-#define MCPWM_CHOPPER1_EN    (BIT(0))
-#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
-#define MCPWM_CHOPPER1_EN_V  0x00000001U
-#define MCPWM_CHOPPER1_EN_S  0
-/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
-#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER1_PRESCALE_S  1
-/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CHOPPER1_DUTY    0x00000007U
-#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
-#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER1_DUTY_S  5
-/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
-#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER1_OSHTWTH_S  8
-/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM1A and PWM1B for this submodule
- */
-#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
-#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER1_OUT_INVERT_S  12
-/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM1A and PWM1B for this submodule
- */
-#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
-#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER1_IN_INVERT_S  13
-
-/** MCPWM_FH1_CFG0_REG register
- *  Actions on PWM1A and PWM1B trip events
- */
-#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0)
-/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_SW_CBC    (BIT(0))
-#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
-#define MCPWM_TZ1_SW_CBC_V  0x00000001U
-#define MCPWM_TZ1_SW_CBC_S  0
-/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F2_CBC    (BIT(1))
-#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
-#define MCPWM_TZ1_F2_CBC_V  0x00000001U
-#define MCPWM_TZ1_F2_CBC_S  1
-/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F1_CBC    (BIT(2))
-#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
-#define MCPWM_TZ1_F1_CBC_V  0x00000001U
-#define MCPWM_TZ1_F1_CBC_S  2
-/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F0_CBC    (BIT(3))
-#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
-#define MCPWM_TZ1_F0_CBC_V  0x00000001U
-#define MCPWM_TZ1_F0_CBC_S  3
-/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_SW_OST    (BIT(4))
-#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
-#define MCPWM_TZ1_SW_OST_V  0x00000001U
-#define MCPWM_TZ1_SW_OST_S  4
-/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
- *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F2_OST    (BIT(5))
-#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
-#define MCPWM_TZ1_F2_OST_V  0x00000001U
-#define MCPWM_TZ1_F2_OST_S  5
-/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
- *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F1_OST    (BIT(6))
-#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
-#define MCPWM_TZ1_F1_OST_V  0x00000001U
-#define MCPWM_TZ1_F1_OST_S  6
-/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
- *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ1_F0_OST    (BIT(7))
-#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
-#define MCPWM_TZ1_F0_OST_V  0x00000001U
-#define MCPWM_TZ1_F0_OST_S  7
-/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_A_CBC_D    0x00000003U
-#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
-#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ1_A_CBC_D_S  8
-/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_A_CBC_U    0x00000003U
-#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
-#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ1_A_CBC_U_S  10
-/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0:
- *  do nothing,1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_A_OST_D    0x00000003U
-#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
-#define MCPWM_TZ1_A_OST_D_V  0x00000003U
-#define MCPWM_TZ1_A_OST_D_S  12
-/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_A_OST_U    0x00000003U
-#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
-#define MCPWM_TZ1_A_OST_U_V  0x00000003U
-#define MCPWM_TZ1_A_OST_U_S  14
-/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_B_CBC_D    0x00000003U
-#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
-#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ1_B_CBC_D_S  16
-/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_B_CBC_U    0x00000003U
-#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
-#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ1_B_CBC_U_S  18
-/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_B_OST_D    0x00000003U
-#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
-#define MCPWM_TZ1_B_OST_D_V  0x00000003U
-#define MCPWM_TZ1_B_OST_D_S  20
-/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ1_B_OST_U    0x00000003U
-#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
-#define MCPWM_TZ1_B_OST_U_V  0x00000003U
-#define MCPWM_TZ1_B_OST_U_S  22
-
-/** MCPWM_FH1_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4)
-/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_TZ1_CLR_OST    (BIT(0))
-#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
-#define MCPWM_TZ1_CLR_OST_V  0x00000001U
-#define MCPWM_TZ1_CLR_OST_S  0
-/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP
- */
-#define MCPWM_TZ1_CBCPULSE    0x00000003U
-#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
-#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ1_CBCPULSE_S  1
-/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
-#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ1_FORCE_CBC_S  3
-/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_TZ1_FORCE_OST    (BIT(4))
-#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
-#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ1_FORCE_OST_S  4
-
-/** MCPWM_FH1_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8)
-/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_TZ1_CBC_ON    (BIT(0))
-#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
-#define MCPWM_TZ1_CBC_ON_V  0x00000001U
-#define MCPWM_TZ1_CBC_ON_S  0
-/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_TZ1_OST_ON    (BIT(1))
-#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
-#define MCPWM_TZ1_OST_ON_V  0x00000001U
-#define MCPWM_TZ1_OST_ON_S  1
-
-/** MCPWM_GEN2_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac)
-/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 2 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR2_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR2_A_UPMETHOD_M  (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S)
-#define MCPWM_CMPR2_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR2_A_UPMETHOD_S  0
-/** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 2 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_CMPR2_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR2_B_UPMETHOD_M  (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S)
-#define MCPWM_CMPR2_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR2_B_UPMETHOD_S  4
-/** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR2_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR2_A_SHDW_FULL_M  (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S)
-#define MCPWM_CMPR2_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR2_A_SHDW_FULL_S  8
-/** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_CMPR2_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR2_B_SHDW_FULL_M  (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S)
-#define MCPWM_CMPR2_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR2_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN2_TSTMP_A_REG register
- *  Shadow register for register A.
- */
-#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0)
-/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 2 time stamp A's shadow register
- */
-#define MCPWM_CMPR2_A    0x0000FFFFU
-#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
-#define MCPWM_CMPR2_A_V  0x0000FFFFU
-#define MCPWM_CMPR2_A_S  0
-
-/** MCPWM_GEN2_TSTMP_B_REG register
- *  Shadow register for register B.
- */
-#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4)
-/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 2 time stamp B's shadow register
- */
-#define MCPWM_CMPR2_B    0x0000FFFFU
-#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
-#define MCPWM_CMPR2_B_V  0x0000FFFFU
-#define MCPWM_CMPR2_B_S  0
-
-/** MCPWM_GEN2_CFG0_REG register
- *  Fault event T0 and T1 handling
- */
-#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8)
-/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 2's active register of configuration. 0:
- *  immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is
- *  set to 1:disable the update.
- */
-#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
-#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_S  0
-/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 2 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN2_T0_SEL    0x00000007U
-#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
-#define MCPWM_GEN2_T0_SEL_V  0x00000007U
-#define MCPWM_GEN2_T0_SEL_S  4
-/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 2 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN2_T1_SEL    0x00000007U
-#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
-#define MCPWM_GEN2_T1_SEL_V  0x00000007U
-#define MCPWM_GEN2_T1_SEL_S  7
-
-/** MCPWM_GEN2_FORCE_REG register
- *  Permissives to force PWM2A and PWM2B outputs by software
- */
-#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc)
-/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator 2. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM2A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
-#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_A_NCIFORCE_S  10
-/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM2B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
-#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_B_NCIFORCE_S  13
-/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN2_A_REG register
- *  Actions triggered by events on PWM2A
- */
-#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0)
-/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM2A triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN2_A_UTEZ    0x00000003U
-#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
-#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_UTEZ_S  0
-/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM2A triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN2_A_UTEP    0x00000003U
-#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
-#define MCPWM_GEN2_A_UTEP_V  0x00000003U
-#define MCPWM_GEN2_A_UTEP_S  2
-/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM2A triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN2_A_UTEA    0x00000003U
-#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
-#define MCPWM_GEN2_A_UTEA_V  0x00000003U
-#define MCPWM_GEN2_A_UTEA_S  4
-/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM2A triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN2_A_UTEB    0x00000003U
-#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
-#define MCPWM_GEN2_A_UTEB_V  0x00000003U
-#define MCPWM_GEN2_A_UTEB_S  6
-/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM2A triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN2_A_UT0    0x00000003U
-#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
-#define MCPWM_GEN2_A_UT0_V  0x00000003U
-#define MCPWM_GEN2_A_UT0_S  8
-/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM2A triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN2_A_UT1    0x00000003U
-#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
-#define MCPWM_GEN2_A_UT1_V  0x00000003U
-#define MCPWM_GEN2_A_UT1_S  10
-/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM2A triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN2_A_DTEZ    0x00000003U
-#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
-#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_DTEZ_S  12
-/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM2A triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN2_A_DTEP    0x00000003U
-#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
-#define MCPWM_GEN2_A_DTEP_V  0x00000003U
-#define MCPWM_GEN2_A_DTEP_S  14
-/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM2A triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN2_A_DTEA    0x00000003U
-#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
-#define MCPWM_GEN2_A_DTEA_V  0x00000003U
-#define MCPWM_GEN2_A_DTEA_S  16
-/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM2A triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN2_A_DTEB    0x00000003U
-#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
-#define MCPWM_GEN2_A_DTEB_V  0x00000003U
-#define MCPWM_GEN2_A_DTEB_S  18
-/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM2A triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN2_A_DT0    0x00000003U
-#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
-#define MCPWM_GEN2_A_DT0_V  0x00000003U
-#define MCPWM_GEN2_A_DT0_S  20
-/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_DT1    0x00000003U
-#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
-#define MCPWM_GEN2_A_DT1_V  0x00000003U
-#define MCPWM_GEN2_A_DT1_S  22
-
-/** MCPWM_GEN2_B_REG register
- *  Actions triggered by events on PWM2B
- */
-#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4)
-/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM2B triggered by event TEZ when timer increasing
- */
-#define MCPWM_GEN2_B_UTEZ    0x00000003U
-#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
-#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_UTEZ_S  0
-/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM2B triggered by event TEP when timer increasing
- */
-#define MCPWM_GEN2_B_UTEP    0x00000003U
-#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
-#define MCPWM_GEN2_B_UTEP_V  0x00000003U
-#define MCPWM_GEN2_B_UTEP_S  2
-/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM2B triggered by event TEA when timer increasing
- */
-#define MCPWM_GEN2_B_UTEA    0x00000003U
-#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
-#define MCPWM_GEN2_B_UTEA_V  0x00000003U
-#define MCPWM_GEN2_B_UTEA_S  4
-/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM2B triggered by event TEB when timer increasing
- */
-#define MCPWM_GEN2_B_UTEB    0x00000003U
-#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
-#define MCPWM_GEN2_B_UTEB_V  0x00000003U
-#define MCPWM_GEN2_B_UTEB_S  6
-/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM2B triggered by event_t0 when timer increasing
- */
-#define MCPWM_GEN2_B_UT0    0x00000003U
-#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
-#define MCPWM_GEN2_B_UT0_V  0x00000003U
-#define MCPWM_GEN2_B_UT0_S  8
-/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM2B triggered by event_t1 when timer increasing
- */
-#define MCPWM_GEN2_B_UT1    0x00000003U
-#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
-#define MCPWM_GEN2_B_UT1_V  0x00000003U
-#define MCPWM_GEN2_B_UT1_S  10
-/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM2B triggered by event TEZ when timer decreasing
- */
-#define MCPWM_GEN2_B_DTEZ    0x00000003U
-#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
-#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_DTEZ_S  12
-/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM2B triggered by event TEP when timer decreasing
- */
-#define MCPWM_GEN2_B_DTEP    0x00000003U
-#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
-#define MCPWM_GEN2_B_DTEP_V  0x00000003U
-#define MCPWM_GEN2_B_DTEP_S  14
-/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM2B triggered by event TEA when timer decreasing
- */
-#define MCPWM_GEN2_B_DTEA    0x00000003U
-#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
-#define MCPWM_GEN2_B_DTEA_V  0x00000003U
-#define MCPWM_GEN2_B_DTEA_S  16
-/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM2B triggered by event TEB when timer decreasing
- */
-#define MCPWM_GEN2_B_DTEB    0x00000003U
-#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
-#define MCPWM_GEN2_B_DTEB_V  0x00000003U
-#define MCPWM_GEN2_B_DTEB_S  18
-/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM2B triggered by event_t0 when timer decreasing
- */
-#define MCPWM_GEN2_B_DT0    0x00000003U
-#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
-#define MCPWM_GEN2_B_DT0_V  0x00000003U
-#define MCPWM_GEN2_B_DT0_S  20
-/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_DT1    0x00000003U
-#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
-#define MCPWM_GEN2_B_DT1_V  0x00000003U
-#define MCPWM_GEN2_B_DT1_S  22
-
-/** MCPWM_DT2_CFG_REG register
- *  dead time type selection and configuration
- */
-#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8)
-/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (falling edge delay) active register.  0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
-#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB2_FED_UPMETHOD_S  0
-/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register.  0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
-#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB2_RED_UPMETHOD_S  4
-/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB2_DEB_MODE    (BIT(8))
-#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
-#define MCPWM_DB2_DEB_MODE_V  0x00000001U
-#define MCPWM_DB2_DEB_MODE_S  8
-/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
-#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB2_A_OUTSWAP_S  9
-/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
-#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB2_B_OUTSWAP_S  10
-/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DB2_RED_INSEL    (BIT(11))
-#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
-#define MCPWM_DB2_RED_INSEL_V  0x00000001U
-#define MCPWM_DB2_RED_INSEL_S  11
-/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DB2_FED_INSEL    (BIT(12))
-#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
-#define MCPWM_DB2_FED_INSEL_V  0x00000001U
-#define MCPWM_DB2_FED_INSEL_S  12
-/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
-#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB2_RED_OUTINVERT_S  13
-/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
-#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB2_FED_OUTINVERT_S  14
-/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
-#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB2_A_OUTBYPASS_S  15
-/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
-#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB2_B_OUTBYPASS_S  16
-/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DB2_CLK_SEL    (BIT(17))
-#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
-#define MCPWM_DB2_CLK_SEL_V  0x00000001U
-#define MCPWM_DB2_CLK_SEL_S  17
-
-/** MCPWM_DT2_FED_CFG_REG register
- *  Shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc)
-/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DB2_FED    0x0000FFFFU
-#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
-#define MCPWM_DB2_FED_V  0x0000FFFFU
-#define MCPWM_DB2_FED_S  0
-
-/** MCPWM_DT2_RED_CFG_REG register
- *  Shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0)
-/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DB2_RED    0x0000FFFFU
-#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
-#define MCPWM_DB2_RED_V  0x0000FFFFU
-#define MCPWM_DB2_RED_S  0
-
-/** MCPWM_CARRIER2_CFG_REG register
- *  Carrier enable and configuratoin
- */
-#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4)
-/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier2 function is enabled. When cleared, carrier2 is bypassed
- */
-#define MCPWM_CHOPPER2_EN    (BIT(0))
-#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
-#define MCPWM_CHOPPER2_EN_V  0x00000001U
-#define MCPWM_CHOPPER2_EN_S  0
-/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
-#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER2_PRESCALE_S  1
-/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CHOPPER2_DUTY    0x00000007U
-#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
-#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER2_DUTY_S  5
-/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
-#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER2_OSHTWTH_S  8
-/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM2A and PWM2B for this submodule
- */
-#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
-#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER2_OUT_INVERT_S  12
-/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM2A and PWM2B for this submodule
- */
-#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
-#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER2_IN_INVERT_S  13
-
-/** MCPWM_FH2_CFG0_REG register
- *  Actions on PWM2A and PWM2B trip events
- */
-#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8)
-/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_SW_CBC    (BIT(0))
-#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
-#define MCPWM_TZ2_SW_CBC_V  0x00000001U
-#define MCPWM_TZ2_SW_CBC_S  0
-/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F2_CBC    (BIT(1))
-#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
-#define MCPWM_TZ2_F2_CBC_V  0x00000001U
-#define MCPWM_TZ2_F2_CBC_S  1
-/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F1_CBC    (BIT(2))
-#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
-#define MCPWM_TZ2_F1_CBC_V  0x00000001U
-#define MCPWM_TZ2_F1_CBC_S  2
-/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F0_CBC    (BIT(3))
-#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
-#define MCPWM_TZ2_F0_CBC_V  0x00000001U
-#define MCPWM_TZ2_F0_CBC_S  3
-/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_SW_OST    (BIT(4))
-#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
-#define MCPWM_TZ2_SW_OST_V  0x00000001U
-#define MCPWM_TZ2_SW_OST_S  4
-/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
- *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F2_OST    (BIT(5))
-#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
-#define MCPWM_TZ2_F2_OST_V  0x00000001U
-#define MCPWM_TZ2_F2_OST_S  5
-/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
- *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F1_OST    (BIT(6))
-#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
-#define MCPWM_TZ2_F1_OST_V  0x00000001U
-#define MCPWM_TZ2_F1_OST_S  6
-/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
- *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_TZ2_F0_OST    (BIT(7))
-#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
-#define MCPWM_TZ2_F0_OST_V  0x00000001U
-#define MCPWM_TZ2_F0_OST_S  7
-/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_A_CBC_D    0x00000003U
-#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
-#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ2_A_CBC_D_S  8
-/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_A_CBC_U    0x00000003U
-#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
-#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ2_A_CBC_U_S  10
-/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_A_OST_D    0x00000003U
-#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
-#define MCPWM_TZ2_A_OST_D_V  0x00000003U
-#define MCPWM_TZ2_A_OST_D_S  12
-/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_A_OST_U    0x00000003U
-#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
-#define MCPWM_TZ2_A_OST_U_V  0x00000003U
-#define MCPWM_TZ2_A_OST_U_S  14
-/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_B_CBC_D    0x00000003U
-#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
-#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ2_B_CBC_D_S  16
-/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_B_CBC_U    0x00000003U
-#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
-#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ2_B_CBC_U_S  18
-/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_B_OST_D    0x00000003U
-#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
-#define MCPWM_TZ2_B_OST_D_V  0x00000003U
-#define MCPWM_TZ2_B_OST_D_S  20
-/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_TZ2_B_OST_U    0x00000003U
-#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
-#define MCPWM_TZ2_B_OST_U_V  0x00000003U
-#define MCPWM_TZ2_B_OST_U_S  22
-
-/** MCPWM_FH2_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc)
-/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_TZ2_CLR_OST    (BIT(0))
-#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
-#define MCPWM_TZ2_CLR_OST_V  0x00000001U
-#define MCPWM_TZ2_CLR_OST_S  0
-/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP
- */
-#define MCPWM_TZ2_CBCPULSE    0x00000003U
-#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
-#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ2_CBCPULSE_S  1
-/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
-#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ2_FORCE_CBC_S  3
-/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_TZ2_FORCE_OST    (BIT(4))
-#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
-#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ2_FORCE_OST_S  4
-
-/** MCPWM_FH2_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0)
-/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_TZ2_CBC_ON    (BIT(0))
-#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
-#define MCPWM_TZ2_CBC_ON_V  0x00000001U
-#define MCPWM_TZ2_CBC_ON_S  0
-/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_TZ2_OST_ON    (BIT(1))
-#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
-#define MCPWM_TZ2_OST_ON_V  0x00000001U
-#define MCPWM_TZ2_OST_ON_S  1
-
-/** MCPWM_FAULT_DETECT_REG register
- *  Fault detection configuration and status
- */
-#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4)
-/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, event_f0 generation is enabled
- */
-#define MCPWM_F0_EN    (BIT(0))
-#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
-#define MCPWM_F0_EN_V  0x00000001U
-#define MCPWM_F0_EN_S  0
-/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
- *  When set, event_f1 generation is enabled
- */
-#define MCPWM_F1_EN    (BIT(1))
-#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
-#define MCPWM_F1_EN_V  0x00000001U
-#define MCPWM_F1_EN_S  1
-/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
- *  When set, event_f2 generation is enabled
- */
-#define MCPWM_F2_EN    (BIT(2))
-#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
-#define MCPWM_F2_EN_V  0x00000001U
-#define MCPWM_F2_EN_S  2
-/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
- *  Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
- *  level high
- */
-#define MCPWM_F0_POLE    (BIT(3))
-#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
-#define MCPWM_F0_POLE_V  0x00000001U
-#define MCPWM_F0_POLE_S  3
-/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
- *  Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
- *  level high
- */
-#define MCPWM_F1_POLE    (BIT(4))
-#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
-#define MCPWM_F1_POLE_V  0x00000001U
-#define MCPWM_F1_POLE_S  4
-/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
- *  Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
- *  level high
- */
-#define MCPWM_F2_POLE    (BIT(5))
-#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
-#define MCPWM_F2_POLE_V  0x00000001U
-#define MCPWM_F2_POLE_S  5
-/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
- *  Set and reset by hardware. If set, event_f0 is on going
- */
-#define MCPWM_EVENT_F0    (BIT(6))
-#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
-#define MCPWM_EVENT_F0_V  0x00000001U
-#define MCPWM_EVENT_F0_S  6
-/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
- *  Set and reset by hardware. If set, event_f1 is on going
- */
-#define MCPWM_EVENT_F1    (BIT(7))
-#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
-#define MCPWM_EVENT_F1_V  0x00000001U
-#define MCPWM_EVENT_F1_S  7
-/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, event_f2 is on going
- */
-#define MCPWM_EVENT_F2    (BIT(8))
-#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
-#define MCPWM_EVENT_F2_V  0x00000001U
-#define MCPWM_EVENT_F2_S  8
-
-/** MCPWM_CAP_TIMER_CFG_REG register
- *  Configure capture timer
- */
-#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8)
-/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture timer incrementing under APB_clk is enabled.
- */
-#define MCPWM_CAP_TIMER_EN    (BIT(0))
-#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
-#define MCPWM_CAP_TIMER_EN_V  0x00000001U
-#define MCPWM_CAP_TIMER_EN_S  0
-/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
- *  When set, capture timer sync is enabled.
- */
-#define MCPWM_CAP_SYNCI_EN    (BIT(1))
-#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
-#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
-#define MCPWM_CAP_SYNCI_EN_S  1
-/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
- *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
- *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
- *  6: SYNC2 from GPIO matrix
- */
-#define MCPWM_CAP_SYNCI_SEL    0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
-#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_S  2
-/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
- *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
- *  timer is loaded with value in phase register.
- */
-#define MCPWM_CAP_SYNC_SW    (BIT(5))
-#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
-#define MCPWM_CAP_SYNC_SW_V  0x00000001U
-#define MCPWM_CAP_SYNC_SW_S  5
-
-/** MCPWM_CAP_TIMER_PHASE_REG register
- *  Phase for capture timer sync
- */
-#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec)
-/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
- *  Phase value for capture timer sync operation.
- */
-#define MCPWM_CAP_PHASE    0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
-#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_S  0
-
-/** MCPWM_CAP_CH0_CFG_REG register
- *  Capture channel 0 configuration and enable
- */
-#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 0 is enabled
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
- *  1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP0 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 0
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH1_CFG_REG register
- *  Capture channel 1 configuration and enable
- */
-#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4)
-/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 2 is enabled
- */
-#define MCPWM_CAP1_EN    (BIT(0))
-#define MCPWM_CAP1_EN_M  (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S)
-#define MCPWM_CAP1_EN_V  0x00000001U
-#define MCPWM_CAP1_EN_S  0
-/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP1_MODE    0x00000003U
-#define MCPWM_CAP1_MODE_M  (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S)
-#define MCPWM_CAP1_MODE_V  0x00000003U
-#define MCPWM_CAP1_MODE_S  1
-/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
- *  1
- */
-#define MCPWM_CAP1_PRESCALE    0x000000FFU
-#define MCPWM_CAP1_PRESCALE_M  (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S)
-#define MCPWM_CAP1_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP1_PRESCALE_S  3
-/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP1 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP1_IN_INVERT    (BIT(11))
-#define MCPWM_CAP1_IN_INVERT_M  (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S)
-#define MCPWM_CAP1_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP1_IN_INVERT_S  11
-/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 1
- */
-#define MCPWM_CAP1_SW    (BIT(12))
-#define MCPWM_CAP1_SW_M  (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S)
-#define MCPWM_CAP1_SW_V  0x00000001U
-#define MCPWM_CAP1_SW_S  12
-
-/** MCPWM_CAP_CH2_CFG_REG register
- *  Capture channel 2 configuration and enable
- */
-#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8)
-/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 2 is enabled
- */
-#define MCPWM_CAP2_EN    (BIT(0))
-#define MCPWM_CAP2_EN_M  (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S)
-#define MCPWM_CAP2_EN_V  0x00000001U
-#define MCPWM_CAP2_EN_S  0
-/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP2_MODE    0x00000003U
-#define MCPWM_CAP2_MODE_M  (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S)
-#define MCPWM_CAP2_MODE_V  0x00000003U
-#define MCPWM_CAP2_MODE_S  1
-/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
- *  1
- */
-#define MCPWM_CAP2_PRESCALE    0x000000FFU
-#define MCPWM_CAP2_PRESCALE_M  (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S)
-#define MCPWM_CAP2_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP2_PRESCALE_S  3
-/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP2 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP2_IN_INVERT    (BIT(11))
-#define MCPWM_CAP2_IN_INVERT_M  (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S)
-#define MCPWM_CAP2_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP2_IN_INVERT_S  11
-/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 2
- */
-#define MCPWM_CAP2_SW    (BIT(12))
-#define MCPWM_CAP2_SW_M  (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S)
-#define MCPWM_CAP2_SW_V  0x00000001U
-#define MCPWM_CAP2_SW_S  12
-
-/** MCPWM_CAP_CH0_REG register
- *  ch0 capture value status register
- */
-#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 0
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_CH1_REG register
- *  ch1 capture value status register
- */
-#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100)
-/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 1
- */
-#define MCPWM_CAP1_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP1_VALUE_M  (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S)
-#define MCPWM_CAP1_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP1_VALUE_S  0
-
-/** MCPWM_CAP_CH2_REG register
- *  ch2 capture value status register
- */
-#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104)
-/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 2
- */
-#define MCPWM_CAP2_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP2_VALUE_M  (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S)
-#define MCPWM_CAP2_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP2_VALUE_S  0
-
-/** MCPWM_CAP_STATUS_REG register
- *  Edge of last capture trigger
- */
-#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108)
-/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
- *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP0_EDGE    (BIT(0))
-#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
-#define MCPWM_CAP0_EDGE_V  0x00000001U
-#define MCPWM_CAP0_EDGE_S  0
-/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
- *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP1_EDGE    (BIT(1))
-#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
-#define MCPWM_CAP1_EDGE_V  0x00000001U
-#define MCPWM_CAP1_EDGE_S  1
-/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
- *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP2_EDGE    (BIT(2))
-#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
-#define MCPWM_CAP2_EDGE_V  0x00000001U
-#define MCPWM_CAP2_EDGE_S  2
-
-/** MCPWM_UPDATE_CFG_REG register
- *  Enable update.
- */
-#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c)
-/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
- *  The global enable of update of all active registers in MCPWM module
- */
-#define MCPWM_GLOBAL_UP_EN    (BIT(0))
-#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
-#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
-#define MCPWM_GLOBAL_UP_EN_S  0
-/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of all active
- *  registers in MCPWM module
- */
-#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
-#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
-#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
-#define MCPWM_GLOBAL_FORCE_UP_S  1
-/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
- *  are enabled
- */
-#define MCPWM_OP0_UP_EN    (BIT(2))
-#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
-#define MCPWM_OP0_UP_EN_V  0x00000001U
-#define MCPWM_OP0_UP_EN_S  2
-/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 0
- */
-#define MCPWM_OP0_FORCE_UP    (BIT(3))
-#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
-#define MCPWM_OP0_FORCE_UP_V  0x00000001U
-#define MCPWM_OP0_FORCE_UP_S  3
-/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
- *  are enabled
- */
-#define MCPWM_OP1_UP_EN    (BIT(4))
-#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
-#define MCPWM_OP1_UP_EN_V  0x00000001U
-#define MCPWM_OP1_UP_EN_S  4
-/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 1
- */
-#define MCPWM_OP1_FORCE_UP    (BIT(5))
-#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
-#define MCPWM_OP1_FORCE_UP_V  0x00000001U
-#define MCPWM_OP1_FORCE_UP_S  5
-/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
- *  are enabled
- */
-#define MCPWM_OP2_UP_EN    (BIT(6))
-#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
-#define MCPWM_OP2_UP_EN_V  0x00000001U
-#define MCPWM_OP2_UP_EN_S  6
-/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 2
- */
-#define MCPWM_OP2_FORCE_UP    (BIT(7))
-#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
-#define MCPWM_OP2_FORCE_UP_V  0x00000001U
-#define MCPWM_OP2_FORCE_UP_S  7
-
-/** MCPWM_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110)
-/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
-#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ENA_S  0
-/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
-#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ENA_S  1
-/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
-#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ENA_S  2
-/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
-#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
-/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
-#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
-/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
-#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
-/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
-#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ENA_S  6
-/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
-#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ENA_S  7
-/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
-#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ENA_S  8
-/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The enable bit for the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ENA    (BIT(9))
-#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
-#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_INT_ENA_S  9
-/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ENA    (BIT(10))
-#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
-#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_INT_ENA_S  10
-/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The enable bit for the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ENA    (BIT(11))
-#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
-#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_INT_ENA_S  11
-/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The enable bit for the interrupt triggered when event_f0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
-#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ENA_S  12
-/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The enable bit for the interrupt triggered when event_f1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
-#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ENA_S  13
-/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The enable bit for the interrupt triggered when event_f2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
-#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ENA_S  14
-/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
-#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ENA_S  15
-/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
-#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ENA_S  16
-/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
-#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ENA_S  17
-/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
-#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ENA_S  18
-/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
-#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ENA_S  19
-/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
-#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ENA_S  20
-/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
-#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ENA_S  21
-/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
-#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ENA_S  22
-/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
-#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ENA_S  23
-/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
-#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ENA_S  24
-/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
-#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ENA_S  25
-/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
-#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ENA_S  26
-/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_ENA    (BIT(27))
-#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
-#define MCPWM_CAP0_INT_ENA_V  0x00000001U
-#define MCPWM_CAP0_INT_ENA_S  27
-/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_ENA    (BIT(28))
-#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
-#define MCPWM_CAP1_INT_ENA_V  0x00000001U
-#define MCPWM_CAP1_INT_ENA_S  28
-/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_ENA    (BIT(29))
-#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
-#define MCPWM_CAP2_INT_ENA_V  0x00000001U
-#define MCPWM_CAP2_INT_ENA_S  29
-
-/** MCPWM_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114)
-/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
-#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_RAW_S  0
-/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
-#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_RAW_S  1
-/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
-#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_RAW_S  2
-/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
-#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
-/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
-#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
-/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
-#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
-/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
-#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_RAW_S  6
-/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
-#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_RAW_S  7
-/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
-#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_RAW_S  8
-/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_RAW    (BIT(9))
-#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
-#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_INT_RAW_S  9
-/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_RAW    (BIT(10))
-#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
-#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_INT_RAW_S  10
-/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_RAW    (BIT(11))
-#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
-#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_INT_RAW_S  11
-/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
-#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_RAW_S  12
-/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
-#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_RAW_S  13
-/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw status bit for the interrupt triggered when event_f2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
-#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_RAW_S  14
-/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
-#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_RAW_S  15
-/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
-#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_RAW_S  16
-/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
-#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_RAW_S  17
-/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
-#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_RAW_S  18
-/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
-#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_RAW_S  19
-/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
-#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_RAW_S  20
-/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
-#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_RAW_S  21
-/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
-#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_RAW_S  22
-/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
-#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_RAW_S  23
-/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
-#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
-#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_RAW_S  24
-/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
-#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
-#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_RAW_S  25
-/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
-#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
-#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_RAW_S  26
-/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_RAW    (BIT(27))
-#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
-#define MCPWM_CAP0_INT_RAW_V  0x00000001U
-#define MCPWM_CAP0_INT_RAW_S  27
-/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_RAW    (BIT(28))
-#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
-#define MCPWM_CAP1_INT_RAW_V  0x00000001U
-#define MCPWM_CAP1_INT_RAW_S  28
-/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_RAW    (BIT(29))
-#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
-#define MCPWM_CAP2_INT_RAW_V  0x00000001U
-#define MCPWM_CAP2_INT_RAW_S  29
-
-/** MCPWM_INT_ST_REG register
- *  Masked interrupt status
- */
-#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118)
-/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
-#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ST_S  0
-/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
-#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ST_S  1
-/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
-#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ST_S  2
-/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
-#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ST_S  3
-/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
-#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ST_S  4
-/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
-#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ST_S  5
-/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
-#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ST_S  6
-/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
-#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ST_S  7
-/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
-#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ST_S  8
-/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ST    (BIT(9))
-#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
-#define MCPWM_FAULT0_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_INT_ST_S  9
-/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ST    (BIT(10))
-#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
-#define MCPWM_FAULT1_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_INT_ST_S  10
-/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ST    (BIT(11))
-#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
-#define MCPWM_FAULT2_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_INT_ST_S  11
-/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
-#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ST_S  12
-/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
-#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ST_S  13
-/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
- *  The masked status bit for the interrupt triggered when event_f2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
-#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ST_S  14
-/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
-#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ST_S  15
-/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
-#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ST_S  16
-/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
-#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ST_S  17
-/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
-#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ST_S  18
-/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
-#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ST_S  19
-/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
-#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ST_S  20
-/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
-#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ST_S  21
-/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
-#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ST_S  22
-/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
-#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ST_S  23
-/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
-#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ST_S  24
-/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
-#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ST_S  25
-/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
-#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ST_S  26
-/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_ST    (BIT(27))
-#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
-#define MCPWM_CAP0_INT_ST_V  0x00000001U
-#define MCPWM_CAP0_INT_ST_S  27
-/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_ST    (BIT(28))
-#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
-#define MCPWM_CAP1_INT_ST_V  0x00000001U
-#define MCPWM_CAP1_INT_ST_S  28
-/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_ST    (BIT(29))
-#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
-#define MCPWM_CAP2_INT_ST_V  0x00000001U
-#define MCPWM_CAP2_INT_ST_S  29
-
-/** MCPWM_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c)
-/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
-#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_CLR_S  0
-/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
-#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_CLR_S  1
-/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
-#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_CLR_S  2
-/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
-#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
-/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
-#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
-/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
-#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
-/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
-#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_CLR_S  6
-/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
-#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_CLR_S  7
-/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
-#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_CLR_S  8
-/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_CLR    (BIT(9))
-#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
-#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_INT_CLR_S  9
-/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_CLR    (BIT(10))
-#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
-#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_INT_CLR_S  10
-/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_CLR    (BIT(11))
-#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
-#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_INT_CLR_S  11
-/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
-#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_CLR_S  12
-/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
-#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_CLR_S  13
-/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the interrupt triggered when event_f2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
-#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_CLR_S  14
-/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
-#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_CLR_S  15
-/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
-#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_CLR_S  16
-/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
-#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_CLR_S  17
-/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
-#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_CLR_S  18
-/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
-#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_CLR_S  19
-/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
-#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_CLR_S  20
-/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
-#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_CLR_S  21
-/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
-#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_CLR_S  22
-/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
-#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_CLR_S  23
-/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
-#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
-#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_CLR_S  24
-/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
-#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
-#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_CLR_S  25
-/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
-#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
-#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_CLR_S  26
-/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_CLR    (BIT(27))
-#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
-#define MCPWM_CAP0_INT_CLR_V  0x00000001U
-#define MCPWM_CAP0_INT_CLR_S  27
-/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_CLR    (BIT(28))
-#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
-#define MCPWM_CAP1_INT_CLR_V  0x00000001U
-#define MCPWM_CAP1_INT_CLR_S  28
-/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_CLR    (BIT(29))
-#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
-#define MCPWM_CAP2_INT_CLR_V  0x00000001U
-#define MCPWM_CAP2_INT_CLR_S  29
-
-/** MCPWM_EVT_EN_REG register
- *  MCPWM event enable register
- */
-#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120)
-/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
- *  set this bit high to enable timer0 stop event generate
- */
-#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
-#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
-#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_STOP_EN_S  0
-/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
- *  set this bit high to enable timer1 stop event generate
- */
-#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
-#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
-#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_STOP_EN_S  1
-/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
- *  set this bit high to enable timer2 stop event generate
- */
-#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
-#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
-#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_STOP_EN_S  2
-/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
- *  set this bit high to enable timer0 equal zero event generate
- */
-#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
-#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
-#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
-/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
- *  set this bit high to enable timer1 equal zero event generate
- */
-#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
-#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
-#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
-/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
- *  set this bit high to enable timer2 equal zero event generate
- */
-#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
-#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
-#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
-/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
- *  set this bit high to enable timer0 equal period event generate
- */
-#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
-#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
-#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEP_EN_S  6
-/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
- *  set this bit high to enable timer1 equal period event generate
- */
-#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
-#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
-#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEP_EN_S  7
-/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
- *  set this bit high to enable timer2 equal period event generate
- */
-#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
-#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
-#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEP_EN_S  8
-/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
- *  set this bit high to enable PWM generator0 timer equal a event generate
- */
-#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
-#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
-#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEA_EN_S  9
-/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
- *  set this bit high to enable PWM generator1 timer equal a event generate
- */
-#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
-#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
-#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEA_EN_S  10
-/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
- *  set this bit high to enable PWM generator2 timer equal a event generate
- */
-#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
-#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
-#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEA_EN_S  11
-/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
- *  set this bit high to enable PWM generator0 timer equal b event generate
- */
-#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
-#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
-#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEB_EN_S  12
-/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
- *  set this bit high to enable PWM generator1 timer equal b event generate
- */
-#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
-#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
-#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEB_EN_S  13
-/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
- *  set this bit high to enable PWM generator2 timer equal b event generate
- */
-#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
-#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
-#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEB_EN_S  14
-/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
- *  set this bit high to enable fault0 event generate
- */
-#define MCPWM_EVT_F0_EN    (BIT(15))
-#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
-#define MCPWM_EVT_F0_EN_V  0x00000001U
-#define MCPWM_EVT_F0_EN_S  15
-/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
- *  set this bit high to enable fault1 event generate
- */
-#define MCPWM_EVT_F1_EN    (BIT(16))
-#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
-#define MCPWM_EVT_F1_EN_V  0x00000001U
-#define MCPWM_EVT_F1_EN_S  16
-/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
- *  set this bit high to enable fault2 event generate
- */
-#define MCPWM_EVT_F2_EN    (BIT(17))
-#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
-#define MCPWM_EVT_F2_EN_V  0x00000001U
-#define MCPWM_EVT_F2_EN_S  17
-/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
- *  set this bit high to enable fault0 clear event generate
- */
-#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
-#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
-#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F0_CLR_EN_S  18
-/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  set this bit high to enable fault1 clear event generate
- */
-#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
-#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
-#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F1_CLR_EN_S  19
-/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  set this bit high to enable fault2 clear event generate
- */
-#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
-#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
-#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F2_CLR_EN_S  20
-/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
- *  set this bit high to enable cycle by cycle trip0 event generate
- */
-#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
-#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
-#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_CBC_EN_S  21
-/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
- *  set this bit high to enable cycle by cycle trip1 event generate
- */
-#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
-#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
-#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_CBC_EN_S  22
-/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
- *  set this bit high to enable cycle by cycle trip2 event generate
- */
-#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
-#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
-#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_CBC_EN_S  23
-/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
- *  set this bit high to enable one shot trip0 event generate
- */
-#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
-#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
-#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_OST_EN_S  24
-/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
- *  set this bit high to enable one shot trip1 event generate
- */
-#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
-#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
-#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_OST_EN_S  25
-/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
- *  set this bit high to enable one shot trip2 event generate
- */
-#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
-#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
-#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_OST_EN_S  26
-/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
- *  set this bit high to enable capture0 event generate
- */
-#define MCPWM_EVT_CAP0_EN    (BIT(27))
-#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
-#define MCPWM_EVT_CAP0_EN_V  0x00000001U
-#define MCPWM_EVT_CAP0_EN_S  27
-/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
- *  set this bit high to enable capture1 event generate
- */
-#define MCPWM_EVT_CAP1_EN    (BIT(28))
-#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
-#define MCPWM_EVT_CAP1_EN_V  0x00000001U
-#define MCPWM_EVT_CAP1_EN_S  28
-/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
- *  set this bit high to enable capture2 event generate
- */
-#define MCPWM_EVT_CAP2_EN    (BIT(29))
-#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
-#define MCPWM_EVT_CAP2_EN_V  0x00000001U
-#define MCPWM_EVT_CAP2_EN_S  29
-
-/** MCPWM_TASK_EN_REG register
- *  MCPWM task enable register
- */
-#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124)
-/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
- *  set this bit high to enable PWM generator0 timer stamp A's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
-#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
-#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
-/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
- *  set this bit high to enable PWM generator1 timer stamp A's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
-#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
-#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
-/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
- *  set this bit high to enable PWM generator2 timer stamp A's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
-#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
-#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
-/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
- *  set this bit high to enable PWM generator0 timer stamp B's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
-#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
-#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
-/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
- *  set this bit high to enable PWM generator1 timer stamp B's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
-#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
-#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
-/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
- *  set this bit high to enable PWM generator2 timer stamp B's shadow register update
- *  task receive
- */
-#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
-#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
-#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
-/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
- *  set this bit high to enable all PWM generate stop task receive
- */
-#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
-#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
-#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
-#define MCPWM_TASK_GEN_STOP_EN_S  6
-/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
- *  set this bit high to enable timer0 sync task receive
- */
-#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
-#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
-#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
-/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
- *  set this bit high to enable timer1 sync task receive
- */
-#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
-#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
-#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
-/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
- *  set this bit high to enable timer2 sync task receive
- */
-#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
-#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
-#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
-/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
- *  set this bit high to enable timer0 period update task receive
- */
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
-/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
- *  set this bit high to enable timer1 period update task receive
- */
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
-/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
- *  set this bit high to enable timer2 period update task receive
- */
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
-/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
- *  set this bit high to enable one shot trip0 task receive
- */
-#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
-#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
-#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ0_OST_EN_S  13
-/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
- *  set this bit high to enable one shot trip1 task receive
- */
-#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
-#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
-#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ1_OST_EN_S  14
-/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
- *  set this bit high to enable one shot trip2 task receive
- */
-#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
-#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
-#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ2_OST_EN_S  15
-/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
- *  set this bit high to enable one shot trip0 clear task receive
- */
-#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
-#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
-#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR0_OST_EN_S  16
-/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
- *  set this bit high to enable one shot trip1 clear task receive
- */
-#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
-#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
-#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR1_OST_EN_S  17
-/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
- *  set this bit high to enable one shot trip2 clear task receive
- */
-#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
-#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
-#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR2_OST_EN_S  18
-/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
- *  set this bit high to enable capture0 task receive
- */
-#define MCPWM_TASK_CAP0_EN    (BIT(19))
-#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
-#define MCPWM_TASK_CAP0_EN_V  0x00000001U
-#define MCPWM_TASK_CAP0_EN_S  19
-/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
- *  set this bit high to enable capture1 task receive
- */
-#define MCPWM_TASK_CAP1_EN    (BIT(20))
-#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
-#define MCPWM_TASK_CAP1_EN_V  0x00000001U
-#define MCPWM_TASK_CAP1_EN_S  20
-/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
- *  set this bit high to enable capture2 task receive
- */
-#define MCPWM_TASK_CAP2_EN    (BIT(21))
-#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
-#define MCPWM_TASK_CAP2_EN_V  0x00000001U
-#define MCPWM_TASK_CAP2_EN_S  21
-
-/** MCPWM_CLK_REG register
- *  MCPWM APB configuration register
- */
-#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x128)
-/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Force clock on for this register file
- */
-#define MCPWM_CLK_EN    (BIT(0))
-#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
-#define MCPWM_CLK_EN_V  0x00000001U
-#define MCPWM_CLK_EN_S  0
-
-/** MCPWM_VERSION_REG register
- *  Version register.
- */
-#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x12c)
-/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35656256;
- *  Version of this register file
- */
-#define MCPWM_DATE    0x0FFFFFFFU
-#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
-#define MCPWM_DATE_V  0x0FFFFFFFU
-#define MCPWM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/mcpwm_struct.h b/components/soc/esp32h2/include/soc/mcpwm_struct.h
deleted file mode 100644
index 1a91a623f6b..00000000000
--- a/components/soc/esp32h2/include/soc/mcpwm_struct.h
+++ /dev/null
@@ -1,1694 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Prescaler configuration */
-/** Type of clk_cfg register
- *  PWM clock prescaler register.
- */
-typedef union {
-    struct {
-        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
-         */
-        uint32_t clk_prescale:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_clk_cfg_reg_t;
-
-
-/** Group: MCPWM Timer Configuration and status */
-/** Type of timer_cfg0 register
- *  PWM timer period and update method configuration register.
- */
-typedef union {
-    struct {
-        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1)
-         */
-        uint32_t timer_prescale:8;
-        /** timer_period : R/W; bitpos: [23:8]; default: 255;
-         *  period shadow register of PWM timer
-         */
-        uint32_t timer_period:16;
-        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
-         *  Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2:
-         *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
-         */
-        uint32_t timer_period_upmethod:2;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg0_reg_t;
-
-/** Type of timer_cfg1 register
- *  PWM timer0 working mode and start/stop control configuration register.
- */
-typedef union {
-    struct {
-        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
-         *  PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1:
-         *  if timer0 starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer
-         *  starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP
-         *  here and below means the event that happens when the timer equals to period
-         */
-        uint32_t timer_start:3;
-        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
-         *  PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
-         *  mode
-         */
-        uint32_t timer_mod:2;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg1_reg_t;
-
-/** Type of timer_sync register
- *  PWM timer sync function configuration register.
- */
-typedef union {
-    struct {
-        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
-         *  When set, timer reloading with phase on sync input event is enabled.
-         */
-        uint32_t timer_synci_en:1;
-        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
-         *  Toggling this bit will trigger a software sync.
-         */
-        uint32_t timer_sync_sw:1;
-        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
-         *  PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
-         *  generate when toggling the reg_timer0_sync_sw bit
-         */
-        uint32_t timer_synco_sel:2;
-        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
-         *  phase for timer reload on sync event
-         */
-        uint32_t timer_phase:16;
-        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
-         *  Configure the PWM timer0's direction when timer mode is up-down mode:
-         *  0-increase,1-decrease
-         */
-        uint32_t timer_phase_direction:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} mcpwm_timer_sync_reg_t;
-
-/** Type of timer_status register
- *  PWM timer status register.
- */
-typedef union {
-    struct {
-        /** timer_value : RO; bitpos: [15:0]; default: 0;
-         *  current PWM timer counter value
-         */
-        uint32_t timer_value:16;
-        /** timer_direction : RO; bitpos: [16]; default: 0;
-         *  current PWM timer counter direction, 0: increment 1: decrement
-         */
-        uint32_t timer_direction:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} mcpwm_timer_status_reg_t;
-
-
-/** Group: Common configuration for MCPWM timers */
-/** Type of timer_synci_cfg register
- *  Synchronization input selection for three PWM timers.
- */
-typedef union {
-    struct {
-        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
-         *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer0_syncisel:3;
-        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
-         *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer1_syncisel:3;
-        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
-         *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer2_syncisel:3;
-        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
-         *  invert SYNC0 from GPIO matrix
-         */
-        uint32_t external_synci0_invert:1;
-        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
-         *  invert SYNC1 from GPIO matrix
-         */
-        uint32_t external_synci1_invert:1;
-        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
-         *  invert SYNC2 from GPIO matrix
-         */
-        uint32_t external_synci2_invert:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} mcpwm_timer_synci_cfg_reg_t;
-
-/** Type of operator_timersel register
- *  Select specific timer for PWM operators.
- */
-typedef union {
-    struct {
-        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
-         *  Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator0_timersel:2;
-        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
-         *  Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator1_timersel:2;
-        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
-         *  Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator2_timersel:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_operator_timersel_reg_t;
-
-
-/** Group: MCPWM Operator Configuration and Status */
-/** Type of gen_stmp_cfg register
- *  Transfer status and update method for time stamp registers A and B
- */
-typedef union {
-    struct {
-        /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for PWM generator time stamp A's active register. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
-         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
-         */
-        uint32_t cmpr_a_upmethod:4;
-        /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Update method for PWM generator time stamp B's active register. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
-         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
-         */
-        uint32_t cmpr_b_upmethod:4;
-        /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
-         *  Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is
-         *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
-         *  has been updated with shadow register latest value
-         */
-        uint32_t cmpr_a_shdw_full:1;
-        /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
-         *  Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is
-         *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
-         *  has been updated with shadow register latest value
-         */
-        uint32_t cmpr_b_shdw_full:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_gen_stmp_cfg_reg_t;
-
-/** Type of gen_tstmp register
- *  Shadow register for register B.
- */
-typedef union {
-    struct {
-        /** cmpr : R/W; bitpos: [15:0]; default: 0;
-         *  PWM generator time stamp's shadow register
-         */
-        uint32_t cmpr:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_tstmp_reg_t;
-
-/** Type of gen_cfg0 register
- *  Fault event T0 and T1 handling
- */
-typedef union {
-    struct {
-        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for PWM generator's active register of configuration. When all bits
-         *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
-         *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
-         */
-        uint32_t gen_cfg_upmethod:4;
-        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
-         *  Source selection for PWM generator event_t0, take effect immediately, 0:
-         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
-         */
-        uint32_t gen_t0_sel:3;
-        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
-         *  Source selection for PWM generator event_t1, take effect immediately, 0:
-         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
-         */
-        uint32_t gen_t1_sel:3;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_gen_cfg0_reg_t;
-
-/** Type of gen_force register
- *  Permissives to force PWM0A and PWM0B outputs by software
- */
-typedef union {
-    struct {
-        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
-         *  Updating method for continuous software force of PWM generator. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
-         *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
-         *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
-         *  generated when the timer's value equals to that of register A/B.)
-         */
-        uint32_t gen_cntuforce_upmethod:6;
-        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
-         *  Continuous software force mode for PWMnA. 0: disabled, 1: low, 2: high, 3: disabled
-         */
-        uint32_t gen_a_cntuforce_mode:2;
-        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
-         *  Continuous software force mode for PWMnB. 0: disabled, 1: low, 2: high, 3: disabled
-         */
-        uint32_t gen_b_cntuforce_mode:2;
-        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
-         *  Trigger of non-continuous immediate software-force event for PWMnA, a toggle will
-         *  trigger a force event.
-         */
-        uint32_t gen_a_nciforce:1;
-        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
-         *  non-continuous immediate software force mode for PWMnA, 0: disabled, 1: low, 2:
-         *  high, 3: disabled
-         */
-        uint32_t gen_a_nciforce_mode:2;
-        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
-         *  Trigger of non-continuous immediate software-force event for PWMnB, a toggle will
-         *  trigger a force event.
-         */
-        uint32_t gen_b_nciforce:1;
-        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
-         *  non-continuous immediate software force mode for PWMnB, 0: disabled, 1: low, 2:
-         *  high, 3: disabled
-         */
-        uint32_t gen_b_nciforce_mode:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_force_reg_t;
-
-/** Type of gen register
- *  Actions triggered by events on PWM0B
- */
-typedef union {
-    struct {
-        /** gen_utez : R/W; bitpos: [1:0]; default: 0;
-         *  Action on PWMnA/B triggered by event TEZ when timer increasing
-         */
-        uint32_t gen_utez:2;
-        /** gen_utep : R/W; bitpos: [3:2]; default: 0;
-         *  Action on PWMnA/B triggered by event TEP when timer increasing
-         */
-        uint32_t gen_utep:2;
-        /** gen_utea : R/W; bitpos: [5:4]; default: 0;
-         *  Action on PWMnA/B triggered by event TEA when timer increasing
-         */
-        uint32_t gen_utea:2;
-        /** gen_uteb : R/W; bitpos: [7:6]; default: 0;
-         *  Action on PWMnA/B triggered by event TEB when timer increasing
-         */
-        uint32_t gen_uteb:2;
-        /** gen_ut0 : R/W; bitpos: [9:8]; default: 0;
-         *  Action on PWMnA/B triggered by event_t0 when timer increasing
-         */
-        uint32_t gen_ut0:2;
-        /** gen_ut1 : R/W; bitpos: [11:10]; default: 0;
-         *  Action on PWMnA/B triggered by event_t1 when timer increasing
-         */
-        uint32_t gen_ut1:2;
-        /** gen_dtez : R/W; bitpos: [13:12]; default: 0;
-         *  Action on PWMnA/B triggered by event TEZ when timer decreasing
-         */
-        uint32_t gen_dtez:2;
-        /** gen_dtep : R/W; bitpos: [15:14]; default: 0;
-         *  Action on PWMnA/B triggered by event TEP when timer decreasing
-         */
-        uint32_t gen_dtep:2;
-        /** gen_dtea : R/W; bitpos: [17:16]; default: 0;
-         *  Action on PWMnA/B triggered by event TEA when timer decreasing
-         */
-        uint32_t gen_dtea:2;
-        /** gen_dteb : R/W; bitpos: [19:18]; default: 0;
-         *  Action on PWMnA/B triggered by event TEB when timer decreasing
-         */
-        uint32_t gen_dteb:2;
-        /** gen_dt0 : R/W; bitpos: [21:20]; default: 0;
-         *  Action on PWMnA/B triggered by event_t0 when timer decreasing
-         */
-        uint32_t gen_dt0:2;
-        /** gen_dt1 : R/W; bitpos: [23:22]; default: 0;
-         *  Action on PWMnA/B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_dt1:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_gen_reg_t;
-
-/** Type of dt_cfg register
- *  dead time type selection and configuration
- */
-typedef union {
-    struct {
-        /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
-         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
-         *  bit3 is set to 1: disable the update
-         */
-        uint32_t db_fed_upmethod:4;
-        /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
-         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
-         *  bit3 is set to 1: disable the update
-         */
-        uint32_t db_red_upmethod:4;
-        /** db_deb_mode : R/W; bitpos: [8]; default: 0;
-         *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
-         *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
-         */
-        uint32_t db_deb_mode:1;
-        /** db_a_outswap : R/W; bitpos: [9]; default: 0;
-         *  S6 in table
-         */
-        uint32_t db_a_outswap:1;
-        /** db_b_outswap : R/W; bitpos: [10]; default: 0;
-         *  S7 in table
-         */
-        uint32_t db_b_outswap:1;
-        /** db_red_insel : R/W; bitpos: [11]; default: 0;
-         *  S4 in table
-         */
-        uint32_t db_red_insel:1;
-        /** db_fed_insel : R/W; bitpos: [12]; default: 0;
-         *  S5 in table
-         */
-        uint32_t db_fed_insel:1;
-        /** db_red_outinvert : R/W; bitpos: [13]; default: 0;
-         *  S2 in table
-         */
-        uint32_t db_red_outinvert:1;
-        /** db_fed_outinvert : R/W; bitpos: [14]; default: 0;
-         *  S3 in table
-         */
-        uint32_t db_fed_outinvert:1;
-        /** db_a_outbypass : R/W; bitpos: [15]; default: 1;
-         *  S1 in table
-         */
-        uint32_t db_a_outbypass:1;
-        /** db_b_outbypass : R/W; bitpos: [16]; default: 1;
-         *  S0 in table
-         */
-        uint32_t db_b_outbypass:1;
-        /** db_clk_sel : R/W; bitpos: [17]; default: 0;
-         *  Dead time generator n clock selection. 0: PWM_clk, 1: PT_clk
-         */
-        uint32_t db_clk_sel:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} mcpwm_dt_cfg_reg_t;
-
-/** Type of dt_fed_cfg register
- *  Shadow register for falling edge delay (FED).
- */
-typedef union {
-    struct {
-        /** db_fed : R/W; bitpos: [15:0]; default: 0;
-         *  Shadow register for FED
-         */
-        uint32_t db_fed:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dt_fed_cfg_reg_t;
-
-/** Type of dt_red_cfg register
- *  Shadow register for rising edge delay (RED).
- */
-typedef union {
-    struct {
-        /** db_red : R/W; bitpos: [15:0]; default: 0;
-         *  Shadow register for RED
-         */
-        uint32_t db_red:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dt_red_cfg_reg_t;
-
-/** Type of carrier_cfg register
- *  Carrier enable and configuratoin
- */
-typedef union {
-    struct {
-        /** chopper_en : R/W; bitpos: [0]; default: 0;
-         *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
-         */
-        uint32_t chopper_en:1;
-        /** chopper_prescale : R/W; bitpos: [4:1]; default: 0;
-         *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
-         *  (PWM_CARRIER0_PRESCALE + 1)
-         */
-        uint32_t chopper_prescale:4;
-        /** chopper_duty : R/W; bitpos: [7:5]; default: 0;
-         *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
-         */
-        uint32_t chopper_duty:3;
-        /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0;
-         *  width of the first pulse in number of periods of the carrier
-         */
-        uint32_t chopper_oshtwth:4;
-        /** chopper_out_invert : R/W; bitpos: [12]; default: 0;
-         *  when set, invert the output of PWM0A and PWM0B for this submodule
-         */
-        uint32_t chopper_out_invert:1;
-        /** chopper_in_invert : R/W; bitpos: [13]; default: 0;
-         *  when set, invert the input of PWM0A and PWM0B for this submodule
-         */
-        uint32_t chopper_in_invert:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} mcpwm_carrier_cfg_reg_t;
-
-/** Type of fh_cfg0 register
- *  Actions on PWM0A and PWM0B trip events
- */
-typedef union {
-    struct {
-        /** tz_sw_cbc : R/W; bitpos: [0]; default: 0;
-         *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_sw_cbc:1;
-        /** tz_f2_cbc : R/W; bitpos: [1]; default: 0;
-         *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f2_cbc:1;
-        /** tz_f1_cbc : R/W; bitpos: [2]; default: 0;
-         *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f1_cbc:1;
-        /** tz_f0_cbc : R/W; bitpos: [3]; default: 0;
-         *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f0_cbc:1;
-        /** tz_sw_ost : R/W; bitpos: [4]; default: 0;
-         *  Enable register for software force one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_sw_ost:1;
-        /** tz_f2_ost : R/W; bitpos: [5]; default: 0;
-         *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f2_ost:1;
-        /** tz_f1_ost : R/W; bitpos: [6]; default: 0;
-         *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f1_ost:1;
-        /** tz_f0_ost : R/W; bitpos: [7]; default: 0;
-         *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t tz_f0_ost:1;
-        /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
-         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_a_cbc_d:2;
-        /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
-         *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_a_cbc_u:2;
-        /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0;
-         *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_a_ost_d:2;
-        /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0;
-         *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_a_ost_u:2;
-        /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
-         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_b_cbc_d:2;
-        /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
-         *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_b_cbc_u:2;
-        /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0;
-         *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_b_ost_d:2;
-        /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0;
-         *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t tz_b_ost_u:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg0_reg_t;
-
-/** Type of fh_cfg1 register
- *  Software triggers for fault handler actions
- */
-typedef union {
-    struct {
-        /** tz_clr_ost : R/W; bitpos: [0]; default: 0;
-         *  a rising edge will clear on going one-shot mode action
-         */
-        uint32_t tz_clr_ost:1;
-        /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0;
-         *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
-         *  when bit1 is set to 1:TEP
-         */
-        uint32_t tz_cbcpulse:2;
-        /** tz_force_cbc : R/W; bitpos: [3]; default: 0;
-         *  a toggle trigger a cycle-by-cycle mode action
-         */
-        uint32_t tz_force_cbc:1;
-        /** tz_force_ost : R/W; bitpos: [4]; default: 0;
-         *  a toggle (software negate its value) triggers a one-shot mode action
-         */
-        uint32_t tz_force_ost:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg1_reg_t;
-
-/** Type of fh_status register
- *  Status of fault events.
- */
-typedef union {
-    struct {
-        /** tz_cbc_on : RO; bitpos: [0]; default: 0;
-         *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
-         */
-        uint32_t tz_cbc_on:1;
-        /** tz_ost_on : RO; bitpos: [1]; default: 0;
-         *  Set and reset by hardware. If set, an one-shot mode action is on going
-         */
-        uint32_t tz_ost_on:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} mcpwm_fh_status_reg_t;
-
-
-/** Group: Fault Detection Configuration and Status */
-/** Type of fault_detect register
- *  Fault detection configuration and status
- */
-typedef union {
-    struct {
-        /** f0_en : R/W; bitpos: [0]; default: 0;
-         *  When set, event_f0 generation is enabled
-         */
-        uint32_t f0_en:1;
-        /** f1_en : R/W; bitpos: [1]; default: 0;
-         *  When set, event_f1 generation is enabled
-         */
-        uint32_t f1_en:1;
-        /** f2_en : R/W; bitpos: [2]; default: 0;
-         *  When set, event_f2 generation is enabled
-         */
-        uint32_t f2_en:1;
-        /** f0_pole : R/W; bitpos: [3]; default: 0;
-         *  Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
-         *  level high
-         */
-        uint32_t f0_pole:1;
-        /** f1_pole : R/W; bitpos: [4]; default: 0;
-         *  Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
-         *  level high
-         */
-        uint32_t f1_pole:1;
-        /** f2_pole : R/W; bitpos: [5]; default: 0;
-         *  Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
-         *  level high
-         */
-        uint32_t f2_pole:1;
-        /** event_f0 : RO; bitpos: [6]; default: 0;
-         *  Set and reset by hardware. If set, event_f0 is on going
-         */
-        uint32_t event_f0:1;
-        /** event_f1 : RO; bitpos: [7]; default: 0;
-         *  Set and reset by hardware. If set, event_f1 is on going
-         */
-        uint32_t event_f1:1;
-        /** event_f2 : RO; bitpos: [8]; default: 0;
-         *  Set and reset by hardware. If set, event_f2 is on going
-         */
-        uint32_t event_f2:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} mcpwm_fault_detect_reg_t;
-
-
-/** Group: Capture Configuration and Status */
-/** Type of cap_timer_cfg register
- *  Configure capture timer
- */
-typedef union {
-    struct {
-        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
-         *  When set, capture timer incrementing under APB_clk is enabled.
-         */
-        uint32_t cap_timer_en:1;
-        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
-         *  When set, capture timer sync is enabled.
-         */
-        uint32_t cap_synci_en:1;
-        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
-         *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
-         *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
-         *  6: SYNC2 from GPIO matrix
-         */
-        uint32_t cap_synci_sel:3;
-        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
-         *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
-         *  timer is loaded with value in phase register.
-         */
-        uint32_t cap_sync_sw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_cfg_reg_t;
-
-/** Type of cap_timer_phase register
- *  Phase for capture timer sync
- */
-typedef union {
-    struct {
-        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
-         *  Phase value for capture timer sync operation.
-         */
-        uint32_t cap_phase:32;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_phase_reg_t;
-
-/** Type of cap_chn_cfg register
- *  Capture channel n configuration and enable
- */
-typedef union {
-    struct {
-        /** capn_en : R/W; bitpos: [0]; default: 0;
-         *  When set, capture on channel 0 is enabled
-         */
-        uint32_t capn_en:1;
-        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
-         *  Edge of capture on channel n after prescaling. When bit0 is set to 1: enable
-         *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
-         *  edge.
-         */
-        uint32_t capn_mode:2;
-        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
-         *  1
-         */
-        uint32_t capn_prescale:8;
-        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
-         *  when set, CAPn form GPIO matrix is inverted before prescale
-         */
-        uint32_t capn_in_invert:1;
-        /** capn_sw : WT; bitpos: [12]; default: 0;
-         *  Write 1 will trigger a software forced capture on channel n
-         */
-        uint32_t capn_sw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_cfg_reg_t;
-
-/** Type of cap_chn register
- *  chn capture value status register
- */
-typedef union {
-    struct {
-        /** capn_value : RO; bitpos: [31:0]; default: 0;
-         *  Value of last capture on channel n
-         */
-        uint32_t capn_value:32;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_reg_t;
-
-/** Type of cap_status register
- *  Edge of last capture trigger
- */
-typedef union {
-    struct {
-        /** cap0_edge : RO; bitpos: [0]; default: 0;
-         *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
-         */
-        uint32_t cap0_edge:1;
-        /** cap1_edge : RO; bitpos: [1]; default: 0;
-         *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
-         */
-        uint32_t cap1_edge:1;
-        /** cap2_edge : RO; bitpos: [2]; default: 0;
-         *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
-         */
-        uint32_t cap2_edge:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} mcpwm_cap_status_reg_t;
-
-
-/** Group: Enable update of active registers */
-/** Type of update_cfg register
- *  Enable update.
- */
-typedef union {
-    struct {
-        /** global_up_en : R/W; bitpos: [0]; default: 1;
-         *  The global enable of update of all active registers in MCPWM module
-         */
-        uint32_t global_up_en:1;
-        /** global_force_up : R/W; bitpos: [1]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of all active
-         *  registers in MCPWM module
-         */
-        uint32_t global_force_up:1;
-        /** op0_up_en : R/W; bitpos: [2]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
-         *  are enabled
-         */
-        uint32_t op0_up_en:1;
-        /** op0_force_up : R/W; bitpos: [3]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 0
-         */
-        uint32_t op0_force_up:1;
-        /** op1_up_en : R/W; bitpos: [4]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
-         *  are enabled
-         */
-        uint32_t op1_up_en:1;
-        /** op1_force_up : R/W; bitpos: [5]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 1
-         */
-        uint32_t op1_force_up:1;
-        /** op2_up_en : R/W; bitpos: [6]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
-         *  are enabled
-         */
-        uint32_t op2_up_en:1;
-        /** op2_force_up : R/W; bitpos: [7]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 2
-         */
-        uint32_t op2_force_up:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_update_cfg_reg_t;
-
-
-/** Group: Manage Interrupts */
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_ena:1;
-        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_ena:1;
-        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_ena:1;
-        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_ena:1;
-        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_ena:1;
-        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_ena:1;
-        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_ena:1;
-        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_ena:1;
-        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_ena:1;
-        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_ena:1;
-        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_ena:1;
-        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_ena:1;
-        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f0 ends.
-         */
-        uint32_t fault0_clr_int_ena:1;
-        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f1 ends.
-         */
-        uint32_t fault1_clr_int_ena:1;
-        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The enable bit for the interrupt triggered when event_f2 ends.
-         */
-        uint32_t fault2_clr_int_ena:1;
-        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_ena:1;
-        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_ena:1;
-        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_ena:1;
-        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_ena:1;
-        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_ena:1;
-        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_ena:1;
-        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t tz0_cbc_int_ena:1;
-        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t tz1_cbc_int_ena:1;
-        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t tz2_cbc_int_ena:1;
-        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_ena:1;
-        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_ena:1;
-        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_ena:1;
-        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_ena:1;
-        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_ena:1;
-        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_ena:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_raw:1;
-        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_raw:1;
-        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_raw:1;
-        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_raw:1;
-        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_raw:1;
-        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_raw:1;
-        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_raw:1;
-        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_raw:1;
-        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_raw:1;
-        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_raw:1;
-        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_raw:1;
-        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_raw:1;
-        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f0 ends.
-         */
-        uint32_t fault0_clr_int_raw:1;
-        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f1 ends.
-         */
-        uint32_t fault1_clr_int_raw:1;
-        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw status bit for the interrupt triggered when event_f2 ends.
-         */
-        uint32_t fault2_clr_int_raw:1;
-        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_raw:1;
-        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_raw:1;
-        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_raw:1;
-        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_raw:1;
-        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_raw:1;
-        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_raw:1;
-        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_cbc_int_raw:1;
-        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_cbc_int_raw:1;
-        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_cbc_int_raw:1;
-        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_raw:1;
-        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_raw:1;
-        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_raw:1;
-        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_raw:1;
-        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_raw:1;
-        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_raw:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_st:1;
-        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_st:1;
-        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_st:1;
-        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_st:1;
-        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_st:1;
-        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_st:1;
-        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_st:1;
-        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_st:1;
-        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_st:1;
-        /** fault0_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_st:1;
-        /** fault1_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_st:1;
-        /** fault2_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_st:1;
-        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f0 ends.
-         */
-        uint32_t fault0_clr_int_st:1;
-        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f1 ends.
-         */
-        uint32_t fault1_clr_int_st:1;
-        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked status bit for the interrupt triggered when event_f2 ends.
-         */
-        uint32_t fault2_clr_int_st:1;
-        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_st:1;
-        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_st:1;
-        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_st:1;
-        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_st:1;
-        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_st:1;
-        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_st:1;
-        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM0.
-         */
-        uint32_t tz0_cbc_int_st:1;
-        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM1.
-         */
-        uint32_t tz1_cbc_int_st:1;
-        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM2.
-         */
-        uint32_t tz2_cbc_int_st:1;
-        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_st:1;
-        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_st:1;
-        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_st:1;
-        /** cap0_int_st : RO; bitpos: [27]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_st:1;
-        /** cap1_int_st : RO; bitpos: [28]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_st:1;
-        /** cap2_int_st : RO; bitpos: [29]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_st:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_st_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_clr:1;
-        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_clr:1;
-        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_clr:1;
-        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_clr:1;
-        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_clr:1;
-        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_clr:1;
-        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_clr:1;
-        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_clr:1;
-        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_clr:1;
-        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_clr:1;
-        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_clr:1;
-        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_clr:1;
-        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f0 ends.
-         */
-        uint32_t fault0_clr_int_clr:1;
-        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f1 ends.
-         */
-        uint32_t fault1_clr_int_clr:1;
-        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the interrupt triggered when event_f2 ends.
-         */
-        uint32_t fault2_clr_int_clr:1;
-        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_clr:1;
-        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_clr:1;
-        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_clr:1;
-        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_clr:1;
-        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_clr:1;
-        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_clr:1;
-        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_cbc_int_clr:1;
-        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_cbc_int_clr:1;
-        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_cbc_int_clr:1;
-        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_clr:1;
-        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_clr:1;
-        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_clr:1;
-        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_clr:1;
-        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_clr:1;
-        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_clr:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_clr_reg_t;
-
-
-/** Group: MCPWM event enable register */
-/** Type of evt_en register
- *  MCPWM event enable register
- */
-typedef union {
-    struct {
-        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
-         *  set this bit high to enable timer0 stop event generate
-         */
-        uint32_t evt_timer0_stop_en:1;
-        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
-         *  set this bit high to enable timer1 stop event generate
-         */
-        uint32_t evt_timer1_stop_en:1;
-        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
-         *  set this bit high to enable timer2 stop event generate
-         */
-        uint32_t evt_timer2_stop_en:1;
-        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
-         *  set this bit high to enable timer0 equal zero event generate
-         */
-        uint32_t evt_timer0_tez_en:1;
-        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
-         *  set this bit high to enable timer1 equal zero event generate
-         */
-        uint32_t evt_timer1_tez_en:1;
-        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
-         *  set this bit high to enable timer2 equal zero event generate
-         */
-        uint32_t evt_timer2_tez_en:1;
-        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
-         *  set this bit high to enable timer0 equal period event generate
-         */
-        uint32_t evt_timer0_tep_en:1;
-        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
-         *  set this bit high to enable timer1 equal period event generate
-         */
-        uint32_t evt_timer1_tep_en:1;
-        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
-         *  set this bit high to enable timer2 equal period event generate
-         */
-        uint32_t evt_timer2_tep_en:1;
-        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
-         *  set this bit high to enable PWM generator0 timer equal a event generate
-         */
-        uint32_t evt_op0_tea_en:1;
-        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
-         *  set this bit high to enable PWM generator1 timer equal a event generate
-         */
-        uint32_t evt_op1_tea_en:1;
-        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
-         *  set this bit high to enable PWM generator2 timer equal a event generate
-         */
-        uint32_t evt_op2_tea_en:1;
-        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
-         *  set this bit high to enable PWM generator0 timer equal b event generate
-         */
-        uint32_t evt_op0_teb_en:1;
-        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
-         *  set this bit high to enable PWM generator1 timer equal b event generate
-         */
-        uint32_t evt_op1_teb_en:1;
-        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
-         *  set this bit high to enable PWM generator2 timer equal b event generate
-         */
-        uint32_t evt_op2_teb_en:1;
-        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
-         *  set this bit high to enable fault0 event generate
-         */
-        uint32_t evt_f0_en:1;
-        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
-         *  set this bit high to enable fault1 event generate
-         */
-        uint32_t evt_f1_en:1;
-        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
-         *  set this bit high to enable fault2 event generate
-         */
-        uint32_t evt_f2_en:1;
-        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
-         *  set this bit high to enable fault0 clear event generate
-         */
-        uint32_t evt_f0_clr_en:1;
-        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
-         *  set this bit high to enable fault1 clear event generate
-         */
-        uint32_t evt_f1_clr_en:1;
-        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
-         *  set this bit high to enable fault2 clear event generate
-         */
-        uint32_t evt_f2_clr_en:1;
-        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
-         *  set this bit high to enable cycle by cycle trip0 event generate
-         */
-        uint32_t evt_tz0_cbc_en:1;
-        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
-         *  set this bit high to enable cycle by cycle trip1 event generate
-         */
-        uint32_t evt_tz1_cbc_en:1;
-        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
-         *  set this bit high to enable cycle by cycle trip2 event generate
-         */
-        uint32_t evt_tz2_cbc_en:1;
-        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
-         *  set this bit high to enable one shot trip0 event generate
-         */
-        uint32_t evt_tz0_ost_en:1;
-        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
-         *  set this bit high to enable one shot trip1 event generate
-         */
-        uint32_t evt_tz1_ost_en:1;
-        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
-         *  set this bit high to enable one shot trip2 event generate
-         */
-        uint32_t evt_tz2_ost_en:1;
-        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
-         *  set this bit high to enable capture0 event generate
-         */
-        uint32_t evt_cap0_en:1;
-        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
-         *  set this bit high to enable capture1 event generate
-         */
-        uint32_t evt_cap1_en:1;
-        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
-         *  set this bit high to enable capture2 event generate
-         */
-        uint32_t evt_cap2_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_evt_en_reg_t;
-
-
-/** Group: MCPWM task enable register */
-/** Type of task_en register
- *  MCPWM task enable register
- */
-typedef union {
-    struct {
-        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
-         *  set this bit high to enable PWM generator0 timer stamp A's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr0_a_up_en:1;
-        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
-         *  set this bit high to enable PWM generator1 timer stamp A's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr1_a_up_en:1;
-        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
-         *  set this bit high to enable PWM generator2 timer stamp A's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr2_a_up_en:1;
-        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
-         *  set this bit high to enable PWM generator0 timer stamp B's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr0_b_up_en:1;
-        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
-         *  set this bit high to enable PWM generator1 timer stamp B's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr1_b_up_en:1;
-        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
-         *  set this bit high to enable PWM generator2 timer stamp B's shadow register update
-         *  task receive
-         */
-        uint32_t task_cmpr2_b_up_en:1;
-        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
-         *  set this bit high to enable all PWM generate stop task receive
-         */
-        uint32_t task_gen_stop_en:1;
-        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
-         *  set this bit high to enable timer0 sync task receive
-         */
-        uint32_t task_timer0_sync_en:1;
-        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
-         *  set this bit high to enable timer1 sync task receive
-         */
-        uint32_t task_timer1_sync_en:1;
-        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
-         *  set this bit high to enable timer2 sync task receive
-         */
-        uint32_t task_timer2_sync_en:1;
-        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
-         *  set this bit high to enable timer0 period update task receive
-         */
-        uint32_t task_timer0_period_up_en:1;
-        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
-         *  set this bit high to enable timer1 period update task receive
-         */
-        uint32_t task_timer1_period_up_en:1;
-        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
-         *  set this bit high to enable timer2 period update task receive
-         */
-        uint32_t task_timer2_period_up_en:1;
-        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
-         *  set this bit high to enable one shot trip0 task receive
-         */
-        uint32_t task_tz0_ost_en:1;
-        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
-         *  set this bit high to enable one shot trip1 task receive
-         */
-        uint32_t task_tz1_ost_en:1;
-        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
-         *  set this bit high to enable one shot trip2 task receive
-         */
-        uint32_t task_tz2_ost_en:1;
-        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
-         *  set this bit high to enable one shot trip0 clear task receive
-         */
-        uint32_t task_clr0_ost_en:1;
-        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
-         *  set this bit high to enable one shot trip1 clear task receive
-         */
-        uint32_t task_clr1_ost_en:1;
-        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
-         *  set this bit high to enable one shot trip2 clear task receive
-         */
-        uint32_t task_clr2_ost_en:1;
-        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
-         *  set this bit high to enable capture0 task receive
-         */
-        uint32_t task_cap0_en:1;
-        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
-         *  set this bit high to enable capture1 task receive
-         */
-        uint32_t task_cap1_en:1;
-        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
-         *  set this bit high to enable capture2 task receive
-         */
-        uint32_t task_cap2_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} mcpwm_task_en_reg_t;
-
-
-/** Group: MCPWM APB configuration register */
-/** Type of clk register
- *  MCPWM APB configuration register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Force clock on for this register file
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mcpwm_clk_reg_t;
-
-
-/** Group: Version Register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35656256;
-         *  Version of this register file
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} mcpwm_version_reg_t;
-
-typedef struct {
-    mcpwm_timer_cfg0_reg_t timer_cfg0;
-    mcpwm_timer_cfg1_reg_t timer_cfg1;
-    mcpwm_timer_sync_reg_t timer_sync;
-    mcpwm_timer_status_reg_t timer_status;
-} mcpwm_timer_regs_t;
-
-typedef struct {
-    mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
-    mcpwm_gen_tstmp_reg_t timestamp[2];
-    mcpwm_gen_cfg0_reg_t gen_cfg0;
-    mcpwm_gen_force_reg_t gen_force;
-    mcpwm_gen_reg_t generator[2];
-    mcpwm_dt_cfg_reg_t dt_cfg;
-    mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
-    mcpwm_dt_red_cfg_reg_t dt_red_cfg;
-    mcpwm_carrier_cfg_reg_t carrier_cfg;
-    mcpwm_fh_cfg0_reg_t fh_cfg0;
-    mcpwm_fh_cfg1_reg_t fh_cfg1;
-    mcpwm_fh_status_reg_t fh_status;
-} mcpwm_operator_reg_t;
-
-typedef struct mcpwm_dev_t {
-    volatile mcpwm_clk_cfg_reg_t clk_cfg;
-    volatile mcpwm_timer_regs_t timer[3];
-    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
-    volatile mcpwm_operator_timersel_reg_t operator_timersel;
-    volatile mcpwm_operator_reg_t operators[3];
-    volatile mcpwm_fault_detect_reg_t fault_detect;
-    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
-    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
-    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
-    volatile mcpwm_cap_chn_reg_t cap_chn[3];
-    volatile mcpwm_cap_status_reg_t cap_status;
-    volatile mcpwm_update_cfg_reg_t update_cfg;
-    volatile mcpwm_int_ena_reg_t int_ena;
-    volatile mcpwm_int_raw_reg_t int_raw;
-    volatile mcpwm_int_st_reg_t int_st;
-    volatile mcpwm_int_clr_reg_t int_clr;
-    volatile mcpwm_evt_en_reg_t evt_en;
-    volatile mcpwm_task_en_reg_t task_en;
-    volatile mcpwm_clk_reg_t clk;
-    volatile mcpwm_version_reg_t version;
-} mcpwm_dev_t;
-
-extern mcpwm_dev_t MCPWM0;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mcpwm_dev_t) == 0x130, "Invalid size of mcpwm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/mem_monitor_reg.h b/components/soc/esp32h2/include/soc/mem_monitor_reg.h
deleted file mode 100644
index bbddf93b89a..00000000000
--- a/components/soc/esp32h2/include/soc/mem_monitor_reg.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MEM_MONITOR_LOG_SETTING_REG register
- *  log config regsiter
- */
-#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
-/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
- *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu
- */
-#define MEM_MONITOR_LOG_ENA    0x00000007U
-#define MEM_MONITOR_LOG_ENA_M  (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
-#define MEM_MONITOR_LOG_ENA_V  0x00000007U
-#define MEM_MONITOR_LOG_ENA_S  0
-/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
- *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
- *  HALFWORD monitor, 4'b1000: BYTE monitor.
- */
-#define MEM_MONITOR_LOG_MODE    0x0000000FU
-#define MEM_MONITOR_LOG_MODE_M  (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
-#define MEM_MONITOR_LOG_MODE_V  0x0000000FU
-#define MEM_MONITOR_LOG_MODE_S  3
-/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
- *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
- */
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(7))
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
-
-/** MEM_MONITOR_LOG_CHECK_DATA_REG register
- *  check data regsiter
- */
-#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
-/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
- *  The special check data, when write this special data, it will trigger logging.
- */
-#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_CHECK_DATA_M  (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
-#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_CHECK_DATA_S  0
-
-/** MEM_MONITOR_LOG_DATA_MASK_REG register
- *  check data mask register
- */
-#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
-/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
- *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
- *  mask second byte, and so on.
- */
-#define MEM_MONITOR_LOG_DATA_MASK    0x0000000FU
-#define MEM_MONITOR_LOG_DATA_MASK_M  (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
-#define MEM_MONITOR_LOG_DATA_MASK_V  0x0000000FU
-#define MEM_MONITOR_LOG_DATA_MASK_S  0
-
-/** MEM_MONITOR_LOG_MIN_REG register
- *  log boundary regsiter
- */
-#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
-/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
- *  the min address of log range
- */
-#define MEM_MONITOR_LOG_MIN    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MIN_M  (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
-#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MIN_S  0
-
-/** MEM_MONITOR_LOG_MAX_REG register
- *  log boundary regsiter
- */
-#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
-/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
- *  the max address of log range
- */
-#define MEM_MONITOR_LOG_MAX    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MAX_M  (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
-#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MAX_S  0
-
-/** MEM_MONITOR_LOG_MEM_START_REG register
- *  log message store range register
- */
-#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
-/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
- *  the start address of writing logging message
- */
-#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_START_M  (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
-#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_START_S  0
-
-/** MEM_MONITOR_LOG_MEM_END_REG register
- *  log message store range register
- */
-#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
-/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
- *  the end address of writing logging message
- */
-#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_END_M  (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
-#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_END_S  0
-
-/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
- *  current writing address.
- */
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
-/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  means next writing address
- */
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
-#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
-
-/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
- *  writing address update
- */
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
-/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
- *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
- *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
- */
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
-
-/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
- *  full flag status register
- */
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
-/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
- *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
- */
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x00000001U
-#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
-/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
- *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
- */
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
-#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
-
-/** MEM_MONITOR_CLOCK_GATE_REG register
- *  clock gate force on register
- */
-#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
-/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to force on the clk of mem_monitor register
- */
-#define MEM_MONITOR_CLK_EN    (BIT(0))
-#define MEM_MONITOR_CLK_EN_M  (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
-#define MEM_MONITOR_CLK_EN_V  0x00000001U
-#define MEM_MONITOR_CLK_EN_S  0
-
-/** MEM_MONITOR_DATE_REG register
- *  version register
- */
-#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
-/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096;
- *  version register
- */
-#define MEM_MONITOR_DATE    0x0FFFFFFFU
-#define MEM_MONITOR_DATE_M  (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
-#define MEM_MONITOR_DATE_V  0x0FFFFFFFU
-#define MEM_MONITOR_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/mem_monitor_struct.h b/components/soc/esp32h2/include/soc/mem_monitor_struct.h
deleted file mode 100644
index 8d4628467f7..00000000000
--- a/components/soc/esp32h2/include/soc/mem_monitor_struct.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configuration registers */
-/** Type of log_setting register
- *  log config regsiter
- */
-typedef union {
-    struct {
-        /** log_ena : R/W; bitpos: [2:0]; default: 0;
-         *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu
-         */
-        uint32_t log_ena:3;
-        /** log_mode : R/W; bitpos: [6:3]; default: 0;
-         *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
-         *  HALFWORD monitor, 4'b1000: BYTE monitor.
-         */
-        uint32_t log_mode:4;
-        /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
-         *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
-         */
-        uint32_t log_mem_loop_enable:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mem_monitor_log_setting_reg_t;
-
-/** Type of log_check_data register
- *  check data regsiter
- */
-typedef union {
-    struct {
-        /** log_check_data : R/W; bitpos: [31:0]; default: 0;
-         *  The special check data, when write this special data, it will trigger logging.
-         */
-        uint32_t log_check_data:32;
-    };
-    uint32_t val;
-} mem_monitor_log_check_data_reg_t;
-
-/** Type of log_data_mask register
- *  check data mask register
- */
-typedef union {
-    struct {
-        /** log_data_mask : R/W; bitpos: [3:0]; default: 0;
-         *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
-         *  mask second byte, and so on.
-         */
-        uint32_t log_data_mask:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} mem_monitor_log_data_mask_reg_t;
-
-/** Type of log_min register
- *  log boundary regsiter
- */
-typedef union {
-    struct {
-        /** log_min : R/W; bitpos: [31:0]; default: 0;
-         *  the min address of log range
-         */
-        uint32_t log_min:32;
-    };
-    uint32_t val;
-} mem_monitor_log_min_reg_t;
-
-/** Type of log_max register
- *  log boundary regsiter
- */
-typedef union {
-    struct {
-        /** log_max : R/W; bitpos: [31:0]; default: 0;
-         *  the max address of log range
-         */
-        uint32_t log_max:32;
-    };
-    uint32_t val;
-} mem_monitor_log_max_reg_t;
-
-/** Type of log_mem_start register
- *  log message store range register
- */
-typedef union {
-    struct {
-        /** log_mem_start : R/W; bitpos: [31:0]; default: 0;
-         *  the start address of writing logging message
-         */
-        uint32_t log_mem_start:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_start_reg_t;
-
-/** Type of log_mem_end register
- *  log message store range register
- */
-typedef union {
-    struct {
-        /** log_mem_end : R/W; bitpos: [31:0]; default: 0;
-         *  the end address of writing logging message
-         */
-        uint32_t log_mem_end:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_end_reg_t;
-
-/** Type of log_mem_current_addr register
- *  current writing address.
- */
-typedef union {
-    struct {
-        /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
-         *  means next writing address
-         */
-        uint32_t log_mem_current_addr:32;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_current_addr_reg_t;
-
-/** Type of log_mem_addr_update register
- *  writing address update
- */
-typedef union {
-    struct {
-        /** log_mem_addr_update : WT; bitpos: [0]; default: 0;
-         *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
-         *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
-         */
-        uint32_t log_mem_addr_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_addr_update_reg_t;
-
-/** Type of log_mem_full_flag register
- *  full flag status register
- */
-typedef union {
-    struct {
-        /** log_mem_full_flag : RO; bitpos: [0]; default: 0;
-         *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
-         */
-        uint32_t log_mem_full_flag:1;
-        /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
-         *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
-         */
-        uint32_t clr_log_mem_full_flag:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} mem_monitor_log_mem_full_flag_reg_t;
-
-
-/** Group: clk register */
-/** Type of clock_gate register
- *  clock gate force on register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to force on the clk of mem_monitor register
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mem_monitor_clock_gate_reg_t;
-
-
-/** Group: version register */
-/** Type of date register
- *  version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35660096;
-         *  version register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} mem_monitor_date_reg_t;
-
-
-typedef struct {
-    volatile mem_monitor_log_setting_reg_t log_setting;
-    volatile mem_monitor_log_check_data_reg_t log_check_data;
-    volatile mem_monitor_log_data_mask_reg_t log_data_mask;
-    volatile mem_monitor_log_min_reg_t log_min;
-    volatile mem_monitor_log_max_reg_t log_max;
-    volatile mem_monitor_log_mem_start_reg_t log_mem_start;
-    volatile mem_monitor_log_mem_end_reg_t log_mem_end;
-    volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
-    volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
-    volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
-    volatile mem_monitor_clock_gate_reg_t clock_gate;
-    uint32_t reserved_02c[244];
-    volatile mem_monitor_date_reg_t date;
-} mem_monitor_dev_t;
-
-extern mem_monitor_dev_t MEM_MONITOR;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/parl_io_reg.h b/components/soc/esp32h2/include/soc/parl_io_reg.h
deleted file mode 100644
index 810530ded7b..00000000000
--- a/components/soc/esp32h2/include/soc/parl_io_reg.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PARL_IO_RX_MODE_CFG_REG register
- *  Parallel RX Sampling mode configuration register.
- */
-#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
-/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
- *  Configures rx external enable signal selection from IO PAD.
- */
-#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
-#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
-#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
-#define PARL_IO_RX_EXT_EN_SEL_S  21
-/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
- *  Set this bit to enable data sampling by software.
- */
-#define PARL_IO_RX_SW_EN    (BIT(25))
-#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
-#define PARL_IO_RX_SW_EN_V  0x00000001U
-#define PARL_IO_RX_SW_EN_S  25
-/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
- *  Set this bit to invert the external enable signal.
- */
-#define PARL_IO_RX_EXT_EN_INV    (BIT(26))
-#define PARL_IO_RX_EXT_EN_INV_M  (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
-#define PARL_IO_RX_EXT_EN_INV_V  0x00000001U
-#define PARL_IO_RX_EXT_EN_INV_S  26
-/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
- *  Configures the rxd pulse sampling submode.
- *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
- *  included)
- *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
- *  excluded)
- *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
- *  included)
- *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
- *  excluded)
- *  4'd4: positive pulse start(data bit included) && length end
- *  4'd5: positive pulse start(data bit excluded) && length end
- */
-#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x00000007U
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x00000007U
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  27
-/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
- *  Configures the rxd sampling mode.
- *  2'b00: external level enable mode
- *  2'b01: external pulse enable mode
- *  2'b10: internal software enable mode
- */
-#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
-#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
-#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
-#define PARL_IO_RX_SMP_MODE_SEL_S  30
-
-/** PARL_IO_RX_DATA_CFG_REG register
- *  Parallel RX data configuration register.
- */
-#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
-/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
- *  Configures expected byte number of received data.
- */
-#define PARL_IO_RX_BITLEN    0x0007FFFFU
-#define PARL_IO_RX_BITLEN_M  (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
-#define PARL_IO_RX_BITLEN_V  0x0007FFFFU
-#define PARL_IO_RX_BITLEN_S  9
-/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
- *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
- */
-#define PARL_IO_RX_DATA_ORDER_INV    (BIT(28))
-#define PARL_IO_RX_DATA_ORDER_INV_M  (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
-#define PARL_IO_RX_DATA_ORDER_INV_V  0x00000001U
-#define PARL_IO_RX_DATA_ORDER_INV_S  28
-/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
- *  Configures the rxd bus width.
- *  3'd0: bus width is 1.
- *  3'd1: bus width is 2.
- *  3'd2: bus width is 4.
- *  3'd3: bus width is 8.
- */
-#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
-#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
-#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
-#define PARL_IO_RX_BUS_WID_SEL_S  29
-
-/** PARL_IO_RX_GENRL_CFG_REG register
- *  Parallel RX general configuration register.
- */
-#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
-/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable the clock gating of output rx clock.
- */
-#define PARL_IO_RX_GATING_EN    (BIT(12))
-#define PARL_IO_RX_GATING_EN_M  (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
-#define PARL_IO_RX_GATING_EN_V  0x00000001U
-#define PARL_IO_RX_GATING_EN_S  12
-/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
- *  Configures threshold of timeout counter.
- */
-#define PARL_IO_RX_TIMEOUT_THRES    0x0000FFFFU
-#define PARL_IO_RX_TIMEOUT_THRES_M  (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
-#define PARL_IO_RX_TIMEOUT_THRES_V  0x0000FFFFU
-#define PARL_IO_RX_TIMEOUT_THRES_S  13
-/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
- *  Set this bit to enable timeout function to generate error eof.
- */
-#define PARL_IO_RX_TIMEOUT_EN    (BIT(29))
-#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
-#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
-#define PARL_IO_RX_TIMEOUT_EN_S  29
-/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
- *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data byte
- *  length. 1'b1: eof generated by external enable signal.
- */
-#define PARL_IO_RX_EOF_GEN_SEL    (BIT(30))
-#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
-#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
-#define PARL_IO_RX_EOF_GEN_SEL_S  30
-
-/** PARL_IO_RX_START_CFG_REG register
- *  Parallel RX Start configuration register.
- */
-#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
-/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
- *  Set this bit to start rx data sampling.
- */
-#define PARL_IO_RX_START    (BIT(31))
-#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
-#define PARL_IO_RX_START_V  0x00000001U
-#define PARL_IO_RX_START_S  31
-
-/** PARL_IO_TX_DATA_CFG_REG register
- *  Parallel TX data configuration register.
- */
-#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
-/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
- *  Configures expected byte number of sent data.
- */
-#define PARL_IO_TX_BITLEN    0x0007FFFFU
-#define PARL_IO_TX_BITLEN_M  (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
-#define PARL_IO_TX_BITLEN_V  0x0007FFFFU
-#define PARL_IO_TX_BITLEN_S  9
-/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
- *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
- */
-#define PARL_IO_TX_DATA_ORDER_INV    (BIT(28))
-#define PARL_IO_TX_DATA_ORDER_INV_M  (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
-#define PARL_IO_TX_DATA_ORDER_INV_V  0x00000001U
-#define PARL_IO_TX_DATA_ORDER_INV_S  28
-/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
- *  Configures the txd bus width.
- *  3'd0: bus width is 1.
- *  3'd1: bus width is 2.
- *  3'd2: bus width is 4.
- *  3'd3: bus width is 8.
- */
-#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
-#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
-#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
-#define PARL_IO_TX_BUS_WID_SEL_S  29
-
-/** PARL_IO_TX_START_CFG_REG register
- *  Parallel TX Start configuration register.
- */
-#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
-/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
- *  Set this bit to start tx data transmit.
- */
-#define PARL_IO_TX_START    (BIT(31))
-#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
-#define PARL_IO_TX_START_V  0x00000001U
-#define PARL_IO_TX_START_S  31
-
-/** PARL_IO_TX_GENRL_CFG_REG register
- *  Parallel TX general configuration register.
- */
-#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
-/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
- *  Configures bus value of transmitter in IDLE state.
- */
-#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
-#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
-#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
-#define PARL_IO_TX_IDLE_VALUE_S  14
-/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
- *  Set this bit to enable the clock gating of output tx clock.
- */
-#define PARL_IO_TX_GATING_EN    (BIT(30))
-#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
-#define PARL_IO_TX_GATING_EN_V  0x00000001U
-#define PARL_IO_TX_GATING_EN_S  30
-/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
- *  Set this bit to enable the output of tx data valid signal.
- */
-#define PARL_IO_TX_VALID_OUTPUT_EN    (BIT(31))
-#define PARL_IO_TX_VALID_OUTPUT_EN_M  (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
-#define PARL_IO_TX_VALID_OUTPUT_EN_V  0x00000001U
-#define PARL_IO_TX_VALID_OUTPUT_EN_S  31
-
-/** PARL_IO_FIFO_CFG_REG register
- *  Parallel IO FIFO configuration register.
- */
-#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
-/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
- *  Set this bit to reset async fifo in tx module.
- */
-#define PARL_IO_TX_FIFO_SRST    (BIT(30))
-#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
-#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
-#define PARL_IO_TX_FIFO_SRST_S  30
-/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
- *  Set this bit to reset async fifo in rx module.
- */
-#define PARL_IO_RX_FIFO_SRST    (BIT(31))
-#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
-#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
-#define PARL_IO_RX_FIFO_SRST_S  31
-
-/** PARL_IO_REG_UPDATE_REG register
- *  Parallel IO FIFO configuration register.
- */
-#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
-/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
- *  Set this bit to update rx register configuration.
- */
-#define PARL_IO_RX_REG_UPDATE    (BIT(31))
-#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
-#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
-#define PARL_IO_RX_REG_UPDATE_S  31
-
-/** PARL_IO_ST_REG register
- *  Parallel IO module status register0.
- */
-#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
-/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
- *  Represents the status that tx is ready to transmit.
- */
-#define PARL_IO_TX_READY    (BIT(31))
-#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
-#define PARL_IO_TX_READY_V  0x00000001U
-#define PARL_IO_TX_READY_S  31
-
-/** PARL_IO_INT_ENA_REG register
- *  Parallel IO interrupt enable singal configuration register.
- */
-#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
-/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M  (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S  1
-/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
-#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
-#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_ENA_S  2
-
-/** PARL_IO_INT_RAW_REG register
- *  Parallel IO interrupt raw singal status register.
- */
-#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
-/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status of TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status of RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M  (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S  1
-/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status of TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
-#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
-#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_RAW_S  2
-
-/** PARL_IO_INT_ST_REG register
- *  Parallel IO interrupt singal status register.
- */
-#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
-/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status of TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status of RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_ST    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_M  (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_S  1
-/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status of TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
-#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
-#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_ST_S  2
-
-/** PARL_IO_INT_CLR_REG register
- *  Parallel IO interrupt  clear singal configuration register.
- */
-#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
-/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M  (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S  1
-/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
-#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
-#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_CLR_S  2
-
-/** PARL_IO_RX_ST0_REG register
- *  Parallel IO RX status register0
- */
-#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
-/** PARL_IO_RX_CNT : RO; bitpos: [12:9]; default: 0;
- *  Indicates the cycle number of reading Rx FIFO.
- */
-#define PARL_IO_RX_CNT    0x0000000FU
-#define PARL_IO_RX_CNT_M  (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
-#define PARL_IO_RX_CNT_V  0x0000000FU
-#define PARL_IO_RX_CNT_S  9
-/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current written bit number into Rx FIFO.
- */
-#define PARL_IO_RX_FIFO_WR_BIT_CNT    0x0007FFFFU
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_M  (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_S  13
-
-/** PARL_IO_RX_ST1_REG register
- *  Parallel IO RX status register1
- */
-#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
-/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current read bit number from Rx FIFO.
- */
-#define PARL_IO_RX_FIFO_RD_BIT_CNT    0x0007FFFFU
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_M  (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_S  13
-
-/** PARL_IO_TX_ST0_REG register
- *  Parallel IO TX status register0
- */
-#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
-/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
- *  Indicates the cycle number of reading Tx FIFO.
- */
-#define PARL_IO_TX_CNT    0x0000007FU
-#define PARL_IO_TX_CNT_M  (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
-#define PARL_IO_TX_CNT_V  0x0000007FU
-#define PARL_IO_TX_CNT_S  6
-/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current read bit number from Tx FIFO.
- */
-#define PARL_IO_TX_FIFO_RD_BIT_CNT    0x0007FFFFU
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_M  (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_S  13
-
-/** PARL_IO_RX_CLK_CFG_REG register
- *  Parallel IO RX clk configuration register
- */
-#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
-/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
- *  Set this bit to invert the input Rx core clock.
- */
-#define PARL_IO_RX_CLK_I_INV    (BIT(30))
-#define PARL_IO_RX_CLK_I_INV_M  (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
-#define PARL_IO_RX_CLK_I_INV_V  0x00000001U
-#define PARL_IO_RX_CLK_I_INV_S  30
-/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
- *  Set this bit to invert the output Rx core clock.
- */
-#define PARL_IO_RX_CLK_O_INV    (BIT(31))
-#define PARL_IO_RX_CLK_O_INV_M  (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
-#define PARL_IO_RX_CLK_O_INV_V  0x00000001U
-#define PARL_IO_RX_CLK_O_INV_S  31
-
-/** PARL_IO_TX_CLK_CFG_REG register
- *  Parallel IO TX clk configuration register
- */
-#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
-/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
- *  Set this bit to invert the input Tx core clock.
- */
-#define PARL_IO_TX_CLK_I_INV    (BIT(30))
-#define PARL_IO_TX_CLK_I_INV_M  (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
-#define PARL_IO_TX_CLK_I_INV_V  0x00000001U
-#define PARL_IO_TX_CLK_I_INV_S  30
-/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
- *  Set this bit to invert the output Tx core clock.
- */
-#define PARL_IO_TX_CLK_O_INV    (BIT(31))
-#define PARL_IO_TX_CLK_O_INV_M  (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
-#define PARL_IO_TX_CLK_O_INV_V  0x00000001U
-#define PARL_IO_TX_CLK_O_INV_S  31
-
-/** PARL_IO_CLK_REG register
- *  Parallel IO clk configuration register
- */
-#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
-/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Force clock on for this register file
- */
-#define PARL_IO_CLK_EN    (BIT(31))
-#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
-#define PARL_IO_CLK_EN_V  0x00000001U
-#define PARL_IO_CLK_EN_S  31
-
-/** PARL_IO_VERSION_REG register
- *  Version register.
- */
-#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
-/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35684928;
- *  Version of this register file
- */
-#define PARL_IO_DATE    0x0FFFFFFFU
-#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
-#define PARL_IO_DATE_V  0x0FFFFFFFU
-#define PARL_IO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/parl_io_struct.h b/components/soc/esp32h2/include/soc/parl_io_struct.h
deleted file mode 100644
index 97dc285531d..00000000000
--- a/components/soc/esp32h2/include/soc/parl_io_struct.h
+++ /dev/null
@@ -1,504 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PARL_IO RX  Mode Configuration */
-/** Type of rx_mode_cfg register
- *  Parallel RX Sampling mode configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
-         *  Configures rx external enable signal selection from IO PAD.
-         */
-        uint32_t rx_ext_en_sel:4;
-        /** rx_sw_en : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to enable data sampling by software.
-         */
-        uint32_t rx_sw_en:1;
-        /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to invert the external enable signal.
-         */
-        uint32_t rx_ext_en_inv:1;
-        /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
-         *  Configures the rxd pulse sampling submode.
-         *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
-         *  included)
-         *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
-         *  excluded)
-         *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
-         *  included)
-         *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
-         *  excluded)
-         *  4'd4: positive pulse start(data bit included) && length end
-         *  4'd5: positive pulse start(data bit excluded) && length end
-         */
-        uint32_t rx_pulse_submode_sel:3;
-        /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
-         *  Configures the rxd sampling mode.
-         *  2'b00: external level enable mode
-         *  2'b01: external pulse enable mode
-         *  2'b10: internal software enable mode
-         */
-        uint32_t rx_smp_mode_sel:2;
-    };
-    uint32_t val;
-} parl_io_rx_mode_cfg_reg_t;
-
-
-/** Group: PARL_IO RX Data Configuration */
-/** Type of rx_data_cfg register
- *  Parallel RX data configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
-         *  Configures expected byte number of received data.
-         */
-        uint32_t rx_bitlen:19;
-        /** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
-         */
-        uint32_t rx_data_order_inv:1;
-        /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
-         *  Configures the rxd bus width.
-         *  3'd0: bus width is 1.
-         *  3'd1: bus width is 2.
-         *  3'd2: bus width is 4.
-         *  3'd3: bus width is 8.
-         */
-        uint32_t rx_bus_wid_sel:3;
-    };
-    uint32_t val;
-} parl_io_rx_data_cfg_reg_t;
-
-
-/** Group: PARL_IO RX General Configuration */
-/** Type of rx_genrl_cfg register
- *  Parallel RX general configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** rx_gating_en : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable the clock gating of output rx clock.
-         */
-        uint32_t rx_gating_en:1;
-        /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
-         *  Configures threshold of timeout counter.
-         */
-        uint32_t rx_timeout_thres:16;
-        /** rx_timeout_en : R/W; bitpos: [29]; default: 1;
-         *  Set this bit to enable timeout function to generate error eof.
-         */
-        uint32_t rx_timeout_en:1;
-        /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
-         *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data byte
-         *  length. 1'b1: eof generated by external enable signal.
-         */
-        uint32_t rx_eof_gen_sel:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} parl_io_rx_genrl_cfg_reg_t;
-
-
-/** Group: PARL_IO RX Start Configuration */
-/** Type of rx_start_cfg register
- *  Parallel RX Start configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** rx_start : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to start rx data sampling.
-         */
-        uint32_t rx_start:1;
-    };
-    uint32_t val;
-} parl_io_rx_start_cfg_reg_t;
-
-
-/** Group: PARL_IO TX Data Configuration */
-/** Type of tx_data_cfg register
- *  Parallel TX data configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
-         *  Configures expected byte number of sent data.
-         */
-        uint32_t tx_bitlen:19;
-        /** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
-         */
-        uint32_t tx_data_order_inv:1;
-        /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
-         *  Configures the txd bus width.
-         *  3'd0: bus width is 1.
-         *  3'd1: bus width is 2.
-         *  3'd2: bus width is 4.
-         *  3'd3: bus width is 8.
-         */
-        uint32_t tx_bus_wid_sel:3;
-    };
-    uint32_t val;
-} parl_io_tx_data_cfg_reg_t;
-
-
-/** Group: PARL_IO TX Start Configuration */
-/** Type of tx_start_cfg register
- *  Parallel TX Start configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_start : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to start tx data transmit.
-         */
-        uint32_t tx_start:1;
-    };
-    uint32_t val;
-} parl_io_tx_start_cfg_reg_t;
-
-
-/** Group: PARL_IO TX General Configuration */
-/** Type of tx_genrl_cfg register
- *  Parallel TX general configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:14;
-        /** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
-         *  Configures bus value of transmitter in IDLE state.
-         */
-        uint32_t tx_idle_value:16;
-        /** tx_gating_en : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to enable the clock gating of output tx clock.
-         */
-        uint32_t tx_gating_en:1;
-        /** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to enable the output of tx data valid signal.
-         */
-        uint32_t tx_valid_output_en:1;
-    };
-    uint32_t val;
-} parl_io_tx_genrl_cfg_reg_t;
-
-
-/** Group: PARL_IO FIFO Configuration */
-/** Type of fifo_cfg register
- *  Parallel IO FIFO configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to reset async fifo in tx module.
-         */
-        uint32_t tx_fifo_srst:1;
-        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to reset async fifo in rx module.
-         */
-        uint32_t rx_fifo_srst:1;
-    };
-    uint32_t val;
-} parl_io_fifo_cfg_reg_t;
-
-
-/** Group: PARL_IO Register Update Configuration */
-/** Type of reg_update register
- *  Parallel IO FIFO configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** rx_reg_update : WT; bitpos: [31]; default: 0;
-         *  Set this bit to update rx register configuration.
-         */
-        uint32_t rx_reg_update:1;
-    };
-    uint32_t val;
-} parl_io_reg_update_reg_t;
-
-
-/** Group: PARL_IO Status */
-/** Type of st register
- *  Parallel IO module status register0.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_ready : RO; bitpos: [31]; default: 0;
-         *  Represents the status that tx is ready to transmit.
-         */
-        uint32_t tx_ready:1;
-    };
-    uint32_t val;
-} parl_io_st_reg_t;
-
-
-/** Group: PARL_IO Interrupt Configuration and Status */
-/** Type of int_ena register
- *  Parallel IO interrupt enable singal configuration register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_ena:1;
-        /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_ena:1;
-        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to enable TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Parallel IO interrupt raw singal status register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status of TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_raw:1;
-        /** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status of RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_raw:1;
-        /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status of TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_raw_reg_t;
-
-/** Type of int_st register
- *  Parallel IO interrupt singal status register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status of TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_st:1;
-        /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status of RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_st:1;
-        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status of TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_st_reg_t;
-
-/** Type of int_clr register
- *  Parallel IO interrupt  clear singal configuration register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_clr:1;
-        /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_clr:1;
-        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_clr_reg_t;
-
-
-/** Group: PARL_IO Rx Status0 */
-/** Type of rx_st0 register
- *  Parallel IO RX status register0
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** rx_cnt : RO; bitpos: [12:9]; default: 0;
-         *  Indicates the cycle number of reading Rx FIFO.
-         */
-        uint32_t rx_cnt:4;
-        /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current written bit number into Rx FIFO.
-         */
-        uint32_t rx_fifo_wr_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_rx_st0_reg_t;
-
-
-/** Group: PARL_IO Rx Status1 */
-/** Type of rx_st1 register
- *  Parallel IO RX status register1
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:13;
-        /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current read bit number from Rx FIFO.
-         */
-        uint32_t rx_fifo_rd_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_rx_st1_reg_t;
-
-
-/** Group: PARL_IO Tx Status0 */
-/** Type of tx_st0 register
- *  Parallel IO TX status register0
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:6;
-        /** tx_cnt : RO; bitpos: [12:6]; default: 0;
-         *  Indicates the cycle number of reading Tx FIFO.
-         */
-        uint32_t tx_cnt:7;
-        /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current read bit number from Tx FIFO.
-         */
-        uint32_t tx_fifo_rd_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_tx_st0_reg_t;
-
-
-/** Group: PARL_IO Rx Clock Configuration */
-/** Type of rx_clk_cfg register
- *  Parallel IO RX clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to invert the input Rx core clock.
-         */
-        uint32_t rx_clk_i_inv:1;
-        /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to invert the output Rx core clock.
-         */
-        uint32_t rx_clk_o_inv:1;
-    };
-    uint32_t val;
-} parl_io_rx_clk_cfg_reg_t;
-
-
-/** Group: PARL_IO Tx Clock Configuration */
-/** Type of tx_clk_cfg register
- *  Parallel IO TX clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to invert the input Tx core clock.
-         */
-        uint32_t tx_clk_i_inv:1;
-        /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to invert the output Tx core clock.
-         */
-        uint32_t tx_clk_o_inv:1;
-    };
-    uint32_t val;
-} parl_io_tx_clk_cfg_reg_t;
-
-
-/** Group: PARL_IO Clock Configuration */
-/** Type of clk register
- *  Parallel IO clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Force clock on for this register file
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} parl_io_clk_reg_t;
-
-
-/** Group: PARL_IO Version Register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35684928;
-         *  Version of this register file
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} parl_io_version_reg_t;
-
-
-typedef struct parl_io_dev_t {
-    volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
-    volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
-    volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
-    volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
-    volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
-    volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
-    volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
-    volatile parl_io_fifo_cfg_reg_t fifo_cfg;
-    volatile parl_io_reg_update_reg_t reg_update;
-    volatile parl_io_st_reg_t st;
-    volatile parl_io_int_ena_reg_t int_ena;
-    volatile parl_io_int_raw_reg_t int_raw;
-    volatile parl_io_int_st_reg_t int_st;
-    volatile parl_io_int_clr_reg_t int_clr;
-    volatile parl_io_rx_st0_reg_t rx_st0;
-    volatile parl_io_rx_st1_reg_t rx_st1;
-    volatile parl_io_tx_st0_reg_t tx_st0;
-    volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
-    volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
-    uint32_t reserved_04c[53];
-    volatile parl_io_clk_reg_t clk;
-    uint32_t reserved_124[182];
-    volatile parl_io_version_reg_t version;
-} parl_io_dev_t;
-
-extern parl_io_dev_t PARL_IO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/pcr_reg.h b/components/soc/esp32h2/include/soc/pcr_reg.h
deleted file mode 100644
index f44d7a31ea5..00000000000
--- a/components/soc/esp32h2/include/soc/pcr_reg.h
+++ /dev/null
@@ -1,2347 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PCR_UART0_CONF_REG register
- *  UART0 configuration register
- */
-#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)
-/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uart0 apb clock
- */
-#define PCR_UART0_CLK_EN    (BIT(0))
-#define PCR_UART0_CLK_EN_M  (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S)
-#define PCR_UART0_CLK_EN_V  0x00000001U
-#define PCR_UART0_CLK_EN_S  0
-/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uart0 module
- */
-#define PCR_UART0_RST_EN    (BIT(1))
-#define PCR_UART0_RST_EN_M  (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
-#define PCR_UART0_RST_EN_V  0x00000001U
-#define PCR_UART0_RST_EN_S  1
-/** PCR_UART0_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset uart0 module
- */
-#define PCR_UART0_READY    (BIT(2))
-#define PCR_UART0_READY_M  (PCR_UART0_READY_V << PCR_UART0_READY_S)
-#define PCR_UART0_READY_V  0x00000001U
-#define PCR_UART0_READY_S  2
-
-/** PCR_UART0_SCLK_CONF_REG register
- *  UART0_SCLK configuration register
- */
-#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)
-/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_A    0x0000003FU
-#define PCR_UART0_SCLK_DIV_A_M  (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S)
-#define PCR_UART0_SCLK_DIV_A_V  0x0000003FU
-#define PCR_UART0_SCLK_DIV_A_S  0
-/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_B    0x0000003FU
-#define PCR_UART0_SCLK_DIV_B_M  (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S)
-#define PCR_UART0_SCLK_DIV_B_V  0x0000003FU
-#define PCR_UART0_SCLK_DIV_B_S  6
-/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the uart0 function clock.
- */
-#define PCR_UART0_SCLK_DIV_NUM    0x000000FFU
-#define PCR_UART0_SCLK_DIV_NUM_M  (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S)
-#define PCR_UART0_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_UART0_SCLK_DIV_NUM_S  12
-/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_UART0_SCLK_SEL    0x00000003U
-#define PCR_UART0_SCLK_SEL_M  (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
-#define PCR_UART0_SCLK_SEL_V  0x00000003U
-#define PCR_UART0_SCLK_SEL_S  20
-/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable uart0 function clock
- */
-#define PCR_UART0_SCLK_EN    (BIT(22))
-#define PCR_UART0_SCLK_EN_M  (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S)
-#define PCR_UART0_SCLK_EN_V  0x00000001U
-#define PCR_UART0_SCLK_EN_S  22
-
-/** PCR_UART0_PD_CTRL_REG register
- *  UART0 power control register
- */
-#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)
-/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power down UART0 memory.
- */
-#define PCR_UART0_MEM_FORCE_PU    (BIT(1))
-#define PCR_UART0_MEM_FORCE_PU_M  (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S)
-#define PCR_UART0_MEM_FORCE_PU_V  0x00000001U
-#define PCR_UART0_MEM_FORCE_PU_S  1
-/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power up UART0 memory.
- */
-#define PCR_UART0_MEM_FORCE_PD    (BIT(2))
-#define PCR_UART0_MEM_FORCE_PD_M  (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S)
-#define PCR_UART0_MEM_FORCE_PD_V  0x00000001U
-#define PCR_UART0_MEM_FORCE_PD_S  2
-
-/** PCR_UART1_CONF_REG register
- *  UART1 configuration register
- */
-#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)
-/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uart1 apb clock
- */
-#define PCR_UART1_CLK_EN    (BIT(0))
-#define PCR_UART1_CLK_EN_M  (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S)
-#define PCR_UART1_CLK_EN_V  0x00000001U
-#define PCR_UART1_CLK_EN_S  0
-/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uart1 module
- */
-#define PCR_UART1_RST_EN    (BIT(1))
-#define PCR_UART1_RST_EN_M  (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
-#define PCR_UART1_RST_EN_V  0x00000001U
-#define PCR_UART1_RST_EN_S  1
-/** PCR_UART1_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset uart1 module
- */
-#define PCR_UART1_READY    (BIT(2))
-#define PCR_UART1_READY_M  (PCR_UART1_READY_V << PCR_UART1_READY_S)
-#define PCR_UART1_READY_V  0x00000001U
-#define PCR_UART1_READY_S  2
-
-/** PCR_UART1_SCLK_CONF_REG register
- *  UART1_SCLK configuration register
- */
-#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)
-/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_A    0x0000003FU
-#define PCR_UART1_SCLK_DIV_A_M  (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S)
-#define PCR_UART1_SCLK_DIV_A_V  0x0000003FU
-#define PCR_UART1_SCLK_DIV_A_S  0
-/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_B    0x0000003FU
-#define PCR_UART1_SCLK_DIV_B_M  (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S)
-#define PCR_UART1_SCLK_DIV_B_V  0x0000003FU
-#define PCR_UART1_SCLK_DIV_B_S  6
-/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the uart1 function clock.
- */
-#define PCR_UART1_SCLK_DIV_NUM    0x000000FFU
-#define PCR_UART1_SCLK_DIV_NUM_M  (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S)
-#define PCR_UART1_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_UART1_SCLK_DIV_NUM_S  12
-/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_UART1_SCLK_SEL    0x00000003U
-#define PCR_UART1_SCLK_SEL_M  (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
-#define PCR_UART1_SCLK_SEL_V  0x00000003U
-#define PCR_UART1_SCLK_SEL_S  20
-/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable uart0 function clock
- */
-#define PCR_UART1_SCLK_EN    (BIT(22))
-#define PCR_UART1_SCLK_EN_M  (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S)
-#define PCR_UART1_SCLK_EN_V  0x00000001U
-#define PCR_UART1_SCLK_EN_S  22
-
-/** PCR_UART1_PD_CTRL_REG register
- *  UART1 power control register
- */
-#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)
-/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power down UART1 memory.
- */
-#define PCR_UART1_MEM_FORCE_PU    (BIT(1))
-#define PCR_UART1_MEM_FORCE_PU_M  (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S)
-#define PCR_UART1_MEM_FORCE_PU_V  0x00000001U
-#define PCR_UART1_MEM_FORCE_PU_S  1
-/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power up UART1 memory.
- */
-#define PCR_UART1_MEM_FORCE_PD    (BIT(2))
-#define PCR_UART1_MEM_FORCE_PD_M  (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S)
-#define PCR_UART1_MEM_FORCE_PD_V  0x00000001U
-#define PCR_UART1_MEM_FORCE_PD_S  2
-
-/** PCR_MSPI_CONF_REG register
- *  MSPI configuration register
- */
-#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)
-/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable mspi clock, include mspi pll clock
- */
-#define PCR_MSPI_CLK_EN    (BIT(0))
-#define PCR_MSPI_CLK_EN_M  (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S)
-#define PCR_MSPI_CLK_EN_V  0x00000001U
-#define PCR_MSPI_CLK_EN_S  0
-/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset mspi module
- */
-#define PCR_MSPI_RST_EN    (BIT(1))
-#define PCR_MSPI_RST_EN_M  (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
-#define PCR_MSPI_RST_EN_V  0x00000001U
-#define PCR_MSPI_RST_EN_S  1
-/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable mspi pll clock
- */
-#define PCR_MSPI_PLL_CLK_EN    (BIT(2))
-#define PCR_MSPI_PLL_CLK_EN_M  (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S)
-#define PCR_MSPI_PLL_CLK_EN_V  0x00000001U
-#define PCR_MSPI_PLL_CLK_EN_S  2
-/** PCR_MSPI_CLK_SEL : R/W; bitpos: [4:3]; default: 0;
- *  set this field to select clock-source.
- */
-#define PCR_MSPI_CLK_SEL    0x00000003U
-#define PCR_MSPI_CLK_SEL_M  (PCR_MSPI_CLK_SEL_V << PCR_MSPI_CLK_SEL_S)
-#define PCR_MSPI_CLK_SEL_V  0x00000003U
-#define PCR_MSPI_CLK_SEL_S  3
-/** PCR_MSPI_READY : RO; bitpos: [5]; default: 1;
- *  Query this field after reset mspi module
- */
-#define PCR_MSPI_READY    (BIT(5))
-#define PCR_MSPI_READY_M  (PCR_MSPI_READY_V << PCR_MSPI_READY_S)
-#define PCR_MSPI_READY_V  0x00000001U
-#define PCR_MSPI_READY_S  5
-
-/** PCR_MSPI_CLK_CONF_REG register
- *  MSPI_CLK configuration register
- */
-#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
-/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
- *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
- *  low-speed clock-source such as XTAL/FOSC.
- */
-#define PCR_MSPI_FAST_DIV_NUM    0x000000FFU
-#define PCR_MSPI_FAST_DIV_NUM_M  (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S)
-#define PCR_MSPI_FAST_DIV_NUM_V  0x000000FFU
-#define PCR_MSPI_FAST_DIV_NUM_S  0
-
-/** PCR_I2C0_CONF_REG register
- *  I2C configuration register
- */
-#define PCR_I2C0_CONF_REG (DR_REG_PCR_BASE + 0x20)
-/** PCR_I2C0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2c apb clock
- */
-#define PCR_I2C0_CLK_EN    (BIT(0))
-#define PCR_I2C0_CLK_EN_M  (PCR_I2C0_CLK_EN_V << PCR_I2C0_CLK_EN_S)
-#define PCR_I2C0_CLK_EN_V  0x00000001U
-#define PCR_I2C0_CLK_EN_S  0
-/** PCR_I2C0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2c module
- */
-#define PCR_I2C0_RST_EN    (BIT(1))
-#define PCR_I2C0_RST_EN_M  (PCR_I2C0_RST_EN_V << PCR_I2C0_RST_EN_S)
-#define PCR_I2C0_RST_EN_V  0x00000001U
-#define PCR_I2C0_RST_EN_S  1
-/** PCR_I2C0_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset i2c0 module
- */
-#define PCR_I2C0_READY    (BIT(2))
-#define PCR_I2C0_READY_M  (PCR_I2C0_READY_V << PCR_I2C0_READY_S)
-#define PCR_I2C0_READY_V  0x00000001U
-#define PCR_I2C0_READY_S  2
-
-/** PCR_I2C0_SCLK_CONF_REG register
- *  I2C_SCLK configuration register
- */
-#define PCR_I2C0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)
-/** PCR_I2C0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C0_SCLK_DIV_A    0x0000003FU
-#define PCR_I2C0_SCLK_DIV_A_M  (PCR_I2C0_SCLK_DIV_A_V << PCR_I2C0_SCLK_DIV_A_S)
-#define PCR_I2C0_SCLK_DIV_A_V  0x0000003FU
-#define PCR_I2C0_SCLK_DIV_A_S  0
-/** PCR_I2C0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C0_SCLK_DIV_B    0x0000003FU
-#define PCR_I2C0_SCLK_DIV_B_M  (PCR_I2C0_SCLK_DIV_B_V << PCR_I2C0_SCLK_DIV_B_S)
-#define PCR_I2C0_SCLK_DIV_B_V  0x0000003FU
-#define PCR_I2C0_SCLK_DIV_B_S  6
-/** PCR_I2C0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C0_SCLK_DIV_NUM    0x000000FFU
-#define PCR_I2C0_SCLK_DIV_NUM_M  (PCR_I2C0_SCLK_DIV_NUM_V << PCR_I2C0_SCLK_DIV_NUM_S)
-#define PCR_I2C0_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_I2C0_SCLK_DIV_NUM_S  12
-/** PCR_I2C0_SCLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_I2C0_SCLK_SEL    (BIT(20))
-#define PCR_I2C0_SCLK_SEL_M  (PCR_I2C0_SCLK_SEL_V << PCR_I2C0_SCLK_SEL_S)
-#define PCR_I2C0_SCLK_SEL_V  0x00000001U
-#define PCR_I2C0_SCLK_SEL_S  20
-/** PCR_I2C0_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2c function clock
- */
-#define PCR_I2C0_SCLK_EN    (BIT(22))
-#define PCR_I2C0_SCLK_EN_M  (PCR_I2C0_SCLK_EN_V << PCR_I2C0_SCLK_EN_S)
-#define PCR_I2C0_SCLK_EN_V  0x00000001U
-#define PCR_I2C0_SCLK_EN_S  22
-
-/** PCR_I2C1_CONF_REG register
- *  I2C configuration register
- */
-#define PCR_I2C1_CONF_REG (DR_REG_PCR_BASE + 0x28)
-/** PCR_I2C1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2c apb clock
- */
-#define PCR_I2C1_CLK_EN    (BIT(0))
-#define PCR_I2C1_CLK_EN_M  (PCR_I2C1_CLK_EN_V << PCR_I2C1_CLK_EN_S)
-#define PCR_I2C1_CLK_EN_V  0x00000001U
-#define PCR_I2C1_CLK_EN_S  0
-/** PCR_I2C1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2c module
- */
-#define PCR_I2C1_RST_EN    (BIT(1))
-#define PCR_I2C1_RST_EN_M  (PCR_I2C1_RST_EN_V << PCR_I2C1_RST_EN_S)
-#define PCR_I2C1_RST_EN_V  0x00000001U
-#define PCR_I2C1_RST_EN_S  1
-/** PCR_I2C1_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset i2c1 module
- */
-#define PCR_I2C1_READY    (BIT(2))
-#define PCR_I2C1_READY_M  (PCR_I2C1_READY_V << PCR_I2C1_READY_S)
-#define PCR_I2C1_READY_V  0x00000001U
-#define PCR_I2C1_READY_S  2
-
-/** PCR_I2C1_SCLK_CONF_REG register
- *  I2C_SCLK configuration register
- */
-#define PCR_I2C1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x2c)
-/** PCR_I2C1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C1_SCLK_DIV_A    0x0000003FU
-#define PCR_I2C1_SCLK_DIV_A_M  (PCR_I2C1_SCLK_DIV_A_V << PCR_I2C1_SCLK_DIV_A_S)
-#define PCR_I2C1_SCLK_DIV_A_V  0x0000003FU
-#define PCR_I2C1_SCLK_DIV_A_S  0
-/** PCR_I2C1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C1_SCLK_DIV_B    0x0000003FU
-#define PCR_I2C1_SCLK_DIV_B_M  (PCR_I2C1_SCLK_DIV_B_V << PCR_I2C1_SCLK_DIV_B_S)
-#define PCR_I2C1_SCLK_DIV_B_V  0x0000003FU
-#define PCR_I2C1_SCLK_DIV_B_S  6
-/** PCR_I2C1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
- *  The integral part of the frequency divider factor of the i2c function clock.
- */
-#define PCR_I2C1_SCLK_DIV_NUM    0x000000FFU
-#define PCR_I2C1_SCLK_DIV_NUM_M  (PCR_I2C1_SCLK_DIV_NUM_V << PCR_I2C1_SCLK_DIV_NUM_S)
-#define PCR_I2C1_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_I2C1_SCLK_DIV_NUM_S  12
-/** PCR_I2C1_SCLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_I2C1_SCLK_SEL    (BIT(20))
-#define PCR_I2C1_SCLK_SEL_M  (PCR_I2C1_SCLK_SEL_V << PCR_I2C1_SCLK_SEL_S)
-#define PCR_I2C1_SCLK_SEL_V  0x00000001U
-#define PCR_I2C1_SCLK_SEL_S  20
-/** PCR_I2C1_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2c function clock
- */
-#define PCR_I2C1_SCLK_EN    (BIT(22))
-#define PCR_I2C1_SCLK_EN_M  (PCR_I2C1_SCLK_EN_V << PCR_I2C1_SCLK_EN_S)
-#define PCR_I2C1_SCLK_EN_V  0x00000001U
-#define PCR_I2C1_SCLK_EN_S  22
-
-/** PCR_UHCI_CONF_REG register
- *  UHCI configuration register
- */
-#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x30)
-/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable uhci clock
- */
-#define PCR_UHCI_CLK_EN    (BIT(0))
-#define PCR_UHCI_CLK_EN_M  (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S)
-#define PCR_UHCI_CLK_EN_V  0x00000001U
-#define PCR_UHCI_CLK_EN_S  0
-/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset uhci module
- */
-#define PCR_UHCI_RST_EN    (BIT(1))
-#define PCR_UHCI_RST_EN_M  (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S)
-#define PCR_UHCI_RST_EN_V  0x00000001U
-#define PCR_UHCI_RST_EN_S  1
-/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset uhci module
- */
-#define PCR_UHCI_READY    (BIT(2))
-#define PCR_UHCI_READY_M  (PCR_UHCI_READY_V << PCR_UHCI_READY_S)
-#define PCR_UHCI_READY_V  0x00000001U
-#define PCR_UHCI_READY_S  2
-
-/** PCR_RMT_CONF_REG register
- *  RMT configuration register
- */
-#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x34)
-/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable rmt apb clock
- */
-#define PCR_RMT_CLK_EN    (BIT(0))
-#define PCR_RMT_CLK_EN_M  (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S)
-#define PCR_RMT_CLK_EN_V  0x00000001U
-#define PCR_RMT_CLK_EN_S  0
-/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset rmt module
- */
-#define PCR_RMT_RST_EN    (BIT(1))
-#define PCR_RMT_RST_EN_M  (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S)
-#define PCR_RMT_RST_EN_V  0x00000001U
-#define PCR_RMT_RST_EN_S  1
-/** PCR_RMT_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset rmt module
- */
-#define PCR_RMT_READY    (BIT(2))
-#define PCR_RMT_READY_M  (PCR_RMT_READY_V << PCR_RMT_READY_S)
-#define PCR_RMT_READY_V  0x00000001U
-#define PCR_RMT_READY_S  2
-
-/** PCR_RMT_SCLK_CONF_REG register
- *  RMT_SCLK configuration register
- */
-#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38)
-/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_A    0x0000003FU
-#define PCR_RMT_SCLK_DIV_A_M  (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S)
-#define PCR_RMT_SCLK_DIV_A_V  0x0000003FU
-#define PCR_RMT_SCLK_DIV_A_S  0
-/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_B    0x0000003FU
-#define PCR_RMT_SCLK_DIV_B_M  (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S)
-#define PCR_RMT_SCLK_DIV_B_V  0x0000003FU
-#define PCR_RMT_SCLK_DIV_B_S  6
-/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
- *  The integral part of the frequency divider factor of the rmt function clock.
- */
-#define PCR_RMT_SCLK_DIV_NUM    0x000000FFU
-#define PCR_RMT_SCLK_DIV_NUM_M  (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S)
-#define PCR_RMT_SCLK_DIV_NUM_V  0x000000FFU
-#define PCR_RMT_SCLK_DIV_NUM_S  12
-/** PCR_RMT_SCLK_SEL : R/W; bitpos: [20]; default: 1;
- *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
- *  80MHz, 2: FOSC, 3: XTAL.
- */
-#define PCR_RMT_SCLK_SEL    (BIT(20))
-#define PCR_RMT_SCLK_SEL_M  (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S)
-#define PCR_RMT_SCLK_SEL_V  0x00000001U
-#define PCR_RMT_SCLK_SEL_S  20
-/** PCR_RMT_SCLK_EN : R/W; bitpos: [21]; default: 1;
- *  Set 1 to enable rmt function clock
- */
-#define PCR_RMT_SCLK_EN    (BIT(21))
-#define PCR_RMT_SCLK_EN_M  (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S)
-#define PCR_RMT_SCLK_EN_V  0x00000001U
-#define PCR_RMT_SCLK_EN_S  21
-
-/** PCR_LEDC_CONF_REG register
- *  LEDC configuration register
- */
-#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x3c)
-/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ledc apb clock
- */
-#define PCR_LEDC_CLK_EN    (BIT(0))
-#define PCR_LEDC_CLK_EN_M  (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S)
-#define PCR_LEDC_CLK_EN_V  0x00000001U
-#define PCR_LEDC_CLK_EN_S  0
-/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ledc module
- */
-#define PCR_LEDC_RST_EN    (BIT(1))
-#define PCR_LEDC_RST_EN_M  (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
-#define PCR_LEDC_RST_EN_V  0x00000001U
-#define PCR_LEDC_RST_EN_S  1
-/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset ledc module
- */
-#define PCR_LEDC_READY    (BIT(2))
-#define PCR_LEDC_READY_M  (PCR_LEDC_READY_V << PCR_LEDC_READY_S)
-#define PCR_LEDC_READY_V  0x00000001U
-#define PCR_LEDC_READY_S  2
-
-/** PCR_LEDC_SCLK_CONF_REG register
- *  LEDC_SCLK configuration register
- */
-#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
-/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
- *  80MHz, 2: FOSC, 3: XTAL.
- */
-#define PCR_LEDC_SCLK_SEL    0x00000003U
-#define PCR_LEDC_SCLK_SEL_M  (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
-#define PCR_LEDC_SCLK_SEL_V  0x00000003U
-#define PCR_LEDC_SCLK_SEL_S  20
-/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable ledc function clock
- */
-#define PCR_LEDC_SCLK_EN    (BIT(22))
-#define PCR_LEDC_SCLK_EN_M  (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S)
-#define PCR_LEDC_SCLK_EN_V  0x00000001U
-#define PCR_LEDC_SCLK_EN_S  22
-
-/** PCR_TIMERGROUP0_CONF_REG register
- *  TIMERGROUP0 configuration register
- */
-#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x44)
-/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable timer_group0 apb clock
- */
-#define PCR_TG0_CLK_EN    (BIT(0))
-#define PCR_TG0_CLK_EN_M  (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S)
-#define PCR_TG0_CLK_EN_V  0x00000001U
-#define PCR_TG0_CLK_EN_S  0
-/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group0 module
- */
-#define PCR_TG0_RST_EN    (BIT(1))
-#define PCR_TG0_RST_EN_M  (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
-#define PCR_TG0_RST_EN_V  0x00000001U
-#define PCR_TG0_RST_EN_S  1
-/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset timer_group0 wdt module
- */
-#define PCR_TG0_WDT_READY    (BIT(2))
-#define PCR_TG0_WDT_READY_M  (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S)
-#define PCR_TG0_WDT_READY_V  0x00000001U
-#define PCR_TG0_WDT_READY_S  2
-/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1;
- *  Query this field after reset timer_group0 timer0 module
- */
-#define PCR_TG0_TIMER0_READY    (BIT(3))
-#define PCR_TG0_TIMER0_READY_M  (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S)
-#define PCR_TG0_TIMER0_READY_V  0x00000001U
-#define PCR_TG0_TIMER0_READY_S  3
-/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1;
- *  reserved
- */
-#define PCR_TG0_TIMER1_READY    (BIT(4))
-#define PCR_TG0_TIMER1_READY_M  (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S)
-#define PCR_TG0_TIMER1_READY_V  0x00000001U
-#define PCR_TG0_TIMER1_READY_S  4
-
-/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register
- *  TIMERGROUP0_TIMER_CLK configuration register
- */
-#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48)
-/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG0_TIMER_CLK_SEL    0x00000003U
-#define PCR_TG0_TIMER_CLK_SEL_M  (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
-#define PCR_TG0_TIMER_CLK_SEL_V  0x00000003U
-#define PCR_TG0_TIMER_CLK_SEL_S  20
-/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 timer clock
- */
-#define PCR_TG0_TIMER_CLK_EN    (BIT(22))
-#define PCR_TG0_TIMER_CLK_EN_M  (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S)
-#define PCR_TG0_TIMER_CLK_EN_V  0x00000001U
-#define PCR_TG0_TIMER_CLK_EN_S  22
-
-/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register
- *  TIMERGROUP0_WDT_CLK configuration register
- */
-#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c)
-/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG0_WDT_CLK_SEL    0x00000003U
-#define PCR_TG0_WDT_CLK_SEL_M  (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
-#define PCR_TG0_WDT_CLK_SEL_V  0x00000003U
-#define PCR_TG0_WDT_CLK_SEL_S  20
-/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 wdt clock
- */
-#define PCR_TG0_WDT_CLK_EN    (BIT(22))
-#define PCR_TG0_WDT_CLK_EN_M  (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S)
-#define PCR_TG0_WDT_CLK_EN_V  0x00000001U
-#define PCR_TG0_WDT_CLK_EN_S  22
-
-/** PCR_TIMERGROUP1_CONF_REG register
- *  TIMERGROUP1 configuration register
- */
-#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x50)
-/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable timer_group1 apb clock
- */
-#define PCR_TG1_CLK_EN    (BIT(0))
-#define PCR_TG1_CLK_EN_M  (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S)
-#define PCR_TG1_CLK_EN_V  0x00000001U
-#define PCR_TG1_CLK_EN_S  0
-/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset timer_group1 module
- */
-#define PCR_TG1_RST_EN    (BIT(1))
-#define PCR_TG1_RST_EN_M  (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
-#define PCR_TG1_RST_EN_V  0x00000001U
-#define PCR_TG1_RST_EN_S  1
-/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset timer_group1 wdt module
- */
-#define PCR_TG1_WDT_READY    (BIT(2))
-#define PCR_TG1_WDT_READY_M  (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S)
-#define PCR_TG1_WDT_READY_V  0x00000001U
-#define PCR_TG1_WDT_READY_S  2
-/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1;
- *  Query this field after reset timer_group1 timer0 module
- */
-#define PCR_TG1_TIMER0_READY    (BIT(3))
-#define PCR_TG1_TIMER0_READY_M  (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S)
-#define PCR_TG1_TIMER0_READY_V  0x00000001U
-#define PCR_TG1_TIMER0_READY_S  3
-/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1;
- *  reserved
- */
-#define PCR_TG1_TIMER1_READY    (BIT(4))
-#define PCR_TG1_TIMER1_READY_M  (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S)
-#define PCR_TG1_TIMER1_READY_V  0x00000001U
-#define PCR_TG1_TIMER1_READY_S  4
-
-/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register
- *  TIMERGROUP1_TIMER_CLK configuration register
- */
-#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54)
-/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG1_TIMER_CLK_SEL    0x00000003U
-#define PCR_TG1_TIMER_CLK_SEL_M  (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
-#define PCR_TG1_TIMER_CLK_SEL_V  0x00000003U
-#define PCR_TG1_TIMER_CLK_SEL_S  20
-/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group1 timer clock
- */
-#define PCR_TG1_TIMER_CLK_EN    (BIT(22))
-#define PCR_TG1_TIMER_CLK_EN_M  (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S)
-#define PCR_TG1_TIMER_CLK_EN_V  0x00000001U
-#define PCR_TG1_TIMER_CLK_EN_S  22
-
-/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register
- *  TIMERGROUP1_WDT_CLK configuration register
- */
-#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58)
-/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_TG1_WDT_CLK_SEL    0x00000003U
-#define PCR_TG1_WDT_CLK_SEL_M  (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
-#define PCR_TG1_WDT_CLK_SEL_V  0x00000003U
-#define PCR_TG1_WDT_CLK_SEL_S  20
-/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable timer_group0 wdt clock
- */
-#define PCR_TG1_WDT_CLK_EN    (BIT(22))
-#define PCR_TG1_WDT_CLK_EN_M  (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S)
-#define PCR_TG1_WDT_CLK_EN_V  0x00000001U
-#define PCR_TG1_WDT_CLK_EN_S  22
-
-/** PCR_SYSTIMER_CONF_REG register
- *  SYSTIMER configuration register
- */
-#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x5c)
-/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable systimer apb clock
- */
-#define PCR_SYSTIMER_CLK_EN    (BIT(0))
-#define PCR_SYSTIMER_CLK_EN_M  (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S)
-#define PCR_SYSTIMER_CLK_EN_V  0x00000001U
-#define PCR_SYSTIMER_CLK_EN_S  0
-/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset systimer module
- */
-#define PCR_SYSTIMER_RST_EN    (BIT(1))
-#define PCR_SYSTIMER_RST_EN_M  (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
-#define PCR_SYSTIMER_RST_EN_V  0x00000001U
-#define PCR_SYSTIMER_RST_EN_S  1
-/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset systimer module
- */
-#define PCR_SYSTIMER_READY    (BIT(2))
-#define PCR_SYSTIMER_READY_M  (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S)
-#define PCR_SYSTIMER_READY_V  0x00000001U
-#define PCR_SYSTIMER_READY_S  2
-
-/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register
- *  SYSTIMER_FUNC_CLK configuration register
- */
-#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60)
-/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_SYSTIMER_FUNC_CLK_SEL    (BIT(20))
-#define PCR_SYSTIMER_FUNC_CLK_SEL_M  (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
-#define PCR_SYSTIMER_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_SYSTIMER_FUNC_CLK_SEL_S  20
-/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable systimer function clock
- */
-#define PCR_SYSTIMER_FUNC_CLK_EN    (BIT(22))
-#define PCR_SYSTIMER_FUNC_CLK_EN_M  (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S)
-#define PCR_SYSTIMER_FUNC_CLK_EN_V  0x00000001U
-#define PCR_SYSTIMER_FUNC_CLK_EN_S  22
-
-/** PCR_TWAI0_CONF_REG register
- *  TWAI0 configuration register
- */
-#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x64)
-/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable twai0 apb clock
- */
-#define PCR_TWAI0_CLK_EN    (BIT(0))
-#define PCR_TWAI0_CLK_EN_M  (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S)
-#define PCR_TWAI0_CLK_EN_V  0x00000001U
-#define PCR_TWAI0_CLK_EN_S  0
-/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset twai0 module
- */
-#define PCR_TWAI0_RST_EN    (BIT(1))
-#define PCR_TWAI0_RST_EN_M  (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S)
-#define PCR_TWAI0_RST_EN_V  0x00000001U
-#define PCR_TWAI0_RST_EN_S  1
-/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset twai0 module
- */
-#define PCR_TWAI0_READY    (BIT(2))
-#define PCR_TWAI0_READY_M  (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S)
-#define PCR_TWAI0_READY_V  0x00000001U
-#define PCR_TWAI0_READY_S  2
-
-/** PCR_TWAI0_FUNC_CLK_CONF_REG register
- *  TWAI0_FUNC_CLK configuration register
- */
-#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68)
-/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
- */
-#define PCR_TWAI0_FUNC_CLK_SEL    (BIT(20))
-#define PCR_TWAI0_FUNC_CLK_SEL_M  (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S)
-#define PCR_TWAI0_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_TWAI0_FUNC_CLK_SEL_S  20
-/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable twai0 function clock
- */
-#define PCR_TWAI0_FUNC_CLK_EN    (BIT(22))
-#define PCR_TWAI0_FUNC_CLK_EN_M  (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S)
-#define PCR_TWAI0_FUNC_CLK_EN_V  0x00000001U
-#define PCR_TWAI0_FUNC_CLK_EN_S  22
-
-/** PCR_I2S_CONF_REG register
- *  I2S configuration register
- */
-#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c)
-/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable i2s apb clock
- */
-#define PCR_I2S_CLK_EN    (BIT(0))
-#define PCR_I2S_CLK_EN_M  (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S)
-#define PCR_I2S_CLK_EN_V  0x00000001U
-#define PCR_I2S_CLK_EN_S  0
-/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset i2s module
- */
-#define PCR_I2S_RST_EN    (BIT(1))
-#define PCR_I2S_RST_EN_M  (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
-#define PCR_I2S_RST_EN_V  0x00000001U
-#define PCR_I2S_RST_EN_S  1
-/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1;
- *  Query this field before using i2s rx function, after reset i2s module
- */
-#define PCR_I2S_RX_READY    (BIT(2))
-#define PCR_I2S_RX_READY_M  (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S)
-#define PCR_I2S_RX_READY_V  0x00000001U
-#define PCR_I2S_RX_READY_S  2
-/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1;
- *  Query this field before using i2s tx function, after reset i2s module
- */
-#define PCR_I2S_TX_READY    (BIT(3))
-#define PCR_I2S_TX_READY_M  (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S)
-#define PCR_I2S_TX_READY_V  0x00000001U
-#define PCR_I2S_TX_READY_S  3
-
-/** PCR_I2S_TX_CLKM_CONF_REG register
- *  I2S_TX_CLKM configuration register
- */
-#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70)
-/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
- *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
- *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
- *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
- *  (n+1)-div] + y * (n+1)-div.
- */
-#define PCR_I2S_TX_CLKM_DIV_NUM    0x000000FFU
-#define PCR_I2S_TX_CLKM_DIV_NUM_M  (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S)
-#define PCR_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_I2S_TX_CLKM_DIV_NUM_S  12
-/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
- *  I2S_MCLK_in.
- */
-#define PCR_I2S_TX_CLKM_SEL    0x00000003U
-#define PCR_I2S_TX_CLKM_SEL_M  (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
-#define PCR_I2S_TX_CLKM_SEL_V  0x00000003U
-#define PCR_I2S_TX_CLKM_SEL_S  20
-/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2s_tx function clock
- */
-#define PCR_I2S_TX_CLKM_EN    (BIT(22))
-#define PCR_I2S_TX_CLKM_EN_M  (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S)
-#define PCR_I2S_TX_CLKM_EN_V  0x00000001U
-#define PCR_I2S_TX_CLKM_EN_S  22
-
-/** PCR_I2S_TX_CLKM_DIV_CONF_REG register
- *  I2S_TX_CLKM_DIV configuration register
- */
-#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74)
-/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Z is (a-b).
- */
-#define PCR_I2S_TX_CLKM_DIV_Z    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Z_M  (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S)
-#define PCR_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Z_S  0
-/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define PCR_I2S_TX_CLKM_DIV_Y    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Y_M  (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S)
-#define PCR_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_Y_S  9
-/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define PCR_I2S_TX_CLKM_DIV_X    0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_X_M  (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S)
-#define PCR_I2S_TX_CLKM_DIV_X_V  0x000001FFU
-#define PCR_I2S_TX_CLKM_DIV_X_S  18
-/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_TX_CLKM_DIV_YN1 is 1.
- */
-#define PCR_I2S_TX_CLKM_DIV_YN1    (BIT(27))
-#define PCR_I2S_TX_CLKM_DIV_YN1_M  (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S)
-#define PCR_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
-#define PCR_I2S_TX_CLKM_DIV_YN1_S  27
-
-/** PCR_I2S_RX_CLKM_CONF_REG register
- *  I2S_RX_CLKM configuration register
- */
-#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78)
-/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
- *  Integral I2S clock divider value
- */
-#define PCR_I2S_RX_CLKM_DIV_NUM    0x000000FFU
-#define PCR_I2S_RX_CLKM_DIV_NUM_M  (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S)
-#define PCR_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_I2S_RX_CLKM_DIV_NUM_S  12
-/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
- */
-#define PCR_I2S_RX_CLKM_SEL    0x00000003U
-#define PCR_I2S_RX_CLKM_SEL_M  (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
-#define PCR_I2S_RX_CLKM_SEL_V  0x00000003U
-#define PCR_I2S_RX_CLKM_SEL_S  20
-/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable i2s_rx function clock
- */
-#define PCR_I2S_RX_CLKM_EN    (BIT(22))
-#define PCR_I2S_RX_CLKM_EN_M  (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S)
-#define PCR_I2S_RX_CLKM_EN_V  0x00000001U
-#define PCR_I2S_RX_CLKM_EN_S  22
-/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
- *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
- */
-#define PCR_I2S_MCLK_SEL    (BIT(23))
-#define PCR_I2S_MCLK_SEL_M  (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
-#define PCR_I2S_MCLK_SEL_V  0x00000001U
-#define PCR_I2S_MCLK_SEL_S  23
-
-/** PCR_I2S_RX_CLKM_DIV_CONF_REG register
- *  I2S_RX_CLKM_DIV configuration register
- */
-#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c)
-/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Z is (a-b).
- */
-#define PCR_I2S_RX_CLKM_DIV_Z    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Z_M  (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S)
-#define PCR_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Z_S  0
-/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
- */
-#define PCR_I2S_RX_CLKM_DIV_Y    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Y_M  (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S)
-#define PCR_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_Y_S  9
-/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
- *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
- */
-#define PCR_I2S_RX_CLKM_DIV_X    0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_X_M  (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S)
-#define PCR_I2S_RX_CLKM_DIV_X_V  0x000001FFU
-#define PCR_I2S_RX_CLKM_DIV_X_S  18
-/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
- *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
- *  I2S_RX_CLKM_DIV_YN1 is 1.
- */
-#define PCR_I2S_RX_CLKM_DIV_YN1    (BIT(27))
-#define PCR_I2S_RX_CLKM_DIV_YN1_M  (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S)
-#define PCR_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
-#define PCR_I2S_RX_CLKM_DIV_YN1_S  27
-
-/** PCR_SARADC_CONF_REG register
- *  SARADC configuration register
- */
-#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80)
-/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  no use
- */
-#define PCR_SARADC_CLK_EN    (BIT(0))
-#define PCR_SARADC_CLK_EN_M  (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S)
-#define PCR_SARADC_CLK_EN_V  0x00000001U
-#define PCR_SARADC_CLK_EN_S  0
-/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset function_register of saradc module
- */
-#define PCR_SARADC_RST_EN    (BIT(1))
-#define PCR_SARADC_RST_EN_M  (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
-#define PCR_SARADC_RST_EN_V  0x00000001U
-#define PCR_SARADC_RST_EN_S  1
-/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable saradc apb clock
- */
-#define PCR_SARADC_REG_CLK_EN    (BIT(2))
-#define PCR_SARADC_REG_CLK_EN_M  (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S)
-#define PCR_SARADC_REG_CLK_EN_V  0x00000001U
-#define PCR_SARADC_REG_CLK_EN_S  2
-/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
- *  Set 0 to reset apb_register of saradc module
- */
-#define PCR_SARADC_REG_RST_EN    (BIT(3))
-#define PCR_SARADC_REG_RST_EN_M  (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
-#define PCR_SARADC_REG_RST_EN_V  0x00000001U
-#define PCR_SARADC_REG_RST_EN_S  3
-
-/** PCR_SARADC_CLKM_CONF_REG register
- *  SARADC_CLKM configuration register
- */
-#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84)
-/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_A    0x0000003FU
-#define PCR_SARADC_CLKM_DIV_A_M  (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S)
-#define PCR_SARADC_CLKM_DIV_A_V  0x0000003FU
-#define PCR_SARADC_CLKM_DIV_A_S  0
-/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_B    0x0000003FU
-#define PCR_SARADC_CLKM_DIV_B_M  (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S)
-#define PCR_SARADC_CLKM_DIV_B_V  0x0000003FU
-#define PCR_SARADC_CLKM_DIV_B_S  6
-/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
- *  The integral part of the frequency divider factor of the saradc function clock.
- */
-#define PCR_SARADC_CLKM_DIV_NUM    0x000000FFU
-#define PCR_SARADC_CLKM_DIV_NUM_M  (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S)
-#define PCR_SARADC_CLKM_DIV_NUM_V  0x000000FFU
-#define PCR_SARADC_CLKM_DIV_NUM_S  12
-/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_SARADC_CLKM_SEL    0x00000003U
-#define PCR_SARADC_CLKM_SEL_M  (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
-#define PCR_SARADC_CLKM_SEL_V  0x00000003U
-#define PCR_SARADC_CLKM_SEL_S  20
-/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable saradc function clock
- */
-#define PCR_SARADC_CLKM_EN    (BIT(22))
-#define PCR_SARADC_CLKM_EN_M  (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S)
-#define PCR_SARADC_CLKM_EN_V  0x00000001U
-#define PCR_SARADC_CLKM_EN_S  22
-
-/** PCR_TSENS_CLK_CONF_REG register
- *  TSENS_CLK configuration register
- */
-#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88)
-/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
- */
-#define PCR_TSENS_CLK_SEL    (BIT(20))
-#define PCR_TSENS_CLK_SEL_M  (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
-#define PCR_TSENS_CLK_SEL_V  0x00000001U
-#define PCR_TSENS_CLK_SEL_S  20
-/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable tsens clock
- */
-#define PCR_TSENS_CLK_EN    (BIT(22))
-#define PCR_TSENS_CLK_EN_M  (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S)
-#define PCR_TSENS_CLK_EN_V  0x00000001U
-#define PCR_TSENS_CLK_EN_S  22
-/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
- *  Set 0 to reset tsens module
- */
-#define PCR_TSENS_RST_EN    (BIT(23))
-#define PCR_TSENS_RST_EN_M  (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
-#define PCR_TSENS_RST_EN_V  0x00000001U
-#define PCR_TSENS_RST_EN_S  23
-
-/** PCR_USB_DEVICE_CONF_REG register
- *  USB_DEVICE configuration register
- */
-#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c)
-/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable usb_device clock
- */
-#define PCR_USB_DEVICE_CLK_EN    (BIT(0))
-#define PCR_USB_DEVICE_CLK_EN_M  (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S)
-#define PCR_USB_DEVICE_CLK_EN_V  0x00000001U
-#define PCR_USB_DEVICE_CLK_EN_S  0
-/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset usb_device module
- */
-#define PCR_USB_DEVICE_RST_EN    (BIT(1))
-#define PCR_USB_DEVICE_RST_EN_M  (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
-#define PCR_USB_DEVICE_RST_EN_V  0x00000001U
-#define PCR_USB_DEVICE_RST_EN_S  1
-/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset usb_device module
- */
-#define PCR_USB_DEVICE_READY    (BIT(2))
-#define PCR_USB_DEVICE_READY_M  (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S)
-#define PCR_USB_DEVICE_READY_V  0x00000001U
-#define PCR_USB_DEVICE_READY_S  2
-
-/** PCR_INTMTX_CONF_REG register
- *  INTMTX configuration register
- */
-#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90)
-/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable intmtx clock
- */
-#define PCR_INTMTX_CLK_EN    (BIT(0))
-#define PCR_INTMTX_CLK_EN_M  (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S)
-#define PCR_INTMTX_CLK_EN_V  0x00000001U
-#define PCR_INTMTX_CLK_EN_S  0
-/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset intmtx module
- */
-#define PCR_INTMTX_RST_EN    (BIT(1))
-#define PCR_INTMTX_RST_EN_M  (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
-#define PCR_INTMTX_RST_EN_V  0x00000001U
-#define PCR_INTMTX_RST_EN_S  1
-/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset intmtx module
- */
-#define PCR_INTMTX_READY    (BIT(2))
-#define PCR_INTMTX_READY_M  (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S)
-#define PCR_INTMTX_READY_V  0x00000001U
-#define PCR_INTMTX_READY_S  2
-
-/** PCR_PCNT_CONF_REG register
- *  PCNT configuration register
- */
-#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94)
-/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable pcnt clock
- */
-#define PCR_PCNT_CLK_EN    (BIT(0))
-#define PCR_PCNT_CLK_EN_M  (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S)
-#define PCR_PCNT_CLK_EN_V  0x00000001U
-#define PCR_PCNT_CLK_EN_S  0
-/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset pcnt module
- */
-#define PCR_PCNT_RST_EN    (BIT(1))
-#define PCR_PCNT_RST_EN_M  (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S)
-#define PCR_PCNT_RST_EN_V  0x00000001U
-#define PCR_PCNT_RST_EN_S  1
-/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset pcnt module
- */
-#define PCR_PCNT_READY    (BIT(2))
-#define PCR_PCNT_READY_M  (PCR_PCNT_READY_V << PCR_PCNT_READY_S)
-#define PCR_PCNT_READY_V  0x00000001U
-#define PCR_PCNT_READY_S  2
-
-/** PCR_ETM_CONF_REG register
- *  ETM configuration register
- */
-#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98)
-/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable etm clock
- */
-#define PCR_ETM_CLK_EN    (BIT(0))
-#define PCR_ETM_CLK_EN_M  (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S)
-#define PCR_ETM_CLK_EN_V  0x00000001U
-#define PCR_ETM_CLK_EN_S  0
-/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset etm module
- */
-#define PCR_ETM_RST_EN    (BIT(1))
-#define PCR_ETM_RST_EN_M  (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
-#define PCR_ETM_RST_EN_V  0x00000001U
-#define PCR_ETM_RST_EN_S  1
-/** PCR_ETM_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset etm module
- */
-#define PCR_ETM_READY    (BIT(2))
-#define PCR_ETM_READY_M  (PCR_ETM_READY_V << PCR_ETM_READY_S)
-#define PCR_ETM_READY_V  0x00000001U
-#define PCR_ETM_READY_S  2
-
-/** PCR_PWM_CONF_REG register
- *  PWM configuration register
- */
-#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c)
-/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable pwm clock
- */
-#define PCR_PWM_CLK_EN    (BIT(0))
-#define PCR_PWM_CLK_EN_M  (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S)
-#define PCR_PWM_CLK_EN_V  0x00000001U
-#define PCR_PWM_CLK_EN_S  0
-/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset pwm module
- */
-#define PCR_PWM_RST_EN    (BIT(1))
-#define PCR_PWM_RST_EN_M  (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S)
-#define PCR_PWM_RST_EN_V  0x00000001U
-#define PCR_PWM_RST_EN_S  1
-/** PCR_PWM_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset pwm module
- */
-#define PCR_PWM_READY    (BIT(2))
-#define PCR_PWM_READY_M  (PCR_PWM_READY_V << PCR_PWM_READY_S)
-#define PCR_PWM_READY_V  0x00000001U
-#define PCR_PWM_READY_S  2
-
-/** PCR_PWM_CLK_CONF_REG register
- *  PWM_CLK configuration register
- */
-#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0)
-/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
- *  The integral part of the frequency divider factor of the pwm function clock.
- */
-#define PCR_PWM_DIV_NUM    0x000000FFU
-#define PCR_PWM_DIV_NUM_M  (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S)
-#define PCR_PWM_DIV_NUM_V  0x000000FFU
-#define PCR_PWM_DIV_NUM_S  12
-/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
- *  160MHz, 2: XTAL, 3: FOSC.
- */
-#define PCR_PWM_CLKM_SEL    0x00000003U
-#define PCR_PWM_CLKM_SEL_M  (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S)
-#define PCR_PWM_CLKM_SEL_V  0x00000003U
-#define PCR_PWM_CLKM_SEL_S  20
-/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  set this field as 1 to activate pwm clkm.
- */
-#define PCR_PWM_CLKM_EN    (BIT(22))
-#define PCR_PWM_CLKM_EN_M  (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S)
-#define PCR_PWM_CLKM_EN_V  0x00000001U
-#define PCR_PWM_CLKM_EN_S  22
-
-/** PCR_PARL_IO_CONF_REG register
- *  PARL_IO configuration register
- */
-#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4)
-/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable parl apb clock
- */
-#define PCR_PARL_CLK_EN    (BIT(0))
-#define PCR_PARL_CLK_EN_M  (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S)
-#define PCR_PARL_CLK_EN_V  0x00000001U
-#define PCR_PARL_CLK_EN_S  0
-/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset parl apb reg
- */
-#define PCR_PARL_RST_EN    (BIT(1))
-#define PCR_PARL_RST_EN_M  (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S)
-#define PCR_PARL_RST_EN_V  0x00000001U
-#define PCR_PARL_RST_EN_S  1
-/** PCR_PARL_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset parl module
- */
-#define PCR_PARL_READY    (BIT(2))
-#define PCR_PARL_READY_M  (PCR_PARL_READY_V << PCR_PARL_READY_S)
-#define PCR_PARL_READY_V  0x00000001U
-#define PCR_PARL_READY_S  2
-
-/** PCR_PARL_CLK_RX_CONF_REG register
- *  PARL_CLK_RX configuration register
- */
-#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8)
-/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
- *  The integral part of the frequency divider factor of the parl rx clock.
- */
-#define PCR_PARL_CLK_RX_DIV_NUM    0x0000FFFFU
-#define PCR_PARL_CLK_RX_DIV_NUM_M  (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S)
-#define PCR_PARL_CLK_RX_DIV_NUM_V  0x0000FFFFU
-#define PCR_PARL_CLK_RX_DIV_NUM_S  0
-/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  user clock from pad.
- */
-#define PCR_PARL_CLK_RX_SEL    0x00000003U
-#define PCR_PARL_CLK_RX_SEL_M  (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S)
-#define PCR_PARL_CLK_RX_SEL_V  0x00000003U
-#define PCR_PARL_CLK_RX_SEL_S  16
-/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1;
- *  Set 1 to enable parl rx clock
- */
-#define PCR_PARL_CLK_RX_EN    (BIT(18))
-#define PCR_PARL_CLK_RX_EN_M  (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S)
-#define PCR_PARL_CLK_RX_EN_V  0x00000001U
-#define PCR_PARL_CLK_RX_EN_S  18
-/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0;
- *  Set 0 to reset parl rx module
- */
-#define PCR_PARL_RX_RST_EN    (BIT(19))
-#define PCR_PARL_RX_RST_EN_M  (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S)
-#define PCR_PARL_RX_RST_EN_V  0x00000001U
-#define PCR_PARL_RX_RST_EN_S  19
-
-/** PCR_PARL_CLK_TX_CONF_REG register
- *  PARL_CLK_TX configuration register
- */
-#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac)
-/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
- *  The integral part of the frequency divider factor of the parl tx clock.
- */
-#define PCR_PARL_CLK_TX_DIV_NUM    0x0000FFFFU
-#define PCR_PARL_CLK_TX_DIV_NUM_M  (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S)
-#define PCR_PARL_CLK_TX_DIV_NUM_V  0x0000FFFFU
-#define PCR_PARL_CLK_TX_DIV_NUM_S  0
-/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
- *  user clock from pad.
- */
-#define PCR_PARL_CLK_TX_SEL    0x00000003U
-#define PCR_PARL_CLK_TX_SEL_M  (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S)
-#define PCR_PARL_CLK_TX_SEL_V  0x00000003U
-#define PCR_PARL_CLK_TX_SEL_S  16
-/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1;
- *  Set 1 to enable parl tx clock
- */
-#define PCR_PARL_CLK_TX_EN    (BIT(18))
-#define PCR_PARL_CLK_TX_EN_M  (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S)
-#define PCR_PARL_CLK_TX_EN_V  0x00000001U
-#define PCR_PARL_CLK_TX_EN_S  18
-/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0;
- *  Set 0 to reset parl tx module
- */
-#define PCR_PARL_TX_RST_EN    (BIT(19))
-#define PCR_PARL_TX_RST_EN_M  (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S)
-#define PCR_PARL_TX_RST_EN_V  0x00000001U
-#define PCR_PARL_TX_RST_EN_S  19
-
-/** PCR_PVT_MONITOR_CONF_REG register
- *  PVT_MONITOR configuration register
- */
-#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0)
-/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable apb clock of pvt module
- */
-#define PCR_PVT_MONITOR_CLK_EN    (BIT(0))
-#define PCR_PVT_MONITOR_CLK_EN_M  (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S)
-#define PCR_PVT_MONITOR_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_CLK_EN_S  0
-/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset all pvt monitor module
- */
-#define PCR_PVT_MONITOR_RST_EN    (BIT(1))
-#define PCR_PVT_MONITOR_RST_EN_M  (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S)
-#define PCR_PVT_MONITOR_RST_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_RST_EN_S  1
-/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable function clock of modem pvt module
- */
-#define PCR_PVT_MONITOR_SITE1_CLK_EN    (BIT(2))
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_M  (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE1_CLK_EN_S  2
-/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  Set 1 to enable function clock of cpu pvt module
- */
-#define PCR_PVT_MONITOR_SITE2_CLK_EN    (BIT(3))
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_M  (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE2_CLK_EN_S  3
-/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  Set 1 to enable function clock of hp_peri pvt module
- */
-#define PCR_PVT_MONITOR_SITE3_CLK_EN    (BIT(4))
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_M  (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S)
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_SITE3_CLK_EN_S  4
-
-/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register
- *  PVT_MONITOR function clock configuration register
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4)
-/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0;
- *  The integral part of the frequency divider factor of the pvt_monitor function clock.
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM    0x0000000FU
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M  (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
-#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
-/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
- *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
- *  divided by 3.
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M  (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V  0x00000001U
-#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S  20
-/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable source clock of pvt sitex
- */
-#define PCR_PVT_MONITOR_FUNC_CLK_EN    (BIT(22))
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_M  (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S)
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_V  0x00000001U
-#define PCR_PVT_MONITOR_FUNC_CLK_EN_S  22
-
-/** PCR_GDMA_CONF_REG register
- *  GDMA configuration register
- */
-#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8)
-/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable gdma clock
- */
-#define PCR_GDMA_CLK_EN    (BIT(0))
-#define PCR_GDMA_CLK_EN_M  (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S)
-#define PCR_GDMA_CLK_EN_V  0x00000001U
-#define PCR_GDMA_CLK_EN_S  0
-/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset gdma module
- */
-#define PCR_GDMA_RST_EN    (BIT(1))
-#define PCR_GDMA_RST_EN_M  (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
-#define PCR_GDMA_RST_EN_V  0x00000001U
-#define PCR_GDMA_RST_EN_S  1
-
-/** PCR_SPI2_CONF_REG register
- *  SPI2 configuration register
- */
-#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc)
-/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable spi2 apb clock
- */
-#define PCR_SPI2_CLK_EN    (BIT(0))
-#define PCR_SPI2_CLK_EN_M  (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S)
-#define PCR_SPI2_CLK_EN_V  0x00000001U
-#define PCR_SPI2_CLK_EN_S  0
-/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset spi2 module
- */
-#define PCR_SPI2_RST_EN    (BIT(1))
-#define PCR_SPI2_RST_EN_M  (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
-#define PCR_SPI2_RST_EN_V  0x00000001U
-#define PCR_SPI2_RST_EN_S  1
-/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset spi2 module
- */
-#define PCR_SPI2_READY    (BIT(2))
-#define PCR_SPI2_READY_M  (PCR_SPI2_READY_V << PCR_SPI2_READY_S)
-#define PCR_SPI2_READY_V  0x00000001U
-#define PCR_SPI2_READY_S  2
-
-/** PCR_SPI2_CLKM_CONF_REG register
- *  SPI2_CLKM configuration register
- */
-#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0)
-/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
- *  reserved.
- */
-#define PCR_SPI2_CLKM_SEL    0x00000003U
-#define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
-#define PCR_SPI2_CLKM_SEL_V  0x00000003U
-#define PCR_SPI2_CLKM_SEL_S  20
-/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable spi2 function clock
- */
-#define PCR_SPI2_CLKM_EN    (BIT(22))
-#define PCR_SPI2_CLKM_EN_M  (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S)
-#define PCR_SPI2_CLKM_EN_V  0x00000001U
-#define PCR_SPI2_CLKM_EN_S  22
-
-/** PCR_AES_CONF_REG register
- *  AES configuration register
- */
-#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4)
-/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable aes clock
- */
-#define PCR_AES_CLK_EN    (BIT(0))
-#define PCR_AES_CLK_EN_M  (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
-#define PCR_AES_CLK_EN_V  0x00000001U
-#define PCR_AES_CLK_EN_S  0
-/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset aes module
- */
-#define PCR_AES_RST_EN    (BIT(1))
-#define PCR_AES_RST_EN_M  (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
-#define PCR_AES_RST_EN_V  0x00000001U
-#define PCR_AES_RST_EN_S  1
-/** PCR_AES_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset aes module
- */
-#define PCR_AES_READY    (BIT(2))
-#define PCR_AES_READY_M  (PCR_AES_READY_V << PCR_AES_READY_S)
-#define PCR_AES_READY_V  0x00000001U
-#define PCR_AES_READY_S  2
-
-/** PCR_SHA_CONF_REG register
- *  SHA configuration register
- */
-#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8)
-/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable sha clock
- */
-#define PCR_SHA_CLK_EN    (BIT(0))
-#define PCR_SHA_CLK_EN_M  (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S)
-#define PCR_SHA_CLK_EN_V  0x00000001U
-#define PCR_SHA_CLK_EN_S  0
-/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset sha module
- */
-#define PCR_SHA_RST_EN    (BIT(1))
-#define PCR_SHA_RST_EN_M  (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
-#define PCR_SHA_RST_EN_V  0x00000001U
-#define PCR_SHA_RST_EN_S  1
-/** PCR_SHA_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset sha module
- */
-#define PCR_SHA_READY    (BIT(2))
-#define PCR_SHA_READY_M  (PCR_SHA_READY_V << PCR_SHA_READY_S)
-#define PCR_SHA_READY_V  0x00000001U
-#define PCR_SHA_READY_S  2
-
-/** PCR_RSA_CONF_REG register
- *  RSA configuration register
- */
-#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc)
-/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable rsa clock
- */
-#define PCR_RSA_CLK_EN    (BIT(0))
-#define PCR_RSA_CLK_EN_M  (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
-#define PCR_RSA_CLK_EN_V  0x00000001U
-#define PCR_RSA_CLK_EN_S  0
-/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset rsa module
- */
-#define PCR_RSA_RST_EN    (BIT(1))
-#define PCR_RSA_RST_EN_M  (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
-#define PCR_RSA_RST_EN_V  0x00000001U
-#define PCR_RSA_RST_EN_S  1
-/** PCR_RSA_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset rsa module
- */
-#define PCR_RSA_READY    (BIT(2))
-#define PCR_RSA_READY_M  (PCR_RSA_READY_V << PCR_RSA_READY_S)
-#define PCR_RSA_READY_V  0x00000001U
-#define PCR_RSA_READY_S  2
-
-/** PCR_RSA_PD_CTRL_REG register
- *  RSA power control register
- */
-#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0)
-/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down rsa internal memory.
- */
-#define PCR_RSA_MEM_PD    (BIT(0))
-#define PCR_RSA_MEM_PD_M  (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
-#define PCR_RSA_MEM_PD_V  0x00000001U
-#define PCR_RSA_MEM_PD_S  0
-/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up rsa internal memory
- */
-#define PCR_RSA_MEM_FORCE_PU    (BIT(1))
-#define PCR_RSA_MEM_FORCE_PU_M  (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
-#define PCR_RSA_MEM_FORCE_PU_V  0x00000001U
-#define PCR_RSA_MEM_FORCE_PU_S  1
-/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down rsa internal memory.
- */
-#define PCR_RSA_MEM_FORCE_PD    (BIT(2))
-#define PCR_RSA_MEM_FORCE_PD_M  (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
-#define PCR_RSA_MEM_FORCE_PD_V  0x00000001U
-#define PCR_RSA_MEM_FORCE_PD_S  2
-
-/** PCR_ECC_CONF_REG register
- *  ECC configuration register
- */
-#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4)
-/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ecc clock
- */
-#define PCR_ECC_CLK_EN    (BIT(0))
-#define PCR_ECC_CLK_EN_M  (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S)
-#define PCR_ECC_CLK_EN_V  0x00000001U
-#define PCR_ECC_CLK_EN_S  0
-/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ecc module
- */
-#define PCR_ECC_RST_EN    (BIT(1))
-#define PCR_ECC_RST_EN_M  (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
-#define PCR_ECC_RST_EN_V  0x00000001U
-#define PCR_ECC_RST_EN_S  1
-/** PCR_ECC_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset ecc module
- */
-#define PCR_ECC_READY    (BIT(2))
-#define PCR_ECC_READY_M  (PCR_ECC_READY_V << PCR_ECC_READY_S)
-#define PCR_ECC_READY_V  0x00000001U
-#define PCR_ECC_READY_S  2
-
-/** PCR_ECC_PD_CTRL_REG register
- *  ECC power control register
- */
-#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8)
-/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down ecc internal memory.
- */
-#define PCR_ECC_MEM_PD    (BIT(0))
-#define PCR_ECC_MEM_PD_M  (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S)
-#define PCR_ECC_MEM_PD_V  0x00000001U
-#define PCR_ECC_MEM_PD_S  0
-/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up ecc internal memory
- */
-#define PCR_ECC_MEM_FORCE_PU    (BIT(1))
-#define PCR_ECC_MEM_FORCE_PU_M  (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S)
-#define PCR_ECC_MEM_FORCE_PU_V  0x00000001U
-#define PCR_ECC_MEM_FORCE_PU_S  1
-/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down ecc internal memory.
- */
-#define PCR_ECC_MEM_FORCE_PD    (BIT(2))
-#define PCR_ECC_MEM_FORCE_PD_M  (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S)
-#define PCR_ECC_MEM_FORCE_PD_V  0x00000001U
-#define PCR_ECC_MEM_FORCE_PD_S  2
-
-/** PCR_DS_CONF_REG register
- *  DS configuration register
- */
-#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc)
-/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ds clock
- */
-#define PCR_DS_CLK_EN    (BIT(0))
-#define PCR_DS_CLK_EN_M  (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
-#define PCR_DS_CLK_EN_V  0x00000001U
-#define PCR_DS_CLK_EN_S  0
-/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ds module
- */
-#define PCR_DS_RST_EN    (BIT(1))
-#define PCR_DS_RST_EN_M  (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
-#define PCR_DS_RST_EN_V  0x00000001U
-#define PCR_DS_RST_EN_S  1
-/** PCR_DS_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset ds module
- */
-#define PCR_DS_READY    (BIT(2))
-#define PCR_DS_READY_M  (PCR_DS_READY_V << PCR_DS_READY_S)
-#define PCR_DS_READY_V  0x00000001U
-#define PCR_DS_READY_S  2
-
-/** PCR_HMAC_CONF_REG register
- *  HMAC configuration register
- */
-#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0)
-/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable hmac clock
- */
-#define PCR_HMAC_CLK_EN    (BIT(0))
-#define PCR_HMAC_CLK_EN_M  (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
-#define PCR_HMAC_CLK_EN_V  0x00000001U
-#define PCR_HMAC_CLK_EN_S  0
-/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset hmac module
- */
-#define PCR_HMAC_RST_EN    (BIT(1))
-#define PCR_HMAC_RST_EN_M  (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
-#define PCR_HMAC_RST_EN_V  0x00000001U
-#define PCR_HMAC_RST_EN_S  1
-/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset hmac module
- */
-#define PCR_HMAC_READY    (BIT(2))
-#define PCR_HMAC_READY_M  (PCR_HMAC_READY_V << PCR_HMAC_READY_S)
-#define PCR_HMAC_READY_V  0x00000001U
-#define PCR_HMAC_READY_S  2
-
-/** PCR_ECDSA_CONF_REG register
- *  ECDSA configuration register
- */
-#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4)
-/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable ecdsa clock
- */
-#define PCR_ECDSA_CLK_EN    (BIT(0))
-#define PCR_ECDSA_CLK_EN_M  (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S)
-#define PCR_ECDSA_CLK_EN_V  0x00000001U
-#define PCR_ECDSA_CLK_EN_S  0
-/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset ecdsa module
- */
-#define PCR_ECDSA_RST_EN    (BIT(1))
-#define PCR_ECDSA_RST_EN_M  (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S)
-#define PCR_ECDSA_RST_EN_V  0x00000001U
-#define PCR_ECDSA_RST_EN_S  1
-/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset ecdsa module
- */
-#define PCR_ECDSA_READY    (BIT(2))
-#define PCR_ECDSA_READY_M  (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S)
-#define PCR_ECDSA_READY_V  0x00000001U
-#define PCR_ECDSA_READY_S  2
-
-/** PCR_IOMUX_CONF_REG register
- *  IOMUX configuration register
- */
-#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8)
-/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable iomux apb clock
- */
-#define PCR_IOMUX_CLK_EN    (BIT(0))
-#define PCR_IOMUX_CLK_EN_M  (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S)
-#define PCR_IOMUX_CLK_EN_V  0x00000001U
-#define PCR_IOMUX_CLK_EN_S  0
-/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset iomux module
- */
-#define PCR_IOMUX_RST_EN    (BIT(1))
-#define PCR_IOMUX_RST_EN_M  (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
-#define PCR_IOMUX_RST_EN_V  0x00000001U
-#define PCR_IOMUX_RST_EN_S  1
-
-/** PCR_IOMUX_CLK_CONF_REG register
- *  IOMUX_CLK configuration register
- */
-#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec)
-/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
- *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
- *  FOSC, 3(default): XTAL.
- */
-#define PCR_IOMUX_FUNC_CLK_SEL    0x00000003U
-#define PCR_IOMUX_FUNC_CLK_SEL_M  (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
-#define PCR_IOMUX_FUNC_CLK_SEL_V  0x00000003U
-#define PCR_IOMUX_FUNC_CLK_SEL_S  20
-/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set 1 to enable iomux function clock
- */
-#define PCR_IOMUX_FUNC_CLK_EN    (BIT(22))
-#define PCR_IOMUX_FUNC_CLK_EN_M  (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S)
-#define PCR_IOMUX_FUNC_CLK_EN_V  0x00000001U
-#define PCR_IOMUX_FUNC_CLK_EN_S  22
-
-/** PCR_MEM_MONITOR_CONF_REG register
- *  MEM_MONITOR configuration register
- */
-#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0)
-/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable mem_monitor clock
- */
-#define PCR_MEM_MONITOR_CLK_EN    (BIT(0))
-#define PCR_MEM_MONITOR_CLK_EN_M  (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S)
-#define PCR_MEM_MONITOR_CLK_EN_V  0x00000001U
-#define PCR_MEM_MONITOR_CLK_EN_S  0
-/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset mem_monitor module
- */
-#define PCR_MEM_MONITOR_RST_EN    (BIT(1))
-#define PCR_MEM_MONITOR_RST_EN_M  (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S)
-#define PCR_MEM_MONITOR_RST_EN_V  0x00000001U
-#define PCR_MEM_MONITOR_RST_EN_S  1
-/** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1;
- *  Query this field after reset mem_monitor module
- */
-#define PCR_MEM_MONITOR_READY    (BIT(2))
-#define PCR_MEM_MONITOR_READY_M  (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S)
-#define PCR_MEM_MONITOR_READY_V  0x00000001U
-#define PCR_MEM_MONITOR_READY_S  2
-
-/** PCR_REGDMA_CONF_REG register
- *  REGDMA configuration register
- */
-#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4)
-/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable regdma clock
- */
-#define PCR_REGDMA_CLK_EN    (BIT(0))
-#define PCR_REGDMA_CLK_EN_M  (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S)
-#define PCR_REGDMA_CLK_EN_V  0x00000001U
-#define PCR_REGDMA_CLK_EN_S  0
-/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset regdma module
- */
-#define PCR_REGDMA_RST_EN    (BIT(1))
-#define PCR_REGDMA_RST_EN_M  (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
-#define PCR_REGDMA_RST_EN_V  0x00000001U
-#define PCR_REGDMA_RST_EN_S  1
-
-/** PCR_TRACE_CONF_REG register
- *  TRACE configuration register
- */
-#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8)
-/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable trace clock
- */
-#define PCR_TRACE_CLK_EN    (BIT(0))
-#define PCR_TRACE_CLK_EN_M  (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S)
-#define PCR_TRACE_CLK_EN_V  0x00000001U
-#define PCR_TRACE_CLK_EN_S  0
-/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset trace module
- */
-#define PCR_TRACE_RST_EN    (BIT(1))
-#define PCR_TRACE_RST_EN_M  (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
-#define PCR_TRACE_RST_EN_V  0x00000001U
-#define PCR_TRACE_RST_EN_S  1
-
-/** PCR_ASSIST_CONF_REG register
- *  ASSIST configuration register
- */
-#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc)
-/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable assist clock
- */
-#define PCR_ASSIST_CLK_EN    (BIT(0))
-#define PCR_ASSIST_CLK_EN_M  (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S)
-#define PCR_ASSIST_CLK_EN_V  0x00000001U
-#define PCR_ASSIST_CLK_EN_S  0
-/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset assist module
- */
-#define PCR_ASSIST_RST_EN    (BIT(1))
-#define PCR_ASSIST_RST_EN_M  (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
-#define PCR_ASSIST_RST_EN_V  0x00000001U
-#define PCR_ASSIST_RST_EN_S  1
-
-/** PCR_CACHE_CONF_REG register
- *  CACHE configuration register
- */
-#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100)
-/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable cache clock
- */
-#define PCR_CACHE_CLK_EN    (BIT(0))
-#define PCR_CACHE_CLK_EN_M  (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S)
-#define PCR_CACHE_CLK_EN_V  0x00000001U
-#define PCR_CACHE_CLK_EN_S  0
-/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset cache module
- */
-#define PCR_CACHE_RST_EN    (BIT(1))
-#define PCR_CACHE_RST_EN_M  (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
-#define PCR_CACHE_RST_EN_V  0x00000001U
-#define PCR_CACHE_RST_EN_S  1
-
-/** PCR_MODEM_CONF_REG register
- *  MODEM_APB configuration register
- */
-#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104)
-/** PCR_MODEM_CLK_SEL : R/W; bitpos: [0]; default: 0;
- *  xxxx
- */
-#define PCR_MODEM_CLK_SEL    (BIT(0))
-#define PCR_MODEM_CLK_SEL_M  (PCR_MODEM_CLK_SEL_V << PCR_MODEM_CLK_SEL_S)
-#define PCR_MODEM_CLK_SEL_V  0x00000001U
-#define PCR_MODEM_CLK_SEL_S  0
-/** PCR_MODEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  xxxx
- */
-#define PCR_MODEM_CLK_EN    (BIT(1))
-#define PCR_MODEM_CLK_EN_M  (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S)
-#define PCR_MODEM_CLK_EN_V  0x00000001U
-#define PCR_MODEM_CLK_EN_S  1
-/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0;
- *  Set this file as 1 to reset modem-subsystem.
- */
-#define PCR_MODEM_RST_EN    (BIT(2))
-#define PCR_MODEM_RST_EN_M  (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S)
-#define PCR_MODEM_RST_EN_V  0x00000001U
-#define PCR_MODEM_RST_EN_S  2
-
-/** PCR_TIMEOUT_CONF_REG register
- *  TIMEOUT configuration register
- */
-#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108)
-/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
- *  Set 0 to reset cpu_peri timeout module
- */
-#define PCR_CPU_TIMEOUT_RST_EN    (BIT(1))
-#define PCR_CPU_TIMEOUT_RST_EN_M  (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
-#define PCR_CPU_TIMEOUT_RST_EN_V  0x00000001U
-#define PCR_CPU_TIMEOUT_RST_EN_S  1
-/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
- *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
- */
-#define PCR_HP_TIMEOUT_RST_EN    (BIT(2))
-#define PCR_HP_TIMEOUT_RST_EN_M  (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
-#define PCR_HP_TIMEOUT_RST_EN_V  0x00000001U
-#define PCR_HP_TIMEOUT_RST_EN_S  2
-
-/** PCR_SYSCLK_CONF_REG register
- *  SYSCLK configuration register
- */
-#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c)
-/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
- *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
- *  clock-source such as XTAL/FOSC.
- */
-#define PCR_LS_DIV_NUM    0x000000FFU
-#define PCR_LS_DIV_NUM_M  (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
-#define PCR_LS_DIV_NUM_V  0x000000FFU
-#define PCR_LS_DIV_NUM_S  0
-/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
- *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
- */
-#define PCR_HS_DIV_NUM    0x000000FFU
-#define PCR_HS_DIV_NUM_M  (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
-#define PCR_HS_DIV_NUM_V  0x000000FFU
-#define PCR_HS_DIV_NUM_S  8
-/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
- *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
- */
-#define PCR_SOC_CLK_SEL    0x00000003U
-#define PCR_SOC_CLK_SEL_M  (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
-#define PCR_SOC_CLK_SEL_V  0x00000003U
-#define PCR_SOC_CLK_SEL_S  16
-/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 32;
- *  This field indicates the frequency(MHz) of XTAL.
- */
-#define PCR_CLK_XTAL_FREQ    0x0000007FU
-#define PCR_CLK_XTAL_FREQ_M  (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S)
-#define PCR_CLK_XTAL_FREQ_V  0x0000007FU
-#define PCR_CLK_XTAL_FREQ_S  24
-
-/** PCR_CPU_WAITI_CONF_REG register
- *  CPU_WAITI configuration register
- */
-#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110)
-/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
- *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
- */
-#define PCR_CPUPERIOD_SEL    0x00000003U
-#define PCR_CPUPERIOD_SEL_M  (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
-#define PCR_CPUPERIOD_SEL_V  0x00000003U
-#define PCR_CPUPERIOD_SEL_S  0
-/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
- *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
- */
-#define PCR_PLL_FREQ_SEL    (BIT(2))
-#define PCR_PLL_FREQ_SEL_M  (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
-#define PCR_PLL_FREQ_SEL_V  0x00000001U
-#define PCR_PLL_FREQ_SEL_S  2
-/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
- *  Set 1 to force cpu_waiti_clk enable.
- */
-#define PCR_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
-#define PCR_CPU_WAIT_MODE_FORCE_ON_M  (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S)
-#define PCR_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
-#define PCR_CPU_WAIT_MODE_FORCE_ON_S  3
-/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
- *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
- *  will close
- */
-#define PCR_CPU_WAITI_DELAY_NUM    0x0000000FU
-#define PCR_CPU_WAITI_DELAY_NUM_M  (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S)
-#define PCR_CPU_WAITI_DELAY_NUM_V  0x0000000FU
-#define PCR_CPU_WAITI_DELAY_NUM_S  4
-
-/** PCR_CPU_FREQ_CONF_REG register
- *  CPU_FREQ configuration register
- */
-#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114)
-/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
- *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
- *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
- */
-#define PCR_CPU_DIV_NUM    0x000000FFU
-#define PCR_CPU_DIV_NUM_M  (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S)
-#define PCR_CPU_DIV_NUM_V  0x000000FFU
-#define PCR_CPU_DIV_NUM_S  0
-
-/** PCR_AHB_FREQ_CONF_REG register
- *  AHB_FREQ configuration register
- */
-#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
-/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
- *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
- *  low-speed clock-source such as XTAL/FOSC, and should be used together with
- *  PCR_CPU_DIV_NUM.
- */
-#define PCR_AHB_DIV_NUM    0x000000FFU
-#define PCR_AHB_DIV_NUM_M  (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S)
-#define PCR_AHB_DIV_NUM_V  0x000000FFU
-#define PCR_AHB_DIV_NUM_S  0
-
-/** PCR_APB_FREQ_CONF_REG register
- *  APB_FREQ configuration register
- */
-#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
-/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
- *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
- *  recover to the previous frequency when a new access appears on apb-bus. Set as one
- *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
- *  that enable this function will reduce performance. Users can set this field as zero
- *  to disable the auto-decrease-apb-freq function. By default, this function is
- *  disable.
- */
-#define PCR_APB_DECREASE_DIV_NUM    0x000000FFU
-#define PCR_APB_DECREASE_DIV_NUM_M  (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S)
-#define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
-#define PCR_APB_DECREASE_DIV_NUM_S  0
-/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
- *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
- *  div1(default)/div2/div4 of clk_ahb.
- */
-#define PCR_APB_DIV_NUM    0x000000FFU
-#define PCR_APB_DIV_NUM_M  (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S)
-#define PCR_APB_DIV_NUM_V  0x000000FFU
-#define PCR_APB_DIV_NUM_S  8
-
-/** PCR_SYSCLK_FREQ_QUERY_0_REG register
- *  SYSCLK frequency query 0 register
- */
-#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120)
-/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8;
- *  This field indicates the frequency(MHz) of FOSC.
- */
-#define PCR_FOSC_FREQ    0x000000FFU
-#define PCR_FOSC_FREQ_M  (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S)
-#define PCR_FOSC_FREQ_V  0x000000FFU
-#define PCR_FOSC_FREQ_S  0
-/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96;
- *  This field indicates the frequency(MHz) of SPLL.
- */
-#define PCR_PLL_FREQ    0x000003FFU
-#define PCR_PLL_FREQ_M  (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S)
-#define PCR_PLL_FREQ_V  0x000003FFU
-#define PCR_PLL_FREQ_S  8
-
-/** PCR_PLL_DIV_CLK_EN_REG register
- *  SPLL DIV clock-gating configuration register
- */
-#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124)
-/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1:
- *  open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_240M_CLK_EN    (BIT(0))
-#define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
-#define PCR_PLL_240M_CLK_EN_V  0x00000001U
-#define PCR_PLL_240M_CLK_EN_S  0
-/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_160M_CLK_EN    (BIT(1))
-#define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
-#define PCR_PLL_160M_CLK_EN_V  0x00000001U
-#define PCR_PLL_160M_CLK_EN_S  1
-/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_120M_CLK_EN    (BIT(2))
-#define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
-#define PCR_PLL_120M_CLK_EN_V  0x00000001U
-#define PCR_PLL_120M_CLK_EN_S  2
-/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  This field is used to open 32 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_80M_CLK_EN    (BIT(3))
-#define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
-#define PCR_PLL_80M_CLK_EN_V  0x00000001U
-#define PCR_PLL_80M_CLK_EN_S  3
-/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_48M_CLK_EN    (BIT(4))
-#define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
-#define PCR_PLL_48M_CLK_EN_V  0x00000001U
-#define PCR_PLL_48M_CLK_EN_S  4
-/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
- *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
- */
-#define PCR_PLL_40M_CLK_EN    (BIT(5))
-#define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
-#define PCR_PLL_40M_CLK_EN_V  0x00000001U
-#define PCR_PLL_40M_CLK_EN_S  5
-
-/** PCR_CTRL_CLK_OUT_EN_REG register
- *  CLK_OUT_EN configuration register
- */
-#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128)
-/** PCR_CLK8_OEN : R/W; bitpos: [0]; default: 1;
- *  Set 1 to enable 8m clock
- */
-#define PCR_CLK8_OEN    (BIT(0))
-#define PCR_CLK8_OEN_M  (PCR_CLK8_OEN_V << PCR_CLK8_OEN_S)
-#define PCR_CLK8_OEN_V  0x00000001U
-#define PCR_CLK8_OEN_S  0
-/** PCR_CLK16_OEN : R/W; bitpos: [1]; default: 1;
- *  Set 1 to enable 16m clock
- */
-#define PCR_CLK16_OEN    (BIT(1))
-#define PCR_CLK16_OEN_M  (PCR_CLK16_OEN_V << PCR_CLK16_OEN_S)
-#define PCR_CLK16_OEN_V  0x00000001U
-#define PCR_CLK16_OEN_S  1
-/** PCR_CLK32_OEN : R/W; bitpos: [2]; default: 1;
- *  Set 1 to enable 32m clock
- */
-#define PCR_CLK32_OEN    (BIT(2))
-#define PCR_CLK32_OEN_M  (PCR_CLK32_OEN_V << PCR_CLK32_OEN_S)
-#define PCR_CLK32_OEN_V  0x00000001U
-#define PCR_CLK32_OEN_S  2
-/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [3]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_ADC_INF_OEN    (BIT(3))
-#define PCR_CLK_ADC_INF_OEN_M  (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S)
-#define PCR_CLK_ADC_INF_OEN_V  0x00000001U
-#define PCR_CLK_ADC_INF_OEN_S  3
-/** PCR_CLK_DFM_INF_OEN : R/W; bitpos: [4]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_DFM_INF_OEN    (BIT(4))
-#define PCR_CLK_DFM_INF_OEN_M  (PCR_CLK_DFM_INF_OEN_V << PCR_CLK_DFM_INF_OEN_S)
-#define PCR_CLK_DFM_INF_OEN_V  0x00000001U
-#define PCR_CLK_DFM_INF_OEN_S  4
-/** PCR_CLK_SDM_MOD_OEN : R/W; bitpos: [5]; default: 1;
- *  Reserved
- */
-#define PCR_CLK_SDM_MOD_OEN    (BIT(5))
-#define PCR_CLK_SDM_MOD_OEN_M  (PCR_CLK_SDM_MOD_OEN_V << PCR_CLK_SDM_MOD_OEN_S)
-#define PCR_CLK_SDM_MOD_OEN_V  0x00000001U
-#define PCR_CLK_SDM_MOD_OEN_S  5
-/** PCR_CLK_XTAL_OEN : R/W; bitpos: [6]; default: 1;
- *  Set 1 to enable xtal clock
- */
-#define PCR_CLK_XTAL_OEN    (BIT(6))
-#define PCR_CLK_XTAL_OEN_M  (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S)
-#define PCR_CLK_XTAL_OEN_V  0x00000001U
-#define PCR_CLK_XTAL_OEN_S  6
-
-/** PCR_CTRL_TICK_CONF_REG register
- *  TICK configuration register
- */
-#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c)
-/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39;
- *  ******* Description ***********
- */
-#define PCR_XTAL_TICK_NUM    0x000000FFU
-#define PCR_XTAL_TICK_NUM_M  (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S)
-#define PCR_XTAL_TICK_NUM_V  0x000000FFU
-#define PCR_XTAL_TICK_NUM_S  0
-/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7;
- *  ******* Description ***********
- */
-#define PCR_FOSC_TICK_NUM    0x000000FFU
-#define PCR_FOSC_TICK_NUM_M  (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S)
-#define PCR_FOSC_TICK_NUM_V  0x000000FFU
-#define PCR_FOSC_TICK_NUM_S  8
-/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1;
- *  ******* Description ***********
- */
-#define PCR_TICK_ENABLE    (BIT(16))
-#define PCR_TICK_ENABLE_M  (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S)
-#define PCR_TICK_ENABLE_V  0x00000001U
-#define PCR_TICK_ENABLE_S  16
-/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0;
- *  ******* Description ***********
- */
-#define PCR_RST_TICK_CNT    (BIT(17))
-#define PCR_RST_TICK_CNT_M  (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S)
-#define PCR_RST_TICK_CNT_V  0x00000001U
-#define PCR_RST_TICK_CNT_S  17
-
-/** PCR_CTRL_32K_CONF_REG register
- *  32KHz clock configuration register
- */
-#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130)
-/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0;
- *  This field indicates which one 32KHz clock will be used by timergroup. 0:
- *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
- */
-#define PCR_32K_SEL    0x00000003U
-#define PCR_32K_SEL_M  (PCR_32K_SEL_V << PCR_32K_SEL_S)
-#define PCR_32K_SEL_V  0x00000003U
-#define PCR_32K_SEL_S  0
-/** PCR_32K_MODEM_SEL : R/W; bitpos: [3:2]; default: 0;
- *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0:
- *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
- */
-#define PCR_32K_MODEM_SEL    0x00000003U
-#define PCR_32K_MODEM_SEL_M  (PCR_32K_MODEM_SEL_V << PCR_32K_MODEM_SEL_S)
-#define PCR_32K_MODEM_SEL_V  0x00000003U
-#define PCR_32K_MODEM_SEL_S  2
-
-/** PCR_SRAM_POWER_CONF_0_REG register
- *  HP SRAM/ROM configuration register
- */
-#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134)
-/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:13]; default: 3;
- *  Set this bit to force power up ROM
- */
-#define PCR_ROM_FORCE_PU    0x00000003U
-#define PCR_ROM_FORCE_PU_M  (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S)
-#define PCR_ROM_FORCE_PU_V  0x00000003U
-#define PCR_ROM_FORCE_PU_S  13
-/** PCR_ROM_FORCE_PD : R/W; bitpos: [16:15]; default: 0;
- *  Set this bit to force power down ROM.
- */
-#define PCR_ROM_FORCE_PD    0x00000003U
-#define PCR_ROM_FORCE_PD_M  (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S)
-#define PCR_ROM_FORCE_PD_V  0x00000003U
-#define PCR_ROM_FORCE_PD_S  15
-/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [18:17]; default: 0;
- *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
- *  gate-clock will be used when accessing the ROM.
- */
-#define PCR_ROM_CLKGATE_FORCE_ON    0x00000003U
-#define PCR_ROM_CLKGATE_FORCE_ON_M  (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S)
-#define PCR_ROM_CLKGATE_FORCE_ON_V  0x00000003U
-#define PCR_ROM_CLKGATE_FORCE_ON_S  17
-
-/** PCR_SRAM_POWER_CONF_1_REG register
- *  HP SRAM/ROM configuration register
- */
-#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138)
-/** PCR_SRAM_FORCE_PU : R/W; bitpos: [4:0]; default: 31;
- *  Set this bit to force power up SRAM
- */
-#define PCR_SRAM_FORCE_PU    0x0000001FU
-#define PCR_SRAM_FORCE_PU_M  (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S)
-#define PCR_SRAM_FORCE_PU_V  0x0000001FU
-#define PCR_SRAM_FORCE_PU_S  0
-/** PCR_SRAM_FORCE_PD : R/W; bitpos: [14:10]; default: 0;
- *  Set this bit to force power down SRAM.
- */
-#define PCR_SRAM_FORCE_PD    0x0000001FU
-#define PCR_SRAM_FORCE_PD_M  (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S)
-#define PCR_SRAM_FORCE_PD_V  0x0000001FU
-#define PCR_SRAM_FORCE_PD_S  10
-/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [29:25]; default: 0;
- *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
- *  gate-clock will be used when accessing the SRAM.
- */
-#define PCR_SRAM_CLKGATE_FORCE_ON    0x0000001FU
-#define PCR_SRAM_CLKGATE_FORCE_ON_M  (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S)
-#define PCR_SRAM_CLKGATE_FORCE_ON_V  0x0000001FU
-#define PCR_SRAM_CLKGATE_FORCE_ON_S  25
-
-/** PCR_SEC_CONF_REG register
- *  xxxx
- */
-#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c)
-/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
- *  xxxx
- */
-#define PCR_SEC_CLK_SEL    0x00000003U
-#define PCR_SEC_CLK_SEL_M  (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S)
-#define PCR_SEC_CLK_SEL_V  0x00000003U
-#define PCR_SEC_CLK_SEL_S  0
-
-/** PCR_ADC_INV_PHASE_CONF_REG register
- *  xxxx
- */
-#define PCR_ADC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140)
-/** PCR_CLK_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0;
- *  xxxx
- */
-#define PCR_CLK_ADC_INV_PHASE_ENA    (BIT(0))
-#define PCR_CLK_ADC_INV_PHASE_ENA_M  (PCR_CLK_ADC_INV_PHASE_ENA_V << PCR_CLK_ADC_INV_PHASE_ENA_S)
-#define PCR_CLK_ADC_INV_PHASE_ENA_V  0x00000001U
-#define PCR_CLK_ADC_INV_PHASE_ENA_S  0
-
-/** PCR_SDM_INV_PHASE_CONF_REG register
- *  xxxx
- */
-#define PCR_SDM_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x144)
-/** PCR_CLK_SDM_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0;
- *  xxxx
- */
-#define PCR_CLK_SDM_INV_PHASE_ENA    (BIT(0))
-#define PCR_CLK_SDM_INV_PHASE_ENA_M  (PCR_CLK_SDM_INV_PHASE_ENA_V << PCR_CLK_SDM_INV_PHASE_ENA_S)
-#define PCR_CLK_SDM_INV_PHASE_ENA_V  0x00000001U
-#define PCR_CLK_SDM_INV_PHASE_ENA_S  0
-/** PCR_CLK_SDM_INV_PHASE_SEL : R/W; bitpos: [3:1]; default: 0;
- *  xxxx
- */
-#define PCR_CLK_SDM_INV_PHASE_SEL    0x00000007U
-#define PCR_CLK_SDM_INV_PHASE_SEL_M  (PCR_CLK_SDM_INV_PHASE_SEL_V << PCR_CLK_SDM_INV_PHASE_SEL_S)
-#define PCR_CLK_SDM_INV_PHASE_SEL_V  0x00000007U
-#define PCR_CLK_SDM_INV_PHASE_SEL_S  1
-
-/** PCR_BUS_CLK_UPDATE_REG register
- *  xxxx
- */
-#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148)
-/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0;
- *  xxxx
- */
-#define PCR_BUS_CLOCK_UPDATE    (BIT(0))
-#define PCR_BUS_CLOCK_UPDATE_M  (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S)
-#define PCR_BUS_CLOCK_UPDATE_V  0x00000001U
-#define PCR_BUS_CLOCK_UPDATE_S  0
-
-/** PCR_SAR_CLK_DIV_REG register
- *  xxxx
- */
-#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c)
-/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
- *  xxxx
- */
-#define PCR_SAR2_CLK_DIV_NUM    0x000000FFU
-#define PCR_SAR2_CLK_DIV_NUM_M  (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S)
-#define PCR_SAR2_CLK_DIV_NUM_V  0x000000FFU
-#define PCR_SAR2_CLK_DIV_NUM_S  0
-/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
- *  xxxx
- */
-#define PCR_SAR1_CLK_DIV_NUM    0x000000FFU
-#define PCR_SAR1_CLK_DIV_NUM_M  (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S)
-#define PCR_SAR1_CLK_DIV_NUM_V  0x000000FFU
-#define PCR_SAR1_CLK_DIV_NUM_S  8
-
-/** PCR_PWDET_SAR_CLK_CONF_REG register
- *  xxxx
- */
-#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150)
-/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7;
- *  xxxx
- */
-#define PCR_PWDET_SAR_CLK_DIV_NUM    0x000000FFU
-#define PCR_PWDET_SAR_CLK_DIV_NUM_M  (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S)
-#define PCR_PWDET_SAR_CLK_DIV_NUM_V  0x000000FFU
-#define PCR_PWDET_SAR_CLK_DIV_NUM_S  0
-/** PCR_PWDET_SAR_READER_EN : R/W; bitpos: [8]; default: 1;
- *  xxxx
- */
-#define PCR_PWDET_SAR_READER_EN    (BIT(8))
-#define PCR_PWDET_SAR_READER_EN_M  (PCR_PWDET_SAR_READER_EN_V << PCR_PWDET_SAR_READER_EN_S)
-#define PCR_PWDET_SAR_READER_EN_V  0x00000001U
-#define PCR_PWDET_SAR_READER_EN_S  8
-
-/** PCR_RESET_EVENT_BYPASS_REG register
- *  reset event bypass backdoor configuration register
- */
-#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0)
-/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0;
- *  This field is used to control reset event relationship for
- *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
- *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
- *  will not only be reset by power-reset, but also some reset event.
- */
-#define PCR_RESET_EVENT_BYPASS_APM    (BIT(0))
-#define PCR_RESET_EVENT_BYPASS_APM_M  (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S)
-#define PCR_RESET_EVENT_BYPASS_APM_V  0x00000001U
-#define PCR_RESET_EVENT_BYPASS_APM_S  0
-/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1;
- *  This field is used to control reset event relationship for system-bus. 1: system
- *  bus (including arbiter/router) will only be reset by power-reset. some reset event
- *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
- *  power-reset, but also some reset event.
- */
-#define PCR_RESET_EVENT_BYPASS    (BIT(1))
-#define PCR_RESET_EVENT_BYPASS_M  (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S)
-#define PCR_RESET_EVENT_BYPASS_V  0x00000001U
-#define PCR_RESET_EVENT_BYPASS_S  1
-
-/** PCR_FPGA_DEBUG_REG register
- *  fpga debug register
- */
-#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
-/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
- *  Only used in fpga debug.
- */
-#define PCR_FPGA_DEBUG    0xFFFFFFFFU
-#define PCR_FPGA_DEBUG_M  (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
-#define PCR_FPGA_DEBUG_V  0xFFFFFFFFU
-#define PCR_FPGA_DEBUG_S  0
-
-/** PCR_CLOCK_GATE_REG register
- *  PCR clock gating configure register
- */
-#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
-/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to force on clock gating.
- */
-#define PCR_CLK_EN    (BIT(0))
-#define PCR_CLK_EN_M  (PCR_CLK_EN_V << PCR_CLK_EN_S)
-#define PCR_CLK_EN_V  0x00000001U
-#define PCR_CLK_EN_S  0
-
-/** PCR_DATE_REG register
- *  Date register.
- */
-#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
-/** PCR_DATE : R/W; bitpos: [27:0]; default: 35717248;
- *  PCR version information.
- */
-#define PCR_DATE    0x0FFFFFFFU
-#define PCR_DATE_M  (PCR_DATE_V << PCR_DATE_S)
-#define PCR_DATE_V  0x0FFFFFFFU
-#define PCR_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/pcr_struct.h b/components/soc/esp32h2/include/soc/pcr_struct.h
deleted file mode 100644
index 31e49c232cc..00000000000
--- a/components/soc/esp32h2/include/soc/pcr_struct.h
+++ /dev/null
@@ -1,2093 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Configuration Register */
-/** Type of uart0_conf register
- *  UART0 configuration register
- */
-typedef union {
-    struct {
-        /** uart0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uart0 apb clock
-         */
-        uint32_t uart0_clk_en:1;
-        /** uart0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uart0 module
-         */
-        uint32_t uart0_rst_en:1;
-        /** uart0_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset uart0 module
-         */
-        uint32_t uart0_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart0_conf_reg_t;
-
-/** Type of uart0_sclk_conf register
- *  UART0_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_a:6;
-        /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_b:6;
-        /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the uart0 function clock.
-         */
-        uint32_t uart0_sclk_div_num:8;
-        /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
-         *  FOSC, 3(default): XTAL.
-         */
-        uint32_t uart0_sclk_sel:2;
-        /** uart0_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable uart0 function clock
-         */
-        uint32_t uart0_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_uart0_sclk_conf_reg_t;
-
-/** Type of uart0_pd_ctrl register
- *  UART0 power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power down UART0 memory.
-         */
-        uint32_t uart0_mem_force_pu:1;
-        /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power up UART0 memory.
-         */
-        uint32_t uart0_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart0_pd_ctrl_reg_t;
-
-/** Type of uart1_conf register
- *  UART1 configuration register
- */
-typedef union {
-    struct {
-        /** uart1_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uart1 apb clock
-         */
-        uint32_t uart1_clk_en:1;
-        /** uart1_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uart1 module
-         */
-        uint32_t uart1_rst_en:1;
-        /** uart1_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset uart1 module
-         */
-        uint32_t uart1_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart1_conf_reg_t;
-
-/** Type of uart1_sclk_conf register
- *  UART1_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_a:6;
-        /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_b:6;
-        /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the uart1 function clock.
-         */
-        uint32_t uart1_sclk_div_num:8;
-        /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
-         *  FOSC, 3(default): XTAL.
-         */
-        uint32_t uart1_sclk_sel:2;
-        /** uart1_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable uart0 function clock
-         */
-        uint32_t uart1_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_uart1_sclk_conf_reg_t;
-
-/** Type of uart1_pd_ctrl register
- *  UART1 power control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power down UART1 memory.
-         */
-        uint32_t uart1_mem_force_pu:1;
-        /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power up UART1 memory.
-         */
-        uint32_t uart1_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uart1_pd_ctrl_reg_t;
-
-/** Type of mspi_conf register
- *  MSPI configuration register
- */
-typedef union {
-    struct {
-        /** mspi_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable mspi clock, include mspi pll clock
-         */
-        uint32_t mspi_clk_en:1;
-        /** mspi_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset mspi module
-         */
-        uint32_t mspi_rst_en:1;
-        /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable mspi pll clock
-         */
-        uint32_t mspi_pll_clk_en:1;
-        /** mspi_clk_sel : R/W; bitpos: [4:3]; default: 0;
-         *  set this field to select clock-source.
-         */
-        uint32_t mspi_clk_sel:2;
-        /** mspi_ready : RO; bitpos: [5]; default: 1;
-         *  Query this field after reset mspi module
-         */
-        uint32_t mspi_ready:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} pcr_mspi_conf_reg_t;
-
-/** Type of mspi_clk_conf register
- *  MSPI_CLK configuration register
- */
-typedef union {
-    struct {
-        /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
-         *  clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a
-         *  low-speed clock-source such as XTAL/FOSC.
-         */
-        uint32_t mspi_fast_div_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} pcr_mspi_clk_conf_reg_t;
-
-/** Type of i2c_conf register
- *  I2C configuration register
- */
-typedef union {
-    struct {
-        /** i2c_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable i2c apb clock
-         */
-        uint32_t i2c_clk_en:1;
-        /** i2c_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset i2c module
-         */
-        uint32_t i2c_rst_en:1;
-        /** i2c_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset i2c module
-         */
-        uint32_t i2c_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_i2c_conf_reg_t;
-
-/** Type of i2c_sclk_conf register
- *  I2C_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_a:6;
-        /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_b:6;
-        /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
-         *  The integral part of the frequency divider factor of the i2c function clock.
-         */
-        uint32_t i2c_sclk_div_num:8;
-        /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t i2c_sclk_sel:1;
-        uint32_t reserved_21:1;
-        /** i2c_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2c function clock
-         */
-        uint32_t i2c_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_i2c_sclk_conf_reg_t;
-
-/** Type of uhci_conf register
- *  UHCI configuration register
- */
-typedef union {
-    struct {
-        /** uhci_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable uhci clock
-         */
-        uint32_t uhci_clk_en:1;
-        /** uhci_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset uhci module
-         */
-        uint32_t uhci_rst_en:1;
-        /** uhci_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset uhci module
-         */
-        uint32_t uhci_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_uhci_conf_reg_t;
-
-/** Type of rmt_conf register
- *  RMT configuration register
- */
-typedef union {
-    struct {
-        /** rmt_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable rmt apb clock
-         */
-        uint32_t rmt_clk_en:1;
-        /** rmt_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset rmt module
-         */
-        uint32_t rmt_rst_en:1;
-        /** rmt_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset rmt module
-         */
-        uint32_t rmt_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_rmt_conf_reg_t;
-
-/** Type of rmt_sclk_conf register
- *  RMT_SCLK configuration register
- */
-typedef union {
-    struct {
-        /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_a:6;
-        /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_b:6;
-        /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor of the rmt function clock.
-         */
-        uint32_t rmt_sclk_div_num:8;
-        /** rmt_sclk_sel : R/W; bitpos: [20]; default: 1;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
-         *  80MHz, 2: FOSC, 3: XTAL.
-         */
-        uint32_t rmt_sclk_sel:1;
-        /** rmt_sclk_en : R/W; bitpos: [21]; default: 1;
-         *  Set 1 to enable rmt function clock
-         */
-        uint32_t rmt_sclk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} pcr_rmt_sclk_conf_reg_t;
-
-/** Type of ledc_conf register
- *  LEDC configuration register
- */
-typedef union {
-    struct {
-        /** ledc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ledc apb clock
-         */
-        uint32_t ledc_clk_en:1;
-        /** ledc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ledc module
-         */
-        uint32_t ledc_rst_en:1;
-        /** ledc_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset ledc module
-         */
-        uint32_t ledc_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ledc_conf_reg_t;
-
-/** Type of ledc_sclk_conf register
- *  LEDC_SCLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
-         *  80MHz, 2: FOSC, 3: XTAL.
-         */
-        uint32_t ledc_sclk_sel:2;
-        /** ledc_sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable ledc function clock
-         */
-        uint32_t ledc_sclk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_ledc_sclk_conf_reg_t;
-
-/** Type of timergroup0_conf register
- *  TIMERGROUP0 configuration register
- */
-typedef union {
-    struct {
-        /** tg0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable timer_group0 apb clock
-         */
-        uint32_t tg0_clk_en:1;
-        /** tg0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset timer_group0 module
-         */
-        uint32_t tg0_rst_en:1;
-        /** tg0_wdt_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset timer_group0 wdt module
-         */
-        uint32_t tg0_wdt_ready:1;
-        /** tg0_timer0_ready : RO; bitpos: [3]; default: 1;
-         *  Query this field after reset timer_group0 timer0 module
-         */
-        uint32_t tg0_timer0_ready:1;
-        /** tg0_timer1_ready : RO; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t tg0_timer1_ready:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} pcr_timergroup0_conf_reg_t;
-
-/** Type of timergroup0_timer_clk_conf register
- *  TIMERGROUP0_TIMER_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg0_timer_clk_sel:2;
-        /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 timer clock
-         */
-        uint32_t tg0_timer_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup0_timer_clk_conf_reg_t;
-
-/** Type of timergroup0_wdt_clk_conf register
- *  TIMERGROUP0_WDT_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg0_wdt_clk_sel:2;
-        /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 wdt clock
-         */
-        uint32_t tg0_wdt_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup0_wdt_clk_conf_reg_t;
-
-/** Type of timergroup1_conf register
- *  TIMERGROUP1 configuration register
- */
-typedef union {
-    struct {
-        /** tg1_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable timer_group1 apb clock
-         */
-        uint32_t tg1_clk_en:1;
-        /** tg1_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset timer_group1 module
-         */
-        uint32_t tg1_rst_en:1;
-        /** tg1_wdt_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset timer_group1 wdt module
-         */
-        uint32_t tg1_wdt_ready:1;
-        /** tg1_timer0_ready : RO; bitpos: [3]; default: 1;
-         *  Query this field after reset timer_group1 timer0 module
-         */
-        uint32_t tg1_timer0_ready:1;
-        /** tg1_timer1_ready : RO; bitpos: [4]; default: 1;
-         *  reserved
-         */
-        uint32_t tg1_timer1_ready:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} pcr_timergroup1_conf_reg_t;
-
-/** Type of timergroup1_timer_clk_conf register
- *  TIMERGROUP1_TIMER_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg1_timer_clk_sel:2;
-        /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group1 timer clock
-         */
-        uint32_t tg1_timer_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup1_timer_clk_conf_reg_t;
-
-/** Type of timergroup1_wdt_clk_conf register
- *  TIMERGROUP1_WDT_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t tg1_wdt_clk_sel:2;
-        /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable timer_group0 wdt clock
-         */
-        uint32_t tg1_wdt_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_timergroup1_wdt_clk_conf_reg_t;
-
-/** Type of systimer_conf register
- *  SYSTIMER configuration register
- */
-typedef union {
-    struct {
-        /** systimer_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable systimer apb clock
-         */
-        uint32_t systimer_clk_en:1;
-        /** systimer_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset systimer module
-         */
-        uint32_t systimer_rst_en:1;
-        /** systimer_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset systimer module
-         */
-        uint32_t systimer_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_systimer_conf_reg_t;
-
-/** Type of systimer_func_clk_conf register
- *  SYSTIMER_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t systimer_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable systimer function clock
-         */
-        uint32_t systimer_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_systimer_func_clk_conf_reg_t;
-
-/** Type of twai0_conf register
- *  TWAI0 configuration register
- */
-typedef union {
-    struct {
-        /** twai0_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable twai0 apb clock
-         */
-        uint32_t twai0_clk_en:1;
-        /** twai0_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset twai0 module
-         */
-        uint32_t twai0_rst_en:1;
-        /** twai0_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset twai0 module
-         */
-        uint32_t twai0_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_twai0_conf_reg_t;
-
-/** Type of twai0_func_clk_conf register
- *  TWAI0_FUNC_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
-         */
-        uint32_t twai0_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable twai0 function clock
-         */
-        uint32_t twai0_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_twai0_func_clk_conf_reg_t;
-
-/** Type of i2s_conf register
- *  I2S configuration register
- */
-typedef union {
-    struct {
-        /** i2s_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable i2s apb clock
-         */
-        uint32_t i2s_clk_en:1;
-        /** i2s_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset i2s module
-         */
-        uint32_t i2s_rst_en:1;
-        /** i2s_rx_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field before using i2s rx function, after reset i2s module
-         */
-        uint32_t i2s_rx_ready:1;
-        /** i2s_tx_ready : RO; bitpos: [3]; default: 1;
-         *  Query this field before using i2s tx function, after reset i2s module
-         */
-        uint32_t i2s_tx_ready:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_i2s_conf_reg_t;
-
-/** Type of i2s_tx_clkm_conf register
- *  I2S_TX_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
-         *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
-         *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
-         *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
-         *  (n+1)-div] + y * (n+1)-div.
-         */
-        uint32_t i2s_tx_clkm_div_num:8;
-        /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
-         *  I2S_MCLK_in.
-         */
-        uint32_t i2s_tx_clkm_sel:2;
-        /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2s_tx function clock
-         */
-        uint32_t i2s_tx_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_i2s_tx_clkm_conf_reg_t;
-
-/** Type of i2s_tx_clkm_div_conf register
- *  I2S_TX_CLKM_DIV configuration register
- */
-typedef union {
-    struct {
-        /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_Z is (a-b).
-         */
-        uint32_t i2s_tx_clkm_div_z:9;
-        /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
-         */
-        uint32_t i2s_tx_clkm_div_y:9;
-        /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
-         *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
-         */
-        uint32_t i2s_tx_clkm_div_x:9;
-        /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
-         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-         *  I2S_TX_CLKM_DIV_YN1 is 1.
-         */
-        uint32_t i2s_tx_clkm_div_yn1:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_i2s_tx_clkm_div_conf_reg_t;
-
-/** Type of i2s_rx_clkm_conf register
- *  I2S_RX_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
-         *  Integral I2S clock divider value
-         */
-        uint32_t i2s_rx_clkm_div_num:8;
-        /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
-         */
-        uint32_t i2s_rx_clkm_sel:2;
-        /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable i2s_rx function clock
-         */
-        uint32_t i2s_rx_clkm_en:1;
-        /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0;
-         *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
-         */
-        uint32_t i2s_mclk_sel:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} pcr_i2s_rx_clkm_conf_reg_t;
-
-/** Type of i2s_rx_clkm_div_conf register
- *  I2S_RX_CLKM_DIV configuration register
- */
-typedef union {
-    struct {
-        /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_Z is (a-b).
-         */
-        uint32_t i2s_rx_clkm_div_z:9;
-        /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
-         */
-        uint32_t i2s_rx_clkm_div_y:9;
-        /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
-         *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
-         */
-        uint32_t i2s_rx_clkm_div_x:9;
-        /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
-         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-         *  I2S_RX_CLKM_DIV_YN1 is 1.
-         */
-        uint32_t i2s_rx_clkm_div_yn1:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_i2s_rx_clkm_div_conf_reg_t;
-
-/** Type of saradc_conf register
- *  SARADC configuration register
- */
-typedef union {
-    struct {
-        /** saradc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  no use
-         */
-        uint32_t saradc_clk_en:1;
-        /** saradc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset function_register of saradc module
-         */
-        uint32_t saradc_rst_en:1;
-        /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable saradc apb clock
-         */
-        uint32_t saradc_reg_clk_en:1;
-        /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0;
-         *  Set 0 to reset apb_register of saradc module
-         */
-        uint32_t saradc_reg_rst_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_saradc_conf_reg_t;
-
-/** Type of saradc_clkm_conf register
- *  SARADC_CLKM configuration register
- */
-typedef union {
-    struct {
-        /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_a:6;
-        /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_b:6;
-        /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4;
-         *  The integral part of the frequency divider factor of the saradc function clock.
-         */
-        uint32_t saradc_clkm_div_num:8;
-        /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t saradc_clkm_sel:2;
-        /** saradc_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable saradc function clock
-         */
-        uint32_t saradc_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_saradc_clkm_conf_reg_t;
-
-/** Type of tsens_clk_conf register
- *  TSENS_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** tsens_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
-         */
-        uint32_t tsens_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** tsens_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable tsens clock
-         */
-        uint32_t tsens_clk_en:1;
-        /** tsens_rst_en : R/W; bitpos: [23]; default: 0;
-         *  Set 0 to reset tsens module
-         */
-        uint32_t tsens_rst_en:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} pcr_tsens_clk_conf_reg_t;
-
-/** Type of usb_device_conf register
- *  USB_DEVICE configuration register
- */
-typedef union {
-    struct {
-        /** usb_device_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable usb_device clock
-         */
-        uint32_t usb_device_clk_en:1;
-        /** usb_device_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset usb_device module
-         */
-        uint32_t usb_device_rst_en:1;
-        /** usb_device_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset usb_device module
-         */
-        uint32_t usb_device_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_usb_device_conf_reg_t;
-
-/** Type of intmtx_conf register
- *  INTMTX configuration register
- */
-typedef union {
-    struct {
-        /** intmtx_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable intmtx clock
-         */
-        uint32_t intmtx_clk_en:1;
-        /** intmtx_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset intmtx module
-         */
-        uint32_t intmtx_rst_en:1;
-        /** intmtx_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset intmtx module
-         */
-        uint32_t intmtx_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_intmtx_conf_reg_t;
-
-/** Type of pcnt_conf register
- *  PCNT configuration register
- */
-typedef union {
-    struct {
-        /** pcnt_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable pcnt clock
-         */
-        uint32_t pcnt_clk_en:1;
-        /** pcnt_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset pcnt module
-         */
-        uint32_t pcnt_rst_en:1;
-        /** pcnt_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset pcnt module
-         */
-        uint32_t pcnt_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_pcnt_conf_reg_t;
-
-/** Type of etm_conf register
- *  ETM configuration register
- */
-typedef union {
-    struct {
-        /** etm_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable etm clock
-         */
-        uint32_t etm_clk_en:1;
-        /** etm_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset etm module
-         */
-        uint32_t etm_rst_en:1;
-        /** etm_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset etm module
-         */
-        uint32_t etm_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_etm_conf_reg_t;
-
-/** Type of pwm_conf register
- *  PWM configuration register
- */
-typedef union {
-    struct {
-        /** pwm_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable pwm clock
-         */
-        uint32_t pwm_clk_en:1;
-        /** pwm_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset pwm module
-         */
-        uint32_t pwm_rst_en:1;
-        /** pwm_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset pwm module
-         */
-        uint32_t pwm_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_pwm_conf_reg_t;
-
-/** Type of pwm_clk_conf register
- *  PWM_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** pwm_div_num : R/W; bitpos: [19:12]; default: 4;
-         *  The integral part of the frequency divider factor of the pwm function clock.
-         */
-        uint32_t pwm_div_num:8;
-        /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
-         *  160MHz, 2: XTAL, 3: FOSC.
-         */
-        uint32_t pwm_clkm_sel:2;
-        /** pwm_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  set this field as 1 to activate pwm clkm.
-         */
-        uint32_t pwm_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_pwm_clk_conf_reg_t;
-
-/** Type of parl_io_conf register
- *  PARL_IO configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable parl apb clock
-         */
-        uint32_t parl_clk_en:1;
-        /** parl_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset parl apb reg
-         */
-        uint32_t parl_rst_en:1;
-        /** parl_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset parl module
-         */
-        uint32_t parl_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_parl_io_conf_reg_t;
-
-/** Type of parl_clk_rx_conf register
- *  PARL_CLK_RX configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0;
-         *  The integral part of the frequency divider factor of the parl rx clock.
-         */
-        uint32_t parl_clk_rx_div_num:16;
-        /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
-         *  user clock from pad.
-         */
-        uint32_t parl_clk_rx_sel:2;
-        /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1;
-         *  Set 1 to enable parl rx clock
-         */
-        uint32_t parl_clk_rx_en:1;
-        /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0;
-         *  Set 0 to reset parl rx module
-         */
-        uint32_t parl_rx_rst_en:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} pcr_parl_clk_rx_conf_reg_t;
-
-/** Type of parl_clk_tx_conf register
- *  PARL_CLK_TX configuration register
- */
-typedef union {
-    struct {
-        /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0;
-         *  The integral part of the frequency divider factor of the parl tx clock.
-         */
-        uint32_t parl_clk_tx_div_num:16;
-        /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
-         *  user clock from pad.
-         */
-        uint32_t parl_clk_tx_sel:2;
-        /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1;
-         *  Set 1 to enable parl tx clock
-         */
-        uint32_t parl_clk_tx_en:1;
-        /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0;
-         *  Set 0 to reset parl tx module
-         */
-        uint32_t parl_tx_rst_en:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} pcr_parl_clk_tx_conf_reg_t;
-
-/** Type of pvt_monitor_conf register
- *  PVT_MONITOR configuration register
- */
-typedef union {
-    struct {
-        /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable apb clock of pvt module
-         */
-        uint32_t pvt_monitor_clk_en:1;
-        /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset all pvt monitor module
-         */
-        uint32_t pvt_monitor_rst_en:1;
-        /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable function clock of modem pvt module
-         */
-        uint32_t pvt_monitor_site1_clk_en:1;
-        /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1;
-         *  Set 1 to enable function clock of cpu pvt module
-         */
-        uint32_t pvt_monitor_site2_clk_en:1;
-        /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1;
-         *  Set 1 to enable function clock of hp_peri pvt module
-         */
-        uint32_t pvt_monitor_site3_clk_en:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} pcr_pvt_monitor_conf_reg_t;
-
-/** Type of pvt_monitor_func_clk_conf register
- *  PVT_MONITOR function clock configuration register
- */
-typedef union {
-    struct {
-        /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0;
-         *  The integral part of the frequency divider factor of the pvt_monitor function clock.
-         */
-        uint32_t pvt_monitor_func_clk_div_num:4;
-        uint32_t reserved_4:16;
-        /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
-         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL
-         *  divided by 3.
-         */
-        uint32_t pvt_monitor_func_clk_sel:1;
-        uint32_t reserved_21:1;
-        /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable source clock of pvt sitex
-         */
-        uint32_t pvt_monitor_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_pvt_monitor_func_clk_conf_reg_t;
-
-/** Type of gdma_conf register
- *  GDMA configuration register
- */
-typedef union {
-    struct {
-        /** gdma_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable gdma clock
-         */
-        uint32_t gdma_clk_en:1;
-        /** gdma_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset gdma module
-         */
-        uint32_t gdma_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_gdma_conf_reg_t;
-
-/** Type of spi2_conf register
- *  SPI2 configuration register
- */
-typedef union {
-    struct {
-        /** spi2_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable spi2 apb clock
-         */
-        uint32_t spi2_clk_en:1;
-        /** spi2_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset spi2 module
-         */
-        uint32_t spi2_rst_en:1;
-        /** spi2_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset spi2 module
-         */
-        uint32_t spi2_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_spi2_conf_reg_t;
-
-/** Type of spi2_clkm_conf register
- *  SPI2_CLKM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0(default): XTAL, 1: 48MHz, 2: FOSC, 3:
-         *  reserved.
-         */
-        uint32_t spi2_clkm_sel:2;
-        /** spi2_clkm_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable spi2 function clock
-         */
-        uint32_t spi2_clkm_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_spi2_clkm_conf_reg_t;
-
-/** Type of aes_conf register
- *  AES configuration register
- */
-typedef union {
-    struct {
-        /** aes_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable aes clock
-         */
-        uint32_t aes_clk_en:1;
-        /** aes_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset aes module
-         */
-        uint32_t aes_rst_en:1;
-        /** aes_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset aes module
-         */
-        uint32_t aes_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_aes_conf_reg_t;
-
-/** Type of sha_conf register
- *  SHA configuration register
- */
-typedef union {
-    struct {
-        /** sha_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable sha clock
-         */
-        uint32_t sha_clk_en:1;
-        /** sha_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset sha module
-         */
-        uint32_t sha_rst_en:1;
-        /** sha_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset sha module
-         */
-        uint32_t sha_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_sha_conf_reg_t;
-
-/** Type of rsa_conf register
- *  RSA configuration register
- */
-typedef union {
-    struct {
-        /** rsa_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable rsa clock
-         */
-        uint32_t rsa_clk_en:1;
-        /** rsa_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset rsa module
-         */
-        uint32_t rsa_rst_en:1;
-        /** rsa_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset rsa module
-         */
-        uint32_t rsa_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_rsa_conf_reg_t;
-
-/** Type of rsa_pd_ctrl register
- *  RSA power control register
- */
-typedef union {
-    struct {
-        /** rsa_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down rsa internal memory.
-         */
-        uint32_t rsa_mem_pd:1;
-        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up rsa internal memory
-         */
-        uint32_t rsa_mem_force_pu:1;
-        /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power down rsa internal memory.
-         */
-        uint32_t rsa_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_rsa_pd_ctrl_reg_t;
-
-/** Type of ecc_conf register
- *  ECC configuration register
- */
-typedef union {
-    struct {
-        /** ecc_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ecc clock
-         */
-        uint32_t ecc_clk_en:1;
-        /** ecc_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ecc module
-         */
-        uint32_t ecc_rst_en:1;
-        /** ecc_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset ecc module
-         */
-        uint32_t ecc_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ecc_conf_reg_t;
-
-/** Type of ecc_pd_ctrl register
- *  ECC power control register
- */
-typedef union {
-    struct {
-        /** ecc_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down ecc internal memory.
-         */
-        uint32_t ecc_mem_pd:1;
-        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up ecc internal memory
-         */
-        uint32_t ecc_mem_force_pu:1;
-        /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power down ecc internal memory.
-         */
-        uint32_t ecc_mem_force_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ecc_pd_ctrl_reg_t;
-
-/** Type of ds_conf register
- *  DS configuration register
- */
-typedef union {
-    struct {
-        /** ds_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ds clock
-         */
-        uint32_t ds_clk_en:1;
-        /** ds_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ds module
-         */
-        uint32_t ds_rst_en:1;
-        /** ds_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset ds module
-         */
-        uint32_t ds_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ds_conf_reg_t;
-
-/** Type of hmac_conf register
- *  HMAC configuration register
- */
-typedef union {
-    struct {
-        /** hmac_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable hmac clock
-         */
-        uint32_t hmac_clk_en:1;
-        /** hmac_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset hmac module
-         */
-        uint32_t hmac_rst_en:1;
-        /** hmac_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset hmac module
-         */
-        uint32_t hmac_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_hmac_conf_reg_t;
-
-/** Type of ecdsa_conf register
- *  ECDSA configuration register
- */
-typedef union {
-    struct {
-        /** ecdsa_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable ecdsa clock
-         */
-        uint32_t ecdsa_clk_en:1;
-        /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset ecdsa module
-         */
-        uint32_t ecdsa_rst_en:1;
-        /** ecdsa_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset ecdsa module
-         */
-        uint32_t ecdsa_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_ecdsa_conf_reg_t;
-
-/** Type of iomux_conf register
- *  IOMUX configuration register
- */
-typedef union {
-    struct {
-        /** iomux_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable iomux apb clock
-         */
-        uint32_t iomux_clk_en:1;
-        /** iomux_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset iomux module
-         */
-        uint32_t iomux_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_iomux_conf_reg_t;
-
-/** Type of iomux_clk_conf register
- *  IOMUX_CLK configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:20;
-        /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0;
-         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
-         *  FOSC, 3(default): XTAL.
-         */
-        uint32_t iomux_func_clk_sel:2;
-        /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1;
-         *  Set 1 to enable iomux function clock
-         */
-        uint32_t iomux_func_clk_en:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} pcr_iomux_clk_conf_reg_t;
-
-/** Type of mem_monitor_conf register
- *  MEM_MONITOR configuration register
- */
-typedef union {
-    struct {
-        /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable mem_monitor clock
-         */
-        uint32_t mem_monitor_clk_en:1;
-        /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset mem_monitor module
-         */
-        uint32_t mem_monitor_rst_en:1;
-        /** mem_monitor_ready : RO; bitpos: [2]; default: 1;
-         *  Query this field after reset mem_monitor module
-         */
-        uint32_t mem_monitor_ready:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_mem_monitor_conf_reg_t;
-
-/** Type of regdma_conf register
- *  REGDMA configuration register
- */
-typedef union {
-    struct {
-        /** regdma_clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable regdma clock
-         */
-        uint32_t regdma_clk_en:1;
-        /** regdma_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset regdma module
-         */
-        uint32_t regdma_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_regdma_conf_reg_t;
-
-/** Type of trace_conf register
- *  TRACE configuration register
- */
-typedef union {
-    struct {
-        /** trace_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable trace clock
-         */
-        uint32_t trace_clk_en:1;
-        /** trace_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset trace module
-         */
-        uint32_t trace_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_trace_conf_reg_t;
-
-/** Type of assist_conf register
- *  ASSIST configuration register
- */
-typedef union {
-    struct {
-        /** assist_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable assist clock
-         */
-        uint32_t assist_clk_en:1;
-        /** assist_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset assist module
-         */
-        uint32_t assist_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_assist_conf_reg_t;
-
-/** Type of cache_conf register
- *  CACHE configuration register
- */
-typedef union {
-    struct {
-        /** cache_clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable cache clock
-         */
-        uint32_t cache_clk_en:1;
-        /** cache_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset cache module
-         */
-        uint32_t cache_rst_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_cache_conf_reg_t;
-
-/** Type of modem_conf register
- *  MODEM_APB configuration register
- */
-typedef union {
-    struct {
-        /** modem_clk_sel : R/W; bitpos: [0]; default: 0;
-         *  xxxx
-         */
-        uint32_t modem_clk_sel:1;
-        /** modem_clk_en : R/W; bitpos: [1]; default: 1;
-         *  xxxx
-         */
-        uint32_t modem_clk_en:1;
-        /** modem_rst_en : R/W; bitpos: [2]; default: 0;
-         *  Set this file as 1 to reset modem-subsystem.
-         */
-        uint32_t modem_rst_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_modem_conf_reg_t;
-
-/** Type of timeout_conf register
- *  TIMEOUT configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0;
-         *  Set 0 to reset cpu_peri timeout module
-         */
-        uint32_t cpu_timeout_rst_en:1;
-        /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0;
-         *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
-         */
-        uint32_t hp_timeout_rst_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} pcr_timeout_conf_reg_t;
-
-/** Type of sysclk_conf register
- *  SYSCLK configuration register
- */
-typedef union {
-    struct {
-        /** ls_div_num : HRO; bitpos: [7:0]; default: 0;
-         *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
-         *  clock-source such as XTAL/FOSC.
-         */
-        uint32_t ls_div_num:8;
-        /** hs_div_num : HRO; bitpos: [15:8]; default: 2;
-         *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
-         */
-        uint32_t hs_div_num:8;
-        /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0;
-         *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
-         */
-        uint32_t soc_clk_sel:2;
-        uint32_t reserved_18:6;
-        /** clk_xtal_freq : RO; bitpos: [30:24]; default: 32;
-         *  This field indicates the frequency(MHz) of XTAL.
-         */
-        uint32_t clk_xtal_freq:7;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} pcr_sysclk_conf_reg_t;
-
-/** Type of cpu_waiti_conf register
- *  CPU_WAITI configuration register
- */
-typedef union {
-    struct {
-        /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1;
-         *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
-         */
-        uint32_t cpuperiod_sel:2;
-        /** pll_freq_sel : HRO; bitpos: [2]; default: 1;
-         *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
-         */
-        uint32_t pll_freq_sel:1;
-        /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
-         *  Set 1 to force cpu_waiti_clk enable.
-         */
-        uint32_t cpu_wait_mode_force_on:1;
-        /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0;
-         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
-         *  will close
-         */
-        uint32_t cpu_waiti_delay_num:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} pcr_cpu_waiti_conf_reg_t;
-
-/** Type of cpu_freq_conf register
- *  CPU_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** cpu_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is
-         *  div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed
-         *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
-         */
-        uint32_t cpu_div_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} pcr_cpu_freq_conf_reg_t;
-
-/** Type of ahb_freq_conf register
- *  AHB_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** ahb_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is
-         *  div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for
-         *  low-speed clock-source such as XTAL/FOSC, and should be used together with
-         *  PCR_CPU_DIV_NUM.
-         */
-        uint32_t ahb_div_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} pcr_ahb_freq_conf_reg_t;
-
-/** Type of apb_freq_conf register
- *  APB_FREQ configuration register
- */
-typedef union {
-    struct {
-        /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
-         *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
-         *  recover to the previous frequency when a new access appears on apb-bus. Set as one
-         *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
-         *  that enable this function will reduce performance. Users can set this field as zero
-         *  to disable the auto-decrease-apb-freq function. By default, this function is
-         *  disable.
-         */
-        uint32_t apb_decrease_div_num:8;
-        /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
-         *  Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is
-         *  div1(default)/div2/div4 of clk_ahb.
-         */
-        uint32_t apb_div_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} pcr_apb_freq_conf_reg_t;
-
-/** Type of pll_div_clk_en register
- *  SPLL DIV clock-gating configuration register
- */
-typedef union {
-    struct {
-        /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
-         *  This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1:
-         *  open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_240m_clk_en:1;
-        /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
-         *  This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_160m_clk_en:1;
-        /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
-         *  This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_120m_clk_en:1;
-        /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
-         *  This field is used to open 32 MHz clock (div6  of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_80m_clk_en:1;
-        /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_48m_clk_en:1;
-        /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close,
-         *  1: open(default). Only avaliable when high-speed clock-source SPLL is active.
-         */
-        uint32_t pll_40m_clk_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} pcr_pll_div_clk_en_reg_t;
-
-/** Type of ctrl_clk_out_en register
- *  CLK_OUT_EN configuration register
- */
-typedef union {
-    struct {
-        /** clk8_oen : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to enable 8m clock
-         */
-        uint32_t clk8_oen:1;
-        /** clk16_oen : R/W; bitpos: [1]; default: 1;
-         *  Set 1 to enable 16m clock
-         */
-        uint32_t clk16_oen:1;
-        /** clk32_oen : R/W; bitpos: [2]; default: 1;
-         *  Set 1 to enable 32m clock
-         */
-        uint32_t clk32_oen:1;
-        /** clk_adc_inf_oen : R/W; bitpos: [3]; default: 1;
-         *  Reserved
-         */
-        uint32_t clk_adc_inf_oen:1;
-        /** clk_dfm_inf_oen : R/W; bitpos: [4]; default: 1;
-         *  Reserved
-         */
-        uint32_t clk_dfm_inf_oen:1;
-        /** clk_sdm_mod_oen : R/W; bitpos: [5]; default: 1;
-         *  Reserved
-         */
-        uint32_t clk_sdm_mod_oen:1;
-        /** clk_xtal_oen : R/W; bitpos: [6]; default: 1;
-         *  Set 1 to enable xtal clock
-         */
-        uint32_t clk_xtal_oen:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} pcr_ctrl_clk_out_en_reg_t;
-
-/** Type of ctrl_tick_conf register
- *  TICK configuration register
- */
-typedef union {
-    struct {
-        /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39;
-         *  ******* Description ***********
-         */
-        uint32_t xtal_tick_num:8;
-        /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7;
-         *  ******* Description ***********
-         */
-        uint32_t fosc_tick_num:8;
-        /** tick_enable : R/W; bitpos: [16]; default: 1;
-         *  ******* Description ***********
-         */
-        uint32_t tick_enable:1;
-        /** rst_tick_cnt : R/W; bitpos: [17]; default: 0;
-         *  ******* Description ***********
-         */
-        uint32_t rst_tick_cnt:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} pcr_ctrl_tick_conf_reg_t;
-
-/** Type of ctrl_32k_conf register
- *  32KHz clock configuration register
- */
-typedef union {
-    struct {
-        /** 32k_sel : R/W; bitpos: [1:0]; default: 0;
-         *  This field indicates which one 32KHz clock will be used by timergroup. 0:
-         *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
-         */
-        uint32_t clk_32k_sel:2;
-        /** 32k_modem_sel : R/W; bitpos: [3:2]; default: 0;
-         *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0:
-         *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
-         */
-        uint32_t clk_32k_modem_sel:2;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_ctrl_32k_conf_reg_t;
-
-/** Type of sram_power_conf_0 register
- *  HP SRAM/ROM configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:13;
-        /** rom_force_pu : R/W; bitpos: [14:13]; default: 3;
-         *  Set this bit to force power up ROM
-         */
-        uint32_t rom_force_pu:2;
-        /** rom_force_pd : R/W; bitpos: [16:15]; default: 0;
-         *  Set this bit to force power down ROM.
-         */
-        uint32_t rom_force_pd:2;
-        /** rom_clkgate_force_on : R/W; bitpos: [18:17]; default: 0;
-         *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
-         *  gate-clock will be used when accessing the ROM.
-         */
-        uint32_t rom_clkgate_force_on:2;
-        uint32_t reserved_19:13;
-    };
-    uint32_t val;
-} pcr_sram_power_conf_0_reg_t;
-
-/** Type of sram_power_conf_1 register
- *  HP SRAM/ROM configuration register
- */
-typedef union {
-    struct {
-        /** sram_force_pu : R/W; bitpos: [4:0]; default: 31;
-         *  Set this bit to force power up SRAM
-         */
-        uint32_t sram_force_pu:5;
-        uint32_t reserved_5:5;
-        /** sram_force_pd : R/W; bitpos: [14:10]; default: 0;
-         *  Set this bit to force power down SRAM.
-         */
-        uint32_t sram_force_pd:5;
-        uint32_t reserved_15:10;
-        /** sram_clkgate_force_on : R/W; bitpos: [29:25]; default: 0;
-         *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
-         *  gate-clock will be used when accessing the SRAM.
-         */
-        uint32_t sram_clkgate_force_on:5;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} pcr_sram_power_conf_1_reg_t;
-
-/** Type of sec_conf register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0;
-         *  xxxx
-         */
-        uint32_t sec_clk_sel:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_sec_conf_reg_t;
-
-/** Type of adc_inv_phase_conf register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** clk_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0;
-         *  xxxx
-         */
-        uint32_t clk_adc_inv_phase_ena:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} pcr_adc_inv_phase_conf_reg_t;
-
-/** Type of sdm_inv_phase_conf register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** clk_sdm_inv_phase_ena : R/W; bitpos: [0]; default: 0;
-         *  xxxx
-         */
-        uint32_t clk_sdm_inv_phase_ena:1;
-        /** clk_sdm_inv_phase_sel : R/W; bitpos: [3:1]; default: 0;
-         *  xxxx
-         */
-        uint32_t clk_sdm_inv_phase_sel:3;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} pcr_sdm_inv_phase_conf_reg_t;
-
-/** Type of bus_clk_update register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0;
-         *  xxxx
-         */
-        uint32_t bus_clock_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} pcr_bus_clk_update_reg_t;
-
-/** Type of sar_clk_div register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4;
-         *  xxxx
-         */
-        uint32_t sar2_clk_div_num:8;
-        /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4;
-         *  xxxx
-         */
-        uint32_t sar1_clk_div_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} pcr_sar_clk_div_reg_t;
-
-/** Type of pwdet_sar_clk_conf register
- *  xxxx
- */
-typedef union {
-    struct {
-        /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7;
-         *  xxxx
-         */
-        uint32_t pwdet_sar_clk_div_num:8;
-        /** pwdet_sar_reader_en : R/W; bitpos: [8]; default: 1;
-         *  xxxx
-         */
-        uint32_t pwdet_sar_reader_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} pcr_pwdet_sar_clk_conf_reg_t;
-
-/** Type of reset_event_bypass register
- *  reset event bypass backdoor configuration register
- */
-typedef union {
-    struct {
-        /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0;
-         *  This field is used to control reset event relationship for
-         *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
-         *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
-         *  will not only be reset by power-reset, but also some reset event.
-         */
-        uint32_t reset_event_bypass_apm:1;
-        /** reset_event_bypass : R/W; bitpos: [1]; default: 1;
-         *  This field is used to control reset event relationship for system-bus. 1: system
-         *  bus (including arbiter/router) will only be reset by power-reset. some reset event
-         *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
-         *  power-reset, but also some reset event.
-         */
-        uint32_t reset_event_bypass:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} pcr_reset_event_bypass_reg_t;
-
-/** Type of clock_gate register
- *  PCR clock gating configure register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit as 1 to force on clock gating.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} pcr_clock_gate_reg_t;
-
-
-/** Group: Frequency Statistics Register */
-/** Type of sysclk_freq_query_0 register
- *  SYSCLK frequency query 0 register
- */
-typedef union {
-    struct {
-        /** fosc_freq : HRO; bitpos: [7:0]; default: 8;
-         *  This field indicates the frequency(MHz) of FOSC.
-         */
-        uint32_t fosc_freq:8;
-        /** pll_freq : HRO; bitpos: [17:8]; default: 96;
-         *  This field indicates the frequency(MHz) of SPLL.
-         */
-        uint32_t pll_freq:10;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} pcr_sysclk_freq_query_0_reg_t;
-
-
-/** Group: FPGA Debug Register */
-/** Type of fpga_debug register
- *  fpga debug register
- */
-typedef union {
-    struct {
-        /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Only used in fpga debug.
-         */
-        uint32_t fpga_debug:32;
-    };
-    uint32_t val;
-} pcr_fpga_debug_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35717248;
-         *  PCR version information.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} pcr_date_reg_t;
-
-
-/**
- * @brief The struct of I2C configuration registers
- */
-typedef struct {
-    pcr_i2c_conf_reg_t i2c_conf;
-    pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
-} pcr_i2c_reg_t;
-
-typedef struct {
-    volatile pcr_uart0_conf_reg_t uart0_conf;
-    volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf;
-    volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl;
-    volatile pcr_uart1_conf_reg_t uart1_conf;
-    volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf;
-    volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl;
-    volatile pcr_mspi_conf_reg_t mspi_conf;
-    volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf;
-    volatile pcr_i2c_reg_t i2c[2];
-    volatile pcr_uhci_conf_reg_t uhci_conf;
-    volatile pcr_rmt_conf_reg_t rmt_conf;
-    volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf;
-    volatile pcr_ledc_conf_reg_t ledc_conf;
-    volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf;
-    volatile pcr_timergroup0_conf_reg_t timergroup0_conf;
-    volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf;
-    volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf;
-    volatile pcr_timergroup1_conf_reg_t timergroup1_conf;
-    volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf;
-    volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf;
-    volatile pcr_systimer_conf_reg_t systimer_conf;
-    volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf;
-    volatile pcr_twai0_conf_reg_t twai0_conf;
-    volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf;
-    volatile pcr_i2s_conf_reg_t i2s_conf;
-    volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf;
-    volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf;
-    volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf;
-    volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf;
-    volatile pcr_saradc_conf_reg_t saradc_conf;
-    volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf;
-    volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf;
-    volatile pcr_usb_device_conf_reg_t usb_device_conf;
-    volatile pcr_intmtx_conf_reg_t intmtx_conf;
-    volatile pcr_pcnt_conf_reg_t pcnt_conf;
-    volatile pcr_etm_conf_reg_t etm_conf;
-    volatile pcr_pwm_conf_reg_t pwm_conf;
-    volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf;
-    volatile pcr_parl_io_conf_reg_t parl_io_conf;
-    volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf;
-    volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf;
-    volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf;
-    volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf;
-    volatile pcr_gdma_conf_reg_t gdma_conf;
-    volatile pcr_spi2_conf_reg_t spi2_conf;
-    volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf;
-    volatile pcr_aes_conf_reg_t aes_conf;
-    volatile pcr_sha_conf_reg_t sha_conf;
-    volatile pcr_rsa_conf_reg_t rsa_conf;
-    volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
-    volatile pcr_ecc_conf_reg_t ecc_conf;
-    volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
-    volatile pcr_ds_conf_reg_t ds_conf;
-    volatile pcr_hmac_conf_reg_t hmac_conf;
-    volatile pcr_ecdsa_conf_reg_t ecdsa_conf;
-    volatile pcr_iomux_conf_reg_t iomux_conf;
-    volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf;
-    volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf;
-    volatile pcr_regdma_conf_reg_t regdma_conf;
-    volatile pcr_trace_conf_reg_t trace_conf;
-    volatile pcr_assist_conf_reg_t assist_conf;
-    volatile pcr_cache_conf_reg_t cache_conf;
-    volatile pcr_modem_conf_reg_t modem_conf;
-    volatile pcr_timeout_conf_reg_t timeout_conf;
-    volatile pcr_sysclk_conf_reg_t sysclk_conf;
-    volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf;
-    volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf;
-    volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf;
-    volatile pcr_apb_freq_conf_reg_t apb_freq_conf;
-    volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0;
-    volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en;
-    volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en;
-    volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf;
-    volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf;
-    volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0;
-    volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1;
-    volatile pcr_sec_conf_reg_t sec_conf;
-    volatile pcr_adc_inv_phase_conf_reg_t adc_inv_phase_conf;
-    volatile pcr_sdm_inv_phase_conf_reg_t sdm_inv_phase_conf;
-    volatile pcr_bus_clk_update_reg_t bus_clk_update;
-    volatile pcr_sar_clk_div_reg_t sar_clk_div;
-    volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf;
-    uint32_t reserved_154[935];
-    volatile pcr_reset_event_bypass_reg_t reset_event_bypass;
-    volatile pcr_fpga_debug_reg_t fpga_debug;
-    volatile pcr_clock_gate_reg_t clock_gate;
-    volatile pcr_date_reg_t date;
-} pcr_dev_t;
-
-extern pcr_dev_t PCR;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/periph_defs.h b/components/soc/esp32h2/include/soc/periph_defs.h
index ea39288868a..8c8477c51cc 100644
--- a/components/soc/esp32h2/include/soc/periph_defs.h
+++ b/components/soc/esp32h2/include/soc/periph_defs.h
@@ -19,7 +19,7 @@ typedef enum {
     PERIPH_USB_DEVICE_MODULE,
     PERIPH_I2C0_MODULE,
     PERIPH_I2C1_MODULE,
-    PERIPH_I2S1_MODULE,
+    PERIPH_I2S0_MODULE,
     PERIPH_TIMG0_MODULE,
     PERIPH_TIMG1_MODULE,
     PERIPH_UHCI0_MODULE,
diff --git a/components/soc/esp32h2/include/soc/pmu_icg_mapping.h b/components/soc/esp32h2/include/soc/pmu_icg_mapping.h
index 6501927d3aa..65df97ef264 100644
--- a/components/soc/esp32h2/include/soc/pmu_icg_mapping.h
+++ b/components/soc/esp32h2/include/soc/pmu_icg_mapping.h
@@ -1,66 +1,63 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#pragma once
 
-#define PMU_ICG_APB_ENA_CAN0                               18
-#define PMU_ICG_APB_ENA_CAN1                               19
+#pragma once
+#define PMU_ICG_APB_ENA_SEC                                0
 #define PMU_ICG_APB_ENA_GDMA                               1
-#define PMU_ICG_APB_ENA_I2C                                13
-#define PMU_ICG_APB_ENA_I2S                                4
+#define PMU_ICG_APB_ENA_SPI2                               2
 #define PMU_ICG_APB_ENA_INTMTX                             3
-#define PMU_ICG_APB_ENA_IOMUX                              26
-#define PMU_ICG_APB_ENA_LEDC                               14
-#define PMU_ICG_APB_ENA_MEM_MONITOR                        25
+#define PMU_ICG_APB_ENA_I2S                                4
 #define PMU_ICG_APB_ENA_MSPI                               5
-#define PMU_ICG_APB_ENA_PARL                               23
-#define PMU_ICG_APB_ENA_PCNT                               20
-#define PMU_ICG_APB_ENA_PVT_MONITOR                        27
-#define PMU_ICG_APB_ENA_PWM                                21
-#define PMU_ICG_APB_ENA_REGDMA                             24
-#define PMU_ICG_APB_ENA_RMT                                15
-#define PMU_ICG_APB_ENA_SARADC                             9
-#define PMU_ICG_APB_ENA_SEC                                0
-#define PMU_ICG_APB_ENA_SOC_ETM                            22
-#define PMU_ICG_APB_ENA_SPI2                               2
-#define PMU_ICG_APB_ENA_SYSTIMER                           16
-#define PMU_ICG_APB_ENA_TG0                                11
-#define PMU_ICG_APB_ENA_TG1                                12
 #define PMU_ICG_APB_ENA_UART0                              6
 #define PMU_ICG_APB_ENA_UART1                              7
 #define PMU_ICG_APB_ENA_UHCI                               8
+#define PMU_ICG_APB_ENA_SARADC                             9
+#define PMU_ICG_APB_ENA_TG0                                11
+#define PMU_ICG_APB_ENA_TG1                                12
+#define PMU_ICG_APB_ENA_I2C                                13
+#define PMU_ICG_APB_ENA_LEDC                               14
+#define PMU_ICG_APB_ENA_RMT                                15
+#define PMU_ICG_APB_ENA_SYSTIMER                           16
 #define PMU_ICG_APB_ENA_USB_DEVICE                         17
-#define PMU_ICG_FUNC_ENA_CAN0                              31
-#define PMU_ICG_FUNC_ENA_CAN1                              30
-#define PMU_ICG_FUNC_ENA_I2C                               29
-#define PMU_ICG_FUNC_ENA_I2S_RX                            2
-#define PMU_ICG_FUNC_ENA_I2S_TX                            7
-#define PMU_ICG_FUNC_ENA_IOMUX                             28
-#define PMU_ICG_FUNC_ENA_LEDC                              27
-#define PMU_ICG_FUNC_ENA_MEM_MONITOR                       10
-#define PMU_ICG_FUNC_ENA_MSPI                              26
-#define PMU_ICG_FUNC_ENA_PARL_RX                           25
-#define PMU_ICG_FUNC_ENA_PARL_TX                           24
-#define PMU_ICG_FUNC_ENA_PVT_MONITOR                       23
-#define PMU_ICG_FUNC_ENA_PWM                               22
-#define PMU_ICG_FUNC_ENA_RMT                               21
-#define PMU_ICG_FUNC_ENA_SARADC                            20
-#define PMU_ICG_FUNC_ENA_SEC                               19
+#define PMU_ICG_APB_ENA_TWAI                               18
+#define PMU_ICG_APB_ENA_PCNT                               20
+#define PMU_ICG_APB_ENA_PWM                                21
+#define PMU_ICG_APB_ENA_SOC_ETM                            22
+#define PMU_ICG_APB_ENA_PARL                               23
+#define PMU_ICG_APB_ENA_REGDMA                             24
+#define PMU_ICG_APB_ENA_MEM_MONITOR                        25
+#define PMU_ICG_APB_ENA_IOMUX                              26
+#define PMU_ICG_APB_ENA_PVT_MONITOR                        27
+#define PMU_ICG_FUNC_ENA_GDMA                              0
 #define PMU_ICG_FUNC_ENA_SPI2                              1
-#define PMU_ICG_FUNC_ENA_SYSTIMER                          18
-#define PMU_ICG_FUNC_ENA_TG0                               14
-#define PMU_ICG_FUNC_ENA_TG1                               13
-#define PMU_ICG_FUNC_ENA_TSENS                             12
+#define PMU_ICG_FUNC_ENA_I2S_RX                            2
 #define PMU_ICG_FUNC_ENA_UART0                             3
 #define PMU_ICG_FUNC_ENA_UART1                             4
+#define PMU_ICG_FUNC_ENA_UHCI                              5
 #define PMU_ICG_FUNC_ENA_USB_DEVICE                        6
-#define PMU_ICG_FUNC_ENA_GDMA                              0
-#define PMU_ICG_FUNC_ENA_SOC_ETM                           16
+#define PMU_ICG_FUNC_ENA_I2S_TX                            7
 #define PMU_ICG_FUNC_ENA_REGDMA                            8
-#define PMU_ICG_FUNC_ENA_RETENTION                         9
-#define PMU_ICG_FUNC_ENA_SDIO_SLAVE                        11
-#define PMU_ICG_FUNC_ENA_UHCI                              5
-#define PMU_ICG_FUNC_ENA_HPCORE                            17
+#define PMU_ICG_FUNC_ENA_MEM_MONITOR                       10
+#define PMU_ICG_FUNC_ENA_TSENS                             12
+#define PMU_ICG_FUNC_ENA_TG1                               13
+#define PMU_ICG_FUNC_ENA_TG0                               14
 #define PMU_ICG_FUNC_ENA_HPBUS                             15
+#define PMU_ICG_FUNC_ENA_HPMEM                             15
+#define PMU_ICG_FUNC_ENA_SOC_ETM                           16
+#define PMU_ICG_FUNC_ENA_HPCORE                            17
+#define PMU_ICG_FUNC_ENA_SYSTIMER                          18
+#define PMU_ICG_FUNC_ENA_SEC                               19
+#define PMU_ICG_FUNC_ENA_SARADC                            20
+#define PMU_ICG_FUNC_ENA_RMT                               21
+#define PMU_ICG_FUNC_ENA_PWM                               22
+#define PMU_ICG_FUNC_ENA_PVT_MONITOR                       23
+#define PMU_ICG_FUNC_ENA_PARL_TX                           24
+#define PMU_ICG_FUNC_ENA_PARL_RX                           25
+#define PMU_ICG_FUNC_ENA_MSPI                              26
+#define PMU_ICG_FUNC_ENA_LEDC                              27
+#define PMU_ICG_FUNC_ENA_IOMUX                             28
+#define PMU_ICG_FUNC_ENA_I2C                               29
+#define PMU_ICG_FUNC_ENA_TWAI                              31
diff --git a/components/soc/esp32h2/include/soc/reg_base.h b/components/soc/esp32h2/include/soc/reg_base.h
deleted file mode 100644
index e3801b9c9a6..00000000000
--- a/components/soc/esp32h2/include/soc/reg_base.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DR_REG_UART_BASE                        0x60000000
-#define DR_REG_UART1_BASE                       0x60001000
-#define DR_REG_SPI0_BASE                        0x60002000
-#define DR_REG_SPI1_BASE                        0x60003000
-#define DR_REG_I2C_EXT0_BASE                    0x60004000
-#define DR_REG_I2C_EXT1_BASE                    0x60005000
-#define DR_REG_UHCI0_BASE                       0x60006000
-#define DR_REG_RMT_BASE                         0x60007000
-#define DR_REG_LEDC_BASE                        0x60008000
-#define DR_REG_TIMERGROUP0_BASE                 0x60009000
-#define DR_REG_TIMERGROUP1_BASE                 0x6000A000
-#define DR_REG_SYSTIMER_BASE                    0x6000B000
-#define DR_REG_TWAI_BASE                        0x6000C000
-#define DR_REG_I2S_BASE                         0x6000D000
-#define DR_REG_APB_SARADC_BASE                  0x6000E000
-#define DR_REG_USB_SERIAL_JTAG_BASE             0x6000F000
-#define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
-#define DR_REG_PCNT_BASE                        0x60012000
-#define DR_REG_SOC_ETM_BASE                     0x60013000
-#define DR_REG_MCPWM_BASE                       0x60014000
-#define DR_REG_PARl_IO_BASE                     0x60015000
-#define DR_REG_PVT_MONITOR_BASE                 0x60019000
-#define DR_REG_GDMA_BASE                        0x60080000
-#define DR_REG_SPI2_BASE                        0x60081000
-#define DR_REG_AES_BASE                         0x60088000
-#define DR_REG_SHA_BASE                         0x60089000
-#define DR_REG_RSA_BASE                         0x6008A000
-#define DR_REG_ECC_MULT_BASE                    0x6008B000
-#define DR_REG_DS_BASE                          0x6008C000
-#define DR_REG_HMAC_BASE                        0x6008D000
-#define DR_REG_ECDSA_BASE                       0x6008E000
-#define DR_REG_IO_MUX_BASE                      0x60090000
-#define DR_REG_MEM_MONITOR_BASE                 0x60092000
-#define DR_REG_PAU_BASE                         0x60093000
-#define DR_REG_LPPERI_BASE                      0x600B2800
-#define DR_REG_GPIO_BASE                        0x60091000
-#define DR_REG_GPIO_EXT_BASE                    0x60091f00
-#define DR_REG_MEM_ACS_MONITOR_BASE             0x60092000
-#define DR_REG_REGDMA_BASE                      0x60093000
-#define DR_REG_HP_SYSTEM_BASE                   0x60095000
-#define DR_REG_PCR_BASE                         0x60096000
-#define DR_REG_TEE_BASE                         0x60098000
-#define DR_REG_HP_APM_BASE                      0x60099000
-#define DR_REG_LP_APM0_BASE                     0x60099800
-#define DR_REG_MISC_BASE                        0x6009F000
-
-#define DR_REG_I2C_ANA_MST_BASE                 0x600AD800
-
-#define DR_REG_PMU_BASE                         0x600B0000
-#define DR_REG_LP_CLKRST_BASE                   0x600B0400
-#define DR_REG_EFUSE_BASE                       0x600B0800
-#define DR_REG_LP_TIMER_BASE                    0x600B0C00
-#define DR_REG_LP_AON_BASE                      0x600B1000
-#define DR_REG_LP_WDT_BASE                      0x600B1C00
-#define DR_REG_LP_IO_BASE                       0x600B2000
-#define DR_REG_LP_ANALOG_PERI_BASE              0x600B2C00
-#define DR_REG_LP_APM_BASE                      0x600B3800
-#define DR_REG_OTP_DEBUG_BASE                   0x600B3C00
-
-#define DR_REG_TRACE_BASE                       0x600C0000
-#define DR_REG_ASSIST_DEBUG_BASE                0x600C2000
-#define DR_REG_INTPRI_BASE                      0x600C5000
-#define DR_REG_CACHE_BASE                       0x600C8000
-
-#define PWDET_CONF_REG                          0x600A0810
-#define IEEE802154_REG_BASE                     0x600A3000
diff --git a/components/soc/esp32h2/include/soc/regi2c_brownout.h b/components/soc/esp32h2/include/soc/regi2c_brownout.h
index 9daf67f093b..0d2caf531c1 100644
--- a/components/soc/esp32h2/include/soc/regi2c_brownout.h
+++ b/components/soc/esp32h2/include/soc/regi2c_brownout.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -44,6 +44,10 @@
 #define I2C_PMU_OR_DREFH_VDDA_MSB     7
 #define I2C_PMU_OR_DREFH_VDDA_LSB     5
 
-#define I2C_BOD_THRESHOLD           I2C_PMU_OR_DREFL_VDDA
-#define I2C_BOD_THRESHOLD_MSB       I2C_PMU_OR_DREFL_VDDA_MSB
-#define I2C_BOD_THRESHOLD_LSB       I2C_PMU_OR_DREFL_VDDA_LSB
+#define I2C_BOD_THRESHOLD_L           I2C_PMU_OR_DREFL_VDDA
+#define I2C_BOD_THRESHOLD_L_MSB       I2C_PMU_OR_DREFL_VDDA_MSB
+#define I2C_BOD_THRESHOLD_L_LSB       I2C_PMU_OR_DREFL_VDDA_LSB
+
+#define I2C_BOD_THRESHOLD_H           I2C_PMU_OR_DREFH_VDDA
+#define I2C_BOD_THRESHOLD_H_MSB       I2C_PMU_OR_DREFH_VDDA_MSB
+#define I2C_BOD_THRESHOLD_H_LSB       I2C_PMU_OR_DREFH_VDDA_LSB
diff --git a/components/soc/esp32h2/include/soc/retention_periph_defs.h b/components/soc/esp32h2/include/soc/retention_periph_defs.h
index 819af3a2b35..de9a8c16bfb 100644
--- a/components/soc/esp32h2/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32h2/include/soc/retention_periph_defs.h
@@ -15,6 +15,7 @@ extern "C" {
 
 typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_MIN          = 0,
+    SLEEP_RETENTION_MODULE_NULL         = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
     SLEEP_RETENTION_MODULE_CLOCK_MODEM  = 2,
@@ -38,6 +39,14 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_UART0        = 15,
     SLEEP_RETENTION_MODULE_UART1        = 16,
     SLEEP_RETENTION_MODULE_I2S0         = 17,
+    SLEEP_RETENTION_MODULE_ETM0         = 18,
+    SLEEP_RETENTION_MODULE_TEMP_SENSOR  = 19,
+    SLEEP_RETENTION_MODULE_TWAI0        = 20,
+    SLEEP_RETENTION_MODULE_PARLIO0      = 21,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 22,
+    SLEEP_RETENTION_MODULE_LEDC         = 23,
+    SLEEP_RETENTION_MODULE_PCNT0        = 24,
+    SLEEP_RETENTION_MODULE_MCPWM0       = 25,
 
     /* Modem module, which includes BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
@@ -47,6 +56,8 @@ typedef enum periph_retention_module {
 } periph_retention_module_t;
 
 typedef enum periph_retention_module_bitmap {
+    SLEEP_RETENTION_MODULE_BM_NULL = BIT(SLEEP_RETENTION_MODULE_NULL),
+
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
     SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM  = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
@@ -70,6 +81,14 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_UART0        = BIT(SLEEP_RETENTION_MODULE_UART0),
     SLEEP_RETENTION_MODULE_BM_UART1        = BIT(SLEEP_RETENTION_MODULE_UART1),
     SLEEP_RETENTION_MODULE_BM_I2S0         = BIT(SLEEP_RETENTION_MODULE_I2S0),
+    SLEEP_RETENTION_MODULE_BM_ETM0         = BIT(SLEEP_RETENTION_MODULE_ETM0),
+    SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR  = BIT(SLEEP_RETENTION_MODULE_TEMP_SENSOR),
+    SLEEP_RETENTION_MODULE_BM_TWAI0        = BIT(SLEEP_RETENTION_MODULE_TWAI0),
+    SLEEP_RETENTION_MODULE_BM_PARLIO0      = BIT(SLEEP_RETENTION_MODULE_PARLIO0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
+    SLEEP_RETENTION_MODULE_BM_PCNT0        = BIT(SLEEP_RETENTION_MODULE_PCNT0),
+    SLEEP_RETENTION_MODULE_BM_MCPWM0       = BIT(SLEEP_RETENTION_MODULE_MCPWM0),
     /* modem module, which includes BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BM_BLE_MAC      = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
     SLEEP_RETENTION_MODULE_BM_BT_BB        = BIT(SLEEP_RETENTION_MODULE_BT_BB),
@@ -92,6 +111,15 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_UART0       \
                                   | SLEEP_RETENTION_MODULE_BM_UART1       \
                                   | SLEEP_RETENTION_MODULE_BM_I2S0        \
+                                  | SLEEP_RETENTION_MODULE_BM_ETM0        \
+                                  | SLEEP_RETENTION_MODULE_BM_TEMP_SENSOR \
+                                  | SLEEP_RETENTION_MODULE_BM_TWAI0       \
+                                  | SLEEP_RETENTION_MODULE_BM_PARLIO0     \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC        \
+                                  | SLEEP_RETENTION_MODULE_BM_PCNT0       \
+                                  | SLEEP_RETENTION_MODULE_BM_MCPWM0      \
+                                  | SLEEP_RETENTION_MODULE_BM_NULL       \
                                   )
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32h2/include/soc/sha_reg.h b/components/soc/esp32h2/include/soc/sha_reg.h
deleted file mode 100644
index b5a4529f4e1..00000000000
--- a/components/soc/esp32h2/include/soc/sha_reg.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SHA_MODE_REG register
- *  Initial configuration register.
- */
-#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
-/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  Sha mode.
- */
-#define SHA_MODE    0x00000007U
-#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
-#define SHA_MODE_V  0x00000007U
-#define SHA_MODE_S  0
-
-/** SHA_T_STRING_REG register
- *  SHA 512/t configuration register 0.
- */
-#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
-/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
- *  Sha t_string (used if and only if mode == SHA_512/t).
- */
-#define SHA_T_STRING    0xFFFFFFFFU
-#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
-#define SHA_T_STRING_V  0xFFFFFFFFU
-#define SHA_T_STRING_S  0
-
-/** SHA_T_LENGTH_REG register
- *  SHA 512/t configuration register 1.
- */
-#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
-/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
- *  Sha t_length (used if and only if mode == SHA_512/t).
- */
-#define SHA_T_LENGTH    0x0000003FU
-#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
-#define SHA_T_LENGTH_V  0x0000003FU
-#define SHA_T_LENGTH_S  0
-
-/** SHA_DMA_BLOCK_NUM_REG register
- *  DMA configuration register 0.
- */
-#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
-/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
- *  Dma-sha block number.
- */
-#define SHA_DMA_BLOCK_NUM    0x0000003FU
-#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
-#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
-#define SHA_DMA_BLOCK_NUM_S  0
-
-/** SHA_START_REG register
- *  Typical SHA configuration register 0.
- */
-#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
-/** SHA_START : RO; bitpos: [31:1]; default: 0;
- *  Reserved.
- */
-#define SHA_START    0x7FFFFFFFU
-#define SHA_START_M  (SHA_START_V << SHA_START_S)
-#define SHA_START_V  0x7FFFFFFFU
-#define SHA_START_S  1
-
-/** SHA_CONTINUE_REG register
- *  Typical SHA configuration register 1.
- */
-#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
-/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
- *  Reserved.
- */
-#define SHA_CONTINUE    0x7FFFFFFFU
-#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
-#define SHA_CONTINUE_V  0x7FFFFFFFU
-#define SHA_CONTINUE_S  1
-
-/** SHA_BUSY_REG register
- *  Busy register.
- */
-#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
-/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
- *  Sha busy state. 1'b0: idle. 1'b1: busy.
- */
-#define SHA_BUSY_STATE    (BIT(0))
-#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
-#define SHA_BUSY_STATE_V  0x00000001U
-#define SHA_BUSY_STATE_S  0
-
-/** SHA_DMA_START_REG register
- *  DMA configuration register 1.
- */
-#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
-/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
- *  Start dma-sha.
- */
-#define SHA_DMA_START    (BIT(0))
-#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
-#define SHA_DMA_START_V  0x00000001U
-#define SHA_DMA_START_S  0
-
-/** SHA_DMA_CONTINUE_REG register
- *  DMA configuration register 2.
- */
-#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
-/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
- *  Continue dma-sha.
- */
-#define SHA_DMA_CONTINUE    (BIT(0))
-#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
-#define SHA_DMA_CONTINUE_V  0x00000001U
-#define SHA_DMA_CONTINUE_S  0
-
-/** SHA_CLEAR_IRQ_REG register
- *  Interrupt clear register.
- */
-#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
-/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
- *  Clear sha interrupt.
- */
-#define SHA_CLEAR_INTERRUPT    (BIT(0))
-#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
-#define SHA_CLEAR_INTERRUPT_V  0x00000001U
-#define SHA_CLEAR_INTERRUPT_S  0
-
-/** SHA_IRQ_ENA_REG register
- *  Interrupt enable register.
- */
-#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
-/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
- *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
- */
-#define SHA_INTERRUPT_ENA    (BIT(0))
-#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
-#define SHA_INTERRUPT_ENA_V  0x00000001U
-#define SHA_INTERRUPT_ENA_S  0
-
-/** SHA_DATE_REG register
- *  Date register.
- */
-#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
-/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
- *  Sha date information/ sha version information.
- */
-#define SHA_DATE    0x3FFFFFFFU
-#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
-#define SHA_DATE_V  0x3FFFFFFFU
-#define SHA_DATE_S  0
-
-/** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
- */
-#define SHA_H_MEM_REG (DR_REG_SHA_BASE + 0x40)
-#define SHA_H_MEM_SIZE_BYTES 64
-
-/** SHA_M_MEM register
- *  Sha M memory which contains message.
- */
-#define SHA_M_MEM_REG (DR_REG_SHA_BASE + 0x80)
-#define SHA_M_MEM_SIZE_BYTES 64
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h
index f3d2b2a9041..b35b9cc15fa 100644
--- a/components/soc/esp32h2/include/soc/soc.h
+++ b/components/soc/esp32h2/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index d5ae0377d19..c355f01633d 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -181,6 +181,7 @@
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
 #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
+#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1   // Support sleep retention
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-H2 has 1 GPIO peripheral
@@ -279,12 +280,14 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (6)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_SUPPORT_SLEEP_RETENTION    (1)
 
 /*-------------------------- MPU CAPS ----------------------------------------*/
 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED    0
@@ -299,6 +302,7 @@
 #define SOC_PCNT_CHANNELS_PER_UNIT            2
 #define SOC_PCNT_THRES_POINT_PER_UNIT         2
 #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
+#define SOC_PCNT_SUPPORT_SLEEP_RETENTION      1  /*!< The sleep retention feature can help back up PCNT registers before sleep */
 
 /*--------------------------- RMT CAPS ---------------------------------------*/
 #define SOC_RMT_GROUPS                        1U /*!< One RMT group */
@@ -331,6 +335,7 @@
 #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE       (1)    ///< Software sync event can be routed to its output
 #define SOC_MCPWM_SUPPORT_ETM                (1)    ///< Support ETM (Event Task Matrix)
 #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP     (1)    ///< Capture timer shares clock with other PWM timers
+#define SOC_MCPWM_SUPPORT_SLEEP_RETENTION    (1)    ///< Support back up registers before sleep
 
 /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
 // #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
@@ -345,6 +350,7 @@
 #define SOC_PARLIO_RX_CLK_SUPPORT_GATING     1  /*!< Support gating RX clock */
 #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT     1  /*!< Support output RX clock to a GPIO */
 #define SOC_PARLIO_TRANS_BIT_ALIGN           1  /*!< Support bit alignment in transaction */
+#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION   1  /*!< Support back up registers before sleep */
 
 /*--------------------------- MPI CAPS ---------------------------------------*/
 #define SOC_MPI_MEM_BLOCKS_NUM (4)
@@ -391,6 +397,7 @@
 #define SOC_SPI_SUPPORT_CD_SIG              1
 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS    1
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+#define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
 #define SOC_SPI_SUPPORT_CLK_XTAL            1
 #define SOC_SPI_SUPPORT_CLK_PLL_F48M        1
 #define SOC_SPI_SUPPORT_CLK_RC_FAST         1
@@ -452,11 +459,12 @@
 #define SOC_MWDT_SUPPORT_SLEEP_RETENTION   (1)
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
-#define SOC_TWAI_CONTROLLER_NUM         1UL
-#define SOC_TWAI_CLK_SUPPORT_XTAL       1
-#define SOC_TWAI_BRP_MIN                2
-#define SOC_TWAI_BRP_MAX                32768
-#define SOC_TWAI_SUPPORTS_RX_STATUS     1
+#define SOC_TWAI_CONTROLLER_NUM             1UL
+#define SOC_TWAI_CLK_SUPPORT_XTAL           1
+#define SOC_TWAI_BRP_MIN                    2
+#define SOC_TWAI_BRP_MAX                    32768
+#define SOC_TWAI_SUPPORTS_RX_STATUS         1
+#define SOC_TWAI_SUPPORT_SLEEP_RETENTION    1
 
 /*-------------------------- eFuse CAPS----------------------------*/
 #define SOC_EFUSE_DIS_PAD_JTAG 1
@@ -548,16 +556,21 @@
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
 #define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
 
-#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL            (1)      /*!< Support LP_PLL clock as the LP_FAST clock source */
+#define SOC_CLK_LP_FAST_SUPPORT_LP_PLL            (1)     /*!< Support LP_PLL clock as the LP_FAST clock source */
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2           (1)     /*!< Support XTAL_D2 clock as the LP_FAST clock source */
 #define SOC_MODEM_CLOCK_IS_INDEPENDENT            (1)
 
 #define SOC_RCC_IS_INDEPENDENT                    1       /*!< Reset and Clock Control is independent, thanks to the PCR registers */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                   (1)
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                   (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM                    (1)
+#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION        (1)
+#define SOC_TEMPERATURE_SENSOR_UNDER_PD_TOP_DOMAIN            (1)
 
 /*--------------------------------- RNG CAPS --------------------------------------------*/
 #define SOC_RNG_CLOCK_IS_INDEPENDENT                          (1)
@@ -571,3 +584,6 @@
 #define SOC_BLE_POWER_CONTROL_SUPPORTED (1)    /*!< Support Bluetooth Power Control */
 #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1)    /*!< Support multiple connections optimization */
 #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED  (1)    /*!< Support For BLE Periodic Adv Enhancements */
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
diff --git a/components/soc/esp32h2/include/soc/spi_mem_reg.h b/components/soc/esp32h2/include/soc/spi_mem_reg.h
deleted file mode 100644
index adb74b0e0b5..00000000000
--- a/components/soc/esp32h2/include/soc/spi_mem_reg.h
+++ /dev/null
@@ -1,3085 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
-/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (BIT(31))
-#define SPI_MEM_FLASH_READ_V  0x1
-#define SPI_MEM_FLASH_READ_S  31
-/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
-bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (BIT(30))
-#define SPI_MEM_FLASH_WREN_V  0x1
-#define SPI_MEM_FLASH_WREN_S  30
-/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Write flash disable. Write disable command will be sent when the bit is set. The
- bit will be cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
-#define SPI_MEM_FLASH_WRDI_V  0x1
-#define SPI_MEM_FLASH_WRDI_S  29
-/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
-e cleared once the operation done. 1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (BIT(28))
-#define SPI_MEM_FLASH_RDID_V  0x1
-#define SPI_MEM_FLASH_RDID_S  28
-/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Read status register-1.  Read status operation will be triggered when the bit is
- set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
-#define SPI_MEM_FLASH_RDSR_V  0x1
-#define SPI_MEM_FLASH_RDSR_S  27
-/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write status register enable.   Write status operation  will be triggered when t
-he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
-ble..*/
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
-#define SPI_MEM_FLASH_WRSR_V  0x1
-#define SPI_MEM_FLASH_WRSR_S  26
-/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
-tion  will be triggered when the bit is set. The bit will be cleared once the op
-eration done .1: enable 0: disable..*/
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (BIT(25))
-#define SPI_MEM_FLASH_PP_V  0x1
-#define SPI_MEM_FLASH_PP_S  25
-/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
-is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (BIT(24))
-#define SPI_MEM_FLASH_SE_V  0x1
-#define SPI_MEM_FLASH_SE_S  24
-/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
- is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (BIT(23))
-#define SPI_MEM_FLASH_BE_V  0x1
-#define SPI_MEM_FLASH_BE_S  23
-/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (BIT(22))
-#define SPI_MEM_FLASH_CE_V  0x1
-#define SPI_MEM_FLASH_CE_S  22
-/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
-. The bit will be cleared once the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (BIT(21))
-#define SPI_MEM_FLASH_DP_V  0x1
-#define SPI_MEM_FLASH_DP_S  21
-/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
-e or high performance mode and obtains the devices ID. The bit will be cleared o
-nce the operation done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (BIT(20))
-#define SPI_MEM_FLASH_RES_V  0x1
-#define SPI_MEM_FLASH_RES_S  20
-/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
-ion done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (BIT(19))
-#define SPI_MEM_FLASH_HPM_V  0x1
-#define SPI_MEM_FLASH_HPM_S  19
-/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operat
-ion will be triggered when the bit is set. The bit will be cleared once the oper
-ation done.1: enable 0: disable..*/
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (BIT(18))
-#define SPI_MEM_USR_V  0x1
-#define SPI_MEM_USR_S  18
-/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
-/*description: In user mode, it is set to indicate that program/erase operation will be trigger
-ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
-peration done.1: enable 0: disable..*/
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (BIT(17))
-#define SPI_MEM_FLASH_PE_V  0x1
-#define SPI_MEM_FLASH_PE_S  17
-/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
-/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation sta
-te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
-ate, 6:write data state, 7: done state, 8: read data end state..*/
-#define SPI_MEM_SLV_ST    0x0000000F
-#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
-#define SPI_MEM_SLV_ST_V  0xF
-#define SPI_MEM_SLV_ST_S  4
-/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
-, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
-nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
-#define SPI_MEM_MST_ST    0x0000000F
-#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
-#define SPI_MEM_MST_ST_V  0xF
-#define SPI_MEM_MST_ST_S  0
-
-#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
-/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
-address, the bit24-bit31 are the byte length of a transfer..*/
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_S  0
-
-#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
-/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
-lways 1. 0: Others..*/
-#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
-/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are alway
-s 1. 0: Others..*/
-#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
-/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
-ble 0: disable..*/
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (BIT(24))
-#define SPI_MEM_FREAD_QIO_V  0x1
-#define SPI_MEM_FREAD_QIO_S  24
-/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
-ble 0: disable..*/
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (BIT(23))
-#define SPI_MEM_FREAD_DIO_V  0x1
-#define SPI_MEM_FREAD_DIO_S  23
-/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
-isable..*/
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (BIT(22))
-#define SPI_MEM_WRSR_2B_V  0x1
-#define SPI_MEM_WRSR_2B_S  22
-/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (BIT(21))
-#define SPI_MEM_WP_REG_V  0x1
-#define SPI_MEM_WP_REG_S  21
-/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
-#define SPI_MEM_FREAD_QUAD_V  0x1
-#define SPI_MEM_FREAD_QUAD_S  20
-/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (BIT(19))
-#define SPI_MEM_D_POL_V  0x1
-#define SPI_MEM_D_POL_S  19
-/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (BIT(18))
-#define SPI_MEM_Q_POL_V  0x1
-#define SPI_MEM_Q_POL_S  18
-/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-spi_mem_flash_res bit. 1: enable 0: disable..*/
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (BIT(15))
-#define SPI_MEM_RESANDRES_V  0x1
-#define SPI_MEM_RESANDRES_S  15
-/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
-#define SPI_MEM_FREAD_DUAL_V  0x1
-#define SPI_MEM_FREAD_DUAL_S  14
-/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
-UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
-#define SPI_MEM_FASTRD_MODE_V  0x1
-#define SPI_MEM_FASTRD_MODE_S  13
-/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
-e.*/
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
-#define SPI_MEM_TX_CRC_EN_V  0x1
-#define SPI_MEM_TX_CRC_EN_S  11
-/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
-e low..*/
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_V  0x1
-#define SPI_MEM_FCS_CRC_EN_S  10
-/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (BIT(9))
-#define SPI_MEM_FCMD_OCT_V  0x1
-#define SPI_MEM_FCMD_OCT_S  9
-/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
-#define SPI_MEM_FCMD_QUAD_V  0x1
-#define SPI_MEM_FCMD_QUAD_S  8
-/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (BIT(6))
-#define SPI_MEM_FADDR_OCT_V  0x1
-#define SPI_MEM_FADDR_OCT_S  6
-/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (BIT(5))
-#define SPI_MEM_FDIN_OCT_V  0x1
-#define SPI_MEM_FDIN_OCT_S  5
-/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (BIT(4))
-#define SPI_MEM_FDOUT_OCT_V  0x1
-#define SPI_MEM_FDOUT_OCT_S  4
-/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
-is output by the MSPI controller in the second half part of dummy phase. It is u
-sed to pre-drive flash..*/
-#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_M  (BIT(3))
-#define SPI_MEM_FDUMMY_WOUT_V  0x1
-#define SPI_MEM_FDUMMY_WOUT_S  3
-/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
-s output by the MSPI controller in the first half part of dummy phase. It is use
-d to mask invalid SPI_DQS in the half part of dummy phase..*/
-#define SPI_MEM_FDUMMY_RIN    (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_M  (BIT(2))
-#define SPI_MEM_FDUMMY_RIN_V  0x1
-#define SPI_MEM_FDUMMY_RIN_S  2
-/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_IO[7:0] is output by the MSPI controller..*/
-#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
-/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
-vel of SPI_DQS is output by the MSPI controller..*/
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
-
-#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
-/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
- send signals to AXI. Set this bit to reset these FIFO..*/
-#define SPI_MEM_TXFIFO_RST    (BIT(31))
-#define SPI_MEM_TXFIFO_RST_M  (BIT(31))
-#define SPI_MEM_TXFIFO_RST_V  0x1
-#define SPI_MEM_TXFIFO_RST_S  31
-/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
- receive signals from AXI.  Set this bit to reset these FIFO..*/
-#define SPI_MEM_RXFIFO_RST    (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
-#define SPI_MEM_RXFIFO_RST_V  0x1
-#define SPI_MEM_RXFIFO_RST_S  30
-/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
-bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
-in  tx_bus_fifo_l2..*/
-#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_M  (BIT(29))
-#define SPI_MEM_FAST_WRITE_EN_V  0x1
-#define SPI_MEM_FAST_WRITE_EN_S  29
-/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
-the same time..*/
-#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_M  (BIT(28))
-#define SPI_MEM_DUAL_RAM_EN_V  0x1
-#define SPI_MEM_DUAL_RAM_EN_S  28
-/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
-cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
-ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
-cessed at the same time..*/
-#define SPI_MEM_RAM0_EN    (BIT(27))
-#define SPI_MEM_RAM0_EN_M  (BIT(27))
-#define SPI_MEM_RAM0_EN_V  0x1
-#define SPI_MEM_RAM0_EN_S  27
-/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Write Splice-transfer..*/
-#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_M  (BIT(26))
-#define SPI_MEM_AW_SPLICE_EN_V  0x1
-#define SPI_MEM_AW_SPLICE_EN_S  26
-/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to enable AXI Read Splice-transfer..*/
-#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_M  (BIT(25))
-#define SPI_MEM_AR_SPLICE_EN_V  0x1
-#define SPI_MEM_AR_SPLICE_EN_S  25
-/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
- when there is a ECC error in AXI read data. The ECC error information is record
-ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
-#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
-#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x1
-#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
-/* SPI_MEM_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */
-/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
-eply AXI read data to AXI bus when all the read data is available..*/
-#define SPI_MEM_AXI_RDATA_BACK_FAST    (BIT(23))
-#define SPI_MEM_AXI_RDATA_BACK_FAST_M  (BIT(23))
-#define SPI_MEM_AXI_RDATA_BACK_FAST_V  0x1
-#define SPI_MEM_AXI_RDATA_BACK_FAST_S  23
-/* SPI_MEM_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
-#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
-#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
-#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V  0x1
-#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S  22
-/* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
-y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
-#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
-#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
-#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_V  0x1
-#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_S  21
-/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
-/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
-12) SPI_CLK cycles..*/
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
-#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
-/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on..*/
-#define SPI_MEM_CLK_MODE    0x00000003
-#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
-#define SPI_MEM_CLK_MODE_V  0x3
-#define SPI_MEM_CLK_MODE_S  0
-
-#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
-/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (BIT(31))
-#define SPI_MEM_SYNC_RESET_V  0x1
-#define SPI_MEM_SYNC_RESET_S  31
-/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
- clock cycles..*/
-#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_SPLIT_TRANS_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
-fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
-whether there is an ECC region or not..*/
-#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
-#define SPI_MEM_SPLIT_TRANS_EN_V  0x1
-#define SPI_MEM_SPLIT_TRANS_EN_S  24
-/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses flash..*/
-#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
-#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */
-/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
-hen accesses flash..*/
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
- mode when accessed flash..*/
-#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
-#define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
-#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
-#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
-/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
-/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
-th SPI_MEM_CS_HOLD bit..*/
-#define SPI_MEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
-#define SPI_MEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
-/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
-M_CS_SETUP bit..*/
-#define SPI_MEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
-#define SPI_MEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_CS_SETUP_TIME_S  0
-
-#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
-/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
- clock..*/
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
-/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
- system/(spi_mem_clkcnt_N+1).*/
-#define SPI_MEM_CLKCNT_N    0x000000FF
-#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
-#define SPI_MEM_CLKCNT_N_V  0xFF
-#define SPI_MEM_CLKCNT_N_S  16
-/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define SPI_MEM_CLKCNT_H    0x000000FF
-#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
-#define SPI_MEM_CLKCNT_H_V  0xFF
-#define SPI_MEM_CLKCNT_H_S  8
-/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
-#define SPI_MEM_CLKCNT_L    0x000000FF
-#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
-#define SPI_MEM_CLKCNT_L_V  0xFF
-#define SPI_MEM_CLKCNT_L_S  0
-
-#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
-/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation..*/
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (BIT(31))
-#define SPI_MEM_USR_COMMAND_V  0x1
-#define SPI_MEM_USR_COMMAND_S  31
-/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation..*/
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (BIT(30))
-#define SPI_MEM_USR_ADDR_V  0x1
-#define SPI_MEM_USR_ADDR_S  30
-/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation..*/
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (BIT(29))
-#define SPI_MEM_USR_DUMMY_V  0x1
-#define SPI_MEM_USR_DUMMY_S  29
-/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation..*/
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (BIT(28))
-#define SPI_MEM_USR_MISO_V  0x1
-#define SPI_MEM_USR_MISO_S  28
-/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation..*/
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (BIT(27))
-#define SPI_MEM_USR_MOSI_V  0x1
-#define SPI_MEM_USR_MOSI_S  27
-/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable..*/
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
-1: enable 0: disable..*/
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
-: enable 0: disable..*/
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 4 signals..*/
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
-#define SPI_MEM_FWRITE_QIO_V  0x1
-#define SPI_MEM_FWRITE_QIO_S  15
-/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the write operations address phase and read-data phase apply 2 signals..*/
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
-#define SPI_MEM_FWRITE_DIO_V  0x1
-#define SPI_MEM_FWRITE_DIO_S  14
-/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals.*/
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_V  0x1
-#define SPI_MEM_FWRITE_QUAD_S  13
-/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals.*/
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_V  0x1
-#define SPI_MEM_FWRITE_DUAL_S  12
-/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_V  0x1
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
-#define SPI_MEM_CS_SETUP    (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (BIT(7))
-#define SPI_MEM_CS_SETUP_V  0x1
-#define SPI_MEM_CS_SETUP_S  7
-/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
-#define SPI_MEM_CS_HOLD    (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (BIT(6))
-#define SPI_MEM_CS_HOLD_V  0x1
-#define SPI_MEM_CS_HOLD_S  6
-
-#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
-/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
-/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
-/*description: SPI0 USR_CMD read or write data byte length -1.*/
-#define SPI_MEM_USR_DBYTELEN    0x00000007
-#define SPI_MEM_USR_DBYTELEN_M  ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S))
-#define SPI_MEM_USR_DBYTELEN_V  0x7
-#define SPI_MEM_USR_DBYTELEN_S  6
-/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
-/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
-cle_num-1)..*/
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
-/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
-#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
-/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command..*/
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
-#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
-#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-
-#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
-/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
-
-#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
-/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
-
-#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
-/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
-it..*/
-#define SPI_MEM_WB_MODE    0x000000FF
-#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
-#define SPI_MEM_WB_MODE_V  0xFF
-#define SPI_MEM_WB_MODE_S  16
-/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
-#define SPI_MEM_STATUS    0x0000FFFF
-#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
-#define SPI_MEM_STATUS_V  0xFFFF
-#define SPI_MEM_STATUS_S  0
-
-#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
-/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: SPI_CS line keep low when the bit is set..*/
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
-/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_V  0x1
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0,  sram is connected to SUBPINs..*/
-#define SPI_MEM_SSUB_PIN    (BIT(8))
-#define SPI_MEM_SSUB_PIN_M  (BIT(8))
-#define SPI_MEM_SSUB_PIN_V  0x1
-#define SPI_MEM_SSUB_PIN_S  8
-/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0,  flash is connected to SUBPINs..*/
-#define SPI_MEM_FSUB_PIN    (BIT(7))
-#define SPI_MEM_FSUB_PIN_M  (BIT(7))
-#define SPI_MEM_FSUB_PIN_V  0x1
-#define SPI_MEM_FSUB_PIN_S  7
-/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
-evice, such as flash, external RAM and so on..*/
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (BIT(1))
-#define SPI_MEM_CS1_DIS_V  0x1
-#define SPI_MEM_CS1_DIS_S  1
-/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
-evice, such as flash, external RAM and so on..*/
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (BIT(0))
-#define SPI_MEM_CS0_DIS_V  0x1
-#define SPI_MEM_CS0_DIS_S  0
-
-#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
-/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: For SPI1, the value of crc32..*/
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_S  0
-
-#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
-/* SPI_MEM_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
-_ERR will be replied to BRESP/RRESP..*/
-#define SPI_MEM_CLOSE_AXI_INF_EN    (BIT(31))
-#define SPI_MEM_CLOSE_AXI_INF_EN_M  (BIT(31))
-#define SPI_MEM_CLOSE_AXI_INF_EN_V  0x1
-#define SPI_MEM_CLOSE_AXI_INF_EN_S  31
-/* SPI_MEM_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: Set this bit to check AXI read/write the same address region..*/
-#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
-#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
-#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V  0x1
-#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S  30
-/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_qio..*/
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
-#define SPI_MEM_FADDR_QUAD_V  0x1
-#define SPI_MEM_FADDR_QUAD_S  8
-/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
-e same with spi_mem_fread_qio..*/
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_V  0x1
-#define SPI_MEM_FDOUT_QUAD_S  7
-/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
- same with spi_mem_fread_qio..*/
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
-#define SPI_MEM_FDIN_QUAD_V  0x1
-#define SPI_MEM_FDIN_QUAD_S  6
-/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
- the same with spi_mem_fread_dio..*/
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
-#define SPI_MEM_FADDR_DUAL_V  0x1
-#define SPI_MEM_FADDR_DUAL_S  5
-/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
- same with spi_mem_fread_dio..*/
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_V  0x1
-#define SPI_MEM_FDOUT_DUAL_S  4
-/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
-same with spi_mem_fread_dio..*/
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
-#define SPI_MEM_FDIN_DUAL_V  0x1
-#define SPI_MEM_FDIN_DUAL_S  3
-/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
-#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
-/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
-/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
-#define SPI_MEM_AXI_REQ_EN    (BIT(0))
-#define SPI_MEM_AXI_REQ_EN_M  (BIT(0))
-#define SPI_MEM_AXI_REQ_EN_V  0x1
-#define SPI_MEM_AXI_REQ_EN_S  0
-
-#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
-/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
-e. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
-/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: reserved.*/
-#define SPI_MEM_SRAM_OCT    (BIT(21))
-#define SPI_MEM_SRAM_OCT_M  (BIT(21))
-#define SPI_MEM_SRAM_OCT_V  0x1
-#define SPI_MEM_SRAM_OCT_S  21
-/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
-#define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
-/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
-he register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
-#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
-/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
-. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
-/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode cache read external RAM for user define comma
-nd..*/
-#define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
-/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
- operations..*/
-#define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
-#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
-#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
-#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
-/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
-e operations..*/
-#define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
-#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
-#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
-#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
-/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
-le.*/
-#define SPI_MEM_USR_SRAM_QIO    (BIT(2))
-#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
-#define SPI_MEM_USR_SRAM_QIO_V  0x1
-#define SPI_MEM_USR_SRAM_QIO_S  2
-/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
-le.*/
-#define SPI_MEM_USR_SRAM_DIO    (BIT(1))
-#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
-#define SPI_MEM_USR_SRAM_DIO_V  0x1
-#define SPI_MEM_USR_SRAM_DIO_S  1
-/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
-able, 0:disable..*/
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
-
-#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
-/* SPI_MEM_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
-] are always 1. 0: Others..*/
-#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
-#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
-#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_S  31
-/* SPI_MEM_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
-e always 1. 0: Others..*/
-#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
-#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
-#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_V  0x1
-#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_S  30
-/* SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_IO[7:0] is output by the MSPI controller..*/
-#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
-#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
-#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
-#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_S  25
-/* SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
- the level of SPI_DQS is output by the MSPI controller..*/
-#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
-#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
-#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
-#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
-/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
-the signal level of SPI bus is output by the MSPI controller..*/
-#define SPI_MEM_SDUMMY_WOUT    (BIT(23))
-#define SPI_MEM_SDUMMY_WOUT_M  (BIT(23))
-#define SPI_MEM_SDUMMY_WOUT_V  0x1
-#define SPI_MEM_SDUMMY_WOUT_S  23
-/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
-he signal level of SPI bus is output by the MSPI controller..*/
-#define SPI_MEM_SDUMMY_RIN    (BIT(22))
-#define SPI_MEM_SDUMMY_RIN_M  (BIT(22))
-#define SPI_MEM_SDUMMY_RIN_V  0x1
-#define SPI_MEM_SDUMMY_RIN_S  22
-/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SCMD_OCT    (BIT(21))
-#define SPI_MEM_SCMD_OCT_M  (BIT(21))
-#define SPI_MEM_SCMD_OCT_V  0x1
-#define SPI_MEM_SCMD_OCT_S  21
-/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SADDR_OCT    (BIT(20))
-#define SPI_MEM_SADDR_OCT_M  (BIT(20))
-#define SPI_MEM_SADDR_OCT_V  0x1
-#define SPI_MEM_SADDR_OCT_S  20
-/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SDOUT_OCT    (BIT(19))
-#define SPI_MEM_SDOUT_OCT_M  (BIT(19))
-#define SPI_MEM_SDOUT_OCT_V  0x1
-#define SPI_MEM_SDOUT_OCT_S  19
-/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
-#define SPI_MEM_SDIN_OCT    (BIT(18))
-#define SPI_MEM_SDIN_OCT_M  (BIT(18))
-#define SPI_MEM_SDIN_OCT_V  0x1
-#define SPI_MEM_SDIN_OCT_S  18
-/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SCMD_QUAD    (BIT(17))
-#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
-#define SPI_MEM_SCMD_QUAD_V  0x1
-#define SPI_MEM_SCMD_QUAD_S  17
-/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SADDR_QUAD    (BIT(16))
-#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
-#define SPI_MEM_SADDR_QUAD_V  0x1
-#define SPI_MEM_SADDR_QUAD_S  16
-/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SDOUT_QUAD    (BIT(15))
-#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
-#define SPI_MEM_SDOUT_QUAD_V  0x1
-#define SPI_MEM_SDOUT_QUAD_S  15
-/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_qio..*/
-#define SPI_MEM_SDIN_QUAD    (BIT(14))
-#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
-#define SPI_MEM_SDIN_QUAD_V  0x1
-#define SPI_MEM_SDIN_QUAD_S  14
-/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
- bit is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SADDR_DUAL    (BIT(12))
-#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
-#define SPI_MEM_SADDR_DUAL_V  0x1
-#define SPI_MEM_SADDR_DUAL_S  12
-/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
-t is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SDOUT_DUAL    (BIT(11))
-#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
-#define SPI_MEM_SDOUT_DUAL_V  0x1
-#define SPI_MEM_SDOUT_DUAL_S  11
-/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
- is the same with spi_mem_usr_sram_dio..*/
-#define SPI_MEM_SDIN_DUAL    (BIT(10))
-#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
-#define SPI_MEM_SDIN_DUAL_V  0x1
-#define SPI_MEM_SDIN_DUAL_S  10
-/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */
-/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
-_mode bit..*/
-#define SPI_MEM_SWB_MODE    0x000000FF
-#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
-#define SPI_MEM_SWB_MODE_V  0xFF
-#define SPI_MEM_SWB_MODE_S  2
-/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is always on..*/
-#define SPI_MEM_SCLK_MODE    0x00000003
-#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
-#define SPI_MEM_SCLK_MODE_V  0x3
-#define SPI_MEM_SCLK_MODE_S  0
-
-#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
-/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
- sram. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
-/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the read command value of command phase
- for sram..*/
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
-
-#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
-/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
- The register value shall be (bit_num-1)..*/
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
-/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: For SPI0,When cache mode is enable it is the write command value of command phas
-e for sram..*/
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
-
-#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
-/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_c
-lk is divided from system clock..*/
-#define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
-/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
-lk frequency is system/(spi_mem_clkcnt_N+1).*/
-#define SPI_MEM_SCLKCNT_N    0x000000FF
-#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
-#define SPI_MEM_SCLKCNT_N_V  0xFF
-#define SPI_MEM_SCLKCNT_N_S  16
-/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
-#define SPI_MEM_SCLKCNT_H    0x000000FF
-#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
-#define SPI_MEM_SCLKCNT_H_V  0xFF
-#define SPI_MEM_SCLKCNT_H_S  8
-/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
-#define SPI_MEM_SCLKCNT_L    0x000000FF
-#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
-#define SPI_MEM_SCLKCNT_L_V  0xFF
-#define SPI_MEM_SCLKCNT_L_S  0
-
-#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
-/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
-/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
-#define SPI_MEM_LOCK_DELAY_TIME    0x0000001F
-#define SPI_MEM_LOCK_DELAY_TIME_M  ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S))
-#define SPI_MEM_LOCK_DELAY_TIME_V  0x1F
-#define SPI_MEM_LOCK_DELAY_TIME_S  7
-
-#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
-/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF0    0xFFFFFFFF
-#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
-#define SPI_MEM_BUF0_V  0xFFFFFFFF
-#define SPI_MEM_BUF0_S  0
-
-#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
-/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF1    0xFFFFFFFF
-#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
-#define SPI_MEM_BUF1_V  0xFFFFFFFF
-#define SPI_MEM_BUF1_S  0
-
-#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
-/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF2    0xFFFFFFFF
-#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
-#define SPI_MEM_BUF2_V  0xFFFFFFFF
-#define SPI_MEM_BUF2_S  0
-
-#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
-/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF3    0xFFFFFFFF
-#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
-#define SPI_MEM_BUF3_V  0xFFFFFFFF
-#define SPI_MEM_BUF3_S  0
-
-#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
-/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF4    0xFFFFFFFF
-#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
-#define SPI_MEM_BUF4_V  0xFFFFFFFF
-#define SPI_MEM_BUF4_S  0
-
-#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
-/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF5    0xFFFFFFFF
-#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
-#define SPI_MEM_BUF5_V  0xFFFFFFFF
-#define SPI_MEM_BUF5_S  0
-
-#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
-/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF6    0xFFFFFFFF
-#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
-#define SPI_MEM_BUF6_V  0xFFFFFFFF
-#define SPI_MEM_BUF6_S  0
-
-#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
-/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF7    0xFFFFFFFF
-#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
-#define SPI_MEM_BUF7_V  0xFFFFFFFF
-#define SPI_MEM_BUF7_S  0
-
-#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
-/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF8    0xFFFFFFFF
-#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
-#define SPI_MEM_BUF8_V  0xFFFFFFFF
-#define SPI_MEM_BUF8_S  0
-
-#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
-/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF9    0xFFFFFFFF
-#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
-#define SPI_MEM_BUF9_V  0xFFFFFFFF
-#define SPI_MEM_BUF9_S  0
-
-#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
-/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF10    0xFFFFFFFF
-#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
-#define SPI_MEM_BUF10_V  0xFFFFFFFF
-#define SPI_MEM_BUF10_S  0
-
-#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
-/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF11    0xFFFFFFFF
-#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
-#define SPI_MEM_BUF11_V  0xFFFFFFFF
-#define SPI_MEM_BUF11_S  0
-
-#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
-/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF12    0xFFFFFFFF
-#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
-#define SPI_MEM_BUF12_V  0xFFFFFFFF
-#define SPI_MEM_BUF12_S  0
-
-#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
-/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF13    0xFFFFFFFF
-#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
-#define SPI_MEM_BUF13_V  0xFFFFFFFF
-#define SPI_MEM_BUF13_S  0
-
-#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
-/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF14    0xFFFFFFFF
-#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
-#define SPI_MEM_BUF14_V  0xFFFFFFFF
-#define SPI_MEM_BUF14_S  0
-
-#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
-/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF15    0xFFFFFFFF
-#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
-#define SPI_MEM_BUF15_V  0xFFFFFFFF
-#define SPI_MEM_BUF15_S  0
-
-#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
-/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
-/*description: The command value to wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_CMD    0x0000FFFF
-#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
-#define SPI_MEM_WAITI_CMD_V  0xFFFF
-#define SPI_MEM_WAITI_CMD_S  16
-/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
-/*description: The dummy cycle length when wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is
- 8..*/
-#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_M  (BIT(9))
-#define SPI_MEM_WAITI_CMD_2B_V  0x1
-#define SPI_MEM_WAITI_CMD_2B_S  9
-/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI
-_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
-SPI_MEM_WAITI_ADDR_EN is cleared..*/
-#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S))
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x3
-#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
-/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out ad
-dress in RDSR or read SUS command transfer..*/
-#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_M  (BIT(2))
-#define SPI_MEM_WAITI_ADDR_EN_V  0x1
-#define SPI_MEM_WAITI_ADDR_EN_S  2
-/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The dummy phase enable when wait flash idle (RDSR).*/
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_V  0x1
-#define SPI_MEM_WAITI_DUMMY_S  1
-/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
- Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
-Suspend/Resume are not supported..*/
-#define SPI_MEM_WAITI_EN    (BIT(0))
-#define SPI_MEM_WAITI_EN_M  (BIT(0))
-#define SPI_MEM_WAITI_EN_V  0x1
-#define SPI_MEM_WAITI_EN_S  0
-
-#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
-/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
-/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
- it will be treated as check pass..*/
-#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
-#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
-#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
-#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
-/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
-s of flash. 0: Only need to check WIP is 0..*/
-#define SPI_MEM_PES_END_EN    (BIT(24))
-#define SPI_MEM_PES_END_EN_M  (BIT(24))
-#define SPI_MEM_PES_END_EN_V  0x1
-#define SPI_MEM_PES_END_EN_S  24
-/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
- of flash. 0: Only need to check WIP is 0..*/
-#define SPI_MEM_PER_END_EN    (BIT(23))
-#define SPI_MEM_PER_END_EN_M  (BIT(23))
-#define SPI_MEM_PER_END_EN_V  0x1
-#define SPI_MEM_PER_END_EN_S  23
-/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
-hen check flash SUS/SUS1/SUS2 status bit.*/
-#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
-#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
-#define SPI_MEM_FMEM_RD_SUS_2B_S  22
-/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
-/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
-status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
-out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
-2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
-#define SPI_MEM_PESR_END_MSK    0x0000FFFF
-#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
-#define SPI_MEM_PESR_END_MSK_V  0xFFFF
-#define SPI_MEM_PESR_END_MSK_S  6
-/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable Auto-suspending function..*/
-#define SPI_MEM_FLASH_PES_EN    (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
-#define SPI_MEM_FLASH_PES_EN_V  0x1
-#define SPI_MEM_FLASH_PES_EN_S  5
-/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
-pplication should send PER after PES is done..*/
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (BIT(4))
-#define SPI_MEM_PES_PER_EN_V  0x1
-#define SPI_MEM_PES_PER_EN_S  4
-/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-program erase suspend command is sent. 0: SPI1 does not wait after program erase
- suspend command is sent..*/
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-program erase resume command is sent. 0: SPI1 does not wait after program erase
-resume command is sent..*/
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program erase suspend bit, program erase suspend operation will be triggered whe
-n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
-isable..*/
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (BIT(1))
-#define SPI_MEM_FLASH_PES_V  0x1
-#define SPI_MEM_FLASH_PES_S  1
-/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: program erase resume bit, program erase suspend operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: di
-sable..*/
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (BIT(0))
-#define SPI_MEM_FLASH_PER_V  0x1
-#define SPI_MEM_FLASH_PER_S  0
-
-#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
-/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
-/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
-/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
-..*/
-#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
-#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
-#define SPI_MEM_WAIT_PESR_COMMAND_S  16
-/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */
-/*description: Program/Erase suspend command..*/
-#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFF
-#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
-#define SPI_MEM_FLASH_PES_COMMAND_V  0xFFFF
-#define SPI_MEM_FLASH_PES_COMMAND_S  0
-
-#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
-/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */
-/*description: Program/Erase resume command..*/
-#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFF
-#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
-#define SPI_MEM_FLASH_PER_COMMAND_V  0xFFFF
-#define SPI_MEM_FLASH_PER_COMMAND_S  16
-/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng
-th of Program/Erase Suspend/Resume command is 8..*/
-#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_M  (BIT(15))
-#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x1
-#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
-/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
-#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
-#define SPI_MEM_SPI0_LOCK_EN_V  0x1
-#define SPI_MEM_SPI0_LOCK_EN_S  7
-/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
-#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PES_DLY_128_S  6
-/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
-#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
-#define SPI_MEM_FLASH_PER_DLY_128_S  5
-/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
-mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
-after DP command is sent..*/
-#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
-#define SPI_MEM_FLASH_DP_DLY_128_S  4
-/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after RES command is sent..*/
-#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
-#define SPI_MEM_FLASH_RES_DLY_128_S  3
-/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after HPM command is sent..*/
-#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
-#define SPI_MEM_FLASH_HPM_DLY_128_S  2
-/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
- SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
-#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
-#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
-#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
-/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The status of flash suspend, only used in SPI1..*/
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (BIT(0))
-#define SPI_MEM_FLASH_SUS_V  0x1
-#define SPI_MEM_FLASH_SUS_S  0
-
-#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
-/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
-/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
-/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
-#define SPI_MEM_ECC_ERR_INT_ENA_S  5
-/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ENA_S  4
-/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
-/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ENA_V  0x1
-#define SPI_MEM_WPE_END_INT_ENA_S  2
-/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_V  0x1
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_V  0x1
-#define SPI_MEM_PER_END_INT_ENA_S  0
-
-#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
-/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
-/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
-/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
-#define SPI_MEM_ECC_ERR_INT_CLR_S  5
-/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_MST_ST_END_INT_CLR_S  4
-/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
-/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_CLR_V  0x1
-#define SPI_MEM_WPE_END_INT_CLR_S  2
-/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_V  0x1
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_V  0x1
-#define SPI_MEM_PER_END_INT_CLR_S  0
-
-#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
-/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-chip is loosing power and RTC module sends out brown out close flash request to
-SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
- and MSPI returns to idle state. 0: Others..*/
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
- address is invalid by compared to MMU configuration. 0: Others..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
-ite flash request is received. 0: Others..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
-address is invalid by compared to MMU configuration. 0: Others..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
-/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
-is rejected. 0: Others..*/
-#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
-/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
-et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
- times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
-. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
-his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
-ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
-I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
-of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
-RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleare
-d, this bit will not be triggered..*/
-#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
-#define SPI_MEM_ECC_ERR_INT_RAW_S  5
-/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
-is changed from non idle state to idle state. 0: Others..*/
-#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_MST_ST_END_INT_RAW_S  4
-/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
-is changed from non idle state to idle state. It means that SPI_CS raises high.
-0: Others.*/
-#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
-/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
-E is sent and flash is already idle. 0: Others..*/
-#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_RAW_V  0x1
-#define SPI_MEM_WPE_END_INT_RAW_S  2
-/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
-mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_V  0x1
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
-mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_V  0x1
-#define SPI_MEM_PER_END_INT_RAW_S  0
-
-#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
-/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(10))
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ST_S  10
-/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
-/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
-/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
-#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
-/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
-#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
-#define SPI_MEM_PMS_REJECT_INT_ST_V  0x1
-#define SPI_MEM_PMS_REJECT_INT_ST_S  6
-/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
-#define SPI_MEM_ECC_ERR_INT_ST_V  0x1
-#define SPI_MEM_ECC_ERR_INT_ST_S  5
-/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
-#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
-#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
-#define SPI_MEM_MST_ST_END_INT_ST_S  4
-/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
-#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
-#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
-#define SPI_MEM_SLV_ST_END_INT_ST_S  3
-/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
-#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
-#define SPI_MEM_WPE_END_INT_ST_V  0x1
-#define SPI_MEM_WPE_END_INT_ST_S  2
-/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_V  0x1
-#define SPI_MEM_PES_END_INT_ST_S  1
-/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_V  0x1
-#define SPI_MEM_PER_END_INT_ST_S  0
-
-#define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
-/* SPI_MEM_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
-#define SPI_MEM_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_FMEM_HYPERBUS_CA_M  (BIT(30))
-#define SPI_MEM_FMEM_HYPERBUS_CA_V  0x1
-#define SPI_MEM_FMEM_HYPERBUS_CA_S  30
-/* SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
-..*/
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V  0x1
-#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S  29
-/* SPI_MEM_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
-#define SPI_MEM_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_FMEM_CLK_DIFF_INV_M  (BIT(28))
-#define SPI_MEM_FMEM_CLK_DIFF_INV_V  0x1
-#define SPI_MEM_FMEM_CLK_DIFF_INV_S  28
-/* SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S  27
-/* SPI_MEM_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define SPI_MEM_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_FMEM_DQS_CA_IN_M  (BIT(26))
-#define SPI_MEM_FMEM_DQS_CA_IN_V  0x1
-#define SPI_MEM_FMEM_DQS_CA_IN_S  26
-/* SPI_MEM_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define SPI_MEM_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_FMEM_CLK_DIFF_EN_M  (BIT(24))
-#define SPI_MEM_FMEM_CLK_DIFF_EN_V  0x1
-#define SPI_MEM_FMEM_CLK_DIFF_EN_S  24
-/* SPI_MEM_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define SPI_MEM_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_V  0x1
-#define SPI_MEM_FMEM_DDR_DQS_LOOP_S  21
-/* SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD    0x0000007F
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_FMEM_USR_DDR_DQS_THD_S))
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V  0x7F
-#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S  14
-/* SPI_MEM_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to flash..*/
-#define SPI_MEM_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_MEM_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define SPI_MEM_FMEM_RX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_FMEM_RX_DDR_MSK_EN_S  13
-/* SPI_MEM_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to flash..*/
-#define SPI_MEM_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_MEM_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define SPI_MEM_FMEM_TX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_FMEM_TX_DDR_MSK_EN_S  12
-/* SPI_MEM_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the panda device..*/
-#define SPI_MEM_FMEM_OUTMINBYTELEN    0x0000007F
-#define SPI_MEM_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_FMEM_OUTMINBYTELEN_S))
-#define SPI_MEM_FMEM_OUTMINBYTELEN_V  0x7F
-#define SPI_MEM_FMEM_OUTMINBYTELEN_S  5
-/* SPI_MEM_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define SPI_MEM_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_FMEM_DDR_CMD_DIS_M  (BIT(4))
-#define SPI_MEM_FMEM_DDR_CMD_DIS_V  0x1
-#define SPI_MEM_FMEM_DDR_CMD_DIS_S  4
-/* SPI_MEM_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define SPI_MEM_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_V  0x1
-#define SPI_MEM_FMEM_DDR_WDAT_SWP_S  3
-/* SPI_MEM_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define SPI_MEM_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_V  0x1
-#define SPI_MEM_FMEM_DDR_RDAT_SWP_S  2
-/* SPI_MEM_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define SPI_MEM_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_FMEM_VAR_DUMMY_M  (BIT(1))
-#define SPI_MEM_FMEM_VAR_DUMMY_V  0x1
-#define SPI_MEM_FMEM_VAR_DUMMY_S  1
-/* SPI_MEM_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define SPI_MEM_FMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_FMEM_DDR_EN_M  (BIT(0))
-#define SPI_MEM_FMEM_DDR_EN_V  0x1
-#define SPI_MEM_FMEM_DDR_EN_S  0
-
-#define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD8)
-/* SPI_MEM_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
-]}..*/
-#define SPI_MEM_SMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_SMEM_HYPERBUS_CA_M  (BIT(30))
-#define SPI_MEM_SMEM_HYPERBUS_CA_V  0x1
-#define SPI_MEM_SMEM_HYPERBUS_CA_S  30
-/* SPI_MEM_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
-, 1'b0}..*/
-#define SPI_MEM_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define SPI_MEM_SMEM_OCTA_RAM_ADDR_V  0x1
-#define SPI_MEM_SMEM_OCTA_RAM_ADDR_S  29
-/* SPI_MEM_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
-#define SPI_MEM_SMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_SMEM_CLK_DIFF_INV_M  (BIT(28))
-#define SPI_MEM_SMEM_CLK_DIFF_INV_V  0x1
-#define SPI_MEM_SMEM_CLK_DIFF_INV_S  28
-/* SPI_MEM_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S  27
-/* SPI_MEM_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define SPI_MEM_SMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_SMEM_DQS_CA_IN_M  (BIT(26))
-#define SPI_MEM_SMEM_DQS_CA_IN_V  0x1
-#define SPI_MEM_SMEM_DQS_CA_IN_S  26
-/* SPI_MEM_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define SPI_MEM_SMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_SMEM_CLK_DIFF_EN_M  (BIT(24))
-#define SPI_MEM_SMEM_CLK_DIFF_EN_V  0x1
-#define SPI_MEM_SMEM_CLK_DIFF_EN_S  24
-/* SPI_MEM_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
-0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
-SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
-egative edge of SPI_DQS..*/
-#define SPI_MEM_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_SMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define SPI_MEM_SMEM_DDR_DQS_LOOP_V  0x1
-#define SPI_MEM_SMEM_DDR_DQS_LOOP_S  21
-/* SPI_MEM_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI clock..*/
-#define SPI_MEM_SMEM_USR_DDR_DQS_THD    0x0000007F
-#define SPI_MEM_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SMEM_USR_DDR_DQS_THD_S))
-#define SPI_MEM_SMEM_USR_DDR_DQS_THD_V  0x7F
-#define SPI_MEM_SMEM_USR_DDR_DQS_THD_S  14
-/* SPI_MEM_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
-accesses to external RAM..*/
-#define SPI_MEM_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_MEM_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define SPI_MEM_SMEM_RX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SMEM_RX_DDR_MSK_EN_S  13
-/* SPI_MEM_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
- accesses to external RAM..*/
-#define SPI_MEM_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_MEM_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define SPI_MEM_SMEM_TX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SMEM_TX_DDR_MSK_EN_S  12
-/* SPI_MEM_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the DDR psram..*/
-#define SPI_MEM_SMEM_OUTMINBYTELEN    0x0000007F
-#define SPI_MEM_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SMEM_OUTMINBYTELEN_S))
-#define SPI_MEM_SMEM_OUTMINBYTELEN_V  0x7F
-#define SPI_MEM_SMEM_OUTMINBYTELEN_S  5
-/* SPI_MEM_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define SPI_MEM_SMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_SMEM_DDR_CMD_DIS_M  (BIT(4))
-#define SPI_MEM_SMEM_DDR_CMD_DIS_V  0x1
-#define SPI_MEM_SMEM_DDR_CMD_DIS_S  4
-/* SPI_MEM_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
-#define SPI_MEM_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_SMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define SPI_MEM_SMEM_DDR_WDAT_SWP_V  0x1
-#define SPI_MEM_SMEM_DDR_WDAT_SWP_S  3
-/* SPI_MEM_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
-#define SPI_MEM_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_SMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define SPI_MEM_SMEM_DDR_RDAT_SWP_V  0x1
-#define SPI_MEM_SMEM_DDR_RDAT_SWP_S  2
-/* SPI_MEM_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
-#define SPI_MEM_SMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_SMEM_VAR_DUMMY_M  (BIT(1))
-#define SPI_MEM_SMEM_VAR_DUMMY_V  0x1
-#define SPI_MEM_SMEM_VAR_DUMMY_S  1
-/* SPI_MEM_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0 in SDR mode.*/
-#define SPI_MEM_SMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_SMEM_DDR_EN_M  (BIT(0))
-#define SPI_MEM_SMEM_DDR_EN_V  0x1
-#define SPI_MEM_SMEM_DDR_EN_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x100)
-/* SPI_MEM_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_FMEM_PMS0_ECC    (BIT(2))
-#define SPI_MEM_FMEM_PMS0_ECC_M  (BIT(2))
-#define SPI_MEM_FMEM_PMS0_ECC_V  0x1
-#define SPI_MEM_FMEM_PMS0_ECC_S  2
-/* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_MEM_FMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_FMEM_PMS0_WR_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS0_WR_ATTR_S  1
-/* SPI_MEM_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_MEM_FMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_FMEM_PMS0_RD_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS0_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x104)
-/* SPI_MEM_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_FMEM_PMS1_ECC    (BIT(2))
-#define SPI_MEM_FMEM_PMS1_ECC_M  (BIT(2))
-#define SPI_MEM_FMEM_PMS1_ECC_V  0x1
-#define SPI_MEM_FMEM_PMS1_ECC_S  2
-/* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_MEM_FMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_FMEM_PMS1_WR_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS1_WR_ATTR_S  1
-/* SPI_MEM_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_MEM_FMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_FMEM_PMS1_RD_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS1_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x108)
-/* SPI_MEM_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_FMEM_PMS2_ECC    (BIT(2))
-#define SPI_MEM_FMEM_PMS2_ECC_M  (BIT(2))
-#define SPI_MEM_FMEM_PMS2_ECC_V  0x1
-#define SPI_MEM_FMEM_PMS2_ECC_S  2
-/* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_MEM_FMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_FMEM_PMS2_WR_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS2_WR_ATTR_S  1
-/* SPI_MEM_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_MEM_FMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_FMEM_PMS2_RD_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS2_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10C)
-/* SPI_MEM_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
- ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
-PMS$n_SIZE_REG..*/
-#define SPI_MEM_FMEM_PMS3_ECC    (BIT(2))
-#define SPI_MEM_FMEM_PMS3_ECC_M  (BIT(2))
-#define SPI_MEM_FMEM_PMS3_ECC_V  0x1
-#define SPI_MEM_FMEM_PMS3_ECC_S  2
-/* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_MEM_FMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_FMEM_PMS3_WR_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS3_WR_ATTR_S  1
-/* SPI_MEM_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_FMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_MEM_FMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_FMEM_PMS3_RD_ATTR_V  0x1
-#define SPI_MEM_FMEM_PMS3_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x110)
-/* SPI_MEM_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: SPI1 flash ACE section $n start address value.*/
-#define SPI_MEM_FMEM_PMS0_ADDR_S    0x03FFFFFF
-#define SPI_MEM_FMEM_PMS0_ADDR_S_M  ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S))
-#define SPI_MEM_FMEM_PMS0_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_FMEM_PMS0_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x114)
-/* SPI_MEM_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
-/*description: SPI1 flash ACE section $n start address value.*/
-#define SPI_MEM_FMEM_PMS1_ADDR_S    0x03FFFFFF
-#define SPI_MEM_FMEM_PMS1_ADDR_S_M  ((SPI_MEM_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_FMEM_PMS1_ADDR_S_S))
-#define SPI_MEM_FMEM_PMS1_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_FMEM_PMS1_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x118)
-/* SPI_MEM_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
-/*description: SPI1 flash ACE section $n start address value.*/
-#define SPI_MEM_FMEM_PMS2_ADDR_S    0x03FFFFFF
-#define SPI_MEM_FMEM_PMS2_ADDR_S_M  ((SPI_MEM_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_FMEM_PMS2_ADDR_S_S))
-#define SPI_MEM_FMEM_PMS2_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_FMEM_PMS2_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x11C)
-/* SPI_MEM_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
-/*description: SPI1 flash ACE section $n start address value.*/
-#define SPI_MEM_FMEM_PMS3_ADDR_S    0x03FFFFFF
-#define SPI_MEM_FMEM_PMS3_ADDR_S_M  ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S))
-#define SPI_MEM_FMEM_PMS3_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_FMEM_PMS3_ADDR_S_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x120)
-/* SPI_MEM_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_FMEM_PMS0_SIZE    0x00003FFF
-#define SPI_MEM_FMEM_PMS0_SIZE_M  ((SPI_MEM_FMEM_PMS0_SIZE_V)<<(SPI_MEM_FMEM_PMS0_SIZE_S))
-#define SPI_MEM_FMEM_PMS0_SIZE_V  0x3FFF
-#define SPI_MEM_FMEM_PMS0_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x124)
-/* SPI_MEM_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_FMEM_PMS1_SIZE    0x00003FFF
-#define SPI_MEM_FMEM_PMS1_SIZE_M  ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S))
-#define SPI_MEM_FMEM_PMS1_SIZE_V  0x3FFF
-#define SPI_MEM_FMEM_PMS1_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x128)
-/* SPI_MEM_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_FMEM_PMS2_SIZE    0x00003FFF
-#define SPI_MEM_FMEM_PMS2_SIZE_M  ((SPI_MEM_FMEM_PMS2_SIZE_V)<<(SPI_MEM_FMEM_PMS2_SIZE_S))
-#define SPI_MEM_FMEM_PMS2_SIZE_V  0x3FFF
-#define SPI_MEM_FMEM_PMS2_SIZE_S  0
-
-#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x12C)
-/* SPI_MEM_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
-$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
-#define SPI_MEM_FMEM_PMS3_SIZE    0x00003FFF
-#define SPI_MEM_FMEM_PMS3_SIZE_M  ((SPI_MEM_FMEM_PMS3_SIZE_V)<<(SPI_MEM_FMEM_PMS3_SIZE_S))
-#define SPI_MEM_FMEM_PMS3_SIZE_V  0x3FFF
-#define SPI_MEM_FMEM_PMS3_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x130)
-/* SPI_MEM_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SMEM_PMS0_ECC    (BIT(2))
-#define SPI_MEM_SMEM_PMS0_ECC_M  (BIT(2))
-#define SPI_MEM_SMEM_PMS0_ECC_V  0x1
-#define SPI_MEM_SMEM_PMS0_ECC_S  2
-/* SPI_MEM_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS0_WR_ATTR    (BIT(1))
-#define SPI_MEM_SMEM_PMS0_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SMEM_PMS0_WR_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS0_WR_ATTR_S  1
-/* SPI_MEM_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS0_RD_ATTR    (BIT(0))
-#define SPI_MEM_SMEM_PMS0_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SMEM_PMS0_RD_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS0_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x134)
-/* SPI_MEM_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SMEM_PMS1_ECC    (BIT(2))
-#define SPI_MEM_SMEM_PMS1_ECC_M  (BIT(2))
-#define SPI_MEM_SMEM_PMS1_ECC_V  0x1
-#define SPI_MEM_SMEM_PMS1_ECC_S  2
-/* SPI_MEM_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS1_WR_ATTR    (BIT(1))
-#define SPI_MEM_SMEM_PMS1_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SMEM_PMS1_WR_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS1_WR_ATTR_S  1
-/* SPI_MEM_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS1_RD_ATTR    (BIT(0))
-#define SPI_MEM_SMEM_PMS1_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SMEM_PMS1_RD_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS1_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x138)
-/* SPI_MEM_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SMEM_PMS2_ECC    (BIT(2))
-#define SPI_MEM_SMEM_PMS2_ECC_M  (BIT(2))
-#define SPI_MEM_SMEM_PMS2_ECC_V  0x1
-#define SPI_MEM_SMEM_PMS2_ECC_S  2
-/* SPI_MEM_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS2_WR_ATTR    (BIT(1))
-#define SPI_MEM_SMEM_PMS2_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SMEM_PMS2_WR_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS2_WR_ATTR_S  1
-/* SPI_MEM_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS2_RD_ATTR    (BIT(0))
-#define SPI_MEM_SMEM_PMS2_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SMEM_PMS2_RD_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS2_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x13C)
-/* SPI_MEM_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
-e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
- and SPI_SMEM_PMS$n_SIZE_REG..*/
-#define SPI_MEM_SMEM_PMS3_ECC    (BIT(2))
-#define SPI_MEM_SMEM_PMS3_ECC_M  (BIT(2))
-#define SPI_MEM_SMEM_PMS3_ECC_V  0x1
-#define SPI_MEM_SMEM_PMS3_ECC_S  2
-/* SPI_MEM_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS3_WR_ATTR    (BIT(1))
-#define SPI_MEM_SMEM_PMS3_WR_ATTR_M  (BIT(1))
-#define SPI_MEM_SMEM_PMS3_WR_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS3_WR_ATTR_S  1
-/* SPI_MEM_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
-#define SPI_MEM_SMEM_PMS3_RD_ATTR    (BIT(0))
-#define SPI_MEM_SMEM_PMS3_RD_ATTR_M  (BIT(0))
-#define SPI_MEM_SMEM_PMS3_RD_ATTR_V  0x1
-#define SPI_MEM_SMEM_PMS3_RD_ATTR_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x140)
-/* SPI_MEM_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: SPI1 external RAM ACE section $n start address value.*/
-#define SPI_MEM_SMEM_PMS0_ADDR_S    0x03FFFFFF
-#define SPI_MEM_SMEM_PMS0_ADDR_S_M  ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S))
-#define SPI_MEM_SMEM_PMS0_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_SMEM_PMS0_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x144)
-/* SPI_MEM_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
-/*description: SPI1 external RAM ACE section $n start address value.*/
-#define SPI_MEM_SMEM_PMS1_ADDR_S    0x03FFFFFF
-#define SPI_MEM_SMEM_PMS1_ADDR_S_M  ((SPI_MEM_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SMEM_PMS1_ADDR_S_S))
-#define SPI_MEM_SMEM_PMS1_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_SMEM_PMS1_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x148)
-/* SPI_MEM_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
-/*description: SPI1 external RAM ACE section $n start address value.*/
-#define SPI_MEM_SMEM_PMS2_ADDR_S    0x03FFFFFF
-#define SPI_MEM_SMEM_PMS2_ADDR_S_M  ((SPI_MEM_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SMEM_PMS2_ADDR_S_S))
-#define SPI_MEM_SMEM_PMS2_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_SMEM_PMS2_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14C)
-/* SPI_MEM_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
-/*description: SPI1 external RAM ACE section $n start address value.*/
-#define SPI_MEM_SMEM_PMS3_ADDR_S    0x03FFFFFF
-#define SPI_MEM_SMEM_PMS3_ADDR_S_M  ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S))
-#define SPI_MEM_SMEM_PMS3_ADDR_S_V  0x3FFFFFF
-#define SPI_MEM_SMEM_PMS3_ADDR_S_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x150)
-/* SPI_MEM_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SMEM_PMS0_SIZE    0x00003FFF
-#define SPI_MEM_SMEM_PMS0_SIZE_M  ((SPI_MEM_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SMEM_PMS0_SIZE_S))
-#define SPI_MEM_SMEM_PMS0_SIZE_V  0x3FFF
-#define SPI_MEM_SMEM_PMS0_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x154)
-/* SPI_MEM_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SMEM_PMS1_SIZE    0x00003FFF
-#define SPI_MEM_SMEM_PMS1_SIZE_M  ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S))
-#define SPI_MEM_SMEM_PMS1_SIZE_V  0x3FFF
-#define SPI_MEM_SMEM_PMS1_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x158)
-/* SPI_MEM_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SMEM_PMS2_SIZE    0x00003FFF
-#define SPI_MEM_SMEM_PMS2_SIZE_M  ((SPI_MEM_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SMEM_PMS2_SIZE_S))
-#define SPI_MEM_SMEM_PMS2_SIZE_V  0x3FFF
-#define SPI_MEM_SMEM_PMS2_SIZE_S  0
-
-#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x15C)
-/* SPI_MEM_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
-/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
-MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
-#define SPI_MEM_SMEM_PMS3_SIZE    0x00003FFF
-#define SPI_MEM_SMEM_PMS3_SIZE_M  ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S))
-#define SPI_MEM_SMEM_PMS3_SIZE_V  0x3FFF
-#define SPI_MEM_SMEM_PMS3_SIZE_S  0
-
-#define SPI_MEM_PMS_REJECT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x164)
-/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
-/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
- error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_IVD    (BIT(31))
-#define SPI_MEM_PMS_IVD_M  (BIT(31))
-#define SPI_MEM_PMS_IVD_V  0x1
-#define SPI_MEM_PMS_IVD_S  31
-/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
- is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
-#define SPI_MEM_PMS_MULTI_HIT_V  0x1
-#define SPI_MEM_PMS_MULTI_HIT_S  30
-/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_ST    (BIT(29))
-#define SPI_MEM_PMS_ST_M  (BIT(29))
-#define SPI_MEM_PMS_ST_V  0x1
-#define SPI_MEM_PMS_ST_S  29
-/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
-_MEM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_PMS_LD    (BIT(28))
-#define SPI_MEM_PMS_LD_M  (BIT(28))
-#define SPI_MEM_PMS_LD_V  0x1
-#define SPI_MEM_PMS_LD_S  28
-/* SPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
-#define SPI_MEM_PM_EN    (BIT(26))
-#define SPI_MEM_PM_EN_M  (BIT(26))
-#define SPI_MEM_PM_EN_V  0x1
-#define SPI_MEM_PM_EN_S  26
-/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
-EM_PMS_REJECT_INT_CLR bit is set..*/
-#define SPI_MEM_REJECT_ADDR    0x03FFFFFF
-#define SPI_MEM_REJECT_ADDR_M  ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S))
-#define SPI_MEM_REJECT_ADDR_V  0x3FFFFFF
-#define SPI_MEM_REJECT_ADDR_S  0
-
-#define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x168)
-/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */
-/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
- to byte 0 bit 0 to byte 15 bit 7).*/
-#define SPI_MEM_ECC_ERR_BITS    0x0000007F
-#define SPI_MEM_ECC_ERR_BITS_M  ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S))
-#define SPI_MEM_ECC_ERR_BITS_V  0x7F
-#define SPI_MEM_ECC_ERR_BITS_S  25
-/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */
-/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
-ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
-R record the first ECC error information..*/
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
-#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
-/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */
-/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
-#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
-#define SPI_MEM_USR_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_USR_ECC_ADDR_EN_S  21
-/* SPI_MEM_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
-is bit should be 0. Otherwise, this bit should be 1..*/
-#define SPI_MEM_FMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_MEM_FMEM_ECC_ADDR_EN_M  (BIT(20))
-#define SPI_MEM_FMEM_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_FMEM_ECC_ADDR_EN_S  20
-/* SPI_MEM_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
-1024 bytes. 3: 2048 bytes..*/
-#define SPI_MEM_FMEM_PAGE_SIZE    0x00000003
-#define SPI_MEM_FMEM_PAGE_SIZE_M  ((SPI_MEM_FMEM_PAGE_SIZE_V)<<(SPI_MEM_FMEM_PAGE_SIZE_S))
-#define SPI_MEM_FMEM_PAGE_SIZE_V  0x3
-#define SPI_MEM_FMEM_PAGE_SIZE_S  18
-/* SPI_MEM_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
-h..*/
-#define SPI_MEM_FMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_MEM_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define SPI_MEM_FMEM_ECC_ERR_INT_EN_V  0x1
-#define SPI_MEM_FMEM_ECC_ERR_INT_EN_S  17
-/* SPI_MEM_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */
-/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
-upt..*/
-#define SPI_MEM_FMEM_ECC_ERR_INT_NUM    0x0000003F
-#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_FMEM_ECC_ERR_INT_NUM_S))
-#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_V  0x3F
-#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_S  11
-
-#define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x16C)
-/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[31:26] ;default: 6'd0 ; */
-/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define SPI_MEM_ECC_ERR_CNT    0x0000003F
-#define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
-#define SPI_MEM_ECC_ERR_CNT_V  0x3F
-#define SPI_MEM_ECC_ERR_CNT_S  26
-/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
-ECC_ERR_INT_CLR bit is set..*/
-#define SPI_MEM_ECC_ERR_ADDR    0x03FFFFFF
-#define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
-#define SPI_MEM_ECC_ERR_ADDR_V  0x3FFFFFF
-#define SPI_MEM_ECC_ERR_ADDR_S  0
-
-#define SPI_MEM_AXI_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x170)
-/* SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
-and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
-#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
-#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
-#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
-#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
-/* SPI_MEM_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
-/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define SPI_MEM_WBLEN_AFIFO_REMPTY    (BIT(30))
-#define SPI_MEM_WBLEN_AFIFO_REMPTY_M  (BIT(30))
-#define SPI_MEM_WBLEN_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_WBLEN_AFIFO_REMPTY_S  30
-/* SPI_MEM_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
-/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
-#define SPI_MEM_WDATA_AFIFO_REMPTY    (BIT(29))
-#define SPI_MEM_WDATA_AFIFO_REMPTY_M  (BIT(29))
-#define SPI_MEM_WDATA_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_WDATA_AFIFO_REMPTY_S  29
-/* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
-/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define SPI_MEM_RADDR_AFIFO_REMPTY    (BIT(28))
-#define SPI_MEM_RADDR_AFIFO_REMPTY_M  (BIT(28))
-#define SPI_MEM_RADDR_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_RADDR_AFIFO_REMPTY_S  28
-/* SPI_MEM_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
-/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
-#define SPI_MEM_RDATA_AFIFO_REMPTY    (BIT(27))
-#define SPI_MEM_RDATA_AFIFO_REMPTY_M  (BIT(27))
-#define SPI_MEM_RDATA_AFIFO_REMPTY_V  0x1
-#define SPI_MEM_RDATA_AFIFO_REMPTY_S  27
-/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
-/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
- and SPI0 transfers are done. 0: Others..*/
-#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
-#define SPI_MEM_ALL_FIFO_EMPTY_V  0x1
-#define SPI_MEM_ALL_FIFO_EMPTY_S  26
-/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits show the first AXI write/read invalid error or AXI write flash error a
-ddress. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLAS
-H_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
-#define SPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
-#define SPI_MEM_AXI_ERR_ADDR_M  ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S))
-#define SPI_MEM_AXI_ERR_ADDR_V  0x3FFFFFF
-#define SPI_MEM_AXI_ERR_ADDR_S  0
-
-#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x174)
-/* SPI_MEM_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
-/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
-he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
-ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
-#define SPI_MEM_SMEM_ECC_ADDR_EN    (BIT(20))
-#define SPI_MEM_SMEM_ECC_ADDR_EN_M  (BIT(20))
-#define SPI_MEM_SMEM_ECC_ADDR_EN_V  0x1
-#define SPI_MEM_SMEM_ECC_ADDR_EN_S  20
-/* SPI_MEM_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */
-/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
-es. 2: 1024 bytes. 3: 2048 bytes..*/
-#define SPI_MEM_SMEM_PAGE_SIZE    0x00000003
-#define SPI_MEM_SMEM_PAGE_SIZE_M  ((SPI_MEM_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SMEM_PAGE_SIZE_S))
-#define SPI_MEM_SMEM_PAGE_SIZE_V  0x3
-#define SPI_MEM_SMEM_PAGE_SIZE_S  18
-/* SPI_MEM_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
-rnal RAM..*/
-#define SPI_MEM_SMEM_ECC_ERR_INT_EN    (BIT(17))
-#define SPI_MEM_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
-#define SPI_MEM_SMEM_ECC_ERR_INT_EN_V  0x1
-#define SPI_MEM_SMEM_ECC_ERR_INT_EN_S  17
-
-#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x180)
-/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
-#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
-#define SPI_MEM_TIMING_CALI_UPDATE_V  0x1
-#define SPI_MEM_TIMING_CALI_UPDATE_S  6
-/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
-lash..*/
-#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
-#define SPI_MEM_DLL_TIMING_CALI_V  0x1
-#define SPI_MEM_DLL_TIMING_CALI_S  5
-/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_TIMING_CALI_V  0x1
-#define SPI_MEM_TIMING_CALI_S  1
-/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable timing adjust clock for all reading operations..*/
-#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x184)
-/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DINS_MODE    0x00000007
-#define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
-#define SPI_MEM_DINS_MODE_V  0x7
-#define SPI_MEM_DINS_MODE_S  24
-/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN7_MODE    0x00000007
-#define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
-#define SPI_MEM_DIN7_MODE_V  0x7
-#define SPI_MEM_DIN7_MODE_S  21
-/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN6_MODE    0x00000007
-#define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
-#define SPI_MEM_DIN6_MODE_V  0x7
-#define SPI_MEM_DIN6_MODE_S  18
-/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN5_MODE    0x00000007
-#define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
-#define SPI_MEM_DIN5_MODE_V  0x7
-#define SPI_MEM_DIN5_MODE_S  15
-/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
-ut with the spi_clk.*/
-#define SPI_MEM_DIN4_MODE    0x00000007
-#define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
-#define SPI_MEM_DIN4_MODE_V  0x7
-#define SPI_MEM_DIN4_MODE_S  12
-/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN3_MODE    0x00000007
-#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
-#define SPI_MEM_DIN3_MODE_V  0x7
-#define SPI_MEM_DIN3_MODE_S  9
-/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN2_MODE    0x00000007
-#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
-#define SPI_MEM_DIN2_MODE_V  0x7
-#define SPI_MEM_DIN2_MODE_S  6
-/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN1_MODE    0x00000007
-#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
-#define SPI_MEM_DIN1_MODE_V  0x7
-#define SPI_MEM_DIN1_MODE_S  3
-/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_DIN0_MODE    0x00000007
-#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
-#define SPI_MEM_DIN0_MODE_V  0x7
-#define SPI_MEM_DIN0_MODE_S  0
-
-#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x188)
-/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DINS_NUM    0x00000003
-#define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
-#define SPI_MEM_DINS_NUM_V  0x3
-#define SPI_MEM_DINS_NUM_S  16
-/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN7_NUM    0x00000003
-#define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
-#define SPI_MEM_DIN7_NUM_V  0x3
-#define SPI_MEM_DIN7_NUM_S  14
-/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN6_NUM    0x00000003
-#define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
-#define SPI_MEM_DIN6_NUM_V  0x3
-#define SPI_MEM_DIN6_NUM_S  12
-/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN5_NUM    0x00000003
-#define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
-#define SPI_MEM_DIN5_NUM_V  0x3
-#define SPI_MEM_DIN5_NUM_S  10
-/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN4_NUM    0x00000003
-#define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
-#define SPI_MEM_DIN4_NUM_V  0x3
-#define SPI_MEM_DIN4_NUM_S  8
-/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN3_NUM    0x00000003
-#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
-#define SPI_MEM_DIN3_NUM_V  0x3
-#define SPI_MEM_DIN3_NUM_S  6
-/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN2_NUM    0x00000003
-#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
-#define SPI_MEM_DIN2_NUM_V  0x3
-#define SPI_MEM_DIN2_NUM_S  4
-/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN1_NUM    0x00000003
-#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
-#define SPI_MEM_DIN1_NUM_V  0x3
-#define SPI_MEM_DIN1_NUM_S  2
-/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_DIN0_NUM    0x00000003
-#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
-#define SPI_MEM_DIN0_NUM_V  0x3
-#define SPI_MEM_DIN0_NUM_S  0
-
-#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18C)
-/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_DOUTS_MODE_M  (BIT(8))
-#define SPI_MEM_DOUTS_MODE_V  0x1
-#define SPI_MEM_DOUTS_MODE_S  8
-/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_DOUT7_MODE_M  (BIT(7))
-#define SPI_MEM_DOUT7_MODE_V  0x1
-#define SPI_MEM_DOUT7_MODE_S  7
-/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_DOUT6_MODE_M  (BIT(6))
-#define SPI_MEM_DOUT6_MODE_V  0x1
-#define SPI_MEM_DOUT6_MODE_S  6
-/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_DOUT5_MODE_M  (BIT(5))
-#define SPI_MEM_DOUT5_MODE_V  0x1
-#define SPI_MEM_DOUT5_MODE_S  5
-/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the spi_clk.*/
-#define SPI_MEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_DOUT4_MODE_M  (BIT(4))
-#define SPI_MEM_DOUT4_MODE_V  0x1
-#define SPI_MEM_DOUT4_MODE_S  4
-/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_DOUT3_MODE_S  3
-/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_DOUT2_MODE_S  2
-/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_DOUT1_MODE_S  1
-/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x190)
-/* SPI_MEM_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
-XT_RAM..*/
-#define SPI_MEM_SMEM_DLL_TIMING_CALI    (BIT(5))
-#define SPI_MEM_SMEM_DLL_TIMING_CALI_M  (BIT(5))
-#define SPI_MEM_SMEM_DLL_TIMING_CALI_V  0x1
-#define SPI_MEM_SMEM_DLL_TIMING_CALI_S  5
-/* SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
-#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
-ations..*/
-#define SPI_MEM_SMEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_SMEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_SMEM_TIMING_CALI_V  0x1
-#define SPI_MEM_SMEM_TIMING_CALI_S  1
-/* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: For sram, the bit is used to enable timing adjust clock for all reading operatio
-ns..*/
-#define SPI_MEM_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_SMEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_SMEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_SMEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x194)
-/* SPI_MEM_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DINS_MODE    0x00000007
-#define SPI_MEM_SMEM_DINS_MODE_M  ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S))
-#define SPI_MEM_SMEM_DINS_MODE_V  0x7
-#define SPI_MEM_SMEM_DINS_MODE_S  24
-/* SPI_MEM_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN7_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN7_MODE_M  ((SPI_MEM_SMEM_DIN7_MODE_V)<<(SPI_MEM_SMEM_DIN7_MODE_S))
-#define SPI_MEM_SMEM_DIN7_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN7_MODE_S  21
-/* SPI_MEM_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN6_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN6_MODE_M  ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S))
-#define SPI_MEM_SMEM_DIN6_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN6_MODE_S  18
-/* SPI_MEM_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN5_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN5_MODE_M  ((SPI_MEM_SMEM_DIN5_MODE_V)<<(SPI_MEM_SMEM_DIN5_MODE_S))
-#define SPI_MEM_SMEM_DIN5_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN5_MODE_S  15
-/* SPI_MEM_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN4_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN4_MODE_M  ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S))
-#define SPI_MEM_SMEM_DIN4_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN4_MODE_S  12
-/* SPI_MEM_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN3_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN3_MODE_M  ((SPI_MEM_SMEM_DIN3_MODE_V)<<(SPI_MEM_SMEM_DIN3_MODE_S))
-#define SPI_MEM_SMEM_DIN3_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN3_MODE_S  9
-/* SPI_MEM_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN2_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN2_MODE_M  ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S))
-#define SPI_MEM_SMEM_DIN2_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN2_MODE_S  6
-/* SPI_MEM_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN1_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN1_MODE_M  ((SPI_MEM_SMEM_DIN1_MODE_V)<<(SPI_MEM_SMEM_DIN1_MODE_S))
-#define SPI_MEM_SMEM_DIN1_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN1_MODE_S  3
-/* SPI_MEM_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DIN0_MODE    0x00000007
-#define SPI_MEM_SMEM_DIN0_MODE_M  ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S))
-#define SPI_MEM_SMEM_DIN0_MODE_V  0x7
-#define SPI_MEM_SMEM_DIN0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x198)
-/* SPI_MEM_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
-1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
-put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
-ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DINS_NUM    0x00000003
-#define SPI_MEM_SMEM_DINS_NUM_M  ((SPI_MEM_SMEM_DINS_NUM_V)<<(SPI_MEM_SMEM_DINS_NUM_S))
-#define SPI_MEM_SMEM_DINS_NUM_V  0x3
-#define SPI_MEM_SMEM_DINS_NUM_S  16
-/* SPI_MEM_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN7_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN7_NUM_M  ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S))
-#define SPI_MEM_SMEM_DIN7_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN7_NUM_S  14
-/* SPI_MEM_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN6_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN6_NUM_M  ((SPI_MEM_SMEM_DIN6_NUM_V)<<(SPI_MEM_SMEM_DIN6_NUM_S))
-#define SPI_MEM_SMEM_DIN6_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN6_NUM_S  12
-/* SPI_MEM_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN5_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN5_NUM_M  ((SPI_MEM_SMEM_DIN5_NUM_V)<<(SPI_MEM_SMEM_DIN5_NUM_S))
-#define SPI_MEM_SMEM_DIN5_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN5_NUM_S  10
-/* SPI_MEM_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN4_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN4_NUM_M  ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S))
-#define SPI_MEM_SMEM_DIN4_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN4_NUM_S  8
-/* SPI_MEM_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN3_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN3_NUM_M  ((SPI_MEM_SMEM_DIN3_NUM_V)<<(SPI_MEM_SMEM_DIN3_NUM_S))
-#define SPI_MEM_SMEM_DIN3_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN3_NUM_S  6
-/* SPI_MEM_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN2_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN2_NUM_M  ((SPI_MEM_SMEM_DIN2_NUM_V)<<(SPI_MEM_SMEM_DIN2_NUM_S))
-#define SPI_MEM_SMEM_DIN2_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN2_NUM_S  4
-/* SPI_MEM_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN1_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN1_NUM_M  ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S))
-#define SPI_MEM_SMEM_DIN1_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN1_NUM_S  2
-/* SPI_MEM_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-delayed by 2 cycles,....*/
-#define SPI_MEM_SMEM_DIN0_NUM    0x00000003
-#define SPI_MEM_SMEM_DIN0_NUM_M  ((SPI_MEM_SMEM_DIN0_NUM_V)<<(SPI_MEM_SMEM_DIN0_NUM_S))
-#define SPI_MEM_SMEM_DIN0_NUM_V  0x3
-#define SPI_MEM_SMEM_DIN0_NUM_S  0
-
-#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x19C)
-/* SPI_MEM_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_SMEM_DOUTS_MODE_M  (BIT(8))
-#define SPI_MEM_SMEM_DOUTS_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUTS_MODE_S  8
-/* SPI_MEM_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_SMEM_DOUT7_MODE_M  (BIT(7))
-#define SPI_MEM_SMEM_DOUT7_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT7_MODE_S  7
-/* SPI_MEM_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_SMEM_DOUT6_MODE_M  (BIT(6))
-#define SPI_MEM_SMEM_DOUT6_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT6_MODE_S  6
-/* SPI_MEM_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_SMEM_DOUT5_MODE_M  (BIT(5))
-#define SPI_MEM_SMEM_DOUT5_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT5_MODE_S  5
-/* SPI_MEM_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_SMEM_DOUT4_MODE_M  (BIT(4))
-#define SPI_MEM_SMEM_DOUT4_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT4_MODE_S  4
-/* SPI_MEM_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_SMEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_SMEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT3_MODE_S  3
-/* SPI_MEM_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_SMEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_SMEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT2_MODE_S  2
-/* SPI_MEM_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_SMEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_SMEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT1_MODE_S  1
-/* SPI_MEM_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
-/*description: the output signals are delayed by system clock cycles, 0: output without delayed
-, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
- output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
-ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
-#define SPI_MEM_SMEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_SMEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_SMEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_SMEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A0)
-/* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
- transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
-er whether there is an ECC region or not..*/
-#define SPI_MEM_SMEM_SPLIT_TRANS_EN    (BIT(31))
-#define SPI_MEM_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
-#define SPI_MEM_SMEM_SPLIT_TRANS_EN_V  0x1
-#define SPI_MEM_SMEM_SPLIT_TRANS_EN_S  31
-/* SPI_MEM_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
-SPI core clock cycles..*/
-#define SPI_MEM_SMEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SMEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_SMEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_SMEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
-n accesses external RAM..*/
-#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
-#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V  0x1
-#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S  16
-/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */
-/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
-en accesses external RAM..*/
-#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
-#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/* SPI_MEM_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
-ycles in ECC mode when accessed external RAM..*/
-#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME    0x00000007
-#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S))
-#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V  0x7
-#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S  12
-/* SPI_MEM_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */
-/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
-re combined with spi_mem_cs_hold bit..*/
-#define SPI_MEM_SMEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S))
-#define SPI_MEM_SMEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_SMEM_CS_HOLD_TIME_S  7
-/* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */
-/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
-pi_mem_cs_setup bit..*/
-#define SPI_MEM_SMEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SMEM_CS_SETUP_TIME_S))
-#define SPI_MEM_SMEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_SMEM_CS_SETUP_TIME_S  2
-/* SPI_MEM_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
-le..*/
-#define SPI_MEM_SMEM_CS_HOLD    (BIT(1))
-#define SPI_MEM_SMEM_CS_HOLD_M  (BIT(1))
-#define SPI_MEM_SMEM_CS_HOLD_V  0x1
-#define SPI_MEM_SMEM_CS_HOLD_S  1
-/* SPI_MEM_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
-isable..*/
-#define SPI_MEM_SMEM_CS_SETUP    (BIT(0))
-#define SPI_MEM_SMEM_CS_SETUP_M  (BIT(0))
-#define SPI_MEM_SMEM_CS_SETUP_V  0x1
-#define SPI_MEM_SMEM_CS_SETUP_S  0
-
-#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x200)
-/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
-#define SPI_MEM_CLK_EN    (BIT(0))
-#define SPI_MEM_CLK_EN_M  (BIT(0))
-#define SPI_MEM_CLK_EN_V  0x1
-#define SPI_MEM_CLK_EN_S  0
-
-#define SPI_MEM_MMU_ITEM_CONTENT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x37C)
-/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: MSPI-MMU item content.*/
-#define SPI_MEM_MMU_ITEM_CONTENT    0xFFFFFFFF
-#define SPI_MEM_MMU_ITEM_CONTENT_M  ((SPI_MEM_MMU_ITEM_CONTENT_V)<<(SPI_MEM_MMU_ITEM_CONTENT_S))
-#define SPI_MEM_MMU_ITEM_CONTENT_V  0xFFFFFFFF
-#define SPI_MEM_MMU_ITEM_CONTENT_S  0
-
-#define SPI_MEM_MMU_ITEM_INDEX_REG(i)          (REG_SPI_MEM_BASE(i) + 0x380)
-/* SPI_MEM_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: MSPI-MMU item index.*/
-#define SPI_MEM_MMU_ITEM_INDEX    0xFFFFFFFF
-#define SPI_MEM_MMU_ITEM_INDEX_M  ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S))
-#define SPI_MEM_MMU_ITEM_INDEX_V  0xFFFFFFFF
-#define SPI_MEM_MMU_ITEM_INDEX_S  0
-
-#define SPI_MEM_MMU_POWER_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x384)
-/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
-#define SPI_MEM_RDN_RESULT    (BIT(31))
-#define SPI_MEM_RDN_RESULT_M  (BIT(31))
-#define SPI_MEM_RDN_RESULT_V  0x1
-#define SPI_MEM_RDN_RESULT_S  31
-/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: ECO register enable bit.*/
-#define SPI_MEM_RDN_ENA    (BIT(30))
-#define SPI_MEM_RDN_ENA_M  (BIT(30))
-#define SPI_MEM_RDN_ENA_V  0x1
-#define SPI_MEM_RDN_ENA_S  30
-/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */
-/*description: MMU PSRAM aux control register.*/
-#define SPI_MEM_AUX_CTRL    0x00003FFF
-#define SPI_MEM_AUX_CTRL_M  ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S))
-#define SPI_MEM_AUX_CTRL_V  0x3FFF
-#define SPI_MEM_AUX_CTRL_S  16
-/* SPI_MEM_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
-/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/
-#define SPI_MEM_MMU_PAGE_SIZE    0x00000003
-#define SPI_MEM_MMU_PAGE_SIZE_M  ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S))
-#define SPI_MEM_MMU_PAGE_SIZE_V  0x3
-#define SPI_MEM_MMU_PAGE_SIZE_S  3
-/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
- controlled by rtc..*/
-#define SPI_MEM_MMU_MEM_FORCE_PU    (BIT(2))
-#define SPI_MEM_MMU_MEM_FORCE_PU_M  (BIT(2))
-#define SPI_MEM_MMU_MEM_FORCE_PU_V  0x1
-#define SPI_MEM_MMU_MEM_FORCE_PU_S  2
-/* SPI_MEM_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to force mmu-memory powerdown.*/
-#define SPI_MEM_MMU_MEM_FORCE_PD    (BIT(1))
-#define SPI_MEM_MMU_MEM_FORCE_PD_M  (BIT(1))
-#define SPI_MEM_MMU_MEM_FORCE_PD_V  0x1
-#define SPI_MEM_MMU_MEM_FORCE_PD_S  1
-/* SPI_MEM_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable mmu-memory clock force on.*/
-#define SPI_MEM_MMU_MEM_FORCE_ON    (BIT(0))
-#define SPI_MEM_MMU_MEM_FORCE_ON_M  (BIT(0))
-#define SPI_MEM_MMU_MEM_FORCE_ON_V  0x1
-#define SPI_MEM_MMU_MEM_FORCE_ON_S  0
-
-#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F0)
-/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO high register.*/
-#define SPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_HIGH_M  ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S))
-#define SPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_HIGH_S  0
-
-#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F4)
-/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */
-/*description: ECO low register.*/
-#define SPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_LOW_M  ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S))
-#define SPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
-#define SPI_MEM_REGISTERRND_ECO_LOW_S  0
-
-#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
-/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2203030 ; */
-/*description: SPI0 register version..*/
-#define SPI_MEM_DATE    0x0FFFFFFF
-#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
-#define SPI_MEM_DATE_V  0xFFFFFFF
-#define SPI_MEM_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/spi_mem_struct.h b/components/soc/esp32h2/include/soc/spi_mem_struct.h
deleted file mode 100644
index 95578484588..00000000000
--- a/components/soc/esp32h2/include/soc/spi_mem_struct.h
+++ /dev/null
@@ -1,1076 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-typedef volatile struct spi_mem_dev_s {
-    union {
-        struct {
-            uint32_t mst_st                        :    4;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
-            uint32_t slv_st                        :    4;  /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
-            uint32_t reserved8                     :    9;  /*reserved*/
-            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t usr                           :    1;  /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
-            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/
-            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/
-            uint32_t fdummy_rin                    :    1;  /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/
-            uint32_t fdummy_wout                   :    1;  /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/
-            uint32_t fdout_oct                     :    1;  /*Apply 8 signals during write-data phase 1:enable 0: disable*/
-            uint32_t fdin_oct                      :    1;  /*Apply 8 signals during read-data phase 1:enable 0: disable*/
-            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during address phase 1:enable 0: disable*/
-            uint32_t reserved7                     :    1;  /*reserved*/
-            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
-            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable*/
-            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
-            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
-            uint32_t reserved12                    :    1;  /*reserved*/
-            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
-            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
-            uint32_t reserved16                    :    2;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
-            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
-            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
-            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t reserved25                    :    5;  /*reserved*/
-            uint32_t dqs_ie_always_on              :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
-            uint32_t data_ie_always_on             :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
-            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
-            uint32_t reserved2                     :    9;  /*reserved*/
-            uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
-            uint32_t reg_aw_size0_1_support_en     :    1;  /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/
-            uint32_t reg_axi_rdata_back_fast       :    1;  /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/
-            uint32_t rresp_ecc_err_en              :    1;  /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/
-            uint32_t ar_splice_en                  :    1;  /*Set this bit to enable AXI Read Splice-transfer.*/
-            uint32_t aw_splice_en                  :    1;  /*Set this bit to enable AXI Write Splice-transfer.*/
-            uint32_t ram0_en                       :    1;  /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
-            uint32_t dual_ram_en                   :    1;  /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
-            uint32_t fast_write_en                 :    1;  /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.*/
-            uint32_t rxfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.*/
-            uint32_t txfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/
-        };
-        uint32_t val;
-    } ctrl1;
-    union {
-        struct {
-            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/
-            uint32_t cs_hold_time                  :    5;  /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/
-            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/
-            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
-            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
-            uint32_t reserved15                    :    9;  /*reserved*/
-            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
-            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t sync_reset                    :    1;  /*The spi0_mst_st and spi0_slv_st will be reset.*/
-        };
-        uint32_t val;
-    } ctrl2;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
-            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
-            uint32_t clk_equ_sysclk                :    1;  /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
-            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
-            uint32_t reserved8                     :    1;  /*reserved*/
-            uint32_t ck_out_edge                   :    1;  /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
-            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
-            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
-            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
-            uint32_t reserved16                    :    8;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
-            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
-            uint32_t usr_dbytelen                  :    3;  /*SPI0 USR_CMD read or write data byte length -1*/
-            uint32_t reserved9                     :    17;  /*reserved*/
-            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of  command.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } mosi_dlen;
-    union {
-        struct {
-            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } miso_dlen;
-    union {
-        struct {
-            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
-            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t reserved24                    :    8;  /*reserved*/
-        };
-        uint32_t val;
-    } rd_status;
-    uint32_t reserved_30;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
-            uint32_t reserved0                     :    5;  /*reserved*/
-            uint32_t fsub_pin                      :    1;  /*For SPI0,  flash is connected to SUBPINs.*/
-            uint32_t ssub_pin                      :    1;  /*For SPI0,  sram is connected to SUBPINs.*/
-            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle     0: spi clk line is low when idle */
-            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } misc;
-    uint32_t tx_crc;
-    union {
-        struct {
-            uint32_t axi_req_en                    :    1;  /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/
-            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
-            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
-            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
-            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
-            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
-            uint32_t reserved9                     :    21;  /*reserved*/
-            uint32_t reg_same_aw_ar_addr_chk_en    :    1;  /*Set this bit to check AXI read/write the same address region.*/
-            uint32_t reg_close_axi_inf_en          :    1;  /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/
-        };
-        uint32_t val;
-    } cache_fctrl;
-    union {
-        struct {
-            uint32_t usr_saddr_4byte               :    1;  /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/
-            uint32_t usr_sram_dio                  :    1;  /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
-            uint32_t usr_sram_qio                  :    1;  /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
-            uint32_t usr_wr_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/
-            uint32_t usr_rd_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/
-            uint32_t sram_usr_rcmd                 :    1;  /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/
-            uint32_t sram_rdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved12                    :    2;  /*reserved*/
-            uint32_t sram_addr_bitlen              :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/
-            uint32_t sram_usr_wcmd                 :    1;  /*For SPI0, In the external RAM mode cache write sram for user define command*/
-            uint32_t sram_oct                      :    1;  /*reserved*/
-            uint32_t sram_wdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } cache_sctrl;
-    union {
-        struct {
-            uint32_t sclk_mode                     :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
-            uint32_t swb_mode                      :    8;  /*Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
-            uint32_t sdin_dual                     :    1;  /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t sdout_dual                    :    1;  /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t saddr_dual                    :    1;  /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
-            uint32_t reserved13                    :    1;  /*reserved*/
-            uint32_t sdin_quad                     :    1;  /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t sdout_quad                    :    1;  /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t saddr_quad                    :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t scmd_quad                     :    1;  /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
-            uint32_t sdin_oct                      :    1;  /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t sdout_oct                     :    1;  /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t saddr_oct                     :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */
-            uint32_t scmd_oct                      :    1;  /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */
-            uint32_t sdummy_rin                    :    1;  /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
-            uint32_t sdummy_wout                   :    1;  /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
-            uint32_t reg_smem_wdummy_dqs_always_out:    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/
-            uint32_t reg_smem_wdummy_always_out    :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/
-            uint32_t reserved26                    :    4;  /*reserved*/
-            uint32_t reg_smem_dqs_ie_always_on     :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
-            uint32_t reg_smem_data_ie_always_on    :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
-        };
-        uint32_t val;
-    } sram_cmd;
-    union {
-        struct {
-            uint32_t sram_usr_rd_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t sram_usr_rd_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_drd_cmd;
-    union {
-        struct {
-            uint32_t sram_usr_wr_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t sram_usr_wr_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_dwr_cmd;
-    union {
-        struct {
-            uint32_t sclkcnt_l                     :    8;  /*For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.*/
-            uint32_t sclkcnt_h                     :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
-            uint32_t sclkcnt_n                     :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
-            uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
-        };
-        uint32_t val;
-    } sram_clk;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;  /*reserved*/
-            uint32_t lock_delay_time               :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } fsm;
-    uint32_t data_buf[16];
-    union {
-        struct {
-            uint32_t waiti_en                      :    1;  /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/
-            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
-            uint32_t waiti_addr_en                 :    1;  /*1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/
-            uint32_t waiti_addr_cyclelen           :    2;  /*When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/
-            uint32_t reserved5                     :    4;  /*reserved*/
-            uint32_t waiti_cmd_2b                  :    1;  /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/
-            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
-            uint32_t waiti_cmd                     :    16;  /*The command value to wait flash idle(RDSR).*/
-        };
-        uint32_t val;
-    } flash_waiti_ctrl;
-    union {
-        struct {
-            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
-            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
-            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
-            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
-            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
-            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
-            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
-            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
-        };
-        uint32_t val;
-    } flash_sus_ctrl;
-    union {
-        struct {
-            uint32_t flash_pes_command             :    16;  /*Program/Erase suspend command.*/
-            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
-        };
-        uint32_t val;
-    } flash_sus_cmd;
-    union {
-        struct {
-            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
-            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
-            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
-            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
-            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
-            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
-            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
-            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
-            uint32_t reserved8                     :    7;  /*reserved*/
-            uint32_t flash_pesr_cmd_2b             :    1;  /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/
-            uint32_t flash_per_command             :    16;  /*Program/Erase resume command.*/
-        };
-        uint32_t val;
-    } sus_status;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    union {
-        struct {
-            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject_en                 :    1;  /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err_en           :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err                       :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject                    :    1;  /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
-            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
-            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
-            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
-            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/
-            uint32_t ecc_err                       :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
-            uint32_t pms_reject                    :    1;  /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/
-            uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
-            uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
-            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
-            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
-            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
-            uint32_t ecc_err                       :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t pms_reject                    :    1;  /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
-            uint32_t axi_raddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
-            uint32_t axi_wr_flash_err              :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
-            uint32_t axi_waddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
-            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t reserved11                    :    21;  /*reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    uint32_t reserved_d0;
-    union {
-        struct {
-            uint32_t reg_fmem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
-            uint32_t reg_fmem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
-            uint32_t reg_fmem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
-            uint32_t reg_fmem_outminbytelen        :    7;  /*It is the minimum output data length in the panda device.*/
-            uint32_t reg_fmem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
-            uint32_t reg_fmem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/
-            uint32_t reg_fmem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
-            uint32_t reg_fmem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t reg_fmem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t reserved25                    :    1;  /*reserved*/
-            uint32_t reg_fmem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t reg_fmem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
-            uint32_t reg_fmem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
-            uint32_t reg_fmem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t reg_fmem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } ddr;
-    union {
-        struct {
-            uint32_t reg_smem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
-            uint32_t reg_smem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
-            uint32_t reg_smem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
-            uint32_t reg_smem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
-            uint32_t reg_smem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
-            uint32_t reg_smem_outminbytelen        :    7;  /*It is the minimum output data length in the DDR psram.*/
-            uint32_t reg_smem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/
-            uint32_t reg_smem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/
-            uint32_t reg_smem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
-            uint32_t reg_smem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t reg_smem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t reserved25                    :    1;  /*reserved*/
-            uint32_t reg_smem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t reg_smem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
-            uint32_t reg_smem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
-            uint32_t reg_smem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t reg_smem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ddr;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms0_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms0_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms1_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms1_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms2_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms2_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms3_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_fmem_pms3_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_attr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_addr;
-    union {
-        struct {
-            uint32_t reg_fmem_pms0_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms0_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms1_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms1_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms2_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms2_size;
-    union {
-        struct {
-            uint32_t reg_fmem_pms3_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_fmem_pms3_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms0_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms0_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms1_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms1_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms2_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms2_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms3_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
-            uint32_t reg_smem_pms3_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_attr;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_addr;
-    union {
-        struct {
-            uint32_t reg_smem_pms0_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms0_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms1_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms1_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms2_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms2_size;
-    union {
-        struct {
-            uint32_t reg_smem_pms3_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
-            uint32_t reserved14                    :    18;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_pms3_size;
-    uint32_t reserved_160;
-    union {
-        struct {
-            uint32_t reject_addr                   :    26;  /*This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pm_en                         :    1;  /*Set this bit to enable SPI0/1 transfer permission control function.*/
-            uint32_t reserved27                    :    1;  /*reserved*/
-            uint32_t pms_ld                        :    1;  /*1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_st                        :    1;  /*1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_multi_hit                 :    1;  /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-            uint32_t pms_ivd                       :    1;  /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
-        };
-        uint32_t val;
-    } pms_reject;
-    union {
-        struct {
-            uint32_t reserved0                     :    11;  /*reserved*/
-            uint32_t ecc_err_int_num               :    6;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t reg_fmem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
-            uint32_t reg_fmem_page_size            :    2;  /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t reg_fmem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/
-            uint32_t usr_ecc_addr_en               :    1;  /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/
-            uint32_t reserved22                    :    2;  /*reserved*/
-            uint32_t ecc_continue_record_err_en    :    1;  /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/
-            uint32_t ecc_err_bits                  :    7;  /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/
-        };
-        uint32_t val;
-    } ecc_ctrl;
-    union {
-        struct {
-            uint32_t ecc_err_addr                  :    26;  /*This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-            uint32_t ecc_err_cnt                   :    6;  /*This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-        };
-        uint32_t val;
-    } ecc_err_addr;
-    union {
-        struct {
-            uint32_t axi_err_addr                  :    26;  /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
-            uint32_t all_fifo_empty                :    1;  /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
-            uint32_t reg_rdata_afifo_rempty        :    1;  /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
-            uint32_t reg_raddr_afifo_rempty        :    1;  /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
-            uint32_t reg_wdata_afifo_rempty        :    1;  /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
-            uint32_t reg_wblen_afifo_rempty        :    1;  /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
-            uint32_t reg_all_axi_trans_afifo_empty :    1;  /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/
-        };
-        uint32_t val;
-    } axi_err_addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    17;  /*reserved*/
-            uint32_t reg_smem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
-            uint32_t reg_smem_page_size            :    2;  /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
-            uint32_t reg_smem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ecc_ctrl;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    union {
-        struct {
-            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/
-            uint32_t timing_cali_update            :    1;  /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/
-            uint32_t reserved7                     :    25;  /*reserved*/
-        };
-        uint32_t val;
-    } timing_cali;
-    union {
-        struct {
-            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    union {
-        struct {
-            uint32_t reg_smem_timing_clk_ena       :    1;  /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/
-            uint32_t reg_smem_timing_cali          :    1;  /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
-            uint32_t reg_smem_extra_dummy_cyclelen :    3;  /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
-            uint32_t reg_smem_dll_timing_cali      :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_timing_cali;
-    union {
-        struct {
-            uint32_t reg_smem_din0_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din1_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din2_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din3_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din4_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din5_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din6_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_din7_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reg_smem_dins_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_mode;
-    union {
-        struct {
-            uint32_t reg_smem_din0_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din1_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din2_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din3_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din4_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din5_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din6_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_din7_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
-            uint32_t reg_smem_dins_num             :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_num;
-    union {
-        struct {
-            uint32_t reg_smem_dout0_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout1_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout2_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout3_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout4_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout5_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout6_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_dout7_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reg_smem_douts_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_dout_mode;
-    union {
-        struct {
-            uint32_t reg_smem_cs_setup             :    1;  /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */
-            uint32_t reg_smem_cs_hold              :    1;  /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
-            uint32_t reg_smem_cs_setup_time        :    5;  /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
-            uint32_t reg_smem_cs_hold_time         :    5;  /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
-            uint32_t reg_smem_ecc_cs_hold_time     :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/
-            uint32_t reg_smem_ecc_skip_page_corner :    1;  /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/
-            uint32_t reg_smem_ecc_16to18_byte_en   :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/
-            uint32_t reserved17                    :    8;  /*reserved*/
-            uint32_t reg_smem_cs_hold_delay        :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t reg_smem_split_trans_en       :    1;  /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
-        };
-        uint32_t val;
-    } spi_smem_ac;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    union {
-        struct {
-            uint32_t reg_clk_en                    :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t xts_plain_base;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    union {
-        struct {
-            uint32_t reg_xts_linesize              :    2;  /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_linesize;
-    union {
-        struct {
-            uint32_t reg_xts_destination           :    1;  /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_destination;
-    union {
-        struct {
-            uint32_t reg_xts_physical_address      :    26;  /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/
-            uint32_t reserved26                    :    6;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_physical_address;
-    union {
-        struct {
-            uint32_t reg_xts_trigger               :    1;  /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_trigger;
-    union {
-        struct {
-            uint32_t reg_xts_release               :    1;  /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_release;
-    union {
-        struct {
-            uint32_t reg_xts_destroy               :    1;  /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_destroy;
-    union {
-        struct {
-            uint32_t reg_xts_state                 :    2;  /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_state;
-    union {
-        struct {
-            uint32_t reg_xts_date                  :    30;  /*This bits stores the last modified-time of manual encryption feature.*/
-            uint32_t reserved30                    :    2;  /*reserved*/
-        };
-        uint32_t val;
-    } xts_date;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t mmu_item_content;
-    uint32_t mmu_item_index;
-    union {
-        struct {
-            uint32_t reg_mmu_mem_force_on          :    1;  /*Set this bit to enable mmu-memory clock force on*/
-            uint32_t reg_mmu_mem_force_pd          :    1;  /*Set this bit to force mmu-memory powerdown*/
-            uint32_t reg_mmu_mem_force_pu          :    1;  /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/
-            uint32_t reg_mmu_page_size             :    2;  /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/
-            uint32_t reserved5                     :    11;  /*reserved*/
-            uint32_t aux_ctrl                      :    14;  /*MMU PSRAM aux control register*/
-            uint32_t rdn_ena                       :    1;  /*ECO register enable bit*/
-            uint32_t rdn_result                    :    1;  /*MSPI module clock domain and AXI clock domain ECO register result register*/
-        };
-        uint32_t val;
-    } mmu_power_ctrl;
-    union {
-        struct {
-            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
-            uint32_t reg_crypt_calc_d_dpa_en       :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
-            uint32_t reg_crypt_dpa_selectister     :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } dpa_ctrl;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t spi_memisterrnd_eco_high;
-    uint32_t spi_memisterrnd_eco_low;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*SPI0 register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_mem_dev_t;
-extern spi_mem_dev_t SPIMEM0;
-extern spi_mem_dev_t SPIMEM1;
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/spi_reg.h b/components/soc/esp32h2/include/soc/spi_reg.h
deleted file mode 100644
index 126b6b53243..00000000000
--- a/components/soc/esp32h2/include/soc/spi_reg.h
+++ /dev/null
@@ -1,2114 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SPI_CMD_REG register
- *  Command control register
- */
-#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0)
-/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
- */
-#define SPI_CONF_BITLEN    0x0003FFFFU
-#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
-#define SPI_CONF_BITLEN_V  0x0003FFFFU
-#define SPI_CONF_BITLEN_S  0
-/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
- *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
- *  clock domain, which is only used in SPI master mode.
- */
-#define SPI_UPDATE    (BIT(23))
-#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
-#define SPI_UPDATE_V  0x00000001U
-#define SPI_UPDATE_S  23
-/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
- *  User define command enable.  An operation will be triggered when the bit is set.
- *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
- *  changed by CONF_buf.
- */
-#define SPI_USR    (BIT(24))
-#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
-#define SPI_USR_V  0x00000001U
-#define SPI_USR_S  24
-
-/** SPI_ADDR_REG register
- *  Address value register
- */
-#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4)
-/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  Address to slave. Can be configured in CONF state.
- */
-#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
-#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_S  0
-
-/** SPI_CTRL_REG register
- *  SPI control register
- */
-#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8)
-/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
- *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
- *  the FSPI bus signals are output. Can be configured in CONF state.
- */
-#define SPI_DUMMY_OUT    (BIT(3))
-#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
-#define SPI_DUMMY_OUT_V  0x00000001U
-#define SPI_DUMMY_OUT_S  3
-/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
- *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_DUAL    (BIT(5))
-#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
-#define SPI_FADDR_DUAL_V  0x00000001U
-#define SPI_FADDR_DUAL_S  5
-/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
- *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_QUAD    (BIT(6))
-#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
-#define SPI_FADDR_QUAD_V  0x00000001U
-#define SPI_FADDR_QUAD_S  6
-/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0;
- *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_OCT    (BIT(7))
-#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
-#define SPI_FADDR_OCT_V  0x00000001U
-#define SPI_FADDR_OCT_S  7
-/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
- *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_DUAL    (BIT(8))
-#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
-#define SPI_FCMD_DUAL_V  0x00000001U
-#define SPI_FCMD_DUAL_S  8
-/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
- *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_QUAD    (BIT(9))
-#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
-#define SPI_FCMD_QUAD_V  0x00000001U
-#define SPI_FCMD_QUAD_S  9
-/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0;
- *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_OCT    (BIT(10))
-#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
-#define SPI_FCMD_OCT_V  0x00000001U
-#define SPI_FCMD_OCT_S  10
-/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
- *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_DUAL    (BIT(14))
-#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
-#define SPI_FREAD_DUAL_V  0x00000001U
-#define SPI_FREAD_DUAL_S  14
-/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
- *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_QUAD    (BIT(15))
-#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
-#define SPI_FREAD_QUAD_V  0x00000001U
-#define SPI_FREAD_QUAD_S  15
-/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0;
- *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_OCT    (BIT(16))
-#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
-#define SPI_FREAD_OCT_V  0x00000001U
-#define SPI_FREAD_OCT_S  16
-/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
- *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
- *  CONF state.
- */
-#define SPI_Q_POL    (BIT(18))
-#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
-#define SPI_Q_POL_V  0x00000001U
-#define SPI_Q_POL_S  18
-/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
- *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
- *  CONF state.
- */
-#define SPI_D_POL    (BIT(19))
-#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
-#define SPI_D_POL_V  0x00000001U
-#define SPI_D_POL_S  19
-/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
- *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
- *  configured in CONF state.
- */
-#define SPI_HOLD_POL    (BIT(20))
-#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
-#define SPI_HOLD_POL_V  0x00000001U
-#define SPI_HOLD_POL_S  20
-/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
- *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
- *  be configured in CONF state.
- */
-#define SPI_WP_POL    (BIT(21))
-#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
-#define SPI_WP_POL_V  0x00000001U
-#define SPI_WP_POL_S  21
-/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
- *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
- *  state.
- */
-#define SPI_RD_BIT_ORDER    0x00000003U
-#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
-#define SPI_RD_BIT_ORDER_V  0x00000003U
-#define SPI_RD_BIT_ORDER_S  23
-/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
- *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
- *  configured in CONF state.
- */
-#define SPI_WR_BIT_ORDER    0x00000003U
-#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
-#define SPI_WR_BIT_ORDER_V  0x00000003U
-#define SPI_WR_BIT_ORDER_S  25
-
-/** SPI_CLOCK_REG register
- *  SPI clock control register
- */
-#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc)
-/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
- *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
- *  0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_L    0x0000003FU
-#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
-#define SPI_CLKCNT_L_V  0x0000003FU
-#define SPI_CLKCNT_L_S  0
-/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
- *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
- *  must be 0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_H    0x0000003FU
-#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
-#define SPI_CLKCNT_H_V  0x0000003FU
-#define SPI_CLKCNT_H_S  6
-/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
- *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
- *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
- */
-#define SPI_CLKCNT_N    0x0000003FU
-#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
-#define SPI_CLKCNT_N_V  0x0000003FU
-#define SPI_CLKCNT_N_S  12
-/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
- *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
- */
-#define SPI_CLKDIV_PRE    0x0000000FU
-#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
-#define SPI_CLKDIV_PRE_V  0x0000000FU
-#define SPI_CLKDIV_PRE_S  18
-/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
- *  clock. Can be configured in CONF state.
- */
-#define SPI_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
-#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_CLK_EQU_SYSCLK_S  31
-
-/** SPI_USER_REG register
- *  SPI USER control register
- */
-#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10)
-/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
- *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUTDIN    (BIT(0))
-#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
-#define SPI_DOUTDIN_V  0x00000001U
-#define SPI_DOUTDIN_S  0
-/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
- *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
- *  Can be configured in CONF state.
- */
-#define SPI_QPI_MODE    (BIT(3))
-#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
-#define SPI_QPI_MODE_V  0x00000001U
-#define SPI_QPI_MODE_S  3
-/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0;
- *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
- *  Can be configured in CONF state.
- */
-#define SPI_OPI_MODE    (BIT(4))
-#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
-#define SPI_OPI_MODE_V  0x00000001U
-#define SPI_OPI_MODE_S  4
-/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
- *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
- *  spi_ck_i. 1:tsck = !spi_ck_i.
- */
-#define SPI_TSCK_I_EDGE    (BIT(5))
-#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
-#define SPI_TSCK_I_EDGE_V  0x00000001U
-#define SPI_TSCK_I_EDGE_S  5
-/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
- *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_CS_HOLD    (BIT(6))
-#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
-#define SPI_CS_HOLD_V  0x00000001U
-#define SPI_CS_HOLD_S  6
-/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
- *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_CS_SETUP    (BIT(7))
-#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
-#define SPI_CS_SETUP_V  0x00000001U
-#define SPI_CS_SETUP_S  7
-/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
- *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
- *  !spi_ck_i. 1:rsck = spi_ck_i.
- */
-#define SPI_RSCK_I_EDGE    (BIT(8))
-#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
-#define SPI_RSCK_I_EDGE_V  0x00000001U
-#define SPI_RSCK_I_EDGE_S  8
-/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
- *  be configured in CONF state.
- */
-#define SPI_CK_OUT_EDGE    (BIT(9))
-#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
-#define SPI_CK_OUT_EDGE_V  0x00000001U
-#define SPI_CK_OUT_EDGE_S  9
-/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
- *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_DUAL    (BIT(12))
-#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
-#define SPI_FWRITE_DUAL_V  0x00000001U
-#define SPI_FWRITE_DUAL_S  12
-/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
- *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_QUAD    (BIT(13))
-#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
-#define SPI_FWRITE_QUAD_V  0x00000001U
-#define SPI_FWRITE_QUAD_S  13
-/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0;
- *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_OCT    (BIT(14))
-#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
-#define SPI_FWRITE_OCT_V  0x00000001U
-#define SPI_FWRITE_OCT_S  14
-/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
- *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
- *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
- *  not seg-trans mode. Can be configured in CONF state.
- */
-#define SPI_USR_CONF_NXT    (BIT(15))
-#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
-#define SPI_USR_CONF_NXT_V  0x00000001U
-#define SPI_USR_CONF_NXT_S  15
-/** SPI_SIO : R/W; bitpos: [17]; default: 0;
- *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
- *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
- */
-#define SPI_SIO    (BIT(17))
-#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
-#define SPI_SIO_V  0x00000001U
-#define SPI_SIO_S  17
-/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
- *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
- *  disable. Can be configured in CONF state.
- */
-#define SPI_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
-#define SPI_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_USR_MISO_HIGHPART_S  24
-/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
- *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
- *  0: disable.  Can be configured in CONF state.
- */
-#define SPI_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
-#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_USR_MOSI_HIGHPART_S  25
-/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
- *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
- *  CONF state.
- */
-#define SPI_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
-#define SPI_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_USR_DUMMY_IDLE_S  26
-/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
- *  This bit enable the write-data phase of an operation. Can be configured in CONF
- *  state.
- */
-#define SPI_USR_MOSI    (BIT(27))
-#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
-#define SPI_USR_MOSI_V  0x00000001U
-#define SPI_USR_MOSI_S  27
-/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
- *  This bit enable the read-data phase of an operation. Can be configured in CONF
- *  state.
- */
-#define SPI_USR_MISO    (BIT(28))
-#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
-#define SPI_USR_MISO_V  0x00000001U
-#define SPI_USR_MISO_S  28
-/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
- *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY    (BIT(29))
-#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
-#define SPI_USR_DUMMY_V  0x00000001U
-#define SPI_USR_DUMMY_S  29
-/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
- *  This bit enable the address phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_ADDR    (BIT(30))
-#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
-#define SPI_USR_ADDR_V  0x00000001U
-#define SPI_USR_ADDR_S  30
-/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
- *  This bit enable the command phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND    (BIT(31))
-#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
-#define SPI_USR_COMMAND_V  0x00000001U
-#define SPI_USR_COMMAND_S  31
-
-/** SPI_USER1_REG register
- *  SPI USER control register 1
- */
-#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14)
-/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
- *  The length in spi_clk cycles of dummy phase. The register value shall be
- *  (cycle_num-1). Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
-#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
- *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
- *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
- *  GP-SPI master FD/HD-mode.
- */
-#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
-#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
-#define SPI_MST_WFULL_ERR_END_EN_S  16
-/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
- *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
- *  bit. Can be configured in CONF state.
- */
-#define SPI_CS_SETUP_TIME    0x0000001FU
-#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
-#define SPI_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_CS_SETUP_TIME_S  17
-/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
- *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
- *  Can be configured in CONF state.
- */
-#define SPI_CS_HOLD_TIME    0x0000001FU
-#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
-#define SPI_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_CS_HOLD_TIME_S  22
-/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
- *  The length in bits of address phase. The register value shall be (bit_num-1). Can
- *  be configured in CONF state.
- */
-#define SPI_USR_ADDR_BITLEN    0x0000001FU
-#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
-#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
-#define SPI_USR_ADDR_BITLEN_S  27
-
-/** SPI_USER2_REG register
- *  SPI USER control register 2
- */
-#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18)
-/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
- *  The value of  command. Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
-#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_S  0
-/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
- *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
- *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
- *  is valid in GP-SPI master FD/HD-mode.
- */
-#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
-#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
-#define SPI_MST_REMPTY_ERR_END_EN_S  27
-/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
- *  The length in bits of command phase. The register value shall be (bit_num-1). Can
- *  be configured in CONF state.
- */
-#define SPI_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
-#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_S  28
-
-/** SPI_MS_DLEN_REG register
- *  SPI data bit length control register
- */
-#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c)
-/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  The value of these bits is the configured SPI transmission data bit length in
- *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
- *  the configured bit length in slave mode DMA RX controlled transfer. The register
- *  value shall be (bit_num-1). Can be configured in CONF state.
- */
-#define SPI_MS_DATA_BITLEN    0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
-#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_S  0
-
-/** SPI_MISC_REG register
- *  SPI misc register
- */
-#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20)
-/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS0_DIS    (BIT(0))
-#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
-#define SPI_CS0_DIS_V  0x00000001U
-#define SPI_CS0_DIS_S  0
-/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS1_DIS    (BIT(1))
-#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
-#define SPI_CS1_DIS_V  0x00000001U
-#define SPI_CS1_DIS_S  1
-/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS2_DIS    (BIT(2))
-#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
-#define SPI_CS2_DIS_V  0x00000001U
-#define SPI_CS2_DIS_S  2
-/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS3_DIS    (BIT(3))
-#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
-#define SPI_CS3_DIS_V  0x00000001U
-#define SPI_CS3_DIS_S  3
-/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS4_DIS    (BIT(4))
-#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
-#define SPI_CS4_DIS_V  0x00000001U
-#define SPI_CS4_DIS_S  4
-/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS5_DIS    (BIT(5))
-#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
-#define SPI_CS5_DIS_V  0x00000001U
-#define SPI_CS5_DIS_S  5
-/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
- *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
- */
-#define SPI_CK_DIS    (BIT(6))
-#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
-#define SPI_CK_DIS_V  0x00000001U
-#define SPI_CK_DIS_S  6
-/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
- *  In the master mode the bits are the polarity of spi cs line, the value is
- *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
- */
-#define SPI_MASTER_CS_POL    0x0000003FU
-#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
-#define SPI_MASTER_CS_POL_V  0x0000003FU
-#define SPI_MASTER_CS_POL_S  7
-/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0;
- *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
- *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
- */
-#define SPI_CLK_DATA_DTR_EN    (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
-#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
-#define SPI_CLK_DATA_DTR_EN_S  16
-/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0;
- *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
- *  Can be configured in CONF state.
- */
-#define SPI_DATA_DTR_EN    (BIT(17))
-#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
-#define SPI_DATA_DTR_EN_V  0x00000001U
-#define SPI_DATA_DTR_EN_S  17
-/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0;
- *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
- *  configured in CONF state.
- */
-#define SPI_ADDR_DTR_EN    (BIT(18))
-#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
-#define SPI_ADDR_DTR_EN_V  0x00000001U
-#define SPI_ADDR_DTR_EN_S  18
-/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0;
- *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
- *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
- *  configured in CONF state.
- */
-#define SPI_CMD_DTR_EN    (BIT(19))
-#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
-#define SPI_CMD_DTR_EN_V  0x00000001U
-#define SPI_CMD_DTR_EN_S  19
-/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
- *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
- *  CONF state.
- */
-#define SPI_SLAVE_CS_POL    (BIT(23))
-#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
-#define SPI_SLAVE_CS_POL_V  0x00000001U
-#define SPI_SLAVE_CS_POL_S  23
-/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0;
- *  The default value of spi_dqs. Can be configured in CONF state.
- */
-#define SPI_DQS_IDLE_EDGE    (BIT(24))
-#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
-#define SPI_DQS_IDLE_EDGE_V  0x00000001U
-#define SPI_DQS_IDLE_EDGE_S  24
-/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
- *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
- *  configured in CONF state.
- */
-#define SPI_CK_IDLE_EDGE    (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
-#define SPI_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_CK_IDLE_EDGE_S  29
-/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
- *  spi cs line keep low when the bit is set. Can be configured in CONF state.
- */
-#define SPI_CS_KEEP_ACTIVE    (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
-#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_CS_KEEP_ACTIVE_S  30
-/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
- *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
- *  spi quad input swap disable. Can be configured in CONF state.
- */
-#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
-#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
-#define SPI_QUAD_DIN_PIN_SWAP_S  31
-
-/** SPI_DIN_MODE_REG register
- *  SPI input delay mode configuration
- */
-#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24)
-/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN0_MODE    0x00000003U
-#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
-#define SPI_DIN0_MODE_V  0x00000003U
-#define SPI_DIN0_MODE_S  0
-/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN1_MODE    0x00000003U
-#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
-#define SPI_DIN1_MODE_V  0x00000003U
-#define SPI_DIN1_MODE_S  2
-/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN2_MODE    0x00000003U
-#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
-#define SPI_DIN2_MODE_V  0x00000003U
-#define SPI_DIN2_MODE_S  4
-/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN3_MODE    0x00000003U
-#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
-#define SPI_DIN3_MODE_V  0x00000003U
-#define SPI_DIN3_MODE_S  6
-/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN4_MODE    0x00000003U
-#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
-#define SPI_DIN4_MODE_V  0x00000003U
-#define SPI_DIN4_MODE_S  8
-/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the
- *  (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
- *  3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
- *  falling edge cycle. Can be configured in CONF state.
- */
-#define SPI_DIN5_MODE    0x00000003U
-#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
-#define SPI_DIN5_MODE_V  0x00000003U
-#define SPI_DIN5_MODE_S  10
-/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the
- *  (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
- *  3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
- *  falling edge cycle. Can be configured in CONF state.
- */
-#define SPI_DIN6_MODE    0x00000003U
-#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
-#define SPI_DIN6_MODE_V  0x00000003U
-#define SPI_DIN6_MODE_S  12
-/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the
- *  (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
- *  3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
- *  falling edge cycle. Can be configured in CONF state.
- */
-#define SPI_DIN7_MODE    0x00000003U
-#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
-#define SPI_DIN7_MODE_V  0x00000003U
-#define SPI_DIN7_MODE_S  14
-/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
- *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
- *  state.
- */
-#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
-#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
-#define SPI_TIMING_HCLK_ACTIVE_S  16
-
-/** SPI_DIN_NUM_REG register
- *  SPI input delay number configuration
- */
-#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28)
-/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN0_NUM    0x00000003U
-#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
-#define SPI_DIN0_NUM_V  0x00000003U
-#define SPI_DIN0_NUM_S  0
-/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN1_NUM    0x00000003U
-#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
-#define SPI_DIN1_NUM_V  0x00000003U
-#define SPI_DIN1_NUM_S  2
-/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN2_NUM    0x00000003U
-#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
-#define SPI_DIN2_NUM_V  0x00000003U
-#define SPI_DIN2_NUM_S  4
-/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN3_NUM    0x00000003U
-#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
-#define SPI_DIN3_NUM_V  0x00000003U
-#define SPI_DIN3_NUM_S  6
-/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN4_NUM    0x00000003U
-#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
-#define SPI_DIN4_NUM_V  0x00000003U
-#define SPI_DIN4_NUM_S  8
-/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN5_NUM    0x00000003U
-#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
-#define SPI_DIN5_NUM_V  0x00000003U
-#define SPI_DIN5_NUM_S  10
-/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN6_NUM    0x00000003U
-#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
-#define SPI_DIN6_NUM_V  0x00000003U
-#define SPI_DIN6_NUM_S  12
-/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN7_NUM    0x00000003U
-#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
-#define SPI_DIN7_NUM_V  0x00000003U
-#define SPI_DIN7_NUM_S  14
-
-/** SPI_DOUT_MODE_REG register
- *  SPI output delay mode configuration
- */
-#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c)
-/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT0_MODE    (BIT(0))
-#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
-#define SPI_DOUT0_MODE_V  0x00000001U
-#define SPI_DOUT0_MODE_S  0
-/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT1_MODE    (BIT(1))
-#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
-#define SPI_DOUT1_MODE_V  0x00000001U
-#define SPI_DOUT1_MODE_S  1
-/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT2_MODE    (BIT(2))
-#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
-#define SPI_DOUT2_MODE_V  0x00000001U
-#define SPI_DOUT2_MODE_S  2
-/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT3_MODE    (BIT(3))
-#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
-#define SPI_DOUT3_MODE_V  0x00000001U
-#define SPI_DOUT3_MODE_S  3
-/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT4_MODE    (BIT(4))
-#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
-#define SPI_DOUT4_MODE_V  0x00000001U
-#define SPI_DOUT4_MODE_S  4
-/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT5_MODE    (BIT(5))
-#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
-#define SPI_DOUT5_MODE_V  0x00000001U
-#define SPI_DOUT5_MODE_S  5
-/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT6_MODE    (BIT(6))
-#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
-#define SPI_DOUT6_MODE_V  0x00000001U
-#define SPI_DOUT6_MODE_S  6
-/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT7_MODE    (BIT(7))
-#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
-#define SPI_DOUT7_MODE_V  0x00000001U
-#define SPI_DOUT7_MODE_S  7
-/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0;
- *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
- *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_D_DQS_MODE    (BIT(8))
-#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
-#define SPI_D_DQS_MODE_V  0x00000001U
-#define SPI_D_DQS_MODE_S  8
-
-/** SPI_DMA_CONF_REG register
- *  SPI DMA control register
- */
-#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30)
-/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
- *  DMA TX FIFO is ready for sending data.
- */
-#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
-#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_S  0
-/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
- *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
- *  0: DMA RX FIFO is ready for receiving data.
- */
-#define SPI_DMA_INFIFO_FULL    (BIT(1))
-#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
-#define SPI_DMA_INFIFO_FULL_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_S  1
-/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
- *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
- */
-#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
-#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
-#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
-/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
- *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
- */
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
-/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
- *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
- */
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
-/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
- *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
- *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
- *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
- *  spi_dma_seg_trans_done in seg-trans.
- */
-#define SPI_RX_EOF_EN    (BIT(21))
-#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
-#define SPI_RX_EOF_EN_V  0x00000001U
-#define SPI_RX_EOF_EN_S  21
-/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
- *  Set this bit to enable SPI DMA controlled receive data mode.
- */
-#define SPI_DMA_RX_ENA    (BIT(27))
-#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
-#define SPI_DMA_RX_ENA_V  0x00000001U
-#define SPI_DMA_RX_ENA_S  27
-/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
- *  Set this bit to enable SPI DMA controlled send data mode.
- */
-#define SPI_DMA_TX_ENA    (BIT(28))
-#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
-#define SPI_DMA_TX_ENA_V  0x00000001U
-#define SPI_DMA_TX_ENA_S  28
-/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
- *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
- *  slave mode transfer.
- */
-#define SPI_RX_AFIFO_RST    (BIT(29))
-#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
-#define SPI_RX_AFIFO_RST_V  0x00000001U
-#define SPI_RX_AFIFO_RST_S  29
-/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
- *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
- *  controlled mode transfer and master mode transfer.
- */
-#define SPI_BUF_AFIFO_RST    (BIT(30))
-#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
-#define SPI_BUF_AFIFO_RST_V  0x00000001U
-#define SPI_BUF_AFIFO_RST_S  30
-/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
- *  controlled mode transfer.
- */
-#define SPI_DMA_AFIFO_RST    (BIT(31))
-#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
-#define SPI_DMA_AFIFO_RST_V  0x00000001U
-#define SPI_DMA_AFIFO_RST_S  31
-
-/** SPI_DMA_INT_ENA_REG register
- *  SPI interrupt enable register
- */
-#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
-/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
-#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ENA_S  2
-/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
-#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ENA_S  3
-/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
-#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ENA_S  4
-/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The enable bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
-#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ENA_S  5
-/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
-#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ENA_S  6
-/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
-#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ENA_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
-/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The enable bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
-#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ENA_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
-#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
-/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
-#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ENA_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
-/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  The enable bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ENA    (BIT(19))
-#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
-#define SPI_APP2_INT_ENA_V  0x00000001U
-#define SPI_APP2_INT_ENA_S  19
-/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  The enable bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ENA    (BIT(20))
-#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
-#define SPI_APP1_INT_ENA_V  0x00000001U
-#define SPI_APP1_INT_ENA_S  20
-
-/** SPI_DMA_INT_CLR_REG register
- *  SPI interrupt clear register
- */
-#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
-/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
-#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_CLR_S  2
-/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
-#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_CLR_S  3
-/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
-#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD7_INT_CLR_S  4
-/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The clear bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
-#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD8_INT_CLR_S  5
-/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The clear bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
-#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD9_INT_CLR_S  6
-/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
- *  The clear bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
-#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMDA_INT_CLR_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
- *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
- *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
- *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
-/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  The clear bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
-#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_TRANS_DONE_INT_CLR_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
-/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
-#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
-/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
-#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_CLR_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
- *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
- *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
-/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
- *  The clear bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_CLR    (BIT(19))
-#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
-#define SPI_APP2_INT_CLR_V  0x00000001U
-#define SPI_APP2_INT_CLR_S  19
-/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  The clear bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_CLR    (BIT(20))
-#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
-#define SPI_APP1_INT_CLR_V  0x00000001U
-#define SPI_APP1_INT_CLR_S  20
-
-/** SPI_DMA_INT_RAW_REG register
- *  SPI interrupt raw register
- */
-#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
- *  receive data.  0: Others.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
- *  master mode and send out all 0 in slave mode.  0: Others.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
-/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
- *  is ended. 0: Others.
- */
-#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
-#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_RAW_S  2
-/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
- *  is ended. 0: Others.
- */
-#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
-#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_RAW_S  3
-/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
-#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD7_INT_RAW_S  4
-/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
-#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD8_INT_RAW_S  5
-/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
-#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD9_INT_RAW_S  6
-/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
-#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMDA_INT_RAW_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
-/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
- *  ended. 0: others.
- */
-#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
-#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_TRANS_DONE_INT_RAW_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
- *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
- *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
- *  is not ended or not occurred.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
-/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
- *  is error in the DMA seg-conf-trans. 0: others.
- */
-#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
-#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
- *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
- *  bigger than 63. 0: Others.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
-/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
- *  current SPI slave HD mode transmission is not supported. 0: Others.
- */
-#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
-#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_RAW_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
- *  write-full error when SPI inputs data in master mode. 0: Others.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
- *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
-/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
- */
-#define SPI_APP2_INT_RAW    (BIT(19))
-#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
-#define SPI_APP2_INT_RAW_V  0x00000001U
-#define SPI_APP2_INT_RAW_S  19
-/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
- */
-#define SPI_APP1_INT_RAW    (BIT(20))
-#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
-#define SPI_APP1_INT_RAW_V  0x00000001U
-#define SPI_APP1_INT_RAW_S  20
-
-/** SPI_DMA_INT_ST_REG register
- *  SPI interrupt status register
- */
-#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
-/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
-#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ST_S  2
-/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
-#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ST_S  3
-/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_ST    (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
-#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ST_S  4
-/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
- *  The status bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_ST    (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
-#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ST_S  5
-/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
- *  The status bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_ST    (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
-#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ST_S  6
-/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
- *  The status bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_ST    (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
-#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ST_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
- *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
- *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
- *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
-/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  The status bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ST    (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
-#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ST_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
- *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
-#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
-/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
-#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ST_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
- *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
- *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
-/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
- *  The status bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ST    (BIT(19))
-#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
-#define SPI_APP2_INT_ST_V  0x00000001U
-#define SPI_APP2_INT_ST_S  19
-/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
- *  The status bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ST    (BIT(20))
-#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
-#define SPI_APP1_INT_ST_V  0x00000001U
-#define SPI_APP1_INT_ST_S  20
-
-/** SPI_DMA_INT_SET_REG register
- *  SPI interrupt software set register
- */
-#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
- *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
- *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
-/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
- *  The software set bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
-#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_SET_S  2
-/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
- *  The software set bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
-#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_SET_S  3
-/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
- *  The software set bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_SET    (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
-#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD7_INT_SET_S  4
-/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
- *  The software set bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_SET    (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
-#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD8_INT_SET_S  5
-/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
- *  The software set bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_SET    (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
-#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD9_INT_SET_S  6
-/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
- *  The software set bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_SET    (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
-#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
-#define SPI_SLV_CMDA_INT_SET_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
- *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
-#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
- *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
-#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
- *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
-#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
- *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
-#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
-/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
- *  The software set bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_SET    (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
-#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_TRANS_DONE_INT_SET_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
- *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
-/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
- *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
-#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
- *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
-/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
- *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
-#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_SET_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
- *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
- *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
-/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
- *  The software set bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_SET    (BIT(19))
-#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
-#define SPI_APP2_INT_SET_V  0x00000001U
-#define SPI_APP2_INT_SET_S  19
-/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
- *  The software set bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_SET    (BIT(20))
-#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
-#define SPI_APP1_INT_SET_V  0x00000001U
-#define SPI_APP1_INT_SET_S  20
-
-/** SPI_W0_REG register
- *  SPI CPU-controlled buffer0
- */
-#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98)
-/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF0    0xFFFFFFFFU
-#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
-#define SPI_BUF0_V  0xFFFFFFFFU
-#define SPI_BUF0_S  0
-
-/** SPI_W1_REG register
- *  SPI CPU-controlled buffer1
- */
-#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c)
-/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF1    0xFFFFFFFFU
-#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
-#define SPI_BUF1_V  0xFFFFFFFFU
-#define SPI_BUF1_S  0
-
-/** SPI_W2_REG register
- *  SPI CPU-controlled buffer2
- */
-#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0)
-/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF2    0xFFFFFFFFU
-#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
-#define SPI_BUF2_V  0xFFFFFFFFU
-#define SPI_BUF2_S  0
-
-/** SPI_W3_REG register
- *  SPI CPU-controlled buffer3
- */
-#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4)
-/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF3    0xFFFFFFFFU
-#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
-#define SPI_BUF3_V  0xFFFFFFFFU
-#define SPI_BUF3_S  0
-
-/** SPI_W4_REG register
- *  SPI CPU-controlled buffer4
- */
-#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8)
-/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF4    0xFFFFFFFFU
-#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
-#define SPI_BUF4_V  0xFFFFFFFFU
-#define SPI_BUF4_S  0
-
-/** SPI_W5_REG register
- *  SPI CPU-controlled buffer5
- */
-#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac)
-/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF5    0xFFFFFFFFU
-#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
-#define SPI_BUF5_V  0xFFFFFFFFU
-#define SPI_BUF5_S  0
-
-/** SPI_W6_REG register
- *  SPI CPU-controlled buffer6
- */
-#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0)
-/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF6    0xFFFFFFFFU
-#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
-#define SPI_BUF6_V  0xFFFFFFFFU
-#define SPI_BUF6_S  0
-
-/** SPI_W7_REG register
- *  SPI CPU-controlled buffer7
- */
-#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4)
-/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF7    0xFFFFFFFFU
-#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
-#define SPI_BUF7_V  0xFFFFFFFFU
-#define SPI_BUF7_S  0
-
-/** SPI_W8_REG register
- *  SPI CPU-controlled buffer8
- */
-#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8)
-/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF8    0xFFFFFFFFU
-#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
-#define SPI_BUF8_V  0xFFFFFFFFU
-#define SPI_BUF8_S  0
-
-/** SPI_W9_REG register
- *  SPI CPU-controlled buffer9
- */
-#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc)
-/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF9    0xFFFFFFFFU
-#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
-#define SPI_BUF9_V  0xFFFFFFFFU
-#define SPI_BUF9_S  0
-
-/** SPI_W10_REG register
- *  SPI CPU-controlled buffer10
- */
-#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0)
-/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF10    0xFFFFFFFFU
-#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
-#define SPI_BUF10_V  0xFFFFFFFFU
-#define SPI_BUF10_S  0
-
-/** SPI_W11_REG register
- *  SPI CPU-controlled buffer11
- */
-#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4)
-/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF11    0xFFFFFFFFU
-#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
-#define SPI_BUF11_V  0xFFFFFFFFU
-#define SPI_BUF11_S  0
-
-/** SPI_W12_REG register
- *  SPI CPU-controlled buffer12
- */
-#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8)
-/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF12    0xFFFFFFFFU
-#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
-#define SPI_BUF12_V  0xFFFFFFFFU
-#define SPI_BUF12_S  0
-
-/** SPI_W13_REG register
- *  SPI CPU-controlled buffer13
- */
-#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc)
-/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF13    0xFFFFFFFFU
-#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
-#define SPI_BUF13_V  0xFFFFFFFFU
-#define SPI_BUF13_S  0
-
-/** SPI_W14_REG register
- *  SPI CPU-controlled buffer14
- */
-#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0)
-/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF14    0xFFFFFFFFU
-#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
-#define SPI_BUF14_V  0xFFFFFFFFU
-#define SPI_BUF14_S  0
-
-/** SPI_W15_REG register
- *  SPI CPU-controlled buffer15
- */
-#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4)
-/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF15    0xFFFFFFFFU
-#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
-#define SPI_BUF15_V  0xFFFFFFFFU
-#define SPI_BUF15_S  0
-
-/** SPI_SLAVE_REG register
- *  SPI slave control register
- */
-#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0)
-/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
- *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on. Can be configured in CONF state.
- */
-#define SPI_CLK_MODE    0x00000003U
-#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
-#define SPI_CLK_MODE_V  0x00000003U
-#define SPI_CLK_MODE_S  0
-/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
- *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
- *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
- */
-#define SPI_CLK_MODE_13    (BIT(2))
-#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
-#define SPI_CLK_MODE_13_V  0x00000001U
-#define SPI_CLK_MODE_13_S  2
-/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
- *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
- *  0: output data at tsck posedge
- */
-#define SPI_RSCK_DATA_OUT    (BIT(3))
-#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
-#define SPI_RSCK_DATA_OUT_V  0x00000001U
-#define SPI_RSCK_DATA_OUT_S  3
-/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
- *  DMA controlled mode(Rd_DMA). 0: others
- */
-#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
-#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDDMA_BITLEN_EN_S  8
-/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
- *  in DMA controlled mode(Wr_DMA). 0: others
- */
-#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
-#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRDMA_BITLEN_EN_S  9
-/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
- *  CPU controlled mode(Rd_BUF). 0: others
- */
-#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
-#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDBUF_BITLEN_EN_S  10
-/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
- *  in CPU controlled mode(Wr_BUF). 0: others
- */
-#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
-#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRBUF_BITLEN_EN_S  11
-/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
- *  The magic value of BM table in master DMA seg-trans.
- */
-#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
-#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_S  22
-/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
- *  Set SPI work mode. 1: slave mode 0: master mode.
- */
-#define SPI_SLAVE_MODE    (BIT(26))
-#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
-#define SPI_SLAVE_MODE_V  0x00000001U
-#define SPI_SLAVE_MODE_S  26
-/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
- *  Software reset enable, reset the spi clock line cs line and data lines. Can be
- *  configured in CONF state.
- */
-#define SPI_SOFT_RESET    (BIT(27))
-#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
-#define SPI_SOFT_RESET_V  0x00000001U
-#define SPI_SOFT_RESET_S  27
-/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
- *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
- *  will start. 0: This is not seg-trans mode.
- */
-#define SPI_USR_CONF    (BIT(28))
-#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
-#define SPI_USR_CONF_V  0x00000001U
-#define SPI_USR_CONF_S  28
-/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
- *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
- *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
- *  transfer.
- */
-#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
-
-/** SPI_SLAVE1_REG register
- *  SPI slave control register 1
- */
-#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4)
-/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
- *  The transferred data bit length in SPI slave FD and HD mode.
- */
-#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
-#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_S  0
-/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
- *  In the slave mode it is the value of command.
- */
-#define SPI_SLV_LAST_COMMAND    0x000000FFU
-#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
-#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
-#define SPI_SLV_LAST_COMMAND_S  18
-/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
- *  In the slave mode it is the value of address.
- */
-#define SPI_SLV_LAST_ADDR    0x0000003FU
-#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
-#define SPI_SLV_LAST_ADDR_V  0x0000003FU
-#define SPI_SLV_LAST_ADDR_S  26
-
-/** SPI_CLK_GATE_REG register
- *  SPI module clock and register clock control
- */
-#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8)
-/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable clk gate
- */
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
-#define SPI_CLK_EN_V  0x00000001U
-#define SPI_CLK_EN_S  0
-/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
- *  Set this bit to power on the SPI module clock.
- */
-#define SPI_MST_CLK_ACTIVE    (BIT(1))
-#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
-#define SPI_MST_CLK_ACTIVE_V  0x00000001U
-#define SPI_MST_CLK_ACTIVE_S  1
-/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
- *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
- *  0: XTAL CLK.
- */
-#define SPI_MST_CLK_SEL    (BIT(2))
-#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
-#define SPI_MST_CLK_SEL_V  0x00000001U
-#define SPI_MST_CLK_SEL_S  2
-
-/** SPI_DATE_REG register
- *  Version control
- */
-#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0)
-/** SPI_DATE : R/W; bitpos: [27:0]; default: 35656448;
- *  SPI register version.
- */
-#define SPI_DATE    0x0FFFFFFFU
-#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
-#define SPI_DATE_V  0x0FFFFFFFU
-#define SPI_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/spi_struct.h b/components/soc/esp32h2/include/soc/spi_struct.h
deleted file mode 100644
index de7705f92c9..00000000000
--- a/components/soc/esp32h2/include/soc/spi_struct.h
+++ /dev/null
@@ -1,1406 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: User-defined control registers */
-/** Type of cmd register
- *  Command control register
- */
-typedef union {
-    struct {
-        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
-         */
-        uint32_t conf_bitlen:18;
-        uint32_t reserved_18:5;
-        /** update : WT; bitpos: [23]; default: 0;
-         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
-         *  clock domain, which is only used in SPI master mode.
-         */
-        uint32_t update:1;
-        /** usr : R/W/SC; bitpos: [24]; default: 0;
-         *  User define command enable.  An operation will be triggered when the bit is set.
-         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
-         *  changed by CONF_buf.
-         */
-        uint32_t usr:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} spi_cmd_reg_t;
-
-/** Type of addr register
- *  Address value register
- */
-typedef union {
-    struct {
-        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
-         *  Address to slave. Can be configured in CONF state.
-         */
-        uint32_t usr_addr_value:32;
-    };
-    uint32_t val;
-} spi_addr_reg_t;
-
-/** Type of user register
- *  SPI USER control register
- */
-typedef union {
-    struct {
-        /** doutdin : R/W; bitpos: [0]; default: 0;
-         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t doutdin:1;
-        uint32_t reserved_1:2;
-        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
-         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t qpi_mode:1;
-        /** opi_mode : HRO; bitpos: [4]; default: 0;
-         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t opi_mode:1;
-        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
-         *  spi_ck_i. 1:tsck = !spi_ck_i.
-         */
-        uint32_t tsck_i_edge:1;
-        /** cs_hold : R/W; bitpos: [6]; default: 1;
-         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_hold:1;
-        /** cs_setup : R/W; bitpos: [7]; default: 1;
-         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_setup:1;
-        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
-         *  !spi_ck_i. 1:rsck = spi_ck_i.
-         */
-        uint32_t rsck_i_edge:1;
-        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
-         *  be configured in CONF state.
-         */
-        uint32_t ck_out_edge:1;
-        uint32_t reserved_10:2;
-        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
-         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_dual:1;
-        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
-         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_quad:1;
-        /** fwrite_oct : HRO; bitpos: [14]; default: 0;
-         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_oct:1;
-        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
-         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
-         *  not seg-trans mode. Can be configured in CONF state.
-         */
-        uint32_t usr_conf_nxt:1;
-        uint32_t reserved_16:1;
-        /** sio : R/W; bitpos: [17]; default: 0;
-         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
-         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
-         */
-        uint32_t sio:1;
-        uint32_t reserved_18:6;
-        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
-         *  disable. Can be configured in CONF state.
-         */
-        uint32_t usr_miso_highpart:1;
-        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
-         *  0: disable.  Can be configured in CONF state.
-         */
-        uint32_t usr_mosi_highpart:1;
-        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
-         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
-         *  CONF state.
-         */
-        uint32_t usr_dummy_idle:1;
-        /** usr_mosi : R/W; bitpos: [27]; default: 0;
-         *  This bit enable the write-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_mosi:1;
-        /** usr_miso : R/W; bitpos: [28]; default: 0;
-         *  This bit enable the read-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_miso:1;
-        /** usr_dummy : R/W; bitpos: [29]; default: 0;
-         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_dummy:1;
-        /** usr_addr : R/W; bitpos: [30]; default: 0;
-         *  This bit enable the address phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_addr:1;
-        /** usr_command : R/W; bitpos: [31]; default: 1;
-         *  This bit enable the command phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_command:1;
-    };
-    uint32_t val;
-} spi_user_reg_t;
-
-/** Type of user1 register
- *  SPI USER control register 1
- */
-typedef union {
-    struct {
-        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
-         *  The length in spi_clk cycles of dummy phase. The register value shall be
-         *  (cycle_num-1). Can be configured in CONF state.
-         */
-        uint32_t usr_dummy_cyclelen:8;
-        uint32_t reserved_8:8;
-        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
-         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
-         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
-         *  GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_wfull_err_end_en:1;
-        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
-         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
-         *  bit. Can be configured in CONF state.
-         */
-        uint32_t cs_setup_time:5;
-        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
-         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs_hold_time:5;
-        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
-         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_addr_bitlen:5;
-    };
-    uint32_t val;
-} spi_user1_reg_t;
-
-/** Type of user2 register
- *  SPI USER control register 2
- */
-typedef union {
-    struct {
-        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
-         *  The value of  command. Can be configured in CONF state.
-         */
-        uint32_t usr_command_value:16;
-        uint32_t reserved_16:11;
-        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
-         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
-         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
-         *  is valid in GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_rempty_err_end_en:1;
-        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
-         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_command_bitlen:4;
-    };
-    uint32_t val;
-} spi_user2_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of ctrl register
- *  SPI control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** dummy_out : R/W; bitpos: [3]; default: 0;
-         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
-         *  the FSPI bus signals are output. Can be configured in CONF state.
-         */
-        uint32_t dummy_out:1;
-        uint32_t reserved_4:1;
-        /** faddr_dual : R/W; bitpos: [5]; default: 0;
-         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_dual:1;
-        /** faddr_quad : R/W; bitpos: [6]; default: 0;
-         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_quad:1;
-        /** faddr_oct : HRO; bitpos: [7]; default: 0;
-         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_oct:1;
-        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
-         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_dual:1;
-        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
-         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_quad:1;
-        /** fcmd_oct : HRO; bitpos: [10]; default: 0;
-         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_oct:1;
-        uint32_t reserved_11:3;
-        /** fread_dual : R/W; bitpos: [14]; default: 0;
-         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_dual:1;
-        /** fread_quad : R/W; bitpos: [15]; default: 0;
-         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_quad:1;
-        /** fread_oct : HRO; bitpos: [16]; default: 0;
-         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_oct:1;
-        uint32_t reserved_17:1;
-        /** q_pol : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t q_pol:1;
-        /** d_pol : R/W; bitpos: [19]; default: 1;
-         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t d_pol:1;
-        /** hold_pol : R/W; bitpos: [20]; default: 1;
-         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
-         *  configured in CONF state.
-         */
-        uint32_t hold_pol:1;
-        /** wp_pol : R/W; bitpos: [21]; default: 1;
-         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t wp_pol:1;
-        uint32_t reserved_22:1;
-        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
-         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
-         *  state.
-         */
-        uint32_t rd_bit_order:2;
-        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
-         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
-         *  configured in CONF state.
-         */
-        uint32_t wr_bit_order:2;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} spi_ctrl_reg_t;
-
-/** Type of ms_dlen register
- *  SPI data bit length control register
- */
-typedef union {
-    struct {
-        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  The value of these bits is the configured SPI transmission data bit length in
-         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
-         *  the configured bit length in slave mode DMA RX controlled transfer. The register
-         *  value shall be (bit_num-1). Can be configured in CONF state.
-         */
-        uint32_t ms_data_bitlen:18;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} spi_ms_dlen_reg_t;
-
-/** Type of misc register
- *  SPI misc register
- */
-typedef union {
-    struct {
-        /** cs0_dis : R/W; bitpos: [0]; default: 0;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs0_dis:1;
-        /** cs1_dis : R/W; bitpos: [1]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs1_dis:1;
-        /** cs2_dis : R/W; bitpos: [2]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs2_dis:1;
-        /** cs3_dis : R/W; bitpos: [3]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs3_dis:1;
-        /** cs4_dis : R/W; bitpos: [4]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs4_dis:1;
-        /** cs5_dis : R/W; bitpos: [5]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs5_dis:1;
-        /** ck_dis : R/W; bitpos: [6]; default: 0;
-         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
-         */
-        uint32_t ck_dis:1;
-        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
-         *  In the master mode the bits are the polarity of spi cs line, the value is
-         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-         */
-        uint32_t master_cs_pol:6;
-        uint32_t reserved_13:3;
-        /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0;
-         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
-         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
-         */
-        uint32_t clk_data_dtr_en:1;
-        /** data_dtr_en : HRO; bitpos: [17]; default: 0;
-         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
-         *  Can be configured in CONF state.
-         */
-        uint32_t data_dtr_en:1;
-        /** addr_dtr_en : HRO; bitpos: [18]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t addr_dtr_en:1;
-        /** cmd_dtr_en : HRO; bitpos: [19]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
-         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cmd_dtr_en:1;
-        uint32_t reserved_20:3;
-        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
-         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
-         *  CONF state.
-         */
-        uint32_t slave_cs_pol:1;
-        /** dqs_idle_edge : HRO; bitpos: [24]; default: 0;
-         *  The default value of spi_dqs. Can be configured in CONF state.
-         */
-        uint32_t dqs_idle_edge:1;
-        uint32_t reserved_25:4;
-        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
-         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
-         *  configured in CONF state.
-         */
-        uint32_t ck_idle_edge:1;
-        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
-         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
-         */
-        uint32_t cs_keep_active:1;
-        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
-         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
-         *  spi quad input swap disable. Can be configured in CONF state.
-         */
-        uint32_t quad_din_pin_swap:1;
-    };
-    uint32_t val;
-} spi_misc_reg_t;
-
-/** Type of dma_conf register
- *  SPI DMA control register
- */
-typedef union {
-    struct {
-        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
-         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
-         *  DMA TX FIFO is ready for sending data.
-         */
-        uint32_t dma_outfifo_empty:1;
-        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
-         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
-         *  0: DMA RX FIFO is ready for receiving data.
-         */
-        uint32_t dma_infifo_full:1;
-        uint32_t reserved_2:16;
-        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
-         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-         */
-        uint32_t dma_slv_seg_trans_en:1;
-        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
-         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
-         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_rx_seg_trans_clr_en:1;
-        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
-         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
-         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_tx_seg_trans_clr_en:1;
-        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
-         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
-         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
-         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
-         *  spi_dma_seg_trans_done in seg-trans.
-         */
-        uint32_t rx_eof_en:1;
-        uint32_t reserved_22:5;
-        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
-         *  Set this bit to enable SPI DMA controlled receive data mode.
-         */
-        uint32_t dma_rx_ena:1;
-        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to enable SPI DMA controlled send data mode.
-         */
-        uint32_t dma_tx_ena:1;
-        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
-         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-         *  slave mode transfer.
-         */
-        uint32_t rx_afifo_rst:1;
-        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
-         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
-         *  controlled mode transfer and master mode transfer.
-         */
-        uint32_t buf_afifo_rst:1;
-        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
-         *  controlled mode transfer.
-         */
-        uint32_t dma_afifo_rst:1;
-    };
-    uint32_t val;
-} spi_dma_conf_reg_t;
-
-/** Type of slave register
- *  SPI slave control register
- */
-typedef union {
-    struct {
-        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
-         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
-         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on. Can be configured in CONF state.
-         */
-        uint32_t clk_mode:2;
-        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
-         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
-         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-         */
-        uint32_t clk_mode_13:1;
-        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
-         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
-         *  0: output data at tsck posedge
-         */
-        uint32_t rsck_data_out:1;
-        uint32_t reserved_4:4;
-        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  DMA controlled mode(Rd_DMA). 0: others
-         */
-        uint32_t slv_rddma_bitlen_en:1;
-        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in DMA controlled mode(Wr_DMA). 0: others
-         */
-        uint32_t slv_wrdma_bitlen_en:1;
-        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  CPU controlled mode(Rd_BUF). 0: others
-         */
-        uint32_t slv_rdbuf_bitlen_en:1;
-        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in CPU controlled mode(Wr_BUF). 0: others
-         */
-        uint32_t slv_wrbuf_bitlen_en:1;
-        uint32_t reserved_12:10;
-        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
-         *  The magic value of BM table in master DMA seg-trans.
-         */
-        uint32_t dma_seg_magic_value:4;
-        /** slave_mode : R/W; bitpos: [26]; default: 0;
-         *  Set SPI work mode. 1: slave mode 0: master mode.
-         */
-        uint32_t slave_mode:1;
-        /** soft_reset : WT; bitpos: [27]; default: 0;
-         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
-         *  configured in CONF state.
-         */
-        uint32_t soft_reset:1;
-        /** usr_conf : R/W; bitpos: [28]; default: 0;
-         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
-         *  will start. 0: This is not seg-trans mode.
-         */
-        uint32_t usr_conf:1;
-        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
-         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
-         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
-         *  transfer.
-         */
-        uint32_t mst_fd_wait_dma_tx_data:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} spi_slave_reg_t;
-
-/** Type of slave1 register
- *  SPI slave control register 1
- */
-typedef union {
-    struct {
-        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
-         *  The transferred data bit length in SPI slave FD and HD mode.
-         */
-        uint32_t slv_data_bitlen:18;
-        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
-         *  In the slave mode it is the value of command.
-         */
-        uint32_t slv_last_command:8;
-        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
-         *  In the slave mode it is the value of address.
-         */
-        uint32_t slv_last_addr:6;
-    };
-    uint32_t val;
-} spi_slave1_reg_t;
-
-
-/** Group: Clock control registers */
-/** Type of clock register
- *  SPI clock control register
- */
-typedef union {
-    struct {
-        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
-         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
-         *  0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_l:6;
-        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
-         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-         *  must be 0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_h:6;
-        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
-         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
-         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-         */
-        uint32_t clkcnt_n:6;
-        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
-         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
-         */
-        uint32_t clkdiv_pre:4;
-        uint32_t reserved_22:9;
-        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
-         *  clock. Can be configured in CONF state.
-         */
-        uint32_t clk_equ_sysclk:1;
-    };
-    uint32_t val;
-} spi_clock_reg_t;
-
-/** Type of clk_gate register
- *  SPI module clock and register clock control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable clk gate
-         */
-        uint32_t clk_en:1;
-        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to power on the SPI module clock.
-         */
-        uint32_t mst_clk_active:1;
-        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
-         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
-         *  0: XTAL CLK.
-         */
-        uint32_t mst_clk_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} spi_clk_gate_reg_t;
-
-
-/** Group: Timing registers */
-/** Type of din_mode register
- *  SPI input delay mode configuration
- */
-typedef union {
-    struct {
-        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din0_mode:2;
-        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din1_mode:2;
-        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din2_mode:2;
-        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din3_mode:2;
-        /** din4_mode : HRO; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din4_mode:2;
-        /** din5_mode : HRO; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the
-         *  (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
-         *  3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  falling edge cycle. Can be configured in CONF state.
-         */
-        uint32_t din5_mode:2;
-        /** din6_mode : HRO; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the
-         *  (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
-         *  3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  falling edge cycle. Can be configured in CONF state.
-         */
-        uint32_t din6_mode:2;
-        /** din7_mode : HRO; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the
-         *  (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
-         *  3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
-         *  falling edge cycle. Can be configured in CONF state.
-         */
-        uint32_t din7_mode:2;
-        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
-         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
-         *  state.
-         */
-        uint32_t timing_hclk_active:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} spi_din_mode_reg_t;
-
-/** Type of din_num register
- *  SPI input delay number configuration
- */
-typedef union {
-    struct {
-        /** din0_num : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din0_num:2;
-        /** din1_num : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din1_num:2;
-        /** din2_num : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din2_num:2;
-        /** din3_num : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din3_num:2;
-        /** din4_num : HRO; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din4_num:2;
-        /** din5_num : HRO; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din5_num:2;
-        /** din6_num : HRO; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din6_num:2;
-        /** din7_num : HRO; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din7_num:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} spi_din_num_reg_t;
-
-/** Type of dout_mode register
- *  SPI output delay mode configuration
- */
-typedef union {
-    struct {
-        /** dout0_mode : R/W; bitpos: [0]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout0_mode:1;
-        /** dout1_mode : R/W; bitpos: [1]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout1_mode:1;
-        /** dout2_mode : R/W; bitpos: [2]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout2_mode:1;
-        /** dout3_mode : R/W; bitpos: [3]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout3_mode:1;
-        /** dout4_mode : HRO; bitpos: [4]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout4_mode:1;
-        /** dout5_mode : HRO; bitpos: [5]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout5_mode:1;
-        /** dout6_mode : HRO; bitpos: [6]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout6_mode:1;
-        /** dout7_mode : HRO; bitpos: [7]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout7_mode:1;
-        /** d_dqs_mode : HRO; bitpos: [8]; default: 0;
-         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
-         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t d_dqs_mode:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} spi_dout_mode_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of dma_int_ena register
- *  SPI interrupt enable register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_ena:1;
-        /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_ena:1;
-        /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_ena:1;
-        /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_ena:1;
-        /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_ena:1;
-        /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The enable bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_ena:1;
-        /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_ena:1;
-        /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_ena:1;
-        /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_ena:1;
-        /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_ena:1;
-        /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_ena:1;
-        /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_ena:1;
-        /** trans_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The enable bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_ena:1;
-        /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_ena:1;
-        /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_ena:1;
-        /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_ena:1;
-        /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0;
-         *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_ena:1;
-        /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0;
-         *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_ena:1;
-        /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0;
-         *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_ena:1;
-        /** app2_int_ena : R/W; bitpos: [19]; default: 0;
-         *  The enable bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_ena:1;
-        /** app1_int_ena : R/W; bitpos: [20]; default: 0;
-         *  The enable bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_ena:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_ena_reg_t;
-
-/** Type of dma_int_clr register
- *  SPI interrupt clear register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_clr:1;
-        /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_clr:1;
-        /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_clr:1;
-        /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_clr:1;
-        /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_clr:1;
-        /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0;
-         *  The clear bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_clr:1;
-        /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0;
-         *  The clear bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_clr:1;
-        /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0;
-         *  The clear bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_clr:1;
-        /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0;
-         *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_clr:1;
-        /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0;
-         *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_clr:1;
-        /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0;
-         *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_clr:1;
-        /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0;
-         *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_clr:1;
-        /** trans_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  The clear bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_clr:1;
-        /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_clr:1;
-        /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0;
-         *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_clr:1;
-        /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
-         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_clr:1;
-        /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0;
-         *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_clr:1;
-        /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0;
-         *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_clr:1;
-        /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0;
-         *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_clr:1;
-        /** app2_int_clr : WT; bitpos: [19]; default: 0;
-         *  The clear bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_clr:1;
-        /** app1_int_clr : WT; bitpos: [20]; default: 0;
-         *  The clear bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_clr:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_clr_reg_t;
-
-/** Type of dma_int_raw register
- *  SPI interrupt raw register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
-         *  receive data.  0: Others.
-         */
-        uint32_t dma_infifo_full_err_int_raw:1;
-        /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
-         *  master mode and send out all 0 in slave mode.  0: Others.
-         */
-        uint32_t dma_outfifo_empty_err_int_raw:1;
-        /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_ex_qpi_int_raw:1;
-        /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_en_qpi_int_raw:1;
-        /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd7_int_raw:1;
-        /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd8_int_raw:1;
-        /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd9_int_raw:1;
-        /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmda_int_raw:1;
-        /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_dma_done_int_raw:1;
-        /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_dma_done_int_raw:1;
-        /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_buf_done_int_raw:1;
-        /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_buf_done_int_raw:1;
-        /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
-         *  ended. 0: others.
-         */
-        uint32_t trans_done_int_raw:1;
-        /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
-         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
-         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
-         *  is not ended or not occurred.
-         */
-        uint32_t dma_seg_trans_done_int_raw:1;
-        /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
-         *  is error in the DMA seg-conf-trans. 0: others.
-         */
-        uint32_t seg_magic_err_int_raw:1;
-        /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
-         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
-         *  bigger than 63. 0: Others.
-         */
-        uint32_t slv_buf_addr_err_int_raw:1;
-        /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
-         *  current SPI slave HD mode transmission is not supported. 0: Others.
-         */
-        uint32_t slv_cmd_err_int_raw:1;
-        /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
-         *  write-full error when SPI inputs data in master mode. 0: Others.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_raw:1;
-        /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_raw:1;
-        /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app2_int_raw:1;
-        /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app1_int_raw:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_raw_reg_t;
-
-/** Type of dma_int_st register
- *  SPI interrupt status register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_st:1;
-        /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_st:1;
-        /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_st:1;
-        /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_st:1;
-        /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_st:1;
-        /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0;
-         *  The status bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_st:1;
-        /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0;
-         *  The status bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_st:1;
-        /** slv_cmda_int_st : RO; bitpos: [7]; default: 0;
-         *  The status bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_st:1;
-        /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0;
-         *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_st:1;
-        /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0;
-         *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_st:1;
-        /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0;
-         *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_st:1;
-        /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0;
-         *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_st:1;
-        /** trans_done_int_st : RO; bitpos: [12]; default: 0;
-         *  The status bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_st:1;
-        /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0;
-         *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_st:1;
-        /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0;
-         *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_st:1;
-        /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
-         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_st:1;
-        /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0;
-         *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_st:1;
-        /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0;
-         *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_st:1;
-        /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0;
-         *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_st:1;
-        /** app2_int_st : RO; bitpos: [19]; default: 0;
-         *  The status bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_st:1;
-        /** app1_int_st : RO; bitpos: [20]; default: 0;
-         *  The status bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_st:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_st_reg_t;
-
-/** Type of dma_int_set register
- *  SPI interrupt software set register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
-         *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-         */
-        uint32_t dma_infifo_full_err_int_set:1;
-        /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
-         *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-         */
-        uint32_t dma_outfifo_empty_err_int_set:1;
-        /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
-         *  The software set bit for SPI slave Ex_QPI interrupt.
-         */
-        uint32_t slv_ex_qpi_int_set:1;
-        /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
-         *  The software set bit for SPI slave En_QPI interrupt.
-         */
-        uint32_t slv_en_qpi_int_set:1;
-        /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
-         *  The software set bit for SPI slave CMD7 interrupt.
-         */
-        uint32_t slv_cmd7_int_set:1;
-        /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
-         *  The software set bit for SPI slave CMD8 interrupt.
-         */
-        uint32_t slv_cmd8_int_set:1;
-        /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
-         *  The software set bit for SPI slave CMD9 interrupt.
-         */
-        uint32_t slv_cmd9_int_set:1;
-        /** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
-         *  The software set bit for SPI slave CMDA interrupt.
-         */
-        uint32_t slv_cmda_int_set:1;
-        /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
-         *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_dma_done_int_set:1;
-        /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
-         *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_dma_done_int_set:1;
-        /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
-         *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_rd_buf_done_int_set:1;
-        /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
-         *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-         */
-        uint32_t slv_wr_buf_done_int_set:1;
-        /** trans_done_int_set : WT; bitpos: [12]; default: 0;
-         *  The software set bit for SPI_TRANS_DONE_INT interrupt.
-         */
-        uint32_t trans_done_int_set:1;
-        /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
-         *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-         */
-        uint32_t dma_seg_trans_done_int_set:1;
-        /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
-         *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-         */
-        uint32_t seg_magic_err_int_set:1;
-        /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
-         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-         */
-        uint32_t slv_buf_addr_err_int_set:1;
-        /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
-         *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
-         */
-        uint32_t slv_cmd_err_int_set:1;
-        /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
-         *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int_set:1;
-        /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
-         *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int_set:1;
-        /** app2_int_set : WT; bitpos: [19]; default: 0;
-         *  The software set bit for SPI_APP2_INT interrupt.
-         */
-        uint32_t app2_int_set:1;
-        /** app1_int_set : WT; bitpos: [20]; default: 0;
-         *  The software set bit for SPI_APP1_INT interrupt.
-         */
-        uint32_t app1_int_set:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_set_reg_t;
-
-
-/** Group: CPU-controlled data buffer */
-/** Type of w0 register
- *  SPI CPU-controlled buffer0
- */
-typedef union {
-    struct {
-        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf0:32;
-    };
-    uint32_t val;
-} spi_wn_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35656448;
-         *  SPI register version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} spi_date_reg_t;
-
-
-typedef struct {
-    volatile spi_cmd_reg_t cmd;
-    volatile spi_addr_reg_t addr;
-    volatile spi_ctrl_reg_t ctrl;
-    volatile spi_clock_reg_t clock;
-    volatile spi_user_reg_t user;
-    volatile spi_user1_reg_t user1;
-    volatile spi_user2_reg_t user2;
-    volatile spi_ms_dlen_reg_t ms_dlen;
-    volatile spi_misc_reg_t misc;
-    volatile spi_din_mode_reg_t din_mode;
-    volatile spi_din_num_reg_t din_num;
-    volatile spi_dout_mode_reg_t dout_mode;
-    volatile spi_dma_conf_reg_t dma_conf;
-    volatile spi_dma_int_ena_reg_t dma_int_ena;
-    volatile spi_dma_int_clr_reg_t dma_int_clr;
-    volatile spi_dma_int_raw_reg_t dma_int_raw;
-    volatile spi_dma_int_st_reg_t dma_int_st;
-    volatile spi_dma_int_set_reg_t dma_int_set;
-    uint32_t reserved_048[20];
-    volatile spi_wn_reg_t data_buf[16];
-    uint32_t reserved_0d8[2];
-    volatile spi_slave_reg_t slave;
-    volatile spi_slave1_reg_t slave1;
-    volatile spi_clk_gate_reg_t clk_gate;
-    uint32_t reserved_0ec;
-    volatile spi_date_reg_t date;
-} spi_dev_t;
-
-extern spi_dev_t GPSPI2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/system_reg.h b/components/soc/esp32h2/include/soc/system_reg.h
index 6a52d2da700..b2cb6089eec 100644
--- a/components/soc/esp32h2/include/soc/system_reg.h
+++ b/components/soc/esp32h2/include/soc/system_reg.h
@@ -5,7 +5,7 @@
  */
 
 #include "soc/hp_system_reg.h"
-#include "intpri_reg.h"
+#include "soc/intpri_reg.h"
 
 // ESP32H2-TODO : TODO: IDF-5720
 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
diff --git a/components/soc/esp32h2/include/soc/trace_reg.h b/components/soc/esp32h2/include/soc/trace_reg.h
deleted file mode 100644
index a5c3eda9dc7..00000000000
--- a/components/soc/esp32h2/include/soc/trace_reg.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** TRACE_MEM_START_ADDR_REG register
- *  mem start addr
- */
-#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
-/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  The start address of trace memory
- */
-#define TRACE_MEM_STAET_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_STAET_ADDR_M  (TRACE_MEM_STAET_ADDR_V << TRACE_MEM_STAET_ADDR_S)
-#define TRACE_MEM_STAET_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_STAET_ADDR_S  0
-
-/** TRACE_MEM_END_ADDR_REG register
- *  mem end addr
- */
-#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
-/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
- *  The end address of trace memory
- */
-#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
-#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_END_ADDR_S  0
-
-/** TRACE_MEM_CURRENT_ADDR_REG register
- *  mem current addr
- */
-#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
-/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
- *  current_mem_addr,indicate that next writing addr
- */
-#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
-#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
-#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
-#define TRACE_MEM_CURRENT_ADDR_S  0
-
-/** TRACE_MEM_ADDR_UPDATE_REG register
- *  mem addr update
- */
-#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
-/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
- *  when set this reg, the current_mem_addr will update to start_addr
- */
-#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
-#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
-
-/** TRACE_FIFO_STATUS_REG register
- *  fifo status register
- */
-#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
-/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  1 indicate that fifo is empty
- */
-#define TRACE_FIFO_EMPTY    (BIT(0))
-#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
-#define TRACE_FIFO_EMPTY_V  0x00000001U
-#define TRACE_FIFO_EMPTY_S  0
-/** TRACE_WORK_STATUS : RO; bitpos: [1]; default: 0;
- *  mem_full interrupt status
- */
-#define TRACE_WORK_STATUS    (BIT(1))
-#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
-#define TRACE_WORK_STATUS_V  0x00000001U
-#define TRACE_WORK_STATUS_S  1
-
-/** TRACE_INTR_ENA_REG register
- *  interrupt enable register
- */
-#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
-/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
- *  Set 1 enable fifo_overflow interrupt
- */
-#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
-/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
- *  Set 1 enable mem_full interrupt
- */
-#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
-#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
-#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_ENA_S  1
-
-/** TRACE_INTR_RAW_REG register
- *  interrupt status register
- */
-#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
-/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
- *  fifo_overflow interrupt status
- */
-#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
-/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
- *  mem_full interrupt status
- */
-#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
-#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
-#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_RAW_S  1
-
-/** TRACE_INTR_CLR_REG register
- *  interrupt clear register
- */
-#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
-/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
- *  Set 1 clr fifo overflow interrupt
- */
-#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
-#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
-/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
- *  Set 1 clr mem full interrupt
- */
-#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
-#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
-#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
-#define TRACE_MEM_FULL_INTR_CLR_S  1
-
-/** TRACE_TRIGGER_REG register
- *  trigger register
- */
-#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
-/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
- *  [0] set 1 start trace.
- */
-#define TRACE_TRIGGER_ON    (BIT(0))
-#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
-#define TRACE_TRIGGER_ON_V  0x00000001U
-#define TRACE_TRIGGER_ON_S  0
-/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
- *  set 1 stop trace.
- */
-#define TRACE_TRIGGER_OFF    (BIT(1))
-#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
-#define TRACE_TRIGGER_OFF_V  0x00000001U
-#define TRACE_TRIGGER_OFF_S  1
-/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
- *  if this reg is 1, trace will loop wrtie trace_mem.  If is 0, when mem_current_addr
- *  at mem_end_addr, it will stop at the mem_end_addr
- */
-#define TRACE_MEM_LOOP    (BIT(2))
-#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
-#define TRACE_MEM_LOOP_V  0x00000001U
-#define TRACE_MEM_LOOP_S  2
-/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
- *  enable encoder auto-restart, when lost package, the encoder will end, if enable
- *  auto-restart, when fifo empty, encoder will restart and send a sync package.
- */
-#define TRACE_RESTART_ENA    (BIT(3))
-#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
-#define TRACE_RESTART_ENA_V  0x00000001U
-#define TRACE_RESTART_ENA_S  3
-
-/** TRACE_RESYNC_PROLONGED_REG register
- *  resync configuration register
- */
-#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24)
-/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
- *  count number, when count to this value, send a sync package
- */
-#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
-#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
-#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
-#define TRACE_RESYNC_PROLONGED_S  0
-/** TRACE_RESYNC_MODE : R/W; bitpos: [24]; default: 0;
- *  resyc mode sel: 0: default, cycle count   1: package num count
- */
-#define TRACE_RESYNC_MODE    (BIT(24))
-#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
-#define TRACE_RESYNC_MODE_V  0x00000001U
-#define TRACE_RESYNC_MODE_S  24
-
-/** TRACE_CLOCK_GATE_REG register
- *  Clock gate control register
- */
-#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x28)
-/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable clock gate when access all registers in this module.
- */
-#define TRACE_CLK_EN    (BIT(0))
-#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
-#define TRACE_CLK_EN_V  0x00000001U
-#define TRACE_CLK_EN_S  0
-
-/** TRACE_DATE_REG register
- *  Version control register
- */
-#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
-/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35663920;
- *  version control register. Note that this default value stored is the latest date
- *  when the hardware logic was updated.
- */
-#define TRACE_DATE    0x0FFFFFFFU
-#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
-#define TRACE_DATE_V  0x0FFFFFFFU
-#define TRACE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/trace_struct.h b/components/soc/esp32h2/include/soc/trace_struct.h
deleted file mode 100644
index 41677de4288..00000000000
--- a/components/soc/esp32h2/include/soc/trace_struct.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Trace memory configuration registers */
-/** Type of mem_start_addr register
- *  mem start addr
- */
-typedef union {
-    struct {
-        /** mem_staet_addr : R/W; bitpos: [31:0]; default: 0;
-         *  The start address of trace memory
-         */
-        uint32_t mem_staet_addr:32;
-    };
-    uint32_t val;
-} trace_mem_start_addr_reg_t;
-
-/** Type of mem_end_addr register
- *  mem end addr
- */
-typedef union {
-    struct {
-        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
-         *  The end address of trace memory
-         */
-        uint32_t mem_end_addr:32;
-    };
-    uint32_t val;
-} trace_mem_end_addr_reg_t;
-
-/** Type of mem_current_addr register
- *  mem current addr
- */
-typedef union {
-    struct {
-        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
-         *  current_mem_addr,indicate that next writing addr
-         */
-        uint32_t mem_current_addr:32;
-    };
-    uint32_t val;
-} trace_mem_current_addr_reg_t;
-
-/** Type of mem_addr_update register
- *  mem addr update
- */
-typedef union {
-    struct {
-        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
-         *  when set this reg, the current_mem_addr will update to start_addr
-         */
-        uint32_t mem_current_addr_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} trace_mem_addr_update_reg_t;
-
-
-/** Group: Trace fifo status register */
-/** Type of fifo_status register
- *  fifo status register
- */
-typedef union {
-    struct {
-        /** fifo_empty : RO; bitpos: [0]; default: 1;
-         *  1 indicate that fifo is empty
-         */
-        uint32_t fifo_empty:1;
-        /** work_status : RO; bitpos: [1]; default: 0;
-         *  mem_full interrupt status
-         */
-        uint32_t work_status:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_fifo_status_reg_t;
-
-
-/** Group: Trace interrupt configuration registers */
-/** Type of intr_ena register
- *  interrupt enable register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
-         *  Set 1 enable fifo_overflow interrupt
-         */
-        uint32_t fifo_overflow_intr_ena:1;
-        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
-         *  Set 1 enable mem_full interrupt
-         */
-        uint32_t mem_full_intr_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_ena_reg_t;
-
-/** Type of intr_raw register
- *  interrupt status register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
-         *  fifo_overflow interrupt status
-         */
-        uint32_t fifo_overflow_intr_raw:1;
-        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
-         *  mem_full interrupt status
-         */
-        uint32_t mem_full_intr_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_raw_reg_t;
-
-/** Type of intr_clr register
- *  interrupt clear register
- */
-typedef union {
-    struct {
-        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
-         *  Set 1 clr fifo overflow interrupt
-         */
-        uint32_t fifo_overflow_intr_clr:1;
-        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
-         *  Set 1 clr mem full interrupt
-         */
-        uint32_t mem_full_intr_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} trace_intr_clr_reg_t;
-
-
-/** Group: Trace configuration register */
-/** Type of trigger register
- *  trigger register
- */
-typedef union {
-    struct {
-        /** trigger_on : WT; bitpos: [0]; default: 0;
-         *  [0] set 1 start trace.
-         */
-        uint32_t trigger_on:1;
-        /** trigger_off : WT; bitpos: [1]; default: 0;
-         *  set 1 stop trace.
-         */
-        uint32_t trigger_off:1;
-        /** mem_loop : R/W; bitpos: [2]; default: 1;
-         *  if this reg is 1, trace will loop wrtie trace_mem.  If is 0, when mem_current_addr
-         *  at mem_end_addr, it will stop at the mem_end_addr
-         */
-        uint32_t mem_loop:1;
-        /** restart_ena : R/W; bitpos: [3]; default: 1;
-         *  enable encoder auto-restart, when lost package, the encoder will end, if enable
-         *  auto-restart, when fifo empty, encoder will restart and send a sync package.
-         */
-        uint32_t restart_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} trace_trigger_reg_t;
-
-/** Type of resync_prolonged register
- *  resync configuration register
- */
-typedef union {
-    struct {
-        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
-         *  count number, when count to this value, send a sync package
-         */
-        uint32_t resync_prolonged:24;
-        /** resync_mode : R/W; bitpos: [24]; default: 0;
-         *  resyc mode sel: 0: default, cycle count   1: package num count
-         */
-        uint32_t resync_mode:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} trace_resync_prolonged_reg_t;
-
-
-/** Group: Clock Gate Control and configuration register */
-/** Type of clock_gate register
- *  Clock gate control register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  The bit is used to enable clock gate when access all registers in this module.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} trace_clock_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35663920;
-         *  version control register. Note that this default value stored is the latest date
-         *  when the hardware logic was updated.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} trace_date_reg_t;
-
-
-typedef struct {
-    volatile trace_mem_start_addr_reg_t mem_start_addr;
-    volatile trace_mem_end_addr_reg_t mem_end_addr;
-    volatile trace_mem_current_addr_reg_t mem_current_addr;
-    volatile trace_mem_addr_update_reg_t mem_addr_update;
-    volatile trace_fifo_status_reg_t fifo_status;
-    volatile trace_intr_ena_reg_t intr_ena;
-    volatile trace_intr_raw_reg_t intr_raw;
-    volatile trace_intr_clr_reg_t intr_clr;
-    volatile trace_trigger_reg_t trigger;
-    volatile trace_resync_prolonged_reg_t resync_prolonged;
-    volatile trace_clock_gate_reg_t clock_gate;
-    uint32_t reserved_02c[244];
-    volatile trace_date_reg_t date;
-} trace_dev_t;
-
-extern trace_dev_t TRACE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/uart_reg.h b/components/soc/esp32h2/include/soc/uart_reg.h
deleted file mode 100644
index 5c8d8c01f9f..00000000000
--- a/components/soc/esp32h2/include/soc/uart_reg.h
+++ /dev/null
@@ -1,1546 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** UART_FIFO_REG(i) register
- *  FIFO data register
- */
-#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
-/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
- *  UART $n accesses FIFO via this register.
- */
-#define UART_RXFIFO_RD_BYTE    0x000000FFU
-#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
-#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
-#define UART_RXFIFO_RD_BYTE_S  0
-
-/** UART_INT_RAW_REG(i) register
- *  Raw interrupt status
- */
-#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
-/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  what rxfifo_full_thrhd specifies.
- */
-#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
-#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_RAW_S  0
-/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
- *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- *  less than what txfifo_empty_thrhd specifies .
- */
-#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error in
- *  the data.
- */
-#define UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
-#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_PARITY_ERR_INT_RAW_S  2
-/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  .
- */
-#define UART_FRM_ERR_INT_RAW    (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
-#define UART_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_FRM_ERR_INT_RAW_S  3
-/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  the FIFO can store.
- */
-#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
-#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  DSRn signal.
- */
-#define UART_DSR_CHG_INT_RAW    (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
-#define UART_DSR_CHG_INT_RAW_V  0x00000001U
-#define UART_DSR_CHG_INT_RAW_S  5
-/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  CTSn signal.
- */
-#define UART_CTS_CHG_INT_RAW    (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
-#define UART_CTS_CHG_INT_RAW_V  0x00000001U
-#define UART_CTS_CHG_INT_RAW_S  6
-/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
- *  bit.
- */
-#define UART_BRK_DET_INT_RAW    (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
-#define UART_BRK_DET_INT_RAW_V  0x00000001U
-#define UART_BRK_DET_INT_RAW_S  7
-/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  This interrupt raw bit turns to high level when receiver takes more time than
- *  rx_tout_thrhd to receive a byte.
- */
-#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XON_INT_RAW    (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
-#define UART_SW_XON_INT_RAW_V  0x00000001U
-#define UART_SW_XON_INT_RAW_S  9
-/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives Xoff char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XOFF_INT_RAW    (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
-#define UART_SW_XOFF_INT_RAW_V  0x00000001U
-#define UART_SW_XOFF_INT_RAW_S  10
-/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a glitch in the
- *  middle of a start bit.
- */
-#define UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
-#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
-#define UART_GLITCH_DET_INT_RAW_S  11
-/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter completes  sending
- *  NULL characters after all data in Tx-FIFO are sent.
- */
-#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
-#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has kept the shortest
- *  duration after sending the  last data.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has send out all data
- *  in FIFO.
- */
-#define UART_TX_DONE_INT_RAW    (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
-#define UART_TX_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_DONE_INT_RAW_S  14
-/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  This interrupt raw bit turns to high level when detects a clash between transmitter
- *  and receiver in rs485 mode.
- */
-#define UART_RS485_CLASH_INT_RAW    (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
-#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
-#define UART_RS485_CLASH_INT_RAW_S  17
-/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the configured
- *  at_cmd char.
- */
-#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  This interrupt raw bit turns to high level when input rxd edge changes more times
- *  than what reg_active_threshold specifies in light sleeping mode.
- */
-#define UART_WAKEUP_INT_RAW    (BIT(19))
-#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
-#define UART_WAKEUP_INT_RAW_V  0x00000001U
-#define UART_WAKEUP_INT_RAW_S  19
-
-/** UART_INT_ST_REG(i) register
- *  Masked interrupt status
- */
-#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
-/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
- *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
- */
-#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
-#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ST_S  0
-/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
- *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
- *  to 1.
- */
-#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
- *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
- */
-#define UART_PARITY_ERR_INT_ST    (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
-#define UART_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_PARITY_ERR_INT_ST_S  2
-/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
- *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
- */
-#define UART_FRM_ERR_INT_ST    (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
-#define UART_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_FRM_ERR_INT_ST_S  3
-/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
- */
-#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
-#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
- */
-#define UART_DSR_CHG_INT_ST    (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
-#define UART_DSR_CHG_INT_ST_V  0x00000001U
-#define UART_DSR_CHG_INT_ST_S  5
-/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
- *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
- */
-#define UART_CTS_CHG_INT_ST    (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
-#define UART_CTS_CHG_INT_ST_V  0x00000001U
-#define UART_CTS_CHG_INT_ST_S  6
-/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
- *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
- */
-#define UART_BRK_DET_INT_ST    (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
-#define UART_BRK_DET_INT_ST_V  0x00000001U
-#define UART_BRK_DET_INT_ST_S  7
-/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
- */
-#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
-#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
- *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
- */
-#define UART_SW_XON_INT_ST    (BIT(9))
-#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
-#define UART_SW_XON_INT_ST_V  0x00000001U
-#define UART_SW_XON_INT_ST_S  9
-/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
- *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
- */
-#define UART_SW_XOFF_INT_ST    (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
-#define UART_SW_XOFF_INT_ST_V  0x00000001U
-#define UART_SW_XOFF_INT_ST_S  10
-/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
- *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
- */
-#define UART_GLITCH_DET_INT_ST    (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
-#define UART_GLITCH_DET_INT_ST_V  0x00000001U
-#define UART_GLITCH_DET_INT_ST_S  11
-/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
- */
-#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
-#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- *  is set to 1.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
- */
-#define UART_TX_DONE_INT_ST    (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
-#define UART_TX_DONE_INT_ST_V  0x00000001U
-#define UART_TX_DONE_INT_ST_S  14
-/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
- *  set to 1.
- */
-#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
- *  to 1.
- */
-#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
-#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
- *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
- */
-#define UART_RS485_CLASH_INT_ST    (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
-#define UART_RS485_CLASH_INT_ST_V  0x00000001U
-#define UART_RS485_CLASH_INT_ST_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
- *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
- *  to 1.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
- *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
- */
-#define UART_WAKEUP_INT_ST    (BIT(19))
-#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
-#define UART_WAKEUP_INT_ST_V  0x00000001U
-#define UART_WAKEUP_INT_ST_S  19
-
-/** UART_INT_ENA_REG(i) register
- *  Interrupt enable bits
- */
-#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
-/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  This is the enable bit for rxfifo_full_int_st register.
- */
-#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
-#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ENA_S  0
-/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  This is the enable bit for txfifo_empty_int_st register.
- */
-#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  This is the enable bit for parity_err_int_st register.
- */
-#define UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
-#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_PARITY_ERR_INT_ENA_S  2
-/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  This is the enable bit for frm_err_int_st register.
- */
-#define UART_FRM_ERR_INT_ENA    (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
-#define UART_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_FRM_ERR_INT_ENA_S  3
-/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  This is the enable bit for rxfifo_ovf_int_st register.
- */
-#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
-#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for dsr_chg_int_st register.
- */
-#define UART_DSR_CHG_INT_ENA    (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
-#define UART_DSR_CHG_INT_ENA_V  0x00000001U
-#define UART_DSR_CHG_INT_ENA_S  5
-/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  This is the enable bit for cts_chg_int_st register.
- */
-#define UART_CTS_CHG_INT_ENA    (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
-#define UART_CTS_CHG_INT_ENA_V  0x00000001U
-#define UART_CTS_CHG_INT_ENA_S  6
-/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  This is the enable bit for brk_det_int_st register.
- */
-#define UART_BRK_DET_INT_ENA    (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
-#define UART_BRK_DET_INT_ENA_V  0x00000001U
-#define UART_BRK_DET_INT_ENA_S  7
-/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  This is the enable bit for rxfifo_tout_int_st register.
- */
-#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  This is the enable bit for sw_xon_int_st register.
- */
-#define UART_SW_XON_INT_ENA    (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
-#define UART_SW_XON_INT_ENA_V  0x00000001U
-#define UART_SW_XON_INT_ENA_S  9
-/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  This is the enable bit for sw_xoff_int_st register.
- */
-#define UART_SW_XOFF_INT_ENA    (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
-#define UART_SW_XOFF_INT_ENA_V  0x00000001U
-#define UART_SW_XOFF_INT_ENA_S  10
-/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  This is the enable bit for glitch_det_int_st register.
- */
-#define UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
-#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
-#define UART_GLITCH_DET_INT_ENA_S  11
-/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for tx_brk_done_int_st register.
- */
-#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
-#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit for tx_brk_idle_done_int_st register.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for tx_done_int_st register.
- */
-#define UART_TX_DONE_INT_ENA    (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
-#define UART_TX_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_DONE_INT_ENA_S  14
-/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  This is the enable bit for rs485_clash_int_st register.
- */
-#define UART_RS485_CLASH_INT_ENA    (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
-#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
-#define UART_RS485_CLASH_INT_ENA_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  This is the enable bit for at_cmd_char_det_int_st register.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for uart_wakeup_int_st register.
- */
-#define UART_WAKEUP_INT_ENA    (BIT(19))
-#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
-#define UART_WAKEUP_INT_ENA_V  0x00000001U
-#define UART_WAKEUP_INT_ENA_S  19
-
-/** UART_INT_CLR_REG(i) register
- *  Interrupt clear bits
- */
-#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
-/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the rxfifo_full_int_raw interrupt.
- */
-#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
-#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_CLR_S  0
-/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear txfifo_empty_int_raw interrupt.
- */
-#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear parity_err_int_raw interrupt.
- */
-#define UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
-#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_PARITY_ERR_INT_CLR_S  2
-/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear frm_err_int_raw interrupt.
- */
-#define UART_FRM_ERR_INT_CLR    (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
-#define UART_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_FRM_ERR_INT_CLR_S  3
-/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
- */
-#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
-#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the dsr_chg_int_raw interrupt.
- */
-#define UART_DSR_CHG_INT_CLR    (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
-#define UART_DSR_CHG_INT_CLR_V  0x00000001U
-#define UART_DSR_CHG_INT_CLR_S  5
-/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the cts_chg_int_raw interrupt.
- */
-#define UART_CTS_CHG_INT_CLR    (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
-#define UART_CTS_CHG_INT_CLR_V  0x00000001U
-#define UART_CTS_CHG_INT_CLR_S  6
-/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the brk_det_int_raw interrupt.
- */
-#define UART_BRK_DET_INT_CLR    (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
-#define UART_BRK_DET_INT_CLR_V  0x00000001U
-#define UART_BRK_DET_INT_CLR_S  7
-/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
- */
-#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the sw_xon_int_raw interrupt.
- */
-#define UART_SW_XON_INT_CLR    (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
-#define UART_SW_XON_INT_CLR_V  0x00000001U
-#define UART_SW_XON_INT_CLR_S  9
-/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the sw_xoff_int_raw interrupt.
- */
-#define UART_SW_XOFF_INT_CLR    (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
-#define UART_SW_XOFF_INT_CLR_V  0x00000001U
-#define UART_SW_XOFF_INT_CLR_S  10
-/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the glitch_det_int_raw interrupt.
- */
-#define UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
-#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
-#define UART_GLITCH_DET_INT_CLR_S  11
-/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the tx_brk_done_int_raw interrupt..
- */
-#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
-#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the tx_done_int_raw interrupt.
- */
-#define UART_TX_DONE_INT_CLR    (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
-#define UART_TX_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_DONE_INT_CLR_S  14
-/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
- */
-#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
- */
-#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit to clear the rs485_clash_int_raw interrupt.
- */
-#define UART_RS485_CLASH_INT_CLR    (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
-#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
-#define UART_RS485_CLASH_INT_CLR_S  17
-/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
- */
-#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the uart_wakeup_int_raw interrupt.
- */
-#define UART_WAKEUP_INT_CLR    (BIT(19))
-#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
-#define UART_WAKEUP_INT_CLR_V  0x00000001U
-#define UART_WAKEUP_INT_CLR_S  19
-
-/** UART_CLKDIV_SYNC_REG(i) register
- *  Clock divider configuration
- */
-#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
-/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
- *  The integral part of the frequency divider factor.
- */
-#define UART_CLKDIV    0x00000FFFU
-#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
-#define UART_CLKDIV_V  0x00000FFFU
-#define UART_CLKDIV_S  0
-/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
- *  The decimal part of the frequency divider factor.
- */
-#define UART_CLKDIV_FRAG    0x0000000FU
-#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
-#define UART_CLKDIV_FRAG_V  0x0000000FU
-#define UART_CLKDIV_FRAG_S  20
-
-/** UART_RX_FILT_REG(i) register
- *  Rx Filter configuration
- */
-#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
-/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
- *  when input pulse width is lower than this value the pulse is ignored.
- */
-#define UART_GLITCH_FILT    0x000000FFU
-#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
-#define UART_GLITCH_FILT_V  0x000000FFU
-#define UART_GLITCH_FILT_S  0
-/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable Rx signal filter.
- */
-#define UART_GLITCH_FILT_EN    (BIT(8))
-#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
-#define UART_GLITCH_FILT_EN_V  0x00000001U
-#define UART_GLITCH_FILT_EN_S  8
-
-/** UART_STATUS_REG(i) register
- *  UART status register
- */
-#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
-/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
- *  Stores the byte number of valid data in Rx-FIFO.
- */
-#define UART_RXFIFO_CNT    0x000000FFU
-#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
-#define UART_RXFIFO_CNT_V  0x000000FFU
-#define UART_RXFIFO_CNT_S  0
-/** UART_DSRN : RO; bitpos: [13]; default: 0;
- *  The register represent the level value of the internal uart dsr signal.
- */
-#define UART_DSRN    (BIT(13))
-#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
-#define UART_DSRN_V  0x00000001U
-#define UART_DSRN_S  13
-/** UART_CTSN : RO; bitpos: [14]; default: 1;
- *  This register represent the level value of the internal uart cts signal.
- */
-#define UART_CTSN    (BIT(14))
-#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
-#define UART_CTSN_V  0x00000001U
-#define UART_CTSN_S  14
-/** UART_RXD : RO; bitpos: [15]; default: 1;
- *  This register represent the  level value of the internal uart rxd signal.
- */
-#define UART_RXD    (BIT(15))
-#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
-#define UART_RXD_V  0x00000001U
-#define UART_RXD_S  15
-/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
- *  Stores the byte number of data in Tx-FIFO.
- */
-#define UART_TXFIFO_CNT    0x000000FFU
-#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
-#define UART_TXFIFO_CNT_V  0x000000FFU
-#define UART_TXFIFO_CNT_S  16
-/** UART_DTRN : RO; bitpos: [29]; default: 1;
- *  This bit represents the level of the internal uart dtr signal.
- */
-#define UART_DTRN    (BIT(29))
-#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
-#define UART_DTRN_V  0x00000001U
-#define UART_DTRN_S  29
-/** UART_RTSN : RO; bitpos: [30]; default: 1;
- *  This bit represents the level of the internal uart rts signal.
- */
-#define UART_RTSN    (BIT(30))
-#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
-#define UART_RTSN_V  0x00000001U
-#define UART_RTSN_S  30
-/** UART_TXD : RO; bitpos: [31]; default: 1;
- *  This bit represents the  level of the internal uart txd signal.
- */
-#define UART_TXD    (BIT(31))
-#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
-#define UART_TXD_V  0x00000001U
-#define UART_TXD_S  31
-
-/** UART_CONF0_SYNC_REG(i) register
- *  a
- */
-#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
-/** UART_PARITY : R/W; bitpos: [0]; default: 0;
- *  This register is used to configure the parity check mode.
- */
-#define UART_PARITY    (BIT(0))
-#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
-#define UART_PARITY_V  0x00000001U
-#define UART_PARITY_S  0
-/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable uart parity check.
- */
-#define UART_PARITY_EN    (BIT(1))
-#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
-#define UART_PARITY_EN_V  0x00000001U
-#define UART_PARITY_EN_S  1
-/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
- *  This register is used to set the length of data.
- */
-#define UART_BIT_NUM    0x00000003U
-#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
-#define UART_BIT_NUM_V  0x00000003U
-#define UART_BIT_NUM_S  2
-/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
- *  This register is used to set the length of  stop bit.
- */
-#define UART_STOP_BIT_NUM    0x00000003U
-#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
-#define UART_STOP_BIT_NUM_V  0x00000003U
-#define UART_STOP_BIT_NUM_S  4
-/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
- *  is done.
- */
-#define UART_TXD_BRK    (BIT(6))
-#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
-#define UART_TXD_BRK_V  0x00000001U
-#define UART_TXD_BRK_S  6
-/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
- *  Set this bit to enable IrDA loopback mode.
- */
-#define UART_IRDA_DPLX    (BIT(7))
-#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
-#define UART_IRDA_DPLX_V  0x00000001U
-#define UART_IRDA_DPLX_S  7
-/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
- *  This is the start enable bit for IrDA transmitter.
- */
-#define UART_IRDA_TX_EN    (BIT(8))
-#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
-#define UART_IRDA_TX_EN_V  0x00000001U
-#define UART_IRDA_TX_EN_S  8
-/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
- *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
- *  transmitter's 11th bit to 0.
- */
-#define UART_IRDA_WCTL    (BIT(9))
-#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
-#define UART_IRDA_WCTL_V  0x00000001U
-#define UART_IRDA_WCTL_S  9
-/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
- *  Set this bit to invert the level of  IrDA transmitter.
- */
-#define UART_IRDA_TX_INV    (BIT(10))
-#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
-#define UART_IRDA_TX_INV_V  0x00000001U
-#define UART_IRDA_TX_INV_S  10
-/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
- *  Set this bit to invert the level of IrDA receiver.
- */
-#define UART_IRDA_RX_INV    (BIT(11))
-#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
-#define UART_IRDA_RX_INV_V  0x00000001U
-#define UART_IRDA_RX_INV_S  11
-/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable uart loopback test mode.
- */
-#define UART_LOOPBACK    (BIT(12))
-#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
-#define UART_LOOPBACK_V  0x00000001U
-#define UART_LOOPBACK_S  12
-/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
- *  Set this bit to enable flow control function for transmitter.
- */
-#define UART_TX_FLOW_EN    (BIT(13))
-#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
-#define UART_TX_FLOW_EN_V  0x00000001U
-#define UART_TX_FLOW_EN_S  13
-/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
- *  Set this bit to enable IrDA protocol.
- */
-#define UART_IRDA_EN    (BIT(14))
-#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
-#define UART_IRDA_EN_V  0x00000001U
-#define UART_IRDA_EN_S  14
-/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
- *  Set this bit to inverse the level value of uart rxd signal.
- */
-#define UART_RXD_INV    (BIT(15))
-#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
-#define UART_RXD_INV_V  0x00000001U
-#define UART_RXD_INV_S  15
-/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart txd signal.
- */
-#define UART_TXD_INV    (BIT(16))
-#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
-#define UART_TXD_INV_V  0x00000001U
-#define UART_TXD_INV_S  16
-/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
- *  Disable UART Rx data overflow detect.
- */
-#define UART_DIS_RX_DAT_OVF    (BIT(17))
-#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
-#define UART_DIS_RX_DAT_OVF_V  0x00000001U
-#define UART_DIS_RX_DAT_OVF_S  17
-/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
- *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
- *  stores the data even if the  received data is wrong.
- */
-#define UART_ERR_WR_MASK    (BIT(18))
-#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
-#define UART_ERR_WR_MASK_V  0x00000001U
-#define UART_ERR_WR_MASK_S  18
-/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for detecting baudrate.
- */
-#define UART_AUTOBAUD_EN    (BIT(19))
-#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
-#define UART_AUTOBAUD_EN_V  0x00000001U
-#define UART_AUTOBAUD_EN_S  19
-/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
- *  UART memory clock gate enable signal.
- */
-#define UART_MEM_CLK_EN    (BIT(20))
-#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
-#define UART_MEM_CLK_EN_V  0x00000001U
-#define UART_MEM_CLK_EN_S  20
-/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
- *  This register is used to configure the software rts signal which is used in
- *  software flow control.
- */
-#define UART_SW_RTS    (BIT(21))
-#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
-#define UART_SW_RTS_V  0x00000001U
-#define UART_SW_RTS_S  21
-/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
- *  Set this bit to reset the uart receive-FIFO.
- */
-#define UART_RXFIFO_RST    (BIT(22))
-#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
-#define UART_RXFIFO_RST_V  0x00000001U
-#define UART_RXFIFO_RST_S  22
-/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
- *  Set this bit to reset the uart transmit-FIFO.
- */
-#define UART_TXFIFO_RST    (BIT(23))
-#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
-#define UART_TXFIFO_RST_V  0x00000001U
-#define UART_TXFIFO_RST_S  23
-
-/** UART_CONF1_REG(i) register
- *  Configuration register 1
- */
-#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
-/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
- *  It will produce rxfifo_full_int interrupt when receiver receives more data than
- *  this register value.
- */
-#define UART_RXFIFO_FULL_THRHD    0x000000FFU
-#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
-#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
-#define UART_RXFIFO_FULL_THRHD_S  0
-/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
- *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
- *  than this register value.
- */
-#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
-#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
-#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
-#define UART_TXFIFO_EMPTY_THRHD_S  8
-/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart cts signal.
- */
-#define UART_CTS_INV    (BIT(16))
-#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
-#define UART_CTS_INV_V  0x00000001U
-#define UART_CTS_INV_S  16
-/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
- *  Set this bit to inverse the level value of uart dsr signal.
- */
-#define UART_DSR_INV    (BIT(17))
-#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
-#define UART_DSR_INV_V  0x00000001U
-#define UART_DSR_INV_S  17
-/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
- *  Set this bit to inverse the level value of uart rts signal.
- */
-#define UART_RTS_INV    (BIT(18))
-#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
-#define UART_RTS_INV_V  0x00000001U
-#define UART_RTS_INV_S  18
-/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
- *  Set this bit to inverse the level value of uart dtr signal.
- */
-#define UART_DTR_INV    (BIT(19))
-#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
-#define UART_DTR_INV_V  0x00000001U
-#define UART_DTR_INV_S  19
-/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
- *  This register is used to configure the software dtr signal which is used in
- *  software flow control.
- */
-#define UART_SW_DTR    (BIT(20))
-#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
-#define UART_SW_DTR_V  0x00000001U
-#define UART_SW_DTR_S  20
-/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define UART_CLK_EN    (BIT(21))
-#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
-#define UART_CLK_EN_V  0x00000001U
-#define UART_CLK_EN_S  21
-
-/** UART_HWFC_CONF_SYNC_REG(i) register
- *  Hardware flow-control configuration
- */
-#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
-/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
- *  This register is used to configure the maximum amount of data that can be received
- *  when hardware flow control works.
- */
-#define UART_RX_FLOW_THRHD    0x000000FFU
-#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
-#define UART_RX_FLOW_THRHD_V  0x000000FFU
-#define UART_RX_FLOW_THRHD_S  0
-/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
- *  This is the flow enable bit for UART receiver.
- */
-#define UART_RX_FLOW_EN    (BIT(8))
-#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
-#define UART_RX_FLOW_EN_V  0x00000001U
-#define UART_RX_FLOW_EN_S  8
-
-/** UART_SLEEP_CONF0_REG(i) register
- *  UART sleep configure register 0
- */
-#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
-/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified wake up char1 to wake up
- */
-#define UART_WK_CHAR1    0x000000FFU
-#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
-#define UART_WK_CHAR1_V  0x000000FFU
-#define UART_WK_CHAR1_S  0
-/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
- *  This register restores the specified wake up char2 to wake up
- */
-#define UART_WK_CHAR2    0x000000FFU
-#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
-#define UART_WK_CHAR2_V  0x000000FFU
-#define UART_WK_CHAR2_S  8
-/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
- *  This register restores the specified wake up char3 to wake up
- */
-#define UART_WK_CHAR3    0x000000FFU
-#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
-#define UART_WK_CHAR3_V  0x000000FFU
-#define UART_WK_CHAR3_S  16
-/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
- *  This register restores the specified wake up char4 to wake up
- */
-#define UART_WK_CHAR4    0x000000FFU
-#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
-#define UART_WK_CHAR4_V  0x000000FFU
-#define UART_WK_CHAR4_S  24
-
-/** UART_SLEEP_CONF1_REG(i) register
- *  UART sleep configure register 1
- */
-#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
-/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified char0 to wake up
- */
-#define UART_WK_CHAR0    0x000000FFU
-#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
-#define UART_WK_CHAR0_V  0x000000FFU
-#define UART_WK_CHAR0_S  0
-
-/** UART_SLEEP_CONF2_REG(i) register
- *  UART sleep configure register 2
- */
-#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
-/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
- *  The uart is activated from light sleeping mode when the input rxd edge changes more
- *  times than this register value.
- */
-#define UART_ACTIVE_THRESHOLD    0x000003FFU
-#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
-#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
-#define UART_ACTIVE_THRESHOLD_S  0
-/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
- *  In wake up mode 1 this field is used to set the received data number threshold to
- *  wake up chip.
- */
-#define UART_RX_WAKE_UP_THRHD    0x000000FFU
-#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
-#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
-#define UART_RX_WAKE_UP_THRHD_S  10
-/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
- *  This register is used to select number of wake up char.
- */
-#define UART_WK_CHAR_NUM    0x00000007U
-#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
-#define UART_WK_CHAR_NUM_V  0x00000007U
-#define UART_WK_CHAR_NUM_S  18
-/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
- *  This register is used to mask  wake up char.
- */
-#define UART_WK_CHAR_MASK    0x0000001FU
-#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
-#define UART_WK_CHAR_MASK_V  0x0000001FU
-#define UART_WK_CHAR_MASK_S  21
-/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
- *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
- *  received data number larger than
- */
-#define UART_WK_MODE_SEL    0x00000003U
-#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
-#define UART_WK_MODE_SEL_V  0x00000003U
-#define UART_WK_MODE_SEL_S  26
-
-/** UART_SWFC_CONF0_SYNC_REG(i) register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
-/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
- *  This register stores the Xon flow control char.
- */
-#define UART_XON_CHAR    0x000000FFU
-#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
-#define UART_XON_CHAR_V  0x000000FFU
-#define UART_XON_CHAR_S  0
-/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
- *  This register stores the Xoff flow control char.
- */
-#define UART_XOFF_CHAR    0x000000FFU
-#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
-#define UART_XOFF_CHAR_V  0x000000FFU
-#define UART_XOFF_CHAR_S  8
-/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
- *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
- *  this status, UART Tx can not transmit XOFF even the received data number is larger
- *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
- *  UART Tx is disabled.
- */
-#define UART_XON_XOFF_STILL_SEND    (BIT(16))
-#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
-#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
-#define UART_XON_XOFF_STILL_SEND_S  16
-/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
- *  Set this bit to enable software flow control. It is used with register sw_xon or
- *  sw_xoff.
- */
-#define UART_SW_FLOW_CON_EN    (BIT(17))
-#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
-#define UART_SW_FLOW_CON_EN_V  0x00000001U
-#define UART_SW_FLOW_CON_EN_S  17
-/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
- *  Set this bit to remove flow control char from the received data.
- */
-#define UART_XONOFF_DEL    (BIT(18))
-#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
-#define UART_XONOFF_DEL_V  0x00000001U
-#define UART_XONOFF_DEL_S  18
-/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
- *  Set this bit to enable the transmitter to go on sending data.
- */
-#define UART_FORCE_XON    (BIT(19))
-#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
-#define UART_FORCE_XON_V  0x00000001U
-#define UART_FORCE_XON_S  19
-/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
- *  Set this bit to stop the  transmitter from sending data.
- */
-#define UART_FORCE_XOFF    (BIT(20))
-#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
-#define UART_FORCE_XOFF_V  0x00000001U
-#define UART_FORCE_XOFF_S  20
-/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
- *  Set this bit to send Xon char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XON    (BIT(21))
-#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
-#define UART_SEND_XON_V  0x00000001U
-#define UART_SEND_XON_S  21
-/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
- *  Set this bit to send Xoff char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XOFF    (BIT(22))
-#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
-#define UART_SEND_XOFF_V  0x00000001U
-#define UART_SEND_XOFF_S  22
-
-/** UART_SWFC_CONF1_REG(i) register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
-/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
- *  When the data amount in Rx-FIFO is less than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xon char.
- */
-#define UART_XON_THRESHOLD    0x000000FFU
-#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
-#define UART_XON_THRESHOLD_V  0x000000FFU
-#define UART_XON_THRESHOLD_S  0
-/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
- *  When the data amount in Rx-FIFO is more than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
- */
-#define UART_XOFF_THRESHOLD    0x000000FFU
-#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
-#define UART_XOFF_THRESHOLD_V  0x000000FFU
-#define UART_XOFF_THRESHOLD_S  8
-
-/** UART_TXBRK_CONF_SYNC_REG(i) register
- *  Tx Break character configuration
- */
-#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
-/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
- *  This register is used to configure the number of 0 to be sent after the process of
- *  sending data is done. It is active when txd_brk is set to 1.
- */
-#define UART_TX_BRK_NUM    0x000000FFU
-#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
-#define UART_TX_BRK_NUM_V  0x000000FFU
-#define UART_TX_BRK_NUM_S  0
-
-/** UART_IDLE_CONF_SYNC_REG(i) register
- *  Frame-end idle configuration
- */
-#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
-/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
- *  It will produce frame end signal when receiver takes more time to receive one byte
- *  data than this register value.
- */
-#define UART_RX_IDLE_THRHD    0x000003FFU
-#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
-#define UART_RX_IDLE_THRHD_V  0x000003FFU
-#define UART_RX_IDLE_THRHD_S  0
-/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
- *  This register is used to configure the duration time between transfers.
- */
-#define UART_TX_IDLE_NUM    0x000003FFU
-#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
-#define UART_TX_IDLE_NUM_V  0x000003FFU
-#define UART_TX_IDLE_NUM_S  10
-
-/** UART_RS485_CONF_SYNC_REG(i) register
- *  RS485 mode configuration
- */
-#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
-/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to choose the rs485 mode.
- */
-#define UART_RS485_EN    (BIT(0))
-#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
-#define UART_RS485_EN_V  0x00000001U
-#define UART_RS485_EN_S  0
-/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL0_EN    (BIT(1))
-#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
-#define UART_DL0_EN_V  0x00000001U
-#define UART_DL0_EN_S  1
-/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL1_EN    (BIT(2))
-#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
-#define UART_DL1_EN_V  0x00000001U
-#define UART_DL1_EN_S  2
-/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable receiver could receive data when the transmitter is
- *  transmitting data in rs485 mode.
- */
-#define UART_RS485TX_RX_EN    (BIT(3))
-#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
-#define UART_RS485TX_RX_EN_V  0x00000001U
-#define UART_RS485TX_RX_EN_S  3
-/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
- *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
- */
-#define UART_RS485RXBY_TX_EN    (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
-#define UART_RS485RXBY_TX_EN_V  0x00000001U
-#define UART_RS485RXBY_TX_EN_S  4
-/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
- *  This register is used to delay the receiver's internal data signal.
- */
-#define UART_RS485_RX_DLY_NUM    (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
-#define UART_RS485_RX_DLY_NUM_V  0x00000001U
-#define UART_RS485_RX_DLY_NUM_S  5
-/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
- *  This register is used to delay the transmitter's internal data signal.
- */
-#define UART_RS485_TX_DLY_NUM    0x0000000FU
-#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
-#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
-#define UART_RS485_TX_DLY_NUM_S  6
-
-/** UART_AT_CMD_PRECNT_SYNC_REG(i) register
- *  Pre-sequence timing configuration
- */
-#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
-/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the idle duration time before the first at_cmd
- *  is received by receiver.
- */
-#define UART_PRE_IDLE_NUM    0x0000FFFFU
-#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
-#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
-#define UART_PRE_IDLE_NUM_S  0
-
-/** UART_AT_CMD_POSTCNT_SYNC_REG(i) register
- *  Post-sequence timing configuration
- */
-#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
-/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the duration time between the last at_cmd and
- *  the next data.
- */
-#define UART_POST_IDLE_NUM    0x0000FFFFU
-#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
-#define UART_POST_IDLE_NUM_V  0x0000FFFFU
-#define UART_POST_IDLE_NUM_S  0
-
-/** UART_AT_CMD_GAPTOUT_SYNC_REG(i) register
- *  Timeout configuration
- */
-#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
-/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
- *  This register is used to configure the duration time between the at_cmd chars.
- */
-#define UART_RX_GAP_TOUT    0x0000FFFFU
-#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
-#define UART_RX_GAP_TOUT_V  0x0000FFFFU
-#define UART_RX_GAP_TOUT_S  0
-
-/** UART_AT_CMD_CHAR_SYNC_REG(i) register
- *  AT escape sequence detection configuration
- */
-#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
-/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
- *  This register is used to configure the content of at_cmd char.
- */
-#define UART_AT_CMD_CHAR    0x000000FFU
-#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
-#define UART_AT_CMD_CHAR_V  0x000000FFU
-#define UART_AT_CMD_CHAR_S  0
-/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
- *  This register is used to configure the num of continuous at_cmd chars received by
- *  receiver.
- */
-#define UART_CHAR_NUM    0x000000FFU
-#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
-#define UART_CHAR_NUM_V  0x000000FFU
-#define UART_CHAR_NUM_S  8
-
-/** UART_MEM_CONF_REG(i) register
- *  UART memory power configuration
- */
-#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
-/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
- *  Set this bit to force power down UART memory.
- */
-#define UART_MEM_FORCE_PD    (BIT(25))
-#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
-#define UART_MEM_FORCE_PD_V  0x00000001U
-#define UART_MEM_FORCE_PD_S  25
-/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
- *  Set this bit to force power up UART memory.
- */
-#define UART_MEM_FORCE_PU    (BIT(26))
-#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
-#define UART_MEM_FORCE_PU_V  0x00000001U
-#define UART_MEM_FORCE_PU_S  26
-
-/** UART_TOUT_CONF_SYNC_REG(i) register
- *  UART threshold and allocation configuration
- */
-#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
-/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
- */
-#define UART_RX_TOUT_EN    (BIT(0))
-#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
-#define UART_RX_TOUT_EN_V  0x00000001U
-#define UART_RX_TOUT_EN_S  0
-/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
- *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
- */
-#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
-#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
-#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
-#define UART_RX_TOUT_FLOW_DIS_S  1
-/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
- *  This register is used to configure the threshold time that receiver takes to
- *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
- *  takes more time to receive one byte with rx_tout_en set to 1.
- */
-#define UART_RX_TOUT_THRHD    0x000003FFU
-#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
-#define UART_RX_TOUT_THRHD_V  0x000003FFU
-#define UART_RX_TOUT_THRHD_S  2
-
-/** UART_MEM_TX_STATUS_REG(i) register
- *  Tx-SRAM write and read offset address.
- */
-#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
-/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
- *  This register stores the offset write address in Tx-SRAM.
- */
-#define UART_TX_SRAM_WADDR    0x000000FFU
-#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
-#define UART_TX_SRAM_WADDR_V  0x000000FFU
-#define UART_TX_SRAM_WADDR_S  0
-/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
- *  This register stores the offset read address in Tx-SRAM.
- */
-#define UART_TX_SRAM_RADDR    0x000000FFU
-#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
-#define UART_TX_SRAM_RADDR_V  0x000000FFU
-#define UART_TX_SRAM_RADDR_S  9
-
-/** UART_MEM_RX_STATUS_REG(i) register
- *  Rx-SRAM write and read offset address.
- */
-#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
-/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
- *  This register stores the offset read address in RX-SRAM.
- */
-#define UART_RX_SRAM_RADDR    0x000000FFU
-#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
-#define UART_RX_SRAM_RADDR_V  0x000000FFU
-#define UART_RX_SRAM_RADDR_S  0
-/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
- *  This register stores the offset write address in Rx-SRAM.
- */
-#define UART_RX_SRAM_WADDR    0x000000FFU
-#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
-#define UART_RX_SRAM_WADDR_V  0x000000FFU
-#define UART_RX_SRAM_WADDR_S  9
-
-/** UART_FSM_STATUS_REG(i) register
- *  UART transmit and receive status.
- */
-#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
-/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
- *  This is the status register of receiver.
- */
-#define UART_ST_URX_OUT    0x0000000FU
-#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
-#define UART_ST_URX_OUT_V  0x0000000FU
-#define UART_ST_URX_OUT_S  0
-/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
- *  This is the status register of transmitter.
- */
-#define UART_ST_UTX_OUT    0x0000000FU
-#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
-#define UART_ST_UTX_OUT_V  0x0000000FU
-#define UART_ST_UTX_OUT_S  4
-
-/** UART_POSPULSE_REG(i) register
- *  Autobaud high pulse register
- */
-#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
-/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two positive edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_POSEDGE_MIN_CNT    0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
-#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_S  0
-
-/** UART_NEGPULSE_REG(i) register
- *  Autobaud low pulse register
- */
-#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
-/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two negative edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
-#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_S  0
-
-/** UART_LOWPULSE_REG(i) register
- *  Autobaud minimum low pulse duration register
- */
-#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
-/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the value of the minimum duration time of the low level pulse.
- *  It is used in baud rate-detect process.
- */
-#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
-#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_S  0
-
-/** UART_HIGHPULSE_REG(i) register
- *  Autobaud minimum high pulse duration register
- */
-#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
-/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores  the value of the maxinum duration time for the high level
- *  pulse. It is used in baud rate-detect process.
- */
-#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
-#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_S  0
-
-/** UART_RXD_CNT_REG(i) register
- *  Autobaud edge change count register
- */
-#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
-/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
- *  This register stores the count of rxd edge change. It is used in baud rate-detect
- *  process.
- */
-#define UART_RXD_EDGE_CNT    0x000003FFU
-#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
-#define UART_RXD_EDGE_CNT_V  0x000003FFU
-#define UART_RXD_EDGE_CNT_S  0
-
-/** UART_DATE_REG(i) register
- *  UART Version register
- */
-#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
-/** UART_DATE : R/W; bitpos: [31:0]; default: 35680848;
- *  This is the version register.
- */
-#define UART_DATE    0xFFFFFFFFU
-#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
-#define UART_DATE_V  0xFFFFFFFFU
-#define UART_DATE_S  0
-
-/** UART_AFIFO_STATUS_REG(i) register
- *  UART AFIFO Status
- */
-#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
-/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
- *  Full signal of APB TX AFIFO.
- */
-#define UART_TX_AFIFO_FULL    (BIT(0))
-#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
-#define UART_TX_AFIFO_FULL_V  0x00000001U
-#define UART_TX_AFIFO_FULL_S  0
-/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
- *  Empty signal of APB TX AFIFO.
- */
-#define UART_TX_AFIFO_EMPTY    (BIT(1))
-#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
-#define UART_TX_AFIFO_EMPTY_V  0x00000001U
-#define UART_TX_AFIFO_EMPTY_S  1
-/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
- *  Full signal of APB RX AFIFO.
- */
-#define UART_RX_AFIFO_FULL    (BIT(2))
-#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
-#define UART_RX_AFIFO_FULL_V  0x00000001U
-#define UART_RX_AFIFO_FULL_S  2
-/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
- *  Empty signal of APB RX AFIFO.
- */
-#define UART_RX_AFIFO_EMPTY    (BIT(3))
-#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
-#define UART_RX_AFIFO_EMPTY_V  0x00000001U
-#define UART_RX_AFIFO_EMPTY_S  3
-
-/** UART_REG_UPDATE_REG(i) register
- *  UART Registers Configuration Update register
- */
-#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
-/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
- *  Software write 1 would synchronize registers into UART Core clock domain and would
- *  be cleared by hardware after synchronization is done.
- */
-#define UART_REG_UPDATE    (BIT(0))
-#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
-#define UART_REG_UPDATE_V  0x00000001U
-#define UART_REG_UPDATE_S  0
-
-/** UART_ID_REG(i) register
- *  UART ID register
- */
-#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
-/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
- *  This register is used to configure the uart_id.
- */
-#define UART_ID    0xFFFFFFFFU
-#define UART_ID_M  (UART_ID_V << UART_ID_S)
-#define UART_ID_V  0xFFFFFFFFU
-#define UART_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/uart_struct.h b/components/soc/esp32h2/include/soc/uart_struct.h
deleted file mode 100644
index 467f86ff5a4..00000000000
--- a/components/soc/esp32h2/include/soc/uart_struct.h
+++ /dev/null
@@ -1,1243 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
-         *  UART $n accesses FIFO via this register.
-         */
-        uint32_t rxfifo_rd_byte:32;
-    };
-    uint32_t val;
-} uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  This register is used to configure the threshold time that receiver takes to
-         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
-         *  takes more time to receive one byte with rx_tout_en set to 1.
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  what rxfifo_full_thrhd specifies.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1;
-         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-         *  less than what txfifo_empty_thrhd specifies .
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error in
-         *  the data.
-         */
-        uint32_t parity_err:1;
-        /** frm_err : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  .
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  the FIFO can store.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  DSRn signal.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  CTSn signal.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
-         *  bit.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver takes more time than
-         *  rx_tout_thrhd to receive a byte.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det : R/WTC/SS; bitpos: [11]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
-         *  middle of a start bit.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter completes  sending
-         *  NULL characters after all data in Tx-FIFO are sent.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
-         *  duration after sending the  last data.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done : R/WTC/SS; bitpos: [14]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has send out all data
-         *  in FIFO.
-         */
-        uint32_t tx_done:1;
-        /** rs485_parity_err : R/WTC/SS; bitpos: [15]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_parity_err:1;
-        /** rs485_frm_err : R/WTC/SS; bitpos: [16]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_frm_err:1;
-        /** rs485_clash : R/WTC/SS; bitpos: [17]; default: 0;
-         *  This interrupt raw bit turns to high level when detects a clash between transmitter
-         *  and receiver in rs485 mode.
-         */
-        uint32_t rs485_clash:1;
-        /** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the configured
-         *  at_cmd char.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup : R/WTC/SS; bitpos: [19]; default: 0;
-         *  This interrupt raw bit turns to high level when input rxd edge changes more times
-         *  than what reg_active_threshold specifies in light sleeping mode.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full : RO; bitpos: [0]; default: 0;
-         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty : RO; bitpos: [1]; default: 0;
-         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
-         *  to 1.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err : RO; bitpos: [2]; default: 0;
-         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-         */
-        uint32_t parity_err:1;
-        /** frm_err : RO; bitpos: [3]; default: 0;
-         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf : RO; bitpos: [4]; default: 0;
-         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg : RO; bitpos: [5]; default: 0;
-         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg : RO; bitpos: [6]; default: 0;
-         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det : RO; bitpos: [7]; default: 0;
-         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout : RO; bitpos: [8]; default: 0;
-         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon : RO; bitpos: [9]; default: 0;
-         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff : RO; bitpos: [10]; default: 0;
-         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det : RO; bitpos: [11]; default: 0;
-         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done : RO; bitpos: [12]; default: 0;
-         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
-         *  is set to 1.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done : RO; bitpos: [14]; default: 0;
-         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-         */
-        uint32_t tx_done:1;
-        /** rs485_parity_err : RO; bitpos: [15]; default: 0;
-         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-         *  set to 1.
-         */
-        uint32_t rs485_parity_err:1;
-        /** rs485_frm_err : RO; bitpos: [16]; default: 0;
-         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
-         *  to 1.
-         */
-        uint32_t rs485_frm_err:1;
-        /** rs485_clash : RO; bitpos: [17]; default: 0;
-         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
-         */
-        uint32_t rs485_clash:1;
-        /** at_cmd_char_det : RO; bitpos: [18]; default: 0;
-         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
-         *  to 1.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup : RO; bitpos: [19]; default: 0;
-         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full: R/W; bitpos: [0]; default: 0;
-         *  This is the enable bit for rxfifo_full_int_st register.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty: R/W; bitpos: [1]; default: 0;
-         *  This is the enable bit for txfifo_empty_int_st register.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err: R/W; bitpos: [2]; default: 0;
-         *  This is the enable bit for parity_err_int_st register.
-         */
-        uint32_t parity_err:1;
-        /** frm_err: R/W; bitpos: [3]; default: 0;
-         *  This is the enable bit for frm_err_int_st register.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf: R/W; bitpos: [4]; default: 0;
-         *  This is the enable bit for rxfifo_ovf_int_st register.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg: R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for dsr_chg_int_st register.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg: R/W; bitpos: [6]; default: 0;
-         *  This is the enable bit for cts_chg_int_st register.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det: R/W; bitpos: [7]; default: 0;
-         *  This is the enable bit for brk_det_int_st register.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout: R/W; bitpos: [8]; default: 0;
-         *  This is the enable bit for rxfifo_tout_int_st register.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon: R/W; bitpos: [9]; default: 0;
-         *  This is the enable bit for sw_xon_int_st register.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff: R/W; bitpos: [10]; default: 0;
-         *  This is the enable bit for sw_xoff_int_st register.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det: R/W; bitpos: [11]; default: 0;
-         *  This is the enable bit for glitch_det_int_st register.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done: R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for tx_brk_done_int_st register.
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done: R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit for tx_brk_idle_done_int_st register.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done: R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for tx_done_int_st register.
-         */
-        uint32_t tx_done:1;
-        /** rs485_parity_err: R/W; bitpos: [15]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_parity_err:1;
-        /** rs485_frm_err: R/W; bitpos: [16]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_frm_err:1;
-        /** rs485_clash: R/W; bitpos: [17]; default: 0;
-         *  This is the enable bit for rs485_clash_int_st register.
-         */
-        uint32_t rs485_clash:1;
-        /** at_cmd_char_det: R/W; bitpos: [18]; default: 0;
-         *  This is the enable bit for at_cmd_char_det_int_st register.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup: R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for uart_wakeup_int_st register.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full: WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
-         */
-        uint32_t rxfifo_full:1;
-        /** txfifo_empty: WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear txfifo_empty_int_raw interrupt.
-         */
-        uint32_t txfifo_empty:1;
-        /** parity_err: WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear parity_err_int_raw interrupt.
-         */
-        uint32_t parity_err:1;
-        /** frm_err: WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear frm_err_int_raw interrupt.
-         */
-        uint32_t frm_err:1;
-        /** rxfifo_ovf: WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-         */
-        uint32_t rxfifo_ovf:1;
-        /** dsr_chg: WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the dsr_chg_int_raw interrupt.
-         */
-        uint32_t dsr_chg:1;
-        /** cts_chg: WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the cts_chg_int_raw interrupt.
-         */
-        uint32_t cts_chg:1;
-        /** brk_det: WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the brk_det_int_raw interrupt.
-         */
-        uint32_t brk_det:1;
-        /** rxfifo_tout: WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-         */
-        uint32_t rxfifo_tout:1;
-        /** sw_xon: WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the sw_xon_int_raw interrupt.
-         */
-        uint32_t sw_xon:1;
-        /** sw_xoff: WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the sw_xoff_int_raw interrupt.
-         */
-        uint32_t sw_xoff:1;
-        /** glitch_det: WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the glitch_det_int_raw interrupt.
-         */
-        uint32_t glitch_det:1;
-        /** tx_brk_done: WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
-         */
-        uint32_t tx_brk_done:1;
-        /** tx_brk_idle_done: WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-         */
-        uint32_t tx_brk_idle_done:1;
-        /** tx_done: WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the tx_done_int_raw interrupt.
-         */
-        uint32_t tx_done:1;
-        /** rs485_parity_err: WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
-         */
-        uint32_t rs485_parity_err:1;
-        /** rs485_frm_err: WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
-         */
-        uint32_t rs485_frm_err:1;
-        /** rs485_clash: WT; bitpos: [17]; default: 0;
-         *  Set this bit to clear the rs485_clash_int_raw interrupt.
-         */
-        uint32_t rs485_clash:1;
-        /** at_cmd_char_det: WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-         */
-        uint32_t at_cmd_char_det:1;
-        /** wakeup: WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
-         */
-        uint32_t wakeup:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t clkdiv_int:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  The decimal part of the frequency divider factor.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  Rx Filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  when input pulse width is lower than this value the pulse is ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable Rx signal filter.
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  a
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  This register is used to configure the parity check mode.
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable uart parity check.
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  This register is used to set the length of data.
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  This register is used to set the length of  stop bit.
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
-         *  is done.
-         */
-        uint32_t txd_brk:1;
-        /** irda_dplx : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to enable IrDA loopback mode.
-         */
-        uint32_t irda_dplx:1;
-        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
-         *  This is the start enable bit for IrDA transmitter.
-         */
-        uint32_t irda_tx_en:1;
-        /** irda_wctl : R/W; bitpos: [9]; default: 0;
-         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-         *  transmitter's 11th bit to 0.
-         */
-        uint32_t irda_wctl:1;
-        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to invert the level of  IrDA transmitter.
-         */
-        uint32_t irda_tx_inv:1;
-        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
-         *  Set this bit to invert the level of IrDA receiver.
-         */
-        uint32_t irda_rx_inv:1;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable uart loopback test mode.
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to enable flow control function for transmitter.
-         */
-        uint32_t tx_flow_en:1;
-        /** irda_en : R/W; bitpos: [14]; default: 0;
-         *  Set this bit to enable IrDA protocol.
-         */
-        uint32_t irda_en:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Set this bit to inverse the level value of uart rxd signal.
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart txd signal.
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Disable UART Rx data overflow detect.
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-         *  stores the data even if the  received data is wrong.
-         */
-        uint32_t err_wr_mask:1;
-        /** autobaud_en : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for detecting baudrate.
-         */
-        uint32_t autobaud_en:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 1;
-         *  UART memory clock gate enable signal.
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  This register is used to configure the software rts signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Set this bit to reset the uart receive-FIFO.
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Set this bit to reset the uart transmit-FIFO.
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
-         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
-         *  this register value.
-         */
-        uint32_t rxfifo_full_thrhd:8;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
-         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
-         *  than this register value.
-         */
-        uint32_t txfifo_empty_thrhd:8;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart cts signal.
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to inverse the level value of uart dsr signal.
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to inverse the level value of uart rts signal.
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to inverse the level value of uart dtr signal.
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  This register is used to configure the software dtr signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow-control configuration
- */
-typedef union {
-    struct {
-        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
-         *  This register is used to configure the maximum amount of data that can be received
-         *  when hardware flow control works.
-         */
-        uint32_t rx_flow_thrhd:8;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  This is the flow enable bit for UART receiver.
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configure register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified wake up char1 to wake up
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  This register restores the specified wake up char2 to wake up
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  This register restores the specified wake up char3 to wake up
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  This register restores the specified wake up char4 to wake up
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configure register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified char0 to wake up
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configure register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  The uart is activated from light sleeping mode when the input rxd edge changes more
-         *  times than this register value.
-         */
-        uint32_t active_threshold:10;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
-         *  In wake up mode 1 this field is used to set the received data number threshold to
-         *  wake up chip.
-         */
-        uint32_t rx_wake_up_thrhd:8;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  This register is used to select number of wake up char.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  This register is used to mask  wake up char.
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
-         *  received data number larger than
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  This register stores the Xon flow control char.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  This register stores the Xoff flow control char.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
-         *  this status, UART Tx can not transmit XOFF even the received data number is larger
-         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
-         *  UART Tx is disabled.
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to enable software flow control. It is used with register sw_xon or
-         *  sw_xoff.
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to remove flow control char from the received data.
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to enable the transmitter to go on sending data.
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Set this bit to stop the  transmitter from sending data.
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Set this bit to send Xon char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
-         *  When the data amount in Rx-FIFO is less than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
-         */
-        uint32_t xon_threshold:8;
-        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
-         *  When the data amount in Rx-FIFO is more than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
-         */
-        uint32_t xoff_threshold:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  Tx Break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  This register is used to configure the number of 0 to be sent after the process of
-         *  sending data is done. It is active when txd_brk is set to 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame-end idle configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  It will produce frame end signal when receiver takes more time to receive one byte
-         *  data than this register value.
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  This register is used to configure the duration time between transfers.
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        /** rs485_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to choose the rs485 mode.
-         */
-        uint32_t rs485_en:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl1_en:1;
-        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable receiver could receive data when the transmitter is
-         *  transmitting data in rs485 mode.
-         */
-        uint32_t rs485tx_rx_en:1;
-        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
-         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-         */
-        uint32_t rs485rxby_tx_en:1;
-        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
-         *  This register is used to delay the receiver's internal data signal.
-         */
-        uint32_t rs485_rx_dly_num:1;
-        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
-         *  This register is used to delay the transmitter's internal data signal.
-         */
-        uint32_t rs485_tx_dly_num:4;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rs485_conf_sync_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
-         *  Stores the byte number of valid data in Rx-FIFO.
-         */
-        uint32_t rxfifo_cnt:8;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  The register represent the level value of the internal uart dsr signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  This register represent the level value of the internal uart cts signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  This register represent the  level value of the internal uart rxd signal.
-         */
-        uint32_t rxd:1;
-        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
-         *  Stores the byte number of data in Tx-FIFO.
-         */
-        uint32_t txfifo_cnt:8;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  This bit represents the level of the internal uart dtr signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  This bit represents the level of the internal uart rts signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  This bit represents the  level of the internal uart txd signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  Tx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
-         *  This register stores the offset write address in Tx-SRAM.
-         */
-        uint32_t tx_sram_waddr:8;
-        uint32_t reserved_8:1;
-        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
-         *  This register stores the offset read address in Tx-SRAM.
-         */
-        uint32_t tx_sram_raddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
-         *  This register stores the offset read address in RX-SRAM.
-         */
-        uint32_t rx_sram_raddr:8;
-        uint32_t reserved_8:1;
-        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
-         *  This register stores the offset write address in Rx-SRAM.
-         */
-        uint32_t rx_sram_waddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status.
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  This is the status register of receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  This is the status register of transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART AFIFO Status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Full signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Empty signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Full signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Empty signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the idle duration time before the first at_cmd
-         *  is received by receiver.
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the duration time between the last at_cmd and
-         *  the next data.
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  This register is used to configure the duration time between the at_cmd chars.
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** data : R/W; bitpos: [7:0]; default: 43;
-         *  This register is used to configure the content of at_cmd char.
-         */
-        uint32_t data:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  This register is used to configure the num of continuous at_cmd chars received by
-         *  receiver.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Autobaud Register */
-/** Type of pospulse register
- *  Autobaud high pulse register
- */
-typedef union {
-    struct {
-        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two positive edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t posedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_pospulse_reg_t;
-
-/** Type of negpulse register
- *  Autobaud low pulse register
- */
-typedef union {
-    struct {
-        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two negative edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t negedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_negpulse_reg_t;
-
-/** Type of lowpulse register
- *  Autobaud minimum low pulse duration register
- */
-typedef union {
-    struct {
-        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the value of the minimum duration time of the low level pulse.
-         *  It is used in baud rate-detect process.
-         */
-        uint32_t lowpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_lowpulse_reg_t;
-
-/** Type of highpulse register
- *  Autobaud minimum high pulse duration register
- */
-typedef union {
-    struct {
-        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores  the value of the maxinum duration time for the high level
-         *  pulse. It is used in baud rate-detect process.
-         */
-        uint32_t highpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_highpulse_reg_t;
-
-/** Type of rxd_cnt register
- *  Autobaud edge change count register
- */
-typedef union {
-    struct {
-        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
-         *  This register stores the count of rxd edge change. It is used in baud rate-detect
-         *  process.
-         */
-        uint32_t rxd_edge_cnt:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rxd_cnt_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 35656288;
-         *  This is the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART Registers Configuration Update register
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Software write 1 would synchronize registers into UART Core clock domain and would
-         *  be cleared by hardware after synchronization is done.
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  This register is used to configure the uart_id.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} uart_id_reg_t;
-
-
-typedef struct uart_dev_s {
-    volatile uart_fifo_reg_t fifo;
-    volatile uart_int_raw_reg_t int_raw;
-    volatile uart_int_st_reg_t int_st;
-    volatile uart_int_ena_reg_t int_ena;
-    volatile uart_int_clr_reg_t int_clr;
-    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile uart_rx_filt_reg_t rx_filt;
-    volatile uart_status_reg_t status;
-    volatile uart_conf0_sync_reg_t conf0_sync;
-    volatile uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile uart_sleep_conf0_reg_t sleep_conf0;
-    volatile uart_sleep_conf1_reg_t sleep_conf1;
-    volatile uart_sleep_conf2_reg_t sleep_conf2;
-    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile uart_swfc_conf1_reg_t swfc_conf1;
-    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile uart_mem_conf_reg_t mem_conf;
-    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile uart_mem_tx_status_reg_t mem_tx_status;
-    volatile uart_mem_rx_status_reg_t mem_rx_status;
-    volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;
-    volatile uart_negpulse_reg_t negpulse;
-    volatile uart_lowpulse_reg_t lowpulse;
-    volatile uart_highpulse_reg_t highpulse;
-    volatile uart_rxd_cnt_reg_t rxd_cnt;
-    uint32_t reserved_088;
-    volatile uart_date_reg_t date;
-    volatile uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile uart_reg_update_reg_t reg_update;
-    volatile uart_id_reg_t id;
-} uart_dev_t;
-
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h
deleted file mode 100644
index eb4b8a1e039..00000000000
--- a/components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h
+++ /dev/null
@@ -1,1188 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** USB_SERIAL_JTAG_EP1_REG register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
- *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
- *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
- *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
- *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
- *  how many data is received, then read data from UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
- *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
- */
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
-#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
- *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
- *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
- *  USB Host.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
- *  1'b1: Indicate there is data in UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- *  Interrupt raw status register.
- */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when flush cmd is received for IN
- *  endpoint 2 of JTAG.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when SOF frame is received.
- */
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- *  one packet.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
- *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when pid error is detected.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt bit turns to high level when CRC5 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt bit turns to high level when CRC16 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt bit turns to high level when stuff error is detected.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
- *  received.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt bit turns to high level when usb bus reset is detected.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
-
-/** USB_SERIAL_JTAG_INT_ST_REG register
- *  Interrupt status register.
- */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
- *  interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
- *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
-
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- *  Interrupt enable status register.
- */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
-
-/** USB_SERIAL_JTAG_INT_CLR_REG register
- *  Interrupt clear status register.
- */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
-
-/** USB_SERIAL_JTAG_CONF0_REG register
- *  PHY hardware configuration.
- */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  Select internal/external PHY
- */
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
- *  Enable software control USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
- *  USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
- *  Control single-end input high threshold,1.76V to 2V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFH    0x00000003U
-#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
-#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFH_S  3
-/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
- *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFL    0x00000003U
-#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
-#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFL_S  5
-/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
- *  Enable software control input  threshold
- */
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
- *  Enable software control USB D+ D- pullup pulldown
- */
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
- *  Control USB D+ pull up.
- */
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
- *  Control USB D+ pull down.
- */
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
- *  Control USB D- pull up.
- */
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
- *  Control USB D- pull down.
- */
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
- *  Control pull up value.
- */
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
- *  Enable USB pad function.
- */
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
- *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
- *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
- *  through GPIO Matrix.
- */
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
-
-/** USB_SERIAL_JTAG_TEST_REG register
- *  Registers used for debugging the PHY.
- */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
-/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Enable test of the USB pad
- */
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad oen in test
- */
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- *  USB D+ tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- *  USB D- tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
- *  USB RCV value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
-#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
-/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
- *  USB D+ rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
-#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
-/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
- *  USB D- rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
-#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
-
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- *  JTAG FIFO status and control registers.
- */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
- *  JTAT in fifo counter.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- *  1: JTAG in fifo is empty.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
- *  1: JTAG in fifo is full.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
- *  JTAT out fifo counter.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
- *  1: JTAG out fifo is empty.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
- *  1: JTAG out fifo is full.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
- *  Write 1 to reset JTAG in fifo.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
- *  Write 1 to reset JTAG out fifo.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- *  Last received SOF frame index register.
- */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
- *  Frame index of received SOF frame.
- */
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- *  Control IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- *  CDC-ACM IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
-/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- *  JTAG IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- *  Control OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- *  CDC-ACM OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
-/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
- *  Data count in OUT endpoint 1 when one packet is received.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- *  JTAG OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
- *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- *  Clock enable control
- */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
-#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- *  Memory power control
- */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  1: power down usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  1: Force clock on for usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-
-/** USB_SERIAL_JTAG_CHIP_RST_REG register
- *  CDC-ACM chip reset control.
- */
-#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
-/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
- *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_RTS    (BIT(0))
-#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
-#define USB_SERIAL_JTAG_RTS_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_S  0
-/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
- *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_DTR    (BIT(1))
-#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
-#define USB_SERIAL_JTAG_DTR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_S  1
-/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
- *  Set this bit to disable chip reset from usb serial channel to reset chip.
- */
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
- *  W0 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
-/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
- *  W1 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
-/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
-/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_S  16
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
- *  W0 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
-/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
- *  W1 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
-/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
-/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
-
-/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
- *  Configuration registers' value update
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
-/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
- *  Write 1 to this register would update the value of configure registers from APB
- *  clock domain to 48MHz clock domain.
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
-
-/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
- *  Serial AFIFO configure register
- */
-#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
- *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
-
-/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
- *  USB Bus reset status register
- */
-#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
-/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
- *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
- *  reset is released.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
-
-/** USB_SERIAL_JTAG_DATE_REG register
- *  Date register
- */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416;
- *  register version.
- */
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/include/soc/xts_aes_reg.h b/components/soc/esp32h2/include/soc/xts_aes_reg.h
deleted file mode 100644
index ab5f66583ed..00000000000
--- a/components/soc/esp32h2/include/soc/xts_aes_reg.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define XTS_AES_PLAIN_MEM(i)          (REG_SPI_MEM_BASE(i) + 0x300)
-/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This field is only used to generate include file in c case. This field is useles
-s. Please do not use this field..*/
-#define XTS_AES_PLAIN    0xFFFFFFFF
-#define XTS_AES_PLAIN_M  ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
-#define XTS_AES_PLAIN_V  0xFFFFFFFF
-#define XTS_AES_PLAIN_S  0
-
-#define XTS_AES_LINESIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x340)
-/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the line-size parameter which will be used in manual encryption
- calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
- 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
-#define XTS_AES_LINESIZE    0x00000003
-#define XTS_AES_LINESIZE_M  ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
-#define XTS_AES_LINESIZE_V  0x3
-#define XTS_AES_LINESIZE_S  0
-
-#define XTS_AES_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
-/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit stores the destination parameter which will be used in manual encryptio
-n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
-used..*/
-#define XTS_AES_DESTINATION    (BIT(0))
-#define XTS_AES_DESTINATION_M  (BIT(0))
-#define XTS_AES_DESTINATION_V  0x1
-#define XTS_AES_DESTINATION_S  0
-
-#define XTS_AES_PHYSICAL_ADDRESS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x348)
-/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
-/*description: This bits stores the physical-address parameter which will be used in manual enc
-ryption calculation. This value should aligned with byte number decided by line-
-size parameter..*/
-#define XTS_AES_PHYSICAL_ADDRESS    0x03FFFFFF
-#define XTS_AES_PHYSICAL_ADDRESS_M  ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
-#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFF
-#define XTS_AES_PHYSICAL_ADDRESS_S  0
-
-#define XTS_AES_TRIGGER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34C)
-/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to trigger the process of manual encryption calculation. This actio
-n should only be asserted when manual encryption status is 0. After this action,
- manual encryption status becomes 1. After calculation is done, manual encryptio
-n status becomes 2..*/
-#define XTS_AES_TRIGGER    (BIT(0))
-#define XTS_AES_TRIGGER_M  (BIT(0))
-#define XTS_AES_TRIGGER_V  0x1
-#define XTS_AES_TRIGGER_S  0
-
-#define XTS_AES_RELEASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x350)
-/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to release encrypted result to mspi. This action should only be ass
-erted when manual encryption status is 2. After this action, manual encryption s
-tatus will become 3..*/
-#define XTS_AES_RELEASE    (BIT(0))
-#define XTS_AES_RELEASE_M  (BIT(0))
-#define XTS_AES_RELEASE_V  0x1
-#define XTS_AES_RELEASE_S  0
-
-#define XTS_AES_DESTROY_REG(i)          (REG_SPI_MEM_BASE(i) + 0x354)
-/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
-en manual encryption status is 3. After this action, manual encryption status wi
-ll become 0..*/
-#define XTS_AES_DESTROY    (BIT(0))
-#define XTS_AES_DESTROY_M  (BIT(0))
-#define XTS_AES_DESTROY_V  0x1
-#define XTS_AES_DESTROY_S  0
-
-#define XTS_AES_STATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x358)
-/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
- calculation, 2: encryption calculation is done but the encrypted result is invi
-sible to mspi, 3: the encrypted result is visible to mspi..*/
-#define XTS_AES_STATE    0x00000003
-#define XTS_AES_STATE_M  ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
-#define XTS_AES_STATE_V  0x3
-#define XTS_AES_STATE_S  0
-
-#define XTS_AES_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x35C)
-/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
-/*description: This bits stores the last modified-time of manual encryption feature..*/
-#define XTS_AES_DATE    0x3FFFFFFF
-#define XTS_AES_DATE_M  ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
-#define XTS_AES_DATE_V  0x3FFFFFFF
-#define XTS_AES_DATE_S  0
-
-#define XTS_AES_DPA_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x388)
-/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
-T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V  0x1
-#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S  4
-/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
-ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
-ing key 1..*/
-#define XTS_AES_CRYPT_CALC_D_DPA_EN    (BIT(3))
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_V  0x1
-#define XTS_AES_CRYPT_CALC_D_DPA_EN_S  3
-/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
-7: The bigger the number is, the more secure the cryption is. (Note that the per
-formance of cryption will decrease together with this number increasing).*/
-#define XTS_AES_CRYPT_SECURITY_LEVEL    0x00000007
-#define XTS_AES_CRYPT_SECURITY_LEVEL_M  ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
-#define XTS_AES_CRYPT_SECURITY_LEVEL_V  0x7
-#define XTS_AES_CRYPT_SECURITY_LEVEL_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32h2/interrupts.c b/components/soc/esp32h2/interrupts.c
index c64a2247adc..68c6cd48bcc 100644
--- a/components/soc/esp32h2/interrupts.c
+++ b/components/soc/esp32h2/interrupts.c
@@ -38,7 +38,7 @@ const char *const esp_isr_names[] = {
     [28] = "HP_APM_M2",
     [29] = "HP_APM_M3",
     [30] = "MSPI",
-    [31] = "I2S1",
+    [31] = "I2S0",
     [32] = "UHCI0",
     [33] = "UART0",
     [34] = "UART1",
diff --git a/components/soc/esp32h2/ledc_periph.c b/components/soc/esp32h2/ledc_periph.c
index b150f9bc991..e20f002e5a3 100644
--- a/components/soc/esp32h2/ledc_periph.c
+++ b/components/soc/esp32h2/ledc_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,3 +15,141 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
 	}
 };
+
+/**
+ * LEDC registers to be saved for sleep retention
+ *
+ * channel:
+ * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
+ *
+ * timer:
+ * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
+ *
+ * common:
+ * LEDC_INT_ENA_REG,
+ * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
+ * LEDC_CONF_REG,
+ *
+ * Note 1: Gamma feature is hard to do hardware retention, will consider to use software to do the backup and restore.
+ * 		   We won't start a fade automatically after wake-up.
+ *         Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep.
+ *
+ * Note 2: For timer/channel registers to get synced, update bits need to be set
+ *
+ * Note 3: Retention backup/restore does not rely on LEDC function clock enabled
+ */
+#define LEDC_COMMON_RETENTION_REGS_CNT  5
+#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
+static const uint32_t ledc_common_regs_map[4] = {0x1, 0x1c00000, 0x400, 0x0};
+static const regdma_entries_config_t ledc_common_regdma_entries[] = {
+	// If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
+    // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
+			 							    LEDC_INT_ENA_REG, 0,
+			 							    (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1),
+		    .owner = LEDC_RETENTION_ENTRY },
+    [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
+                                               LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
+                                               LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
+                                               ledc_common_regs_map[0], ledc_common_regs_map[1],
+                                               ledc_common_regs_map[2], ledc_common_regs_map[3]),
+            .owner = LEDC_RETENTION_ENTRY },
+};
+
+#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
+	[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
+			 								     LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+			 								     LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
+			 							    LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
+static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
+#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
+	[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
+                                               LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
+                                               LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
+                                               ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
+                                               ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+                                                 LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
+			 							    LEDC_DUTY_START_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
+			 							    LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
+			 							    LEDC_PARA_UP_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
+
+static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
+static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
+static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+	.common = {
+		.regdma_entry_array = ledc_common_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
+	},
+	.timer[0] = {
+		.regdma_entry_array = ledc_timer0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
+	},
+	.timer[1] = {
+		.regdma_entry_array = ledc_timer1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
+	},
+	.timer[2] = {
+		.regdma_entry_array = ledc_timer2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
+	},
+	.timer[3] = {
+		.regdma_entry_array = ledc_timer3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
+	},
+	.channel[0] = {
+		.regdma_entry_array = ledc_channel0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
+	},
+	.channel[1] = {
+		.regdma_entry_array = ledc_channel1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
+	},
+	.channel[2] = {
+		.regdma_entry_array = ledc_channel2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
+	},
+	.channel[3] = {
+		.regdma_entry_array = ledc_channel3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
+	},
+	.channel[4] = {
+		.regdma_entry_array = ledc_channel4_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
+	},
+	.channel[5] = {
+		.regdma_entry_array = ledc_channel5_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
+	},
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};
diff --git a/components/soc/esp32h2/mcpwm_periph.c b/components/soc/esp32h2/mcpwm_periph.c
index f8806c57f13..9879e557f4d 100644
--- a/components/soc/esp32h2/mcpwm_periph.c
+++ b/components/soc/esp32h2/mcpwm_periph.c
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/soc.h"
 #include "soc/mcpwm_periph.h"
+#include "soc/mcpwm_reg.h"
 #include "soc/gpio_sig_map.h"
 
 const mcpwm_signal_conn_t mcpwm_periph_signals = {
@@ -81,3 +82,46 @@ const mcpwm_signal_conn_t mcpwm_periph_signals = {
         },
     }
 };
+
+/**
+ * MCPWM Registers to be saved during sleep retention
+ * - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
+ * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
+ * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
+ *   |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
+ *   |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
+ *   |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
+ *   └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
+ * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
+ * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
+ * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
+ * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
+*/
+#define MCPWM_RETENTION_REGS_CNT 61
+#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
+static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
+static const regdma_entries_config_t mcpwm_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
+                                               MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
+                                               MCPWM_RETENTION_REGS_CNT, 0, 0,
+                                               mcpwm_regs_map[0], mcpwm_regs_map[1],
+                                               mcpwm_regs_map[2], mcpwm_regs_map[3]),
+                                               .owner = ENTRY(0) | ENTRY(2) },
+    // restore stage: trigger a forced update of all active registers
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
+                                                MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
+                                                .owner = ENTRY(0) | ENTRY(2) },
+    [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
+                                                MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = mcpwm_regs_retention,
+        .array_size = ARRAY_SIZE(mcpwm_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_MCPWM0
+    },
+};
diff --git a/components/soc/esp32h2/parlio_periph.c b/components/soc/esp32h2/parlio_periph.c
index 6cc86f13cbf..bd17bfceb11 100644
--- a/components/soc/esp32h2/parlio_periph.c
+++ b/components/soc/esp32h2/parlio_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -48,3 +48,31 @@ const parlio_signal_conn_t parlio_periph_signals = {
         },
     },
 };
+
+/**
+ * PARLIO Registers to be saved during sleep retention
+ * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG
+ * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG
+ * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG
+ * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG
+*/
+#define PARLIO_RETENTION_REGS_CNT 8
+#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0)
+static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0};
+static const regdma_entries_config_t parlio_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \
+                                               PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \
+                                               PARLIO_RETENTION_REGS_CNT, 0, 0, \
+                                               parlio_regs_map[0], parlio_regs_map[1], \
+                                               parlio_regs_map[2], parlio_regs_map[3]), \
+                                               .owner = ENTRY(0) | ENTRY(2) }, \
+};
+const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = parlio_regs_retention,
+        .array_size = ARRAY_SIZE(parlio_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_PARLIO0
+    },
+};
diff --git a/components/soc/esp32h2/pcnt_periph.c b/components/soc/esp32h2/pcnt_periph.c
index b2b440245b7..14c52fc0d62 100644
--- a/components/soc/esp32h2/pcnt_periph.c
+++ b/components/soc/esp32h2/pcnt_periph.c
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/pcnt_periph.h"
 #include "soc/gpio_sig_map.h"
+#include "soc/pcnt_reg.h"
 
 const pcnt_signal_conn_t pcnt_periph_signals = {
     .groups = {
@@ -64,3 +65,30 @@ const pcnt_signal_conn_t pcnt_periph_signals = {
         }
     }
 };
+
+/**
+ * PCNT Registers to be saved during sleep retention
+ * - Configuration registers, e.g.: PCNT_CTRL_REG, PCNT_U0_CONF0_REG, PCNT_U0_CONF1_REG, PCNT_U0_CONF2_REG, PCNT_U1_CONF0_REG...
+ * - Interrupt enable registers, e.g.: PCNT_INT_ENA_REG
+*/
+#define PCNT_RETENTION_REGS_CNT 14
+#define PCNT_RETENTION_REGS_BASE (DR_REG_PCNT_BASE + 0x0)
+static const uint32_t pcnt_regs_map[4] = {0x1040fff, 0x0, 0x0, 0x0};
+static const regdma_entries_config_t pcnt_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \
+                                               PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \
+                                               PCNT_RETENTION_REGS_CNT, 0, 0, \
+                                               pcnt_regs_map[0], pcnt_regs_map[1], \
+                                               pcnt_regs_map[2], pcnt_regs_map[3]), \
+                                               .owner = ENTRY(0) | ENTRY(2) }, \
+};
+
+const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = pcnt_regs_retention,
+        .array_size = ARRAY_SIZE(pcnt_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_PCNT0
+    },
+};
diff --git a/components/soc/esp32h2/register/soc/.gitkeep b/components/soc/esp32h2/register/soc/.gitkeep
deleted file mode 100644
index e69de29bb2d..00000000000
diff --git a/components/soc/esp32h2/include/soc/aes_reg.h b/components/soc/esp32h2/register/soc/aes_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/aes_reg.h
rename to components/soc/esp32h2/register/soc/aes_reg.h
diff --git a/components/soc/esp32h2/include/soc/aes_struct.h b/components/soc/esp32h2/register/soc/aes_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/aes_struct.h
rename to components/soc/esp32h2/register/soc/aes_struct.h
diff --git a/components/soc/esp32h2/include/soc/apb_saradc_reg.h b/components/soc/esp32h2/register/soc/apb_saradc_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/apb_saradc_reg.h
rename to components/soc/esp32h2/register/soc/apb_saradc_reg.h
diff --git a/components/soc/esp32h2/include/soc/apb_saradc_struct.h b/components/soc/esp32h2/register/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/apb_saradc_struct.h
rename to components/soc/esp32h2/register/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32h2/register/soc/assist_debug_reg.h b/components/soc/esp32h2/register/soc/assist_debug_reg.h
new file mode 100644
index 00000000000..d2b947d9466
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/assist_debug_reg.h
@@ -0,0 +1,777 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
+ *  IBUS busy monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
+ *  DBUS busy monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
+ *  DBUS busy monitor initerrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
+ *  DBUS busy monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
+
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0;
+ *  IBUS busy monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0;
+ *  DBUS busy monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
+ *  core0 area pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  the stackpointer when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
+ *  core0 area sp status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
+/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  the PC when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core0 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core0 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_0
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_1
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CLOCK_GATE_REG register
+ *  clock register
+ */
+#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
+/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 force on the clock gate
+ */
+#define ASSIST_DEBUG_CLK_EN    (BIT(0))
+#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
+#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
+#define ASSIST_DEBUG_CLK_EN_S  0
+
+/** ASSIST_DEBUG_DATE_REG register
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
+/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
+ *  version register
+ */
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/assist_debug_struct.h b/components/soc/esp32h2/register/soc/assist_debug_struct.h
new file mode 100644
index 00000000000..62323e8dbc1
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/assist_debug_struct.h
@@ -0,0 +1,717 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: monitor configuration registers */
+/** Type of core_0_intr_ena register
+ *  core0 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor enable
+         */
+        uint32_t core_0_area_dram0_0_rd_ena:1;
+        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor enable
+         */
+        uint32_t core_0_area_dram0_0_wr_ena:1;
+        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor enable
+         */
+        uint32_t core_0_area_dram0_1_rd_ena:1;
+        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor enable
+         */
+        uint32_t core_0_area_dram0_1_wr_ena:1;
+        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor enable
+         */
+        uint32_t core_0_area_pif_0_rd_ena:1;
+        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor enable
+         */
+        uint32_t core_0_area_pif_0_wr_ena:1;
+        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor enable
+         */
+        uint32_t core_0_area_pif_1_rd_ena:1;
+        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor enable
+         */
+        uint32_t core_0_area_pif_1_wr_ena:1;
+        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor enable
+         */
+        uint32_t core_0_sp_spill_min_ena:1;
+        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor enable
+         */
+        uint32_t core_0_sp_spill_max_ena:1;
+        /** core_0_iram0_exception_monitor_ena : R/W; bitpos: [10]; default: 0;
+         *  IBUS busy monitor enable
+         */
+        uint32_t core_0_iram0_exception_monitor_ena:1;
+        /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
+         *  DBUS busy monitor enable
+         */
+        uint32_t core_0_dram0_exception_monitor_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_ena_reg_t;
+
+/** Type of core_0_area_dram0_0_min register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region0 start addr
+         */
+        uint32_t core_0_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_min_reg_t;
+
+/** Type of core_0_area_dram0_0_max register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region0 end addr
+         */
+        uint32_t core_0_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_max_reg_t;
+
+/** Type of core_0_area_dram0_1_min register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region1 start addr
+         */
+        uint32_t core_0_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_min_reg_t;
+
+/** Type of core_0_area_dram0_1_max register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region1 end addr
+         */
+        uint32_t core_0_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_max_reg_t;
+
+/** Type of core_0_area_pif_0_min register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region0 start addr
+         */
+        uint32_t core_0_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_min_reg_t;
+
+/** Type of core_0_area_pif_0_max register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region0 end addr
+         */
+        uint32_t core_0_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_max_reg_t;
+
+/** Type of core_0_area_pif_1_min register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region1 start addr
+         */
+        uint32_t core_0_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_min_reg_t;
+
+/** Type of core_0_area_pif_1_max register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region1 end addr
+         */
+        uint32_t core_0_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_max_reg_t;
+
+/** Type of core_0_area_pc register
+ *  core0 area pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  the stackpointer when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pc_reg_t;
+
+/** Type of core_0_area_sp register
+ *  core0 area sp status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  the PC when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_sp_reg_t;
+
+/** Type of core_0_sp_min register
+ *  stack min value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  core0 sp region configuration register
+         */
+        uint32_t core_0_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_min_reg_t;
+
+/** Type of core_0_sp_max register
+ *  stack max value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  core0 sp pc status register
+         */
+        uint32_t core_0_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_max_reg_t;
+
+/** Type of core_0_sp_pc register
+ *  stack monitor pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the PC when trigger stack monitor.
+         */
+        uint32_t core_0_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_pc_reg_t;
+
+
+/** Group: interrupt configuration register */
+/** Type of core_0_intr_raw register
+ *  core0 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_rd_raw:1;
+        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_wr_raw:1;
+        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_rd_raw:1;
+        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_wr_raw:1;
+        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_rd_raw:1;
+        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_wr_raw:1;
+        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_rd_raw:1;
+        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_wr_raw:1;
+        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_min_raw:1;
+        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_max_raw:1;
+        /** core_0_iram0_exception_monitor_raw : RO; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt status
+         */
+        uint32_t core_0_iram0_exception_monitor_raw:1;
+        /** core_0_dram0_exception_monitor_raw : RO; bitpos: [11]; default: 0;
+         *  DBUS busy monitor initerrupt status
+         */
+        uint32_t core_0_dram0_exception_monitor_raw:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_raw_reg_t;
+
+/** Type of core_0_intr_rls register
+ *  core0 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_rd_rls:1;
+        /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_wr_rls:1;
+        /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_rd_rls:1;
+        /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_wr_rls:1;
+        /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_rd_rls:1;
+        /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_wr_rls:1;
+        /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_rd_rls:1;
+        /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_wr_rls:1;
+        /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_min_rls:1;
+        /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_max_rls:1;
+        /** core_0_iram0_exception_monitor_rls : R/W; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt enable
+         */
+        uint32_t core_0_iram0_exception_monitor_rls:1;
+        /** core_0_dram0_exception_monitor_rls : R/W; bitpos: [11]; default: 0;
+         *  DBUS busy monitor interrupt enable
+         */
+        uint32_t core_0_dram0_exception_monitor_rls:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_rls_reg_t;
+
+/** Type of core_0_intr_clr register
+ *  core0 monitor interrupt clr register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_rd_clr:1;
+        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_wr_clr:1;
+        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_rd_clr:1;
+        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_wr_clr:1;
+        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_rd_clr:1;
+        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_wr_clr:1;
+        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_rd_clr:1;
+        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_wr_clr:1;
+        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_min_clr:1;
+        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_max_clr:1;
+        /** core_0_iram0_exception_monitor_clr : WT; bitpos: [10]; default: 0;
+         *  IBUS busy monitor interrupt clr
+         */
+        uint32_t core_0_iram0_exception_monitor_clr:1;
+        /** core_0_dram0_exception_monitor_clr : WT; bitpos: [11]; default: 0;
+         *  DBUS busy monitor interrupt clr
+         */
+        uint32_t core_0_dram0_exception_monitor_clr:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_clr_reg_t;
+
+
+/** Group: pc recording configuration register */
+/** Type of core_0_rcd_en register
+ *  record enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable record PC
+         */
+        uint32_t core_0_rcd_recorden:1;
+        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+         */
+        uint32_t core_0_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_en_reg_t;
+
+
+/** Group: pc recording status register */
+/** Type of core_0_rcd_pdebugpc register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  recorded PC
+         */
+        uint32_t core_0_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugpc_reg_t;
+
+/** Type of core_0_rcd_pdebugsp register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  recorded sp
+         */
+        uint32_t core_0_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugsp_reg_t;
+
+
+/** Group: exception monitor register */
+/** Type of core_0_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_0
+         */
+        uint32_t core_0_iram0_recording_addr_0:24;
+        /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_0
+         */
+        uint32_t core_0_iram0_recording_wr_0:1;
+        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_0
+         */
+        uint32_t core_0_iram0_recording_loadstore_0:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_1
+         */
+        uint32_t core_0_iram0_recording_addr_1:24;
+        /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_1
+         */
+        uint32_t core_0_iram0_recording_wr_1:1;
+        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_1
+         */
+        uint32_t core_0_iram0_recording_loadstore_1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_0
+         */
+        uint32_t core_0_dram0_recording_addr_0:24;
+        /** core_0_dram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_dram0_recording_wr_0
+         */
+        uint32_t core_0_dram0_recording_wr_0:1;
+        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [28:25]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_0
+         */
+        uint32_t core_0_dram0_recording_byteen_0:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_0
+         */
+        uint32_t core_0_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_1
+         */
+        uint32_t core_0_dram0_recording_addr_1:24;
+        /** core_0_dram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_dram0_recording_wr_1
+         */
+        uint32_t core_0_dram0_recording_wr_1:1;
+        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [28:25]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_1
+         */
+        uint32_t core_0_dram0_recording_byteen_1:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_1
+         */
+        uint32_t core_0_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_0 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_0
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_1 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_1
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
+
+
+/** Group: cpu status registers */
+/** Type of core_0_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  cpu's lastpc before exception
+         */
+        uint32_t core_0_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_lastpc_before_exception_reg_t;
+
+/** Type of core_0_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
+         *  cpu debug mode status, 1 means cpu enter debug mode.
+         */
+        uint32_t core_0_debug_mode:1;
+        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  cpu debug_module active status
+         */
+        uint32_t core_0_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_debug_mode_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clock_gate register
+ *  clock register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 force on the clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} assist_debug_clock_gate_reg_t;
+
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
+         *  version register
+         */
+        uint32_t assist_debug_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} assist_debug_date_reg_t;
+
+
+typedef struct {
+    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
+    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
+    volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
+    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
+    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
+    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
+    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
+    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
+    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
+    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
+    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
+    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
+    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
+    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
+    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
+    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
+    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
+    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
+    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
+    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
+    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
+    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
+    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
+    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
+    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
+    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
+    volatile assist_debug_clock_gate_reg_t clock_gate;
+    uint32_t reserved_07c[224];
+    volatile assist_debug_date_reg_t date;
+} assist_debug_dev_t;
+
+extern assist_debug_dev_t ASSIST_DEBUG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/cache_reg.h b/components/soc/esp32h2/register/soc/cache_reg.h
new file mode 100644
index 00000000000..30181edf326
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/cache_reg.h
@@ -0,0 +1,6235 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CACHE_L1_ICACHE_CTRL_REG register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
+/** CACHE_L1_ICACHE_SHUT_IBUS0 : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
+#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
+/** CACHE_L1_ICACHE_SHUT_IBUS1 : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
+#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
+/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
+#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
+/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
+#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
+/** CACHE_L1_ICACHE_UNDEF_OP : HRO; bitpos: [7:4]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_UNDEF_OP    0x0000000FU
+#define CACHE_L1_ICACHE_UNDEF_OP_M  (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S)
+#define CACHE_L1_ICACHE_UNDEF_OP_V  0x0000000FU
+#define CACHE_L1_ICACHE_UNDEF_OP_S  4
+
+/** CACHE_L1_CACHE_CTRL_REG register
+ *  L1 data Cache(L1-Cache) control register
+ */
+#define CACHE_L1_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
+/** CACHE_L1_CACHE_SHUT_BUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L1_CACHE_SHUT_BUS0    (BIT(0))
+#define CACHE_L1_CACHE_SHUT_BUS0_M  (CACHE_L1_CACHE_SHUT_BUS0_V << CACHE_L1_CACHE_SHUT_BUS0_S)
+#define CACHE_L1_CACHE_SHUT_BUS0_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_BUS0_S  0
+/** CACHE_L1_CACHE_SHUT_BUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L1_CACHE_SHUT_BUS1    (BIT(1))
+#define CACHE_L1_CACHE_SHUT_BUS1_M  (CACHE_L1_CACHE_SHUT_BUS1_V << CACHE_L1_CACHE_SHUT_BUS1_S)
+#define CACHE_L1_CACHE_SHUT_BUS1_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_BUS1_S  1
+/** CACHE_L1_CACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_CACHE_SHUT_DBUS2    (BIT(2))
+#define CACHE_L1_CACHE_SHUT_DBUS2_M  (CACHE_L1_CACHE_SHUT_DBUS2_V << CACHE_L1_CACHE_SHUT_DBUS2_S)
+#define CACHE_L1_CACHE_SHUT_DBUS2_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_DBUS2_S  2
+/** CACHE_L1_CACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_CACHE_SHUT_DBUS3    (BIT(3))
+#define CACHE_L1_CACHE_SHUT_DBUS3_M  (CACHE_L1_CACHE_SHUT_DBUS3_V << CACHE_L1_CACHE_SHUT_DBUS3_S)
+#define CACHE_L1_CACHE_SHUT_DBUS3_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_DBUS3_S  3
+/** CACHE_L1_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L1_CACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L1_CACHE_SHUT_DMA_M  (CACHE_L1_CACHE_SHUT_DMA_V << CACHE_L1_CACHE_SHUT_DMA_S)
+#define CACHE_L1_CACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L1_CACHE_SHUT_DMA_S  4
+/** CACHE_L1_CACHE_UNDEF_OP : R/W; bitpos: [11:8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_CACHE_UNDEF_OP    0x0000000FU
+#define CACHE_L1_CACHE_UNDEF_OP_M  (CACHE_L1_CACHE_UNDEF_OP_V << CACHE_L1_CACHE_UNDEF_OP_S)
+#define CACHE_L1_CACHE_UNDEF_OP_V  0x0000000FU
+#define CACHE_L1_CACHE_UNDEF_OP_S  8
+
+/** CACHE_L1_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
+/** CACHE_BYPASS_L1_ICACHE0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
+#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
+#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
+/** CACHE_BYPASS_L1_ICACHE1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
+#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
+#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
+/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
+#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
+#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
+/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
+#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
+#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
+/** CACHE_BYPASS_L1_DCACHE_EN : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
+#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
+#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_DCACHE_EN_S  4
+
+/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
+ *  L1 Cache atomic feature configure register
+ */
+#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
+/** CACHE_L1_CACHE_ATOMIC_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
+ *  L1-Cache.  1: disable, 1: enable.
+ */
+#define CACHE_L1_CACHE_ATOMIC_EN    (BIT(0))
+#define CACHE_L1_CACHE_ATOMIC_EN_M  (CACHE_L1_CACHE_ATOMIC_EN_V << CACHE_L1_CACHE_ATOMIC_EN_S)
+#define CACHE_L1_CACHE_ATOMIC_EN_V  0x00000001U
+#define CACHE_L1_CACHE_ATOMIC_EN_S  0
+
+/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
+/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(0))
+#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1K_S  0
+/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(1))
+#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_2K_S  1
+/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(2))
+#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_4K_S  2
+/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(3))
+#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_8K_S  3
+/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(4))
+#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_16K_S  4
+/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(5))
+#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_32K_S  5
+/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(6))
+#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_64K_S  6
+/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(7))
+#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_128K_S  7
+/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(8))
+#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256K_S  8
+/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(9))
+#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512K_S  9
+/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(10))
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  10
+/** CACHE_L1_ICACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_2048K    (BIT(11))
+#define CACHE_L1_ICACHE_CACHESIZE_2048K_M  (CACHE_L1_ICACHE_CACHESIZE_2048K_V << CACHE_L1_ICACHE_CACHESIZE_2048K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_2048K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_2048K_S  11
+/** CACHE_L1_ICACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_4096K    (BIT(12))
+#define CACHE_L1_ICACHE_CACHESIZE_4096K_M  (CACHE_L1_ICACHE_CACHESIZE_4096K_V << CACHE_L1_ICACHE_CACHESIZE_4096K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_4096K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_4096K_S  12
+
+/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
+/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_CACHE_CACHESIZE_CONF_REG register
+ *  L1 data Cache CacheSize mode configure register
+ */
+#define CACHE_L1_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
+/** CACHE_L1_CACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_1K    (BIT(0))
+#define CACHE_L1_CACHE_CACHESIZE_1K_M  (CACHE_L1_CACHE_CACHESIZE_1K_V << CACHE_L1_CACHE_CACHESIZE_1K_S)
+#define CACHE_L1_CACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_1K_S  0
+/** CACHE_L1_CACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_2K    (BIT(1))
+#define CACHE_L1_CACHE_CACHESIZE_2K_M  (CACHE_L1_CACHE_CACHESIZE_2K_V << CACHE_L1_CACHE_CACHESIZE_2K_S)
+#define CACHE_L1_CACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_2K_S  1
+/** CACHE_L1_CACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_4K    (BIT(2))
+#define CACHE_L1_CACHE_CACHESIZE_4K_M  (CACHE_L1_CACHE_CACHESIZE_4K_V << CACHE_L1_CACHE_CACHESIZE_4K_S)
+#define CACHE_L1_CACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_4K_S  2
+/** CACHE_L1_CACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_8K    (BIT(3))
+#define CACHE_L1_CACHE_CACHESIZE_8K_M  (CACHE_L1_CACHE_CACHESIZE_8K_V << CACHE_L1_CACHE_CACHESIZE_8K_S)
+#define CACHE_L1_CACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_8K_S  3
+/** CACHE_L1_CACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 1;
+ *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_16K    (BIT(4))
+#define CACHE_L1_CACHE_CACHESIZE_16K_M  (CACHE_L1_CACHE_CACHESIZE_16K_V << CACHE_L1_CACHE_CACHESIZE_16K_S)
+#define CACHE_L1_CACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_16K_S  4
+/** CACHE_L1_CACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_32K    (BIT(5))
+#define CACHE_L1_CACHE_CACHESIZE_32K_M  (CACHE_L1_CACHE_CACHESIZE_32K_V << CACHE_L1_CACHE_CACHESIZE_32K_S)
+#define CACHE_L1_CACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_32K_S  5
+/** CACHE_L1_CACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_64K    (BIT(6))
+#define CACHE_L1_CACHE_CACHESIZE_64K_M  (CACHE_L1_CACHE_CACHESIZE_64K_V << CACHE_L1_CACHE_CACHESIZE_64K_S)
+#define CACHE_L1_CACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_64K_S  6
+/** CACHE_L1_CACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_128K    (BIT(7))
+#define CACHE_L1_CACHE_CACHESIZE_128K_M  (CACHE_L1_CACHE_CACHESIZE_128K_V << CACHE_L1_CACHE_CACHESIZE_128K_S)
+#define CACHE_L1_CACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_128K_S  7
+/** CACHE_L1_CACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_256K    (BIT(8))
+#define CACHE_L1_CACHE_CACHESIZE_256K_M  (CACHE_L1_CACHE_CACHESIZE_256K_V << CACHE_L1_CACHE_CACHESIZE_256K_S)
+#define CACHE_L1_CACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_256K_S  8
+/** CACHE_L1_CACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_512K    (BIT(9))
+#define CACHE_L1_CACHE_CACHESIZE_512K_M  (CACHE_L1_CACHE_CACHESIZE_512K_V << CACHE_L1_CACHE_CACHESIZE_512K_S)
+#define CACHE_L1_CACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_512K_S  9
+/** CACHE_L1_CACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_1024K    (BIT(10))
+#define CACHE_L1_CACHE_CACHESIZE_1024K_M  (CACHE_L1_CACHE_CACHESIZE_1024K_V << CACHE_L1_CACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_CACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_1024K_S  10
+/** CACHE_L1_CACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_2048K    (BIT(11))
+#define CACHE_L1_CACHE_CACHESIZE_2048K_M  (CACHE_L1_CACHE_CACHESIZE_2048K_V << CACHE_L1_CACHE_CACHESIZE_2048K_S)
+#define CACHE_L1_CACHE_CACHESIZE_2048K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_2048K_S  11
+/** CACHE_L1_CACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_CACHESIZE_4096K    (BIT(12))
+#define CACHE_L1_CACHE_CACHESIZE_4096K_M  (CACHE_L1_CACHE_CACHESIZE_4096K_V << CACHE_L1_CACHE_CACHESIZE_4096K_S)
+#define CACHE_L1_CACHE_CACHESIZE_4096K_V  0x00000001U
+#define CACHE_L1_CACHE_CACHESIZE_4096K_S  12
+
+/** CACHE_L1_CACHE_BLOCKSIZE_CONF_REG register
+ *  L1 data Cache BlockSize mode configure register
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
+/** CACHE_L1_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_CACHE_BLOCKSIZE_8_M  (CACHE_L1_CACHE_BLOCKSIZE_8_V << CACHE_L1_CACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_CACHE_BLOCKSIZE_16_M  (CACHE_L1_CACHE_BLOCKSIZE_16_V << CACHE_L1_CACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 1;
+ *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_CACHE_BLOCKSIZE_32_M  (CACHE_L1_CACHE_BLOCKSIZE_32_V << CACHE_L1_CACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_CACHE_BLOCKSIZE_64_M  (CACHE_L1_CACHE_BLOCKSIZE_64_V << CACHE_L1_CACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_CACHE_BLOCKSIZE_128_M  (CACHE_L1_CACHE_BLOCKSIZE_128_V << CACHE_L1_CACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_CACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_CACHE_BLOCKSIZE_256_M  (CACHE_L1_CACHE_BLOCKSIZE_256_V << CACHE_L1_CACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_CACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_CACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
+/** CACHE_L1_ICACHE0_WRAP : HRO; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+ */
+#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
+#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
+#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE0_WRAP_S  0
+/** CACHE_L1_ICACHE1_WRAP : HRO; bitpos: [1]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+ */
+#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
+#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
+#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE1_WRAP_S  1
+/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
+#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
+#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE2_WRAP_S  2
+/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
+#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
+#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE3_WRAP_S  3
+/** CACHE_L1_CACHE_WRAP : R/W; bitpos: [4]; default: 0;
+ *  Set this bit as 1 to enable L1-DCache wrap around mode.
+ */
+#define CACHE_L1_CACHE_WRAP    (BIT(4))
+#define CACHE_L1_CACHE_WRAP_M  (CACHE_L1_CACHE_WRAP_V << CACHE_L1_CACHE_WRAP_S)
+#define CACHE_L1_CACHE_WRAP_V  0x00000001U
+#define CACHE_L1_CACHE_WRAP_S  4
+
+/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register
+ *  Cache tag memory power control register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON : HRO; bitpos: [0]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S  1
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU : HRO; bitpos: [2]; default: 1;
+ *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU    (BIT(2))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S  2
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON : HRO; bitpos: [4]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S  5
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU : HRO; bitpos: [6]; default: 1;
+ *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU    (BIT(6))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S  6
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S  9
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU    (BIT(10))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S  10
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S  13
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU    (BIT(14))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S  14
+/** CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S  16
+/** CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+ */
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S  17
+/** CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register
+ *  Cache data memory power control register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON : HRO; bitpos: [0]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S  1
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU : HRO; bitpos: [2]; default: 1;
+ *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU    (BIT(2))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S  2
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON : HRO; bitpos: [4]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S  5
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU : HRO; bitpos: [6]; default: 1;
+ *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU    (BIT(6))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S  6
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S  9
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU    (BIT(10))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S  10
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S  13
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU    (BIT(14))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S  14
+/** CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S  16
+/** CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S  17
+/** CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S  18
+
+/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c)
+/** CACHE_L1_ICACHE0_FREEZE_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
+#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
+/** CACHE_L1_ICACHE0_FREEZE_MODE : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
+#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
+/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
+#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
+/** CACHE_L1_ICACHE1_FREEZE_EN : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
+#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
+/** CACHE_L1_ICACHE1_FREEZE_MODE : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
+#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
+/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
+#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
+/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
+#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
+/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
+#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
+/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
+#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
+/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
+#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
+/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
+#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
+/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
+#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
+/** CACHE_L1_CACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
+ *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_CACHE_FREEZE_EN    (BIT(16))
+#define CACHE_L1_CACHE_FREEZE_EN_M  (CACHE_L1_CACHE_FREEZE_EN_V << CACHE_L1_CACHE_FREEZE_EN_S)
+#define CACHE_L1_CACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_CACHE_FREEZE_EN_S  16
+/** CACHE_L1_CACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_CACHE_FREEZE_MODE    (BIT(17))
+#define CACHE_L1_CACHE_FREEZE_MODE_M  (CACHE_L1_CACHE_FREEZE_MODE_V << CACHE_L1_CACHE_FREEZE_MODE_S)
+#define CACHE_L1_CACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_CACHE_FREEZE_MODE_S  17
+/** CACHE_L1_CACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_CACHE_FREEZE_DONE    (BIT(18))
+#define CACHE_L1_CACHE_FREEZE_DONE_M  (CACHE_L1_CACHE_FREEZE_DONE_V << CACHE_L1_CACHE_FREEZE_DONE_S)
+#define CACHE_L1_CACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_CACHE_FREEZE_DONE_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
+/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : HRO; bitpos: [0]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : HRO; bitpos: [1]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : HRO; bitpos: [4]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : HRO; bitpos: [5]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
+/** CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M  (CACHE_L1_CACHE_DATA_MEM_RD_EN_V << CACHE_L1_CACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S  16
+/** CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
+ *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M  (CACHE_L1_CACHE_DATA_MEM_WR_EN_V << CACHE_L1_CACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S  17
+
+/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34)
+/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : HRO; bitpos: [0]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : HRO; bitpos: [1]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : HRO; bitpos: [4]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : HRO; bitpos: [5]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
+/** CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M  (CACHE_L1_CACHE_TAG_MEM_RD_EN_V << CACHE_L1_CACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S  16
+/** CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
+ *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M  (CACHE_L1_CACHE_TAG_MEM_WR_EN_V << CACHE_L1_CACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S  17
+
+/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x38)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE0_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 prelock.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x3c)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache0, which should be used together with
+ *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x40)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache0, which should be used together with
+ *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x44)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x48)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE1_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 prelock.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x4c)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache1, which should be used together with
+ *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x50)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache1, which should be used together with
+ *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x54)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x58)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 prelock.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x5c)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache2, which should be used together with
+ *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x60)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache2, which should be used together with
+ *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x64)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x68)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 prelock.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x6c)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache3, which should be used together with
+ *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x70)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache3, which should be used together with
+ *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x74)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_CACHE_PRELOCK_CONF_REG register
+ *  L1 Cache prelock configure register
+ */
+#define CACHE_L1_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78)
+/** CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-Cache.
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT0_EN_V << CACHE_L1_CACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-Cache.
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_CACHE_PRELOCK_SCT1_EN_V << CACHE_L1_CACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 cache prelock.
+ */
+#define CACHE_L1_CACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_CACHE_PRELOCK_RGID_M  (CACHE_L1_CACHE_PRELOCK_RGID_V << CACHE_L1_CACHE_PRELOCK_RGID_S)
+#define CACHE_L1_CACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_CACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L1 Cache prelock section0 address configure register
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
+/** CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-Cache, which should be used together with
+ *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L1 Cache prelock section1 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80)
+/** CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-Cache, which should be used together with
+ *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
+ *  L1  Cache prelock section size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84)
+/** CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_LOCK_CTRL_REG register
+ *  Lock-class (manual lock) operation control register
+ */
+#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88)
+/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+ *  operation done
+ */
+#define CACHE_LOCK_ENA    (BIT(0))
+#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
+#define CACHE_LOCK_ENA_V  0x00000001U
+#define CACHE_LOCK_ENA_S  0
+/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable unlock operation. It will be cleared by hardware after
+ *  unlock operation done
+ */
+#define CACHE_UNLOCK_ENA    (BIT(1))
+#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
+#define CACHE_UNLOCK_ENA_V  0x00000001U
+#define CACHE_UNLOCK_ENA_S  1
+/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
+ *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+ *  not finished. 1: finished.
+ */
+#define CACHE_LOCK_DONE    (BIT(2))
+#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
+#define CACHE_LOCK_DONE_V  0x00000001U
+#define CACHE_LOCK_DONE_S  2
+/** CACHE_LOCK_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of cache lock/unlock.
+ */
+#define CACHE_LOCK_RGID    0x0000000FU
+#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
+#define CACHE_LOCK_RGID_V  0x0000000FU
+#define CACHE_LOCK_RGID_S  3
+
+/** CACHE_LOCK_MAP_REG register
+ *  Lock (manual lock) map configure register
+ */
+#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c)
+/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply this lock/unlock operation. [4]: L1-Cache
+ */
+#define CACHE_LOCK_MAP    0x0000003FU
+#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
+#define CACHE_LOCK_MAP_V  0x0000003FU
+#define CACHE_LOCK_MAP_S  0
+
+/** CACHE_LOCK_ADDR_REG register
+ *  Lock (manual lock) address configure register
+ */
+#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90)
+/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the lock/unlock
+ *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+ */
+#define CACHE_LOCK_ADDR    0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
+#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_S  0
+
+/** CACHE_LOCK_SIZE_REG register
+ *  Lock (manual lock) size configure register
+ */
+#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94)
+/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the lock/unlock operation, which
+ *  should be used together with CACHE_LOCK_ADDR_REG
+ */
+#define CACHE_LOCK_SIZE    0x0000FFFFU
+#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
+#define CACHE_LOCK_SIZE_V  0x0000FFFFU
+#define CACHE_LOCK_SIZE_S  0
+
+/** CACHE_SYNC_CTRL_REG register
+ *  Sync-class operation control register
+ */
+#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98)
+/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
+ *  The bit is used to enable invalidate operation. It will be cleared by hardware
+ *  after invalidate operation done. Note that this bit and the other sync-bits
+ *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_INVALIDATE_ENA    (BIT(0))
+#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
+#define CACHE_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_INVALIDATE_ENA_S  0
+/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable clean operation. It will be cleared by hardware after
+ *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+ *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+ *  bits can not be set to 1 at the same time.
+ */
+#define CACHE_CLEAN_ENA    (BIT(1))
+#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
+#define CACHE_CLEAN_ENA_V  0x00000001U
+#define CACHE_CLEAN_ENA_S  1
+/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
+ *  The bit is used to enable writeback operation. It will be cleared by hardware after
+ *  writeback operation done. Note that this bit and the other sync-bits
+ *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_ENA    (BIT(2))
+#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
+#define CACHE_WRITEBACK_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_ENA_S  2
+/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
+ *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+ *  hardware after writeback-invalidate operation done. Note that this bit and the
+ *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+ *  that is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
+#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
+ *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+ *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+ */
+#define CACHE_SYNC_DONE    (BIT(4))
+#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
+#define CACHE_SYNC_DONE_V  0x00000001U
+#define CACHE_SYNC_DONE_S  4
+/** CACHE_SYNC_RGID : HRO; bitpos: [8:5]; default: 0;
+ *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+ *  writeback, writeback_invalidate)
+ */
+#define CACHE_SYNC_RGID    0x0000000FU
+#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
+#define CACHE_SYNC_RGID_V  0x0000000FU
+#define CACHE_SYNC_RGID_S  5
+
+/** CACHE_SYNC_MAP_REG register
+ *  Sync map configure register
+ */
+#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c)
+/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 63;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply the sync operation.  [4]: L1-Cache
+ */
+#define CACHE_SYNC_MAP    0x0000003FU
+#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
+#define CACHE_SYNC_MAP_V  0x0000003FU
+#define CACHE_SYNC_MAP_S  0
+
+/** CACHE_SYNC_ADDR_REG register
+ *  Sync address configure register
+ */
+#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0)
+/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the sync operation,
+ *  which should be used together with CACHE_SYNC_SIZE_REG
+ */
+#define CACHE_SYNC_ADDR    0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
+#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_S  0
+
+/** CACHE_SYNC_SIZE_REG register
+ *  Sync size configure register
+ */
+#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4)
+/** CACHE_SYNC_SIZE : R/W; bitpos: [23:0]; default: 0;
+ *  Those bits are used to configure the size of the sync operation, which should be
+ *  used together with CACHE_SYNC_ADDR_REG
+ */
+#define CACHE_SYNC_SIZE    0x00FFFFFFU
+#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
+#define CACHE_SYNC_SIZE_V  0x00FFFFFFU
+#define CACHE_SYNC_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa8)
+/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 preload.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xac)
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb0)
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb4)
+/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 preload.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb8)
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xbc)
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc0)
+/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 preload.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc4)
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc8)
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xcc)
+/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 preload.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd0)
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd4)
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_CACHE_PRELOAD_CTRL_REG register
+ *  L1 Cache  preload-operation control register
+ */
+#define CACHE_L1_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8)
+/** CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_CACHE_PRELOAD_ENA_M  (CACHE_L1_CACHE_PRELOAD_ENA_V << CACHE_L1_CACHE_PRELOAD_ENA_S)
+#define CACHE_L1_CACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOAD_ENA_S  0
+/** CACHE_L1_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_CACHE_PRELOAD_DONE_M  (CACHE_L1_CACHE_PRELOAD_DONE_V << CACHE_L1_CACHE_PRELOAD_DONE_S)
+#define CACHE_L1_CACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOAD_DONE_S  1
+/** CACHE_L1_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_CACHE_PRELOAD_ORDER_M  (CACHE_L1_CACHE_PRELOAD_ORDER_V << CACHE_L1_CACHE_PRELOAD_ORDER_S)
+#define CACHE_L1_CACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_CACHE_PRELOAD_ORDER_S  2
+/** CACHE_L1_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 cache preload.
+ */
+#define CACHE_L1_CACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_CACHE_PRELOAD_RGID_M  (CACHE_L1_CACHE_PRELOAD_RGID_V << CACHE_L1_CACHE_PRELOAD_RGID_S)
+#define CACHE_L1_CACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_CACHE_PRELOAD_RGID_S  3
+
+/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
+ *  L1 Cache  preload address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc)
+/** CACHE_L1_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on L1-Cache,
+ *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOAD_ADDR_M  (CACHE_L1_CACHE_PRELOAD_ADDR_V << CACHE_L1_CACHE_PRELOAD_ADDR_S)
+#define CACHE_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
+ *  L1 Cache  preload size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0)
+/** CACHE_L1_CACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_CACHE_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_CACHE_PRELOAD_SIZE_M  (CACHE_L1_CACHE_PRELOAD_SIZE_V << CACHE_L1_CACHE_PRELOAD_SIZE_S)
+#define CACHE_L1_CACHE_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_CACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 autoload.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe8)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xec)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xf0)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf8)
+/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 autoload.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xfc)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x100)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x104)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x108)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x10c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 autoload.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x110)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x114)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x118)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x11c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x120)
+/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 autoload.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x124)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x128)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x12c)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x130)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_CTRL_REG register
+ *  L1 Cache autoload-operation control register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134)
+/** CACHE_L1_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_ENA_V << CACHE_L1_CACHE_AUTOLOAD_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L1_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_M  (CACHE_L1_CACHE_AUTOLOAD_DONE_V << CACHE_L1_CACHE_AUTOLOAD_DONE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M  (CACHE_L1_CACHE_AUTOLOAD_ORDER_V << CACHE_L1_CACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
+ *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-Cache.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-Cache.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L1-Cache.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L1_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l1 cache autoload.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_CACHE_AUTOLOAD_RGID_M  (CACHE_L1_CACHE_AUTOLOAD_RGID_V << CACHE_L1_CACHE_AUTOLOAD_RGID_S)
+#define CACHE_L1_CACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_CACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 Cache autoload section 0 address configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 Cache autoload section 0 size configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x00FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0x00FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x00FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0x00FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L1 Cache autoload section 2 address configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x148)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the third section for
+ *  autoload operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L1 Cache autoload section 2 size configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x14c)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [23:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE    0x00FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V  0x00FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L1 Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x150)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the fourth section
+ *  for autoload operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L1 Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x154)
+/** CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [23:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L1-Cache. Note that it should be used together with
+ *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE    0x00FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V  0x00FFFFFFU
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158)
+/** CACHE_L1_IBUS0_OVF_INT_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
+/** CACHE_L1_BUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS0_OVF_INT_ENA    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_ENA_M  (CACHE_L1_BUS0_OVF_INT_ENA_V << CACHE_L1_BUS0_OVF_INT_ENA_S)
+#define CACHE_L1_BUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_BUS0_OVF_INT_ENA_S  4
+/** CACHE_L1_BUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS1_OVF_INT_ENA    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_ENA_M  (CACHE_L1_BUS1_OVF_INT_ENA_V << CACHE_L1_BUS1_OVF_INT_ENA_S)
+#define CACHE_L1_BUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_BUS1_OVF_INT_ENA_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c)
+/** CACHE_L1_IBUS0_OVF_INT_CLR : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+ *  to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
+/** CACHE_L1_IBUS1_OVF_INT_CLR : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+ *  to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
+/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
+/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
+/** CACHE_L1_BUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS0_OVF_INT_CLR    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_CLR_M  (CACHE_L1_BUS0_OVF_INT_CLR_V << CACHE_L1_BUS0_OVF_INT_CLR_S)
+#define CACHE_L1_BUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_BUS0_OVF_INT_CLR_S  4
+/** CACHE_L1_BUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS1_OVF_INT_CLR    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_CLR_M  (CACHE_L1_BUS1_OVF_INT_CLR_V << CACHE_L1_BUS1_OVF_INT_CLR_S)
+#define CACHE_L1_BUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_BUS1_OVF_INT_CLR_S  5
+/** CACHE_L1_DBUS2_OVF_INT_CLR : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
+/** CACHE_L1_DBUS3_OVF_INT_CLR : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160)
+/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+ *  due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
+/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+ *  due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
+/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+ *  due to bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
+/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+ *  due to bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
+/** CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS0_OVF_INT_RAW    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_RAW_M  (CACHE_L1_BUS0_OVF_INT_RAW_V << CACHE_L1_BUS0_OVF_INT_RAW_S)
+#define CACHE_L1_BUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_BUS0_OVF_INT_RAW_S  4
+/** CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS1_OVF_INT_RAW    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_RAW_M  (CACHE_L1_BUS1_OVF_INT_RAW_V << CACHE_L1_BUS1_OVF_INT_RAW_S)
+#define CACHE_L1_BUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_BUS1_OVF_INT_RAW_S  5
+/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
+/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164)
+/** CACHE_L1_IBUS0_OVF_INT_ST : HRO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
+#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ST : HRO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
+#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
+#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
+#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
+/** CACHE_L1_BUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS0_OVF_INT_ST    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_ST_M  (CACHE_L1_BUS0_OVF_INT_ST_V << CACHE_L1_BUS0_OVF_INT_ST_S)
+#define CACHE_L1_BUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_BUS0_OVF_INT_ST_S  4
+/** CACHE_L1_BUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_BUS1_OVF_INT_ST    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_ST_M  (CACHE_L1_BUS1_OVF_INT_ST_V << CACHE_L1_BUS1_OVF_INT_ST_S)
+#define CACHE_L1_BUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_BUS1_OVF_INT_ST_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ST : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
+#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ST : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
+#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x168)
+/** CACHE_L1_ICACHE0_FAIL_INT_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
+/** CACHE_L1_CACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_CACHE_FAIL_INT_ENA    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_ENA_M  (CACHE_L1_CACHE_FAIL_INT_ENA_V << CACHE_L1_CACHE_FAIL_INT_ENA_S)
+#define CACHE_L1_CACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_FAIL_INT_ENA_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x16c)
+/** CACHE_L1_ICACHE0_FAIL_INT_CLR : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_CLR : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
+/** CACHE_L1_CACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_CACHE_FAIL_INT_CLR    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_CLR_M  (CACHE_L1_CACHE_FAIL_INT_CLR_V << CACHE_L1_CACHE_FAIL_INT_CLR_S)
+#define CACHE_L1_CACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_FAIL_INT_CLR_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x170)
+/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
+/** CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+ */
+#define CACHE_L1_CACHE_FAIL_INT_RAW    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_RAW_M  (CACHE_L1_CACHE_FAIL_INT_RAW_V << CACHE_L1_CACHE_FAIL_INT_RAW_S)
+#define CACHE_L1_CACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_CACHE_FAIL_INT_RAW_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x174)
+/** CACHE_L1_ICACHE0_FAIL_INT_ST : HRO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ST : HRO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
+/** CACHE_L1_CACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+ *  to cpu accesses L1-DCache.
+ */
+#define CACHE_L1_CACHE_FAIL_INT_ST    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_ST_M  (CACHE_L1_CACHE_FAIL_INT_ST_V << CACHE_L1_CACHE_FAIL_INT_ST_S)
+#define CACHE_L1_CACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_CACHE_FAIL_INT_ST_S  4
+
+/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x178)
+/** CACHE_L1_IBUS0_CNT_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
+#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_ENA_S  0
+/** CACHE_L1_IBUS1_CNT_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
+#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_ENA_S  1
+/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
+#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_ENA_S  2
+/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
+#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_ENA_S  3
+/** CACHE_L1_BUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_BUS0_CNT_ENA    (BIT(4))
+#define CACHE_L1_BUS0_CNT_ENA_M  (CACHE_L1_BUS0_CNT_ENA_V << CACHE_L1_BUS0_CNT_ENA_S)
+#define CACHE_L1_BUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_BUS0_CNT_ENA_S  4
+/** CACHE_L1_BUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_BUS1_CNT_ENA    (BIT(5))
+#define CACHE_L1_BUS1_CNT_ENA_M  (CACHE_L1_BUS1_CNT_ENA_V << CACHE_L1_BUS1_CNT_ENA_S)
+#define CACHE_L1_BUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_BUS1_CNT_ENA_S  5
+/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
+#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_ENA_S  6
+/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
+#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_ENA_S  7
+/** CACHE_L1_IBUS0_CNT_CLR : HRO; bitpos: [16]; default: 0;
+ *  The bit is used to clear ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
+#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
+#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_CLR_S  16
+/** CACHE_L1_IBUS1_CNT_CLR : HRO; bitpos: [17]; default: 0;
+ *  The bit is used to clear ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
+#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
+#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_CLR_S  17
+/** CACHE_L1_IBUS2_CNT_CLR : HRO; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
+#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
+#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_CLR_S  18
+/** CACHE_L1_IBUS3_CNT_CLR : HRO; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
+#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
+#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_CLR_S  19
+/** CACHE_L1_BUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
+ *  The bit is used to clear dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_BUS0_CNT_CLR    (BIT(20))
+#define CACHE_L1_BUS0_CNT_CLR_M  (CACHE_L1_BUS0_CNT_CLR_V << CACHE_L1_BUS0_CNT_CLR_S)
+#define CACHE_L1_BUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_BUS0_CNT_CLR_S  20
+/** CACHE_L1_BUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
+ *  The bit is used to clear dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_BUS1_CNT_CLR    (BIT(21))
+#define CACHE_L1_BUS1_CNT_CLR_M  (CACHE_L1_BUS1_CNT_CLR_V << CACHE_L1_BUS1_CNT_CLR_S)
+#define CACHE_L1_BUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_BUS1_CNT_CLR_S  21
+/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
+#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
+#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_CLR_S  22
+/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
+#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
+#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_CLR_S  23
+
+/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x17c)
+/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
+#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x180)
+/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
+#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x184)
+/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_NXTLVL_CNT_REG register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x188)
+/** CACHE_L1_IBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_CNT_M  (CACHE_L1_IBUS0_NXTLVL_CNT_V << CACHE_L1_IBUS0_NXTLVL_CNT_S)
+#define CACHE_L1_IBUS0_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
+/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
+#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x190)
+/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
+#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x194)
+/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_NXTLVL_CNT_REG register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x198)
+/** CACHE_L1_IBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_CNT_M  (CACHE_L1_IBUS1_NXTLVL_CNT_V << CACHE_L1_IBUS1_NXTLVL_CNT_S)
+#define CACHE_L1_IBUS1_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
+/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
+#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
+/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
+#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
+/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_NXTLVL_CNT_REG register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
+/** CACHE_L1_IBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_CNT_M  (CACHE_L1_IBUS2_NXTLVL_CNT_V << CACHE_L1_IBUS2_NXTLVL_CNT_S)
+#define CACHE_L1_IBUS2_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
+/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
+#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
+/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
+#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
+/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_NXTLVL_CNT_REG register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
+/** CACHE_L1_IBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_CNT_M  (CACHE_L1_IBUS3_NXTLVL_CNT_V << CACHE_L1_IBUS3_NXTLVL_CNT_S)
+#define CACHE_L1_IBUS3_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_CNT_S  0
+
+/** CACHE_L1_BUS0_ACS_HIT_CNT_REG register
+ *  L1-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_BUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
+/** CACHE_L1_BUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_HIT_CNT_M  (CACHE_L1_BUS0_HIT_CNT_V << CACHE_L1_BUS0_HIT_CNT_S)
+#define CACHE_L1_BUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_HIT_CNT_S  0
+
+/** CACHE_L1_BUS0_ACS_MISS_CNT_REG register
+ *  L1-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_BUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
+/** CACHE_L1_BUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_MISS_CNT_M  (CACHE_L1_BUS0_MISS_CNT_V << CACHE_L1_BUS0_MISS_CNT_S)
+#define CACHE_L1_BUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_MISS_CNT_S  0
+
+/** CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
+/** CACHE_L1_BUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_CONFLICT_CNT_M  (CACHE_L1_BUS0_CONFLICT_CNT_V << CACHE_L1_BUS0_CONFLICT_CNT_S)
+#define CACHE_L1_BUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG register
+ *  L1-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
+/** CACHE_L1_BUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-Cache accesses L2-Cache due to
+ *  bus0 accessing L1-Cache.
+ */
+#define CACHE_L1_BUS0_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS0_NXTLVL_CNT_M  (CACHE_L1_BUS0_NXTLVL_CNT_V << CACHE_L1_BUS0_NXTLVL_CNT_S)
+#define CACHE_L1_BUS0_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS0_NXTLVL_CNT_S  0
+
+/** CACHE_L1_BUS1_ACS_HIT_CNT_REG register
+ *  L1-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_BUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
+/** CACHE_L1_BUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS1_HIT_CNT_M  (CACHE_L1_BUS1_HIT_CNT_V << CACHE_L1_BUS1_HIT_CNT_S)
+#define CACHE_L1_BUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS1_HIT_CNT_S  0
+
+/** CACHE_L1_BUS1_ACS_MISS_CNT_REG register
+ *  L1-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_BUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
+/** CACHE_L1_BUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS1_MISS_CNT_M  (CACHE_L1_BUS1_MISS_CNT_V << CACHE_L1_BUS1_MISS_CNT_S)
+#define CACHE_L1_BUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS1_MISS_CNT_S  0
+
+/** CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
+/** CACHE_L1_BUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
+ */
+#define CACHE_L1_BUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS1_CONFLICT_CNT_M  (CACHE_L1_BUS1_CONFLICT_CNT_V << CACHE_L1_BUS1_CONFLICT_CNT_S)
+#define CACHE_L1_BUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG register
+ *  L1-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
+/** CACHE_L1_BUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-Cache accesses L2-Cache due to
+ *  bus1 accessing L1-Cache.
+ */
+#define CACHE_L1_BUS1_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L1_BUS1_NXTLVL_CNT_M  (CACHE_L1_BUS1_NXTLVL_CNT_V << CACHE_L1_BUS1_NXTLVL_CNT_S)
+#define CACHE_L1_BUS1_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_BUS1_NXTLVL_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
+/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
+#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
+/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
+#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
+/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_CNT_REG register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
+/** CACHE_L1_DBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_CNT_M  (CACHE_L1_DBUS2_NXTLVL_CNT_V << CACHE_L1_DBUS2_NXTLVL_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
+/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
+#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
+/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
+#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
+/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_CNT_REG register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
+/** CACHE_L1_DBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_CNT_M  (CACHE_L1_DBUS3_NXTLVL_CNT_V << CACHE_L1_DBUS3_NXTLVL_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_CNT_S  0
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x1fc)
+/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
+#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_S  0
+/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x200)
+/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x204)
+/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
+#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_S  0
+/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x208)
+/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x20c)
+/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
+#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_S  0
+/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x210)
+/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214)
+/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
+#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_S  0
+/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218)
+/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
+
+/** CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L1-Cache Access Fail ID/attribution information register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c)
+/** CACHE_L1_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache accesses L1-Cache.
+ */
+#define CACHE_L1_CACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_CACHE_FAIL_ID_M  (CACHE_L1_CACHE_FAIL_ID_V << CACHE_L1_CACHE_FAIL_ID_S)
+#define CACHE_L1_CACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_CACHE_FAIL_ID_S  0
+/** CACHE_L1_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache accesses L1-Cache.
+ */
+#define CACHE_L1_CACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_CACHE_FAIL_ATTR_M  (CACHE_L1_CACHE_FAIL_ATTR_V << CACHE_L1_CACHE_FAIL_ATTR_S)
+#define CACHE_L1_CACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_CACHE_FAIL_ATTR_S  16
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
+ *  L1-Cache Access Fail Address information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220)
+/** CACHE_L1_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache accesses L1-Cache.
+ */
+#define CACHE_L1_CACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_FAIL_ADDR_M  (CACHE_L1_CACHE_FAIL_ADDR_V << CACHE_L1_CACHE_FAIL_ADDR_S)
+#define CACHE_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_FAIL_ADDR_S  0
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x224)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
+/** CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_CACHE_PLD_DONE_INT_ENA_V << CACHE_L1_CACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S  4
+/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation done.
+ */
+#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
+#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ENA_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : HRO; bitpos: [7]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
+/** CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable interrupt of L1-Cache preload-operation error.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_CACHE_PLD_ERR_INT_ENA_V << CACHE_L1_CACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S  11
+/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
+#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ENA_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x228)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
+/** CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
+ *  is done.
+ */
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_CACHE_PLD_DONE_INT_CLR_V << CACHE_L1_CACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S  4
+/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ *  done.
+ */
+#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
+#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_CLR_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : HRO; bitpos: [7]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
+/** CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The bit is used to clear interrupt of L1-Cache preload-operation error.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_CACHE_PLD_ERR_INT_CLR_V << CACHE_L1_CACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S  11
+/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
+#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_CLR_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x22c)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
+/** CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+ *  done.
+ */
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_CACHE_PLD_DONE_INT_RAW_V << CACHE_L1_CACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S  4
+/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
+#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_RAW_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
+/** CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
+ *  occurs.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_CACHE_PLD_ERR_INT_RAW_V << CACHE_L1_CACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S  11
+/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+ *  occurs.
+ */
+#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
+#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_RAW_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x230)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : HRO; bitpos: [0]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : HRO; bitpos: [1]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
+/** CACHE_L1_CACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-Cache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M  (CACHE_L1_CACHE_PLD_DONE_INT_ST_V << CACHE_L1_CACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S  4
+/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when Cache
+ *  sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
+#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ST_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : HRO; bitpos: [7]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : HRO; bitpos: [8]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
+/** CACHE_L1_CACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M  (CACHE_L1_CACHE_PLD_ERR_INT_ST_V << CACHE_L1_CACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S  11
+/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the status of the interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
+#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ST_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x234)
+/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
+/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
+/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
+/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
+/** CACHE_L1_CACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-Cache.
+ */
+#define CACHE_L1_CACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_CACHE_PLD_ERR_CODE_M  (CACHE_L1_CACHE_PLD_ERR_CODE_V << CACHE_L1_CACHE_PLD_ERR_CODE_S)
+#define CACHE_L1_CACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_CACHE_PLD_ERR_CODE_S  8
+/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
+ *  The values 0-2 are available which means sync map, command conflict and size are
+ *  error in Cache System.
+ */
+#define CACHE_SYNC_ERR_CODE    0x00000003U
+#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
+#define CACHE_SYNC_ERR_CODE_V  0x00000003U
+#define CACHE_SYNC_ERR_CODE_S  12
+
+/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x238)
+/** CACHE_L1_ICACHE0_SYNC_RST : HRO; bitpos: [0]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
+#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_SYNC_RST_S  0
+/** CACHE_L1_ICACHE1_SYNC_RST : HRO; bitpos: [1]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
+#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_SYNC_RST_S  1
+/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
+#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_SYNC_RST_S  2
+/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
+#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_SYNC_RST_S  3
+/** CACHE_L1_CACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_CACHE_SYNC_RST    (BIT(4))
+#define CACHE_L1_CACHE_SYNC_RST_M  (CACHE_L1_CACHE_SYNC_RST_V << CACHE_L1_CACHE_SYNC_RST_S)
+#define CACHE_L1_CACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L1_CACHE_SYNC_RST_S  4
+
+/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x23c)
+/** CACHE_L1_ICACHE0_PLD_RST : HRO; bitpos: [0]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
+#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_RST_S  0
+/** CACHE_L1_ICACHE1_PLD_RST : HRO; bitpos: [1]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
+#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_RST_S  1
+/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
+#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_RST_S  2
+/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
+#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_RST_S  3
+/** CACHE_L1_CACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_CACHE_PLD_RST    (BIT(4))
+#define CACHE_L1_CACHE_PLD_RST_M  (CACHE_L1_CACHE_PLD_RST_V << CACHE_L1_CACHE_PLD_RST_S)
+#define CACHE_L1_CACHE_PLD_RST_V  0x00000001U
+#define CACHE_L1_CACHE_PLD_RST_S  4
+
+/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x240)
+/** CACHE_L1_ICACHE0_ALD_BUF_CLR : HRO; bitpos: [0]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+ *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+ *  works in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
+/** CACHE_L1_ICACHE1_ALD_BUF_CLR : HRO; bitpos: [1]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+ *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+ *  works in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
+/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
+/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
+/** CACHE_L1_CACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
+ *  autoload will not work in L1-Cache. This bit should not be active when autoload
+ *  works in L1-Cache.
+ */
+#define CACHE_L1_CACHE_ALD_BUF_CLR    (BIT(4))
+#define CACHE_L1_CACHE_ALD_BUF_CLR_M  (CACHE_L1_CACHE_ALD_BUF_CLR_V << CACHE_L1_CACHE_ALD_BUF_CLR_S)
+#define CACHE_L1_CACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_ALD_BUF_CLR_S  4
+
+/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x244)
+/** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
+/** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
+/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
+/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
+/** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 cache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
+#define CACHE_L1_CACHE_UNALLOC_CLR_M  (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S)
+#define CACHE_L1_CACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_CACHE_UNALLOC_CLR_S  4
+
+/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x248)
+/** CACHE_L1_ICACHE0_TAG_OBJECT : HRO; bitpos: [0]; default: 0;
+ *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
+/** CACHE_L1_ICACHE1_TAG_OBJECT : HRO; bitpos: [1]; default: 0;
+ *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
+#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
+/** CACHE_L1_ICACHE2_TAG_OBJECT : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
+#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
+/** CACHE_L1_ICACHE3_TAG_OBJECT : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
+#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
+/** CACHE_L1_CACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_CACHE_TAG_OBJECT    (BIT(4))
+#define CACHE_L1_CACHE_TAG_OBJECT_M  (CACHE_L1_CACHE_TAG_OBJECT_V << CACHE_L1_CACHE_TAG_OBJECT_S)
+#define CACHE_L1_CACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_CACHE_TAG_OBJECT_S  4
+/** CACHE_L1_ICACHE0_MEM_OBJECT : HRO; bitpos: [6]; default: 0;
+ *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
+#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
+/** CACHE_L1_ICACHE1_MEM_OBJECT : HRO; bitpos: [7]; default: 0;
+ *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
+#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
+/** CACHE_L1_ICACHE2_MEM_OBJECT : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
+#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
+/** CACHE_L1_ICACHE3_MEM_OBJECT : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
+#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
+/** CACHE_L1_CACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_CACHE_MEM_OBJECT    (BIT(10))
+#define CACHE_L1_CACHE_MEM_OBJECT_M  (CACHE_L1_CACHE_MEM_OBJECT_V << CACHE_L1_CACHE_MEM_OBJECT_S)
+#define CACHE_L1_CACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_CACHE_MEM_OBJECT_S  10
+
+/** CACHE_L1_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x24c)
+/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
+#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L1_CACHE_VADDR_REG register
+ *  Cache Vaddr register
+ */
+#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x250)
+/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the virtual address which will decide where inside the specified
+ *  tag memory object will be accessed.
+ */
+#define CACHE_L1_CACHE_VADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_VADDR_M  (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S)
+#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_VADDR_S  0
+
+/** CACHE_L1_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x254)
+/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 596;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
+#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_LEVEL_SPLIT0_REG register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x258)
+/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 600;
+ *  Reserved
+ */
+#define CACHE_LEVEL_SPLIT0    0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT0_M  (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S)
+#define CACHE_LEVEL_SPLIT0_V  0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT0_S  0
+
+/** CACHE_L2_CACHE_CTRL_REG register
+ *  L2 Cache(L2-Cache) control register
+ */
+#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x25c)
+/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 0;
+ *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
+#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L2_CACHE_SHUT_DMA_S  4
+/** CACHE_L2_CACHE_UNDEF_OP : HRO; bitpos: [8:5]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_CACHE_UNDEF_OP    0x0000000FU
+#define CACHE_L2_CACHE_UNDEF_OP_M  (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S)
+#define CACHE_L2_CACHE_UNDEF_OP_V  0x0000000FU
+#define CACHE_L2_CACHE_UNDEF_OP_S  5
+
+/** CACHE_L2_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x260)
+/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
+#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
+#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L2_CACHE_EN_S  5
+
+/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
+ *  L2 Cache CacheSize mode configure register
+ */
+#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x264)
+/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(0))
+#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1K_S  0
+/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(1))
+#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
+#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_2K_S  1
+/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(2))
+#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
+#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_4K_S  2
+/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(3))
+#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
+#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_8K_S  3
+/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(4))
+#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
+#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_16K_S  4
+/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(5))
+#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
+#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_32K_S  5
+/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(6))
+#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
+#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_64K_S  6
+/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(7))
+#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
+#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_128K_S  7
+/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(8))
+#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
+#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256K_S  8
+/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(9))
+#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
+#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512K_S  9
+/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(10))
+#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1024K_S  10
+/** CACHE_L2_CACHE_CACHESIZE_2048K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_2048K    (BIT(11))
+#define CACHE_L2_CACHE_CACHESIZE_2048K_M  (CACHE_L2_CACHE_CACHESIZE_2048K_V << CACHE_L2_CACHE_CACHESIZE_2048K_S)
+#define CACHE_L2_CACHE_CACHESIZE_2048K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_2048K_S  11
+/** CACHE_L2_CACHE_CACHESIZE_4096K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_4096K    (BIT(12))
+#define CACHE_L2_CACHE_CACHESIZE_4096K_M  (CACHE_L2_CACHE_CACHESIZE_4096K_V << CACHE_L2_CACHE_CACHESIZE_4096K_S)
+#define CACHE_L2_CACHE_CACHESIZE_4096K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_4096K_S  12
+
+/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
+ *  L2 Cache BlockSize mode configure register
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x268)
+/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
+/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
+/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
+/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
+/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
+/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x26c)
+/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0;
+ *  Set this bit as 1 to enable L2-Cache wrap around mode.
+ */
+#define CACHE_L2_CACHE_WRAP    (BIT(5))
+#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
+#define CACHE_L2_CACHE_WRAP_V  0x00000001U
+#define CACHE_L2_CACHE_WRAP_S  5
+
+/** CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG register
+ *  Cache tag memory power control register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x270)
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_ON : HRO; bitpos: [20]; default: 0;
+ *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S  20
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_PD : HRO; bitpos: [21]; default: 0;
+ *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S  21
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_PU : HRO; bitpos: [22]; default: 0;
+ *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU    (BIT(22))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG register
+ *  Cache data memory power control register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x274)
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_ON : HRO; bitpos: [20]; default: 0;
+ *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S  20
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_PD : HRO; bitpos: [21]; default: 0;
+ *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S  21
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_PU : HRO; bitpos: [22]; default: 0;
+ *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU    (BIT(22))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S  22
+
+/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x278)
+/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0;
+ *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
+#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
+#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_EN_S  20
+/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0;
+ *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
+#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
+#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_MODE_S  21
+/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
+#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
+#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_DONE_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x27c)
+/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 0;
+ *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 0;
+ *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x280)
+/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 0;
+ *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 0;
+ *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
+ *  L2 Cache prelock configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x284)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l2 cache prelock.
+ */
+#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
+#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L2 Cache prelock section0 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x288)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L2-Cache, which should be used together with
+ *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L2 Cache prelock section1 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x28c)
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L2-Cache, which should be used together with
+ *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
+ *  L2 Cache prelock section size configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x290)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
+ *  L2 Cache preload-operation control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x294)
+/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
+#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
+/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
+#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
+/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
+#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
+/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l2 cache preload.
+ */
+#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
+#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
+
+/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
+ *  L2 Cache preload address configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x298)
+/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+ *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
+#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
+ *  L2 Cache preload size configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x29c)
+/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
+#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
+ *  L2 Cache autoload-operation control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a0)
+/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+ *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l2 cache autoload.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L2 Cache autoload section 0 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2a4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L2 Cache autoload section 0 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2a8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L2 Cache autoload section 1 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2ac)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L2 Cache autoload section 1 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2b0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L2 Cache autoload section 2 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2b4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the third section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L2 Cache autoload section 2 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2b8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L2 Cache autoload section 3 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2bc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the fourth section
+ *  for autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L2 Cache autoload section 3 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2c0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2c4)
+/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2c8)
+/** CACHE_L2_IBUS0_OVF_INT_CLR : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
+/** CACHE_L2_IBUS1_OVF_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
+/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
+/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
+/** CACHE_L2_DBUS0_OVF_INT_CLR : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
+/** CACHE_L2_DBUS1_OVF_INT_CLR : HRO; bitpos: [13]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
+/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
+/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2cc)
+/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-ICache0.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
+/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-ICache1.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
+/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-ICache2.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
+/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-ICache3.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
+/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
+/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
+/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
+/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2d0)
+/** CACHE_L2_IBUS0_OVF_INT_ST : HRO; bitpos: [8]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
+#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ST : HRO; bitpos: [9]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
+#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
+#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
+#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ST : HRO; bitpos: [12]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
+#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ST : HRO; bitpos: [13]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
+#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
+#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
+#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d4)
+/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+ *  l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
+#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2d8)
+/** CACHE_L2_CACHE_FAIL_INT_CLR : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+ *  cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
+#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2dc)
+/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
+#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2e0)
+/** CACHE_L2_CACHE_FAIL_INT_ST : HRO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+ *  to l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
+#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
+
+/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2e4)
+/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
+#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_ENA_S  8
+/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
+#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_ENA_S  9
+/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
+#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_ENA_S  10
+/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
+#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_ENA_S  11
+/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to enable dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
+#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_ENA_S  12
+/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0;
+ *  The bit is used to enable dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
+#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_ENA_S  13
+/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
+#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_ENA_S  14
+/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
+#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_ENA_S  15
+/** CACHE_L2_IBUS0_CNT_CLR : HRO; bitpos: [24]; default: 0;
+ *  The bit is used to clear ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
+#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
+#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_CLR_S  24
+/** CACHE_L2_IBUS1_CNT_CLR : HRO; bitpos: [25]; default: 0;
+ *  The bit is used to clear ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
+#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
+#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_CLR_S  25
+/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
+#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
+#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_CLR_S  26
+/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
+#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
+#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_CLR_S  27
+/** CACHE_L2_DBUS0_CNT_CLR : HRO; bitpos: [28]; default: 0;
+ *  The bit is used to clear dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
+#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
+#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_CLR_S  28
+/** CACHE_L2_DBUS1_CNT_CLR : HRO; bitpos: [29]; default: 0;
+ *  The bit is used to clear dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
+#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
+#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_CLR_S  29
+/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
+#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
+#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_CLR_S  30
+/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
+#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
+#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_CLR_S  31
+
+/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2e8)
+/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
+#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2ec)
+/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
+#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x2f0)
+/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache0 accesses
+ *  L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_NXTLVL_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x2f4)
+/** CACHE_L2_IBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_CNT_M  (CACHE_L2_IBUS0_NXTLVL_CNT_V << CACHE_L2_IBUS0_NXTLVL_CNT_S)
+#define CACHE_L2_IBUS0_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x2f8)
+/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
+#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x2fc)
+/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
+#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
+/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache1 accesses
+ *  L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_NXTLVL_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x304)
+/** CACHE_L2_IBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_CNT_M  (CACHE_L2_IBUS1_NXTLVL_CNT_V << CACHE_L2_IBUS1_NXTLVL_CNT_S)
+#define CACHE_L2_IBUS1_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
+/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
+#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
+/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
+#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
+/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache2 accesses
+ *  L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_NXTLVL_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x314)
+/** CACHE_L2_IBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_CNT_M  (CACHE_L2_IBUS2_NXTLVL_CNT_V << CACHE_L2_IBUS2_NXTLVL_CNT_S)
+#define CACHE_L2_IBUS2_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
+/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
+#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
+/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
+#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
+/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache3 accesses
+ *  L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_NXTLVL_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x324)
+/** CACHE_L2_IBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_CNT_M  (CACHE_L2_IBUS3_NXTLVL_CNT_V << CACHE_L2_IBUS3_NXTLVL_CNT_S)
+#define CACHE_L2_IBUS3_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
+/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
+#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
+/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
+#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
+/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x334)
+/** CACHE_L2_DBUS0_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_CNT_M  (CACHE_L2_DBUS0_NXTLVL_CNT_V << CACHE_L2_DBUS0_NXTLVL_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
+/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
+#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
+/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
+#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
+/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x344)
+/** CACHE_L2_DBUS1_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_CNT_M  (CACHE_L2_DBUS1_NXTLVL_CNT_V << CACHE_L2_DBUS1_NXTLVL_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x348)
+/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
+#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
+/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
+#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x350)
+/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x354)
+/** CACHE_L2_DBUS2_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_CNT_M  (CACHE_L2_DBUS2_NXTLVL_CNT_V << CACHE_L2_DBUS2_NXTLVL_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x358)
+/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
+#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
+/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
+#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x360)
+/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_CNT_REG (DR_REG_CACHE_BASE + 0x364)
+/** CACHE_L2_DBUS3_NXTLVL_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_CNT_M  (CACHE_L2_DBUS3_NXTLVL_CNT_V << CACHE_L2_DBUS3_NXTLVL_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_CNT_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x368)
+/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
+#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_S  0
+/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+ *  due to cache accessing L1-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
+#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_S  16
+
+/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
+ *  L2-Cache Access Fail Address information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x36c)
+/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
+#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_S  0
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x370)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x374)
+/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+ *  is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : HRO; bitpos: [12]; default: 0;
+ *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x378)
+/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+ *  done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x37c)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ST : HRO; bitpos: [5]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+ *  preload-operation is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ST : HRO; bitpos: [12]; default: 0;
+ *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x380)
+/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L2-Cache.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
+#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
+
+/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x384)
+/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0;
+ *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
+#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
+#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L2_CACHE_SYNC_RST_S  5
+
+/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x388)
+/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0;
+ *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
+#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_RST_S  5
+
+/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x38c)
+/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0;
+ *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+ *  autoload will not work in L2-Cache. This bit should not be active when autoload
+ *  works in L2-Cache.
+ */
+#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
+#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
+#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
+
+/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x390)
+/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l2 icache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
+#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
+#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
+
+/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
+ *  L1 Cache access Attribute propagation control register
+ */
+#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x394)
+/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1;
+ *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+ *  non-cacheable.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
+/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+ *  write-through.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
+/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  write-miss-allocate and write-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
+/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1;
+ *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  read-miss-allocate and read-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
+
+/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x398)
+/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0;
+ *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
+#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
+#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_OBJECT_S  5
+/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0;
+ *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
+#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
+#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_MEM_OBJECT_S  11
+
+/** CACHE_L2_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x39c)
+/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
+#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L2_CACHE_VADDR_REG register
+ *  Cache Vaddr register
+ */
+#define CACHE_L2_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x3a0)
+/** CACHE_L2_CACHE_VADDR : HRO; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the virtual address which will decide where inside the specified
+ *  tag memory object will be accessed.
+ */
+#define CACHE_L2_CACHE_VADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_VADDR_M  (CACHE_L2_CACHE_VADDR_V << CACHE_L2_CACHE_VADDR_S)
+#define CACHE_L2_CACHE_VADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_VADDR_S  0
+
+/** CACHE_L2_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3a4)
+/** CACHE_L2_CACHE_DEBUG_BUS : HRO; bitpos: [31:0]; default: 932;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
+#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_LEVEL_SPLIT1_REG register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3a8)
+/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 936;
+ *  Reserved
+ */
+#define CACHE_LEVEL_SPLIT1    0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT1_M  (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S)
+#define CACHE_LEVEL_SPLIT1_V  0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT1_S  0
+
+/** CACHE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3ac)
+/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define CACHE_CLK_EN    (BIT(0))
+#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
+#define CACHE_CLK_EN_V  0x00000001U
+#define CACHE_CLK_EN_S  0
+
+/** CACHE_REDUNDANCY_SIG0_REG register
+ *  Cache redundancy signal 0 register
+ */
+#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3b0)
+/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG0    0xFFFFFFFFU
+#define CACHE_REDCY_SIG0_M  (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S)
+#define CACHE_REDCY_SIG0_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG0_S  0
+
+/** CACHE_REDUNDANCY_SIG1_REG register
+ *  Cache redundancy signal 1 register
+ */
+#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3b4)
+/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG1    0xFFFFFFFFU
+#define CACHE_REDCY_SIG1_M  (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S)
+#define CACHE_REDCY_SIG1_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG1_S  0
+
+/** CACHE_REDUNDANCY_SIG2_REG register
+ *  Cache redundancy signal 2 register
+ */
+#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3b8)
+/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG2    0xFFFFFFFFU
+#define CACHE_REDCY_SIG2_M  (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S)
+#define CACHE_REDCY_SIG2_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG2_S  0
+
+/** CACHE_REDUNDANCY_SIG3_REG register
+ *  Cache redundancy signal 3 register
+ */
+#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3bc)
+/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG3    0xFFFFFFFFU
+#define CACHE_REDCY_SIG3_M  (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S)
+#define CACHE_REDCY_SIG3_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG3_S  0
+
+/** CACHE_REDUNDANCY_SIG4_REG register
+ *  Cache redundancy signal 0 register
+ */
+#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3c0)
+/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ */
+#define CACHE_REDCY_SIG4    0x0000000FU
+#define CACHE_REDCY_SIG4_M  (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S)
+#define CACHE_REDCY_SIG4_V  0x0000000FU
+#define CACHE_REDCY_SIG4_S  0
+
+/** CACHE_DATE_REG register
+ *  Version control register
+ */
+#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
+/** CACHE_DATE : R/W; bitpos: [27:0]; default: 35680848;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define CACHE_DATE    0x0FFFFFFFU
+#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
+#define CACHE_DATE_V  0x0FFFFFFFU
+#define CACHE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/cache_struct.h b/components/soc/esp32h2/register/soc/cache_struct.h
new file mode 100644
index 00000000000..32ec8a069c7
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/cache_struct.h
@@ -0,0 +1,5747 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of l1_icache_ctrl register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+typedef union {
+    struct {
+        /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus0:1;
+        /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus1:1;
+        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus2:1;
+        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus3:1;
+        /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_undef_op:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache_ctrl_reg_t;
+
+/** Type of l1_cache_ctrl register
+ *  L1 data Cache(L1-Cache) control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus0:1;
+        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus1:1;
+        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus2:1;
+        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus3:1;
+        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_dma:1;
+        uint32_t reserved_5:3;
+        /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_undef_op:4;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l1_cache_ctrl_reg_t;
+
+/** Type of l2_cache_ctrl register
+ *  L2 Cache(L2-Cache) control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+         */
+        uint32_t l2_cache_shut_dma:1;
+        /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_cache_undef_op:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} cache_l2_cache_ctrl_reg_t;
+
+
+/** Group: Bypass Cache Control and configuration registers */
+/** Type of l1_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache0_en:1;
+        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache1_en:1;
+        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache2_en:1;
+        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache3_en:1;
+        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_dcache_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_bypass_cache_conf_reg_t;
+
+/** Type of l2_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l2_cache_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_bypass_cache_conf_reg_t;
+
+
+/** Group: Cache Atomic Control and configuration registers */
+/** Type of l1_cache_atomic_conf register
+ *  L1 Cache atomic feature configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
+         *  L1-Cache.  1: disable, 1: enable.
+         */
+        uint32_t l1_cache_atomic_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l1_cache_atomic_conf_reg_t;
+
+
+/** Group: Cache Mode Control and configuration registers */
+/** Type of l1_icache_cachesize_conf register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1k:1;
+        /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2k:1;
+        /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4k:1;
+        /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_8k:1;
+        /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_16k:1;
+        /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_32k:1;
+        /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_64k:1;
+        /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_128k:1;
+        /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256k:1;
+        /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512k:1;
+        /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1024k:1;
+        /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2048k:1;
+        /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_icache_cachesize_conf_reg_t;
+
+/** Type of l1_icache_blocksize_conf register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_8:1;
+        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_16:1;
+        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_32:1;
+        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_64:1;
+        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_128:1;
+        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache_blocksize_conf_reg_t;
+
+/** Type of l1_cache_cachesize_conf register
+ *  L1 data Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1k:1;
+        /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2k:1;
+        /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4k:1;
+        /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_8k:1;
+        /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 1;
+         *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_16k:1;
+        /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_32k:1;
+        /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_64k:1;
+        /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_128k:1;
+        /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_256k:1;
+        /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_512k:1;
+        /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1024k:1;
+        /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2048k:1;
+        /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_cache_cachesize_conf_reg_t;
+
+/** Type of l1_cache_blocksize_conf register
+ *  L1 data Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_8:1;
+        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_16:1;
+        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
+         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_32:1;
+        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_64:1;
+        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_128:1;
+        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_cache_blocksize_conf_reg_t;
+
+/** Type of l2_cache_cachesize_conf register
+ *  L2 Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1k:1;
+        /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2k:1;
+        /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4k:1;
+        /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_8k:1;
+        /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_16k:1;
+        /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_32k:1;
+        /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_64k:1;
+        /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_128k:1;
+        /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256k:1;
+        /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512k:1;
+        /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1024k:1;
+        /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2048k:1;
+        /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_cachesize_conf_reg_t;
+
+/** Type of l2_cache_blocksize_conf register
+ *  L2 Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_8:1;
+        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_16:1;
+        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_32:1;
+        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_64:1;
+        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_128:1;
+        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_blocksize_conf_reg_t;
+
+
+/** Group: Wrap Mode Control and configuration registers */
+/** Type of l1_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+         */
+        uint32_t l1_icache0_wrap:1;
+        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+         */
+        uint32_t l1_icache1_wrap:1;
+        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_wrap:1;
+        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_wrap:1;
+        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to enable L1-DCache wrap around mode.
+         */
+        uint32_t l1_cache_wrap:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_wrap_around_ctrl_reg_t;
+
+/** Type of l2_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to enable L2-Cache wrap around mode.
+         */
+        uint32_t l2_cache_wrap:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_wrap_around_ctrl_reg_t;
+
+
+/** Group: Cache Tag Memory Power Control registers */
+/** Type of l1_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_tag_mem_force_on:1;
+        /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_tag_mem_force_pd:1;
+        /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_tag_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_tag_mem_force_on:1;
+        /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_tag_mem_force_pd:1;
+        /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_tag_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_on:1;
+        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pd:1;
+        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_on:1;
+        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pd:1;
+        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_cache_tag_mem_force_on:1;
+        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l1_cache_tag_mem_force_pd:1;
+        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_cache_tag_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_tag_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_tag_mem_force_on:1;
+        /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l2_cache_tag_mem_force_pd:1;
+        /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0;
+         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_tag_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_tag_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Power Control registers */
+/** Type of l1_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_data_mem_force_on:1;
+        /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_data_mem_force_pd:1;
+        /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_data_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_data_mem_force_on:1;
+        /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_data_mem_force_pd:1;
+        /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_data_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_on:1;
+        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pd:1;
+        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_on:1;
+        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pd:1;
+        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_cache_data_mem_force_on:1;
+        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_cache_data_mem_force_pd:1;
+        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_cache_data_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_data_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_data_mem_force_on:1;
+        /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l2_cache_data_mem_force_pd:1;
+        /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0;
+         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_data_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_data_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Freeze Control registers */
+/** Type of l1_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache0_freeze_en:1;
+        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache0_freeze_mode:1;
+        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_freeze_done:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache1_freeze_en:1;
+        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache1_freeze_mode:1;
+        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_freeze_done:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_en:1;
+        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_mode:1;
+        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_done:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_en:1;
+        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_mode:1;
+        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_done:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_cache_freeze_en:1;
+        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_cache_freeze_mode:1;
+        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_freeze_done:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_freeze_ctrl_reg_t;
+
+/** Type of l2_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l2_cache_freeze_en:1;
+        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l2_cache_freeze_mode:1;
+        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_freeze_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_freeze_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Access Control and Configuration registers */
+/** Type of l1_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_data_mem_rd_en:1;
+        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache0_data_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_data_mem_rd_en:1;
+        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache1_data_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_rd_en:1;
+        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_rd_en:1;
+        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_rd_en:1;
+        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_data_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_rd_en:1;
+        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_data_mem_acs_conf_reg_t;
+
+
+/** Group: Cache Tag Memory Access Control and Configuration registers */
+/** Type of l1_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_rd_en:1;
+        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_rd_en:1;
+        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_rd_en:1;
+        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_rd_en:1;
+        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_rd_en:1;
+        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_tag_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_rd_en:1;
+        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_tag_mem_acs_conf_reg_t;
+
+
+/** Group: Prelock Control and configuration registers */
+/** Type of l1_icache0_prelock_conf register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct0_en:1;
+        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct1_en:1;
+        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 prelock.
+         */
+        uint32_t l1_icache0_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_conf_reg_t;
+
+/** Type of l1_icache0_prelock_sct0_addr register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct1_addr register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct_size register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct_size_reg_t;
+
+/** Type of l1_icache1_prelock_conf register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct0_en:1;
+        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct1_en:1;
+        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 prelock.
+         */
+        uint32_t l1_icache1_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_conf_reg_t;
+
+/** Type of l1_icache1_prelock_sct0_addr register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct1_addr register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct_size register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct_size_reg_t;
+
+/** Type of l1_icache2_prelock_conf register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct0_en:1;
+        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct1_en:1;
+        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 prelock.
+         */
+        uint32_t l1_icache2_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_conf_reg_t;
+
+/** Type of l1_icache2_prelock_sct0_addr register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct1_addr register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct_size register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct_size_reg_t;
+
+/** Type of l1_icache3_prelock_conf register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct0_en:1;
+        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct1_en:1;
+        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 prelock.
+         */
+        uint32_t l1_icache3_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_conf_reg_t;
+
+/** Type of l1_icache3_prelock_sct0_addr register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct1_addr register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct_size register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct_size_reg_t;
+
+/** Type of l1_cache_prelock_conf register
+ *  L1 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct0_en:1;
+        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct1_en:1;
+        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 cache prelock.
+         */
+        uint32_t l1_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_cache_prelock_conf_reg_t;
+
+/** Type of l1_cache_prelock_sct0_addr register
+ *  L1 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-Cache, which should be used together with
+         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct1_addr register
+ *  L1 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-Cache, which should be used together with
+         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct1_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct_size register
+ *  L1  Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct_size_reg_t;
+
+/** Type of l2_cache_prelock_conf register
+ *  L2 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct0_en:1;
+        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct1_en:1;
+        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l2 cache prelock.
+         */
+        uint32_t l2_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_conf_reg_t;
+
+/** Type of l2_cache_prelock_sct0_addr register
+ *  L2 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct1_addr register
+ *  L2 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct1_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct_size register
+ *  L2 Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct0_size:16;
+        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct1_size:16;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct_size_reg_t;
+
+
+/** Group: Lock Control and configuration registers */
+/** Type of lock_ctrl register
+ *  Lock-class (manual lock) operation control register
+ */
+typedef union {
+    struct {
+        /** lock_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+         *  operation done
+         */
+        uint32_t lock_ena:1;
+        /** unlock_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable unlock operation. It will be cleared by hardware after
+         *  unlock operation done
+         */
+        uint32_t unlock_ena:1;
+        /** lock_done : RO; bitpos: [2]; default: 1;
+         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+         *  not finished. 1: finished.
+         */
+        uint32_t lock_done:1;
+        /** lock_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of cache lock/unlock.
+         */
+        uint32_t lock_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_lock_ctrl_reg_t;
+
+/** Type of lock_map register
+ *  Lock (manual lock) map configure register
+ */
+typedef union {
+    struct {
+        /** lock_map : R/W; bitpos: [5:0]; default: 0;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply this lock/unlock operation. [4]: L1-Cache
+         */
+        uint32_t lock_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_lock_map_reg_t;
+
+/** Type of lock_addr register
+ *  Lock (manual lock) address configure register
+ */
+typedef union {
+    struct {
+        /** lock_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the lock/unlock
+         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+         */
+        uint32_t lock_addr:32;
+    };
+    uint32_t val;
+} cache_lock_addr_reg_t;
+
+/** Type of lock_size register
+ *  Lock (manual lock) size configure register
+ */
+typedef union {
+    struct {
+        /** lock_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the lock/unlock operation, which
+         *  should be used together with CACHE_LOCK_ADDR_REG
+         */
+        uint32_t lock_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_lock_size_reg_t;
+
+
+/** Group: Sync Control and configuration registers */
+/** Type of sync_ctrl register
+ *  Sync-class operation control register
+ */
+typedef union {
+    struct {
+        /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
+         *  The bit is used to enable invalidate operation. It will be cleared by hardware
+         *  after invalidate operation done. Note that this bit and the other sync-bits
+         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t invalidate_ena:1;
+        /** clean_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable clean operation. It will be cleared by hardware after
+         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+         *  bits can not be set to 1 at the same time.
+         */
+        uint32_t clean_ena:1;
+        /** writeback_ena : R/W/SC; bitpos: [2]; default: 0;
+         *  The bit is used to enable writeback operation. It will be cleared by hardware after
+         *  writeback operation done. Note that this bit and the other sync-bits
+         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t writeback_ena:1;
+        /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
+         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+         *  hardware after writeback-invalidate operation done. Note that this bit and the
+         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t writeback_invalidate_ena:1;
+        /** sync_done : RO; bitpos: [4]; default: 0;
+         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+         */
+        uint32_t sync_done:1;
+        /** sync_rgid : HRO; bitpos: [8:5]; default: 0;
+         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+         *  writeback, writeback_invalidate)
+         */
+        uint32_t sync_rgid:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} cache_sync_ctrl_reg_t;
+
+/** Type of sync_map register
+ *  Sync map configure register
+ */
+typedef union {
+    struct {
+        /** sync_map : R/W; bitpos: [5:0]; default: 63;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply the sync operation.  [4]: L1-Cache
+         */
+        uint32_t sync_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_sync_map_reg_t;
+
+/** Type of sync_addr register
+ *  Sync address configure register
+ */
+typedef union {
+    struct {
+        /** sync_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the sync operation,
+         *  which should be used together with CACHE_SYNC_SIZE_REG
+         */
+        uint32_t sync_addr:32;
+    };
+    uint32_t val;
+} cache_sync_addr_reg_t;
+
+/** Type of sync_size register
+ *  Sync size configure register
+ */
+typedef union {
+    struct {
+        /** sync_size : R/W; bitpos: [23:0]; default: 0;
+         *  Those bits are used to configure the size of the sync operation, which should be
+         *  used together with CACHE_SYNC_ADDR_REG
+         */
+        uint32_t sync_size:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_sync_size_reg_t;
+
+
+/** Group: Preload Control and configuration registers */
+/** Type of l1_icache0_preload_ctrl register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache0_preload_ena:1;
+        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache0_preload_done:1;
+        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache0_preload_order:1;
+        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 preload.
+         */
+        uint32_t l1_icache0_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_ctrl_reg_t;
+
+/** Type of l1_icache0_preload_addr register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache0_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_addr_reg_t;
+
+/** Type of l1_icache0_preload_size register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache0_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_size_reg_t;
+
+/** Type of l1_icache1_preload_ctrl register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache1_preload_ena:1;
+        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache1_preload_done:1;
+        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache1_preload_order:1;
+        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 preload.
+         */
+        uint32_t l1_icache1_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_ctrl_reg_t;
+
+/** Type of l1_icache1_preload_addr register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache1_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_addr_reg_t;
+
+/** Type of l1_icache1_preload_size register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache1_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_size_reg_t;
+
+/** Type of l1_icache2_preload_ctrl register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache2_preload_ena:1;
+        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache2_preload_done:1;
+        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache2_preload_order:1;
+        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 preload.
+         */
+        uint32_t l1_icache2_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_ctrl_reg_t;
+
+/** Type of l1_icache2_preload_addr register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache2_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_addr_reg_t;
+
+/** Type of l1_icache2_preload_size register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache2_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_size_reg_t;
+
+/** Type of l1_icache3_preload_ctrl register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache3_preload_ena:1;
+        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache3_preload_done:1;
+        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache3_preload_order:1;
+        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 preload.
+         */
+        uint32_t l1_icache3_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_ctrl_reg_t;
+
+/** Type of l1_icache3_preload_addr register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache3_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_addr_reg_t;
+
+/** Type of l1_icache3_preload_size register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache3_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_size_reg_t;
+
+/** Type of l1_cache_preload_ctrl register
+ *  L1 Cache  preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_cache_preload_ena:1;
+        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_cache_preload_done:1;
+        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_cache_preload_order:1;
+        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 cache preload.
+         */
+        uint32_t l1_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l1_cache_preload_ctrl_reg_t;
+
+/** Type of l1_dcache_preload_addr register
+ *  L1 Cache  preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
+         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_cache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_addr_reg_t;
+
+/** Type of l1_dcache_preload_size register
+ *  L1 Cache  preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_cache_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_size_reg_t;
+
+/** Type of l2_cache_preload_ctrl register
+ *  L2 Cache preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l2_cache_preload_ena:1;
+        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l2_cache_preload_done:1;
+        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l2_cache_preload_order:1;
+        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l2 cache preload.
+         */
+        uint32_t l2_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_ctrl_reg_t;
+
+/** Type of l2_cache_preload_addr register
+ *  L2 Cache preload address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l2_cache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_addr_reg_t;
+
+/** Type of l2_cache_preload_size register
+ *  L2 Cache preload size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l2_cache_preload_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_size_reg_t;
+
+
+/** Group: Autoload Control and configuration registers */
+/** Type of l1_icache0_autoload_ctrl register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache0_autoload_ena:1;
+        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_autoload_done:1;
+        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache0_autoload_order:1;
+        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache0_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct0_ena:1;
+        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct1_ena:1;
+        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 autoload.
+         */
+        uint32_t l1_icache0_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_ctrl_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_addr register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_size register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_addr register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_size register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache1_autoload_ctrl register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache1_autoload_ena:1;
+        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_autoload_done:1;
+        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache1_autoload_order:1;
+        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache1_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct0_ena:1;
+        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct1_ena:1;
+        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 autoload.
+         */
+        uint32_t l1_icache1_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_ctrl_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_addr register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_size register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_addr register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_size register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache2_autoload_ctrl register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache2_autoload_ena:1;
+        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache2_autoload_done:1;
+        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache2_autoload_order:1;
+        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache2_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct0_ena:1;
+        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct1_ena:1;
+        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 autoload.
+         */
+        uint32_t l1_icache2_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_ctrl_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_addr register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_size register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_addr register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_size register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache3_autoload_ctrl register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache3_autoload_ena:1;
+        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache3_autoload_done:1;
+        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache3_autoload_order:1;
+        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache3_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct0_ena:1;
+        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct1_ena:1;
+        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 autoload.
+         */
+        uint32_t l1_icache3_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_ctrl_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_addr register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_size register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_addr register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_size register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_ctrl register
+ *  L1 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_cache_autoload_ena:1;
+        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_autoload_done:1;
+        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_cache_autoload_order:1;
+        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct0_ena:1;
+        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct1_ena:1;
+        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct2_ena:1;
+        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct3_ena:1;
+        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l1 cache autoload.
+         */
+        uint32_t l1_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_ctrl_reg_t;
+
+/** Type of l1_cache_autoload_sct0_addr register
+ *  L1 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct0_size register
+ *  L1 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_size : R/W; bitpos: [23:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_size:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct0_size_reg_t;
+
+/** Type of l1_cache_autoload_sct1_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct1_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_size : R/W; bitpos: [23:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_size:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_sct2_addr register
+ *  L1 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct2_size register
+ *  L1 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_size : HRO; bitpos: [23:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_size:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct2_size_reg_t;
+
+/** Type of l1_cache_autoload_sct3_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct3_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_size : HRO; bitpos: [23:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_size:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_sct3_size_reg_t;
+
+/** Type of l2_cache_autoload_ctrl register
+ *  L2 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l2_cache_autoload_ena:1;
+        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_autoload_done:1;
+        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l2_cache_autoload_order:1;
+        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l2_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct0_ena:1;
+        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct1_ena:1;
+        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct2_ena:1;
+        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct3_ena:1;
+        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l2 cache autoload.
+         */
+        uint32_t l2_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_sct0_addr register
+ *  L2 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct0_size register
+ *  L2 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_size_reg_t;
+
+/** Type of l2_cache_autoload_sct1_addr register
+ *  L2 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct1_size register
+ *  L2 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_size_reg_t;
+
+/** Type of l2_cache_autoload_sct2_addr register
+ *  L2 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct2_size register
+ *  L2 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_size_reg_t;
+
+/** Type of l2_cache_autoload_sct3_addr register
+ *  L2 Cache autoload section 3 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct3_size register
+ *  L2 Cache autoload section 3 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_size_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of l1_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_ena:1;
+        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_ena:1;
+        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_ena:1;
+        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_ena:1;
+        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_ena:1;
+        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_ena:1;
+        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_ena:1;
+        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+         *  to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_clr:1;
+        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+         *  to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_clr:1;
+        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_clr:1;
+        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_clr:1;
+        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_clr:1;
+        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_clr:1;
+        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_clr:1;
+        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+         *  due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_raw:1;
+        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+         *  due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_raw:1;
+        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+         *  due to bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_ovf_int_raw:1;
+        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+         *  due to bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_ovf_int_raw:1;
+        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_raw:1;
+        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_raw:1;
+        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_ovf_int_raw:1;
+        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_ovf_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_st:1;
+        /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_st:1;
+        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_st:1;
+        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_st:1;
+        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_st:1;
+        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_st:1;
+        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_st:1;
+        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l1_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_ena:1;
+        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_ena:1;
+        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_ena:1;
+        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_ena:1;
+        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l1_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_clr:1;
+        /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_clr:1;
+        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_clr:1;
+        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_clr:1;
+        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l1_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_raw:1;
+        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_raw:1;
+        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+         */
+        uint32_t l1_icache2_fail_int_raw:1;
+        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+         */
+        uint32_t l1_icache3_fail_int_raw:1;
+        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l1_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_int_st:1;
+        /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_int_st:1;
+        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_st:1;
+        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_st:1;
+        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+         *  to cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_st_reg_t;
+
+/** Type of l1_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache0_pld_done_int_ena:1;
+        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache1_pld_done_int_ena:1;
+        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_ena:1;
+        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_ena:1;
+        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_cache_pld_done_int_ena:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation done.
+         */
+        uint32_t sync_done_int_ena:1;
+        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_ena:1;
+        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_ena:1;
+        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_ena:1;
+        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_ena:1;
+        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_ena:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l1_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_clr:1;
+        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_clr:1;
+        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_clr:1;
+        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_clr:1;
+        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l1_cache_pld_done_int_clr:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+         *  done.
+         */
+        uint32_t sync_done_int_clr:1;
+        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_clr:1;
+        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_clr:1;
+        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_clr:1;
+        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_clr:1;
+        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
+         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_clr:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l1_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache0_pld_done_int_raw:1;
+        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache1_pld_done_int_raw:1;
+        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_raw:1;
+        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_raw:1;
+        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l1_cache_pld_done_int_raw:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+         */
+        uint32_t sync_done_int_raw:1;
+        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache0_pld_err_int_raw:1;
+        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache1_pld_err_int_raw:1;
+        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_raw:1;
+        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_raw:1;
+        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_err_int_raw:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+         *  occurs.
+         */
+        uint32_t sync_err_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l1_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_st:1;
+        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_st:1;
+        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_st:1;
+        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_st:1;
+        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l1_cache_pld_done_int_st:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_st : RO; bitpos: [6]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when Cache
+         *  sync-operation is done.
+         */
+        uint32_t sync_done_int_st:1;
+        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_st:1;
+        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_st:1;
+        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_st:1;
+        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_st:1;
+        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_st:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the status of the interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_st_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_ena:1;
+        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_ena:1;
+        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_ena:1;
+        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_ena:1;
+        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_ena:1;
+        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_ena:1;
+        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_ena:1;
+        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_clr:1;
+        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_clr:1;
+        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_clr:1;
+        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_clr:1;
+        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_clr:1;
+        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_clr:1;
+        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_clr:1;
+        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-ICache0.
+         */
+        uint32_t l2_ibus0_ovf_int_raw:1;
+        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-ICache1.
+         */
+        uint32_t l2_ibus1_ovf_int_raw:1;
+        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-ICache2.
+         */
+        uint32_t l2_ibus2_ovf_int_raw:1;
+        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-ICache3.
+         */
+        uint32_t l2_ibus3_ovf_int_raw:1;
+        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-DCache.
+         */
+        uint32_t l2_dbus0_ovf_int_raw:1;
+        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-DCache.
+         */
+        uint32_t l2_dbus1_ovf_int_raw:1;
+        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-DCache.
+         */
+        uint32_t l2_dbus2_ovf_int_raw:1;
+        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-DCache.
+         */
+        uint32_t l2_dbus3_ovf_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_st:1;
+        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_st:1;
+        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_st:1;
+        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_st:1;
+        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_st:1;
+        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_st:1;
+        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_st:1;
+        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l2_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+         *  l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l2_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+         *  cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l2_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l2_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+         *  to l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_st_reg_t;
+
+/** Type of l2_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+         */
+        uint32_t l2_cache_pld_done_int_ena:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l2_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l2_cache_pld_done_int_clr:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l2_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l2_cache_pld_done_int_raw:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_err_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l2_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l2_cache_pld_done_int_st:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_st_reg_t;
+
+
+/** Group: Access Statistics registers */
+/** Type of l1_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_ena:1;
+        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_ena:1;
+        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_ena:1;
+        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_ena:1;
+        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_ena:1;
+        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_ena:1;
+        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_ena:1;
+        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_ena:1;
+        uint32_t reserved_8:8;
+        /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0;
+         *  The bit is used to clear ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_clr:1;
+        /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0;
+         *  The bit is used to clear ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_clr:1;
+        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_clr:1;
+        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_clr:1;
+        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
+         *  The bit is used to clear dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_clr:1;
+        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
+         *  The bit is used to clear dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_clr:1;
+        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_clr:1;
+        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_clr:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l1_ibus0_acs_hit_cnt register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_miss_cnt register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_conflict_cnt register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_nxtlvl_cnt register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l1_ibus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_hit_cnt register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_miss_cnt register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_conflict_cnt register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_nxtlvl_cnt register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l1_ibus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_hit_cnt register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_miss_cnt register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_conflict_cnt register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_nxtlvl_cnt register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l1_ibus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_hit_cnt register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_miss_cnt register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_conflict_cnt register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_nxtlvl_cnt register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l1_ibus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_bus0_acs_hit_cnt register
+ *  L1-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus0_acs_miss_cnt register
+ *  L1-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus0_acs_conflict_cnt register
+ *  L1-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_bus0_acs_nxtlvl_cnt register
+ *  L1-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus0 accessing L1-Cache.
+         */
+        uint32_t l1_bus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_bus1_acs_hit_cnt register
+ *  L1-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus1_acs_miss_cnt register
+ *  L1-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus1_acs_conflict_cnt register
+ *  L1-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_bus1_acs_nxtlvl_cnt register
+ *  L1-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus1 accessing L1-Cache.
+         */
+        uint32_t l1_bus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_bus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_hit_cnt register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_miss_cnt register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_conflict_cnt register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_cnt register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_hit_cnt register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_miss_cnt register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_conflict_cnt register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_cnt register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_ena:1;
+        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_ena:1;
+        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_ena:1;
+        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_ena:1;
+        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_ena:1;
+        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_ena:1;
+        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_ena:1;
+        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_ena:1;
+        uint32_t reserved_16:8;
+        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
+         *  The bit is used to clear ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_clr:1;
+        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
+         *  The bit is used to clear ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_clr:1;
+        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_clr:1;
+        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_clr:1;
+        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
+         *  The bit is used to clear dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_clr:1;
+        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
+         *  The bit is used to clear dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_clr:1;
+        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_clr:1;
+        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_clr:1;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l2_ibus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache0 accesses
+         *  L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_nxtlvl_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache1 accesses
+         *  L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_nxtlvl_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache2 accesses
+         *  L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_nxtlvl_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache3 accesses
+         *  L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_nxtlvl_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_cnt_reg_t;
+
+
+/** Group: Access Fail Debug registers */
+/** Type of l1_icache0_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_id:16;
+        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache0_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_addr_reg_t;
+
+/** Type of l1_icache1_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_id:16;
+        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache1_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_addr_reg_t;
+
+/** Type of l1_icache2_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_id:16;
+        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache2_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_addr_reg_t;
+
+/** Type of l1_icache3_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_id:16;
+        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache3_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_addr_reg_t;
+
+/** Type of l1_cache_acs_fail_id_attr register
+ *  L1-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_id:16;
+        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l1_dcache_acs_fail_addr register
+ *  L1-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_addr_reg_t;
+
+/** Type of l2_cache_acs_fail_id_attr register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_id:16;
+        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+         *  due to cache accessing L1-Cache.
+         */
+        uint32_t l2_cache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l2_cache_acs_fail_addr register
+ *  L2-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_addr_reg_t;
+
+
+/** Group: Operation Exception registers */
+/** Type of l1_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache0.
+         */
+        uint32_t l1_icache0_pld_err_code:2;
+        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache1.
+         */
+        uint32_t l1_icache1_pld_err_code:2;
+        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_code:2;
+        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_code:2;
+        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-Cache.
+         */
+        uint32_t l1_cache_pld_err_code:2;
+        uint32_t reserved_10:2;
+        /** sync_err_code : RO; bitpos: [13:12]; default: 0;
+         *  The values 0-2 are available which means sync map, command conflict and size are
+         *  error in Cache System.
+         */
+        uint32_t sync_err_code:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_exception_reg_t;
+
+/** Type of l2_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L2-Cache.
+         */
+        uint32_t l2_cache_pld_err_code:2;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_exception_reg_t;
+
+
+/** Group: Sync Reset control and configuration registers */
+/** Type of l1_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache0_sync_rst:1;
+        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache1_sync_rst:1;
+        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_sync_rst:1;
+        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_sync_rst:1;
+        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_cache_sync_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_rst_ctrl_reg_t;
+
+/** Type of l2_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l2_cache_sync_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_rst_ctrl_reg_t;
+
+
+/** Group: Preload Reset control and configuration registers */
+/** Type of l1_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache0_pld_rst:1;
+        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache1_pld_rst:1;
+        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_rst:1;
+        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_rst:1;
+        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_preload_rst_ctrl_reg_t;
+
+/** Type of l2_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_rst_ctrl_reg_t;
+
+
+/** Group: Autoload buffer clear control and configuration registers */
+/** Type of l1_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+         *  works in L1-ICache0.
+         */
+        uint32_t l1_icache0_ald_buf_clr:1;
+        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+         *  works in L1-ICache1.
+         */
+        uint32_t l1_icache1_ald_buf_clr:1;
+        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_ald_buf_clr:1;
+        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_ald_buf_clr:1;
+        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
+         *  autoload will not work in L1-Cache. This bit should not be active when autoload
+         *  works in L1-Cache.
+         */
+        uint32_t l1_cache_ald_buf_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_buf_clr_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
+         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+         *  autoload will not work in L2-Cache. This bit should not be active when autoload
+         *  works in L2-Cache.
+         */
+        uint32_t l2_cache_ald_buf_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_buf_clr_ctrl_reg_t;
+
+
+/** Group: Unallocate request buffer clear registers */
+/** Type of l1_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache0_unalloc_clr:1;
+        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache1_unalloc_clr:1;
+        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_unalloc_clr:1;
+        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_unalloc_clr:1;
+        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 cache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_cache_unalloc_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_unallocate_buffer_clear_reg_t;
+
+/** Type of l2_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l2 icache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l2_cache_unalloc_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_unallocate_buffer_clear_reg_t;
+
+
+/** Group: Tag and Data Memory Access Control and configuration register */
+/** Type of l1_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0;
+         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache0_tag_object:1;
+        /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0;
+         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache1_tag_object:1;
+        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_object:1;
+        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_object:1;
+        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_tag_object:1;
+        uint32_t reserved_5:1;
+        /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0;
+         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache0_mem_object:1;
+        /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0;
+         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache1_mem_object:1;
+        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_mem_object:1;
+        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_mem_object:1;
+        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_mem_object:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} cache_l1_cache_object_ctrl_reg_t;
+
+/** Type of l1_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l1_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l1_cache_way_object_reg_t;
+
+/** Type of l1_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l1_cache_vaddr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_vaddr_reg_t;
+
+/** Type of l1_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l1_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l1_cache_debug_bus_reg_t;
+
+/** Type of l2_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
+         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_tag_object:1;
+        uint32_t reserved_6:5;
+        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
+         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_mem_object:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_object_ctrl_reg_t;
+
+/** Type of l2_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l2_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l2_cache_way_object_reg_t;
+
+/** Type of l2_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l2_cache_vaddr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_vaddr_reg_t;
+
+/** Type of l2_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l2_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l2_cache_debug_bus_reg_t;
+
+
+/** Group: Split L1 and L2 registers */
+/** Type of level_split0 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split0 : HRO; bitpos: [31:0]; default: 600;
+         *  Reserved
+         */
+        uint32_t level_split0:32;
+    };
+    uint32_t val;
+} cache_level_split0_reg_t;
+
+/** Type of level_split1 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split1 : HRO; bitpos: [31:0]; default: 936;
+         *  Reserved
+         */
+        uint32_t level_split1:32;
+    };
+    uint32_t val;
+} cache_level_split1_reg_t;
+
+
+/** Group: L2 cache access attribute control register */
+/** Type of l2_cache_access_attr_ctrl register
+ *  L1 Cache access Attribute propagation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
+         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+         *  non-cacheable.
+         */
+        uint32_t l2_cache_access_force_cc:1;
+        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+         *  write-through.
+         */
+        uint32_t l2_cache_access_force_wb:1;
+        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  write-miss-allocate and write-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_wma:1;
+        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
+         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  read-miss-allocate and read-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_rma:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_l2_cache_access_attr_ctrl_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_clock_gate_reg_t;
+
+
+/** Group: Redundancy  register (Prepare for ECO) */
+/** Type of redundancy_sig0 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig0:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig0_reg_t;
+
+/** Type of redundancy_sig1 register
+ *  Cache redundancy signal 1 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig1:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig1_reg_t;
+
+/** Type of redundancy_sig2 register
+ *  Cache redundancy signal 2 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig2:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig2_reg_t;
+
+/** Type of redundancy_sig3 register
+ *  Cache redundancy signal 3 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig3:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig3_reg_t;
+
+/** Type of redundancy_sig4 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig4 : RO; bitpos: [3:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t redcy_sig4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_redundancy_sig4_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35680848;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_date_reg_t;
+
+
+typedef struct {
+    volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl;
+    volatile cache_l1_cache_ctrl_reg_t l1_cache_ctrl;
+    volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
+    volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
+    volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
+    volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
+    volatile cache_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
+    volatile cache_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
+    volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
+    volatile cache_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
+    volatile cache_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
+    volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
+    volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
+    volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
+    volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
+    volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
+    volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
+    volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
+    volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
+    volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
+    volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
+    volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
+    volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
+    volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
+    volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
+    volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
+    volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
+    volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
+    volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
+    volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
+    volatile cache_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
+    volatile cache_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
+    volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
+    volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
+    volatile cache_lock_ctrl_reg_t lock_ctrl;
+    volatile cache_lock_map_reg_t lock_map;
+    volatile cache_lock_addr_reg_t lock_addr;
+    volatile cache_lock_size_reg_t lock_size;
+    volatile cache_sync_ctrl_reg_t sync_ctrl;
+    volatile cache_sync_map_reg_t sync_map;
+    volatile cache_sync_addr_reg_t sync_addr;
+    volatile cache_sync_size_reg_t sync_size;
+    volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
+    volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
+    volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
+    volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
+    volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
+    volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
+    volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
+    volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
+    volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
+    volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
+    volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
+    volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
+    volatile cache_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
+    volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
+    volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
+    volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
+    volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
+    volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
+    volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
+    volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
+    volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
+    volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
+    volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
+    volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
+    volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
+    volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
+    volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
+    volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
+    volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
+    volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
+    volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
+    volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
+    volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
+    volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
+    volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
+    volatile cache_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
+    volatile cache_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
+    volatile cache_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
+    volatile cache_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
+    volatile cache_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
+    volatile cache_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
+    volatile cache_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
+    volatile cache_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
+    volatile cache_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
+    volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
+    volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
+    volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
+    volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
+    volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
+    volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
+    volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
+    volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
+    volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
+    volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
+    volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
+    volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
+    volatile cache_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt;
+    volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
+    volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
+    volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
+    volatile cache_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt;
+    volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
+    volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
+    volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
+    volatile cache_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt;
+    volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
+    volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
+    volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
+    volatile cache_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt;
+    volatile cache_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
+    volatile cache_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
+    volatile cache_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
+    volatile cache_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt;
+    volatile cache_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
+    volatile cache_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
+    volatile cache_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
+    volatile cache_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt;
+    volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
+    volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
+    volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt;
+    volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
+    volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
+    volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt;
+    volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
+    volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
+    volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
+    volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
+    volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
+    volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
+    volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
+    volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
+    volatile cache_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr;
+    volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
+    volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
+    volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
+    volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
+    volatile cache_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
+    volatile cache_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
+    volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
+    volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
+    volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
+    volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
+    volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
+    volatile cache_l1_cache_way_object_reg_t l1_cache_way_object;
+    volatile cache_l1_cache_vaddr_reg_t l1_cache_vaddr;
+    volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
+    volatile cache_level_split0_reg_t level_split0;
+    volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl;
+    volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
+    volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
+    volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
+    volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
+    volatile cache_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
+    volatile cache_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
+    volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
+    volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
+    volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
+    volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
+    volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
+    volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
+    volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
+    volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
+    volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
+    volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size;
+    volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
+    volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
+    volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
+    volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
+    volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
+    volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
+    volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
+    volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
+    volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
+    volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
+    volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
+    volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
+    volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
+    volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
+    volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
+    volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
+    volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
+    volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
+    volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
+    volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
+    volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
+    volatile cache_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt;
+    volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
+    volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
+    volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
+    volatile cache_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt;
+    volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
+    volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
+    volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
+    volatile cache_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt;
+    volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
+    volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
+    volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
+    volatile cache_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt;
+    volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
+    volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
+    volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt;
+    volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
+    volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
+    volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt;
+    volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
+    volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
+    volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt;
+    volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
+    volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
+    volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt;
+    volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
+    volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
+    volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
+    volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
+    volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
+    volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
+    volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
+    volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
+    volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
+    volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
+    volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
+    volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
+    volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
+    volatile cache_l2_cache_way_object_reg_t l2_cache_way_object;
+    volatile cache_l2_cache_vaddr_reg_t l2_cache_vaddr;
+    volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
+    volatile cache_level_split1_reg_t level_split1;
+    volatile cache_clock_gate_reg_t clock_gate;
+    volatile cache_redundancy_sig0_reg_t redundancy_sig0;
+    volatile cache_redundancy_sig1_reg_t redundancy_sig1;
+    volatile cache_redundancy_sig2_reg_t redundancy_sig2;
+    volatile cache_redundancy_sig3_reg_t redundancy_sig3;
+    volatile cache_redundancy_sig4_reg_t redundancy_sig4;
+    uint32_t reserved_3c4[14];
+    volatile cache_date_reg_t date;
+} cache_dev_t;
+
+extern cache_dev_t CACHE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/clint_reg.h b/components/soc/esp32h2/register/soc/clint_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/clint_reg.h
rename to components/soc/esp32h2/register/soc/clint_reg.h
diff --git a/components/soc/esp32h2/include/soc/ds_reg.h b/components/soc/esp32h2/register/soc/ds_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/ds_reg.h
rename to components/soc/esp32h2/register/soc/ds_reg.h
diff --git a/components/soc/esp32h2/include/soc/ds_struct.h b/components/soc/esp32h2/register/soc/ds_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/ds_struct.h
rename to components/soc/esp32h2/register/soc/ds_struct.h
diff --git a/components/soc/esp32h2/register/soc/ecc_mult_reg.h b/components/soc/esp32h2/register/soc/ecc_mult_reg.h
new file mode 100644
index 00000000000..bd6084940fe
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/ecc_mult_reg.h
@@ -0,0 +1,185 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECC_MULT_INT_RAW_REG register
+ *  ECC interrupt raw register, valid in level.
+ */
+#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
+/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_RAW_S  0
+
+/** ECC_MULT_INT_ST_REG register
+ *  ECC interrupt status register.
+ */
+#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
+/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ST_S  0
+
+/** ECC_MULT_INT_ENA_REG register
+ *  ECC interrupt enable register.
+ */
+#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
+/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ENA_S  0
+
+/** ECC_MULT_INT_CLR_REG register
+ *  ECC interrupt clear register.
+ */
+#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
+/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_CLR_S  0
+
+/** ECC_MULT_CONF_REG register
+ *  ECC configure register
+ */
+#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
+/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
+ *  the caculatrion is done.
+ */
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
+#define ECC_MULT_START_V  0x00000001U
+#define ECC_MULT_START_S  0
+/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
+ *  Write 1 to reset ECC Accelerator.
+ */
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
+#define ECC_MULT_RESET_V  0x00000001U
+#define ECC_MULT_RESET_S  1
+/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
+ *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
+ */
+#define ECC_MULT_KEY_LENGTH    (BIT(2))
+#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
+#define ECC_MULT_KEY_LENGTH_V  0x00000001U
+#define ECC_MULT_KEY_LENGTH_S  2
+/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
+ *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
+ *  1: p(mod base of curve)
+ */
+#define ECC_MULT_MOD_BASE    (BIT(3))
+#define ECC_MULT_MOD_BASE_M  (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
+#define ECC_MULT_MOD_BASE_V  0x00000001U
+#define ECC_MULT_MOD_BASE_S  3
+/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
+ *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
+ *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
+ *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
+ *  8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division.
+ */
+#define ECC_MULT_WORK_MODE    0x0000000FU
+#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
+#define ECC_MULT_WORK_MODE_V  0x0000000FU
+#define ECC_MULT_WORK_MODE_S  4
+/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define ECC_MULT_SECURITY_MODE    (BIT(8))
+#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
+#define ECC_MULT_SECURITY_MODE_V  0x00000001U
+#define ECC_MULT_SECURITY_MODE_S  8
+/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
+ *  The verification result bit of ECC Accelerator, only valid when calculation is done.
+ */
+#define ECC_MULT_VERIFICATION_RESULT    (BIT(29))
+#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
+#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
+#define ECC_MULT_VERIFICATION_RESULT_S  29
+/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECC_MULT_CLK_EN    (BIT(30))
+#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
+#define ECC_MULT_CLK_EN_V  0x00000001U
+#define ECC_MULT_CLK_EN_S  30
+/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 1;
+ *  ECC memory clock gate force on register
+ */
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
+
+/** ECC_MULT_DATE_REG register
+ *  Version control register
+ */
+#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
+/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 35680640;
+ *  ECC mult version control register
+ */
+#define ECC_MULT_DATE    0x0FFFFFFFU
+#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
+#define ECC_MULT_DATE_V  0x0FFFFFFFU
+#define ECC_MULT_DATE_S  0
+
+/** ECC_MULT_K_MEM register
+ *  The memory that stores k.
+ */
+#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
+#define ECC_MULT_K_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_PX_MEM register
+ *  The memory that stores Px.
+ */
+#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
+#define ECC_MULT_PX_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_PY_MEM register
+ *  The memory that stores Py.
+ */
+#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
+#define ECC_MULT_PY_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_QX_MEM register
+ *  The memory that stores Qx.
+ */
+#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
+#define ECC_MULT_QX_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_QY_MEM register
+ *  The memory that stores Qy.
+ */
+#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
+#define ECC_MULT_QY_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_QZ_MEM register
+ *  The memory that stores Qz.
+ */
+#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0)
+#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/ecc_mult_struct.h b/components/soc/esp32h2/register/soc/ecc_mult_struct.h
new file mode 100644
index 00000000000..a9f458c5d96
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/ecc_mult_struct.h
@@ -0,0 +1,169 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "esp_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECC interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECC interrupt status register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECC interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECC interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of conf register
+ *  ECC configure register
+ */
+typedef union {
+    struct {
+        /** start : R/W/SC; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
+         *  the caculatrion is done.
+         */
+        uint32_t start:1;
+        /** reset : WT; bitpos: [1]; default: 0;
+         *  Write 1 to reset ECC Accelerator.
+         */
+        uint32_t reset:1;
+        /** key_length : R/W; bitpos: [2]; default: 0;
+         *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
+         */
+        uint32_t key_length:1;
+        /** mod_base : R/W; bitpos: [3]; default: 0;
+         *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
+         *  1: p(mod base of curve)
+         */
+        uint32_t mod_base:1;
+        /** work_mode : R/W; bitpos: [7:4]; default: 0;
+         *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
+         *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
+         *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
+         *  8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division.
+         */
+        uint32_t work_mode:4;
+        /** security_mode : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t security_mode:1;
+        uint32_t reserved_9:20;
+        /** verification_result : RO/SS; bitpos: [29]; default: 0;
+         *  The verification result bit of ECC Accelerator, only valid when calculation is done.
+         */
+        uint32_t verification_result:1;
+        /** clk_en : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_en:1;
+        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 1;
+         *  ECC memory clock gate force on register
+         */
+        uint32_t mem_clock_gate_force_on:1;
+    };
+    uint32_t val;
+} ecc_mult_conf_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35680640;
+         *  ECC mult version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecc_mult_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile ecc_mult_int_raw_reg_t int_raw;
+    volatile ecc_mult_int_st_reg_t int_st;
+    volatile ecc_mult_int_ena_reg_t int_ena;
+    volatile ecc_mult_int_clr_reg_t int_clr;
+    volatile ecc_mult_conf_reg_t conf;
+    uint32_t reserved_020[55];
+    volatile ecc_mult_date_reg_t date;
+    volatile uint32_t k[8];
+    volatile uint32_t px[8];
+    volatile uint32_t py[8];
+    volatile uint32_t qx[8];
+    volatile uint32_t qy[8];
+    volatile uint32_t qz[8];
+} ecc_mult_dev_t;
+
+extern ecc_mult_dev_t ECC;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecc_mult_dev_t) == 0x1C0, "Invalid size of ecc_mult_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/ecdsa_reg.h b/components/soc/esp32h2/register/soc/ecdsa_reg.h
new file mode 100644
index 00000000000..88f19ad16ce
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/ecdsa_reg.h
@@ -0,0 +1,295 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECDSA_CONF_REG register
+ *  ECDSA configure register
+ */
+#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
+/** ECDSA_WORK_MODE : R/W; bitpos: [0]; default: 0;
+ *  The work mode bits of ECDSA Accelerator. 0: Signature Verify mode. 1: Signature
+ *  Generate Mode.
+ */
+#define ECDSA_WORK_MODE    (BIT(0))
+#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
+#define ECDSA_WORK_MODE_V  0x00000001U
+#define ECDSA_WORK_MODE_S  0
+/** ECDSA_ECC_CURVE : R/W; bitpos: [1]; default: 0;
+ *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
+ */
+#define ECDSA_ECC_CURVE    (BIT(1))
+#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
+#define ECDSA_ECC_CURVE_V  0x00000001U
+#define ECDSA_ECC_CURVE_S  1
+/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [2]; default: 0;
+ *  The source of k select bit. 0: k is automatically generated by TRNG. 1: k is
+ *  written by software.
+ */
+#define ECDSA_SOFTWARE_SET_K    (BIT(2))
+#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
+#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_K_S  2
+/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [3]; default: 0;
+ *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+ *  software.
+ */
+#define ECDSA_SOFTWARE_SET_Z    (BIT(3))
+#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
+#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_Z_S  3
+
+/** ECDSA_CLK_REG register
+ *  ECDSA clock gate register
+ */
+#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
+/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
+#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
+#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
+#define ECDSA_CLK_GATE_FORCE_ON_S  0
+
+/** ECDSA_INT_RAW_REG register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
+/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_RAW    (BIT(0))
+#define ECDSA_CALC_DONE_INT_RAW_M  (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
+#define ECDSA_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_RAW_S  0
+/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
+#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_RAW_S  1
+
+/** ECDSA_INT_ST_REG register
+ *  ECDSA interrupt status register.
+ */
+#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
+/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_ST    (BIT(0))
+#define ECDSA_CALC_DONE_INT_ST_M  (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
+#define ECDSA_CALC_DONE_INT_ST_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_ST_S  0
+/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ST    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
+#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ST_S  1
+
+/** ECDSA_INT_ENA_REG register
+ *  ECDSA interrupt enable register.
+ */
+#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
+/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_ENA    (BIT(0))
+#define ECDSA_CALC_DONE_INT_ENA_M  (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
+#define ECDSA_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_ENA_S  0
+/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
+#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ENA_S  1
+
+/** ECDSA_INT_CLR_REG register
+ *  ECDSA interrupt clear register.
+ */
+#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
+/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_CLR    (BIT(0))
+#define ECDSA_CALC_DONE_INT_CLR_M  (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
+#define ECDSA_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_CLR_S  0
+/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
+#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_CLR_S  1
+
+/** ECDSA_START_REG register
+ *  ECDSA start register
+ */
+#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
+/** ECDSA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+ *  after configuration.
+ */
+#define ECDSA_START    (BIT(0))
+#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
+#define ECDSA_START_V  0x00000001U
+#define ECDSA_START_S  0
+/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_LOAD_DONE    (BIT(1))
+#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
+#define ECDSA_LOAD_DONE_V  0x00000001U
+#define ECDSA_LOAD_DONE_S  1
+/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_GET_DONE    (BIT(2))
+#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
+#define ECDSA_GET_DONE_V  0x00000001U
+#define ECDSA_GET_DONE_S  2
+
+/** ECDSA_STATE_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
+/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
+ *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+ *  state.
+ */
+#define ECDSA_BUSY    0x00000003U
+#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
+#define ECDSA_BUSY_V  0x00000003U
+#define ECDSA_BUSY_S  0
+
+/** ECDSA_RESULT_REG register
+ *  ECDSA result register
+ */
+#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
+/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+ *  done.
+ */
+#define ECDSA_OPERATION_RESULT    (BIT(0))
+#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
+#define ECDSA_OPERATION_RESULT_V  0x00000001U
+#define ECDSA_OPERATION_RESULT_S  0
+
+/** ECDSA_DATE_REG register
+ *  Version control register
+ */
+#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
+/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 35684752;
+ *  ECDSA version control register
+ */
+#define ECDSA_DATE    0x0FFFFFFFU
+#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
+#define ECDSA_DATE_V  0x0FFFFFFFU
+#define ECDSA_DATE_S  0
+
+/** ECDSA_SHA_MODE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
+/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
+ *  Others: invalid.
+ */
+#define ECDSA_SHA_MODE    0x00000007U
+#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
+#define ECDSA_SHA_MODE_V  0x00000007U
+#define ECDSA_SHA_MODE_S  0
+
+/** ECDSA_SHA_START_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
+/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_START    (BIT(0))
+#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
+#define ECDSA_SHA_START_V  0x00000001U
+#define ECDSA_SHA_START_S  0
+
+/** ECDSA_SHA_CONTINUE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
+/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_CONTINUE    (BIT(0))
+#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
+#define ECDSA_SHA_CONTINUE_V  0x00000001U
+#define ECDSA_SHA_CONTINUE_S  0
+
+/** ECDSA_SHA_BUSY_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
+/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
+ *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+ *  calculation. 0: SHA is idle.
+ */
+#define ECDSA_SHA_BUSY    (BIT(0))
+#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
+#define ECDSA_SHA_BUSY_V  0x00000001U
+#define ECDSA_SHA_BUSY_S  0
+
+/** ECDSA_MESSAGE_MEM register
+ *  The memory that stores message.
+ */
+#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
+#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
+
+/** ECDSA_R_MEM register
+ *  The memory that stores r.
+ */
+#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
+#define ECDSA_R_MEM_SIZE_BYTES 32
+
+/** ECDSA_S_MEM register
+ *  The memory that stores s.
+ */
+#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
+#define ECDSA_S_MEM_SIZE_BYTES 32
+
+/** ECDSA_Z_MEM register
+ *  The memory that stores software written z.
+ */
+#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
+#define ECDSA_Z_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAX_MEM register
+ *  The memory that stores x coordinates of QA or software written k.
+ */
+#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
+#define ECDSA_QAX_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAY_MEM register
+ *  The memory that stores y coordinates of QA.
+ */
+#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
+#define ECDSA_QAY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/ecdsa_struct.h b/components/soc/esp32h2/register/soc/ecdsa_struct.h
new file mode 100644
index 00000000000..ca9076e5526
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/ecdsa_struct.h
@@ -0,0 +1,310 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Data Memory */
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  ECDSA configure register
+ */
+typedef union {
+    struct {
+        /** work_mode : R/W; bitpos: [0]; default: 0;
+         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+         *  Generate Mode.
+         */
+        uint32_t work_mode:1;
+        /** ecc_curve : R/W; bitpos: [1]; default: 0;
+         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
+         */
+        uint32_t ecc_curve:1;
+        /** software_set_k : R/W; bitpos: [2]; default: 0;
+         *  The source of k select bit. 0: k is automatically generated by TRNG. 1: k is
+         *  written by software.
+         */
+        uint32_t software_set_k:1;
+        /** software_set_z : R/W; bitpos: [3]; default: 0;
+         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+         *  software.
+         */
+        uint32_t software_set_z:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_conf_reg_t;
+
+/** Type of start register
+ *  ECDSA start register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+         *  after configuration.
+         */
+        uint32_t start:1;
+        /** load_done : WT; bitpos: [1]; default: 0;
+         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t load_done:1;
+        /** get_done : WT; bitpos: [2]; default: 0;
+         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t get_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_start_reg_t;
+
+
+/** Group: Clock and reset registers */
+/** Type of clk register
+ *  ECDSA clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_gate_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_raw:1;
+        /** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECDSA interrupt status register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_st:1;
+        /** sha_release_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECDSA interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_ena:1;
+        /** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECDSA interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecdsa_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_clr:1;
+        /** sha_release_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_int_clr_reg_t;
+
+
+/** Group: Status registers */
+/** Type of state register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** busy : RO; bitpos: [1:0]; default: 0;
+         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+         *  state.
+         */
+        uint32_t busy:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of result register
+ *  ECDSA result register
+ */
+typedef union {
+    struct {
+        /** operation_result : RO/SS; bitpos: [0]; default: 0;
+         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+         *  done.
+         */
+        uint32_t operation_result:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_result_reg_t;
+
+
+/** Group: SHA register */
+/** Type of sha_mode register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
+         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
+         *  Others: invalid.
+         */
+        uint32_t sha_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_sha_mode_reg_t;
+
+/** Type of sha_start register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_start_reg_t;
+
+/** Type of sha_continue register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_continue : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_continue_reg_t;
+
+/** Type of sha_busy register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** sha_busy : RO; bitpos: [0]; default: 0;
+         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+         *  calculation. 0: SHA is idle.
+         */
+        uint32_t sha_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_busy_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35684752;
+         *  ECDSA version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecdsa_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile ecdsa_conf_reg_t conf;
+    volatile ecdsa_clk_reg_t clk;
+    volatile ecdsa_int_raw_reg_t int_raw;
+    volatile ecdsa_int_st_reg_t int_st;
+    volatile ecdsa_int_ena_reg_t int_ena;
+    volatile ecdsa_int_clr_reg_t int_clr;
+    volatile ecdsa_start_reg_t start;
+    volatile ecdsa_state_reg_t state;
+    volatile ecdsa_result_reg_t result;
+    uint32_t reserved_028[53];
+    volatile ecdsa_date_reg_t date;
+    uint32_t reserved_100[64];
+    volatile ecdsa_sha_mode_reg_t sha_mode;
+    uint32_t reserved_204[3];
+    volatile ecdsa_sha_start_reg_t sha_start;
+    volatile ecdsa_sha_continue_reg_t sha_continue;
+    volatile ecdsa_sha_busy_reg_t sha_busy;
+    uint32_t reserved_21c[25];
+    volatile uint32_t message[8];
+    uint32_t reserved_2a0[472];
+    volatile uint32_t r[8];
+    volatile uint32_t s[8];
+    volatile uint32_t z[8];
+    volatile uint32_t qax[8];
+    volatile uint32_t qay[8];
+} ecdsa_dev_t;
+
+extern ecdsa_dev_t ECDSA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/efuse_reg.h b/components/soc/esp32h2/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..915c37d8481
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/efuse_reg.h
@@ -0,0 +1,2706 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/efuse_defs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled or
+ *  enabled. 1: Disabled. 0 Enabled.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_RPT4_RESERVED0_4 : RO; bitpos: [7]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_4    (BIT(7))
+#define EFUSE_RPT4_RESERVED0_4_M  (EFUSE_RPT4_RESERVED0_4_V << EFUSE_RPT4_RESERVED0_4_S)
+#define EFUSE_RPT4_RESERVED0_4_V  0x00000001U
+#define EFUSE_RPT4_RESERVED0_4_S  7
+/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
+ *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_ICACHE    (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
+#define EFUSE_DIS_ICACHE_V  0x00000001U
+#define EFUSE_DIS_ICACHE_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
+ *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_POWERGLITCH_EN    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
+ *  Represents whether SPI0 controller during boot_mode_download is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+ *  enabled.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+ *  enabled.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode). 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
+ */
+#define EFUSE_USB_DREFH    0x00000003U
+#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
+#define EFUSE_USB_DREFH_V  0x00000003U
+#define EFUSE_USB_DREFH_S  21
+/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
+ *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
+ */
+#define EFUSE_USB_DREFL    0x00000003U
+#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
+#define EFUSE_USB_DREFL_V  0x00000003U
+#define EFUSE_USB_DREFL_S  23
+/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
+ *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.
+ */
+#define EFUSE_USB_EXCHG_PINS    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
+#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_S  25
+/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
+ *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
+ *  functioned.
+ */
+#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
+#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_S  26
+/** EFUSE_RPT4_RESERVED0_2 : RO; bitpos: [28:27]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_2    0x00000003U
+#define EFUSE_RPT4_RESERVED0_2_M  (EFUSE_RPT4_RESERVED0_2_V << EFUSE_RPT4_RESERVED0_2_S)
+#define EFUSE_RPT4_RESERVED0_2_V  0x00000003U
+#define EFUSE_RPT4_RESERVED0_2_S  27
+/** EFUSE_RPT4_RESERVED0_1 : RO; bitpos: [29]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_1    (BIT(29))
+#define EFUSE_RPT4_RESERVED0_1_M  (EFUSE_RPT4_RESERVED0_1_V << EFUSE_RPT4_RESERVED0_1_S)
+#define EFUSE_RPT4_RESERVED0_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED0_1_S  29
+/** EFUSE_RPT4_RESERVED0_0 : RO; bitpos: [31:30]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_0    0x00000003U
+#define EFUSE_RPT4_RESERVED0_0_M  (EFUSE_RPT4_RESERVED0_0_V << EFUSE_RPT4_RESERVED0_0_S)
+#define EFUSE_RPT4_RESERVED0_0_V  0x00000003U
+#define EFUSE_RPT4_RESERVED0_0_S  30
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register 2.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_RPT4_RESERVED1_1 : RO; bitpos: [15:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED1_1    0x0000FFFFU
+#define EFUSE_RPT4_RESERVED1_1_M  (EFUSE_RPT4_RESERVED1_1_V << EFUSE_RPT4_RESERVED1_1_S)
+#define EFUSE_RPT4_RESERVED1_1_V  0x0000FFFFU
+#define EFUSE_RPT4_RESERVED1_1_S  0
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+ *  selected. 0: not selected.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+ *  1: enabled. Even number of 1: disabled.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register 3.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Represents the purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  16
+/** EFUSE_ECDSA_FORCE_USE_HARDWARE_K : RO; bitpos: [18]; default: 1;
+ *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+ *  0: not force used.
+ */
+#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K    (BIT(18))
+#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_M  (EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V << EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S)
+#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_V  0x00000001U
+#define EFUSE_ECDSA_FORCE_USE_HARDWARE_K_S  18
+/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
+ *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
+#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_S  19
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RPT4_RESERVED2_0 : RO; bitpos: [27:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_0    0x0000003FU
+#define EFUSE_RPT4_RESERVED2_0_M  (EFUSE_RPT4_RESERVED2_0_V << EFUSE_RPT4_RESERVED2_0_S)
+#define EFUSE_RPT4_RESERVED2_0_V  0x0000003FU
+#define EFUSE_RPT4_RESERVED2_0_S  22
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+ *  is 2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register 4.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Set this bit to disable USB-Serial-JTAG print during rom boot.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_5    (BIT(3))
+#define EFUSE_RPT4_RESERVED3_5_M  (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S)
+#define EFUSE_RPT4_RESERVED3_5_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_5_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+ *  disabled.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Represents the type of UART printing. 00: force enable printing. 01: enable
+ *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+ *  at high level. 11: force disable printing.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+ *  forced. 0:not forced.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  8
+/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
+ *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
+/** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0;
+ *  Set bits to enable hysteresis function of PAD0~5
+ */
+#define EFUSE_HYS_EN_PAD0    0x0000003FU
+#define EFUSE_HYS_EN_PAD0_M  (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S)
+#define EFUSE_HYS_EN_PAD0_V  0x0000003FU
+#define EFUSE_HYS_EN_PAD0_S  26
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register 5.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0;
+ *  Set bits to enable hysteresis function of PAD6~27
+ */
+#define EFUSE_HYS_EN_PAD1    0x003FFFFFU
+#define EFUSE_HYS_EN_PAD1_M  (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S)
+#define EFUSE_HYS_EN_PAD1_V  0x003FFFFFU
+#define EFUSE_HYS_EN_PAD1_S  0
+/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_1    0x00000003U
+#define EFUSE_RPT4_RESERVED4_1_M  (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S)
+#define EFUSE_RPT4_RESERVED4_1_V  0x00000003U
+#define EFUSE_RPT4_RESERVED4_1_S  22
+/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_0    0x000000FFU
+#define EFUSE_RPT4_RESERVED4_0_M  (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S)
+#define EFUSE_RPT4_RESERVED4_0_V  0x000000FFU
+#define EFUSE_RPT4_RESERVED4_0_S  24
+
+/** EFUSE_RD_MAC_SYS_0_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SYS_1_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
+ *  Stores the extended bits of MAC address.
+ */
+#define EFUSE_MAC_EXT    0x0000FFFFU
+#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
+#define EFUSE_MAC_EXT_V  0x0000FFFFU
+#define EFUSE_MAC_EXT_S  16
+
+/** EFUSE_RD_MAC_SYS_2_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_RXIQ_VERSION : RO; bitpos: [2:0]; default: 0;
+ *  Stores RF Calibration data. RXIQ version.
+ */
+#define EFUSE_RXIQ_VERSION    0x00000007U
+#define EFUSE_RXIQ_VERSION_M  (EFUSE_RXIQ_VERSION_V << EFUSE_RXIQ_VERSION_S)
+#define EFUSE_RXIQ_VERSION_V  0x00000007U
+#define EFUSE_RXIQ_VERSION_S  0
+/** EFUSE_RXIQ_0 : RO; bitpos: [9:3]; default: 0;
+ *  Stores RF Calibration data. RXIQ data 0.
+ */
+#define EFUSE_RXIQ_0    0x0000007FU
+#define EFUSE_RXIQ_0_M  (EFUSE_RXIQ_0_V << EFUSE_RXIQ_0_S)
+#define EFUSE_RXIQ_0_V  0x0000007FU
+#define EFUSE_RXIQ_0_S  3
+/** EFUSE_RXIQ_1 : RO; bitpos: [16:10]; default: 0;
+ *  Stores RF Calibration data. RXIQ data 1.
+ */
+#define EFUSE_RXIQ_1    0x0000007FU
+#define EFUSE_RXIQ_1_M  (EFUSE_RXIQ_1_V << EFUSE_RXIQ_1_S)
+#define EFUSE_RXIQ_1_V  0x0000007FU
+#define EFUSE_RXIQ_1_S  10
+/** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [21:17]; default: 0;
+ *  Stores the PMU active hp dbias.
+ */
+#define EFUSE_ACTIVE_HP_DBIAS    0x0000001FU
+#define EFUSE_ACTIVE_HP_DBIAS_M  (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
+#define EFUSE_ACTIVE_HP_DBIAS_V  0x0000001FU
+#define EFUSE_ACTIVE_HP_DBIAS_S  17
+/** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [26:22]; default: 0;
+ *  Stores the PMU active lp dbias.
+ */
+#define EFUSE_ACTIVE_LP_DBIAS    0x0000001FU
+#define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
+#define EFUSE_ACTIVE_LP_DBIAS_V  0x0000001FU
+#define EFUSE_ACTIVE_LP_DBIAS_S  22
+/** EFUSE_DSLP_DBIAS : RO; bitpos: [30:27]; default: 0;
+ *  Stores the PMU sleep dbias.
+ */
+#define EFUSE_DSLP_DBIAS    0x0000000FU
+#define EFUSE_DSLP_DBIAS_M  (EFUSE_DSLP_DBIAS_V << EFUSE_DSLP_DBIAS_S)
+#define EFUSE_DSLP_DBIAS_V  0x0000000FU
+#define EFUSE_DSLP_DBIAS_S  27
+/** EFUSE_DBIAS_VOL_GAP_VALUE1 : RO; bitpos: [31]; default: 0;
+ *  Stores the low 1 bit of dbias_vol_gap.
+ */
+#define EFUSE_DBIAS_VOL_GAP_VALUE1    (BIT(31))
+#define EFUSE_DBIAS_VOL_GAP_VALUE1_M  (EFUSE_DBIAS_VOL_GAP_VALUE1_V << EFUSE_DBIAS_VOL_GAP_VALUE1_S)
+#define EFUSE_DBIAS_VOL_GAP_VALUE1_V  0x00000001U
+#define EFUSE_DBIAS_VOL_GAP_VALUE1_S  31
+
+/** EFUSE_RD_MAC_SYS_3_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_DBIAS_VOL_GAP_VALUE2 : RO; bitpos: [2:0]; default: 0;
+ *  Stores the high 3 bits of dbias_vol_gap.
+ */
+#define EFUSE_DBIAS_VOL_GAP_VALUE2    0x00000007U
+#define EFUSE_DBIAS_VOL_GAP_VALUE2_M  (EFUSE_DBIAS_VOL_GAP_VALUE2_V << EFUSE_DBIAS_VOL_GAP_VALUE2_S)
+#define EFUSE_DBIAS_VOL_GAP_VALUE2_V  0x00000007U
+#define EFUSE_DBIAS_VOL_GAP_VALUE2_S  0
+/** EFUSE_DBIAS_VOL_GAP_SIGN : RO; bitpos: [3]; default: 0;
+ *  Stores the sign bit of dbias_vol_gap.
+ */
+#define EFUSE_DBIAS_VOL_GAP_SIGN    (BIT(3))
+#define EFUSE_DBIAS_VOL_GAP_SIGN_M  (EFUSE_DBIAS_VOL_GAP_SIGN_V << EFUSE_DBIAS_VOL_GAP_SIGN_S)
+#define EFUSE_DBIAS_VOL_GAP_SIGN_V  0x00000001U
+#define EFUSE_DBIAS_VOL_GAP_SIGN_S  3
+/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:4]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_MAC_RESERVED_2    0x00003FFFU
+#define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
+#define EFUSE_MAC_RESERVED_2_V  0x00003FFFU
+#define EFUSE_MAC_RESERVED_2_S  4
+/** EFUSE_WAFER_VERSION_MINOR : RO; bitpos: [20:18]; default: 0;
+ *  Stores the wafer version minor.
+ */
+#define EFUSE_WAFER_VERSION_MINOR    0x00000007U
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x00000007U
+#define EFUSE_WAFER_VERSION_MINOR_S  18
+/** EFUSE_WAFER_VERSION_MAJOR : RO; bitpos: [22:21]; default: 0;
+ *  Stores the wafer version major.
+ */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  21
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : RO; bitpos: [23]; default: 0;
+ *  Disables check of wafer version major.
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(23))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  23
+/** EFUSE_FLASH_CAP : RO; bitpos: [26:24]; default: 0;
+ *  Stores the flash cap.
+ */
+#define EFUSE_FLASH_CAP    0x00000007U
+#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
+#define EFUSE_FLASH_CAP_V  0x00000007U
+#define EFUSE_FLASH_CAP_S  24
+/** EFUSE_FLASH_TEMP : RO; bitpos: [28:27]; default: 0;
+ *  Stores the flash temp.
+ */
+#define EFUSE_FLASH_TEMP    0x00000003U
+#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
+#define EFUSE_FLASH_TEMP_V  0x00000003U
+#define EFUSE_FLASH_TEMP_S  27
+/** EFUSE_FLASH_VENDOR : RO; bitpos: [31:29]; default: 0;
+ *  Stores the flash vendor.
+ */
+#define EFUSE_FLASH_VENDOR    0x00000007U
+#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
+#define EFUSE_FLASH_VENDOR_V  0x00000007U
+#define EFUSE_FLASH_VENDOR_S  29
+
+/** EFUSE_RD_MAC_SYS_4_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_PKG_VERSION : R; bitpos: [2:0]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  0
+/** EFUSE_RESERVED_1_131 : R; bitpos: [31:3]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_131    0x1FFFFFFFU
+#define EFUSE_RESERVED_1_131_M  (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S)
+#define EFUSE_RESERVED_1_131_V  0x1FFFFFFFU
+#define EFUSE_RESERVED_1_131_S  3
+
+/** EFUSE_RD_MAC_SYS_5_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of the zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_RESERVED_2_128 : R; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_128    0x00000003U
+#define EFUSE_RESERVED_2_128_M  (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
+#define EFUSE_RESERVED_2_128_V  0x00000003U
+#define EFUSE_RESERVED_2_128_S  0
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [4:2]; default: 0;
+ *  BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  2
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [6:5]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  5
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
+/** EFUSE_TEMP_CALIB : R; bitpos: [16:8]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMP_CALIB    0x000001FFU
+#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
+#define EFUSE_TEMP_CALIB_V  0x000001FFU
+#define EFUSE_TEMP_CALIB_S  8
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S  17
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1    0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V  0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S  27
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1    0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V  0x0000001FU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S  0
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S  5
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S  15
+/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0    0x0000007FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_V  0x0000007FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_S  25
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1    0x00000007U
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V  0x00000007U
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S  0
+/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_S  3
+/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_M  (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_S  13
+/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3    0x000001FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_V  0x000001FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_S  23
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1    (BIT(0))
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V  0x00000001U
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S  0
+/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S  1
+/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S  5
+/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S  9
+/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S  13
+/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0;
+ *  ADC1 calibration data
+ */
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S  17
+/** EFUSE_RESERVED_2_245 : R; bitpos: [31:21]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_245    0x000007FFU
+#define EFUSE_RESERVED_2_245_M  (EFUSE_RESERVED_2_245_V << EFUSE_RESERVED_2_245_S)
+#define EFUSE_RESERVED_2_245_V  0x000007FFU
+#define EFUSE_RESERVED_2_245_S  21
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Indicates a programming error of RD_DIS.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_RPT4_RESERVED0_ERR_4 : RO; bitpos: [7]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR_4    (BIT(7))
+#define EFUSE_RPT4_RESERVED0_ERR_4_M  (EFUSE_RPT4_RESERVED0_ERR_4_V << EFUSE_RPT4_RESERVED0_ERR_4_S)
+#define EFUSE_RPT4_RESERVED0_ERR_4_V  0x00000001U
+#define EFUSE_RPT4_RESERVED0_ERR_4_S  7
+/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of DIS_ICACHE.
+ */
+#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
+#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_ICACHE_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  Indicates a programming error of DIS_USB_JTAG.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
+ *  Indicates a programming error of POWERGLITCH_EN.
+ */
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_ERR_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
+ *  Indicates a programming error of DIS_USB_DEVICE.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of DIS_CAN.
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  Indicates a programming error of JTAG_SEL_ENABLE.
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  Indicates a programming error of SOFT_DIS_JTAG.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DIS_PAD_JTAG.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Indicates a programming error of USB_DREFH.
+ */
+#define EFUSE_USB_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
+#define EFUSE_USB_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DREFH_ERR_S  21
+/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
+ *  Indicates a programming error of USB_DREFL.
+ */
+#define EFUSE_USB_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
+#define EFUSE_USB_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DREFL_ERR_S  23
+/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of USB_EXCHG_PINS.
+ */
+#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_ERR_S  25
+/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of VDD_SPI_AS_GPIO.
+ */
+#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
+/** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR_2    0x00000003U
+#define EFUSE_RPT4_RESERVED0_ERR_2_M  (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S)
+#define EFUSE_RPT4_RESERVED0_ERR_2_V  0x00000003U
+#define EFUSE_RPT4_RESERVED0_ERR_2_S  27
+/** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR_1    (BIT(29))
+#define EFUSE_RPT4_RESERVED0_ERR_1_M  (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S)
+#define EFUSE_RPT4_RESERVED0_ERR_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED0_ERR_1_S  29
+/** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR_0    0x00000003U
+#define EFUSE_RPT4_RESERVED0_ERR_0_M  (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S)
+#define EFUSE_RPT4_RESERVED0_ERR_0_V  0x00000003U
+#define EFUSE_RPT4_RESERVED0_ERR_0_S  30
+
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED1_ERR_0    0x0000FFFFU
+#define EFUSE_RPT4_RESERVED1_ERR_0_M  (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S)
+#define EFUSE_RPT4_RESERVED1_ERR_0_V  0x0000FFFFU
+#define EFUSE_RPT4_RESERVED1_ERR_0_S  0
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of WDT_DELAY_SEL.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_0.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_1.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_2.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_3.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_4.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_5.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of SEC_DPA_LEVEL.
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
+/** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_ERR_1    (BIT(18))
+#define EFUSE_RPT4_RESERVED2_ERR_1_M  (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S)
+#define EFUSE_RPT4_RESERVED2_ERR_1_V  0x00000001U
+#define EFUSE_RPT4_RESERVED2_ERR_1_S  18
+/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of CRYPT_DPA_ENABLE.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_EN.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_ERR_0    0x0000003FU
+#define EFUSE_RPT4_RESERVED2_ERR_0_M  (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S)
+#define EFUSE_RPT4_RESERVED2_ERR_0_V  0x0000003FU
+#define EFUSE_RPT4_RESERVED2_ERR_0_S  22
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of FLASH_TPUW.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  Indicates a programming error of DIS_DIRECT_BOOT.
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0;
+ *  Indicates a programming error of UART_PRINT_CHANNEL.
+ */
+#define EFUSE_USB_PRINT_ERR    (BIT(2))
+#define EFUSE_USB_PRINT_ERR_M  (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S)
+#define EFUSE_USB_PRINT_ERR_V  0x00000001U
+#define EFUSE_USB_PRINT_ERR_S  2
+/** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR_5    (BIT(3))
+#define EFUSE_RPT4_RESERVED3_ERR_5_M  (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S)
+#define EFUSE_RPT4_RESERVED3_ERR_5_V  0x00000001U
+#define EFUSE_RPT4_RESERVED3_ERR_5_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of UART_PRINT_CONTROL.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of FORCE_SEND_RESUME.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
+ *  Indicates a programming error of SECURE VERSION.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
+/** EFUSE_HYS_EN_PAD0_ERR : RO; bitpos: [31:26]; default: 0;
+ *  Indicates a programming error of HYS_EN_PAD0.
+ */
+#define EFUSE_HYS_EN_PAD0_ERR    0x0000003FU
+#define EFUSE_HYS_EN_PAD0_ERR_M  (EFUSE_HYS_EN_PAD0_ERR_V << EFUSE_HYS_EN_PAD0_ERR_S)
+#define EFUSE_HYS_EN_PAD0_ERR_V  0x0000003FU
+#define EFUSE_HYS_EN_PAD0_ERR_S  26
+
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
+/** EFUSE_HYS_EN_PAD1_ERR : RO; bitpos: [21:0]; default: 0;
+ *  Indicates a programming error of HYS_EN_PAD1.
+ */
+#define EFUSE_HYS_EN_PAD1_ERR    0x003FFFFFU
+#define EFUSE_HYS_EN_PAD1_ERR_M  (EFUSE_HYS_EN_PAD1_ERR_V << EFUSE_HYS_EN_PAD1_ERR_S)
+#define EFUSE_HYS_EN_PAD1_ERR_V  0x003FFFFFU
+#define EFUSE_HYS_EN_PAD1_ERR_S  0
+/** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_ERR_1    0x00000003U
+#define EFUSE_RPT4_RESERVED4_ERR_1_M  (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S)
+#define EFUSE_RPT4_RESERVED4_ERR_1_V  0x00000003U
+#define EFUSE_RPT4_RESERVED4_ERR_1_S  22
+/** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_ERR_0    0x000000FFU
+#define EFUSE_RPT4_RESERVED4_ERR_0_M  (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S)
+#define EFUSE_RPT4_RESERVED4_ERR_0_V  0x000000FFU
+#define EFUSE_RPT4_RESERVED4_ERR_0_S  24
+
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
+#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
+/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SPI_8M_FAIL    (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
+#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
+#define EFUSE_MAC_SPI_8M_FAIL_S  3
+/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_NUM    0x00000007U
+#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
+#define EFUSE_SYS_PART1_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_NUM_S  4
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+ *  key0 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+ *  key1 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+ *  key2 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+ *  key3 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+ *  key4 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  31
+
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+ *  key5 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART2_FAIL_S  7
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to force enable eFuse register configuration clock signal.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
+ *  Configures which block to use for ECDSA key output.
+ */
+#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
+#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_S  16
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Indicates the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Indicates which block is used for ECDSA key output.
+ */
+#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
+#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_S  20
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
+ *  Configures the waiting time of reading eFuse memory.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
+ *  Configures the active programming time.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to bypass reed solomon correction step.
+ */
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures block number of programming twice operation.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Set this bit to update multi-bit register signals.
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/efuse_struct.h b/components/soc/esp32h2/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..ab4c17e4750
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/efuse_struct.h
@@ -0,0 +1,2433 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: Read Data Register */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled or
+         *  enabled. 1: Disabled. 0 Enabled.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t rd_dis:7;
+        /** rpt4_reserved0_4 : RO; bitpos: [7]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_4:1;
+        /** dis_icache : RO; bitpos: [8]; default: 0;
+         *  Represents whether icache is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_icache:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** powerglitch_en : RO; bitpos: [10]; default: 0;
+         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+         */
+        uint32_t powerglitch_en:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Represents whether SPI0 controller during boot_mode_download is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+         *  enabled.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+         *  enabled.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode). 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
+         *  Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
+         */
+        uint32_t usb_drefh:2;
+        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
+         *  Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
+         */
+        uint32_t usb_drefl:2;
+        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
+         *  Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged.
+         */
+        uint32_t usb_exchg_pins:1;
+        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
+         *  Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not
+         *  functioned.
+         */
+        uint32_t vdd_spi_as_gpio:1;
+        /** rpt4_reserved0_2 : RO; bitpos: [28:27]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_2:2;
+        /** rpt4_reserved0_1 : RO; bitpos: [29]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_1:1;
+        /** rpt4_reserved0_0 : RO; bitpos: [31:30]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_0:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register 2.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved1_1 : RO; bitpos: [15:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved1_1:16;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+         *  selected. 0: not selected.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+         *  1: enabled. Even number of 1: disabled.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register 3.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Represents the purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** ecdsa_force_use_hardware_k : RO; bitpos: [18]; default: 1;
+         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+         *  0: not force used.
+         */
+        uint32_t ecdsa_force_use_hardware_k:1;
+        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
+         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+         */
+        uint32_t crypt_dpa_enable:1;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** rpt4_reserved2_0 : RO; bitpos: [27:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_0:6;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+         *  is 2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register 4.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Set this bit to disable USB-Serial-JTAG print during rom boot.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_5:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+         *  disabled.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Represents the type of UART printing. 00: force enable printing. 01: enable
+         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+         *  at high level. 11: force disable printing.
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [8]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+         *  forced. 0:not forced.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [24:9]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
+         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad0 : RO; bitpos: [31:26]; default: 0;
+         *  Set bits to enable hysteresis function of PAD0~5
+         */
+        uint32_t hys_en_pad0:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register 5.
+ */
+typedef union {
+    struct {
+        /** hys_en_pad1 : RO; bitpos: [21:0]; default: 0;
+         *  Set bits to enable hysteresis function of PAD6~27
+         */
+        uint32_t hys_en_pad1:22;
+        /** rpt4_reserved4_1 : RO; bitpos: [23:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_1:2;
+        /** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_0:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_sys_0 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_0_reg_t;
+
+/** Type of rd_mac_sys_1 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** mac_ext : RO; bitpos: [31:16]; default: 0;
+         *  Stores the extended bits of MAC address.
+         */
+        uint32_t mac_ext:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_1_reg_t;
+
+/** Type of rd_mac_sys_2 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** rxiq_version : RO; bitpos: [2:0]; default: 0;
+         *  Stores RF Calibration data. RXIQ version.
+         */
+        uint32_t rxiq_version:3;
+        /** rxiq_0 : RO; bitpos: [9:3]; default: 0;
+         *  Stores RF Calibration data. RXIQ data 0.
+         */
+        uint32_t rxiq_0:7;
+        /** rxiq_1 : RO; bitpos: [16:10]; default: 0;
+         *  Stores RF Calibration data. RXIQ data 1.
+         */
+        uint32_t rxiq_1:7;
+        /** active_hp_dbias : RO; bitpos: [21:17]; default: 0;
+         *  Stores the PMU active hp dbias.
+         */
+        uint32_t active_hp_dbias:5;
+        /** active_lp_dbias : RO; bitpos: [26:22]; default: 0;
+         *  Stores the PMU active lp dbias.
+         */
+        uint32_t active_lp_dbias:5;
+        /** dslp_dbias : RO; bitpos: [30:27]; default: 0;
+         *  Stores the PMU sleep dbias.
+         */
+        uint32_t dslp_dbias:4;
+        /** dbias_vol_gap_value1 : RO; bitpos: [31]; default: 0;
+         *  Stores the low 1 bit of dbias_vol_gap.
+         */
+        uint32_t dbias_vol_gap_value1:1;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_2_reg_t;
+
+/** Type of rd_mac_sys_3 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** dbias_vol_gap_value2 : RO; bitpos: [2:0]; default: 0;
+         *  Stores the high 3 bits of dbias_vol_gap.
+         */
+        uint32_t dbias_vol_gap_value2:3;
+        /** dbias_vol_gap_sign : RO; bitpos: [3]; default: 0;
+         *  Stores the sign bit of dbias_vol_gap.
+         */
+        uint32_t dbias_vol_gap_sign:1;
+        /** mac_reserved_2 : RO; bitpos: [17:4]; default: 0;
+         *  Reserved.
+         */
+        uint32_t mac_reserved_2:14;
+        /** wafer_version_minor : RO; bitpos: [20:18]; default: 0;
+         *  Stores the wafer version minor.
+         */
+        uint32_t wafer_version_minor:3;
+        /** wafer_version_major : RO; bitpos: [22:21]; default: 0;
+         *  Stores the wafer version major.
+         */
+        uint32_t wafer_version_major:2;
+        /** disable_wafer_version_major : RO; bitpos: [23]; default: 0;
+         *  Disables check of wafer version major.
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** flash_cap : RO; bitpos: [26:24]; default: 0;
+         *  Stores the flash cap.
+         */
+        uint32_t flash_cap:3;
+        /** flash_temp : RO; bitpos: [28:27]; default: 0;
+         *  Stores the flash temp.
+         */
+        uint32_t flash_temp:2;
+        /** flash_vendor : RO; bitpos: [31:29]; default: 0;
+         *  Stores the flash vendor.
+         */
+        uint32_t flash_vendor:3;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_3_reg_t;
+
+/** Type of rd_mac_sys_4 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** pkg_version : R; bitpos: [2:0]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** reserved_1_131 : R; bitpos: [31:3]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_131:29;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_4_reg_t;
+
+/** Type of rd_mac_sys_5 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of the zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** reserved_2_128 : R; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_128:2;
+        /** blk_version_minor : R; bitpos: [4:2]; default: 0;
+         *  BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [6:5]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** temp_calib : R; bitpos: [16:8]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temp_calib:9;
+        /** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten0:10;
+        /** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten1:5;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten1_1:5;
+        /** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten2:10;
+        /** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ave_initcode_atten3:10;
+        /** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten0:7;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten0_1:3;
+        /** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten1:10;
+        /** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten2:10;
+        /** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten3:9;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_hi_dout_atten3_1:1;
+        /** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch0_atten0_initcode_diff:4;
+        /** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch1_atten0_initcode_diff:4;
+        /** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch2_atten0_initcode_diff:4;
+        /** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch3_atten0_initcode_diff:4;
+        /** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0;
+         *  ADC1 calibration data
+         */
+        uint32_t adc1_ch4_atten0_initcode_diff:4;
+        /** reserved_2_245 : R; bitpos: [31:21]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_245:11;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+
+/** Group: Report Register */
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Indicates a programming error of RD_DIS.
+         */
+        uint32_t rd_dis_err:7;
+        /** rpt4_reserved0_err_4 : RO; bitpos: [7]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err_4:1;
+        /** dis_icache_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of DIS_ICACHE.
+         */
+        uint32_t dis_icache_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Indicates a programming error of DIS_USB_JTAG.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
+         *  Indicates a programming error of POWERGLITCH_EN.
+         */
+        uint32_t powerglitch_en_err:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
+         *  Indicates a programming error of DIS_USB_DEVICE.
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of DIS_CAN.
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Indicates a programming error of JTAG_SEL_ENABLE.
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Indicates a programming error of SOFT_DIS_JTAG.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DIS_PAD_JTAG.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  Indicates a programming error of USB_DREFH.
+         */
+        uint32_t usb_drefh_err:2;
+        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
+         *  Indicates a programming error of USB_DREFL.
+         */
+        uint32_t usb_drefl_err:2;
+        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of USB_EXCHG_PINS.
+         */
+        uint32_t usb_exchg_pins_err:1;
+        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of VDD_SPI_AS_GPIO.
+         */
+        uint32_t vdd_spi_as_gpio_err:1;
+        /** rpt4_reserved0_err_2 : RO; bitpos: [28:27]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err_2:2;
+        /** rpt4_reserved0_err_1 : RO; bitpos: [29]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err_1:1;
+        /** rpt4_reserved0_err_0 : RO; bitpos: [31:30]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err_0:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved1_err_0 : RO; bitpos: [15:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved1_err_0:16;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of WDT_DELAY_SEL.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_0.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_1.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_2.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_3.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_4.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_5.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of SEC_DPA_LEVEL.
+         */
+        uint32_t sec_dpa_level_err:2;
+        /** rpt4_reserved2_err_1 : RO; bitpos: [18]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_err_1:1;
+        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of CRYPT_DPA_ENABLE.
+         */
+        uint32_t crypt_dpa_enable_err:1;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_EN.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        /** rpt4_reserved2_err_0 : RO; bitpos: [27:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_err_0:6;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of FLASH_TPUW.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Indicates a programming error of DIS_DIRECT_BOOT.
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** usb_print_err : RO; bitpos: [2]; default: 0;
+         *  Indicates a programming error of UART_PRINT_CHANNEL.
+         */
+        uint32_t usb_print_err:1;
+        /** rpt4_reserved3_err_5 : RO; bitpos: [3]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err_5:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of UART_PRINT_CONTROL.
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of FORCE_SEND_RESUME.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
+         *  Indicates a programming error of SECURE VERSION.
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad0_err : RO; bitpos: [31:26]; default: 0;
+         *  Indicates a programming error of HYS_EN_PAD0.
+         */
+        uint32_t hys_en_pad0_err:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** hys_en_pad1_err : RO; bitpos: [21:0]; default: 0;
+         *  Indicates a programming error of HYS_EN_PAD1.
+         */
+        uint32_t hys_en_pad1_err:22;
+        /** rpt4_reserved4_err_1 : RO; bitpos: [23:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_err_1:2;
+        /** rpt4_reserved4_err_0 : RO; bitpos: [31:24]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_err_0:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_spi_8m_err_num:3;
+        /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_spi_8m_fail:1;
+        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_num:3;
+        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** key0_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+         *  key0 failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key1_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+         *  key1 failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key2_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+         *  key2 failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key3_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+         *  key3 failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key4_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+         *  key4 failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key5_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+         *  key5 failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part2_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
+         *  Configures which block to use for ECDSA key output.
+         */
+        uint32_t cfg_ecdsa_blk:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 160;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
+         *  Indicates which block is used for ECDSA key output.
+         */
+        uint32_t cur_ecdsa_blk:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35684640;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
+    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
+    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
+    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
+    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
+    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_190[12];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    volatile efuse_date_reg_t date;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/extmem_reg.h b/components/soc/esp32h2/register/soc/extmem_reg.h
new file mode 100644
index 00000000000..c277ae582c2
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/extmem_reg.h
@@ -0,0 +1,971 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_CACHE_REG_H_
+#define _SOC_CACHE_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+#define CACHE_L1_CACHE_CTRL_REG          (DR_REG_CACHE_BASE + 0x4)
+/* CACHE_L1_CACHE_SHUT_BUS1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable.*/
+#define CACHE_L1_CACHE_SHUT_BUS1    (BIT(1))
+#define CACHE_L1_CACHE_SHUT_BUS1_M  (BIT(1))
+#define CACHE_L1_CACHE_SHUT_BUS1_V  0x1
+#define CACHE_L1_CACHE_SHUT_BUS1_S  1
+/* CACHE_L1_CACHE_SHUT_BUS0 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable.*/
+#define CACHE_L1_CACHE_SHUT_BUS0    (BIT(0))
+#define CACHE_L1_CACHE_SHUT_BUS0_M  (BIT(0))
+#define CACHE_L1_CACHE_SHUT_BUS0_V  0x1
+#define CACHE_L1_CACHE_SHUT_BUS0_S  0
+
+#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_CACHE_BASE + 0x20)
+/* CACHE_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: Set this bit as 1 to enable L1-DCache wrap around mode..*/
+#define CACHE_L1_CACHE_WRAP    (BIT(4))
+#define CACHE_L1_CACHE_WRAP_M  (BIT(4))
+#define CACHE_L1_CACHE_WRAP_V  0x1
+#define CACHE_L1_CACHE_WRAP_S  4
+
+#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG          (DR_REG_CACHE_BASE + 0x24)
+/* CACHE_L1_CACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
+/*description: The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up.*/
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_M  (BIT(18))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_V  0x1
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PU_S  18
+/* CACHE_L1_CACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power
+down.*/
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_M  (BIT(17))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_V  0x1
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_PD_S  17
+/* CACHE_L1_CACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating,
+0: open clock gating..*/
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_M  (BIT(16))
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_V  0x1
+#define CACHE_L1_CACHE_TAG_MEM_FORCE_ON_S  16
+
+#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG          (DR_REG_CACHE_BASE + 0x28)
+/* CACHE_L1_CACHE_DATA_MEM_FORCE_PU : R/W ;bitpos:[18] ;default: 1'h1 ; */
+/*description: The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power u
+p.*/
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_M  (BIT(18))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_V  0x1
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PU_S  18
+/* CACHE_L1_CACHE_DATA_MEM_FORCE_PD : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
+ down.*/
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_M  (BIT(17))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_V  0x1
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_PD_S  17
+/* CACHE_L1_CACHE_DATA_MEM_FORCE_ON : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to close clock gating of  L1-Cache data memory. 1: close gating,
+ 0: open clock gating..*/
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_M  (BIT(16))
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_V  0x1
+#define CACHE_L1_CACHE_DATA_MEM_FORCE_ON_S  16
+
+#define CACHE_L1_CACHE_FREEZE_CTRL_REG          (DR_REG_CACHE_BASE + 0x2C)
+/* CACHE_L1_CACHE_FREEZE_DONE : RO ;bitpos:[18] ;default: 1'h0 ; */
+/*description: The bit is used to indicate whether freeze operation on L1-Cache is finished or
+not. 0: not finished. 1: finished..*/
+#define CACHE_L1_CACHE_FREEZE_DONE    (BIT(18))
+#define CACHE_L1_CACHE_FREEZE_DONE_M  (BIT(18))
+#define CACHE_L1_CACHE_FREEZE_DONE_V  0x1
+#define CACHE_L1_CACHE_FREEZE_DONE_S  18
+/* CACHE_L1_CACHE_FREEZE_MODE : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+ will not stuck. 1: a miss-access will stuck..*/
+#define CACHE_L1_CACHE_FREEZE_MODE    (BIT(17))
+#define CACHE_L1_CACHE_FREEZE_MODE_M  (BIT(17))
+#define CACHE_L1_CACHE_FREEZE_MODE_V  0x1
+#define CACHE_L1_CACHE_FREEZE_MODE_S  17
+/* CACHE_L1_CACHE_FREEZE_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by sof
+tware..*/
+#define CACHE_L1_CACHE_FREEZE_EN    (BIT(16))
+#define CACHE_L1_CACHE_FREEZE_EN_M  (BIT(16))
+#define CACHE_L1_CACHE_FREEZE_EN_V  0x1
+#define CACHE_L1_CACHE_FREEZE_EN_S  16
+
+#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG          (DR_REG_CACHE_BASE + 0x30)
+/* CACHE_L1_CACHE_DATA_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable,
+1: enable..*/
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_M  (BIT(17))
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_V  0x1
+#define CACHE_L1_CACHE_DATA_MEM_WR_EN_S  17
+/* CACHE_L1_CACHE_DATA_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1
+: enable..*/
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_M  (BIT(16))
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_V  0x1
+#define CACHE_L1_CACHE_DATA_MEM_RD_EN_S  16
+
+#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG          (DR_REG_CACHE_BASE + 0x34)
+/* CACHE_L1_CACHE_TAG_MEM_WR_EN : R/W ;bitpos:[17] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1
+: enable..*/
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_M  (BIT(17))
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_V  0x1
+#define CACHE_L1_CACHE_TAG_MEM_WR_EN_S  17
+/* CACHE_L1_CACHE_TAG_MEM_RD_EN : R/W ;bitpos:[16] ;default: 1'h1 ; */
+/*description: The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+ enable..*/
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_M  (BIT(16))
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_V  0x1
+#define CACHE_L1_CACHE_TAG_MEM_RD_EN_S  16
+
+#define CACHE_L1_CACHE_PRELOCK_CONF_REG          (DR_REG_CACHE_BASE + 0x78)
+/* CACHE_L1_CACHE_PRELOCK_RGID : HRO ;bitpos:[5:2] ;default: 4'h0 ; */
+/*description: The bit is used to set  the gid of l1 cache prelock..*/
+#define CACHE_L1_CACHE_PRELOCK_RGID    0x0000000F
+#define CACHE_L1_CACHE_PRELOCK_RGID_M  ((CACHE_L1_CACHE_PRELOCK_RGID_V)<<(CACHE_L1_CACHE_PRELOCK_RGID_S))
+#define CACHE_L1_CACHE_PRELOCK_RGID_V  0xF
+#define CACHE_L1_CACHE_PRELOCK_RGID_S  2
+/* CACHE_L1_CACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section of prelock function on L1-Cache..*/
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_M  (BIT(1))
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_V  0x1
+#define CACHE_L1_CACHE_PRELOCK_SCT1_EN_S  1
+/* CACHE_L1_CACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section of prelock function on L1-Cache..*/
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_M  (BIT(0))
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_V  0x1
+#define CACHE_L1_CACHE_PRELOCK_SCT0_EN_S  0
+
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_CACHE_BASE + 0x7C)
+/* CACHE_L1_CACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the first section
+of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0
+_SIZE_REG.*/
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_M  ((CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V)<<(CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S))
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_CACHE_BASE + 0x80)
+/* CACHE_L1_CACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the second section
+ of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT
+1_SIZE_REG.*/
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_M  ((CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V)<<(CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S))
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+#define CACHE_L1_CACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_CACHE_BASE + 0x84)
+/* CACHE_L1_CACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[29:16] ;default: 14'h3fff ; */
+/*description: Those bits are used to configure the size of the second section of prelock on L1
+-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG.*/
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE    0x00003FFF
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_M  ((CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V)<<(CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S))
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_V  0x3FFF
+#define CACHE_L1_CACHE_PRELOCK_SCT1_SIZE_S  16
+/* CACHE_L1_CACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h3fff ; */
+/*description: Those bits are used to configure the size of the first section of prelock on L1-
+Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG.*/
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE    0x00003FFF
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_M  ((CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V)<<(CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S))
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_V  0x3FFF
+#define CACHE_L1_CACHE_PRELOCK_SCT0_SIZE_S  0
+
+#define CACHE_LOCK_CTRL_REG          (DR_REG_CACHE_BASE + 0x88)
+/* CACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+ not finished. 1: finished..*/
+#define CACHE_LOCK_DONE    (BIT(2))
+#define CACHE_LOCK_DONE_M  (BIT(2))
+#define CACHE_LOCK_DONE_V  0x1
+#define CACHE_LOCK_DONE_S  2
+/* CACHE_UNLOCK_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
+ unlock operation done.*/
+#define CACHE_UNLOCK_ENA    (BIT(1))
+#define CACHE_UNLOCK_ENA_M  (BIT(1))
+#define CACHE_UNLOCK_ENA_V  0x1
+#define CACHE_UNLOCK_ENA_S  1
+/* CACHE_LOCK_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
+ock operation done.*/
+#define CACHE_LOCK_ENA    (BIT(0))
+#define CACHE_LOCK_ENA_M  (BIT(0))
+#define CACHE_LOCK_ENA_V  0x1
+#define CACHE_LOCK_ENA_S  0
+
+#define CACHE_LOCK_MAP_REG          (DR_REG_CACHE_BASE + 0x8C)
+/* CACHE_LOCK_MAP : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: Those bits are used to indicate which caches in the two-level cache structure wi
+ll apply this lock/unlock operation. [4]: L1-Cache.*/
+#define CACHE_LOCK_MAP    0x0000003F
+#define CACHE_LOCK_MAP_M  ((CACHE_LOCK_MAP_V)<<(CACHE_LOCK_MAP_S))
+#define CACHE_LOCK_MAP_V  0x3F
+#define CACHE_LOCK_MAP_S  0
+
+#define CACHE_LOCK_ADDR_REG          (DR_REG_CACHE_BASE + 0x90)
+/* CACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the lock/unlock op
+eration, which should be used together with CACHE_LOCK_SIZE_REG.*/
+#define CACHE_LOCK_ADDR    0xFFFFFFFF
+#define CACHE_LOCK_ADDR_M  ((CACHE_LOCK_ADDR_V)<<(CACHE_LOCK_ADDR_S))
+#define CACHE_LOCK_ADDR_V  0xFFFFFFFF
+#define CACHE_LOCK_ADDR_S  0
+
+#define CACHE_LOCK_SIZE_REG          (DR_REG_CACHE_BASE + 0x94)
+/* CACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: Those bits are used to configure the size of the lock/unlock operation, which sh
+ould be used together with CACHE_LOCK_ADDR_REG.*/
+#define CACHE_LOCK_SIZE    0x0000FFFF
+#define CACHE_LOCK_SIZE_M  ((CACHE_LOCK_SIZE_V)<<(CACHE_LOCK_SIZE_S))
+#define CACHE_LOCK_SIZE_V  0xFFFF
+#define CACHE_LOCK_SIZE_S  0
+
+#define CACHE_SYNC_CTRL_REG          (DR_REG_CACHE_BASE + 0x98)
+/* CACHE_SYNC_DONE : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The bit is used to indicate whether sync operation (invalidate, clean, writeback
+, writeback_invalidate) is finished or not. 0: not finished. 1: finished..*/
+#define CACHE_SYNC_DONE    (BIT(4))
+#define CACHE_SYNC_DONE_M  (BIT(4))
+#define CACHE_SYNC_DONE_V  0x1
+#define CACHE_SYNC_DONE_S  4
+/* CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The bit is used to enable writeback-invalidate operation. It will be cleared by
+hardware after writeback-invalidate operation done. Note that this bit and the
+other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive
+, that is, those bits can not be set to 1 at the same time..*/
+#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (BIT(3))
+#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x1
+#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/* CACHE_WRITEBACK_ENA : R/W/SC ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
+ter writeback operation done. Note that this bit and the other sync-bits (invali
+date_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+those bits can not be set to 1 at the same time..*/
+#define CACHE_WRITEBACK_ENA    (BIT(2))
+#define CACHE_WRITEBACK_ENA_M  (BIT(2))
+#define CACHE_WRITEBACK_ENA_V  0x1
+#define CACHE_WRITEBACK_ENA_S  2
+/* CACHE_CLEAN_ENA : R/W/SC ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable clean operation. It will be cleared by hardware after
+clean operation done. Note that this bit and the other sync-bits (invalidate_ena
+, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+bits can not be set to 1 at the same time..*/
+#define CACHE_CLEAN_ENA    (BIT(1))
+#define CACHE_CLEAN_ENA_M  (BIT(1))
+#define CACHE_CLEAN_ENA_V  0x1
+#define CACHE_CLEAN_ENA_S  1
+/* CACHE_INVALIDATE_ENA : R/W/SC ;bitpos:[0] ;default: 1'h1 ; */
+/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
+after invalidate operation done. Note that this bit and the other sync-bits (clean_ena,
+writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is,
+ those bits can not be set to 1 at the same time..*/
+#define CACHE_INVALIDATE_ENA    (BIT(0))
+#define CACHE_INVALIDATE_ENA_M  (BIT(0))
+#define CACHE_INVALIDATE_ENA_V  0x1
+#define CACHE_INVALIDATE_ENA_S  0
+
+#define CACHE_SYNC_MAP_REG          (DR_REG_CACHE_BASE + 0x9C)
+/* CACHE_SYNC_MAP : R/W ;bitpos:[5:0] ;default: 6'h3f ; */
+/*description: Those bits are used to indicate which caches in the two-level cache structure wi
+ll apply the sync operation.  [4]: L1-Cache.*/
+#define CACHE_SYNC_MAP    0x0000003F
+#define CACHE_SYNC_MAP_M  ((CACHE_SYNC_MAP_V)<<(CACHE_SYNC_MAP_S))
+#define CACHE_SYNC_MAP_V  0x3F
+#define CACHE_SYNC_MAP_S  0
+
+#define CACHE_SYNC_ADDR_REG          (DR_REG_CACHE_BASE + 0xA0)
+/* CACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the sync operation
+, which should be used together with CACHE_SYNC_SIZE_REG.*/
+#define CACHE_SYNC_ADDR    0xFFFFFFFF
+#define CACHE_SYNC_ADDR_M  ((CACHE_SYNC_ADDR_V)<<(CACHE_SYNC_ADDR_S))
+#define CACHE_SYNC_ADDR_V  0xFFFFFFFF
+#define CACHE_SYNC_ADDR_S  0
+
+#define CACHE_SYNC_SIZE_REG          (DR_REG_CACHE_BASE + 0xA4)
+/* CACHE_SYNC_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Those bits are used to configure the size of the sync operation, which should be
+ used together with CACHE_SYNC_ADDR_REG.*/
+#define CACHE_SYNC_SIZE    0x00FFFFFF
+#define CACHE_SYNC_SIZE_M  ((CACHE_SYNC_SIZE_V)<<(CACHE_SYNC_SIZE_S))
+#define CACHE_SYNC_SIZE_V  0xFFFFFF
+#define CACHE_SYNC_SIZE_S  0
+
+#define CACHE_L1_CACHE_PRELOAD_CTRL_REG          (DR_REG_CACHE_BASE + 0xD8)
+/* CACHE_L1_CACHE_PRELOAD_RGID : HRO ;bitpos:[6:3] ;default: 4'h0 ; */
+/*description: The bit is used to set  the gid of l1 cache preload..*/
+#define CACHE_L1_CACHE_PRELOAD_RGID    0x0000000F
+#define CACHE_L1_CACHE_PRELOAD_RGID_M  ((CACHE_L1_CACHE_PRELOAD_RGID_V)<<(CACHE_L1_CACHE_PRELOAD_RGID_S))
+#define CACHE_L1_CACHE_PRELOAD_RGID_V  0xF
+#define CACHE_L1_CACHE_PRELOAD_RGID_S  3
+/* CACHE_L1_CACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to configure the direction of preload operation. 0: ascending, 1
+: descending..*/
+#define CACHE_L1_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_CACHE_PRELOAD_ORDER_M  (BIT(2))
+#define CACHE_L1_CACHE_PRELOAD_ORDER_V  0x1
+#define CACHE_L1_CACHE_PRELOAD_ORDER_S  2
+/* CACHE_L1_CACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether preload operation is finished or not. 0: not
+ finished. 1: finished..*/
+#define CACHE_L1_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_CACHE_PRELOAD_DONE_M  (BIT(1))
+#define CACHE_L1_CACHE_PRELOAD_DONE_V  0x1
+#define CACHE_L1_CACHE_PRELOAD_DONE_S  1
+/* CACHE_L1_CACHE_PRELOAD_ENA : R/W/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable preload operation on L1-Cache. It will be cleared by h
+ardware automatically after preload operation is done..*/
+#define CACHE_L1_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_CACHE_PRELOAD_ENA_M  (BIT(0))
+#define CACHE_L1_CACHE_PRELOAD_ENA_V  0x1
+#define CACHE_L1_CACHE_PRELOAD_ENA_S  0
+
+#define CACHE_L1_CACHE_PRELOAD_ADDR_REG          (DR_REG_CACHE_BASE + 0xDC)
+/* CACHE_L1_CACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of preload on L1-Cach
+e, which should be used together with L1_CACHE_PRELOAD_SIZE_REG.*/
+#define CACHE_L1_CACHE_PRELOAD_ADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_PRELOAD_ADDR_M  ((CACHE_L1_CACHE_PRELOAD_ADDR_V)<<(CACHE_L1_CACHE_PRELOAD_ADDR_S))
+#define CACHE_L1_CACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_PRELOAD_ADDR_S  0
+
+#define CACHE_L1_CACHE_PRELOAD_SIZE_REG          (DR_REG_CACHE_BASE + 0xE0)
+/* CACHE_L1_CACHE_PRELOAD_SIZE : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: Those bits are used to configure the size of the first section of prelock on L1-
+Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG.*/
+#define CACHE_L1_CACHE_PRELOAD_SIZE    0x00003FFF
+#define CACHE_L1_CACHE_PRELOAD_SIZE_M  ((CACHE_L1_CACHE_PRELOAD_SIZE_V)<<(CACHE_L1_CACHE_PRELOAD_SIZE_S))
+#define CACHE_L1_CACHE_PRELOAD_SIZE_V  0x3FFF
+#define CACHE_L1_CACHE_PRELOAD_SIZE_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_CTRL_REG          (DR_REG_CACHE_BASE + 0x134)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section for autoload operation on L1-Cache..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_M  (BIT(9))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_V  0x1
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/* CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section for autoload operation on L1-Cache..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_M  (BIT(8))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_V  0x1
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/* CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: The field is used to configure trigger mode of autoload operation on L1-Cache. 0
+/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger..*/
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_M  ((CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V)<<(CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S))
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x3
+#define CACHE_L1_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/* CACHE_L1_CACHE_AUTOLOAD_ORDER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+ ascending. 1: descending..*/
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_M  (BIT(2))
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_V  0x1
+#define CACHE_L1_CACHE_AUTOLOAD_ORDER_S  2
+/* CACHE_L1_CACHE_AUTOLOAD_DONE : RO ;bitpos:[1] ;default: 1'h1 ; */
+/*description: The bit is used to indicate whether autoload operation on L1-Cache is finished o
+r not. 0: not finished. 1: finished..*/
+#define CACHE_L1_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_M  (BIT(1))
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_V  0x1
+#define CACHE_L1_CACHE_AUTOLOAD_DONE_S  1
+/* CACHE_L1_CACHE_AUTOLOAD_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable and disable autoload operation on L1-Cache.  1: enable
+, 0: disable..*/
+#define CACHE_L1_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_M  (BIT(0))
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_V  0x1
+#define CACHE_L1_CACHE_AUTOLOAD_ENA_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_CACHE_BASE + 0x138)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the first section
+for autoload operation on L1-Cache. Note that it should be used together with L1
+_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_CACHE_BASE + 0x13C)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Those bits are used to configure the size of the first section for autoload oper
+ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
+CT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE    0x00FFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_CACHE_BASE + 0x140)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the second section
+ for autoload operation on L1-Cache. Note that it should be used together with L
+1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_CACHE_BASE + 0x144)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Those bits are used to configure the size of the second section for autoload ope
+ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
+SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE    0x00FFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_REG          (DR_REG_CACHE_BASE + 0x148)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR : HRO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the third section
+for autoload operation on L1-Cache. Note that it should be used together with L1
+_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_REG          (DR_REG_CACHE_BASE + 0x14C)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE : HRO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Those bits are used to configure the size of the third section for autoload oper
+ation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_S
+CT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE    0x00FFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_V  0xFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_REG          (DR_REG_CACHE_BASE + 0x150)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR : HRO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are used to configure the start virtual address of the fourth section
+ for autoload operation on L1-Cache. Note that it should be used together with L
+1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_REG          (DR_REG_CACHE_BASE + 0x154)
+/* CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE : HRO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Those bits are used to configure the size of the fourth section for autoload ope
+ration on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_
+SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA..*/
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE    0x00FFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_M  ((CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V)<<(CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S))
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_V  0xFFFFFF
+#define CACHE_L1_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG          (DR_REG_CACHE_BASE + 0x158)
+/* CACHE_L1_BUS1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
+1-DCache due to bus1 accesses L1-DCache..*/
+#define CACHE_L1_BUS1_OVF_INT_ENA    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_ENA_M  (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_ENA_V  0x1
+#define CACHE_L1_BUS1_OVF_INT_ENA_S  5
+/* CACHE_L1_BUS0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of one of counters overflow that occurs in L
+1-DCache due to bus0 accesses L1-DCache..*/
+#define CACHE_L1_BUS0_OVF_INT_ENA    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_ENA_M  (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_ENA_V  0x1
+#define CACHE_L1_BUS0_OVF_INT_ENA_S  4
+
+#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG          (DR_REG_CACHE_BASE + 0x15C)
+/* CACHE_L1_BUS1_OVF_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache
+due to bus1 accesses L1-DCache..*/
+#define CACHE_L1_BUS1_OVF_INT_CLR    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_CLR_M  (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_CLR_V  0x1
+#define CACHE_L1_BUS1_OVF_INT_CLR_S  5
+/* CACHE_L1_BUS0_OVF_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear counters overflow interrupt and counters in L1-DCache
+due to bus0 accesses L1-DCache..*/
+#define CACHE_L1_BUS0_OVF_INT_CLR    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_CLR_M  (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_CLR_V  0x1
+#define CACHE_L1_BUS0_OVF_INT_CLR_S  4
+
+#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG          (DR_REG_CACHE_BASE + 0x160)
+/* CACHE_L1_BUS1_OVF_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
+e due to bus1 accesses L1-DCache..*/
+#define CACHE_L1_BUS1_OVF_INT_RAW    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_RAW_M  (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_RAW_V  0x1
+#define CACHE_L1_BUS1_OVF_INT_RAW_S  5
+/* CACHE_L1_BUS0_OVF_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCach
+e due to bus0 accesses L1-DCache..*/
+#define CACHE_L1_BUS0_OVF_INT_RAW    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_RAW_M  (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_RAW_V  0x1
+#define CACHE_L1_BUS0_OVF_INT_RAW_S  4
+
+#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG          (DR_REG_CACHE_BASE + 0x164)
+/* CACHE_L1_BUS1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
+n L1-DCache due to bus1 accesses L1-DCache..*/
+#define CACHE_L1_BUS1_OVF_INT_ST    (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_ST_M  (BIT(5))
+#define CACHE_L1_BUS1_OVF_INT_ST_V  0x1
+#define CACHE_L1_BUS1_OVF_INT_ST_S  5
+/* CACHE_L1_BUS0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of one of counters overflow that occurs i
+n L1-DCache due to bus0 accesses L1-DCache..*/
+#define CACHE_L1_BUS0_OVF_INT_ST    (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_ST_M  (BIT(4))
+#define CACHE_L1_BUS0_OVF_INT_ST_V  0x1
+#define CACHE_L1_BUS0_OVF_INT_ST_S  4
+
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG          (DR_REG_CACHE_BASE + 0x168)
+/* CACHE_L1_CACHE_FAIL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due
+to cpu accesses L1-DCache..*/
+#define CACHE_L1_CACHE_FAIL_INT_ENA    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_ENA_M  (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_ENA_V  0x1
+#define CACHE_L1_CACHE_FAIL_INT_ENA_S  4
+
+#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG          (DR_REG_CACHE_BASE + 0x16C)
+/* CACHE_L1_CACHE_FAIL_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due t
+o cpu accesses L1-DCache..*/
+#define CACHE_L1_CACHE_FAIL_INT_CLR    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_CLR_M  (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_CLR_V  0x1
+#define CACHE_L1_CACHE_FAIL_INT_CLR_S  4
+
+#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG          (DR_REG_CACHE_BASE + 0x170)
+/* CACHE_L1_CACHE_FAIL_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt of access fail that occurs in L1-DCache..*/
+#define CACHE_L1_CACHE_FAIL_INT_RAW    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_RAW_M  (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_RAW_V  0x1
+#define CACHE_L1_CACHE_FAIL_INT_RAW_S  4
+
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG          (DR_REG_CACHE_BASE + 0x174)
+/* CACHE_L1_CACHE_FAIL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the interrupt status of access fail that occurs in L1-DCache
+due to cpu accesses L1-DCache..*/
+#define CACHE_L1_CACHE_FAIL_INT_ST    (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_ST_M  (BIT(4))
+#define CACHE_L1_CACHE_FAIL_INT_ST_V  0x1
+#define CACHE_L1_CACHE_FAIL_INT_ST_S  4
+
+#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG          (DR_REG_CACHE_BASE + 0x178)
+/* CACHE_L1_BUS1_CNT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus1 counter in L1-DCache..*/
+#define CACHE_L1_BUS1_CNT_CLR    (BIT(21))
+#define CACHE_L1_BUS1_CNT_CLR_M  (BIT(21))
+#define CACHE_L1_BUS1_CNT_CLR_V  0x1
+#define CACHE_L1_BUS1_CNT_CLR_S  21
+/* CACHE_L1_BUS0_CNT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The bit is used to clear dbus0 counter in L1-DCache..*/
+#define CACHE_L1_BUS0_CNT_CLR    (BIT(20))
+#define CACHE_L1_BUS0_CNT_CLR_M  (BIT(20))
+#define CACHE_L1_BUS0_CNT_CLR_V  0x1
+#define CACHE_L1_BUS0_CNT_CLR_S  20
+/* CACHE_L1_BUS1_CNT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable dbus1 counter in L1-DCache..*/
+#define CACHE_L1_BUS1_CNT_ENA    (BIT(5))
+#define CACHE_L1_BUS1_CNT_ENA_M  (BIT(5))
+#define CACHE_L1_BUS1_CNT_ENA_V  0x1
+#define CACHE_L1_BUS1_CNT_ENA_S  5
+/* CACHE_L1_BUS0_CNT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable dbus0 counter in L1-DCache..*/
+#define CACHE_L1_BUS0_CNT_ENA    (BIT(4))
+#define CACHE_L1_BUS0_CNT_ENA_M  (BIT(4))
+#define CACHE_L1_BUS0_CNT_ENA_V  0x1
+#define CACHE_L1_BUS0_CNT_ENA_S  4
+
+#define CACHE_L1_BUS0_ACS_HIT_CNT_REG          (DR_REG_CACHE_BASE + 0x1BC)
+/* CACHE_L1_BUS0_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of hits when bus0 accesses L1-Cache..*/
+#define CACHE_L1_BUS0_HIT_CNT    0xFFFFFFFF
+#define CACHE_L1_BUS0_HIT_CNT_M  ((CACHE_L1_BUS0_HIT_CNT_V)<<(CACHE_L1_BUS0_HIT_CNT_S))
+#define CACHE_L1_BUS0_HIT_CNT_V  0xFFFFFFFF
+#define CACHE_L1_BUS0_HIT_CNT_S  0
+
+#define CACHE_L1_BUS0_ACS_MISS_CNT_REG          (DR_REG_CACHE_BASE + 0x1C0)
+/* CACHE_L1_BUS0_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of missing when bus0 accesses L1-Cache..*/
+#define CACHE_L1_BUS0_MISS_CNT    0xFFFFFFFF
+#define CACHE_L1_BUS0_MISS_CNT_M  ((CACHE_L1_BUS0_MISS_CNT_V)<<(CACHE_L1_BUS0_MISS_CNT_S))
+#define CACHE_L1_BUS0_MISS_CNT_V  0xFFFFFFFF
+#define CACHE_L1_BUS0_MISS_CNT_S  0
+
+#define CACHE_L1_BUS0_ACS_CONFLICT_CNT_REG          (DR_REG_CACHE_BASE + 0x1C4)
+/* CACHE_L1_BUS0_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of access-conflicts when bus0 accesses L1-Cache..*/
+#define CACHE_L1_BUS0_CONFLICT_CNT    0xFFFFFFFF
+#define CACHE_L1_BUS0_CONFLICT_CNT_M  ((CACHE_L1_BUS0_CONFLICT_CNT_V)<<(CACHE_L1_BUS0_CONFLICT_CNT_S))
+#define CACHE_L1_BUS0_CONFLICT_CNT_V  0xFFFFFFFF
+#define CACHE_L1_BUS0_CONFLICT_CNT_S  0
+
+#define CACHE_L1_BUS0_ACS_NXTLVL_CNT_REG          (DR_REG_CACHE_BASE + 0x1C8)
+/* CACHE_L1_BUS0_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
+bus0 accessing L1-Cache..*/
+#define CACHE_L1_BUS0_NXTLVL_CNT    0xFFFFFFFF
+#define CACHE_L1_BUS0_NXTLVL_CNT_M  ((CACHE_L1_BUS0_NXTLVL_CNT_V)<<(CACHE_L1_BUS0_NXTLVL_CNT_S))
+#define CACHE_L1_BUS0_NXTLVL_CNT_V  0xFFFFFFFF
+#define CACHE_L1_BUS0_NXTLVL_CNT_S  0
+
+#define CACHE_L1_BUS1_ACS_HIT_CNT_REG          (DR_REG_CACHE_BASE + 0x1CC)
+/* CACHE_L1_BUS1_HIT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of hits when bus1 accesses L1-Cache..*/
+#define CACHE_L1_BUS1_HIT_CNT    0xFFFFFFFF
+#define CACHE_L1_BUS1_HIT_CNT_M  ((CACHE_L1_BUS1_HIT_CNT_V)<<(CACHE_L1_BUS1_HIT_CNT_S))
+#define CACHE_L1_BUS1_HIT_CNT_V  0xFFFFFFFF
+#define CACHE_L1_BUS1_HIT_CNT_S  0
+
+#define CACHE_L1_BUS1_ACS_MISS_CNT_REG          (DR_REG_CACHE_BASE + 0x1D0)
+/* CACHE_L1_BUS1_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of missing when bus1 accesses L1-Cache..*/
+#define CACHE_L1_BUS1_MISS_CNT    0xFFFFFFFF
+#define CACHE_L1_BUS1_MISS_CNT_M  ((CACHE_L1_BUS1_MISS_CNT_V)<<(CACHE_L1_BUS1_MISS_CNT_S))
+#define CACHE_L1_BUS1_MISS_CNT_V  0xFFFFFFFF
+#define CACHE_L1_BUS1_MISS_CNT_S  0
+
+#define CACHE_L1_BUS1_ACS_CONFLICT_CNT_REG          (DR_REG_CACHE_BASE + 0x1D4)
+/* CACHE_L1_BUS1_CONFLICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of access-conflicts when bus1 accesses L1-Cache..*/
+#define CACHE_L1_BUS1_CONFLICT_CNT    0xFFFFFFFF
+#define CACHE_L1_BUS1_CONFLICT_CNT_M  ((CACHE_L1_BUS1_CONFLICT_CNT_V)<<(CACHE_L1_BUS1_CONFLICT_CNT_S))
+#define CACHE_L1_BUS1_CONFLICT_CNT_V  0xFFFFFFFF
+#define CACHE_L1_BUS1_CONFLICT_CNT_S  0
+
+#define CACHE_L1_BUS1_ACS_NXTLVL_CNT_REG          (DR_REG_CACHE_BASE + 0x1D8)
+/* CACHE_L1_BUS1_NXTLVL_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the number of times that L1-Cache accesses L2-Cache due to
+bus1 accessing L1-Cache..*/
+#define CACHE_L1_BUS1_NXTLVL_CNT    0xFFFFFFFF
+#define CACHE_L1_BUS1_NXTLVL_CNT_M  ((CACHE_L1_BUS1_NXTLVL_CNT_V)<<(CACHE_L1_BUS1_NXTLVL_CNT_S))
+#define CACHE_L1_BUS1_NXTLVL_CNT_V  0xFFFFFFFF
+#define CACHE_L1_BUS1_NXTLVL_CNT_S  0
+
+#define CACHE_L1_CACHE_ACS_FAIL_ID_ATTR_REG          (DR_REG_CACHE_BASE + 0x21C)
+/* CACHE_L1_CACHE_FAIL_ATTR : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: The register records the attribution of fail-access when cache accesses L1-Cache
+..*/
+#define CACHE_L1_CACHE_FAIL_ATTR    0x0000FFFF
+#define CACHE_L1_CACHE_FAIL_ATTR_M  ((CACHE_L1_CACHE_FAIL_ATTR_V)<<(CACHE_L1_CACHE_FAIL_ATTR_S))
+#define CACHE_L1_CACHE_FAIL_ATTR_V  0xFFFF
+#define CACHE_L1_CACHE_FAIL_ATTR_S  16
+/* CACHE_L1_CACHE_FAIL_ID : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The register records the ID of fail-access when cache accesses L1-Cache..*/
+#define CACHE_L1_CACHE_FAIL_ID    0x0000FFFF
+#define CACHE_L1_CACHE_FAIL_ID_M  ((CACHE_L1_CACHE_FAIL_ID_V)<<(CACHE_L1_CACHE_FAIL_ID_S))
+#define CACHE_L1_CACHE_FAIL_ID_V  0xFFFF
+#define CACHE_L1_CACHE_FAIL_ID_S  0
+
+#define CACHE_L1_CACHE_ACS_FAIL_ADDR_REG          (DR_REG_CACHE_BASE + 0x220)
+/* CACHE_L1_CACHE_FAIL_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The register records the address of fail-access when cache accesses L1-Cache..*/
+#define CACHE_L1_CACHE_FAIL_ADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_FAIL_ADDR_M  ((CACHE_L1_CACHE_FAIL_ADDR_V)<<(CACHE_L1_CACHE_FAIL_ADDR_S))
+#define CACHE_L1_CACHE_FAIL_ADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_FAIL_ADDR_S  0
+
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG          (DR_REG_CACHE_BASE + 0x224)
+/* CACHE_SYNC_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of Cache sync-operation error..*/
+#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ENA_M  (BIT(13))
+#define CACHE_SYNC_ERR_INT_ENA_V  0x1
+#define CACHE_SYNC_ERR_INT_ENA_S  13
+/* CACHE_L1_CACHE_PLD_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of L1-Cache preload-operation error..*/
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_M  (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_V  0x1
+#define CACHE_L1_CACHE_PLD_ERR_INT_ENA_S  11
+/* CACHE_SYNC_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of Cache sync-operation done..*/
+#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ENA_M  (BIT(6))
+#define CACHE_SYNC_DONE_INT_ENA_V  0x1
+#define CACHE_SYNC_DONE_INT_ENA_S  6
+/* CACHE_L1_CACHE_PLD_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt of L1-Cache preload-operation. If preload op
+eration is done, interrupt occurs..*/
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_M  (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_V  0x1
+#define CACHE_L1_CACHE_PLD_DONE_INT_ENA_S  4
+
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG          (DR_REG_CACHE_BASE + 0x228)
+/* CACHE_SYNC_ERR_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of Cache sync-operation error..*/
+#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define CACHE_SYNC_ERR_INT_CLR_M  (BIT(13))
+#define CACHE_SYNC_ERR_INT_CLR_V  0x1
+#define CACHE_SYNC_ERR_INT_CLR_S  13
+/* CACHE_L1_CACHE_PLD_ERR_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt of L1-Cache preload-operation error..*/
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_M  (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_V  0x1
+#define CACHE_L1_CACHE_PLD_ERR_INT_CLR_S  11
+/* CACHE_SYNC_DONE_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ done..*/
+#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define CACHE_SYNC_DONE_INT_CLR_M  (BIT(6))
+#define CACHE_SYNC_DONE_INT_CLR_V  0x1
+#define CACHE_SYNC_DONE_INT_CLR_S  6
+/* CACHE_L1_CACHE_PLD_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operat
+ion is done..*/
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_M  (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_V  0x1
+#define CACHE_L1_CACHE_PLD_DONE_INT_CLR_S  4
+
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG          (DR_REG_CACHE_BASE + 0x22C)
+/* CACHE_SYNC_ERR_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when Cache sync-operation error oc
+curs..*/
+#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define CACHE_SYNC_ERR_INT_RAW_M  (BIT(13))
+#define CACHE_SYNC_ERR_INT_RAW_V  0x1
+#define CACHE_SYNC_ERR_INT_RAW_S  13
+/* CACHE_L1_CACHE_PLD_ERR_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation er
+ror occurs..*/
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_M  (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_V  0x1
+#define CACHE_L1_CACHE_PLD_ERR_INT_RAW_S  11
+/* CACHE_SYNC_DONE_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when Cache sync-operation is done..*/
+#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define CACHE_SYNC_DONE_INT_RAW_M  (BIT(6))
+#define CACHE_SYNC_DONE_INT_RAW_V  0x1
+#define CACHE_SYNC_DONE_INT_RAW_S  6
+/* CACHE_L1_CACHE_PLD_DONE_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+ done..*/
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_M  (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_V  0x1
+#define CACHE_L1_CACHE_PLD_DONE_INT_RAW_S  4
+
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG          (DR_REG_CACHE_BASE + 0x230)
+/* CACHE_SYNC_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt of Cache sync-operation error..*/
+#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ST_M  (BIT(13))
+#define CACHE_SYNC_ERR_INT_ST_V  0x1
+#define CACHE_SYNC_ERR_INT_ST_S  13
+/* CACHE_L1_CACHE_PLD_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt of L1-Cache preload-operation error
+r..*/
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST    (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_M  (BIT(11))
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_V  0x1
+#define CACHE_L1_CACHE_PLD_ERR_INT_ST_S  11
+/* CACHE_SYNC_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt that occurs only when Cache sync-o
+peration is done..*/
+#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ST_M  (BIT(6))
+#define CACHE_SYNC_DONE_INT_ST_V  0x1
+#define CACHE_SYNC_DONE_INT_ST_S  6
+/* CACHE_L1_CACHE_PLD_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit indicates the status of the interrupt that occurs only when L1-Cache pre
+load-operation is done..*/
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST    (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_M  (BIT(4))
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_V  0x1
+#define CACHE_L1_CACHE_PLD_DONE_INT_ST_S  4
+
+#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG          (DR_REG_CACHE_BASE + 0x234)
+/* CACHE_SYNC_ERR_CODE : RO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: The values 0-2 are available which means sync map, command conflict and size are
+ error in Cache System..*/
+#define CACHE_SYNC_ERR_CODE    0x00000003
+#define CACHE_SYNC_ERR_CODE_M  ((CACHE_SYNC_ERR_CODE_V)<<(CACHE_SYNC_ERR_CODE_S))
+#define CACHE_SYNC_ERR_CODE_V  0x3
+#define CACHE_SYNC_ERR_CODE_S  12
+/* CACHE_L1_CACHE_PLD_ERR_CODE : RO ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: The value 2 is Only available which means preload size is error in L1-Cache..*/
+#define CACHE_L1_CACHE_PLD_ERR_CODE    0x00000003
+#define CACHE_L1_CACHE_PLD_ERR_CODE_M  ((CACHE_L1_CACHE_PLD_ERR_CODE_V)<<(CACHE_L1_CACHE_PLD_ERR_CODE_S))
+#define CACHE_L1_CACHE_PLD_ERR_CODE_V  0x3
+#define CACHE_L1_CACHE_PLD_ERR_CODE_S  8
+
+#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG          (DR_REG_CACHE_BASE + 0x238)
+/* CACHE_L1_CACHE_SYNC_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+y be used to initialize sync-logic when some fatal error of sync-logic occurs..*/
+#define CACHE_L1_CACHE_SYNC_RST    (BIT(4))
+#define CACHE_L1_CACHE_SYNC_RST_M  (BIT(4))
+#define CACHE_L1_CACHE_SYNC_RST_V  0x1
+#define CACHE_L1_CACHE_SYNC_RST_S  4
+
+#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG          (DR_REG_CACHE_BASE + 0x23C)
+/* CACHE_L1_CACHE_PLD_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+only be used to initialize preload-logic when some fatal error of preload-logic
+occurs..*/
+#define CACHE_L1_CACHE_PLD_RST    (BIT(4))
+#define CACHE_L1_CACHE_PLD_RST_M  (BIT(4))
+#define CACHE_L1_CACHE_PLD_RST_V  0x1
+#define CACHE_L1_CACHE_PLD_RST_S  4
+
+#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG          (DR_REG_CACHE_BASE + 0x240)
+/* CACHE_L1_CACHE_ALD_BUF_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, au
+toload will not work in L1-Cache. This bit should not be active when autoload wo
+rks in L1-Cache..*/
+#define CACHE_L1_CACHE_ALD_BUF_CLR    (BIT(4))
+#define CACHE_L1_CACHE_ALD_BUF_CLR_M  (BIT(4))
+#define CACHE_L1_CACHE_ALD_BUF_CLR_V  0x1
+#define CACHE_L1_CACHE_ALD_BUF_CLR_S  4
+
+#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG          (DR_REG_CACHE_BASE + 0x244)
+/* CACHE_L1_CACHE_UNALLOC_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear the unallocate request buffer of l1 cache where the una
+llocate request is responded but not completed..*/
+#define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
+#define CACHE_L1_CACHE_UNALLOC_CLR_M  (BIT(4))
+#define CACHE_L1_CACHE_UNALLOC_CLR_V  0x1
+#define CACHE_L1_CACHE_UNALLOC_CLR_S  4
+
+#define CACHE_L1_CACHE_OBJECT_CTRL_REG          (DR_REG_CACHE_BASE + 0x248)
+/* CACHE_L1_CACHE_MEM_OBJECT : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to set L1-Cache data memory as object. This bit should be onehot wi
+th the others fields inside this register..*/
+#define CACHE_L1_CACHE_MEM_OBJECT    (BIT(10))
+#define CACHE_L1_CACHE_MEM_OBJECT_M  (BIT(10))
+#define CACHE_L1_CACHE_MEM_OBJECT_V  0x1
+#define CACHE_L1_CACHE_MEM_OBJECT_S  10
+/* CACHE_L1_CACHE_TAG_OBJECT : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+h the others fields inside this register..*/
+#define CACHE_L1_CACHE_TAG_OBJECT    (BIT(4))
+#define CACHE_L1_CACHE_TAG_OBJECT_M  (BIT(4))
+#define CACHE_L1_CACHE_TAG_OBJECT_V  0x1
+#define CACHE_L1_CACHE_TAG_OBJECT_S  4
+
+#define CACHE_L1_CACHE_WAY_OBJECT_REG          (DR_REG_CACHE_BASE + 0x24C)
+/* CACHE_L1_CACHE_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
+: way1, 2: way2, 3: way3, ?, 7: way7..*/
+#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007
+#define CACHE_L1_CACHE_WAY_OBJECT_M  ((CACHE_L1_CACHE_WAY_OBJECT_V)<<(CACHE_L1_CACHE_WAY_OBJECT_S))
+#define CACHE_L1_CACHE_WAY_OBJECT_V  0x7
+#define CACHE_L1_CACHE_WAY_OBJECT_S  0
+
+#define CACHE_L1_CACHE_VADDR_REG          (DR_REG_CACHE_BASE + 0x250)
+/* CACHE_L1_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h40000000 ; */
+/*description: Those bits stores the virtual address which will decide where inside the specified
+tag memory object will be accessed..*/
+#define CACHE_L1_CACHE_VADDR    0xFFFFFFFF
+#define CACHE_L1_CACHE_VADDR_M  ((CACHE_L1_CACHE_VADDR_V)<<(CACHE_L1_CACHE_VADDR_S))
+#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_VADDR_S  0
+
+#define CACHE_L1_CACHE_DEBUG_BUS_REG          (DR_REG_CACHE_BASE + 0x254)
+/* CACHE_L1_CACHE_DEBUG_BUS : R/W ;bitpos:[31:0] ;default: 32'h254 ; */
+/*description: This is a constant place where we can write data to or read data from the tag/da
+ta memory on the specified cache..*/
+#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFF
+#define CACHE_L1_CACHE_DEBUG_BUS_M  ((CACHE_L1_CACHE_DEBUG_BUS_V)<<(CACHE_L1_CACHE_DEBUG_BUS_S))
+#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFF
+#define CACHE_L1_CACHE_DEBUG_BUS_S  0
+
+#define CACHE_CLOCK_GATE_REG          (DR_REG_CACHE_BASE + 0x3AC)
+/* CACHE_CLK_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: The bit is used to enable clock gate when access all registers in this module..*/
+#define CACHE_CLK_EN    (BIT(0))
+#define CACHE_CLK_EN_M  (BIT(0))
+#define CACHE_CLK_EN_V  0x1
+#define CACHE_CLK_EN_S  0
+
+#define CACHE_REDUNDANCY_SIG0_REG          (DR_REG_CACHE_BASE + 0x3B0)
+/* CACHE_REDCY_SIG0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are prepared for ECO..*/
+#define CACHE_REDCY_SIG0    0xFFFFFFFF
+#define CACHE_REDCY_SIG0_M  ((CACHE_REDCY_SIG0_V)<<(CACHE_REDCY_SIG0_S))
+#define CACHE_REDCY_SIG0_V  0xFFFFFFFF
+#define CACHE_REDCY_SIG0_S  0
+
+#define CACHE_REDUNDANCY_SIG1_REG          (DR_REG_CACHE_BASE + 0x3B4)
+/* CACHE_REDCY_SIG1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are prepared for ECO..*/
+#define CACHE_REDCY_SIG1    0xFFFFFFFF
+#define CACHE_REDCY_SIG1_M  ((CACHE_REDCY_SIG1_V)<<(CACHE_REDCY_SIG1_S))
+#define CACHE_REDCY_SIG1_V  0xFFFFFFFF
+#define CACHE_REDCY_SIG1_S  0
+
+#define CACHE_REDUNDANCY_SIG2_REG          (DR_REG_CACHE_BASE + 0x3B8)
+/* CACHE_REDCY_SIG2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are prepared for ECO..*/
+#define CACHE_REDCY_SIG2    0xFFFFFFFF
+#define CACHE_REDCY_SIG2_M  ((CACHE_REDCY_SIG2_V)<<(CACHE_REDCY_SIG2_S))
+#define CACHE_REDCY_SIG2_V  0xFFFFFFFF
+#define CACHE_REDCY_SIG2_S  0
+
+#define CACHE_REDUNDANCY_SIG3_REG          (DR_REG_CACHE_BASE + 0x3BC)
+/* CACHE_REDCY_SIG3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Those bits are prepared for ECO..*/
+#define CACHE_REDCY_SIG3    0xFFFFFFFF
+#define CACHE_REDCY_SIG3_M  ((CACHE_REDCY_SIG3_V)<<(CACHE_REDCY_SIG3_S))
+#define CACHE_REDCY_SIG3_V  0xFFFFFFFF
+#define CACHE_REDCY_SIG3_S  0
+
+#define CACHE_REDUNDANCY_SIG4_REG          (DR_REG_CACHE_BASE + 0x3C0)
+/* CACHE_REDCY_SIG4 : RO ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: Those bits are prepared for ECO..*/
+#define CACHE_REDCY_SIG4    0x0000000F
+#define CACHE_REDCY_SIG4_M  ((CACHE_REDCY_SIG4_V)<<(CACHE_REDCY_SIG4_S))
+#define CACHE_REDCY_SIG4_V  0xF
+#define CACHE_REDCY_SIG4_S  0
+
+#define CACHE_DATE_REG          (DR_REG_CACHE_BASE + 0x3FC)
+/* CACHE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2207250 ; */
+/*description: version control register. Note that this default value stored is the latest date
+ when the hardware logic was updated..*/
+#define CACHE_DATE    0x0FFFFFFF
+#define CACHE_DATE_M  ((CACHE_DATE_V)<<(CACHE_DATE_S))
+#define CACHE_DATE_V  0xFFFFFFF
+#define CACHE_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_CACHE_REG_H_ */
diff --git a/components/soc/esp32h2/register/soc/extmem_struct.h b/components/soc/esp32h2/register/soc/extmem_struct.h
new file mode 100644
index 00000000000..d43c5fcee3d
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/extmem_struct.h
@@ -0,0 +1,5747 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of l1_icache_ctrl register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+typedef union {
+    struct {
+        /** l1_icache_shut_ibus0 : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus0:1;
+        /** l1_icache_shut_ibus1 : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+         */
+        uint32_t l1_icache_shut_ibus1:1;
+        /** l1_icache_shut_ibus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus2:1;
+        /** l1_icache_shut_ibus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_shut_ibus3:1;
+        /** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache_undef_op:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_icache_ctrl_reg_t;
+
+/** Type of l1_cache_ctrl register
+ *  L1 data Cache(L1-Cache) control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_shut_bus0 : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus0:1;
+        /** l1_cache_shut_bus1 : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_bus1:1;
+        /** l1_cache_shut_dbus2 : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus2:1;
+        /** l1_cache_shut_dbus3 : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_shut_dbus3:1;
+        /** l1_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable
+         */
+        uint32_t l1_cache_shut_dma:1;
+        uint32_t reserved_5:3;
+        /** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_cache_undef_op:4;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l1_cache_ctrl_reg_t;
+
+/** Type of l2_cache_ctrl register
+ *  L2 Cache(L2-Cache) control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+         */
+        uint32_t l2_cache_shut_dma:1;
+        /** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_cache_undef_op:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} extmem_l2_cache_ctrl_reg_t;
+
+
+/** Group: Bypass Cache Control and configuration registers */
+/** Type of l1_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        /** bypass_l1_icache0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache0_en:1;
+        /** bypass_l1_icache1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_icache1_en:1;
+        /** bypass_l1_icache2_en : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache2_en:1;
+        /** bypass_l1_icache3_en : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t bypass_l1_icache3_en:1;
+        /** bypass_l1_dcache_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l1_dcache_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_bypass_cache_conf_reg_t;
+
+/** Type of l2_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+         */
+        uint32_t bypass_l2_cache_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_bypass_cache_conf_reg_t;
+
+
+/** Group: Cache Atomic Control and configuration registers */
+/** Type of l1_cache_atomic_conf register
+ *  L1 Cache atomic feature configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_atomic_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable atomic feature on L1-Cache when multiple cores access
+         *  L1-Cache.  1: disable, 1: enable.
+         */
+        uint32_t l1_cache_atomic_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} extmem_l1_cache_atomic_conf_reg_t;
+
+
+/** Group: Cache Mode Control and configuration registers */
+/** Type of l1_icache_cachesize_conf register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1k:1;
+        /** l1_icache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2k:1;
+        /** l1_icache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4k:1;
+        /** l1_icache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_8k:1;
+        /** l1_icache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_16k:1;
+        /** l1_icache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_32k:1;
+        /** l1_icache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_64k:1;
+        /** l1_icache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_128k:1;
+        /** l1_icache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_256k:1;
+        /** l1_icache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_512k:1;
+        /** l1_icache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_1024k:1;
+        /** l1_icache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2048k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_2048k:1;
+        /** l1_icache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4096k bytes. This field
+         *  and all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l1_icache_cachesize_conf_reg_t;
+
+/** Type of l1_icache_blocksize_conf register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_8:1;
+        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_16:1;
+        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_32:1;
+        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_64:1;
+        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_128:1;
+        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache_blocksize_conf_reg_t;
+
+/** Type of l1_cache_cachesize_conf register
+ *  L1 data Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1k:1;
+        /** l1_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2k:1;
+        /** l1_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4k:1;
+        /** l1_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_8k:1;
+        /** l1_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_16k:1;
+        /** l1_cache_cachesize_32k : HRO; bitpos: [5]; default: 1;
+         *  The field is used to configure cachesize of L1-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_32k:1;
+        /** l1_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_64k:1;
+        /** l1_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_128k:1;
+        /** l1_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_256k:1;
+        /** l1_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_512k:1;
+        /** l1_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_1024k:1;
+        /** l1_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_2048k:1;
+        /** l1_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l1_cache_cachesize_conf_reg_t;
+
+/** Type of l1_cache_blocksize_conf register
+ *  L1 data Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_8:1;
+        /** l1_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_16:1;
+        /** l1_cache_blocksize_32 : HRO; bitpos: [2]; default: 1;
+         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_32:1;
+        /** l1_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_64:1;
+        /** l1_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_128:1;
+        /** l1_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_cache_blocksize_conf_reg_t;
+
+/** Type of l2_cache_cachesize_conf register
+ *  L2 Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_cachesize_1k : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1k:1;
+        /** l2_cache_cachesize_2k : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2k:1;
+        /** l2_cache_cachesize_4k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4k:1;
+        /** l2_cache_cachesize_8k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_8k:1;
+        /** l2_cache_cachesize_16k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_16k:1;
+        /** l2_cache_cachesize_32k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_32k:1;
+        /** l2_cache_cachesize_64k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_64k:1;
+        /** l2_cache_cachesize_128k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_128k:1;
+        /** l2_cache_cachesize_256k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_256k:1;
+        /** l2_cache_cachesize_512k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_512k:1;
+        /** l2_cache_cachesize_1024k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_1024k:1;
+        /** l2_cache_cachesize_2048k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_2048k:1;
+        /** l2_cache_cachesize_4096k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_cachesize_4096k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_cachesize_conf_reg_t;
+
+/** Type of l2_cache_blocksize_conf register
+ *  L2 Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_8:1;
+        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_16:1;
+        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_32:1;
+        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+         *  other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_64:1;
+        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_128:1;
+        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l2_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_blocksize_conf_reg_t;
+
+
+/** Group: Wrap Mode Control and configuration registers */
+/** Type of l1_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_wrap : HRO; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+         */
+        uint32_t l1_icache0_wrap:1;
+        /** l1_icache1_wrap : HRO; bitpos: [1]; default: 0;
+         *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+         */
+        uint32_t l1_icache1_wrap:1;
+        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_wrap:1;
+        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_wrap:1;
+        /** l1_cache_wrap : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to enable L1-DCache wrap around mode.
+         */
+        uint32_t l1_cache_wrap:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_wrap_around_ctrl_reg_t;
+
+/** Type of l2_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to enable L2-Cache wrap around mode.
+         */
+        uint32_t l2_cache_wrap:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_wrap_around_ctrl_reg_t;
+
+
+/** Group: Cache Tag Memory Power Control registers */
+/** Type of l1_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_force_on : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_tag_mem_force_on:1;
+        /** l1_icache0_tag_mem_force_pd : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_tag_mem_force_pd:1;
+        /** l1_icache0_tag_mem_force_pu : HRO; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_tag_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_tag_mem_force_on : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_tag_mem_force_on:1;
+        /** l1_icache1_tag_mem_force_pd : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_tag_mem_force_pd:1;
+        /** l1_icache1_tag_mem_force_pu : HRO; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_tag_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_tag_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_on:1;
+        /** l1_icache2_tag_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pd:1;
+        /** l1_icache2_tag_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_tag_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_on:1;
+        /** l1_icache3_tag_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pd:1;
+        /** l1_icache3_tag_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_tag_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_cache_tag_mem_force_on:1;
+        /** l1_cache_tag_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l1_cache_tag_mem_force_pd:1;
+        /** l1_cache_tag_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_cache_tag_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_tag_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_tag_mem_power_ctrl register
+ *  Cache tag memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_force_on : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_tag_mem_force_on:1;
+        /** l2_cache_tag_mem_force_pd : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+         */
+        uint32_t l2_cache_tag_mem_force_pd:1;
+        /** l2_cache_tag_mem_force_pu : HRO; bitpos: [22]; default: 0;
+         *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_tag_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_tag_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Power Control registers */
+/** Type of l1_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_force_on : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache0_data_mem_force_on:1;
+        /** l1_icache0_data_mem_force_pd : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache0_data_mem_force_pd:1;
+        /** l1_icache0_data_mem_force_pu : HRO; bitpos: [2]; default: 1;
+         *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache0_data_mem_force_pu:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_data_mem_force_on : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+         *  0: open clock gating.
+         */
+        uint32_t l1_icache1_data_mem_force_on:1;
+        /** l1_icache1_data_mem_force_pd : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_icache1_data_mem_force_pd:1;
+        /** l1_icache1_data_mem_force_pu : HRO; bitpos: [6]; default: 1;
+         *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_icache1_data_mem_force_pu:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_data_mem_force_on : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_on:1;
+        /** l1_icache2_data_mem_force_pd : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pd:1;
+        /** l1_icache2_data_mem_force_pu : HRO; bitpos: [10]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_force_pu:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_data_mem_force_on : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_on:1;
+        /** l1_icache3_data_mem_force_pd : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pd:1;
+        /** l1_icache3_data_mem_force_pu : HRO; bitpos: [14]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_force_pu:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_data_mem_force_on : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to close clock gating of  L1-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l1_cache_data_mem_force_on:1;
+        /** l1_cache_data_mem_force_pd : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l1_cache_data_mem_force_pd:1;
+        /** l1_cache_data_mem_force_pu : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l1_cache_data_mem_force_pu:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_data_mem_power_ctrl_reg_t;
+
+/** Type of l2_cache_data_mem_power_ctrl register
+ *  Cache data memory power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_force_on : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+         *  open clock gating.
+         */
+        uint32_t l2_cache_data_mem_force_on:1;
+        /** l2_cache_data_mem_force_pd : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+         *  down
+         */
+        uint32_t l2_cache_data_mem_force_pd:1;
+        /** l2_cache_data_mem_force_pu : HRO; bitpos: [22]; default: 0;
+         *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+         */
+        uint32_t l2_cache_data_mem_force_pu:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_data_mem_power_ctrl_reg_t;
+
+
+/** Group: Cache Freeze Control registers */
+/** Type of l1_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_freeze_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache0_freeze_en:1;
+        /** l1_icache0_freeze_mode : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache0_freeze_mode:1;
+        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_freeze_done:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_freeze_en : HRO; bitpos: [4]; default: 0;
+         *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_icache1_freeze_en:1;
+        /** l1_icache1_freeze_mode : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_icache1_freeze_mode:1;
+        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_freeze_done:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_en:1;
+        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_mode:1;
+        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_freeze_done:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_en:1;
+        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_mode:1;
+        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_freeze_done:1;
+        uint32_t reserved_15:1;
+        /** l1_cache_freeze_en : R/W; bitpos: [16]; default: 0;
+         *  The bit is used to enable freeze operation on L1-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l1_cache_freeze_en:1;
+        /** l1_cache_freeze_mode : R/W; bitpos: [17]; default: 0;
+         *  The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l1_cache_freeze_mode:1;
+        /** l1_cache_freeze_done : RO; bitpos: [18]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_freeze_done:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} extmem_l1_cache_freeze_ctrl_reg_t;
+
+/** Type of l2_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+         *  software.
+         */
+        uint32_t l2_cache_freeze_en:1;
+        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+         *  will not stuck. 1: a miss-access will stuck.
+         */
+        uint32_t l2_cache_freeze_mode:1;
+        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_freeze_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} extmem_l2_cache_freeze_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Access Control and Configuration registers */
+/** Type of l1_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_rd_en : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_data_mem_rd_en:1;
+        /** l1_icache0_data_mem_wr_en : HRO; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache0_data_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_data_mem_rd_en : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_data_mem_rd_en:1;
+        /** l1_icache1_data_mem_wr_en : HRO; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+         *  1: enable.
+         */
+        uint32_t l1_icache1_data_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_data_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_rd_en:1;
+        /** l1_icache2_data_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_data_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_rd_en:1;
+        /** l1_icache3_data_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_data_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_rd_en:1;
+        /** l1_cache_data_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_data_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} extmem_l1_cache_data_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_rd_en:1;
+        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_data_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} extmem_l2_cache_data_mem_acs_conf_reg_t;
+
+
+/** Group: Cache Tag Memory Access Control and Configuration registers */
+/** Type of l1_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_rd_en : HRO; bitpos: [0]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_rd_en:1;
+        /** l1_icache0_tag_mem_wr_en : HRO; bitpos: [1]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache0_tag_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_tag_mem_rd_en : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_rd_en:1;
+        /** l1_icache1_tag_mem_wr_en : HRO; bitpos: [5]; default: 1;
+         *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_icache1_tag_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_tag_mem_rd_en : HRO; bitpos: [8]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_rd_en:1;
+        /** l1_icache2_tag_mem_wr_en : HRO; bitpos: [9]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_tag_mem_rd_en : HRO; bitpos: [12]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_rd_en:1;
+        /** l1_icache3_tag_mem_wr_en : HRO; bitpos: [13]; default: 1;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_cache_tag_mem_rd_en : R/W; bitpos: [16]; default: 1;
+         *  The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_rd_en:1;
+        /** l1_cache_tag_mem_wr_en : R/W; bitpos: [17]; default: 1;
+         *  The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l1_cache_tag_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} extmem_l1_cache_tag_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 0;
+         *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_rd_en:1;
+        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 0;
+         *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+         *  enable.
+         */
+        uint32_t l2_cache_tag_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} extmem_l2_cache_tag_mem_acs_conf_reg_t;
+
+
+/** Group: Prelock Control and configuration registers */
+/** Type of l1_icache0_prelock_conf register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct0_en:1;
+        /** l1_icache0_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache0.
+         */
+        uint32_t l1_icache0_prelock_sct1_en:1;
+        /** l1_icache0_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 prelock.
+         */
+        uint32_t l1_icache0_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_conf_reg_t;
+
+/** Type of l1_icache0_prelock_sct0_addr register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct1_addr register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache0, which should be used together with
+         *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct_size register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache0_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache0_prelock_sct_size_reg_t;
+
+/** Type of l1_icache1_prelock_conf register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct0_en:1;
+        /** l1_icache1_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache1.
+         */
+        uint32_t l1_icache1_prelock_sct1_en:1;
+        /** l1_icache1_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 prelock.
+         */
+        uint32_t l1_icache1_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_conf_reg_t;
+
+/** Type of l1_icache1_prelock_sct0_addr register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct1_addr register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache1, which should be used together with
+         *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct_size register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache1_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache1_prelock_sct_size_reg_t;
+
+/** Type of l1_icache2_prelock_conf register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct0_en:1;
+        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache2.
+         */
+        uint32_t l1_icache2_prelock_sct1_en:1;
+        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 prelock.
+         */
+        uint32_t l1_icache2_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_conf_reg_t;
+
+/** Type of l1_icache2_prelock_sct0_addr register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct1_addr register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache2, which should be used together with
+         *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct_size register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache2_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache2_prelock_sct_size_reg_t;
+
+/** Type of l1_icache3_prelock_conf register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct0_en:1;
+        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-ICache3.
+         */
+        uint32_t l1_icache3_prelock_sct1_en:1;
+        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 prelock.
+         */
+        uint32_t l1_icache3_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_conf_reg_t;
+
+/** Type of l1_icache3_prelock_sct0_addr register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct1_addr register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-ICache3, which should be used together with
+         *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct_size register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache3_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_icache3_prelock_sct_size_reg_t;
+
+/** Type of l1_cache_prelock_conf register
+ *  L1 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct0_en:1;
+        /** l1_cache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L1-Cache.
+         */
+        uint32_t l1_cache_prelock_sct1_en:1;
+        /** l1_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l1 cache prelock.
+         */
+        uint32_t l1_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l1_cache_prelock_conf_reg_t;
+
+/** Type of l1_cache_prelock_sct0_addr register
+ *  L1 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L1-Cache, which should be used together with
+         *  L1_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct1_addr register
+ *  L1 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L1-Cache, which should be used together with
+         *  L1_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_prelock_sct1_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct_size register
+ *  L1  Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_cache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_cache_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} extmem_l1_dcache_prelock_sct_size_reg_t;
+
+/** Type of l2_cache_prelock_conf register
+ *  L2 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable the first section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct0_en:1;
+        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable the second section of prelock function on L2-Cache.
+         */
+        uint32_t l2_cache_prelock_sct1_en:1;
+        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  The bit is used to set  the gid of l2 cache prelock.
+         */
+        uint32_t l2_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_conf_reg_t;
+
+/** Type of l2_cache_prelock_sct0_addr register
+ *  L2 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct1_addr register
+ *  L2 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section of
+         *  prelock on L2-Cache, which should be used together with
+         *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l2_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct1_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct_size register
+ *  L2 Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct0_size:16;
+        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
+         *  Those bits are used to configure the size of the second section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l2_cache_prelock_sct1_size:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_prelock_sct_size_reg_t;
+
+
+/** Group: Lock Control and configuration registers */
+/** Type of cache_lock_ctrl register
+ *  Lock-class (manual lock) operation control register
+ */
+typedef union {
+    struct {
+        /** cache_lock_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+         *  operation done
+         */
+        uint32_t cache_lock_ena:1;
+        /** cache_unlock_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable unlock operation. It will be cleared by hardware after
+         *  unlock operation done
+         */
+        uint32_t cache_unlock_ena:1;
+        /** cache_lock_done : RO; bitpos: [2]; default: 1;
+         *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+         *  not finished. 1: finished.
+         */
+        uint32_t cache_lock_done:1;
+        /** cache_lock_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of cache lock/unlock.
+         */
+        uint32_t cache_lock_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_cache_lock_ctrl_reg_t;
+
+/** Type of cache_lock_map register
+ *  Lock (manual lock) map configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_map : R/W; bitpos: [5:0]; default: 0;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply this lock/unlock operation. [4]: L1-Cache
+         */
+        uint32_t cache_lock_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_cache_lock_map_reg_t;
+
+/** Type of cache_lock_addr register
+ *  Lock (manual lock) address configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the lock/unlock
+         *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+         */
+        uint32_t cache_lock_addr:32;
+    };
+    uint32_t val;
+} extmem_cache_lock_addr_reg_t;
+
+/** Type of cache_lock_size register
+ *  Lock (manual lock) size configure register
+ */
+typedef union {
+    struct {
+        /** cache_lock_size : R/W; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the lock/unlock operation, which
+         *  should be used together with CACHE_LOCK_ADDR_REG
+         */
+        uint32_t cache_lock_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_cache_lock_size_reg_t;
+
+
+/** Group: Sync Control and configuration registers */
+/** Type of cache_sync_ctrl register
+ *  Sync-class operation control register
+ */
+typedef union {
+    struct {
+        /** cache_invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
+         *  The bit is used to enable invalidate operation. It will be cleared by hardware
+         *  after invalidate operation done. Note that this bit and the other sync-bits
+         *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_invalidate_ena:1;
+        /** cache_clean_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  The bit is used to enable clean operation. It will be cleared by hardware after
+         *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+         *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+         *  bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_clean_ena:1;
+        /** cache_writeback_ena : R/W/SC; bitpos: [2]; default: 0;
+         *  The bit is used to enable writeback operation. It will be cleared by hardware after
+         *  writeback operation done. Note that this bit and the other sync-bits
+         *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+         *  is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_writeback_ena:1;
+        /** cache_writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
+         *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+         *  hardware after writeback-invalidate operation done. Note that this bit and the
+         *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+         *  that is, those bits can not be set to 1 at the same time.
+         */
+        uint32_t cache_writeback_invalidate_ena:1;
+        /** cache_sync_done : RO; bitpos: [4]; default: 0;
+         *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+         *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+         */
+        uint32_t cache_sync_done:1;
+        /** cache_sync_rgid : HRO; bitpos: [8:5]; default: 0;
+         *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+         *  writeback, writeback_invalidate)
+         */
+        uint32_t cache_sync_rgid:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} extmem_cache_sync_ctrl_reg_t;
+
+/** Type of cache_sync_map register
+ *  Sync map configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_map : R/W; bitpos: [5:0]; default: 63;
+         *  Those bits are used to indicate which caches in the two-level cache structure will
+         *  apply the sync operation.  [4]: L1-Cache
+         */
+        uint32_t cache_sync_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_cache_sync_map_reg_t;
+
+/** Type of cache_sync_addr register
+ *  Sync address configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the sync operation,
+         *  which should be used together with CACHE_SYNC_SIZE_REG
+         */
+        uint32_t cache_sync_addr:32;
+    };
+    uint32_t val;
+} extmem_cache_sync_addr_reg_t;
+
+/** Type of cache_sync_size register
+ *  Sync size configure register
+ */
+typedef union {
+    struct {
+        /** cache_sync_size : R/W; bitpos: [23:0]; default: 0;
+         *  Those bits are used to configure the size of the sync operation, which should be
+         *  used together with CACHE_SYNC_ADDR_REG
+         */
+        uint32_t cache_sync_size:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} extmem_cache_sync_size_reg_t;
+
+
+/** Group: Preload Control and configuration registers */
+/** Type of l1_icache0_preload_ctrl register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache0_preload_ena:1;
+        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache0_preload_done:1;
+        /** l1_icache0_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache0_preload_order:1;
+        /** l1_icache0_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 preload.
+         */
+        uint32_t l1_icache0_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_ctrl_reg_t;
+
+/** Type of l1_icache0_preload_addr register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache0_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_addr_reg_t;
+
+/** Type of l1_icache0_preload_size register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache0_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache0_preload_size_reg_t;
+
+/** Type of l1_icache1_preload_ctrl register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache1_preload_ena:1;
+        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache1_preload_done:1;
+        /** l1_icache1_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache1_preload_order:1;
+        /** l1_icache1_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 preload.
+         */
+        uint32_t l1_icache1_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_ctrl_reg_t;
+
+/** Type of l1_icache1_preload_addr register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache1_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_addr_reg_t;
+
+/** Type of l1_icache1_preload_size register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache1_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache1_preload_size_reg_t;
+
+/** Type of l1_icache2_preload_ctrl register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache2_preload_ena:1;
+        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache2_preload_done:1;
+        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache2_preload_order:1;
+        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 preload.
+         */
+        uint32_t l1_icache2_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_ctrl_reg_t;
+
+/** Type of l1_icache2_preload_addr register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache2_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_addr_reg_t;
+
+/** Type of l1_icache2_preload_size register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache2_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache2_preload_size_reg_t;
+
+/** Type of l1_icache3_preload_ctrl register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_icache3_preload_ena:1;
+        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_icache3_preload_done:1;
+        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_icache3_preload_order:1;
+        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 preload.
+         */
+        uint32_t l1_icache3_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_ctrl_reg_t;
+
+/** Type of l1_icache3_preload_addr register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache3_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_addr_reg_t;
+
+/** Type of l1_icache3_preload_size register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache3_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache3_preload_size_reg_t;
+
+/** Type of l1_cache_preload_ctrl register
+ *  L1 Cache  preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L1-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l1_cache_preload_ena:1;
+        /** l1_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l1_cache_preload_done:1;
+        /** l1_cache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l1_cache_preload_order:1;
+        /** l1_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l1 cache preload.
+         */
+        uint32_t l1_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l1_cache_preload_ctrl_reg_t;
+
+/** Type of l1_dcache_preload_addr register
+ *  L1 Cache  preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L1-Cache,
+         *  which should be used together with L1_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_cache_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_preload_addr_reg_t;
+
+/** Type of l1_dcache_preload_size register
+ *  L1 Cache  preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_cache_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_dcache_preload_size_reg_t;
+
+/** Type of l2_cache_preload_ctrl register
+ *  L2 Cache preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+         *  hardware automatically after preload operation is done.
+         */
+        uint32_t l2_cache_preload_ena:1;
+        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         */
+        uint32_t l2_cache_preload_done:1;
+        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+         *  descending.
+         */
+        uint32_t l2_cache_preload_order:1;
+        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  The bit is used to set  the gid of l2 cache preload.
+         */
+        uint32_t l2_cache_preload_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_ctrl_reg_t;
+
+/** Type of l2_cache_preload_addr register
+ *  L2 Cache preload address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+         *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l2_cache_preload_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_addr_reg_t;
+
+/** Type of l2_cache_preload_size register
+ *  L2 Cache preload size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
+         *  Those bits are used to configure the size of the first section of prelock on
+         *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l2_cache_preload_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_size_reg_t;
+
+
+/** Group: Autoload Control and configuration registers */
+/** Type of l1_icache0_autoload_ctrl register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache0_autoload_ena:1;
+        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache0_autoload_done:1;
+        /** l1_icache0_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache0_autoload_order:1;
+        /** l1_icache0_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache0_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache0_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct0_ena:1;
+        /** l1_icache0_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+         */
+        uint32_t l1_icache0_autoload_sct1_ena:1;
+        /** l1_icache0_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache0 autoload.
+         */
+        uint32_t l1_icache0_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_ctrl_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_addr register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_size register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_addr register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_size register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache0. Note that it should be used together with
+         *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache0_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache1_autoload_ctrl register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache1_autoload_ena:1;
+        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache1_autoload_done:1;
+        /** l1_icache1_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache1_autoload_order:1;
+        /** l1_icache1_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache1_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache1_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct0_ena:1;
+        /** l1_icache1_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+         */
+        uint32_t l1_icache1_autoload_sct1_ena:1;
+        /** l1_icache1_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache1 autoload.
+         */
+        uint32_t l1_icache1_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_ctrl_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_addr register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_size register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_addr register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_size register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache1. Note that it should be used together with
+         *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache1_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache2_autoload_ctrl register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache2_autoload_ena:1;
+        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache2_autoload_done:1;
+        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache2_autoload_order:1;
+        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache2_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct0_ena:1;
+        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+         */
+        uint32_t l1_icache2_autoload_sct1_ena:1;
+        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache2 autoload.
+         */
+        uint32_t l1_icache2_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_ctrl_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_addr register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_size register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_addr register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_size register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-ICache2. Note that it should be used together with
+         *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache2_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache2_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache3_autoload_ctrl register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_icache3_autoload_ena:1;
+        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_icache3_autoload_done:1;
+        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_icache3_autoload_order:1;
+        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_icache3_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct0_ena:1;
+        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+         */
+        uint32_t l1_icache3_autoload_sct1_ena:1;
+        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  The bit is used to set  the gid of l1 icache3 autoload.
+         */
+        uint32_t l1_icache3_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_ctrl_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_addr register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_size register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_addr register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-ICache3. Note that it should be used together with
+         *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache3_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_size register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_icache3_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_ctrl register
+ *  L1 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L1-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l1_cache_autoload_ena:1;
+        /** l1_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l1_cache_autoload_done:1;
+        /** l1_cache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L1-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l1_cache_autoload_order:1;
+        /** l1_cache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l1_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_cache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct0_ena:1;
+        /** l1_cache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct1_ena:1;
+        /** l1_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct2_ena:1;
+        /** l1_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L1-Cache.
+         */
+        uint32_t l1_cache_autoload_sct3_ena:1;
+        /** l1_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l1 cache autoload.
+         */
+        uint32_t l1_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_ctrl_reg_t;
+
+/** Type of l1_cache_autoload_sct0_addr register
+ *  L1 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct0_size register
+ *  L1 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct0_size_reg_t;
+
+/** Type of l1_cache_autoload_sct1_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct1_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct1_size_reg_t;
+
+/** Type of l1_cache_autoload_sct2_addr register
+ *  L1 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct2_size register
+ *  L1 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct2_size_reg_t;
+
+/** Type of l1_cache_autoload_sct3_addr register
+ *  L1 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l1_cache_autoload_sct3_size register
+ *  L1 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L1-Cache. Note that it should be used together with
+         *  L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_sct3_size_reg_t;
+
+/** Type of l2_cache_autoload_ctrl register
+ *  L2 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+         *  0: disable.
+         */
+        uint32_t l2_cache_autoload_ena:1;
+        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         */
+        uint32_t l2_cache_autoload_done:1;
+        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+         *  ascending. 1: descending.
+         */
+        uint32_t l2_cache_autoload_order:1;
+        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         */
+        uint32_t l2_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable the first section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct0_ena:1;
+        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable the second section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct1_ena:1;
+        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  The bit is used to enable the third section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct2_ena:1;
+        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+         */
+        uint32_t l2_cache_autoload_sct3_ena:1;
+        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  The bit is used to set  the gid of l2 cache autoload.
+         */
+        uint32_t l2_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_sct0_addr register
+ *  L2 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the first section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct0_size register
+ *  L2 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the first section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l2_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct0_size_reg_t;
+
+/** Type of l2_cache_autoload_sct1_addr register
+ *  L2 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the second section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct1_size register
+ *  L2 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the second section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l2_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct1_size_reg_t;
+
+/** Type of l2_cache_autoload_sct2_addr register
+ *  L2 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the third section for
+         *  autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct2_size register
+ *  L2 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the third section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l2_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct2_size_reg_t;
+
+/** Type of l2_cache_autoload_sct3_addr register
+ *  L2 Cache autoload section 3 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start virtual address of the fourth section
+         *  for autoload operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct3_size register
+ *  L2 Cache autoload section 3 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Those bits are used to configure the size of the fourth section for autoload
+         *  operation on L2-Cache. Note that it should be used together with
+         *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l2_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_sct3_size_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of l1_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_ena:1;
+        /** l1_ibus1_ovf_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_ena:1;
+        /** l1_ibus2_ovf_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_ena:1;
+        /** l1_ibus3_ovf_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_ena:1;
+        /** l1_bus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_ena:1;
+        /** l1_bus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_ena:1;
+        /** l1_dbus2_ovf_int_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_ena:1;
+        /** l1_dbus3_ovf_int_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+         *  to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_clr:1;
+        /** l1_ibus1_ovf_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+         *  to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_clr:1;
+        /** l1_ibus2_ovf_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_clr:1;
+        /** l1_ibus3_ovf_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_clr:1;
+        /** l1_bus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_clr:1;
+        /** l1_bus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_clr:1;
+        /** l1_dbus2_ovf_int_clr : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_clr:1;
+        /** l1_dbus3_ovf_int_clr : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+         *  due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_raw:1;
+        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+         *  due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_raw:1;
+        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+         *  due to bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_ovf_int_raw:1;
+        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+         *  due to bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_ovf_int_raw:1;
+        /** l1_bus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_raw:1;
+        /** l1_bus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_raw:1;
+        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_ovf_int_raw:1;
+        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_ovf_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_st:1;
+        /** l1_ibus1_ovf_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_st:1;
+        /** l1_ibus2_ovf_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_st:1;
+        /** l1_ibus3_ovf_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_st:1;
+        /** l1_bus0_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_bus0_ovf_int_st:1;
+        /** l1_bus1_ovf_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_bus1_ovf_int_st:1;
+        /** l1_dbus2_ovf_int_st : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_st:1;
+        /** l1_dbus3_ovf_int_st : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l1_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_ena:1;
+        /** l1_icache1_fail_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_ena:1;
+        /** l1_icache2_fail_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_ena:1;
+        /** l1_icache3_fail_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_ena:1;
+        /** l1_cache_fail_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l1_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_clr:1;
+        /** l1_icache1_fail_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_clr:1;
+        /** l1_icache2_fail_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_clr:1;
+        /** l1_icache3_fail_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_clr:1;
+        /** l1_cache_fail_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l1_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_raw:1;
+        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_raw:1;
+        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+         */
+        uint32_t l1_icache2_fail_int_raw:1;
+        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+         */
+        uint32_t l1_icache3_fail_int_raw:1;
+        /** l1_cache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l1_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_int_st:1;
+        /** l1_icache1_fail_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_int_st:1;
+        /** l1_icache2_fail_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_st:1;
+        /** l1_icache3_fail_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_st:1;
+        /** l1_cache_fail_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+         *  to cpu accesses L1-DCache.
+         */
+        uint32_t l1_cache_fail_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_int_st_reg_t;
+
+/** Type of l1_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache0_pld_done_int_ena:1;
+        /** l1_icache1_pld_done_int_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_icache1_pld_done_int_ena:1;
+        /** l1_icache2_pld_done_int_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_ena:1;
+        /** l1_icache3_pld_done_int_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_ena:1;
+        /** l1_cache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation. If preload
+         *  operation is done, interrupt occurs.
+         */
+        uint32_t l1_cache_pld_done_int_ena:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation done.
+         */
+        uint32_t cache_sync_done_int_ena:1;
+        /** l1_icache0_pld_err_int_ena : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_ena:1;
+        /** l1_icache1_pld_err_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_ena:1;
+        /** l1_icache2_pld_err_int_ena : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_ena:1;
+        /** l1_icache3_pld_err_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_ena:1;
+        /** l1_cache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The bit is used to enable interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_ena:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l1_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_clr:1;
+        /** l1_icache1_pld_done_int_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_clr:1;
+        /** l1_icache2_pld_done_int_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_clr:1;
+        /** l1_icache3_pld_done_int_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_clr:1;
+        /** l1_cache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l1_cache_pld_done_int_clr:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+         *  done.
+         */
+        uint32_t cache_sync_done_int_clr:1;
+        /** l1_icache0_pld_err_int_clr : HRO; bitpos: [7]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_clr:1;
+        /** l1_icache1_pld_err_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_clr:1;
+        /** l1_icache2_pld_err_int_clr : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_clr:1;
+        /** l1_icache3_pld_err_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_clr:1;
+        /** l1_cache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
+         *  The bit is used to clear interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_clr:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l1_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache0_pld_done_int_raw:1;
+        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache1_pld_done_int_raw:1;
+        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_raw:1;
+        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_raw:1;
+        /** l1_cache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l1_cache_pld_done_int_raw:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+         */
+        uint32_t cache_sync_done_int_raw:1;
+        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache0_pld_err_int_raw:1;
+        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache1_pld_err_int_raw:1;
+        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_raw:1;
+        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_raw:1;
+        /** l1_cache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_err_int_raw:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+         *  occurs.
+         */
+        uint32_t cache_sync_err_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l1_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_st : HRO; bitpos: [0]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_st:1;
+        /** l1_icache1_pld_done_int_st : HRO; bitpos: [1]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_st:1;
+        /** l1_icache2_pld_done_int_st : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_done_int_st:1;
+        /** l1_icache3_pld_done_int_st : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_done_int_st:1;
+        /** l1_cache_pld_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l1_cache_pld_done_int_st:1;
+        uint32_t reserved_5:1;
+        /** cache_sync_done_int_st : RO; bitpos: [6]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when Cache
+         *  sync-operation is done.
+         */
+        uint32_t cache_sync_done_int_st:1;
+        /** l1_icache0_pld_err_int_st : HRO; bitpos: [7]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_st:1;
+        /** l1_icache1_pld_err_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_st:1;
+        /** l1_icache2_pld_err_int_st : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_int_st:1;
+        /** l1_icache3_pld_err_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_int_st:1;
+        /** l1_cache_pld_err_int_st : RO; bitpos: [11]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-Cache preload-operation error.
+         */
+        uint32_t l1_cache_pld_err_int_st:1;
+        uint32_t reserved_12:1;
+        /** cache_sync_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the status of the interrupt of Cache sync-operation error.
+         */
+        uint32_t cache_sync_err_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_int_st_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_ena:1;
+        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_ena:1;
+        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_ena:1;
+        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_ena:1;
+        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_ena:1;
+        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable interrupt of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_ena:1;
+        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_ena:1;
+        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_clr : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_clr:1;
+        /** l2_ibus1_ovf_int_clr : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_clr:1;
+        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_clr:1;
+        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_clr:1;
+        /** l2_dbus0_ovf_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_clr:1;
+        /** l2_dbus1_ovf_int_clr : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_clr:1;
+        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_clr:1;
+        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-ICache0.
+         */
+        uint32_t l2_ibus0_ovf_int_raw:1;
+        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-ICache1.
+         */
+        uint32_t l2_ibus1_ovf_int_raw:1;
+        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-ICache2.
+         */
+        uint32_t l2_ibus2_ovf_int_raw:1;
+        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-ICache3.
+         */
+        uint32_t l2_ibus3_ovf_int_raw:1;
+        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-DCache.
+         */
+        uint32_t l2_dbus0_ovf_int_raw:1;
+        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-DCache.
+         */
+        uint32_t l2_dbus1_ovf_int_raw:1;
+        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-DCache.
+         */
+        uint32_t l2_dbus2_ovf_int_raw:1;
+        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-DCache.
+         */
+        uint32_t l2_dbus3_ovf_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_st : HRO; bitpos: [8]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_ibus0_ovf_int_st:1;
+        /** l2_ibus1_ovf_int_st : HRO; bitpos: [9]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_ibus1_ovf_int_st:1;
+        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_ovf_int_st:1;
+        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_ovf_int_st:1;
+        /** l2_dbus0_ovf_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         */
+        uint32_t l2_dbus0_ovf_int_st:1;
+        /** l2_dbus1_ovf_int_st : HRO; bitpos: [13]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         */
+        uint32_t l2_dbus1_ovf_int_st:1;
+        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_ovf_int_st:1;
+        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_ovf_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l2_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+         *  l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l2_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+         *  cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l2_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l2_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+         *  to l1 cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_int_st_reg_t;
+
+/** Type of l2_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+         */
+        uint32_t l2_cache_pld_done_int_ena:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l2_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+         *  is done.
+         */
+        uint32_t l2_cache_pld_done_int_clr:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_clr : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l2_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+         *  done.
+         */
+        uint32_t l2_cache_pld_done_int_raw:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_err_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l2_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_st : HRO; bitpos: [5]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+         *  preload-operation is done.
+         */
+        uint32_t l2_cache_pld_done_int_st:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_st : HRO; bitpos: [12]; default: 0;
+         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+         */
+        uint32_t l2_cache_pld_err_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_int_st_reg_t;
+
+
+/** Group: Access Statistics registers */
+/** Type of l1_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_cnt_ena : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to enable ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_ena:1;
+        /** l1_ibus1_cnt_ena : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to enable ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_ena:1;
+        /** l1_ibus2_cnt_ena : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_ena:1;
+        /** l1_ibus3_cnt_ena : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_ena:1;
+        /** l1_bus0_cnt_ena : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to enable dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_ena:1;
+        /** l1_bus1_cnt_ena : R/W; bitpos: [5]; default: 0;
+         *  The bit is used to enable dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_ena:1;
+        /** l1_dbus2_cnt_ena : HRO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_ena:1;
+        /** l1_dbus3_cnt_ena : HRO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_ena:1;
+        uint32_t reserved_8:8;
+        /** l1_ibus0_cnt_clr : HRO; bitpos: [16]; default: 0;
+         *  The bit is used to clear ibus0 counter in L1-ICache0.
+         */
+        uint32_t l1_ibus0_cnt_clr:1;
+        /** l1_ibus1_cnt_clr : HRO; bitpos: [17]; default: 0;
+         *  The bit is used to clear ibus1 counter in L1-ICache1.
+         */
+        uint32_t l1_ibus1_cnt_clr:1;
+        /** l1_ibus2_cnt_clr : HRO; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_clr:1;
+        /** l1_ibus3_cnt_clr : HRO; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_clr:1;
+        /** l1_bus0_cnt_clr : WT; bitpos: [20]; default: 0;
+         *  The bit is used to clear dbus0 counter in L1-DCache.
+         */
+        uint32_t l1_bus0_cnt_clr:1;
+        /** l1_bus1_cnt_clr : WT; bitpos: [21]; default: 0;
+         *  The bit is used to clear dbus1 counter in L1-DCache.
+         */
+        uint32_t l1_bus1_cnt_clr:1;
+        /** l1_dbus2_cnt_clr : HRO; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_clr:1;
+        /** l1_dbus3_cnt_clr : HRO; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_clr:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l1_ibus0_acs_hit_cnt register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_miss_cnt register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_conflict_cnt register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_nxtlvl_cnt register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l1_ibus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_hit_cnt register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_miss_cnt register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_conflict_cnt register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_nxtlvl_cnt register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l1_ibus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_hit_cnt register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_miss_cnt register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_conflict_cnt register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_nxtlvl_cnt register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l1_ibus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_hit_cnt register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_miss_cnt register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_conflict_cnt register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_nxtlvl_cnt register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l1_ibus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_bus0_acs_hit_cnt register
+ *  L1-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus0_acs_miss_cnt register
+ *  L1-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus0_acs_conflict_cnt register
+ *  L1-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-Cache.
+         */
+        uint32_t l1_bus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_bus0_acs_nxtlvl_cnt register
+ *  L1-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus0 accessing L1-Cache.
+         */
+        uint32_t l1_bus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_bus1_acs_hit_cnt register
+ *  L1-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_bus1_acs_miss_cnt register
+ *  L1-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_bus1_acs_conflict_cnt register
+ *  L1-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-Cache.
+         */
+        uint32_t l1_bus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_bus1_acs_nxtlvl_cnt register
+ *  L1-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_bus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-Cache accesses L2-Cache due to
+         *  bus1 accessing L1-Cache.
+         */
+        uint32_t l1_bus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_bus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_hit_cnt register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_miss_cnt register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_conflict_cnt register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_cnt register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_hit_cnt register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_miss_cnt register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_conflict_cnt register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_cnt register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
+         *  The bit is used to enable ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_ena:1;
+        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
+         *  The bit is used to enable ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_ena:1;
+        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_ena:1;
+        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_ena:1;
+        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
+         *  The bit is used to enable dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_ena:1;
+        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
+         *  The bit is used to enable dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_ena:1;
+        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_ena:1;
+        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_ena:1;
+        uint32_t reserved_16:8;
+        /** l2_ibus0_cnt_clr : HRO; bitpos: [24]; default: 0;
+         *  The bit is used to clear ibus0 counter in L2-Cache.
+         */
+        uint32_t l2_ibus0_cnt_clr:1;
+        /** l2_ibus1_cnt_clr : HRO; bitpos: [25]; default: 0;
+         *  The bit is used to clear ibus1 counter in L2-Cache.
+         */
+        uint32_t l2_ibus1_cnt_clr:1;
+        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus2_cnt_clr:1;
+        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_ibus3_cnt_clr:1;
+        /** l2_dbus0_cnt_clr : HRO; bitpos: [28]; default: 0;
+         *  The bit is used to clear dbus0 counter in L2-Cache.
+         */
+        uint32_t l2_dbus0_cnt_clr:1;
+        /** l2_dbus1_cnt_clr : HRO; bitpos: [29]; default: 0;
+         *  The bit is used to clear dbus1 counter in L2-Cache.
+         */
+        uint32_t l2_dbus1_cnt_clr:1;
+        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus2_cnt_clr:1;
+        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
+         *  Reserved
+         */
+        uint32_t l2_dbus3_cnt_clr:1;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l2_ibus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache0 accesses
+         *  L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_nxtlvl_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+         */
+        uint32_t l2_ibus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache1 accesses
+         *  L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_nxtlvl_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+         */
+        uint32_t l2_ibus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache2 accesses
+         *  L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_nxtlvl_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+         */
+        uint32_t l2_ibus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache3 accesses
+         *  L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_nxtlvl_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+         */
+        uint32_t l2_ibus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+         */
+        uint32_t l2_dbus0_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+         */
+        uint32_t l2_dbus1_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+         */
+        uint32_t l2_dbus2_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+         */
+        uint32_t l2_dbus3_nxtlvl_cnt:32;
+    };
+    uint32_t val;
+} extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t;
+
+
+/** Group: Access Fail Debug registers */
+/** Type of l1_icache0_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_id:16;
+        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache0_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache0_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache0_acs_fail_addr_reg_t;
+
+/** Type of l1_icache1_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_id:16;
+        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache1_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache1_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache1_acs_fail_addr_reg_t;
+
+/** Type of l1_icache2_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_id:16;
+        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache2_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache2_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache2_acs_fail_addr_reg_t;
+
+/** Type of l1_icache3_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_id:16;
+        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_icache3_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache3_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_icache3_acs_fail_addr_reg_t;
+
+/** Type of l1_cache_acs_fail_id_attr register
+ *  L1-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_id:16;
+        /** l1_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l1_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l1_dcache_acs_fail_addr register
+ *  L1-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache accesses L1-Cache.
+         */
+        uint32_t l1_cache_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l1_dcache_acs_fail_addr_reg_t;
+
+/** Type of l2_cache_acs_fail_id_attr register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_id:16;
+        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+         *  due to cache accessing L1-Cache.
+         */
+        uint32_t l2_cache_fail_attr:16;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l2_cache_acs_fail_addr register
+ *  L2-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+         */
+        uint32_t l2_cache_fail_addr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_acs_fail_addr_reg_t;
+
+
+/** Group: Operation Exception registers */
+/** Type of l1_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache0.
+         */
+        uint32_t l1_icache0_pld_err_code:2;
+        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache1.
+         */
+        uint32_t l1_icache1_pld_err_code:2;
+        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_err_code:2;
+        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_err_code:2;
+        /** l1_cache_pld_err_code : RO; bitpos: [9:8]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-Cache.
+         */
+        uint32_t l1_cache_pld_err_code:2;
+        uint32_t reserved_10:2;
+        /** cache_sync_err_code : RO; bitpos: [13:12]; default: 0;
+         *  The values 0-2 are available which means sync map, command conflict and size are
+         *  error in Cache System.
+         */
+        uint32_t cache_sync_err_code:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_preload_exception_reg_t;
+
+/** Type of l2_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L2-Cache.
+         */
+        uint32_t l2_cache_pld_err_code:2;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_preload_exception_reg_t;
+
+
+/** Group: Sync Reset control and configuration registers */
+/** Type of l1_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_sync_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache0_sync_rst:1;
+        /** l1_icache1_sync_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache1_sync_rst:1;
+        /** l1_icache2_sync_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_sync_rst:1;
+        /** l1_icache3_sync_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_sync_rst:1;
+        /** l1_cache_sync_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset sync-logic inside L1-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_cache_sync_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_sync_rst_ctrl_reg_t;
+
+/** Type of l2_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+         *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l2_cache_sync_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_sync_rst_ctrl_reg_t;
+
+
+/** Group: Preload Reset control and configuration registers */
+/** Type of l1_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_rst : HRO; bitpos: [0]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache0_pld_rst:1;
+        /** l1_icache1_pld_rst : HRO; bitpos: [1]; default: 0;
+         *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_icache1_pld_rst:1;
+        /** l1_icache2_pld_rst : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_pld_rst:1;
+        /** l1_icache3_pld_rst : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_pld_rst:1;
+        /** l1_cache_pld_rst : R/W; bitpos: [4]; default: 0;
+         *  set this bit to reset preload-logic inside L1-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l1_cache_pld_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_preload_rst_ctrl_reg_t;
+
+/** Type of l2_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
+         *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+         *  only be used to initialize preload-logic when some fatal error of preload-logic
+         *  occurs.
+         */
+        uint32_t l2_cache_pld_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_preload_rst_ctrl_reg_t;
+
+
+/** Group: Autoload buffer clear control and configuration registers */
+/** Type of l1_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_ald_buf_clr : HRO; bitpos: [0]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+         *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+         *  works in L1-ICache0.
+         */
+        uint32_t l1_icache0_ald_buf_clr:1;
+        /** l1_icache1_ald_buf_clr : HRO; bitpos: [1]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+         *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+         *  works in L1-ICache1.
+         */
+        uint32_t l1_icache1_ald_buf_clr:1;
+        /** l1_icache2_ald_buf_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_ald_buf_clr:1;
+        /** l1_icache3_ald_buf_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_ald_buf_clr:1;
+        /** l1_cache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
+         *  set this bit to clear autoload-buffer inside L1-Cache. If this bit is active,
+         *  autoload will not work in L1-Cache. This bit should not be active when autoload
+         *  works in L1-Cache.
+         */
+        uint32_t l1_cache_ald_buf_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_cache_autoload_buf_clr_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
+         *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+         *  autoload will not work in L2-Cache. This bit should not be active when autoload
+         *  works in L2-Cache.
+         */
+        uint32_t l2_cache_ald_buf_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_cache_autoload_buf_clr_ctrl_reg_t;
+
+
+/** Group: Unallocate request buffer clear registers */
+/** Type of l1_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache0_unalloc_clr:1;
+        /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache1_unalloc_clr:1;
+        /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_unalloc_clr:1;
+        /** l1_icache3_unalloc_clr : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_unalloc_clr:1;
+        /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 cache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_cache_unalloc_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} extmem_l1_unallocate_buffer_clear_reg_t;
+
+/** Type of l2_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l2 icache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l2_cache_unalloc_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} extmem_l2_unallocate_buffer_clear_reg_t;
+
+
+/** Group: Tag and Data Memory Access Control and configuration register */
+/** Type of l1_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_object : HRO; bitpos: [0]; default: 0;
+         *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache0_tag_object:1;
+        /** l1_icache1_tag_object : HRO; bitpos: [1]; default: 0;
+         *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_icache1_tag_object:1;
+        /** l1_icache2_tag_object : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_object:1;
+        /** l1_icache3_tag_object : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_object:1;
+        /** l1_cache_tag_object : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to set L1-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_tag_object:1;
+        uint32_t reserved_5:1;
+        /** l1_icache0_mem_object : HRO; bitpos: [6]; default: 0;
+         *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache0_mem_object:1;
+        /** l1_icache1_mem_object : HRO; bitpos: [7]; default: 0;
+         *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+         *  with the others fields inside this register.
+         */
+        uint32_t l1_icache1_mem_object:1;
+        /** l1_icache2_mem_object : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_mem_object:1;
+        /** l1_icache3_mem_object : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_mem_object:1;
+        /** l1_cache_mem_object : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to set L1-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l1_cache_mem_object:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} extmem_l1_cache_object_ctrl_reg_t;
+
+/** Type of l1_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l1_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} extmem_l1_cache_way_object_reg_t;
+
+/** Type of l1_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l1_cache_vaddr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l1_cache_vaddr:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_vaddr_reg_t;
+
+/** Type of l1_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 596;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l1_cache_debug_bus:32;
+    };
+    uint32_t val;
+} extmem_l1_cache_debug_bus_reg_t;
+
+/** Type of l2_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
+         *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_tag_object:1;
+        uint32_t reserved_6:5;
+        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
+         *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+         *  the others fields inside this register.
+         */
+        uint32_t l2_cache_mem_object:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} extmem_l2_cache_object_ctrl_reg_t;
+
+/** Type of l2_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
+         *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+         *  way1, 2: way2, 3: way3, ?, 7: way7.
+         */
+        uint32_t l2_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} extmem_l2_cache_way_object_reg_t;
+
+/** Type of l2_cache_vaddr register
+ *  Cache Vaddr register
+ */
+typedef union {
+    struct {
+        /** l2_cache_vaddr : HRO; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the virtual address which will decide where inside the specified
+         *  tag memory object will be accessed.
+         */
+        uint32_t l2_cache_vaddr:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_vaddr_reg_t;
+
+/** Type of l2_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l2_cache_debug_bus : HRO; bitpos: [31:0]; default: 932;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l2_cache_debug_bus:32;
+    };
+    uint32_t val;
+} extmem_l2_cache_debug_bus_reg_t;
+
+
+/** Group: Split L1 and L2 registers */
+/** Type of level_split0 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split0 : HRO; bitpos: [31:0]; default: 600;
+         *  Reserved
+         */
+        uint32_t level_split0:32;
+    };
+    uint32_t val;
+} extmem_level_split0_reg_t;
+
+/** Type of level_split1 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split1 : HRO; bitpos: [31:0]; default: 936;
+         *  Reserved
+         */
+        uint32_t level_split1:32;
+    };
+    uint32_t val;
+} extmem_level_split1_reg_t;
+
+
+/** Group: L2 cache access attribute control register */
+/** Type of l2_cache_access_attr_ctrl register
+ *  L1 Cache access Attribute propagation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
+         *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+         *  non-cacheable.
+         */
+        uint32_t l2_cache_access_force_cc:1;
+        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+         *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+         *  write-through.
+         */
+        uint32_t l2_cache_access_force_wb:1;
+        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
+         *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  write-miss-allocate and write-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_wma:1;
+        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
+         *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  read-miss-allocate and read-miss-no-allocate.
+         */
+        uint32_t l2_cache_access_force_rma:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} extmem_l2_cache_access_attr_ctrl_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} extmem_clock_gate_reg_t;
+
+
+/** Group: Redundancy  register (Prepare for ECO) */
+/** Type of redundancy_sig0 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig0:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig0_reg_t;
+
+/** Type of redundancy_sig1 register
+ *  Cache redundancy signal 1 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig1:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig1_reg_t;
+
+/** Type of redundancy_sig2 register
+ *  Cache redundancy signal 2 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig2:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig2_reg_t;
+
+/** Type of redundancy_sig3 register
+ *  Cache redundancy signal 3 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig3:32;
+    };
+    uint32_t val;
+} extmem_redundancy_sig3_reg_t;
+
+/** Type of redundancy_sig4 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** cache_redcy_sig4 : RO; bitpos: [3:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         */
+        uint32_t cache_redcy_sig4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} extmem_redundancy_sig4_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35659904;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} extmem_date_reg_t;
+
+
+typedef struct extmem_dev_s {
+    volatile extmem_l1_icache_ctrl_reg_t l1_icache_ctrl;
+    volatile extmem_l1_cache_ctrl_reg_t l1_cache_ctrl;
+    volatile extmem_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
+    volatile extmem_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
+    volatile extmem_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
+    volatile extmem_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
+    volatile extmem_l1_cache_cachesize_conf_reg_t l1_cache_cachesize_conf;
+    volatile extmem_l1_cache_blocksize_conf_reg_t l1_cache_blocksize_conf;
+    volatile extmem_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
+    volatile extmem_l1_cache_tag_mem_power_ctrl_reg_t l1_cache_tag_mem_power_ctrl;
+    volatile extmem_l1_cache_data_mem_power_ctrl_reg_t l1_cache_data_mem_power_ctrl;
+    volatile extmem_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
+    volatile extmem_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
+    volatile extmem_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
+    volatile extmem_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
+    volatile extmem_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
+    volatile extmem_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
+    volatile extmem_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
+    volatile extmem_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
+    volatile extmem_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
+    volatile extmem_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
+    volatile extmem_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
+    volatile extmem_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
+    volatile extmem_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
+    volatile extmem_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
+    volatile extmem_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
+    volatile extmem_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
+    volatile extmem_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
+    volatile extmem_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
+    volatile extmem_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
+    volatile extmem_l1_cache_prelock_conf_reg_t l1_cache_prelock_conf;
+    volatile extmem_l1_cache_prelock_sct0_addr_reg_t l1_cache_prelock_sct0_addr;
+    volatile extmem_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
+    volatile extmem_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
+    volatile extmem_cache_lock_ctrl_reg_t cache_lock_ctrl;
+    volatile extmem_cache_lock_map_reg_t cache_lock_map;
+    volatile extmem_cache_lock_addr_reg_t cache_lock_addr;
+    volatile extmem_cache_lock_size_reg_t cache_lock_size;
+    volatile extmem_cache_sync_ctrl_reg_t cache_sync_ctrl;
+    volatile extmem_cache_sync_map_reg_t cache_sync_map;
+    volatile extmem_cache_sync_addr_reg_t cache_sync_addr;
+    volatile extmem_cache_sync_size_reg_t cache_sync_size;
+    volatile extmem_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
+    volatile extmem_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
+    volatile extmem_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
+    volatile extmem_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
+    volatile extmem_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
+    volatile extmem_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
+    volatile extmem_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
+    volatile extmem_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
+    volatile extmem_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
+    volatile extmem_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
+    volatile extmem_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
+    volatile extmem_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
+    volatile extmem_l1_cache_preload_ctrl_reg_t l1_cache_preload_ctrl;
+    volatile extmem_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
+    volatile extmem_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
+    volatile extmem_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
+    volatile extmem_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
+    volatile extmem_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
+    volatile extmem_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
+    volatile extmem_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
+    volatile extmem_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
+    volatile extmem_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
+    volatile extmem_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
+    volatile extmem_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
+    volatile extmem_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
+    volatile extmem_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
+    volatile extmem_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
+    volatile extmem_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
+    volatile extmem_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
+    volatile extmem_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
+    volatile extmem_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
+    volatile extmem_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
+    volatile extmem_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
+    volatile extmem_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
+    volatile extmem_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
+    volatile extmem_l1_cache_autoload_ctrl_reg_t l1_cache_autoload_ctrl;
+    volatile extmem_l1_cache_autoload_sct0_addr_reg_t l1_cache_autoload_sct0_addr;
+    volatile extmem_l1_cache_autoload_sct0_size_reg_t l1_cache_autoload_sct0_size;
+    volatile extmem_l1_cache_autoload_sct1_addr_reg_t l1_cache_autoload_sct1_addr;
+    volatile extmem_l1_cache_autoload_sct1_size_reg_t l1_cache_autoload_sct1_size;
+    volatile extmem_l1_cache_autoload_sct2_addr_reg_t l1_cache_autoload_sct2_addr;
+    volatile extmem_l1_cache_autoload_sct2_size_reg_t l1_cache_autoload_sct2_size;
+    volatile extmem_l1_cache_autoload_sct3_addr_reg_t l1_cache_autoload_sct3_addr;
+    volatile extmem_l1_cache_autoload_sct3_size_reg_t l1_cache_autoload_sct3_size;
+    volatile extmem_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
+    volatile extmem_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
+    volatile extmem_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
+    volatile extmem_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
+    volatile extmem_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
+    volatile extmem_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
+    volatile extmem_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
+    volatile extmem_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
+    volatile extmem_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
+    volatile extmem_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
+    volatile extmem_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
+    volatile extmem_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
+    volatile extmem_l1_ibus0_acs_nxtlvl_cnt_reg_t l1_ibus0_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
+    volatile extmem_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
+    volatile extmem_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
+    volatile extmem_l1_ibus1_acs_nxtlvl_cnt_reg_t l1_ibus1_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
+    volatile extmem_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
+    volatile extmem_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
+    volatile extmem_l1_ibus2_acs_nxtlvl_cnt_reg_t l1_ibus2_acs_nxtlvl_cnt;
+    volatile extmem_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
+    volatile extmem_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
+    volatile extmem_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
+    volatile extmem_l1_ibus3_acs_nxtlvl_cnt_reg_t l1_ibus3_acs_nxtlvl_cnt;
+    volatile extmem_l1_bus0_acs_hit_cnt_reg_t l1_bus0_acs_hit_cnt;
+    volatile extmem_l1_bus0_acs_miss_cnt_reg_t l1_bus0_acs_miss_cnt;
+    volatile extmem_l1_bus0_acs_conflict_cnt_reg_t l1_bus0_acs_conflict_cnt;
+    volatile extmem_l1_bus0_acs_nxtlvl_cnt_reg_t l1_bus0_acs_nxtlvl_cnt;
+    volatile extmem_l1_bus1_acs_hit_cnt_reg_t l1_bus1_acs_hit_cnt;
+    volatile extmem_l1_bus1_acs_miss_cnt_reg_t l1_bus1_acs_miss_cnt;
+    volatile extmem_l1_bus1_acs_conflict_cnt_reg_t l1_bus1_acs_conflict_cnt;
+    volatile extmem_l1_bus1_acs_nxtlvl_cnt_reg_t l1_bus1_acs_nxtlvl_cnt;
+    volatile extmem_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
+    volatile extmem_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
+    volatile extmem_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
+    volatile extmem_l1_dbus2_acs_nxtlvl_cnt_reg_t l1_dbus2_acs_nxtlvl_cnt;
+    volatile extmem_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
+    volatile extmem_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
+    volatile extmem_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
+    volatile extmem_l1_dbus3_acs_nxtlvl_cnt_reg_t l1_dbus3_acs_nxtlvl_cnt;
+    volatile extmem_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
+    volatile extmem_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
+    volatile extmem_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
+    volatile extmem_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
+    volatile extmem_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
+    volatile extmem_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
+    volatile extmem_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
+    volatile extmem_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
+    volatile extmem_l1_cache_acs_fail_id_attr_reg_t l1_cache_acs_fail_id_attr;
+    volatile extmem_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
+    volatile extmem_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
+    volatile extmem_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
+    volatile extmem_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
+    volatile extmem_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
+    volatile extmem_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
+    volatile extmem_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
+    volatile extmem_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
+    volatile extmem_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
+    volatile extmem_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
+    volatile extmem_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
+    volatile extmem_l1_cache_way_object_reg_t l1_cache_way_object;
+    volatile extmem_l1_cache_vaddr_reg_t l1_cache_vaddr;
+    volatile extmem_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
+    volatile extmem_level_split0_reg_t level_split0;
+    volatile extmem_l2_cache_ctrl_reg_t l2_cache_ctrl;
+    volatile extmem_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
+    volatile extmem_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
+    volatile extmem_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
+    volatile extmem_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
+    volatile extmem_l2_cache_tag_mem_power_ctrl_reg_t l2_cache_tag_mem_power_ctrl;
+    volatile extmem_l2_cache_data_mem_power_ctrl_reg_t l2_cache_data_mem_power_ctrl;
+    volatile extmem_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
+    volatile extmem_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
+    volatile extmem_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
+    volatile extmem_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
+    volatile extmem_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
+    volatile extmem_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
+    volatile extmem_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
+    volatile extmem_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
+    volatile extmem_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
+    volatile extmem_l2_cache_preload_size_reg_t l2_cache_preload_size;
+    volatile extmem_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
+    volatile extmem_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
+    volatile extmem_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
+    volatile extmem_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
+    volatile extmem_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
+    volatile extmem_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
+    volatile extmem_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
+    volatile extmem_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
+    volatile extmem_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
+    volatile extmem_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
+    volatile extmem_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
+    volatile extmem_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
+    volatile extmem_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
+    volatile extmem_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
+    volatile extmem_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
+    volatile extmem_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
+    volatile extmem_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
+    volatile extmem_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
+    volatile extmem_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
+    volatile extmem_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
+    volatile extmem_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
+    volatile extmem_l2_ibus0_acs_nxtlvl_cnt_reg_t l2_ibus0_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
+    volatile extmem_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
+    volatile extmem_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
+    volatile extmem_l2_ibus1_acs_nxtlvl_cnt_reg_t l2_ibus1_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
+    volatile extmem_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
+    volatile extmem_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
+    volatile extmem_l2_ibus2_acs_nxtlvl_cnt_reg_t l2_ibus2_acs_nxtlvl_cnt;
+    volatile extmem_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
+    volatile extmem_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
+    volatile extmem_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
+    volatile extmem_l2_ibus3_acs_nxtlvl_cnt_reg_t l2_ibus3_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
+    volatile extmem_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
+    volatile extmem_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
+    volatile extmem_l2_dbus0_acs_nxtlvl_cnt_reg_t l2_dbus0_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
+    volatile extmem_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
+    volatile extmem_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
+    volatile extmem_l2_dbus1_acs_nxtlvl_cnt_reg_t l2_dbus1_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
+    volatile extmem_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
+    volatile extmem_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
+    volatile extmem_l2_dbus2_acs_nxtlvl_cnt_reg_t l2_dbus2_acs_nxtlvl_cnt;
+    volatile extmem_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
+    volatile extmem_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
+    volatile extmem_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
+    volatile extmem_l2_dbus3_acs_nxtlvl_cnt_reg_t l2_dbus3_acs_nxtlvl_cnt;
+    volatile extmem_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
+    volatile extmem_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
+    volatile extmem_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
+    volatile extmem_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
+    volatile extmem_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
+    volatile extmem_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
+    volatile extmem_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
+    volatile extmem_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
+    volatile extmem_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
+    volatile extmem_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
+    volatile extmem_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
+    volatile extmem_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
+    volatile extmem_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
+    volatile extmem_l2_cache_way_object_reg_t l2_cache_way_object;
+    volatile extmem_l2_cache_vaddr_reg_t l2_cache_vaddr;
+    volatile extmem_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
+    volatile extmem_level_split1_reg_t level_split1;
+    volatile extmem_clock_gate_reg_t clock_gate;
+    volatile extmem_redundancy_sig0_reg_t redundancy_sig0;
+    volatile extmem_redundancy_sig1_reg_t redundancy_sig1;
+    volatile extmem_redundancy_sig2_reg_t redundancy_sig2;
+    volatile extmem_redundancy_sig3_reg_t redundancy_sig3;
+    volatile extmem_redundancy_sig4_reg_t redundancy_sig4;
+    uint32_t reserved_3c4[14];
+    volatile extmem_date_reg_t date;
+} extmem_dev_t;
+
+extern extmem_dev_t EXTMEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(extmem_dev_t) == 0x400, "Invalid size of extmem_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/gdma_reg.h b/components/soc/esp32h2/register/soc/gdma_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/gdma_reg.h
rename to components/soc/esp32h2/register/soc/gdma_reg.h
diff --git a/components/soc/esp32h2/include/soc/gdma_struct.h b/components/soc/esp32h2/register/soc/gdma_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/gdma_struct.h
rename to components/soc/esp32h2/register/soc/gdma_struct.h
diff --git a/components/soc/esp32h2/include/soc/gpio_ext_reg.h b/components/soc/esp32h2/register/soc/gpio_ext_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/gpio_ext_reg.h
rename to components/soc/esp32h2/register/soc/gpio_ext_reg.h
diff --git a/components/soc/esp32h2/include/soc/gpio_ext_struct.h b/components/soc/esp32h2/register/soc/gpio_ext_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/gpio_ext_struct.h
rename to components/soc/esp32h2/register/soc/gpio_ext_struct.h
diff --git a/components/soc/esp32h2/include/soc/gpio_reg.h b/components/soc/esp32h2/register/soc/gpio_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/gpio_reg.h
rename to components/soc/esp32h2/register/soc/gpio_reg.h
diff --git a/components/soc/esp32h2/include/soc/gpio_struct.h b/components/soc/esp32h2/register/soc/gpio_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/gpio_struct.h
rename to components/soc/esp32h2/register/soc/gpio_struct.h
diff --git a/components/soc/esp32h2/include/soc/hmac_reg.h b/components/soc/esp32h2/register/soc/hmac_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/hmac_reg.h
rename to components/soc/esp32h2/register/soc/hmac_reg.h
diff --git a/components/soc/esp32h2/include/soc/hmac_struct.h b/components/soc/esp32h2/register/soc/hmac_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/hmac_struct.h
rename to components/soc/esp32h2/register/soc/hmac_struct.h
diff --git a/components/soc/esp32h2/include/soc/hp_apm_reg.h b/components/soc/esp32h2/register/soc/hp_apm_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/hp_apm_reg.h
rename to components/soc/esp32h2/register/soc/hp_apm_reg.h
diff --git a/components/soc/esp32h2/include/soc/hp_apm_struct.h b/components/soc/esp32h2/register/soc/hp_apm_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/hp_apm_struct.h
rename to components/soc/esp32h2/register/soc/hp_apm_struct.h
diff --git a/components/soc/esp32h2/register/soc/hp_system_reg.h b/components/soc/esp32h2/register/soc/hp_system_reg.h
new file mode 100644
index 00000000000..842750731d8
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/hp_system_reg.h
@@ -0,0 +1,339 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
+ *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
+ */
+#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
+/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
+ */
+#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : HRO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
+#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
+ *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
+ */
+#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
+#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
+#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
+ *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
+ */
+#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+
+/** HP_SYSTEM_SRAM_USAGE_CONF_REG register
+ *  HP memory usage configuration register
+ */
+#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
+/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [14:10]; default: 0;
+ *  0: cpu use hp-memory. 1: mac-dump accessing hp-memory.
+ */
+#define HP_SYSTEM_SRAM_USAGE    0x0000001FU
+#define HP_SYSTEM_SRAM_USAGE_M  (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S)
+#define HP_SYSTEM_SRAM_USAGE_V  0x0000001FU
+#define HP_SYSTEM_SRAM_USAGE_S  10
+/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [24:20]; default: 0;
+ *  reserved.
+ */
+#define HP_SYSTEM_MAC_DUMP_ALLOC    0x0000001FU
+#define HP_SYSTEM_MAC_DUMP_ALLOC_M  (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S)
+#define HP_SYSTEM_MAC_DUMP_ALLOC_V  0x0000001FU
+#define HP_SYSTEM_MAC_DUMP_ALLOC_S  20
+/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define HP_SYSTEM_CACHE_USAGE    (BIT(31))
+#define HP_SYSTEM_CACHE_USAGE_M  (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
+#define HP_SYSTEM_CACHE_USAGE_V  0x00000001U
+#define HP_SYSTEM_CACHE_USAGE_S  31
+
+/** HP_SYSTEM_SEC_DPA_CONF_REG register
+ *  HP anti-DPA security configuration register
+ */
+#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
+/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
+ *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
+ *  the number, the stronger the ability to resist DPA attacks and the higher the
+ *  security level, but it will increase the computational overhead of the hardware
+ *  crypto-accelerators. Only available if HP_SYSTEM_SEC_DPA_CFG_SEL is 0.
+ */
+#define HP_SYSTEM_SEC_DPA_LEVEL    0x00000003U
+#define HP_SYSTEM_SEC_DPA_LEVEL_M  (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
+#define HP_SYSTEM_SEC_DPA_LEVEL_V  0x00000003U
+#define HP_SYSTEM_SEC_DPA_LEVEL_S  0
+/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
+ *  This field is used to select either HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
+ *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYSTEM_SEC_DPA_LEVEL.
+ */
+#define HP_SYSTEM_SEC_DPA_CFG_SEL    (BIT(2))
+#define HP_SYSTEM_SEC_DPA_CFG_SEL_M  (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
+#define HP_SYSTEM_SEC_DPA_CFG_SEL_V  0x00000001U
+#define HP_SYSTEM_SEC_DPA_CFG_SEL_S  2
+
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
+ *  CPU_PERI_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc)
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Set the timeout threshold for bus access, corresponding to the number of clock
+ *  cycles of the clock domain.
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
+ *  Set this bit as 1 to clear timeout interrupt
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S  16
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
+ *  registers
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
+ *  CPU_PERI_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10)
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Record the address information of abnormal access
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
+ *  CPU_PERI_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14)
+/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
+ *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+ *  will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID    0x0000007FU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M  (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V  0x0000007FU
+#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
+ *  HP_PERI_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18)
+/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Set the timeout threshold for bus access, corresponding to the number of clock
+ *  cycles of the clock domain.
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M  (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
+ *  Set this bit as 1 to clear timeout interrupt
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR    (BIT(16))
+#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M  (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V  0x00000001U
+#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S  16
+/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
+ *  HP_PERI_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c)
+/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Record the address information of abnormal access
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M  (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
+ *  HP_PERI_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20)
+/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
+ *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+ *  will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID    0x0000007FU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M  (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V  0x0000007FU
+#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
+ *  Rom-Table lock register
+ */
+#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
+/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
+ *  XXXX
+ */
+#define HP_SYSTEM_ROM_TABLE_LOCK    (BIT(0))
+#define HP_SYSTEM_ROM_TABLE_LOCK_M  (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
+#define HP_SYSTEM_ROM_TABLE_LOCK_V  0x00000001U
+#define HP_SYSTEM_ROM_TABLE_LOCK_S  0
+
+/** HP_SYSTEM_ROM_TABLE_REG register
+ *  Rom-Table register
+ */
+#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
+/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
+ *  XXXX
+ */
+#define HP_SYSTEM_ROM_TABLE    0xFFFFFFFFU
+#define HP_SYSTEM_ROM_TABLE_M  (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
+#define HP_SYSTEM_ROM_TABLE_V  0xFFFFFFFFU
+#define HP_SYSTEM_ROM_TABLE_S  0
+
+/** HP_SYSTEM_MEM_TEST_CONF_REG register
+ *  MEM_TEST configuration register
+ */
+#define HP_SYSTEM_MEM_TEST_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
+/** HP_SYSTEM_HP_MEM_WPULSE : R/W; bitpos: [2:0]; default: 0;
+ *  This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V
+ *  operating Voltage.
+ */
+#define HP_SYSTEM_HP_MEM_WPULSE    0x00000007U
+#define HP_SYSTEM_HP_MEM_WPULSE_M  (HP_SYSTEM_HP_MEM_WPULSE_V << HP_SYSTEM_HP_MEM_WPULSE_S)
+#define HP_SYSTEM_HP_MEM_WPULSE_V  0x00000007U
+#define HP_SYSTEM_HP_MEM_WPULSE_S  0
+/** HP_SYSTEM_HP_MEM_WA : R/W; bitpos: [5:3]; default: 5;
+ *  This field controls hp system memory WA parameter. 0b100 for 1.1V operating
+ *  Voltage, 0b101 for 1.0V, 0b110 for 0.9V.
+ */
+#define HP_SYSTEM_HP_MEM_WA    0x00000007U
+#define HP_SYSTEM_HP_MEM_WA_M  (HP_SYSTEM_HP_MEM_WA_V << HP_SYSTEM_HP_MEM_WA_S)
+#define HP_SYSTEM_HP_MEM_WA_V  0x00000007U
+#define HP_SYSTEM_HP_MEM_WA_S  3
+/** HP_SYSTEM_HP_MEM_RA : R/W; bitpos: [7:6]; default: 0;
+ *  This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating
+ *  Voltage, 0b01 for 0.9V.
+ */
+#define HP_SYSTEM_HP_MEM_RA    0x00000003U
+#define HP_SYSTEM_HP_MEM_RA_M  (HP_SYSTEM_HP_MEM_RA_V << HP_SYSTEM_HP_MEM_RA_S)
+#define HP_SYSTEM_HP_MEM_RA_V  0x00000003U
+#define HP_SYSTEM_HP_MEM_RA_S  6
+/** HP_SYSTEM_HP_MEM_RM : R/W; bitpos: [11:8]; default: 2;
+ *  This field controls hp system memory RM parameter. 0b0011 for 1.1V operating
+ *  Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V.
+ */
+#define HP_SYSTEM_HP_MEM_RM    0x0000000FU
+#define HP_SYSTEM_HP_MEM_RM_M  (HP_SYSTEM_HP_MEM_RM_V << HP_SYSTEM_HP_MEM_RM_S)
+#define HP_SYSTEM_HP_MEM_RM_V  0x0000000FU
+#define HP_SYSTEM_HP_MEM_RM_S  8
+/** HP_SYSTEM_ROM_RM : R/W; bitpos: [15:12]; default: 2;
+ *  This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for
+ *  1.0V, 0b0010(default) or 0b0001(slow) for 0.9V.
+ */
+#define HP_SYSTEM_ROM_RM    0x0000000FU
+#define HP_SYSTEM_ROM_RM_M  (HP_SYSTEM_ROM_RM_V << HP_SYSTEM_ROM_RM_S)
+#define HP_SYSTEM_ROM_RM_V  0x0000000FU
+#define HP_SYSTEM_ROM_RM_S  12
+
+/** HP_SYSTEM_RND_ECO_REG register
+ *  redcy eco register.
+ */
+#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x3e0)
+/** HP_SYSTEM_REDCY_ENA : R/W; bitpos: [0]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define HP_SYSTEM_REDCY_ENA    (BIT(0))
+#define HP_SYSTEM_REDCY_ENA_M  (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
+#define HP_SYSTEM_REDCY_ENA_V  0x00000001U
+#define HP_SYSTEM_REDCY_ENA_S  0
+/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define HP_SYSTEM_REDCY_RESULT    (BIT(1))
+#define HP_SYSTEM_REDCY_RESULT_M  (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
+#define HP_SYSTEM_REDCY_RESULT_V  0x00000001U
+#define HP_SYSTEM_REDCY_RESULT_S  1
+
+/** HP_SYSTEM_RND_ECO_LOW_REG register
+ *  redcy eco low register.
+ */
+#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x3e4)
+/** HP_SYSTEM_REDCY_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  Only reserved for ECO.
+ */
+#define HP_SYSTEM_REDCY_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REDCY_LOW_M  (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
+#define HP_SYSTEM_REDCY_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REDCY_LOW_S  0
+
+/** HP_SYSTEM_RND_ECO_HIGH_REG register
+ *  redcy eco high register.
+ */
+#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x3e8)
+/** HP_SYSTEM_REDCY_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Only reserved for ECO.
+ */
+#define HP_SYSTEM_REDCY_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REDCY_HIGH_M  (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
+#define HP_SYSTEM_REDCY_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REDCY_HIGH_S  0
+
+/** HP_SYSTEM_CLOCK_GATE_REG register
+ *  HP-SYSTEM clock gating configure register
+ */
+#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3f8)
+/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to force on clock gating.
+ */
+#define HP_SYSTEM_CLK_EN    (BIT(0))
+#define HP_SYSTEM_CLK_EN_M  (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)
+#define HP_SYSTEM_CLK_EN_V  0x00000001U
+#define HP_SYSTEM_CLK_EN_S  0
+
+/** HP_SYSTEM_DATE_REG register
+ *  Date register.
+ */
+#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
+/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 35689073;
+ *  HP-SYSTEM date information/ HP-SYSTEM version information.
+ */
+#define HP_SYSTEM_DATE    0x0FFFFFFFU
+#define HP_SYSTEM_DATE_M  (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
+#define HP_SYSTEM_DATE_V  0x0FFFFFFFU
+#define HP_SYSTEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/hp_system_struct.h b/components/soc/esp32h2/register/soc/hp_system_struct.h
new file mode 100644
index 00000000000..4dcaf955003
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/hp_system_struct.h
@@ -0,0 +1,360 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of external_device_encrypt_decrypt_control register
+ *  EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register
+ */
+typedef union {
+    struct {
+        /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode.
+         */
+        uint32_t enable_spi_manual_encrypt:1;
+        /** enable_download_db_encrypt : HRO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t enable_download_db_encrypt:1;
+        /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
+         *  Set this bit as 1 to enable mspi xts auto decrypt in download boot mode.
+         */
+        uint32_t enable_download_g0cb_decrypt:1;
+        /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
+         *  Set this bit as 1 to enable mspi xts manual encrypt in download boot mode.
+         */
+        uint32_t enable_download_manual_encrypt:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_external_device_encrypt_decrypt_control_reg_t;
+
+/** Type of sram_usage_conf register
+ *  HP memory usage configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** sram_usage : R/W; bitpos: [14:10]; default: 0;
+         *  0: cpu use hp-memory. 1: mac-dump accessing hp-memory.
+         */
+        uint32_t sram_usage:5;
+        uint32_t reserved_15:5;
+        /** mac_dump_alloc : R/W; bitpos: [24:20]; default: 0;
+         *  reserved.
+         */
+        uint32_t mac_dump_alloc:5;
+        uint32_t reserved_25:6;
+        /** cache_usage : HRO; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t cache_usage:1;
+    };
+    uint32_t val;
+} hp_sys_sram_usage_conf_reg_t;
+
+/** Type of sec_dpa_conf register
+ *  HP anti-DPA security configuration register
+ */
+typedef union {
+    struct {
+        /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
+         *  0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger
+         *  the number, the stronger the ability to resist DPA attacks and the higher the
+         *  security level, but it will increase the computational overhead of the hardware
+         *  crypto-accelerators. Only available if HP_SYS_SEC_DPA_CFG_SEL is 0.
+         */
+        uint32_t sec_dpa_level:2;
+        /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
+         *  This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL
+         *  (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL.
+         */
+        uint32_t sec_dpa_cfg_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_sec_dpa_conf_reg_t;
+
+/** Type of rom_table_lock register
+ *  Rom-Table lock register
+ */
+typedef union {
+    struct {
+        /** rom_table_lock : R/W; bitpos: [0]; default: 0;
+         *  XXXX
+         */
+        uint32_t rom_table_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_rom_table_lock_reg_t;
+
+/** Type of rom_table register
+ *  Rom-Table register
+ */
+typedef union {
+    struct {
+        /** rom_table : R/W; bitpos: [31:0]; default: 0;
+         *  XXXX
+         */
+        uint32_t rom_table:32;
+    };
+    uint32_t val;
+} hp_sys_rom_table_reg_t;
+
+/** Type of mem_test_conf register
+ *  MEM_TEST configuration register
+ */
+typedef union {
+    struct {
+        /** hp_mem_wpulse : R/W; bitpos: [2:0]; default: 0;
+         *  This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V
+         *  operating Voltage.
+         */
+        uint32_t hp_mem_wpulse:3;
+        /** hp_mem_wa : R/W; bitpos: [5:3]; default: 5;
+         *  This field controls hp system memory WA parameter. 0b100 for 1.1V operating
+         *  Voltage, 0b101 for 1.0V, 0b110 for 0.9V.
+         */
+        uint32_t hp_mem_wa:3;
+        /** hp_mem_ra : R/W; bitpos: [7:6]; default: 0;
+         *  This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating
+         *  Voltage, 0b01 for 0.9V.
+         */
+        uint32_t hp_mem_ra:2;
+        /** hp_mem_rm : R/W; bitpos: [11:8]; default: 2;
+         *  This field controls hp system memory RM parameter. 0b0011 for 1.1V operating
+         *  Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V.
+         */
+        uint32_t hp_mem_rm:4;
+        /** rom_rm : R/W; bitpos: [15:12]; default: 2;
+         *  This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for
+         *  1.0V, 0b0010(default) or 0b0001(slow) for 0.9V.
+         */
+        uint32_t rom_rm:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} hp_sys_mem_test_conf_reg_t;
+
+/** Type of clock_gate register
+ *  HP-SYSTEM clock gating configure register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to force on clock gating.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clock_gate_reg_t;
+
+
+/** Group: Timeout Register */
+/** Type of cpu_peri_timeout_conf register
+ *  CPU_PERI_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Set the timeout threshold for bus access, corresponding to the number of clock
+         *  cycles of the clock domain.
+         */
+        uint32_t cpu_peri_timeout_thres:16;
+        /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
+         *  Set this bit as 1 to clear timeout interrupt
+         */
+        uint32_t cpu_peri_timeout_int_clear:1;
+        /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Set this bit as 1 to enable timeout protection for accessing cpu peripheral
+         *  registers
+         */
+        uint32_t cpu_peri_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_sys_cpu_peri_timeout_conf_reg_t;
+
+/** Type of cpu_peri_timeout_addr register
+ *  CPU_PERI_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Record the address information of abnormal access
+         */
+        uint32_t cpu_peri_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_sys_cpu_peri_timeout_addr_reg_t;
+
+/** Type of cpu_peri_timeout_uid register
+ *  CPU_PERI_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
+         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+         *  will be cleared after the interrupt is cleared.
+         */
+        uint32_t cpu_peri_timeout_uid:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_sys_cpu_peri_timeout_uid_reg_t;
+
+/** Type of hp_peri_timeout_conf register
+ *  HP_PERI_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Set the timeout threshold for bus access, corresponding to the number of clock
+         *  cycles of the clock domain.
+         */
+        uint32_t hp_peri_timeout_thres:16;
+        /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
+         *  Set this bit as 1 to clear timeout interrupt
+         */
+        uint32_t hp_peri_timeout_int_clear:1;
+        /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Set this bit as 1 to enable timeout protection for accessing hp peripheral registers
+         */
+        uint32_t hp_peri_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_sys_hp_peri_timeout_conf_reg_t;
+
+/** Type of hp_peri_timeout_addr register
+ *  HP_PERI_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Record the address information of abnormal access
+         */
+        uint32_t hp_peri_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_sys_hp_peri_timeout_addr_reg_t;
+
+/** Type of hp_peri_timeout_uid register
+ *  HP_PERI_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
+         *  Record master id[4:0] & master permission[6:5] when trigger timeout. This register
+         *  will be cleared after the interrupt is cleared.
+         */
+        uint32_t hp_peri_timeout_uid:7;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_sys_hp_peri_timeout_uid_reg_t;
+
+
+/** Group: Redcy ECO Registers */
+/** Type of rnd_eco register
+ *  redcy eco register.
+ */
+typedef union {
+    struct {
+        /** redcy_ena : R/W; bitpos: [0]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_ena:1;
+        /** redcy_result : RO; bitpos: [1]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_rnd_eco_reg_t;
+
+/** Type of rnd_eco_low register
+ *  redcy eco low register.
+ */
+typedef union {
+    struct {
+        /** redcy_low : R/W; bitpos: [31:0]; default: 0;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_low:32;
+    };
+    uint32_t val;
+} hp_sys_rnd_eco_low_reg_t;
+
+/** Type of rnd_eco_high register
+ *  redcy eco high register.
+ */
+typedef union {
+    struct {
+        /** redcy_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Only reserved for ECO.
+         */
+        uint32_t redcy_high:32;
+    };
+    uint32_t val;
+} hp_sys_rnd_eco_high_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35689073;
+         *  HP-SYSTEM date information/ HP-SYSTEM version information.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_date_reg_t;
+
+
+typedef struct {
+    volatile hp_sys_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
+    volatile hp_sys_sram_usage_conf_reg_t sram_usage_conf;
+    volatile hp_sys_sec_dpa_conf_reg_t sec_dpa_conf;
+    volatile hp_sys_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
+    volatile hp_sys_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
+    volatile hp_sys_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
+    volatile hp_sys_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
+    volatile hp_sys_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
+    volatile hp_sys_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
+    volatile hp_sys_rom_table_lock_reg_t rom_table_lock;
+    volatile hp_sys_rom_table_reg_t rom_table;
+    volatile hp_sys_mem_test_conf_reg_t mem_test_conf;
+    uint32_t reserved_030[236];
+    volatile hp_sys_rnd_eco_reg_t rnd_eco;
+    volatile hp_sys_rnd_eco_low_reg_t rnd_eco_low;
+    volatile hp_sys_rnd_eco_high_reg_t rnd_eco_high;
+    uint32_t reserved_3ec[3];
+    volatile hp_sys_clock_gate_reg_t clock_gate;
+    volatile hp_sys_date_reg_t date;
+} hp_sys_dev_t;
+
+extern hp_sys_dev_t HP_SYSTEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_sys_dev_t) == 0x400, "Invalid size of hp_sys_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/i2c_ana_mst_reg.h
rename to components/soc/esp32h2/register/soc/i2c_ana_mst_reg.h
diff --git a/components/soc/esp32h2/include/soc/i2c_reg.h b/components/soc/esp32h2/register/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/i2c_reg.h
rename to components/soc/esp32h2/register/soc/i2c_reg.h
diff --git a/components/soc/esp32h2/include/soc/i2c_struct.h b/components/soc/esp32h2/register/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/i2c_struct.h
rename to components/soc/esp32h2/register/soc/i2c_struct.h
diff --git a/components/soc/esp32h2/register/soc/i2s_reg.h b/components/soc/esp32h2/register/soc/i2s_reg.h
new file mode 100644
index 00000000000..95b982407e6
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/i2s_reg.h
@@ -0,0 +1,1296 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2S_INT_RAW_REG register
+ *  I2S interrupt raw register, valid in level.
+ */
+#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
+/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_RAW    (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
+#define I2S_RX_DONE_INT_RAW_V  0x00000001U
+#define I2S_RX_DONE_INT_RAW_S  0
+/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_RAW    (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
+#define I2S_TX_DONE_INT_RAW_V  0x00000001U
+#define I2S_TX_DONE_INT_RAW_S  1
+/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_RAW    (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
+#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_RX_HUNG_INT_RAW_S  2
+/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_RAW    (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
+#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_TX_HUNG_INT_RAW_S  3
+
+/** I2S_INT_ST_REG register
+ *  I2S interrupt status register.
+ */
+#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
+/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ST    (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
+#define I2S_RX_DONE_INT_ST_V  0x00000001U
+#define I2S_RX_DONE_INT_ST_S  0
+/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ST    (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
+#define I2S_TX_DONE_INT_ST_V  0x00000001U
+#define I2S_TX_DONE_INT_ST_S  1
+/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ST    (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
+#define I2S_RX_HUNG_INT_ST_V  0x00000001U
+#define I2S_RX_HUNG_INT_ST_S  2
+/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ST    (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
+#define I2S_TX_HUNG_INT_ST_V  0x00000001U
+#define I2S_TX_HUNG_INT_ST_S  3
+
+/** I2S_INT_ENA_REG register
+ *  I2S interrupt enable register.
+ */
+#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
+/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ENA    (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
+#define I2S_RX_DONE_INT_ENA_V  0x00000001U
+#define I2S_RX_DONE_INT_ENA_S  0
+/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ENA    (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
+#define I2S_TX_DONE_INT_ENA_V  0x00000001U
+#define I2S_TX_DONE_INT_ENA_S  1
+/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ENA    (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
+#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_RX_HUNG_INT_ENA_S  2
+/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ENA    (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
+#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_TX_HUNG_INT_ENA_S  3
+
+/** I2S_INT_CLR_REG register
+ *  I2S interrupt clear register.
+ */
+#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
+/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_CLR    (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
+#define I2S_RX_DONE_INT_CLR_V  0x00000001U
+#define I2S_RX_DONE_INT_CLR_S  0
+/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_CLR    (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
+#define I2S_TX_DONE_INT_CLR_V  0x00000001U
+#define I2S_TX_DONE_INT_CLR_S  1
+/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_CLR    (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
+#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_RX_HUNG_INT_CLR_S  2
+/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_CLR    (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
+#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_TX_HUNG_INT_CLR_S  3
+
+/** I2S_RX_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
+/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset receiver
+ */
+#define I2S_RX_RESET    (BIT(0))
+#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
+#define I2S_RX_RESET_V  0x00000001U
+#define I2S_RX_RESET_S  0
+/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Rx AFIFO
+ */
+#define I2S_RX_FIFO_RESET    (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
+#define I2S_RX_FIFO_RESET_V  0x00000001U
+#define I2S_RX_FIFO_RESET_S  1
+/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start receiving data
+ */
+#define I2S_RX_START    (BIT(2))
+#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
+#define I2S_RX_START_V  0x00000001U
+#define I2S_RX_START_S  2
+/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave receiver mode
+ */
+#define I2S_RX_SLAVE_MOD    (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
+#define I2S_RX_SLAVE_MOD_V  0x00000001U
+#define I2S_RX_SLAVE_MOD_S  3
+/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+ *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+ */
+#define I2S_RX_STOP_MODE    0x00000003U
+#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
+#define I2S_RX_STOP_MODE_V  0x00000003U
+#define I2S_RX_STOP_MODE_S  4
+/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable receiver  in mono mode
+ */
+#define I2S_RX_MONO    (BIT(6))
+#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
+#define I2S_RX_MONO_V  0x00000001U
+#define I2S_RX_MONO_S  6
+/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+ */
+#define I2S_RX_BIG_ENDIAN    (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
+#define I2S_RX_BIG_ENDIAN_V  0x00000001U
+#define I2S_RX_BIG_ENDIAN_S  7
+/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_RX_UPDATE    (BIT(8))
+#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
+#define I2S_RX_UPDATE_V  0x00000001U
+#define I2S_RX_UPDATE_S  8
+/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+ *  channel data value is valid in I2S RX mono mode.
+ */
+#define I2S_RX_MONO_FST_VLD    (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
+#define I2S_RX_MONO_FST_VLD_V  0x00000001U
+#define I2S_RX_MONO_FST_VLD_S  9
+/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
+ *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_RX_PCM_CONF    0x00000003U
+#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
+#define I2S_RX_PCM_CONF_V  0x00000003U
+#define I2S_RX_PCM_CONF_S  10
+/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass Compress/Decompress module for received data.
+ */
+#define I2S_RX_PCM_BYPASS    (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
+#define I2S_RX_PCM_BYPASS_V  0x00000001U
+#define I2S_RX_PCM_BYPASS_S  12
+/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable receiver in Phillips standard mode
+ */
+#define I2S_RX_MSB_SHIFT    (BIT(13))
+#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
+#define I2S_RX_MSB_SHIFT_V  0x00000001U
+#define I2S_RX_MSB_SHIFT_S  13
+/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+ */
+#define I2S_RX_LEFT_ALIGN    (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
+#define I2S_RX_LEFT_ALIGN_V  0x00000001U
+#define I2S_RX_LEFT_ALIGN_S  15
+/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+ */
+#define I2S_RX_24_FILL_EN    (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
+#define I2S_RX_24_FILL_EN_V  0x00000001U
+#define I2S_RX_24_FILL_EN_S  16
+/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+ *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+ */
+#define I2S_RX_WS_IDLE_POL    (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
+#define I2S_RX_WS_IDLE_POL_V  0x00000001U
+#define I2S_RX_WS_IDLE_POL_S  17
+/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+ *  is received first.
+ */
+#define I2S_RX_BIT_ORDER    (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
+#define I2S_RX_BIT_ORDER_V  0x00000001U
+#define I2S_RX_BIT_ORDER_S  18
+/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_TDM_EN    (BIT(19))
+#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
+#define I2S_RX_TDM_EN_V  0x00000001U
+#define I2S_RX_TDM_EN_S  19
+/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_PDM_EN    (BIT(20))
+#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
+#define I2S_RX_PDM_EN_V  0x00000001U
+#define I2S_RX_PDM_EN_S  20
+/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in receiver mode.
+ */
+#define I2S_RX_BCK_DIV_NUM    0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
+#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_S  21
+
+/** I2S_TX_CONF_REG register
+ *  I2S TX configure register
+ */
+#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
+/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset transmitter
+ */
+#define I2S_TX_RESET    (BIT(0))
+#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
+#define I2S_TX_RESET_V  0x00000001U
+#define I2S_TX_RESET_S  0
+/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Tx AFIFO
+ */
+#define I2S_TX_FIFO_RESET    (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
+#define I2S_TX_FIFO_RESET_V  0x00000001U
+#define I2S_TX_FIFO_RESET_S  1
+/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start transmitting data
+ */
+#define I2S_TX_START    (BIT(2))
+#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
+#define I2S_TX_START_V  0x00000001U
+#define I2S_TX_START_S  2
+/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave transmitter mode
+ */
+#define I2S_TX_SLAVE_MOD    (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
+#define I2S_TX_SLAVE_MOD_V  0x00000001U
+#define I2S_TX_SLAVE_MOD_S  3
+/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+ */
+#define I2S_TX_STOP_EN    (BIT(4))
+#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
+#define I2S_TX_STOP_EN_V  0x00000001U
+#define I2S_TX_STOP_EN_S  4
+/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
+ *  1: The value of Left channel data is equal to the value of right channel data in
+ *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+ *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+ */
+#define I2S_TX_CHAN_EQUAL    (BIT(5))
+#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
+#define I2S_TX_CHAN_EQUAL_V  0x00000001U
+#define I2S_TX_CHAN_EQUAL_S  5
+/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter in mono mode
+ */
+#define I2S_TX_MONO    (BIT(6))
+#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
+#define I2S_TX_MONO_V  0x00000001U
+#define I2S_TX_MONO_S  6
+/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+ *  value.
+ */
+#define I2S_TX_BIG_ENDIAN    (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
+#define I2S_TX_BIG_ENDIAN_V  0x00000001U
+#define I2S_TX_BIG_ENDIAN_S  7
+/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_TX_UPDATE    (BIT(8))
+#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
+#define I2S_TX_UPDATE_V  0x00000001U
+#define I2S_TX_UPDATE_S  8
+/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+ *  channel data value is valid in I2S TX mono mode.
+ */
+#define I2S_TX_MONO_FST_VLD    (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
+#define I2S_TX_MONO_FST_VLD_V  0x00000001U
+#define I2S_TX_MONO_FST_VLD_S  9
+/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
+ *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_TX_PCM_CONF    0x00000003U
+#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
+#define I2S_TX_PCM_CONF_V  0x00000003U
+#define I2S_TX_PCM_CONF_S  10
+/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+ */
+#define I2S_TX_PCM_BYPASS    (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
+#define I2S_TX_PCM_BYPASS_V  0x00000001U
+#define I2S_TX_PCM_BYPASS_S  12
+/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable transmitter in Phillips standard mode
+ */
+#define I2S_TX_MSB_SHIFT    (BIT(13))
+#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
+#define I2S_TX_MSB_SHIFT_V  0x00000001U
+#define I2S_TX_MSB_SHIFT_S  13
+/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
+ *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+ *  generate pos/neg edge in master mode.
+ */
+#define I2S_TX_BCK_NO_DLY    (BIT(14))
+#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
+#define I2S_TX_BCK_NO_DLY_V  0x00000001U
+#define I2S_TX_BCK_NO_DLY_S  14
+/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+ */
+#define I2S_TX_LEFT_ALIGN    (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
+#define I2S_TX_LEFT_ALIGN_V  0x00000001U
+#define I2S_TX_LEFT_ALIGN_S  15
+/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+ */
+#define I2S_TX_24_FILL_EN    (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
+#define I2S_TX_24_FILL_EN_V  0x00000001U
+#define I2S_TX_24_FILL_EN_S  16
+/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+ *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+ */
+#define I2S_TX_WS_IDLE_POL    (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
+#define I2S_TX_WS_IDLE_POL_V  0x00000001U
+#define I2S_TX_WS_IDLE_POL_S  17
+/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+ *  sent first.
+ */
+#define I2S_TX_BIT_ORDER    (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
+#define I2S_TX_BIT_ORDER_V  0x00000001U
+#define I2S_TX_BIT_ORDER_S  18
+/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_TDM_EN    (BIT(19))
+#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
+#define I2S_TX_TDM_EN_V  0x00000001U
+#define I2S_TX_TDM_EN_S  19
+/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_PDM_EN    (BIT(20))
+#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
+#define I2S_TX_PDM_EN_V  0x00000001U
+#define I2S_TX_PDM_EN_S  20
+/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in transmitter mode.
+ */
+#define I2S_TX_BCK_DIV_NUM    0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
+#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_S  21
+/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
+ *  I2S transmitter channel mode configuration bits.
+ */
+#define I2S_TX_CHAN_MOD    0x00000007U
+#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
+#define I2S_TX_CHAN_MOD_V  0x00000007U
+#define I2S_TX_CHAN_MOD_S  27
+/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
+ *  Enable signal loop back mode with transmitter module and receiver module sharing
+ *  the same WS and BCK signals.
+ */
+#define I2S_SIG_LOOPBACK    (BIT(30))
+#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
+#define I2S_SIG_LOOPBACK_V  0x00000001U
+#define I2S_SIG_LOOPBACK_S  30
+
+/** I2S_RX_CONF1_REG register
+ *  I2S RX configure register 1
+ */
+#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
+/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
+#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_S  0
+/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+ *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_RX_BITS_MOD    0x0000001FU
+#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
+#define I2S_RX_BITS_MOD_V  0x0000001FU
+#define I2S_RX_BITS_MOD_S  14
+/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Rx half sample bits -1.
+ */
+#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_S  19
+/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Rx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
+#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_CONF1_REG register
+ *  I2S TX configure register 1
+ */
+#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
+/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
+#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_S  0
+/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+ *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_TX_BITS_MOD    0x0000001FU
+#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
+#define I2S_TX_BITS_MOD_V  0x0000001FU
+#define I2S_TX_BITS_MOD_S  14
+/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Tx half sample bits -1.
+ */
+#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_S  19
+/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Tx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
+#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_S  27
+
+/** I2S_RX_CLKM_CONF_REG register
+ *  I2S RX clock configure register
+ */
+#define I2S_RX_CLKM_CONF_REG (DR_REG_I2S_BASE + 0x30)
+/** I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
+ *  Integral I2S clock divider value
+ */
+#define I2S_RX_CLKM_DIV_NUM    0x000000FFU
+#define I2S_RX_CLKM_DIV_NUM_M  (I2S_RX_CLKM_DIV_NUM_V << I2S_RX_CLKM_DIV_NUM_S)
+#define I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
+#define I2S_RX_CLKM_DIV_NUM_S  0
+/** I2S_RX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0;
+ *  I2S Rx module clock enable signal.
+ */
+#define I2S_RX_CLK_ACTIVE    (BIT(26))
+#define I2S_RX_CLK_ACTIVE_M  (I2S_RX_CLK_ACTIVE_V << I2S_RX_CLK_ACTIVE_S)
+#define I2S_RX_CLK_ACTIVE_V  0x00000001U
+#define I2S_RX_CLK_ACTIVE_S  26
+/** I2S_RX_CLK_SEL : R/W; bitpos: [28:27]; default: 0;
+ *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+ */
+#define I2S_RX_CLK_SEL    0x00000003U
+#define I2S_RX_CLK_SEL_M  (I2S_RX_CLK_SEL_V << I2S_RX_CLK_SEL_S)
+#define I2S_RX_CLK_SEL_V  0x00000003U
+#define I2S_RX_CLK_SEL_S  27
+/** I2S_MCLK_SEL : R/W; bitpos: [29]; default: 0;
+ *  0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as
+ *  I2S_MCLK_OUT.
+ */
+#define I2S_MCLK_SEL    (BIT(29))
+#define I2S_MCLK_SEL_M  (I2S_MCLK_SEL_V << I2S_MCLK_SEL_S)
+#define I2S_MCLK_SEL_V  0x00000001U
+#define I2S_MCLK_SEL_S  29
+
+/** I2S_TX_CLKM_CONF_REG register
+ *  I2S TX clock configure register
+ */
+#define I2S_TX_CLKM_CONF_REG (DR_REG_I2S_BASE + 0x34)
+/** I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
+ *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
+ *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
+ *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+ *  (n+1)-div] + y * (n+1)-div.
+ */
+#define I2S_TX_CLKM_DIV_NUM    0x000000FFU
+#define I2S_TX_CLKM_DIV_NUM_M  (I2S_TX_CLKM_DIV_NUM_V << I2S_TX_CLKM_DIV_NUM_S)
+#define I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
+#define I2S_TX_CLKM_DIV_NUM_S  0
+/** I2S_TX_CLK_ACTIVE : R/W; bitpos: [26]; default: 0;
+ *  I2S Tx module clock enable signal.
+ */
+#define I2S_TX_CLK_ACTIVE    (BIT(26))
+#define I2S_TX_CLK_ACTIVE_M  (I2S_TX_CLK_ACTIVE_V << I2S_TX_CLK_ACTIVE_S)
+#define I2S_TX_CLK_ACTIVE_V  0x00000001U
+#define I2S_TX_CLK_ACTIVE_S  26
+/** I2S_TX_CLK_SEL : R/W; bitpos: [28:27]; default: 0;
+ *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+ *  I2S_MCLK_in.
+ */
+#define I2S_TX_CLK_SEL    0x00000003U
+#define I2S_TX_CLK_SEL_M  (I2S_TX_CLK_SEL_V << I2S_TX_CLK_SEL_S)
+#define I2S_TX_CLK_SEL_V  0x00000003U
+#define I2S_TX_CLK_SEL_S  27
+/** I2S_CLK_EN : R/W; bitpos: [29]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define I2S_CLK_EN    (BIT(29))
+#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
+#define I2S_CLK_EN_V  0x00000001U
+#define I2S_CLK_EN_S  29
+
+/** I2S_RX_CLKM_DIV_CONF_REG register
+ *  I2S RX module clock divider configure register
+ */
+#define I2S_RX_CLKM_DIV_CONF_REG (DR_REG_I2S_BASE + 0x38)
+/** I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Z is (a-b).
+ */
+#define I2S_RX_CLKM_DIV_Z    0x000001FFU
+#define I2S_RX_CLKM_DIV_Z_M  (I2S_RX_CLKM_DIV_Z_V << I2S_RX_CLKM_DIV_Z_S)
+#define I2S_RX_CLKM_DIV_Z_V  0x000001FFU
+#define I2S_RX_CLKM_DIV_Z_S  0
+/** I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define I2S_RX_CLKM_DIV_Y    0x000001FFU
+#define I2S_RX_CLKM_DIV_Y_M  (I2S_RX_CLKM_DIV_Y_V << I2S_RX_CLKM_DIV_Y_S)
+#define I2S_RX_CLKM_DIV_Y_V  0x000001FFU
+#define I2S_RX_CLKM_DIV_Y_S  9
+/** I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define I2S_RX_CLKM_DIV_X    0x000001FFU
+#define I2S_RX_CLKM_DIV_X_M  (I2S_RX_CLKM_DIV_X_V << I2S_RX_CLKM_DIV_X_S)
+#define I2S_RX_CLKM_DIV_X_V  0x000001FFU
+#define I2S_RX_CLKM_DIV_X_S  18
+/** I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_YN1 is 1.
+ */
+#define I2S_RX_CLKM_DIV_YN1    (BIT(27))
+#define I2S_RX_CLKM_DIV_YN1_M  (I2S_RX_CLKM_DIV_YN1_V << I2S_RX_CLKM_DIV_YN1_S)
+#define I2S_RX_CLKM_DIV_YN1_V  0x00000001U
+#define I2S_RX_CLKM_DIV_YN1_S  27
+
+/** I2S_TX_CLKM_DIV_CONF_REG register
+ *  I2S TX module clock divider configure register
+ */
+#define I2S_TX_CLKM_DIV_CONF_REG (DR_REG_I2S_BASE + 0x3c)
+/** I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Z is (a-b).
+ */
+#define I2S_TX_CLKM_DIV_Z    0x000001FFU
+#define I2S_TX_CLKM_DIV_Z_M  (I2S_TX_CLKM_DIV_Z_V << I2S_TX_CLKM_DIV_Z_S)
+#define I2S_TX_CLKM_DIV_Z_V  0x000001FFU
+#define I2S_TX_CLKM_DIV_Z_S  0
+/** I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define I2S_TX_CLKM_DIV_Y    0x000001FFU
+#define I2S_TX_CLKM_DIV_Y_M  (I2S_TX_CLKM_DIV_Y_V << I2S_TX_CLKM_DIV_Y_S)
+#define I2S_TX_CLKM_DIV_Y_V  0x000001FFU
+#define I2S_TX_CLKM_DIV_Y_S  9
+/** I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define I2S_TX_CLKM_DIV_X    0x000001FFU
+#define I2S_TX_CLKM_DIV_X_M  (I2S_TX_CLKM_DIV_X_V << I2S_TX_CLKM_DIV_X_S)
+#define I2S_TX_CLKM_DIV_X_V  0x000001FFU
+#define I2S_TX_CLKM_DIV_X_S  18
+/** I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_YN1 is 1.
+ */
+#define I2S_TX_CLKM_DIV_YN1    (BIT(27))
+#define I2S_TX_CLKM_DIV_YN1_M  (I2S_TX_CLKM_DIV_YN1_V << I2S_TX_CLKM_DIV_YN1_S)
+#define I2S_TX_CLKM_DIV_YN1_V  0x00000001U
+#define I2S_TX_CLKM_DIV_YN1_S  27
+
+/** I2S_TX_PCM2PDM_CONF_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x40)
+/** I2S_TX_PDM_HP_BYPASS : R/W; bitpos: [0]; default: 0;
+ *  I2S TX PDM bypass hp filter or not. The option has been removed.
+ */
+#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_M  (I2S_TX_PDM_HP_BYPASS_V << I2S_TX_PDM_HP_BYPASS_S)
+#define I2S_TX_PDM_HP_BYPASS_V  0x00000001U
+#define I2S_TX_PDM_HP_BYPASS_S  0
+/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
+ *  I2S TX PDM OSR2 value
+ */
+#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
+#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
+ *  I2S TX PDM prescale for sigmadelta
+ */
+#define I2S_TX_PDM_PRESCALE    0x000000FFU
+#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
+#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
+#define I2S_TX_PDM_PRESCALE_S  5
+/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
+ *  I2S TX PDM sigmadelta dither2 value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
+ *  I2S TX PDM sigmadelta dither value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
+ *  I2S TX PDM dac mode enable
+ */
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
+ *  I2S TX PDM dac 2channel enable
+ */
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
+ *  I2S TX PDM Converter enable
+ */
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
+#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
+#define I2S_PCM2PDM_CONV_EN_S  25
+
+/** I2S_TX_PCM2PDM_CONF1_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x44)
+/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
+ *  I2S TX PDM Fp
+ */
+#define I2S_TX_PDM_FP    0x000003FFU
+#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
+#define I2S_TX_PDM_FP_V  0x000003FFU
+#define I2S_TX_PDM_FP_S  0
+/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
+ *  I2S TX PDM Fs
+ */
+#define I2S_TX_PDM_FS    0x000003FFU
+#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
+#define I2S_TX_PDM_FS_V  0x000003FFU
+#define I2S_TX_PDM_FS_S  10
+/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
+#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
+#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+
+/** I2S_RX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
+/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
+#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
+#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
+#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
+#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
+#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
+#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
+#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
+#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+
+/** I2S_TX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
+/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
+#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN0_EN_S  0
+/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
+#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
+#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
+#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
+#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
+#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
+#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
+#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
+#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
+#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
+#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
+#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
+#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
+#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
+#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
+#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
+ *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+ *  only the data of the enabled channels is sent, then this bit should be set. Clear
+ *  it when all the data stored in DMA TX buffer is for enabled channels.
+ */
+#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+
+/** I2S_RX_TIMING_REG register
+ *  I2S RX timing control register
+ */
+#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
+/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD_IN_DM    0x00000003U
+#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
+#define I2S_RX_SD_IN_DM_V  0x00000003U
+#define I2S_RX_SD_IN_DM_S  0
+/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_OUT_DM    0x00000003U
+#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
+#define I2S_RX_WS_OUT_DM_V  0x00000003U
+#define I2S_RX_WS_OUT_DM_S  16
+/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_OUT_DM    0x00000003U
+#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
+#define I2S_RX_BCK_OUT_DM_V  0x00000003U
+#define I2S_RX_BCK_OUT_DM_S  20
+/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_IN_DM    0x00000003U
+#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
+#define I2S_RX_WS_IN_DM_V  0x00000003U
+#define I2S_RX_WS_IN_DM_S  24
+/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_IN_DM    0x00000003U
+#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
+#define I2S_RX_BCK_IN_DM_V  0x00000003U
+#define I2S_RX_BCK_IN_DM_S  28
+
+/** I2S_TX_TIMING_REG register
+ *  I2S TX timing control register
+ */
+#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
+/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD_OUT_DM    0x00000003U
+#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
+#define I2S_TX_SD_OUT_DM_V  0x00000003U
+#define I2S_TX_SD_OUT_DM_S  0
+/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD1_OUT_DM    0x00000003U
+#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
+#define I2S_TX_SD1_OUT_DM_V  0x00000003U
+#define I2S_TX_SD1_OUT_DM_S  4
+/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_OUT_DM    0x00000003U
+#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
+#define I2S_TX_WS_OUT_DM_V  0x00000003U
+#define I2S_TX_WS_OUT_DM_S  16
+/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_OUT_DM    0x00000003U
+#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
+#define I2S_TX_BCK_OUT_DM_V  0x00000003U
+#define I2S_TX_BCK_OUT_DM_S  20
+/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_IN_DM    0x00000003U
+#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
+#define I2S_TX_WS_IN_DM_V  0x00000003U
+#define I2S_TX_WS_IN_DM_S  24
+/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_IN_DM    0x00000003U
+#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
+#define I2S_TX_BCK_IN_DM_V  0x00000003U
+#define I2S_TX_BCK_IN_DM_S  28
+
+/** I2S_LC_HUNG_CONF_REG register
+ *  I2S HUNG configure register.
+ */
+#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
+/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ *  when fifo hung counter is equal to this value
+ */
+#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
+#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_S  0
+/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  The bits are used to scale tick counter threshold. The tick counter is reset when
+ *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+ */
+#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  The enable bit for FIFO timeout
+ */
+#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+
+/** I2S_RXEOF_NUM_REG register
+ *  I2S RX data number control register.
+ */
+#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
+/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
+ *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+ *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+ */
+#define I2S_RX_EOF_NUM    0x00000FFFU
+#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
+#define I2S_RX_EOF_NUM_V  0x00000FFFU
+#define I2S_RX_EOF_NUM_S  0
+
+/** I2S_CONF_SIGLE_DATA_REG register
+ *  I2S signal data register
+ */
+#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
+/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The configured constant channel data to be sent out.
+ */
+#define I2S_SINGLE_DATA    0xFFFFFFFFU
+#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
+#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
+#define I2S_SINGLE_DATA_S  0
+
+/** I2S_STATE_REG register
+ *  I2S TX status register
+ */
+#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
+/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
+ *  1: i2s_tx is idle state. 0: i2s_tx is working.
+ */
+#define I2S_TX_IDLE    (BIT(0))
+#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
+#define I2S_TX_IDLE_V  0x00000001U
+#define I2S_TX_IDLE_S  0
+
+/** I2S_ETM_CONF_REG register
+ *  I2S ETM configure register
+ */
+#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
+/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
+ *  I2S ETM send x words event. When sending word number of
+ *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
+#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_S  0
+/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
+ *  I2S ETM receive x words event. When receiving word number of
+ *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
+
+/** I2S_DATE_REG register
+ *  Version control register
+ */
+#define I2S_DATE_REG (DR_REG_I2S_BASE + 0x80)
+/** I2S_DATE : R/W; bitpos: [27:0]; default: 35684944;
+ *  I2S version control register
+ */
+#define I2S_DATE    0x0FFFFFFFU
+#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
+#define I2S_DATE_V  0x0FFFFFFFU
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/i2s_struct.h b/components/soc/esp32h2/register/soc/i2s_struct.h
new file mode 100644
index 00000000000..0a01bf6f670
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/i2s_struct.h
@@ -0,0 +1,900 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_14:1;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t rx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:8;
+        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
+         *  I2S TX PDM bypass hp filter or not. The option has been removed.
+         */
+        uint32_t tx_pdm_hp_bypass:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rx_eof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_rx_eof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [30]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t tx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:8;
+        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:14;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_single_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_single_data_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:10;
+        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35684944;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    uint32_t reserved_030[4];
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    uint32_t reserved_048[2];
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rx_eof_num_reg_t rx_eof_num;
+    volatile i2s_conf_single_data_reg_t conf_single_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    uint32_t reserved_074[3];
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+extern i2s_dev_t I2S0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/ieee802154_reg.h b/components/soc/esp32h2/register/soc/ieee802154_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/ieee802154_reg.h
rename to components/soc/esp32h2/register/soc/ieee802154_reg.h
diff --git a/components/soc/esp32h2/include/soc/ieee802154_struct.h b/components/soc/esp32h2/register/soc/ieee802154_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/ieee802154_struct.h
rename to components/soc/esp32h2/register/soc/ieee802154_struct.h
diff --git a/components/soc/esp32h2/register/soc/interrupt_matrix_reg.h b/components/soc/esp32h2/register/soc/interrupt_matrix_reg.h
new file mode 100644
index 00000000000..c526cacc8bc
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/interrupt_matrix_reg.h
@@ -0,0 +1,856 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+// #include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** INTMTX_CORE0_PMU_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x0)
+/** INTMTX_CORE0_PMU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_PMU_INTR mapping register
+ */
+#define INTMTX_CORE0_PMU_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PMU_INTR_MAP_M  (INTMTX_CORE0_PMU_INTR_MAP_V << INTMTX_CORE0_PMU_INTR_MAP_S)
+#define INTMTX_CORE0_PMU_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PMU_INTR_MAP_S  0
+
+/** INTMTX_CORE0_EFUSE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4)
+/** INTMTX_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_EFUSE_INTR mapping register
+ */
+#define INTMTX_CORE0_EFUSE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_EFUSE_INTR_MAP_M  (INTMTX_CORE0_EFUSE_INTR_MAP_V << INTMTX_CORE0_EFUSE_INTR_MAP_S)
+#define INTMTX_CORE0_EFUSE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_EFUSE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8)
+/** INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_LP_RTC_TIMER_INTR mapping register
+ */
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_RTC_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc)
+/** INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_LP_BLE_TIMER_INTR mapping register
+ */
+#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_M  (INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_BLE_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10)
+/** INTMTX_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_LP_WDT_INTR mapping register
+ */
+#define INTMTX_CORE0_LP_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_M  (INTMTX_CORE0_LP_WDT_INTR_MAP_V << INTMTX_CORE0_LP_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x14)
+/** INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_LP_PERI_TIMEOUT_INTR mapping register
+ */
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x18)
+/** INTMTX_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_LP_APM_M0_INTR mapping register
+ */
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_LP_APM_M0_INTR_MAP_V << INTMTX_CORE0_LP_APM_M0_INTR_MAP_S)
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LP_APM_M0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x1c)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_CPU_INTR_FROM_CPU_0 mapping register
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x20)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_CPU_INTR_FROM_CPU_1 mapping register
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x24)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_CPU_INTR_FROM_CPU_2 mapping register
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
+
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x28)
+/** INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_CPU_INTR_FROM_CPU_3 mapping register
+ */
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
+
+/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x2c)
+/** INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_ASSIST_DEBUG_INTR mapping register
+ */
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_M  (INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S)
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TRACE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x30)
+/** INTMTX_CORE0_TRACE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_TRACE_INTR mapping register
+ */
+#define INTMTX_CORE0_TRACE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TRACE_INTR_MAP_M  (INTMTX_CORE0_TRACE_INTR_MAP_V << INTMTX_CORE0_TRACE_INTR_MAP_S)
+#define INTMTX_CORE0_TRACE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TRACE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CACHE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x34)
+/** INTMTX_CORE0_CACHE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_CACHE_INTR mapping register
+ */
+#define INTMTX_CORE0_CACHE_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CACHE_INTR_MAP_M  (INTMTX_CORE0_CACHE_INTR_MAP_V << INTMTX_CORE0_CACHE_INTR_MAP_S)
+#define INTMTX_CORE0_CACHE_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CACHE_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x38)
+/** INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_CPU_PERI_TIMEOUT_INTR mapping register
+ */
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x3c)
+/** INTMTX_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_BT_MAC_INTR mapping register
+ */
+#define INTMTX_CORE0_BT_MAC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_M  (INTMTX_CORE0_BT_MAC_INTR_MAP_V << INTMTX_CORE0_BT_MAC_INTR_MAP_S)
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_MAC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_BB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x40)
+/** INTMTX_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_BT_BB_INTR mapping register
+ */
+#define INTMTX_CORE0_BT_BB_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_BB_INTR_MAP_M  (INTMTX_CORE0_BT_BB_INTR_MAP_V << INTMTX_CORE0_BT_BB_INTR_MAP_S)
+#define INTMTX_CORE0_BT_BB_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_BB_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BT_BB_NMI_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x44)
+/** INTMTX_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_BT_BB_NMI mapping register
+ */
+#define INTMTX_CORE0_BT_BB_NMI_MAP    0x0000001FU
+#define INTMTX_CORE0_BT_BB_NMI_MAP_M  (INTMTX_CORE0_BT_BB_NMI_MAP_V << INTMTX_CORE0_BT_BB_NMI_MAP_S)
+#define INTMTX_CORE0_BT_BB_NMI_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BT_BB_NMI_MAP_S  0
+
+/** INTMTX_CORE0_COEX_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x48)
+/** INTMTX_CORE0_COEX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_COEX_INTR mapping register
+ */
+#define INTMTX_CORE0_COEX_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_COEX_INTR_MAP_M  (INTMTX_CORE0_COEX_INTR_MAP_V << INTMTX_CORE0_COEX_INTR_MAP_S)
+#define INTMTX_CORE0_COEX_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_COEX_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x4c)
+/** INTMTX_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_BLE_TIMER_INTR mapping register
+ */
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_M  (INTMTX_CORE0_BLE_TIMER_INTR_MAP_V << INTMTX_CORE0_BLE_TIMER_INTR_MAP_S)
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BLE_TIMER_INTR_MAP_S  0
+
+/** INTMTX_CORE0_BLE_SEC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x50)
+/** INTMTX_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_BLE_SEC_INTR mapping register
+ */
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_M  (INTMTX_CORE0_BLE_SEC_INTR_MAP_V << INTMTX_CORE0_BLE_SEC_INTR_MAP_S)
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_BLE_SEC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_ZB_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x54)
+/** INTMTX_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_ZB_MAC_INTR mapping register
+ */
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_M  (INTMTX_CORE0_ZB_MAC_INTR_MAP_V << INTMTX_CORE0_ZB_MAC_INTR_MAP_S)
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ZB_MAC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x58)
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_GPIO_INTERRUPT_PRO mapping register
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
+
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x5c)
+/** INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_GPIO_INTERRUPT_PRO_NMI mapping register
+ */
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  (INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
+
+/** INTMTX_CORE0_PAU_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x60)
+/** INTMTX_CORE0_PAU_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_PAU_INTR mapping register
+ */
+#define INTMTX_CORE0_PAU_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PAU_INTR_MAP_M  (INTMTX_CORE0_PAU_INTR_MAP_V << INTMTX_CORE0_PAU_INTR_MAP_S)
+#define INTMTX_CORE0_PAU_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PAU_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x64)
+/** INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_HP_PERI_TIMEOUT_INTR mapping register
+ */
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M  (INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x68)
+/** INTMTX_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_HP_APM_M0_INTR mapping register
+ */
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M0_INTR_MAP_V << INTMTX_CORE0_HP_APM_M0_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x6c)
+/** INTMTX_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_HP_APM_M1_INTR mapping register
+ */
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M1_INTR_MAP_V << INTMTX_CORE0_HP_APM_M1_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x70)
+/** INTMTX_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_HP_APM_M2_INTR mapping register
+ */
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M2_INTR_MAP_V << INTMTX_CORE0_HP_APM_M2_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x74)
+/** INTMTX_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_HP_APM_M3_INTR mapping register
+ */
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_M  (INTMTX_CORE0_HP_APM_M3_INTR_MAP_V << INTMTX_CORE0_HP_APM_M3_INTR_MAP_S)
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_HP_APM_M3_INTR_MAP_S  0
+
+/** INTMTX_CORE0_MSPI_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x78)
+/** INTMTX_CORE0_MSPI_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_MSPI_INTR mapping register
+ */
+#define INTMTX_CORE0_MSPI_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_MSPI_INTR_MAP_M  (INTMTX_CORE0_MSPI_INTR_MAP_V << INTMTX_CORE0_MSPI_INTR_MAP_S)
+#define INTMTX_CORE0_MSPI_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_MSPI_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2S_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7c)
+/** INTMTX_CORE0_I2S_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_I2S_INTR mapping register
+ */
+#define INTMTX_CORE0_I2S_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2S_INTR_MAP_M  (INTMTX_CORE0_I2S_INTR_MAP_V << INTMTX_CORE0_I2S_INTR_MAP_S)
+#define INTMTX_CORE0_I2S_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2S_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UHCI0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x80)
+/** INTMTX_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_UHCI0_INTR mapping register
+ */
+#define INTMTX_CORE0_UHCI0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UHCI0_INTR_MAP_M  (INTMTX_CORE0_UHCI0_INTR_MAP_V << INTMTX_CORE0_UHCI0_INTR_MAP_S)
+#define INTMTX_CORE0_UHCI0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UHCI0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UART0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x84)
+/** INTMTX_CORE0_UART0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_UART0_INTR mapping register
+ */
+#define INTMTX_CORE0_UART0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UART0_INTR_MAP_M  (INTMTX_CORE0_UART0_INTR_MAP_V << INTMTX_CORE0_UART0_INTR_MAP_S)
+#define INTMTX_CORE0_UART0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UART0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_UART1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x88)
+/** INTMTX_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_UART1_INTR mapping register
+ */
+#define INTMTX_CORE0_UART1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_UART1_INTR_MAP_M  (INTMTX_CORE0_UART1_INTR_MAP_V << INTMTX_CORE0_UART1_INTR_MAP_S)
+#define INTMTX_CORE0_UART1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_UART1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_LEDC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x8c)
+/** INTMTX_CORE0_LEDC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_LEDC_INTR mapping register
+ */
+#define INTMTX_CORE0_LEDC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_LEDC_INTR_MAP_M  (INTMTX_CORE0_LEDC_INTR_MAP_V << INTMTX_CORE0_LEDC_INTR_MAP_S)
+#define INTMTX_CORE0_LEDC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_LEDC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_CAN0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x90)
+/** INTMTX_CORE0_CAN0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_CAN0_INTR mapping register
+ */
+#define INTMTX_CORE0_CAN0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_CAN0_INTR_MAP_M  (INTMTX_CORE0_CAN0_INTR_MAP_V << INTMTX_CORE0_CAN0_INTR_MAP_S)
+#define INTMTX_CORE0_CAN0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_CAN0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_USB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x94)
+/** INTMTX_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_USB_INTR mapping register
+ */
+#define INTMTX_CORE0_USB_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_USB_INTR_MAP_M  (INTMTX_CORE0_USB_INTR_MAP_V << INTMTX_CORE0_USB_INTR_MAP_S)
+#define INTMTX_CORE0_USB_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_USB_INTR_MAP_S  0
+
+/** INTMTX_CORE0_RMT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x98)
+/** INTMTX_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_RMT_INTR mapping register
+ */
+#define INTMTX_CORE0_RMT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_RMT_INTR_MAP_M  (INTMTX_CORE0_RMT_INTR_MAP_V << INTMTX_CORE0_RMT_INTR_MAP_S)
+#define INTMTX_CORE0_RMT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_RMT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x9c)
+/** INTMTX_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_I2C_EXT0_INTR mapping register
+ */
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_M  (INTMTX_CORE0_I2C_EXT0_INTR_MAP_V << INTMTX_CORE0_I2C_EXT0_INTR_MAP_S)
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2C_EXT0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa0)
+/** INTMTX_CORE0_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_I2C_EXT1_INTR mapping register
+ */
+#define INTMTX_CORE0_I2C_EXT1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_M  (INTMTX_CORE0_I2C_EXT1_INTR_MAP_V << INTMTX_CORE0_I2C_EXT1_INTR_MAP_S)
+#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_I2C_EXT1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG0_T0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa4)
+/** INTMTX_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_TG0_T0_INTR mapping register
+ */
+#define INTMTX_CORE0_TG0_T0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_M  (INTMTX_CORE0_TG0_T0_INTR_MAP_V << INTMTX_CORE0_TG0_T0_INTR_MAP_S)
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG0_T0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG0_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xa8)
+/** INTMTX_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_TG0_WDT_INTR mapping register
+ */
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_M  (INTMTX_CORE0_TG0_WDT_INTR_MAP_V << INTMTX_CORE0_TG0_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG0_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG1_T0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xac)
+/** INTMTX_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_TG1_T0_INTR mapping register
+ */
+#define INTMTX_CORE0_TG1_T0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_M  (INTMTX_CORE0_TG1_T0_INTR_MAP_V << INTMTX_CORE0_TG1_T0_INTR_MAP_S)
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG1_T0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_TG1_WDT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb0)
+/** INTMTX_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_TG1_WDT_INTR mapping register
+ */
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_M  (INTMTX_CORE0_TG1_WDT_INTR_MAP_V << INTMTX_CORE0_TG1_WDT_INTR_MAP_S)
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_TG1_WDT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb4)
+/** INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_SYSTIMER_TARGET0_INTR mapping register
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xb8)
+/** INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_SYSTIMER_TARGET1_INTR mapping register
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xbc)
+/** INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_SYSTIMER_TARGET2_INTR mapping register
+ */
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_APB_ADC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc0)
+/** INTMTX_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_APB_ADC_INTR mapping register
+ */
+#define INTMTX_CORE0_APB_ADC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_M  (INTMTX_CORE0_APB_ADC_INTR_MAP_V << INTMTX_CORE0_APB_ADC_INTR_MAP_S)
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_APB_ADC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PWM_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PWM_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc4)
+/** INTMTX_CORE0_PWM_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_PWM_INTR mapping register
+ */
+#define INTMTX_CORE0_PWM_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PWM_INTR_MAP_M  (INTMTX_CORE0_PWM_INTR_MAP_V << INTMTX_CORE0_PWM_INTR_MAP_S)
+#define INTMTX_CORE0_PWM_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PWM_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PCNT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xc8)
+/** INTMTX_CORE0_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_PCNT_INTR mapping register
+ */
+#define INTMTX_CORE0_PCNT_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PCNT_INTR_MAP_M  (INTMTX_CORE0_PCNT_INTR_MAP_V << INTMTX_CORE0_PCNT_INTR_MAP_S)
+#define INTMTX_CORE0_PCNT_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PCNT_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xcc)
+/** INTMTX_CORE0_PARL_IO_TX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_PARL_IO_TX_INTR mapping register
+ */
+#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_M  (INTMTX_CORE0_PARL_IO_TX_INTR_MAP_V << INTMTX_CORE0_PARL_IO_TX_INTR_MAP_S)
+#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PARL_IO_TX_INTR_MAP_S  0
+
+/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd0)
+/** INTMTX_CORE0_PARL_IO_RX_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_PARL_IO_RX_INTR mapping register
+ */
+#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_M  (INTMTX_CORE0_PARL_IO_RX_INTR_MAP_V << INTMTX_CORE0_PARL_IO_RX_INTR_MAP_S)
+#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_PARL_IO_RX_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd4)
+/** INTMTX_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_DMA_IN_CH0_INTR mapping register
+ */
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xd8)
+/** INTMTX_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_DMA_IN_CH1_INTR mapping register
+ */
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xdc)
+/** INTMTX_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_DMA_IN_CH2_INTR mapping register
+ */
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_IN_CH2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe0)
+/** INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_DMA_OUT_CH0_INTR mapping register
+ */
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH0_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe4)
+/** INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_DMA_OUT_CH1_INTR mapping register
+ */
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH1_INTR_MAP_S  0
+
+/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xe8)
+/** INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_DMA_OUT_CH2_INTR mapping register
+ */
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_M  (INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V << INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S)
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_DMA_OUT_CH2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_GPSPI2_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xec)
+/** INTMTX_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_GPSPI2_INTR mapping register
+ */
+#define INTMTX_CORE0_GPSPI2_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_M  (INTMTX_CORE0_GPSPI2_INTR_MAP_V << INTMTX_CORE0_GPSPI2_INTR_MAP_S)
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_GPSPI2_INTR_MAP_S  0
+
+/** INTMTX_CORE0_AES_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf0)
+/** INTMTX_CORE0_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_AES_INTR mapping register
+ */
+#define INTMTX_CORE0_AES_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_AES_INTR_MAP_M  (INTMTX_CORE0_AES_INTR_MAP_V << INTMTX_CORE0_AES_INTR_MAP_S)
+#define INTMTX_CORE0_AES_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_AES_INTR_MAP_S  0
+
+/** INTMTX_CORE0_SHA_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf4)
+/** INTMTX_CORE0_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_SHA_INTR mapping register
+ */
+#define INTMTX_CORE0_SHA_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_SHA_INTR_MAP_M  (INTMTX_CORE0_SHA_INTR_MAP_V << INTMTX_CORE0_SHA_INTR_MAP_S)
+#define INTMTX_CORE0_SHA_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_SHA_INTR_MAP_S  0
+
+/** INTMTX_CORE0_RSA_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xf8)
+/** INTMTX_CORE0_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_RSA_INTR mapping register
+ */
+#define INTMTX_CORE0_RSA_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_RSA_INTR_MAP_M  (INTMTX_CORE0_RSA_INTR_MAP_V << INTMTX_CORE0_RSA_INTR_MAP_S)
+#define INTMTX_CORE0_RSA_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_RSA_INTR_MAP_S  0
+
+/** INTMTX_CORE0_ECC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0xfc)
+/** INTMTX_CORE0_ECC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_ECC_INTR mapping register
+ */
+#define INTMTX_CORE0_ECC_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ECC_INTR_MAP_M  (INTMTX_CORE0_ECC_INTR_MAP_V << INTMTX_CORE0_ECC_INTR_MAP_S)
+#define INTMTX_CORE0_ECC_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ECC_INTR_MAP_S  0
+
+/** INTMTX_CORE0_ECDSA_INTR_MAP_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x100)
+/** INTMTX_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  CORE0_ECDSA_INTR mapping register
+ */
+#define INTMTX_CORE0_ECDSA_INTR_MAP    0x0000001FU
+#define INTMTX_CORE0_ECDSA_INTR_MAP_M  (INTMTX_CORE0_ECDSA_INTR_MAP_V << INTMTX_CORE0_ECDSA_INTR_MAP_S)
+#define INTMTX_CORE0_ECDSA_INTR_MAP_V  0x0000001FU
+#define INTMTX_CORE0_ECDSA_INTR_MAP_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_0_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x104)
+/** INTMTX_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Status register for interrupt sources 0~31 mapping register
+ */
+#define INTMTX_CORE0_INT_STATUS_0    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_0_M  (INTMTX_CORE0_INT_STATUS_0_V << INTMTX_CORE0_INT_STATUS_0_S)
+#define INTMTX_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_0_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_1_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x108)
+/** INTMTX_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Status register for interrupt sources 32~63 mapping register
+ */
+#define INTMTX_CORE0_INT_STATUS_1    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_1_M  (INTMTX_CORE0_INT_STATUS_1_V << INTMTX_CORE0_INT_STATUS_1_S)
+#define INTMTX_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_1_S  0
+
+/** INTMTX_CORE0_INT_STATUS_REG_2_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x10c)
+/** INTMTX_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Status register for interrupt sources 64~95 mapping register
+ */
+#define INTMTX_CORE0_INT_STATUS_2    0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_2_M  (INTMTX_CORE0_INT_STATUS_2_V << INTMTX_CORE0_INT_STATUS_2_S)
+#define INTMTX_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
+#define INTMTX_CORE0_INT_STATUS_2_S  0
+
+/** INTMTX_CORE0_CLOCK_GATE_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x110)
+/** INTMTX_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Clock register
+ */
+#define INTMTX_CORE0_REG_CLK_EN    (BIT(0))
+#define INTMTX_CORE0_REG_CLK_EN_M  (INTMTX_CORE0_REG_CLK_EN_V << INTMTX_CORE0_REG_CLK_EN_S)
+#define INTMTX_CORE0_REG_CLK_EN_V  0x00000001U
+#define INTMTX_CORE0_REG_CLK_EN_S  0
+
+/** INTMTX_CORE0_INTERRUPT_REG_DATE_REG register
+ *  register description
+ */
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_MATRIX_BASE + 0x7fc)
+/** INTMTX_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 35688784;
+ *  Version control register
+ */
+#define INTMTX_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_M  (INTMTX_CORE0_INTERRUPT_REG_DATE_V << INTMTX_CORE0_INTERRUPT_REG_DATE_S)
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
+#define INTMTX_CORE0_INTERRUPT_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/interrupt_matrix_struct.h b/components/soc/esp32h2/register/soc/interrupt_matrix_struct.h
new file mode 100644
index 00000000000..47e0526b64a
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/interrupt_matrix_struct.h
@@ -0,0 +1,1074 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of pmu_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pmu_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_PMU_INTR mapping register
+         */
+        uint32_t pmu_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_pmu_intr_map_reg_t;
+
+/** Type of efuse_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** efuse_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_EFUSE_INTR mapping register
+         */
+        uint32_t efuse_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_efuse_intr_map_reg_t;
+
+/** Type of lp_rtc_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_rtc_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_LP_RTC_TIMER_INTR mapping register
+         */
+        uint32_t lp_rtc_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_lp_rtc_timer_intr_map_reg_t;
+
+/** Type of lp_ble_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_LP_BLE_TIMER_INTR mapping register
+         */
+        uint32_t lp_ble_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_lp_ble_timer_intr_map_reg_t;
+
+/** Type of lp_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_LP_WDT_INTR mapping register
+         */
+        uint32_t lp_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_lp_wdt_intr_map_reg_t;
+
+/** Type of lp_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_LP_PERI_TIMEOUT_INTR mapping register
+         */
+        uint32_t lp_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_lp_peri_timeout_intr_map_reg_t;
+
+/** Type of lp_apm_m0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_LP_APM_M0_INTR mapping register
+         */
+        uint32_t lp_apm_m0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_lp_apm_m0_intr_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_0_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_CPU_INTR_FROM_CPU_0 mapping register
+         */
+        uint32_t cpu_intr_from_cpu_0_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_cpu_intr_from_cpu_0_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_1_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_CPU_INTR_FROM_CPU_1 mapping register
+         */
+        uint32_t cpu_intr_from_cpu_1_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_cpu_intr_from_cpu_1_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_2_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_CPU_INTR_FROM_CPU_2 mapping register
+         */
+        uint32_t cpu_intr_from_cpu_2_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_cpu_intr_from_cpu_2_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_3_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_CPU_INTR_FROM_CPU_3 mapping register
+         */
+        uint32_t cpu_intr_from_cpu_3_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_cpu_intr_from_cpu_3_map_reg_t;
+
+/** Type of assist_debug_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** assist_debug_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_ASSIST_DEBUG_INTR mapping register
+         */
+        uint32_t assist_debug_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_assist_debug_intr_map_reg_t;
+
+/** Type of trace_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** trace_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_TRACE_INTR mapping register
+         */
+        uint32_t trace_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_trace_intr_map_reg_t;
+
+/** Type of cache_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cache_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_CACHE_INTR mapping register
+         */
+        uint32_t cache_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_cache_intr_map_reg_t;
+
+/** Type of cpu_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_CPU_PERI_TIMEOUT_INTR mapping register
+         */
+        uint32_t cpu_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_cpu_peri_timeout_intr_map_reg_t;
+
+/** Type of bt_mac_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_BT_MAC_INTR mapping register
+         */
+        uint32_t bt_mac_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_bt_mac_intr_map_reg_t;
+
+/** Type of bt_bb_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_bb_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_BT_BB_INTR mapping register
+         */
+        uint32_t bt_bb_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_bt_bb_intr_map_reg_t;
+
+/** Type of bt_bb_nmi_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** bt_bb_nmi_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_BT_BB_NMI mapping register
+         */
+        uint32_t bt_bb_nmi_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_bt_bb_nmi_map_reg_t;
+
+/** Type of coex_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** coex_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_COEX_INTR mapping register
+         */
+        uint32_t coex_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_coex_intr_map_reg_t;
+
+/** Type of ble_timer_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ble_timer_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_BLE_TIMER_INTR mapping register
+         */
+        uint32_t ble_timer_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_ble_timer_intr_map_reg_t;
+
+/** Type of ble_sec_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ble_sec_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_BLE_SEC_INTR mapping register
+         */
+        uint32_t ble_sec_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_ble_sec_intr_map_reg_t;
+
+/** Type of zb_mac_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** zb_mac_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_ZB_MAC_INTR mapping register
+         */
+        uint32_t zb_mac_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_zb_mac_intr_map_reg_t;
+
+/** Type of gpio_interrupt_pro_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpio_interrupt_pro_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_GPIO_INTERRUPT_PRO mapping register
+         */
+        uint32_t gpio_interrupt_pro_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_gpio_interrupt_pro_map_reg_t;
+
+/** Type of gpio_interrupt_pro_nmi_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpio_interrupt_pro_nmi_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_GPIO_INTERRUPT_PRO_NMI mapping register
+         */
+        uint32_t gpio_interrupt_pro_nmi_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_gpio_interrupt_pro_nmi_map_reg_t;
+
+/** Type of pau_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pau_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_PAU_INTR mapping register
+         */
+        uint32_t pau_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_pau_intr_map_reg_t;
+
+/** Type of hp_peri_timeout_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_peri_timeout_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_HP_PERI_TIMEOUT_INTR mapping register
+         */
+        uint32_t hp_peri_timeout_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_hp_peri_timeout_intr_map_reg_t;
+
+/** Type of hp_apm_m0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_HP_APM_M0_INTR mapping register
+         */
+        uint32_t hp_apm_m0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_hp_apm_m0_intr_map_reg_t;
+
+/** Type of hp_apm_m1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_HP_APM_M1_INTR mapping register
+         */
+        uint32_t hp_apm_m1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_hp_apm_m1_intr_map_reg_t;
+
+/** Type of hp_apm_m2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_HP_APM_M2_INTR mapping register
+         */
+        uint32_t hp_apm_m2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_hp_apm_m2_intr_map_reg_t;
+
+/** Type of hp_apm_m3_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** hp_apm_m3_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_HP_APM_M3_INTR mapping register
+         */
+        uint32_t hp_apm_m3_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_hp_apm_m3_intr_map_reg_t;
+
+/** Type of mspi_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** mspi_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_MSPI_INTR mapping register
+         */
+        uint32_t mspi_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_mspi_intr_map_reg_t;
+
+/** Type of i2s_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2s_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_i2s_INTR mapping register
+         */
+        uint32_t i2s_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_i2s_intr_map_reg_t;
+
+/** Type of uhci0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uhci0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_UHCI0_INTR mapping register
+         */
+        uint32_t uhci0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_uhci0_intr_map_reg_t;
+
+/** Type of uart0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uart0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_UART0_INTR mapping register
+         */
+        uint32_t uart0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_uart0_intr_map_reg_t;
+
+/** Type of uart1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** uart1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_UART1_INTR mapping register
+         */
+        uint32_t uart1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_uart1_intr_map_reg_t;
+
+/** Type of ledc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ledc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_LEDC_INTR mapping register
+         */
+        uint32_t ledc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_ledc_intr_map_reg_t;
+
+/** Type of can0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** can0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_CAN0_INTR mapping register
+         */
+        uint32_t can0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_can0_intr_map_reg_t;
+
+/** Type of usb_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** usb_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_USB_INTR mapping register
+         */
+        uint32_t usb_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_usb_intr_map_reg_t;
+
+/** Type of rmt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rmt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_RMT_INTR mapping register
+         */
+        uint32_t rmt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_rmt_intr_map_reg_t;
+
+/** Type of i2c_ext0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2c_ext0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_I2C_EXT0_INTR mapping register
+         */
+        uint32_t i2c_ext0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_i2c_ext0_intr_map_reg_t;
+
+/** Type of i2c_ext1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** i2c_ext1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_I2C_EXT1_INTR mapping register
+         */
+        uint32_t i2c_ext1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_i2c_ext1_intr_map_reg_t;
+
+/** Type of tg0_t0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg0_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_TG0_T0_INTR mapping register
+         */
+        uint32_t tg0_t0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_tg0_t0_intr_map_reg_t;
+
+/** Type of tg0_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg0_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_TG0_WDT_INTR mapping register
+         */
+        uint32_t tg0_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_tg0_wdt_intr_map_reg_t;
+
+/** Type of tg1_t0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg1_t0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_TG1_T0_INTR mapping register
+         */
+        uint32_t tg1_t0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_tg1_t0_intr_map_reg_t;
+
+/** Type of tg1_wdt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** tg1_wdt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_TG1_WDT_INTR mapping register
+         */
+        uint32_t tg1_wdt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_tg1_wdt_intr_map_reg_t;
+
+/** Type of systimer_target0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_SYSTIMER_TARGET0_INTR mapping register
+         */
+        uint32_t systimer_target0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_systimer_target0_intr_map_reg_t;
+
+/** Type of systimer_target1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_SYSTIMER_TARGET1_INTR mapping register
+         */
+        uint32_t systimer_target1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_systimer_target1_intr_map_reg_t;
+
+/** Type of systimer_target2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** systimer_target2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_SYSTIMER_TARGET2_INTR mapping register
+         */
+        uint32_t systimer_target2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_systimer_target2_intr_map_reg_t;
+
+/** Type of apb_adc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** apb_adc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_APB_ADC_INTR mapping register
+         */
+        uint32_t apb_adc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_apb_adc_intr_map_reg_t;
+
+/** Type of pwm_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pwm_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_PWM_INTR mapping register
+         */
+        uint32_t pwm_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_pwm_intr_map_reg_t;
+
+/** Type of pcnt_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pcnt_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_PCNT_INTR mapping register
+         */
+        uint32_t pcnt_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_pcnt_intr_map_reg_t;
+
+/** Type of parl_io_tx_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** parl_io_tx_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_PARL_IO_TX_INTR mapping register
+         */
+        uint32_t parl_io_tx_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_parl_io_tx_intr_map_reg_t;
+
+/** Type of parl_io_rx_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** parl_io_rx_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_PARL_IO_RX_INTR mapping register
+         */
+        uint32_t parl_io_rx_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_parl_io_rx_intr_map_reg_t;
+
+/** Type of dma_in_ch0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_DMA_IN_CH0_INTR mapping register
+         */
+        uint32_t dma_in_ch0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_dma_in_ch0_intr_map_reg_t;
+
+/** Type of dma_in_ch1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_DMA_IN_CH1_INTR mapping register
+         */
+        uint32_t dma_in_ch1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_dma_in_ch1_intr_map_reg_t;
+
+/** Type of dma_in_ch2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_in_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_DMA_IN_CH2_INTR mapping register
+         */
+        uint32_t dma_in_ch2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_dma_in_ch2_intr_map_reg_t;
+
+/** Type of dma_out_ch0_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch0_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_DMA_OUT_CH0_INTR mapping register
+         */
+        uint32_t dma_out_ch0_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_dma_out_ch0_intr_map_reg_t;
+
+/** Type of dma_out_ch1_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch1_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_DMA_OUT_CH1_INTR mapping register
+         */
+        uint32_t dma_out_ch1_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_dma_out_ch1_intr_map_reg_t;
+
+/** Type of dma_out_ch2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_out_ch2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_DMA_OUT_CH2_INTR mapping register
+         */
+        uint32_t dma_out_ch2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_dma_out_ch2_intr_map_reg_t;
+
+/** Type of gpspi2_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** gpspi2_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_GPSPI2_INTR mapping register
+         */
+        uint32_t gpspi2_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_gpspi2_intr_map_reg_t;
+
+/** Type of aes_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** aes_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_AES_INTR mapping register
+         */
+        uint32_t aes_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_aes_intr_map_reg_t;
+
+/** Type of sha_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** sha_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_SHA_INTR mapping register
+         */
+        uint32_t sha_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_sha_intr_map_reg_t;
+
+/** Type of rsa_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rsa_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_RSA_INTR mapping register
+         */
+        uint32_t rsa_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_rsa_intr_map_reg_t;
+
+/** Type of ecc_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ecc_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_ECC_INTR mapping register
+         */
+        uint32_t ecc_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_ecc_intr_map_reg_t;
+
+/** Type of ecdsa_intr_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ecdsa_intr_map : R/W; bitpos: [4:0]; default: 0;
+         *  CORE0_ECDSA_INTR mapping register
+         */
+        uint32_t ecdsa_intr_map:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} intmtx_core0_ecdsa_intr_map_reg_t;
+
+/** Type of int_status_reg_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Status register for interrupt sources 0~31 mapping register
+         */
+        uint32_t int_status_0:32;
+    };
+    uint32_t val;
+} intmtx_core0_int_status_reg_0_reg_t;
+
+/** Type of int_status_reg_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Status register for interrupt sources 32~63 mapping register
+         */
+        uint32_t int_status_1:32;
+    };
+    uint32_t val;
+} intmtx_core0_int_status_reg_1_reg_t;
+
+/** Type of int_status_reg_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Status register for interrupt sources 64~95 mapping register
+         */
+        uint32_t int_status_2:32;
+    };
+    uint32_t val;
+} intmtx_core0_int_status_reg_2_reg_t;
+
+/** Type of clock_gate register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Clock register
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} intmtx_core0_clock_gate_reg_t;
+
+/** Type of interrupt_reg_date register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** interrupt_reg_date : R/W; bitpos: [27:0]; default: 35688784;
+         *  Version control register
+         */
+        uint32_t interrupt_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} intmtx_core0_interrupt_reg_date_reg_t;
+
+
+typedef struct interrupt_matrix_dev_t {
+    volatile intmtx_core0_pmu_intr_map_reg_t pmu_intr_map;
+    volatile intmtx_core0_efuse_intr_map_reg_t efuse_intr_map;
+    volatile intmtx_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
+    volatile intmtx_core0_lp_ble_timer_intr_map_reg_t lp_ble_timer_intr_map;
+    volatile intmtx_core0_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
+    volatile intmtx_core0_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
+    volatile intmtx_core0_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
+    volatile intmtx_core0_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
+    volatile intmtx_core0_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
+    volatile intmtx_core0_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
+    volatile intmtx_core0_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
+    volatile intmtx_core0_assist_debug_intr_map_reg_t assist_debug_intr_map;
+    volatile intmtx_core0_trace_intr_map_reg_t trace_intr_map;
+    volatile intmtx_core0_cache_intr_map_reg_t cache_intr_map;
+    volatile intmtx_core0_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map;
+    volatile intmtx_core0_bt_mac_intr_map_reg_t bt_mac_intr_map;
+    volatile intmtx_core0_bt_bb_intr_map_reg_t bt_bb_intr_map;
+    volatile intmtx_core0_bt_bb_nmi_map_reg_t bt_bb_nmi_map;
+    volatile intmtx_core0_coex_intr_map_reg_t coex_intr_map;
+    volatile intmtx_core0_ble_timer_intr_map_reg_t ble_timer_intr_map;
+    volatile intmtx_core0_ble_sec_intr_map_reg_t ble_sec_intr_map;
+    volatile intmtx_core0_zb_mac_intr_map_reg_t zb_mac_intr_map;
+    volatile intmtx_core0_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map;
+    volatile intmtx_core0_gpio_interrupt_pro_nmi_map_reg_t gpio_interrupt_pro_nmi_map;
+    volatile intmtx_core0_pau_intr_map_reg_t pau_intr_map;
+    volatile intmtx_core0_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map;
+    volatile intmtx_core0_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
+    volatile intmtx_core0_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
+    volatile intmtx_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
+    volatile intmtx_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
+    volatile intmtx_core0_mspi_intr_map_reg_t mspi_intr_map;
+    volatile intmtx_core0_i2s_intr_map_reg_t i2s_intr_map;
+    volatile intmtx_core0_uhci0_intr_map_reg_t uhci0_intr_map;
+    volatile intmtx_core0_uart0_intr_map_reg_t uart0_intr_map;
+    volatile intmtx_core0_uart1_intr_map_reg_t uart1_intr_map;
+    volatile intmtx_core0_ledc_intr_map_reg_t ledc_intr_map;
+    volatile intmtx_core0_can0_intr_map_reg_t can0_intr_map;
+    volatile intmtx_core0_usb_intr_map_reg_t usb_intr_map;
+    volatile intmtx_core0_rmt_intr_map_reg_t rmt_intr_map;
+    volatile intmtx_core0_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map;
+    volatile intmtx_core0_i2c_ext1_intr_map_reg_t i2c_ext1_intr_map;
+    volatile intmtx_core0_tg0_t0_intr_map_reg_t tg0_t0_intr_map;
+    volatile intmtx_core0_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map;
+    volatile intmtx_core0_tg1_t0_intr_map_reg_t tg1_t0_intr_map;
+    volatile intmtx_core0_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map;
+    volatile intmtx_core0_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
+    volatile intmtx_core0_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
+    volatile intmtx_core0_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
+    volatile intmtx_core0_apb_adc_intr_map_reg_t apb_adc_intr_map;
+    volatile intmtx_core0_pwm_intr_map_reg_t pwm_intr_map;
+    volatile intmtx_core0_pcnt_intr_map_reg_t pcnt_intr_map;
+    volatile intmtx_core0_parl_io_tx_intr_map_reg_t parl_io_tx_intr_map;
+    volatile intmtx_core0_parl_io_rx_intr_map_reg_t parl_io_rx_intr_map;
+    volatile intmtx_core0_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map;
+    volatile intmtx_core0_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map;
+    volatile intmtx_core0_dma_in_ch2_intr_map_reg_t dma_in_ch2_intr_map;
+    volatile intmtx_core0_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map;
+    volatile intmtx_core0_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map;
+    volatile intmtx_core0_dma_out_ch2_intr_map_reg_t dma_out_ch2_intr_map;
+    volatile intmtx_core0_gpspi2_intr_map_reg_t gpspi2_intr_map;
+    volatile intmtx_core0_aes_intr_map_reg_t aes_intr_map;
+    volatile intmtx_core0_sha_intr_map_reg_t sha_intr_map;
+    volatile intmtx_core0_rsa_intr_map_reg_t rsa_intr_map;
+    volatile intmtx_core0_ecc_intr_map_reg_t ecc_intr_map;
+    volatile intmtx_core0_ecdsa_intr_map_reg_t ecdsa_intr_map;
+    volatile intmtx_core0_int_status_reg_0_reg_t int_status_reg_0;
+    volatile intmtx_core0_int_status_reg_1_reg_t int_status_reg_1;
+    volatile intmtx_core0_int_status_reg_2_reg_t int_status_reg_2;
+    volatile intmtx_core0_clock_gate_reg_t clock_gate;
+    uint32_t reserved_114[442];
+    volatile intmtx_core0_interrupt_reg_date_reg_t interrupt_reg_date;
+} interrupt_matrix_dev_t;
+
+extern interrupt_matrix_dev_t INTMTX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/intpri_reg.h b/components/soc/esp32h2/register/soc/intpri_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/intpri_reg.h
rename to components/soc/esp32h2/register/soc/intpri_reg.h
diff --git a/components/soc/esp32h2/include/soc/intpri_struct.h b/components/soc/esp32h2/register/soc/intpri_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/intpri_struct.h
rename to components/soc/esp32h2/register/soc/intpri_struct.h
diff --git a/components/soc/esp32h2/register/soc/io_mux_reg.h b/components/soc/esp32h2/register/soc/io_mux_reg.h
new file mode 100644
index 00000000000..4bbb466906a
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/io_mux_reg.h
@@ -0,0 +1,370 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "soc/soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+/* HYS_EN : R/W; bitpos: [16]; default: 0;
+ * Software enables hysteresis function for the pad.
+ * 1: Hysteresis enabled. 0: Hysteresis disabled.
+ */
+#define HYS_EN    (BIT(16))
+#define HYS_EN_M  (HYS_EN_V << HYS_EN_S)
+#define HYS_EN_V  0x00000001
+#define HYS_EN_S  16
+/* HYS_SEL : R/W; bitpos: [17]; default: 0;
+ * Select enabling signals of the pad from software and efuse hardware.
+ * 1: Select enabling signal from software.
+ * 0: Select enabling signal from efuse hardware.
+ */
+#define HYS_SEL    (BIT(17))
+#define HYS_SEL_M  (HYS_SEL_V << HYS_SEL_S)
+#define HYS_SEL_V  0x00000001
+#define HYS_SEL_S  17
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+#define PIN_HYS_EN_SEL_EFUSE(PIN_NAME)      REG_CLR_BIT(PIN_NAME, HYS_SEL)
+#define PIN_HYS_EN_SEL_SOFT(PIN_NAME)       REG_SET_BIT(PIN_NAME, HYS_SEL)
+#define PIN_HYS_SOFT_ENABLE(PIN_NAME)       REG_SET_BIT(PIN_NAME, HYS_EN)
+#define PIN_HYS_SOFT_DISABLE(PIN_NAME)      REG_CLR_BIT(PIN_NAME, HYS_EN)
+
+#define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_GPIO0_U
+#define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_GPIO1_U
+#define IO_MUX_GPIO2_REG               PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO3_REG               PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO4_REG               PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO5_REG               PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO6_REG               PERIPHS_IO_MUX_GPIO6_U
+#define IO_MUX_GPIO7_REG               PERIPHS_IO_MUX_GPIO7_U
+#define IO_MUX_GPIO8_REG               PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG               PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG              PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG              PERIPHS_IO_MUX_GPIO11_U
+#define IO_MUX_GPIO12_REG              PERIPHS_IO_MUX_GPIO12_U
+#define IO_MUX_GPIO13_REG              PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO14_REG              PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO15_REG              PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO16_REG              PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO17_REG              PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO18_REG              PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO19_REG              PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO20_REG              PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO21_REG              PERIPHS_IO_MUX_VDD_SPI_U
+#define IO_MUX_GPIO22_REG              PERIPHS_IO_MUX_GPIO22_U
+#define IO_MUX_GPIO23_REG              PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO24_REG              PERIPHS_IO_MUX_U0TXD_U
+#define IO_MUX_GPIO25_REG              PERIPHS_IO_MUX_GPIO25_U
+#define IO_MUX_GPIO26_REG              PERIPHS_IO_MUX_GPIO26_U
+#define IO_MUX_GPIO27_REG              PERIPHS_IO_MUX_GPIO27_U
+
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define SPI_HD_GPIO_NUM              18
+#define SPI_WP_GPIO_NUM              17
+#define SPI_CS0_GPIO_NUM             15
+#define SPI_CLK_GPIO_NUM             19
+#define SPI_D_GPIO_NUM               20
+#define SPI_Q_GPIO_NUM               16
+
+#define USB_INT_PHY0_DM_GPIO_NUM              26
+#define USB_INT_PHY0_DP_GPIO_NUM              27
+
+#define EXT_OSC_SLOW_GPIO_NUM        13
+
+#define MAX_RTC_GPIO_NUM             14            // GPIO7~14 are the pads with LP function
+#define MAX_PAD_GPIO_NUM             27
+#define MAX_GPIO_NUM                 31
+#define HIGH_IO_HOLD_BIT_SHIFT       32
+
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
+
+#define CLK_OUT3                                    IO_MUX_CLK_OUT3
+#define CLK_OUT3_V                                  IO_MUX_CLK_OUT3_V
+#define CLK_OUT3_S                                  IO_MUX_CLK_OUT3_S
+#define CLK_OUT3_M                                  IO_MUX_CLK_OUT3_M
+#define CLK_OUT2                                    IO_MUX_CLK_OUT2
+#define CLK_OUT2_V                                  IO_MUX_CLK_OUT2_V
+#define CLK_OUT2_S                                  IO_MUX_CLK_OUT2_S
+#define CLK_OUT2_M                                  IO_MUX_CLK_OUT2_M
+#define CLK_OUT1                                    IO_MUX_CLK_OUT1
+#define CLK_OUT1_V                                  IO_MUX_CLK_OUT1_V
+#define CLK_OUT1_S                                  IO_MUX_CLK_OUT1_S
+#define CLK_OUT1_M                                  IO_MUX_CLK_OUT1_M
+// definitions above are inherited from previous version of code, should double check
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_GPIO0_U                (REG_IO_MUX_BASE + 0x4)
+#define FUNC_GPIO0_FSPIQ                                            2
+#define FUNC_GPIO0_GPIO0                                            1
+#define FUNC_GPIO0_GPIO0_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO1_U                (REG_IO_MUX_BASE + 0x8)
+#define FUNC_GPIO1_FSPICS0                                          2
+#define FUNC_GPIO1_GPIO1                                            1
+#define FUNC_GPIO1_GPIO1_0                                          0
+
+#define PERIPHS_IO_MUX_MTMS_U                 (REG_IO_MUX_BASE + 0xC)
+#define FUNC_MTMS_FSPIWP                                            2
+#define FUNC_MTMS_GPIO2                                             1
+#define FUNC_MTMS_MTMS                                              0
+
+#define PERIPHS_IO_MUX_MTDO_U                (REG_IO_MUX_BASE + 0x10)
+#define FUNC_MTDO_FSPIHD                                            2
+#define FUNC_MTDO_GPIO3                                             1
+#define FUNC_MTDO_MTDO                                              0
+
+#define PERIPHS_IO_MUX_MTCK_U                (REG_IO_MUX_BASE + 0x14)
+#define FUNC_MTCK_FSPICLK                                           2
+#define FUNC_MTCK_GPIO4                                             1
+#define FUNC_MTCK_MTCK                                              0
+
+#define PERIPHS_IO_MUX_MTDI_U                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_MTDI_FSPID                                             2
+#define FUNC_MTDI_GPIO5                                             1
+#define FUNC_MTDI_MTDI                                              0
+
+#define PERIPHS_IO_MUX_GPIO6_U               (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_GPIO6_GPIO6                                            1
+#define FUNC_GPIO6_GPIO6_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO7_U               (REG_IO_MUX_BASE + 0x20)
+#define FUNC_GPIO7_GPIO7                                            1
+#define FUNC_GPIO7_GPIO7_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO8_U               (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_GPIO8                                            1
+#define FUNC_GPIO8_GPIO8_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO9_U               (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_GPIO9                                            1
+#define FUNC_GPIO9_GPIO9_0                                          0
+
+#define PERIPHS_IO_MUX_GPIO10_U              (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_GPIO10_GPIO10                                          1
+#define FUNC_GPIO10_GPIO10_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO11_U              (REG_IO_MUX_BASE + 0x30)
+#define FUNC_GPIO11_GPIO11                                          1
+#define FUNC_GPIO11_GPIO11_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO12_U              (REG_IO_MUX_BASE + 0x34)
+#define FUNC_GPIO12_GPIO12                                          1
+#define FUNC_GPIO12_GPIO12_0                                        0
+
+#define PERIPHS_IO_MUX_XTAL_32K_P_U          (REG_IO_MUX_BASE + 0x38)
+#define FUNC_XTAL_32K_P_GPIO13                                      1
+#define FUNC_XTAL_32K_P_GPIO13_0                                    0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U          (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_XTAL_32K_N_GPIO14                                      1
+#define FUNC_XTAL_32K_N_GPIO14_0                                    0
+
+#define PERIPHS_IO_MUX_SPICS0_U              (REG_IO_MUX_BASE + 0x40)
+#define FUNC_SPICS0_GPIO15                                          1
+#define FUNC_SPICS0_SPICS0                                          0
+
+#define PERIPHS_IO_MUX_SPIQ_U                (REG_IO_MUX_BASE + 0x44)
+#define FUNC_SPIQ_GPIO16                                            1
+#define FUNC_SPIQ_SPIQ                                              0
+
+#define PERIPHS_IO_MUX_SPIWP_U               (REG_IO_MUX_BASE + 0x48)
+#define FUNC_SPIWP_GPIO17                                           1
+#define FUNC_SPIWP_SPIWP                                            0
+
+#define PERIPHS_IO_MUX_SPIHD_U               (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_SPIHD_GPIO18                                           1
+#define FUNC_SPIHD_SPIHD                                            0
+
+#define PERIPHS_IO_MUX_SPICLK_U              (REG_IO_MUX_BASE + 0x50)
+#define FUNC_SPICLK_GPIO19                                          1
+#define FUNC_SPICLK_SPICLK                                          0
+
+#define PERIPHS_IO_MUX_SPID_U                (REG_IO_MUX_BASE + 0x54)
+#define FUNC_SPID_GPIO20                                            1
+#define FUNC_SPID_SPID                                              0
+
+#define PERIPHS_IO_MUX_VDD_SPI_U             (REG_IO_MUX_BASE + 0x58)
+#define FUNC_VDD_SPI_GPIO21                                         1
+#define FUNC_VDD_SPI_GPIO21_0                                       0
+
+#define PERIPHS_IO_MUX_GPIO22_U              (REG_IO_MUX_BASE + 0x5C)
+#define FUNC_GPIO22_GPIO22                                          1
+#define FUNC_GPIO22_GPIO22_0                                        0
+
+#define PERIPHS_IO_MUX_U0RXD_U               (REG_IO_MUX_BASE + 0x60)
+#define FUNC_U0RXD_FSPICS1                                          2
+#define FUNC_U0RXD_GPIO23                                           1
+#define FUNC_U0RXD_U0RXD                                            0
+
+#define PERIPHS_IO_MUX_U0TXD_U               (REG_IO_MUX_BASE + 0x64)
+#define FUNC_U0TXD_FSPICS2                                          2
+#define FUNC_U0TXD_GPIO24                                           1
+#define FUNC_U0TXD_U0TXD                                            0
+
+#define PERIPHS_IO_MUX_GPIO25_U              (REG_IO_MUX_BASE + 0x68)
+#define FUNC_GPIO25_FSPICS3                                         2
+#define FUNC_GPIO25_GPIO25                                          1
+#define FUNC_GPIO25_GPIO25_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO26_U              (REG_IO_MUX_BASE + 0x6C)
+#define FUNC_GPIO26_FSPICS4                                         2
+#define FUNC_GPIO26_GPIO26                                          1
+#define FUNC_GPIO26_GPIO26_0                                        0
+
+#define PERIPHS_IO_MUX_GPIO27_U              (REG_IO_MUX_BASE + 0x70)
+#define FUNC_GPIO27_FSPICS5                                         2
+#define FUNC_GPIO27_GPIO27                                          1
+#define FUNC_GPIO27_GPIO27_0                                        0
+
+/** IO_MUX_PIN_CTRL_REG register
+ *  Clock Output Configuration
+ *  Register
+ */
+#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
+/* IO_MUX_CLK_OUT1 : R/W; bitpos: [5:0]; default: 15;
+ * If you want to output clock for I2S to CLK_OUT_out1, set this register
+ * to 0x0. CLK_OUT_out1 can be found in peripheral output
+ * signals.
+ */
+#define IO_MUX_CLK_OUT1    0x0000001F
+#define IO_MUX_CLK_OUT1_M  (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
+#define IO_MUX_CLK_OUT1_V  0x0000001F
+#define IO_MUX_CLK_OUT1_S  0
+/* IO_MUX_CLK_OUT2 : R/W; bitpos: [10:5]; default: 15;
+ * If you want to output clock for I2S to CLK_OUT_out2, set this register
+ * to 0x0. CLK_OUT_out2 can be found in peripheral output
+ * signals.
+ */
+#define IO_MUX_CLK_OUT2    0x0000001F
+#define IO_MUX_CLK_OUT2_M  (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
+#define IO_MUX_CLK_OUT2_V  0x0000001F
+#define IO_MUX_CLK_OUT2_S  5
+/* IO_MUX_CLK_OUT3 : R/W; bitpos: [15:10]; default: 7;
+ * If you want to output clock for I2S to CLK_OUT_out3, set this register
+ * to 0x0. CLK_OUT_out3 can be found in peripheral output
+ * signals.
+ */
+#define IO_MUX_CLK_OUT3    0x0000001F
+#define IO_MUX_CLK_OUT3_M  (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
+#define IO_MUX_CLK_OUT3_V  0x0000001F
+#define IO_MUX_CLK_OUT3_S  10
+
+/** IO_MUX_MODEM_DIAG_EN_REG register
+ *  GPIO MATRIX Configure Register for modem
+ *  diag
+ */
+#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
+/* IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [32:0]; default: 0;
+ * bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i]
+ * into gpio matrix. 0:enable other signals into gpio
+ * matrix
+ */
+#define IO_MUX_MODEM_DIAG_EN    0xFFFFFFFF
+#define IO_MUX_MODEM_DIAG_EN_M  (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
+#define IO_MUX_MODEM_DIAG_EN_V  0xFFFFFFFF
+#define IO_MUX_MODEM_DIAG_EN_S  0
+
+/** IO_MUX_DATE_REG register
+ *  IO MUX Version Control
+ *  Register
+ */
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+/* IO_MUX_REG_DATE : R/W; bitpos: [28:0]; default: 35680880;
+ * Version control
+ * register
+ */
+#define IO_MUX_REG_DATE    0x0FFFFFFF
+#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
+#define IO_MUX_REG_DATE_V  0x0FFFFFFF
+#define IO_MUX_REG_DATE_S  0
diff --git a/components/soc/esp32h2/include/soc/ledc_reg.h b/components/soc/esp32h2/register/soc/ledc_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/ledc_reg.h
rename to components/soc/esp32h2/register/soc/ledc_reg.h
diff --git a/components/soc/esp32h2/include/soc/ledc_struct.h b/components/soc/esp32h2/register/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/ledc_struct.h
rename to components/soc/esp32h2/register/soc/ledc_struct.h
diff --git a/components/soc/esp32h2/include/soc/lp_analog_peri_reg.h b/components/soc/esp32h2/register/soc/lp_analog_peri_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_analog_peri_reg.h
rename to components/soc/esp32h2/register/soc/lp_analog_peri_reg.h
diff --git a/components/soc/esp32h2/include/soc/lp_analog_peri_struct.h b/components/soc/esp32h2/register/soc/lp_analog_peri_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_analog_peri_struct.h
rename to components/soc/esp32h2/register/soc/lp_analog_peri_struct.h
diff --git a/components/soc/esp32h2/include/soc/lp_aon_reg.h b/components/soc/esp32h2/register/soc/lp_aon_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_aon_reg.h
rename to components/soc/esp32h2/register/soc/lp_aon_reg.h
diff --git a/components/soc/esp32h2/include/soc/lp_aon_struct.h b/components/soc/esp32h2/register/soc/lp_aon_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_aon_struct.h
rename to components/soc/esp32h2/register/soc/lp_aon_struct.h
diff --git a/components/soc/esp32h2/include/soc/lp_apm0_reg.h b/components/soc/esp32h2/register/soc/lp_apm0_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_apm0_reg.h
rename to components/soc/esp32h2/register/soc/lp_apm0_reg.h
diff --git a/components/soc/esp32h2/include/soc/lp_apm0_struct.h b/components/soc/esp32h2/register/soc/lp_apm0_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_apm0_struct.h
rename to components/soc/esp32h2/register/soc/lp_apm0_struct.h
diff --git a/components/soc/esp32h2/include/soc/lp_apm_reg.h b/components/soc/esp32h2/register/soc/lp_apm_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_apm_reg.h
rename to components/soc/esp32h2/register/soc/lp_apm_reg.h
diff --git a/components/soc/esp32h2/include/soc/lp_apm_struct.h b/components/soc/esp32h2/register/soc/lp_apm_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_apm_struct.h
rename to components/soc/esp32h2/register/soc/lp_apm_struct.h
diff --git a/components/soc/esp32h2/include/soc/lp_clkrst_reg.h b/components/soc/esp32h2/register/soc/lp_clkrst_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_clkrst_reg.h
rename to components/soc/esp32h2/register/soc/lp_clkrst_reg.h
diff --git a/components/soc/esp32h2/include/soc/lp_clkrst_struct.h b/components/soc/esp32h2/register/soc/lp_clkrst_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_clkrst_struct.h
rename to components/soc/esp32h2/register/soc/lp_clkrst_struct.h
diff --git a/components/soc/esp32h2/include/soc/lp_timer_reg.h b/components/soc/esp32h2/register/soc/lp_timer_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_timer_reg.h
rename to components/soc/esp32h2/register/soc/lp_timer_reg.h
diff --git a/components/soc/esp32h2/include/soc/lp_timer_struct.h b/components/soc/esp32h2/register/soc/lp_timer_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_timer_struct.h
rename to components/soc/esp32h2/register/soc/lp_timer_struct.h
diff --git a/components/soc/esp32h2/include/soc/lp_wdt_reg.h b/components/soc/esp32h2/register/soc/lp_wdt_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_wdt_reg.h
rename to components/soc/esp32h2/register/soc/lp_wdt_reg.h
diff --git a/components/soc/esp32h2/include/soc/lp_wdt_struct.h b/components/soc/esp32h2/register/soc/lp_wdt_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lp_wdt_struct.h
rename to components/soc/esp32h2/register/soc/lp_wdt_struct.h
diff --git a/components/soc/esp32h2/include/soc/lpperi_reg.h b/components/soc/esp32h2/register/soc/lpperi_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lpperi_reg.h
rename to components/soc/esp32h2/register/soc/lpperi_reg.h
diff --git a/components/soc/esp32h2/include/soc/lpperi_struct.h b/components/soc/esp32h2/register/soc/lpperi_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/lpperi_struct.h
rename to components/soc/esp32h2/register/soc/lpperi_struct.h
diff --git a/components/soc/esp32h2/register/soc/mcpwm_reg.h b/components/soc/esp32h2/register/soc/mcpwm_reg.h
new file mode 100644
index 00000000000..a14ba71be36
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/mcpwm_reg.h
@@ -0,0 +1,4137 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MCPWM_CLK_CFG_REG register
+ *  PWM clock prescaler register.
+ */
+#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0)
+/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
+ */
+#define MCPWM_CLK_PRESCALE    0x000000FFU
+#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
+#define MCPWM_CLK_PRESCALE_V  0x000000FFU
+#define MCPWM_CLK_PRESCALE_S  0
+
+/** MCPWM_TIMER0_CFG0_REG register
+ *  PWM timer0 period and update method configuration register.
+ */
+#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer0
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER0_CFG1_REG register
+ *  PWM timer0 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8)
+/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1:
+ *  if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0
+ *  starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER0_START    0x00000007U
+#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
+#define MCPWM_TIMER0_START_V  0x00000007U
+#define MCPWM_TIMER0_START_S  0
+/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER0_MOD    0x00000003U
+#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
+#define MCPWM_TIMER0_MOD_V  0x00000003U
+#define MCPWM_TIMER0_MOD_S  3
+
+/** MCPWM_TIMER0_SYNC_REG register
+ *  PWM timer0 sync function configuration register.
+ */
+#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc)
+/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
+#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
+#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer0_sync_sw bit
+ */
+#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER0_PHASE    0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
+#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_S  4
+/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer0's direction when timer0 mode is up-down mode:
+ *  0-increase,1-decrease
+ */
+#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
+#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER0_STATUS_REG register
+ *  PWM timer0 status register.
+ */
+#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10)
+/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer0 counter value
+ */
+#define MCPWM_TIMER0_VALUE    0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
+#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_S  0
+/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer0 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER0_DIRECTION    (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
+#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_DIRECTION_S  16
+
+/** MCPWM_TIMER1_CFG0_REG register
+ *  PWM timer1 period and update method configuration register.
+ */
+#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14)
+/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1)
+ */
+#define MCPWM_TIMER1_PRESCALE    0x000000FFU
+#define MCPWM_TIMER1_PRESCALE_M  (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S)
+#define MCPWM_TIMER1_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER1_PRESCALE_S  0
+/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer1
+ */
+#define MCPWM_TIMER1_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER1_PERIOD_M  (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S)
+#define MCPWM_TIMER1_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER1_PERIOD_S  8
+/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER1_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER1_CFG1_REG register
+ *  PWM timer1 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18)
+/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1:
+ *  if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1
+ *  starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER1_START    0x00000007U
+#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
+#define MCPWM_TIMER1_START_V  0x00000007U
+#define MCPWM_TIMER1_START_S  0
+/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER1_MOD    0x00000003U
+#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
+#define MCPWM_TIMER1_MOD_V  0x00000003U
+#define MCPWM_TIMER1_MOD_S  3
+
+/** MCPWM_TIMER1_SYNC_REG register
+ *  PWM timer1 sync function configuration register.
+ */
+#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c)
+/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
+#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
+#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer1_sync_sw bit
+ */
+#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER1_PHASE    0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
+#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_S  4
+/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer1's direction when timer1 mode is up-down mode:
+ *  0-increase,1-decrease
+ */
+#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
+#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER1_STATUS_REG register
+ *  PWM timer1 status register.
+ */
+#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20)
+/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer1 counter value
+ */
+#define MCPWM_TIMER1_VALUE    0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
+#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_S  0
+/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer1 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER1_DIRECTION    (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
+#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_DIRECTION_S  16
+
+/** MCPWM_TIMER2_CFG0_REG register
+ *  PWM timer2 period and update method configuration register.
+ */
+#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24)
+/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1)
+ */
+#define MCPWM_TIMER2_PRESCALE    0x000000FFU
+#define MCPWM_TIMER2_PRESCALE_M  (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S)
+#define MCPWM_TIMER2_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER2_PRESCALE_S  0
+/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer2
+ */
+#define MCPWM_TIMER2_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER2_PERIOD_M  (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S)
+#define MCPWM_TIMER2_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER2_PERIOD_S  8
+/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER2_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER2_CFG1_REG register
+ *  PWM timer2 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28)
+/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1:
+ *  if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2
+ *  starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER2_START    0x00000007U
+#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
+#define MCPWM_TIMER2_START_V  0x00000007U
+#define MCPWM_TIMER2_START_S  0
+/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER2_MOD    0x00000003U
+#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
+#define MCPWM_TIMER2_MOD_V  0x00000003U
+#define MCPWM_TIMER2_MOD_S  3
+
+/** MCPWM_TIMER2_SYNC_REG register
+ *  PWM timer2 sync function configuration register.
+ */
+#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c)
+/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
+#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
+#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer0_sync_sw bit
+ */
+#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER2_PHASE    0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
+#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_S  4
+/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer2's direction when timer2 mode is up-down mode:
+ *  0-increase,1-decrease
+ */
+#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
+#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER2_STATUS_REG register
+ *  PWM timer2 status register.
+ */
+#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30)
+/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer2 counter value
+ */
+#define MCPWM_TIMER2_VALUE    0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
+#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_S  0
+/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer2 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER2_DIRECTION    (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
+#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_DIRECTION_S  16
+
+/** MCPWM_TIMER_SYNCI_CFG_REG register
+ *  Synchronization input selection for three PWM timers.
+ */
+#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34)
+/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
+ *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER0_SYNCISEL    0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
+#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_S  0
+/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
+ *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER1_SYNCISEL    0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
+#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
+ *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER2_SYNCISEL    0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
+#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
+ *  invert SYNC0 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
+ *  invert SYNC1 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
+ *  invert SYNC2 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+
+/** MCPWM_OPERATOR_TIMERSEL_REG register
+ *  Select specific timer for PWM operators.
+ */
+#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38)
+/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
+ *  Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
+ *  Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
+ *  Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+
+/** MCPWM_GEN0_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 0 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 0 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN0_TSTMP_A_REG register
+ *  Shadow register for register A.
+ */
+#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40)
+/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 0 time stamp A's shadow register
+ */
+#define MCPWM_CMPR0_A    0x0000FFFFU
+#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
+#define MCPWM_CMPR0_A_V  0x0000FFFFU
+#define MCPWM_CMPR0_A_S  0
+
+/** MCPWM_GEN0_TSTMP_B_REG register
+ *  Shadow register for register B.
+ */
+#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44)
+/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 0 time stamp B's shadow register
+ */
+#define MCPWM_CMPR0_B    0x0000FFFFU
+#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
+#define MCPWM_CMPR0_B_V  0x0000FFFFU
+#define MCPWM_CMPR0_B_S  0
+
+/** MCPWM_GEN0_CFG0_REG register
+ *  Fault event T0 and T1 handling
+ */
+#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48)
+/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 0's active register of configuration. When all bits
+ *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+ *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
+ */
+#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 0 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN0_T0_SEL    0x00000007U
+#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
+#define MCPWM_GEN0_T0_SEL_V  0x00000007U
+#define MCPWM_GEN0_T0_SEL_S  4
+/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 0 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN0_T1_SEL    0x00000007U
+#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
+#define MCPWM_GEN0_T1_SEL_V  0x00000007U
+#define MCPWM_GEN0_T1_SEL_S  7
+
+/** MCPWM_GEN0_FORCE_REG register
+ *  Permissives to force PWM0A and PWM0B outputs by software
+ */
+#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c)
+/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator0. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM0A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
+#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM0B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
+#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN0_A_REG register
+ *  Actions triggered by events on PWM0A
+ */
+#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50)
+/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM0A triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN0_A_UTEZ    0x00000003U
+#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
+#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_UTEZ_S  0
+/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM0A triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN0_A_UTEP    0x00000003U
+#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
+#define MCPWM_GEN0_A_UTEP_V  0x00000003U
+#define MCPWM_GEN0_A_UTEP_S  2
+/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM0A triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN0_A_UTEA    0x00000003U
+#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
+#define MCPWM_GEN0_A_UTEA_V  0x00000003U
+#define MCPWM_GEN0_A_UTEA_S  4
+/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM0A triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN0_A_UTEB    0x00000003U
+#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
+#define MCPWM_GEN0_A_UTEB_V  0x00000003U
+#define MCPWM_GEN0_A_UTEB_S  6
+/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM0A triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN0_A_UT0    0x00000003U
+#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
+#define MCPWM_GEN0_A_UT0_V  0x00000003U
+#define MCPWM_GEN0_A_UT0_S  8
+/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM0A triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN0_A_UT1    0x00000003U
+#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
+#define MCPWM_GEN0_A_UT1_V  0x00000003U
+#define MCPWM_GEN0_A_UT1_S  10
+/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM0A triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN0_A_DTEZ    0x00000003U
+#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
+#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_DTEZ_S  12
+/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM0A triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN0_A_DTEP    0x00000003U
+#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
+#define MCPWM_GEN0_A_DTEP_V  0x00000003U
+#define MCPWM_GEN0_A_DTEP_S  14
+/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM0A triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN0_A_DTEA    0x00000003U
+#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
+#define MCPWM_GEN0_A_DTEA_V  0x00000003U
+#define MCPWM_GEN0_A_DTEA_S  16
+/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM0A triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN0_A_DTEB    0x00000003U
+#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
+#define MCPWM_GEN0_A_DTEB_V  0x00000003U
+#define MCPWM_GEN0_A_DTEB_S  18
+/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM0A triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN0_A_DT0    0x00000003U
+#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
+#define MCPWM_GEN0_A_DT0_V  0x00000003U
+#define MCPWM_GEN0_A_DT0_S  20
+/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_DT1    0x00000003U
+#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
+#define MCPWM_GEN0_A_DT1_V  0x00000003U
+#define MCPWM_GEN0_A_DT1_S  22
+
+/** MCPWM_GEN0_B_REG register
+ *  Actions triggered by events on PWM0B
+ */
+#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54)
+/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM0B triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN0_B_UTEZ    0x00000003U
+#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
+#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_UTEZ_S  0
+/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM0B triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN0_B_UTEP    0x00000003U
+#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
+#define MCPWM_GEN0_B_UTEP_V  0x00000003U
+#define MCPWM_GEN0_B_UTEP_S  2
+/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM0B triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN0_B_UTEA    0x00000003U
+#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
+#define MCPWM_GEN0_B_UTEA_V  0x00000003U
+#define MCPWM_GEN0_B_UTEA_S  4
+/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM0B triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN0_B_UTEB    0x00000003U
+#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
+#define MCPWM_GEN0_B_UTEB_V  0x00000003U
+#define MCPWM_GEN0_B_UTEB_S  6
+/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM0B triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN0_B_UT0    0x00000003U
+#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
+#define MCPWM_GEN0_B_UT0_V  0x00000003U
+#define MCPWM_GEN0_B_UT0_S  8
+/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM0B triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN0_B_UT1    0x00000003U
+#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
+#define MCPWM_GEN0_B_UT1_V  0x00000003U
+#define MCPWM_GEN0_B_UT1_S  10
+/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM0B triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN0_B_DTEZ    0x00000003U
+#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
+#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_DTEZ_S  12
+/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM0B triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN0_B_DTEP    0x00000003U
+#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
+#define MCPWM_GEN0_B_DTEP_V  0x00000003U
+#define MCPWM_GEN0_B_DTEP_S  14
+/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM0B triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN0_B_DTEA    0x00000003U
+#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
+#define MCPWM_GEN0_B_DTEA_V  0x00000003U
+#define MCPWM_GEN0_B_DTEA_S  16
+/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM0B triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN0_B_DTEB    0x00000003U
+#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
+#define MCPWM_GEN0_B_DTEB_V  0x00000003U
+#define MCPWM_GEN0_B_DTEB_S  18
+/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM0B triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN0_B_DT0    0x00000003U
+#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
+#define MCPWM_GEN0_B_DT0_V  0x00000003U
+#define MCPWM_GEN0_B_DT0_S  20
+/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_DT1    0x00000003U
+#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
+#define MCPWM_GEN0_B_DT1_V  0x00000003U
+#define MCPWM_GEN0_B_DT1_S  22
+
+/** MCPWM_DT0_CFG_REG register
+ *  dead time type selection and configuration
+ */
+#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58)
+/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
+#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_S  0
+/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
+#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_S  4
+/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB0_DEB_MODE    (BIT(8))
+#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
+#define MCPWM_DB0_DEB_MODE_V  0x00000001U
+#define MCPWM_DB0_DEB_MODE_S  8
+/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
+#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_A_OUTSWAP_S  9
+/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
+#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_B_OUTSWAP_S  10
+/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DB0_RED_INSEL    (BIT(11))
+#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
+#define MCPWM_DB0_RED_INSEL_V  0x00000001U
+#define MCPWM_DB0_RED_INSEL_S  11
+/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DB0_FED_INSEL    (BIT(12))
+#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
+#define MCPWM_DB0_FED_INSEL_V  0x00000001U
+#define MCPWM_DB0_FED_INSEL_S  12
+/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
+#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_RED_OUTINVERT_S  13
+/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
+#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_FED_OUTINVERT_S  14
+/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
+#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_A_OUTBYPASS_S  15
+/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
+#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_B_OUTBYPASS_S  16
+/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DB0_CLK_SEL    (BIT(17))
+#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
+#define MCPWM_DB0_CLK_SEL_V  0x00000001U
+#define MCPWM_DB0_CLK_SEL_S  17
+
+/** MCPWM_DT0_FED_CFG_REG register
+ *  Shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c)
+/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DB0_FED    0x0000FFFFU
+#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
+#define MCPWM_DB0_FED_V  0x0000FFFFU
+#define MCPWM_DB0_FED_S  0
+
+/** MCPWM_DT0_RED_CFG_REG register
+ *  Shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60)
+/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DB0_RED    0x0000FFFFU
+#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
+#define MCPWM_DB0_RED_V  0x0000FFFFU
+#define MCPWM_DB0_RED_S  0
+
+/** MCPWM_CARRIER0_CFG_REG register
+ *  Carrier enable and configuration
+ */
+#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64)
+/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
+ */
+#define MCPWM_CHOPPER0_EN    (BIT(0))
+#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
+#define MCPWM_CHOPPER0_EN_V  0x00000001U
+#define MCPWM_CHOPPER0_EN_S  0
+/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
+#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_S  1
+/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CHOPPER0_DUTY    0x00000007U
+#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
+#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER0_DUTY_S  5
+/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
+#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_S  8
+/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM0A and PWM0B for this submodule
+ */
+#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
+#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_OUT_INVERT_S  12
+/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM0A and PWM0B for this submodule
+ */
+#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
+#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_IN_INVERT_S  13
+
+/** MCPWM_FH0_CFG0_REG register
+ *  Actions on PWM0A and PWM0B trip events
+ */
+#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68)
+/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_SW_CBC    (BIT(0))
+#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
+#define MCPWM_TZ0_SW_CBC_V  0x00000001U
+#define MCPWM_TZ0_SW_CBC_S  0
+/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F2_CBC    (BIT(1))
+#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
+#define MCPWM_TZ0_F2_CBC_V  0x00000001U
+#define MCPWM_TZ0_F2_CBC_S  1
+/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F1_CBC    (BIT(2))
+#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
+#define MCPWM_TZ0_F1_CBC_V  0x00000001U
+#define MCPWM_TZ0_F1_CBC_S  2
+/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F0_CBC    (BIT(3))
+#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
+#define MCPWM_TZ0_F0_CBC_V  0x00000001U
+#define MCPWM_TZ0_F0_CBC_S  3
+/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_SW_OST    (BIT(4))
+#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
+#define MCPWM_TZ0_SW_OST_V  0x00000001U
+#define MCPWM_TZ0_SW_OST_S  4
+/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F2_OST    (BIT(5))
+#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
+#define MCPWM_TZ0_F2_OST_V  0x00000001U
+#define MCPWM_TZ0_F2_OST_S  5
+/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F1_OST    (BIT(6))
+#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
+#define MCPWM_TZ0_F1_OST_V  0x00000001U
+#define MCPWM_TZ0_F1_OST_S  6
+/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ0_F0_OST    (BIT(7))
+#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
+#define MCPWM_TZ0_F0_OST_V  0x00000001U
+#define MCPWM_TZ0_F0_OST_S  7
+/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_A_CBC_D    0x00000003U
+#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
+#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_D_S  8
+/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_A_CBC_U    0x00000003U
+#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
+#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_U_S  10
+/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_A_OST_D    0x00000003U
+#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
+#define MCPWM_TZ0_A_OST_D_V  0x00000003U
+#define MCPWM_TZ0_A_OST_D_S  12
+/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_A_OST_U    0x00000003U
+#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
+#define MCPWM_TZ0_A_OST_U_V  0x00000003U
+#define MCPWM_TZ0_A_OST_U_S  14
+/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_B_CBC_D    0x00000003U
+#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
+#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_D_S  16
+/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+ *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_B_CBC_U    0x00000003U
+#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
+#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_U_S  18
+/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_B_OST_D    0x00000003U
+#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
+#define MCPWM_TZ0_B_OST_D_V  0x00000003U
+#define MCPWM_TZ0_B_OST_D_S  20
+/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ0_B_OST_U    0x00000003U
+#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
+#define MCPWM_TZ0_B_OST_U_V  0x00000003U
+#define MCPWM_TZ0_B_OST_U_S  22
+
+/** MCPWM_FH0_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c)
+/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_TZ0_CLR_OST    (BIT(0))
+#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
+#define MCPWM_TZ0_CLR_OST_V  0x00000001U
+#define MCPWM_TZ0_CLR_OST_S  0
+/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP
+ */
+#define MCPWM_TZ0_CBCPULSE    0x00000003U
+#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
+#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ0_CBCPULSE_S  1
+/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
+#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ0_FORCE_CBC_S  3
+/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_TZ0_FORCE_OST    (BIT(4))
+#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
+#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ0_FORCE_OST_S  4
+
+/** MCPWM_FH0_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70)
+/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_TZ0_CBC_ON    (BIT(0))
+#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
+#define MCPWM_TZ0_CBC_ON_V  0x00000001U
+#define MCPWM_TZ0_CBC_ON_S  0
+/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_TZ0_OST_ON    (BIT(1))
+#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
+#define MCPWM_TZ0_OST_ON_V  0x00000001U
+#define MCPWM_TZ0_OST_ON_S  1
+
+/** MCPWM_GEN1_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74)
+/** MCPWM_CMPR1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 1 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR1_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR1_A_UPMETHOD_M  (MCPWM_CMPR1_A_UPMETHOD_V << MCPWM_CMPR1_A_UPMETHOD_S)
+#define MCPWM_CMPR1_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR1_A_UPMETHOD_S  0
+/** MCPWM_CMPR1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 1 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR1_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR1_B_UPMETHOD_M  (MCPWM_CMPR1_B_UPMETHOD_V << MCPWM_CMPR1_B_UPMETHOD_S)
+#define MCPWM_CMPR1_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR1_B_UPMETHOD_S  4
+/** MCPWM_CMPR1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR1_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR1_A_SHDW_FULL_M  (MCPWM_CMPR1_A_SHDW_FULL_V << MCPWM_CMPR1_A_SHDW_FULL_S)
+#define MCPWM_CMPR1_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR1_A_SHDW_FULL_S  8
+/** MCPWM_CMPR1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR1_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR1_B_SHDW_FULL_M  (MCPWM_CMPR1_B_SHDW_FULL_V << MCPWM_CMPR1_B_SHDW_FULL_S)
+#define MCPWM_CMPR1_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR1_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN1_TSTMP_A_REG register
+ *  Shadow register for register A.
+ */
+#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78)
+/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 1 time stamp A's shadow register
+ */
+#define MCPWM_CMPR1_A    0x0000FFFFU
+#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
+#define MCPWM_CMPR1_A_V  0x0000FFFFU
+#define MCPWM_CMPR1_A_S  0
+
+/** MCPWM_GEN1_TSTMP_B_REG register
+ *  Shadow register for register B.
+ */
+#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c)
+/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 1 time stamp B's shadow register
+ */
+#define MCPWM_CMPR1_B    0x0000FFFFU
+#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
+#define MCPWM_CMPR1_B_V  0x0000FFFFU
+#define MCPWM_CMPR1_B_S  0
+
+/** MCPWM_GEN1_CFG0_REG register
+ *  Fault event T0 and T1 handling
+ */
+#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80)
+/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 1's active register of configuration. When all bits
+ *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+ *  1:sync;when bit3 is set to 1:disable the update.
+ */
+#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 1 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN1_T0_SEL    0x00000007U
+#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
+#define MCPWM_GEN1_T0_SEL_V  0x00000007U
+#define MCPWM_GEN1_T0_SEL_S  4
+/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 1 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN1_T1_SEL    0x00000007U
+#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
+#define MCPWM_GEN1_T1_SEL_V  0x00000007U
+#define MCPWM_GEN1_T1_SEL_S  7
+
+/** MCPWM_GEN1_FORCE_REG register
+ *  Permissives to force PWM1A and PWM1B outputs by software
+ */
+#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84)
+/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator 1. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM1A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
+#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM1B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
+#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN1_A_REG register
+ *  Actions triggered by events on PWM1A
+ */
+#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88)
+/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM1A triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN1_A_UTEZ    0x00000003U
+#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
+#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_UTEZ_S  0
+/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM1A triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN1_A_UTEP    0x00000003U
+#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
+#define MCPWM_GEN1_A_UTEP_V  0x00000003U
+#define MCPWM_GEN1_A_UTEP_S  2
+/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM1A triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN1_A_UTEA    0x00000003U
+#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
+#define MCPWM_GEN1_A_UTEA_V  0x00000003U
+#define MCPWM_GEN1_A_UTEA_S  4
+/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM1A triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN1_A_UTEB    0x00000003U
+#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
+#define MCPWM_GEN1_A_UTEB_V  0x00000003U
+#define MCPWM_GEN1_A_UTEB_S  6
+/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM1A triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN1_A_UT0    0x00000003U
+#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
+#define MCPWM_GEN1_A_UT0_V  0x00000003U
+#define MCPWM_GEN1_A_UT0_S  8
+/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM1A triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN1_A_UT1    0x00000003U
+#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
+#define MCPWM_GEN1_A_UT1_V  0x00000003U
+#define MCPWM_GEN1_A_UT1_S  10
+/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM1A triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN1_A_DTEZ    0x00000003U
+#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
+#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_DTEZ_S  12
+/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM1A triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN1_A_DTEP    0x00000003U
+#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
+#define MCPWM_GEN1_A_DTEP_V  0x00000003U
+#define MCPWM_GEN1_A_DTEP_S  14
+/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM1A triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN1_A_DTEA    0x00000003U
+#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
+#define MCPWM_GEN1_A_DTEA_V  0x00000003U
+#define MCPWM_GEN1_A_DTEA_S  16
+/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM1A triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN1_A_DTEB    0x00000003U
+#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
+#define MCPWM_GEN1_A_DTEB_V  0x00000003U
+#define MCPWM_GEN1_A_DTEB_S  18
+/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM1A triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN1_A_DT0    0x00000003U
+#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
+#define MCPWM_GEN1_A_DT0_V  0x00000003U
+#define MCPWM_GEN1_A_DT0_S  20
+/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_DT1    0x00000003U
+#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
+#define MCPWM_GEN1_A_DT1_V  0x00000003U
+#define MCPWM_GEN1_A_DT1_S  22
+
+/** MCPWM_GEN1_B_REG register
+ *  Actions triggered by events on PWM1B
+ */
+#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c)
+/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM1B triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN1_B_UTEZ    0x00000003U
+#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
+#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_UTEZ_S  0
+/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM1B triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN1_B_UTEP    0x00000003U
+#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
+#define MCPWM_GEN1_B_UTEP_V  0x00000003U
+#define MCPWM_GEN1_B_UTEP_S  2
+/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM1B triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN1_B_UTEA    0x00000003U
+#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
+#define MCPWM_GEN1_B_UTEA_V  0x00000003U
+#define MCPWM_GEN1_B_UTEA_S  4
+/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM1B triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN1_B_UTEB    0x00000003U
+#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
+#define MCPWM_GEN1_B_UTEB_V  0x00000003U
+#define MCPWM_GEN1_B_UTEB_S  6
+/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM1B triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN1_B_UT0    0x00000003U
+#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
+#define MCPWM_GEN1_B_UT0_V  0x00000003U
+#define MCPWM_GEN1_B_UT0_S  8
+/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM1B triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN1_B_UT1    0x00000003U
+#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
+#define MCPWM_GEN1_B_UT1_V  0x00000003U
+#define MCPWM_GEN1_B_UT1_S  10
+/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM1B triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN1_B_DTEZ    0x00000003U
+#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
+#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_DTEZ_S  12
+/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM1B triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN1_B_DTEP    0x00000003U
+#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
+#define MCPWM_GEN1_B_DTEP_V  0x00000003U
+#define MCPWM_GEN1_B_DTEP_S  14
+/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM1B triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN1_B_DTEA    0x00000003U
+#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
+#define MCPWM_GEN1_B_DTEA_V  0x00000003U
+#define MCPWM_GEN1_B_DTEA_S  16
+/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM1B triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN1_B_DTEB    0x00000003U
+#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
+#define MCPWM_GEN1_B_DTEB_V  0x00000003U
+#define MCPWM_GEN1_B_DTEB_S  18
+/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM1B triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN1_B_DT0    0x00000003U
+#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
+#define MCPWM_GEN1_B_DT0_V  0x00000003U
+#define MCPWM_GEN1_B_DT0_S  20
+/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_DT1    0x00000003U
+#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
+#define MCPWM_GEN1_B_DT1_V  0x00000003U
+#define MCPWM_GEN1_B_DT1_S  22
+
+/** MCPWM_DT1_CFG_REG register
+ *  dead time type selection and configuration
+ */
+#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90)
+/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (falling edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
+#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_S  0
+/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register. 0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
+#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_S  4
+/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB1_DEB_MODE    (BIT(8))
+#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
+#define MCPWM_DB1_DEB_MODE_V  0x00000001U
+#define MCPWM_DB1_DEB_MODE_S  8
+/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
+#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_A_OUTSWAP_S  9
+/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
+#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_B_OUTSWAP_S  10
+/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DB1_RED_INSEL    (BIT(11))
+#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
+#define MCPWM_DB1_RED_INSEL_V  0x00000001U
+#define MCPWM_DB1_RED_INSEL_S  11
+/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DB1_FED_INSEL    (BIT(12))
+#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
+#define MCPWM_DB1_FED_INSEL_V  0x00000001U
+#define MCPWM_DB1_FED_INSEL_S  12
+/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
+#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_RED_OUTINVERT_S  13
+/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
+#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_FED_OUTINVERT_S  14
+/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
+#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_A_OUTBYPASS_S  15
+/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
+#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_B_OUTBYPASS_S  16
+/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DB1_CLK_SEL    (BIT(17))
+#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
+#define MCPWM_DB1_CLK_SEL_V  0x00000001U
+#define MCPWM_DB1_CLK_SEL_S  17
+
+/** MCPWM_DT1_FED_CFG_REG register
+ *  Shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94)
+/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DB1_FED    0x0000FFFFU
+#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
+#define MCPWM_DB1_FED_V  0x0000FFFFU
+#define MCPWM_DB1_FED_S  0
+
+/** MCPWM_DT1_RED_CFG_REG register
+ *  Shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98)
+/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DB1_RED    0x0000FFFFU
+#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
+#define MCPWM_DB1_RED_V  0x0000FFFFU
+#define MCPWM_DB1_RED_S  0
+
+/** MCPWM_CARRIER1_CFG_REG register
+ *  Carrier enable and configuration
+ */
+#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c)
+/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier1 function is enabled. When cleared, carrier1 is bypassed
+ */
+#define MCPWM_CHOPPER1_EN    (BIT(0))
+#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
+#define MCPWM_CHOPPER1_EN_V  0x00000001U
+#define MCPWM_CHOPPER1_EN_S  0
+/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
+#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_S  1
+/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CHOPPER1_DUTY    0x00000007U
+#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
+#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER1_DUTY_S  5
+/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
+#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_S  8
+/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM1A and PWM1B for this submodule
+ */
+#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
+#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_OUT_INVERT_S  12
+/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM1A and PWM1B for this submodule
+ */
+#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
+#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_IN_INVERT_S  13
+
+/** MCPWM_FH1_CFG0_REG register
+ *  Actions on PWM1A and PWM1B trip events
+ */
+#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0)
+/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_SW_CBC    (BIT(0))
+#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
+#define MCPWM_TZ1_SW_CBC_V  0x00000001U
+#define MCPWM_TZ1_SW_CBC_S  0
+/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F2_CBC    (BIT(1))
+#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
+#define MCPWM_TZ1_F2_CBC_V  0x00000001U
+#define MCPWM_TZ1_F2_CBC_S  1
+/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F1_CBC    (BIT(2))
+#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
+#define MCPWM_TZ1_F1_CBC_V  0x00000001U
+#define MCPWM_TZ1_F1_CBC_S  2
+/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F0_CBC    (BIT(3))
+#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
+#define MCPWM_TZ1_F0_CBC_V  0x00000001U
+#define MCPWM_TZ1_F0_CBC_S  3
+/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_SW_OST    (BIT(4))
+#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
+#define MCPWM_TZ1_SW_OST_V  0x00000001U
+#define MCPWM_TZ1_SW_OST_S  4
+/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F2_OST    (BIT(5))
+#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
+#define MCPWM_TZ1_F2_OST_V  0x00000001U
+#define MCPWM_TZ1_F2_OST_S  5
+/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F1_OST    (BIT(6))
+#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
+#define MCPWM_TZ1_F1_OST_V  0x00000001U
+#define MCPWM_TZ1_F1_OST_S  6
+/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ1_F0_OST    (BIT(7))
+#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
+#define MCPWM_TZ1_F0_OST_V  0x00000001U
+#define MCPWM_TZ1_F0_OST_S  7
+/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_A_CBC_D    0x00000003U
+#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
+#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_D_S  8
+/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_A_CBC_U    0x00000003U
+#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
+#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_U_S  10
+/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0:
+ *  do nothing,1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_A_OST_D    0x00000003U
+#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
+#define MCPWM_TZ1_A_OST_D_V  0x00000003U
+#define MCPWM_TZ1_A_OST_D_S  12
+/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_A_OST_U    0x00000003U
+#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
+#define MCPWM_TZ1_A_OST_U_V  0x00000003U
+#define MCPWM_TZ1_A_OST_U_S  14
+/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_B_CBC_D    0x00000003U
+#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
+#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_D_S  16
+/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_B_CBC_U    0x00000003U
+#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
+#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_U_S  18
+/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_B_OST_D    0x00000003U
+#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
+#define MCPWM_TZ1_B_OST_D_V  0x00000003U
+#define MCPWM_TZ1_B_OST_D_S  20
+/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ1_B_OST_U    0x00000003U
+#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
+#define MCPWM_TZ1_B_OST_U_V  0x00000003U
+#define MCPWM_TZ1_B_OST_U_S  22
+
+/** MCPWM_FH1_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4)
+/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_TZ1_CLR_OST    (BIT(0))
+#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
+#define MCPWM_TZ1_CLR_OST_V  0x00000001U
+#define MCPWM_TZ1_CLR_OST_S  0
+/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP
+ */
+#define MCPWM_TZ1_CBCPULSE    0x00000003U
+#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
+#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ1_CBCPULSE_S  1
+/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
+#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ1_FORCE_CBC_S  3
+/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_TZ1_FORCE_OST    (BIT(4))
+#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
+#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ1_FORCE_OST_S  4
+
+/** MCPWM_FH1_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8)
+/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_TZ1_CBC_ON    (BIT(0))
+#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
+#define MCPWM_TZ1_CBC_ON_V  0x00000001U
+#define MCPWM_TZ1_CBC_ON_S  0
+/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_TZ1_OST_ON    (BIT(1))
+#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
+#define MCPWM_TZ1_OST_ON_V  0x00000001U
+#define MCPWM_TZ1_OST_ON_S  1
+
+/** MCPWM_GEN2_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac)
+/** MCPWM_CMPR2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 2 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR2_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR2_A_UPMETHOD_M  (MCPWM_CMPR2_A_UPMETHOD_V << MCPWM_CMPR2_A_UPMETHOD_S)
+#define MCPWM_CMPR2_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR2_A_UPMETHOD_S  0
+/** MCPWM_CMPR2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 2 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_CMPR2_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR2_B_UPMETHOD_M  (MCPWM_CMPR2_B_UPMETHOD_V << MCPWM_CMPR2_B_UPMETHOD_S)
+#define MCPWM_CMPR2_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR2_B_UPMETHOD_S  4
+/** MCPWM_CMPR2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR2_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR2_A_SHDW_FULL_M  (MCPWM_CMPR2_A_SHDW_FULL_V << MCPWM_CMPR2_A_SHDW_FULL_S)
+#define MCPWM_CMPR2_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR2_A_SHDW_FULL_S  8
+/** MCPWM_CMPR2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_CMPR2_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR2_B_SHDW_FULL_M  (MCPWM_CMPR2_B_SHDW_FULL_V << MCPWM_CMPR2_B_SHDW_FULL_S)
+#define MCPWM_CMPR2_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR2_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN2_TSTMP_A_REG register
+ *  Shadow register for register A.
+ */
+#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0)
+/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 2 time stamp A's shadow register
+ */
+#define MCPWM_CMPR2_A    0x0000FFFFU
+#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
+#define MCPWM_CMPR2_A_V  0x0000FFFFU
+#define MCPWM_CMPR2_A_S  0
+
+/** MCPWM_GEN2_TSTMP_B_REG register
+ *  Shadow register for register B.
+ */
+#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4)
+/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 2 time stamp B's shadow register
+ */
+#define MCPWM_CMPR2_B    0x0000FFFFU
+#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
+#define MCPWM_CMPR2_B_V  0x0000FFFFU
+#define MCPWM_CMPR2_B_S  0
+
+/** MCPWM_GEN2_CFG0_REG register
+ *  Fault event T0 and T1 handling
+ */
+#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8)
+/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 2's active register of configuration. 0:
+ *  immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is
+ *  set to 1:disable the update.
+ */
+#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 2 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN2_T0_SEL    0x00000007U
+#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
+#define MCPWM_GEN2_T0_SEL_V  0x00000007U
+#define MCPWM_GEN2_T0_SEL_S  4
+/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 2 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN2_T1_SEL    0x00000007U
+#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
+#define MCPWM_GEN2_T1_SEL_V  0x00000007U
+#define MCPWM_GEN2_T1_SEL_S  7
+
+/** MCPWM_GEN2_FORCE_REG register
+ *  Permissives to force PWM2A and PWM2B outputs by software
+ */
+#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc)
+/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator 2. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM2A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
+#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM2B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
+#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN2_A_REG register
+ *  Actions triggered by events on PWM2A
+ */
+#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0)
+/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM2A triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN2_A_UTEZ    0x00000003U
+#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
+#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_UTEZ_S  0
+/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM2A triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN2_A_UTEP    0x00000003U
+#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
+#define MCPWM_GEN2_A_UTEP_V  0x00000003U
+#define MCPWM_GEN2_A_UTEP_S  2
+/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM2A triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN2_A_UTEA    0x00000003U
+#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
+#define MCPWM_GEN2_A_UTEA_V  0x00000003U
+#define MCPWM_GEN2_A_UTEA_S  4
+/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM2A triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN2_A_UTEB    0x00000003U
+#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
+#define MCPWM_GEN2_A_UTEB_V  0x00000003U
+#define MCPWM_GEN2_A_UTEB_S  6
+/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM2A triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN2_A_UT0    0x00000003U
+#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
+#define MCPWM_GEN2_A_UT0_V  0x00000003U
+#define MCPWM_GEN2_A_UT0_S  8
+/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM2A triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN2_A_UT1    0x00000003U
+#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
+#define MCPWM_GEN2_A_UT1_V  0x00000003U
+#define MCPWM_GEN2_A_UT1_S  10
+/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM2A triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN2_A_DTEZ    0x00000003U
+#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
+#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_DTEZ_S  12
+/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM2A triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN2_A_DTEP    0x00000003U
+#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
+#define MCPWM_GEN2_A_DTEP_V  0x00000003U
+#define MCPWM_GEN2_A_DTEP_S  14
+/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM2A triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN2_A_DTEA    0x00000003U
+#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
+#define MCPWM_GEN2_A_DTEA_V  0x00000003U
+#define MCPWM_GEN2_A_DTEA_S  16
+/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM2A triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN2_A_DTEB    0x00000003U
+#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
+#define MCPWM_GEN2_A_DTEB_V  0x00000003U
+#define MCPWM_GEN2_A_DTEB_S  18
+/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM2A triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN2_A_DT0    0x00000003U
+#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
+#define MCPWM_GEN2_A_DT0_V  0x00000003U
+#define MCPWM_GEN2_A_DT0_S  20
+/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_DT1    0x00000003U
+#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
+#define MCPWM_GEN2_A_DT1_V  0x00000003U
+#define MCPWM_GEN2_A_DT1_S  22
+
+/** MCPWM_GEN2_B_REG register
+ *  Actions triggered by events on PWM2B
+ */
+#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4)
+/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM2B triggered by event TEZ when timer increasing
+ */
+#define MCPWM_GEN2_B_UTEZ    0x00000003U
+#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
+#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_UTEZ_S  0
+/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM2B triggered by event TEP when timer increasing
+ */
+#define MCPWM_GEN2_B_UTEP    0x00000003U
+#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
+#define MCPWM_GEN2_B_UTEP_V  0x00000003U
+#define MCPWM_GEN2_B_UTEP_S  2
+/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM2B triggered by event TEA when timer increasing
+ */
+#define MCPWM_GEN2_B_UTEA    0x00000003U
+#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
+#define MCPWM_GEN2_B_UTEA_V  0x00000003U
+#define MCPWM_GEN2_B_UTEA_S  4
+/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM2B triggered by event TEB when timer increasing
+ */
+#define MCPWM_GEN2_B_UTEB    0x00000003U
+#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
+#define MCPWM_GEN2_B_UTEB_V  0x00000003U
+#define MCPWM_GEN2_B_UTEB_S  6
+/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM2B triggered by event_t0 when timer increasing
+ */
+#define MCPWM_GEN2_B_UT0    0x00000003U
+#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
+#define MCPWM_GEN2_B_UT0_V  0x00000003U
+#define MCPWM_GEN2_B_UT0_S  8
+/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM2B triggered by event_t1 when timer increasing
+ */
+#define MCPWM_GEN2_B_UT1    0x00000003U
+#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
+#define MCPWM_GEN2_B_UT1_V  0x00000003U
+#define MCPWM_GEN2_B_UT1_S  10
+/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM2B triggered by event TEZ when timer decreasing
+ */
+#define MCPWM_GEN2_B_DTEZ    0x00000003U
+#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
+#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_DTEZ_S  12
+/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM2B triggered by event TEP when timer decreasing
+ */
+#define MCPWM_GEN2_B_DTEP    0x00000003U
+#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
+#define MCPWM_GEN2_B_DTEP_V  0x00000003U
+#define MCPWM_GEN2_B_DTEP_S  14
+/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM2B triggered by event TEA when timer decreasing
+ */
+#define MCPWM_GEN2_B_DTEA    0x00000003U
+#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
+#define MCPWM_GEN2_B_DTEA_V  0x00000003U
+#define MCPWM_GEN2_B_DTEA_S  16
+/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM2B triggered by event TEB when timer decreasing
+ */
+#define MCPWM_GEN2_B_DTEB    0x00000003U
+#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
+#define MCPWM_GEN2_B_DTEB_V  0x00000003U
+#define MCPWM_GEN2_B_DTEB_S  18
+/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM2B triggered by event_t0 when timer decreasing
+ */
+#define MCPWM_GEN2_B_DT0    0x00000003U
+#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
+#define MCPWM_GEN2_B_DT0_V  0x00000003U
+#define MCPWM_GEN2_B_DT0_S  20
+/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_DT1    0x00000003U
+#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
+#define MCPWM_GEN2_B_DT1_V  0x00000003U
+#define MCPWM_GEN2_B_DT1_S  22
+
+/** MCPWM_DT2_CFG_REG register
+ *  dead time type selection and configuration
+ */
+#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8)
+/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (falling edge delay) active register.  0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
+#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_S  0
+/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register.  0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
+#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_S  4
+/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB2_DEB_MODE    (BIT(8))
+#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
+#define MCPWM_DB2_DEB_MODE_V  0x00000001U
+#define MCPWM_DB2_DEB_MODE_S  8
+/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
+#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_A_OUTSWAP_S  9
+/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
+#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_B_OUTSWAP_S  10
+/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DB2_RED_INSEL    (BIT(11))
+#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
+#define MCPWM_DB2_RED_INSEL_V  0x00000001U
+#define MCPWM_DB2_RED_INSEL_S  11
+/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DB2_FED_INSEL    (BIT(12))
+#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
+#define MCPWM_DB2_FED_INSEL_V  0x00000001U
+#define MCPWM_DB2_FED_INSEL_S  12
+/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
+#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_RED_OUTINVERT_S  13
+/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
+#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_FED_OUTINVERT_S  14
+/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
+#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_A_OUTBYPASS_S  15
+/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
+#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_B_OUTBYPASS_S  16
+/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DB2_CLK_SEL    (BIT(17))
+#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
+#define MCPWM_DB2_CLK_SEL_V  0x00000001U
+#define MCPWM_DB2_CLK_SEL_S  17
+
+/** MCPWM_DT2_FED_CFG_REG register
+ *  Shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc)
+/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DB2_FED    0x0000FFFFU
+#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
+#define MCPWM_DB2_FED_V  0x0000FFFFU
+#define MCPWM_DB2_FED_S  0
+
+/** MCPWM_DT2_RED_CFG_REG register
+ *  Shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0)
+/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DB2_RED    0x0000FFFFU
+#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
+#define MCPWM_DB2_RED_V  0x0000FFFFU
+#define MCPWM_DB2_RED_S  0
+
+/** MCPWM_CARRIER2_CFG_REG register
+ *  Carrier enable and configuration
+ */
+#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4)
+/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier2 function is enabled. When cleared, carrier2 is bypassed
+ */
+#define MCPWM_CHOPPER2_EN    (BIT(0))
+#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
+#define MCPWM_CHOPPER2_EN_V  0x00000001U
+#define MCPWM_CHOPPER2_EN_S  0
+/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
+#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_S  1
+/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CHOPPER2_DUTY    0x00000007U
+#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
+#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER2_DUTY_S  5
+/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
+#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_S  8
+/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM2A and PWM2B for this submodule
+ */
+#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
+#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_OUT_INVERT_S  12
+/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM2A and PWM2B for this submodule
+ */
+#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
+#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_IN_INVERT_S  13
+
+/** MCPWM_FH2_CFG0_REG register
+ *  Actions on PWM2A and PWM2B trip events
+ */
+#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8)
+/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_SW_CBC    (BIT(0))
+#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
+#define MCPWM_TZ2_SW_CBC_V  0x00000001U
+#define MCPWM_TZ2_SW_CBC_S  0
+/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F2_CBC    (BIT(1))
+#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
+#define MCPWM_TZ2_F2_CBC_V  0x00000001U
+#define MCPWM_TZ2_F2_CBC_S  1
+/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F1_CBC    (BIT(2))
+#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
+#define MCPWM_TZ2_F1_CBC_V  0x00000001U
+#define MCPWM_TZ2_F1_CBC_S  2
+/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F0_CBC    (BIT(3))
+#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
+#define MCPWM_TZ2_F0_CBC_V  0x00000001U
+#define MCPWM_TZ2_F0_CBC_S  3
+/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_SW_OST    (BIT(4))
+#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
+#define MCPWM_TZ2_SW_OST_V  0x00000001U
+#define MCPWM_TZ2_SW_OST_S  4
+/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F2_OST    (BIT(5))
+#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
+#define MCPWM_TZ2_F2_OST_V  0x00000001U
+#define MCPWM_TZ2_F2_OST_S  5
+/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F1_OST    (BIT(6))
+#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
+#define MCPWM_TZ2_F1_OST_V  0x00000001U
+#define MCPWM_TZ2_F1_OST_S  6
+/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_TZ2_F0_OST    (BIT(7))
+#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
+#define MCPWM_TZ2_F0_OST_V  0x00000001U
+#define MCPWM_TZ2_F0_OST_S  7
+/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_A_CBC_D    0x00000003U
+#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
+#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_D_S  8
+/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_A_CBC_U    0x00000003U
+#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
+#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_U_S  10
+/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_A_OST_D    0x00000003U
+#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
+#define MCPWM_TZ2_A_OST_D_V  0x00000003U
+#define MCPWM_TZ2_A_OST_D_S  12
+/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_A_OST_U    0x00000003U
+#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
+#define MCPWM_TZ2_A_OST_U_V  0x00000003U
+#define MCPWM_TZ2_A_OST_U_S  14
+/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_B_CBC_D    0x00000003U
+#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
+#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_D_S  16
+/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_B_CBC_U    0x00000003U
+#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
+#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_U_S  18
+/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_B_OST_D    0x00000003U
+#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
+#define MCPWM_TZ2_B_OST_D_V  0x00000003U
+#define MCPWM_TZ2_B_OST_D_S  20
+/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_TZ2_B_OST_U    0x00000003U
+#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
+#define MCPWM_TZ2_B_OST_U_V  0x00000003U
+#define MCPWM_TZ2_B_OST_U_S  22
+
+/** MCPWM_FH2_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc)
+/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_TZ2_CLR_OST    (BIT(0))
+#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
+#define MCPWM_TZ2_CLR_OST_V  0x00000001U
+#define MCPWM_TZ2_CLR_OST_S  0
+/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP
+ */
+#define MCPWM_TZ2_CBCPULSE    0x00000003U
+#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
+#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ2_CBCPULSE_S  1
+/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
+#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ2_FORCE_CBC_S  3
+/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_TZ2_FORCE_OST    (BIT(4))
+#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
+#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ2_FORCE_OST_S  4
+
+/** MCPWM_FH2_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0)
+/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_TZ2_CBC_ON    (BIT(0))
+#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
+#define MCPWM_TZ2_CBC_ON_V  0x00000001U
+#define MCPWM_TZ2_CBC_ON_S  0
+/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_TZ2_OST_ON    (BIT(1))
+#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
+#define MCPWM_TZ2_OST_ON_V  0x00000001U
+#define MCPWM_TZ2_OST_ON_S  1
+
+/** MCPWM_FAULT_DETECT_REG register
+ *  Fault detection configuration and status
+ */
+#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4)
+/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, event_f0 generation is enabled
+ */
+#define MCPWM_F0_EN    (BIT(0))
+#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
+#define MCPWM_F0_EN_V  0x00000001U
+#define MCPWM_F0_EN_S  0
+/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
+ *  When set, event_f1 generation is enabled
+ */
+#define MCPWM_F1_EN    (BIT(1))
+#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
+#define MCPWM_F1_EN_V  0x00000001U
+#define MCPWM_F1_EN_S  1
+/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
+ *  When set, event_f2 generation is enabled
+ */
+#define MCPWM_F2_EN    (BIT(2))
+#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
+#define MCPWM_F2_EN_V  0x00000001U
+#define MCPWM_F2_EN_S  2
+/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
+ *  Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+ *  level high
+ */
+#define MCPWM_F0_POLE    (BIT(3))
+#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
+#define MCPWM_F0_POLE_V  0x00000001U
+#define MCPWM_F0_POLE_S  3
+/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
+ *  Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+ *  level high
+ */
+#define MCPWM_F1_POLE    (BIT(4))
+#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
+#define MCPWM_F1_POLE_V  0x00000001U
+#define MCPWM_F1_POLE_S  4
+/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
+ *  Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+ *  level high
+ */
+#define MCPWM_F2_POLE    (BIT(5))
+#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
+#define MCPWM_F2_POLE_V  0x00000001U
+#define MCPWM_F2_POLE_S  5
+/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
+ *  Set and reset by hardware. If set, event_f0 is on going
+ */
+#define MCPWM_EVENT_F0    (BIT(6))
+#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
+#define MCPWM_EVENT_F0_V  0x00000001U
+#define MCPWM_EVENT_F0_S  6
+/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
+ *  Set and reset by hardware. If set, event_f1 is on going
+ */
+#define MCPWM_EVENT_F1    (BIT(7))
+#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
+#define MCPWM_EVENT_F1_V  0x00000001U
+#define MCPWM_EVENT_F1_S  7
+/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, event_f2 is on going
+ */
+#define MCPWM_EVENT_F2    (BIT(8))
+#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
+#define MCPWM_EVENT_F2_V  0x00000001U
+#define MCPWM_EVENT_F2_S  8
+
+/** MCPWM_CAP_TIMER_CFG_REG register
+ *  Configure capture timer
+ */
+#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8)
+/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture timer incrementing under APB_clk is enabled.
+ */
+#define MCPWM_CAP_TIMER_EN    (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
+#define MCPWM_CAP_TIMER_EN_V  0x00000001U
+#define MCPWM_CAP_TIMER_EN_S  0
+/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
+ *  When set, capture timer sync is enabled.
+ */
+#define MCPWM_CAP_SYNCI_EN    (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
+#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
+#define MCPWM_CAP_SYNCI_EN_S  1
+/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
+ *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
+ *  6: SYNC2 from GPIO matrix
+ */
+#define MCPWM_CAP_SYNCI_SEL    0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
+#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
+ *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
+ *  timer is loaded with value in phase register.
+ */
+#define MCPWM_CAP_SYNC_SW    (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
+#define MCPWM_CAP_SYNC_SW_V  0x00000001U
+#define MCPWM_CAP_SYNC_SW_S  5
+
+/** MCPWM_CAP_TIMER_PHASE_REG register
+ *  Phase for capture timer sync
+ */
+#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec)
+/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
+ *  Phase value for capture timer sync operation.
+ */
+#define MCPWM_CAP_PHASE    0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
+#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_S  0
+
+/** MCPWM_CAP_CH0_CFG_REG register
+ *  Capture channel 0 configuration and enable
+ */
+#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 0 is enabled
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP0 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 0
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH1_CFG_REG register
+ *  Capture channel 1 configuration and enable
+ */
+#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4)
+/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 2 is enabled
+ */
+#define MCPWM_CAP1_EN    (BIT(0))
+#define MCPWM_CAP1_EN_M  (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S)
+#define MCPWM_CAP1_EN_V  0x00000001U
+#define MCPWM_CAP1_EN_S  0
+/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP1_MODE    0x00000003U
+#define MCPWM_CAP1_MODE_M  (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S)
+#define MCPWM_CAP1_MODE_V  0x00000003U
+#define MCPWM_CAP1_MODE_S  1
+/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP1_PRESCALE    0x000000FFU
+#define MCPWM_CAP1_PRESCALE_M  (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S)
+#define MCPWM_CAP1_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP1_PRESCALE_S  3
+/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP1 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP1_IN_INVERT    (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_M  (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S)
+#define MCPWM_CAP1_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP1_IN_INVERT_S  11
+/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 1
+ */
+#define MCPWM_CAP1_SW    (BIT(12))
+#define MCPWM_CAP1_SW_M  (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S)
+#define MCPWM_CAP1_SW_V  0x00000001U
+#define MCPWM_CAP1_SW_S  12
+
+/** MCPWM_CAP_CH2_CFG_REG register
+ *  Capture channel 2 configuration and enable
+ */
+#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8)
+/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 2 is enabled
+ */
+#define MCPWM_CAP2_EN    (BIT(0))
+#define MCPWM_CAP2_EN_M  (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S)
+#define MCPWM_CAP2_EN_V  0x00000001U
+#define MCPWM_CAP2_EN_S  0
+/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP2_MODE    0x00000003U
+#define MCPWM_CAP2_MODE_M  (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S)
+#define MCPWM_CAP2_MODE_V  0x00000003U
+#define MCPWM_CAP2_MODE_S  1
+/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP2_PRESCALE    0x000000FFU
+#define MCPWM_CAP2_PRESCALE_M  (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S)
+#define MCPWM_CAP2_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP2_PRESCALE_S  3
+/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP2 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP2_IN_INVERT    (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_M  (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S)
+#define MCPWM_CAP2_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP2_IN_INVERT_S  11
+/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 2
+ */
+#define MCPWM_CAP2_SW    (BIT(12))
+#define MCPWM_CAP2_SW_M  (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S)
+#define MCPWM_CAP2_SW_V  0x00000001U
+#define MCPWM_CAP2_SW_S  12
+
+/** MCPWM_CAP_CH0_REG register
+ *  ch0 capture value status register
+ */
+#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 0
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_CH1_REG register
+ *  ch1 capture value status register
+ */
+#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100)
+/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 1
+ */
+#define MCPWM_CAP1_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP1_VALUE_M  (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S)
+#define MCPWM_CAP1_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP1_VALUE_S  0
+
+/** MCPWM_CAP_CH2_REG register
+ *  ch2 capture value status register
+ */
+#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104)
+/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 2
+ */
+#define MCPWM_CAP2_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP2_VALUE_M  (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S)
+#define MCPWM_CAP2_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP2_VALUE_S  0
+
+/** MCPWM_CAP_STATUS_REG register
+ *  Edge of last capture trigger
+ */
+#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108)
+/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
+ *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP0_EDGE    (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
+#define MCPWM_CAP0_EDGE_V  0x00000001U
+#define MCPWM_CAP0_EDGE_S  0
+/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
+ *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP1_EDGE    (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
+#define MCPWM_CAP1_EDGE_V  0x00000001U
+#define MCPWM_CAP1_EDGE_S  1
+/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
+ *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP2_EDGE    (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
+#define MCPWM_CAP2_EDGE_V  0x00000001U
+#define MCPWM_CAP2_EDGE_S  2
+
+/** MCPWM_UPDATE_CFG_REG register
+ *  Enable update.
+ */
+#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c)
+/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
+ *  The global enable of update of all active registers in MCPWM module
+ */
+#define MCPWM_GLOBAL_UP_EN    (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
+#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
+#define MCPWM_GLOBAL_UP_EN_S  0
+/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of all active
+ *  registers in MCPWM module
+ */
+#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
+#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
+ *  are enabled
+ */
+#define MCPWM_OP0_UP_EN    (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
+#define MCPWM_OP0_UP_EN_V  0x00000001U
+#define MCPWM_OP0_UP_EN_S  2
+/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 0
+ */
+#define MCPWM_OP0_FORCE_UP    (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
+#define MCPWM_OP0_FORCE_UP_V  0x00000001U
+#define MCPWM_OP0_FORCE_UP_S  3
+/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
+ *  are enabled
+ */
+#define MCPWM_OP1_UP_EN    (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
+#define MCPWM_OP1_UP_EN_V  0x00000001U
+#define MCPWM_OP1_UP_EN_S  4
+/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 1
+ */
+#define MCPWM_OP1_FORCE_UP    (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
+#define MCPWM_OP1_FORCE_UP_V  0x00000001U
+#define MCPWM_OP1_FORCE_UP_S  5
+/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
+ *  are enabled
+ */
+#define MCPWM_OP2_UP_EN    (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
+#define MCPWM_OP2_UP_EN_V  0x00000001U
+#define MCPWM_OP2_UP_EN_S  6
+/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 2
+ */
+#define MCPWM_OP2_FORCE_UP    (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
+#define MCPWM_OP2_FORCE_UP_V  0x00000001U
+#define MCPWM_OP2_FORCE_UP_S  7
+
+/** MCPWM_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110)
+/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ENA    (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
+#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_INT_ENA_S  9
+/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ENA    (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
+#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_INT_ENA_S  10
+/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ENA    (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
+#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_INT_ENA_S  11
+/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable bit for the interrupt triggered when event_f2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
+#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ENA_S  15
+/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
+#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ENA_S  16
+/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
+#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ENA_S  17
+/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
+#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ENA_S  18
+/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
+#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ENA_S  19
+/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
+#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ENA_S  20
+/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
+#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ENA_S  21
+/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
+#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ENA_S  22
+/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
+#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ENA_S  23
+/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
+#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ENA_S  24
+/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
+#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ENA_S  25
+/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
+#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ENA_S  26
+/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_ENA    (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
+#define MCPWM_CAP0_INT_ENA_V  0x00000001U
+#define MCPWM_CAP0_INT_ENA_S  27
+/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_ENA    (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
+#define MCPWM_CAP1_INT_ENA_V  0x00000001U
+#define MCPWM_CAP1_INT_ENA_S  28
+/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_ENA    (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
+#define MCPWM_CAP2_INT_ENA_V  0x00000001U
+#define MCPWM_CAP2_INT_ENA_S  29
+
+/** MCPWM_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114)
+/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_RAW    (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
+#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_INT_RAW_S  9
+/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_RAW    (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
+#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_INT_RAW_S  10
+/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_RAW    (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
+#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_INT_RAW_S  11
+/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw status bit for the interrupt triggered when event_f2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
+#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_RAW_S  15
+/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
+#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_RAW_S  16
+/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
+#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_RAW_S  17
+/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
+#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_RAW_S  18
+/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
+#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_RAW_S  19
+/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
+#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_RAW_S  20
+/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
+#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_RAW_S  21
+/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
+#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_RAW_S  22
+/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
+#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_RAW_S  23
+/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
+#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
+#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_RAW_S  24
+/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
+#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
+#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_RAW_S  25
+/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
+#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
+#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_RAW_S  26
+/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_RAW    (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
+#define MCPWM_CAP0_INT_RAW_V  0x00000001U
+#define MCPWM_CAP0_INT_RAW_S  27
+/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_RAW    (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
+#define MCPWM_CAP1_INT_RAW_V  0x00000001U
+#define MCPWM_CAP1_INT_RAW_S  28
+/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_RAW    (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
+#define MCPWM_CAP2_INT_RAW_V  0x00000001U
+#define MCPWM_CAP2_INT_RAW_S  29
+
+/** MCPWM_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118)
+/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ST    (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
+#define MCPWM_FAULT0_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_INT_ST_S  9
+/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ST    (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
+#define MCPWM_FAULT1_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_INT_ST_S  10
+/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ST    (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
+#define MCPWM_FAULT2_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_INT_ST_S  11
+/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked status bit for the interrupt triggered when event_f2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
+#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ST_S  15
+/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
+#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ST_S  16
+/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
+#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ST_S  17
+/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
+#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ST_S  18
+/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
+#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ST_S  19
+/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
+#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ST_S  20
+/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
+#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ST_S  21
+/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
+#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ST_S  22
+/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
+#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ST_S  23
+/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
+#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ST_S  24
+/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
+#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ST_S  25
+/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
+#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ST_S  26
+/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_ST    (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
+#define MCPWM_CAP0_INT_ST_V  0x00000001U
+#define MCPWM_CAP0_INT_ST_S  27
+/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_ST    (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
+#define MCPWM_CAP1_INT_ST_V  0x00000001U
+#define MCPWM_CAP1_INT_ST_S  28
+/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_ST    (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
+#define MCPWM_CAP2_INT_ST_V  0x00000001U
+#define MCPWM_CAP2_INT_ST_S  29
+
+/** MCPWM_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c)
+/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_CLR    (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
+#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_INT_CLR_S  9
+/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_CLR    (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
+#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_INT_CLR_S  10
+/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_CLR    (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
+#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_INT_CLR_S  11
+/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the interrupt triggered when event_f2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
+#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_CLR_S  15
+/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
+#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_CLR_S  16
+/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
+#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_CLR_S  17
+/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
+#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_CLR_S  18
+/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
+#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_CLR_S  19
+/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
+#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_CLR_S  20
+/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
+#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_CLR_S  21
+/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
+#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_CLR_S  22
+/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
+#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_CLR_S  23
+/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
+#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
+#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_CLR_S  24
+/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
+#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
+#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_CLR_S  25
+/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
+#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
+#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_CLR_S  26
+/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_CLR    (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
+#define MCPWM_CAP0_INT_CLR_V  0x00000001U
+#define MCPWM_CAP0_INT_CLR_S  27
+/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_CLR    (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
+#define MCPWM_CAP1_INT_CLR_V  0x00000001U
+#define MCPWM_CAP1_INT_CLR_S  28
+/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_CLR    (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
+#define MCPWM_CAP2_INT_CLR_V  0x00000001U
+#define MCPWM_CAP2_INT_CLR_S  29
+
+/** MCPWM_EVT_EN_REG register
+ *  MCPWM event enable register
+ */
+#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120)
+/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit high to enable timer0 stop event generate
+ */
+#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
+#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
+#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_STOP_EN_S  0
+/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
+ *  set this bit high to enable timer1 stop event generate
+ */
+#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
+#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
+#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_STOP_EN_S  1
+/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
+ *  set this bit high to enable timer2 stop event generate
+ */
+#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
+#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
+#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_STOP_EN_S  2
+/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
+ *  set this bit high to enable timer0 equal zero event generate
+ */
+#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
+#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
+#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
+/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
+ *  set this bit high to enable timer1 equal zero event generate
+ */
+#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
+#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
+#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
+/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
+ *  set this bit high to enable timer2 equal zero event generate
+ */
+#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
+#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
+#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
+/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
+ *  set this bit high to enable timer0 equal period event generate
+ */
+#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
+#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
+#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEP_EN_S  6
+/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
+ *  set this bit high to enable timer1 equal period event generate
+ */
+#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
+#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
+#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEP_EN_S  7
+/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
+ *  set this bit high to enable timer2 equal period event generate
+ */
+#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
+#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
+#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEP_EN_S  8
+/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
+ *  set this bit high to enable PWM generator0 timer equal a event generate
+ */
+#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
+#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
+#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEA_EN_S  9
+/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
+ *  set this bit high to enable PWM generator1 timer equal a event generate
+ */
+#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
+#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
+#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEA_EN_S  10
+/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
+ *  set this bit high to enable PWM generator2 timer equal a event generate
+ */
+#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
+#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
+#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEA_EN_S  11
+/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
+ *  set this bit high to enable PWM generator0 timer equal b event generate
+ */
+#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
+#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
+#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEB_EN_S  12
+/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
+ *  set this bit high to enable PWM generator1 timer equal b event generate
+ */
+#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
+#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
+#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEB_EN_S  13
+/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
+ *  set this bit high to enable PWM generator2 timer equal b event generate
+ */
+#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
+#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
+#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEB_EN_S  14
+/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
+ *  set this bit high to enable fault0 event generate
+ */
+#define MCPWM_EVT_F0_EN    (BIT(15))
+#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
+#define MCPWM_EVT_F0_EN_V  0x00000001U
+#define MCPWM_EVT_F0_EN_S  15
+/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
+ *  set this bit high to enable fault1 event generate
+ */
+#define MCPWM_EVT_F1_EN    (BIT(16))
+#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
+#define MCPWM_EVT_F1_EN_V  0x00000001U
+#define MCPWM_EVT_F1_EN_S  16
+/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
+ *  set this bit high to enable fault2 event generate
+ */
+#define MCPWM_EVT_F2_EN    (BIT(17))
+#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
+#define MCPWM_EVT_F2_EN_V  0x00000001U
+#define MCPWM_EVT_F2_EN_S  17
+/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
+ *  set this bit high to enable fault0 clear event generate
+ */
+#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
+#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
+#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F0_CLR_EN_S  18
+/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  set this bit high to enable fault1 clear event generate
+ */
+#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
+#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
+#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F1_CLR_EN_S  19
+/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  set this bit high to enable fault2 clear event generate
+ */
+#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
+#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
+#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F2_CLR_EN_S  20
+/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
+ *  set this bit high to enable cycle by cycle trip0 event generate
+ */
+#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
+#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
+#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_CBC_EN_S  21
+/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
+ *  set this bit high to enable cycle by cycle trip1 event generate
+ */
+#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
+#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
+#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_CBC_EN_S  22
+/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
+ *  set this bit high to enable cycle by cycle trip2 event generate
+ */
+#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
+#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
+#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_CBC_EN_S  23
+/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
+ *  set this bit high to enable one shot trip0 event generate
+ */
+#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
+#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
+#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_OST_EN_S  24
+/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
+ *  set this bit high to enable one shot trip1 event generate
+ */
+#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
+#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
+#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_OST_EN_S  25
+/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
+ *  set this bit high to enable one shot trip2 event generate
+ */
+#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
+#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
+#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_OST_EN_S  26
+/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
+ *  set this bit high to enable capture0 event generate
+ */
+#define MCPWM_EVT_CAP0_EN    (BIT(27))
+#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
+#define MCPWM_EVT_CAP0_EN_V  0x00000001U
+#define MCPWM_EVT_CAP0_EN_S  27
+/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
+ *  set this bit high to enable capture1 event generate
+ */
+#define MCPWM_EVT_CAP1_EN    (BIT(28))
+#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
+#define MCPWM_EVT_CAP1_EN_V  0x00000001U
+#define MCPWM_EVT_CAP1_EN_S  28
+/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
+ *  set this bit high to enable capture2 event generate
+ */
+#define MCPWM_EVT_CAP2_EN    (BIT(29))
+#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
+#define MCPWM_EVT_CAP2_EN_V  0x00000001U
+#define MCPWM_EVT_CAP2_EN_S  29
+
+/** MCPWM_TASK_EN_REG register
+ *  MCPWM task enable register
+ */
+#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124)
+/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit high to enable PWM generator0 timer stamp A's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
+#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
+#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
+/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
+ *  set this bit high to enable PWM generator1 timer stamp A's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
+#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
+#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
+/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
+ *  set this bit high to enable PWM generator2 timer stamp A's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
+#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
+#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
+/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
+ *  set this bit high to enable PWM generator0 timer stamp B's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
+#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
+#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
+/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
+ *  set this bit high to enable PWM generator1 timer stamp B's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
+#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
+#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
+/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
+ *  set this bit high to enable PWM generator2 timer stamp B's shadow register update
+ *  task receive
+ */
+#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
+#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
+#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
+/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
+ *  set this bit high to enable all PWM generate stop task receive
+ */
+#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
+#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
+#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
+#define MCPWM_TASK_GEN_STOP_EN_S  6
+/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
+ *  set this bit high to enable timer0 sync task receive
+ */
+#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
+#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
+#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
+/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
+ *  set this bit high to enable timer1 sync task receive
+ */
+#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
+#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
+#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
+/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
+ *  set this bit high to enable timer2 sync task receive
+ */
+#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
+#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
+#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
+/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
+ *  set this bit high to enable timer0 period update task receive
+ */
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
+/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
+ *  set this bit high to enable timer1 period update task receive
+ */
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
+/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
+ *  set this bit high to enable timer2 period update task receive
+ */
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
+/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
+ *  set this bit high to enable one shot trip0 task receive
+ */
+#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
+#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
+#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ0_OST_EN_S  13
+/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
+ *  set this bit high to enable one shot trip1 task receive
+ */
+#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
+#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
+#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ1_OST_EN_S  14
+/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
+ *  set this bit high to enable one shot trip2 task receive
+ */
+#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
+#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
+#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ2_OST_EN_S  15
+/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
+ *  set this bit high to enable one shot trip0 clear task receive
+ */
+#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
+#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
+#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR0_OST_EN_S  16
+/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
+ *  set this bit high to enable one shot trip1 clear task receive
+ */
+#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
+#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
+#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR1_OST_EN_S  17
+/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
+ *  set this bit high to enable one shot trip2 clear task receive
+ */
+#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
+#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
+#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR2_OST_EN_S  18
+/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
+ *  set this bit high to enable capture0 task receive
+ */
+#define MCPWM_TASK_CAP0_EN    (BIT(19))
+#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
+#define MCPWM_TASK_CAP0_EN_V  0x00000001U
+#define MCPWM_TASK_CAP0_EN_S  19
+/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
+ *  set this bit high to enable capture1 task receive
+ */
+#define MCPWM_TASK_CAP1_EN    (BIT(20))
+#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
+#define MCPWM_TASK_CAP1_EN_V  0x00000001U
+#define MCPWM_TASK_CAP1_EN_S  20
+/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
+ *  set this bit high to enable capture2 task receive
+ */
+#define MCPWM_TASK_CAP2_EN    (BIT(21))
+#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
+#define MCPWM_TASK_CAP2_EN_V  0x00000001U
+#define MCPWM_TASK_CAP2_EN_S  21
+
+/** MCPWM_CLK_REG register
+ *  MCPWM APB configuration register
+ */
+#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x128)
+/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Force clock on for this register file
+ */
+#define MCPWM_CLK_EN    (BIT(0))
+#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
+#define MCPWM_CLK_EN_V  0x00000001U
+#define MCPWM_CLK_EN_S  0
+
+/** MCPWM_VERSION_REG register
+ *  Version register.
+ */
+#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x12c)
+/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35656256;
+ *  Version of this register file
+ */
+#define MCPWM_DATE    0x0FFFFFFFU
+#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
+#define MCPWM_DATE_V  0x0FFFFFFFU
+#define MCPWM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/mcpwm_struct.h b/components/soc/esp32h2/register/soc/mcpwm_struct.h
new file mode 100644
index 00000000000..5fe75f3c99e
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/mcpwm_struct.h
@@ -0,0 +1,1694 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Prescaler configuration */
+/** Type of clk_cfg register
+ *  PWM clock prescaler register.
+ */
+typedef union {
+    struct {
+        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
+         */
+        uint32_t clk_prescale:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_clk_cfg_reg_t;
+
+
+/** Group: MCPWM Timer Configuration and status */
+/** Type of timer_cfg0 register
+ *  PWM timer period and update method configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1)
+         */
+        uint32_t timer_prescale:8;
+        /** timer_period : R/W; bitpos: [23:8]; default: 255;
+         *  period shadow register of PWM timer
+         */
+        uint32_t timer_period:16;
+        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
+         *  Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2:
+         *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+         */
+        uint32_t timer_period_upmethod:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg0_reg_t;
+
+/** Type of timer_cfg1 register
+ *  PWM timer0 working mode and start/stop control configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1:
+         *  if timer0 starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer
+         *  starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP
+         *  here and below means the event that happens when the timer equals to period
+         */
+        uint32_t timer_start:3;
+        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
+         *  PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+         *  mode
+         */
+        uint32_t timer_mod:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg1_reg_t;
+
+/** Type of timer_sync register
+ *  PWM timer sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
+         *  When set, timer reloading with phase on sync input event is enabled.
+         */
+        uint32_t timer_synci_en:1;
+        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Toggling this bit will trigger a software sync.
+         */
+        uint32_t timer_sync_sw:1;
+        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+         *  generate when toggling the reg_timer0_sync_sw bit
+         */
+        uint32_t timer_synco_sel:2;
+        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
+         *  phase for timer reload on sync event
+         */
+        uint32_t timer_phase:16;
+        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configure the PWM timer0's direction when timer mode is up-down mode:
+         *  0-increase,1-decrease
+         */
+        uint32_t timer_phase_direction:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} mcpwm_timer_sync_reg_t;
+
+/** Type of timer_status register
+ *  PWM timer status register.
+ */
+typedef union {
+    struct {
+        /** timer_value : RO; bitpos: [15:0]; default: 0;
+         *  current PWM timer counter value
+         */
+        uint32_t timer_value:16;
+        /** timer_direction : RO; bitpos: [16]; default: 0;
+         *  current PWM timer counter direction, 0: increment 1: decrement
+         */
+        uint32_t timer_direction:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} mcpwm_timer_status_reg_t;
+
+
+/** Group: Common configuration for MCPWM timers */
+/** Type of timer_synci_cfg register
+ *  Synchronization input selection for three PWM timers.
+ */
+typedef union {
+    struct {
+        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
+         *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer0_syncisel:3;
+        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
+         *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer1_syncisel:3;
+        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
+         *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer2_syncisel:3;
+        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
+         *  invert SYNC0 from GPIO matrix
+         */
+        uint32_t external_synci0_invert:1;
+        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
+         *  invert SYNC1 from GPIO matrix
+         */
+        uint32_t external_synci1_invert:1;
+        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
+         *  invert SYNC2 from GPIO matrix
+         */
+        uint32_t external_synci2_invert:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} mcpwm_timer_synci_cfg_reg_t;
+
+/** Type of operator_timersel register
+ *  Select specific timer for PWM operators.
+ */
+typedef union {
+    struct {
+        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
+         *  Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator0_timersel:2;
+        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
+         *  Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator1_timersel:2;
+        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
+         *  Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator2_timersel:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_operator_timersel_reg_t;
+
+
+/** Group: MCPWM Operator Configuration and Status */
+/** Type of gen_stmp_cfg register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+typedef union {
+    struct {
+        /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for PWM generator time stamp A's active register. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+         */
+        uint32_t cmpr_a_upmethod:4;
+        /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Update method for PWM generator time stamp B's active register. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+         */
+        uint32_t cmpr_b_upmethod:4;
+        /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
+         *  Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is
+         *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+         *  has been updated with shadow register latest value
+         */
+        uint32_t cmpr_a_shdw_full:1;
+        /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
+         *  Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is
+         *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+         *  has been updated with shadow register latest value
+         */
+        uint32_t cmpr_b_shdw_full:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_stmp_cfg_reg_t;
+
+/** Type of gen_tstmp register
+ *  Shadow register for register B.
+ */
+typedef union {
+    struct {
+        /** cmpr : R/W; bitpos: [15:0]; default: 0;
+         *  PWM generator time stamp's shadow register
+         */
+        uint32_t cmpr:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_tstmp_reg_t;
+
+/** Type of gen_cfg0 register
+ *  Fault event T0 and T1 handling
+ */
+typedef union {
+    struct {
+        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for PWM generator's active register of configuration. When all bits
+         *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+         *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
+         */
+        uint32_t gen_cfg_upmethod:4;
+        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
+         *  Source selection for PWM generator event_t0, take effect immediately, 0:
+         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+         */
+        uint32_t gen_t0_sel:3;
+        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
+         *  Source selection for PWM generator event_t1, take effect immediately, 0:
+         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+         */
+        uint32_t gen_t1_sel:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_cfg0_reg_t;
+
+/** Type of gen_force register
+ *  Permissives to force PWM0A and PWM0B outputs by software
+ */
+typedef union {
+    struct {
+        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
+         *  Updating method for continuous software force of PWM generator. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
+         *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+         *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+         *  generated when the timer's value equals to that of register A/B.)
+         */
+        uint32_t gen_cntuforce_upmethod:6;
+        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
+         *  Continuous software force mode for PWMnA. 0: disabled, 1: low, 2: high, 3: disabled
+         */
+        uint32_t gen_a_cntuforce_mode:2;
+        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
+         *  Continuous software force mode for PWMnB. 0: disabled, 1: low, 2: high, 3: disabled
+         */
+        uint32_t gen_b_cntuforce_mode:2;
+        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
+         *  Trigger of non-continuous immediate software-force event for PWMnA, a toggle will
+         *  trigger a force event.
+         */
+        uint32_t gen_a_nciforce:1;
+        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
+         *  non-continuous immediate software force mode for PWMnA, 0: disabled, 1: low, 2:
+         *  high, 3: disabled
+         */
+        uint32_t gen_a_nciforce_mode:2;
+        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
+         *  Trigger of non-continuous immediate software-force event for PWMnB, a toggle will
+         *  trigger a force event.
+         */
+        uint32_t gen_b_nciforce:1;
+        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
+         *  non-continuous immediate software force mode for PWMnB, 0: disabled, 1: low, 2:
+         *  high, 3: disabled
+         */
+        uint32_t gen_b_nciforce_mode:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_force_reg_t;
+
+/** Type of gen register
+ *  Actions triggered by events on PWM0B
+ */
+typedef union {
+    struct {
+        /** gen_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Action on PWMnA/B triggered by event TEZ when timer increasing
+         */
+        uint32_t gen_utez:2;
+        /** gen_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Action on PWMnA/B triggered by event TEP when timer increasing
+         */
+        uint32_t gen_utep:2;
+        /** gen_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Action on PWMnA/B triggered by event TEA when timer increasing
+         */
+        uint32_t gen_utea:2;
+        /** gen_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Action on PWMnA/B triggered by event TEB when timer increasing
+         */
+        uint32_t gen_uteb:2;
+        /** gen_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Action on PWMnA/B triggered by event_t0 when timer increasing
+         */
+        uint32_t gen_ut0:2;
+        /** gen_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Action on PWMnA/B triggered by event_t1 when timer increasing
+         */
+        uint32_t gen_ut1:2;
+        /** gen_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Action on PWMnA/B triggered by event TEZ when timer decreasing
+         */
+        uint32_t gen_dtez:2;
+        /** gen_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Action on PWMnA/B triggered by event TEP when timer decreasing
+         */
+        uint32_t gen_dtep:2;
+        /** gen_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Action on PWMnA/B triggered by event TEA when timer decreasing
+         */
+        uint32_t gen_dtea:2;
+        /** gen_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Action on PWMnA/B triggered by event TEB when timer decreasing
+         */
+        uint32_t gen_dteb:2;
+        /** gen_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Action on PWMnA/B triggered by event_t0 when timer decreasing
+         */
+        uint32_t gen_dt0:2;
+        /** gen_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Action on PWMnA/B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_dt1:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_gen_reg_t;
+
+/** Type of dt_cfg register
+ *  dead time type selection and configuration
+ */
+typedef union {
+    struct {
+        /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
+         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+         *  bit3 is set to 1: disable the update
+         */
+        uint32_t db_fed_upmethod:4;
+        /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
+         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+         *  bit3 is set to 1: disable the update
+         */
+        uint32_t db_red_upmethod:4;
+        /** db_deb_mode : R/W; bitpos: [8]; default: 0;
+         *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+         *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+         */
+        uint32_t db_deb_mode:1;
+        /** db_a_outswap : R/W; bitpos: [9]; default: 0;
+         *  S6 in table
+         */
+        uint32_t db_a_outswap:1;
+        /** db_b_outswap : R/W; bitpos: [10]; default: 0;
+         *  S7 in table
+         */
+        uint32_t db_b_outswap:1;
+        /** db_red_insel : R/W; bitpos: [11]; default: 0;
+         *  S4 in table
+         */
+        uint32_t db_red_insel:1;
+        /** db_fed_insel : R/W; bitpos: [12]; default: 0;
+         *  S5 in table
+         */
+        uint32_t db_fed_insel:1;
+        /** db_red_outinvert : R/W; bitpos: [13]; default: 0;
+         *  S2 in table
+         */
+        uint32_t db_red_outinvert:1;
+        /** db_fed_outinvert : R/W; bitpos: [14]; default: 0;
+         *  S3 in table
+         */
+        uint32_t db_fed_outinvert:1;
+        /** db_a_outbypass : R/W; bitpos: [15]; default: 1;
+         *  S1 in table
+         */
+        uint32_t db_a_outbypass:1;
+        /** db_b_outbypass : R/W; bitpos: [16]; default: 1;
+         *  S0 in table
+         */
+        uint32_t db_b_outbypass:1;
+        /** db_clk_sel : R/W; bitpos: [17]; default: 0;
+         *  Dead time generator n clock selection. 0: PWM_clk, 1: PT_clk
+         */
+        uint32_t db_clk_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} mcpwm_dt_cfg_reg_t;
+
+/** Type of dt_fed_cfg register
+ *  Shadow register for falling edge delay (FED).
+ */
+typedef union {
+    struct {
+        /** db_fed : R/W; bitpos: [15:0]; default: 0;
+         *  Shadow register for FED
+         */
+        uint32_t db_fed:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_fed_cfg_reg_t;
+
+/** Type of dt_red_cfg register
+ *  Shadow register for rising edge delay (RED).
+ */
+typedef union {
+    struct {
+        /** db_red : R/W; bitpos: [15:0]; default: 0;
+         *  Shadow register for RED
+         */
+        uint32_t db_red:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_red_cfg_reg_t;
+
+/** Type of carrier_cfg register
+ *  Carrier enable and configuration
+ */
+typedef union {
+    struct {
+        /** chopper_en : R/W; bitpos: [0]; default: 0;
+         *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
+         */
+        uint32_t chopper_en:1;
+        /** chopper_prescale : R/W; bitpos: [4:1]; default: 0;
+         *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+         *  (PWM_CARRIER0_PRESCALE + 1)
+         */
+        uint32_t chopper_prescale:4;
+        /** chopper_duty : R/W; bitpos: [7:5]; default: 0;
+         *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+         */
+        uint32_t chopper_duty:3;
+        /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0;
+         *  width of the first pulse in number of periods of the carrier
+         */
+        uint32_t chopper_oshtwth:4;
+        /** chopper_out_invert : R/W; bitpos: [12]; default: 0;
+         *  when set, invert the output of PWM0A and PWM0B for this submodule
+         */
+        uint32_t chopper_out_invert:1;
+        /** chopper_in_invert : R/W; bitpos: [13]; default: 0;
+         *  when set, invert the input of PWM0A and PWM0B for this submodule
+         */
+        uint32_t chopper_in_invert:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} mcpwm_carrier_cfg_reg_t;
+
+/** Type of fh_cfg0 register
+ *  Actions on PWM0A and PWM0B trip events
+ */
+typedef union {
+    struct {
+        /** tz_sw_cbc : R/W; bitpos: [0]; default: 0;
+         *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_sw_cbc:1;
+        /** tz_f2_cbc : R/W; bitpos: [1]; default: 0;
+         *  event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f2_cbc:1;
+        /** tz_f1_cbc : R/W; bitpos: [2]; default: 0;
+         *  event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f1_cbc:1;
+        /** tz_f0_cbc : R/W; bitpos: [3]; default: 0;
+         *  event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f0_cbc:1;
+        /** tz_sw_ost : R/W; bitpos: [4]; default: 0;
+         *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_sw_ost:1;
+        /** tz_f2_ost : R/W; bitpos: [5]; default: 0;
+         *  event_f2 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f2_ost:1;
+        /** tz_f1_ost : R/W; bitpos: [6]; default: 0;
+         *  event_f1 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f1_ost:1;
+        /** tz_f0_ost : R/W; bitpos: [7]; default: 0;
+         *  event_f0 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t tz_f0_ost:1;
+        /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_a_cbc_d:2;
+        /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+         *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_a_cbc_u:2;
+        /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0;
+         *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_a_ost_d:2;
+        /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0;
+         *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_a_ost_u:2;
+        /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_b_cbc_d:2;
+        /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+         *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_b_cbc_u:2;
+        /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0;
+         *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_b_ost_d:2;
+        /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0;
+         *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t tz_b_ost_u:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg0_reg_t;
+
+/** Type of fh_cfg1 register
+ *  Software triggers for fault handler actions
+ */
+typedef union {
+    struct {
+        /** tz_clr_ost : R/W; bitpos: [0]; default: 0;
+         *  a rising edge will clear on going one-shot mode action
+         */
+        uint32_t tz_clr_ost:1;
+        /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0;
+         *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+         *  when bit1 is set to 1:TEP
+         */
+        uint32_t tz_cbcpulse:2;
+        /** tz_force_cbc : R/W; bitpos: [3]; default: 0;
+         *  a toggle trigger a cycle-by-cycle mode action
+         */
+        uint32_t tz_force_cbc:1;
+        /** tz_force_ost : R/W; bitpos: [4]; default: 0;
+         *  a toggle (software negate its value) triggers a one-shot mode action
+         */
+        uint32_t tz_force_ost:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg1_reg_t;
+
+/** Type of fh_status register
+ *  Status of fault events.
+ */
+typedef union {
+    struct {
+        /** tz_cbc_on : RO; bitpos: [0]; default: 0;
+         *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+         */
+        uint32_t tz_cbc_on:1;
+        /** tz_ost_on : RO; bitpos: [1]; default: 0;
+         *  Set and reset by hardware. If set, an one-shot mode action is on going
+         */
+        uint32_t tz_ost_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mcpwm_fh_status_reg_t;
+
+
+/** Group: Fault Detection Configuration and Status */
+/** Type of fault_detect register
+ *  Fault detection configuration and status
+ */
+typedef union {
+    struct {
+        /** f0_en : R/W; bitpos: [0]; default: 0;
+         *  When set, event_f0 generation is enabled
+         */
+        uint32_t f0_en:1;
+        /** f1_en : R/W; bitpos: [1]; default: 0;
+         *  When set, event_f1 generation is enabled
+         */
+        uint32_t f1_en:1;
+        /** f2_en : R/W; bitpos: [2]; default: 0;
+         *  When set, event_f2 generation is enabled
+         */
+        uint32_t f2_en:1;
+        /** f0_pole : R/W; bitpos: [3]; default: 0;
+         *  Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+         *  level high
+         */
+        uint32_t f0_pole:1;
+        /** f1_pole : R/W; bitpos: [4]; default: 0;
+         *  Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+         *  level high
+         */
+        uint32_t f1_pole:1;
+        /** f2_pole : R/W; bitpos: [5]; default: 0;
+         *  Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
+         *  level high
+         */
+        uint32_t f2_pole:1;
+        /** event_f0 : RO; bitpos: [6]; default: 0;
+         *  Set and reset by hardware. If set, event_f0 is on going
+         */
+        uint32_t event_f0:1;
+        /** event_f1 : RO; bitpos: [7]; default: 0;
+         *  Set and reset by hardware. If set, event_f1 is on going
+         */
+        uint32_t event_f1:1;
+        /** event_f2 : RO; bitpos: [8]; default: 0;
+         *  Set and reset by hardware. If set, event_f2 is on going
+         */
+        uint32_t event_f2:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} mcpwm_fault_detect_reg_t;
+
+
+/** Group: Capture Configuration and Status */
+/** Type of cap_timer_cfg register
+ *  Configure capture timer
+ */
+typedef union {
+    struct {
+        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
+         *  When set, capture timer incrementing under APB_clk is enabled.
+         */
+        uint32_t cap_timer_en:1;
+        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
+         *  When set, capture timer sync is enabled.
+         */
+        uint32_t cap_synci_en:1;
+        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
+         *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
+         *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
+         *  6: SYNC2 from GPIO matrix
+         */
+        uint32_t cap_synci_sel:3;
+        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
+         *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
+         *  timer is loaded with value in phase register.
+         */
+        uint32_t cap_sync_sw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_cfg_reg_t;
+
+/** Type of cap_timer_phase register
+ *  Phase for capture timer sync
+ */
+typedef union {
+    struct {
+        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
+         *  Phase value for capture timer sync operation.
+         */
+        uint32_t cap_phase:32;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_phase_reg_t;
+
+/** Type of cap_chn_cfg register
+ *  Capture channel n configuration and enable
+ */
+typedef union {
+    struct {
+        /** capn_en : R/W; bitpos: [0]; default: 0;
+         *  When set, capture on channel 0 is enabled
+         */
+        uint32_t capn_en:1;
+        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
+         *  Edge of capture on channel n after prescaling. When bit0 is set to 1: enable
+         *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+         *  edge.
+         */
+        uint32_t capn_mode:2;
+        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
+         *  Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAP0_PRESCALE +
+         *  1
+         */
+        uint32_t capn_prescale:8;
+        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
+         *  when set, CAPn form GPIO matrix is inverted before prescale
+         */
+        uint32_t capn_in_invert:1;
+        /** capn_sw : WT; bitpos: [12]; default: 0;
+         *  Write 1 will trigger a software forced capture on channel n
+         */
+        uint32_t capn_sw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_cfg_reg_t;
+
+/** Type of cap_chn register
+ *  chn capture value status register
+ */
+typedef union {
+    struct {
+        /** capn_value : RO; bitpos: [31:0]; default: 0;
+         *  Value of last capture on channel n
+         */
+        uint32_t capn_value:32;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_reg_t;
+
+/** Type of cap_status register
+ *  Edge of last capture trigger
+ */
+typedef union {
+    struct {
+        /** cap0_edge : RO; bitpos: [0]; default: 0;
+         *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
+         */
+        uint32_t cap0_edge:1;
+        /** cap1_edge : RO; bitpos: [1]; default: 0;
+         *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
+         */
+        uint32_t cap1_edge:1;
+        /** cap2_edge : RO; bitpos: [2]; default: 0;
+         *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
+         */
+        uint32_t cap2_edge:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} mcpwm_cap_status_reg_t;
+
+
+/** Group: Enable update of active registers */
+/** Type of update_cfg register
+ *  Enable update.
+ */
+typedef union {
+    struct {
+        /** global_up_en : R/W; bitpos: [0]; default: 1;
+         *  The global enable of update of all active registers in MCPWM module
+         */
+        uint32_t global_up_en:1;
+        /** global_force_up : R/W; bitpos: [1]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of all active
+         *  registers in MCPWM module
+         */
+        uint32_t global_force_up:1;
+        /** op0_up_en : R/W; bitpos: [2]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
+         *  are enabled
+         */
+        uint32_t op0_up_en:1;
+        /** op0_force_up : R/W; bitpos: [3]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 0
+         */
+        uint32_t op0_force_up:1;
+        /** op1_up_en : R/W; bitpos: [4]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
+         *  are enabled
+         */
+        uint32_t op1_up_en:1;
+        /** op1_force_up : R/W; bitpos: [5]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 1
+         */
+        uint32_t op1_force_up:1;
+        /** op2_up_en : R/W; bitpos: [6]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
+         *  are enabled
+         */
+        uint32_t op2_up_en:1;
+        /** op2_force_up : R/W; bitpos: [7]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 2
+         */
+        uint32_t op2_force_up:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_update_cfg_reg_t;
+
+
+/** Group: Manage Interrupts */
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_ena:1;
+        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_ena:1;
+        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_ena:1;
+        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_ena:1;
+        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_ena:1;
+        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_ena:1;
+        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_ena:1;
+        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_ena:1;
+        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_ena:1;
+        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_ena:1;
+        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_ena:1;
+        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_ena:1;
+        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f0 ends.
+         */
+        uint32_t fault0_clr_int_ena:1;
+        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f1 ends.
+         */
+        uint32_t fault1_clr_int_ena:1;
+        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The enable bit for the interrupt triggered when event_f2 ends.
+         */
+        uint32_t fault2_clr_int_ena:1;
+        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_ena:1;
+        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_ena:1;
+        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_ena:1;
+        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_ena:1;
+        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_ena:1;
+        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_ena:1;
+        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_ena:1;
+        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_ena:1;
+        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_ena:1;
+        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_ena:1;
+        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_ena:1;
+        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_ena:1;
+        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_ena:1;
+        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_ena:1;
+        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_ena:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_raw:1;
+        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_raw:1;
+        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_raw:1;
+        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_raw:1;
+        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_raw:1;
+        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_raw:1;
+        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_raw:1;
+        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_raw:1;
+        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_raw:1;
+        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_raw:1;
+        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_raw:1;
+        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_raw:1;
+        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f0 ends.
+         */
+        uint32_t fault0_clr_int_raw:1;
+        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f1 ends.
+         */
+        uint32_t fault1_clr_int_raw:1;
+        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw status bit for the interrupt triggered when event_f2 ends.
+         */
+        uint32_t fault2_clr_int_raw:1;
+        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_raw:1;
+        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_raw:1;
+        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_raw:1;
+        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_raw:1;
+        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_raw:1;
+        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_raw:1;
+        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_cbc_int_raw:1;
+        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_cbc_int_raw:1;
+        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_cbc_int_raw:1;
+        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_raw:1;
+        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_raw:1;
+        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_raw:1;
+        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_raw:1;
+        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_raw:1;
+        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_raw:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_st:1;
+        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_st:1;
+        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_st:1;
+        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_st:1;
+        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_st:1;
+        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_st:1;
+        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_st:1;
+        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_st:1;
+        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_st:1;
+        /** fault0_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_st:1;
+        /** fault1_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_st:1;
+        /** fault2_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_st:1;
+        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f0 ends.
+         */
+        uint32_t fault0_clr_int_st:1;
+        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f1 ends.
+         */
+        uint32_t fault1_clr_int_st:1;
+        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked status bit for the interrupt triggered when event_f2 ends.
+         */
+        uint32_t fault2_clr_int_st:1;
+        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_st:1;
+        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_st:1;
+        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_st:1;
+        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_st:1;
+        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_st:1;
+        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_st:1;
+        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM0.
+         */
+        uint32_t tz0_cbc_int_st:1;
+        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM1.
+         */
+        uint32_t tz1_cbc_int_st:1;
+        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM2.
+         */
+        uint32_t tz2_cbc_int_st:1;
+        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_st:1;
+        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_st:1;
+        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_st:1;
+        /** cap0_int_st : RO; bitpos: [27]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_st:1;
+        /** cap1_int_st : RO; bitpos: [28]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_st:1;
+        /** cap2_int_st : RO; bitpos: [29]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_st:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_clr:1;
+        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_clr:1;
+        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_clr:1;
+        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_clr:1;
+        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_clr:1;
+        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_clr:1;
+        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_clr:1;
+        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_clr:1;
+        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_clr:1;
+        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_clr:1;
+        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_clr:1;
+        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_clr:1;
+        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f0 ends.
+         */
+        uint32_t fault0_clr_int_clr:1;
+        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f1 ends.
+         */
+        uint32_t fault1_clr_int_clr:1;
+        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the interrupt triggered when event_f2 ends.
+         */
+        uint32_t fault2_clr_int_clr:1;
+        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_clr:1;
+        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_clr:1;
+        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_clr:1;
+        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_clr:1;
+        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_clr:1;
+        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_clr:1;
+        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_cbc_int_clr:1;
+        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_cbc_int_clr:1;
+        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_cbc_int_clr:1;
+        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_clr:1;
+        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_clr:1;
+        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_clr:1;
+        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_clr:1;
+        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_clr:1;
+        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_clr:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_clr_reg_t;
+
+
+/** Group: MCPWM event enable register */
+/** Type of evt_en register
+ *  MCPWM event enable register
+ */
+typedef union {
+    struct {
+        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit high to enable timer0 stop event generate
+         */
+        uint32_t evt_timer0_stop_en:1;
+        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
+         *  set this bit high to enable timer1 stop event generate
+         */
+        uint32_t evt_timer1_stop_en:1;
+        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
+         *  set this bit high to enable timer2 stop event generate
+         */
+        uint32_t evt_timer2_stop_en:1;
+        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
+         *  set this bit high to enable timer0 equal zero event generate
+         */
+        uint32_t evt_timer0_tez_en:1;
+        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
+         *  set this bit high to enable timer1 equal zero event generate
+         */
+        uint32_t evt_timer1_tez_en:1;
+        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
+         *  set this bit high to enable timer2 equal zero event generate
+         */
+        uint32_t evt_timer2_tez_en:1;
+        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
+         *  set this bit high to enable timer0 equal period event generate
+         */
+        uint32_t evt_timer0_tep_en:1;
+        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
+         *  set this bit high to enable timer1 equal period event generate
+         */
+        uint32_t evt_timer1_tep_en:1;
+        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
+         *  set this bit high to enable timer2 equal period event generate
+         */
+        uint32_t evt_timer2_tep_en:1;
+        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
+         *  set this bit high to enable PWM generator0 timer equal a event generate
+         */
+        uint32_t evt_op0_tea_en:1;
+        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
+         *  set this bit high to enable PWM generator1 timer equal a event generate
+         */
+        uint32_t evt_op1_tea_en:1;
+        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
+         *  set this bit high to enable PWM generator2 timer equal a event generate
+         */
+        uint32_t evt_op2_tea_en:1;
+        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
+         *  set this bit high to enable PWM generator0 timer equal b event generate
+         */
+        uint32_t evt_op0_teb_en:1;
+        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
+         *  set this bit high to enable PWM generator1 timer equal b event generate
+         */
+        uint32_t evt_op1_teb_en:1;
+        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
+         *  set this bit high to enable PWM generator2 timer equal b event generate
+         */
+        uint32_t evt_op2_teb_en:1;
+        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
+         *  set this bit high to enable fault0 event generate
+         */
+        uint32_t evt_f0_en:1;
+        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
+         *  set this bit high to enable fault1 event generate
+         */
+        uint32_t evt_f1_en:1;
+        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
+         *  set this bit high to enable fault2 event generate
+         */
+        uint32_t evt_f2_en:1;
+        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
+         *  set this bit high to enable fault0 clear event generate
+         */
+        uint32_t evt_f0_clr_en:1;
+        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
+         *  set this bit high to enable fault1 clear event generate
+         */
+        uint32_t evt_f1_clr_en:1;
+        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
+         *  set this bit high to enable fault2 clear event generate
+         */
+        uint32_t evt_f2_clr_en:1;
+        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
+         *  set this bit high to enable cycle by cycle trip0 event generate
+         */
+        uint32_t evt_tz0_cbc_en:1;
+        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
+         *  set this bit high to enable cycle by cycle trip1 event generate
+         */
+        uint32_t evt_tz1_cbc_en:1;
+        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
+         *  set this bit high to enable cycle by cycle trip2 event generate
+         */
+        uint32_t evt_tz2_cbc_en:1;
+        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
+         *  set this bit high to enable one shot trip0 event generate
+         */
+        uint32_t evt_tz0_ost_en:1;
+        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
+         *  set this bit high to enable one shot trip1 event generate
+         */
+        uint32_t evt_tz1_ost_en:1;
+        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
+         *  set this bit high to enable one shot trip2 event generate
+         */
+        uint32_t evt_tz2_ost_en:1;
+        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
+         *  set this bit high to enable capture0 event generate
+         */
+        uint32_t evt_cap0_en:1;
+        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
+         *  set this bit high to enable capture1 event generate
+         */
+        uint32_t evt_cap1_en:1;
+        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
+         *  set this bit high to enable capture2 event generate
+         */
+        uint32_t evt_cap2_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_evt_en_reg_t;
+
+
+/** Group: MCPWM task enable register */
+/** Type of task_en register
+ *  MCPWM task enable register
+ */
+typedef union {
+    struct {
+        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit high to enable PWM generator0 timer stamp A's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr0_a_up_en:1;
+        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
+         *  set this bit high to enable PWM generator1 timer stamp A's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr1_a_up_en:1;
+        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
+         *  set this bit high to enable PWM generator2 timer stamp A's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr2_a_up_en:1;
+        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
+         *  set this bit high to enable PWM generator0 timer stamp B's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr0_b_up_en:1;
+        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
+         *  set this bit high to enable PWM generator1 timer stamp B's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr1_b_up_en:1;
+        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
+         *  set this bit high to enable PWM generator2 timer stamp B's shadow register update
+         *  task receive
+         */
+        uint32_t task_cmpr2_b_up_en:1;
+        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
+         *  set this bit high to enable all PWM generate stop task receive
+         */
+        uint32_t task_gen_stop_en:1;
+        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
+         *  set this bit high to enable timer0 sync task receive
+         */
+        uint32_t task_timer0_sync_en:1;
+        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
+         *  set this bit high to enable timer1 sync task receive
+         */
+        uint32_t task_timer1_sync_en:1;
+        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
+         *  set this bit high to enable timer2 sync task receive
+         */
+        uint32_t task_timer2_sync_en:1;
+        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
+         *  set this bit high to enable timer0 period update task receive
+         */
+        uint32_t task_timer0_period_up_en:1;
+        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
+         *  set this bit high to enable timer1 period update task receive
+         */
+        uint32_t task_timer1_period_up_en:1;
+        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
+         *  set this bit high to enable timer2 period update task receive
+         */
+        uint32_t task_timer2_period_up_en:1;
+        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
+         *  set this bit high to enable one shot trip0 task receive
+         */
+        uint32_t task_tz0_ost_en:1;
+        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
+         *  set this bit high to enable one shot trip1 task receive
+         */
+        uint32_t task_tz1_ost_en:1;
+        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
+         *  set this bit high to enable one shot trip2 task receive
+         */
+        uint32_t task_tz2_ost_en:1;
+        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
+         *  set this bit high to enable one shot trip0 clear task receive
+         */
+        uint32_t task_clr0_ost_en:1;
+        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
+         *  set this bit high to enable one shot trip1 clear task receive
+         */
+        uint32_t task_clr1_ost_en:1;
+        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
+         *  set this bit high to enable one shot trip2 clear task receive
+         */
+        uint32_t task_clr2_ost_en:1;
+        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
+         *  set this bit high to enable capture0 task receive
+         */
+        uint32_t task_cap0_en:1;
+        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
+         *  set this bit high to enable capture1 task receive
+         */
+        uint32_t task_cap1_en:1;
+        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
+         *  set this bit high to enable capture2 task receive
+         */
+        uint32_t task_cap2_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} mcpwm_task_en_reg_t;
+
+
+/** Group: MCPWM APB configuration register */
+/** Type of clk register
+ *  MCPWM APB configuration register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mcpwm_clk_reg_t;
+
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35656256;
+         *  Version of this register file
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mcpwm_version_reg_t;
+
+typedef struct {
+    mcpwm_timer_cfg0_reg_t timer_cfg0;
+    mcpwm_timer_cfg1_reg_t timer_cfg1;
+    mcpwm_timer_sync_reg_t timer_sync;
+    mcpwm_timer_status_reg_t timer_status;
+} mcpwm_timer_regs_t;
+
+typedef struct {
+    mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
+    mcpwm_gen_tstmp_reg_t timestamp[2];
+    mcpwm_gen_cfg0_reg_t gen_cfg0;
+    mcpwm_gen_force_reg_t gen_force;
+    mcpwm_gen_reg_t generator[2];
+    mcpwm_dt_cfg_reg_t dt_cfg;
+    mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
+    mcpwm_dt_red_cfg_reg_t dt_red_cfg;
+    mcpwm_carrier_cfg_reg_t carrier_cfg;
+    mcpwm_fh_cfg0_reg_t fh_cfg0;
+    mcpwm_fh_cfg1_reg_t fh_cfg1;
+    mcpwm_fh_status_reg_t fh_status;
+} mcpwm_operator_reg_t;
+
+typedef struct mcpwm_dev_t {
+    volatile mcpwm_clk_cfg_reg_t clk_cfg;
+    volatile mcpwm_timer_regs_t timer[3];
+    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
+    volatile mcpwm_operator_timersel_reg_t operator_timersel;
+    volatile mcpwm_operator_reg_t operators[3];
+    volatile mcpwm_fault_detect_reg_t fault_detect;
+    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
+    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
+    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
+    volatile mcpwm_cap_chn_reg_t cap_chn[3];
+    volatile mcpwm_cap_status_reg_t cap_status;
+    volatile mcpwm_update_cfg_reg_t update_cfg;
+    volatile mcpwm_int_ena_reg_t int_ena;
+    volatile mcpwm_int_raw_reg_t int_raw;
+    volatile mcpwm_int_st_reg_t int_st;
+    volatile mcpwm_int_clr_reg_t int_clr;
+    volatile mcpwm_evt_en_reg_t evt_en;
+    volatile mcpwm_task_en_reg_t task_en;
+    volatile mcpwm_clk_reg_t clk;
+    volatile mcpwm_version_reg_t version;
+} mcpwm_dev_t;
+
+extern mcpwm_dev_t MCPWM0;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mcpwm_dev_t) == 0x130, "Invalid size of mcpwm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/mem_monitor_reg.h b/components/soc/esp32h2/register/soc/mem_monitor_reg.h
new file mode 100644
index 00000000000..1a90e585be1
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/mem_monitor_reg.h
@@ -0,0 +1,184 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MEM_MONITOR_LOG_SETTING_REG register
+ *  log config register
+ */
+#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
+/** MEM_MONITOR_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
+ *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu
+ */
+#define MEM_MONITOR_LOG_ENA    0x00000007U
+#define MEM_MONITOR_LOG_ENA_M  (MEM_MONITOR_LOG_ENA_V << MEM_MONITOR_LOG_ENA_S)
+#define MEM_MONITOR_LOG_ENA_V  0x00000007U
+#define MEM_MONITOR_LOG_ENA_S  0
+/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
+ *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
+ *  HALFWORD monitor, 4'b1000: BYTE monitor.
+ */
+#define MEM_MONITOR_LOG_MODE    0x0000000FU
+#define MEM_MONITOR_LOG_MODE_M  (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
+#define MEM_MONITOR_LOG_MODE_V  0x0000000FU
+#define MEM_MONITOR_LOG_MODE_S  3
+/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
+ *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
+ */
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE    (BIT(7))
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M  (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S  7
+
+/** MEM_MONITOR_LOG_CHECK_DATA_REG register
+ *  check data register
+ */
+#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
+/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The special check data, when write this special data, it will trigger logging.
+ */
+#define MEM_MONITOR_LOG_CHECK_DATA    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_CHECK_DATA_M  (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
+#define MEM_MONITOR_LOG_CHECK_DATA_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_CHECK_DATA_S  0
+
+/** MEM_MONITOR_LOG_DATA_MASK_REG register
+ *  check data mask register
+ */
+#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
+/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
+ *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
+ *  mask second byte, and so on.
+ */
+#define MEM_MONITOR_LOG_DATA_MASK    0x0000000FU
+#define MEM_MONITOR_LOG_DATA_MASK_M  (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
+#define MEM_MONITOR_LOG_DATA_MASK_V  0x0000000FU
+#define MEM_MONITOR_LOG_DATA_MASK_S  0
+
+/** MEM_MONITOR_LOG_MIN_REG register
+ *  log boundary register
+ */
+#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
+/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  the min address of log range
+ */
+#define MEM_MONITOR_LOG_MIN    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MIN_M  (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
+#define MEM_MONITOR_LOG_MIN_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MIN_S  0
+
+/** MEM_MONITOR_LOG_MAX_REG register
+ *  log boundary register
+ */
+#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
+/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  the max address of log range
+ */
+#define MEM_MONITOR_LOG_MAX    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MAX_M  (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
+#define MEM_MONITOR_LOG_MAX_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MAX_S  0
+
+/** MEM_MONITOR_LOG_MEM_START_REG register
+ *  log message store range register
+ */
+#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
+/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
+ *  the start address of writing logging message
+ */
+#define MEM_MONITOR_LOG_MEM_START    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_START_M  (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
+#define MEM_MONITOR_LOG_MEM_START_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_START_S  0
+
+/** MEM_MONITOR_LOG_MEM_END_REG register
+ *  log message store range register
+ */
+#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
+/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
+ *  the end address of writing logging message
+ */
+#define MEM_MONITOR_LOG_MEM_END    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_END_M  (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
+#define MEM_MONITOR_LOG_MEM_END_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_END_S  0
+
+/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
+ *  current writing address.
+ */
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
+/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  means next writing address
+ */
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M  (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S  0
+
+/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
+ *  writing address update
+ */
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
+/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
+ *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
+ */
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M  (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S  0
+
+/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
+ *  full flag status register
+ */
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
+/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
+ *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
+ */
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG    (BIT(0))
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S  0
+/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
+ *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
+ */
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M  (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S  1
+
+/** MEM_MONITOR_CLOCK_GATE_REG register
+ *  clock gate force on register
+ */
+#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
+/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to force on the clk of mem_monitor register
+ */
+#define MEM_MONITOR_CLK_EN    (BIT(0))
+#define MEM_MONITOR_CLK_EN_M  (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
+#define MEM_MONITOR_CLK_EN_V  0x00000001U
+#define MEM_MONITOR_CLK_EN_S  0
+
+/** MEM_MONITOR_DATE_REG register
+ *  version register
+ */
+#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
+/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 35660096;
+ *  version register
+ */
+#define MEM_MONITOR_DATE    0x0FFFFFFFU
+#define MEM_MONITOR_DATE_M  (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
+#define MEM_MONITOR_DATE_V  0x0FFFFFFFU
+#define MEM_MONITOR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/mem_monitor_struct.h b/components/soc/esp32h2/register/soc/mem_monitor_struct.h
new file mode 100644
index 00000000000..ef63ca9c264
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/mem_monitor_struct.h
@@ -0,0 +1,220 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration registers */
+/** Type of log_setting register
+ *  log config register
+ */
+typedef union {
+    struct {
+        /** log_ena : R/W; bitpos: [2:0]; default: 0;
+         *  enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu
+         */
+        uint32_t log_ena:3;
+        /** log_mode : R/W; bitpos: [6:3]; default: 0;
+         *  This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100:
+         *  HALFWORD monitor, 4'b1000: BYTE monitor.
+         */
+        uint32_t log_mode:4;
+        /** log_mem_loop_enable : R/W; bitpos: [7]; default: 1;
+         *  Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END
+         */
+        uint32_t log_mem_loop_enable:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mem_monitor_log_setting_reg_t;
+
+/** Type of log_check_data register
+ *  check data register
+ */
+typedef union {
+    struct {
+        /** log_check_data : R/W; bitpos: [31:0]; default: 0;
+         *  The special check data, when write this special data, it will trigger logging.
+         */
+        uint32_t log_check_data:32;
+    };
+    uint32_t val;
+} mem_monitor_log_check_data_reg_t;
+
+/** Type of log_data_mask register
+ *  check data mask register
+ */
+typedef union {
+    struct {
+        /** log_data_mask : R/W; bitpos: [3:0]; default: 0;
+         *  byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1
+         *  mask second byte, and so on.
+         */
+        uint32_t log_data_mask:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} mem_monitor_log_data_mask_reg_t;
+
+/** Type of log_min register
+ *  log boundary register
+ */
+typedef union {
+    struct {
+        /** log_min : R/W; bitpos: [31:0]; default: 0;
+         *  the min address of log range
+         */
+        uint32_t log_min:32;
+    };
+    uint32_t val;
+} mem_monitor_log_min_reg_t;
+
+/** Type of log_max register
+ *  log boundary register
+ */
+typedef union {
+    struct {
+        /** log_max : R/W; bitpos: [31:0]; default: 0;
+         *  the max address of log range
+         */
+        uint32_t log_max:32;
+    };
+    uint32_t val;
+} mem_monitor_log_max_reg_t;
+
+/** Type of log_mem_start register
+ *  log message store range register
+ */
+typedef union {
+    struct {
+        /** log_mem_start : R/W; bitpos: [31:0]; default: 0;
+         *  the start address of writing logging message
+         */
+        uint32_t log_mem_start:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_start_reg_t;
+
+/** Type of log_mem_end register
+ *  log message store range register
+ */
+typedef union {
+    struct {
+        /** log_mem_end : R/W; bitpos: [31:0]; default: 0;
+         *  the end address of writing logging message
+         */
+        uint32_t log_mem_end:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_end_reg_t;
+
+/** Type of log_mem_current_addr register
+ *  current writing address.
+ */
+typedef union {
+    struct {
+        /** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  means next writing address
+         */
+        uint32_t log_mem_current_addr:32;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_current_addr_reg_t;
+
+/** Type of log_mem_addr_update register
+ *  writing address update
+ */
+typedef union {
+    struct {
+        /** log_mem_addr_update : WT; bitpos: [0]; default: 0;
+         *  Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1,
+         *  MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START
+         */
+        uint32_t log_mem_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_addr_update_reg_t;
+
+/** Type of log_mem_full_flag register
+ *  full flag status register
+ */
+typedef union {
+    struct {
+        /** log_mem_full_flag : RO; bitpos: [0]; default: 0;
+         *  1 means memory write loop at least one time at the range of MEM_START and MEM_END
+         */
+        uint32_t log_mem_full_flag:1;
+        /** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
+         *  Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG
+         */
+        uint32_t clr_log_mem_full_flag:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mem_monitor_log_mem_full_flag_reg_t;
+
+
+/** Group: clk register */
+/** Type of clock_gate register
+ *  clock gate force on register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to force on the clk of mem_monitor register
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mem_monitor_clock_gate_reg_t;
+
+
+/** Group: version register */
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35660096;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mem_monitor_date_reg_t;
+
+
+typedef struct {
+    volatile mem_monitor_log_setting_reg_t log_setting;
+    volatile mem_monitor_log_check_data_reg_t log_check_data;
+    volatile mem_monitor_log_data_mask_reg_t log_data_mask;
+    volatile mem_monitor_log_min_reg_t log_min;
+    volatile mem_monitor_log_max_reg_t log_max;
+    volatile mem_monitor_log_mem_start_reg_t log_mem_start;
+    volatile mem_monitor_log_mem_end_reg_t log_mem_end;
+    volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
+    volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
+    volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
+    volatile mem_monitor_clock_gate_reg_t clock_gate;
+    uint32_t reserved_02c[244];
+    volatile mem_monitor_date_reg_t date;
+} mem_monitor_dev_t;
+
+extern mem_monitor_dev_t MEM_MONITOR;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/parl_io_reg.h b/components/soc/esp32h2/register/soc/parl_io_reg.h
new file mode 100644
index 00000000000..d68f5191cb2
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/parl_io_reg.h
@@ -0,0 +1,472 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PARL_IO_RX_MODE_CFG_REG register
+ *  Parallel RX Sampling mode configuration register.
+ */
+#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
+/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
+ *  Configures rx external enable signal selection from IO PAD.
+ */
+#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
+#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_S  21
+/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to enable data sampling by software.
+ */
+#define PARL_IO_RX_SW_EN    (BIT(25))
+#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
+#define PARL_IO_RX_SW_EN_V  0x00000001U
+#define PARL_IO_RX_SW_EN_S  25
+/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to invert the external enable signal.
+ */
+#define PARL_IO_RX_EXT_EN_INV    (BIT(26))
+#define PARL_IO_RX_EXT_EN_INV_M  (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
+#define PARL_IO_RX_EXT_EN_INV_V  0x00000001U
+#define PARL_IO_RX_EXT_EN_INV_S  26
+/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
+ *  Configures the rxd pulse sampling submode.
+ *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
+ *  included)
+ *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
+ *  excluded)
+ *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
+ *  included)
+ *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
+ *  excluded)
+ *  4'd4: positive pulse start(data bit included) && length end
+ *  4'd5: positive pulse start(data bit excluded) && length end
+ */
+#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x00000007U
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x00000007U
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  27
+/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  Configures the rxd sampling mode.
+ *  2'b00: external level enable mode
+ *  2'b01: external pulse enable mode
+ *  2'b10: internal software enable mode
+ */
+#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
+#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_S  30
+
+/** PARL_IO_RX_DATA_CFG_REG register
+ *  Parallel RX data configuration register.
+ */
+#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
+/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
+ *  Configures expected byte number of received data.
+ */
+#define PARL_IO_RX_BITLEN    0x0007FFFFU
+#define PARL_IO_RX_BITLEN_M  (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
+#define PARL_IO_RX_BITLEN_V  0x0007FFFFU
+#define PARL_IO_RX_BITLEN_S  9
+/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
+ */
+#define PARL_IO_RX_DATA_ORDER_INV    (BIT(28))
+#define PARL_IO_RX_DATA_ORDER_INV_M  (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
+#define PARL_IO_RX_DATA_ORDER_INV_V  0x00000001U
+#define PARL_IO_RX_DATA_ORDER_INV_S  28
+/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
+ *  Configures the rxd bus width.
+ *  3'd0: bus width is 1.
+ *  3'd1: bus width is 2.
+ *  3'd2: bus width is 4.
+ *  3'd3: bus width is 8.
+ */
+#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
+#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_S  29
+
+/** PARL_IO_RX_GENRL_CFG_REG register
+ *  Parallel RX general configuration register.
+ */
+#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
+/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable the clock gating of output rx clock.
+ */
+#define PARL_IO_RX_GATING_EN    (BIT(12))
+#define PARL_IO_RX_GATING_EN_M  (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
+#define PARL_IO_RX_GATING_EN_V  0x00000001U
+#define PARL_IO_RX_GATING_EN_S  12
+/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
+ *  Configures threshold of timeout counter.
+ */
+#define PARL_IO_RX_TIMEOUT_THRES    0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRES_M  (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
+#define PARL_IO_RX_TIMEOUT_THRES_V  0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRES_S  13
+/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
+ *  Set this bit to enable timeout function to generate error eof.
+ */
+#define PARL_IO_RX_TIMEOUT_EN    (BIT(29))
+#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
+#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
+#define PARL_IO_RX_TIMEOUT_EN_S  29
+/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
+ *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data byte
+ *  length. 1'b1: eof generated by external enable signal.
+ */
+#define PARL_IO_RX_EOF_GEN_SEL    (BIT(30))
+#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
+#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
+#define PARL_IO_RX_EOF_GEN_SEL_S  30
+
+/** PARL_IO_RX_START_CFG_REG register
+ *  Parallel RX Start configuration register.
+ */
+#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
+/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start rx data sampling.
+ */
+#define PARL_IO_RX_START    (BIT(31))
+#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
+#define PARL_IO_RX_START_V  0x00000001U
+#define PARL_IO_RX_START_S  31
+
+/** PARL_IO_TX_DATA_CFG_REG register
+ *  Parallel TX data configuration register.
+ */
+#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
+/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
+ *  Configures expected byte number of sent data.
+ */
+#define PARL_IO_TX_BITLEN    0x0007FFFFU
+#define PARL_IO_TX_BITLEN_M  (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
+#define PARL_IO_TX_BITLEN_V  0x0007FFFFU
+#define PARL_IO_TX_BITLEN_S  9
+/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
+ */
+#define PARL_IO_TX_DATA_ORDER_INV    (BIT(28))
+#define PARL_IO_TX_DATA_ORDER_INV_M  (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
+#define PARL_IO_TX_DATA_ORDER_INV_V  0x00000001U
+#define PARL_IO_TX_DATA_ORDER_INV_S  28
+/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
+ *  Configures the txd bus width.
+ *  3'd0: bus width is 1.
+ *  3'd1: bus width is 2.
+ *  3'd2: bus width is 4.
+ *  3'd3: bus width is 8.
+ */
+#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
+#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_S  29
+
+/** PARL_IO_TX_START_CFG_REG register
+ *  Parallel TX Start configuration register.
+ */
+#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
+/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start tx data transmit.
+ */
+#define PARL_IO_TX_START    (BIT(31))
+#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
+#define PARL_IO_TX_START_V  0x00000001U
+#define PARL_IO_TX_START_S  31
+
+/** PARL_IO_TX_GENRL_CFG_REG register
+ *  Parallel TX general configuration register.
+ */
+#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
+/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
+ *  Configures bus value of transmitter in IDLE state.
+ */
+#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
+#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_S  14
+/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to enable the clock gating of output tx clock.
+ */
+#define PARL_IO_TX_GATING_EN    (BIT(30))
+#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
+#define PARL_IO_TX_GATING_EN_V  0x00000001U
+#define PARL_IO_TX_GATING_EN_S  30
+/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to enable the output of tx data valid signal.
+ */
+#define PARL_IO_TX_VALID_OUTPUT_EN    (BIT(31))
+#define PARL_IO_TX_VALID_OUTPUT_EN_M  (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
+#define PARL_IO_TX_VALID_OUTPUT_EN_V  0x00000001U
+#define PARL_IO_TX_VALID_OUTPUT_EN_S  31
+
+/** PARL_IO_FIFO_CFG_REG register
+ *  Parallel IO FIFO configuration register.
+ */
+#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
+/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to reset async fifo in tx module.
+ */
+#define PARL_IO_TX_FIFO_SRST    (BIT(30))
+#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
+#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_TX_FIFO_SRST_S  30
+/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to reset async fifo in rx module.
+ */
+#define PARL_IO_RX_FIFO_SRST    (BIT(31))
+#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
+#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_RX_FIFO_SRST_S  31
+
+/** PARL_IO_REG_UPDATE_REG register
+ *  Parallel IO FIFO configuration register.
+ */
+#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
+/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
+ *  Set this bit to update rx register configuration.
+ */
+#define PARL_IO_RX_REG_UPDATE    (BIT(31))
+#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
+#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
+#define PARL_IO_RX_REG_UPDATE_S  31
+
+/** PARL_IO_ST_REG register
+ *  Parallel IO module status register0.
+ */
+#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
+/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
+ *  Represents the status that tx is ready to transmit.
+ */
+#define PARL_IO_TX_READY    (BIT(31))
+#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
+#define PARL_IO_TX_READY_V  0x00000001U
+#define PARL_IO_TX_READY_S  31
+
+/** PARL_IO_INT_ENA_REG register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M  (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S  1
+/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
+#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ENA_S  2
+
+/** PARL_IO_INT_RAW_REG register
+ *  Parallel IO interrupt raw signal status register.
+ */
+#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
+/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M  (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S  1
+/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
+#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
+#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_RAW_S  2
+
+/** PARL_IO_INT_ST_REG register
+ *  Parallel IO interrupt signal status register.
+ */
+#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_ST    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_M  (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_S  1
+/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
+#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ST_S  2
+
+/** PARL_IO_INT_CLR_REG register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
+/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M  (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S  1
+/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
+#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
+#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_CLR_S  2
+
+/** PARL_IO_RX_ST0_REG register
+ *  Parallel IO RX status register0
+ */
+#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
+/** PARL_IO_RX_CNT : RO; bitpos: [12:9]; default: 0;
+ *  Indicates the cycle number of reading Rx FIFO.
+ */
+#define PARL_IO_RX_CNT    0x0000000FU
+#define PARL_IO_RX_CNT_M  (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
+#define PARL_IO_RX_CNT_V  0x0000000FU
+#define PARL_IO_RX_CNT_S  9
+/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current written bit number into Rx FIFO.
+ */
+#define PARL_IO_RX_FIFO_WR_BIT_CNT    0x0007FFFFU
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_M  (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_S  13
+
+/** PARL_IO_RX_ST1_REG register
+ *  Parallel IO RX status register1
+ */
+#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
+/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current read bit number from Rx FIFO.
+ */
+#define PARL_IO_RX_FIFO_RD_BIT_CNT    0x0007FFFFU
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_M  (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_S  13
+
+/** PARL_IO_TX_ST0_REG register
+ *  Parallel IO TX status register0
+ */
+#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
+/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
+ *  Indicates the cycle number of reading Tx FIFO.
+ */
+#define PARL_IO_TX_CNT    0x0000007FU
+#define PARL_IO_TX_CNT_M  (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
+#define PARL_IO_TX_CNT_V  0x0000007FU
+#define PARL_IO_TX_CNT_S  6
+/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current read bit number from Tx FIFO.
+ */
+#define PARL_IO_TX_FIFO_RD_BIT_CNT    0x0007FFFFU
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_M  (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_S  13
+
+/** PARL_IO_RX_CLK_CFG_REG register
+ *  Parallel IO RX clk configuration register
+ */
+#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
+/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to invert the input Rx core clock.
+ */
+#define PARL_IO_RX_CLK_I_INV    (BIT(30))
+#define PARL_IO_RX_CLK_I_INV_M  (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
+#define PARL_IO_RX_CLK_I_INV_V  0x00000001U
+#define PARL_IO_RX_CLK_I_INV_S  30
+/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to invert the output Rx core clock.
+ */
+#define PARL_IO_RX_CLK_O_INV    (BIT(31))
+#define PARL_IO_RX_CLK_O_INV_M  (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
+#define PARL_IO_RX_CLK_O_INV_V  0x00000001U
+#define PARL_IO_RX_CLK_O_INV_S  31
+
+/** PARL_IO_TX_CLK_CFG_REG register
+ *  Parallel IO TX clk configuration register
+ */
+#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
+/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to invert the input Tx core clock.
+ */
+#define PARL_IO_TX_CLK_I_INV    (BIT(30))
+#define PARL_IO_TX_CLK_I_INV_M  (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
+#define PARL_IO_TX_CLK_I_INV_V  0x00000001U
+#define PARL_IO_TX_CLK_I_INV_S  30
+/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to invert the output Tx core clock.
+ */
+#define PARL_IO_TX_CLK_O_INV    (BIT(31))
+#define PARL_IO_TX_CLK_O_INV_M  (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
+#define PARL_IO_TX_CLK_O_INV_V  0x00000001U
+#define PARL_IO_TX_CLK_O_INV_S  31
+
+/** PARL_IO_CLK_REG register
+ *  Parallel IO clk configuration register
+ */
+#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
+/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Force clock on for this register file
+ */
+#define PARL_IO_CLK_EN    (BIT(31))
+#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
+#define PARL_IO_CLK_EN_V  0x00000001U
+#define PARL_IO_CLK_EN_S  31
+
+/** PARL_IO_VERSION_REG register
+ *  Version register.
+ */
+#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
+/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35684928;
+ *  Version of this register file
+ */
+#define PARL_IO_DATE    0x0FFFFFFFU
+#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
+#define PARL_IO_DATE_V  0x0FFFFFFFU
+#define PARL_IO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/parl_io_struct.h b/components/soc/esp32h2/register/soc/parl_io_struct.h
new file mode 100644
index 00000000000..6e501e6c579
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/parl_io_struct.h
@@ -0,0 +1,504 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PARL_IO RX  Mode Configuration */
+/** Type of rx_mode_cfg register
+ *  Parallel RX Sampling mode configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
+         *  Configures rx external enable signal selection from IO PAD.
+         */
+        uint32_t rx_ext_en_sel:4;
+        /** rx_sw_en : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to enable data sampling by software.
+         */
+        uint32_t rx_sw_en:1;
+        /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to invert the external enable signal.
+         */
+        uint32_t rx_ext_en_inv:1;
+        /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
+         *  Configures the rxd pulse sampling submode.
+         *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
+         *  included)
+         *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
+         *  excluded)
+         *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
+         *  included)
+         *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
+         *  excluded)
+         *  4'd4: positive pulse start(data bit included) && length end
+         *  4'd5: positive pulse start(data bit excluded) && length end
+         */
+        uint32_t rx_pulse_submode_sel:3;
+        /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Configures the rxd sampling mode.
+         *  2'b00: external level enable mode
+         *  2'b01: external pulse enable mode
+         *  2'b10: internal software enable mode
+         */
+        uint32_t rx_smp_mode_sel:2;
+    };
+    uint32_t val;
+} parl_io_rx_mode_cfg_reg_t;
+
+
+/** Group: PARL_IO RX Data Configuration */
+/** Type of rx_data_cfg register
+ *  Parallel RX data configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
+         *  Configures expected byte number of received data.
+         */
+        uint32_t rx_bitlen:19;
+        /** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
+         */
+        uint32_t rx_data_order_inv:1;
+        /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
+         *  Configures the rxd bus width.
+         *  3'd0: bus width is 1.
+         *  3'd1: bus width is 2.
+         *  3'd2: bus width is 4.
+         *  3'd3: bus width is 8.
+         */
+        uint32_t rx_bus_wid_sel:3;
+    };
+    uint32_t val;
+} parl_io_rx_data_cfg_reg_t;
+
+
+/** Group: PARL_IO RX General Configuration */
+/** Type of rx_genrl_cfg register
+ *  Parallel RX general configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rx_gating_en : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable the clock gating of output rx clock.
+         */
+        uint32_t rx_gating_en:1;
+        /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
+         *  Configures threshold of timeout counter.
+         */
+        uint32_t rx_timeout_thres:16;
+        /** rx_timeout_en : R/W; bitpos: [29]; default: 1;
+         *  Set this bit to enable timeout function to generate error eof.
+         */
+        uint32_t rx_timeout_en:1;
+        /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
+         *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data byte
+         *  length. 1'b1: eof generated by external enable signal.
+         */
+        uint32_t rx_eof_gen_sel:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} parl_io_rx_genrl_cfg_reg_t;
+
+
+/** Group: PARL_IO RX Start Configuration */
+/** Type of rx_start_cfg register
+ *  Parallel RX Start configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** rx_start : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start rx data sampling.
+         */
+        uint32_t rx_start:1;
+    };
+    uint32_t val;
+} parl_io_rx_start_cfg_reg_t;
+
+
+/** Group: PARL_IO TX Data Configuration */
+/** Type of tx_data_cfg register
+ *  Parallel TX data configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
+         *  Configures expected byte number of sent data.
+         */
+        uint32_t tx_bitlen:19;
+        /** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
+         */
+        uint32_t tx_data_order_inv:1;
+        /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
+         *  Configures the txd bus width.
+         *  3'd0: bus width is 1.
+         *  3'd1: bus width is 2.
+         *  3'd2: bus width is 4.
+         *  3'd3: bus width is 8.
+         */
+        uint32_t tx_bus_wid_sel:3;
+    };
+    uint32_t val;
+} parl_io_tx_data_cfg_reg_t;
+
+
+/** Group: PARL_IO TX Start Configuration */
+/** Type of tx_start_cfg register
+ *  Parallel TX Start configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_start : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start tx data transmit.
+         */
+        uint32_t tx_start:1;
+    };
+    uint32_t val;
+} parl_io_tx_start_cfg_reg_t;
+
+
+/** Group: PARL_IO TX General Configuration */
+/** Type of tx_genrl_cfg register
+ *  Parallel TX general configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
+         *  Configures bus value of transmitter in IDLE state.
+         */
+        uint32_t tx_idle_value:16;
+        /** tx_gating_en : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to enable the clock gating of output tx clock.
+         */
+        uint32_t tx_gating_en:1;
+        /** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to enable the output of tx data valid signal.
+         */
+        uint32_t tx_valid_output_en:1;
+    };
+    uint32_t val;
+} parl_io_tx_genrl_cfg_reg_t;
+
+
+/** Group: PARL_IO FIFO Configuration */
+/** Type of fifo_cfg register
+ *  Parallel IO FIFO configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to reset async fifo in tx module.
+         */
+        uint32_t tx_fifo_srst:1;
+        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to reset async fifo in rx module.
+         */
+        uint32_t rx_fifo_srst:1;
+    };
+    uint32_t val;
+} parl_io_fifo_cfg_reg_t;
+
+
+/** Group: PARL_IO Register Update Configuration */
+/** Type of reg_update register
+ *  Parallel IO FIFO configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** rx_reg_update : WT; bitpos: [31]; default: 0;
+         *  Set this bit to update rx register configuration.
+         */
+        uint32_t rx_reg_update:1;
+    };
+    uint32_t val;
+} parl_io_reg_update_reg_t;
+
+
+/** Group: PARL_IO Status */
+/** Type of st register
+ *  Parallel IO module status register0.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_ready : RO; bitpos: [31]; default: 0;
+         *  Represents the status that tx is ready to transmit.
+         */
+        uint32_t tx_ready:1;
+    };
+    uint32_t val;
+} parl_io_st_reg_t;
+
+
+/** Group: PARL_IO Interrupt Configuration and Status */
+/** Type of int_ena register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_ena:1;
+        /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_ena:1;
+        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Parallel IO interrupt raw signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_raw:1;
+        /** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_raw:1;
+        /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Parallel IO interrupt signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_st:1;
+        /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_st:1;
+        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_clr:1;
+        /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_clr:1;
+        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_clr_reg_t;
+
+
+/** Group: PARL_IO Rx Status0 */
+/** Type of rx_st0 register
+ *  Parallel IO RX status register0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** rx_cnt : RO; bitpos: [12:9]; default: 0;
+         *  Indicates the cycle number of reading Rx FIFO.
+         */
+        uint32_t rx_cnt:4;
+        /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current written bit number into Rx FIFO.
+         */
+        uint32_t rx_fifo_wr_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_rx_st0_reg_t;
+
+
+/** Group: PARL_IO Rx Status1 */
+/** Type of rx_st1 register
+ *  Parallel IO RX status register1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current read bit number from Rx FIFO.
+         */
+        uint32_t rx_fifo_rd_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_rx_st1_reg_t;
+
+
+/** Group: PARL_IO Tx Status0 */
+/** Type of tx_st0 register
+ *  Parallel IO TX status register0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** tx_cnt : RO; bitpos: [12:6]; default: 0;
+         *  Indicates the cycle number of reading Tx FIFO.
+         */
+        uint32_t tx_cnt:7;
+        /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current read bit number from Tx FIFO.
+         */
+        uint32_t tx_fifo_rd_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_tx_st0_reg_t;
+
+
+/** Group: PARL_IO Rx Clock Configuration */
+/** Type of rx_clk_cfg register
+ *  Parallel IO RX clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to invert the input Rx core clock.
+         */
+        uint32_t rx_clk_i_inv:1;
+        /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to invert the output Rx core clock.
+         */
+        uint32_t rx_clk_o_inv:1;
+    };
+    uint32_t val;
+} parl_io_rx_clk_cfg_reg_t;
+
+
+/** Group: PARL_IO Tx Clock Configuration */
+/** Type of tx_clk_cfg register
+ *  Parallel IO TX clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to invert the input Tx core clock.
+         */
+        uint32_t tx_clk_i_inv:1;
+        /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to invert the output Tx core clock.
+         */
+        uint32_t tx_clk_o_inv:1;
+    };
+    uint32_t val;
+} parl_io_tx_clk_cfg_reg_t;
+
+
+/** Group: PARL_IO Clock Configuration */
+/** Type of clk register
+ *  Parallel IO clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} parl_io_clk_reg_t;
+
+
+/** Group: PARL_IO Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35684928;
+         *  Version of this register file
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} parl_io_version_reg_t;
+
+
+typedef struct parl_io_dev_t {
+    volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
+    volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
+    volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
+    volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
+    volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
+    volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
+    volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
+    volatile parl_io_fifo_cfg_reg_t fifo_cfg;
+    volatile parl_io_reg_update_reg_t reg_update;
+    volatile parl_io_st_reg_t st;
+    volatile parl_io_int_ena_reg_t int_ena;
+    volatile parl_io_int_raw_reg_t int_raw;
+    volatile parl_io_int_st_reg_t int_st;
+    volatile parl_io_int_clr_reg_t int_clr;
+    volatile parl_io_rx_st0_reg_t rx_st0;
+    volatile parl_io_rx_st1_reg_t rx_st1;
+    volatile parl_io_tx_st0_reg_t tx_st0;
+    volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
+    volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
+    uint32_t reserved_04c[53];
+    volatile parl_io_clk_reg_t clk;
+    uint32_t reserved_124[182];
+    volatile parl_io_version_reg_t version;
+} parl_io_dev_t;
+
+extern parl_io_dev_t PARL_IO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/pau_reg.h b/components/soc/esp32h2/register/soc/pau_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/pau_reg.h
rename to components/soc/esp32h2/register/soc/pau_reg.h
diff --git a/components/soc/esp32h2/include/soc/pau_struct.h b/components/soc/esp32h2/register/soc/pau_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/pau_struct.h
rename to components/soc/esp32h2/register/soc/pau_struct.h
diff --git a/components/soc/esp32h2/include/soc/pcnt_reg.h b/components/soc/esp32h2/register/soc/pcnt_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/pcnt_reg.h
rename to components/soc/esp32h2/register/soc/pcnt_reg.h
diff --git a/components/soc/esp32h2/include/soc/pcnt_struct.h b/components/soc/esp32h2/register/soc/pcnt_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/pcnt_struct.h
rename to components/soc/esp32h2/register/soc/pcnt_struct.h
diff --git a/components/soc/esp32h2/register/soc/pcr_reg.h b/components/soc/esp32h2/register/soc/pcr_reg.h
new file mode 100644
index 00000000000..02d26df2db3
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/pcr_reg.h
@@ -0,0 +1,2347 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PCR_UART0_CONF_REG register
+ *  UART0 configuration register
+ */
+#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0)
+/** PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uart0 apb clock
+ */
+#define PCR_UART0_CLK_EN    (BIT(0))
+#define PCR_UART0_CLK_EN_M  (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S)
+#define PCR_UART0_CLK_EN_V  0x00000001U
+#define PCR_UART0_CLK_EN_S  0
+/** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uart0 module
+ */
+#define PCR_UART0_RST_EN    (BIT(1))
+#define PCR_UART0_RST_EN_M  (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S)
+#define PCR_UART0_RST_EN_V  0x00000001U
+#define PCR_UART0_RST_EN_S  1
+/** PCR_UART0_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset uart0 module
+ */
+#define PCR_UART0_READY    (BIT(2))
+#define PCR_UART0_READY_M  (PCR_UART0_READY_V << PCR_UART0_READY_S)
+#define PCR_UART0_READY_V  0x00000001U
+#define PCR_UART0_READY_S  2
+
+/** PCR_UART0_SCLK_CONF_REG register
+ *  UART0_SCLK configuration register
+ */
+#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4)
+/** PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_A    0x0000003FU
+#define PCR_UART0_SCLK_DIV_A_M  (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S)
+#define PCR_UART0_SCLK_DIV_A_V  0x0000003FU
+#define PCR_UART0_SCLK_DIV_A_S  0
+/** PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_B    0x0000003FU
+#define PCR_UART0_SCLK_DIV_B_M  (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S)
+#define PCR_UART0_SCLK_DIV_B_V  0x0000003FU
+#define PCR_UART0_SCLK_DIV_B_S  6
+/** PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the uart0 function clock.
+ */
+#define PCR_UART0_SCLK_DIV_NUM    0x000000FFU
+#define PCR_UART0_SCLK_DIV_NUM_M  (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S)
+#define PCR_UART0_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_UART0_SCLK_DIV_NUM_S  12
+/** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_UART0_SCLK_SEL    0x00000003U
+#define PCR_UART0_SCLK_SEL_M  (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S)
+#define PCR_UART0_SCLK_SEL_V  0x00000003U
+#define PCR_UART0_SCLK_SEL_S  20
+/** PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable uart0 function clock
+ */
+#define PCR_UART0_SCLK_EN    (BIT(22))
+#define PCR_UART0_SCLK_EN_M  (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S)
+#define PCR_UART0_SCLK_EN_V  0x00000001U
+#define PCR_UART0_SCLK_EN_S  22
+
+/** PCR_UART0_PD_CTRL_REG register
+ *  UART0 power control register
+ */
+#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8)
+/** PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power down UART0 memory.
+ */
+#define PCR_UART0_MEM_FORCE_PU    (BIT(1))
+#define PCR_UART0_MEM_FORCE_PU_M  (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S)
+#define PCR_UART0_MEM_FORCE_PU_V  0x00000001U
+#define PCR_UART0_MEM_FORCE_PU_S  1
+/** PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power up UART0 memory.
+ */
+#define PCR_UART0_MEM_FORCE_PD    (BIT(2))
+#define PCR_UART0_MEM_FORCE_PD_M  (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S)
+#define PCR_UART0_MEM_FORCE_PD_V  0x00000001U
+#define PCR_UART0_MEM_FORCE_PD_S  2
+
+/** PCR_UART1_CONF_REG register
+ *  UART1 configuration register
+ */
+#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc)
+/** PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uart1 apb clock
+ */
+#define PCR_UART1_CLK_EN    (BIT(0))
+#define PCR_UART1_CLK_EN_M  (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S)
+#define PCR_UART1_CLK_EN_V  0x00000001U
+#define PCR_UART1_CLK_EN_S  0
+/** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uart1 module
+ */
+#define PCR_UART1_RST_EN    (BIT(1))
+#define PCR_UART1_RST_EN_M  (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S)
+#define PCR_UART1_RST_EN_V  0x00000001U
+#define PCR_UART1_RST_EN_S  1
+/** PCR_UART1_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset uart1 module
+ */
+#define PCR_UART1_READY    (BIT(2))
+#define PCR_UART1_READY_M  (PCR_UART1_READY_V << PCR_UART1_READY_S)
+#define PCR_UART1_READY_V  0x00000001U
+#define PCR_UART1_READY_S  2
+
+/** PCR_UART1_SCLK_CONF_REG register
+ *  UART1_SCLK configuration register
+ */
+#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10)
+/** PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_A    0x0000003FU
+#define PCR_UART1_SCLK_DIV_A_M  (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S)
+#define PCR_UART1_SCLK_DIV_A_V  0x0000003FU
+#define PCR_UART1_SCLK_DIV_A_S  0
+/** PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_B    0x0000003FU
+#define PCR_UART1_SCLK_DIV_B_M  (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S)
+#define PCR_UART1_SCLK_DIV_B_V  0x0000003FU
+#define PCR_UART1_SCLK_DIV_B_S  6
+/** PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the uart1 function clock.
+ */
+#define PCR_UART1_SCLK_DIV_NUM    0x000000FFU
+#define PCR_UART1_SCLK_DIV_NUM_M  (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S)
+#define PCR_UART1_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_UART1_SCLK_DIV_NUM_S  12
+/** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_UART1_SCLK_SEL    0x00000003U
+#define PCR_UART1_SCLK_SEL_M  (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S)
+#define PCR_UART1_SCLK_SEL_V  0x00000003U
+#define PCR_UART1_SCLK_SEL_S  20
+/** PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable uart0 function clock
+ */
+#define PCR_UART1_SCLK_EN    (BIT(22))
+#define PCR_UART1_SCLK_EN_M  (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S)
+#define PCR_UART1_SCLK_EN_V  0x00000001U
+#define PCR_UART1_SCLK_EN_S  22
+
+/** PCR_UART1_PD_CTRL_REG register
+ *  UART1 power control register
+ */
+#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14)
+/** PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power down UART1 memory.
+ */
+#define PCR_UART1_MEM_FORCE_PU    (BIT(1))
+#define PCR_UART1_MEM_FORCE_PU_M  (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S)
+#define PCR_UART1_MEM_FORCE_PU_V  0x00000001U
+#define PCR_UART1_MEM_FORCE_PU_S  1
+/** PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power up UART1 memory.
+ */
+#define PCR_UART1_MEM_FORCE_PD    (BIT(2))
+#define PCR_UART1_MEM_FORCE_PD_M  (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S)
+#define PCR_UART1_MEM_FORCE_PD_V  0x00000001U
+#define PCR_UART1_MEM_FORCE_PD_S  2
+
+/** PCR_MSPI_CONF_REG register
+ *  MSPI configuration register
+ */
+#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18)
+/** PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable mspi clock, include mspi pll clock
+ */
+#define PCR_MSPI_CLK_EN    (BIT(0))
+#define PCR_MSPI_CLK_EN_M  (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S)
+#define PCR_MSPI_CLK_EN_V  0x00000001U
+#define PCR_MSPI_CLK_EN_S  0
+/** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset mspi module
+ */
+#define PCR_MSPI_RST_EN    (BIT(1))
+#define PCR_MSPI_RST_EN_M  (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S)
+#define PCR_MSPI_RST_EN_V  0x00000001U
+#define PCR_MSPI_RST_EN_S  1
+/** PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable mspi pll clock
+ */
+#define PCR_MSPI_PLL_CLK_EN    (BIT(2))
+#define PCR_MSPI_PLL_CLK_EN_M  (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S)
+#define PCR_MSPI_PLL_CLK_EN_V  0x00000001U
+#define PCR_MSPI_PLL_CLK_EN_S  2
+/** PCR_MSPI_CLK_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  set this field to select clock-source.
+ */
+#define PCR_MSPI_CLK_SEL    0x00000003U
+#define PCR_MSPI_CLK_SEL_M  (PCR_MSPI_CLK_SEL_V << PCR_MSPI_CLK_SEL_S)
+#define PCR_MSPI_CLK_SEL_V  0x00000003U
+#define PCR_MSPI_CLK_SEL_S  3
+/** PCR_MSPI_READY : RO; bitpos: [5]; default: 1;
+ *  Query this field after reset mspi module
+ */
+#define PCR_MSPI_READY    (BIT(5))
+#define PCR_MSPI_READY_M  (PCR_MSPI_READY_V << PCR_MSPI_READY_S)
+#define PCR_MSPI_READY_V  0x00000001U
+#define PCR_MSPI_READY_S  5
+
+/** PCR_MSPI_CLK_CONF_REG register
+ *  MSPI_CLK configuration register
+ */
+#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c)
+/** PCR_MSPI_FAST_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
+ *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
+ *  low-speed clock-source such as XTAL/FOSC.
+ */
+#define PCR_MSPI_FAST_DIV_NUM    0x000000FFU
+#define PCR_MSPI_FAST_DIV_NUM_M  (PCR_MSPI_FAST_DIV_NUM_V << PCR_MSPI_FAST_DIV_NUM_S)
+#define PCR_MSPI_FAST_DIV_NUM_V  0x000000FFU
+#define PCR_MSPI_FAST_DIV_NUM_S  0
+
+/** PCR_I2C0_CONF_REG register
+ *  I2C configuration register
+ */
+#define PCR_I2C0_CONF_REG (DR_REG_PCR_BASE + 0x20)
+/** PCR_I2C0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable i2c apb clock
+ */
+#define PCR_I2C0_CLK_EN    (BIT(0))
+#define PCR_I2C0_CLK_EN_M  (PCR_I2C0_CLK_EN_V << PCR_I2C0_CLK_EN_S)
+#define PCR_I2C0_CLK_EN_V  0x00000001U
+#define PCR_I2C0_CLK_EN_S  0
+/** PCR_I2C0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset i2c module
+ */
+#define PCR_I2C0_RST_EN    (BIT(1))
+#define PCR_I2C0_RST_EN_M  (PCR_I2C0_RST_EN_V << PCR_I2C0_RST_EN_S)
+#define PCR_I2C0_RST_EN_V  0x00000001U
+#define PCR_I2C0_RST_EN_S  1
+/** PCR_I2C0_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset i2c0 module
+ */
+#define PCR_I2C0_READY    (BIT(2))
+#define PCR_I2C0_READY_M  (PCR_I2C0_READY_V << PCR_I2C0_READY_S)
+#define PCR_I2C0_READY_V  0x00000001U
+#define PCR_I2C0_READY_S  2
+
+/** PCR_I2C0_SCLK_CONF_REG register
+ *  I2C_SCLK configuration register
+ */
+#define PCR_I2C0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24)
+/** PCR_I2C0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C0_SCLK_DIV_A    0x0000003FU
+#define PCR_I2C0_SCLK_DIV_A_M  (PCR_I2C0_SCLK_DIV_A_V << PCR_I2C0_SCLK_DIV_A_S)
+#define PCR_I2C0_SCLK_DIV_A_V  0x0000003FU
+#define PCR_I2C0_SCLK_DIV_A_S  0
+/** PCR_I2C0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C0_SCLK_DIV_B    0x0000003FU
+#define PCR_I2C0_SCLK_DIV_B_M  (PCR_I2C0_SCLK_DIV_B_V << PCR_I2C0_SCLK_DIV_B_S)
+#define PCR_I2C0_SCLK_DIV_B_V  0x0000003FU
+#define PCR_I2C0_SCLK_DIV_B_S  6
+/** PCR_I2C0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C0_SCLK_DIV_NUM    0x000000FFU
+#define PCR_I2C0_SCLK_DIV_NUM_M  (PCR_I2C0_SCLK_DIV_NUM_V << PCR_I2C0_SCLK_DIV_NUM_S)
+#define PCR_I2C0_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_I2C0_SCLK_DIV_NUM_S  12
+/** PCR_I2C0_SCLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_I2C0_SCLK_SEL    (BIT(20))
+#define PCR_I2C0_SCLK_SEL_M  (PCR_I2C0_SCLK_SEL_V << PCR_I2C0_SCLK_SEL_S)
+#define PCR_I2C0_SCLK_SEL_V  0x00000001U
+#define PCR_I2C0_SCLK_SEL_S  20
+/** PCR_I2C0_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2c function clock
+ */
+#define PCR_I2C0_SCLK_EN    (BIT(22))
+#define PCR_I2C0_SCLK_EN_M  (PCR_I2C0_SCLK_EN_V << PCR_I2C0_SCLK_EN_S)
+#define PCR_I2C0_SCLK_EN_V  0x00000001U
+#define PCR_I2C0_SCLK_EN_S  22
+
+/** PCR_I2C1_CONF_REG register
+ *  I2C configuration register
+ */
+#define PCR_I2C1_CONF_REG (DR_REG_PCR_BASE + 0x28)
+/** PCR_I2C1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable i2c apb clock
+ */
+#define PCR_I2C1_CLK_EN    (BIT(0))
+#define PCR_I2C1_CLK_EN_M  (PCR_I2C1_CLK_EN_V << PCR_I2C1_CLK_EN_S)
+#define PCR_I2C1_CLK_EN_V  0x00000001U
+#define PCR_I2C1_CLK_EN_S  0
+/** PCR_I2C1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset i2c module
+ */
+#define PCR_I2C1_RST_EN    (BIT(1))
+#define PCR_I2C1_RST_EN_M  (PCR_I2C1_RST_EN_V << PCR_I2C1_RST_EN_S)
+#define PCR_I2C1_RST_EN_V  0x00000001U
+#define PCR_I2C1_RST_EN_S  1
+/** PCR_I2C1_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset i2c1 module
+ */
+#define PCR_I2C1_READY    (BIT(2))
+#define PCR_I2C1_READY_M  (PCR_I2C1_READY_V << PCR_I2C1_READY_S)
+#define PCR_I2C1_READY_V  0x00000001U
+#define PCR_I2C1_READY_S  2
+
+/** PCR_I2C1_SCLK_CONF_REG register
+ *  I2C_SCLK configuration register
+ */
+#define PCR_I2C1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x2c)
+/** PCR_I2C1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C1_SCLK_DIV_A    0x0000003FU
+#define PCR_I2C1_SCLK_DIV_A_M  (PCR_I2C1_SCLK_DIV_A_V << PCR_I2C1_SCLK_DIV_A_S)
+#define PCR_I2C1_SCLK_DIV_A_V  0x0000003FU
+#define PCR_I2C1_SCLK_DIV_A_S  0
+/** PCR_I2C1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C1_SCLK_DIV_B    0x0000003FU
+#define PCR_I2C1_SCLK_DIV_B_M  (PCR_I2C1_SCLK_DIV_B_V << PCR_I2C1_SCLK_DIV_B_S)
+#define PCR_I2C1_SCLK_DIV_B_V  0x0000003FU
+#define PCR_I2C1_SCLK_DIV_B_S  6
+/** PCR_I2C1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0;
+ *  The integral part of the frequency divider factor of the i2c function clock.
+ */
+#define PCR_I2C1_SCLK_DIV_NUM    0x000000FFU
+#define PCR_I2C1_SCLK_DIV_NUM_M  (PCR_I2C1_SCLK_DIV_NUM_V << PCR_I2C1_SCLK_DIV_NUM_S)
+#define PCR_I2C1_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_I2C1_SCLK_DIV_NUM_S  12
+/** PCR_I2C1_SCLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_I2C1_SCLK_SEL    (BIT(20))
+#define PCR_I2C1_SCLK_SEL_M  (PCR_I2C1_SCLK_SEL_V << PCR_I2C1_SCLK_SEL_S)
+#define PCR_I2C1_SCLK_SEL_V  0x00000001U
+#define PCR_I2C1_SCLK_SEL_S  20
+/** PCR_I2C1_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2c function clock
+ */
+#define PCR_I2C1_SCLK_EN    (BIT(22))
+#define PCR_I2C1_SCLK_EN_M  (PCR_I2C1_SCLK_EN_V << PCR_I2C1_SCLK_EN_S)
+#define PCR_I2C1_SCLK_EN_V  0x00000001U
+#define PCR_I2C1_SCLK_EN_S  22
+
+/** PCR_UHCI_CONF_REG register
+ *  UHCI configuration register
+ */
+#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x30)
+/** PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable uhci clock
+ */
+#define PCR_UHCI_CLK_EN    (BIT(0))
+#define PCR_UHCI_CLK_EN_M  (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S)
+#define PCR_UHCI_CLK_EN_V  0x00000001U
+#define PCR_UHCI_CLK_EN_S  0
+/** PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset uhci module
+ */
+#define PCR_UHCI_RST_EN    (BIT(1))
+#define PCR_UHCI_RST_EN_M  (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S)
+#define PCR_UHCI_RST_EN_V  0x00000001U
+#define PCR_UHCI_RST_EN_S  1
+/** PCR_UHCI_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset uhci module
+ */
+#define PCR_UHCI_READY    (BIT(2))
+#define PCR_UHCI_READY_M  (PCR_UHCI_READY_V << PCR_UHCI_READY_S)
+#define PCR_UHCI_READY_V  0x00000001U
+#define PCR_UHCI_READY_S  2
+
+/** PCR_RMT_CONF_REG register
+ *  RMT configuration register
+ */
+#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x34)
+/** PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable rmt apb clock
+ */
+#define PCR_RMT_CLK_EN    (BIT(0))
+#define PCR_RMT_CLK_EN_M  (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S)
+#define PCR_RMT_CLK_EN_V  0x00000001U
+#define PCR_RMT_CLK_EN_S  0
+/** PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset rmt module
+ */
+#define PCR_RMT_RST_EN    (BIT(1))
+#define PCR_RMT_RST_EN_M  (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S)
+#define PCR_RMT_RST_EN_V  0x00000001U
+#define PCR_RMT_RST_EN_S  1
+/** PCR_RMT_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset rmt module
+ */
+#define PCR_RMT_READY    (BIT(2))
+#define PCR_RMT_READY_M  (PCR_RMT_READY_V << PCR_RMT_READY_S)
+#define PCR_RMT_READY_V  0x00000001U
+#define PCR_RMT_READY_S  2
+
+/** PCR_RMT_SCLK_CONF_REG register
+ *  RMT_SCLK configuration register
+ */
+#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38)
+/** PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_A    0x0000003FU
+#define PCR_RMT_SCLK_DIV_A_M  (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S)
+#define PCR_RMT_SCLK_DIV_A_V  0x0000003FU
+#define PCR_RMT_SCLK_DIV_A_S  0
+/** PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_B    0x0000003FU
+#define PCR_RMT_SCLK_DIV_B_M  (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S)
+#define PCR_RMT_SCLK_DIV_B_V  0x0000003FU
+#define PCR_RMT_SCLK_DIV_B_S  6
+/** PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
+ *  The integral part of the frequency divider factor of the rmt function clock.
+ */
+#define PCR_RMT_SCLK_DIV_NUM    0x000000FFU
+#define PCR_RMT_SCLK_DIV_NUM_M  (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S)
+#define PCR_RMT_SCLK_DIV_NUM_V  0x000000FFU
+#define PCR_RMT_SCLK_DIV_NUM_S  12
+/** PCR_RMT_SCLK_SEL : R/W; bitpos: [20]; default: 1;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
+ *  80MHz, 2: FOSC, 3: XTAL.
+ */
+#define PCR_RMT_SCLK_SEL    (BIT(20))
+#define PCR_RMT_SCLK_SEL_M  (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S)
+#define PCR_RMT_SCLK_SEL_V  0x00000001U
+#define PCR_RMT_SCLK_SEL_S  20
+/** PCR_RMT_SCLK_EN : R/W; bitpos: [21]; default: 1;
+ *  Set 1 to enable rmt function clock
+ */
+#define PCR_RMT_SCLK_EN    (BIT(21))
+#define PCR_RMT_SCLK_EN_M  (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S)
+#define PCR_RMT_SCLK_EN_V  0x00000001U
+#define PCR_RMT_SCLK_EN_S  21
+
+/** PCR_LEDC_CONF_REG register
+ *  LEDC configuration register
+ */
+#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x3c)
+/** PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ledc apb clock
+ */
+#define PCR_LEDC_CLK_EN    (BIT(0))
+#define PCR_LEDC_CLK_EN_M  (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S)
+#define PCR_LEDC_CLK_EN_V  0x00000001U
+#define PCR_LEDC_CLK_EN_S  0
+/** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ledc module
+ */
+#define PCR_LEDC_RST_EN    (BIT(1))
+#define PCR_LEDC_RST_EN_M  (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S)
+#define PCR_LEDC_RST_EN_V  0x00000001U
+#define PCR_LEDC_RST_EN_S  1
+/** PCR_LEDC_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset ledc module
+ */
+#define PCR_LEDC_READY    (BIT(2))
+#define PCR_LEDC_READY_M  (PCR_LEDC_READY_V << PCR_LEDC_READY_S)
+#define PCR_LEDC_READY_V  0x00000001U
+#define PCR_LEDC_READY_S  2
+
+/** PCR_LEDC_SCLK_CONF_REG register
+ *  LEDC_SCLK configuration register
+ */
+#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
+/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+ *  80MHz, 2: FOSC, 3: XTAL.
+ */
+#define PCR_LEDC_SCLK_SEL    0x00000003U
+#define PCR_LEDC_SCLK_SEL_M  (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
+#define PCR_LEDC_SCLK_SEL_V  0x00000003U
+#define PCR_LEDC_SCLK_SEL_S  20
+/** PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable ledc function clock
+ */
+#define PCR_LEDC_SCLK_EN    (BIT(22))
+#define PCR_LEDC_SCLK_EN_M  (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S)
+#define PCR_LEDC_SCLK_EN_V  0x00000001U
+#define PCR_LEDC_SCLK_EN_S  22
+
+/** PCR_TIMERGROUP0_CONF_REG register
+ *  TIMERGROUP0 configuration register
+ */
+#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x44)
+/** PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable timer_group0 apb clock
+ */
+#define PCR_TG0_CLK_EN    (BIT(0))
+#define PCR_TG0_CLK_EN_M  (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S)
+#define PCR_TG0_CLK_EN_V  0x00000001U
+#define PCR_TG0_CLK_EN_S  0
+/** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset timer_group0 module
+ */
+#define PCR_TG0_RST_EN    (BIT(1))
+#define PCR_TG0_RST_EN_M  (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S)
+#define PCR_TG0_RST_EN_V  0x00000001U
+#define PCR_TG0_RST_EN_S  1
+/** PCR_TG0_WDT_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset timer_group0 wdt module
+ */
+#define PCR_TG0_WDT_READY    (BIT(2))
+#define PCR_TG0_WDT_READY_M  (PCR_TG0_WDT_READY_V << PCR_TG0_WDT_READY_S)
+#define PCR_TG0_WDT_READY_V  0x00000001U
+#define PCR_TG0_WDT_READY_S  2
+/** PCR_TG0_TIMER0_READY : RO; bitpos: [3]; default: 1;
+ *  Query this field after reset timer_group0 timer0 module
+ */
+#define PCR_TG0_TIMER0_READY    (BIT(3))
+#define PCR_TG0_TIMER0_READY_M  (PCR_TG0_TIMER0_READY_V << PCR_TG0_TIMER0_READY_S)
+#define PCR_TG0_TIMER0_READY_V  0x00000001U
+#define PCR_TG0_TIMER0_READY_S  3
+/** PCR_TG0_TIMER1_READY : RO; bitpos: [4]; default: 1;
+ *  reserved
+ */
+#define PCR_TG0_TIMER1_READY    (BIT(4))
+#define PCR_TG0_TIMER1_READY_M  (PCR_TG0_TIMER1_READY_V << PCR_TG0_TIMER1_READY_S)
+#define PCR_TG0_TIMER1_READY_V  0x00000001U
+#define PCR_TG0_TIMER1_READY_S  4
+
+/** PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register
+ *  TIMERGROUP0_TIMER_CLK configuration register
+ */
+#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48)
+/** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG0_TIMER_CLK_SEL    0x00000003U
+#define PCR_TG0_TIMER_CLK_SEL_M  (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S)
+#define PCR_TG0_TIMER_CLK_SEL_V  0x00000003U
+#define PCR_TG0_TIMER_CLK_SEL_S  20
+/** PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 timer clock
+ */
+#define PCR_TG0_TIMER_CLK_EN    (BIT(22))
+#define PCR_TG0_TIMER_CLK_EN_M  (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S)
+#define PCR_TG0_TIMER_CLK_EN_V  0x00000001U
+#define PCR_TG0_TIMER_CLK_EN_S  22
+
+/** PCR_TIMERGROUP0_WDT_CLK_CONF_REG register
+ *  TIMERGROUP0_WDT_CLK configuration register
+ */
+#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c)
+/** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG0_WDT_CLK_SEL    0x00000003U
+#define PCR_TG0_WDT_CLK_SEL_M  (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S)
+#define PCR_TG0_WDT_CLK_SEL_V  0x00000003U
+#define PCR_TG0_WDT_CLK_SEL_S  20
+/** PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 wdt clock
+ */
+#define PCR_TG0_WDT_CLK_EN    (BIT(22))
+#define PCR_TG0_WDT_CLK_EN_M  (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S)
+#define PCR_TG0_WDT_CLK_EN_V  0x00000001U
+#define PCR_TG0_WDT_CLK_EN_S  22
+
+/** PCR_TIMERGROUP1_CONF_REG register
+ *  TIMERGROUP1 configuration register
+ */
+#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x50)
+/** PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable timer_group1 apb clock
+ */
+#define PCR_TG1_CLK_EN    (BIT(0))
+#define PCR_TG1_CLK_EN_M  (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S)
+#define PCR_TG1_CLK_EN_V  0x00000001U
+#define PCR_TG1_CLK_EN_S  0
+/** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset timer_group1 module
+ */
+#define PCR_TG1_RST_EN    (BIT(1))
+#define PCR_TG1_RST_EN_M  (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S)
+#define PCR_TG1_RST_EN_V  0x00000001U
+#define PCR_TG1_RST_EN_S  1
+/** PCR_TG1_WDT_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset timer_group1 wdt module
+ */
+#define PCR_TG1_WDT_READY    (BIT(2))
+#define PCR_TG1_WDT_READY_M  (PCR_TG1_WDT_READY_V << PCR_TG1_WDT_READY_S)
+#define PCR_TG1_WDT_READY_V  0x00000001U
+#define PCR_TG1_WDT_READY_S  2
+/** PCR_TG1_TIMER0_READY : RO; bitpos: [3]; default: 1;
+ *  Query this field after reset timer_group1 timer0 module
+ */
+#define PCR_TG1_TIMER0_READY    (BIT(3))
+#define PCR_TG1_TIMER0_READY_M  (PCR_TG1_TIMER0_READY_V << PCR_TG1_TIMER0_READY_S)
+#define PCR_TG1_TIMER0_READY_V  0x00000001U
+#define PCR_TG1_TIMER0_READY_S  3
+/** PCR_TG1_TIMER1_READY : RO; bitpos: [4]; default: 1;
+ *  reserved
+ */
+#define PCR_TG1_TIMER1_READY    (BIT(4))
+#define PCR_TG1_TIMER1_READY_M  (PCR_TG1_TIMER1_READY_V << PCR_TG1_TIMER1_READY_S)
+#define PCR_TG1_TIMER1_READY_V  0x00000001U
+#define PCR_TG1_TIMER1_READY_S  4
+
+/** PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register
+ *  TIMERGROUP1_TIMER_CLK configuration register
+ */
+#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54)
+/** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG1_TIMER_CLK_SEL    0x00000003U
+#define PCR_TG1_TIMER_CLK_SEL_M  (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S)
+#define PCR_TG1_TIMER_CLK_SEL_V  0x00000003U
+#define PCR_TG1_TIMER_CLK_SEL_S  20
+/** PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group1 timer clock
+ */
+#define PCR_TG1_TIMER_CLK_EN    (BIT(22))
+#define PCR_TG1_TIMER_CLK_EN_M  (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S)
+#define PCR_TG1_TIMER_CLK_EN_V  0x00000001U
+#define PCR_TG1_TIMER_CLK_EN_S  22
+
+/** PCR_TIMERGROUP1_WDT_CLK_CONF_REG register
+ *  TIMERGROUP1_WDT_CLK configuration register
+ */
+#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58)
+/** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_TG1_WDT_CLK_SEL    0x00000003U
+#define PCR_TG1_WDT_CLK_SEL_M  (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S)
+#define PCR_TG1_WDT_CLK_SEL_V  0x00000003U
+#define PCR_TG1_WDT_CLK_SEL_S  20
+/** PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable timer_group0 wdt clock
+ */
+#define PCR_TG1_WDT_CLK_EN    (BIT(22))
+#define PCR_TG1_WDT_CLK_EN_M  (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S)
+#define PCR_TG1_WDT_CLK_EN_V  0x00000001U
+#define PCR_TG1_WDT_CLK_EN_S  22
+
+/** PCR_SYSTIMER_CONF_REG register
+ *  SYSTIMER configuration register
+ */
+#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x5c)
+/** PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable systimer apb clock
+ */
+#define PCR_SYSTIMER_CLK_EN    (BIT(0))
+#define PCR_SYSTIMER_CLK_EN_M  (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S)
+#define PCR_SYSTIMER_CLK_EN_V  0x00000001U
+#define PCR_SYSTIMER_CLK_EN_S  0
+/** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset systimer module
+ */
+#define PCR_SYSTIMER_RST_EN    (BIT(1))
+#define PCR_SYSTIMER_RST_EN_M  (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S)
+#define PCR_SYSTIMER_RST_EN_V  0x00000001U
+#define PCR_SYSTIMER_RST_EN_S  1
+/** PCR_SYSTIMER_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset systimer module
+ */
+#define PCR_SYSTIMER_READY    (BIT(2))
+#define PCR_SYSTIMER_READY_M  (PCR_SYSTIMER_READY_V << PCR_SYSTIMER_READY_S)
+#define PCR_SYSTIMER_READY_V  0x00000001U
+#define PCR_SYSTIMER_READY_S  2
+
+/** PCR_SYSTIMER_FUNC_CLK_CONF_REG register
+ *  SYSTIMER_FUNC_CLK configuration register
+ */
+#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60)
+/** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_SYSTIMER_FUNC_CLK_SEL    (BIT(20))
+#define PCR_SYSTIMER_FUNC_CLK_SEL_M  (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S)
+#define PCR_SYSTIMER_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_SYSTIMER_FUNC_CLK_SEL_S  20
+/** PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable systimer function clock
+ */
+#define PCR_SYSTIMER_FUNC_CLK_EN    (BIT(22))
+#define PCR_SYSTIMER_FUNC_CLK_EN_M  (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S)
+#define PCR_SYSTIMER_FUNC_CLK_EN_V  0x00000001U
+#define PCR_SYSTIMER_FUNC_CLK_EN_S  22
+
+/** PCR_TWAI0_CONF_REG register
+ *  TWAI0 configuration register
+ */
+#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x64)
+/** PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable twai0 apb clock
+ */
+#define PCR_TWAI0_CLK_EN    (BIT(0))
+#define PCR_TWAI0_CLK_EN_M  (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S)
+#define PCR_TWAI0_CLK_EN_V  0x00000001U
+#define PCR_TWAI0_CLK_EN_S  0
+/** PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset twai0 module
+ */
+#define PCR_TWAI0_RST_EN    (BIT(1))
+#define PCR_TWAI0_RST_EN_M  (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S)
+#define PCR_TWAI0_RST_EN_V  0x00000001U
+#define PCR_TWAI0_RST_EN_S  1
+/** PCR_TWAI0_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset twai0 module
+ */
+#define PCR_TWAI0_READY    (BIT(2))
+#define PCR_TWAI0_READY_M  (PCR_TWAI0_READY_V << PCR_TWAI0_READY_S)
+#define PCR_TWAI0_READY_V  0x00000001U
+#define PCR_TWAI0_READY_S  2
+
+/** PCR_TWAI0_FUNC_CLK_CONF_REG register
+ *  TWAI0_FUNC_CLK configuration register
+ */
+#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68)
+/** PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+ */
+#define PCR_TWAI0_FUNC_CLK_SEL    (BIT(20))
+#define PCR_TWAI0_FUNC_CLK_SEL_M  (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S)
+#define PCR_TWAI0_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_TWAI0_FUNC_CLK_SEL_S  20
+/** PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable twai0 function clock
+ */
+#define PCR_TWAI0_FUNC_CLK_EN    (BIT(22))
+#define PCR_TWAI0_FUNC_CLK_EN_M  (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S)
+#define PCR_TWAI0_FUNC_CLK_EN_V  0x00000001U
+#define PCR_TWAI0_FUNC_CLK_EN_S  22
+
+/** PCR_I2S_CONF_REG register
+ *  I2S configuration register
+ */
+#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c)
+/** PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable i2s apb clock
+ */
+#define PCR_I2S_CLK_EN    (BIT(0))
+#define PCR_I2S_CLK_EN_M  (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S)
+#define PCR_I2S_CLK_EN_V  0x00000001U
+#define PCR_I2S_CLK_EN_S  0
+/** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset i2s module
+ */
+#define PCR_I2S_RST_EN    (BIT(1))
+#define PCR_I2S_RST_EN_M  (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S)
+#define PCR_I2S_RST_EN_V  0x00000001U
+#define PCR_I2S_RST_EN_S  1
+/** PCR_I2S_RX_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field before using i2s rx function, after reset i2s module
+ */
+#define PCR_I2S_RX_READY    (BIT(2))
+#define PCR_I2S_RX_READY_M  (PCR_I2S_RX_READY_V << PCR_I2S_RX_READY_S)
+#define PCR_I2S_RX_READY_V  0x00000001U
+#define PCR_I2S_RX_READY_S  2
+/** PCR_I2S_TX_READY : RO; bitpos: [3]; default: 1;
+ *  Query this field before using i2s tx function, after reset i2s module
+ */
+#define PCR_I2S_TX_READY    (BIT(3))
+#define PCR_I2S_TX_READY_M  (PCR_I2S_TX_READY_V << PCR_I2S_TX_READY_S)
+#define PCR_I2S_TX_READY_V  0x00000001U
+#define PCR_I2S_TX_READY_S  3
+
+/** PCR_I2S_TX_CLKM_CONF_REG register
+ *  I2S_TX_CLKM configuration register
+ */
+#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70)
+/** PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
+ *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
+ *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
+ *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+ *  (n+1)-div] + y * (n+1)-div.
+ */
+#define PCR_I2S_TX_CLKM_DIV_NUM    0x000000FFU
+#define PCR_I2S_TX_CLKM_DIV_NUM_M  (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S)
+#define PCR_I2S_TX_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_I2S_TX_CLKM_DIV_NUM_S  12
+/** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+ *  I2S_MCLK_in.
+ */
+#define PCR_I2S_TX_CLKM_SEL    0x00000003U
+#define PCR_I2S_TX_CLKM_SEL_M  (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S)
+#define PCR_I2S_TX_CLKM_SEL_V  0x00000003U
+#define PCR_I2S_TX_CLKM_SEL_S  20
+/** PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2s_tx function clock
+ */
+#define PCR_I2S_TX_CLKM_EN    (BIT(22))
+#define PCR_I2S_TX_CLKM_EN_M  (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S)
+#define PCR_I2S_TX_CLKM_EN_V  0x00000001U
+#define PCR_I2S_TX_CLKM_EN_S  22
+
+/** PCR_I2S_TX_CLKM_DIV_CONF_REG register
+ *  I2S_TX_CLKM_DIV configuration register
+ */
+#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74)
+/** PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Z is (a-b).
+ */
+#define PCR_I2S_TX_CLKM_DIV_Z    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Z_M  (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S)
+#define PCR_I2S_TX_CLKM_DIV_Z_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Z_S  0
+/** PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define PCR_I2S_TX_CLKM_DIV_Y    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Y_M  (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S)
+#define PCR_I2S_TX_CLKM_DIV_Y_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_Y_S  9
+/** PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define PCR_I2S_TX_CLKM_DIV_X    0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_X_M  (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S)
+#define PCR_I2S_TX_CLKM_DIV_X_V  0x000001FFU
+#define PCR_I2S_TX_CLKM_DIV_X_S  18
+/** PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_TX_CLKM_DIV_YN1 is 1.
+ */
+#define PCR_I2S_TX_CLKM_DIV_YN1    (BIT(27))
+#define PCR_I2S_TX_CLKM_DIV_YN1_M  (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S)
+#define PCR_I2S_TX_CLKM_DIV_YN1_V  0x00000001U
+#define PCR_I2S_TX_CLKM_DIV_YN1_S  27
+
+/** PCR_I2S_RX_CLKM_CONF_REG register
+ *  I2S_RX_CLKM configuration register
+ */
+#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78)
+/** PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2;
+ *  Integral I2S clock divider value
+ */
+#define PCR_I2S_RX_CLKM_DIV_NUM    0x000000FFU
+#define PCR_I2S_RX_CLKM_DIV_NUM_M  (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S)
+#define PCR_I2S_RX_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_I2S_RX_CLKM_DIV_NUM_S  12
+/** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+ */
+#define PCR_I2S_RX_CLKM_SEL    0x00000003U
+#define PCR_I2S_RX_CLKM_SEL_M  (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S)
+#define PCR_I2S_RX_CLKM_SEL_V  0x00000003U
+#define PCR_I2S_RX_CLKM_SEL_S  20
+/** PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable i2s_rx function clock
+ */
+#define PCR_I2S_RX_CLKM_EN    (BIT(22))
+#define PCR_I2S_RX_CLKM_EN_M  (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S)
+#define PCR_I2S_RX_CLKM_EN_V  0x00000001U
+#define PCR_I2S_RX_CLKM_EN_S  22
+/** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0;
+ *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
+ */
+#define PCR_I2S_MCLK_SEL    (BIT(23))
+#define PCR_I2S_MCLK_SEL_M  (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S)
+#define PCR_I2S_MCLK_SEL_V  0x00000001U
+#define PCR_I2S_MCLK_SEL_S  23
+
+/** PCR_I2S_RX_CLKM_DIV_CONF_REG register
+ *  I2S_RX_CLKM_DIV configuration register
+ */
+#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c)
+/** PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Z is (a-b).
+ */
+#define PCR_I2S_RX_CLKM_DIV_Z    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Z_M  (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S)
+#define PCR_I2S_RX_CLKM_DIV_Z_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Z_S  0
+/** PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+ */
+#define PCR_I2S_RX_CLKM_DIV_Y    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Y_M  (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S)
+#define PCR_I2S_RX_CLKM_DIV_Y_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_Y_S  9
+/** PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+ *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+ */
+#define PCR_I2S_RX_CLKM_DIV_X    0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_X_M  (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S)
+#define PCR_I2S_RX_CLKM_DIV_X_V  0x000001FFU
+#define PCR_I2S_RX_CLKM_DIV_X_S  18
+/** PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+ *  I2S_RX_CLKM_DIV_YN1 is 1.
+ */
+#define PCR_I2S_RX_CLKM_DIV_YN1    (BIT(27))
+#define PCR_I2S_RX_CLKM_DIV_YN1_M  (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S)
+#define PCR_I2S_RX_CLKM_DIV_YN1_V  0x00000001U
+#define PCR_I2S_RX_CLKM_DIV_YN1_S  27
+
+/** PCR_SARADC_CONF_REG register
+ *  SARADC configuration register
+ */
+#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80)
+/** PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  no use
+ */
+#define PCR_SARADC_CLK_EN    (BIT(0))
+#define PCR_SARADC_CLK_EN_M  (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S)
+#define PCR_SARADC_CLK_EN_V  0x00000001U
+#define PCR_SARADC_CLK_EN_S  0
+/** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset function_register of saradc module
+ */
+#define PCR_SARADC_RST_EN    (BIT(1))
+#define PCR_SARADC_RST_EN_M  (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S)
+#define PCR_SARADC_RST_EN_V  0x00000001U
+#define PCR_SARADC_RST_EN_S  1
+/** PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable saradc apb clock
+ */
+#define PCR_SARADC_REG_CLK_EN    (BIT(2))
+#define PCR_SARADC_REG_CLK_EN_M  (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S)
+#define PCR_SARADC_REG_CLK_EN_V  0x00000001U
+#define PCR_SARADC_REG_CLK_EN_S  2
+/** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  Set 0 to reset apb_register of saradc module
+ */
+#define PCR_SARADC_REG_RST_EN    (BIT(3))
+#define PCR_SARADC_REG_RST_EN_M  (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S)
+#define PCR_SARADC_REG_RST_EN_V  0x00000001U
+#define PCR_SARADC_REG_RST_EN_S  3
+
+/** PCR_SARADC_CLKM_CONF_REG register
+ *  SARADC_CLKM configuration register
+ */
+#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84)
+/** PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_A    0x0000003FU
+#define PCR_SARADC_CLKM_DIV_A_M  (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S)
+#define PCR_SARADC_CLKM_DIV_A_V  0x0000003FU
+#define PCR_SARADC_CLKM_DIV_A_S  0
+/** PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_B    0x0000003FU
+#define PCR_SARADC_CLKM_DIV_B_M  (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S)
+#define PCR_SARADC_CLKM_DIV_B_V  0x0000003FU
+#define PCR_SARADC_CLKM_DIV_B_S  6
+/** PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
+ *  The integral part of the frequency divider factor of the saradc function clock.
+ */
+#define PCR_SARADC_CLKM_DIV_NUM    0x000000FFU
+#define PCR_SARADC_CLKM_DIV_NUM_M  (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S)
+#define PCR_SARADC_CLKM_DIV_NUM_V  0x000000FFU
+#define PCR_SARADC_CLKM_DIV_NUM_S  12
+/** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_SARADC_CLKM_SEL    0x00000003U
+#define PCR_SARADC_CLKM_SEL_M  (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S)
+#define PCR_SARADC_CLKM_SEL_V  0x00000003U
+#define PCR_SARADC_CLKM_SEL_S  20
+/** PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable saradc function clock
+ */
+#define PCR_SARADC_CLKM_EN    (BIT(22))
+#define PCR_SARADC_CLKM_EN_M  (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S)
+#define PCR_SARADC_CLKM_EN_V  0x00000001U
+#define PCR_SARADC_CLKM_EN_S  22
+
+/** PCR_TSENS_CLK_CONF_REG register
+ *  TSENS_CLK configuration register
+ */
+#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88)
+/** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
+ */
+#define PCR_TSENS_CLK_SEL    (BIT(20))
+#define PCR_TSENS_CLK_SEL_M  (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S)
+#define PCR_TSENS_CLK_SEL_V  0x00000001U
+#define PCR_TSENS_CLK_SEL_S  20
+/** PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable tsens clock
+ */
+#define PCR_TSENS_CLK_EN    (BIT(22))
+#define PCR_TSENS_CLK_EN_M  (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S)
+#define PCR_TSENS_CLK_EN_V  0x00000001U
+#define PCR_TSENS_CLK_EN_S  22
+/** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0;
+ *  Set 0 to reset tsens module
+ */
+#define PCR_TSENS_RST_EN    (BIT(23))
+#define PCR_TSENS_RST_EN_M  (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S)
+#define PCR_TSENS_RST_EN_V  0x00000001U
+#define PCR_TSENS_RST_EN_S  23
+
+/** PCR_USB_DEVICE_CONF_REG register
+ *  USB_DEVICE configuration register
+ */
+#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c)
+/** PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable usb_device clock
+ */
+#define PCR_USB_DEVICE_CLK_EN    (BIT(0))
+#define PCR_USB_DEVICE_CLK_EN_M  (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S)
+#define PCR_USB_DEVICE_CLK_EN_V  0x00000001U
+#define PCR_USB_DEVICE_CLK_EN_S  0
+/** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset usb_device module
+ */
+#define PCR_USB_DEVICE_RST_EN    (BIT(1))
+#define PCR_USB_DEVICE_RST_EN_M  (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S)
+#define PCR_USB_DEVICE_RST_EN_V  0x00000001U
+#define PCR_USB_DEVICE_RST_EN_S  1
+/** PCR_USB_DEVICE_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset usb_device module
+ */
+#define PCR_USB_DEVICE_READY    (BIT(2))
+#define PCR_USB_DEVICE_READY_M  (PCR_USB_DEVICE_READY_V << PCR_USB_DEVICE_READY_S)
+#define PCR_USB_DEVICE_READY_V  0x00000001U
+#define PCR_USB_DEVICE_READY_S  2
+
+/** PCR_INTMTX_CONF_REG register
+ *  INTMTX configuration register
+ */
+#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90)
+/** PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable intmtx clock
+ */
+#define PCR_INTMTX_CLK_EN    (BIT(0))
+#define PCR_INTMTX_CLK_EN_M  (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S)
+#define PCR_INTMTX_CLK_EN_V  0x00000001U
+#define PCR_INTMTX_CLK_EN_S  0
+/** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset intmtx module
+ */
+#define PCR_INTMTX_RST_EN    (BIT(1))
+#define PCR_INTMTX_RST_EN_M  (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S)
+#define PCR_INTMTX_RST_EN_V  0x00000001U
+#define PCR_INTMTX_RST_EN_S  1
+/** PCR_INTMTX_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset intmtx module
+ */
+#define PCR_INTMTX_READY    (BIT(2))
+#define PCR_INTMTX_READY_M  (PCR_INTMTX_READY_V << PCR_INTMTX_READY_S)
+#define PCR_INTMTX_READY_V  0x00000001U
+#define PCR_INTMTX_READY_S  2
+
+/** PCR_PCNT_CONF_REG register
+ *  PCNT configuration register
+ */
+#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94)
+/** PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable pcnt clock
+ */
+#define PCR_PCNT_CLK_EN    (BIT(0))
+#define PCR_PCNT_CLK_EN_M  (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S)
+#define PCR_PCNT_CLK_EN_V  0x00000001U
+#define PCR_PCNT_CLK_EN_S  0
+/** PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset pcnt module
+ */
+#define PCR_PCNT_RST_EN    (BIT(1))
+#define PCR_PCNT_RST_EN_M  (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S)
+#define PCR_PCNT_RST_EN_V  0x00000001U
+#define PCR_PCNT_RST_EN_S  1
+/** PCR_PCNT_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset pcnt module
+ */
+#define PCR_PCNT_READY    (BIT(2))
+#define PCR_PCNT_READY_M  (PCR_PCNT_READY_V << PCR_PCNT_READY_S)
+#define PCR_PCNT_READY_V  0x00000001U
+#define PCR_PCNT_READY_S  2
+
+/** PCR_ETM_CONF_REG register
+ *  ETM configuration register
+ */
+#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98)
+/** PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable etm clock
+ */
+#define PCR_ETM_CLK_EN    (BIT(0))
+#define PCR_ETM_CLK_EN_M  (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S)
+#define PCR_ETM_CLK_EN_V  0x00000001U
+#define PCR_ETM_CLK_EN_S  0
+/** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset etm module
+ */
+#define PCR_ETM_RST_EN    (BIT(1))
+#define PCR_ETM_RST_EN_M  (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S)
+#define PCR_ETM_RST_EN_V  0x00000001U
+#define PCR_ETM_RST_EN_S  1
+/** PCR_ETM_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset etm module
+ */
+#define PCR_ETM_READY    (BIT(2))
+#define PCR_ETM_READY_M  (PCR_ETM_READY_V << PCR_ETM_READY_S)
+#define PCR_ETM_READY_V  0x00000001U
+#define PCR_ETM_READY_S  2
+
+/** PCR_PWM_CONF_REG register
+ *  PWM configuration register
+ */
+#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c)
+/** PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable pwm clock
+ */
+#define PCR_PWM_CLK_EN    (BIT(0))
+#define PCR_PWM_CLK_EN_M  (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S)
+#define PCR_PWM_CLK_EN_V  0x00000001U
+#define PCR_PWM_CLK_EN_S  0
+/** PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset pwm module
+ */
+#define PCR_PWM_RST_EN    (BIT(1))
+#define PCR_PWM_RST_EN_M  (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S)
+#define PCR_PWM_RST_EN_V  0x00000001U
+#define PCR_PWM_RST_EN_S  1
+/** PCR_PWM_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset pwm module
+ */
+#define PCR_PWM_READY    (BIT(2))
+#define PCR_PWM_READY_M  (PCR_PWM_READY_V << PCR_PWM_READY_S)
+#define PCR_PWM_READY_V  0x00000001U
+#define PCR_PWM_READY_S  2
+
+/** PCR_PWM_CLK_CONF_REG register
+ *  PWM_CLK configuration register
+ */
+#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0)
+/** PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4;
+ *  The integral part of the frequency divider factor of the pwm function clock.
+ */
+#define PCR_PWM_DIV_NUM    0x000000FFU
+#define PCR_PWM_DIV_NUM_M  (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S)
+#define PCR_PWM_DIV_NUM_V  0x000000FFU
+#define PCR_PWM_DIV_NUM_S  12
+/** PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+ *  160MHz, 2: XTAL, 3: FOSC.
+ */
+#define PCR_PWM_CLKM_SEL    0x00000003U
+#define PCR_PWM_CLKM_SEL_M  (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S)
+#define PCR_PWM_CLKM_SEL_V  0x00000003U
+#define PCR_PWM_CLKM_SEL_S  20
+/** PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  set this field as 1 to activate pwm clkm.
+ */
+#define PCR_PWM_CLKM_EN    (BIT(22))
+#define PCR_PWM_CLKM_EN_M  (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S)
+#define PCR_PWM_CLKM_EN_V  0x00000001U
+#define PCR_PWM_CLKM_EN_S  22
+
+/** PCR_PARL_IO_CONF_REG register
+ *  PARL_IO configuration register
+ */
+#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4)
+/** PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable parl apb clock
+ */
+#define PCR_PARL_CLK_EN    (BIT(0))
+#define PCR_PARL_CLK_EN_M  (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S)
+#define PCR_PARL_CLK_EN_V  0x00000001U
+#define PCR_PARL_CLK_EN_S  0
+/** PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset parl apb reg
+ */
+#define PCR_PARL_RST_EN    (BIT(1))
+#define PCR_PARL_RST_EN_M  (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S)
+#define PCR_PARL_RST_EN_V  0x00000001U
+#define PCR_PARL_RST_EN_S  1
+/** PCR_PARL_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset parl module
+ */
+#define PCR_PARL_READY    (BIT(2))
+#define PCR_PARL_READY_M  (PCR_PARL_READY_V << PCR_PARL_READY_S)
+#define PCR_PARL_READY_V  0x00000001U
+#define PCR_PARL_READY_S  2
+
+/** PCR_PARL_CLK_RX_CONF_REG register
+ *  PARL_CLK_RX configuration register
+ */
+#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8)
+/** PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  The integral part of the frequency divider factor of the parl rx clock.
+ */
+#define PCR_PARL_CLK_RX_DIV_NUM    0x0000FFFFU
+#define PCR_PARL_CLK_RX_DIV_NUM_M  (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S)
+#define PCR_PARL_CLK_RX_DIV_NUM_V  0x0000FFFFU
+#define PCR_PARL_CLK_RX_DIV_NUM_S  0
+/** PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  user clock from pad.
+ */
+#define PCR_PARL_CLK_RX_SEL    0x00000003U
+#define PCR_PARL_CLK_RX_SEL_M  (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S)
+#define PCR_PARL_CLK_RX_SEL_V  0x00000003U
+#define PCR_PARL_CLK_RX_SEL_S  16
+/** PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1;
+ *  Set 1 to enable parl rx clock
+ */
+#define PCR_PARL_CLK_RX_EN    (BIT(18))
+#define PCR_PARL_CLK_RX_EN_M  (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S)
+#define PCR_PARL_CLK_RX_EN_V  0x00000001U
+#define PCR_PARL_CLK_RX_EN_S  18
+/** PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0;
+ *  Set 0 to reset parl rx module
+ */
+#define PCR_PARL_RX_RST_EN    (BIT(19))
+#define PCR_PARL_RX_RST_EN_M  (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S)
+#define PCR_PARL_RX_RST_EN_V  0x00000001U
+#define PCR_PARL_RX_RST_EN_S  19
+
+/** PCR_PARL_CLK_TX_CONF_REG register
+ *  PARL_CLK_TX configuration register
+ */
+#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac)
+/** PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  The integral part of the frequency divider factor of the parl tx clock.
+ */
+#define PCR_PARL_CLK_TX_DIV_NUM    0x0000FFFFU
+#define PCR_PARL_CLK_TX_DIV_NUM_M  (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S)
+#define PCR_PARL_CLK_TX_DIV_NUM_V  0x0000FFFFU
+#define PCR_PARL_CLK_TX_DIV_NUM_S  0
+/** PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+ *  user clock from pad.
+ */
+#define PCR_PARL_CLK_TX_SEL    0x00000003U
+#define PCR_PARL_CLK_TX_SEL_M  (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S)
+#define PCR_PARL_CLK_TX_SEL_V  0x00000003U
+#define PCR_PARL_CLK_TX_SEL_S  16
+/** PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1;
+ *  Set 1 to enable parl tx clock
+ */
+#define PCR_PARL_CLK_TX_EN    (BIT(18))
+#define PCR_PARL_CLK_TX_EN_M  (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S)
+#define PCR_PARL_CLK_TX_EN_V  0x00000001U
+#define PCR_PARL_CLK_TX_EN_S  18
+/** PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0;
+ *  Set 0 to reset parl tx module
+ */
+#define PCR_PARL_TX_RST_EN    (BIT(19))
+#define PCR_PARL_TX_RST_EN_M  (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S)
+#define PCR_PARL_TX_RST_EN_V  0x00000001U
+#define PCR_PARL_TX_RST_EN_S  19
+
+/** PCR_PVT_MONITOR_CONF_REG register
+ *  PVT_MONITOR configuration register
+ */
+#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb0)
+/** PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable apb clock of pvt module
+ */
+#define PCR_PVT_MONITOR_CLK_EN    (BIT(0))
+#define PCR_PVT_MONITOR_CLK_EN_M  (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S)
+#define PCR_PVT_MONITOR_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_CLK_EN_S  0
+/** PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset all pvt monitor module
+ */
+#define PCR_PVT_MONITOR_RST_EN    (BIT(1))
+#define PCR_PVT_MONITOR_RST_EN_M  (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S)
+#define PCR_PVT_MONITOR_RST_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_RST_EN_S  1
+/** PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable function clock of modem pvt module
+ */
+#define PCR_PVT_MONITOR_SITE1_CLK_EN    (BIT(2))
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_M  (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE1_CLK_EN_S  2
+/** PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to enable function clock of cpu pvt module
+ */
+#define PCR_PVT_MONITOR_SITE2_CLK_EN    (BIT(3))
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_M  (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE2_CLK_EN_S  3
+/** PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  Set 1 to enable function clock of hp_peri pvt module
+ */
+#define PCR_PVT_MONITOR_SITE3_CLK_EN    (BIT(4))
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_M  (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S)
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_SITE3_CLK_EN_S  4
+
+/** PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register
+ *  PVT_MONITOR function clock configuration register
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb4)
+/** PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0;
+ *  The integral part of the frequency divider factor of the pvt_monitor function clock.
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM    0x0000000FU
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M  (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V  0x0000000FU
+#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S  0
+/** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
+ *  divided by 3.
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL    (BIT(20))
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M  (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V  0x00000001U
+#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S  20
+/** PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable source clock of pvt sitex
+ */
+#define PCR_PVT_MONITOR_FUNC_CLK_EN    (BIT(22))
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_M  (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S)
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_V  0x00000001U
+#define PCR_PVT_MONITOR_FUNC_CLK_EN_S  22
+
+/** PCR_GDMA_CONF_REG register
+ *  GDMA configuration register
+ */
+#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xb8)
+/** PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable gdma clock
+ */
+#define PCR_GDMA_CLK_EN    (BIT(0))
+#define PCR_GDMA_CLK_EN_M  (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S)
+#define PCR_GDMA_CLK_EN_V  0x00000001U
+#define PCR_GDMA_CLK_EN_S  0
+/** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset gdma module
+ */
+#define PCR_GDMA_RST_EN    (BIT(1))
+#define PCR_GDMA_RST_EN_M  (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S)
+#define PCR_GDMA_RST_EN_V  0x00000001U
+#define PCR_GDMA_RST_EN_S  1
+
+/** PCR_SPI2_CONF_REG register
+ *  SPI2 configuration register
+ */
+#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xbc)
+/** PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable spi2 apb clock
+ */
+#define PCR_SPI2_CLK_EN    (BIT(0))
+#define PCR_SPI2_CLK_EN_M  (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S)
+#define PCR_SPI2_CLK_EN_V  0x00000001U
+#define PCR_SPI2_CLK_EN_S  0
+/** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset spi2 module
+ */
+#define PCR_SPI2_RST_EN    (BIT(1))
+#define PCR_SPI2_RST_EN_M  (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S)
+#define PCR_SPI2_RST_EN_V  0x00000001U
+#define PCR_SPI2_RST_EN_S  1
+/** PCR_SPI2_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset spi2 module
+ */
+#define PCR_SPI2_READY    (BIT(2))
+#define PCR_SPI2_READY_M  (PCR_SPI2_READY_V << PCR_SPI2_READY_S)
+#define PCR_SPI2_READY_V  0x00000001U
+#define PCR_SPI2_READY_S  2
+
+/** PCR_SPI2_CLKM_CONF_REG register
+ *  SPI2_CLKM configuration register
+ */
+#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc0)
+/** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+ *  reserved.
+ */
+#define PCR_SPI2_CLKM_SEL    0x00000003U
+#define PCR_SPI2_CLKM_SEL_M  (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S)
+#define PCR_SPI2_CLKM_SEL_V  0x00000003U
+#define PCR_SPI2_CLKM_SEL_S  20
+/** PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable spi2 function clock
+ */
+#define PCR_SPI2_CLKM_EN    (BIT(22))
+#define PCR_SPI2_CLKM_EN_M  (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S)
+#define PCR_SPI2_CLKM_EN_V  0x00000001U
+#define PCR_SPI2_CLKM_EN_S  22
+
+/** PCR_AES_CONF_REG register
+ *  AES configuration register
+ */
+#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc4)
+/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable aes clock
+ */
+#define PCR_AES_CLK_EN    (BIT(0))
+#define PCR_AES_CLK_EN_M  (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
+#define PCR_AES_CLK_EN_V  0x00000001U
+#define PCR_AES_CLK_EN_S  0
+/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset aes module
+ */
+#define PCR_AES_RST_EN    (BIT(1))
+#define PCR_AES_RST_EN_M  (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
+#define PCR_AES_RST_EN_V  0x00000001U
+#define PCR_AES_RST_EN_S  1
+/** PCR_AES_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset aes module
+ */
+#define PCR_AES_READY    (BIT(2))
+#define PCR_AES_READY_M  (PCR_AES_READY_V << PCR_AES_READY_S)
+#define PCR_AES_READY_V  0x00000001U
+#define PCR_AES_READY_S  2
+
+/** PCR_SHA_CONF_REG register
+ *  SHA configuration register
+ */
+#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xc8)
+/** PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable sha clock
+ */
+#define PCR_SHA_CLK_EN    (BIT(0))
+#define PCR_SHA_CLK_EN_M  (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S)
+#define PCR_SHA_CLK_EN_V  0x00000001U
+#define PCR_SHA_CLK_EN_S  0
+/** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset sha module
+ */
+#define PCR_SHA_RST_EN    (BIT(1))
+#define PCR_SHA_RST_EN_M  (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S)
+#define PCR_SHA_RST_EN_V  0x00000001U
+#define PCR_SHA_RST_EN_S  1
+/** PCR_SHA_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset sha module
+ */
+#define PCR_SHA_READY    (BIT(2))
+#define PCR_SHA_READY_M  (PCR_SHA_READY_V << PCR_SHA_READY_S)
+#define PCR_SHA_READY_V  0x00000001U
+#define PCR_SHA_READY_S  2
+
+/** PCR_RSA_CONF_REG register
+ *  RSA configuration register
+ */
+#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xcc)
+/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable rsa clock
+ */
+#define PCR_RSA_CLK_EN    (BIT(0))
+#define PCR_RSA_CLK_EN_M  (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
+#define PCR_RSA_CLK_EN_V  0x00000001U
+#define PCR_RSA_CLK_EN_S  0
+/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset rsa module
+ */
+#define PCR_RSA_RST_EN    (BIT(1))
+#define PCR_RSA_RST_EN_M  (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
+#define PCR_RSA_RST_EN_V  0x00000001U
+#define PCR_RSA_RST_EN_S  1
+/** PCR_RSA_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset rsa module
+ */
+#define PCR_RSA_READY    (BIT(2))
+#define PCR_RSA_READY_M  (PCR_RSA_READY_V << PCR_RSA_READY_S)
+#define PCR_RSA_READY_V  0x00000001U
+#define PCR_RSA_READY_S  2
+
+/** PCR_RSA_PD_CTRL_REG register
+ *  RSA power control register
+ */
+#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd0)
+/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down rsa internal memory.
+ */
+#define PCR_RSA_MEM_PD    (BIT(0))
+#define PCR_RSA_MEM_PD_M  (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
+#define PCR_RSA_MEM_PD_V  0x00000001U
+#define PCR_RSA_MEM_PD_S  0
+/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up rsa internal memory
+ */
+#define PCR_RSA_MEM_FORCE_PU    (BIT(1))
+#define PCR_RSA_MEM_FORCE_PU_M  (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
+#define PCR_RSA_MEM_FORCE_PU_V  0x00000001U
+#define PCR_RSA_MEM_FORCE_PU_S  1
+/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down rsa internal memory.
+ */
+#define PCR_RSA_MEM_FORCE_PD    (BIT(2))
+#define PCR_RSA_MEM_FORCE_PD_M  (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
+#define PCR_RSA_MEM_FORCE_PD_V  0x00000001U
+#define PCR_RSA_MEM_FORCE_PD_S  2
+
+/** PCR_ECC_CONF_REG register
+ *  ECC configuration register
+ */
+#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd4)
+/** PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ecc clock
+ */
+#define PCR_ECC_CLK_EN    (BIT(0))
+#define PCR_ECC_CLK_EN_M  (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S)
+#define PCR_ECC_CLK_EN_V  0x00000001U
+#define PCR_ECC_CLK_EN_S  0
+/** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ecc module
+ */
+#define PCR_ECC_RST_EN    (BIT(1))
+#define PCR_ECC_RST_EN_M  (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S)
+#define PCR_ECC_RST_EN_V  0x00000001U
+#define PCR_ECC_RST_EN_S  1
+/** PCR_ECC_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset ecc module
+ */
+#define PCR_ECC_READY    (BIT(2))
+#define PCR_ECC_READY_M  (PCR_ECC_READY_V << PCR_ECC_READY_S)
+#define PCR_ECC_READY_V  0x00000001U
+#define PCR_ECC_READY_S  2
+
+/** PCR_ECC_PD_CTRL_REG register
+ *  ECC power control register
+ */
+#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd8)
+/** PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down ecc internal memory.
+ */
+#define PCR_ECC_MEM_PD    (BIT(0))
+#define PCR_ECC_MEM_PD_M  (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S)
+#define PCR_ECC_MEM_PD_V  0x00000001U
+#define PCR_ECC_MEM_PD_S  0
+/** PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up ecc internal memory
+ */
+#define PCR_ECC_MEM_FORCE_PU    (BIT(1))
+#define PCR_ECC_MEM_FORCE_PU_M  (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S)
+#define PCR_ECC_MEM_FORCE_PU_V  0x00000001U
+#define PCR_ECC_MEM_FORCE_PU_S  1
+/** PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down ecc internal memory.
+ */
+#define PCR_ECC_MEM_FORCE_PD    (BIT(2))
+#define PCR_ECC_MEM_FORCE_PD_M  (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S)
+#define PCR_ECC_MEM_FORCE_PD_V  0x00000001U
+#define PCR_ECC_MEM_FORCE_PD_S  2
+
+/** PCR_DS_CONF_REG register
+ *  DS configuration register
+ */
+#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xdc)
+/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ds clock
+ */
+#define PCR_DS_CLK_EN    (BIT(0))
+#define PCR_DS_CLK_EN_M  (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
+#define PCR_DS_CLK_EN_V  0x00000001U
+#define PCR_DS_CLK_EN_S  0
+/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ds module
+ */
+#define PCR_DS_RST_EN    (BIT(1))
+#define PCR_DS_RST_EN_M  (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
+#define PCR_DS_RST_EN_V  0x00000001U
+#define PCR_DS_RST_EN_S  1
+/** PCR_DS_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset ds module
+ */
+#define PCR_DS_READY    (BIT(2))
+#define PCR_DS_READY_M  (PCR_DS_READY_V << PCR_DS_READY_S)
+#define PCR_DS_READY_V  0x00000001U
+#define PCR_DS_READY_S  2
+
+/** PCR_HMAC_CONF_REG register
+ *  HMAC configuration register
+ */
+#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe0)
+/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable hmac clock
+ */
+#define PCR_HMAC_CLK_EN    (BIT(0))
+#define PCR_HMAC_CLK_EN_M  (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
+#define PCR_HMAC_CLK_EN_V  0x00000001U
+#define PCR_HMAC_CLK_EN_S  0
+/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset hmac module
+ */
+#define PCR_HMAC_RST_EN    (BIT(1))
+#define PCR_HMAC_RST_EN_M  (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
+#define PCR_HMAC_RST_EN_V  0x00000001U
+#define PCR_HMAC_RST_EN_S  1
+/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset hmac module
+ */
+#define PCR_HMAC_READY    (BIT(2))
+#define PCR_HMAC_READY_M  (PCR_HMAC_READY_V << PCR_HMAC_READY_S)
+#define PCR_HMAC_READY_V  0x00000001U
+#define PCR_HMAC_READY_S  2
+
+/** PCR_ECDSA_CONF_REG register
+ *  ECDSA configuration register
+ */
+#define PCR_ECDSA_CONF_REG (DR_REG_PCR_BASE + 0xe4)
+/** PCR_ECDSA_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable ecdsa clock
+ */
+#define PCR_ECDSA_CLK_EN    (BIT(0))
+#define PCR_ECDSA_CLK_EN_M  (PCR_ECDSA_CLK_EN_V << PCR_ECDSA_CLK_EN_S)
+#define PCR_ECDSA_CLK_EN_V  0x00000001U
+#define PCR_ECDSA_CLK_EN_S  0
+/** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset ecdsa module
+ */
+#define PCR_ECDSA_RST_EN    (BIT(1))
+#define PCR_ECDSA_RST_EN_M  (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S)
+#define PCR_ECDSA_RST_EN_V  0x00000001U
+#define PCR_ECDSA_RST_EN_S  1
+/** PCR_ECDSA_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset ecdsa module
+ */
+#define PCR_ECDSA_READY    (BIT(2))
+#define PCR_ECDSA_READY_M  (PCR_ECDSA_READY_V << PCR_ECDSA_READY_S)
+#define PCR_ECDSA_READY_V  0x00000001U
+#define PCR_ECDSA_READY_S  2
+
+/** PCR_IOMUX_CONF_REG register
+ *  IOMUX configuration register
+ */
+#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8)
+/** PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable iomux apb clock
+ */
+#define PCR_IOMUX_CLK_EN    (BIT(0))
+#define PCR_IOMUX_CLK_EN_M  (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S)
+#define PCR_IOMUX_CLK_EN_V  0x00000001U
+#define PCR_IOMUX_CLK_EN_S  0
+/** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset iomux module
+ */
+#define PCR_IOMUX_RST_EN    (BIT(1))
+#define PCR_IOMUX_RST_EN_M  (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S)
+#define PCR_IOMUX_RST_EN_V  0x00000001U
+#define PCR_IOMUX_RST_EN_S  1
+
+/** PCR_IOMUX_CLK_CONF_REG register
+ *  IOMUX_CLK configuration register
+ */
+#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec)
+/** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+ *  FOSC, 3(default): XTAL.
+ */
+#define PCR_IOMUX_FUNC_CLK_SEL    0x00000003U
+#define PCR_IOMUX_FUNC_CLK_SEL_M  (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S)
+#define PCR_IOMUX_FUNC_CLK_SEL_V  0x00000003U
+#define PCR_IOMUX_FUNC_CLK_SEL_S  20
+/** PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set 1 to enable iomux function clock
+ */
+#define PCR_IOMUX_FUNC_CLK_EN    (BIT(22))
+#define PCR_IOMUX_FUNC_CLK_EN_M  (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S)
+#define PCR_IOMUX_FUNC_CLK_EN_V  0x00000001U
+#define PCR_IOMUX_FUNC_CLK_EN_S  22
+
+/** PCR_MEM_MONITOR_CONF_REG register
+ *  MEM_MONITOR configuration register
+ */
+#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0)
+/** PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable mem_monitor clock
+ */
+#define PCR_MEM_MONITOR_CLK_EN    (BIT(0))
+#define PCR_MEM_MONITOR_CLK_EN_M  (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S)
+#define PCR_MEM_MONITOR_CLK_EN_V  0x00000001U
+#define PCR_MEM_MONITOR_CLK_EN_S  0
+/** PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset mem_monitor module
+ */
+#define PCR_MEM_MONITOR_RST_EN    (BIT(1))
+#define PCR_MEM_MONITOR_RST_EN_M  (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S)
+#define PCR_MEM_MONITOR_RST_EN_V  0x00000001U
+#define PCR_MEM_MONITOR_RST_EN_S  1
+/** PCR_MEM_MONITOR_READY : RO; bitpos: [2]; default: 1;
+ *  Query this field after reset mem_monitor module
+ */
+#define PCR_MEM_MONITOR_READY    (BIT(2))
+#define PCR_MEM_MONITOR_READY_M  (PCR_MEM_MONITOR_READY_V << PCR_MEM_MONITOR_READY_S)
+#define PCR_MEM_MONITOR_READY_V  0x00000001U
+#define PCR_MEM_MONITOR_READY_S  2
+
+/** PCR_REGDMA_CONF_REG register
+ *  REGDMA configuration register
+ */
+#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4)
+/** PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable regdma clock
+ */
+#define PCR_REGDMA_CLK_EN    (BIT(0))
+#define PCR_REGDMA_CLK_EN_M  (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S)
+#define PCR_REGDMA_CLK_EN_V  0x00000001U
+#define PCR_REGDMA_CLK_EN_S  0
+/** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset regdma module
+ */
+#define PCR_REGDMA_RST_EN    (BIT(1))
+#define PCR_REGDMA_RST_EN_M  (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S)
+#define PCR_REGDMA_RST_EN_V  0x00000001U
+#define PCR_REGDMA_RST_EN_S  1
+
+/** PCR_TRACE_CONF_REG register
+ *  TRACE configuration register
+ */
+#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xf8)
+/** PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable trace clock
+ */
+#define PCR_TRACE_CLK_EN    (BIT(0))
+#define PCR_TRACE_CLK_EN_M  (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S)
+#define PCR_TRACE_CLK_EN_V  0x00000001U
+#define PCR_TRACE_CLK_EN_S  0
+/** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset trace module
+ */
+#define PCR_TRACE_RST_EN    (BIT(1))
+#define PCR_TRACE_RST_EN_M  (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S)
+#define PCR_TRACE_RST_EN_V  0x00000001U
+#define PCR_TRACE_RST_EN_S  1
+
+/** PCR_ASSIST_CONF_REG register
+ *  ASSIST configuration register
+ */
+#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0xfc)
+/** PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable assist clock
+ */
+#define PCR_ASSIST_CLK_EN    (BIT(0))
+#define PCR_ASSIST_CLK_EN_M  (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S)
+#define PCR_ASSIST_CLK_EN_V  0x00000001U
+#define PCR_ASSIST_CLK_EN_S  0
+/** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset assist module
+ */
+#define PCR_ASSIST_RST_EN    (BIT(1))
+#define PCR_ASSIST_RST_EN_M  (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S)
+#define PCR_ASSIST_RST_EN_V  0x00000001U
+#define PCR_ASSIST_RST_EN_S  1
+
+/** PCR_CACHE_CONF_REG register
+ *  CACHE configuration register
+ */
+#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x100)
+/** PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable cache clock
+ */
+#define PCR_CACHE_CLK_EN    (BIT(0))
+#define PCR_CACHE_CLK_EN_M  (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S)
+#define PCR_CACHE_CLK_EN_V  0x00000001U
+#define PCR_CACHE_CLK_EN_S  0
+/** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset cache module
+ */
+#define PCR_CACHE_RST_EN    (BIT(1))
+#define PCR_CACHE_RST_EN_M  (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S)
+#define PCR_CACHE_RST_EN_V  0x00000001U
+#define PCR_CACHE_RST_EN_S  1
+
+/** PCR_MODEM_CONF_REG register
+ *  MODEM_APB configuration register
+ */
+#define PCR_MODEM_CONF_REG (DR_REG_PCR_BASE + 0x104)
+/** PCR_MODEM_CLK_SEL : R/W; bitpos: [0]; default: 0;
+ *  xxxx
+ */
+#define PCR_MODEM_CLK_SEL    (BIT(0))
+#define PCR_MODEM_CLK_SEL_M  (PCR_MODEM_CLK_SEL_V << PCR_MODEM_CLK_SEL_S)
+#define PCR_MODEM_CLK_SEL_V  0x00000001U
+#define PCR_MODEM_CLK_SEL_S  0
+/** PCR_MODEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  xxxx
+ */
+#define PCR_MODEM_CLK_EN    (BIT(1))
+#define PCR_MODEM_CLK_EN_M  (PCR_MODEM_CLK_EN_V << PCR_MODEM_CLK_EN_S)
+#define PCR_MODEM_CLK_EN_V  0x00000001U
+#define PCR_MODEM_CLK_EN_S  1
+/** PCR_MODEM_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this file as 1 to reset modem-subsystem.
+ */
+#define PCR_MODEM_RST_EN    (BIT(2))
+#define PCR_MODEM_RST_EN_M  (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S)
+#define PCR_MODEM_RST_EN_V  0x00000001U
+#define PCR_MODEM_RST_EN_S  2
+
+/** PCR_TIMEOUT_CONF_REG register
+ *  TIMEOUT configuration register
+ */
+#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x108)
+/** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 0 to reset cpu_peri timeout module
+ */
+#define PCR_CPU_TIMEOUT_RST_EN    (BIT(1))
+#define PCR_CPU_TIMEOUT_RST_EN_M  (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S)
+#define PCR_CPU_TIMEOUT_RST_EN_V  0x00000001U
+#define PCR_CPU_TIMEOUT_RST_EN_S  1
+/** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
+ */
+#define PCR_HP_TIMEOUT_RST_EN    (BIT(2))
+#define PCR_HP_TIMEOUT_RST_EN_M  (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S)
+#define PCR_HP_TIMEOUT_RST_EN_V  0x00000001U
+#define PCR_HP_TIMEOUT_RST_EN_S  2
+
+/** PCR_SYSCLK_CONF_REG register
+ *  SYSCLK configuration register
+ */
+#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x10c)
+/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0;
+ *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
+ *  clock-source such as XTAL/FOSC.
+ */
+#define PCR_LS_DIV_NUM    0x000000FFU
+#define PCR_LS_DIV_NUM_M  (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S)
+#define PCR_LS_DIV_NUM_V  0x000000FFU
+#define PCR_LS_DIV_NUM_S  0
+/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2;
+ *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
+ */
+#define PCR_HS_DIV_NUM    0x000000FFU
+#define PCR_HS_DIV_NUM_M  (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S)
+#define PCR_HS_DIV_NUM_V  0x000000FFU
+#define PCR_HS_DIV_NUM_S  8
+/** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0;
+ *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
+ */
+#define PCR_SOC_CLK_SEL    0x00000003U
+#define PCR_SOC_CLK_SEL_M  (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S)
+#define PCR_SOC_CLK_SEL_V  0x00000003U
+#define PCR_SOC_CLK_SEL_S  16
+/** PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 32;
+ *  This field indicates the frequency(MHz) of XTAL.
+ */
+#define PCR_CLK_XTAL_FREQ    0x0000007FU
+#define PCR_CLK_XTAL_FREQ_M  (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S)
+#define PCR_CLK_XTAL_FREQ_V  0x0000007FU
+#define PCR_CLK_XTAL_FREQ_S  24
+
+/** PCR_CPU_WAITI_CONF_REG register
+ *  CPU_WAITI configuration register
+ */
+#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x110)
+/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1;
+ *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
+ */
+#define PCR_CPUPERIOD_SEL    0x00000003U
+#define PCR_CPUPERIOD_SEL_M  (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S)
+#define PCR_CPUPERIOD_SEL_V  0x00000003U
+#define PCR_CPUPERIOD_SEL_S  0
+/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1;
+ *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
+ */
+#define PCR_PLL_FREQ_SEL    (BIT(2))
+#define PCR_PLL_FREQ_SEL_M  (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S)
+#define PCR_PLL_FREQ_SEL_V  0x00000001U
+#define PCR_PLL_FREQ_SEL_S  2
+/** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to force cpu_waiti_clk enable.
+ */
+#define PCR_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
+#define PCR_CPU_WAIT_MODE_FORCE_ON_M  (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S)
+#define PCR_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
+#define PCR_CPU_WAIT_MODE_FORCE_ON_S  3
+/** PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
+ *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+ *  will close
+ */
+#define PCR_CPU_WAITI_DELAY_NUM    0x0000000FU
+#define PCR_CPU_WAITI_DELAY_NUM_M  (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S)
+#define PCR_CPU_WAITI_DELAY_NUM_V  0x0000000FU
+#define PCR_CPU_WAITI_DELAY_NUM_S  4
+
+/** PCR_CPU_FREQ_CONF_REG register
+ *  CPU_FREQ configuration register
+ */
+#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x114)
+/** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is
+ *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
+ *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
+ */
+#define PCR_CPU_DIV_NUM    0x000000FFU
+#define PCR_CPU_DIV_NUM_M  (PCR_CPU_DIV_NUM_V << PCR_CPU_DIV_NUM_S)
+#define PCR_CPU_DIV_NUM_V  0x000000FFU
+#define PCR_CPU_DIV_NUM_S  0
+
+/** PCR_AHB_FREQ_CONF_REG register
+ *  AHB_FREQ configuration register
+ */
+#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118)
+/** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is
+ *  div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
+ *  low-speed clock-source such as XTAL/FOSC, and should be used together with
+ *  PCR_CPU_DIV_NUM.
+ */
+#define PCR_AHB_DIV_NUM    0x000000FFU
+#define PCR_AHB_DIV_NUM_M  (PCR_AHB_DIV_NUM_V << PCR_AHB_DIV_NUM_S)
+#define PCR_AHB_DIV_NUM_V  0x000000FFU
+#define PCR_AHB_DIV_NUM_S  0
+
+/** PCR_APB_FREQ_CONF_REG register
+ *  APB_FREQ configuration register
+ */
+#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c)
+/** PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
+ *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
+ *  recover to the previous frequency when a new access appears on apb-bus. Set as one
+ *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
+ *  that enable this function will reduce performance. Users can set this field as zero
+ *  to disable the auto-decrease-apb-freq function. By default, this function is
+ *  disable.
+ */
+#define PCR_APB_DECREASE_DIV_NUM    0x000000FFU
+#define PCR_APB_DECREASE_DIV_NUM_M  (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S)
+#define PCR_APB_DECREASE_DIV_NUM_V  0x000000FFU
+#define PCR_APB_DECREASE_DIV_NUM_S  0
+/** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
+ *  div1(default)/div2/div4 of clk_ahb.
+ */
+#define PCR_APB_DIV_NUM    0x000000FFU
+#define PCR_APB_DIV_NUM_M  (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S)
+#define PCR_APB_DIV_NUM_V  0x000000FFU
+#define PCR_APB_DIV_NUM_S  8
+
+/** PCR_SYSCLK_FREQ_QUERY_0_REG register
+ *  SYSCLK frequency query 0 register
+ */
+#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x120)
+/** PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 8;
+ *  This field indicates the frequency(MHz) of FOSC.
+ */
+#define PCR_FOSC_FREQ    0x000000FFU
+#define PCR_FOSC_FREQ_M  (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S)
+#define PCR_FOSC_FREQ_V  0x000000FFU
+#define PCR_FOSC_FREQ_S  0
+/** PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 96;
+ *  This field indicates the frequency(MHz) of SPLL.
+ */
+#define PCR_PLL_FREQ    0x000003FFU
+#define PCR_PLL_FREQ_M  (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S)
+#define PCR_PLL_FREQ_V  0x000003FFU
+#define PCR_PLL_FREQ_S  8
+
+/** PCR_PLL_DIV_CLK_EN_REG register
+ *  SPLL DIV clock-gating configuration register
+ */
+#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x124)
+/** PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  This field is used to open 96 MHz clock (SPLL) driven from SPLL. 0: close, 1:
+ *  open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_240M_CLK_EN    (BIT(0))
+#define PCR_PLL_240M_CLK_EN_M  (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S)
+#define PCR_PLL_240M_CLK_EN_V  0x00000001U
+#define PCR_PLL_240M_CLK_EN_S  0
+/** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  This field is used to open 64 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_160M_CLK_EN    (BIT(1))
+#define PCR_PLL_160M_CLK_EN_M  (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S)
+#define PCR_PLL_160M_CLK_EN_V  0x00000001U
+#define PCR_PLL_160M_CLK_EN_S  1
+/** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  This field is used to open 48 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_120M_CLK_EN    (BIT(2))
+#define PCR_PLL_120M_CLK_EN_M  (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S)
+#define PCR_PLL_120M_CLK_EN_V  0x00000001U
+#define PCR_PLL_120M_CLK_EN_S  2
+/** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  This field is used to open 32 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_80M_CLK_EN    (BIT(3))
+#define PCR_PLL_80M_CLK_EN_M  (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S)
+#define PCR_PLL_80M_CLK_EN_V  0x00000001U
+#define PCR_PLL_80M_CLK_EN_S  3
+/** PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  This field is used to open 16 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_48M_CLK_EN    (BIT(4))
+#define PCR_PLL_48M_CLK_EN_M  (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S)
+#define PCR_PLL_48M_CLK_EN_V  0x00000001U
+#define PCR_PLL_48M_CLK_EN_S  4
+/** PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  This field is used to open 8 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+ *  1: open(default). Only available when high-speed clock-source SPLL is active.
+ */
+#define PCR_PLL_40M_CLK_EN    (BIT(5))
+#define PCR_PLL_40M_CLK_EN_M  (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S)
+#define PCR_PLL_40M_CLK_EN_V  0x00000001U
+#define PCR_PLL_40M_CLK_EN_S  5
+
+/** PCR_CTRL_CLK_OUT_EN_REG register
+ *  CLK_OUT_EN configuration register
+ */
+#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x128)
+/** PCR_CLK8_OEN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to enable 8m clock
+ */
+#define PCR_CLK8_OEN    (BIT(0))
+#define PCR_CLK8_OEN_M  (PCR_CLK8_OEN_V << PCR_CLK8_OEN_S)
+#define PCR_CLK8_OEN_V  0x00000001U
+#define PCR_CLK8_OEN_S  0
+/** PCR_CLK16_OEN : R/W; bitpos: [1]; default: 1;
+ *  Set 1 to enable 16m clock
+ */
+#define PCR_CLK16_OEN    (BIT(1))
+#define PCR_CLK16_OEN_M  (PCR_CLK16_OEN_V << PCR_CLK16_OEN_S)
+#define PCR_CLK16_OEN_V  0x00000001U
+#define PCR_CLK16_OEN_S  1
+/** PCR_CLK32_OEN : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to enable 32m clock
+ */
+#define PCR_CLK32_OEN    (BIT(2))
+#define PCR_CLK32_OEN_M  (PCR_CLK32_OEN_V << PCR_CLK32_OEN_S)
+#define PCR_CLK32_OEN_V  0x00000001U
+#define PCR_CLK32_OEN_S  2
+/** PCR_CLK_ADC_INF_OEN : R/W; bitpos: [3]; default: 1;
+ *  Reserved
+ */
+#define PCR_CLK_ADC_INF_OEN    (BIT(3))
+#define PCR_CLK_ADC_INF_OEN_M  (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S)
+#define PCR_CLK_ADC_INF_OEN_V  0x00000001U
+#define PCR_CLK_ADC_INF_OEN_S  3
+/** PCR_CLK_DFM_INF_OEN : R/W; bitpos: [4]; default: 1;
+ *  Reserved
+ */
+#define PCR_CLK_DFM_INF_OEN    (BIT(4))
+#define PCR_CLK_DFM_INF_OEN_M  (PCR_CLK_DFM_INF_OEN_V << PCR_CLK_DFM_INF_OEN_S)
+#define PCR_CLK_DFM_INF_OEN_V  0x00000001U
+#define PCR_CLK_DFM_INF_OEN_S  4
+/** PCR_CLK_SDM_MOD_OEN : R/W; bitpos: [5]; default: 1;
+ *  Reserved
+ */
+#define PCR_CLK_SDM_MOD_OEN    (BIT(5))
+#define PCR_CLK_SDM_MOD_OEN_M  (PCR_CLK_SDM_MOD_OEN_V << PCR_CLK_SDM_MOD_OEN_S)
+#define PCR_CLK_SDM_MOD_OEN_V  0x00000001U
+#define PCR_CLK_SDM_MOD_OEN_S  5
+/** PCR_CLK_XTAL_OEN : R/W; bitpos: [6]; default: 1;
+ *  Set 1 to enable xtal clock
+ */
+#define PCR_CLK_XTAL_OEN    (BIT(6))
+#define PCR_CLK_XTAL_OEN_M  (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S)
+#define PCR_CLK_XTAL_OEN_V  0x00000001U
+#define PCR_CLK_XTAL_OEN_S  6
+
+/** PCR_CTRL_TICK_CONF_REG register
+ *  TICK configuration register
+ */
+#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x12c)
+/** PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39;
+ *  ******* Description ***********
+ */
+#define PCR_XTAL_TICK_NUM    0x000000FFU
+#define PCR_XTAL_TICK_NUM_M  (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S)
+#define PCR_XTAL_TICK_NUM_V  0x000000FFU
+#define PCR_XTAL_TICK_NUM_S  0
+/** PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7;
+ *  ******* Description ***********
+ */
+#define PCR_FOSC_TICK_NUM    0x000000FFU
+#define PCR_FOSC_TICK_NUM_M  (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S)
+#define PCR_FOSC_TICK_NUM_V  0x000000FFU
+#define PCR_FOSC_TICK_NUM_S  8
+/** PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1;
+ *  ******* Description ***********
+ */
+#define PCR_TICK_ENABLE    (BIT(16))
+#define PCR_TICK_ENABLE_M  (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S)
+#define PCR_TICK_ENABLE_V  0x00000001U
+#define PCR_TICK_ENABLE_S  16
+/** PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0;
+ *  ******* Description ***********
+ */
+#define PCR_RST_TICK_CNT    (BIT(17))
+#define PCR_RST_TICK_CNT_M  (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S)
+#define PCR_RST_TICK_CNT_V  0x00000001U
+#define PCR_RST_TICK_CNT_S  17
+
+/** PCR_CTRL_32K_CONF_REG register
+ *  32KHz clock configuration register
+ */
+#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x130)
+/** PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  This field indicates which one 32KHz clock will be used by timergroup. 0:
+ *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
+ */
+#define PCR_32K_SEL    0x00000003U
+#define PCR_32K_SEL_M  (PCR_32K_SEL_V << PCR_32K_SEL_S)
+#define PCR_32K_SEL_V  0x00000003U
+#define PCR_32K_SEL_S  0
+/** PCR_32K_MODEM_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0:
+ *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
+ */
+#define PCR_32K_MODEM_SEL    0x00000003U
+#define PCR_32K_MODEM_SEL_M  (PCR_32K_MODEM_SEL_V << PCR_32K_MODEM_SEL_S)
+#define PCR_32K_MODEM_SEL_V  0x00000003U
+#define PCR_32K_MODEM_SEL_S  2
+
+/** PCR_SRAM_POWER_CONF_0_REG register
+ *  HP SRAM/ROM configuration register
+ */
+#define PCR_SRAM_POWER_CONF_0_REG (DR_REG_PCR_BASE + 0x134)
+/** PCR_ROM_FORCE_PU : R/W; bitpos: [14:13]; default: 3;
+ *  Set this bit to force power up ROM
+ */
+#define PCR_ROM_FORCE_PU    0x00000003U
+#define PCR_ROM_FORCE_PU_M  (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S)
+#define PCR_ROM_FORCE_PU_V  0x00000003U
+#define PCR_ROM_FORCE_PU_S  13
+/** PCR_ROM_FORCE_PD : R/W; bitpos: [16:15]; default: 0;
+ *  Set this bit to force power down ROM.
+ */
+#define PCR_ROM_FORCE_PD    0x00000003U
+#define PCR_ROM_FORCE_PD_M  (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S)
+#define PCR_ROM_FORCE_PD_V  0x00000003U
+#define PCR_ROM_FORCE_PD_S  15
+/** PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [18:17]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
+ *  gate-clock will be used when accessing the ROM.
+ */
+#define PCR_ROM_CLKGATE_FORCE_ON    0x00000003U
+#define PCR_ROM_CLKGATE_FORCE_ON_M  (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S)
+#define PCR_ROM_CLKGATE_FORCE_ON_V  0x00000003U
+#define PCR_ROM_CLKGATE_FORCE_ON_S  17
+
+/** PCR_SRAM_POWER_CONF_1_REG register
+ *  HP SRAM/ROM configuration register
+ */
+#define PCR_SRAM_POWER_CONF_1_REG (DR_REG_PCR_BASE + 0x138)
+/** PCR_SRAM_FORCE_PU : R/W; bitpos: [4:0]; default: 31;
+ *  Set this bit to force power up SRAM
+ */
+#define PCR_SRAM_FORCE_PU    0x0000001FU
+#define PCR_SRAM_FORCE_PU_M  (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S)
+#define PCR_SRAM_FORCE_PU_V  0x0000001FU
+#define PCR_SRAM_FORCE_PU_S  0
+/** PCR_SRAM_FORCE_PD : R/W; bitpos: [14:10]; default: 0;
+ *  Set this bit to force power down SRAM.
+ */
+#define PCR_SRAM_FORCE_PD    0x0000001FU
+#define PCR_SRAM_FORCE_PD_M  (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S)
+#define PCR_SRAM_FORCE_PD_V  0x0000001FU
+#define PCR_SRAM_FORCE_PD_S  10
+/** PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [29:25]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
+ *  gate-clock will be used when accessing the SRAM.
+ */
+#define PCR_SRAM_CLKGATE_FORCE_ON    0x0000001FU
+#define PCR_SRAM_CLKGATE_FORCE_ON_M  (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S)
+#define PCR_SRAM_CLKGATE_FORCE_ON_V  0x0000001FU
+#define PCR_SRAM_CLKGATE_FORCE_ON_S  25
+
+/** PCR_SEC_CONF_REG register
+ *  xxxx
+ */
+#define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x13c)
+/** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  xxxx
+ */
+#define PCR_SEC_CLK_SEL    0x00000003U
+#define PCR_SEC_CLK_SEL_M  (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S)
+#define PCR_SEC_CLK_SEL_V  0x00000003U
+#define PCR_SEC_CLK_SEL_S  0
+
+/** PCR_ADC_INV_PHASE_CONF_REG register
+ *  xxxx
+ */
+#define PCR_ADC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x140)
+/** PCR_CLK_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0;
+ *  xxxx
+ */
+#define PCR_CLK_ADC_INV_PHASE_ENA    (BIT(0))
+#define PCR_CLK_ADC_INV_PHASE_ENA_M  (PCR_CLK_ADC_INV_PHASE_ENA_V << PCR_CLK_ADC_INV_PHASE_ENA_S)
+#define PCR_CLK_ADC_INV_PHASE_ENA_V  0x00000001U
+#define PCR_CLK_ADC_INV_PHASE_ENA_S  0
+
+/** PCR_SDM_INV_PHASE_CONF_REG register
+ *  xxxx
+ */
+#define PCR_SDM_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x144)
+/** PCR_CLK_SDM_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0;
+ *  xxxx
+ */
+#define PCR_CLK_SDM_INV_PHASE_ENA    (BIT(0))
+#define PCR_CLK_SDM_INV_PHASE_ENA_M  (PCR_CLK_SDM_INV_PHASE_ENA_V << PCR_CLK_SDM_INV_PHASE_ENA_S)
+#define PCR_CLK_SDM_INV_PHASE_ENA_V  0x00000001U
+#define PCR_CLK_SDM_INV_PHASE_ENA_S  0
+/** PCR_CLK_SDM_INV_PHASE_SEL : R/W; bitpos: [3:1]; default: 0;
+ *  xxxx
+ */
+#define PCR_CLK_SDM_INV_PHASE_SEL    0x00000007U
+#define PCR_CLK_SDM_INV_PHASE_SEL_M  (PCR_CLK_SDM_INV_PHASE_SEL_V << PCR_CLK_SDM_INV_PHASE_SEL_S)
+#define PCR_CLK_SDM_INV_PHASE_SEL_V  0x00000007U
+#define PCR_CLK_SDM_INV_PHASE_SEL_S  1
+
+/** PCR_BUS_CLK_UPDATE_REG register
+ *  xxxx
+ */
+#define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x148)
+/** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0;
+ *  xxxx
+ */
+#define PCR_BUS_CLOCK_UPDATE    (BIT(0))
+#define PCR_BUS_CLOCK_UPDATE_M  (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S)
+#define PCR_BUS_CLOCK_UPDATE_V  0x00000001U
+#define PCR_BUS_CLOCK_UPDATE_S  0
+
+/** PCR_SAR_CLK_DIV_REG register
+ *  xxxx
+ */
+#define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x14c)
+/** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
+ *  xxxx
+ */
+#define PCR_SAR2_CLK_DIV_NUM    0x000000FFU
+#define PCR_SAR2_CLK_DIV_NUM_M  (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S)
+#define PCR_SAR2_CLK_DIV_NUM_V  0x000000FFU
+#define PCR_SAR2_CLK_DIV_NUM_S  0
+/** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4;
+ *  xxxx
+ */
+#define PCR_SAR1_CLK_DIV_NUM    0x000000FFU
+#define PCR_SAR1_CLK_DIV_NUM_M  (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S)
+#define PCR_SAR1_CLK_DIV_NUM_V  0x000000FFU
+#define PCR_SAR1_CLK_DIV_NUM_S  8
+
+/** PCR_PWDET_SAR_CLK_CONF_REG register
+ *  xxxx
+ */
+#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x150)
+/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7;
+ *  xxxx
+ */
+#define PCR_PWDET_SAR_CLK_DIV_NUM    0x000000FFU
+#define PCR_PWDET_SAR_CLK_DIV_NUM_M  (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S)
+#define PCR_PWDET_SAR_CLK_DIV_NUM_V  0x000000FFU
+#define PCR_PWDET_SAR_CLK_DIV_NUM_S  0
+/** PCR_PWDET_SAR_READER_EN : R/W; bitpos: [8]; default: 1;
+ *  xxxx
+ */
+#define PCR_PWDET_SAR_READER_EN    (BIT(8))
+#define PCR_PWDET_SAR_READER_EN_M  (PCR_PWDET_SAR_READER_EN_V << PCR_PWDET_SAR_READER_EN_S)
+#define PCR_PWDET_SAR_READER_EN_V  0x00000001U
+#define PCR_PWDET_SAR_READER_EN_S  8
+
+/** PCR_RESET_EVENT_BYPASS_REG register
+ *  reset event bypass backdoor configuration register
+ */
+#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0)
+/** PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0;
+ *  This field is used to control reset event relationship for
+ *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
+ *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
+ *  will not only be reset by power-reset, but also some reset event.
+ */
+#define PCR_RESET_EVENT_BYPASS_APM    (BIT(0))
+#define PCR_RESET_EVENT_BYPASS_APM_M  (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S)
+#define PCR_RESET_EVENT_BYPASS_APM_V  0x00000001U
+#define PCR_RESET_EVENT_BYPASS_APM_S  0
+/** PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  This field is used to control reset event relationship for system-bus. 1: system
+ *  bus (including arbiter/router) will only be reset by power-reset. some reset event
+ *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
+ *  power-reset, but also some reset event.
+ */
+#define PCR_RESET_EVENT_BYPASS    (BIT(1))
+#define PCR_RESET_EVENT_BYPASS_M  (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S)
+#define PCR_RESET_EVENT_BYPASS_V  0x00000001U
+#define PCR_RESET_EVENT_BYPASS_S  1
+
+/** PCR_FPGA_DEBUG_REG register
+ *  fpga debug register
+ */
+#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4)
+/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Only used in fpga debug.
+ */
+#define PCR_FPGA_DEBUG    0xFFFFFFFFU
+#define PCR_FPGA_DEBUG_M  (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S)
+#define PCR_FPGA_DEBUG_V  0xFFFFFFFFU
+#define PCR_FPGA_DEBUG_S  0
+
+/** PCR_CLOCK_GATE_REG register
+ *  PCR clock gating configure register
+ */
+#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8)
+/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to force on clock gating.
+ */
+#define PCR_CLK_EN    (BIT(0))
+#define PCR_CLK_EN_M  (PCR_CLK_EN_V << PCR_CLK_EN_S)
+#define PCR_CLK_EN_V  0x00000001U
+#define PCR_CLK_EN_S  0
+
+/** PCR_DATE_REG register
+ *  Date register.
+ */
+#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc)
+/** PCR_DATE : R/W; bitpos: [27:0]; default: 35717248;
+ *  PCR version information.
+ */
+#define PCR_DATE    0x0FFFFFFFU
+#define PCR_DATE_M  (PCR_DATE_V << PCR_DATE_S)
+#define PCR_DATE_V  0x0FFFFFFFU
+#define PCR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/pcr_struct.h b/components/soc/esp32h2/register/soc/pcr_struct.h
new file mode 100644
index 00000000000..cf1a690ac30
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/pcr_struct.h
@@ -0,0 +1,2093 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Register */
+/** Type of uart0_conf register
+ *  UART0 configuration register
+ */
+typedef union {
+    struct {
+        /** uart0_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable uart0 apb clock
+         */
+        uint32_t uart0_clk_en:1;
+        /** uart0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset uart0 module
+         */
+        uint32_t uart0_rst_en:1;
+        /** uart0_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset uart0 module
+         */
+        uint32_t uart0_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_uart0_conf_reg_t;
+
+/** Type of uart0_sclk_conf register
+ *  UART0_SCLK configuration register
+ */
+typedef union {
+    struct {
+        /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the uart0 function clock.
+         */
+        uint32_t uart0_sclk_div_a:6;
+        /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the uart0 function clock.
+         */
+        uint32_t uart0_sclk_div_b:6;
+        /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
+         *  The integral part of the frequency divider factor of the uart0 function clock.
+         */
+        uint32_t uart0_sclk_div_num:8;
+        /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+         *  FOSC, 3(default): XTAL.
+         */
+        uint32_t uart0_sclk_sel:2;
+        /** uart0_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable uart0 function clock
+         */
+        uint32_t uart0_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_uart0_sclk_conf_reg_t;
+
+/** Type of uart0_pd_ctrl register
+ *  UART0 power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power down UART0 memory.
+         */
+        uint32_t uart0_mem_force_pu:1;
+        /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power up UART0 memory.
+         */
+        uint32_t uart0_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_uart0_pd_ctrl_reg_t;
+
+/** Type of uart1_conf register
+ *  UART1 configuration register
+ */
+typedef union {
+    struct {
+        /** uart1_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable uart1 apb clock
+         */
+        uint32_t uart1_clk_en:1;
+        /** uart1_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset uart1 module
+         */
+        uint32_t uart1_rst_en:1;
+        /** uart1_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset uart1 module
+         */
+        uint32_t uart1_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_uart1_conf_reg_t;
+
+/** Type of uart1_sclk_conf register
+ *  UART1_SCLK configuration register
+ */
+typedef union {
+    struct {
+        /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the uart1 function clock.
+         */
+        uint32_t uart1_sclk_div_a:6;
+        /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the uart1 function clock.
+         */
+        uint32_t uart1_sclk_div_b:6;
+        /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
+         *  The integral part of the frequency divider factor of the uart1 function clock.
+         */
+        uint32_t uart1_sclk_div_num:8;
+        /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+         *  FOSC, 3(default): XTAL.
+         */
+        uint32_t uart1_sclk_sel:2;
+        /** uart1_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable uart0 function clock
+         */
+        uint32_t uart1_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_uart1_sclk_conf_reg_t;
+
+/** Type of uart1_pd_ctrl register
+ *  UART1 power control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power down UART1 memory.
+         */
+        uint32_t uart1_mem_force_pu:1;
+        /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power up UART1 memory.
+         */
+        uint32_t uart1_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_uart1_pd_ctrl_reg_t;
+
+/** Type of mspi_conf register
+ *  MSPI configuration register
+ */
+typedef union {
+    struct {
+        /** mspi_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable mspi clock, include mspi pll clock
+         */
+        uint32_t mspi_clk_en:1;
+        /** mspi_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset mspi module
+         */
+        uint32_t mspi_rst_en:1;
+        /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to enable mspi pll clock
+         */
+        uint32_t mspi_pll_clk_en:1;
+        /** mspi_clk_sel : R/W; bitpos: [4:3]; default: 0;
+         *  set this field to select clock-source.
+         */
+        uint32_t mspi_clk_sel:2;
+        /** mspi_ready : RO; bitpos: [5]; default: 1;
+         *  Query this field after reset mspi module
+         */
+        uint32_t mspi_ready:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} pcr_mspi_conf_reg_t;
+
+/** Type of mspi_clk_conf register
+ *  MSPI_CLK configuration register
+ */
+typedef union {
+    struct {
+        /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed
+         *  clock-source to drive clk_mspi_fast. Only available when the clck-source is a
+         *  low-speed clock-source such as XTAL/FOSC.
+         */
+        uint32_t mspi_fast_div_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} pcr_mspi_clk_conf_reg_t;
+
+/** Type of i2c_conf register
+ *  I2C configuration register
+ */
+typedef union {
+    struct {
+        /** i2c_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable i2c apb clock
+         */
+        uint32_t i2c_clk_en:1;
+        /** i2c_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset i2c module
+         */
+        uint32_t i2c_rst_en:1;
+        /** i2c_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset i2c module
+         */
+        uint32_t i2c_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_i2c_conf_reg_t;
+
+/** Type of i2c_sclk_conf register
+ *  I2C_SCLK configuration register
+ */
+typedef union {
+    struct {
+        /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the i2c function clock.
+         */
+        uint32_t i2c_sclk_div_a:6;
+        /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the i2c function clock.
+         */
+        uint32_t i2c_sclk_div_b:6;
+        /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0;
+         *  The integral part of the frequency divider factor of the i2c function clock.
+         */
+        uint32_t i2c_sclk_div_num:8;
+        /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+         */
+        uint32_t i2c_sclk_sel:1;
+        uint32_t reserved_21:1;
+        /** i2c_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable i2c function clock
+         */
+        uint32_t i2c_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_i2c_sclk_conf_reg_t;
+
+/** Type of uhci_conf register
+ *  UHCI configuration register
+ */
+typedef union {
+    struct {
+        /** uhci_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable uhci clock
+         */
+        uint32_t uhci_clk_en:1;
+        /** uhci_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset uhci module
+         */
+        uint32_t uhci_rst_en:1;
+        /** uhci_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset uhci module
+         */
+        uint32_t uhci_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_uhci_conf_reg_t;
+
+/** Type of rmt_conf register
+ *  RMT configuration register
+ */
+typedef union {
+    struct {
+        /** rmt_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable rmt apb clock
+         */
+        uint32_t rmt_clk_en:1;
+        /** rmt_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset rmt module
+         */
+        uint32_t rmt_rst_en:1;
+        /** rmt_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset rmt module
+         */
+        uint32_t rmt_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_rmt_conf_reg_t;
+
+/** Type of rmt_sclk_conf register
+ *  RMT_SCLK configuration register
+ */
+typedef union {
+    struct {
+        /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the rmt function clock.
+         */
+        uint32_t rmt_sclk_div_a:6;
+        /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the rmt function clock.
+         */
+        uint32_t rmt_sclk_div_b:6;
+        /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor of the rmt function clock.
+         */
+        uint32_t rmt_sclk_div_num:8;
+        /** rmt_sclk_sel : R/W; bitpos: [20]; default: 1;
+         *  set this field to select clock-source. 0: do not select anyone clock, 1(default):
+         *  80MHz, 2: FOSC, 3: XTAL.
+         */
+        uint32_t rmt_sclk_sel:1;
+        /** rmt_sclk_en : R/W; bitpos: [21]; default: 1;
+         *  Set 1 to enable rmt function clock
+         */
+        uint32_t rmt_sclk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} pcr_rmt_sclk_conf_reg_t;
+
+/** Type of ledc_conf register
+ *  LEDC configuration register
+ */
+typedef union {
+    struct {
+        /** ledc_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable ledc apb clock
+         */
+        uint32_t ledc_clk_en:1;
+        /** ledc_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset ledc module
+         */
+        uint32_t ledc_rst_en:1;
+        /** ledc_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset ledc module
+         */
+        uint32_t ledc_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_ledc_conf_reg_t;
+
+/** Type of ledc_sclk_conf register
+ *  LEDC_SCLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+         *  80MHz, 2: FOSC, 3: XTAL.
+         */
+        uint32_t ledc_sclk_sel:2;
+        /** ledc_sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable ledc function clock
+         */
+        uint32_t ledc_sclk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_ledc_sclk_conf_reg_t;
+
+/** Type of timergroup0_conf register
+ *  TIMERGROUP0 configuration register
+ */
+typedef union {
+    struct {
+        /** tg0_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable timer_group0 apb clock
+         */
+        uint32_t tg0_clk_en:1;
+        /** tg0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset timer_group0 module
+         */
+        uint32_t tg0_rst_en:1;
+        /** tg0_wdt_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset timer_group0 wdt module
+         */
+        uint32_t tg0_wdt_ready:1;
+        /** tg0_timer0_ready : RO; bitpos: [3]; default: 1;
+         *  Query this field after reset timer_group0 timer0 module
+         */
+        uint32_t tg0_timer0_ready:1;
+        /** tg0_timer1_ready : RO; bitpos: [4]; default: 1;
+         *  reserved
+         */
+        uint32_t tg0_timer1_ready:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} pcr_timergroup0_conf_reg_t;
+
+/** Type of timergroup0_timer_clk_conf register
+ *  TIMERGROUP0_TIMER_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t tg0_timer_clk_sel:2;
+        /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable timer_group0 timer clock
+         */
+        uint32_t tg0_timer_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_timergroup0_timer_clk_conf_reg_t;
+
+/** Type of timergroup0_wdt_clk_conf register
+ *  TIMERGROUP0_WDT_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t tg0_wdt_clk_sel:2;
+        /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable timer_group0 wdt clock
+         */
+        uint32_t tg0_wdt_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_timergroup0_wdt_clk_conf_reg_t;
+
+/** Type of timergroup1_conf register
+ *  TIMERGROUP1 configuration register
+ */
+typedef union {
+    struct {
+        /** tg1_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable timer_group1 apb clock
+         */
+        uint32_t tg1_clk_en:1;
+        /** tg1_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset timer_group1 module
+         */
+        uint32_t tg1_rst_en:1;
+        /** tg1_wdt_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset timer_group1 wdt module
+         */
+        uint32_t tg1_wdt_ready:1;
+        /** tg1_timer0_ready : RO; bitpos: [3]; default: 1;
+         *  Query this field after reset timer_group1 timer0 module
+         */
+        uint32_t tg1_timer0_ready:1;
+        /** tg1_timer1_ready : RO; bitpos: [4]; default: 1;
+         *  reserved
+         */
+        uint32_t tg1_timer1_ready:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} pcr_timergroup1_conf_reg_t;
+
+/** Type of timergroup1_timer_clk_conf register
+ *  TIMERGROUP1_TIMER_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t tg1_timer_clk_sel:2;
+        /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable timer_group1 timer clock
+         */
+        uint32_t tg1_timer_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_timergroup1_timer_clk_conf_reg_t;
+
+/** Type of timergroup1_wdt_clk_conf register
+ *  TIMERGROUP1_WDT_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t tg1_wdt_clk_sel:2;
+        /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable timer_group0 wdt clock
+         */
+        uint32_t tg1_wdt_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_timergroup1_wdt_clk_conf_reg_t;
+
+/** Type of systimer_conf register
+ *  SYSTIMER configuration register
+ */
+typedef union {
+    struct {
+        /** systimer_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable systimer apb clock
+         */
+        uint32_t systimer_clk_en:1;
+        /** systimer_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset systimer module
+         */
+        uint32_t systimer_rst_en:1;
+        /** systimer_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset systimer module
+         */
+        uint32_t systimer_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_systimer_conf_reg_t;
+
+/** Type of systimer_func_clk_conf register
+ *  SYSTIMER_FUNC_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+         */
+        uint32_t systimer_func_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable systimer function clock
+         */
+        uint32_t systimer_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_systimer_func_clk_conf_reg_t;
+
+/** Type of twai0_conf register
+ *  TWAI0 configuration register
+ */
+typedef union {
+    struct {
+        /** twai0_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable twai0 apb clock
+         */
+        uint32_t twai0_clk_en:1;
+        /** twai0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset twai0 module
+         */
+        uint32_t twai0_rst_en:1;
+        /** twai0_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset twai0 module
+         */
+        uint32_t twai0_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_twai0_conf_reg_t;
+
+/** Type of twai0_func_clk_conf register
+ *  TWAI0_FUNC_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: FOSC.
+         */
+        uint32_t twai0_func_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable twai0 function clock
+         */
+        uint32_t twai0_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_twai0_func_clk_conf_reg_t;
+
+/** Type of i2s_conf register
+ *  I2S configuration register
+ */
+typedef union {
+    struct {
+        /** i2s_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable i2s apb clock
+         */
+        uint32_t i2s_clk_en:1;
+        /** i2s_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset i2s module
+         */
+        uint32_t i2s_rst_en:1;
+        /** i2s_rx_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field before using i2s rx function, after reset i2s module
+         */
+        uint32_t i2s_rx_ready:1;
+        /** i2s_tx_ready : RO; bitpos: [3]; default: 1;
+         *  Query this field before using i2s tx function, after reset i2s module
+         */
+        uint32_t i2s_tx_ready:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcr_i2s_conf_reg_t;
+
+/** Type of i2s_tx_clkm_conf register
+ *  I2S_TX_CLKM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
+         *  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
+         *  (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <=
+         *  a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+         *  (n+1)-div] + y * (n+1)-div.
+         */
+        uint32_t i2s_tx_clkm_div_num:8;
+        /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+         *  I2S_MCLK_in.
+         */
+        uint32_t i2s_tx_clkm_sel:2;
+        /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable i2s_tx function clock
+         */
+        uint32_t i2s_tx_clkm_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_i2s_tx_clkm_conf_reg_t;
+
+/** Type of i2s_tx_clkm_div_conf register
+ *  I2S_TX_CLKM_DIV configuration register
+ */
+typedef union {
+    struct {
+        /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
+         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+         *  I2S_TX_CLKM_DIV_Z is (a-b).
+         */
+        uint32_t i2s_tx_clkm_div_z:9;
+        /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
+         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+         *  I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+         */
+        uint32_t i2s_tx_clkm_div_y:9;
+        /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
+         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+         *  of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+         */
+        uint32_t i2s_tx_clkm_div_x:9;
+        /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+         *  I2S_TX_CLKM_DIV_YN1 is 1.
+         */
+        uint32_t i2s_tx_clkm_div_yn1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} pcr_i2s_tx_clkm_div_conf_reg_t;
+
+/** Type of i2s_rx_clkm_conf register
+ *  I2S_RX_CLKM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2;
+         *  Integral I2S clock divider value
+         */
+        uint32_t i2s_rx_clkm_div_num:8;
+        /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+         */
+        uint32_t i2s_rx_clkm_sel:2;
+        /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable i2s_rx function clock
+         */
+        uint32_t i2s_rx_clkm_en:1;
+        /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0;
+         *  This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx
+         */
+        uint32_t i2s_mclk_sel:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} pcr_i2s_rx_clkm_conf_reg_t;
+
+/** Type of i2s_rx_clkm_div_conf register
+ *  I2S_RX_CLKM_DIV configuration register
+ */
+typedef union {
+    struct {
+        /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0;
+         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+         *  I2S_RX_CLKM_DIV_Z is (a-b).
+         */
+        uint32_t i2s_rx_clkm_div_z:9;
+        /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1;
+         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of
+         *  I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+         */
+        uint32_t i2s_rx_clkm_div_y:9;
+        /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0;
+         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+         *  of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+         */
+        uint32_t i2s_rx_clkm_div_x:9;
+        /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+         *  I2S_RX_CLKM_DIV_YN1 is 1.
+         */
+        uint32_t i2s_rx_clkm_div_yn1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} pcr_i2s_rx_clkm_div_conf_reg_t;
+
+/** Type of saradc_conf register
+ *  SARADC configuration register
+ */
+typedef union {
+    struct {
+        /** saradc_clk_en : R/W; bitpos: [0]; default: 1;
+         *  no use
+         */
+        uint32_t saradc_clk_en:1;
+        /** saradc_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset function_register of saradc module
+         */
+        uint32_t saradc_rst_en:1;
+        /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to enable saradc apb clock
+         */
+        uint32_t saradc_reg_clk_en:1;
+        /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0;
+         *  Set 0 to reset apb_register of saradc module
+         */
+        uint32_t saradc_reg_rst_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcr_saradc_conf_reg_t;
+
+/** Type of saradc_clkm_conf register
+ *  SARADC_CLKM configuration register
+ */
+typedef union {
+    struct {
+        /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor of the saradc function clock.
+         */
+        uint32_t saradc_clkm_div_a:6;
+        /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor of the saradc function clock.
+         */
+        uint32_t saradc_clkm_div_b:6;
+        /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4;
+         *  The integral part of the frequency divider factor of the saradc function clock.
+         */
+        uint32_t saradc_clkm_div_num:8;
+        /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t saradc_clkm_sel:2;
+        /** saradc_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable saradc function clock
+         */
+        uint32_t saradc_clkm_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_saradc_clkm_conf_reg_t;
+
+/** Type of tsens_clk_conf register
+ *  TSENS_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** tsens_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0(default): FOSC, 1: XTAL.
+         */
+        uint32_t tsens_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** tsens_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable tsens clock
+         */
+        uint32_t tsens_clk_en:1;
+        /** tsens_rst_en : R/W; bitpos: [23]; default: 0;
+         *  Set 0 to reset tsens module
+         */
+        uint32_t tsens_rst_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} pcr_tsens_clk_conf_reg_t;
+
+/** Type of usb_device_conf register
+ *  USB_DEVICE configuration register
+ */
+typedef union {
+    struct {
+        /** usb_device_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable usb_device clock
+         */
+        uint32_t usb_device_clk_en:1;
+        /** usb_device_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset usb_device module
+         */
+        uint32_t usb_device_rst_en:1;
+        /** usb_device_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset usb_device module
+         */
+        uint32_t usb_device_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_usb_device_conf_reg_t;
+
+/** Type of intmtx_conf register
+ *  INTMTX configuration register
+ */
+typedef union {
+    struct {
+        /** intmtx_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable intmtx clock
+         */
+        uint32_t intmtx_clk_en:1;
+        /** intmtx_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset intmtx module
+         */
+        uint32_t intmtx_rst_en:1;
+        /** intmtx_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset intmtx module
+         */
+        uint32_t intmtx_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_intmtx_conf_reg_t;
+
+/** Type of pcnt_conf register
+ *  PCNT configuration register
+ */
+typedef union {
+    struct {
+        /** pcnt_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable pcnt clock
+         */
+        uint32_t pcnt_clk_en:1;
+        /** pcnt_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset pcnt module
+         */
+        uint32_t pcnt_rst_en:1;
+        /** pcnt_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset pcnt module
+         */
+        uint32_t pcnt_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_pcnt_conf_reg_t;
+
+/** Type of etm_conf register
+ *  ETM configuration register
+ */
+typedef union {
+    struct {
+        /** etm_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable etm clock
+         */
+        uint32_t etm_clk_en:1;
+        /** etm_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset etm module
+         */
+        uint32_t etm_rst_en:1;
+        /** etm_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset etm module
+         */
+        uint32_t etm_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_etm_conf_reg_t;
+
+/** Type of pwm_conf register
+ *  PWM configuration register
+ */
+typedef union {
+    struct {
+        /** pwm_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable pwm clock
+         */
+        uint32_t pwm_clk_en:1;
+        /** pwm_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset pwm module
+         */
+        uint32_t pwm_rst_en:1;
+        /** pwm_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset pwm module
+         */
+        uint32_t pwm_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_pwm_conf_reg_t;
+
+/** Type of pwm_clk_conf register
+ *  PWM_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** pwm_div_num : R/W; bitpos: [19:12]; default: 4;
+         *  The integral part of the frequency divider factor of the pwm function clock.
+         */
+        uint32_t pwm_div_num:8;
+        /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): do not select anyone clock, 1:
+         *  160MHz, 2: XTAL, 3: FOSC.
+         */
+        uint32_t pwm_clkm_sel:2;
+        /** pwm_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  set this field as 1 to activate pwm clkm.
+         */
+        uint32_t pwm_clkm_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_pwm_clk_conf_reg_t;
+
+/** Type of parl_io_conf register
+ *  PARL_IO configuration register
+ */
+typedef union {
+    struct {
+        /** parl_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable parl apb clock
+         */
+        uint32_t parl_clk_en:1;
+        /** parl_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset parl apb reg
+         */
+        uint32_t parl_rst_en:1;
+        /** parl_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset parl module
+         */
+        uint32_t parl_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_parl_io_conf_reg_t;
+
+/** Type of parl_clk_rx_conf register
+ *  PARL_CLK_RX configuration register
+ */
+typedef union {
+    struct {
+        /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0;
+         *  The integral part of the frequency divider factor of the parl rx clock.
+         */
+        uint32_t parl_clk_rx_div_num:16;
+        /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+         *  user clock from pad.
+         */
+        uint32_t parl_clk_rx_sel:2;
+        /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1;
+         *  Set 1 to enable parl rx clock
+         */
+        uint32_t parl_clk_rx_en:1;
+        /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0;
+         *  Set 0 to reset parl rx module
+         */
+        uint32_t parl_rx_rst_en:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} pcr_parl_clk_rx_conf_reg_t;
+
+/** Type of parl_clk_tx_conf register
+ *  PARL_CLK_TX configuration register
+ */
+typedef union {
+    struct {
+        /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0;
+         *  The integral part of the frequency divider factor of the parl tx clock.
+         */
+        uint32_t parl_clk_tx_div_num:16;
+        /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3:
+         *  user clock from pad.
+         */
+        uint32_t parl_clk_tx_sel:2;
+        /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1;
+         *  Set 1 to enable parl tx clock
+         */
+        uint32_t parl_clk_tx_en:1;
+        /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0;
+         *  Set 0 to reset parl tx module
+         */
+        uint32_t parl_tx_rst_en:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} pcr_parl_clk_tx_conf_reg_t;
+
+/** Type of pvt_monitor_conf register
+ *  PVT_MONITOR configuration register
+ */
+typedef union {
+    struct {
+        /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable apb clock of pvt module
+         */
+        uint32_t pvt_monitor_clk_en:1;
+        /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset all pvt monitor module
+         */
+        uint32_t pvt_monitor_rst_en:1;
+        /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to enable function clock of modem pvt module
+         */
+        uint32_t pvt_monitor_site1_clk_en:1;
+        /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1;
+         *  Set 1 to enable function clock of cpu pvt module
+         */
+        uint32_t pvt_monitor_site2_clk_en:1;
+        /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1;
+         *  Set 1 to enable function clock of hp_peri pvt module
+         */
+        uint32_t pvt_monitor_site3_clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} pcr_pvt_monitor_conf_reg_t;
+
+/** Type of pvt_monitor_func_clk_conf register
+ *  PVT_MONITOR function clock configuration register
+ */
+typedef union {
+    struct {
+        /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0;
+         *  The integral part of the frequency divider factor of the pvt_monitor function clock.
+         */
+        uint32_t pvt_monitor_func_clk_div_num:4;
+        uint32_t reserved_4:16;
+        /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0;
+         *  set this field to select clock-source. 0: XTAL, 1(default): 160MHz driven by SPLL
+         *  divided by 3.
+         */
+        uint32_t pvt_monitor_func_clk_sel:1;
+        uint32_t reserved_21:1;
+        /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable source clock of pvt sitex
+         */
+        uint32_t pvt_monitor_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_pvt_monitor_func_clk_conf_reg_t;
+
+/** Type of gdma_conf register
+ *  GDMA configuration register
+ */
+typedef union {
+    struct {
+        /** gdma_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable gdma clock
+         */
+        uint32_t gdma_clk_en:1;
+        /** gdma_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset gdma module
+         */
+        uint32_t gdma_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_gdma_conf_reg_t;
+
+/** Type of spi2_conf register
+ *  SPI2 configuration register
+ */
+typedef union {
+    struct {
+        /** spi2_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable spi2 apb clock
+         */
+        uint32_t spi2_clk_en:1;
+        /** spi2_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset spi2 module
+         */
+        uint32_t spi2_rst_en:1;
+        /** spi2_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset spi2 module
+         */
+        uint32_t spi2_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_spi2_conf_reg_t;
+
+/** Type of spi2_clkm_conf register
+ *  SPI2_CLKM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0(default): XTAL, 1: 48MHz, 2: FOSC, 3:
+         *  reserved.
+         */
+        uint32_t spi2_clkm_sel:2;
+        /** spi2_clkm_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable spi2 function clock
+         */
+        uint32_t spi2_clkm_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_spi2_clkm_conf_reg_t;
+
+/** Type of aes_conf register
+ *  AES configuration register
+ */
+typedef union {
+    struct {
+        /** aes_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable aes clock
+         */
+        uint32_t aes_clk_en:1;
+        /** aes_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset aes module
+         */
+        uint32_t aes_rst_en:1;
+        /** aes_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset aes module
+         */
+        uint32_t aes_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_aes_conf_reg_t;
+
+/** Type of sha_conf register
+ *  SHA configuration register
+ */
+typedef union {
+    struct {
+        /** sha_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable sha clock
+         */
+        uint32_t sha_clk_en:1;
+        /** sha_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset sha module
+         */
+        uint32_t sha_rst_en:1;
+        /** sha_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset sha module
+         */
+        uint32_t sha_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_sha_conf_reg_t;
+
+/** Type of rsa_conf register
+ *  RSA configuration register
+ */
+typedef union {
+    struct {
+        /** rsa_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable rsa clock
+         */
+        uint32_t rsa_clk_en:1;
+        /** rsa_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset rsa module
+         */
+        uint32_t rsa_rst_en:1;
+        /** rsa_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset rsa module
+         */
+        uint32_t rsa_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_rsa_conf_reg_t;
+
+/** Type of rsa_pd_ctrl register
+ *  RSA power control register
+ */
+typedef union {
+    struct {
+        /** rsa_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down rsa internal memory.
+         */
+        uint32_t rsa_mem_pd:1;
+        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up rsa internal memory
+         */
+        uint32_t rsa_mem_force_pu:1;
+        /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down rsa internal memory.
+         */
+        uint32_t rsa_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_rsa_pd_ctrl_reg_t;
+
+/** Type of ecc_conf register
+ *  ECC configuration register
+ */
+typedef union {
+    struct {
+        /** ecc_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable ecc clock
+         */
+        uint32_t ecc_clk_en:1;
+        /** ecc_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset ecc module
+         */
+        uint32_t ecc_rst_en:1;
+        /** ecc_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset ecc module
+         */
+        uint32_t ecc_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_ecc_conf_reg_t;
+
+/** Type of ecc_pd_ctrl register
+ *  ECC power control register
+ */
+typedef union {
+    struct {
+        /** ecc_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down ecc internal memory.
+         */
+        uint32_t ecc_mem_pd:1;
+        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up ecc internal memory
+         */
+        uint32_t ecc_mem_force_pu:1;
+        /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down ecc internal memory.
+         */
+        uint32_t ecc_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_ecc_pd_ctrl_reg_t;
+
+/** Type of ds_conf register
+ *  DS configuration register
+ */
+typedef union {
+    struct {
+        /** ds_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable ds clock
+         */
+        uint32_t ds_clk_en:1;
+        /** ds_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset ds module
+         */
+        uint32_t ds_rst_en:1;
+        /** ds_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset ds module
+         */
+        uint32_t ds_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_ds_conf_reg_t;
+
+/** Type of hmac_conf register
+ *  HMAC configuration register
+ */
+typedef union {
+    struct {
+        /** hmac_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable hmac clock
+         */
+        uint32_t hmac_clk_en:1;
+        /** hmac_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset hmac module
+         */
+        uint32_t hmac_rst_en:1;
+        /** hmac_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset hmac module
+         */
+        uint32_t hmac_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_hmac_conf_reg_t;
+
+/** Type of ecdsa_conf register
+ *  ECDSA configuration register
+ */
+typedef union {
+    struct {
+        /** ecdsa_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable ecdsa clock
+         */
+        uint32_t ecdsa_clk_en:1;
+        /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset ecdsa module
+         */
+        uint32_t ecdsa_rst_en:1;
+        /** ecdsa_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset ecdsa module
+         */
+        uint32_t ecdsa_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_ecdsa_conf_reg_t;
+
+/** Type of iomux_conf register
+ *  IOMUX configuration register
+ */
+typedef union {
+    struct {
+        /** iomux_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable iomux apb clock
+         */
+        uint32_t iomux_clk_en:1;
+        /** iomux_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset iomux module
+         */
+        uint32_t iomux_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_iomux_conf_reg_t;
+
+/** Type of iomux_clk_conf register
+ *  IOMUX_CLK configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0;
+         *  set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2:
+         *  FOSC, 3(default): XTAL.
+         */
+        uint32_t iomux_func_clk_sel:2;
+        /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1;
+         *  Set 1 to enable iomux function clock
+         */
+        uint32_t iomux_func_clk_en:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} pcr_iomux_clk_conf_reg_t;
+
+/** Type of mem_monitor_conf register
+ *  MEM_MONITOR configuration register
+ */
+typedef union {
+    struct {
+        /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable mem_monitor clock
+         */
+        uint32_t mem_monitor_clk_en:1;
+        /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset mem_monitor module
+         */
+        uint32_t mem_monitor_rst_en:1;
+        /** mem_monitor_ready : RO; bitpos: [2]; default: 1;
+         *  Query this field after reset mem_monitor module
+         */
+        uint32_t mem_monitor_ready:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_mem_monitor_conf_reg_t;
+
+/** Type of regdma_conf register
+ *  REGDMA configuration register
+ */
+typedef union {
+    struct {
+        /** regdma_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable regdma clock
+         */
+        uint32_t regdma_clk_en:1;
+        /** regdma_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset regdma module
+         */
+        uint32_t regdma_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_regdma_conf_reg_t;
+
+/** Type of trace_conf register
+ *  TRACE configuration register
+ */
+typedef union {
+    struct {
+        /** trace_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable trace clock
+         */
+        uint32_t trace_clk_en:1;
+        /** trace_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset trace module
+         */
+        uint32_t trace_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_trace_conf_reg_t;
+
+/** Type of assist_conf register
+ *  ASSIST configuration register
+ */
+typedef union {
+    struct {
+        /** assist_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable assist clock
+         */
+        uint32_t assist_clk_en:1;
+        /** assist_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset assist module
+         */
+        uint32_t assist_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_assist_conf_reg_t;
+
+/** Type of cache_conf register
+ *  CACHE configuration register
+ */
+typedef union {
+    struct {
+        /** cache_clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable cache clock
+         */
+        uint32_t cache_clk_en:1;
+        /** cache_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset cache module
+         */
+        uint32_t cache_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_cache_conf_reg_t;
+
+/** Type of modem_conf register
+ *  MODEM_APB configuration register
+ */
+typedef union {
+    struct {
+        /** modem_clk_sel : R/W; bitpos: [0]; default: 0;
+         *  xxxx
+         */
+        uint32_t modem_clk_sel:1;
+        /** modem_clk_en : R/W; bitpos: [1]; default: 1;
+         *  xxxx
+         */
+        uint32_t modem_clk_en:1;
+        /** modem_rst_en : R/W; bitpos: [2]; default: 0;
+         *  Set this file as 1 to reset modem-subsystem.
+         */
+        uint32_t modem_rst_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_modem_conf_reg_t;
+
+/** Type of timeout_conf register
+ *  TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set 0 to reset cpu_peri timeout module
+         */
+        uint32_t cpu_timeout_rst_en:1;
+        /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0;
+         *  Set 0 to reset hp_peri timeout module and hp_modem timeout module
+         */
+        uint32_t hp_timeout_rst_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} pcr_timeout_conf_reg_t;
+
+/** Type of sysclk_conf register
+ *  SYSCLK configuration register
+ */
+typedef union {
+    struct {
+        /** ls_div_num : HRO; bitpos: [7:0]; default: 0;
+         *  clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed
+         *  clock-source such as XTAL/FOSC.
+         */
+        uint32_t ls_div_num:8;
+        /** hs_div_num : HRO; bitpos: [15:8]; default: 2;
+         *  clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
+         */
+        uint32_t hs_div_num:8;
+        /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0;
+         *  This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
+         */
+        uint32_t soc_clk_sel:2;
+        uint32_t reserved_18:6;
+        /** clk_xtal_freq : RO; bitpos: [30:24]; default: 32;
+         *  This field indicates the frequency(MHz) of XTAL.
+         */
+        uint32_t clk_xtal_freq:7;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} pcr_sysclk_conf_reg_t;
+
+/** Type of cpu_waiti_conf register
+ *  CPU_WAITI configuration register
+ */
+typedef union {
+    struct {
+        /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1;
+         *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
+         */
+        uint32_t cpuperiod_sel:2;
+        /** pll_freq_sel : HRO; bitpos: [2]; default: 1;
+         *  Reserved. This filed has been replaced by PCR_CPU_DIV_NUM
+         */
+        uint32_t pll_freq_sel:1;
+        /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
+         *  Set 1 to force cpu_waiti_clk enable.
+         */
+        uint32_t cpu_wait_mode_force_on:1;
+        /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0;
+         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+         *  will close
+         */
+        uint32_t cpu_waiti_delay_num:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} pcr_cpu_waiti_conf_reg_t;
+
+/** Type of cpu_freq_conf register
+ *  CPU_FREQ configuration register
+ */
+typedef union {
+    struct {
+        /** cpu_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is
+         *  div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed
+         *  clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM.
+         */
+        uint32_t cpu_div_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} pcr_cpu_freq_conf_reg_t;
+
+/** Type of ahb_freq_conf register
+ *  AHB_FREQ configuration register
+ */
+typedef union {
+    struct {
+        /** ahb_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is
+         *  div1(default)/div2/div4/div8 of clk_hproot. This field is only available for
+         *  low-speed clock-source such as XTAL/FOSC, and should be used together with
+         *  PCR_CPU_DIV_NUM.
+         */
+        uint32_t ahb_div_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} pcr_ahb_freq_conf_reg_t;
+
+/** Type of apb_freq_conf register
+ *  APB_FREQ configuration register
+ */
+typedef union {
+    struct {
+        /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be
+         *  automatically down to clk_apb_decrease only when no access is on apb-bus, and will
+         *  recover to the previous frequency when a new access appears on apb-bus. Set as one
+         *  within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note
+         *  that enable this function will reduce performance. Users can set this field as zero
+         *  to disable the auto-decrease-apb-freq function. By default, this function is
+         *  disable.
+         */
+        uint32_t apb_decrease_div_num:8;
+        /** apb_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is
+         *  div1(default)/div2/div4 of clk_ahb.
+         */
+        uint32_t apb_div_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcr_apb_freq_conf_reg_t;
+
+/** Type of pll_div_clk_en register
+ *  SPLL DIV clock-gating configuration register
+ */
+typedef union {
+    struct {
+        /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1;
+         *  This field is used to open 96 MHz clock (SPLL) driven from SPLL. 0: close, 1:
+         *  open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_240m_clk_en:1;
+        /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1;
+         *  This field is used to open 64 MHz clock (div3 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_160m_clk_en:1;
+        /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1;
+         *  This field is used to open 48 MHz clock (div4 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_120m_clk_en:1;
+        /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1;
+         *  This field is used to open 32 MHz clock (div6  of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_80m_clk_en:1;
+        /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1;
+         *  This field is used to open 16 MHz clock (div10 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_48m_clk_en:1;
+        /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1;
+         *  This field is used to open 8 MHz clock (div12 of SPLL) driven from SPLL. 0: close,
+         *  1: open(default). Only available when high-speed clock-source SPLL is active.
+         */
+        uint32_t pll_40m_clk_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} pcr_pll_div_clk_en_reg_t;
+
+/** Type of ctrl_clk_out_en register
+ *  CLK_OUT_EN configuration register
+ */
+typedef union {
+    struct {
+        /** clk8_oen : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to enable 8m clock
+         */
+        uint32_t clk8_oen:1;
+        /** clk16_oen : R/W; bitpos: [1]; default: 1;
+         *  Set 1 to enable 16m clock
+         */
+        uint32_t clk16_oen:1;
+        /** clk32_oen : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to enable 32m clock
+         */
+        uint32_t clk32_oen:1;
+        /** clk_adc_inf_oen : R/W; bitpos: [3]; default: 1;
+         *  Reserved
+         */
+        uint32_t clk_adc_inf_oen:1;
+        /** clk_dfm_inf_oen : R/W; bitpos: [4]; default: 1;
+         *  Reserved
+         */
+        uint32_t clk_dfm_inf_oen:1;
+        /** clk_sdm_mod_oen : R/W; bitpos: [5]; default: 1;
+         *  Reserved
+         */
+        uint32_t clk_sdm_mod_oen:1;
+        /** clk_xtal_oen : R/W; bitpos: [6]; default: 1;
+         *  Set 1 to enable xtal clock
+         */
+        uint32_t clk_xtal_oen:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} pcr_ctrl_clk_out_en_reg_t;
+
+/** Type of ctrl_tick_conf register
+ *  TICK configuration register
+ */
+typedef union {
+    struct {
+        /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39;
+         *  ******* Description ***********
+         */
+        uint32_t xtal_tick_num:8;
+        /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7;
+         *  ******* Description ***********
+         */
+        uint32_t fosc_tick_num:8;
+        /** tick_enable : R/W; bitpos: [16]; default: 1;
+         *  ******* Description ***********
+         */
+        uint32_t tick_enable:1;
+        /** rst_tick_cnt : R/W; bitpos: [17]; default: 0;
+         *  ******* Description ***********
+         */
+        uint32_t rst_tick_cnt:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} pcr_ctrl_tick_conf_reg_t;
+
+/** Type of ctrl_32k_conf register
+ *  32KHz clock configuration register
+ */
+typedef union {
+    struct {
+        /** 32k_sel : R/W; bitpos: [1:0]; default: 0;
+         *  This field indicates which one 32KHz clock will be used by timergroup. 0:
+         *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
+         */
+        uint32_t clk_32k_sel:2;
+        /** 32k_modem_sel : R/W; bitpos: [3:2]; default: 0;
+         *  This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0:
+         *  OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0.
+         */
+        uint32_t clk_32k_modem_sel:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcr_ctrl_32k_conf_reg_t;
+
+/** Type of sram_power_conf_0 register
+ *  HP SRAM/ROM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** rom_force_pu : R/W; bitpos: [14:13]; default: 3;
+         *  Set this bit to force power up ROM
+         */
+        uint32_t rom_force_pu:2;
+        /** rom_force_pd : R/W; bitpos: [16:15]; default: 0;
+         *  Set this bit to force power down ROM.
+         */
+        uint32_t rom_force_pd:2;
+        /** rom_clkgate_force_on : R/W; bitpos: [18:17]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A
+         *  gate-clock will be used when accessing the ROM.
+         */
+        uint32_t rom_clkgate_force_on:2;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} pcr_sram_power_conf_0_reg_t;
+
+/** Type of sram_power_conf_1 register
+ *  HP SRAM/ROM configuration register
+ */
+typedef union {
+    struct {
+        /** sram_force_pu : R/W; bitpos: [4:0]; default: 31;
+         *  Set this bit to force power up SRAM
+         */
+        uint32_t sram_force_pu:5;
+        uint32_t reserved_5:5;
+        /** sram_force_pd : R/W; bitpos: [14:10]; default: 0;
+         *  Set this bit to force power down SRAM.
+         */
+        uint32_t sram_force_pd:5;
+        uint32_t reserved_15:10;
+        /** sram_clkgate_force_on : R/W; bitpos: [29:25]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A
+         *  gate-clock will be used when accessing the SRAM.
+         */
+        uint32_t sram_clkgate_force_on:5;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} pcr_sram_power_conf_1_reg_t;
+
+/** Type of sec_conf register
+ *  xxxx
+ */
+typedef union {
+    struct {
+        /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  xxxx
+         */
+        uint32_t sec_clk_sel:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_sec_conf_reg_t;
+
+/** Type of adc_inv_phase_conf register
+ *  xxxx
+ */
+typedef union {
+    struct {
+        /** clk_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0;
+         *  xxxx
+         */
+        uint32_t clk_adc_inv_phase_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} pcr_adc_inv_phase_conf_reg_t;
+
+/** Type of sdm_inv_phase_conf register
+ *  xxxx
+ */
+typedef union {
+    struct {
+        /** clk_sdm_inv_phase_ena : R/W; bitpos: [0]; default: 0;
+         *  xxxx
+         */
+        uint32_t clk_sdm_inv_phase_ena:1;
+        /** clk_sdm_inv_phase_sel : R/W; bitpos: [3:1]; default: 0;
+         *  xxxx
+         */
+        uint32_t clk_sdm_inv_phase_sel:3;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} pcr_sdm_inv_phase_conf_reg_t;
+
+/** Type of bus_clk_update register
+ *  xxxx
+ */
+typedef union {
+    struct {
+        /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0;
+         *  xxxx
+         */
+        uint32_t bus_clock_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} pcr_bus_clk_update_reg_t;
+
+/** Type of sar_clk_div register
+ *  xxxx
+ */
+typedef union {
+    struct {
+        /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4;
+         *  xxxx
+         */
+        uint32_t sar2_clk_div_num:8;
+        /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4;
+         *  xxxx
+         */
+        uint32_t sar1_clk_div_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} pcr_sar_clk_div_reg_t;
+
+/** Type of pwdet_sar_clk_conf register
+ *  xxxx
+ */
+typedef union {
+    struct {
+        /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7;
+         *  xxxx
+         */
+        uint32_t pwdet_sar_clk_div_num:8;
+        /** pwdet_sar_reader_en : R/W; bitpos: [8]; default: 1;
+         *  xxxx
+         */
+        uint32_t pwdet_sar_reader_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} pcr_pwdet_sar_clk_conf_reg_t;
+
+/** Type of reset_event_bypass register
+ *  reset event bypass backdoor configuration register
+ */
+typedef union {
+    struct {
+        /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0;
+         *  This field is used to control reset event relationship for
+         *  tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset
+         *  by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg
+         *  will not only be reset by power-reset, but also some reset event.
+         */
+        uint32_t reset_event_bypass_apm:1;
+        /** reset_event_bypass : R/W; bitpos: [1]; default: 1;
+         *  This field is used to control reset event relationship for system-bus. 1: system
+         *  bus (including arbiter/router) will only be reset by power-reset. some reset event
+         *  will be bypass. 0: system bus (including arbiter/router) will not only be reset by
+         *  power-reset, but also some reset event.
+         */
+        uint32_t reset_event_bypass:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} pcr_reset_event_bypass_reg_t;
+
+/** Type of clock_gate register
+ *  PCR clock gating configure register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to force on clock gating.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} pcr_clock_gate_reg_t;
+
+
+/** Group: Frequency Statistics Register */
+/** Type of sysclk_freq_query_0 register
+ *  SYSCLK frequency query 0 register
+ */
+typedef union {
+    struct {
+        /** fosc_freq : HRO; bitpos: [7:0]; default: 8;
+         *  This field indicates the frequency(MHz) of FOSC.
+         */
+        uint32_t fosc_freq:8;
+        /** pll_freq : HRO; bitpos: [17:8]; default: 96;
+         *  This field indicates the frequency(MHz) of SPLL.
+         */
+        uint32_t pll_freq:10;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} pcr_sysclk_freq_query_0_reg_t;
+
+
+/** Group: FPGA Debug Register */
+/** Type of fpga_debug register
+ *  fpga debug register
+ */
+typedef union {
+    struct {
+        /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Only used in fpga debug.
+         */
+        uint32_t fpga_debug:32;
+    };
+    uint32_t val;
+} pcr_fpga_debug_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35717248;
+         *  PCR version information.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} pcr_date_reg_t;
+
+
+/**
+ * @brief The struct of I2C configuration registers
+ */
+typedef struct {
+    pcr_i2c_conf_reg_t i2c_conf;
+    pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
+} pcr_i2c_reg_t;
+
+typedef struct {
+    volatile pcr_uart0_conf_reg_t uart0_conf;
+    volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf;
+    volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl;
+    volatile pcr_uart1_conf_reg_t uart1_conf;
+    volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf;
+    volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl;
+    volatile pcr_mspi_conf_reg_t mspi_conf;
+    volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf;
+    volatile pcr_i2c_reg_t i2c[2];
+    volatile pcr_uhci_conf_reg_t uhci_conf;
+    volatile pcr_rmt_conf_reg_t rmt_conf;
+    volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf;
+    volatile pcr_ledc_conf_reg_t ledc_conf;
+    volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf;
+    volatile pcr_timergroup0_conf_reg_t timergroup0_conf;
+    volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf;
+    volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf;
+    volatile pcr_timergroup1_conf_reg_t timergroup1_conf;
+    volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf;
+    volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf;
+    volatile pcr_systimer_conf_reg_t systimer_conf;
+    volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf;
+    volatile pcr_twai0_conf_reg_t twai0_conf;
+    volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf;
+    volatile pcr_i2s_conf_reg_t i2s_conf;
+    volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf;
+    volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf;
+    volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf;
+    volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf;
+    volatile pcr_saradc_conf_reg_t saradc_conf;
+    volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf;
+    volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf;
+    volatile pcr_usb_device_conf_reg_t usb_device_conf;
+    volatile pcr_intmtx_conf_reg_t intmtx_conf;
+    volatile pcr_pcnt_conf_reg_t pcnt_conf;
+    volatile pcr_etm_conf_reg_t etm_conf;
+    volatile pcr_pwm_conf_reg_t pwm_conf;
+    volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf;
+    volatile pcr_parl_io_conf_reg_t parl_io_conf;
+    volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf;
+    volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf;
+    volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf;
+    volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf;
+    volatile pcr_gdma_conf_reg_t gdma_conf;
+    volatile pcr_spi2_conf_reg_t spi2_conf;
+    volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf;
+    volatile pcr_aes_conf_reg_t aes_conf;
+    volatile pcr_sha_conf_reg_t sha_conf;
+    volatile pcr_rsa_conf_reg_t rsa_conf;
+    volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
+    volatile pcr_ecc_conf_reg_t ecc_conf;
+    volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
+    volatile pcr_ds_conf_reg_t ds_conf;
+    volatile pcr_hmac_conf_reg_t hmac_conf;
+    volatile pcr_ecdsa_conf_reg_t ecdsa_conf;
+    volatile pcr_iomux_conf_reg_t iomux_conf;
+    volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf;
+    volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf;
+    volatile pcr_regdma_conf_reg_t regdma_conf;
+    volatile pcr_trace_conf_reg_t trace_conf;
+    volatile pcr_assist_conf_reg_t assist_conf;
+    volatile pcr_cache_conf_reg_t cache_conf;
+    volatile pcr_modem_conf_reg_t modem_conf;
+    volatile pcr_timeout_conf_reg_t timeout_conf;
+    volatile pcr_sysclk_conf_reg_t sysclk_conf;
+    volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf;
+    volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf;
+    volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf;
+    volatile pcr_apb_freq_conf_reg_t apb_freq_conf;
+    volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0;
+    volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en;
+    volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en;
+    volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf;
+    volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf;
+    volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0;
+    volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1;
+    volatile pcr_sec_conf_reg_t sec_conf;
+    volatile pcr_adc_inv_phase_conf_reg_t adc_inv_phase_conf;
+    volatile pcr_sdm_inv_phase_conf_reg_t sdm_inv_phase_conf;
+    volatile pcr_bus_clk_update_reg_t bus_clk_update;
+    volatile pcr_sar_clk_div_reg_t sar_clk_div;
+    volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf;
+    uint32_t reserved_154[935];
+    volatile pcr_reset_event_bypass_reg_t reset_event_bypass;
+    volatile pcr_fpga_debug_reg_t fpga_debug;
+    volatile pcr_clock_gate_reg_t clock_gate;
+    volatile pcr_date_reg_t date;
+} pcr_dev_t;
+
+extern pcr_dev_t PCR;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/plic_reg.h b/components/soc/esp32h2/register/soc/plic_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/plic_reg.h
rename to components/soc/esp32h2/register/soc/plic_reg.h
diff --git a/components/soc/esp32h2/include/soc/pmu_reg.h b/components/soc/esp32h2/register/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/pmu_reg.h
rename to components/soc/esp32h2/register/soc/pmu_reg.h
diff --git a/components/soc/esp32h2/include/soc/pmu_struct.h b/components/soc/esp32h2/register/soc/pmu_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/pmu_struct.h
rename to components/soc/esp32h2/register/soc/pmu_struct.h
diff --git a/components/soc/esp32h2/register/soc/reg_base.h b/components/soc/esp32h2/register/soc/reg_base.h
new file mode 100644
index 00000000000..1a5a0e4f0a6
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/reg_base.h
@@ -0,0 +1,72 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DR_REG_UART_BASE                        0x60000000
+#define DR_REG_UART1_BASE                       0x60001000
+#define DR_REG_SPI0_BASE                        0x60002000
+#define DR_REG_SPI1_BASE                        0x60003000
+#define DR_REG_I2C_EXT0_BASE                    0x60004000
+#define DR_REG_I2C_EXT1_BASE                    0x60005000
+#define DR_REG_UHCI0_BASE                       0x60006000
+#define DR_REG_RMT_BASE                         0x60007000
+#define DR_REG_LEDC_BASE                        0x60008000
+#define DR_REG_TIMERGROUP0_BASE                 0x60009000
+#define DR_REG_TIMERGROUP1_BASE                 0x6000A000
+#define DR_REG_SYSTIMER_BASE                    0x6000B000
+#define DR_REG_TWAI_BASE                        0x6000C000
+#define DR_REG_I2S_BASE                         0x6000D000
+#define DR_REG_APB_SARADC_BASE                  0x6000E000
+#define DR_REG_USB_SERIAL_JTAG_BASE             0x6000F000
+#define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
+#define DR_REG_PCNT_BASE                        0x60012000
+#define DR_REG_SOC_ETM_BASE                     0x60013000
+#define DR_REG_MCPWM_BASE                       0x60014000
+#define DR_REG_PARL_IO_BASE                     0x60015000
+#define DR_REG_PVT_MONITOR_BASE                 0x60019000
+#define DR_REG_GDMA_BASE                        0x60080000
+#define DR_REG_SPI2_BASE                        0x60081000
+#define DR_REG_AES_BASE                         0x60088000
+#define DR_REG_SHA_BASE                         0x60089000
+#define DR_REG_RSA_BASE                         0x6008A000
+#define DR_REG_ECC_MULT_BASE                    0x6008B000
+#define DR_REG_DS_BASE                          0x6008C000
+#define DR_REG_HMAC_BASE                        0x6008D000
+#define DR_REG_ECDSA_BASE                       0x6008E000
+#define DR_REG_IO_MUX_BASE                      0x60090000
+#define DR_REG_MEM_MONITOR_BASE                 0x60092000
+#define DR_REG_PAU_BASE                         0x60093000
+#define DR_REG_LPPERI_BASE                      0x600B2800
+#define DR_REG_GPIO_BASE                        0x60091000
+#define DR_REG_GPIO_EXT_BASE                    0x60091f00
+#define DR_REG_MEM_ACS_MONITOR_BASE             0x60092000
+#define DR_REG_REGDMA_BASE                      0x60093000
+#define DR_REG_HP_SYSTEM_BASE                   0x60095000
+#define DR_REG_PCR_BASE                         0x60096000
+#define DR_REG_TEE_BASE                         0x60098000
+#define DR_REG_HP_APM_BASE                      0x60099000
+#define DR_REG_LP_APM0_BASE                     0x60099800
+#define DR_REG_MISC_BASE                        0x6009F000
+
+#define DR_REG_I2C_ANA_MST_BASE                 0x600AD800
+
+#define DR_REG_PMU_BASE                         0x600B0000
+#define DR_REG_LP_CLKRST_BASE                   0x600B0400
+#define DR_REG_EFUSE_BASE                       0x600B0800
+#define DR_REG_LP_TIMER_BASE                    0x600B0C00
+#define DR_REG_LP_AON_BASE                      0x600B1000
+#define DR_REG_LP_WDT_BASE                      0x600B1C00
+#define DR_REG_LP_IO_BASE                       0x600B2000
+#define DR_REG_LP_ANALOG_PERI_BASE              0x600B2C00
+#define DR_REG_LP_APM_BASE                      0x600B3800
+#define DR_REG_OTP_DEBUG_BASE                   0x600B3C00
+
+#define DR_REG_TRACE_BASE                       0x600C0000
+#define DR_REG_ASSIST_DEBUG_BASE                0x600C2000
+#define DR_REG_INTPRI_BASE                      0x600C5000
+#define DR_REG_CACHE_BASE                       0x600C8000
+
+#define PWDET_CONF_REG                          0x600A0810
+#define IEEE802154_REG_BASE                     0x600A3000
diff --git a/components/soc/esp32h2/include/soc/rmt_reg.h b/components/soc/esp32h2/register/soc/rmt_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/rmt_reg.h
rename to components/soc/esp32h2/register/soc/rmt_reg.h
diff --git a/components/soc/esp32h2/include/soc/rmt_struct.h b/components/soc/esp32h2/register/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/rmt_struct.h
rename to components/soc/esp32h2/register/soc/rmt_struct.h
diff --git a/components/soc/esp32h2/include/soc/rsa_reg.h b/components/soc/esp32h2/register/soc/rsa_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/rsa_reg.h
rename to components/soc/esp32h2/register/soc/rsa_reg.h
diff --git a/components/soc/esp32h2/include/soc/rsa_struct.h b/components/soc/esp32h2/register/soc/rsa_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/rsa_struct.h
rename to components/soc/esp32h2/register/soc/rsa_struct.h
diff --git a/components/soc/esp32h2/register/soc/sha_reg.h b/components/soc/esp32h2/register/soc/sha_reg.h
new file mode 100644
index 00000000000..633d53446c7
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/sha_reg.h
@@ -0,0 +1,172 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SHA_MODE_REG register
+ *  Initial configuration register.
+ */
+#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
+/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Sha mode.
+ */
+#define SHA_MODE    0x00000007U
+#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
+#define SHA_MODE_V  0x00000007U
+#define SHA_MODE_S  0
+
+/** SHA_T_STRING_REG register
+ *  SHA 512/t configuration register 0.
+ */
+#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
+/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
+ *  Sha t_string (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_STRING    0xFFFFFFFFU
+#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
+#define SHA_T_STRING_V  0xFFFFFFFFU
+#define SHA_T_STRING_S  0
+
+/** SHA_T_LENGTH_REG register
+ *  SHA 512/t configuration register 1.
+ */
+#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
+/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
+ *  Sha t_length (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_LENGTH    0x0000003FU
+#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
+#define SHA_T_LENGTH_V  0x0000003FU
+#define SHA_T_LENGTH_S  0
+
+/** SHA_DMA_BLOCK_NUM_REG register
+ *  DMA configuration register 0.
+ */
+#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
+/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
+ *  Dma-sha block number.
+ */
+#define SHA_DMA_BLOCK_NUM    0x0000003FU
+#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
+#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
+#define SHA_DMA_BLOCK_NUM_S  0
+
+/** SHA_START_REG register
+ *  Typical SHA configuration register 0.
+ */
+#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
+/** SHA_START : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_START    0x7FFFFFFFU
+#define SHA_START_M  (SHA_START_V << SHA_START_S)
+#define SHA_START_V  0x7FFFFFFFU
+#define SHA_START_S  1
+
+/** SHA_CONTINUE_REG register
+ *  Typical SHA configuration register 1.
+ */
+#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
+/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_CONTINUE    0x7FFFFFFFU
+#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
+#define SHA_CONTINUE_V  0x7FFFFFFFU
+#define SHA_CONTINUE_S  1
+
+/** SHA_BUSY_REG register
+ *  Busy register.
+ */
+#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
+/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Sha busy state. 1'b0: idle. 1'b1: busy.
+ */
+#define SHA_BUSY_STATE    (BIT(0))
+#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
+#define SHA_BUSY_STATE_V  0x00000001U
+#define SHA_BUSY_STATE_S  0
+
+/** SHA_DMA_START_REG register
+ *  DMA configuration register 1.
+ */
+#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
+/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
+ *  Start dma-sha.
+ */
+#define SHA_DMA_START    (BIT(0))
+#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
+#define SHA_DMA_START_V  0x00000001U
+#define SHA_DMA_START_S  0
+
+/** SHA_DMA_CONTINUE_REG register
+ *  DMA configuration register 2.
+ */
+#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
+/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Continue dma-sha.
+ */
+#define SHA_DMA_CONTINUE    (BIT(0))
+#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
+#define SHA_DMA_CONTINUE_V  0x00000001U
+#define SHA_DMA_CONTINUE_S  0
+
+/** SHA_CLEAR_IRQ_REG register
+ *  Interrupt clear register.
+ */
+#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
+/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
+ *  Clear sha interrupt.
+ */
+#define SHA_CLEAR_INTERRUPT    (BIT(0))
+#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
+#define SHA_CLEAR_INTERRUPT_V  0x00000001U
+#define SHA_CLEAR_INTERRUPT_S  0
+
+/** SHA_IRQ_ENA_REG register
+ *  Interrupt enable register.
+ */
+#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
+/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+ */
+#define SHA_INTERRUPT_ENA    (BIT(0))
+#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
+#define SHA_INTERRUPT_ENA_V  0x00000001U
+#define SHA_INTERRUPT_ENA_S  0
+
+/** SHA_DATE_REG register
+ *  Date register.
+ */
+#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
+/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
+ *  Sha date information/ sha version information.
+ */
+#define SHA_DATE    0x3FFFFFFFU
+#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
+#define SHA_DATE_V  0x3FFFFFFFU
+#define SHA_DATE_S  0
+
+/** SHA_H_MEM register
+ *  Sha H memory which contains intermediate hash or final hash.
+ */
+#define SHA_H_MEM_REG (DR_REG_SHA_BASE + 0x40)
+#define SHA_H_MEM_SIZE_BYTES 64
+
+/** SHA_M_MEM register
+ *  Sha M memory which contains message.
+ */
+#define SHA_M_MEM_REG (DR_REG_SHA_BASE + 0x80)
+#define SHA_M_MEM_SIZE_BYTES 64
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/sha_struct.h b/components/soc/esp32h2/register/soc/sha_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/sha_struct.h
rename to components/soc/esp32h2/register/soc/sha_struct.h
diff --git a/components/soc/esp32h2/include/soc/soc_etm_reg.h b/components/soc/esp32h2/register/soc/soc_etm_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/soc_etm_reg.h
rename to components/soc/esp32h2/register/soc/soc_etm_reg.h
diff --git a/components/soc/esp32h2/include/soc/soc_etm_struct.h b/components/soc/esp32h2/register/soc/soc_etm_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/soc_etm_struct.h
rename to components/soc/esp32h2/register/soc/soc_etm_struct.h
diff --git a/components/soc/esp32h2/register/soc/spi_mem_reg.h b/components/soc/esp32h2/register/soc/spi_mem_reg.h
new file mode 100644
index 00000000000..1f084a0acc1
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/spi_mem_reg.h
@@ -0,0 +1,3085 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
+/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_READ    (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
+bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WREN    (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when the bit is set. The
+ bit will be cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_WRDI    (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
+e cleared once the operation done. 1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDID    (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered when the bit is
+ set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RDSR    (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will be triggered when t
+he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
+ble..*/
+#define SPI_MEM_FLASH_WRSR    (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed). Page program opera
+tion  will be triggered when the bit is set. The bit will be cleared once the op
+eration done .1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PP    (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
+is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_SE    (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
+ is set. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_BE    (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_CE    (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
+. The bit will be cleared once the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_DP    (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
+e or high performance mode and obtains the devices ID. The bit will be cleared once
+the operation done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_RES    (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared once the operation
+done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_HPM    (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation
+will be triggered when the bit is set. The bit will be cleared once the operation
+done.1: enable 0: disable..*/
+#define SPI_MEM_USR    (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode, it is set to indicate that program/erase operation will be trigger
+ed. The bit is combined with spi_mem_usr bit. The bit will be cleared once the o
+peration done.1: enable 0: disable..*/
+#define SPI_MEM_FLASH_PE    (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+/* SPI_MEM_SLV_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation
+state, 2: send command state, 3: send address state, 4: wait state, 5: read data state
+, 6:write data state, 7: done state, 8: read data end state..*/
+#define SPI_MEM_SLV_ST    0x0000000F
+#define SPI_MEM_SLV_ST_M  ((SPI_MEM_SLV_ST_V)<<(SPI_MEM_SLV_ST_S))
+#define SPI_MEM_SLV_ST_V  0xF
+#define SPI_MEM_SLV_ST_S  4
+/* SPI_MEM_MST_ST : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT
+, 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA se
+nt data is stored in SPI0 TX FIFO, 5: SPI0 write data state..*/
+#define SPI_MEM_MST_ST    0x0000000F
+#define SPI_MEM_MST_ST_M  ((SPI_MEM_MST_ST_V)<<(SPI_MEM_MST_ST_S))
+#define SPI_MEM_MST_ST_V  0xF
+#define SPI_MEM_MST_ST_S  0
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
+address, the bit24-bit31 are the byte length of a transfer..*/
+#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
+/* SPI_MEM_DATA_IE_ALWAYS_ON : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are a
+lways 1. 0: Others..*/
+#define SPI_MEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
+#define SPI_MEM_DATA_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_DATA_IE_ALWAYS_ON_S  31
+/* SPI_MEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always
+s 1. 0: Others..*/
+#define SPI_MEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
+#define SPI_MEM_DQS_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_DQS_IE_ALWAYS_ON_S  30
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 4 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_QIO    (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply 2 signals. 1: ena
+ble 0: disable..*/
+#define SPI_MEM_FREAD_DIO    (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is set. 1: enable 0: d
+isable..*/
+#define SPI_MEM_WRSR_2B    (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low..*/
+#define SPI_MEM_WP_REG    (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
+#define SPI_MEM_D_POL    (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
+#define SPI_MEM_Q_POL    (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
+spi_mem_flash_res bit. 1: enable 0: disable..*/
+#define SPI_MEM_RESANDRES    (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable..*/
+#define SPI_MEM_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QO
+UT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
+#define SPI_MEM_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : HRO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+e.*/
+#define SPI_MEM_TX_CRC_EN    (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : HRO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
+e low..*/
+#define SPI_MEM_FCS_CRC_EN    (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_OCT : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 8 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_OCT    (BIT(9))
+#define SPI_MEM_FCMD_OCT_M  (BIT(9))
+#define SPI_MEM_FCMD_OCT_V  0x1
+#define SPI_MEM_FCMD_OCT_S  9
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable.*/
+#define SPI_MEM_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FADDR_OCT : HRO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 8 signals during address phase 1:enable 0: disable.*/
+#define SPI_MEM_FADDR_OCT    (BIT(6))
+#define SPI_MEM_FADDR_OCT_M  (BIT(6))
+#define SPI_MEM_FADDR_OCT_V  0x1
+#define SPI_MEM_FADDR_OCT_S  6
+/* SPI_MEM_FDIN_OCT : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 8 signals during read-data phase 1:enable 0: disable.*/
+#define SPI_MEM_FDIN_OCT    (BIT(5))
+#define SPI_MEM_FDIN_OCT_M  (BIT(5))
+#define SPI_MEM_FDIN_OCT_V  0x1
+#define SPI_MEM_FDIN_OCT_S  5
+/* SPI_MEM_FDOUT_OCT : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Apply 8 signals during write-data phase 1:enable 0: disable.*/
+#define SPI_MEM_FDOUT_OCT    (BIT(4))
+#define SPI_MEM_FDOUT_OCT_M  (BIT(4))
+#define SPI_MEM_FDOUT_OCT_V  0x1
+#define SPI_MEM_FDOUT_OCT_S  4
+/* SPI_MEM_FDUMMY_WOUT : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0]
+is output by the MSPI controller in the second half part of dummy phase. It is u
+sed to pre-drive flash..*/
+#define SPI_MEM_FDUMMY_WOUT    (BIT(3))
+#define SPI_MEM_FDUMMY_WOUT_M  (BIT(3))
+#define SPI_MEM_FDUMMY_WOUT_V  0x1
+#define SPI_MEM_FDUMMY_WOUT_S  3
+/* SPI_MEM_FDUMMY_RIN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] i
+s output by the MSPI controller in the first half part of dummy phase. It is use
+d to mask invalid SPI_DQS in the half part of dummy phase..*/
+#define SPI_MEM_FDUMMY_RIN    (BIT(2))
+#define SPI_MEM_FDUMMY_RIN_M  (BIT(2))
+#define SPI_MEM_FDUMMY_RIN_V  0x1
+#define SPI_MEM_FDUMMY_RIN_S  2
+/* SPI_MEM_WDUMMY_ALWAYS_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
+vel of SPI_IO[7:0] is output by the MSPI controller..*/
+#define SPI_MEM_WDUMMY_ALWAYS_OUT    (BIT(1))
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_M  (BIT(1))
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_V  0x1
+#define SPI_MEM_WDUMMY_ALWAYS_OUT_S  1
+/* SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to flash, the le
+vel of SPI_DQS is output by the MSPI controller..*/
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(0))
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(0))
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
+#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S  0
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
+/* SPI_MEM_TXFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to
+ send signals to AXI. Set this bit to reset these FIFO..*/
+#define SPI_MEM_TXFIFO_RST    (BIT(31))
+#define SPI_MEM_TXFIFO_RST_M  (BIT(31))
+#define SPI_MEM_TXFIFO_RST_V  0x1
+#define SPI_MEM_TXFIFO_RST_S  31
+/* SPI_MEM_RXFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to
+ receive signals from AXI.  Set this bit to reset these FIFO..*/
+#define SPI_MEM_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_V  0x1
+#define SPI_MEM_RXFIFO_RST_S  30
+/* SPI_MEM_FAST_WRITE_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to write data faster, do not wait write data has been stored in tx_
+bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored
+in  tx_bus_fifo_l2..*/
+#define SPI_MEM_FAST_WRITE_EN    (BIT(29))
+#define SPI_MEM_FAST_WRITE_EN_M  (BIT(29))
+#define SPI_MEM_FAST_WRITE_EN_V  0x1
+#define SPI_MEM_FAST_WRITE_EN_S  29
+/* SPI_MEM_DUAL_RAM_EN : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at
+the same time..*/
+#define SPI_MEM_DUAL_RAM_EN    (BIT(28))
+#define SPI_MEM_DUAL_RAM_EN_M  (BIT(28))
+#define SPI_MEM_DUAL_RAM_EN_V  0x1
+#define SPI_MEM_DUAL_RAM_EN_S  28
+/* SPI_MEM_RAM0_EN : HRO ;bitpos:[27] ;default: 1'b1 ; */
+/*description: When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be ac
+cessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 wi
+ll be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be ac
+cessed at the same time..*/
+#define SPI_MEM_RAM0_EN    (BIT(27))
+#define SPI_MEM_RAM0_EN_M  (BIT(27))
+#define SPI_MEM_RAM0_EN_V  0x1
+#define SPI_MEM_RAM0_EN_S  27
+/* SPI_MEM_AW_SPLICE_EN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable AXI Write Splice-transfer..*/
+#define SPI_MEM_AW_SPLICE_EN    (BIT(26))
+#define SPI_MEM_AW_SPLICE_EN_M  (BIT(26))
+#define SPI_MEM_AW_SPLICE_EN_V  0x1
+#define SPI_MEM_AW_SPLICE_EN_S  26
+/* SPI_MEM_AR_SPLICE_EN : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to enable AXI Read Splice-transfer..*/
+#define SPI_MEM_AR_SPLICE_EN    (BIT(25))
+#define SPI_MEM_AR_SPLICE_EN_M  (BIT(25))
+#define SPI_MEM_AR_SPLICE_EN_V  0x1
+#define SPI_MEM_AR_SPLICE_EN_S  25
+/* SPI_MEM_RRESP_ECC_ERR_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
+ when there is a ECC error in AXI read data. The ECC error information is record
+ed in SPI_MEM_ECC_ERR_ADDR_REG..*/
+#define SPI_MEM_RRESP_ECC_ERR_EN    (BIT(24))
+#define SPI_MEM_RRESP_ECC_ERR_EN_M  (BIT(24))
+#define SPI_MEM_RRESP_ECC_ERR_EN_V  0x1
+#define SPI_MEM_RRESP_ECC_ERR_EN_S  24
+/* SPI_MEM_AXI_RDATA_BACK_FAST : HRO ;bitpos:[23] ;default: 1'b1 ; */
+/*description: 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: R
+eply AXI read data to AXI bus when all the read data is available..*/
+#define SPI_MEM_AXI_RDATA_BACK_FAST    (BIT(23))
+#define SPI_MEM_AXI_RDATA_BACK_FAST_M  (BIT(23))
+#define SPI_MEM_AXI_RDATA_BACK_FAST_V  0x1
+#define SPI_MEM_AXI_RDATA_BACK_FAST_S  23
+/* SPI_MEM_AW_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR..*/
+#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN    (BIT(22))
+#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_M  (BIT(22))
+#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_V  0x1
+#define SPI_MEM_AW_SIZE0_1_SUPPORT_EN_S  22
+/* SPI_MEM_AR_SIZE0_1_SUPPORT_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and repl
+y the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR..*/
+#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN    (BIT(21))
+#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_M  (BIT(21))
+#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_V  0x1
+#define SPI_MEM_AR_SIZE0_1_SUPPORT_EN_S  21
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
+/*description: After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 5
+12) SPI_CLK cycles..*/
+#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on..*/
+#define SPI_MEM_CLK_MODE    0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
+/* SPI_MEM_SYNC_RESET : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The spi0_mst_st and spi0_slv_st will be reset..*/
+#define SPI_MEM_SYNC_RESET    (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
+ clock cycles..*/
+#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_SPLIT_TRANS_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 split one AXI read flash transfer into two SPI trans
+fers when one transfer will cross flash or EXT_RAM page corner, valid no matter
+whether there is an ECC region or not..*/
+#define SPI_MEM_SPLIT_TRANS_EN    (BIT(24))
+#define SPI_MEM_SPLIT_TRANS_EN_M  (BIT(24))
+#define SPI_MEM_SPLIT_TRANS_EN_V  0x1
+#define SPI_MEM_SPLIT_TRANS_EN_S  24
+/* SPI_MEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+accesses flash..*/
+#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
+#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
+#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
+#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
+/* SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[13] ;default: 1'b1 ; */
+/*description: 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner w
+hen accesses flash..*/
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
+/* SPI_MEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
+ mode when accessed flash..*/
+#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
+#define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
+#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
+#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined wi
+th SPI_MEM_CS_HOLD bit..*/
+#define SPI_MEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_CS_HOLD_TIME_S  5
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_ME
+M_CS_SETUP bit..*/
+#define SPI_MEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module
+ clock..*/
+#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+ system/(spi_mem_clkcnt_N+1).*/
+#define SPI_MEM_CLKCNT_N    0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define SPI_MEM_CLKCNT_H    0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N..*/
+#define SPI_MEM_CLKCNT_L    0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation..*/
+#define SPI_MEM_USR_COMMAND    (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation..*/
+#define SPI_MEM_USR_ADDR    (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation..*/
+#define SPI_MEM_USR_DUMMY    (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation..*/
+#define SPI_MEM_USR_MISO    (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation..*/
+#define SPI_MEM_USR_MOSI    (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable..*/
+#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+1: enable 0: disable..*/
+#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1
+: enable 0: disable..*/
+#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals..*/
+#define SPI_MEM_FWRITE_QIO    (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals..*/
+#define SPI_MEM_FWRITE_DIO    (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals.*/
+#define SPI_MEM_FWRITE_QUAD    (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals.*/
+#define SPI_MEM_FWRITE_DUAL    (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3..*/
+#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_SETUP    (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable..*/
+#define SPI_MEM_CS_HOLD    (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DBYTELEN : HRO ;bitpos:[8:6] ;default: 3'd1 ; */
+/*description: SPI0 USR_CMD read or write data byte length -1.*/
+#define SPI_MEM_USR_DBYTELEN    0x00000007
+#define SPI_MEM_USR_DBYTELEN_M  ((SPI_MEM_USR_DBYTELEN_V)<<(SPI_MEM_USR_DBYTELEN_S))
+#define SPI_MEM_USR_DBYTELEN_V  0x7
+#define SPI_MEM_USR_DBYTELEN_S  6
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cy
+cle_num-1)..*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command..*/
+#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode b
+it..*/
+#define SPI_MEM_WB_MODE    0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit..*/
+#define SPI_MEM_STATUS    0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: SPI_CS line keep low when the bit is set..*/
+#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_CLK line is high when idle     0: spi clk line is low when idle.*/
+#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_SSUB_PIN : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0,  sram is connected to SUBPINs..*/
+#define SPI_MEM_SSUB_PIN    (BIT(8))
+#define SPI_MEM_SSUB_PIN_M  (BIT(8))
+#define SPI_MEM_SSUB_PIN_V  0x1
+#define SPI_MEM_SSUB_PIN_S  8
+/* SPI_MEM_FSUB_PIN : HRO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0,  flash is connected to SUBPINs..*/
+#define SPI_MEM_FSUB_PIN    (BIT(7))
+#define SPI_MEM_FSUB_PIN_M  (BIT(7))
+#define SPI_MEM_FSUB_PIN_V  0x1
+#define SPI_MEM_FSUB_PIN_S  7
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS1_DIS    (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI d
+evice, such as flash, external RAM and so on..*/
+#define SPI_MEM_CS0_DIS    (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: For SPI1, the value of crc32..*/
+#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
+/* SPI_MEM_CLOSE_AXI_INF_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to close AXI read/write transfer to MSPI, which means that only SLV
+_ERR will be replied to BRESP/RRESP..*/
+#define SPI_MEM_CLOSE_AXI_INF_EN    (BIT(31))
+#define SPI_MEM_CLOSE_AXI_INF_EN_M  (BIT(31))
+#define SPI_MEM_CLOSE_AXI_INF_EN_V  0x1
+#define SPI_MEM_CLOSE_AXI_INF_EN_S  31
+/* SPI_MEM_SAME_AW_AR_ADDR_CHK_EN : HRO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: Set this bit to check AXI read/write the same address region..*/
+#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN    (BIT(30))
+#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_M  (BIT(30))
+#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_V  0x1
+#define SPI_MEM_SAME_AW_AR_ADDR_CHK_EN_S  30
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_qio..*/
+#define SPI_MEM_FADDR_QUAD    (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is th
+e same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDOUT_QUAD    (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the
+ same with spi_mem_fread_qio..*/
+#define SPI_MEM_FDIN_QUAD    (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is
+ the same with spi_mem_fread_dio..*/
+#define SPI_MEM_FADDR_DUAL    (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+ same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDOUT_DUAL    (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+same with spi_mem_fread_dio..*/
+#define SPI_MEM_FDIN_DUAL    (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash for user define command, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable..*/
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE    (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S  1
+/* SPI_MEM_AXI_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, AXI master access enable, 1: enable, 0:disable..*/
+#define SPI_MEM_AXI_REQ_EN    (BIT(0))
+#define SPI_MEM_AXI_REQ_EN_M  (BIT(0))
+#define SPI_MEM_AXI_REQ_EN_V  0x1
+#define SPI_MEM_AXI_REQ_EN_S  0
+
+#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
+/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO ;bitpos:[27:22] ;default: 6'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of write dummy phas
+e. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
+/* SPI_MEM_SRAM_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: reserved.*/
+#define SPI_MEM_SRAM_OCT    (BIT(21))
+#define SPI_MEM_SRAM_OCT_M  (BIT(21))
+#define SPI_MEM_SRAM_OCT_V  0x1
+#define SPI_MEM_SRAM_OCT_S  21
+/* SPI_MEM_CACHE_SRAM_USR_WCMD : HRO ;bitpos:[20] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode cache write sram for user define command.*/
+#define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
+/* SPI_MEM_SRAM_ADDR_BITLEN : HRO ;bitpos:[19:14] ;default: 6'd23 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of address phase. T
+he register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
+#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
+/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO ;bitpos:[11:6] ;default: 6'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the length in bits of read dummy phase
+. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
+/* SPI_MEM_CACHE_SRAM_USR_RCMD : HRO ;bitpos:[5] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode cache read external RAM for user define command
+..*/
+#define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
+/* SPI_MEM_USR_RD_SRAM_DUMMY : HRO ;bitpos:[4] ;default: 1'b1 ; */
+/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read
+ operations..*/
+#define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
+/* SPI_MEM_USR_WR_SRAM_DUMMY : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, it is the enable bit of dummy phase for writ
+e operations..*/
+#define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
+/* SPI_MEM_USR_SRAM_QIO : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disab
+le.*/
+#define SPI_MEM_USR_SRAM_QIO    (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_V  0x1
+#define SPI_MEM_USR_SRAM_QIO_S  2
+/* SPI_MEM_USR_SRAM_DIO : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disab
+le.*/
+#define SPI_MEM_USR_SRAM_DIO    (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_V  0x1
+#define SPI_MEM_USR_SRAM_DIO_S  1
+/* SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: en
+able, 0:disable..*/
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE    (BIT(0))
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M  (BIT(0))
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S  0
+
+#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
+/* SPI_MEM_SMEM_DATA_IE_ALWAYS_ON : HRO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0
+] are always 1. 0: Others..*/
+#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON    (BIT(31))
+#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_M  (BIT(31))
+#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_SMEM_DATA_IE_ALWAYS_ON_S  31
+/* SPI_MEM_SMEM_DQS_IE_ALWAYS_ON : HRO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS ar
+e always 1. 0: Others..*/
+#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON    (BIT(30))
+#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_M  (BIT(30))
+#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_V  0x1
+#define SPI_MEM_SMEM_DQS_IE_ALWAYS_ON_S  30
+/* SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT : HRO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ the level of SPI_IO[7:0] is output by the MSPI controller..*/
+#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT    (BIT(25))
+#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_M  (BIT(25))
+#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_V  0x1
+#define SPI_MEM_SMEM_WDUMMY_ALWAYS_OUT_S  25
+/* SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the dummy phase of an MSPI write data transfer when accesses to external RAM,
+ the level of SPI_DQS is output by the MSPI controller..*/
+#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT    (BIT(24))
+#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_M  (BIT(24))
+#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_V  0x1
+#define SPI_MEM_SMEM_WDUMMY_DQS_ALWAYS_OUT_S  24
+/* SPI_MEM_SDUMMY_WOUT : HRO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the dummy phase of a MSPI write data transfer when accesses to external RAM,
+the signal level of SPI bus is output by the MSPI controller..*/
+#define SPI_MEM_SDUMMY_WOUT    (BIT(23))
+#define SPI_MEM_SDUMMY_WOUT_M  (BIT(23))
+#define SPI_MEM_SDUMMY_WOUT_V  0x1
+#define SPI_MEM_SDUMMY_WOUT_S  23
+/* SPI_MEM_SDUMMY_RIN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: In the dummy phase of a MSPI read data transfer when accesses to external RAM, t
+he signal level of SPI bus is output by the MSPI controller..*/
+#define SPI_MEM_SDUMMY_RIN    (BIT(22))
+#define SPI_MEM_SDUMMY_RIN_M  (BIT(22))
+#define SPI_MEM_SDUMMY_RIN_V  0x1
+#define SPI_MEM_SDUMMY_RIN_S  22
+/* SPI_MEM_SCMD_OCT : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SCMD_OCT    (BIT(21))
+#define SPI_MEM_SCMD_OCT_M  (BIT(21))
+#define SPI_MEM_SCMD_OCT_V  0x1
+#define SPI_MEM_SCMD_OCT_S  21
+/* SPI_MEM_SADDR_OCT : HRO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SADDR_OCT    (BIT(20))
+#define SPI_MEM_SADDR_OCT_M  (BIT(20))
+#define SPI_MEM_SADDR_OCT_V  0x1
+#define SPI_MEM_SADDR_OCT_S  20
+/* SPI_MEM_SDOUT_OCT : HRO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SDOUT_OCT    (BIT(19))
+#define SPI_MEM_SDOUT_OCT_M  (BIT(19))
+#define SPI_MEM_SDOUT_OCT_V  0x1
+#define SPI_MEM_SDOUT_OCT_S  19
+/* SPI_MEM_SDIN_OCT : HRO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable..*/
+#define SPI_MEM_SDIN_OCT    (BIT(18))
+#define SPI_MEM_SDIN_OCT_M  (BIT(18))
+#define SPI_MEM_SDIN_OCT_V  0x1
+#define SPI_MEM_SDIN_OCT_S  18
+/* SPI_MEM_SCMD_QUAD : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SCMD_QUAD    (BIT(17))
+#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
+#define SPI_MEM_SCMD_QUAD_V  0x1
+#define SPI_MEM_SCMD_QUAD_S  17
+/* SPI_MEM_SADDR_QUAD : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SADDR_QUAD    (BIT(16))
+#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
+#define SPI_MEM_SADDR_QUAD_V  0x1
+#define SPI_MEM_SADDR_QUAD_S  16
+/* SPI_MEM_SDOUT_QUAD : HRO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bi
+t is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SDOUT_QUAD    (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_V  0x1
+#define SPI_MEM_SDOUT_QUAD_S  15
+/* SPI_MEM_SDIN_QUAD : HRO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_qio..*/
+#define SPI_MEM_SDIN_QUAD    (BIT(14))
+#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
+#define SPI_MEM_SDIN_QUAD_V  0x1
+#define SPI_MEM_SDIN_QUAD_S  14
+/* SPI_MEM_SADDR_DUAL : HRO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The
+ bit is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SADDR_DUAL    (BIT(12))
+#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
+#define SPI_MEM_SADDR_DUAL_V  0x1
+#define SPI_MEM_SADDR_DUAL_S  12
+/* SPI_MEM_SDOUT_DUAL : HRO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bi
+t is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SDOUT_DUAL    (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_V  0x1
+#define SPI_MEM_SDOUT_DUAL_S  11
+/* SPI_MEM_SDIN_DUAL : HRO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit
+ is the same with spi_mem_usr_sram_dio..*/
+#define SPI_MEM_SDIN_DUAL    (BIT(10))
+#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
+#define SPI_MEM_SDIN_DUAL_V  0x1
+#define SPI_MEM_SDIN_DUAL_S  10
+/* SPI_MEM_SWB_MODE : HRO ;bitpos:[9:2] ;default: 8'b0 ; */
+/*description: Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd
+_mode bit..*/
+#define SPI_MEM_SWB_MODE    0x000000FF
+#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
+#define SPI_MEM_SWB_MODE_V  0xFF
+#define SPI_MEM_SWB_MODE_S  2
+/* SPI_MEM_SCLK_MODE : HRO ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on..*/
+#define SPI_MEM_SCLK_MODE    0x00000003
+#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
+#define SPI_MEM_SCLK_MODE_V  0x3
+#define SPI_MEM_SCLK_MODE_S  0
+
+#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the length in bits of command phase for
+ sram. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the read command value of command phase
+ for sram..*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the in bits of command phase  for sram.
+ The register value shall be (bit_num-1)..*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0,When cache mode is enable it is the write command value of command phas
+e for sram..*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
+/* SPI_MEM_SCLK_EQU_SYSCLK : HRO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_c
+lk is divided from system clock..*/
+#define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
+/* SPI_MEM_SCLKCNT_N : HRO ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_c
+lk frequency is system/(spi_mem_clkcnt_N+1).*/
+#define SPI_MEM_SCLKCNT_N    0x000000FF
+#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
+#define SPI_MEM_SCLKCNT_N_V  0xFF
+#define SPI_MEM_SCLKCNT_N_S  16
+/* SPI_MEM_SCLKCNT_H : HRO ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)..*/
+#define SPI_MEM_SCLKCNT_H    0x000000FF
+#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
+#define SPI_MEM_SCLKCNT_H_V  0xFF
+#define SPI_MEM_SCLKCNT_H_S  8
+/* SPI_MEM_SCLKCNT_L : HRO ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N..*/
+#define SPI_MEM_SCLKCNT_L    0x000000FF
+#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
+#define SPI_MEM_SCLKCNT_L_V  0xFF
+#define SPI_MEM_SCLKCNT_L_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
+/* SPI_MEM_LOCK_DELAY_TIME : R/W ;bitpos:[11:7] ;default: 5'd4 ; */
+/*description: The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1..*/
+#define SPI_MEM_LOCK_DELAY_TIME    0x0000001F
+#define SPI_MEM_LOCK_DELAY_TIME_M  ((SPI_MEM_LOCK_DELAY_TIME_V)<<(SPI_MEM_LOCK_DELAY_TIME_S))
+#define SPI_MEM_LOCK_DELAY_TIME_V  0x1F
+#define SPI_MEM_LOCK_DELAY_TIME_S  7
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
+/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF0    0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
+/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF1    0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
+/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF2    0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
+/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF3    0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
+/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF4    0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
+/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF5    0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
+/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF6    0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
+/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF7    0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
+/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF8    0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
+/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF9    0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
+/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF10    0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
+/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF11    0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
+/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF12    0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
+/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF13    0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
+/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF14    0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
+/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF15    0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: The command value to wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_CMD    0x0000FFFF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFFFF
+#define SPI_MEM_WAITI_CMD_S  16
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: The dummy cycle length when wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD_2B : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: 1:The wait idle command bit length is 16. 0: The wait idle command bit length is
+ 8..*/
+#define SPI_MEM_WAITI_CMD_2B    (BIT(9))
+#define SPI_MEM_WAITI_CMD_2B_M  (BIT(9))
+#define SPI_MEM_WAITI_CMD_2B_V  0x1
+#define SPI_MEM_WAITI_CMD_2B_S  9
+/* SPI_MEM_WAITI_ADDR_CYCLELEN : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI
+_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when
+SPI_MEM_WAITI_ADDR_EN is cleared..*/
+#define SPI_MEM_WAITI_ADDR_CYCLELEN    0x00000003
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_M  ((SPI_MEM_WAITI_ADDR_CYCLELEN_V)<<(SPI_MEM_WAITI_ADDR_CYCLELEN_S))
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_V  0x3
+#define SPI_MEM_WAITI_ADDR_CYCLELEN_S  3
+/* SPI_MEM_WAITI_ADDR_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out ad
+dress in RDSR or read SUS command transfer..*/
+#define SPI_MEM_WAITI_ADDR_EN    (BIT(2))
+#define SPI_MEM_WAITI_ADDR_EN_M  (BIT(2))
+#define SPI_MEM_WAITI_ADDR_EN_V  0x1
+#define SPI_MEM_WAITI_ADDR_EN_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The dummy phase enable when wait flash idle (RDSR).*/
+#define SPI_MEM_WAITI_DUMMY    (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
+ Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
+Suspend/Resume are not supported..*/
+#define SPI_MEM_WAITI_EN    (BIT(0))
+#define SPI_MEM_WAITI_EN_M  (BIT(0))
+#define SPI_MEM_WAITI_EN_V  0x1
+#define SPI_MEM_WAITI_EN_S  0
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
+/* SPI_MEM_SUS_TIMEOUT_CNT : R/W ;bitpos:[31:25] ;default: 7'h4 ; */
+/*description: When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
+ it will be treated as check pass..*/
+#define SPI_MEM_SUS_TIMEOUT_CNT    0x0000007F
+#define SPI_MEM_SUS_TIMEOUT_CNT_M  ((SPI_MEM_SUS_TIMEOUT_CNT_V)<<(SPI_MEM_SUS_TIMEOUT_CNT_S))
+#define SPI_MEM_SUS_TIMEOUT_CNT_V  0x7F
+#define SPI_MEM_SUS_TIMEOUT_CNT_S  25
+/* SPI_MEM_PES_END_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend statu
+s of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PES_END_EN    (BIT(24))
+#define SPI_MEM_PES_END_EN_M  (BIT(24))
+#define SPI_MEM_PES_END_EN_V  0x1
+#define SPI_MEM_PES_END_EN_S  24
+/* SPI_MEM_PER_END_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
+ of flash. 0: Only need to check WIP is 0..*/
+#define SPI_MEM_PER_END_EN    (BIT(23))
+#define SPI_MEM_PER_END_EN_M  (BIT(23))
+#define SPI_MEM_PER_END_EN_V  0x1
+#define SPI_MEM_PER_END_EN_S  23
+/* SPI_MEM_FMEM_RD_SUS_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte w
+hen check flash SUS/SUS1/SUS2 status bit.*/
+#define SPI_MEM_FMEM_RD_SUS_2B    (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_M  (BIT(22))
+#define SPI_MEM_FMEM_RD_SUS_2B_V  0x1
+#define SPI_MEM_FMEM_RD_SUS_2B_S  22
+/* SPI_MEM_PESR_END_MSK : R/W ;bitpos:[21:6] ;default: 16'h80 ; */
+/*description: The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
+2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]..*/
+#define SPI_MEM_PESR_END_MSK    0x0000FFFF
+#define SPI_MEM_PESR_END_MSK_M  ((SPI_MEM_PESR_END_MSK_V)<<(SPI_MEM_PESR_END_MSK_S))
+#define SPI_MEM_PESR_END_MSK_V  0xFFFF
+#define SPI_MEM_PESR_END_MSK_S  6
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable Auto-suspending function..*/
+#define SPI_MEM_FLASH_PES_EN    (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(5))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  5
+/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
+application should send PER after PES is done..*/
+#define SPI_MEM_PES_PER_EN    (BIT(4))
+#define SPI_MEM_PES_PER_EN_M  (BIT(4))
+#define SPI_MEM_PES_PER_EN_V  0x1
+#define SPI_MEM_PES_PER_EN_S  4
+/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase suspend command is sent. 0: SPI1 does not wait after program erase
+ suspend command is sent..*/
+#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
+/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+program erase resume command is sent. 0: SPI1 does not wait after program erase
+resume command is sent..*/
+#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
+/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit, program erase suspend operation will be triggered when
+the bit is set. The bit will be cleared once the operation done.1: enable 0: d
+isable..*/
+#define SPI_MEM_FLASH_PES    (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit, program erase suspend operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: di
+sable..*/
+#define SPI_MEM_FLASH_PER    (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
+/* SPI_MEM_WAIT_PESR_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h05 ; */
+/*description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS
+/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash
+..*/
+#define SPI_MEM_WAIT_PESR_COMMAND    0x0000FFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_M  ((SPI_MEM_WAIT_PESR_COMMAND_V)<<(SPI_MEM_WAIT_PESR_COMMAND_S))
+#define SPI_MEM_WAIT_PESR_COMMAND_V  0xFFFF
+#define SPI_MEM_WAIT_PESR_COMMAND_S  16
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[15:0] ;default: 16'h7575 ; */
+/*description: Program/Erase suspend command..*/
+#define SPI_MEM_FLASH_PES_COMMAND    0x0000FFFF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFFFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[31:16] ;default: 16'h7a7a ; */
+/*description: Program/Erase resume command..*/
+#define SPI_MEM_FLASH_PER_COMMAND    0x0000FFFF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFFFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  16
+/* SPI_MEM_FLASH_PESR_CMD_2B : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit leng
+th of Program/Erase Suspend/Resume command is 8..*/
+#define SPI_MEM_FLASH_PESR_CMD_2B    (BIT(15))
+#define SPI_MEM_FLASH_PESR_CMD_2B_M  (BIT(15))
+#define SPI_MEM_FLASH_PESR_CMD_2B_V  0x1
+#define SPI_MEM_FLASH_PESR_CMD_2B_S  15
+/* SPI_MEM_SPI0_LOCK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it..*/
+#define SPI_MEM_SPI0_LOCK_EN    (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_M  (BIT(7))
+#define SPI_MEM_SPI0_LOCK_EN_V  0x1
+#define SPI_MEM_SPI0_LOCK_EN_S  7
+/* SPI_MEM_FLASH_PES_DLY_128 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
+#define SPI_MEM_FLASH_PES_DLY_128    (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_M  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PES_DLY_128_S  6
+/* SPI_MEM_FLASH_PER_DLY_128 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
+#define SPI_MEM_FLASH_PER_DLY_128    (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_M  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_128_V  0x1
+#define SPI_MEM_FLASH_PER_DLY_128_S  5
+/* SPI_MEM_FLASH_DP_DLY_128 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP com
+mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+after DP command is sent..*/
+#define SPI_MEM_FLASH_DP_DLY_128    (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_M  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_128_V  0x1
+#define SPI_MEM_FLASH_DP_DLY_128_S  4
+/* SPI_MEM_FLASH_RES_DLY_128 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after RES command is sent..*/
+#define SPI_MEM_FLASH_RES_DLY_128    (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_M  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_128_V  0x1
+#define SPI_MEM_FLASH_RES_DLY_128_S  3
+/* SPI_MEM_FLASH_HPM_DLY_128 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after HPM command is sent..*/
+#define SPI_MEM_FLASH_HPM_DLY_128    (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_M  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_128_V  0x1
+#define SPI_MEM_FLASH_HPM_DLY_128_S  2
+/* SPI_MEM_WAIT_PESR_CMD_2B : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+ SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit..*/
+#define SPI_MEM_WAIT_PESR_CMD_2B    (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_M  (BIT(1))
+#define SPI_MEM_WAIT_PESR_CMD_2B_V  0x1
+#define SPI_MEM_WAIT_PESR_CMD_2B_S  1
+/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend, only used in SPI1..*/
+#define SPI_MEM_FLASH_SUS    (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
+/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ENA_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT__ENA    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S  7
+/* SPI_MEM_PMS_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_ENA    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ENA_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ENA_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_ENA_S  6
+/* SPI_MEM_ECC_ERR_INT_ENA : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
+#define SPI_MEM_ECC_ERR_INT_ENA_S  5
+/* SPI_MEM_MST_ST_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ENA    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ENA_S  4
+/* SPI_MEM_SLV_ST_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ENA    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ENA_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ENA_S  3
+/* SPI_MEM_WPE_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ENA    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ENA_V  0x1
+#define SPI_MEM_WPE_END_INT_ENA_S  2
+/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_V  0x1
+#define SPI_MEM_PES_END_INT_ENA_S  1
+/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_V  0x1
+#define SPI_MEM_PER_END_INT_ENA_S  0
+
+#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
+/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_CLR_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S  7
+/* SPI_MEM_PMS_REJECT_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_CLR    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_CLR_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_CLR_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_CLR_S  6
+/* SPI_MEM_ECC_ERR_INT_CLR : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
+#define SPI_MEM_ECC_ERR_INT_CLR_S  5
+/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_CLR    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_MST_ST_END_INT_CLR_S  4
+/* SPI_MEM_SLV_ST_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_CLR    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_CLR_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_CLR_S  3
+/* SPI_MEM_WPE_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_CLR    (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_CLR_V  0x1
+#define SPI_MEM_WPE_END_INT_CLR_S  2
+/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_V  0x1
+#define SPI_MEM_PES_END_INT_CLR_S  1
+/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_V  0x1
+#define SPI_MEM_PER_END_INT_CLR_S  0
+
+#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
+/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+chip is losing power and RTC module sends out brown out close flash request to
+SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+ and MSPI returns to idle state. 0: Others..*/
+#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_RAW_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write
+ address is invalid by compared to MMU configuration. 0: Others..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI wr
+ite flash request is received. 0: Others..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read
+address is invalid by compared to MMU configuration. 0: Others..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S  7
+/* SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access
+is rejected. 0: Others..*/
+#define SPI_MEM_PMS_REJECT_INT_RAW    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_RAW_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_RAW_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_RAW_S  6
+/* SPI_MEM_ECC_ERR_INT_RAW : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is s
+et and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error
+ times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
+. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, t
+his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
+ual or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SP
+I_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times
+of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
+RR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are clearer,
+this bit will not be triggered..*/
+#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
+#define SPI_MEM_ECC_ERR_INT_RAW_S  5
+/* SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st
+is changed from non idle state to idle state. 0: Others..*/
+#define SPI_MEM_MST_ST_END_INT_RAW    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_MST_ST_END_INT_RAW_S  4
+/* SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st
+is changed from non idle state to idle state. It means that SPI_CS raises high.
+0: Others.*/
+#define SPI_MEM_SLV_ST_END_INT_RAW    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_RAW_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_RAW_S  3
+/* SPI_MEM_WPE_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/C
+E is sent and flash is already idle. 0: Others..*/
+#define SPI_MEM_WPE_END_INT_RAW    (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_RAW_V  0x1
+#define SPI_MEM_WPE_END_INT_RAW_S  2
+/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
+mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
+#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_V  0x1
+#define SPI_MEM_PES_END_INT_RAW_S  1
+/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
+mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
+#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_V  0x1
+#define SPI_MEM_PER_END_INT_RAW_S  0
+
+#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
+/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(10))
+#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ST_S  10
+/* SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST    (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M  (BIT(9))
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S  9
+/* SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST    (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M  (BIT(8))
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S  8
+/* SPI_MEM_AXI_RADDR_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt..*/
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST    (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M  (BIT(7))
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V  0x1
+#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S  7
+/* SPI_MEM_PMS_REJECT_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt..*/
+#define SPI_MEM_PMS_REJECT_INT_ST    (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ST_M  (BIT(6))
+#define SPI_MEM_PMS_REJECT_INT_ST_V  0x1
+#define SPI_MEM_PMS_REJECT_INT_ST_S  6
+/* SPI_MEM_ECC_ERR_INT_ST : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_ST    (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(5))
+#define SPI_MEM_ECC_ERR_INT_ST_V  0x1
+#define SPI_MEM_ECC_ERR_INT_ST_S  5
+/* SPI_MEM_MST_ST_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_MST_ST_END_INT interrupt..*/
+#define SPI_MEM_MST_ST_END_INT_ST    (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_M  (BIT(4))
+#define SPI_MEM_MST_ST_END_INT_ST_V  0x1
+#define SPI_MEM_MST_ST_END_INT_ST_S  4
+/* SPI_MEM_SLV_ST_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt..*/
+#define SPI_MEM_SLV_ST_END_INT_ST    (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_M  (BIT(3))
+#define SPI_MEM_SLV_ST_END_INT_ST_V  0x1
+#define SPI_MEM_SLV_ST_END_INT_ST_S  3
+/* SPI_MEM_WPE_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_WPE_END_INT interrupt..*/
+#define SPI_MEM_WPE_END_INT_ST    (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_M  (BIT(2))
+#define SPI_MEM_WPE_END_INT_ST_V  0x1
+#define SPI_MEM_WPE_END_INT_ST_S  2
+/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ST    (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_V  0x1
+#define SPI_MEM_PES_END_INT_ST_S  1
+/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ST    (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_V  0x1
+#define SPI_MEM_PER_END_INT_ST_S  0
+
+#define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
+/* SPI_MEM_FMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
+#define SPI_MEM_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_FMEM_HYPERBUS_CA_M  (BIT(30))
+#define SPI_MEM_FMEM_HYPERBUS_CA_V  0x1
+#define SPI_MEM_FMEM_HYPERBUS_CA_S  30
+/* SPI_MEM_FMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
+..*/
+#define SPI_MEM_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V  0x1
+#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S  29
+/* SPI_MEM_FMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
+#define SPI_MEM_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_FMEM_CLK_DIFF_INV_M  (BIT(28))
+#define SPI_MEM_FMEM_CLK_DIFF_INV_V  0x1
+#define SPI_MEM_FMEM_CLK_DIFF_INV_S  28
+/* SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S  27
+/* SPI_MEM_FMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define SPI_MEM_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_FMEM_DQS_CA_IN_M  (BIT(26))
+#define SPI_MEM_FMEM_DQS_CA_IN_V  0x1
+#define SPI_MEM_FMEM_DQS_CA_IN_S  26
+/* SPI_MEM_FMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define SPI_MEM_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_FMEM_CLK_DIFF_EN_M  (BIT(24))
+#define SPI_MEM_FMEM_CLK_DIFF_EN_V  0x1
+#define SPI_MEM_FMEM_CLK_DIFF_EN_S  24
+/* SPI_MEM_FMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
+0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
+egative edge of SPI_DQS..*/
+#define SPI_MEM_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_FMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define SPI_MEM_FMEM_DDR_DQS_LOOP_V  0x1
+#define SPI_MEM_FMEM_DDR_DQS_LOOP_S  21
+/* SPI_MEM_FMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI clock..*/
+#define SPI_MEM_FMEM_USR_DDR_DQS_THD    0x0000007F
+#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_FMEM_USR_DDR_DQS_THD_S))
+#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V  0x7F
+#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S  14
+/* SPI_MEM_FMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+accesses to flash..*/
+#define SPI_MEM_FMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define SPI_MEM_FMEM_RX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_FMEM_RX_DDR_MSK_EN_S  13
+/* SPI_MEM_FMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ accesses to flash..*/
+#define SPI_MEM_FMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define SPI_MEM_FMEM_TX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_FMEM_TX_DDR_MSK_EN_S  12
+/* SPI_MEM_FMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the panda device..*/
+#define SPI_MEM_FMEM_OUTMINBYTELEN    0x0000007F
+#define SPI_MEM_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_FMEM_OUTMINBYTELEN_S))
+#define SPI_MEM_FMEM_OUTMINBYTELEN_V  0x7F
+#define SPI_MEM_FMEM_OUTMINBYTELEN_S  5
+/* SPI_MEM_FMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define SPI_MEM_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_FMEM_DDR_CMD_DIS_M  (BIT(4))
+#define SPI_MEM_FMEM_DDR_CMD_DIS_V  0x1
+#define SPI_MEM_FMEM_DDR_CMD_DIS_S  4
+/* SPI_MEM_FMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
+#define SPI_MEM_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_FMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define SPI_MEM_FMEM_DDR_WDAT_SWP_V  0x1
+#define SPI_MEM_FMEM_DDR_WDAT_SWP_S  3
+/* SPI_MEM_FMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
+#define SPI_MEM_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_FMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define SPI_MEM_FMEM_DDR_RDAT_SWP_V  0x1
+#define SPI_MEM_FMEM_DDR_RDAT_SWP_S  2
+/* SPI_MEM_FMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
+#define SPI_MEM_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_FMEM_VAR_DUMMY_M  (BIT(1))
+#define SPI_MEM_FMEM_VAR_DUMMY_V  0x1
+#define SPI_MEM_FMEM_VAR_DUMMY_S  1
+/* SPI_MEM_FMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0 in SDR mode.*/
+#define SPI_MEM_FMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_FMEM_DDR_EN_M  (BIT(0))
+#define SPI_MEM_FMEM_DDR_EN_V  0x1
+#define SPI_MEM_FMEM_DDR_EN_S  0
+
+#define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD8)
+/* SPI_MEM_SMEM_HYPERBUS_CA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
+]}..*/
+#define SPI_MEM_SMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_SMEM_HYPERBUS_CA_M  (BIT(30))
+#define SPI_MEM_SMEM_HYPERBUS_CA_V  0x1
+#define SPI_MEM_SMEM_HYPERBUS_CA_S  30
+/* SPI_MEM_SMEM_OCTA_RAM_ADDR : HRO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
+, 1'b0}..*/
+#define SPI_MEM_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define SPI_MEM_SMEM_OCTA_RAM_ADDR_V  0x1
+#define SPI_MEM_SMEM_OCTA_RAM_ADDR_S  29
+/* SPI_MEM_SMEM_CLK_DIFF_INV : HRO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
+#define SPI_MEM_SMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_SMEM_CLK_DIFF_INV_M  (BIT(28))
+#define SPI_MEM_SMEM_CLK_DIFF_INV_V  0x1
+#define SPI_MEM_SMEM_CLK_DIFF_INV_S  28
+/* SPI_MEM_SMEM_HYPERBUS_DUMMY_2X : HRO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define SPI_MEM_SMEM_HYPERBUS_DUMMY_2X_S  27
+/* SPI_MEM_SMEM_DQS_CA_IN : HRO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define SPI_MEM_SMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_SMEM_DQS_CA_IN_M  (BIT(26))
+#define SPI_MEM_SMEM_DQS_CA_IN_V  0x1
+#define SPI_MEM_SMEM_DQS_CA_IN_S  26
+/* SPI_MEM_SMEM_CLK_DIFF_EN : HRO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define SPI_MEM_SMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_SMEM_CLK_DIFF_EN_M  (BIT(24))
+#define SPI_MEM_SMEM_CLK_DIFF_EN_V  0x1
+#define SPI_MEM_SMEM_CLK_DIFF_EN_S  24
+/* SPI_MEM_SMEM_DDR_DQS_LOOP : HRO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi
+0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or
+SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and n
+egative edge of SPI_DQS..*/
+#define SPI_MEM_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_SMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define SPI_MEM_SMEM_DDR_DQS_LOOP_V  0x1
+#define SPI_MEM_SMEM_DDR_DQS_LOOP_S  21
+/* SPI_MEM_SMEM_USR_DDR_DQS_THD : HRO ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI clock..*/
+#define SPI_MEM_SMEM_USR_DDR_DQS_THD    0x0000007F
+#define SPI_MEM_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SMEM_USR_DDR_DQS_THD_S))
+#define SPI_MEM_SMEM_USR_DDR_DQS_THD_V  0x7F
+#define SPI_MEM_SMEM_USR_DDR_DQS_THD_S  14
+/* SPI_MEM_SMEM_RX_DDR_MSK_EN : HRO ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
+accesses to external RAM..*/
+#define SPI_MEM_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define SPI_MEM_SMEM_RX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SMEM_RX_DDR_MSK_EN_S  13
+/* SPI_MEM_SMEM_TX_DDR_MSK_EN : HRO ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
+ accesses to external RAM..*/
+#define SPI_MEM_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define SPI_MEM_SMEM_TX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SMEM_TX_DDR_MSK_EN_S  12
+/* SPI_MEM_SMEM_OUTMINBYTELEN : HRO ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the DDR psram..*/
+#define SPI_MEM_SMEM_OUTMINBYTELEN    0x0000007F
+#define SPI_MEM_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SMEM_OUTMINBYTELEN_S))
+#define SPI_MEM_SMEM_OUTMINBYTELEN_V  0x7F
+#define SPI_MEM_SMEM_OUTMINBYTELEN_S  5
+/* SPI_MEM_SMEM_DDR_CMD_DIS : HRO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define SPI_MEM_SMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_SMEM_DDR_CMD_DIS_M  (BIT(4))
+#define SPI_MEM_SMEM_DDR_CMD_DIS_V  0x1
+#define SPI_MEM_SMEM_DDR_CMD_DIS_S  4
+/* SPI_MEM_SMEM_DDR_WDAT_SWP : HRO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi DDR mode..*/
+#define SPI_MEM_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_SMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define SPI_MEM_SMEM_DDR_WDAT_SWP_V  0x1
+#define SPI_MEM_SMEM_DDR_WDAT_SWP_S  3
+/* SPI_MEM_SMEM_DDR_RDAT_SWP : HRO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi DDR mode..*/
+#define SPI_MEM_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_SMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define SPI_MEM_SMEM_DDR_RDAT_SWP_V  0x1
+#define SPI_MEM_SMEM_DDR_RDAT_SWP_S  2
+/* SPI_MEM_SMEM_VAR_DUMMY : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi DDR mode..*/
+#define SPI_MEM_SMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_SMEM_VAR_DUMMY_M  (BIT(1))
+#define SPI_MEM_SMEM_VAR_DUMMY_V  0x1
+#define SPI_MEM_SMEM_VAR_DUMMY_S  1
+/* SPI_MEM_SMEM_DDR_EN : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0 in SDR mode.*/
+#define SPI_MEM_SMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_SMEM_DDR_EN_M  (BIT(0))
+#define SPI_MEM_SMEM_DDR_EN_V  0x1
+#define SPI_MEM_SMEM_DDR_EN_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x100)
+/* SPI_MEM_FMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_FMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_FMEM_PMS0_ECC_M  (BIT(2))
+#define SPI_MEM_FMEM_PMS0_ECC_V  0x1
+#define SPI_MEM_FMEM_PMS0_ECC_S  2
+/* SPI_MEM_FMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_FMEM_PMS0_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_FMEM_PMS0_WR_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS0_WR_ATTR_S  1
+/* SPI_MEM_FMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_FMEM_PMS0_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_FMEM_PMS0_RD_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS0_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x104)
+/* SPI_MEM_FMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_FMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_FMEM_PMS1_ECC_M  (BIT(2))
+#define SPI_MEM_FMEM_PMS1_ECC_V  0x1
+#define SPI_MEM_FMEM_PMS1_ECC_S  2
+/* SPI_MEM_FMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_FMEM_PMS1_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_FMEM_PMS1_WR_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS1_WR_ATTR_S  1
+/* SPI_MEM_FMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_FMEM_PMS1_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_FMEM_PMS1_RD_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS1_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x108)
+/* SPI_MEM_FMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_FMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_FMEM_PMS2_ECC_M  (BIT(2))
+#define SPI_MEM_FMEM_PMS2_ECC_V  0x1
+#define SPI_MEM_FMEM_PMS2_ECC_S  2
+/* SPI_MEM_FMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_FMEM_PMS2_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_FMEM_PMS2_WR_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS2_WR_ATTR_S  1
+/* SPI_MEM_FMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_FMEM_PMS2_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_FMEM_PMS2_RD_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS2_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10C)
+/* SPI_MEM_FMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash
+ ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_
+PMS$n_SIZE_REG..*/
+#define SPI_MEM_FMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_FMEM_PMS3_ECC_M  (BIT(2))
+#define SPI_MEM_FMEM_PMS3_ECC_V  0x1
+#define SPI_MEM_FMEM_PMS3_ECC_S  2
+/* SPI_MEM_FMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_FMEM_PMS3_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_FMEM_PMS3_WR_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS3_WR_ATTR_S  1
+/* SPI_MEM_FMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 flash ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_FMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_FMEM_PMS3_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_FMEM_PMS3_RD_ATTR_V  0x1
+#define SPI_MEM_FMEM_PMS3_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x110)
+/* SPI_MEM_FMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: SPI1 flash ACE section $n start address value.*/
+#define SPI_MEM_FMEM_PMS0_ADDR_S    0x03FFFFFF
+#define SPI_MEM_FMEM_PMS0_ADDR_S_M  ((SPI_MEM_FMEM_PMS0_ADDR_S_V)<<(SPI_MEM_FMEM_PMS0_ADDR_S_S))
+#define SPI_MEM_FMEM_PMS0_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_FMEM_PMS0_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x114)
+/* SPI_MEM_FMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
+/*description: SPI1 flash ACE section $n start address value.*/
+#define SPI_MEM_FMEM_PMS1_ADDR_S    0x03FFFFFF
+#define SPI_MEM_FMEM_PMS1_ADDR_S_M  ((SPI_MEM_FMEM_PMS1_ADDR_S_V)<<(SPI_MEM_FMEM_PMS1_ADDR_S_S))
+#define SPI_MEM_FMEM_PMS1_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_FMEM_PMS1_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x118)
+/* SPI_MEM_FMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
+/*description: SPI1 flash ACE section $n start address value.*/
+#define SPI_MEM_FMEM_PMS2_ADDR_S    0x03FFFFFF
+#define SPI_MEM_FMEM_PMS2_ADDR_S_M  ((SPI_MEM_FMEM_PMS2_ADDR_S_V)<<(SPI_MEM_FMEM_PMS2_ADDR_S_S))
+#define SPI_MEM_FMEM_PMS2_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_FMEM_PMS2_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x11C)
+/* SPI_MEM_FMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
+/*description: SPI1 flash ACE section $n start address value.*/
+#define SPI_MEM_FMEM_PMS3_ADDR_S    0x03FFFFFF
+#define SPI_MEM_FMEM_PMS3_ADDR_S_M  ((SPI_MEM_FMEM_PMS3_ADDR_S_V)<<(SPI_MEM_FMEM_PMS3_ADDR_S_S))
+#define SPI_MEM_FMEM_PMS3_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_FMEM_PMS3_ADDR_S_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x120)
+/* SPI_MEM_FMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_FMEM_PMS0_SIZE    0x00003FFF
+#define SPI_MEM_FMEM_PMS0_SIZE_M  ((SPI_MEM_FMEM_PMS0_SIZE_V)<<(SPI_MEM_FMEM_PMS0_SIZE_S))
+#define SPI_MEM_FMEM_PMS0_SIZE_V  0x3FFF
+#define SPI_MEM_FMEM_PMS0_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x124)
+/* SPI_MEM_FMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_FMEM_PMS1_SIZE    0x00003FFF
+#define SPI_MEM_FMEM_PMS1_SIZE_M  ((SPI_MEM_FMEM_PMS1_SIZE_V)<<(SPI_MEM_FMEM_PMS1_SIZE_S))
+#define SPI_MEM_FMEM_PMS1_SIZE_V  0x3FFF
+#define SPI_MEM_FMEM_PMS1_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x128)
+/* SPI_MEM_FMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_FMEM_PMS2_SIZE    0x00003FFF
+#define SPI_MEM_FMEM_PMS2_SIZE_M  ((SPI_MEM_FMEM_PMS2_SIZE_V)<<(SPI_MEM_FMEM_PMS2_SIZE_S))
+#define SPI_MEM_FMEM_PMS2_SIZE_V  0x3FFF
+#define SPI_MEM_FMEM_PMS2_SIZE_S  0
+
+#define SPI_MEM_SPI_FMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x12C)
+/* SPI_MEM_FMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS
+$n_ADDR_S + SPI_FMEM_PMS$n_SIZE).*/
+#define SPI_MEM_FMEM_PMS3_SIZE    0x00003FFF
+#define SPI_MEM_FMEM_PMS3_SIZE_M  ((SPI_MEM_FMEM_PMS3_SIZE_V)<<(SPI_MEM_FMEM_PMS3_SIZE_S))
+#define SPI_MEM_FMEM_PMS3_SIZE_V  0x3FFF
+#define SPI_MEM_FMEM_PMS3_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x130)
+/* SPI_MEM_SMEM_PMS0_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SMEM_PMS0_ECC    (BIT(2))
+#define SPI_MEM_SMEM_PMS0_ECC_M  (BIT(2))
+#define SPI_MEM_SMEM_PMS0_ECC_V  0x1
+#define SPI_MEM_SMEM_PMS0_ECC_S  2
+/* SPI_MEM_SMEM_PMS0_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS0_WR_ATTR    (BIT(1))
+#define SPI_MEM_SMEM_PMS0_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SMEM_PMS0_WR_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS0_WR_ATTR_S  1
+/* SPI_MEM_SMEM_PMS0_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS0_RD_ATTR    (BIT(0))
+#define SPI_MEM_SMEM_PMS0_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SMEM_PMS0_RD_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS0_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x134)
+/* SPI_MEM_SMEM_PMS1_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SMEM_PMS1_ECC    (BIT(2))
+#define SPI_MEM_SMEM_PMS1_ECC_M  (BIT(2))
+#define SPI_MEM_SMEM_PMS1_ECC_V  0x1
+#define SPI_MEM_SMEM_PMS1_ECC_S  2
+/* SPI_MEM_SMEM_PMS1_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS1_WR_ATTR    (BIT(1))
+#define SPI_MEM_SMEM_PMS1_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SMEM_PMS1_WR_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS1_WR_ATTR_S  1
+/* SPI_MEM_SMEM_PMS1_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS1_RD_ATTR    (BIT(0))
+#define SPI_MEM_SMEM_PMS1_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SMEM_PMS1_RD_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS1_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x138)
+/* SPI_MEM_SMEM_PMS2_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SMEM_PMS2_ECC    (BIT(2))
+#define SPI_MEM_SMEM_PMS2_ECC_M  (BIT(2))
+#define SPI_MEM_SMEM_PMS2_ECC_V  0x1
+#define SPI_MEM_SMEM_PMS2_ECC_S  2
+/* SPI_MEM_SMEM_PMS2_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS2_WR_ATTR    (BIT(1))
+#define SPI_MEM_SMEM_PMS2_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SMEM_PMS2_WR_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS2_WR_ATTR_S  1
+/* SPI_MEM_SMEM_PMS2_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS2_RD_ATTR    (BIT(0))
+#define SPI_MEM_SMEM_PMS2_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SMEM_PMS2_RD_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS2_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_ATTR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x13C)
+/* SPI_MEM_SMEM_PMS3_ECC : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. Th
+e external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG
+ and SPI_SMEM_PMS$n_SIZE_REG..*/
+#define SPI_MEM_SMEM_PMS3_ECC    (BIT(2))
+#define SPI_MEM_SMEM_PMS3_ECC_M  (BIT(2))
+#define SPI_MEM_SMEM_PMS3_ECC_V  0x1
+#define SPI_MEM_SMEM_PMS3_ECC_S  2
+/* SPI_MEM_SMEM_PMS3_WR_ATTR : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS3_WR_ATTR    (BIT(1))
+#define SPI_MEM_SMEM_PMS3_WR_ATTR_M  (BIT(1))
+#define SPI_MEM_SMEM_PMS3_WR_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS3_WR_ATTR_S  1
+/* SPI_MEM_SMEM_PMS3_RD_ATTR : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed..*/
+#define SPI_MEM_SMEM_PMS3_RD_ATTR    (BIT(0))
+#define SPI_MEM_SMEM_PMS3_RD_ATTR_M  (BIT(0))
+#define SPI_MEM_SMEM_PMS3_RD_ATTR_V  0x1
+#define SPI_MEM_SMEM_PMS3_RD_ATTR_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x140)
+/* SPI_MEM_SMEM_PMS0_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: SPI1 external RAM ACE section $n start address value.*/
+#define SPI_MEM_SMEM_PMS0_ADDR_S    0x03FFFFFF
+#define SPI_MEM_SMEM_PMS0_ADDR_S_M  ((SPI_MEM_SMEM_PMS0_ADDR_S_V)<<(SPI_MEM_SMEM_PMS0_ADDR_S_S))
+#define SPI_MEM_SMEM_PMS0_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_SMEM_PMS0_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x144)
+/* SPI_MEM_SMEM_PMS1_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'hffffff ; */
+/*description: SPI1 external RAM ACE section $n start address value.*/
+#define SPI_MEM_SMEM_PMS1_ADDR_S    0x03FFFFFF
+#define SPI_MEM_SMEM_PMS1_ADDR_S_M  ((SPI_MEM_SMEM_PMS1_ADDR_S_V)<<(SPI_MEM_SMEM_PMS1_ADDR_S_S))
+#define SPI_MEM_SMEM_PMS1_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_SMEM_PMS1_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x148)
+/* SPI_MEM_SMEM_PMS2_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h1ffffff ; */
+/*description: SPI1 external RAM ACE section $n start address value.*/
+#define SPI_MEM_SMEM_PMS2_ADDR_S    0x03FFFFFF
+#define SPI_MEM_SMEM_PMS2_ADDR_S_M  ((SPI_MEM_SMEM_PMS2_ADDR_S_V)<<(SPI_MEM_SMEM_PMS2_ADDR_S_S))
+#define SPI_MEM_SMEM_PMS2_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_SMEM_PMS2_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14C)
+/* SPI_MEM_SMEM_PMS3_ADDR_S : R/W ;bitpos:[25:0] ;default: 26'h2ffffff ; */
+/*description: SPI1 external RAM ACE section $n start address value.*/
+#define SPI_MEM_SMEM_PMS3_ADDR_S    0x03FFFFFF
+#define SPI_MEM_SMEM_PMS3_ADDR_S_M  ((SPI_MEM_SMEM_PMS3_ADDR_S_V)<<(SPI_MEM_SMEM_PMS3_ADDR_S_S))
+#define SPI_MEM_SMEM_PMS3_ADDR_S_V  0x3FFFFFF
+#define SPI_MEM_SMEM_PMS3_ADDR_S_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS0_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x150)
+/* SPI_MEM_SMEM_PMS0_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SMEM_PMS0_SIZE    0x00003FFF
+#define SPI_MEM_SMEM_PMS0_SIZE_M  ((SPI_MEM_SMEM_PMS0_SIZE_V)<<(SPI_MEM_SMEM_PMS0_SIZE_S))
+#define SPI_MEM_SMEM_PMS0_SIZE_V  0x3FFF
+#define SPI_MEM_SMEM_PMS0_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS1_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x154)
+/* SPI_MEM_SMEM_PMS1_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SMEM_PMS1_SIZE    0x00003FFF
+#define SPI_MEM_SMEM_PMS1_SIZE_M  ((SPI_MEM_SMEM_PMS1_SIZE_V)<<(SPI_MEM_SMEM_PMS1_SIZE_S))
+#define SPI_MEM_SMEM_PMS1_SIZE_V  0x3FFF
+#define SPI_MEM_SMEM_PMS1_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS2_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x158)
+/* SPI_MEM_SMEM_PMS2_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SMEM_PMS2_SIZE    0x00003FFF
+#define SPI_MEM_SMEM_PMS2_SIZE_M  ((SPI_MEM_SMEM_PMS2_SIZE_V)<<(SPI_MEM_SMEM_PMS2_SIZE_S))
+#define SPI_MEM_SMEM_PMS2_SIZE_V  0x3FFF
+#define SPI_MEM_SMEM_PMS2_SIZE_S  0
+
+#define SPI_MEM_SPI_SMEM_PMS3_SIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x15C)
+/* SPI_MEM_SMEM_PMS3_SIZE : R/W ;bitpos:[13:0] ;default: 14'h1000 ; */
+/*description: SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_S
+MEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE).*/
+#define SPI_MEM_SMEM_PMS3_SIZE    0x00003FFF
+#define SPI_MEM_SMEM_PMS3_SIZE_M  ((SPI_MEM_SMEM_PMS3_SIZE_V)<<(SPI_MEM_SMEM_PMS3_SIZE_S))
+#define SPI_MEM_SMEM_PMS3_SIZE_V  0x3FFF
+#define SPI_MEM_SMEM_PMS3_SIZE_S  0
+
+#define SPI_MEM_PMS_REJECT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x164)
+/* SPI_MEM_PMS_IVD : R/SS/WTC ;bitpos:[31] ;default: 1'h0 ; */
+/*description: 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit
+ error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_IVD    (BIT(31))
+#define SPI_MEM_PMS_IVD_M  (BIT(31))
+#define SPI_MEM_PMS_IVD_V  0x1
+#define SPI_MEM_PMS_IVD_S  31
+/* SPI_MEM_PMS_MULTI_HIT : R/SS/WTC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 1: SPI1 access is rejected because of address miss. 0: No address miss error. It
+ is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_MULTI_HIT    (BIT(30))
+#define SPI_MEM_PMS_MULTI_HIT_M  (BIT(30))
+#define SPI_MEM_PMS_MULTI_HIT_V  0x1
+#define SPI_MEM_PMS_MULTI_HIT_S  30
+/* SPI_MEM_PMS_ST : R/SS/WTC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_M
+EM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_ST    (BIT(29))
+#define SPI_MEM_PMS_ST_M  (BIT(29))
+#define SPI_MEM_PMS_ST_V  0x1
+#define SPI_MEM_PMS_ST_S  29
+/* SPI_MEM_PMS_LD : R/SS/WTC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI
+_MEM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_PMS_LD    (BIT(28))
+#define SPI_MEM_PMS_LD_M  (BIT(28))
+#define SPI_MEM_PMS_LD_V  0x1
+#define SPI_MEM_PMS_LD_S  28
+/* SPI_MEM_PM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0/1 transfer permission control function..*/
+#define SPI_MEM_PM_EN    (BIT(26))
+#define SPI_MEM_PM_EN_M  (BIT(26))
+#define SPI_MEM_PM_EN_V  0x1
+#define SPI_MEM_PM_EN_S  26
+/* SPI_MEM_REJECT_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first SPI1 access error address. It is cleared by when  SPI_M
+EM_PMS_REJECT_INT_CLR bit is set..*/
+#define SPI_MEM_REJECT_ADDR    0x03FFFFFF
+#define SPI_MEM_REJECT_ADDR_M  ((SPI_MEM_REJECT_ADDR_V)<<(SPI_MEM_REJECT_ADDR_S))
+#define SPI_MEM_REJECT_ADDR_V  0x3FFFFFF
+#define SPI_MEM_REJECT_ADDR_S  0
+
+#define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x168)
+/* SPI_MEM_ECC_ERR_BITS : HRO ;bitpos:[31:25] ;default: 7'd0 ; */
+/*description: Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding
+ to byte 0 bit 0 to byte 15 bit 7).*/
+#define SPI_MEM_ECC_ERR_BITS    0x0000007F
+#define SPI_MEM_ECC_ERR_BITS_M  ((SPI_MEM_ECC_ERR_BITS_V)<<(SPI_MEM_ECC_ERR_BITS_S))
+#define SPI_MEM_ECC_ERR_BITS_V  0x7F
+#define SPI_MEM_ECC_ERR_BITS_S  25
+/* SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO ;bitpos:[24] ;default: 1'b1 ; */
+/*description: 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is upd
+ated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADD
+R record the first ECC error information..*/
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN    (BIT(24))
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M  (BIT(24))
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V  0x1
+#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S  24
+/* SPI_MEM_USR_ECC_ADDR_EN : HRO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer..*/
+#define SPI_MEM_USR_ECC_ADDR_EN    (BIT(21))
+#define SPI_MEM_USR_ECC_ADDR_EN_M  (BIT(21))
+#define SPI_MEM_USR_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_USR_ECC_ADDR_EN_S  21
+/* SPI_MEM_FMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
+he ECC region or non-ECC region of flash. If there is no ECC region in flash, th
+is bit should be 0. Otherwise, this bit should be 1..*/
+#define SPI_MEM_FMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_FMEM_ECC_ADDR_EN_M  (BIT(20))
+#define SPI_MEM_FMEM_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_FMEM_ECC_ADDR_EN_S  20
+/* SPI_MEM_FMEM_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2:
+1024 bytes. 3: 2048 bytes..*/
+#define SPI_MEM_FMEM_PAGE_SIZE    0x00000003
+#define SPI_MEM_FMEM_PAGE_SIZE_M  ((SPI_MEM_FMEM_PAGE_SIZE_V)<<(SPI_MEM_FMEM_PAGE_SIZE_S))
+#define SPI_MEM_FMEM_PAGE_SIZE_V  0x3
+#define SPI_MEM_FMEM_PAGE_SIZE_S  18
+/* SPI_MEM_FMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
+h..*/
+#define SPI_MEM_FMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_FMEM_ECC_ERR_INT_EN_M  (BIT(17))
+#define SPI_MEM_FMEM_ECC_ERR_INT_EN_V  0x1
+#define SPI_MEM_FMEM_ECC_ERR_INT_EN_S  17
+/* SPI_MEM_FMEM_ECC_ERR_INT_NUM : HRO ;bitpos:[16:11] ;default: 6'd10 ; */
+/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
+upt..*/
+#define SPI_MEM_FMEM_ECC_ERR_INT_NUM    0x0000003F
+#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_FMEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_FMEM_ECC_ERR_INT_NUM_S))
+#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_V  0x3F
+#define SPI_MEM_FMEM_ECC_ERR_INT_NUM_S  11
+
+#define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x16C)
+/* SPI_MEM_ECC_ERR_CNT : HRO ;bitpos:[31:26] ;default: 6'd0 ; */
+/*description: This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_
+ECC_ERR_INT_CLR bit is set..*/
+#define SPI_MEM_ECC_ERR_CNT    0x0000003F
+#define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
+#define SPI_MEM_ECC_ERR_CNT_V  0x3F
+#define SPI_MEM_ECC_ERR_CNT_S  26
+/* SPI_MEM_ECC_ERR_ADDR : HRO ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_
+ECC_ERR_INT_CLR bit is set..*/
+#define SPI_MEM_ECC_ERR_ADDR    0x03FFFFFF
+#define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
+#define SPI_MEM_ECC_ERR_ADDR_V  0x3FFFFFF
+#define SPI_MEM_ECC_ERR_ADDR_S  0
+
+#define SPI_MEM_AXI_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x170)
+/* SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO
+and RDATA_AFIFO are empty and spi0_mst_st is IDLE..*/
+#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY    (BIT(31))
+#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_M  (BIT(31))
+#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_V  0x1
+#define SPI_MEM_ALL_AXI_TRANS_AFIFO_EMPTY_S  31
+/* SPI_MEM_WBLEN_AFIFO_REMPTY : RO ;bitpos:[30] ;default: 1'b1 ; */
+/*description: 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
+#define SPI_MEM_WBLEN_AFIFO_REMPTY    (BIT(30))
+#define SPI_MEM_WBLEN_AFIFO_REMPTY_M  (BIT(30))
+#define SPI_MEM_WBLEN_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_WBLEN_AFIFO_REMPTY_S  30
+/* SPI_MEM_WDATA_AFIFO_REMPTY : RO ;bitpos:[29] ;default: 1'b1 ; */
+/*description: 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending..*/
+#define SPI_MEM_WDATA_AFIFO_REMPTY    (BIT(29))
+#define SPI_MEM_WDATA_AFIFO_REMPTY_M  (BIT(29))
+#define SPI_MEM_WDATA_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_WDATA_AFIFO_REMPTY_S  29
+/* SPI_MEM_RADDR_AFIFO_REMPTY : RO ;bitpos:[28] ;default: 1'b1 ; */
+/*description: 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
+#define SPI_MEM_RADDR_AFIFO_REMPTY    (BIT(28))
+#define SPI_MEM_RADDR_AFIFO_REMPTY_M  (BIT(28))
+#define SPI_MEM_RADDR_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_RADDR_AFIFO_REMPTY_S  28
+/* SPI_MEM_RDATA_AFIFO_REMPTY : RO ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending..*/
+#define SPI_MEM_RDATA_AFIFO_REMPTY    (BIT(27))
+#define SPI_MEM_RDATA_AFIFO_REMPTY_M  (BIT(27))
+#define SPI_MEM_RDATA_AFIFO_REMPTY_V  0x1
+#define SPI_MEM_RDATA_AFIFO_REMPTY_S  27
+/* SPI_MEM_ALL_FIFO_EMPTY : RO ;bitpos:[26] ;default: 1'b1 ; */
+/*description: The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers
+ and SPI0 transfers are done. 0: Others..*/
+#define SPI_MEM_ALL_FIFO_EMPTY    (BIT(26))
+#define SPI_MEM_ALL_FIFO_EMPTY_M  (BIT(26))
+#define SPI_MEM_ALL_FIFO_EMPTY_V  0x1
+#define SPI_MEM_ALL_FIFO_EMPTY_S  26
+/* SPI_MEM_AXI_ERR_ADDR : R/SS/WTC ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits show the first AXI write/read invalid error or AXI write flash error
+address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR
+or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set..*/
+#define SPI_MEM_AXI_ERR_ADDR    0x03FFFFFF
+#define SPI_MEM_AXI_ERR_ADDR_M  ((SPI_MEM_AXI_ERR_ADDR_V)<<(SPI_MEM_AXI_ERR_ADDR_S))
+#define SPI_MEM_AXI_ERR_ADDR_V  0x3FFFFFF
+#define SPI_MEM_AXI_ERR_ADDR_S  0
+
+#define SPI_MEM_SPI_SMEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x174)
+/* SPI_MEM_SMEM_ECC_ADDR_EN : HRO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to t
+he ECC region or non-ECC region of external RAM. If there is no ECC region in ex
+ternal RAM, this bit should be 0. Otherwise, this bit should be 1..*/
+#define SPI_MEM_SMEM_ECC_ADDR_EN    (BIT(20))
+#define SPI_MEM_SMEM_ECC_ADDR_EN_M  (BIT(20))
+#define SPI_MEM_SMEM_ECC_ADDR_EN_V  0x1
+#define SPI_MEM_SMEM_ECC_ADDR_EN_S  20
+/* SPI_MEM_SMEM_PAGE_SIZE : HRO ;bitpos:[19:18] ;default: 2'd2 ; */
+/*description: Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 byt
+es. 2: 1024 bytes. 3: 2048 bytes..*/
+#define SPI_MEM_SMEM_PAGE_SIZE    0x00000003
+#define SPI_MEM_SMEM_PAGE_SIZE_M  ((SPI_MEM_SMEM_PAGE_SIZE_V)<<(SPI_MEM_SMEM_PAGE_SIZE_S))
+#define SPI_MEM_SMEM_PAGE_SIZE_V  0x3
+#define SPI_MEM_SMEM_PAGE_SIZE_S  18
+/* SPI_MEM_SMEM_ECC_ERR_INT_EN : HRO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
+rnal RAM..*/
+#define SPI_MEM_SMEM_ECC_ERR_INT_EN    (BIT(17))
+#define SPI_MEM_SMEM_ECC_ERR_INT_EN_M  (BIT(17))
+#define SPI_MEM_SMEM_ECC_ERR_INT_EN_V  0x1
+#define SPI_MEM_SMEM_ECC_ERR_INT_EN_S  17
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x180)
+/* SPI_MEM_TIMING_CALI_UPDATE : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to update delay mode, delay num and extra dummy in MSPI..*/
+#define SPI_MEM_TIMING_CALI_UPDATE    (BIT(6))
+#define SPI_MEM_TIMING_CALI_UPDATE_M  (BIT(6))
+#define SPI_MEM_TIMING_CALI_UPDATE_V  0x1
+#define SPI_MEM_TIMING_CALI_UPDATE_S  6
+/* SPI_MEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to f
+lash..*/
+#define SPI_MEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_DLL_TIMING_CALI_M  (BIT(5))
+#define SPI_MEM_DLL_TIMING_CALI_V  0x1
+#define SPI_MEM_DLL_TIMING_CALI_S  5
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration..*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations..*/
+#define SPI_MEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations..*/
+#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x184)
+/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DINS_MODE    0x00000007
+#define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
+#define SPI_MEM_DINS_MODE_V  0x7
+#define SPI_MEM_DINS_MODE_S  24
+/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN7_MODE    0x00000007
+#define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
+#define SPI_MEM_DIN7_MODE_V  0x7
+#define SPI_MEM_DIN7_MODE_S  21
+/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN6_MODE    0x00000007
+#define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
+#define SPI_MEM_DIN6_MODE_V  0x7
+#define SPI_MEM_DIN6_MODE_S  18
+/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN5_MODE    0x00000007
+#define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
+#define SPI_MEM_DIN5_MODE_V  0x7
+#define SPI_MEM_DIN5_MODE_S  15
+/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: inp
+ut with the spi_clk.*/
+#define SPI_MEM_DIN4_MODE    0x00000007
+#define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
+#define SPI_MEM_DIN4_MODE_V  0x7
+#define SPI_MEM_DIN4_MODE_S  12
+/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN3_MODE    0x00000007
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x7
+#define SPI_MEM_DIN3_MODE_S  9
+/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN2_MODE    0x00000007
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x7
+#define SPI_MEM_DIN2_MODE_S  6
+/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN1_MODE    0x00000007
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x7
+#define SPI_MEM_DIN1_MODE_S  3
+/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_DIN0_MODE    0x00000007
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x7
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x188)
+/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DINS_NUM    0x00000003
+#define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
+#define SPI_MEM_DINS_NUM_V  0x3
+#define SPI_MEM_DINS_NUM_S  16
+/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN7_NUM    0x00000003
+#define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
+#define SPI_MEM_DIN7_NUM_V  0x3
+#define SPI_MEM_DIN7_NUM_S  14
+/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN6_NUM    0x00000003
+#define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
+#define SPI_MEM_DIN6_NUM_V  0x3
+#define SPI_MEM_DIN6_NUM_S  12
+/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN5_NUM    0x00000003
+#define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
+#define SPI_MEM_DIN5_NUM_V  0x3
+#define SPI_MEM_DIN5_NUM_S  10
+/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN4_NUM    0x00000003
+#define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
+#define SPI_MEM_DIN4_NUM_V  0x3
+#define SPI_MEM_DIN4_NUM_S  8
+/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN3_NUM    0x00000003
+#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
+#define SPI_MEM_DIN3_NUM_V  0x3
+#define SPI_MEM_DIN3_NUM_S  6
+/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN2_NUM    0x00000003
+#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
+#define SPI_MEM_DIN2_NUM_V  0x3
+#define SPI_MEM_DIN2_NUM_S  4
+/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN1_NUM    0x00000003
+#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
+#define SPI_MEM_DIN1_NUM_V  0x3
+#define SPI_MEM_DIN1_NUM_S  2
+/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_DIN0_NUM    0x00000003
+#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
+#define SPI_MEM_DIN0_NUM_V  0x3
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18C)
+/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_DOUTS_MODE_M  (BIT(8))
+#define SPI_MEM_DOUTS_MODE_V  0x1
+#define SPI_MEM_DOUTS_MODE_S  8
+/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_DOUT7_MODE_M  (BIT(7))
+#define SPI_MEM_DOUT7_MODE_V  0x1
+#define SPI_MEM_DOUT7_MODE_S  7
+/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_DOUT6_MODE_M  (BIT(6))
+#define SPI_MEM_DOUT6_MODE_V  0x1
+#define SPI_MEM_DOUT6_MODE_S  6
+/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_DOUT5_MODE_M  (BIT(5))
+#define SPI_MEM_DOUT5_MODE_V  0x1
+#define SPI_MEM_DOUT5_MODE_S  5
+/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the spi_clk.*/
+#define SPI_MEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_DOUT4_MODE_M  (BIT(4))
+#define SPI_MEM_DOUT4_MODE_V  0x1
+#define SPI_MEM_DOUT4_MODE_S  4
+/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_DOUT3_MODE_S  3
+/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_DOUT2_MODE_S  2
+/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_DOUT1_MODE_S  1
+/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x190)
+/* SPI_MEM_SMEM_DLL_TIMING_CALI : HRO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to E
+XT_RAM..*/
+#define SPI_MEM_SMEM_DLL_TIMING_CALI    (BIT(5))
+#define SPI_MEM_SMEM_DLL_TIMING_CALI_M  (BIT(5))
+#define SPI_MEM_SMEM_DLL_TIMING_CALI_V  0x1
+#define SPI_MEM_SMEM_DLL_TIMING_CALI_S  5
+/* SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN : HRO ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: For sram, add extra dummy spi clock cycle length for spi clock calibration..*/
+#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_SMEM_TIMING_CALI : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For sram, the bit is used to enable timing auto-calibration for all reading oper
+ations..*/
+#define SPI_MEM_SMEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_SMEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_SMEM_TIMING_CALI_V  0x1
+#define SPI_MEM_SMEM_TIMING_CALI_S  1
+/* SPI_MEM_SMEM_TIMING_CLK_ENA : HRO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: For sram, the bit is used to enable timing adjust clock for all reading operation
+ns..*/
+#define SPI_MEM_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_SMEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_SMEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_SMEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x194)
+/* SPI_MEM_SMEM_DINS_MODE : HRO ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DINS_MODE    0x00000007
+#define SPI_MEM_SMEM_DINS_MODE_M  ((SPI_MEM_SMEM_DINS_MODE_V)<<(SPI_MEM_SMEM_DINS_MODE_S))
+#define SPI_MEM_SMEM_DINS_MODE_V  0x7
+#define SPI_MEM_SMEM_DINS_MODE_S  24
+/* SPI_MEM_SMEM_DIN7_MODE : HRO ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN7_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN7_MODE_M  ((SPI_MEM_SMEM_DIN7_MODE_V)<<(SPI_MEM_SMEM_DIN7_MODE_S))
+#define SPI_MEM_SMEM_DIN7_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN7_MODE_S  21
+/* SPI_MEM_SMEM_DIN6_MODE : HRO ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN6_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN6_MODE_M  ((SPI_MEM_SMEM_DIN6_MODE_V)<<(SPI_MEM_SMEM_DIN6_MODE_S))
+#define SPI_MEM_SMEM_DIN6_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN6_MODE_S  18
+/* SPI_MEM_SMEM_DIN5_MODE : HRO ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN5_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN5_MODE_M  ((SPI_MEM_SMEM_DIN5_MODE_V)<<(SPI_MEM_SMEM_DIN5_MODE_S))
+#define SPI_MEM_SMEM_DIN5_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN5_MODE_S  15
+/* SPI_MEM_SMEM_DIN4_MODE : HRO ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN4_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN4_MODE_M  ((SPI_MEM_SMEM_DIN4_MODE_V)<<(SPI_MEM_SMEM_DIN4_MODE_S))
+#define SPI_MEM_SMEM_DIN4_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN4_MODE_S  12
+/* SPI_MEM_SMEM_DIN3_MODE : HRO ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN3_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN3_MODE_M  ((SPI_MEM_SMEM_DIN3_MODE_V)<<(SPI_MEM_SMEM_DIN3_MODE_S))
+#define SPI_MEM_SMEM_DIN3_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN3_MODE_S  9
+/* SPI_MEM_SMEM_DIN2_MODE : HRO ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN2_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN2_MODE_M  ((SPI_MEM_SMEM_DIN2_MODE_V)<<(SPI_MEM_SMEM_DIN2_MODE_S))
+#define SPI_MEM_SMEM_DIN2_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN2_MODE_S  6
+/* SPI_MEM_SMEM_DIN1_MODE : HRO ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN1_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN1_MODE_M  ((SPI_MEM_SMEM_DIN1_MODE_V)<<(SPI_MEM_SMEM_DIN1_MODE_S))
+#define SPI_MEM_SMEM_DIN1_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN1_MODE_S  3
+/* SPI_MEM_SMEM_DIN0_MODE : HRO ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DIN0_MODE    0x00000007
+#define SPI_MEM_SMEM_DIN0_MODE_M  ((SPI_MEM_SMEM_DIN0_MODE_V)<<(SPI_MEM_SMEM_DIN0_MODE_S))
+#define SPI_MEM_SMEM_DIN0_MODE_V  0x7
+#define SPI_MEM_SMEM_DIN0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x198)
+/* SPI_MEM_SMEM_DINS_NUM : HRO ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: input without delayed,
+1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: in
+put with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input w
+ith the spi_clk high edge,  6: input with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DINS_NUM    0x00000003
+#define SPI_MEM_SMEM_DINS_NUM_M  ((SPI_MEM_SMEM_DINS_NUM_V)<<(SPI_MEM_SMEM_DINS_NUM_S))
+#define SPI_MEM_SMEM_DINS_NUM_V  0x3
+#define SPI_MEM_SMEM_DINS_NUM_S  16
+/* SPI_MEM_SMEM_DIN7_NUM : HRO ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN7_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN7_NUM_M  ((SPI_MEM_SMEM_DIN7_NUM_V)<<(SPI_MEM_SMEM_DIN7_NUM_S))
+#define SPI_MEM_SMEM_DIN7_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN7_NUM_S  14
+/* SPI_MEM_SMEM_DIN6_NUM : HRO ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN6_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN6_NUM_M  ((SPI_MEM_SMEM_DIN6_NUM_V)<<(SPI_MEM_SMEM_DIN6_NUM_S))
+#define SPI_MEM_SMEM_DIN6_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN6_NUM_S  12
+/* SPI_MEM_SMEM_DIN5_NUM : HRO ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN5_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN5_NUM_M  ((SPI_MEM_SMEM_DIN5_NUM_V)<<(SPI_MEM_SMEM_DIN5_NUM_S))
+#define SPI_MEM_SMEM_DIN5_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN5_NUM_S  10
+/* SPI_MEM_SMEM_DIN4_NUM : HRO ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN4_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN4_NUM_M  ((SPI_MEM_SMEM_DIN4_NUM_V)<<(SPI_MEM_SMEM_DIN4_NUM_S))
+#define SPI_MEM_SMEM_DIN4_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN4_NUM_S  8
+/* SPI_MEM_SMEM_DIN3_NUM : HRO ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN3_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN3_NUM_M  ((SPI_MEM_SMEM_DIN3_NUM_V)<<(SPI_MEM_SMEM_DIN3_NUM_S))
+#define SPI_MEM_SMEM_DIN3_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN3_NUM_S  6
+/* SPI_MEM_SMEM_DIN2_NUM : HRO ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN2_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN2_NUM_M  ((SPI_MEM_SMEM_DIN2_NUM_V)<<(SPI_MEM_SMEM_DIN2_NUM_S))
+#define SPI_MEM_SMEM_DIN2_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN2_NUM_S  4
+/* SPI_MEM_SMEM_DIN1_NUM : HRO ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN1_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN1_NUM_M  ((SPI_MEM_SMEM_DIN1_NUM_V)<<(SPI_MEM_SMEM_DIN1_NUM_S))
+#define SPI_MEM_SMEM_DIN1_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN1_NUM_S  2
+/* SPI_MEM_SMEM_DIN0_NUM : HRO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+delayed by 2 cycles,....*/
+#define SPI_MEM_SMEM_DIN0_NUM    0x00000003
+#define SPI_MEM_SMEM_DIN0_NUM_M  ((SPI_MEM_SMEM_DIN0_NUM_V)<<(SPI_MEM_SMEM_DIN0_NUM_S))
+#define SPI_MEM_SMEM_DIN0_NUM_V  0x3
+#define SPI_MEM_SMEM_DIN0_NUM_S  0
+
+#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x19C)
+/* SPI_MEM_SMEM_DOUTS_MODE : HRO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_SMEM_DOUTS_MODE_M  (BIT(8))
+#define SPI_MEM_SMEM_DOUTS_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUTS_MODE_S  8
+/* SPI_MEM_SMEM_DOUT7_MODE : HRO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_SMEM_DOUT7_MODE_M  (BIT(7))
+#define SPI_MEM_SMEM_DOUT7_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT7_MODE_S  7
+/* SPI_MEM_SMEM_DOUT6_MODE : HRO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_SMEM_DOUT6_MODE_M  (BIT(6))
+#define SPI_MEM_SMEM_DOUT6_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT6_MODE_S  6
+/* SPI_MEM_SMEM_DOUT5_MODE : HRO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_SMEM_DOUT5_MODE_M  (BIT(5))
+#define SPI_MEM_SMEM_DOUT5_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT5_MODE_S  5
+/* SPI_MEM_SMEM_DOUT4_MODE : HRO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_SMEM_DOUT4_MODE_M  (BIT(4))
+#define SPI_MEM_SMEM_DOUT4_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT4_MODE_S  4
+/* SPI_MEM_SMEM_DOUT3_MODE : HRO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_SMEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_SMEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT3_MODE_S  3
+/* SPI_MEM_SMEM_DOUT2_MODE : HRO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_SMEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_SMEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT2_MODE_S  2
+/* SPI_MEM_SMEM_DOUT1_MODE : HRO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_SMEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_SMEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT1_MODE_S  1
+/* SPI_MEM_SMEM_DOUT0_MODE : HRO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: the output signals are delayed by system clock cycles, 0: output without delayed
+, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3:
+ output with the posedge of clk_160,4 output with the negedge of clk_160,5: outp
+ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
+#define SPI_MEM_SMEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_SMEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_SMEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_SMEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1A0)
+/* SPI_MEM_SMEM_SPLIT_TRANS_EN : HRO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI
+ transfers when one transfer will cross flash/EXT_RAM page corner, valid no matt
+er whether there is an ECC region or not..*/
+#define SPI_MEM_SMEM_SPLIT_TRANS_EN    (BIT(31))
+#define SPI_MEM_SMEM_SPLIT_TRANS_EN_M  (BIT(31))
+#define SPI_MEM_SMEM_SPLIT_TRANS_EN_V  0x1
+#define SPI_MEM_SMEM_SPLIT_TRANS_EN_S  31
+/* SPI_MEM_SMEM_CS_HOLD_DELAY : HRO ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
+SPI core clock cycles..*/
+#define SPI_MEM_SMEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SMEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_SMEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_SMEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_SMEM_ECC_16TO18_BYTE_EN : HRO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when
+accesses external RAM..*/
+#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
+#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_V  0x1
+#define SPI_MEM_SMEM_ECC_16TO18_BYTE_EN_S  16
+/* SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER : HRO ;bitpos:[15] ;default: 1'b1 ; */
+/*description: 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner wh
+en accesses external RAM..*/
+#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
+#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define SPI_MEM_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/* SPI_MEM_SMEM_ECC_CS_HOLD_TIME : HRO ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold c
+ycles in ECC mode when accessed external RAM..*/
+#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME    0x00000007
+#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S))
+#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_V  0x7
+#define SPI_MEM_SMEM_ECC_CS_HOLD_TIME_S  12
+/* SPI_MEM_SMEM_CS_HOLD_TIME : HRO ;bitpos:[11:7] ;default: 5'h1 ; */
+/*description: For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits a
+re combined with spi_mem_cs_hold bit..*/
+#define SPI_MEM_SMEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SMEM_CS_HOLD_TIME_S))
+#define SPI_MEM_SMEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_SMEM_CS_HOLD_TIME_S  7
+/* SPI_MEM_SMEM_CS_SETUP_TIME : HRO ;bitpos:[6:2] ;default: 5'h1 ; */
+/*description: For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with s
+pi_mem_cs_setup bit..*/
+#define SPI_MEM_SMEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SMEM_CS_SETUP_TIME_S))
+#define SPI_MEM_SMEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_SMEM_CS_SETUP_TIME_S  2
+/* SPI_MEM_SMEM_CS_HOLD : HRO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disab
+le..*/
+#define SPI_MEM_SMEM_CS_HOLD    (BIT(1))
+#define SPI_MEM_SMEM_CS_HOLD_M  (BIT(1))
+#define SPI_MEM_SMEM_CS_HOLD_V  0x1
+#define SPI_MEM_SMEM_CS_HOLD_S  1
+/* SPI_MEM_SMEM_CS_SETUP : HRO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: d
+isable..*/
+#define SPI_MEM_SMEM_CS_SETUP    (BIT(0))
+#define SPI_MEM_SMEM_CS_SETUP_M  (BIT(0))
+#define SPI_MEM_SMEM_CS_SETUP_V  0x1
+#define SPI_MEM_SMEM_CS_SETUP_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x200)
+/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
+#define SPI_MEM_CLK_EN    (BIT(0))
+#define SPI_MEM_CLK_EN_M  (BIT(0))
+#define SPI_MEM_CLK_EN_V  0x1
+#define SPI_MEM_CLK_EN_S  0
+
+#define SPI_MEM_MMU_ITEM_CONTENT_REG(i)          (REG_SPI_MEM_BASE(i) + 0x37C)
+/* SPI_MEM_MMU_ITEM_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: MSPI-MMU item content.*/
+#define SPI_MEM_MMU_ITEM_CONTENT    0xFFFFFFFF
+#define SPI_MEM_MMU_ITEM_CONTENT_M  ((SPI_MEM_MMU_ITEM_CONTENT_V)<<(SPI_MEM_MMU_ITEM_CONTENT_S))
+#define SPI_MEM_MMU_ITEM_CONTENT_V  0xFFFFFFFF
+#define SPI_MEM_MMU_ITEM_CONTENT_S  0
+
+#define SPI_MEM_MMU_ITEM_INDEX_REG(i)          (REG_SPI_MEM_BASE(i) + 0x380)
+/* SPI_MEM_MMU_ITEM_INDEX : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: MSPI-MMU item index.*/
+#define SPI_MEM_MMU_ITEM_INDEX    0xFFFFFFFF
+#define SPI_MEM_MMU_ITEM_INDEX_M  ((SPI_MEM_MMU_ITEM_INDEX_V)<<(SPI_MEM_MMU_ITEM_INDEX_S))
+#define SPI_MEM_MMU_ITEM_INDEX_V  0xFFFFFFFF
+#define SPI_MEM_MMU_ITEM_INDEX_S  0
+
+#define SPI_MEM_MMU_POWER_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x384)
+/* SPI_MEM_RDN_RESULT : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: MSPI module clock domain and AXI clock domain ECO register result register.*/
+#define SPI_MEM_RDN_RESULT    (BIT(31))
+#define SPI_MEM_RDN_RESULT_M  (BIT(31))
+#define SPI_MEM_RDN_RESULT_V  0x1
+#define SPI_MEM_RDN_RESULT_S  31
+/* SPI_MEM_RDN_ENA : HRO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: ECO register enable bit.*/
+#define SPI_MEM_RDN_ENA    (BIT(30))
+#define SPI_MEM_RDN_ENA_M  (BIT(30))
+#define SPI_MEM_RDN_ENA_V  0x1
+#define SPI_MEM_RDN_ENA_S  30
+/* SPI_MEM_AUX_CTRL : HRO ;bitpos:[29:16] ;default: 14'h1320 ; */
+/*description: MMU PSRAM aux control register.*/
+#define SPI_MEM_AUX_CTRL    0x00003FFF
+#define SPI_MEM_AUX_CTRL_M  ((SPI_MEM_AUX_CTRL_V)<<(SPI_MEM_AUX_CTRL_S))
+#define SPI_MEM_AUX_CTRL_V  0x3FFF
+#define SPI_MEM_AUX_CTRL_S  16
+/* SPI_MEM_MMU_PAGE_SIZE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
+/*description: 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8.*/
+#define SPI_MEM_MMU_PAGE_SIZE    0x00000003
+#define SPI_MEM_MMU_PAGE_SIZE_M  ((SPI_MEM_MMU_PAGE_SIZE_V)<<(SPI_MEM_MMU_PAGE_SIZE_S))
+#define SPI_MEM_MMU_PAGE_SIZE_V  0x3
+#define SPI_MEM_MMU_PAGE_SIZE_S  3
+/* SPI_MEM_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: Set this bit to force mmu-memory powerup, in this case, the power should also be
+ controlled by rtc..*/
+#define SPI_MEM_MMU_MEM_FORCE_PU    (BIT(2))
+#define SPI_MEM_MMU_MEM_FORCE_PU_M  (BIT(2))
+#define SPI_MEM_MMU_MEM_FORCE_PU_V  0x1
+#define SPI_MEM_MMU_MEM_FORCE_PU_S  2
+/* SPI_MEM_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to force mmu-memory powerdown.*/
+#define SPI_MEM_MMU_MEM_FORCE_PD    (BIT(1))
+#define SPI_MEM_MMU_MEM_FORCE_PD_M  (BIT(1))
+#define SPI_MEM_MMU_MEM_FORCE_PD_V  0x1
+#define SPI_MEM_MMU_MEM_FORCE_PD_S  1
+/* SPI_MEM_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable mmu-memory clock force on.*/
+#define SPI_MEM_MMU_MEM_FORCE_ON    (BIT(0))
+#define SPI_MEM_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define SPI_MEM_MMU_MEM_FORCE_ON_V  0x1
+#define SPI_MEM_MMU_MEM_FORCE_ON_S  0
+
+#define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F0)
+/* SPI_MEM_REGISTERRND_ECO_HIGH : RO ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: ECO high register.*/
+#define SPI_MEM_REGISTERRND_ECO_HIGH    0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_HIGH_M  ((SPI_MEM_REGISTERRND_ECO_HIGH_V)<<(SPI_MEM_REGISTERRND_ECO_HIGH_S))
+#define SPI_MEM_REGISTERRND_ECO_HIGH_V  0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_HIGH_S  0
+
+#define SPI_MEM_REGISTERRND_ECO_LOW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3F4)
+/* SPI_MEM_REGISTERRND_ECO_LOW : RO ;bitpos:[31:0] ;default: 32'h037c ; */
+/*description: ECO low register.*/
+#define SPI_MEM_REGISTERRND_ECO_LOW    0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_LOW_M  ((SPI_MEM_REGISTERRND_ECO_LOW_V)<<(SPI_MEM_REGISTERRND_ECO_LOW_S))
+#define SPI_MEM_REGISTERRND_ECO_LOW_V  0xFFFFFFFF
+#define SPI_MEM_REGISTERRND_ECO_LOW_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2203030 ; */
+/*description: SPI0 register version..*/
+#define SPI_MEM_DATE    0x0FFFFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0xFFFFFFF
+#define SPI_MEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/spi_mem_struct.h b/components/soc/esp32h2/register/soc/spi_mem_struct.h
new file mode 100644
index 00000000000..45810eb9afa
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/spi_mem_struct.h
@@ -0,0 +1,1076 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+typedef volatile struct spi_mem_dev_s {
+    union {
+        struct {
+            uint32_t mst_st                        :    4;  /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.*/
+            uint32_t slv_st                        :    4;  /*The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.*/
+            uint32_t reserved8                     :    9;  /*reserved*/
+            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t usr                           :    1;  /*SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_res                     :    1;  /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
+            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t wdummy_dqs_always_out         :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller.*/
+            uint32_t wdummy_always_out             :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.*/
+            uint32_t fdummy_rin                    :    1;  /*In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.*/
+            uint32_t fdummy_wout                   :    1;  /*In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.*/
+            uint32_t fdout_oct                     :    1;  /*Apply 8 signals during write-data phase 1:enable 0: disable*/
+            uint32_t fdin_oct                      :    1;  /*Apply 8 signals during read-data phase 1:enable 0: disable*/
+            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during address phase 1:enable 0: disable*/
+            uint32_t reserved7                     :    1;  /*reserved*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable*/
+            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12                    :    1;  /*reserved*/
+            uint32_t fastrd_mode                   :    1;  /*This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
+            uint32_t reserved16                    :    2;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
+            uint32_t wrsr_2b                       :    1;  /*two bytes data will be written to status register when it is set. 1: enable 0: disable. */
+            uint32_t fread_dio                     :    1;  /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t fread_qio                     :    1;  /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t reserved25                    :    5;  /*reserved*/
+            uint32_t dqs_ie_always_on              :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
+            uint32_t data_ie_always_on             :    1;  /*When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
+            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
+            uint32_t reserved2                     :    9;  /*reserved*/
+            uint32_t reg_ar_size0_1_support_en     :    1;  /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
+            uint32_t reg_aw_size0_1_support_en     :    1;  /*1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.*/
+            uint32_t reg_axi_rdata_back_fast       :    1;  /*1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available.*/
+            uint32_t rresp_ecc_err_en              :    1;  /*1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.*/
+            uint32_t ar_splice_en                  :    1;  /*Set this bit to enable AXI Read Splice-transfer.*/
+            uint32_t aw_splice_en                  :    1;  /*Set this bit to enable AXI Write Splice-transfer.*/
+            uint32_t ram0_en                       :    1;  /*When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1,  EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
+            uint32_t dual_ram_en                   :    1;  /*Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time.*/
+            uint32_t fast_write_en                 :    1;  /*Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in  tx_bus_fifo_l2.*/
+            uint32_t rxfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI.  Set this bit to reset these FIFO.*/
+            uint32_t txfifo_rst                    :    1;  /*The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.*/
+            uint32_t cs_hold_time                  :    5;  /*SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.*/
+            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.*/
+            uint32_t ecc_skip_page_corner          :    1;  /*1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
+            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
+            uint32_t reserved15                    :    9;  /*reserved*/
+            uint32_t split_trans_en                :    1;  /*Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
+            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t sync_reset                    :    1;  /*The spi0_mst_st and spi0_slv_st will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    8;  /*In the master mode it must be equal to spi_mem_clkcnt_N. */
+            uint32_t clkcnt_h                      :    8;  /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t clkcnt_n                      :    8;  /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24                    :    7;  /*In the master mode it is pre-divider of spi_mem_clk. */
+            uint32_t clk_equ_sysclk                :    1;  /*1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. */
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. */
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t ck_out_edge                   :    1;  /*The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3.*/
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals*/
+            uint32_t fwrite_dio                    :    1;  /*In the write operations address phase and read-data phase apply 2 signals.*/
+            uint32_t fwrite_qio                    :    1;  /*In the write operations address phase and read-data phase apply 4 signals.*/
+            uint32_t reserved16                    :    8;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. */
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    6;  /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t usr_dbytelen                  :    3;  /*SPI0 USR_CMD read or write data byte length -1*/
+            uint32_t reserved9                     :    17;  /*reserved*/
+            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status                        :    16;  /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t reserved_30;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t cs1_dis                       :    1;  /*SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.*/
+            uint32_t reserved0                     :    5;  /*reserved*/
+            uint32_t fsub_pin                      :    1;  /*For SPI0,  flash is connected to SUBPINs.*/
+            uint32_t ssub_pin                      :    1;  /*For SPI0,  sram is connected to SUBPINs.*/
+            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle     0: spi clk line is low when idle */
+            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;
+    union {
+        struct {
+            uint32_t axi_req_en                    :    1;  /*For SPI0, AXI master access enable, 1: enable, 0:disable.*/
+            uint32_t usr_addr_4byte                :    1;  /*For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.*/
+            uint32_t flash_usr_cmd                 :    1;  /*For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.*/
+            uint32_t fdin_dual                     :    1;  /*For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdout_dual                    :    1;  /*For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t faddr_dual                    :    1;  /*For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdin_quad                     :    1;  /*For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t fdout_quad                    :    1;  /*For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t faddr_quad                    :    1;  /*For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t reserved9                     :    21;  /*reserved*/
+            uint32_t reg_same_aw_ar_addr_chk_en    :    1;  /*Set this bit to check AXI read/write the same address region.*/
+            uint32_t reg_close_axi_inf_en          :    1;  /*Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP.*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    union {
+        struct {
+            uint32_t usr_saddr_4byte               :    1;  /*For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable.*/
+            uint32_t usr_sram_dio                  :    1;  /*For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable*/
+            uint32_t usr_sram_qio                  :    1;  /*For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable*/
+            uint32_t usr_wr_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.*/
+            uint32_t usr_rd_sram_dummy             :    1;  /*For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations.*/
+            uint32_t sram_usr_rcmd                 :    1;  /*For SPI0, In the external RAM mode cache read external RAM for user define command.*/
+            uint32_t sram_rdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved12                    :    2;  /*reserved*/
+            uint32_t sram_addr_bitlen              :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1).*/
+            uint32_t sram_usr_wcmd                 :    1;  /*For SPI0, In the external RAM mode cache write sram for user define command*/
+            uint32_t sram_oct                      :    1;  /*reserved*/
+            uint32_t sram_wdummy_cyclelen          :    6;  /*For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_sctrl;
+    union {
+        struct {
+            uint32_t sclk_mode                     :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
+            uint32_t swb_mode                      :    8;  /*Mode bits in the external RAM fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t sdin_dual                     :    1;  /*For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t sdout_dual                    :    1;  /*For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t saddr_dual                    :    1;  /*For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t reserved13                    :    1;  /*reserved*/
+            uint32_t sdin_quad                     :    1;  /*For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t sdout_quad                    :    1;  /*For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t saddr_quad                    :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t scmd_quad                     :    1;  /*For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t sdin_oct                      :    1;  /*For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t sdout_oct                     :    1;  /*For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t saddr_oct                     :    1;  /*For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. */
+            uint32_t scmd_oct                      :    1;  /*For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. */
+            uint32_t sdummy_rin                    :    1;  /*In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
+            uint32_t sdummy_wout                   :    1;  /*In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.*/
+            uint32_t reg_smem_wdummy_dqs_always_out:    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.*/
+            uint32_t reg_smem_wdummy_always_out    :    1;  /*In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.*/
+            uint32_t reserved26                    :    4;  /*reserved*/
+            uint32_t reg_smem_dqs_ie_always_on     :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.*/
+            uint32_t reg_smem_data_ie_always_on    :    1;  /*When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.*/
+        };
+        uint32_t val;
+    } sram_cmd;
+    union {
+        struct {
+            uint32_t sram_usr_rd_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the read command value of command phase for sram.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t sram_usr_rd_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_drd_cmd;
+    union {
+        struct {
+            uint32_t sram_usr_wr_cmd_value         :    16;  /*For SPI0,When cache mode is enable it is the write command value of command phase for sram.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t sram_usr_wr_cmd_bitlen        :    4;  /*For SPI0,When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_dwr_cmd;
+    union {
+        struct {
+            uint32_t sclkcnt_l                     :    8;  /*For SPI0 external RAM  interface, it must be equal to spi_mem_clkcnt_N.*/
+            uint32_t sclkcnt_h                     :    8;  /*For SPI0 external RAM  interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+            uint32_t sclkcnt_n                     :    8;  /*For SPI0 external RAM  interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24                    :    7;  /*reserved*/
+            uint32_t sclk_equ_sysclk               :    1;  /*For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/
+        };
+        uint32_t val;
+    } sram_clk;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;  /*reserved*/
+            uint32_t lock_delay_time               :    5;  /*The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    uint32_t data_buf[16];
+    union {
+        struct {
+            uint32_t waiti_en                      :    1;  /*1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.*/
+            uint32_t waiti_dummy                   :    1;  /*The dummy phase enable when wait flash idle (RDSR)*/
+            uint32_t waiti_addr_en                 :    1;  /*1: Output  address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.*/
+            uint32_t waiti_addr_cyclelen           :    2;  /*When SPI_MEM_WAITI_ADDR_EN is set, the  cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI  bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.*/
+            uint32_t reserved5                     :    4;  /*reserved*/
+            uint32_t waiti_cmd_2b                  :    1;  /*1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.*/
+            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
+            uint32_t waiti_cmd                     :    16;  /*The command value to wait flash idle(RDSR).*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_per_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. */
+            uint32_t flash_pes_wait_en             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. */
+            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.*/
+            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable Auto-suspending function.*/
+            uint32_t pesr_end_msk                  :    16;  /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
+            uint32_t frd_sus_2b                    :    1;  /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit*/
+            uint32_t per_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t pes_end_en                    :    1;  /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
+            uint32_t sus_timeout_cnt               :    7;  /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.*/
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t flash_pes_command             :    16;  /*Program/Erase suspend command.*/
+            uint32_t wait_pesr_command             :    16;  /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_sus                     :    1;  /*The status of flash suspend, only used in SPI1.*/
+            uint32_t wait_pesr_cmd_2b              :    1;  /*1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.*/
+            uint32_t flash_hpm_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
+            uint32_t flash_res_dly_128             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
+            uint32_t flash_dp_dly_128              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
+            uint32_t flash_per_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
+            uint32_t flash_pes_dly_128             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
+            uint32_t spi0_lock_en                  :    1;  /*1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.*/
+            uint32_t reserved8                     :    7;  /*reserved*/
+            uint32_t flash_pesr_cmd_2b             :    1;  /*1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8.*/
+            uint32_t flash_per_command             :    16;  /*Program/Erase resume command.*/
+        };
+        uint32_t val;
+    } sus_status;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    union {
+        struct {
+            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end_en                    :    1;  /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end_en                 :    1;  /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end_en                 :    1;  /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject_en                 :    1;  /*The enable bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err_en           :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err_en              :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err                       :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject                    :    1;  /*The clear bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err                 :    1;  /*The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
+            uint32_t pes_end                       :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
+            uint32_t wpe_end                       :    1;  /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
+            uint32_t slv_st_end                    :    1;  /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
+            uint32_t mst_st_end                    :    1;  /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.*/
+            uint32_t ecc_err                       :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and  SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and  SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and  SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
+            uint32_t pms_reject                    :    1;  /*The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.*/
+            uint32_t axi_raddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
+            uint32_t axi_waddr_err                 :    1;  /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
+            uint32_t brown_out                     :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t per_end                       :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end                       :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t wpe_end                       :    1;  /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
+            uint32_t slv_st_end                    :    1;  /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
+            uint32_t mst_st_end                    :    1;  /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
+            uint32_t ecc_err                       :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t pms_reject                    :    1;  /*The status bit for SPI_MEM_PMS_REJECT_INT interrupt.*/
+            uint32_t axi_raddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt.*/
+            uint32_t axi_wr_flash_err              :    1;  /*The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt.*/
+            uint32_t axi_waddr_err                 :    1;  /*The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt.*/
+            uint32_t brown_out                     :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t reserved11                    :    21;  /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_d0;
+    union {
+        struct {
+            uint32_t reg_fmem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
+            uint32_t reg_fmem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
+            uint32_t reg_fmem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
+            uint32_t reg_fmem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
+            uint32_t reg_fmem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
+            uint32_t reg_fmem_outminbytelen        :    7;  /*It is the minimum output data length in the panda device.*/
+            uint32_t reg_fmem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.*/
+            uint32_t reg_fmem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.*/
+            uint32_t reg_fmem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
+            uint32_t reg_fmem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t reg_fmem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
+            uint32_t reserved25                    :    1;  /*reserved*/
+            uint32_t reg_fmem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
+            uint32_t reg_fmem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
+            uint32_t reg_fmem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
+            uint32_t reg_fmem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
+            uint32_t reg_fmem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } ddr;
+    union {
+        struct {
+            uint32_t reg_smem_ddr_en               :    1;  /*1: in DDR mode,  0 in SDR mode*/
+            uint32_t reg_smem_var_dummy            :    1;  /*Set the bit to enable variable dummy cycle in spi DDR mode.*/
+            uint32_t reg_smem_ddr_rdat_swp         :    1;  /*Set the bit to reorder rx data of the word in spi DDR mode.*/
+            uint32_t reg_smem_ddr_wdat_swp         :    1;  /*Set the bit to reorder tx data of the word in spi DDR mode.*/
+            uint32_t reg_smem_ddr_cmd_dis          :    1;  /*the bit is used to disable dual edge in command phase when DDR mode.*/
+            uint32_t reg_smem_outminbytelen        :    7;  /*It is the minimum output data length in the DDR psram.*/
+            uint32_t reg_smem_tx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.*/
+            uint32_t reg_smem_rx_ddr_msk_en        :    1;  /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.*/
+            uint32_t reg_smem_usr_ddr_dqs_thd      :    7;  /*The delay number of data strobe which from memory based on SPI clock.*/
+            uint32_t reg_smem_ddr_dqs_loop         :    1;  /*1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t reg_smem_clk_diff_en          :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
+            uint32_t reserved25                    :    1;  /*reserved*/
+            uint32_t reg_smem_dqs_ca_in            :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
+            uint32_t reg_smem_hyperbus_dummy_2x    :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.*/
+            uint32_t reg_smem_clk_diff_inv         :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
+            uint32_t reg_smem_octa_ram_addr        :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
+            uint32_t reg_smem_hyperbus_ca          :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_ddr;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    union {
+        struct {
+            uint32_t reg_fmem_pms0_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms0_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms0_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_attr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms1_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms1_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms1_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_attr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms2_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms2_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms2_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_attr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms3_rd_attr         :    1;  /*1: SPI1 flash ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms3_wr_attr         :    1;  /*1: SPI1 flash ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_fmem_pms3_ecc             :    1;  /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section $n is configured by registers SPI_FMEM_PMS$n_ADDR_REG and SPI_FMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_attr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms0_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_addr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms1_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_addr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms2_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_addr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms3_addr_s          :    26;  /*SPI1 flash ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_addr;
+    union {
+        struct {
+            uint32_t reg_fmem_pms0_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms0_size;
+    union {
+        struct {
+            uint32_t reg_fmem_pms1_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms1_size;
+    union {
+        struct {
+            uint32_t reg_fmem_pms2_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms2_size;
+    union {
+        struct {
+            uint32_t reg_fmem_pms3_size            :    14;  /*SPI1 flash ACE section $n address region is (SPI_FMEM_PMS$n_ADDR_S, SPI_FMEM_PMS$n_ADDR_S + SPI_FMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_fmem_pms3_size;
+    union {
+        struct {
+            uint32_t reg_smem_pms0_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms0_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms0_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_attr;
+    union {
+        struct {
+            uint32_t reg_smem_pms1_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms1_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms1_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_attr;
+    union {
+        struct {
+            uint32_t reg_smem_pms2_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms2_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms2_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_attr;
+    union {
+        struct {
+            uint32_t reg_smem_pms3_rd_attr         :    1;  /*1: SPI1 external RAM ACE section $n read accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms3_wr_attr         :    1;  /*1: SPI1 external RAM ACE section $n write accessible. 0: Not allowed.*/
+            uint32_t reg_smem_pms3_ecc             :    1;  /*SPI1 external RAM ACE section $n ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section $n is configured by registers SPI_SMEM_PMS$n_ADDR_REG and SPI_SMEM_PMS$n_SIZE_REG.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_attr;
+    union {
+        struct {
+            uint32_t reg_smem_pms0_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_addr;
+    union {
+        struct {
+            uint32_t reg_smem_pms1_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_addr;
+    union {
+        struct {
+            uint32_t reg_smem_pms2_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_addr;
+    union {
+        struct {
+            uint32_t reg_smem_pms3_addr_s          :    26;  /*SPI1 external RAM ACE section $n start address value*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_addr;
+    union {
+        struct {
+            uint32_t reg_smem_pms0_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms0_size;
+    union {
+        struct {
+            uint32_t reg_smem_pms1_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms1_size;
+    union {
+        struct {
+            uint32_t reg_smem_pms2_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms2_size;
+    union {
+        struct {
+            uint32_t reg_smem_pms3_size            :    14;  /*SPI1 external RAM ACE section $n address region is (SPI_SMEM_PMS$n_ADDR_S, SPI_SMEM_PMS$n_ADDR_S + SPI_SMEM_PMS$n_SIZE)*/
+            uint32_t reserved14                    :    18;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_pms3_size;
+    uint32_t reserved_160;
+    union {
+        struct {
+            uint32_t reject_addr                   :    26;  /*This bits show the first SPI1 access error address. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pm_en                         :    1;  /*Set this bit to enable SPI0/1 transfer permission control function.*/
+            uint32_t reserved27                    :    1;  /*reserved*/
+            uint32_t pms_ld                        :    1;  /*1: SPI1 write access error. 0: No write access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_st                        :    1;  /*1: SPI1 read access error. 0: No read access error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_multi_hit                 :    1;  /*1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+            uint32_t pms_ivd                       :    1;  /*1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when  SPI_MEM_PMS_REJECT_INT_CLR bit is set. */
+        };
+        uint32_t val;
+    } pms_reject;
+    union {
+        struct {
+            uint32_t reserved0                     :    11;  /*reserved*/
+            uint32_t ecc_err_int_num               :    6;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t reg_fmem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
+            uint32_t reg_fmem_page_size            :    2;  /*Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
+            uint32_t reg_fmem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1.*/
+            uint32_t usr_ecc_addr_en               :    1;  /*Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer.*/
+            uint32_t reserved22                    :    2;  /*reserved*/
+            uint32_t ecc_continue_record_err_en    :    1;  /*1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information.*/
+            uint32_t ecc_err_bits                  :    7;  /*Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)*/
+        };
+        uint32_t val;
+    } ecc_ctrl;
+    union {
+        struct {
+            uint32_t ecc_err_addr                  :    26;  /*This bits show the first MSPI ECC error address. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
+            uint32_t ecc_err_cnt                   :    6;  /*This bits show the error times of MSPI ECC read. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
+        };
+        uint32_t val;
+    } ecc_err_addr;
+    union {
+        struct {
+            uint32_t axi_err_addr                  :    26;  /*This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */
+            uint32_t all_fifo_empty                :    1;  /*The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.*/
+            uint32_t reg_rdata_afifo_rempty        :    1;  /*1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
+            uint32_t reg_raddr_afifo_rempty        :    1;  /*1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.*/
+            uint32_t reg_wdata_afifo_rempty        :    1;  /*1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
+            uint32_t reg_wblen_afifo_rempty        :    1;  /*1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.*/
+            uint32_t reg_all_axi_trans_afifo_empty :    1;  /*This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.*/
+        };
+        uint32_t val;
+    } axi_err_addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    17;  /*reserved*/
+            uint32_t reg_smem_ecc_err_int_en       :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
+            uint32_t reg_smem_page_size            :    2;  /*Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
+            uint32_t reg_smem_ecc_addr_en          :    1;  /*Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_ecc_ctrl;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    union {
+        struct {
+            uint32_t timing_clk_ena                :    1;  /*The bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t timing_cali                   :    1;  /*The bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t extra_dummy_cyclelen          :    3;  /*add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t dll_timing_cali               :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash.*/
+            uint32_t timing_cali_update            :    1;  /*Set this bit to update delay mode, delay num and extra dummy in MSPI.*/
+            uint32_t reserved7                     :    25;  /*reserved*/
+        };
+        uint32_t val;
+    } timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din1_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din2_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din3_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t din4_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din5_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din6_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t din7_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t dins_mode                     :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din4_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din5_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din6_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t din7_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t dins_num                      :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout1_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout2_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout3_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t dout4_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout5_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout6_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t dout7_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t douts_mode                    :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t reg_smem_timing_clk_ena       :    1;  /*For sram, the bit is used to enable timing adjust clock for all reading operations.*/
+            uint32_t reg_smem_timing_cali          :    1;  /*For sram, the bit is used to enable timing auto-calibration for all reading operations.*/
+            uint32_t reg_smem_extra_dummy_cyclelen :    3;  /*For sram, add extra dummy spi clock cycle length for spi clock calibration.*/
+            uint32_t reg_smem_dll_timing_cali      :    1;  /*Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_timing_cali;
+    union {
+        struct {
+            uint32_t reg_smem_din0_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din1_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din2_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din3_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din4_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din5_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din6_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_din7_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reg_smem_dins_mode            :    3;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_mode;
+    union {
+        struct {
+            uint32_t reg_smem_din0_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din1_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din2_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din3_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din4_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din5_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din6_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_din7_num             :    2;  /*the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...*/
+            uint32_t reg_smem_dins_num             :    2;  /*the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_num;
+    union {
+        struct {
+            uint32_t reg_smem_dout0_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout1_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout2_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout3_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout4_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout5_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout6_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_dout7_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reg_smem_douts_mode           :    1;  /*the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_dout_mode;
+    union {
+        struct {
+            uint32_t reg_smem_cs_setup             :    1;  /*For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. */
+            uint32_t reg_smem_cs_hold              :    1;  /*For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */
+            uint32_t reg_smem_cs_setup_time        :    5;  /*For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
+            uint32_t reg_smem_cs_hold_time         :    5;  /*For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
+            uint32_t reg_smem_ecc_cs_hold_time     :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM.*/
+            uint32_t reg_smem_ecc_skip_page_corner :    1;  /*1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/
+            uint32_t reg_smem_ecc_16to18_byte_en   :    1;  /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/
+            uint32_t reserved17                    :    8;  /*reserved*/
+            uint32_t reg_smem_cs_hold_delay        :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t reg_smem_split_trans_en       :    1;  /*Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
+        };
+        uint32_t val;
+    } spi_smem_ac;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t xts_plain_base;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    union {
+        struct {
+            uint32_t reg_xts_linesize              :    2;  /*This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved.*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_linesize;
+    union {
+        struct {
+            uint32_t reg_xts_destination           :    1;  /*This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_destination;
+    union {
+        struct {
+            uint32_t reg_xts_physical_address      :    26;  /*This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter.*/
+            uint32_t reserved26                    :    6;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_physical_address;
+    union {
+        struct {
+            uint32_t reg_xts_trigger               :    1;  /*Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_trigger;
+    union {
+        struct {
+            uint32_t reg_xts_release               :    1;  /*Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_release;
+    union {
+        struct {
+            uint32_t reg_xts_destroy               :    1;  /*Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_destroy;
+    union {
+        struct {
+            uint32_t reg_xts_state                 :    2;  /*This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi.*/
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_state;
+    union {
+        struct {
+            uint32_t reg_xts_date                  :    30;  /*This bits stores the last modified-time of manual encryption feature.*/
+            uint32_t reserved30                    :    2;  /*reserved*/
+        };
+        uint32_t val;
+    } xts_date;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t mmu_item_content;
+    uint32_t mmu_item_index;
+    union {
+        struct {
+            uint32_t reg_mmu_mem_force_on          :    1;  /*Set this bit to enable mmu-memory clock force on*/
+            uint32_t reg_mmu_mem_force_pd          :    1;  /*Set this bit to force mmu-memory powerdown*/
+            uint32_t reg_mmu_mem_force_pu          :    1;  /*Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc.*/
+            uint32_t reg_mmu_page_size             :    2;  /*0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8*/
+            uint32_t reserved5                     :    11;  /*reserved*/
+            uint32_t aux_ctrl                      :    14;  /*MMU PSRAM aux control register*/
+            uint32_t rdn_ena                       :    1;  /*ECO register enable bit*/
+            uint32_t rdn_result                    :    1;  /*MSPI module clock domain and AXI clock domain ECO register result register*/
+        };
+        uint32_t val;
+    } mmu_power_ctrl;
+    union {
+        struct {
+            uint32_t reg_crypt_security_level      :    3;  /*Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
+            uint32_t reg_crypt_calc_d_dpa_en       :    1;  /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
+            uint32_t reg_crypt_dpa_selectister     :    1;  /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } dpa_ctrl;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t spi_memisterrnd_eco_high;
+    uint32_t spi_memisterrnd_eco_low;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI0 register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/spi_reg.h b/components/soc/esp32h2/register/soc/spi_reg.h
new file mode 100644
index 00000000000..d1326cea82a
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/spi_reg.h
@@ -0,0 +1,2114 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI_CMD_REG register
+ *  Command control register
+ */
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
+/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+ */
+#define SPI_CONF_BITLEN    0x0003FFFFU
+#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
+#define SPI_CONF_BITLEN_V  0x0003FFFFU
+#define SPI_CONF_BITLEN_S  0
+/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
+ *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+ *  clock domain, which is only used in SPI master mode.
+ */
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
+#define SPI_UPDATE_V  0x00000001U
+#define SPI_UPDATE_S  23
+/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
+ *  User define command enable.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+ *  changed by CONF_buf.
+ */
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
+#define SPI_USR_V  0x00000001U
+#define SPI_USR_S  24
+
+/** SPI_ADDR_REG register
+ *  Address value register
+ */
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
+/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  Address to slave. Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_S  0
+
+/** SPI_CTRL_REG register
+ *  SPI control register
+ */
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
+/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
+ *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+ *  the FSPI bus signals are output. Can be configured in CONF state.
+ */
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
+#define SPI_DUMMY_OUT_V  0x00000001U
+#define SPI_DUMMY_OUT_S  3
+/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+ *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
+#define SPI_FADDR_DUAL_V  0x00000001U
+#define SPI_FADDR_DUAL_S  5
+/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
+ *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
+#define SPI_FADDR_QUAD_V  0x00000001U
+#define SPI_FADDR_QUAD_S  6
+/** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0;
+ *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_OCT    (BIT(7))
+#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
+#define SPI_FADDR_OCT_V  0x00000001U
+#define SPI_FADDR_OCT_S  7
+/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
+ *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
+#define SPI_FCMD_DUAL_V  0x00000001U
+#define SPI_FCMD_DUAL_S  8
+/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
+ *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
+#define SPI_FCMD_QUAD_V  0x00000001U
+#define SPI_FCMD_QUAD_S  9
+/** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0;
+ *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_OCT    (BIT(10))
+#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
+#define SPI_FCMD_OCT_V  0x00000001U
+#define SPI_FCMD_OCT_S  10
+/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
+#define SPI_FREAD_DUAL_V  0x00000001U
+#define SPI_FREAD_DUAL_S  14
+/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
+ *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
+#define SPI_FREAD_QUAD_V  0x00000001U
+#define SPI_FREAD_QUAD_S  15
+/** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0;
+ *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_OCT    (BIT(16))
+#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
+#define SPI_FREAD_OCT_V  0x00000001U
+#define SPI_FREAD_OCT_S  16
+/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
+#define SPI_Q_POL_V  0x00000001U
+#define SPI_Q_POL_S  18
+/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
+#define SPI_D_POL_V  0x00000001U
+#define SPI_D_POL_S  19
+/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
+ *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+ *  configured in CONF state.
+ */
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
+#define SPI_HOLD_POL_V  0x00000001U
+#define SPI_HOLD_POL_S  20
+/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
+ *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
+#define SPI_WP_POL_V  0x00000001U
+#define SPI_WP_POL_S  21
+/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
+ *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+ *  state.
+ */
+#define SPI_RD_BIT_ORDER    0x00000003U
+#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
+#define SPI_RD_BIT_ORDER_V  0x00000003U
+#define SPI_RD_BIT_ORDER_S  23
+/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
+ *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+ *  configured in CONF state.
+ */
+#define SPI_WR_BIT_ORDER    0x00000003U
+#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
+#define SPI_WR_BIT_ORDER_V  0x00000003U
+#define SPI_WR_BIT_ORDER_S  25
+
+/** SPI_CLOCK_REG register
+ *  SPI clock control register
+ */
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
+/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
+ *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+ *  0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_L    0x0000003FU
+#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
+#define SPI_CLKCNT_L_V  0x0000003FU
+#define SPI_CLKCNT_L_S  0
+/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
+ *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+ *  must be 0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_H    0x0000003FU
+#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
+#define SPI_CLKCNT_H_V  0x0000003FU
+#define SPI_CLKCNT_H_S  6
+/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
+ *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+ *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_N    0x0000003FU
+#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
+#define SPI_CLKCNT_N_V  0x0000003FU
+#define SPI_CLKCNT_N_S  12
+/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
+ *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+ */
+#define SPI_CLKDIV_PRE    0x0000000FU
+#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
+#define SPI_CLKDIV_PRE_V  0x0000000FU
+#define SPI_CLKDIV_PRE_S  18
+/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
+ *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+ *  clock. Can be configured in CONF state.
+ */
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
+#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_CLK_EQU_SYSCLK_S  31
+
+/** SPI_USER_REG register
+ *  SPI USER control register
+ */
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
+/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
+ *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
+#define SPI_DOUTDIN_V  0x00000001U
+#define SPI_DOUTDIN_S  0
+/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
+ *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+ *  Can be configured in CONF state.
+ */
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
+#define SPI_QPI_MODE_V  0x00000001U
+#define SPI_QPI_MODE_S  3
+/** SPI_OPI_MODE : HRO; bitpos: [4]; default: 0;
+ *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+ *  Can be configured in CONF state.
+ */
+#define SPI_OPI_MODE    (BIT(4))
+#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
+#define SPI_OPI_MODE_V  0x00000001U
+#define SPI_OPI_MODE_S  4
+/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+ *  spi_ck_i. 1:tsck = !spi_ck_i.
+ */
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
+#define SPI_TSCK_I_EDGE_V  0x00000001U
+#define SPI_TSCK_I_EDGE_S  5
+/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
+ *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
+#define SPI_CS_HOLD_V  0x00000001U
+#define SPI_CS_HOLD_S  6
+/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
+ *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
+#define SPI_CS_SETUP_V  0x00000001U
+#define SPI_CS_SETUP_S  7
+/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+ *  !spi_ck_i. 1:rsck = spi_ck_i.
+ */
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
+#define SPI_RSCK_I_EDGE_V  0x00000001U
+#define SPI_RSCK_I_EDGE_S  8
+/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
+#define SPI_CK_OUT_EDGE_V  0x00000001U
+#define SPI_CK_OUT_EDGE_S  9
+/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+ *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
+#define SPI_FWRITE_DUAL_V  0x00000001U
+#define SPI_FWRITE_DUAL_S  12
+/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+ *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
+#define SPI_FWRITE_QUAD_V  0x00000001U
+#define SPI_FWRITE_QUAD_S  13
+/** SPI_FWRITE_OCT : HRO; bitpos: [14]; default: 0;
+ *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_OCT    (BIT(14))
+#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
+#define SPI_FWRITE_OCT_V  0x00000001U
+#define SPI_FWRITE_OCT_S  14
+/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
+ *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+ *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+ *  not seg-trans mode. Can be configured in CONF state.
+ */
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
+#define SPI_USR_CONF_NXT_V  0x00000001U
+#define SPI_USR_CONF_NXT_S  15
+/** SPI_SIO : R/W; bitpos: [17]; default: 0;
+ *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+ *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+ */
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
+#define SPI_SIO_V  0x00000001U
+#define SPI_SIO_S  17
+/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+ *  disable. Can be configured in CONF state.
+ */
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
+#define SPI_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI_USR_MISO_HIGHPART_S  24
+/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ *  0: disable.  Can be configured in CONF state.
+ */
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
+#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI_USR_MOSI_HIGHPART_S  25
+/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ *  CONF state.
+ */
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
+#define SPI_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_USR_DUMMY_IDLE_S  26
+/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
+ *  This bit enable the write-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
+#define SPI_USR_MOSI_V  0x00000001U
+#define SPI_USR_MOSI_S  27
+/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
+ *  This bit enable the read-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
+#define SPI_USR_MISO_V  0x00000001U
+#define SPI_USR_MISO_S  28
+/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
+#define SPI_USR_DUMMY_V  0x00000001U
+#define SPI_USR_DUMMY_S  29
+/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
+ *  This bit enable the address phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
+#define SPI_USR_ADDR_V  0x00000001U
+#define SPI_USR_ADDR_S  30
+/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+ *  This bit enable the command phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
+#define SPI_USR_COMMAND_V  0x00000001U
+#define SPI_USR_COMMAND_S  31
+
+/** SPI_USER1_REG register
+ *  SPI USER control register 1
+ */
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
+/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
+ *  The length in spi_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1). Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
+#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
+ *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+ *  GP-SPI master FD/HD-mode.
+ */
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
+#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
+ *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+ *  bit. Can be configured in CONF state.
+ */
+#define SPI_CS_SETUP_TIME    0x0000001FU
+#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
+#define SPI_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_CS_SETUP_TIME_S  17
+/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
+ *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS_HOLD_TIME    0x0000001FU
+#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
+#define SPI_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_CS_HOLD_TIME_S  22
+/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define SPI_USR_ADDR_BITLEN    0x0000001FU
+#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
+#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
+#define SPI_USR_ADDR_BITLEN_S  27
+
+/** SPI_USER2_REG register
+ *  SPI USER control register 2
+ */
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
+/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command. Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
+#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_S  0
+/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
+ *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+ *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+ *  is valid in GP-SPI master FD/HD-mode.
+ */
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
+#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_S  28
+
+/** SPI_MS_DLEN_REG register
+ *  SPI data bit length control register
+ */
+#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
+/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  The value of these bits is the configured SPI transmission data bit length in
+ *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+ *  the configured bit length in slave mode DMA RX controlled transfer. The register
+ *  value shall be (bit_num-1). Can be configured in CONF state.
+ */
+#define SPI_MS_DATA_BITLEN    0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
+#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_S  0
+
+/** SPI_MISC_REG register
+ *  SPI misc register
+ */
+#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
+/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
+#define SPI_CS0_DIS_V  0x00000001U
+#define SPI_CS0_DIS_S  0
+/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
+#define SPI_CS1_DIS_V  0x00000001U
+#define SPI_CS1_DIS_S  1
+/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
+#define SPI_CS2_DIS_V  0x00000001U
+#define SPI_CS2_DIS_S  2
+/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
+#define SPI_CS3_DIS_V  0x00000001U
+#define SPI_CS3_DIS_S  3
+/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
+#define SPI_CS4_DIS_V  0x00000001U
+#define SPI_CS4_DIS_S  4
+/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
+#define SPI_CS5_DIS_V  0x00000001U
+#define SPI_CS5_DIS_S  5
+/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
+ *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+ */
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
+#define SPI_CK_DIS_V  0x00000001U
+#define SPI_CK_DIS_S  6
+/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
+ *  In the master mode the bits are the polarity of spi cs line, the value is
+ *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+ */
+#define SPI_MASTER_CS_POL    0x0000003FU
+#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
+#define SPI_MASTER_CS_POL_V  0x0000003FU
+#define SPI_MASTER_CS_POL_S  7
+/** SPI_CLK_DATA_DTR_EN : HRO; bitpos: [16]; default: 0;
+ *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+ *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+ */
+#define SPI_CLK_DATA_DTR_EN    (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
+#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
+#define SPI_CLK_DATA_DTR_EN_S  16
+/** SPI_DATA_DTR_EN : HRO; bitpos: [17]; default: 0;
+ *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+ *  Can be configured in CONF state.
+ */
+#define SPI_DATA_DTR_EN    (BIT(17))
+#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
+#define SPI_DATA_DTR_EN_V  0x00000001U
+#define SPI_DATA_DTR_EN_S  17
+/** SPI_ADDR_DTR_EN : HRO; bitpos: [18]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+#define SPI_ADDR_DTR_EN    (BIT(18))
+#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
+#define SPI_ADDR_DTR_EN_V  0x00000001U
+#define SPI_ADDR_DTR_EN_S  18
+/** SPI_CMD_DTR_EN : HRO; bitpos: [19]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+ *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CMD_DTR_EN    (BIT(19))
+#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
+#define SPI_CMD_DTR_EN_V  0x00000001U
+#define SPI_CMD_DTR_EN_S  19
+/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
+ *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+ *  CONF state.
+ */
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
+#define SPI_SLAVE_CS_POL_V  0x00000001U
+#define SPI_SLAVE_CS_POL_S  23
+/** SPI_DQS_IDLE_EDGE : HRO; bitpos: [24]; default: 0;
+ *  The default value of spi_dqs. Can be configured in CONF state.
+ */
+#define SPI_DQS_IDLE_EDGE    (BIT(24))
+#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
+#define SPI_DQS_IDLE_EDGE_V  0x00000001U
+#define SPI_DQS_IDLE_EDGE_S  24
+/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
+ *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
+#define SPI_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_CK_IDLE_EDGE_S  29
+/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
+ *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+ */
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
+#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_CS_KEEP_ACTIVE_S  30
+/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
+ *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+ *  spi quad input swap disable. Can be configured in CONF state.
+ */
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+
+/** SPI_DIN_MODE_REG register
+ *  SPI input delay mode configuration
+ */
+#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
+/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN0_MODE    0x00000003U
+#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
+#define SPI_DIN0_MODE_V  0x00000003U
+#define SPI_DIN0_MODE_S  0
+/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN1_MODE    0x00000003U
+#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
+#define SPI_DIN1_MODE_V  0x00000003U
+#define SPI_DIN1_MODE_S  2
+/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN2_MODE    0x00000003U
+#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
+#define SPI_DIN2_MODE_V  0x00000003U
+#define SPI_DIN2_MODE_S  4
+/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN3_MODE    0x00000003U
+#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
+#define SPI_DIN3_MODE_V  0x00000003U
+#define SPI_DIN3_MODE_S  6
+/** SPI_DIN4_MODE : HRO; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN4_MODE    0x00000003U
+#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
+#define SPI_DIN4_MODE_V  0x00000003U
+#define SPI_DIN4_MODE_S  8
+/** SPI_DIN5_MODE : HRO; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the
+ *  (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
+ *  3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  falling edge cycle. Can be configured in CONF state.
+ */
+#define SPI_DIN5_MODE    0x00000003U
+#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
+#define SPI_DIN5_MODE_V  0x00000003U
+#define SPI_DIN5_MODE_S  10
+/** SPI_DIN6_MODE : HRO; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the
+ *  (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
+ *  3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  falling edge cycle. Can be configured in CONF state.
+ */
+#define SPI_DIN6_MODE    0x00000003U
+#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
+#define SPI_DIN6_MODE_V  0x00000003U
+#define SPI_DIN6_MODE_S  12
+/** SPI_DIN7_MODE : HRO; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the
+ *  (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
+ *  3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
+ *  falling edge cycle. Can be configured in CONF state.
+ */
+#define SPI_DIN7_MODE    0x00000003U
+#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
+#define SPI_DIN7_MODE_V  0x00000003U
+#define SPI_DIN7_MODE_S  14
+/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
+ *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+ *  state.
+ */
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
+#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+
+/** SPI_DIN_NUM_REG register
+ *  SPI input delay number configuration
+ */
+#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
+/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN0_NUM    0x00000003U
+#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
+#define SPI_DIN0_NUM_V  0x00000003U
+#define SPI_DIN0_NUM_S  0
+/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN1_NUM    0x00000003U
+#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
+#define SPI_DIN1_NUM_V  0x00000003U
+#define SPI_DIN1_NUM_S  2
+/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN2_NUM    0x00000003U
+#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
+#define SPI_DIN2_NUM_V  0x00000003U
+#define SPI_DIN2_NUM_S  4
+/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN3_NUM    0x00000003U
+#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
+#define SPI_DIN3_NUM_V  0x00000003U
+#define SPI_DIN3_NUM_S  6
+/** SPI_DIN4_NUM : HRO; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN4_NUM    0x00000003U
+#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
+#define SPI_DIN4_NUM_V  0x00000003U
+#define SPI_DIN4_NUM_S  8
+/** SPI_DIN5_NUM : HRO; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN5_NUM    0x00000003U
+#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
+#define SPI_DIN5_NUM_V  0x00000003U
+#define SPI_DIN5_NUM_S  10
+/** SPI_DIN6_NUM : HRO; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN6_NUM    0x00000003U
+#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
+#define SPI_DIN6_NUM_V  0x00000003U
+#define SPI_DIN6_NUM_S  12
+/** SPI_DIN7_NUM : HRO; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN7_NUM    0x00000003U
+#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
+#define SPI_DIN7_NUM_V  0x00000003U
+#define SPI_DIN7_NUM_S  14
+
+/** SPI_DOUT_MODE_REG register
+ *  SPI output delay mode configuration
+ */
+#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
+/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
+#define SPI_DOUT0_MODE_V  0x00000001U
+#define SPI_DOUT0_MODE_S  0
+/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
+#define SPI_DOUT1_MODE_V  0x00000001U
+#define SPI_DOUT1_MODE_S  1
+/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
+#define SPI_DOUT2_MODE_V  0x00000001U
+#define SPI_DOUT2_MODE_S  2
+/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
+#define SPI_DOUT3_MODE_V  0x00000001U
+#define SPI_DOUT3_MODE_S  3
+/** SPI_DOUT4_MODE : HRO; bitpos: [4]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT4_MODE    (BIT(4))
+#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
+#define SPI_DOUT4_MODE_V  0x00000001U
+#define SPI_DOUT4_MODE_S  4
+/** SPI_DOUT5_MODE : HRO; bitpos: [5]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT5_MODE    (BIT(5))
+#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
+#define SPI_DOUT5_MODE_V  0x00000001U
+#define SPI_DOUT5_MODE_S  5
+/** SPI_DOUT6_MODE : HRO; bitpos: [6]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT6_MODE    (BIT(6))
+#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
+#define SPI_DOUT6_MODE_V  0x00000001U
+#define SPI_DOUT6_MODE_S  6
+/** SPI_DOUT7_MODE : HRO; bitpos: [7]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT7_MODE    (BIT(7))
+#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
+#define SPI_DOUT7_MODE_V  0x00000001U
+#define SPI_DOUT7_MODE_S  7
+/** SPI_D_DQS_MODE : HRO; bitpos: [8]; default: 0;
+ *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+ *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_D_DQS_MODE    (BIT(8))
+#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
+#define SPI_D_DQS_MODE_V  0x00000001U
+#define SPI_D_DQS_MODE_S  8
+
+/** SPI_DMA_CONF_REG register
+ *  SPI DMA control register
+ */
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
+/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+ *  DMA TX FIFO is ready for sending data.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
+/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
+ *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+ *  0: DMA RX FIFO is ready for receiving data.
+ */
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
+#define SPI_DMA_INFIFO_FULL_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_S  1
+/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
+ *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+ */
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+ *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+ */
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+ *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+ */
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
+ *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+ *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+ *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+ *  spi_dma_seg_trans_done in seg-trans.
+ */
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
+#define SPI_RX_EOF_EN_V  0x00000001U
+#define SPI_RX_EOF_EN_S  21
+/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable SPI DMA controlled receive data mode.
+ */
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
+#define SPI_DMA_RX_ENA_V  0x00000001U
+#define SPI_DMA_RX_ENA_S  27
+/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to enable SPI DMA controlled send data mode.
+ */
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
+#define SPI_DMA_TX_ENA_V  0x00000001U
+#define SPI_DMA_TX_ENA_S  28
+/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
+ *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+ *  slave mode transfer.
+ */
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
+#define SPI_RX_AFIFO_RST_V  0x00000001U
+#define SPI_RX_AFIFO_RST_S  29
+/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
+ *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ *  controlled mode transfer and master mode transfer.
+ */
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
+#define SPI_BUF_AFIFO_RST_V  0x00000001U
+#define SPI_BUF_AFIFO_RST_S  30
+/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+ *  controlled mode transfer.
+ */
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
+#define SPI_DMA_AFIFO_RST_V  0x00000001U
+#define SPI_DMA_AFIFO_RST_S  31
+
+/** SPI_DMA_INT_ENA_REG register
+ *  SPI interrupt enable register
+ */
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
+#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
+#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
+#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
+#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
+#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
+#define SPI_APP2_INT_ENA_V  0x00000001U
+#define SPI_APP2_INT_ENA_S  19
+/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
+#define SPI_APP1_INT_ENA_V  0x00000001U
+#define SPI_APP1_INT_ENA_S  20
+
+/** SPI_DMA_INT_CLR_REG register
+ *  SPI interrupt clear register
+ */
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
+#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The clear bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
+#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
+#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
+#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
+#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  The clear bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
+#define SPI_APP2_INT_CLR_V  0x00000001U
+#define SPI_APP2_INT_CLR_S  19
+/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  The clear bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
+#define SPI_APP1_INT_CLR_V  0x00000001U
+#define SPI_APP1_INT_CLR_S  20
+
+/** SPI_DMA_INT_RAW_REG register
+ *  SPI interrupt raw register
+ */
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+ *  receive data.  0: Others.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ *  master mode and send out all 0 in slave mode.  0: Others.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+ *  is ended. 0: Others.
+ */
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+ *  is ended. 0: Others.
+ */
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
+#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
+#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
+#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
+#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ *  ended. 0: others.
+ */
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
+#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+ *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+ *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+ *  is not ended or not occurred.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+ *  is error in the DMA seg-conf-trans. 0: others.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+ *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+ *  bigger than 63. 0: Others.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ *  current SPI slave HD mode transmission is not supported. 0: Others.
+ */
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ *  write-full error when SPI inputs data in master mode. 0: Others.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+ *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+ */
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
+#define SPI_APP2_INT_RAW_V  0x00000001U
+#define SPI_APP2_INT_RAW_S  19
+/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+ */
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
+#define SPI_APP1_INT_RAW_V  0x00000001U
+#define SPI_APP1_INT_RAW_S  20
+
+/** SPI_DMA_INT_ST_REG register
+ *  SPI interrupt status register
+ */
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
+#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
+#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
+#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ST_S  4
+/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The status bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
+#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ST_S  5
+/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
+#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ST_S  6
+/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The status bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
+#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ST_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The status bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
+#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ST_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The status bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
+#define SPI_APP2_INT_ST_V  0x00000001U
+#define SPI_APP2_INT_ST_S  19
+/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The status bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
+#define SPI_APP1_INT_ST_V  0x00000001U
+#define SPI_APP1_INT_ST_S  20
+
+/** SPI_DMA_INT_SET_REG register
+ *  SPI interrupt software set register
+ */
+#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
+ *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
+ *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
+/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
+ *  The software set bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
+#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_SET_S  2
+/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
+ *  The software set bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
+#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_SET_S  3
+/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
+ *  The software set bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_SET    (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
+#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD7_INT_SET_S  4
+/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
+ *  The software set bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_SET    (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
+#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD8_INT_SET_S  5
+/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
+ *  The software set bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_SET    (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
+#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD9_INT_SET_S  6
+/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
+ *  The software set bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_SET    (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
+#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
+#define SPI_SLV_CMDA_INT_SET_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
+ *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
+#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
+ *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
+#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
+ *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
+#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
+ *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
+#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
+ *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
+#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_TRANS_DONE_INT_SET_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
+ *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
+/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
+ *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
+#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
+ *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
+ *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
+#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_SET_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
+ *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
+ *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
+ *  The software set bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_SET    (BIT(19))
+#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
+#define SPI_APP2_INT_SET_V  0x00000001U
+#define SPI_APP2_INT_SET_S  19
+/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
+ *  The software set bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_SET    (BIT(20))
+#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
+#define SPI_APP1_INT_SET_V  0x00000001U
+#define SPI_APP1_INT_SET_S  20
+
+/** SPI_W0_REG register
+ *  SPI CPU-controlled buffer0
+ */
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
+/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF0    0xFFFFFFFFU
+#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
+#define SPI_BUF0_V  0xFFFFFFFFU
+#define SPI_BUF0_S  0
+
+/** SPI_W1_REG register
+ *  SPI CPU-controlled buffer1
+ */
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
+/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF1    0xFFFFFFFFU
+#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
+#define SPI_BUF1_V  0xFFFFFFFFU
+#define SPI_BUF1_S  0
+
+/** SPI_W2_REG register
+ *  SPI CPU-controlled buffer2
+ */
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
+/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF2    0xFFFFFFFFU
+#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
+#define SPI_BUF2_V  0xFFFFFFFFU
+#define SPI_BUF2_S  0
+
+/** SPI_W3_REG register
+ *  SPI CPU-controlled buffer3
+ */
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
+/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF3    0xFFFFFFFFU
+#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
+#define SPI_BUF3_V  0xFFFFFFFFU
+#define SPI_BUF3_S  0
+
+/** SPI_W4_REG register
+ *  SPI CPU-controlled buffer4
+ */
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
+/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF4    0xFFFFFFFFU
+#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
+#define SPI_BUF4_V  0xFFFFFFFFU
+#define SPI_BUF4_S  0
+
+/** SPI_W5_REG register
+ *  SPI CPU-controlled buffer5
+ */
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
+/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF5    0xFFFFFFFFU
+#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
+#define SPI_BUF5_V  0xFFFFFFFFU
+#define SPI_BUF5_S  0
+
+/** SPI_W6_REG register
+ *  SPI CPU-controlled buffer6
+ */
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
+/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF6    0xFFFFFFFFU
+#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
+#define SPI_BUF6_V  0xFFFFFFFFU
+#define SPI_BUF6_S  0
+
+/** SPI_W7_REG register
+ *  SPI CPU-controlled buffer7
+ */
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
+/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF7    0xFFFFFFFFU
+#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
+#define SPI_BUF7_V  0xFFFFFFFFU
+#define SPI_BUF7_S  0
+
+/** SPI_W8_REG register
+ *  SPI CPU-controlled buffer8
+ */
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
+/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF8    0xFFFFFFFFU
+#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
+#define SPI_BUF8_V  0xFFFFFFFFU
+#define SPI_BUF8_S  0
+
+/** SPI_W9_REG register
+ *  SPI CPU-controlled buffer9
+ */
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
+/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF9    0xFFFFFFFFU
+#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
+#define SPI_BUF9_V  0xFFFFFFFFU
+#define SPI_BUF9_S  0
+
+/** SPI_W10_REG register
+ *  SPI CPU-controlled buffer10
+ */
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
+/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF10    0xFFFFFFFFU
+#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
+#define SPI_BUF10_V  0xFFFFFFFFU
+#define SPI_BUF10_S  0
+
+/** SPI_W11_REG register
+ *  SPI CPU-controlled buffer11
+ */
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
+/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF11    0xFFFFFFFFU
+#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
+#define SPI_BUF11_V  0xFFFFFFFFU
+#define SPI_BUF11_S  0
+
+/** SPI_W12_REG register
+ *  SPI CPU-controlled buffer12
+ */
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
+/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF12    0xFFFFFFFFU
+#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
+#define SPI_BUF12_V  0xFFFFFFFFU
+#define SPI_BUF12_S  0
+
+/** SPI_W13_REG register
+ *  SPI CPU-controlled buffer13
+ */
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
+/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF13    0xFFFFFFFFU
+#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
+#define SPI_BUF13_V  0xFFFFFFFFU
+#define SPI_BUF13_S  0
+
+/** SPI_W14_REG register
+ *  SPI CPU-controlled buffer14
+ */
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
+/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF14    0xFFFFFFFFU
+#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
+#define SPI_BUF14_V  0xFFFFFFFFU
+#define SPI_BUF14_S  0
+
+/** SPI_W15_REG register
+ *  SPI CPU-controlled buffer15
+ */
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
+/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF15    0xFFFFFFFFU
+#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
+#define SPI_BUF15_V  0xFFFFFFFFU
+#define SPI_BUF15_S  0
+
+/** SPI_SLAVE_REG register
+ *  SPI slave control register
+ */
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
+/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on. Can be configured in CONF state.
+ */
+#define SPI_CLK_MODE    0x00000003U
+#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
+#define SPI_CLK_MODE_V  0x00000003U
+#define SPI_CLK_MODE_S  0
+/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
+ *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+ *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+ */
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
+#define SPI_CLK_MODE_13_V  0x00000001U
+#define SPI_CLK_MODE_13_S  2
+/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
+ *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+ *  0: output data at tsck posedge
+ */
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
+#define SPI_RSCK_DATA_OUT_V  0x00000001U
+#define SPI_RSCK_DATA_OUT_S  3
+/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  DMA controlled mode(Rd_DMA). 0: others
+ */
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in DMA controlled mode(Wr_DMA). 0: others
+ */
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  CPU controlled mode(Rd_BUF). 0: others
+ */
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in CPU controlled mode(Wr_BUF). 0: others
+ */
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
+ *  The magic value of BM table in master DMA seg-trans.
+ */
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
+ *  Set SPI work mode. 1: slave mode 0: master mode.
+ */
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
+#define SPI_SLAVE_MODE_V  0x00000001U
+#define SPI_SLAVE_MODE_S  26
+/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
+ *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+ *  configured in CONF state.
+ */
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
+#define SPI_SOFT_RESET_V  0x00000001U
+#define SPI_SOFT_RESET_S  27
+/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
+ *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+ *  will start. 0: This is not seg-trans mode.
+ */
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
+#define SPI_USR_CONF_V  0x00000001U
+#define SPI_USR_CONF_S  28
+/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
+ *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+ *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+ *  transfer.
+ */
+#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
+
+/** SPI_SLAVE1_REG register
+ *  SPI slave control register 1
+ */
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
+/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
+ *  The transferred data bit length in SPI slave FD and HD mode.
+ */
+#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
+#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_S  0
+/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
+ *  In the slave mode it is the value of command.
+ */
+#define SPI_SLV_LAST_COMMAND    0x000000FFU
+#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
+#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
+#define SPI_SLV_LAST_COMMAND_S  18
+/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
+ *  In the slave mode it is the value of address.
+ */
+#define SPI_SLV_LAST_ADDR    0x0000003FU
+#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
+#define SPI_SLV_LAST_ADDR_V  0x0000003FU
+#define SPI_SLV_LAST_ADDR_S  26
+
+/** SPI_CLK_GATE_REG register
+ *  SPI module clock and register clock control
+ */
+#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
+/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
+#define SPI_CLK_EN_V  0x00000001U
+#define SPI_CLK_EN_S  0
+/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to power on the SPI module clock.
+ */
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
+#define SPI_MST_CLK_ACTIVE_V  0x00000001U
+#define SPI_MST_CLK_ACTIVE_S  1
+/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+ *  0: XTAL CLK.
+ */
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
+#define SPI_MST_CLK_SEL_V  0x00000001U
+#define SPI_MST_CLK_SEL_S  2
+
+/** SPI_DATE_REG register
+ *  Version control
+ */
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
+/** SPI_DATE : R/W; bitpos: [27:0]; default: 35656448;
+ *  SPI register version.
+ */
+#define SPI_DATE    0x0FFFFFFFU
+#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
+#define SPI_DATE_V  0x0FFFFFFFU
+#define SPI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/spi_struct.h b/components/soc/esp32h2/register/soc/spi_struct.h
new file mode 100644
index 00000000000..76644890a56
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/spi_struct.h
@@ -0,0 +1,1406 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: User-defined control registers */
+/** Type of cmd register
+ *  Command control register
+ */
+typedef union {
+    struct {
+        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+         */
+        uint32_t conf_bitlen:18;
+        uint32_t reserved_18:5;
+        /** update : WT; bitpos: [23]; default: 0;
+         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+         *  clock domain, which is only used in SPI master mode.
+         */
+        uint32_t update:1;
+        /** usr : R/W/SC; bitpos: [24]; default: 0;
+         *  User define command enable.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+         *  changed by CONF_buf.
+         */
+        uint32_t usr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} spi_cmd_reg_t;
+
+/** Type of addr register
+ *  Address value register
+ */
+typedef union {
+    struct {
+        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  Address to slave. Can be configured in CONF state.
+         */
+        uint32_t usr_addr_value:32;
+    };
+    uint32_t val;
+} spi_addr_reg_t;
+
+/** Type of user register
+ *  SPI USER control register
+ */
+typedef union {
+    struct {
+        /** doutdin : R/W; bitpos: [0]; default: 0;
+         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t doutdin:1;
+        uint32_t reserved_1:2;
+        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
+         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t qpi_mode:1;
+        /** opi_mode : HRO; bitpos: [4]; default: 0;
+         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t opi_mode:1;
+        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+         *  spi_ck_i. 1:tsck = !spi_ck_i.
+         */
+        uint32_t tsck_i_edge:1;
+        /** cs_hold : R/W; bitpos: [6]; default: 1;
+         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_hold:1;
+        /** cs_setup : R/W; bitpos: [7]; default: 1;
+         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_setup:1;
+        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+         *  !spi_ck_i. 1:rsck = spi_ck_i.
+         */
+        uint32_t rsck_i_edge:1;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+         *  be configured in CONF state.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:2;
+        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
+         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_dual:1;
+        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
+         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_quad:1;
+        /** fwrite_oct : HRO; bitpos: [14]; default: 0;
+         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_oct:1;
+        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
+         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+         *  not seg-trans mode. Can be configured in CONF state.
+         */
+        uint32_t usr_conf_nxt:1;
+        uint32_t reserved_16:1;
+        /** sio : R/W; bitpos: [17]; default: 0;
+         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+         */
+        uint32_t sio:1;
+        uint32_t reserved_18:6;
+        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
+         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+         *  disable. Can be configured in CONF state.
+         */
+        uint32_t usr_miso_highpart:1;
+        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
+         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+         *  0: disable.  Can be configured in CONF state.
+         */
+        uint32_t usr_mosi_highpart:1;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+         *  CONF state.
+         */
+        uint32_t usr_dummy_idle:1;
+        /** usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  This bit enable the write-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_mosi:1;
+        /** usr_miso : R/W; bitpos: [28]; default: 0;
+         *  This bit enable the read-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_miso:1;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_dummy:1;
+        /** usr_addr : R/W; bitpos: [30]; default: 0;
+         *  This bit enable the address phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_addr:1;
+        /** usr_command : R/W; bitpos: [31]; default: 1;
+         *  This bit enable the command phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_command:1;
+    };
+    uint32_t val;
+} spi_user_reg_t;
+
+/** Type of user1 register
+ *  SPI USER control register 1
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
+         *  The length in spi_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1). Can be configured in CONF state.
+         */
+        uint32_t usr_dummy_cyclelen:8;
+        uint32_t reserved_8:8;
+        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
+         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+         *  GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_wfull_err_end_en:1;
+        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
+         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+         *  bit. Can be configured in CONF state.
+         */
+        uint32_t cs_setup_time:5;
+        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
+         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs_hold_time:5;
+        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_addr_bitlen:5;
+    };
+    uint32_t val;
+} spi_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI USER control register 2
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command. Can be configured in CONF state.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:11;
+        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
+         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+         *  is valid in GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_rempty_err_end_en:1;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi_user2_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of ctrl register
+ *  SPI control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** dummy_out : R/W; bitpos: [3]; default: 0;
+         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+         *  the FSPI bus signals are output. Can be configured in CONF state.
+         */
+        uint32_t dummy_out:1;
+        uint32_t reserved_4:1;
+        /** faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_dual:1;
+        /** faddr_quad : R/W; bitpos: [6]; default: 0;
+         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_quad:1;
+        /** faddr_oct : HRO; bitpos: [7]; default: 0;
+         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_oct:1;
+        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
+         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_dual:1;
+        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : HRO; bitpos: [10]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_oct:1;
+        uint32_t reserved_11:3;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_dual:1;
+        /** fread_quad : R/W; bitpos: [15]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_quad:1;
+        /** fread_oct : HRO; bitpos: [16]; default: 0;
+         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_oct:1;
+        uint32_t reserved_17:1;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t d_pol:1;
+        /** hold_pol : R/W; bitpos: [20]; default: 1;
+         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+         *  configured in CONF state.
+         */
+        uint32_t hold_pol:1;
+        /** wp_pol : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t wp_pol:1;
+        uint32_t reserved_22:1;
+        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
+         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+         *  state.
+         */
+        uint32_t rd_bit_order:2;
+        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
+         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+         *  configured in CONF state.
+         */
+        uint32_t wr_bit_order:2;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_ctrl_reg_t;
+
+/** Type of ms_dlen register
+ *  SPI data bit length control register
+ */
+typedef union {
+    struct {
+        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  The value of these bits is the configured SPI transmission data bit length in
+         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+         *  the configured bit length in slave mode DMA RX controlled transfer. The register
+         *  value shall be (bit_num-1). Can be configured in CONF state.
+         */
+        uint32_t ms_data_bitlen:18;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_ms_dlen_reg_t;
+
+/** Type of misc register
+ *  SPI misc register
+ */
+typedef union {
+    struct {
+        /** cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs0_dis:1;
+        /** cs1_dis : R/W; bitpos: [1]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs1_dis:1;
+        /** cs2_dis : R/W; bitpos: [2]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs2_dis:1;
+        /** cs3_dis : R/W; bitpos: [3]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs3_dis:1;
+        /** cs4_dis : R/W; bitpos: [4]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs4_dis:1;
+        /** cs5_dis : R/W; bitpos: [5]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs5_dis:1;
+        /** ck_dis : R/W; bitpos: [6]; default: 0;
+         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+         */
+        uint32_t ck_dis:1;
+        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
+         *  In the master mode the bits are the polarity of spi cs line, the value is
+         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+         */
+        uint32_t master_cs_pol:6;
+        uint32_t reserved_13:3;
+        /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0;
+         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+         */
+        uint32_t clk_data_dtr_en:1;
+        /** data_dtr_en : HRO; bitpos: [17]; default: 0;
+         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+         *  Can be configured in CONF state.
+         */
+        uint32_t data_dtr_en:1;
+        /** addr_dtr_en : HRO; bitpos: [18]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t addr_dtr_en:1;
+        /** cmd_dtr_en : HRO; bitpos: [19]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cmd_dtr_en:1;
+        uint32_t reserved_20:3;
+        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
+         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+         *  CONF state.
+         */
+        uint32_t slave_cs_pol:1;
+        /** dqs_idle_edge : HRO; bitpos: [24]; default: 0;
+         *  The default value of spi_dqs. Can be configured in CONF state.
+         */
+        uint32_t dqs_idle_edge:1;
+        uint32_t reserved_25:4;
+        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
+         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+         *  configured in CONF state.
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
+         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+         */
+        uint32_t cs_keep_active:1;
+        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
+         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+         *  spi quad input swap disable. Can be configured in CONF state.
+         */
+        uint32_t quad_din_pin_swap:1;
+    };
+    uint32_t val;
+} spi_misc_reg_t;
+
+/** Type of dma_conf register
+ *  SPI DMA control register
+ */
+typedef union {
+    struct {
+        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
+         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+         *  DMA TX FIFO is ready for sending data.
+         */
+        uint32_t dma_outfifo_empty:1;
+        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
+         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+         *  0: DMA RX FIFO is ready for receiving data.
+         */
+        uint32_t dma_infifo_full:1;
+        uint32_t reserved_2:16;
+        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
+         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+         */
+        uint32_t dma_slv_seg_trans_en:1;
+        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
+         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_rx_seg_trans_clr_en:1;
+        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
+         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_tx_seg_trans_clr_en:1;
+        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
+         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+         *  spi_dma_seg_trans_done in seg-trans.
+         */
+        uint32_t rx_eof_en:1;
+        uint32_t reserved_22:5;
+        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable SPI DMA controlled receive data mode.
+         */
+        uint32_t dma_rx_ena:1;
+        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable SPI DMA controlled send data mode.
+         */
+        uint32_t dma_tx_ena:1;
+        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
+         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+         *  slave mode transfer.
+         */
+        uint32_t rx_afifo_rst:1;
+        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
+         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+         *  controlled mode transfer and master mode transfer.
+         */
+        uint32_t buf_afifo_rst:1;
+        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+         *  controlled mode transfer.
+         */
+        uint32_t dma_afifo_rst:1;
+    };
+    uint32_t val;
+} spi_dma_conf_reg_t;
+
+/** Type of slave register
+ *  SPI slave control register
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on. Can be configured in CONF state.
+         */
+        uint32_t clk_mode:2;
+        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
+         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+         */
+        uint32_t clk_mode_13:1;
+        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
+         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+         *  0: output data at tsck posedge
+         */
+        uint32_t rsck_data_out:1;
+        uint32_t reserved_4:4;
+        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  DMA controlled mode(Rd_DMA). 0: others
+         */
+        uint32_t slv_rddma_bitlen_en:1;
+        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in DMA controlled mode(Wr_DMA). 0: others
+         */
+        uint32_t slv_wrdma_bitlen_en:1;
+        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  CPU controlled mode(Rd_BUF). 0: others
+         */
+        uint32_t slv_rdbuf_bitlen_en:1;
+        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in CPU controlled mode(Wr_BUF). 0: others
+         */
+        uint32_t slv_wrbuf_bitlen_en:1;
+        uint32_t reserved_12:10;
+        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
+         *  The magic value of BM table in master DMA seg-trans.
+         */
+        uint32_t dma_seg_magic_value:4;
+        /** slave_mode : R/W; bitpos: [26]; default: 0;
+         *  Set SPI work mode. 1: slave mode 0: master mode.
+         */
+        uint32_t slave_mode:1;
+        /** soft_reset : WT; bitpos: [27]; default: 0;
+         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+         *  configured in CONF state.
+         */
+        uint32_t soft_reset:1;
+        /** usr_conf : R/W; bitpos: [28]; default: 0;
+         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+         *  will start. 0: This is not seg-trans mode.
+         */
+        uint32_t usr_conf:1;
+        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
+         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+         *  transfer.
+         */
+        uint32_t mst_fd_wait_dma_tx_data:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_slave_reg_t;
+
+/** Type of slave1 register
+ *  SPI slave control register 1
+ */
+typedef union {
+    struct {
+        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
+         *  The transferred data bit length in SPI slave FD and HD mode.
+         */
+        uint32_t slv_data_bitlen:18;
+        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
+         *  In the slave mode it is the value of command.
+         */
+        uint32_t slv_last_command:8;
+        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
+         *  In the slave mode it is the value of address.
+         */
+        uint32_t slv_last_addr:6;
+    };
+    uint32_t val;
+} spi_slave1_reg_t;
+
+
+/** Group: Clock control registers */
+/** Type of clock register
+ *  SPI clock control register
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
+         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+         *  0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_l:6;
+        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
+         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+         *  must be 0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_h:6;
+        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
+         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+         */
+        uint32_t clkcnt_n:6;
+        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
+         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+         */
+        uint32_t clkdiv_pre:4;
+        uint32_t reserved_22:9;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+         *  clock. Can be configured in CONF state.
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_clock_reg_t;
+
+/** Type of clk_gate register
+ *  SPI module clock and register clock control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to power on the SPI module clock.
+         */
+        uint32_t mst_clk_active:1;
+        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+         *  0: XTAL CLK.
+         */
+        uint32_t mst_clk_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_clk_gate_reg_t;
+
+
+/** Group: Timing registers */
+/** Type of din_mode register
+ *  SPI input delay mode configuration
+ */
+typedef union {
+    struct {
+        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din0_mode:2;
+        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din1_mode:2;
+        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din2_mode:2;
+        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din3_mode:2;
+        /** din4_mode : HRO; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din4_mode:2;
+        /** din5_mode : HRO; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the
+         *  (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
+         *  3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  falling edge cycle. Can be configured in CONF state.
+         */
+        uint32_t din5_mode:2;
+        /** din6_mode : HRO; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the
+         *  (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
+         *  3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  falling edge cycle. Can be configured in CONF state.
+         */
+        uint32_t din6_mode:2;
+        /** din7_mode : HRO; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the
+         *  (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle,
+         *  3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst
+         *  falling edge cycle. Can be configured in CONF state.
+         */
+        uint32_t din7_mode:2;
+        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
+         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+         *  state.
+         */
+        uint32_t timing_hclk_active:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} spi_din_mode_reg_t;
+
+/** Type of din_num register
+ *  SPI input delay number configuration
+ */
+typedef union {
+    struct {
+        /** din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din0_num:2;
+        /** din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din1_num:2;
+        /** din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din2_num:2;
+        /** din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din3_num:2;
+        /** din4_num : HRO; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din4_num:2;
+        /** din5_num : HRO; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din5_num:2;
+        /** din6_num : HRO; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din6_num:2;
+        /** din7_num : HRO; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din7_num:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} spi_din_num_reg_t;
+
+/** Type of dout_mode register
+ *  SPI output delay mode configuration
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout0_mode:1;
+        /** dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout1_mode:1;
+        /** dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout2_mode:1;
+        /** dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout3_mode:1;
+        /** dout4_mode : HRO; bitpos: [4]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout4_mode:1;
+        /** dout5_mode : HRO; bitpos: [5]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout5_mode:1;
+        /** dout6_mode : HRO; bitpos: [6]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout6_mode:1;
+        /** dout7_mode : HRO; bitpos: [7]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout7_mode:1;
+        /** d_dqs_mode : HRO; bitpos: [8]; default: 0;
+         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t d_dqs_mode:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_dout_mode_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of dma_int_ena register
+ *  SPI interrupt enable register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_ena:1;
+        /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_ena:1;
+        /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_ena:1;
+        /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_ena:1;
+        /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_ena:1;
+        /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The enable bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_ena:1;
+        /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_ena:1;
+        /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_ena:1;
+        /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_ena:1;
+        /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_ena:1;
+        /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_ena:1;
+        /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_ena:1;
+        /** trans_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_ena:1;
+        /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_ena:1;
+        /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_ena:1;
+        /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_ena:1;
+        /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_ena:1;
+        /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_ena:1;
+        /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_ena:1;
+        /** app2_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The enable bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_ena:1;
+        /** app1_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The enable bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_ena:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_ena_reg_t;
+
+/** Type of dma_int_clr register
+ *  SPI interrupt clear register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_clr:1;
+        /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_clr:1;
+        /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0;
+         *  The clear bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_clr:1;
+        /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0;
+         *  The clear bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_clr:1;
+        /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_clr:1;
+        /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0;
+         *  The clear bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_clr:1;
+        /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0;
+         *  The clear bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_clr:1;
+        /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0;
+         *  The clear bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_clr:1;
+        /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0;
+         *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_clr:1;
+        /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0;
+         *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_clr:1;
+        /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0;
+         *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_clr:1;
+        /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0;
+         *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_clr:1;
+        /** trans_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_clr:1;
+        /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_clr:1;
+        /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0;
+         *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_clr:1;
+        /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_clr:1;
+        /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_clr:1;
+        /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0;
+         *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_clr:1;
+        /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0;
+         *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_clr:1;
+        /** app2_int_clr : WT; bitpos: [19]; default: 0;
+         *  The clear bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_clr:1;
+        /** app1_int_clr : WT; bitpos: [20]; default: 0;
+         *  The clear bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_clr:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_clr_reg_t;
+
+/** Type of dma_int_raw register
+ *  SPI interrupt raw register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+         *  receive data.  0: Others.
+         */
+        uint32_t dma_infifo_full_err_int_raw:1;
+        /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+         *  master mode and send out all 0 in slave mode.  0: Others.
+         */
+        uint32_t dma_outfifo_empty_err_int_raw:1;
+        /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_ex_qpi_int_raw:1;
+        /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_en_qpi_int_raw:1;
+        /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd7_int_raw:1;
+        /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd8_int_raw:1;
+        /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd9_int_raw:1;
+        /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmda_int_raw:1;
+        /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_dma_done_int_raw:1;
+        /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_dma_done_int_raw:1;
+        /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_buf_done_int_raw:1;
+        /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_buf_done_int_raw:1;
+        /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+         *  ended. 0: others.
+         */
+        uint32_t trans_done_int_raw:1;
+        /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+         *  is not ended or not occurred.
+         */
+        uint32_t dma_seg_trans_done_int_raw:1;
+        /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+         *  is error in the DMA seg-conf-trans. 0: others.
+         */
+        uint32_t seg_magic_err_int_raw:1;
+        /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+         *  bigger than 63. 0: Others.
+         */
+        uint32_t slv_buf_addr_err_int_raw:1;
+        /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+         *  current SPI slave HD mode transmission is not supported. 0: Others.
+         */
+        uint32_t slv_cmd_err_int_raw:1;
+        /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+         *  write-full error when SPI inputs data in master mode. 0: Others.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_raw:1;
+        /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_raw:1;
+        /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app2_int_raw:1;
+        /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app1_int_raw:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_raw_reg_t;
+
+/** Type of dma_int_st register
+ *  SPI interrupt status register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0;
+         *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_st:1;
+        /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0;
+         *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_st:1;
+        /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0;
+         *  The status bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_st:1;
+        /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0;
+         *  The status bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_st:1;
+        /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_st:1;
+        /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0;
+         *  The status bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_st:1;
+        /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0;
+         *  The status bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_st:1;
+        /** slv_cmda_int_st : RO; bitpos: [7]; default: 0;
+         *  The status bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_st:1;
+        /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0;
+         *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_st:1;
+        /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0;
+         *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_st:1;
+        /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0;
+         *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_st:1;
+        /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0;
+         *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_st:1;
+        /** trans_done_int_st : RO; bitpos: [12]; default: 0;
+         *  The status bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_st:1;
+        /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0;
+         *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_st:1;
+        /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0;
+         *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_st:1;
+        /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0;
+         *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_st:1;
+        /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0;
+         *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_st:1;
+        /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0;
+         *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_st:1;
+        /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0;
+         *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_st:1;
+        /** app2_int_st : RO; bitpos: [19]; default: 0;
+         *  The status bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_st:1;
+        /** app1_int_st : RO; bitpos: [20]; default: 0;
+         *  The status bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_st:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_st_reg_t;
+
+/** Type of dma_int_set register
+ *  SPI interrupt software set register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0;
+         *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+         */
+        uint32_t dma_infifo_full_err_int_set:1;
+        /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0;
+         *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+         */
+        uint32_t dma_outfifo_empty_err_int_set:1;
+        /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0;
+         *  The software set bit for SPI slave Ex_QPI interrupt.
+         */
+        uint32_t slv_ex_qpi_int_set:1;
+        /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0;
+         *  The software set bit for SPI slave En_QPI interrupt.
+         */
+        uint32_t slv_en_qpi_int_set:1;
+        /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0;
+         *  The software set bit for SPI slave CMD7 interrupt.
+         */
+        uint32_t slv_cmd7_int_set:1;
+        /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0;
+         *  The software set bit for SPI slave CMD8 interrupt.
+         */
+        uint32_t slv_cmd8_int_set:1;
+        /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0;
+         *  The software set bit for SPI slave CMD9 interrupt.
+         */
+        uint32_t slv_cmd9_int_set:1;
+        /** slv_cmda_int_set : WT; bitpos: [7]; default: 0;
+         *  The software set bit for SPI slave CMDA interrupt.
+         */
+        uint32_t slv_cmda_int_set:1;
+        /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0;
+         *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_dma_done_int_set:1;
+        /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0;
+         *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_dma_done_int_set:1;
+        /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0;
+         *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_rd_buf_done_int_set:1;
+        /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0;
+         *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+         */
+        uint32_t slv_wr_buf_done_int_set:1;
+        /** trans_done_int_set : WT; bitpos: [12]; default: 0;
+         *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+         */
+        uint32_t trans_done_int_set:1;
+        /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0;
+         *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+         */
+        uint32_t dma_seg_trans_done_int_set:1;
+        /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0;
+         *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+         */
+        uint32_t seg_magic_err_int_set:1;
+        /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0;
+         *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+         */
+        uint32_t slv_buf_addr_err_int_set:1;
+        /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0;
+         *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+         */
+        uint32_t slv_cmd_err_int_set:1;
+        /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0;
+         *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int_set:1;
+        /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0;
+         *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int_set:1;
+        /** app2_int_set : WT; bitpos: [19]; default: 0;
+         *  The software set bit for SPI_APP2_INT interrupt.
+         */
+        uint32_t app2_int_set:1;
+        /** app1_int_set : WT; bitpos: [20]; default: 0;
+         *  The software set bit for SPI_APP1_INT interrupt.
+         */
+        uint32_t app1_int_set:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_set_reg_t;
+
+
+/** Group: CPU-controlled data buffer */
+/** Type of w0 register
+ *  SPI CPU-controlled buffer0
+ */
+typedef union {
+    struct {
+        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf0:32;
+    };
+    uint32_t val;
+} spi_wn_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35656448;
+         *  SPI register version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_date_reg_t;
+
+
+typedef struct {
+    volatile spi_cmd_reg_t cmd;
+    volatile spi_addr_reg_t addr;
+    volatile spi_ctrl_reg_t ctrl;
+    volatile spi_clock_reg_t clock;
+    volatile spi_user_reg_t user;
+    volatile spi_user1_reg_t user1;
+    volatile spi_user2_reg_t user2;
+    volatile spi_ms_dlen_reg_t ms_dlen;
+    volatile spi_misc_reg_t misc;
+    volatile spi_din_mode_reg_t din_mode;
+    volatile spi_din_num_reg_t din_num;
+    volatile spi_dout_mode_reg_t dout_mode;
+    volatile spi_dma_conf_reg_t dma_conf;
+    volatile spi_dma_int_ena_reg_t dma_int_ena;
+    volatile spi_dma_int_clr_reg_t dma_int_clr;
+    volatile spi_dma_int_raw_reg_t dma_int_raw;
+    volatile spi_dma_int_st_reg_t dma_int_st;
+    volatile spi_dma_int_set_reg_t dma_int_set;
+    uint32_t reserved_048[20];
+    volatile spi_wn_reg_t data_buf[16];
+    uint32_t reserved_0d8[2];
+    volatile spi_slave_reg_t slave;
+    volatile spi_slave1_reg_t slave1;
+    volatile spi_clk_gate_reg_t clk_gate;
+    uint32_t reserved_0ec;
+    volatile spi_date_reg_t date;
+} spi_dev_t;
+
+extern spi_dev_t GPSPI2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/systimer_reg.h b/components/soc/esp32h2/register/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/systimer_reg.h
rename to components/soc/esp32h2/register/soc/systimer_reg.h
diff --git a/components/soc/esp32h2/include/soc/systimer_struct.h b/components/soc/esp32h2/register/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/systimer_struct.h
rename to components/soc/esp32h2/register/soc/systimer_struct.h
diff --git a/components/soc/esp32h2/include/soc/tee_reg.h b/components/soc/esp32h2/register/soc/tee_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/tee_reg.h
rename to components/soc/esp32h2/register/soc/tee_reg.h
diff --git a/components/soc/esp32h2/include/soc/tee_struct.h b/components/soc/esp32h2/register/soc/tee_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/tee_struct.h
rename to components/soc/esp32h2/register/soc/tee_struct.h
diff --git a/components/soc/esp32h2/include/soc/timer_group_reg.h b/components/soc/esp32h2/register/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/timer_group_reg.h
rename to components/soc/esp32h2/register/soc/timer_group_reg.h
diff --git a/components/soc/esp32h2/include/soc/timer_group_struct.h b/components/soc/esp32h2/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/timer_group_struct.h
rename to components/soc/esp32h2/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32h2/register/soc/trace_reg.h b/components/soc/esp32h2/register/soc/trace_reg.h
new file mode 100644
index 00000000000..b363fbd1f8e
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/trace_reg.h
@@ -0,0 +1,219 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** TRACE_MEM_START_ADDR_REG register
+ *  mem start addr
+ */
+#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0)
+/** TRACE_MEM_STAET_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of trace memory
+ */
+#define TRACE_MEM_STAET_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_STAET_ADDR_M  (TRACE_MEM_STAET_ADDR_V << TRACE_MEM_STAET_ADDR_S)
+#define TRACE_MEM_STAET_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_STAET_ADDR_S  0
+
+/** TRACE_MEM_END_ADDR_REG register
+ *  mem end addr
+ */
+#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4)
+/** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The end address of trace memory
+ */
+#define TRACE_MEM_END_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_M  (TRACE_MEM_END_ADDR_V << TRACE_MEM_END_ADDR_S)
+#define TRACE_MEM_END_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_END_ADDR_S  0
+
+/** TRACE_MEM_CURRENT_ADDR_REG register
+ *  mem current addr
+ */
+#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8)
+/** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  current_mem_addr,indicate that next writing addr
+ */
+#define TRACE_MEM_CURRENT_ADDR    0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_M  (TRACE_MEM_CURRENT_ADDR_V << TRACE_MEM_CURRENT_ADDR_S)
+#define TRACE_MEM_CURRENT_ADDR_V  0xFFFFFFFFU
+#define TRACE_MEM_CURRENT_ADDR_S  0
+
+/** TRACE_MEM_ADDR_UPDATE_REG register
+ *  mem addr update
+ */
+#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc)
+/** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
+ *  when set this reg, the current_mem_addr will update to start_addr
+ */
+#define TRACE_MEM_CURRENT_ADDR_UPDATE    (BIT(0))
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_M  (TRACE_MEM_CURRENT_ADDR_UPDATE_V << TRACE_MEM_CURRENT_ADDR_UPDATE_S)
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_V  0x00000001U
+#define TRACE_MEM_CURRENT_ADDR_UPDATE_S  0
+
+/** TRACE_FIFO_STATUS_REG register
+ *  fifo status register
+ */
+#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10)
+/** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  1 indicate that fifo is empty
+ */
+#define TRACE_FIFO_EMPTY    (BIT(0))
+#define TRACE_FIFO_EMPTY_M  (TRACE_FIFO_EMPTY_V << TRACE_FIFO_EMPTY_S)
+#define TRACE_FIFO_EMPTY_V  0x00000001U
+#define TRACE_FIFO_EMPTY_S  0
+/** TRACE_WORK_STATUS : RO; bitpos: [1]; default: 0;
+ *  mem_full interrupt status
+ */
+#define TRACE_WORK_STATUS    (BIT(1))
+#define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
+#define TRACE_WORK_STATUS_V  0x00000001U
+#define TRACE_WORK_STATUS_S  1
+
+/** TRACE_INTR_ENA_REG register
+ *  interrupt enable register
+ */
+#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14)
+/** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set 1 enable fifo_overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_ENA    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_M  (TRACE_FIFO_OVERFLOW_INTR_ENA_V << TRACE_FIFO_OVERFLOW_INTR_ENA_S)
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_ENA_S  0
+/** TRACE_MEM_FULL_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set 1 enable mem_full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_ENA    (BIT(1))
+#define TRACE_MEM_FULL_INTR_ENA_M  (TRACE_MEM_FULL_INTR_ENA_V << TRACE_MEM_FULL_INTR_ENA_S)
+#define TRACE_MEM_FULL_INTR_ENA_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_ENA_S  1
+
+/** TRACE_INTR_RAW_REG register
+ *  interrupt status register
+ */
+#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18)
+/** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0;
+ *  fifo_overflow interrupt status
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_RAW    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_M  (TRACE_FIFO_OVERFLOW_INTR_RAW_V << TRACE_FIFO_OVERFLOW_INTR_RAW_S)
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_RAW_S  0
+/** TRACE_MEM_FULL_INTR_RAW : RO; bitpos: [1]; default: 0;
+ *  mem_full interrupt status
+ */
+#define TRACE_MEM_FULL_INTR_RAW    (BIT(1))
+#define TRACE_MEM_FULL_INTR_RAW_M  (TRACE_MEM_FULL_INTR_RAW_V << TRACE_MEM_FULL_INTR_RAW_S)
+#define TRACE_MEM_FULL_INTR_RAW_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_RAW_S  1
+
+/** TRACE_INTR_CLR_REG register
+ *  interrupt clear register
+ */
+#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c)
+/** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0;
+ *  Set 1 clr fifo overflow interrupt
+ */
+#define TRACE_FIFO_OVERFLOW_INTR_CLR    (BIT(0))
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_M  (TRACE_FIFO_OVERFLOW_INTR_CLR_V << TRACE_FIFO_OVERFLOW_INTR_CLR_S)
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_V  0x00000001U
+#define TRACE_FIFO_OVERFLOW_INTR_CLR_S  0
+/** TRACE_MEM_FULL_INTR_CLR : WT; bitpos: [1]; default: 0;
+ *  Set 1 clr mem full interrupt
+ */
+#define TRACE_MEM_FULL_INTR_CLR    (BIT(1))
+#define TRACE_MEM_FULL_INTR_CLR_M  (TRACE_MEM_FULL_INTR_CLR_V << TRACE_MEM_FULL_INTR_CLR_S)
+#define TRACE_MEM_FULL_INTR_CLR_V  0x00000001U
+#define TRACE_MEM_FULL_INTR_CLR_S  1
+
+/** TRACE_TRIGGER_REG register
+ *  trigger register
+ */
+#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20)
+/** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0;
+ *  [0] set 1 start trace.
+ */
+#define TRACE_TRIGGER_ON    (BIT(0))
+#define TRACE_TRIGGER_ON_M  (TRACE_TRIGGER_ON_V << TRACE_TRIGGER_ON_S)
+#define TRACE_TRIGGER_ON_V  0x00000001U
+#define TRACE_TRIGGER_ON_S  0
+/** TRACE_TRIGGER_OFF : WT; bitpos: [1]; default: 0;
+ *  set 1 stop trace.
+ */
+#define TRACE_TRIGGER_OFF    (BIT(1))
+#define TRACE_TRIGGER_OFF_M  (TRACE_TRIGGER_OFF_V << TRACE_TRIGGER_OFF_S)
+#define TRACE_TRIGGER_OFF_V  0x00000001U
+#define TRACE_TRIGGER_OFF_S  1
+/** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1;
+ *  if this reg is 1, trace will loop write trace_mem.  If is 0, when mem_current_addr
+ *  at mem_end_addr, it will stop at the mem_end_addr
+ */
+#define TRACE_MEM_LOOP    (BIT(2))
+#define TRACE_MEM_LOOP_M  (TRACE_MEM_LOOP_V << TRACE_MEM_LOOP_S)
+#define TRACE_MEM_LOOP_V  0x00000001U
+#define TRACE_MEM_LOOP_S  2
+/** TRACE_RESTART_ENA : R/W; bitpos: [3]; default: 1;
+ *  enable encoder auto-restart, when lost package, the encoder will end, if enable
+ *  auto-restart, when fifo empty, encoder will restart and send a sync package.
+ */
+#define TRACE_RESTART_ENA    (BIT(3))
+#define TRACE_RESTART_ENA_M  (TRACE_RESTART_ENA_V << TRACE_RESTART_ENA_S)
+#define TRACE_RESTART_ENA_V  0x00000001U
+#define TRACE_RESTART_ENA_S  3
+
+/** TRACE_RESYNC_PROLONGED_REG register
+ *  resync configuration register
+ */
+#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x24)
+/** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128;
+ *  count number, when count to this value, send a sync package
+ */
+#define TRACE_RESYNC_PROLONGED    0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_M  (TRACE_RESYNC_PROLONGED_V << TRACE_RESYNC_PROLONGED_S)
+#define TRACE_RESYNC_PROLONGED_V  0x00FFFFFFU
+#define TRACE_RESYNC_PROLONGED_S  0
+/** TRACE_RESYNC_MODE : R/W; bitpos: [24]; default: 0;
+ *  resyc mode sel: 0: default, cycle count   1: package num count
+ */
+#define TRACE_RESYNC_MODE    (BIT(24))
+#define TRACE_RESYNC_MODE_M  (TRACE_RESYNC_MODE_V << TRACE_RESYNC_MODE_S)
+#define TRACE_RESYNC_MODE_V  0x00000001U
+#define TRACE_RESYNC_MODE_S  24
+
+/** TRACE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x28)
+/** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define TRACE_CLK_EN    (BIT(0))
+#define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)
+#define TRACE_CLK_EN_V  0x00000001U
+#define TRACE_CLK_EN_S  0
+
+/** TRACE_DATE_REG register
+ *  Version control register
+ */
+#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc)
+/** TRACE_DATE : R/W; bitpos: [27:0]; default: 35663920;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define TRACE_DATE    0x0FFFFFFFU
+#define TRACE_DATE_M  (TRACE_DATE_V << TRACE_DATE_S)
+#define TRACE_DATE_V  0x0FFFFFFFU
+#define TRACE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/trace_struct.h b/components/soc/esp32h2/register/soc/trace_struct.h
new file mode 100644
index 00000000000..365ac45dd06
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/trace_struct.h
@@ -0,0 +1,249 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Trace memory configuration registers */
+/** Type of mem_start_addr register
+ *  mem start addr
+ */
+typedef union {
+    struct {
+        /** mem_staet_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of trace memory
+         */
+        uint32_t mem_staet_addr:32;
+    };
+    uint32_t val;
+} trace_mem_start_addr_reg_t;
+
+/** Type of mem_end_addr register
+ *  mem end addr
+ */
+typedef union {
+    struct {
+        /** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of trace memory
+         */
+        uint32_t mem_end_addr:32;
+    };
+    uint32_t val;
+} trace_mem_end_addr_reg_t;
+
+/** Type of mem_current_addr register
+ *  mem current addr
+ */
+typedef union {
+    struct {
+        /** mem_current_addr : RO; bitpos: [31:0]; default: 0;
+         *  current_mem_addr,indicate that next writing addr
+         */
+        uint32_t mem_current_addr:32;
+    };
+    uint32_t val;
+} trace_mem_current_addr_reg_t;
+
+/** Type of mem_addr_update register
+ *  mem addr update
+ */
+typedef union {
+    struct {
+        /** mem_current_addr_update : WT; bitpos: [0]; default: 0;
+         *  when set this reg, the current_mem_addr will update to start_addr
+         */
+        uint32_t mem_current_addr_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_mem_addr_update_reg_t;
+
+
+/** Group: Trace fifo status register */
+/** Type of fifo_status register
+ *  fifo status register
+ */
+typedef union {
+    struct {
+        /** fifo_empty : RO; bitpos: [0]; default: 1;
+         *  1 indicate that fifo is empty
+         */
+        uint32_t fifo_empty:1;
+        /** work_status : RO; bitpos: [1]; default: 0;
+         *  mem_full interrupt status
+         */
+        uint32_t work_status:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_fifo_status_reg_t;
+
+
+/** Group: Trace interrupt configuration registers */
+/** Type of intr_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Set 1 enable fifo_overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_ena:1;
+        /** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Set 1 enable mem_full interrupt
+         */
+        uint32_t mem_full_intr_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_ena_reg_t;
+
+/** Type of intr_raw register
+ *  interrupt status register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
+         *  fifo_overflow interrupt status
+         */
+        uint32_t fifo_overflow_intr_raw:1;
+        /** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
+         *  mem_full interrupt status
+         */
+        uint32_t mem_full_intr_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_raw_reg_t;
+
+/** Type of intr_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
+         *  Set 1 clr fifo overflow interrupt
+         */
+        uint32_t fifo_overflow_intr_clr:1;
+        /** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
+         *  Set 1 clr mem full interrupt
+         */
+        uint32_t mem_full_intr_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} trace_intr_clr_reg_t;
+
+
+/** Group: Trace configuration register */
+/** Type of trigger register
+ *  trigger register
+ */
+typedef union {
+    struct {
+        /** trigger_on : WT; bitpos: [0]; default: 0;
+         *  [0] set 1 start trace.
+         */
+        uint32_t trigger_on:1;
+        /** trigger_off : WT; bitpos: [1]; default: 0;
+         *  set 1 stop trace.
+         */
+        uint32_t trigger_off:1;
+        /** mem_loop : R/W; bitpos: [2]; default: 1;
+         *  if this reg is 1, trace will loop write trace_mem.  If is 0, when mem_current_addr
+         *  at mem_end_addr, it will stop at the mem_end_addr
+         */
+        uint32_t mem_loop:1;
+        /** restart_ena : R/W; bitpos: [3]; default: 1;
+         *  enable encoder auto-restart, when lost package, the encoder will end, if enable
+         *  auto-restart, when fifo empty, encoder will restart and send a sync package.
+         */
+        uint32_t restart_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} trace_trigger_reg_t;
+
+/** Type of resync_prolonged register
+ *  resync configuration register
+ */
+typedef union {
+    struct {
+        /** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
+         *  count number, when count to this value, send a sync package
+         */
+        uint32_t resync_prolonged:24;
+        /** resync_mode : R/W; bitpos: [24]; default: 0;
+         *  resyc mode sel: 0: default, cycle count   1: package num count
+         */
+        uint32_t resync_mode:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} trace_resync_prolonged_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  The bit is used to enable clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} trace_clock_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35663920;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} trace_date_reg_t;
+
+
+typedef struct {
+    volatile trace_mem_start_addr_reg_t mem_start_addr;
+    volatile trace_mem_end_addr_reg_t mem_end_addr;
+    volatile trace_mem_current_addr_reg_t mem_current_addr;
+    volatile trace_mem_addr_update_reg_t mem_addr_update;
+    volatile trace_fifo_status_reg_t fifo_status;
+    volatile trace_intr_ena_reg_t intr_ena;
+    volatile trace_intr_raw_reg_t intr_raw;
+    volatile trace_intr_clr_reg_t intr_clr;
+    volatile trace_trigger_reg_t trigger;
+    volatile trace_resync_prolonged_reg_t resync_prolonged;
+    volatile trace_clock_gate_reg_t clock_gate;
+    uint32_t reserved_02c[244];
+    volatile trace_date_reg_t date;
+} trace_dev_t;
+
+extern trace_dev_t TRACE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/twai_reg.h b/components/soc/esp32h2/register/soc/twai_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/twai_reg.h
rename to components/soc/esp32h2/register/soc/twai_reg.h
diff --git a/components/soc/esp32h2/include/soc/twai_struct.h b/components/soc/esp32h2/register/soc/twai_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/twai_struct.h
rename to components/soc/esp32h2/register/soc/twai_struct.h
diff --git a/components/soc/esp32h2/register/soc/uart_reg.h b/components/soc/esp32h2/register/soc/uart_reg.h
new file mode 100644
index 00000000000..a8c550dfbb1
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/uart_reg.h
@@ -0,0 +1,1546 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UART_FIFO_REG(i) register
+ *  FIFO data register
+ */
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define UART_RXFIFO_RD_BYTE    0x000000FFU
+#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define UART_RXFIFO_RD_BYTE_S  0
+
+/** UART_INT_RAW_REG(i) register
+ *  Raw interrupt status
+ */
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
+#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
+#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_PARITY_ERR_INT_RAW_S  2
+/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
+#define UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_FRM_ERR_INT_RAW_S  3
+/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
+#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
+#define UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define UART_DSR_CHG_INT_RAW_S  5
+/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
+#define UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define UART_CTS_CHG_INT_RAW_S  6
+/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
+#define UART_BRK_DET_INT_RAW_V  0x00000001U
+#define UART_BRK_DET_INT_RAW_S  7
+/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
+#define UART_SW_XON_INT_RAW_V  0x00000001U
+#define UART_SW_XON_INT_RAW_S  9
+/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
+#define UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define UART_SW_XOFF_INT_RAW_S  10
+/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
+#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define UART_GLITCH_DET_INT_RAW_S  11
+/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
+#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
+#define UART_TX_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_DONE_INT_RAW_S  14
+/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  This interrupt raw bit turns to high level when detects a clash between transmitter
+ *  and receiver in rs485 mode.
+ */
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
+#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
+#define UART_RS485_CLASH_INT_RAW_S  17
+/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
+#define UART_WAKEUP_INT_RAW_V  0x00000001U
+#define UART_WAKEUP_INT_RAW_S  19
+
+/** UART_INT_ST_REG(i) register
+ *  Masked interrupt status
+ */
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
+/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
+#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ST_S  0
+/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
+#define UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_PARITY_ERR_INT_ST_S  2
+/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
+#define UART_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_FRM_ERR_INT_ST_S  3
+/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
+#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
+#define UART_DSR_CHG_INT_ST_V  0x00000001U
+#define UART_DSR_CHG_INT_ST_S  5
+/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
+#define UART_CTS_CHG_INT_ST_V  0x00000001U
+#define UART_CTS_CHG_INT_ST_S  6
+/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
+#define UART_BRK_DET_INT_ST_V  0x00000001U
+#define UART_BRK_DET_INT_ST_S  7
+/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
+#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
+#define UART_SW_XON_INT_ST_V  0x00000001U
+#define UART_SW_XON_INT_ST_S  9
+/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
+#define UART_SW_XOFF_INT_ST_V  0x00000001U
+#define UART_SW_XOFF_INT_ST_S  10
+/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
+#define UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define UART_GLITCH_DET_INT_ST_S  11
+/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
+#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
+#define UART_TX_DONE_INT_ST_V  0x00000001U
+#define UART_TX_DONE_INT_ST_S  14
+/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ *  set to 1.
+ */
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+ *  to 1.
+ */
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
+#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
+ *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+ */
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
+#define UART_RS485_CLASH_INT_ST_V  0x00000001U
+#define UART_RS485_CLASH_INT_ST_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
+#define UART_WAKEUP_INT_ST_V  0x00000001U
+#define UART_WAKEUP_INT_ST_S  19
+
+/** UART_INT_ENA_REG(i) register
+ *  Interrupt enable bits
+ */
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
+/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
+#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
+#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_PARITY_ERR_INT_ENA_S  2
+/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
+#define UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_FRM_ERR_INT_ENA_S  3
+/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
+#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
+#define UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define UART_DSR_CHG_INT_ENA_S  5
+/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
+#define UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define UART_CTS_CHG_INT_ENA_S  6
+/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
+#define UART_BRK_DET_INT_ENA_V  0x00000001U
+#define UART_BRK_DET_INT_ENA_S  7
+/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
+#define UART_SW_XON_INT_ENA_V  0x00000001U
+#define UART_SW_XON_INT_ENA_S  9
+/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
+#define UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define UART_SW_XOFF_INT_ENA_S  10
+/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
+#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define UART_GLITCH_DET_INT_ENA_S  11
+/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
+#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
+#define UART_TX_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_DONE_INT_ENA_S  14
+/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  This is the enable bit for rs485_clash_int_st register.
+ */
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
+#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
+#define UART_RS485_CLASH_INT_ENA_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
+#define UART_WAKEUP_INT_ENA_V  0x00000001U
+#define UART_WAKEUP_INT_ENA_S  19
+
+/** UART_INT_CLR_REG(i) register
+ *  Interrupt clear bits
+ */
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
+/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
+#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
+#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_PARITY_ERR_INT_CLR_S  2
+/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
+#define UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_FRM_ERR_INT_CLR_S  3
+/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
+#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
+#define UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define UART_DSR_CHG_INT_CLR_S  5
+/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
+#define UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define UART_CTS_CHG_INT_CLR_S  6
+/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
+#define UART_BRK_DET_INT_CLR_V  0x00000001U
+#define UART_BRK_DET_INT_CLR_S  7
+/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
+#define UART_SW_XON_INT_CLR_V  0x00000001U
+#define UART_SW_XON_INT_CLR_S  9
+/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
+#define UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define UART_SW_XOFF_INT_CLR_S  10
+/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
+#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define UART_GLITCH_DET_INT_CLR_S  11
+/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
+#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
+#define UART_TX_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_DONE_INT_CLR_S  14
+/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+ */
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+ */
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the rs485_clash_int_raw interrupt.
+ */
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
+#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
+#define UART_RS485_CLASH_INT_CLR_S  17
+/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
+#define UART_WAKEUP_INT_CLR_V  0x00000001U
+#define UART_WAKEUP_INT_CLR_S  19
+
+/** UART_CLKDIV_SYNC_REG(i) register
+ *  Clock divider configuration
+ */
+#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
+/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_CLKDIV    0x00000FFFU
+#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
+#define UART_CLKDIV_V  0x00000FFFU
+#define UART_CLKDIV_S  0
+/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define UART_CLKDIV_FRAG    0x0000000FU
+#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
+#define UART_CLKDIV_FRAG_V  0x0000000FU
+#define UART_CLKDIV_FRAG_S  20
+
+/** UART_RX_FILT_REG(i) register
+ *  Rx Filter configuration
+ */
+#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
+/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define UART_GLITCH_FILT    0x000000FFU
+#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
+#define UART_GLITCH_FILT_V  0x000000FFU
+#define UART_GLITCH_FILT_S  0
+/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
+#define UART_GLITCH_FILT_EN_V  0x00000001U
+#define UART_GLITCH_FILT_EN_S  8
+
+/** UART_STATUS_REG(i) register
+ *  UART status register
+ */
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
+/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define UART_RXFIFO_CNT    0x000000FFU
+#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
+#define UART_RXFIFO_CNT_V  0x000000FFU
+#define UART_RXFIFO_CNT_S  0
+/** UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
+#define UART_DSRN_V  0x00000001U
+#define UART_DSRN_S  13
+/** UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
+#define UART_CTSN_V  0x00000001U
+#define UART_CTSN_S  14
+/** UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
+#define UART_RXD_V  0x00000001U
+#define UART_RXD_S  15
+/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define UART_TXFIFO_CNT    0x000000FFU
+#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
+#define UART_TXFIFO_CNT_V  0x000000FFU
+#define UART_TXFIFO_CNT_S  16
+/** UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
+#define UART_DTRN_V  0x00000001U
+#define UART_DTRN_S  29
+/** UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
+#define UART_RTSN_V  0x00000001U
+#define UART_RTSN_S  30
+/** UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
+#define UART_TXD_V  0x00000001U
+#define UART_TXD_S  31
+
+/** UART_CONF0_SYNC_REG(i) register
+ *  a
+ */
+#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
+/** UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
+#define UART_PARITY_V  0x00000001U
+#define UART_PARITY_S  0
+/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
+#define UART_PARITY_EN_V  0x00000001U
+#define UART_PARITY_EN_S  1
+/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define UART_BIT_NUM    0x00000003U
+#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
+#define UART_BIT_NUM_V  0x00000003U
+#define UART_BIT_NUM_S  2
+/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define UART_STOP_BIT_NUM    0x00000003U
+#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
+#define UART_STOP_BIT_NUM_V  0x00000003U
+#define UART_STOP_BIT_NUM_S  4
+/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define UART_TXD_BRK    (BIT(6))
+#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
+#define UART_TXD_BRK_V  0x00000001U
+#define UART_TXD_BRK_S  6
+/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable IrDA loopback mode.
+ */
+#define UART_IRDA_DPLX    (BIT(7))
+#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
+#define UART_IRDA_DPLX_V  0x00000001U
+#define UART_IRDA_DPLX_S  7
+/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the start enable bit for IrDA transmitter.
+ */
+#define UART_IRDA_TX_EN    (BIT(8))
+#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
+#define UART_IRDA_TX_EN_V  0x00000001U
+#define UART_IRDA_TX_EN_S  8
+/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
+ *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+ *  transmitter's 11th bit to 0.
+ */
+#define UART_IRDA_WCTL    (BIT(9))
+#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
+#define UART_IRDA_WCTL_V  0x00000001U
+#define UART_IRDA_WCTL_S  9
+/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to invert the level of  IrDA transmitter.
+ */
+#define UART_IRDA_TX_INV    (BIT(10))
+#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
+#define UART_IRDA_TX_INV_V  0x00000001U
+#define UART_IRDA_TX_INV_S  10
+/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to invert the level of IrDA receiver.
+ */
+#define UART_IRDA_RX_INV    (BIT(11))
+#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
+#define UART_IRDA_RX_INV_V  0x00000001U
+#define UART_IRDA_RX_INV_S  11
+/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define UART_LOOPBACK    (BIT(12))
+#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
+#define UART_LOOPBACK_V  0x00000001U
+#define UART_LOOPBACK_S  12
+/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define UART_TX_FLOW_EN    (BIT(13))
+#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
+#define UART_TX_FLOW_EN_V  0x00000001U
+#define UART_TX_FLOW_EN_S  13
+/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable IrDA protocol.
+ */
+#define UART_IRDA_EN    (BIT(14))
+#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
+#define UART_IRDA_EN_V  0x00000001U
+#define UART_IRDA_EN_S  14
+/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define UART_RXD_INV    (BIT(15))
+#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
+#define UART_RXD_INV_V  0x00000001U
+#define UART_RXD_INV_S  15
+/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define UART_TXD_INV    (BIT(16))
+#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
+#define UART_TXD_INV_V  0x00000001U
+#define UART_TXD_INV_S  16
+/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define UART_DIS_RX_DAT_OVF    (BIT(17))
+#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
+#define UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define UART_DIS_RX_DAT_OVF_S  17
+/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define UART_ERR_WR_MASK    (BIT(18))
+#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
+#define UART_ERR_WR_MASK_V  0x00000001U
+#define UART_ERR_WR_MASK_S  18
+/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for detecting baudrate.
+ */
+#define UART_AUTOBAUD_EN    (BIT(19))
+#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
+#define UART_AUTOBAUD_EN_V  0x00000001U
+#define UART_AUTOBAUD_EN_S  19
+/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  UART memory clock gate enable signal.
+ */
+#define UART_MEM_CLK_EN    (BIT(20))
+#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
+#define UART_MEM_CLK_EN_V  0x00000001U
+#define UART_MEM_CLK_EN_S  20
+/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_RTS    (BIT(21))
+#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
+#define UART_SW_RTS_V  0x00000001U
+#define UART_SW_RTS_S  21
+/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define UART_RXFIFO_RST    (BIT(22))
+#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
+#define UART_RXFIFO_RST_V  0x00000001U
+#define UART_RXFIFO_RST_S  22
+/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define UART_TXFIFO_RST    (BIT(23))
+#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
+#define UART_TXFIFO_RST_V  0x00000001U
+#define UART_TXFIFO_RST_S  23
+
+/** UART_CONF1_REG(i) register
+ *  Configuration register 1
+ */
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
+/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define UART_RXFIFO_FULL_THRHD    0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
+#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
+#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_S  8
+/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define UART_CTS_INV    (BIT(16))
+#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
+#define UART_CTS_INV_V  0x00000001U
+#define UART_CTS_INV_S  16
+/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define UART_DSR_INV    (BIT(17))
+#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
+#define UART_DSR_INV_V  0x00000001U
+#define UART_DSR_INV_S  17
+/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define UART_RTS_INV    (BIT(18))
+#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
+#define UART_RTS_INV_V  0x00000001U
+#define UART_RTS_INV_S  18
+/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define UART_DTR_INV    (BIT(19))
+#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
+#define UART_DTR_INV_V  0x00000001U
+#define UART_DTR_INV_S  19
+/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_DTR    (BIT(20))
+#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
+#define UART_SW_DTR_V  0x00000001U
+#define UART_SW_DTR_S  20
+/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define UART_CLK_EN    (BIT(21))
+#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
+#define UART_CLK_EN_V  0x00000001U
+#define UART_CLK_EN_S  21
+
+/** UART_HWFC_CONF_SYNC_REG(i) register
+ *  Hardware flow-control configuration
+ */
+#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
+/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define UART_RX_FLOW_THRHD    0x000000FFU
+#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
+#define UART_RX_FLOW_THRHD_V  0x000000FFU
+#define UART_RX_FLOW_THRHD_S  0
+/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define UART_RX_FLOW_EN    (BIT(8))
+#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
+#define UART_RX_FLOW_EN_V  0x00000001U
+#define UART_RX_FLOW_EN_S  8
+
+/** UART_SLEEP_CONF0_REG(i) register
+ *  UART sleep configure register 0
+ */
+#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
+/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define UART_WK_CHAR1    0x000000FFU
+#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
+#define UART_WK_CHAR1_V  0x000000FFU
+#define UART_WK_CHAR1_S  0
+/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define UART_WK_CHAR2    0x000000FFU
+#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
+#define UART_WK_CHAR2_V  0x000000FFU
+#define UART_WK_CHAR2_S  8
+/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define UART_WK_CHAR3    0x000000FFU
+#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
+#define UART_WK_CHAR3_V  0x000000FFU
+#define UART_WK_CHAR3_S  16
+/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define UART_WK_CHAR4    0x000000FFU
+#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
+#define UART_WK_CHAR4_V  0x000000FFU
+#define UART_WK_CHAR4_S  24
+
+/** UART_SLEEP_CONF1_REG(i) register
+ *  UART sleep configure register 1
+ */
+#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
+/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define UART_WK_CHAR0    0x000000FFU
+#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
+#define UART_WK_CHAR0_V  0x000000FFU
+#define UART_WK_CHAR0_S  0
+
+/** UART_SLEEP_CONF2_REG(i) register
+ *  UART sleep configure register 2
+ */
+#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
+/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define UART_ACTIVE_THRESHOLD    0x000003FFU
+#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
+#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define UART_ACTIVE_THRESHOLD_S  0
+/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define UART_RX_WAKE_UP_THRHD    0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
+#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_S  10
+/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define UART_WK_CHAR_NUM    0x00000007U
+#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
+#define UART_WK_CHAR_NUM_V  0x00000007U
+#define UART_WK_CHAR_NUM_S  18
+/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define UART_WK_CHAR_MASK    0x0000001FU
+#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
+#define UART_WK_CHAR_MASK_V  0x0000001FU
+#define UART_WK_CHAR_MASK_S  21
+/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define UART_WK_MODE_SEL    0x00000003U
+#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
+#define UART_WK_MODE_SEL_V  0x00000003U
+#define UART_WK_MODE_SEL_S  26
+
+/** UART_SWFC_CONF0_SYNC_REG(i) register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
+/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define UART_XON_CHAR    0x000000FFU
+#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
+#define UART_XON_CHAR_V  0x000000FFU
+#define UART_XON_CHAR_S  0
+/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define UART_XOFF_CHAR    0x000000FFU
+#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
+#define UART_XOFF_CHAR_V  0x000000FFU
+#define UART_XOFF_CHAR_S  8
+/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
+#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define UART_XON_XOFF_STILL_SEND_S  16
+/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define UART_SW_FLOW_CON_EN    (BIT(17))
+#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
+#define UART_SW_FLOW_CON_EN_V  0x00000001U
+#define UART_SW_FLOW_CON_EN_S  17
+/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define UART_XONOFF_DEL    (BIT(18))
+#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
+#define UART_XONOFF_DEL_V  0x00000001U
+#define UART_XONOFF_DEL_S  18
+/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define UART_FORCE_XON    (BIT(19))
+#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
+#define UART_FORCE_XON_V  0x00000001U
+#define UART_FORCE_XON_S  19
+/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define UART_FORCE_XOFF    (BIT(20))
+#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
+#define UART_FORCE_XOFF_V  0x00000001U
+#define UART_FORCE_XOFF_S  20
+/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XON    (BIT(21))
+#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
+#define UART_SEND_XON_V  0x00000001U
+#define UART_SEND_XON_S  21
+/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XOFF    (BIT(22))
+#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
+#define UART_SEND_XOFF_V  0x00000001U
+#define UART_SEND_XOFF_S  22
+
+/** UART_SWFC_CONF1_REG(i) register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
+/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define UART_XON_THRESHOLD    0x000000FFU
+#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
+#define UART_XON_THRESHOLD_V  0x000000FFU
+#define UART_XON_THRESHOLD_S  0
+/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define UART_XOFF_THRESHOLD    0x000000FFU
+#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
+#define UART_XOFF_THRESHOLD_V  0x000000FFU
+#define UART_XOFF_THRESHOLD_S  8
+
+/** UART_TXBRK_CONF_SYNC_REG(i) register
+ *  Tx Break character configuration
+ */
+#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
+/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define UART_TX_BRK_NUM    0x000000FFU
+#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
+#define UART_TX_BRK_NUM_V  0x000000FFU
+#define UART_TX_BRK_NUM_S  0
+
+/** UART_IDLE_CONF_SYNC_REG(i) register
+ *  Frame-end idle configuration
+ */
+#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
+/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define UART_RX_IDLE_THRHD    0x000003FFU
+#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
+#define UART_RX_IDLE_THRHD_V  0x000003FFU
+#define UART_RX_IDLE_THRHD_S  0
+/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define UART_TX_IDLE_NUM    0x000003FFU
+#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
+#define UART_TX_IDLE_NUM_V  0x000003FFU
+#define UART_TX_IDLE_NUM_S  10
+
+/** UART_RS485_CONF_SYNC_REG(i) register
+ *  RS485 mode configuration
+ */
+#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
+/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to choose the rs485 mode.
+ */
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
+#define UART_RS485_EN_V  0x00000001U
+#define UART_RS485_EN_S  0
+/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
+#define UART_DL0_EN_V  0x00000001U
+#define UART_DL0_EN_S  1
+/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
+#define UART_DL1_EN_V  0x00000001U
+#define UART_DL1_EN_S  2
+/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable receiver could receive data when the transmitter is
+ *  transmitting data in rs485 mode.
+ */
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
+#define UART_RS485TX_RX_EN_V  0x00000001U
+#define UART_RS485TX_RX_EN_S  3
+/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+ */
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
+#define UART_RS485RXBY_TX_EN_V  0x00000001U
+#define UART_RS485RXBY_TX_EN_S  4
+/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
+ *  This register is used to delay the receiver's internal data signal.
+ */
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
+#define UART_RS485_RX_DLY_NUM_V  0x00000001U
+#define UART_RS485_RX_DLY_NUM_S  5
+/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
+ *  This register is used to delay the transmitter's internal data signal.
+ */
+#define UART_RS485_TX_DLY_NUM    0x0000000FU
+#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
+#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
+#define UART_RS485_TX_DLY_NUM_S  6
+
+/** UART_AT_CMD_PRECNT_SYNC_REG(i) register
+ *  Pre-sequence timing configuration
+ */
+#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
+/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define UART_PRE_IDLE_NUM    0x0000FFFFU
+#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
+#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define UART_PRE_IDLE_NUM_S  0
+
+/** UART_AT_CMD_POSTCNT_SYNC_REG(i) register
+ *  Post-sequence timing configuration
+ */
+#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
+/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define UART_POST_IDLE_NUM    0x0000FFFFU
+#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
+#define UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define UART_POST_IDLE_NUM_S  0
+
+/** UART_AT_CMD_GAPTOUT_SYNC_REG(i) register
+ *  Timeout configuration
+ */
+#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
+/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define UART_RX_GAP_TOUT    0x0000FFFFU
+#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
+#define UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define UART_RX_GAP_TOUT_S  0
+
+/** UART_AT_CMD_CHAR_SYNC_REG(i) register
+ *  AT escape sequence detection configuration
+ */
+#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
+/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define UART_AT_CMD_CHAR    0x000000FFU
+#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
+#define UART_AT_CMD_CHAR_V  0x000000FFU
+#define UART_AT_CMD_CHAR_S  0
+/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define UART_CHAR_NUM    0x000000FFU
+#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
+#define UART_CHAR_NUM_V  0x000000FFU
+#define UART_CHAR_NUM_S  8
+
+/** UART_MEM_CONF_REG(i) register
+ *  UART memory power configuration
+ */
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
+/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define UART_MEM_FORCE_PD    (BIT(25))
+#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
+#define UART_MEM_FORCE_PD_V  0x00000001U
+#define UART_MEM_FORCE_PD_S  25
+/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define UART_MEM_FORCE_PU    (BIT(26))
+#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
+#define UART_MEM_FORCE_PU_V  0x00000001U
+#define UART_MEM_FORCE_PU_S  26
+
+/** UART_TOUT_CONF_SYNC_REG(i) register
+ *  UART threshold and allocation configuration
+ */
+#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
+/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define UART_RX_TOUT_EN    (BIT(0))
+#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
+#define UART_RX_TOUT_EN_V  0x00000001U
+#define UART_RX_TOUT_EN_S  0
+/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
+#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define UART_RX_TOUT_FLOW_DIS_S  1
+/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define UART_RX_TOUT_THRHD    0x000003FFU
+#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
+#define UART_RX_TOUT_THRHD_V  0x000003FFU
+#define UART_RX_TOUT_THRHD_S  2
+
+/** UART_MEM_TX_STATUS_REG(i) register
+ *  Tx-SRAM write and read offset address.
+ */
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
+/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_WADDR    0x000000FFU
+#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
+#define UART_TX_SRAM_WADDR_V  0x000000FFU
+#define UART_TX_SRAM_WADDR_S  0
+/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_RADDR    0x000000FFU
+#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
+#define UART_TX_SRAM_RADDR_V  0x000000FFU
+#define UART_TX_SRAM_RADDR_S  9
+
+/** UART_MEM_RX_STATUS_REG(i) register
+ *  Rx-SRAM write and read offset address.
+ */
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
+/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define UART_RX_SRAM_RADDR    0x000000FFU
+#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
+#define UART_RX_SRAM_RADDR_V  0x000000FFU
+#define UART_RX_SRAM_RADDR_S  0
+/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define UART_RX_SRAM_WADDR    0x000000FFU
+#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
+#define UART_RX_SRAM_WADDR_V  0x000000FFU
+#define UART_RX_SRAM_WADDR_S  9
+
+/** UART_FSM_STATUS_REG(i) register
+ *  UART transmit and receive status.
+ */
+#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
+/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define UART_ST_URX_OUT    0x0000000FU
+#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
+#define UART_ST_URX_OUT_V  0x0000000FU
+#define UART_ST_URX_OUT_S  0
+/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define UART_ST_UTX_OUT    0x0000000FU
+#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
+#define UART_ST_UTX_OUT_V  0x0000000FU
+#define UART_ST_UTX_OUT_S  4
+
+/** UART_POSPULSE_REG(i) register
+ *  Autobaud high pulse register
+ */
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
+/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two positive edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_POSEDGE_MIN_CNT    0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
+#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_S  0
+
+/** UART_NEGPULSE_REG(i) register
+ *  Autobaud low pulse register
+ */
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
+/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two negative edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
+#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+/** UART_LOWPULSE_REG(i) register
+ *  Autobaud minimum low pulse duration register
+ */
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
+/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the value of the minimum duration time of the low level pulse.
+ *  It is used in baud rate-detect process.
+ */
+#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
+#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+/** UART_HIGHPULSE_REG(i) register
+ *  Autobaud minimum high pulse duration register
+ */
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
+/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores  the value of the maximum duration time for the high level
+ *  pulse. It is used in baud rate-detect process.
+ */
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
+#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+/** UART_RXD_CNT_REG(i) register
+ *  Autobaud edge change count register
+ */
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
+/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the count of rxd edge change. It is used in baud rate-detect
+ *  process.
+ */
+#define UART_RXD_EDGE_CNT    0x000003FFU
+#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
+#define UART_RXD_EDGE_CNT_V  0x000003FFU
+#define UART_RXD_EDGE_CNT_S  0
+
+/** UART_DATE_REG(i) register
+ *  UART Version register
+ */
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
+/** UART_DATE : R/W; bitpos: [31:0]; default: 35680848;
+ *  This is the version register.
+ */
+#define UART_DATE    0xFFFFFFFFU
+#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
+#define UART_DATE_V  0xFFFFFFFFU
+#define UART_DATE_S  0
+
+/** UART_AFIFO_STATUS_REG(i) register
+ *  UART AFIFO Status
+ */
+#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
+/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_FULL    (BIT(0))
+#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
+#define UART_TX_AFIFO_FULL_V  0x00000001U
+#define UART_TX_AFIFO_FULL_S  0
+/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_EMPTY    (BIT(1))
+#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
+#define UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define UART_TX_AFIFO_EMPTY_S  1
+/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_FULL    (BIT(2))
+#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
+#define UART_RX_AFIFO_FULL_V  0x00000001U
+#define UART_RX_AFIFO_FULL_S  2
+/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_EMPTY    (BIT(3))
+#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
+#define UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define UART_RX_AFIFO_EMPTY_S  3
+
+/** UART_REG_UPDATE_REG(i) register
+ *  UART Registers Configuration Update register
+ */
+#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
+/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define UART_REG_UPDATE    (BIT(0))
+#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
+#define UART_REG_UPDATE_V  0x00000001U
+#define UART_REG_UPDATE_S  0
+
+/** UART_ID_REG(i) register
+ *  UART ID register
+ */
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
+/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define UART_ID    0xFFFFFFFFU
+#define UART_ID_M  (UART_ID_V << UART_ID_S)
+#define UART_ID_V  0xFFFFFFFFU
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/register/soc/uart_struct.h b/components/soc/esp32h2/register/soc/uart_struct.h
new file mode 100644
index 00000000000..d267b1869b3
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/uart_struct.h
@@ -0,0 +1,1243 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [31:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:32;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err:1;
+        /** frm_err : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done:1;
+        /** rs485_parity_err : R/WTC/SS; bitpos: [15]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_parity_err:1;
+        /** rs485_frm_err : R/WTC/SS; bitpos: [16]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_frm_err:1;
+        /** rs485_clash : R/WTC/SS; bitpos: [17]; default: 0;
+         *  This interrupt raw bit turns to high level when detects a clash between transmitter
+         *  and receiver in rs485 mode.
+         */
+        uint32_t rs485_clash:1;
+        /** at_cmd_char_det : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err:1;
+        /** frm_err : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done:1;
+        /** rs485_parity_err : RO; bitpos: [15]; default: 0;
+         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+         *  set to 1.
+         */
+        uint32_t rs485_parity_err:1;
+        /** rs485_frm_err : RO; bitpos: [16]; default: 0;
+         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+         *  to 1.
+         */
+        uint32_t rs485_frm_err:1;
+        /** rs485_clash : RO; bitpos: [17]; default: 0;
+         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+         */
+        uint32_t rs485_clash:1;
+        /** at_cmd_char_det : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full: R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty: R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err: R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err:1;
+        /** frm_err: R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf: R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg: R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg: R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det: R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout: R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon: R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff: R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det: R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done: R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done: R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done: R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done:1;
+        /** rs485_parity_err: R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_parity_err:1;
+        /** rs485_frm_err: R/W; bitpos: [16]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_frm_err:1;
+        /** rs485_clash: R/W; bitpos: [17]; default: 0;
+         *  This is the enable bit for rs485_clash_int_st register.
+         */
+        uint32_t rs485_clash:1;
+        /** at_cmd_char_det: R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup: R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full: WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full:1;
+        /** txfifo_empty: WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty:1;
+        /** parity_err: WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err:1;
+        /** frm_err: WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err:1;
+        /** rxfifo_ovf: WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf:1;
+        /** dsr_chg: WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg:1;
+        /** cts_chg: WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg:1;
+        /** brk_det: WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det:1;
+        /** rxfifo_tout: WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout:1;
+        /** sw_xon: WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon:1;
+        /** sw_xoff: WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff:1;
+        /** glitch_det: WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det:1;
+        /** tx_brk_done: WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done:1;
+        /** tx_brk_idle_done: WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done:1;
+        /** tx_done: WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done:1;
+        /** rs485_parity_err: WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+         */
+        uint32_t rs485_parity_err:1;
+        /** rs485_frm_err: WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+         */
+        uint32_t rs485_frm_err:1;
+        /** rs485_clash: WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the rs485_clash_int_raw interrupt.
+         */
+        uint32_t rs485_clash:1;
+        /** at_cmd_char_det: WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det:1;
+        /** wakeup: WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv_int : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv_int:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  a
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable IrDA loopback mode.
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
+         *  This is the start enable bit for IrDA transmitter.
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [9]; default: 0;
+         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+         *  transmitter's 11th bit to 0.
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the level of  IrDA transmitter.
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to invert the level of IrDA receiver.
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable IrDA protocol.
+         */
+        uint32_t irda_en:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for detecting baudrate.
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 1;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:8;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:8;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:8;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:8;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_character : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_character:8;
+        /** xoff_character : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_character:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to choose the rs485 mode.
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable receiver could receive data when the transmitter is
+         *  transmitting data in rs485 mode.
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  This register is used to delay the receiver's internal data signal.
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  This register is used to delay the transmitter's internal data signal.
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_sync_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:8;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:8;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:8;
+        uint32_t reserved_8:1;
+        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:8;
+        uint32_t reserved_8:1;
+        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** data : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t data:8;
+        /** at_char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t at_char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two positive edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two negative edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the value of the minimum duration time of the low level pulse.
+         *  It is used in baud rate-detect process.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores  the value of the maximum duration time for the high level
+         *  pulse. It is used in baud rate-detect process.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the count of rxd edge change. It is used in baud rate-detect
+         *  process.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 35656288;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct uart_dev_s {
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_sync_reg_t conf0_sync;
+    volatile uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile uart_sleep_conf0_reg_t sleep_conf0;
+    volatile uart_sleep_conf1_reg_t sleep_conf1;
+    volatile uart_sleep_conf2_reg_t sleep_conf2;
+    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;
+    volatile uart_negpulse_reg_t negpulse;
+    volatile uart_lowpulse_reg_t lowpulse;
+    volatile uart_highpulse_reg_t highpulse;
+    volatile uart_rxd_cnt_reg_t rxd_cnt;
+    uint32_t reserved_088;
+    volatile uart_date_reg_t date;
+    volatile uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile uart_reg_update_reg_t reg_update;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/uhci_reg.h b/components/soc/esp32h2/register/soc/uhci_reg.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/uhci_reg.h
rename to components/soc/esp32h2/register/soc/uhci_reg.h
diff --git a/components/soc/esp32h2/include/soc/uhci_struct.h b/components/soc/esp32h2/register/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/uhci_struct.h
rename to components/soc/esp32h2/register/soc/uhci_struct.h
diff --git a/components/soc/esp32h2/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32h2/register/soc/usb_serial_jtag_reg.h
new file mode 100644
index 00000000000..e188eea9111
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,1188 @@
+/**
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
+ *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
+ *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
+ *  how many data is received, then read data from UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
+ *  USB Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFH_S  3
+/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFL_S  5
+/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+ *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+ *  through GPIO Matrix.
+ */
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
+ *  USB RCV value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
+ *  USB D+ rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_SERIAL_JTAG_CHIP_RST_REG register
+ *  CDC-ACM chip reset control.
+ */
+#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
+/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
+ *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_RTS    (BIT(0))
+#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
+#define USB_SERIAL_JTAG_RTS_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_S  0
+/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
+ *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_DTR    (BIT(1))
+#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
+#define USB_SERIAL_JTAG_DTR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_S  1
+/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable chip reset from usb serial channel to reset chip.
+ */
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
+ *  W0 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
+/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
+ *  W1 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
+/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
+/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_S  16
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
+ *  W0 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
+/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
+ *  W1 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
+/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
+/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
+
+/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
+ *  Configuration registers' value update
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
+/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this register would update the value of configure registers from APB
+ *  clock domain to 48MHz clock domain.
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
+
+/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
+ *  Serial AFIFO configure register
+ */
+#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
+ *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
+
+/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
+ *  USB Bus reset status register
+ */
+#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
+/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
+ *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+ *  reset is released.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  Date register
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34640416;
+ *  register version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32h2/register/soc/usb_serial_jtag_struct.h
similarity index 100%
rename from components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
rename to components/soc/esp32h2/register/soc/usb_serial_jtag_struct.h
diff --git a/components/soc/esp32h2/register/soc/xts_aes_reg.h b/components/soc/esp32h2/register/soc/xts_aes_reg.h
new file mode 100644
index 00000000000..921701bc742
--- /dev/null
+++ b/components/soc/esp32h2/register/soc/xts_aes_reg.h
@@ -0,0 +1,129 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define XTS_AES_PLAIN_MEM(i)          (REG_SPI_MEM_BASE(i) + 0x300)
+/* XTS_AES_PLAIN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This field is only used to generate include file in c case. This field is useles
+s. Please do not use this field..*/
+#define XTS_AES_PLAIN    0xFFFFFFFF
+#define XTS_AES_PLAIN_M  ((XTS_AES_PLAIN_V)<<(XTS_AES_PLAIN_S))
+#define XTS_AES_PLAIN_V  0xFFFFFFFF
+#define XTS_AES_PLAIN_S  0
+
+#define XTS_AES_LINESIZE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x340)
+/* XTS_AES_LINESIZE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the line-size parameter which will be used in manual encryption
+ calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes,
+ 1: 32-bytes, 2: 64-bytes, 3:reserved..*/
+#define XTS_AES_LINESIZE    0x00000003
+#define XTS_AES_LINESIZE_M  ((XTS_AES_LINESIZE_V)<<(XTS_AES_LINESIZE_S))
+#define XTS_AES_LINESIZE_V  0x3
+#define XTS_AES_LINESIZE_S  0
+
+#define XTS_AES_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
+/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This bit stores the destination parameter which will be used in manual encryption
+n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
+used..*/
+#define XTS_AES_DESTINATION    (BIT(0))
+#define XTS_AES_DESTINATION_M  (BIT(0))
+#define XTS_AES_DESTINATION_V  0x1
+#define XTS_AES_DESTINATION_S  0
+
+#define XTS_AES_PHYSICAL_ADDRESS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x348)
+/* XTS_AES_PHYSICAL_ADDRESS : R/W ;bitpos:[25:0] ;default: 26'h0 ; */
+/*description: This bits stores the physical-address parameter which will be used in manual enc
+ryption calculation. This value should aligned with byte number decided by line-
+size parameter..*/
+#define XTS_AES_PHYSICAL_ADDRESS    0x03FFFFFF
+#define XTS_AES_PHYSICAL_ADDRESS_M  ((XTS_AES_PHYSICAL_ADDRESS_V)<<(XTS_AES_PHYSICAL_ADDRESS_S))
+#define XTS_AES_PHYSICAL_ADDRESS_V  0x3FFFFFF
+#define XTS_AES_PHYSICAL_ADDRESS_S  0
+
+#define XTS_AES_TRIGGER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34C)
+/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to trigger the process of manual encryption calculation. This actio
+n should only be asserted when manual encryption status is 0. After this action,
+ manual encryption status becomes 1. After calculation is done, manual encryption
+n status becomes 2..*/
+#define XTS_AES_TRIGGER    (BIT(0))
+#define XTS_AES_TRIGGER_M  (BIT(0))
+#define XTS_AES_TRIGGER_V  0x1
+#define XTS_AES_TRIGGER_S  0
+
+#define XTS_AES_RELEASE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x350)
+/* XTS_AES_RELEASE : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to release encrypted result to mspi. This action should only be ass
+erted when manual encryption status is 2. After this action, manual encryption s
+tatus will become 3..*/
+#define XTS_AES_RELEASE    (BIT(0))
+#define XTS_AES_RELEASE_M  (BIT(0))
+#define XTS_AES_RELEASE_V  0x1
+#define XTS_AES_RELEASE_S  0
+
+#define XTS_AES_DESTROY_REG(i)          (REG_SPI_MEM_BASE(i) + 0x354)
+/* XTS_AES_DESTROY : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to destroy encrypted result. This action should be asserted only wh
+en manual encryption status is 3. After this action, manual encryption status wi
+ll become 0..*/
+#define XTS_AES_DESTROY    (BIT(0))
+#define XTS_AES_DESTROY_M  (BIT(0))
+#define XTS_AES_DESTROY_V  0x1
+#define XTS_AES_DESTROY_S  0
+
+#define XTS_AES_STATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x358)
+/* XTS_AES_STATE : RO ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: This bits stores the status of manual encryption. 0: idle, 1: busy of encryption
+ calculation, 2: encryption calculation is done but the encrypted result is invi
+sible to mspi, 3: the encrypted result is visible to mspi..*/
+#define XTS_AES_STATE    0x00000003
+#define XTS_AES_STATE_M  ((XTS_AES_STATE_V)<<(XTS_AES_STATE_S))
+#define XTS_AES_STATE_V  0x3
+#define XTS_AES_STATE_S  0
+
+#define XTS_AES_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x35C)
+/* XTS_AES_DATE : R/W ;bitpos:[29:0] ;default: 30'h20201010 ; */
+/*description: This bits stores the last modified-time of manual encryption feature..*/
+#define XTS_AES_DATE    0x3FFFFFFF
+#define XTS_AES_DATE_M  ((XTS_AES_DATE_V)<<(XTS_AES_DATE_S))
+#define XTS_AES_DATE_V  0x3FFFFFFF
+#define XTS_AES_DATE_S  0
+
+#define XTS_AES_DPA_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x388)
+/* XTS_AES_CRYPT_DPA_SELECT_REGISTER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYP
+T_SECURITY_LEVEL. 0: Controlled by efuse bits..*/
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER    (BIT(4))
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_M  (BIT(4))
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_V  0x1
+#define XTS_AES_CRYPT_DPA_SELECT_REGISTER_S  4
+/* XTS_AES_CRYPT_CALC_D_DPA_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calc
+ulation that using key 1 or key 2. 0: Enable DPA only in the calculation that us
+ing key 1..*/
+#define XTS_AES_CRYPT_CALC_D_DPA_EN    (BIT(3))
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_M  (BIT(3))
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_V  0x1
+#define XTS_AES_CRYPT_CALC_D_DPA_EN_S  3
+/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-
+7: The bigger the number is, the more secure the cryption is. (Note that the per
+formance of cryption will decrease together with this number increasing).*/
+#define XTS_AES_CRYPT_SECURITY_LEVEL    0x00000007
+#define XTS_AES_CRYPT_SECURITY_LEVEL_M  ((XTS_AES_CRYPT_SECURITY_LEVEL_V)<<(XTS_AES_CRYPT_SECURITY_LEVEL_S))
+#define XTS_AES_CRYPT_SECURITY_LEVEL_V  0x7
+#define XTS_AES_CRYPT_SECURITY_LEVEL_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32h2/rmt_periph.c b/components/soc/esp32h2/rmt_periph.c
index 7ca8a5ddcbd..c08da463f29 100644
--- a/components/soc/esp32h2/rmt_periph.c
+++ b/components/soc/esp32h2/rmt_periph.c
@@ -60,6 +60,7 @@ static const regdma_entries_config_t rmt_regdma_entries[] = {
 
 const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_RMT0,
         .regdma_entry_array = rmt_regdma_entries,
         .array_size = ARRAY_SIZE(rmt_regdma_entries)
     },
diff --git a/components/soc/esp32h2/spi_periph.c b/components/soc/esp32h2/spi_periph.c
index 213bed6def4..1ac5f7e40cb 100644
--- a/components/soc/esp32h2/spi_periph.c
+++ b/components/soc/esp32h2/spi_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,29 +13,6 @@
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
     {
         // MSPI has dedicated iomux pins
-        .spiclk_out = -1,
-        .spiclk_in = -1,
-        .spid_out = -1,
-        .spiq_out = -1,
-        .spiwp_out = -1,
-        .spihd_out = -1,
-        .spid_in = -1,
-        .spiq_in = -1,
-        .spiwp_in = -1,
-        .spihd_in = -1,
-        .spics_out = {-1},
-        .spics_in = -1,
-        .spiclk_iomux_pin = -1,
-        .spid_iomux_pin = -1,
-        .spiq_iomux_pin = -1,
-        .spiwp_iomux_pin = -1,
-        .spihd_iomux_pin = -1,
-        .spics0_iomux_pin = -1,
-        .irq = -1,
-        .irq_dma = -1,
-        .module = -1,
-        .hw = NULL,
-        .func = -1,
     }, {
         .spiclk_out = FSPICLK_OUT_IDX,
         .spiclk_in = FSPICLK_IN_IDX,
@@ -57,8 +34,50 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
         .irq = ETS_GSPI2_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_SPI2_MODULE,
         .hw = &GPSPI2,
         .func = SPI2_FUNC_NUM,
     }
 };
+
+/**
+ * Backup registers in Light sleep: (total cnt 12)
+ *
+ * cmd
+ * addr
+ * ctrl
+ * clock
+ * user
+ * user1
+ * user2
+ * ms_dlen
+ * misc
+ * dma_conf
+ * dma_int_ena
+ * slave
+ */
+#define SPI_RETENTION_REGS_CNT 12
+static const uint32_t spi_regs_map[4] = {0x31ff, 0x1000000, 0x0, 0x0};
+#define SPI_REG_RETENTION_ENTRIES(num) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
+                                               REG_SPI_BASE(num), REG_SPI_BASE(num), \
+                                               SPI_RETENTION_REGS_CNT, 0, 0, \
+                                               spi_regs_map[0], spi_regs_map[1], \
+                                               spi_regs_map[2], spi_regs_map[3]), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+    /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
+                                            SPI_DMA_INT_SET_REG(num), \
+                                            SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET , \
+                                            UINT32_MAX, 1, 0), \
+            .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2);   // '2' for GPSPI2
+
+const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = {   // '-1' to except mspi
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI2,
+        .entry_array = spi2_regs_retention,
+        .array_size = ARRAY_SIZE(spi2_regs_retention),
+    },
+};
diff --git a/components/soc/esp32h2/temperature_sensor_periph.c b/components/soc/esp32h2/temperature_sensor_periph.c
index e75c60b3178..348567d3f2f 100644
--- a/components/soc/esp32h2/temperature_sensor_periph.c
+++ b/components/soc/esp32h2/temperature_sensor_periph.c
@@ -1,10 +1,14 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
+#include "soc/regdma.h"
 #include "soc/temperature_sensor_periph.h"
+#include "soc/apb_saradc_reg.h"
+
 
 const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM] = {
     /*Offset   reg_val  min  max  error */
@@ -14,3 +18,24 @@ const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_S
     { 1,    11,   -30,   50,   2},
     { 2,    10,   -40,   20,   3},
 };
+
+// Temperature sensor sleep retention entries
+// Temperature sensor registers require set the reg_update bit to make the configuration take effect
+
+/* Temperature sensor Registers Context
+   Include: APB_SARADC_INT_ENA_REG /
+            APB_SARADC_APB_TSENS_CTRL_REG / APB_SARADC_TSENS_CTRL2_REG / APB_TSENS_WAKE_REG / APB_TSENS_SAMPLE_REG
+*/
+#define TEMPERATURE_SENSOR_RETENTION_REGS_CNT  5
+#define TEMPERATURE_SENSOR_RETENTION_MAP_BASE  APB_SARADC_INT_ENA_REG
+static const uint32_t temperature_sensor_regs_map[4] = {0x6c1, 0, 0, 0};
+static const regdma_entries_config_t temperature_sensor_regs_entries[] = {
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TSENS_LINK(0x00), TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_MAP_BASE, TEMPERATURE_SENSOR_RETENTION_REGS_CNT, 0, 0, temperature_sensor_regs_map[0], temperature_sensor_regs_map[1], temperature_sensor_regs_map[2], temperature_sensor_regs_map[3]), \
+           .owner = ENTRY(0) | ENTRY(2) }, \
+};
+
+const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention = {
+    .link_list = temperature_sensor_regs_entries,
+    .link_num = ARRAY_SIZE(temperature_sensor_regs_entries),
+    .module_id = SLEEP_RETENTION_MODULE_TEMP_SENSOR,
+};
diff --git a/components/soc/esp32h2/twai_periph.c b/components/soc/esp32h2/twai_periph.c
index 5104c78ed85..b81202a7411 100644
--- a/components/soc/esp32h2/twai_periph.c
+++ b/components/soc/esp32h2/twai_periph.c
@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/twai_periph.h"
+#include "soc/twai_reg.h"
 #include "soc/gpio_sig_map.h"
 
 const twai_controller_signal_conn_t twai_controller_periph_signals = {
@@ -20,3 +21,42 @@ const twai_controller_signal_conn_t twai_controller_periph_signals = {
         }
     }
 };
+
+/**
+ * TWAI Registers to be saved during sleep retention
+ * - TWAI_MODE_REG
+ * - TWAI_INTERRUPT_ENABLE_REG
+ * - TWAI_BUS_TIMING_0_REG / TWAI_BUS_TIMING_1_REG
+ * - TWAI_ERR_WARNING_LIMIT_REG
+ * - TWAI_RX_ERR_CNT_REG
+ * - TWAI_TX_ERR_CNT_REG
+ * - TWAI_DATA_x_REG
+ * - TWAI_CLOCK_DIVIDER_REG
+ * - TWAI_SW_STANDBY_CFG_REG
+ * - TWAI_HW_CFG_REG
+ * - TWAI_HW_STANDBY_CNT_REG
+ * - TWAI_IDLE_INTR_CNT_REG
+ * - TWAI_ECO_CFG_REG
+ * - TWAI_TIMESTAMP_PRESCALER_REG
+ * - TWAI_TIMESTAMP_CFG_REG
+*/
+#define TWAI_RETENTION_REGS_CNT 28
+#define TWAI_RETENTION_REGS_BASE(i) DR_REG_TWAI_BASE
+static const uint32_t twai_regs_map[4] = {0x9fffe0d1, 0xdf, 0x0, 0x0};
+#define TWAI_SLEEP_RETENTION_ENTRIES(id) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TWAI_LINK(0x00), \
+                                               TWAI_RETENTION_REGS_BASE(id), TWAI_RETENTION_REGS_BASE(id), \
+                                               TWAI_RETENTION_REGS_CNT, 0, 0, \
+                                               twai_regs_map[0], twai_regs_map[1], \
+                                               twai_regs_map[2], twai_regs_map[3]), \
+                                               .owner = ENTRY(0) | ENTRY(2) }, \
+}
+
+static const regdma_entries_config_t twai0_regs_retention[] = TWAI_SLEEP_RETENTION_ENTRIES(0);
+const twai_reg_retention_info_t twai_reg_retention_info[SOC_TWAI_CONTROLLER_NUM] = {
+    [0] = {
+        .module_id = SLEEP_RETENTION_MODULE_TWAI0,
+        .entry_array = twai0_regs_retention,
+        .array_size = ARRAY_SIZE(twai0_regs_retention)
+    },
+};
diff --git a/components/soc/esp32h2/uart_periph.c b/components/soc/esp32h2/uart_periph.c
index 7e44499e1e6..857eeb65e5d 100644
--- a/components/soc/esp32h2/uart_periph.c
+++ b/components/soc/esp32h2/uart_periph.c
@@ -118,10 +118,12 @@ static const regdma_entries_config_t uart1_regdma_entries[] = UART_SLEEP_RETENTI
 
 const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_UART0,
         .regdma_entry_array = uart0_regdma_entries,
         .array_size = ARRAY_SIZE(uart0_regdma_entries),
     },
     [1] = {
+        .module = SLEEP_RETENTION_MODULE_UART1,
         .regdma_entry_array = uart1_regdma_entries,
         .array_size = ARRAY_SIZE(uart1_regdma_entries),
     },
diff --git a/components/soc/esp32p4/etm_periph.c b/components/soc/esp32p4/etm_periph.c
new file mode 100644
index 00000000000..f7b28b02bf7
--- /dev/null
+++ b/components/soc/esp32p4/etm_periph.c
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/etm_periph.h"
+#include "soc/soc_etm_reg.h"
+
+/**
+ * ETM Registers to be saved during sleep retention
+ * - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
+*/
+#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
+
+static const regdma_entries_config_t etm_regdma_entries[] = {
+    // backup stage: save the status of enabled channels
+    // restore stage: store the enabled channels
+    [0] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
+        SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0),
+    },
+    [1] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
+        SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
+        .owner = ENTRY(0),
+    },
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [2] = {
+        .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
+        SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
+        .owner = ENTRY(0),
+    },
+};
+
+const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS] = {
+    [0] = {
+        .module = SLEEP_RETENTION_MODULE_ETM0,
+        .regdma_entry_array = etm_regdma_entries,
+        .array_size = ARRAY_SIZE(etm_regdma_entries)
+    },
+};
diff --git a/components/soc/esp32p4/i2c_periph.c b/components/soc/esp32p4/i2c_periph.c
index 41c208dda0f..699e5890dec 100644
--- a/components/soc/esp32p4/i2c_periph.c
+++ b/components/soc/esp32p4/i2c_periph.c
@@ -34,3 +34,49 @@ const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
         .irq = ETS_LP_I2C_INTR_SOURCE,
     },
 };
+
+// I2C sleep retention entries
+// I2C registers require set the reg_update bit to make the configuration take effect
+
+/* I2C Registers Context
+   Include: I2C_SCL_LOW_PERIOD_REG /
+            I2C_CTR_REG / I2C_TO_REG / I2C_SLAVE_ADDR_REG / I2C_FIFO_CONF_REG
+            I2C_INT_ENA_REG / I2C_SDA_HOLD_REG / I2C_SDA_SAMPLE_REG / I2C_SCL_START_HOLD_REG
+            I2C_SCL_RSTART_SETUP_REG / I2C_SCL_STOP_HOLD_REG / I2C_SCL_STOP_SETUP_REG /I2C_FILTER_CFG_REG / I2C_CLK_CONF_REG / I2C_SCL_ST_TIME_OUT_REG / I2C_SCL_MAIN_ST_TIME_OUT_REG / I2C_SCL_SP_CONF_REG / I2C_SCL_STRETCH_CONF_REG
+*/
+#define I2C0_RETENTION_REGS_CNT  18
+#define I2C0_RETENTION_MAP_BASE  I2C_SCL_LOW_PERIOD_REG(0)
+static const uint32_t i2c0_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
+static const regdma_entries_config_t i2c0_regs_retention[] = {
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_MAP_BASE, I2C0_RETENTION_REGS_CNT, 0, 0, i2c0_regs_map[0], i2c0_regs_map[1], i2c0_regs_map[2], i2c0_regs_map[3]), \
+           .owner = ENTRY(0) }, \
+    [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(0), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
+           .owner = ENTRY(0) }, \
+    [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(0), 0x0, I2C_FSM_RST_M, 1, 0), \
+           .owner = ENTRY(0) }, \
+    [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(0), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
+           .owner = ENTRY(0) }, \
+    [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(0), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
+           .owner = ENTRY(0) }, \
+};
+
+#define I2C1_RETENTION_REGS_CNT  18
+#define I2C1_RETENTION_MAP_BASE  I2C_SCL_LOW_PERIOD_REG(1)
+static const uint32_t i2c1_regs_map[4] = {0xc03f345b, 0x3, 0, 0};
+static const regdma_entries_config_t i2c1_regs_retention[] = {
+    [0] = {.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_I2C_LINK(0x00), I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_MAP_BASE, I2C1_RETENTION_REGS_CNT, 0, 0, i2c1_regs_map[0], i2c1_regs_map[1], i2c1_regs_map[2], i2c1_regs_map[3]), \
+           .owner = ENTRY(0) }, \
+    [1] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x01), I2C_CTR_REG(1), I2C_FSM_RST, I2C_FSM_RST_M, 1, 0), \
+           .owner = ENTRY(0) }, \
+    [2] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x02), I2C_CTR_REG(1), 0x0, I2C_FSM_RST_M, 1, 0), \
+    .owner = ENTRY(0) }, \
+    [3] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_I2C_LINK(0x03), I2C_CTR_REG(1), I2C_CONF_UPGATE, I2C_CONF_UPGATE_M, 1, 0), \
+           .owner = ENTRY(0) }, \
+    [4] = {.config = REGDMA_LINK_WAIT_INIT(REGDMA_I2C_LINK(0x04), I2C_CTR_REG(1), 0x0, I2C_CONF_UPGATE_M, 1, 0), \
+           .owner = ENTRY(0) }, \
+};
+
+const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM] = {
+    {i2c0_regs_retention, ARRAY_SIZE(i2c0_regs_retention), SLEEP_RETENTION_MODULE_I2C0},
+    {i2c1_regs_retention, ARRAY_SIZE(i2c1_regs_retention), SLEEP_RETENTION_MODULE_I2C1},
+};
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index a883653c744..98a2a44acdc 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -59,6 +59,10 @@ config SOC_LCDCAM_I80_LCD_SUPPORTED
     bool
     default y
 
+config SOC_LCDCAM_RGB_LCD_SUPPORTED
+    bool
+    default y
+
 config SOC_MIPI_CSI_SUPPORTED
     bool
     default y
@@ -263,6 +267,10 @@ config SOC_LP_ADC_SUPPORTED
     bool
     default y
 
+config SOC_LP_VAD_SUPPORTED
+    bool
+    default y
+
 config SOC_SPIRAM_SUPPORTED
     bool
     default y
@@ -595,6 +603,10 @@ config SOC_ETM_CHANNELS_PER_GROUP
     int
     default 50
 
+config SOC_ETM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_GPIO_PORT
     int
     default 1
@@ -767,6 +779,10 @@ config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
 
+config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
     bool
     default y
@@ -775,6 +791,10 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_LP_I2C_NUM
     int
     default 1
@@ -875,6 +895,10 @@ config SOC_ISP_COLOR_SUPPORTED
     bool
     default y
 
+config SOC_ISP_LSC_SUPPORTED
+    bool
+    default y
+
 config SOC_ISP_SHARE_CSI_BRG
     bool
     default y
@@ -987,6 +1011,18 @@ config SOC_ISP_HIST_INTERVAL_NUMS
     int
     default 15
 
+config SOC_ISP_LSC_GRAD_RATIO_INT_BITS
+    int
+    default 2
+
+config SOC_ISP_LSC_GRAD_RATIO_DEC_BITS
+    int
+    default 8
+
+config SOC_ISP_LSC_GRAD_RATIO_RES_BITS
+    int
+    default 22
+
 config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
     bool
     default y
@@ -995,6 +1031,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 8
@@ -1019,6 +1059,10 @@ config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
     int
     default 10
 
+config SOC_LEDC_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MMU_PERIPH_NUM
     int
     default 2
@@ -1147,6 +1191,10 @@ config SOC_LCD_I80_SUPPORTED
     bool
     default y
 
+config SOC_LCD_RGB_SUPPORTED
+    bool
+    default y
+
 config SOC_LCDCAM_I80_NUM_BUSES
     int
     default 1
@@ -1159,6 +1207,14 @@ config SOC_LCDCAM_RGB_NUM_PANELS
     int
     default 1
 
+config SOC_LCDCAM_RGB_DATA_WIDTH
+    int
+    default 24
+
+config SOC_LCD_SUPPORT_RGB_YUV_CONV
+    bool
+    default y
+
 config SOC_MCPWM_GROUPS
     int
     default 2
@@ -1219,6 +1275,14 @@ config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
     bool
     default y
 
+config SOC_USB_OTG_PERIPH_NUM
+    int
+    default 2
+
+config SOC_USB_UTMI_PHY_NUM
+    int
+    default 1
+
 config SOC_PARLIO_GROUPS
     int
     default 1
@@ -1259,6 +1323,10 @@ config SOC_PARLIO_TX_SIZE_BY_DMA
     bool
     default y
 
+config SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MPI_MEM_BLOCKS_NUM
     int
     default 4
@@ -1295,6 +1363,10 @@ config SOC_SDMMC_PSRAM_DMA_CAPABLE
     bool
     default y
 
+config SOC_SDMMC_UHS_I_SUPPORTED
+    bool
+    default y
+
 config SOC_SHA_DMA_MAX_BUFFER_SIZE
     int
     default 3968
@@ -1383,6 +1455,10 @@ config SOC_SPI_MAXIMUM_BUFFER_SIZE
     int
     default 64
 
+config SOC_SPI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_SPI_SUPPORT_SLAVE_HD_VER2
     bool
     default y
@@ -1631,6 +1707,10 @@ config SOC_TWAI_SUPPORTS_RX_STATUS
     bool
     default y
 
+config SOC_TWAI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_EFUSE_DIS_PAD_JTAG
     bool
     default y
@@ -1755,6 +1835,10 @@ config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
     bool
     default y
 
+config SOC_LP_I2S_SUPPORT_VAD
+    bool
+    default y
+
 config SOC_COEX_HW_PTI
     bool
     default y
@@ -1843,17 +1927,21 @@ config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
     bool
     default y
 
-config SOC_PSRAM_VDD_POWER_MPLL
+config SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
     bool
     default y
 
-config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
+config SOC_SLEEP_TGWDT_STOP_WORKAROUND
     bool
     default y
 
-config SOC_MODEM_CLOCK_IS_INDEPENDENT
+config SOC_PSRAM_VDD_POWER_MPLL
     bool
-    default n
+    default y
+
+config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
+    bool
+    default y
 
 config SOC_CLK_APLL_SUPPORTED
     bool
@@ -1863,6 +1951,10 @@ config SOC_CLK_MPLL_SUPPORTED
     bool
     default y
 
+config SOC_CLK_SDIO_PLL_SUPPORTED
+    bool
+    default y
+
 config SOC_CLK_XTAL32K_SUPPORTED
     bool
     default y
@@ -1883,6 +1975,10 @@ config SOC_PERIPH_CLK_CTRL_SHARED
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT
     bool
     default y
@@ -1899,6 +1995,10 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM
     bool
     default y
 
+config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_MEM_TCM_SUPPORTED
     bool
     default y
@@ -1911,7 +2011,7 @@ config SOC_ASYNCHRONOUS_BUS_ERROR_MODE
     bool
     default y
 
-config SOC_EMAC_IEEE_1588_SUPPORT
+config SOC_EMAC_IEEE1588V2_SUPPORTED
     bool
     default y
 
@@ -1954,3 +2054,7 @@ config SOC_LP_CORE_SUPPORT_ETM
 config SOC_LP_CORE_SUPPORT_LP_ADC
     bool
     default y
+
+config SOC_LP_CORE_SUPPORT_LP_VAD
+    bool
+    default y
diff --git a/components/soc/esp32p4/include/soc/assist_debug_reg.h b/components/soc/esp32p4/include/soc/assist_debug_reg.h
deleted file mode 100644
index 89c49a9cc6f..00000000000
--- a/components/soc/esp32p4/include/soc/assist_debug_reg.h
+++ /dev/null
@@ -1,1399 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
- *  core0 monitor enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
-
-/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
- *  core0 monitor interrupt status register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
-
-/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
- *  core0 monitor interrupt enable register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
-
-/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
- *  core0 monitor interrupt clr register
- */
-#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
- *  Core0 dram0 area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
- *  Core0 dram0 area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
- *  Core0 dram0 area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
- *  Core0 dram0 area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
- *  Core0 PIF area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
- *  Core0 PIF area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
- *  Core0 PIF area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
- *  Core0 PIF area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
- *  Core0 stackpoint underflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
-/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
- *  Core0 stackpoint overflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
- *  core0 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 dram0 region0 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
- *  core0 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 dram0 region0 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
- *  core0 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 dram0 region1 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
- *  core0 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
-/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 dram0 region1 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
- *  core0 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 PIF region0 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
- *  core0 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 PIF region0 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
- *  core0 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core0 PIF region1 start addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
- *  core0 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
-/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core0 PIF region1 end addr
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
- *  core0 area pc status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
-/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
- *  the stackpointer when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
- *  core0 area sp status register
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
-/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
- *  the PC when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
- *  stack min value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
-/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core0 sp region configuration regsiter
- */
-#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
- *  stack max value
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
-/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
- *  core0 sp pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
- *  stack monitor pc status register
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
-/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
- */
-#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
- *  record enable configuration register
- */
-#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
-/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable record PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
- *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
- *  recorded PC
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
-
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
-/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
- *  recorded sp
- */
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
-
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_iram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_iram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
- *  reg_core_0_iram0_recording_loadstore_0
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
-
-/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_iram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
- *  reg_core_0_iram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
-/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
- *  reg_core_0_iram0_recording_loadstore_1
- */
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register2
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
- *  reg_core_0_dram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  0
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [16:1]; default: 0;
- *  reg_core_0_dram0_recording_byteen_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000FFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000FFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  1
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register3
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_dram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
- *  exception monitor status register4
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_0_dram0_recording_pc_0
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
- *  exception monitor status register5
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
- *  reg_core_0_dram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  0
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [16:1]; default: 0;
- *  reg_core_0_dram0_recording_byteen_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000FFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000FFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  1
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register
- *  exception monitor status register6
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_0_dram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
-
-/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register
- *  exception monitor status register7
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
-/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_0_dram0_recording_pc_1
- */
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
-
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
-/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
- *  cpu's lastpc before exception
- */
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
-
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
- *  cpu debug mode status, 1 means cpu enter debug mode.
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
-/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
- *  cpu debug_module active status
- */
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
-
-/** ASSIST_DEBUG_CORE_1_INTR_ENA_REG register
- *  core1 monitor enable configuration register
- */
-#define ASSIST_DEBUG_CORE_1_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80)
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
- *  Core1 dram0 area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S  0
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
- *  Core1 dram0 area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S  1
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
- *  Core1 dram0 area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S  2
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
- *  Core1 dram0 area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S  3
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
- *  Core1 PIF area0 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S  4
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
- *  Core1 PIF area0 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S  5
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
- *  Core1 PIF area1 read monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S  6
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
- *  Core1 PIF area1 write monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S  7
-/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
- *  Core1 stackpoint underflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S  8
-/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
- *  Core1 stackpoint overflow monitor enable
- */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S  9
-
-/** ASSIST_DEBUG_CORE_1_INTR_RAW_REG register
- *  core1 monitor interrupt status register
- */
-#define ASSIST_DEBUG_CORE_1_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84)
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
- *  Core1 dram0 area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S  0
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
- *  Core1 dram0 area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S  1
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
- *  Core1 dram0 area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S  2
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
- *  Core1 dram0 area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S  3
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
- *  Core1 PIF area0 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S  4
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
- *  Core1 PIF area0 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S  5
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
- *  Core1 PIF area1 read monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S  6
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
- *  Core1 PIF area1 write monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S  7
-/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
- *  Core1 stackpoint underflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S  8
-/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
- *  Core1 stackpoint overflow monitor interrupt status
- */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S  9
-
-/** ASSIST_DEBUG_CORE_1_INTR_RLS_REG register
- *  core1 monitor interrupt enable register
- */
-#define ASSIST_DEBUG_CORE_1_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88)
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
- *  Core1 dram0 area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S  0
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
- *  Core1 dram0 area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S  1
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
- *  Core1 dram0 area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS    (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S  2
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
- *  Core1 dram0 area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS    (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S  3
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
- *  Core1 PIF area0 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS    (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S  4
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
- *  Core1 PIF area0 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS    (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S  5
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
- *  Core1 PIF area1 read monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS    (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S  6
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
- *  Core1 PIF area1 write monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS    (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S  7
-/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
- *  Core1 stackpoint underflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS    (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S  8
-/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
- *  Core1 stackpoint overflow monitor interrupt enable
- */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS    (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S  9
-
-/** ASSIST_DEBUG_CORE_1_INTR_CLR_REG register
- *  core1 monitor interrupt clr register
- */
-#define ASSIST_DEBUG_CORE_1_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8c)
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
- *  Core1 dram0 area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S  0
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
- *  Core1 dram0 area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S  1
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
- *  Core1 dram0 area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S  2
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
- *  Core1 dram0 area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S  3
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
- *  Core1 PIF area0 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S  4
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
- *  Core1 PIF area0 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S  5
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
- *  Core1 PIF area1 read monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S  6
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
- *  Core1 PIF area1 write monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S  7
-/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
- *  Core1 stackpoint underflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S  8
-/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
- *  Core1 stackpoint overflow monitor interrupt clr
- */
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S)
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S  9
-
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG register
- *  core1 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90)
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core1 dram0 region0 start addr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG register
- *  core1 dram0 region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core1 dram0 region0 end addr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG register
- *  core1 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98)
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core1 dram0 region1 start addr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG register
- *  core1 dram0 region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x9c)
-/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core1 dram0 region1 end addr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S)
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG register
- *  core1 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa0)
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core1 PIF region0 start addr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG register
- *  core1 PIF region0 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa4)
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core1 PIF region0 end addr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG register
- *  core1 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa8)
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
- *  Core1 PIF region1 start addr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG register
- *  core1 PIF region1 addr configuration register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xac)
-/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
- *  Core1 PIF region1 end addr
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_PC_REG register
- *  core1 area pc status register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb0)
-/** ASSIST_DEBUG_CORE_1_AREA_PC : RO; bitpos: [31:0]; default: 0;
- *  the stackpointer when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_1_AREA_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PC_M  (ASSIST_DEBUG_CORE_1_AREA_PC_V << ASSIST_DEBUG_CORE_1_AREA_PC_S)
-#define ASSIST_DEBUG_CORE_1_AREA_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_PC_S  0
-
-/** ASSIST_DEBUG_CORE_1_AREA_SP_REG register
- *  core1 area sp status register
- */
-#define ASSIST_DEBUG_CORE_1_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb4)
-/** ASSIST_DEBUG_CORE_1_AREA_SP : RO; bitpos: [31:0]; default: 0;
- *  the PC when first touch region monitor interrupt
- */
-#define ASSIST_DEBUG_CORE_1_AREA_SP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_SP_M  (ASSIST_DEBUG_CORE_1_AREA_SP_V << ASSIST_DEBUG_CORE_1_AREA_SP_S)
-#define ASSIST_DEBUG_CORE_1_AREA_SP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_AREA_SP_S  0
-
-/** ASSIST_DEBUG_CORE_1_SP_MIN_REG register
- *  stack min value
- */
-#define ASSIST_DEBUG_CORE_1_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb8)
-/** ASSIST_DEBUG_CORE_1_SP_MIN : R/W; bitpos: [31:0]; default: 0;
- *  core1 sp region configuration regsiter
- */
-#define ASSIST_DEBUG_CORE_1_SP_MIN    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_SP_MIN_M  (ASSIST_DEBUG_CORE_1_SP_MIN_V << ASSIST_DEBUG_CORE_1_SP_MIN_S)
-#define ASSIST_DEBUG_CORE_1_SP_MIN_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_SP_MIN_S  0
-
-/** ASSIST_DEBUG_CORE_1_SP_MAX_REG register
- *  stack max value
- */
-#define ASSIST_DEBUG_CORE_1_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xbc)
-/** ASSIST_DEBUG_CORE_1_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
- *  core1 sp pc status register
- */
-#define ASSIST_DEBUG_CORE_1_SP_MAX    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_SP_MAX_M  (ASSIST_DEBUG_CORE_1_SP_MAX_V << ASSIST_DEBUG_CORE_1_SP_MAX_S)
-#define ASSIST_DEBUG_CORE_1_SP_MAX_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_SP_MAX_S  0
-
-/** ASSIST_DEBUG_CORE_1_SP_PC_REG register
- *  stack monitor pc status register
- */
-#define ASSIST_DEBUG_CORE_1_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc0)
-/** ASSIST_DEBUG_CORE_1_SP_PC : RO; bitpos: [31:0]; default: 0;
- *  This regsiter stores the PC when trigger stack monitor.
- */
-#define ASSIST_DEBUG_CORE_1_SP_PC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_SP_PC_M  (ASSIST_DEBUG_CORE_1_SP_PC_V << ASSIST_DEBUG_CORE_1_SP_PC_S)
-#define ASSIST_DEBUG_CORE_1_SP_PC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_SP_PC_S  0
-
-/** ASSIST_DEBUG_CORE_1_RCD_EN_REG register
- *  record enable configuration register
- */
-#define ASSIST_DEBUG_CORE_1_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc4)
-/** ASSIST_DEBUG_CORE_1_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable record PC
- */
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_1_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_1_RCD_RECORDEN_S)
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_S  0
-/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
- *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
- */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S)
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S  1
-
-/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc8)
-/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
- *  recorded PC
- */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S)
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S  0
-
-/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG register
- *  record status regsiter
- */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xcc)
-/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
- *  recorded sp
- */
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_S)
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_S  0
-
-/** ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register0
- */
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd0)
-/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_1_iram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S  0
-/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
- *  reg_core_1_iram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S  24
-/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
- *  reg_core_1_iram0_recording_loadstore_0
- */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S)
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S  25
-
-/** ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register1
- */
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd4)
-/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_1_iram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S  0
-/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
- *  reg_core_1_iram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S  24
-/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
- *  reg_core_1_iram0_recording_loadstore_1
- */
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S)
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S  25
-
-/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register2
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd8)
-/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
- *  reg_core_1_dram0_recording_wr_0
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S)
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S  0
-/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [16:1]; default: 0;
- *  reg_core_1_dram0_recording_byteen_0
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0    0x0000FFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S)
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V  0x0000FFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S  1
-
-/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register3
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0xdc)
-/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_1_dram0_recording_addr_0
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S)
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S  0
-
-/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG register
- *  exception monitor status register4
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe0)
-/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_1_dram0_recording_pc_0
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S)
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S  0
-
-/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG register
- *  exception monitor status register5
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe4)
-/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
- *  reg_core_1_dram0_recording_wr_1
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S)
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S  0
-/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [16:1]; default: 0;
- *  reg_core_1_dram0_recording_byteen_1
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1    0x0000FFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S)
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V  0x0000FFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S  1
-
-/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG register
- *  exception monitor status register6
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe8)
-/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
- *  reg_core_1_dram0_recording_addr_1
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S)
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S  0
-
-/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG register
- *  exception monitor status register7
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0xec)
-/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
- *  reg_core_1_dram0_recording_pc_1
- */
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S)
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S  0
-
-/** ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0xf0)
-/** ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
- *  cpu's lastpc before exception
- */
-#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC    0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_S)
-#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
-#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_S  0
-
-/** ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG register
- *  cpu status register
- */
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0xf4)
-/** ASSIST_DEBUG_CORE_1_DEBUG_MODE : RO; bitpos: [0]; default: 0;
- *  cpu debug mode status, 1 means cpu enter debug mode.
- */
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODE    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_1_DEBUG_MODE_V << ASSIST_DEBUG_CORE_1_DEBUG_MODE_S)
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_S  0
-/** ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
- *  cpu debug_module active status
- */
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_S)
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_V  0x00000001U
-#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_S  1
-
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
- *  exception monitor status register6
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
- *  reg_core_x_iram0_dram0_limit_cycle_0
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
-
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
- *  exception monitor status register7
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
-/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
- *  reg_core_x_iram0_dram0_limit_cycle_1
- */
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
-
-/** ASSIST_DEBUG_CLOCK_GATE_REG register
- *  clock register
- */
-#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
-/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  Set 1 force on the clock gate
- */
-#define ASSIST_DEBUG_CLK_EN    (BIT(0))
-#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
-#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
-#define ASSIST_DEBUG_CLK_EN_S  0
-
-/** ASSIST_DEBUG_DATE_REG register
- *  version register
- */
-#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
-/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
- *  version register
- */
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
-#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/assist_debug_struct.h b/components/soc/esp32p4/include/soc/assist_debug_struct.h
deleted file mode 100644
index 88dd72df88e..00000000000
--- a/components/soc/esp32p4/include/soc/assist_debug_struct.h
+++ /dev/null
@@ -1,1316 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: monitor configuration registers */
-/** Type of core_0_intr_ena register
- *  core0 monitor enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor enable
-         */
-        uint32_t core_0_area_dram0_0_rd_ena:1;
-        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor enable
-         */
-        uint32_t core_0_area_dram0_0_wr_ena:1;
-        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor enable
-         */
-        uint32_t core_0_area_dram0_1_rd_ena:1;
-        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor enable
-         */
-        uint32_t core_0_area_dram0_1_wr_ena:1;
-        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor enable
-         */
-        uint32_t core_0_area_pif_0_rd_ena:1;
-        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor enable
-         */
-        uint32_t core_0_area_pif_0_wr_ena:1;
-        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor enable
-         */
-        uint32_t core_0_area_pif_1_rd_ena:1;
-        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor enable
-         */
-        uint32_t core_0_area_pif_1_wr_ena:1;
-        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor enable
-         */
-        uint32_t core_0_sp_spill_min_ena:1;
-        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor enable
-         */
-        uint32_t core_0_sp_spill_max_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_ena_reg_t;
-
-/** Type of core_0_area_dram0_0_min register
- *  core0 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 dram0 region0 start addr
-         */
-        uint32_t core_0_area_dram0_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_min_reg_t;
-
-/** Type of core_0_area_dram0_0_max register
- *  core0 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 dram0 region0 end addr
-         */
-        uint32_t core_0_area_dram0_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_0_max_reg_t;
-
-/** Type of core_0_area_dram0_1_min register
- *  core0 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 dram0 region1 start addr
-         */
-        uint32_t core_0_area_dram0_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_min_reg_t;
-
-/** Type of core_0_area_dram0_1_max register
- *  core0 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 dram0 region1 end addr
-         */
-        uint32_t core_0_area_dram0_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_dram0_1_max_reg_t;
-
-/** Type of core_0_area_pif_0_min register
- *  core0 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 PIF region0 start addr
-         */
-        uint32_t core_0_area_pif_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_min_reg_t;
-
-/** Type of core_0_area_pif_0_max register
- *  core0 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 PIF region0 end addr
-         */
-        uint32_t core_0_area_pif_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_0_max_reg_t;
-
-/** Type of core_0_area_pif_1_min register
- *  core0 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core0 PIF region1 start addr
-         */
-        uint32_t core_0_area_pif_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_min_reg_t;
-
-/** Type of core_0_area_pif_1_max register
- *  core0 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core0 PIF region1 end addr
-         */
-        uint32_t core_0_area_pif_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pif_1_max_reg_t;
-
-/** Type of core_0_area_pc register
- *  core0 area pc status register
- */
-typedef union {
-    struct {
-        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
-         *  the stackpointer when first touch region monitor interrupt
-         */
-        uint32_t core_0_area_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_pc_reg_t;
-
-/** Type of core_0_area_sp register
- *  core0 area sp status register
- */
-typedef union {
-    struct {
-        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
-         *  the PC when first touch region monitor interrupt
-         */
-        uint32_t core_0_area_sp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_area_sp_reg_t;
-
-/** Type of core_0_sp_min register
- *  stack min value
- */
-typedef union {
-    struct {
-        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core0 sp region configuration regsiter
-         */
-        uint32_t core_0_sp_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_min_reg_t;
-
-/** Type of core_0_sp_max register
- *  stack max value
- */
-typedef union {
-    struct {
-        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
-         *  core0 sp pc status register
-         */
-        uint32_t core_0_sp_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_max_reg_t;
-
-/** Type of core_0_sp_pc register
- *  stack monitor pc status register
- */
-typedef union {
-    struct {
-        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
-         */
-        uint32_t core_0_sp_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_sp_pc_reg_t;
-
-/** Type of core_1_intr_ena register
- *  core1 monitor enable configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
-         *  Core1 dram0 area0 read monitor enable
-         */
-        uint32_t core_1_area_dram0_0_rd_ena:1;
-        /** core_1_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
-         *  Core1 dram0 area0 write monitor enable
-         */
-        uint32_t core_1_area_dram0_0_wr_ena:1;
-        /** core_1_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
-         *  Core1 dram0 area1 read monitor enable
-         */
-        uint32_t core_1_area_dram0_1_rd_ena:1;
-        /** core_1_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
-         *  Core1 dram0 area1 write monitor enable
-         */
-        uint32_t core_1_area_dram0_1_wr_ena:1;
-        /** core_1_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
-         *  Core1 PIF area0 read monitor enable
-         */
-        uint32_t core_1_area_pif_0_rd_ena:1;
-        /** core_1_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
-         *  Core1 PIF area0 write monitor enable
-         */
-        uint32_t core_1_area_pif_0_wr_ena:1;
-        /** core_1_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
-         *  Core1 PIF area1 read monitor enable
-         */
-        uint32_t core_1_area_pif_1_rd_ena:1;
-        /** core_1_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
-         *  Core1 PIF area1 write monitor enable
-         */
-        uint32_t core_1_area_pif_1_wr_ena:1;
-        /** core_1_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
-         *  Core1 stackpoint underflow monitor enable
-         */
-        uint32_t core_1_sp_spill_min_ena:1;
-        /** core_1_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
-         *  Core1 stackpoint overflow monitor enable
-         */
-        uint32_t core_1_sp_spill_max_ena:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_1_intr_ena_reg_t;
-
-/** Type of core_1_area_dram0_0_min register
- *  core1 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core1 dram0 region0 start addr
-         */
-        uint32_t core_1_area_dram0_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_dram0_0_min_reg_t;
-
-/** Type of core_1_area_dram0_0_max register
- *  core1 dram0 region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core1 dram0 region0 end addr
-         */
-        uint32_t core_1_area_dram0_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_dram0_0_max_reg_t;
-
-/** Type of core_1_area_dram0_1_min register
- *  core1 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core1 dram0 region1 start addr
-         */
-        uint32_t core_1_area_dram0_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_dram0_1_min_reg_t;
-
-/** Type of core_1_area_dram0_1_max register
- *  core1 dram0 region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core1 dram0 region1 end addr
-         */
-        uint32_t core_1_area_dram0_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_dram0_1_max_reg_t;
-
-/** Type of core_1_area_pif_0_min register
- *  core1 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core1 PIF region0 start addr
-         */
-        uint32_t core_1_area_pif_0_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_pif_0_min_reg_t;
-
-/** Type of core_1_area_pif_0_max register
- *  core1 PIF region0 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core1 PIF region0 end addr
-         */
-        uint32_t core_1_area_pif_0_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_pif_0_max_reg_t;
-
-/** Type of core_1_area_pif_1_min register
- *  core1 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
-         *  Core1 PIF region1 start addr
-         */
-        uint32_t core_1_area_pif_1_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_pif_1_min_reg_t;
-
-/** Type of core_1_area_pif_1_max register
- *  core1 PIF region1 addr configuration register
- */
-typedef union {
-    struct {
-        /** core_1_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
-         *  Core1 PIF region1 end addr
-         */
-        uint32_t core_1_area_pif_1_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_pif_1_max_reg_t;
-
-/** Type of core_1_area_pc register
- *  core1 area pc status register
- */
-typedef union {
-    struct {
-        /** core_1_area_pc : RO; bitpos: [31:0]; default: 0;
-         *  the stackpointer when first touch region monitor interrupt
-         */
-        uint32_t core_1_area_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_pc_reg_t;
-
-/** Type of core_1_area_sp register
- *  core1 area sp status register
- */
-typedef union {
-    struct {
-        /** core_1_area_sp : RO; bitpos: [31:0]; default: 0;
-         *  the PC when first touch region monitor interrupt
-         */
-        uint32_t core_1_area_sp:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_area_sp_reg_t;
-
-/** Type of core_1_sp_min register
- *  stack min value
- */
-typedef union {
-    struct {
-        /** core_1_sp_min : R/W; bitpos: [31:0]; default: 0;
-         *  core1 sp region configuration regsiter
-         */
-        uint32_t core_1_sp_min:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_sp_min_reg_t;
-
-/** Type of core_1_sp_max register
- *  stack max value
- */
-typedef union {
-    struct {
-        /** core_1_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
-         *  core1 sp pc status register
-         */
-        uint32_t core_1_sp_max:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_sp_max_reg_t;
-
-/** Type of core_1_sp_pc register
- *  stack monitor pc status register
- */
-typedef union {
-    struct {
-        /** core_1_sp_pc : RO; bitpos: [31:0]; default: 0;
-         *  This regsiter stores the PC when trigger stack monitor.
-         */
-        uint32_t core_1_sp_pc:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_sp_pc_reg_t;
-
-
-/** Group: interrupt configuration register */
-/** Type of core_0_intr_raw register
- *  core0 monitor interrupt status register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_0_rd_raw:1;
-        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_0_wr_raw:1;
-        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_1_rd_raw:1;
-        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt status
-         */
-        uint32_t core_0_area_dram0_1_wr_raw:1;
-        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt status
-         */
-        uint32_t core_0_area_pif_0_rd_raw:1;
-        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt status
-         */
-        uint32_t core_0_area_pif_0_wr_raw:1;
-        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt status
-         */
-        uint32_t core_0_area_pif_1_rd_raw:1;
-        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt status
-         */
-        uint32_t core_0_area_pif_1_wr_raw:1;
-        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt status
-         */
-        uint32_t core_0_sp_spill_min_raw:1;
-        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt status
-         */
-        uint32_t core_0_sp_spill_max_raw:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_raw_reg_t;
-
-/** Type of core_0_intr_rls register
- *  core0 monitor interrupt enable register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_rd_rls:1;
-        /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_0_wr_rls:1;
-        /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_rd_rls:1;
-        /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_dram0_1_wr_rls:1;
-        /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_rd_rls:1;
-        /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_0_wr_rls:1;
-        /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_rd_rls:1;
-        /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt enable
-         */
-        uint32_t core_0_area_pif_1_wr_rls:1;
-        /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_min_rls:1;
-        /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt enable
-         */
-        uint32_t core_0_sp_spill_max_rls:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_rls_reg_t;
-
-/** Type of core_0_intr_clr register
- *  core0 monitor interrupt clr register
- */
-typedef union {
-    struct {
-        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
-         *  Core0 dram0 area0 read monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_0_rd_clr:1;
-        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
-         *  Core0 dram0 area0 write monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_0_wr_clr:1;
-        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
-         *  Core0 dram0 area1 read monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_1_rd_clr:1;
-        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
-         *  Core0 dram0 area1 write monitor interrupt clr
-         */
-        uint32_t core_0_area_dram0_1_wr_clr:1;
-        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
-         *  Core0 PIF area0 read monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_0_rd_clr:1;
-        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
-         *  Core0 PIF area0 write monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_0_wr_clr:1;
-        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
-         *  Core0 PIF area1 read monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_1_rd_clr:1;
-        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
-         *  Core0 PIF area1 write monitor interrupt clr
-         */
-        uint32_t core_0_area_pif_1_wr_clr:1;
-        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
-         *  Core0 stackpoint underflow monitor interrupt clr
-         */
-        uint32_t core_0_sp_spill_min_clr:1;
-        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
-         *  Core0 stackpoint overflow monitor interrupt clr
-         */
-        uint32_t core_0_sp_spill_max_clr:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_0_intr_clr_reg_t;
-
-/** Type of core_1_intr_raw register
- *  core1 monitor interrupt status register
- */
-typedef union {
-    struct {
-        /** core_1_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
-         *  Core1 dram0 area0 read monitor interrupt status
-         */
-        uint32_t core_1_area_dram0_0_rd_raw:1;
-        /** core_1_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
-         *  Core1 dram0 area0 write monitor interrupt status
-         */
-        uint32_t core_1_area_dram0_0_wr_raw:1;
-        /** core_1_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
-         *  Core1 dram0 area1 read monitor interrupt status
-         */
-        uint32_t core_1_area_dram0_1_rd_raw:1;
-        /** core_1_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
-         *  Core1 dram0 area1 write monitor interrupt status
-         */
-        uint32_t core_1_area_dram0_1_wr_raw:1;
-        /** core_1_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
-         *  Core1 PIF area0 read monitor interrupt status
-         */
-        uint32_t core_1_area_pif_0_rd_raw:1;
-        /** core_1_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
-         *  Core1 PIF area0 write monitor interrupt status
-         */
-        uint32_t core_1_area_pif_0_wr_raw:1;
-        /** core_1_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
-         *  Core1 PIF area1 read monitor interrupt status
-         */
-        uint32_t core_1_area_pif_1_rd_raw:1;
-        /** core_1_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
-         *  Core1 PIF area1 write monitor interrupt status
-         */
-        uint32_t core_1_area_pif_1_wr_raw:1;
-        /** core_1_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
-         *  Core1 stackpoint underflow monitor interrupt status
-         */
-        uint32_t core_1_sp_spill_min_raw:1;
-        /** core_1_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
-         *  Core1 stackpoint overflow monitor interrupt status
-         */
-        uint32_t core_1_sp_spill_max_raw:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_1_intr_raw_reg_t;
-
-/** Type of core_1_intr_rls register
- *  core1 monitor interrupt enable register
- */
-typedef union {
-    struct {
-        /** core_1_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
-         *  Core1 dram0 area0 read monitor interrupt enable
-         */
-        uint32_t core_1_area_dram0_0_rd_rls:1;
-        /** core_1_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
-         *  Core1 dram0 area0 write monitor interrupt enable
-         */
-        uint32_t core_1_area_dram0_0_wr_rls:1;
-        /** core_1_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
-         *  Core1 dram0 area1 read monitor interrupt enable
-         */
-        uint32_t core_1_area_dram0_1_rd_rls:1;
-        /** core_1_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
-         *  Core1 dram0 area1 write monitor interrupt enable
-         */
-        uint32_t core_1_area_dram0_1_wr_rls:1;
-        /** core_1_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
-         *  Core1 PIF area0 read monitor interrupt enable
-         */
-        uint32_t core_1_area_pif_0_rd_rls:1;
-        /** core_1_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
-         *  Core1 PIF area0 write monitor interrupt enable
-         */
-        uint32_t core_1_area_pif_0_wr_rls:1;
-        /** core_1_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
-         *  Core1 PIF area1 read monitor interrupt enable
-         */
-        uint32_t core_1_area_pif_1_rd_rls:1;
-        /** core_1_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
-         *  Core1 PIF area1 write monitor interrupt enable
-         */
-        uint32_t core_1_area_pif_1_wr_rls:1;
-        /** core_1_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
-         *  Core1 stackpoint underflow monitor interrupt enable
-         */
-        uint32_t core_1_sp_spill_min_rls:1;
-        /** core_1_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
-         *  Core1 stackpoint overflow monitor interrupt enable
-         */
-        uint32_t core_1_sp_spill_max_rls:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_1_intr_rls_reg_t;
-
-/** Type of core_1_intr_clr register
- *  core1 monitor interrupt clr register
- */
-typedef union {
-    struct {
-        /** core_1_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
-         *  Core1 dram0 area0 read monitor interrupt clr
-         */
-        uint32_t core_1_area_dram0_0_rd_clr:1;
-        /** core_1_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
-         *  Core1 dram0 area0 write monitor interrupt clr
-         */
-        uint32_t core_1_area_dram0_0_wr_clr:1;
-        /** core_1_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
-         *  Core1 dram0 area1 read monitor interrupt clr
-         */
-        uint32_t core_1_area_dram0_1_rd_clr:1;
-        /** core_1_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
-         *  Core1 dram0 area1 write monitor interrupt clr
-         */
-        uint32_t core_1_area_dram0_1_wr_clr:1;
-        /** core_1_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
-         *  Core1 PIF area0 read monitor interrupt clr
-         */
-        uint32_t core_1_area_pif_0_rd_clr:1;
-        /** core_1_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
-         *  Core1 PIF area0 write monitor interrupt clr
-         */
-        uint32_t core_1_area_pif_0_wr_clr:1;
-        /** core_1_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
-         *  Core1 PIF area1 read monitor interrupt clr
-         */
-        uint32_t core_1_area_pif_1_rd_clr:1;
-        /** core_1_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
-         *  Core1 PIF area1 write monitor interrupt clr
-         */
-        uint32_t core_1_area_pif_1_wr_clr:1;
-        /** core_1_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
-         *  Core1 stackpoint underflow monitor interrupt clr
-         */
-        uint32_t core_1_sp_spill_min_clr:1;
-        /** core_1_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
-         *  Core1 stackpoint overflow monitor interrupt clr
-         */
-        uint32_t core_1_sp_spill_max_clr:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} assist_debug_core_1_intr_clr_reg_t;
-
-
-/** Group: pc reording configuration register */
-/** Type of core_0_rcd_en register
- *  record enable configuration register
- */
-typedef union {
-    struct {
-        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable record PC
-         */
-        uint32_t core_0_rcd_recorden:1;
-        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
-         */
-        uint32_t core_0_rcd_pdebugen:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_en_reg_t;
-
-/** Type of core_1_rcd_en register
- *  record enable configuration register
- */
-typedef union {
-    struct {
-        /** core_1_rcd_recorden : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable record PC
-         */
-        uint32_t core_1_rcd_recorden:1;
-        /** core_1_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
-         */
-        uint32_t core_1_rcd_pdebugen:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_1_rcd_en_reg_t;
-
-
-/** Group: pc reording status register */
-/** Type of core_0_rcd_pdebugpc register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
-         *  recorded PC
-         */
-        uint32_t core_0_rcd_pdebugpc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugpc_reg_t;
-
-/** Type of core_0_rcd_pdebugsp register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
-         *  recorded sp
-         */
-        uint32_t core_0_rcd_pdebugsp:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_rcd_pdebugsp_reg_t;
-
-/** Type of core_1_rcd_pdebugpc register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_1_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
-         *  recorded PC
-         */
-        uint32_t core_1_rcd_pdebugpc:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_rcd_pdebugpc_reg_t;
-
-/** Type of core_1_rcd_pdebugsp register
- *  record status regsiter
- */
-typedef union {
-    struct {
-        /** core_1_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
-         *  recorded sp
-         */
-        uint32_t core_1_rcd_pdebugsp:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_rcd_pdebugsp_reg_t;
-
-
-/** Group: exception monitor regsiter */
-/** Type of core_0_iram0_exception_monitor_0 register
- *  exception monitor status register0
- */
-typedef union {
-    struct {
-        /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_iram0_recording_addr_0
-         */
-        uint32_t core_0_iram0_recording_addr_0:24;
-        /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_iram0_recording_wr_0
-         */
-        uint32_t core_0_iram0_recording_wr_0:1;
-        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
-         *  reg_core_0_iram0_recording_loadstore_0
-         */
-        uint32_t core_0_iram0_recording_loadstore_0:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
-
-/** Type of core_0_iram0_exception_monitor_1 register
- *  exception monitor status register1
- */
-typedef union {
-    struct {
-        /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_iram0_recording_addr_1
-         */
-        uint32_t core_0_iram0_recording_addr_1:24;
-        /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
-         *  reg_core_0_iram0_recording_wr_1
-         */
-        uint32_t core_0_iram0_recording_wr_1:1;
-        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
-         *  reg_core_0_iram0_recording_loadstore_1
-         */
-        uint32_t core_0_iram0_recording_loadstore_1:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_0 register
- *  exception monitor status register2
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
-         *  reg_core_0_dram0_recording_wr_0
-         */
-        uint32_t core_0_dram0_recording_wr_0:1;
-        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
-         *  reg_core_0_dram0_recording_byteen_0
-         */
-        uint32_t core_0_dram0_recording_byteen_0:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_1 register
- *  exception monitor status register3
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_dram0_recording_addr_0
-         */
-        uint32_t core_0_dram0_recording_addr_0:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_2 register
- *  exception monitor status register4
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_0_dram0_recording_pc_0
-         */
-        uint32_t core_0_dram0_recording_pc_0:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_3 register
- *  exception monitor status register5
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
-         *  reg_core_0_dram0_recording_wr_1
-         */
-        uint32_t core_0_dram0_recording_wr_1:1;
-        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
-         *  reg_core_0_dram0_recording_byteen_1
-         */
-        uint32_t core_0_dram0_recording_byteen_1:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_4 register
- *  exception monitor status register6
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_0_dram0_recording_addr_1
-         */
-        uint32_t core_0_dram0_recording_addr_1:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
-
-/** Type of core_0_dram0_exception_monitor_5 register
- *  exception monitor status register7
- */
-typedef union {
-    struct {
-        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_0_dram0_recording_pc_1
-         */
-        uint32_t core_0_dram0_recording_pc_1:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
-
-/** Type of core_1_iram0_exception_monitor_0 register
- *  exception monitor status register0
- */
-typedef union {
-    struct {
-        /** core_1_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_1_iram0_recording_addr_0
-         */
-        uint32_t core_1_iram0_recording_addr_0:24;
-        /** core_1_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
-         *  reg_core_1_iram0_recording_wr_0
-         */
-        uint32_t core_1_iram0_recording_wr_0:1;
-        /** core_1_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
-         *  reg_core_1_iram0_recording_loadstore_0
-         */
-        uint32_t core_1_iram0_recording_loadstore_0:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} assist_debug_core_1_iram0_exception_monitor_0_reg_t;
-
-/** Type of core_1_iram0_exception_monitor_1 register
- *  exception monitor status register1
- */
-typedef union {
-    struct {
-        /** core_1_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_1_iram0_recording_addr_1
-         */
-        uint32_t core_1_iram0_recording_addr_1:24;
-        /** core_1_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
-         *  reg_core_1_iram0_recording_wr_1
-         */
-        uint32_t core_1_iram0_recording_wr_1:1;
-        /** core_1_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
-         *  reg_core_1_iram0_recording_loadstore_1
-         */
-        uint32_t core_1_iram0_recording_loadstore_1:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} assist_debug_core_1_iram0_exception_monitor_1_reg_t;
-
-/** Type of core_1_dram0_exception_monitor_0 register
- *  exception monitor status register2
- */
-typedef union {
-    struct {
-        /** core_1_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
-         *  reg_core_1_dram0_recording_wr_0
-         */
-        uint32_t core_1_dram0_recording_wr_0:1;
-        /** core_1_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
-         *  reg_core_1_dram0_recording_byteen_0
-         */
-        uint32_t core_1_dram0_recording_byteen_0:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} assist_debug_core_1_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_1_dram0_exception_monitor_1 register
- *  exception monitor status register3
- */
-typedef union {
-    struct {
-        /** core_1_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_1_dram0_recording_addr_0
-         */
-        uint32_t core_1_dram0_recording_addr_0:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} assist_debug_core_1_dram0_exception_monitor_1_reg_t;
-
-/** Type of core_1_dram0_exception_monitor_2 register
- *  exception monitor status register4
- */
-typedef union {
-    struct {
-        /** core_1_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_1_dram0_recording_pc_0
-         */
-        uint32_t core_1_dram0_recording_pc_0:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_dram0_exception_monitor_2_reg_t;
-
-/** Type of core_1_dram0_exception_monitor_3 register
- *  exception monitor status register5
- */
-typedef union {
-    struct {
-        /** core_1_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
-         *  reg_core_1_dram0_recording_wr_1
-         */
-        uint32_t core_1_dram0_recording_wr_1:1;
-        /** core_1_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
-         *  reg_core_1_dram0_recording_byteen_1
-         */
-        uint32_t core_1_dram0_recording_byteen_1:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} assist_debug_core_1_dram0_exception_monitor_3_reg_t;
-
-/** Type of core_1_dram0_exception_monitor_4 register
- *  exception monitor status register6
- */
-typedef union {
-    struct {
-        /** core_1_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
-         *  reg_core_1_dram0_recording_addr_1
-         */
-        uint32_t core_1_dram0_recording_addr_1:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} assist_debug_core_1_dram0_exception_monitor_4_reg_t;
-
-/** Type of core_1_dram0_exception_monitor_5 register
- *  exception monitor status register7
- */
-typedef union {
-    struct {
-        /** core_1_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
-         *  reg_core_1_dram0_recording_pc_1
-         */
-        uint32_t core_1_dram0_recording_pc_1:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_dram0_exception_monitor_5_reg_t;
-
-/** Type of core_x_iram0_dram0_exception_monitor_0 register
- *  exception monitor status register6
- */
-typedef union {
-    struct {
-        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
-         *  reg_core_x_iram0_dram0_limit_cycle_0
-         */
-        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
-
-/** Type of core_x_iram0_dram0_exception_monitor_1 register
- *  exception monitor status register7
- */
-typedef union {
-    struct {
-        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
-         *  reg_core_x_iram0_dram0_limit_cycle_1
-         */
-        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
-
-
-/** Group: cpu status registers */
-/** Type of core_0_lastpc_before_exception register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
-         *  cpu's lastpc before exception
-         */
-        uint32_t core_0_lastpc_before_exc:32;
-    };
-    uint32_t val;
-} assist_debug_core_0_lastpc_before_exception_reg_t;
-
-/** Type of core_0_debug_mode register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
-         *  cpu debug mode status, 1 means cpu enter debug mode.
-         */
-        uint32_t core_0_debug_mode:1;
-        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
-         *  cpu debug_module active status
-         */
-        uint32_t core_0_debug_module_active:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_0_debug_mode_reg_t;
-
-/** Type of core_1_lastpc_before_exception register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_1_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
-         *  cpu's lastpc before exception
-         */
-        uint32_t core_1_lastpc_before_exc:32;
-    };
-    uint32_t val;
-} assist_debug_core_1_lastpc_before_exception_reg_t;
-
-/** Type of core_1_debug_mode register
- *  cpu status register
- */
-typedef union {
-    struct {
-        /** core_1_debug_mode : RO; bitpos: [0]; default: 0;
-         *  cpu debug mode status, 1 means cpu enter debug mode.
-         */
-        uint32_t core_1_debug_mode:1;
-        /** core_1_debug_module_active : RO; bitpos: [1]; default: 0;
-         *  cpu debug_module active status
-         */
-        uint32_t core_1_debug_module_active:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} assist_debug_core_1_debug_mode_reg_t;
-
-
-/** Group: Configuration Registers */
-/** Type of clock_gate register
- *  clock register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  Set 1 force on the clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} assist_debug_clock_gate_reg_t;
-
-/** Type of date register
- *  version register
- */
-typedef union {
-    struct {
-        /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
-         *  version register
-         */
-        uint32_t assist_debug_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} assist_debug_date_reg_t;
-
-
-typedef struct {
-    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
-    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
-    volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
-    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
-    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
-    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
-    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
-    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
-    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
-    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
-    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
-    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
-    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
-    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
-    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
-    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
-    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
-    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
-    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
-    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
-    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
-    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
-    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
-    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
-    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
-    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
-    volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
-    volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
-    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
-    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
-    uint32_t reserved_078[2];
-    volatile assist_debug_core_1_intr_ena_reg_t core_1_intr_ena;
-    volatile assist_debug_core_1_intr_raw_reg_t core_1_intr_raw;
-    volatile assist_debug_core_1_intr_rls_reg_t core_1_intr_rls;
-    volatile assist_debug_core_1_intr_clr_reg_t core_1_intr_clr;
-    volatile assist_debug_core_1_area_dram0_0_min_reg_t core_1_area_dram0_0_min;
-    volatile assist_debug_core_1_area_dram0_0_max_reg_t core_1_area_dram0_0_max;
-    volatile assist_debug_core_1_area_dram0_1_min_reg_t core_1_area_dram0_1_min;
-    volatile assist_debug_core_1_area_dram0_1_max_reg_t core_1_area_dram0_1_max;
-    volatile assist_debug_core_1_area_pif_0_min_reg_t core_1_area_pif_0_min;
-    volatile assist_debug_core_1_area_pif_0_max_reg_t core_1_area_pif_0_max;
-    volatile assist_debug_core_1_area_pif_1_min_reg_t core_1_area_pif_1_min;
-    volatile assist_debug_core_1_area_pif_1_max_reg_t core_1_area_pif_1_max;
-    volatile assist_debug_core_1_area_pc_reg_t core_1_area_pc;
-    volatile assist_debug_core_1_area_sp_reg_t core_1_area_sp;
-    volatile assist_debug_core_1_sp_min_reg_t core_1_sp_min;
-    volatile assist_debug_core_1_sp_max_reg_t core_1_sp_max;
-    volatile assist_debug_core_1_sp_pc_reg_t core_1_sp_pc;
-    volatile assist_debug_core_1_rcd_en_reg_t core_1_rcd_en;
-    volatile assist_debug_core_1_rcd_pdebugpc_reg_t core_1_rcd_pdebugpc;
-    volatile assist_debug_core_1_rcd_pdebugsp_reg_t core_1_rcd_pdebugsp;
-    volatile assist_debug_core_1_iram0_exception_monitor_0_reg_t core_1_iram0_exception_monitor_0;
-    volatile assist_debug_core_1_iram0_exception_monitor_1_reg_t core_1_iram0_exception_monitor_1;
-    volatile assist_debug_core_1_dram0_exception_monitor_0_reg_t core_1_dram0_exception_monitor_0;
-    volatile assist_debug_core_1_dram0_exception_monitor_1_reg_t core_1_dram0_exception_monitor_1;
-    volatile assist_debug_core_1_dram0_exception_monitor_2_reg_t core_1_dram0_exception_monitor_2;
-    volatile assist_debug_core_1_dram0_exception_monitor_3_reg_t core_1_dram0_exception_monitor_3;
-    volatile assist_debug_core_1_dram0_exception_monitor_4_reg_t core_1_dram0_exception_monitor_4;
-    volatile assist_debug_core_1_dram0_exception_monitor_5_reg_t core_1_dram0_exception_monitor_5;
-    volatile assist_debug_core_1_lastpc_before_exception_reg_t core_1_lastpc_before_exception;
-    volatile assist_debug_core_1_debug_mode_reg_t core_1_debug_mode;
-    uint32_t reserved_0f8[2];
-    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
-    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
-    volatile assist_debug_clock_gate_reg_t clock_gate;
-    uint32_t reserved_10c[188];
-    volatile assist_debug_date_reg_t date;
-} assist_debug_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/cache_reg.h b/components/soc/esp32p4/include/soc/cache_reg.h
deleted file mode 100644
index b3cc3cd039c..00000000000
--- a/components/soc/esp32p4/include/soc/cache_reg.h
+++ /dev/null
@@ -1,6294 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** CACHE_L1_ICACHE_CTRL_REG register
- *  L1 instruction Cache(L1-ICache) control register
- */
-#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
-/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0;
- *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
-#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
-/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0;
- *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
-#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
-/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
-#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
-/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
-#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
-#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
-#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
-
-/** CACHE_L1_DCACHE_CTRL_REG register
- *  L1 data Cache(L1-DCache) control register
- */
-#define CACHE_L1_DCACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
-/** CACHE_L1_DCACHE_SHUT_DBUS0 : R/W; bitpos: [0]; default: 0;
- *  The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable
- */
-#define CACHE_L1_DCACHE_SHUT_DBUS0    (BIT(0))
-#define CACHE_L1_DCACHE_SHUT_DBUS0_M  (CACHE_L1_DCACHE_SHUT_DBUS0_V << CACHE_L1_DCACHE_SHUT_DBUS0_S)
-#define CACHE_L1_DCACHE_SHUT_DBUS0_V  0x00000001U
-#define CACHE_L1_DCACHE_SHUT_DBUS0_S  0
-/** CACHE_L1_DCACHE_SHUT_DBUS1 : R/W; bitpos: [1]; default: 0;
- *  The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable
- */
-#define CACHE_L1_DCACHE_SHUT_DBUS1    (BIT(1))
-#define CACHE_L1_DCACHE_SHUT_DBUS1_M  (CACHE_L1_DCACHE_SHUT_DBUS1_V << CACHE_L1_DCACHE_SHUT_DBUS1_S)
-#define CACHE_L1_DCACHE_SHUT_DBUS1_V  0x00000001U
-#define CACHE_L1_DCACHE_SHUT_DBUS1_S  1
-/** CACHE_L1_DCACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DCACHE_SHUT_DBUS2    (BIT(2))
-#define CACHE_L1_DCACHE_SHUT_DBUS2_M  (CACHE_L1_DCACHE_SHUT_DBUS2_V << CACHE_L1_DCACHE_SHUT_DBUS2_S)
-#define CACHE_L1_DCACHE_SHUT_DBUS2_V  0x00000001U
-#define CACHE_L1_DCACHE_SHUT_DBUS2_S  2
-/** CACHE_L1_DCACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DCACHE_SHUT_DBUS3    (BIT(3))
-#define CACHE_L1_DCACHE_SHUT_DBUS3_M  (CACHE_L1_DCACHE_SHUT_DBUS3_V << CACHE_L1_DCACHE_SHUT_DBUS3_S)
-#define CACHE_L1_DCACHE_SHUT_DBUS3_V  0x00000001U
-#define CACHE_L1_DCACHE_SHUT_DBUS3_S  3
-/** CACHE_L1_DCACHE_SHUT_DMA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable
- */
-#define CACHE_L1_DCACHE_SHUT_DMA    (BIT(4))
-#define CACHE_L1_DCACHE_SHUT_DMA_M  (CACHE_L1_DCACHE_SHUT_DMA_V << CACHE_L1_DCACHE_SHUT_DMA_S)
-#define CACHE_L1_DCACHE_SHUT_DMA_V  0x00000001U
-#define CACHE_L1_DCACHE_SHUT_DMA_S  4
-
-/** CACHE_L1_BYPASS_CACHE_CONF_REG register
- *  Bypass Cache configure register
- */
-#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
-/** CACHE_BYPASS_L1_ICACHE0_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
-#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
-#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
-/** CACHE_BYPASS_L1_ICACHE1_EN : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
-#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
-#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
-/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
-#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
-#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
-/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
-#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
-#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
-/** CACHE_BYPASS_L1_DCACHE_EN : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
-#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
-#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
-#define CACHE_BYPASS_L1_DCACHE_EN_S  4
-
-/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
- *  L1 Cache atomic feature configure register
- */
-#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
-/** CACHE_L1_DCACHE_ATOMIC_EN : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable atomic feature on L1-DCache when multiple cores access
- *  L1-DCache.  1: disable, 1: enable.
- */
-#define CACHE_L1_DCACHE_ATOMIC_EN    (BIT(0))
-#define CACHE_L1_DCACHE_ATOMIC_EN_M  (CACHE_L1_DCACHE_ATOMIC_EN_V << CACHE_L1_DCACHE_ATOMIC_EN_S)
-#define CACHE_L1_DCACHE_ATOMIC_EN_V  0x00000001U
-#define CACHE_L1_DCACHE_ATOMIC_EN_S  0
-
-/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
- *  L1 instruction Cache CacheSize mode configure register
- */
-#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
-/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_256    (BIT(0))
-#define CACHE_L1_ICACHE_CACHESIZE_256_M  (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S)
-#define CACHE_L1_ICACHE_CACHESIZE_256_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_256_S  0
-/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_512    (BIT(1))
-#define CACHE_L1_ICACHE_CACHESIZE_512_M  (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S)
-#define CACHE_L1_ICACHE_CACHESIZE_512_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_512_S  1
-/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(2))
-#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_1K_S  2
-/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(3))
-#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_2K_S  3
-/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(4))
-#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_4K_S  4
-/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(5))
-#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_8K_S  5
-/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 1;
- *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(6))
-#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_16K_S  6
-/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(7))
-#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_32K_S  7
-/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(8))
-#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_64K_S  8
-/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(9))
-#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_128K_S  9
-/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(10))
-#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_256K_S  10
-/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(11))
-#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_512K_S  11
-/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
- *  and all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(12))
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  12
-
-/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
- *  L1 instruction Cache BlockSize mode configure register
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
-/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
-/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
-/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
-/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
- *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
-/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
-/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L1_DCACHE_CACHESIZE_CONF_REG register
- *  L1 data Cache CacheSize mode configure register
- */
-#define CACHE_L1_DCACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
-/** CACHE_L1_DCACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_256    (BIT(0))
-#define CACHE_L1_DCACHE_CACHESIZE_256_M  (CACHE_L1_DCACHE_CACHESIZE_256_V << CACHE_L1_DCACHE_CACHESIZE_256_S)
-#define CACHE_L1_DCACHE_CACHESIZE_256_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_256_S  0
-/** CACHE_L1_DCACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_512    (BIT(1))
-#define CACHE_L1_DCACHE_CACHESIZE_512_M  (CACHE_L1_DCACHE_CACHESIZE_512_V << CACHE_L1_DCACHE_CACHESIZE_512_S)
-#define CACHE_L1_DCACHE_CACHESIZE_512_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_512_S  1
-/** CACHE_L1_DCACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_1K    (BIT(2))
-#define CACHE_L1_DCACHE_CACHESIZE_1K_M  (CACHE_L1_DCACHE_CACHESIZE_1K_V << CACHE_L1_DCACHE_CACHESIZE_1K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_1K_S  2
-/** CACHE_L1_DCACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_2K    (BIT(3))
-#define CACHE_L1_DCACHE_CACHESIZE_2K_M  (CACHE_L1_DCACHE_CACHESIZE_2K_V << CACHE_L1_DCACHE_CACHESIZE_2K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_2K_S  3
-/** CACHE_L1_DCACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_4K    (BIT(4))
-#define CACHE_L1_DCACHE_CACHESIZE_4K_M  (CACHE_L1_DCACHE_CACHESIZE_4K_V << CACHE_L1_DCACHE_CACHESIZE_4K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_4K_S  4
-/** CACHE_L1_DCACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_8K    (BIT(5))
-#define CACHE_L1_DCACHE_CACHESIZE_8K_M  (CACHE_L1_DCACHE_CACHESIZE_8K_V << CACHE_L1_DCACHE_CACHESIZE_8K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_8K_S  5
-/** CACHE_L1_DCACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_16K    (BIT(6))
-#define CACHE_L1_DCACHE_CACHESIZE_16K_M  (CACHE_L1_DCACHE_CACHESIZE_16K_V << CACHE_L1_DCACHE_CACHESIZE_16K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_16K_S  6
-/** CACHE_L1_DCACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_32K    (BIT(7))
-#define CACHE_L1_DCACHE_CACHESIZE_32K_M  (CACHE_L1_DCACHE_CACHESIZE_32K_V << CACHE_L1_DCACHE_CACHESIZE_32K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_32K_S  7
-/** CACHE_L1_DCACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 1;
- *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_64K    (BIT(8))
-#define CACHE_L1_DCACHE_CACHESIZE_64K_M  (CACHE_L1_DCACHE_CACHESIZE_64K_V << CACHE_L1_DCACHE_CACHESIZE_64K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_64K_S  8
-/** CACHE_L1_DCACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_128K    (BIT(9))
-#define CACHE_L1_DCACHE_CACHESIZE_128K_M  (CACHE_L1_DCACHE_CACHESIZE_128K_V << CACHE_L1_DCACHE_CACHESIZE_128K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_128K_S  9
-/** CACHE_L1_DCACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_256K    (BIT(10))
-#define CACHE_L1_DCACHE_CACHESIZE_256K_M  (CACHE_L1_DCACHE_CACHESIZE_256K_V << CACHE_L1_DCACHE_CACHESIZE_256K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_256K_S  10
-/** CACHE_L1_DCACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_512K    (BIT(11))
-#define CACHE_L1_DCACHE_CACHESIZE_512K_M  (CACHE_L1_DCACHE_CACHESIZE_512K_V << CACHE_L1_DCACHE_CACHESIZE_512K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_512K_S  11
-/** CACHE_L1_DCACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
- *  and all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_CACHESIZE_1024K    (BIT(12))
-#define CACHE_L1_DCACHE_CACHESIZE_1024K_M  (CACHE_L1_DCACHE_CACHESIZE_1024K_V << CACHE_L1_DCACHE_CACHESIZE_1024K_S)
-#define CACHE_L1_DCACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L1_DCACHE_CACHESIZE_1024K_S  12
-
-/** CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG register
- *  L1 data Cache BlockSize mode configure register
- */
-#define CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
-/** CACHE_L1_DCACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L1_DCACHE_BLOCKSIZE_8_M  (CACHE_L1_DCACHE_BLOCKSIZE_8_V << CACHE_L1_DCACHE_BLOCKSIZE_8_S)
-#define CACHE_L1_DCACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L1_DCACHE_BLOCKSIZE_8_S  0
-/** CACHE_L1_DCACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L1_DCACHE_BLOCKSIZE_16_M  (CACHE_L1_DCACHE_BLOCKSIZE_16_V << CACHE_L1_DCACHE_BLOCKSIZE_16_S)
-#define CACHE_L1_DCACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L1_DCACHE_BLOCKSIZE_16_S  1
-/** CACHE_L1_DCACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L1_DCACHE_BLOCKSIZE_32_M  (CACHE_L1_DCACHE_BLOCKSIZE_32_V << CACHE_L1_DCACHE_BLOCKSIZE_32_S)
-#define CACHE_L1_DCACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L1_DCACHE_BLOCKSIZE_32_S  2
-/** CACHE_L1_DCACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
- *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L1_DCACHE_BLOCKSIZE_64_M  (CACHE_L1_DCACHE_BLOCKSIZE_64_V << CACHE_L1_DCACHE_BLOCKSIZE_64_S)
-#define CACHE_L1_DCACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L1_DCACHE_BLOCKSIZE_64_S  3
-/** CACHE_L1_DCACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L1_DCACHE_BLOCKSIZE_128_M  (CACHE_L1_DCACHE_BLOCKSIZE_128_V << CACHE_L1_DCACHE_BLOCKSIZE_128_S)
-#define CACHE_L1_DCACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L1_DCACHE_BLOCKSIZE_128_S  4
-/** CACHE_L1_DCACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L1_DCACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L1_DCACHE_BLOCKSIZE_256_M  (CACHE_L1_DCACHE_BLOCKSIZE_256_V << CACHE_L1_DCACHE_BLOCKSIZE_256_S)
-#define CACHE_L1_DCACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L1_DCACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
-/** CACHE_L1_ICACHE0_WRAP : R/W; bitpos: [0]; default: 0;
- *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
- */
-#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
-#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
-#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE0_WRAP_S  0
-/** CACHE_L1_ICACHE1_WRAP : R/W; bitpos: [1]; default: 0;
- *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
- */
-#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
-#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
-#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE1_WRAP_S  1
-/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
-#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
-#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE2_WRAP_S  2
-/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
-#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
-#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
-#define CACHE_L1_ICACHE3_WRAP_S  3
-/** CACHE_L1_DCACHE_WRAP : R/W; bitpos: [4]; default: 0;
- *  Set this bit as 1 to enable L1-DCache wrap around mode.
- */
-#define CACHE_L1_DCACHE_WRAP    (BIT(4))
-#define CACHE_L1_DCACHE_WRAP_M  (CACHE_L1_DCACHE_WRAP_V << CACHE_L1_DCACHE_WRAP_S)
-#define CACHE_L1_DCACHE_WRAP_V  0x00000001U
-#define CACHE_L1_DCACHE_WRAP_S  4
-
-/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register
- *  Cache tag memory power control register
- */
-#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
-/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
- *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON    (BIT(0))
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S  0
-/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
- *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD    (BIT(1))
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S  1
-/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
- *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU    (BIT(2))
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S  2
-/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON : R/W; bitpos: [4]; default: 1;
- *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON    (BIT(4))
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S  4
-/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
- *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD    (BIT(5))
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S  5
-/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1;
- *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU    (BIT(6))
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S  6
-/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON    (BIT(8))
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S  8
-/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD    (BIT(9))
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S  9
-/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU    (BIT(10))
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S  10
-/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON    (BIT(12))
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S  12
-/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD    (BIT(13))
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S  13
-/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU    (BIT(14))
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S  14
-/** CACHE_L1_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
- *  The bit is used to close clock gating of  L1-DCache tag memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON    (BIT(16))
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_S)
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_S  16
-/** CACHE_L1_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
- *  The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD    (BIT(17))
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_S)
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_S  17
-/** CACHE_L1_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
- *  The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU    (BIT(18))
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_S)
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_S  18
-
-/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register
- *  Cache data memory power control register
- */
-#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
-/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
- *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON    (BIT(0))
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S  0
-/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
- *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD    (BIT(1))
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S  1
-/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
- *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU    (BIT(2))
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S  2
-/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON : R/W; bitpos: [4]; default: 1;
- *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON    (BIT(4))
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S  4
-/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
- *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD    (BIT(5))
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S  5
-/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1;
- *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU    (BIT(6))
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S  6
-/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON    (BIT(8))
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S  8
-/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD    (BIT(9))
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S  9
-/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU    (BIT(10))
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S  10
-/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON    (BIT(12))
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S  12
-/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD    (BIT(13))
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S  13
-/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU    (BIT(14))
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S  14
-/** CACHE_L1_DCACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
- *  The bit is used to close clock gating of  L1-DCache data memory. 1: close gating,
- *  0: open clock gating.
- */
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON    (BIT(16))
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_S)
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_S  16
-/** CACHE_L1_DCACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
- *  The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD    (BIT(17))
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_S)
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_S  17
-/** CACHE_L1_DCACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
- *  The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU    (BIT(18))
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_S)
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_S  18
-
-/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
- *  Cache Freeze control register
- */
-#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c)
-/** CACHE_L1_ICACHE0_FREEZE_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
- *  software.
- */
-#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
-#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
-/** CACHE_L1_ICACHE0_FREEZE_MODE : R/W; bitpos: [1]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
-#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
-/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
-#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
-/** CACHE_L1_ICACHE1_FREEZE_EN : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
- *  software.
- */
-#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
-#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
-/** CACHE_L1_ICACHE1_FREEZE_MODE : R/W; bitpos: [5]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
-#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
-/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
-#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
-/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
-#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
-/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
-#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
-/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
-#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
-/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
-#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
-/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
-#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
-#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
-/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
-#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
-#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
-/** CACHE_L1_DCACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
- *  The bit is used to enable freeze operation on L1-DCache. It can be cleared by
- *  software.
- */
-#define CACHE_L1_DCACHE_FREEZE_EN    (BIT(16))
-#define CACHE_L1_DCACHE_FREEZE_EN_M  (CACHE_L1_DCACHE_FREEZE_EN_V << CACHE_L1_DCACHE_FREEZE_EN_S)
-#define CACHE_L1_DCACHE_FREEZE_EN_V  0x00000001U
-#define CACHE_L1_DCACHE_FREEZE_EN_S  16
-/** CACHE_L1_DCACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
- *  The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L1_DCACHE_FREEZE_MODE    (BIT(17))
-#define CACHE_L1_DCACHE_FREEZE_MODE_M  (CACHE_L1_DCACHE_FREEZE_MODE_V << CACHE_L1_DCACHE_FREEZE_MODE_S)
-#define CACHE_L1_DCACHE_FREEZE_MODE_V  0x00000001U
-#define CACHE_L1_DCACHE_FREEZE_MODE_S  17
-/** CACHE_L1_DCACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
- *  The bit is used to indicate whether freeze operation on L1-DCache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_DCACHE_FREEZE_DONE    (BIT(18))
-#define CACHE_L1_DCACHE_FREEZE_DONE_M  (CACHE_L1_DCACHE_FREEZE_DONE_V << CACHE_L1_DCACHE_FREEZE_DONE_S)
-#define CACHE_L1_DCACHE_FREEZE_DONE_V  0x00000001U
-#define CACHE_L1_DCACHE_FREEZE_DONE_S  18
-
-/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
- *  Cache data memory access configure register
- */
-#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
-/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
-/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : R/W; bitpos: [1]; default: 1;
- *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
- *  1: enable.
- */
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
-/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : R/W; bitpos: [4]; default: 1;
- *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
-/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : R/W; bitpos: [5]; default: 1;
- *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
- *  1: enable.
- */
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
-/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
-/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
-/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
-/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
-/** CACHE_L1_DCACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
- *  The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_DCACHE_DATA_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_M  (CACHE_L1_DCACHE_DATA_MEM_RD_EN_V << CACHE_L1_DCACHE_DATA_MEM_RD_EN_S)
-#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_S  16
-/** CACHE_L1_DCACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
- *  The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_DCACHE_DATA_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_M  (CACHE_L1_DCACHE_DATA_MEM_WR_EN_V << CACHE_L1_DCACHE_DATA_MEM_WR_EN_S)
-#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_S  17
-
-/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
- *  Cache tag memory access configure register
- */
-#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34)
-/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
-/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : R/W; bitpos: [1]; default: 1;
- *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
-/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : R/W; bitpos: [4]; default: 1;
- *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
-/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : R/W; bitpos: [5]; default: 1;
- *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
-/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
-/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
-/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
-/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
-/** CACHE_L1_DCACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
- *  The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_DCACHE_TAG_MEM_RD_EN    (BIT(16))
-#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_M  (CACHE_L1_DCACHE_TAG_MEM_RD_EN_V << CACHE_L1_DCACHE_TAG_MEM_RD_EN_S)
-#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_S  16
-/** CACHE_L1_DCACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
- *  The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L1_DCACHE_TAG_MEM_WR_EN    (BIT(17))
-#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_M  (CACHE_L1_DCACHE_TAG_MEM_WR_EN_V << CACHE_L1_DCACHE_TAG_MEM_WR_EN_S)
-#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_S  17
-
-/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
- *  L1 instruction Cache 0 prelock configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x38)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE0_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 prelock.
- */
-#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 0 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x3c)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-ICache0, which should be used together with
- *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 0 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x40)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-ICache0, which should be used together with
- *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 0 prelock section size configure register
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x44)
-/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
- *  L1 instruction Cache 1 prelock configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x48)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE1_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 prelock.
- */
-#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 1 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x4c)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-ICache1, which should be used together with
- *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 1 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x50)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-ICache1, which should be used together with
- *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 1 prelock section size configure register
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x54)
-/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
- *  L1 instruction Cache 2 prelock configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x58)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 prelock.
- */
-#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 2 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x5c)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-ICache2, which should be used together with
- *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 2 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x60)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-ICache2, which should be used together with
- *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 2 prelock section size configure register
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x64)
-/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
- *  L1 instruction Cache 3 prelock configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x68)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 prelock.
- */
-#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
- *  L1 instruction Cache 3 prelock section0 address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x6c)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-ICache3, which should be used together with
- *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
- *  L1 instruction Cache 3 prelock section1 address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x70)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-ICache3, which should be used together with
- *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
- *  L1 instruction Cache 3 prelock section size configure register
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x74)
-/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L1_DCACHE_PRELOCK_CONF_REG register
- *  L1 data Cache prelock configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78)
-/** CACHE_L1_DCACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L1-DCache.
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S)
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S  0
-/** CACHE_L1_DCACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L1-DCache.
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S)
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S  1
-/** CACHE_L1_DCACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l1 dcache prelock.
- */
-#define CACHE_L1_DCACHE_PRELOCK_RGID    0x0000000FU
-#define CACHE_L1_DCACHE_PRELOCK_RGID_M  (CACHE_L1_DCACHE_PRELOCK_RGID_V << CACHE_L1_DCACHE_PRELOCK_RGID_S)
-#define CACHE_L1_DCACHE_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L1_DCACHE_PRELOCK_RGID_S  2
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG register
- *  L1 data Cache prelock section0 address configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
-/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L1-DCache, which should be used together with
- *  L1_DCACHE_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
- *  L1 data Cache prelock section1 address configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80)
-/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L1-DCache, which should be used together with
- *  L1_DCACHE_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
- *  L1 data Cache prelock section size configure register
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84)
-/** CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
-#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
-#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_LOCK_CTRL_REG register
- *  Lock-class (manual lock) operation control register
- */
-#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88)
-/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable lock operation. It will be cleared by hardware after lock
- *  operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive,
- *  that is, those bits can not be set to 1 at the same time. (2) lock operation can be
- *  applied on LL1-ICache, L1-DCache and L2-Cache.
- */
-#define CACHE_LOCK_ENA    (BIT(0))
-#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
-#define CACHE_LOCK_ENA_V  0x00000001U
-#define CACHE_LOCK_ENA_S  0
-/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
- *  The bit is used to enable unlock operation. It will be cleared by hardware after
- *  unlock operation done. Note that (1) this bit and lock_ena bit are mutually
- *  exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock
- *  operation can be applied on L1-ICache, L1-DCache and L2-Cache.
- */
-#define CACHE_UNLOCK_ENA    (BIT(1))
-#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
-#define CACHE_UNLOCK_ENA_V  0x00000001U
-#define CACHE_UNLOCK_ENA_S  1
-/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
- *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
- *  not finished. 1: finished.
- */
-#define CACHE_LOCK_DONE    (BIT(2))
-#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
-#define CACHE_LOCK_DONE_V  0x00000001U
-#define CACHE_LOCK_DONE_S  2
-/** CACHE_LOCK_RGID : R/W; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of cache lock/unlock.
- */
-#define CACHE_LOCK_RGID    0x0000000FU
-#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
-#define CACHE_LOCK_RGID_V  0x0000000FU
-#define CACHE_LOCK_RGID_S  3
-
-/** CACHE_LOCK_MAP_REG register
- *  Lock (manual lock) map configure register
- */
-#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c)
-/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
- *  Those bits are used to indicate which caches in the two-level cache structure will
- *  apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]:
- *  L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
- */
-#define CACHE_LOCK_MAP    0x0000003FU
-#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
-#define CACHE_LOCK_MAP_V  0x0000003FU
-#define CACHE_LOCK_MAP_S  0
-
-/** CACHE_LOCK_ADDR_REG register
- *  Lock (manual lock) address configure register
- */
-#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90)
-/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the lock/unlock
- *  operation, which should be used together with CACHE_LOCK_SIZE_REG
- */
-#define CACHE_LOCK_ADDR    0xFFFFFFFFU
-#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
-#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
-#define CACHE_LOCK_ADDR_S  0
-
-/** CACHE_LOCK_SIZE_REG register
- *  Lock (manual lock) size configure register
- */
-#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94)
-/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
- *  Those bits are used to configure the size of the lock/unlock operation, which
- *  should be used together with CACHE_LOCK_ADDR_REG
- */
-#define CACHE_LOCK_SIZE    0x0000FFFFU
-#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
-#define CACHE_LOCK_SIZE_V  0x0000FFFFU
-#define CACHE_LOCK_SIZE_S  0
-
-/** CACHE_SYNC_CTRL_REG register
- *  Sync-class operation control register
- */
-#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98)
-/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
- *  The bit is used to enable invalidate operation. It will be cleared by hardware
- *  after invalidate operation done. Note that this bit and the other sync-bits
- *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
- *  is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_INVALIDATE_ENA    (BIT(0))
-#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
-#define CACHE_INVALIDATE_ENA_V  0x00000001U
-#define CACHE_INVALIDATE_ENA_S  0
-/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
- *  The bit is used to enable clean operation. It will be cleared by hardware after
- *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
- *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
- *  bits can not be set to 1 at the same time.
- */
-#define CACHE_CLEAN_ENA    (BIT(1))
-#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
-#define CACHE_CLEAN_ENA_V  0x00000001U
-#define CACHE_CLEAN_ENA_S  1
-/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
- *  The bit is used to enable writeback operation. It will be cleared by hardware after
- *  writeback operation done. Note that this bit and the other sync-bits
- *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
- *  is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_WRITEBACK_ENA    (BIT(2))
-#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
-#define CACHE_WRITEBACK_ENA_V  0x00000001U
-#define CACHE_WRITEBACK_ENA_S  2
-/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
- *  The bit is used to enable writeback-invalidate operation. It will be cleared by
- *  hardware after writeback-invalidate operation done. Note that this bit and the
- *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
- *  that is, those bits can not be set to 1 at the same time.
- */
-#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
-#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
-#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
-#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
-/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
- *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
- *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
- */
-#define CACHE_SYNC_DONE    (BIT(4))
-#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
-#define CACHE_SYNC_DONE_V  0x00000001U
-#define CACHE_SYNC_DONE_S  4
-/** CACHE_SYNC_RGID : R/W; bitpos: [8:5]; default: 0;
- *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
- *  writeback, writeback_invalidate)
- */
-#define CACHE_SYNC_RGID    0x0000000FU
-#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
-#define CACHE_SYNC_RGID_V  0x0000000FU
-#define CACHE_SYNC_RGID_S  5
-
-/** CACHE_SYNC_MAP_REG register
- *  Sync map configure register
- */
-#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c)
-/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 31;
- *  Those bits are used to indicate which caches in the two-level cache structure will
- *  apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]:
- *  L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
- */
-#define CACHE_SYNC_MAP    0x0000003FU
-#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
-#define CACHE_SYNC_MAP_V  0x0000003FU
-#define CACHE_SYNC_MAP_S  0
-
-/** CACHE_SYNC_ADDR_REG register
- *  Sync address configure register
- */
-#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0)
-/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the sync operation,
- *  which should be used together with CACHE_SYNC_SIZE_REG
- */
-#define CACHE_SYNC_ADDR    0xFFFFFFFFU
-#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
-#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
-#define CACHE_SYNC_ADDR_S  0
-
-/** CACHE_SYNC_SIZE_REG register
- *  Sync size configure register
- */
-#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4)
-/** CACHE_SYNC_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the sync operation, which should be
- *  used together with CACHE_SYNC_ADDR_REG
- */
-#define CACHE_SYNC_SIZE    0x0FFFFFFFU
-#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
-#define CACHE_SYNC_SIZE_V  0x0FFFFFFFU
-#define CACHE_SYNC_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 0 preload-operation control register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa8)
-/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE0_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE0_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 preload.
- */
-#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 0 preload address configure register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xac)
-/** CACHE_L1_ICACHE0_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 0 preload size configure register
- */
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb0)
-/** CACHE_L1_ICACHE0_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 1 preload-operation control register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb4)
-/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE1_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE1_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 preload.
- */
-#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 1 preload address configure register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb8)
-/** CACHE_L1_ICACHE1_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 1 preload size configure register
- */
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xbc)
-/** CACHE_L1_ICACHE1_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 2 preload-operation control register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc0)
-/** CACHE_L1_ICACHE2_PRELOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 preload.
- */
-#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 2 preload address configure register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc4)
-/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 2 preload size configure register
- */
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc8)
-/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
- *  L1 instruction Cache 3 preload-operation control register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xcc)
-/** CACHE_L1_ICACHE3_PRELOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
-/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
-/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
-/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 preload.
- */
-#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
-
-/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
- *  L1 instruction Cache 3 preload address configure register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd0)
-/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
- *  L1 instruction Cache 3 preload size configure register
- */
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd4)
-/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_DCACHE_PRELOAD_CTRL_REG register
- *  L1 data Cache  preload-operation control register
- */
-#define CACHE_L1_DCACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8)
-/** CACHE_L1_DCACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L1-DCache. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L1_DCACHE_PRELOAD_ENA    (BIT(0))
-#define CACHE_L1_DCACHE_PRELOAD_ENA_M  (CACHE_L1_DCACHE_PRELOAD_ENA_V << CACHE_L1_DCACHE_PRELOAD_ENA_S)
-#define CACHE_L1_DCACHE_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_PRELOAD_ENA_S  0
-/** CACHE_L1_DCACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L1_DCACHE_PRELOAD_DONE    (BIT(1))
-#define CACHE_L1_DCACHE_PRELOAD_DONE_M  (CACHE_L1_DCACHE_PRELOAD_DONE_V << CACHE_L1_DCACHE_PRELOAD_DONE_S)
-#define CACHE_L1_DCACHE_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L1_DCACHE_PRELOAD_DONE_S  1
-/** CACHE_L1_DCACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L1_DCACHE_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L1_DCACHE_PRELOAD_ORDER_M  (CACHE_L1_DCACHE_PRELOAD_ORDER_V << CACHE_L1_DCACHE_PRELOAD_ORDER_S)
-#define CACHE_L1_DCACHE_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L1_DCACHE_PRELOAD_ORDER_S  2
-/** CACHE_L1_DCACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l1 dcache preload.
- */
-#define CACHE_L1_DCACHE_PRELOAD_RGID    0x0000000FU
-#define CACHE_L1_DCACHE_PRELOAD_RGID_M  (CACHE_L1_DCACHE_PRELOAD_RGID_V << CACHE_L1_DCACHE_PRELOAD_RGID_S)
-#define CACHE_L1_DCACHE_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L1_DCACHE_PRELOAD_RGID_S  3
-
-/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
- *  L1 data Cache  preload address configure register
- */
-#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc)
-/** CACHE_L1_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on L1-DCache,
- *  which should be used together with L1_DCACHE_PRELOAD_SIZE_REG
- */
-#define CACHE_L1_DCACHE_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L1_DCACHE_PRELOAD_ADDR_M  (CACHE_L1_DCACHE_PRELOAD_ADDR_V << CACHE_L1_DCACHE_PRELOAD_ADDR_S)
-#define CACHE_L1_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_DCACHE_PRELOAD_ADDR_S  0
-
-/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
- *  L1 data Cache  preload size configure register
- */
-#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0)
-/** CACHE_L1_DCACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG
- */
-#define CACHE_L1_DCACHE_PRELOAD_SIZE    0x00003FFFU
-#define CACHE_L1_DCACHE_PRELOAD_SIZE_M  (CACHE_L1_DCACHE_PRELOAD_SIZE_V << CACHE_L1_DCACHE_PRELOAD_SIZE_S)
-#define CACHE_L1_DCACHE_PRELOAD_SIZE_V  0x00003FFFU
-#define CACHE_L1_DCACHE_PRELOAD_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 0 autoload-operation control register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe4)
-/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache0 autoload.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 0 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe8)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 0 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xec)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 0 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xf0)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 0 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf4)
-/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache0. Note that it should be used together with
- *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 1 autoload-operation control register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf8)
-/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache1 autoload.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 1 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xfc)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 1 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x100)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 1 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x104)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 1 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x108)
-/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache1. Note that it should be used together with
- *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 2 autoload-operation control register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x10c)
-/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache2 autoload.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 2 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x110)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 2 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x114)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 2 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x118)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 2 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x11c)
-/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-ICache2. Note that it should be used together with
- *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
- *  L1 instruction Cache 3 autoload-operation control register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x120)
-/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
-/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
-/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
- *  The bit is used to set  the gid of l1 icache3 autoload.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 instruction Cache 3 autoload section 0 address configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x124)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 instruction Cache 3 autoload section 0 size configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x128)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 instruction Cache 3 autoload section 1 address configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x12c)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-ICache3. Note that it should be used together with
- *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 instruction Cache 3 autoload section 1 size configure register
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x130)
-/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG register
- *  L1 data Cache autoload-operation control register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134)
-/** CACHE_L1_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L1-DCache.  1: enable,
- *  0: disable.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L1_DCACHE_AUTOLOAD_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_ENA_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_AUTOLOAD_ENA_S  0
-/** CACHE_L1_DCACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L1-DCache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L1_DCACHE_AUTOLOAD_DONE_M  (CACHE_L1_DCACHE_AUTOLOAD_DONE_V << CACHE_L1_DCACHE_AUTOLOAD_DONE_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L1_DCACHE_AUTOLOAD_DONE_S  1
-/** CACHE_L1_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L1-DCache. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_M  (CACHE_L1_DCACHE_AUTOLOAD_ORDER_V << CACHE_L1_DCACHE_AUTOLOAD_ORDER_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_S  2
-/** CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L1-DCache.
- *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L1-DCache.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L1-DCache.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
- *  The bit is used to enable the third section for autoload operation on L1-DCache.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S  10
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
- *  The bit is used to enable the fourth section for autoload operation on L1-DCache.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S  11
-/** CACHE_L1_DCACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
- *  The bit is used to set  the gid of l1 dcache autoload.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L1_DCACHE_AUTOLOAD_RGID_M  (CACHE_L1_DCACHE_AUTOLOAD_RGID_V << CACHE_L1_DCACHE_AUTOLOAD_RGID_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L1_DCACHE_AUTOLOAD_RGID_S  12
-
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG register
- *  L1 data Cache autoload section 0 address configure register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138)
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L1-DCache. Note that it should be used together with
- *  L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG register
- *  L1 data Cache autoload section 0 size configure register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c)
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L1-DCache. Note that it should be used together with
- *  L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG register
- *  L1 data Cache autoload section 1 address configure register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140)
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L1-DCache. Note that it should be used together with
- *  L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG register
- *  L1 data Cache autoload section 1 size configure register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144)
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L1-DCache. Note that it should be used together with
- *  L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG register
- *  L1 data Cache autoload section 2 address configure register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x148)
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the third section for
- *  autoload operation on L1-DCache. Note that it should be used together with
- *  L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S  0
-
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG register
- *  L1 data Cache autoload section 2 size configure register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x14c)
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the third section for autoload
- *  operation on L1-DCache. Note that it should be used together with
- *  L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S  0
-
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG register
- *  L1 data Cache autoload section 1 address configure register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x150)
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the fourth section
- *  for autoload operation on L1-DCache. Note that it should be used together with
- *  L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S  0
-
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG register
- *  L1 data Cache autoload section 1 size configure register
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x154)
-/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the fourth section for autoload
- *  operation on L1-DCache. Note that it should be used together with
- *  L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S)
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
-#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S  0
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
- *  Cache Access Counter Interrupt enable register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158)
-/** CACHE_L1_IBUS0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-ICache0 due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
-/** CACHE_L1_IBUS1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-ICache1 due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
-/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
-/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
-#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
-/** CACHE_L1_DBUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-DCache due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS0_OVF_INT_ENA    (BIT(4))
-#define CACHE_L1_DBUS0_OVF_INT_ENA_M  (CACHE_L1_DBUS0_OVF_INT_ENA_V << CACHE_L1_DBUS0_OVF_INT_ENA_S)
-#define CACHE_L1_DBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS0_OVF_INT_ENA_S  4
-/** CACHE_L1_DBUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L1-DCache due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS1_OVF_INT_ENA    (BIT(5))
-#define CACHE_L1_DBUS1_OVF_INT_ENA_M  (CACHE_L1_DBUS1_OVF_INT_ENA_V << CACHE_L1_DBUS1_OVF_INT_ENA_S)
-#define CACHE_L1_DBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS1_OVF_INT_ENA_S  5
-/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
-#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
-/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
-#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
- *  Cache Access Counter Interrupt clear register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c)
-/** CACHE_L1_IBUS0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
- *  to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
-/** CACHE_L1_IBUS1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
- *  to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
-/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
-/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
-#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
-/** CACHE_L1_DBUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
- *  to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS0_OVF_INT_CLR    (BIT(4))
-#define CACHE_L1_DBUS0_OVF_INT_CLR_M  (CACHE_L1_DBUS0_OVF_INT_CLR_V << CACHE_L1_DBUS0_OVF_INT_CLR_S)
-#define CACHE_L1_DBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS0_OVF_INT_CLR_S  4
-/** CACHE_L1_DBUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
- *  to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS1_OVF_INT_CLR    (BIT(5))
-#define CACHE_L1_DBUS1_OVF_INT_CLR_M  (CACHE_L1_DBUS1_OVF_INT_CLR_V << CACHE_L1_DBUS1_OVF_INT_CLR_S)
-#define CACHE_L1_DBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS1_OVF_INT_CLR_S  5
-/** CACHE_L1_DBUS2_OVF_INT_CLR : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
-#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
-/** CACHE_L1_DBUS3_OVF_INT_CLR : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
-#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
- *  Cache Access Counter Interrupt raw register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160)
-/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
- *  due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
-/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
- *  due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
-/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
- *  due to bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
-/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
- *  due to bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
-#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
-/** CACHE_L1_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS0_OVF_INT_RAW    (BIT(4))
-#define CACHE_L1_DBUS0_OVF_INT_RAW_M  (CACHE_L1_DBUS0_OVF_INT_RAW_V << CACHE_L1_DBUS0_OVF_INT_RAW_S)
-#define CACHE_L1_DBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_DBUS0_OVF_INT_RAW_S  4
-/** CACHE_L1_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS1_OVF_INT_RAW    (BIT(5))
-#define CACHE_L1_DBUS1_OVF_INT_RAW_M  (CACHE_L1_DBUS1_OVF_INT_RAW_V << CACHE_L1_DBUS1_OVF_INT_RAW_S)
-#define CACHE_L1_DBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_DBUS1_OVF_INT_RAW_S  5
-/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
-#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
-/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
- *  due to bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
-#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
-
-/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
- *  Cache Access Counter Interrupt status register
- */
-#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164)
-/** CACHE_L1_IBUS0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-ICache0 due to bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
-#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
-#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
-/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-ICache1 due to bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
-#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
-#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
-/** CACHE_L1_IBUS2_OVF_INT_ST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
-#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
-#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
-/** CACHE_L1_IBUS3_OVF_INT_ST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
-#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
-#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
-/** CACHE_L1_DBUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-DCache due to bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS0_OVF_INT_ST    (BIT(4))
-#define CACHE_L1_DBUS0_OVF_INT_ST_M  (CACHE_L1_DBUS0_OVF_INT_ST_V << CACHE_L1_DBUS0_OVF_INT_ST_S)
-#define CACHE_L1_DBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_DBUS0_OVF_INT_ST_S  4
-/** CACHE_L1_DBUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L1-DCache due to bus1 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS1_OVF_INT_ST    (BIT(5))
-#define CACHE_L1_DBUS1_OVF_INT_ST_M  (CACHE_L1_DBUS1_OVF_INT_ST_V << CACHE_L1_DBUS1_OVF_INT_ST_S)
-#define CACHE_L1_DBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_DBUS1_OVF_INT_ST_S  5
-/** CACHE_L1_DBUS2_OVF_INT_ST : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
-#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
-#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
-/** CACHE_L1_DBUS3_OVF_INT_ST : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
-#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
-#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
-
-/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register
- *  Cache Access Fail Configuration register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x168)
-/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
- *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE    (BIT(0))
-#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S  0
-/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : R/W; bitpos: [1]; default: 0;
- *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE    (BIT(1))
-#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S  1
-/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE    (BIT(2))
-#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S  2
-/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : R/W; bitpos: [3]; default: 0;
- *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE    (BIT(3))
-#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S  3
-/** CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0;
- *  The bit is used to configure l1 dcache access fail check mode. 0: the access fail
- *  is not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE    (BIT(4))
-#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
- *  Cache Access Fail Interrupt enable register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x16c)
-/** CACHE_L1_ICACHE0_FAIL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
- *  cpu accesses L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
- *  cpu accesses L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
-/** CACHE_L1_DCACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
- *  cpu accesses L1-DCache.
- */
-#define CACHE_L1_DCACHE_FAIL_INT_ENA    (BIT(4))
-#define CACHE_L1_DCACHE_FAIL_INT_ENA_M  (CACHE_L1_DCACHE_FAIL_INT_ENA_V << CACHE_L1_DCACHE_FAIL_INT_ENA_S)
-#define CACHE_L1_DCACHE_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_FAIL_INT_ENA_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
- *  L1-Cache Access Fail Interrupt clear register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x170)
-/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
- *  cpu accesses L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
- *  cpu accesses L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
-/** CACHE_L1_DCACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
- *  cpu accesses L1-DCache.
- */
-#define CACHE_L1_DCACHE_FAIL_INT_CLR    (BIT(4))
-#define CACHE_L1_DCACHE_FAIL_INT_CLR_M  (CACHE_L1_DCACHE_FAIL_INT_CLR_V << CACHE_L1_DCACHE_FAIL_INT_CLR_S)
-#define CACHE_L1_DCACHE_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L1_DCACHE_FAIL_INT_CLR_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
- *  Cache Access Fail Interrupt raw register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x174)
-/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
-/** CACHE_L1_DCACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
- */
-#define CACHE_L1_DCACHE_FAIL_INT_RAW    (BIT(4))
-#define CACHE_L1_DCACHE_FAIL_INT_RAW_M  (CACHE_L1_DCACHE_FAIL_INT_RAW_V << CACHE_L1_DCACHE_FAIL_INT_RAW_S)
-#define CACHE_L1_DCACHE_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L1_DCACHE_FAIL_INT_RAW_S  4
-
-/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
- *  Cache Access Fail Interrupt status register
- */
-#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x178)
-/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
- *  to cpu accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
-/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
- *  to cpu accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
-/** CACHE_L1_ICACHE2_FAIL_INT_ST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
-/** CACHE_L1_ICACHE3_FAIL_INT_ST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
-/** CACHE_L1_DCACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
- *  to cpu accesses L1-DCache.
- */
-#define CACHE_L1_DCACHE_FAIL_INT_ST    (BIT(4))
-#define CACHE_L1_DCACHE_FAIL_INT_ST_M  (CACHE_L1_DCACHE_FAIL_INT_ST_V << CACHE_L1_DCACHE_FAIL_INT_ST_S)
-#define CACHE_L1_DCACHE_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L1_DCACHE_FAIL_INT_ST_S  4
-
-/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
- *  Cache Access Counter enable and clear register
- */
-#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x17c)
-/** CACHE_L1_IBUS0_CNT_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable ibus0 counter in L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
-#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
-#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS0_CNT_ENA_S  0
-/** CACHE_L1_IBUS1_CNT_ENA : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable ibus1 counter in L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
-#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
-#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS1_CNT_ENA_S  1
-/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
-#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
-#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS2_CNT_ENA_S  2
-/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
-#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
-#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L1_IBUS3_CNT_ENA_S  3
-/** CACHE_L1_DBUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable dbus0 counter in L1-DCache.
- */
-#define CACHE_L1_DBUS0_CNT_ENA    (BIT(4))
-#define CACHE_L1_DBUS0_CNT_ENA_M  (CACHE_L1_DBUS0_CNT_ENA_V << CACHE_L1_DBUS0_CNT_ENA_S)
-#define CACHE_L1_DBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS0_CNT_ENA_S  4
-/** CACHE_L1_DBUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable dbus1 counter in L1-DCache.
- */
-#define CACHE_L1_DBUS1_CNT_ENA    (BIT(5))
-#define CACHE_L1_DBUS1_CNT_ENA_M  (CACHE_L1_DBUS1_CNT_ENA_V << CACHE_L1_DBUS1_CNT_ENA_S)
-#define CACHE_L1_DBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS1_CNT_ENA_S  5
-/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
-#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
-#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS2_CNT_ENA_S  6
-/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
-#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
-#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L1_DBUS3_CNT_ENA_S  7
-/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0;
- *  The bit is used to clear ibus0 counter in L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
-#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
-#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS0_CNT_CLR_S  16
-/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0;
- *  The bit is used to clear ibus1 counter in L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
-#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
-#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS1_CNT_CLR_S  17
-/** CACHE_L1_IBUS2_CNT_CLR : HRO; bitpos: [18]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
-#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
-#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS2_CNT_CLR_S  18
-/** CACHE_L1_IBUS3_CNT_CLR : HRO; bitpos: [19]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
-#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
-#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L1_IBUS3_CNT_CLR_S  19
-/** CACHE_L1_DBUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
- *  The bit is used to clear dbus0 counter in L1-DCache.
- */
-#define CACHE_L1_DBUS0_CNT_CLR    (BIT(20))
-#define CACHE_L1_DBUS0_CNT_CLR_M  (CACHE_L1_DBUS0_CNT_CLR_V << CACHE_L1_DBUS0_CNT_CLR_S)
-#define CACHE_L1_DBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS0_CNT_CLR_S  20
-/** CACHE_L1_DBUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
- *  The bit is used to clear dbus1 counter in L1-DCache.
- */
-#define CACHE_L1_DBUS1_CNT_CLR    (BIT(21))
-#define CACHE_L1_DBUS1_CNT_CLR_M  (CACHE_L1_DBUS1_CNT_CLR_V << CACHE_L1_DBUS1_CNT_CLR_S)
-#define CACHE_L1_DBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS1_CNT_CLR_S  21
-/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
-#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
-#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS2_CNT_CLR_S  22
-/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
-#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
-#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L1_DBUS3_CNT_CLR_S  23
-
-/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
- *  L1-ICache bus0 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x180)
-/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
-#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
- *  L1-ICache bus0 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x184)
-/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
-#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus0 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x188)
-/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
- */
-#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L1-ICache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
-/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L1_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
- *  L1-ICache bus1 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x190)
-/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
-#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
- *  L1-ICache bus1 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x194)
-/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
-#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus1 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x198)
-/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
- */
-#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L1-ICache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
-/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L1_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
- *  L1-ICache bus2 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
-/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
-#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
- *  L1-ICache bus2 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
-/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
-#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus2 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
-/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
- */
-#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register
- *  L1-ICache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
-/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L1_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S)
-#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
- *  L1-ICache bus3 Hit-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
-/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
-#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_HIT_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
- *  L1-ICache bus3 Miss-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
-/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
-#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_MISS_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
- *  L1-ICache bus3 Conflict-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
-/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
- */
-#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
-#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register
- *  L1-ICache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
-/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-ICache accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L1_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S)
-#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_HIT_CNT_REG register
- *  L1-DCache bus0 Hit-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
-/** CACHE_L1_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS0_HIT_CNT_M  (CACHE_L1_DBUS0_HIT_CNT_V << CACHE_L1_DBUS0_HIT_CNT_S)
-#define CACHE_L1_DBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS0_HIT_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_MISS_CNT_REG register
- *  L1-DCache bus0 Miss-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
-/** CACHE_L1_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS0_MISS_CNT_M  (CACHE_L1_DBUS0_MISS_CNT_V << CACHE_L1_DBUS0_MISS_CNT_S)
-#define CACHE_L1_DBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS0_MISS_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG register
- *  L1-DCache bus0 Conflict-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
-/** CACHE_L1_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS0_CONFLICT_CNT_M  (CACHE_L1_DBUS0_CONFLICT_CNT_V << CACHE_L1_DBUS0_CONFLICT_CNT_S)
-#define CACHE_L1_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L1-DCache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
-/** CACHE_L1_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-DCache accesses L2-Cache due to
- *  bus0 accessing L1-DCache.
- */
-#define CACHE_L1_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS0_NXTLVL_RD_CNT_V << CACHE_L1_DBUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus0 WB-Access Counter register
- */
-#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
-/** CACHE_L1_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS0_NXTLVL_WR_CNT_V << CACHE_L1_DBUS0_NXTLVL_WR_CNT_S)
-#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_HIT_CNT_REG register
- *  L1-DCache bus1 Hit-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
-/** CACHE_L1_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus1 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_HIT_CNT_M  (CACHE_L1_DBUS1_HIT_CNT_V << CACHE_L1_DBUS1_HIT_CNT_S)
-#define CACHE_L1_DBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_HIT_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_MISS_CNT_REG register
- *  L1-DCache bus1 Miss-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
-/** CACHE_L1_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus1 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_MISS_CNT_M  (CACHE_L1_DBUS1_MISS_CNT_V << CACHE_L1_DBUS1_MISS_CNT_S)
-#define CACHE_L1_DBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_MISS_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG register
- *  L1-DCache bus1 Conflict-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
-/** CACHE_L1_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus1 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_CONFLICT_CNT_M  (CACHE_L1_DBUS1_CONFLICT_CNT_V << CACHE_L1_DBUS1_CONFLICT_CNT_S)
-#define CACHE_L1_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L1-DCache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
-/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-DCache accesses L2-Cache due to
- *  bus1 accessing L1-DCache.
- */
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus1 WB-Access Counter register
- */
-#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
-/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus1 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S)
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
- *  L1-DCache bus2 Hit-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
-/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
-#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_HIT_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
- *  L1-DCache bus2 Miss-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
-/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
-#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_MISS_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
- *  L1-DCache bus2 Conflict-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
-/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
-#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register
- *  L1-DCache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
-/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-DCache accesses L2-Cache due to
- *  bus2 accessing L1-DCache.
- */
-#define CACHE_L1_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S)
-#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus2 WB-Access Counter register
- */
-#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
-/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus2 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S)
-#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
- *  L1-DCache bus3 Hit-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1fc)
-/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
-#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_HIT_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
- *  L1-DCache bus3 Miss-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x200)
-/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
-#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_MISS_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
- *  L1-DCache bus3 Conflict-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x204)
-/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
-#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register
- *  L1-DCache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x208)
-/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L1-DCache accesses L2-Cache due to
- *  bus3 accessing L1-DCache.
- */
-#define CACHE_L1_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S)
-#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register
- *  L1-DCache bus3 WB-Access Counter register
- */
-#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x20c)
-/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when bus0 accesses L1-DCache.
- */
-#define CACHE_L1_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S)
-#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x210)
-/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
-#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ID_S  0
-/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x214)
-/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache0 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x218)
-/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
-#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ID_S  0
-/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x21c)
-/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache1 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x220)
-/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
-#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ID_S  0
-/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x224)
-/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache2 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
-
-/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
- *  L1-ICache0 Access Fail ID/attribution information register
- */
-#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x228)
-/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
-#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ID_S  0
-/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
-#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
-
-/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
- *  L1-ICache0 Access Fail Address information register
- */
-#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x22c)
-/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache3 accesses L1-ICache.
- */
-#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
-#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
-
-/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register
- *  L1-DCache Access Fail ID/attribution information register
- */
-#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x230)
-/** CACHE_L1_DCACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when cache accesses L1-DCache.
- */
-#define CACHE_L1_DCACHE_FAIL_ID    0x0000FFFFU
-#define CACHE_L1_DCACHE_FAIL_ID_M  (CACHE_L1_DCACHE_FAIL_ID_V << CACHE_L1_DCACHE_FAIL_ID_S)
-#define CACHE_L1_DCACHE_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L1_DCACHE_FAIL_ID_S  0
-/** CACHE_L1_DCACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when cache accesses L1-DCache.
- */
-#define CACHE_L1_DCACHE_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L1_DCACHE_FAIL_ATTR_M  (CACHE_L1_DCACHE_FAIL_ATTR_V << CACHE_L1_DCACHE_FAIL_ATTR_S)
-#define CACHE_L1_DCACHE_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L1_DCACHE_FAIL_ATTR_S  16
-
-/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
- *  L1-DCache Access Fail Address information register
- */
-#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x234)
-/** CACHE_L1_DCACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when cache accesses L1-DCache.
- */
-#define CACHE_L1_DCACHE_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L1_DCACHE_FAIL_ADDR_M  (CACHE_L1_DCACHE_FAIL_ADDR_V << CACHE_L1_DCACHE_FAIL_ADDR_S)
-#define CACHE_L1_DCACHE_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L1_DCACHE_FAIL_ADDR_S  0
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG register
- *  L1-Cache Access Fail Interrupt enable register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x238)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
-/** CACHE_L1_DCACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The bit is used to enable interrupt of L1-DCache preload-operation. If preload
- *  operation is done, interrupt occurs.
- */
-#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA    (BIT(4))
-#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V << CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S)
-#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S  4
-/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The bit is used to enable interrupt of Cache sync-operation done.
- */
-#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
-#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_ENA_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
-/** CACHE_L1_DCACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The bit is used to enable interrupt of L1-DCache preload-operation error.
- */
-#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA    (BIT(11))
-#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V << CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S)
-#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S  11
-/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The bit is used to enable interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
-#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_ENA_S  13
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG register
- *  Sync Preload operation Interrupt clear register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x23c)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-ICache0
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-ICache1
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
-/** CACHE_L1_DCACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L1-DCache
- *  preload-operation is done.
- */
-#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR    (BIT(4))
-#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V << CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S)
-#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S  4
-/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
- *  done.
- */
-#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
-#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
-#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_CLR_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
- *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
-/** CACHE_L1_DCACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
- *  The bit is used to clear interrupt of L1-DCache preload-operation error.
- */
-#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR    (BIT(11))
-#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V << CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S)
-#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S  11
-/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The bit is used to clear interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
-#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
-#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_CLR_S  13
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG register
- *  Sync Preload operation Interrupt raw register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x240)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
- *  done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
- *  done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
-/** CACHE_L1_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation is
- *  done.
- */
-#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW    (BIT(4))
-#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V << CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S)
-#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S  4
-/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
- */
-#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
-#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
-#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_RAW_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
- *  error occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
- *  error occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
-/** CACHE_L1_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation
- *  error occurs.
- */
-#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW    (BIT(11))
-#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V << CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S)
-#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S  11
-/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit of the interrupt that occurs only when Cache sync-operation error
- *  occurs.
- */
-#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
-#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
-#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_RAW_S  13
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG register
- *  L1-Cache Access Fail Interrupt status register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x244)
-/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
-/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
- *  preload-operation is done.
- */
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
-/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : RO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
-/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : RO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
-/** CACHE_L1_DCACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L1-DCache
- *  preload-operation is done.
- */
-#define CACHE_L1_DCACHE_PLD_DONE_INT_ST    (BIT(4))
-#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ST_V << CACHE_L1_DCACHE_PLD_DONE_INT_ST_S)
-#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_S  4
-/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when Cache
- *  sync-operation is done.
- */
-#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
-#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
-#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
-#define CACHE_SYNC_DONE_INT_ST_S  6
-/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
-/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : RO; bitpos: [8]; default: 0;
- *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
-/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : RO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
-/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : RO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
-/** CACHE_L1_DCACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
- *  The bit indicates the status of the interrupt of L1-DCache preload-operation error.
- */
-#define CACHE_L1_DCACHE_PLD_ERR_INT_ST    (BIT(11))
-#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ST_V << CACHE_L1_DCACHE_PLD_ERR_INT_ST_S)
-#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_S  11
-/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
- *  The bit indicates the status of the interrupt of Cache sync-operation error.
- */
-#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
-#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
-#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
-#define CACHE_SYNC_ERR_INT_ST_S  13
-
-/** CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG register
- *  Cache Sync/Preload Operation exception register
- */
-#define CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x248)
-/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
-/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
-/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
-/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
-/** CACHE_L1_DCACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
- *  The value 2 is Only available which means preload size is error in L1-DCache.
- */
-#define CACHE_L1_DCACHE_PLD_ERR_CODE    0x00000003U
-#define CACHE_L1_DCACHE_PLD_ERR_CODE_M  (CACHE_L1_DCACHE_PLD_ERR_CODE_V << CACHE_L1_DCACHE_PLD_ERR_CODE_S)
-#define CACHE_L1_DCACHE_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L1_DCACHE_PLD_ERR_CODE_S  8
-/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
- *  The values 0-2 are available which means sync map, command conflict and size are
- *  error in Cache System.
- */
-#define CACHE_SYNC_ERR_CODE    0x00000003U
-#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
-#define CACHE_SYNC_ERR_CODE_V  0x00000003U
-#define CACHE_SYNC_ERR_CODE_S  12
-
-/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
- *  Cache Sync Reset control register
- */
-#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c)
-/** CACHE_L1_ICACHE0_SYNC_RST : R/W; bitpos: [0]; default: 0;
- *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
-#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
-#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE0_SYNC_RST_S  0
-/** CACHE_L1_ICACHE1_SYNC_RST : R/W; bitpos: [1]; default: 0;
- *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
-#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
-#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE1_SYNC_RST_S  1
-/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
-#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
-#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE2_SYNC_RST_S  2
-/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
-#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
-#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
-#define CACHE_L1_ICACHE3_SYNC_RST_S  3
-/** CACHE_L1_DCACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
- *  set this bit to reset sync-logic inside L1-DCache. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L1_DCACHE_SYNC_RST    (BIT(4))
-#define CACHE_L1_DCACHE_SYNC_RST_M  (CACHE_L1_DCACHE_SYNC_RST_V << CACHE_L1_DCACHE_SYNC_RST_S)
-#define CACHE_L1_DCACHE_SYNC_RST_V  0x00000001U
-#define CACHE_L1_DCACHE_SYNC_RST_S  4
-
-/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
- *  Cache Preload Reset control register
- */
-#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x250)
-/** CACHE_L1_ICACHE0_PLD_RST : R/W; bitpos: [0]; default: 0;
- *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
-#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
-#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE0_PLD_RST_S  0
-/** CACHE_L1_ICACHE1_PLD_RST : R/W; bitpos: [1]; default: 0;
- *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
-#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
-#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE1_PLD_RST_S  1
-/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
-#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
-#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE2_PLD_RST_S  2
-/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
-#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
-#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
-#define CACHE_L1_ICACHE3_PLD_RST_S  3
-/** CACHE_L1_DCACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
- *  set this bit to reset preload-logic inside L1-DCache. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L1_DCACHE_PLD_RST    (BIT(4))
-#define CACHE_L1_DCACHE_PLD_RST_M  (CACHE_L1_DCACHE_PLD_RST_V << CACHE_L1_DCACHE_PLD_RST_S)
-#define CACHE_L1_DCACHE_PLD_RST_V  0x00000001U
-#define CACHE_L1_DCACHE_PLD_RST_S  4
-
-/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
- *  Cache Autoload buffer clear control register
- */
-#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x254)
-/** CACHE_L1_ICACHE0_ALD_BUF_CLR : R/W; bitpos: [0]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
- *  autoload will not work in L1-ICache0. This bit should not be active when autoload
- *  works in L1-ICache0.
- */
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
-/** CACHE_L1_ICACHE1_ALD_BUF_CLR : R/W; bitpos: [1]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
- *  autoload will not work in L1-ICache1. This bit should not be active when autoload
- *  works in L1-ICache1.
- */
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
-/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
-/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
-/** CACHE_L1_DCACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
- *  set this bit to clear autoload-buffer inside L1-DCache. If this bit is active,
- *  autoload will not work in L1-DCache. This bit should not be active when autoload
- *  works in L1-DCache.
- */
-#define CACHE_L1_DCACHE_ALD_BUF_CLR    (BIT(4))
-#define CACHE_L1_DCACHE_ALD_BUF_CLR_M  (CACHE_L1_DCACHE_ALD_BUF_CLR_V << CACHE_L1_DCACHE_ALD_BUF_CLR_S)
-#define CACHE_L1_DCACHE_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L1_DCACHE_ALD_BUF_CLR_S  4
-
-/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
- *  Unallocate request buffer clear registers
- */
-#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258)
-/** CACHE_L1_ICACHE0_UNALLOC_CLR : R/W; bitpos: [0]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
-/** CACHE_L1_ICACHE1_UNALLOC_CLR : R/W; bitpos: [1]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
-/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
-/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
-/** CACHE_L1_DCACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l1 dcache where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L1_DCACHE_UNALLOC_CLR    (BIT(4))
-#define CACHE_L1_DCACHE_UNALLOC_CLR_M  (CACHE_L1_DCACHE_UNALLOC_CLR_V << CACHE_L1_DCACHE_UNALLOC_CLR_S)
-#define CACHE_L1_DCACHE_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L1_DCACHE_UNALLOC_CLR_S  4
-
-/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
- *  Cache Tag and Data memory Object control register
- */
-#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x25c)
-/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0;
- *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
-#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
-/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0;
- *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
-#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
-/** CACHE_L1_ICACHE2_TAG_OBJECT : HRO; bitpos: [2]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
-#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
-/** CACHE_L1_ICACHE3_TAG_OBJECT : HRO; bitpos: [3]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
-#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
-#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
-/** CACHE_L1_DCACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
- *  Set this bit to set L1-DCache tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_DCACHE_TAG_OBJECT    (BIT(4))
-#define CACHE_L1_DCACHE_TAG_OBJECT_M  (CACHE_L1_DCACHE_TAG_OBJECT_V << CACHE_L1_DCACHE_TAG_OBJECT_S)
-#define CACHE_L1_DCACHE_TAG_OBJECT_V  0x00000001U
-#define CACHE_L1_DCACHE_TAG_OBJECT_S  4
-/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0;
- *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
- *  with the others fields inside this register.
- */
-#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
-#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
-/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0;
- *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
- *  with the others fields inside this register.
- */
-#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
-#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
-/** CACHE_L1_ICACHE2_MEM_OBJECT : HRO; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
-#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
-/** CACHE_L1_ICACHE3_MEM_OBJECT : HRO; bitpos: [9]; default: 0;
- *  Reserved
- */
-#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
-#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
-#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
-/** CACHE_L1_DCACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
- *  Set this bit to set L1-DCache data memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L1_DCACHE_MEM_OBJECT    (BIT(10))
-#define CACHE_L1_DCACHE_MEM_OBJECT_M  (CACHE_L1_DCACHE_MEM_OBJECT_V << CACHE_L1_DCACHE_MEM_OBJECT_S)
-#define CACHE_L1_DCACHE_MEM_OBJECT_V  0x00000001U
-#define CACHE_L1_DCACHE_MEM_OBJECT_S  10
-
-/** CACHE_L1_CACHE_WAY_OBJECT_REG register
- *  Cache Tag and Data memory way register
- */
-#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x260)
-/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
- *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
- *  way1, 2: way2, 3: way3, ?, 7: way7.
- */
-#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
-#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
-#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
-#define CACHE_L1_CACHE_WAY_OBJECT_S  0
-
-/** CACHE_L1_CACHE_VADDR_REG register
- *  Cache Vaddr register
- */
-#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x264)
-/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
- *  Those bits stores the virtual address which will decide where inside the specified
- *  tag memory object will be accessed.
- */
-#define CACHE_L1_CACHE_VADDR    0xFFFFFFFFU
-#define CACHE_L1_CACHE_VADDR_M  (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S)
-#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_VADDR_S  0
-
-/** CACHE_L1_CACHE_DEBUG_BUS_REG register
- *  Cache Tag/data memory content register
- */
-#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x268)
-/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 616;
- *  This is a constant place where we can write data to or read data from the tag/data
- *  memory on the specified cache.
- */
-#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
-#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
-#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
-#define CACHE_L1_CACHE_DEBUG_BUS_S  0
-
-/** CACHE_L2_CACHE_CTRL_REG register
- *  L2 Cache(L2-Cache) control register
- */
-#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x270)
-/** CACHE_L2_CACHE_SHUT_DMA : R/W; bitpos: [4]; default: 1;
- *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
- */
-#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
-#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
-#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
-#define CACHE_L2_CACHE_SHUT_DMA_S  4
-
-/** CACHE_L2_BYPASS_CACHE_CONF_REG register
- *  Bypass Cache configure register
- */
-#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x274)
-/** CACHE_BYPASS_L2_CACHE_EN : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
- */
-#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
-#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
-#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
-#define CACHE_BYPASS_L2_CACHE_EN_S  5
-
-/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
- *  L2 Cache CacheSize mode configure register
- */
-#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278)
-/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_256    (BIT(0))
-#define CACHE_L2_CACHE_CACHESIZE_256_M  (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S)
-#define CACHE_L2_CACHE_CACHESIZE_256_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_256_S  0
-/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_512    (BIT(1))
-#define CACHE_L2_CACHE_CACHESIZE_512_M  (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S)
-#define CACHE_L2_CACHE_CACHESIZE_512_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_512_S  1
-/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(2))
-#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
-#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_1K_S  2
-/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(3))
-#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
-#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_2K_S  3
-/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(4))
-#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
-#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_4K_S  4
-/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(5))
-#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
-#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_8K_S  5
-/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(6))
-#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
-#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_16K_S  6
-/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(7))
-#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
-#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_32K_S  7
-/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(8))
-#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
-#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_64K_S  8
-/** CACHE_L2_CACHE_CACHESIZE_128K : R/W; bitpos: [9]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(9))
-#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
-#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_128K_S  9
-/** CACHE_L2_CACHE_CACHESIZE_256K : R/W; bitpos: [10]; default: 1;
- *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(10))
-#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
-#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_256K_S  10
-/** CACHE_L2_CACHE_CACHESIZE_512K : R/W; bitpos: [11]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(11))
-#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
-#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_512K_S  11
-/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
- *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(12))
-#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
-#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
-#define CACHE_L2_CACHE_CACHESIZE_1024K_S  12
-
-/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
- *  L2 Cache BlockSize mode configure register
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x27c)
-/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
-#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
-/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
-#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
-/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
-#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
-/** CACHE_L2_CACHE_BLOCKSIZE_64 : R/W; bitpos: [3]; default: 1;
- *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
- *  other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
-#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
-/** CACHE_L2_CACHE_BLOCKSIZE_128 : R/W; bitpos: [4]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
-#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
-/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
- *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
- *  all other fields within this register is onehot.
- */
-#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
-#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
-#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
-#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
-
-/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
- *  Cache wrap around control register
- */
-#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x280)
-/** CACHE_L2_CACHE_WRAP : R/W; bitpos: [5]; default: 0;
- *  Set this bit as 1 to enable L2-Cache wrap around mode.
- */
-#define CACHE_L2_CACHE_WRAP    (BIT(5))
-#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
-#define CACHE_L2_CACHE_WRAP_V  0x00000001U
-#define CACHE_L2_CACHE_WRAP_S  5
-
-/** CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG register
- *  Cache tag memory power control register
- */
-#define CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x284)
-/** CACHE_L2_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [20]; default: 1;
- *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON    (BIT(20))
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S)
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S  20
-/** CACHE_L2_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [21]; default: 0;
- *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
- */
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD    (BIT(21))
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S)
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S  21
-/** CACHE_L2_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [22]; default: 1;
- *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU    (BIT(22))
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S)
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S  22
-
-/** CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG register
- *  Cache data memory power control register
- */
-#define CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x288)
-/** CACHE_L2_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [20]; default: 1;
- *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
- *  open clock gating.
- */
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON    (BIT(20))
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S)
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S  20
-/** CACHE_L2_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [21]; default: 0;
- *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
- *  down
- */
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD    (BIT(21))
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S)
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S  21
-/** CACHE_L2_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [22]; default: 1;
- *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
- */
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU    (BIT(22))
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S)
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S  22
-
-/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
- *  Cache Freeze control register
- */
-#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28c)
-/** CACHE_L2_CACHE_FREEZE_EN : R/W; bitpos: [20]; default: 0;
- *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
- *  software.
- */
-#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
-#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
-#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_EN_S  20
-/** CACHE_L2_CACHE_FREEZE_MODE : R/W; bitpos: [21]; default: 0;
- *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
- *  will not stuck. 1: a miss-access will stuck.
- */
-#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
-#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
-#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_MODE_S  21
-/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
- *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
-#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
-#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_FREEZE_DONE_S  22
-
-/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
- *  Cache data memory access configure register
- */
-#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x290)
-/** CACHE_L2_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [20]; default: 1;
- *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
-/** CACHE_L2_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [21]; default: 1;
- *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
-#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
-
-/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
- *  Cache tag memory access configure register
- */
-#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x294)
-/** CACHE_L2_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [20]; default: 1;
- *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
-/** CACHE_L2_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [21]; default: 1;
- *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
- *  enable.
- */
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
-
-/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
- *  L2 Cache prelock configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x298)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable the first section of prelock function on L2-Cache.
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
-/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
- *  The bit is used to enable the second section of prelock function on L2-Cache.
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
-/** CACHE_L2_CACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
- *  The bit is used to set  the gid of l2 cache prelock.
- */
-#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
-#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
-#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
-
-/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
- *  L2 Cache prelock section0 address configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x29c)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section of
- *  prelock on L2-Cache, which should be used together with
- *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
- *  L2 Cache prelock section1 address configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2a0)
-/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section of
- *  prelock on L2-Cache, which should be used together with
- *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
- *  L2 Cache prelock section size configure register
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x2a4)
-/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [15:0]; default: 65535;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
-/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [31:16]; default: 65535;
- *  Those bits are used to configure the size of the second section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
-
-/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
- *  L2 Cache preload-operation control register
- */
-#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a8)
-/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
- *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
- *  hardware automatically after preload operation is done.
- */
-#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
-#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
-#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
-/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether preload operation is finished or not. 0: not
- *  finished. 1: finished.
- */
-#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
-#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
-#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
-/** CACHE_L2_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
- *  descending.
- */
-#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
-#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
-#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
-#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
-/** CACHE_L2_CACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
- *  The bit is used to set  the gid of l2 cache preload.
- */
-#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
-#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
-#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
-
-/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
- *  L2 Cache preload address configure register
- */
-#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2ac)
-/** CACHE_L2_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of preload on L2-Cache,
- *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
- */
-#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
-#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
-
-/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
- *  L2 Cache preload size configure register
- */
-#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2b0)
-/** CACHE_L2_CACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0;
- *  Those bits are used to configure the size of the first section of prelock on
- *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
- */
-#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
-#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
-#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
- *  L2 Cache autoload-operation control register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2b4)
-/** CACHE_L2_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
- *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
- *  0: disable.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
-/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
- *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
- *  not. 0: not finished. 1: finished.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
-/** CACHE_L2_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
- *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
- *  ascending. 1: descending.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
-/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
- *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
- *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
-#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable the first section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable the second section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
- *  The bit is used to enable the third section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
- *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
-/** CACHE_L2_CACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
- *  The bit is used to set  the gid of l2 cache autoload.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
-#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
- *  L2 Cache autoload section 0 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the first section for
- *  autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
- *  L2 Cache autoload section 0 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the first section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
- *  L2 Cache autoload section 1 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the second section
- *  for autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
- *  L2 Cache autoload section 1 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the second section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
- *  L2 Cache autoload section 2 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the third section for
- *  autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
- *  L2 Cache autoload section 2 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the third section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
- *  L2 Cache autoload section 3 address configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2d0)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
- *  Those bits are used to configure the start virtual address of the fourth section
- *  for autoload operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
-
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
- *  L2 Cache autoload section 3 size configure register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2d4)
-/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
- *  Those bits are used to configure the size of the fourth section for autoload
- *  operation on L2-Cache. Note that it should be used together with
- *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
- */
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
-#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
- *  Cache Access Counter Interrupt enable register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d8)
-/** CACHE_L2_IBUS0_OVF_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
-/** CACHE_L2_IBUS1_OVF_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
-/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
-/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
-#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
-/** CACHE_L2_DBUS0_OVF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
-/** CACHE_L2_DBUS1_OVF_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The bit is used to enable interrupt of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
-/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
-/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
-#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
- *  Cache Access Counter Interrupt clear register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2dc)
-/** CACHE_L2_IBUS0_OVF_INT_CLR : WT; bitpos: [8]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
-/** CACHE_L2_IBUS1_OVF_INT_CLR : WT; bitpos: [9]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
-/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
-/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
-#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
-/** CACHE_L2_DBUS0_OVF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
-/** CACHE_L2_DBUS1_OVF_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
- *  to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
-/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
-/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
-#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
- *  Cache Access Counter Interrupt raw register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2e0)
-/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus0 accesses L2-ICache0.
- */
-#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
-/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus1 accesses L2-ICache1.
- */
-#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
-/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus2 accesses L2-ICache2.
- */
-#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
-/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus3 accesses L2-ICache3.
- */
-#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
-#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
-/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus0 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
-/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus1 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
-/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus2 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
-/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
- *  due to bus3 accesses L2-DCache.
- */
-#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
-#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
-
-/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
- *  Cache Access Counter Interrupt status register
- */
-#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2e4)
-/** CACHE_L2_IBUS0_OVF_INT_ST : RO; bitpos: [8]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
-#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
-#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
-/** CACHE_L2_IBUS1_OVF_INT_ST : RO; bitpos: [9]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
-#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
-#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
-/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
-#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
-#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
-/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
-#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
-#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
-/** CACHE_L2_DBUS0_OVF_INT_ST : RO; bitpos: [12]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus0 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
-#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
-#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
-/** CACHE_L2_DBUS1_OVF_INT_ST : RO; bitpos: [13]; default: 0;
- *  The bit indicates the interrupt status of one of counters overflow that occurs in
- *  L2-Cache due to bus1 accesses L2-Cache.
- */
-#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
-#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
-#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
-/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
-#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
-#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
-/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
-#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
-#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
-#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
-
-/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register
- *  Cache Access Fail Configuration register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e8)
-/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
- *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
- *  not propagated to the request, 1: the access fail is propagated to the request
- */
-#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE    (BIT(0))
-#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S)
-#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
-#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S  0
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
- *  Cache Access Fail Interrupt enable register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2ec)
-/** CACHE_L2_CACHE_FAIL_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
- *  l1 cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
-#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
- *  L1-Cache Access Fail Interrupt clear register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2f0)
-/** CACHE_L2_CACHE_FAIL_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
- *  cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
-#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
- *  Cache Access Fail Interrupt raw register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2f4)
-/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
-#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
-
-/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
- *  Cache Access Fail Interrupt status register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f8)
-/** CACHE_L2_CACHE_FAIL_INT_ST : RO; bitpos: [5]; default: 0;
- *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
- *  to l1 cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
-#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
-#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
-
-/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
- *  Cache Access Counter enable and clear register
- */
-#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2fc)
-/** CACHE_L2_IBUS0_CNT_ENA : R/W; bitpos: [8]; default: 0;
- *  The bit is used to enable ibus0 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
-#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
-#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS0_CNT_ENA_S  8
-/** CACHE_L2_IBUS1_CNT_ENA : R/W; bitpos: [9]; default: 0;
- *  The bit is used to enable ibus1 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
-#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
-#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS1_CNT_ENA_S  9
-/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
-#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
-#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS2_CNT_ENA_S  10
-/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
-#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
-#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L2_IBUS3_CNT_ENA_S  11
-/** CACHE_L2_DBUS0_CNT_ENA : R/W; bitpos: [12]; default: 0;
- *  The bit is used to enable dbus0 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
-#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
-#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS0_CNT_ENA_S  12
-/** CACHE_L2_DBUS1_CNT_ENA : R/W; bitpos: [13]; default: 0;
- *  The bit is used to enable dbus1 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
-#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
-#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS1_CNT_ENA_S  13
-/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
-#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
-#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS2_CNT_ENA_S  14
-/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
-#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
-#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
-#define CACHE_L2_DBUS3_CNT_ENA_S  15
-/** CACHE_L2_IBUS0_CNT_CLR : WT; bitpos: [24]; default: 0;
- *  The bit is used to clear ibus0 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
-#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
-#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS0_CNT_CLR_S  24
-/** CACHE_L2_IBUS1_CNT_CLR : WT; bitpos: [25]; default: 0;
- *  The bit is used to clear ibus1 counter in L2-Cache.
- */
-#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
-#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
-#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS1_CNT_CLR_S  25
-/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
-#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
-#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS2_CNT_CLR_S  26
-/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
-#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
-#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L2_IBUS3_CNT_CLR_S  27
-/** CACHE_L2_DBUS0_CNT_CLR : WT; bitpos: [28]; default: 0;
- *  The bit is used to clear dbus0 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
-#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
-#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS0_CNT_CLR_S  28
-/** CACHE_L2_DBUS1_CNT_CLR : WT; bitpos: [29]; default: 0;
- *  The bit is used to clear dbus1 counter in L2-Cache.
- */
-#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
-#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
-#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS1_CNT_CLR_S  29
-/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
-#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
-#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS2_CNT_CLR_S  30
-/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
- *  Reserved
- */
-#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
-#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
-#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
-#define CACHE_L2_DBUS3_CNT_CLR_S  31
-
-/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
-/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
-#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x304)
-/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
- *  bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
-#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
-/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache0 accesses
- *  L2-Cache due to bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
-/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
- */
-#define CACHE_L2_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
-/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
-#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x314)
-/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
- *  bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
-#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
-/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache1 accesses
- *  L2-Cache due to bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
-/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
- */
-#define CACHE_L2_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
-/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
-#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x324)
-/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
- *  bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
-#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
-/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache2 accesses
- *  L2-Cache due to bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
-/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
- */
-#define CACHE_L2_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S)
-#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
-/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
-#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_HIT_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x334)
-/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
- *  bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
-#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_MISS_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
-/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-ICache3 accesses
- *  L2-Cache due to bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
-#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
-/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
- */
-#define CACHE_L2_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S)
-#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
- *  L2-Cache bus0 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
-/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
-#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
- *  L2-Cache bus0 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x344)
-/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
-#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus0 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x348)
-/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus0 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
-/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S)
-#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register
- *  L2-Cache bus0 WB-Access Counter register
- */
-#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x350)
-/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when L1-DCache accesses L2-Cache due
- *  to bus0 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S)
-#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
- *  L2-Cache bus1 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x354)
-/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
-#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
- *  L2-Cache bus1 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x358)
-/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
-#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus1 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
-/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus1 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x360)
-/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S)
-#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register
- *  L2-Cache bus1 WB-Access Counter register
- */
-#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x364)
-/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when L1-DCache accesses L2-Cache due
- *  to bus1 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S)
-#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
- *  L2-Cache bus2 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x368)
-/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
-#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
- *  L2-Cache bus2 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x36c)
-/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
-#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus2 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x370)
-/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus2 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x374)
-/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S)
-#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register
- *  L2-Cache bus2 WB-Access Counter register
- */
-#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x378)
-/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when L1-DCache accesses L2-Cache due
- *  to bus2 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S)
-#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
- *  L2-Cache bus3 Hit-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x37c)
-/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of hits when L1-DCache accesses L2-Cache due to
- *  bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
-#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_HIT_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
- *  L2-Cache bus3 Miss-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x380)
-/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of missing when L1-DCache accesses L2-Cache due to
- *  bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
-#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_MISS_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
- *  L2-Cache bus3 Conflict-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x384)
-/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of access-conflicts when L1-DCache accesses
- *  L2-Cache due to bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
-#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register
- *  L2-Cache bus3 Next-Level-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x388)
-/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of times that L2-Cache accesses external memory due
- *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S)
-#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S  0
-
-/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register
- *  L2-Cache bus3 WB-Access Counter register
- */
-#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x38c)
-/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
- *  The register records the number of write back when L1-DCache accesses L2-Cache due
- *  to bus3 accessing L1-DCache.
- */
-#define CACHE_L2_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S)
-#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
-#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S  0
-
-/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
- *  L2-Cache Access Fail ID/attribution information register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x390)
-/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
- *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
-#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ID_S  0
-/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
- *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
- *  due to cache accessing L1-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
-#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
-#define CACHE_L2_CACHE_FAIL_ATTR_S  16
-
-/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
- *  L2-Cache Access Fail Address information register
- */
-#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x394)
-/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
- *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
- */
-#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
-#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_FAIL_ADDR_S  0
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
- *  L1-Cache Access Fail Interrupt enable register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x398)
-/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The bit is used to enable interrupt of L2-Cache preload-operation done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The bit is used to enable interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
- *  Sync Preload operation Interrupt clear register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x39c)
-/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
- *  is done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [12]; default: 0;
- *  The bit is used to clear interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
- *  Sync Preload operation Interrupt raw register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x3a0)
-/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
- *  done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
- *  occurs.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
- *  L1-Cache Access Fail Interrupt status register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x3a4)
-/** CACHE_L2_CACHE_PLD_DONE_INT_ST : RO; bitpos: [5]; default: 0;
- *  The bit indicates the status of the interrupt that occurs only when L2-Cache
- *  preload-operation is done.
- */
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
-/** CACHE_L2_CACHE_PLD_ERR_INT_ST : RO; bitpos: [12]; default: 0;
- *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
- */
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
-
-/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
- *  Cache Sync/Preload Operation exception register
- */
-#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a8)
-/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
- *  The value 2 is Only available which means preload size is error in L2-Cache.
- */
-#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
-#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
-#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
-#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
-
-/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
- *  Cache Sync Reset control register
- */
-#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac)
-/** CACHE_L2_CACHE_SYNC_RST : R/W; bitpos: [5]; default: 0;
- *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
- *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
- */
-#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
-#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
-#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
-#define CACHE_L2_CACHE_SYNC_RST_S  5
-
-/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
- *  Cache Preload Reset control register
- */
-#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3b0)
-/** CACHE_L2_CACHE_PLD_RST : R/W; bitpos: [5]; default: 0;
- *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
- *  only be used to initialize preload-logic when some fatal error of preload-logic
- *  occurs.
- */
-#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
-#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
-#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
-#define CACHE_L2_CACHE_PLD_RST_S  5
-
-/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
- *  Cache Autoload buffer clear control register
- */
-#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4)
-/** CACHE_L2_CACHE_ALD_BUF_CLR : R/W; bitpos: [5]; default: 0;
- *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
- *  autoload will not work in L2-Cache. This bit should not be active when autoload
- *  works in L2-Cache.
- */
-#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
-#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
-#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
-
-/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
- *  Unallocate request buffer clear registers
- */
-#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b8)
-/** CACHE_L2_CACHE_UNALLOC_CLR : R/W; bitpos: [5]; default: 0;
- *  The bit is used to clear the unallocate request buffer of l2 icache where the
- *  unallocate request is responsed but not completed.
- */
-#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
-#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
-#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
-#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
-
-/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
- *  L2 cache access attribute control register
- */
-#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3bc)
-/** CACHE_L2_CACHE_ACCESS_FORCE_CC : R/W; bitpos: [0]; default: 1;
- *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
- *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
- *  non-cacheable.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
-/** CACHE_L2_CACHE_ACCESS_FORCE_WB : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
- *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
- *  write-through.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
-/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : R/W; bitpos: [2]; default: 1;
- *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
- *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
- *  write-miss-allocate and write-miss-no-allocate.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
-/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : R/W; bitpos: [3]; default: 1;
- *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
- *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
- *  read-miss-allocate and read-miss-no-allocate.
- */
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
-#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
-
-/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
- *  Cache Tag and Data memory Object control register
- */
-#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3c0)
-/** CACHE_L2_CACHE_TAG_OBJECT : R/W; bitpos: [5]; default: 0;
- *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
-#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
-#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
-#define CACHE_L2_CACHE_TAG_OBJECT_S  5
-/** CACHE_L2_CACHE_MEM_OBJECT : R/W; bitpos: [11]; default: 0;
- *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
- *  the others fields inside this register.
- */
-#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
-#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
-#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
-#define CACHE_L2_CACHE_MEM_OBJECT_S  11
-
-/** CACHE_L2_CACHE_WAY_OBJECT_REG register
- *  Cache Tag and Data memory way register
- */
-#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3c4)
-/** CACHE_L2_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
- *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
- *  way1, 2: way2, 3: way3, ?, 7: way7.
- */
-#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
-#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
-#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
-#define CACHE_L2_CACHE_WAY_OBJECT_S  0
-
-/** CACHE_L2_CACHE_VADDR_REG register
- *  Cache Vaddr register
- */
-#define CACHE_L2_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x3c8)
-/** CACHE_L2_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
- *  Those bits stores the virtual address which will decide where inside the specified
- *  tag memory object will be accessed.
- */
-#define CACHE_L2_CACHE_VADDR    0xFFFFFFFFU
-#define CACHE_L2_CACHE_VADDR_M  (CACHE_L2_CACHE_VADDR_V << CACHE_L2_CACHE_VADDR_S)
-#define CACHE_L2_CACHE_VADDR_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_VADDR_S  0
-
-/** CACHE_L2_CACHE_DEBUG_BUS_REG register
- *  Cache Tag/data memory content register
- */
-#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3cc)
-/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 972;
- *  This is a constant place where we can write data to or read data from the tag/data
- *  memory on the specified cache.
- */
-#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
-#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
-#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
-#define CACHE_L2_CACHE_DEBUG_BUS_S  0
-
-/** CACHE_CLOCK_GATE_REG register
- *  Clock gate control register
- */
-#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3d4)
-/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  The bit is used to enable clock gate when access all registers in this module.
- */
-#define CACHE_CLK_EN    (BIT(0))
-#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
-#define CACHE_CLK_EN_V  0x00000001U
-#define CACHE_CLK_EN_S  0
-
-/** CACHE_DATE_REG register
- *  Version control register
- */
-#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
-/** CACHE_DATE : R/W; bitpos: [27:0]; default: 36716848;
- *  version control register. Note that this default value stored is the latest date
- *  when the hardware logic was updated.
- */
-#define CACHE_DATE    0x0FFFFFFFU
-#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
-#define CACHE_DATE_V  0x0FFFFFFFU
-#define CACHE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index 8e140f05717..6b0ee7ed530 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -103,9 +103,12 @@ typedef enum {
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_XTAL = 1,         /*!< Select XTAL_CLK as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL` */
     SOC_RTC_FAST_CLK_SRC_LP_PLL = 2,       /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K) */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< XTAL_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL` */
 } soc_rtc_fast_clk_src_t;
 
 /**
@@ -151,6 +154,7 @@ typedef enum {
     SOC_MOD_CLK_CPLL,                          /*!< CPLL is from 40MHz XTAL oscillator frequency multipliers */
     SOC_MOD_CLK_SPLL,                          /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */
     SOC_MOD_CLK_MPLL,                          /*!< MPLL is from 40MHz XTAL oscillator frequency multipliers */
+    SOC_MOD_CLK_SDIO_PLL,                      /*!< SDIO PLL is from 40MHz XTAL oscillator frequency multipliers, it has a "fixed" frequency of 200MHz */
     SOC_MOD_CLK_XTAL32K,                       /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
     SOC_MOD_CLK_RC_FAST,                       /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
     SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
@@ -159,8 +163,8 @@ typedef enum {
     SOC_MOD_CLK_XTAL_D2,                       /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
     SOC_MOD_CLK_LP_PLL,                        /*!< LP_PLL is from 32kHz XTAL oscillator frequency multipliers, it has a fixed frequency of 8MHz */
     SOC_MOD_CLK_LP_DYN_FAST,                   /*!< LP_DYN_FAST can be derived from RTC_SLOW_CLK or RTC_FAST_CLK depending on the chip’s power mode:
-                                                    in active mode, select RTC_FAST_CLK as the clock source;
-                                                    in light/deep sleep mode, select RTC_SLOW_CLK as the clock source */
+                                                    Only in LP_SLEEP mode, select RTC_SLOW_CLK as the clock source;
+                                                    In other non-LP_SLEEP mode, select RTC_FAST_CLK as the clock source; */
     SOC_MOD_CLK_LP_PERI,                       /*!< LP_PERI_CLK is derived from LP_DYN_FAST (configurable divider) */
     SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
 } soc_module_clk_t;
@@ -706,7 +710,7 @@ typedef enum {
 /**
  * @brief Array initializer for all supported clock sources of SDMMC
  */
-#define SOC_SDMMC_CLKS {SOC_MOD_CLK_PLL_F160M}
+#define SOC_SDMMC_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_SDIO_PLL}
 
 /**
  * @brief Type of SDMMC clock source
@@ -714,7 +718,7 @@ typedef enum {
 typedef enum {
     SDMMC_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M,  /*!< Select PLL_160M as the default choice */
     SDMMC_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M,  /*!< Select PLL_160M as the source clock */
-    // SOC_MOD_CLK_SDIO_PLL TODO:IDF-8886
+    SDMMC_CLK_SRC_SDIO_200M = SOC_MOD_CLK_SDIO_PLL,
 } soc_periph_sdmmc_clk_src_t;
 
 //////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
@@ -732,6 +736,19 @@ typedef enum {
     TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PERI,    /*!< Select LP_PERI as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
+//////////////////////////////////////////////////EMAC PTP///////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of EMAC PTP
+ */
+#define SOC_EMAC_PTP_CLK {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M}
+
+typedef enum {
+    EMAC_PTP_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
+    EMAC_PTP_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,
+    EMAC_PTP_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
+} soc_periph_emac_ptp_clk_src_t;
+
 //////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
 typedef enum {
     CLKOUT_SIG_MPLL     = 0,    /*!< MPLL is from 40MHz XTAL oscillator frequency multipliers */
diff --git a/components/soc/esp32p4/include/soc/dport_access.h b/components/soc/esp32p4/include/soc/dport_access.h
index 3747073d224..189fc786b83 100644
--- a/components/soc/esp32p4/include/soc/dport_access.h
+++ b/components/soc/esp32p4/include/soc/dport_access.h
@@ -9,7 +9,6 @@
 
 #include <stdint.h>
 #include "soc.h"
-#include "uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/soc/esp32p4/include/soc/ecc_mult_reg.h b/components/soc/esp32p4/include/soc/ecc_mult_reg.h
deleted file mode 100644
index 2bec4bb8c79..00000000000
--- a/components/soc/esp32p4/include/soc/ecc_mult_reg.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ECC_MULT_INT_RAW_REG register
- *  ECC interrupt raw register, valid in level.
- */
-#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
-/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
-#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_RAW_S  0
-
-/** ECC_MULT_INT_ST_REG register
- *  ECC interrupt status register.
- */
-#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
-/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
-#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_ST_S  0
-
-/** ECC_MULT_INT_ENA_REG register
- *  ECC interrupt enable register.
- */
-#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
-/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
-#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_ENA_S  0
-
-/** ECC_MULT_INT_CLR_REG register
- *  ECC interrupt clear register.
- */
-#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
-/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecc_calc_done_int interrupt
- */
-#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
-#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
-#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
-#define ECC_MULT_CALC_DONE_INT_CLR_S  0
-
-/** ECC_MULT_CONF_REG register
- *  ECC configure register
- */
-#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
-/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
- *  the caculatrion is done.
- */
-#define ECC_MULT_START    (BIT(0))
-#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
-#define ECC_MULT_START_V  0x00000001U
-#define ECC_MULT_START_S  0
-/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
- *  Write 1 to reset ECC Accelerator.
- */
-#define ECC_MULT_RESET    (BIT(1))
-#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
-#define ECC_MULT_RESET_V  0x00000001U
-#define ECC_MULT_RESET_S  1
-/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
- *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
- */
-#define ECC_MULT_KEY_LENGTH    (BIT(2))
-#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
-#define ECC_MULT_KEY_LENGTH_V  0x00000001U
-#define ECC_MULT_KEY_LENGTH_S  2
-/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
- *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
- *  1: p(mod base of curve)
- */
-#define ECC_MULT_MOD_BASE    (BIT(3))
-#define ECC_MULT_MOD_BASE_M  (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
-#define ECC_MULT_MOD_BASE_V  0x00000001U
-#define ECC_MULT_MOD_BASE_S  3
-/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
- *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
- *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
- *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
- *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
- */
-#define ECC_MULT_WORK_MODE    0x0000000FU
-#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
-#define ECC_MULT_WORK_MODE_V  0x0000000FU
-#define ECC_MULT_WORK_MODE_S  4
-/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define ECC_MULT_SECURITY_MODE    (BIT(8))
-#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
-#define ECC_MULT_SECURITY_MODE_V  0x00000001U
-#define ECC_MULT_SECURITY_MODE_S  8
-/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
- *  The verification result bit of ECC Accelerator, only valid when calculation is done.
- */
-#define ECC_MULT_VERIFICATION_RESULT    (BIT(29))
-#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
-#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
-#define ECC_MULT_VERIFICATION_RESULT_S  29
-/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
- *  Write 1 to force on register clock gate.
- */
-#define ECC_MULT_CLK_EN    (BIT(30))
-#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
-#define ECC_MULT_CLK_EN_V  0x00000001U
-#define ECC_MULT_CLK_EN_S  30
-/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  ECC memory clock gate force on register
- */
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
-#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
-
-/** ECC_MULT_DATE_REG register
- *  Version control register
- */
-#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
-/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704;
- *  ECC mult version control register
- */
-#define ECC_MULT_DATE    0x0FFFFFFFU
-#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
-#define ECC_MULT_DATE_V  0x0FFFFFFFU
-#define ECC_MULT_DATE_S  0
-
-/** ECC_MULT_K_MEM register
- *  The memory that stores k.
- */
-#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
-#define ECC_MULT_K_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_PX_MEM register
- *  The memory that stores Px.
- */
-#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
-#define ECC_MULT_PX_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_PY_MEM register
- *  The memory that stores Py.
- */
-#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
-#define ECC_MULT_PY_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QX_MEM register
- *  The memory that stores Qx.
- */
-#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
-#define ECC_MULT_QX_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QY_MEM register
- *  The memory that stores Qy.
- */
-#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
-#define ECC_MULT_QY_MEM_SIZE_BYTES 32
-
-/** ECC_MULT_QZ_MEM register
- *  The memory that stores Qz.
- */
-#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0)
-#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/ecc_mult_struct.h b/components/soc/esp32p4/include/soc/ecc_mult_struct.h
deleted file mode 100644
index 5754a9e3cdd..00000000000
--- a/components/soc/esp32p4/include/soc/ecc_mult_struct.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Memory data */
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  ECC interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_raw:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_raw_reg_t;
-
-/** Type of int_st register
- *  ECC interrupt status register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_st:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_st_reg_t;
-
-/** Type of int_ena register
- *  ECC interrupt enable register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_ena:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_ena_reg_t;
-
-/** Type of int_clr register
- *  ECC interrupt clear register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the ecc_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_clr:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecc_mult_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of conf register
- *  ECC configure register
- */
-typedef union {
-    struct {
-        /** start : R/W/SC; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
-         *  the caculatrion is done.
-         */
-        uint32_t start:1;
-        /** reset : WT; bitpos: [1]; default: 0;
-         *  Write 1 to reset ECC Accelerator.
-         */
-        uint32_t reset:1;
-        /** key_length : R/W; bitpos: [2]; default: 0;
-         *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
-         */
-        uint32_t key_length:1;
-        /** mod_base : R/W; bitpos: [3]; default: 0;
-         *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
-         *  1: p(mod base of curve)
-         */
-        uint32_t mod_base:1;
-        /** work_mode : R/W; bitpos: [7:4]; default: 0;
-         *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
-         *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
-         *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
-         *  8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division.
-         */
-        uint32_t work_mode:4;
-        /** security_mode : R/W; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t security_mode:1;
-        uint32_t reserved_9:20;
-        /** verification_result : RO/SS; bitpos: [29]; default: 0;
-         *  The verification result bit of ECC Accelerator, only valid when calculation is done.
-         */
-        uint32_t verification_result:1;
-        /** clk_en : R/W; bitpos: [30]; default: 0;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_en:1;
-        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
-         *  ECC memory clock gate force on register
-         */
-        uint32_t mem_clock_gate_force_on:1;
-    };
-    uint32_t val;
-} ecc_mult_conf_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720704;
-         *  ECC mult version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ecc_mult_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000[3];
-    volatile ecc_mult_int_raw_reg_t int_raw;
-    volatile ecc_mult_int_st_reg_t int_st;
-    volatile ecc_mult_int_ena_reg_t int_ena;
-    volatile ecc_mult_int_clr_reg_t int_clr;
-    volatile ecc_mult_conf_reg_t conf;
-    uint32_t reserved_020[55];
-    volatile ecc_mult_date_reg_t date;
-    volatile uint32_t k[8];
-    volatile uint32_t px[8];
-    volatile uint32_t py[8];
-    volatile uint32_t qx[8];
-    volatile uint32_t qy[8];
-    volatile uint32_t qz[8];
-} ecc_mult_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ecc_mult_dev_t) == 0x1C0, "Invalid size of ecc_mult_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/ecdsa_reg.h b/components/soc/esp32p4/include/soc/ecdsa_reg.h
deleted file mode 100644
index 6e09925e090..00000000000
--- a/components/soc/esp32p4/include/soc/ecdsa_reg.h
+++ /dev/null
@@ -1,318 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** ECDSA_CONF_REG register
- *  ECDSA configure register
- */
-#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
-/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
- *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
- */
-#define ECDSA_WORK_MODE    0x00000003U
-#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
-#define ECDSA_WORK_MODE_V  0x00000003U
-#define ECDSA_WORK_MODE_S  0
-/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
- *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
- */
-#define ECDSA_ECC_CURVE    (BIT(2))
-#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
-#define ECDSA_ECC_CURVE_V  0x00000001U
-#define ECDSA_ECC_CURVE_S  2
-/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
- *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
- *  written by software.
- */
-#define ECDSA_SOFTWARE_SET_K    (BIT(3))
-#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
-#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
-#define ECDSA_SOFTWARE_SET_K_S  3
-/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
- *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
- *  software.
- */
-#define ECDSA_SOFTWARE_SET_Z    (BIT(4))
-#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
-#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
-#define ECDSA_SOFTWARE_SET_Z_S  4
-/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
- *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
- *  deterministic derivation algorithm.
- */
-#define ECDSA_DETERMINISTIC_K    (BIT(5))
-#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
-#define ECDSA_DETERMINISTIC_K_V  0x00000001U
-#define ECDSA_DETERMINISTIC_K_S  5
-/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
- *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
- */
-#define ECDSA_DETERMINISTIC_LOOP    0x0000FFFFU
-#define ECDSA_DETERMINISTIC_LOOP_M  (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
-#define ECDSA_DETERMINISTIC_LOOP_V  0x0000FFFFU
-#define ECDSA_DETERMINISTIC_LOOP_S  6
-
-/** ECDSA_CLK_REG register
- *  ECDSA clock gate register
- */
-#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
-/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  Write 1 to force on register clock gate.
- */
-#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
-#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
-#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
-#define ECDSA_CLK_GATE_FORCE_ON_S  0
-
-/** ECDSA_INT_RAW_REG register
- *  ECDSA interrupt raw register, valid in level.
- */
-#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
-/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_RAW    (BIT(0))
-#define ECDSA_CALC_DONE_INT_RAW_M  (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
-#define ECDSA_CALC_DONE_INT_RAW_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_RAW_S  0
-/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
-#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_RAW_S  1
-
-/** ECDSA_INT_ST_REG register
- *  ECDSA interrupt status register.
- */
-#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
-/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_ST    (BIT(0))
-#define ECDSA_CALC_DONE_INT_ST_M  (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
-#define ECDSA_CALC_DONE_INT_ST_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_ST_S  0
-/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_ST    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
-#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_ST_S  1
-
-/** ECDSA_INT_ENA_REG register
- *  ECDSA interrupt enable register.
- */
-#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
-/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_ENA    (BIT(0))
-#define ECDSA_CALC_DONE_INT_ENA_M  (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
-#define ECDSA_CALC_DONE_INT_ENA_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_ENA_S  0
-/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
-#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_ENA_S  1
-
-/** ECDSA_INT_CLR_REG register
- *  ECDSA interrupt clear register.
- */
-#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
-/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the ecdsa_calc_done_int interrupt
- */
-#define ECDSA_CALC_DONE_INT_CLR    (BIT(0))
-#define ECDSA_CALC_DONE_INT_CLR_M  (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
-#define ECDSA_CALC_DONE_INT_CLR_V  0x00000001U
-#define ECDSA_CALC_DONE_INT_CLR_S  0
-/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the ecdsa_sha_release_int interrupt
- */
-#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(1))
-#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
-#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
-#define ECDSA_SHA_RELEASE_INT_CLR_S  1
-
-/** ECDSA_START_REG register
- *  ECDSA start register
- */
-#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
-/** ECDSA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
- *  after configuration.
- */
-#define ECDSA_START    (BIT(0))
-#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
-#define ECDSA_START_V  0x00000001U
-#define ECDSA_START_S  0
-/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
- *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
- *  self-cleared after configuration.
- */
-#define ECDSA_LOAD_DONE    (BIT(1))
-#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
-#define ECDSA_LOAD_DONE_V  0x00000001U
-#define ECDSA_LOAD_DONE_S  1
-/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
- *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
- *  self-cleared after configuration.
- */
-#define ECDSA_GET_DONE    (BIT(2))
-#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
-#define ECDSA_GET_DONE_V  0x00000001U
-#define ECDSA_GET_DONE_S  2
-
-/** ECDSA_STATE_REG register
- *  ECDSA status register
- */
-#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
-/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
- *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
- *  state.
- */
-#define ECDSA_BUSY    0x00000003U
-#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
-#define ECDSA_BUSY_V  0x00000003U
-#define ECDSA_BUSY_S  0
-
-/** ECDSA_RESULT_REG register
- *  ECDSA result register
- */
-#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
-/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
- *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
- *  done.
- */
-#define ECDSA_OPERATION_RESULT    (BIT(0))
-#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
-#define ECDSA_OPERATION_RESULT_V  0x00000001U
-#define ECDSA_OPERATION_RESULT_S  0
-/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
- *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
- *  curve order, then actually taken k = k mod n.
- */
-#define ECDSA_K_VALUE_WARNING    (BIT(1))
-#define ECDSA_K_VALUE_WARNING_M  (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
-#define ECDSA_K_VALUE_WARNING_V  0x00000001U
-#define ECDSA_K_VALUE_WARNING_S  1
-
-/** ECDSA_DATE_REG register
- *  Version control register
- */
-#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
-/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
- *  ECDSA version control register
- */
-#define ECDSA_DATE    0x0FFFFFFFU
-#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
-#define ECDSA_DATE_V  0x0FFFFFFFU
-#define ECDSA_DATE_S  0
-
-/** ECDSA_SHA_MODE_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
-/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
- *  Others: invalid.
- */
-#define ECDSA_SHA_MODE    0x00000007U
-#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
-#define ECDSA_SHA_MODE_V  0x00000007U
-#define ECDSA_SHA_MODE_S  0
-
-/** ECDSA_SHA_START_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
-/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
- *  bit will be self-cleared after configuration.
- */
-#define ECDSA_SHA_START    (BIT(0))
-#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
-#define ECDSA_SHA_START_V  0x00000001U
-#define ECDSA_SHA_START_S  0
-
-/** ECDSA_SHA_CONTINUE_REG register
- *  ECDSA control SHA register
- */
-#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
-/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
- *  bit will be self-cleared after configuration.
- */
-#define ECDSA_SHA_CONTINUE    (BIT(0))
-#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
-#define ECDSA_SHA_CONTINUE_V  0x00000001U
-#define ECDSA_SHA_CONTINUE_S  0
-
-/** ECDSA_SHA_BUSY_REG register
- *  ECDSA status register
- */
-#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
-/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
- *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
- *  calculation. 0: SHA is idle.
- */
-#define ECDSA_SHA_BUSY    (BIT(0))
-#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
-#define ECDSA_SHA_BUSY_V  0x00000001U
-#define ECDSA_SHA_BUSY_S  0
-
-/** ECDSA_MESSAGE_MEM register
- *  The memory that stores message.
- */
-#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
-#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
-
-/** ECDSA_R_MEM register
- *  The memory that stores r.
- */
-#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
-#define ECDSA_R_MEM_SIZE_BYTES 32
-
-/** ECDSA_S_MEM register
- *  The memory that stores s.
- */
-#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
-#define ECDSA_S_MEM_SIZE_BYTES 32
-
-/** ECDSA_Z_MEM register
- *  The memory that stores software written z.
- */
-#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
-#define ECDSA_Z_MEM_SIZE_BYTES 32
-
-/** ECDSA_QAX_MEM register
- *  The memory that stores x coordinates of QA or software written k.
- */
-#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
-#define ECDSA_QAX_MEM_SIZE_BYTES 32
-
-/** ECDSA_QAY_MEM register
- *  The memory that stores y coordinates of QA.
- */
-#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
-#define ECDSA_QAY_MEM_SIZE_BYTES 32
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/ecdsa_struct.h b/components/soc/esp32p4/include/soc/ecdsa_struct.h
deleted file mode 100644
index 1d39f1ad04d..00000000000
--- a/components/soc/esp32p4/include/soc/ecdsa_struct.h
+++ /dev/null
@@ -1,323 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Data Memory */
-
-/** Group: Configuration registers */
-/** Type of conf register
- *  ECDSA configure register
- */
-typedef union {
-    struct {
-        /** work_mode : R/W; bitpos: [1:0]; default: 0;
-         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
-         *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
-         */
-        uint32_t work_mode:2;
-        /** ecc_curve : R/W; bitpos: [2]; default: 0;
-         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
-         */
-        uint32_t ecc_curve:1;
-        /** software_set_k : R/W; bitpos: [3]; default: 0;
-         *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
-         *  written by software.
-         */
-        uint32_t software_set_k:1;
-        /** software_set_z : R/W; bitpos: [4]; default: 0;
-         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
-         *  software.
-         */
-        uint32_t software_set_z:1;
-        /** deterministic_k : R/W; bitpos: [5]; default: 0;
-         *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
-         *  deterministic derivation algorithm.
-         */
-        uint32_t deterministic_k:1;
-        /** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
-         *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
-         */
-        uint32_t deterministic_loop:16;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} ecdsa_conf_reg_t;
-
-/** Type of start register
- *  ECDSA start register
- */
-typedef union {
-    struct {
-        /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
-         *  after configuration.
-         */
-        uint32_t start:1;
-        /** load_done : WT; bitpos: [1]; default: 0;
-         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
-         *  self-cleared after configuration.
-         */
-        uint32_t load_done:1;
-        /** get_done : WT; bitpos: [2]; default: 0;
-         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
-         *  self-cleared after configuration.
-         */
-        uint32_t get_done:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} ecdsa_start_reg_t;
-
-
-/** Group: Clock and reset registers */
-/** Type of clk register
- *  ECDSA clock gate register
- */
-typedef union {
-    struct {
-        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to force on register clock gate.
-         */
-        uint32_t clk_gate_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_clk_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  ECDSA interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_raw:1;
-        /** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_raw_reg_t;
-
-/** Type of int_st register
- *  ECDSA interrupt status register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_st:1;
-        /** sha_release_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_st_reg_t;
-
-/** Type of int_ena register
- *  ECDSA interrupt enable register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_ena:1;
-        /** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_ena_reg_t;
-
-/** Type of int_clr register
- *  ECDSA interrupt clear register.
- */
-typedef union {
-    struct {
-        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the ecdsa_calc_done_int interrupt
-         */
-        uint32_t calc_done_int_clr:1;
-        /** sha_release_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the ecdsa_sha_release_int interrupt
-         */
-        uint32_t sha_release_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_int_clr_reg_t;
-
-
-/** Group: Status registers */
-/** Type of state register
- *  ECDSA status register
- */
-typedef union {
-    struct {
-        /** busy : RO; bitpos: [1:0]; default: 0;
-         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
-         *  state.
-         */
-        uint32_t busy:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_state_reg_t;
-
-
-/** Group: Result registers */
-/** Type of result register
- *  ECDSA result register
- */
-typedef union {
-    struct {
-        /** operation_result : RO/SS; bitpos: [0]; default: 0;
-         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
-         *  done.
-         */
-        uint32_t operation_result:1;
-        /** k_value_warning : RO/SS; bitpos: [1]; default: 0;
-         *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
-         *  curve order, then actually taken k = k mod n.
-         */
-        uint32_t k_value_warning:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} ecdsa_result_reg_t;
-
-
-/** Group: SHA register */
-/** Type of sha_mode register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
-         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
-         *  Others: invalid.
-         */
-        uint32_t sha_mode:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} ecdsa_sha_mode_reg_t;
-
-/** Type of sha_start register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
-         *  bit will be self-cleared after configuration.
-         */
-        uint32_t sha_start:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_start_reg_t;
-
-/** Type of sha_continue register
- *  ECDSA control SHA register
- */
-typedef union {
-    struct {
-        /** sha_continue : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
-         *  bit will be self-cleared after configuration.
-         */
-        uint32_t sha_continue:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_continue_reg_t;
-
-/** Type of sha_busy register
- *  ECDSA status register
- */
-typedef union {
-    struct {
-        /** sha_busy : RO; bitpos: [0]; default: 0;
-         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
-         *  calculation. 0: SHA is idle.
-         */
-        uint32_t sha_busy:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} ecdsa_sha_busy_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36716656;
-         *  ECDSA version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} ecdsa_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000;
-    volatile ecdsa_conf_reg_t conf;
-    volatile ecdsa_clk_reg_t clk;
-    volatile ecdsa_int_raw_reg_t int_raw;
-    volatile ecdsa_int_st_reg_t int_st;
-    volatile ecdsa_int_ena_reg_t int_ena;
-    volatile ecdsa_int_clr_reg_t int_clr;
-    volatile ecdsa_start_reg_t start;
-    volatile ecdsa_state_reg_t state;
-    volatile ecdsa_result_reg_t result;
-    uint32_t reserved_028[53];
-    volatile ecdsa_date_reg_t date;
-    uint32_t reserved_100[64];
-    volatile ecdsa_sha_mode_reg_t sha_mode;
-    uint32_t reserved_204[3];
-    volatile ecdsa_sha_start_reg_t sha_start;
-    volatile ecdsa_sha_continue_reg_t sha_continue;
-    volatile ecdsa_sha_busy_reg_t sha_busy;
-    uint32_t reserved_21c[25];
-    volatile uint32_t message[8];
-    uint32_t reserved_2a0[472];
-    volatile uint32_t r[8];
-    volatile uint32_t s[8];
-    volatile uint32_t z[8];
-    volatile uint32_t qax[8];
-    volatile uint32_t qay[8];
-} ecdsa_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/efuse_reg.h b/components/soc/esp32p4/include/soc/efuse_reg.h
deleted file mode 100644
index 310bdaa73f6..00000000000
--- a/components/soc/esp32p4/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,4345 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#include "efuse_defs.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 3rd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 0th 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 1st 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  Configures the 2nd 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS_REG register
- *  BLOCK0 data register 0.
- */
-#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Represents whether programming of individual eFuse memory bit is disabled or
- *  enabled. 1: Disabled. 0 Enabled.
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  BLOCK0 data register 1.
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0;
- *  Enable usb device exchange pins of D+ and D-.
- */
-#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
-#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
-#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
-/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0;
- *  Enable usb otg11 exchange pins of D+ and D-.
- */
-#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
-#define EFUSE_USB_OTG11_EXCHG_PINS_M  (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S)
-#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
- *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  9
-/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
- *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_POWERGLITCH_EN    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
-#define EFUSE_POWERGLITCH_EN_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
- *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Represents whether the function that forces chip into download mode is disabled or
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
- *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
- *  boot_mode_download.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
-/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
-#define EFUSE_DIS_TWAI_V  0x00000001U
-#define EFUSE_DIS_TWAI_S  14
-/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
- *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
- *  is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
-#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_S  15
-/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
- *  enabled.
- */
-#define EFUSE_SOFT_DIS_JTAG    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
-#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
- *  enabled.
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
- *  mode). 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [22:21]; default: 0;
- *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
- */
-#define EFUSE_USB_DEVICE_DREFH    0x00000003U
-#define EFUSE_USB_DEVICE_DREFH_M  (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S)
-#define EFUSE_USB_DEVICE_DREFH_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFH_S  21
-/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [24:23]; default: 0;
- *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
- */
-#define EFUSE_USB_OTG11_DREFH    0x00000003U
-#define EFUSE_USB_OTG11_DREFH_M  (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S)
-#define EFUSE_USB_OTG11_DREFH_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFH_S  23
-/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
- *  TBD
- */
-#define EFUSE_USB_PHY_SEL    (BIT(25))
-#define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
-#define EFUSE_USB_PHY_SEL_V  0x00000001U
-#define EFUSE_USB_PHY_SEL_S  25
-/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0;
- *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
- *  of 1 is valid.
- */
-#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003FU
-#define EFUSE_KM_HUK_GEN_STATE_LOW_M  (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S)
-#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x0000003FU
-#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  BLOCK0 data register 2.
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0;
- *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
- *  of 1 is valid.
- */
-#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S)
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0;
- *  Set bits to control key manager random number switch cycle. 0: control by register.
- *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
-/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0;
- *  Set each bit to control whether corresponding key can only be deployed once. 1 is
- *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
- */
-#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
-/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0;
- *  Set each bit to control whether corresponding key must come from key manager.. 1 is
- *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
- */
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  9
-/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [13]; default: 0;
- *  Set this bit to disable software written init key, and force use efuse_init_key.
- */
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(13))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
-/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0;
- *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
- */
-#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
-#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
-#define EFUSE_XTS_KEY_LENGTH_256_S  14
-/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_79    (BIT(15))
-#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
-#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_79_S  15
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
- *  selected. 0: not selected.
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
- *  1: enabled. Even number of 1: disabled.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking first secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Represents whether revoking second secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Represents whether revoking third secure boot key is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Represents the purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  24
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Represents the purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  BLOCK0 data register 3.
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Represents the purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  0
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Represents the purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  4
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Represents the purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  8
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Represents the purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  12
-/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
- *  Represents the spa secure level by configuring the clock random divide mode.
- */
-#define EFUSE_SEC_DPA_LEVEL    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
-#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_S  16
-/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0;
- *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
- *  0: not force used.
- */
-#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S)
-#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x00000001U
-#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
-/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
- *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
- */
-#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
-#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_S  19
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
- *  enabled. 0: disabled.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [22]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_118    (BIT(22))
-#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
-#define EFUSE_RD_RESERVE_0_118_V  0x00000001U
-#define EFUSE_RD_RESERVE_0_118_S  22
-/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
- *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
- */
-#define EFUSE_FLASH_TYPE    (BIT(23))
-#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
-#define EFUSE_FLASH_TYPE_V  0x00000001U
-#define EFUSE_FLASH_TYPE_S  23
-/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0;
- *  Set flash page size.
- */
-#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
-#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_S  24
-/** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0;
- *  Set this bit to enable ecc for flash boot.
- */
-#define EFUSE_FLASH_ECC_EN    (BIT(26))
-#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
-#define EFUSE_FLASH_ECC_EN_V  0x00000001U
-#define EFUSE_FLASH_ECC_EN_S  26
-/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [27]; default: 0;
- *  Set this bit to disable download via USB-OTG.
- */
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(27))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Represents the flash waiting time after power-up, in unit of ms. When the value
- *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
- *  is 2 times the programmed value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  BLOCK0 data register 4.
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
- *  0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
- *  TBD
- */
-#define EFUSE_LOCK_KM_KEY    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
-#define EFUSE_LOCK_KM_KEY_V  0x00000001U
-#define EFUSE_LOCK_KM_KEY_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
- *  disabled. 0: enabled.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Represents whether security download is enabled or disabled. 1: enabled. 0:
- *  disabled.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Represents the type of UART printing. 00: force enable printing. 01: enable
- *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
- *  at high level. 11: force disable printing.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
- *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
- *  forced. 0:not forced.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  8
-/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
- *  Represents the version used by ESP-IDF anti-rollback feature.
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
- *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
- *  enabled. 1: disabled. 0: enabled.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
-/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
- *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
- *  enabled. 0:disabled.
- */
-#define EFUSE_HYS_EN_PAD    (BIT(26))
-#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
-#define EFUSE_HYS_EN_PAD_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_S  26
-/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0;
- *  Set the dcdc voltage default.
- */
-#define EFUSE_DCDC_VSET    0x0000001FU
-#define EFUSE_DCDC_VSET_M  (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S)
-#define EFUSE_DCDC_VSET_V  0x0000001FU
-#define EFUSE_DCDC_VSET_S  27
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  BLOCK0 data register 5.
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_PXA0_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
- *  TBD
- */
-#define EFUSE_PXA0_TIEH_SEL_0    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_0_M  (EFUSE_PXA0_TIEH_SEL_0_V << EFUSE_PXA0_TIEH_SEL_0_S)
-#define EFUSE_PXA0_TIEH_SEL_0_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_0_S  0
-/** EFUSE_PXA0_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
- *  TBD.
- */
-#define EFUSE_PXA0_TIEH_SEL_1    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_1_M  (EFUSE_PXA0_TIEH_SEL_1_V << EFUSE_PXA0_TIEH_SEL_1_S)
-#define EFUSE_PXA0_TIEH_SEL_1_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_1_S  2
-/** EFUSE_PXA0_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
- *  TBD.
- */
-#define EFUSE_PXA0_TIEH_SEL_2    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_2_M  (EFUSE_PXA0_TIEH_SEL_2_V << EFUSE_PXA0_TIEH_SEL_2_S)
-#define EFUSE_PXA0_TIEH_SEL_2_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_2_S  4
-/** EFUSE_PXA0_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
- *  TBD.
- */
-#define EFUSE_PXA0_TIEH_SEL_3    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_3_M  (EFUSE_PXA0_TIEH_SEL_3_V << EFUSE_PXA0_TIEH_SEL_3_S)
-#define EFUSE_PXA0_TIEH_SEL_3_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_3_S  6
-/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
- *  TBD.
- */
-#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
-/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
- *  Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step
- *  of 80 mV.
- */
-#define EFUSE_USB_DEVICE_DREFL    0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_M  (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
-#define EFUSE_USB_DEVICE_DREFL_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_S  12
-/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
- *  Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step
- *  of 80 mV.
- */
-#define EFUSE_USB_OTG11_DREFL    0x00000003U
-#define EFUSE_USB_OTG11_DREFL_M  (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
-#define EFUSE_USB_OTG11_DREFL_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFL_S  14
-/** EFUSE_RD_RESERVE_0_176 : RW; bitpos: [17:16]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_176    0x00000003U
-#define EFUSE_RD_RESERVE_0_176_M  (EFUSE_RD_RESERVE_0_176_V << EFUSE_RD_RESERVE_0_176_S)
-#define EFUSE_RD_RESERVE_0_176_V  0x00000003U
-#define EFUSE_RD_RESERVE_0_176_S  16
-/** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
- *  HP system power source select. 0:LDO. 1: DCDC.
- */
-#define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
-#define EFUSE_HP_PWR_SRC_SEL_M  (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S)
-#define EFUSE_HP_PWR_SRC_SEL_V  0x00000001U
-#define EFUSE_HP_PWR_SRC_SEL_S  18
-/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0;
- *  Select dcdc vset use efuse_dcdc_vset.
- */
-#define EFUSE_DCDC_VSET_EN    (BIT(19))
-#define EFUSE_DCDC_VSET_EN_M  (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S)
-#define EFUSE_DCDC_VSET_EN_V  0x00000001U
-#define EFUSE_DCDC_VSET_EN_S  19
-/** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0;
- *  Set this bit to disable watch dog.
- */
-#define EFUSE_DIS_WDT    (BIT(20))
-#define EFUSE_DIS_WDT_M  (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S)
-#define EFUSE_DIS_WDT_V  0x00000001U
-#define EFUSE_DIS_WDT_S  20
-/** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0;
- *  Set this bit to disable super-watchdog.
- */
-#define EFUSE_DIS_SWD    (BIT(21))
-#define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
-#define EFUSE_DIS_SWD_V  0x00000001U
-#define EFUSE_DIS_SWD_S  21
-/** EFUSE_RD_RESERVE_0_182 : RW; bitpos: [31:22]; default: 0;
- *  Reserved, it was created by set_missed_fields_in_regs func
- */
-#define EFUSE_RD_RESERVE_0_182    0x000003FFU
-#define EFUSE_RD_RESERVE_0_182_M  (EFUSE_RD_RESERVE_0_182_V << EFUSE_RD_RESERVE_0_182_S)
-#define EFUSE_RD_RESERVE_0_182_V  0x000003FFU
-#define EFUSE_RD_RESERVE_0_182_S  22
-
-/** EFUSE_RD_MAC_SYS_0_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the low 32 bits of MAC address.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SYS_1_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Stores the high 16 bits of MAC address.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_RESERVED_1_16 : RO; bitpos: [31:16]; default: 0;
- *  Stores the extended bits of MAC address.
- */
-#define EFUSE_RESERVED_1_16    0x0000FFFFU
-#define EFUSE_RESERVED_1_16_M  (EFUSE_RESERVED_1_16_V << EFUSE_RESERVED_1_16_S)
-#define EFUSE_RESERVED_1_16_V  0x0000FFFFU
-#define EFUSE_RESERVED_1_16_S  16
-
-/** EFUSE_RD_MAC_SYS_2_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
-/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
- *  Minor chip version
- */
-#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
-#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
-#define EFUSE_WAFER_VERSION_MINOR_S  0
-/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
- *  Major chip version
- */
-#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_S  4
-/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
- *  Disables check of wafer version major
- */
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(6))
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  6
-/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
- *  Disables check of blk version major
- */
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
-/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
- *  BLK_VERSION_MINOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MINOR    0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
-#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_S  8
-/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
- *  BLK_VERSION_MAJOR of BLOCK2
- */
-#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
-#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_S  11
-/** EFUSE_PSRAM_CAP : R; bitpos: [15:13]; default: 0;
- *  PSRAM capacity
- */
-#define EFUSE_PSRAM_CAP    0x00000007U
-#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
-#define EFUSE_PSRAM_CAP_V  0x00000007U
-#define EFUSE_PSRAM_CAP_S  13
-/** EFUSE_TEMP : R; bitpos: [17:16]; default: 0;
- *  Operating temperature of the ESP chip
- */
-#define EFUSE_TEMP    0x00000003U
-#define EFUSE_TEMP_M  (EFUSE_TEMP_V << EFUSE_TEMP_S)
-#define EFUSE_TEMP_V  0x00000003U
-#define EFUSE_TEMP_S  16
-/** EFUSE_PSRAM_VENDOR : R; bitpos: [19:18]; default: 0;
- *  PSRAM vendor
- */
-#define EFUSE_PSRAM_VENDOR    0x00000003U
-#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
-#define EFUSE_PSRAM_VENDOR_V  0x00000003U
-#define EFUSE_PSRAM_VENDOR_S  18
-/** EFUSE_PKG_VERSION : R; bitpos: [22:20]; default: 0;
- *  Package version
- */
-#define EFUSE_PKG_VERSION    0x00000007U
-#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
-#define EFUSE_PKG_VERSION_V  0x00000007U
-#define EFUSE_PKG_VERSION_S  20
-/** EFUSE_RESERVED_1_87 : R; bitpos: [31:23]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_87    0x000001FFU
-#define EFUSE_RESERVED_1_87_M  (EFUSE_RESERVED_1_87_V << EFUSE_RESERVED_1_87_S)
-#define EFUSE_RESERVED_1_87_V  0x000001FFU
-#define EFUSE_RESERVED_1_87_S  23
-
-/** EFUSE_RD_MAC_SYS_3_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
- *  Reserved.
- */
-#define EFUSE_MAC_RESERVED_2    0x0003FFFFU
-#define EFUSE_MAC_RESERVED_2_M  (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
-#define EFUSE_MAC_RESERVED_2_V  0x0003FFFFU
-#define EFUSE_MAC_RESERVED_2_S  0
-/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
- *  Stores the first 14 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
-#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
-#define EFUSE_SYS_DATA_PART0_0_S  18
-
-/** EFUSE_RD_MAC_SYS_4_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
-#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_1_S  0
-
-/** EFUSE_RD_MAC_SYS_5_REG register
- *  BLOCK1 data register $n.
- */
-#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of the zeroth part of system data.
- */
-#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
-#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART0_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_M  (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
-#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_4_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
-#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_5_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
-#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_6_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Register $n of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of the first part of system data.
- */
-#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
-#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART1_7_S  0
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_192    0x000000FFU
-#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
-#define EFUSE_RESERVED_3_192_V  0x000000FFU
-#define EFUSE_RESERVED_3_192_S  0
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_S  8
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Register $n of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_248    0x000000FFU
-#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
-#define EFUSE_RESERVED_3_248_V  0x000000FFU
-#define EFUSE_RESERVED_3_248_S  24
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Register $n of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Register $n of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Register $n of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Register $n of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Register $n of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Register $n of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Register $n of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the $nth 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_ERR0_REG register
- *  Programming error record register 0 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  Indicates a programming error of RD_DIS.
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0;
- *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
- */
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S)
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
-/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
- */
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S)
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
- *  Indicates a programming error of DIS_USB_JTAG.
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  9
-/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
- *  Indicates a programming error of POWERGLITCH_EN.
- */
-#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
-#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
-#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_ERR_S  10
-/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
- */
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
-#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
-/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
- *  Indicates a programming error of DIS_TWAI.
- */
-#define EFUSE_DIS_TWAI_ERR    (BIT(14))
-#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
-#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
-#define EFUSE_DIS_TWAI_ERR_S  14
-/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
- *  Indicates a programming error of JTAG_SEL_ENABLE.
- */
-#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
-#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
-#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
-#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
-/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  Indicates a programming error of SOFT_DIS_JTAG.
- */
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of DIS_PAD_JTAG.
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_DEVICE_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
- *  Indicates a programming error of USB_DEVICE_DREFH.
- */
-#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DEVICE_DREFH_ERR_M  (EFUSE_USB_DEVICE_DREFH_ERR_V << EFUSE_USB_DEVICE_DREFH_ERR_S)
-#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
-/** EFUSE_USB_OTG11_DREFH_ERR : RO; bitpos: [24:23]; default: 0;
- *  Indicates a programming error of USB_OTG11_DREFH.
- */
-#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003U
-#define EFUSE_USB_OTG11_DREFH_ERR_M  (EFUSE_USB_OTG11_DREFH_ERR_V << EFUSE_USB_OTG11_DREFH_ERR_S)
-#define EFUSE_USB_OTG11_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFH_ERR_S  23
-/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of USB_PHY_SEL.
- */
-#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
-#define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
-#define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
-#define EFUSE_USB_PHY_SEL_ERR_S  25
-/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0;
- *  Indicates a programming error of HUK_GEN_STATE_LOW.
- */
-#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003FU
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S)
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x0000003FU
-#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
-
-/** EFUSE_RD_REPEAT_ERR1_REG register
- *  Programming error record register 1 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0;
- *  Indicates a programming error of HUK_GEN_STATE_HIGH.
- */
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S)
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x00000007U
-#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S  0
-/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0;
- *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
- */
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
-#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
-/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0;
- *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
- */
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
-#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
-/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0;
- *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
- */
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
-#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
-/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0;
- *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
- */
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
-#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
-/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0;
- *  Indicates a programming error of XTS_KEY_LENGTH_256.
- */
-#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
-#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of WDT_DELAY_SEL.
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_0.
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_1.
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR2_REG register
- *  Programming error record register 2 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_2.
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  0
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_3.
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_4.
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  Indicates a programming error of KEY_PURPOSE_5.
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  Indicates a programming error of SEC_DPA_LEVEL.
- */
-#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
-#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
-#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
-/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0;
- *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
- */
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S)
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x00000001U
-#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
-/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of CRYPT_DPA_ENABLE.
- */
-#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
-#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_EN.
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0;
- *  Indicates a programming error of FLASH_TYPE.
- */
-#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
-#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
-#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
-#define EFUSE_FLASH_TYPE_ERR_S  23
-/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0;
- *  Indicates a programming error of FLASH_PAGE_SIZE.
- */
-#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
-#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
-/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0;
- *  Indicates a programming error of FLASH_ECC_EN.
- */
-#define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
-#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
-#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
-#define EFUSE_FLASH_ECC_EN_ERR_S  26
-/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0;
- *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  Indicates a programming error of FLASH_TPUW.
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR3_REG register
- *  Programming error record register 3 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  Indicates a programming error of DIS_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  Indicates a programming error of DIS_DIRECT_BOOT.
- */
-#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
-#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
-/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
- *  TBD
- */
-#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
-#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
-#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
-#define EFUSE_LOCK_KM_KEY_ERR_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  Indicates a programming error of UART_PRINT_CONTROL.
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
- *  Indicates a programming error of FORCE_SEND_RESUME.
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
- *  Indicates a programming error of SECURE VERSION.
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  9
-/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
- *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
- */
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
-/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
- *  Indicates a programming error of HYS_EN_PAD.
- */
-#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
-#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
-#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
-#define EFUSE_HYS_EN_PAD_ERR_S  26
-/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0;
- *  Indicates a programming error of DCDC_VSET.
- */
-#define EFUSE_DCDC_VSET_ERR    0x0000001FU
-#define EFUSE_DCDC_VSET_ERR_M  (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S)
-#define EFUSE_DCDC_VSET_ERR_V  0x0000001FU
-#define EFUSE_DCDC_VSET_ERR_S  27
-
-/** EFUSE_RD_REPEAT_ERR4_REG register
- *  Programming error record register 4 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
-/** EFUSE_PXA0_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_0.
- */
-#define EFUSE_PXA0_TIEH_SEL_0_ERR    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_0_ERR_M  (EFUSE_PXA0_TIEH_SEL_0_ERR_V << EFUSE_PXA0_TIEH_SEL_0_ERR_S)
-#define EFUSE_PXA0_TIEH_SEL_0_ERR_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_0_ERR_S  0
-/** EFUSE_PXA0_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_1.
- */
-#define EFUSE_PXA0_TIEH_SEL_1_ERR    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_1_ERR_M  (EFUSE_PXA0_TIEH_SEL_1_ERR_V << EFUSE_PXA0_TIEH_SEL_1_ERR_S)
-#define EFUSE_PXA0_TIEH_SEL_1_ERR_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_1_ERR_S  2
-/** EFUSE_PXA0_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_2.
- */
-#define EFUSE_PXA0_TIEH_SEL_2_ERR    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_2_ERR_M  (EFUSE_PXA0_TIEH_SEL_2_ERR_V << EFUSE_PXA0_TIEH_SEL_2_ERR_S)
-#define EFUSE_PXA0_TIEH_SEL_2_ERR_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_2_ERR_S  4
-/** EFUSE_PXA0_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
- *  Indicates a programming error of 0PXA_TIEH_SEL_3.
- */
-#define EFUSE_PXA0_TIEH_SEL_3_ERR    0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_3_ERR_M  (EFUSE_PXA0_TIEH_SEL_3_ERR_V << EFUSE_PXA0_TIEH_SEL_3_ERR_S)
-#define EFUSE_PXA0_TIEH_SEL_3_ERR_V  0x00000003U
-#define EFUSE_PXA0_TIEH_SEL_3_ERR_S  6
-/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
- *  TBD.
- */
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
-#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
-/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0;
- *  Indicates a programming error of USB_DEVICE_DREFL.
- */
-#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_ERR_M  (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S)
-#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
-/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0;
- *  Indicates a programming error of USB_OTG11_DREFL.
- */
-#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003U
-#define EFUSE_USB_OTG11_DREFL_ERR_M  (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S)
-#define EFUSE_USB_OTG11_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_OTG11_DREFL_ERR_S  14
-/** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0;
- *  Indicates a programming error of HP_PWR_SRC_SEL.
- */
-#define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
-#define EFUSE_HP_PWR_SRC_SEL_ERR_M  (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S)
-#define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x00000001U
-#define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
-/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0;
- *  Indicates a programming error of DCDC_VSET_EN.
- */
-#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
-#define EFUSE_DCDC_VSET_EN_ERR_M  (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S)
-#define EFUSE_DCDC_VSET_EN_ERR_V  0x00000001U
-#define EFUSE_DCDC_VSET_EN_ERR_S  19
-/** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0;
- *  Indicates a programming error of DIS_WDT.
- */
-#define EFUSE_DIS_WDT_ERR    (BIT(20))
-#define EFUSE_DIS_WDT_ERR_M  (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S)
-#define EFUSE_DIS_WDT_ERR_V  0x00000001U
-#define EFUSE_DIS_WDT_ERR_S  20
-/** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0;
- *  Indicates a programming error of DIS_SWD.
- */
-#define EFUSE_DIS_SWD_ERR    (BIT(21))
-#define EFUSE_DIS_SWD_ERR_M  (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S)
-#define EFUSE_DIS_SWD_ERR_V  0x00000001U
-#define EFUSE_DIS_SWD_ERR_S  21
-
-/** EFUSE_RD_RS_ERR0_REG register
- *  Programming error record register 0 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_MAC_SYS_ERR_NUM    0x00000007U
-#define EFUSE_MAC_SYS_ERR_NUM_M  (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S)
-#define EFUSE_MAC_SYS_ERR_NUM_V  0x00000007U
-#define EFUSE_MAC_SYS_ERR_NUM_S  0
-/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_MAC_SYS_FAIL    (BIT(3))
-#define EFUSE_MAC_SYS_FAIL_M  (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S)
-#define EFUSE_MAC_SYS_FAIL_V  0x00000001U
-#define EFUSE_MAC_SYS_FAIL_S  3
-/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART1_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART1_ERR_NUM_M  (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S)
-#define EFUSE_SYS_PART1_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART1_ERR_NUM_S  4
-/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part1 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART1_FAIL    (BIT(7))
-#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
-#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART1_FAIL_S  7
-/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
-#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_S  8
-/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  0: Means no failure and that the user data is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
-#define EFUSE_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_USR_DATA_FAIL_S  11
-/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY0_ERR_NUM    0x00000007U
-#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
-#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY0_ERR_NUM_S  12
-/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
- *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
- *  key0 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY0_FAIL    (BIT(15))
-#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
-#define EFUSE_KEY0_FAIL_V  0x00000001U
-#define EFUSE_KEY0_FAIL_S  15
-/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY1_ERR_NUM    0x00000007U
-#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
-#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY1_ERR_NUM_S  16
-/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
- *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
- *  key1 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY1_FAIL    (BIT(19))
-#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
-#define EFUSE_KEY1_FAIL_V  0x00000001U
-#define EFUSE_KEY1_FAIL_S  19
-/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY2_ERR_NUM    0x00000007U
-#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
-#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY2_ERR_NUM_S  20
-/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
- *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
- *  key2 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY2_FAIL    (BIT(23))
-#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
-#define EFUSE_KEY2_FAIL_V  0x00000001U
-#define EFUSE_KEY2_FAIL_S  23
-/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY3_ERR_NUM    0x00000007U
-#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
-#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY3_ERR_NUM_S  24
-/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
- *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
- *  key3 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY3_FAIL    (BIT(27))
-#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
-#define EFUSE_KEY3_FAIL_V  0x00000001U
-#define EFUSE_KEY3_FAIL_S  27
-/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY4_ERR_NUM    0x00000007U
-#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
-#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY4_ERR_NUM_S  28
-/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
- *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
- *  key4 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY4_FAIL    (BIT(31))
-#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
-#define EFUSE_KEY4_FAIL_V  0x00000001U
-#define EFUSE_KEY4_FAIL_S  31
-
-/** EFUSE_RD_RS_ERR1_REG register
- *  Programming error record register 1 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY5_ERR_NUM    0x00000007U
-#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
-#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY5_ERR_NUM_S  0
-/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
- *  key5 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY5_FAIL    (BIT(3))
-#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
-#define EFUSE_KEY5_FAIL_V  0x00000001U
-#define EFUSE_KEY5_FAIL_S  3
-/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
-#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_S  4
-/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part2 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART2_FAIL    (BIT(7))
-#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
-#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART2_FAIL_S  7
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
-/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit to force enable eFuse register configuration clock signal.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuration register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A:  programming operation command 0x5AA5: read operation command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
- *  Configures which block to use for ECDSA key output.
- */
-#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
-#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CFG_ECDSA_BLK_S  16
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
- *  The value of OTP_LOAD_SW.
- */
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
-#define EFUSE_OTP_LOAD_SW_V  0x00000001U
-#define EFUSE_OTP_LOAD_SW_S  4
-/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
- *  The value of OTP_VDDQ_C_SYNC2.
- */
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
- *  The value of OTP_STROBE_SW.
- */
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
-#define EFUSE_OTP_STROBE_SW_V  0x00000001U
-#define EFUSE_OTP_STROBE_SW_S  6
-/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
- *  The value of OTP_CSB_SW.
- */
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
-#define EFUSE_OTP_CSB_SW_V  0x00000001U
-#define EFUSE_OTP_CSB_SW_S  7
-/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
- *  The value of OTP_PGENB_SW.
- */
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
-#define EFUSE_OTP_PGENB_SW_V  0x00000001U
-#define EFUSE_OTP_PGENB_SW_S  8
-/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
- *  The value of OTP_VDDQ_IS_SW.
- */
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
- *  Indicates the number of block valid bit.
- */
-#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
-#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
-#define EFUSE_BLK0_VALID_BIT_CNT_S  10
-/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
- *  Indicates which block is used for ECDSA key output.
- */
-#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
-#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
-#define EFUSE_CUR_ECDSA_BLK_S  20
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
-/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the read hold time.
- */
-#define EFUSE_THR_A    0x000000FFU
-#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
-#define EFUSE_THR_A_V  0x000000FFU
-#define EFUSE_THR_A_S  0
-/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
- *  Configures the read time.
- */
-#define EFUSE_TRD    0x000000FFU
-#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
-#define EFUSE_TRD_V  0x000000FFU
-#define EFUSE_TRD_S  8
-/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
- *  Configures the read setup time.
- */
-#define EFUSE_TSUR_A    0x000000FFU
-#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
-#define EFUSE_TSUR_A_V  0x000000FFU
-#define EFUSE_TSUR_A_S  16
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
- *  Configures the waiting time of reading eFuse memory.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
-/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
- *  Configures the programming setup time.
- */
-#define EFUSE_TSUP_A    0x000000FFU
-#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
-#define EFUSE_TSUP_A_V  0x000000FFU
-#define EFUSE_TSUP_A_S  0
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
- *  Configures the programming hold time.
- */
-#define EFUSE_THP_A    0x000000FFU
-#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
-#define EFUSE_THP_A_V  0x000000FFU
-#define EFUSE_THP_A_S  24
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
- *  Configures the active programming time.
- */
-#define EFUSE_TPGM    0x0000FFFFU
-#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
-#define EFUSE_TPGM_V  0x0000FFFFU
-#define EFUSE_TPGM_S  16
-
-/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
-/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
- *  Set this bit to bypass reed solomon correction step.
- */
-#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
-#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
-#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
-#define EFUSE_BYPASS_RS_CORRECTION_S  0
-/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
- *  Configures block number of programming twice operation.
- */
-#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
-#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
-#define EFUSE_BYPASS_RS_BLK_NUM_S  1
-/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
- *  Set this bit to update multi-bit register signals.
- */
-#define EFUSE_UPDATE    (BIT(12))
-#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
-#define EFUSE_UPDATE_V  0x00000001U
-#define EFUSE_UPDATE_S  12
-/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
- *  Configures the inactive programming time.
- */
-#define EFUSE_TPGM_INACTIVE    0x000000FFU
-#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
-#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
-#define EFUSE_TPGM_INACTIVE_S  13
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-/** EFUSE_APB2OTP_WR_DIS_REG register
- *  eFuse apb2otp block0 data register1.
- */
-#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800)
-/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 write disable data.
- */
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
- *  eFuse apb2otp block0 data register2.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
- *  eFuse apb2otp block0 data register3.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
- *  eFuse apb2otp block0 data register4.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
- *  eFuse apb2otp block0 data register5.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
- *  eFuse apb2otp block0 data register6.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup1 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
- *  eFuse apb2otp block0 data register7.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
- *  eFuse apb2otp block0 data register8.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
- *  eFuse apb2otp block0 data register9.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
- *  eFuse apb2otp block0 data register10.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
- *  eFuse apb2otp block0 data register11.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup2 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
- *  eFuse apb2otp block0 data register12.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
- *  eFuse apb2otp block0 data register13.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
- *  eFuse apb2otp block0 data register14.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
- *  eFuse apb2otp block0 data register15.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
- *  eFuse apb2otp block0 data register16.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup3 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
- *  eFuse apb2otp block0 data register17.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
- *  eFuse apb2otp block0 data register18.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
- *  eFuse apb2otp block0 data register19.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
- *  eFuse apb2otp block0 data register20.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84c)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
-
-/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
- *  eFuse apb2otp block0 data register21.
- */
-#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850)
-/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block0 backup4 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
-
-/** EFUSE_APB2OTP_BLK1_W1_REG register
- *  eFuse apb2otp block1 data register1.
- */
-#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854)
-/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
-#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W1_S  0
-
-/** EFUSE_APB2OTP_BLK1_W2_REG register
- *  eFuse apb2otp block1 data register2.
- */
-#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858)
-/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
-#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W2_S  0
-
-/** EFUSE_APB2OTP_BLK1_W3_REG register
- *  eFuse apb2otp block1 data register3.
- */
-#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85c)
-/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
-#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W3_S  0
-
-/** EFUSE_APB2OTP_BLK1_W4_REG register
- *  eFuse apb2otp block1 data register4.
- */
-#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860)
-/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
-#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W4_S  0
-
-/** EFUSE_APB2OTP_BLK1_W5_REG register
- *  eFuse apb2otp block1 data register5.
- */
-#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864)
-/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
-#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W5_S  0
-
-/** EFUSE_APB2OTP_BLK1_W6_REG register
- *  eFuse apb2otp block1 data register6.
- */
-#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868)
-/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
-#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W6_S  0
-
-/** EFUSE_APB2OTP_BLK1_W7_REG register
- *  eFuse apb2otp block1 data register7.
- */
-#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86c)
-/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
-#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W7_S  0
-
-/** EFUSE_APB2OTP_BLK1_W8_REG register
- *  eFuse apb2otp block1 data register8.
- */
-#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870)
-/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
-#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W8_S  0
-
-/** EFUSE_APB2OTP_BLK1_W9_REG register
- *  eFuse apb2otp block1 data register9.
- */
-#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874)
-/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block1  word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
-#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK1_W9_S  0
-
-/** EFUSE_APB2OTP_BLK2_W1_REG register
- *  eFuse apb2otp block2 data register1.
- */
-#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878)
-/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
-#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W1_S  0
-
-/** EFUSE_APB2OTP_BLK2_W2_REG register
- *  eFuse apb2otp block2 data register2.
- */
-#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87c)
-/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
-#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W2_S  0
-
-/** EFUSE_APB2OTP_BLK2_W3_REG register
- *  eFuse apb2otp block2 data register3.
- */
-#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880)
-/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
-#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W3_S  0
-
-/** EFUSE_APB2OTP_BLK2_W4_REG register
- *  eFuse apb2otp block2 data register4.
- */
-#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884)
-/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
-#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W4_S  0
-
-/** EFUSE_APB2OTP_BLK2_W5_REG register
- *  eFuse apb2otp block2 data register5.
- */
-#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888)
-/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
-#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W5_S  0
-
-/** EFUSE_APB2OTP_BLK2_W6_REG register
- *  eFuse apb2otp block2 data register6.
- */
-#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88c)
-/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
-#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W6_S  0
-
-/** EFUSE_APB2OTP_BLK2_W7_REG register
- *  eFuse apb2otp block2 data register7.
- */
-#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890)
-/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
-#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W7_S  0
-
-/** EFUSE_APB2OTP_BLK2_W8_REG register
- *  eFuse apb2otp block2 data register8.
- */
-#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894)
-/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
-#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W8_S  0
-
-/** EFUSE_APB2OTP_BLK2_W9_REG register
- *  eFuse apb2otp block2 data register9.
- */
-#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898)
-/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
-#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W9_S  0
-
-/** EFUSE_APB2OTP_BLK2_W10_REG register
- *  eFuse apb2otp block2 data register10.
- */
-#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89c)
-/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
-#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W10_S  0
-
-/** EFUSE_APB2OTP_BLK2_W11_REG register
- *  eFuse apb2otp block2 data register11.
- */
-#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8a0)
-/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block2 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
-#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK2_W11_S  0
-
-/** EFUSE_APB2OTP_BLK3_W1_REG register
- *  eFuse apb2otp block3 data register1.
- */
-#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8a4)
-/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
-#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W1_S  0
-
-/** EFUSE_APB2OTP_BLK3_W2_REG register
- *  eFuse apb2otp block3 data register2.
- */
-#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8a8)
-/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
-#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W2_S  0
-
-/** EFUSE_APB2OTP_BLK3_W3_REG register
- *  eFuse apb2otp block3 data register3.
- */
-#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8ac)
-/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
-#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W3_S  0
-
-/** EFUSE_APB2OTP_BLK3_W4_REG register
- *  eFuse apb2otp block3 data register4.
- */
-#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8b0)
-/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
-#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W4_S  0
-
-/** EFUSE_APB2OTP_BLK3_W5_REG register
- *  eFuse apb2otp block3 data register5.
- */
-#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8b4)
-/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
-#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W5_S  0
-
-/** EFUSE_APB2OTP_BLK3_W6_REG register
- *  eFuse apb2otp block3 data register6.
- */
-#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8b8)
-/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
-#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W6_S  0
-
-/** EFUSE_APB2OTP_BLK3_W7_REG register
- *  eFuse apb2otp block3 data register7.
- */
-#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8bc)
-/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
-#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W7_S  0
-
-/** EFUSE_APB2OTP_BLK3_W8_REG register
- *  eFuse apb2otp block3 data register8.
- */
-#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8c0)
-/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
-#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W8_S  0
-
-/** EFUSE_APB2OTP_BLK3_W9_REG register
- *  eFuse apb2otp block3 data register9.
- */
-#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8c4)
-/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
-#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W9_S  0
-
-/** EFUSE_APB2OTP_BLK3_W10_REG register
- *  eFuse apb2otp block3 data register10.
- */
-#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8c8)
-/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
-#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W10_S  0
-
-/** EFUSE_APB2OTP_BLK3_W11_REG register
- *  eFuse apb2otp block3 data register11.
- */
-#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8cc)
-/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block3 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
-#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK3_W11_S  0
-
-/** EFUSE_APB2OTP_BLK4_W1_REG register
- *  eFuse apb2otp block4 data register1.
- */
-#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8d0)
-/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
-#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W1_S  0
-
-/** EFUSE_APB2OTP_BLK4_W2_REG register
- *  eFuse apb2otp block4 data register2.
- */
-#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8d4)
-/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
-#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W2_S  0
-
-/** EFUSE_APB2OTP_BLK4_W3_REG register
- *  eFuse apb2otp block4 data register3.
- */
-#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8d8)
-/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
-#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W3_S  0
-
-/** EFUSE_APB2OTP_BLK4_W4_REG register
- *  eFuse apb2otp block4 data register4.
- */
-#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8dc)
-/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
-#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W4_S  0
-
-/** EFUSE_APB2OTP_BLK4_W5_REG register
- *  eFuse apb2otp block4 data register5.
- */
-#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8e0)
-/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
-#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W5_S  0
-
-/** EFUSE_APB2OTP_BLK4_W6_REG register
- *  eFuse apb2otp block4 data register6.
- */
-#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8e4)
-/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
-#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W6_S  0
-
-/** EFUSE_APB2OTP_BLK4_W7_REG register
- *  eFuse apb2otp block4 data register7.
- */
-#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8e8)
-/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
-#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W7_S  0
-
-/** EFUSE_APB2OTP_BLK4_W8_REG register
- *  eFuse apb2otp block4 data register8.
- */
-#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8ec)
-/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
-#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W8_S  0
-
-/** EFUSE_APB2OTP_BLK4_W9_REG register
- *  eFuse apb2otp block4 data register9.
- */
-#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8f0)
-/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
-#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W9_S  0
-
-/** EFUSE_APB2OTP_BLK4_W10_REG register
- *  eFuse apb2otp block4 data registe10.
- */
-#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8f4)
-/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
-#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W10_S  0
-
-/** EFUSE_APB2OTP_BLK4_W11_REG register
- *  eFuse apb2otp block4 data register11.
- */
-#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8f8)
-/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block4 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
-#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK4_W11_S  0
-
-/** EFUSE_APB2OTP_BLK5_W1_REG register
- *  eFuse apb2otp block5 data register1.
- */
-#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8fc)
-/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
-#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W1_S  0
-
-/** EFUSE_APB2OTP_BLK5_W2_REG register
- *  eFuse apb2otp block5 data register2.
- */
-#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900)
-/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
-#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W2_S  0
-
-/** EFUSE_APB2OTP_BLK5_W3_REG register
- *  eFuse apb2otp block5 data register3.
- */
-#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904)
-/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
-#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W3_S  0
-
-/** EFUSE_APB2OTP_BLK5_W4_REG register
- *  eFuse apb2otp block5 data register4.
- */
-#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908)
-/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
-#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W4_S  0
-
-/** EFUSE_APB2OTP_BLK5_W5_REG register
- *  eFuse apb2otp block5 data register5.
- */
-#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90c)
-/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
-#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W5_S  0
-
-/** EFUSE_APB2OTP_BLK5_W6_REG register
- *  eFuse apb2otp block5 data register6.
- */
-#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910)
-/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
-#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W6_S  0
-
-/** EFUSE_APB2OTP_BLK5_W7_REG register
- *  eFuse apb2otp block5 data register7.
- */
-#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914)
-/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
-#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W7_S  0
-
-/** EFUSE_APB2OTP_BLK5_W8_REG register
- *  eFuse apb2otp block5 data register8.
- */
-#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918)
-/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
-#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W8_S  0
-
-/** EFUSE_APB2OTP_BLK5_W9_REG register
- *  eFuse apb2otp block5 data register9.
- */
-#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91c)
-/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
-#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W9_S  0
-
-/** EFUSE_APB2OTP_BLK5_W10_REG register
- *  eFuse apb2otp block5 data register10.
- */
-#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920)
-/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
-#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W10_S  0
-
-/** EFUSE_APB2OTP_BLK5_W11_REG register
- *  eFuse apb2otp block5 data register11.
- */
-#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924)
-/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block5 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
-#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK5_W11_S  0
-
-/** EFUSE_APB2OTP_BLK6_W1_REG register
- *  eFuse apb2otp block6 data register1.
- */
-#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928)
-/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
-#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W1_S  0
-
-/** EFUSE_APB2OTP_BLK6_W2_REG register
- *  eFuse apb2otp block6 data register2.
- */
-#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92c)
-/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
-#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W2_S  0
-
-/** EFUSE_APB2OTP_BLK6_W3_REG register
- *  eFuse apb2otp block6 data register3.
- */
-#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930)
-/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
-#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W3_S  0
-
-/** EFUSE_APB2OTP_BLK6_W4_REG register
- *  eFuse apb2otp block6 data register4.
- */
-#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934)
-/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
-#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W4_S  0
-
-/** EFUSE_APB2OTP_BLK6_W5_REG register
- *  eFuse apb2otp block6 data register5.
- */
-#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938)
-/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
-#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W5_S  0
-
-/** EFUSE_APB2OTP_BLK6_W6_REG register
- *  eFuse apb2otp block6 data register6.
- */
-#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93c)
-/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
-#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W6_S  0
-
-/** EFUSE_APB2OTP_BLK6_W7_REG register
- *  eFuse apb2otp block6 data register7.
- */
-#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940)
-/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
-#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W7_S  0
-
-/** EFUSE_APB2OTP_BLK6_W8_REG register
- *  eFuse apb2otp block6 data register8.
- */
-#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944)
-/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
-#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W8_S  0
-
-/** EFUSE_APB2OTP_BLK6_W9_REG register
- *  eFuse apb2otp block6 data register9.
- */
-#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948)
-/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
-#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W9_S  0
-
-/** EFUSE_APB2OTP_BLK6_W10_REG register
- *  eFuse apb2otp block6 data register10.
- */
-#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94c)
-/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
-#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W10_S  0
-
-/** EFUSE_APB2OTP_BLK6_W11_REG register
- *  eFuse apb2otp block6 data register11.
- */
-#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950)
-/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block6 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
-#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK6_W11_S  0
-
-/** EFUSE_APB2OTP_BLK7_W1_REG register
- *  eFuse apb2otp block7 data register1.
- */
-#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954)
-/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
-#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W1_S  0
-
-/** EFUSE_APB2OTP_BLK7_W2_REG register
- *  eFuse apb2otp block7 data register2.
- */
-#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958)
-/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
-#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W2_S  0
-
-/** EFUSE_APB2OTP_BLK7_W3_REG register
- *  eFuse apb2otp block7 data register3.
- */
-#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95c)
-/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
-#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W3_S  0
-
-/** EFUSE_APB2OTP_BLK7_W4_REG register
- *  eFuse apb2otp block7 data register4.
- */
-#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960)
-/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
-#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W4_S  0
-
-/** EFUSE_APB2OTP_BLK7_W5_REG register
- *  eFuse apb2otp block7 data register5.
- */
-#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964)
-/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
-#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W5_S  0
-
-/** EFUSE_APB2OTP_BLK7_W6_REG register
- *  eFuse apb2otp block7 data register6.
- */
-#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968)
-/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
-#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W6_S  0
-
-/** EFUSE_APB2OTP_BLK7_W7_REG register
- *  eFuse apb2otp block7 data register7.
- */
-#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96c)
-/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
-#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W7_S  0
-
-/** EFUSE_APB2OTP_BLK7_W8_REG register
- *  eFuse apb2otp block7 data register8.
- */
-#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970)
-/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
-#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W8_S  0
-
-/** EFUSE_APB2OTP_BLK7_W9_REG register
- *  eFuse apb2otp block7 data register9.
- */
-#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974)
-/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
-#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W9_S  0
-
-/** EFUSE_APB2OTP_BLK7_W10_REG register
- *  eFuse apb2otp block7 data register10.
- */
-#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978)
-/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
-#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W10_S  0
-
-/** EFUSE_APB2OTP_BLK7_W11_REG register
- *  eFuse apb2otp block7 data register11.
- */
-#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97c)
-/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block7 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
-#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK7_W11_S  0
-
-/** EFUSE_APB2OTP_BLK8_W1_REG register
- *  eFuse apb2otp block8 data register1.
- */
-#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980)
-/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
-#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W1_S  0
-
-/** EFUSE_APB2OTP_BLK8_W2_REG register
- *  eFuse apb2otp block8 data register2.
- */
-#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984)
-/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
-#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W2_S  0
-
-/** EFUSE_APB2OTP_BLK8_W3_REG register
- *  eFuse apb2otp block8 data register3.
- */
-#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988)
-/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
-#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W3_S  0
-
-/** EFUSE_APB2OTP_BLK8_W4_REG register
- *  eFuse apb2otp block8 data register4.
- */
-#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98c)
-/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
-#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W4_S  0
-
-/** EFUSE_APB2OTP_BLK8_W5_REG register
- *  eFuse apb2otp block8 data register5.
- */
-#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990)
-/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
-#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W5_S  0
-
-/** EFUSE_APB2OTP_BLK8_W6_REG register
- *  eFuse apb2otp block8 data register6.
- */
-#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994)
-/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
-#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W6_S  0
-
-/** EFUSE_APB2OTP_BLK8_W7_REG register
- *  eFuse apb2otp block8 data register7.
- */
-#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998)
-/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
-#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W7_S  0
-
-/** EFUSE_APB2OTP_BLK8_W8_REG register
- *  eFuse apb2otp block8 data register8.
- */
-#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99c)
-/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
-#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W8_S  0
-
-/** EFUSE_APB2OTP_BLK8_W9_REG register
- *  eFuse apb2otp block8 data register9.
- */
-#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9a0)
-/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
-#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W9_S  0
-
-/** EFUSE_APB2OTP_BLK8_W10_REG register
- *  eFuse apb2otp block8 data register10.
- */
-#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9a4)
-/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
-#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W10_S  0
-
-/** EFUSE_APB2OTP_BLK8_W11_REG register
- *  eFuse apb2otp block8 data register11.
- */
-#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9a8)
-/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block8 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
-#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK8_W11_S  0
-
-/** EFUSE_APB2OTP_BLK9_W1_REG register
- *  eFuse apb2otp block9 data register1.
- */
-#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9ac)
-/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
-#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W1_S  0
-
-/** EFUSE_APB2OTP_BLK9_W2_REG register
- *  eFuse apb2otp block9 data register2.
- */
-#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9b0)
-/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
-#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W2_S  0
-
-/** EFUSE_APB2OTP_BLK9_W3_REG register
- *  eFuse apb2otp block9 data register3.
- */
-#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9b4)
-/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
-#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W3_S  0
-
-/** EFUSE_APB2OTP_BLK9_W4_REG register
- *  eFuse apb2otp block9 data register4.
- */
-#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9b8)
-/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
-#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W4_S  0
-
-/** EFUSE_APB2OTP_BLK9_W5_REG register
- *  eFuse apb2otp block9 data register5.
- */
-#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9bc)
-/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
-#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W5_S  0
-
-/** EFUSE_APB2OTP_BLK9_W6_REG register
- *  eFuse apb2otp block9 data register6.
- */
-#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9c0)
-/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
-#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W6_S  0
-
-/** EFUSE_APB2OTP_BLK9_W7_REG register
- *  eFuse apb2otp block9 data register7.
- */
-#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9c4)
-/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
-#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W7_S  0
-
-/** EFUSE_APB2OTP_BLK9_W8_REG register
- *  eFuse apb2otp block9 data register8.
- */
-#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9c8)
-/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
-#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W8_S  0
-
-/** EFUSE_APB2OTP_BLK9_W9_REG register
- *  eFuse apb2otp block9 data register9.
- */
-#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9cc)
-/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
-#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W9_S  0
-
-/** EFUSE_APB2OTP_BLK9_W10_REG register
- *  eFuse apb2otp block9 data register10.
- */
-#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9d0)
-/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
-#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W10_S  0
-
-/** EFUSE_APB2OTP_BLK9_W11_REG register
- *  eFuse apb2otp block9 data register11.
- */
-#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9d4)
-/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block9 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
-#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK9_W11_S  0
-
-/** EFUSE_APB2OTP_BLK10_W1_REG register
- *  eFuse apb2otp block10 data register1.
- */
-#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9d8)
-/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word1 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
-#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W1_S  0
-
-/** EFUSE_APB2OTP_BLK10_W2_REG register
- *  eFuse apb2otp block10 data register2.
- */
-#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9dc)
-/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word2 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
-#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W2_S  0
-
-/** EFUSE_APB2OTP_BLK10_W3_REG register
- *  eFuse apb2otp block10 data register3.
- */
-#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9e0)
-/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word3 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
-#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W3_S  0
-
-/** EFUSE_APB2OTP_BLK10_W4_REG register
- *  eFuse apb2otp block10 data register4.
- */
-#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9e4)
-/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word4 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
-#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W4_S  0
-
-/** EFUSE_APB2OTP_BLK10_W5_REG register
- *  eFuse apb2otp block10 data register5.
- */
-#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9e8)
-/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word5 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
-#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W5_S  0
-
-/** EFUSE_APB2OTP_BLK10_W6_REG register
- *  eFuse apb2otp block10 data register6.
- */
-#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9ec)
-/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word6 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
-#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W6_S  0
-
-/** EFUSE_APB2OTP_BLK10_W7_REG register
- *  eFuse apb2otp block10 data register7.
- */
-#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9f0)
-/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word7 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
-#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W7_S  0
-
-/** EFUSE_APB2OTP_BLK10_W8_REG register
- *  eFuse apb2otp block10 data register8.
- */
-#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9f4)
-/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word8 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
-#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W8_S  0
-
-/** EFUSE_APB2OTP_BLK10_W9_REG register
- *  eFuse apb2otp block10 data register9.
- */
-#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9f8)
-/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word9 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
-#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W9_S  0
-
-/** EFUSE_APB2OTP_BLK10_W10_REG register
- *  eFuse apb2otp block10 data register10.
- */
-#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9fc)
-/** EFUSE_APB2OTP_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word10 data.
- */
-#define EFUSE_APB2OTP_BLOCK19_W10    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK19_W10_M  (EFUSE_APB2OTP_BLOCK19_W10_V << EFUSE_APB2OTP_BLOCK19_W10_S)
-#define EFUSE_APB2OTP_BLOCK19_W10_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK19_W10_S  0
-
-/** EFUSE_APB2OTP_BLK10_W11_REG register
- *  eFuse apb2otp block10 data register11.
- */
-#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xa00)
-/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
- *  Otp block10 word11 data.
- */
-#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
-#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
-#define EFUSE_APB2OTP_BLOCK10_W11_S  0
-
-/** EFUSE_APB2OTP_EN_REG register
- *  eFuse apb2otp enable configuration register.
- */
-#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xa08)
-/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
- *  Apb2otp mode enable signal.
- */
-#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
-#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
-#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
-#define EFUSE_APB2OTP_APB2OTP_EN_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/efuse_struct.h b/components/soc/esp32p4/include/soc/efuse_struct.h
deleted file mode 100644
index ac74f0f7ecb..00000000000
--- a/components/soc/esp32p4/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,4559 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PGM Data Register */
-/** Type of pgm_data0 register
- *  Register 0 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Register 1 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Register 2 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Register 3 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 3rd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Register 4 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 4th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Register 5 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 5th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Register 6 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 6th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Register 7 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 7th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-/** Type of pgm_check_value0 register
- *  Register 0 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 0th 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Register 1 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 1st 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Register 2 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  Configures the 2nd 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: ******** Registers */
-/** Type of rd_wr_dis register
- *  BLOCK0 data register 0.
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Represents whether programming of individual eFuse memory bit is disabled or
-         *  enabled. 1: Disabled. 0 Enabled.
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  BLOCK0 data register 1.
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t rd_dis:7;
-        /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0;
-         *  Enable usb device exchange pins of D+ and D-.
-         */
-        uint32_t usb_device_exchg_pins:1;
-        /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0;
-         *  Enable usb otg11 exchange pins of D+ and D-.
-         */
-        uint32_t usb_otg11_exchg_pins:1;
-        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
-         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_jtag:1;
-        /** powerglitch_en : RO; bitpos: [10]; default: 0;
-         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
-         */
-        uint32_t powerglitch_en:1;
-        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
-         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Represents whether the function that forces chip into download mode is disabled or
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_force_download:1;
-        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
-         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
-         *  boot_mode_download.
-         */
-        uint32_t spi_download_mspi_dis:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_twai:1;
-        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
-         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
-         *  is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t jtag_sel_enable:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
-         *  enabled.
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
-         *  enabled.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
-         *  mode). 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** usb_device_drefh : RO; bitpos: [22:21]; default: 0;
-         *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
-         */
-        uint32_t usb_device_drefh:2;
-        /** usb_otg11_drefh : RO; bitpos: [24:23]; default: 0;
-         *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
-         */
-        uint32_t usb_otg11_drefh:2;
-        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
-         *  TBD
-         */
-        uint32_t usb_phy_sel:1;
-        /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0;
-         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
-         *  of 1 is valid.
-         */
-        uint32_t km_huk_gen_state_low:6;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  BLOCK0 data register 2.
- */
-typedef union {
-    struct {
-        /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0;
-         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
-         *  of 1 is valid.
-         */
-        uint32_t km_huk_gen_state_high:3;
-        /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0;
-         *  Set bits to control key manager random number switch cycle. 0: control by register.
-         *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
-         */
-        uint32_t km_rnd_switch_cycle:2;
-        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
-         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
-         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
-         */
-        uint32_t km_deploy_only_once:4;
-        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
-         *  Set each bit to control whether corresponding key must come from key manager.. 1 is
-         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
-         */
-        uint32_t force_use_key_manager_key:4;
-        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
-         *  Set this bit to disable software written init key, and force use efuse_init_key.
-         */
-        uint32_t force_disable_sw_init_key:1;
-        /** xts_key_length_256 : RO; bitpos: [14]; default: 0;
-         *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
-         */
-        uint32_t xts_key_length_256:1;
-        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_79:1;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
-         *  selected. 0: not selected.
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
-         *  1: enabled. Even number of 1: disabled.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Represents the purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Represents the purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  BLOCK0 data register 3.
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Represents the purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Represents the purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Represents the purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Represents the purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
-         *  Represents the spa secure level by configuring the clock random divide mode.
-         */
-        uint32_t sec_dpa_level:2;
-        /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0;
-         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
-         *  0: not force used.
-         */
-        uint32_t ecdsa_enable_soft_k:1;
-        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
-         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
-         */
-        uint32_t crypt_dpa_enable:1;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
-         *  enabled. 0: disabled.
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** rd_reserve_0_118 : RW; bitpos: [22]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_118:1;
-        /** flash_type : RO; bitpos: [23]; default: 0;
-         *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
-         */
-        uint32_t flash_type:1;
-        /** flash_page_size : RO; bitpos: [25:24]; default: 0;
-         *  Set flash page size.
-         */
-        uint32_t flash_page_size:2;
-        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
-         *  Set this bit to enable ecc for flash boot.
-         */
-        uint32_t flash_ecc_en:1;
-        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
-         *  Set this bit to disable download via USB-OTG.
-         */
-        uint32_t dis_usb_otg_download_mode:1;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Represents the flash waiting time after power-up, in unit of ms. When the value
-         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
-         *  is 2 times the programmed value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  BLOCK0 data register 4.
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
-         *  0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** lock_km_key : RO; bitpos: [3]; default: 0;
-         *  TBD
-         */
-        uint32_t lock_km_key:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
-         *  disabled. 0: enabled.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
-         *  disabled.
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Represents the type of UART printing. 00: force enable printing. 01: enable
-         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
-         *  at high level. 11: force disable printing.
-         */
-        uint32_t uart_print_control:2;
-        /** force_send_resume : RO; bitpos: [8]; default: 0;
-         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
-         *  forced. 0:not forced.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [24:9]; default: 0;
-         *  Represents the version used by ESP-IDF anti-rollback feature.
-         */
-        uint32_t secure_version:16;
-        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
-         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
-         *  enabled. 1: disabled. 0: enabled.
-         */
-        uint32_t secure_boot_disable_fast_wake:1;
-        /** hys_en_pad : RO; bitpos: [26]; default: 0;
-         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
-         *  enabled. 0:disabled.
-         */
-        uint32_t hys_en_pad:1;
-        /** dcdc_vset : RO; bitpos: [31:27]; default: 0;
-         *  Set the dcdc voltage default.
-         */
-        uint32_t dcdc_vset:5;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  BLOCK0 data register 5.
- */
-typedef union {
-    struct {
-        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
-         *  TBD
-         */
-        uint32_t pxa0_tieh_sel_0:2;
-        /** pxa0_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
-         *  TBD.
-         */
-        uint32_t pxa0_tieh_sel_1:2;
-        /** pxa0_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
-         *  TBD.
-         */
-        uint32_t pxa0_tieh_sel_2:2;
-        /** pxa0_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
-         *  TBD.
-         */
-        uint32_t pxa0_tieh_sel_3:2;
-        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
-         *  TBD.
-         */
-        uint32_t km_disable_deploy_mode:4;
-        /** usb_device_drefl : RO; bitpos: [13:12]; default: 0;
-         *  Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step
-         *  of 80 mV.
-         */
-        uint32_t usb_device_drefl:2;
-        /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0;
-         *  Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step
-         *  of 80 mV.
-         */
-        uint32_t usb_otg11_drefl:2;
-        /** rd_reserve_0_176 : RW; bitpos: [17:16]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_176:2;
-        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
-         *  HP system power source select. 0:LDO. 1: DCDC.
-         */
-        uint32_t hp_pwr_src_sel:1;
-        /** dcdc_vset_en : RO; bitpos: [19]; default: 0;
-         *  Select dcdc vset use efuse_dcdc_vset.
-         */
-        uint32_t dcdc_vset_en:1;
-        /** dis_wdt : RO; bitpos: [20]; default: 0;
-         *  Set this bit to disable watch dog.
-         */
-        uint32_t dis_wdt:1;
-        /** dis_swd : RO; bitpos: [21]; default: 0;
-         *  Set this bit to disable super-watchdog.
-         */
-        uint32_t dis_swd:1;
-        /** rd_reserve_0_182 : RW; bitpos: [31:22]; default: 0;
-         *  Reserved, it was created by set_missed_fields_in_regs func
-         */
-        uint32_t rd_reserve_0_182:10;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-/** Type of rd_mac_sys_0 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the low 32 bits of MAC address.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_0_reg_t;
-
-/** Type of rd_mac_sys_1 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Stores the high 16 bits of MAC address.
-         */
-        uint32_t mac_1:16;
-        /** reserved_1_16 : RO; bitpos: [31:16]; default: 0;
-         *  Stores the extended bits of MAC address.
-         */
-        uint32_t reserved_1_16:16;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_1_reg_t;
-
-/** Type of rd_mac_sys_2 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** wafer_version_minor : R; bitpos: [3:0]; default: 0;
-         *  Minor chip version
-         */
-        uint32_t wafer_version_minor:4;
-        /** wafer_version_major : R; bitpos: [5:4]; default: 0;
-         *  Major chip version
-         */
-        uint32_t wafer_version_major:2;
-        /** disable_wafer_version_major : R; bitpos: [6]; default: 0;
-         *  Disables check of wafer version major
-         */
-        uint32_t disable_wafer_version_major:1;
-        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
-         *  Disables check of blk version major
-         */
-        uint32_t disable_blk_version_major:1;
-        /** blk_version_minor : R; bitpos: [10:8]; default: 0;
-         *  BLK_VERSION_MINOR of BLOCK2
-         */
-        uint32_t blk_version_minor:3;
-        /** blk_version_major : R; bitpos: [12:11]; default: 0;
-         *  BLK_VERSION_MAJOR of BLOCK2
-         */
-        uint32_t blk_version_major:2;
-        /** psram_cap : R; bitpos: [15:13]; default: 0;
-         *  PSRAM capacity
-         */
-        uint32_t psram_cap:3;
-        /** temp : R; bitpos: [17:16]; default: 0;
-         *  Operating temperature of the ESP chip
-         */
-        uint32_t temp:2;
-        /** psram_vendor : R; bitpos: [19:18]; default: 0;
-         *  PSRAM vendor
-         */
-        uint32_t psram_vendor:2;
-        /** pkg_version : R; bitpos: [22:20]; default: 0;
-         *  Package version
-         */
-        uint32_t pkg_version:3;
-        /** reserved_1_87 : R; bitpos: [31:23]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_87:9;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_2_reg_t;
-
-/** Type of rd_mac_sys_3 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
-         *  Reserved.
-         */
-        uint32_t mac_reserved_2:18;
-        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
-         *  Stores the first 14 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_0:14;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_3_reg_t;
-
-/** Type of rd_mac_sys_4 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_1:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_4_reg_t;
-
-/** Type of rd_mac_sys_5 register
- *  BLOCK1 data register $n.
- */
-typedef union {
-    struct {
-        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of the zeroth part of system data.
-         */
-        uint32_t sys_data_part0_2:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_sys_5_reg_t;
-
-/** Type of rd_sys_part1_data0 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Register $n of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of the first part of system data.
-         */
-        uint32_t sys_data_part1_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-/** Type of rd_usr_data0 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_192:8;
-        /** custom_mac : R; bitpos: [31:8]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac:24;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Register $n of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac_1:24;
-        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_248:8;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-/** Type of rd_key0_data0 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Register $n of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-/** Type of rd_key1_data0 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Register $n of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-/** Type of rd_key2_data0 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Register $n of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-/** Type of rd_key3_data0 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Register $n of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-/** Type of rd_key4_data0 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Register $n of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-/** Type of rd_key5_data0 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-/** Type of rd_sys_part2_data0 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Register $n of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Register $n of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the $nth 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-/** Type of rd_repeat_err0 register
- *  Programming error record register 0 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  Indicates a programming error of RD_DIS.
-         */
-        uint32_t rd_dis_err:7;
-        /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0;
-         *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
-         */
-        uint32_t dis_usb_device_exchg_pins_err:1;
-        /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
-         */
-        uint32_t dis_usb_otg11_exchg_pins_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
-         *  Indicates a programming error of DIS_USB_JTAG.
-         */
-        uint32_t dis_usb_jtag_err:1;
-        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
-         *  Indicates a programming error of POWERGLITCH_EN.
-         */
-        uint32_t powerglitch_en_err:1;
-        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
-         */
-        uint32_t dis_usb_serial_jtag_err:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
-         */
-        uint32_t dis_force_download_err:1;
-        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
-         */
-        uint32_t spi_download_mspi_dis_err:1;
-        /** dis_twai_err : RO; bitpos: [14]; default: 0;
-         *  Indicates a programming error of DIS_TWAI.
-         */
-        uint32_t dis_twai_err:1;
-        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
-         *  Indicates a programming error of JTAG_SEL_ENABLE.
-         */
-        uint32_t jtag_sel_enable_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  Indicates a programming error of SOFT_DIS_JTAG.
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of DIS_PAD_JTAG.
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_device_drefh_err : RO; bitpos: [22:21]; default: 0;
-         *  Indicates a programming error of USB_DEVICE_DREFH.
-         */
-        uint32_t usb_device_drefh_err:2;
-        /** usb_otg11_drefh_err : RO; bitpos: [24:23]; default: 0;
-         *  Indicates a programming error of USB_OTG11_DREFH.
-         */
-        uint32_t usb_otg11_drefh_err:2;
-        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of USB_PHY_SEL.
-         */
-        uint32_t usb_phy_sel_err:1;
-        /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0;
-         *  Indicates a programming error of HUK_GEN_STATE_LOW.
-         */
-        uint32_t huk_gen_state_low_err:6;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err0_reg_t;
-
-/** Type of rd_repeat_err1 register
- *  Programming error record register 1 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0;
-         *  Indicates a programming error of HUK_GEN_STATE_HIGH.
-         */
-        uint32_t km_huk_gen_state_high_err:3;
-        /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0;
-         *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
-         */
-        uint32_t km_rnd_switch_cycle_err:2;
-        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
-         *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
-         */
-        uint32_t km_deploy_only_once_err:4;
-        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
-         *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
-         */
-        uint32_t force_use_key_manager_key_err:4;
-        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
-         *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
-         */
-        uint32_t force_disable_sw_init_key_err:1;
-        /** xts_key_length_256_err : RO; bitpos: [14]; default: 0;
-         *  Indicates a programming error of XTS_KEY_LENGTH_256.
-         */
-        uint32_t xts_key_length_256_err:1;
-        uint32_t reserved_15:1;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of WDT_DELAY_SEL.
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_0.
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_1.
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err1_reg_t;
-
-/** Type of rd_repeat_err2 register
- *  Programming error record register 2 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_2.
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_3.
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_4.
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  Indicates a programming error of KEY_PURPOSE_5.
-         */
-        uint32_t key_purpose_5_err:4;
-        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
-         *  Indicates a programming error of SEC_DPA_LEVEL.
-         */
-        uint32_t sec_dpa_level_err:2;
-        /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0;
-         *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
-         */
-        uint32_t ecdsa_enable_soft_k_err:1;
-        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of CRYPT_DPA_ENABLE.
-         */
-        uint32_t crypt_dpa_enable_err:1;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_EN.
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        uint32_t reserved_22:1;
-        /** flash_type_err : RO; bitpos: [23]; default: 0;
-         *  Indicates a programming error of FLASH_TYPE.
-         */
-        uint32_t flash_type_err:1;
-        /** flash_page_size_err : RO; bitpos: [25:24]; default: 0;
-         *  Indicates a programming error of FLASH_PAGE_SIZE.
-         */
-        uint32_t flash_page_size_err:2;
-        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
-         *  Indicates a programming error of FLASH_ECC_EN.
-         */
-        uint32_t flash_ecc_en_err:1;
-        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
-         *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
-         */
-        uint32_t dis_usb_otg_download_mode_err:1;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  Indicates a programming error of FLASH_TPUW.
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err2_reg_t;
-
-/** Type of rd_repeat_err3 register
- *  Programming error record register 3 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
-         *  Indicates a programming error of DIS_DIRECT_BOOT.
-         */
-        uint32_t dis_direct_boot_err:1;
-        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print_err:1;
-        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
-         *  TBD
-         */
-        uint32_t lock_km_key_err:1;
-        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  Indicates a programming error of UART_PRINT_CONTROL.
-         */
-        uint32_t uart_print_control_err:2;
-        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
-         *  Indicates a programming error of FORCE_SEND_RESUME.
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
-         *  Indicates a programming error of SECURE VERSION.
-         */
-        uint32_t secure_version_err:16;
-        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
-         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
-         */
-        uint32_t secure_boot_disable_fast_wake_err:1;
-        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
-         *  Indicates a programming error of HYS_EN_PAD.
-         */
-        uint32_t hys_en_pad_err:1;
-        /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0;
-         *  Indicates a programming error of DCDC_VSET.
-         */
-        uint32_t dcdc_vset_err:5;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err3_reg_t;
-
-/** Type of rd_repeat_err4 register
- *  Programming error record register 4 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_0.
-         */
-        uint32_t pxa0_tieh_sel_0_err:2;
-        /** pxa0_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_1.
-         */
-        uint32_t pxa0_tieh_sel_1_err:2;
-        /** pxa0_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_2.
-         */
-        uint32_t pxa0_tieh_sel_2_err:2;
-        /** pxa0_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
-         *  Indicates a programming error of 0PXA_TIEH_SEL_3.
-         */
-        uint32_t pxa0_tieh_sel_3_err:2;
-        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
-         *  TBD.
-         */
-        uint32_t km_disable_deploy_mode_err:4;
-        /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0;
-         *  Indicates a programming error of USB_DEVICE_DREFL.
-         */
-        uint32_t usb_device_drefl_err:2;
-        /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0;
-         *  Indicates a programming error of USB_OTG11_DREFL.
-         */
-        uint32_t usb_otg11_drefl_err:2;
-        uint32_t reserved_16:2;
-        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
-         *  Indicates a programming error of HP_PWR_SRC_SEL.
-         */
-        uint32_t hp_pwr_src_sel_err:1;
-        /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0;
-         *  Indicates a programming error of DCDC_VSET_EN.
-         */
-        uint32_t dcdc_vset_en_err:1;
-        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
-         *  Indicates a programming error of DIS_WDT.
-         */
-        uint32_t dis_wdt_err:1;
-        /** dis_swd_err : RO; bitpos: [21]; default: 0;
-         *  Indicates a programming error of DIS_SWD.
-         */
-        uint32_t dis_swd_err:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err4_reg_t;
-
-/** Type of rd_rs_err0 register
- *  Programming error record register 0 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t mac_sys_err_num:3;
-        /** mac_sys_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t mac_sys_fail:1;
-        /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part1_err_num:3;
-        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part1_fail:1;
-        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t usr_data_err_num:3;
-        /** usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  0: Means no failure and that the user data is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t usr_data_fail:1;
-        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key0_err_num:3;
-        /** key0_fail : RO; bitpos: [15]; default: 0;
-         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
-         *  key0 failed and the number of error bytes is over 6.
-         */
-        uint32_t key0_fail:1;
-        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key1_err_num:3;
-        /** key1_fail : RO; bitpos: [19]; default: 0;
-         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
-         *  key1 failed and the number of error bytes is over 6.
-         */
-        uint32_t key1_fail:1;
-        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key2_err_num:3;
-        /** key2_fail : RO; bitpos: [23]; default: 0;
-         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
-         *  key2 failed and the number of error bytes is over 6.
-         */
-        uint32_t key2_fail:1;
-        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key3_err_num:3;
-        /** key3_fail : RO; bitpos: [27]; default: 0;
-         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
-         *  key3 failed and the number of error bytes is over 6.
-         */
-        uint32_t key3_fail:1;
-        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key4_err_num:3;
-        /** key4_fail : RO; bitpos: [31]; default: 0;
-         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
-         *  key4 failed and the number of error bytes is over 6.
-         */
-        uint32_t key4_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_err0_reg_t;
-
-/** Type of rd_rs_err1 register
- *  Programming error record register 1 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key5_err_num:3;
-        /** key5_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
-         *  key5 failed and the number of error bytes is over 6.
-         */
-        uint32_t key5_fail:1;
-        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part2_err_num:3;
-        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part2_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_err1_reg_t;
-
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to force enable eFuse register configuration clock signal.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuration register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
-         */
-        uint32_t op_code:16;
-        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
-         *  Configures which block to use for ECDSA key output.
-         */
-        uint32_t cfg_ecdsa_blk:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
-         *  Indicates the number of block valid bit.
-         */
-        uint32_t blk0_valid_bit_cnt:10;
-        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
-         *  Indicates which block is used for ECDSA key output.
-         */
-        uint32_t cur_ecdsa_blk:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        /** thr_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the read hold time.
-         */
-        uint32_t thr_a:8;
-        /** trd : R/W; bitpos: [15:8]; default: 2;
-         *  Configures the read time.
-         */
-        uint32_t trd:8;
-        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
-         *  Configures the read setup time.
-         */
-        uint32_t tsur_a:8;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
-         *  Configures the waiting time of reading eFuse memory.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
-         *  Configures the programming setup time.
-         */
-        uint32_t tsup_a:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        /** thp_a : R/W; bitpos: [31:24]; default: 1;
-         *  Configures the programming hold time.
-         */
-        uint32_t thp_a:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        /** tpgm : R/W; bitpos: [31:16]; default: 160;
-         *  Configures the active programming time.
-         */
-        uint32_t tpgm:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-/** Type of wr_tim_conf0_rs_bypass register
- *  Configurarion register0 of eFuse programming time parameters and rs bypass
- *  operation.
- */
-typedef union {
-    struct {
-        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to bypass reed solomon correction step.
-         */
-        uint32_t bypass_rs_correction:1;
-        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
-         *  Configures block number of programming twice operation.
-         */
-        uint32_t bypass_rs_blk_num:11;
-        /** update : WT; bitpos: [12]; default: 0;
-         *  Set this bit to update multi-bit register signals.
-         */
-        uint32_t update:1;
-        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
-         *  Configures the inactive programming time.
-         */
-        uint32_t tpgm_inactive:8;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf0_rs_bypass_reg_t;
-
-
-/** Group: EFUSE Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36720720;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
-/** Type of apb2otp_wr_dis register
- *  eFuse apb2otp block0 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 write disable data.
-         */
-        uint32_t apb2otp_block0_wr_dis:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_wr_dis_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
-/** Type of apb2otp_blk0_backup1_w1 register
- *  eFuse apb2otp block0 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word1 data.
-         */
-        uint32_t apb2otp_block0_backup1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
-/** Type of apb2otp_blk0_backup1_w2 register
- *  eFuse apb2otp block0 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word2 data.
-         */
-        uint32_t apb2otp_block0_backup1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
-/** Type of apb2otp_blk0_backup1_w3 register
- *  eFuse apb2otp block0 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word3 data.
-         */
-        uint32_t apb2otp_block0_backup1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
-/** Type of apb2otp_blk0_backup1_w4 register
- *  eFuse apb2otp block0 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word4 data.
-         */
-        uint32_t apb2otp_block0_backup1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
-/** Type of apb2otp_blk0_backup1_w5 register
- *  eFuse apb2otp block0 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup1 word5 data.
-         */
-        uint32_t apb2otp_block0_backup1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
-/** Type of apb2otp_blk0_backup2_w1 register
- *  eFuse apb2otp block0 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word1 data.
-         */
-        uint32_t apb2otp_block0_backup2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
-/** Type of apb2otp_blk0_backup2_w2 register
- *  eFuse apb2otp block0 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word2 data.
-         */
-        uint32_t apb2otp_block0_backup2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
-/** Type of apb2otp_blk0_backup2_w3 register
- *  eFuse apb2otp block0 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word3 data.
-         */
-        uint32_t apb2otp_block0_backup2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
-/** Type of apb2otp_blk0_backup2_w4 register
- *  eFuse apb2otp block0 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word4 data.
-         */
-        uint32_t apb2otp_block0_backup2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
-/** Type of apb2otp_blk0_backup2_w5 register
- *  eFuse apb2otp block0 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup2 word5 data.
-         */
-        uint32_t apb2otp_block0_backup2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
-/** Type of apb2otp_blk0_backup3_w1 register
- *  eFuse apb2otp block0 data register12.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word1 data.
-         */
-        uint32_t apb2otp_block0_backup3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
-/** Type of apb2otp_blk0_backup3_w2 register
- *  eFuse apb2otp block0 data register13.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word2 data.
-         */
-        uint32_t apb2otp_block0_backup3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
-/** Type of apb2otp_blk0_backup3_w3 register
- *  eFuse apb2otp block0 data register14.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word3 data.
-         */
-        uint32_t apb2otp_block0_backup3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
-/** Type of apb2otp_blk0_backup3_w4 register
- *  eFuse apb2otp block0 data register15.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word4 data.
-         */
-        uint32_t apb2otp_block0_backup3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
-/** Type of apb2otp_blk0_backup3_w5 register
- *  eFuse apb2otp block0 data register16.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup3 word5 data.
-         */
-        uint32_t apb2otp_block0_backup3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
-/** Type of apb2otp_blk0_backup4_w1 register
- *  eFuse apb2otp block0 data register17.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word1 data.
-         */
-        uint32_t apb2otp_block0_backup4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
-/** Type of apb2otp_blk0_backup4_w2 register
- *  eFuse apb2otp block0 data register18.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word2 data.
-         */
-        uint32_t apb2otp_block0_backup4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
-/** Type of apb2otp_blk0_backup4_w3 register
- *  eFuse apb2otp block0 data register19.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word3 data.
-         */
-        uint32_t apb2otp_block0_backup4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
-/** Type of apb2otp_blk0_backup4_w4 register
- *  eFuse apb2otp block0 data register20.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word4 data.
-         */
-        uint32_t apb2otp_block0_backup4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
-/** Type of apb2otp_blk0_backup4_w5 register
- *  eFuse apb2otp block0 data register21.
- */
-typedef union {
-    struct {
-        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block0 backup4 word5 data.
-         */
-        uint32_t apb2otp_block0_backup4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk0_backup4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word1 Data */
-/** Type of apb2otp_blk1_w1 register
- *  eFuse apb2otp block1 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word1 data.
-         */
-        uint32_t apb2otp_block1_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word2 Data */
-/** Type of apb2otp_blk1_w2 register
- *  eFuse apb2otp block1 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word2 data.
-         */
-        uint32_t apb2otp_block1_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word3 Data */
-/** Type of apb2otp_blk1_w3 register
- *  eFuse apb2otp block1 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word3 data.
-         */
-        uint32_t apb2otp_block1_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word4 Data */
-/** Type of apb2otp_blk1_w4 register
- *  eFuse apb2otp block1 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word4 data.
-         */
-        uint32_t apb2otp_block1_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word5 Data */
-/** Type of apb2otp_blk1_w5 register
- *  eFuse apb2otp block1 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word5 data.
-         */
-        uint32_t apb2otp_block1_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word6 Data */
-/** Type of apb2otp_blk1_w6 register
- *  eFuse apb2otp block1 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word6 data.
-         */
-        uint32_t apb2otp_block1_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word7 Data */
-/** Type of apb2otp_blk1_w7 register
- *  eFuse apb2otp block1 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word7 data.
-         */
-        uint32_t apb2otp_block1_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word8 Data */
-/** Type of apb2otp_blk1_w8 register
- *  eFuse apb2otp block1 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word8 data.
-         */
-        uint32_t apb2otp_block1_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block1 Word9 Data */
-/** Type of apb2otp_blk1_w9 register
- *  eFuse apb2otp block1 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block1  word9 data.
-         */
-        uint32_t apb2otp_block1_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk1_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word1 Data */
-/** Type of apb2otp_blk2_w1 register
- *  eFuse apb2otp block2 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word1 data.
-         */
-        uint32_t apb2otp_block2_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word2 Data */
-/** Type of apb2otp_blk2_w2 register
- *  eFuse apb2otp block2 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word2 data.
-         */
-        uint32_t apb2otp_block2_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word3 Data */
-/** Type of apb2otp_blk2_w3 register
- *  eFuse apb2otp block2 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word3 data.
-         */
-        uint32_t apb2otp_block2_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word4 Data */
-/** Type of apb2otp_blk2_w4 register
- *  eFuse apb2otp block2 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word4 data.
-         */
-        uint32_t apb2otp_block2_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word5 Data */
-/** Type of apb2otp_blk2_w5 register
- *  eFuse apb2otp block2 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word5 data.
-         */
-        uint32_t apb2otp_block2_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word6 Data */
-/** Type of apb2otp_blk2_w6 register
- *  eFuse apb2otp block2 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word6 data.
-         */
-        uint32_t apb2otp_block2_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word7 Data */
-/** Type of apb2otp_blk2_w7 register
- *  eFuse apb2otp block2 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word7 data.
-         */
-        uint32_t apb2otp_block2_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word8 Data */
-/** Type of apb2otp_blk2_w8 register
- *  eFuse apb2otp block2 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word8 data.
-         */
-        uint32_t apb2otp_block2_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word9 Data */
-/** Type of apb2otp_blk2_w9 register
- *  eFuse apb2otp block2 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word9 data.
-         */
-        uint32_t apb2otp_block2_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word10 Data */
-/** Type of apb2otp_blk2_w10 register
- *  eFuse apb2otp block2 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word10 data.
-         */
-        uint32_t apb2otp_block2_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block2 Word11 Data */
-/** Type of apb2otp_blk2_w11 register
- *  eFuse apb2otp block2 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block2 word11 data.
-         */
-        uint32_t apb2otp_block2_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk2_w11_reg_t;
-
-/** Type of apb2otp_blk10_w11 register
- *  eFuse apb2otp block10 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word11 data.
-         */
-        uint32_t apb2otp_block10_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word1 Data */
-/** Type of apb2otp_blk3_w1 register
- *  eFuse apb2otp block3 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word1 data.
-         */
-        uint32_t apb2otp_block3_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word2 Data */
-/** Type of apb2otp_blk3_w2 register
- *  eFuse apb2otp block3 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word2 data.
-         */
-        uint32_t apb2otp_block3_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word3 Data */
-/** Type of apb2otp_blk3_w3 register
- *  eFuse apb2otp block3 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word3 data.
-         */
-        uint32_t apb2otp_block3_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word4 Data */
-/** Type of apb2otp_blk3_w4 register
- *  eFuse apb2otp block3 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word4 data.
-         */
-        uint32_t apb2otp_block3_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word5 Data */
-/** Type of apb2otp_blk3_w5 register
- *  eFuse apb2otp block3 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word5 data.
-         */
-        uint32_t apb2otp_block3_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word6 Data */
-/** Type of apb2otp_blk3_w6 register
- *  eFuse apb2otp block3 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word6 data.
-         */
-        uint32_t apb2otp_block3_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word7 Data */
-/** Type of apb2otp_blk3_w7 register
- *  eFuse apb2otp block3 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word7 data.
-         */
-        uint32_t apb2otp_block3_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word8 Data */
-/** Type of apb2otp_blk3_w8 register
- *  eFuse apb2otp block3 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word8 data.
-         */
-        uint32_t apb2otp_block3_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word9 Data */
-/** Type of apb2otp_blk3_w9 register
- *  eFuse apb2otp block3 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word9 data.
-         */
-        uint32_t apb2otp_block3_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word10 Data */
-/** Type of apb2otp_blk3_w10 register
- *  eFuse apb2otp block3 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word10 data.
-         */
-        uint32_t apb2otp_block3_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block3 Word11 Data */
-/** Type of apb2otp_blk3_w11 register
- *  eFuse apb2otp block3 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block3 word11 data.
-         */
-        uint32_t apb2otp_block3_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk3_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word1 Data */
-/** Type of apb2otp_blk4_w1 register
- *  eFuse apb2otp block4 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word1 data.
-         */
-        uint32_t apb2otp_block4_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word2 Data */
-/** Type of apb2otp_blk4_w2 register
- *  eFuse apb2otp block4 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word2 data.
-         */
-        uint32_t apb2otp_block4_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word3 Data */
-/** Type of apb2otp_blk4_w3 register
- *  eFuse apb2otp block4 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word3 data.
-         */
-        uint32_t apb2otp_block4_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word4 Data */
-/** Type of apb2otp_blk4_w4 register
- *  eFuse apb2otp block4 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word4 data.
-         */
-        uint32_t apb2otp_block4_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word5 Data */
-/** Type of apb2otp_blk4_w5 register
- *  eFuse apb2otp block4 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word5 data.
-         */
-        uint32_t apb2otp_block4_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word6 Data */
-/** Type of apb2otp_blk4_w6 register
- *  eFuse apb2otp block4 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word6 data.
-         */
-        uint32_t apb2otp_block4_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word7 Data */
-/** Type of apb2otp_blk4_w7 register
- *  eFuse apb2otp block4 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word7 data.
-         */
-        uint32_t apb2otp_block4_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word8 Data */
-/** Type of apb2otp_blk4_w8 register
- *  eFuse apb2otp block4 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word8 data.
-         */
-        uint32_t apb2otp_block4_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word9 Data */
-/** Type of apb2otp_blk4_w9 register
- *  eFuse apb2otp block4 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word9 data.
-         */
-        uint32_t apb2otp_block4_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word10 Data */
-/** Type of apb2otp_blk4_w10 register
- *  eFuse apb2otp block4 data registe10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word10 data.
-         */
-        uint32_t apb2otp_block4_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block4 Word11 Data */
-/** Type of apb2otp_blk4_w11 register
- *  eFuse apb2otp block4 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block4 word11 data.
-         */
-        uint32_t apb2otp_block4_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk4_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word1 Data */
-/** Type of apb2otp_blk5_w1 register
- *  eFuse apb2otp block5 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word1 data.
-         */
-        uint32_t apb2otp_block5_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word2 Data */
-/** Type of apb2otp_blk5_w2 register
- *  eFuse apb2otp block5 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word2 data.
-         */
-        uint32_t apb2otp_block5_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word3 Data */
-/** Type of apb2otp_blk5_w3 register
- *  eFuse apb2otp block5 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word3 data.
-         */
-        uint32_t apb2otp_block5_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word4 Data */
-/** Type of apb2otp_blk5_w4 register
- *  eFuse apb2otp block5 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word4 data.
-         */
-        uint32_t apb2otp_block5_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word5 Data */
-/** Type of apb2otp_blk5_w5 register
- *  eFuse apb2otp block5 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word5 data.
-         */
-        uint32_t apb2otp_block5_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word6 Data */
-/** Type of apb2otp_blk5_w6 register
- *  eFuse apb2otp block5 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word6 data.
-         */
-        uint32_t apb2otp_block5_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word7 Data */
-/** Type of apb2otp_blk5_w7 register
- *  eFuse apb2otp block5 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word7 data.
-         */
-        uint32_t apb2otp_block5_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word8 Data */
-/** Type of apb2otp_blk5_w8 register
- *  eFuse apb2otp block5 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word8 data.
-         */
-        uint32_t apb2otp_block5_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word9 Data */
-/** Type of apb2otp_blk5_w9 register
- *  eFuse apb2otp block5 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word9 data.
-         */
-        uint32_t apb2otp_block5_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word10 Data */
-/** Type of apb2otp_blk5_w10 register
- *  eFuse apb2otp block5 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word10 data.
-         */
-        uint32_t apb2otp_block5_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block5 Word11 Data */
-/** Type of apb2otp_blk5_w11 register
- *  eFuse apb2otp block5 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block5 word11 data.
-         */
-        uint32_t apb2otp_block5_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk5_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word1 Data */
-/** Type of apb2otp_blk6_w1 register
- *  eFuse apb2otp block6 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word1 data.
-         */
-        uint32_t apb2otp_block6_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word2 Data */
-/** Type of apb2otp_blk6_w2 register
- *  eFuse apb2otp block6 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word2 data.
-         */
-        uint32_t apb2otp_block6_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word3 Data */
-/** Type of apb2otp_blk6_w3 register
- *  eFuse apb2otp block6 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word3 data.
-         */
-        uint32_t apb2otp_block6_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word4 Data */
-/** Type of apb2otp_blk6_w4 register
- *  eFuse apb2otp block6 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word4 data.
-         */
-        uint32_t apb2otp_block6_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word5 Data */
-/** Type of apb2otp_blk6_w5 register
- *  eFuse apb2otp block6 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word5 data.
-         */
-        uint32_t apb2otp_block6_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word6 Data */
-/** Type of apb2otp_blk6_w6 register
- *  eFuse apb2otp block6 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word6 data.
-         */
-        uint32_t apb2otp_block6_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word7 Data */
-/** Type of apb2otp_blk6_w7 register
- *  eFuse apb2otp block6 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word7 data.
-         */
-        uint32_t apb2otp_block6_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word8 Data */
-/** Type of apb2otp_blk6_w8 register
- *  eFuse apb2otp block6 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word8 data.
-         */
-        uint32_t apb2otp_block6_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word9 Data */
-/** Type of apb2otp_blk6_w9 register
- *  eFuse apb2otp block6 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word9 data.
-         */
-        uint32_t apb2otp_block6_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word10 Data */
-/** Type of apb2otp_blk6_w10 register
- *  eFuse apb2otp block6 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word10 data.
-         */
-        uint32_t apb2otp_block6_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block6 Word11 Data */
-/** Type of apb2otp_blk6_w11 register
- *  eFuse apb2otp block6 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block6 word11 data.
-         */
-        uint32_t apb2otp_block6_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk6_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word1 Data */
-/** Type of apb2otp_blk7_w1 register
- *  eFuse apb2otp block7 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word1 data.
-         */
-        uint32_t apb2otp_block7_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word2 Data */
-/** Type of apb2otp_blk7_w2 register
- *  eFuse apb2otp block7 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word2 data.
-         */
-        uint32_t apb2otp_block7_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word3 Data */
-/** Type of apb2otp_blk7_w3 register
- *  eFuse apb2otp block7 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word3 data.
-         */
-        uint32_t apb2otp_block7_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word4 Data */
-/** Type of apb2otp_blk7_w4 register
- *  eFuse apb2otp block7 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word4 data.
-         */
-        uint32_t apb2otp_block7_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word5 Data */
-/** Type of apb2otp_blk7_w5 register
- *  eFuse apb2otp block7 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word5 data.
-         */
-        uint32_t apb2otp_block7_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word6 Data */
-/** Type of apb2otp_blk7_w6 register
- *  eFuse apb2otp block7 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word6 data.
-         */
-        uint32_t apb2otp_block7_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word7 Data */
-/** Type of apb2otp_blk7_w7 register
- *  eFuse apb2otp block7 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word7 data.
-         */
-        uint32_t apb2otp_block7_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word8 Data */
-/** Type of apb2otp_blk7_w8 register
- *  eFuse apb2otp block7 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word8 data.
-         */
-        uint32_t apb2otp_block7_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word9 Data */
-/** Type of apb2otp_blk7_w9 register
- *  eFuse apb2otp block7 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word9 data.
-         */
-        uint32_t apb2otp_block7_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word10 Data */
-/** Type of apb2otp_blk7_w10 register
- *  eFuse apb2otp block7 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word10 data.
-         */
-        uint32_t apb2otp_block7_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block7 Word11 Data */
-/** Type of apb2otp_blk7_w11 register
- *  eFuse apb2otp block7 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block7 word11 data.
-         */
-        uint32_t apb2otp_block7_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk7_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word1 Data */
-/** Type of apb2otp_blk8_w1 register
- *  eFuse apb2otp block8 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word1 data.
-         */
-        uint32_t apb2otp_block8_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word2 Data */
-/** Type of apb2otp_blk8_w2 register
- *  eFuse apb2otp block8 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word2 data.
-         */
-        uint32_t apb2otp_block8_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word3 Data */
-/** Type of apb2otp_blk8_w3 register
- *  eFuse apb2otp block8 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word3 data.
-         */
-        uint32_t apb2otp_block8_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word4 Data */
-/** Type of apb2otp_blk8_w4 register
- *  eFuse apb2otp block8 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word4 data.
-         */
-        uint32_t apb2otp_block8_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word5 Data */
-/** Type of apb2otp_blk8_w5 register
- *  eFuse apb2otp block8 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word5 data.
-         */
-        uint32_t apb2otp_block8_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word6 Data */
-/** Type of apb2otp_blk8_w6 register
- *  eFuse apb2otp block8 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word6 data.
-         */
-        uint32_t apb2otp_block8_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word7 Data */
-/** Type of apb2otp_blk8_w7 register
- *  eFuse apb2otp block8 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word7 data.
-         */
-        uint32_t apb2otp_block8_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word8 Data */
-/** Type of apb2otp_blk8_w8 register
- *  eFuse apb2otp block8 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word8 data.
-         */
-        uint32_t apb2otp_block8_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word9 Data */
-/** Type of apb2otp_blk8_w9 register
- *  eFuse apb2otp block8 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word9 data.
-         */
-        uint32_t apb2otp_block8_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word10 Data */
-/** Type of apb2otp_blk8_w10 register
- *  eFuse apb2otp block8 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word10 data.
-         */
-        uint32_t apb2otp_block8_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block8 Word11 Data */
-/** Type of apb2otp_blk8_w11 register
- *  eFuse apb2otp block8 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block8 word11 data.
-         */
-        uint32_t apb2otp_block8_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk8_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word1 Data */
-/** Type of apb2otp_blk9_w1 register
- *  eFuse apb2otp block9 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word1 data.
-         */
-        uint32_t apb2otp_block9_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word2 Data */
-/** Type of apb2otp_blk9_w2 register
- *  eFuse apb2otp block9 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word2 data.
-         */
-        uint32_t apb2otp_block9_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word3 Data */
-/** Type of apb2otp_blk9_w3 register
- *  eFuse apb2otp block9 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word3 data.
-         */
-        uint32_t apb2otp_block9_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word4 Data */
-/** Type of apb2otp_blk9_w4 register
- *  eFuse apb2otp block9 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word4 data.
-         */
-        uint32_t apb2otp_block9_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word5 Data */
-/** Type of apb2otp_blk9_w5 register
- *  eFuse apb2otp block9 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word5 data.
-         */
-        uint32_t apb2otp_block9_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word6 Data */
-/** Type of apb2otp_blk9_w6 register
- *  eFuse apb2otp block9 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word6 data.
-         */
-        uint32_t apb2otp_block9_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word7 Data */
-/** Type of apb2otp_blk9_w7 register
- *  eFuse apb2otp block9 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word7 data.
-         */
-        uint32_t apb2otp_block9_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word8 Data */
-/** Type of apb2otp_blk9_w8 register
- *  eFuse apb2otp block9 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word8 data.
-         */
-        uint32_t apb2otp_block9_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word9 Data */
-/** Type of apb2otp_blk9_w9 register
- *  eFuse apb2otp block9 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word9 data.
-         */
-        uint32_t apb2otp_block9_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word10 Data */
-/** Type of apb2otp_blk9_w10 register
- *  eFuse apb2otp block9 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word10 data.
-         */
-        uint32_t apb2otp_block9_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block9 Word11 Data */
-/** Type of apb2otp_blk9_w11 register
- *  eFuse apb2otp block9 data register11.
- */
-typedef union {
-    struct {
-        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block9 word11 data.
-         */
-        uint32_t apb2otp_block9_w11:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk9_w11_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word1 Data */
-/** Type of apb2otp_blk10_w1 register
- *  eFuse apb2otp block10 data register1.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word1 data.
-         */
-        uint32_t apb2otp_block10_w1:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w1_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word2 Data */
-/** Type of apb2otp_blk10_w2 register
- *  eFuse apb2otp block10 data register2.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word2 data.
-         */
-        uint32_t apb2otp_block10_w2:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w2_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word3 Data */
-/** Type of apb2otp_blk10_w3 register
- *  eFuse apb2otp block10 data register3.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word3 data.
-         */
-        uint32_t apb2otp_block10_w3:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w3_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word4 Data */
-/** Type of apb2otp_blk10_w4 register
- *  eFuse apb2otp block10 data register4.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word4 data.
-         */
-        uint32_t apb2otp_block10_w4:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w4_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word5 Data */
-/** Type of apb2otp_blk10_w5 register
- *  eFuse apb2otp block10 data register5.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word5 data.
-         */
-        uint32_t apb2otp_block10_w5:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w5_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word6 Data */
-/** Type of apb2otp_blk10_w6 register
- *  eFuse apb2otp block10 data register6.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word6 data.
-         */
-        uint32_t apb2otp_block10_w6:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w6_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word7 Data */
-/** Type of apb2otp_blk10_w7 register
- *  eFuse apb2otp block10 data register7.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word7 data.
-         */
-        uint32_t apb2otp_block10_w7:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w7_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word8 Data */
-/** Type of apb2otp_blk10_w8 register
- *  eFuse apb2otp block10 data register8.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word8 data.
-         */
-        uint32_t apb2otp_block10_w8:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w8_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word9 Data */
-/** Type of apb2otp_blk10_w9 register
- *  eFuse apb2otp block10 data register9.
- */
-typedef union {
-    struct {
-        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word9 data.
-         */
-        uint32_t apb2otp_block10_w9:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w9_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Block10 Word10 Data */
-/** Type of apb2otp_blk10_w10 register
- *  eFuse apb2otp block10 data register10.
- */
-typedef union {
-    struct {
-        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
-         *  Otp block10 word10 data.
-         */
-        uint32_t apb2otp_block19_w10:32;
-    };
-    uint32_t val;
-} efuse_apb2otp_blk10_w10_reg_t;
-
-
-/** Group: EFUSE_APB2OTP Function Enable Signal */
-/** Type of apb2otp_en register
- *  eFuse apb2otp enable configuration register.
- */
-typedef union {
-    struct {
-        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
-         *  Apb2otp mode enable signal.
-         */
-        uint32_t apb2otp_apb2otp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} efuse_apb2otp_en_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
-    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
-    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
-    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
-    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
-    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
-    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
-    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
-    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
-    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
-    uint32_t reserved_190[12];
-    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
-    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
-    volatile efuse_date_reg_t date;
-    uint32_t reserved_200[384];
-    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
-    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
-    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
-    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
-    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
-    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
-    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
-    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
-    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
-    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
-    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
-    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
-    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
-    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
-    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
-    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
-    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
-    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
-    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
-    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
-    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
-    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
-    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
-    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
-    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
-    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
-    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
-    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
-    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
-    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
-    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
-    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
-    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
-    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
-    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
-    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
-    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
-    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
-    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
-    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
-    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
-    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
-    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
-    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
-    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
-    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
-    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
-    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
-    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
-    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
-    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
-    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
-    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
-    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
-    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
-    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
-    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
-    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
-    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
-    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
-    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
-    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
-    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
-    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
-    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
-    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
-    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
-    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
-    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
-    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
-    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
-    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
-    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
-    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
-    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
-    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
-    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
-    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
-    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
-    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
-    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
-    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
-    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
-    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
-    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
-    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
-    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
-    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
-    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
-    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
-    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
-    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
-    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
-    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
-    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
-    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
-    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
-    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
-    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
-    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
-    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
-    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
-    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
-    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
-    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
-    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
-    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
-    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
-    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
-    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
-    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
-    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
-    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
-    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
-    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
-    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
-    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
-    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
-    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
-    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
-    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
-    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
-    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
-    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
-    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
-    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
-    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
-    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
-    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
-    uint32_t reserved_a04;
-    volatile efuse_apb2otp_en_reg_t apb2otp_en;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/emac_ptp_struct.h b/components/soc/esp32p4/include/soc/emac_ptp_struct.h
new file mode 100644
index 00000000000..ef01da6f8a7
--- /dev/null
+++ b/components/soc/esp32p4/include/soc/emac_ptp_struct.h
@@ -0,0 +1,268 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct emac_ptp_dev_s {
+    volatile union{
+        struct {
+            uint32_t en_timestamp : 1;                /* Timestamp Enable */
+            uint32_t ts_fine_coarse_update : 1;       /* Timestamp Fine or Coarse Update */
+            uint32_t ts_initialize : 1;               /* Timestamp Initialize */
+            uint32_t ts_update : 1;                   /* Timestamp Update */
+            uint32_t en_ts_int_trig : 1;              /* Timestamp Interrupt Trigger Enable */
+            uint32_t addend_reg_update : 1;           /* Addend Reg Update */
+            uint32_t reserved1 : 2;                   /* Reserved */
+            uint32_t en_ts4all : 1;                   /* Enable Timestamp for All Frames */
+            uint32_t ts_digit_bin_roll_ctrl : 1;      /* Timestamp Digital or Binary Rollover Control */
+            uint32_t en_ptp_pkg_proc_ver2_fmt : 1;    /* Enable PTP packet Processing for Version 2 Format */
+            uint32_t en_proc_ptp_ether_frm : 1;       /* Enable Processing of PTP over Ethernet Frames */
+            uint32_t en_proc_ptp_ipv6_udp : 1;        /* Enable Processing of PTP Frames Sent over IPv6-UDP */
+            uint32_t en_proc_ptp_ipv4_udp : 1;        /* Enable Processing of PTP Frames Sent over IPv4-UDP */
+            uint32_t en_ts_snap_event_msg : 1;        /* Enable Timestamp Snapshot for Event Messages */
+            uint32_t en_snap_msg_relevant_master : 1; /* Enable Snapshot for Messages Relevant to Master */
+            uint32_t sel_snap_type : 2;               /* Select PTP packets for Taking Snapshots */
+            uint32_t en_mac_addr_filter : 1;          /* Enable MAC address for PTP Frame Filtering */
+            uint32_t reserved2 : 5;                   /* Reserved */
+            uint32_t aux_snap_fifo_clear : 1;         /* Auxiliary Snapshot FIFO Clear */
+            uint32_t en_aux_snap0 : 1;                /* Auxiliary Snapshot 0 Enable */
+            uint32_t en_aux_snap1 : 1;                /* Auxiliary Snapshot 1 Enable */
+            uint32_t en_aux_snap2 : 1;                /* Auxiliary Snapshot 2 Enable */
+            uint32_t en_aux_snap3 : 1;                /* Auxiliary Snapshot 3 Enable */
+            uint32_t reserved3 : 3;                   /* Reserved */
+        };
+        uint32_t val;
+    } timestamp_ctrl;
+    volatile union{
+        struct {
+            uint32_t sub_second_incre_value : 8; /* Sub-second Increment Value */
+            uint32_t reserved : 24;              /* Reserved */
+        };
+        uint32_t val;
+    } sub_sec_incre;
+    volatile union{
+        struct {
+            uint32_t ts_second : 32; /* Timestamp Second */
+        };
+        uint32_t val;
+    } sys_seconds;
+    volatile union{
+        struct {
+            uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */
+            uint32_t reserved: 1;         /* Reserved */
+        };
+        uint32_t val;
+    } sys_nanosec;
+    volatile union{
+        struct {
+            uint32_t ts_second : 32; /* Timestamp Second */
+        };
+        uint32_t val;
+    } sys_seconds_update;
+    volatile union{
+        struct {
+            uint32_t ts_sub_seconds : 31; /* Timestamp Sub Seconds */
+            uint32_t add_sub : 1;         /* Add or Subtract Time */
+        };
+        uint32_t val;
+    } sys_nanosec_update;
+    volatile union{
+        struct {
+            uint32_t ts_addend_val: 32; /* Timestamp Addend Register */
+        };
+        uint32_t val;
+    } timestamp_addend;
+    volatile union{
+        struct {
+            uint32_t tgt_time_second_val : 32; /* Target Time Seconds Register */
+        };
+        uint32_t val;
+    } tgt_seconds;
+    volatile union{
+        struct {
+            uint32_t tgt_ts_low_reg : 31;   /* Target Timestamp Low Register */
+            uint32_t tgt_time_reg_busy : 1; /* Target Time Register Busy */
+        };
+        uint32_t val;
+    } tgt_nanosec;
+    volatile union{
+        struct {
+            uint32_t ts_higher_word : 16; /* Timestamp Higher Word Register */
+            uint32_t reserved : 16;       /* Reserved */
+        };
+        uint32_t val;
+    } sys_seconds_high;
+    volatile union{
+        struct {
+            uint32_t ts_secons_ovf : 1;             /* Timestamp Seconds Overflow */
+            uint32_t ts_tgt_time_reach : 1;         /* Timestamp Target Time Reached */
+            uint32_t aux_ts_trig_snap : 1;          /* Auxiliary Timestamp Trigger Snapshot */
+            uint32_t ts_tgt_time_err : 1;           /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps1 : 1;    /* Timestamp Target Time Reached for Target Time PPS1 */
+            uint32_t ts_tgt_time_err1 : 1;          /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps2 : 1;    /* Timestamp Target Time Reached for Target Time PPS2 */
+            uint32_t ts_tgt_time_err2 : 1;          /* Timestamp Target Time Error */
+            uint32_t ts_tgt_time_reach_pps3 : 1;    /* Timestamp Target Time Reached for Target Time PPS3 */
+            uint32_t ts_tgt_time_err3 : 1;          /* Timestamp Target Time Error */
+            uint32_t reserved1 : 6;                 /* Reserved */
+            uint32_t aux_ts_snap_trig_identify : 4; /* Auxiliary Timestamp Snapshot Trigger Identifier */
+            uint32_t reserved2 : 4;                 /* Reserved */
+            uint32_t aux_tx_snap_trig_miss : 1;     /* Auxiliary Timestamp Snapshot Trigger Missed */
+            uint32_t aux_ts_snap_num : 5;           /* Number of Auxiliary Timestamp Snapshots */
+            uint32_t reserved : 2;                  /* Reserved */
+        };
+        uint32_t val;
+    } status;
+    volatile union{
+        struct {
+            uint32_t pps_cmd0 : 4;      /* Flexible PPS0 Output Control */
+            uint32_t en_pps0 : 1;       /* Flexible PPS Output Mode Enable */
+            uint32_t tgt_mode_sel0 : 2; /* Target Time Register Mode for PPS0 Output */
+            uint32_t reserved1 : 1;     /* Reserved */
+            uint32_t pps_cmd1 : 3;      /* Flexible PPS1 Output Control */
+            uint32_t reserved2 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel1 : 2; /* Target Time Register Mode for PPS1 Output */
+            uint32_t reserved3 : 1;     /* Reserved */
+            uint32_t pps_cmd2 : 3;      /* Flexible PPS2 Output Control */
+            uint32_t reserved4 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel2 : 2; /* Target Time Register Mode for PPS2 Output */
+            uint32_t reserved5 : 1;     /* Reserved */
+            uint32_t pps_cmd3 : 3;      /* Flexible PPS3 Output Control */
+            uint32_t reserved6 : 2;     /* Reserved */
+            uint32_t tgt_mode_sel3 : 2; /* Target Time Register Mode for PPS3 Output */
+            uint32_t reserved7 : 1;     /* Reserved */
+        };
+        uint32_t val;
+    } pps_ctrl;
+    volatile union{
+        struct {
+            uint32_t aux_ts_low : 31; /* Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. */
+            uint32_t reserved : 1;    /* Reserved */
+        };
+        uint32_t val;
+    } aux_nanosec;
+    volatile union{
+        struct {
+            uint32_t aux_tx_high : 32; /* Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */
+        };
+        uint32_t val;
+    } aux_seconds;
+    volatile union{
+        struct {
+            uint32_t av_ethertype_val : 16;       /* AV EtherType Value */
+            uint32_t ac_queue_pri : 3;            /* AV Priority for Queuing */
+            uint32_t en_queue_non_av_pkt : 1;     /* VLAN Tagged Non-AV Packets Queueing Enable */
+            uint32_t dis_av_chann : 1;            /* AV Channel Disable */
+            uint32_t queue_av_ctrl_pkt_chann : 2; /* Channel for Queuing the AV Control Packets */
+            uint32_t reserved1 : 1;               /* Reserved */
+            uint32_t queue_ptp_pkt_chann : 2;     /* Channel for Queuing the PTP Packets */
+            uint32_t reserved2 : 6;               /* Reserved */
+        };
+        uint32_t val;
+    } av_mac_ctrl;
+    uint32_t reserved1[9]; /* Reserved */
+    volatile union{
+        struct {
+            uint32_t pps0_interval : 32; /* PPS0 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps0_interval;
+    volatile union{
+        struct {
+            uint32_t pps0_width : 32; /* PPS0 Output Signal Width */
+        };
+        uint32_t val;
+    } pps0_width;
+    uint32_t reserved2[6]; /* Reserved */
+    volatile union{
+        struct {
+            uint32_t pps1_tgt_seconds : 32; /* PPS1 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps1_tgt_seconds;
+    volatile union{
+        struct {
+            uint32_t pps1_tgt_nanosec : 31;  /* Target Time Low for PPS1 Register */
+            uint32_t pps1_tgt_time_busy : 1; /* PPS1 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps1_tgt_nanosec;
+    volatile union{
+        struct {
+            uint32_t pps1_interval : 32; /* PPS1 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps1_interval;
+    volatile union{
+        struct {
+            uint32_t pps1_width : 32; /* PPS1 Output Signal Width */
+        };
+        uint32_t val;
+    } pps1_width;
+    uint32_t reserved3[4]; /* Reserved */
+    volatile union{
+        struct {
+            uint32_t pps2_tgt_seconds : 32; /* PPS2 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps2_tgt_seconds;
+    volatile union{
+        struct {
+            uint32_t pps2_tgt_nanosec : 31;  /* Target Time Low for PPS2 Register */
+            uint32_t pps2_tgt_time_busy : 1; /* PPS2 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps2_tgt_nanosec;
+    volatile union{
+        struct {
+            uint32_t pps2_interval : 32; /* PPS2 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps2_interval;
+    volatile union{
+        struct {
+            uint32_t pps2_width : 32; /* PPS2 Output Signal Width */
+        };
+        uint32_t val;
+    } pps2_width;
+    uint32_t reserved4[4]; /* Reserved */
+    volatile union{
+        struct {
+            uint32_t pps3_tgt_seconds : 32; /* PPS3 Target Time Seconds Register */
+        };
+        uint32_t val;
+    } pps3_tgt_seconds;
+    volatile union{
+        struct {
+            uint32_t pps3_tgt_nanosec : 31;  /* Target Time Low for PPS3 Register */
+            uint32_t pps3_tgt_time_busy : 1; /* PPS3 Target Time Register Busy */
+        };
+        uint32_t val;
+    } pps3_tgt_nanosec;
+    volatile union{
+        struct {
+            uint32_t pps3_interval : 32; /* PPS3 Output Signal Interval */
+        };
+        uint32_t val;
+    } pps3_interval;
+    volatile union{
+        struct {
+            uint32_t pps3_width : 32; /* PPS3 Output Signal Width */
+        };
+        uint32_t val;
+    } pps3_width;
+} emac_ptp_dev_t;
+
+extern emac_ptp_dev_t EMAC_PTP;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/gpio_reg.h b/components/soc/esp32p4/include/soc/gpio_reg.h
deleted file mode 100644
index 014c3753940..00000000000
--- a/components/soc/esp32p4/include/soc/gpio_reg.h
+++ /dev/null
@@ -1,12210 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** GPIO_BT_SELECT_REG register
- *  GPIO bit select register
- */
-#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0)
-/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0;
- *  GPIO bit select register
- */
-#define GPIO_BT_SEL    0xFFFFFFFFU
-#define GPIO_BT_SEL_M  (GPIO_BT_SEL_V << GPIO_BT_SEL_S)
-#define GPIO_BT_SEL_V  0xFFFFFFFFU
-#define GPIO_BT_SEL_S  0
-
-/** GPIO_OUT_REG register
- *  GPIO output register for GPIO0-31
- */
-#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
-/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0;
- *  GPIO output register for GPIO0-31
- */
-#define GPIO_OUT_DATA_ORIG    0xFFFFFFFFU
-#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
-#define GPIO_OUT_DATA_ORIG_V  0xFFFFFFFFU
-#define GPIO_OUT_DATA_ORIG_S  0
-
-/** GPIO_OUT_W1TS_REG register
- *  GPIO output set register for GPIO0-31
- */
-#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
-/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0;
- *  GPIO output set register for GPIO0-31
- */
-#define GPIO_OUT_W1TS    0xFFFFFFFFU
-#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
-#define GPIO_OUT_W1TS_V  0xFFFFFFFFU
-#define GPIO_OUT_W1TS_S  0
-
-/** GPIO_OUT_W1TC_REG register
- *  GPIO output clear register for GPIO0-31
- */
-#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
-/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0;
- *  GPIO output clear register for GPIO0-31
- */
-#define GPIO_OUT_W1TC    0xFFFFFFFFU
-#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
-#define GPIO_OUT_W1TC_V  0xFFFFFFFFU
-#define GPIO_OUT_W1TC_S  0
-
-/** GPIO_OUT1_REG register
- *  GPIO output register for GPIO32-56
- */
-#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10)
-/** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [24:0]; default: 0;
- *  GPIO output register for GPIO32-56
- */
-#define GPIO_OUT1_DATA_ORIG    0x01FFFFFFU
-#define GPIO_OUT1_DATA_ORIG_M  (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S)
-#define GPIO_OUT1_DATA_ORIG_V  0x01FFFFFFU
-#define GPIO_OUT1_DATA_ORIG_S  0
-
-/** GPIO_OUT1_W1TS_REG register
- *  GPIO output set register for GPIO32-56
- */
-#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14)
-/** GPIO_OUT1_W1TS : WT; bitpos: [24:0]; default: 0;
- *  GPIO output set register for GPIO32-56
- */
-#define GPIO_OUT1_W1TS    0x01FFFFFFU
-#define GPIO_OUT1_W1TS_M  (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S)
-#define GPIO_OUT1_W1TS_V  0x01FFFFFFU
-#define GPIO_OUT1_W1TS_S  0
-
-/** GPIO_OUT1_W1TC_REG register
- *  GPIO output clear register for GPIO32-56
- */
-#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18)
-/** GPIO_OUT1_W1TC : WT; bitpos: [24:0]; default: 0;
- *  GPIO output clear register for GPIO32-56
- */
-#define GPIO_OUT1_W1TC    0x01FFFFFFU
-#define GPIO_OUT1_W1TC_M  (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S)
-#define GPIO_OUT1_W1TC_V  0x01FFFFFFU
-#define GPIO_OUT1_W1TC_S  0
-
-/** GPIO_ENABLE_REG register
- *  GPIO output enable register for GPIO0-31
- */
-#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20)
-/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0;
- *  GPIO output enable register for GPIO0-31
- */
-#define GPIO_ENABLE_DATA    0xFFFFFFFFU
-#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
-#define GPIO_ENABLE_DATA_V  0xFFFFFFFFU
-#define GPIO_ENABLE_DATA_S  0
-
-/** GPIO_ENABLE_W1TS_REG register
- *  GPIO output enable set register for GPIO0-31
- */
-#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24)
-/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0;
- *  GPIO output enable set register for GPIO0-31
- */
-#define GPIO_ENABLE_W1TS    0xFFFFFFFFU
-#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
-#define GPIO_ENABLE_W1TS_V  0xFFFFFFFFU
-#define GPIO_ENABLE_W1TS_S  0
-
-/** GPIO_ENABLE_W1TC_REG register
- *  GPIO output enable clear register for GPIO0-31
- */
-#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28)
-/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0;
- *  GPIO output enable clear register for GPIO0-31
- */
-#define GPIO_ENABLE_W1TC    0xFFFFFFFFU
-#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
-#define GPIO_ENABLE_W1TC_V  0xFFFFFFFFU
-#define GPIO_ENABLE_W1TC_S  0
-
-/** GPIO_ENABLE1_REG register
- *  GPIO output enable register for GPIO32-56
- */
-#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c)
-/** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [24:0]; default: 0;
- *  GPIO output enable register for GPIO32-56
- */
-#define GPIO_ENABLE1_DATA    0x01FFFFFFU
-#define GPIO_ENABLE1_DATA_M  (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S)
-#define GPIO_ENABLE1_DATA_V  0x01FFFFFFU
-#define GPIO_ENABLE1_DATA_S  0
-
-/** GPIO_ENABLE1_W1TS_REG register
- *  GPIO output enable set register for GPIO32-56
- */
-#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30)
-/** GPIO_ENABLE1_W1TS : WT; bitpos: [24:0]; default: 0;
- *  GPIO output enable set register for GPIO32-56
- */
-#define GPIO_ENABLE1_W1TS    0x01FFFFFFU
-#define GPIO_ENABLE1_W1TS_M  (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S)
-#define GPIO_ENABLE1_W1TS_V  0x01FFFFFFU
-#define GPIO_ENABLE1_W1TS_S  0
-
-/** GPIO_ENABLE1_W1TC_REG register
- *  GPIO output enable clear register for GPIO32-56
- */
-#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34)
-/** GPIO_ENABLE1_W1TC : WT; bitpos: [24:0]; default: 0;
- *  GPIO output enable clear register for GPIO32-56
- */
-#define GPIO_ENABLE1_W1TC    0x01FFFFFFU
-#define GPIO_ENABLE1_W1TC_M  (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S)
-#define GPIO_ENABLE1_W1TC_V  0x01FFFFFFU
-#define GPIO_ENABLE1_W1TC_S  0
-
-/** GPIO_STRAP_REG register
- *  pad strapping register
- */
-#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38)
-/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
- *  pad strapping register
- */
-#define GPIO_STRAPPING    0x0000FFFFU
-#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
-#define GPIO_STRAPPING_V  0x0000FFFFU
-#define GPIO_STRAPPING_S  0
-
-/** GPIO_IN_REG register
- *  GPIO input register for GPIO0-31
- */
-#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c)
-/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0;
- *  GPIO input register for GPIO0-31
- */
-#define GPIO_IN_DATA_NEXT    0xFFFFFFFFU
-#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
-#define GPIO_IN_DATA_NEXT_V  0xFFFFFFFFU
-#define GPIO_IN_DATA_NEXT_S  0
-
-/** GPIO_IN1_REG register
- *  GPIO input register for GPIO32-56
- */
-#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40)
-/** GPIO_IN1_DATA_NEXT : RO; bitpos: [24:0]; default: 0;
- *  GPIO input register for GPIO32-56
- */
-#define GPIO_IN1_DATA_NEXT    0x01FFFFFFU
-#define GPIO_IN1_DATA_NEXT_M  (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S)
-#define GPIO_IN1_DATA_NEXT_V  0x01FFFFFFU
-#define GPIO_IN1_DATA_NEXT_S  0
-
-/** GPIO_STATUS_REG register
- *  GPIO interrupt status register for GPIO0-31
- */
-#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44)
-/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0;
- *  GPIO interrupt status register for GPIO0-31
- */
-#define GPIO_STATUS_INTERRUPT    0xFFFFFFFFU
-#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
-#define GPIO_STATUS_INTERRUPT_V  0xFFFFFFFFU
-#define GPIO_STATUS_INTERRUPT_S  0
-
-/** GPIO_STATUS_W1TS_REG register
- *  GPIO interrupt status set register for GPIO0-31
- */
-#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48)
-/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0;
- *  GPIO interrupt status set register for GPIO0-31
- */
-#define GPIO_STATUS_W1TS    0xFFFFFFFFU
-#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
-#define GPIO_STATUS_W1TS_V  0xFFFFFFFFU
-#define GPIO_STATUS_W1TS_S  0
-
-/** GPIO_STATUS_W1TC_REG register
- *  GPIO interrupt status clear register for GPIO0-31
- */
-#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c)
-/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0;
- *  GPIO interrupt status clear register for GPIO0-31
- */
-#define GPIO_STATUS_W1TC    0xFFFFFFFFU
-#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
-#define GPIO_STATUS_W1TC_V  0xFFFFFFFFU
-#define GPIO_STATUS_W1TC_S  0
-
-/** GPIO_STATUS1_REG register
- *  GPIO interrupt status register for GPIO32-56
- */
-#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50)
-/** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [24:0]; default: 0;
- *  GPIO interrupt status register for GPIO32-56
- */
-#define GPIO_STATUS1_INTERRUPT    0x01FFFFFFU
-#define GPIO_STATUS1_INTERRUPT_M  (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S)
-#define GPIO_STATUS1_INTERRUPT_V  0x01FFFFFFU
-#define GPIO_STATUS1_INTERRUPT_S  0
-
-/** GPIO_STATUS1_W1TS_REG register
- *  GPIO interrupt status set register for GPIO32-56
- */
-#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54)
-/** GPIO_STATUS1_W1TS : WT; bitpos: [24:0]; default: 0;
- *  GPIO interrupt status set register for GPIO32-56
- */
-#define GPIO_STATUS1_W1TS    0x01FFFFFFU
-#define GPIO_STATUS1_W1TS_M  (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S)
-#define GPIO_STATUS1_W1TS_V  0x01FFFFFFU
-#define GPIO_STATUS1_W1TS_S  0
-
-/** GPIO_STATUS1_W1TC_REG register
- *  GPIO interrupt status clear register for GPIO32-56
- */
-#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58)
-/** GPIO_STATUS1_W1TC : WT; bitpos: [24:0]; default: 0;
- *  GPIO interrupt status clear register for GPIO32-56
- */
-#define GPIO_STATUS1_W1TC    0x01FFFFFFU
-#define GPIO_STATUS1_W1TC_M  (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S)
-#define GPIO_STATUS1_W1TC_V  0x01FFFFFFU
-#define GPIO_STATUS1_W1TC_S  0
-
-/** GPIO_INTR_0_REG register
- *  GPIO interrupt 0 status register for GPIO0-31
- */
-#define GPIO_INTR_0_REG (DR_REG_GPIO_BASE + 0x5c)
-/** GPIO_INT_0 : RO; bitpos: [31:0]; default: 0;
- *  GPIO interrupt 0 status register for GPIO0-31
- */
-#define GPIO_INT_0    0xFFFFFFFFU
-#define GPIO_INT_0_M  (GPIO_INT_0_V << GPIO_INT_0_S)
-#define GPIO_INT_0_V  0xFFFFFFFFU
-#define GPIO_INT_0_S  0
-
-/** GPIO_INTR1_0_REG register
- *  GPIO interrupt 0 status register for GPIO32-56
- */
-#define GPIO_INTR1_0_REG (DR_REG_GPIO_BASE + 0x60)
-/** GPIO_INT1_0 : RO; bitpos: [24:0]; default: 0;
- *  GPIO interrupt 0 status register for GPIO32-56
- */
-#define GPIO_INT1_0    0x01FFFFFFU
-#define GPIO_INT1_0_M  (GPIO_INT1_0_V << GPIO_INT1_0_S)
-#define GPIO_INT1_0_V  0x01FFFFFFU
-#define GPIO_INT1_0_S  0
-
-/** GPIO_INTR_1_REG register
- *  GPIO interrupt 1 status register for GPIO0-31
- */
-#define GPIO_INTR_1_REG (DR_REG_GPIO_BASE + 0x64)
-/** GPIO_INT_1 : RO; bitpos: [31:0]; default: 0;
- *  GPIO interrupt 1 status register for GPIO0-31
- */
-#define GPIO_INT_1    0xFFFFFFFFU
-#define GPIO_INT_1_M  (GPIO_INT_1_V << GPIO_INT_1_S)
-#define GPIO_INT_1_V  0xFFFFFFFFU
-#define GPIO_INT_1_S  0
-
-/** GPIO_INTR1_1_REG register
- *  GPIO interrupt 1 status register for GPIO32-56
- */
-#define GPIO_INTR1_1_REG (DR_REG_GPIO_BASE + 0x68)
-/** GPIO_INT1_1 : RO; bitpos: [24:0]; default: 0;
- *  GPIO interrupt 1 status register for GPIO32-56
- */
-#define GPIO_INT1_1    0x01FFFFFFU
-#define GPIO_INT1_1_M  (GPIO_INT1_1_V << GPIO_INT1_1_S)
-#define GPIO_INT1_1_V  0x01FFFFFFU
-#define GPIO_INT1_1_S  0
-
-/** GPIO_STATUS_NEXT_REG register
- *  GPIO interrupt source register for GPIO0-31
- */
-#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x6c)
-/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0;
- *  GPIO interrupt source register for GPIO0-31
- */
-#define GPIO_STATUS_INTERRUPT_NEXT    0xFFFFFFFFU
-#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
-#define GPIO_STATUS_INTERRUPT_NEXT_V  0xFFFFFFFFU
-#define GPIO_STATUS_INTERRUPT_NEXT_S  0
-
-/** GPIO_STATUS_NEXT1_REG register
- *  GPIO interrupt source register for GPIO32-56
- */
-#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x70)
-/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [24:0]; default: 0;
- *  GPIO interrupt source register for GPIO32-56
- */
-#define GPIO_STATUS_INTERRUPT_NEXT1    0x01FFFFFFU
-#define GPIO_STATUS_INTERRUPT_NEXT1_M  (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S)
-#define GPIO_STATUS_INTERRUPT_NEXT1_V  0x01FFFFFFU
-#define GPIO_STATUS_INTERRUPT_NEXT1_S  0
-
-/** GPIO_PIN0_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74)
-/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
-#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN0_SYNC2_BYPASS_S  0
-/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
-#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN0_PAD_DRIVER_S  2
-/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
-#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN0_SYNC1_BYPASS_S  3
-/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN0_INT_TYPE    0x00000007U
-#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
-#define GPIO_PIN0_INT_TYPE_V  0x00000007U
-#define GPIO_PIN0_INT_TYPE_S  7
-/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
-#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN0_WAKEUP_ENABLE_S  10
-/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN0_CONFIG    0x00000003U
-#define GPIO_PIN0_CONFIG_M  (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S)
-#define GPIO_PIN0_CONFIG_V  0x00000003U
-#define GPIO_PIN0_CONFIG_S  11
-/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN0_INT_ENA    0x0000001FU
-#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
-#define GPIO_PIN0_INT_ENA_V  0x0000001FU
-#define GPIO_PIN0_INT_ENA_S  13
-
-/** GPIO_PIN1_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78)
-/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
-#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN1_SYNC2_BYPASS_S  0
-/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
-#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN1_PAD_DRIVER_S  2
-/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
-#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN1_SYNC1_BYPASS_S  3
-/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN1_INT_TYPE    0x00000007U
-#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
-#define GPIO_PIN1_INT_TYPE_V  0x00000007U
-#define GPIO_PIN1_INT_TYPE_S  7
-/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
-#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN1_WAKEUP_ENABLE_S  10
-/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN1_CONFIG    0x00000003U
-#define GPIO_PIN1_CONFIG_M  (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S)
-#define GPIO_PIN1_CONFIG_V  0x00000003U
-#define GPIO_PIN1_CONFIG_S  11
-/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN1_INT_ENA    0x0000001FU
-#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
-#define GPIO_PIN1_INT_ENA_V  0x0000001FU
-#define GPIO_PIN1_INT_ENA_S  13
-
-/** GPIO_PIN2_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c)
-/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
-#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN2_SYNC2_BYPASS_S  0
-/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
-#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN2_PAD_DRIVER_S  2
-/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
-#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN2_SYNC1_BYPASS_S  3
-/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN2_INT_TYPE    0x00000007U
-#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
-#define GPIO_PIN2_INT_TYPE_V  0x00000007U
-#define GPIO_PIN2_INT_TYPE_S  7
-/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
-#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN2_WAKEUP_ENABLE_S  10
-/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN2_CONFIG    0x00000003U
-#define GPIO_PIN2_CONFIG_M  (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S)
-#define GPIO_PIN2_CONFIG_V  0x00000003U
-#define GPIO_PIN2_CONFIG_S  11
-/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN2_INT_ENA    0x0000001FU
-#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
-#define GPIO_PIN2_INT_ENA_V  0x0000001FU
-#define GPIO_PIN2_INT_ENA_S  13
-
-/** GPIO_PIN3_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80)
-/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
-#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN3_SYNC2_BYPASS_S  0
-/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
-#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN3_PAD_DRIVER_S  2
-/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
-#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN3_SYNC1_BYPASS_S  3
-/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN3_INT_TYPE    0x00000007U
-#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
-#define GPIO_PIN3_INT_TYPE_V  0x00000007U
-#define GPIO_PIN3_INT_TYPE_S  7
-/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
-#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN3_WAKEUP_ENABLE_S  10
-/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN3_CONFIG    0x00000003U
-#define GPIO_PIN3_CONFIG_M  (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S)
-#define GPIO_PIN3_CONFIG_V  0x00000003U
-#define GPIO_PIN3_CONFIG_S  11
-/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN3_INT_ENA    0x0000001FU
-#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
-#define GPIO_PIN3_INT_ENA_V  0x0000001FU
-#define GPIO_PIN3_INT_ENA_S  13
-
-/** GPIO_PIN4_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84)
-/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
-#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN4_SYNC2_BYPASS_S  0
-/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
-#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN4_PAD_DRIVER_S  2
-/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
-#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN4_SYNC1_BYPASS_S  3
-/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN4_INT_TYPE    0x00000007U
-#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
-#define GPIO_PIN4_INT_TYPE_V  0x00000007U
-#define GPIO_PIN4_INT_TYPE_S  7
-/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
-#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN4_WAKEUP_ENABLE_S  10
-/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN4_CONFIG    0x00000003U
-#define GPIO_PIN4_CONFIG_M  (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S)
-#define GPIO_PIN4_CONFIG_V  0x00000003U
-#define GPIO_PIN4_CONFIG_S  11
-/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN4_INT_ENA    0x0000001FU
-#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
-#define GPIO_PIN4_INT_ENA_V  0x0000001FU
-#define GPIO_PIN4_INT_ENA_S  13
-
-/** GPIO_PIN5_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88)
-/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
-#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN5_SYNC2_BYPASS_S  0
-/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
-#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN5_PAD_DRIVER_S  2
-/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
-#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN5_SYNC1_BYPASS_S  3
-/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN5_INT_TYPE    0x00000007U
-#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
-#define GPIO_PIN5_INT_TYPE_V  0x00000007U
-#define GPIO_PIN5_INT_TYPE_S  7
-/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
-#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN5_WAKEUP_ENABLE_S  10
-/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN5_CONFIG    0x00000003U
-#define GPIO_PIN5_CONFIG_M  (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S)
-#define GPIO_PIN5_CONFIG_V  0x00000003U
-#define GPIO_PIN5_CONFIG_S  11
-/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN5_INT_ENA    0x0000001FU
-#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
-#define GPIO_PIN5_INT_ENA_V  0x0000001FU
-#define GPIO_PIN5_INT_ENA_S  13
-
-/** GPIO_PIN6_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c)
-/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
-#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN6_SYNC2_BYPASS_S  0
-/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
-#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN6_PAD_DRIVER_S  2
-/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
-#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN6_SYNC1_BYPASS_S  3
-/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN6_INT_TYPE    0x00000007U
-#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
-#define GPIO_PIN6_INT_TYPE_V  0x00000007U
-#define GPIO_PIN6_INT_TYPE_S  7
-/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
-#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN6_WAKEUP_ENABLE_S  10
-/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN6_CONFIG    0x00000003U
-#define GPIO_PIN6_CONFIG_M  (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S)
-#define GPIO_PIN6_CONFIG_V  0x00000003U
-#define GPIO_PIN6_CONFIG_S  11
-/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN6_INT_ENA    0x0000001FU
-#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
-#define GPIO_PIN6_INT_ENA_V  0x0000001FU
-#define GPIO_PIN6_INT_ENA_S  13
-
-/** GPIO_PIN7_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90)
-/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
-#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN7_SYNC2_BYPASS_S  0
-/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
-#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN7_PAD_DRIVER_S  2
-/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
-#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN7_SYNC1_BYPASS_S  3
-/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN7_INT_TYPE    0x00000007U
-#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
-#define GPIO_PIN7_INT_TYPE_V  0x00000007U
-#define GPIO_PIN7_INT_TYPE_S  7
-/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
-#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN7_WAKEUP_ENABLE_S  10
-/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN7_CONFIG    0x00000003U
-#define GPIO_PIN7_CONFIG_M  (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S)
-#define GPIO_PIN7_CONFIG_V  0x00000003U
-#define GPIO_PIN7_CONFIG_S  11
-/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN7_INT_ENA    0x0000001FU
-#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
-#define GPIO_PIN7_INT_ENA_V  0x0000001FU
-#define GPIO_PIN7_INT_ENA_S  13
-
-/** GPIO_PIN8_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94)
-/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
-#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN8_SYNC2_BYPASS_S  0
-/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
-#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN8_PAD_DRIVER_S  2
-/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
-#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN8_SYNC1_BYPASS_S  3
-/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN8_INT_TYPE    0x00000007U
-#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
-#define GPIO_PIN8_INT_TYPE_V  0x00000007U
-#define GPIO_PIN8_INT_TYPE_S  7
-/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
-#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN8_WAKEUP_ENABLE_S  10
-/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN8_CONFIG    0x00000003U
-#define GPIO_PIN8_CONFIG_M  (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S)
-#define GPIO_PIN8_CONFIG_V  0x00000003U
-#define GPIO_PIN8_CONFIG_S  11
-/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN8_INT_ENA    0x0000001FU
-#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
-#define GPIO_PIN8_INT_ENA_V  0x0000001FU
-#define GPIO_PIN8_INT_ENA_S  13
-
-/** GPIO_PIN9_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98)
-/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
-#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN9_SYNC2_BYPASS_S  0
-/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
-#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN9_PAD_DRIVER_S  2
-/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
-#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN9_SYNC1_BYPASS_S  3
-/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN9_INT_TYPE    0x00000007U
-#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
-#define GPIO_PIN9_INT_TYPE_V  0x00000007U
-#define GPIO_PIN9_INT_TYPE_S  7
-/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
-#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN9_WAKEUP_ENABLE_S  10
-/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN9_CONFIG    0x00000003U
-#define GPIO_PIN9_CONFIG_M  (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S)
-#define GPIO_PIN9_CONFIG_V  0x00000003U
-#define GPIO_PIN9_CONFIG_S  11
-/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN9_INT_ENA    0x0000001FU
-#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
-#define GPIO_PIN9_INT_ENA_V  0x0000001FU
-#define GPIO_PIN9_INT_ENA_S  13
-
-/** GPIO_PIN10_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c)
-/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
-#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN10_SYNC2_BYPASS_S  0
-/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
-#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN10_PAD_DRIVER_S  2
-/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
-#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN10_SYNC1_BYPASS_S  3
-/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN10_INT_TYPE    0x00000007U
-#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
-#define GPIO_PIN10_INT_TYPE_V  0x00000007U
-#define GPIO_PIN10_INT_TYPE_S  7
-/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
-#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN10_WAKEUP_ENABLE_S  10
-/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN10_CONFIG    0x00000003U
-#define GPIO_PIN10_CONFIG_M  (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S)
-#define GPIO_PIN10_CONFIG_V  0x00000003U
-#define GPIO_PIN10_CONFIG_S  11
-/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN10_INT_ENA    0x0000001FU
-#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
-#define GPIO_PIN10_INT_ENA_V  0x0000001FU
-#define GPIO_PIN10_INT_ENA_S  13
-
-/** GPIO_PIN11_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0)
-/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
-#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN11_SYNC2_BYPASS_S  0
-/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
-#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN11_PAD_DRIVER_S  2
-/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
-#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN11_SYNC1_BYPASS_S  3
-/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN11_INT_TYPE    0x00000007U
-#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
-#define GPIO_PIN11_INT_TYPE_V  0x00000007U
-#define GPIO_PIN11_INT_TYPE_S  7
-/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
-#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN11_WAKEUP_ENABLE_S  10
-/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN11_CONFIG    0x00000003U
-#define GPIO_PIN11_CONFIG_M  (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S)
-#define GPIO_PIN11_CONFIG_V  0x00000003U
-#define GPIO_PIN11_CONFIG_S  11
-/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN11_INT_ENA    0x0000001FU
-#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
-#define GPIO_PIN11_INT_ENA_V  0x0000001FU
-#define GPIO_PIN11_INT_ENA_S  13
-
-/** GPIO_PIN12_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4)
-/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
-#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN12_SYNC2_BYPASS_S  0
-/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
-#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN12_PAD_DRIVER_S  2
-/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
-#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN12_SYNC1_BYPASS_S  3
-/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN12_INT_TYPE    0x00000007U
-#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
-#define GPIO_PIN12_INT_TYPE_V  0x00000007U
-#define GPIO_PIN12_INT_TYPE_S  7
-/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
-#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN12_WAKEUP_ENABLE_S  10
-/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN12_CONFIG    0x00000003U
-#define GPIO_PIN12_CONFIG_M  (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S)
-#define GPIO_PIN12_CONFIG_V  0x00000003U
-#define GPIO_PIN12_CONFIG_S  11
-/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN12_INT_ENA    0x0000001FU
-#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
-#define GPIO_PIN12_INT_ENA_V  0x0000001FU
-#define GPIO_PIN12_INT_ENA_S  13
-
-/** GPIO_PIN13_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8)
-/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
-#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN13_SYNC2_BYPASS_S  0
-/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
-#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN13_PAD_DRIVER_S  2
-/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
-#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN13_SYNC1_BYPASS_S  3
-/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN13_INT_TYPE    0x00000007U
-#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
-#define GPIO_PIN13_INT_TYPE_V  0x00000007U
-#define GPIO_PIN13_INT_TYPE_S  7
-/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
-#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN13_WAKEUP_ENABLE_S  10
-/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN13_CONFIG    0x00000003U
-#define GPIO_PIN13_CONFIG_M  (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S)
-#define GPIO_PIN13_CONFIG_V  0x00000003U
-#define GPIO_PIN13_CONFIG_S  11
-/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN13_INT_ENA    0x0000001FU
-#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
-#define GPIO_PIN13_INT_ENA_V  0x0000001FU
-#define GPIO_PIN13_INT_ENA_S  13
-
-/** GPIO_PIN14_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac)
-/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
-#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN14_SYNC2_BYPASS_S  0
-/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
-#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN14_PAD_DRIVER_S  2
-/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
-#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN14_SYNC1_BYPASS_S  3
-/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN14_INT_TYPE    0x00000007U
-#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
-#define GPIO_PIN14_INT_TYPE_V  0x00000007U
-#define GPIO_PIN14_INT_TYPE_S  7
-/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
-#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN14_WAKEUP_ENABLE_S  10
-/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN14_CONFIG    0x00000003U
-#define GPIO_PIN14_CONFIG_M  (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S)
-#define GPIO_PIN14_CONFIG_V  0x00000003U
-#define GPIO_PIN14_CONFIG_S  11
-/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN14_INT_ENA    0x0000001FU
-#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
-#define GPIO_PIN14_INT_ENA_V  0x0000001FU
-#define GPIO_PIN14_INT_ENA_S  13
-
-/** GPIO_PIN15_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0)
-/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
-#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN15_SYNC2_BYPASS_S  0
-/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
-#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN15_PAD_DRIVER_S  2
-/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
-#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN15_SYNC1_BYPASS_S  3
-/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN15_INT_TYPE    0x00000007U
-#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
-#define GPIO_PIN15_INT_TYPE_V  0x00000007U
-#define GPIO_PIN15_INT_TYPE_S  7
-/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
-#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN15_WAKEUP_ENABLE_S  10
-/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN15_CONFIG    0x00000003U
-#define GPIO_PIN15_CONFIG_M  (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S)
-#define GPIO_PIN15_CONFIG_V  0x00000003U
-#define GPIO_PIN15_CONFIG_S  11
-/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN15_INT_ENA    0x0000001FU
-#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
-#define GPIO_PIN15_INT_ENA_V  0x0000001FU
-#define GPIO_PIN15_INT_ENA_S  13
-
-/** GPIO_PIN16_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4)
-/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
-#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN16_SYNC2_BYPASS_S  0
-/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
-#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN16_PAD_DRIVER_S  2
-/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
-#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN16_SYNC1_BYPASS_S  3
-/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN16_INT_TYPE    0x00000007U
-#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
-#define GPIO_PIN16_INT_TYPE_V  0x00000007U
-#define GPIO_PIN16_INT_TYPE_S  7
-/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
-#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN16_WAKEUP_ENABLE_S  10
-/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN16_CONFIG    0x00000003U
-#define GPIO_PIN16_CONFIG_M  (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S)
-#define GPIO_PIN16_CONFIG_V  0x00000003U
-#define GPIO_PIN16_CONFIG_S  11
-/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN16_INT_ENA    0x0000001FU
-#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
-#define GPIO_PIN16_INT_ENA_V  0x0000001FU
-#define GPIO_PIN16_INT_ENA_S  13
-
-/** GPIO_PIN17_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8)
-/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
-#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN17_SYNC2_BYPASS_S  0
-/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
-#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN17_PAD_DRIVER_S  2
-/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
-#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN17_SYNC1_BYPASS_S  3
-/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN17_INT_TYPE    0x00000007U
-#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
-#define GPIO_PIN17_INT_TYPE_V  0x00000007U
-#define GPIO_PIN17_INT_TYPE_S  7
-/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
-#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN17_WAKEUP_ENABLE_S  10
-/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN17_CONFIG    0x00000003U
-#define GPIO_PIN17_CONFIG_M  (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S)
-#define GPIO_PIN17_CONFIG_V  0x00000003U
-#define GPIO_PIN17_CONFIG_S  11
-/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN17_INT_ENA    0x0000001FU
-#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
-#define GPIO_PIN17_INT_ENA_V  0x0000001FU
-#define GPIO_PIN17_INT_ENA_S  13
-
-/** GPIO_PIN18_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc)
-/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
-#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN18_SYNC2_BYPASS_S  0
-/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
-#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN18_PAD_DRIVER_S  2
-/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
-#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN18_SYNC1_BYPASS_S  3
-/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN18_INT_TYPE    0x00000007U
-#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
-#define GPIO_PIN18_INT_TYPE_V  0x00000007U
-#define GPIO_PIN18_INT_TYPE_S  7
-/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
-#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN18_WAKEUP_ENABLE_S  10
-/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN18_CONFIG    0x00000003U
-#define GPIO_PIN18_CONFIG_M  (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S)
-#define GPIO_PIN18_CONFIG_V  0x00000003U
-#define GPIO_PIN18_CONFIG_S  11
-/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN18_INT_ENA    0x0000001FU
-#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
-#define GPIO_PIN18_INT_ENA_V  0x0000001FU
-#define GPIO_PIN18_INT_ENA_S  13
-
-/** GPIO_PIN19_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0)
-/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
-#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN19_SYNC2_BYPASS_S  0
-/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
-#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN19_PAD_DRIVER_S  2
-/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
-#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN19_SYNC1_BYPASS_S  3
-/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN19_INT_TYPE    0x00000007U
-#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
-#define GPIO_PIN19_INT_TYPE_V  0x00000007U
-#define GPIO_PIN19_INT_TYPE_S  7
-/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
-#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN19_WAKEUP_ENABLE_S  10
-/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN19_CONFIG    0x00000003U
-#define GPIO_PIN19_CONFIG_M  (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S)
-#define GPIO_PIN19_CONFIG_V  0x00000003U
-#define GPIO_PIN19_CONFIG_S  11
-/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN19_INT_ENA    0x0000001FU
-#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
-#define GPIO_PIN19_INT_ENA_V  0x0000001FU
-#define GPIO_PIN19_INT_ENA_S  13
-
-/** GPIO_PIN20_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4)
-/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
-#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN20_SYNC2_BYPASS_S  0
-/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
-#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN20_PAD_DRIVER_S  2
-/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
-#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN20_SYNC1_BYPASS_S  3
-/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN20_INT_TYPE    0x00000007U
-#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
-#define GPIO_PIN20_INT_TYPE_V  0x00000007U
-#define GPIO_PIN20_INT_TYPE_S  7
-/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
-#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN20_WAKEUP_ENABLE_S  10
-/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN20_CONFIG    0x00000003U
-#define GPIO_PIN20_CONFIG_M  (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S)
-#define GPIO_PIN20_CONFIG_V  0x00000003U
-#define GPIO_PIN20_CONFIG_S  11
-/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN20_INT_ENA    0x0000001FU
-#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
-#define GPIO_PIN20_INT_ENA_V  0x0000001FU
-#define GPIO_PIN20_INT_ENA_S  13
-
-/** GPIO_PIN21_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8)
-/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
-#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN21_SYNC2_BYPASS_S  0
-/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
-#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN21_PAD_DRIVER_S  2
-/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
-#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN21_SYNC1_BYPASS_S  3
-/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN21_INT_TYPE    0x00000007U
-#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
-#define GPIO_PIN21_INT_TYPE_V  0x00000007U
-#define GPIO_PIN21_INT_TYPE_S  7
-/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
-#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN21_WAKEUP_ENABLE_S  10
-/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN21_CONFIG    0x00000003U
-#define GPIO_PIN21_CONFIG_M  (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S)
-#define GPIO_PIN21_CONFIG_V  0x00000003U
-#define GPIO_PIN21_CONFIG_S  11
-/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN21_INT_ENA    0x0000001FU
-#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
-#define GPIO_PIN21_INT_ENA_V  0x0000001FU
-#define GPIO_PIN21_INT_ENA_S  13
-
-/** GPIO_PIN22_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc)
-/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN22_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN22_SYNC2_BYPASS_M  (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
-#define GPIO_PIN22_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN22_SYNC2_BYPASS_S  0
-/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN22_PAD_DRIVER_M  (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
-#define GPIO_PIN22_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN22_PAD_DRIVER_S  2
-/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN22_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN22_SYNC1_BYPASS_M  (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
-#define GPIO_PIN22_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN22_SYNC1_BYPASS_S  3
-/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN22_INT_TYPE    0x00000007U
-#define GPIO_PIN22_INT_TYPE_M  (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
-#define GPIO_PIN22_INT_TYPE_V  0x00000007U
-#define GPIO_PIN22_INT_TYPE_S  7
-/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN22_WAKEUP_ENABLE_M  (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
-#define GPIO_PIN22_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN22_WAKEUP_ENABLE_S  10
-/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN22_CONFIG    0x00000003U
-#define GPIO_PIN22_CONFIG_M  (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S)
-#define GPIO_PIN22_CONFIG_V  0x00000003U
-#define GPIO_PIN22_CONFIG_S  11
-/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN22_INT_ENA    0x0000001FU
-#define GPIO_PIN22_INT_ENA_M  (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
-#define GPIO_PIN22_INT_ENA_V  0x0000001FU
-#define GPIO_PIN22_INT_ENA_S  13
-
-/** GPIO_PIN23_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0)
-/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN23_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN23_SYNC2_BYPASS_M  (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
-#define GPIO_PIN23_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN23_SYNC2_BYPASS_S  0
-/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN23_PAD_DRIVER_M  (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
-#define GPIO_PIN23_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN23_PAD_DRIVER_S  2
-/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN23_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN23_SYNC1_BYPASS_M  (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
-#define GPIO_PIN23_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN23_SYNC1_BYPASS_S  3
-/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN23_INT_TYPE    0x00000007U
-#define GPIO_PIN23_INT_TYPE_M  (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
-#define GPIO_PIN23_INT_TYPE_V  0x00000007U
-#define GPIO_PIN23_INT_TYPE_S  7
-/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN23_WAKEUP_ENABLE_M  (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
-#define GPIO_PIN23_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN23_WAKEUP_ENABLE_S  10
-/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN23_CONFIG    0x00000003U
-#define GPIO_PIN23_CONFIG_M  (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S)
-#define GPIO_PIN23_CONFIG_V  0x00000003U
-#define GPIO_PIN23_CONFIG_S  11
-/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN23_INT_ENA    0x0000001FU
-#define GPIO_PIN23_INT_ENA_M  (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
-#define GPIO_PIN23_INT_ENA_V  0x0000001FU
-#define GPIO_PIN23_INT_ENA_S  13
-
-/** GPIO_PIN24_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4)
-/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN24_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN24_SYNC2_BYPASS_M  (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
-#define GPIO_PIN24_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN24_SYNC2_BYPASS_S  0
-/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN24_PAD_DRIVER_M  (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
-#define GPIO_PIN24_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN24_PAD_DRIVER_S  2
-/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN24_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN24_SYNC1_BYPASS_M  (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
-#define GPIO_PIN24_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN24_SYNC1_BYPASS_S  3
-/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN24_INT_TYPE    0x00000007U
-#define GPIO_PIN24_INT_TYPE_M  (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
-#define GPIO_PIN24_INT_TYPE_V  0x00000007U
-#define GPIO_PIN24_INT_TYPE_S  7
-/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN24_WAKEUP_ENABLE_M  (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
-#define GPIO_PIN24_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN24_WAKEUP_ENABLE_S  10
-/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN24_CONFIG    0x00000003U
-#define GPIO_PIN24_CONFIG_M  (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S)
-#define GPIO_PIN24_CONFIG_V  0x00000003U
-#define GPIO_PIN24_CONFIG_S  11
-/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN24_INT_ENA    0x0000001FU
-#define GPIO_PIN24_INT_ENA_M  (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
-#define GPIO_PIN24_INT_ENA_V  0x0000001FU
-#define GPIO_PIN24_INT_ENA_S  13
-
-/** GPIO_PIN25_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8)
-/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN25_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN25_SYNC2_BYPASS_M  (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S)
-#define GPIO_PIN25_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN25_SYNC2_BYPASS_S  0
-/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN25_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN25_PAD_DRIVER_M  (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S)
-#define GPIO_PIN25_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN25_PAD_DRIVER_S  2
-/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN25_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN25_SYNC1_BYPASS_M  (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S)
-#define GPIO_PIN25_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN25_SYNC1_BYPASS_S  3
-/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN25_INT_TYPE    0x00000007U
-#define GPIO_PIN25_INT_TYPE_M  (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S)
-#define GPIO_PIN25_INT_TYPE_V  0x00000007U
-#define GPIO_PIN25_INT_TYPE_S  7
-/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN25_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN25_WAKEUP_ENABLE_M  (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S)
-#define GPIO_PIN25_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN25_WAKEUP_ENABLE_S  10
-/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN25_CONFIG    0x00000003U
-#define GPIO_PIN25_CONFIG_M  (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S)
-#define GPIO_PIN25_CONFIG_V  0x00000003U
-#define GPIO_PIN25_CONFIG_S  11
-/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN25_INT_ENA    0x0000001FU
-#define GPIO_PIN25_INT_ENA_M  (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S)
-#define GPIO_PIN25_INT_ENA_V  0x0000001FU
-#define GPIO_PIN25_INT_ENA_S  13
-
-/** GPIO_PIN26_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc)
-/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN26_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN26_SYNC2_BYPASS_M  (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S)
-#define GPIO_PIN26_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN26_SYNC2_BYPASS_S  0
-/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN26_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN26_PAD_DRIVER_M  (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S)
-#define GPIO_PIN26_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN26_PAD_DRIVER_S  2
-/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN26_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN26_SYNC1_BYPASS_M  (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S)
-#define GPIO_PIN26_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN26_SYNC1_BYPASS_S  3
-/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN26_INT_TYPE    0x00000007U
-#define GPIO_PIN26_INT_TYPE_M  (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S)
-#define GPIO_PIN26_INT_TYPE_V  0x00000007U
-#define GPIO_PIN26_INT_TYPE_S  7
-/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN26_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN26_WAKEUP_ENABLE_M  (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S)
-#define GPIO_PIN26_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN26_WAKEUP_ENABLE_S  10
-/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN26_CONFIG    0x00000003U
-#define GPIO_PIN26_CONFIG_M  (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S)
-#define GPIO_PIN26_CONFIG_V  0x00000003U
-#define GPIO_PIN26_CONFIG_S  11
-/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN26_INT_ENA    0x0000001FU
-#define GPIO_PIN26_INT_ENA_M  (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S)
-#define GPIO_PIN26_INT_ENA_V  0x0000001FU
-#define GPIO_PIN26_INT_ENA_S  13
-
-/** GPIO_PIN27_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0)
-/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN27_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN27_SYNC2_BYPASS_M  (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S)
-#define GPIO_PIN27_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN27_SYNC2_BYPASS_S  0
-/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN27_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN27_PAD_DRIVER_M  (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S)
-#define GPIO_PIN27_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN27_PAD_DRIVER_S  2
-/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN27_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN27_SYNC1_BYPASS_M  (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S)
-#define GPIO_PIN27_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN27_SYNC1_BYPASS_S  3
-/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN27_INT_TYPE    0x00000007U
-#define GPIO_PIN27_INT_TYPE_M  (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S)
-#define GPIO_PIN27_INT_TYPE_V  0x00000007U
-#define GPIO_PIN27_INT_TYPE_S  7
-/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN27_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN27_WAKEUP_ENABLE_M  (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S)
-#define GPIO_PIN27_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN27_WAKEUP_ENABLE_S  10
-/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN27_CONFIG    0x00000003U
-#define GPIO_PIN27_CONFIG_M  (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S)
-#define GPIO_PIN27_CONFIG_V  0x00000003U
-#define GPIO_PIN27_CONFIG_S  11
-/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN27_INT_ENA    0x0000001FU
-#define GPIO_PIN27_INT_ENA_M  (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S)
-#define GPIO_PIN27_INT_ENA_V  0x0000001FU
-#define GPIO_PIN27_INT_ENA_S  13
-
-/** GPIO_PIN28_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4)
-/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN28_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN28_SYNC2_BYPASS_M  (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S)
-#define GPIO_PIN28_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN28_SYNC2_BYPASS_S  0
-/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN28_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN28_PAD_DRIVER_M  (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S)
-#define GPIO_PIN28_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN28_PAD_DRIVER_S  2
-/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN28_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN28_SYNC1_BYPASS_M  (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S)
-#define GPIO_PIN28_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN28_SYNC1_BYPASS_S  3
-/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN28_INT_TYPE    0x00000007U
-#define GPIO_PIN28_INT_TYPE_M  (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S)
-#define GPIO_PIN28_INT_TYPE_V  0x00000007U
-#define GPIO_PIN28_INT_TYPE_S  7
-/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN28_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN28_WAKEUP_ENABLE_M  (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S)
-#define GPIO_PIN28_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN28_WAKEUP_ENABLE_S  10
-/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN28_CONFIG    0x00000003U
-#define GPIO_PIN28_CONFIG_M  (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S)
-#define GPIO_PIN28_CONFIG_V  0x00000003U
-#define GPIO_PIN28_CONFIG_S  11
-/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN28_INT_ENA    0x0000001FU
-#define GPIO_PIN28_INT_ENA_M  (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S)
-#define GPIO_PIN28_INT_ENA_V  0x0000001FU
-#define GPIO_PIN28_INT_ENA_S  13
-
-/** GPIO_PIN29_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8)
-/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN29_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN29_SYNC2_BYPASS_M  (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S)
-#define GPIO_PIN29_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN29_SYNC2_BYPASS_S  0
-/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN29_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN29_PAD_DRIVER_M  (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S)
-#define GPIO_PIN29_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN29_PAD_DRIVER_S  2
-/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN29_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN29_SYNC1_BYPASS_M  (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S)
-#define GPIO_PIN29_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN29_SYNC1_BYPASS_S  3
-/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN29_INT_TYPE    0x00000007U
-#define GPIO_PIN29_INT_TYPE_M  (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S)
-#define GPIO_PIN29_INT_TYPE_V  0x00000007U
-#define GPIO_PIN29_INT_TYPE_S  7
-/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN29_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN29_WAKEUP_ENABLE_M  (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S)
-#define GPIO_PIN29_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN29_WAKEUP_ENABLE_S  10
-/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN29_CONFIG    0x00000003U
-#define GPIO_PIN29_CONFIG_M  (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S)
-#define GPIO_PIN29_CONFIG_V  0x00000003U
-#define GPIO_PIN29_CONFIG_S  11
-/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN29_INT_ENA    0x0000001FU
-#define GPIO_PIN29_INT_ENA_M  (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S)
-#define GPIO_PIN29_INT_ENA_V  0x0000001FU
-#define GPIO_PIN29_INT_ENA_S  13
-
-/** GPIO_PIN30_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec)
-/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN30_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN30_SYNC2_BYPASS_M  (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S)
-#define GPIO_PIN30_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN30_SYNC2_BYPASS_S  0
-/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN30_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN30_PAD_DRIVER_M  (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S)
-#define GPIO_PIN30_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN30_PAD_DRIVER_S  2
-/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN30_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN30_SYNC1_BYPASS_M  (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S)
-#define GPIO_PIN30_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN30_SYNC1_BYPASS_S  3
-/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN30_INT_TYPE    0x00000007U
-#define GPIO_PIN30_INT_TYPE_M  (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S)
-#define GPIO_PIN30_INT_TYPE_V  0x00000007U
-#define GPIO_PIN30_INT_TYPE_S  7
-/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN30_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN30_WAKEUP_ENABLE_M  (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S)
-#define GPIO_PIN30_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN30_WAKEUP_ENABLE_S  10
-/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN30_CONFIG    0x00000003U
-#define GPIO_PIN30_CONFIG_M  (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S)
-#define GPIO_PIN30_CONFIG_V  0x00000003U
-#define GPIO_PIN30_CONFIG_S  11
-/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN30_INT_ENA    0x0000001FU
-#define GPIO_PIN30_INT_ENA_M  (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S)
-#define GPIO_PIN30_INT_ENA_V  0x0000001FU
-#define GPIO_PIN30_INT_ENA_S  13
-
-/** GPIO_PIN31_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0)
-/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN31_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN31_SYNC2_BYPASS_M  (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S)
-#define GPIO_PIN31_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN31_SYNC2_BYPASS_S  0
-/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN31_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN31_PAD_DRIVER_M  (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S)
-#define GPIO_PIN31_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN31_PAD_DRIVER_S  2
-/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN31_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN31_SYNC1_BYPASS_M  (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S)
-#define GPIO_PIN31_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN31_SYNC1_BYPASS_S  3
-/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN31_INT_TYPE    0x00000007U
-#define GPIO_PIN31_INT_TYPE_M  (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S)
-#define GPIO_PIN31_INT_TYPE_V  0x00000007U
-#define GPIO_PIN31_INT_TYPE_S  7
-/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN31_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN31_WAKEUP_ENABLE_M  (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S)
-#define GPIO_PIN31_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN31_WAKEUP_ENABLE_S  10
-/** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN31_CONFIG    0x00000003U
-#define GPIO_PIN31_CONFIG_M  (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S)
-#define GPIO_PIN31_CONFIG_V  0x00000003U
-#define GPIO_PIN31_CONFIG_S  11
-/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN31_INT_ENA    0x0000001FU
-#define GPIO_PIN31_INT_ENA_M  (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S)
-#define GPIO_PIN31_INT_ENA_V  0x0000001FU
-#define GPIO_PIN31_INT_ENA_S  13
-
-/** GPIO_PIN32_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4)
-/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN32_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN32_SYNC2_BYPASS_M  (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S)
-#define GPIO_PIN32_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN32_SYNC2_BYPASS_S  0
-/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN32_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN32_PAD_DRIVER_M  (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S)
-#define GPIO_PIN32_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN32_PAD_DRIVER_S  2
-/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN32_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN32_SYNC1_BYPASS_M  (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S)
-#define GPIO_PIN32_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN32_SYNC1_BYPASS_S  3
-/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN32_INT_TYPE    0x00000007U
-#define GPIO_PIN32_INT_TYPE_M  (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S)
-#define GPIO_PIN32_INT_TYPE_V  0x00000007U
-#define GPIO_PIN32_INT_TYPE_S  7
-/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN32_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN32_WAKEUP_ENABLE_M  (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S)
-#define GPIO_PIN32_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN32_WAKEUP_ENABLE_S  10
-/** GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN32_CONFIG    0x00000003U
-#define GPIO_PIN32_CONFIG_M  (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S)
-#define GPIO_PIN32_CONFIG_V  0x00000003U
-#define GPIO_PIN32_CONFIG_S  11
-/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN32_INT_ENA    0x0000001FU
-#define GPIO_PIN32_INT_ENA_M  (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S)
-#define GPIO_PIN32_INT_ENA_V  0x0000001FU
-#define GPIO_PIN32_INT_ENA_S  13
-
-/** GPIO_PIN33_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8)
-/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN33_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN33_SYNC2_BYPASS_M  (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S)
-#define GPIO_PIN33_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN33_SYNC2_BYPASS_S  0
-/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN33_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN33_PAD_DRIVER_M  (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S)
-#define GPIO_PIN33_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN33_PAD_DRIVER_S  2
-/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN33_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN33_SYNC1_BYPASS_M  (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S)
-#define GPIO_PIN33_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN33_SYNC1_BYPASS_S  3
-/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN33_INT_TYPE    0x00000007U
-#define GPIO_PIN33_INT_TYPE_M  (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S)
-#define GPIO_PIN33_INT_TYPE_V  0x00000007U
-#define GPIO_PIN33_INT_TYPE_S  7
-/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN33_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN33_WAKEUP_ENABLE_M  (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S)
-#define GPIO_PIN33_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN33_WAKEUP_ENABLE_S  10
-/** GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN33_CONFIG    0x00000003U
-#define GPIO_PIN33_CONFIG_M  (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S)
-#define GPIO_PIN33_CONFIG_V  0x00000003U
-#define GPIO_PIN33_CONFIG_S  11
-/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN33_INT_ENA    0x0000001FU
-#define GPIO_PIN33_INT_ENA_M  (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S)
-#define GPIO_PIN33_INT_ENA_V  0x0000001FU
-#define GPIO_PIN33_INT_ENA_S  13
-
-/** GPIO_PIN34_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc)
-/** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN34_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN34_SYNC2_BYPASS_M  (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S)
-#define GPIO_PIN34_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN34_SYNC2_BYPASS_S  0
-/** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN34_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN34_PAD_DRIVER_M  (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S)
-#define GPIO_PIN34_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN34_PAD_DRIVER_S  2
-/** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN34_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN34_SYNC1_BYPASS_M  (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S)
-#define GPIO_PIN34_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN34_SYNC1_BYPASS_S  3
-/** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN34_INT_TYPE    0x00000007U
-#define GPIO_PIN34_INT_TYPE_M  (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S)
-#define GPIO_PIN34_INT_TYPE_V  0x00000007U
-#define GPIO_PIN34_INT_TYPE_S  7
-/** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN34_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN34_WAKEUP_ENABLE_M  (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S)
-#define GPIO_PIN34_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN34_WAKEUP_ENABLE_S  10
-/** GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN34_CONFIG    0x00000003U
-#define GPIO_PIN34_CONFIG_M  (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S)
-#define GPIO_PIN34_CONFIG_V  0x00000003U
-#define GPIO_PIN34_CONFIG_S  11
-/** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN34_INT_ENA    0x0000001FU
-#define GPIO_PIN34_INT_ENA_M  (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S)
-#define GPIO_PIN34_INT_ENA_V  0x0000001FU
-#define GPIO_PIN34_INT_ENA_S  13
-
-/** GPIO_PIN35_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100)
-/** GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN35_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN35_SYNC2_BYPASS_M  (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S)
-#define GPIO_PIN35_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN35_SYNC2_BYPASS_S  0
-/** GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN35_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN35_PAD_DRIVER_M  (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S)
-#define GPIO_PIN35_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN35_PAD_DRIVER_S  2
-/** GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN35_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN35_SYNC1_BYPASS_M  (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S)
-#define GPIO_PIN35_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN35_SYNC1_BYPASS_S  3
-/** GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN35_INT_TYPE    0x00000007U
-#define GPIO_PIN35_INT_TYPE_M  (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S)
-#define GPIO_PIN35_INT_TYPE_V  0x00000007U
-#define GPIO_PIN35_INT_TYPE_S  7
-/** GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN35_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN35_WAKEUP_ENABLE_M  (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S)
-#define GPIO_PIN35_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN35_WAKEUP_ENABLE_S  10
-/** GPIO_PIN35_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN35_CONFIG    0x00000003U
-#define GPIO_PIN35_CONFIG_M  (GPIO_PIN35_CONFIG_V << GPIO_PIN35_CONFIG_S)
-#define GPIO_PIN35_CONFIG_V  0x00000003U
-#define GPIO_PIN35_CONFIG_S  11
-/** GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN35_INT_ENA    0x0000001FU
-#define GPIO_PIN35_INT_ENA_M  (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S)
-#define GPIO_PIN35_INT_ENA_V  0x0000001FU
-#define GPIO_PIN35_INT_ENA_S  13
-
-/** GPIO_PIN36_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104)
-/** GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN36_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN36_SYNC2_BYPASS_M  (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S)
-#define GPIO_PIN36_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN36_SYNC2_BYPASS_S  0
-/** GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN36_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN36_PAD_DRIVER_M  (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S)
-#define GPIO_PIN36_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN36_PAD_DRIVER_S  2
-/** GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN36_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN36_SYNC1_BYPASS_M  (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S)
-#define GPIO_PIN36_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN36_SYNC1_BYPASS_S  3
-/** GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN36_INT_TYPE    0x00000007U
-#define GPIO_PIN36_INT_TYPE_M  (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S)
-#define GPIO_PIN36_INT_TYPE_V  0x00000007U
-#define GPIO_PIN36_INT_TYPE_S  7
-/** GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN36_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN36_WAKEUP_ENABLE_M  (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S)
-#define GPIO_PIN36_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN36_WAKEUP_ENABLE_S  10
-/** GPIO_PIN36_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN36_CONFIG    0x00000003U
-#define GPIO_PIN36_CONFIG_M  (GPIO_PIN36_CONFIG_V << GPIO_PIN36_CONFIG_S)
-#define GPIO_PIN36_CONFIG_V  0x00000003U
-#define GPIO_PIN36_CONFIG_S  11
-/** GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN36_INT_ENA    0x0000001FU
-#define GPIO_PIN36_INT_ENA_M  (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S)
-#define GPIO_PIN36_INT_ENA_V  0x0000001FU
-#define GPIO_PIN36_INT_ENA_S  13
-
-/** GPIO_PIN37_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108)
-/** GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN37_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN37_SYNC2_BYPASS_M  (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S)
-#define GPIO_PIN37_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN37_SYNC2_BYPASS_S  0
-/** GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN37_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN37_PAD_DRIVER_M  (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S)
-#define GPIO_PIN37_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN37_PAD_DRIVER_S  2
-/** GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN37_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN37_SYNC1_BYPASS_M  (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S)
-#define GPIO_PIN37_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN37_SYNC1_BYPASS_S  3
-/** GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN37_INT_TYPE    0x00000007U
-#define GPIO_PIN37_INT_TYPE_M  (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S)
-#define GPIO_PIN37_INT_TYPE_V  0x00000007U
-#define GPIO_PIN37_INT_TYPE_S  7
-/** GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN37_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN37_WAKEUP_ENABLE_M  (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S)
-#define GPIO_PIN37_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN37_WAKEUP_ENABLE_S  10
-/** GPIO_PIN37_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN37_CONFIG    0x00000003U
-#define GPIO_PIN37_CONFIG_M  (GPIO_PIN37_CONFIG_V << GPIO_PIN37_CONFIG_S)
-#define GPIO_PIN37_CONFIG_V  0x00000003U
-#define GPIO_PIN37_CONFIG_S  11
-/** GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN37_INT_ENA    0x0000001FU
-#define GPIO_PIN37_INT_ENA_M  (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S)
-#define GPIO_PIN37_INT_ENA_V  0x0000001FU
-#define GPIO_PIN37_INT_ENA_S  13
-
-/** GPIO_PIN38_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10c)
-/** GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN38_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN38_SYNC2_BYPASS_M  (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S)
-#define GPIO_PIN38_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN38_SYNC2_BYPASS_S  0
-/** GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN38_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN38_PAD_DRIVER_M  (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S)
-#define GPIO_PIN38_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN38_PAD_DRIVER_S  2
-/** GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN38_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN38_SYNC1_BYPASS_M  (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S)
-#define GPIO_PIN38_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN38_SYNC1_BYPASS_S  3
-/** GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN38_INT_TYPE    0x00000007U
-#define GPIO_PIN38_INT_TYPE_M  (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S)
-#define GPIO_PIN38_INT_TYPE_V  0x00000007U
-#define GPIO_PIN38_INT_TYPE_S  7
-/** GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN38_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN38_WAKEUP_ENABLE_M  (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S)
-#define GPIO_PIN38_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN38_WAKEUP_ENABLE_S  10
-/** GPIO_PIN38_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN38_CONFIG    0x00000003U
-#define GPIO_PIN38_CONFIG_M  (GPIO_PIN38_CONFIG_V << GPIO_PIN38_CONFIG_S)
-#define GPIO_PIN38_CONFIG_V  0x00000003U
-#define GPIO_PIN38_CONFIG_S  11
-/** GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN38_INT_ENA    0x0000001FU
-#define GPIO_PIN38_INT_ENA_M  (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S)
-#define GPIO_PIN38_INT_ENA_V  0x0000001FU
-#define GPIO_PIN38_INT_ENA_S  13
-
-/** GPIO_PIN39_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110)
-/** GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN39_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN39_SYNC2_BYPASS_M  (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S)
-#define GPIO_PIN39_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN39_SYNC2_BYPASS_S  0
-/** GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN39_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN39_PAD_DRIVER_M  (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S)
-#define GPIO_PIN39_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN39_PAD_DRIVER_S  2
-/** GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN39_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN39_SYNC1_BYPASS_M  (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S)
-#define GPIO_PIN39_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN39_SYNC1_BYPASS_S  3
-/** GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN39_INT_TYPE    0x00000007U
-#define GPIO_PIN39_INT_TYPE_M  (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S)
-#define GPIO_PIN39_INT_TYPE_V  0x00000007U
-#define GPIO_PIN39_INT_TYPE_S  7
-/** GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN39_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN39_WAKEUP_ENABLE_M  (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S)
-#define GPIO_PIN39_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN39_WAKEUP_ENABLE_S  10
-/** GPIO_PIN39_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN39_CONFIG    0x00000003U
-#define GPIO_PIN39_CONFIG_M  (GPIO_PIN39_CONFIG_V << GPIO_PIN39_CONFIG_S)
-#define GPIO_PIN39_CONFIG_V  0x00000003U
-#define GPIO_PIN39_CONFIG_S  11
-/** GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN39_INT_ENA    0x0000001FU
-#define GPIO_PIN39_INT_ENA_M  (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S)
-#define GPIO_PIN39_INT_ENA_V  0x0000001FU
-#define GPIO_PIN39_INT_ENA_S  13
-
-/** GPIO_PIN40_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114)
-/** GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN40_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN40_SYNC2_BYPASS_M  (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S)
-#define GPIO_PIN40_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN40_SYNC2_BYPASS_S  0
-/** GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN40_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN40_PAD_DRIVER_M  (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S)
-#define GPIO_PIN40_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN40_PAD_DRIVER_S  2
-/** GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN40_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN40_SYNC1_BYPASS_M  (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S)
-#define GPIO_PIN40_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN40_SYNC1_BYPASS_S  3
-/** GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN40_INT_TYPE    0x00000007U
-#define GPIO_PIN40_INT_TYPE_M  (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S)
-#define GPIO_PIN40_INT_TYPE_V  0x00000007U
-#define GPIO_PIN40_INT_TYPE_S  7
-/** GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN40_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN40_WAKEUP_ENABLE_M  (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S)
-#define GPIO_PIN40_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN40_WAKEUP_ENABLE_S  10
-/** GPIO_PIN40_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN40_CONFIG    0x00000003U
-#define GPIO_PIN40_CONFIG_M  (GPIO_PIN40_CONFIG_V << GPIO_PIN40_CONFIG_S)
-#define GPIO_PIN40_CONFIG_V  0x00000003U
-#define GPIO_PIN40_CONFIG_S  11
-/** GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN40_INT_ENA    0x0000001FU
-#define GPIO_PIN40_INT_ENA_M  (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S)
-#define GPIO_PIN40_INT_ENA_V  0x0000001FU
-#define GPIO_PIN40_INT_ENA_S  13
-
-/** GPIO_PIN41_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118)
-/** GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN41_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN41_SYNC2_BYPASS_M  (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S)
-#define GPIO_PIN41_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN41_SYNC2_BYPASS_S  0
-/** GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN41_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN41_PAD_DRIVER_M  (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S)
-#define GPIO_PIN41_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN41_PAD_DRIVER_S  2
-/** GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN41_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN41_SYNC1_BYPASS_M  (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S)
-#define GPIO_PIN41_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN41_SYNC1_BYPASS_S  3
-/** GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN41_INT_TYPE    0x00000007U
-#define GPIO_PIN41_INT_TYPE_M  (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S)
-#define GPIO_PIN41_INT_TYPE_V  0x00000007U
-#define GPIO_PIN41_INT_TYPE_S  7
-/** GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN41_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN41_WAKEUP_ENABLE_M  (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S)
-#define GPIO_PIN41_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN41_WAKEUP_ENABLE_S  10
-/** GPIO_PIN41_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN41_CONFIG    0x00000003U
-#define GPIO_PIN41_CONFIG_M  (GPIO_PIN41_CONFIG_V << GPIO_PIN41_CONFIG_S)
-#define GPIO_PIN41_CONFIG_V  0x00000003U
-#define GPIO_PIN41_CONFIG_S  11
-/** GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN41_INT_ENA    0x0000001FU
-#define GPIO_PIN41_INT_ENA_M  (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S)
-#define GPIO_PIN41_INT_ENA_V  0x0000001FU
-#define GPIO_PIN41_INT_ENA_S  13
-
-/** GPIO_PIN42_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11c)
-/** GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN42_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN42_SYNC2_BYPASS_M  (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S)
-#define GPIO_PIN42_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN42_SYNC2_BYPASS_S  0
-/** GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN42_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN42_PAD_DRIVER_M  (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S)
-#define GPIO_PIN42_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN42_PAD_DRIVER_S  2
-/** GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN42_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN42_SYNC1_BYPASS_M  (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S)
-#define GPIO_PIN42_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN42_SYNC1_BYPASS_S  3
-/** GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN42_INT_TYPE    0x00000007U
-#define GPIO_PIN42_INT_TYPE_M  (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S)
-#define GPIO_PIN42_INT_TYPE_V  0x00000007U
-#define GPIO_PIN42_INT_TYPE_S  7
-/** GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN42_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN42_WAKEUP_ENABLE_M  (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S)
-#define GPIO_PIN42_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN42_WAKEUP_ENABLE_S  10
-/** GPIO_PIN42_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN42_CONFIG    0x00000003U
-#define GPIO_PIN42_CONFIG_M  (GPIO_PIN42_CONFIG_V << GPIO_PIN42_CONFIG_S)
-#define GPIO_PIN42_CONFIG_V  0x00000003U
-#define GPIO_PIN42_CONFIG_S  11
-/** GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN42_INT_ENA    0x0000001FU
-#define GPIO_PIN42_INT_ENA_M  (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S)
-#define GPIO_PIN42_INT_ENA_V  0x0000001FU
-#define GPIO_PIN42_INT_ENA_S  13
-
-/** GPIO_PIN43_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120)
-/** GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN43_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN43_SYNC2_BYPASS_M  (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S)
-#define GPIO_PIN43_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN43_SYNC2_BYPASS_S  0
-/** GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN43_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN43_PAD_DRIVER_M  (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S)
-#define GPIO_PIN43_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN43_PAD_DRIVER_S  2
-/** GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN43_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN43_SYNC1_BYPASS_M  (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S)
-#define GPIO_PIN43_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN43_SYNC1_BYPASS_S  3
-/** GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN43_INT_TYPE    0x00000007U
-#define GPIO_PIN43_INT_TYPE_M  (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S)
-#define GPIO_PIN43_INT_TYPE_V  0x00000007U
-#define GPIO_PIN43_INT_TYPE_S  7
-/** GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN43_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN43_WAKEUP_ENABLE_M  (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S)
-#define GPIO_PIN43_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN43_WAKEUP_ENABLE_S  10
-/** GPIO_PIN43_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN43_CONFIG    0x00000003U
-#define GPIO_PIN43_CONFIG_M  (GPIO_PIN43_CONFIG_V << GPIO_PIN43_CONFIG_S)
-#define GPIO_PIN43_CONFIG_V  0x00000003U
-#define GPIO_PIN43_CONFIG_S  11
-/** GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN43_INT_ENA    0x0000001FU
-#define GPIO_PIN43_INT_ENA_M  (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S)
-#define GPIO_PIN43_INT_ENA_V  0x0000001FU
-#define GPIO_PIN43_INT_ENA_S  13
-
-/** GPIO_PIN44_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124)
-/** GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN44_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN44_SYNC2_BYPASS_M  (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S)
-#define GPIO_PIN44_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN44_SYNC2_BYPASS_S  0
-/** GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN44_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN44_PAD_DRIVER_M  (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S)
-#define GPIO_PIN44_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN44_PAD_DRIVER_S  2
-/** GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN44_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN44_SYNC1_BYPASS_M  (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S)
-#define GPIO_PIN44_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN44_SYNC1_BYPASS_S  3
-/** GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN44_INT_TYPE    0x00000007U
-#define GPIO_PIN44_INT_TYPE_M  (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S)
-#define GPIO_PIN44_INT_TYPE_V  0x00000007U
-#define GPIO_PIN44_INT_TYPE_S  7
-/** GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN44_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN44_WAKEUP_ENABLE_M  (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S)
-#define GPIO_PIN44_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN44_WAKEUP_ENABLE_S  10
-/** GPIO_PIN44_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN44_CONFIG    0x00000003U
-#define GPIO_PIN44_CONFIG_M  (GPIO_PIN44_CONFIG_V << GPIO_PIN44_CONFIG_S)
-#define GPIO_PIN44_CONFIG_V  0x00000003U
-#define GPIO_PIN44_CONFIG_S  11
-/** GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN44_INT_ENA    0x0000001FU
-#define GPIO_PIN44_INT_ENA_M  (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S)
-#define GPIO_PIN44_INT_ENA_V  0x0000001FU
-#define GPIO_PIN44_INT_ENA_S  13
-
-/** GPIO_PIN45_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN45_REG (DR_REG_GPIO_BASE + 0x128)
-/** GPIO_PIN45_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN45_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN45_SYNC2_BYPASS_M  (GPIO_PIN45_SYNC2_BYPASS_V << GPIO_PIN45_SYNC2_BYPASS_S)
-#define GPIO_PIN45_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN45_SYNC2_BYPASS_S  0
-/** GPIO_PIN45_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN45_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN45_PAD_DRIVER_M  (GPIO_PIN45_PAD_DRIVER_V << GPIO_PIN45_PAD_DRIVER_S)
-#define GPIO_PIN45_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN45_PAD_DRIVER_S  2
-/** GPIO_PIN45_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN45_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN45_SYNC1_BYPASS_M  (GPIO_PIN45_SYNC1_BYPASS_V << GPIO_PIN45_SYNC1_BYPASS_S)
-#define GPIO_PIN45_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN45_SYNC1_BYPASS_S  3
-/** GPIO_PIN45_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN45_INT_TYPE    0x00000007U
-#define GPIO_PIN45_INT_TYPE_M  (GPIO_PIN45_INT_TYPE_V << GPIO_PIN45_INT_TYPE_S)
-#define GPIO_PIN45_INT_TYPE_V  0x00000007U
-#define GPIO_PIN45_INT_TYPE_S  7
-/** GPIO_PIN45_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN45_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN45_WAKEUP_ENABLE_M  (GPIO_PIN45_WAKEUP_ENABLE_V << GPIO_PIN45_WAKEUP_ENABLE_S)
-#define GPIO_PIN45_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN45_WAKEUP_ENABLE_S  10
-/** GPIO_PIN45_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN45_CONFIG    0x00000003U
-#define GPIO_PIN45_CONFIG_M  (GPIO_PIN45_CONFIG_V << GPIO_PIN45_CONFIG_S)
-#define GPIO_PIN45_CONFIG_V  0x00000003U
-#define GPIO_PIN45_CONFIG_S  11
-/** GPIO_PIN45_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN45_INT_ENA    0x0000001FU
-#define GPIO_PIN45_INT_ENA_M  (GPIO_PIN45_INT_ENA_V << GPIO_PIN45_INT_ENA_S)
-#define GPIO_PIN45_INT_ENA_V  0x0000001FU
-#define GPIO_PIN45_INT_ENA_S  13
-
-/** GPIO_PIN46_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN46_REG (DR_REG_GPIO_BASE + 0x12c)
-/** GPIO_PIN46_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN46_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN46_SYNC2_BYPASS_M  (GPIO_PIN46_SYNC2_BYPASS_V << GPIO_PIN46_SYNC2_BYPASS_S)
-#define GPIO_PIN46_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN46_SYNC2_BYPASS_S  0
-/** GPIO_PIN46_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN46_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN46_PAD_DRIVER_M  (GPIO_PIN46_PAD_DRIVER_V << GPIO_PIN46_PAD_DRIVER_S)
-#define GPIO_PIN46_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN46_PAD_DRIVER_S  2
-/** GPIO_PIN46_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN46_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN46_SYNC1_BYPASS_M  (GPIO_PIN46_SYNC1_BYPASS_V << GPIO_PIN46_SYNC1_BYPASS_S)
-#define GPIO_PIN46_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN46_SYNC1_BYPASS_S  3
-/** GPIO_PIN46_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN46_INT_TYPE    0x00000007U
-#define GPIO_PIN46_INT_TYPE_M  (GPIO_PIN46_INT_TYPE_V << GPIO_PIN46_INT_TYPE_S)
-#define GPIO_PIN46_INT_TYPE_V  0x00000007U
-#define GPIO_PIN46_INT_TYPE_S  7
-/** GPIO_PIN46_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN46_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN46_WAKEUP_ENABLE_M  (GPIO_PIN46_WAKEUP_ENABLE_V << GPIO_PIN46_WAKEUP_ENABLE_S)
-#define GPIO_PIN46_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN46_WAKEUP_ENABLE_S  10
-/** GPIO_PIN46_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN46_CONFIG    0x00000003U
-#define GPIO_PIN46_CONFIG_M  (GPIO_PIN46_CONFIG_V << GPIO_PIN46_CONFIG_S)
-#define GPIO_PIN46_CONFIG_V  0x00000003U
-#define GPIO_PIN46_CONFIG_S  11
-/** GPIO_PIN46_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN46_INT_ENA    0x0000001FU
-#define GPIO_PIN46_INT_ENA_M  (GPIO_PIN46_INT_ENA_V << GPIO_PIN46_INT_ENA_S)
-#define GPIO_PIN46_INT_ENA_V  0x0000001FU
-#define GPIO_PIN46_INT_ENA_S  13
-
-/** GPIO_PIN47_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN47_REG (DR_REG_GPIO_BASE + 0x130)
-/** GPIO_PIN47_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN47_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN47_SYNC2_BYPASS_M  (GPIO_PIN47_SYNC2_BYPASS_V << GPIO_PIN47_SYNC2_BYPASS_S)
-#define GPIO_PIN47_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN47_SYNC2_BYPASS_S  0
-/** GPIO_PIN47_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN47_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN47_PAD_DRIVER_M  (GPIO_PIN47_PAD_DRIVER_V << GPIO_PIN47_PAD_DRIVER_S)
-#define GPIO_PIN47_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN47_PAD_DRIVER_S  2
-/** GPIO_PIN47_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN47_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN47_SYNC1_BYPASS_M  (GPIO_PIN47_SYNC1_BYPASS_V << GPIO_PIN47_SYNC1_BYPASS_S)
-#define GPIO_PIN47_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN47_SYNC1_BYPASS_S  3
-/** GPIO_PIN47_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN47_INT_TYPE    0x00000007U
-#define GPIO_PIN47_INT_TYPE_M  (GPIO_PIN47_INT_TYPE_V << GPIO_PIN47_INT_TYPE_S)
-#define GPIO_PIN47_INT_TYPE_V  0x00000007U
-#define GPIO_PIN47_INT_TYPE_S  7
-/** GPIO_PIN47_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN47_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN47_WAKEUP_ENABLE_M  (GPIO_PIN47_WAKEUP_ENABLE_V << GPIO_PIN47_WAKEUP_ENABLE_S)
-#define GPIO_PIN47_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN47_WAKEUP_ENABLE_S  10
-/** GPIO_PIN47_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN47_CONFIG    0x00000003U
-#define GPIO_PIN47_CONFIG_M  (GPIO_PIN47_CONFIG_V << GPIO_PIN47_CONFIG_S)
-#define GPIO_PIN47_CONFIG_V  0x00000003U
-#define GPIO_PIN47_CONFIG_S  11
-/** GPIO_PIN47_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN47_INT_ENA    0x0000001FU
-#define GPIO_PIN47_INT_ENA_M  (GPIO_PIN47_INT_ENA_V << GPIO_PIN47_INT_ENA_S)
-#define GPIO_PIN47_INT_ENA_V  0x0000001FU
-#define GPIO_PIN47_INT_ENA_S  13
-
-/** GPIO_PIN48_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN48_REG (DR_REG_GPIO_BASE + 0x134)
-/** GPIO_PIN48_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN48_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN48_SYNC2_BYPASS_M  (GPIO_PIN48_SYNC2_BYPASS_V << GPIO_PIN48_SYNC2_BYPASS_S)
-#define GPIO_PIN48_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN48_SYNC2_BYPASS_S  0
-/** GPIO_PIN48_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN48_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN48_PAD_DRIVER_M  (GPIO_PIN48_PAD_DRIVER_V << GPIO_PIN48_PAD_DRIVER_S)
-#define GPIO_PIN48_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN48_PAD_DRIVER_S  2
-/** GPIO_PIN48_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN48_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN48_SYNC1_BYPASS_M  (GPIO_PIN48_SYNC1_BYPASS_V << GPIO_PIN48_SYNC1_BYPASS_S)
-#define GPIO_PIN48_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN48_SYNC1_BYPASS_S  3
-/** GPIO_PIN48_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN48_INT_TYPE    0x00000007U
-#define GPIO_PIN48_INT_TYPE_M  (GPIO_PIN48_INT_TYPE_V << GPIO_PIN48_INT_TYPE_S)
-#define GPIO_PIN48_INT_TYPE_V  0x00000007U
-#define GPIO_PIN48_INT_TYPE_S  7
-/** GPIO_PIN48_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN48_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN48_WAKEUP_ENABLE_M  (GPIO_PIN48_WAKEUP_ENABLE_V << GPIO_PIN48_WAKEUP_ENABLE_S)
-#define GPIO_PIN48_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN48_WAKEUP_ENABLE_S  10
-/** GPIO_PIN48_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN48_CONFIG    0x00000003U
-#define GPIO_PIN48_CONFIG_M  (GPIO_PIN48_CONFIG_V << GPIO_PIN48_CONFIG_S)
-#define GPIO_PIN48_CONFIG_V  0x00000003U
-#define GPIO_PIN48_CONFIG_S  11
-/** GPIO_PIN48_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN48_INT_ENA    0x0000001FU
-#define GPIO_PIN48_INT_ENA_M  (GPIO_PIN48_INT_ENA_V << GPIO_PIN48_INT_ENA_S)
-#define GPIO_PIN48_INT_ENA_V  0x0000001FU
-#define GPIO_PIN48_INT_ENA_S  13
-
-/** GPIO_PIN49_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN49_REG (DR_REG_GPIO_BASE + 0x138)
-/** GPIO_PIN49_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN49_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN49_SYNC2_BYPASS_M  (GPIO_PIN49_SYNC2_BYPASS_V << GPIO_PIN49_SYNC2_BYPASS_S)
-#define GPIO_PIN49_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN49_SYNC2_BYPASS_S  0
-/** GPIO_PIN49_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN49_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN49_PAD_DRIVER_M  (GPIO_PIN49_PAD_DRIVER_V << GPIO_PIN49_PAD_DRIVER_S)
-#define GPIO_PIN49_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN49_PAD_DRIVER_S  2
-/** GPIO_PIN49_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN49_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN49_SYNC1_BYPASS_M  (GPIO_PIN49_SYNC1_BYPASS_V << GPIO_PIN49_SYNC1_BYPASS_S)
-#define GPIO_PIN49_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN49_SYNC1_BYPASS_S  3
-/** GPIO_PIN49_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN49_INT_TYPE    0x00000007U
-#define GPIO_PIN49_INT_TYPE_M  (GPIO_PIN49_INT_TYPE_V << GPIO_PIN49_INT_TYPE_S)
-#define GPIO_PIN49_INT_TYPE_V  0x00000007U
-#define GPIO_PIN49_INT_TYPE_S  7
-/** GPIO_PIN49_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN49_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN49_WAKEUP_ENABLE_M  (GPIO_PIN49_WAKEUP_ENABLE_V << GPIO_PIN49_WAKEUP_ENABLE_S)
-#define GPIO_PIN49_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN49_WAKEUP_ENABLE_S  10
-/** GPIO_PIN49_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN49_CONFIG    0x00000003U
-#define GPIO_PIN49_CONFIG_M  (GPIO_PIN49_CONFIG_V << GPIO_PIN49_CONFIG_S)
-#define GPIO_PIN49_CONFIG_V  0x00000003U
-#define GPIO_PIN49_CONFIG_S  11
-/** GPIO_PIN49_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN49_INT_ENA    0x0000001FU
-#define GPIO_PIN49_INT_ENA_M  (GPIO_PIN49_INT_ENA_V << GPIO_PIN49_INT_ENA_S)
-#define GPIO_PIN49_INT_ENA_V  0x0000001FU
-#define GPIO_PIN49_INT_ENA_S  13
-
-/** GPIO_PIN50_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN50_REG (DR_REG_GPIO_BASE + 0x13c)
-/** GPIO_PIN50_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN50_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN50_SYNC2_BYPASS_M  (GPIO_PIN50_SYNC2_BYPASS_V << GPIO_PIN50_SYNC2_BYPASS_S)
-#define GPIO_PIN50_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN50_SYNC2_BYPASS_S  0
-/** GPIO_PIN50_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN50_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN50_PAD_DRIVER_M  (GPIO_PIN50_PAD_DRIVER_V << GPIO_PIN50_PAD_DRIVER_S)
-#define GPIO_PIN50_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN50_PAD_DRIVER_S  2
-/** GPIO_PIN50_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN50_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN50_SYNC1_BYPASS_M  (GPIO_PIN50_SYNC1_BYPASS_V << GPIO_PIN50_SYNC1_BYPASS_S)
-#define GPIO_PIN50_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN50_SYNC1_BYPASS_S  3
-/** GPIO_PIN50_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN50_INT_TYPE    0x00000007U
-#define GPIO_PIN50_INT_TYPE_M  (GPIO_PIN50_INT_TYPE_V << GPIO_PIN50_INT_TYPE_S)
-#define GPIO_PIN50_INT_TYPE_V  0x00000007U
-#define GPIO_PIN50_INT_TYPE_S  7
-/** GPIO_PIN50_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN50_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN50_WAKEUP_ENABLE_M  (GPIO_PIN50_WAKEUP_ENABLE_V << GPIO_PIN50_WAKEUP_ENABLE_S)
-#define GPIO_PIN50_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN50_WAKEUP_ENABLE_S  10
-/** GPIO_PIN50_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN50_CONFIG    0x00000003U
-#define GPIO_PIN50_CONFIG_M  (GPIO_PIN50_CONFIG_V << GPIO_PIN50_CONFIG_S)
-#define GPIO_PIN50_CONFIG_V  0x00000003U
-#define GPIO_PIN50_CONFIG_S  11
-/** GPIO_PIN50_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN50_INT_ENA    0x0000001FU
-#define GPIO_PIN50_INT_ENA_M  (GPIO_PIN50_INT_ENA_V << GPIO_PIN50_INT_ENA_S)
-#define GPIO_PIN50_INT_ENA_V  0x0000001FU
-#define GPIO_PIN50_INT_ENA_S  13
-
-/** GPIO_PIN51_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN51_REG (DR_REG_GPIO_BASE + 0x140)
-/** GPIO_PIN51_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN51_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN51_SYNC2_BYPASS_M  (GPIO_PIN51_SYNC2_BYPASS_V << GPIO_PIN51_SYNC2_BYPASS_S)
-#define GPIO_PIN51_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN51_SYNC2_BYPASS_S  0
-/** GPIO_PIN51_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN51_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN51_PAD_DRIVER_M  (GPIO_PIN51_PAD_DRIVER_V << GPIO_PIN51_PAD_DRIVER_S)
-#define GPIO_PIN51_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN51_PAD_DRIVER_S  2
-/** GPIO_PIN51_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN51_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN51_SYNC1_BYPASS_M  (GPIO_PIN51_SYNC1_BYPASS_V << GPIO_PIN51_SYNC1_BYPASS_S)
-#define GPIO_PIN51_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN51_SYNC1_BYPASS_S  3
-/** GPIO_PIN51_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN51_INT_TYPE    0x00000007U
-#define GPIO_PIN51_INT_TYPE_M  (GPIO_PIN51_INT_TYPE_V << GPIO_PIN51_INT_TYPE_S)
-#define GPIO_PIN51_INT_TYPE_V  0x00000007U
-#define GPIO_PIN51_INT_TYPE_S  7
-/** GPIO_PIN51_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN51_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN51_WAKEUP_ENABLE_M  (GPIO_PIN51_WAKEUP_ENABLE_V << GPIO_PIN51_WAKEUP_ENABLE_S)
-#define GPIO_PIN51_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN51_WAKEUP_ENABLE_S  10
-/** GPIO_PIN51_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN51_CONFIG    0x00000003U
-#define GPIO_PIN51_CONFIG_M  (GPIO_PIN51_CONFIG_V << GPIO_PIN51_CONFIG_S)
-#define GPIO_PIN51_CONFIG_V  0x00000003U
-#define GPIO_PIN51_CONFIG_S  11
-/** GPIO_PIN51_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN51_INT_ENA    0x0000001FU
-#define GPIO_PIN51_INT_ENA_M  (GPIO_PIN51_INT_ENA_V << GPIO_PIN51_INT_ENA_S)
-#define GPIO_PIN51_INT_ENA_V  0x0000001FU
-#define GPIO_PIN51_INT_ENA_S  13
-
-/** GPIO_PIN52_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN52_REG (DR_REG_GPIO_BASE + 0x144)
-/** GPIO_PIN52_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN52_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN52_SYNC2_BYPASS_M  (GPIO_PIN52_SYNC2_BYPASS_V << GPIO_PIN52_SYNC2_BYPASS_S)
-#define GPIO_PIN52_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN52_SYNC2_BYPASS_S  0
-/** GPIO_PIN52_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN52_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN52_PAD_DRIVER_M  (GPIO_PIN52_PAD_DRIVER_V << GPIO_PIN52_PAD_DRIVER_S)
-#define GPIO_PIN52_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN52_PAD_DRIVER_S  2
-/** GPIO_PIN52_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN52_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN52_SYNC1_BYPASS_M  (GPIO_PIN52_SYNC1_BYPASS_V << GPIO_PIN52_SYNC1_BYPASS_S)
-#define GPIO_PIN52_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN52_SYNC1_BYPASS_S  3
-/** GPIO_PIN52_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN52_INT_TYPE    0x00000007U
-#define GPIO_PIN52_INT_TYPE_M  (GPIO_PIN52_INT_TYPE_V << GPIO_PIN52_INT_TYPE_S)
-#define GPIO_PIN52_INT_TYPE_V  0x00000007U
-#define GPIO_PIN52_INT_TYPE_S  7
-/** GPIO_PIN52_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN52_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN52_WAKEUP_ENABLE_M  (GPIO_PIN52_WAKEUP_ENABLE_V << GPIO_PIN52_WAKEUP_ENABLE_S)
-#define GPIO_PIN52_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN52_WAKEUP_ENABLE_S  10
-/** GPIO_PIN52_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN52_CONFIG    0x00000003U
-#define GPIO_PIN52_CONFIG_M  (GPIO_PIN52_CONFIG_V << GPIO_PIN52_CONFIG_S)
-#define GPIO_PIN52_CONFIG_V  0x00000003U
-#define GPIO_PIN52_CONFIG_S  11
-/** GPIO_PIN52_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN52_INT_ENA    0x0000001FU
-#define GPIO_PIN52_INT_ENA_M  (GPIO_PIN52_INT_ENA_V << GPIO_PIN52_INT_ENA_S)
-#define GPIO_PIN52_INT_ENA_V  0x0000001FU
-#define GPIO_PIN52_INT_ENA_S  13
-
-/** GPIO_PIN53_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN53_REG (DR_REG_GPIO_BASE + 0x148)
-/** GPIO_PIN53_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN53_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN53_SYNC2_BYPASS_M  (GPIO_PIN53_SYNC2_BYPASS_V << GPIO_PIN53_SYNC2_BYPASS_S)
-#define GPIO_PIN53_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN53_SYNC2_BYPASS_S  0
-/** GPIO_PIN53_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN53_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN53_PAD_DRIVER_M  (GPIO_PIN53_PAD_DRIVER_V << GPIO_PIN53_PAD_DRIVER_S)
-#define GPIO_PIN53_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN53_PAD_DRIVER_S  2
-/** GPIO_PIN53_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN53_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN53_SYNC1_BYPASS_M  (GPIO_PIN53_SYNC1_BYPASS_V << GPIO_PIN53_SYNC1_BYPASS_S)
-#define GPIO_PIN53_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN53_SYNC1_BYPASS_S  3
-/** GPIO_PIN53_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN53_INT_TYPE    0x00000007U
-#define GPIO_PIN53_INT_TYPE_M  (GPIO_PIN53_INT_TYPE_V << GPIO_PIN53_INT_TYPE_S)
-#define GPIO_PIN53_INT_TYPE_V  0x00000007U
-#define GPIO_PIN53_INT_TYPE_S  7
-/** GPIO_PIN53_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN53_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN53_WAKEUP_ENABLE_M  (GPIO_PIN53_WAKEUP_ENABLE_V << GPIO_PIN53_WAKEUP_ENABLE_S)
-#define GPIO_PIN53_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN53_WAKEUP_ENABLE_S  10
-/** GPIO_PIN53_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN53_CONFIG    0x00000003U
-#define GPIO_PIN53_CONFIG_M  (GPIO_PIN53_CONFIG_V << GPIO_PIN53_CONFIG_S)
-#define GPIO_PIN53_CONFIG_V  0x00000003U
-#define GPIO_PIN53_CONFIG_S  11
-/** GPIO_PIN53_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN53_INT_ENA    0x0000001FU
-#define GPIO_PIN53_INT_ENA_M  (GPIO_PIN53_INT_ENA_V << GPIO_PIN53_INT_ENA_S)
-#define GPIO_PIN53_INT_ENA_V  0x0000001FU
-#define GPIO_PIN53_INT_ENA_S  13
-
-/** GPIO_PIN54_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN54_REG (DR_REG_GPIO_BASE + 0x14c)
-/** GPIO_PIN54_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN54_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN54_SYNC2_BYPASS_M  (GPIO_PIN54_SYNC2_BYPASS_V << GPIO_PIN54_SYNC2_BYPASS_S)
-#define GPIO_PIN54_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN54_SYNC2_BYPASS_S  0
-/** GPIO_PIN54_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN54_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN54_PAD_DRIVER_M  (GPIO_PIN54_PAD_DRIVER_V << GPIO_PIN54_PAD_DRIVER_S)
-#define GPIO_PIN54_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN54_PAD_DRIVER_S  2
-/** GPIO_PIN54_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN54_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN54_SYNC1_BYPASS_M  (GPIO_PIN54_SYNC1_BYPASS_V << GPIO_PIN54_SYNC1_BYPASS_S)
-#define GPIO_PIN54_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN54_SYNC1_BYPASS_S  3
-/** GPIO_PIN54_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN54_INT_TYPE    0x00000007U
-#define GPIO_PIN54_INT_TYPE_M  (GPIO_PIN54_INT_TYPE_V << GPIO_PIN54_INT_TYPE_S)
-#define GPIO_PIN54_INT_TYPE_V  0x00000007U
-#define GPIO_PIN54_INT_TYPE_S  7
-/** GPIO_PIN54_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN54_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN54_WAKEUP_ENABLE_M  (GPIO_PIN54_WAKEUP_ENABLE_V << GPIO_PIN54_WAKEUP_ENABLE_S)
-#define GPIO_PIN54_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN54_WAKEUP_ENABLE_S  10
-/** GPIO_PIN54_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN54_CONFIG    0x00000003U
-#define GPIO_PIN54_CONFIG_M  (GPIO_PIN54_CONFIG_V << GPIO_PIN54_CONFIG_S)
-#define GPIO_PIN54_CONFIG_V  0x00000003U
-#define GPIO_PIN54_CONFIG_S  11
-/** GPIO_PIN54_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN54_INT_ENA    0x0000001FU
-#define GPIO_PIN54_INT_ENA_M  (GPIO_PIN54_INT_ENA_V << GPIO_PIN54_INT_ENA_S)
-#define GPIO_PIN54_INT_ENA_V  0x0000001FU
-#define GPIO_PIN54_INT_ENA_S  13
-
-/** GPIO_PIN55_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN55_REG (DR_REG_GPIO_BASE + 0x150)
-/** GPIO_PIN55_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN55_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN55_SYNC2_BYPASS_M  (GPIO_PIN55_SYNC2_BYPASS_V << GPIO_PIN55_SYNC2_BYPASS_S)
-#define GPIO_PIN55_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN55_SYNC2_BYPASS_S  0
-/** GPIO_PIN55_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN55_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN55_PAD_DRIVER_M  (GPIO_PIN55_PAD_DRIVER_V << GPIO_PIN55_PAD_DRIVER_S)
-#define GPIO_PIN55_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN55_PAD_DRIVER_S  2
-/** GPIO_PIN55_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN55_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN55_SYNC1_BYPASS_M  (GPIO_PIN55_SYNC1_BYPASS_V << GPIO_PIN55_SYNC1_BYPASS_S)
-#define GPIO_PIN55_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN55_SYNC1_BYPASS_S  3
-/** GPIO_PIN55_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN55_INT_TYPE    0x00000007U
-#define GPIO_PIN55_INT_TYPE_M  (GPIO_PIN55_INT_TYPE_V << GPIO_PIN55_INT_TYPE_S)
-#define GPIO_PIN55_INT_TYPE_V  0x00000007U
-#define GPIO_PIN55_INT_TYPE_S  7
-/** GPIO_PIN55_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN55_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN55_WAKEUP_ENABLE_M  (GPIO_PIN55_WAKEUP_ENABLE_V << GPIO_PIN55_WAKEUP_ENABLE_S)
-#define GPIO_PIN55_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN55_WAKEUP_ENABLE_S  10
-/** GPIO_PIN55_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN55_CONFIG    0x00000003U
-#define GPIO_PIN55_CONFIG_M  (GPIO_PIN55_CONFIG_V << GPIO_PIN55_CONFIG_S)
-#define GPIO_PIN55_CONFIG_V  0x00000003U
-#define GPIO_PIN55_CONFIG_S  11
-/** GPIO_PIN55_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN55_INT_ENA    0x0000001FU
-#define GPIO_PIN55_INT_ENA_M  (GPIO_PIN55_INT_ENA_V << GPIO_PIN55_INT_ENA_S)
-#define GPIO_PIN55_INT_ENA_V  0x0000001FU
-#define GPIO_PIN55_INT_ENA_S  13
-
-/** GPIO_PIN56_REG register
- *  GPIO pin configuration register
- */
-#define GPIO_PIN56_REG (DR_REG_GPIO_BASE + 0x154)
-/** GPIO_PIN56_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
- *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN56_SYNC2_BYPASS    0x00000003U
-#define GPIO_PIN56_SYNC2_BYPASS_M  (GPIO_PIN56_SYNC2_BYPASS_V << GPIO_PIN56_SYNC2_BYPASS_S)
-#define GPIO_PIN56_SYNC2_BYPASS_V  0x00000003U
-#define GPIO_PIN56_SYNC2_BYPASS_S  0
-/** GPIO_PIN56_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
- *  set this bit to select pad driver. 1:open-drain. 0:normal.
- */
-#define GPIO_PIN56_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN56_PAD_DRIVER_M  (GPIO_PIN56_PAD_DRIVER_V << GPIO_PIN56_PAD_DRIVER_S)
-#define GPIO_PIN56_PAD_DRIVER_V  0x00000001U
-#define GPIO_PIN56_PAD_DRIVER_S  2
-/** GPIO_PIN56_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
- *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
- *  posedge.
- */
-#define GPIO_PIN56_SYNC1_BYPASS    0x00000003U
-#define GPIO_PIN56_SYNC1_BYPASS_M  (GPIO_PIN56_SYNC1_BYPASS_V << GPIO_PIN56_SYNC1_BYPASS_S)
-#define GPIO_PIN56_SYNC1_BYPASS_V  0x00000003U
-#define GPIO_PIN56_SYNC1_BYPASS_S  3
-/** GPIO_PIN56_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
- *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
- *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
- *  at high level
- */
-#define GPIO_PIN56_INT_TYPE    0x00000007U
-#define GPIO_PIN56_INT_TYPE_M  (GPIO_PIN56_INT_TYPE_V << GPIO_PIN56_INT_TYPE_S)
-#define GPIO_PIN56_INT_TYPE_V  0x00000007U
-#define GPIO_PIN56_INT_TYPE_S  7
-/** GPIO_PIN56_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
- *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
- */
-#define GPIO_PIN56_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN56_WAKEUP_ENABLE_M  (GPIO_PIN56_WAKEUP_ENABLE_V << GPIO_PIN56_WAKEUP_ENABLE_S)
-#define GPIO_PIN56_WAKEUP_ENABLE_V  0x00000001U
-#define GPIO_PIN56_WAKEUP_ENABLE_S  10
-/** GPIO_PIN56_CONFIG : R/W; bitpos: [12:11]; default: 0;
- *  reserved
- */
-#define GPIO_PIN56_CONFIG    0x00000003U
-#define GPIO_PIN56_CONFIG_M  (GPIO_PIN56_CONFIG_V << GPIO_PIN56_CONFIG_S)
-#define GPIO_PIN56_CONFIG_V  0x00000003U
-#define GPIO_PIN56_CONFIG_S  11
-/** GPIO_PIN56_INT_ENA : R/W; bitpos: [17:13]; default: 0;
- *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
- *  interrupt.
- */
-#define GPIO_PIN56_INT_ENA    0x0000001FU
-#define GPIO_PIN56_INT_ENA_M  (GPIO_PIN56_INT_ENA_V << GPIO_PIN56_INT_ENA_S)
-#define GPIO_PIN56_INT_ENA_V  0x0000001FU
-#define GPIO_PIN56_INT_ENA_S  13
-
-/** GPIO_FUNC1_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
-/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC1_IN_SEL    0x0000003FU
-#define GPIO_FUNC1_IN_SEL_M  (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S)
-#define GPIO_FUNC1_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC1_IN_SEL_S  0
-/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC1_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC1_IN_INV_SEL_M  (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S)
-#define GPIO_FUNC1_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC1_IN_INV_SEL_S  6
-/** GPIO_SIG1_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG1_IN_SEL    (BIT(7))
-#define GPIO_SIG1_IN_SEL_M  (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S)
-#define GPIO_SIG1_IN_SEL_V  0x00000001U
-#define GPIO_SIG1_IN_SEL_S  7
-
-/** GPIO_FUNC2_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160)
-/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC2_IN_SEL    0x0000003FU
-#define GPIO_FUNC2_IN_SEL_M  (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S)
-#define GPIO_FUNC2_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC2_IN_SEL_S  0
-/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC2_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC2_IN_INV_SEL_M  (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S)
-#define GPIO_FUNC2_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC2_IN_INV_SEL_S  6
-/** GPIO_SIG2_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG2_IN_SEL    (BIT(7))
-#define GPIO_SIG2_IN_SEL_M  (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S)
-#define GPIO_SIG2_IN_SEL_V  0x00000001U
-#define GPIO_SIG2_IN_SEL_S  7
-
-/** GPIO_FUNC3_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164)
-/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC3_IN_SEL    0x0000003FU
-#define GPIO_FUNC3_IN_SEL_M  (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S)
-#define GPIO_FUNC3_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC3_IN_SEL_S  0
-/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC3_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC3_IN_INV_SEL_M  (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S)
-#define GPIO_FUNC3_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC3_IN_INV_SEL_S  6
-/** GPIO_SIG3_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG3_IN_SEL    (BIT(7))
-#define GPIO_SIG3_IN_SEL_M  (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S)
-#define GPIO_SIG3_IN_SEL_V  0x00000001U
-#define GPIO_SIG3_IN_SEL_S  7
-
-/** GPIO_FUNC4_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168)
-/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC4_IN_SEL    0x0000003FU
-#define GPIO_FUNC4_IN_SEL_M  (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S)
-#define GPIO_FUNC4_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC4_IN_SEL_S  0
-/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC4_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC4_IN_INV_SEL_M  (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S)
-#define GPIO_FUNC4_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC4_IN_INV_SEL_S  6
-/** GPIO_SIG4_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG4_IN_SEL    (BIT(7))
-#define GPIO_SIG4_IN_SEL_M  (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S)
-#define GPIO_SIG4_IN_SEL_V  0x00000001U
-#define GPIO_SIG4_IN_SEL_S  7
-
-/** GPIO_FUNC5_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
-/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC5_IN_SEL    0x0000003FU
-#define GPIO_FUNC5_IN_SEL_M  (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S)
-#define GPIO_FUNC5_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC5_IN_SEL_S  0
-/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC5_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC5_IN_INV_SEL_M  (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S)
-#define GPIO_FUNC5_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC5_IN_INV_SEL_S  6
-/** GPIO_SIG5_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG5_IN_SEL    (BIT(7))
-#define GPIO_SIG5_IN_SEL_M  (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S)
-#define GPIO_SIG5_IN_SEL_V  0x00000001U
-#define GPIO_SIG5_IN_SEL_S  7
-
-/** GPIO_FUNC6_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170)
-/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC6_IN_SEL    0x0000003FU
-#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
-#define GPIO_FUNC6_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC6_IN_SEL_S  0
-/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
-#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_IN_INV_SEL_S  6
-/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG6_IN_SEL    (BIT(7))
-#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
-#define GPIO_SIG6_IN_SEL_V  0x00000001U
-#define GPIO_SIG6_IN_SEL_S  7
-
-/** GPIO_FUNC7_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174)
-/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC7_IN_SEL    0x0000003FU
-#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
-#define GPIO_FUNC7_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC7_IN_SEL_S  0
-/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
-#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_IN_INV_SEL_S  6
-/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG7_IN_SEL    (BIT(7))
-#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
-#define GPIO_SIG7_IN_SEL_V  0x00000001U
-#define GPIO_SIG7_IN_SEL_S  7
-
-/** GPIO_FUNC8_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178)
-/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC8_IN_SEL    0x0000003FU
-#define GPIO_FUNC8_IN_SEL_M  (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S)
-#define GPIO_FUNC8_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC8_IN_SEL_S  0
-/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC8_IN_INV_SEL_M  (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S)
-#define GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_IN_INV_SEL_S  6
-/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG8_IN_SEL    (BIT(7))
-#define GPIO_SIG8_IN_SEL_M  (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S)
-#define GPIO_SIG8_IN_SEL_V  0x00000001U
-#define GPIO_SIG8_IN_SEL_S  7
-
-/** GPIO_FUNC9_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c)
-/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC9_IN_SEL    0x0000003FU
-#define GPIO_FUNC9_IN_SEL_M  (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S)
-#define GPIO_FUNC9_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC9_IN_SEL_S  0
-/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC9_IN_INV_SEL_M  (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S)
-#define GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_IN_INV_SEL_S  6
-/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG9_IN_SEL    (BIT(7))
-#define GPIO_SIG9_IN_SEL_M  (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S)
-#define GPIO_SIG9_IN_SEL_V  0x00000001U
-#define GPIO_SIG9_IN_SEL_S  7
-
-/** GPIO_FUNC10_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180)
-/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC10_IN_SEL    0x0000003FU
-#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
-#define GPIO_FUNC10_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC10_IN_SEL_S  0
-/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
-#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_IN_INV_SEL_S  6
-/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG10_IN_SEL    (BIT(7))
-#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
-#define GPIO_SIG10_IN_SEL_V  0x00000001U
-#define GPIO_SIG10_IN_SEL_S  7
-
-/** GPIO_FUNC11_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184)
-/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC11_IN_SEL    0x0000003FU
-#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
-#define GPIO_FUNC11_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC11_IN_SEL_S  0
-/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
-#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_IN_INV_SEL_S  6
-/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG11_IN_SEL    (BIT(7))
-#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
-#define GPIO_SIG11_IN_SEL_V  0x00000001U
-#define GPIO_SIG11_IN_SEL_S  7
-
-/** GPIO_FUNC12_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188)
-/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC12_IN_SEL    0x0000003FU
-#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
-#define GPIO_FUNC12_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC12_IN_SEL_S  0
-/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
-#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_IN_INV_SEL_S  6
-/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG12_IN_SEL    (BIT(7))
-#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
-#define GPIO_SIG12_IN_SEL_V  0x00000001U
-#define GPIO_SIG12_IN_SEL_S  7
-
-/** GPIO_FUNC13_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c)
-/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC13_IN_SEL    0x0000003FU
-#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
-#define GPIO_FUNC13_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC13_IN_SEL_S  0
-/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
-#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_IN_INV_SEL_S  6
-/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG13_IN_SEL    (BIT(7))
-#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
-#define GPIO_SIG13_IN_SEL_V  0x00000001U
-#define GPIO_SIG13_IN_SEL_S  7
-
-/** GPIO_FUNC14_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190)
-/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC14_IN_SEL    0x0000003FU
-#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
-#define GPIO_FUNC14_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC14_IN_SEL_S  0
-/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
-#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_IN_INV_SEL_S  6
-/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG14_IN_SEL    (BIT(7))
-#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
-#define GPIO_SIG14_IN_SEL_V  0x00000001U
-#define GPIO_SIG14_IN_SEL_S  7
-
-/** GPIO_FUNC15_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194)
-/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC15_IN_SEL    0x0000003FU
-#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
-#define GPIO_FUNC15_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC15_IN_SEL_S  0
-/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
-#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_IN_INV_SEL_S  6
-/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG15_IN_SEL    (BIT(7))
-#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
-#define GPIO_SIG15_IN_SEL_V  0x00000001U
-#define GPIO_SIG15_IN_SEL_S  7
-
-/** GPIO_FUNC16_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198)
-/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC16_IN_SEL    0x0000003FU
-#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
-#define GPIO_FUNC16_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC16_IN_SEL_S  0
-/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
-#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_IN_INV_SEL_S  6
-/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG16_IN_SEL    (BIT(7))
-#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
-#define GPIO_SIG16_IN_SEL_V  0x00000001U
-#define GPIO_SIG16_IN_SEL_S  7
-
-/** GPIO_FUNC17_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c)
-/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC17_IN_SEL    0x0000003FU
-#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
-#define GPIO_FUNC17_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC17_IN_SEL_S  0
-/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
-#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_IN_INV_SEL_S  6
-/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG17_IN_SEL    (BIT(7))
-#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
-#define GPIO_SIG17_IN_SEL_V  0x00000001U
-#define GPIO_SIG17_IN_SEL_S  7
-
-/** GPIO_FUNC18_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0)
-/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC18_IN_SEL    0x0000003FU
-#define GPIO_FUNC18_IN_SEL_M  (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S)
-#define GPIO_FUNC18_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC18_IN_SEL_S  0
-/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC18_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC18_IN_INV_SEL_M  (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S)
-#define GPIO_FUNC18_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC18_IN_INV_SEL_S  6
-/** GPIO_SIG18_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG18_IN_SEL    (BIT(7))
-#define GPIO_SIG18_IN_SEL_M  (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S)
-#define GPIO_SIG18_IN_SEL_V  0x00000001U
-#define GPIO_SIG18_IN_SEL_S  7
-
-/** GPIO_FUNC19_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4)
-/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC19_IN_SEL    0x0000003FU
-#define GPIO_FUNC19_IN_SEL_M  (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S)
-#define GPIO_FUNC19_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC19_IN_SEL_S  0
-/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC19_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC19_IN_INV_SEL_M  (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S)
-#define GPIO_FUNC19_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC19_IN_INV_SEL_S  6
-/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG19_IN_SEL    (BIT(7))
-#define GPIO_SIG19_IN_SEL_M  (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S)
-#define GPIO_SIG19_IN_SEL_V  0x00000001U
-#define GPIO_SIG19_IN_SEL_S  7
-
-/** GPIO_FUNC20_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8)
-/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC20_IN_SEL    0x0000003FU
-#define GPIO_FUNC20_IN_SEL_M  (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S)
-#define GPIO_FUNC20_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC20_IN_SEL_S  0
-/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC20_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC20_IN_INV_SEL_M  (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S)
-#define GPIO_FUNC20_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC20_IN_INV_SEL_S  6
-/** GPIO_SIG20_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG20_IN_SEL    (BIT(7))
-#define GPIO_SIG20_IN_SEL_M  (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S)
-#define GPIO_SIG20_IN_SEL_V  0x00000001U
-#define GPIO_SIG20_IN_SEL_S  7
-
-/** GPIO_FUNC21_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac)
-/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC21_IN_SEL    0x0000003FU
-#define GPIO_FUNC21_IN_SEL_M  (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S)
-#define GPIO_FUNC21_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC21_IN_SEL_S  0
-/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC21_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC21_IN_INV_SEL_M  (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S)
-#define GPIO_FUNC21_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC21_IN_INV_SEL_S  6
-/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG21_IN_SEL    (BIT(7))
-#define GPIO_SIG21_IN_SEL_M  (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S)
-#define GPIO_SIG21_IN_SEL_V  0x00000001U
-#define GPIO_SIG21_IN_SEL_S  7
-
-/** GPIO_FUNC22_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0)
-/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC22_IN_SEL    0x0000003FU
-#define GPIO_FUNC22_IN_SEL_M  (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S)
-#define GPIO_FUNC22_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC22_IN_SEL_S  0
-/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC22_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC22_IN_INV_SEL_M  (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S)
-#define GPIO_FUNC22_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC22_IN_INV_SEL_S  6
-/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG22_IN_SEL    (BIT(7))
-#define GPIO_SIG22_IN_SEL_M  (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S)
-#define GPIO_SIG22_IN_SEL_V  0x00000001U
-#define GPIO_SIG22_IN_SEL_S  7
-
-/** GPIO_FUNC23_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4)
-/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC23_IN_SEL    0x0000003FU
-#define GPIO_FUNC23_IN_SEL_M  (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S)
-#define GPIO_FUNC23_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC23_IN_SEL_S  0
-/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC23_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC23_IN_INV_SEL_M  (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S)
-#define GPIO_FUNC23_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC23_IN_INV_SEL_S  6
-/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG23_IN_SEL    (BIT(7))
-#define GPIO_SIG23_IN_SEL_M  (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S)
-#define GPIO_SIG23_IN_SEL_V  0x00000001U
-#define GPIO_SIG23_IN_SEL_S  7
-
-/** GPIO_FUNC24_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8)
-/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC24_IN_SEL    0x0000003FU
-#define GPIO_FUNC24_IN_SEL_M  (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S)
-#define GPIO_FUNC24_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC24_IN_SEL_S  0
-/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC24_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC24_IN_INV_SEL_M  (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S)
-#define GPIO_FUNC24_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC24_IN_INV_SEL_S  6
-/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG24_IN_SEL    (BIT(7))
-#define GPIO_SIG24_IN_SEL_M  (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S)
-#define GPIO_SIG24_IN_SEL_V  0x00000001U
-#define GPIO_SIG24_IN_SEL_S  7
-
-/** GPIO_FUNC25_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc)
-/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC25_IN_SEL    0x0000003FU
-#define GPIO_FUNC25_IN_SEL_M  (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S)
-#define GPIO_FUNC25_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC25_IN_SEL_S  0
-/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC25_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC25_IN_INV_SEL_M  (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S)
-#define GPIO_FUNC25_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC25_IN_INV_SEL_S  6
-/** GPIO_SIG25_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG25_IN_SEL    (BIT(7))
-#define GPIO_SIG25_IN_SEL_M  (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S)
-#define GPIO_SIG25_IN_SEL_V  0x00000001U
-#define GPIO_SIG25_IN_SEL_S  7
-
-/** GPIO_FUNC26_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0)
-/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC26_IN_SEL    0x0000003FU
-#define GPIO_FUNC26_IN_SEL_M  (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S)
-#define GPIO_FUNC26_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC26_IN_SEL_S  0
-/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC26_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC26_IN_INV_SEL_M  (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S)
-#define GPIO_FUNC26_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC26_IN_INV_SEL_S  6
-/** GPIO_SIG26_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG26_IN_SEL    (BIT(7))
-#define GPIO_SIG26_IN_SEL_M  (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S)
-#define GPIO_SIG26_IN_SEL_V  0x00000001U
-#define GPIO_SIG26_IN_SEL_S  7
-
-/** GPIO_FUNC27_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4)
-/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC27_IN_SEL    0x0000003FU
-#define GPIO_FUNC27_IN_SEL_M  (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S)
-#define GPIO_FUNC27_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC27_IN_SEL_S  0
-/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC27_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC27_IN_INV_SEL_M  (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S)
-#define GPIO_FUNC27_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC27_IN_INV_SEL_S  6
-/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG27_IN_SEL    (BIT(7))
-#define GPIO_SIG27_IN_SEL_M  (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S)
-#define GPIO_SIG27_IN_SEL_V  0x00000001U
-#define GPIO_SIG27_IN_SEL_S  7
-
-/** GPIO_FUNC28_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8)
-/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC28_IN_SEL    0x0000003FU
-#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
-#define GPIO_FUNC28_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC28_IN_SEL_S  0
-/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
-#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC28_IN_INV_SEL_S  6
-/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG28_IN_SEL    (BIT(7))
-#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
-#define GPIO_SIG28_IN_SEL_V  0x00000001U
-#define GPIO_SIG28_IN_SEL_S  7
-
-/** GPIO_FUNC29_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc)
-/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC29_IN_SEL    0x0000003FU
-#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
-#define GPIO_FUNC29_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC29_IN_SEL_S  0
-/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
-#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC29_IN_INV_SEL_S  6
-/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG29_IN_SEL    (BIT(7))
-#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
-#define GPIO_SIG29_IN_SEL_V  0x00000001U
-#define GPIO_SIG29_IN_SEL_S  7
-
-/** GPIO_FUNC30_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0)
-/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC30_IN_SEL    0x0000003FU
-#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
-#define GPIO_FUNC30_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC30_IN_SEL_S  0
-/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
-#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC30_IN_INV_SEL_S  6
-/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG30_IN_SEL    (BIT(7))
-#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
-#define GPIO_SIG30_IN_SEL_V  0x00000001U
-#define GPIO_SIG30_IN_SEL_S  7
-
-/** GPIO_FUNC31_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4)
-/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC31_IN_SEL    0x0000003FU
-#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
-#define GPIO_FUNC31_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC31_IN_SEL_S  0
-/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
-#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC31_IN_INV_SEL_S  6
-/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG31_IN_SEL    (BIT(7))
-#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
-#define GPIO_SIG31_IN_SEL_V  0x00000001U
-#define GPIO_SIG31_IN_SEL_S  7
-
-/** GPIO_FUNC32_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8)
-/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC32_IN_SEL    0x0000003FU
-#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
-#define GPIO_FUNC32_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC32_IN_SEL_S  0
-/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
-#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC32_IN_INV_SEL_S  6
-/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG32_IN_SEL    (BIT(7))
-#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
-#define GPIO_SIG32_IN_SEL_V  0x00000001U
-#define GPIO_SIG32_IN_SEL_S  7
-
-/** GPIO_FUNC33_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc)
-/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC33_IN_SEL    0x0000003FU
-#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
-#define GPIO_FUNC33_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC33_IN_SEL_S  0
-/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
-#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC33_IN_INV_SEL_S  6
-/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG33_IN_SEL    (BIT(7))
-#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
-#define GPIO_SIG33_IN_SEL_V  0x00000001U
-#define GPIO_SIG33_IN_SEL_S  7
-
-/** GPIO_FUNC34_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0)
-/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC34_IN_SEL    0x0000003FU
-#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
-#define GPIO_FUNC34_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC34_IN_SEL_S  0
-/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
-#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC34_IN_INV_SEL_S  6
-/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG34_IN_SEL    (BIT(7))
-#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
-#define GPIO_SIG34_IN_SEL_V  0x00000001U
-#define GPIO_SIG34_IN_SEL_S  7
-
-/** GPIO_FUNC35_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4)
-/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC35_IN_SEL    0x0000003FU
-#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
-#define GPIO_FUNC35_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC35_IN_SEL_S  0
-/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
-#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC35_IN_INV_SEL_S  6
-/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG35_IN_SEL    (BIT(7))
-#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
-#define GPIO_SIG35_IN_SEL_V  0x00000001U
-#define GPIO_SIG35_IN_SEL_S  7
-
-/** GPIO_FUNC36_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8)
-/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC36_IN_SEL    0x0000003FU
-#define GPIO_FUNC36_IN_SEL_M  (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S)
-#define GPIO_FUNC36_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC36_IN_SEL_S  0
-/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC36_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC36_IN_INV_SEL_M  (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S)
-#define GPIO_FUNC36_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC36_IN_INV_SEL_S  6
-/** GPIO_SIG36_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG36_IN_SEL    (BIT(7))
-#define GPIO_SIG36_IN_SEL_M  (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S)
-#define GPIO_SIG36_IN_SEL_V  0x00000001U
-#define GPIO_SIG36_IN_SEL_S  7
-
-/** GPIO_FUNC37_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec)
-/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC37_IN_SEL    0x0000003FU
-#define GPIO_FUNC37_IN_SEL_M  (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S)
-#define GPIO_FUNC37_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC37_IN_SEL_S  0
-/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC37_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC37_IN_INV_SEL_M  (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S)
-#define GPIO_FUNC37_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC37_IN_INV_SEL_S  6
-/** GPIO_SIG37_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG37_IN_SEL    (BIT(7))
-#define GPIO_SIG37_IN_SEL_M  (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S)
-#define GPIO_SIG37_IN_SEL_V  0x00000001U
-#define GPIO_SIG37_IN_SEL_S  7
-
-/** GPIO_FUNC38_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0)
-/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC38_IN_SEL    0x0000003FU
-#define GPIO_FUNC38_IN_SEL_M  (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S)
-#define GPIO_FUNC38_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC38_IN_SEL_S  0
-/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC38_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC38_IN_INV_SEL_M  (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S)
-#define GPIO_FUNC38_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC38_IN_INV_SEL_S  6
-/** GPIO_SIG38_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG38_IN_SEL    (BIT(7))
-#define GPIO_SIG38_IN_SEL_M  (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S)
-#define GPIO_SIG38_IN_SEL_V  0x00000001U
-#define GPIO_SIG38_IN_SEL_S  7
-
-/** GPIO_FUNC39_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4)
-/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC39_IN_SEL    0x0000003FU
-#define GPIO_FUNC39_IN_SEL_M  (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S)
-#define GPIO_FUNC39_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC39_IN_SEL_S  0
-/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC39_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC39_IN_INV_SEL_M  (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S)
-#define GPIO_FUNC39_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC39_IN_INV_SEL_S  6
-/** GPIO_SIG39_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG39_IN_SEL    (BIT(7))
-#define GPIO_SIG39_IN_SEL_M  (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S)
-#define GPIO_SIG39_IN_SEL_V  0x00000001U
-#define GPIO_SIG39_IN_SEL_S  7
-
-/** GPIO_FUNC40_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8)
-/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC40_IN_SEL    0x0000003FU
-#define GPIO_FUNC40_IN_SEL_M  (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S)
-#define GPIO_FUNC40_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC40_IN_SEL_S  0
-/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC40_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC40_IN_INV_SEL_M  (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S)
-#define GPIO_FUNC40_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC40_IN_INV_SEL_S  6
-/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG40_IN_SEL    (BIT(7))
-#define GPIO_SIG40_IN_SEL_M  (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S)
-#define GPIO_SIG40_IN_SEL_V  0x00000001U
-#define GPIO_SIG40_IN_SEL_S  7
-
-/** GPIO_FUNC41_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc)
-/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC41_IN_SEL    0x0000003FU
-#define GPIO_FUNC41_IN_SEL_M  (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S)
-#define GPIO_FUNC41_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC41_IN_SEL_S  0
-/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC41_IN_INV_SEL_M  (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S)
-#define GPIO_FUNC41_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC41_IN_INV_SEL_S  6
-/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG41_IN_SEL    (BIT(7))
-#define GPIO_SIG41_IN_SEL_M  (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S)
-#define GPIO_SIG41_IN_SEL_V  0x00000001U
-#define GPIO_SIG41_IN_SEL_S  7
-
-/** GPIO_FUNC42_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200)
-/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC42_IN_SEL    0x0000003FU
-#define GPIO_FUNC42_IN_SEL_M  (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S)
-#define GPIO_FUNC42_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC42_IN_SEL_S  0
-/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC42_IN_INV_SEL_M  (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S)
-#define GPIO_FUNC42_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC42_IN_INV_SEL_S  6
-/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG42_IN_SEL    (BIT(7))
-#define GPIO_SIG42_IN_SEL_M  (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S)
-#define GPIO_SIG42_IN_SEL_V  0x00000001U
-#define GPIO_SIG42_IN_SEL_S  7
-
-/** GPIO_FUNC43_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204)
-/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC43_IN_SEL    0x0000003FU
-#define GPIO_FUNC43_IN_SEL_M  (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S)
-#define GPIO_FUNC43_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC43_IN_SEL_S  0
-/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC43_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC43_IN_INV_SEL_M  (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S)
-#define GPIO_FUNC43_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC43_IN_INV_SEL_S  6
-/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG43_IN_SEL    (BIT(7))
-#define GPIO_SIG43_IN_SEL_M  (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S)
-#define GPIO_SIG43_IN_SEL_V  0x00000001U
-#define GPIO_SIG43_IN_SEL_S  7
-
-/** GPIO_FUNC44_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208)
-/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC44_IN_SEL    0x0000003FU
-#define GPIO_FUNC44_IN_SEL_M  (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S)
-#define GPIO_FUNC44_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC44_IN_SEL_S  0
-/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC44_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC44_IN_INV_SEL_M  (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S)
-#define GPIO_FUNC44_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC44_IN_INV_SEL_S  6
-/** GPIO_SIG44_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG44_IN_SEL    (BIT(7))
-#define GPIO_SIG44_IN_SEL_M  (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S)
-#define GPIO_SIG44_IN_SEL_V  0x00000001U
-#define GPIO_SIG44_IN_SEL_S  7
-
-/** GPIO_FUNC45_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c)
-/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC45_IN_SEL    0x0000003FU
-#define GPIO_FUNC45_IN_SEL_M  (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S)
-#define GPIO_FUNC45_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC45_IN_SEL_S  0
-/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC45_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC45_IN_INV_SEL_M  (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S)
-#define GPIO_FUNC45_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC45_IN_INV_SEL_S  6
-/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG45_IN_SEL    (BIT(7))
-#define GPIO_SIG45_IN_SEL_M  (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S)
-#define GPIO_SIG45_IN_SEL_V  0x00000001U
-#define GPIO_SIG45_IN_SEL_S  7
-
-/** GPIO_FUNC47_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214)
-/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC47_IN_SEL    0x0000003FU
-#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
-#define GPIO_FUNC47_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC47_IN_SEL_S  0
-/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
-#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC47_IN_INV_SEL_S  6
-/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG47_IN_SEL    (BIT(7))
-#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
-#define GPIO_SIG47_IN_SEL_V  0x00000001U
-#define GPIO_SIG47_IN_SEL_S  7
-
-/** GPIO_FUNC48_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218)
-/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC48_IN_SEL    0x0000003FU
-#define GPIO_FUNC48_IN_SEL_M  (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S)
-#define GPIO_FUNC48_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC48_IN_SEL_S  0
-/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC48_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC48_IN_INV_SEL_M  (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S)
-#define GPIO_FUNC48_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC48_IN_INV_SEL_S  6
-/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG48_IN_SEL    (BIT(7))
-#define GPIO_SIG48_IN_SEL_M  (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S)
-#define GPIO_SIG48_IN_SEL_V  0x00000001U
-#define GPIO_SIG48_IN_SEL_S  7
-
-/** GPIO_FUNC49_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c)
-/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC49_IN_SEL    0x0000003FU
-#define GPIO_FUNC49_IN_SEL_M  (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S)
-#define GPIO_FUNC49_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC49_IN_SEL_S  0
-/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC49_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC49_IN_INV_SEL_M  (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S)
-#define GPIO_FUNC49_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC49_IN_INV_SEL_S  6
-/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG49_IN_SEL    (BIT(7))
-#define GPIO_SIG49_IN_SEL_M  (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S)
-#define GPIO_SIG49_IN_SEL_V  0x00000001U
-#define GPIO_SIG49_IN_SEL_S  7
-
-/** GPIO_FUNC50_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220)
-/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC50_IN_SEL    0x0000003FU
-#define GPIO_FUNC50_IN_SEL_M  (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S)
-#define GPIO_FUNC50_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC50_IN_SEL_S  0
-/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC50_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC50_IN_INV_SEL_M  (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S)
-#define GPIO_FUNC50_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC50_IN_INV_SEL_S  6
-/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG50_IN_SEL    (BIT(7))
-#define GPIO_SIG50_IN_SEL_M  (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S)
-#define GPIO_SIG50_IN_SEL_V  0x00000001U
-#define GPIO_SIG50_IN_SEL_S  7
-
-/** GPIO_FUNC51_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224)
-/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC51_IN_SEL    0x0000003FU
-#define GPIO_FUNC51_IN_SEL_M  (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S)
-#define GPIO_FUNC51_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC51_IN_SEL_S  0
-/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC51_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC51_IN_INV_SEL_M  (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S)
-#define GPIO_FUNC51_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC51_IN_INV_SEL_S  6
-/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG51_IN_SEL    (BIT(7))
-#define GPIO_SIG51_IN_SEL_M  (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S)
-#define GPIO_SIG51_IN_SEL_V  0x00000001U
-#define GPIO_SIG51_IN_SEL_S  7
-
-/** GPIO_FUNC52_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228)
-/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC52_IN_SEL    0x0000003FU
-#define GPIO_FUNC52_IN_SEL_M  (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S)
-#define GPIO_FUNC52_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC52_IN_SEL_S  0
-/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC52_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC52_IN_INV_SEL_M  (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S)
-#define GPIO_FUNC52_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC52_IN_INV_SEL_S  6
-/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG52_IN_SEL    (BIT(7))
-#define GPIO_SIG52_IN_SEL_M  (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S)
-#define GPIO_SIG52_IN_SEL_V  0x00000001U
-#define GPIO_SIG52_IN_SEL_S  7
-
-/** GPIO_FUNC53_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c)
-/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC53_IN_SEL    0x0000003FU
-#define GPIO_FUNC53_IN_SEL_M  (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S)
-#define GPIO_FUNC53_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC53_IN_SEL_S  0
-/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC53_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC53_IN_INV_SEL_M  (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S)
-#define GPIO_FUNC53_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC53_IN_INV_SEL_S  6
-/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG53_IN_SEL    (BIT(7))
-#define GPIO_SIG53_IN_SEL_M  (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S)
-#define GPIO_SIG53_IN_SEL_V  0x00000001U
-#define GPIO_SIG53_IN_SEL_S  7
-
-/** GPIO_FUNC54_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230)
-/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC54_IN_SEL    0x0000003FU
-#define GPIO_FUNC54_IN_SEL_M  (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S)
-#define GPIO_FUNC54_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC54_IN_SEL_S  0
-/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC54_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC54_IN_INV_SEL_M  (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S)
-#define GPIO_FUNC54_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC54_IN_INV_SEL_S  6
-/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG54_IN_SEL    (BIT(7))
-#define GPIO_SIG54_IN_SEL_M  (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S)
-#define GPIO_SIG54_IN_SEL_V  0x00000001U
-#define GPIO_SIG54_IN_SEL_S  7
-
-/** GPIO_FUNC55_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234)
-/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC55_IN_SEL    0x0000003FU
-#define GPIO_FUNC55_IN_SEL_M  (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S)
-#define GPIO_FUNC55_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC55_IN_SEL_S  0
-/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC55_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC55_IN_INV_SEL_M  (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S)
-#define GPIO_FUNC55_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC55_IN_INV_SEL_S  6
-/** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG55_IN_SEL    (BIT(7))
-#define GPIO_SIG55_IN_SEL_M  (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S)
-#define GPIO_SIG55_IN_SEL_V  0x00000001U
-#define GPIO_SIG55_IN_SEL_S  7
-
-/** GPIO_FUNC56_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238)
-/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC56_IN_SEL    0x0000003FU
-#define GPIO_FUNC56_IN_SEL_M  (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S)
-#define GPIO_FUNC56_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC56_IN_SEL_S  0
-/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC56_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC56_IN_INV_SEL_M  (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S)
-#define GPIO_FUNC56_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC56_IN_INV_SEL_S  6
-/** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG56_IN_SEL    (BIT(7))
-#define GPIO_SIG56_IN_SEL_M  (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S)
-#define GPIO_SIG56_IN_SEL_V  0x00000001U
-#define GPIO_SIG56_IN_SEL_S  7
-
-/** GPIO_FUNC57_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c)
-/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC57_IN_SEL    0x0000003FU
-#define GPIO_FUNC57_IN_SEL_M  (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S)
-#define GPIO_FUNC57_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC57_IN_SEL_S  0
-/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC57_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC57_IN_INV_SEL_M  (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S)
-#define GPIO_FUNC57_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC57_IN_INV_SEL_S  6
-/** GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG57_IN_SEL    (BIT(7))
-#define GPIO_SIG57_IN_SEL_M  (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S)
-#define GPIO_SIG57_IN_SEL_V  0x00000001U
-#define GPIO_SIG57_IN_SEL_S  7
-
-/** GPIO_FUNC58_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240)
-/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC58_IN_SEL    0x0000003FU
-#define GPIO_FUNC58_IN_SEL_M  (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S)
-#define GPIO_FUNC58_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC58_IN_SEL_S  0
-/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC58_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC58_IN_INV_SEL_M  (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S)
-#define GPIO_FUNC58_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC58_IN_INV_SEL_S  6
-/** GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG58_IN_SEL    (BIT(7))
-#define GPIO_SIG58_IN_SEL_M  (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S)
-#define GPIO_SIG58_IN_SEL_V  0x00000001U
-#define GPIO_SIG58_IN_SEL_S  7
-
-/** GPIO_FUNC59_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244)
-/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC59_IN_SEL    0x0000003FU
-#define GPIO_FUNC59_IN_SEL_M  (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S)
-#define GPIO_FUNC59_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC59_IN_SEL_S  0
-/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC59_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC59_IN_INV_SEL_M  (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S)
-#define GPIO_FUNC59_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC59_IN_INV_SEL_S  6
-/** GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG59_IN_SEL    (BIT(7))
-#define GPIO_SIG59_IN_SEL_M  (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S)
-#define GPIO_SIG59_IN_SEL_V  0x00000001U
-#define GPIO_SIG59_IN_SEL_S  7
-
-/** GPIO_FUNC60_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248)
-/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC60_IN_SEL    0x0000003FU
-#define GPIO_FUNC60_IN_SEL_M  (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S)
-#define GPIO_FUNC60_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC60_IN_SEL_S  0
-/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC60_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC60_IN_INV_SEL_M  (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S)
-#define GPIO_FUNC60_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC60_IN_INV_SEL_S  6
-/** GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG60_IN_SEL    (BIT(7))
-#define GPIO_SIG60_IN_SEL_M  (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S)
-#define GPIO_SIG60_IN_SEL_V  0x00000001U
-#define GPIO_SIG60_IN_SEL_S  7
-
-/** GPIO_FUNC61_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c)
-/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC61_IN_SEL    0x0000003FU
-#define GPIO_FUNC61_IN_SEL_M  (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S)
-#define GPIO_FUNC61_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC61_IN_SEL_S  0
-/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC61_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC61_IN_INV_SEL_M  (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S)
-#define GPIO_FUNC61_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC61_IN_INV_SEL_S  6
-/** GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG61_IN_SEL    (BIT(7))
-#define GPIO_SIG61_IN_SEL_M  (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S)
-#define GPIO_SIG61_IN_SEL_V  0x00000001U
-#define GPIO_SIG61_IN_SEL_S  7
-
-/** GPIO_FUNC62_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250)
-/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC62_IN_SEL    0x0000003FU
-#define GPIO_FUNC62_IN_SEL_M  (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S)
-#define GPIO_FUNC62_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC62_IN_SEL_S  0
-/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC62_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC62_IN_INV_SEL_M  (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S)
-#define GPIO_FUNC62_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC62_IN_INV_SEL_S  6
-/** GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG62_IN_SEL    (BIT(7))
-#define GPIO_SIG62_IN_SEL_M  (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S)
-#define GPIO_SIG62_IN_SEL_V  0x00000001U
-#define GPIO_SIG62_IN_SEL_S  7
-
-/** GPIO_FUNC63_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254)
-/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC63_IN_SEL    0x0000003FU
-#define GPIO_FUNC63_IN_SEL_M  (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S)
-#define GPIO_FUNC63_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC63_IN_SEL_S  0
-/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC63_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC63_IN_INV_SEL_M  (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S)
-#define GPIO_FUNC63_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC63_IN_INV_SEL_S  6
-/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG63_IN_SEL    (BIT(7))
-#define GPIO_SIG63_IN_SEL_M  (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S)
-#define GPIO_SIG63_IN_SEL_V  0x00000001U
-#define GPIO_SIG63_IN_SEL_S  7
-
-/** GPIO_FUNC64_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258)
-/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC64_IN_SEL    0x0000003FU
-#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
-#define GPIO_FUNC64_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC64_IN_SEL_S  0
-/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
-#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC64_IN_INV_SEL_S  6
-/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG64_IN_SEL    (BIT(7))
-#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
-#define GPIO_SIG64_IN_SEL_V  0x00000001U
-#define GPIO_SIG64_IN_SEL_S  7
-
-/** GPIO_FUNC65_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c)
-/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC65_IN_SEL    0x0000003FU
-#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
-#define GPIO_FUNC65_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC65_IN_SEL_S  0
-/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
-#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC65_IN_INV_SEL_S  6
-/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG65_IN_SEL    (BIT(7))
-#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
-#define GPIO_SIG65_IN_SEL_V  0x00000001U
-#define GPIO_SIG65_IN_SEL_S  7
-
-/** GPIO_FUNC66_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260)
-/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC66_IN_SEL    0x0000003FU
-#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
-#define GPIO_FUNC66_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC66_IN_SEL_S  0
-/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
-#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC66_IN_INV_SEL_S  6
-/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG66_IN_SEL    (BIT(7))
-#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
-#define GPIO_SIG66_IN_SEL_V  0x00000001U
-#define GPIO_SIG66_IN_SEL_S  7
-
-/** GPIO_FUNC68_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268)
-/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC68_IN_SEL    0x0000003FU
-#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
-#define GPIO_FUNC68_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC68_IN_SEL_S  0
-/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
-#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC68_IN_INV_SEL_S  6
-/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG68_IN_SEL    (BIT(7))
-#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
-#define GPIO_SIG68_IN_SEL_V  0x00000001U
-#define GPIO_SIG68_IN_SEL_S  7
-
-/** GPIO_FUNC69_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c)
-/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC69_IN_SEL    0x0000003FU
-#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
-#define GPIO_FUNC69_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC69_IN_SEL_S  0
-/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
-#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC69_IN_INV_SEL_S  6
-/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG69_IN_SEL    (BIT(7))
-#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
-#define GPIO_SIG69_IN_SEL_V  0x00000001U
-#define GPIO_SIG69_IN_SEL_S  7
-
-/** GPIO_FUNC70_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270)
-/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC70_IN_SEL    0x0000003FU
-#define GPIO_FUNC70_IN_SEL_M  (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S)
-#define GPIO_FUNC70_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC70_IN_SEL_S  0
-/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC70_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC70_IN_INV_SEL_M  (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S)
-#define GPIO_FUNC70_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC70_IN_INV_SEL_S  6
-/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG70_IN_SEL    (BIT(7))
-#define GPIO_SIG70_IN_SEL_M  (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S)
-#define GPIO_SIG70_IN_SEL_V  0x00000001U
-#define GPIO_SIG70_IN_SEL_S  7
-
-/** GPIO_FUNC71_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274)
-/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC71_IN_SEL    0x0000003FU
-#define GPIO_FUNC71_IN_SEL_M  (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S)
-#define GPIO_FUNC71_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC71_IN_SEL_S  0
-/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC71_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC71_IN_INV_SEL_M  (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S)
-#define GPIO_FUNC71_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC71_IN_INV_SEL_S  6
-/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG71_IN_SEL    (BIT(7))
-#define GPIO_SIG71_IN_SEL_M  (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S)
-#define GPIO_SIG71_IN_SEL_V  0x00000001U
-#define GPIO_SIG71_IN_SEL_S  7
-
-/** GPIO_FUNC74_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280)
-/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC74_IN_SEL    0x0000003FU
-#define GPIO_FUNC74_IN_SEL_M  (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S)
-#define GPIO_FUNC74_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC74_IN_SEL_S  0
-/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC74_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC74_IN_INV_SEL_M  (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S)
-#define GPIO_FUNC74_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC74_IN_INV_SEL_S  6
-/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG74_IN_SEL    (BIT(7))
-#define GPIO_SIG74_IN_SEL_M  (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S)
-#define GPIO_SIG74_IN_SEL_V  0x00000001U
-#define GPIO_SIG74_IN_SEL_S  7
-
-/** GPIO_FUNC75_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284)
-/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC75_IN_SEL    0x0000003FU
-#define GPIO_FUNC75_IN_SEL_M  (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S)
-#define GPIO_FUNC75_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC75_IN_SEL_S  0
-/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC75_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC75_IN_INV_SEL_M  (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S)
-#define GPIO_FUNC75_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC75_IN_INV_SEL_S  6
-/** GPIO_SIG75_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG75_IN_SEL    (BIT(7))
-#define GPIO_SIG75_IN_SEL_M  (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S)
-#define GPIO_SIG75_IN_SEL_V  0x00000001U
-#define GPIO_SIG75_IN_SEL_S  7
-
-/** GPIO_FUNC76_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288)
-/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC76_IN_SEL    0x0000003FU
-#define GPIO_FUNC76_IN_SEL_M  (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S)
-#define GPIO_FUNC76_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC76_IN_SEL_S  0
-/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC76_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC76_IN_INV_SEL_M  (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S)
-#define GPIO_FUNC76_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC76_IN_INV_SEL_S  6
-/** GPIO_SIG76_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG76_IN_SEL    (BIT(7))
-#define GPIO_SIG76_IN_SEL_M  (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S)
-#define GPIO_SIG76_IN_SEL_V  0x00000001U
-#define GPIO_SIG76_IN_SEL_S  7
-
-/** GPIO_FUNC77_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c)
-/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC77_IN_SEL    0x0000003FU
-#define GPIO_FUNC77_IN_SEL_M  (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S)
-#define GPIO_FUNC77_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC77_IN_SEL_S  0
-/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC77_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC77_IN_INV_SEL_M  (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S)
-#define GPIO_FUNC77_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC77_IN_INV_SEL_S  6
-/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG77_IN_SEL    (BIT(7))
-#define GPIO_SIG77_IN_SEL_M  (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S)
-#define GPIO_SIG77_IN_SEL_V  0x00000001U
-#define GPIO_SIG77_IN_SEL_S  7
-
-/** GPIO_FUNC78_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290)
-/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC78_IN_SEL    0x0000003FU
-#define GPIO_FUNC78_IN_SEL_M  (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S)
-#define GPIO_FUNC78_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC78_IN_SEL_S  0
-/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC78_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC78_IN_INV_SEL_M  (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S)
-#define GPIO_FUNC78_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC78_IN_INV_SEL_S  6
-/** GPIO_SIG78_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG78_IN_SEL    (BIT(7))
-#define GPIO_SIG78_IN_SEL_M  (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S)
-#define GPIO_SIG78_IN_SEL_V  0x00000001U
-#define GPIO_SIG78_IN_SEL_S  7
-
-/** GPIO_FUNC80_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298)
-/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC80_IN_SEL    0x0000003FU
-#define GPIO_FUNC80_IN_SEL_M  (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S)
-#define GPIO_FUNC80_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC80_IN_SEL_S  0
-/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC80_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC80_IN_INV_SEL_M  (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S)
-#define GPIO_FUNC80_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC80_IN_INV_SEL_S  6
-/** GPIO_SIG80_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG80_IN_SEL    (BIT(7))
-#define GPIO_SIG80_IN_SEL_M  (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S)
-#define GPIO_SIG80_IN_SEL_V  0x00000001U
-#define GPIO_SIG80_IN_SEL_S  7
-
-/** GPIO_FUNC83_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4)
-/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC83_IN_SEL    0x0000003FU
-#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
-#define GPIO_FUNC83_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC83_IN_SEL_S  0
-/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
-#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC83_IN_INV_SEL_S  6
-/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG83_IN_SEL    (BIT(7))
-#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
-#define GPIO_SIG83_IN_SEL_V  0x00000001U
-#define GPIO_SIG83_IN_SEL_S  7
-
-/** GPIO_FUNC86_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0)
-/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC86_IN_SEL    0x0000003FU
-#define GPIO_FUNC86_IN_SEL_M  (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S)
-#define GPIO_FUNC86_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC86_IN_SEL_S  0
-/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC86_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC86_IN_INV_SEL_M  (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S)
-#define GPIO_FUNC86_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC86_IN_INV_SEL_S  6
-/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG86_IN_SEL    (BIT(7))
-#define GPIO_SIG86_IN_SEL_M  (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S)
-#define GPIO_SIG86_IN_SEL_V  0x00000001U
-#define GPIO_SIG86_IN_SEL_S  7
-
-/** GPIO_FUNC89_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc)
-/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC89_IN_SEL    0x0000003FU
-#define GPIO_FUNC89_IN_SEL_M  (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S)
-#define GPIO_FUNC89_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC89_IN_SEL_S  0
-/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC89_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC89_IN_INV_SEL_M  (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S)
-#define GPIO_FUNC89_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC89_IN_INV_SEL_S  6
-/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG89_IN_SEL    (BIT(7))
-#define GPIO_SIG89_IN_SEL_M  (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S)
-#define GPIO_SIG89_IN_SEL_V  0x00000001U
-#define GPIO_SIG89_IN_SEL_S  7
-
-/** GPIO_FUNC90_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0)
-/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC90_IN_SEL    0x0000003FU
-#define GPIO_FUNC90_IN_SEL_M  (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S)
-#define GPIO_FUNC90_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC90_IN_SEL_S  0
-/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC90_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC90_IN_INV_SEL_M  (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S)
-#define GPIO_FUNC90_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC90_IN_INV_SEL_S  6
-/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG90_IN_SEL    (BIT(7))
-#define GPIO_SIG90_IN_SEL_M  (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S)
-#define GPIO_SIG90_IN_SEL_V  0x00000001U
-#define GPIO_SIG90_IN_SEL_S  7
-
-/** GPIO_FUNC91_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
-/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC91_IN_SEL    0x0000003FU
-#define GPIO_FUNC91_IN_SEL_M  (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S)
-#define GPIO_FUNC91_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC91_IN_SEL_S  0
-/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC91_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC91_IN_INV_SEL_M  (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S)
-#define GPIO_FUNC91_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC91_IN_INV_SEL_S  6
-/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG91_IN_SEL    (BIT(7))
-#define GPIO_SIG91_IN_SEL_M  (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S)
-#define GPIO_SIG91_IN_SEL_V  0x00000001U
-#define GPIO_SIG91_IN_SEL_S  7
-
-/** GPIO_FUNC92_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8)
-/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC92_IN_SEL    0x0000003FU
-#define GPIO_FUNC92_IN_SEL_M  (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S)
-#define GPIO_FUNC92_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC92_IN_SEL_S  0
-/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC92_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC92_IN_INV_SEL_M  (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S)
-#define GPIO_FUNC92_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC92_IN_INV_SEL_S  6
-/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG92_IN_SEL    (BIT(7))
-#define GPIO_SIG92_IN_SEL_M  (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S)
-#define GPIO_SIG92_IN_SEL_V  0x00000001U
-#define GPIO_SIG92_IN_SEL_S  7
-
-/** GPIO_FUNC93_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc)
-/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC93_IN_SEL    0x0000003FU
-#define GPIO_FUNC93_IN_SEL_M  (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S)
-#define GPIO_FUNC93_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC93_IN_SEL_S  0
-/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC93_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC93_IN_INV_SEL_M  (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S)
-#define GPIO_FUNC93_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC93_IN_INV_SEL_S  6
-/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG93_IN_SEL    (BIT(7))
-#define GPIO_SIG93_IN_SEL_M  (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S)
-#define GPIO_SIG93_IN_SEL_V  0x00000001U
-#define GPIO_SIG93_IN_SEL_S  7
-
-/** GPIO_FUNC94_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0)
-/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC94_IN_SEL    0x0000003FU
-#define GPIO_FUNC94_IN_SEL_M  (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S)
-#define GPIO_FUNC94_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC94_IN_SEL_S  0
-/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC94_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC94_IN_INV_SEL_M  (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S)
-#define GPIO_FUNC94_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC94_IN_INV_SEL_S  6
-/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG94_IN_SEL    (BIT(7))
-#define GPIO_SIG94_IN_SEL_M  (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S)
-#define GPIO_SIG94_IN_SEL_V  0x00000001U
-#define GPIO_SIG94_IN_SEL_S  7
-
-/** GPIO_FUNC95_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4)
-/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC95_IN_SEL    0x0000003FU
-#define GPIO_FUNC95_IN_SEL_M  (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S)
-#define GPIO_FUNC95_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC95_IN_SEL_S  0
-/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC95_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC95_IN_INV_SEL_M  (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S)
-#define GPIO_FUNC95_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC95_IN_INV_SEL_S  6
-/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG95_IN_SEL    (BIT(7))
-#define GPIO_SIG95_IN_SEL_M  (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S)
-#define GPIO_SIG95_IN_SEL_V  0x00000001U
-#define GPIO_SIG95_IN_SEL_S  7
-
-/** GPIO_FUNC96_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8)
-/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC96_IN_SEL    0x0000003FU
-#define GPIO_FUNC96_IN_SEL_M  (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S)
-#define GPIO_FUNC96_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC96_IN_SEL_S  0
-/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC96_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC96_IN_INV_SEL_M  (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S)
-#define GPIO_FUNC96_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC96_IN_INV_SEL_S  6
-/** GPIO_SIG96_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG96_IN_SEL    (BIT(7))
-#define GPIO_SIG96_IN_SEL_M  (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S)
-#define GPIO_SIG96_IN_SEL_V  0x00000001U
-#define GPIO_SIG96_IN_SEL_S  7
-
-/** GPIO_FUNC97_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
-/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC97_IN_SEL    0x0000003FU
-#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
-#define GPIO_FUNC97_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC97_IN_SEL_S  0
-/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
-#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC97_IN_INV_SEL_S  6
-/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG97_IN_SEL    (BIT(7))
-#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
-#define GPIO_SIG97_IN_SEL_V  0x00000001U
-#define GPIO_SIG97_IN_SEL_S  7
-
-/** GPIO_FUNC98_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
-/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC98_IN_SEL    0x0000003FU
-#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
-#define GPIO_FUNC98_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC98_IN_SEL_S  0
-/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
-#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC98_IN_INV_SEL_S  6
-/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG98_IN_SEL    (BIT(7))
-#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
-#define GPIO_SIG98_IN_SEL_V  0x00000001U
-#define GPIO_SIG98_IN_SEL_S  7
-
-/** GPIO_FUNC99_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
-/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC99_IN_SEL    0x0000003FU
-#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
-#define GPIO_FUNC99_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC99_IN_SEL_S  0
-/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
-#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC99_IN_INV_SEL_S  6
-/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG99_IN_SEL    (BIT(7))
-#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
-#define GPIO_SIG99_IN_SEL_V  0x00000001U
-#define GPIO_SIG99_IN_SEL_S  7
-
-/** GPIO_FUNC100_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
-/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC100_IN_SEL    0x0000003FU
-#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
-#define GPIO_FUNC100_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC100_IN_SEL_S  0
-/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
-#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC100_IN_INV_SEL_S  6
-/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG100_IN_SEL    (BIT(7))
-#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
-#define GPIO_SIG100_IN_SEL_V  0x00000001U
-#define GPIO_SIG100_IN_SEL_S  7
-
-/** GPIO_FUNC101_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
-/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC101_IN_SEL    0x0000003FU
-#define GPIO_FUNC101_IN_SEL_M  (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S)
-#define GPIO_FUNC101_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC101_IN_SEL_S  0
-/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC101_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC101_IN_INV_SEL_M  (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S)
-#define GPIO_FUNC101_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC101_IN_INV_SEL_S  6
-/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG101_IN_SEL    (BIT(7))
-#define GPIO_SIG101_IN_SEL_M  (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S)
-#define GPIO_SIG101_IN_SEL_V  0x00000001U
-#define GPIO_SIG101_IN_SEL_S  7
-
-/** GPIO_FUNC102_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
-/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC102_IN_SEL    0x0000003FU
-#define GPIO_FUNC102_IN_SEL_M  (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S)
-#define GPIO_FUNC102_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC102_IN_SEL_S  0
-/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC102_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC102_IN_INV_SEL_M  (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S)
-#define GPIO_FUNC102_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC102_IN_INV_SEL_S  6
-/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG102_IN_SEL    (BIT(7))
-#define GPIO_SIG102_IN_SEL_M  (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S)
-#define GPIO_SIG102_IN_SEL_V  0x00000001U
-#define GPIO_SIG102_IN_SEL_S  7
-
-/** GPIO_FUNC103_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
-/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC103_IN_SEL    0x0000003FU
-#define GPIO_FUNC103_IN_SEL_M  (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S)
-#define GPIO_FUNC103_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC103_IN_SEL_S  0
-/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC103_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC103_IN_INV_SEL_M  (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S)
-#define GPIO_FUNC103_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC103_IN_INV_SEL_S  6
-/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG103_IN_SEL    (BIT(7))
-#define GPIO_SIG103_IN_SEL_M  (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S)
-#define GPIO_SIG103_IN_SEL_V  0x00000001U
-#define GPIO_SIG103_IN_SEL_S  7
-
-/** GPIO_FUNC104_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
-/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC104_IN_SEL    0x0000003FU
-#define GPIO_FUNC104_IN_SEL_M  (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S)
-#define GPIO_FUNC104_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC104_IN_SEL_S  0
-/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC104_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC104_IN_INV_SEL_M  (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S)
-#define GPIO_FUNC104_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC104_IN_INV_SEL_S  6
-/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG104_IN_SEL    (BIT(7))
-#define GPIO_SIG104_IN_SEL_M  (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S)
-#define GPIO_SIG104_IN_SEL_V  0x00000001U
-#define GPIO_SIG104_IN_SEL_S  7
-
-/** GPIO_FUNC105_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
-/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC105_IN_SEL    0x0000003FU
-#define GPIO_FUNC105_IN_SEL_M  (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S)
-#define GPIO_FUNC105_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC105_IN_SEL_S  0
-/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC105_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC105_IN_INV_SEL_M  (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S)
-#define GPIO_FUNC105_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC105_IN_INV_SEL_S  6
-/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG105_IN_SEL    (BIT(7))
-#define GPIO_SIG105_IN_SEL_M  (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S)
-#define GPIO_SIG105_IN_SEL_V  0x00000001U
-#define GPIO_SIG105_IN_SEL_S  7
-
-/** GPIO_FUNC106_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
-/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC106_IN_SEL    0x0000003FU
-#define GPIO_FUNC106_IN_SEL_M  (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S)
-#define GPIO_FUNC106_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC106_IN_SEL_S  0
-/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC106_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC106_IN_INV_SEL_M  (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S)
-#define GPIO_FUNC106_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC106_IN_INV_SEL_S  6
-/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG106_IN_SEL    (BIT(7))
-#define GPIO_SIG106_IN_SEL_M  (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S)
-#define GPIO_SIG106_IN_SEL_V  0x00000001U
-#define GPIO_SIG106_IN_SEL_S  7
-
-/** GPIO_FUNC107_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
-/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC107_IN_SEL    0x0000003FU
-#define GPIO_FUNC107_IN_SEL_M  (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S)
-#define GPIO_FUNC107_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC107_IN_SEL_S  0
-/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC107_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC107_IN_INV_SEL_M  (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S)
-#define GPIO_FUNC107_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC107_IN_INV_SEL_S  6
-/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG107_IN_SEL    (BIT(7))
-#define GPIO_SIG107_IN_SEL_M  (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S)
-#define GPIO_SIG107_IN_SEL_V  0x00000001U
-#define GPIO_SIG107_IN_SEL_S  7
-
-/** GPIO_FUNC108_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
-/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC108_IN_SEL    0x0000003FU
-#define GPIO_FUNC108_IN_SEL_M  (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S)
-#define GPIO_FUNC108_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC108_IN_SEL_S  0
-/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC108_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC108_IN_INV_SEL_M  (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S)
-#define GPIO_FUNC108_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC108_IN_INV_SEL_S  6
-/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG108_IN_SEL    (BIT(7))
-#define GPIO_SIG108_IN_SEL_M  (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S)
-#define GPIO_SIG108_IN_SEL_V  0x00000001U
-#define GPIO_SIG108_IN_SEL_S  7
-
-/** GPIO_FUNC109_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c)
-/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC109_IN_SEL    0x0000003FU
-#define GPIO_FUNC109_IN_SEL_M  (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S)
-#define GPIO_FUNC109_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC109_IN_SEL_S  0
-/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC109_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC109_IN_INV_SEL_M  (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S)
-#define GPIO_FUNC109_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC109_IN_INV_SEL_S  6
-/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG109_IN_SEL    (BIT(7))
-#define GPIO_SIG109_IN_SEL_M  (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S)
-#define GPIO_SIG109_IN_SEL_V  0x00000001U
-#define GPIO_SIG109_IN_SEL_S  7
-
-/** GPIO_FUNC110_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310)
-/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC110_IN_SEL    0x0000003FU
-#define GPIO_FUNC110_IN_SEL_M  (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S)
-#define GPIO_FUNC110_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC110_IN_SEL_S  0
-/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC110_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC110_IN_INV_SEL_M  (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S)
-#define GPIO_FUNC110_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC110_IN_INV_SEL_S  6
-/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG110_IN_SEL    (BIT(7))
-#define GPIO_SIG110_IN_SEL_M  (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S)
-#define GPIO_SIG110_IN_SEL_V  0x00000001U
-#define GPIO_SIG110_IN_SEL_S  7
-
-/** GPIO_FUNC111_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314)
-/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC111_IN_SEL    0x0000003FU
-#define GPIO_FUNC111_IN_SEL_M  (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S)
-#define GPIO_FUNC111_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC111_IN_SEL_S  0
-/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC111_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC111_IN_INV_SEL_M  (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S)
-#define GPIO_FUNC111_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC111_IN_INV_SEL_S  6
-/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG111_IN_SEL    (BIT(7))
-#define GPIO_SIG111_IN_SEL_M  (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S)
-#define GPIO_SIG111_IN_SEL_V  0x00000001U
-#define GPIO_SIG111_IN_SEL_S  7
-
-/** GPIO_FUNC112_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318)
-/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC112_IN_SEL    0x0000003FU
-#define GPIO_FUNC112_IN_SEL_M  (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S)
-#define GPIO_FUNC112_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC112_IN_SEL_S  0
-/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC112_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC112_IN_INV_SEL_M  (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S)
-#define GPIO_FUNC112_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC112_IN_INV_SEL_S  6
-/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG112_IN_SEL    (BIT(7))
-#define GPIO_SIG112_IN_SEL_M  (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S)
-#define GPIO_SIG112_IN_SEL_V  0x00000001U
-#define GPIO_SIG112_IN_SEL_S  7
-
-/** GPIO_FUNC113_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c)
-/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC113_IN_SEL    0x0000003FU
-#define GPIO_FUNC113_IN_SEL_M  (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S)
-#define GPIO_FUNC113_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC113_IN_SEL_S  0
-/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC113_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC113_IN_INV_SEL_M  (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S)
-#define GPIO_FUNC113_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC113_IN_INV_SEL_S  6
-/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG113_IN_SEL    (BIT(7))
-#define GPIO_SIG113_IN_SEL_M  (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S)
-#define GPIO_SIG113_IN_SEL_V  0x00000001U
-#define GPIO_SIG113_IN_SEL_S  7
-
-/** GPIO_FUNC114_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320)
-/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC114_IN_SEL    0x0000003FU
-#define GPIO_FUNC114_IN_SEL_M  (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S)
-#define GPIO_FUNC114_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC114_IN_SEL_S  0
-/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC114_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC114_IN_INV_SEL_M  (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S)
-#define GPIO_FUNC114_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC114_IN_INV_SEL_S  6
-/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG114_IN_SEL    (BIT(7))
-#define GPIO_SIG114_IN_SEL_M  (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S)
-#define GPIO_SIG114_IN_SEL_V  0x00000001U
-#define GPIO_SIG114_IN_SEL_S  7
-
-/** GPIO_FUNC117_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c)
-/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC117_IN_SEL    0x0000003FU
-#define GPIO_FUNC117_IN_SEL_M  (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S)
-#define GPIO_FUNC117_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC117_IN_SEL_S  0
-/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC117_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC117_IN_INV_SEL_M  (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S)
-#define GPIO_FUNC117_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC117_IN_INV_SEL_S  6
-/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG117_IN_SEL    (BIT(7))
-#define GPIO_SIG117_IN_SEL_M  (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S)
-#define GPIO_SIG117_IN_SEL_V  0x00000001U
-#define GPIO_SIG117_IN_SEL_S  7
-
-/** GPIO_FUNC118_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
-/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC118_IN_SEL    0x0000003FU
-#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
-#define GPIO_FUNC118_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC118_IN_SEL_S  0
-/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
-#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC118_IN_INV_SEL_S  6
-/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG118_IN_SEL    (BIT(7))
-#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
-#define GPIO_SIG118_IN_SEL_V  0x00000001U
-#define GPIO_SIG118_IN_SEL_S  7
-
-/** GPIO_FUNC126_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
-/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC126_IN_SEL    0x0000003FU
-#define GPIO_FUNC126_IN_SEL_M  (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S)
-#define GPIO_FUNC126_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC126_IN_SEL_S  0
-/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC126_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC126_IN_INV_SEL_M  (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S)
-#define GPIO_FUNC126_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC126_IN_INV_SEL_S  6
-/** GPIO_SIG126_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG126_IN_SEL    (BIT(7))
-#define GPIO_SIG126_IN_SEL_M  (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S)
-#define GPIO_SIG126_IN_SEL_V  0x00000001U
-#define GPIO_SIG126_IN_SEL_S  7
-
-/** GPIO_FUNC127_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354)
-/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC127_IN_SEL    0x0000003FU
-#define GPIO_FUNC127_IN_SEL_M  (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S)
-#define GPIO_FUNC127_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC127_IN_SEL_S  0
-/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC127_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC127_IN_INV_SEL_M  (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S)
-#define GPIO_FUNC127_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC127_IN_INV_SEL_S  6
-/** GPIO_SIG127_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG127_IN_SEL    (BIT(7))
-#define GPIO_SIG127_IN_SEL_M  (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S)
-#define GPIO_SIG127_IN_SEL_V  0x00000001U
-#define GPIO_SIG127_IN_SEL_S  7
-
-/** GPIO_FUNC128_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358)
-/** GPIO_FUNC128_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC128_IN_SEL    0x0000003FU
-#define GPIO_FUNC128_IN_SEL_M  (GPIO_FUNC128_IN_SEL_V << GPIO_FUNC128_IN_SEL_S)
-#define GPIO_FUNC128_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC128_IN_SEL_S  0
-/** GPIO_FUNC128_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC128_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC128_IN_INV_SEL_M  (GPIO_FUNC128_IN_INV_SEL_V << GPIO_FUNC128_IN_INV_SEL_S)
-#define GPIO_FUNC128_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC128_IN_INV_SEL_S  6
-/** GPIO_SIG128_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG128_IN_SEL    (BIT(7))
-#define GPIO_SIG128_IN_SEL_M  (GPIO_SIG128_IN_SEL_V << GPIO_SIG128_IN_SEL_S)
-#define GPIO_SIG128_IN_SEL_V  0x00000001U
-#define GPIO_SIG128_IN_SEL_S  7
-
-/** GPIO_FUNC129_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c)
-/** GPIO_FUNC129_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC129_IN_SEL    0x0000003FU
-#define GPIO_FUNC129_IN_SEL_M  (GPIO_FUNC129_IN_SEL_V << GPIO_FUNC129_IN_SEL_S)
-#define GPIO_FUNC129_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC129_IN_SEL_S  0
-/** GPIO_FUNC129_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC129_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC129_IN_INV_SEL_M  (GPIO_FUNC129_IN_INV_SEL_V << GPIO_FUNC129_IN_INV_SEL_S)
-#define GPIO_FUNC129_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC129_IN_INV_SEL_S  6
-/** GPIO_SIG129_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG129_IN_SEL    (BIT(7))
-#define GPIO_SIG129_IN_SEL_M  (GPIO_SIG129_IN_SEL_V << GPIO_SIG129_IN_SEL_S)
-#define GPIO_SIG129_IN_SEL_V  0x00000001U
-#define GPIO_SIG129_IN_SEL_S  7
-
-/** GPIO_FUNC130_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360)
-/** GPIO_FUNC130_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC130_IN_SEL    0x0000003FU
-#define GPIO_FUNC130_IN_SEL_M  (GPIO_FUNC130_IN_SEL_V << GPIO_FUNC130_IN_SEL_S)
-#define GPIO_FUNC130_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC130_IN_SEL_S  0
-/** GPIO_FUNC130_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC130_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC130_IN_INV_SEL_M  (GPIO_FUNC130_IN_INV_SEL_V << GPIO_FUNC130_IN_INV_SEL_S)
-#define GPIO_FUNC130_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC130_IN_INV_SEL_S  6
-/** GPIO_SIG130_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG130_IN_SEL    (BIT(7))
-#define GPIO_SIG130_IN_SEL_M  (GPIO_SIG130_IN_SEL_V << GPIO_SIG130_IN_SEL_S)
-#define GPIO_SIG130_IN_SEL_V  0x00000001U
-#define GPIO_SIG130_IN_SEL_S  7
-
-/** GPIO_FUNC131_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x364)
-/** GPIO_FUNC131_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC131_IN_SEL    0x0000003FU
-#define GPIO_FUNC131_IN_SEL_M  (GPIO_FUNC131_IN_SEL_V << GPIO_FUNC131_IN_SEL_S)
-#define GPIO_FUNC131_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC131_IN_SEL_S  0
-/** GPIO_FUNC131_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC131_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC131_IN_INV_SEL_M  (GPIO_FUNC131_IN_INV_SEL_V << GPIO_FUNC131_IN_INV_SEL_S)
-#define GPIO_FUNC131_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC131_IN_INV_SEL_S  6
-/** GPIO_SIG131_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG131_IN_SEL    (BIT(7))
-#define GPIO_SIG131_IN_SEL_M  (GPIO_SIG131_IN_SEL_V << GPIO_SIG131_IN_SEL_S)
-#define GPIO_SIG131_IN_SEL_V  0x00000001U
-#define GPIO_SIG131_IN_SEL_S  7
-
-/** GPIO_FUNC132_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368)
-/** GPIO_FUNC132_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC132_IN_SEL    0x0000003FU
-#define GPIO_FUNC132_IN_SEL_M  (GPIO_FUNC132_IN_SEL_V << GPIO_FUNC132_IN_SEL_S)
-#define GPIO_FUNC132_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC132_IN_SEL_S  0
-/** GPIO_FUNC132_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC132_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC132_IN_INV_SEL_M  (GPIO_FUNC132_IN_INV_SEL_V << GPIO_FUNC132_IN_INV_SEL_S)
-#define GPIO_FUNC132_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC132_IN_INV_SEL_S  6
-/** GPIO_SIG132_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG132_IN_SEL    (BIT(7))
-#define GPIO_SIG132_IN_SEL_M  (GPIO_SIG132_IN_SEL_V << GPIO_SIG132_IN_SEL_S)
-#define GPIO_SIG132_IN_SEL_V  0x00000001U
-#define GPIO_SIG132_IN_SEL_S  7
-
-/** GPIO_FUNC133_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c)
-/** GPIO_FUNC133_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC133_IN_SEL    0x0000003FU
-#define GPIO_FUNC133_IN_SEL_M  (GPIO_FUNC133_IN_SEL_V << GPIO_FUNC133_IN_SEL_S)
-#define GPIO_FUNC133_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC133_IN_SEL_S  0
-/** GPIO_FUNC133_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC133_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC133_IN_INV_SEL_M  (GPIO_FUNC133_IN_INV_SEL_V << GPIO_FUNC133_IN_INV_SEL_S)
-#define GPIO_FUNC133_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC133_IN_INV_SEL_S  6
-/** GPIO_SIG133_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG133_IN_SEL    (BIT(7))
-#define GPIO_SIG133_IN_SEL_M  (GPIO_SIG133_IN_SEL_V << GPIO_SIG133_IN_SEL_S)
-#define GPIO_SIG133_IN_SEL_V  0x00000001U
-#define GPIO_SIG133_IN_SEL_S  7
-
-/** GPIO_FUNC134_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370)
-/** GPIO_FUNC134_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC134_IN_SEL    0x0000003FU
-#define GPIO_FUNC134_IN_SEL_M  (GPIO_FUNC134_IN_SEL_V << GPIO_FUNC134_IN_SEL_S)
-#define GPIO_FUNC134_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC134_IN_SEL_S  0
-/** GPIO_FUNC134_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC134_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC134_IN_INV_SEL_M  (GPIO_FUNC134_IN_INV_SEL_V << GPIO_FUNC134_IN_INV_SEL_S)
-#define GPIO_FUNC134_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC134_IN_INV_SEL_S  6
-/** GPIO_SIG134_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG134_IN_SEL    (BIT(7))
-#define GPIO_SIG134_IN_SEL_M  (GPIO_SIG134_IN_SEL_V << GPIO_SIG134_IN_SEL_S)
-#define GPIO_SIG134_IN_SEL_V  0x00000001U
-#define GPIO_SIG134_IN_SEL_S  7
-
-/** GPIO_FUNC135_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x374)
-/** GPIO_FUNC135_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC135_IN_SEL    0x0000003FU
-#define GPIO_FUNC135_IN_SEL_M  (GPIO_FUNC135_IN_SEL_V << GPIO_FUNC135_IN_SEL_S)
-#define GPIO_FUNC135_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC135_IN_SEL_S  0
-/** GPIO_FUNC135_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC135_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC135_IN_INV_SEL_M  (GPIO_FUNC135_IN_INV_SEL_V << GPIO_FUNC135_IN_INV_SEL_S)
-#define GPIO_FUNC135_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC135_IN_INV_SEL_S  6
-/** GPIO_SIG135_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG135_IN_SEL    (BIT(7))
-#define GPIO_SIG135_IN_SEL_M  (GPIO_SIG135_IN_SEL_V << GPIO_SIG135_IN_SEL_S)
-#define GPIO_SIG135_IN_SEL_V  0x00000001U
-#define GPIO_SIG135_IN_SEL_S  7
-
-/** GPIO_FUNC136_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378)
-/** GPIO_FUNC136_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC136_IN_SEL    0x0000003FU
-#define GPIO_FUNC136_IN_SEL_M  (GPIO_FUNC136_IN_SEL_V << GPIO_FUNC136_IN_SEL_S)
-#define GPIO_FUNC136_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC136_IN_SEL_S  0
-/** GPIO_FUNC136_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC136_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC136_IN_INV_SEL_M  (GPIO_FUNC136_IN_INV_SEL_V << GPIO_FUNC136_IN_INV_SEL_S)
-#define GPIO_FUNC136_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC136_IN_INV_SEL_S  6
-/** GPIO_SIG136_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG136_IN_SEL    (BIT(7))
-#define GPIO_SIG136_IN_SEL_M  (GPIO_SIG136_IN_SEL_V << GPIO_SIG136_IN_SEL_S)
-#define GPIO_SIG136_IN_SEL_V  0x00000001U
-#define GPIO_SIG136_IN_SEL_S  7
-
-/** GPIO_FUNC137_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c)
-/** GPIO_FUNC137_IN_SEL : R/W; bitpos: [5:0]; default: 63;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC137_IN_SEL    0x0000003FU
-#define GPIO_FUNC137_IN_SEL_M  (GPIO_FUNC137_IN_SEL_V << GPIO_FUNC137_IN_SEL_S)
-#define GPIO_FUNC137_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC137_IN_SEL_S  0
-/** GPIO_FUNC137_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC137_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC137_IN_INV_SEL_M  (GPIO_FUNC137_IN_INV_SEL_V << GPIO_FUNC137_IN_INV_SEL_S)
-#define GPIO_FUNC137_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC137_IN_INV_SEL_S  6
-/** GPIO_SIG137_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG137_IN_SEL    (BIT(7))
-#define GPIO_SIG137_IN_SEL_M  (GPIO_SIG137_IN_SEL_V << GPIO_SIG137_IN_SEL_S)
-#define GPIO_SIG137_IN_SEL_V  0x00000001U
-#define GPIO_SIG137_IN_SEL_S  7
-
-/** GPIO_FUNC138_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380)
-/** GPIO_FUNC138_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC138_IN_SEL    0x0000003FU
-#define GPIO_FUNC138_IN_SEL_M  (GPIO_FUNC138_IN_SEL_V << GPIO_FUNC138_IN_SEL_S)
-#define GPIO_FUNC138_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC138_IN_SEL_S  0
-/** GPIO_FUNC138_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC138_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC138_IN_INV_SEL_M  (GPIO_FUNC138_IN_INV_SEL_V << GPIO_FUNC138_IN_INV_SEL_S)
-#define GPIO_FUNC138_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC138_IN_INV_SEL_S  6
-/** GPIO_SIG138_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG138_IN_SEL    (BIT(7))
-#define GPIO_SIG138_IN_SEL_M  (GPIO_SIG138_IN_SEL_V << GPIO_SIG138_IN_SEL_S)
-#define GPIO_SIG138_IN_SEL_V  0x00000001U
-#define GPIO_SIG138_IN_SEL_S  7
-
-/** GPIO_FUNC139_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x384)
-/** GPIO_FUNC139_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC139_IN_SEL    0x0000003FU
-#define GPIO_FUNC139_IN_SEL_M  (GPIO_FUNC139_IN_SEL_V << GPIO_FUNC139_IN_SEL_S)
-#define GPIO_FUNC139_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC139_IN_SEL_S  0
-/** GPIO_FUNC139_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC139_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC139_IN_INV_SEL_M  (GPIO_FUNC139_IN_INV_SEL_V << GPIO_FUNC139_IN_INV_SEL_S)
-#define GPIO_FUNC139_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC139_IN_INV_SEL_S  6
-/** GPIO_SIG139_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG139_IN_SEL    (BIT(7))
-#define GPIO_SIG139_IN_SEL_M  (GPIO_SIG139_IN_SEL_V << GPIO_SIG139_IN_SEL_S)
-#define GPIO_SIG139_IN_SEL_V  0x00000001U
-#define GPIO_SIG139_IN_SEL_S  7
-
-/** GPIO_FUNC140_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388)
-/** GPIO_FUNC140_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC140_IN_SEL    0x0000003FU
-#define GPIO_FUNC140_IN_SEL_M  (GPIO_FUNC140_IN_SEL_V << GPIO_FUNC140_IN_SEL_S)
-#define GPIO_FUNC140_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC140_IN_SEL_S  0
-/** GPIO_FUNC140_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC140_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC140_IN_INV_SEL_M  (GPIO_FUNC140_IN_INV_SEL_V << GPIO_FUNC140_IN_INV_SEL_S)
-#define GPIO_FUNC140_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC140_IN_INV_SEL_S  6
-/** GPIO_SIG140_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG140_IN_SEL    (BIT(7))
-#define GPIO_SIG140_IN_SEL_M  (GPIO_SIG140_IN_SEL_V << GPIO_SIG140_IN_SEL_S)
-#define GPIO_SIG140_IN_SEL_V  0x00000001U
-#define GPIO_SIG140_IN_SEL_S  7
-
-/** GPIO_FUNC141_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c)
-/** GPIO_FUNC141_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC141_IN_SEL    0x0000003FU
-#define GPIO_FUNC141_IN_SEL_M  (GPIO_FUNC141_IN_SEL_V << GPIO_FUNC141_IN_SEL_S)
-#define GPIO_FUNC141_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC141_IN_SEL_S  0
-/** GPIO_FUNC141_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC141_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC141_IN_INV_SEL_M  (GPIO_FUNC141_IN_INV_SEL_V << GPIO_FUNC141_IN_INV_SEL_S)
-#define GPIO_FUNC141_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC141_IN_INV_SEL_S  6
-/** GPIO_SIG141_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG141_IN_SEL    (BIT(7))
-#define GPIO_SIG141_IN_SEL_M  (GPIO_SIG141_IN_SEL_V << GPIO_SIG141_IN_SEL_S)
-#define GPIO_SIG141_IN_SEL_V  0x00000001U
-#define GPIO_SIG141_IN_SEL_S  7
-
-/** GPIO_FUNC142_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390)
-/** GPIO_FUNC142_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC142_IN_SEL    0x0000003FU
-#define GPIO_FUNC142_IN_SEL_M  (GPIO_FUNC142_IN_SEL_V << GPIO_FUNC142_IN_SEL_S)
-#define GPIO_FUNC142_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC142_IN_SEL_S  0
-/** GPIO_FUNC142_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC142_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC142_IN_INV_SEL_M  (GPIO_FUNC142_IN_INV_SEL_V << GPIO_FUNC142_IN_INV_SEL_S)
-#define GPIO_FUNC142_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC142_IN_INV_SEL_S  6
-/** GPIO_SIG142_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG142_IN_SEL    (BIT(7))
-#define GPIO_SIG142_IN_SEL_M  (GPIO_SIG142_IN_SEL_V << GPIO_SIG142_IN_SEL_S)
-#define GPIO_SIG142_IN_SEL_V  0x00000001U
-#define GPIO_SIG142_IN_SEL_S  7
-
-/** GPIO_FUNC143_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394)
-/** GPIO_FUNC143_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC143_IN_SEL    0x0000003FU
-#define GPIO_FUNC143_IN_SEL_M  (GPIO_FUNC143_IN_SEL_V << GPIO_FUNC143_IN_SEL_S)
-#define GPIO_FUNC143_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC143_IN_SEL_S  0
-/** GPIO_FUNC143_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC143_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC143_IN_INV_SEL_M  (GPIO_FUNC143_IN_INV_SEL_V << GPIO_FUNC143_IN_INV_SEL_S)
-#define GPIO_FUNC143_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC143_IN_INV_SEL_S  6
-/** GPIO_SIG143_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG143_IN_SEL    (BIT(7))
-#define GPIO_SIG143_IN_SEL_M  (GPIO_SIG143_IN_SEL_V << GPIO_SIG143_IN_SEL_S)
-#define GPIO_SIG143_IN_SEL_V  0x00000001U
-#define GPIO_SIG143_IN_SEL_S  7
-
-/** GPIO_FUNC144_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398)
-/** GPIO_FUNC144_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC144_IN_SEL    0x0000003FU
-#define GPIO_FUNC144_IN_SEL_M  (GPIO_FUNC144_IN_SEL_V << GPIO_FUNC144_IN_SEL_S)
-#define GPIO_FUNC144_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC144_IN_SEL_S  0
-/** GPIO_FUNC144_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC144_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC144_IN_INV_SEL_M  (GPIO_FUNC144_IN_INV_SEL_V << GPIO_FUNC144_IN_INV_SEL_S)
-#define GPIO_FUNC144_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC144_IN_INV_SEL_S  6
-/** GPIO_SIG144_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG144_IN_SEL    (BIT(7))
-#define GPIO_SIG144_IN_SEL_M  (GPIO_SIG144_IN_SEL_V << GPIO_SIG144_IN_SEL_S)
-#define GPIO_SIG144_IN_SEL_V  0x00000001U
-#define GPIO_SIG144_IN_SEL_S  7
-
-/** GPIO_FUNC145_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39c)
-/** GPIO_FUNC145_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC145_IN_SEL    0x0000003FU
-#define GPIO_FUNC145_IN_SEL_M  (GPIO_FUNC145_IN_SEL_V << GPIO_FUNC145_IN_SEL_S)
-#define GPIO_FUNC145_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC145_IN_SEL_S  0
-/** GPIO_FUNC145_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC145_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC145_IN_INV_SEL_M  (GPIO_FUNC145_IN_INV_SEL_V << GPIO_FUNC145_IN_INV_SEL_S)
-#define GPIO_FUNC145_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC145_IN_INV_SEL_S  6
-/** GPIO_SIG145_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG145_IN_SEL    (BIT(7))
-#define GPIO_SIG145_IN_SEL_M  (GPIO_SIG145_IN_SEL_V << GPIO_SIG145_IN_SEL_S)
-#define GPIO_SIG145_IN_SEL_V  0x00000001U
-#define GPIO_SIG145_IN_SEL_S  7
-
-/** GPIO_FUNC146_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0)
-/** GPIO_FUNC146_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC146_IN_SEL    0x0000003FU
-#define GPIO_FUNC146_IN_SEL_M  (GPIO_FUNC146_IN_SEL_V << GPIO_FUNC146_IN_SEL_S)
-#define GPIO_FUNC146_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC146_IN_SEL_S  0
-/** GPIO_FUNC146_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC146_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC146_IN_INV_SEL_M  (GPIO_FUNC146_IN_INV_SEL_V << GPIO_FUNC146_IN_INV_SEL_S)
-#define GPIO_FUNC146_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC146_IN_INV_SEL_S  6
-/** GPIO_SIG146_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG146_IN_SEL    (BIT(7))
-#define GPIO_SIG146_IN_SEL_M  (GPIO_SIG146_IN_SEL_V << GPIO_SIG146_IN_SEL_S)
-#define GPIO_SIG146_IN_SEL_V  0x00000001U
-#define GPIO_SIG146_IN_SEL_S  7
-
-/** GPIO_FUNC147_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4)
-/** GPIO_FUNC147_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC147_IN_SEL    0x0000003FU
-#define GPIO_FUNC147_IN_SEL_M  (GPIO_FUNC147_IN_SEL_V << GPIO_FUNC147_IN_SEL_S)
-#define GPIO_FUNC147_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC147_IN_SEL_S  0
-/** GPIO_FUNC147_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC147_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC147_IN_INV_SEL_M  (GPIO_FUNC147_IN_INV_SEL_V << GPIO_FUNC147_IN_INV_SEL_S)
-#define GPIO_FUNC147_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC147_IN_INV_SEL_S  6
-/** GPIO_SIG147_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG147_IN_SEL    (BIT(7))
-#define GPIO_SIG147_IN_SEL_M  (GPIO_SIG147_IN_SEL_V << GPIO_SIG147_IN_SEL_S)
-#define GPIO_SIG147_IN_SEL_V  0x00000001U
-#define GPIO_SIG147_IN_SEL_S  7
-
-/** GPIO_FUNC148_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8)
-/** GPIO_FUNC148_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC148_IN_SEL    0x0000003FU
-#define GPIO_FUNC148_IN_SEL_M  (GPIO_FUNC148_IN_SEL_V << GPIO_FUNC148_IN_SEL_S)
-#define GPIO_FUNC148_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC148_IN_SEL_S  0
-/** GPIO_FUNC148_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC148_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC148_IN_INV_SEL_M  (GPIO_FUNC148_IN_INV_SEL_V << GPIO_FUNC148_IN_INV_SEL_S)
-#define GPIO_FUNC148_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC148_IN_INV_SEL_S  6
-/** GPIO_SIG148_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG148_IN_SEL    (BIT(7))
-#define GPIO_SIG148_IN_SEL_M  (GPIO_SIG148_IN_SEL_V << GPIO_SIG148_IN_SEL_S)
-#define GPIO_SIG148_IN_SEL_V  0x00000001U
-#define GPIO_SIG148_IN_SEL_S  7
-
-/** GPIO_FUNC149_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ac)
-/** GPIO_FUNC149_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC149_IN_SEL    0x0000003FU
-#define GPIO_FUNC149_IN_SEL_M  (GPIO_FUNC149_IN_SEL_V << GPIO_FUNC149_IN_SEL_S)
-#define GPIO_FUNC149_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC149_IN_SEL_S  0
-/** GPIO_FUNC149_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC149_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC149_IN_INV_SEL_M  (GPIO_FUNC149_IN_INV_SEL_V << GPIO_FUNC149_IN_INV_SEL_S)
-#define GPIO_FUNC149_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC149_IN_INV_SEL_S  6
-/** GPIO_SIG149_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG149_IN_SEL    (BIT(7))
-#define GPIO_SIG149_IN_SEL_M  (GPIO_SIG149_IN_SEL_V << GPIO_SIG149_IN_SEL_S)
-#define GPIO_SIG149_IN_SEL_V  0x00000001U
-#define GPIO_SIG149_IN_SEL_S  7
-
-/** GPIO_FUNC150_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0)
-/** GPIO_FUNC150_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC150_IN_SEL    0x0000003FU
-#define GPIO_FUNC150_IN_SEL_M  (GPIO_FUNC150_IN_SEL_V << GPIO_FUNC150_IN_SEL_S)
-#define GPIO_FUNC150_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC150_IN_SEL_S  0
-/** GPIO_FUNC150_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC150_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC150_IN_INV_SEL_M  (GPIO_FUNC150_IN_INV_SEL_V << GPIO_FUNC150_IN_INV_SEL_S)
-#define GPIO_FUNC150_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC150_IN_INV_SEL_S  6
-/** GPIO_SIG150_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG150_IN_SEL    (BIT(7))
-#define GPIO_SIG150_IN_SEL_M  (GPIO_SIG150_IN_SEL_V << GPIO_SIG150_IN_SEL_S)
-#define GPIO_SIG150_IN_SEL_V  0x00000001U
-#define GPIO_SIG150_IN_SEL_S  7
-
-/** GPIO_FUNC151_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4)
-/** GPIO_FUNC151_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC151_IN_SEL    0x0000003FU
-#define GPIO_FUNC151_IN_SEL_M  (GPIO_FUNC151_IN_SEL_V << GPIO_FUNC151_IN_SEL_S)
-#define GPIO_FUNC151_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC151_IN_SEL_S  0
-/** GPIO_FUNC151_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC151_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC151_IN_INV_SEL_M  (GPIO_FUNC151_IN_INV_SEL_V << GPIO_FUNC151_IN_INV_SEL_S)
-#define GPIO_FUNC151_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC151_IN_INV_SEL_S  6
-/** GPIO_SIG151_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG151_IN_SEL    (BIT(7))
-#define GPIO_SIG151_IN_SEL_M  (GPIO_SIG151_IN_SEL_V << GPIO_SIG151_IN_SEL_S)
-#define GPIO_SIG151_IN_SEL_V  0x00000001U
-#define GPIO_SIG151_IN_SEL_S  7
-
-/** GPIO_FUNC152_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8)
-/** GPIO_FUNC152_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC152_IN_SEL    0x0000003FU
-#define GPIO_FUNC152_IN_SEL_M  (GPIO_FUNC152_IN_SEL_V << GPIO_FUNC152_IN_SEL_S)
-#define GPIO_FUNC152_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC152_IN_SEL_S  0
-/** GPIO_FUNC152_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC152_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC152_IN_INV_SEL_M  (GPIO_FUNC152_IN_INV_SEL_V << GPIO_FUNC152_IN_INV_SEL_S)
-#define GPIO_FUNC152_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC152_IN_INV_SEL_S  6
-/** GPIO_SIG152_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG152_IN_SEL    (BIT(7))
-#define GPIO_SIG152_IN_SEL_M  (GPIO_SIG152_IN_SEL_V << GPIO_SIG152_IN_SEL_S)
-#define GPIO_SIG152_IN_SEL_V  0x00000001U
-#define GPIO_SIG152_IN_SEL_S  7
-
-/** GPIO_FUNC153_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc)
-/** GPIO_FUNC153_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC153_IN_SEL    0x0000003FU
-#define GPIO_FUNC153_IN_SEL_M  (GPIO_FUNC153_IN_SEL_V << GPIO_FUNC153_IN_SEL_S)
-#define GPIO_FUNC153_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC153_IN_SEL_S  0
-/** GPIO_FUNC153_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC153_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC153_IN_INV_SEL_M  (GPIO_FUNC153_IN_INV_SEL_V << GPIO_FUNC153_IN_INV_SEL_S)
-#define GPIO_FUNC153_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC153_IN_INV_SEL_S  6
-/** GPIO_SIG153_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG153_IN_SEL    (BIT(7))
-#define GPIO_SIG153_IN_SEL_M  (GPIO_SIG153_IN_SEL_V << GPIO_SIG153_IN_SEL_S)
-#define GPIO_SIG153_IN_SEL_V  0x00000001U
-#define GPIO_SIG153_IN_SEL_S  7
-
-/** GPIO_FUNC154_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0)
-/** GPIO_FUNC154_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC154_IN_SEL    0x0000003FU
-#define GPIO_FUNC154_IN_SEL_M  (GPIO_FUNC154_IN_SEL_V << GPIO_FUNC154_IN_SEL_S)
-#define GPIO_FUNC154_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC154_IN_SEL_S  0
-/** GPIO_FUNC154_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC154_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC154_IN_INV_SEL_M  (GPIO_FUNC154_IN_INV_SEL_V << GPIO_FUNC154_IN_INV_SEL_S)
-#define GPIO_FUNC154_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC154_IN_INV_SEL_S  6
-/** GPIO_SIG154_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG154_IN_SEL    (BIT(7))
-#define GPIO_SIG154_IN_SEL_M  (GPIO_SIG154_IN_SEL_V << GPIO_SIG154_IN_SEL_S)
-#define GPIO_SIG154_IN_SEL_V  0x00000001U
-#define GPIO_SIG154_IN_SEL_S  7
-
-/** GPIO_FUNC155_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4)
-/** GPIO_FUNC155_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC155_IN_SEL    0x0000003FU
-#define GPIO_FUNC155_IN_SEL_M  (GPIO_FUNC155_IN_SEL_V << GPIO_FUNC155_IN_SEL_S)
-#define GPIO_FUNC155_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC155_IN_SEL_S  0
-/** GPIO_FUNC155_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC155_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC155_IN_INV_SEL_M  (GPIO_FUNC155_IN_INV_SEL_V << GPIO_FUNC155_IN_INV_SEL_S)
-#define GPIO_FUNC155_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC155_IN_INV_SEL_S  6
-/** GPIO_SIG155_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG155_IN_SEL    (BIT(7))
-#define GPIO_SIG155_IN_SEL_M  (GPIO_SIG155_IN_SEL_V << GPIO_SIG155_IN_SEL_S)
-#define GPIO_SIG155_IN_SEL_V  0x00000001U
-#define GPIO_SIG155_IN_SEL_S  7
-
-/** GPIO_FUNC156_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8)
-/** GPIO_FUNC156_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC156_IN_SEL    0x0000003FU
-#define GPIO_FUNC156_IN_SEL_M  (GPIO_FUNC156_IN_SEL_V << GPIO_FUNC156_IN_SEL_S)
-#define GPIO_FUNC156_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC156_IN_SEL_S  0
-/** GPIO_FUNC156_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC156_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC156_IN_INV_SEL_M  (GPIO_FUNC156_IN_INV_SEL_V << GPIO_FUNC156_IN_INV_SEL_S)
-#define GPIO_FUNC156_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC156_IN_INV_SEL_S  6
-/** GPIO_SIG156_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG156_IN_SEL    (BIT(7))
-#define GPIO_SIG156_IN_SEL_M  (GPIO_SIG156_IN_SEL_V << GPIO_SIG156_IN_SEL_S)
-#define GPIO_SIG156_IN_SEL_V  0x00000001U
-#define GPIO_SIG156_IN_SEL_S  7
-
-/** GPIO_FUNC158_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0)
-/** GPIO_FUNC158_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC158_IN_SEL    0x0000003FU
-#define GPIO_FUNC158_IN_SEL_M  (GPIO_FUNC158_IN_SEL_V << GPIO_FUNC158_IN_SEL_S)
-#define GPIO_FUNC158_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC158_IN_SEL_S  0
-/** GPIO_FUNC158_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC158_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC158_IN_INV_SEL_M  (GPIO_FUNC158_IN_INV_SEL_V << GPIO_FUNC158_IN_INV_SEL_S)
-#define GPIO_FUNC158_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC158_IN_INV_SEL_S  6
-/** GPIO_SIG158_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG158_IN_SEL    (BIT(7))
-#define GPIO_SIG158_IN_SEL_M  (GPIO_SIG158_IN_SEL_V << GPIO_SIG158_IN_SEL_S)
-#define GPIO_SIG158_IN_SEL_V  0x00000001U
-#define GPIO_SIG158_IN_SEL_S  7
-
-/** GPIO_FUNC159_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4)
-/** GPIO_FUNC159_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC159_IN_SEL    0x0000003FU
-#define GPIO_FUNC159_IN_SEL_M  (GPIO_FUNC159_IN_SEL_V << GPIO_FUNC159_IN_SEL_S)
-#define GPIO_FUNC159_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC159_IN_SEL_S  0
-/** GPIO_FUNC159_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC159_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC159_IN_INV_SEL_M  (GPIO_FUNC159_IN_INV_SEL_V << GPIO_FUNC159_IN_INV_SEL_S)
-#define GPIO_FUNC159_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC159_IN_INV_SEL_S  6
-/** GPIO_SIG159_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG159_IN_SEL    (BIT(7))
-#define GPIO_SIG159_IN_SEL_M  (GPIO_SIG159_IN_SEL_V << GPIO_SIG159_IN_SEL_S)
-#define GPIO_SIG159_IN_SEL_V  0x00000001U
-#define GPIO_SIG159_IN_SEL_S  7
-
-/** GPIO_FUNC160_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8)
-/** GPIO_FUNC160_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC160_IN_SEL    0x0000003FU
-#define GPIO_FUNC160_IN_SEL_M  (GPIO_FUNC160_IN_SEL_V << GPIO_FUNC160_IN_SEL_S)
-#define GPIO_FUNC160_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC160_IN_SEL_S  0
-/** GPIO_FUNC160_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC160_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC160_IN_INV_SEL_M  (GPIO_FUNC160_IN_INV_SEL_V << GPIO_FUNC160_IN_INV_SEL_S)
-#define GPIO_FUNC160_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC160_IN_INV_SEL_S  6
-/** GPIO_SIG160_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG160_IN_SEL    (BIT(7))
-#define GPIO_SIG160_IN_SEL_M  (GPIO_SIG160_IN_SEL_V << GPIO_SIG160_IN_SEL_S)
-#define GPIO_SIG160_IN_SEL_V  0x00000001U
-#define GPIO_SIG160_IN_SEL_S  7
-
-/** GPIO_FUNC161_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc)
-/** GPIO_FUNC161_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC161_IN_SEL    0x0000003FU
-#define GPIO_FUNC161_IN_SEL_M  (GPIO_FUNC161_IN_SEL_V << GPIO_FUNC161_IN_SEL_S)
-#define GPIO_FUNC161_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC161_IN_SEL_S  0
-/** GPIO_FUNC161_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC161_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC161_IN_INV_SEL_M  (GPIO_FUNC161_IN_INV_SEL_V << GPIO_FUNC161_IN_INV_SEL_S)
-#define GPIO_FUNC161_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC161_IN_INV_SEL_S  6
-/** GPIO_SIG161_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG161_IN_SEL    (BIT(7))
-#define GPIO_SIG161_IN_SEL_M  (GPIO_SIG161_IN_SEL_V << GPIO_SIG161_IN_SEL_S)
-#define GPIO_SIG161_IN_SEL_V  0x00000001U
-#define GPIO_SIG161_IN_SEL_S  7
-
-/** GPIO_FUNC162_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0)
-/** GPIO_FUNC162_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC162_IN_SEL    0x0000003FU
-#define GPIO_FUNC162_IN_SEL_M  (GPIO_FUNC162_IN_SEL_V << GPIO_FUNC162_IN_SEL_S)
-#define GPIO_FUNC162_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC162_IN_SEL_S  0
-/** GPIO_FUNC162_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC162_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC162_IN_INV_SEL_M  (GPIO_FUNC162_IN_INV_SEL_V << GPIO_FUNC162_IN_INV_SEL_S)
-#define GPIO_FUNC162_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC162_IN_INV_SEL_S  6
-/** GPIO_SIG162_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG162_IN_SEL    (BIT(7))
-#define GPIO_SIG162_IN_SEL_M  (GPIO_SIG162_IN_SEL_V << GPIO_SIG162_IN_SEL_S)
-#define GPIO_SIG162_IN_SEL_V  0x00000001U
-#define GPIO_SIG162_IN_SEL_S  7
-
-/** GPIO_FUNC163_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4)
-/** GPIO_FUNC163_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC163_IN_SEL    0x0000003FU
-#define GPIO_FUNC163_IN_SEL_M  (GPIO_FUNC163_IN_SEL_V << GPIO_FUNC163_IN_SEL_S)
-#define GPIO_FUNC163_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC163_IN_SEL_S  0
-/** GPIO_FUNC163_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC163_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC163_IN_INV_SEL_M  (GPIO_FUNC163_IN_INV_SEL_V << GPIO_FUNC163_IN_INV_SEL_S)
-#define GPIO_FUNC163_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC163_IN_INV_SEL_S  6
-/** GPIO_SIG163_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG163_IN_SEL    (BIT(7))
-#define GPIO_SIG163_IN_SEL_M  (GPIO_SIG163_IN_SEL_V << GPIO_SIG163_IN_SEL_S)
-#define GPIO_SIG163_IN_SEL_V  0x00000001U
-#define GPIO_SIG163_IN_SEL_S  7
-
-/** GPIO_FUNC164_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8)
-/** GPIO_FUNC164_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC164_IN_SEL    0x0000003FU
-#define GPIO_FUNC164_IN_SEL_M  (GPIO_FUNC164_IN_SEL_V << GPIO_FUNC164_IN_SEL_S)
-#define GPIO_FUNC164_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC164_IN_SEL_S  0
-/** GPIO_FUNC164_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC164_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC164_IN_INV_SEL_M  (GPIO_FUNC164_IN_INV_SEL_V << GPIO_FUNC164_IN_INV_SEL_S)
-#define GPIO_FUNC164_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC164_IN_INV_SEL_S  6
-/** GPIO_SIG164_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG164_IN_SEL    (BIT(7))
-#define GPIO_SIG164_IN_SEL_M  (GPIO_SIG164_IN_SEL_V << GPIO_SIG164_IN_SEL_S)
-#define GPIO_SIG164_IN_SEL_V  0x00000001U
-#define GPIO_SIG164_IN_SEL_S  7
-
-/** GPIO_FUNC165_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec)
-/** GPIO_FUNC165_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC165_IN_SEL    0x0000003FU
-#define GPIO_FUNC165_IN_SEL_M  (GPIO_FUNC165_IN_SEL_V << GPIO_FUNC165_IN_SEL_S)
-#define GPIO_FUNC165_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC165_IN_SEL_S  0
-/** GPIO_FUNC165_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC165_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC165_IN_INV_SEL_M  (GPIO_FUNC165_IN_INV_SEL_V << GPIO_FUNC165_IN_INV_SEL_S)
-#define GPIO_FUNC165_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC165_IN_INV_SEL_S  6
-/** GPIO_SIG165_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG165_IN_SEL    (BIT(7))
-#define GPIO_SIG165_IN_SEL_M  (GPIO_SIG165_IN_SEL_V << GPIO_SIG165_IN_SEL_S)
-#define GPIO_SIG165_IN_SEL_V  0x00000001U
-#define GPIO_SIG165_IN_SEL_S  7
-
-/** GPIO_FUNC166_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f0)
-/** GPIO_FUNC166_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC166_IN_SEL    0x0000003FU
-#define GPIO_FUNC166_IN_SEL_M  (GPIO_FUNC166_IN_SEL_V << GPIO_FUNC166_IN_SEL_S)
-#define GPIO_FUNC166_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC166_IN_SEL_S  0
-/** GPIO_FUNC166_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC166_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC166_IN_INV_SEL_M  (GPIO_FUNC166_IN_INV_SEL_V << GPIO_FUNC166_IN_INV_SEL_S)
-#define GPIO_FUNC166_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC166_IN_INV_SEL_S  6
-/** GPIO_SIG166_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG166_IN_SEL    (BIT(7))
-#define GPIO_SIG166_IN_SEL_M  (GPIO_SIG166_IN_SEL_V << GPIO_SIG166_IN_SEL_S)
-#define GPIO_SIG166_IN_SEL_V  0x00000001U
-#define GPIO_SIG166_IN_SEL_S  7
-
-/** GPIO_FUNC167_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4)
-/** GPIO_FUNC167_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC167_IN_SEL    0x0000003FU
-#define GPIO_FUNC167_IN_SEL_M  (GPIO_FUNC167_IN_SEL_V << GPIO_FUNC167_IN_SEL_S)
-#define GPIO_FUNC167_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC167_IN_SEL_S  0
-/** GPIO_FUNC167_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC167_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC167_IN_INV_SEL_M  (GPIO_FUNC167_IN_INV_SEL_V << GPIO_FUNC167_IN_INV_SEL_S)
-#define GPIO_FUNC167_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC167_IN_INV_SEL_S  6
-/** GPIO_SIG167_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG167_IN_SEL    (BIT(7))
-#define GPIO_SIG167_IN_SEL_M  (GPIO_SIG167_IN_SEL_V << GPIO_SIG167_IN_SEL_S)
-#define GPIO_SIG167_IN_SEL_V  0x00000001U
-#define GPIO_SIG167_IN_SEL_S  7
-
-/** GPIO_FUNC168_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8)
-/** GPIO_FUNC168_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC168_IN_SEL    0x0000003FU
-#define GPIO_FUNC168_IN_SEL_M  (GPIO_FUNC168_IN_SEL_V << GPIO_FUNC168_IN_SEL_S)
-#define GPIO_FUNC168_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC168_IN_SEL_S  0
-/** GPIO_FUNC168_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC168_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC168_IN_INV_SEL_M  (GPIO_FUNC168_IN_INV_SEL_V << GPIO_FUNC168_IN_INV_SEL_S)
-#define GPIO_FUNC168_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC168_IN_INV_SEL_S  6
-/** GPIO_SIG168_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG168_IN_SEL    (BIT(7))
-#define GPIO_SIG168_IN_SEL_M  (GPIO_SIG168_IN_SEL_V << GPIO_SIG168_IN_SEL_S)
-#define GPIO_SIG168_IN_SEL_V  0x00000001U
-#define GPIO_SIG168_IN_SEL_S  7
-
-/** GPIO_FUNC169_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc)
-/** GPIO_FUNC169_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC169_IN_SEL    0x0000003FU
-#define GPIO_FUNC169_IN_SEL_M  (GPIO_FUNC169_IN_SEL_V << GPIO_FUNC169_IN_SEL_S)
-#define GPIO_FUNC169_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC169_IN_SEL_S  0
-/** GPIO_FUNC169_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC169_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC169_IN_INV_SEL_M  (GPIO_FUNC169_IN_INV_SEL_V << GPIO_FUNC169_IN_INV_SEL_S)
-#define GPIO_FUNC169_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC169_IN_INV_SEL_S  6
-/** GPIO_SIG169_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG169_IN_SEL    (BIT(7))
-#define GPIO_SIG169_IN_SEL_M  (GPIO_SIG169_IN_SEL_V << GPIO_SIG169_IN_SEL_S)
-#define GPIO_SIG169_IN_SEL_V  0x00000001U
-#define GPIO_SIG169_IN_SEL_S  7
-
-/** GPIO_FUNC170_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400)
-/** GPIO_FUNC170_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC170_IN_SEL    0x0000003FU
-#define GPIO_FUNC170_IN_SEL_M  (GPIO_FUNC170_IN_SEL_V << GPIO_FUNC170_IN_SEL_S)
-#define GPIO_FUNC170_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC170_IN_SEL_S  0
-/** GPIO_FUNC170_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC170_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC170_IN_INV_SEL_M  (GPIO_FUNC170_IN_INV_SEL_V << GPIO_FUNC170_IN_INV_SEL_S)
-#define GPIO_FUNC170_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC170_IN_INV_SEL_S  6
-/** GPIO_SIG170_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG170_IN_SEL    (BIT(7))
-#define GPIO_SIG170_IN_SEL_M  (GPIO_SIG170_IN_SEL_V << GPIO_SIG170_IN_SEL_S)
-#define GPIO_SIG170_IN_SEL_V  0x00000001U
-#define GPIO_SIG170_IN_SEL_S  7
-
-/** GPIO_FUNC171_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404)
-/** GPIO_FUNC171_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC171_IN_SEL    0x0000003FU
-#define GPIO_FUNC171_IN_SEL_M  (GPIO_FUNC171_IN_SEL_V << GPIO_FUNC171_IN_SEL_S)
-#define GPIO_FUNC171_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC171_IN_SEL_S  0
-/** GPIO_FUNC171_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC171_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC171_IN_INV_SEL_M  (GPIO_FUNC171_IN_INV_SEL_V << GPIO_FUNC171_IN_INV_SEL_S)
-#define GPIO_FUNC171_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC171_IN_INV_SEL_S  6
-/** GPIO_SIG171_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG171_IN_SEL    (BIT(7))
-#define GPIO_SIG171_IN_SEL_M  (GPIO_SIG171_IN_SEL_V << GPIO_SIG171_IN_SEL_S)
-#define GPIO_SIG171_IN_SEL_V  0x00000001U
-#define GPIO_SIG171_IN_SEL_S  7
-
-/** GPIO_FUNC172_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408)
-/** GPIO_FUNC172_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC172_IN_SEL    0x0000003FU
-#define GPIO_FUNC172_IN_SEL_M  (GPIO_FUNC172_IN_SEL_V << GPIO_FUNC172_IN_SEL_S)
-#define GPIO_FUNC172_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC172_IN_SEL_S  0
-/** GPIO_FUNC172_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC172_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC172_IN_INV_SEL_M  (GPIO_FUNC172_IN_INV_SEL_V << GPIO_FUNC172_IN_INV_SEL_S)
-#define GPIO_FUNC172_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC172_IN_INV_SEL_S  6
-/** GPIO_SIG172_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG172_IN_SEL    (BIT(7))
-#define GPIO_SIG172_IN_SEL_M  (GPIO_SIG172_IN_SEL_V << GPIO_SIG172_IN_SEL_S)
-#define GPIO_SIG172_IN_SEL_V  0x00000001U
-#define GPIO_SIG172_IN_SEL_S  7
-
-/** GPIO_FUNC173_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c)
-/** GPIO_FUNC173_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC173_IN_SEL    0x0000003FU
-#define GPIO_FUNC173_IN_SEL_M  (GPIO_FUNC173_IN_SEL_V << GPIO_FUNC173_IN_SEL_S)
-#define GPIO_FUNC173_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC173_IN_SEL_S  0
-/** GPIO_FUNC173_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC173_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC173_IN_INV_SEL_M  (GPIO_FUNC173_IN_INV_SEL_V << GPIO_FUNC173_IN_INV_SEL_S)
-#define GPIO_FUNC173_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC173_IN_INV_SEL_S  6
-/** GPIO_SIG173_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG173_IN_SEL    (BIT(7))
-#define GPIO_SIG173_IN_SEL_M  (GPIO_SIG173_IN_SEL_V << GPIO_SIG173_IN_SEL_S)
-#define GPIO_SIG173_IN_SEL_V  0x00000001U
-#define GPIO_SIG173_IN_SEL_S  7
-
-/** GPIO_FUNC174_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410)
-/** GPIO_FUNC174_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC174_IN_SEL    0x0000003FU
-#define GPIO_FUNC174_IN_SEL_M  (GPIO_FUNC174_IN_SEL_V << GPIO_FUNC174_IN_SEL_S)
-#define GPIO_FUNC174_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC174_IN_SEL_S  0
-/** GPIO_FUNC174_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC174_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC174_IN_INV_SEL_M  (GPIO_FUNC174_IN_INV_SEL_V << GPIO_FUNC174_IN_INV_SEL_S)
-#define GPIO_FUNC174_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC174_IN_INV_SEL_S  6
-/** GPIO_SIG174_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG174_IN_SEL    (BIT(7))
-#define GPIO_SIG174_IN_SEL_M  (GPIO_SIG174_IN_SEL_V << GPIO_SIG174_IN_SEL_S)
-#define GPIO_SIG174_IN_SEL_V  0x00000001U
-#define GPIO_SIG174_IN_SEL_S  7
-
-/** GPIO_FUNC175_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414)
-/** GPIO_FUNC175_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC175_IN_SEL    0x0000003FU
-#define GPIO_FUNC175_IN_SEL_M  (GPIO_FUNC175_IN_SEL_V << GPIO_FUNC175_IN_SEL_S)
-#define GPIO_FUNC175_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC175_IN_SEL_S  0
-/** GPIO_FUNC175_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC175_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC175_IN_INV_SEL_M  (GPIO_FUNC175_IN_INV_SEL_V << GPIO_FUNC175_IN_INV_SEL_S)
-#define GPIO_FUNC175_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC175_IN_INV_SEL_S  6
-/** GPIO_SIG175_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG175_IN_SEL    (BIT(7))
-#define GPIO_SIG175_IN_SEL_M  (GPIO_SIG175_IN_SEL_V << GPIO_SIG175_IN_SEL_S)
-#define GPIO_SIG175_IN_SEL_V  0x00000001U
-#define GPIO_SIG175_IN_SEL_S  7
-
-/** GPIO_FUNC176_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418)
-/** GPIO_FUNC176_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC176_IN_SEL    0x0000003FU
-#define GPIO_FUNC176_IN_SEL_M  (GPIO_FUNC176_IN_SEL_V << GPIO_FUNC176_IN_SEL_S)
-#define GPIO_FUNC176_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC176_IN_SEL_S  0
-/** GPIO_FUNC176_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC176_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC176_IN_INV_SEL_M  (GPIO_FUNC176_IN_INV_SEL_V << GPIO_FUNC176_IN_INV_SEL_S)
-#define GPIO_FUNC176_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC176_IN_INV_SEL_S  6
-/** GPIO_SIG176_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG176_IN_SEL    (BIT(7))
-#define GPIO_SIG176_IN_SEL_M  (GPIO_SIG176_IN_SEL_V << GPIO_SIG176_IN_SEL_S)
-#define GPIO_SIG176_IN_SEL_V  0x00000001U
-#define GPIO_SIG176_IN_SEL_S  7
-
-/** GPIO_FUNC177_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c)
-/** GPIO_FUNC177_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC177_IN_SEL    0x0000003FU
-#define GPIO_FUNC177_IN_SEL_M  (GPIO_FUNC177_IN_SEL_V << GPIO_FUNC177_IN_SEL_S)
-#define GPIO_FUNC177_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC177_IN_SEL_S  0
-/** GPIO_FUNC177_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC177_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC177_IN_INV_SEL_M  (GPIO_FUNC177_IN_INV_SEL_V << GPIO_FUNC177_IN_INV_SEL_S)
-#define GPIO_FUNC177_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC177_IN_INV_SEL_S  6
-/** GPIO_SIG177_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG177_IN_SEL    (BIT(7))
-#define GPIO_SIG177_IN_SEL_M  (GPIO_SIG177_IN_SEL_V << GPIO_SIG177_IN_SEL_S)
-#define GPIO_SIG177_IN_SEL_V  0x00000001U
-#define GPIO_SIG177_IN_SEL_S  7
-
-/** GPIO_FUNC178_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420)
-/** GPIO_FUNC178_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC178_IN_SEL    0x0000003FU
-#define GPIO_FUNC178_IN_SEL_M  (GPIO_FUNC178_IN_SEL_V << GPIO_FUNC178_IN_SEL_S)
-#define GPIO_FUNC178_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC178_IN_SEL_S  0
-/** GPIO_FUNC178_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC178_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC178_IN_INV_SEL_M  (GPIO_FUNC178_IN_INV_SEL_V << GPIO_FUNC178_IN_INV_SEL_S)
-#define GPIO_FUNC178_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC178_IN_INV_SEL_S  6
-/** GPIO_SIG178_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG178_IN_SEL    (BIT(7))
-#define GPIO_SIG178_IN_SEL_M  (GPIO_SIG178_IN_SEL_V << GPIO_SIG178_IN_SEL_S)
-#define GPIO_SIG178_IN_SEL_V  0x00000001U
-#define GPIO_SIG178_IN_SEL_S  7
-
-/** GPIO_FUNC179_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424)
-/** GPIO_FUNC179_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC179_IN_SEL    0x0000003FU
-#define GPIO_FUNC179_IN_SEL_M  (GPIO_FUNC179_IN_SEL_V << GPIO_FUNC179_IN_SEL_S)
-#define GPIO_FUNC179_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC179_IN_SEL_S  0
-/** GPIO_FUNC179_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC179_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC179_IN_INV_SEL_M  (GPIO_FUNC179_IN_INV_SEL_V << GPIO_FUNC179_IN_INV_SEL_S)
-#define GPIO_FUNC179_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC179_IN_INV_SEL_S  6
-/** GPIO_SIG179_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG179_IN_SEL    (BIT(7))
-#define GPIO_SIG179_IN_SEL_M  (GPIO_SIG179_IN_SEL_V << GPIO_SIG179_IN_SEL_S)
-#define GPIO_SIG179_IN_SEL_V  0x00000001U
-#define GPIO_SIG179_IN_SEL_S  7
-
-/** GPIO_FUNC180_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428)
-/** GPIO_FUNC180_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC180_IN_SEL    0x0000003FU
-#define GPIO_FUNC180_IN_SEL_M  (GPIO_FUNC180_IN_SEL_V << GPIO_FUNC180_IN_SEL_S)
-#define GPIO_FUNC180_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC180_IN_SEL_S  0
-/** GPIO_FUNC180_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC180_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC180_IN_INV_SEL_M  (GPIO_FUNC180_IN_INV_SEL_V << GPIO_FUNC180_IN_INV_SEL_S)
-#define GPIO_FUNC180_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC180_IN_INV_SEL_S  6
-/** GPIO_SIG180_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG180_IN_SEL    (BIT(7))
-#define GPIO_SIG180_IN_SEL_M  (GPIO_SIG180_IN_SEL_V << GPIO_SIG180_IN_SEL_S)
-#define GPIO_SIG180_IN_SEL_V  0x00000001U
-#define GPIO_SIG180_IN_SEL_S  7
-
-/** GPIO_FUNC181_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c)
-/** GPIO_FUNC181_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC181_IN_SEL    0x0000003FU
-#define GPIO_FUNC181_IN_SEL_M  (GPIO_FUNC181_IN_SEL_V << GPIO_FUNC181_IN_SEL_S)
-#define GPIO_FUNC181_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC181_IN_SEL_S  0
-/** GPIO_FUNC181_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC181_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC181_IN_INV_SEL_M  (GPIO_FUNC181_IN_INV_SEL_V << GPIO_FUNC181_IN_INV_SEL_S)
-#define GPIO_FUNC181_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC181_IN_INV_SEL_S  6
-/** GPIO_SIG181_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG181_IN_SEL    (BIT(7))
-#define GPIO_SIG181_IN_SEL_M  (GPIO_SIG181_IN_SEL_V << GPIO_SIG181_IN_SEL_S)
-#define GPIO_SIG181_IN_SEL_V  0x00000001U
-#define GPIO_SIG181_IN_SEL_S  7
-
-/** GPIO_FUNC182_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430)
-/** GPIO_FUNC182_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC182_IN_SEL    0x0000003FU
-#define GPIO_FUNC182_IN_SEL_M  (GPIO_FUNC182_IN_SEL_V << GPIO_FUNC182_IN_SEL_S)
-#define GPIO_FUNC182_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC182_IN_SEL_S  0
-/** GPIO_FUNC182_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC182_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC182_IN_INV_SEL_M  (GPIO_FUNC182_IN_INV_SEL_V << GPIO_FUNC182_IN_INV_SEL_S)
-#define GPIO_FUNC182_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC182_IN_INV_SEL_S  6
-/** GPIO_SIG182_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG182_IN_SEL    (BIT(7))
-#define GPIO_SIG182_IN_SEL_M  (GPIO_SIG182_IN_SEL_V << GPIO_SIG182_IN_SEL_S)
-#define GPIO_SIG182_IN_SEL_V  0x00000001U
-#define GPIO_SIG182_IN_SEL_S  7
-
-/** GPIO_FUNC183_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434)
-/** GPIO_FUNC183_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC183_IN_SEL    0x0000003FU
-#define GPIO_FUNC183_IN_SEL_M  (GPIO_FUNC183_IN_SEL_V << GPIO_FUNC183_IN_SEL_S)
-#define GPIO_FUNC183_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC183_IN_SEL_S  0
-/** GPIO_FUNC183_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC183_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC183_IN_INV_SEL_M  (GPIO_FUNC183_IN_INV_SEL_V << GPIO_FUNC183_IN_INV_SEL_S)
-#define GPIO_FUNC183_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC183_IN_INV_SEL_S  6
-/** GPIO_SIG183_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG183_IN_SEL    (BIT(7))
-#define GPIO_SIG183_IN_SEL_M  (GPIO_SIG183_IN_SEL_V << GPIO_SIG183_IN_SEL_S)
-#define GPIO_SIG183_IN_SEL_V  0x00000001U
-#define GPIO_SIG183_IN_SEL_S  7
-
-/** GPIO_FUNC184_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438)
-/** GPIO_FUNC184_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC184_IN_SEL    0x0000003FU
-#define GPIO_FUNC184_IN_SEL_M  (GPIO_FUNC184_IN_SEL_V << GPIO_FUNC184_IN_SEL_S)
-#define GPIO_FUNC184_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC184_IN_SEL_S  0
-/** GPIO_FUNC184_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC184_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC184_IN_INV_SEL_M  (GPIO_FUNC184_IN_INV_SEL_V << GPIO_FUNC184_IN_INV_SEL_S)
-#define GPIO_FUNC184_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC184_IN_INV_SEL_S  6
-/** GPIO_SIG184_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG184_IN_SEL    (BIT(7))
-#define GPIO_SIG184_IN_SEL_M  (GPIO_SIG184_IN_SEL_V << GPIO_SIG184_IN_SEL_S)
-#define GPIO_SIG184_IN_SEL_V  0x00000001U
-#define GPIO_SIG184_IN_SEL_S  7
-
-/** GPIO_FUNC185_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43c)
-/** GPIO_FUNC185_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC185_IN_SEL    0x0000003FU
-#define GPIO_FUNC185_IN_SEL_M  (GPIO_FUNC185_IN_SEL_V << GPIO_FUNC185_IN_SEL_S)
-#define GPIO_FUNC185_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC185_IN_SEL_S  0
-/** GPIO_FUNC185_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC185_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC185_IN_INV_SEL_M  (GPIO_FUNC185_IN_INV_SEL_V << GPIO_FUNC185_IN_INV_SEL_S)
-#define GPIO_FUNC185_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC185_IN_INV_SEL_S  6
-/** GPIO_SIG185_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG185_IN_SEL    (BIT(7))
-#define GPIO_SIG185_IN_SEL_M  (GPIO_SIG185_IN_SEL_V << GPIO_SIG185_IN_SEL_S)
-#define GPIO_SIG185_IN_SEL_V  0x00000001U
-#define GPIO_SIG185_IN_SEL_S  7
-
-/** GPIO_FUNC186_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440)
-/** GPIO_FUNC186_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC186_IN_SEL    0x0000003FU
-#define GPIO_FUNC186_IN_SEL_M  (GPIO_FUNC186_IN_SEL_V << GPIO_FUNC186_IN_SEL_S)
-#define GPIO_FUNC186_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC186_IN_SEL_S  0
-/** GPIO_FUNC186_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC186_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC186_IN_INV_SEL_M  (GPIO_FUNC186_IN_INV_SEL_V << GPIO_FUNC186_IN_INV_SEL_S)
-#define GPIO_FUNC186_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC186_IN_INV_SEL_S  6
-/** GPIO_SIG186_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG186_IN_SEL    (BIT(7))
-#define GPIO_SIG186_IN_SEL_M  (GPIO_SIG186_IN_SEL_V << GPIO_SIG186_IN_SEL_S)
-#define GPIO_SIG186_IN_SEL_V  0x00000001U
-#define GPIO_SIG186_IN_SEL_S  7
-
-/** GPIO_FUNC187_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444)
-/** GPIO_FUNC187_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC187_IN_SEL    0x0000003FU
-#define GPIO_FUNC187_IN_SEL_M  (GPIO_FUNC187_IN_SEL_V << GPIO_FUNC187_IN_SEL_S)
-#define GPIO_FUNC187_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC187_IN_SEL_S  0
-/** GPIO_FUNC187_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC187_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC187_IN_INV_SEL_M  (GPIO_FUNC187_IN_INV_SEL_V << GPIO_FUNC187_IN_INV_SEL_S)
-#define GPIO_FUNC187_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC187_IN_INV_SEL_S  6
-/** GPIO_SIG187_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG187_IN_SEL    (BIT(7))
-#define GPIO_SIG187_IN_SEL_M  (GPIO_SIG187_IN_SEL_V << GPIO_SIG187_IN_SEL_S)
-#define GPIO_SIG187_IN_SEL_V  0x00000001U
-#define GPIO_SIG187_IN_SEL_S  7
-
-/** GPIO_FUNC188_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448)
-/** GPIO_FUNC188_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC188_IN_SEL    0x0000003FU
-#define GPIO_FUNC188_IN_SEL_M  (GPIO_FUNC188_IN_SEL_V << GPIO_FUNC188_IN_SEL_S)
-#define GPIO_FUNC188_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC188_IN_SEL_S  0
-/** GPIO_FUNC188_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC188_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC188_IN_INV_SEL_M  (GPIO_FUNC188_IN_INV_SEL_V << GPIO_FUNC188_IN_INV_SEL_S)
-#define GPIO_FUNC188_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC188_IN_INV_SEL_S  6
-/** GPIO_SIG188_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG188_IN_SEL    (BIT(7))
-#define GPIO_SIG188_IN_SEL_M  (GPIO_SIG188_IN_SEL_V << GPIO_SIG188_IN_SEL_S)
-#define GPIO_SIG188_IN_SEL_V  0x00000001U
-#define GPIO_SIG188_IN_SEL_S  7
-
-/** GPIO_FUNC189_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c)
-/** GPIO_FUNC189_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC189_IN_SEL    0x0000003FU
-#define GPIO_FUNC189_IN_SEL_M  (GPIO_FUNC189_IN_SEL_V << GPIO_FUNC189_IN_SEL_S)
-#define GPIO_FUNC189_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC189_IN_SEL_S  0
-/** GPIO_FUNC189_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC189_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC189_IN_INV_SEL_M  (GPIO_FUNC189_IN_INV_SEL_V << GPIO_FUNC189_IN_INV_SEL_S)
-#define GPIO_FUNC189_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC189_IN_INV_SEL_S  6
-/** GPIO_SIG189_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG189_IN_SEL    (BIT(7))
-#define GPIO_SIG189_IN_SEL_M  (GPIO_SIG189_IN_SEL_V << GPIO_SIG189_IN_SEL_S)
-#define GPIO_SIG189_IN_SEL_V  0x00000001U
-#define GPIO_SIG189_IN_SEL_S  7
-
-/** GPIO_FUNC190_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450)
-/** GPIO_FUNC190_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC190_IN_SEL    0x0000003FU
-#define GPIO_FUNC190_IN_SEL_M  (GPIO_FUNC190_IN_SEL_V << GPIO_FUNC190_IN_SEL_S)
-#define GPIO_FUNC190_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC190_IN_SEL_S  0
-/** GPIO_FUNC190_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC190_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC190_IN_INV_SEL_M  (GPIO_FUNC190_IN_INV_SEL_V << GPIO_FUNC190_IN_INV_SEL_S)
-#define GPIO_FUNC190_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC190_IN_INV_SEL_S  6
-/** GPIO_SIG190_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG190_IN_SEL    (BIT(7))
-#define GPIO_SIG190_IN_SEL_M  (GPIO_SIG190_IN_SEL_V << GPIO_SIG190_IN_SEL_S)
-#define GPIO_SIG190_IN_SEL_V  0x00000001U
-#define GPIO_SIG190_IN_SEL_S  7
-
-/** GPIO_FUNC191_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454)
-/** GPIO_FUNC191_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC191_IN_SEL    0x0000003FU
-#define GPIO_FUNC191_IN_SEL_M  (GPIO_FUNC191_IN_SEL_V << GPIO_FUNC191_IN_SEL_S)
-#define GPIO_FUNC191_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC191_IN_SEL_S  0
-/** GPIO_FUNC191_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC191_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC191_IN_INV_SEL_M  (GPIO_FUNC191_IN_INV_SEL_V << GPIO_FUNC191_IN_INV_SEL_S)
-#define GPIO_FUNC191_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC191_IN_INV_SEL_S  6
-/** GPIO_SIG191_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG191_IN_SEL    (BIT(7))
-#define GPIO_SIG191_IN_SEL_M  (GPIO_SIG191_IN_SEL_V << GPIO_SIG191_IN_SEL_S)
-#define GPIO_SIG191_IN_SEL_V  0x00000001U
-#define GPIO_SIG191_IN_SEL_S  7
-
-/** GPIO_FUNC192_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458)
-/** GPIO_FUNC192_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC192_IN_SEL    0x0000003FU
-#define GPIO_FUNC192_IN_SEL_M  (GPIO_FUNC192_IN_SEL_V << GPIO_FUNC192_IN_SEL_S)
-#define GPIO_FUNC192_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC192_IN_SEL_S  0
-/** GPIO_FUNC192_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC192_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC192_IN_INV_SEL_M  (GPIO_FUNC192_IN_INV_SEL_V << GPIO_FUNC192_IN_INV_SEL_S)
-#define GPIO_FUNC192_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC192_IN_INV_SEL_S  6
-/** GPIO_SIG192_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG192_IN_SEL    (BIT(7))
-#define GPIO_SIG192_IN_SEL_M  (GPIO_SIG192_IN_SEL_V << GPIO_SIG192_IN_SEL_S)
-#define GPIO_SIG192_IN_SEL_V  0x00000001U
-#define GPIO_SIG192_IN_SEL_S  7
-
-/** GPIO_FUNC193_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c)
-/** GPIO_FUNC193_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC193_IN_SEL    0x0000003FU
-#define GPIO_FUNC193_IN_SEL_M  (GPIO_FUNC193_IN_SEL_V << GPIO_FUNC193_IN_SEL_S)
-#define GPIO_FUNC193_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC193_IN_SEL_S  0
-/** GPIO_FUNC193_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC193_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC193_IN_INV_SEL_M  (GPIO_FUNC193_IN_INV_SEL_V << GPIO_FUNC193_IN_INV_SEL_S)
-#define GPIO_FUNC193_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC193_IN_INV_SEL_S  6
-/** GPIO_SIG193_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG193_IN_SEL    (BIT(7))
-#define GPIO_SIG193_IN_SEL_M  (GPIO_SIG193_IN_SEL_V << GPIO_SIG193_IN_SEL_S)
-#define GPIO_SIG193_IN_SEL_V  0x00000001U
-#define GPIO_SIG193_IN_SEL_S  7
-
-/** GPIO_FUNC194_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460)
-/** GPIO_FUNC194_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC194_IN_SEL    0x0000003FU
-#define GPIO_FUNC194_IN_SEL_M  (GPIO_FUNC194_IN_SEL_V << GPIO_FUNC194_IN_SEL_S)
-#define GPIO_FUNC194_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC194_IN_SEL_S  0
-/** GPIO_FUNC194_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC194_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC194_IN_INV_SEL_M  (GPIO_FUNC194_IN_INV_SEL_V << GPIO_FUNC194_IN_INV_SEL_S)
-#define GPIO_FUNC194_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC194_IN_INV_SEL_S  6
-/** GPIO_SIG194_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG194_IN_SEL    (BIT(7))
-#define GPIO_SIG194_IN_SEL_M  (GPIO_SIG194_IN_SEL_V << GPIO_SIG194_IN_SEL_S)
-#define GPIO_SIG194_IN_SEL_V  0x00000001U
-#define GPIO_SIG194_IN_SEL_S  7
-
-/** GPIO_FUNC195_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464)
-/** GPIO_FUNC195_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC195_IN_SEL    0x0000003FU
-#define GPIO_FUNC195_IN_SEL_M  (GPIO_FUNC195_IN_SEL_V << GPIO_FUNC195_IN_SEL_S)
-#define GPIO_FUNC195_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC195_IN_SEL_S  0
-/** GPIO_FUNC195_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC195_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC195_IN_INV_SEL_M  (GPIO_FUNC195_IN_INV_SEL_V << GPIO_FUNC195_IN_INV_SEL_S)
-#define GPIO_FUNC195_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC195_IN_INV_SEL_S  6
-/** GPIO_SIG195_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG195_IN_SEL    (BIT(7))
-#define GPIO_SIG195_IN_SEL_M  (GPIO_SIG195_IN_SEL_V << GPIO_SIG195_IN_SEL_S)
-#define GPIO_SIG195_IN_SEL_V  0x00000001U
-#define GPIO_SIG195_IN_SEL_S  7
-
-/** GPIO_FUNC196_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468)
-/** GPIO_FUNC196_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC196_IN_SEL    0x0000003FU
-#define GPIO_FUNC196_IN_SEL_M  (GPIO_FUNC196_IN_SEL_V << GPIO_FUNC196_IN_SEL_S)
-#define GPIO_FUNC196_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC196_IN_SEL_S  0
-/** GPIO_FUNC196_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC196_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC196_IN_INV_SEL_M  (GPIO_FUNC196_IN_INV_SEL_V << GPIO_FUNC196_IN_INV_SEL_S)
-#define GPIO_FUNC196_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC196_IN_INV_SEL_S  6
-/** GPIO_SIG196_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG196_IN_SEL    (BIT(7))
-#define GPIO_SIG196_IN_SEL_M  (GPIO_SIG196_IN_SEL_V << GPIO_SIG196_IN_SEL_S)
-#define GPIO_SIG196_IN_SEL_V  0x00000001U
-#define GPIO_SIG196_IN_SEL_S  7
-
-/** GPIO_FUNC197_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c)
-/** GPIO_FUNC197_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC197_IN_SEL    0x0000003FU
-#define GPIO_FUNC197_IN_SEL_M  (GPIO_FUNC197_IN_SEL_V << GPIO_FUNC197_IN_SEL_S)
-#define GPIO_FUNC197_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC197_IN_SEL_S  0
-/** GPIO_FUNC197_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC197_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC197_IN_INV_SEL_M  (GPIO_FUNC197_IN_INV_SEL_V << GPIO_FUNC197_IN_INV_SEL_S)
-#define GPIO_FUNC197_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC197_IN_INV_SEL_S  6
-/** GPIO_SIG197_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG197_IN_SEL    (BIT(7))
-#define GPIO_SIG197_IN_SEL_M  (GPIO_SIG197_IN_SEL_V << GPIO_SIG197_IN_SEL_S)
-#define GPIO_SIG197_IN_SEL_V  0x00000001U
-#define GPIO_SIG197_IN_SEL_S  7
-
-/** GPIO_FUNC198_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470)
-/** GPIO_FUNC198_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC198_IN_SEL    0x0000003FU
-#define GPIO_FUNC198_IN_SEL_M  (GPIO_FUNC198_IN_SEL_V << GPIO_FUNC198_IN_SEL_S)
-#define GPIO_FUNC198_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC198_IN_SEL_S  0
-/** GPIO_FUNC198_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC198_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC198_IN_INV_SEL_M  (GPIO_FUNC198_IN_INV_SEL_V << GPIO_FUNC198_IN_INV_SEL_S)
-#define GPIO_FUNC198_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC198_IN_INV_SEL_S  6
-/** GPIO_SIG198_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG198_IN_SEL    (BIT(7))
-#define GPIO_SIG198_IN_SEL_M  (GPIO_SIG198_IN_SEL_V << GPIO_SIG198_IN_SEL_S)
-#define GPIO_SIG198_IN_SEL_V  0x00000001U
-#define GPIO_SIG198_IN_SEL_S  7
-
-/** GPIO_FUNC199_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474)
-/** GPIO_FUNC199_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC199_IN_SEL    0x0000003FU
-#define GPIO_FUNC199_IN_SEL_M  (GPIO_FUNC199_IN_SEL_V << GPIO_FUNC199_IN_SEL_S)
-#define GPIO_FUNC199_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC199_IN_SEL_S  0
-/** GPIO_FUNC199_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC199_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC199_IN_INV_SEL_M  (GPIO_FUNC199_IN_INV_SEL_V << GPIO_FUNC199_IN_INV_SEL_S)
-#define GPIO_FUNC199_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC199_IN_INV_SEL_S  6
-/** GPIO_SIG199_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG199_IN_SEL    (BIT(7))
-#define GPIO_SIG199_IN_SEL_M  (GPIO_SIG199_IN_SEL_V << GPIO_SIG199_IN_SEL_S)
-#define GPIO_SIG199_IN_SEL_V  0x00000001U
-#define GPIO_SIG199_IN_SEL_S  7
-
-/** GPIO_FUNC200_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478)
-/** GPIO_FUNC200_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC200_IN_SEL    0x0000003FU
-#define GPIO_FUNC200_IN_SEL_M  (GPIO_FUNC200_IN_SEL_V << GPIO_FUNC200_IN_SEL_S)
-#define GPIO_FUNC200_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC200_IN_SEL_S  0
-/** GPIO_FUNC200_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC200_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC200_IN_INV_SEL_M  (GPIO_FUNC200_IN_INV_SEL_V << GPIO_FUNC200_IN_INV_SEL_S)
-#define GPIO_FUNC200_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC200_IN_INV_SEL_S  6
-/** GPIO_SIG200_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG200_IN_SEL    (BIT(7))
-#define GPIO_SIG200_IN_SEL_M  (GPIO_SIG200_IN_SEL_V << GPIO_SIG200_IN_SEL_S)
-#define GPIO_SIG200_IN_SEL_V  0x00000001U
-#define GPIO_SIG200_IN_SEL_S  7
-
-/** GPIO_FUNC201_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c)
-/** GPIO_FUNC201_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC201_IN_SEL    0x0000003FU
-#define GPIO_FUNC201_IN_SEL_M  (GPIO_FUNC201_IN_SEL_V << GPIO_FUNC201_IN_SEL_S)
-#define GPIO_FUNC201_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC201_IN_SEL_S  0
-/** GPIO_FUNC201_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC201_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC201_IN_INV_SEL_M  (GPIO_FUNC201_IN_INV_SEL_V << GPIO_FUNC201_IN_INV_SEL_S)
-#define GPIO_FUNC201_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC201_IN_INV_SEL_S  6
-/** GPIO_SIG201_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG201_IN_SEL    (BIT(7))
-#define GPIO_SIG201_IN_SEL_M  (GPIO_SIG201_IN_SEL_V << GPIO_SIG201_IN_SEL_S)
-#define GPIO_SIG201_IN_SEL_V  0x00000001U
-#define GPIO_SIG201_IN_SEL_S  7
-
-/** GPIO_FUNC202_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480)
-/** GPIO_FUNC202_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC202_IN_SEL    0x0000003FU
-#define GPIO_FUNC202_IN_SEL_M  (GPIO_FUNC202_IN_SEL_V << GPIO_FUNC202_IN_SEL_S)
-#define GPIO_FUNC202_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC202_IN_SEL_S  0
-/** GPIO_FUNC202_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC202_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC202_IN_INV_SEL_M  (GPIO_FUNC202_IN_INV_SEL_V << GPIO_FUNC202_IN_INV_SEL_S)
-#define GPIO_FUNC202_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC202_IN_INV_SEL_S  6
-/** GPIO_SIG202_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG202_IN_SEL    (BIT(7))
-#define GPIO_SIG202_IN_SEL_M  (GPIO_SIG202_IN_SEL_V << GPIO_SIG202_IN_SEL_S)
-#define GPIO_SIG202_IN_SEL_V  0x00000001U
-#define GPIO_SIG202_IN_SEL_S  7
-
-/** GPIO_FUNC203_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484)
-/** GPIO_FUNC203_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC203_IN_SEL    0x0000003FU
-#define GPIO_FUNC203_IN_SEL_M  (GPIO_FUNC203_IN_SEL_V << GPIO_FUNC203_IN_SEL_S)
-#define GPIO_FUNC203_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC203_IN_SEL_S  0
-/** GPIO_FUNC203_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC203_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC203_IN_INV_SEL_M  (GPIO_FUNC203_IN_INV_SEL_V << GPIO_FUNC203_IN_INV_SEL_S)
-#define GPIO_FUNC203_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC203_IN_INV_SEL_S  6
-/** GPIO_SIG203_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG203_IN_SEL    (BIT(7))
-#define GPIO_SIG203_IN_SEL_M  (GPIO_SIG203_IN_SEL_V << GPIO_SIG203_IN_SEL_S)
-#define GPIO_SIG203_IN_SEL_V  0x00000001U
-#define GPIO_SIG203_IN_SEL_S  7
-
-/** GPIO_FUNC214_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0)
-/** GPIO_FUNC214_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC214_IN_SEL    0x0000003FU
-#define GPIO_FUNC214_IN_SEL_M  (GPIO_FUNC214_IN_SEL_V << GPIO_FUNC214_IN_SEL_S)
-#define GPIO_FUNC214_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC214_IN_SEL_S  0
-/** GPIO_FUNC214_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC214_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC214_IN_INV_SEL_M  (GPIO_FUNC214_IN_INV_SEL_V << GPIO_FUNC214_IN_INV_SEL_S)
-#define GPIO_FUNC214_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC214_IN_INV_SEL_S  6
-/** GPIO_SIG214_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG214_IN_SEL    (BIT(7))
-#define GPIO_SIG214_IN_SEL_M  (GPIO_SIG214_IN_SEL_V << GPIO_SIG214_IN_SEL_S)
-#define GPIO_SIG214_IN_SEL_V  0x00000001U
-#define GPIO_SIG214_IN_SEL_S  7
-
-/** GPIO_FUNC215_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4)
-/** GPIO_FUNC215_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC215_IN_SEL    0x0000003FU
-#define GPIO_FUNC215_IN_SEL_M  (GPIO_FUNC215_IN_SEL_V << GPIO_FUNC215_IN_SEL_S)
-#define GPIO_FUNC215_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC215_IN_SEL_S  0
-/** GPIO_FUNC215_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC215_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC215_IN_INV_SEL_M  (GPIO_FUNC215_IN_INV_SEL_V << GPIO_FUNC215_IN_INV_SEL_S)
-#define GPIO_FUNC215_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC215_IN_INV_SEL_S  6
-/** GPIO_SIG215_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG215_IN_SEL    (BIT(7))
-#define GPIO_SIG215_IN_SEL_M  (GPIO_SIG215_IN_SEL_V << GPIO_SIG215_IN_SEL_S)
-#define GPIO_SIG215_IN_SEL_V  0x00000001U
-#define GPIO_SIG215_IN_SEL_S  7
-
-/** GPIO_FUNC216_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8)
-/** GPIO_FUNC216_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC216_IN_SEL    0x0000003FU
-#define GPIO_FUNC216_IN_SEL_M  (GPIO_FUNC216_IN_SEL_V << GPIO_FUNC216_IN_SEL_S)
-#define GPIO_FUNC216_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC216_IN_SEL_S  0
-/** GPIO_FUNC216_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC216_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC216_IN_INV_SEL_M  (GPIO_FUNC216_IN_INV_SEL_V << GPIO_FUNC216_IN_INV_SEL_S)
-#define GPIO_FUNC216_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC216_IN_INV_SEL_S  6
-/** GPIO_SIG216_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG216_IN_SEL    (BIT(7))
-#define GPIO_SIG216_IN_SEL_M  (GPIO_SIG216_IN_SEL_V << GPIO_SIG216_IN_SEL_S)
-#define GPIO_SIG216_IN_SEL_V  0x00000001U
-#define GPIO_SIG216_IN_SEL_S  7
-
-/** GPIO_FUNC217_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4bc)
-/** GPIO_FUNC217_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC217_IN_SEL    0x0000003FU
-#define GPIO_FUNC217_IN_SEL_M  (GPIO_FUNC217_IN_SEL_V << GPIO_FUNC217_IN_SEL_S)
-#define GPIO_FUNC217_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC217_IN_SEL_S  0
-/** GPIO_FUNC217_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC217_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC217_IN_INV_SEL_M  (GPIO_FUNC217_IN_INV_SEL_V << GPIO_FUNC217_IN_INV_SEL_S)
-#define GPIO_FUNC217_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC217_IN_INV_SEL_S  6
-/** GPIO_SIG217_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG217_IN_SEL    (BIT(7))
-#define GPIO_SIG217_IN_SEL_M  (GPIO_SIG217_IN_SEL_V << GPIO_SIG217_IN_SEL_S)
-#define GPIO_SIG217_IN_SEL_V  0x00000001U
-#define GPIO_SIG217_IN_SEL_S  7
-
-/** GPIO_FUNC218_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c0)
-/** GPIO_FUNC218_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC218_IN_SEL    0x0000003FU
-#define GPIO_FUNC218_IN_SEL_M  (GPIO_FUNC218_IN_SEL_V << GPIO_FUNC218_IN_SEL_S)
-#define GPIO_FUNC218_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC218_IN_SEL_S  0
-/** GPIO_FUNC218_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC218_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC218_IN_INV_SEL_M  (GPIO_FUNC218_IN_INV_SEL_V << GPIO_FUNC218_IN_INV_SEL_S)
-#define GPIO_FUNC218_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC218_IN_INV_SEL_S  6
-/** GPIO_SIG218_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG218_IN_SEL    (BIT(7))
-#define GPIO_SIG218_IN_SEL_M  (GPIO_SIG218_IN_SEL_V << GPIO_SIG218_IN_SEL_S)
-#define GPIO_SIG218_IN_SEL_V  0x00000001U
-#define GPIO_SIG218_IN_SEL_S  7
-
-/** GPIO_FUNC219_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c4)
-/** GPIO_FUNC219_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC219_IN_SEL    0x0000003FU
-#define GPIO_FUNC219_IN_SEL_M  (GPIO_FUNC219_IN_SEL_V << GPIO_FUNC219_IN_SEL_S)
-#define GPIO_FUNC219_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC219_IN_SEL_S  0
-/** GPIO_FUNC219_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC219_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC219_IN_INV_SEL_M  (GPIO_FUNC219_IN_INV_SEL_V << GPIO_FUNC219_IN_INV_SEL_S)
-#define GPIO_FUNC219_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC219_IN_INV_SEL_S  6
-/** GPIO_SIG219_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG219_IN_SEL    (BIT(7))
-#define GPIO_SIG219_IN_SEL_M  (GPIO_SIG219_IN_SEL_V << GPIO_SIG219_IN_SEL_S)
-#define GPIO_SIG219_IN_SEL_V  0x00000001U
-#define GPIO_SIG219_IN_SEL_S  7
-
-/** GPIO_FUNC220_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c8)
-/** GPIO_FUNC220_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC220_IN_SEL    0x0000003FU
-#define GPIO_FUNC220_IN_SEL_M  (GPIO_FUNC220_IN_SEL_V << GPIO_FUNC220_IN_SEL_S)
-#define GPIO_FUNC220_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC220_IN_SEL_S  0
-/** GPIO_FUNC220_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC220_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC220_IN_INV_SEL_M  (GPIO_FUNC220_IN_INV_SEL_V << GPIO_FUNC220_IN_INV_SEL_S)
-#define GPIO_FUNC220_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC220_IN_INV_SEL_S  6
-/** GPIO_SIG220_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG220_IN_SEL    (BIT(7))
-#define GPIO_SIG220_IN_SEL_M  (GPIO_SIG220_IN_SEL_V << GPIO_SIG220_IN_SEL_S)
-#define GPIO_SIG220_IN_SEL_V  0x00000001U
-#define GPIO_SIG220_IN_SEL_S  7
-
-/** GPIO_FUNC221_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4cc)
-/** GPIO_FUNC221_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC221_IN_SEL    0x0000003FU
-#define GPIO_FUNC221_IN_SEL_M  (GPIO_FUNC221_IN_SEL_V << GPIO_FUNC221_IN_SEL_S)
-#define GPIO_FUNC221_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC221_IN_SEL_S  0
-/** GPIO_FUNC221_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC221_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC221_IN_INV_SEL_M  (GPIO_FUNC221_IN_INV_SEL_V << GPIO_FUNC221_IN_INV_SEL_S)
-#define GPIO_FUNC221_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC221_IN_INV_SEL_S  6
-/** GPIO_SIG221_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG221_IN_SEL    (BIT(7))
-#define GPIO_SIG221_IN_SEL_M  (GPIO_SIG221_IN_SEL_V << GPIO_SIG221_IN_SEL_S)
-#define GPIO_SIG221_IN_SEL_V  0x00000001U
-#define GPIO_SIG221_IN_SEL_S  7
-
-/** GPIO_FUNC222_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d0)
-/** GPIO_FUNC222_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC222_IN_SEL    0x0000003FU
-#define GPIO_FUNC222_IN_SEL_M  (GPIO_FUNC222_IN_SEL_V << GPIO_FUNC222_IN_SEL_S)
-#define GPIO_FUNC222_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC222_IN_SEL_S  0
-/** GPIO_FUNC222_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC222_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC222_IN_INV_SEL_M  (GPIO_FUNC222_IN_INV_SEL_V << GPIO_FUNC222_IN_INV_SEL_S)
-#define GPIO_FUNC222_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC222_IN_INV_SEL_S  6
-/** GPIO_SIG222_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG222_IN_SEL    (BIT(7))
-#define GPIO_SIG222_IN_SEL_M  (GPIO_SIG222_IN_SEL_V << GPIO_SIG222_IN_SEL_S)
-#define GPIO_SIG222_IN_SEL_V  0x00000001U
-#define GPIO_SIG222_IN_SEL_S  7
-
-/** GPIO_FUNC223_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d4)
-/** GPIO_FUNC223_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC223_IN_SEL    0x0000003FU
-#define GPIO_FUNC223_IN_SEL_M  (GPIO_FUNC223_IN_SEL_V << GPIO_FUNC223_IN_SEL_S)
-#define GPIO_FUNC223_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC223_IN_SEL_S  0
-/** GPIO_FUNC223_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC223_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC223_IN_INV_SEL_M  (GPIO_FUNC223_IN_INV_SEL_V << GPIO_FUNC223_IN_INV_SEL_S)
-#define GPIO_FUNC223_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC223_IN_INV_SEL_S  6
-/** GPIO_SIG223_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG223_IN_SEL    (BIT(7))
-#define GPIO_SIG223_IN_SEL_M  (GPIO_SIG223_IN_SEL_V << GPIO_SIG223_IN_SEL_S)
-#define GPIO_SIG223_IN_SEL_V  0x00000001U
-#define GPIO_SIG223_IN_SEL_S  7
-
-/** GPIO_FUNC224_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d8)
-/** GPIO_FUNC224_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC224_IN_SEL    0x0000003FU
-#define GPIO_FUNC224_IN_SEL_M  (GPIO_FUNC224_IN_SEL_V << GPIO_FUNC224_IN_SEL_S)
-#define GPIO_FUNC224_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC224_IN_SEL_S  0
-/** GPIO_FUNC224_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC224_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC224_IN_INV_SEL_M  (GPIO_FUNC224_IN_INV_SEL_V << GPIO_FUNC224_IN_INV_SEL_S)
-#define GPIO_FUNC224_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC224_IN_INV_SEL_S  6
-/** GPIO_SIG224_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG224_IN_SEL    (BIT(7))
-#define GPIO_SIG224_IN_SEL_M  (GPIO_SIG224_IN_SEL_V << GPIO_SIG224_IN_SEL_S)
-#define GPIO_SIG224_IN_SEL_V  0x00000001U
-#define GPIO_SIG224_IN_SEL_S  7
-
-/** GPIO_FUNC225_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4dc)
-/** GPIO_FUNC225_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC225_IN_SEL    0x0000003FU
-#define GPIO_FUNC225_IN_SEL_M  (GPIO_FUNC225_IN_SEL_V << GPIO_FUNC225_IN_SEL_S)
-#define GPIO_FUNC225_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC225_IN_SEL_S  0
-/** GPIO_FUNC225_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC225_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC225_IN_INV_SEL_M  (GPIO_FUNC225_IN_INV_SEL_V << GPIO_FUNC225_IN_INV_SEL_S)
-#define GPIO_FUNC225_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC225_IN_INV_SEL_S  6
-/** GPIO_SIG225_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG225_IN_SEL    (BIT(7))
-#define GPIO_SIG225_IN_SEL_M  (GPIO_SIG225_IN_SEL_V << GPIO_SIG225_IN_SEL_S)
-#define GPIO_SIG225_IN_SEL_V  0x00000001U
-#define GPIO_SIG225_IN_SEL_S  7
-
-/** GPIO_FUNC226_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e0)
-/** GPIO_FUNC226_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC226_IN_SEL    0x0000003FU
-#define GPIO_FUNC226_IN_SEL_M  (GPIO_FUNC226_IN_SEL_V << GPIO_FUNC226_IN_SEL_S)
-#define GPIO_FUNC226_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC226_IN_SEL_S  0
-/** GPIO_FUNC226_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC226_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC226_IN_INV_SEL_M  (GPIO_FUNC226_IN_INV_SEL_V << GPIO_FUNC226_IN_INV_SEL_S)
-#define GPIO_FUNC226_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC226_IN_INV_SEL_S  6
-/** GPIO_SIG226_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG226_IN_SEL    (BIT(7))
-#define GPIO_SIG226_IN_SEL_M  (GPIO_SIG226_IN_SEL_V << GPIO_SIG226_IN_SEL_S)
-#define GPIO_SIG226_IN_SEL_V  0x00000001U
-#define GPIO_SIG226_IN_SEL_S  7
-
-/** GPIO_FUNC227_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e4)
-/** GPIO_FUNC227_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC227_IN_SEL    0x0000003FU
-#define GPIO_FUNC227_IN_SEL_M  (GPIO_FUNC227_IN_SEL_V << GPIO_FUNC227_IN_SEL_S)
-#define GPIO_FUNC227_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC227_IN_SEL_S  0
-/** GPIO_FUNC227_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC227_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC227_IN_INV_SEL_M  (GPIO_FUNC227_IN_INV_SEL_V << GPIO_FUNC227_IN_INV_SEL_S)
-#define GPIO_FUNC227_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC227_IN_INV_SEL_S  6
-/** GPIO_SIG227_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG227_IN_SEL    (BIT(7))
-#define GPIO_SIG227_IN_SEL_M  (GPIO_SIG227_IN_SEL_V << GPIO_SIG227_IN_SEL_S)
-#define GPIO_SIG227_IN_SEL_V  0x00000001U
-#define GPIO_SIG227_IN_SEL_S  7
-
-/** GPIO_FUNC228_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e8)
-/** GPIO_FUNC228_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC228_IN_SEL    0x0000003FU
-#define GPIO_FUNC228_IN_SEL_M  (GPIO_FUNC228_IN_SEL_V << GPIO_FUNC228_IN_SEL_S)
-#define GPIO_FUNC228_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC228_IN_SEL_S  0
-/** GPIO_FUNC228_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC228_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC228_IN_INV_SEL_M  (GPIO_FUNC228_IN_INV_SEL_V << GPIO_FUNC228_IN_INV_SEL_S)
-#define GPIO_FUNC228_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC228_IN_INV_SEL_S  6
-/** GPIO_SIG228_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG228_IN_SEL    (BIT(7))
-#define GPIO_SIG228_IN_SEL_M  (GPIO_SIG228_IN_SEL_V << GPIO_SIG228_IN_SEL_S)
-#define GPIO_SIG228_IN_SEL_V  0x00000001U
-#define GPIO_SIG228_IN_SEL_S  7
-
-/** GPIO_FUNC229_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ec)
-/** GPIO_FUNC229_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC229_IN_SEL    0x0000003FU
-#define GPIO_FUNC229_IN_SEL_M  (GPIO_FUNC229_IN_SEL_V << GPIO_FUNC229_IN_SEL_S)
-#define GPIO_FUNC229_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC229_IN_SEL_S  0
-/** GPIO_FUNC229_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC229_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC229_IN_INV_SEL_M  (GPIO_FUNC229_IN_INV_SEL_V << GPIO_FUNC229_IN_INV_SEL_S)
-#define GPIO_FUNC229_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC229_IN_INV_SEL_S  6
-/** GPIO_SIG229_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG229_IN_SEL    (BIT(7))
-#define GPIO_SIG229_IN_SEL_M  (GPIO_SIG229_IN_SEL_V << GPIO_SIG229_IN_SEL_S)
-#define GPIO_SIG229_IN_SEL_V  0x00000001U
-#define GPIO_SIG229_IN_SEL_S  7
-
-/** GPIO_FUNC230_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f0)
-/** GPIO_FUNC230_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC230_IN_SEL    0x0000003FU
-#define GPIO_FUNC230_IN_SEL_M  (GPIO_FUNC230_IN_SEL_V << GPIO_FUNC230_IN_SEL_S)
-#define GPIO_FUNC230_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC230_IN_SEL_S  0
-/** GPIO_FUNC230_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC230_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC230_IN_INV_SEL_M  (GPIO_FUNC230_IN_INV_SEL_V << GPIO_FUNC230_IN_INV_SEL_S)
-#define GPIO_FUNC230_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC230_IN_INV_SEL_S  6
-/** GPIO_SIG230_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG230_IN_SEL    (BIT(7))
-#define GPIO_SIG230_IN_SEL_M  (GPIO_SIG230_IN_SEL_V << GPIO_SIG230_IN_SEL_S)
-#define GPIO_SIG230_IN_SEL_V  0x00000001U
-#define GPIO_SIG230_IN_SEL_S  7
-
-/** GPIO_FUNC231_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f4)
-/** GPIO_FUNC231_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC231_IN_SEL    0x0000003FU
-#define GPIO_FUNC231_IN_SEL_M  (GPIO_FUNC231_IN_SEL_V << GPIO_FUNC231_IN_SEL_S)
-#define GPIO_FUNC231_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC231_IN_SEL_S  0
-/** GPIO_FUNC231_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC231_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC231_IN_INV_SEL_M  (GPIO_FUNC231_IN_INV_SEL_V << GPIO_FUNC231_IN_INV_SEL_S)
-#define GPIO_FUNC231_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC231_IN_INV_SEL_S  6
-/** GPIO_SIG231_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG231_IN_SEL    (BIT(7))
-#define GPIO_SIG231_IN_SEL_M  (GPIO_SIG231_IN_SEL_V << GPIO_SIG231_IN_SEL_S)
-#define GPIO_SIG231_IN_SEL_V  0x00000001U
-#define GPIO_SIG231_IN_SEL_S  7
-
-/** GPIO_FUNC232_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f8)
-/** GPIO_FUNC232_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC232_IN_SEL    0x0000003FU
-#define GPIO_FUNC232_IN_SEL_M  (GPIO_FUNC232_IN_SEL_V << GPIO_FUNC232_IN_SEL_S)
-#define GPIO_FUNC232_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC232_IN_SEL_S  0
-/** GPIO_FUNC232_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC232_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC232_IN_INV_SEL_M  (GPIO_FUNC232_IN_INV_SEL_V << GPIO_FUNC232_IN_INV_SEL_S)
-#define GPIO_FUNC232_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC232_IN_INV_SEL_S  6
-/** GPIO_SIG232_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG232_IN_SEL    (BIT(7))
-#define GPIO_SIG232_IN_SEL_M  (GPIO_SIG232_IN_SEL_V << GPIO_SIG232_IN_SEL_S)
-#define GPIO_SIG232_IN_SEL_V  0x00000001U
-#define GPIO_SIG232_IN_SEL_S  7
-
-/** GPIO_FUNC233_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4fc)
-/** GPIO_FUNC233_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC233_IN_SEL    0x0000003FU
-#define GPIO_FUNC233_IN_SEL_M  (GPIO_FUNC233_IN_SEL_V << GPIO_FUNC233_IN_SEL_S)
-#define GPIO_FUNC233_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC233_IN_SEL_S  0
-/** GPIO_FUNC233_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC233_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC233_IN_INV_SEL_M  (GPIO_FUNC233_IN_INV_SEL_V << GPIO_FUNC233_IN_INV_SEL_S)
-#define GPIO_FUNC233_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC233_IN_INV_SEL_S  6
-/** GPIO_SIG233_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG233_IN_SEL    (BIT(7))
-#define GPIO_SIG233_IN_SEL_M  (GPIO_SIG233_IN_SEL_V << GPIO_SIG233_IN_SEL_S)
-#define GPIO_SIG233_IN_SEL_V  0x00000001U
-#define GPIO_SIG233_IN_SEL_S  7
-
-/** GPIO_FUNC234_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x500)
-/** GPIO_FUNC234_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC234_IN_SEL    0x0000003FU
-#define GPIO_FUNC234_IN_SEL_M  (GPIO_FUNC234_IN_SEL_V << GPIO_FUNC234_IN_SEL_S)
-#define GPIO_FUNC234_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC234_IN_SEL_S  0
-/** GPIO_FUNC234_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC234_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC234_IN_INV_SEL_M  (GPIO_FUNC234_IN_INV_SEL_V << GPIO_FUNC234_IN_INV_SEL_S)
-#define GPIO_FUNC234_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC234_IN_INV_SEL_S  6
-/** GPIO_SIG234_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG234_IN_SEL    (BIT(7))
-#define GPIO_SIG234_IN_SEL_M  (GPIO_SIG234_IN_SEL_V << GPIO_SIG234_IN_SEL_S)
-#define GPIO_SIG234_IN_SEL_V  0x00000001U
-#define GPIO_SIG234_IN_SEL_S  7
-
-/** GPIO_FUNC235_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x504)
-/** GPIO_FUNC235_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC235_IN_SEL    0x0000003FU
-#define GPIO_FUNC235_IN_SEL_M  (GPIO_FUNC235_IN_SEL_V << GPIO_FUNC235_IN_SEL_S)
-#define GPIO_FUNC235_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC235_IN_SEL_S  0
-/** GPIO_FUNC235_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC235_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC235_IN_INV_SEL_M  (GPIO_FUNC235_IN_INV_SEL_V << GPIO_FUNC235_IN_INV_SEL_S)
-#define GPIO_FUNC235_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC235_IN_INV_SEL_S  6
-/** GPIO_SIG235_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG235_IN_SEL    (BIT(7))
-#define GPIO_SIG235_IN_SEL_M  (GPIO_SIG235_IN_SEL_V << GPIO_SIG235_IN_SEL_S)
-#define GPIO_SIG235_IN_SEL_V  0x00000001U
-#define GPIO_SIG235_IN_SEL_S  7
-
-/** GPIO_FUNC236_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x508)
-/** GPIO_FUNC236_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC236_IN_SEL    0x0000003FU
-#define GPIO_FUNC236_IN_SEL_M  (GPIO_FUNC236_IN_SEL_V << GPIO_FUNC236_IN_SEL_S)
-#define GPIO_FUNC236_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC236_IN_SEL_S  0
-/** GPIO_FUNC236_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC236_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC236_IN_INV_SEL_M  (GPIO_FUNC236_IN_INV_SEL_V << GPIO_FUNC236_IN_INV_SEL_S)
-#define GPIO_FUNC236_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC236_IN_INV_SEL_S  6
-/** GPIO_SIG236_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG236_IN_SEL    (BIT(7))
-#define GPIO_SIG236_IN_SEL_M  (GPIO_SIG236_IN_SEL_V << GPIO_SIG236_IN_SEL_S)
-#define GPIO_SIG236_IN_SEL_V  0x00000001U
-#define GPIO_SIG236_IN_SEL_S  7
-
-/** GPIO_FUNC237_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x50c)
-/** GPIO_FUNC237_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC237_IN_SEL    0x0000003FU
-#define GPIO_FUNC237_IN_SEL_M  (GPIO_FUNC237_IN_SEL_V << GPIO_FUNC237_IN_SEL_S)
-#define GPIO_FUNC237_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC237_IN_SEL_S  0
-/** GPIO_FUNC237_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC237_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC237_IN_INV_SEL_M  (GPIO_FUNC237_IN_INV_SEL_V << GPIO_FUNC237_IN_INV_SEL_S)
-#define GPIO_FUNC237_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC237_IN_INV_SEL_S  6
-/** GPIO_SIG237_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG237_IN_SEL    (BIT(7))
-#define GPIO_SIG237_IN_SEL_M  (GPIO_SIG237_IN_SEL_V << GPIO_SIG237_IN_SEL_S)
-#define GPIO_SIG237_IN_SEL_V  0x00000001U
-#define GPIO_SIG237_IN_SEL_S  7
-
-/** GPIO_FUNC238_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x510)
-/** GPIO_FUNC238_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC238_IN_SEL    0x0000003FU
-#define GPIO_FUNC238_IN_SEL_M  (GPIO_FUNC238_IN_SEL_V << GPIO_FUNC238_IN_SEL_S)
-#define GPIO_FUNC238_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC238_IN_SEL_S  0
-/** GPIO_FUNC238_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC238_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC238_IN_INV_SEL_M  (GPIO_FUNC238_IN_INV_SEL_V << GPIO_FUNC238_IN_INV_SEL_S)
-#define GPIO_FUNC238_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC238_IN_INV_SEL_S  6
-/** GPIO_SIG238_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG238_IN_SEL    (BIT(7))
-#define GPIO_SIG238_IN_SEL_M  (GPIO_SIG238_IN_SEL_V << GPIO_SIG238_IN_SEL_S)
-#define GPIO_SIG238_IN_SEL_V  0x00000001U
-#define GPIO_SIG238_IN_SEL_S  7
-
-/** GPIO_FUNC239_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x514)
-/** GPIO_FUNC239_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC239_IN_SEL    0x0000003FU
-#define GPIO_FUNC239_IN_SEL_M  (GPIO_FUNC239_IN_SEL_V << GPIO_FUNC239_IN_SEL_S)
-#define GPIO_FUNC239_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC239_IN_SEL_S  0
-/** GPIO_FUNC239_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC239_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC239_IN_INV_SEL_M  (GPIO_FUNC239_IN_INV_SEL_V << GPIO_FUNC239_IN_INV_SEL_S)
-#define GPIO_FUNC239_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC239_IN_INV_SEL_S  6
-/** GPIO_SIG239_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG239_IN_SEL    (BIT(7))
-#define GPIO_SIG239_IN_SEL_M  (GPIO_SIG239_IN_SEL_V << GPIO_SIG239_IN_SEL_S)
-#define GPIO_SIG239_IN_SEL_V  0x00000001U
-#define GPIO_SIG239_IN_SEL_S  7
-
-/** GPIO_FUNC240_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x518)
-/** GPIO_FUNC240_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC240_IN_SEL    0x0000003FU
-#define GPIO_FUNC240_IN_SEL_M  (GPIO_FUNC240_IN_SEL_V << GPIO_FUNC240_IN_SEL_S)
-#define GPIO_FUNC240_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC240_IN_SEL_S  0
-/** GPIO_FUNC240_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC240_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC240_IN_INV_SEL_M  (GPIO_FUNC240_IN_INV_SEL_V << GPIO_FUNC240_IN_INV_SEL_S)
-#define GPIO_FUNC240_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC240_IN_INV_SEL_S  6
-/** GPIO_SIG240_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG240_IN_SEL    (BIT(7))
-#define GPIO_SIG240_IN_SEL_M  (GPIO_SIG240_IN_SEL_V << GPIO_SIG240_IN_SEL_S)
-#define GPIO_SIG240_IN_SEL_V  0x00000001U
-#define GPIO_SIG240_IN_SEL_S  7
-
-/** GPIO_FUNC241_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x51c)
-/** GPIO_FUNC241_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC241_IN_SEL    0x0000003FU
-#define GPIO_FUNC241_IN_SEL_M  (GPIO_FUNC241_IN_SEL_V << GPIO_FUNC241_IN_SEL_S)
-#define GPIO_FUNC241_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC241_IN_SEL_S  0
-/** GPIO_FUNC241_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC241_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC241_IN_INV_SEL_M  (GPIO_FUNC241_IN_INV_SEL_V << GPIO_FUNC241_IN_INV_SEL_S)
-#define GPIO_FUNC241_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC241_IN_INV_SEL_S  6
-/** GPIO_SIG241_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG241_IN_SEL    (BIT(7))
-#define GPIO_SIG241_IN_SEL_M  (GPIO_SIG241_IN_SEL_V << GPIO_SIG241_IN_SEL_S)
-#define GPIO_SIG241_IN_SEL_V  0x00000001U
-#define GPIO_SIG241_IN_SEL_S  7
-
-/** GPIO_FUNC242_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x520)
-/** GPIO_FUNC242_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC242_IN_SEL    0x0000003FU
-#define GPIO_FUNC242_IN_SEL_M  (GPIO_FUNC242_IN_SEL_V << GPIO_FUNC242_IN_SEL_S)
-#define GPIO_FUNC242_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC242_IN_SEL_S  0
-/** GPIO_FUNC242_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC242_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC242_IN_INV_SEL_M  (GPIO_FUNC242_IN_INV_SEL_V << GPIO_FUNC242_IN_INV_SEL_S)
-#define GPIO_FUNC242_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC242_IN_INV_SEL_S  6
-/** GPIO_SIG242_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG242_IN_SEL    (BIT(7))
-#define GPIO_SIG242_IN_SEL_M  (GPIO_SIG242_IN_SEL_V << GPIO_SIG242_IN_SEL_S)
-#define GPIO_SIG242_IN_SEL_V  0x00000001U
-#define GPIO_SIG242_IN_SEL_S  7
-
-/** GPIO_FUNC243_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x524)
-/** GPIO_FUNC243_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC243_IN_SEL    0x0000003FU
-#define GPIO_FUNC243_IN_SEL_M  (GPIO_FUNC243_IN_SEL_V << GPIO_FUNC243_IN_SEL_S)
-#define GPIO_FUNC243_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC243_IN_SEL_S  0
-/** GPIO_FUNC243_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC243_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC243_IN_INV_SEL_M  (GPIO_FUNC243_IN_INV_SEL_V << GPIO_FUNC243_IN_INV_SEL_S)
-#define GPIO_FUNC243_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC243_IN_INV_SEL_S  6
-/** GPIO_SIG243_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG243_IN_SEL    (BIT(7))
-#define GPIO_SIG243_IN_SEL_M  (GPIO_SIG243_IN_SEL_V << GPIO_SIG243_IN_SEL_S)
-#define GPIO_SIG243_IN_SEL_V  0x00000001U
-#define GPIO_SIG243_IN_SEL_S  7
-
-/** GPIO_FUNC244_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x528)
-/** GPIO_FUNC244_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC244_IN_SEL    0x0000003FU
-#define GPIO_FUNC244_IN_SEL_M  (GPIO_FUNC244_IN_SEL_V << GPIO_FUNC244_IN_SEL_S)
-#define GPIO_FUNC244_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC244_IN_SEL_S  0
-/** GPIO_FUNC244_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC244_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC244_IN_INV_SEL_M  (GPIO_FUNC244_IN_INV_SEL_V << GPIO_FUNC244_IN_INV_SEL_S)
-#define GPIO_FUNC244_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC244_IN_INV_SEL_S  6
-/** GPIO_SIG244_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG244_IN_SEL    (BIT(7))
-#define GPIO_SIG244_IN_SEL_M  (GPIO_SIG244_IN_SEL_V << GPIO_SIG244_IN_SEL_S)
-#define GPIO_SIG244_IN_SEL_V  0x00000001U
-#define GPIO_SIG244_IN_SEL_S  7
-
-/** GPIO_FUNC245_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x52c)
-/** GPIO_FUNC245_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC245_IN_SEL    0x0000003FU
-#define GPIO_FUNC245_IN_SEL_M  (GPIO_FUNC245_IN_SEL_V << GPIO_FUNC245_IN_SEL_S)
-#define GPIO_FUNC245_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC245_IN_SEL_S  0
-/** GPIO_FUNC245_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC245_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC245_IN_INV_SEL_M  (GPIO_FUNC245_IN_INV_SEL_V << GPIO_FUNC245_IN_INV_SEL_S)
-#define GPIO_FUNC245_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC245_IN_INV_SEL_S  6
-/** GPIO_SIG245_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG245_IN_SEL    (BIT(7))
-#define GPIO_SIG245_IN_SEL_M  (GPIO_SIG245_IN_SEL_V << GPIO_SIG245_IN_SEL_S)
-#define GPIO_SIG245_IN_SEL_V  0x00000001U
-#define GPIO_SIG245_IN_SEL_S  7
-
-/** GPIO_FUNC246_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x530)
-/** GPIO_FUNC246_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC246_IN_SEL    0x0000003FU
-#define GPIO_FUNC246_IN_SEL_M  (GPIO_FUNC246_IN_SEL_V << GPIO_FUNC246_IN_SEL_S)
-#define GPIO_FUNC246_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC246_IN_SEL_S  0
-/** GPIO_FUNC246_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC246_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC246_IN_INV_SEL_M  (GPIO_FUNC246_IN_INV_SEL_V << GPIO_FUNC246_IN_INV_SEL_S)
-#define GPIO_FUNC246_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC246_IN_INV_SEL_S  6
-/** GPIO_SIG246_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG246_IN_SEL    (BIT(7))
-#define GPIO_SIG246_IN_SEL_M  (GPIO_SIG246_IN_SEL_V << GPIO_SIG246_IN_SEL_S)
-#define GPIO_SIG246_IN_SEL_V  0x00000001U
-#define GPIO_SIG246_IN_SEL_S  7
-
-/** GPIO_FUNC247_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x534)
-/** GPIO_FUNC247_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC247_IN_SEL    0x0000003FU
-#define GPIO_FUNC247_IN_SEL_M  (GPIO_FUNC247_IN_SEL_V << GPIO_FUNC247_IN_SEL_S)
-#define GPIO_FUNC247_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC247_IN_SEL_S  0
-/** GPIO_FUNC247_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC247_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC247_IN_INV_SEL_M  (GPIO_FUNC247_IN_INV_SEL_V << GPIO_FUNC247_IN_INV_SEL_S)
-#define GPIO_FUNC247_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC247_IN_INV_SEL_S  6
-/** GPIO_SIG247_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG247_IN_SEL    (BIT(7))
-#define GPIO_SIG247_IN_SEL_M  (GPIO_SIG247_IN_SEL_V << GPIO_SIG247_IN_SEL_S)
-#define GPIO_SIG247_IN_SEL_V  0x00000001U
-#define GPIO_SIG247_IN_SEL_S  7
-
-/** GPIO_FUNC248_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x538)
-/** GPIO_FUNC248_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC248_IN_SEL    0x0000003FU
-#define GPIO_FUNC248_IN_SEL_M  (GPIO_FUNC248_IN_SEL_V << GPIO_FUNC248_IN_SEL_S)
-#define GPIO_FUNC248_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC248_IN_SEL_S  0
-/** GPIO_FUNC248_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC248_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC248_IN_INV_SEL_M  (GPIO_FUNC248_IN_INV_SEL_V << GPIO_FUNC248_IN_INV_SEL_S)
-#define GPIO_FUNC248_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC248_IN_INV_SEL_S  6
-/** GPIO_SIG248_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG248_IN_SEL    (BIT(7))
-#define GPIO_SIG248_IN_SEL_M  (GPIO_SIG248_IN_SEL_V << GPIO_SIG248_IN_SEL_S)
-#define GPIO_SIG248_IN_SEL_V  0x00000001U
-#define GPIO_SIG248_IN_SEL_S  7
-
-/** GPIO_FUNC249_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x53c)
-/** GPIO_FUNC249_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC249_IN_SEL    0x0000003FU
-#define GPIO_FUNC249_IN_SEL_M  (GPIO_FUNC249_IN_SEL_V << GPIO_FUNC249_IN_SEL_S)
-#define GPIO_FUNC249_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC249_IN_SEL_S  0
-/** GPIO_FUNC249_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC249_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC249_IN_INV_SEL_M  (GPIO_FUNC249_IN_INV_SEL_V << GPIO_FUNC249_IN_INV_SEL_S)
-#define GPIO_FUNC249_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC249_IN_INV_SEL_S  6
-/** GPIO_SIG249_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG249_IN_SEL    (BIT(7))
-#define GPIO_SIG249_IN_SEL_M  (GPIO_SIG249_IN_SEL_V << GPIO_SIG249_IN_SEL_S)
-#define GPIO_SIG249_IN_SEL_V  0x00000001U
-#define GPIO_SIG249_IN_SEL_S  7
-
-/** GPIO_FUNC250_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x540)
-/** GPIO_FUNC250_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC250_IN_SEL    0x0000003FU
-#define GPIO_FUNC250_IN_SEL_M  (GPIO_FUNC250_IN_SEL_V << GPIO_FUNC250_IN_SEL_S)
-#define GPIO_FUNC250_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC250_IN_SEL_S  0
-/** GPIO_FUNC250_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC250_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC250_IN_INV_SEL_M  (GPIO_FUNC250_IN_INV_SEL_V << GPIO_FUNC250_IN_INV_SEL_S)
-#define GPIO_FUNC250_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC250_IN_INV_SEL_S  6
-/** GPIO_SIG250_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG250_IN_SEL    (BIT(7))
-#define GPIO_SIG250_IN_SEL_M  (GPIO_SIG250_IN_SEL_V << GPIO_SIG250_IN_SEL_S)
-#define GPIO_SIG250_IN_SEL_V  0x00000001U
-#define GPIO_SIG250_IN_SEL_S  7
-
-/** GPIO_FUNC251_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x544)
-/** GPIO_FUNC251_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC251_IN_SEL    0x0000003FU
-#define GPIO_FUNC251_IN_SEL_M  (GPIO_FUNC251_IN_SEL_V << GPIO_FUNC251_IN_SEL_S)
-#define GPIO_FUNC251_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC251_IN_SEL_S  0
-/** GPIO_FUNC251_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC251_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC251_IN_INV_SEL_M  (GPIO_FUNC251_IN_INV_SEL_V << GPIO_FUNC251_IN_INV_SEL_S)
-#define GPIO_FUNC251_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC251_IN_INV_SEL_S  6
-/** GPIO_SIG251_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG251_IN_SEL    (BIT(7))
-#define GPIO_SIG251_IN_SEL_M  (GPIO_SIG251_IN_SEL_V << GPIO_SIG251_IN_SEL_S)
-#define GPIO_SIG251_IN_SEL_V  0x00000001U
-#define GPIO_SIG251_IN_SEL_S  7
-
-/** GPIO_FUNC252_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x548)
-/** GPIO_FUNC252_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC252_IN_SEL    0x0000003FU
-#define GPIO_FUNC252_IN_SEL_M  (GPIO_FUNC252_IN_SEL_V << GPIO_FUNC252_IN_SEL_S)
-#define GPIO_FUNC252_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC252_IN_SEL_S  0
-/** GPIO_FUNC252_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC252_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC252_IN_INV_SEL_M  (GPIO_FUNC252_IN_INV_SEL_V << GPIO_FUNC252_IN_INV_SEL_S)
-#define GPIO_FUNC252_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC252_IN_INV_SEL_S  6
-/** GPIO_SIG252_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG252_IN_SEL    (BIT(7))
-#define GPIO_SIG252_IN_SEL_M  (GPIO_SIG252_IN_SEL_V << GPIO_SIG252_IN_SEL_S)
-#define GPIO_SIG252_IN_SEL_V  0x00000001U
-#define GPIO_SIG252_IN_SEL_S  7
-
-/** GPIO_FUNC253_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x54c)
-/** GPIO_FUNC253_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC253_IN_SEL    0x0000003FU
-#define GPIO_FUNC253_IN_SEL_M  (GPIO_FUNC253_IN_SEL_V << GPIO_FUNC253_IN_SEL_S)
-#define GPIO_FUNC253_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC253_IN_SEL_S  0
-/** GPIO_FUNC253_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC253_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC253_IN_INV_SEL_M  (GPIO_FUNC253_IN_INV_SEL_V << GPIO_FUNC253_IN_INV_SEL_S)
-#define GPIO_FUNC253_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC253_IN_INV_SEL_S  6
-/** GPIO_SIG253_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG253_IN_SEL    (BIT(7))
-#define GPIO_SIG253_IN_SEL_M  (GPIO_SIG253_IN_SEL_V << GPIO_SIG253_IN_SEL_S)
-#define GPIO_SIG253_IN_SEL_V  0x00000001U
-#define GPIO_SIG253_IN_SEL_S  7
-
-/** GPIO_FUNC254_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x550)
-/** GPIO_FUNC254_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC254_IN_SEL    0x0000003FU
-#define GPIO_FUNC254_IN_SEL_M  (GPIO_FUNC254_IN_SEL_V << GPIO_FUNC254_IN_SEL_S)
-#define GPIO_FUNC254_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC254_IN_SEL_S  0
-/** GPIO_FUNC254_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC254_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC254_IN_INV_SEL_M  (GPIO_FUNC254_IN_INV_SEL_V << GPIO_FUNC254_IN_INV_SEL_S)
-#define GPIO_FUNC254_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC254_IN_INV_SEL_S  6
-/** GPIO_SIG254_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG254_IN_SEL    (BIT(7))
-#define GPIO_SIG254_IN_SEL_M  (GPIO_SIG254_IN_SEL_V << GPIO_SIG254_IN_SEL_S)
-#define GPIO_SIG254_IN_SEL_V  0x00000001U
-#define GPIO_SIG254_IN_SEL_S  7
-
-/** GPIO_FUNC255_IN_SEL_CFG_REG register
- *  GPIO input function configuration register
- */
-#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554)
-/** GPIO_FUNC255_IN_SEL : R/W; bitpos: [5:0]; default: 62;
- *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
- *  high level. s=0x3E: set this port always low level.
- */
-#define GPIO_FUNC255_IN_SEL    0x0000003FU
-#define GPIO_FUNC255_IN_SEL_M  (GPIO_FUNC255_IN_SEL_V << GPIO_FUNC255_IN_SEL_S)
-#define GPIO_FUNC255_IN_SEL_V  0x0000003FU
-#define GPIO_FUNC255_IN_SEL_S  0
-/** GPIO_FUNC255_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
- *  set this bit to invert input signal. 1:invert. 0:not invert.
- */
-#define GPIO_FUNC255_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC255_IN_INV_SEL_M  (GPIO_FUNC255_IN_INV_SEL_V << GPIO_FUNC255_IN_INV_SEL_S)
-#define GPIO_FUNC255_IN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC255_IN_INV_SEL_S  6
-/** GPIO_SIG255_IN_SEL : R/W; bitpos: [7]; default: 0;
- *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
- */
-#define GPIO_SIG255_IN_SEL    (BIT(7))
-#define GPIO_SIG255_IN_SEL_M  (GPIO_SIG255_IN_SEL_V << GPIO_SIG255_IN_SEL_S)
-#define GPIO_SIG255_IN_SEL_V  0x00000001U
-#define GPIO_SIG255_IN_SEL_S  7
-
-/** GPIO_FUNC0_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558)
-/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC0_OUT_SEL    0x000001FFU
-#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
-#define GPIO_FUNC0_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC0_OUT_SEL_S  0
-/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
-#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC0_OUT_INV_SEL_S  9
-/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC0_OEN_SEL    (BIT(10))
-#define GPIO_FUNC0_OEN_SEL_M  (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S)
-#define GPIO_FUNC0_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC0_OEN_SEL_S  10
-/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC0_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC0_OEN_INV_SEL_M  (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S)
-#define GPIO_FUNC0_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC0_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC1_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c)
-/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC1_OUT_SEL    0x000001FFU
-#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
-#define GPIO_FUNC1_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC1_OUT_SEL_S  0
-/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
-#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC1_OUT_INV_SEL_S  9
-/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC1_OEN_SEL    (BIT(10))
-#define GPIO_FUNC1_OEN_SEL_M  (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S)
-#define GPIO_FUNC1_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC1_OEN_SEL_S  10
-/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC1_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC1_OEN_INV_SEL_M  (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S)
-#define GPIO_FUNC1_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC1_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC2_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560)
-/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC2_OUT_SEL    0x000001FFU
-#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
-#define GPIO_FUNC2_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC2_OUT_SEL_S  0
-/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
-#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC2_OUT_INV_SEL_S  9
-/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC2_OEN_SEL    (BIT(10))
-#define GPIO_FUNC2_OEN_SEL_M  (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S)
-#define GPIO_FUNC2_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC2_OEN_SEL_S  10
-/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC2_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC2_OEN_INV_SEL_M  (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S)
-#define GPIO_FUNC2_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC2_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC3_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564)
-/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC3_OUT_SEL    0x000001FFU
-#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
-#define GPIO_FUNC3_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC3_OUT_SEL_S  0
-/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
-#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC3_OUT_INV_SEL_S  9
-/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC3_OEN_SEL    (BIT(10))
-#define GPIO_FUNC3_OEN_SEL_M  (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S)
-#define GPIO_FUNC3_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC3_OEN_SEL_S  10
-/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC3_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC3_OEN_INV_SEL_M  (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S)
-#define GPIO_FUNC3_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC3_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC4_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568)
-/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC4_OUT_SEL    0x000001FFU
-#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
-#define GPIO_FUNC4_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC4_OUT_SEL_S  0
-/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
-#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC4_OUT_INV_SEL_S  9
-/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC4_OEN_SEL    (BIT(10))
-#define GPIO_FUNC4_OEN_SEL_M  (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S)
-#define GPIO_FUNC4_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC4_OEN_SEL_S  10
-/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC4_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC4_OEN_INV_SEL_M  (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S)
-#define GPIO_FUNC4_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC4_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC5_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c)
-/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC5_OUT_SEL    0x000001FFU
-#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
-#define GPIO_FUNC5_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC5_OUT_SEL_S  0
-/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
-#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC5_OUT_INV_SEL_S  9
-/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC5_OEN_SEL    (BIT(10))
-#define GPIO_FUNC5_OEN_SEL_M  (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S)
-#define GPIO_FUNC5_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC5_OEN_SEL_S  10
-/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC5_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC5_OEN_INV_SEL_M  (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S)
-#define GPIO_FUNC5_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC5_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC6_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570)
-/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC6_OUT_SEL    0x000001FFU
-#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
-#define GPIO_FUNC6_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC6_OUT_SEL_S  0
-/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
-#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_OUT_INV_SEL_S  9
-/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC6_OEN_SEL    (BIT(10))
-#define GPIO_FUNC6_OEN_SEL_M  (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S)
-#define GPIO_FUNC6_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC6_OEN_SEL_S  10
-/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC6_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC6_OEN_INV_SEL_M  (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S)
-#define GPIO_FUNC6_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC6_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC7_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574)
-/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC7_OUT_SEL    0x000001FFU
-#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
-#define GPIO_FUNC7_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC7_OUT_SEL_S  0
-/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
-#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_OUT_INV_SEL_S  9
-/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC7_OEN_SEL    (BIT(10))
-#define GPIO_FUNC7_OEN_SEL_M  (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S)
-#define GPIO_FUNC7_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC7_OEN_SEL_S  10
-/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC7_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC7_OEN_INV_SEL_M  (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S)
-#define GPIO_FUNC7_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC7_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC8_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578)
-/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC8_OUT_SEL    0x000001FFU
-#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
-#define GPIO_FUNC8_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC8_OUT_SEL_S  0
-/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
-#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_OUT_INV_SEL_S  9
-/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC8_OEN_SEL    (BIT(10))
-#define GPIO_FUNC8_OEN_SEL_M  (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S)
-#define GPIO_FUNC8_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC8_OEN_SEL_S  10
-/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC8_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC8_OEN_INV_SEL_M  (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S)
-#define GPIO_FUNC8_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC8_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC9_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c)
-/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC9_OUT_SEL    0x000001FFU
-#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
-#define GPIO_FUNC9_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC9_OUT_SEL_S  0
-/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
-#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_OUT_INV_SEL_S  9
-/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC9_OEN_SEL    (BIT(10))
-#define GPIO_FUNC9_OEN_SEL_M  (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S)
-#define GPIO_FUNC9_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC9_OEN_SEL_S  10
-/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC9_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC9_OEN_INV_SEL_M  (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S)
-#define GPIO_FUNC9_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC9_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC10_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580)
-/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC10_OUT_SEL    0x000001FFU
-#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
-#define GPIO_FUNC10_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC10_OUT_SEL_S  0
-/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
-#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_OUT_INV_SEL_S  9
-/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC10_OEN_SEL    (BIT(10))
-#define GPIO_FUNC10_OEN_SEL_M  (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S)
-#define GPIO_FUNC10_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC10_OEN_SEL_S  10
-/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC10_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC10_OEN_INV_SEL_M  (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S)
-#define GPIO_FUNC10_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC10_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC11_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584)
-/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC11_OUT_SEL    0x000001FFU
-#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
-#define GPIO_FUNC11_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC11_OUT_SEL_S  0
-/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
-#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_OUT_INV_SEL_S  9
-/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC11_OEN_SEL    (BIT(10))
-#define GPIO_FUNC11_OEN_SEL_M  (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S)
-#define GPIO_FUNC11_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC11_OEN_SEL_S  10
-/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC11_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC11_OEN_INV_SEL_M  (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S)
-#define GPIO_FUNC11_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC11_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC12_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588)
-/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC12_OUT_SEL    0x000001FFU
-#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
-#define GPIO_FUNC12_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC12_OUT_SEL_S  0
-/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
-#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_OUT_INV_SEL_S  9
-/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC12_OEN_SEL    (BIT(10))
-#define GPIO_FUNC12_OEN_SEL_M  (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S)
-#define GPIO_FUNC12_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC12_OEN_SEL_S  10
-/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC12_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC12_OEN_INV_SEL_M  (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S)
-#define GPIO_FUNC12_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC12_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC13_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c)
-/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC13_OUT_SEL    0x000001FFU
-#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
-#define GPIO_FUNC13_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC13_OUT_SEL_S  0
-/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
-#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_OUT_INV_SEL_S  9
-/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC13_OEN_SEL    (BIT(10))
-#define GPIO_FUNC13_OEN_SEL_M  (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S)
-#define GPIO_FUNC13_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC13_OEN_SEL_S  10
-/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC13_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC13_OEN_INV_SEL_M  (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S)
-#define GPIO_FUNC13_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC13_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC14_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590)
-/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC14_OUT_SEL    0x000001FFU
-#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
-#define GPIO_FUNC14_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC14_OUT_SEL_S  0
-/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
-#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_OUT_INV_SEL_S  9
-/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC14_OEN_SEL    (BIT(10))
-#define GPIO_FUNC14_OEN_SEL_M  (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S)
-#define GPIO_FUNC14_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC14_OEN_SEL_S  10
-/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC14_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC14_OEN_INV_SEL_M  (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S)
-#define GPIO_FUNC14_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC14_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC15_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594)
-/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC15_OUT_SEL    0x000001FFU
-#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
-#define GPIO_FUNC15_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC15_OUT_SEL_S  0
-/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
-#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_OUT_INV_SEL_S  9
-/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC15_OEN_SEL    (BIT(10))
-#define GPIO_FUNC15_OEN_SEL_M  (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S)
-#define GPIO_FUNC15_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC15_OEN_SEL_S  10
-/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC15_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC15_OEN_INV_SEL_M  (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S)
-#define GPIO_FUNC15_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC15_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC16_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598)
-/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC16_OUT_SEL    0x000001FFU
-#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
-#define GPIO_FUNC16_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC16_OUT_SEL_S  0
-/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
-#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_OUT_INV_SEL_S  9
-/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC16_OEN_SEL    (BIT(10))
-#define GPIO_FUNC16_OEN_SEL_M  (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S)
-#define GPIO_FUNC16_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC16_OEN_SEL_S  10
-/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC16_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC16_OEN_INV_SEL_M  (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S)
-#define GPIO_FUNC16_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC16_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC17_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c)
-/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC17_OUT_SEL    0x000001FFU
-#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
-#define GPIO_FUNC17_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC17_OUT_SEL_S  0
-/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
-#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_OUT_INV_SEL_S  9
-/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC17_OEN_SEL    (BIT(10))
-#define GPIO_FUNC17_OEN_SEL_M  (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S)
-#define GPIO_FUNC17_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC17_OEN_SEL_S  10
-/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC17_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC17_OEN_INV_SEL_M  (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S)
-#define GPIO_FUNC17_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC17_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC18_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0)
-/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC18_OUT_SEL    0x000001FFU
-#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
-#define GPIO_FUNC18_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC18_OUT_SEL_S  0
-/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
-#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC18_OUT_INV_SEL_S  9
-/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC18_OEN_SEL    (BIT(10))
-#define GPIO_FUNC18_OEN_SEL_M  (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S)
-#define GPIO_FUNC18_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC18_OEN_SEL_S  10
-/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC18_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC18_OEN_INV_SEL_M  (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S)
-#define GPIO_FUNC18_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC18_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC19_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4)
-/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC19_OUT_SEL    0x000001FFU
-#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
-#define GPIO_FUNC19_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC19_OUT_SEL_S  0
-/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
-#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC19_OUT_INV_SEL_S  9
-/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC19_OEN_SEL    (BIT(10))
-#define GPIO_FUNC19_OEN_SEL_M  (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S)
-#define GPIO_FUNC19_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC19_OEN_SEL_S  10
-/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC19_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC19_OEN_INV_SEL_M  (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S)
-#define GPIO_FUNC19_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC19_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC20_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8)
-/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC20_OUT_SEL    0x000001FFU
-#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
-#define GPIO_FUNC20_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC20_OUT_SEL_S  0
-/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
-#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC20_OUT_INV_SEL_S  9
-/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC20_OEN_SEL    (BIT(10))
-#define GPIO_FUNC20_OEN_SEL_M  (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S)
-#define GPIO_FUNC20_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC20_OEN_SEL_S  10
-/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC20_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC20_OEN_INV_SEL_M  (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S)
-#define GPIO_FUNC20_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC20_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC21_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac)
-/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC21_OUT_SEL    0x000001FFU
-#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
-#define GPIO_FUNC21_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC21_OUT_SEL_S  0
-/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
-#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC21_OUT_INV_SEL_S  9
-/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC21_OEN_SEL    (BIT(10))
-#define GPIO_FUNC21_OEN_SEL_M  (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S)
-#define GPIO_FUNC21_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC21_OEN_SEL_S  10
-/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC21_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC21_OEN_INV_SEL_M  (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S)
-#define GPIO_FUNC21_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC21_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC22_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0)
-/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC22_OUT_SEL    0x000001FFU
-#define GPIO_FUNC22_OUT_SEL_M  (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
-#define GPIO_FUNC22_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC22_OUT_SEL_S  0
-/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC22_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC22_OUT_INV_SEL_M  (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
-#define GPIO_FUNC22_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC22_OUT_INV_SEL_S  9
-/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC22_OEN_SEL    (BIT(10))
-#define GPIO_FUNC22_OEN_SEL_M  (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S)
-#define GPIO_FUNC22_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC22_OEN_SEL_S  10
-/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC22_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC22_OEN_INV_SEL_M  (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S)
-#define GPIO_FUNC22_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC22_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC23_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4)
-/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC23_OUT_SEL    0x000001FFU
-#define GPIO_FUNC23_OUT_SEL_M  (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
-#define GPIO_FUNC23_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC23_OUT_SEL_S  0
-/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC23_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC23_OUT_INV_SEL_M  (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
-#define GPIO_FUNC23_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC23_OUT_INV_SEL_S  9
-/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC23_OEN_SEL    (BIT(10))
-#define GPIO_FUNC23_OEN_SEL_M  (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S)
-#define GPIO_FUNC23_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC23_OEN_SEL_S  10
-/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC23_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC23_OEN_INV_SEL_M  (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S)
-#define GPIO_FUNC23_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC23_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC24_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8)
-/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC24_OUT_SEL    0x000001FFU
-#define GPIO_FUNC24_OUT_SEL_M  (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
-#define GPIO_FUNC24_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC24_OUT_SEL_S  0
-/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC24_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC24_OUT_INV_SEL_M  (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
-#define GPIO_FUNC24_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC24_OUT_INV_SEL_S  9
-/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC24_OEN_SEL    (BIT(10))
-#define GPIO_FUNC24_OEN_SEL_M  (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S)
-#define GPIO_FUNC24_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC24_OEN_SEL_S  10
-/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC24_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC24_OEN_INV_SEL_M  (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S)
-#define GPIO_FUNC24_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC24_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC25_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc)
-/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC25_OUT_SEL    0x000001FFU
-#define GPIO_FUNC25_OUT_SEL_M  (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S)
-#define GPIO_FUNC25_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC25_OUT_SEL_S  0
-/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC25_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC25_OUT_INV_SEL_M  (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S)
-#define GPIO_FUNC25_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC25_OUT_INV_SEL_S  9
-/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC25_OEN_SEL    (BIT(10))
-#define GPIO_FUNC25_OEN_SEL_M  (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S)
-#define GPIO_FUNC25_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC25_OEN_SEL_S  10
-/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC25_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC25_OEN_INV_SEL_M  (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S)
-#define GPIO_FUNC25_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC25_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC26_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0)
-/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC26_OUT_SEL    0x000001FFU
-#define GPIO_FUNC26_OUT_SEL_M  (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S)
-#define GPIO_FUNC26_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC26_OUT_SEL_S  0
-/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC26_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC26_OUT_INV_SEL_M  (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S)
-#define GPIO_FUNC26_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC26_OUT_INV_SEL_S  9
-/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC26_OEN_SEL    (BIT(10))
-#define GPIO_FUNC26_OEN_SEL_M  (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S)
-#define GPIO_FUNC26_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC26_OEN_SEL_S  10
-/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC26_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC26_OEN_INV_SEL_M  (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S)
-#define GPIO_FUNC26_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC26_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC27_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4)
-/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC27_OUT_SEL    0x000001FFU
-#define GPIO_FUNC27_OUT_SEL_M  (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S)
-#define GPIO_FUNC27_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC27_OUT_SEL_S  0
-/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC27_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC27_OUT_INV_SEL_M  (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S)
-#define GPIO_FUNC27_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC27_OUT_INV_SEL_S  9
-/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC27_OEN_SEL    (BIT(10))
-#define GPIO_FUNC27_OEN_SEL_M  (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S)
-#define GPIO_FUNC27_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC27_OEN_SEL_S  10
-/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC27_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC27_OEN_INV_SEL_M  (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S)
-#define GPIO_FUNC27_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC27_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC28_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8)
-/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC28_OUT_SEL    0x000001FFU
-#define GPIO_FUNC28_OUT_SEL_M  (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
-#define GPIO_FUNC28_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC28_OUT_SEL_S  0
-/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC28_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC28_OUT_INV_SEL_M  (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S)
-#define GPIO_FUNC28_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC28_OUT_INV_SEL_S  9
-/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC28_OEN_SEL    (BIT(10))
-#define GPIO_FUNC28_OEN_SEL_M  (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S)
-#define GPIO_FUNC28_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC28_OEN_SEL_S  10
-/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC28_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC28_OEN_INV_SEL_M  (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S)
-#define GPIO_FUNC28_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC28_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC29_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc)
-/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC29_OUT_SEL    0x000001FFU
-#define GPIO_FUNC29_OUT_SEL_M  (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S)
-#define GPIO_FUNC29_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC29_OUT_SEL_S  0
-/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC29_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC29_OUT_INV_SEL_M  (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S)
-#define GPIO_FUNC29_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC29_OUT_INV_SEL_S  9
-/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC29_OEN_SEL    (BIT(10))
-#define GPIO_FUNC29_OEN_SEL_M  (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S)
-#define GPIO_FUNC29_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC29_OEN_SEL_S  10
-/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC29_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC29_OEN_INV_SEL_M  (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S)
-#define GPIO_FUNC29_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC29_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC30_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0)
-/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC30_OUT_SEL    0x000001FFU
-#define GPIO_FUNC30_OUT_SEL_M  (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S)
-#define GPIO_FUNC30_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC30_OUT_SEL_S  0
-/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC30_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC30_OUT_INV_SEL_M  (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S)
-#define GPIO_FUNC30_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC30_OUT_INV_SEL_S  9
-/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC30_OEN_SEL    (BIT(10))
-#define GPIO_FUNC30_OEN_SEL_M  (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S)
-#define GPIO_FUNC30_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC30_OEN_SEL_S  10
-/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC30_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC30_OEN_INV_SEL_M  (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S)
-#define GPIO_FUNC30_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC30_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC31_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4)
-/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC31_OUT_SEL    0x000001FFU
-#define GPIO_FUNC31_OUT_SEL_M  (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S)
-#define GPIO_FUNC31_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC31_OUT_SEL_S  0
-/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC31_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC31_OUT_INV_SEL_M  (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S)
-#define GPIO_FUNC31_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC31_OUT_INV_SEL_S  9
-/** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC31_OEN_SEL    (BIT(10))
-#define GPIO_FUNC31_OEN_SEL_M  (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S)
-#define GPIO_FUNC31_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC31_OEN_SEL_S  10
-/** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC31_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC31_OEN_INV_SEL_M  (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S)
-#define GPIO_FUNC31_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC31_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC32_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8)
-/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC32_OUT_SEL    0x000001FFU
-#define GPIO_FUNC32_OUT_SEL_M  (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S)
-#define GPIO_FUNC32_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC32_OUT_SEL_S  0
-/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC32_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC32_OUT_INV_SEL_M  (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S)
-#define GPIO_FUNC32_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC32_OUT_INV_SEL_S  9
-/** GPIO_FUNC32_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC32_OEN_SEL    (BIT(10))
-#define GPIO_FUNC32_OEN_SEL_M  (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S)
-#define GPIO_FUNC32_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC32_OEN_SEL_S  10
-/** GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC32_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC32_OEN_INV_SEL_M  (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S)
-#define GPIO_FUNC32_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC32_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC33_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc)
-/** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC33_OUT_SEL    0x000001FFU
-#define GPIO_FUNC33_OUT_SEL_M  (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S)
-#define GPIO_FUNC33_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC33_OUT_SEL_S  0
-/** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC33_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC33_OUT_INV_SEL_M  (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S)
-#define GPIO_FUNC33_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC33_OUT_INV_SEL_S  9
-/** GPIO_FUNC33_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC33_OEN_SEL    (BIT(10))
-#define GPIO_FUNC33_OEN_SEL_M  (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S)
-#define GPIO_FUNC33_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC33_OEN_SEL_S  10
-/** GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC33_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC33_OEN_INV_SEL_M  (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S)
-#define GPIO_FUNC33_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC33_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC34_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0)
-/** GPIO_FUNC34_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC34_OUT_SEL    0x000001FFU
-#define GPIO_FUNC34_OUT_SEL_M  (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S)
-#define GPIO_FUNC34_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC34_OUT_SEL_S  0
-/** GPIO_FUNC34_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC34_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC34_OUT_INV_SEL_M  (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S)
-#define GPIO_FUNC34_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC34_OUT_INV_SEL_S  9
-/** GPIO_FUNC34_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC34_OEN_SEL    (BIT(10))
-#define GPIO_FUNC34_OEN_SEL_M  (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S)
-#define GPIO_FUNC34_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC34_OEN_SEL_S  10
-/** GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC34_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC34_OEN_INV_SEL_M  (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S)
-#define GPIO_FUNC34_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC34_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC35_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4)
-/** GPIO_FUNC35_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC35_OUT_SEL    0x000001FFU
-#define GPIO_FUNC35_OUT_SEL_M  (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S)
-#define GPIO_FUNC35_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC35_OUT_SEL_S  0
-/** GPIO_FUNC35_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC35_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC35_OUT_INV_SEL_M  (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S)
-#define GPIO_FUNC35_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC35_OUT_INV_SEL_S  9
-/** GPIO_FUNC35_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC35_OEN_SEL    (BIT(10))
-#define GPIO_FUNC35_OEN_SEL_M  (GPIO_FUNC35_OEN_SEL_V << GPIO_FUNC35_OEN_SEL_S)
-#define GPIO_FUNC35_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC35_OEN_SEL_S  10
-/** GPIO_FUNC35_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC35_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC35_OEN_INV_SEL_M  (GPIO_FUNC35_OEN_INV_SEL_V << GPIO_FUNC35_OEN_INV_SEL_S)
-#define GPIO_FUNC35_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC35_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC36_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8)
-/** GPIO_FUNC36_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC36_OUT_SEL    0x000001FFU
-#define GPIO_FUNC36_OUT_SEL_M  (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S)
-#define GPIO_FUNC36_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC36_OUT_SEL_S  0
-/** GPIO_FUNC36_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC36_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC36_OUT_INV_SEL_M  (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S)
-#define GPIO_FUNC36_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC36_OUT_INV_SEL_S  9
-/** GPIO_FUNC36_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC36_OEN_SEL    (BIT(10))
-#define GPIO_FUNC36_OEN_SEL_M  (GPIO_FUNC36_OEN_SEL_V << GPIO_FUNC36_OEN_SEL_S)
-#define GPIO_FUNC36_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC36_OEN_SEL_S  10
-/** GPIO_FUNC36_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC36_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC36_OEN_INV_SEL_M  (GPIO_FUNC36_OEN_INV_SEL_V << GPIO_FUNC36_OEN_INV_SEL_S)
-#define GPIO_FUNC36_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC36_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC37_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec)
-/** GPIO_FUNC37_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC37_OUT_SEL    0x000001FFU
-#define GPIO_FUNC37_OUT_SEL_M  (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S)
-#define GPIO_FUNC37_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC37_OUT_SEL_S  0
-/** GPIO_FUNC37_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC37_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC37_OUT_INV_SEL_M  (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S)
-#define GPIO_FUNC37_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC37_OUT_INV_SEL_S  9
-/** GPIO_FUNC37_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC37_OEN_SEL    (BIT(10))
-#define GPIO_FUNC37_OEN_SEL_M  (GPIO_FUNC37_OEN_SEL_V << GPIO_FUNC37_OEN_SEL_S)
-#define GPIO_FUNC37_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC37_OEN_SEL_S  10
-/** GPIO_FUNC37_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC37_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC37_OEN_INV_SEL_M  (GPIO_FUNC37_OEN_INV_SEL_V << GPIO_FUNC37_OEN_INV_SEL_S)
-#define GPIO_FUNC37_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC37_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC38_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0)
-/** GPIO_FUNC38_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC38_OUT_SEL    0x000001FFU
-#define GPIO_FUNC38_OUT_SEL_M  (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S)
-#define GPIO_FUNC38_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC38_OUT_SEL_S  0
-/** GPIO_FUNC38_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC38_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC38_OUT_INV_SEL_M  (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S)
-#define GPIO_FUNC38_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC38_OUT_INV_SEL_S  9
-/** GPIO_FUNC38_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC38_OEN_SEL    (BIT(10))
-#define GPIO_FUNC38_OEN_SEL_M  (GPIO_FUNC38_OEN_SEL_V << GPIO_FUNC38_OEN_SEL_S)
-#define GPIO_FUNC38_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC38_OEN_SEL_S  10
-/** GPIO_FUNC38_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC38_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC38_OEN_INV_SEL_M  (GPIO_FUNC38_OEN_INV_SEL_V << GPIO_FUNC38_OEN_INV_SEL_S)
-#define GPIO_FUNC38_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC38_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC39_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4)
-/** GPIO_FUNC39_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC39_OUT_SEL    0x000001FFU
-#define GPIO_FUNC39_OUT_SEL_M  (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S)
-#define GPIO_FUNC39_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC39_OUT_SEL_S  0
-/** GPIO_FUNC39_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC39_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC39_OUT_INV_SEL_M  (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S)
-#define GPIO_FUNC39_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC39_OUT_INV_SEL_S  9
-/** GPIO_FUNC39_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC39_OEN_SEL    (BIT(10))
-#define GPIO_FUNC39_OEN_SEL_M  (GPIO_FUNC39_OEN_SEL_V << GPIO_FUNC39_OEN_SEL_S)
-#define GPIO_FUNC39_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC39_OEN_SEL_S  10
-/** GPIO_FUNC39_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC39_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC39_OEN_INV_SEL_M  (GPIO_FUNC39_OEN_INV_SEL_V << GPIO_FUNC39_OEN_INV_SEL_S)
-#define GPIO_FUNC39_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC39_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC40_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8)
-/** GPIO_FUNC40_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC40_OUT_SEL    0x000001FFU
-#define GPIO_FUNC40_OUT_SEL_M  (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S)
-#define GPIO_FUNC40_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC40_OUT_SEL_S  0
-/** GPIO_FUNC40_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC40_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC40_OUT_INV_SEL_M  (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S)
-#define GPIO_FUNC40_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC40_OUT_INV_SEL_S  9
-/** GPIO_FUNC40_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC40_OEN_SEL    (BIT(10))
-#define GPIO_FUNC40_OEN_SEL_M  (GPIO_FUNC40_OEN_SEL_V << GPIO_FUNC40_OEN_SEL_S)
-#define GPIO_FUNC40_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC40_OEN_SEL_S  10
-/** GPIO_FUNC40_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC40_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC40_OEN_INV_SEL_M  (GPIO_FUNC40_OEN_INV_SEL_V << GPIO_FUNC40_OEN_INV_SEL_S)
-#define GPIO_FUNC40_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC40_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC41_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc)
-/** GPIO_FUNC41_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC41_OUT_SEL    0x000001FFU
-#define GPIO_FUNC41_OUT_SEL_M  (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S)
-#define GPIO_FUNC41_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC41_OUT_SEL_S  0
-/** GPIO_FUNC41_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC41_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC41_OUT_INV_SEL_M  (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S)
-#define GPIO_FUNC41_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC41_OUT_INV_SEL_S  9
-/** GPIO_FUNC41_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC41_OEN_SEL    (BIT(10))
-#define GPIO_FUNC41_OEN_SEL_M  (GPIO_FUNC41_OEN_SEL_V << GPIO_FUNC41_OEN_SEL_S)
-#define GPIO_FUNC41_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC41_OEN_SEL_S  10
-/** GPIO_FUNC41_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC41_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC41_OEN_INV_SEL_M  (GPIO_FUNC41_OEN_INV_SEL_V << GPIO_FUNC41_OEN_INV_SEL_S)
-#define GPIO_FUNC41_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC41_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC42_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600)
-/** GPIO_FUNC42_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC42_OUT_SEL    0x000001FFU
-#define GPIO_FUNC42_OUT_SEL_M  (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S)
-#define GPIO_FUNC42_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC42_OUT_SEL_S  0
-/** GPIO_FUNC42_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC42_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC42_OUT_INV_SEL_M  (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S)
-#define GPIO_FUNC42_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC42_OUT_INV_SEL_S  9
-/** GPIO_FUNC42_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC42_OEN_SEL    (BIT(10))
-#define GPIO_FUNC42_OEN_SEL_M  (GPIO_FUNC42_OEN_SEL_V << GPIO_FUNC42_OEN_SEL_S)
-#define GPIO_FUNC42_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC42_OEN_SEL_S  10
-/** GPIO_FUNC42_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC42_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC42_OEN_INV_SEL_M  (GPIO_FUNC42_OEN_INV_SEL_V << GPIO_FUNC42_OEN_INV_SEL_S)
-#define GPIO_FUNC42_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC42_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC43_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604)
-/** GPIO_FUNC43_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC43_OUT_SEL    0x000001FFU
-#define GPIO_FUNC43_OUT_SEL_M  (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S)
-#define GPIO_FUNC43_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC43_OUT_SEL_S  0
-/** GPIO_FUNC43_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC43_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC43_OUT_INV_SEL_M  (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S)
-#define GPIO_FUNC43_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC43_OUT_INV_SEL_S  9
-/** GPIO_FUNC43_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC43_OEN_SEL    (BIT(10))
-#define GPIO_FUNC43_OEN_SEL_M  (GPIO_FUNC43_OEN_SEL_V << GPIO_FUNC43_OEN_SEL_S)
-#define GPIO_FUNC43_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC43_OEN_SEL_S  10
-/** GPIO_FUNC43_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC43_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC43_OEN_INV_SEL_M  (GPIO_FUNC43_OEN_INV_SEL_V << GPIO_FUNC43_OEN_INV_SEL_S)
-#define GPIO_FUNC43_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC43_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC44_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x608)
-/** GPIO_FUNC44_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC44_OUT_SEL    0x000001FFU
-#define GPIO_FUNC44_OUT_SEL_M  (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S)
-#define GPIO_FUNC44_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC44_OUT_SEL_S  0
-/** GPIO_FUNC44_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC44_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC44_OUT_INV_SEL_M  (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S)
-#define GPIO_FUNC44_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC44_OUT_INV_SEL_S  9
-/** GPIO_FUNC44_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC44_OEN_SEL    (BIT(10))
-#define GPIO_FUNC44_OEN_SEL_M  (GPIO_FUNC44_OEN_SEL_V << GPIO_FUNC44_OEN_SEL_S)
-#define GPIO_FUNC44_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC44_OEN_SEL_S  10
-/** GPIO_FUNC44_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC44_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC44_OEN_INV_SEL_M  (GPIO_FUNC44_OEN_INV_SEL_V << GPIO_FUNC44_OEN_INV_SEL_S)
-#define GPIO_FUNC44_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC44_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC45_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC45_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x60c)
-/** GPIO_FUNC45_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC45_OUT_SEL    0x000001FFU
-#define GPIO_FUNC45_OUT_SEL_M  (GPIO_FUNC45_OUT_SEL_V << GPIO_FUNC45_OUT_SEL_S)
-#define GPIO_FUNC45_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC45_OUT_SEL_S  0
-/** GPIO_FUNC45_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC45_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC45_OUT_INV_SEL_M  (GPIO_FUNC45_OUT_INV_SEL_V << GPIO_FUNC45_OUT_INV_SEL_S)
-#define GPIO_FUNC45_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC45_OUT_INV_SEL_S  9
-/** GPIO_FUNC45_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC45_OEN_SEL    (BIT(10))
-#define GPIO_FUNC45_OEN_SEL_M  (GPIO_FUNC45_OEN_SEL_V << GPIO_FUNC45_OEN_SEL_S)
-#define GPIO_FUNC45_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC45_OEN_SEL_S  10
-/** GPIO_FUNC45_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC45_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC45_OEN_INV_SEL_M  (GPIO_FUNC45_OEN_INV_SEL_V << GPIO_FUNC45_OEN_INV_SEL_S)
-#define GPIO_FUNC45_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC45_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC46_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC46_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x610)
-/** GPIO_FUNC46_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC46_OUT_SEL    0x000001FFU
-#define GPIO_FUNC46_OUT_SEL_M  (GPIO_FUNC46_OUT_SEL_V << GPIO_FUNC46_OUT_SEL_S)
-#define GPIO_FUNC46_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC46_OUT_SEL_S  0
-/** GPIO_FUNC46_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC46_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC46_OUT_INV_SEL_M  (GPIO_FUNC46_OUT_INV_SEL_V << GPIO_FUNC46_OUT_INV_SEL_S)
-#define GPIO_FUNC46_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC46_OUT_INV_SEL_S  9
-/** GPIO_FUNC46_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC46_OEN_SEL    (BIT(10))
-#define GPIO_FUNC46_OEN_SEL_M  (GPIO_FUNC46_OEN_SEL_V << GPIO_FUNC46_OEN_SEL_S)
-#define GPIO_FUNC46_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC46_OEN_SEL_S  10
-/** GPIO_FUNC46_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC46_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC46_OEN_INV_SEL_M  (GPIO_FUNC46_OEN_INV_SEL_V << GPIO_FUNC46_OEN_INV_SEL_S)
-#define GPIO_FUNC46_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC46_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC47_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC47_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x614)
-/** GPIO_FUNC47_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC47_OUT_SEL    0x000001FFU
-#define GPIO_FUNC47_OUT_SEL_M  (GPIO_FUNC47_OUT_SEL_V << GPIO_FUNC47_OUT_SEL_S)
-#define GPIO_FUNC47_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC47_OUT_SEL_S  0
-/** GPIO_FUNC47_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC47_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC47_OUT_INV_SEL_M  (GPIO_FUNC47_OUT_INV_SEL_V << GPIO_FUNC47_OUT_INV_SEL_S)
-#define GPIO_FUNC47_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC47_OUT_INV_SEL_S  9
-/** GPIO_FUNC47_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC47_OEN_SEL    (BIT(10))
-#define GPIO_FUNC47_OEN_SEL_M  (GPIO_FUNC47_OEN_SEL_V << GPIO_FUNC47_OEN_SEL_S)
-#define GPIO_FUNC47_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC47_OEN_SEL_S  10
-/** GPIO_FUNC47_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC47_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC47_OEN_INV_SEL_M  (GPIO_FUNC47_OEN_INV_SEL_V << GPIO_FUNC47_OEN_INV_SEL_S)
-#define GPIO_FUNC47_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC47_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC48_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC48_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x618)
-/** GPIO_FUNC48_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC48_OUT_SEL    0x000001FFU
-#define GPIO_FUNC48_OUT_SEL_M  (GPIO_FUNC48_OUT_SEL_V << GPIO_FUNC48_OUT_SEL_S)
-#define GPIO_FUNC48_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC48_OUT_SEL_S  0
-/** GPIO_FUNC48_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC48_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC48_OUT_INV_SEL_M  (GPIO_FUNC48_OUT_INV_SEL_V << GPIO_FUNC48_OUT_INV_SEL_S)
-#define GPIO_FUNC48_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC48_OUT_INV_SEL_S  9
-/** GPIO_FUNC48_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC48_OEN_SEL    (BIT(10))
-#define GPIO_FUNC48_OEN_SEL_M  (GPIO_FUNC48_OEN_SEL_V << GPIO_FUNC48_OEN_SEL_S)
-#define GPIO_FUNC48_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC48_OEN_SEL_S  10
-/** GPIO_FUNC48_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC48_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC48_OEN_INV_SEL_M  (GPIO_FUNC48_OEN_INV_SEL_V << GPIO_FUNC48_OEN_INV_SEL_S)
-#define GPIO_FUNC48_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC48_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC49_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC49_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x61c)
-/** GPIO_FUNC49_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC49_OUT_SEL    0x000001FFU
-#define GPIO_FUNC49_OUT_SEL_M  (GPIO_FUNC49_OUT_SEL_V << GPIO_FUNC49_OUT_SEL_S)
-#define GPIO_FUNC49_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC49_OUT_SEL_S  0
-/** GPIO_FUNC49_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC49_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC49_OUT_INV_SEL_M  (GPIO_FUNC49_OUT_INV_SEL_V << GPIO_FUNC49_OUT_INV_SEL_S)
-#define GPIO_FUNC49_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC49_OUT_INV_SEL_S  9
-/** GPIO_FUNC49_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC49_OEN_SEL    (BIT(10))
-#define GPIO_FUNC49_OEN_SEL_M  (GPIO_FUNC49_OEN_SEL_V << GPIO_FUNC49_OEN_SEL_S)
-#define GPIO_FUNC49_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC49_OEN_SEL_S  10
-/** GPIO_FUNC49_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC49_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC49_OEN_INV_SEL_M  (GPIO_FUNC49_OEN_INV_SEL_V << GPIO_FUNC49_OEN_INV_SEL_S)
-#define GPIO_FUNC49_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC49_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC50_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC50_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x620)
-/** GPIO_FUNC50_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC50_OUT_SEL    0x000001FFU
-#define GPIO_FUNC50_OUT_SEL_M  (GPIO_FUNC50_OUT_SEL_V << GPIO_FUNC50_OUT_SEL_S)
-#define GPIO_FUNC50_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC50_OUT_SEL_S  0
-/** GPIO_FUNC50_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC50_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC50_OUT_INV_SEL_M  (GPIO_FUNC50_OUT_INV_SEL_V << GPIO_FUNC50_OUT_INV_SEL_S)
-#define GPIO_FUNC50_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC50_OUT_INV_SEL_S  9
-/** GPIO_FUNC50_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC50_OEN_SEL    (BIT(10))
-#define GPIO_FUNC50_OEN_SEL_M  (GPIO_FUNC50_OEN_SEL_V << GPIO_FUNC50_OEN_SEL_S)
-#define GPIO_FUNC50_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC50_OEN_SEL_S  10
-/** GPIO_FUNC50_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC50_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC50_OEN_INV_SEL_M  (GPIO_FUNC50_OEN_INV_SEL_V << GPIO_FUNC50_OEN_INV_SEL_S)
-#define GPIO_FUNC50_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC50_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC51_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC51_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x624)
-/** GPIO_FUNC51_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC51_OUT_SEL    0x000001FFU
-#define GPIO_FUNC51_OUT_SEL_M  (GPIO_FUNC51_OUT_SEL_V << GPIO_FUNC51_OUT_SEL_S)
-#define GPIO_FUNC51_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC51_OUT_SEL_S  0
-/** GPIO_FUNC51_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC51_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC51_OUT_INV_SEL_M  (GPIO_FUNC51_OUT_INV_SEL_V << GPIO_FUNC51_OUT_INV_SEL_S)
-#define GPIO_FUNC51_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC51_OUT_INV_SEL_S  9
-/** GPIO_FUNC51_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC51_OEN_SEL    (BIT(10))
-#define GPIO_FUNC51_OEN_SEL_M  (GPIO_FUNC51_OEN_SEL_V << GPIO_FUNC51_OEN_SEL_S)
-#define GPIO_FUNC51_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC51_OEN_SEL_S  10
-/** GPIO_FUNC51_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC51_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC51_OEN_INV_SEL_M  (GPIO_FUNC51_OEN_INV_SEL_V << GPIO_FUNC51_OEN_INV_SEL_S)
-#define GPIO_FUNC51_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC51_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC52_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC52_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x628)
-/** GPIO_FUNC52_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC52_OUT_SEL    0x000001FFU
-#define GPIO_FUNC52_OUT_SEL_M  (GPIO_FUNC52_OUT_SEL_V << GPIO_FUNC52_OUT_SEL_S)
-#define GPIO_FUNC52_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC52_OUT_SEL_S  0
-/** GPIO_FUNC52_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC52_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC52_OUT_INV_SEL_M  (GPIO_FUNC52_OUT_INV_SEL_V << GPIO_FUNC52_OUT_INV_SEL_S)
-#define GPIO_FUNC52_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC52_OUT_INV_SEL_S  9
-/** GPIO_FUNC52_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC52_OEN_SEL    (BIT(10))
-#define GPIO_FUNC52_OEN_SEL_M  (GPIO_FUNC52_OEN_SEL_V << GPIO_FUNC52_OEN_SEL_S)
-#define GPIO_FUNC52_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC52_OEN_SEL_S  10
-/** GPIO_FUNC52_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC52_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC52_OEN_INV_SEL_M  (GPIO_FUNC52_OEN_INV_SEL_V << GPIO_FUNC52_OEN_INV_SEL_S)
-#define GPIO_FUNC52_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC52_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC53_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC53_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x62c)
-/** GPIO_FUNC53_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC53_OUT_SEL    0x000001FFU
-#define GPIO_FUNC53_OUT_SEL_M  (GPIO_FUNC53_OUT_SEL_V << GPIO_FUNC53_OUT_SEL_S)
-#define GPIO_FUNC53_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC53_OUT_SEL_S  0
-/** GPIO_FUNC53_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC53_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC53_OUT_INV_SEL_M  (GPIO_FUNC53_OUT_INV_SEL_V << GPIO_FUNC53_OUT_INV_SEL_S)
-#define GPIO_FUNC53_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC53_OUT_INV_SEL_S  9
-/** GPIO_FUNC53_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC53_OEN_SEL    (BIT(10))
-#define GPIO_FUNC53_OEN_SEL_M  (GPIO_FUNC53_OEN_SEL_V << GPIO_FUNC53_OEN_SEL_S)
-#define GPIO_FUNC53_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC53_OEN_SEL_S  10
-/** GPIO_FUNC53_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC53_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC53_OEN_INV_SEL_M  (GPIO_FUNC53_OEN_INV_SEL_V << GPIO_FUNC53_OEN_INV_SEL_S)
-#define GPIO_FUNC53_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC53_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC54_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC54_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x630)
-/** GPIO_FUNC54_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC54_OUT_SEL    0x000001FFU
-#define GPIO_FUNC54_OUT_SEL_M  (GPIO_FUNC54_OUT_SEL_V << GPIO_FUNC54_OUT_SEL_S)
-#define GPIO_FUNC54_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC54_OUT_SEL_S  0
-/** GPIO_FUNC54_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC54_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC54_OUT_INV_SEL_M  (GPIO_FUNC54_OUT_INV_SEL_V << GPIO_FUNC54_OUT_INV_SEL_S)
-#define GPIO_FUNC54_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC54_OUT_INV_SEL_S  9
-/** GPIO_FUNC54_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC54_OEN_SEL    (BIT(10))
-#define GPIO_FUNC54_OEN_SEL_M  (GPIO_FUNC54_OEN_SEL_V << GPIO_FUNC54_OEN_SEL_S)
-#define GPIO_FUNC54_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC54_OEN_SEL_S  10
-/** GPIO_FUNC54_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC54_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC54_OEN_INV_SEL_M  (GPIO_FUNC54_OEN_INV_SEL_V << GPIO_FUNC54_OEN_INV_SEL_S)
-#define GPIO_FUNC54_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC54_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC55_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC55_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x634)
-/** GPIO_FUNC55_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC55_OUT_SEL    0x000001FFU
-#define GPIO_FUNC55_OUT_SEL_M  (GPIO_FUNC55_OUT_SEL_V << GPIO_FUNC55_OUT_SEL_S)
-#define GPIO_FUNC55_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC55_OUT_SEL_S  0
-/** GPIO_FUNC55_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC55_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC55_OUT_INV_SEL_M  (GPIO_FUNC55_OUT_INV_SEL_V << GPIO_FUNC55_OUT_INV_SEL_S)
-#define GPIO_FUNC55_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC55_OUT_INV_SEL_S  9
-/** GPIO_FUNC55_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC55_OEN_SEL    (BIT(10))
-#define GPIO_FUNC55_OEN_SEL_M  (GPIO_FUNC55_OEN_SEL_V << GPIO_FUNC55_OEN_SEL_S)
-#define GPIO_FUNC55_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC55_OEN_SEL_S  10
-/** GPIO_FUNC55_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC55_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC55_OEN_INV_SEL_M  (GPIO_FUNC55_OEN_INV_SEL_V << GPIO_FUNC55_OEN_INV_SEL_S)
-#define GPIO_FUNC55_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC55_OEN_INV_SEL_S  11
-
-/** GPIO_FUNC56_OUT_SEL_CFG_REG register
- *  GPIO output function select register
- */
-#define GPIO_FUNC56_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x638)
-/** GPIO_FUNC56_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
- *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
- *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
- *  GPIO_OUT_REG[n].
- */
-#define GPIO_FUNC56_OUT_SEL    0x000001FFU
-#define GPIO_FUNC56_OUT_SEL_M  (GPIO_FUNC56_OUT_SEL_V << GPIO_FUNC56_OUT_SEL_S)
-#define GPIO_FUNC56_OUT_SEL_V  0x000001FFU
-#define GPIO_FUNC56_OUT_SEL_S  0
-/** GPIO_FUNC56_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
- *  set this bit to invert output signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC56_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC56_OUT_INV_SEL_M  (GPIO_FUNC56_OUT_INV_SEL_V << GPIO_FUNC56_OUT_INV_SEL_S)
-#define GPIO_FUNC56_OUT_INV_SEL_V  0x00000001U
-#define GPIO_FUNC56_OUT_INV_SEL_S  9
-/** GPIO_FUNC56_OEN_SEL : R/W; bitpos: [10]; default: 0;
- *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
- *  enable signal.0:use peripheral output enable signal.
- */
-#define GPIO_FUNC56_OEN_SEL    (BIT(10))
-#define GPIO_FUNC56_OEN_SEL_M  (GPIO_FUNC56_OEN_SEL_V << GPIO_FUNC56_OEN_SEL_S)
-#define GPIO_FUNC56_OEN_SEL_V  0x00000001U
-#define GPIO_FUNC56_OEN_SEL_S  10
-/** GPIO_FUNC56_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
- *  set this bit to invert output enable signal.1:invert.0:not invert.
- */
-#define GPIO_FUNC56_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC56_OEN_INV_SEL_M  (GPIO_FUNC56_OEN_INV_SEL_V << GPIO_FUNC56_OEN_INV_SEL_S)
-#define GPIO_FUNC56_OEN_INV_SEL_V  0x00000001U
-#define GPIO_FUNC56_OEN_INV_SEL_S  11
-
-/** GPIO_INTR_2_REG register
- *  GPIO interrupt 2 status register for GPIO0-31
- */
-#define GPIO_INTR_2_REG (DR_REG_GPIO_BASE + 0x63c)
-/** GPIO_INT_2 : RO; bitpos: [31:0]; default: 0;
- *  GPIO interrupt 2 status register for GPIO0-31
- */
-#define GPIO_INT_2    0xFFFFFFFFU
-#define GPIO_INT_2_M  (GPIO_INT_2_V << GPIO_INT_2_S)
-#define GPIO_INT_2_V  0xFFFFFFFFU
-#define GPIO_INT_2_S  0
-
-/** GPIO_INTR1_2_REG register
- *  GPIO interrupt 2 status register for GPIO32-56
- */
-#define GPIO_INTR1_2_REG (DR_REG_GPIO_BASE + 0x640)
-/** GPIO_INT1_2 : RO; bitpos: [24:0]; default: 0;
- *  GPIO interrupt 2 status register for GPIO32-56
- */
-#define GPIO_INT1_2    0x01FFFFFFU
-#define GPIO_INT1_2_M  (GPIO_INT1_2_V << GPIO_INT1_2_S)
-#define GPIO_INT1_2_V  0x01FFFFFFU
-#define GPIO_INT1_2_S  0
-
-/** GPIO_INTR_3_REG register
- *  GPIO interrupt 3 status register for GPIO0-31
- */
-#define GPIO_INTR_3_REG (DR_REG_GPIO_BASE + 0x644)
-/** GPIO_INT_3 : RO; bitpos: [31:0]; default: 0;
- *  GPIO interrupt 3 status register for GPIO0-31
- */
-#define GPIO_INT_3    0xFFFFFFFFU
-#define GPIO_INT_3_M  (GPIO_INT_3_V << GPIO_INT_3_S)
-#define GPIO_INT_3_V  0xFFFFFFFFU
-#define GPIO_INT_3_S  0
-
-/** GPIO_INTR1_3_REG register
- *  GPIO interrupt 3 status register for GPIO32-56
- */
-#define GPIO_INTR1_3_REG (DR_REG_GPIO_BASE + 0x648)
-/** GPIO_INT1_3 : RO; bitpos: [24:0]; default: 0;
- *  GPIO interrupt 3 status register for GPIO32-56
- */
-#define GPIO_INT1_3    0x01FFFFFFU
-#define GPIO_INT1_3_M  (GPIO_INT1_3_V << GPIO_INT1_3_S)
-#define GPIO_INT1_3_V  0x01FFFFFFU
-#define GPIO_INT1_3_S  0
-
-/** GPIO_CLOCK_GATE_REG register
- *  GPIO clock gate register
- */
-#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x64c)
-/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
- *  set this bit to enable GPIO clock gate
- */
-#define GPIO_CLK_EN    (BIT(0))
-#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
-#define GPIO_CLK_EN_V  0x00000001U
-#define GPIO_CLK_EN_S  0
-
-/** GPIO_INT_RAW_REG register
- *  analog comparator interrupt raw
- */
-#define GPIO_INT_RAW_REG (DR_REG_GPIO_BASE + 0x700)
-/** GPIO_COMP0_NEG_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  analog comparator pos edge interrupt raw
- */
-#define GPIO_COMP0_NEG_INT_RAW    (BIT(0))
-#define GPIO_COMP0_NEG_INT_RAW_M  (GPIO_COMP0_NEG_INT_RAW_V << GPIO_COMP0_NEG_INT_RAW_S)
-#define GPIO_COMP0_NEG_INT_RAW_V  0x00000001U
-#define GPIO_COMP0_NEG_INT_RAW_S  0
-/** GPIO_COMP0_POS_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  analog comparator neg edge interrupt raw
- */
-#define GPIO_COMP0_POS_INT_RAW    (BIT(1))
-#define GPIO_COMP0_POS_INT_RAW_M  (GPIO_COMP0_POS_INT_RAW_V << GPIO_COMP0_POS_INT_RAW_S)
-#define GPIO_COMP0_POS_INT_RAW_V  0x00000001U
-#define GPIO_COMP0_POS_INT_RAW_S  1
-/** GPIO_COMP0_ALL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  analog comparator neg or pos edge interrupt raw
- */
-#define GPIO_COMP0_ALL_INT_RAW    (BIT(2))
-#define GPIO_COMP0_ALL_INT_RAW_M  (GPIO_COMP0_ALL_INT_RAW_V << GPIO_COMP0_ALL_INT_RAW_S)
-#define GPIO_COMP0_ALL_INT_RAW_V  0x00000001U
-#define GPIO_COMP0_ALL_INT_RAW_S  2
-/** GPIO_COMP1_NEG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  analog comparator pos edge interrupt raw
- */
-#define GPIO_COMP1_NEG_INT_RAW    (BIT(3))
-#define GPIO_COMP1_NEG_INT_RAW_M  (GPIO_COMP1_NEG_INT_RAW_V << GPIO_COMP1_NEG_INT_RAW_S)
-#define GPIO_COMP1_NEG_INT_RAW_V  0x00000001U
-#define GPIO_COMP1_NEG_INT_RAW_S  3
-/** GPIO_COMP1_POS_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  analog comparator neg edge interrupt raw
- */
-#define GPIO_COMP1_POS_INT_RAW    (BIT(4))
-#define GPIO_COMP1_POS_INT_RAW_M  (GPIO_COMP1_POS_INT_RAW_V << GPIO_COMP1_POS_INT_RAW_S)
-#define GPIO_COMP1_POS_INT_RAW_V  0x00000001U
-#define GPIO_COMP1_POS_INT_RAW_S  4
-/** GPIO_COMP1_ALL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  analog comparator neg or pos edge interrupt raw
- */
-#define GPIO_COMP1_ALL_INT_RAW    (BIT(5))
-#define GPIO_COMP1_ALL_INT_RAW_M  (GPIO_COMP1_ALL_INT_RAW_V << GPIO_COMP1_ALL_INT_RAW_S)
-#define GPIO_COMP1_ALL_INT_RAW_V  0x00000001U
-#define GPIO_COMP1_ALL_INT_RAW_S  5
-/** GPIO_BISTOK_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  pad bistok interrupt raw
- */
-#define GPIO_BISTOK_INT_RAW    (BIT(6))
-#define GPIO_BISTOK_INT_RAW_M  (GPIO_BISTOK_INT_RAW_V << GPIO_BISTOK_INT_RAW_S)
-#define GPIO_BISTOK_INT_RAW_V  0x00000001U
-#define GPIO_BISTOK_INT_RAW_S  6
-/** GPIO_BISTFAIL_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  pad bistfail interrupt raw
- */
-#define GPIO_BISTFAIL_INT_RAW    (BIT(7))
-#define GPIO_BISTFAIL_INT_RAW_M  (GPIO_BISTFAIL_INT_RAW_V << GPIO_BISTFAIL_INT_RAW_S)
-#define GPIO_BISTFAIL_INT_RAW_V  0x00000001U
-#define GPIO_BISTFAIL_INT_RAW_S  7
-
-/** GPIO_INT_ST_REG register
- *  analog comparator interrupt status
- */
-#define GPIO_INT_ST_REG (DR_REG_GPIO_BASE + 0x704)
-/** GPIO_COMP0_NEG_INT_ST : RO; bitpos: [0]; default: 0;
- *  analog comparator pos edge interrupt status
- */
-#define GPIO_COMP0_NEG_INT_ST    (BIT(0))
-#define GPIO_COMP0_NEG_INT_ST_M  (GPIO_COMP0_NEG_INT_ST_V << GPIO_COMP0_NEG_INT_ST_S)
-#define GPIO_COMP0_NEG_INT_ST_V  0x00000001U
-#define GPIO_COMP0_NEG_INT_ST_S  0
-/** GPIO_COMP0_POS_INT_ST : RO; bitpos: [1]; default: 0;
- *  analog comparator neg edge interrupt status
- */
-#define GPIO_COMP0_POS_INT_ST    (BIT(1))
-#define GPIO_COMP0_POS_INT_ST_M  (GPIO_COMP0_POS_INT_ST_V << GPIO_COMP0_POS_INT_ST_S)
-#define GPIO_COMP0_POS_INT_ST_V  0x00000001U
-#define GPIO_COMP0_POS_INT_ST_S  1
-/** GPIO_COMP0_ALL_INT_ST : RO; bitpos: [2]; default: 0;
- *  analog comparator neg or pos edge interrupt status
- */
-#define GPIO_COMP0_ALL_INT_ST    (BIT(2))
-#define GPIO_COMP0_ALL_INT_ST_M  (GPIO_COMP0_ALL_INT_ST_V << GPIO_COMP0_ALL_INT_ST_S)
-#define GPIO_COMP0_ALL_INT_ST_V  0x00000001U
-#define GPIO_COMP0_ALL_INT_ST_S  2
-/** GPIO_COMP1_NEG_INT_ST : RO; bitpos: [3]; default: 0;
- *  analog comparator pos edge interrupt status
- */
-#define GPIO_COMP1_NEG_INT_ST    (BIT(3))
-#define GPIO_COMP1_NEG_INT_ST_M  (GPIO_COMP1_NEG_INT_ST_V << GPIO_COMP1_NEG_INT_ST_S)
-#define GPIO_COMP1_NEG_INT_ST_V  0x00000001U
-#define GPIO_COMP1_NEG_INT_ST_S  3
-/** GPIO_COMP1_POS_INT_ST : RO; bitpos: [4]; default: 0;
- *  analog comparator neg edge interrupt status
- */
-#define GPIO_COMP1_POS_INT_ST    (BIT(4))
-#define GPIO_COMP1_POS_INT_ST_M  (GPIO_COMP1_POS_INT_ST_V << GPIO_COMP1_POS_INT_ST_S)
-#define GPIO_COMP1_POS_INT_ST_V  0x00000001U
-#define GPIO_COMP1_POS_INT_ST_S  4
-/** GPIO_COMP1_ALL_INT_ST : RO; bitpos: [5]; default: 0;
- *  analog comparator neg or pos edge interrupt status
- */
-#define GPIO_COMP1_ALL_INT_ST    (BIT(5))
-#define GPIO_COMP1_ALL_INT_ST_M  (GPIO_COMP1_ALL_INT_ST_V << GPIO_COMP1_ALL_INT_ST_S)
-#define GPIO_COMP1_ALL_INT_ST_V  0x00000001U
-#define GPIO_COMP1_ALL_INT_ST_S  5
-/** GPIO_BISTOK_INT_ST : RO; bitpos: [6]; default: 0;
- *  pad bistok interrupt status
- */
-#define GPIO_BISTOK_INT_ST    (BIT(6))
-#define GPIO_BISTOK_INT_ST_M  (GPIO_BISTOK_INT_ST_V << GPIO_BISTOK_INT_ST_S)
-#define GPIO_BISTOK_INT_ST_V  0x00000001U
-#define GPIO_BISTOK_INT_ST_S  6
-/** GPIO_BISTFAIL_INT_ST : RO; bitpos: [7]; default: 0;
- *  pad bistfail interrupt status
- */
-#define GPIO_BISTFAIL_INT_ST    (BIT(7))
-#define GPIO_BISTFAIL_INT_ST_M  (GPIO_BISTFAIL_INT_ST_V << GPIO_BISTFAIL_INT_ST_S)
-#define GPIO_BISTFAIL_INT_ST_V  0x00000001U
-#define GPIO_BISTFAIL_INT_ST_S  7
-
-/** GPIO_INT_ENA_REG register
- *  analog comparator interrupt enable
- */
-#define GPIO_INT_ENA_REG (DR_REG_GPIO_BASE + 0x708)
-/** GPIO_COMP0_NEG_INT_ENA : R/W; bitpos: [0]; default: 1;
- *  analog comparator pos edge interrupt enable
- */
-#define GPIO_COMP0_NEG_INT_ENA    (BIT(0))
-#define GPIO_COMP0_NEG_INT_ENA_M  (GPIO_COMP0_NEG_INT_ENA_V << GPIO_COMP0_NEG_INT_ENA_S)
-#define GPIO_COMP0_NEG_INT_ENA_V  0x00000001U
-#define GPIO_COMP0_NEG_INT_ENA_S  0
-/** GPIO_COMP0_POS_INT_ENA : R/W; bitpos: [1]; default: 1;
- *  analog comparator neg edge interrupt enable
- */
-#define GPIO_COMP0_POS_INT_ENA    (BIT(1))
-#define GPIO_COMP0_POS_INT_ENA_M  (GPIO_COMP0_POS_INT_ENA_V << GPIO_COMP0_POS_INT_ENA_S)
-#define GPIO_COMP0_POS_INT_ENA_V  0x00000001U
-#define GPIO_COMP0_POS_INT_ENA_S  1
-/** GPIO_COMP0_ALL_INT_ENA : R/W; bitpos: [2]; default: 1;
- *  analog comparator neg or pos edge interrupt enable
- */
-#define GPIO_COMP0_ALL_INT_ENA    (BIT(2))
-#define GPIO_COMP0_ALL_INT_ENA_M  (GPIO_COMP0_ALL_INT_ENA_V << GPIO_COMP0_ALL_INT_ENA_S)
-#define GPIO_COMP0_ALL_INT_ENA_V  0x00000001U
-#define GPIO_COMP0_ALL_INT_ENA_S  2
-/** GPIO_COMP1_NEG_INT_ENA : R/W; bitpos: [3]; default: 1;
- *  analog comparator pos edge interrupt enable
- */
-#define GPIO_COMP1_NEG_INT_ENA    (BIT(3))
-#define GPIO_COMP1_NEG_INT_ENA_M  (GPIO_COMP1_NEG_INT_ENA_V << GPIO_COMP1_NEG_INT_ENA_S)
-#define GPIO_COMP1_NEG_INT_ENA_V  0x00000001U
-#define GPIO_COMP1_NEG_INT_ENA_S  3
-/** GPIO_COMP1_POS_INT_ENA : R/W; bitpos: [4]; default: 1;
- *  analog comparator neg edge interrupt enable
- */
-#define GPIO_COMP1_POS_INT_ENA    (BIT(4))
-#define GPIO_COMP1_POS_INT_ENA_M  (GPIO_COMP1_POS_INT_ENA_V << GPIO_COMP1_POS_INT_ENA_S)
-#define GPIO_COMP1_POS_INT_ENA_V  0x00000001U
-#define GPIO_COMP1_POS_INT_ENA_S  4
-/** GPIO_COMP1_ALL_INT_ENA : R/W; bitpos: [5]; default: 1;
- *  analog comparator neg or pos edge interrupt enable
- */
-#define GPIO_COMP1_ALL_INT_ENA    (BIT(5))
-#define GPIO_COMP1_ALL_INT_ENA_M  (GPIO_COMP1_ALL_INT_ENA_V << GPIO_COMP1_ALL_INT_ENA_S)
-#define GPIO_COMP1_ALL_INT_ENA_V  0x00000001U
-#define GPIO_COMP1_ALL_INT_ENA_S  5
-/** GPIO_BISTOK_INT_ENA : R/W; bitpos: [6]; default: 1;
- *  pad bistok interrupt enable
- */
-#define GPIO_BISTOK_INT_ENA    (BIT(6))
-#define GPIO_BISTOK_INT_ENA_M  (GPIO_BISTOK_INT_ENA_V << GPIO_BISTOK_INT_ENA_S)
-#define GPIO_BISTOK_INT_ENA_V  0x00000001U
-#define GPIO_BISTOK_INT_ENA_S  6
-/** GPIO_BISTFAIL_INT_ENA : R/W; bitpos: [7]; default: 1;
- *  pad bistfail interrupt enable
- */
-#define GPIO_BISTFAIL_INT_ENA    (BIT(7))
-#define GPIO_BISTFAIL_INT_ENA_M  (GPIO_BISTFAIL_INT_ENA_V << GPIO_BISTFAIL_INT_ENA_S)
-#define GPIO_BISTFAIL_INT_ENA_V  0x00000001U
-#define GPIO_BISTFAIL_INT_ENA_S  7
-
-/** GPIO_INT_CLR_REG register
- *  analog comparator interrupt clear
- */
-#define GPIO_INT_CLR_REG (DR_REG_GPIO_BASE + 0x70c)
-/** GPIO_COMP0_NEG_INT_CLR : WT; bitpos: [0]; default: 0;
- *  analog comparator pos edge interrupt clear
- */
-#define GPIO_COMP0_NEG_INT_CLR    (BIT(0))
-#define GPIO_COMP0_NEG_INT_CLR_M  (GPIO_COMP0_NEG_INT_CLR_V << GPIO_COMP0_NEG_INT_CLR_S)
-#define GPIO_COMP0_NEG_INT_CLR_V  0x00000001U
-#define GPIO_COMP0_NEG_INT_CLR_S  0
-/** GPIO_COMP0_POS_INT_CLR : WT; bitpos: [1]; default: 0;
- *  analog comparator neg edge interrupt clear
- */
-#define GPIO_COMP0_POS_INT_CLR    (BIT(1))
-#define GPIO_COMP0_POS_INT_CLR_M  (GPIO_COMP0_POS_INT_CLR_V << GPIO_COMP0_POS_INT_CLR_S)
-#define GPIO_COMP0_POS_INT_CLR_V  0x00000001U
-#define GPIO_COMP0_POS_INT_CLR_S  1
-/** GPIO_COMP0_ALL_INT_CLR : WT; bitpos: [2]; default: 0;
- *  analog comparator neg or pos edge interrupt clear
- */
-#define GPIO_COMP0_ALL_INT_CLR    (BIT(2))
-#define GPIO_COMP0_ALL_INT_CLR_M  (GPIO_COMP0_ALL_INT_CLR_V << GPIO_COMP0_ALL_INT_CLR_S)
-#define GPIO_COMP0_ALL_INT_CLR_V  0x00000001U
-#define GPIO_COMP0_ALL_INT_CLR_S  2
-/** GPIO_COMP1_NEG_INT_CLR : WT; bitpos: [3]; default: 0;
- *  analog comparator pos edge interrupt clear
- */
-#define GPIO_COMP1_NEG_INT_CLR    (BIT(3))
-#define GPIO_COMP1_NEG_INT_CLR_M  (GPIO_COMP1_NEG_INT_CLR_V << GPIO_COMP1_NEG_INT_CLR_S)
-#define GPIO_COMP1_NEG_INT_CLR_V  0x00000001U
-#define GPIO_COMP1_NEG_INT_CLR_S  3
-/** GPIO_COMP1_POS_INT_CLR : WT; bitpos: [4]; default: 0;
- *  analog comparator neg edge interrupt clear
- */
-#define GPIO_COMP1_POS_INT_CLR    (BIT(4))
-#define GPIO_COMP1_POS_INT_CLR_M  (GPIO_COMP1_POS_INT_CLR_V << GPIO_COMP1_POS_INT_CLR_S)
-#define GPIO_COMP1_POS_INT_CLR_V  0x00000001U
-#define GPIO_COMP1_POS_INT_CLR_S  4
-/** GPIO_COMP1_ALL_INT_CLR : WT; bitpos: [5]; default: 0;
- *  analog comparator neg or pos edge interrupt clear
- */
-#define GPIO_COMP1_ALL_INT_CLR    (BIT(5))
-#define GPIO_COMP1_ALL_INT_CLR_M  (GPIO_COMP1_ALL_INT_CLR_V << GPIO_COMP1_ALL_INT_CLR_S)
-#define GPIO_COMP1_ALL_INT_CLR_V  0x00000001U
-#define GPIO_COMP1_ALL_INT_CLR_S  5
-/** GPIO_BISTOK_INT_CLR : WT; bitpos: [6]; default: 0;
- *  pad bistok interrupt enable
- */
-#define GPIO_BISTOK_INT_CLR    (BIT(6))
-#define GPIO_BISTOK_INT_CLR_M  (GPIO_BISTOK_INT_CLR_V << GPIO_BISTOK_INT_CLR_S)
-#define GPIO_BISTOK_INT_CLR_V  0x00000001U
-#define GPIO_BISTOK_INT_CLR_S  6
-/** GPIO_BISTFAIL_INT_CLR : WT; bitpos: [7]; default: 0;
- *  pad bistfail interrupt enable
- */
-#define GPIO_BISTFAIL_INT_CLR    (BIT(7))
-#define GPIO_BISTFAIL_INT_CLR_M  (GPIO_BISTFAIL_INT_CLR_V << GPIO_BISTFAIL_INT_CLR_S)
-#define GPIO_BISTFAIL_INT_CLR_V  0x00000001U
-#define GPIO_BISTFAIL_INT_CLR_S  7
-
-/** GPIO_ZERO_DET0_FILTER_CNT_REG register
- *  GPIO analog comparator zero detect filter count
- */
-#define GPIO_ZERO_DET0_FILTER_CNT_REG (DR_REG_GPIO_BASE + 0x710)
-/** GPIO_ZERO_DET0_FILTER_CNT : R/W; bitpos: [31:0]; default: 4294967295;
- *  GPIO analog comparator zero detect filter count
- */
-#define GPIO_ZERO_DET0_FILTER_CNT    0xFFFFFFFFU
-#define GPIO_ZERO_DET0_FILTER_CNT_M  (GPIO_ZERO_DET0_FILTER_CNT_V << GPIO_ZERO_DET0_FILTER_CNT_S)
-#define GPIO_ZERO_DET0_FILTER_CNT_V  0xFFFFFFFFU
-#define GPIO_ZERO_DET0_FILTER_CNT_S  0
-
-/** GPIO_ZERO_DET1_FILTER_CNT_REG register
- *  GPIO analog comparator zero detect filter count
- */
-#define GPIO_ZERO_DET1_FILTER_CNT_REG (DR_REG_GPIO_BASE + 0x714)
-/** GPIO_ZERO_DET1_FILTER_CNT : R/W; bitpos: [31:0]; default: 4294967295;
- *  GPIO analog comparator zero detect filter count
- */
-#define GPIO_ZERO_DET1_FILTER_CNT    0xFFFFFFFFU
-#define GPIO_ZERO_DET1_FILTER_CNT_M  (GPIO_ZERO_DET1_FILTER_CNT_V << GPIO_ZERO_DET1_FILTER_CNT_S)
-#define GPIO_ZERO_DET1_FILTER_CNT_V  0xFFFFFFFFU
-#define GPIO_ZERO_DET1_FILTER_CNT_S  0
-
-/** GPIO_SEND_SEQ_REG register
- *  High speed sdio pad bist send sequence
- */
-#define GPIO_SEND_SEQ_REG (DR_REG_GPIO_BASE + 0x718)
-/** GPIO_SEND_SEQ : R/W; bitpos: [31:0]; default: 305419896;
- *  High speed sdio pad bist send sequence
- */
-#define GPIO_SEND_SEQ    0xFFFFFFFFU
-#define GPIO_SEND_SEQ_M  (GPIO_SEND_SEQ_V << GPIO_SEND_SEQ_S)
-#define GPIO_SEND_SEQ_V  0xFFFFFFFFU
-#define GPIO_SEND_SEQ_S  0
-
-/** GPIO_RECIVE_SEQ_REG register
- *  High speed sdio pad bist recive sequence
- */
-#define GPIO_RECIVE_SEQ_REG (DR_REG_GPIO_BASE + 0x71c)
-/** GPIO_RECIVE_SEQ : RO; bitpos: [31:0]; default: 0;
- *  High speed sdio pad bist recive sequence
- */
-#define GPIO_RECIVE_SEQ    0xFFFFFFFFU
-#define GPIO_RECIVE_SEQ_M  (GPIO_RECIVE_SEQ_V << GPIO_RECIVE_SEQ_S)
-#define GPIO_RECIVE_SEQ_V  0xFFFFFFFFU
-#define GPIO_RECIVE_SEQ_S  0
-
-/** GPIO_BISTIN_SEL_REG register
- *  High speed sdio pad bist in pad sel
- */
-#define GPIO_BISTIN_SEL_REG (DR_REG_GPIO_BASE + 0x720)
-/** GPIO_BISTIN_SEL : R/W; bitpos: [3:0]; default: 15;
- *  High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
- */
-#define GPIO_BISTIN_SEL    0x0000000FU
-#define GPIO_BISTIN_SEL_M  (GPIO_BISTIN_SEL_V << GPIO_BISTIN_SEL_S)
-#define GPIO_BISTIN_SEL_V  0x0000000FU
-#define GPIO_BISTIN_SEL_S  0
-
-/** GPIO_BIST_CTRL_REG register
- *  High speed sdio pad bist control
- */
-#define GPIO_BIST_CTRL_REG (DR_REG_GPIO_BASE + 0x724)
-/** GPIO_BIST_PAD_OE : R/W; bitpos: [0]; default: 1;
- *  High speed sdio pad bist out pad oe
- */
-#define GPIO_BIST_PAD_OE    (BIT(0))
-#define GPIO_BIST_PAD_OE_M  (GPIO_BIST_PAD_OE_V << GPIO_BIST_PAD_OE_S)
-#define GPIO_BIST_PAD_OE_V  0x00000001U
-#define GPIO_BIST_PAD_OE_S  0
-/** GPIO_BIST_START : WT; bitpos: [1]; default: 0;
- *  High speed sdio pad bist start
- */
-#define GPIO_BIST_START    (BIT(1))
-#define GPIO_BIST_START_M  (GPIO_BIST_START_V << GPIO_BIST_START_S)
-#define GPIO_BIST_START_V  0x00000001U
-#define GPIO_BIST_START_S  1
-
-/** GPIO_DATE_REG register
- *  GPIO version register
- */
-#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x7fc)
-/** GPIO_DATE : R/W; bitpos: [27:0]; default: 2294787;
- *  version register
- */
-#define GPIO_DATE    0x0FFFFFFFU
-#define GPIO_DATE_M  (GPIO_DATE_V << GPIO_DATE_S)
-#define GPIO_DATE_V  0x0FFFFFFFU
-#define GPIO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/gpio_struct.h b/components/soc/esp32p4/include/soc/gpio_struct.h
deleted file mode 100644
index 052c0b9a6db..00000000000
--- a/components/soc/esp32p4/include/soc/gpio_struct.h
+++ /dev/null
@@ -1,878 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configuration register */
-/** Type of bt_select register
- *  GPIO bit select register
- */
-typedef union {
-    struct {
-        /** bt_sel : R/W; bitpos: [31:0]; default: 0;
-         *  GPIO bit select register
-         */
-        uint32_t bt_sel:32;
-    };
-    uint32_t val;
-} gpio_bt_select_reg_t;
-
-/** Type of out register
- *  GPIO output register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
-         *  GPIO output register for GPIO0-31
-         */
-        uint32_t out_data_orig:32;
-    };
-    uint32_t val;
-} gpio_out_reg_t;
-
-/** Type of out_w1ts register
- *  GPIO output set register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** out_w1ts : WT; bitpos: [31:0]; default: 0;
-         *  GPIO output set register for GPIO0-31
-         */
-        uint32_t out_w1ts:32;
-    };
-    uint32_t val;
-} gpio_out_w1ts_reg_t;
-
-/** Type of out_w1tc register
- *  GPIO output clear register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** out_w1tc : WT; bitpos: [31:0]; default: 0;
-         *  GPIO output clear register for GPIO0-31
-         */
-        uint32_t out_w1tc:32;
-    };
-    uint32_t val;
-} gpio_out_w1tc_reg_t;
-
-/** Type of out1 register
- *  GPIO output register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** out1_data_orig : R/W/SC/WTC; bitpos: [24:0]; default: 0;
-         *  GPIO output register for GPIO32-56
-         */
-        uint32_t out1_data_orig:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_out1_reg_t;
-
-/** Type of out1_w1ts register
- *  GPIO output set register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** out1_w1ts : WT; bitpos: [24:0]; default: 0;
-         *  GPIO output set register for GPIO32-56
-         */
-        uint32_t out1_w1ts:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_out1_w1ts_reg_t;
-
-/** Type of out1_w1tc register
- *  GPIO output clear register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** out1_w1tc : WT; bitpos: [24:0]; default: 0;
-         *  GPIO output clear register for GPIO32-56
-         */
-        uint32_t out1_w1tc:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_out1_w1tc_reg_t;
-
-/** Type of enable register
- *  GPIO output enable register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
-         *  GPIO output enable register for GPIO0-31
-         */
-        uint32_t enable_data:32;
-    };
-    uint32_t val;
-} gpio_enable_reg_t;
-
-/** Type of enable_w1ts register
- *  GPIO output enable set register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** enable_w1ts : WT; bitpos: [31:0]; default: 0;
-         *  GPIO output enable set register for GPIO0-31
-         */
-        uint32_t enable_w1ts:32;
-    };
-    uint32_t val;
-} gpio_enable_w1ts_reg_t;
-
-/** Type of enable_w1tc register
- *  GPIO output enable clear register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** enable_w1tc : WT; bitpos: [31:0]; default: 0;
-         *  GPIO output enable clear register for GPIO0-31
-         */
-        uint32_t enable_w1tc:32;
-    };
-    uint32_t val;
-} gpio_enable_w1tc_reg_t;
-
-/** Type of enable1 register
- *  GPIO output enable register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** enable1_data : R/W/WTC; bitpos: [24:0]; default: 0;
-         *  GPIO output enable register for GPIO32-56
-         */
-        uint32_t enable1_data:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_enable1_reg_t;
-
-/** Type of enable1_w1ts register
- *  GPIO output enable set register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** enable1_w1ts : WT; bitpos: [24:0]; default: 0;
-         *  GPIO output enable set register for GPIO32-56
-         */
-        uint32_t enable1_w1ts:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_enable1_w1ts_reg_t;
-
-/** Type of enable1_w1tc register
- *  GPIO output enable clear register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** enable1_w1tc : WT; bitpos: [24:0]; default: 0;
-         *  GPIO output enable clear register for GPIO32-56
-         */
-        uint32_t enable1_w1tc:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_enable1_w1tc_reg_t;
-
-/** Type of strap register
- *  pad strapping register
- */
-typedef union {
-    struct {
-        /** strapping : RO; bitpos: [15:0]; default: 0;
-         *  pad strapping register
-         */
-        uint32_t strapping:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} gpio_strap_reg_t;
-
-/** Type of in register
- *  GPIO input register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** in_data_next : RO; bitpos: [31:0]; default: 0;
-         *  GPIO input register for GPIO0-31
-         */
-        uint32_t in_data_next:32;
-    };
-    uint32_t val;
-} gpio_in_reg_t;
-
-/** Type of in1 register
- *  GPIO input register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** in1_data_next : RO; bitpos: [24:0]; default: 0;
-         *  GPIO input register for GPIO32-56
-         */
-        uint32_t in1_data_next:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_in1_reg_t;
-
-/** Type of status register
- *  GPIO interrupt status register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
-         *  GPIO interrupt status register for GPIO0-31
-         */
-        uint32_t status_interrupt:32;
-    };
-    uint32_t val;
-} gpio_status_reg_t;
-
-/** Type of status_w1ts register
- *  GPIO interrupt status set register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** status_w1ts : WT; bitpos: [31:0]; default: 0;
-         *  GPIO interrupt status set register for GPIO0-31
-         */
-        uint32_t status_w1ts:32;
-    };
-    uint32_t val;
-} gpio_status_w1ts_reg_t;
-
-/** Type of status_w1tc register
- *  GPIO interrupt status clear register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** status_w1tc : WT; bitpos: [31:0]; default: 0;
-         *  GPIO interrupt status clear register for GPIO0-31
-         */
-        uint32_t status_w1tc:32;
-    };
-    uint32_t val;
-} gpio_status_w1tc_reg_t;
-
-/** Type of status1 register
- *  GPIO interrupt status register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** status1_interrupt : R/W/WTC; bitpos: [24:0]; default: 0;
-         *  GPIO interrupt status register for GPIO32-56
-         */
-        uint32_t status1_interrupt:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_status1_reg_t;
-
-/** Type of status1_w1ts register
- *  GPIO interrupt status set register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** status1_w1ts : WT; bitpos: [24:0]; default: 0;
-         *  GPIO interrupt status set register for GPIO32-56
-         */
-        uint32_t status1_w1ts:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_status1_w1ts_reg_t;
-
-/** Type of status1_w1tc register
- *  GPIO interrupt status clear register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** status1_w1tc : WT; bitpos: [24:0]; default: 0;
-         *  GPIO interrupt status clear register for GPIO32-56
-         */
-        uint32_t status1_w1tc:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_status1_w1tc_reg_t;
-
-/** Type of intr_0 register
- *  GPIO interrupt 0 status register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** int_0 : RO; bitpos: [31:0]; default: 0;
-         *  GPIO interrupt 0 status register for GPIO0-31
-         */
-        uint32_t int_0:32;
-    };
-    uint32_t val;
-} gpio_intr_0_reg_t;
-
-/** Type of intr1_0 register
- *  GPIO interrupt 0 status register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** int1_0 : RO; bitpos: [24:0]; default: 0;
-         *  GPIO interrupt 0 status register for GPIO32-56
-         */
-        uint32_t int1_0:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_intr1_0_reg_t;
-
-/** Type of intr_1 register
- *  GPIO interrupt 1 status register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** int_1 : RO; bitpos: [31:0]; default: 0;
-         *  GPIO interrupt 1 status register for GPIO0-31
-         */
-        uint32_t int_1:32;
-    };
-    uint32_t val;
-} gpio_intr_1_reg_t;
-
-/** Type of intr1_1 register
- *  GPIO interrupt 1 status register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** int1_1 : RO; bitpos: [24:0]; default: 0;
-         *  GPIO interrupt 1 status register for GPIO32-56
-         */
-        uint32_t int1_1:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_intr1_1_reg_t;
-
-/** Type of status_next register
- *  GPIO interrupt source register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
-         *  GPIO interrupt source register for GPIO0-31
-         */
-        uint32_t status_interrupt_next:32;
-    };
-    uint32_t val;
-} gpio_status_next_reg_t;
-
-/** Type of status_next1 register
- *  GPIO interrupt source register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** status_interrupt_next1 : RO; bitpos: [24:0]; default: 0;
-         *  GPIO interrupt source register for GPIO32-56
-         */
-        uint32_t status_interrupt_next1:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_status_next1_reg_t;
-
-/** Type of pin register
- *  GPIO pin configuration register
- */
-typedef union {
-    struct {
-        /** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
-         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
-         *  posedge.
-         */
-        uint32_t sync2_bypass:2;
-        /** pad_driver : R/W; bitpos: [2]; default: 0;
-         *  set this bit to select pad driver. 1:open-drain. 0:normal.
-         */
-        uint32_t pad_driver:1;
-        /** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
-         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
-         *  posedge.
-         */
-        uint32_t sync1_bypass:2;
-        uint32_t reserved_5:2;
-        /** int_type : R/W; bitpos: [9:7]; default: 0;
-         *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
-         *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
-         *  at high level
-         */
-        uint32_t int_type:3;
-        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
-         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-         */
-        uint32_t wakeup_enable:1;
-        /** config : R/W; bitpos: [12:11]; default: 0;
-         *  reserved
-         */
-        uint32_t config:2;
-        /** int_ena : R/W; bitpos: [17:13]; default: 0;
-         *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-         *  interrupt.
-         */
-        uint32_t int_ena:5;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} gpio_pin_reg_t;
-
-/** Type of func_in_sel_cfg register
- *  GPIO input function configuration register
- */
-typedef union {
-    struct {
-        /** in_sel : R/W; bitpos: [5:0]; default: 63;
-         *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
-         *  high level. s=0x3E: set this port always low level.
-         */
-        uint32_t in_sel:6;
-        /** in_inv_sel : R/W; bitpos: [6]; default: 0;
-         *  set this bit to invert input signal. 1:invert. 0:not invert.
-         */
-        uint32_t in_inv_sel:1;
-        /** sig_in_sel : R/W; bitpos: [7]; default: 0;
-         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
-         */
-        uint32_t sig_in_sel:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_func_in_sel_cfg_reg_t;
-
-/** Type of func_out_sel_cfg register
- *  GPIO output function select register
- */
-typedef union {
-    struct {
-        /** out_sel : R/W/SC; bitpos: [8:0]; default: 256;
-         *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
-         *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-         *  GPIO_OUT_REG[n].
-         */
-        uint32_t out_sel:9;
-        /** out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
-         *  set this bit to invert output signal.1:invert.0:not invert.
-         */
-        uint32_t out_inv_sel:1;
-        /** oen_sel : R/W; bitpos: [10]; default: 0;
-         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-         *  enable signal.0:use peripheral output enable signal.
-         */
-        uint32_t oen_sel:1;
-        /** oen_inv_sel : R/W; bitpos: [11]; default: 0;
-         *  set this bit to invert output enable signal.1:invert.0:not invert.
-         */
-        uint32_t oen_inv_sel:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} gpio_func_out_sel_cfg_reg_t;
-
-/** Type of intr_2 register
- *  GPIO interrupt 2 status register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** int_2 : RO; bitpos: [31:0]; default: 0;
-         *  GPIO interrupt 2 status register for GPIO0-31
-         */
-        uint32_t int_2:32;
-    };
-    uint32_t val;
-} gpio_intr_2_reg_t;
-
-/** Type of intr1_2 register
- *  GPIO interrupt 2 status register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** int1_2 : RO; bitpos: [24:0]; default: 0;
-         *  GPIO interrupt 2 status register for GPIO32-56
-         */
-        uint32_t int1_2:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_intr1_2_reg_t;
-
-/** Type of intr_3 register
- *  GPIO interrupt 3 status register for GPIO0-31
- */
-typedef union {
-    struct {
-        /** int_3 : RO; bitpos: [31:0]; default: 0;
-         *  GPIO interrupt 3 status register for GPIO0-31
-         */
-        uint32_t int_3:32;
-    };
-    uint32_t val;
-} gpio_intr_3_reg_t;
-
-/** Type of intr1_3 register
- *  GPIO interrupt 3 status register for GPIO32-56
- */
-typedef union {
-    struct {
-        /** int1_3 : RO; bitpos: [24:0]; default: 0;
-         *  GPIO interrupt 3 status register for GPIO32-56
-         */
-        uint32_t int1_3:25;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} gpio_intr1_3_reg_t;
-
-/** Type of clock_gate register
- *  GPIO clock gate register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 1;
-         *  set this bit to enable GPIO clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} gpio_clock_gate_reg_t;
-
-/** Type of zero_det_filter_cnt register
- *  GPIO analog comparator zero detect filter count
- */
-typedef union {
-    struct {
-        /** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 4294967295;
-         *  GPIO analog comparator zero detect filter count
-         */
-        uint32_t zero_det_filter_cnt:32;
-    };
-    uint32_t val;
-} gpio_zero_det_filter_cnt_reg_t;
-
-/** Type of send_seq register
- *  High speed sdio pad bist send sequence
- */
-typedef union {
-    struct {
-        /** send_seq : R/W; bitpos: [31:0]; default: 305419896;
-         *  High speed sdio pad bist send sequence
-         */
-        uint32_t send_seq:32;
-    };
-    uint32_t val;
-} gpio_send_seq_reg_t;
-
-/** Type of recive_seq register
- *  High speed sdio pad bist recive sequence
- */
-typedef union {
-    struct {
-        /** recive_seq : RO; bitpos: [31:0]; default: 0;
-         *  High speed sdio pad bist recive sequence
-         */
-        uint32_t recive_seq:32;
-    };
-    uint32_t val;
-} gpio_recive_seq_reg_t;
-
-/** Type of bistin_sel register
- *  High speed sdio pad bist in pad sel
- */
-typedef union {
-    struct {
-        /** bistin_sel : R/W; bitpos: [3:0]; default: 15;
-         *  High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
-         */
-        uint32_t bistin_sel:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} gpio_bistin_sel_reg_t;
-
-/** Type of bist_ctrl register
- *  High speed sdio pad bist control
- */
-typedef union {
-    struct {
-        /** bist_pad_oe : R/W; bitpos: [0]; default: 1;
-         *  High speed sdio pad bist out pad oe
-         */
-        uint32_t bist_pad_oe:1;
-        /** bist_start : WT; bitpos: [1]; default: 0;
-         *  High speed sdio pad bist start
-         */
-        uint32_t bist_start:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} gpio_bist_ctrl_reg_t;
-
-/** Type of date register
- *  GPIO version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 2294787;
-         *  version register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_date_reg_t;
-
-
-/** Group: GPIO INT RAW REG */
-/** Type of int_raw register
- *  analog comparator interrupt raw
- */
-typedef union {
-    struct {
-        /** comp0_neg_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  analog comparator pos edge interrupt raw
-         */
-        uint32_t comp0_neg_int_raw:1;
-        /** comp0_pos_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  analog comparator neg edge interrupt raw
-         */
-        uint32_t comp0_pos_int_raw:1;
-        /** comp0_all_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  analog comparator neg or pos edge interrupt raw
-         */
-        uint32_t comp0_all_int_raw:1;
-        /** comp1_neg_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  analog comparator pos edge interrupt raw
-         */
-        uint32_t comp1_neg_int_raw:1;
-        /** comp1_pos_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  analog comparator neg edge interrupt raw
-         */
-        uint32_t comp1_pos_int_raw:1;
-        /** comp1_all_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  analog comparator neg or pos edge interrupt raw
-         */
-        uint32_t comp1_all_int_raw:1;
-        /** bistok_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  pad bistok interrupt raw
-         */
-        uint32_t bistok_int_raw:1;
-        /** bistfail_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  pad bistfail interrupt raw
-         */
-        uint32_t bistfail_int_raw:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_int_raw_reg_t;
-
-
-/** Group: GPIO INT ST REG */
-/** Type of int_st register
- *  analog comparator interrupt status
- */
-typedef union {
-    struct {
-        /** comp0_neg_int_st : RO; bitpos: [0]; default: 0;
-         *  analog comparator pos edge interrupt status
-         */
-        uint32_t comp0_neg_int_st:1;
-        /** comp0_pos_int_st : RO; bitpos: [1]; default: 0;
-         *  analog comparator neg edge interrupt status
-         */
-        uint32_t comp0_pos_int_st:1;
-        /** comp0_all_int_st : RO; bitpos: [2]; default: 0;
-         *  analog comparator neg or pos edge interrupt status
-         */
-        uint32_t comp0_all_int_st:1;
-        /** comp1_neg_int_st : RO; bitpos: [3]; default: 0;
-         *  analog comparator pos edge interrupt status
-         */
-        uint32_t comp1_neg_int_st:1;
-        /** comp1_pos_int_st : RO; bitpos: [4]; default: 0;
-         *  analog comparator neg edge interrupt status
-         */
-        uint32_t comp1_pos_int_st:1;
-        /** comp1_all_int_st : RO; bitpos: [5]; default: 0;
-         *  analog comparator neg or pos edge interrupt status
-         */
-        uint32_t comp1_all_int_st:1;
-        /** bistok_int_st : RO; bitpos: [6]; default: 0;
-         *  pad bistok interrupt status
-         */
-        uint32_t bistok_int_st:1;
-        /** bistfail_int_st : RO; bitpos: [7]; default: 0;
-         *  pad bistfail interrupt status
-         */
-        uint32_t bistfail_int_st:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_int_st_reg_t;
-
-
-/** Group: GPIO INT ENA REG */
-/** Type of int_ena register
- *  analog comparator interrupt enable
- */
-typedef union {
-    struct {
-        /** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1;
-         *  analog comparator pos edge interrupt enable
-         */
-        uint32_t comp0_neg_int_ena:1;
-        /** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1;
-         *  analog comparator neg edge interrupt enable
-         */
-        uint32_t comp0_pos_int_ena:1;
-        /** comp0_all_int_ena : R/W; bitpos: [2]; default: 1;
-         *  analog comparator neg or pos edge interrupt enable
-         */
-        uint32_t comp0_all_int_ena:1;
-        /** comp1_neg_int_ena : R/W; bitpos: [3]; default: 1;
-         *  analog comparator pos edge interrupt enable
-         */
-        uint32_t comp1_neg_int_ena:1;
-        /** comp1_pos_int_ena : R/W; bitpos: [4]; default: 1;
-         *  analog comparator neg edge interrupt enable
-         */
-        uint32_t comp1_pos_int_ena:1;
-        /** comp1_all_int_ena : R/W; bitpos: [5]; default: 1;
-         *  analog comparator neg or pos edge interrupt enable
-         */
-        uint32_t comp1_all_int_ena:1;
-        /** bistok_int_ena : R/W; bitpos: [6]; default: 1;
-         *  pad bistok interrupt enable
-         */
-        uint32_t bistok_int_ena:1;
-        /** bistfail_int_ena : R/W; bitpos: [7]; default: 1;
-         *  pad bistfail interrupt enable
-         */
-        uint32_t bistfail_int_ena:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_int_ena_reg_t;
-
-
-/** Group: GPIO INT CLR REG */
-/** Type of int_clr register
- *  analog comparator interrupt clear
- */
-typedef union {
-    struct {
-        /** comp0_neg_int_clr : WT; bitpos: [0]; default: 0;
-         *  analog comparator pos edge interrupt clear
-         */
-        uint32_t comp0_neg_int_clr:1;
-        /** comp0_pos_int_clr : WT; bitpos: [1]; default: 0;
-         *  analog comparator neg edge interrupt clear
-         */
-        uint32_t comp0_pos_int_clr:1;
-        /** comp0_all_int_clr : WT; bitpos: [2]; default: 0;
-         *  analog comparator neg or pos edge interrupt clear
-         */
-        uint32_t comp0_all_int_clr:1;
-        /** comp1_neg_int_clr : WT; bitpos: [3]; default: 0;
-         *  analog comparator pos edge interrupt clear
-         */
-        uint32_t comp1_neg_int_clr:1;
-        /** comp1_pos_int_clr : WT; bitpos: [4]; default: 0;
-         *  analog comparator neg edge interrupt clear
-         */
-        uint32_t comp1_pos_int_clr:1;
-        /** comp1_all_int_clr : WT; bitpos: [5]; default: 0;
-         *  analog comparator neg or pos edge interrupt clear
-         */
-        uint32_t comp1_all_int_clr:1;
-        /** bistok_int_clr : WT; bitpos: [6]; default: 0;
-         *  pad bistok interrupt enable
-         */
-        uint32_t bistok_int_clr:1;
-        /** bistfail_int_clr : WT; bitpos: [7]; default: 0;
-         *  pad bistfail interrupt enable
-         */
-        uint32_t bistfail_int_clr:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} gpio_int_clr_reg_t;
-
-
-typedef struct gpio_dev_t {
-    volatile gpio_bt_select_reg_t bt_select;
-    volatile gpio_out_reg_t out;
-    volatile gpio_out_w1ts_reg_t out_w1ts;
-    volatile gpio_out_w1tc_reg_t out_w1tc;
-    volatile gpio_out1_reg_t out1;
-    volatile gpio_out1_w1ts_reg_t out1_w1ts;
-    volatile gpio_out1_w1tc_reg_t out1_w1tc;
-    uint32_t reserved_01c;
-    volatile gpio_enable_reg_t enable;
-    volatile gpio_enable_w1ts_reg_t enable_w1ts;
-    volatile gpio_enable_w1tc_reg_t enable_w1tc;
-    volatile gpio_enable1_reg_t enable1;
-    volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
-    volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
-    volatile gpio_strap_reg_t strap;
-    volatile gpio_in_reg_t in;
-    volatile gpio_in1_reg_t in1;
-    volatile gpio_status_reg_t status;
-    volatile gpio_status_w1ts_reg_t status_w1ts;
-    volatile gpio_status_w1tc_reg_t status_w1tc;
-    volatile gpio_status1_reg_t status1;
-    volatile gpio_status1_w1ts_reg_t status1_w1ts;
-    volatile gpio_status1_w1tc_reg_t status1_w1tc;
-    volatile gpio_intr_0_reg_t intr_0;
-    volatile gpio_intr1_0_reg_t intr1_0;
-    volatile gpio_intr_1_reg_t intr_1;
-    volatile gpio_intr1_1_reg_t intr1_1;
-    volatile gpio_status_next_reg_t status_next;
-    volatile gpio_status_next1_reg_t status_next1;
-    volatile gpio_pin_reg_t pin[57];
-    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; /* func0-func255: reserved for func0, 46, 67, 72, 73, 79, 81, 82, 84, 85, 87, 88, 115, 116, 119-125, 157, 204-213 */
-    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[57];
-    volatile gpio_intr_2_reg_t intr_2;
-    volatile gpio_intr1_2_reg_t intr1_2;
-    volatile gpio_intr_3_reg_t intr_3;
-    volatile gpio_intr1_3_reg_t intr1_3;
-    volatile gpio_clock_gate_reg_t clock_gate;
-    uint32_t reserved_650[44];
-    volatile gpio_int_raw_reg_t int_raw;
-    volatile gpio_int_st_reg_t int_st;
-    volatile gpio_int_ena_reg_t int_ena;
-    volatile gpio_int_clr_reg_t int_clr;
-    volatile gpio_zero_det_filter_cnt_reg_t zero_det_filter_cnt[2];
-    volatile gpio_send_seq_reg_t send_seq;
-    volatile gpio_recive_seq_reg_t recive_seq;
-    volatile gpio_bistin_sel_reg_t bistin_sel;
-    volatile gpio_bist_ctrl_reg_t bist_ctrl;
-    uint32_t reserved_728[53];
-    volatile gpio_date_reg_t date;
-} gpio_dev_t;
-
-extern gpio_dev_t GPIO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(gpio_dev_t) == 0x800, "Invalid size of gpio_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/hp_system_reg.h b/components/soc/esp32p4/include/soc/hp_system_reg.h
deleted file mode 100644
index ec9b55a793a..00000000000
--- a/components/soc/esp32p4/include/soc/hp_system_reg.h
+++ /dev/null
@@ -1,1977 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** HP_SYSTEM_VER_DATE_REG register
- *  NA
- */
-#define HP_SYSTEM_VER_DATE_REG (DR_REG_HP_SYS_BASE + 0x0)
-/** HP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165977;
- *  NA
- */
-#define HP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
-#define HP_SYSTEM_REG_VER_DATE_M  (HP_SYSTEM_REG_VER_DATE_V << HP_SYSTEM_REG_VER_DATE_S)
-#define HP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
-#define HP_SYSTEM_REG_VER_DATE_S  0
-
-/** HP_SYSTEM_CLK_EN_REG register
- *  NA
- */
-#define HP_SYSTEM_CLK_EN_REG (DR_REG_HP_SYS_BASE + 0x4)
-/** HP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_CLK_EN    (BIT(0))
-#define HP_SYSTEM_REG_CLK_EN_M  (HP_SYSTEM_REG_CLK_EN_V << HP_SYSTEM_REG_CLK_EN_S)
-#define HP_SYSTEM_REG_CLK_EN_V  0x00000001U
-#define HP_SYSTEM_REG_CLK_EN_S  0
-
-/** HP_SYSTEM_CPU_INT_FROM_CPU_0_REG register
- *  NA
- */
-#define HP_SYSTEM_CPU_INT_FROM_CPU_0_REG (DR_REG_HP_SYS_BASE + 0x10)
-/** HP_SYSTEM_CPU_INT_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
- *  set 1 will triger a interrupt
- */
-#define HP_SYSTEM_CPU_INT_FROM_CPU_0    (BIT(0))
-#define HP_SYSTEM_CPU_INT_FROM_CPU_0_M  (HP_SYSTEM_CPU_INT_FROM_CPU_0_V << HP_SYSTEM_CPU_INT_FROM_CPU_0_S)
-#define HP_SYSTEM_CPU_INT_FROM_CPU_0_V  0x00000001U
-#define HP_SYSTEM_CPU_INT_FROM_CPU_0_S  0
-
-/** HP_SYSTEM_CPU_INT_FROM_CPU_1_REG register
- *  NA
- */
-#define HP_SYSTEM_CPU_INT_FROM_CPU_1_REG (DR_REG_HP_SYS_BASE + 0x14)
-/** HP_SYSTEM_CPU_INT_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
- *  set 1 will triger a interrupt
- */
-#define HP_SYSTEM_CPU_INT_FROM_CPU_1    (BIT(0))
-#define HP_SYSTEM_CPU_INT_FROM_CPU_1_M  (HP_SYSTEM_CPU_INT_FROM_CPU_1_V << HP_SYSTEM_CPU_INT_FROM_CPU_1_S)
-#define HP_SYSTEM_CPU_INT_FROM_CPU_1_V  0x00000001U
-#define HP_SYSTEM_CPU_INT_FROM_CPU_1_S  0
-
-/** HP_SYSTEM_CPU_INT_FROM_CPU_2_REG register
- *  NA
- */
-#define HP_SYSTEM_CPU_INT_FROM_CPU_2_REG (DR_REG_HP_SYS_BASE + 0x18)
-/** HP_SYSTEM_CPU_INT_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
- *  set 1 will triger a interrupt
- */
-#define HP_SYSTEM_CPU_INT_FROM_CPU_2    (BIT(0))
-#define HP_SYSTEM_CPU_INT_FROM_CPU_2_M  (HP_SYSTEM_CPU_INT_FROM_CPU_2_V << HP_SYSTEM_CPU_INT_FROM_CPU_2_S)
-#define HP_SYSTEM_CPU_INT_FROM_CPU_2_V  0x00000001U
-#define HP_SYSTEM_CPU_INT_FROM_CPU_2_S  0
-
-/** HP_SYSTEM_CPU_INT_FROM_CPU_3_REG register
- *  NA
- */
-#define HP_SYSTEM_CPU_INT_FROM_CPU_3_REG (DR_REG_HP_SYS_BASE + 0x1c)
-/** HP_SYSTEM_CPU_INT_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
- *  set 1 will triger a interrupt
- */
-#define HP_SYSTEM_CPU_INT_FROM_CPU_3    (BIT(0))
-#define HP_SYSTEM_CPU_INT_FROM_CPU_3_M  (HP_SYSTEM_CPU_INT_FROM_CPU_3_V << HP_SYSTEM_CPU_INT_FROM_CPU_3_S)
-#define HP_SYSTEM_CPU_INT_FROM_CPU_3_V  0x00000001U
-#define HP_SYSTEM_CPU_INT_FROM_CPU_3_S  0
-
-/** HP_SYSTEM_CACHE_CLK_CONFIG_REG register
- *  NA
- */
-#define HP_SYSTEM_CACHE_CLK_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x20)
-/** HP_SYSTEM_REG_L2_CACHE_CLK_ON : R/W; bitpos: [0]; default: 1;
- *  l2 cahce clk enable
- */
-#define HP_SYSTEM_REG_L2_CACHE_CLK_ON    (BIT(0))
-#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L2_CACHE_CLK_ON_V << HP_SYSTEM_REG_L2_CACHE_CLK_ON_S)
-#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_V  0x00000001U
-#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_S  0
-/** HP_SYSTEM_REG_L1_D_CACHE_CLK_ON : R/W; bitpos: [1]; default: 1;
- *  l1 dcahce clk enable
- */
-#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON    (BIT(1))
-#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_V << HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_S)
-#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_V  0x00000001U
-#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_S  1
-/** HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON : R/W; bitpos: [4]; default: 1;
- *  l1 icahce1 clk enable
- */
-#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON    (BIT(4))
-#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_V << HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_S)
-#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_V  0x00000001U
-#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_S  4
-/** HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON : R/W; bitpos: [5]; default: 1;
- *  l1 icahce0 clk enable
- */
-#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON    (BIT(5))
-#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_V << HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_S)
-#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_V  0x00000001U
-#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_S  5
-
-/** HP_SYSTEM_CACHE_RESET_CONFIG_REG register
- *  NA
- */
-#define HP_SYSTEM_CACHE_RESET_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x24)
-/** HP_SYSTEM_REG_L1_D_CACHE_RESET : R/W; bitpos: [1]; default: 0;
- *  set 1 to reset l1 dcahce
- */
-#define HP_SYSTEM_REG_L1_D_CACHE_RESET    (BIT(1))
-#define HP_SYSTEM_REG_L1_D_CACHE_RESET_M  (HP_SYSTEM_REG_L1_D_CACHE_RESET_V << HP_SYSTEM_REG_L1_D_CACHE_RESET_S)
-#define HP_SYSTEM_REG_L1_D_CACHE_RESET_V  0x00000001U
-#define HP_SYSTEM_REG_L1_D_CACHE_RESET_S  1
-/** HP_SYSTEM_REG_L1_I1_CACHE_RESET : R/W; bitpos: [4]; default: 0;
- *  set 1 to reset l1 icahce1
- */
-#define HP_SYSTEM_REG_L1_I1_CACHE_RESET    (BIT(4))
-#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_M  (HP_SYSTEM_REG_L1_I1_CACHE_RESET_V << HP_SYSTEM_REG_L1_I1_CACHE_RESET_S)
-#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_V  0x00000001U
-#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_S  4
-/** HP_SYSTEM_REG_L1_I0_CACHE_RESET : R/W; bitpos: [5]; default: 0;
- *  set 1 to reset l1 icahce0
- */
-#define HP_SYSTEM_REG_L1_I0_CACHE_RESET    (BIT(5))
-#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_M  (HP_SYSTEM_REG_L1_I0_CACHE_RESET_V << HP_SYSTEM_REG_L1_I0_CACHE_RESET_S)
-#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_V  0x00000001U
-#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_S  5
-
-/** HP_SYSTEM_DMA_ADDR_CTRL_REG register
- *  NA
- */
-#define HP_SYSTEM_DMA_ADDR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2c)
-/** HP_SYSTEM_REG_SYS_DMA_ADDR_SEL : R/W; bitpos: [0]; default: 0;
- *  0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx
- */
-#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL    (BIT(0))
-#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_M  (HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_V << HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_S)
-#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_V  0x00000001U
-#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_S  0
-
-/** HP_SYSTEM_TCM_RAM_WRR_CONFIG_REG register
- *  NA
- */
-#define HP_SYSTEM_TCM_RAM_WRR_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x34)
-/** HP_SYSTEM_REG_TCM_RAM_IBUS0_WT : R/W; bitpos: [2:0]; default: 7;
- *  weight value of ibus0
- */
-#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_M  (HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_V << HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_S  0
-/** HP_SYSTEM_REG_TCM_RAM_IBUS1_WT : R/W; bitpos: [5:3]; default: 7;
- *  weight value of ibus1
- */
-#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_M  (HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_V << HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_S  3
-/** HP_SYSTEM_REG_TCM_RAM_IBUS2_WT : R/W; bitpos: [8:6]; default: 4;
- *  weight value of ibus2
- */
-#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_M  (HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_V << HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_S  6
-/** HP_SYSTEM_REG_TCM_RAM_IBUS3_WT : R/W; bitpos: [11:9]; default: 4;
- *  weight value of ibus3
- */
-#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_M  (HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_V << HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_S  9
-/** HP_SYSTEM_REG_TCM_RAM_DBUS0_WT : R/W; bitpos: [14:12]; default: 5;
- *  weight value of dbus0
- */
-#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_M  (HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_V << HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_S  12
-/** HP_SYSTEM_REG_TCM_RAM_DBUS1_WT : R/W; bitpos: [17:15]; default: 5;
- *  weight value of dbus1
- */
-#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_M  (HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_V << HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_S  15
-/** HP_SYSTEM_REG_TCM_RAM_DBUS2_WT : R/W; bitpos: [20:18]; default: 3;
- *  weight value of dbus2
- */
-#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_M  (HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_V << HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_S  18
-/** HP_SYSTEM_REG_TCM_RAM_DBUS3_WT : R/W; bitpos: [23:21]; default: 3;
- *  weight value of dbus3
- */
-#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_M  (HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_V << HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_S  21
-/** HP_SYSTEM_REG_TCM_RAM_DMA_WT : R/W; bitpos: [26:24]; default: 2;
- *  weight value of dma
- */
-#define HP_SYSTEM_REG_TCM_RAM_DMA_WT    0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_M  (HP_SYSTEM_REG_TCM_RAM_DMA_WT_V << HP_SYSTEM_REG_TCM_RAM_DMA_WT_S)
-#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_V  0x00000007U
-#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_S  24
-/** HP_SYSTEM_REG_TCM_RAM_WRR_HIGH : R/W; bitpos: [31]; default: 1;
- *  enable weighted round robin arbitration
- */
-#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH    (BIT(31))
-#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_M  (HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_V << HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_S)
-#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_V  0x00000001U
-#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_S  31
-
-/** HP_SYSTEM_TCM_SW_PARITY_BWE_MASK_REG register
- *  NA
- */
-#define HP_SYSTEM_TCM_SW_PARITY_BWE_MASK_REG (DR_REG_HP_SYS_BASE + 0x38)
-/** HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL : R/W; bitpos: [0]; default: 0;
- *  Set 1 to mask tcm bwe parity code bit
- */
-#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL    (BIT(0))
-#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_M  (HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_V << HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_S)
-#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_V  0x00000001U
-#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_S  0
-
-/** HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG register
- *  NA
- */
-#define HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x3c)
-/** HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  HP_SYSTEM_tcm clk gatig force on
- */
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON    (BIT(0))
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_S  0
-
-/** HP_SYSTEM_L2_ROM_PWR_CTRL0_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_ROM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x40)
-/** HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  l2_rom clk gating force on
- */
-#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON    (BIT(0))
-#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_V << HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_S  0
-
-/** HP_SYSTEM_PROBEA_CTRL_REG register
- *  NA
- */
-#define HP_SYSTEM_PROBEA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x50)
-/** HP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
- *  Tihs field is used to selec probe_group from probe_group0 to probe_group15 for
- *  module's probe_out[31:0] in a mode
- */
-#define HP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
-#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (HP_SYSTEM_REG_PROBE_A_MOD_SEL_V << HP_SYSTEM_REG_PROBE_A_MOD_SEL_S)
-#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
-#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
-/** HP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
- *  Tihs field is used to selec module's probe_out[31:0] as probe out in a mode
- */
-#define HP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
-#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_A_TOP_SEL_V << HP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
-#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
-#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
-/** HP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
- *  Tihs field is used to selec probe_out[31:16]
- */
-#define HP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
-#define HP_SYSTEM_REG_PROBE_L_SEL_M  (HP_SYSTEM_REG_PROBE_L_SEL_V << HP_SYSTEM_REG_PROBE_L_SEL_S)
-#define HP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
-#define HP_SYSTEM_REG_PROBE_L_SEL_S  24
-/** HP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
- *  Tihs field is used to selec probe_out[31:16]
- */
-#define HP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
-#define HP_SYSTEM_REG_PROBE_H_SEL_M  (HP_SYSTEM_REG_PROBE_H_SEL_V << HP_SYSTEM_REG_PROBE_H_SEL_S)
-#define HP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
-#define HP_SYSTEM_REG_PROBE_H_SEL_S  26
-/** HP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
- *  Set this bit to enable global debug probe in hp system.
- */
-#define HP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
-#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (HP_SYSTEM_REG_PROBE_GLOBAL_EN_V << HP_SYSTEM_REG_PROBE_GLOBAL_EN_S)
-#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
-#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
-
-/** HP_SYSTEM_PROBEB_CTRL_REG register
- *  NA
- */
-#define HP_SYSTEM_PROBEB_CTRL_REG (DR_REG_HP_SYS_BASE + 0x54)
-/** HP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
- *  Tihs field is used to selec probe_group from probe_group0 to probe_group15 for
- *  module's probe_out[31:0] in b mode.
- */
-#define HP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
-#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (HP_SYSTEM_REG_PROBE_B_MOD_SEL_V << HP_SYSTEM_REG_PROBE_B_MOD_SEL_S)
-#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
-#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
-/** HP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
- *  Tihs field is used to select module's probe_out[31:0]  as probe_out in b mode
- */
-#define HP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
-#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_B_TOP_SEL_V << HP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
-#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
-#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
-/** HP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
- *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
- */
-#define HP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
-#define HP_SYSTEM_REG_PROBE_B_EN_M  (HP_SYSTEM_REG_PROBE_B_EN_V << HP_SYSTEM_REG_PROBE_B_EN_S)
-#define HP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
-#define HP_SYSTEM_REG_PROBE_B_EN_S  24
-
-/** HP_SYSTEM_PROBE_OUT_REG register
- *  NA
- */
-#define HP_SYSTEM_PROBE_OUT_REG (DR_REG_HP_SYS_BASE + 0x5c)
-/** HP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
-#define HP_SYSTEM_REG_PROBE_TOP_OUT_M  (HP_SYSTEM_REG_PROBE_TOP_OUT_V << HP_SYSTEM_REG_PROBE_TOP_OUT_S)
-#define HP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
-#define HP_SYSTEM_REG_PROBE_TOP_OUT_S  0
-
-/** HP_SYSTEM_L2_MEM_RAM_PWR_CTRL0_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x60)
-/** HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  l2ram clk_gating force on
- */
-#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON    (BIT(0))
-#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_V << HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_S  0
-
-/** HP_SYSTEM_CPU_CORESTALLED_ST_REG register
- *  NA
- */
-#define HP_SYSTEM_CPU_CORESTALLED_ST_REG (DR_REG_HP_SYS_BASE + 0x64)
-/** HP_SYSTEM_REG_CORE0_CORESTALLED_ST : RO; bitpos: [0]; default: 0;
- *  hp core0 corestalled status
- */
-#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST    (BIT(0))
-#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_M  (HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V << HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S)
-#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V  0x00000001U
-#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S  0
-/** HP_SYSTEM_REG_CORE1_CORESTALLED_ST : RO; bitpos: [1]; default: 0;
- *  hp core1 corestalled status
- */
-#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST    (BIT(1))
-#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_M  (HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V << HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S)
-#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V  0x00000001U
-#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S  1
-
-/** HP_SYSTEM_CRYPTO_CTRL_REG register
- *  NA
- */
-#define HP_SYSTEM_CRYPTO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
-/** HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
-#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S)
-#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S  0
-/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
-/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
-/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
-
-/** HP_SYSTEM_GPIO_O_HOLD_CTRL0_REG register
- *  NA
- */
-#define HP_SYSTEM_GPIO_O_HOLD_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x74)
-/** HP_SYSTEM_REG_GPIO_0_HOLD_LOW : R/W; bitpos: [31:0]; default: 0;
- *  hold control for gpio47~16
- */
-#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW    0xFFFFFFFFU
-#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_M  (HP_SYSTEM_REG_GPIO_0_HOLD_LOW_V << HP_SYSTEM_REG_GPIO_0_HOLD_LOW_S)
-#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_V  0xFFFFFFFFU
-#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_S  0
-
-/** HP_SYSTEM_GPIO_O_HOLD_CTRL1_REG register
- *  NA
- */
-#define HP_SYSTEM_GPIO_O_HOLD_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x78)
-/** HP_SYSTEM_REG_GPIO_0_HOLD_HIGH : R/W; bitpos: [8:0]; default: 0;
- *  hold control for gpio56~48
- */
-#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH    0x000001FFU
-#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_M  (HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_V << HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_S)
-#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_V  0x000001FFU
-#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_S  0
-
-/** HP_SYSTEM_RDN_ECO_CS_REG register
- *  NA
- */
-#define HP_SYSTEM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0x7c)
-/** HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN    (BIT(0))
-#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_M  (HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_V << HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_S)
-#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_V  0x00000001U
-#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_S  0
-/** HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT    (BIT(1))
-#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_S)
-#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_V  0x00000001U
-#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_S  1
-
-/** HP_SYSTEM_CACHE_APB_POSTW_EN_REG register
- *  NA
- */
-#define HP_SYSTEM_CACHE_APB_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x80)
-/** HP_SYSTEM_REG_CACHE_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
- *  cache apb register interface post write enable, 1 will speed up write, but will
- *  take some time to update value to register
- */
-#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN    (BIT(0))
-#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_M  (HP_SYSTEM_REG_CACHE_APB_POSTW_EN_V << HP_SYSTEM_REG_CACHE_APB_POSTW_EN_S)
-#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_V  0x00000001U
-#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_S  0
-
-/** HP_SYSTEM_L2_MEM_SUBSIZE_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_SUBSIZE_REG (DR_REG_HP_SYS_BASE + 0x84)
-/** HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE : R/W; bitpos: [1:0]; default: 0;
- *  l2mem sub block size 00=>32 01=>64 10=>128 11=>256
- */
-#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE    0x00000003U
-#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_M  (HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_V << HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_S)
-#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_V  0x00000003U
-#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_S  0
-
-/** HP_SYSTEM_L2_MEM_INT_RAW_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x9c)
-/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  intr triggered when two bit error detected and corrected from ecc
- */
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW    (BIT(0))
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_S)
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_S  0
-/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds
- *  0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode
- */
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW    (BIT(1))
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_S)
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_S  1
-/** HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  intr triggered when err response occurs
- */
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW    (BIT(2))
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_M  (HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_V << HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_S)
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_S  2
-
-/** HP_SYSTEM_L2_MEM_INT_ST_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_INT_ST_REG (DR_REG_HP_SYS_BASE + 0xa0)
-/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST : RO; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST    (BIT(0))
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_S)
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_S  0
-/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST : RO; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST    (BIT(1))
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_S)
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_S  1
-/** HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST : RO; bitpos: [2]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST    (BIT(2))
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_M  (HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_V << HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_S)
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_S  2
-
-/** HP_SYSTEM_L2_MEM_INT_ENA_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0xa4)
-/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA    (BIT(0))
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_S)
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_S  0
-/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA    (BIT(1))
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_S)
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_S  1
-/** HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA    (BIT(2))
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_M  (HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_V << HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_S)
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_S  2
-
-/** HP_SYSTEM_L2_MEM_INT_CLR_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0xa8)
-/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR    (BIT(0))
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_S)
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_S  0
-/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR : WT; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR    (BIT(1))
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_S)
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_S  1
-/** HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR : WT; bitpos: [2]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR    (BIT(2))
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_M  (HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_V << HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_S)
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_S  2
-
-/** HP_SYSTEM_L2_MEM_L2_RAM_ECC_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_L2_RAM_ECC_REG (DR_REG_HP_SYS_BASE + 0xac)
-/** HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN    (BIT(0))
-#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_S)
-#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_S  0
-/** HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN : R/W; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN    (BIT(1))
-#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_S)
-#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_S  1
-/** HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN : R/W; bitpos: [2]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN    (BIT(2))
-#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_S)
-#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_S  2
-/** HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN : R/W; bitpos: [3]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN    (BIT(3))
-#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_S)
-#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_S  3
-/** HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN : R/W; bitpos: [4]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN    (BIT(4))
-#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_S)
-#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_S  4
-/** HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN : R/W; bitpos: [5]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN    (BIT(5))
-#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_S)
-#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_S  5
-
-/** HP_SYSTEM_L2_MEM_INT_RECORD0_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_INT_RECORD0_REG (DR_REG_HP_SYS_BASE + 0xb0)
-/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR : RO; bitpos: [20:0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR    0x001FFFFFU
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_S)
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_V  0x001FFFFFU
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_S  0
-/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE : RO; bitpos: [21]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE    (BIT(21))
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_S)
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_S  21
-/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER : RO; bitpos: [24:22]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER    0x00000007U
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_S)
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_V  0x00000007U
-#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_S  22
-
-/** HP_SYSTEM_L2_MEM_INT_RECORD1_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_INT_RECORD1_REG (DR_REG_HP_SYS_BASE + 0xb4)
-/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR : RO; bitpos: [14:0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR    0x00007FFFU
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_S)
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_V  0x00007FFFU
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_S  0
-/** HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR : RO; bitpos: [15]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR    (BIT(15))
-#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_M  (HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_V << HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_S)
-#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_S  15
-/** HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR : RO; bitpos: [16]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR    (BIT(16))
-#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_M  (HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_V << HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_S)
-#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_S  16
-/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT : RO; bitpos: [25:17]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT    0x000001FFU
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_S)
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_V  0x000001FFU
-#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_S  17
-/** HP_SYSTEM_REG_L2_CACHE_ERR_BANK : RO; bitpos: [26]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK    (BIT(26))
-#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_M  (HP_SYSTEM_REG_L2_CACHE_ERR_BANK_V << HP_SYSTEM_REG_L2_CACHE_ERR_BANK_S)
-#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_V  0x00000001U
-#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_S  26
-
-/** HP_SYSTEM_L2_MEM_L2_CACHE_ECC_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_L2_CACHE_ECC_REG (DR_REG_HP_SYS_BASE + 0xc4)
-/** HP_SYSTEM_REG_L2_CACHE_ECC_EN : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_CACHE_ECC_EN    (BIT(0))
-#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_M  (HP_SYSTEM_REG_L2_CACHE_ECC_EN_V << HP_SYSTEM_REG_L2_CACHE_ECC_EN_S)
-#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_S  0
-
-/** HP_SYSTEM_L1CACHE_BUS0_ID_REG register
- *  NA
- */
-#define HP_SYSTEM_L1CACHE_BUS0_ID_REG (DR_REG_HP_SYS_BASE + 0xc8)
-/** HP_SYSTEM_REG_L1_CACHE_BUS0_ID : R/W; bitpos: [3:0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID    0x0000000FU
-#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_M  (HP_SYSTEM_REG_L1_CACHE_BUS0_ID_V << HP_SYSTEM_REG_L1_CACHE_BUS0_ID_S)
-#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_V  0x0000000FU
-#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_S  0
-
-/** HP_SYSTEM_L1CACHE_BUS1_ID_REG register
- *  NA
- */
-#define HP_SYSTEM_L1CACHE_BUS1_ID_REG (DR_REG_HP_SYS_BASE + 0xcc)
-/** HP_SYSTEM_REG_L1_CACHE_BUS1_ID : R/W; bitpos: [3:0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID    0x0000000FU
-#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_M  (HP_SYSTEM_REG_L1_CACHE_BUS1_ID_V << HP_SYSTEM_REG_L1_CACHE_BUS1_ID_S)
-#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_V  0x0000000FU
-#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_S  0
-
-/** HP_SYSTEM_L2_MEM_RDN_ECO_CS_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xd8)
-/** HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN    (BIT(0))
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_M  (HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_V << HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_S)
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_S  0
-/** HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT    (BIT(1))
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_S)
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_S  1
-
-/** HP_SYSTEM_L2_MEM_RDN_ECO_LOW_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xdc)
-/** HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW    0xFFFFFFFFU
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_M  (HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_V << HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_S)
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_S  0
-
-/** HP_SYSTEM_L2_MEM_RDN_ECO_HIGH_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xe0)
-/** HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH    0xFFFFFFFFU
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_M  (HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_V << HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_S)
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_S  0
-
-/** HP_SYSTEM_TCM_RDN_ECO_CS_REG register
- *  NA
- */
-#define HP_SYSTEM_TCM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xe4)
-/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN    (BIT(0))
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_S)
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_V  0x00000001U
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_S  0
-/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT    (BIT(1))
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_S)
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_V  0x00000001U
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_S  1
-
-/** HP_SYSTEM_TCM_RDN_ECO_LOW_REG register
- *  NA
- */
-#define HP_SYSTEM_TCM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xe8)
-/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW    0xFFFFFFFFU
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_S)
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_V  0xFFFFFFFFU
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_S  0
-
-/** HP_SYSTEM_TCM_RDN_ECO_HIGH_REG register
- *  NA
- */
-#define HP_SYSTEM_TCM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xec)
-/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
- *  NA
- */
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH    0xFFFFFFFFU
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_S)
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_V  0xFFFFFFFFU
-#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_S  0
-
-/** HP_SYSTEM_GPIO_DED_HOLD_CTRL_REG register
- *  NA
- */
-#define HP_SYSTEM_GPIO_DED_HOLD_CTRL_REG (DR_REG_HP_SYS_BASE + 0xf0)
-/** HP_SYSTEM_REG_GPIO_DED_HOLD : R/W; bitpos: [25:0]; default: 0;
- *  hold control for gpio63~56
- */
-#define HP_SYSTEM_REG_GPIO_DED_HOLD    0x03FFFFFFU
-#define HP_SYSTEM_REG_GPIO_DED_HOLD_M  (HP_SYSTEM_REG_GPIO_DED_HOLD_V << HP_SYSTEM_REG_GPIO_DED_HOLD_S)
-#define HP_SYSTEM_REG_GPIO_DED_HOLD_V  0x03FFFFFFU
-#define HP_SYSTEM_REG_GPIO_DED_HOLD_S  0
-
-/** HP_SYSTEM_L2_MEM_SW_ECC_BWE_MASK_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_SW_ECC_BWE_MASK_REG (DR_REG_HP_SYS_BASE + 0xf4)
-/** HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL : R/W; bitpos: [0]; default: 0;
- *  Set 1 to mask bwe hamming code bit
- */
-#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL    (BIT(0))
-#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_M  (HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_V << HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_S)
-#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_S  0
-
-/** HP_SYSTEM_USB20OTG_MEM_CTRL_REG register
- *  NA
- */
-#define HP_SYSTEM_USB20OTG_MEM_CTRL_REG (DR_REG_HP_SYS_BASE + 0xf8)
-/** HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON    (BIT(0))
-#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_V << HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_S  0
-
-/** HP_SYSTEM_TCM_INT_RAW_REG register
- *  need_des
- */
-#define HP_SYSTEM_TCM_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0xfc)
-/** HP_SYSTEM_TCM_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
- *  need_des
- */
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW    (BIT(31))
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_V << HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_S)
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_S  31
-
-/** HP_SYSTEM_TCM_INT_ST_REG register
- *  need_des
- */
-#define HP_SYSTEM_TCM_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x100)
-/** HP_SYSTEM_TCM_PARITY_ERR_INT_ST : RO; bitpos: [31]; default: 0;
- *  need_des
- */
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST    (BIT(31))
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_ST_V << HP_SYSTEM_TCM_PARITY_ERR_INT_ST_S)
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_V  0x00000001U
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_S  31
-
-/** HP_SYSTEM_TCM_INT_ENA_REG register
- *  need_des
- */
-#define HP_SYSTEM_TCM_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x104)
-/** HP_SYSTEM_TCM_PARITY_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA    (BIT(31))
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_V << HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_S)
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_S  31
-
-/** HP_SYSTEM_TCM_INT_CLR_REG register
- *  need_des
- */
-#define HP_SYSTEM_TCM_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x108)
-/** HP_SYSTEM_TCM_PARITY_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR    (BIT(31))
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_V << HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_S)
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_S  31
-
-/** HP_SYSTEM_TCM_PARITY_INT_RECORD_REG register
- *  need_des
- */
-#define HP_SYSTEM_TCM_PARITY_INT_RECORD_REG (DR_REG_HP_SYS_BASE + 0x10c)
-/** HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR : RO; bitpos: [12:0]; default: 0;
- *  hp tcm_parity_err_addr
- */
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR    0x00001FFFU
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_V << HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_S)
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_V  0x00001FFFU
-#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_S  0
-
-/** HP_SYSTEM_L1_CACHE_PWR_CTRL_REG register
- *  NA
- */
-#define HP_SYSTEM_L1_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x110)
-/** HP_SYSTEM_REG_L1_CACHE_MEM_FO : R/W; bitpos: [5:0]; default: 0;
- *  need_des
- */
-#define HP_SYSTEM_REG_L1_CACHE_MEM_FO    0x0000003FU
-#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_M  (HP_SYSTEM_REG_L1_CACHE_MEM_FO_V << HP_SYSTEM_REG_L1_CACHE_MEM_FO_S)
-#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_V  0x0000003FU
-#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_S  0
-
-/** HP_SYSTEM_L2_CACHE_PWR_CTRL_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x114)
-/** HP_SYSTEM_REG_L2_CACHE_MEM_FO : R/W; bitpos: [1:0]; default: 0;
- *  need_des
- */
-#define HP_SYSTEM_REG_L2_CACHE_MEM_FO    0x00000003U
-#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_M  (HP_SYSTEM_REG_L2_CACHE_MEM_FO_V << HP_SYSTEM_REG_L2_CACHE_MEM_FO_S)
-#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_V  0x00000003U
-#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_S  0
-
-/** HP_SYSTEM_CPU_WAITI_CONF_REG register
- *  CPU_WAITI configuration register
- */
-#define HP_SYSTEM_CPU_WAITI_CONF_REG (DR_REG_HP_SYS_BASE + 0x118)
-/** HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [0]; default: 1;
- *  Set 1 to force cpu_waiti_clk enable.
- */
-#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(0))
-#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S)
-#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  0
-/** HP_SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [4:1]; default: 0;
- *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
- *  will close
- */
-#define HP_SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000FU
-#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_M  (HP_SYSTEM_CPU_WAITI_DELAY_NUM_V << HP_SYSTEM_CPU_WAITI_DELAY_NUM_S)
-#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000FU
-#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_S  1
-
-/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
- *  Core Debug runstall configure register
- */
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x11c)
-/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
- */
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
-#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S  0
-
-/** HP_SYSTEM_CORE_AHB_TIMEOUT_REG register
- *  need_des
- */
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x120)
-/** HP_SYSTEM_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable hp core0&1 ahb timeout handle
- */
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN    (BIT(0))
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_M  (HP_SYSTEM_CORE_AHB_TIMEOUT_EN_V << HP_SYSTEM_CORE_AHB_TIMEOUT_EN_S)
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_V  0x00000001U
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_S  0
-/** HP_SYSTEM_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set hp core0&1 ahb bus timeout  threshold
- */
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_V << HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_S)
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_S  1
-
-/** HP_SYSTEM_CORE_IBUS_TIMEOUT_REG register
- *  need_des
- */
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x124)
-/** HP_SYSTEM_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable hp core0&1 ibus timeout handle
- */
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN    (BIT(0))
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_M  (HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_V << HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_S)
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_S  0
-/** HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set hp core0&1 ibus timeout  threshold
- */
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V << HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S)
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S  1
-
-/** HP_SYSTEM_CORE_DBUS_TIMEOUT_REG register
- *  need_des
- */
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x128)
-/** HP_SYSTEM_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
- *  set this field to 1 to enable hp core0&1 dbus timeout handle
- */
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN    (BIT(0))
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_M  (HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_V << HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_S)
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_S  0
-/** HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
- *  This field used to set hp core0&1 dbus timeout  threshold
- */
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V << HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S)
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
-#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S  1
-
-/** HP_SYSTEM_ICM_CPU_H2X_CFG_REG register
- *  need_des
- */
-#define HP_SYSTEM_ICM_CPU_H2X_CFG_REG (DR_REG_HP_SYS_BASE + 0x138)
-/** HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN : R/W; bitpos: [0]; default: 1;
- *  need_des
- */
-#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN    (BIT(0))
-#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_M  (HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V << HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S)
-#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V  0x00000001U
-#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S  0
-/** HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN : R/W; bitpos: [1]; default: 1;
- *  need_des
- */
-#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN    (BIT(1))
-#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_M  (HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V << HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S)
-#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V  0x00000001U
-#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S  1
-/** HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY : RO; bitpos: [2]; default: 0;
- *  need_des
- */
-#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY    (BIT(2))
-#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_M  (HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V << HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S)
-#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V  0x00000001U
-#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S  2
-
-/** HP_SYSTEM_PERI1_APB_POSTW_EN_REG register
- *  NA
- */
-#define HP_SYSTEM_PERI1_APB_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x13c)
-/** HP_SYSTEM_PERI1_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
- *  HP_SYSTEM_peri1 apb register interface post write enable, 1 will speed up write, but will
- *  take some time to update value to register
- */
-#define HP_SYSTEM_PERI1_APB_POSTW_EN    (BIT(0))
-#define HP_SYSTEM_PERI1_APB_POSTW_EN_M  (HP_SYSTEM_PERI1_APB_POSTW_EN_V << HP_SYSTEM_PERI1_APB_POSTW_EN_S)
-#define HP_SYSTEM_PERI1_APB_POSTW_EN_V  0x00000001U
-#define HP_SYSTEM_PERI1_APB_POSTW_EN_S  0
-
-/** HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register
- *  Bitscrambler Peri Sel
- */
-#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYS_BASE + 0x140)
-/** HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL : R/W; bitpos: [3:0]; default: 15;
- *  Set  this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0
- *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
- *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
- *  else : none
- */
-#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL    0x0000000FU
-#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_M  (HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V << HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S)
-#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V  0x0000000FU
-#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S  0
-/** HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL : R/W; bitpos: [7:4]; default: 15;
- *  Set  this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0
- *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
- *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
- *  else : none
- */
-#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL    0x0000000FU
-#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_M  (HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V << HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S)
-#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V  0x0000000FU
-#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S  4
-
-/** HP_SYSTEM_APB_SYNC_POSTW_EN_REG register
- *  N/A
- */
-#define HP_SYSTEM_APB_SYNC_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x144)
-/** HP_SYSTEM_GMAC_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_GMAC_APB_POSTW_EN    (BIT(0))
-#define HP_SYSTEM_GMAC_APB_POSTW_EN_M  (HP_SYSTEM_GMAC_APB_POSTW_EN_V << HP_SYSTEM_GMAC_APB_POSTW_EN_S)
-#define HP_SYSTEM_GMAC_APB_POSTW_EN_V  0x00000001U
-#define HP_SYSTEM_GMAC_APB_POSTW_EN_S  0
-/** HP_SYSTEM_DSI_HOST_APB_POSTW_EN : R/W; bitpos: [1]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_DSI_HOST_APB_POSTW_EN    (BIT(1))
-#define HP_SYSTEM_DSI_HOST_APB_POSTW_EN_M  (HP_SYSTEM_DSI_HOST_APB_POSTW_EN_V << HP_SYSTEM_DSI_HOST_APB_POSTW_EN_S)
-#define HP_SYSTEM_DSI_HOST_APB_POSTW_EN_V  0x00000001U
-#define HP_SYSTEM_DSI_HOST_APB_POSTW_EN_S  1
-/** HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN : R/W; bitpos: [2]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN    (BIT(2))
-#define HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_M  (HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_V << HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_S)
-#define HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_V  0x00000001U
-#define HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_S  2
-/** HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN : R/W; bitpos: [3]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN    (BIT(3))
-#define HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_M  (HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_V << HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_S)
-#define HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_V  0x00000001U
-#define HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_S  3
-
-/** HP_SYSTEM_GDMA_CTRL_REG register
- *  N/A
- */
-#define HP_SYSTEM_GDMA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x148)
-/** HP_SYSTEM_DEBUG_CH_NUM : R/W; bitpos: [1:0]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_DEBUG_CH_NUM    0x00000003U
-#define HP_SYSTEM_DEBUG_CH_NUM_M  (HP_SYSTEM_DEBUG_CH_NUM_V << HP_SYSTEM_DEBUG_CH_NUM_S)
-#define HP_SYSTEM_DEBUG_CH_NUM_V  0x00000003U
-#define HP_SYSTEM_DEBUG_CH_NUM_S  0
-
-/** HP_SYSTEM_GMAC_CTRL0_REG register
- *  N/A
- */
-#define HP_SYSTEM_GMAC_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x14c)
-/** HP_SYSTEM_PTP_PPS : RO; bitpos: [0]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PTP_PPS    (BIT(0))
-#define HP_SYSTEM_PTP_PPS_M  (HP_SYSTEM_PTP_PPS_V << HP_SYSTEM_PTP_PPS_S)
-#define HP_SYSTEM_PTP_PPS_V  0x00000001U
-#define HP_SYSTEM_PTP_PPS_S  0
-/** HP_SYSTEM_SBD_FLOWCTRL : R/W; bitpos: [1]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_SBD_FLOWCTRL    (BIT(1))
-#define HP_SYSTEM_SBD_FLOWCTRL_M  (HP_SYSTEM_SBD_FLOWCTRL_V << HP_SYSTEM_SBD_FLOWCTRL_S)
-#define HP_SYSTEM_SBD_FLOWCTRL_V  0x00000001U
-#define HP_SYSTEM_SBD_FLOWCTRL_S  1
-/** HP_SYSTEM_PHY_INTF_SEL : R/W; bitpos: [4:2]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PHY_INTF_SEL    0x00000007U
-#define HP_SYSTEM_PHY_INTF_SEL_M  (HP_SYSTEM_PHY_INTF_SEL_V << HP_SYSTEM_PHY_INTF_SEL_S)
-#define HP_SYSTEM_PHY_INTF_SEL_V  0x00000007U
-#define HP_SYSTEM_PHY_INTF_SEL_S  2
-/** HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON    (BIT(5))
-#define HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_V << HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_S  5
-/** HP_SYSTEM_GMAC_RST_CLK_TX_N : RO; bitpos: [6]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_GMAC_RST_CLK_TX_N    (BIT(6))
-#define HP_SYSTEM_GMAC_RST_CLK_TX_N_M  (HP_SYSTEM_GMAC_RST_CLK_TX_N_V << HP_SYSTEM_GMAC_RST_CLK_TX_N_S)
-#define HP_SYSTEM_GMAC_RST_CLK_TX_N_V  0x00000001U
-#define HP_SYSTEM_GMAC_RST_CLK_TX_N_S  6
-/** HP_SYSTEM_GMAC_RST_CLK_RX_N : RO; bitpos: [7]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_GMAC_RST_CLK_RX_N    (BIT(7))
-#define HP_SYSTEM_GMAC_RST_CLK_RX_N_M  (HP_SYSTEM_GMAC_RST_CLK_RX_N_V << HP_SYSTEM_GMAC_RST_CLK_RX_N_S)
-#define HP_SYSTEM_GMAC_RST_CLK_RX_N_V  0x00000001U
-#define HP_SYSTEM_GMAC_RST_CLK_RX_N_S  7
-
-/** HP_SYSTEM_GMAC_CTRL1_REG register
- *  N/A
- */
-#define HP_SYSTEM_GMAC_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x150)
-/** HP_SYSTEM_PTP_TIMESTAMP_L : RO; bitpos: [31:0]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PTP_TIMESTAMP_L    0xFFFFFFFFU
-#define HP_SYSTEM_PTP_TIMESTAMP_L_M  (HP_SYSTEM_PTP_TIMESTAMP_L_V << HP_SYSTEM_PTP_TIMESTAMP_L_S)
-#define HP_SYSTEM_PTP_TIMESTAMP_L_V  0xFFFFFFFFU
-#define HP_SYSTEM_PTP_TIMESTAMP_L_S  0
-
-/** HP_SYSTEM_GMAC_CTRL2_REG register
- *  N/A
- */
-#define HP_SYSTEM_GMAC_CTRL2_REG (DR_REG_HP_SYS_BASE + 0x154)
-/** HP_SYSTEM_PTP_TIMESTAMP_H : RO; bitpos: [31:0]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PTP_TIMESTAMP_H    0xFFFFFFFFU
-#define HP_SYSTEM_PTP_TIMESTAMP_H_M  (HP_SYSTEM_PTP_TIMESTAMP_H_V << HP_SYSTEM_PTP_TIMESTAMP_H_S)
-#define HP_SYSTEM_PTP_TIMESTAMP_H_V  0xFFFFFFFFU
-#define HP_SYSTEM_PTP_TIMESTAMP_H_S  0
-
-/** HP_SYSTEM_VPU_CTRL_REG register
- *  N/A
- */
-#define HP_SYSTEM_VPU_CTRL_REG (DR_REG_HP_SYS_BASE + 0x158)
-/** HP_SYSTEM_PPA_LSLP_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PPA_LSLP_MEM_PD    (BIT(0))
-#define HP_SYSTEM_PPA_LSLP_MEM_PD_M  (HP_SYSTEM_PPA_LSLP_MEM_PD_V << HP_SYSTEM_PPA_LSLP_MEM_PD_S)
-#define HP_SYSTEM_PPA_LSLP_MEM_PD_V  0x00000001U
-#define HP_SYSTEM_PPA_LSLP_MEM_PD_S  0
-/** HP_SYSTEM_JPEG_SDSLP_MEM_PD : R/W; bitpos: [1]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_JPEG_SDSLP_MEM_PD    (BIT(1))
-#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_M  (HP_SYSTEM_JPEG_SDSLP_MEM_PD_V << HP_SYSTEM_JPEG_SDSLP_MEM_PD_S)
-#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_V  0x00000001U
-#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_S  1
-/** HP_SYSTEM_JPEG_LSLP_MEM_PD : R/W; bitpos: [2]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_JPEG_LSLP_MEM_PD    (BIT(2))
-#define HP_SYSTEM_JPEG_LSLP_MEM_PD_M  (HP_SYSTEM_JPEG_LSLP_MEM_PD_V << HP_SYSTEM_JPEG_LSLP_MEM_PD_S)
-#define HP_SYSTEM_JPEG_LSLP_MEM_PD_V  0x00000001U
-#define HP_SYSTEM_JPEG_LSLP_MEM_PD_S  2
-/** HP_SYSTEM_JPEG_DSLP_MEM_PD : R/W; bitpos: [3]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_JPEG_DSLP_MEM_PD    (BIT(3))
-#define HP_SYSTEM_JPEG_DSLP_MEM_PD_M  (HP_SYSTEM_JPEG_DSLP_MEM_PD_V << HP_SYSTEM_JPEG_DSLP_MEM_PD_S)
-#define HP_SYSTEM_JPEG_DSLP_MEM_PD_V  0x00000001U
-#define HP_SYSTEM_JPEG_DSLP_MEM_PD_S  3
-/** HP_SYSTEM_DMA2D_LSLP_MEM_PD : R/W; bitpos: [4]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_DMA2D_LSLP_MEM_PD    (BIT(4))
-#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_M  (HP_SYSTEM_DMA2D_LSLP_MEM_PD_V << HP_SYSTEM_DMA2D_LSLP_MEM_PD_S)
-#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_V  0x00000001U
-#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_S  4
-
-/** HP_SYSTEM_USBOTG20_CTRL_REG register
- *  N/A
- */
-#define HP_SYSTEM_USBOTG20_CTRL_REG (DR_REG_HP_SYS_BASE + 0x15c)
-/** HP_SYSTEM_OTG_PHY_TEST_DONE : RO; bitpos: [0]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_OTG_PHY_TEST_DONE    (BIT(0))
-#define HP_SYSTEM_OTG_PHY_TEST_DONE_M  (HP_SYSTEM_OTG_PHY_TEST_DONE_V << HP_SYSTEM_OTG_PHY_TEST_DONE_S)
-#define HP_SYSTEM_OTG_PHY_TEST_DONE_V  0x00000001U
-#define HP_SYSTEM_OTG_PHY_TEST_DONE_S  0
-/** HP_SYSTEM_USB_MEM_AUX_CTRL : R/W; bitpos: [14:1]; default: 4896;
- *  N/A
- */
-#define HP_SYSTEM_USB_MEM_AUX_CTRL    0x00003FFFU
-#define HP_SYSTEM_USB_MEM_AUX_CTRL_M  (HP_SYSTEM_USB_MEM_AUX_CTRL_V << HP_SYSTEM_USB_MEM_AUX_CTRL_S)
-#define HP_SYSTEM_USB_MEM_AUX_CTRL_V  0x00003FFFU
-#define HP_SYSTEM_USB_MEM_AUX_CTRL_S  1
-/** HP_SYSTEM_PHY_SUSPENDM : R/W; bitpos: [15]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PHY_SUSPENDM    (BIT(15))
-#define HP_SYSTEM_PHY_SUSPENDM_M  (HP_SYSTEM_PHY_SUSPENDM_V << HP_SYSTEM_PHY_SUSPENDM_S)
-#define HP_SYSTEM_PHY_SUSPENDM_V  0x00000001U
-#define HP_SYSTEM_PHY_SUSPENDM_S  15
-/** HP_SYSTEM_PHY_SUSPEND_FORCE_EN : R/W; bitpos: [16]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PHY_SUSPEND_FORCE_EN    (BIT(16))
-#define HP_SYSTEM_PHY_SUSPEND_FORCE_EN_M  (HP_SYSTEM_PHY_SUSPEND_FORCE_EN_V << HP_SYSTEM_PHY_SUSPEND_FORCE_EN_S)
-#define HP_SYSTEM_PHY_SUSPEND_FORCE_EN_V  0x00000001U
-#define HP_SYSTEM_PHY_SUSPEND_FORCE_EN_S  16
-/** HP_SYSTEM_PHY_RSTN : R/W; bitpos: [17]; default: 1;
- *  N/A
- */
-#define HP_SYSTEM_PHY_RSTN    (BIT(17))
-#define HP_SYSTEM_PHY_RSTN_M  (HP_SYSTEM_PHY_RSTN_V << HP_SYSTEM_PHY_RSTN_S)
-#define HP_SYSTEM_PHY_RSTN_V  0x00000001U
-#define HP_SYSTEM_PHY_RSTN_S  17
-/** HP_SYSTEM_PHY_RESET_FORCE_EN : R/W; bitpos: [18]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PHY_RESET_FORCE_EN    (BIT(18))
-#define HP_SYSTEM_PHY_RESET_FORCE_EN_M  (HP_SYSTEM_PHY_RESET_FORCE_EN_V << HP_SYSTEM_PHY_RESET_FORCE_EN_S)
-#define HP_SYSTEM_PHY_RESET_FORCE_EN_V  0x00000001U
-#define HP_SYSTEM_PHY_RESET_FORCE_EN_S  18
-/** HP_SYSTEM_PHY_PLL_FORCE_EN : R/W; bitpos: [19]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PHY_PLL_FORCE_EN    (BIT(19))
-#define HP_SYSTEM_PHY_PLL_FORCE_EN_M  (HP_SYSTEM_PHY_PLL_FORCE_EN_V << HP_SYSTEM_PHY_PLL_FORCE_EN_S)
-#define HP_SYSTEM_PHY_PLL_FORCE_EN_V  0x00000001U
-#define HP_SYSTEM_PHY_PLL_FORCE_EN_S  19
-/** HP_SYSTEM_PHY_PLL_EN : R/W; bitpos: [20]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_PHY_PLL_EN    (BIT(20))
-#define HP_SYSTEM_PHY_PLL_EN_M  (HP_SYSTEM_PHY_PLL_EN_V << HP_SYSTEM_PHY_PLL_EN_S)
-#define HP_SYSTEM_PHY_PLL_EN_V  0x00000001U
-#define HP_SYSTEM_PHY_PLL_EN_S  20
-/** HP_SYSTEM_OTG_SUSPENDM : R/W; bitpos: [21]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_OTG_SUSPENDM    (BIT(21))
-#define HP_SYSTEM_OTG_SUSPENDM_M  (HP_SYSTEM_OTG_SUSPENDM_V << HP_SYSTEM_OTG_SUSPENDM_S)
-#define HP_SYSTEM_OTG_SUSPENDM_V  0x00000001U
-#define HP_SYSTEM_OTG_SUSPENDM_S  21
-/** HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN : R/W; bitpos: [22]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN    (BIT(22))
-#define HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_M  (HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_V << HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_S)
-#define HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_V  0x00000001U
-#define HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_S  22
-/** HP_SYSTEM_OTG_PHY_REFCLK_MODE : R/W; bitpos: [23]; default: 1;
- *  N/A
- */
-#define HP_SYSTEM_OTG_PHY_REFCLK_MODE    (BIT(23))
-#define HP_SYSTEM_OTG_PHY_REFCLK_MODE_M  (HP_SYSTEM_OTG_PHY_REFCLK_MODE_V << HP_SYSTEM_OTG_PHY_REFCLK_MODE_S)
-#define HP_SYSTEM_OTG_PHY_REFCLK_MODE_V  0x00000001U
-#define HP_SYSTEM_OTG_PHY_REFCLK_MODE_S  23
-/** HP_SYSTEM_OTG_PHY_BISTEN : R/W; bitpos: [24]; default: 0;
- *  N/A
- */
-#define HP_SYSTEM_OTG_PHY_BISTEN    (BIT(24))
-#define HP_SYSTEM_OTG_PHY_BISTEN_M  (HP_SYSTEM_OTG_PHY_BISTEN_V << HP_SYSTEM_OTG_PHY_BISTEN_S)
-#define HP_SYSTEM_OTG_PHY_BISTEN_V  0x00000001U
-#define HP_SYSTEM_OTG_PHY_BISTEN_S  24
-
-/** HP_SYSTEM_TCM_ERR_RESP_CTRL_REG register
- *  need_des
- */
-#define HP_SYSTEM_TCM_ERR_RESP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x160)
-/** HP_SYSTEM_TCM_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to turn on tcm error response
- */
-#define HP_SYSTEM_TCM_ERR_RESP_EN    (BIT(0))
-#define HP_SYSTEM_TCM_ERR_RESP_EN_M  (HP_SYSTEM_TCM_ERR_RESP_EN_V << HP_SYSTEM_TCM_ERR_RESP_EN_S)
-#define HP_SYSTEM_TCM_ERR_RESP_EN_V  0x00000001U
-#define HP_SYSTEM_TCM_ERR_RESP_EN_S  0
-
-/** HP_SYSTEM_L2_MEM_REFRESH_REG register
- *  NA
- */
-#define HP_SYSTEM_L2_MEM_REFRESH_REG (DR_REG_HP_SYS_BASE + 0x164)
-/** HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN    (BIT(0))
-#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_S  0
-/** HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN : R/W; bitpos: [1]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN    (BIT(1))
-#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_S  1
-/** HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN : R/W; bitpos: [2]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN    (BIT(2))
-#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_S  2
-/** HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN : R/W; bitpos: [3]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN    (BIT(3))
-#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_S  3
-/** HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN : R/W; bitpos: [4]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN    (BIT(4))
-#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_S  4
-/** HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN : R/W; bitpos: [5]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN    (BIT(5))
-#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_S  5
-/** HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET : R/W; bitpos: [6]; default: 1;
- *  Set 1 to reset l2mem_refresh_cnt
- */
-#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET    (BIT(6))
-#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_M  (HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_V << HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_S)
-#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_S  6
-/** HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE : RO; bitpos: [7]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE    (BIT(7))
-#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_S  7
-/** HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE : RO; bitpos: [8]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE    (BIT(8))
-#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_S  8
-/** HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE : RO; bitpos: [9]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE    (BIT(9))
-#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_S  9
-/** HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE : RO; bitpos: [10]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE    (BIT(10))
-#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_S  10
-/** HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE : RO; bitpos: [11]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE    (BIT(11))
-#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_S  11
-/** HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE : RO; bitpos: [12]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE    (BIT(12))
-#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_S)
-#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_V  0x00000001U
-#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_S  12
-
-/** HP_SYSTEM_TCM_INIT_REG register
- *  NA
- */
-#define HP_SYSTEM_TCM_INIT_REG (DR_REG_HP_SYS_BASE + 0x168)
-/** HP_SYSTEM_REG_TCM_INIT_EN : R/W; bitpos: [0]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_TCM_INIT_EN    (BIT(0))
-#define HP_SYSTEM_REG_TCM_INIT_EN_M  (HP_SYSTEM_REG_TCM_INIT_EN_V << HP_SYSTEM_REG_TCM_INIT_EN_S)
-#define HP_SYSTEM_REG_TCM_INIT_EN_V  0x00000001U
-#define HP_SYSTEM_REG_TCM_INIT_EN_S  0
-/** HP_SYSTEM_REG_TCM_INIT_CNT_RESET : R/W; bitpos: [1]; default: 1;
- *  Set 1 to reset tcm init cnt
- */
-#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET    (BIT(1))
-#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_M  (HP_SYSTEM_REG_TCM_INIT_CNT_RESET_V << HP_SYSTEM_REG_TCM_INIT_CNT_RESET_S)
-#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_V  0x00000001U
-#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_S  1
-/** HP_SYSTEM_REG_TCM_INIT_DONE : RO; bitpos: [2]; default: 0;
- *  NA
- */
-#define HP_SYSTEM_REG_TCM_INIT_DONE    (BIT(2))
-#define HP_SYSTEM_REG_TCM_INIT_DONE_M  (HP_SYSTEM_REG_TCM_INIT_DONE_V << HP_SYSTEM_REG_TCM_INIT_DONE_S)
-#define HP_SYSTEM_REG_TCM_INIT_DONE_V  0x00000001U
-#define HP_SYSTEM_REG_TCM_INIT_DONE_S  2
-
-/** HP_SYSTEM_TCM_PARITY_CHECK_CTRL_REG register
- *  need_des
- */
-#define HP_SYSTEM_TCM_PARITY_CHECK_CTRL_REG (DR_REG_HP_SYS_BASE + 0x16c)
-/** HP_SYSTEM_TCM_PARITY_CHECK_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to turn on tcm parity check
- */
-#define HP_SYSTEM_TCM_PARITY_CHECK_EN    (BIT(0))
-#define HP_SYSTEM_TCM_PARITY_CHECK_EN_M  (HP_SYSTEM_TCM_PARITY_CHECK_EN_V << HP_SYSTEM_TCM_PARITY_CHECK_EN_S)
-#define HP_SYSTEM_TCM_PARITY_CHECK_EN_V  0x00000001U
-#define HP_SYSTEM_TCM_PARITY_CHECK_EN_S  0
-
-/** HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG register
- *  need_des
- */
-#define HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG (DR_REG_HP_SYS_BASE + 0x170)
-/** HP_SYSTEM_DFV0 : R/W; bitpos: [31:0]; default: 0;
- *  register for DV
- */
-#define HP_SYSTEM_DFV0    0xFFFFFFFFU
-#define HP_SYSTEM_DFV0_M  (HP_SYSTEM_DFV0_V << HP_SYSTEM_DFV0_S)
-#define HP_SYSTEM_DFV0_V  0xFFFFFFFFU
-#define HP_SYSTEM_DFV0_S  0
-
-/** HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG register
- *  need_des
- */
-#define HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG (DR_REG_HP_SYS_BASE + 0x174)
-/** HP_SYSTEM_DFV1 : R/W; bitpos: [31:0]; default: 0;
- *  register for DV
- */
-#define HP_SYSTEM_DFV1    0xFFFFFFFFU
-#define HP_SYSTEM_DFV1_M  (HP_SYSTEM_DFV1_V << HP_SYSTEM_DFV1_S)
-#define HP_SYSTEM_DFV1_V  0xFFFFFFFFU
-#define HP_SYSTEM_DFV1_S  0
-
-/** HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_REG register
- *  need_des
- */
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_REG (DR_REG_HP_SYS_BASE + 0x180)
-/** HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU : R/W; bitpos: [0]; default: 0;
- *  Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu
- *  access through cache
- */
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU    (BIT(0))
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_M  (HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_V << HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_S)
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_V  0x00000001U
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_S  0
-/** HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA : R/W; bitpos: [1]; default: 0;
- *  Set 1 to enable addr interchange between psram and flash in axi matrix when dma
- *  device access, lp core access and hp core access through ahb
- */
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA    (BIT(1))
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_M  (HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_V << HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_S)
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_V  0x00000001U
-#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_S  1
-
-/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG register
- *  NA
- */
-#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x188)
-/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
- *  post write mode in ahb2axi.
- */
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW    (BIT(0))
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S)
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S  0
-
-/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG register
- *  need_des
- */
-#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x18c)
-/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST : RO; bitpos: [31]; default: 0;
- *  the masked interrupt status of  cpu_icm_h2x_bresp_err
- */
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST    (BIT(31))
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S)
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V  0x00000001U
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S  31
-
-/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG register
- *  need_des
- */
-#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x190)
-/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
- *  Write 1 to enable cpu_icm_h2x_bresp_err int
- */
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA    (BIT(31))
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S)
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S  31
-
-/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG register
- *  need_des
- */
-#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x194)
-/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
- *  Write 1 to clear cpu_icm_h2x_bresp_err  int
- */
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR    (BIT(31))
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S)
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S  31
-
-/** HP_SYSTEM_L2_MEM_ERR_RESP_CTRL_REG register
- *  need_des
- */
-#define HP_SYSTEM_L2_MEM_ERR_RESP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x198)
-/** HP_SYSTEM_L2_MEM_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to turn on l2mem error response
- */
-#define HP_SYSTEM_L2_MEM_ERR_RESP_EN    (BIT(0))
-#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_M  (HP_SYSTEM_L2_MEM_ERR_RESP_EN_V << HP_SYSTEM_L2_MEM_ERR_RESP_EN_S)
-#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_V  0x00000001U
-#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_S  0
-
-/** HP_SYSTEM_L2_MEM_AHB_BUFFER_CTRL_REG register
- *  need_des
- */
-#define HP_SYSTEM_L2_MEM_AHB_BUFFER_CTRL_REG (DR_REG_HP_SYS_BASE + 0x19c)
-/** HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN : R/W; bitpos: [0]; default: 0;
- *  Set 1 to turn on l2mem ahb wr buffer
- */
-#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN    (BIT(0))
-#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_M  (HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_V << HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_S)
-#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_V  0x00000001U
-#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_S  0
-/** HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN : R/W; bitpos: [1]; default: 0;
- *  Set 1 to turn on l2mem ahb rd buffer
- */
-#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN    (BIT(1))
-#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_M  (HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_V << HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_S)
-#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_V  0x00000001U
-#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_S  1
-
-/** HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG register
- *  need_des
- */
-#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG (DR_REG_HP_SYS_BASE + 0x1a0)
-/** HP_SYSTEM_CORE_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
- *  hp core dmactive_lpcore value
- */
-#define HP_SYSTEM_CORE_DMACTIVE_LPCORE    (BIT(0))
-#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_M  (HP_SYSTEM_CORE_DMACTIVE_LPCORE_V << HP_SYSTEM_CORE_DMACTIVE_LPCORE_S)
-#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_V  0x00000001U
-#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_S  0
-
-/** HP_SYSTEM_CORE_ERR_RESP_DIS_REG register
- *  need_des
- */
-#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG (DR_REG_HP_SYS_BASE + 0x1a4)
-/** HP_SYSTEM_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
- *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
- *  disable ahb err resp.
- */
-#define HP_SYSTEM_CORE_ERR_RESP_DIS    0x00000007U
-#define HP_SYSTEM_CORE_ERR_RESP_DIS_M  (HP_SYSTEM_CORE_ERR_RESP_DIS_V << HP_SYSTEM_CORE_ERR_RESP_DIS_S)
-#define HP_SYSTEM_CORE_ERR_RESP_DIS_V  0x00000007U
-#define HP_SYSTEM_CORE_ERR_RESP_DIS_S  0
-
-/** HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG register
- *  Hp core bus timeout interrupt raw register
- */
-#define HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x1a8)
-/** HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  the raw interrupt status of hp core0  ahb timeout
- */
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW    (BIT(0))
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_S)
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_S  0
-/** HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  the raw interrupt status of hp core1  ahb timeout
- */
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW    (BIT(1))
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_S)
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_S  1
-/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  the raw interrupt status of hp core0  ibus timeout
- */
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW    (BIT(2))
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S)
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S  2
-/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  the raw interrupt status of hp core1  ibus timeout
- */
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW    (BIT(3))
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S)
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S  3
-/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  the raw interrupt status of hp core0  dbus timeout
- */
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW    (BIT(4))
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S)
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S  4
-/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  the raw interrupt status of hp core1  dbus timeout
- */
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW    (BIT(5))
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S)
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S  5
-
-/** HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG register
- *  masked interrupt register
- */
-#define HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x1ac)
-/** HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST : RO; bitpos: [0]; default: 0;
- *  the masked interrupt status of hp core0  ahb timeout
- */
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST    (BIT(0))
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_S)
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_V  0x00000001U
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_S  0
-/** HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST : RO; bitpos: [1]; default: 0;
- *  the masked interrupt status of hp core1  ahb timeout
- */
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST    (BIT(1))
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_S)
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_V  0x00000001U
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_S  1
-/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
- *  the masked interrupt status of hp core0  ibus timeout
- */
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST    (BIT(2))
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S)
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V  0x00000001U
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S  2
-/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
- *  the masked interrupt status of hp core1  ibus timeout
- */
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST    (BIT(3))
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S)
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V  0x00000001U
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S  3
-/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
- *  the masked interrupt status of hp core0  dbus timeout
- */
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST    (BIT(4))
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S)
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V  0x00000001U
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S  4
-/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST : RO; bitpos: [5]; default: 0;
- *  the masked interrupt status of hp core1  dbus timeout
- */
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST    (BIT(5))
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S)
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V  0x00000001U
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S  5
-
-/** HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG register
- *  masked interrupt register
- */
-#define HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x1b0)
-/** HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Write 1 to enable HP_SYSTEM_core0_ahb_timeout int
- */
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA    (BIT(0))
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_S)
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_S  0
-/** HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Write 1 to enable HP_SYSTEM_core1_ahb_timeout int
- */
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA    (BIT(1))
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_S)
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_S  1
-/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Write 1 to enable HP_SYSTEM_core0_ibus_timeout int
- */
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA    (BIT(2))
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S)
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S  2
-/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Write 1 to enable HP_SYSTEM_core1_ibus_timeout int
- */
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA    (BIT(3))
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S)
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S  3
-/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Write 1 to enable HP_SYSTEM_core0_dbus_timeout int
- */
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA    (BIT(4))
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S)
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S  4
-/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Write 1 to enable HP_SYSTEM_core1_dbus_timeout int
- */
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA    (BIT(5))
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S)
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S  5
-
-/** HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG register
- *  interrupt clear register
- */
-#define HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x1b4)
-/** HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Write 1 to clear HP_SYSTEM_core0_ahb_timeout int
- */
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR    (BIT(0))
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_S)
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_S  0
-/** HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Write 1 to clear HP_SYSTEM_core1_ahb_timeout int
- */
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR    (BIT(1))
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_S)
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_S  1
-/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Write 1 to clear HP_SYSTEM_core0_ibus_timeout int
- */
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR    (BIT(2))
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S)
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S  2
-/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Write 1 to clear HP_SYSTEM_core1_ibus_timeout int
- */
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR    (BIT(3))
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S)
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S  3
-/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Write 1 to clear HP_SYSTEM_core0_dbus_timeout int
- */
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR    (BIT(4))
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S)
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S  4
-/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Write 1 to clear HP_SYSTEM_core1_dbus_timeout int
- */
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR    (BIT(5))
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S)
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
-#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S  5
-
-/** HP_SYSTEM_GPIO_O_HYS_CTRL0_REG register
- *  NA
- */
-#define HP_SYSTEM_GPIO_O_HYS_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x1c0)
-/** HP_SYSTEM_REG_GPIO_0_HYS_LOW : R/W; bitpos: [31:0]; default: 0;
- *  hys control for gpio47~16
- */
-#define HP_SYSTEM_REG_GPIO_0_HYS_LOW    0xFFFFFFFFU
-#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_M  (HP_SYSTEM_REG_GPIO_0_HYS_LOW_V << HP_SYSTEM_REG_GPIO_0_HYS_LOW_S)
-#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_V  0xFFFFFFFFU
-#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_S  0
-
-/** HP_SYSTEM_GPIO_O_HYS_CTRL1_REG register
- *  NA
- */
-#define HP_SYSTEM_GPIO_O_HYS_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x1c4)
-/** HP_SYSTEM_REG_GPIO_0_HYS_HIGH : R/W; bitpos: [8:0]; default: 0;
- *  hys control for gpio56~48
- */
-#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH    0x000001FFU
-#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_M  (HP_SYSTEM_REG_GPIO_0_HYS_HIGH_V << HP_SYSTEM_REG_GPIO_0_HYS_HIGH_S)
-#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_V  0x000001FFU
-#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_S  0
-
-/** HP_SYSTEM_RSA_PD_CTRL_REG register
- *  rsa pd ctrl register
- */
-#define HP_SYSTEM_RSA_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1d0)
-/** HP_SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down rsa internal memory.
- */
-#define HP_SYSTEM_RSA_MEM_FORCE_PD    (BIT(0))
-#define HP_SYSTEM_RSA_MEM_FORCE_PD_M  (HP_SYSTEM_RSA_MEM_FORCE_PD_V << HP_SYSTEM_RSA_MEM_FORCE_PD_S)
-#define HP_SYSTEM_RSA_MEM_FORCE_PD_V  0x00000001U
-#define HP_SYSTEM_RSA_MEM_FORCE_PD_S  0
-/** HP_SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up rsa internal memory
- */
-#define HP_SYSTEM_RSA_MEM_FORCE_PU    (BIT(1))
-#define HP_SYSTEM_RSA_MEM_FORCE_PU_M  (HP_SYSTEM_RSA_MEM_FORCE_PU_V << HP_SYSTEM_RSA_MEM_FORCE_PU_S)
-#define HP_SYSTEM_RSA_MEM_FORCE_PU_V  0x00000001U
-#define HP_SYSTEM_RSA_MEM_FORCE_PU_S  1
-/** HP_SYSTEM_RSA_MEM_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down rsa internal memory.
- */
-#define HP_SYSTEM_RSA_MEM_PD    (BIT(2))
-#define HP_SYSTEM_RSA_MEM_PD_M  (HP_SYSTEM_RSA_MEM_PD_V << HP_SYSTEM_RSA_MEM_PD_S)
-#define HP_SYSTEM_RSA_MEM_PD_V  0x00000001U
-#define HP_SYSTEM_RSA_MEM_PD_S  2
-
-/** HP_SYSTEM_ECC_PD_CTRL_REG register
- *  ecc pd ctrl register
- */
-#define HP_SYSTEM_ECC_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1d4)
-/** HP_SYSTEM_ECC_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down ecc internal memory.
- */
-#define HP_SYSTEM_ECC_MEM_FORCE_PD    (BIT(0))
-#define HP_SYSTEM_ECC_MEM_FORCE_PD_M  (HP_SYSTEM_ECC_MEM_FORCE_PD_V << HP_SYSTEM_ECC_MEM_FORCE_PD_S)
-#define HP_SYSTEM_ECC_MEM_FORCE_PD_V  0x00000001U
-#define HP_SYSTEM_ECC_MEM_FORCE_PD_S  0
-/** HP_SYSTEM_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up ecc internal memory
- */
-#define HP_SYSTEM_ECC_MEM_FORCE_PU    (BIT(1))
-#define HP_SYSTEM_ECC_MEM_FORCE_PU_M  (HP_SYSTEM_ECC_MEM_FORCE_PU_V << HP_SYSTEM_ECC_MEM_FORCE_PU_S)
-#define HP_SYSTEM_ECC_MEM_FORCE_PU_V  0x00000001U
-#define HP_SYSTEM_ECC_MEM_FORCE_PU_S  1
-/** HP_SYSTEM_ECC_MEM_PD : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force power down ecc internal memory.
- */
-#define HP_SYSTEM_ECC_MEM_PD    (BIT(2))
-#define HP_SYSTEM_ECC_MEM_PD_M  (HP_SYSTEM_ECC_MEM_PD_V << HP_SYSTEM_ECC_MEM_PD_S)
-#define HP_SYSTEM_ECC_MEM_PD_V  0x00000001U
-#define HP_SYSTEM_ECC_MEM_PD_S  2
-
-/** HP_SYSTEM_RNG_CFG_REG register
- *  rng cfg register
- */
-#define HP_SYSTEM_RNG_CFG_REG (DR_REG_HP_SYS_BASE + 0x1d8)
-/** HP_SYSTEM_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
- *  enable rng sample chain
- */
-#define HP_SYSTEM_RNG_SAMPLE_ENABLE    (BIT(0))
-#define HP_SYSTEM_RNG_SAMPLE_ENABLE_M  (HP_SYSTEM_RNG_SAMPLE_ENABLE_V << HP_SYSTEM_RNG_SAMPLE_ENABLE_S)
-#define HP_SYSTEM_RNG_SAMPLE_ENABLE_V  0x00000001U
-#define HP_SYSTEM_RNG_SAMPLE_ENABLE_S  0
-/** HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
- *  chain clk div num to pad for debug
- */
-#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM    0x000000FFU
-#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_M  (HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V << HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S)
-#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V  0x000000FFU
-#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S  16
-/** HP_SYSTEM_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
- *  debug rng sample cnt
- */
-#define HP_SYSTEM_RNG_SAMPLE_CNT    0x000000FFU
-#define HP_SYSTEM_RNG_SAMPLE_CNT_M  (HP_SYSTEM_RNG_SAMPLE_CNT_V << HP_SYSTEM_RNG_SAMPLE_CNT_S)
-#define HP_SYSTEM_RNG_SAMPLE_CNT_V  0x000000FFU
-#define HP_SYSTEM_RNG_SAMPLE_CNT_S  24
-
-/** HP_SYSTEM_UART_PD_CTRL_REG register
- *  ecc pd ctrl register
- */
-#define HP_SYSTEM_UART_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1dc)
-/** HP_SYSTEM_UART_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to power down hp uart internal memory.
- */
-#define HP_SYSTEM_UART_MEM_FORCE_PD    (BIT(0))
-#define HP_SYSTEM_UART_MEM_FORCE_PD_M  (HP_SYSTEM_UART_MEM_FORCE_PD_V << HP_SYSTEM_UART_MEM_FORCE_PD_S)
-#define HP_SYSTEM_UART_MEM_FORCE_PD_V  0x00000001U
-#define HP_SYSTEM_UART_MEM_FORCE_PD_S  0
-/** HP_SYSTEM_UART_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
- *  Set this bit to force power up hp uart  internal memory
- */
-#define HP_SYSTEM_UART_MEM_FORCE_PU    (BIT(1))
-#define HP_SYSTEM_UART_MEM_FORCE_PU_M  (HP_SYSTEM_UART_MEM_FORCE_PU_V << HP_SYSTEM_UART_MEM_FORCE_PU_S)
-#define HP_SYSTEM_UART_MEM_FORCE_PU_V  0x00000001U
-#define HP_SYSTEM_UART_MEM_FORCE_PU_S  1
-
-/** HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG register
- *  hp peri mem clk force on regpster
- */
-#define HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG (DR_REG_HP_SYS_BASE + 0x1e0)
-/** HP_SYSTEM_RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force on mem clk in rmt
- */
-#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON    (BIT(0))
-#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V << HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S  0
-/** HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
- *  Set this bit to force on tx mem clk in bitscrambler
- */
-#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON    (BIT(1))
-#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V << HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S  1
-/** HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force on rx mem clk in bitscrambler
- */
-#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON    (BIT(2))
-#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V << HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S  2
-/** HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON : R/W; bitpos: [3]; default: 0;
- *  Set this bit to force on mem clk in gdma
- */
-#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON    (BIT(3))
-#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V << HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S)
-#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V  0x00000001U
-#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S  3
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/hp_system_struct.h b/components/soc/esp32p4/include/soc/hp_system_struct.h
deleted file mode 100644
index 628ef31ef4f..00000000000
--- a/components/soc/esp32p4/include/soc/hp_system_struct.h
+++ /dev/null
@@ -1,2034 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: HP SYS VER DATE REG */
-/** Type of sys_ver_date register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_ver_date : R/W; bitpos: [31:0]; default: 539165977;
-         *  NA
-         */
-        uint32_t reg_ver_date:32;
-    };
-    uint32_t val;
-} hp_system_ver_date_reg_t;
-
-
-/** Group: HP CLK EN REG */
-/** Type of clk_en register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_clk_en_reg_t;
-
-
-/** Group: HP CPU INT FROM CPU 0 REG */
-/** Type of cpu_int_from_cpu_0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** cpu_int_from_cpu_0 : R/W; bitpos: [0]; default: 0;
-         *  set 1 will triger a interrupt
-         */
-        uint32_t cpu_int_from_cpu_0:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_cpu_int_from_cpu_0_reg_t;
-
-
-/** Group: HP CPU INT FROM CPU 1 REG */
-/** Type of cpu_int_from_cpu_1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** cpu_int_from_cpu_1 : R/W; bitpos: [0]; default: 0;
-         *  set 1 will triger a interrupt
-         */
-        uint32_t cpu_int_from_cpu_1:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_cpu_int_from_cpu_1_reg_t;
-
-
-/** Group: HP CPU INT FROM CPU 2 REG */
-/** Type of cpu_int_from_cpu_2 register
- *  NA
- */
-typedef union {
-    struct {
-        /** cpu_int_from_cpu_2 : R/W; bitpos: [0]; default: 0;
-         *  set 1 will triger a interrupt
-         */
-        uint32_t cpu_int_from_cpu_2:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_cpu_int_from_cpu_2_reg_t;
-
-
-/** Group: HP CPU INT FROM CPU 3 REG */
-/** Type of cpu_int_from_cpu_3 register
- *  NA
- */
-typedef union {
-    struct {
-        /** cpu_int_from_cpu_3 : R/W; bitpos: [0]; default: 0;
-         *  set 1 will triger a interrupt
-         */
-        uint32_t cpu_int_from_cpu_3:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_cpu_int_from_cpu_3_reg_t;
-
-
-/** Group: HP CACHE CLK CONFIG REG */
-/** Type of cache_clk_config register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_cache_clk_on : R/W; bitpos: [0]; default: 1;
-         *  l2 cahce clk enable
-         */
-        uint32_t reg_l2_cache_clk_on:1;
-        /** reg_l1_d_cache_clk_on : R/W; bitpos: [1]; default: 1;
-         *  l1 dcahce clk enable
-         */
-        uint32_t reg_l1_d_cache_clk_on:1;
-        uint32_t reserved_2:2;
-        /** reg_l1_i1_cache_clk_on : R/W; bitpos: [4]; default: 1;
-         *  l1 icahce1 clk enable
-         */
-        uint32_t reg_l1_i1_cache_clk_on:1;
-        /** reg_l1_i0_cache_clk_on : R/W; bitpos: [5]; default: 1;
-         *  l1 icahce0 clk enable
-         */
-        uint32_t reg_l1_i0_cache_clk_on:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_system_cache_clk_config_reg_t;
-
-
-/** Group: HP CACHE RESET CONFIG REG */
-/** Type of cache_reset_config register
- *  NA
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** reg_l1_d_cache_reset : R/W; bitpos: [1]; default: 0;
-         *  set 1 to reset l1 dcahce
-         */
-        uint32_t reg_l1_d_cache_reset:1;
-        uint32_t reserved_2:2;
-        /** reg_l1_i1_cache_reset : R/W; bitpos: [4]; default: 0;
-         *  set 1 to reset l1 icahce1
-         */
-        uint32_t reg_l1_i1_cache_reset:1;
-        /** reg_l1_i0_cache_reset : R/W; bitpos: [5]; default: 0;
-         *  set 1 to reset l1 icahce0
-         */
-        uint32_t reg_l1_i0_cache_reset:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_system_cache_reset_config_reg_t;
-
-
-/** Group: HP SYS DMA ADDR CTRL REG */
-/** Type of sys_dma_addr_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_sys_dma_addr_sel : R/W; bitpos: [0]; default: 0;
-         *  0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx
-         */
-        uint32_t reg_sys_dma_addr_sel:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_dma_addr_ctrl_reg_t;
-
-
-/** Group: HP TCM RAM WRR CONFIG REG */
-/** Type of tcm_ram_wrr_config register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_tcm_ram_ibus0_wt : R/W; bitpos: [2:0]; default: 7;
-         *  weight value of ibus0
-         */
-        uint32_t reg_tcm_ram_ibus0_wt:3;
-        /** reg_tcm_ram_ibus1_wt : R/W; bitpos: [5:3]; default: 7;
-         *  weight value of ibus1
-         */
-        uint32_t reg_tcm_ram_ibus1_wt:3;
-        /** reg_tcm_ram_ibus2_wt : R/W; bitpos: [8:6]; default: 4;
-         *  weight value of ibus2
-         */
-        uint32_t reg_tcm_ram_ibus2_wt:3;
-        /** reg_tcm_ram_ibus3_wt : R/W; bitpos: [11:9]; default: 4;
-         *  weight value of ibus3
-         */
-        uint32_t reg_tcm_ram_ibus3_wt:3;
-        /** reg_tcm_ram_dbus0_wt : R/W; bitpos: [14:12]; default: 5;
-         *  weight value of dbus0
-         */
-        uint32_t reg_tcm_ram_dbus0_wt:3;
-        /** reg_tcm_ram_dbus1_wt : R/W; bitpos: [17:15]; default: 5;
-         *  weight value of dbus1
-         */
-        uint32_t reg_tcm_ram_dbus1_wt:3;
-        /** reg_tcm_ram_dbus2_wt : R/W; bitpos: [20:18]; default: 3;
-         *  weight value of dbus2
-         */
-        uint32_t reg_tcm_ram_dbus2_wt:3;
-        /** reg_tcm_ram_dbus3_wt : R/W; bitpos: [23:21]; default: 3;
-         *  weight value of dbus3
-         */
-        uint32_t reg_tcm_ram_dbus3_wt:3;
-        /** reg_tcm_ram_dma_wt : R/W; bitpos: [26:24]; default: 2;
-         *  weight value of dma
-         */
-        uint32_t reg_tcm_ram_dma_wt:3;
-        uint32_t reserved_27:4;
-        /** reg_tcm_ram_wrr_high : R/W; bitpos: [31]; default: 1;
-         *  enable weighted round robin arbitration
-         */
-        uint32_t reg_tcm_ram_wrr_high:1;
-    };
-    uint32_t val;
-} hp_system_tcm_ram_wrr_config_reg_t;
-
-
-/** Group: HP TCM SW PARITY BWE MASK REG */
-/** Type of tcm_sw_parity_bwe_mask register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_tcm_sw_parity_bwe_mask_ctrl : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to mask tcm bwe parity code bit
-         */
-        uint32_t reg_tcm_sw_parity_bwe_mask_ctrl:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_tcm_sw_parity_bwe_mask_reg_t;
-
-
-/** Group: HP TCM RAM PWR CTRL0 REG */
-/** Type of tcm_ram_pwr_ctrl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_hp_system_tcm_clk_force_on : R/W; bitpos: [0]; default: 0;
-         *  hp_system_tcm clk gatig force on
-         */
-        uint32_t reg_hp_system_tcm_clk_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_tcm_ram_pwr_ctrl0_reg_t;
-
-
-/** Group: HP L2 ROM PWR CTRL0 REG */
-/** Type of l2_rom_pwr_ctrl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_rom_clk_force_on : R/W; bitpos: [0]; default: 0;
-         *  l2_rom clk gating force on
-         */
-        uint32_t reg_l2_rom_clk_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_l2_rom_pwr_ctrl0_reg_t;
-
-
-/** Group: HP PROBEA CTRL REG */
-/** Type of probea_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
-         *  Tihs field is used to selec probe_group from probe_group0 to probe_group15 for
-         *  module's probe_out[31:0] in a mode
-         */
-        uint32_t reg_probe_a_mod_sel:16;
-        /** reg_probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
-         *  Tihs field is used to selec module's probe_out[31:0] as probe out in a mode
-         */
-        uint32_t reg_probe_a_top_sel:8;
-        /** reg_probe_l_sel : R/W; bitpos: [25:24]; default: 0;
-         *  Tihs field is used to selec probe_out[31:16]
-         */
-        uint32_t reg_probe_l_sel:2;
-        /** reg_probe_h_sel : R/W; bitpos: [27:26]; default: 0;
-         *  Tihs field is used to selec probe_out[31:16]
-         */
-        uint32_t reg_probe_h_sel:2;
-        /** reg_probe_global_en : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to enable global debug probe in hp system.
-         */
-        uint32_t reg_probe_global_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} hp_system_probea_ctrl_reg_t;
-
-
-/** Group: HP PROBEB CTRL REG */
-/** Type of probeb_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
-         *  Tihs field is used to selec probe_group from probe_group0 to probe_group15 for
-         *  module's probe_out[31:0] in b mode.
-         */
-        uint32_t reg_probe_b_mod_sel:16;
-        /** reg_probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
-         *  Tihs field is used to select module's probe_out[31:0]  as probe_out in b mode
-         */
-        uint32_t reg_probe_b_top_sel:8;
-        /** reg_probe_b_en : R/W; bitpos: [24]; default: 0;
-         *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
-         */
-        uint32_t reg_probe_b_en:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} hp_system_probeb_ctrl_reg_t;
-
-
-/** Group: HP PROBE OUT REG */
-/** Type of probe_out register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_probe_top_out : RO; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_probe_top_out:32;
-    };
-    uint32_t val;
-} hp_system_probe_out_reg_t;
-
-
-/** Group: HP L2 MEM RAM PWR CTRL0 REG */
-/** Type of l2_mem_ram_pwr_ctrl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
-         *  l2ram clk_gating force on
-         */
-        uint32_t reg_l2_mem_clk_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_l2_mem_ram_pwr_ctrl0_reg_t;
-
-
-/** Group: HP CPU CORESTALLED ST REG */
-/** Type of cpu_corestalled_st register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_core0_corestalled_st : RO; bitpos: [0]; default: 0;
-         *  hp core0 corestalled status
-         */
-        uint32_t reg_core0_corestalled_st:1;
-        /** reg_core1_corestalled_st : RO; bitpos: [1]; default: 0;
-         *  hp core1 corestalled status
-         */
-        uint32_t reg_core1_corestalled_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_cpu_corestalled_st_reg_t;
-
-
-/** Group: HP CRYPTO CTRL REG */
-/** Type of crypto_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_enable_spi_manual_encrypt:1;
-        /** reg_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_enable_download_db_encrypt:1;
-        /** reg_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t reg_enable_download_g0cb_decrypt:1;
-        /** reg_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t reg_enable_download_manual_encrypt:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_system_crypto_ctrl_reg_t;
-
-
-/** Group: HP GPIO O HOLD CTRL0 REG */
-/** Type of gpio_o_hold_ctrl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0;
-         *  hold control for gpio47~16
-         */
-        uint32_t reg_gpio_0_hold_low:32;
-    };
-    uint32_t val;
-} hp_system_gpio_o_hold_ctrl0_reg_t;
-
-
-/** Group: HP GPIO O HOLD CTRL1 REG */
-/** Type of gpio_o_hold_ctrl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0;
-         *  hold control for gpio56~48
-         */
-        uint32_t reg_gpio_0_hold_high:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} hp_system_gpio_o_hold_ctrl1_reg_t;
-
-
-/** Group: HP SYS RDN ECO CS REG */
-/** Type of sys_rdn_eco_cs register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_hp_system_rdn_eco_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_hp_system_rdn_eco_en:1;
-        /** reg_hp_system_rdn_eco_result : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_hp_system_rdn_eco_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_rdn_eco_cs_reg_t;
-
-
-/** Group: HP CACHE APB POSTW EN REG */
-/** Type of cache_apb_postw_en register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_cache_apb_postw_en : R/W; bitpos: [0]; default: 0;
-         *  cache apb register interface post write enable, 1 will speed up write, but will
-         *  take some time to update value to register
-         */
-        uint32_t reg_cache_apb_postw_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_cache_apb_postw_en_reg_t;
-
-
-/** Group: HP L2 MEM SUBSIZE REG */
-/** Type of l2_mem_subsize register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_sub_blksize : R/W; bitpos: [1:0]; default: 0;
-         *  l2mem sub block size 00=>32 01=>64 10=>128 11=>256
-         */
-        uint32_t reg_l2_mem_sub_blksize:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_l2_mem_subsize_reg_t;
-
-
-/** Group: HP L2 MEM INT RAW REG */
-/** Type of l2_mem_int_raw register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_ecc_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  intr triggered when two bit error detected and corrected from ecc
-         */
-        uint32_t reg_l2_mem_ecc_err_int_raw:1;
-        /** reg_l2_mem_exceed_addr_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds
-         *  0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode
-         */
-        uint32_t reg_l2_mem_exceed_addr_int_raw:1;
-        /** reg_l2_mem_err_resp_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  intr triggered when err response occurs
-         */
-        uint32_t reg_l2_mem_err_resp_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_l2_mem_int_raw_reg_t;
-
-
-/** Group: HP L2 MEM INT ST REG */
-/** Type of l2_mem_int_st register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_ecc_err_int_st : RO; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_ecc_err_int_st:1;
-        /** reg_l2_mem_exceed_addr_int_st : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_exceed_addr_int_st:1;
-        /** reg_l2_mem_err_resp_int_st : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_err_resp_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_l2_mem_int_st_reg_t;
-
-
-/** Group: HP L2 MEM INT ENA REG */
-/** Type of l2_mem_int_ena register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_ecc_err_int_ena : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_ecc_err_int_ena:1;
-        /** reg_l2_mem_exceed_addr_int_ena : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_exceed_addr_int_ena:1;
-        /** reg_l2_mem_err_resp_int_ena : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_err_resp_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_l2_mem_int_ena_reg_t;
-
-
-/** Group: HP L2 MEM INT CLR REG */
-/** Type of l2_mem_int_clr register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_ecc_err_int_clr : WT; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_ecc_err_int_clr:1;
-        /** reg_l2_mem_exceed_addr_int_clr : WT; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_exceed_addr_int_clr:1;
-        /** reg_l2_mem_err_resp_int_clr : WT; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_err_resp_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_l2_mem_int_clr_reg_t;
-
-
-/** Group: HP L2 MEM L2 RAM ECC REG */
-/** Type of l2_mem_l2_ram_ecc register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_ram_unit0_ecc_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_ram_unit0_ecc_en:1;
-        /** reg_l2_ram_unit1_ecc_en : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_ram_unit1_ecc_en:1;
-        /** reg_l2_ram_unit2_ecc_en : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_ram_unit2_ecc_en:1;
-        /** reg_l2_ram_unit3_ecc_en : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_ram_unit3_ecc_en:1;
-        /** reg_l2_ram_unit4_ecc_en : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_ram_unit4_ecc_en:1;
-        /** reg_l2_ram_unit5_ecc_en : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_ram_unit5_ecc_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_system_l2_mem_l2_ram_ecc_reg_t;
-
-
-/** Group: HP L2 MEM INT RECORD0 REG */
-/** Type of l2_mem_int_record0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_exceed_addr_int_addr : RO; bitpos: [20:0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_exceed_addr_int_addr:21;
-        /** reg_l2_mem_exceed_addr_int_we : RO; bitpos: [21]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_exceed_addr_int_we:1;
-        /** reg_l2_mem_exceed_addr_int_master : RO; bitpos: [24:22]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_exceed_addr_int_master:3;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} hp_system_l2_mem_int_record0_reg_t;
-
-
-/** Group: HP L2 MEM INT RECORD1 REG */
-/** Type of l2_mem_int_record1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_ecc_err_int_addr : RO; bitpos: [14:0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_ecc_err_int_addr:15;
-        /** reg_l2_mem_ecc_one_bit_err : RO; bitpos: [15]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_ecc_one_bit_err:1;
-        /** reg_l2_mem_ecc_two_bit_err : RO; bitpos: [16]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_ecc_two_bit_err:1;
-        /** reg_l2_mem_ecc_err_bit : RO; bitpos: [25:17]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_ecc_err_bit:9;
-        /** reg_l2_cache_err_bank : RO; bitpos: [26]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_cache_err_bank:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} hp_system_l2_mem_int_record1_reg_t;
-
-
-/** Group: HP L2 MEM L2 CACHE ECC REG */
-/** Type of l2_mem_l2_cache_ecc register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_cache_ecc_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_cache_ecc_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_l2_mem_l2_cache_ecc_reg_t;
-
-
-/** Group: HP L1CACHE BUS0 ID REG */
-/** Type of l1cache_bus0_id register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l1_cache_bus0_id : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l1_cache_bus0_id:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_system_l1cache_bus0_id_reg_t;
-
-
-/** Group: HP L1CACHE BUS1 ID REG */
-/** Type of l1cache_bus1_id register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l1_cache_bus1_id : R/W; bitpos: [3:0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l1_cache_bus1_id:4;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_system_l1cache_bus1_id_reg_t;
-
-
-/** Group: HP L2 MEM RDN ECO CS REG */
-/** Type of l2_mem_rdn_eco_cs register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_rdn_eco_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_rdn_eco_en:1;
-        /** reg_l2_mem_rdn_eco_result : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_rdn_eco_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_l2_mem_rdn_eco_cs_reg_t;
-
-
-/** Group: HP L2 MEM RDN ECO LOW REG */
-/** Type of l2_mem_rdn_eco_low register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_rdn_eco_low:32;
-    };
-    uint32_t val;
-} hp_system_l2_mem_rdn_eco_low_reg_t;
-
-
-/** Group: HP L2 MEM RDN ECO HIGH REG */
-/** Type of l2_mem_rdn_eco_high register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
-         *  NA
-         */
-        uint32_t reg_l2_mem_rdn_eco_high:32;
-    };
-    uint32_t val;
-} hp_system_l2_mem_rdn_eco_high_reg_t;
-
-
-/** Group: HP TCM RDN ECO CS REG */
-/** Type of tcm_rdn_eco_cs register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_hp_system_tcm_rdn_eco_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_hp_system_tcm_rdn_eco_en:1;
-        /** reg_hp_system_tcm_rdn_eco_result : RO; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_hp_system_tcm_rdn_eco_result:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_tcm_rdn_eco_cs_reg_t;
-
-
-/** Group: HP TCM RDN ECO LOW REG */
-/** Type of tcm_rdn_eco_low register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_hp_system_tcm_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_hp_system_tcm_rdn_eco_low:32;
-    };
-    uint32_t val;
-} hp_system_tcm_rdn_eco_low_reg_t;
-
-
-/** Group: HP TCM RDN ECO HIGH REG */
-/** Type of tcm_rdn_eco_high register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_hp_system_tcm_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
-         *  NA
-         */
-        uint32_t reg_hp_system_tcm_rdn_eco_high:32;
-    };
-    uint32_t val;
-} hp_system_tcm_rdn_eco_high_reg_t;
-
-
-/** Group: HP GPIO DED HOLD CTRL REG */
-/** Type of gpio_ded_hold_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_gpio_ded_hold : R/W; bitpos: [25:0]; default: 0;
-         *  hold control for gpio63~56
-         */
-        uint32_t reg_gpio_ded_hold:26;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} hp_system_gpio_ded_hold_ctrl_reg_t;
-
-
-/** Group: HP L2 MEM SW ECC BWE MASK REG */
-/** Type of l2_mem_sw_ecc_bwe_mask register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_sw_ecc_bwe_mask_ctrl : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to mask bwe hamming code bit
-         */
-        uint32_t reg_l2_mem_sw_ecc_bwe_mask_ctrl:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_l2_mem_sw_ecc_bwe_mask_reg_t;
-
-
-/** Group: HP USB20OTG MEM CTRL REG */
-/** Type of usb20otg_mem_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_usb20_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_usb20_mem_clk_force_on:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_usb20otg_mem_ctrl_reg_t;
-
-
-/** Group: configure_register */
-/** Type of tcm_int_raw register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tcm_parity_err_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t tcm_parity_err_int_raw:1;
-    };
-    uint32_t val;
-} hp_system_tcm_int_raw_reg_t;
-
-/** Type of tcm_int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tcm_parity_err_int_st : RO; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t tcm_parity_err_int_st:1;
-    };
-    uint32_t val;
-} hp_system_tcm_int_st_reg_t;
-
-/** Type of tcm_int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tcm_parity_err_int_ena : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t tcm_parity_err_int_ena:1;
-    };
-    uint32_t val;
-} hp_system_tcm_int_ena_reg_t;
-
-/** Type of tcm_int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tcm_parity_err_int_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t tcm_parity_err_int_clr:1;
-    };
-    uint32_t val;
-} hp_system_tcm_int_clr_reg_t;
-
-/** Type of core_ahb_timeout register
- *  need_des
- */
-typedef union {
-    struct {
-        /** core_ahb_timeout_en : R/W; bitpos: [0]; default: 1;
-         *  set this field to 1 to enable hp core0&1 ahb timeout handle
-         */
-        uint32_t core_ahb_timeout_en:1;
-        /** core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
-         *  This field used to set hp core0&1 ahb bus timeout  threshold
-         */
-        uint32_t core_ahb_timeout_thres:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} hp_system_core_ahb_timeout_reg_t;
-
-/** Type of core_ibus_timeout register
- *  need_des
- */
-typedef union {
-    struct {
-        /** core_ibus_timeout_en : R/W; bitpos: [0]; default: 1;
-         *  set this field to 1 to enable hp core0&1 ibus timeout handle
-         */
-        uint32_t core_ibus_timeout_en:1;
-        /** core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
-         *  This field used to set hp core0&1 ibus timeout  threshold
-         */
-        uint32_t core_ibus_timeout_thres:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} hp_system_core_ibus_timeout_reg_t;
-
-/** Type of core_dbus_timeout register
- *  need_des
- */
-typedef union {
-    struct {
-        /** core_dbus_timeout_en : R/W; bitpos: [0]; default: 1;
-         *  set this field to 1 to enable hp core0&1 dbus timeout handle
-         */
-        uint32_t core_dbus_timeout_en:1;
-        /** core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
-         *  This field used to set hp core0&1 dbus timeout  threshold
-         */
-        uint32_t core_dbus_timeout_thres:16;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} hp_system_core_dbus_timeout_reg_t;
-
-/** Type of icm_cpu_h2x_cfg register
- *  need_des
- */
-typedef union {
-    struct {
-        /** cpu_icm_h2x_post_wr_en : R/W; bitpos: [0]; default: 1;
-         *  need_des
-         */
-        uint32_t cpu_icm_h2x_post_wr_en:1;
-        /** cpu_icm_h2x_cut_through_en : R/W; bitpos: [1]; default: 1;
-         *  need_des
-         */
-        uint32_t cpu_icm_h2x_cut_through_en:1;
-        /** cpu_icm_h2x_bridge_busy : RO; bitpos: [2]; default: 0;
-         *  need_des
-         */
-        uint32_t cpu_icm_h2x_bridge_busy:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_icm_cpu_h2x_cfg_reg_t;
-
-/** Type of bitscrambler_peri_sel register
- *  Bitscrambler Peri Sel
- */
-typedef union {
-    struct {
-        /** bitscrambler_peri_rx_sel : R/W; bitpos: [3:0]; default: 15;
-         *  Set  this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0
-         *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
-         *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
-         *  else : none
-         */
-        uint32_t bitscrambler_peri_rx_sel:4;
-        /** bitscrambler_peri_tx_sel : R/W; bitpos: [7:4]; default: 15;
-         *  Set  this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0
-         *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
-         *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
-         *  else : none
-         */
-        uint32_t bitscrambler_peri_tx_sel:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} hp_system_bitscrambler_peri_sel_reg_t;
-
-
-/** Group: hp_system_TCM_PARITY_INT_RECORD_REG */
-/** Type of tcm_parity_int_record register
- *  need_des
- */
-typedef union {
-    struct {
-        /** tcm_parity_err_int_addr : RO; bitpos: [12:0]; default: 0;
-         *  hp tcm_parity_err_addr
-         */
-        uint32_t tcm_parity_err_int_addr:13;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} hp_system_tcm_parity_int_record_reg_t;
-
-
-/** Group: HP L1 CACHE PWR CTRL REG */
-/** Type of l1_cache_pwr_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l1_cache_mem_fo : R/W; bitpos: [5:0]; default: 0;
-         *  need_des
-         */
-        uint32_t reg_l1_cache_mem_fo:6;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_system_l1_cache_pwr_ctrl_reg_t;
-
-
-/** Group: HP L2 CACHE PWR CTRL REG */
-/** Type of l2_cache_pwr_ctrl register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_cache_mem_fo : R/W; bitpos: [1:0]; default: 0;
-         *  need_des
-         */
-        uint32_t reg_l2_cache_mem_fo:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_l2_cache_pwr_ctrl_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of cpu_waiti_conf register
- *  CPU_WAITI configuration register
- */
-typedef union {
-    struct {
-        /** cpu_wait_mode_force_on : R/W; bitpos: [0]; default: 1;
-         *  Set 1 to force cpu_waiti_clk enable.
-         */
-        uint32_t cpu_wait_mode_force_on:1;
-        /** cpu_waiti_delay_num : R/W; bitpos: [4:1]; default: 0;
-         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
-         *  will close
-         */
-        uint32_t cpu_waiti_delay_num:4;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} hp_system_cpu_waiti_conf_reg_t;
-
-/** Type of sys_core_debug_runstall_conf register
- *  Core Debug runstall configure register
- */
-typedef union {
-    struct {
-        /** sys_core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
-         *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
-         */
-        uint32_t sys_core_debug_runstall_enable:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_core_debug_runstall_conf_reg_t;
-
-/** Type of rsa_pd_ctrl register
- *  rsa pd ctrl register
- */
-typedef union {
-    struct {
-        /** rsa_mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down rsa internal memory.
-         */
-        uint32_t rsa_mem_force_pd:1;
-        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up rsa internal memory
-         */
-        uint32_t rsa_mem_force_pu:1;
-        /** rsa_mem_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power down rsa internal memory.
-         */
-        uint32_t rsa_mem_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_rsa_pd_ctrl_reg_t;
-
-/** Type of ecc_pd_ctrl register
- *  ecc pd ctrl register
- */
-typedef union {
-    struct {
-        /** ecc_mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down ecc internal memory.
-         */
-        uint32_t ecc_mem_force_pd:1;
-        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up ecc internal memory
-         */
-        uint32_t ecc_mem_force_pu:1;
-        /** ecc_mem_pd : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force power down ecc internal memory.
-         */
-        uint32_t ecc_mem_pd:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_ecc_pd_ctrl_reg_t;
-
-/** Type of rng_cfg register
- *  rng cfg register
- */
-typedef union {
-    struct {
-        /** rng_sample_enable : R/W; bitpos: [0]; default: 0;
-         *  enable rng sample chain
-         */
-        uint32_t rng_sample_enable:1;
-        uint32_t reserved_1:15;
-        /** rng_chain_clk_div_num : R/W; bitpos: [23:16]; default: 0;
-         *  chain clk div num to pad for debug
-         */
-        uint32_t rng_chain_clk_div_num:8;
-        /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0;
-         *  debug rng sample cnt
-         */
-        uint32_t rng_sample_cnt:8;
-    };
-    uint32_t val;
-} hp_system_rng_cfg_reg_t;
-
-/** Type of uart_pd_ctrl register
- *  ecc pd ctrl register
- */
-typedef union {
-    struct {
-        /** uart_mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to power down hp uart internal memory.
-         */
-        uint32_t uart_mem_force_pd:1;
-        /** uart_mem_force_pu : R/W; bitpos: [1]; default: 1;
-         *  Set this bit to force power up hp uart  internal memory
-         */
-        uint32_t uart_mem_force_pu:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_uart_pd_ctrl_reg_t;
-
-/** Type of peri_mem_clk_force_on register
- *  hp peri mem clk force on regpster
- */
-typedef union {
-    struct {
-        /** rmt_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force on mem clk in rmt
-         */
-        uint32_t rmt_mem_clk_force_on:1;
-        /** bitscrambler_tx_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to force on tx mem clk in bitscrambler
-         */
-        uint32_t bitscrambler_tx_mem_clk_force_on:1;
-        /** bitscrambler_rx_mem_clk_force_on : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force on rx mem clk in bitscrambler
-         */
-        uint32_t bitscrambler_rx_mem_clk_force_on:1;
-        /** gdma_mem_clk_force_on : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to force on mem clk in gdma
-         */
-        uint32_t gdma_mem_clk_force_on:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_system_peri_mem_clk_force_on_reg_t;
-
-
-/** Group: HP PERI1 APB POSTW EN REG */
-/** Type of peri1_apb_postw_en register
- *  NA
- */
-typedef union {
-    struct {
-        /** peri1_apb_postw_en : R/W; bitpos: [0]; default: 0;
-         *  hp_system_peri1 apb register interface post write enable, 1 will speed up write, but will
-         *  take some time to update value to register
-         */
-        uint32_t peri1_apb_postw_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_peri1_apb_postw_en_reg_t;
-
-
-/** Group: APB Sync Register */
-/** Type of sys_apb_sync_postw_en register
- *  N/A
- */
-typedef union {
-    struct {
-        /** sys_gmac_apb_postw_en : R/W; bitpos: [0]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_gmac_apb_postw_en:1;
-        /** sys_dsi_host_apb_postw_en : R/W; bitpos: [1]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_dsi_host_apb_postw_en:1;
-        /** sys_csi_host_apb_sync_postw_en : R/W; bitpos: [2]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_csi_host_apb_sync_postw_en:1;
-        /** sys_csi_host_apb_async_postw_en : R/W; bitpos: [3]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_csi_host_apb_async_postw_en:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} hp_system_apb_sync_postw_en_reg_t;
-
-
-/** Group: GDMA Ctonrol Register */
-/** Type of sys_gdma_ctrl register
- *  N/A
- */
-typedef union {
-    struct {
-        /** sys_debug_ch_num : R/W; bitpos: [1:0]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_debug_ch_num:2;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_gdma_ctrl_reg_t;
-
-
-/** Group: GMAC Control Register */
-/** Type of sys_gmac_ctrl0 register
- *  N/A
- */
-typedef union {
-    struct {
-        /** sys_ptp_pps : RO; bitpos: [0]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_ptp_pps:1;
-        /** sys_sbd_flowctrl : R/W; bitpos: [1]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_sbd_flowctrl:1;
-        /** sys_phy_intf_sel : R/W; bitpos: [4:2]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_phy_intf_sel:3;
-        /** sys_gmac_mem_clk_force_on : R/W; bitpos: [5]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_gmac_mem_clk_force_on:1;
-        /** sys_gmac_rst_clk_tx_n : RO; bitpos: [6]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_gmac_rst_clk_tx_n:1;
-        /** sys_gmac_rst_clk_rx_n : RO; bitpos: [7]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_gmac_rst_clk_rx_n:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} hp_system_gmac_ctrl0_reg_t;
-
-/** Type of sys_gmac_ctrl1 register
- *  N/A
- */
-typedef union {
-    struct {
-        /** sys_ptp_timestamp_l : RO; bitpos: [31:0]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_ptp_timestamp_l:32;
-    };
-    uint32_t val;
-} hp_system_gmac_ctrl1_reg_t;
-
-/** Type of sys_gmac_ctrl2 register
- *  N/A
- */
-typedef union {
-    struct {
-        /** sys_ptp_timestamp_h : RO; bitpos: [31:0]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_ptp_timestamp_h:32;
-    };
-    uint32_t val;
-} hp_system_gmac_ctrl2_reg_t;
-
-
-/** Group: VPU Control Register */
-/** Type of sys_vpu_ctrl register
- *  N/A
- */
-typedef union {
-    struct {
-        /** sys_ppa_lslp_mem_pd : R/W; bitpos: [0]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_ppa_lslp_mem_pd:1;
-        /** sys_jpeg_sdslp_mem_pd : R/W; bitpos: [1]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_jpeg_sdslp_mem_pd:1;
-        /** sys_jpeg_lslp_mem_pd : R/W; bitpos: [2]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_jpeg_lslp_mem_pd:1;
-        /** sys_jpeg_dslp_mem_pd : R/W; bitpos: [3]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_jpeg_dslp_mem_pd:1;
-        /** sys_dma2d_lslp_mem_pd : R/W; bitpos: [4]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_dma2d_lslp_mem_pd:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} hp_system_vpu_ctrl_reg_t;
-
-
-/** Group: USB OTG20 Control Register */
-/** Type of sys_usbotg20_ctrl register
- *  N/A
- */
-typedef union {
-    struct {
-        /** sys_otg_phy_test_done : RO; bitpos: [0]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_otg_phy_test_done:1;
-        /** sys_usb_mem_aux_ctrl : R/W; bitpos: [14:1]; default: 4896;
-         *  N/A
-         */
-        uint32_t sys_usb_mem_aux_ctrl:14;
-        /** sys_phy_suspendm : R/W; bitpos: [15]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_phy_suspendm:1;
-        /** sys_phy_suspend_force_en : R/W; bitpos: [16]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_phy_suspend_force_en:1;
-        /** sys_phy_rstn : R/W; bitpos: [17]; default: 1;
-         *  N/A
-         */
-        uint32_t sys_phy_rstn:1;
-        /** sys_phy_reset_force_en : R/W; bitpos: [18]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_phy_reset_force_en:1;
-        /** sys_phy_pll_force_en : R/W; bitpos: [19]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_phy_pll_force_en:1;
-        /** sys_phy_pll_en : R/W; bitpos: [20]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_phy_pll_en:1;
-        /** sys_otg_suspendm : R/W; bitpos: [21]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_otg_suspendm:1;
-        /** sys_otg_phy_txbitstuff_en : R/W; bitpos: [22]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_otg_phy_txbitstuff_en:1;
-        /** sys_otg_phy_refclk_mode : R/W; bitpos: [23]; default: 1;
-         *  N/A
-         */
-        uint32_t sys_otg_phy_refclk_mode:1;
-        /** sys_otg_phy_bisten : R/W; bitpos: [24]; default: 0;
-         *  N/A
-         */
-        uint32_t sys_otg_phy_bisten:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} hp_system_usbotg20_ctrl_reg_t;
-
-
-/** Group: hp_system_TCM_ERR_RESP_CTRL_REG */
-/** Type of tcm_err_resp_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** tcm_err_resp_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to turn on tcm error response
-         */
-        uint32_t tcm_err_resp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_tcm_err_resp_ctrl_reg_t;
-
-
-/** Group: HP L2 MEM REFRESH REG */
-/** Type of l2_mem_refresh register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_l2_mem_unit0_refersh_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit0_refersh_en:1;
-        /** reg_l2_mem_unit1_refersh_en : R/W; bitpos: [1]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit1_refersh_en:1;
-        /** reg_l2_mem_unit2_refersh_en : R/W; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit2_refersh_en:1;
-        /** reg_l2_mem_unit3_refersh_en : R/W; bitpos: [3]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit3_refersh_en:1;
-        /** reg_l2_mem_unit4_refersh_en : R/W; bitpos: [4]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit4_refersh_en:1;
-        /** reg_l2_mem_unit5_refersh_en : R/W; bitpos: [5]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit5_refersh_en:1;
-        /** reg_l2_mem_refersh_cnt_reset : R/W; bitpos: [6]; default: 1;
-         *  Set 1 to reset l2mem_refresh_cnt
-         */
-        uint32_t reg_l2_mem_refersh_cnt_reset:1;
-        /** reg_l2_mem_unit0_refresh_done : RO; bitpos: [7]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit0_refresh_done:1;
-        /** reg_l2_mem_unit1_refresh_done : RO; bitpos: [8]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit1_refresh_done:1;
-        /** reg_l2_mem_unit2_refresh_done : RO; bitpos: [9]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit2_refresh_done:1;
-        /** reg_l2_mem_unit3_refresh_done : RO; bitpos: [10]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit3_refresh_done:1;
-        /** reg_l2_mem_unit4_refresh_done : RO; bitpos: [11]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit4_refresh_done:1;
-        /** reg_l2_mem_unit5_refresh_done : RO; bitpos: [12]; default: 0;
-         *  NA
-         */
-        uint32_t reg_l2_mem_unit5_refresh_done:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} hp_system_l2_mem_refresh_reg_t;
-
-
-/** Group: HP TCM INIT REG */
-/** Type of tcm_init register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_tcm_init_en : R/W; bitpos: [0]; default: 0;
-         *  NA
-         */
-        uint32_t reg_tcm_init_en:1;
-        /** reg_tcm_init_cnt_reset : R/W; bitpos: [1]; default: 1;
-         *  Set 1 to reset tcm init cnt
-         */
-        uint32_t reg_tcm_init_cnt_reset:1;
-        /** reg_tcm_init_done : RO; bitpos: [2]; default: 0;
-         *  NA
-         */
-        uint32_t reg_tcm_init_done:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_tcm_init_reg_t;
-
-
-/** Group: hp_system_TCM_PARITY_CHECK_CTRL_REG */
-/** Type of tcm_parity_check_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** tcm_parity_check_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to turn on tcm parity check
-         */
-        uint32_t tcm_parity_check_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_tcm_parity_check_ctrl_reg_t;
-
-
-/** Group: hp_system_DESIGN_FOR_VERIFICATION0 */
-/** Type of design_for_verification0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** dfv0 : R/W; bitpos: [31:0]; default: 0;
-         *  register for DV
-         */
-        uint32_t dfv0:32;
-    };
-    uint32_t val;
-} hp_system_design_for_verification0_reg_t;
-
-
-/** Group: hp_system_DESIGN_FOR_VERIFICATION1 */
-/** Type of design_for_verification1 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** dfv1 : R/W; bitpos: [31:0]; default: 0;
-         *  register for DV
-         */
-        uint32_t dfv1:32;
-    };
-    uint32_t val;
-} hp_system_design_for_verification1_reg_t;
-
-
-/** Group: hp_system_PSRAM_FLASH_ADDR_INTERCHANGE */
-/** Type of psram_flash_addr_interchange register
- *  need_des
- */
-typedef union {
-    struct {
-        /** psram_flash_addr_interchange_cpu : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu
-         *  access through cache
-         */
-        uint32_t psram_flash_addr_interchange_cpu:1;
-        /** psram_flash_addr_interchange_dma : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to enable addr interchange between psram and flash in axi matrix when dma
-         *  device access, lp core access and hp core access through ahb
-         */
-        uint32_t psram_flash_addr_interchange_dma:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_psram_flash_addr_interchange_reg_t;
-
-
-/** Group: Interrupt Registers */
-/** Type of ahb2axi_bresp_err_int_raw register
- *  NA
- */
-typedef union {
-    struct {
-        /** cpu_icm_h2x_bresp_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
-         *  post write mode in ahb2axi.
-         */
-        uint32_t cpu_icm_h2x_bresp_err_int_raw:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_ahb2axi_bresp_err_int_raw_reg_t;
-
-/** Type of ahb2axi_bresp_err_int_st register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** cpu_icm_h2x_bresp_err_int_st : RO; bitpos: [31]; default: 0;
-         *  the masked interrupt status of  cpu_icm_h2x_bresp_err
-         */
-        uint32_t cpu_icm_h2x_bresp_err_int_st:1;
-    };
-    uint32_t val;
-} hp_system_ahb2axi_bresp_err_int_st_reg_t;
-
-/** Type of ahb2axi_bresp_err_int_ena register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** cpu_icm_h2x_bresp_err_int_ena : R/W; bitpos: [31]; default: 0;
-         *  Write 1 to enable cpu_icm_h2x_bresp_err int
-         */
-        uint32_t cpu_icm_h2x_bresp_err_int_ena:1;
-    };
-    uint32_t val;
-} hp_system_ahb2axi_bresp_err_int_ena_reg_t;
-
-/** Type of ahb2axi_bresp_err_int_clr register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** cpu_icm_h2x_bresp_err_int_clr : WT; bitpos: [31]; default: 0;
-         *  Write 1 to clear cpu_icm_h2x_bresp_err  int
-         */
-        uint32_t cpu_icm_h2x_bresp_err_int_clr:1;
-    };
-    uint32_t val;
-} hp_system_ahb2axi_bresp_err_int_clr_reg_t;
-
-/** Type of core_timeout_int_raw register
- *  Hp core bus timeout interrupt raw register
- */
-typedef union {
-    struct {
-        /** core0_ahb_timeout_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  the raw interrupt status of hp core0  ahb timeout
-         */
-        uint32_t core0_ahb_timeout_int_raw:1;
-        /** core1_ahb_timeout_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  the raw interrupt status of hp core1  ahb timeout
-         */
-        uint32_t core1_ahb_timeout_int_raw:1;
-        /** core0_ibus_timeout_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  the raw interrupt status of hp core0  ibus timeout
-         */
-        uint32_t core0_ibus_timeout_int_raw:1;
-        /** core1_ibus_timeout_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  the raw interrupt status of hp core1  ibus timeout
-         */
-        uint32_t core1_ibus_timeout_int_raw:1;
-        /** core0_dbus_timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  the raw interrupt status of hp core0  dbus timeout
-         */
-        uint32_t core0_dbus_timeout_int_raw:1;
-        /** core1_dbus_timeout_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  the raw interrupt status of hp core1  dbus timeout
-         */
-        uint32_t core1_dbus_timeout_int_raw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_system_core_timeout_int_raw_reg_t;
-
-/** Type of core_timeout_int_st register
- *  masked interrupt register
- */
-typedef union {
-    struct {
-        /** core0_ahb_timeout_int_st : RO; bitpos: [0]; default: 0;
-         *  the masked interrupt status of hp core0  ahb timeout
-         */
-        uint32_t core0_ahb_timeout_int_st:1;
-        /** core1_ahb_timeout_int_st : RO; bitpos: [1]; default: 0;
-         *  the masked interrupt status of hp core1  ahb timeout
-         */
-        uint32_t core1_ahb_timeout_int_st:1;
-        /** core0_ibus_timeout_int_st : RO; bitpos: [2]; default: 0;
-         *  the masked interrupt status of hp core0  ibus timeout
-         */
-        uint32_t core0_ibus_timeout_int_st:1;
-        /** core1_ibus_timeout_int_st : RO; bitpos: [3]; default: 0;
-         *  the masked interrupt status of hp core1  ibus timeout
-         */
-        uint32_t core1_ibus_timeout_int_st:1;
-        /** core0_dbus_timeout_int_st : RO; bitpos: [4]; default: 0;
-         *  the masked interrupt status of hp core0  dbus timeout
-         */
-        uint32_t core0_dbus_timeout_int_st:1;
-        /** core1_dbus_timeout_int_st : RO; bitpos: [5]; default: 0;
-         *  the masked interrupt status of hp core1  dbus timeout
-         */
-        uint32_t core1_dbus_timeout_int_st:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_system_core_timeout_int_st_reg_t;
-
-/** Type of core_timeout_int_ena register
- *  masked interrupt register
- */
-typedef union {
-    struct {
-        /** core0_ahb_timeout_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Write 1 to enable hp_system_core0_ahb_timeout int
-         */
-        uint32_t core0_ahb_timeout_int_ena:1;
-        /** core1_ahb_timeout_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Write 1 to enable hp_system_core1_ahb_timeout int
-         */
-        uint32_t core1_ahb_timeout_int_ena:1;
-        /** core0_ibus_timeout_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Write 1 to enable hp_system_core0_ibus_timeout int
-         */
-        uint32_t core0_ibus_timeout_int_ena:1;
-        /** core1_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Write 1 to enable hp_system_core1_ibus_timeout int
-         */
-        uint32_t core1_ibus_timeout_int_ena:1;
-        /** core0_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Write 1 to enable hp_system_core0_dbus_timeout int
-         */
-        uint32_t core0_dbus_timeout_int_ena:1;
-        /** core1_dbus_timeout_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Write 1 to enable hp_system_core1_dbus_timeout int
-         */
-        uint32_t core1_dbus_timeout_int_ena:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_system_core_timeout_int_ena_reg_t;
-
-/** Type of core_timeout_int_clr register
- *  interrupt clear register
- */
-typedef union {
-    struct {
-        /** core0_ahb_timeout_int_clr : WT; bitpos: [0]; default: 0;
-         *  Write 1 to clear hp_system_core0_ahb_timeout int
-         */
-        uint32_t core0_ahb_timeout_int_clr:1;
-        /** core1_ahb_timeout_int_clr : WT; bitpos: [1]; default: 0;
-         *  Write 1 to clear hp_system_core1_ahb_timeout int
-         */
-        uint32_t core1_ahb_timeout_int_clr:1;
-        /** core0_ibus_timeout_int_clr : WT; bitpos: [2]; default: 0;
-         *  Write 1 to clear hp_system_core0_ibus_timeout int
-         */
-        uint32_t core0_ibus_timeout_int_clr:1;
-        /** core1_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0;
-         *  Write 1 to clear hp_system_core1_ibus_timeout int
-         */
-        uint32_t core1_ibus_timeout_int_clr:1;
-        /** core0_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0;
-         *  Write 1 to clear hp_system_core0_dbus_timeout int
-         */
-        uint32_t core0_dbus_timeout_int_clr:1;
-        /** core1_dbus_timeout_int_clr : WT; bitpos: [5]; default: 0;
-         *  Write 1 to clear hp_system_core1_dbus_timeout int
-         */
-        uint32_t core1_dbus_timeout_int_clr:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} hp_system_core_timeout_int_clr_reg_t;
-
-
-/** Group: hp_system_L2_MEM_ERR_RESP_CTRL_REG */
-/** Type of l2_mem_err_resp_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** l2_mem_err_resp_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to turn on l2mem error response
-         */
-        uint32_t l2_mem_err_resp_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_l2_mem_err_resp_ctrl_reg_t;
-
-
-/** Group: hp_system_L2_MEM_AHB_BUFFER_CTRL_REG */
-/** Type of l2_mem_ahb_buffer_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** l2_mem_ahb_wrbuffer_en : R/W; bitpos: [0]; default: 0;
-         *  Set 1 to turn on l2mem ahb wr buffer
-         */
-        uint32_t l2_mem_ahb_wrbuffer_en:1;
-        /** l2_mem_ahb_rdbuffer_en : R/W; bitpos: [1]; default: 0;
-         *  Set 1 to turn on l2mem ahb rd buffer
-         */
-        uint32_t l2_mem_ahb_rdbuffer_en:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} hp_system_l2_mem_ahb_buffer_ctrl_reg_t;
-
-
-/** Group: hp_system_CORE_DMACTIVE_LPCORE_REG */
-/** Type of core_dmactive_lpcore register
- *  need_des
- */
-typedef union {
-    struct {
-        /** core_dmactive_lpcore : RO; bitpos: [0]; default: 0;
-         *  hp core dmactive_lpcore value
-         */
-        uint32_t core_dmactive_lpcore:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} hp_system_core_dmactive_lpcore_reg_t;
-
-
-/** Group: control registers */
-/** Type of core_err_resp_dis register
- *  need_des
- */
-typedef union {
-    struct {
-        /** core_err_resp_dis : R/W; bitpos: [2:0]; default: 0;
-         *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
-         *  disable ahb err resp.
-         */
-        uint32_t core_err_resp_dis:3;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} hp_system_core_err_resp_dis_reg_t;
-
-
-/** Group: HP GPIO O HYS CTRL0 REG */
-/** Type of gpio_o_hys_ctrl0 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_gpio_0_hys_low : R/W; bitpos: [31:0]; default: 0;
-         *  hys control for gpio47~16
-         */
-        uint32_t reg_gpio_0_hys_low:32;
-    };
-    uint32_t val;
-} hp_system_gpio_o_hys_ctrl0_reg_t;
-
-
-/** Group: HP GPIO O HYS CTRL1 REG */
-/** Type of gpio_o_hys_ctrl1 register
- *  NA
- */
-typedef union {
-    struct {
-        /** reg_gpio_0_hys_high : R/W; bitpos: [8:0]; default: 0;
-         *  hys control for gpio56~48
-         */
-        uint32_t reg_gpio_0_hys_high:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} hp_system_gpio_o_hys_ctrl1_reg_t;
-
-
-typedef struct hp_system_dev_t {
-    volatile hp_system_ver_date_reg_t sys_ver_date;
-    volatile hp_system_clk_en_reg_t clk_en;
-    uint32_t reserved_008[2];
-    volatile hp_system_cpu_int_from_cpu_0_reg_t cpu_int_from_cpu_0;
-    volatile hp_system_cpu_int_from_cpu_1_reg_t cpu_int_from_cpu_1;
-    volatile hp_system_cpu_int_from_cpu_2_reg_t cpu_int_from_cpu_2;
-    volatile hp_system_cpu_int_from_cpu_3_reg_t cpu_int_from_cpu_3;
-    volatile hp_system_cache_clk_config_reg_t cache_clk_config;
-    volatile hp_system_cache_reset_config_reg_t cache_reset_config;
-    uint32_t reserved_028;
-    volatile hp_system_dma_addr_ctrl_reg_t sys_dma_addr_ctrl;
-    uint32_t reserved_030;
-    volatile hp_system_tcm_ram_wrr_config_reg_t tcm_ram_wrr_config;
-    volatile hp_system_tcm_sw_parity_bwe_mask_reg_t tcm_sw_parity_bwe_mask;
-    volatile hp_system_tcm_ram_pwr_ctrl0_reg_t tcm_ram_pwr_ctrl0;
-    volatile hp_system_l2_rom_pwr_ctrl0_reg_t l2_rom_pwr_ctrl0;
-    uint32_t reserved_044[3];
-    volatile hp_system_probea_ctrl_reg_t probea_ctrl;
-    volatile hp_system_probeb_ctrl_reg_t probeb_ctrl;
-    uint32_t reserved_058;
-    volatile hp_system_probe_out_reg_t probe_out;
-    volatile hp_system_l2_mem_ram_pwr_ctrl0_reg_t l2_mem_ram_pwr_ctrl0;
-    volatile hp_system_cpu_corestalled_st_reg_t cpu_corestalled_st;
-    uint32_t reserved_068[2];
-    volatile hp_system_crypto_ctrl_reg_t crypto_ctrl;
-    volatile hp_system_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0;
-    volatile hp_system_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1;
-    volatile hp_system_rdn_eco_cs_reg_t sys_rdn_eco_cs;
-    volatile hp_system_cache_apb_postw_en_reg_t cache_apb_postw_en;
-    volatile hp_system_l2_mem_subsize_reg_t l2_mem_subsize;
-    uint32_t reserved_088[5];
-    volatile hp_system_l2_mem_int_raw_reg_t l2_mem_int_raw;
-    volatile hp_system_l2_mem_int_st_reg_t l2_mem_int_st;
-    volatile hp_system_l2_mem_int_ena_reg_t l2_mem_int_ena;
-    volatile hp_system_l2_mem_int_clr_reg_t l2_mem_int_clr;
-    volatile hp_system_l2_mem_l2_ram_ecc_reg_t l2_mem_l2_ram_ecc;
-    volatile hp_system_l2_mem_int_record0_reg_t l2_mem_int_record0;
-    volatile hp_system_l2_mem_int_record1_reg_t l2_mem_int_record1;
-    uint32_t reserved_0b8[3];
-    volatile hp_system_l2_mem_l2_cache_ecc_reg_t l2_mem_l2_cache_ecc;
-    volatile hp_system_l1cache_bus0_id_reg_t l1cache_bus0_id;
-    volatile hp_system_l1cache_bus1_id_reg_t l1cache_bus1_id;
-    uint32_t reserved_0d0[2];
-    volatile hp_system_l2_mem_rdn_eco_cs_reg_t l2_mem_rdn_eco_cs;
-    volatile hp_system_l2_mem_rdn_eco_low_reg_t l2_mem_rdn_eco_low;
-    volatile hp_system_l2_mem_rdn_eco_high_reg_t l2_mem_rdn_eco_high;
-    volatile hp_system_tcm_rdn_eco_cs_reg_t tcm_rdn_eco_cs;
-    volatile hp_system_tcm_rdn_eco_low_reg_t tcm_rdn_eco_low;
-    volatile hp_system_tcm_rdn_eco_high_reg_t tcm_rdn_eco_high;
-    volatile hp_system_gpio_ded_hold_ctrl_reg_t gpio_ded_hold_ctrl;
-    volatile hp_system_l2_mem_sw_ecc_bwe_mask_reg_t l2_mem_sw_ecc_bwe_mask;
-    volatile hp_system_usb20otg_mem_ctrl_reg_t usb20otg_mem_ctrl;
-    volatile hp_system_tcm_int_raw_reg_t tcm_int_raw;
-    volatile hp_system_tcm_int_st_reg_t tcm_int_st;
-    volatile hp_system_tcm_int_ena_reg_t tcm_int_ena;
-    volatile hp_system_tcm_int_clr_reg_t tcm_int_clr;
-    volatile hp_system_tcm_parity_int_record_reg_t tcm_parity_int_record;
-    volatile hp_system_l1_cache_pwr_ctrl_reg_t l1_cache_pwr_ctrl;
-    volatile hp_system_l2_cache_pwr_ctrl_reg_t l2_cache_pwr_ctrl;
-    volatile hp_system_cpu_waiti_conf_reg_t cpu_waiti_conf;
-    volatile hp_system_core_debug_runstall_conf_reg_t sys_core_debug_runstall_conf;
-    volatile hp_system_core_ahb_timeout_reg_t core_ahb_timeout;
-    volatile hp_system_core_ibus_timeout_reg_t core_ibus_timeout;
-    volatile hp_system_core_dbus_timeout_reg_t core_dbus_timeout;
-    uint32_t reserved_12c[3];
-    volatile hp_system_icm_cpu_h2x_cfg_reg_t icm_cpu_h2x_cfg;
-    volatile hp_system_peri1_apb_postw_en_reg_t peri1_apb_postw_en;
-    volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
-    volatile hp_system_apb_sync_postw_en_reg_t sys_apb_sync_postw_en;
-    volatile hp_system_gdma_ctrl_reg_t sys_gdma_ctrl;
-    volatile hp_system_gmac_ctrl0_reg_t sys_gmac_ctrl0;
-    volatile hp_system_gmac_ctrl1_reg_t sys_gmac_ctrl1;
-    volatile hp_system_gmac_ctrl2_reg_t sys_gmac_ctrl2;
-    volatile hp_system_vpu_ctrl_reg_t sys_vpu_ctrl;
-    volatile hp_system_usbotg20_ctrl_reg_t sys_usbotg20_ctrl;
-    volatile hp_system_tcm_err_resp_ctrl_reg_t tcm_err_resp_ctrl;
-    volatile hp_system_l2_mem_refresh_reg_t l2_mem_refresh;
-    volatile hp_system_tcm_init_reg_t tcm_init;
-    volatile hp_system_tcm_parity_check_ctrl_reg_t tcm_parity_check_ctrl;
-    volatile hp_system_design_for_verification0_reg_t design_for_verification0;
-    volatile hp_system_design_for_verification1_reg_t design_for_verification1;
-    uint32_t reserved_178[2];
-    volatile hp_system_psram_flash_addr_interchange_reg_t psram_flash_addr_interchange;
-    uint32_t reserved_184;
-    volatile hp_system_ahb2axi_bresp_err_int_raw_reg_t ahb2axi_bresp_err_int_raw;
-    volatile hp_system_ahb2axi_bresp_err_int_st_reg_t ahb2axi_bresp_err_int_st;
-    volatile hp_system_ahb2axi_bresp_err_int_ena_reg_t ahb2axi_bresp_err_int_ena;
-    volatile hp_system_ahb2axi_bresp_err_int_clr_reg_t ahb2axi_bresp_err_int_clr;
-    volatile hp_system_l2_mem_err_resp_ctrl_reg_t l2_mem_err_resp_ctrl;
-    volatile hp_system_l2_mem_ahb_buffer_ctrl_reg_t l2_mem_ahb_buffer_ctrl;
-    volatile hp_system_core_dmactive_lpcore_reg_t core_dmactive_lpcore;
-    volatile hp_system_core_err_resp_dis_reg_t core_err_resp_dis;
-    volatile hp_system_core_timeout_int_raw_reg_t core_timeout_int_raw;
-    volatile hp_system_core_timeout_int_st_reg_t core_timeout_int_st;
-    volatile hp_system_core_timeout_int_ena_reg_t core_timeout_int_ena;
-    volatile hp_system_core_timeout_int_clr_reg_t core_timeout_int_clr;
-    uint32_t reserved_1b8[2];
-    volatile hp_system_gpio_o_hys_ctrl0_reg_t gpio_o_hys_ctrl0;
-    volatile hp_system_gpio_o_hys_ctrl1_reg_t gpio_o_hys_ctrl1;
-    uint32_t reserved_1c8[2];
-    volatile hp_system_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
-    volatile hp_system_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
-    volatile hp_system_rng_cfg_reg_t rng_cfg;
-    volatile hp_system_uart_pd_ctrl_reg_t uart_pd_ctrl;
-    volatile hp_system_peri_mem_clk_force_on_reg_t peri_mem_clk_force_on;
-} hp_system_dev_t;
-
-extern hp_system_dev_t HP_SYSTEM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(hp_system_dev_t) == 0x1e4, "Invalid size of hp_system_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/i2s_reg.h b/components/soc/esp32p4/include/soc/i2s_reg.h
deleted file mode 100644
index cf9267487d1..00000000000
--- a/components/soc/esp32p4/include/soc/i2s_reg.h
+++ /dev/null
@@ -1,1268 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** I2S_INT_RAW_REG register
- *  I2S interrupt raw register, valid in level.
- */
-#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
-/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_RAW    (BIT(0))
-#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
-#define I2S_RX_DONE_INT_RAW_V  0x00000001U
-#define I2S_RX_DONE_INT_RAW_S  0
-/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_RAW    (BIT(1))
-#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
-#define I2S_TX_DONE_INT_RAW_V  0x00000001U
-#define I2S_TX_DONE_INT_RAW_S  1
-/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_RAW    (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
-#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_RX_HUNG_INT_RAW_S  2
-/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
- *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_RAW    (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
-#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
-#define I2S_TX_HUNG_INT_RAW_S  3
-
-/** I2S_INT_ST_REG register
- *  I2S interrupt status register.
- */
-#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
-/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ST    (BIT(0))
-#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
-#define I2S_RX_DONE_INT_ST_V  0x00000001U
-#define I2S_RX_DONE_INT_ST_S  0
-/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ST    (BIT(1))
-#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
-#define I2S_TX_DONE_INT_ST_V  0x00000001U
-#define I2S_TX_DONE_INT_ST_S  1
-/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ST    (BIT(2))
-#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
-#define I2S_RX_HUNG_INT_ST_V  0x00000001U
-#define I2S_RX_HUNG_INT_ST_S  2
-/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ST    (BIT(3))
-#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
-#define I2S_TX_HUNG_INT_ST_V  0x00000001U
-#define I2S_TX_HUNG_INT_ST_S  3
-
-/** I2S_INT_ENA_REG register
- *  I2S interrupt enable register.
- */
-#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
-/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_ENA    (BIT(0))
-#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
-#define I2S_RX_DONE_INT_ENA_V  0x00000001U
-#define I2S_RX_DONE_INT_ENA_S  0
-/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_ENA    (BIT(1))
-#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
-#define I2S_TX_DONE_INT_ENA_V  0x00000001U
-#define I2S_TX_DONE_INT_ENA_S  1
-/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_ENA    (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
-#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_RX_HUNG_INT_ENA_S  2
-/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_ENA    (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
-#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
-#define I2S_TX_HUNG_INT_ENA_S  3
-
-/** I2S_INT_CLR_REG register
- *  I2S interrupt clear register.
- */
-#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
-/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the i2s_rx_done_int interrupt
- */
-#define I2S_RX_DONE_INT_CLR    (BIT(0))
-#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
-#define I2S_RX_DONE_INT_CLR_V  0x00000001U
-#define I2S_RX_DONE_INT_CLR_S  0
-/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the i2s_tx_done_int interrupt
- */
-#define I2S_TX_DONE_INT_CLR    (BIT(1))
-#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
-#define I2S_TX_DONE_INT_CLR_V  0x00000001U
-#define I2S_TX_DONE_INT_CLR_S  1
-/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the i2s_rx_hung_int interrupt
- */
-#define I2S_RX_HUNG_INT_CLR    (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
-#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_RX_HUNG_INT_CLR_S  2
-/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the i2s_tx_hung_int interrupt
- */
-#define I2S_TX_HUNG_INT_CLR    (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
-#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
-#define I2S_TX_HUNG_INT_CLR_S  3
-
-/** I2S_RX_CONF_REG register
- *  I2S RX configure register
- */
-#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
-/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset receiver
- */
-#define I2S_RX_RESET    (BIT(0))
-#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
-#define I2S_RX_RESET_V  0x00000001U
-#define I2S_RX_RESET_S  0
-/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Rx AFIFO
- */
-#define I2S_RX_FIFO_RESET    (BIT(1))
-#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
-#define I2S_RX_FIFO_RESET_V  0x00000001U
-#define I2S_RX_FIFO_RESET_S  1
-/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start receiving data
- */
-#define I2S_RX_START    (BIT(2))
-#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
-#define I2S_RX_START_V  0x00000001U
-#define I2S_RX_START_S  2
-/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave receiver mode
- */
-#define I2S_RX_SLAVE_MOD    (BIT(3))
-#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
-#define I2S_RX_SLAVE_MOD_V  0x00000001U
-#define I2S_RX_SLAVE_MOD_S  3
-/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
- *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
- *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
- */
-#define I2S_RX_STOP_MODE    0x00000003U
-#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
-#define I2S_RX_STOP_MODE_V  0x00000003U
-#define I2S_RX_STOP_MODE_S  4
-/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable receiver  in mono mode
- */
-#define I2S_RX_MONO    (BIT(6))
-#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
-#define I2S_RX_MONO_V  0x00000001U
-#define I2S_RX_MONO_S  6
-/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
- */
-#define I2S_RX_BIG_ENDIAN    (BIT(7))
-#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
-#define I2S_RX_BIG_ENDIAN_V  0x00000001U
-#define I2S_RX_BIG_ENDIAN_S  7
-/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_RX_UPDATE    (BIT(8))
-#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
-#define I2S_RX_UPDATE_V  0x00000001U
-#define I2S_RX_UPDATE_S  8
-/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
- *  channel data value is valid in I2S RX mono mode.
- */
-#define I2S_RX_MONO_FST_VLD    (BIT(9))
-#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
-#define I2S_RX_MONO_FST_VLD_V  0x00000001U
-#define I2S_RX_MONO_FST_VLD_S  9
-/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
- *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_RX_PCM_CONF    0x00000003U
-#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
-#define I2S_RX_PCM_CONF_V  0x00000003U
-#define I2S_RX_PCM_CONF_S  10
-/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass Compress/Decompress module for received data.
- */
-#define I2S_RX_PCM_BYPASS    (BIT(12))
-#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
-#define I2S_RX_PCM_BYPASS_V  0x00000001U
-#define I2S_RX_PCM_BYPASS_S  12
-/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
- *  Set this bit to enable receiver in Phillips standard mode
- */
-#define I2S_RX_MSB_SHIFT    (BIT(13))
-#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
-#define I2S_RX_MSB_SHIFT_V  0x00000001U
-#define I2S_RX_MSB_SHIFT_S  13
-/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
- */
-#define I2S_RX_LEFT_ALIGN    (BIT(15))
-#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
-#define I2S_RX_LEFT_ALIGN_V  0x00000001U
-#define I2S_RX_LEFT_ALIGN_S  15
-/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
- */
-#define I2S_RX_24_FILL_EN    (BIT(16))
-#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
-#define I2S_RX_24_FILL_EN_V  0x00000001U
-#define I2S_RX_24_FILL_EN_S  16
-/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
- *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
- */
-#define I2S_RX_WS_IDLE_POL    (BIT(17))
-#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
-#define I2S_RX_WS_IDLE_POL_V  0x00000001U
-#define I2S_RX_WS_IDLE_POL_S  17
-/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
- *  is received first.
- */
-#define I2S_RX_BIT_ORDER    (BIT(18))
-#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
-#define I2S_RX_BIT_ORDER_V  0x00000001U
-#define I2S_RX_BIT_ORDER_S  18
-/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Rx mode . 0: Disable.
- */
-#define I2S_RX_TDM_EN    (BIT(19))
-#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
-#define I2S_RX_TDM_EN_V  0x00000001U
-#define I2S_RX_TDM_EN_S  19
-/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Rx mode . 0: Disable.
- */
-#define I2S_RX_PDM_EN    (BIT(20))
-#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
-#define I2S_RX_PDM_EN_V  0x00000001U
-#define I2S_RX_PDM_EN_S  20
-/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
- *  Bit clock configuration bits in receiver mode.
- */
-#define I2S_RX_BCK_DIV_NUM    0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
-#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_RX_BCK_DIV_NUM_S  21
-
-/** I2S_TX_CONF_REG register
- *  I2S TX configure register
- */
-#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
-/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
- *  Set this bit to reset transmitter
- */
-#define I2S_TX_RESET    (BIT(0))
-#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
-#define I2S_TX_RESET_V  0x00000001U
-#define I2S_TX_RESET_S  0
-/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
- *  Set this bit to reset Tx AFIFO
- */
-#define I2S_TX_FIFO_RESET    (BIT(1))
-#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
-#define I2S_TX_FIFO_RESET_V  0x00000001U
-#define I2S_TX_FIFO_RESET_S  1
-/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
- *  Set this bit to start transmitting data
- */
-#define I2S_TX_START    (BIT(2))
-#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
-#define I2S_TX_START_V  0x00000001U
-#define I2S_TX_START_S  2
-/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable slave transmitter mode
- */
-#define I2S_TX_SLAVE_MOD    (BIT(3))
-#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
-#define I2S_TX_SLAVE_MOD_V  0x00000001U
-#define I2S_TX_SLAVE_MOD_S  3
-/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
- */
-#define I2S_TX_STOP_EN    (BIT(4))
-#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
-#define I2S_TX_STOP_EN_V  0x00000001U
-#define I2S_TX_STOP_EN_S  4
-/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
- *  1: The value of Left channel data is equal to the value of right channel data in
- *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
- *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
- */
-#define I2S_TX_CHAN_EQUAL    (BIT(5))
-#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
-#define I2S_TX_CHAN_EQUAL_V  0x00000001U
-#define I2S_TX_CHAN_EQUAL_S  5
-/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enable transmitter in mono mode
- */
-#define I2S_TX_MONO    (BIT(6))
-#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
-#define I2S_TX_MONO_V  0x00000001U
-#define I2S_TX_MONO_S  6
-/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
- *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
- *  value.
- */
-#define I2S_TX_BIG_ENDIAN    (BIT(7))
-#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
-#define I2S_TX_BIG_ENDIAN_V  0x00000001U
-#define I2S_TX_BIG_ENDIAN_S  7
-/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
- *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
- *  bit will be cleared by hardware after update register done.
- */
-#define I2S_TX_UPDATE    (BIT(8))
-#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
-#define I2S_TX_UPDATE_V  0x00000001U
-#define I2S_TX_UPDATE_S  8
-/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
- *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
- *  channel data value is valid in I2S TX mono mode.
- */
-#define I2S_TX_MONO_FST_VLD    (BIT(9))
-#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
-#define I2S_TX_MONO_FST_VLD_V  0x00000001U
-#define I2S_TX_MONO_FST_VLD_S  9
-/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
- *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
- *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
- */
-#define I2S_TX_PCM_CONF    0x00000003U
-#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
-#define I2S_TX_PCM_CONF_V  0x00000003U
-#define I2S_TX_PCM_CONF_S  10
-/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
- *  Set this bit to bypass  Compress/Decompress module for transmitted data.
- */
-#define I2S_TX_PCM_BYPASS    (BIT(12))
-#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
-#define I2S_TX_PCM_BYPASS_V  0x00000001U
-#define I2S_TX_PCM_BYPASS_S  12
-/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
- *  Set this bit to enable transmitter in Phillips standard mode
- */
-#define I2S_TX_MSB_SHIFT    (BIT(13))
-#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
-#define I2S_TX_MSB_SHIFT_V  0x00000001U
-#define I2S_TX_MSB_SHIFT_S  13
-/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
- *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
- *  generate pos/neg edge in master mode.
- */
-#define I2S_TX_BCK_NO_DLY    (BIT(14))
-#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
-#define I2S_TX_BCK_NO_DLY_V  0x00000001U
-#define I2S_TX_BCK_NO_DLY_S  14
-/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
- *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
- */
-#define I2S_TX_LEFT_ALIGN    (BIT(15))
-#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
-#define I2S_TX_LEFT_ALIGN_V  0x00000001U
-#define I2S_TX_LEFT_ALIGN_S  15
-/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
- *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
- */
-#define I2S_TX_24_FILL_EN    (BIT(16))
-#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
-#define I2S_TX_24_FILL_EN_V  0x00000001U
-#define I2S_TX_24_FILL_EN_S  16
-/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
- *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
- *  WS should be 1 when sending left channel data, and WS is 0in right channel.
- */
-#define I2S_TX_WS_IDLE_POL    (BIT(17))
-#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
-#define I2S_TX_WS_IDLE_POL_V  0x00000001U
-#define I2S_TX_WS_IDLE_POL_S  17
-/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
- *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
- *  sent first.
- */
-#define I2S_TX_BIT_ORDER    (BIT(18))
-#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
-#define I2S_TX_BIT_ORDER_V  0x00000001U
-#define I2S_TX_BIT_ORDER_S  18
-/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable I2S TDM Tx mode . 0: Disable.
- */
-#define I2S_TX_TDM_EN    (BIT(19))
-#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
-#define I2S_TX_TDM_EN_V  0x00000001U
-#define I2S_TX_TDM_EN_S  19
-/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
- *  1: Enable I2S PDM Tx mode . 0: Disable.
- */
-#define I2S_TX_PDM_EN    (BIT(20))
-#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
-#define I2S_TX_PDM_EN_V  0x00000001U
-#define I2S_TX_PDM_EN_S  20
-/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
- *  Bit clock configuration bits in transmitter mode.
- */
-#define I2S_TX_BCK_DIV_NUM    0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
-#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
-#define I2S_TX_BCK_DIV_NUM_S  21
-/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
- *  I2S transmitter channel mode configuration bits.
- */
-#define I2S_TX_CHAN_MOD    0x00000007U
-#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
-#define I2S_TX_CHAN_MOD_V  0x00000007U
-#define I2S_TX_CHAN_MOD_S  27
-/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
- *  Enable signal loop back mode with transmitter module and receiver module sharing
- *  the same WS and BCK signals.
- */
-#define I2S_SIG_LOOPBACK    (BIT(30))
-#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
-#define I2S_SIG_LOOPBACK_V  0x00000001U
-#define I2S_SIG_LOOPBACK_S  30
-
-/** I2S_RX_CONF1_REG register
- *  I2S RX configure register 1
- */
-#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
-/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
- *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
- *  T_bck
- */
-#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
-#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
-#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
-#define I2S_RX_TDM_WS_WIDTH_S  0
-/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
- *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_RX_BITS_MOD    0x0000001FU
-#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
-#define I2S_RX_BITS_MOD_V  0x0000001FU
-#define I2S_RX_BITS_MOD_S  14
-/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
- *  I2S Rx half sample bits -1.
- */
-#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
-#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
-#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
-#define I2S_RX_HALF_SAMPLE_BITS_S  19
-/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
- *  The Rx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
-#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_RX_TDM_CHAN_BITS_S  27
-
-/** I2S_TX_CONF1_REG register
- *  I2S TX configure register 1
- */
-#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
-/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
- *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
- *  T_bck
- */
-#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
-#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
-#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
-#define I2S_TX_TDM_WS_WIDTH_S  0
-/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
- *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
- *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
- *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
- *  channel data is in 32-bit-mode.
- */
-#define I2S_TX_BITS_MOD    0x0000001FU
-#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
-#define I2S_TX_BITS_MOD_V  0x0000001FU
-#define I2S_TX_BITS_MOD_S  14
-/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
- *  I2S Tx half sample bits -1.
- */
-#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
-#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
-#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
-#define I2S_TX_HALF_SAMPLE_BITS_S  19
-/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
- *  The Tx bit number for each channel minus 1in TDM mode.
- */
-#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
-#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
-#define I2S_TX_TDM_CHAN_BITS_S  27
-
-/** I2S_TX_PCM2PDM_CONF_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40)
-/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
- *  I2S TX PDM OSR2 value
- */
-#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
-#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
-#define I2S_TX_PDM_SINC_OSR2_S  1
-/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
- *  I2S TX PDM prescale for sigmadelta
- */
-#define I2S_TX_PDM_PRESCALE    0x000000FFU
-#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
-#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
-#define I2S_TX_PDM_PRESCALE_S  5
-/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
-#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_HP_IN_SHIFT_S  13
-/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
-#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_LP_IN_SHIFT_S  15
-/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
-#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
-/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
- *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
- */
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
-/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
- *  I2S TX PDM sigmadelta dither2 value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
-/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
- *  I2S TX PDM sigmadelta dither value
- */
-#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
-#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
-#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
-/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
- *  I2S TX PDM dac mode enable
- */
-#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
-#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_2OUT_EN_S  23
-/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
- *  I2S TX PDM dac 2channel enable
- */
-#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
-#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
-#define I2S_TX_PDM_DAC_MODE_EN_S  24
-/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
- *  I2S TX PDM Converter enable
- */
-#define I2S_PCM2PDM_CONV_EN    (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
-#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
-#define I2S_PCM2PDM_CONV_EN_S  25
-
-/** I2S_TX_PCM2PDM_CONF1_REG register
- *  I2S TX PCM2PDM configuration register
- */
-#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44)
-/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
- *  I2S TX PDM Fp
- */
-#define I2S_TX_PDM_FP    0x000003FFU
-#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
-#define I2S_TX_PDM_FP_V  0x000003FFU
-#define I2S_TX_PDM_FP_S  0
-/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
- *  I2S TX PDM Fs
- */
-#define I2S_TX_PDM_FS    0x000003FFU
-#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
-#define I2S_TX_PDM_FS_V  0x000003FFU
-#define I2S_TX_PDM_FS_S  10
-/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
- *  I2S_TX_IIR_HP_MULT12_5[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
-#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_5_S  20
-/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
- *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
- *  I2S_TX_IIR_HP_MULT12_0[2:0])
- */
-#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
-#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
-#define I2S_TX_IIR_HP_MULT12_0_S  23
-
-/** I2S_RX_PDM2PCM_CONF_REG register
- *  I2S RX configure register
- */
-#define I2S_RX_PDM2PCM_CONF_REG(i) (REG_I2S_BASE(i) + 0x48)
-/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
- *  1: Enable PDM2PCM RX mode. 0: DIsable.
- */
-#define I2S_RX_PDM2PCM_EN    (BIT(19))
-#define I2S_RX_PDM2PCM_EN_M  (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
-#define I2S_RX_PDM2PCM_EN_V  0x00000001U
-#define I2S_RX_PDM2PCM_EN_S  19
-/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
- *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
- *  sampling rate is 128. 0: down sampling rate is 64.
- */
-#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
-#define I2S_RX_PDM_SINC_DSR_16_EN_M  (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
-#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
-#define I2S_RX_PDM_SINC_DSR_16_EN_S  20
-/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
- *  Configure PDM RX amplify number.
- */
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
-#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
-/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
- *  I2S PDM RX bypass hp filter or not.
- */
-#define I2S_RX_PDM_HP_BYPASS    (BIT(25))
-#define I2S_RX_PDM_HP_BYPASS_M  (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
-#define I2S_RX_PDM_HP_BYPASS_V  0x00000001U
-#define I2S_RX_PDM_HP_BYPASS_S  25
-/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
- *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
- *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
- */
-#define I2S_RX_IIR_HP_MULT12_5    0x00000007U
-#define I2S_RX_IIR_HP_MULT12_5_M  (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
-#define I2S_RX_IIR_HP_MULT12_5_V  0x00000007U
-#define I2S_RX_IIR_HP_MULT12_5_S  26
-/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
- *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
- *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
- */
-#define I2S_RX_IIR_HP_MULT12_0    0x00000007U
-#define I2S_RX_IIR_HP_MULT12_0_M  (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
-#define I2S_RX_IIR_HP_MULT12_0_V  0x00000007U
-#define I2S_RX_IIR_HP_MULT12_0_S  29
-
-/** I2S_RX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
-/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
-#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
-/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
-#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
-/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
-#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
-/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
-#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
-/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
-#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
-/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
-#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
-/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
-#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
-/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
- *  input 0 in this channel.
- */
-#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
-#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
-#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
-/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
-#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN8_EN_S  8
-/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
-#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN9_EN_S  9
-/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
-#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN10_EN_S  10
-/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
-#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN11_EN_S  11
-/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
-#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN12_EN_S  12
-/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
-#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN13_EN_S  13
-/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
-#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN14_EN_S  14
-/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
- *  in this channel.
- */
-#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
-#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_RX_TDM_CHAN15_EN_S  15
-/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
-#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
-
-/** I2S_TX_TDM_CTRL_REG register
- *  I2S TX TDM mode control register
- */
-#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
-/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
-#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN0_EN_S  0
-/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
-#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN1_EN_S  1
-/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
-#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN2_EN_S  2
-/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
-#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN3_EN_S  3
-/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
-#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN4_EN_S  4
-/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
-#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN5_EN_S  5
-/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
-#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN6_EN_S  6
-/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
-#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN7_EN_S  7
-/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
-#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN8_EN_S  8
-/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
-#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN9_EN_S  9
-/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
-#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN10_EN_S  10
-/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
-#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN11_EN_S  11
-/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
-#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN12_EN_S  12
-/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
-#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN13_EN_S  13
-/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
-#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN14_EN_S  14
-/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
- *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
- *  0 in this channel.
- */
-#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
-#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
-#define I2S_TX_TDM_CHAN15_EN_S  15
-/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
- *  The total channel number of I2S TX TDM mode.
- */
-#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
-#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
-#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
-/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
- *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
- *  only the data of the enabled channels is sent, then this bit should be set. Clear
- *  it when all the data stored in DMA TX buffer is for enabled channels.
- */
-#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
-#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
-#define I2S_TX_TDM_SKIP_MSK_EN_S  20
-
-/** I2S_RX_TIMING_REG register
- *  I2S RX timing control register
- */
-#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
-/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD_IN_DM    0x00000003U
-#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
-#define I2S_RX_SD_IN_DM_V  0x00000003U
-#define I2S_RX_SD_IN_DM_S  0
-/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0;
- *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD1_IN_DM    0x00000003U
-#define I2S_RX_SD1_IN_DM_M  (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S)
-#define I2S_RX_SD1_IN_DM_V  0x00000003U
-#define I2S_RX_SD1_IN_DM_S  4
-/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0;
- *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD2_IN_DM    0x00000003U
-#define I2S_RX_SD2_IN_DM_M  (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S)
-#define I2S_RX_SD2_IN_DM_V  0x00000003U
-#define I2S_RX_SD2_IN_DM_S  8
-/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0;
- *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_SD3_IN_DM    0x00000003U
-#define I2S_RX_SD3_IN_DM_M  (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S)
-#define I2S_RX_SD3_IN_DM_V  0x00000003U
-#define I2S_RX_SD3_IN_DM_S  12
-/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_OUT_DM    0x00000003U
-#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
-#define I2S_RX_WS_OUT_DM_V  0x00000003U
-#define I2S_RX_WS_OUT_DM_S  16
-/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_OUT_DM    0x00000003U
-#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
-#define I2S_RX_BCK_OUT_DM_V  0x00000003U
-#define I2S_RX_BCK_OUT_DM_S  20
-/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_WS_IN_DM    0x00000003U
-#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
-#define I2S_RX_WS_IN_DM_V  0x00000003U
-#define I2S_RX_WS_IN_DM_S  24
-/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_RX_BCK_IN_DM    0x00000003U
-#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
-#define I2S_RX_BCK_IN_DM_V  0x00000003U
-#define I2S_RX_BCK_IN_DM_S  28
-
-/** I2S_TX_TIMING_REG register
- *  I2S TX timing control register
- */
-#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
-/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
- *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD_OUT_DM    0x00000003U
-#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
-#define I2S_TX_SD_OUT_DM_V  0x00000003U
-#define I2S_TX_SD_OUT_DM_S  0
-/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
- *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_SD1_OUT_DM    0x00000003U
-#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
-#define I2S_TX_SD1_OUT_DM_V  0x00000003U
-#define I2S_TX_SD1_OUT_DM_S  4
-/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
- *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_OUT_DM    0x00000003U
-#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
-#define I2S_TX_WS_OUT_DM_V  0x00000003U
-#define I2S_TX_WS_OUT_DM_S  16
-/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
- *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_OUT_DM    0x00000003U
-#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
-#define I2S_TX_BCK_OUT_DM_V  0x00000003U
-#define I2S_TX_BCK_OUT_DM_S  20
-/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
- *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_WS_IN_DM    0x00000003U
-#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
-#define I2S_TX_WS_IN_DM_V  0x00000003U
-#define I2S_TX_WS_IN_DM_S  24
-/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
- *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
- *  delay by neg edge. 3: not used.
- */
-#define I2S_TX_BCK_IN_DM    0x00000003U
-#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
-#define I2S_TX_BCK_IN_DM_V  0x00000003U
-#define I2S_TX_BCK_IN_DM_S  28
-
-/** I2S_LC_HUNG_CONF_REG register
- *  I2S HUNG configure register.
- */
-#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
-/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
- *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
- *  when fifo hung counter is equal to this value
- */
-#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
-#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
-#define I2S_LC_FIFO_TIMEOUT_S  0
-/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
- *  The bits are used to scale tick counter threshold. The tick counter is reset when
- *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
- */
-#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
-/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
- *  The enable bit for FIFO timeout
- */
-#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
-#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
-#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
-
-/** I2S_RXEOF_NUM_REG register
- *  I2S RX data number control register.
- */
-#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
-/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
- *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
- *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
- */
-#define I2S_RX_EOF_NUM    0x00000FFFU
-#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
-#define I2S_RX_EOF_NUM_V  0x00000FFFU
-#define I2S_RX_EOF_NUM_S  0
-
-/** I2S_CONF_SIGLE_DATA_REG register
- *  I2S signal data register
- */
-#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
-/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
- *  The configured constant channel data to be sent out.
- */
-#define I2S_SINGLE_DATA    0xFFFFFFFFU
-#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
-#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
-#define I2S_SINGLE_DATA_S  0
-
-/** I2S_STATE_REG register
- *  I2S TX status register
- */
-#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
-/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
- *  1: i2s_tx is idle state. 0: i2s_tx is working.
- */
-#define I2S_TX_IDLE    (BIT(0))
-#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
-#define I2S_TX_IDLE_V  0x00000001U
-#define I2S_TX_IDLE_S  0
-
-/** I2S_ETM_CONF_REG register
- *  I2S ETM configure register
- */
-#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
-/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
- *  I2S ETM send x words event. When sending word number of
- *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
-#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_TX_SEND_WORD_NUM_S  0
-/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
- *  I2S ETM receive x words event. When receiving word number of
- *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
- */
-#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
-#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
-
-/** I2S_FIFO_CNT_REG register
- *  I2S sync counter register
- */
-#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x74)
-/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
- *  tx fifo counter value.
- */
-#define I2S_TX_FIFO_CNT    0x7FFFFFFFU
-#define I2S_TX_FIFO_CNT_M  (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S)
-#define I2S_TX_FIFO_CNT_V  0x7FFFFFFFU
-#define I2S_TX_FIFO_CNT_S  0
-/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset tx fifo counter.
- */
-#define I2S_TX_FIFO_CNT_RST    (BIT(31))
-#define I2S_TX_FIFO_CNT_RST_M  (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S)
-#define I2S_TX_FIFO_CNT_RST_V  0x00000001U
-#define I2S_TX_FIFO_CNT_RST_S  31
-
-/** I2S_BCK_CNT_REG register
- *  I2S sync counter register
- */
-#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x78)
-/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
- *  tx bck counter value.
- */
-#define I2S_TX_BCK_CNT    0x7FFFFFFFU
-#define I2S_TX_BCK_CNT_M  (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S)
-#define I2S_TX_BCK_CNT_V  0x7FFFFFFFU
-#define I2S_TX_BCK_CNT_S  0
-/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset tx bck counter.
- */
-#define I2S_TX_BCK_CNT_RST    (BIT(31))
-#define I2S_TX_BCK_CNT_RST_M  (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S)
-#define I2S_TX_BCK_CNT_RST_V  0x00000001U
-#define I2S_TX_BCK_CNT_RST_S  31
-
-/** I2S_CLK_GATE_REG register
- *  Clock gate register
- */
-#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0x7c)
-/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  set this bit to enable clock gate
- */
-#define I2S_CLK_EN    (BIT(0))
-#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
-#define I2S_CLK_EN_V  0x00000001U
-#define I2S_CLK_EN_S  0
-
-/** I2S_DATE_REG register
- *  Version control register
- */
-#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80)
-/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024;
- *  I2S version control register
- */
-#define I2S_DATE    0x0FFFFFFFU
-#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
-#define I2S_DATE_V  0x0FFFFFFFU
-#define I2S_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/i2s_struct.h b/components/soc/esp32p4/include/soc/i2s_struct.h
deleted file mode 100644
index 6e05f6a2eb8..00000000000
--- a/components/soc/esp32p4/include/soc/i2s_struct.h
+++ /dev/null
@@ -1,1012 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  I2S interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_raw:1;
-        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_raw:1;
-        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_raw:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_raw_reg_t;
-
-/** Type of int_st register
- *  I2S interrupt status register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_st:1;
-        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_st:1;
-        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_st:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_st_reg_t;
-
-/** Type of int_ena register
- *  I2S interrupt enable register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_ena:1;
-        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_ena:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_ena_reg_t;
-
-/** Type of int_clr register
- *  I2S interrupt clear register.
- */
-typedef union {
-    struct {
-        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the i2s_rx_done_int interrupt
-         */
-        uint32_t rx_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the i2s_tx_done_int interrupt
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the i2s_rx_hung_int interrupt
-         */
-        uint32_t rx_hung_int_clr:1;
-        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the i2s_tx_hung_int interrupt
-         */
-        uint32_t tx_hung_int_clr:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} i2s_int_clr_reg_t;
-
-
-/** Group: RX Control and configuration registers */
-/** Type of rx_conf register
- *  I2S RX configure register
- */
-typedef union {
-    struct {
-        /** rx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset receiver
-         */
-        uint32_t rx_reset:1;
-        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Rx AFIFO
-         */
-        uint32_t rx_fifo_reset:1;
-        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start receiving data
-         */
-        uint32_t rx_start:1;
-        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave receiver mode
-         */
-        uint32_t rx_slave_mod:1;
-        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
-         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
-         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-         */
-        uint32_t rx_stop_mode:2;
-        /** rx_mono : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable receiver  in mono mode
-         */
-        uint32_t rx_mono:1;
-        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-         */
-        uint32_t rx_big_endian:1;
-        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t rx_update:1;
-        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
-         *  channel data value is valid in I2S RX mono mode.
-         */
-        uint32_t rx_mono_fst_vld:1;
-        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
-         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t rx_pcm_conf:2;
-        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass Compress/Decompress module for received data.
-         */
-        uint32_t rx_pcm_bypass:1;
-        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to enable receiver in Phillips standard mode
-         */
-        uint32_t rx_msb_shift:1;
-        uint32_t reserved_14:1;
-        /** rx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-         */
-        uint32_t rx_left_align:1;
-        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-         */
-        uint32_t rx_24_fill_en:1;
-        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
-         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-         */
-        uint32_t rx_ws_idle_pol:1;
-        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
-         *  is received first.
-         */
-        uint32_t rx_bit_order:1;
-        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_tdm_en:1;
-        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Rx mode . 0: Disable.
-         */
-        uint32_t rx_pdm_en:1;
-        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
-         *  Bit clock configuration bits in receiver mode.
-         */
-        uint32_t rx_bck_div_num:6;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} i2s_rx_conf_reg_t;
-
-/** Type of rx_conf1 register
- *  I2S RX configure register 1
- */
-typedef union {
-    struct {
-        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
-         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
-         *  T_bck
-         */
-        uint32_t rx_tdm_ws_width:9;
-        uint32_t reserved_9:5;
-        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
-         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t rx_bits_mod:5;
-        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
-         *  I2S Rx half sample bits -1.
-         */
-        uint32_t rx_half_sample_bits:8;
-        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
-         *  The Rx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t rx_tdm_chan_bits:5;
-    };
-    uint32_t val;
-} i2s_rx_conf1_reg_t;
-
-/** Type of rx_pdm2pcm_conf register
- *  I2S RX configure register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:19;
-        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable PDM2PCM RX mode. 0: DIsable.
-         */
-        uint32_t rx_pdm2pcm_en:1;
-        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
-         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
-         *  sampling rate is 128. 0: down sampling rate is 64.
-         */
-        uint32_t rx_pdm_sinc_dsr_16_en:1;
-        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
-         *  Configure PDM RX amplify number.
-         */
-        uint32_t rx_pdm2pcm_amplify_num:4;
-        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
-         *  I2S PDM RX bypass hp filter or not.
-         */
-        uint32_t rx_pdm_hp_bypass:1;
-        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
-         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
-         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
-         */
-        uint32_t rx_iir_hp_mult12_5:3;
-        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
-         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
-         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
-         */
-        uint32_t rx_iir_hp_mult12_0:3;
-    };
-    uint32_t val;
-} i2s_rx_pdm2pcm_conf_reg_t;
-
-/** Type of tx_pcm2pdm_conf register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
-         *  I2S TX PDM bypass hp filter or not. The option has been removed.
-         */
-        uint32_t tx_pdm_hp_bypass:1;
-        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
-         *  I2S TX PDM OSR2 value
-         */
-        uint32_t tx_pdm_sinc_osr2:4;
-        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
-         *  I2S TX PDM prescale for sigmadelta
-         */
-        uint32_t tx_pdm_prescale:8;
-        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_hp_in_shift:2;
-        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_lp_in_shift:2;
-        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sinc_in_shift:2;
-        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
-         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-         */
-        uint32_t tx_pdm_sigmadelta_in_shift:2;
-        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
-         *  I2S TX PDM sigmadelta dither2 value
-         */
-        uint32_t tx_pdm_sigmadelta_dither2:1;
-        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
-         *  I2S TX PDM sigmadelta dither value
-         */
-        uint32_t tx_pdm_sigmadelta_dither:1;
-        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
-         *  I2S TX PDM dac mode enable
-         */
-        uint32_t tx_pdm_dac_2out_en:1;
-        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
-         *  I2S TX PDM dac 2channel enable
-         */
-        uint32_t tx_pdm_dac_mode_en:1;
-        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
-         *  I2S TX PDM Converter enable
-         */
-        uint32_t pcm2pdm_conv_en:1;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf_reg_t;
-
-/** Type of tx_pcm2pdm_conf1 register
- *  I2S TX PCM2PDM configuration register
- */
-typedef union {
-    struct {
-        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
-         *  I2S TX PDM Fp
-         */
-        uint32_t tx_pdm_fp:10;
-        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
-         *  I2S TX PDM Fs
-         */
-        uint32_t tx_pdm_fs:10;
-        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_5[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_5:3;
-        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
-         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
-         *  I2S_TX_IIR_HP_MULT12_0[2:0])
-         */
-        uint32_t tx_iir_hp_mult12_0:3;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} i2s_tx_pcm2pdm_conf1_reg_t;
-
-/** Type of rx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan0_en:1;
-        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan1_en:1;
-        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan2_en:1;
-        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan3_en:1;
-        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan4_en:1;
-        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan5_en:1;
-        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan6_en:1;
-        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
-         *  input 0 in this channel.
-         */
-        uint32_t rx_tdm_pdm_chan7_en:1;
-        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan8_en:1;
-        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan9_en:1;
-        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan10_en:1;
-        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan11_en:1;
-        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan12_en:1;
-        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan13_en:1;
-        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan14_en:1;
-        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
-         *  in this channel.
-         */
-        uint32_t rx_tdm_chan15_en:1;
-        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t rx_tdm_tot_chan_num:4;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_rx_tdm_ctrl_reg_t;
-
-/** Type of rx_eof_num register
- *  I2S RX data number control register.
- */
-typedef union {
-    struct {
-        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
-         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
-         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
-         */
-        uint32_t rx_eof_num:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_rx_eof_num_reg_t;
-
-
-/** Group: TX Control and configuration registers */
-/** Type of tx_conf register
- *  I2S TX configure register
- */
-typedef union {
-    struct {
-        /** tx_reset : WT; bitpos: [0]; default: 0;
-         *  Set this bit to reset transmitter
-         */
-        uint32_t tx_reset:1;
-        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
-         *  Set this bit to reset Tx AFIFO
-         */
-        uint32_t tx_fifo_reset:1;
-        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
-         *  Set this bit to start transmitting data
-         */
-        uint32_t tx_start:1;
-        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable slave transmitter mode
-         */
-        uint32_t tx_slave_mod:1;
-        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
-         */
-        uint32_t tx_stop_en:1;
-        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
-         *  1: The value of Left channel data is equal to the value of right channel data in
-         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
-         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-         */
-        uint32_t tx_chan_equal:1;
-        /** tx_mono : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enable transmitter in mono mode
-         */
-        uint32_t tx_mono:1;
-        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
-         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
-         *  value.
-         */
-        uint32_t tx_big_endian:1;
-        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
-         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
-         *  bit will be cleared by hardware after update register done.
-         */
-        uint32_t tx_update:1;
-        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
-         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
-         *  channel data value is valid in I2S TX mono mode.
-         */
-        uint32_t tx_mono_fst_vld:1;
-        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
-         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-         */
-        uint32_t tx_pcm_conf:2;
-        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
-         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
-         */
-        uint32_t tx_pcm_bypass:1;
-        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
-         *  Set this bit to enable transmitter in Phillips standard mode
-         */
-        uint32_t tx_msb_shift:1;
-        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
-         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
-         *  generate pos/neg edge in master mode.
-         */
-        uint32_t tx_bck_no_dly:1;
-        /** tx_left_align : R/W; bitpos: [15]; default: 1;
-         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-         */
-        uint32_t tx_left_align:1;
-        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
-         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-         */
-        uint32_t tx_24_fill_en:1;
-        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
-         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
-         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
-         */
-        uint32_t tx_ws_idle_pol:1;
-        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
-         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
-         *  sent first.
-         */
-        uint32_t tx_bit_order:1;
-        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
-         *  1: Enable I2S TDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_tdm_en:1;
-        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
-         *  1: Enable I2S PDM Tx mode . 0: Disable.
-         */
-        uint32_t tx_pdm_en:1;
-        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
-         *  Bit clock configuration bits in transmitter mode.
-         */
-        uint32_t tx_bck_div_num:6;
-        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
-         *  I2S transmitter channel mode configuration bits.
-         */
-        uint32_t tx_chan_mod:3;
-        /** sig_loopback : R/W; bitpos: [30]; default: 0;
-         *  Enable signal loop back mode with transmitter module and receiver module sharing
-         *  the same WS and BCK signals.
-         */
-        uint32_t sig_loopback:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} i2s_tx_conf_reg_t;
-
-/** Type of tx_conf1 register
- *  I2S TX configure register 1
- */
-typedef union {
-    struct {
-        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
-         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
-         *  T_bck
-         */
-        uint32_t tx_tdm_ws_width:9;
-        uint32_t reserved_9:5;
-        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
-         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
-         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
-         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
-         *  channel data is in 32-bit-mode.
-         */
-        uint32_t tx_bits_mod:5;
-        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
-         *  I2S Tx half sample bits -1.
-         */
-        uint32_t tx_half_sample_bits:8;
-        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
-         *  The Tx bit number for each channel minus 1in TDM mode.
-         */
-        uint32_t tx_tdm_chan_bits:5;
-    };
-    uint32_t val;
-} i2s_tx_conf1_reg_t;
-
-/** Type of tx_tdm_ctrl register
- *  I2S TX TDM mode control register
- */
-typedef union {
-    struct {
-        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan0_en:1;
-        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan1_en:1;
-        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan2_en:1;
-        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan3_en:1;
-        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan4_en:1;
-        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan5_en:1;
-        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan6_en:1;
-        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan7_en:1;
-        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan8_en:1;
-        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan9_en:1;
-        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan10_en:1;
-        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan11_en:1;
-        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan12_en:1;
-        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan13_en:1;
-        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan14_en:1;
-        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
-         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
-         *  0 in this channel.
-         */
-        uint32_t tx_tdm_chan15_en:1;
-        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
-         *  The total channel number of I2S TX TDM mode.
-         */
-        uint32_t tx_tdm_tot_chan_num:4;
-        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
-         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
-         *  only the data of the enabled channels is sent, then this bit should be set. Clear
-         *  it when all the data stored in DMA TX buffer is for enabled channels.
-         */
-        uint32_t tx_tdm_skip_msk_en:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} i2s_tx_tdm_ctrl_reg_t;
-
-
-/** Group: RX clock and timing registers */
-/** Type of rx_timing register
- *  I2S RX timing control register
- */
-typedef union {
-    struct {
-        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd_in_dm:2;
-        uint32_t reserved_2:2;
-        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
-         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd1_in_dm:2;
-        uint32_t reserved_6:2;
-        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
-         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd2_in_dm:2;
-        uint32_t reserved_10:2;
-        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
-         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_sd3_in_dm:2;
-        uint32_t reserved_14:2;
-        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t rx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_rx_timing_reg_t;
-
-
-/** Group: TX clock and timing registers */
-/** Type of tx_timing register
- *  I2S TX timing control register
- */
-typedef union {
-    struct {
-        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
-         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd_out_dm:2;
-        uint32_t reserved_2:2;
-        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
-         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_sd1_out_dm:2;
-        uint32_t reserved_6:10;
-        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
-         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_out_dm:2;
-        uint32_t reserved_18:2;
-        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
-         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_out_dm:2;
-        uint32_t reserved_22:2;
-        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
-         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_ws_in_dm:2;
-        uint32_t reserved_26:2;
-        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
-         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-         *  delay by neg edge. 3: not used.
-         */
-        uint32_t tx_bck_in_dm:2;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2s_tx_timing_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of lc_hung_conf register
- *  I2S HUNG configure register.
- */
-typedef union {
-    struct {
-        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
-         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
-         *  when fifo hung counter is equal to this value
-         */
-        uint32_t lc_fifo_timeout:8;
-        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
-         *  The bits are used to scale tick counter threshold. The tick counter is reset when
-         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-         */
-        uint32_t lc_fifo_timeout_shift:3;
-        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
-         *  The enable bit for FIFO timeout
-         */
-        uint32_t lc_fifo_timeout_ena:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} i2s_lc_hung_conf_reg_t;
-
-/** Type of conf_single_data register
- *  I2S signal data register
- */
-typedef union {
-    struct {
-        /** single_data : R/W; bitpos: [31:0]; default: 0;
-         *  The configured constant channel data to be sent out.
-         */
-        uint32_t single_data:32;
-    };
-    uint32_t val;
-} i2s_conf_single_data_reg_t;
-
-
-/** Group: TX status registers */
-/** Type of state register
- *  I2S TX status register
- */
-typedef union {
-    struct {
-        /** tx_idle : RO; bitpos: [0]; default: 1;
-         *  1: i2s_tx is idle state. 0: i2s_tx is working.
-         */
-        uint32_t tx_idle:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} i2s_state_reg_t;
-
-
-/** Group: ETM registers */
-/** Type of etm_conf register
- *  I2S ETM configure register
- */
-typedef union {
-    struct {
-        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
-         *  I2S ETM send x words event. When sending word number of
-         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_tx_send_word_num:10;
-        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
-         *  I2S ETM receive x words event. When receiving word number of
-         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
-         */
-        uint32_t etm_rx_receive_word_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} i2s_etm_conf_reg_t;
-
-
-/** Group: Sync counter registers */
-/** Type of fifo_cnt register
- *  I2S sync counter register
- */
-typedef union {
-    struct {
-        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
-         *  tx fifo counter value.
-         */
-        uint32_t tx_fifo_cnt:31;
-        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset tx fifo counter.
-         */
-        uint32_t tx_fifo_cnt_rst:1;
-    };
-    uint32_t val;
-} i2s_fifo_cnt_reg_t;
-
-/** Type of bck_cnt register
- *  I2S sync counter register
- */
-typedef union {
-    struct {
-        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
-         *  tx bck counter value.
-         */
-        uint32_t tx_bck_cnt:31;
-        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset tx bck counter.
-         */
-        uint32_t tx_bck_cnt_rst:1;
-    };
-    uint32_t val;
-} i2s_bck_cnt_reg_t;
-
-
-/** Group: Clock registers */
-/** Type of clk_gate register
- *  Clock gate register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  set this bit to enable clock gate
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} i2s_clk_gate_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 36713024;
-         *  I2S version control register
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} i2s_date_reg_t;
-
-
-typedef struct {
-    uint32_t reserved_000[3];
-    volatile i2s_int_raw_reg_t int_raw;
-    volatile i2s_int_st_reg_t int_st;
-    volatile i2s_int_ena_reg_t int_ena;
-    volatile i2s_int_clr_reg_t int_clr;
-    uint32_t reserved_01c;
-    volatile i2s_rx_conf_reg_t rx_conf;
-    volatile i2s_tx_conf_reg_t tx_conf;
-    volatile i2s_rx_conf1_reg_t rx_conf1;
-    volatile i2s_tx_conf1_reg_t tx_conf1;
-    uint32_t reserved_030[4];
-    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
-    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
-    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
-    uint32_t reserved_04c;
-    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
-    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
-    volatile i2s_rx_timing_reg_t rx_timing;
-    volatile i2s_tx_timing_reg_t tx_timing;
-    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
-    volatile i2s_rx_eof_num_reg_t rx_eof_num;
-    volatile i2s_conf_single_data_reg_t conf_single_data;
-    volatile i2s_state_reg_t state;
-    volatile i2s_etm_conf_reg_t etm_conf;
-    volatile i2s_fifo_cnt_reg_t fifo_cnt;
-    volatile i2s_bck_cnt_reg_t bck_cnt;
-    volatile i2s_clk_gate_reg_t clk_gate;
-    volatile i2s_date_reg_t date;
-} i2s_dev_t;
-
-extern i2s_dev_t I2S0;
-extern i2s_dev_t I2S1;
-extern i2s_dev_t I2S2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/io_mux_reg.h b/components/soc/esp32p4/include/soc/io_mux_reg.h
deleted file mode 100644
index 02440af9030..00000000000
--- a/components/soc/esp32p4/include/soc/io_mux_reg.h
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-#include "soc.h"
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Pin used for wakeup from sleep */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
-#define FILTER_EN (BIT(15))
-#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
-#define FILTER_EN_V 1
-#define FILTER_EN_S 15
-
-#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-
-#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
-
-#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_GPIO0
-#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_GPIO1
-#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_PAD_GPIO2
-#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_PAD_GPIO3
-#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_PAD_GPIO4
-#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_PAD_GPIO5
-#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_PAD_GPIO6
-#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_PAD_GPIO7
-#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_PAD_GPIO8
-#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_PAD_GPIO9
-#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_PAD_GPIO10
-#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_PAD_GPIO11
-#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_PAD_GPIO12
-#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_PAD_GPIO13
-#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_PAD_GPIO14
-#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_PAD_GPIO15
-#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_PAD_GPIO16
-#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_PAD_GPIO17
-#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_PAD_GPIO18
-#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_PAD_GPIO19
-#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_PAD_GPIO20
-#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_PAD_GPIO21
-#define IO_MUX_GPIO22_REG                   PERIPHS_IO_MUX_U_PAD_GPIO22
-#define IO_MUX_GPIO23_REG                   PERIPHS_IO_MUX_U_PAD_GPIO23
-#define IO_MUX_GPIO24_REG                   PERIPHS_IO_MUX_U_PAD_GPIO24
-#define IO_MUX_GPIO25_REG                   PERIPHS_IO_MUX_U_PAD_GPIO25
-#define IO_MUX_GPIO26_REG                   PERIPHS_IO_MUX_U_PAD_GPIO26
-#define IO_MUX_GPIO27_REG                   PERIPHS_IO_MUX_U_PAD_GPIO27
-#define IO_MUX_GPIO28_REG                   PERIPHS_IO_MUX_U_PAD_GPIO28
-#define IO_MUX_GPIO29_REG                   PERIPHS_IO_MUX_U_PAD_GPIO29
-#define IO_MUX_GPIO30_REG                   PERIPHS_IO_MUX_U_PAD_GPIO30
-#define IO_MUX_GPIO31_REG                   PERIPHS_IO_MUX_U_PAD_GPIO31
-#define IO_MUX_GPIO32_REG                   PERIPHS_IO_MUX_U_PAD_GPIO32
-#define IO_MUX_GPIO33_REG                   PERIPHS_IO_MUX_U_PAD_GPIO33
-#define IO_MUX_GPIO34_REG                   PERIPHS_IO_MUX_U_PAD_GPIO34
-#define IO_MUX_GPIO35_REG                   PERIPHS_IO_MUX_U_PAD_GPIO35
-#define IO_MUX_GPIO36_REG                   PERIPHS_IO_MUX_U_PAD_GPIO36
-#define IO_MUX_GPIO37_REG                   PERIPHS_IO_MUX_U_PAD_GPIO37
-#define IO_MUX_GPIO38_REG                   PERIPHS_IO_MUX_U_PAD_GPIO38
-#define IO_MUX_GPIO39_REG                   PERIPHS_IO_MUX_U_PAD_GPIO39
-#define IO_MUX_GPIO40_REG                   PERIPHS_IO_MUX_U_PAD_GPIO40
-#define IO_MUX_GPIO41_REG                   PERIPHS_IO_MUX_U_PAD_GPIO41
-#define IO_MUX_GPIO42_REG                   PERIPHS_IO_MUX_U_PAD_GPIO42
-#define IO_MUX_GPIO43_REG                   PERIPHS_IO_MUX_U_PAD_GPIO43
-#define IO_MUX_GPIO44_REG                   PERIPHS_IO_MUX_U_PAD_GPIO44
-#define IO_MUX_GPIO45_REG                   PERIPHS_IO_MUX_U_PAD_GPIO45
-#define IO_MUX_GPIO46_REG                   PERIPHS_IO_MUX_U_PAD_GPIO46
-#define IO_MUX_GPIO47_REG                   PERIPHS_IO_MUX_U_PAD_GPIO47
-#define IO_MUX_GPIO48_REG                   PERIPHS_IO_MUX_U_PAD_GPIO48
-#define IO_MUX_GPIO49_REG                   PERIPHS_IO_MUX_U_PAD_GPIO49
-#define IO_MUX_GPIO50_REG                   PERIPHS_IO_MUX_U_PAD_GPIO50
-#define IO_MUX_GPIO51_REG                   PERIPHS_IO_MUX_U_PAD_GPIO51
-#define IO_MUX_GPIO52_REG                   PERIPHS_IO_MUX_U_PAD_GPIO52
-#define IO_MUX_GPIO53_REG                   PERIPHS_IO_MUX_U_PAD_GPIO53
-#define IO_MUX_GPIO54_REG                   PERIPHS_IO_MUX_U_PAD_GPIO54
-
-#define PIN_FUNC_GPIO								1
-
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
-// TODO: IDF-7499, IDF-7495
-// SPI pins defined here are all wrong. On P4, these pins are individual pins, don't use normal GPIO pins anymore.
-// Please check iomux_mspi_pin_struct/reg.h
-#include "soc/gpio_num.h"
-#define SPI_CS1_GPIO_NUM GPIO_NUM_MAX
-#define SPI_HD_GPIO_NUM  GPIO_NUM_MAX
-#define SPI_WP_GPIO_NUM  GPIO_NUM_MAX
-#define SPI_CS0_GPIO_NUM GPIO_NUM_MAX
-#define SPI_CLK_GPIO_NUM GPIO_NUM_MAX
-#define SPI_Q_GPIO_NUM   GPIO_NUM_MAX
-#define SPI_D_GPIO_NUM   GPIO_NUM_MAX
-#define SPI_D4_GPIO_NUM  GPIO_NUM_MAX
-#define SPI_D5_GPIO_NUM  GPIO_NUM_MAX
-#define SPI_D6_GPIO_NUM  GPIO_NUM_MAX
-#define SPI_D7_GPIO_NUM  GPIO_NUM_MAX
-#define SPI_DQS_GPIO_NUM GPIO_NUM_MAX
-
-#define SD_CLK_GPIO_NUM           43
-#define SD_CMD_GPIO_NUM           44
-#define SD_DATA0_GPIO_NUM         39
-#define SD_DATA1_GPIO_NUM         40
-#define SD_DATA2_GPIO_NUM         41
-#define SD_DATA3_GPIO_NUM         42
-#define SD_DATA4_GPIO_NUM         45
-#define SD_DATA5_GPIO_NUM         46
-#define SD_DATA6_GPIO_NUM         47
-#define SD_DATA7_GPIO_NUM         48
-
-#define USB_INT_PHY0_DM_GPIO_NUM  24
-#define USB_INT_PHY0_DP_GPIO_NUM  25
-#define USB_INT_PHY1_DM_GPIO_NUM  26
-#define USB_INT_PHY1_DP_GPIO_NUM  27
-
-// We would fix the USB PHY usage on P4: PHY0 -> USJ, PHY1 -> USB_OTG
-#define USB_USJ_INT_PHY_DM_GPIO_NUM     USB_INT_PHY0_DM_GPIO_NUM
-#define USB_USJ_INT_PHY_DP_GPIO_NUM     USB_INT_PHY0_DP_GPIO_NUM
-#define USB_OTG_INT_PHY_DM_GPIO_NUM     USB_INT_PHY1_DM_GPIO_NUM
-#define USB_OTG_INT_PHY_DP_GPIO_NUM     USB_INT_PHY1_DP_GPIO_NUM
-
-#define EXT_OSC_SLOW_GPIO_NUM        0 // XTAL_32K_N
-
-#define MAX_RTC_GPIO_NUM             15
-#define MAX_PAD_GPIO_NUM             54
-#define MAX_GPIO_NUM                 56
-#define HIGH_IO_HOLD_BIT_SHIFT       32
-
-
-#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
-
-// definitions below are generated from pin_txt.csv
-#define PERIPHS_IO_MUX_U_PAD_GPIO0                 (REG_IO_MUX_BASE + 0x4)
-#define FUNC_GPIO0_GPIO0                                                 1
-#define FUNC_GPIO0_GPIO0_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO1                 (REG_IO_MUX_BASE + 0x8)
-#define FUNC_GPIO1_GPIO1                                                 1
-#define FUNC_GPIO1_GPIO1_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO2                 (REG_IO_MUX_BASE + 0xC)
-#define FUNC_GPIO2_GPIO2                                                 1
-#define FUNC_GPIO2_MTCK                                                  0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO3                (REG_IO_MUX_BASE + 0x10)
-#define FUNC_GPIO3_GPIO3                                                 1
-#define FUNC_GPIO3_MTDI                                                  0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO4                (REG_IO_MUX_BASE + 0x14)
-#define FUNC_GPIO4_GPIO4                                                 1
-#define FUNC_GPIO4_MTMS                                                  0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO5                (REG_IO_MUX_BASE + 0x18)
-#define FUNC_GPIO5_GPIO5                                                 1
-#define FUNC_GPIO5_MTDO                                                  0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO6                (REG_IO_MUX_BASE + 0x1C)
-#define FUNC_GPIO6_SPI2_HOLD_PAD                                         3
-#define FUNC_GPIO6_GPIO6                                                 1
-#define FUNC_GPIO6_GPIO6_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO7                (REG_IO_MUX_BASE + 0x20)
-#define FUNC_GPIO7_SPI2_CS_PAD                                           3
-#define FUNC_GPIO7_GPIO7                                                 1
-#define FUNC_GPIO7_GPIO7_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO8                (REG_IO_MUX_BASE + 0x24)
-#define FUNC_GPIO8_SPI2_D_PAD                                            3
-#define FUNC_GPIO8_UART0_RTS_PAD                                         2
-#define FUNC_GPIO8_GPIO8                                                 1
-#define FUNC_GPIO8_GPIO8_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO9                (REG_IO_MUX_BASE + 0x28)
-#define FUNC_GPIO9_SPI2_CK_PAD                                           3
-#define FUNC_GPIO9_UART0_CTS_PAD                                         2
-#define FUNC_GPIO9_GPIO9                                                 1
-#define FUNC_GPIO9_GPIO9_0                                               0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO10               (REG_IO_MUX_BASE + 0x2C)
-#define FUNC_GPIO10_SPI2_Q_PAD                                           3
-#define FUNC_GPIO10_UART1_TXD_PAD                                        2
-#define FUNC_GPIO10_GPIO10                                               1
-#define FUNC_GPIO10_GPIO10_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO11               (REG_IO_MUX_BASE + 0x30)
-#define FUNC_GPIO11_SPI2_WP_PAD                                          3
-#define FUNC_GPIO11_UART1_RXD_PAD                                        2
-#define FUNC_GPIO11_GPIO11                                               1
-#define FUNC_GPIO11_GPIO11_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO12               (REG_IO_MUX_BASE + 0x34)
-#define FUNC_GPIO12_UART1_RTS_PAD                                        2
-#define FUNC_GPIO12_GPIO12                                               1
-#define FUNC_GPIO12_GPIO12_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO13               (REG_IO_MUX_BASE + 0x38)
-#define FUNC_GPIO13_UART1_CTS_PAD                                        2
-#define FUNC_GPIO13_GPIO13                                               1
-#define FUNC_GPIO13_GPIO13_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO14               (REG_IO_MUX_BASE + 0x3C)
-#define FUNC_GPIO14_GPIO14                                               1
-#define FUNC_GPIO14_GPIO14_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO15               (REG_IO_MUX_BASE + 0x40)
-#define FUNC_GPIO15_GPIO15                                               1
-#define FUNC_GPIO15_GPIO15_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO16               (REG_IO_MUX_BASE + 0x44)
-#define FUNC_GPIO16_GPIO16                                               1
-#define FUNC_GPIO16_GPIO16_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO17               (REG_IO_MUX_BASE + 0x48)
-#define FUNC_GPIO17_GPIO17                                               1
-#define FUNC_GPIO17_GPIO17_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO18               (REG_IO_MUX_BASE + 0x4C)
-#define FUNC_GPIO18_GPIO18                                               1
-#define FUNC_GPIO18_GPIO18_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO19               (REG_IO_MUX_BASE + 0x50)
-#define FUNC_GPIO19_GPIO19                                               1
-#define FUNC_GPIO19_GPIO19_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO20               (REG_IO_MUX_BASE + 0x54)
-#define FUNC_GPIO20_GPIO20                                               1
-#define FUNC_GPIO20_GPIO20_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO21               (REG_IO_MUX_BASE + 0x58)
-#define FUNC_GPIO21_GPIO21                                               1
-#define FUNC_GPIO21_GPIO21_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO22               (REG_IO_MUX_BASE + 0x5C)
-#define FUNC_GPIO22_DBG_PSRAM_CK_PAD                                     4
-#define FUNC_GPIO22_GPIO22                                               1
-#define FUNC_GPIO22_GPIO22_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO23               (REG_IO_MUX_BASE + 0x60)
-#define FUNC_GPIO23_DBG_PSRAM_CS_PAD                                     4
-#define FUNC_GPIO23_REF_50M_CLK_PAD                                      3
-#define FUNC_GPIO23_GPIO23                                               1
-#define FUNC_GPIO23_GPIO23_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO24               (REG_IO_MUX_BASE + 0x64)
-#define FUNC_GPIO24_GPIO24                                               1
-#define FUNC_GPIO24_GPIO24_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO25               (REG_IO_MUX_BASE + 0x68)
-#define FUNC_GPIO25_GPIO25                                               1
-#define FUNC_GPIO25_GPIO25_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO26               (REG_IO_MUX_BASE + 0x6C)
-#define FUNC_GPIO26_GPIO26                                               1
-#define FUNC_GPIO26_GPIO26_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO27               (REG_IO_MUX_BASE + 0x70)
-#define FUNC_GPIO27_GPIO27                                               1
-#define FUNC_GPIO27_GPIO27_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO28               (REG_IO_MUX_BASE + 0x74)
-#define FUNC_GPIO28_DBG_PSRAM_D_PAD                                      4
-#define FUNC_GPIO28_EMAC_PHY_RXDV_PAD                                    3
-#define FUNC_GPIO28_SPI2_CS_PAD                                          2
-#define FUNC_GPIO28_GPIO28                                               1
-#define FUNC_GPIO28_GPIO28_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO29               (REG_IO_MUX_BASE + 0x78)
-#define FUNC_GPIO29_DBG_PSRAM_Q_PAD                                      4
-#define FUNC_GPIO29_EMAC_PHY_RXD0_PAD                                    3
-#define FUNC_GPIO29_SPI2_D_PAD                                           2
-#define FUNC_GPIO29_GPIO29                                               1
-#define FUNC_GPIO29_GPIO29_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO30               (REG_IO_MUX_BASE + 0x7C)
-#define FUNC_GPIO30_DBG_PSRAM_WP_PAD                                     4
-#define FUNC_GPIO30_EMAC_PHY_RXD1_PAD                                    3
-#define FUNC_GPIO30_SPI2_CK_PAD                                          2
-#define FUNC_GPIO30_GPIO30                                               1
-#define FUNC_GPIO30_GPIO30_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO31               (REG_IO_MUX_BASE + 0x80)
-#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD                                   4
-#define FUNC_GPIO31_EMAC_PHY_RXER_PAD                                    3
-#define FUNC_GPIO31_SPI2_Q_PAD                                           2
-#define FUNC_GPIO31_GPIO31                                               1
-#define FUNC_GPIO31_GPIO31_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO32               (REG_IO_MUX_BASE + 0x84)
-#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD                                    4
-#define FUNC_GPIO32_EMAC_RMII_CLK_PAD                                    3
-#define FUNC_GPIO32_SPI2_HOLD_PAD                                        2
-#define FUNC_GPIO32_GPIO32                                               1
-#define FUNC_GPIO32_GPIO32_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO33               (REG_IO_MUX_BASE + 0x88)
-#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD                                    4
-#define FUNC_GPIO33_EMAC_PHY_TXEN_PAD                                    3
-#define FUNC_GPIO33_SPI2_WP_PAD                                          2
-#define FUNC_GPIO33_GPIO33                                               1
-#define FUNC_GPIO33_GPIO33_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO34               (REG_IO_MUX_BASE + 0x8C)
-#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD                                    4
-#define FUNC_GPIO34_EMAC_PHY_TXD0_PAD                                    3
-#define FUNC_GPIO34_SPI2_IO4_PAD                                         2
-#define FUNC_GPIO34_GPIO34                                               1
-#define FUNC_GPIO34_GPIO34_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO35               (REG_IO_MUX_BASE + 0x90)
-#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD                                    4
-#define FUNC_GPIO35_EMAC_PHY_TXD1_PAD                                    3
-#define FUNC_GPIO35_SPI2_IO5_PAD                                         2
-#define FUNC_GPIO35_GPIO35                                               1
-#define FUNC_GPIO35_GPIO35_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO36               (REG_IO_MUX_BASE + 0x94)
-#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD                                  4
-#define FUNC_GPIO36_EMAC_PHY_TXER_PAD                                    3
-#define FUNC_GPIO36_SPI2_IO6_PAD                                         2
-#define FUNC_GPIO36_GPIO36                                               1
-#define FUNC_GPIO36_GPIO36_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO37               (REG_IO_MUX_BASE + 0x98)
-#define FUNC_GPIO37_SPI2_IO7_PAD                                         2
-#define FUNC_GPIO37_GPIO37                                               1
-#define FUNC_GPIO37_UART0_TXD_PAD                                        0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO38               (REG_IO_MUX_BASE + 0x9C)
-#define FUNC_GPIO38_SPI2_DQS_PAD                                         2
-#define FUNC_GPIO38_GPIO38                                               1
-#define FUNC_GPIO38_UART0_RXD_PAD                                        0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO39               (REG_IO_MUX_BASE + 0xA0)
-#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD                                    4
-#define FUNC_GPIO39_REF_50M_CLK_PAD                                      3
-#define FUNC_GPIO39_BIST_PAD                                             2
-#define FUNC_GPIO39_GPIO39                                               1
-#define FUNC_GPIO39_SD1_CDATA0_PAD                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO40               (REG_IO_MUX_BASE + 0xA4)
-#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD                                    4
-#define FUNC_GPIO40_EMAC_PHY_TXEN_PAD                                    3
-#define FUNC_GPIO40_BIST_PAD                                             2
-#define FUNC_GPIO40_GPIO40                                               1
-#define FUNC_GPIO40_SD1_CDATA1_PAD                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO41               (REG_IO_MUX_BASE + 0xA8)
-#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD                                   4
-#define FUNC_GPIO41_EMAC_PHY_TXD0_PAD                                    3
-#define FUNC_GPIO41_BIST_PAD                                             2
-#define FUNC_GPIO41_GPIO41                                               1
-#define FUNC_GPIO41_SD1_CDATA2_PAD                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO42               (REG_IO_MUX_BASE + 0xAC)
-#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD                                   4
-#define FUNC_GPIO42_EMAC_PHY_TXD1_PAD                                    3
-#define FUNC_GPIO42_BIST_PAD                                             2
-#define FUNC_GPIO42_GPIO42                                               1
-#define FUNC_GPIO42_SD1_CDATA3_PAD                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO43               (REG_IO_MUX_BASE + 0xB0)
-#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD                                   4
-#define FUNC_GPIO43_EMAC_PHY_TXER_PAD                                    3
-#define FUNC_GPIO43_BIST_PAD                                             2
-#define FUNC_GPIO43_GPIO43                                               1
-#define FUNC_GPIO43_SD1_CCLK_PAD                                         0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO44               (REG_IO_MUX_BASE + 0xB4)
-#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD                                   4
-#define FUNC_GPIO44_EMAC_RMII_CLK_PAD                                    3
-#define FUNC_GPIO44_BIST_PAD                                             2
-#define FUNC_GPIO44_GPIO44                                               1
-#define FUNC_GPIO44_SD1_CCMD_PAD                                         0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO45               (REG_IO_MUX_BASE + 0xB8)
-#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD                                   4
-#define FUNC_GPIO45_EMAC_PHY_RXDV_PAD                                    3
-#define FUNC_GPIO45_BIST_PAD                                             2
-#define FUNC_GPIO45_GPIO45                                               1
-#define FUNC_GPIO45_SD1_CDATA4_PAD                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO46               (REG_IO_MUX_BASE + 0xBC)
-#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD                                   4
-#define FUNC_GPIO46_EMAC_PHY_RXD0_PAD                                    3
-#define FUNC_GPIO46_BIST_PAD                                             2
-#define FUNC_GPIO46_GPIO46                                               1
-#define FUNC_GPIO46_SD1_CDATA5_PAD                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO47               (REG_IO_MUX_BASE + 0xC0)
-#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD                                  4
-#define FUNC_GPIO47_EMAC_PHY_RXD1_PAD                                    3
-#define FUNC_GPIO47_BIST_PAD                                             2
-#define FUNC_GPIO47_GPIO47                                               1
-#define FUNC_GPIO47_SD1_CDATA6_PAD                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO48               (REG_IO_MUX_BASE + 0xC4)
-#define FUNC_GPIO48_EMAC_PHY_RXER_PAD                                    3
-#define FUNC_GPIO48_BIST_PAD                                             2
-#define FUNC_GPIO48_GPIO48                                               1
-#define FUNC_GPIO48_SD1_CDATA7_PAD                                       0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO49               (REG_IO_MUX_BASE + 0xC8)
-#define FUNC_GPIO49_DBG_FLASH_CS_PAD                                      4
-#define FUNC_GPIO49_EMAC_PHY_TXEN_PAD                                    3
-#define FUNC_GPIO49_GPIO49                                               1
-#define FUNC_GPIO49_GPIO49_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO50               (REG_IO_MUX_BASE + 0xCC)
-#define FUNC_GPIO50_DBG_FLASH_Q_PAD                                       4
-#define FUNC_GPIO50_EMAC_RMII_CLK_PAD                                    3
-#define FUNC_GPIO50_GPIO50                                               1
-#define FUNC_GPIO50_GPIO50_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO51               (REG_IO_MUX_BASE + 0xD0)
-#define FUNC_GPIO51_DBG_FLASH_WP_PAD                                     4
-#define FUNC_GPIO51_EMAC_PHY_RXDV_PAD                                    3
-#define FUNC_GPIO51_GPIO51                                               1
-#define FUNC_GPIO51_GPIO51_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO52               (REG_IO_MUX_BASE + 0xD4)
-#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD                                   4
-#define FUNC_GPIO52_EMAC_PHY_RXD0_PAD                                    3
-#define FUNC_GPIO52_GPIO52                                               1
-#define FUNC_GPIO52_GPIO52_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO53               (REG_IO_MUX_BASE + 0xD8)
-#define FUNC_GPIO53_DBG_FLASH_CK_PAD                                      4
-#define FUNC_GPIO53_EMAC_PHY_RXD1_PAD                                    3
-#define FUNC_GPIO53_GPIO53                                               1
-#define FUNC_GPIO53_GPIO53_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO54               (REG_IO_MUX_BASE + 0xDC)
-#define FUNC_GPIO54_DBG_FLASH_D_PAD                                       4
-#define FUNC_GPIO54_EMAC_PHY_RXER_PAD                                    3
-#define FUNC_GPIO54_GPIO54                                               1
-#define FUNC_GPIO54_GPIO54_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO55               (REG_IO_MUX_BASE + 0xE0)
-#define FUNC_GPIO55_GPIO55                                               1
-#define FUNC_GPIO55_GPIO55_0                                             0
-
-#define PERIPHS_IO_MUX_U_PAD_GPIO56               (REG_IO_MUX_BASE + 0xE4)
-#define FUNC_GPIO56_GPIO56                                               1
-#define FUNC_GPIO56_GPIO56_0                                             0
-
-#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0x104)
-/* IO_MUX_DATE : R/W ;bitpos:[27:0] ;default: 27'h0201222 ; */
-/*description: csv date.*/
-#define IO_MUX_DATE    0x0FFFFFFF
-#define IO_MUX_DATE_M  ((IO_MUX_DATE_V)<<(IO_MUX_DATE_S))
-#define IO_MUX_DATE_V  0xFFFFFFF
-#define IO_MUX_DATE_S  0
diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h b/components/soc/esp32p4/include/soc/lp_clkrst_reg.h
deleted file mode 100644
index de3f17820c1..00000000000
--- a/components/soc/esp32p4/include/soc/lp_clkrst_reg.h
+++ /dev/null
@@ -1,1036 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_CLKRST_LP_CLK_CONF_REG register
- *  need_des
- */
-#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
-/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_SLOW_CLK_SEL    0x00000003U
-#define LP_CLKRST_SLOW_CLK_SEL_M  (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
-#define LP_CLKRST_SLOW_CLK_SEL_V  0x00000003U
-#define LP_CLKRST_SLOW_CLK_SEL_S  0
-/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_FAST_CLK_SEL    0x00000003U
-#define LP_CLKRST_FAST_CLK_SEL_M  (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
-#define LP_CLKRST_FAST_CLK_SEL_V  0x00000003U
-#define LP_CLKRST_FAST_CLK_SEL_S  2
-/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LP_PERI_DIV_NUM    0x0000003FU
-#define LP_CLKRST_LP_PERI_DIV_NUM_M  (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
-#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x0000003FU
-#define LP_CLKRST_LP_PERI_DIV_NUM_S  4
-/** LP_CLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_ANA_SEL_REF_PLL8M    (BIT(10))
-#define LP_CLKRST_ANA_SEL_REF_PLL8M_M  (LP_CLKRST_ANA_SEL_REF_PLL8M_V << LP_CLKRST_ANA_SEL_REF_PLL8M_S)
-#define LP_CLKRST_ANA_SEL_REF_PLL8M_V  0x00000001U
-#define LP_CLKRST_ANA_SEL_REF_PLL8M_S  10
-
-/** LP_CLKRST_LP_CLK_PO_EN_REG register
- *  need_des
- */
-#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
-/** LP_CLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_CORE_EFUSE_OEN    (BIT(0))
-#define LP_CLKRST_CLK_CORE_EFUSE_OEN_M  (LP_CLKRST_CLK_CORE_EFUSE_OEN_V << LP_CLKRST_CLK_CORE_EFUSE_OEN_S)
-#define LP_CLKRST_CLK_CORE_EFUSE_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_CORE_EFUSE_OEN_S  0
-/** LP_CLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_LP_BUS_OEN    (BIT(1))
-#define LP_CLKRST_CLK_LP_BUS_OEN_M  (LP_CLKRST_CLK_LP_BUS_OEN_V << LP_CLKRST_CLK_LP_BUS_OEN_S)
-#define LP_CLKRST_CLK_LP_BUS_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_LP_BUS_OEN_S  1
-/** LP_CLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_AON_SLOW_OEN    (BIT(2))
-#define LP_CLKRST_CLK_AON_SLOW_OEN_M  (LP_CLKRST_CLK_AON_SLOW_OEN_V << LP_CLKRST_CLK_AON_SLOW_OEN_S)
-#define LP_CLKRST_CLK_AON_SLOW_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_AON_SLOW_OEN_S  2
-/** LP_CLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_AON_FAST_OEN    (BIT(3))
-#define LP_CLKRST_CLK_AON_FAST_OEN_M  (LP_CLKRST_CLK_AON_FAST_OEN_V << LP_CLKRST_CLK_AON_FAST_OEN_S)
-#define LP_CLKRST_CLK_AON_FAST_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_AON_FAST_OEN_S  3
-/** LP_CLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_SLOW_OEN    (BIT(4))
-#define LP_CLKRST_CLK_SLOW_OEN_M  (LP_CLKRST_CLK_SLOW_OEN_V << LP_CLKRST_CLK_SLOW_OEN_S)
-#define LP_CLKRST_CLK_SLOW_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_SLOW_OEN_S  4
-/** LP_CLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_FAST_OEN    (BIT(5))
-#define LP_CLKRST_CLK_FAST_OEN_M  (LP_CLKRST_CLK_FAST_OEN_V << LP_CLKRST_CLK_FAST_OEN_S)
-#define LP_CLKRST_CLK_FAST_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_FAST_OEN_S  5
-/** LP_CLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_FOSC_OEN    (BIT(6))
-#define LP_CLKRST_CLK_FOSC_OEN_M  (LP_CLKRST_CLK_FOSC_OEN_V << LP_CLKRST_CLK_FOSC_OEN_S)
-#define LP_CLKRST_CLK_FOSC_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_FOSC_OEN_S  6
-/** LP_CLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_RC32K_OEN    (BIT(7))
-#define LP_CLKRST_CLK_RC32K_OEN_M  (LP_CLKRST_CLK_RC32K_OEN_V << LP_CLKRST_CLK_RC32K_OEN_S)
-#define LP_CLKRST_CLK_RC32K_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_RC32K_OEN_S  7
-/** LP_CLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_SXTAL_OEN    (BIT(8))
-#define LP_CLKRST_CLK_SXTAL_OEN_M  (LP_CLKRST_CLK_SXTAL_OEN_V << LP_CLKRST_CLK_SXTAL_OEN_S)
-#define LP_CLKRST_CLK_SXTAL_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_SXTAL_OEN_S  8
-/** LP_CLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0;
- *  1'b1: probe sosc clk on
- *  1'b0: probe sosc clk off
- */
-#define LP_CLKRST_CLK_SOSC_OEN    (BIT(9))
-#define LP_CLKRST_CLK_SOSC_OEN_M  (LP_CLKRST_CLK_SOSC_OEN_V << LP_CLKRST_CLK_SOSC_OEN_S)
-#define LP_CLKRST_CLK_SOSC_OEN_V  0x00000001U
-#define LP_CLKRST_CLK_SOSC_OEN_S  9
-
-/** LP_CLKRST_LP_CLK_EN_REG register
- *  need_des
- */
-#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
-/** LP_CLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON    (BIT(26))
-#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_M  (LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S)
-#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V  0x00000001U
-#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S  26
-/** LP_CLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_CK_EN_LP_RAM    (BIT(27))
-#define LP_CLKRST_CK_EN_LP_RAM_M  (LP_CLKRST_CK_EN_LP_RAM_V << LP_CLKRST_CK_EN_LP_RAM_S)
-#define LP_CLKRST_CK_EN_LP_RAM_V  0x00000001U
-#define LP_CLKRST_CK_EN_LP_RAM_S  27
-/** LP_CLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_ETM_EVENT_TICK_EN    (BIT(28))
-#define LP_CLKRST_ETM_EVENT_TICK_EN_M  (LP_CLKRST_ETM_EVENT_TICK_EN_V << LP_CLKRST_ETM_EVENT_TICK_EN_S)
-#define LP_CLKRST_ETM_EVENT_TICK_EN_V  0x00000001U
-#define LP_CLKRST_ETM_EVENT_TICK_EN_S  28
-/** LP_CLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_PLL8M_CLK_FORCE_ON    (BIT(29))
-#define LP_CLKRST_PLL8M_CLK_FORCE_ON_M  (LP_CLKRST_PLL8M_CLK_FORCE_ON_V << LP_CLKRST_PLL8M_CLK_FORCE_ON_S)
-#define LP_CLKRST_PLL8M_CLK_FORCE_ON_V  0x00000001U
-#define LP_CLKRST_PLL8M_CLK_FORCE_ON_S  29
-/** LP_CLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_XTAL_CLK_FORCE_ON    (BIT(30))
-#define LP_CLKRST_XTAL_CLK_FORCE_ON_M  (LP_CLKRST_XTAL_CLK_FORCE_ON_V << LP_CLKRST_XTAL_CLK_FORCE_ON_S)
-#define LP_CLKRST_XTAL_CLK_FORCE_ON_V  0x00000001U
-#define LP_CLKRST_XTAL_CLK_FORCE_ON_S  30
-/** LP_CLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_FOSC_CLK_FORCE_ON    (BIT(31))
-#define LP_CLKRST_FOSC_CLK_FORCE_ON_M  (LP_CLKRST_FOSC_CLK_FORCE_ON_V << LP_CLKRST_FOSC_CLK_FORCE_ON_S)
-#define LP_CLKRST_FOSC_CLK_FORCE_ON_V  0x00000001U
-#define LP_CLKRST_FOSC_CLK_FORCE_ON_S  31
-
-/** LP_CLKRST_LP_RST_EN_REG register
- *  need_des
- */
-#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
-/** LP_CLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RST_EN_LP_HUK    (BIT(24))
-#define LP_CLKRST_RST_EN_LP_HUK_M  (LP_CLKRST_RST_EN_LP_HUK_V << LP_CLKRST_RST_EN_LP_HUK_S)
-#define LP_CLKRST_RST_EN_LP_HUK_V  0x00000001U
-#define LP_CLKRST_RST_EN_LP_HUK_S  24
-/** LP_CLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RST_EN_LP_ANAPERI    (BIT(25))
-#define LP_CLKRST_RST_EN_LP_ANAPERI_M  (LP_CLKRST_RST_EN_LP_ANAPERI_V << LP_CLKRST_RST_EN_LP_ANAPERI_S)
-#define LP_CLKRST_RST_EN_LP_ANAPERI_V  0x00000001U
-#define LP_CLKRST_RST_EN_LP_ANAPERI_S  25
-/** LP_CLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RST_EN_LP_WDT    (BIT(26))
-#define LP_CLKRST_RST_EN_LP_WDT_M  (LP_CLKRST_RST_EN_LP_WDT_V << LP_CLKRST_RST_EN_LP_WDT_S)
-#define LP_CLKRST_RST_EN_LP_WDT_V  0x00000001U
-#define LP_CLKRST_RST_EN_LP_WDT_S  26
-/** LP_CLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RST_EN_LP_TIMER    (BIT(27))
-#define LP_CLKRST_RST_EN_LP_TIMER_M  (LP_CLKRST_RST_EN_LP_TIMER_V << LP_CLKRST_RST_EN_LP_TIMER_S)
-#define LP_CLKRST_RST_EN_LP_TIMER_V  0x00000001U
-#define LP_CLKRST_RST_EN_LP_TIMER_S  27
-/** LP_CLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RST_EN_LP_RTC    (BIT(28))
-#define LP_CLKRST_RST_EN_LP_RTC_M  (LP_CLKRST_RST_EN_LP_RTC_V << LP_CLKRST_RST_EN_LP_RTC_S)
-#define LP_CLKRST_RST_EN_LP_RTC_V  0x00000001U
-#define LP_CLKRST_RST_EN_LP_RTC_S  28
-/** LP_CLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RST_EN_LP_MAILBOX    (BIT(29))
-#define LP_CLKRST_RST_EN_LP_MAILBOX_M  (LP_CLKRST_RST_EN_LP_MAILBOX_V << LP_CLKRST_RST_EN_LP_MAILBOX_S)
-#define LP_CLKRST_RST_EN_LP_MAILBOX_V  0x00000001U
-#define LP_CLKRST_RST_EN_LP_MAILBOX_S  29
-/** LP_CLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RST_EN_LP_AONEFUSEREG    (BIT(30))
-#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_M  (LP_CLKRST_RST_EN_LP_AONEFUSEREG_V << LP_CLKRST_RST_EN_LP_AONEFUSEREG_S)
-#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_V  0x00000001U
-#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_S  30
-/** LP_CLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_RST_EN_LP_RAM    (BIT(31))
-#define LP_CLKRST_RST_EN_LP_RAM_M  (LP_CLKRST_RST_EN_LP_RAM_V << LP_CLKRST_RST_EN_LP_RAM_S)
-#define LP_CLKRST_RST_EN_LP_RAM_V  0x00000001U
-#define LP_CLKRST_RST_EN_LP_RAM_S  31
-
-/** LP_CLKRST_RESET_CAUSE_REG register
- *  need_des
- */
-#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
-/** LP_CLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0;
- *  6'h1: POR reset
- *  6'h9: PMU LP PERI power down reset
- *  6'ha: PMU LP CPU reset
- *  6'hf: brown out reset
- *  6'h10: LP watchdog chip reset
- *  6'h12: super watch dog reset
- *  6'h13: glitch reset
- *  6'h14: software reset
- */
-#define LP_CLKRST_LPCORE_RESET_CAUSE    0x0000003FU
-#define LP_CLKRST_LPCORE_RESET_CAUSE_M  (LP_CLKRST_LPCORE_RESET_CAUSE_V << LP_CLKRST_LPCORE_RESET_CAUSE_S)
-#define LP_CLKRST_LPCORE_RESET_CAUSE_V  0x0000003FU
-#define LP_CLKRST_LPCORE_RESET_CAUSE_S  0
-/** LP_CLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LPCORE_RESET_FLAG    (BIT(6))
-#define LP_CLKRST_LPCORE_RESET_FLAG_M  (LP_CLKRST_LPCORE_RESET_FLAG_V << LP_CLKRST_LPCORE_RESET_FLAG_S)
-#define LP_CLKRST_LPCORE_RESET_FLAG_V  0x00000001U
-#define LP_CLKRST_LPCORE_RESET_FLAG_S  6
-/** LP_CLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0;
- *  6'h1: POR reset
- *  6'h3: digital system software reset
- *  6'h5: PMU HP system power down reset
- *  6'h7: HP system reset from HP watchdog
- *  6'h9: HP system reset from LP watchdog
- *  6'hb: HP core reset from HP watchdog
- *  6'hc: HP core software reset
- *  6'hd: HP core reset from LP watchdog
- *  6'hf: brown out reset
- *  6'h10: LP watchdog chip reset
- *  6'h12: super watch dog reset
- *  6'h13: glitch reset
- *  6'h14: efuse crc error reset
- *  6'h16: HP usb jtag chip reset
- *  6'h17: HP usb uart chip reset
- *  6'h18: HP jtag reset
- *  6'h1a: HP core lockup
- */
-#define LP_CLKRST_HPCORE0_RESET_CAUSE    0x0000003FU
-#define LP_CLKRST_HPCORE0_RESET_CAUSE_M  (LP_CLKRST_HPCORE0_RESET_CAUSE_V << LP_CLKRST_HPCORE0_RESET_CAUSE_S)
-#define LP_CLKRST_HPCORE0_RESET_CAUSE_V  0x0000003FU
-#define LP_CLKRST_HPCORE0_RESET_CAUSE_S  7
-/** LP_CLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE0_RESET_FLAG    (BIT(13))
-#define LP_CLKRST_HPCORE0_RESET_FLAG_M  (LP_CLKRST_HPCORE0_RESET_FLAG_V << LP_CLKRST_HPCORE0_RESET_FLAG_S)
-#define LP_CLKRST_HPCORE0_RESET_FLAG_V  0x00000001U
-#define LP_CLKRST_HPCORE0_RESET_FLAG_S  13
-/** LP_CLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0;
- *  6'h1: POR reset
- *  6'h3: digital system software reset
- *  6'h5: PMU HP system power down reset
- *  6'h7: HP system reset from HP watchdog
- *  6'h9: HP system reset from LP watchdog
- *  6'hb: HP core reset from HP watchdog
- *  6'hc: HP core software reset
- *  6'hd: HP core reset from LP watchdog
- *  6'hf: brown out reset
- *  6'h10: LP watchdog chip reset
- *  6'h12: super watch dog reset
- *  6'h13: glitch reset
- *  6'h14: efuse crc error reset
- *  6'h16: HP usb jtag chip reset
- *  6'h17: HP usb uart chip reset
- *  6'h18: HP jtag reset
- *  6'h1a: HP core lockup
- */
-#define LP_CLKRST_HPCORE1_RESET_CAUSE    0x0000003FU
-#define LP_CLKRST_HPCORE1_RESET_CAUSE_M  (LP_CLKRST_HPCORE1_RESET_CAUSE_V << LP_CLKRST_HPCORE1_RESET_CAUSE_S)
-#define LP_CLKRST_HPCORE1_RESET_CAUSE_V  0x0000003FU
-#define LP_CLKRST_HPCORE1_RESET_CAUSE_S  14
-/** LP_CLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE1_RESET_FLAG    (BIT(20))
-#define LP_CLKRST_HPCORE1_RESET_FLAG_M  (LP_CLKRST_HPCORE1_RESET_FLAG_V << LP_CLKRST_HPCORE1_RESET_FLAG_S)
-#define LP_CLKRST_HPCORE1_RESET_FLAG_V  0x00000001U
-#define LP_CLKRST_HPCORE1_RESET_FLAG_S  20
-/** LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1;
- *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
- *  pmu_lp_cpu_reset reset_cause
- */
-#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK    (BIT(25))
-#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M  (LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S)
-#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V  0x00000001U
-#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S  25
-/** LP_CLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR    (BIT(26))
-#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_M  (LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S)
-#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S  26
-/** LP_CLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_LPCORE_RESET_FLAG_CLR    (BIT(27))
-#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_M  (LP_CLKRST_LPCORE_RESET_FLAG_CLR_V << LP_CLKRST_LPCORE_RESET_FLAG_CLR_S)
-#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_V  0x00000001U
-#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_S  27
-/** LP_CLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR    (BIT(28))
-#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S)
-#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S  28
-/** LP_CLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR    (BIT(29))
-#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_M  (LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S)
-#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V  0x00000001U
-#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S  29
-/** LP_CLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR    (BIT(30))
-#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_M  (LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S)
-#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V  0x00000001U
-#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S  30
-/** LP_CLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR    (BIT(31))
-#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_M  (LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S)
-#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V  0x00000001U
-#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S  31
-
-/** LP_CLKRST_HPCPU_RESET_CTRL0_REG register
- *  need_des
- */
-#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14)
-/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0;
- *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
- *  reset feature
- */
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(0))
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
-#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S  0
-/** LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH    0x00000007U
-#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M  (LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S)
-#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V  0x00000007U
-#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S  1
-/** LP_CLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0;
- *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
- *  hpcore0 feature
- */
-#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN    (BIT(4))
-#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_M  (LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S)
-#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V  0x00000001U
-#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S  4
-/** LP_CLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE0_STALL_WAIT    0x0000007FU
-#define LP_CLKRST_HPCORE0_STALL_WAIT_M  (LP_CLKRST_HPCORE0_STALL_WAIT_V << LP_CLKRST_HPCORE0_STALL_WAIT_S)
-#define LP_CLKRST_HPCORE0_STALL_WAIT_V  0x0000007FU
-#define LP_CLKRST_HPCORE0_STALL_WAIT_S  5
-/** LP_CLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE0_STALL_EN    (BIT(12))
-#define LP_CLKRST_HPCORE0_STALL_EN_M  (LP_CLKRST_HPCORE0_STALL_EN_V << LP_CLKRST_HPCORE0_STALL_EN_S)
-#define LP_CLKRST_HPCORE0_STALL_EN_V  0x00000001U
-#define LP_CLKRST_HPCORE0_STALL_EN_S  12
-/** LP_CLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE0_SW_RESET    (BIT(13))
-#define LP_CLKRST_HPCORE0_SW_RESET_M  (LP_CLKRST_HPCORE0_SW_RESET_V << LP_CLKRST_HPCORE0_SW_RESET_S)
-#define LP_CLKRST_HPCORE0_SW_RESET_V  0x00000001U
-#define LP_CLKRST_HPCORE0_SW_RESET_S  13
-/** LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET    (BIT(14))
-#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_M  (LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S)
-#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V  0x00000001U
-#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S  14
-/** LP_CLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1;
- *  1'b1: boot from HP TCM ROM: 0x4FC00000
- *  1'b0: boot from LP TCM RAM:  0x50108000
- */
-#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL    (BIT(15))
-#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_M  (LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S)
-#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V  0x00000001U
-#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S  15
-/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0;
- *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
- *  reset feature
- */
-#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN    (BIT(16))
-#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S)
-#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V  0x00000001U
-#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S  16
-/** LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1;
- *  need_des
- */
-#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH    0x00000007U
-#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M  (LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S)
-#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V  0x00000007U
-#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S  17
-/** LP_CLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0;
- *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
- *  hpcore1 feature
- */
-#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN    (BIT(20))
-#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_M  (LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S)
-#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V  0x00000001U
-#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S  20
-/** LP_CLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE1_STALL_WAIT    0x0000007FU
-#define LP_CLKRST_HPCORE1_STALL_WAIT_M  (LP_CLKRST_HPCORE1_STALL_WAIT_V << LP_CLKRST_HPCORE1_STALL_WAIT_S)
-#define LP_CLKRST_HPCORE1_STALL_WAIT_V  0x0000007FU
-#define LP_CLKRST_HPCORE1_STALL_WAIT_S  21
-/** LP_CLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE1_STALL_EN    (BIT(28))
-#define LP_CLKRST_HPCORE1_STALL_EN_M  (LP_CLKRST_HPCORE1_STALL_EN_V << LP_CLKRST_HPCORE1_STALL_EN_S)
-#define LP_CLKRST_HPCORE1_STALL_EN_V  0x00000001U
-#define LP_CLKRST_HPCORE1_STALL_EN_S  28
-/** LP_CLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE1_SW_RESET    (BIT(29))
-#define LP_CLKRST_HPCORE1_SW_RESET_M  (LP_CLKRST_HPCORE1_SW_RESET_V << LP_CLKRST_HPCORE1_SW_RESET_S)
-#define LP_CLKRST_HPCORE1_SW_RESET_V  0x00000001U
-#define LP_CLKRST_HPCORE1_SW_RESET_S  29
-/** LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET    (BIT(30))
-#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_M  (LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S)
-#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V  0x00000001U
-#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S  30
-/** LP_CLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1;
- *  1'b1: boot from HP TCM ROM: 0x4FC00000
- *  1'b0: boot from LP TCM RAM:  0x50108000
- */
-#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL    (BIT(31))
-#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_M  (LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S)
-#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V  0x00000001U
-#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S  31
-
-/** LP_CLKRST_HPCPU_RESET_CTRL1_REG register
- *  need_des
- */
-#define LP_CLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x18)
-/** LP_CLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0;
- *  HP core0 software stall when set to 8'h86
- */
-#define LP_CLKRST_HPCORE0_SW_STALL_CODE    0x000000FFU
-#define LP_CLKRST_HPCORE0_SW_STALL_CODE_M  (LP_CLKRST_HPCORE0_SW_STALL_CODE_V << LP_CLKRST_HPCORE0_SW_STALL_CODE_S)
-#define LP_CLKRST_HPCORE0_SW_STALL_CODE_V  0x000000FFU
-#define LP_CLKRST_HPCORE0_SW_STALL_CODE_S  16
-/** LP_CLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0;
- *  HP core1 software stall when set to 8'h86
- */
-#define LP_CLKRST_HPCORE1_SW_STALL_CODE    0x000000FFU
-#define LP_CLKRST_HPCORE1_SW_STALL_CODE_M  (LP_CLKRST_HPCORE1_SW_STALL_CODE_V << LP_CLKRST_HPCORE1_SW_STALL_CODE_S)
-#define LP_CLKRST_HPCORE1_SW_STALL_CODE_V  0x000000FFU
-#define LP_CLKRST_HPCORE1_SW_STALL_CODE_S  24
-
-/** LP_CLKRST_FOSC_CNTL_REG register
- *  need_des
- */
-#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
-/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400;
- *  need_des
- */
-#define LP_CLKRST_FOSC_DFREQ    0x000003FFU
-#define LP_CLKRST_FOSC_DFREQ_M  (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
-#define LP_CLKRST_FOSC_DFREQ_V  0x000003FFU
-#define LP_CLKRST_FOSC_DFREQ_S  22
-
-/** LP_CLKRST_RC32K_CNTL_REG register
- *  need_des
- */
-#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x20)
-/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650;
- *  need_des
- */
-#define LP_CLKRST_RC32K_DFREQ    0xFFFFFFFFU
-#define LP_CLKRST_RC32K_DFREQ_M  (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
-#define LP_CLKRST_RC32K_DFREQ_V  0xFFFFFFFFU
-#define LP_CLKRST_RC32K_DFREQ_S  0
-
-/** LP_CLKRST_SOSC_CNTL_REG register
- *  need_des
- */
-#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x24)
-/** LP_CLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
- *  need_des
- */
-#define LP_CLKRST_SOSC_DFREQ    0x000003FFU
-#define LP_CLKRST_SOSC_DFREQ_M  (LP_CLKRST_SOSC_DFREQ_V << LP_CLKRST_SOSC_DFREQ_S)
-#define LP_CLKRST_SOSC_DFREQ_V  0x000003FFU
-#define LP_CLKRST_SOSC_DFREQ_S  22
-
-/** LP_CLKRST_CLK_TO_HP_REG register
- *  need_des
- */
-#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x28)
-/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
- *  reserved
- */
-#define LP_CLKRST_ICG_HP_XTAL32K    (BIT(28))
-#define LP_CLKRST_ICG_HP_XTAL32K_M  (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
-#define LP_CLKRST_ICG_HP_XTAL32K_V  0x00000001U
-#define LP_CLKRST_ICG_HP_XTAL32K_S  28
-/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
- *  reserved
- */
-#define LP_CLKRST_ICG_HP_SOSC    (BIT(29))
-#define LP_CLKRST_ICG_HP_SOSC_M  (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
-#define LP_CLKRST_ICG_HP_SOSC_V  0x00000001U
-#define LP_CLKRST_ICG_HP_SOSC_S  29
-/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
- *  reserved
- */
-#define LP_CLKRST_ICG_HP_OSC32K    (BIT(30))
-#define LP_CLKRST_ICG_HP_OSC32K_M  (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
-#define LP_CLKRST_ICG_HP_OSC32K_V  0x00000001U
-#define LP_CLKRST_ICG_HP_OSC32K_S  30
-/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
- *  reserved
- */
-#define LP_CLKRST_ICG_HP_FOSC    (BIT(31))
-#define LP_CLKRST_ICG_HP_FOSC_M  (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
-#define LP_CLKRST_ICG_HP_FOSC_V  0x00000001U
-#define LP_CLKRST_ICG_HP_FOSC_S  31
-
-/** LP_CLKRST_LPMEM_FORCE_REG register
- *  need_des
- */
-#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
-/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
- *  reserved
- */
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M  (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
-#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S  31
-
-/** LP_CLKRST_XTAL32K_REG register
- *  need_des
- */
-#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x30)
-/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
- *  need_des
- */
-#define LP_CLKRST_DRES_XTAL32K    0x00000007U
-#define LP_CLKRST_DRES_XTAL32K_M  (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
-#define LP_CLKRST_DRES_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DRES_XTAL32K_S  22
-/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
- *  need_des
- */
-#define LP_CLKRST_DGM_XTAL32K    0x00000007U
-#define LP_CLKRST_DGM_XTAL32K_M  (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
-#define LP_CLKRST_DGM_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DGM_XTAL32K_S  25
-/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_DBUF_XTAL32K    (BIT(28))
-#define LP_CLKRST_DBUF_XTAL32K_M  (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
-#define LP_CLKRST_DBUF_XTAL32K_V  0x00000001U
-#define LP_CLKRST_DBUF_XTAL32K_S  28
-/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
- *  need_des
- */
-#define LP_CLKRST_DAC_XTAL32K    0x00000007U
-#define LP_CLKRST_DAC_XTAL32K_M  (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
-#define LP_CLKRST_DAC_XTAL32K_V  0x00000007U
-#define LP_CLKRST_DAC_XTAL32K_S  29
-
-/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG register
- *  need_des
- */
-#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x34)
-/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS    0xFFFFFFFFU
-#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_M  (LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S)
-#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V  0xFFFFFFFFU
-#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S  0
-
-/** LP_CLKRST_HPSYS_0_RESET_BYPASS_REG register
- *  need_des
- */
-#define LP_CLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x38)
-/** LP_CLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define LP_CLKRST_HPSYS_0_RESET_BYPASS    0xFFFFFFFFU
-#define LP_CLKRST_HPSYS_0_RESET_BYPASS_M  (LP_CLKRST_HPSYS_0_RESET_BYPASS_V << LP_CLKRST_HPSYS_0_RESET_BYPASS_S)
-#define LP_CLKRST_HPSYS_0_RESET_BYPASS_V  0xFFFFFFFFU
-#define LP_CLKRST_HPSYS_0_RESET_BYPASS_S  0
-
-/** LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG register
- *  need_des
- */
-#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x3c)
-/** LP_CLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
- *  reserved
- */
-#define LP_CLKRST_HPSYS_APM_RESET_BYPASS    0xFFFFFFFFU
-#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_M  (LP_CLKRST_HPSYS_APM_RESET_BYPASS_V << LP_CLKRST_HPSYS_APM_RESET_BYPASS_S)
-#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_V  0xFFFFFFFFU
-#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_S  0
-
-/** LP_CLKRST_HP_CLK_CTRL_REG register
- *  HP Clock Control Register.
- */
-#define LP_CLKRST_HP_CLK_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x40)
-/** LP_CLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
- *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
- */
-#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL    0x00000003U
-#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_M  (LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S)
-#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V  0x00000003U
-#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S  0
-/** LP_CLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1;
- *  HP SoC Root Clock Enable.
- */
-#define LP_CLKRST_HP_ROOT_CLK_EN    (BIT(2))
-#define LP_CLKRST_HP_ROOT_CLK_EN_M  (LP_CLKRST_HP_ROOT_CLK_EN_V << LP_CLKRST_HP_ROOT_CLK_EN_S)
-#define LP_CLKRST_HP_ROOT_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_ROOT_CLK_EN_S  2
-/** LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  PARLIO TX Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN    (BIT(3))
-#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_M  (LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S  3
-/** LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  PARLIO RX Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN    (BIT(4))
-#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_M  (LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S  4
-/** LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  UART4 SLP Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN    (BIT(5))
-#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S  5
-/** LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1;
- *  UART3 SLP Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN    (BIT(6))
-#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S  6
-/** LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1;
- *  UART2 SLP Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN    (BIT(7))
-#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S  7
-/** LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1;
- *  UART1 SLP Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN    (BIT(8))
-#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S  8
-/** LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1;
- *  UART0 SLP Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN    (BIT(9))
-#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S  9
-/** LP_CLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1;
- *  I2S2 MCLK Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN    (BIT(10))
-#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S)
-#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S  10
-/** LP_CLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1;
- *  I2S1 MCLK Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN    (BIT(11))
-#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S)
-#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S  11
-/** LP_CLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1;
- *  I2S0 MCLK Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN    (BIT(12))
-#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S)
-#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S  12
-/** LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1;
- *  EMAC RX Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN    (BIT(13))
-#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S  13
-/** LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1;
- *  EMAC TX Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN    (BIT(14))
-#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S  14
-/** LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1;
- *  EMAC TXRX Clock From Pad Enable.
- */
-#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN    (BIT(15))
-#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S)
-#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S  15
-/** LP_CLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1;
- *  XTAL 32K Clock Enable.
- */
-#define LP_CLKRST_HP_XTAL_32K_CLK_EN    (BIT(16))
-#define LP_CLKRST_HP_XTAL_32K_CLK_EN_M  (LP_CLKRST_HP_XTAL_32K_CLK_EN_V << LP_CLKRST_HP_XTAL_32K_CLK_EN_S)
-#define LP_CLKRST_HP_XTAL_32K_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_XTAL_32K_CLK_EN_S  16
-/** LP_CLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1;
- *  RC 32K Clock Enable.
- */
-#define LP_CLKRST_HP_RC_32K_CLK_EN    (BIT(17))
-#define LP_CLKRST_HP_RC_32K_CLK_EN_M  (LP_CLKRST_HP_RC_32K_CLK_EN_V << LP_CLKRST_HP_RC_32K_CLK_EN_S)
-#define LP_CLKRST_HP_RC_32K_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_RC_32K_CLK_EN_S  17
-/** LP_CLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1;
- *  SOSC 150K Clock Enable.
- */
-#define LP_CLKRST_HP_SOSC_150K_CLK_EN    (BIT(18))
-#define LP_CLKRST_HP_SOSC_150K_CLK_EN_M  (LP_CLKRST_HP_SOSC_150K_CLK_EN_V << LP_CLKRST_HP_SOSC_150K_CLK_EN_S)
-#define LP_CLKRST_HP_SOSC_150K_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_SOSC_150K_CLK_EN_S  18
-/** LP_CLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1;
- *  PLL 8M Clock Enable.
- */
-#define LP_CLKRST_HP_PLL_8M_CLK_EN    (BIT(19))
-#define LP_CLKRST_HP_PLL_8M_CLK_EN_M  (LP_CLKRST_HP_PLL_8M_CLK_EN_V << LP_CLKRST_HP_PLL_8M_CLK_EN_S)
-#define LP_CLKRST_HP_PLL_8M_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_PLL_8M_CLK_EN_S  19
-/** LP_CLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1;
- *  AUDIO PLL Clock Enable.
- */
-#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN    (BIT(20))
-#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_M  (LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S)
-#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S  20
-/** LP_CLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1;
- *  SDIO PLL2 Clock Enable.
- */
-#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN    (BIT(21))
-#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S)
-#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S  21
-/** LP_CLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1;
- *  SDIO PLL1 Clock Enable.
- */
-#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN    (BIT(22))
-#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S)
-#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S  22
-/** LP_CLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1;
- *  SDIO PLL0 Clock Enable.
- */
-#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN    (BIT(23))
-#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S)
-#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S  23
-/** LP_CLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1;
- *  FOSC 20M Clock Enable.
- */
-#define LP_CLKRST_HP_FOSC_20M_CLK_EN    (BIT(24))
-#define LP_CLKRST_HP_FOSC_20M_CLK_EN_M  (LP_CLKRST_HP_FOSC_20M_CLK_EN_V << LP_CLKRST_HP_FOSC_20M_CLK_EN_S)
-#define LP_CLKRST_HP_FOSC_20M_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_FOSC_20M_CLK_EN_S  24
-/** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1;
- *  XTAL 40M Clock Enalbe.
- */
-#define LP_CLKRST_HP_XTAL_40M_CLK_EN    (BIT(25))
-#define LP_CLKRST_HP_XTAL_40M_CLK_EN_M  (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S)
-#define LP_CLKRST_HP_XTAL_40M_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_XTAL_40M_CLK_EN_S  25
-/** LP_CLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1;
- *  CPLL 400M Clock Enable.
- */
-#define LP_CLKRST_HP_CPLL_400M_CLK_EN    (BIT(26))
-#define LP_CLKRST_HP_CPLL_400M_CLK_EN_M  (LP_CLKRST_HP_CPLL_400M_CLK_EN_V << LP_CLKRST_HP_CPLL_400M_CLK_EN_S)
-#define LP_CLKRST_HP_CPLL_400M_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_CPLL_400M_CLK_EN_S  26
-/** LP_CLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1;
- *  SPLL 480M Clock Enable.
- */
-#define LP_CLKRST_HP_SPLL_480M_CLK_EN    (BIT(27))
-#define LP_CLKRST_HP_SPLL_480M_CLK_EN_M  (LP_CLKRST_HP_SPLL_480M_CLK_EN_V << LP_CLKRST_HP_SPLL_480M_CLK_EN_S)
-#define LP_CLKRST_HP_SPLL_480M_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_SPLL_480M_CLK_EN_S  27
-/** LP_CLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1;
- *  MPLL 500M Clock Enable.
- */
-#define LP_CLKRST_HP_MPLL_500M_CLK_EN    (BIT(28))
-#define LP_CLKRST_HP_MPLL_500M_CLK_EN_M  (LP_CLKRST_HP_MPLL_500M_CLK_EN_V << LP_CLKRST_HP_MPLL_500M_CLK_EN_S)
-#define LP_CLKRST_HP_MPLL_500M_CLK_EN_V  0x00000001U
-#define LP_CLKRST_HP_MPLL_500M_CLK_EN_S  28
-
-/** LP_CLKRST_HP_USB_CLKRST_CTRL0_REG register
- *  HP USB Clock Reset Control Register.
- */
-#define LP_CLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x44)
-/** LP_CLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0;
- *  unused.
- */
-#define LP_CLKRST_USB_OTG20_SLEEP_MODE    (BIT(0))
-#define LP_CLKRST_USB_OTG20_SLEEP_MODE_M  (LP_CLKRST_USB_OTG20_SLEEP_MODE_V << LP_CLKRST_USB_OTG20_SLEEP_MODE_S)
-#define LP_CLKRST_USB_OTG20_SLEEP_MODE_V  0x00000001U
-#define LP_CLKRST_USB_OTG20_SLEEP_MODE_S  0
-/** LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  unused.
- */
-#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN    (BIT(1))
-#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_M  (LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S)
-#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V  0x00000001U
-#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S  1
-/** LP_CLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0;
- *  unused.
- */
-#define LP_CLKRST_USB_OTG11_SLEEP_MODE    (BIT(2))
-#define LP_CLKRST_USB_OTG11_SLEEP_MODE_M  (LP_CLKRST_USB_OTG11_SLEEP_MODE_V << LP_CLKRST_USB_OTG11_SLEEP_MODE_S)
-#define LP_CLKRST_USB_OTG11_SLEEP_MODE_V  0x00000001U
-#define LP_CLKRST_USB_OTG11_SLEEP_MODE_S  2
-/** LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1;
- *  unused.
- */
-#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN    (BIT(3))
-#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_M  (LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S)
-#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V  0x00000001U
-#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S  3
-/** LP_CLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
- *  usb otg11 fs phy clock enable.
- */
-#define LP_CLKRST_USB_OTG11_48M_CLK_EN    (BIT(4))
-#define LP_CLKRST_USB_OTG11_48M_CLK_EN_M  (LP_CLKRST_USB_OTG11_48M_CLK_EN_V << LP_CLKRST_USB_OTG11_48M_CLK_EN_S)
-#define LP_CLKRST_USB_OTG11_48M_CLK_EN_V  0x00000001U
-#define LP_CLKRST_USB_OTG11_48M_CLK_EN_S  4
-/** LP_CLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1;
- *  usb device fs phy clock enable.
- */
-#define LP_CLKRST_USB_DEVICE_48M_CLK_EN    (BIT(5))
-#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_M  (LP_CLKRST_USB_DEVICE_48M_CLK_EN_V << LP_CLKRST_USB_DEVICE_48M_CLK_EN_S)
-#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_V  0x00000001U
-#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_S  5
-/** LP_CLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9;
- *  usb 480m to 25m divide number.
- */
-#define LP_CLKRST_USB_48M_DIV_NUM    0x000000FFU
-#define LP_CLKRST_USB_48M_DIV_NUM_M  (LP_CLKRST_USB_48M_DIV_NUM_V << LP_CLKRST_USB_48M_DIV_NUM_S)
-#define LP_CLKRST_USB_48M_DIV_NUM_V  0x000000FFU
-#define LP_CLKRST_USB_48M_DIV_NUM_S  6
-/** LP_CLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19;
- *  usb 500m to 25m divide number.
- */
-#define LP_CLKRST_USB_25M_DIV_NUM    0x000000FFU
-#define LP_CLKRST_USB_25M_DIV_NUM_M  (LP_CLKRST_USB_25M_DIV_NUM_V << LP_CLKRST_USB_25M_DIV_NUM_S)
-#define LP_CLKRST_USB_25M_DIV_NUM_V  0x000000FFU
-#define LP_CLKRST_USB_25M_DIV_NUM_S  14
-/** LP_CLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39;
- *  usb 480m to 12m divide number.
- */
-#define LP_CLKRST_USB_12M_DIV_NUM    0x000000FFU
-#define LP_CLKRST_USB_12M_DIV_NUM_M  (LP_CLKRST_USB_12M_DIV_NUM_V << LP_CLKRST_USB_12M_DIV_NUM_S)
-#define LP_CLKRST_USB_12M_DIV_NUM_V  0x000000FFU
-#define LP_CLKRST_USB_12M_DIV_NUM_S  22
-
-/** LP_CLKRST_HP_USB_CLKRST_CTRL1_REG register
- *  HP USB Clock Reset Control Register.
- */
-#define LP_CLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x48)
-/** LP_CLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0;
- *  usb otg20 adp reset en
- */
-#define LP_CLKRST_RST_EN_USB_OTG20_ADP    (BIT(0))
-#define LP_CLKRST_RST_EN_USB_OTG20_ADP_M  (LP_CLKRST_RST_EN_USB_OTG20_ADP_V << LP_CLKRST_RST_EN_USB_OTG20_ADP_S)
-#define LP_CLKRST_RST_EN_USB_OTG20_ADP_V  0x00000001U
-#define LP_CLKRST_RST_EN_USB_OTG20_ADP_S  0
-/** LP_CLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0;
- *  usb otg20 phy reset en
- */
-#define LP_CLKRST_RST_EN_USB_OTG20_PHY    (BIT(1))
-#define LP_CLKRST_RST_EN_USB_OTG20_PHY_M  (LP_CLKRST_RST_EN_USB_OTG20_PHY_V << LP_CLKRST_RST_EN_USB_OTG20_PHY_S)
-#define LP_CLKRST_RST_EN_USB_OTG20_PHY_V  0x00000001U
-#define LP_CLKRST_RST_EN_USB_OTG20_PHY_S  1
-/** LP_CLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0;
- *  usb otg20 reset en
- */
-#define LP_CLKRST_RST_EN_USB_OTG20    (BIT(2))
-#define LP_CLKRST_RST_EN_USB_OTG20_M  (LP_CLKRST_RST_EN_USB_OTG20_V << LP_CLKRST_RST_EN_USB_OTG20_S)
-#define LP_CLKRST_RST_EN_USB_OTG20_V  0x00000001U
-#define LP_CLKRST_RST_EN_USB_OTG20_S  2
-/** LP_CLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0;
- *  usb org11 reset en
- */
-#define LP_CLKRST_RST_EN_USB_OTG11    (BIT(3))
-#define LP_CLKRST_RST_EN_USB_OTG11_M  (LP_CLKRST_RST_EN_USB_OTG11_V << LP_CLKRST_RST_EN_USB_OTG11_S)
-#define LP_CLKRST_RST_EN_USB_OTG11_V  0x00000001U
-#define LP_CLKRST_RST_EN_USB_OTG11_S  3
-/** LP_CLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0;
- *  usb device reset en
- */
-#define LP_CLKRST_RST_EN_USB_DEVICE    (BIT(4))
-#define LP_CLKRST_RST_EN_USB_DEVICE_M  (LP_CLKRST_RST_EN_USB_DEVICE_V << LP_CLKRST_RST_EN_USB_DEVICE_S)
-#define LP_CLKRST_RST_EN_USB_DEVICE_V  0x00000001U
-#define LP_CLKRST_RST_EN_USB_DEVICE_S  4
-/** LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0;
- *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
- */
-#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL    0x00000003U
-#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M  (LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S)
-#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V  0x00000003U
-#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S  28
-/** LP_CLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1;
- *  usb otg20 hs phy refclk enable.
- */
-#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN    (BIT(30))
-#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_M  (LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S)
-#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V  0x00000001U
-#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S  30
-/** LP_CLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1;
- *  usb otg20 ulpi clock enable.
- */
-#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN    (BIT(31))
-#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_M  (LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S)
-#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V  0x00000001U
-#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S  31
-
-/** LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register
- *  need_des
- */
-#define LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x4c)
-/** LP_CLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0;
- *  hp sdmmc reset en
- */
-#define LP_CLKRST_RST_EN_SDMMC    (BIT(28))
-#define LP_CLKRST_RST_EN_SDMMC_M  (LP_CLKRST_RST_EN_SDMMC_V << LP_CLKRST_RST_EN_SDMMC_S)
-#define LP_CLKRST_RST_EN_SDMMC_V  0x00000001U
-#define LP_CLKRST_RST_EN_SDMMC_S  28
-/** LP_CLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0;
- *  hp sdmmc force norst
- */
-#define LP_CLKRST_FORCE_NORST_SDMMC    (BIT(29))
-#define LP_CLKRST_FORCE_NORST_SDMMC_M  (LP_CLKRST_FORCE_NORST_SDMMC_V << LP_CLKRST_FORCE_NORST_SDMMC_S)
-#define LP_CLKRST_FORCE_NORST_SDMMC_V  0x00000001U
-#define LP_CLKRST_FORCE_NORST_SDMMC_S  29
-/** LP_CLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0;
- *  hp emac reset en
- */
-#define LP_CLKRST_RST_EN_EMAC    (BIT(30))
-#define LP_CLKRST_RST_EN_EMAC_M  (LP_CLKRST_RST_EN_EMAC_V << LP_CLKRST_RST_EN_EMAC_S)
-#define LP_CLKRST_RST_EN_EMAC_V  0x00000001U
-#define LP_CLKRST_RST_EN_EMAC_S  30
-/** LP_CLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0;
- *  hp emac force norst
- */
-#define LP_CLKRST_FORCE_NORST_EMAC    (BIT(31))
-#define LP_CLKRST_FORCE_NORST_EMAC_M  (LP_CLKRST_FORCE_NORST_EMAC_V << LP_CLKRST_FORCE_NORST_EMAC_S)
-#define LP_CLKRST_FORCE_NORST_EMAC_V  0x00000001U
-#define LP_CLKRST_FORCE_NORST_EMAC_S  31
-
-/** LP_CLKRST_DATE_REG register
- *  need_des
- */
-#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
-/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  need_des
- */
-#define LP_CLKRST_CLK_EN    (BIT(31))
-#define LP_CLKRST_CLK_EN_M  (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
-#define LP_CLKRST_CLK_EN_V  0x00000001U
-#define LP_CLKRST_CLK_EN_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h b/components/soc/esp32p4/include/soc/lp_clkrst_struct.h
deleted file mode 100644
index 2e2246001f4..00000000000
--- a/components/soc/esp32p4/include/soc/lp_clkrst_struct.h
+++ /dev/null
@@ -1,797 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: configure_register */
-/** Type of lp_clk_conf register
- *  need_des
- */
-typedef union {
-    struct {
-        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
-         *  need_des
-         */
-        uint32_t slow_clk_sel:2;
-        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
-         *  need_des
-         */
-        uint32_t fast_clk_sel:2;
-        /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_peri_div_num:6;
-        /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0;
-         *  need_des
-         */
-        uint32_t ana_sel_ref_pll8m:1;
-        uint32_t reserved_11:21;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_conf_reg_t;
-
-/** Type of lp_clk_po_en register
- *  need_des
- */
-typedef union {
-    struct {
-        /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_core_efuse_oen:1;
-        /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_lp_bus_oen:1;
-        /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_aon_slow_oen:1;
-        /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_aon_fast_oen:1;
-        /** clk_slow_oen : R/W; bitpos: [4]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_slow_oen:1;
-        /** clk_fast_oen : R/W; bitpos: [5]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_fast_oen:1;
-        /** clk_fosc_oen : R/W; bitpos: [6]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_fosc_oen:1;
-        /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_rc32k_oen:1;
-        /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_sxtal_oen:1;
-        /** clk_sosc_oen : R/W; bitpos: [9]; default: 0;
-         *  1'b1: probe sosc clk on
-         *  1'b0: probe sosc clk off
-         */
-        uint32_t clk_sosc_oen:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_po_en_reg_t;
-
-/** Type of lp_clk_en register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:26;
-        /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t lp_rtc_xtal_force_on:1;
-        /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1;
-         *  need_des
-         */
-        uint32_t ck_en_lp_ram:1;
-        /** etm_event_tick_en : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t etm_event_tick_en:1;
-        /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t pll8m_clk_force_on:1;
-        /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t xtal_clk_force_on:1;
-        /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t fosc_clk_force_on:1;
-    };
-    uint32_t val;
-} lp_clkrst_lp_clk_en_reg_t;
-
-/** Type of lp_rst_en register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_huk:1;
-        /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_anaperi:1;
-        /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_wdt:1;
-        /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_timer:1;
-        /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_rtc:1;
-        /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_mailbox:1;
-        /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_aonefusereg:1;
-        /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t rst_en_lp_ram:1;
-    };
-    uint32_t val;
-} lp_clkrst_lp_rst_en_reg_t;
-
-/** Type of reset_cause register
- *  need_des
- */
-typedef union {
-    struct {
-        /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0;
-         *  6'h1: POR reset
-         *  6'h9: PMU LP PERI power down reset
-         *  6'ha: PMU LP CPU reset
-         *  6'hf: brown out reset
-         *  6'h10: LP watchdog chip reset
-         *  6'h12: super watch dog reset
-         *  6'h13: glitch reset
-         *  6'h14: software reset
-         */
-        uint32_t lpcore_reset_cause:6;
-        /** lpcore_reset_flag : RO; bitpos: [6]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_reset_flag:1;
-        /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0;
-         *  6'h1: POR reset
-         *  6'h3: digital system software reset
-         *  6'h5: PMU HP system power down reset
-         *  6'h7: HP system reset from HP watchdog
-         *  6'h9: HP system reset from LP watchdog
-         *  6'hb: HP core reset from HP watchdog
-         *  6'hc: HP core software reset
-         *  6'hd: HP core reset from LP watchdog
-         *  6'hf: brown out reset
-         *  6'h10: LP watchdog chip reset
-         *  6'h12: super watch dog reset
-         *  6'h13: glitch reset
-         *  6'h14: efuse crc error reset
-         *  6'h16: HP usb jtag chip reset
-         *  6'h17: HP usb uart chip reset
-         *  6'h18: HP jtag reset
-         *  6'h1a: HP core lockup
-         */
-        uint32_t hpcore0_reset_cause:6;
-        /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_reset_flag:1;
-        /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0;
-         *  6'h1: POR reset
-         *  6'h3: digital system software reset
-         *  6'h5: PMU HP system power down reset
-         *  6'h7: HP system reset from HP watchdog
-         *  6'h9: HP system reset from LP watchdog
-         *  6'hb: HP core reset from HP watchdog
-         *  6'hc: HP core software reset
-         *  6'hd: HP core reset from LP watchdog
-         *  6'hf: brown out reset
-         *  6'h10: LP watchdog chip reset
-         *  6'h12: super watch dog reset
-         *  6'h13: glitch reset
-         *  6'h14: efuse crc error reset
-         *  6'h16: HP usb jtag chip reset
-         *  6'h17: HP usb uart chip reset
-         *  6'h18: HP jtag reset
-         *  6'h1a: HP core lockup
-         */
-        uint32_t hpcore1_reset_cause:6;
-        /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_reset_flag:1;
-        uint32_t reserved_21:4;
-        /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1;
-         *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
-         *  pmu_lp_cpu_reset reset_cause
-         */
-        uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1;
-        /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_reset_cause_clr:1;
-        /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0;
-         *  need_des
-         */
-        uint32_t lpcore_reset_flag_clr:1;
-        /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_reset_cause_clr:1;
-        /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_reset_flag_clr:1;
-        /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_reset_cause_clr:1;
-        /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_reset_flag_clr:1;
-    };
-    uint32_t val;
-} lp_clkrst_reset_cause_reg_t;
-
-/** Type of hpcpu_reset_ctrl0 register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0;
-         *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
-         *  reset feature
-         */
-        uint32_t hpcore0_lockup_reset_en:1;
-        /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_wdt_hpcore0_reset_length:3;
-        /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0;
-         *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
-         *  hpcore0 feature
-         */
-        uint32_t lp_wdt_hpcore0_reset_en:1;
-        /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_stall_wait:7;
-        /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_stall_en:1;
-        /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_sw_reset:1;
-        /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore0_ocd_halt_on_reset:1;
-        /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1;
-         *  1'b1: boot from HP TCM ROM: 0x4FC00000
-         *  1'b0: boot from LP TCM RAM:  0x50108000
-         */
-        uint32_t hpcore0_stat_vector_sel:1;
-        /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0;
-         *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
-         *  reset feature
-         */
-        uint32_t hpcore1_lockup_reset_en:1;
-        /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1;
-         *  need_des
-         */
-        uint32_t lp_wdt_hpcore1_reset_length:3;
-        /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0;
-         *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
-         *  hpcore1 feature
-         */
-        uint32_t lp_wdt_hpcore1_reset_en:1;
-        /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_stall_wait:7;
-        /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_stall_en:1;
-        /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_sw_reset:1;
-        /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0;
-         *  need_des
-         */
-        uint32_t hpcore1_ocd_halt_on_reset:1;
-        /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1;
-         *  1'b1: boot from HP TCM ROM: 0x4FC00000
-         *  1'b0: boot from LP TCM RAM:  0x50108000
-         */
-        uint32_t hpcore1_stat_vector_sel:1;
-    };
-    uint32_t val;
-} lp_clkrst_hpcpu_reset_ctrl0_reg_t;
-
-/** Type of hpcpu_reset_ctrl1 register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:16;
-        /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0;
-         *  HP core0 software stall when set to 8'h86
-         */
-        uint32_t hpcore0_sw_stall_code:8;
-        /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0;
-         *  HP core1 software stall when set to 8'h86
-         */
-        uint32_t hpcore1_sw_stall_code:8;
-    };
-    uint32_t val;
-} lp_clkrst_hpcpu_reset_ctrl1_reg_t;
-
-/** Type of fosc_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400;
-         *  need_des
-         */
-        uint32_t fosc_dfreq:10;
-    };
-    uint32_t val;
-} lp_clkrst_fosc_cntl_reg_t;
-
-/** Type of rc32k_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650;
-         *  need_des
-         */
-        uint32_t rc32k_dfreq:32;
-    };
-    uint32_t val;
-} lp_clkrst_rc32k_cntl_reg_t;
-
-/** Type of sosc_cntl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172;
-         *  need_des
-         */
-        uint32_t sosc_dfreq:10;
-    };
-    uint32_t val;
-} lp_clkrst_sosc_cntl_reg_t;
-
-/** Type of clk_to_hp register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
-         *  reserved
-         */
-        uint32_t icg_hp_xtal32k:1;
-        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
-         *  reserved
-         */
-        uint32_t icg_hp_sosc:1;
-        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
-         *  reserved
-         */
-        uint32_t icg_hp_osc32k:1;
-        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
-         *  reserved
-         */
-        uint32_t icg_hp_fosc:1;
-    };
-    uint32_t val;
-} lp_clkrst_clk_to_hp_reg_t;
-
-/** Type of lpmem_force register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
-         *  reserved
-         */
-        uint32_t lpmem_clk_force_on:1;
-    };
-    uint32_t val;
-} lp_clkrst_lpmem_force_reg_t;
-
-/** Type of xtal32k register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:22;
-        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
-         *  need_des
-         */
-        uint32_t dres_xtal32k:3;
-        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
-         *  need_des
-         */
-        uint32_t dgm_xtal32k:3;
-        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
-         *  need_des
-         */
-        uint32_t dbuf_xtal32k:1;
-        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
-         *  need_des
-         */
-        uint32_t dac_xtal32k:3;
-    };
-    uint32_t val;
-} lp_clkrst_xtal32k_reg_t;
-
-/** Type of mux_hpsys_reset_bypass register
- *  need_des
- */
-typedef union {
-    struct {
-        /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t mux_hpsys_reset_bypass:32;
-    };
-    uint32_t val;
-} lp_clkrst_mux_hpsys_reset_bypass_reg_t;
-
-/** Type of hpsys_0_reset_bypass register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t hpsys_0_reset_bypass:32;
-    };
-    uint32_t val;
-} lp_clkrst_hpsys_0_reset_bypass_reg_t;
-
-/** Type of hpsys_apm_reset_bypass register
- *  need_des
- */
-typedef union {
-    struct {
-        /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
-         *  reserved
-         */
-        uint32_t hpsys_apm_reset_bypass:32;
-    };
-    uint32_t val;
-} lp_clkrst_hpsys_apm_reset_bypass_reg_t;
-
-/** Type of hp_clk_ctrl register
- *  HP Clock Control Register.
- */
-typedef union {
-    struct {
-        /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
-         *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
-         */
-        uint32_t hp_root_clk_src_sel:2;
-        /** hp_root_clk_en : R/W; bitpos: [2]; default: 1;
-         *  HP SoC Root Clock Enable.
-         */
-        uint32_t hp_root_clk_en:1;
-        /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1;
-         *  PARLIO TX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_parlio_tx_clk_en:1;
-        /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1;
-         *  PARLIO RX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_parlio_rx_clk_en:1;
-        /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1;
-         *  UART4 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart4_slp_clk_en:1;
-        /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1;
-         *  UART3 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart3_slp_clk_en:1;
-        /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1;
-         *  UART2 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart2_slp_clk_en:1;
-        /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1;
-         *  UART1 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart1_slp_clk_en:1;
-        /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1;
-         *  UART0 SLP Clock From Pad Enable.
-         */
-        uint32_t hp_pad_uart0_slp_clk_en:1;
-        /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1;
-         *  I2S2 MCLK Clock From Pad Enable.
-         */
-        uint32_t hp_pad_i2s2_mclk_en:1;
-        /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1;
-         *  I2S1 MCLK Clock From Pad Enable.
-         */
-        uint32_t hp_pad_i2s1_mclk_en:1;
-        /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1;
-         *  I2S0 MCLK Clock From Pad Enable.
-         */
-        uint32_t hp_pad_i2s0_mclk_en:1;
-        /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1;
-         *  EMAC RX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_emac_tx_clk_en:1;
-        /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1;
-         *  EMAC TX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_emac_rx_clk_en:1;
-        /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1;
-         *  EMAC TXRX Clock From Pad Enable.
-         */
-        uint32_t hp_pad_emac_txrx_clk_en:1;
-        /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1;
-         *  XTAL 32K Clock Enable.
-         */
-        uint32_t hp_xtal_32k_clk_en:1;
-        /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1;
-         *  RC 32K Clock Enable.
-         */
-        uint32_t hp_rc_32k_clk_en:1;
-        /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1;
-         *  SOSC 150K Clock Enable.
-         */
-        uint32_t hp_sosc_150k_clk_en:1;
-        /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1;
-         *  PLL 8M Clock Enable.
-         */
-        uint32_t hp_pll_8m_clk_en:1;
-        /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1;
-         *  AUDIO PLL Clock Enable.
-         */
-        uint32_t hp_audio_pll_clk_en:1;
-        /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1;
-         *  SDIO PLL2 Clock Enable.
-         */
-        uint32_t hp_sdio_pll2_clk_en:1;
-        /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1;
-         *  SDIO PLL1 Clock Enable.
-         */
-        uint32_t hp_sdio_pll1_clk_en:1;
-        /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1;
-         *  SDIO PLL0 Clock Enable.
-         */
-        uint32_t hp_sdio_pll0_clk_en:1;
-        /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1;
-         *  FOSC 20M Clock Enable.
-         */
-        uint32_t hp_fosc_20m_clk_en:1;
-        /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1;
-         *  XTAL 40M Clock Enalbe.
-         */
-        uint32_t hp_xtal_40m_clk_en:1;
-        /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1;
-         *  CPLL 400M Clock Enable.
-         */
-        uint32_t hp_cpll_400m_clk_en:1;
-        /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1;
-         *  SPLL 480M Clock Enable.
-         */
-        uint32_t hp_spll_480m_clk_en:1;
-        /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1;
-         *  MPLL 500M Clock Enable.
-         */
-        uint32_t hp_mpll_500m_clk_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} lp_clkrst_hp_clk_ctrl_reg_t;
-
-/** Type of hp_usb_clkrst_ctrl0 register
- *  HP USB Clock Reset Control Register.
- */
-typedef union {
-    struct {
-        /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0;
-         *  unused.
-         */
-        uint32_t usb_otg20_sleep_mode:1;
-        /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1;
-         *  unused.
-         */
-        uint32_t usb_otg20_bk_sys_clk_en:1;
-        /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0;
-         *  unused.
-         */
-        uint32_t usb_otg11_sleep_mode:1;
-        /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1;
-         *  unused.
-         */
-        uint32_t usb_otg11_bk_sys_clk_en:1;
-        /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1;
-         *  usb otg11 fs phy clock enable.
-         */
-        uint32_t usb_otg11_48m_clk_en:1;
-        /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1;
-         *  usb device fs phy clock enable.
-         */
-        uint32_t usb_device_48m_clk_en:1;
-        /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9;
-         *  usb 480m to 25m divide number.
-         */
-        uint32_t usb_48m_div_num:8;
-        /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19;
-         *  usb 500m to 25m divide number.
-         */
-        uint32_t usb_25m_div_num:8;
-        /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39;
-         *  usb 480m to 12m divide number.
-         */
-        uint32_t usb_12m_div_num:8;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} lp_clkrst_hp_usb_clkrst_ctrl0_reg_t;
-
-/** Type of hp_usb_clkrst_ctrl1 register
- *  HP USB Clock Reset Control Register.
- */
-typedef union {
-    struct {
-        /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0;
-         *  usb otg20 adp reset en
-         */
-        uint32_t rst_en_usb_otg20_adp:1;
-        /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0;
-         *  usb otg20 phy reset en
-         */
-        uint32_t rst_en_usb_otg20_phy:1;
-        /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0;
-         *  usb otg20 reset en
-         */
-        uint32_t rst_en_usb_otg20:1;
-        /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0;
-         *  usb org11 reset en
-         */
-        uint32_t rst_en_usb_otg11:1;
-        /** rst_en_usb_device : R/W; bitpos: [4]; default: 0;
-         *  usb device reset en
-         */
-        uint32_t rst_en_usb_device:1;
-        uint32_t reserved_5:23;
-        /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0;
-         *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
-         */
-        uint32_t usb_otg20_phyref_clk_src_sel:2;
-        /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1;
-         *  usb otg20 hs phy refclk enable.
-         */
-        uint32_t usb_otg20_phyref_clk_en:1;
-        /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1;
-         *  usb otg20 ulpi clock enable.
-         */
-        uint32_t usb_otg20_ulpi_clk_en:1;
-    };
-    uint32_t val;
-} lp_clkrst_hp_usb_clkrst_ctrl1_reg_t;
-
-/** Type of hp_sdmmc_emac_rst_ctrl register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:28;
-        /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0;
-         *  hp sdmmc reset en
-         */
-        uint32_t rst_en_sdmmc:1;
-        /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0;
-         *  hp sdmmc force norst
-         */
-        uint32_t force_norst_sdmmc:1;
-        /** rst_en_emac : R/W; bitpos: [30]; default: 0;
-         *  hp emac reset en
-         */
-        uint32_t rst_en_emac:1;
-        /** force_norst_emac : R/W; bitpos: [31]; default: 0;
-         *  hp emac force norst
-         */
-        uint32_t force_norst_emac:1;
-    };
-    uint32_t val;
-} lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t;
-
-/** Type of date register
- *  need_des
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  need_des
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lp_clkrst_date_reg_t;
-
-
-typedef struct {
-    volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
-    volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
-    volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
-    volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
-    volatile lp_clkrst_reset_cause_reg_t reset_cause;
-    volatile lp_clkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0;
-    volatile lp_clkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1;
-    volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
-    volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
-    volatile lp_clkrst_sosc_cntl_reg_t sosc_cntl;
-    volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
-    volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
-    volatile lp_clkrst_xtal32k_reg_t xtal32k;
-    volatile lp_clkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass;
-    volatile lp_clkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass;
-    volatile lp_clkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass;
-    volatile lp_clkrst_hp_clk_ctrl_reg_t hp_clk_ctrl;
-    volatile lp_clkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0;
-    volatile lp_clkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1;
-    volatile lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl;
-    uint32_t reserved_050[235];
-    volatile lp_clkrst_date_reg_t date;
-} lp_clkrst_dev_t;
-
-extern lp_clkrst_dev_t LP_AON_CLKRST;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_uart_reg.h b/components/soc/esp32p4/include/soc/lp_uart_reg.h
deleted file mode 100644
index 0a5ba491f40..00000000000
--- a/components/soc/esp32p4/include/soc/lp_uart_reg.h
+++ /dev/null
@@ -1,1339 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** LP_UART_FIFO_REG register
- *  FIFO data register
- */
-#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0)
-/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
- *  UART $n accesses FIFO via this register.
- */
-#define LP_UART_RXFIFO_RD_BYTE    0x000000FFU
-#define LP_UART_RXFIFO_RD_BYTE_M  (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S)
-#define LP_UART_RXFIFO_RD_BYTE_V  0x000000FFU
-#define LP_UART_RXFIFO_RD_BYTE_S  0
-
-/** LP_UART_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4)
-/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  what rxfifo_full_thrhd specifies.
- */
-#define LP_UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_RAW_M  (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S)
-#define LP_UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_RAW_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
- *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- *  less than what txfifo_empty_thrhd specifies .
- */
-#define LP_UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_M  (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S)
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_RAW_S  1
-/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error in
- *  the data.
- */
-#define LP_UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_RAW_M  (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S)
-#define LP_UART_PARITY_ERR_INT_RAW_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_RAW_S  2
-/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  .
- */
-#define LP_UART_FRM_ERR_INT_RAW    (BIT(3))
-#define LP_UART_FRM_ERR_INT_RAW_M  (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S)
-#define LP_UART_FRM_ERR_INT_RAW_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_RAW_S  3
-/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  the FIFO can store.
- */
-#define LP_UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_RAW_M  (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S)
-#define LP_UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_RAW_S  4
-/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  DSRn signal.
- */
-#define LP_UART_DSR_CHG_INT_RAW    (BIT(5))
-#define LP_UART_DSR_CHG_INT_RAW_M  (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S)
-#define LP_UART_DSR_CHG_INT_RAW_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_RAW_S  5
-/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  CTSn signal.
- */
-#define LP_UART_CTS_CHG_INT_RAW    (BIT(6))
-#define LP_UART_CTS_CHG_INT_RAW_M  (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S)
-#define LP_UART_CTS_CHG_INT_RAW_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_RAW_S  6
-/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
- *  bit.
- */
-#define LP_UART_BRK_DET_INT_RAW    (BIT(7))
-#define LP_UART_BRK_DET_INT_RAW_M  (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S)
-#define LP_UART_BRK_DET_INT_RAW_V  0x00000001U
-#define LP_UART_BRK_DET_INT_RAW_S  7
-/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  This interrupt raw bit turns to high level when receiver takes more time than
- *  rx_tout_thrhd to receive a byte.
- */
-#define LP_UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_RAW_M  (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S)
-#define LP_UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_RAW_S  8
-/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define LP_UART_SW_XON_INT_RAW    (BIT(9))
-#define LP_UART_SW_XON_INT_RAW_M  (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S)
-#define LP_UART_SW_XON_INT_RAW_V  0x00000001U
-#define LP_UART_SW_XON_INT_RAW_S  9
-/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives Xoff char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define LP_UART_SW_XOFF_INT_RAW    (BIT(10))
-#define LP_UART_SW_XOFF_INT_RAW_M  (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S)
-#define LP_UART_SW_XOFF_INT_RAW_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_RAW_S  10
-/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a glitch in the
- *  middle of a start bit.
- */
-#define LP_UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_RAW_M  (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S)
-#define LP_UART_GLITCH_DET_INT_RAW_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_RAW_S  11
-/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter completes  sending
- *  NULL characters after all data in Tx-FIFO are sent.
- */
-#define LP_UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_RAW_M  (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S)
-#define LP_UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_RAW_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has kept the shortest
- *  duration after sending the  last data.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M  (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has send out all data
- *  in FIFO.
- */
-#define LP_UART_TX_DONE_INT_RAW    (BIT(14))
-#define LP_UART_TX_DONE_INT_RAW_M  (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S)
-#define LP_UART_TX_DONE_INT_RAW_V  0x00000001U
-#define LP_UART_TX_DONE_INT_RAW_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the configured
- *  at_cmd char.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M  (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  This interrupt raw bit turns to high level when input rxd edge changes more times
- *  than what reg_active_threshold specifies in light sleeping mode.
- */
-#define LP_UART_WAKEUP_INT_RAW    (BIT(19))
-#define LP_UART_WAKEUP_INT_RAW_M  (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S)
-#define LP_UART_WAKEUP_INT_RAW_V  0x00000001U
-#define LP_UART_WAKEUP_INT_RAW_S  19
-
-/** LP_UART_INT_ST_REG register
- *  Masked interrupt status
- */
-#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8)
-/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
- *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_ST_M  (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S)
-#define LP_UART_RXFIFO_FULL_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_ST_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
- *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
- *  to 1.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_ST_M  (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S)
-#define LP_UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_ST_S  1
-/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
- *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
- */
-#define LP_UART_PARITY_ERR_INT_ST    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_ST_M  (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S)
-#define LP_UART_PARITY_ERR_INT_ST_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_ST_S  2
-/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
- *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
- */
-#define LP_UART_FRM_ERR_INT_ST    (BIT(3))
-#define LP_UART_FRM_ERR_INT_ST_M  (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S)
-#define LP_UART_FRM_ERR_INT_ST_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_ST_S  3
-/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_ST_M  (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S)
-#define LP_UART_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_ST_S  4
-/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
- */
-#define LP_UART_DSR_CHG_INT_ST    (BIT(5))
-#define LP_UART_DSR_CHG_INT_ST_M  (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S)
-#define LP_UART_DSR_CHG_INT_ST_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_ST_S  5
-/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
- *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
- */
-#define LP_UART_CTS_CHG_INT_ST    (BIT(6))
-#define LP_UART_CTS_CHG_INT_ST_M  (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S)
-#define LP_UART_CTS_CHG_INT_ST_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_ST_S  6
-/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
- *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
- */
-#define LP_UART_BRK_DET_INT_ST    (BIT(7))
-#define LP_UART_BRK_DET_INT_ST_M  (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S)
-#define LP_UART_BRK_DET_INT_ST_V  0x00000001U
-#define LP_UART_BRK_DET_INT_ST_S  7
-/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
- */
-#define LP_UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_ST_M  (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S)
-#define LP_UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_ST_S  8
-/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
- *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
- */
-#define LP_UART_SW_XON_INT_ST    (BIT(9))
-#define LP_UART_SW_XON_INT_ST_M  (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S)
-#define LP_UART_SW_XON_INT_ST_V  0x00000001U
-#define LP_UART_SW_XON_INT_ST_S  9
-/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
- *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
- */
-#define LP_UART_SW_XOFF_INT_ST    (BIT(10))
-#define LP_UART_SW_XOFF_INT_ST_M  (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S)
-#define LP_UART_SW_XOFF_INT_ST_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_ST_S  10
-/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
- *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
- */
-#define LP_UART_GLITCH_DET_INT_ST    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_ST_M  (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S)
-#define LP_UART_GLITCH_DET_INT_ST_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_ST_S  11
-/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
- */
-#define LP_UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_ST_M  (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S)
-#define LP_UART_TX_BRK_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_ST_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- *  is set to 1.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
- */
-#define LP_UART_TX_DONE_INT_ST    (BIT(14))
-#define LP_UART_TX_DONE_INT_ST_M  (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S)
-#define LP_UART_TX_DONE_INT_ST_V  0x00000001U
-#define LP_UART_TX_DONE_INT_ST_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
- *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
- *  to 1.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M  (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
- *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
- */
-#define LP_UART_WAKEUP_INT_ST    (BIT(19))
-#define LP_UART_WAKEUP_INT_ST_M  (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S)
-#define LP_UART_WAKEUP_INT_ST_V  0x00000001U
-#define LP_UART_WAKEUP_INT_ST_S  19
-
-/** LP_UART_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc)
-/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  This is the enable bit for rxfifo_full_int_st register.
- */
-#define LP_UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_ENA_M  (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S)
-#define LP_UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_ENA_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  This is the enable bit for txfifo_empty_int_st register.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_M  (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S)
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_ENA_S  1
-/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  This is the enable bit for parity_err_int_st register.
- */
-#define LP_UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_ENA_M  (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S)
-#define LP_UART_PARITY_ERR_INT_ENA_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_ENA_S  2
-/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  This is the enable bit for frm_err_int_st register.
- */
-#define LP_UART_FRM_ERR_INT_ENA    (BIT(3))
-#define LP_UART_FRM_ERR_INT_ENA_M  (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S)
-#define LP_UART_FRM_ERR_INT_ENA_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_ENA_S  3
-/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  This is the enable bit for rxfifo_ovf_int_st register.
- */
-#define LP_UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_ENA_M  (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S)
-#define LP_UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_ENA_S  4
-/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for dsr_chg_int_st register.
- */
-#define LP_UART_DSR_CHG_INT_ENA    (BIT(5))
-#define LP_UART_DSR_CHG_INT_ENA_M  (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S)
-#define LP_UART_DSR_CHG_INT_ENA_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_ENA_S  5
-/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  This is the enable bit for cts_chg_int_st register.
- */
-#define LP_UART_CTS_CHG_INT_ENA    (BIT(6))
-#define LP_UART_CTS_CHG_INT_ENA_M  (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S)
-#define LP_UART_CTS_CHG_INT_ENA_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_ENA_S  6
-/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  This is the enable bit for brk_det_int_st register.
- */
-#define LP_UART_BRK_DET_INT_ENA    (BIT(7))
-#define LP_UART_BRK_DET_INT_ENA_M  (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S)
-#define LP_UART_BRK_DET_INT_ENA_V  0x00000001U
-#define LP_UART_BRK_DET_INT_ENA_S  7
-/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  This is the enable bit for rxfifo_tout_int_st register.
- */
-#define LP_UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_ENA_M  (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S)
-#define LP_UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_ENA_S  8
-/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  This is the enable bit for sw_xon_int_st register.
- */
-#define LP_UART_SW_XON_INT_ENA    (BIT(9))
-#define LP_UART_SW_XON_INT_ENA_M  (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S)
-#define LP_UART_SW_XON_INT_ENA_V  0x00000001U
-#define LP_UART_SW_XON_INT_ENA_S  9
-/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  This is the enable bit for sw_xoff_int_st register.
- */
-#define LP_UART_SW_XOFF_INT_ENA    (BIT(10))
-#define LP_UART_SW_XOFF_INT_ENA_M  (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S)
-#define LP_UART_SW_XOFF_INT_ENA_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_ENA_S  10
-/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  This is the enable bit for glitch_det_int_st register.
- */
-#define LP_UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_ENA_M  (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S)
-#define LP_UART_GLITCH_DET_INT_ENA_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_ENA_S  11
-/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for tx_brk_done_int_st register.
- */
-#define LP_UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_ENA_M  (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S)
-#define LP_UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_ENA_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit for tx_brk_idle_done_int_st register.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for tx_done_int_st register.
- */
-#define LP_UART_TX_DONE_INT_ENA    (BIT(14))
-#define LP_UART_TX_DONE_INT_ENA_M  (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S)
-#define LP_UART_TX_DONE_INT_ENA_V  0x00000001U
-#define LP_UART_TX_DONE_INT_ENA_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  This is the enable bit for at_cmd_char_det_int_st register.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M  (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for uart_wakeup_int_st register.
- */
-#define LP_UART_WAKEUP_INT_ENA    (BIT(19))
-#define LP_UART_WAKEUP_INT_ENA_M  (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S)
-#define LP_UART_WAKEUP_INT_ENA_V  0x00000001U
-#define LP_UART_WAKEUP_INT_ENA_S  19
-
-/** LP_UART_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10)
-/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the rxfifo_full_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define LP_UART_RXFIFO_FULL_INT_CLR_M  (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S)
-#define LP_UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_FULL_INT_CLR_S  0
-/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear txfifo_empty_int_raw interrupt.
- */
-#define LP_UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_M  (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S)
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
-#define LP_UART_TXFIFO_EMPTY_INT_CLR_S  1
-/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear parity_err_int_raw interrupt.
- */
-#define LP_UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define LP_UART_PARITY_ERR_INT_CLR_M  (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S)
-#define LP_UART_PARITY_ERR_INT_CLR_V  0x00000001U
-#define LP_UART_PARITY_ERR_INT_CLR_S  2
-/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear frm_err_int_raw interrupt.
- */
-#define LP_UART_FRM_ERR_INT_CLR    (BIT(3))
-#define LP_UART_FRM_ERR_INT_CLR_M  (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S)
-#define LP_UART_FRM_ERR_INT_CLR_V  0x00000001U
-#define LP_UART_FRM_ERR_INT_CLR_S  3
-/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define LP_UART_RXFIFO_OVF_INT_CLR_M  (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S)
-#define LP_UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_OVF_INT_CLR_S  4
-/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the dsr_chg_int_raw interrupt.
- */
-#define LP_UART_DSR_CHG_INT_CLR    (BIT(5))
-#define LP_UART_DSR_CHG_INT_CLR_M  (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S)
-#define LP_UART_DSR_CHG_INT_CLR_V  0x00000001U
-#define LP_UART_DSR_CHG_INT_CLR_S  5
-/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the cts_chg_int_raw interrupt.
- */
-#define LP_UART_CTS_CHG_INT_CLR    (BIT(6))
-#define LP_UART_CTS_CHG_INT_CLR_M  (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S)
-#define LP_UART_CTS_CHG_INT_CLR_V  0x00000001U
-#define LP_UART_CTS_CHG_INT_CLR_S  6
-/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the brk_det_int_raw interrupt.
- */
-#define LP_UART_BRK_DET_INT_CLR    (BIT(7))
-#define LP_UART_BRK_DET_INT_CLR_M  (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S)
-#define LP_UART_BRK_DET_INT_CLR_V  0x00000001U
-#define LP_UART_BRK_DET_INT_CLR_S  7
-/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
- */
-#define LP_UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define LP_UART_RXFIFO_TOUT_INT_CLR_M  (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S)
-#define LP_UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
-#define LP_UART_RXFIFO_TOUT_INT_CLR_S  8
-/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the sw_xon_int_raw interrupt.
- */
-#define LP_UART_SW_XON_INT_CLR    (BIT(9))
-#define LP_UART_SW_XON_INT_CLR_M  (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S)
-#define LP_UART_SW_XON_INT_CLR_V  0x00000001U
-#define LP_UART_SW_XON_INT_CLR_S  9
-/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the sw_xoff_int_raw interrupt.
- */
-#define LP_UART_SW_XOFF_INT_CLR    (BIT(10))
-#define LP_UART_SW_XOFF_INT_CLR_M  (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S)
-#define LP_UART_SW_XOFF_INT_CLR_V  0x00000001U
-#define LP_UART_SW_XOFF_INT_CLR_S  10
-/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the glitch_det_int_raw interrupt.
- */
-#define LP_UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define LP_UART_GLITCH_DET_INT_CLR_M  (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S)
-#define LP_UART_GLITCH_DET_INT_CLR_V  0x00000001U
-#define LP_UART_GLITCH_DET_INT_CLR_S  11
-/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the tx_brk_done_int_raw interrupt..
- */
-#define LP_UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define LP_UART_TX_BRK_DONE_INT_CLR_M  (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S)
-#define LP_UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_BRK_DONE_INT_CLR_S  12
-/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
- */
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M  (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S)
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the tx_done_int_raw interrupt.
- */
-#define LP_UART_TX_DONE_INT_CLR    (BIT(14))
-#define LP_UART_TX_DONE_INT_CLR_M  (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S)
-#define LP_UART_TX_DONE_INT_CLR_V  0x00000001U
-#define LP_UART_TX_DONE_INT_CLR_S  14
-/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
- */
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M  (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S)
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
-#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the uart_wakeup_int_raw interrupt.
- */
-#define LP_UART_WAKEUP_INT_CLR    (BIT(19))
-#define LP_UART_WAKEUP_INT_CLR_M  (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S)
-#define LP_UART_WAKEUP_INT_CLR_V  0x00000001U
-#define LP_UART_WAKEUP_INT_CLR_S  19
-
-/** LP_UART_CLKDIV_SYNC_REG register
- *  Clock divider configuration
- */
-#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14)
-/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
- *  The integral part of the frequency divider factor.
- */
-#define LP_UART_CLKDIV    0x00000FFFU
-#define LP_UART_CLKDIV_M  (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S)
-#define LP_UART_CLKDIV_V  0x00000FFFU
-#define LP_UART_CLKDIV_S  0
-/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
- *  The decimal part of the frequency divider factor.
- */
-#define LP_UART_CLKDIV_FRAG    0x0000000FU
-#define LP_UART_CLKDIV_FRAG_M  (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S)
-#define LP_UART_CLKDIV_FRAG_V  0x0000000FU
-#define LP_UART_CLKDIV_FRAG_S  20
-
-/** LP_UART_RX_FILT_REG register
- *  Rx Filter configuration
- */
-#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18)
-/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
- *  when input pulse width is lower than this value the pulse is ignored.
- */
-#define LP_UART_GLITCH_FILT    0x000000FFU
-#define LP_UART_GLITCH_FILT_M  (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S)
-#define LP_UART_GLITCH_FILT_V  0x000000FFU
-#define LP_UART_GLITCH_FILT_S  0
-/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable Rx signal filter.
- */
-#define LP_UART_GLITCH_FILT_EN    (BIT(8))
-#define LP_UART_GLITCH_FILT_EN_M  (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S)
-#define LP_UART_GLITCH_FILT_EN_V  0x00000001U
-#define LP_UART_GLITCH_FILT_EN_S  8
-
-/** LP_UART_STATUS_REG register
- *  UART status register
- */
-#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c)
-/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0;
- *  Stores the byte number of valid data in Rx-FIFO.
- */
-#define LP_UART_RXFIFO_CNT    0x0000001FU
-#define LP_UART_RXFIFO_CNT_M  (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S)
-#define LP_UART_RXFIFO_CNT_V  0x0000001FU
-#define LP_UART_RXFIFO_CNT_S  3
-/** LP_UART_DSRN : RO; bitpos: [13]; default: 0;
- *  The register represent the level value of the internal uart dsr signal.
- */
-#define LP_UART_DSRN    (BIT(13))
-#define LP_UART_DSRN_M  (LP_UART_DSRN_V << LP_UART_DSRN_S)
-#define LP_UART_DSRN_V  0x00000001U
-#define LP_UART_DSRN_S  13
-/** LP_UART_CTSN : RO; bitpos: [14]; default: 1;
- *  This register represent the level value of the internal uart cts signal.
- */
-#define LP_UART_CTSN    (BIT(14))
-#define LP_UART_CTSN_M  (LP_UART_CTSN_V << LP_UART_CTSN_S)
-#define LP_UART_CTSN_V  0x00000001U
-#define LP_UART_CTSN_S  14
-/** LP_UART_RXD : RO; bitpos: [15]; default: 1;
- *  This register represent the  level value of the internal uart rxd signal.
- */
-#define LP_UART_RXD    (BIT(15))
-#define LP_UART_RXD_M  (LP_UART_RXD_V << LP_UART_RXD_S)
-#define LP_UART_RXD_V  0x00000001U
-#define LP_UART_RXD_S  15
-/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0;
- *  Stores the byte number of data in Tx-FIFO.
- */
-#define LP_UART_TXFIFO_CNT    0x0000001FU
-#define LP_UART_TXFIFO_CNT_M  (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S)
-#define LP_UART_TXFIFO_CNT_V  0x0000001FU
-#define LP_UART_TXFIFO_CNT_S  19
-/** LP_UART_DTRN : RO; bitpos: [29]; default: 1;
- *  This bit represents the level of the internal uart dtr signal.
- */
-#define LP_UART_DTRN    (BIT(29))
-#define LP_UART_DTRN_M  (LP_UART_DTRN_V << LP_UART_DTRN_S)
-#define LP_UART_DTRN_V  0x00000001U
-#define LP_UART_DTRN_S  29
-/** LP_UART_RTSN : RO; bitpos: [30]; default: 1;
- *  This bit represents the level of the internal uart rts signal.
- */
-#define LP_UART_RTSN    (BIT(30))
-#define LP_UART_RTSN_M  (LP_UART_RTSN_V << LP_UART_RTSN_S)
-#define LP_UART_RTSN_V  0x00000001U
-#define LP_UART_RTSN_S  30
-/** LP_UART_TXD : RO; bitpos: [31]; default: 1;
- *  This bit represents the  level of the internal uart txd signal.
- */
-#define LP_UART_TXD    (BIT(31))
-#define LP_UART_TXD_M  (LP_UART_TXD_V << LP_UART_TXD_S)
-#define LP_UART_TXD_V  0x00000001U
-#define LP_UART_TXD_S  31
-
-/** LP_UART_CONF0_SYNC_REG register
- *  Configuration register 0
- */
-#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20)
-/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0;
- *  This register is used to configure the parity check mode.
- */
-#define LP_UART_PARITY    (BIT(0))
-#define LP_UART_PARITY_M  (LP_UART_PARITY_V << LP_UART_PARITY_S)
-#define LP_UART_PARITY_V  0x00000001U
-#define LP_UART_PARITY_S  0
-/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable uart parity check.
- */
-#define LP_UART_PARITY_EN    (BIT(1))
-#define LP_UART_PARITY_EN_M  (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S)
-#define LP_UART_PARITY_EN_V  0x00000001U
-#define LP_UART_PARITY_EN_S  1
-/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
- *  This register is used to set the length of data.
- */
-#define LP_UART_BIT_NUM    0x00000003U
-#define LP_UART_BIT_NUM_M  (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S)
-#define LP_UART_BIT_NUM_V  0x00000003U
-#define LP_UART_BIT_NUM_S  2
-/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
- *  This register is used to set the length of  stop bit.
- */
-#define LP_UART_STOP_BIT_NUM    0x00000003U
-#define LP_UART_STOP_BIT_NUM_M  (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S)
-#define LP_UART_STOP_BIT_NUM_V  0x00000003U
-#define LP_UART_STOP_BIT_NUM_S  4
-/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
- *  is done.
- */
-#define LP_UART_TXD_BRK    (BIT(6))
-#define LP_UART_TXD_BRK_M  (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S)
-#define LP_UART_TXD_BRK_V  0x00000001U
-#define LP_UART_TXD_BRK_S  6
-/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable uart loopback test mode.
- */
-#define LP_UART_LOOPBACK    (BIT(12))
-#define LP_UART_LOOPBACK_M  (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S)
-#define LP_UART_LOOPBACK_V  0x00000001U
-#define LP_UART_LOOPBACK_S  12
-/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
- *  Set this bit to enable flow control function for transmitter.
- */
-#define LP_UART_TX_FLOW_EN    (BIT(13))
-#define LP_UART_TX_FLOW_EN_M  (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S)
-#define LP_UART_TX_FLOW_EN_V  0x00000001U
-#define LP_UART_TX_FLOW_EN_S  13
-/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0;
- *  Set this bit to inverse the level value of uart rxd signal.
- */
-#define LP_UART_RXD_INV    (BIT(15))
-#define LP_UART_RXD_INV_M  (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S)
-#define LP_UART_RXD_INV_V  0x00000001U
-#define LP_UART_RXD_INV_S  15
-/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart txd signal.
- */
-#define LP_UART_TXD_INV    (BIT(16))
-#define LP_UART_TXD_INV_M  (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S)
-#define LP_UART_TXD_INV_V  0x00000001U
-#define LP_UART_TXD_INV_S  16
-/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
- *  Disable UART Rx data overflow detect.
- */
-#define LP_UART_DIS_RX_DAT_OVF    (BIT(17))
-#define LP_UART_DIS_RX_DAT_OVF_M  (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S)
-#define LP_UART_DIS_RX_DAT_OVF_V  0x00000001U
-#define LP_UART_DIS_RX_DAT_OVF_S  17
-/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
- *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
- *  stores the data even if the  received data is wrong.
- */
-#define LP_UART_ERR_WR_MASK    (BIT(18))
-#define LP_UART_ERR_WR_MASK_M  (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S)
-#define LP_UART_ERR_WR_MASK_V  0x00000001U
-#define LP_UART_ERR_WR_MASK_S  18
-/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
- *  UART memory clock gate enable signal.
- */
-#define LP_UART_MEM_CLK_EN    (BIT(20))
-#define LP_UART_MEM_CLK_EN_M  (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S)
-#define LP_UART_MEM_CLK_EN_V  0x00000001U
-#define LP_UART_MEM_CLK_EN_S  20
-/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0;
- *  This register is used to configure the software rts signal which is used in
- *  software flow control.
- */
-#define LP_UART_SW_RTS    (BIT(21))
-#define LP_UART_SW_RTS_M  (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S)
-#define LP_UART_SW_RTS_V  0x00000001U
-#define LP_UART_SW_RTS_S  21
-/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
- *  Set this bit to reset the uart receive-FIFO.
- */
-#define LP_UART_RXFIFO_RST    (BIT(22))
-#define LP_UART_RXFIFO_RST_M  (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S)
-#define LP_UART_RXFIFO_RST_V  0x00000001U
-#define LP_UART_RXFIFO_RST_S  22
-/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
- *  Set this bit to reset the uart transmit-FIFO.
- */
-#define LP_UART_TXFIFO_RST    (BIT(23))
-#define LP_UART_TXFIFO_RST_M  (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S)
-#define LP_UART_TXFIFO_RST_V  0x00000001U
-#define LP_UART_TXFIFO_RST_S  23
-
-/** LP_UART_CONF1_REG register
- *  Configuration register 1
- */
-#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24)
-/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12;
- *  It will produce rxfifo_full_int interrupt when receiver receives more data than
- *  this register value.
- */
-#define LP_UART_RXFIFO_FULL_THRHD    0x0000001FU
-#define LP_UART_RXFIFO_FULL_THRHD_M  (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S)
-#define LP_UART_RXFIFO_FULL_THRHD_V  0x0000001FU
-#define LP_UART_RXFIFO_FULL_THRHD_S  3
-/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12;
- *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
- *  than this register value.
- */
-#define LP_UART_TXFIFO_EMPTY_THRHD    0x0000001FU
-#define LP_UART_TXFIFO_EMPTY_THRHD_M  (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S)
-#define LP_UART_TXFIFO_EMPTY_THRHD_V  0x0000001FU
-#define LP_UART_TXFIFO_EMPTY_THRHD_S  11
-/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart cts signal.
- */
-#define LP_UART_CTS_INV    (BIT(16))
-#define LP_UART_CTS_INV_M  (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S)
-#define LP_UART_CTS_INV_V  0x00000001U
-#define LP_UART_CTS_INV_S  16
-/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0;
- *  Set this bit to inverse the level value of uart dsr signal.
- */
-#define LP_UART_DSR_INV    (BIT(17))
-#define LP_UART_DSR_INV_M  (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S)
-#define LP_UART_DSR_INV_V  0x00000001U
-#define LP_UART_DSR_INV_S  17
-/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0;
- *  Set this bit to inverse the level value of uart rts signal.
- */
-#define LP_UART_RTS_INV    (BIT(18))
-#define LP_UART_RTS_INV_M  (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S)
-#define LP_UART_RTS_INV_V  0x00000001U
-#define LP_UART_RTS_INV_S  18
-/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0;
- *  Set this bit to inverse the level value of uart dtr signal.
- */
-#define LP_UART_DTR_INV    (BIT(19))
-#define LP_UART_DTR_INV_M  (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S)
-#define LP_UART_DTR_INV_V  0x00000001U
-#define LP_UART_DTR_INV_S  19
-/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0;
- *  This register is used to configure the software dtr signal which is used in
- *  software flow control.
- */
-#define LP_UART_SW_DTR    (BIT(20))
-#define LP_UART_SW_DTR_M  (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S)
-#define LP_UART_SW_DTR_V  0x00000001U
-#define LP_UART_SW_DTR_S  20
-/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define LP_UART_CLK_EN    (BIT(21))
-#define LP_UART_CLK_EN_M  (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S)
-#define LP_UART_CLK_EN_V  0x00000001U
-#define LP_UART_CLK_EN_S  21
-
-/** LP_UART_HWFC_CONF_SYNC_REG register
- *  Hardware flow-control configuration
- */
-#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c)
-/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0;
- *  This register is used to configure the maximum amount of data that can be received
- *  when hardware flow control works.
- */
-#define LP_UART_RX_FLOW_THRHD    0x0000001FU
-#define LP_UART_RX_FLOW_THRHD_M  (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S)
-#define LP_UART_RX_FLOW_THRHD_V  0x0000001FU
-#define LP_UART_RX_FLOW_THRHD_S  3
-/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
- *  This is the flow enable bit for UART receiver.
- */
-#define LP_UART_RX_FLOW_EN    (BIT(8))
-#define LP_UART_RX_FLOW_EN_M  (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S)
-#define LP_UART_RX_FLOW_EN_V  0x00000001U
-#define LP_UART_RX_FLOW_EN_S  8
-
-/** LP_UART_SLEEP_CONF0_REG register
- *  UART sleep configure register 0
- */
-#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30)
-/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified wake up char1 to wake up
- */
-#define LP_UART_WK_CHAR1    0x000000FFU
-#define LP_UART_WK_CHAR1_M  (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S)
-#define LP_UART_WK_CHAR1_V  0x000000FFU
-#define LP_UART_WK_CHAR1_S  0
-/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
- *  This register restores the specified wake up char2 to wake up
- */
-#define LP_UART_WK_CHAR2    0x000000FFU
-#define LP_UART_WK_CHAR2_M  (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S)
-#define LP_UART_WK_CHAR2_V  0x000000FFU
-#define LP_UART_WK_CHAR2_S  8
-/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
- *  This register restores the specified wake up char3 to wake up
- */
-#define LP_UART_WK_CHAR3    0x000000FFU
-#define LP_UART_WK_CHAR3_M  (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S)
-#define LP_UART_WK_CHAR3_V  0x000000FFU
-#define LP_UART_WK_CHAR3_S  16
-/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
- *  This register restores the specified wake up char4 to wake up
- */
-#define LP_UART_WK_CHAR4    0x000000FFU
-#define LP_UART_WK_CHAR4_M  (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S)
-#define LP_UART_WK_CHAR4_V  0x000000FFU
-#define LP_UART_WK_CHAR4_S  24
-
-/** LP_UART_SLEEP_CONF1_REG register
- *  UART sleep configure register 1
- */
-#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34)
-/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified char0 to wake up
- */
-#define LP_UART_WK_CHAR0    0x000000FFU
-#define LP_UART_WK_CHAR0_M  (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S)
-#define LP_UART_WK_CHAR0_V  0x000000FFU
-#define LP_UART_WK_CHAR0_S  0
-
-/** LP_UART_SLEEP_CONF2_REG register
- *  UART sleep configure register 2
- */
-#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38)
-/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
- *  The uart is activated from light sleeping mode when the input rxd edge changes more
- *  times than this register value.
- */
-#define LP_UART_ACTIVE_THRESHOLD    0x000003FFU
-#define LP_UART_ACTIVE_THRESHOLD_M  (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S)
-#define LP_UART_ACTIVE_THRESHOLD_V  0x000003FFU
-#define LP_UART_ACTIVE_THRESHOLD_S  0
-/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1;
- *  In wake up mode 1 this field is used to set the received data number threshold to
- *  wake up chip.
- */
-#define LP_UART_RX_WAKE_UP_THRHD    0x0000001FU
-#define LP_UART_RX_WAKE_UP_THRHD_M  (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S)
-#define LP_UART_RX_WAKE_UP_THRHD_V  0x0000001FU
-#define LP_UART_RX_WAKE_UP_THRHD_S  13
-/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
- *  This register is used to select number of wake up char.
- */
-#define LP_UART_WK_CHAR_NUM    0x00000007U
-#define LP_UART_WK_CHAR_NUM_M  (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S)
-#define LP_UART_WK_CHAR_NUM_V  0x00000007U
-#define LP_UART_WK_CHAR_NUM_S  18
-/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
- *  This register is used to mask  wake up char.
- */
-#define LP_UART_WK_CHAR_MASK    0x0000001FU
-#define LP_UART_WK_CHAR_MASK_M  (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S)
-#define LP_UART_WK_CHAR_MASK_V  0x0000001FU
-#define LP_UART_WK_CHAR_MASK_S  21
-/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
- *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
- *  received data number larger than
- */
-#define LP_UART_WK_MODE_SEL    0x00000003U
-#define LP_UART_WK_MODE_SEL_M  (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S)
-#define LP_UART_WK_MODE_SEL_V  0x00000003U
-#define LP_UART_WK_MODE_SEL_S  26
-
-/** LP_UART_SWFC_CONF0_SYNC_REG register
- *  Software flow-control character configuration
- */
-#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c)
-/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
- *  This register stores the Xon flow control char.
- */
-#define LP_UART_XON_CHAR    0x000000FFU
-#define LP_UART_XON_CHAR_M  (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S)
-#define LP_UART_XON_CHAR_V  0x000000FFU
-#define LP_UART_XON_CHAR_S  0
-/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
- *  This register stores the Xoff flow control char.
- */
-#define LP_UART_XOFF_CHAR    0x000000FFU
-#define LP_UART_XOFF_CHAR_M  (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S)
-#define LP_UART_XOFF_CHAR_V  0x000000FFU
-#define LP_UART_XOFF_CHAR_S  8
-/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
- *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
- *  this status, UART Tx can not transmit XOFF even the received data number is larger
- *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
- *  UART Tx is disabled.
- */
-#define LP_UART_XON_XOFF_STILL_SEND    (BIT(16))
-#define LP_UART_XON_XOFF_STILL_SEND_M  (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S)
-#define LP_UART_XON_XOFF_STILL_SEND_V  0x00000001U
-#define LP_UART_XON_XOFF_STILL_SEND_S  16
-/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
- *  Set this bit to enable software flow control. It is used with register sw_xon or
- *  sw_xoff.
- */
-#define LP_UART_SW_FLOW_CON_EN    (BIT(17))
-#define LP_UART_SW_FLOW_CON_EN_M  (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S)
-#define LP_UART_SW_FLOW_CON_EN_V  0x00000001U
-#define LP_UART_SW_FLOW_CON_EN_S  17
-/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
- *  Set this bit to remove flow control char from the received data.
- */
-#define LP_UART_XONOFF_DEL    (BIT(18))
-#define LP_UART_XONOFF_DEL_M  (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S)
-#define LP_UART_XONOFF_DEL_V  0x00000001U
-#define LP_UART_XONOFF_DEL_S  18
-/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
- *  Set this bit to enable the transmitter to go on sending data.
- */
-#define LP_UART_FORCE_XON    (BIT(19))
-#define LP_UART_FORCE_XON_M  (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S)
-#define LP_UART_FORCE_XON_V  0x00000001U
-#define LP_UART_FORCE_XON_S  19
-/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
- *  Set this bit to stop the  transmitter from sending data.
- */
-#define LP_UART_FORCE_XOFF    (BIT(20))
-#define LP_UART_FORCE_XOFF_M  (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S)
-#define LP_UART_FORCE_XOFF_V  0x00000001U
-#define LP_UART_FORCE_XOFF_S  20
-/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
- *  Set this bit to send Xon char. It is cleared by hardware automatically.
- */
-#define LP_UART_SEND_XON    (BIT(21))
-#define LP_UART_SEND_XON_M  (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S)
-#define LP_UART_SEND_XON_V  0x00000001U
-#define LP_UART_SEND_XON_S  21
-/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
- *  Set this bit to send Xoff char. It is cleared by hardware automatically.
- */
-#define LP_UART_SEND_XOFF    (BIT(22))
-#define LP_UART_SEND_XOFF_M  (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S)
-#define LP_UART_SEND_XOFF_V  0x00000001U
-#define LP_UART_SEND_XOFF_S  22
-
-/** LP_UART_SWFC_CONF1_REG register
- *  Software flow-control character configuration
- */
-#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40)
-/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0;
- *  When the data amount in Rx-FIFO is less than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xon char.
- */
-#define LP_UART_XON_THRESHOLD    0x0000001FU
-#define LP_UART_XON_THRESHOLD_M  (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S)
-#define LP_UART_XON_THRESHOLD_V  0x0000001FU
-#define LP_UART_XON_THRESHOLD_S  3
-/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12;
- *  When the data amount in Rx-FIFO is more than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
- */
-#define LP_UART_XOFF_THRESHOLD    0x0000001FU
-#define LP_UART_XOFF_THRESHOLD_M  (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S)
-#define LP_UART_XOFF_THRESHOLD_V  0x0000001FU
-#define LP_UART_XOFF_THRESHOLD_S  11
-
-/** LP_UART_TXBRK_CONF_SYNC_REG register
- *  Tx Break character configuration
- */
-#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44)
-/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
- *  This register is used to configure the number of 0 to be sent after the process of
- *  sending data is done. It is active when txd_brk is set to 1.
- */
-#define LP_UART_TX_BRK_NUM    0x000000FFU
-#define LP_UART_TX_BRK_NUM_M  (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S)
-#define LP_UART_TX_BRK_NUM_V  0x000000FFU
-#define LP_UART_TX_BRK_NUM_S  0
-
-/** LP_UART_IDLE_CONF_SYNC_REG register
- *  Frame-end idle configuration
- */
-#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48)
-/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
- *  It will produce frame end signal when receiver takes more time to receive one byte
- *  data than this register value.
- */
-#define LP_UART_RX_IDLE_THRHD    0x000003FFU
-#define LP_UART_RX_IDLE_THRHD_M  (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S)
-#define LP_UART_RX_IDLE_THRHD_V  0x000003FFU
-#define LP_UART_RX_IDLE_THRHD_S  0
-/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
- *  This register is used to configure the duration time between transfers.
- */
-#define LP_UART_TX_IDLE_NUM    0x000003FFU
-#define LP_UART_TX_IDLE_NUM_M  (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S)
-#define LP_UART_TX_IDLE_NUM_V  0x000003FFU
-#define LP_UART_TX_IDLE_NUM_S  10
-
-/** LP_UART_RS485_CONF_SYNC_REG register
- *  RS485 mode configuration
- */
-#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c)
-/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define LP_UART_DL0_EN    (BIT(1))
-#define LP_UART_DL0_EN_M  (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S)
-#define LP_UART_DL0_EN_V  0x00000001U
-#define LP_UART_DL0_EN_S  1
-/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define LP_UART_DL1_EN    (BIT(2))
-#define LP_UART_DL1_EN_M  (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S)
-#define LP_UART_DL1_EN_V  0x00000001U
-#define LP_UART_DL1_EN_S  2
-
-/** LP_UART_AT_CMD_PRECNT_SYNC_REG register
- *  Pre-sequence timing configuration
- */
-#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50)
-/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the idle duration time before the first at_cmd
- *  is received by receiver.
- */
-#define LP_UART_PRE_IDLE_NUM    0x0000FFFFU
-#define LP_UART_PRE_IDLE_NUM_M  (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S)
-#define LP_UART_PRE_IDLE_NUM_V  0x0000FFFFU
-#define LP_UART_PRE_IDLE_NUM_S  0
-
-/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register
- *  Post-sequence timing configuration
- */
-#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54)
-/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the duration time between the last at_cmd and
- *  the next data.
- */
-#define LP_UART_POST_IDLE_NUM    0x0000FFFFU
-#define LP_UART_POST_IDLE_NUM_M  (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S)
-#define LP_UART_POST_IDLE_NUM_V  0x0000FFFFU
-#define LP_UART_POST_IDLE_NUM_S  0
-
-/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register
- *  Timeout configuration
- */
-#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58)
-/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
- *  This register is used to configure the duration time between the at_cmd chars.
- */
-#define LP_UART_RX_GAP_TOUT    0x0000FFFFU
-#define LP_UART_RX_GAP_TOUT_M  (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S)
-#define LP_UART_RX_GAP_TOUT_V  0x0000FFFFU
-#define LP_UART_RX_GAP_TOUT_S  0
-
-/** LP_UART_AT_CMD_CHAR_SYNC_REG register
- *  AT escape sequence detection configuration
- */
-#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c)
-/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
- *  This register is used to configure the content of at_cmd char.
- */
-#define LP_UART_AT_CMD_CHAR    0x000000FFU
-#define LP_UART_AT_CMD_CHAR_M  (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S)
-#define LP_UART_AT_CMD_CHAR_V  0x000000FFU
-#define LP_UART_AT_CMD_CHAR_S  0
-/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
- *  This register is used to configure the num of continuous at_cmd chars received by
- *  receiver.
- */
-#define LP_UART_CHAR_NUM    0x000000FFU
-#define LP_UART_CHAR_NUM_M  (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S)
-#define LP_UART_CHAR_NUM_V  0x000000FFU
-#define LP_UART_CHAR_NUM_S  8
-
-/** LP_UART_MEM_CONF_REG register
- *  UART memory power configuration
- */
-#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60)
-/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
- *  Set this bit to force power down UART memory.
- */
-#define LP_UART_MEM_FORCE_PD    (BIT(25))
-#define LP_UART_MEM_FORCE_PD_M  (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S)
-#define LP_UART_MEM_FORCE_PD_V  0x00000001U
-#define LP_UART_MEM_FORCE_PD_S  25
-/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
- *  Set this bit to force power up UART memory.
- */
-#define LP_UART_MEM_FORCE_PU    (BIT(26))
-#define LP_UART_MEM_FORCE_PU_M  (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S)
-#define LP_UART_MEM_FORCE_PU_V  0x00000001U
-#define LP_UART_MEM_FORCE_PU_S  26
-
-/** LP_UART_TOUT_CONF_SYNC_REG register
- *  UART threshold and allocation configuration
- */
-#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
-/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
- */
-#define LP_UART_RX_TOUT_EN    (BIT(0))
-#define LP_UART_RX_TOUT_EN_M  (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)
-#define LP_UART_RX_TOUT_EN_V  0x00000001U
-#define LP_UART_RX_TOUT_EN_S  0
-/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
- *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
- */
-#define LP_UART_RX_TOUT_FLOW_DIS    (BIT(1))
-#define LP_UART_RX_TOUT_FLOW_DIS_M  (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S)
-#define LP_UART_RX_TOUT_FLOW_DIS_V  0x00000001U
-#define LP_UART_RX_TOUT_FLOW_DIS_S  1
-/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
- *  This register is used to configure the threshold time that receiver takes to
- *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
- *  takes more time to receive one byte with rx_tout_en set to 1.
- */
-#define LP_UART_RX_TOUT_THRHD    0x000003FFU
-#define LP_UART_RX_TOUT_THRHD_M  (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S)
-#define LP_UART_RX_TOUT_THRHD_V  0x000003FFU
-#define LP_UART_RX_TOUT_THRHD_S  2
-
-/** LP_UART_MEM_TX_STATUS_REG register
- *  Tx-SRAM write and read offset address.
- */
-#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68)
-/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0;
- *  This register stores the offset write address in Tx-SRAM.
- */
-#define LP_UART_TX_SRAM_WADDR    0x0000001FU
-#define LP_UART_TX_SRAM_WADDR_M  (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S)
-#define LP_UART_TX_SRAM_WADDR_V  0x0000001FU
-#define LP_UART_TX_SRAM_WADDR_S  3
-/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0;
- *  This register stores the offset read address in Tx-SRAM.
- */
-#define LP_UART_TX_SRAM_RADDR    0x0000001FU
-#define LP_UART_TX_SRAM_RADDR_M  (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S)
-#define LP_UART_TX_SRAM_RADDR_V  0x0000001FU
-#define LP_UART_TX_SRAM_RADDR_S  12
-
-/** LP_UART_MEM_RX_STATUS_REG register
- *  Rx-SRAM write and read offset address.
- */
-#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c)
-/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16;
- *  This register stores the offset read address in RX-SRAM.
- */
-#define LP_UART_RX_SRAM_RADDR    0x0000001FU
-#define LP_UART_RX_SRAM_RADDR_M  (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S)
-#define LP_UART_RX_SRAM_RADDR_V  0x0000001FU
-#define LP_UART_RX_SRAM_RADDR_S  3
-/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16;
- *  This register stores the offset write address in Rx-SRAM.
- */
-#define LP_UART_RX_SRAM_WADDR    0x0000001FU
-#define LP_UART_RX_SRAM_WADDR_M  (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S)
-#define LP_UART_RX_SRAM_WADDR_V  0x0000001FU
-#define LP_UART_RX_SRAM_WADDR_S  12
-
-/** LP_UART_FSM_STATUS_REG register
- *  UART transmit and receive status.
- */
-#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70)
-/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
- *  This is the status register of receiver.
- */
-#define LP_UART_ST_URX_OUT    0x0000000FU
-#define LP_UART_ST_URX_OUT_M  (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S)
-#define LP_UART_ST_URX_OUT_V  0x0000000FU
-#define LP_UART_ST_URX_OUT_S  0
-/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
- *  This is the status register of transmitter.
- */
-#define LP_UART_ST_UTX_OUT    0x0000000FU
-#define LP_UART_ST_UTX_OUT_M  (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S)
-#define LP_UART_ST_UTX_OUT_V  0x0000000FU
-#define LP_UART_ST_UTX_OUT_S  4
-
-/** LP_UART_CLK_CONF_REG register
- *  UART core clock configuration
- */
-#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
-/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
- *  Set this bit to enable UART Tx clock.
- */
-#define LP_UART_TX_SCLK_EN    (BIT(24))
-#define LP_UART_TX_SCLK_EN_M  (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S)
-#define LP_UART_TX_SCLK_EN_V  0x00000001U
-#define LP_UART_TX_SCLK_EN_S  24
-/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
- *  Set this bit to enable UART Rx clock.
- */
-#define LP_UART_RX_SCLK_EN    (BIT(25))
-#define LP_UART_RX_SCLK_EN_M  (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S)
-#define LP_UART_RX_SCLK_EN_V  0x00000001U
-#define LP_UART_RX_SCLK_EN_S  25
-/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Tx.
- */
-#define LP_UART_TX_RST_CORE    (BIT(26))
-#define LP_UART_TX_RST_CORE_M  (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S)
-#define LP_UART_TX_RST_CORE_V  0x00000001U
-#define LP_UART_TX_RST_CORE_S  26
-/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Rx.
- */
-#define LP_UART_RX_RST_CORE    (BIT(27))
-#define LP_UART_RX_RST_CORE_M  (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S)
-#define LP_UART_RX_RST_CORE_V  0x00000001U
-#define LP_UART_RX_RST_CORE_S  27
-
-/** LP_UART_DATE_REG register
- *  UART Version register
- */
-#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c)
-/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 36720720;
- *  This is the version register.
- */
-#define LP_UART_DATE    0xFFFFFFFFU
-#define LP_UART_DATE_M  (LP_UART_DATE_V << LP_UART_DATE_S)
-#define LP_UART_DATE_V  0xFFFFFFFFU
-#define LP_UART_DATE_S  0
-
-/** LP_UART_AFIFO_STATUS_REG register
- *  UART AFIFO Status
- */
-#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90)
-/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
- *  Full signal of APB TX AFIFO.
- */
-#define LP_UART_TX_AFIFO_FULL    (BIT(0))
-#define LP_UART_TX_AFIFO_FULL_M  (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S)
-#define LP_UART_TX_AFIFO_FULL_V  0x00000001U
-#define LP_UART_TX_AFIFO_FULL_S  0
-/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
- *  Empty signal of APB TX AFIFO.
- */
-#define LP_UART_TX_AFIFO_EMPTY    (BIT(1))
-#define LP_UART_TX_AFIFO_EMPTY_M  (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S)
-#define LP_UART_TX_AFIFO_EMPTY_V  0x00000001U
-#define LP_UART_TX_AFIFO_EMPTY_S  1
-/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
- *  Full signal of APB RX AFIFO.
- */
-#define LP_UART_RX_AFIFO_FULL    (BIT(2))
-#define LP_UART_RX_AFIFO_FULL_M  (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S)
-#define LP_UART_RX_AFIFO_FULL_V  0x00000001U
-#define LP_UART_RX_AFIFO_FULL_S  2
-/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
- *  Empty signal of APB RX AFIFO.
- */
-#define LP_UART_RX_AFIFO_EMPTY    (BIT(3))
-#define LP_UART_RX_AFIFO_EMPTY_M  (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S)
-#define LP_UART_RX_AFIFO_EMPTY_V  0x00000001U
-#define LP_UART_RX_AFIFO_EMPTY_S  3
-
-/** LP_UART_REG_UPDATE_REG register
- *  UART Registers Configuration Update register
- */
-#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98)
-/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
- *  Software write 1 would synchronize registers into UART Core clock domain and would
- *  be cleared by hardware after synchronization is done.
- */
-#define LP_UART_REG_UPDATE    (BIT(0))
-#define LP_UART_REG_UPDATE_M  (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S)
-#define LP_UART_REG_UPDATE_V  0x00000001U
-#define LP_UART_REG_UPDATE_S  0
-
-/** LP_UART_ID_REG register
- *  UART ID register
- */
-#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c)
-/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280;
- *  This register is used to configure the uart_id.
- */
-#define LP_UART_ID    0xFFFFFFFFU
-#define LP_UART_ID_M  (LP_UART_ID_V << LP_UART_ID_S)
-#define LP_UART_ID_V  0xFFFFFFFFU
-#define LP_UART_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/lp_uart_struct.h b/components/soc/esp32p4/include/soc/lp_uart_struct.h
deleted file mode 100644
index 5bd4d605c0b..00000000000
--- a/components/soc/esp32p4/include/soc/lp_uart_struct.h
+++ /dev/null
@@ -1,1103 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
-         *  UART $n accesses FIFO via this register.
-         */
-        uint32_t rxfifo_rd_byte:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} lp_uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  This register is used to configure the threshold time that receiver takes to
-         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
-         *  takes more time to receive one byte with rx_tout_en set to 1.
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} lp_uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  what rxfifo_full_thrhd specifies.
-         */
-        uint32_t rxfifo_full_int_raw:1;
-        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
-         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-         *  less than what txfifo_empty_thrhd specifies .
-         */
-        uint32_t txfifo_empty_int_raw:1;
-        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error in
-         *  the data.
-         */
-        uint32_t parity_err_int_raw:1;
-        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  .
-         */
-        uint32_t frm_err_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  the FIFO can store.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  DSRn signal.
-         */
-        uint32_t dsr_chg_int_raw:1;
-        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  CTSn signal.
-         */
-        uint32_t cts_chg_int_raw:1;
-        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
-         *  bit.
-         */
-        uint32_t brk_det_int_raw:1;
-        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver takes more time than
-         *  rx_tout_thrhd to receive a byte.
-         */
-        uint32_t rxfifo_tout_int_raw:1;
-        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xon_int_raw:1;
-        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xoff_int_raw:1;
-        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
-         *  middle of a start bit.
-         */
-        uint32_t glitch_det_int_raw:1;
-        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter completes  sending
-         *  NULL characters after all data in Tx-FIFO are sent.
-         */
-        uint32_t tx_brk_done_int_raw:1;
-        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
-         *  duration after sending the  last data.
-         */
-        uint32_t tx_brk_idle_done_int_raw:1;
-        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has send out all data
-         *  in FIFO.
-         */
-        uint32_t tx_done_int_raw:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the configured
-         *  at_cmd char.
-         */
-        uint32_t at_cmd_char_det_int_raw:1;
-        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  This interrupt raw bit turns to high level when input rxd edge changes more times
-         *  than what reg_active_threshold specifies in light sleeping mode.
-         */
-        uint32_t wakeup_int_raw:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
-         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-         */
-        uint32_t rxfifo_full_int_st:1;
-        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
-         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
-         *  to 1.
-         */
-        uint32_t txfifo_empty_int_st:1;
-        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
-         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-         */
-        uint32_t parity_err_int_st:1;
-        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
-         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-         */
-        uint32_t frm_err_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
-         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-         */
-        uint32_t dsr_chg_int_st:1;
-        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
-         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-         */
-        uint32_t cts_chg_int_st:1;
-        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
-         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-         */
-        uint32_t brk_det_int_st:1;
-        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
-         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-         */
-        uint32_t rxfifo_tout_int_st:1;
-        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
-         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-         */
-        uint32_t sw_xon_int_st:1;
-        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
-         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-         */
-        uint32_t sw_xoff_int_st:1;
-        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
-         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-         */
-        uint32_t glitch_det_int_st:1;
-        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
-         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-         */
-        uint32_t tx_brk_done_int_st:1;
-        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
-         *  is set to 1.
-         */
-        uint32_t tx_brk_idle_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-         */
-        uint32_t tx_done_int_st:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
-         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
-         *  to 1.
-         */
-        uint32_t at_cmd_char_det_int_st:1;
-        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
-         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-         */
-        uint32_t wakeup_int_st:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
-         *  This is the enable bit for rxfifo_full_int_st register.
-         */
-        uint32_t rxfifo_full_int_ena:1;
-        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
-         *  This is the enable bit for txfifo_empty_int_st register.
-         */
-        uint32_t txfifo_empty_int_ena:1;
-        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
-         *  This is the enable bit for parity_err_int_st register.
-         */
-        uint32_t parity_err_int_ena:1;
-        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
-         *  This is the enable bit for frm_err_int_st register.
-         */
-        uint32_t frm_err_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  This is the enable bit for rxfifo_ovf_int_st register.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for dsr_chg_int_st register.
-         */
-        uint32_t dsr_chg_int_ena:1;
-        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
-         *  This is the enable bit for cts_chg_int_st register.
-         */
-        uint32_t cts_chg_int_ena:1;
-        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
-         *  This is the enable bit for brk_det_int_st register.
-         */
-        uint32_t brk_det_int_ena:1;
-        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
-         *  This is the enable bit for rxfifo_tout_int_st register.
-         */
-        uint32_t rxfifo_tout_int_ena:1;
-        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
-         *  This is the enable bit for sw_xon_int_st register.
-         */
-        uint32_t sw_xon_int_ena:1;
-        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
-         *  This is the enable bit for sw_xoff_int_st register.
-         */
-        uint32_t sw_xoff_int_ena:1;
-        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
-         *  This is the enable bit for glitch_det_int_st register.
-         */
-        uint32_t glitch_det_int_ena:1;
-        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for tx_brk_done_int_st register.
-         */
-        uint32_t tx_brk_done_int_ena:1;
-        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit for tx_brk_idle_done_int_st register.
-         */
-        uint32_t tx_brk_idle_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for tx_done_int_st register.
-         */
-        uint32_t tx_done_int_ena:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
-         *  This is the enable bit for at_cmd_char_det_int_st register.
-         */
-        uint32_t at_cmd_char_det_int_ena:1;
-        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for uart_wakeup_int_st register.
-         */
-        uint32_t wakeup_int_ena:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
-         */
-        uint32_t rxfifo_full_int_clr:1;
-        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear txfifo_empty_int_raw interrupt.
-         */
-        uint32_t txfifo_empty_int_clr:1;
-        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear parity_err_int_raw interrupt.
-         */
-        uint32_t parity_err_int_clr:1;
-        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear frm_err_int_raw interrupt.
-         */
-        uint32_t frm_err_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the dsr_chg_int_raw interrupt.
-         */
-        uint32_t dsr_chg_int_clr:1;
-        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the cts_chg_int_raw interrupt.
-         */
-        uint32_t cts_chg_int_clr:1;
-        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the brk_det_int_raw interrupt.
-         */
-        uint32_t brk_det_int_clr:1;
-        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-         */
-        uint32_t rxfifo_tout_int_clr:1;
-        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the sw_xon_int_raw interrupt.
-         */
-        uint32_t sw_xon_int_clr:1;
-        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the sw_xoff_int_raw interrupt.
-         */
-        uint32_t sw_xoff_int_clr:1;
-        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the glitch_det_int_raw interrupt.
-         */
-        uint32_t glitch_det_int_clr:1;
-        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
-         */
-        uint32_t tx_brk_done_int_clr:1;
-        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-         */
-        uint32_t tx_brk_idle_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the tx_done_int_raw interrupt.
-         */
-        uint32_t tx_done_int_clr:1;
-        uint32_t reserved_15:3;
-        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-         */
-        uint32_t at_cmd_char_det_int_clr:1;
-        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
-         */
-        uint32_t wakeup_int_clr:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t clkdiv:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  The decimal part of the frequency divider factor.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lp_uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  Rx Filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  when input pulse width is lower than this value the pulse is ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable Rx signal filter.
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  Configuration register 0
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  This register is used to configure the parity check mode.
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable uart parity check.
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  This register is used to set the length of data.
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  This register is used to set the length of  stop bit.
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
-         *  is done.
-         */
-        uint32_t txd_brk:1;
-        uint32_t reserved_7:5;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable uart loopback test mode.
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to enable flow control function for transmitter.
-         */
-        uint32_t tx_flow_en:1;
-        uint32_t reserved_14:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Set this bit to inverse the level value of uart rxd signal.
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart txd signal.
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Disable UART Rx data overflow detect.
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-         *  stores the data even if the  received data is wrong.
-         */
-        uint32_t err_wr_mask:1;
-        uint32_t reserved_19:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
-         *  UART memory clock gate enable signal.
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  This register is used to configure the software rts signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Set this bit to reset the uart receive-FIFO.
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Set this bit to reset the uart transmit-FIFO.
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lp_uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12;
-         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
-         *  this register value.
-         */
-        uint32_t rxfifo_full_thrhd:5;
-        uint32_t reserved_8:3;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12;
-         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
-         *  than this register value.
-         */
-        uint32_t txfifo_empty_thrhd:5;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart cts signal.
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to inverse the level value of uart dsr signal.
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to inverse the level value of uart rts signal.
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to inverse the level value of uart dtr signal.
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  This register is used to configure the software dtr signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} lp_uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow-control configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0;
-         *  This register is used to configure the maximum amount of data that can be received
-         *  when hardware flow control works.
-         */
-        uint32_t rx_flow_thrhd:5;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  This is the flow enable bit for UART receiver.
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} lp_uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configure register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified wake up char1 to wake up
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  This register restores the specified wake up char2 to wake up
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  This register restores the specified wake up char3 to wake up
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  This register restores the specified wake up char4 to wake up
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configure register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified char0 to wake up
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configure register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  The uart is activated from light sleeping mode when the input rxd edge changes more
-         *  times than this register value.
-         */
-        uint32_t active_threshold:10;
-        uint32_t reserved_10:3;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1;
-         *  In wake up mode 1 this field is used to set the received data number threshold to
-         *  wake up chip.
-         */
-        uint32_t rx_wake_up_thrhd:5;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  This register is used to select number of wake up char.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  This register is used to mask  wake up char.
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
-         *  received data number larger than
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  This register stores the Xon flow control char.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  This register stores the Xoff flow control char.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
-         *  this status, UART Tx can not transmit XOFF even the received data number is larger
-         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
-         *  UART Tx is disabled.
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to enable software flow control. It is used with register sw_xon or
-         *  sw_xoff.
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to remove flow control char from the received data.
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to enable the transmitter to go on sending data.
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Set this bit to stop the  transmitter from sending data.
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Set this bit to send Xon char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} lp_uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** xon_threshold : R/W; bitpos: [7:3]; default: 0;
-         *  When the data amount in Rx-FIFO is less than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
-         */
-        uint32_t xon_threshold:5;
-        uint32_t reserved_8:3;
-        /** xoff_threshold : R/W; bitpos: [15:11]; default: 12;
-         *  When the data amount in Rx-FIFO is more than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
-         */
-        uint32_t xoff_threshold:5;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  Tx Break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  This register is used to configure the number of 0 to be sent after the process of
-         *  sending data is done. It is active when txd_brk is set to 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame-end idle configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  It will produce frame end signal when receiver takes more time to receive one byte
-         *  data than this register value.
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  This register is used to configure the duration time between transfers.
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} lp_uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl1_en:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} lp_uart_rs485_conf_sync_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Set this bit to enable UART Tx clock.
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Set this bit to enable UART Rx clock.
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Rx.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lp_uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0;
-         *  Stores the byte number of valid data in Rx-FIFO.
-         */
-        uint32_t rxfifo_cnt:5;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  The register represent the level value of the internal uart dsr signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  This register represent the level value of the internal uart cts signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  This register represent the  level value of the internal uart rxd signal.
-         */
-        uint32_t rxd:1;
-        uint32_t reserved_16:3;
-        /** txfifo_cnt : RO; bitpos: [23:19]; default: 0;
-         *  Stores the byte number of data in Tx-FIFO.
-         */
-        uint32_t txfifo_cnt:5;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  This bit represents the level of the internal uart dtr signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  This bit represents the level of the internal uart rts signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  This bit represents the  level of the internal uart txd signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} lp_uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  Tx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0;
-         *  This register stores the offset write address in Tx-SRAM.
-         */
-        uint32_t tx_sram_waddr:5;
-        uint32_t reserved_8:4;
-        /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0;
-         *  This register stores the offset read address in Tx-SRAM.
-         */
-        uint32_t tx_sram_raddr:5;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16;
-         *  This register stores the offset read address in RX-SRAM.
-         */
-        uint32_t rx_sram_raddr:5;
-        uint32_t reserved_8:4;
-        /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16;
-         *  This register stores the offset write address in Rx-SRAM.
-         */
-        uint32_t rx_sram_waddr:5;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} lp_uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status.
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  This is the status register of receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  This is the status register of transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} lp_uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART AFIFO Status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Full signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Empty signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Full signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Empty signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} lp_uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the idle duration time before the first at_cmd
-         *  is received by receiver.
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the duration time between the last at_cmd and
-         *  the next data.
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  This register is used to configure the duration time between the at_cmd chars.
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
-         *  This register is used to configure the content of at_cmd char.
-         */
-        uint32_t at_cmd_char:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  This register is used to configure the num of continuous at_cmd chars received by
-         *  receiver.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} lp_uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 36720720;
-         *  This is the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} lp_uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART Registers Configuration Update register
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Software write 1 would synchronize registers into UART Core clock domain and would
-         *  be cleared by hardware after synchronization is done.
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} lp_uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  This register is used to configure the uart_id.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} lp_uart_id_reg_t;
-
-
-typedef struct {
-    volatile lp_uart_fifo_reg_t fifo;
-    volatile lp_uart_int_raw_reg_t int_raw;
-    volatile lp_uart_int_st_reg_t int_st;
-    volatile lp_uart_int_ena_reg_t int_ena;
-    volatile lp_uart_int_clr_reg_t int_clr;
-    volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile lp_uart_rx_filt_reg_t rx_filt;
-    volatile lp_uart_status_reg_t status;
-    volatile lp_uart_conf0_sync_reg_t conf0_sync;
-    volatile lp_uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile lp_uart_sleep_conf0_reg_t sleep_conf0;
-    volatile lp_uart_sleep_conf1_reg_t sleep_conf1;
-    volatile lp_uart_sleep_conf2_reg_t sleep_conf2;
-    volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile lp_uart_swfc_conf1_reg_t swfc_conf1;
-    volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile lp_uart_mem_conf_reg_t mem_conf;
-    volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile lp_uart_mem_tx_status_reg_t mem_tx_status;
-    volatile lp_uart_mem_rx_status_reg_t mem_rx_status;
-    volatile lp_uart_fsm_status_reg_t fsm_status;
-    uint32_t reserved_074[5];
-    volatile lp_uart_clk_conf_reg_t clk_conf;
-    volatile lp_uart_date_reg_t date;
-    volatile lp_uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile lp_uart_reg_update_reg_t reg_update;
-    volatile lp_uart_id_reg_t id;
-} lp_uart_dev_t;
-
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/mcpwm_reg.h b/components/soc/esp32p4/include/soc/mcpwm_reg.h
deleted file mode 100644
index e526c38e605..00000000000
--- a/components/soc/esp32p4/include/soc/mcpwm_reg.h
+++ /dev/null
@@ -1,4514 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** MCPWM_CLK_CFG_REG register
- *  PWM clock prescaler register.
- */
-#define MCPWM_CLK_CFG_REG (DR_REG_MCPWM_BASE + 0x0)
-/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
- *  (PWM_CLK_PRESCALE + 1).
- */
-#define MCPWM_CLK_PRESCALE    0x000000FFU
-#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
-#define MCPWM_CLK_PRESCALE_V  0x000000FFU
-#define MCPWM_CLK_PRESCALE_S  0
-
-/** MCPWM_TIMER0_CFG0_REG register
- *  PWM timer0 period and update method configuration register.
- */
-#define MCPWM_TIMER0_CFG0_REG (DR_REG_MCPWM_BASE + 0x4)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer0, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER0_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer0
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer0 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER0_CFG1_REG register
- *  PWM timer$n working mode and start/stop control register.
- */
-#define MCPWM_TIMER0_CFG1_REG (DR_REG_MCPWM_BASE + 0x8)
-/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
- *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
- *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
- *  stops at the next TEP.\\TEP here and below means the event that happens when the
- *  timer equals to period
- */
-#define MCPWM_TIMER0_START    0x00000007U
-#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
-#define MCPWM_TIMER0_START_V  0x00000007U
-#define MCPWM_TIMER0_START_S  0
-/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER0_MOD    0x00000003U
-#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
-#define MCPWM_TIMER0_MOD_V  0x00000003U
-#define MCPWM_TIMER0_MOD_S  3
-
-/** MCPWM_TIMER0_SYNC_REG register
- *  PWM timer$n sync function configuration register.
- */
-#define MCPWM_TIMER0_SYNC_REG (DR_REG_MCPWM_BASE + 0xc)
-/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer$n reloading with phase on sync input
- *  event is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
-#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER0_SYNCI_EN_S  0
-/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
-#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER0_SYNC_SW_S  1
-/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
-#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_S  2
-/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer$n reload on sync event.
- */
-#define MCPWM_TIMER0_PHASE    0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
-#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_S  4
-/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
-#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER0_STATUS_REG register
- *  PWM timer$n status register.
- */
-#define MCPWM_TIMER0_STATUS_REG (DR_REG_MCPWM_BASE + 0x10)
-/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer$n counter value.
- */
-#define MCPWM_TIMER0_VALUE    0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
-#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_S  0
-/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER0_DIRECTION    (BIT(16))
-#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
-#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_DIRECTION_S  16
-
-/** MCPWM_TIMER1_CFG0_REG register
- *  PWM timer1 period and update method configuration register.
- */
-#define MCPWM_TIMER1_CFG0_REG (DR_REG_MCPWM_BASE + 0x14)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer1, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER1_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer1
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer1 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER1_CFG1_REG register
- *  PWM timer$n working mode and start/stop control register.
- */
-#define MCPWM_TIMER1_CFG1_REG (DR_REG_MCPWM_BASE + 0x18)
-/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
- *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
- *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
- *  stops at the next TEP.\\TEP here and below means the event that happens when the
- *  timer equals to period
- */
-#define MCPWM_TIMER1_START    0x00000007U
-#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
-#define MCPWM_TIMER1_START_V  0x00000007U
-#define MCPWM_TIMER1_START_S  0
-/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER1_MOD    0x00000003U
-#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
-#define MCPWM_TIMER1_MOD_V  0x00000003U
-#define MCPWM_TIMER1_MOD_S  3
-
-/** MCPWM_TIMER1_SYNC_REG register
- *  PWM timer$n sync function configuration register.
- */
-#define MCPWM_TIMER1_SYNC_REG (DR_REG_MCPWM_BASE + 0x1c)
-/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer$n reloading with phase on sync input
- *  event is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
-#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER1_SYNCI_EN_S  0
-/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
-#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER1_SYNC_SW_S  1
-/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
-#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_S  2
-/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer$n reload on sync event.
- */
-#define MCPWM_TIMER1_PHASE    0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
-#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_S  4
-/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
-#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER1_STATUS_REG register
- *  PWM timer$n status register.
- */
-#define MCPWM_TIMER1_STATUS_REG (DR_REG_MCPWM_BASE + 0x20)
-/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer$n counter value.
- */
-#define MCPWM_TIMER1_VALUE    0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
-#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_S  0
-/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER1_DIRECTION    (BIT(16))
-#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
-#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_DIRECTION_S  16
-
-/** MCPWM_TIMER2_CFG0_REG register
- *  PWM timer2 period and update method configuration register.
- */
-#define MCPWM_TIMER2_CFG0_REG (DR_REG_MCPWM_BASE + 0x24)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configures the prescaler value of timer2, so that the period of PT0_clk = Period of
- *  PWM_clk * (PWM_TIMER2_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  Configures the period shadow of PWM timer2
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Configures the update method for active register of PWM timer2 period.\\0:
- *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
- *  zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER2_CFG1_REG register
- *  PWM timer$n working mode and start/stop control register.
- */
-#define MCPWM_TIMER2_CFG1_REG (DR_REG_MCPWM_BASE + 0x28)
-/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
- *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
- *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
- *  stops at the next TEP.\\TEP here and below means the event that happens when the
- *  timer equals to period
- */
-#define MCPWM_TIMER2_START    0x00000007U
-#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
-#define MCPWM_TIMER2_START_V  0x00000007U
-#define MCPWM_TIMER2_START_S  0
-/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
- *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
- *  Decrease mode\\3: Up-down mode
- */
-#define MCPWM_TIMER2_MOD    0x00000003U
-#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
-#define MCPWM_TIMER2_MOD_V  0x00000003U
-#define MCPWM_TIMER2_MOD_S  3
-
-/** MCPWM_TIMER2_SYNC_REG register
- *  PWM timer$n sync function configuration register.
- */
-#define MCPWM_TIMER2_SYNC_REG (DR_REG_MCPWM_BASE + 0x2c)
-/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer$n reloading with phase on sync input
- *  event is enabled.\\0: Disable\\1: Enable
- */
-#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
-#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER2_SYNCI_EN_S  0
-/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of software sync. Toggling this bit will trigger a
- *  software sync.
- */
-#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
-#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER2_SYNC_SW_S  1
-/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
- *  Invalid, sync_out selects noting
- */
-#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
-#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_S  2
-/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  Configures the phase for timer$n reload on sync event.
- */
-#define MCPWM_TIMER2_PHASE    0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
-#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_S  4
-/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
- *  Increase\\1: Decrease
- */
-#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
-#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER2_STATUS_REG register
- *  PWM timer$n status register.
- */
-#define MCPWM_TIMER2_STATUS_REG (DR_REG_MCPWM_BASE + 0x30)
-/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
- *  Represents current PWM timer$n counter value.
- */
-#define MCPWM_TIMER2_VALUE    0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
-#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_S  0
-/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
- *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
- */
-#define MCPWM_TIMER2_DIRECTION    (BIT(16))
-#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
-#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_DIRECTION_S  16
-
-/** MCPWM_TIMER_SYNCI_CFG_REG register
- *  Synchronization input selection register for PWM timers.
- */
-#define MCPWM_TIMER_SYNCI_CFG_REG (DR_REG_MCPWM_BASE + 0x34)
-/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
- *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER0_SYNCISEL    0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
-#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_S  0
-/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
- *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER1_SYNCISEL    0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
-#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_S  3
-/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
- *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
- *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
- *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
- */
-#define MCPWM_TIMER2_SYNCISEL    0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
-#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_S  6
-/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
-/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
-/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
- *  Invert
- */
-#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
-
-/** MCPWM_OPERATOR_TIMERSEL_REG register
- *  PWM operator's timer select register
- */
-#define MCPWM_OPERATOR_TIMERSEL_REG (DR_REG_MCPWM_BASE + 0x38)
-/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
-#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_S  0
-/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
-#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_S  2
-/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
- *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
- *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
- */
-#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
-#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_S  4
-
-/** MCPWM_GEN0_STMP_CFG_REG register
- *  Generator0 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN0_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x3c)
-/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 0 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
-#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_S  0
-/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 0 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
-#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_S  4
-/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator0 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
-#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_A_SHDW_FULL_S  8
-/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator0 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
-#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN0_TSTMP_A_REG register
- *  Generator$n time stamp A's shadow register
- */
-#define MCPWM_GEN0_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x40)
-/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp A's shadow register.
- */
-#define MCPWM_CMPR0_A    0x0000FFFFU
-#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
-#define MCPWM_CMPR0_A_V  0x0000FFFFU
-#define MCPWM_CMPR0_A_S  0
-
-/** MCPWM_GEN0_TSTMP_B_REG register
- *  Generator$n time stamp B's shadow register
- */
-#define MCPWM_GEN0_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x44)
-/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp B's shadow register.
- */
-#define MCPWM_CMPR0_B    0x0000FFFFU
-#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
-#define MCPWM_CMPR0_B_V  0x0000FFFFU
-#define MCPWM_CMPR0_B_S  0
-
-/** MCPWM_GEN0_CFG0_REG register
- *  Generator$n fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN0_CFG0_REG (DR_REG_MCPWM_BASE + 0x48)
-/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator $n's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
-#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_S  0
-/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator $n event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN0_T0_SEL    0x00000007U
-#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
-#define MCPWM_GEN0_T0_SEL_V  0x00000007U
-#define MCPWM_GEN0_T0_SEL_S  4
-/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator $n event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN0_T1_SEL    0x00000007U
-#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
-#define MCPWM_GEN0_T1_SEL_V  0x00000007U
-#define MCPWM_GEN0_T1_SEL_S  7
-
-/** MCPWM_GEN0_FORCE_REG register
- *  Generator$n output signal force mode register.
- */
-#define MCPWM_GEN0_FORCE_REG (DR_REG_MCPWM_BASE + 0x4c)
-/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator$n.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
-#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_A_NCIFORCE_S  10
-/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
-#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_B_NCIFORCE_S  13
-/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN0_A_REG register
- *  PWM$n output signal A actions configuration register
- */
-#define MCPWM_GEN0_A_REG (DR_REG_MCPWM_BASE + 0x50)
-/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEZ    0x00000003U
-#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
-#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_UTEZ_S  0
-/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEP    0x00000003U
-#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
-#define MCPWM_GEN0_A_UTEP_V  0x00000003U
-#define MCPWM_GEN0_A_UTEP_S  2
-/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEA    0x00000003U
-#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
-#define MCPWM_GEN0_A_UTEA_V  0x00000003U
-#define MCPWM_GEN0_A_UTEA_S  4
-/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UTEB    0x00000003U
-#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
-#define MCPWM_GEN0_A_UTEB_V  0x00000003U
-#define MCPWM_GEN0_A_UTEB_S  6
-/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UT0    0x00000003U
-#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
-#define MCPWM_GEN0_A_UT0_V  0x00000003U
-#define MCPWM_GEN0_A_UT0_S  8
-/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_UT1    0x00000003U
-#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
-#define MCPWM_GEN0_A_UT1_V  0x00000003U
-#define MCPWM_GEN0_A_UT1_S  10
-/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEZ    0x00000003U
-#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
-#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_DTEZ_S  12
-/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEP    0x00000003U
-#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
-#define MCPWM_GEN0_A_DTEP_V  0x00000003U
-#define MCPWM_GEN0_A_DTEP_S  14
-/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEA    0x00000003U
-#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
-#define MCPWM_GEN0_A_DTEA_V  0x00000003U
-#define MCPWM_GEN0_A_DTEA_S  16
-/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DTEB    0x00000003U
-#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
-#define MCPWM_GEN0_A_DTEB_V  0x00000003U
-#define MCPWM_GEN0_A_DTEB_S  18
-/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DT0    0x00000003U
-#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
-#define MCPWM_GEN0_A_DT0_V  0x00000003U
-#define MCPWM_GEN0_A_DT0_S  20
-/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_A_DT1    0x00000003U
-#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
-#define MCPWM_GEN0_A_DT1_V  0x00000003U
-#define MCPWM_GEN0_A_DT1_S  22
-
-/** MCPWM_GEN0_B_REG register
- *  PWM$n output signal B actions configuration register
- */
-#define MCPWM_GEN0_B_REG (DR_REG_MCPWM_BASE + 0x54)
-/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEZ    0x00000003U
-#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
-#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_UTEZ_S  0
-/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEP    0x00000003U
-#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
-#define MCPWM_GEN0_B_UTEP_V  0x00000003U
-#define MCPWM_GEN0_B_UTEP_S  2
-/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEA    0x00000003U
-#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
-#define MCPWM_GEN0_B_UTEA_V  0x00000003U
-#define MCPWM_GEN0_B_UTEA_S  4
-/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UTEB    0x00000003U
-#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
-#define MCPWM_GEN0_B_UTEB_V  0x00000003U
-#define MCPWM_GEN0_B_UTEB_S  6
-/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UT0    0x00000003U
-#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
-#define MCPWM_GEN0_B_UT0_V  0x00000003U
-#define MCPWM_GEN0_B_UT0_S  8
-/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_UT1    0x00000003U
-#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
-#define MCPWM_GEN0_B_UT1_V  0x00000003U
-#define MCPWM_GEN0_B_UT1_S  10
-/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEZ    0x00000003U
-#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
-#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_DTEZ_S  12
-/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEP    0x00000003U
-#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
-#define MCPWM_GEN0_B_DTEP_V  0x00000003U
-#define MCPWM_GEN0_B_DTEP_S  14
-/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEA    0x00000003U
-#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
-#define MCPWM_GEN0_B_DTEA_V  0x00000003U
-#define MCPWM_GEN0_B_DTEA_S  16
-/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DTEB    0x00000003U
-#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
-#define MCPWM_GEN0_B_DTEB_V  0x00000003U
-#define MCPWM_GEN0_B_DTEB_S  18
-/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DT0    0x00000003U
-#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
-#define MCPWM_GEN0_B_DT0_V  0x00000003U
-#define MCPWM_GEN0_B_DT0_S  20
-/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN0_B_DT1    0x00000003U
-#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
-#define MCPWM_GEN0_B_DT1_V  0x00000003U
-#define MCPWM_GEN0_B_DT1_S  22
-
-/** MCPWM_DT0_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT0_CFG_REG (DR_REG_MCPWM_BASE + 0x58)
-/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
-#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB0_FED_UPMETHOD_S  0
-/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
-#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB0_RED_UPMETHOD_S  4
-/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB0_DEB_MODE    (BIT(8))
-#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
-#define MCPWM_DB0_DEB_MODE_V  0x00000001U
-#define MCPWM_DB0_DEB_MODE_S  8
-/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
-#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB0_A_OUTSWAP_S  9
-/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
-#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB0_B_OUTSWAP_S  10
-/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DB0_RED_INSEL    (BIT(11))
-#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
-#define MCPWM_DB0_RED_INSEL_V  0x00000001U
-#define MCPWM_DB0_RED_INSEL_S  11
-/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DB0_FED_INSEL    (BIT(12))
-#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
-#define MCPWM_DB0_FED_INSEL_V  0x00000001U
-#define MCPWM_DB0_FED_INSEL_S  12
-/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
-#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB0_RED_OUTINVERT_S  13
-/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
-#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB0_FED_OUTINVERT_S  14
-/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
-#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB0_A_OUTBYPASS_S  15
-/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
-#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB0_B_OUTBYPASS_S  16
-/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DB0_CLK_SEL    (BIT(17))
-#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
-#define MCPWM_DB0_CLK_SEL_V  0x00000001U
-#define MCPWM_DB0_CLK_SEL_S  17
-
-/** MCPWM_DT0_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT0_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x5c)
-/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DB0_FED    0x0000FFFFU
-#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
-#define MCPWM_DB0_FED_V  0x0000FFFFU
-#define MCPWM_DB0_FED_S  0
-
-/** MCPWM_DT0_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT0_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x60)
-/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DB0_RED    0x0000FFFFU
-#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
-#define MCPWM_DB0_RED_V  0x0000FFFFU
-#define MCPWM_DB0_RED_S  0
-
-/** MCPWM_CARRIER0_CFG_REG register
- *  Carrier$n configuration register
- */
-#define MCPWM_CARRIER0_CFG_REG (DR_REG_MCPWM_BASE + 0x64)
-/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CHOPPER0_EN    (BIT(0))
-#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
-#define MCPWM_CHOPPER0_EN_V  0x00000001U
-#define MCPWM_CHOPPER0_EN_S  0
-/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
-#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER0_PRESCALE_S  1
-/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
- */
-#define MCPWM_CHOPPER0_DUTY    0x00000007U
-#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
-#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER0_DUTY_S  5
-/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
-#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER0_OSHTWTH_S  8
-/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
-#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER0_OUT_INVERT_S  12
-/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
-#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER0_IN_INVERT_S  13
-
-/** MCPWM_FH0_CFG0_REG register
- *  PWM$n A and PWM$n B trip events actions configuration register
- */
-#define MCPWM_FH0_CFG0_REG (DR_REG_MCPWM_BASE + 0x68)
-/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_SW_CBC    (BIT(0))
-#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
-#define MCPWM_TZ0_SW_CBC_V  0x00000001U
-#define MCPWM_TZ0_SW_CBC_S  0
-/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F2_CBC    (BIT(1))
-#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
-#define MCPWM_TZ0_F2_CBC_V  0x00000001U
-#define MCPWM_TZ0_F2_CBC_S  1
-/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F1_CBC    (BIT(2))
-#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
-#define MCPWM_TZ0_F1_CBC_V  0x00000001U
-#define MCPWM_TZ0_F1_CBC_S  2
-/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F0_CBC    (BIT(3))
-#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
-#define MCPWM_TZ0_F0_CBC_V  0x00000001U
-#define MCPWM_TZ0_F0_CBC_S  3
-/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_SW_OST    (BIT(4))
-#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
-#define MCPWM_TZ0_SW_OST_V  0x00000001U
-#define MCPWM_TZ0_SW_OST_S  4
-/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F2_OST    (BIT(5))
-#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
-#define MCPWM_TZ0_F2_OST_V  0x00000001U
-#define MCPWM_TZ0_F2_OST_S  5
-/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F1_OST    (BIT(6))
-#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
-#define MCPWM_TZ0_F1_OST_V  0x00000001U
-#define MCPWM_TZ0_F1_OST_S  6
-/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ0_F0_OST    (BIT(7))
-#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
-#define MCPWM_TZ0_F0_OST_V  0x00000001U
-#define MCPWM_TZ0_F0_OST_S  7
-/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_A_CBC_D    0x00000003U
-#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
-#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ0_A_CBC_D_S  8
-/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_A_CBC_U    0x00000003U
-#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
-#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ0_A_CBC_U_S  10
-/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_A_OST_D    0x00000003U
-#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
-#define MCPWM_TZ0_A_OST_D_V  0x00000003U
-#define MCPWM_TZ0_A_OST_D_S  12
-/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_A_OST_U    0x00000003U
-#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
-#define MCPWM_TZ0_A_OST_U_V  0x00000003U
-#define MCPWM_TZ0_A_OST_U_S  14
-/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_B_CBC_D    0x00000003U
-#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
-#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ0_B_CBC_D_S  16
-/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_B_CBC_U    0x00000003U
-#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
-#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ0_B_CBC_U_S  18
-/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_B_OST_D    0x00000003U
-#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
-#define MCPWM_TZ0_B_OST_D_V  0x00000003U
-#define MCPWM_TZ0_B_OST_D_S  20
-/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ0_B_OST_U    0x00000003U
-#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
-#define MCPWM_TZ0_B_OST_U_V  0x00000003U
-#define MCPWM_TZ0_B_OST_U_S  22
-
-/** MCPWM_FH0_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH0_CFG1_REG (DR_REG_MCPWM_BASE + 0x6c)
-/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_TZ0_CLR_OST    (BIT(0))
-#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
-#define MCPWM_TZ0_CLR_OST_V  0x00000001U
-#define MCPWM_TZ0_CLR_OST_S  0
-/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_TZ0_CBCPULSE    0x00000003U
-#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
-#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ0_CBCPULSE_S  1
-/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
-#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ0_FORCE_CBC_S  3
-/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_TZ0_FORCE_OST    (BIT(4))
-#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
-#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ0_FORCE_OST_S  4
-
-/** MCPWM_FH0_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH0_STATUS_REG (DR_REG_MCPWM_BASE + 0x70)
-/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_TZ0_CBC_ON    (BIT(0))
-#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
-#define MCPWM_TZ0_CBC_ON_V  0x00000001U
-#define MCPWM_TZ0_CBC_ON_S  0
-/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_TZ0_OST_ON    (BIT(1))
-#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
-#define MCPWM_TZ0_OST_ON_V  0x00000001U
-#define MCPWM_TZ0_OST_ON_S  1
-
-/** MCPWM_GEN1_STMP_CFG_REG register
- *  Generator1 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN1_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0x74)
-/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 1 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
-#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_S  0
-/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 1 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
-#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_S  4
-/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator1 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
-#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_A_SHDW_FULL_S  8
-/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator1 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
-#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN1_TSTMP_A_REG register
- *  Generator$n time stamp A's shadow register
- */
-#define MCPWM_GEN1_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0x78)
-/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp A's shadow register.
- */
-#define MCPWM_CMPR1_A    0x0000FFFFU
-#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
-#define MCPWM_CMPR1_A_V  0x0000FFFFU
-#define MCPWM_CMPR1_A_S  0
-
-/** MCPWM_GEN1_TSTMP_B_REG register
- *  Generator$n time stamp B's shadow register
- */
-#define MCPWM_GEN1_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0x7c)
-/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp B's shadow register.
- */
-#define MCPWM_CMPR1_B    0x0000FFFFU
-#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
-#define MCPWM_CMPR1_B_V  0x0000FFFFU
-#define MCPWM_CMPR1_B_S  0
-
-/** MCPWM_GEN1_CFG0_REG register
- *  Generator$n fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN1_CFG0_REG (DR_REG_MCPWM_BASE + 0x80)
-/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator $n's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
-#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_S  0
-/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator $n event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN1_T0_SEL    0x00000007U
-#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
-#define MCPWM_GEN1_T0_SEL_V  0x00000007U
-#define MCPWM_GEN1_T0_SEL_S  4
-/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator $n event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN1_T1_SEL    0x00000007U
-#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
-#define MCPWM_GEN1_T1_SEL_V  0x00000007U
-#define MCPWM_GEN1_T1_SEL_S  7
-
-/** MCPWM_GEN1_FORCE_REG register
- *  Generator$n output signal force mode register.
- */
-#define MCPWM_GEN1_FORCE_REG (DR_REG_MCPWM_BASE + 0x84)
-/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator$n.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
-#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_A_NCIFORCE_S  10
-/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
-#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_B_NCIFORCE_S  13
-/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN1_A_REG register
- *  PWM$n output signal A actions configuration register
- */
-#define MCPWM_GEN1_A_REG (DR_REG_MCPWM_BASE + 0x88)
-/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEZ    0x00000003U
-#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
-#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_UTEZ_S  0
-/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEP    0x00000003U
-#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
-#define MCPWM_GEN1_A_UTEP_V  0x00000003U
-#define MCPWM_GEN1_A_UTEP_S  2
-/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEA    0x00000003U
-#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
-#define MCPWM_GEN1_A_UTEA_V  0x00000003U
-#define MCPWM_GEN1_A_UTEA_S  4
-/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UTEB    0x00000003U
-#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
-#define MCPWM_GEN1_A_UTEB_V  0x00000003U
-#define MCPWM_GEN1_A_UTEB_S  6
-/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UT0    0x00000003U
-#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
-#define MCPWM_GEN1_A_UT0_V  0x00000003U
-#define MCPWM_GEN1_A_UT0_S  8
-/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_UT1    0x00000003U
-#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
-#define MCPWM_GEN1_A_UT1_V  0x00000003U
-#define MCPWM_GEN1_A_UT1_S  10
-/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEZ    0x00000003U
-#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
-#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_DTEZ_S  12
-/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEP    0x00000003U
-#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
-#define MCPWM_GEN1_A_DTEP_V  0x00000003U
-#define MCPWM_GEN1_A_DTEP_S  14
-/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEA    0x00000003U
-#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
-#define MCPWM_GEN1_A_DTEA_V  0x00000003U
-#define MCPWM_GEN1_A_DTEA_S  16
-/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DTEB    0x00000003U
-#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
-#define MCPWM_GEN1_A_DTEB_V  0x00000003U
-#define MCPWM_GEN1_A_DTEB_S  18
-/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DT0    0x00000003U
-#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
-#define MCPWM_GEN1_A_DT0_V  0x00000003U
-#define MCPWM_GEN1_A_DT0_S  20
-/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_A_DT1    0x00000003U
-#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
-#define MCPWM_GEN1_A_DT1_V  0x00000003U
-#define MCPWM_GEN1_A_DT1_S  22
-
-/** MCPWM_GEN1_B_REG register
- *  PWM$n output signal B actions configuration register
- */
-#define MCPWM_GEN1_B_REG (DR_REG_MCPWM_BASE + 0x8c)
-/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEZ    0x00000003U
-#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
-#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_UTEZ_S  0
-/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEP    0x00000003U
-#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
-#define MCPWM_GEN1_B_UTEP_V  0x00000003U
-#define MCPWM_GEN1_B_UTEP_S  2
-/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEA    0x00000003U
-#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
-#define MCPWM_GEN1_B_UTEA_V  0x00000003U
-#define MCPWM_GEN1_B_UTEA_S  4
-/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UTEB    0x00000003U
-#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
-#define MCPWM_GEN1_B_UTEB_V  0x00000003U
-#define MCPWM_GEN1_B_UTEB_S  6
-/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UT0    0x00000003U
-#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
-#define MCPWM_GEN1_B_UT0_V  0x00000003U
-#define MCPWM_GEN1_B_UT0_S  8
-/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_UT1    0x00000003U
-#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
-#define MCPWM_GEN1_B_UT1_V  0x00000003U
-#define MCPWM_GEN1_B_UT1_S  10
-/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEZ    0x00000003U
-#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
-#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_DTEZ_S  12
-/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEP    0x00000003U
-#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
-#define MCPWM_GEN1_B_DTEP_V  0x00000003U
-#define MCPWM_GEN1_B_DTEP_S  14
-/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEA    0x00000003U
-#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
-#define MCPWM_GEN1_B_DTEA_V  0x00000003U
-#define MCPWM_GEN1_B_DTEA_S  16
-/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DTEB    0x00000003U
-#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
-#define MCPWM_GEN1_B_DTEB_V  0x00000003U
-#define MCPWM_GEN1_B_DTEB_S  18
-/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DT0    0x00000003U
-#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
-#define MCPWM_GEN1_B_DT0_V  0x00000003U
-#define MCPWM_GEN1_B_DT0_S  20
-/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN1_B_DT1    0x00000003U
-#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
-#define MCPWM_GEN1_B_DT1_V  0x00000003U
-#define MCPWM_GEN1_B_DT1_S  22
-
-/** MCPWM_DT1_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT1_CFG_REG (DR_REG_MCPWM_BASE + 0x90)
-/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
-#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB1_FED_UPMETHOD_S  0
-/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
-#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB1_RED_UPMETHOD_S  4
-/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB1_DEB_MODE    (BIT(8))
-#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
-#define MCPWM_DB1_DEB_MODE_V  0x00000001U
-#define MCPWM_DB1_DEB_MODE_S  8
-/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
-#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB1_A_OUTSWAP_S  9
-/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
-#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB1_B_OUTSWAP_S  10
-/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DB1_RED_INSEL    (BIT(11))
-#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
-#define MCPWM_DB1_RED_INSEL_V  0x00000001U
-#define MCPWM_DB1_RED_INSEL_S  11
-/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DB1_FED_INSEL    (BIT(12))
-#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
-#define MCPWM_DB1_FED_INSEL_V  0x00000001U
-#define MCPWM_DB1_FED_INSEL_S  12
-/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
-#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB1_RED_OUTINVERT_S  13
-/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
-#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB1_FED_OUTINVERT_S  14
-/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
-#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB1_A_OUTBYPASS_S  15
-/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
-#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB1_B_OUTBYPASS_S  16
-/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DB1_CLK_SEL    (BIT(17))
-#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
-#define MCPWM_DB1_CLK_SEL_V  0x00000001U
-#define MCPWM_DB1_CLK_SEL_S  17
-
-/** MCPWM_DT1_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT1_FED_CFG_REG (DR_REG_MCPWM_BASE + 0x94)
-/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DB1_FED    0x0000FFFFU
-#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
-#define MCPWM_DB1_FED_V  0x0000FFFFU
-#define MCPWM_DB1_FED_S  0
-
-/** MCPWM_DT1_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT1_RED_CFG_REG (DR_REG_MCPWM_BASE + 0x98)
-/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DB1_RED    0x0000FFFFU
-#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
-#define MCPWM_DB1_RED_V  0x0000FFFFU
-#define MCPWM_DB1_RED_S  0
-
-/** MCPWM_CARRIER1_CFG_REG register
- *  Carrier$n configuration register
- */
-#define MCPWM_CARRIER1_CFG_REG (DR_REG_MCPWM_BASE + 0x9c)
-/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CHOPPER1_EN    (BIT(0))
-#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
-#define MCPWM_CHOPPER1_EN_V  0x00000001U
-#define MCPWM_CHOPPER1_EN_S  0
-/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
-#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER1_PRESCALE_S  1
-/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
- */
-#define MCPWM_CHOPPER1_DUTY    0x00000007U
-#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
-#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER1_DUTY_S  5
-/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
-#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER1_OSHTWTH_S  8
-/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
-#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER1_OUT_INVERT_S  12
-/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
-#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER1_IN_INVERT_S  13
-
-/** MCPWM_FH1_CFG0_REG register
- *  PWM$n A and PWM$n B trip events actions configuration register
- */
-#define MCPWM_FH1_CFG0_REG (DR_REG_MCPWM_BASE + 0xa0)
-/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_SW_CBC    (BIT(0))
-#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
-#define MCPWM_TZ1_SW_CBC_V  0x00000001U
-#define MCPWM_TZ1_SW_CBC_S  0
-/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F2_CBC    (BIT(1))
-#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
-#define MCPWM_TZ1_F2_CBC_V  0x00000001U
-#define MCPWM_TZ1_F2_CBC_S  1
-/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F1_CBC    (BIT(2))
-#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
-#define MCPWM_TZ1_F1_CBC_V  0x00000001U
-#define MCPWM_TZ1_F1_CBC_S  2
-/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F0_CBC    (BIT(3))
-#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
-#define MCPWM_TZ1_F0_CBC_V  0x00000001U
-#define MCPWM_TZ1_F0_CBC_S  3
-/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_SW_OST    (BIT(4))
-#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
-#define MCPWM_TZ1_SW_OST_V  0x00000001U
-#define MCPWM_TZ1_SW_OST_S  4
-/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F2_OST    (BIT(5))
-#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
-#define MCPWM_TZ1_F2_OST_V  0x00000001U
-#define MCPWM_TZ1_F2_OST_S  5
-/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F1_OST    (BIT(6))
-#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
-#define MCPWM_TZ1_F1_OST_V  0x00000001U
-#define MCPWM_TZ1_F1_OST_S  6
-/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ1_F0_OST    (BIT(7))
-#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
-#define MCPWM_TZ1_F0_OST_V  0x00000001U
-#define MCPWM_TZ1_F0_OST_S  7
-/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_A_CBC_D    0x00000003U
-#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
-#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ1_A_CBC_D_S  8
-/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_A_CBC_U    0x00000003U
-#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
-#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ1_A_CBC_U_S  10
-/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_A_OST_D    0x00000003U
-#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
-#define MCPWM_TZ1_A_OST_D_V  0x00000003U
-#define MCPWM_TZ1_A_OST_D_S  12
-/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_A_OST_U    0x00000003U
-#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
-#define MCPWM_TZ1_A_OST_U_V  0x00000003U
-#define MCPWM_TZ1_A_OST_U_S  14
-/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_B_CBC_D    0x00000003U
-#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
-#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ1_B_CBC_D_S  16
-/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_B_CBC_U    0x00000003U
-#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
-#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ1_B_CBC_U_S  18
-/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_B_OST_D    0x00000003U
-#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
-#define MCPWM_TZ1_B_OST_D_V  0x00000003U
-#define MCPWM_TZ1_B_OST_D_S  20
-/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ1_B_OST_U    0x00000003U
-#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
-#define MCPWM_TZ1_B_OST_U_V  0x00000003U
-#define MCPWM_TZ1_B_OST_U_S  22
-
-/** MCPWM_FH1_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH1_CFG1_REG (DR_REG_MCPWM_BASE + 0xa4)
-/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_TZ1_CLR_OST    (BIT(0))
-#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
-#define MCPWM_TZ1_CLR_OST_V  0x00000001U
-#define MCPWM_TZ1_CLR_OST_S  0
-/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_TZ1_CBCPULSE    0x00000003U
-#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
-#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ1_CBCPULSE_S  1
-/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
-#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ1_FORCE_CBC_S  3
-/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_TZ1_FORCE_OST    (BIT(4))
-#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
-#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ1_FORCE_OST_S  4
-
-/** MCPWM_FH1_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH1_STATUS_REG (DR_REG_MCPWM_BASE + 0xa8)
-/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_TZ1_CBC_ON    (BIT(0))
-#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
-#define MCPWM_TZ1_CBC_ON_V  0x00000001U
-#define MCPWM_TZ1_CBC_ON_S  0
-/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_TZ1_OST_ON    (BIT(1))
-#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
-#define MCPWM_TZ1_OST_ON_V  0x00000001U
-#define MCPWM_TZ1_OST_ON_S  1
-
-/** MCPWM_GEN2_STMP_CFG_REG register
- *  Generator2 time stamp registers A and B transfer status and update method register
- */
-#define MCPWM_GEN2_STMP_CFG_REG (DR_REG_MCPWM_BASE + 0xac)
-/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures the update method for PWM generator 2 time stamp A's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
-#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_A_UPMETHOD_S  0
-/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures the update method for PWM generator 2 time stamp B's active
- *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
- *  set to 1: Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
-#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_CMPR0_B_UPMETHOD_S  4
-/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Represents whether or not generator2 time stamp A's shadow reg is transferred.\\0:
- *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
- *  reg is filled and waiting to be transferred to A's active reg
- */
-#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
-#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_A_SHDW_FULL_S  8
-/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Represents whether or not generator2 time stamp B's shadow reg is transferred.\\0:
- *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
- *  reg is filled and waiting to be transferred to B's active reg
- */
-#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
-#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_CMPR0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN2_TSTMP_A_REG register
- *  Generator$n time stamp A's shadow register
- */
-#define MCPWM_GEN2_TSTMP_A_REG (DR_REG_MCPWM_BASE + 0xb0)
-/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp A's shadow register.
- */
-#define MCPWM_CMPR2_A    0x0000FFFFU
-#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
-#define MCPWM_CMPR2_A_V  0x0000FFFFU
-#define MCPWM_CMPR2_A_S  0
-
-/** MCPWM_GEN2_TSTMP_B_REG register
- *  Generator$n time stamp B's shadow register
- */
-#define MCPWM_GEN2_TSTMP_B_REG (DR_REG_MCPWM_BASE + 0xb4)
-/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
- *  Configures the value of PWM generator $n time stamp B's shadow register.
- */
-#define MCPWM_CMPR2_B    0x0000FFFFU
-#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
-#define MCPWM_CMPR2_B_V  0x0000FFFFU
-#define MCPWM_CMPR2_B_S  0
-
-/** MCPWM_GEN2_CFG0_REG register
- *  Generator$n fault event T0 and T1 configuration register
- */
-#define MCPWM_GEN2_CFG0_REG (DR_REG_MCPWM_BASE + 0xb8)
-/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for PWM generator $n's active register.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
-#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_S  0
-/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Configures source selection for PWM generator $n event_t0, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN2_T0_SEL    0x00000007U
-#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
-#define MCPWM_GEN2_T0_SEL_V  0x00000007U
-#define MCPWM_GEN2_T0_SEL_S  4
-/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Configures source selection for PWM generator $n event_t1, take effect
- *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
- *  Invalid, Select nothing
- */
-#define MCPWM_GEN2_T1_SEL    0x00000007U
-#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
-#define MCPWM_GEN2_T1_SEL_V  0x00000007U
-#define MCPWM_GEN2_T1_SEL_S  7
-
-/** MCPWM_GEN2_FORCE_REG register
- *  Generator$n output signal force mode register.
- */
-#define MCPWM_GEN2_FORCE_REG (DR_REG_MCPWM_BASE + 0xbc)
-/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Configures update method for continuous software force of PWM generator$n.\\0:
- *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
- *  update. TEA/B here and below means an event generated when the timer's value equals
- *  to that of register A/B.
- */
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
- *  High\\3: Disabled
- */
-#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n A, a toggle will trigger a force event.
- */
-#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
-#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_A_NCIFORCE_S  10
-/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Configures the generation of non-continuous immediate software-force event for
- *  PWM$n B, a toggle will trigger a force event.
- */
-#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
-#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_B_NCIFORCE_S  13
-/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
- *  Disabled\\1: Low\\2: High\\3: Disabled
- */
-#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN2_A_REG register
- *  PWM$n output signal A actions configuration register
- */
-#define MCPWM_GEN2_A_REG (DR_REG_MCPWM_BASE + 0xc0)
-/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEZ    0x00000003U
-#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
-#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_UTEZ_S  0
-/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEP    0x00000003U
-#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
-#define MCPWM_GEN2_A_UTEP_V  0x00000003U
-#define MCPWM_GEN2_A_UTEP_S  2
-/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEA    0x00000003U
-#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
-#define MCPWM_GEN2_A_UTEA_V  0x00000003U
-#define MCPWM_GEN2_A_UTEA_S  4
-/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UTEB    0x00000003U
-#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
-#define MCPWM_GEN2_A_UTEB_V  0x00000003U
-#define MCPWM_GEN2_A_UTEB_S  6
-/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UT0    0x00000003U
-#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
-#define MCPWM_GEN2_A_UT0_V  0x00000003U
-#define MCPWM_GEN2_A_UT0_S  8
-/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_UT1    0x00000003U
-#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
-#define MCPWM_GEN2_A_UT1_V  0x00000003U
-#define MCPWM_GEN2_A_UT1_S  10
-/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEZ    0x00000003U
-#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
-#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_DTEZ_S  12
-/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEP    0x00000003U
-#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
-#define MCPWM_GEN2_A_DTEP_V  0x00000003U
-#define MCPWM_GEN2_A_DTEP_S  14
-/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEA    0x00000003U
-#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
-#define MCPWM_GEN2_A_DTEA_V  0x00000003U
-#define MCPWM_GEN2_A_DTEA_S  16
-/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DTEB    0x00000003U
-#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
-#define MCPWM_GEN2_A_DTEB_V  0x00000003U
-#define MCPWM_GEN2_A_DTEB_S  18
-/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DT0    0x00000003U
-#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
-#define MCPWM_GEN2_A_DT0_V  0x00000003U
-#define MCPWM_GEN2_A_DT0_S  20
-/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_A_DT1    0x00000003U
-#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
-#define MCPWM_GEN2_A_DT1_V  0x00000003U
-#define MCPWM_GEN2_A_DT1_S  22
-
-/** MCPWM_GEN2_B_REG register
- *  PWM$n output signal B actions configuration register
- */
-#define MCPWM_GEN2_B_REG (DR_REG_MCPWM_BASE + 0xc4)
-/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEZ    0x00000003U
-#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
-#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_UTEZ_S  0
-/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEP    0x00000003U
-#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
-#define MCPWM_GEN2_B_UTEP_V  0x00000003U
-#define MCPWM_GEN2_B_UTEP_S  2
-/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEA    0x00000003U
-#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
-#define MCPWM_GEN2_B_UTEA_V  0x00000003U
-#define MCPWM_GEN2_B_UTEA_S  4
-/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UTEB    0x00000003U
-#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
-#define MCPWM_GEN2_B_UTEB_V  0x00000003U
-#define MCPWM_GEN2_B_UTEB_S  6
-/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UT0    0x00000003U
-#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
-#define MCPWM_GEN2_B_UT0_V  0x00000003U
-#define MCPWM_GEN2_B_UT0_S  8
-/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_UT1    0x00000003U
-#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
-#define MCPWM_GEN2_B_UT1_V  0x00000003U
-#define MCPWM_GEN2_B_UT1_S  10
-/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEZ    0x00000003U
-#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
-#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_DTEZ_S  12
-/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEP    0x00000003U
-#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
-#define MCPWM_GEN2_B_DTEP_V  0x00000003U
-#define MCPWM_GEN2_B_DTEP_S  14
-/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEA    0x00000003U
-#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
-#define MCPWM_GEN2_B_DTEA_V  0x00000003U
-#define MCPWM_GEN2_B_DTEA_S  16
-/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DTEB    0x00000003U
-#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
-#define MCPWM_GEN2_B_DTEB_V  0x00000003U
-#define MCPWM_GEN2_B_DTEB_S  18
-/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DT0    0x00000003U
-#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
-#define MCPWM_GEN2_B_DT0_V  0x00000003U
-#define MCPWM_GEN2_B_DT0_S  20
-/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
- *  change\\1: Low\\2: High\\3: Toggle
- */
-#define MCPWM_GEN2_B_DT1    0x00000003U
-#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
-#define MCPWM_GEN2_B_DT1_V  0x00000003U
-#define MCPWM_GEN2_B_DT1_S  22
-
-/** MCPWM_DT2_CFG_REG register
- *  Dead time configuration register
- */
-#define MCPWM_DT2_CFG_REG (DR_REG_MCPWM_BASE + 0xc8)
-/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Configures update method for FED (Falling edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
-#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB2_FED_UPMETHOD_S  0
-/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Configures update method for RED (rising edge delay) active register.\\0:
- *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
- *  Sync\\Bit3 is set to 1: Disable the update
- */
-#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
-#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DB2_RED_UPMETHOD_S  4
-/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
- *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DB2_DEB_MODE    (BIT(8))
-#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
-#define MCPWM_DB2_DEB_MODE_V  0x00000001U
-#define MCPWM_DB2_DEB_MODE_S  8
-/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  Configures S6 in table.
- */
-#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
-#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
-#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DB2_A_OUTSWAP_S  9
-/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  Configures S7 in table.
- */
-#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
-#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
-#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DB2_B_OUTSWAP_S  10
-/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  Configures S4 in table.
- */
-#define MCPWM_DB2_RED_INSEL    (BIT(11))
-#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
-#define MCPWM_DB2_RED_INSEL_V  0x00000001U
-#define MCPWM_DB2_RED_INSEL_S  11
-/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  Configures S5 in table.
- */
-#define MCPWM_DB2_FED_INSEL    (BIT(12))
-#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
-#define MCPWM_DB2_FED_INSEL_V  0x00000001U
-#define MCPWM_DB2_FED_INSEL_S  12
-/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  Configures S2 in table.
- */
-#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
-#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB2_RED_OUTINVERT_S  13
-/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  Configures S3 in table.
- */
-#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
-#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DB2_FED_OUTINVERT_S  14
-/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  Configures S1 in table.
- */
-#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
-#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB2_A_OUTBYPASS_S  15
-/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  Configures S0 in table.
- */
-#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
-#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DB2_B_OUTBYPASS_S  16
-/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
- */
-#define MCPWM_DB2_CLK_SEL    (BIT(17))
-#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
-#define MCPWM_DB2_CLK_SEL_V  0x00000001U
-#define MCPWM_DB2_CLK_SEL_S  17
-
-/** MCPWM_DT2_FED_CFG_REG register
- *  Falling edge delay (FED) shadow register
- */
-#define MCPWM_DT2_FED_CFG_REG (DR_REG_MCPWM_BASE + 0xcc)
-/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for FED.
- */
-#define MCPWM_DB2_FED    0x0000FFFFU
-#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
-#define MCPWM_DB2_FED_V  0x0000FFFFU
-#define MCPWM_DB2_FED_S  0
-
-/** MCPWM_DT2_RED_CFG_REG register
- *  Rising edge delay (RED) shadow register
- */
-#define MCPWM_DT2_RED_CFG_REG (DR_REG_MCPWM_BASE + 0xd0)
-/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
- *  Configures shadow register for RED.
- */
-#define MCPWM_DB2_RED    0x0000FFFFU
-#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
-#define MCPWM_DB2_RED_V  0x0000FFFFU
-#define MCPWM_DB2_RED_S  0
-
-/** MCPWM_CARRIER2_CFG_REG register
- *  Carrier$n configuration register
- */
-#define MCPWM_CARRIER2_CFG_REG (DR_REG_MCPWM_BASE + 0xd4)
-/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
- */
-#define MCPWM_CHOPPER2_EN    (BIT(0))
-#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
-#define MCPWM_CHOPPER2_EN_V  0x00000001U
-#define MCPWM_CHOPPER2_EN_S  0
-/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
- *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
- */
-#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
-#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
-#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
-#define MCPWM_CHOPPER2_PRESCALE_S  1
-/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
- */
-#define MCPWM_CHOPPER2_DUTY    0x00000007U
-#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
-#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
-#define MCPWM_CHOPPER2_DUTY_S  5
-/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
- */
-#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
-#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
-#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
-#define MCPWM_CHOPPER2_OSHTWTH_S  8
-/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
-#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
-#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER2_OUT_INVERT_S  12
-/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
- *  submodule.\\0: Normal\\1: Invert
- */
-#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
-#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
-#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
-#define MCPWM_CHOPPER2_IN_INVERT_S  13
-
-/** MCPWM_FH2_CFG0_REG register
- *  PWM$n A and PWM$n B trip events actions configuration register
- */
-#define MCPWM_FH2_CFG0_REG (DR_REG_MCPWM_BASE + 0xd8)
-/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_SW_CBC    (BIT(0))
-#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
-#define MCPWM_TZ2_SW_CBC_V  0x00000001U
-#define MCPWM_TZ2_SW_CBC_S  0
-/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F2_CBC    (BIT(1))
-#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
-#define MCPWM_TZ2_F2_CBC_V  0x00000001U
-#define MCPWM_TZ2_F2_CBC_S  1
-/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F1_CBC    (BIT(2))
-#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
-#define MCPWM_TZ2_F1_CBC_V  0x00000001U
-#define MCPWM_TZ2_F1_CBC_S  2
-/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F0_CBC    (BIT(3))
-#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
-#define MCPWM_TZ2_F0_CBC_V  0x00000001U
-#define MCPWM_TZ2_F0_CBC_S  3
-/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable software force one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_SW_OST    (BIT(4))
-#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
-#define MCPWM_TZ2_SW_OST_V  0x00000001U
-#define MCPWM_TZ2_SW_OST_S  4
-/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F2_OST    (BIT(5))
-#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
-#define MCPWM_TZ2_F2_OST_V  0x00000001U
-#define MCPWM_TZ2_F2_OST_S  5
-/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F1_OST    (BIT(6))
-#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
-#define MCPWM_TZ2_F1_OST_V  0x00000001U
-#define MCPWM_TZ2_F1_OST_S  6
-/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TZ2_F0_OST    (BIT(7))
-#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
-#define MCPWM_TZ2_F0_OST_V  0x00000001U
-#define MCPWM_TZ2_F0_OST_S  7
-/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_A_CBC_D    0x00000003U
-#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
-#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
-#define MCPWM_TZ2_A_CBC_D_S  8
-/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_A_CBC_U    0x00000003U
-#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
-#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
-#define MCPWM_TZ2_A_CBC_U_S  10
-/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_A_OST_D    0x00000003U
-#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
-#define MCPWM_TZ2_A_OST_D_V  0x00000003U
-#define MCPWM_TZ2_A_OST_D_S  12
-/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_A_OST_U    0x00000003U
-#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
-#define MCPWM_TZ2_A_OST_U_V  0x00000003U
-#define MCPWM_TZ2_A_OST_U_S  14
-/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_B_CBC_D    0x00000003U
-#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
-#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
-#define MCPWM_TZ2_B_CBC_D_S  16
-/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
- *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_B_CBC_U    0x00000003U
-#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
-#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
-#define MCPWM_TZ2_B_CBC_U_S  18
-/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_B_OST_D    0x00000003U
-#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
-#define MCPWM_TZ2_B_OST_D_V  0x00000003U
-#define MCPWM_TZ2_B_OST_D_S  20
-/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
- *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
- */
-#define MCPWM_TZ2_B_OST_U    0x00000003U
-#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
-#define MCPWM_TZ2_B_OST_U_V  0x00000003U
-#define MCPWM_TZ2_B_OST_U_S  22
-
-/** MCPWM_FH2_CFG1_REG register
- *  Software triggers for fault handler actions configuration register
- */
-#define MCPWM_FH2_CFG1_REG (DR_REG_MCPWM_BASE + 0xdc)
-/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  Configures the generation of software one-shot mode action clear. A toggle
- *  (software negate its value) triggers a clear for on going one-shot mode action.
- */
-#define MCPWM_TZ2_CLR_OST    (BIT(0))
-#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
-#define MCPWM_TZ2_CLR_OST_V  0x00000001U
-#define MCPWM_TZ2_CLR_OST_S  0
-/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
- *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
- */
-#define MCPWM_TZ2_CBCPULSE    0x00000003U
-#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
-#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
-#define MCPWM_TZ2_CBCPULSE_S  1
-/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of software cycle-by-cycle mode action. A toggle
- *  (software negate its value) triggers a cycle-by-cycle mode action.
- */
-#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
-#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
-#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
-#define MCPWM_TZ2_FORCE_CBC_S  3
-/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  Configures the generation of software one-shot mode action. A toggle (software
- *  negate its value) triggers a one-shot mode action.
- */
-#define MCPWM_TZ2_FORCE_OST    (BIT(4))
-#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
-#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
-#define MCPWM_TZ2_FORCE_OST_S  4
-
-/** MCPWM_FH2_STATUS_REG register
- *  Fault events status register
- */
-#define MCPWM_FH2_STATUS_REG (DR_REG_MCPWM_BASE + 0xe0)
-/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
- *  action\\1: On going
- */
-#define MCPWM_TZ2_CBC_ON    (BIT(0))
-#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
-#define MCPWM_TZ2_CBC_ON_V  0x00000001U
-#define MCPWM_TZ2_CBC_ON_S  0
-/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
- *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
- *  going
- */
-#define MCPWM_TZ2_OST_ON    (BIT(1))
-#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
-#define MCPWM_TZ2_OST_ON_V  0x00000001U
-#define MCPWM_TZ2_OST_ON_S  1
-
-/** MCPWM_FAULT_DETECT_REG register
- *  Fault detection configuration and status register
- */
-#define MCPWM_FAULT_DETECT_REG (DR_REG_MCPWM_BASE + 0xe4)
-/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F0_EN    (BIT(0))
-#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
-#define MCPWM_F0_EN_V  0x00000001U
-#define MCPWM_F0_EN_S  0
-/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F1_EN    (BIT(1))
-#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
-#define MCPWM_F1_EN_V  0x00000001U
-#define MCPWM_F1_EN_S  1
-/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
- */
-#define MCPWM_F2_EN    (BIT(2))
-#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
-#define MCPWM_F2_EN_V  0x00000001U
-#define MCPWM_F2_EN_S  2
-/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
- *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F0_POLE    (BIT(3))
-#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
-#define MCPWM_F0_POLE_V  0x00000001U
-#define MCPWM_F0_POLE_S  3
-/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
- *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F1_POLE    (BIT(4))
-#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
-#define MCPWM_F1_POLE_V  0x00000001U
-#define MCPWM_F1_POLE_S  4
-/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
- *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
- *  low\\1: Level high
- */
-#define MCPWM_F2_POLE    (BIT(5))
-#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
-#define MCPWM_F2_POLE_V  0x00000001U
-#define MCPWM_F2_POLE_S  5
-/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
- *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F0    (BIT(6))
-#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
-#define MCPWM_EVENT_F0_V  0x00000001U
-#define MCPWM_EVENT_F0_S  6
-/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
- *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F1    (BIT(7))
-#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
-#define MCPWM_EVENT_F1_V  0x00000001U
-#define MCPWM_EVENT_F1_S  7
-/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
- *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
- */
-#define MCPWM_EVENT_F2    (BIT(8))
-#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
-#define MCPWM_EVENT_F2_V  0x00000001U
-#define MCPWM_EVENT_F2_S  8
-
-/** MCPWM_CAP_TIMER_CFG_REG register
- *  Capture timer configuration register
- */
-#define MCPWM_CAP_TIMER_CFG_REG (DR_REG_MCPWM_BASE + 0xe8)
-/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP_TIMER_EN    (BIT(0))
-#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
-#define MCPWM_CAP_TIMER_EN_V  0x00000001U
-#define MCPWM_CAP_TIMER_EN_S  0
-/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP_SYNCI_EN    (BIT(1))
-#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
-#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
-#define MCPWM_CAP_SYNCI_EN_S  1
-/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
- *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
- *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
- *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
- */
-#define MCPWM_CAP_SYNCI_SEL    0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
-#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_S  2
-/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
- *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
- *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
- *  value in phase register
- */
-#define MCPWM_CAP_SYNC_SW    (BIT(5))
-#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
-#define MCPWM_CAP_SYNC_SW_V  0x00000001U
-#define MCPWM_CAP_SYNC_SW_S  5
-
-/** MCPWM_CAP_TIMER_PHASE_REG register
- *  Capture timer sync phase register
- */
-#define MCPWM_CAP_TIMER_PHASE_REG (DR_REG_MCPWM_BASE + 0xec)
-/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
- *  Configures phase value for capture timer sync operation.
- */
-#define MCPWM_CAP_PHASE    0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
-#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
-#define MCPWM_CAP_PHASE_S  0
-
-/** MCPWM_CAP_CH0_CFG_REG register
- *  Capture channel 0 configuration register
- */
-#define MCPWM_CAP_CH0_CFG_REG (DR_REG_MCPWM_BASE + 0xf0)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 0.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 0 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP0. Prescale value =
- *  PWM_CAP0_PRESCALE + 1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP0 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 0
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH1_CFG_REG register
- *  Capture channel 1 configuration register
- */
-#define MCPWM_CAP_CH1_CFG_REG (DR_REG_MCPWM_BASE + 0xf4)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 1 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP1. Prescale value =
- *  PWM_CAP1_PRESCALE + 1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP1 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 1
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH2_CFG_REG register
- *  Capture channel 2 configuration register
- */
-#define MCPWM_CAP_CH2_CFG_REG (DR_REG_MCPWM_BASE + 0xf8)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable capture on channel 2.\\0: Disable\\1: Enable
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Configures which edge of capture on channel 2 after prescaling is used.\\0:
- *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
- *  Enable capture on the positive edge
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Configures prescale value on possitive edge of CAP2. Prescale value =
- *  PWM_CAP2_PRESCALE + 1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to invert CAP2 from GPIO matrix before prescale.\\0:
- *  Normal\\1: Invert
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
- *  software forced capture on channel 2
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH0_REG register
- *  CAP0 capture value register
- */
-#define MCPWM_CAP_CH0_REG (DR_REG_MCPWM_BASE + 0xfc)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP0
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_CH1_REG register
- *  CAP1 capture value register
- */
-#define MCPWM_CAP_CH1_REG (DR_REG_MCPWM_BASE + 0x100)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP1
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_CH2_REG register
- *  CAP2 capture value register
- */
-#define MCPWM_CAP_CH2_REG (DR_REG_MCPWM_BASE + 0x104)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Represents value of last capture on CAP2
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_STATUS_REG register
- *  Last capture trigger edge information register
- */
-#define MCPWM_CAP_STATUS_REG (DR_REG_MCPWM_BASE + 0x108)
-/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
- *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP0_EDGE    (BIT(0))
-#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
-#define MCPWM_CAP0_EDGE_V  0x00000001U
-#define MCPWM_CAP0_EDGE_S  0
-/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
- *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP1_EDGE    (BIT(1))
-#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
-#define MCPWM_CAP1_EDGE_V  0x00000001U
-#define MCPWM_CAP1_EDGE_S  1
-/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
- *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
- */
-#define MCPWM_CAP2_EDGE    (BIT(2))
-#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
-#define MCPWM_CAP2_EDGE_V  0x00000001U
-#define MCPWM_CAP2_EDGE_S  2
-
-/** MCPWM_UPDATE_CFG_REG register
- *  Generator Update configuration register
- */
-#define MCPWM_UPDATE_CFG_REG (DR_REG_MCPWM_BASE + 0x10c)
-/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
- *  Configures whether or not to enable global update for all active registers in MCPWM
- *  module.\\0: Disable\\1: Enable
- */
-#define MCPWM_GLOBAL_UP_EN    (BIT(0))
-#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
-#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
-#define MCPWM_GLOBAL_UP_EN_S  0
-/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
- *  Configures the generation of global forced update for all active registers in MCPWM
- *  module. A toggle (software invert its value) will trigger a global forced update.
- *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
- */
-#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
-#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
-#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
-#define MCPWM_GLOBAL_FORCE_UP_S  1
-/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP0_UP_EN    (BIT(2))
-#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
-#define MCPWM_OP0_UP_EN_V  0x00000001U
-#define MCPWM_OP0_UP_EN_S  2
-/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator0. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
- */
-#define MCPWM_OP0_FORCE_UP    (BIT(3))
-#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
-#define MCPWM_OP0_FORCE_UP_V  0x00000001U
-#define MCPWM_OP0_FORCE_UP_S  3
-/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP1_UP_EN    (BIT(4))
-#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
-#define MCPWM_OP1_UP_EN_V  0x00000001U
-#define MCPWM_OP1_UP_EN_S  4
-/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator1. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
- */
-#define MCPWM_OP1_FORCE_UP    (BIT(5))
-#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
-#define MCPWM_OP1_FORCE_UP_V  0x00000001U
-#define MCPWM_OP1_FORCE_UP_S  5
-/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
- *  Configures whether or not to enable update of active registers in PWM operator$n.
- *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
- */
-#define MCPWM_OP2_UP_EN    (BIT(6))
-#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
-#define MCPWM_OP2_UP_EN_V  0x00000001U
-#define MCPWM_OP2_UP_EN_S  6
-/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
- *  Configures the generation of forced update for active registers in PWM operator2. A
- *  toggle (software invert its value) will trigger a forced update. Valid only when
- *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
- */
-#define MCPWM_OP2_FORCE_UP    (BIT(7))
-#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
-#define MCPWM_OP2_FORCE_UP_V  0x00000001U
-#define MCPWM_OP2_FORCE_UP_S  7
-
-/** MCPWM_INT_ENA_REG register
- *  Interrupt enable register
- */
-#define MCPWM_INT_ENA_REG (DR_REG_MCPWM_BASE + 0x110)
-/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
-#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ENA_S  0
-/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
-#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ENA_S  1
-/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
-#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ENA_S  2
-/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
-#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
-/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
-#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
-/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
-#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
-/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
-#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ENA_S  6
-/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
-#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ENA_S  7
-/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
-#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ENA_S  8
-/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ENA    (BIT(9))
-#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
-#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_INT_ENA_S  9
-/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ENA    (BIT(10))
-#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
-#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_INT_ENA_S  10
-/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ENA    (BIT(11))
-#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
-#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_INT_ENA_S  11
-/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
-#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ENA_S  12
-/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
-#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ENA_S  13
-/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
-#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ENA_S  14
-/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
- */
-#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
-#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ENA_S  15
-/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
- */
-#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
-#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ENA_S  16
-/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
- */
-#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
-#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ENA_S  17
-/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
- */
-#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
-#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ENA_S  18
-/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
- */
-#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
-#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ENA_S  19
-/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
- */
-#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
-#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ENA_S  20
-/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
-#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ENA_S  21
-/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
-#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ENA_S  22
-/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
- *  action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
-#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ENA_S  23
-/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
-#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ENA_S  24
-/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
-#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ENA_S  25
-/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
-#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ENA_S  26
-/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
- */
-#define MCPWM_CAP0_INT_ENA    (BIT(27))
-#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
-#define MCPWM_CAP0_INT_ENA_V  0x00000001U
-#define MCPWM_CAP0_INT_ENA_S  27
-/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
- */
-#define MCPWM_CAP1_INT_ENA    (BIT(28))
-#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
-#define MCPWM_CAP1_INT_ENA_V  0x00000001U
-#define MCPWM_CAP1_INT_ENA_S  28
-/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
- */
-#define MCPWM_CAP2_INT_ENA    (BIT(29))
-#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
-#define MCPWM_CAP2_INT_ENA_V  0x00000001U
-#define MCPWM_CAP2_INT_ENA_S  29
-
-/** MCPWM_INT_RAW_REG register
- *  Interrupt raw status register
- */
-#define MCPWM_INT_RAW_REG (DR_REG_MCPWM_BASE + 0x114)
-/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
-#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_RAW_S  0
-/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
-#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_RAW_S  1
-/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
- *  2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
-#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_RAW_S  2
-/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
-#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
-/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
-#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
-/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
-#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
-/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
-#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_RAW_S  6
-/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
-#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_RAW_S  7
-/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
- *  2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
-#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_RAW_S  8
-/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
- *  starts.
- */
-#define MCPWM_FAULT0_INT_RAW    (BIT(9))
-#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
-#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_INT_RAW_S  9
-/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
- *  starts.
- */
-#define MCPWM_FAULT1_INT_RAW    (BIT(10))
-#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
-#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_INT_RAW_S  10
-/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
- *  starts.
- */
-#define MCPWM_FAULT2_INT_RAW    (BIT(11))
-#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
-#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_INT_RAW_S  11
-/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
- *  clears.
- */
-#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
-#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_RAW_S  12
-/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
- *  clears.
- */
-#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
-#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_RAW_S  13
-/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
- *  clears.
- */
-#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
-#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_RAW_S  14
-/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
-#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_RAW_S  15
-/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
-#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_RAW_S  16
-/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
-#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_RAW_S  17
-/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
-#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_RAW_S  18
-/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
-#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_RAW_S  19
-/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
-#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_RAW_S  20
-/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
-#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_RAW_S  21
-/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
-#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_RAW_S  22
-/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
-#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_RAW_S  23
-/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
-#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
-#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_RAW_S  24
-/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
-#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
-#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_RAW_S  25
-/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
- *  mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
-#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
-#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_RAW_S  26
-/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP0.
- */
-#define MCPWM_CAP0_INT_RAW    (BIT(27))
-#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
-#define MCPWM_CAP0_INT_RAW_V  0x00000001U
-#define MCPWM_CAP0_INT_RAW_S  27
-/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP1.
- */
-#define MCPWM_CAP1_INT_RAW    (BIT(28))
-#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
-#define MCPWM_CAP1_INT_RAW_V  0x00000001U
-#define MCPWM_CAP1_INT_RAW_S  28
-/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
- *  CAP2.
- */
-#define MCPWM_CAP2_INT_RAW    (BIT(29))
-#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
-#define MCPWM_CAP2_INT_RAW_V  0x00000001U
-#define MCPWM_CAP2_INT_RAW_S  29
-
-/** MCPWM_INT_ST_REG register
- *  Interrupt masked status register
- */
-#define MCPWM_INT_ST_REG (DR_REG_MCPWM_BASE + 0x118)
-/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
-#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ST_S  0
-/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
-#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ST_S  1
-/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when the
- *  timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
-#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ST_S  2
-/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
-#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ST_S  3
-/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
-#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ST_S  4
-/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
-#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ST_S  5
-/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
-#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ST_S  6
-/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
-#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ST_S  7
-/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
-#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ST_S  8
-/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_ST    (BIT(9))
-#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
-#define MCPWM_FAULT0_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_INT_ST_S  9
-/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_ST    (BIT(10))
-#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
-#define MCPWM_FAULT1_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_INT_ST_S  10
-/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_ST    (BIT(11))
-#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
-#define MCPWM_FAULT2_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_INT_ST_S  11
-/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
-#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ST_S  12
-/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
-#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ST_S  13
-/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered when
- *  event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
-#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ST_S  14
-/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
-#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_ST_S  15
-/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
-#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_ST_S  16
-/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
-#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_ST_S  17
-/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
-#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_ST_S  18
-/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
-#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_ST_S  19
-/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
- *  operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
-#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_ST_S  20
-/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
-#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_ST_S  21
-/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
-#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_ST_S  22
-/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
-#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_ST_S  23
-/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM0.
- */
-#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
-#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
-#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_ST_S  24
-/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM1.
- */
-#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
-#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
-#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_ST_S  25
-/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by a
- *  one-shot mode action on PWM2.
- */
-#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
-#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
-#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_ST_S  26
-/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP0.
- */
-#define MCPWM_CAP0_INT_ST    (BIT(27))
-#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
-#define MCPWM_CAP0_INT_ST_V  0x00000001U
-#define MCPWM_CAP0_INT_ST_S  27
-/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP1.
- */
-#define MCPWM_CAP1_INT_ST    (BIT(28))
-#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
-#define MCPWM_CAP1_INT_ST_V  0x00000001U
-#define MCPWM_CAP1_INT_ST_S  28
-/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
- *  Masked status bit: The masked interrupt status of the interrupt triggered by
- *  capture on CAP2.
- */
-#define MCPWM_CAP2_INT_ST    (BIT(29))
-#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
-#define MCPWM_CAP2_INT_ST_V  0x00000001U
-#define MCPWM_CAP2_INT_ST_S  29
-
-/** MCPWM_INT_CLR_REG register
- *  Interrupt clear register
- */
-#define MCPWM_INT_CLR_REG (DR_REG_MCPWM_BASE + 0x11c)
-/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
-#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_CLR_S  0
-/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
-#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_CLR_S  1
-/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
-#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_CLR_S  2
-/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
-#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
-/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
-#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
-/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
-#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
-/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
-#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_CLR_S  6
-/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
-#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_CLR_S  7
-/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
-#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_CLR_S  8
-/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
- */
-#define MCPWM_FAULT0_INT_CLR    (BIT(9))
-#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
-#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_INT_CLR_S  9
-/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
- */
-#define MCPWM_FAULT1_INT_CLR    (BIT(10))
-#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
-#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_INT_CLR_S  10
-/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
- */
-#define MCPWM_FAULT2_INT_CLR    (BIT(11))
-#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
-#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_INT_CLR_S  11
-/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
- */
-#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
-#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_CLR_S  12
-/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
- */
-#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
-#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_CLR_S  13
-/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
- */
-#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
-#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_CLR_S  14
-/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
-#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
-#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEA_INT_CLR_S  15
-/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
-#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
-#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEA_INT_CLR_S  16
-/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
-#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
-#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEA_INT_CLR_S  17
-/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
-#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
-#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR0_TEB_INT_CLR_S  18
-/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
-#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
-#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR1_TEB_INT_CLR_S  19
-/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
-#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
-#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_CMPR2_TEB_INT_CLR_S  20
-/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM0.
- */
-#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
-#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
-#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_CBC_INT_CLR_S  21
-/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM1.
- */
-#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
-#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
-#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_CBC_INT_CLR_S  22
-/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM2.
- */
-#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
-#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
-#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_CBC_INT_CLR_S  23
-/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM0.
- */
-#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
-#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
-#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ0_OST_INT_CLR_S  24
-/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM1.
- */
-#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
-#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
-#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ1_OST_INT_CLR_S  25
-/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
- *  PWM2.
- */
-#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
-#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
-#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
-#define MCPWM_TZ2_OST_INT_CLR_S  26
-/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
- */
-#define MCPWM_CAP0_INT_CLR    (BIT(27))
-#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
-#define MCPWM_CAP0_INT_CLR_V  0x00000001U
-#define MCPWM_CAP0_INT_CLR_S  27
-/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
- */
-#define MCPWM_CAP1_INT_CLR    (BIT(28))
-#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
-#define MCPWM_CAP1_INT_CLR_V  0x00000001U
-#define MCPWM_CAP1_INT_CLR_S  28
-/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
- *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
- */
-#define MCPWM_CAP2_INT_CLR    (BIT(29))
-#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
-#define MCPWM_CAP2_INT_CLR_V  0x00000001U
-#define MCPWM_CAP2_INT_CLR_S  29
-
-/** MCPWM_EVT_EN_REG register
- *  Event enable register
- */
-#define MCPWM_EVT_EN_REG (DR_REG_MCPWM_BASE + 0x120)
-/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
-#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
-#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_STOP_EN_S  0
-/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
-#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
-#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_STOP_EN_S  1
-/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
-#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
-#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_STOP_EN_S  2
-/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable timer0 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
-#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
-#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
-/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable timer1 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
-#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
-#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
-/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable timer2 equal zero event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
-#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
-#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
-/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to enable timer0 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
-#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
-#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER0_TEP_EN_S  6
-/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable timer1 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
-#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
-#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER1_TEP_EN_S  7
-/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable timer2 equal period event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
-#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
-#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
-#define MCPWM_EVT_TIMER2_TEP_EN_S  8
-/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
-#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
-#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEA_EN_S  9
-/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
-#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
-#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEA_EN_S  10
-/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal a event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
-#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
-#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEA_EN_S  11
-/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
-#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
-#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEB_EN_S  12
-/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
-#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
-#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEB_EN_S  13
-/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal b event
- *  generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
-#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
-#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEB_EN_S  14
-/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F0_EN    (BIT(15))
-#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
-#define MCPWM_EVT_F0_EN_V  0x00000001U
-#define MCPWM_EVT_F0_EN_S  15
-/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F1_EN    (BIT(16))
-#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
-#define MCPWM_EVT_F1_EN_V  0x00000001U
-#define MCPWM_EVT_F1_EN_S  16
-/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_F2_EN    (BIT(17))
-#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
-#define MCPWM_EVT_F2_EN_V  0x00000001U
-#define MCPWM_EVT_F2_EN_S  17
-/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
-#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
-#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F0_CLR_EN_S  18
-/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
-#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
-#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F1_CLR_EN_S  19
-/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
-#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
-#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
-#define MCPWM_EVT_F2_CLR_EN_S  20
-/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
-#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
-#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_CBC_EN_S  21
-/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
-#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
-#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_CBC_EN_S  22
-/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
- *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
-#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
-#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_CBC_EN_S  23
-/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
- *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
-#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
-#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ0_OST_EN_S  24
-/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
- *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
-#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
-#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ1_OST_EN_S  25
-/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
- *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
-#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
-#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_EVT_TZ2_OST_EN_S  26
-/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
- *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP0_EN    (BIT(27))
-#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
-#define MCPWM_EVT_CAP0_EN_V  0x00000001U
-#define MCPWM_EVT_CAP0_EN_S  27
-/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
- *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP1_EN    (BIT(28))
-#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
-#define MCPWM_EVT_CAP1_EN_V  0x00000001U
-#define MCPWM_EVT_CAP1_EN_S  28
-/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
- *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_CAP2_EN    (BIT(29))
-#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
-#define MCPWM_EVT_CAP2_EN_V  0x00000001U
-#define MCPWM_EVT_CAP2_EN_S  29
-
-/** MCPWM_TASK_EN_REG register
- *  Task enable register
- */
-#define MCPWM_TASK_EN_REG (DR_REG_MCPWM_BASE + 0x124)
-/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
-#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
-#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
-/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
-#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
-#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
-/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
-#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
-#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
-/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
-#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
-#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
-/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
-#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
-#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
-/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
- *  update task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
-#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
-#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
-#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
-/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
- *  Configures whether or not to enable all PWM generate stop task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
-#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
-#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
-#define MCPWM_TASK_GEN_STOP_EN_S  6
-/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
- *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
-#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
-#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
-/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
- *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
-#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
-#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
-/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
- *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
-#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
-#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
-/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
- *  Configures whether or not to enable timer0 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
-/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
- *  Configures whether or not to enable timer1 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
-/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
- *  Configures whether or not to enable timer2 period update task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
-#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
-/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
- *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
-#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
-#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ0_OST_EN_S  13
-/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
- *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
-#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
-#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ1_OST_EN_S  14
-/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
- *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
- *  Enable
- */
-#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
-#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
-#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_TZ2_OST_EN_S  15
-/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
- *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
-#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
-#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR0_OST_EN_S  16
-/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
- *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
-#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
-#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR1_OST_EN_S  17
-/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
- *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
- *  Disable\\1: Enable
- */
-#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
-#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
-#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
-#define MCPWM_TASK_CLR2_OST_EN_S  18
-/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
- *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP0_EN    (BIT(19))
-#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
-#define MCPWM_TASK_CAP0_EN_V  0x00000001U
-#define MCPWM_TASK_CAP0_EN_S  19
-/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
- *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP1_EN    (BIT(20))
-#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
-#define MCPWM_TASK_CAP1_EN_V  0x00000001U
-#define MCPWM_TASK_CAP1_EN_S  20
-/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
- *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
- */
-#define MCPWM_TASK_CAP2_EN    (BIT(21))
-#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
-#define MCPWM_TASK_CAP2_EN_V  0x00000001U
-#define MCPWM_TASK_CAP2_EN_S  21
-
-/** MCPWM_EVT_EN2_REG register
- *  Event enable register2
- */
-#define MCPWM_EVT_EN2_REG (DR_REG_MCPWM_BASE + 0x128)
-/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEE1_EN    (BIT(0))
-#define MCPWM_EVT_OP0_TEE1_EN_M  (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S)
-#define MCPWM_EVT_OP0_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEE1_EN_S  0
-/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEE1_EN    (BIT(1))
-#define MCPWM_EVT_OP1_TEE1_EN_M  (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S)
-#define MCPWM_EVT_OP1_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEE1_EN_S  1
-/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEE1_EN    (BIT(2))
-#define MCPWM_EVT_OP2_TEE1_EN_M  (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S)
-#define MCPWM_EVT_OP2_TEE1_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEE1_EN_S  2
-/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0;
- *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP0_TEE2_EN    (BIT(3))
-#define MCPWM_EVT_OP0_TEE2_EN_M  (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S)
-#define MCPWM_EVT_OP0_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP0_TEE2_EN_S  3
-/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0;
- *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP1_TEE2_EN    (BIT(4))
-#define MCPWM_EVT_OP1_TEE2_EN_M  (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S)
-#define MCPWM_EVT_OP1_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP1_TEE2_EN_S  4
-/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0;
- *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
- *  event generate.\\0: Disable\\1: Enable
- */
-#define MCPWM_EVT_OP2_TEE2_EN    (BIT(5))
-#define MCPWM_EVT_OP2_TEE2_EN_M  (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S)
-#define MCPWM_EVT_OP2_TEE2_EN_V  0x00000001U
-#define MCPWM_EVT_OP2_TEE2_EN_S  5
-
-/** MCPWM_OP0_TSTMP_E1_REG register
- *  Generator0 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x12c)
-/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator0 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
-#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_S  0
-
-/** MCPWM_OP0_TSTMP_E2_REG register
- *  Generator$n timer stamp E2 value register
- */
-#define MCPWM_OP0_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x130)
-/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator$n timer stamp E2 value register
- */
-#define MCPWM_OP0_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E2_M  (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S)
-#define MCPWM_OP0_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E2_S  0
-
-/** MCPWM_OP1_TSTMP_E1_REG register
- *  Generator1 timer stamp E1 value register
- */
-#define MCPWM_OP1_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x134)
-/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator1 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
-#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_S  0
-
-/** MCPWM_OP1_TSTMP_E2_REG register
- *  Generator$n timer stamp E2 value register
- */
-#define MCPWM_OP1_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x138)
-/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator$n timer stamp E2 value register
- */
-#define MCPWM_OP1_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP1_TSTMP_E2_M  (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S)
-#define MCPWM_OP1_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP1_TSTMP_E2_S  0
-
-/** MCPWM_OP2_TSTMP_E1_REG register
- *  Generator2 timer stamp E1 value register
- */
-#define MCPWM_OP2_TSTMP_E1_REG (DR_REG_MCPWM_BASE + 0x13c)
-/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator2 timer stamp E1 value register
- */
-#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
-#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
-#define MCPWM_OP0_TSTMP_E1_S  0
-
-/** MCPWM_OP2_TSTMP_E2_REG register
- *  Generator$n timer stamp E2 value register
- */
-#define MCPWM_OP2_TSTMP_E2_REG (DR_REG_MCPWM_BASE + 0x140)
-/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
- *  Configures generator$n timer stamp E2 value register
- */
-#define MCPWM_OP2_TSTMP_E2    0x0000FFFFU
-#define MCPWM_OP2_TSTMP_E2_M  (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S)
-#define MCPWM_OP2_TSTMP_E2_V  0x0000FFFFU
-#define MCPWM_OP2_TSTMP_E2_S  0
-
-/** MCPWM_CLK_REG register
- *  Global configuration register
- */
-#define MCPWM_CLK_REG (DR_REG_MCPWM_BASE + 0x144)
-/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
- *  when application writes registers\\1: Force open the clock gate for register
- */
-#define MCPWM_CLK_EN    (BIT(0))
-#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
-#define MCPWM_CLK_EN_V  0x00000001U
-#define MCPWM_CLK_EN_S  0
-
-/** MCPWM_VERSION_REG register
- *  Version register.
- */
-#define MCPWM_VERSION_REG (DR_REG_MCPWM_BASE + 0x148)
-/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968;
- *  Configures the version.
- */
-#define MCPWM_DATE    0x0FFFFFFFU
-#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
-#define MCPWM_DATE_V  0x0FFFFFFFU
-#define MCPWM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/mcpwm_struct.h b/components/soc/esp32p4/include/soc/mcpwm_struct.h
deleted file mode 100644
index 2b72d044e1a..00000000000
--- a/components/soc/esp32p4/include/soc/mcpwm_struct.h
+++ /dev/null
@@ -1,1918 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: clk_cfg */
-/** Type of clk_cfg register
- *  PWM clock prescaler register.
- */
-typedef union {
-    struct {
-        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
-         *  (PWM_CLK_PRESCALE + 1).
-         */
-        uint32_t clk_prescale:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_clk_cfg_reg_t;
-
-
-/** Group: timer */
-/** Type of timern_cfg0 register
- *  PWM timern period and update method configuration register.
- */
-typedef union {
-    struct {
-        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Configures the prescaler value of timern, so that the period of PT0_clk = Period of
-         *  PWM_clk * (PWM_TIMERn_PRESCALE + 1)
-         */
-        uint32_t timer_prescale:8;
-        /** timer_period : R/W; bitpos: [23:8]; default: 255;
-         *  Configures the period shadow of PWM timern
-         */
-        uint32_t timer_period:16;
-        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
-         *  Configures the update method for active register of PWM timern period.\\0:
-         *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
-         *  zero event
-         */
-        uint32_t timer_period_upmethod:2;
-        uint32_t reserved_26:6;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg0_reg_t;
-
-/** Type of timer0_cfg1 register
- *  PWM timer$n working mode and start/stop control register.
- */
-typedef union {
-    struct {
-        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
-         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
-         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
-         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
-         *  stops at the next TEP.\\TEP here and below means the event that happens when the
-         *  timer equals to period
-         */
-        uint32_t timer_start:3;
-        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
-         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
-         *  Decrease mode\\3: Up-down mode
-         */
-        uint32_t timer_mod:2;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg1_reg_t;
-
-/** Type of timer0_sync register
- *  PWM timer$n sync function configuration register.
- */
-typedef union {
-    struct {
-        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable timer$n reloading with phase on sync input
-         *  event is enabled.\\0: Disable\\1: Enable
-         */
-        uint32_t timer_synci_en:1;
-        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
-         *  Configures the generation of software sync. Toggling this bit will trigger a
-         *  software sync.
-         */
-        uint32_t timer_sync_sw:1;
-        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
-         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
-         *  Invalid, sync_out selects noting
-         */
-        uint32_t timer_synco_sel:2;
-        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
-         *  Configures the phase for timer$n reload on sync event.
-         */
-        uint32_t timer_phase:16;
-        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
-         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
-         *  Increase\\1: Decrease
-         */
-        uint32_t timer_phase_direction:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} mcpwm_timer_sync_reg_t;
-
-/** Type of timer_status register
- *  PWM timer$n status register.
- */
-typedef union {
-    struct {
-        /** timer_value : RO; bitpos: [15:0]; default: 0;
-         *  Represents current PWM timer$n counter value.
-         */
-        uint32_t timer_value:16;
-        /** timer_direction : RO; bitpos: [16]; default: 0;
-         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
-         */
-        uint32_t timer_direction:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} mcpwm_timer_status_reg_t;
-
-
-/** Group: timer_synci_cfg */
-/** Type of timer_synci_cfg register
- *  Synchronization input selection register for PWM timers.
- */
-typedef union {
-    struct {
-        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
-         *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer0_syncisel:3;
-        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
-         *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer1_syncisel:3;
-        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
-         *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
-         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
-         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
-         */
-        uint32_t timer2_syncisel:3;
-        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci0_invert:1;
-        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci1_invert:1;
-        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
-         *  Invert
-         */
-        uint32_t external_synci2_invert:1;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} mcpwm_timer_synci_cfg_reg_t;
-
-
-/** Group: operator_timersel */
-/** Type of operator_timersel register
- *  PWM operator's timer select register
- */
-typedef union {
-    struct {
-        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator0_timersel:2;
-        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator1_timersel:2;
-        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
-         *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
-         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
-         */
-        uint32_t operator2_timersel:2;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_operator_timersel_reg_t;
-
-
-/** Group: operators */
-/** Type of genn_stmp_cfg register
- *  Generatorn time stamp registers A and B transfer status and update method register
- */
-typedef union {
-    struct {
-        /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures the update method for PWM generator n time stamp A's active
-         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
-         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t cmpr_a_upmethod:4;
-        /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Configures the update method for PWM generator n time stamp B's active
-         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
-         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t cmpr_b_upmethod:4;
-        /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
-         *  Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0:
-         *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
-         *  reg is filled and waiting to be transferred to A's active reg
-         */
-        uint32_t cmpr_a_shdw_full:1;
-        /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
-         *  Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0:
-         *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
-         *  reg is filled and waiting to be transferred to B's active reg
-         */
-        uint32_t cmpr_b_shdw_full:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_gen_stmp_cfg_reg_t;
-
-/** Type of gen_tstmp_a register
- *  Generator$n time stamp A's shadow register
- */
-typedef union {
-    struct {
-        /** cmpr : R/W; bitpos: [15:0]; default: 0;
-         *  Configures the value of PWM generator $n time stamp 's shadow register.
-         */
-        uint32_t cmpr:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_tstmp_reg_t;
-
-
-/** Type of gen_cfg0 register
- *  Generator$n fault event T0 and T1 configuration register
- */
-typedef union {
-    struct {
-        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures update method for PWM generator $n's active register.\\0:
-         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t gen_cfg_upmethod:4;
-        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
-         *  Configures source selection for PWM generator $n event_t0, take effect
-         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
-         *  Invalid, Select nothing
-         */
-        uint32_t gen_t0_sel:3;
-        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
-         *  Configures source selection for PWM generator $n event_t1, take effect
-         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
-         *  Invalid, Select nothing
-         */
-        uint32_t gen_t1_sel:3;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} mcpwm_gen_cfg0_reg_t;
-
-/** Type of gen_force register
- *  Generator$n output signal force mode register.
- */
-typedef union {
-    struct {
-        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
-         *  Configures update method for continuous software force of PWM generator$n.\\0:
-         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
-         *  update. TEA/B here and below means an event generated when the timer's value equals
-         *  to that of register A/B.
-         */
-        uint32_t gen_cntuforce_upmethod:6;
-        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
-         *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
-         *  High\\3: Disabled
-         */
-        uint32_t gen_a_cntuforce_mode:2;
-        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
-         *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
-         *  High\\3: Disabled
-         */
-        uint32_t gen_b_cntuforce_mode:2;
-        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
-         *  Configures the generation of non-continuous immediate software-force event for
-         *  PWM$n A, a toggle will trigger a force event.
-         */
-        uint32_t gen_a_nciforce:1;
-        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
-         *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
-         *  Disabled\\1: Low\\2: High\\3: Disabled
-         */
-        uint32_t gen_a_nciforce_mode:2;
-        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
-         *  Configures the generation of non-continuous immediate software-force event for
-         *  PWM$n B, a toggle will trigger a force event.
-         */
-        uint32_t gen_b_nciforce:1;
-        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
-         *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
-         *  Disabled\\1: Low\\2: High\\3: Disabled
-         */
-        uint32_t gen_b_nciforce_mode:2;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_gen_force_reg_t;
-
-/** Type of gen register
- *  PWM$n output signal A actions configuration register
- */
-typedef union {
-    struct {
-        /** gen_a_utez : R/W; bitpos: [1:0]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_utez:2;
-        /** gen_a_utep : R/W; bitpos: [3:2]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_utep:2;
-        /** gen_a_utea : R/W; bitpos: [5:4]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_utea:2;
-        /** gen_a_uteb : R/W; bitpos: [7:6]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_uteb:2;
-        /** gen_a_ut0 : R/W; bitpos: [9:8]; default: 0;
-         *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_ut0:2;
-        /** gen_a_ut1 : R/W; bitpos: [11:10]; default: 0;
-         *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_ut1:2;
-        /** gen_a_dtez : R/W; bitpos: [13:12]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_dtez:2;
-        /** gen_a_dtep : R/W; bitpos: [15:14]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_dtep:2;
-        /** gen_a_dtea : R/W; bitpos: [17:16]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_dtea:2;
-        /** gen_a_dteb : R/W; bitpos: [19:18]; default: 0;
-         *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_dteb:2;
-        /** gen_a_dt0 : R/W; bitpos: [21:20]; default: 0;
-         *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_dt0:2;
-        /** gen_a_dt1 : R/W; bitpos: [23:22]; default: 0;
-         *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
-         *  change\\1: Low\\2: High\\3: Toggle
-         */
-        uint32_t gen_dt1:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_gen_reg_t;
-
-/** Type of dt0_cfg register
- *  Dead time configuration register
- */
-typedef union {
-    struct {
-        /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Configures update method for FED (Falling edge delay) active register.\\0:
-         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t db_fed_upmethod:4;
-        /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Configures update method for RED (rising edge delay) active register.\\0:
-         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
-         *  Sync\\Bit3 is set to 1: Disable the update
-         */
-        uint32_t db_red_upmethod:4;
-        /** db_deb_mode : R/W; bitpos: [8]; default: 0;
-         *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
-         *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
-         */
-        uint32_t db_deb_mode:1;
-        /** db_a_outswap : R/W; bitpos: [9]; default: 0;
-         *  Configures S6 in table.
-         */
-        uint32_t db_a_outswap:1;
-        /** db_b_outswap : R/W; bitpos: [10]; default: 0;
-         *  Configures S7 in table.
-         */
-        uint32_t db_b_outswap:1;
-        /** db_red_insel : R/W; bitpos: [11]; default: 0;
-         *  Configures S4 in table.
-         */
-        uint32_t db_red_insel:1;
-        /** db_fed_insel : R/W; bitpos: [12]; default: 0;
-         *  Configures S5 in table.
-         */
-        uint32_t db_fed_insel:1;
-        /** db_red_outinvert : R/W; bitpos: [13]; default: 0;
-         *  Configures S2 in table.
-         */
-        uint32_t db_red_outinvert:1;
-        /** db_fed_outinvert : R/W; bitpos: [14]; default: 0;
-         *  Configures S3 in table.
-         */
-        uint32_t db_fed_outinvert:1;
-        /** db_a_outbypass : R/W; bitpos: [15]; default: 1;
-         *  Configures S1 in table.
-         */
-        uint32_t db_a_outbypass:1;
-        /** db_b_outbypass : R/W; bitpos: [16]; default: 1;
-         *  Configures S0 in table.
-         */
-        uint32_t db_b_outbypass:1;
-        /** db_clk_sel : R/W; bitpos: [17]; default: 0;
-         *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
-         */
-        uint32_t db_clk_sel:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} mcpwm_dt_cfg_reg_t;
-
-/** Type of dt0_fed_cfg register
- *  Falling edge delay (FED) shadow register
- */
-typedef union {
-    struct {
-        /** db_fed : R/W; bitpos: [15:0]; default: 0;
-         *  Configures shadow register for FED.
-         */
-        uint32_t db_fed:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dt_fed_cfg_reg_t;
-
-/** Type of dt0_red_cfg register
- *  Rising edge delay (RED) shadow register
- */
-typedef union {
-    struct {
-        /** db_red : R/W; bitpos: [15:0]; default: 0;
-         *  Configures shadow register for RED.
-         */
-        uint32_t db_red:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_dt_red_cfg_reg_t;
-
-/** Type of carrier0_cfg register
- *  Carrier$n configuration register
- */
-typedef union {
-    struct {
-        /** chopper_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
-         */
-        uint32_t chopper_en:1;
-        /** chopper_prescale : R/W; bitpos: [4:1]; default: 0;
-         *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
-         *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
-         */
-        uint32_t chopper_prescale:4;
-        /** chopper_duty : R/W; bitpos: [7:5]; default: 0;
-         *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
-         */
-        uint32_t chopper_duty:3;
-        /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0;
-         *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
-         */
-        uint32_t chopper_oshtwth:4;
-        /** chopper_out_invert : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
-         *  submodule.\\0: Normal\\1: Invert
-         */
-        uint32_t chopper_out_invert:1;
-        /** chopper_in_invert : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
-         *  submodule.\\0: Normal\\1: Invert
-         */
-        uint32_t chopper_in_invert:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} mcpwm_carrier_cfg_reg_t;
-
-/** Type of fh0_cfg0 register
- *  PWM$n A and PWM$n B trip events actions configuration register
- */
-typedef union {
-    struct {
-        /** tz_sw_cbc : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz_sw_cbc:1;
-        /** tz_f2_cbc : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz_f2_cbc:1;
-        /** tz_f1_cbc : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz_f1_cbc:1;
-        /** tz_f0_cbc : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz_f0_cbc:1;
-        /** tz_sw_ost : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable software force one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz_sw_ost:1;
-        /** tz_f2_ost : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz_f2_ost:1;
-        /** tz_f1_ost : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz_f1_ost:1;
-        /** tz_f0_ost : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t tz_f0_ost:1;
-        /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
-         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz_a_cbc_d:2;
-        /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
-         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz_a_cbc_u:2;
-        /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0;
-         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
-         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz_a_ost_d:2;
-        /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0;
-         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
-         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz_a_ost_u:2;
-        /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
-         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz_b_cbc_d:2;
-        /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
-         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
-         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz_b_cbc_u:2;
-        /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0;
-         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
-         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz_b_ost_d:2;
-        /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0;
-         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
-         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
-         */
-        uint32_t tz_b_ost_u:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg0_reg_t;
-
-/** Type of fh0_cfg1 register
- *  Software triggers for fault handler actions configuration register
- */
-typedef union {
-    struct {
-        /** tz_clr_ost : R/W; bitpos: [0]; default: 0;
-         *  Configures the generation of software one-shot mode action clear. A toggle
-         *  (software negate its value) triggers a clear for on going one-shot mode action.
-         */
-        uint32_t tz_clr_ost:1;
-        /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0;
-         *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
-         *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
-         */
-        uint32_t tz_cbcpulse:2;
-        /** tz_force_cbc : R/W; bitpos: [3]; default: 0;
-         *  Configures the generation of software cycle-by-cycle mode action. A toggle
-         *  (software negate its value) triggers a cycle-by-cycle mode action.
-         */
-        uint32_t tz_force_cbc:1;
-        /** tz_force_ost : R/W; bitpos: [4]; default: 0;
-         *  Configures the generation of software one-shot mode action. A toggle (software
-         *  negate its value) triggers a one-shot mode action.
-         */
-        uint32_t tz_force_ost:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg1_reg_t;
-
-/** Type of fh0_status register
- *  Fault events status register
- */
-typedef union {
-    struct {
-        /** tz_cbc_on : RO; bitpos: [0]; default: 0;
-         *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
-         *  action\\1: On going
-         */
-        uint32_t tz_cbc_on:1;
-        /** tz_ost_on : RO; bitpos: [1]; default: 0;
-         *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
-         *  going
-         */
-        uint32_t tz_ost_on:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} mcpwm_fh_status_reg_t;
-
-/** Group: fault_detect */
-/** Type of fault_detect register
- *  Fault detection configuration and status register
- */
-typedef union {
-    struct {
-        /** f0_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f0_en:1;
-        /** f1_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f1_en:1;
-        /** f2_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
-         */
-        uint32_t f2_en:1;
-        /** f0_pole : R/W; bitpos: [3]; default: 0;
-         *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f0_pole:1;
-        /** f1_pole : R/W; bitpos: [4]; default: 0;
-         *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f1_pole:1;
-        /** f2_pole : R/W; bitpos: [5]; default: 0;
-         *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
-         *  low\\1: Level high
-         */
-        uint32_t f2_pole:1;
-        /** event_f0 : RO; bitpos: [6]; default: 0;
-         *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f0:1;
-        /** event_f1 : RO; bitpos: [7]; default: 0;
-         *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f1:1;
-        /** event_f2 : RO; bitpos: [8]; default: 0;
-         *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
-         */
-        uint32_t event_f2:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} mcpwm_fault_detect_reg_t;
-
-
-/** Group: cap_timer_cfg */
-/** Type of cap_timer_cfg register
- *  Capture timer configuration register
- */
-typedef union {
-    struct {
-        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
-         */
-        uint32_t cap_timer_en:1;
-        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
-         */
-        uint32_t cap_synci_en:1;
-        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
-         *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
-         *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
-         *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
-         */
-        uint32_t cap_synci_sel:3;
-        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
-         *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
-         *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
-         *  value in phase register
-         */
-        uint32_t cap_sync_sw:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_cfg_reg_t;
-
-
-/** Group: cap_timer_phase */
-/** Type of cap_timer_phase register
- *  Capture timer sync phase register
- */
-typedef union {
-    struct {
-        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
-         *  Configures phase value for capture timer sync operation.
-         */
-        uint32_t cap_phase:32;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_phase_reg_t;
-
-
-/** Group: cap_chn_cfg */
-/** Type of cap_chn_cfg register
- *  Capture channel n configuration register
- */
-typedef union {
-    struct {
-        /** capn_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable
-         */
-        uint32_t capn_en:1;
-        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
-         *  Configures which edge of capture on channel n after prescaling is used.\\0:
-         *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
-         *  Enable capture on the positive edge
-         */
-        uint32_t capn_mode:2;
-        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Configures prescale value on possitive edge of CAPn. Prescale value =
-         *  PWM_CAPn_PRESCALE + 1
-         */
-        uint32_t capn_prescale:8;
-        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0:
-         *  Normal\\1: Invert
-         */
-        uint32_t capn_in_invert:1;
-        /** capn_sw : WT; bitpos: [12]; default: 0;
-         *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
-         *  software forced capture on channel n
-         */
-        uint32_t capn_sw:1;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_cfg_reg_t;
-
-
-/** Group: cap_chn */
-/** Type of cap_chn register
- *  CAPn capture value register
- */
-typedef union {
-    struct {
-        /** capn_value : RO; bitpos: [31:0]; default: 0;
-         *  Represents value of last capture on CAPn
-         */
-        uint32_t capn_value:32;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_reg_t;
-
-
-/** Group: cap_status */
-/** Type of cap_status register
- *  Last capture trigger edge information register
- */
-typedef union {
-    struct {
-        /** cap0_edge : RO; bitpos: [0]; default: 0;
-         *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap0_edge:1;
-        /** cap1_edge : RO; bitpos: [1]; default: 0;
-         *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap1_edge:1;
-        /** cap2_edge : RO; bitpos: [2]; default: 0;
-         *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
-         */
-        uint32_t cap2_edge:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} mcpwm_cap_status_reg_t;
-
-
-/** Group: update_cfg */
-/** Type of update_cfg register
- *  Generator Update configuration register
- */
-typedef union {
-    struct {
-        /** global_up_en : R/W; bitpos: [0]; default: 1;
-         *  Configures whether or not to enable global update for all active registers in MCPWM
-         *  module.\\0: Disable\\1: Enable
-         */
-        uint32_t global_up_en:1;
-        /** global_force_up : R/W; bitpos: [1]; default: 0;
-         *  Configures the generation of global forced update for all active registers in MCPWM
-         *  module. A toggle (software invert its value) will trigger a global forced update.
-         *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
-         */
-        uint32_t global_force_up:1;
-        /** op0_up_en : R/W; bitpos: [2]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op0_up_en:1;
-        /** op0_force_up : R/W; bitpos: [3]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator0. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
-         */
-        uint32_t op0_force_up:1;
-        /** op1_up_en : R/W; bitpos: [4]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op1_up_en:1;
-        /** op1_force_up : R/W; bitpos: [5]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator1. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
-         */
-        uint32_t op1_force_up:1;
-        /** op2_up_en : R/W; bitpos: [6]; default: 1;
-         *  Configures whether or not to enable update of active registers in PWM operator$n.
-         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
-         */
-        uint32_t op2_up_en:1;
-        /** op2_force_up : R/W; bitpos: [7]; default: 0;
-         *  Configures the generation of forced update for active registers in PWM operator2. A
-         *  toggle (software invert its value) will trigger a forced update. Valid only when
-         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
-         */
-        uint32_t op2_force_up:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} mcpwm_update_cfg_reg_t;
-
-
-/** Group: int_ena */
-/** Type of int_ena register
- *  Interrupt enable register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_ena:1;
-        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_ena:1;
-        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_ena:1;
-        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_ena:1;
-        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_ena:1;
-        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_ena:1;
-        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_ena:1;
-        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_ena:1;
-        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_ena:1;
-        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_ena:1;
-        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_ena:1;
-        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_ena:1;
-        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
-         */
-        uint32_t fault0_clr_int_ena:1;
-        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
-         */
-        uint32_t fault1_clr_int_ena:1;
-        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
-         */
-        uint32_t fault2_clr_int_ena:1;
-        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
-         */
-        uint32_t cmpr0_tea_int_ena:1;
-        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
-         */
-        uint32_t cmpr1_tea_int_ena:1;
-        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
-         */
-        uint32_t cmpr2_tea_int_ena:1;
-        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
-         */
-        uint32_t cmpr0_teb_int_ena:1;
-        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
-         */
-        uint32_t cmpr1_teb_int_ena:1;
-        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
-         */
-        uint32_t cmpr2_teb_int_ena:1;
-        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM0.
-         */
-        uint32_t tz0_cbc_int_ena:1;
-        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM1.
-         */
-        uint32_t tz1_cbc_int_ena:1;
-        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
-         *  action on PWM2.
-         */
-        uint32_t tz2_cbc_int_ena:1;
-        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_ost_int_ena:1;
-        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_ost_int_ena:1;
-        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_ost_int_ena:1;
-        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
-         */
-        uint32_t cap0_int_ena:1;
-        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
-         */
-        uint32_t cap1_int_ena:1;
-        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
-         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
-         */
-        uint32_t cap2_int_ena:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_ena_reg_t;
-
-
-/** Group: int_raw */
-/** Type of int_raw register
- *  Interrupt raw status register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  0 stops.
-         */
-        uint32_t timer0_stop_int_raw:1;
-        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  1 stops.
-         */
-        uint32_t timer1_stop_int_raw:1;
-        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
-         *  2 stops.
-         */
-        uint32_t timer2_stop_int_raw:1;
-        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  0 TEZ event.
-         */
-        uint32_t timer0_tez_int_raw:1;
-        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  1 TEZ event.
-         */
-        uint32_t timer1_tez_int_raw:1;
-        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  2 TEZ event.
-         */
-        uint32_t timer2_tez_int_raw:1;
-        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  0 TEP event.
-         */
-        uint32_t timer0_tep_int_raw:1;
-        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  1 TEP event.
-         */
-        uint32_t timer1_tep_int_raw:1;
-        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
-         *  2 TEP event.
-         */
-        uint32_t timer2_tep_int_raw:1;
-        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
-         *  starts.
-         */
-        uint32_t fault0_int_raw:1;
-        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
-         *  starts.
-         */
-        uint32_t fault1_int_raw:1;
-        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
-         *  starts.
-         */
-        uint32_t fault2_int_raw:1;
-        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
-         *  clears.
-         */
-        uint32_t fault0_clr_int_raw:1;
-        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
-         *  clears.
-         */
-        uint32_t fault1_clr_int_raw:1;
-        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
-         *  clears.
-         */
-        uint32_t fault2_clr_int_raw:1;
-        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_raw:1;
-        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_raw:1;
-        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_raw:1;
-        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_raw:1;
-        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_raw:1;
-        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_raw:1;
-        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t tz0_cbc_int_raw:1;
-        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t tz1_cbc_int_raw:1;
-        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t tz2_cbc_int_raw:1;
-        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_raw:1;
-        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_raw:1;
-        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
-         *  mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_raw:1;
-        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP0.
-         */
-        uint32_t cap0_int_raw:1;
-        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP1.
-         */
-        uint32_t cap1_int_raw:1;
-        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
-         *  CAP2.
-         */
-        uint32_t cap2_int_raw:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_raw_reg_t;
-
-
-/** Group: int_st */
-/** Type of int_st register
- *  Interrupt masked status register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 0 stops.
-         */
-        uint32_t timer0_stop_int_st:1;
-        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 1 stops.
-         */
-        uint32_t timer1_stop_int_st:1;
-        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
-         *  timer 2 stops.
-         */
-        uint32_t timer2_stop_int_st:1;
-        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_st:1;
-        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_st:1;
-        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_st:1;
-        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_st:1;
-        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_st:1;
-        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_st:1;
-        /** fault0_int_st : RO; bitpos: [9]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f0 starts.
-         */
-        uint32_t fault0_int_st:1;
-        /** fault1_int_st : RO; bitpos: [10]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f1 starts.
-         */
-        uint32_t fault1_int_st:1;
-        /** fault2_int_st : RO; bitpos: [11]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f2 starts.
-         */
-        uint32_t fault2_int_st:1;
-        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f0 clears.
-         */
-        uint32_t fault0_clr_int_st:1;
-        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f1 clears.
-         */
-        uint32_t fault1_clr_int_st:1;
-        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered when
-         *  event_f2 clears.
-         */
-        uint32_t fault2_clr_int_st:1;
-        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_st:1;
-        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_st:1;
-        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_st:1;
-        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_st:1;
-        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_st:1;
-        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
-         *  operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_st:1;
-        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t tz0_cbc_int_st:1;
-        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t tz1_cbc_int_st:1;
-        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t tz2_cbc_int_st:1;
-        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM0.
-         */
-        uint32_t tz0_ost_int_st:1;
-        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM1.
-         */
-        uint32_t tz1_ost_int_st:1;
-        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
-         *  one-shot mode action on PWM2.
-         */
-        uint32_t tz2_ost_int_st:1;
-        /** cap0_int_st : RO; bitpos: [27]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP0.
-         */
-        uint32_t cap0_int_st:1;
-        /** cap1_int_st : RO; bitpos: [28]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP1.
-         */
-        uint32_t cap1_int_st:1;
-        /** cap2_int_st : RO; bitpos: [29]; default: 0;
-         *  Masked status bit: The masked interrupt status of the interrupt triggered by
-         *  capture on CAP2.
-         */
-        uint32_t cap2_int_st:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_st_reg_t;
-
-
-/** Group: int_clr */
-/** Type of int_clr register
- *  Interrupt clear register
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_clr:1;
-        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_clr:1;
-        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_clr:1;
-        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_clr:1;
-        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_clr:1;
-        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_clr:1;
-        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_clr:1;
-        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_clr:1;
-        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_clr:1;
-        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
-         */
-        uint32_t fault0_int_clr:1;
-        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
-         */
-        uint32_t fault1_int_clr:1;
-        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
-         */
-        uint32_t fault2_int_clr:1;
-        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
-         */
-        uint32_t fault0_clr_int_clr:1;
-        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
-         */
-        uint32_t fault1_clr_int_clr:1;
-        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
-         */
-        uint32_t fault2_clr_int_clr:1;
-        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t cmpr0_tea_int_clr:1;
-        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t cmpr1_tea_int_clr:1;
-        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t cmpr2_tea_int_clr:1;
-        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t cmpr0_teb_int_clr:1;
-        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t cmpr1_teb_int_clr:1;
-        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t cmpr2_teb_int_clr:1;
-        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM0.
-         */
-        uint32_t tz0_cbc_int_clr:1;
-        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM1.
-         */
-        uint32_t tz1_cbc_int_clr:1;
-        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM2.
-         */
-        uint32_t tz2_cbc_int_clr:1;
-        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM0.
-         */
-        uint32_t tz0_ost_int_clr:1;
-        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM1.
-         */
-        uint32_t tz1_ost_int_clr:1;
-        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
-         *  PWM2.
-         */
-        uint32_t tz2_ost_int_clr:1;
-        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
-         */
-        uint32_t cap0_int_clr:1;
-        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
-         */
-        uint32_t cap1_int_clr:1;
-        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
-         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
-         */
-        uint32_t cap2_int_clr:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_int_clr_reg_t;
-
-
-/** Group: evt_en */
-/** Type of evt_en register
- *  Event enable register
- */
-typedef union {
-    struct {
-        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer0_stop_en:1;
-        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer1_stop_en:1;
-        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_timer2_stop_en:1;
-        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable timer0 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer0_tez_en:1;
-        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable timer1 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer1_tez_en:1;
-        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable timer2 equal zero event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer2_tez_en:1;
-        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable timer0 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer0_tep_en:1;
-        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable timer1 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer1_tep_en:1;
-        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable timer2 equal period event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_timer2_tep_en:1;
-        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tea_en:1;
-        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tea_en:1;
-        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal a event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tea_en:1;
-        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_teb_en:1;
-        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_teb_en:1;
-        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal b event
-         *  generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_teb_en:1;
-        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f0_en:1;
-        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f1_en:1;
-        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_f2_en:1;
-        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f0_clr_en:1;
-        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f1_clr_en:1;
-        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_f2_clr_en:1;
-        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz0_cbc_en:1;
-        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz1_cbc_en:1;
-        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
-         *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t evt_tz2_cbc_en:1;
-        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
-         *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz0_ost_en:1;
-        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
-         *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz1_ost_en:1;
-        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
-         *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t evt_tz2_ost_en:1;
-        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
-         *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap0_en:1;
-        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
-         *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap1_en:1;
-        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
-         *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_cap2_en:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} mcpwm_evt_en_reg_t;
-
-
-/** Group: task_en */
-/** Type of task_en register
- *  Task enable register
- */
-typedef union {
-    struct {
-        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr0_a_up_en:1;
-        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr1_a_up_en:1;
-        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr2_a_up_en:1;
-        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr0_b_up_en:1;
-        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr1_b_up_en:1;
-        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
-         *  update task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cmpr2_b_up_en:1;
-        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
-         *  Configures whether or not to enable all PWM generate stop task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_gen_stop_en:1;
-        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
-         *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer0_sync_en:1;
-        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
-         *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer1_sync_en:1;
-        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
-         *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_timer2_sync_en:1;
-        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
-         *  Configures whether or not to enable timer0 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer0_period_up_en:1;
-        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
-         *  Configures whether or not to enable timer1 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer1_period_up_en:1;
-        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
-         *  Configures whether or not to enable timer2 period update task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_timer2_period_up_en:1;
-        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
-         *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz0_ost_en:1;
-        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
-         *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz1_ost_en:1;
-        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
-         *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
-         *  Enable
-         */
-        uint32_t task_tz2_ost_en:1;
-        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
-         *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr0_ost_en:1;
-        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
-         *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr1_ost_en:1;
-        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
-         *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
-         *  Disable\\1: Enable
-         */
-        uint32_t task_clr2_ost_en:1;
-        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
-         *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap0_en:1;
-        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
-         *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap1_en:1;
-        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
-         *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
-         */
-        uint32_t task_cap2_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} mcpwm_task_en_reg_t;
-
-
-/** Group: evt_en2 */
-/** Type of evt_en2 register
- *  Event enable register2
- */
-typedef union {
-    struct {
-        /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tee1_en:1;
-        /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tee1_en:1;
-        /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tee1_en:1;
-        /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0;
-         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op0_tee2_en:1;
-        /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0;
-         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op1_tee2_en:1;
-        /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0;
-         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
-         *  event generate.\\0: Disable\\1: Enable
-         */
-        uint32_t evt_op2_tee2_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} mcpwm_evt_en2_reg_t;
-
-
-/** Group: Configuration register */
-/** Type of opn_tstmp_e1 register
- *  Generatorn timer stamp E1 value register
- */
-typedef union {
-    struct {
-        /** op_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
-         *  Configures generatorn timer stamp E1 value register
-         */
-        uint32_t op_tstmp_e:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} mcpwm_op_tstmp_reg_t;
-
-/** Type of clk register
- *  Global configuration register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
-         *  when application writes registers\\1: Force open the clock gate for register
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} mcpwm_clk_reg_t;
-
-
-/** Group: Version register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725968;
-         *  Configures the version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} mcpwm_version_reg_t;
-
-typedef struct {
-    volatile mcpwm_timer_cfg0_reg_t timer_cfg0;
-    volatile mcpwm_timer_cfg1_reg_t timer_cfg1;
-    volatile mcpwm_timer_sync_reg_t timer_sync;
-    volatile mcpwm_timer_status_reg_t timer_status;
-} mcpwm_timer_regs_t;
-
-typedef struct {
-    volatile mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
-    volatile mcpwm_gen_tstmp_reg_t timestamp[2];
-    volatile mcpwm_gen_cfg0_reg_t gen_cfg0;
-    volatile mcpwm_gen_force_reg_t gen_force;
-    volatile mcpwm_gen_reg_t generator[2];
-    volatile mcpwm_dt_cfg_reg_t dt_cfg;
-    volatile mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
-    volatile mcpwm_dt_red_cfg_reg_t dt_red_cfg;
-    volatile mcpwm_carrier_cfg_reg_t carrier_cfg;
-    volatile mcpwm_fh_cfg0_reg_t fh_cfg0;
-    volatile mcpwm_fh_cfg1_reg_t fh_cfg1;
-    volatile mcpwm_fh_status_reg_t fh_status;
-} mcpwm_operator_reg_t;
-
-typedef struct {
-    volatile mcpwm_op_tstmp_reg_t timestamp[2];
-} mcpwm_operator_tstmp_reg_t;
-
-typedef struct mcpwm_dev_t {
-    volatile mcpwm_clk_cfg_reg_t clk_cfg;
-    volatile mcpwm_timer_regs_t timer[3];
-    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
-    volatile mcpwm_operator_timersel_reg_t operator_timersel;
-    volatile mcpwm_operator_reg_t operators[3];
-    volatile mcpwm_fault_detect_reg_t fault_detect;
-    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
-    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
-    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
-    volatile mcpwm_cap_chn_reg_t cap_chn[3];
-    volatile mcpwm_cap_status_reg_t cap_status;
-    volatile mcpwm_update_cfg_reg_t update_cfg;
-    volatile mcpwm_int_ena_reg_t int_ena;
-    volatile mcpwm_int_raw_reg_t int_raw;
-    volatile mcpwm_int_st_reg_t int_st;
-    volatile mcpwm_int_clr_reg_t int_clr;
-    volatile mcpwm_evt_en_reg_t evt_en;
-    volatile mcpwm_task_en_reg_t task_en;
-    volatile mcpwm_evt_en2_reg_t evt_en2;
-    volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3];
-    volatile mcpwm_clk_reg_t clk;
-    volatile mcpwm_version_reg_t version;
-} mcpwm_dev_t;
-
-extern mcpwm_dev_t MCPWM0;
-extern mcpwm_dev_t MCPWM1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/parl_io_reg.h b/components/soc/esp32p4/include/soc/parl_io_reg.h
deleted file mode 100644
index 74a528017d9..00000000000
--- a/components/soc/esp32p4/include/soc/parl_io_reg.h
+++ /dev/null
@@ -1,480 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** PARL_IO_RX_MODE_CFG_REG register
- *  Parallel RX Sampling mode configuration register.
- */
-#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
-/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
- *  Configures rx external enable signal selection from IO PAD.
- */
-#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
-#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
-#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
-#define PARL_IO_RX_EXT_EN_SEL_S  21
-/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
- *  Set this bit to enable data sampling by software.
- */
-#define PARL_IO_RX_SW_EN    (BIT(25))
-#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
-#define PARL_IO_RX_SW_EN_V  0x00000001U
-#define PARL_IO_RX_SW_EN_S  25
-/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
- *  Set this bit to invert the external enable signal.
- */
-#define PARL_IO_RX_EXT_EN_INV    (BIT(26))
-#define PARL_IO_RX_EXT_EN_INV_M  (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
-#define PARL_IO_RX_EXT_EN_INV_V  0x00000001U
-#define PARL_IO_RX_EXT_EN_INV_S  26
-/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
- *  Configures the rxd pulse sampling submode.
- *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
- *  included)
- *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
- *  excluded)
- *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
- *  included)
- *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
- *  excluded)
- *  4'd4: positive pulse start(data bit included) && length end
- *  4'd5: positive pulse start(data bit excluded) && length end
- */
-#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x00000007U
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x00000007U
-#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  27
-/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
- *  Configures the rxd sampling mode.
- *  2'b00: external level enable mode
- *  2'b01: external pulse enable mode
- *  2'b10: internal software enable mode
- */
-#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
-#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
-#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
-#define PARL_IO_RX_SMP_MODE_SEL_S  30
-
-/** PARL_IO_RX_DATA_CFG_REG register
- *  Parallel RX data configuration register.
- */
-#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
-/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
- *  Configures expected byte number of received data.
- */
-#define PARL_IO_RX_BITLEN    0x0007FFFFU
-#define PARL_IO_RX_BITLEN_M  (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
-#define PARL_IO_RX_BITLEN_V  0x0007FFFFU
-#define PARL_IO_RX_BITLEN_S  9
-/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
- *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
- */
-#define PARL_IO_RX_DATA_ORDER_INV    (BIT(28))
-#define PARL_IO_RX_DATA_ORDER_INV_M  (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
-#define PARL_IO_RX_DATA_ORDER_INV_V  0x00000001U
-#define PARL_IO_RX_DATA_ORDER_INV_S  28
-/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
- *  Configures the rxd bus width.
- *  3'd0: bus width is 1.
- *  3'd1: bus width is 2.
- *  3'd2: bus width is 4.
- *  3'd3: bus width is 8.
- */
-#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
-#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
-#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
-#define PARL_IO_RX_BUS_WID_SEL_S  29
-
-/** PARL_IO_RX_GENRL_CFG_REG register
- *  Parallel RX general configuration register.
- */
-#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
-/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable the clock gating of output rx clock.
- */
-#define PARL_IO_RX_GATING_EN    (BIT(12))
-#define PARL_IO_RX_GATING_EN_M  (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
-#define PARL_IO_RX_GATING_EN_V  0x00000001U
-#define PARL_IO_RX_GATING_EN_S  12
-/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
- *  Configures threshold of timeout counter.
- */
-#define PARL_IO_RX_TIMEOUT_THRES    0x0000FFFFU
-#define PARL_IO_RX_TIMEOUT_THRES_M  (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
-#define PARL_IO_RX_TIMEOUT_THRES_V  0x0000FFFFU
-#define PARL_IO_RX_TIMEOUT_THRES_S  13
-/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
- *  Set this bit to enable timeout function to generate error eof.
- */
-#define PARL_IO_RX_TIMEOUT_EN    (BIT(29))
-#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
-#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
-#define PARL_IO_RX_TIMEOUT_EN_S  29
-/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
- *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
- *  1'b1: eof generated by external enable signal.
- */
-#define PARL_IO_RX_EOF_GEN_SEL    (BIT(30))
-#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
-#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
-#define PARL_IO_RX_EOF_GEN_SEL_S  30
-
-/** PARL_IO_RX_START_CFG_REG register
- *  Parallel RX Start configuration register.
- */
-#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
-/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
- *  Set this bit to start rx data sampling.
- */
-#define PARL_IO_RX_START    (BIT(31))
-#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
-#define PARL_IO_RX_START_V  0x00000001U
-#define PARL_IO_RX_START_S  31
-
-/** PARL_IO_TX_DATA_CFG_REG register
- *  Parallel TX data configuration register.
- */
-#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
-/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
- *  Configures expected byte number of sent data.
- */
-#define PARL_IO_TX_BITLEN    0x0007FFFFU
-#define PARL_IO_TX_BITLEN_M  (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
-#define PARL_IO_TX_BITLEN_V  0x0007FFFFU
-#define PARL_IO_TX_BITLEN_S  9
-/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
- *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
- */
-#define PARL_IO_TX_DATA_ORDER_INV    (BIT(28))
-#define PARL_IO_TX_DATA_ORDER_INV_M  (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
-#define PARL_IO_TX_DATA_ORDER_INV_V  0x00000001U
-#define PARL_IO_TX_DATA_ORDER_INV_S  28
-/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
- *  Configures the txd bus width.
- *  3'd0: bus width is 1.
- *  3'd1: bus width is 2.
- *  3'd2: bus width is 4.
- *  3'd3: bus width is 8.
- */
-#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
-#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
-#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
-#define PARL_IO_TX_BUS_WID_SEL_S  29
-
-/** PARL_IO_TX_START_CFG_REG register
- *  Parallel TX Start configuration register.
- */
-#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
-/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
- *  Set this bit to start tx data transmit.
- */
-#define PARL_IO_TX_START    (BIT(31))
-#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
-#define PARL_IO_TX_START_V  0x00000001U
-#define PARL_IO_TX_START_S  31
-
-/** PARL_IO_TX_GENRL_CFG_REG register
- *  Parallel TX general configuration register.
- */
-#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
-/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
- *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
- *  1'b1: eof generated by DMA eof.
- */
-#define PARL_IO_TX_EOF_GEN_SEL    (BIT(13))
-#define PARL_IO_TX_EOF_GEN_SEL_M  (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
-#define PARL_IO_TX_EOF_GEN_SEL_V  0x00000001U
-#define PARL_IO_TX_EOF_GEN_SEL_S  13
-/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
- *  Configures bus value of transmitter in IDLE state.
- */
-#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
-#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
-#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
-#define PARL_IO_TX_IDLE_VALUE_S  14
-/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
- *  Set this bit to enable the clock gating of output tx clock.
- */
-#define PARL_IO_TX_GATING_EN    (BIT(30))
-#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
-#define PARL_IO_TX_GATING_EN_V  0x00000001U
-#define PARL_IO_TX_GATING_EN_S  30
-/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
- *  Set this bit to enable the output of tx data valid signal.
- */
-#define PARL_IO_TX_VALID_OUTPUT_EN    (BIT(31))
-#define PARL_IO_TX_VALID_OUTPUT_EN_M  (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
-#define PARL_IO_TX_VALID_OUTPUT_EN_V  0x00000001U
-#define PARL_IO_TX_VALID_OUTPUT_EN_S  31
-
-/** PARL_IO_FIFO_CFG_REG register
- *  Parallel IO FIFO configuration register.
- */
-#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
-/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
- *  Set this bit to reset async fifo in tx module.
- */
-#define PARL_IO_TX_FIFO_SRST    (BIT(30))
-#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
-#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
-#define PARL_IO_TX_FIFO_SRST_S  30
-/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
- *  Set this bit to reset async fifo in rx module.
- */
-#define PARL_IO_RX_FIFO_SRST    (BIT(31))
-#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
-#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
-#define PARL_IO_RX_FIFO_SRST_S  31
-
-/** PARL_IO_REG_UPDATE_REG register
- *  Parallel IO FIFO configuration register.
- */
-#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
-/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
- *  Set this bit to update rx register configuration.
- */
-#define PARL_IO_RX_REG_UPDATE    (BIT(31))
-#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
-#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
-#define PARL_IO_RX_REG_UPDATE_S  31
-
-/** PARL_IO_ST_REG register
- *  Parallel IO module status register0.
- */
-#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
-/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
- *  Represents the status that tx is ready to transmit.
- */
-#define PARL_IO_TX_READY    (BIT(31))
-#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
-#define PARL_IO_TX_READY_V  0x00000001U
-#define PARL_IO_TX_READY_S  31
-
-/** PARL_IO_INT_ENA_REG register
- *  Parallel IO interrupt enable singal configuration register.
- */
-#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
-/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M  (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S  1
-/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
-#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
-#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_ENA_S  2
-
-/** PARL_IO_INT_RAW_REG register
- *  Parallel IO interrupt raw singal status register.
- */
-#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
-/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt status of TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt status of RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M  (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S  1
-/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt status of TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
-#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
-#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_RAW_S  2
-
-/** PARL_IO_INT_ST_REG register
- *  Parallel IO interrupt singal status register.
- */
-#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
-/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status of TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status of RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_ST    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_M  (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_ST_S  1
-/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status of TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
-#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
-#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_ST_S  2
-
-/** PARL_IO_INT_CLR_REG register
- *  Parallel IO interrupt  clear singal configuration register.
- */
-#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
-/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear TX_FIFO_REMPTY_INT.
- */
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
-#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
-/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear RX_FIFO_WOVF_INT.
- */
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR    (BIT(1))
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M  (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V  0x00000001U
-#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S  1
-/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear TX_EOF_INT.
- */
-#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
-#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
-#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
-#define PARL_IO_TX_EOF_INT_CLR_S  2
-
-/** PARL_IO_RX_ST0_REG register
- *  Parallel IO RX status register0
- */
-#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
-/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
- *  Indicates the cycle number of reading Rx FIFO.
- */
-#define PARL_IO_RX_CNT    0x0000001FU
-#define PARL_IO_RX_CNT_M  (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
-#define PARL_IO_RX_CNT_V  0x0000001FU
-#define PARL_IO_RX_CNT_S  8
-/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current written bit number into Rx FIFO.
- */
-#define PARL_IO_RX_FIFO_WR_BIT_CNT    0x0007FFFFU
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_M  (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_RX_FIFO_WR_BIT_CNT_S  13
-
-/** PARL_IO_RX_ST1_REG register
- *  Parallel IO RX status register1
- */
-#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
-/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current read bit number from Rx FIFO.
- */
-#define PARL_IO_RX_FIFO_RD_BIT_CNT    0x0007FFFFU
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_M  (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_RX_FIFO_RD_BIT_CNT_S  13
-
-/** PARL_IO_TX_ST0_REG register
- *  Parallel IO TX status register0
- */
-#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
-/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
- *  Indicates the cycle number of reading Tx FIFO.
- */
-#define PARL_IO_TX_CNT    0x0000007FU
-#define PARL_IO_TX_CNT_M  (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
-#define PARL_IO_TX_CNT_V  0x0000007FU
-#define PARL_IO_TX_CNT_S  6
-/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
- *  Indicates the current read bit number from Tx FIFO.
- */
-#define PARL_IO_TX_FIFO_RD_BIT_CNT    0x0007FFFFU
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_M  (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
-#define PARL_IO_TX_FIFO_RD_BIT_CNT_S  13
-
-/** PARL_IO_RX_CLK_CFG_REG register
- *  Parallel IO RX clk configuration register
- */
-#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
-/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
- *  Set this bit to invert the input Rx core clock.
- */
-#define PARL_IO_RX_CLK_I_INV    (BIT(30))
-#define PARL_IO_RX_CLK_I_INV_M  (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
-#define PARL_IO_RX_CLK_I_INV_V  0x00000001U
-#define PARL_IO_RX_CLK_I_INV_S  30
-/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
- *  Set this bit to invert the output Rx core clock.
- */
-#define PARL_IO_RX_CLK_O_INV    (BIT(31))
-#define PARL_IO_RX_CLK_O_INV_M  (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
-#define PARL_IO_RX_CLK_O_INV_V  0x00000001U
-#define PARL_IO_RX_CLK_O_INV_S  31
-
-/** PARL_IO_TX_CLK_CFG_REG register
- *  Parallel IO TX clk configuration register
- */
-#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
-/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
- *  Set this bit to invert the input Tx core clock.
- */
-#define PARL_IO_TX_CLK_I_INV    (BIT(30))
-#define PARL_IO_TX_CLK_I_INV_M  (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
-#define PARL_IO_TX_CLK_I_INV_V  0x00000001U
-#define PARL_IO_TX_CLK_I_INV_S  30
-/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
- *  Set this bit to invert the output Tx core clock.
- */
-#define PARL_IO_TX_CLK_O_INV    (BIT(31))
-#define PARL_IO_TX_CLK_O_INV_M  (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
-#define PARL_IO_TX_CLK_O_INV_V  0x00000001U
-#define PARL_IO_TX_CLK_O_INV_S  31
-
-/** PARL_IO_CLK_REG register
- *  Parallel IO clk configuration register
- */
-#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
-/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  Force clock on for this register file
- */
-#define PARL_IO_CLK_EN    (BIT(31))
-#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
-#define PARL_IO_CLK_EN_V  0x00000001U
-#define PARL_IO_CLK_EN_S  31
-
-/** PARL_IO_VERSION_REG register
- *  Version register.
- */
-#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
-/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920;
- *  Version of this register file
- */
-#define PARL_IO_DATE    0x0FFFFFFFU
-#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
-#define PARL_IO_DATE_V  0x0FFFFFFFU
-#define PARL_IO_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/parl_io_struct.h b/components/soc/esp32p4/include/soc/parl_io_struct.h
deleted file mode 100644
index aea2cb383b8..00000000000
--- a/components/soc/esp32p4/include/soc/parl_io_struct.h
+++ /dev/null
@@ -1,509 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PARL_IO RX  Mode Configuration */
-/** Type of rx_mode_cfg register
- *  Parallel RX Sampling mode configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
-         *  Configures rx external enable signal selection from IO PAD.
-         */
-        uint32_t rx_ext_en_sel:4;
-        /** rx_sw_en : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to enable data sampling by software.
-         */
-        uint32_t rx_sw_en:1;
-        /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to invert the external enable signal.
-         */
-        uint32_t rx_ext_en_inv:1;
-        /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
-         *  Configures the rxd pulse sampling submode.
-         *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
-         *  included)
-         *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
-         *  excluded)
-         *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
-         *  included)
-         *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
-         *  excluded)
-         *  4'd4: positive pulse start(data bit included) && length end
-         *  4'd5: positive pulse start(data bit excluded) && length end
-         */
-        uint32_t rx_pulse_submode_sel:3;
-        /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
-         *  Configures the rxd sampling mode.
-         *  2'b00: external level enable mode
-         *  2'b01: external pulse enable mode
-         *  2'b10: internal software enable mode
-         */
-        uint32_t rx_smp_mode_sel:2;
-    };
-    uint32_t val;
-} parl_io_rx_mode_cfg_reg_t;
-
-
-/** Group: PARL_IO RX Data Configuration */
-/** Type of rx_data_cfg register
- *  Parallel RX data configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
-         *  Configures expected byte number of received data.
-         */
-        uint32_t rx_bitlen:19;
-        /** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
-         */
-        uint32_t rx_data_order_inv:1;
-        /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
-         *  Configures the rxd bus width.
-         *  3'd0: bus width is 1.
-         *  3'd1: bus width is 2.
-         *  3'd2: bus width is 4.
-         *  3'd3: bus width is 8.
-         */
-        uint32_t rx_bus_wid_sel:3;
-    };
-    uint32_t val;
-} parl_io_rx_data_cfg_reg_t;
-
-
-/** Group: PARL_IO RX General Configuration */
-/** Type of rx_genrl_cfg register
- *  Parallel RX general configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:12;
-        /** rx_gating_en : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable the clock gating of output rx clock.
-         */
-        uint32_t rx_gating_en:1;
-        /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
-         *  Configures threshold of timeout counter.
-         */
-        uint32_t rx_timeout_thres:16;
-        /** rx_timeout_en : R/W; bitpos: [29]; default: 1;
-         *  Set this bit to enable timeout function to generate error eof.
-         */
-        uint32_t rx_timeout_en:1;
-        /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
-         *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
-         *  1'b1: eof generated by external enable signal.
-         */
-        uint32_t rx_eof_gen_sel:1;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} parl_io_rx_genrl_cfg_reg_t;
-
-
-/** Group: PARL_IO RX Start Configuration */
-/** Type of rx_start_cfg register
- *  Parallel RX Start configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** rx_start : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to start rx data sampling.
-         */
-        uint32_t rx_start:1;
-    };
-    uint32_t val;
-} parl_io_rx_start_cfg_reg_t;
-
-
-/** Group: PARL_IO TX Data Configuration */
-/** Type of tx_data_cfg register
- *  Parallel TX data configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:9;
-        /** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
-         *  Configures expected byte number of sent data.
-         */
-        uint32_t tx_bitlen:19;
-        /** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
-         */
-        uint32_t tx_data_order_inv:1;
-        /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
-         *  Configures the txd bus width.
-         *  3'd0: bus width is 1.
-         *  3'd1: bus width is 2.
-         *  3'd2: bus width is 4.
-         *  3'd3: bus width is 8.
-         */
-        uint32_t tx_bus_wid_sel:3;
-    };
-    uint32_t val;
-} parl_io_tx_data_cfg_reg_t;
-
-
-/** Group: PARL_IO TX Start Configuration */
-/** Type of tx_start_cfg register
- *  Parallel TX Start configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_start : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to start tx data transmit.
-         */
-        uint32_t tx_start:1;
-    };
-    uint32_t val;
-} parl_io_tx_start_cfg_reg_t;
-
-
-/** Group: PARL_IO TX General Configuration */
-/** Type of tx_genrl_cfg register
- *  Parallel TX general configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:13;
-        /** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
-         *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
-         *  1'b1: eof generated by DMA eof.
-         */
-        uint32_t tx_eof_gen_sel:1;
-        /** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
-         *  Configures bus value of transmitter in IDLE state.
-         */
-        uint32_t tx_idle_value:16;
-        /** tx_gating_en : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to enable the clock gating of output tx clock.
-         */
-        uint32_t tx_gating_en:1;
-        /** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to enable the output of tx data valid signal.
-         */
-        uint32_t tx_valid_output_en:1;
-    };
-    uint32_t val;
-} parl_io_tx_genrl_cfg_reg_t;
-
-
-/** Group: PARL_IO FIFO Configuration */
-/** Type of fifo_cfg register
- *  Parallel IO FIFO configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to reset async fifo in tx module.
-         */
-        uint32_t tx_fifo_srst:1;
-        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to reset async fifo in rx module.
-         */
-        uint32_t rx_fifo_srst:1;
-    };
-    uint32_t val;
-} parl_io_fifo_cfg_reg_t;
-
-
-/** Group: PARL_IO Register Update Configuration */
-/** Type of reg_update register
- *  Parallel IO FIFO configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** rx_reg_update : WT; bitpos: [31]; default: 0;
-         *  Set this bit to update rx register configuration.
-         */
-        uint32_t rx_reg_update:1;
-    };
-    uint32_t val;
-} parl_io_reg_update_reg_t;
-
-
-/** Group: PARL_IO Status */
-/** Type of st register
- *  Parallel IO module status register0.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** tx_ready : RO; bitpos: [31]; default: 0;
-         *  Represents the status that tx is ready to transmit.
-         */
-        uint32_t tx_ready:1;
-    };
-    uint32_t val;
-} parl_io_st_reg_t;
-
-
-/** Group: PARL_IO Interrupt Configuration and Status */
-/** Type of int_ena register
- *  Parallel IO interrupt enable singal configuration register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_ena:1;
-        /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_ena:1;
-        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to enable TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_ena:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Parallel IO interrupt raw singal status register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw interrupt status of TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_raw:1;
-        /** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw interrupt status of RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_raw:1;
-        /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw interrupt status of TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_raw:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_raw_reg_t;
-
-/** Type of int_st register
- *  Parallel IO interrupt singal status register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status of TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_st:1;
-        /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status of RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_st:1;
-        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status of TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_st:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_st_reg_t;
-
-/** Type of int_clr register
- *  Parallel IO interrupt  clear singal configuration register.
- */
-typedef union {
-    struct {
-        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear TX_FIFO_REMPTY_INT.
-         */
-        uint32_t tx_fifo_rempty_int_clr:1;
-        /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear RX_FIFO_WOVF_INT.
-         */
-        uint32_t rx_fifo_wovf_int_clr:1;
-        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear TX_EOF_INT.
-         */
-        uint32_t tx_eof_int_clr:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} parl_io_int_clr_reg_t;
-
-
-/** Group: PARL_IO Rx Status0 */
-/** Type of rx_st0 register
- *  Parallel IO RX status register0
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** rx_cnt : RO; bitpos: [12:8]; default: 0;
-         *  Indicates the cycle number of reading Rx FIFO.
-         */
-        uint32_t rx_cnt:5;
-        /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current written bit number into Rx FIFO.
-         */
-        uint32_t rx_fifo_wr_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_rx_st0_reg_t;
-
-
-/** Group: PARL_IO Rx Status1 */
-/** Type of rx_st1 register
- *  Parallel IO RX status register1
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:13;
-        /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current read bit number from Rx FIFO.
-         */
-        uint32_t rx_fifo_rd_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_rx_st1_reg_t;
-
-
-/** Group: PARL_IO Tx Status0 */
-/** Type of tx_st0 register
- *  Parallel IO TX status register0
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:6;
-        /** tx_cnt : RO; bitpos: [12:6]; default: 0;
-         *  Indicates the cycle number of reading Tx FIFO.
-         */
-        uint32_t tx_cnt:7;
-        /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
-         *  Indicates the current read bit number from Tx FIFO.
-         */
-        uint32_t tx_fifo_rd_bit_cnt:19;
-    };
-    uint32_t val;
-} parl_io_tx_st0_reg_t;
-
-
-/** Group: PARL_IO Rx Clock Configuration */
-/** Type of rx_clk_cfg register
- *  Parallel IO RX clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to invert the input Rx core clock.
-         */
-        uint32_t rx_clk_i_inv:1;
-        /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to invert the output Rx core clock.
-         */
-        uint32_t rx_clk_o_inv:1;
-    };
-    uint32_t val;
-} parl_io_rx_clk_cfg_reg_t;
-
-
-/** Group: PARL_IO Tx Clock Configuration */
-/** Type of tx_clk_cfg register
- *  Parallel IO TX clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:30;
-        /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
-         *  Set this bit to invert the input Tx core clock.
-         */
-        uint32_t tx_clk_i_inv:1;
-        /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to invert the output Tx core clock.
-         */
-        uint32_t tx_clk_o_inv:1;
-    };
-    uint32_t val;
-} parl_io_tx_clk_cfg_reg_t;
-
-
-/** Group: PARL_IO Clock Configuration */
-/** Type of clk register
- *  Parallel IO clk configuration register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:31;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Force clock on for this register file
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} parl_io_clk_reg_t;
-
-
-/** Group: PARL_IO Version Register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35725920;
-         *  Version of this register file
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} parl_io_version_reg_t;
-
-
-typedef struct parl_io_dev_t {
-    volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
-    volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
-    volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
-    volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
-    volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
-    volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
-    volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
-    volatile parl_io_fifo_cfg_reg_t fifo_cfg;
-    volatile parl_io_reg_update_reg_t reg_update;
-    volatile parl_io_st_reg_t st;
-    volatile parl_io_int_ena_reg_t int_ena;
-    volatile parl_io_int_raw_reg_t int_raw;
-    volatile parl_io_int_st_reg_t int_st;
-    volatile parl_io_int_clr_reg_t int_clr;
-    volatile parl_io_rx_st0_reg_t rx_st0;
-    volatile parl_io_rx_st1_reg_t rx_st1;
-    volatile parl_io_tx_st0_reg_t tx_st0;
-    volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
-    volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
-    uint32_t reserved_04c[53];
-    volatile parl_io_clk_reg_t clk;
-    uint32_t reserved_124[182];
-    volatile parl_io_version_reg_t version;
-} parl_io_dev_t;
-
-extern parl_io_dev_t PARL_IO;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/periph_defs.h b/components/soc/esp32p4/include/soc/periph_defs.h
index cadf54fdf7c..41f59d69a36 100644
--- a/components/soc/esp32p4/include/soc/periph_defs.h
+++ b/components/soc/esp32p4/include/soc/periph_defs.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -69,9 +69,14 @@ typedef enum {
     PERIPH_UHCI_MODULE,
     PERIPH_PCNT_MODULE,
     PERIPH_ASSIST_DEBUG_MODULE,
+
     /* LP peripherals */
     PERIPH_LP_I2C0_MODULE,
     PERIPH_LP_UART0_MODULE,
+
+    /* MISC */
+    PERIPH_ANA_I2C_MASTER_MODULE,
+
     PERIPH_MODULE_MAX
 } periph_module_t;
 
diff --git a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
index 9021eaaba7d..f81d1da6f46 100644
--- a/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
+++ b/components/soc/esp32p4/include/soc/pmu_icg_mapping.h
@@ -6,8 +6,6 @@
 
 #pragma once
 
-// TODO: IDF-5731
-
 #define PMU_ICG_APB_ENA_CORE0_CPU          0
 #define PMU_ICG_APB_ENA_CORE1_CPU          1
 #define PMU_ICG_APB_ENA_CORE0_CLIC         2
diff --git a/components/soc/esp32p4/include/soc/pmu_struct.h b/components/soc/esp32p4/include/soc/pmu_struct.h
deleted file mode 100644
index f8727c5c88e..00000000000
--- a/components/soc/esp32p4/include/soc/pmu_struct.h
+++ /dev/null
@@ -1,933 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/pmu_reg.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 21;
-        uint32_t dcdc_switch_pd_en :1;
-        uint32_t mem_dslp     : 1;
-        uint32_t mem_pd_en    : 1;
-        uint32_t reserved1    : 6;
-        uint32_t cnnt_pd_en   : 1;
-        uint32_t top_pd_en    : 1;
-    };
-    uint32_t val;
-} pmu_hp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 23;
-        uint32_t power_det_bypass : 1;
-        uint32_t uart_wakeup_en : 1;
-        uint32_t lp_pad_hold_all: 1;
-        uint32_t hp_pad_hold_all: 1;
-        uint32_t dig_pad_slp_sel: 1;
-        uint32_t dig_pause_wdt  : 1;
-        uint32_t dig_cpu_stall  : 1;
-        uint32_t reserved1      : 2;
-    };
-    uint32_t val;
-} pmu_hp_sys_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0    : 21;
-        uint32_t i2c_iso_en   : 1;
-        uint32_t i2c_retention: 1;
-        uint32_t xpd_pll_i2c  : 4;
-        uint32_t xpd_pll      : 4;
-        uint32_t reserved1    : 1;
-    };
-    uint32_t val;
-} pmu_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 18;
-        uint32_t dcm_vset  : 5;
-        uint32_t dcm_mode  : 2;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_hp_bias_reg_t;
-
-typedef union {
-    struct {    /* HP: Active State */
-        uint32_t reserved0                            : 4;
-        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
-        uint32_t hp_modem2active_backup_modem_clk_code: 2;
-        uint32_t reserved1                            : 2;
-        uint32_t hp_active_retention_mode             : 1;
-        uint32_t hp_sleep2active_retention_en         : 1;
-        uint32_t hp_modem2active_retention_en         : 1;
-        uint32_t reserved2                            : 1;
-        uint32_t hp_sleep2active_backup_clk_sel       : 2;
-        uint32_t hp_modem2active_backup_clk_sel       : 2;
-        uint32_t reserved3                            : 2;
-        uint32_t hp_sleep2active_backup_mode          : 3;
-        uint32_t hp_modem2active_backup_mode          : 3;
-        uint32_t reserved4                            : 3;
-        uint32_t hp_sleep2active_backup_en            : 1;
-        uint32_t hp_modem2active_backup_en            : 1;
-        uint32_t reserved5                            : 1;
-    };
-    struct {    /* HP: Modem State */
-        uint32_t reserved6                            : 32;
-    };
-    struct {    /* HP: Sleep State */
-        uint32_t reserved12                           : 6;
-        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
-        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
-        uint32_t hp_sleep_retention_mode              : 1;
-        uint32_t reserved13                           : 1;
-        uint32_t hp_modem2sleep_retention_en          : 1;
-        uint32_t hp_active2sleep_retention_en         : 1;
-        uint32_t reserved14                           : 2;
-        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
-        uint32_t hp_active2sleep_backup_clk_sel       : 2;
-        uint32_t reserved15                           : 3;
-        uint32_t hp_modem2sleep_backup_mode           : 3;
-        uint32_t hp_active2sleep_backup_mode          : 3;
-        uint32_t reserved16                           : 1;
-        uint32_t hp_modem2sleep_backup_en             : 1;
-        uint32_t hp_active2sleep_backup_en            : 1;
-    };
-    uint32_t val;
-} pmu_hp_backup_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0       : 26;
-        uint32_t dig_sysclk_nodiv: 1;
-        uint32_t icg_sysclk_en   : 1;
-        uint32_t sysclk_slp_sel  : 1;
-        uint32_t icg_slp_sel     : 1;
-        uint32_t dig_sysclk_sel  : 2;
-    };
-    uint32_t val;
-} pmu_hp_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
-        uint32_t slp_mem_xpd    : 1;
-        uint32_t slp_logic_xpd  : 1;
-        uint32_t xpd            : 1;
-        uint32_t slp_mem_dbias  : 4;
-        uint32_t slp_logic_dbias: 4;
-        uint32_t dbias          : 5;
-    };
-    uint32_t val;
-} pmu_hp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 26;
-        uint32_t drv_b    : 6;
-    };
-    uint32_t val;
-} pmu_hp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_hp_xtal_reg_t;
-
-typedef struct pmu_hp_hw_regmap_t {
-    pmu_hp_dig_power_reg_t     dig_power;
-    uint32_t                   icg_func;
-    uint32_t                   icg_apb;
-    uint32_t                   icg_modem;
-    pmu_hp_sys_cntl_reg_t      syscntl;
-    pmu_hp_clk_power_reg_t     clk_power;
-    pmu_hp_bias_reg_t          bias;
-    pmu_hp_backup_reg_t        backup;
-    uint32_t                   backup_clk;
-    pmu_hp_sysclk_reg_t        sysclk;
-    pmu_hp_regulator0_reg_t    regulator0;
-    pmu_hp_regulator1_reg_t    regulator1;
-    pmu_hp_xtal_reg_t          xtal;
-} pmu_hp_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 21;
-        uint32_t slp_xpd  : 1;
-        uint32_t xpd      : 1;
-        uint32_t slp_dbias: 4;
-        uint32_t dbias    : 5;
-    };
-    uint32_t val;
-} pmu_lp_regulator0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 26;
-        uint32_t drv_b    : 6;
-    };
-    uint32_t val;
-} pmu_lp_regulator1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t xpd_xtal : 1;
-    };
-    uint32_t val;
-} pmu_lp_xtal_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 26;
-        uint32_t lp_pad_slp_sel : 1;
-        uint32_t bod_source_sel : 1;
-        uint32_t vddbat_mode : 2;
-        uint32_t mem_dslp  : 1;
-        uint32_t peri_pd_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_dig_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0  : 27;
-        uint32_t xpd_lppll  : 1;
-        uint32_t xpd_xtal32k: 1;
-        uint32_t xpd_rc32k  : 1;
-        uint32_t xpd_fosc   : 1;
-        uint32_t pd_osc     : 1;
-    };
-    uint32_t val;
-} pmu_lp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0 : 25;
-        uint32_t xpd_bias  : 1;
-        uint32_t dbg_atten : 4;
-        uint32_t pd_cur    : 1;
-        uint32_t bias_sleep: 1;
-    };
-    uint32_t val;
-} pmu_lp_bias_reg_t;
-
-typedef struct pmu_lp_hw_regmap_t {
-    pmu_lp_regulator0_reg_t    regulator0;
-    pmu_lp_regulator1_reg_t    regulator1;
-    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
-    pmu_lp_dig_power_reg_t     dig_power;
-    pmu_lp_clk_power_reg_t     clk_power;
-    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
-} pmu_lp_hw_regmap_t;
-
-
-typedef union {
-    struct {
-        uint32_t tie_low_cali_xtal_icg      : 1;
-        uint32_t tie_low_global_pll_icg     : 4;
-        uint32_t tie_low_global_xtal_icg    : 1;
-        uint32_t tie_low_i2c_retention      : 1;
-        uint32_t tie_low_xpd_pll_i2c        : 4;
-        uint32_t tie_low_xpd_pll            : 4;
-        uint32_t tie_low_xpd_xtal           : 1;
-        uint32_t tie_high_cali_xtal_icg     : 1;
-        uint32_t tie_high_global_pll_icg    : 4;
-        uint32_t tie_high_global_xtal_icg   : 1;
-        uint32_t tie_high_i2c_retention     : 1;
-        uint32_t tie_high_xpd_pll_i2c       : 4;
-        uint32_t tie_high_xpd_pll           : 4;
-        uint32_t tie_high_xpd_xtal          : 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_clk_power_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 28;
-        uint32_t update_dig_icg_switch: 1;
-        uint32_t tie_low_icg_slp_sel  : 1;
-        uint32_t tie_high_icg_slp_sel : 1;
-        uint32_t update_dig_sysclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_sleep_sysclk_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0             : 31;
-        uint32_t update_dig_icg_func_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_func_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0            : 31;
-        uint32_t update_dig_icg_apb_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_hp_apb_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 31;
-        uint32_t update_dig_icg_modem_en: 1;
-    };
-    uint32_t val;
-} pmu_imm_modem_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0              : 30;
-        uint32_t tie_low_lp_rootclk_sel : 1;
-        uint32_t tie_high_lp_rootclk_sel: 1;
-    };
-    uint32_t val;
-} pmu_imm_lp_icg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t pad_slp_sel             : 1;
-        uint32_t lp_pad_hold_all         : 1;
-        uint32_t hp_pad_hold_all         : 1;
-        uint32_t reserved0               : 23;
-        uint32_t tie_high_pad_slp_sel    : 1;
-        uint32_t tie_low_pad_slp_sel     : 1;
-        uint32_t tie_high_lp_pad_hold_all: 1;
-        uint32_t tie_low_lp_pad_hold_all : 1;
-        uint32_t tie_high_hp_pad_hold_all: 1;
-        uint32_t tie_low_hp_pad_hold_all : 1;
-    };
-    uint32_t val;
-} pmu_imm_pad_hold_all_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 30;
-        uint32_t tie_high_i2c_iso_en: 1;
-        uint32_t tie_low_i2c_iso_en : 1;
-    };
-    uint32_t val;
-} pmu_imm_i2c_isolate_reg_t;
-
-typedef struct pmu_imm_hw_regmap_t {
-    pmu_imm_hp_clk_power_reg_t     clk_power;
-    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
-    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
-    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
-    pmu_imm_modem_icg_reg_t        modem_icg;
-    pmu_imm_lp_icg_reg_t           lp_icg;
-    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
-    pmu_imm_i2c_isolate_reg_t      i2c_iso;
-} pmu_imm_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 5;
-        uint32_t powerdown_timer: 9;
-        uint32_t powerup_timer  : 9;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 5;
-        uint32_t powerdown_timer: 9;
-        uint32_t powerup_timer  : 9;
-        uint32_t wait_timer     : 9;
-    };
-    uint32_t val;
-} pmu_power_wait_timer1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_reset   : 1;
-        uint32_t force_iso     : 1;
-        uint32_t force_pu      : 1;
-        uint32_t force_no_reset: 1;
-        uint32_t force_no_iso  : 1;
-        uint32_t force_pd      : 1;
-        uint32_t reserved0     : 26;    /* Invalid of lp peripherals */
-    };
-    uint32_t val;
-} pmu_power_domain_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t pd_top_mask   : 5;
-        uint32_t reserved0     : 22;    /* Invalid of lp peripherals */
-        uint32_t top_pd_mask   : 5;
-    };
-    uint32_t val;
-} pmu_power_domain_mask_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_pu      :    1;
-        uint32_t force_pd      :    1;
-        uint32_t reserved2     :    30;
-    };
-    uint32_t val;
-} pmu_power_dcdc_switch_reg_t;
-
-typedef union {
-    struct {
-        uint32_t force_hp_pad_no_iso_all: 1;
-        uint32_t force_hp_pad_iso_all   : 1;
-        uint32_t reserved0              : 30;
-    };
-    uint32_t val;
-} pmu_power_hp_pad_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wait_xtal_stable: 16;
-        uint32_t wait_pll_stable : 16;
-    };
-    uint32_t val;
-} pmu_power_clk_wait_cntl_reg_t;
-
-typedef struct pmu_power_hw_regmap_t {
-    pmu_power_wait_timer0_reg_t    wait_timer0;
-    pmu_power_wait_timer1_reg_t    wait_timer1;
-    pmu_power_domain_cntl_reg_t    hp_pd[3];
-    pmu_power_domain_mask_reg_t    hp_pd_mask[3];
-    pmu_power_dcdc_switch_reg_t    dcdc_switch;
-    pmu_power_domain_cntl_reg_t    lp_peri;
-    pmu_power_domain_mask_reg_t    lp_peri_mask;
-    pmu_power_hp_pad_reg_t         hp_pad;
-    pmu_power_clk_wait_cntl_reg_t  clk_wait;
-} pmu_power_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t sleep_reject_ena: 31;
-        uint32_t slp_reject_en   : 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_ena: 31;
-        uint32_t reserved0 : 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl2_reg_t;
-
-typedef union {
-    struct {
-        uint32_t lp_min_slp_val: 8;
-        uint32_t hp_min_slp_val: 8;
-        uint32_t sleep_prt_sel : 2;
-        uint32_t reserved0     : 14;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl3_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0           : 31;
-        uint32_t slp_reject_cause_clr: 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl4_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modem_wait_target : 20;
-        uint32_t reserved0         : 4;
-        uint32_t lp_ana_wait_target: 8;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl5_reg_t;
-
-typedef union {
-    struct {
-        uint32_t soc_wakeup_wait    : 20;
-        uint32_t reserved0          : 10;
-        uint32_t soc_wakeup_wait_cfg: 2;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl6_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 16;
-        uint32_t ana_wait_target: 16;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl7_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 31;
-        uint32_t lp_lite_wakeup_ena : 1;
-    };
-    uint32_t val;
-} pmu_slp_wakeup_cntl8_reg_t;
-
-typedef struct pmu_wakeup_hw_regmap_t {
-    pmu_slp_wakeup_cntl0_reg_t     cntl0;
-    pmu_slp_wakeup_cntl1_reg_t     cntl1;
-    pmu_slp_wakeup_cntl2_reg_t     cntl2;
-    pmu_slp_wakeup_cntl3_reg_t     cntl3;
-    pmu_slp_wakeup_cntl4_reg_t     cntl4;
-    pmu_slp_wakeup_cntl5_reg_t     cntl5;
-    pmu_slp_wakeup_cntl6_reg_t     cntl6;
-    pmu_slp_wakeup_cntl7_reg_t     cntl7;
-    pmu_slp_wakeup_cntl8_reg_t     cntl8;
-    uint32_t                       status0;
-    uint32_t                       status1;
-    uint32_t                       status2;
-} pmu_wakeup_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t i2c_por_wait_target: 8;
-        uint32_t reserved0          : 24;
-    };
-    uint32_t val;
-} pmu_hp_clk_poweron_reg_t;
-
-typedef union {
-    struct {
-        uint32_t modify_icg_cntl_wait: 8;
-        uint32_t switch_icg_cntl_wait: 8;
-        uint32_t reserved0           : 16;
-    };
-    uint32_t val;
-} pmu_hp_clk_cntl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t por_done : 1;
-    };
-    uint32_t val;
-} pmu_por_status_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0     : 24;
-        uint32_t mspi_phy_xpd  : 1;
-        uint32_t sdio_pll_xpd  : 1;
-        uint32_t perif_i2c_rstb: 1;
-        uint32_t xpd_perif_i2c : 1;
-        uint32_t xpd_txrf_i2c  : 1;
-        uint32_t xpd_rfrx_pbus : 1;
-        uint32_t xpd_ckgen_i2c : 1;
-        uint32_t reserved1     : 1;
-    };
-    uint32_t val;
-} pmu_rf_pwc_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0          : 31;
-        uint32_t backup_sysclk_nodiv: 1;
-    };
-    uint32_t val;
-} pmu_backup_cfg_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0   : 14;
-        uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
-        uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
-        uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
-        uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
-        uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
-        uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
-        uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
-        uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
-        uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
-        uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
-        uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
-        uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
-        uint32_t reserved1   : 1;
-        uint32_t lp_exception: 1;
-        uint32_t sdio_idle: 1;
-        uint32_t sw       : 1;
-        uint32_t reject   : 1;
-        uint32_t wakeup   : 1;
-    };
-    uint32_t val;
-} pmu_hp_intr_reg_t;
-
-typedef struct pmu_hp_ext_hw_regmap_t {
-    pmu_hp_clk_poweron_reg_t   clk_poweron;
-    pmu_hp_clk_cntl_reg_t      clk_cntl;
-    pmu_por_status_reg_t       por_status;
-    pmu_rf_pwc_reg_t           rf_pwc;
-    pmu_backup_cfg_reg_t       backup_cfg;
-    pmu_hp_intr_reg_t          int_raw;
-    pmu_hp_intr_reg_t          int_st;
-    pmu_hp_intr_reg_t          int_ena;
-    pmu_hp_intr_reg_t          int_clr;
-} pmu_hp_ext_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0                    : 13;
-        uint32_t sleep_reject                 : 1;
-        uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
-        uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
-        uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
-        uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
-        uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
-        uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
-        uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
-        uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
-        uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
-        uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
-        uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
-        uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
-        uint32_t lp_wakeup                    : 1;
-        uint32_t sleep_switch_active_end      : 1;
-        uint32_t active_switch_sleep_end      : 1;
-        uint32_t sleep_switch_active_start    : 1;
-        uint32_t active_switch_sleep_start    : 1;
-        uint32_t hp_sw_trigger                : 1;
-    };
-    uint32_t val;
-} pmu_lp_intr_reg_t;
-
-typedef union {
-    struct {
-        uint32_t waiti_rdy         : 1;
-        uint32_t stall_rdy         : 1;
-        uint32_t reserved0         : 16;
-        uint32_t force_stall       : 1;
-        uint32_t slp_waiti_flag_en : 1;
-        uint32_t slp_stall_flag_en : 1;
-        uint32_t slp_stall_wait    : 8;
-        uint32_t slp_stall_en      : 1;
-        uint32_t slp_reset_en      : 1;
-        uint32_t slp_bypass_intr_en: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr0_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0: 31;
-        uint32_t sleep_req: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr1_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_en: 31;
-        uint32_t reserved0: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr2_reg_t;
-
-typedef union {
-    struct {
-        uint32_t wakeup_cause: 31;
-        uint32_t reserved0: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr3_reg_t;
-
-typedef union {
-    struct {
-        uint32_t sleep_reject: 31;
-        uint32_t reserved0: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr4_reg_t;
-
-typedef union {
-    struct {
-        uint32_t sleep_reject_cause: 31;
-        uint32_t reserved0: 1;
-    };
-    uint32_t val;
-} pmu_lp_cpu_pwr5_reg_t;
-
-typedef struct pmu_lp_ext_hw_regmap_t {
-    pmu_lp_intr_reg_t          int_raw;
-    pmu_lp_intr_reg_t          int_st;
-    pmu_lp_intr_reg_t          int_ena;
-    pmu_lp_intr_reg_t          int_clr;
-    pmu_lp_cpu_pwr0_reg_t      pwr0;
-    pmu_lp_cpu_pwr1_reg_t      pwr1;
-    pmu_lp_cpu_pwr2_reg_t      pwr2;
-    pmu_lp_cpu_pwr3_reg_t      pwr3;
-    pmu_lp_cpu_pwr4_reg_t      pwr4;
-    pmu_lp_cpu_pwr5_reg_t      pwr5;
-} pmu_lp_ext_hw_regmap_t;
-
-typedef union {
-    struct {
-        uint32_t reserved_0:7;
-        uint32_t force_tieh_sel:1;
-        uint32_t xpd:1;
-        uint32_t tieh_sel:3;
-        uint32_t tieh_pos_en:1;
-        uint32_t tieh_neg_en:1;
-        uint32_t tieh:1;
-        uint32_t target1:8;
-        uint32_t target0:8;
-        uint32_t ldo_cnt_prescaler_sel:1;
-    };
-    uint32_t val;
-} pmu_ext_ldo_reg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved_0:23;
-        uint32_t mul:3;
-        uint32_t en_vdet:1;
-        uint32_t en_cur_lim:1;
-        uint32_t dref:4;
-    };
-    uint32_t val;
-} pmu_ext_ldo_ana_reg_t;
-
-
-typedef struct pmu_ext_ldo_info_t {
-    pmu_ext_ldo_reg_t pmu_ext_ldo;
-    pmu_ext_ldo_ana_reg_t pmu_ext_ldo_ana;
-} pmu_ext_ldo_info_t;
-
-
-typedef union {
-    struct {
-        uint32_t on_req        : 1;
-        uint32_t off_req       : 1;
-        uint32_t lightslp_req  : 1;
-        uint32_t deepslp_req   : 1;
-        uint32_t reserved0     : 3;
-        uint32_t done_force    : 1;
-        uint32_t on_force_pu   : 1;
-        uint32_t on_force_pd   : 1;
-        uint32_t fb_res_force_pu   : 1;
-        uint32_t fb_res_force_pd   : 1;
-        uint32_t ls_force_pu   : 1;
-        uint32_t ls_force_pd   : 1;
-        uint32_t ds_force_pu   : 1;
-        uint32_t ds_force_pd   : 1;
-        uint32_t dcm_cur_st    : 8;
-        uint32_t reserved1     : 5;
-        uint32_t en_amux_test  : 1;
-        uint32_t reserved2     : 2;
-    };
-    uint32_t val;
-} pmu_dcm_ctrl_reg_t;
-
-typedef union {
-    struct {
-        uint32_t pre_delay      : 8;
-        uint32_t res_off_delay  : 8;
-        uint32_t stable_delay   : 10;
-        uint32_t reserved0      : 6;
-    };
-    uint32_t val;
-} pmu_dcm_wait_delay_t;
-
-typedef union {
-    struct {
-        uint32_t module     : 2;
-        uint32_t reserved1  : 29;
-        uint32_t sw_update  : 1;
-    };
-    uint32_t val;
-} pmu_vddbat_cfg_t;
-
-typedef union {
-    struct {
-        uint32_t reserved0      : 5;
-        uint32_t wait_cycles    : 9;
-        uint32_t sleep_cycles   : 16;
-        uint32_t force_done     : 1;
-        uint32_t sleep_timer_en : 1;
-    };
-    uint32_t val;
-} pmu_touch_sensor_pwr_cntl_t;
-
-typedef struct pmu_dev_t {
-    volatile pmu_hp_hw_regmap_t     hp_sys[3];
-    volatile pmu_lp_hw_regmap_t     lp_sys[2];
-    volatile pmu_imm_hw_regmap_t    imm;
-    volatile pmu_power_hw_regmap_t  power;
-    volatile pmu_wakeup_hw_regmap_t wakeup;
-    volatile pmu_hp_ext_hw_regmap_t hp_ext;
-    volatile pmu_lp_ext_hw_regmap_t lp_ext;
-
-    union {
-        struct {
-            volatile uint32_t reserved0    : 30;
-            volatile uint32_t lp_trigger_hp: 1;
-            volatile uint32_t hp_trigger_lp: 1;
-        };
-        volatile uint32_t val;
-    } hp_lp_cpu_comm;
-
-    union {
-        struct {
-            volatile uint32_t reserved0           : 31;
-            volatile uint32_t dig_regulator_en_cal: 1;
-        };
-        volatile uint32_t val;
-    } hp_regulator_cfg;
-
-    union {
-        struct {
-            volatile uint32_t en_cali_pmu_cntl : 1;
-            volatile uint32_t reserved0 : 10;
-            volatile uint32_t last_st   : 7;
-            volatile uint32_t target_st : 7;
-            volatile uint32_t current_st: 7;
-        };
-        volatile uint32_t val;
-    } main_state;
-
-    union {
-        struct {
-            volatile uint32_t reserved0: 13;
-            volatile uint32_t backup_st: 5;
-            volatile uint32_t lp_pwr_st: 5;
-            volatile uint32_t hp_pwr_st: 9;
-        };
-        volatile int32_t val;
-    } pwr_state;
-
-    union {
-        struct {
-            volatile uint32_t stable_xpd_bbpll : 3;
-            volatile uint32_t stable_xpd_xtal  : 1;
-            volatile uint32_t ana_xpd_pll_i2c  : 3;
-            volatile uint32_t reserved0        : 3;
-            volatile uint32_t sysclk_slp_sel   : 1;
-            volatile uint32_t sysclk_sel       : 2;
-            volatile uint32_t sysclk_nodiv     : 1;
-            volatile uint32_t icg_sysclk_en    : 1;
-            volatile uint32_t icg_modem_switch : 1;
-            volatile uint32_t icg_modem_code   : 2;
-            volatile uint32_t icg_slp_sel      : 1;
-            volatile uint32_t icg_global_xtal  : 1;
-            volatile uint32_t icg_global_pll   : 4;
-            volatile uint32_t ana_i2c_iso_en   : 1;
-            volatile uint32_t ana_i2c_retention: 1;
-            volatile uint32_t reserved1        : 1;
-            volatile uint32_t ana_xpd_pll      : 4;
-            volatile uint32_t ana_xpd_xtal     : 1;
-        };
-        volatile uint32_t val;
-    } clk_state0;
-
-    volatile uint32_t clk_state1;
-    volatile uint32_t clk_state2;
-
-    volatile pmu_ext_ldo_info_t ext_ldo[6];
-
-    volatile uint32_t ext_wakeup_lv;
-    volatile uint32_t ext_wakeup_sel;
-    volatile uint32_t ext_wakeup_st;
-    union {
-        struct {
-            volatile uint32_t reserved0      : 30;
-            volatile uint32_t status_clr     : 1;
-            volatile uint32_t filter         : 1;
-        };
-        volatile uint32_t val;
-    } ext_wakeup_cntl;
-
-    union {
-        struct {
-            volatile uint32_t act_dnum   : 10;
-            volatile uint32_t reserved0  : 22;
-        };
-        volatile uint32_t val;
-    } sdio_wakeup_cntl;
-
-    union {
-        struct {
-            volatile uint32_t reserved0  : 16;
-            volatile uint32_t cnt_target : 16;
-        };
-        volatile uint32_t val;
-    } xtal_slp;
-
-    union {
-        struct {
-            volatile uint32_t reserved0  : 16;
-            volatile uint32_t hpcore1_stall_code : 8;
-            volatile uint32_t hpcore0_stall_code : 8;
-        };
-        volatile uint32_t val;
-    } cpu_sw_stall;
-
-    volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
-    volatile pmu_dcm_wait_delay_t dcm_delay;
-    volatile pmu_vddbat_cfg_t vbat_cfg;
-    volatile pmu_touch_sensor_pwr_cntl_t touch_pwr_cntl;
-
-    union {
-        struct {
-            volatile uint32_t eco_result:1;
-            volatile uint32_t reserved0  : 30;
-            volatile uint32_t eco_en: 1;
-
-        };
-        volatile uint32_t val;
-    } pmu_rdn_eco;
-
-
-    uint32_t reserved[121];
-
-    union {
-        struct {
-            volatile uint32_t pmu_date: 31;
-            volatile uint32_t clk_en  : 1;
-        };
-        volatile uint32_t val;
-    } date;
-} pmu_dev_t;
-
-extern pmu_dev_t PMU;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
-
-_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_RDN_ECO_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/regi2c_brownout.h b/components/soc/esp32p4/include/soc/regi2c_brownout.h
index 0504a137056..b7297808f49 100644
--- a/components/soc/esp32p4/include/soc/regi2c_brownout.h
+++ b/components/soc/esp32p4/include/soc/regi2c_brownout.h
@@ -14,9 +14,12 @@
  * bus. These definitions are used via macros defined in regi2c_ctrl.h.
  */
 
-#define I2C_BOD            0x61
+#define I2C_BOD            0x6a
 #define I2C_BOD_HOSTID     0
 
-#define I2C_BOD_THRESHOLD           0x5
-#define I2C_BOD_THRESHOLD_MSB       2
-#define I2C_BOD_THRESHOLD_LSB       0
+#define I2C_BOD_THRESHOLD_L           0x9
+#define I2C_BOD_THRESHOLD_L_MSB       4
+#define I2C_BOD_THRESHOLD_L_LSB       2
+#define I2C_BOD_THRESHOLD_H           0x9
+#define I2C_BOD_THRESHOLD_H_MSB       7
+#define I2C_BOD_THRESHOLD_H_LSB       5
diff --git a/components/soc/esp32p4/include/soc/reset_reasons.h b/components/soc/esp32p4/include/soc/reset_reasons.h
index 39b792e549e..4e6952d555b 100644
--- a/components/soc/esp32p4/include/soc/reset_reasons.h
+++ b/components/soc/esp32p4/include/soc/reset_reasons.h
@@ -45,7 +45,7 @@ typedef enum {
     RESET_REASON_CORE_USB_JTAG     = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core
     RESET_REASON_CORE_USB_UART     = 0x17, // USB Serial/JTAG controller's UART resets the digital core
     RESET_REASON_CPU_JTAG          = 0x18, // Triggered when a reset command from JTAG is received
-    RESET_REASON_CPU_LOCKUP        = 0x1A, // Triggered when the CPU enters lockup (exception inside the execption handler would cause this)
+    RESET_REASON_CPU_LOCKUP        = 0x1A, // Triggered when the CPU enters lockup (exception inside the exception handler would cause this)
 } soc_reset_reason_t;
 
 
diff --git a/components/soc/esp32p4/include/soc/retention_periph_defs.h b/components/soc/esp32p4/include/soc/retention_periph_defs.h
index b069f7babd2..1f3c144aaf6 100644
--- a/components/soc/esp32p4/include/soc/retention_periph_defs.h
+++ b/components/soc/esp32p4/include/soc/retention_periph_defs.h
@@ -15,6 +15,7 @@ extern "C" {
 
 typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_MIN          = 0,
+    SLEEP_RETENTION_MODULE_NULL         = SLEEP_RETENTION_MODULE_MIN, /* This module is for all peripherals that can't survive from PD_TOP to call init only. Shouldn't have any dependency. */
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
     /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
@@ -25,30 +26,41 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_TG1_WDT      = 4,
     SLEEP_RETENTION_MODULE_TG0_TIMER    = 5,
     SLEEP_RETENTION_MODULE_TG1_TIMER    = 6,
-    /* MISC Peripherals */
-    SLEEP_RETENTION_MODULE_UART0        = 7,
-    SLEEP_RETENTION_MODULE_UART1        = 8,
-    SLEEP_RETENTION_MODULE_UART2        = 9,
-    SLEEP_RETENTION_MODULE_UART3        = 10,
-    SLEEP_RETENTION_MODULE_UART4        = 11,
-    SLEEP_RETENTION_MODULE_RMT0         = 12,
     /* AHB_DMA by channel */
-    SLEEP_RETENTION_MODULE_AHB_DMA_CH0  = 13,
-    SLEEP_RETENTION_MODULE_AHB_DMA_CH1  = 14,
-    SLEEP_RETENTION_MODULE_AHB_DMA_CH2  = 15,
+    SLEEP_RETENTION_MODULE_AHB_DMA_CH0  = 7,
+    SLEEP_RETENTION_MODULE_AHB_DMA_CH1  = 8,
+    SLEEP_RETENTION_MODULE_AHB_DMA_CH2  = 9,
     /* AXI_DMA by channel */
-    SLEEP_RETENTION_MODULE_AXI_DMA_CH0  = 16,
-    SLEEP_RETENTION_MODULE_AXI_DMA_CH1  = 17,
-    SLEEP_RETENTION_MODULE_AXI_DMA_CH2  = 18,
-
+    SLEEP_RETENTION_MODULE_AXI_DMA_CH0  = 10,
+    SLEEP_RETENTION_MODULE_AXI_DMA_CH1  = 11,
+    SLEEP_RETENTION_MODULE_AXI_DMA_CH2  = 12,
+    /* MISC Peripherals */
+    SLEEP_RETENTION_MODULE_UART0        = 13,
+    SLEEP_RETENTION_MODULE_UART1        = 14,
+    SLEEP_RETENTION_MODULE_UART2        = 15,
+    SLEEP_RETENTION_MODULE_UART3        = 16,
+    SLEEP_RETENTION_MODULE_UART4        = 17,
+    SLEEP_RETENTION_MODULE_RMT0         = 18,
     SLEEP_RETENTION_MODULE_I2S0         = 19,
     SLEEP_RETENTION_MODULE_I2S1         = 20,
     SLEEP_RETENTION_MODULE_I2S2         = 21,
+    SLEEP_RETENTION_MODULE_I2C0         = 22,
+    SLEEP_RETENTION_MODULE_I2C1         = 23,
+    SLEEP_RETENTION_MODULE_ETM0         = 24,
+    SLEEP_RETENTION_MODULE_TWAI0        = 25,
+    SLEEP_RETENTION_MODULE_TWAI1        = 26,
+    SLEEP_RETENTION_MODULE_TWAI2        = 27,
+    SLEEP_RETENTION_MODULE_PARLIO0      = 28,
+    SLEEP_RETENTION_MODULE_GPSPI2       = 29,
+    SLEEP_RETENTION_MODULE_GPSPI3       = 30,
+    SLEEP_RETENTION_MODULE_LEDC         = 31,
 
     SLEEP_RETENTION_MODULE_MAX          = 31
 } periph_retention_module_t;
 
 typedef enum periph_retention_module_bitmap {
+    SLEEP_RETENTION_MODULE_BM_NULL = BIT(SLEEP_RETENTION_MODULE_NULL),
+
     /* clock module, which includes system and modem */
     SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
     /* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
@@ -77,6 +89,16 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_BM_I2S0         = BIT(SLEEP_RETENTION_MODULE_I2S0),
     SLEEP_RETENTION_MODULE_BM_I2S1         = BIT(SLEEP_RETENTION_MODULE_I2S1),
     SLEEP_RETENTION_MODULE_BM_I2S2         = BIT(SLEEP_RETENTION_MODULE_I2S2),
+    SLEEP_RETENTION_MODULE_BM_ETM0         = BIT(SLEEP_RETENTION_MODULE_ETM0),
+    SLEEP_RETENTION_MODULE_BM_I2C0         = BIT(SLEEP_RETENTION_MODULE_I2C0),
+    SLEEP_RETENTION_MODULE_BM_I2C1         = BIT(SLEEP_RETENTION_MODULE_I2C1),
+    SLEEP_RETENTION_MODULE_BM_TWAI0        = BIT(SLEEP_RETENTION_MODULE_TWAI0),
+    SLEEP_RETENTION_MODULE_BM_TWAI1        = BIT(SLEEP_RETENTION_MODULE_TWAI1),
+    SLEEP_RETENTION_MODULE_BM_TWAI2        = BIT(SLEEP_RETENTION_MODULE_TWAI2),
+    SLEEP_RETENTION_MODULE_BM_PARLIO0      = BIT(SLEEP_RETENTION_MODULE_PARLIO0),
+    SLEEP_RETENTION_MODULE_BM_GPSPI2       = BIT(SLEEP_RETENTION_MODULE_GPSPI2),
+    SLEEP_RETENTION_MODULE_BM_GPSPI3       = BIT(SLEEP_RETENTION_MODULE_GPSPI3),
+    SLEEP_RETENTION_MODULE_BM_LEDC         = BIT(SLEEP_RETENTION_MODULE_LEDC),
 
     SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
 } periph_retention_module_bitmap_t;
@@ -98,9 +120,20 @@ typedef enum periph_retention_module_bitmap {
                                   | SLEEP_RETENTION_MODULE_BM_UART3      \
                                   | SLEEP_RETENTION_MODULE_BM_UART4      \
                                   | SLEEP_RETENTION_MODULE_BM_RMT0       \
-                                  | SLEEP_RETENTION_MODULE_BM_I2S0        \
-                                  | SLEEP_RETENTION_MODULE_BM_I2S1        \
-                                  | SLEEP_RETENTION_MODULE_BM_I2S2        \
+                                  | SLEEP_RETENTION_MODULE_BM_I2S0       \
+                                  | SLEEP_RETENTION_MODULE_BM_I2S1       \
+                                  | SLEEP_RETENTION_MODULE_BM_I2S2       \
+                                  | SLEEP_RETENTION_MODULE_BM_ETM0       \
+                                  | SLEEP_RETENTION_MODULE_BM_I2C0       \
+                                  | SLEEP_RETENTION_MODULE_BM_I2C1       \
+                                  | SLEEP_RETENTION_MODULE_BM_TWAI0      \
+                                  | SLEEP_RETENTION_MODULE_BM_TWAI1      \
+                                  | SLEEP_RETENTION_MODULE_BM_TWAI2      \
+                                  | SLEEP_RETENTION_MODULE_BM_PARLIO0    \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI2     \
+                                  | SLEEP_RETENTION_MODULE_BM_GPSPI3     \
+                                  | SLEEP_RETENTION_MODULE_BM_LEDC       \
+                                  | SLEEP_RETENTION_MODULE_BM_NULL       \
                                   )
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32p4/include/soc/sdmmc_reg.h b/components/soc/esp32p4/include/soc/sdmmc_reg.h
deleted file mode 100644
index f8ba68d49fe..00000000000
--- a/components/soc/esp32p4/include/soc/sdmmc_reg.h
+++ /dev/null
@@ -1,1526 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SDHOST_CTRL_REG register
- *  Control register
- */
-#define SDHOST_CTRL_REG (DR_REG_SDHOST_BASE + 0x0)
-/** SDHOST_CONTROLLER_RESET : R/W; bitpos: [0]; default: 0;
- *  To reset controller, firmware should set this bit. This bit is auto-cleared after
- *  two AHB and two sdhost_cclk_in clock cycles.
- */
-#define SDHOST_CONTROLLER_RESET    (BIT(0))
-#define SDHOST_CONTROLLER_RESET_M  (SDHOST_CONTROLLER_RESET_V << SDHOST_CONTROLLER_RESET_S)
-#define SDHOST_CONTROLLER_RESET_V  0x00000001U
-#define SDHOST_CONTROLLER_RESET_S  0
-/** SDHOST_FIFO_RESET : R/W; bitpos: [1]; default: 0;
- *  To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after
- *  completion of reset operation.
- *  Note: FIFO pointers will be out of reset after 2 cycles of system clocks in
- *  addition to synchronization delay (2 cycles of card clock), after the fifo_reset is
- *  cleared.
- */
-#define SDHOST_FIFO_RESET    (BIT(1))
-#define SDHOST_FIFO_RESET_M  (SDHOST_FIFO_RESET_V << SDHOST_FIFO_RESET_S)
-#define SDHOST_FIFO_RESET_V  0x00000001U
-#define SDHOST_FIFO_RESET_S  1
-/** SDHOST_DMA_RESET : R/W; bitpos: [2]; default: 0;
- *  To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared
- *  after two AHB clocks.
- */
-#define SDHOST_DMA_RESET    (BIT(2))
-#define SDHOST_DMA_RESET_M  (SDHOST_DMA_RESET_V << SDHOST_DMA_RESET_S)
-#define SDHOST_DMA_RESET_V  0x00000001U
-#define SDHOST_DMA_RESET_S  2
-/** SDHOST_INT_ENABLE : R/W; bitpos: [4]; default: 0;
- *  Global interrupt enable/disable bit. 0: Disable; 1: Enable.
- */
-#define SDHOST_INT_ENABLE    (BIT(4))
-#define SDHOST_INT_ENABLE_M  (SDHOST_INT_ENABLE_V << SDHOST_INT_ENABLE_S)
-#define SDHOST_INT_ENABLE_V  0x00000001U
-#define SDHOST_INT_ENABLE_S  4
-/** SDHOST_READ_WAIT : R/W; bitpos: [6]; default: 0;
- *  For sending read-wait to SDIO cards.
- */
-#define SDHOST_READ_WAIT    (BIT(6))
-#define SDHOST_READ_WAIT_M  (SDHOST_READ_WAIT_V << SDHOST_READ_WAIT_S)
-#define SDHOST_READ_WAIT_V  0x00000001U
-#define SDHOST_READ_WAIT_S  6
-/** SDHOST_SEND_IRQ_RESPONSE : R/W; bitpos: [7]; default: 0;
- *  Bit automatically clears once response is sent. To wait for MMC card interrupts,
- *  host issues CMD40 and waits for interrupt response from MMC card(s). In the
- *  meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this
- *  bit, at which time SD/MMC command state-machine sends CMD40 response on bus and
- *  returns to idle state.
- */
-#define SDHOST_SEND_IRQ_RESPONSE    (BIT(7))
-#define SDHOST_SEND_IRQ_RESPONSE_M  (SDHOST_SEND_IRQ_RESPONSE_V << SDHOST_SEND_IRQ_RESPONSE_S)
-#define SDHOST_SEND_IRQ_RESPONSE_V  0x00000001U
-#define SDHOST_SEND_IRQ_RESPONSE_S  7
-/** SDHOST_ABORT_READ_DATA : R/W; bitpos: [8]; default: 0;
- *  After a suspend-command is issued during a read-operation, software polls the card
- *  to find when the suspend-event occurred. Once the suspend-event has occurred,
- *  software sets the bit which will reset the data state machine that is waiting for
- *  the next block of data. This bit is automatically cleared once the data state
- *  machine is reset to idle.
- */
-#define SDHOST_ABORT_READ_DATA    (BIT(8))
-#define SDHOST_ABORT_READ_DATA_M  (SDHOST_ABORT_READ_DATA_V << SDHOST_ABORT_READ_DATA_S)
-#define SDHOST_ABORT_READ_DATA_V  0x00000001U
-#define SDHOST_ABORT_READ_DATA_S  8
-/** SDHOST_SEND_CCSD : R/W; bitpos: [9]; default: 0;
- *  When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if
- *  the current command is expecting CCS (that is, RW_BLK), and if interrupts are
- *  enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC
- *  automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD)
- *  bit  in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host,
- *  in case the Command Done interrupt is not masked.
- *  NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive
- *  the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may
- *  be sent to the CE-ATA device, even if the device has signalled CCS.
- */
-#define SDHOST_SEND_CCSD    (BIT(9))
-#define SDHOST_SEND_CCSD_M  (SDHOST_SEND_CCSD_V << SDHOST_SEND_CCSD_S)
-#define SDHOST_SEND_CCSD_V  0x00000001U
-#define SDHOST_SEND_CCSD_S  9
-/** SDHOST_SEND_AUTO_STOP_CCSD : R/W; bitpos: [10]; default: 0;
- *  Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together;
- *  SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set,
- *  SD/MMC automatically sends an internally-generated STOP command (CMD12) to the
- *  CE-ATA device. After sending this internally-generated STOP command, the Auto
- *  Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated
- *  for the host, in case the ACD interrupt is not masked. After sending the Command
- *  Completion Signal Disable (CCSD), SD/MMC automatically clears the
- *  SDHOST_SEND_AUTO_STOP_CCSD bit.
- */
-#define SDHOST_SEND_AUTO_STOP_CCSD    (BIT(10))
-#define SDHOST_SEND_AUTO_STOP_CCSD_M  (SDHOST_SEND_AUTO_STOP_CCSD_V << SDHOST_SEND_AUTO_STOP_CCSD_S)
-#define SDHOST_SEND_AUTO_STOP_CCSD_V  0x00000001U
-#define SDHOST_SEND_AUTO_STOP_CCSD_S  10
-/** SDHOST_CEATA_DEVICE_INTERRUPT_STATUS : R/W; bitpos: [11]; default: 0;
- *  Software should appropriately write to this bit after the power-on reset or any
- *  other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is
- *  usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt,
- *  then software should set this bit.
- */
-#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS    (BIT(11))
-#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_M  (SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_V << SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_S)
-#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_V  0x00000001U
-#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_S  11
-
-/** SDHOST_CLKDIV_REG register
- *  Clock divider configuration register
- */
-#define SDHOST_CLKDIV_REG (DR_REG_SDHOST_BASE + 0x8)
-/** SDHOST_CLK_DIVIDER0 : R/W; bitpos: [7:0]; default: 0;
- *  Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider
- *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
- *  means divided by 2*255 = 510, and so on.
- */
-#define SDHOST_CLK_DIVIDER0    0x000000FFU
-#define SDHOST_CLK_DIVIDER0_M  (SDHOST_CLK_DIVIDER0_V << SDHOST_CLK_DIVIDER0_S)
-#define SDHOST_CLK_DIVIDER0_V  0x000000FFU
-#define SDHOST_CLK_DIVIDER0_S  0
-/** SDHOST_CLK_DIVIDER1 : R/W; bitpos: [15:8]; default: 0;
- *  Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider
- *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
- *  means divided by 2*255 = 510, and so on.
- */
-#define SDHOST_CLK_DIVIDER1    0x000000FFU
-#define SDHOST_CLK_DIVIDER1_M  (SDHOST_CLK_DIVIDER1_V << SDHOST_CLK_DIVIDER1_S)
-#define SDHOST_CLK_DIVIDER1_V  0x000000FFU
-#define SDHOST_CLK_DIVIDER1_S  8
-/** SDHOST_CLK_DIVIDER2 : R/W; bitpos: [23:16]; default: 0;
- *  Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider
- *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
- *  means divided by 2*255 = 510, and so on.
- */
-#define SDHOST_CLK_DIVIDER2    0x000000FFU
-#define SDHOST_CLK_DIVIDER2_M  (SDHOST_CLK_DIVIDER2_V << SDHOST_CLK_DIVIDER2_S)
-#define SDHOST_CLK_DIVIDER2_V  0x000000FFU
-#define SDHOST_CLK_DIVIDER2_S  16
-/** SDHOST_CLK_DIVIDER3 : R/W; bitpos: [31:24]; default: 0;
- *  Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider
- *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
- *  means divided by 2*255 = 510, and so on.
- */
-#define SDHOST_CLK_DIVIDER3    0x000000FFU
-#define SDHOST_CLK_DIVIDER3_M  (SDHOST_CLK_DIVIDER3_V << SDHOST_CLK_DIVIDER3_S)
-#define SDHOST_CLK_DIVIDER3_V  0x000000FFU
-#define SDHOST_CLK_DIVIDER3_S  24
-
-/** SDHOST_CLKSRC_REG register
- *  Clock source selection register
- */
-#define SDHOST_CLKSRC_REG (DR_REG_SDHOST_BASE + 0xc)
-/** SDHOST_CLKSRC : R/W; bitpos: [3:0]; default: 0;
- *  Clock divider source for two SD cards is supported. Each card has two bits assigned
- *  to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for
- *  card 1. Card 0 maps and internally routes clock divider[0:3] outputs to
- *  cclk_out[1:0] pins, depending on bit value.
- *  00 : Clock divider 0;
- *  01 : Clock divider 1;
- *  10 : Clock divider 2;
- *  11 : Clock divider 3.
- */
-#define SDHOST_CLKSRC    0x0000000FU
-#define SDHOST_CLKSRC_M  (SDHOST_CLKSRC_V << SDHOST_CLKSRC_S)
-#define SDHOST_CLKSRC_V  0x0000000FU
-#define SDHOST_CLKSRC_S  0
-
-/** SDHOST_CLKENA_REG register
- *  Clock enable register
- */
-#define SDHOST_CLKENA_REG (DR_REG_SDHOST_BASE + 0x10)
-/** SDHOST_CCLK_ENABLE : R/W; bitpos: [1:0]; default: 0;
- *  Clock-enable control for two SD card clocks and one MMC card clock is supported.
- *  One bit per card.
- *  0: Clock disabled;
- *  1: Clock enabled.
- */
-#define SDHOST_CCLK_ENABLE    0x00000003U
-#define SDHOST_CCLK_ENABLE_M  (SDHOST_CCLK_ENABLE_V << SDHOST_CCLK_ENABLE_S)
-#define SDHOST_CCLK_ENABLE_V  0x00000003U
-#define SDHOST_CCLK_ENABLE_S  0
-/** SDHOST_LP_ENABLE : R/W; bitpos: [17:16]; default: 0;
- *  Disable clock when the card is in IDLE state. One bit per card.
- *  0: clock disabled;
- *  1: clock enabled.
- */
-#define SDHOST_LP_ENABLE    0x00000003U
-#define SDHOST_LP_ENABLE_M  (SDHOST_LP_ENABLE_V << SDHOST_LP_ENABLE_S)
-#define SDHOST_LP_ENABLE_V  0x00000003U
-#define SDHOST_LP_ENABLE_S  16
-
-/** SDHOST_TMOUT_REG register
- *  Data and response timeout configuration register
- */
-#define SDHOST_TMOUT_REG (DR_REG_SDHOST_BASE + 0x14)
-/** SDHOST_RESPONSE_TIMEOUT : R/W; bitpos: [7:0]; default: 64;
- *  Response timeout value. Value is specified in terms of number of card output
- *  clocks, i.e., sdhost_cclk_out.
- */
-#define SDHOST_RESPONSE_TIMEOUT    0x000000FFU
-#define SDHOST_RESPONSE_TIMEOUT_M  (SDHOST_RESPONSE_TIMEOUT_V << SDHOST_RESPONSE_TIMEOUT_S)
-#define SDHOST_RESPONSE_TIMEOUT_V  0x000000FFU
-#define SDHOST_RESPONSE_TIMEOUT_S  0
-/** SDHOST_DATA_TIMEOUT : R/W; bitpos: [31:8]; default: 16777215;
- *  Value for card data read timeout. This value is also used for data starvation by
- *  host timeout. The timeout counter is started only after the card clock is stopped.
- *  This value is specified in number of card output clocks, i.e. sdhost_cclk_out of
- *  the selected card.
- *  NOTE: The software timer should be used if the timeout value is in the order of 100
- *  ms. In this case, read data timeout interrupt needs to be disabled.
- */
-#define SDHOST_DATA_TIMEOUT    0x00FFFFFFU
-#define SDHOST_DATA_TIMEOUT_M  (SDHOST_DATA_TIMEOUT_V << SDHOST_DATA_TIMEOUT_S)
-#define SDHOST_DATA_TIMEOUT_V  0x00FFFFFFU
-#define SDHOST_DATA_TIMEOUT_S  8
-
-/** SDHOST_CTYPE_REG register
- *  Card bus width configuration register
- */
-#define SDHOST_CTYPE_REG (DR_REG_SDHOST_BASE + 0x18)
-/** SDHOST_CARD_WIDTH4 : R/W; bitpos: [1:0]; default: 0;
- *  One bit per card indicates if card is 1-bit or 4-bit mode.
- *  0: 1-bit mode;
- *  1: 4-bit mode.
- *  Bit[1:0] correspond to card[1:0] respectively.
- */
-#define SDHOST_CARD_WIDTH4    0x00000003U
-#define SDHOST_CARD_WIDTH4_M  (SDHOST_CARD_WIDTH4_V << SDHOST_CARD_WIDTH4_S)
-#define SDHOST_CARD_WIDTH4_V  0x00000003U
-#define SDHOST_CARD_WIDTH4_S  0
-/** SDHOST_CARD_WIDTH8 : R/W; bitpos: [17:16]; default: 0;
- *  One bit per card indicates if card is in 8-bit mode.
- *  0: Non 8-bit mode;
- *  1: 8-bit mode.
- *  Bit[17:16] correspond to card[1:0] respectively.
- */
-#define SDHOST_CARD_WIDTH8    0x00000003U
-#define SDHOST_CARD_WIDTH8_M  (SDHOST_CARD_WIDTH8_V << SDHOST_CARD_WIDTH8_S)
-#define SDHOST_CARD_WIDTH8_V  0x00000003U
-#define SDHOST_CARD_WIDTH8_S  16
-
-/** SDHOST_BLKSIZ_REG register
- *  Card data block size configuration register
- */
-#define SDHOST_BLKSIZ_REG (DR_REG_SDHOST_BASE + 0x1c)
-/** SDHOST_BLOCK_SIZE : R/W; bitpos: [15:0]; default: 512;
- *  Block size.
- */
-#define SDHOST_BLOCK_SIZE    0x0000FFFFU
-#define SDHOST_BLOCK_SIZE_M  (SDHOST_BLOCK_SIZE_V << SDHOST_BLOCK_SIZE_S)
-#define SDHOST_BLOCK_SIZE_V  0x0000FFFFU
-#define SDHOST_BLOCK_SIZE_S  0
-
-/** SDHOST_BYTCNT_REG register
- *  Data transfer length configuration register
- */
-#define SDHOST_BYTCNT_REG (DR_REG_SDHOST_BASE + 0x20)
-/** SDHOST_BYTE_COUNT : R/W; bitpos: [31:0]; default: 512;
- *  Number of bytes to be transferred, should be an integral multiple of Block Size for
- *  block transfers. For data transfers of undefined byte lengths, byte count should be
- *  set to 0. When byte count is set to 0, it is the responsibility of host to
- *  explicitly send stop/abort command to terminate data transfer.
- */
-#define SDHOST_BYTE_COUNT    0xFFFFFFFFU
-#define SDHOST_BYTE_COUNT_M  (SDHOST_BYTE_COUNT_V << SDHOST_BYTE_COUNT_S)
-#define SDHOST_BYTE_COUNT_V  0xFFFFFFFFU
-#define SDHOST_BYTE_COUNT_S  0
-
-/** SDHOST_INTMASK_REG register
- *  SDIO interrupt mask register
- */
-#define SDHOST_INTMASK_REG (DR_REG_SDHOST_BASE + 0x24)
-/** SDHOST_INT_MASK : R/W; bitpos: [15:0]; default: 0;
- *  These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a
- *  value of 1 enables the interrupt.
- *  Bit 15 (EBE): End-bit error/no CRC error;
- *  Bit 14 (ACD): Auto command done;
- *  Bit 13 (SBE/BCI): Rx Start Bit Error;
- *  Bit 12 (HLE): Hardware locked write error;
- *  Bit 11 (FRUN): FIFO underrun/overrun error;
- *  Bit 10 (HTO): Data starvation-by-host timeout;
- *  Bit 9 (DRTO): Data read timeout;
- *  Bit 8 (RTO): Response timeout;
- *  Bit 7 (DCRC): Data CRC error;
- *  Bit 6 (RCRC): Response CRC error;
- *  Bit 5 (RXDR): Receive FIFO data request;
- *  Bit 4 (TXDR): Transmit FIFO data request;
- *  Bit 3 (DTO): Data transfer over;
- *  Bit 2 (CD): Command done;
- *  Bit 1 (RE): Response error;
- *  Bit 0 (CD): Card detect.
- */
-#define SDHOST_INT_MASK    0x0000FFFFU
-#define SDHOST_INT_MASK_M  (SDHOST_INT_MASK_V << SDHOST_INT_MASK_S)
-#define SDHOST_INT_MASK_V  0x0000FFFFU
-#define SDHOST_INT_MASK_S  0
-/** SDHOST_SDIO_INT_MASK : R/W; bitpos: [17:16]; default: 0;
- *  SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0]
- *  respectively. When masked, SDIO interrupt detection for that card is disabled. 0
- *  masks an interrupt, and 1 enables an interrupt.
- */
-#define SDHOST_SDIO_INT_MASK    0x00000003U
-#define SDHOST_SDIO_INT_MASK_M  (SDHOST_SDIO_INT_MASK_V << SDHOST_SDIO_INT_MASK_S)
-#define SDHOST_SDIO_INT_MASK_V  0x00000003U
-#define SDHOST_SDIO_INT_MASK_S  16
-
-/** SDHOST_CMDARG_REG register
- *  Command argument data register
- */
-#define SDHOST_CMDARG_REG (DR_REG_SDHOST_BASE + 0x28)
-/** SDHOST_CMDARG : R/W; bitpos: [31:0]; default: 0;
- *  Value indicates command argument to be passed to the card.
- */
-#define SDHOST_CMDARG    0xFFFFFFFFU
-#define SDHOST_CMDARG_M  (SDHOST_CMDARG_V << SDHOST_CMDARG_S)
-#define SDHOST_CMDARG_V  0xFFFFFFFFU
-#define SDHOST_CMDARG_S  0
-
-/** SDHOST_CMD_REG register
- *  Command and boot configuration register
- */
-#define SDHOST_CMD_REG (DR_REG_SDHOST_BASE + 0x2c)
-/** SDHOST_CMD_INDEX : R/W; bitpos: [5:0]; default: 0;
- *  Command index.
- */
-#define SDHOST_CMD_INDEX    0x0000003FU
-#define SDHOST_CMD_INDEX_M  (SDHOST_CMD_INDEX_V << SDHOST_CMD_INDEX_S)
-#define SDHOST_CMD_INDEX_V  0x0000003FU
-#define SDHOST_CMD_INDEX_S  0
-/** SDHOST_RESPONSE_EXPECT : R/W; bitpos: [6]; default: 0;
- *  0: No response expected from card; 1: Response expected from card.
- */
-#define SDHOST_RESPONSE_EXPECT    (BIT(6))
-#define SDHOST_RESPONSE_EXPECT_M  (SDHOST_RESPONSE_EXPECT_V << SDHOST_RESPONSE_EXPECT_S)
-#define SDHOST_RESPONSE_EXPECT_V  0x00000001U
-#define SDHOST_RESPONSE_EXPECT_S  6
-/** SDHOST_RESPONSE_LENGTH : R/W; bitpos: [7]; default: 0;
- *  0: Short response expected from card; 1: Long response expected from card.
- */
-#define SDHOST_RESPONSE_LENGTH    (BIT(7))
-#define SDHOST_RESPONSE_LENGTH_M  (SDHOST_RESPONSE_LENGTH_V << SDHOST_RESPONSE_LENGTH_S)
-#define SDHOST_RESPONSE_LENGTH_V  0x00000001U
-#define SDHOST_RESPONSE_LENGTH_S  7
-/** SDHOST_CHECK_RESPONSE_CRC : R/W; bitpos: [8]; default: 0;
- *  0: Do not check; 1: Check response CRC.
- *  Some of command responses do not return valid CRC bits. Software should disable CRC
- *  checks for those commands in order to disable CRC checking by controller.
- */
-#define SDHOST_CHECK_RESPONSE_CRC    (BIT(8))
-#define SDHOST_CHECK_RESPONSE_CRC_M  (SDHOST_CHECK_RESPONSE_CRC_V << SDHOST_CHECK_RESPONSE_CRC_S)
-#define SDHOST_CHECK_RESPONSE_CRC_V  0x00000001U
-#define SDHOST_CHECK_RESPONSE_CRC_S  8
-/** SDHOST_DATA_EXPECTED : R/W; bitpos: [9]; default: 0;
- *  0: No data transfer expected; 1: Data transfer expected.
- */
-#define SDHOST_DATA_EXPECTED    (BIT(9))
-#define SDHOST_DATA_EXPECTED_M  (SDHOST_DATA_EXPECTED_V << SDHOST_DATA_EXPECTED_S)
-#define SDHOST_DATA_EXPECTED_V  0x00000001U
-#define SDHOST_DATA_EXPECTED_S  9
-/** SDHOST_READ_WRITE : R/W; bitpos: [10]; default: 0;
- *  0: Read from card; 1: Write to card.
- *  Don't care if no data is expected from card.
- */
-#define SDHOST_READ_WRITE    (BIT(10))
-#define SDHOST_READ_WRITE_M  (SDHOST_READ_WRITE_V << SDHOST_READ_WRITE_S)
-#define SDHOST_READ_WRITE_V  0x00000001U
-#define SDHOST_READ_WRITE_S  10
-/** SDHOST_TRANSFER_MODE : R/W; bitpos: [11]; default: 0;
- *  0: Block data transfer command; 1: Stream data transfer command.
- *  Don't care if no data expected.
- */
-#define SDHOST_TRANSFER_MODE    (BIT(11))
-#define SDHOST_TRANSFER_MODE_M  (SDHOST_TRANSFER_MODE_V << SDHOST_TRANSFER_MODE_S)
-#define SDHOST_TRANSFER_MODE_V  0x00000001U
-#define SDHOST_TRANSFER_MODE_S  11
-/** SDHOST_SEND_AUTO_STOP : R/W; bitpos: [12]; default: 0;
- *  0: No stop command is sent at the end of data transfer; 1: Send stop command at the
- *  end of data transfer.
- */
-#define SDHOST_SEND_AUTO_STOP    (BIT(12))
-#define SDHOST_SEND_AUTO_STOP_M  (SDHOST_SEND_AUTO_STOP_V << SDHOST_SEND_AUTO_STOP_S)
-#define SDHOST_SEND_AUTO_STOP_V  0x00000001U
-#define SDHOST_SEND_AUTO_STOP_S  12
-/** SDHOST_WAIT_PRVDATA_COMPLETE : R/W; bitpos: [13]; default: 0;
- *  0: Send command at once, even if previous data transfer has not completed; 1: Wait
- *  for previous data transfer to complete before sending Command.
- *  The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of
- *  card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr
- *  should be same as in previous command.
- */
-#define SDHOST_WAIT_PRVDATA_COMPLETE    (BIT(13))
-#define SDHOST_WAIT_PRVDATA_COMPLETE_M  (SDHOST_WAIT_PRVDATA_COMPLETE_V << SDHOST_WAIT_PRVDATA_COMPLETE_S)
-#define SDHOST_WAIT_PRVDATA_COMPLETE_V  0x00000001U
-#define SDHOST_WAIT_PRVDATA_COMPLETE_S  13
-/** SDHOST_STOP_ABORT_CMD : R/W; bitpos: [14]; default: 0;
- *  0: Neither stop nor abort command can stop current data transfer. If abort is sent
- *  to function-number currently selected or not in data-transfer mode, then bit should
- *  be set to 0; 1: Stop or abort command intended to stop current data transfer in
- *  progress.
- *  When open-ended or predefined data transfer is in progress, and host issues stop or
- *  abort command to stop data transfer, bit should be set so that command/data
- *  state-machines of CIU can return correctly to idle state.
- */
-#define SDHOST_STOP_ABORT_CMD    (BIT(14))
-#define SDHOST_STOP_ABORT_CMD_M  (SDHOST_STOP_ABORT_CMD_V << SDHOST_STOP_ABORT_CMD_S)
-#define SDHOST_STOP_ABORT_CMD_V  0x00000001U
-#define SDHOST_STOP_ABORT_CMD_S  14
-/** SDHOST_SEND_INITIALIZATION : R/W; bitpos: [15]; default: 0;
- *  0: Do not send initialization sequence (80 clocks of 1) before sending this
- *  command; 1: Send initialization sequence before sending this command.
- *  After powered on, 80 clocks must be sent to card for initialization before sending
- *  any commands to card. Bit should be set while sending first command to card so that
- *  controller will initialize clocks before sending command to card.
- */
-#define SDHOST_SEND_INITIALIZATION    (BIT(15))
-#define SDHOST_SEND_INITIALIZATION_M  (SDHOST_SEND_INITIALIZATION_V << SDHOST_SEND_INITIALIZATION_S)
-#define SDHOST_SEND_INITIALIZATION_V  0x00000001U
-#define SDHOST_SEND_INITIALIZATION_S  15
-/** SDHOST_CARD_NUMBER : R/W; bitpos: [20:16]; default: 0;
- *  Card number in use. Represents physical slot number of card being accessed. In
- *  SD-only mode, up to two cards are supported.
- */
-#define SDHOST_CARD_NUMBER    0x0000001FU
-#define SDHOST_CARD_NUMBER_M  (SDHOST_CARD_NUMBER_V << SDHOST_CARD_NUMBER_S)
-#define SDHOST_CARD_NUMBER_V  0x0000001FU
-#define SDHOST_CARD_NUMBER_S  16
-/** SDHOST_UPDATE_CLOCK_REGISTERS_ONLY : R/W; bitpos: [21]; default: 0;
- *  0: Normal command sequence; 1: Do not send commands, just update clock register
- *  value into card clock domain.
- *  Following register values are transferred into card clock domain: CLKDIV, CLRSRC,
- *  and CLKENA.
- *  Changes card clocks (change frequency, truncate off or on, and set low-frequency
- *  mode). This is provided in order to change clock frequency or stop clock without
- *  having to send command to cards. During normal command sequence, when
- *  sdhost_update_clock_registers_only = 0, following control registers are transferred
- *  from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new
- *  register values for new command sequence to card(s). When bit is set, there are no
- *  Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
- */
-#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY    (BIT(21))
-#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_M  (SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_V << SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_S)
-#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_V  0x00000001U
-#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_S  21
-/** SDHOST_READ_CEATA_DEVICE : R/W; bitpos: [22]; default: 0;
- *  Read access flag.
- *  0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;
- *  1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.
- *  Software should set this bit to indicate that CE-ATA device is being accessed for
- *  read transfer. This bit is used to disable read data timeout indication while
- *  performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no
- *  less than 10 seconds. SD/MMC should not indicate read data timeout while waiting
- *  for data from CE-ATA device.
- */
-#define SDHOST_READ_CEATA_DEVICE    (BIT(22))
-#define SDHOST_READ_CEATA_DEVICE_M  (SDHOST_READ_CEATA_DEVICE_V << SDHOST_READ_CEATA_DEVICE_S)
-#define SDHOST_READ_CEATA_DEVICE_V  0x00000001U
-#define SDHOST_READ_CEATA_DEVICE_S  22
-/** SDHOST_CCS_EXPECTED : R/W; bitpos: [23]; default: 0;
- *  Expected Command Completion Signal (CCS) configuration.
- *  0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register),
- *  or command does not expect CCS from device;
- *  1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects
- *  command completion signal from CE-ATA device.
- *  If the command expects Command Completion Signal (CCS) from the CE-ATA device, the
- *  software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in
- *  RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is
- *  not masked.
- */
-#define SDHOST_CCS_EXPECTED    (BIT(23))
-#define SDHOST_CCS_EXPECTED_M  (SDHOST_CCS_EXPECTED_V << SDHOST_CCS_EXPECTED_S)
-#define SDHOST_CCS_EXPECTED_V  0x00000001U
-#define SDHOST_CCS_EXPECTED_S  23
-/** SDHOST_USE_HOLE_REG : R/W; bitpos: [29]; default: 1;
- *  Use Hold Register.
- *  0: CMD and DATA sent to card bypassing HOLD Register;
- *  1: CMD and DATA sent to card through the HOLD Register.
- */
-#define SDHOST_USE_HOLE_REG    (BIT(29))
-#define SDHOST_USE_HOLE_REG_M  (SDHOST_USE_HOLE_REG_V << SDHOST_USE_HOLE_REG_S)
-#define SDHOST_USE_HOLE_REG_V  0x00000001U
-#define SDHOST_USE_HOLE_REG_S  29
-/** SDHOST_START_CMD : R/W; bitpos: [31]; default: 0;
- *  Start command. Once command is served by the CIU, this bit is automatically
- *  cleared. When this bit is set, host should not attempt to write to any command
- *  registers. If a write is attempted, hardware lock error is set in raw interrupt
- *  register. Once command is sent and a response is received from SD_MMC_CEATA cards,
- *  Command Done bit is set in the raw interrupt Register.
- */
-#define SDHOST_START_CMD    (BIT(31))
-#define SDHOST_START_CMD_M  (SDHOST_START_CMD_V << SDHOST_START_CMD_S)
-#define SDHOST_START_CMD_V  0x00000001U
-#define SDHOST_START_CMD_S  31
-
-/** SDHOST_RESP0_REG register
- *  Response data register
- */
-#define SDHOST_RESP0_REG (DR_REG_SDHOST_BASE + 0x30)
-/** SDHOST_RESPONSE0_REG : RO; bitpos: [31:0]; default: 0;
- *  Bit[31:0] of response.
- */
-#define SDHOST_RESPONSE0_REG    0xFFFFFFFFU
-#define SDHOST_RESPONSE0_REG_M  (SDHOST_RESPONSE0_REG_V << SDHOST_RESPONSE0_REG_S)
-#define SDHOST_RESPONSE0_REG_V  0xFFFFFFFFU
-#define SDHOST_RESPONSE0_REG_S  0
-
-/** SDHOST_RESP1_REG register
- *  Long response data register
- */
-#define SDHOST_RESP1_REG (DR_REG_SDHOST_BASE + 0x34)
-/** SDHOST_RESPONSE1_REG : RO; bitpos: [31:0]; default: 0;
- *  Bit[63:32] of long response.
- */
-#define SDHOST_RESPONSE1_REG    0xFFFFFFFFU
-#define SDHOST_RESPONSE1_REG_M  (SDHOST_RESPONSE1_REG_V << SDHOST_RESPONSE1_REG_S)
-#define SDHOST_RESPONSE1_REG_V  0xFFFFFFFFU
-#define SDHOST_RESPONSE1_REG_S  0
-
-/** SDHOST_RESP2_REG register
- *  Long response data register
- */
-#define SDHOST_RESP2_REG (DR_REG_SDHOST_BASE + 0x38)
-/** SDHOST_RESPONSE2_REG : RO; bitpos: [31:0]; default: 0;
- *  Bit[95:64] of long response.
- */
-#define SDHOST_RESPONSE2_REG    0xFFFFFFFFU
-#define SDHOST_RESPONSE2_REG_M  (SDHOST_RESPONSE2_REG_V << SDHOST_RESPONSE2_REG_S)
-#define SDHOST_RESPONSE2_REG_V  0xFFFFFFFFU
-#define SDHOST_RESPONSE2_REG_S  0
-
-/** SDHOST_RESP3_REG register
- *  Long response data register
- */
-#define SDHOST_RESP3_REG (DR_REG_SDHOST_BASE + 0x3c)
-/** SDHOST_RESPONSE3_REG : RO; bitpos: [31:0]; default: 0;
- *  Bit[127:96] of long response.
- */
-#define SDHOST_RESPONSE3_REG    0xFFFFFFFFU
-#define SDHOST_RESPONSE3_REG_M  (SDHOST_RESPONSE3_REG_V << SDHOST_RESPONSE3_REG_S)
-#define SDHOST_RESPONSE3_REG_V  0xFFFFFFFFU
-#define SDHOST_RESPONSE3_REG_S  0
-
-/** SDHOST_MINTSTS_REG register
- *  Masked interrupt status register
- */
-#define SDHOST_MINTSTS_REG (DR_REG_SDHOST_BASE + 0x40)
-/** SDHOST_INT_STATUS_MSK : RO; bitpos: [15:0]; default: 0;
- *  Interrupt enabled only if corresponding bit in interrupt mask register is set.
- *  Bit 15 (EBE): End-bit error/no CRC error;
- *  Bit 14 (ACD): Auto command done;
- *  Bit 13 (SBE/BCI): RX Start Bit Error;
- *  Bit 12 (HLE): Hardware locked write error;
- *  Bit 11 (FRUN): FIFO underrun/overrun error;
- *  Bit 10 (HTO): Data starvation by host timeout (HTO);
- *  Bit 9 (DTRO): Data read timeout;
- *  Bit 8 (RTO): Response timeout;
- *  Bit 7 (DCRC): Data CRC error;
- *  Bit 6 (RCRC): Response CRC error;
- *  Bit 5 (RXDR): Receive FIFO data request;
- *  Bit 4 (TXDR): Transmit FIFO data request;
- *  Bit 3 (DTO): Data transfer over;
- *  Bit 2 (CD): Command done;
- *  Bit 1 (RE): Response error;
- *  Bit 0 (CD): Card detect.
- */
-#define SDHOST_INT_STATUS_MSK    0x0000FFFFU
-#define SDHOST_INT_STATUS_MSK_M  (SDHOST_INT_STATUS_MSK_V << SDHOST_INT_STATUS_MSK_S)
-#define SDHOST_INT_STATUS_MSK_V  0x0000FFFFU
-#define SDHOST_INT_STATUS_MSK_S  0
-/** SDHOST_SDIO_INTERRUPT_MSK : RO; bitpos: [17:16]; default: 0;
- *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
- *  card0, respectively. SDIO interrupt for card is enabled only if corresponding
- *  sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit
- *  enables interrupt).
- */
-#define SDHOST_SDIO_INTERRUPT_MSK    0x00000003U
-#define SDHOST_SDIO_INTERRUPT_MSK_M  (SDHOST_SDIO_INTERRUPT_MSK_V << SDHOST_SDIO_INTERRUPT_MSK_S)
-#define SDHOST_SDIO_INTERRUPT_MSK_V  0x00000003U
-#define SDHOST_SDIO_INTERRUPT_MSK_S  16
-
-/** SDHOST_RINTSTS_REG register
- *  Raw interrupt status register
- */
-#define SDHOST_RINTSTS_REG (DR_REG_SDHOST_BASE + 0x44)
-/** SDHOST_INT_STATUS_RAW : R/W; bitpos: [15:0]; default: 0;
- *  Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits
- *  are logged regardless of interrupt mask status.
- *  Bit 15 (EBE): End-bit error/no CRC error;
- *  Bit 14 (ACD): Auto command done;
- *  Bit 13 (SBE/BCI): RX Start Bit Error;
- *  Bit 12 (HLE): Hardware locked write error;
- *  Bit 11 (FRUN): FIFO underrun/overrun error;
- *  Bit 10 (HTO): Data starvation by host timeout (HTO);
- *  Bit 9 (DTRO): Data read timeout;
- *  Bit 8 (RTO): Response timeout;
- *  Bit 7 (DCRC): Data CRC error;
- *  Bit 6 (RCRC): Response CRC error;
- *  Bit 5 (RXDR): Receive FIFO data request;
- *  Bit 4 (TXDR): Transmit FIFO data request;
- *  Bit 3 (DTO): Data transfer over;
- *  Bit 2 (CD): Command done;
- *  Bit 1 (RE): Response error;
- *  Bit 0 (CD): Card detect.
- */
-#define SDHOST_INT_STATUS_RAW    0x0000FFFFU
-#define SDHOST_INT_STATUS_RAW_M  (SDHOST_INT_STATUS_RAW_V << SDHOST_INT_STATUS_RAW_S)
-#define SDHOST_INT_STATUS_RAW_V  0x0000FFFFU
-#define SDHOST_INT_STATUS_RAW_S  0
-/** SDHOST_SDIO_INTERRUPT_RAW : R/W; bitpos: [17:16]; default: 0;
- *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
- *  card0, respectively. Setting a bit clears the corresponding interrupt bit and
- *  writing 0 has no effect.
- *  0: No SDIO interrupt from card;
- *  1: SDIO interrupt from card.
- */
-#define SDHOST_SDIO_INTERRUPT_RAW    0x00000003U
-#define SDHOST_SDIO_INTERRUPT_RAW_M  (SDHOST_SDIO_INTERRUPT_RAW_V << SDHOST_SDIO_INTERRUPT_RAW_S)
-#define SDHOST_SDIO_INTERRUPT_RAW_V  0x00000003U
-#define SDHOST_SDIO_INTERRUPT_RAW_S  16
-
-/** SDHOST_STATUS_REG register
- *  SD/MMC status register
- */
-#define SDHOST_STATUS_REG (DR_REG_SDHOST_BASE + 0x48)
-/** SDHOST_FIFO_RX_WATERMARK : RO; bitpos: [0]; default: 0;
- *  FIFO reached Receive watermark level, not qualified with data transfer.
- */
-#define SDHOST_FIFO_RX_WATERMARK    (BIT(0))
-#define SDHOST_FIFO_RX_WATERMARK_M  (SDHOST_FIFO_RX_WATERMARK_V << SDHOST_FIFO_RX_WATERMARK_S)
-#define SDHOST_FIFO_RX_WATERMARK_V  0x00000001U
-#define SDHOST_FIFO_RX_WATERMARK_S  0
-/** SDHOST_FIFO_TX_WATERMARK : RO; bitpos: [1]; default: 1;
- *  FIFO reached Transmit watermark level, not qualified with data transfer.
- */
-#define SDHOST_FIFO_TX_WATERMARK    (BIT(1))
-#define SDHOST_FIFO_TX_WATERMARK_M  (SDHOST_FIFO_TX_WATERMARK_V << SDHOST_FIFO_TX_WATERMARK_S)
-#define SDHOST_FIFO_TX_WATERMARK_V  0x00000001U
-#define SDHOST_FIFO_TX_WATERMARK_S  1
-/** SDHOST_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- *  FIFO is empty status.
- */
-#define SDHOST_FIFO_EMPTY    (BIT(2))
-#define SDHOST_FIFO_EMPTY_M  (SDHOST_FIFO_EMPTY_V << SDHOST_FIFO_EMPTY_S)
-#define SDHOST_FIFO_EMPTY_V  0x00000001U
-#define SDHOST_FIFO_EMPTY_S  2
-/** SDHOST_FIFO_FULL : RO; bitpos: [3]; default: 0;
- *  FIFO is full status.
- */
-#define SDHOST_FIFO_FULL    (BIT(3))
-#define SDHOST_FIFO_FULL_M  (SDHOST_FIFO_FULL_V << SDHOST_FIFO_FULL_S)
-#define SDHOST_FIFO_FULL_V  0x00000001U
-#define SDHOST_FIFO_FULL_S  3
-/** SDHOST_COMMAND_FSM_STATES : RO; bitpos: [7:4]; default: 1;
- *  Command FSM states.
- *  0: Idle;
- *  1: Send init sequence;
- *  2: Send cmd start bit;
- *  3: Send cmd tx bit;
- *  4: Send cmd index + arg;
- *  5: Send cmd crc7;
- *  6: Send cmd end bit;
- *  7: Receive resp start bit;
- *  8: Receive resp IRQ response;
- *  9: Receive resp tx bit;
- *  10: Receive resp cmd idx;
- *  11: Receive resp data;
- *  12: Receive resp crc7;
- *  13: Receive resp end bit;
- *  14: Cmd path wait NCC;
- *  15: Wait, cmd-to-response turnaround.
- */
-#define SDHOST_COMMAND_FSM_STATES    0x0000000FU
-#define SDHOST_COMMAND_FSM_STATES_M  (SDHOST_COMMAND_FSM_STATES_V << SDHOST_COMMAND_FSM_STATES_S)
-#define SDHOST_COMMAND_FSM_STATES_V  0x0000000FU
-#define SDHOST_COMMAND_FSM_STATES_S  4
-/** SDHOST_DATA_3_STATUS : RO; bitpos: [8]; default: 1;
- *  Raw selected sdhost_card_data[3], checks whether card is present.
- *  0: card not present;
- *  1: card present.
- */
-#define SDHOST_DATA_3_STATUS    (BIT(8))
-#define SDHOST_DATA_3_STATUS_M  (SDHOST_DATA_3_STATUS_V << SDHOST_DATA_3_STATUS_S)
-#define SDHOST_DATA_3_STATUS_V  0x00000001U
-#define SDHOST_DATA_3_STATUS_S  8
-/** SDHOST_DATA_BUSY : RO; bitpos: [9]; default: 1;
- *  Inverted version of raw selected sdhost_card_data[0].
- *  0: Card data not busy;
- *  1: Card data busy.
- */
-#define SDHOST_DATA_BUSY    (BIT(9))
-#define SDHOST_DATA_BUSY_M  (SDHOST_DATA_BUSY_V << SDHOST_DATA_BUSY_S)
-#define SDHOST_DATA_BUSY_V  0x00000001U
-#define SDHOST_DATA_BUSY_S  9
-/** SDHOST_DATA_STATE_MC_BUSY : RO; bitpos: [10]; default: 1;
- *  Data transmit or receive state-machine is busy.
- */
-#define SDHOST_DATA_STATE_MC_BUSY    (BIT(10))
-#define SDHOST_DATA_STATE_MC_BUSY_M  (SDHOST_DATA_STATE_MC_BUSY_V << SDHOST_DATA_STATE_MC_BUSY_S)
-#define SDHOST_DATA_STATE_MC_BUSY_V  0x00000001U
-#define SDHOST_DATA_STATE_MC_BUSY_S  10
-/** SDHOST_RESPONSE_INDEX : RO; bitpos: [16:11]; default: 0;
- *  Index of previous response, including any auto-stop sent by core.
- */
-#define SDHOST_RESPONSE_INDEX    0x0000003FU
-#define SDHOST_RESPONSE_INDEX_M  (SDHOST_RESPONSE_INDEX_V << SDHOST_RESPONSE_INDEX_S)
-#define SDHOST_RESPONSE_INDEX_V  0x0000003FU
-#define SDHOST_RESPONSE_INDEX_S  11
-/** SDHOST_FIFO_COUNT : RO; bitpos: [29:17]; default: 0;
- *  FIFO count, number of filled locations in FIFO.
- */
-#define SDHOST_FIFO_COUNT    0x00001FFFU
-#define SDHOST_FIFO_COUNT_M  (SDHOST_FIFO_COUNT_V << SDHOST_FIFO_COUNT_S)
-#define SDHOST_FIFO_COUNT_V  0x00001FFFU
-#define SDHOST_FIFO_COUNT_S  17
-
-/** SDHOST_FIFOTH_REG register
- *  FIFO configuration register
- */
-#define SDHOST_FIFOTH_REG (DR_REG_SDHOST_BASE + 0x4c)
-/** SDHOST_TX_WMARK : R/W; bitpos: [11:0]; default: 0;
- *  FIFO threshold watermark level when transmitting data to card. When FIFO data count
- *  is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is
- *  enabled, then interrupt  occurs. During end of packet, request or interrupt is
- *  generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO
- *  threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA
- *  request. During end of packet, on last interrupt, host is responsible for filling
- *  FIFO with only required remaining bytes (not before FIFO is full or after CIU
- *  completes data transfers, because FIFO may not be empty).  In DMA mode, at end of
- *  packet, if last transfer is less than burst  size, DMA controller does single
- *  cycles until required bytes are  transferred.
- */
-#define SDHOST_TX_WMARK    0x00000FFFU
-#define SDHOST_TX_WMARK_M  (SDHOST_TX_WMARK_V << SDHOST_TX_WMARK_S)
-#define SDHOST_TX_WMARK_V  0x00000FFFU
-#define SDHOST_TX_WMARK_S  0
-/** SDHOST_RX_WMARK : R/W; bitpos: [26:16]; default: 0;
- *  FIFO threshold watermark level when receiving data to card.When FIFO data count
- *  reaches greater than this number , DMA/FIFO request is raised. During end of
- *  packet, request is generated regardless of threshold programming in order to
- *  complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR)
- *  interrupt is enabled, then interrupt is generated instead of DMA request.During end
- *  of packet, interrupt is not generated if threshold programming is larger than any
- *  remaining data. It is responsibility of host to read remaining bytes on seeing Data
- *  Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are
- *  less than threshold, DMA request does single transfers to flush out any remaining
- *  bytes before Data Transfer Done interrupt is set.
- */
-#define SDHOST_RX_WMARK    0x000007FFU
-#define SDHOST_RX_WMARK_M  (SDHOST_RX_WMARK_V << SDHOST_RX_WMARK_S)
-#define SDHOST_RX_WMARK_V  0x000007FFU
-#define SDHOST_RX_WMARK_S  16
-/** SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE : R/W; bitpos: [30:28]; default: 0;
- *  Burst size of multiple transaction, should be programmed same as DMA controller
- *  multiple-transaction-size SDHOST_SRC/DEST_MSIZE.
- *  000: 1-byte transfer;
- *  001: 4-byte transfer;
- *  010: 8-byte transfer;
- *  011: 16-byte transfer;
- *  100: 32-byte transfer;
- *  101: 64-byte transfer;
- *  110: 128-byte transfer;
- *  111: 256-byte transfer.
- */
-#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE    0x00000007U
-#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_M  (SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_V << SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_S)
-#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_V  0x00000007U
-#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_S  28
-
-/** SDHOST_CDETECT_REG register
- *  Card detect register
- */
-#define SDHOST_CDETECT_REG (DR_REG_SDHOST_BASE + 0x50)
-/** SDHOST_CARD_DETECT_N : RO; bitpos: [1:0]; default: 0;
- *  Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0
- *  represents presence of card. Only NUM_CARDS number of bits are implemented.
- */
-#define SDHOST_CARD_DETECT_N    0x00000003U
-#define SDHOST_CARD_DETECT_N_M  (SDHOST_CARD_DETECT_N_V << SDHOST_CARD_DETECT_N_S)
-#define SDHOST_CARD_DETECT_N_V  0x00000003U
-#define SDHOST_CARD_DETECT_N_S  0
-
-/** SDHOST_WRTPRT_REG register
- *  Card write protection (WP) status register
- */
-#define SDHOST_WRTPRT_REG (DR_REG_SDHOST_BASE + 0x54)
-/** SDHOST_WRITE_PROTECT : RO; bitpos: [1:0]; default: 0;
- *  Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write
- *  protection. Only NUM_CARDS number of bits are implemented.
- */
-#define SDHOST_WRITE_PROTECT    0x00000003U
-#define SDHOST_WRITE_PROTECT_M  (SDHOST_WRITE_PROTECT_V << SDHOST_WRITE_PROTECT_S)
-#define SDHOST_WRITE_PROTECT_V  0x00000003U
-#define SDHOST_WRITE_PROTECT_S  0
-
-/** SDHOST_TCBCNT_REG register
- *  Transferred byte count register
- */
-#define SDHOST_TCBCNT_REG (DR_REG_SDHOST_BASE + 0x5c)
-/** SDHOST_TCBCNT : RO; bitpos: [31:0]; default: 0;
- *  Number of bytes transferred by CIU unit to card.
- */
-#define SDHOST_TCBCNT    0xFFFFFFFFU
-#define SDHOST_TCBCNT_M  (SDHOST_TCBCNT_V << SDHOST_TCBCNT_S)
-#define SDHOST_TCBCNT_V  0xFFFFFFFFU
-#define SDHOST_TCBCNT_S  0
-
-/** SDHOST_TBBCNT_REG register
- *  Transferred byte count register
- */
-#define SDHOST_TBBCNT_REG (DR_REG_SDHOST_BASE + 0x60)
-/** SDHOST_TBBCNT : RO; bitpos: [31:0]; default: 0;
- *  Number of bytes transferred between Host/DMA memory and BIU FIFO.
- */
-#define SDHOST_TBBCNT    0xFFFFFFFFU
-#define SDHOST_TBBCNT_M  (SDHOST_TBBCNT_V << SDHOST_TBBCNT_S)
-#define SDHOST_TBBCNT_V  0xFFFFFFFFU
-#define SDHOST_TBBCNT_S  0
-
-/** SDHOST_DEBNCE_REG register
- *  Debounce filter time configuration register
- */
-#define SDHOST_DEBNCE_REG (DR_REG_SDHOST_BASE + 0x64)
-/** SDHOST_DEBOUNCE_COUNT : R/W; bitpos: [23:0]; default: 0;
- *  Number of host clocks (clk) used by debounce filter logic. The typical debounce
- *  time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted
- *  or removed.
- */
-#define SDHOST_DEBOUNCE_COUNT    0x00FFFFFFU
-#define SDHOST_DEBOUNCE_COUNT_M  (SDHOST_DEBOUNCE_COUNT_V << SDHOST_DEBOUNCE_COUNT_S)
-#define SDHOST_DEBOUNCE_COUNT_V  0x00FFFFFFU
-#define SDHOST_DEBOUNCE_COUNT_S  0
-
-/** SDHOST_USRID_REG register
- *  User ID (scratchpad) register
- */
-#define SDHOST_USRID_REG (DR_REG_SDHOST_BASE + 0x68)
-/** SDHOST_USRID : R/W; bitpos: [31:0]; default: 0;
- *  User identification register, value set by user. Can also be used as a scratchpad
- *  register by user.
- */
-#define SDHOST_USRID    0xFFFFFFFFU
-#define SDHOST_USRID_M  (SDHOST_USRID_V << SDHOST_USRID_S)
-#define SDHOST_USRID_V  0xFFFFFFFFU
-#define SDHOST_USRID_S  0
-
-/** SDHOST_VERID_REG register
- *  Version ID (scratchpad) register
- */
-#define SDHOST_VERID_REG (DR_REG_SDHOST_BASE + 0x6c)
-/** SDHOST_VERSIONID : RO; bitpos: [31:0]; default: 1412572938;
- *  Hardware version register. Can also be read by fireware.
- */
-#define SDHOST_VERSIONID    0xFFFFFFFFU
-#define SDHOST_VERSIONID_M  (SDHOST_VERSIONID_V << SDHOST_VERSIONID_S)
-#define SDHOST_VERSIONID_V  0xFFFFFFFFU
-#define SDHOST_VERSIONID_S  0
-
-/** SDHOST_HCON_REG register
- *  Hardware feature register
- */
-#define SDHOST_HCON_REG (DR_REG_SDHOST_BASE + 0x70)
-/** SDHOST_CARD_TYPE_REG : RO; bitpos: [0]; default: 1;
- *  Hardware support SDIO and MMC.
- */
-#define SDHOST_CARD_TYPE_REG    (BIT(0))
-#define SDHOST_CARD_TYPE_REG_M  (SDHOST_CARD_TYPE_REG_V << SDHOST_CARD_TYPE_REG_S)
-#define SDHOST_CARD_TYPE_REG_V  0x00000001U
-#define SDHOST_CARD_TYPE_REG_S  0
-/** SDHOST_CARD_NUM_REG : RO; bitpos: [5:1]; default: 1;
- *  Support card number is 2.
- */
-#define SDHOST_CARD_NUM_REG    0x0000001FU
-#define SDHOST_CARD_NUM_REG_M  (SDHOST_CARD_NUM_REG_V << SDHOST_CARD_NUM_REG_S)
-#define SDHOST_CARD_NUM_REG_V  0x0000001FU
-#define SDHOST_CARD_NUM_REG_S  1
-/** SDHOST_BUS_TYPE_REG : RO; bitpos: [6]; default: 1;
- *  Register config is APB bus.
- */
-#define SDHOST_BUS_TYPE_REG    (BIT(6))
-#define SDHOST_BUS_TYPE_REG_M  (SDHOST_BUS_TYPE_REG_V << SDHOST_BUS_TYPE_REG_S)
-#define SDHOST_BUS_TYPE_REG_V  0x00000001U
-#define SDHOST_BUS_TYPE_REG_S  6
-/** SDHOST_DATA_WIDTH_REG : RO; bitpos: [9:7]; default: 1;
- *  Regisger data widht is 32.
- */
-#define SDHOST_DATA_WIDTH_REG    0x00000007U
-#define SDHOST_DATA_WIDTH_REG_M  (SDHOST_DATA_WIDTH_REG_V << SDHOST_DATA_WIDTH_REG_S)
-#define SDHOST_DATA_WIDTH_REG_V  0x00000007U
-#define SDHOST_DATA_WIDTH_REG_S  7
-/** SDHOST_ADDR_WIDTH_REG : RO; bitpos: [15:10]; default: 19;
- *  Register address width is 32.
- */
-#define SDHOST_ADDR_WIDTH_REG    0x0000003FU
-#define SDHOST_ADDR_WIDTH_REG_M  (SDHOST_ADDR_WIDTH_REG_V << SDHOST_ADDR_WIDTH_REG_S)
-#define SDHOST_ADDR_WIDTH_REG_V  0x0000003FU
-#define SDHOST_ADDR_WIDTH_REG_S  10
-/** SDHOST_DMA_WIDTH_REG : RO; bitpos: [20:18]; default: 1;
- *  DMA data witdth is 32.
- */
-#define SDHOST_DMA_WIDTH_REG    0x00000007U
-#define SDHOST_DMA_WIDTH_REG_M  (SDHOST_DMA_WIDTH_REG_V << SDHOST_DMA_WIDTH_REG_S)
-#define SDHOST_DMA_WIDTH_REG_V  0x00000007U
-#define SDHOST_DMA_WIDTH_REG_S  18
-/** SDHOST_RAM_INDISE_REG : RO; bitpos: [21]; default: 0;
- *  Inside RAM in SDMMC module.
- */
-#define SDHOST_RAM_INDISE_REG    (BIT(21))
-#define SDHOST_RAM_INDISE_REG_M  (SDHOST_RAM_INDISE_REG_V << SDHOST_RAM_INDISE_REG_S)
-#define SDHOST_RAM_INDISE_REG_V  0x00000001U
-#define SDHOST_RAM_INDISE_REG_S  21
-/** SDHOST_HOLD_REG : RO; bitpos: [22]; default: 1;
- *  Have a hold regiser in data path .
- */
-#define SDHOST_HOLD_REG    (BIT(22))
-#define SDHOST_HOLD_REG_M  (SDHOST_HOLD_REG_V << SDHOST_HOLD_REG_S)
-#define SDHOST_HOLD_REG_V  0x00000001U
-#define SDHOST_HOLD_REG_S  22
-/** SDHOST_NUM_CLK_DIV_REG : RO; bitpos: [25:24]; default: 3;
- *  Have 4 clk divider in design .
- */
-#define SDHOST_NUM_CLK_DIV_REG    0x00000003U
-#define SDHOST_NUM_CLK_DIV_REG_M  (SDHOST_NUM_CLK_DIV_REG_V << SDHOST_NUM_CLK_DIV_REG_S)
-#define SDHOST_NUM_CLK_DIV_REG_V  0x00000003U
-#define SDHOST_NUM_CLK_DIV_REG_S  24
-
-/** SDHOST_UHS_REG register
- *  UHS-1 register
- */
-#define SDHOST_UHS_REG (DR_REG_SDHOST_BASE + 0x74)
-/** SDHOST_DDR_REG : R/W; bitpos: [17:16]; default: 0;
- *  DDR mode selecton,1 bit for each card.
- *  0-Non-DDR mdoe.
- *  1-DDR mdoe.
- */
-#define SDHOST_DDR_REG    0x00000003U
-#define SDHOST_DDR_REG_M  (SDHOST_DDR_REG_V << SDHOST_DDR_REG_S)
-#define SDHOST_DDR_REG_V  0x00000003U
-#define SDHOST_DDR_REG_S  16
-
-/** SDHOST_RST_N_REG register
- *  Card reset register
- */
-#define SDHOST_RST_N_REG (DR_REG_SDHOST_BASE + 0x78)
-/** SDHOST_CARD_RESET : R/W; bitpos: [1:0]; default: 1;
- *  Hardware reset.
- *  1: Active mode;
- *  0: Reset.
- *  These bits cause the cards to enter pre-idle state, which requires them to be
- *  re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0,
- *  SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1.
- */
-#define SDHOST_CARD_RESET    0x00000003U
-#define SDHOST_CARD_RESET_M  (SDHOST_CARD_RESET_V << SDHOST_CARD_RESET_S)
-#define SDHOST_CARD_RESET_V  0x00000003U
-#define SDHOST_CARD_RESET_S  0
-
-/** SDHOST_BMOD_REG register
- *  Burst mode transfer configuration register
- */
-#define SDHOST_BMOD_REG (DR_REG_SDHOST_BASE + 0x80)
-/** SDHOST_BMOD_SWR : R/W; bitpos: [0]; default: 0;
- *  Software Reset. When set, the DMA Controller resets all its internal registers. It
- *  is automatically cleared after one clock cycle.
- */
-#define SDHOST_BMOD_SWR    (BIT(0))
-#define SDHOST_BMOD_SWR_M  (SDHOST_BMOD_SWR_V << SDHOST_BMOD_SWR_S)
-#define SDHOST_BMOD_SWR_V  0x00000001U
-#define SDHOST_BMOD_SWR_S  0
-/** SDHOST_BMOD_FB : R/W; bitpos: [1]; default: 0;
- *  Fixed Burst. Controls whether the AHB Master interface performs fixed burst
- *  transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16
- *  during start of normal burst transfers. When reset, the AHB will use SINGLE and
- *  INCR burst transfer operations.
- */
-#define SDHOST_BMOD_FB    (BIT(1))
-#define SDHOST_BMOD_FB_M  (SDHOST_BMOD_FB_V << SDHOST_BMOD_FB_S)
-#define SDHOST_BMOD_FB_V  0x00000001U
-#define SDHOST_BMOD_FB_S  1
-/** SDHOST_BMOD_DE : R/W; bitpos: [7]; default: 0;
- *  IDMAC Enable. When set, the IDMAC is enabled.
- */
-#define SDHOST_BMOD_DE    (BIT(7))
-#define SDHOST_BMOD_DE_M  (SDHOST_BMOD_DE_V << SDHOST_BMOD_DE_S)
-#define SDHOST_BMOD_DE_V  0x00000001U
-#define SDHOST_BMOD_DE_S  7
-/** SDHOST_BMOD_PBL : R/W; bitpos: [10:8]; default: 0;
- *  Programmable Burst Length. These bits indicate the maximum number of beats to be
- *  performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always
- *  attempt to burst as specified in PBL each time it starts a burst transfer on the
- *  host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value
- *  is the mirror of MSIZE of FIFOTH register. In order to change this value, write the
- *  required value to FIFOTH register. This is an encode value as follows:
- *  000: 1-byte transfer;
- *  001: 4-byte transfer;
- *  010: 8-byte transfer;
- *  011: 16-byte transfer;
- *  100: 32-byte transfer;
- *  101: 64-byte transfer;
- *  110: 128-byte transfer;
- *  111: 256-byte transfer.
- *  PBL is a read-only value and is applicable only for data access, it does not apply
- *  to descriptor access.
- */
-#define SDHOST_BMOD_PBL    0x00000007U
-#define SDHOST_BMOD_PBL_M  (SDHOST_BMOD_PBL_V << SDHOST_BMOD_PBL_S)
-#define SDHOST_BMOD_PBL_V  0x00000007U
-#define SDHOST_BMOD_PBL_S  8
-
-/** SDHOST_PLDMND_REG register
- *  Poll demand configuration register
- */
-#define SDHOST_PLDMND_REG (DR_REG_SDHOST_BASE + 0x84)
-/** SDHOST_PLDMND_PD : WO; bitpos: [31:0]; default: 0;
- *  Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the
- *  Suspend state. The host needs to write any value into this register for the IDMAC
- *  FSM to resume normal descriptor fetch operation. This is a write only .
- */
-#define SDHOST_PLDMND_PD    0xFFFFFFFFU
-#define SDHOST_PLDMND_PD_M  (SDHOST_PLDMND_PD_V << SDHOST_PLDMND_PD_S)
-#define SDHOST_PLDMND_PD_V  0xFFFFFFFFU
-#define SDHOST_PLDMND_PD_S  0
-
-/** SDHOST_DBADDR_REG register
- *  Descriptor base address register
- */
-#define SDHOST_DBADDR_REG (DR_REG_SDHOST_BASE + 0x88)
-/** SDHOST_DBADDR : R/W; bitpos: [31:0]; default: 0;
- *  Start of Descriptor List. Contains the base address of the First Descriptor. The
- *  LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence
- *  these LSB bits may be treated as read-only.
- */
-#define SDHOST_DBADDR    0xFFFFFFFFU
-#define SDHOST_DBADDR_M  (SDHOST_DBADDR_V << SDHOST_DBADDR_S)
-#define SDHOST_DBADDR_V  0xFFFFFFFFU
-#define SDHOST_DBADDR_S  0
-
-/** SDHOST_IDSTS_REG register
- *  IDMAC status register
- */
-#define SDHOST_IDSTS_REG (DR_REG_SDHOST_BASE + 0x8c)
-/** SDHOST_IDSTS_TI : R/W; bitpos: [0]; default: 0;
- *  Transmit Interrupt. Indicates that data transmission is finished for a descriptor.
- *  Writing 1 clears this bit.
- */
-#define SDHOST_IDSTS_TI    (BIT(0))
-#define SDHOST_IDSTS_TI_M  (SDHOST_IDSTS_TI_V << SDHOST_IDSTS_TI_S)
-#define SDHOST_IDSTS_TI_V  0x00000001U
-#define SDHOST_IDSTS_TI_S  0
-/** SDHOST_IDSTS_RI : R/W; bitpos: [1]; default: 0;
- *  Receive Interrupt. Indicates the completion of data reception for a descriptor.
- *  Writing 1 clears this bit.
- */
-#define SDHOST_IDSTS_RI    (BIT(1))
-#define SDHOST_IDSTS_RI_M  (SDHOST_IDSTS_RI_V << SDHOST_IDSTS_RI_S)
-#define SDHOST_IDSTS_RI_V  0x00000001U
-#define SDHOST_IDSTS_RI_S  1
-/** SDHOST_IDSTS_FBE : R/W; bitpos: [2]; default: 0;
- *  Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) .
- *  When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this
- *  bit.
- */
-#define SDHOST_IDSTS_FBE    (BIT(2))
-#define SDHOST_IDSTS_FBE_M  (SDHOST_IDSTS_FBE_V << SDHOST_IDSTS_FBE_S)
-#define SDHOST_IDSTS_FBE_V  0x00000001U
-#define SDHOST_IDSTS_FBE_S  2
-/** SDHOST_IDSTS_DU : R/W; bitpos: [4]; default: 0;
- *  Descriptor Unavailable Interrupt. This bit is set when the descriptor is
- *  unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit.
- */
-#define SDHOST_IDSTS_DU    (BIT(4))
-#define SDHOST_IDSTS_DU_M  (SDHOST_IDSTS_DU_V << SDHOST_IDSTS_DU_S)
-#define SDHOST_IDSTS_DU_V  0x00000001U
-#define SDHOST_IDSTS_DU_S  4
-/** SDHOST_IDSTS_CES : R/W; bitpos: [5]; default: 0;
- *  Card Error Summary. Indicates the status of the transaction to/from the card, also
- *  present in RINTSTS. Indicates the logical OR of the following bits:
- *  EBE : End Bit Error;
- *  RTO : Response Timeout/Boot Ack Timeout;
- *  RCRC : Response CRC;
- *  SBE : Start Bit Error;
- *  DRTO : Data Read Timeout/BDS timeout;
- *  DCRC : Data CRC for Receive;
- *  RE : Response Error.
- *  Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting
- *  of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response
- *  error.
- */
-#define SDHOST_IDSTS_CES    (BIT(5))
-#define SDHOST_IDSTS_CES_M  (SDHOST_IDSTS_CES_V << SDHOST_IDSTS_CES_S)
-#define SDHOST_IDSTS_CES_V  0x00000001U
-#define SDHOST_IDSTS_CES_S  5
-/** SDHOST_IDSTS_NIS : R/W; bitpos: [8]; default: 0;
- *  Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit
- *  Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This
- *  is a sticky bit and must be cleared each time a corresponding bit that causes NIS
- *  to be set is cleared. Writing 1 clears this bit.
- */
-#define SDHOST_IDSTS_NIS    (BIT(8))
-#define SDHOST_IDSTS_NIS_M  (SDHOST_IDSTS_NIS_V << SDHOST_IDSTS_NIS_S)
-#define SDHOST_IDSTS_NIS_V  0x00000001U
-#define SDHOST_IDSTS_NIS_S  8
-/** SDHOST_IDSTS_AIS : R/W; bitpos: [9]; default: 0;
- *  Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus
- *  Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is
- *  a sticky bit and must be cleared each time a corresponding bit that causes AIS to
- *  be set is cleared. Writing 1 clears this bit.
- */
-#define SDHOST_IDSTS_AIS    (BIT(9))
-#define SDHOST_IDSTS_AIS_M  (SDHOST_IDSTS_AIS_V << SDHOST_IDSTS_AIS_S)
-#define SDHOST_IDSTS_AIS_V  0x00000001U
-#define SDHOST_IDSTS_AIS_S  9
-/** SDHOST_IDSTS_FBE_CODE : R/W; bitpos: [12:10]; default: 0;
- *  Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid
- *  only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an
- *  interrupt.
- *  001: Host Abort received during transmission;
- *  010: Host Abort received during reception;
- *  Others: Reserved.
- */
-#define SDHOST_IDSTS_FBE_CODE    0x00000007U
-#define SDHOST_IDSTS_FBE_CODE_M  (SDHOST_IDSTS_FBE_CODE_V << SDHOST_IDSTS_FBE_CODE_S)
-#define SDHOST_IDSTS_FBE_CODE_V  0x00000007U
-#define SDHOST_IDSTS_FBE_CODE_S  10
-/** SDHOST_IDSTS_FSM : R/W; bitpos: [16:13]; default: 0;
- *  DMAC FSM present state.
- *  0: DMA_IDLE (idle state);
- *  1: DMA_SUSPEND (suspend state);
- *  2: DESC_RD (descriptor reading state);
- *  3: DESC_CHK (descriptor checking state);
- *  4: DMA_RD_REQ_WAIT (read-data request waiting state);
- *  5: DMA_WR_REQ_WAIT (write-data request waiting state);
- *  6: DMA_RD (data-read state);
- *  7: DMA_WR (data-write state);
- *  8: DESC_CLOSE (descriptor close state).
- */
-#define SDHOST_IDSTS_FSM    0x0000000FU
-#define SDHOST_IDSTS_FSM_M  (SDHOST_IDSTS_FSM_V << SDHOST_IDSTS_FSM_S)
-#define SDHOST_IDSTS_FSM_V  0x0000000FU
-#define SDHOST_IDSTS_FSM_S  13
-
-/** SDHOST_IDINTEN_REG register
- *  IDMAC interrupt enable register
- */
-#define SDHOST_IDINTEN_REG (DR_REG_SDHOST_BASE + 0x90)
-/** SDHOST_IDINTEN_TI : R/W; bitpos: [0]; default: 0;
- *  Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
- *  Interrupt is enabled. When reset, Transmit Interrupt is disabled.
- */
-#define SDHOST_IDINTEN_TI    (BIT(0))
-#define SDHOST_IDINTEN_TI_M  (SDHOST_IDINTEN_TI_V << SDHOST_IDINTEN_TI_S)
-#define SDHOST_IDINTEN_TI_V  0x00000001U
-#define SDHOST_IDINTEN_TI_S  0
-/** SDHOST_IDINTEN_RI : R/W; bitpos: [1]; default: 0;
- *  Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
- *  Interrupt is enabled. When reset, Receive Interrupt is disabled.
- */
-#define SDHOST_IDINTEN_RI    (BIT(1))
-#define SDHOST_IDINTEN_RI_M  (SDHOST_IDINTEN_RI_V << SDHOST_IDINTEN_RI_S)
-#define SDHOST_IDINTEN_RI_V  0x00000001U
-#define SDHOST_IDINTEN_RI_S  1
-/** SDHOST_IDINTEN_FBE : R/W; bitpos: [2]; default: 0;
- *  Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
- *  Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is
- *  disabled.
- */
-#define SDHOST_IDINTEN_FBE    (BIT(2))
-#define SDHOST_IDINTEN_FBE_M  (SDHOST_IDINTEN_FBE_V << SDHOST_IDINTEN_FBE_S)
-#define SDHOST_IDINTEN_FBE_V  0x00000001U
-#define SDHOST_IDINTEN_FBE_S  2
-/** SDHOST_IDINTEN_DU : R/W; bitpos: [4]; default: 0;
- *  Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
- *  Enable, the DU interrupt is enabled.
- */
-#define SDHOST_IDINTEN_DU    (BIT(4))
-#define SDHOST_IDINTEN_DU_M  (SDHOST_IDINTEN_DU_V << SDHOST_IDINTEN_DU_S)
-#define SDHOST_IDINTEN_DU_V  0x00000001U
-#define SDHOST_IDINTEN_DU_S  4
-/** SDHOST_IDINTEN_CES : R/W; bitpos: [5]; default: 0;
- *  Card Error summary Interrupt Enable. When set, it enables the Card Interrupt
- *  summary.
- */
-#define SDHOST_IDINTEN_CES    (BIT(5))
-#define SDHOST_IDINTEN_CES_M  (SDHOST_IDINTEN_CES_V << SDHOST_IDINTEN_CES_S)
-#define SDHOST_IDINTEN_CES_V  0x00000001U
-#define SDHOST_IDINTEN_CES_S  5
-/** SDHOST_IDINTEN_NI : R/W; bitpos: [8]; default: 0;
- *  Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When
- *  reset, a normal interrupt is disabled. This bit enables the following bits:
- *  IDINTEN[0]: Transmit Interrupt;
- *  IDINTEN[1]: Receive Interrupt.
- */
-#define SDHOST_IDINTEN_NI    (BIT(8))
-#define SDHOST_IDINTEN_NI_M  (SDHOST_IDINTEN_NI_V << SDHOST_IDINTEN_NI_S)
-#define SDHOST_IDINTEN_NI_V  0x00000001U
-#define SDHOST_IDINTEN_NI_S  8
-/** SDHOST_IDINTEN_AI : R/W; bitpos: [9]; default: 0;
- *  Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This
- *  bit enables the following bits:
- *  IDINTEN[2]: Fatal Bus Error Interrupt;
- *  IDINTEN[4]: DU Interrupt.
- */
-#define SDHOST_IDINTEN_AI    (BIT(9))
-#define SDHOST_IDINTEN_AI_M  (SDHOST_IDINTEN_AI_V << SDHOST_IDINTEN_AI_S)
-#define SDHOST_IDINTEN_AI_V  0x00000001U
-#define SDHOST_IDINTEN_AI_S  9
-
-/** SDHOST_DSCADDR_REG register
- *  Host descriptor address pointer
- */
-#define SDHOST_DSCADDR_REG (DR_REG_SDHOST_BASE + 0x94)
-/** SDHOST_DSCADDR : RO; bitpos: [31:0]; default: 0;
- *  Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on
- *  reset. This register points to the start address of the current descriptor read by
- *  the IDMAC.
- */
-#define SDHOST_DSCADDR    0xFFFFFFFFU
-#define SDHOST_DSCADDR_M  (SDHOST_DSCADDR_V << SDHOST_DSCADDR_S)
-#define SDHOST_DSCADDR_V  0xFFFFFFFFU
-#define SDHOST_DSCADDR_S  0
-
-/** SDHOST_BUFADDR_REG register
- *  Host buffer address pointer register
- */
-#define SDHOST_BUFADDR_REG (DR_REG_SDHOST_BASE + 0x98)
-/** SDHOST_BUFADDR : RO; bitpos: [31:0]; default: 0;
- *  Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
- *  reset. This register points to the current Data Buffer Address being accessed by
- *  the IDMAC.
- */
-#define SDHOST_BUFADDR    0xFFFFFFFFU
-#define SDHOST_BUFADDR_M  (SDHOST_BUFADDR_V << SDHOST_BUFADDR_S)
-#define SDHOST_BUFADDR_V  0xFFFFFFFFU
-#define SDHOST_BUFADDR_S  0
-
-/** SDHOST_CARDTHRCTL_REG register
- *  Card Threshold Control register
- */
-#define SDHOST_CARDTHRCTL_REG (DR_REG_SDHOST_BASE + 0x100)
-/** SDHOST_CARDRDTHREN_REG : R/W; bitpos: [0]; default: 0;
- *  Card read threshold enable.
- *  1'b0-Card read threshold disabled.
- *  1'b1-Card read threshold enabled.
- */
-#define SDHOST_CARDRDTHREN_REG    (BIT(0))
-#define SDHOST_CARDRDTHREN_REG_M  (SDHOST_CARDRDTHREN_REG_V << SDHOST_CARDRDTHREN_REG_S)
-#define SDHOST_CARDRDTHREN_REG_V  0x00000001U
-#define SDHOST_CARDRDTHREN_REG_S  0
-/** SDHOST_CARDCLRINTEN_REG : R/W; bitpos: [1]; default: 0;
- *  Busy clear interrupt generation:
- *  1'b0-Busy clear interrypt disabled.
- *  1'b1-Busy clear interrypt enabled.
- */
-#define SDHOST_CARDCLRINTEN_REG    (BIT(1))
-#define SDHOST_CARDCLRINTEN_REG_M  (SDHOST_CARDCLRINTEN_REG_V << SDHOST_CARDCLRINTEN_REG_S)
-#define SDHOST_CARDCLRINTEN_REG_V  0x00000001U
-#define SDHOST_CARDCLRINTEN_REG_S  1
-/** SDHOST_CARDWRTHREN_REG : R/W; bitpos: [2]; default: 0;
- *  Applicable when HS400 mode is enabled.
- *  1'b0-Card write Threshold disabled.
- *  1'b1-Card write Threshold enabled.
- */
-#define SDHOST_CARDWRTHREN_REG    (BIT(2))
-#define SDHOST_CARDWRTHREN_REG_M  (SDHOST_CARDWRTHREN_REG_V << SDHOST_CARDWRTHREN_REG_S)
-#define SDHOST_CARDWRTHREN_REG_V  0x00000001U
-#define SDHOST_CARDWRTHREN_REG_S  2
-/** SDHOST_CARDTHRESHOLD_REG : R/W; bitpos: [31:16]; default: 0;
- *  The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG
- *  is set to 1 or SDHOST_CARDRDTHREN_REG set to 1.
- */
-#define SDHOST_CARDTHRESHOLD_REG    0x0000FFFFU
-#define SDHOST_CARDTHRESHOLD_REG_M  (SDHOST_CARDTHRESHOLD_REG_V << SDHOST_CARDTHRESHOLD_REG_S)
-#define SDHOST_CARDTHRESHOLD_REG_V  0x0000FFFFU
-#define SDHOST_CARDTHRESHOLD_REG_S  16
-
-/** SDHOST_EMMCDDR_REG register
- *  eMMC DDR register
- */
-#define SDHOST_EMMCDDR_REG (DR_REG_SDHOST_BASE + 0x10c)
-/** SDHOST_HALFSTARTBIT_REG : R/W; bitpos: [1:0]; default: 0;
- *  Control for start bit detection mechanism duration of start bit.Each bit refers to
- *  one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For
- *  eMMC4.5,start bit can be:
- *  1'b0-Full cycle.
- *  1'b1-less than one full cycle.
- */
-#define SDHOST_HALFSTARTBIT_REG    0x00000003U
-#define SDHOST_HALFSTARTBIT_REG_M  (SDHOST_HALFSTARTBIT_REG_V << SDHOST_HALFSTARTBIT_REG_S)
-#define SDHOST_HALFSTARTBIT_REG_V  0x00000003U
-#define SDHOST_HALFSTARTBIT_REG_S  0
-/** SDHOST_HS400_MODE_REG : R/W; bitpos: [31]; default: 0;
- *  Set 1 to enable HS400 mode.
- */
-#define SDHOST_HS400_MODE_REG    (BIT(31))
-#define SDHOST_HS400_MODE_REG_M  (SDHOST_HS400_MODE_REG_V << SDHOST_HS400_MODE_REG_S)
-#define SDHOST_HS400_MODE_REG_V  0x00000001U
-#define SDHOST_HS400_MODE_REG_S  31
-
-/** SDHOST_ENSHIFT_REG register
- *  Enable Phase Shift register
- */
-#define SDHOST_ENSHIFT_REG (DR_REG_SDHOST_BASE + 0x110)
-/** SDHOST_ENABLE_SHIFT_REG : R/W; bitpos: [3:0]; default: 0;
- *  Control for the amount of phase shift provided on the default enables in the
- *  design.Two bits assigned for each card.
- *  2'b00-Default phase shift.
- *  2'b01-Enables shifted to next immediate positive edge.
- *  2'b10-Enables shifted to next immediate negative edge.
- *  2'b11-Reserved.
- */
-#define SDHOST_ENABLE_SHIFT_REG    0x0000000FU
-#define SDHOST_ENABLE_SHIFT_REG_M  (SDHOST_ENABLE_SHIFT_REG_V << SDHOST_ENABLE_SHIFT_REG_S)
-#define SDHOST_ENABLE_SHIFT_REG_V  0x0000000FU
-#define SDHOST_ENABLE_SHIFT_REG_S  0
-
-/** SDHOST_BUFFIFO_REG register
- *  CPU write and read transmit data by FIFO
- */
-#define SDHOST_BUFFIFO_REG (DR_REG_SDHOST_BASE + 0x200)
-/** SDHOST_BUFFIFO : R/W; bitpos: [31:0]; default: 0;
- *  CPU write and read transmit data by FIFO. This register points to the current Data
- *  FIFO .
- */
-#define SDHOST_BUFFIFO    0xFFFFFFFFU
-#define SDHOST_BUFFIFO_M  (SDHOST_BUFFIFO_V << SDHOST_BUFFIFO_S)
-#define SDHOST_BUFFIFO_V  0xFFFFFFFFU
-#define SDHOST_BUFFIFO_S  0
-
-/** SDHOST_CLK_EDGE_SEL_REG register
- *  SDIO control register.
- */
-#define SDHOST_CLK_EDGE_SEL_REG (DR_REG_SDHOST_BASE + 0x800)
-/** SDHOST_CCLKIN_EDGE_DRV_SEL : R/W; bitpos: [2:0]; default: 0;
- *  It's used to select the clock phase of the output signal from phase 0, phase 90,
- *  phase 180, phase 270.
- */
-#define SDHOST_CCLKIN_EDGE_DRV_SEL    0x00000007U
-#define SDHOST_CCLKIN_EDGE_DRV_SEL_M  (SDHOST_CCLKIN_EDGE_DRV_SEL_V << SDHOST_CCLKIN_EDGE_DRV_SEL_S)
-#define SDHOST_CCLKIN_EDGE_DRV_SEL_V  0x00000007U
-#define SDHOST_CCLKIN_EDGE_DRV_SEL_S  0
-/** SDHOST_CCLKIN_EDGE_SAM_SEL : R/W; bitpos: [5:3]; default: 0;
- *  It's used to select the clock phase of the input signal from phase 0, phase 90,
- *  phase 180, phase 270.
- */
-#define SDHOST_CCLKIN_EDGE_SAM_SEL    0x00000007U
-#define SDHOST_CCLKIN_EDGE_SAM_SEL_M  (SDHOST_CCLKIN_EDGE_SAM_SEL_V << SDHOST_CCLKIN_EDGE_SAM_SEL_S)
-#define SDHOST_CCLKIN_EDGE_SAM_SEL_V  0x00000007U
-#define SDHOST_CCLKIN_EDGE_SAM_SEL_S  3
-/** SDHOST_CCLKIN_EDGE_SLF_SEL : R/W; bitpos: [8:6]; default: 0;
- *  It's used to select the clock phase of the internal signal from phase 0, phase 90,
- *  phase 180, phase 270.
- */
-#define SDHOST_CCLKIN_EDGE_SLF_SEL    0x00000007U
-#define SDHOST_CCLKIN_EDGE_SLF_SEL_M  (SDHOST_CCLKIN_EDGE_SLF_SEL_V << SDHOST_CCLKIN_EDGE_SLF_SEL_S)
-#define SDHOST_CCLKIN_EDGE_SLF_SEL_V  0x00000007U
-#define SDHOST_CCLKIN_EDGE_SLF_SEL_S  6
-/** SDHOST_CCLLKIN_EDGE_H : R/W; bitpos: [12:9]; default: 1;
- *  The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.
- */
-#define SDHOST_CCLLKIN_EDGE_H    0x0000000FU
-#define SDHOST_CCLLKIN_EDGE_H_M  (SDHOST_CCLLKIN_EDGE_H_V << SDHOST_CCLLKIN_EDGE_H_S)
-#define SDHOST_CCLLKIN_EDGE_H_V  0x0000000FU
-#define SDHOST_CCLLKIN_EDGE_H_S  9
-/** SDHOST_CCLLKIN_EDGE_L : R/W; bitpos: [16:13]; default: 0;
- *  The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.
- */
-#define SDHOST_CCLLKIN_EDGE_L    0x0000000FU
-#define SDHOST_CCLLKIN_EDGE_L_M  (SDHOST_CCLLKIN_EDGE_L_V << SDHOST_CCLLKIN_EDGE_L_S)
-#define SDHOST_CCLLKIN_EDGE_L_V  0x0000000FU
-#define SDHOST_CCLLKIN_EDGE_L_S  13
-/** SDHOST_CCLLKIN_EDGE_N : R/W; bitpos: [20:17]; default: 1;
- *  The clock division of cclk_in.
- */
-#define SDHOST_CCLLKIN_EDGE_N    0x0000000FU
-#define SDHOST_CCLLKIN_EDGE_N_M  (SDHOST_CCLLKIN_EDGE_N_V << SDHOST_CCLLKIN_EDGE_N_S)
-#define SDHOST_CCLLKIN_EDGE_N_V  0x0000000FU
-#define SDHOST_CCLLKIN_EDGE_N_S  17
-/** SDHOST_ESDIO_MODE : R/W; bitpos: [21]; default: 0;
- *  Enable esdio mode.
- */
-#define SDHOST_ESDIO_MODE    (BIT(21))
-#define SDHOST_ESDIO_MODE_M  (SDHOST_ESDIO_MODE_V << SDHOST_ESDIO_MODE_S)
-#define SDHOST_ESDIO_MODE_V  0x00000001U
-#define SDHOST_ESDIO_MODE_S  21
-/** SDHOST_ESD_MODE : R/W; bitpos: [22]; default: 0;
- *  Enable esd mode.
- */
-#define SDHOST_ESD_MODE    (BIT(22))
-#define SDHOST_ESD_MODE_M  (SDHOST_ESD_MODE_V << SDHOST_ESD_MODE_S)
-#define SDHOST_ESD_MODE_V  0x00000001U
-#define SDHOST_ESD_MODE_S  22
-/** SDHOST_CCLK_EN : R/W; bitpos: [23]; default: 1;
- *  Sdio clock enable.
- */
-#define SDHOST_CCLK_EN    (BIT(23))
-#define SDHOST_CCLK_EN_M  (SDHOST_CCLK_EN_V << SDHOST_CCLK_EN_S)
-#define SDHOST_CCLK_EN_V  0x00000001U
-#define SDHOST_CCLK_EN_S  23
-/** SDHOST_ULTRA_HIGH_SPEED_MODE : R/W; bitpos: [24]; default: 0;
- *  Enable ultra high speed mode, use dll to generate clk.
- */
-#define SDHOST_ULTRA_HIGH_SPEED_MODE    (BIT(24))
-#define SDHOST_ULTRA_HIGH_SPEED_MODE_M  (SDHOST_ULTRA_HIGH_SPEED_MODE_V << SDHOST_ULTRA_HIGH_SPEED_MODE_S)
-#define SDHOST_ULTRA_HIGH_SPEED_MODE_V  0x00000001U
-#define SDHOST_ULTRA_HIGH_SPEED_MODE_S  24
-
-/** SDHOST_RAW_INTS_REG register
- *  SDIO raw ints register.
- */
-#define SDHOST_RAW_INTS_REG (DR_REG_SDHOST_BASE + 0x804)
-/** SDHOST_RAW_INTS : RO; bitpos: [31:0]; default: 0;
- *  It indicates raw ints.
- */
-#define SDHOST_RAW_INTS    0xFFFFFFFFU
-#define SDHOST_RAW_INTS_M  (SDHOST_RAW_INTS_V << SDHOST_RAW_INTS_S)
-#define SDHOST_RAW_INTS_V  0xFFFFFFFFU
-#define SDHOST_RAW_INTS_S  0
-
-/** SDHOST_DLL_CLK_CONF_REG register
- *  SDIO DLL clock control register.
- */
-#define SDHOST_DLL_CLK_CONF_REG (DR_REG_SDHOST_BASE + 0x808)
-/** SDHOST_DLL_CCLK_IN_SLF_EN : R/W; bitpos: [0]; default: 0;
- *  Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
- */
-#define SDHOST_DLL_CCLK_IN_SLF_EN    (BIT(0))
-#define SDHOST_DLL_CCLK_IN_SLF_EN_M  (SDHOST_DLL_CCLK_IN_SLF_EN_V << SDHOST_DLL_CCLK_IN_SLF_EN_S)
-#define SDHOST_DLL_CCLK_IN_SLF_EN_V  0x00000001U
-#define SDHOST_DLL_CCLK_IN_SLF_EN_S  0
-/** SDHOST_DLL_CCLK_IN_DRV_EN : R/W; bitpos: [1]; default: 0;
- *  Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
- */
-#define SDHOST_DLL_CCLK_IN_DRV_EN    (BIT(1))
-#define SDHOST_DLL_CCLK_IN_DRV_EN_M  (SDHOST_DLL_CCLK_IN_DRV_EN_V << SDHOST_DLL_CCLK_IN_DRV_EN_S)
-#define SDHOST_DLL_CCLK_IN_DRV_EN_V  0x00000001U
-#define SDHOST_DLL_CCLK_IN_DRV_EN_S  1
-/** SDHOST_DLL_CCLK_IN_SAM_EN : R/W; bitpos: [2]; default: 0;
- *  Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
- */
-#define SDHOST_DLL_CCLK_IN_SAM_EN    (BIT(2))
-#define SDHOST_DLL_CCLK_IN_SAM_EN_M  (SDHOST_DLL_CCLK_IN_SAM_EN_V << SDHOST_DLL_CCLK_IN_SAM_EN_S)
-#define SDHOST_DLL_CCLK_IN_SAM_EN_V  0x00000001U
-#define SDHOST_DLL_CCLK_IN_SAM_EN_S  2
-/** SDHOST_DLL_CCLK_IN_SLF_PHASE : R/W; bitpos: [8:3]; default: 0;
- *  It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
- */
-#define SDHOST_DLL_CCLK_IN_SLF_PHASE    0x0000003FU
-#define SDHOST_DLL_CCLK_IN_SLF_PHASE_M  (SDHOST_DLL_CCLK_IN_SLF_PHASE_V << SDHOST_DLL_CCLK_IN_SLF_PHASE_S)
-#define SDHOST_DLL_CCLK_IN_SLF_PHASE_V  0x0000003FU
-#define SDHOST_DLL_CCLK_IN_SLF_PHASE_S  3
-/** SDHOST_DLL_CCLK_IN_DRV_PHASE : R/W; bitpos: [14:9]; default: 0;
- *  It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
- */
-#define SDHOST_DLL_CCLK_IN_DRV_PHASE    0x0000003FU
-#define SDHOST_DLL_CCLK_IN_DRV_PHASE_M  (SDHOST_DLL_CCLK_IN_DRV_PHASE_V << SDHOST_DLL_CCLK_IN_DRV_PHASE_S)
-#define SDHOST_DLL_CCLK_IN_DRV_PHASE_V  0x0000003FU
-#define SDHOST_DLL_CCLK_IN_DRV_PHASE_S  9
-/** SDHOST_DLL_CCLK_IN_SAM_PHASE : R/W; bitpos: [20:15]; default: 0;
- *  It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
- */
-#define SDHOST_DLL_CCLK_IN_SAM_PHASE    0x0000003FU
-#define SDHOST_DLL_CCLK_IN_SAM_PHASE_M  (SDHOST_DLL_CCLK_IN_SAM_PHASE_V << SDHOST_DLL_CCLK_IN_SAM_PHASE_S)
-#define SDHOST_DLL_CCLK_IN_SAM_PHASE_V  0x0000003FU
-#define SDHOST_DLL_CCLK_IN_SAM_PHASE_S  15
-
-/** SDHOST_DLL_CONF_REG register
- *  SDIO DLL configuration register.
- */
-#define SDHOST_DLL_CONF_REG (DR_REG_SDHOST_BASE + 0x80c)
-/** SDHOST_DLL_CAL_STOP : R/W; bitpos: [0]; default: 0;
- *  Set 1 to stop calibration.
- */
-#define SDHOST_DLL_CAL_STOP    (BIT(0))
-#define SDHOST_DLL_CAL_STOP_M  (SDHOST_DLL_CAL_STOP_V << SDHOST_DLL_CAL_STOP_S)
-#define SDHOST_DLL_CAL_STOP_V  0x00000001U
-#define SDHOST_DLL_CAL_STOP_S  0
-/** SDHOST_DLL_CAL_END : RO; bitpos: [1]; default: 0;
- *  1 means calibration finished.
- */
-#define SDHOST_DLL_CAL_END    (BIT(1))
-#define SDHOST_DLL_CAL_END_M  (SDHOST_DLL_CAL_END_V << SDHOST_DLL_CAL_END_S)
-#define SDHOST_DLL_CAL_END_V  0x00000001U
-#define SDHOST_DLL_CAL_END_S  1
-
-
-#define SDMMC_INTMASK_IO_SLOT1  BIT(17)
-#define SDMMC_INTMASK_IO_SLOT0  BIT(16)
-#define SDMMC_INTMASK_EBE       BIT(15)
-#define SDMMC_INTMASK_ACD       BIT(14)
-#define SDMMC_INTMASK_SBE       BIT(13)
-#define SDMMC_INTMASK_HLE       BIT(12)
-#define SDMMC_INTMASK_FRUN      BIT(11)
-#define SDMMC_INTMASK_HTO       BIT(10)
-#define SDMMC_INTMASK_DTO       BIT(9)
-#define SDMMC_INTMASK_RTO       BIT(8)
-#define SDMMC_INTMASK_DCRC      BIT(7)
-#define SDMMC_INTMASK_RCRC      BIT(6)
-#define SDMMC_INTMASK_RXDR      BIT(5)
-#define SDMMC_INTMASK_TXDR      BIT(4)
-#define SDMMC_INTMASK_DATA_OVER BIT(3)
-#define SDMMC_INTMASK_CMD_DONE  BIT(2)
-#define SDMMC_INTMASK_RESP_ERR  BIT(1)
-#define SDMMC_INTMASK_CD        BIT(0)
-
-#define SDMMC_IDMAC_INTMASK_AI  BIT(9)
-#define SDMMC_IDMAC_INTMASK_NI  BIT(8)
-#define SDMMC_IDMAC_INTMASK_CES BIT(5)
-#define SDMMC_IDMAC_INTMASK_DU  BIT(4)
-#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
-#define SDMMC_IDMAC_INTMASK_RI  BIT(1)
-#define SDMMC_IDMAC_INTMASK_TI  BIT(0)
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/sha_reg.h b/components/soc/esp32p4/include/soc/sha_reg.h
deleted file mode 100644
index 888da914b30..00000000000
--- a/components/soc/esp32p4/include/soc/sha_reg.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SHA_MODE_REG register
- *  Initial configuration register.
- */
-#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
-/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
- *  Sha mode.
- */
-#define SHA_MODE    0x00000007U
-#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
-#define SHA_MODE_V  0x00000007U
-#define SHA_MODE_S  0
-
-/** SHA_T_STRING_REG register
- *  SHA 512/t configuration register 0.
- */
-#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
-/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
- *  Sha t_string (used if and only if mode == SHA_512/t).
- */
-#define SHA_T_STRING    0xFFFFFFFFU
-#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
-#define SHA_T_STRING_V  0xFFFFFFFFU
-#define SHA_T_STRING_S  0
-
-/** SHA_T_LENGTH_REG register
- *  SHA 512/t configuration register 1.
- */
-#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
-/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
- *  Sha t_length (used if and only if mode == SHA_512/t).
- */
-#define SHA_T_LENGTH    0x0000003FU
-#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
-#define SHA_T_LENGTH_V  0x0000003FU
-#define SHA_T_LENGTH_S  0
-
-/** SHA_DMA_BLOCK_NUM_REG register
- *  DMA configuration register 0.
- */
-#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
-/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
- *  Dma-sha block number.
- */
-#define SHA_DMA_BLOCK_NUM    0x0000003FU
-#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
-#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
-#define SHA_DMA_BLOCK_NUM_S  0
-
-/** SHA_START_REG register
- *  Typical SHA configuration register 0.
- */
-#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
-/** SHA_START : RO; bitpos: [31:1]; default: 0;
- *  Reserved.
- */
-#define SHA_START    0x7FFFFFFFU
-#define SHA_START_M  (SHA_START_V << SHA_START_S)
-#define SHA_START_V  0x7FFFFFFFU
-#define SHA_START_S  1
-
-/** SHA_CONTINUE_REG register
- *  Typical SHA configuration register 1.
- */
-#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
-/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
- *  Reserved.
- */
-#define SHA_CONTINUE    0x7FFFFFFFU
-#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
-#define SHA_CONTINUE_V  0x7FFFFFFFU
-#define SHA_CONTINUE_S  1
-
-/** SHA_BUSY_REG register
- *  Busy register.
- */
-#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
-/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
- *  Sha busy state. 1'b0: idle. 1'b1: busy.
- */
-#define SHA_BUSY_STATE    (BIT(0))
-#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
-#define SHA_BUSY_STATE_V  0x00000001U
-#define SHA_BUSY_STATE_S  0
-
-/** SHA_DMA_START_REG register
- *  DMA configuration register 1.
- */
-#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
-/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
- *  Start dma-sha.
- */
-#define SHA_DMA_START    (BIT(0))
-#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
-#define SHA_DMA_START_V  0x00000001U
-#define SHA_DMA_START_S  0
-
-/** SHA_DMA_CONTINUE_REG register
- *  DMA configuration register 2.
- */
-#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
-/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
- *  Continue dma-sha.
- */
-#define SHA_DMA_CONTINUE    (BIT(0))
-#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
-#define SHA_DMA_CONTINUE_V  0x00000001U
-#define SHA_DMA_CONTINUE_S  0
-
-/** SHA_CLEAR_IRQ_REG register
- *  Interrupt clear register.
- */
-#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
-/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
- *  Clear sha interrupt.
- */
-#define SHA_CLEAR_INTERRUPT    (BIT(0))
-#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
-#define SHA_CLEAR_INTERRUPT_V  0x00000001U
-#define SHA_CLEAR_INTERRUPT_S  0
-
-/** SHA_IRQ_ENA_REG register
- *  Interrupt enable register.
- */
-#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
-/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
- *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
- */
-#define SHA_INTERRUPT_ENA    (BIT(0))
-#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
-#define SHA_INTERRUPT_ENA_V  0x00000001U
-#define SHA_INTERRUPT_ENA_S  0
-
-/** SHA_DATE_REG register
- *  Date register.
- */
-#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
-/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
- *  Sha date information/ sha version information.
- */
-#define SHA_DATE    0x3FFFFFFFU
-#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
-#define SHA_DATE_V  0x3FFFFFFFU
-#define SHA_DATE_S  0
-
-/** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
- */
-#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
-#define SHA_H_MEM_SIZE_BYTES 64
-
-/** SHA_M_MEM register
- *  Sha M memory which contains message.
- */
-#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
-#define SHA_M_MEM_SIZE_BYTES 64
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
index baf879c9e5e..e8e79a9d07d 100644
--- a/components/soc/esp32p4/include/soc/soc.h
+++ b/components/soc/esp32p4/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index d7dcd4200f0..cfc9dd1dd4c 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -29,9 +29,9 @@
 #define SOC_GPTIMER_SUPPORTED           1
 #define SOC_PCNT_SUPPORTED              1
 #define SOC_LCDCAM_SUPPORTED            1
-#define SOC_LCDCAM_CAM_SUPPORTED        1
+#define SOC_LCDCAM_CAM_SUPPORTED        1 // support the camera driver based on the LCD_CAM peripheral
 #define SOC_LCDCAM_I80_LCD_SUPPORTED    1 // support the Intel 8080 bus driver based on the LCD_CAM peripheral
-// #define SOC_LCDCAM_RGB_LCD_SUPPORTED    1 // TODO: IDF-7465
+#define SOC_LCDCAM_RGB_LCD_SUPPORTED    1 // support the RGB LCD driver based on the LCD_CAM peripheral
 #define SOC_MIPI_CSI_SUPPORTED          1
 #define SOC_MIPI_DSI_SUPPORTED          1
 #define SOC_MCPWM_SUPPORTED             1
@@ -83,6 +83,7 @@
 #define SOC_LP_I2S_SUPPORTED            1
 #define SOC_LP_SPI_SUPPORTED            1
 #define SOC_LP_ADC_SUPPORTED            1
+#define SOC_LP_VAD_SUPPORTED            1
 #define SOC_SPIRAM_SUPPORTED            1
 #define SOC_PSRAM_DMA_CAPABLE           1
 #define SOC_SDMMC_HOST_SUPPORTED        1
@@ -221,6 +222,7 @@
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
 #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
+#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1   // Support sleep retention
 
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-P4 has 1 GPIO peripheral
@@ -301,10 +303,11 @@
 #define SOC_I2C_SUPPORT_RTC         (1)
 #define SOC_I2C_SUPPORT_10BIT_ADDR  (1)
 #define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
 #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
 #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
 
-// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9353
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
 
 /*-------------------------- LP_I2C CAPS -------------------------------------*/
 // ESP32-P4 has 1 LP_I2C
@@ -340,6 +343,7 @@
 #define SOC_ISP_DVP_SUPPORTED                    1
 #define SOC_ISP_SHARPEN_SUPPORTED                1
 #define SOC_ISP_COLOR_SUPPORTED                  1
+#define SOC_ISP_LSC_SUPPORTED                    1
 #define SOC_ISP_SHARE_CSI_BRG                    1
 
 #define SOC_ISP_NUMS                             1U
@@ -369,16 +373,21 @@
 #define SOC_ISP_HIST_BLOCK_Y_NUMS                5
 #define SOC_ISP_HIST_SEGMENT_NUMS                16
 #define SOC_ISP_HIST_INTERVAL_NUMS               15
+#define SOC_ISP_LSC_GRAD_RATIO_INT_BITS          2
+#define SOC_ISP_LSC_GRAD_RATIO_DEC_BITS          8
+#define SOC_ISP_LSC_GRAD_RATIO_RES_BITS          22
 
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK      (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK         (1)
+#define SOC_LEDC_TIMER_NUM                  (4)
 #define SOC_LEDC_CHANNEL_NUM                (8)
 #define SOC_LEDC_TIMER_BIT_WIDTH            (20)
 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
 #define SOC_LEDC_SUPPORT_FADE_STOP          (1)
 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH      (10)
+#define SOC_LEDC_SUPPORT_SLEEP_RETENTION    (1)
 
 /*-------------------------- MMU CAPS ----------------------------------------*/
 #define SOC_MMU_PERIPH_NUM                    (2U)
@@ -400,6 +409,7 @@
 #define SOC_PCNT_THRES_POINT_PER_UNIT         2
 #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
 #define SOC_PCNT_SUPPORT_CLEAR_SIGNAL         1  /*!< Support clear signal input */
+// #define SOC_PCNT_SUPPORT_SLEEP_RETENTION      1  // TODO: IDF-9907 Waiting for expansion of module ID /*!< The sleep retention feature can help back up PCNT registers before sleep */
 
 /*--------------------------- RMT CAPS ---------------------------------------*/
 #define SOC_RMT_GROUPS                        1U /*!< One RMT group */
@@ -422,11 +432,12 @@
 /*-------------------------- LCD CAPS ----------------------------------------*/
 /* I80 bus and RGB timing generator can't work at the same time in the LCD_CAM peripheral */
 #define SOC_LCD_I80_SUPPORTED              1  /*!< support intel 8080 driver */
+#define SOC_LCD_RGB_SUPPORTED              1  /*!< RGB LCD is supported */
 #define SOC_LCDCAM_I80_NUM_BUSES           1U /*!< LCD_CAM peripheral provides one LCD Intel 8080 bus */
 #define SOC_LCDCAM_I80_BUS_WIDTH           24 /*!< Intel 8080 bus max data width */
 #define SOC_LCDCAM_RGB_NUM_PANELS          1U /*!< Support one RGB LCD panel */
-// #define SOC_LCD_RGB_DATA_WIDTH          24 /*!< Number of LCD data lines */
-// #define SOC_LCD_SUPPORT_RGB_YUV_CONV    1  /*!< Support color format conversion between RGB and YUV */
+#define SOC_LCDCAM_RGB_DATA_WIDTH          24 /*!< Number of LCD data lines */
+#define SOC_LCD_SUPPORT_RGB_YUV_CONV       1  /*!< Support color format conversion between RGB and YUV */
 
 /*-------------------------- MCPWM CAPS --------------------------------------*/
 #define SOC_MCPWM_GROUPS                     (2U)   ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
@@ -444,10 +455,18 @@
 #define SOC_MCPWM_SUPPORT_ETM                (1)    ///< Support ETM (Event Task Matrix)
 #define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR   (1)    ///< Support event comparator (based on ETM)
 #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP     (1)    ///< Capture timer shares clock with other PWM timers
+// #define SOC_MCPWM_SUPPORT_SLEEP_RETENTION    (1)   // TODO: IDF-9928 Waiting for expansion of module ID  ///< Support back up registers before sleep
 
-/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
+/*-------------------------- USB CAPS ----------------------------------------*/
+// USB Serial JTAG Caps
 // #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP     (1)     /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
 
+// USB OTG Caps
+#define SOC_USB_OTG_PERIPH_NUM          (2U)
+
+// USB PHY Caps
+#define SOC_USB_UTMI_PHY_NUM            (1U)
+
 /*-------------------------- PARLIO CAPS --------------------------------------*/
 #define SOC_PARLIO_GROUPS                    1U  /*!< Number of parallel IO peripherals */
 #define SOC_PARLIO_TX_UNITS_PER_GROUP        1U  /*!< number of TX units in each group */
@@ -459,6 +478,7 @@
 #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT     1  /*!< Support output RX clock to a GPIO */
 #define SOC_PARLIO_TRANS_BIT_ALIGN           1  /*!< Support bit alignment in transaction */
 #define SOC_PARLIO_TX_SIZE_BY_DMA            1   /*!< Transaction length is controlled by DMA instead of indicated by register */
+#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION   1   /*!< Support back up registers before sleep */
 
 /*--------------------------- MPI CAPS ---------------------------------------*/
 #define SOC_MPI_MEM_BLOCKS_NUM (4)
@@ -481,6 +501,7 @@
 #define SOC_SDMMC_DELAY_PHASE_NUM    4
 #define SOC_SDMMC_IO_POWER_EXTERNAL  1    ///< SDMMC IO power controlled by external power supply
 #define SOC_SDMMC_PSRAM_DMA_CAPABLE  1    ///< SDMMC peripheral can do DMA transfer to/from PSRAM
+#define SOC_SDMMC_UHS_I_SUPPORTED    1
 
 // TODO: IDF-5353 (Copy from esp32c3, need check)
 /*--------------------------- SHA CAPS ---------------------------------------*/
@@ -525,6 +546,7 @@
 #define SOC_SPI_MAX_CS_NUM              6
 #define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
 
+#define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS     1
 #define SOC_SPI_SUPPORT_DDRCLK              1
@@ -610,11 +632,12 @@
 #define SOC_TOUCH_SAMPLE_CFG_NUM                    (3)     /*!< The sample configurations number in total, each sampler can be used to sample on one frequency */
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
-#define SOC_TWAI_CONTROLLER_NUM         3
-#define SOC_TWAI_CLK_SUPPORT_XTAL       1
-#define SOC_TWAI_BRP_MIN                2
-#define SOC_TWAI_BRP_MAX                32768
-#define SOC_TWAI_SUPPORTS_RX_STATUS     1
+#define SOC_TWAI_CONTROLLER_NUM             3
+#define SOC_TWAI_CLK_SUPPORT_XTAL           1
+#define SOC_TWAI_BRP_MIN                    2
+#define SOC_TWAI_BRP_MAX                    32768
+#define SOC_TWAI_SUPPORTS_RX_STATUS         1
+#define SOC_TWAI_SUPPORT_SLEEP_RETENTION    1
 
 /*-------------------------- eFuse CAPS----------------------------*/
 #define SOC_EFUSE_DIS_PAD_JTAG 1
@@ -661,6 +684,9 @@
 // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
 #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND   (1)
 
+/*-------------------------- LP_VAD CAPS -------------------------------------*/
+#define SOC_LP_I2S_SUPPORT_VAD           (1)
+
 // TODO: IDF-5679 (Copy from esp32c3, need check)
 /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
 #define SOC_COEX_HW_PTI                 (1)
@@ -697,37 +723,42 @@
 #define SOC_CPU_IN_TOP_DOMAIN           (1)
 
 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE  (1)
+#define SOC_SLEEP_SYSTIMER_STALL_WORKAROUND 1    //TODO IDF-11381: replace with all xtal field clk gate control
+#define SOC_SLEEP_TGWDT_STOP_WORKAROUND     1    //TODO IDF-11381: replace with all xtal field clk gate control
 
 /*-------------------------- PSRAM CAPS ----------------------------*/
 #define SOC_PSRAM_VDD_POWER_MPLL    (1)
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
-#define SOC_MODEM_CLOCK_IS_INDEPENDENT            (0)
 
 #define SOC_CLK_APLL_SUPPORTED                    (1)     /*!< Support Audio PLL */
 #define SOC_CLK_MPLL_SUPPORTED                    (1)     /*!< Support MSPI PLL */
+#define SOC_CLK_SDIO_PLL_SUPPORTED                (1)     /*!< Support SDIO PLL */
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 #define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
 
 #define SOC_CLK_LP_FAST_SUPPORT_LP_PLL            (1)      /*!< Support LP_PLL clock as the LP_FAST clock source */
 #define SOC_CLK_LP_FAST_SUPPORT_XTAL              (1)     /*!< Support XTAL clock as the LP_FAST clock source */
 
-
 #define SOC_PERIPH_CLK_CTRL_SHARED                (1)     /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT                (1)
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                  (1)
 #define SOC_TSENS_IS_INDEPENDENT_FROM_ADC                    (1)  /*!< Temperature sensor is a separate module, not share regs with ADC */
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM                   (1)
+// temperature sensor on esp32p4 in under low power domain.
+#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION       (1)
 
 /*-------------------------- Memory CAPS --------------------------*/
 #define SOC_MEM_TCM_SUPPORTED                      (1)
 #define SOC_MEM_NON_CONTIGUOUS_SRAM                (1)
 #define SOC_ASYNCHRONOUS_BUS_ERROR_MODE            (1)
 /*--------------------------- EMAC --------------------------------*/
-#define SOC_EMAC_IEEE_1588_SUPPORT                 (1)      /*!< EMAC Supports IEEE1588 time stamping */
+#define SOC_EMAC_IEEE1588V2_SUPPORTED              (1)      /*!< EMAC Supports IEEE1588v2 time stamping */
 #define SOC_EMAC_USE_MULTI_IO_MUX                  (1)      /*!< Multiple GPIO pad options exist to connect EMAC signal via IO_MUX */
 #define SOC_EMAC_MII_USE_GPIO_MATRIX               (1)      /*!< EMAC MII signals are connected to GPIO pads via GPIO Matrix */
 
@@ -744,3 +775,4 @@
 /*------------------------------------- ULP CAPS -------------------------------------*/
 #define SOC_LP_CORE_SUPPORT_ETM               (1) /*!< LP Core supports ETM */
 #define SOC_LP_CORE_SUPPORT_LP_ADC            (1) /*!< LP ADC can be accessed from the LP-Core */
+#define SOC_LP_CORE_SUPPORT_LP_VAD            (1) /*!< LP VAD can be accessed from the LP-Core */
diff --git a/components/soc/esp32p4/include/soc/spi_reg.h b/components/soc/esp32p4/include/soc/spi_reg.h
deleted file mode 100644
index 61a1858b096..00000000000
--- a/components/soc/esp32p4/include/soc/spi_reg.h
+++ /dev/null
@@ -1,2152 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SPI_CMD_REG register
- *  Command control register
- */
-#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
-/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_CONF_BITLEN    0x0003FFFFU
-#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
-#define SPI_CONF_BITLEN_V  0x0003FFFFU
-#define SPI_CONF_BITLEN_S  0
-/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
- *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
- *  clock domain, which is only used in SPI master mode.
- */
-#define SPI_UPDATE    (BIT(23))
-#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
-#define SPI_UPDATE_V  0x00000001U
-#define SPI_UPDATE_S  23
-/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
- *  User define command enable.  An operation will be triggered when the bit is set.
- *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
- *  changed by CONF_buf.
- */
-#define SPI_USR    (BIT(24))
-#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
-#define SPI_USR_V  0x00000001U
-#define SPI_USR_S  24
-
-/** SPI_ADDR_REG register
- *  Address value register
- */
-#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
-/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
- *  Address to slave. Can be configured in CONF state.
- */
-#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
-#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
-#define SPI_USR_ADDR_VALUE_S  0
-
-/** SPI_CTRL_REG register
- *  SPI control register
- */
-#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
-/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
- *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
- *  the FSPI bus signals are output. Can be configured in CONF state.
- */
-#define SPI_DUMMY_OUT    (BIT(3))
-#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
-#define SPI_DUMMY_OUT_V  0x00000001U
-#define SPI_DUMMY_OUT_S  3
-/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
- *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_DUAL    (BIT(5))
-#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
-#define SPI_FADDR_DUAL_V  0x00000001U
-#define SPI_FADDR_DUAL_S  5
-/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
- *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FADDR_QUAD    (BIT(6))
-#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
-#define SPI_FADDR_QUAD_V  0x00000001U
-#define SPI_FADDR_QUAD_S  6
-/** SPI_FADDR_OCT : R/W; bitpos: [7]; default: 0;
- *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-//this field is only for GPSPI2
-#define SPI_FADDR_OCT    (BIT(7))
-#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
-#define SPI_FADDR_OCT_V  0x00000001U
-#define SPI_FADDR_OCT_S  7
-/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
- *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_DUAL    (BIT(8))
-#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
-#define SPI_FCMD_DUAL_V  0x00000001U
-#define SPI_FCMD_DUAL_S  8
-/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
- *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-#define SPI_FCMD_QUAD    (BIT(9))
-#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
-#define SPI_FCMD_QUAD_V  0x00000001U
-#define SPI_FCMD_QUAD_S  9
-/** SPI_FCMD_OCT : R/W; bitpos: [10]; default: 0;
- *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
- *  state.
- */
-//this field is only for GPSPI2
-#define SPI_FCMD_OCT    (BIT(10))
-#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
-#define SPI_FCMD_OCT_V  0x00000001U
-#define SPI_FCMD_OCT_S  10
-/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
- *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_DUAL    (BIT(14))
-#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
-#define SPI_FREAD_DUAL_V  0x00000001U
-#define SPI_FREAD_DUAL_S  14
-/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
- *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
- *  be configured in CONF state.
- */
-#define SPI_FREAD_QUAD    (BIT(15))
-#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
-#define SPI_FREAD_QUAD_V  0x00000001U
-#define SPI_FREAD_QUAD_S  15
-/** SPI_FREAD_OCT : R/W; bitpos: [16]; default: 0;
- *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
- *  be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_FREAD_OCT    (BIT(16))
-#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
-#define SPI_FREAD_OCT_V  0x00000001U
-#define SPI_FREAD_OCT_S  16
-/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
- *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
- *  CONF state.
- */
-#define SPI_Q_POL    (BIT(18))
-#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
-#define SPI_Q_POL_V  0x00000001U
-#define SPI_Q_POL_S  18
-/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
- *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
- *  CONF state.
- */
-#define SPI_D_POL    (BIT(19))
-#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
-#define SPI_D_POL_V  0x00000001U
-#define SPI_D_POL_S  19
-/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
- *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
- *  configured in CONF state.
- */
-#define SPI_HOLD_POL    (BIT(20))
-#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
-#define SPI_HOLD_POL_V  0x00000001U
-#define SPI_HOLD_POL_S  20
-/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
- *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
- *  be configured in CONF state.
- */
-#define SPI_WP_POL    (BIT(21))
-#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
-#define SPI_WP_POL_V  0x00000001U
-#define SPI_WP_POL_S  21
-/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
- *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
- *  state.
- */
-#define SPI_RD_BIT_ORDER    0x00000003U
-#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
-#define SPI_RD_BIT_ORDER_V  0x00000003U
-#define SPI_RD_BIT_ORDER_S  23
-/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
- *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
- *  configured in CONF state.
- */
-#define SPI_WR_BIT_ORDER    0x00000003U
-#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
-#define SPI_WR_BIT_ORDER_V  0x00000003U
-#define SPI_WR_BIT_ORDER_S  25
-
-/** SPI_CLOCK_REG register
- *  SPI clock control register
- */
-#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
-/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
- *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
- *  0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_L    0x0000003FU
-#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
-#define SPI_CLKCNT_L_V  0x0000003FU
-#define SPI_CLKCNT_L_S  0
-/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
- *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
- *  must be 0. Can be configured in CONF state.
- */
-#define SPI_CLKCNT_H    0x0000003FU
-#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
-#define SPI_CLKCNT_H_V  0x0000003FU
-#define SPI_CLKCNT_H_S  6
-/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
- *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
- *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
- */
-#define SPI_CLKCNT_N    0x0000003FU
-#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
-#define SPI_CLKCNT_N_V  0x0000003FU
-#define SPI_CLKCNT_N_S  12
-/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
- *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
- */
-#define SPI_CLKDIV_PRE    0x0000000FU
-#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
-#define SPI_CLKDIV_PRE_V  0x0000000FU
-#define SPI_CLKDIV_PRE_S  18
-/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
- *  clock. Can be configured in CONF state.
- */
-#define SPI_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
-#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
-#define SPI_CLK_EQU_SYSCLK_S  31
-
-/** SPI_USER_REG register
- *  SPI USER control register
- */
-#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
-/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
- *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUTDIN    (BIT(0))
-#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
-#define SPI_DOUTDIN_V  0x00000001U
-#define SPI_DOUTDIN_S  0
-/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
- *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
- *  Can be configured in CONF state.
- */
-#define SPI_QPI_MODE    (BIT(3))
-#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
-#define SPI_QPI_MODE_V  0x00000001U
-#define SPI_QPI_MODE_S  3
-/** SPI_OPI_MODE : R/W; bitpos: [4]; default: 0;
- *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
- *  Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_OPI_MODE    (BIT(4))
-#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
-#define SPI_OPI_MODE_V  0x00000001U
-#define SPI_OPI_MODE_S  4
-/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
- *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
- *  spi_ck_i. 1:tsck = !spi_ck_i.
- */
-#define SPI_TSCK_I_EDGE    (BIT(5))
-#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
-#define SPI_TSCK_I_EDGE_V  0x00000001U
-#define SPI_TSCK_I_EDGE_S  5
-/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
- *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_CS_HOLD    (BIT(6))
-#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
-#define SPI_CS_HOLD_V  0x00000001U
-#define SPI_CS_HOLD_S  6
-/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
- *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
- *  configured in CONF state.
- */
-#define SPI_CS_SETUP    (BIT(7))
-#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
-#define SPI_CS_SETUP_V  0x00000001U
-#define SPI_CS_SETUP_S  7
-/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
- *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
- *  !spi_ck_i. 1:rsck = spi_ck_i.
- */
-#define SPI_RSCK_I_EDGE    (BIT(8))
-#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
-#define SPI_RSCK_I_EDGE_V  0x00000001U
-#define SPI_RSCK_I_EDGE_S  8
-/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
- *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
- *  be configured in CONF state.
- */
-#define SPI_CK_OUT_EDGE    (BIT(9))
-#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
-#define SPI_CK_OUT_EDGE_V  0x00000001U
-#define SPI_CK_OUT_EDGE_S  9
-/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
- *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_DUAL    (BIT(12))
-#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
-#define SPI_FWRITE_DUAL_V  0x00000001U
-#define SPI_FWRITE_DUAL_S  12
-/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
- *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
- *  state.
- */
-#define SPI_FWRITE_QUAD    (BIT(13))
-#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
-#define SPI_FWRITE_QUAD_V  0x00000001U
-#define SPI_FWRITE_QUAD_S  13
-/** SPI_FWRITE_OCT : R/W; bitpos: [14]; default: 0;
- *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
- *  state.
- */
-//this field is only for GPSPI2
-#define SPI_FWRITE_OCT    (BIT(14))
-#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
-#define SPI_FWRITE_OCT_V  0x00000001U
-#define SPI_FWRITE_OCT_S  14
-/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
- *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
- *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
- *  not seg-trans mode. Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_USR_CONF_NXT    (BIT(15))
-#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
-#define SPI_USR_CONF_NXT_V  0x00000001U
-#define SPI_USR_CONF_NXT_S  15
-/** SPI_SIO : R/W; bitpos: [17]; default: 0;
- *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
- *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
- */
-#define SPI_SIO    (BIT(17))
-#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
-#define SPI_SIO_V  0x00000001U
-#define SPI_SIO_S  17
-/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
- *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
- *  disable. Can be configured in CONF state.
- */
-#define SPI_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
-#define SPI_USR_MISO_HIGHPART_V  0x00000001U
-#define SPI_USR_MISO_HIGHPART_S  24
-/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
- *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
- *  0: disable.  Can be configured in CONF state.
- */
-#define SPI_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
-#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
-#define SPI_USR_MOSI_HIGHPART_S  25
-/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
- *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
- *  CONF state.
- */
-#define SPI_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
-#define SPI_USR_DUMMY_IDLE_V  0x00000001U
-#define SPI_USR_DUMMY_IDLE_S  26
-/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
- *  This bit enable the write-data phase of an operation. Can be configured in CONF
- *  state.
- */
-#define SPI_USR_MOSI    (BIT(27))
-#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
-#define SPI_USR_MOSI_V  0x00000001U
-#define SPI_USR_MOSI_S  27
-/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
- *  This bit enable the read-data phase of an operation. Can be configured in CONF
- *  state.
- */
-#define SPI_USR_MISO    (BIT(28))
-#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
-#define SPI_USR_MISO_V  0x00000001U
-#define SPI_USR_MISO_S  28
-/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
- *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY    (BIT(29))
-#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
-#define SPI_USR_DUMMY_V  0x00000001U
-#define SPI_USR_DUMMY_S  29
-/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
- *  This bit enable the address phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_ADDR    (BIT(30))
-#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
-#define SPI_USR_ADDR_V  0x00000001U
-#define SPI_USR_ADDR_S  30
-/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
- *  This bit enable the command phase of an operation. Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND    (BIT(31))
-#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
-#define SPI_USR_COMMAND_V  0x00000001U
-#define SPI_USR_COMMAND_S  31
-
-/** SPI_USER1_REG register
- *  SPI USER control register 1
- */
-#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
-/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
- *  The length in spi_clk cycles of dummy phase. The register value shall be
- *  (cycle_num-1). Can be configured in CONF state.
- */
-#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
-#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
- *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
- *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
- *  GP-SPI master FD/HD-mode.
- */
-#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
-#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
-#define SPI_MST_WFULL_ERR_END_EN_S  16
-/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
- *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
- *  bit. Can be configured in CONF state.
- */
-#define SPI_CS_SETUP_TIME    0x0000001FU
-#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
-#define SPI_CS_SETUP_TIME_V  0x0000001FU
-#define SPI_CS_SETUP_TIME_S  17
-/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
- *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
- *  Can be configured in CONF state.
- */
-#define SPI_CS_HOLD_TIME    0x0000001FU
-#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
-#define SPI_CS_HOLD_TIME_V  0x0000001FU
-#define SPI_CS_HOLD_TIME_S  22
-/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
- *  The length in bits of address phase. The register value shall be (bit_num-1). Can
- *  be configured in CONF state.
- */
-#define SPI_USR_ADDR_BITLEN    0x0000001FU
-#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
-#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
-#define SPI_USR_ADDR_BITLEN_S  27
-
-/** SPI_USER2_REG register
- *  SPI USER control register 2
- */
-#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
-/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
- *  The value of  command. Can be configured in CONF state.
- */
-#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
-#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
-#define SPI_USR_COMMAND_VALUE_S  0
-/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
- *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
- *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
- *  is valid in GP-SPI master FD/HD-mode.
- */
-#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
-#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
-#define SPI_MST_REMPTY_ERR_END_EN_S  27
-/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
- *  The length in bits of command phase. The register value shall be (bit_num-1). Can
- *  be configured in CONF state.
- */
-#define SPI_USR_COMMAND_BITLEN    0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
-#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
-#define SPI_USR_COMMAND_BITLEN_S  28
-
-/** SPI_MS_DLEN_REG register
- *  SPI data bit length control register
- */
-#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
-/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
- *  The value of these bits is the configured SPI transmission data bit length in
- *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
- *  the configured bit length in slave mode DMA RX controlled transfer. The register
- *  value shall be (bit_num-1). Can be configured in CONF state.
- */
-#define SPI_MS_DATA_BITLEN    0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
-#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_MS_DATA_BITLEN_S  0
-
-/** SPI_MISC_REG register
- *  SPI misc register
- */
-#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
-/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS0_DIS    (BIT(0))
-#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
-#define SPI_CS0_DIS_V  0x00000001U
-#define SPI_CS0_DIS_S  0
-/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS1_DIS    (BIT(1))
-#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
-#define SPI_CS1_DIS_V  0x00000001U
-#define SPI_CS1_DIS_S  1
-/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-#define SPI_CS2_DIS    (BIT(2))
-#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
-#define SPI_CS2_DIS_V  0x00000001U
-#define SPI_CS2_DIS_S  2
-/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_CS3_DIS    (BIT(3))
-#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
-#define SPI_CS3_DIS_V  0x00000001U
-#define SPI_CS3_DIS_S  3
-/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_CS4_DIS    (BIT(4))
-#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
-#define SPI_CS4_DIS_V  0x00000001U
-#define SPI_CS4_DIS_S  4
-/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
- *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
- *  be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_CS5_DIS    (BIT(5))
-#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
-#define SPI_CS5_DIS_V  0x00000001U
-#define SPI_CS5_DIS_S  5
-/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
- *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
- */
-#define SPI_CK_DIS    (BIT(6))
-#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
-#define SPI_CK_DIS_V  0x00000001U
-#define SPI_CK_DIS_S  6
-/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
- *  In the master mode the bits are the polarity of spi cs line, the value is
- *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
- */
-//This field for GPSPI3 is only 3-bit-width
-#define SPI_MASTER_CS_POL    0x0000003FU
-#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
-#define SPI_MASTER_CS_POL_V  0x0000003FU
-#define SPI_MASTER_CS_POL_S  7
-/** SPI_CLK_DATA_DTR_EN : R/W; bitpos: [16]; default: 0;
- *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
- *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
- */
-//this field is only for GPSPI2
-#define SPI_CLK_DATA_DTR_EN    (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
-#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
-#define SPI_CLK_DATA_DTR_EN_S  16
-/** SPI_DATA_DTR_EN : R/W; bitpos: [17]; default: 0;
- *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
- *  Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DATA_DTR_EN    (BIT(17))
-#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
-#define SPI_DATA_DTR_EN_V  0x00000001U
-#define SPI_DATA_DTR_EN_S  17
-/** SPI_ADDR_DTR_EN : R/W; bitpos: [18]; default: 0;
- *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
- *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
- *  configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_ADDR_DTR_EN    (BIT(18))
-#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
-#define SPI_ADDR_DTR_EN_V  0x00000001U
-#define SPI_ADDR_DTR_EN_S  18
-/** SPI_CMD_DTR_EN : R/W; bitpos: [19]; default: 0;
- *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
- *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
- *  configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_CMD_DTR_EN    (BIT(19))
-#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
-#define SPI_CMD_DTR_EN_V  0x00000001U
-#define SPI_CMD_DTR_EN_S  19
-/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
- *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
- *  CONF state.
- */
-#define SPI_SLAVE_CS_POL    (BIT(23))
-#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
-#define SPI_SLAVE_CS_POL_V  0x00000001U
-#define SPI_SLAVE_CS_POL_S  23
-/** SPI_DQS_IDLE_EDGE : R/W; bitpos: [24]; default: 0;
- *  The default value of spi_dqs. Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DQS_IDLE_EDGE    (BIT(24))
-#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
-#define SPI_DQS_IDLE_EDGE_V  0x00000001U
-#define SPI_DQS_IDLE_EDGE_S  24
-/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
- *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
- *  configured in CONF state.
- */
-#define SPI_CK_IDLE_EDGE    (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
-#define SPI_CK_IDLE_EDGE_V  0x00000001U
-#define SPI_CK_IDLE_EDGE_S  29
-/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
- *  spi cs line keep low when the bit is set. Can be configured in CONF state.
- */
-#define SPI_CS_KEEP_ACTIVE    (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
-#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
-#define SPI_CS_KEEP_ACTIVE_S  30
-/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
- *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
- *  spi quad input swap disable. Can be configured in CONF state.
- */
-#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
-#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
-#define SPI_QUAD_DIN_PIN_SWAP_S  31
-
-/** SPI_DIN_MODE_REG register
- *  SPI input delay mode configuration
- */
-#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
-/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN0_MODE    0x00000003U
-#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
-#define SPI_DIN0_MODE_V  0x00000003U
-#define SPI_DIN0_MODE_S  0
-/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN1_MODE    0x00000003U
-#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
-#define SPI_DIN1_MODE_V  0x00000003U
-#define SPI_DIN1_MODE_S  2
-/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN2_MODE    0x00000003U
-#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
-#define SPI_DIN2_MODE_V  0x00000003U
-#define SPI_DIN2_MODE_S  4
-/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-#define SPI_DIN3_MODE    0x00000003U
-#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
-#define SPI_DIN3_MODE_V  0x00000003U
-#define SPI_DIN3_MODE_S  6
-/** SPI_DIN4_MODE : R/W; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DIN4_MODE    0x00000003U
-#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
-#define SPI_DIN4_MODE_V  0x00000003U
-#define SPI_DIN4_MODE_S  8
-/** SPI_DIN5_MODE : R/W; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DIN5_MODE    0x00000003U
-#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
-#define SPI_DIN5_MODE_V  0x00000003U
-#define SPI_DIN5_MODE_S  10
-/** SPI_DIN6_MODE : R/W; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DIN6_MODE    0x00000003U
-#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
-#define SPI_DIN6_MODE_V  0x00000003U
-#define SPI_DIN6_MODE_S  12
-/** SPI_DIN7_MODE : R/W; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
- *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
- *  with the spi_clk. Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DIN7_MODE    0x00000003U
-#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
-#define SPI_DIN7_MODE_V  0x00000003U
-#define SPI_DIN7_MODE_S  14
-/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
- *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
- *  state.
- */
-#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
-#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
-#define SPI_TIMING_HCLK_ACTIVE_S  16
-
-/** SPI_DIN_NUM_REG register
- *  SPI input delay number configuration
- */
-#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
-/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN0_NUM    0x00000003U
-#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
-#define SPI_DIN0_NUM_V  0x00000003U
-#define SPI_DIN0_NUM_S  0
-/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN1_NUM    0x00000003U
-#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
-#define SPI_DIN1_NUM_V  0x00000003U
-#define SPI_DIN1_NUM_S  2
-/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN2_NUM    0x00000003U
-#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
-#define SPI_DIN2_NUM_V  0x00000003U
-#define SPI_DIN2_NUM_S  4
-/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-#define SPI_DIN3_NUM    0x00000003U
-#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
-#define SPI_DIN3_NUM_V  0x00000003U
-#define SPI_DIN3_NUM_S  6
-/** SPI_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DIN4_NUM    0x00000003U
-#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
-#define SPI_DIN4_NUM_V  0x00000003U
-#define SPI_DIN4_NUM_S  8
-/** SPI_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DIN5_NUM    0x00000003U
-#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
-#define SPI_DIN5_NUM_V  0x00000003U
-#define SPI_DIN5_NUM_S  10
-/** SPI_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DIN6_NUM    0x00000003U
-#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
-#define SPI_DIN6_NUM_V  0x00000003U
-#define SPI_DIN6_NUM_S  12
-/** SPI_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
- *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
- *  delayed by 2 cycles,...  Can be configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DIN7_NUM    0x00000003U
-#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
-#define SPI_DIN7_NUM_V  0x00000003U
-#define SPI_DIN7_NUM_S  14
-
-/** SPI_DOUT_MODE_REG register
- *  SPI output delay mode configuration
- */
-#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
-/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT0_MODE    (BIT(0))
-#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
-#define SPI_DOUT0_MODE_V  0x00000001U
-#define SPI_DOUT0_MODE_S  0
-/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT1_MODE    (BIT(1))
-#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
-#define SPI_DOUT1_MODE_V  0x00000001U
-#define SPI_DOUT1_MODE_S  1
-/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT2_MODE    (BIT(2))
-#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
-#define SPI_DOUT2_MODE_V  0x00000001U
-#define SPI_DOUT2_MODE_S  2
-/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-#define SPI_DOUT3_MODE    (BIT(3))
-#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
-#define SPI_DOUT3_MODE_V  0x00000001U
-#define SPI_DOUT3_MODE_S  3
-/** SPI_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DOUT4_MODE    (BIT(4))
-#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
-#define SPI_DOUT4_MODE_V  0x00000001U
-#define SPI_DOUT4_MODE_S  4
-/** SPI_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DOUT5_MODE    (BIT(5))
-#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
-#define SPI_DOUT5_MODE_V  0x00000001U
-#define SPI_DOUT5_MODE_S  5
-/** SPI_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DOUT6_MODE    (BIT(6))
-#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
-#define SPI_DOUT6_MODE_V  0x00000001U
-#define SPI_DOUT6_MODE_S  6
-/** SPI_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
- *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
- *  1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_DOUT7_MODE    (BIT(7))
-#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
-#define SPI_DOUT7_MODE_V  0x00000001U
-#define SPI_DOUT7_MODE_S  7
-/** SPI_D_DQS_MODE : R/W; bitpos: [8]; default: 0;
- *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
- *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
- *  configured in CONF state.
- */
-//this field is only for GPSPI2
-#define SPI_D_DQS_MODE    (BIT(8))
-#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
-#define SPI_D_DQS_MODE_V  0x00000001U
-#define SPI_D_DQS_MODE_S  8
-
-/** SPI_DMA_CONF_REG register
- *  SPI DMA control register
- */
-#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
-/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
- *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
- *  DMA TX FIFO is ready for sending data.
- */
-#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
-#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_S  0
-/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
- *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
- *  0: DMA RX FIFO is ready for receiving data.
- */
-#define SPI_DMA_INFIFO_FULL    (BIT(1))
-#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
-#define SPI_DMA_INFIFO_FULL_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_S  1
-/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
- *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
- */
-#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
-#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
-#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
-/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
- *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
- *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
- */
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
-/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
- *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
- *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
- */
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
-/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
- *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
- *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
- *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
- *  spi_dma_seg_trans_done in seg-trans.
- */
-#define SPI_RX_EOF_EN    (BIT(21))
-#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
-#define SPI_RX_EOF_EN_V  0x00000001U
-#define SPI_RX_EOF_EN_S  21
-/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
- *  Set this bit to enable SPI DMA controlled receive data mode.
- */
-#define SPI_DMA_RX_ENA    (BIT(27))
-#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
-#define SPI_DMA_RX_ENA_V  0x00000001U
-#define SPI_DMA_RX_ENA_S  27
-/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
- *  Set this bit to enable SPI DMA controlled send data mode.
- */
-#define SPI_DMA_TX_ENA    (BIT(28))
-#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
-#define SPI_DMA_TX_ENA_V  0x00000001U
-#define SPI_DMA_TX_ENA_S  28
-/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
- *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
- *  slave mode transfer.
- */
-#define SPI_RX_AFIFO_RST    (BIT(29))
-#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
-#define SPI_RX_AFIFO_RST_V  0x00000001U
-#define SPI_RX_AFIFO_RST_S  29
-/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
- *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
- *  controlled mode transfer and master mode transfer.
- */
-#define SPI_BUF_AFIFO_RST    (BIT(30))
-#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
-#define SPI_BUF_AFIFO_RST_V  0x00000001U
-#define SPI_BUF_AFIFO_RST_S  30
-/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
- *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
- *  controlled mode transfer.
- */
-#define SPI_DMA_AFIFO_RST    (BIT(31))
-#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
-#define SPI_DMA_AFIFO_RST_V  0x00000001U
-#define SPI_DMA_AFIFO_RST_S  31
-
-/** SPI_DMA_INT_ENA_REG register
- *  SPI interrupt enable register
- */
-#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
-/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
-#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ENA_S  2
-/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
-#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ENA_S  3
-/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
-#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ENA_S  4
-/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The enable bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
-#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ENA_S  5
-/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
-#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ENA_S  6
-/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
-#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ENA_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
-/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The enable bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
-#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ENA_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-//this field is only for GPSPI2
-#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
-#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
-/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
-#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ENA_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
-/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  The enable bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ENA    (BIT(19))
-#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
-#define SPI_APP2_INT_ENA_V  0x00000001U
-#define SPI_APP2_INT_ENA_S  19
-/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  The enable bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ENA    (BIT(20))
-#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
-#define SPI_APP1_INT_ENA_V  0x00000001U
-#define SPI_APP1_INT_ENA_S  20
-
-/** SPI_DMA_INT_CLR_REG register
- *  SPI interrupt clear register
- */
-#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
- *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
- *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
-/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
- *  The clear bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
-#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_CLR_S  2
-/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
- *  The clear bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
-#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_CLR_S  3
-/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
- *  The clear bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
-#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD7_INT_CLR_S  4
-/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
- *  The clear bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
-#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD8_INT_CLR_S  5
-/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
- *  The clear bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
-#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD9_INT_CLR_S  6
-/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
- *  The clear bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
-#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMDA_INT_CLR_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
- *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
- *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
- *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
- *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
-/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  The clear bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
-#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_TRANS_DONE_INT_CLR_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
-/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-//this field is only for GPSPI2
-#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
-#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
-/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
-#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_CLR_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
- *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
- *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
-/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
- *  The clear bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_CLR    (BIT(19))
-#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
-#define SPI_APP2_INT_CLR_V  0x00000001U
-#define SPI_APP2_INT_CLR_S  19
-/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
- *  The clear bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_CLR    (BIT(20))
-#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
-#define SPI_APP1_INT_CLR_V  0x00000001U
-#define SPI_APP1_INT_CLR_S  20
-
-/** SPI_DMA_INT_RAW_REG register
- *  SPI interrupt raw register
- */
-#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
- *  receive data.  0: Others.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
- *  master mode and send out all 0 in slave mode.  0: Others.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
-/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
- *  is ended. 0: Others.
- */
-#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
-#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_RAW_S  2
-/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
- *  is ended. 0: Others.
- */
-#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
-#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_RAW_S  3
-/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
-#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD7_INT_RAW_S  4
-/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
-#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD8_INT_RAW_S  5
-/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
-#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD9_INT_RAW_S  6
-/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
- *  ended. 0: Others.
- */
-#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
-#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMDA_INT_RAW_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
- *  transmission is ended. 0: Others.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
-/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
- *  ended. 0: others.
- */
-#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
-#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_TRANS_DONE_INT_RAW_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
- *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
- *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
- *  is not ended or not occurred.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
-/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
- *  is error in the DMA seg-conf-trans. 0: others.
- */
-//this field is only for GPSPI2
-#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
-#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
- *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
- *  bigger than 63. 0: Others.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
-/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
- *  current SPI slave HD mode transmission is not supported. 0: Others.
- */
-#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
-#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_RAW_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
- *  write-full error when SPI inputs data in master mode. 0: Others.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
- *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
-/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
- */
-#define SPI_APP2_INT_RAW    (BIT(19))
-#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
-#define SPI_APP2_INT_RAW_V  0x00000001U
-#define SPI_APP2_INT_RAW_S  19
-/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
- */
-#define SPI_APP1_INT_RAW    (BIT(20))
-#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
-#define SPI_APP1_INT_RAW_V  0x00000001U
-#define SPI_APP1_INT_RAW_S  20
-
-/** SPI_DMA_INT_ST_REG register
- *  SPI interrupt status register
- */
-#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
-/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
- *  The status bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
-#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_ST_S  2
-/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
- *  The status bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
-#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_ST_S  3
-/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
- *  The status bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_ST    (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
-#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD7_INT_ST_S  4
-/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
- *  The status bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_ST    (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
-#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD8_INT_ST_S  5
-/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
- *  The status bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_ST    (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
-#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD9_INT_ST_S  6
-/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
- *  The status bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_ST    (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
-#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
-#define SPI_SLV_CMDA_INT_ST_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
- *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
-#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
- *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
-#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
- *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
-#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
- *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
-#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
-/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  The status bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_ST    (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
-#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_TRANS_DONE_INT_ST_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
-/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
- *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-//this field is only for GPSPI2
-#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
-#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
-/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
-#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_ST_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
- *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
- *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
-/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
- *  The status bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_ST    (BIT(19))
-#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
-#define SPI_APP2_INT_ST_V  0x00000001U
-#define SPI_APP2_INT_ST_S  19
-/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
- *  The status bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_ST    (BIT(20))
-#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
-#define SPI_APP1_INT_ST_V  0x00000001U
-#define SPI_APP1_INT_ST_S  20
-
-/** SPI_DMA_INT_SET_REG register
- *  SPI interrupt software set register
- */
-#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
-/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
- *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
- */
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
-/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
- *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
- */
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
-/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
- *  The software set bit for SPI slave Ex_QPI interrupt.
- */
-#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
-#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EX_QPI_INT_SET_S  2
-/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
- *  The software set bit for SPI slave En_QPI interrupt.
- */
-#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
-#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
-#define SPI_SLV_EN_QPI_INT_SET_S  3
-/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
- *  The software set bit for SPI slave CMD7 interrupt.
- */
-#define SPI_SLV_CMD7_INT_SET    (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
-#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD7_INT_SET_S  4
-/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
- *  The software set bit for SPI slave CMD8 interrupt.
- */
-#define SPI_SLV_CMD8_INT_SET    (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
-#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD8_INT_SET_S  5
-/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
- *  The software set bit for SPI slave CMD9 interrupt.
- */
-#define SPI_SLV_CMD9_INT_SET    (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
-#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD9_INT_SET_S  6
-/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
- *  The software set bit for SPI slave CMDA interrupt.
- */
-#define SPI_SLV_CMDA_INT_SET    (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
-#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
-#define SPI_SLV_CMDA_INT_SET_S  7
-/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
- *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
-#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
-/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
- *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
-#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
-/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
- *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
-#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
-/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
- *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
- */
-#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
-#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
-#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
-/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
- *  The software set bit for SPI_TRANS_DONE_INT interrupt.
- */
-#define SPI_TRANS_DONE_INT_SET    (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
-#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_TRANS_DONE_INT_SET_S  12
-/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
- *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
- */
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
-/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
- *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
- */
-//this field is only for GPSPI2
-#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
-#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
-#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
-/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
- *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
- */
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
-/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
- *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
- */
-#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
-#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
-#define SPI_SLV_CMD_ERR_INT_SET_S  16
-/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
- *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
- */
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
-/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
- *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
- */
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
-/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
- *  The software set bit for SPI_APP2_INT interrupt.
- */
-#define SPI_APP2_INT_SET    (BIT(19))
-#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
-#define SPI_APP2_INT_SET_V  0x00000001U
-#define SPI_APP2_INT_SET_S  19
-/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
- *  The software set bit for SPI_APP1_INT interrupt.
- */
-#define SPI_APP1_INT_SET    (BIT(20))
-#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
-#define SPI_APP1_INT_SET_V  0x00000001U
-#define SPI_APP1_INT_SET_S  20
-
-/** SPI_W0_REG register
- *  SPI CPU-controlled buffer0
- */
-#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
-/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF0    0xFFFFFFFFU
-#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
-#define SPI_BUF0_V  0xFFFFFFFFU
-#define SPI_BUF0_S  0
-
-/** SPI_W1_REG register
- *  SPI CPU-controlled buffer1
- */
-#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
-/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF1    0xFFFFFFFFU
-#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
-#define SPI_BUF1_V  0xFFFFFFFFU
-#define SPI_BUF1_S  0
-
-/** SPI_W2_REG register
- *  SPI CPU-controlled buffer2
- */
-#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
-/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF2    0xFFFFFFFFU
-#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
-#define SPI_BUF2_V  0xFFFFFFFFU
-#define SPI_BUF2_S  0
-
-/** SPI_W3_REG register
- *  SPI CPU-controlled buffer3
- */
-#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
-/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF3    0xFFFFFFFFU
-#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
-#define SPI_BUF3_V  0xFFFFFFFFU
-#define SPI_BUF3_S  0
-
-/** SPI_W4_REG register
- *  SPI CPU-controlled buffer4
- */
-#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
-/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF4    0xFFFFFFFFU
-#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
-#define SPI_BUF4_V  0xFFFFFFFFU
-#define SPI_BUF4_S  0
-
-/** SPI_W5_REG register
- *  SPI CPU-controlled buffer5
- */
-#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
-/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF5    0xFFFFFFFFU
-#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
-#define SPI_BUF5_V  0xFFFFFFFFU
-#define SPI_BUF5_S  0
-
-/** SPI_W6_REG register
- *  SPI CPU-controlled buffer6
- */
-#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
-/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF6    0xFFFFFFFFU
-#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
-#define SPI_BUF6_V  0xFFFFFFFFU
-#define SPI_BUF6_S  0
-
-/** SPI_W7_REG register
- *  SPI CPU-controlled buffer7
- */
-#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
-/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF7    0xFFFFFFFFU
-#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
-#define SPI_BUF7_V  0xFFFFFFFFU
-#define SPI_BUF7_S  0
-
-/** SPI_W8_REG register
- *  SPI CPU-controlled buffer8
- */
-#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
-/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF8    0xFFFFFFFFU
-#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
-#define SPI_BUF8_V  0xFFFFFFFFU
-#define SPI_BUF8_S  0
-
-/** SPI_W9_REG register
- *  SPI CPU-controlled buffer9
- */
-#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
-/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF9    0xFFFFFFFFU
-#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
-#define SPI_BUF9_V  0xFFFFFFFFU
-#define SPI_BUF9_S  0
-
-/** SPI_W10_REG register
- *  SPI CPU-controlled buffer10
- */
-#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
-/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF10    0xFFFFFFFFU
-#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
-#define SPI_BUF10_V  0xFFFFFFFFU
-#define SPI_BUF10_S  0
-
-/** SPI_W11_REG register
- *  SPI CPU-controlled buffer11
- */
-#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
-/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF11    0xFFFFFFFFU
-#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
-#define SPI_BUF11_V  0xFFFFFFFFU
-#define SPI_BUF11_S  0
-
-/** SPI_W12_REG register
- *  SPI CPU-controlled buffer12
- */
-#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
-/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF12    0xFFFFFFFFU
-#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
-#define SPI_BUF12_V  0xFFFFFFFFU
-#define SPI_BUF12_S  0
-
-/** SPI_W13_REG register
- *  SPI CPU-controlled buffer13
- */
-#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
-/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF13    0xFFFFFFFFU
-#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
-#define SPI_BUF13_V  0xFFFFFFFFU
-#define SPI_BUF13_S  0
-
-/** SPI_W14_REG register
- *  SPI CPU-controlled buffer14
- */
-#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
-/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF14    0xFFFFFFFFU
-#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
-#define SPI_BUF14_V  0xFFFFFFFFU
-#define SPI_BUF14_S  0
-
-/** SPI_W15_REG register
- *  SPI CPU-controlled buffer15
- */
-#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
-/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
- *  data buffer
- */
-#define SPI_BUF15    0xFFFFFFFFU
-#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
-#define SPI_BUF15_V  0xFFFFFFFFU
-#define SPI_BUF15_S  0
-
-/** SPI_SLAVE_REG register
- *  SPI slave control register
- */
-#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
-/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
- *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
- *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on. Can be configured in CONF state.
- */
-#define SPI_CLK_MODE    0x00000003U
-#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
-#define SPI_CLK_MODE_V  0x00000003U
-#define SPI_CLK_MODE_S  0
-/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
- *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
- *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
- */
-#define SPI_CLK_MODE_13    (BIT(2))
-#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
-#define SPI_CLK_MODE_13_V  0x00000001U
-#define SPI_CLK_MODE_13_S  2
-/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
- *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
- *  0: output data at tsck posedge
- */
-#define SPI_RSCK_DATA_OUT    (BIT(3))
-#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
-#define SPI_RSCK_DATA_OUT_V  0x00000001U
-#define SPI_RSCK_DATA_OUT_S  3
-/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
- *  DMA controlled mode(Rd_DMA). 0: others
- */
-#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
-#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDDMA_BITLEN_EN_S  8
-/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
- *  in DMA controlled mode(Wr_DMA). 0: others
- */
-#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
-#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRDMA_BITLEN_EN_S  9
-/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
- *  CPU controlled mode(Rd_BUF). 0: others
- */
-#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
-#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_RDBUF_BITLEN_EN_S  10
-/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
- *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
- *  in CPU controlled mode(Wr_BUF). 0: others
- */
-#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
-#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
-#define SPI_SLV_WRBUF_BITLEN_EN_S  11
-/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0;
- *  Represents the effective bit of the last received data byte in SPI slave FD and HD
- *  mode.
- */
-#define SPI_SLV_LAST_BYTE_STRB    0x000000FFU
-#define SPI_SLV_LAST_BYTE_STRB_M  (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S)
-#define SPI_SLV_LAST_BYTE_STRB_V  0x000000FFU
-#define SPI_SLV_LAST_BYTE_STRB_S  12
-/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
- *  The magic value of BM table in master DMA seg-trans.
- */
-//this field is only for GPSPI2
-#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
-#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
-#define SPI_DMA_SEG_MAGIC_VALUE_S  22
-/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
- *  Set SPI work mode. 1: slave mode 0: master mode.
- */
-#define SPI_SLAVE_MODE    (BIT(26))
-#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
-#define SPI_SLAVE_MODE_V  0x00000001U
-#define SPI_SLAVE_MODE_S  26
-/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
- *  Software reset enable, reset the spi clock line cs line and data lines. Can be
- *  configured in CONF state.
- */
-#define SPI_SOFT_RESET    (BIT(27))
-#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
-#define SPI_SOFT_RESET_V  0x00000001U
-#define SPI_SOFT_RESET_S  27
-/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
- *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
- *  will start. 0: This is not seg-trans mode.
- */
-//this field is only for GPSPI2
-#define SPI_USR_CONF    (BIT(28))
-#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
-#define SPI_USR_CONF_V  0x00000001U
-#define SPI_USR_CONF_S  28
-/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
- *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
- *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
- *  transfer.
- */
-#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
-#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
-
-/** SPI_SLAVE1_REG register
- *  SPI slave control register 1
- */
-#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
-/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
- *  The transferred data bit length in SPI slave FD and HD mode.
- */
-#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
-#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
-#define SPI_SLV_DATA_BITLEN_S  0
-/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
- *  In the slave mode it is the value of command.
- */
-#define SPI_SLV_LAST_COMMAND    0x000000FFU
-#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
-#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
-#define SPI_SLV_LAST_COMMAND_S  18
-/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
- *  In the slave mode it is the value of address.
- */
-#define SPI_SLV_LAST_ADDR    0x0000003FU
-#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
-#define SPI_SLV_LAST_ADDR_V  0x0000003FU
-#define SPI_SLV_LAST_ADDR_S  26
-
-/** SPI_CLK_GATE_REG register
- *  SPI module clock and register clock control
- */
-#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
-/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable clk gate
- */
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
-#define SPI_CLK_EN_V  0x00000001U
-#define SPI_CLK_EN_S  0
-/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
- *  Set this bit to power on the SPI module clock.
- */
-#define SPI_MST_CLK_ACTIVE    (BIT(1))
-#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
-#define SPI_MST_CLK_ACTIVE_V  0x00000001U
-#define SPI_MST_CLK_ACTIVE_S  1
-/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
- *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
- *  0: XTAL CLK.
- */
-#define SPI_MST_CLK_SEL    (BIT(2))
-#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
-#define SPI_MST_CLK_SEL_V  0x00000001U
-#define SPI_MST_CLK_SEL_S  2
-
-/** SPI_DATE_REG register
- *  Version control
- */
-#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
-/** SPI_DATE : R/W; bitpos: [27:0]; default: 35680770;
- *  SPI register version.
- */
-#define SPI_DATE    0x0FFFFFFFU
-#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
-#define SPI_DATE_V  0x0FFFFFFFU
-#define SPI_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/spi_struct.h b/components/soc/esp32p4/include/soc/spi_struct.h
deleted file mode 100644
index 66929cd3a07..00000000000
--- a/components/soc/esp32p4/include/soc/spi_struct.h
+++ /dev/null
@@ -1,1026 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: User-defined control registers */
-/** Type of cmd register
- *  Command control register
- */
-typedef union {
-    struct {
-        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
-         */
-        uint32_t conf_bitlen:18;  //this field is only for GPSPI2
-        uint32_t reserved_18:5;
-        /** update : WT; bitpos: [23]; default: 0;
-         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
-         *  clock domain, which is only used in SPI master mode.
-         */
-        uint32_t update:1;
-        /** usr : R/W/SC; bitpos: [24]; default: 0;
-         *  User define command enable.  An operation will be triggered when the bit is set.
-         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
-         *  changed by CONF_buf.
-         */
-        uint32_t usr:1;
-        uint32_t reserved_25:7;
-    };
-    uint32_t val;
-} spi_cmd_reg_t;
-
-/** Type of addr register
- *  Address value register
- */
-typedef union {
-    struct {
-        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
-         *  Address to slave. Can be configured in CONF state.
-         */
-        uint32_t usr_addr_value:32;
-    };
-    uint32_t val;
-} spi_addr_reg_t;
-
-/** Type of user register
- *  SPI USER control register
- */
-typedef union {
-    struct {
-        /** doutdin : R/W; bitpos: [0]; default: 0;
-         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t doutdin:1;
-        uint32_t reserved_1:2;
-        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
-         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t qpi_mode:1;
-        /** opi_mode : R/W; bitpos: [4]; default: 0;
-         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
-         *  Can be configured in CONF state.
-         */
-        uint32_t opi_mode:1;  //this field is only for GPSPI2
-        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
-         *  spi_ck_i. 1:tsck = !spi_ck_i.
-         */
-        uint32_t tsck_i_edge:1;
-        /** cs_hold : R/W; bitpos: [6]; default: 1;
-         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_hold:1;
-        /** cs_setup : R/W; bitpos: [7]; default: 1;
-         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cs_setup:1;
-        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
-         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
-         *  !spi_ck_i. 1:rsck = spi_ck_i.
-         */
-        uint32_t rsck_i_edge:1;
-        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
-         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
-         *  be configured in CONF state.
-         */
-        uint32_t ck_out_edge:1;
-        uint32_t reserved_10:2;
-        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
-         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_dual:1;
-        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
-         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_quad:1;
-        /** fwrite_oct : R/W; bitpos: [14]; default: 0;
-         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fwrite_oct:1;  //this field is only for GPSPI2
-        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
-         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
-         *  not seg-trans mode. Can be configured in CONF state.
-         */
-        uint32_t usr_conf_nxt:1;  //this field is only for GPSPI2
-        uint32_t reserved_16:1;
-        /** sio : R/W; bitpos: [17]; default: 0;
-         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
-         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
-         */
-        uint32_t sio:1;
-        uint32_t reserved_18:6;
-        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
-         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
-         *  disable. Can be configured in CONF state.
-         */
-        uint32_t usr_miso_highpart:1;
-        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
-         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
-         *  0: disable.  Can be configured in CONF state.
-         */
-        uint32_t usr_mosi_highpart:1;
-        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
-         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
-         *  CONF state.
-         */
-        uint32_t usr_dummy_idle:1;
-        /** usr_mosi : R/W; bitpos: [27]; default: 0;
-         *  This bit enable the write-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_mosi:1;
-        /** usr_miso : R/W; bitpos: [28]; default: 0;
-         *  This bit enable the read-data phase of an operation. Can be configured in CONF
-         *  state.
-         */
-        uint32_t usr_miso:1;
-        /** usr_dummy : R/W; bitpos: [29]; default: 0;
-         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_dummy:1;
-        /** usr_addr : R/W; bitpos: [30]; default: 0;
-         *  This bit enable the address phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_addr:1;
-        /** usr_command : R/W; bitpos: [31]; default: 1;
-         *  This bit enable the command phase of an operation. Can be configured in CONF state.
-         */
-        uint32_t usr_command:1;
-    };
-    uint32_t val;
-} spi_user_reg_t;
-
-/** Type of user1 register
- *  SPI USER control register 1
- */
-typedef union {
-    struct {
-        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
-         *  The length in spi_clk cycles of dummy phase. The register value shall be
-         *  (cycle_num-1). Can be configured in CONF state.
-         */
-        uint32_t usr_dummy_cyclelen:8;
-        uint32_t reserved_8:8;
-        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
-         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
-         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
-         *  GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_wfull_err_end_en:1;
-        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
-         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
-         *  bit. Can be configured in CONF state.
-         */
-        uint32_t cs_setup_time:5;
-        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
-         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
-         *  Can be configured in CONF state.
-         */
-        uint32_t cs_hold_time:5;
-        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
-         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_addr_bitlen:5;
-    };
-    uint32_t val;
-} spi_user1_reg_t;
-
-/** Type of user2 register
- *  SPI USER control register 2
- */
-typedef union {
-    struct {
-        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
-         *  The value of  command. Can be configured in CONF state.
-         */
-        uint32_t usr_command_value:16;
-        uint32_t reserved_16:11;
-        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
-         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
-         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
-         *  is valid in GP-SPI master FD/HD-mode.
-         */
-        uint32_t mst_rempty_err_end_en:1;
-        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
-         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
-         *  be configured in CONF state.
-         */
-        uint32_t usr_command_bitlen:4;
-    };
-    uint32_t val;
-} spi_user2_reg_t;
-
-
-/** Group: Control and configuration registers */
-/** Type of ctrl register
- *  SPI control register
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:3;
-        /** dummy_out : R/W; bitpos: [3]; default: 0;
-         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
-         *  the FSPI bus signals are output. Can be configured in CONF state.
-         */
-        uint32_t dummy_out:1;
-        uint32_t reserved_4:1;
-        /** faddr_dual : R/W; bitpos: [5]; default: 0;
-         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_dual:1;
-        /** faddr_quad : R/W; bitpos: [6]; default: 0;
-         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_quad:1;
-        /** faddr_oct : R/W; bitpos: [7]; default: 0;
-         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t faddr_oct:1;  //this field is only for GPSPI2
-        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
-         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_dual:1;
-        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
-         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_quad:1;
-        /** fcmd_oct : R/W; bitpos: [10]; default: 0;
-         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
-         *  state.
-         */
-        uint32_t fcmd_oct:1;  //this field is only for GPSPI2
-        uint32_t reserved_11:3;
-        /** fread_dual : R/W; bitpos: [14]; default: 0;
-         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_dual:1;
-        /** fread_quad : R/W; bitpos: [15]; default: 0;
-         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_quad:1;
-        /** fread_oct : R/W; bitpos: [16]; default: 0;
-         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t fread_oct:1;  //this field is only for GPSPI2
-        uint32_t reserved_17:1;
-        /** q_pol : R/W; bitpos: [18]; default: 1;
-         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t q_pol:1;
-        /** d_pol : R/W; bitpos: [19]; default: 1;
-         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-         *  CONF state.
-         */
-        uint32_t d_pol:1;
-        /** hold_pol : R/W; bitpos: [20]; default: 1;
-         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
-         *  configured in CONF state.
-         */
-        uint32_t hold_pol:1;
-        /** wp_pol : R/W; bitpos: [21]; default: 1;
-         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
-         *  be configured in CONF state.
-         */
-        uint32_t wp_pol:1;
-        uint32_t reserved_22:1;
-        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
-         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
-         *  state.
-         */
-        uint32_t rd_bit_order:2;
-        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
-         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
-         *  configured in CONF state.
-         */
-        uint32_t wr_bit_order:2;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} spi_ctrl_reg_t;
-
-/** Type of ms_dlen register
- *  SPI data bit length control register
- */
-typedef union {
-    struct {
-        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
-         *  The value of these bits is the configured SPI transmission data bit length in
-         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
-         *  the configured bit length in slave mode DMA RX controlled transfer. The register
-         *  value shall be (bit_num-1). Can be configured in CONF state.
-         */
-        uint32_t ms_data_bitlen:18;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} spi_ms_dlen_reg_t;
-
-/** Type of misc register
- *  SPI misc register
- */
-typedef union {
-    struct {
-        /** cs0_dis : R/W; bitpos: [0]; default: 0;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs0_dis:1;
-        /** cs1_dis : R/W; bitpos: [1]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs1_dis:1;
-        /** cs2_dis : R/W; bitpos: [2]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs2_dis:1;
-        /** cs3_dis : R/W; bitpos: [3]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs3_dis:1;  //this field is only for GPSPI2
-        /** cs4_dis : R/W; bitpos: [4]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs4_dis:1;  //this field is only for GPSPI2
-        /** cs5_dis : R/W; bitpos: [5]; default: 1;
-         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
-         *  be configured in CONF state.
-         */
-        uint32_t cs5_dis:1;  //this field is only for GPSPI2
-        /** ck_dis : R/W; bitpos: [6]; default: 0;
-         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
-         */
-        uint32_t ck_dis:1;
-        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
-         *  In the master mode the bits are the polarity of spi cs line, the value is
-         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-         */
-        uint32_t master_cs_pol:6;  //This field for GPSPI3 is only 3-bit-width
-        uint32_t reserved_13:3;
-        /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0;
-         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
-         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
-         */
-        uint32_t clk_data_dtr_en:1;  //this field is only for GPSPI2
-        /** data_dtr_en : R/W; bitpos: [17]; default: 0;
-         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
-         *  Can be configured in CONF state.
-         */
-        uint32_t data_dtr_en:1;  //this field is only for GPSPI2
-        /** addr_dtr_en : R/W; bitpos: [18]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
-         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t addr_dtr_en:1;  //this field is only for GPSPI2
-        /** cmd_dtr_en : R/W; bitpos: [19]; default: 0;
-         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
-         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
-         *  configured in CONF state.
-         */
-        uint32_t cmd_dtr_en:1;  //this field is only for GPSPI2
-        uint32_t reserved_20:3;
-        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
-         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
-         *  CONF state.
-         */
-        uint32_t slave_cs_pol:1;
-        /** dqs_idle_edge : R/W; bitpos: [24]; default: 0;
-         *  The default value of spi_dqs. Can be configured in CONF state.
-         */
-        uint32_t dqs_idle_edge:1;  //this field is only for GPSPI2
-        uint32_t reserved_25:4;
-        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
-         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
-         *  configured in CONF state.
-         */
-        uint32_t ck_idle_edge:1;
-        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
-         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
-         */
-        uint32_t cs_keep_active:1;
-        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
-         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
-         *  spi quad input swap disable. Can be configured in CONF state.
-         */
-        uint32_t quad_din_pin_swap:1;
-    };
-    uint32_t val;
-} spi_misc_reg_t;
-
-/** Type of dma_conf register
- *  SPI DMA control register
- */
-typedef union {
-    struct {
-        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
-         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
-         *  DMA TX FIFO is ready for sending data.
-         */
-        uint32_t dma_outfifo_empty:1;
-        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
-         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
-         *  0: DMA RX FIFO is ready for receiving data.
-         */
-        uint32_t dma_infifo_full:1;
-        uint32_t reserved_2:16;
-        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
-         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-         */
-        uint32_t dma_slv_seg_trans_en:1;
-        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
-         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
-         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_rx_seg_trans_clr_en:1;
-        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
-         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
-         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-         */
-        uint32_t slv_tx_seg_trans_clr_en:1;
-        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
-         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
-         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
-         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
-         *  spi_dma_seg_trans_done in seg-trans.
-         */
-        uint32_t rx_eof_en:1;
-        uint32_t reserved_22:5;
-        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
-         *  Set this bit to enable SPI DMA controlled receive data mode.
-         */
-        uint32_t dma_rx_ena:1;
-        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to enable SPI DMA controlled send data mode.
-         */
-        uint32_t dma_tx_ena:1;
-        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
-         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-         *  slave mode transfer.
-         */
-        uint32_t rx_afifo_rst:1;
-        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
-         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
-         *  controlled mode transfer and master mode transfer.
-         */
-        uint32_t buf_afifo_rst:1;
-        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
-         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
-         *  controlled mode transfer.
-         */
-        uint32_t dma_afifo_rst:1;
-    };
-    uint32_t val;
-} spi_dma_conf_reg_t;
-
-/** Type of slave register
- *  SPI slave control register
- */
-typedef union {
-    struct {
-        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
-         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
-         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on. Can be configured in CONF state.
-         */
-        uint32_t clk_mode:2;
-        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
-         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
-         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-         */
-        uint32_t clk_mode_13:1;
-        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
-         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
-         *  0: output data at tsck posedge
-         */
-        uint32_t rsck_data_out:1;
-        uint32_t reserved_4:4;
-        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  DMA controlled mode(Rd_DMA). 0: others
-         */
-        uint32_t slv_rddma_bitlen_en:1;
-        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in DMA controlled mode(Wr_DMA). 0: others
-         */
-        uint32_t slv_wrdma_bitlen_en:1;
-        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
-         *  CPU controlled mode(Rd_BUF). 0: others
-         */
-        uint32_t slv_rdbuf_bitlen_en:1;
-        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
-         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
-         *  in CPU controlled mode(Wr_BUF). 0: others
-         */
-        uint32_t slv_wrbuf_bitlen_en:1;
-        /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0;
-         *  Represents the effective bit of the last received data byte in SPI slave FD and HD
-         *  mode.
-         */
-        uint32_t slv_last_byte_strb:8;
-        uint32_t reserved_20:2;
-        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
-         *  The magic value of BM table in master DMA seg-trans.
-         */
-        uint32_t dma_seg_magic_value:4;  //this field is only for GPSPI2
-        /** slave_mode : R/W; bitpos: [26]; default: 0;
-         *  Set SPI work mode. 1: slave mode 0: master mode.
-         */
-        uint32_t slave_mode:1;
-        /** soft_reset : WT; bitpos: [27]; default: 0;
-         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
-         *  configured in CONF state.
-         */
-        uint32_t soft_reset:1;
-        /** usr_conf : R/W; bitpos: [28]; default: 0;
-         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
-         *  will start. 0: This is not seg-trans mode.
-         */
-        uint32_t usr_conf:1;  //this field is only for GPSPI2
-        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
-         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
-         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
-         *  transfer.
-         */
-        uint32_t mst_fd_wait_dma_tx_data:1;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} spi_slave_reg_t;
-
-/** Type of slave1 register
- *  SPI slave control register 1
- */
-typedef union {
-    struct {
-        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
-         *  The transferred data bit length in SPI slave FD and HD mode.
-         */
-        uint32_t slv_data_bitlen:18;
-        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
-         *  In the slave mode it is the value of command.
-         */
-        uint32_t slv_last_command:8;
-        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
-         *  In the slave mode it is the value of address.
-         */
-        uint32_t slv_last_addr:6;
-    };
-    uint32_t val;
-} spi_slave1_reg_t;
-
-
-/** Group: Clock control registers */
-/** Type of clock register
- *  SPI clock control register
- */
-typedef union {
-    struct {
-        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
-         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
-         *  0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_l:6;
-        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
-         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-         *  must be 0. Can be configured in CONF state.
-         */
-        uint32_t clkcnt_h:6;
-        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
-         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
-         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-         */
-        uint32_t clkcnt_n:6;
-        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
-         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
-         */
-        uint32_t clkdiv_pre:4;
-        uint32_t reserved_22:9;
-        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
-         *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
-         *  clock. Can be configured in CONF state.
-         */
-        uint32_t clk_equ_sysclk:1;
-    };
-    uint32_t val;
-} spi_clock_reg_t;
-
-/** Type of clk_gate register
- *  SPI module clock and register clock control
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable clk gate
-         */
-        uint32_t clk_en:1;
-        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to power on the SPI module clock.
-         */
-        uint32_t mst_clk_active:1;
-        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
-         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
-         *  0: XTAL CLK.
-         */
-        uint32_t mst_clk_sel:1;
-        uint32_t reserved_3:29;
-    };
-    uint32_t val;
-} spi_clk_gate_reg_t;
-
-
-/** Group: Timing registers */
-/** Type of din_mode register
- *  SPI input delay mode configuration
- */
-typedef union {
-    struct {
-        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din0_mode:2;
-        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din1_mode:2;
-        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din2_mode:2;
-        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din3_mode:2;
-        /** din4_mode : R/W; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din4_mode:2;  //this field is only for GPSPI2
-        /** din5_mode : R/W; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din5_mode:2;  //this field is only for GPSPI2
-        /** din6_mode : R/W; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din6_mode:2;  //this field is only for GPSPI2
-        /** din7_mode : R/W; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
-         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
-         *  with the spi_clk. Can be configured in CONF state.
-         */
-        uint32_t din7_mode:2;  //this field is only for GPSPI2
-        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
-         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
-         *  state.
-         */
-        uint32_t timing_hclk_active:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} spi_din_mode_reg_t;
-
-/** Type of din_num register
- *  SPI input delay number configuration
- */
-typedef union {
-    struct {
-        /** din0_num : R/W; bitpos: [1:0]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din0_num:2;
-        /** din1_num : R/W; bitpos: [3:2]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din1_num:2;
-        /** din2_num : R/W; bitpos: [5:4]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din2_num:2;
-        /** din3_num : R/W; bitpos: [7:6]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din3_num:2;
-        /** din4_num : R/W; bitpos: [9:8]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din4_num:2;  //this field is only for GPSPI2
-        /** din5_num : R/W; bitpos: [11:10]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din5_num:2;  //this field is only for GPSPI2
-        /** din6_num : R/W; bitpos: [13:12]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din6_num:2;  //this field is only for GPSPI2
-        /** din7_num : R/W; bitpos: [15:14]; default: 0;
-         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
-         *  delayed by 2 cycles,...  Can be configured in CONF state.
-         */
-        uint32_t din7_num:2;  //this field is only for GPSPI2
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} spi_din_num_reg_t;
-
-/** Type of dout_mode register
- *  SPI output delay mode configuration
- */
-typedef union {
-    struct {
-        /** dout0_mode : R/W; bitpos: [0]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout0_mode:1;
-        /** dout1_mode : R/W; bitpos: [1]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout1_mode:1;
-        /** dout2_mode : R/W; bitpos: [2]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout2_mode:1;
-        /** dout3_mode : R/W; bitpos: [3]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout3_mode:1;
-        /** dout4_mode : R/W; bitpos: [4]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout4_mode:1;  //this field is only for GPSPI2
-        /** dout5_mode : R/W; bitpos: [5]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout5_mode:1;  //this field is only for GPSPI2
-        /** dout6_mode : R/W; bitpos: [6]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout6_mode:1;  //this field is only for GPSPI2
-        /** dout7_mode : R/W; bitpos: [7]; default: 0;
-         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
-         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t dout7_mode:1;  //this field is only for GPSPI2
-        /** d_dqs_mode : R/W; bitpos: [8]; default: 0;
-         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
-         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
-         *  configured in CONF state.
-         */
-        uint32_t d_dqs_mode:1;  //this field is only for GPSPI2
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} spi_dout_mode_reg_t;
-
-/** Type of dma_int register
- *  SPI interrupt raw/ena/clr/sta/set register
- */
-typedef union {
-    struct {
-        /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
-         *  receive data.  0: Others.
-         */
-        uint32_t dma_infifo_full_err_int:1;
-        /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
-         *  master mode and send out all 0 in slave mode.  0: Others.
-         */
-        uint32_t dma_outfifo_empty_err_int:1;
-        /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_ex_qpi_int:1;
-        /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
-         *  is ended. 0: Others.
-         */
-        uint32_t slv_en_qpi_int:1;
-        /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd7_int:1;
-        /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd8_int:1;
-        /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmd9_int:1;
-        /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
-         *  ended. 0: Others.
-         */
-        uint32_t slv_cmda_int:1;
-        /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_dma_done_int:1;
-        /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_dma_done_int:1;
-        /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_rd_buf_done_int:1;
-        /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
-         *  transmission is ended. 0: Others.
-         */
-        uint32_t slv_wr_buf_done_int:1;
-        /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
-         *  ended. 0: others.
-         */
-        uint32_t trans_done_int:1;
-        /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
-         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
-         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
-         *  is not ended or not occurred.
-         */
-        uint32_t dma_seg_trans_done_int:1;
-        /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
-         *  is error in the DMA seg-conf-trans. 0: others.
-         */
-        uint32_t seg_magic_err_int_raw:1;  //this field is only forPI2
-        /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
-         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
-         *  bigger than 63. 0: Others.
-         */
-        uint32_t slv_buf_addr_err_int:1;
-        /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
-         *  current SPI slave HD mode transmission is not supported. 0: Others.
-         */
-        uint32_t slv_cmd_err_int:1;
-        /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
-         *  write-full error when SPI inputs data in master mode. 0: Others.
-         */
-        uint32_t mst_rx_afifo_wfull_err_int:1;
-        /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-         */
-        uint32_t mst_tx_afifo_rempty_err_int:1;
-        /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app2_int:1;
-        /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
-         */
-        uint32_t app1_int:1;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} spi_dma_int_reg_t;
-
-/** Type of wn register
- *  SPI CPU-controlled buffer
- */
-typedef union {
-    struct {
-        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf:32;
-    };
-    uint32_t val;
-} spi_wn_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version control
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 35680770;
-         *  SPI register version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} spi_date_reg_t;
-
-
-typedef struct {
-    volatile spi_cmd_reg_t cmd;
-    volatile spi_addr_reg_t addr;
-    volatile spi_ctrl_reg_t ctrl;
-    volatile spi_clock_reg_t clock;
-    volatile spi_user_reg_t user;
-    volatile spi_user1_reg_t user1;
-    volatile spi_user2_reg_t user2;
-    volatile spi_ms_dlen_reg_t ms_dlen;
-    volatile spi_misc_reg_t misc;
-    volatile spi_din_mode_reg_t din_mode;
-    volatile spi_din_num_reg_t din_num;
-    volatile spi_dout_mode_reg_t dout_mode;
-    volatile spi_dma_conf_reg_t dma_conf;
-    volatile spi_dma_int_reg_t dma_int_ena;
-    volatile spi_dma_int_reg_t dma_int_clr;
-    volatile spi_dma_int_reg_t dma_int_raw;
-    volatile spi_dma_int_reg_t dma_int_sta;
-    volatile spi_dma_int_reg_t dma_int_set;
-    uint32_t reserved_048[20];
-    volatile spi_wn_reg_t data_buf[16];
-    uint32_t reserved_0d8[2];
-    volatile spi_slave_reg_t slave;
-    volatile spi_slave1_reg_t slave1;
-    volatile spi_clk_gate_reg_t clk_gate;
-    uint32_t reserved_0ec;
-    volatile spi_date_reg_t date;
-} spi_dev_t;
-
-extern spi_dev_t GPSPI2;
-extern spi_dev_t GPSPI3;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/uart_reg.h b/components/soc/esp32p4/include/soc/uart_reg.h
deleted file mode 100644
index fc3c662721e..00000000000
--- a/components/soc/esp32p4/include/soc/uart_reg.h
+++ /dev/null
@@ -1,1579 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** UART_FIFO_REG register
- *  FIFO data register
- */
-#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
-/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
- *  UART $n accesses FIFO via this register.
- */
-#define UART_RXFIFO_RD_BYTE    0x000000FFU
-#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
-#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
-#define UART_RXFIFO_RD_BYTE_S  0
-
-/** UART_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
-/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  what rxfifo_full_thrhd specifies.
- */
-#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
-#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_RAW_S  0
-/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
- *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- *  less than what txfifo_empty_thrhd specifies .
- */
-#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error in
- *  the data.
- */
-#define UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
-#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_PARITY_ERR_INT_RAW_S  2
-/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  .
- */
-#define UART_FRM_ERR_INT_RAW    (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
-#define UART_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_FRM_ERR_INT_RAW_S  3
-/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  the FIFO can store.
- */
-#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
-#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  DSRn signal.
- */
-#define UART_DSR_CHG_INT_RAW    (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
-#define UART_DSR_CHG_INT_RAW_V  0x00000001U
-#define UART_DSR_CHG_INT_RAW_S  5
-/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  CTSn signal.
- */
-#define UART_CTS_CHG_INT_RAW    (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
-#define UART_CTS_CHG_INT_RAW_V  0x00000001U
-#define UART_CTS_CHG_INT_RAW_S  6
-/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
- *  bit.
- */
-#define UART_BRK_DET_INT_RAW    (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
-#define UART_BRK_DET_INT_RAW_V  0x00000001U
-#define UART_BRK_DET_INT_RAW_S  7
-/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  This interrupt raw bit turns to high level when receiver takes more time than
- *  rx_tout_thrhd to receive a byte.
- */
-#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XON_INT_RAW    (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
-#define UART_SW_XON_INT_RAW_V  0x00000001U
-#define UART_SW_XON_INT_RAW_S  9
-/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives Xoff char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XOFF_INT_RAW    (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
-#define UART_SW_XOFF_INT_RAW_V  0x00000001U
-#define UART_SW_XOFF_INT_RAW_S  10
-/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a glitch in the
- *  middle of a start bit.
- */
-#define UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
-#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
-#define UART_GLITCH_DET_INT_RAW_S  11
-/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter completes  sending
- *  NULL characters after all data in Tx-FIFO are sent.
- */
-#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
-#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has kept the shortest
- *  duration after sending the  last data.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has send out all data
- *  in FIFO.
- */
-#define UART_TX_DONE_INT_RAW    (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
-#define UART_TX_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_DONE_INT_RAW_S  14
-/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  This interrupt raw bit turns to high level when detects a clash between transmitter
- *  and receiver in rs485 mode.
- */
-#define UART_RS485_CLASH_INT_RAW    (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
-#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
-#define UART_RS485_CLASH_INT_RAW_S  17
-/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the configured
- *  at_cmd char.
- */
-#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  This interrupt raw bit turns to high level when input rxd edge changes more times
- *  than what reg_active_threshold specifies in light sleeping mode.
- */
-#define UART_WAKEUP_INT_RAW    (BIT(19))
-#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
-#define UART_WAKEUP_INT_RAW_V  0x00000001U
-#define UART_WAKEUP_INT_RAW_S  19
-
-/** UART_INT_ST_REG register
- *  Masked interrupt status
- */
-#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
-/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
- *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
- */
-#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
-#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ST_S  0
-/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
- *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
- *  to 1.
- */
-#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
- *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
- */
-#define UART_PARITY_ERR_INT_ST    (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
-#define UART_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_PARITY_ERR_INT_ST_S  2
-/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
- *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
- */
-#define UART_FRM_ERR_INT_ST    (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
-#define UART_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_FRM_ERR_INT_ST_S  3
-/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
- */
-#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
-#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
- */
-#define UART_DSR_CHG_INT_ST    (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
-#define UART_DSR_CHG_INT_ST_V  0x00000001U
-#define UART_DSR_CHG_INT_ST_S  5
-/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
- *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
- */
-#define UART_CTS_CHG_INT_ST    (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
-#define UART_CTS_CHG_INT_ST_V  0x00000001U
-#define UART_CTS_CHG_INT_ST_S  6
-/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
- *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
- */
-#define UART_BRK_DET_INT_ST    (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
-#define UART_BRK_DET_INT_ST_V  0x00000001U
-#define UART_BRK_DET_INT_ST_S  7
-/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
- */
-#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
-#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
- *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
- */
-#define UART_SW_XON_INT_ST    (BIT(9))
-#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
-#define UART_SW_XON_INT_ST_V  0x00000001U
-#define UART_SW_XON_INT_ST_S  9
-/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
- *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
- */
-#define UART_SW_XOFF_INT_ST    (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
-#define UART_SW_XOFF_INT_ST_V  0x00000001U
-#define UART_SW_XOFF_INT_ST_S  10
-/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
- *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
- */
-#define UART_GLITCH_DET_INT_ST    (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
-#define UART_GLITCH_DET_INT_ST_V  0x00000001U
-#define UART_GLITCH_DET_INT_ST_S  11
-/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
- */
-#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
-#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- *  is set to 1.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
- */
-#define UART_TX_DONE_INT_ST    (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
-#define UART_TX_DONE_INT_ST_V  0x00000001U
-#define UART_TX_DONE_INT_ST_S  14
-/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
- *  set to 1.
- */
-#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
- *  to 1.
- */
-#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
-#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
- *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
- */
-#define UART_RS485_CLASH_INT_ST    (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
-#define UART_RS485_CLASH_INT_ST_V  0x00000001U
-#define UART_RS485_CLASH_INT_ST_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
- *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
- *  to 1.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
- *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
- */
-#define UART_WAKEUP_INT_ST    (BIT(19))
-#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
-#define UART_WAKEUP_INT_ST_V  0x00000001U
-#define UART_WAKEUP_INT_ST_S  19
-
-/** UART_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
-/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  This is the enable bit for rxfifo_full_int_st register.
- */
-#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
-#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ENA_S  0
-/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  This is the enable bit for txfifo_empty_int_st register.
- */
-#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  This is the enable bit for parity_err_int_st register.
- */
-#define UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
-#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_PARITY_ERR_INT_ENA_S  2
-/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  This is the enable bit for frm_err_int_st register.
- */
-#define UART_FRM_ERR_INT_ENA    (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
-#define UART_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_FRM_ERR_INT_ENA_S  3
-/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  This is the enable bit for rxfifo_ovf_int_st register.
- */
-#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
-#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for dsr_chg_int_st register.
- */
-#define UART_DSR_CHG_INT_ENA    (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
-#define UART_DSR_CHG_INT_ENA_V  0x00000001U
-#define UART_DSR_CHG_INT_ENA_S  5
-/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  This is the enable bit for cts_chg_int_st register.
- */
-#define UART_CTS_CHG_INT_ENA    (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
-#define UART_CTS_CHG_INT_ENA_V  0x00000001U
-#define UART_CTS_CHG_INT_ENA_S  6
-/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  This is the enable bit for brk_det_int_st register.
- */
-#define UART_BRK_DET_INT_ENA    (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
-#define UART_BRK_DET_INT_ENA_V  0x00000001U
-#define UART_BRK_DET_INT_ENA_S  7
-/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  This is the enable bit for rxfifo_tout_int_st register.
- */
-#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  This is the enable bit for sw_xon_int_st register.
- */
-#define UART_SW_XON_INT_ENA    (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
-#define UART_SW_XON_INT_ENA_V  0x00000001U
-#define UART_SW_XON_INT_ENA_S  9
-/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  This is the enable bit for sw_xoff_int_st register.
- */
-#define UART_SW_XOFF_INT_ENA    (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
-#define UART_SW_XOFF_INT_ENA_V  0x00000001U
-#define UART_SW_XOFF_INT_ENA_S  10
-/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  This is the enable bit for glitch_det_int_st register.
- */
-#define UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
-#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
-#define UART_GLITCH_DET_INT_ENA_S  11
-/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for tx_brk_done_int_st register.
- */
-#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
-#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit for tx_brk_idle_done_int_st register.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for tx_done_int_st register.
- */
-#define UART_TX_DONE_INT_ENA    (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
-#define UART_TX_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_DONE_INT_ENA_S  14
-/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  This is the enable bit for rs485_clash_int_st register.
- */
-#define UART_RS485_CLASH_INT_ENA    (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
-#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
-#define UART_RS485_CLASH_INT_ENA_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  This is the enable bit for at_cmd_char_det_int_st register.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for uart_wakeup_int_st register.
- */
-#define UART_WAKEUP_INT_ENA    (BIT(19))
-#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
-#define UART_WAKEUP_INT_ENA_V  0x00000001U
-#define UART_WAKEUP_INT_ENA_S  19
-
-/** UART_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
-/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the rxfifo_full_int_raw interrupt.
- */
-#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
-#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_CLR_S  0
-/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear txfifo_empty_int_raw interrupt.
- */
-#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear parity_err_int_raw interrupt.
- */
-#define UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
-#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_PARITY_ERR_INT_CLR_S  2
-/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear frm_err_int_raw interrupt.
- */
-#define UART_FRM_ERR_INT_CLR    (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
-#define UART_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_FRM_ERR_INT_CLR_S  3
-/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
- */
-#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
-#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the dsr_chg_int_raw interrupt.
- */
-#define UART_DSR_CHG_INT_CLR    (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
-#define UART_DSR_CHG_INT_CLR_V  0x00000001U
-#define UART_DSR_CHG_INT_CLR_S  5
-/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the cts_chg_int_raw interrupt.
- */
-#define UART_CTS_CHG_INT_CLR    (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
-#define UART_CTS_CHG_INT_CLR_V  0x00000001U
-#define UART_CTS_CHG_INT_CLR_S  6
-/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the brk_det_int_raw interrupt.
- */
-#define UART_BRK_DET_INT_CLR    (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
-#define UART_BRK_DET_INT_CLR_V  0x00000001U
-#define UART_BRK_DET_INT_CLR_S  7
-/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
- */
-#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the sw_xon_int_raw interrupt.
- */
-#define UART_SW_XON_INT_CLR    (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
-#define UART_SW_XON_INT_CLR_V  0x00000001U
-#define UART_SW_XON_INT_CLR_S  9
-/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the sw_xoff_int_raw interrupt.
- */
-#define UART_SW_XOFF_INT_CLR    (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
-#define UART_SW_XOFF_INT_CLR_V  0x00000001U
-#define UART_SW_XOFF_INT_CLR_S  10
-/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the glitch_det_int_raw interrupt.
- */
-#define UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
-#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
-#define UART_GLITCH_DET_INT_CLR_S  11
-/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the tx_brk_done_int_raw interrupt..
- */
-#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
-#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the tx_done_int_raw interrupt.
- */
-#define UART_TX_DONE_INT_CLR    (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
-#define UART_TX_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_DONE_INT_CLR_S  14
-/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
- */
-#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
- */
-#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit to clear the rs485_clash_int_raw interrupt.
- */
-#define UART_RS485_CLASH_INT_CLR    (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
-#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
-#define UART_RS485_CLASH_INT_CLR_S  17
-/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
- */
-#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the uart_wakeup_int_raw interrupt.
- */
-#define UART_WAKEUP_INT_CLR    (BIT(19))
-#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
-#define UART_WAKEUP_INT_CLR_V  0x00000001U
-#define UART_WAKEUP_INT_CLR_S  19
-
-/** UART_CLKDIV_SYNC_REG register
- *  Clock divider configuration
- */
-#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
-/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
- *  The integral part of the frequency divider factor.
- */
-#define UART_CLKDIV    0x00000FFFU
-#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
-#define UART_CLKDIV_V  0x00000FFFU
-#define UART_CLKDIV_S  0
-/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
- *  The decimal part of the frequency divider factor.
- */
-#define UART_CLKDIV_FRAG    0x0000000FU
-#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
-#define UART_CLKDIV_FRAG_V  0x0000000FU
-#define UART_CLKDIV_FRAG_S  20
-
-/** UART_RX_FILT_REG register
- *  Rx Filter configuration
- */
-#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
-/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
- *  when input pulse width is lower than this value the pulse is ignored.
- */
-#define UART_GLITCH_FILT    0x000000FFU
-#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
-#define UART_GLITCH_FILT_V  0x000000FFU
-#define UART_GLITCH_FILT_S  0
-/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable Rx signal filter.
- */
-#define UART_GLITCH_FILT_EN    (BIT(8))
-#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
-#define UART_GLITCH_FILT_EN_V  0x00000001U
-#define UART_GLITCH_FILT_EN_S  8
-
-/** UART_STATUS_REG register
- *  UART status register
- */
-#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
-/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
- *  Stores the byte number of valid data in Rx-FIFO.
- */
-#define UART_RXFIFO_CNT    0x000000FFU
-#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
-#define UART_RXFIFO_CNT_V  0x000000FFU
-#define UART_RXFIFO_CNT_S  0
-/** UART_DSRN : RO; bitpos: [13]; default: 0;
- *  The register represent the level value of the internal uart dsr signal.
- */
-#define UART_DSRN    (BIT(13))
-#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
-#define UART_DSRN_V  0x00000001U
-#define UART_DSRN_S  13
-/** UART_CTSN : RO; bitpos: [14]; default: 1;
- *  This register represent the level value of the internal uart cts signal.
- */
-#define UART_CTSN    (BIT(14))
-#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
-#define UART_CTSN_V  0x00000001U
-#define UART_CTSN_S  14
-/** UART_RXD : RO; bitpos: [15]; default: 1;
- *  This register represent the  level value of the internal uart rxd signal.
- */
-#define UART_RXD    (BIT(15))
-#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
-#define UART_RXD_V  0x00000001U
-#define UART_RXD_S  15
-/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
- *  Stores the byte number of data in Tx-FIFO.
- */
-#define UART_TXFIFO_CNT    0x000000FFU
-#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
-#define UART_TXFIFO_CNT_V  0x000000FFU
-#define UART_TXFIFO_CNT_S  16
-/** UART_DTRN : RO; bitpos: [29]; default: 1;
- *  This bit represents the level of the internal uart dtr signal.
- */
-#define UART_DTRN    (BIT(29))
-#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
-#define UART_DTRN_V  0x00000001U
-#define UART_DTRN_S  29
-/** UART_RTSN : RO; bitpos: [30]; default: 1;
- *  This bit represents the level of the internal uart rts signal.
- */
-#define UART_RTSN    (BIT(30))
-#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
-#define UART_RTSN_V  0x00000001U
-#define UART_RTSN_S  30
-/** UART_TXD : RO; bitpos: [31]; default: 1;
- *  This bit represents the  level of the internal uart txd signal.
- */
-#define UART_TXD    (BIT(31))
-#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
-#define UART_TXD_V  0x00000001U
-#define UART_TXD_S  31
-
-/** UART_CONF0_SYNC_REG register
- *  a
- */
-#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
-/** UART_PARITY : R/W; bitpos: [0]; default: 0;
- *  This register is used to configure the parity check mode.
- */
-#define UART_PARITY    (BIT(0))
-#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
-#define UART_PARITY_V  0x00000001U
-#define UART_PARITY_S  0
-/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable uart parity check.
- */
-#define UART_PARITY_EN    (BIT(1))
-#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
-#define UART_PARITY_EN_V  0x00000001U
-#define UART_PARITY_EN_S  1
-/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
- *  This register is used to set the length of data.
- */
-#define UART_BIT_NUM    0x00000003U
-#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
-#define UART_BIT_NUM_V  0x00000003U
-#define UART_BIT_NUM_S  2
-/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
- *  This register is used to set the length of  stop bit.
- */
-#define UART_STOP_BIT_NUM    0x00000003U
-#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
-#define UART_STOP_BIT_NUM_V  0x00000003U
-#define UART_STOP_BIT_NUM_S  4
-/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
- *  is done.
- */
-#define UART_TXD_BRK    (BIT(6))
-#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
-#define UART_TXD_BRK_V  0x00000001U
-#define UART_TXD_BRK_S  6
-/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
- *  Set this bit to enable IrDA loopback mode.
- */
-#define UART_IRDA_DPLX    (BIT(7))
-#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
-#define UART_IRDA_DPLX_V  0x00000001U
-#define UART_IRDA_DPLX_S  7
-/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
- *  This is the start enable bit for IrDA transmitter.
- */
-#define UART_IRDA_TX_EN    (BIT(8))
-#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
-#define UART_IRDA_TX_EN_V  0x00000001U
-#define UART_IRDA_TX_EN_S  8
-/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
- *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
- *  transmitter's 11th bit to 0.
- */
-#define UART_IRDA_WCTL    (BIT(9))
-#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
-#define UART_IRDA_WCTL_V  0x00000001U
-#define UART_IRDA_WCTL_S  9
-/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
- *  Set this bit to invert the level of  IrDA transmitter.
- */
-#define UART_IRDA_TX_INV    (BIT(10))
-#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
-#define UART_IRDA_TX_INV_V  0x00000001U
-#define UART_IRDA_TX_INV_S  10
-/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
- *  Set this bit to invert the level of IrDA receiver.
- */
-#define UART_IRDA_RX_INV    (BIT(11))
-#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
-#define UART_IRDA_RX_INV_V  0x00000001U
-#define UART_IRDA_RX_INV_S  11
-/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
- *  Set this bit to enable uart loopback test mode.
- */
-#define UART_LOOPBACK    (BIT(12))
-#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
-#define UART_LOOPBACK_V  0x00000001U
-#define UART_LOOPBACK_S  12
-/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
- *  Set this bit to enable flow control function for transmitter.
- */
-#define UART_TX_FLOW_EN    (BIT(13))
-#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
-#define UART_TX_FLOW_EN_V  0x00000001U
-#define UART_TX_FLOW_EN_S  13
-/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
- *  Set this bit to enable IrDA protocol.
- */
-#define UART_IRDA_EN    (BIT(14))
-#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
-#define UART_IRDA_EN_V  0x00000001U
-#define UART_IRDA_EN_S  14
-/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
- *  Set this bit to inverse the level value of uart rxd signal.
- */
-#define UART_RXD_INV    (BIT(15))
-#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
-#define UART_RXD_INV_V  0x00000001U
-#define UART_RXD_INV_S  15
-/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart txd signal.
- */
-#define UART_TXD_INV    (BIT(16))
-#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
-#define UART_TXD_INV_V  0x00000001U
-#define UART_TXD_INV_S  16
-/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
- *  Disable UART Rx data overflow detect.
- */
-#define UART_DIS_RX_DAT_OVF    (BIT(17))
-#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
-#define UART_DIS_RX_DAT_OVF_V  0x00000001U
-#define UART_DIS_RX_DAT_OVF_S  17
-/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
- *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
- *  stores the data even if the  received data is wrong.
- */
-#define UART_ERR_WR_MASK    (BIT(18))
-#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
-#define UART_ERR_WR_MASK_V  0x00000001U
-#define UART_ERR_WR_MASK_S  18
-/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for detecting baudrate.
- */
-#define UART_AUTOBAUD_EN    (BIT(19))
-#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
-#define UART_AUTOBAUD_EN_V  0x00000001U
-#define UART_AUTOBAUD_EN_S  19
-/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
- *  UART memory clock gate enable signal.
- */
-#define UART_MEM_CLK_EN    (BIT(20))
-#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
-#define UART_MEM_CLK_EN_V  0x00000001U
-#define UART_MEM_CLK_EN_S  20
-/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
- *  This register is used to configure the software rts signal which is used in
- *  software flow control.
- */
-#define UART_SW_RTS    (BIT(21))
-#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
-#define UART_SW_RTS_V  0x00000001U
-#define UART_SW_RTS_S  21
-/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
- *  Set this bit to reset the uart receive-FIFO.
- */
-#define UART_RXFIFO_RST    (BIT(22))
-#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
-#define UART_RXFIFO_RST_V  0x00000001U
-#define UART_RXFIFO_RST_S  22
-/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
- *  Set this bit to reset the uart transmit-FIFO.
- */
-#define UART_TXFIFO_RST    (BIT(23))
-#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
-#define UART_TXFIFO_RST_V  0x00000001U
-#define UART_TXFIFO_RST_S  23
-
-/** UART_CONF1_REG register
- *  Configuration register 1
- */
-#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
-/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
- *  It will produce rxfifo_full_int interrupt when receiver receives more data than
- *  this register value.
- */
-#define UART_RXFIFO_FULL_THRHD    0x000000FFU
-#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
-#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
-#define UART_RXFIFO_FULL_THRHD_S  0
-/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
- *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
- *  than this register value.
- */
-#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
-#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
-#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
-#define UART_TXFIFO_EMPTY_THRHD_S  8
-/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
- *  Set this bit to inverse the level value of uart cts signal.
- */
-#define UART_CTS_INV    (BIT(16))
-#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
-#define UART_CTS_INV_V  0x00000001U
-#define UART_CTS_INV_S  16
-/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
- *  Set this bit to inverse the level value of uart dsr signal.
- */
-#define UART_DSR_INV    (BIT(17))
-#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
-#define UART_DSR_INV_V  0x00000001U
-#define UART_DSR_INV_S  17
-/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
- *  Set this bit to inverse the level value of uart rts signal.
- */
-#define UART_RTS_INV    (BIT(18))
-#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
-#define UART_RTS_INV_V  0x00000001U
-#define UART_RTS_INV_S  18
-/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
- *  Set this bit to inverse the level value of uart dtr signal.
- */
-#define UART_DTR_INV    (BIT(19))
-#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
-#define UART_DTR_INV_V  0x00000001U
-#define UART_DTR_INV_S  19
-/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
- *  This register is used to configure the software dtr signal which is used in
- *  software flow control.
- */
-#define UART_SW_DTR    (BIT(20))
-#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
-#define UART_SW_DTR_V  0x00000001U
-#define UART_SW_DTR_S  20
-/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define UART_CLK_EN    (BIT(21))
-#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
-#define UART_CLK_EN_V  0x00000001U
-#define UART_CLK_EN_S  21
-
-/** UART_HWFC_CONF_SYNC_REG register
- *  Hardware flow-control configuration
- */
-#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
-/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
- *  This register is used to configure the maximum amount of data that can be received
- *  when hardware flow control works.
- */
-#define UART_RX_FLOW_THRHD    0x000000FFU
-#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
-#define UART_RX_FLOW_THRHD_V  0x000000FFU
-#define UART_RX_FLOW_THRHD_S  0
-/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
- *  This is the flow enable bit for UART receiver.
- */
-#define UART_RX_FLOW_EN    (BIT(8))
-#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
-#define UART_RX_FLOW_EN_V  0x00000001U
-#define UART_RX_FLOW_EN_S  8
-
-/** UART_SLEEP_CONF0_REG register
- *  UART sleep configure register 0
- */
-#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
-/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified wake up char1 to wake up
- */
-#define UART_WK_CHAR1    0x000000FFU
-#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
-#define UART_WK_CHAR1_V  0x000000FFU
-#define UART_WK_CHAR1_S  0
-/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
- *  This register restores the specified wake up char2 to wake up
- */
-#define UART_WK_CHAR2    0x000000FFU
-#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
-#define UART_WK_CHAR2_V  0x000000FFU
-#define UART_WK_CHAR2_S  8
-/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
- *  This register restores the specified wake up char3 to wake up
- */
-#define UART_WK_CHAR3    0x000000FFU
-#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
-#define UART_WK_CHAR3_V  0x000000FFU
-#define UART_WK_CHAR3_S  16
-/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
- *  This register restores the specified wake up char4 to wake up
- */
-#define UART_WK_CHAR4    0x000000FFU
-#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
-#define UART_WK_CHAR4_V  0x000000FFU
-#define UART_WK_CHAR4_S  24
-
-/** UART_SLEEP_CONF1_REG register
- *  UART sleep configure register 1
- */
-#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
-/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
- *  This register restores the specified char0 to wake up
- */
-#define UART_WK_CHAR0    0x000000FFU
-#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
-#define UART_WK_CHAR0_V  0x000000FFU
-#define UART_WK_CHAR0_S  0
-
-/** UART_SLEEP_CONF2_REG register
- *  UART sleep configure register 2
- */
-#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
-/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
- *  The uart is activated from light sleeping mode when the input rxd edge changes more
- *  times than this register value.
- */
-#define UART_ACTIVE_THRESHOLD    0x000003FFU
-#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
-#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
-#define UART_ACTIVE_THRESHOLD_S  0
-/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
- *  In wake up mode 1 this field is used to set the received data number threshold to
- *  wake up chip.
- */
-#define UART_RX_WAKE_UP_THRHD    0x000000FFU
-#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
-#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
-#define UART_RX_WAKE_UP_THRHD_S  10
-/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
- *  This register is used to select number of wake up char.
- */
-#define UART_WK_CHAR_NUM    0x00000007U
-#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
-#define UART_WK_CHAR_NUM_V  0x00000007U
-#define UART_WK_CHAR_NUM_S  18
-/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
- *  This register is used to mask  wake up char.
- */
-#define UART_WK_CHAR_MASK    0x0000001FU
-#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
-#define UART_WK_CHAR_MASK_V  0x0000001FU
-#define UART_WK_CHAR_MASK_S  21
-/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
- *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
- *  received data number larger than
- */
-#define UART_WK_MODE_SEL    0x00000003U
-#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
-#define UART_WK_MODE_SEL_V  0x00000003U
-#define UART_WK_MODE_SEL_S  26
-
-/** UART_SWFC_CONF0_SYNC_REG register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
-/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
- *  This register stores the Xon flow control char.
- */
-#define UART_XON_CHAR    0x000000FFU
-#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
-#define UART_XON_CHAR_V  0x000000FFU
-#define UART_XON_CHAR_S  0
-/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
- *  This register stores the Xoff flow control char.
- */
-#define UART_XOFF_CHAR    0x000000FFU
-#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
-#define UART_XOFF_CHAR_V  0x000000FFU
-#define UART_XOFF_CHAR_S  8
-/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
- *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
- *  this status, UART Tx can not transmit XOFF even the received data number is larger
- *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
- *  UART Tx is disabled.
- */
-#define UART_XON_XOFF_STILL_SEND    (BIT(16))
-#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
-#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
-#define UART_XON_XOFF_STILL_SEND_S  16
-/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
- *  Set this bit to enable software flow control. It is used with register sw_xon or
- *  sw_xoff.
- */
-#define UART_SW_FLOW_CON_EN    (BIT(17))
-#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
-#define UART_SW_FLOW_CON_EN_V  0x00000001U
-#define UART_SW_FLOW_CON_EN_S  17
-/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
- *  Set this bit to remove flow control char from the received data.
- */
-#define UART_XONOFF_DEL    (BIT(18))
-#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
-#define UART_XONOFF_DEL_V  0x00000001U
-#define UART_XONOFF_DEL_S  18
-/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
- *  Set this bit to enable the transmitter to go on sending data.
- */
-#define UART_FORCE_XON    (BIT(19))
-#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
-#define UART_FORCE_XON_V  0x00000001U
-#define UART_FORCE_XON_S  19
-/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
- *  Set this bit to stop the  transmitter from sending data.
- */
-#define UART_FORCE_XOFF    (BIT(20))
-#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
-#define UART_FORCE_XOFF_V  0x00000001U
-#define UART_FORCE_XOFF_S  20
-/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
- *  Set this bit to send Xon char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XON    (BIT(21))
-#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
-#define UART_SEND_XON_V  0x00000001U
-#define UART_SEND_XON_S  21
-/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
- *  Set this bit to send Xoff char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XOFF    (BIT(22))
-#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
-#define UART_SEND_XOFF_V  0x00000001U
-#define UART_SEND_XOFF_S  22
-
-/** UART_SWFC_CONF1_REG register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
-/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
- *  When the data amount in Rx-FIFO is less than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xon char.
- */
-#define UART_XON_THRESHOLD    0x000000FFU
-#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
-#define UART_XON_THRESHOLD_V  0x000000FFU
-#define UART_XON_THRESHOLD_S  0
-/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
- *  When the data amount in Rx-FIFO is more than this register value with
- *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
- */
-#define UART_XOFF_THRESHOLD    0x000000FFU
-#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
-#define UART_XOFF_THRESHOLD_V  0x000000FFU
-#define UART_XOFF_THRESHOLD_S  8
-
-/** UART_TXBRK_CONF_SYNC_REG register
- *  Tx Break character configuration
- */
-#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
-/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
- *  This register is used to configure the number of 0 to be sent after the process of
- *  sending data is done. It is active when txd_brk is set to 1.
- */
-#define UART_TX_BRK_NUM    0x000000FFU
-#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
-#define UART_TX_BRK_NUM_V  0x000000FFU
-#define UART_TX_BRK_NUM_S  0
-
-/** UART_IDLE_CONF_SYNC_REG register
- *  Frame-end idle configuration
- */
-#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
-/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
- *  It will produce frame end signal when receiver takes more time to receive one byte
- *  data than this register value.
- */
-#define UART_RX_IDLE_THRHD    0x000003FFU
-#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
-#define UART_RX_IDLE_THRHD_V  0x000003FFU
-#define UART_RX_IDLE_THRHD_S  0
-/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
- *  This register is used to configure the duration time between transfers.
- */
-#define UART_TX_IDLE_NUM    0x000003FFU
-#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
-#define UART_TX_IDLE_NUM_V  0x000003FFU
-#define UART_TX_IDLE_NUM_S  10
-
-/** UART_RS485_CONF_SYNC_REG register
- *  RS485 mode configuration
- */
-#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
-/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to choose the rs485 mode.
- */
-#define UART_RS485_EN    (BIT(0))
-#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
-#define UART_RS485_EN_V  0x00000001U
-#define UART_RS485_EN_S  0
-/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL0_EN    (BIT(1))
-#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
-#define UART_DL0_EN_V  0x00000001U
-#define UART_DL0_EN_S  1
-/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL1_EN    (BIT(2))
-#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
-#define UART_DL1_EN_V  0x00000001U
-#define UART_DL1_EN_S  2
-/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable receiver could receive data when the transmitter is
- *  transmitting data in rs485 mode.
- */
-#define UART_RS485TX_RX_EN    (BIT(3))
-#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
-#define UART_RS485TX_RX_EN_V  0x00000001U
-#define UART_RS485TX_RX_EN_S  3
-/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
- *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
- */
-#define UART_RS485RXBY_TX_EN    (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
-#define UART_RS485RXBY_TX_EN_V  0x00000001U
-#define UART_RS485RXBY_TX_EN_S  4
-/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
- *  This register is used to delay the receiver's internal data signal.
- */
-#define UART_RS485_RX_DLY_NUM    (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
-#define UART_RS485_RX_DLY_NUM_V  0x00000001U
-#define UART_RS485_RX_DLY_NUM_S  5
-/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
- *  This register is used to delay the transmitter's internal data signal.
- */
-#define UART_RS485_TX_DLY_NUM    0x0000000FU
-#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
-#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
-#define UART_RS485_TX_DLY_NUM_S  6
-
-/** UART_AT_CMD_PRECNT_SYNC_REG register
- *  Pre-sequence timing configuration
- */
-#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
-/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the idle duration time before the first at_cmd
- *  is received by receiver.
- */
-#define UART_PRE_IDLE_NUM    0x0000FFFFU
-#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
-#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
-#define UART_PRE_IDLE_NUM_S  0
-
-/** UART_AT_CMD_POSTCNT_SYNC_REG register
- *  Post-sequence timing configuration
- */
-#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
-/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the duration time between the last at_cmd and
- *  the next data.
- */
-#define UART_POST_IDLE_NUM    0x0000FFFFU
-#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
-#define UART_POST_IDLE_NUM_V  0x0000FFFFU
-#define UART_POST_IDLE_NUM_S  0
-
-/** UART_AT_CMD_GAPTOUT_SYNC_REG register
- *  Timeout configuration
- */
-#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
-/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
- *  This register is used to configure the duration time between the at_cmd chars.
- */
-#define UART_RX_GAP_TOUT    0x0000FFFFU
-#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
-#define UART_RX_GAP_TOUT_V  0x0000FFFFU
-#define UART_RX_GAP_TOUT_S  0
-
-/** UART_AT_CMD_CHAR_SYNC_REG register
- *  AT escape sequence detection configuration
- */
-#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
-/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
- *  This register is used to configure the content of at_cmd char.
- */
-#define UART_AT_CMD_CHAR    0x000000FFU
-#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
-#define UART_AT_CMD_CHAR_V  0x000000FFU
-#define UART_AT_CMD_CHAR_S  0
-/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
- *  This register is used to configure the num of continuous at_cmd chars received by
- *  receiver.
- */
-#define UART_CHAR_NUM    0x000000FFU
-#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
-#define UART_CHAR_NUM_V  0x000000FFU
-#define UART_CHAR_NUM_S  8
-
-/** UART_MEM_CONF_REG register
- *  UART memory power configuration
- */
-#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
-/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
- *  Set this bit to force power down UART memory.
- */
-#define UART_MEM_FORCE_PD    (BIT(25))
-#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
-#define UART_MEM_FORCE_PD_V  0x00000001U
-#define UART_MEM_FORCE_PD_S  25
-/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
- *  Set this bit to force power up UART memory.
- */
-#define UART_MEM_FORCE_PU    (BIT(26))
-#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
-#define UART_MEM_FORCE_PU_V  0x00000001U
-#define UART_MEM_FORCE_PU_S  26
-
-/** UART_TOUT_CONF_SYNC_REG register
- *  UART threshold and allocation configuration
- */
-#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
-/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
- */
-#define UART_RX_TOUT_EN    (BIT(0))
-#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
-#define UART_RX_TOUT_EN_V  0x00000001U
-#define UART_RX_TOUT_EN_S  0
-/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
- *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
- */
-#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
-#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
-#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
-#define UART_RX_TOUT_FLOW_DIS_S  1
-/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
- *  This register is used to configure the threshold time that receiver takes to
- *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
- *  takes more time to receive one byte with rx_tout_en set to 1.
- */
-#define UART_RX_TOUT_THRHD    0x000003FFU
-#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
-#define UART_RX_TOUT_THRHD_V  0x000003FFU
-#define UART_RX_TOUT_THRHD_S  2
-
-/** UART_MEM_TX_STATUS_REG register
- *  Tx-SRAM write and read offset address.
- */
-#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
-/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
- *  This register stores the offset write address in Tx-SRAM.
- */
-#define UART_TX_SRAM_WADDR    0x000000FFU
-#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
-#define UART_TX_SRAM_WADDR_V  0x000000FFU
-#define UART_TX_SRAM_WADDR_S  0
-/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
- *  This register stores the offset read address in Tx-SRAM.
- */
-#define UART_TX_SRAM_RADDR    0x000000FFU
-#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
-#define UART_TX_SRAM_RADDR_V  0x000000FFU
-#define UART_TX_SRAM_RADDR_S  9
-
-/** UART_MEM_RX_STATUS_REG register
- *  Rx-SRAM write and read offset address.
- */
-#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
-/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
- *  This register stores the offset read address in RX-SRAM.
- */
-#define UART_RX_SRAM_RADDR    0x000000FFU
-#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
-#define UART_RX_SRAM_RADDR_V  0x000000FFU
-#define UART_RX_SRAM_RADDR_S  0
-/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
- *  This register stores the offset write address in Rx-SRAM.
- */
-#define UART_RX_SRAM_WADDR    0x000000FFU
-#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
-#define UART_RX_SRAM_WADDR_V  0x000000FFU
-#define UART_RX_SRAM_WADDR_S  9
-
-/** UART_FSM_STATUS_REG register
- *  UART transmit and receive status.
- */
-#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
-/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
- *  This is the status register of receiver.
- */
-#define UART_ST_URX_OUT    0x0000000FU
-#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
-#define UART_ST_URX_OUT_V  0x0000000FU
-#define UART_ST_URX_OUT_S  0
-/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
- *  This is the status register of transmitter.
- */
-#define UART_ST_UTX_OUT    0x0000000FU
-#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
-#define UART_ST_UTX_OUT_V  0x0000000FU
-#define UART_ST_UTX_OUT_S  4
-
-/** UART_POSPULSE_REG register
- *  Autobaud high pulse register
- */
-#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
-/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two positive edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_POSEDGE_MIN_CNT    0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
-#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_S  0
-
-/** UART_NEGPULSE_REG register
- *  Autobaud low pulse register
- */
-#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
-/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two negative edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
-#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_S  0
-
-/** UART_LOWPULSE_REG register
- *  Autobaud minimum low pulse duration register
- */
-#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
-/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the value of the minimum duration time of the low level pulse.
- *  It is used in baud rate-detect process.
- */
-#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
-#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_S  0
-
-/** UART_HIGHPULSE_REG register
- *  Autobaud minimum high pulse duration register
- */
-#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
-/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores  the value of the maxinum duration time for the high level
- *  pulse. It is used in baud rate-detect process.
- */
-#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
-#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_S  0
-
-/** UART_RXD_CNT_REG register
- *  Autobaud edge change count register
- */
-#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
-/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
- *  This register stores the count of rxd edge change. It is used in baud rate-detect
- *  process.
- */
-#define UART_RXD_EDGE_CNT    0x000003FFU
-#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
-#define UART_RXD_EDGE_CNT_V  0x000003FFU
-#define UART_RXD_EDGE_CNT_S  0
-
-/** UART_CLK_CONF_REG register
- *  UART core clock configuration
- */
-#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
-/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
- *  Set this bit to enable UART Tx clock.
- */
-#define UART_TX_SCLK_EN    (BIT(24))
-#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
-#define UART_TX_SCLK_EN_V  0x00000001U
-#define UART_TX_SCLK_EN_S  24
-/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
- *  Set this bit to enable UART Rx clock.
- */
-#define UART_RX_SCLK_EN    (BIT(25))
-#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
-#define UART_RX_SCLK_EN_V  0x00000001U
-#define UART_RX_SCLK_EN_S  25
-/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Tx.
- */
-#define UART_TX_RST_CORE    (BIT(26))
-#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
-#define UART_TX_RST_CORE_V  0x00000001U
-#define UART_TX_RST_CORE_S  26
-/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
- *  Write 1 then write 0 to this bit to reset UART Rx.
- */
-#define UART_RX_RST_CORE    (BIT(27))
-#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
-#define UART_RX_RST_CORE_V  0x00000001U
-#define UART_RX_RST_CORE_S  27
-
-/** UART_DATE_REG register
- *  UART Version register
- */
-#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
-/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720;
- *  This is the version register.
- */
-#define UART_DATE    0xFFFFFFFFU
-#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
-#define UART_DATE_V  0xFFFFFFFFU
-#define UART_DATE_S  0
-
-/** UART_AFIFO_STATUS_REG register
- *  UART AFIFO Status
- */
-#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
-/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
- *  Full signal of APB TX AFIFO.
- */
-#define UART_TX_AFIFO_FULL    (BIT(0))
-#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
-#define UART_TX_AFIFO_FULL_V  0x00000001U
-#define UART_TX_AFIFO_FULL_S  0
-/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
- *  Empty signal of APB TX AFIFO.
- */
-#define UART_TX_AFIFO_EMPTY    (BIT(1))
-#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
-#define UART_TX_AFIFO_EMPTY_V  0x00000001U
-#define UART_TX_AFIFO_EMPTY_S  1
-/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
- *  Full signal of APB RX AFIFO.
- */
-#define UART_RX_AFIFO_FULL    (BIT(2))
-#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
-#define UART_RX_AFIFO_FULL_V  0x00000001U
-#define UART_RX_AFIFO_FULL_S  2
-/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
- *  Empty signal of APB RX AFIFO.
- */
-#define UART_RX_AFIFO_EMPTY    (BIT(3))
-#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
-#define UART_RX_AFIFO_EMPTY_V  0x00000001U
-#define UART_RX_AFIFO_EMPTY_S  3
-
-/** UART_REG_UPDATE_REG register
- *  UART Registers Configuration Update register
- */
-#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
-/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
- *  Software write 1 would synchronize registers into UART Core clock domain and would
- *  be cleared by hardware after synchronization is done.
- */
-#define UART_REG_UPDATE    (BIT(0))
-#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
-#define UART_REG_UPDATE_V  0x00000001U
-#define UART_REG_UPDATE_S  0
-
-/** UART_ID_REG register
- *  UART ID register
- */
-#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
-/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
- *  This register is used to configure the uart_id.
- */
-#define UART_ID    0xFFFFFFFFU
-#define UART_ID_M  (UART_ID_V << UART_ID_S)
-#define UART_ID_V  0xFFFFFFFFU
-#define UART_ID_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/uart_struct.h b/components/soc/esp32p4/include/soc/uart_struct.h
deleted file mode 100644
index b23e6db9305..00000000000
--- a/components/soc/esp32p4/include/soc/uart_struct.h
+++ /dev/null
@@ -1,1287 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
-         *  UART $n accesses FIFO via this register.
-         */
-        uint32_t rxfifo_rd_byte:32;
-    };
-    uint32_t val;
-} uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART memory power configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:25;
-        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_27:5;
-    };
-    uint32_t val;
-} uart_mem_conf_reg_t;
-
-/** Type of tout_conf_sync register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
-         */
-        uint32_t rx_tout_en:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
-         *  This register is used to configure the threshold time that receiver takes to
-         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
-         *  takes more time to receive one byte with rx_tout_en set to 1.
-         */
-        uint32_t rx_tout_thrhd:10;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_tout_conf_sync_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  what rxfifo_full_thrhd specifies.
-         */
-        uint32_t rxfifo_full_int_raw:1;
-        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
-         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-         *  less than what txfifo_empty_thrhd specifies .
-         */
-        uint32_t txfifo_empty_int_raw:1;
-        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error in
-         *  the data.
-         */
-        uint32_t parity_err_int_raw:1;
-        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  .
-         */
-        uint32_t frm_err_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  the FIFO can store.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  DSRn signal.
-         */
-        uint32_t dsr_chg_int_raw:1;
-        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  CTSn signal.
-         */
-        uint32_t cts_chg_int_raw:1;
-        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
-         *  bit.
-         */
-        uint32_t brk_det_int_raw:1;
-        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver takes more time than
-         *  rx_tout_thrhd to receive a byte.
-         */
-        uint32_t rxfifo_tout_int_raw:1;
-        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xon_int_raw:1;
-        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xoff_int_raw:1;
-        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
-         *  middle of a start bit.
-         */
-        uint32_t glitch_det_int_raw:1;
-        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter completes  sending
-         *  NULL characters after all data in Tx-FIFO are sent.
-         */
-        uint32_t tx_brk_done_int_raw:1;
-        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
-         *  duration after sending the  last data.
-         */
-        uint32_t tx_brk_idle_done_int_raw:1;
-        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has send out all data
-         *  in FIFO.
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_parity_err_int_raw:1;
-        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_frm_err_int_raw:1;
-        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  This interrupt raw bit turns to high level when detects a clash between transmitter
-         *  and receiver in rs485 mode.
-         */
-        uint32_t rs485_clash_int_raw:1;
-        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the configured
-         *  at_cmd char.
-         */
-        uint32_t at_cmd_char_det_int_raw:1;
-        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  This interrupt raw bit turns to high level when input rxd edge changes more times
-         *  than what reg_active_threshold specifies in light sleeping mode.
-         */
-        uint32_t wakeup_int_raw:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
-         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-         */
-        uint32_t rxfifo_full_int_st:1;
-        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
-         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
-         *  to 1.
-         */
-        uint32_t txfifo_empty_int_st:1;
-        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
-         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-         */
-        uint32_t parity_err_int_st:1;
-        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
-         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-         */
-        uint32_t frm_err_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
-         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-         */
-        uint32_t dsr_chg_int_st:1;
-        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
-         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-         */
-        uint32_t cts_chg_int_st:1;
-        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
-         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-         */
-        uint32_t brk_det_int_st:1;
-        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
-         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-         */
-        uint32_t rxfifo_tout_int_st:1;
-        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
-         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-         */
-        uint32_t sw_xon_int_st:1;
-        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
-         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-         */
-        uint32_t sw_xoff_int_st:1;
-        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
-         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-         */
-        uint32_t glitch_det_int_st:1;
-        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
-         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-         */
-        uint32_t tx_brk_done_int_st:1;
-        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
-         *  is set to 1.
-         */
-        uint32_t tx_brk_idle_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-         */
-        uint32_t tx_done_int_st:1;
-        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
-         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-         *  set to 1.
-         */
-        uint32_t rs485_parity_err_int_st:1;
-        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
-         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
-         *  to 1.
-         */
-        uint32_t rs485_frm_err_int_st:1;
-        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
-         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
-         */
-        uint32_t rs485_clash_int_st:1;
-        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
-         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
-         *  to 1.
-         */
-        uint32_t at_cmd_char_det_int_st:1;
-        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
-         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-         */
-        uint32_t wakeup_int_st:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
-         *  This is the enable bit for rxfifo_full_int_st register.
-         */
-        uint32_t rxfifo_full_int_ena:1;
-        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
-         *  This is the enable bit for txfifo_empty_int_st register.
-         */
-        uint32_t txfifo_empty_int_ena:1;
-        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
-         *  This is the enable bit for parity_err_int_st register.
-         */
-        uint32_t parity_err_int_ena:1;
-        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
-         *  This is the enable bit for frm_err_int_st register.
-         */
-        uint32_t frm_err_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  This is the enable bit for rxfifo_ovf_int_st register.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for dsr_chg_int_st register.
-         */
-        uint32_t dsr_chg_int_ena:1;
-        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
-         *  This is the enable bit for cts_chg_int_st register.
-         */
-        uint32_t cts_chg_int_ena:1;
-        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
-         *  This is the enable bit for brk_det_int_st register.
-         */
-        uint32_t brk_det_int_ena:1;
-        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
-         *  This is the enable bit for rxfifo_tout_int_st register.
-         */
-        uint32_t rxfifo_tout_int_ena:1;
-        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
-         *  This is the enable bit for sw_xon_int_st register.
-         */
-        uint32_t sw_xon_int_ena:1;
-        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
-         *  This is the enable bit for sw_xoff_int_st register.
-         */
-        uint32_t sw_xoff_int_ena:1;
-        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
-         *  This is the enable bit for glitch_det_int_st register.
-         */
-        uint32_t glitch_det_int_ena:1;
-        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for tx_brk_done_int_st register.
-         */
-        uint32_t tx_brk_done_int_ena:1;
-        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit for tx_brk_idle_done_int_st register.
-         */
-        uint32_t tx_brk_idle_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for tx_done_int_st register.
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_parity_err_int_ena:1;
-        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_frm_err_int_ena:1;
-        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
-         *  This is the enable bit for rs485_clash_int_st register.
-         */
-        uint32_t rs485_clash_int_ena:1;
-        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
-         *  This is the enable bit for at_cmd_char_det_int_st register.
-         */
-        uint32_t at_cmd_char_det_int_ena:1;
-        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for uart_wakeup_int_st register.
-         */
-        uint32_t wakeup_int_ena:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
-         */
-        uint32_t rxfifo_full_int_clr:1;
-        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear txfifo_empty_int_raw interrupt.
-         */
-        uint32_t txfifo_empty_int_clr:1;
-        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear parity_err_int_raw interrupt.
-         */
-        uint32_t parity_err_int_clr:1;
-        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear frm_err_int_raw interrupt.
-         */
-        uint32_t frm_err_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the dsr_chg_int_raw interrupt.
-         */
-        uint32_t dsr_chg_int_clr:1;
-        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the cts_chg_int_raw interrupt.
-         */
-        uint32_t cts_chg_int_clr:1;
-        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the brk_det_int_raw interrupt.
-         */
-        uint32_t brk_det_int_clr:1;
-        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-         */
-        uint32_t rxfifo_tout_int_clr:1;
-        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the sw_xon_int_raw interrupt.
-         */
-        uint32_t sw_xon_int_clr:1;
-        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the sw_xoff_int_raw interrupt.
-         */
-        uint32_t sw_xoff_int_clr:1;
-        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the glitch_det_int_raw interrupt.
-         */
-        uint32_t glitch_det_int_clr:1;
-        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
-         */
-        uint32_t tx_brk_done_int_clr:1;
-        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-         */
-        uint32_t tx_brk_idle_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the tx_done_int_raw interrupt.
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
-         */
-        uint32_t rs485_parity_err_int_clr:1;
-        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
-         */
-        uint32_t rs485_frm_err_int_clr:1;
-        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
-         *  Set this bit to clear the rs485_clash_int_raw interrupt.
-         */
-        uint32_t rs485_clash_int_clr:1;
-        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-         */
-        uint32_t at_cmd_char_det_int_clr:1;
-        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
-         */
-        uint32_t wakeup_int_clr:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv_sync register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t clkdiv:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  The decimal part of the frequency divider factor.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_clkdiv_sync_reg_t;
-
-/** Type of rx_filt register
- *  Rx Filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  when input pulse width is lower than this value the pulse is ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable Rx signal filter.
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_rx_filt_reg_t;
-
-/** Type of conf0_sync register
- *  a
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  This register is used to configure the parity check mode.
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable uart parity check.
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  This register is used to set the length of data.
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  This register is used to set the length of  stop bit.
-         */
-        uint32_t stop_bit_num:2;
-        /** txd_brk : R/W; bitpos: [6]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
-         *  is done.
-         */
-        uint32_t txd_brk:1;
-        /** irda_dplx : R/W; bitpos: [7]; default: 0;
-         *  Set this bit to enable IrDA loopback mode.
-         */
-        uint32_t irda_dplx:1;
-        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
-         *  This is the start enable bit for IrDA transmitter.
-         */
-        uint32_t irda_tx_en:1;
-        /** irda_wctl : R/W; bitpos: [9]; default: 0;
-         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-         *  transmitter's 11th bit to 0.
-         */
-        uint32_t irda_wctl:1;
-        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to invert the level of  IrDA transmitter.
-         */
-        uint32_t irda_tx_inv:1;
-        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
-         *  Set this bit to invert the level of IrDA receiver.
-         */
-        uint32_t irda_rx_inv:1;
-        /** loopback : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to enable uart loopback test mode.
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to enable flow control function for transmitter.
-         */
-        uint32_t tx_flow_en:1;
-        /** irda_en : R/W; bitpos: [14]; default: 0;
-         *  Set this bit to enable IrDA protocol.
-         */
-        uint32_t irda_en:1;
-        /** rxd_inv : R/W; bitpos: [15]; default: 0;
-         *  Set this bit to inverse the level value of uart rxd signal.
-         */
-        uint32_t rxd_inv:1;
-        /** txd_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart txd signal.
-         */
-        uint32_t txd_inv:1;
-        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
-         *  Disable UART Rx data overflow detect.
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
-         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-         *  stores the data even if the  received data is wrong.
-         */
-        uint32_t err_wr_mask:1;
-        /** autobaud_en : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for detecting baudrate.
-         */
-        uint32_t autobaud_en:1;
-        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
-         *  UART memory clock gate enable signal.
-         */
-        uint32_t mem_clk_en:1;
-        /** sw_rts : R/W; bitpos: [21]; default: 0;
-         *  This register is used to configure the software rts signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_rts:1;
-        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
-         *  Set this bit to reset the uart receive-FIFO.
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
-         *  Set this bit to reset the uart transmit-FIFO.
-         */
-        uint32_t txfifo_rst:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_conf0_sync_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
-         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
-         *  this register value.
-         */
-        uint32_t rxfifo_full_thrhd:8;
-        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
-         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
-         *  than this register value.
-         */
-        uint32_t txfifo_empty_thrhd:8;
-        /** cts_inv : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to inverse the level value of uart cts signal.
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to inverse the level value of uart dsr signal.
-         */
-        uint32_t dsr_inv:1;
-        /** rts_inv : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to inverse the level value of uart rts signal.
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to inverse the level value of uart dtr signal.
-         */
-        uint32_t dtr_inv:1;
-        /** sw_dtr : R/W; bitpos: [20]; default: 0;
-         *  This register is used to configure the software dtr signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_dtr:1;
-        /** clk_en : R/W; bitpos: [21]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} uart_conf1_reg_t;
-
-/** Type of hwfc_conf_sync register
- *  Hardware flow-control configuration
- */
-typedef union {
-    struct {
-        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
-         *  This register is used to configure the maximum amount of data that can be received
-         *  when hardware flow control works.
-         */
-        uint32_t rx_flow_thrhd:8;
-        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
-         *  This is the flow enable bit for UART receiver.
-         */
-        uint32_t rx_flow_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_hwfc_conf_sync_reg_t;
-
-/** Type of sleep_conf0 register
- *  UART sleep configure register 0
- */
-typedef union {
-    struct {
-        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified wake up char1 to wake up
-         */
-        uint32_t wk_char1:8;
-        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
-         *  This register restores the specified wake up char2 to wake up
-         */
-        uint32_t wk_char2:8;
-        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
-         *  This register restores the specified wake up char3 to wake up
-         */
-        uint32_t wk_char3:8;
-        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
-         *  This register restores the specified wake up char4 to wake up
-         */
-        uint32_t wk_char4:8;
-    };
-    uint32_t val;
-} uart_sleep_conf0_reg_t;
-
-/** Type of sleep_conf1 register
- *  UART sleep configure register 1
- */
-typedef union {
-    struct {
-        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
-         *  This register restores the specified char0 to wake up
-         */
-        uint32_t wk_char0:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_sleep_conf1_reg_t;
-
-/** Type of sleep_conf2 register
- *  UART sleep configure register 2
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  The uart is activated from light sleeping mode when the input rxd edge changes more
-         *  times than this register value.
-         */
-        uint32_t active_threshold:10;
-        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
-         *  In wake up mode 1 this field is used to set the received data number threshold to
-         *  wake up chip.
-         */
-        uint32_t rx_wake_up_thrhd:8;
-        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
-         *  This register is used to select number of wake up char.
-         */
-        uint32_t wk_char_num:3;
-        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
-         *  This register is used to mask  wake up char.
-         */
-        uint32_t wk_char_mask:5;
-        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
-         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
-         *  received data number larger than
-         */
-        uint32_t wk_mode_sel:2;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_sleep_conf2_reg_t;
-
-/** Type of swfc_conf0_sync register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_char : R/W; bitpos: [7:0]; default: 17;
-         *  This register stores the Xon flow control char.
-         */
-        uint32_t xon_char:8;
-        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
-         *  This register stores the Xoff flow control char.
-         */
-        uint32_t xoff_char:8;
-        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
-         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
-         *  this status, UART Tx can not transmit XOFF even the received data number is larger
-         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
-         *  UART Tx is disabled.
-         */
-        uint32_t xon_xoff_still_send:1;
-        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to enable software flow control. It is used with register sw_xon or
-         *  sw_xoff.
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to remove flow control char from the received data.
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to enable the transmitter to go on sending data.
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [20]; default: 0;
-         *  Set this bit to stop the  transmitter from sending data.
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
-         *  Set this bit to send Xon char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
-         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_23:9;
-    };
-    uint32_t val;
-} uart_swfc_conf0_sync_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
-         *  When the data amount in Rx-FIFO is less than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
-         */
-        uint32_t xon_threshold:8;
-        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
-         *  When the data amount in Rx-FIFO is more than this register value with
-         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
-         */
-        uint32_t xoff_threshold:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf_sync register
- *  Tx Break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  This register is used to configure the number of 0 to be sent after the process of
-         *  sending data is done. It is active when txd_brk is set to 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_txbrk_conf_sync_reg_t;
-
-/** Type of idle_conf_sync register
- *  Frame-end idle configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  It will produce frame end signal when receiver takes more time to receive one byte
-         *  data than this register value.
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  This register is used to configure the duration time between transfers.
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_idle_conf_sync_reg_t;
-
-/** Type of rs485_conf_sync register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        /** rs485_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to choose the rs485 mode.
-         */
-        uint32_t rs485_en:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl1_en:1;
-        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable receiver could receive data when the transmitter is
-         *  transmitting data in rs485 mode.
-         */
-        uint32_t rs485tx_rx_en:1;
-        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
-         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-         */
-        uint32_t rs485rxby_tx_en:1;
-        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
-         *  This register is used to delay the receiver's internal data signal.
-         */
-        uint32_t rs485_rx_dly_num:1;
-        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
-         *  This register is used to delay the transmitter's internal data signal.
-         */
-        uint32_t rs485_tx_dly_num:4;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rs485_conf_sync_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor.
-         */
-        uint32_t sclk_div_b:6;      //HP UART's sclk_div_b is in hp_sys_clkrst_struct.h
-        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor.
-         */
-        uint32_t sclk_div_a:6;      //HP UART's sclk_div_a is in hp_sys_clkrst_struct.h
-        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor.
-         *  It is only used by LP UART
-         */
-        uint32_t sclk_div_num:8;    //HP UART's sclk_div_num is in hp_sys_clkrst_struct.h
-        uint32_t reserved_20:4;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Set this bit to enable UART Tx clock.
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Set this bit to enable UART Rx clock.
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Tx.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 then write 0 to this bit to reset UART Rx.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
-         *  Stores the byte number of valid data in Rx-FIFO.
-         */
-        uint32_t rxfifo_cnt:8;
-        uint32_t reserved_8:5;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  The register represent the level value of the internal uart dsr signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  This register represent the level value of the internal uart cts signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  This register represent the  level value of the internal uart rxd signal.
-         */
-        uint32_t rxd:1;
-        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
-         *  Stores the byte number of data in Tx-FIFO.
-         */
-        uint32_t txfifo_cnt:8;
-        uint32_t reserved_24:5;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  This bit represents the level of the internal uart dtr signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  This bit represents the level of the internal uart rts signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  This bit represents the  level of the internal uart txd signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  Tx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
-         *  This register stores the offset write address in Tx-SRAM.
-         */
-        uint32_t tx_sram_waddr:8;
-        uint32_t reserved_8:1;
-        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
-         *  This register stores the offset read address in Tx-SRAM.
-         */
-        uint32_t tx_sram_raddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx-SRAM write and read offset address.
- */
-typedef union {
-    struct {
-        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
-         *  This register stores the offset read address in RX-SRAM.
-         */
-        uint32_t rx_sram_raddr:8;
-        uint32_t reserved_8:1;
-        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
-         *  This register stores the offset write address in Rx-SRAM.
-         */
-        uint32_t rx_sram_waddr:8;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status.
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  This is the status register of receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  This is the status register of transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_fsm_status_reg_t;
-
-/** Type of afifo_status register
- *  UART AFIFO Status
- */
-typedef union {
-    struct {
-        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
-         *  Full signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_full:1;
-        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
-         *  Empty signal of APB TX AFIFO.
-         */
-        uint32_t tx_afifo_empty:1;
-        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
-         *  Full signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_full:1;
-        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
-         *  Empty signal of APB RX AFIFO.
-         */
-        uint32_t rx_afifo_empty:1;
-        uint32_t reserved_4:28;
-    };
-    uint32_t val;
-} uart_afifo_status_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt_sync register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the idle duration time before the first at_cmd
-         *  is received by receiver.
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_precnt_sync_reg_t;
-
-/** Type of at_cmd_postcnt_sync register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the duration time between the last at_cmd and
-         *  the next data.
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_postcnt_sync_reg_t;
-
-/** Type of at_cmd_gaptout_sync register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  This register is used to configure the duration time between the at_cmd chars.
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_gaptout_sync_reg_t;
-
-/** Type of at_cmd_char_sync register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
-         *  This register is used to configure the content of at_cmd char.
-         */
-        uint32_t at_cmd_char:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  This register is used to configure the num of continuous at_cmd chars received by
-         *  receiver.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_char_sync_reg_t;
-
-
-/** Group: Autobaud Register */
-/** Type of pospulse register
- *  Autobaud high pulse register
- */
-typedef union {
-    struct {
-        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two positive edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t posedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_pospulse_reg_t;
-
-/** Type of negpulse register
- *  Autobaud low pulse register
- */
-typedef union {
-    struct {
-        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two negative edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t negedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_negpulse_reg_t;
-
-/** Type of lowpulse register
- *  Autobaud minimum low pulse duration register
- */
-typedef union {
-    struct {
-        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the value of the minimum duration time of the low level pulse.
-         *  It is used in baud rate-detect process.
-         */
-        uint32_t lowpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_lowpulse_reg_t;
-
-/** Type of highpulse register
- *  Autobaud minimum high pulse duration register
- */
-typedef union {
-    struct {
-        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores  the value of the maxinum duration time for the high level
-         *  pulse. It is used in baud rate-detect process.
-         */
-        uint32_t highpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_highpulse_reg_t;
-
-/** Type of rxd_cnt register
- *  Autobaud edge change count register
- */
-typedef union {
-    struct {
-        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
-         *  This register stores the count of rxd edge change. It is used in baud rate-detect
-         *  process.
-         */
-        uint32_t rxd_edge_cnt:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rxd_cnt_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 36720720;
-         *  This is the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} uart_date_reg_t;
-
-/** Type of reg_update register
- *  UART Registers Configuration Update register
- */
-typedef union {
-    struct {
-        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
-         *  Software write 1 would synchronize registers into UART Core clock domain and would
-         *  be cleared by hardware after synchronization is done.
-         */
-        uint32_t reg_update:1;
-        uint32_t reserved_1:31;
-    };
-    uint32_t val;
-} uart_reg_update_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [31:0]; default: 1280;
-         *  This register is used to configure the uart_id.
-         */
-        uint32_t id:32;
-    };
-    uint32_t val;
-} uart_id_reg_t;
-
-
-typedef struct uart_dev_t{
-    volatile uart_fifo_reg_t fifo;
-    volatile uart_int_raw_reg_t int_raw;
-    volatile uart_int_st_reg_t int_st;
-    volatile uart_int_ena_reg_t int_ena;
-    volatile uart_int_clr_reg_t int_clr;
-    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
-    volatile uart_rx_filt_reg_t rx_filt;
-    volatile uart_status_reg_t status;
-    volatile uart_conf0_sync_reg_t conf0_sync;
-    volatile uart_conf1_reg_t conf1;
-    uint32_t reserved_028;
-    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
-    volatile uart_sleep_conf0_reg_t sleep_conf0;
-    volatile uart_sleep_conf1_reg_t sleep_conf1;
-    volatile uart_sleep_conf2_reg_t sleep_conf2;
-    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
-    volatile uart_swfc_conf1_reg_t swfc_conf1;
-    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
-    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
-    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
-    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
-    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
-    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
-    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
-    volatile uart_mem_conf_reg_t mem_conf;
-    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
-    volatile uart_mem_tx_status_reg_t mem_tx_status;
-    volatile uart_mem_rx_status_reg_t mem_rx_status;
-    volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;      /* LP_UART instance has this register reserved */
-    volatile uart_negpulse_reg_t negpulse;      /* LP_UART instance has this register reserved */
-    volatile uart_lowpulse_reg_t lowpulse;      /* LP_UART instance has this register reserved */
-    volatile uart_highpulse_reg_t highpulse;    /* LP_UART instance has this register reserved */
-    volatile uart_rxd_cnt_reg_t rxd_cnt;        /* LP_UART instance has this register reserved */
-    volatile uart_clk_conf_reg_t clk_conf;      /* UART0/1/2/3/4 instance have this register reserved, configure in corresponding PCR registers */
-    volatile uart_date_reg_t date;
-    volatile uart_afifo_status_reg_t afifo_status;
-    uint32_t reserved_094;
-    volatile uart_reg_update_reg_t reg_update;
-    volatile uart_id_reg_t id;
-} uart_dev_t;
-
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-extern uart_dev_t UART2;
-extern uart_dev_t UART3;
-extern uart_dev_t UART4;
-extern uart_dev_t LP_UART;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/usb_dwc_cfg.h b/components/soc/esp32p4/include/soc/usb_dwc_cfg.h
index 3b5b887568f..816cff4285c 100644
--- a/components/soc/esp32p4/include/soc/usb_dwc_cfg.h
+++ b/components/soc/esp32p4/include/soc/usb_dwc_cfg.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,94 +11,170 @@ extern "C" {
 #endif
 
 /*
+HS Instance:
 Configuration Set ID: 11
 */
 
 /* 3.1 Basic Config Parameters */
-#define OTG_MODE                0
-#define OTG_ARCHITECTURE        2
-#define OTG_SINGLE_POINT        1
-#define OTG_ENABLE_LPM          0
-#define OTG_EN_DED_TX_FIFO      1
-#define OTG_EN_DESC_DMA         1
-#define OTG_MULTI_PROC_INTRPT   1
+#define OTG20_MODE                0
+#define OTG20_ARCHITECTURE        2
+#define OTG20_SINGLE_POINT        1
+#define OTG20_ENABLE_LPM          0
+#define OTG20_EN_DED_TX_FIFO      1
+#define OTG20_EN_DESC_DMA         1
+#define OTG20_MULTI_PROC_INTRPT   1
 
 /* 3.2 USB Physical Layer Interface Parameters */
-#define OTG_HSPHY_INTERFACE         3
-#define OTG_HSPHY_DWIDTH            2
-#define OTG_FSPHY_INTERFACE         2
-#define OTG_ENABLE_IC_USB           0
-#define OTG_ENABLE_HSIC             0
-#define OTG_I2C_INTERFACE           0
-#define OTG_ULPI_CARKIT             1
-#define OTG_ADP_SUPPORT             1
-#define OTG_BC_SUPPORT              0
-#define OTG_VENDOR_CTL_INTERFACE    1
+#define OTG20_HSPHY_INTERFACE         3
+#define OTG20_HSPHY_DWIDTH            2
+#define OTG20_FSPHY_INTERFACE         2
+#define OTG20_ENABLE_IC_USB           0
+#define OTG20_ENABLE_HSIC             0
+#define OTG20_I2C_INTERFACE           0
+#define OTG20_ULPI_CARKIT             1
+#define OTG20_ADP_SUPPORT             1
+#define OTG20_BC_SUPPORT              0
+#define OTG20_VENDOR_CTL_INTERFACE    1
 
 /* 3.3 Device Endpoint Configuration Parameters */
-#define OTG_NUM_EPS         15
-#define OTG_NUM_IN_EPS      8
-#define OTG_NUM_CRL_EPS     1
+#define OTG20_NUM_EPS         15
+#define OTG20_NUM_IN_EPS      8
+#define OTG20_NUM_CRL_EPS     1
 
 /* 3.4 Host Endpoint Configuration Parameters */
-#define OTG_NUM_HOST_CHAN   16
-#define OTG_EN_PERIO_HOST   1
+#define OTG20_NUM_HOST_CHAN   16
+#define OTG20_EN_PERIO_HOST   1
 
 /* 3.5 Endpoint Channel FIFO Configuration Parameters */
-#define OTG_DFIFO_DEPTH             1024
-#define OTG_DFIFO_DYNAMIC           1
-#define OTG_RX_DFIFO_DEPTH          1024
-#define OTG_TX_HNPERIO_DFIFO_DEPTH  1024
-#define OTG_TX_HPERIO_DFIFO_DEPTH   1024
-#define OTG_NPERIO_TX_QUEUE_DEPTH   4
-#define OTG_PERIO_TX_QUEUE_DEPTH    4
+#define OTG20_DFIFO_DEPTH             1024
+#define OTG20_DFIFO_DYNAMIC           1
+#define OTG20_RX_DFIFO_DEPTH          1024
+#define OTG20_TX_HNPERIO_DFIFO_DEPTH  1024
+#define OTG20_TX_HPERIO_DFIFO_DEPTH   1024
+#define OTG20_NPERIO_TX_QUEUE_DEPTH   4
+#define OTG20_PERIO_TX_QUEUE_DEPTH    4
 
 /* 3.6 Additional Configuration Options Parameters */
-#define OTG_TRANS_COUNT_WIDTH       17
-#define OTG_PACKET_COUNT_WIDTH      8
-#define OTG_RM_OPT_FEATURES         1
-#define OTG_EN_PWROPT               1
-#define OTG_SYNC_RESET_TYPE         0
-#define OTG_EN_IDDIG_FILTER         1
-#define OTG_EN_VBUSVALID_FILTER     1
-#define OTG_EN_A_VALID_FILTER       1
-#define OTG_EN_B_VALID_FILTER       1
-#define OTG_EN_SESSIONEND_FILTER    1
-#define OTG_EXCP_CNTL_XFER_FLOW     1
-#define OTG_PWR_CLAMP               0
-#define OTG_PWR_SWITCH_POLARITY     0
+#define OTG20_TRANS_COUNT_WIDTH       17
+#define OTG20_PACKET_COUNT_WIDTH      8
+#define OTG20_RM_OPT_FEATURES         1
+#define OTG20_EN_PWROPT               1
+#define OTG20_SYNC_RESET_TYPE         0
+#define OTG20_EN_IDDIG_FILTER         1
+#define OTG20_EN_VBUSVALID_FILTER     1
+#define OTG20_EN_A_VALID_FILTER       1
+#define OTG20_EN_B_VALID_FILTER       1
+#define OTG20_EN_SESSIONEND_FILTER    1
+#define OTG20_EXCP_CNTL_XFER_FLOW     1
+#define OTG20_PWR_CLAMP               0
+#define OTG20_PWR_SWITCH_POLARITY     0
 
 /* 3.7 Endpoint Direction Parameters */
-#define OTG_EP_DIR_1    0
-#define OTG_EP_DIR_2    0
-#define OTG_EP_DIR_3    0
-#define OTG_EP_DIR_4    0
-#define OTG_EP_DIR_5    0
-#define OTG_EP_DIR_6    0
-#define OTG_EP_DIR_7    0
-#define OTG_EP_DIR_8    0
-#define OTG_EP_DIR_9    0
-#define OTG_EP_DIR_10   0
-#define OTG_EP_DIR_11   0
-#define OTG_EP_DIR_12   0
-#define OTG_EP_DIR_13   0
-#define OTG_EP_DIR_14   0
-#define OTG_EP_DIR_15   0
+#define OTG20_EP_DIR_1    0
+#define OTG20_EP_DIR_2    0
+#define OTG20_EP_DIR_3    0
+#define OTG20_EP_DIR_4    0
+#define OTG20_EP_DIR_5    0
+#define OTG20_EP_DIR_6    0
+#define OTG20_EP_DIR_7    0
+#define OTG20_EP_DIR_8    0
+#define OTG20_EP_DIR_9    0
+#define OTG20_EP_DIR_10   0
+#define OTG20_EP_DIR_11   0
+#define OTG20_EP_DIR_12   0
+#define OTG20_EP_DIR_13   0
+#define OTG20_EP_DIR_14   0
+#define OTG20_EP_DIR_15   0
 
 /* 3.8 Device Periodic FIFO Depth Parameters */
 
 /* 3.9 Device IN Endpoint FIFO Depth Parameters */
-#define OTG_TX_DINEP_DFIFO_DEPTH_0  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_1  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_2  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_3  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_4  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_5  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_6  512
-#define OTG_TX_DINEP_DFIFO_DEPTH_7  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_0  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_1  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_2  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_3  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_4  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_5  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_6  512
+#define OTG20_TX_DINEP_DFIFO_DEPTH_7  512
 
 /* 3.10 UTMI-To-UTMI Bridge Component Parameters */
-#define DWC_U2UB_EN     0
+#define OTG20_U2UB_EN     0
+
+/*
+FS Instance:
+Configuration Set ID: 1
+*/
+
+/* 3.1 Basic Config Parameters */
+#define OTG11_MODE                0
+#define OTG11_ARCHITECTURE        2
+#define OTG11_SINGLE_POINT        1
+#define OTG11_ENABLE_LPM          0
+#define OTG11_EN_DED_TX_FIFO      1
+#define OTG11_EN_DESC_DMA         1
+#define OTG11_MULTI_PROC_INTRPT   0
+
+/* 3.2 USB Physical Layer Interface Parameters */
+#define OTG11_HSPHY_INTERFACE     0
+#define OTG11_FSPHY_INTERFACE     1
+#define OTG11_ENABLE_IC_USB       0
+#define OTG11_I2C_INTERFACE       0
+#define OTG11_ADP_SUPPORT         0
+#define OTG11_BC_SUPPORT          0
+
+/* 3.3 Device Endpoint Configuration Parameters */
+#define OTG11_NUM_EPS         6
+#define OTG11_NUM_IN_EPS      5
+#define OTG11_NUM_CRL_EPS     0
+
+/* 3.4 Host Endpoint Configuration Parameters */
+#define OTG11_NUM_HOST_CHAN   8
+#define OTG11_EN_PERIO_HOST   1
+
+/* 3.5 Endpoint Channel FIFO Configuration Parameters */
+#define OTG11_DFIFO_DEPTH             256
+#define OTG11_DFIFO_DYNAMIC           1
+#define OTG11_RX_DFIFO_DEPTH          256
+#define OTG11_TX_HNPERIO_DFIFO_DEPTH  256
+#define OTG11_TX_NPERIO_DFIFO_DEPTH   256
+#define OTG11_TX_HPERIO_DFIFO_DEPTH   256
+#define OTG11_NPERIO_TX_QUEUE_DEPTH   4
+#define OTG11_PERIO_TX_QUEUE_DEPTH    8
+
+/* 3.6 Additional Configuration Options Parameters */
+#define OTG11_TRANS_COUNT_WIDTH       16
+#define OTG11_PACKET_COUNT_WIDTH      7
+#define OTG11_RM_OPT_FEATURES         1
+#define OTG11_EN_PWROPT               1
+#define OTG11_SYNC_RESET_TYPE         0
+#define OTG11_EN_IDDIG_FILTER         1
+#define OTG11_EN_VBUSVALID_FILTER     1
+#define OTG11_EN_A_VALID_FILTER       1
+#define OTG11_EN_B_VALID_FILTER       1
+#define OTG11_EN_SESSIONEND_FILTER    1
+#define OTG11_EXCP_CNTL_XFER_FLOW     1
+#define OTG11_PWR_CLAMP               0
+#define OTG11_PWR_SWITCH_POLARITY     0
+
+/* 3.7 Endpoint Direction Parameters */
+#define OTG11_EP_DIR_1    0
+#define OTG11_EP_DIR_2    0
+#define OTG11_EP_DIR_3    0
+#define OTG11_EP_DIR_4    0
+#define OTG11_EP_DIR_5    0
+#define OTG11_EP_DIR_6    0
+
+/* 3.8 Device Periodic FIFO Depth Parameters */
+
+/* 3.9 Device IN Endpoint FIFO Depth Parameters */
+#define OTG11_TX_DINEP_DFIFO_DEPTH_1  256
+#define OTG11_TX_DINEP_DFIFO_DEPTH_2  256
+#define OTG11_TX_DINEP_DFIFO_DEPTH_3  256
+#define OTG11_TX_DINEP_DFIFO_DEPTH_4  256
+
+/* 3.10 UTMI-To-UTMI Bridge Component Parameters */
+#define OTG11_U2UB_EN     0
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/usb_dwc_struct.h b/components/soc/esp32p4/include/soc/usb_dwc_struct.h
index 728be16b0f6..f07575c52a6 100644
--- a/components/soc/esp32p4/include/soc/usb_dwc_struct.h
+++ b/components/soc/esp32p4/include/soc/usb_dwc_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,7 +13,10 @@ extern "C" {
 #endif
 
 /*
-Registers and fields were generated based on a set of configuration options.
+Registers and fields were generated based on a set of USB-DWC configuration options.
+ESP32-P4 contains 2 instances of USB-DWC with different configurations, the structure below corresponds to the HS instance.
+The FS instance contains a subset of registers from HS instance, the user (HAL) is responsible for accessing only existing fields.
+
 See ESP32-P4 "usb_dwc_cfg.h" for more details.
 */
 
@@ -33,7 +36,7 @@ typedef union {
         uint32_t hnpreq: 1;
         uint32_t hstsethnpen: 1;
         uint32_t devhnpen: 1;
-        uint32_t ehen: 1;
+        uint32_t ehen: 1;    // codespell:ignore ehen
         uint32_t reserved_13: 2;
         uint32_t dbncefltrbypass: 1;
         uint32_t conidsts: 1;
@@ -1368,6 +1371,7 @@ _Static_assert(sizeof(usb_dwc_dev_t) == 0xe08, "Invalid size of usb_dwc_dev_t st
 #endif
 
 extern usb_dwc_dev_t USB_DWC_HS;
+extern usb_dwc_dev_t USB_DWC_FS;
 
 #ifdef __cplusplus
 }
diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h
deleted file mode 100644
index 478c734ea80..00000000000
--- a/components/soc/esp32p4/include/soc/usb_serial_jtag_reg.h
+++ /dev/null
@@ -1,1282 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** USB_SERIAL_JTAG_EP1_REG register
- *  FIFO access for the CDC-ACM data IN and OUT endpoints.
- */
-#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0;
- *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
- *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
- *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
- *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
- *  received, then read data from UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-/** USB_SERIAL_JTAG_EP1_CONF_REG register
- *  Configuration and control registers for the CDC-ACM FIFOs.
- */
-#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
- *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
- */
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
-#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
- *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
- *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
- *  Host.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
- *  1'b1: Indicate there is data in UART Rx FIFO.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-
-/** USB_SERIAL_JTAG_INT_RAW_REG register
- *  Interrupt raw status register.
- */
-#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw interrupt bit turns to high level when flush cmd is received for IN
- *  endpoint 2 of JTAG.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw interrupt bit turns to high level when SOF frame is received.
- */
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- *  one packet.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
- *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw interrupt bit turns to high level when pid error is detected.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw interrupt bit turns to high level when CRC5 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw interrupt bit turns to high level when CRC16 error is detected.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw interrupt bit turns to high level when stuff error is detected.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
- *  received.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw interrupt bit turns to high level when usb bus reset is detected.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
- *  zero palyload.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
- *  is changed.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
- *  received.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
-
-/** USB_SERIAL_JTAG_INT_ST_REG register
- *  Interrupt status register.
- */
-#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
- *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
-
-/** USB_SERIAL_JTAG_INT_ENA_REG register
- *  Interrupt enable status register.
- */
-#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
-
-/** USB_SERIAL_JTAG_INT_CLR_REG register
- *  Interrupt clear status register.
- */
-#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
- */
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
- */
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
- */
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
-/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
- */
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
-/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
-/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
-#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
-
-/** USB_SERIAL_JTAG_CONF0_REG register
- *  PHY hardware configuration.
- */
-#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
- *  Select internal/external PHY
- */
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
- *  Enable software control USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
- *  USB D+ D- exchange
- */
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
- *  Control single-end input high threshold,1.76V to 2V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFH    0x00000003U
-#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
-#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFH_S  3
-/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
- *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
- */
-#define USB_SERIAL_JTAG_VREFL    0x00000003U
-#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
-#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
-#define USB_SERIAL_JTAG_VREFL_S  5
-/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
- *  Enable software control input  threshold
- */
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
- *  Enable software control USB D+ D- pullup pulldown
- */
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
- *  Control USB D+ pull up.
- */
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
- *  Control USB D+ pull down.
- */
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
- *  Control USB D- pull up.
- */
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
- *  Control USB D- pull down.
- */
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
- *  Control pull up value.
- */
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
- *  Enable USB pad function.
- */
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
- *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
- *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
- *  through GPIO Matrix.
- */
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
-
-/** USB_SERIAL_JTAG_TEST_REG register
- *  Registers used for debugging the PHY.
- */
-#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
-/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
- *  Enable test of the USB pad
- */
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
- *  USB pad oen in test
- */
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
- *  USB D+ tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
- *  USB D- tx value in test
- */
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
- *  USB RCV value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
-#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
-/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
- *  USB D+ rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
-#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
-/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
- *  USB D- rx value in test
- */
-#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
-#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
-#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
-
-/** USB_SERIAL_JTAG_JFIFO_ST_REG register
- *  JTAG FIFO status and control registers.
- */
-#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
- *  JTAT in fifo counter.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
- *  1: JTAG in fifo is empty.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
- *  1: JTAG in fifo is full.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
- *  JTAT out fifo counter.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
- *  1: JTAG out fifo is empty.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
- *  1: JTAG out fifo is full.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
- *  Write 1 to reset JTAG in fifo.
- */
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
- *  Write 1 to reset JTAG out fifo.
- */
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-
-/** USB_SERIAL_JTAG_FRAM_NUM_REG register
- *  Last received SOF frame index register.
- */
-#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
- *  Frame index of received SOF frame.
- */
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
- *  Control IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 0.
- */
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
- *  CDC-ACM IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
-/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 1.
- */
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
- *  CDC-ACM interrupt IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 2.
- */
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
- *  JTAG IN endpoint status information.
- */
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
- *  State of IN Endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of IN endpoint 3.
- */
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
- *  Control OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 0.
- */
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
- *  CDC-ACM OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
-/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 1.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
- *  Data count in OUT endpoint 1 when one packet is received.
- */
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-
-/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
- *  JTAG OUT endpoint status information.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
- *  State of OUT Endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
- *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
- *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
- *  Read data address of OUT endpoint 2.
- */
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-
-/** USB_SERIAL_JTAG_MISC_CONF_REG register
- *  Clock enable control
- */
-#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
-#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-/** USB_SERIAL_JTAG_MEM_CONF_REG register
- *  Memory power control
- */
-#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
- *  1: power down usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
- *  1: Force clock on for usb memory.
- */
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-
-/** USB_SERIAL_JTAG_CHIP_RST_REG register
- *  CDC-ACM chip reset control.
- */
-#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
-/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
- *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_RTS    (BIT(0))
-#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
-#define USB_SERIAL_JTAG_RTS_V  0x00000001U
-#define USB_SERIAL_JTAG_RTS_S  0
-/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
- *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
- */
-#define USB_SERIAL_JTAG_DTR    (BIT(1))
-#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
-#define USB_SERIAL_JTAG_DTR_V  0x00000001U
-#define USB_SERIAL_JTAG_DTR_S  1
-/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
- *  Set this bit to disable chip reset from usb serial channel to reset chip.
- */
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
- *  W0 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
-/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
- *  W1 of SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
-/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
-/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by host through SET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_BDATA_BITS_S  16
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
- *  W0 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
-/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
- *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
-
-/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
- *  W1 of GET_LINE_CODING command.
- */
-#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
-/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
- *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
-/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
- *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
-/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
- *  The value of bDataBits set by software which is requested by GET_LINE_CODING
- *  command.
- */
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
-#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
-
-/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
- *  Configuration registers' value update
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
-/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
- *  Write 1 to this register would update the value of configure registers from APB
- *  clock domain to 48MHz clock domain.
- */
-#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
-#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
-
-/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
- *  Serial AFIFO configure register
- */
-#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
- *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
- *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
-/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
-/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
- *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
- */
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
-#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
-
-/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
- *  USB Bus reset status register
- */
-#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
-/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
- *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
- *  reset is released.
- */
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
-#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
-
-/** USB_SERIAL_JTAG_ECO_LOW_48_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
-/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RND_ECO_LOW_48    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M  (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S)
-#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S  0
-
-/** USB_SERIAL_JTAG_ECO_HIGH_48_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
-/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_48    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S)
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S  0
-
-/** USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74)
-/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RDN_RESULT_48    (BIT(0))
-#define USB_SERIAL_JTAG_RDN_RESULT_48_M  (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S)
-#define USB_SERIAL_JTAG_RDN_RESULT_48_V  0x00000001U
-#define USB_SERIAL_JTAG_RDN_RESULT_48_S  0
-/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RDN_ENA_48    (BIT(1))
-#define USB_SERIAL_JTAG_RDN_ENA_48_M  (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S)
-#define USB_SERIAL_JTAG_RDN_ENA_48_V  0x00000001U
-#define USB_SERIAL_JTAG_RDN_ENA_48_S  1
-
-/** USB_SERIAL_JTAG_ECO_LOW_APB_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78)
-/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RND_ECO_LOW_APB    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M  (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S)
-#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S  0
-
-/** USB_SERIAL_JTAG_ECO_HIGH_APB_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c)
-/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S)
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S  0
-
-/** USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG register
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RDN_RESULT_APB    (BIT(0))
-#define USB_SERIAL_JTAG_RDN_RESULT_APB_M  (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S)
-#define USB_SERIAL_JTAG_RDN_RESULT_APB_V  0x00000001U
-#define USB_SERIAL_JTAG_RDN_RESULT_APB_S  0
-/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0;
- *  Reserved.
- */
-#define USB_SERIAL_JTAG_RDN_ENA_APB    (BIT(1))
-#define USB_SERIAL_JTAG_RDN_ENA_APB_M  (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S)
-#define USB_SERIAL_JTAG_RDN_ENA_APB_V  0x00000001U
-#define USB_SERIAL_JTAG_RDN_ENA_APB_S  1
-
-/** USB_SERIAL_JTAG_SRAM_CTRL_REG register
- *  PPA SRAM Control Register
- */
-#define USB_SERIAL_JTAG_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84)
-/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
- *  Control signals
- */
-#define USB_SERIAL_JTAG_MEM_AUX_CTRL    0x00003FFFU
-#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M  (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S)
-#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V  0x00003FFFU
-#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S  0
-
-/** USB_SERIAL_JTAG_DATE_REG register
- *  Date register
- */
-#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88)
-/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752;
- *  register version.
- */
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
-#define USB_SERIAL_JTAG_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/include/soc/usb_wrap_struct.h b/components/soc/esp32p4/include/soc/usb_wrap_struct.h
deleted file mode 100644
index b5f36b526db..00000000000
--- a/components/soc/esp32p4/include/soc/usb_wrap_struct.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: USB wrapper registers. */
-/** Type of otg_conf register
- *  USB wrapper configuration registers.
- */
-typedef union {
-    struct {
-        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
-         *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
-         *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
-         *  software.
-         */
-        uint32_t srp_sessend_override:1;
-        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
-         *  Software over-ride value of srp session end signal.
-         */
-        uint32_t srp_sessend_value:1;
-        /** phy_sel : R/W; bitpos: [2]; default: 0;
-         *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
-         */
-        uint32_t phy_sel:1;
-        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
-         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
-         */
-        uint32_t dfifo_force_pd:1;
-        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
-         *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
-         */
-        uint32_t dbnce_fltr_bypass:1;
-        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
-         *  Enable software controlle USB D+ D- exchange
-         */
-        uint32_t exchg_pins_override:1;
-        /** exchg_pins : R/W; bitpos: [6]; default: 0;
-         *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
-         */
-        uint32_t exchg_pins:1;
-        /** vrefh : R/W; bitpos: [8:7]; default: 0;
-         *  Control single-end input high threshold,1.76V to 2V, step 80mV.
-         */
-        uint32_t vrefh:2;
-        /** vrefl : R/W; bitpos: [10:9]; default: 0;
-         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
-         */
-        uint32_t vrefl:2;
-        /** vref_override : R/W; bitpos: [11]; default: 0;
-         *  Enable software controlle input  threshold.
-         */
-        uint32_t vref_override:1;
-        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
-         *  Enable software controlle USB D+ D- pullup pulldown.
-         */
-        uint32_t pad_pull_override:1;
-        /** dp_pullup : R/W; bitpos: [13]; default: 0;
-         *  Controlle USB D+ pullup.
-         */
-        uint32_t dp_pullup:1;
-        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
-         *  Controlle USB D+ pulldown.
-         */
-        uint32_t dp_pulldown:1;
-        /** dm_pullup : R/W; bitpos: [15]; default: 0;
-         *  Controlle USB D+ pullup.
-         */
-        uint32_t dm_pullup:1;
-        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
-         *  Controlle USB D+ pulldown.
-         */
-        uint32_t dm_pulldown:1;
-        /** pullup_value : R/W; bitpos: [17]; default: 0;
-         *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
-         */
-        uint32_t pullup_value:1;
-        /** usb_pad_enable : R/W; bitpos: [18]; default: 0;
-         *  Enable USB pad function.
-         */
-        uint32_t usb_pad_enable:1;
-        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
-         *  Force ahb clock always on.
-         */
-        uint32_t ahb_clk_force_on:1;
-        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
-         *  Force phy clock always on.
-         */
-        uint32_t phy_clk_force_on:1;
-        /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
-         *  Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
-         */
-        uint32_t phy_tx_edge_sel:1;
-        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
-         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
-         */
-        uint32_t dfifo_force_pu:1;
-        uint32_t reserved_23:8;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Disable auto clock gating of CSR registers.
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} usb_wrap_otg_conf_reg_t;
-
-/** Type of test_conf register
- *  TEST relative configuration registers.
- */
-typedef union {
-    struct {
-        /** test_enable : R/W; bitpos: [0]; default: 0;
-         *  Enable to test the USB pad.
-         */
-        uint32_t test_enable:1;
-        /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
-         *  USB pad one in test.
-         */
-        uint32_t test_usb_wrap_oe:1;
-        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
-         *  USB D+ tx value in test.
-         */
-        uint32_t test_tx_dp:1;
-        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
-         *  USB D- tx value in test.
-         */
-        uint32_t test_tx_dm:1;
-        /** test_rx_rcv : RO; bitpos: [4]; default: 0;
-         *  USB differential rx value in test.
-         */
-        uint32_t test_rx_rcv:1;
-        /** test_rx_dp : RO; bitpos: [5]; default: 0;
-         *  USB D+ rx value in test.
-         */
-        uint32_t test_rx_dp:1;
-        /** test_rx_dm : RO; bitpos: [6]; default: 0;
-         *  USB D- rx value in test.
-         */
-        uint32_t test_rx_dm:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} usb_wrap_test_conf_reg_t;
-
-/** Type of date register
- *  Date register.
- */
-typedef union {
-    struct {
-        /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
-         *  Date register.
-         */
-        uint32_t usb_wrap_date:32;
-    };
-    uint32_t val;
-} usb_wrap_date_reg_t;
-
-
-typedef struct usb_wrap_dev_t {
-    volatile usb_wrap_otg_conf_reg_t otg_conf;
-    volatile usb_wrap_test_conf_reg_t test_conf;
-    uint32_t reserved_008[253];
-    volatile usb_wrap_date_reg_t date;
-} usb_wrap_dev_t;
-
-extern usb_wrap_dev_t USB_WRAP;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
index fd880fc50ae..e82a48159e1 100644
--- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld
+++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
@@ -116,6 +116,7 @@ PROVIDE ( USB_DWC_FS         = 0x50040000 );
 PROVIDE ( USB_UTMI           = 0x5009C000 );
 
 PROVIDE ( EMAC_MAC           = 0x50098000 );
+PROVIDE ( EMAC_PTP           = 0x50098700 );
 PROVIDE ( EMAC_DMA           = 0x50099000 );
 
 PROVIDE ( CACHE              = 0x3FF10000);
diff --git a/components/soc/esp32p4/ledc_periph.c b/components/soc/esp32p4/ledc_periph.c
index 6258f357a50..11a073f72b3 100644
--- a/components/soc/esp32p4/ledc_periph.c
+++ b/components/soc/esp32p4/ledc_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,3 +15,162 @@ const ledc_signal_conn_t ledc_periph_signal[1] = {
         .sig_out0_idx = LEDC_LS_SIG_OUT_PAD_OUT0_IDX,
     }
 };
+
+/**
+ * LEDC registers to be saved for sleep retention
+ *
+ * channel:
+ * LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
+ * LEDC_CHx_GAMMA_CONF_REG, LEDC_CHx_GAMMA_RANGEi_REG
+ *
+ * timer:
+ * LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
+ *
+ * common:
+ * LEDC_INT_ENA_REG,
+ * LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
+ * LEDC_CONF_REG,
+ *
+ * Note 1: Gamma parameter registers are backuped and restored. But we won't start a fade automatically after wake-up.
+ *         Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep.
+ *
+ * Note 2: For timer/channel registers to get synced, update bits need to be set
+ *
+ * Note 3: Gamma RAM registers R/W relies both APB and function clock, therefore, retention requires the existence of function clock
+ */
+#define LEDC_COMMON_RETENTION_REGS_CNT  5
+#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
+static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x400, 0x0, 0x0};
+static const regdma_entries_config_t ledc_common_regdma_entries[] = {
+    // If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
+    // Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
+    [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
+			 							    LEDC_INT_ENA_REG, 0,
+			 							    (LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M | LEDC_DUTY_CHNG_END_CH6_INT_ENA_M | LEDC_DUTY_CHNG_END_CH7_INT_ENA_M), 0, 1),
+		    .owner = LEDC_RETENTION_ENTRY },
+    [1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
+                                               LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
+                                               LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
+                                               ledc_common_regs_map[0], ledc_common_regs_map[1],
+                                               ledc_common_regs_map[2], ledc_common_regs_map[3]),
+            .owner = LEDC_RETENTION_ENTRY },
+};
+
+#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
+	[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
+			 								     LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+			 								     LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
+			 								     1, 0, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
+			 							    LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
+static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
+static const uint32_t ledc_channel_gamma_regs_map[4] = {0xffff, 0x0, 0x0, 0x0};
+#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
+	[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
+                                               LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
+                                               LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
+                                               ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
+                                               ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+    [1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
+                                                 LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+	[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
+			 							    LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
+			 							    LEDC_DUTY_START_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+	[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
+			 							    LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
+			 							    LEDC_PARA_UP_CH##chan##_M, 1, 0), \
+		    .owner = LEDC_RETENTION_ENTRY }, \
+    [4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \
+                                                 LEDC_CH##chan##_GAMMA_CONF_REG, LEDC_CH##chan##_GAMMA_CONF_REG, \
+                                                 1, 0, 0), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+    [5] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x05), \
+                                               LEDC_CH##chan##_GAMMA_RANGE0_REG, LEDC_CH##chan##_GAMMA_RANGE0_REG, \
+                                               SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX, 0, 0, \
+                                               ledc_channel_gamma_regs_map[0], ledc_channel_gamma_regs_map[1], \
+                                               ledc_channel_gamma_regs_map[2], ledc_channel_gamma_regs_map[3]), \
+            .owner = LEDC_RETENTION_ENTRY }, \
+}
+
+static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
+
+static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
+static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
+static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
+static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
+static const regdma_entries_config_t ledc_channel6_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(6);
+static const regdma_entries_config_t ledc_channel7_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(7);
+
+const ledc_reg_retention_info_t ledc_reg_retention_info = {
+	.common = {
+		.regdma_entry_array = ledc_common_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
+	},
+	.timer[0] = {
+		.regdma_entry_array = ledc_timer0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
+	},
+	.timer[1] = {
+		.regdma_entry_array = ledc_timer1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
+	},
+	.timer[2] = {
+		.regdma_entry_array = ledc_timer2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
+	},
+	.timer[3] = {
+		.regdma_entry_array = ledc_timer3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
+	},
+	.channel[0] = {
+		.regdma_entry_array = ledc_channel0_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
+	},
+	.channel[1] = {
+		.regdma_entry_array = ledc_channel1_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
+	},
+	.channel[2] = {
+		.regdma_entry_array = ledc_channel2_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
+	},
+	.channel[3] = {
+		.regdma_entry_array = ledc_channel3_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
+	},
+	.channel[4] = {
+		.regdma_entry_array = ledc_channel4_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
+	},
+	.channel[5] = {
+		.regdma_entry_array = ledc_channel5_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
+	},
+    .channel[6] = {
+		.regdma_entry_array = ledc_channel6_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel6_regdma_entries),
+	},
+    .channel[7] = {
+		.regdma_entry_array = ledc_channel7_regdma_entries,
+		.array_size = ARRAY_SIZE(ledc_channel7_regdma_entries),
+	},
+	.module_id = SLEEP_RETENTION_MODULE_LEDC,
+};
diff --git a/components/soc/esp32p4/mcpwm_periph.c b/components/soc/esp32p4/mcpwm_periph.c
index 9fe408099c5..8c0cb3e444b 100644
--- a/components/soc/esp32p4/mcpwm_periph.c
+++ b/components/soc/esp32p4/mcpwm_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -150,3 +150,58 @@ const mcpwm_signal_conn_t mcpwm_periph_signals = {
         }
     }
 };
+
+#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+/**
+ * MCPWM Registers to be saved during sleep retention
+ * - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
+ * - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
+ * - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
+ *   |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
+ *   |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
+ *   |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
+ *   └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
+ * - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
+ * - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
+ * - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
+ * - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
+*/
+#define MCPWM_RETENTION_REGS_CNT 68
+#define MCPWM_RETENTION_REGS_BASE(i) REG_MCPWM_BASE(i)
+static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
+#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) {  \
+    /* backup stage: save configuration registers \
+       restore stage: restore the configuration registers */ \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(  \
+                REGDMA_MCPWM_LINK(0x00), \
+                MCPWM_RETENTION_REGS_BASE(mcpwm_port),  \
+                MCPWM_RETENTION_REGS_BASE(mcpwm_port), \
+                MCPWM_RETENTION_REGS_CNT, 0, 0, \
+                mcpwm_regs_map[0], mcpwm_regs_map[1], \
+                mcpwm_regs_map[2], mcpwm_regs_map[3]), \
+                .owner = ENTRY(0)}, \
+    /* restore stage: trigger a forced update of all active registers*/ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),  \
+                                                MCPWM_UPDATE_CFG_REG(mcpwm_port), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),  \
+                                                .owner = ENTRY(0) }, \
+    [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),  \
+                                                MCPWM_UPDATE_CFG_REG(mcpwm_port), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),  \
+                                                .owner = ENTRY(0) },  \
+};
+
+static const regdma_entries_config_t mcpwm0_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t mcpwm1_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(1);
+
+const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = mcpwm0_regs_retention,
+        .array_size = ARRAY_SIZE(mcpwm0_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_MCPWM0
+    },
+    [1] = {
+        .regdma_entry_array = mcpwm1_regs_retention,
+        .array_size = ARRAY_SIZE(mcpwm1_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_MCPWM1
+    },
+};
+#endif //SOC_MCPWM_SUPPORT_SLEEP_RETENTION
diff --git a/components/soc/esp32p4/parlio_periph.c b/components/soc/esp32p4/parlio_periph.c
index 5dcafc7206e..62ab0ed2957 100644
--- a/components/soc/esp32p4/parlio_periph.c
+++ b/components/soc/esp32p4/parlio_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -64,3 +64,31 @@ const parlio_signal_conn_t parlio_periph_signals = {
         },
     },
 };
+
+/**
+ * PARLIO Registers to be saved during sleep retention
+ * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG
+ * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG
+ * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG
+ * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG
+*/
+#define PARLIO_RETENTION_REGS_CNT 8
+#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0)
+static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0};
+static const regdma_entries_config_t parlio_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00),
+                                               PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE,
+                                               PARLIO_RETENTION_REGS_CNT, 0, 0,
+                                               parlio_regs_map[0], parlio_regs_map[1],
+                                               parlio_regs_map[2], parlio_regs_map[3]),
+                                               .owner = ENTRY(0)},
+};
+const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = parlio_regs_retention,
+        .array_size = ARRAY_SIZE(parlio_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_PARLIO0
+    },
+};
diff --git a/components/soc/esp32p4/pcnt_periph.c b/components/soc/esp32p4/pcnt_periph.c
index ae7d32b2fe8..4b1cbcac5c6 100644
--- a/components/soc/esp32p4/pcnt_periph.c
+++ b/components/soc/esp32p4/pcnt_periph.c
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/pcnt_periph.h"
 #include "soc/gpio_sig_map.h"
+#include "soc/pcnt_reg.h"
 
 const pcnt_signal_conn_t pcnt_periph_signals = {
     .groups = {
@@ -68,3 +69,33 @@ const pcnt_signal_conn_t pcnt_periph_signals = {
         }
     }
 };
+
+#if SOC_PCNT_SUPPORT_SLEEP_RETENTION
+/**
+ * PCNT Registers to be saved during sleep retention
+ * - Configuration registers, e.g.: PCNT_CTRL_REG, PCNT_U0_CONF0_REG, PCNT_U0_CONF1_REG, PCNT_U0_CONF2_REG, PCNT_U1_CONF0_REG...
+ * - Step Configuration registers, e.g.: PCNT_U0_CHANGE_CONF_REG, PCNT_U1_CHANGE_CONF_REG, PCNT_U2_CHANGE_CONF_REG, PCNT_U3_CHANGE_CONF_REG
+ * - Interrupt enable registers, e.g.: PCNT_INT_ENA_REG
+*/
+#define PCNT_RETENTION_REGS_CNT 18
+#define PCNT_RETENTION_REGS_BASE (DR_REG_PCNT_BASE + 0x0)
+static const uint32_t pcnt_regs_map[4] = {0x1f040fff, 0x0, 0x0, 0x0};
+static const regdma_entries_config_t pcnt_regs_retention[] = {
+    // backup stage: save configuration registers
+    // restore stage: restore the configuration registers
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \
+                                               PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \
+                                               PCNT_RETENTION_REGS_CNT, 0, 0, \
+                                               pcnt_regs_map[0], pcnt_regs_map[1], \
+                                               pcnt_regs_map[2], pcnt_regs_map[3]), \
+                                               .owner = ENTRY(0)}, \
+};
+
+const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS] = {
+    [0] = {
+        .regdma_entry_array = pcnt_regs_retention,
+        .array_size = ARRAY_SIZE(pcnt_regs_retention),
+        .retention_module = SLEEP_RETENTION_MODULE_PCNT0
+    },
+};
+#endif // SOC_PCNT_SUPPORT_SLEEP_RETENTION
diff --git a/components/soc/esp32p4/register/soc/.gitkeep b/components/soc/esp32p4/register/soc/.gitkeep
deleted file mode 100644
index e69de29bb2d..00000000000
diff --git a/components/soc/esp32p4/include/soc/adc_reg.h b/components/soc/esp32p4/register/soc/adc_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/adc_reg.h
rename to components/soc/esp32p4/register/soc/adc_reg.h
diff --git a/components/soc/esp32p4/include/soc/adc_struct.h b/components/soc/esp32p4/register/soc/adc_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/adc_struct.h
rename to components/soc/esp32p4/register/soc/adc_struct.h
diff --git a/components/soc/esp32p4/include/soc/aes_reg.h b/components/soc/esp32p4/register/soc/aes_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/aes_reg.h
rename to components/soc/esp32p4/register/soc/aes_reg.h
diff --git a/components/soc/esp32p4/include/soc/aes_struct.h b/components/soc/esp32p4/register/soc/aes_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/aes_struct.h
rename to components/soc/esp32p4/register/soc/aes_struct.h
diff --git a/components/soc/esp32p4/include/soc/ahb_dma_reg.h b/components/soc/esp32p4/register/soc/ahb_dma_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/ahb_dma_reg.h
rename to components/soc/esp32p4/register/soc/ahb_dma_reg.h
diff --git a/components/soc/esp32p4/include/soc/ahb_dma_struct.h b/components/soc/esp32p4/register/soc/ahb_dma_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/ahb_dma_struct.h
rename to components/soc/esp32p4/register/soc/ahb_dma_struct.h
diff --git a/components/soc/esp32p4/register/soc/assist_debug_reg.h b/components/soc/esp32p4/register/soc/assist_debug_reg.h
new file mode 100644
index 00000000000..f8f13c35319
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/assist_debug_reg.h
@@ -0,0 +1,1399 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
+ *  core0 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 dram0 region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
+ *  core0 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 dram0 region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
+ *  core0 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core0 PIF region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
+ *  core0 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core0 PIF region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
+ *  core0 area pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  the stackpointer when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
+ *  core0 area sp status register
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
+/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  the PC when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core0 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core0 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
+
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_0_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  reg_core_0_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
+ *  reg_core_0_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  1
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
+ *  reg_core_0_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_0_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  1
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_0_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_0_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CORE_1_INTR_ENA_REG register
+ *  core1 monitor enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_RAW_REG register
+ *  core1 monitor interrupt status register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt status
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_RLS_REG register
+ *  core1 monitor interrupt enable register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt enable
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S  9
+
+/** ASSIST_DEBUG_CORE_1_INTR_CLR_REG register
+ *  core1 monitor interrupt clr register
+ */
+#define ASSIST_DEBUG_CORE_1_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8c)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt clr
+ */
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S  9
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG register
+ *  core1 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 dram0 region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG register
+ *  core1 dram0 region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 dram0 region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG register
+ *  core1 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 dram0 region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG register
+ *  core1 dram0 region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x9c)
+/** ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 dram0 region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG register
+ *  core1 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa0)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 PIF region0 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG register
+ *  core1 PIF region0 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa4)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 PIF region0 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG register
+ *  core1 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xa8)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Core1 PIF region1 start addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG register
+ *  core1 PIF region1 addr configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xac)
+/** ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Core1 PIF region1 end addr
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_PC_REG register
+ *  core1 area pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb0)
+/** ASSIST_DEBUG_CORE_1_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  the stackpointer when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PC_M  (ASSIST_DEBUG_CORE_1_AREA_PC_V << ASSIST_DEBUG_CORE_1_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_1_AREA_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_PC_S  0
+
+/** ASSIST_DEBUG_CORE_1_AREA_SP_REG register
+ *  core1 area sp status register
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb4)
+/** ASSIST_DEBUG_CORE_1_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  the PC when first touch region monitor interrupt
+ */
+#define ASSIST_DEBUG_CORE_1_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_SP_M  (ASSIST_DEBUG_CORE_1_AREA_SP_V << ASSIST_DEBUG_CORE_1_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_1_AREA_SP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_AREA_SP_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_MIN_REG register
+ *  stack min value
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xb8)
+/** ASSIST_DEBUG_CORE_1_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  core1 sp region configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MIN_M  (ASSIST_DEBUG_CORE_1_SP_MIN_V << ASSIST_DEBUG_CORE_1_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_1_SP_MIN_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MIN_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_MAX_REG register
+ *  stack max value
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0xbc)
+/** ASSIST_DEBUG_CORE_1_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  core1 sp pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MAX_M  (ASSIST_DEBUG_CORE_1_SP_MAX_V << ASSIST_DEBUG_CORE_1_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_1_SP_MAX_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_MAX_S  0
+
+/** ASSIST_DEBUG_CORE_1_SP_PC_REG register
+ *  stack monitor pc status register
+ */
+#define ASSIST_DEBUG_CORE_1_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc0)
+/** ASSIST_DEBUG_CORE_1_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the PC when trigger stack monitor.
+ */
+#define ASSIST_DEBUG_CORE_1_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_PC_M  (ASSIST_DEBUG_CORE_1_SP_PC_V << ASSIST_DEBUG_CORE_1_SP_PC_S)
+#define ASSIST_DEBUG_CORE_1_SP_PC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_SP_PC_S  0
+
+/** ASSIST_DEBUG_CORE_1_RCD_EN_REG register
+ *  record enable configuration register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc4)
+/** ASSIST_DEBUG_CORE_1_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable record PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_1_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_1_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN_S  1
+
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc8)
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  recorded PC
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S  0
+
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG register
+ *  record status register
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0xcc)
+/** ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  recorded sp
+ */
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSP_S  0
+
+/** ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd0)
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_iram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  reg_core_1_iram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S  24
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  reg_core_1_iram0_recording_loadstore_0
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S  25
+
+/** ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd4)
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_iram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  reg_core_1_iram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S  24
+/** ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  reg_core_1_iram0_recording_loadstore_1
+ */
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S  25
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register2
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0xd8)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0;
+ *  reg_core_1_dram0_recording_wr_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S  0
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_1_dram0_recording_byteen_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S  1
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register3
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0xdc)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_dram0_recording_addr_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  exception monitor status register4
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe0)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_1_dram0_recording_pc_0
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  exception monitor status register5
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe4)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0;
+ *  reg_core_1_dram0_recording_wr_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S  0
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [16:1]; default: 0;
+ *  reg_core_1_dram0_recording_byteen_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1    0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V  0x0000FFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S  1
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0xe8)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  reg_core_1_dram0_recording_addr_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S  0
+
+/** ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0xec)
+/** ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  reg_core_1_dram0_recording_pc_1
+ */
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S  0
+
+/** ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0xf0)
+/** ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  cpu's lastpc before exception
+ */
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_1_LASTPC_BEFORE_EXC_S  0
+
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0xf4)
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  cpu debug mode status, 1 means cpu enter debug mode.
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_1_DEBUG_MODE_V << ASSIST_DEBUG_CORE_1_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  cpu debug_module active status
+ */
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_1_DEBUG_MODULE_ACTIVE_S  1
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register6
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_0
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  exception monitor status register7
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_1
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+/** ASSIST_DEBUG_CLOCK_GATE_REG register
+ *  clock register
+ */
+#define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108)
+/** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Set 1 force on the clock gate
+ */
+#define ASSIST_DEBUG_CLK_EN    (BIT(0))
+#define ASSIST_DEBUG_CLK_EN_M  (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S)
+#define ASSIST_DEBUG_CLK_EN_V  0x00000001U
+#define ASSIST_DEBUG_CLK_EN_S  0
+
+/** ASSIST_DEBUG_DATE_REG register
+ *  version register
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc)
+/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176;
+ *  version register
+ */
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/assist_debug_struct.h b/components/soc/esp32p4/register/soc/assist_debug_struct.h
new file mode 100644
index 00000000000..645e5a1cf08
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/assist_debug_struct.h
@@ -0,0 +1,1316 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: monitor configuration registers */
+/** Type of core_0_intr_ena register
+ *  core0 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor enable
+         */
+        uint32_t core_0_area_dram0_0_rd_ena:1;
+        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor enable
+         */
+        uint32_t core_0_area_dram0_0_wr_ena:1;
+        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor enable
+         */
+        uint32_t core_0_area_dram0_1_rd_ena:1;
+        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor enable
+         */
+        uint32_t core_0_area_dram0_1_wr_ena:1;
+        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor enable
+         */
+        uint32_t core_0_area_pif_0_rd_ena:1;
+        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor enable
+         */
+        uint32_t core_0_area_pif_0_wr_ena:1;
+        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor enable
+         */
+        uint32_t core_0_area_pif_1_rd_ena:1;
+        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor enable
+         */
+        uint32_t core_0_area_pif_1_wr_ena:1;
+        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor enable
+         */
+        uint32_t core_0_sp_spill_min_ena:1;
+        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor enable
+         */
+        uint32_t core_0_sp_spill_max_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_ena_reg_t;
+
+/** Type of core_0_area_dram0_0_min register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region0 start addr
+         */
+        uint32_t core_0_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_min_reg_t;
+
+/** Type of core_0_area_dram0_0_max register
+ *  core0 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region0 end addr
+         */
+        uint32_t core_0_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_0_max_reg_t;
+
+/** Type of core_0_area_dram0_1_min register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 dram0 region1 start addr
+         */
+        uint32_t core_0_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_min_reg_t;
+
+/** Type of core_0_area_dram0_1_max register
+ *  core0 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 dram0 region1 end addr
+         */
+        uint32_t core_0_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_dram0_1_max_reg_t;
+
+/** Type of core_0_area_pif_0_min register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region0 start addr
+         */
+        uint32_t core_0_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_min_reg_t;
+
+/** Type of core_0_area_pif_0_max register
+ *  core0 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region0 end addr
+         */
+        uint32_t core_0_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_0_max_reg_t;
+
+/** Type of core_0_area_pif_1_min register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core0 PIF region1 start addr
+         */
+        uint32_t core_0_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_min_reg_t;
+
+/** Type of core_0_area_pif_1_max register
+ *  core0 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core0 PIF region1 end addr
+         */
+        uint32_t core_0_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pif_1_max_reg_t;
+
+/** Type of core_0_area_pc register
+ *  core0 area pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  the stackpointer when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_pc_reg_t;
+
+/** Type of core_0_area_sp register
+ *  core0 area sp status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  the PC when first touch region monitor interrupt
+         */
+        uint32_t core_0_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_area_sp_reg_t;
+
+/** Type of core_0_sp_min register
+ *  stack min value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  core0 sp region configuration register
+         */
+        uint32_t core_0_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_min_reg_t;
+
+/** Type of core_0_sp_max register
+ *  stack max value
+ */
+typedef union {
+    struct {
+        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  core0 sp pc status register
+         */
+        uint32_t core_0_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_max_reg_t;
+
+/** Type of core_0_sp_pc register
+ *  stack monitor pc status register
+ */
+typedef union {
+    struct {
+        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the PC when trigger stack monitor.
+         */
+        uint32_t core_0_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_sp_pc_reg_t;
+
+/** Type of core_1_intr_ena register
+ *  core1 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor enable
+         */
+        uint32_t core_1_area_dram0_0_rd_ena:1;
+        /** core_1_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor enable
+         */
+        uint32_t core_1_area_dram0_0_wr_ena:1;
+        /** core_1_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor enable
+         */
+        uint32_t core_1_area_dram0_1_rd_ena:1;
+        /** core_1_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor enable
+         */
+        uint32_t core_1_area_dram0_1_wr_ena:1;
+        /** core_1_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor enable
+         */
+        uint32_t core_1_area_pif_0_rd_ena:1;
+        /** core_1_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor enable
+         */
+        uint32_t core_1_area_pif_0_wr_ena:1;
+        /** core_1_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor enable
+         */
+        uint32_t core_1_area_pif_1_rd_ena:1;
+        /** core_1_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor enable
+         */
+        uint32_t core_1_area_pif_1_wr_ena:1;
+        /** core_1_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor enable
+         */
+        uint32_t core_1_sp_spill_min_ena:1;
+        /** core_1_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor enable
+         */
+        uint32_t core_1_sp_spill_max_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_ena_reg_t;
+
+/** Type of core_1_area_dram0_0_min register
+ *  core1 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 dram0 region0 start addr
+         */
+        uint32_t core_1_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_0_min_reg_t;
+
+/** Type of core_1_area_dram0_0_max register
+ *  core1 dram0 region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 dram0 region0 end addr
+         */
+        uint32_t core_1_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_0_max_reg_t;
+
+/** Type of core_1_area_dram0_1_min register
+ *  core1 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 dram0 region1 start addr
+         */
+        uint32_t core_1_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_1_min_reg_t;
+
+/** Type of core_1_area_dram0_1_max register
+ *  core1 dram0 region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 dram0 region1 end addr
+         */
+        uint32_t core_1_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_dram0_1_max_reg_t;
+
+/** Type of core_1_area_pif_0_min register
+ *  core1 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 PIF region0 start addr
+         */
+        uint32_t core_1_area_pif_0_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_0_min_reg_t;
+
+/** Type of core_1_area_pif_0_max register
+ *  core1 PIF region0 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 PIF region0 end addr
+         */
+        uint32_t core_1_area_pif_0_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_0_max_reg_t;
+
+/** Type of core_1_area_pif_1_min register
+ *  core1 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Core1 PIF region1 start addr
+         */
+        uint32_t core_1_area_pif_1_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_1_min_reg_t;
+
+/** Type of core_1_area_pif_1_max register
+ *  core1 PIF region1 addr configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Core1 PIF region1 end addr
+         */
+        uint32_t core_1_area_pif_1_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pif_1_max_reg_t;
+
+/** Type of core_1_area_pc register
+ *  core1 area pc status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  the stackpointer when first touch region monitor interrupt
+         */
+        uint32_t core_1_area_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_pc_reg_t;
+
+/** Type of core_1_area_sp register
+ *  core1 area sp status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  the PC when first touch region monitor interrupt
+         */
+        uint32_t core_1_area_sp:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_area_sp_reg_t;
+
+/** Type of core_1_sp_min register
+ *  stack min value
+ */
+typedef union {
+    struct {
+        /** core_1_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  core1 sp region configuration register
+         */
+        uint32_t core_1_sp_min:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_min_reg_t;
+
+/** Type of core_1_sp_max register
+ *  stack max value
+ */
+typedef union {
+    struct {
+        /** core_1_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  core1 sp pc status register
+         */
+        uint32_t core_1_sp_max:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_max_reg_t;
+
+/** Type of core_1_sp_pc register
+ *  stack monitor pc status register
+ */
+typedef union {
+    struct {
+        /** core_1_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the PC when trigger stack monitor.
+         */
+        uint32_t core_1_sp_pc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_sp_pc_reg_t;
+
+
+/** Group: interrupt configuration register */
+/** Type of core_0_intr_raw register
+ *  core0 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_rd_raw:1;
+        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_0_wr_raw:1;
+        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_rd_raw:1;
+        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_dram0_1_wr_raw:1;
+        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_rd_raw:1;
+        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_0_wr_raw:1;
+        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_rd_raw:1;
+        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt status
+         */
+        uint32_t core_0_area_pif_1_wr_raw:1;
+        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_min_raw:1;
+        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt status
+         */
+        uint32_t core_0_sp_spill_max_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_raw_reg_t;
+
+/** Type of core_0_intr_rls register
+ *  core0 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_rd_rls:1;
+        /** core_0_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_wr_rls:1;
+        /** core_0_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_rd_rls:1;
+        /** core_0_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_wr_rls:1;
+        /** core_0_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_rd_rls:1;
+        /** core_0_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_wr_rls:1;
+        /** core_0_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_rd_rls:1;
+        /** core_0_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_wr_rls:1;
+        /** core_0_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_min_rls:1;
+        /** core_0_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_max_rls:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_rls_reg_t;
+
+/** Type of core_0_intr_clr register
+ *  core0 monitor interrupt clr register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_rd_clr:1;
+        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_0_wr_clr:1;
+        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_rd_clr:1;
+        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_dram0_1_wr_clr:1;
+        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_rd_clr:1;
+        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_0_wr_clr:1;
+        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_rd_clr:1;
+        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt clr
+         */
+        uint32_t core_0_area_pif_1_wr_clr:1;
+        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_min_clr:1;
+        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt clr
+         */
+        uint32_t core_0_sp_spill_max_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_0_intr_clr_reg_t;
+
+/** Type of core_1_intr_raw register
+ *  core1 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_0_rd_raw:1;
+        /** core_1_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_0_wr_raw:1;
+        /** core_1_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_1_rd_raw:1;
+        /** core_1_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt status
+         */
+        uint32_t core_1_area_dram0_1_wr_raw:1;
+        /** core_1_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt status
+         */
+        uint32_t core_1_area_pif_0_rd_raw:1;
+        /** core_1_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt status
+         */
+        uint32_t core_1_area_pif_0_wr_raw:1;
+        /** core_1_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt status
+         */
+        uint32_t core_1_area_pif_1_rd_raw:1;
+        /** core_1_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt status
+         */
+        uint32_t core_1_area_pif_1_wr_raw:1;
+        /** core_1_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt status
+         */
+        uint32_t core_1_sp_spill_min_raw:1;
+        /** core_1_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt status
+         */
+        uint32_t core_1_sp_spill_max_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_raw_reg_t;
+
+/** Type of core_1_intr_rls register
+ *  core1 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_rls : R/W; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_0_rd_rls:1;
+        /** core_1_area_dram0_0_wr_rls : R/W; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_0_wr_rls:1;
+        /** core_1_area_dram0_1_rd_rls : R/W; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_1_rd_rls:1;
+        /** core_1_area_dram0_1_wr_rls : R/W; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_1_wr_rls:1;
+        /** core_1_area_pif_0_rd_rls : R/W; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_0_rd_rls:1;
+        /** core_1_area_pif_0_wr_rls : R/W; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_0_wr_rls:1;
+        /** core_1_area_pif_1_rd_rls : R/W; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_1_rd_rls:1;
+        /** core_1_area_pif_1_wr_rls : R/W; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_1_wr_rls:1;
+        /** core_1_sp_spill_min_rls : R/W; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_1_sp_spill_min_rls:1;
+        /** core_1_sp_spill_max_rls : R/W; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_1_sp_spill_max_rls:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_rls_reg_t;
+
+/** Type of core_1_intr_clr register
+ *  core1 monitor interrupt clr register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_0_rd_clr:1;
+        /** core_1_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_0_wr_clr:1;
+        /** core_1_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_1_rd_clr:1;
+        /** core_1_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt clr
+         */
+        uint32_t core_1_area_dram0_1_wr_clr:1;
+        /** core_1_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_0_rd_clr:1;
+        /** core_1_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_0_wr_clr:1;
+        /** core_1_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_1_rd_clr:1;
+        /** core_1_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt clr
+         */
+        uint32_t core_1_area_pif_1_wr_clr:1;
+        /** core_1_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt clr
+         */
+        uint32_t core_1_sp_spill_min_clr:1;
+        /** core_1_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt clr
+         */
+        uint32_t core_1_sp_spill_max_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} assist_debug_core_1_intr_clr_reg_t;
+
+
+/** Group: pc recording configuration register */
+/** Type of core_0_rcd_en register
+ *  record enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable record PC
+         */
+        uint32_t core_0_rcd_recorden:1;
+        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+         */
+        uint32_t core_0_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_en_reg_t;
+
+/** Type of core_1_rcd_en register
+ *  record enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable record PC
+         */
+        uint32_t core_1_rcd_recorden:1;
+        /** core_1_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable cpu pdebug function, must set this bit can get cpu PC
+         */
+        uint32_t core_1_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_en_reg_t;
+
+
+/** Group: pc recording status register */
+/** Type of core_0_rcd_pdebugpc register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  recorded PC
+         */
+        uint32_t core_0_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugpc_reg_t;
+
+/** Type of core_0_rcd_pdebugsp register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  recorded sp
+         */
+        uint32_t core_0_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_rcd_pdebugsp_reg_t;
+
+/** Type of core_1_rcd_pdebugpc register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  recorded PC
+         */
+        uint32_t core_1_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_pdebugpc_reg_t;
+
+/** Type of core_1_rcd_pdebugsp register
+ *  record status register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  recorded sp
+         */
+        uint32_t core_1_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_rcd_pdebugsp_reg_t;
+
+
+/** Group: exception monitor register */
+/** Type of core_0_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_0
+         */
+        uint32_t core_0_iram0_recording_addr_0:24;
+        /** core_0_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_0
+         */
+        uint32_t core_0_iram0_recording_wr_0:1;
+        /** core_0_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_0
+         */
+        uint32_t core_0_iram0_recording_loadstore_0:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_iram0_recording_addr_1
+         */
+        uint32_t core_0_iram0_recording_addr_1:24;
+        /** core_0_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_0_iram0_recording_wr_1
+         */
+        uint32_t core_0_iram0_recording_wr_1:1;
+        /** core_0_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
+         *  reg_core_0_iram0_recording_loadstore_1
+         */
+        uint32_t core_0_iram0_recording_loadstore_1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_0_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
+         *  reg_core_0_dram0_recording_wr_0
+         */
+        uint32_t core_0_dram0_recording_wr_0:1;
+        /** core_0_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_0
+         */
+        uint32_t core_0_dram0_recording_byteen_0:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_0
+         */
+        uint32_t core_0_dram0_recording_addr_0:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_0
+         */
+        uint32_t core_0_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
+         *  reg_core_0_dram0_recording_wr_1
+         */
+        uint32_t core_0_dram0_recording_wr_1:1;
+        /** core_0_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_0_dram0_recording_byteen_1
+         */
+        uint32_t core_0_dram0_recording_byteen_1:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_4 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_0_dram0_recording_addr_1
+         */
+        uint32_t core_0_dram0_recording_addr_1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_4_reg_t;
+
+/** Type of core_0_dram0_exception_monitor_5 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_0_dram0_recording_pc_1
+         */
+        uint32_t core_0_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_dram0_exception_monitor_5_reg_t;
+
+/** Type of core_1_iram0_exception_monitor_0 register
+ *  exception monitor status register0
+ */
+typedef union {
+    struct {
+        /** core_1_iram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_iram0_recording_addr_0
+         */
+        uint32_t core_1_iram0_recording_addr_0:24;
+        /** core_1_iram0_recording_wr_0 : RO; bitpos: [24]; default: 0;
+         *  reg_core_1_iram0_recording_wr_0
+         */
+        uint32_t core_1_iram0_recording_wr_0:1;
+        /** core_1_iram0_recording_loadstore_0 : RO; bitpos: [25]; default: 0;
+         *  reg_core_1_iram0_recording_loadstore_0
+         */
+        uint32_t core_1_iram0_recording_loadstore_0:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_1_iram0_exception_monitor_0_reg_t;
+
+/** Type of core_1_iram0_exception_monitor_1 register
+ *  exception monitor status register1
+ */
+typedef union {
+    struct {
+        /** core_1_iram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_iram0_recording_addr_1
+         */
+        uint32_t core_1_iram0_recording_addr_1:24;
+        /** core_1_iram0_recording_wr_1 : RO; bitpos: [24]; default: 0;
+         *  reg_core_1_iram0_recording_wr_1
+         */
+        uint32_t core_1_iram0_recording_wr_1:1;
+        /** core_1_iram0_recording_loadstore_1 : RO; bitpos: [25]; default: 0;
+         *  reg_core_1_iram0_recording_loadstore_1
+         */
+        uint32_t core_1_iram0_recording_loadstore_1:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} assist_debug_core_1_iram0_exception_monitor_1_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_0 register
+ *  exception monitor status register2
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_wr_0 : RO; bitpos: [0]; default: 0;
+         *  reg_core_1_dram0_recording_wr_0
+         */
+        uint32_t core_1_dram0_recording_wr_0:1;
+        /** core_1_dram0_recording_byteen_0 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_1_dram0_recording_byteen_0
+         */
+        uint32_t core_1_dram0_recording_byteen_0:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_1 register
+ *  exception monitor status register3
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_addr_0 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_dram0_recording_addr_0
+         */
+        uint32_t core_1_dram0_recording_addr_0:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_1_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_2 register
+ *  exception monitor status register4
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_pc_0 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_1_dram0_recording_pc_0
+         */
+        uint32_t core_1_dram0_recording_pc_0:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_2_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_3 register
+ *  exception monitor status register5
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_wr_1 : RO; bitpos: [0]; default: 0;
+         *  reg_core_1_dram0_recording_wr_1
+         */
+        uint32_t core_1_dram0_recording_wr_1:1;
+        /** core_1_dram0_recording_byteen_1 : RO; bitpos: [16:1]; default: 0;
+         *  reg_core_1_dram0_recording_byteen_1
+         */
+        uint32_t core_1_dram0_recording_byteen_1:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_3_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_4 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_addr_1 : RO; bitpos: [23:0]; default: 0;
+         *  reg_core_1_dram0_recording_addr_1
+         */
+        uint32_t core_1_dram0_recording_addr_1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_4_reg_t;
+
+/** Type of core_1_dram0_exception_monitor_5 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_1_dram0_recording_pc_1 : RO; bitpos: [31:0]; default: 0;
+         *  reg_core_1_dram0_recording_pc_1
+         */
+        uint32_t core_1_dram0_recording_pc_1:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_dram0_exception_monitor_5_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_0 register
+ *  exception monitor status register6
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_0
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t;
+
+/** Type of core_x_iram0_dram0_exception_monitor_1 register
+ *  exception monitor status register7
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_1 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_1
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_1:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t;
+
+
+/** Group: cpu status registers */
+/** Type of core_0_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  cpu's lastpc before exception
+         */
+        uint32_t core_0_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_0_lastpc_before_exception_reg_t;
+
+/** Type of core_0_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
+         *  cpu debug mode status, 1 means cpu enter debug mode.
+         */
+        uint32_t core_0_debug_mode:1;
+        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  cpu debug_module active status
+         */
+        uint32_t core_0_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_0_debug_mode_reg_t;
+
+/** Type of core_1_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_1_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  cpu's lastpc before exception
+         */
+        uint32_t core_1_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} assist_debug_core_1_lastpc_before_exception_reg_t;
+
+/** Type of core_1_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_1_debug_mode : RO; bitpos: [0]; default: 0;
+         *  cpu debug mode status, 1 means cpu enter debug mode.
+         */
+        uint32_t core_1_debug_mode:1;
+        /** core_1_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  cpu debug_module active status
+         */
+        uint32_t core_1_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} assist_debug_core_1_debug_mode_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clock_gate register
+ *  clock register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Set 1 force on the clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} assist_debug_clock_gate_reg_t;
+
+/** Type of date register
+ *  version register
+ */
+typedef union {
+    struct {
+        /** assist_debug_date : R/W; bitpos: [27:0]; default: 34640176;
+         *  version register
+         */
+        uint32_t assist_debug_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} assist_debug_date_reg_t;
+
+
+typedef struct {
+    volatile assist_debug_core_0_intr_ena_reg_t core_0_intr_ena;
+    volatile assist_debug_core_0_intr_raw_reg_t core_0_intr_raw;
+    volatile assist_debug_core_0_intr_rls_reg_t core_0_intr_rls;
+    volatile assist_debug_core_0_intr_clr_reg_t core_0_intr_clr;
+    volatile assist_debug_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
+    volatile assist_debug_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
+    volatile assist_debug_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
+    volatile assist_debug_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
+    volatile assist_debug_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
+    volatile assist_debug_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
+    volatile assist_debug_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
+    volatile assist_debug_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
+    volatile assist_debug_core_0_area_pc_reg_t core_0_area_pc;
+    volatile assist_debug_core_0_area_sp_reg_t core_0_area_sp;
+    volatile assist_debug_core_0_sp_min_reg_t core_0_sp_min;
+    volatile assist_debug_core_0_sp_max_reg_t core_0_sp_max;
+    volatile assist_debug_core_0_sp_pc_reg_t core_0_sp_pc;
+    volatile assist_debug_core_0_rcd_en_reg_t core_0_rcd_en;
+    volatile assist_debug_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
+    volatile assist_debug_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
+    volatile assist_debug_core_0_iram0_exception_monitor_0_reg_t core_0_iram0_exception_monitor_0;
+    volatile assist_debug_core_0_iram0_exception_monitor_1_reg_t core_0_iram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_0_reg_t core_0_dram0_exception_monitor_0;
+    volatile assist_debug_core_0_dram0_exception_monitor_1_reg_t core_0_dram0_exception_monitor_1;
+    volatile assist_debug_core_0_dram0_exception_monitor_2_reg_t core_0_dram0_exception_monitor_2;
+    volatile assist_debug_core_0_dram0_exception_monitor_3_reg_t core_0_dram0_exception_monitor_3;
+    volatile assist_debug_core_0_dram0_exception_monitor_4_reg_t core_0_dram0_exception_monitor_4;
+    volatile assist_debug_core_0_dram0_exception_monitor_5_reg_t core_0_dram0_exception_monitor_5;
+    volatile assist_debug_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
+    volatile assist_debug_core_0_debug_mode_reg_t core_0_debug_mode;
+    uint32_t reserved_078[2];
+    volatile assist_debug_core_1_intr_ena_reg_t core_1_intr_ena;
+    volatile assist_debug_core_1_intr_raw_reg_t core_1_intr_raw;
+    volatile assist_debug_core_1_intr_rls_reg_t core_1_intr_rls;
+    volatile assist_debug_core_1_intr_clr_reg_t core_1_intr_clr;
+    volatile assist_debug_core_1_area_dram0_0_min_reg_t core_1_area_dram0_0_min;
+    volatile assist_debug_core_1_area_dram0_0_max_reg_t core_1_area_dram0_0_max;
+    volatile assist_debug_core_1_area_dram0_1_min_reg_t core_1_area_dram0_1_min;
+    volatile assist_debug_core_1_area_dram0_1_max_reg_t core_1_area_dram0_1_max;
+    volatile assist_debug_core_1_area_pif_0_min_reg_t core_1_area_pif_0_min;
+    volatile assist_debug_core_1_area_pif_0_max_reg_t core_1_area_pif_0_max;
+    volatile assist_debug_core_1_area_pif_1_min_reg_t core_1_area_pif_1_min;
+    volatile assist_debug_core_1_area_pif_1_max_reg_t core_1_area_pif_1_max;
+    volatile assist_debug_core_1_area_pc_reg_t core_1_area_pc;
+    volatile assist_debug_core_1_area_sp_reg_t core_1_area_sp;
+    volatile assist_debug_core_1_sp_min_reg_t core_1_sp_min;
+    volatile assist_debug_core_1_sp_max_reg_t core_1_sp_max;
+    volatile assist_debug_core_1_sp_pc_reg_t core_1_sp_pc;
+    volatile assist_debug_core_1_rcd_en_reg_t core_1_rcd_en;
+    volatile assist_debug_core_1_rcd_pdebugpc_reg_t core_1_rcd_pdebugpc;
+    volatile assist_debug_core_1_rcd_pdebugsp_reg_t core_1_rcd_pdebugsp;
+    volatile assist_debug_core_1_iram0_exception_monitor_0_reg_t core_1_iram0_exception_monitor_0;
+    volatile assist_debug_core_1_iram0_exception_monitor_1_reg_t core_1_iram0_exception_monitor_1;
+    volatile assist_debug_core_1_dram0_exception_monitor_0_reg_t core_1_dram0_exception_monitor_0;
+    volatile assist_debug_core_1_dram0_exception_monitor_1_reg_t core_1_dram0_exception_monitor_1;
+    volatile assist_debug_core_1_dram0_exception_monitor_2_reg_t core_1_dram0_exception_monitor_2;
+    volatile assist_debug_core_1_dram0_exception_monitor_3_reg_t core_1_dram0_exception_monitor_3;
+    volatile assist_debug_core_1_dram0_exception_monitor_4_reg_t core_1_dram0_exception_monitor_4;
+    volatile assist_debug_core_1_dram0_exception_monitor_5_reg_t core_1_dram0_exception_monitor_5;
+    volatile assist_debug_core_1_lastpc_before_exception_reg_t core_1_lastpc_before_exception;
+    volatile assist_debug_core_1_debug_mode_reg_t core_1_debug_mode;
+    uint32_t reserved_0f8[2];
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
+    volatile assist_debug_core_x_iram0_dram0_exception_monitor_1_reg_t core_x_iram0_dram0_exception_monitor_1;
+    volatile assist_debug_clock_gate_reg_t clock_gate;
+    uint32_t reserved_10c[188];
+    volatile assist_debug_date_reg_t date;
+} assist_debug_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(assist_debug_dev_t) == 0x400, "Invalid size of assist_debug_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/axi_dma_reg.h b/components/soc/esp32p4/register/soc/axi_dma_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/axi_dma_reg.h
rename to components/soc/esp32p4/register/soc/axi_dma_reg.h
index e3dfc907dbd..8f2775e7959 100644
--- a/components/soc/esp32p4/include/soc/axi_dma_reg.h
+++ b/components/soc/esp32p4/register/soc/axi_dma_reg.h
@@ -770,7 +770,7 @@ extern "C" {
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH0_V  0x0000000FU
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH0_S  4
 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S)
@@ -1654,7 +1654,7 @@ extern "C" {
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH1_V  0x0000000FU
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH1_S  4
 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S)
@@ -2538,7 +2538,7 @@ extern "C" {
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH2_V  0x0000000FU
 #define AXI_DMA_RX_CH_ARB_WEIGH_CH2_S  4
 /** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
 #define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S)
@@ -3384,7 +3384,7 @@ extern "C" {
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH0_V  0x0000000FU
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH0_S  4
 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S)
@@ -4230,7 +4230,7 @@ extern "C" {
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH1_V  0x0000000FU
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH1_S  4
 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S)
@@ -5076,7 +5076,7 @@ extern "C" {
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH2_V  0x0000000FU
 #define AXI_DMA_TX_CH_ARB_WEIGH_CH2_S  4
 /** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
- *  0: mean not optimazation weight function ,1: mean optimazation
+ *  0: mean not optimization weight function ,1: mean optimization
  */
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
 #define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S)
@@ -5490,11 +5490,11 @@ extern "C" {
 #define AXI_DMA_RDN_ECO_LOW_S  0
 
 /** AXI_DMA_WRESP_CNT_REG register
- *  AXI wr responce cnt register.
+ *  AXI wr response cnt register.
  */
 #define AXI_DMA_WRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2b8)
 /** AXI_DMA_WRESP_CNT : RO; bitpos: [3:0]; default: 0;
- *  axi wr responce cnt reg.
+ *  axi wr response cnt reg.
  */
 #define AXI_DMA_WRESP_CNT    0x0000000FU
 #define AXI_DMA_WRESP_CNT_M  (AXI_DMA_WRESP_CNT_V << AXI_DMA_WRESP_CNT_S)
@@ -5502,11 +5502,11 @@ extern "C" {
 #define AXI_DMA_WRESP_CNT_S  0
 
 /** AXI_DMA_RRESP_CNT_REG register
- *  AXI wr responce cnt register.
+ *  AXI wr response cnt register.
  */
 #define AXI_DMA_RRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2bc)
 /** AXI_DMA_RRESP_CNT : RO; bitpos: [3:0]; default: 0;
- *  axi rd responce cnt reg.
+ *  axi rd response cnt reg.
  */
 #define AXI_DMA_RRESP_CNT    0x0000000FU
 #define AXI_DMA_RRESP_CNT_M  (AXI_DMA_RRESP_CNT_V << AXI_DMA_RRESP_CNT_S)
diff --git a/components/soc/esp32p4/include/soc/axi_dma_struct.h b/components/soc/esp32p4/register/soc/axi_dma_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/axi_dma_struct.h
rename to components/soc/esp32p4/register/soc/axi_dma_struct.h
diff --git a/components/soc/esp32p4/include/soc/bitscrambler_reg.h b/components/soc/esp32p4/register/soc/bitscrambler_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/bitscrambler_reg.h
rename to components/soc/esp32p4/register/soc/bitscrambler_reg.h
index 44bfc3c8745..4b8fbe5df57 100644
--- a/components/soc/esp32p4/include/soc/bitscrambler_reg.h
+++ b/components/soc/esp32p4/register/soc/bitscrambler_reg.h
@@ -216,7 +216,7 @@ extern "C" {
 #define BITSCRAMBLER_TX_COND_MODE_S  4
 /** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
  *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
- *  by reset, 1: fetch by instrutions
+ *  by reset, 1: fetch by instructions
  */
 #define BITSCRAMBLER_TX_FETCH_MODE    (BIT(5))
 #define BITSCRAMBLER_TX_FETCH_MODE_M  (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
@@ -291,7 +291,7 @@ extern "C" {
 #define BITSCRAMBLER_RX_COND_MODE_S  4
 /** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
  *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
- *  by reset, 1: fetch by instrutions
+ *  by reset, 1: fetch by instructions
  */
 #define BITSCRAMBLER_RX_FETCH_MODE    (BIT(5))
 #define BITSCRAMBLER_RX_FETCH_MODE_M  (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
diff --git a/components/soc/esp32p4/include/soc/bitscrambler_struct.h b/components/soc/esp32p4/register/soc/bitscrambler_struct.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/bitscrambler_struct.h
rename to components/soc/esp32p4/register/soc/bitscrambler_struct.h
index 007c244d505..6a451171ba1 100644
--- a/components/soc/esp32p4/include/soc/bitscrambler_struct.h
+++ b/components/soc/esp32p4/register/soc/bitscrambler_struct.h
@@ -208,7 +208,7 @@ typedef union {
         uint32_t tx_cond_mode:1;
         /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
          *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instrutions
+         *  by reset, 1: fetch by instructions
          */
         uint32_t tx_fetch_mode:1;
         /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
@@ -261,7 +261,7 @@ typedef union {
         uint32_t rx_cond_mode:1;
         /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
          *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instrutions
+         *  by reset, 1: fetch by instructions
          */
         uint32_t rx_fetch_mode:1;
         /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
diff --git a/components/soc/esp32p4/register/soc/cache_reg.h b/components/soc/esp32p4/register/soc/cache_reg.h
new file mode 100644
index 00000000000..e80afcd41bd
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/cache_reg.h
@@ -0,0 +1,6294 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CACHE_L1_ICACHE_CTRL_REG register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
+/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
+#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
+/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
+#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
+/** CACHE_L1_ICACHE_SHUT_IBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
+#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
+/** CACHE_L1_ICACHE_SHUT_IBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
+#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
+
+/** CACHE_L1_DCACHE_CTRL_REG register
+ *  L1 data Cache(L1-DCache) control register
+ */
+#define CACHE_L1_DCACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
+/** CACHE_L1_DCACHE_SHUT_DBUS0 : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to disable core0 dbus access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS0    (BIT(0))
+#define CACHE_L1_DCACHE_SHUT_DBUS0_M  (CACHE_L1_DCACHE_SHUT_DBUS0_V << CACHE_L1_DCACHE_SHUT_DBUS0_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS0_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS0_S  0
+/** CACHE_L1_DCACHE_SHUT_DBUS1 : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to disable core1 dbus access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS1    (BIT(1))
+#define CACHE_L1_DCACHE_SHUT_DBUS1_M  (CACHE_L1_DCACHE_SHUT_DBUS1_V << CACHE_L1_DCACHE_SHUT_DBUS1_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS1_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS1_S  1
+/** CACHE_L1_DCACHE_SHUT_DBUS2 : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS2    (BIT(2))
+#define CACHE_L1_DCACHE_SHUT_DBUS2_M  (CACHE_L1_DCACHE_SHUT_DBUS2_V << CACHE_L1_DCACHE_SHUT_DBUS2_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS2_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS2_S  2
+/** CACHE_L1_DCACHE_SHUT_DBUS3 : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS3    (BIT(3))
+#define CACHE_L1_DCACHE_SHUT_DBUS3_M  (CACHE_L1_DCACHE_SHUT_DBUS3_V << CACHE_L1_DCACHE_SHUT_DBUS3_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS3_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS3_S  3
+/** CACHE_L1_DCACHE_SHUT_DMA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L1_DCACHE_SHUT_DMA_M  (CACHE_L1_DCACHE_SHUT_DMA_V << CACHE_L1_DCACHE_SHUT_DMA_S)
+#define CACHE_L1_DCACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DMA_S  4
+
+/** CACHE_L1_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
+/** CACHE_BYPASS_L1_ICACHE0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
+#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
+#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
+/** CACHE_BYPASS_L1_ICACHE1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
+#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
+#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
+/** CACHE_BYPASS_L1_ICACHE2_EN : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
+#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
+#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
+/** CACHE_BYPASS_L1_ICACHE3_EN : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
+#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
+#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
+/** CACHE_BYPASS_L1_DCACHE_EN : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
+#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
+#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_DCACHE_EN_S  4
+
+/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
+ *  L1 Cache atomic feature configure register
+ */
+#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
+/** CACHE_L1_DCACHE_ATOMIC_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable atomic feature on L1-DCache when multiple cores access
+ *  L1-DCache.  1: disable, 1: enable.
+ */
+#define CACHE_L1_DCACHE_ATOMIC_EN    (BIT(0))
+#define CACHE_L1_DCACHE_ATOMIC_EN_M  (CACHE_L1_DCACHE_ATOMIC_EN_V << CACHE_L1_DCACHE_ATOMIC_EN_S)
+#define CACHE_L1_DCACHE_ATOMIC_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_ATOMIC_EN_S  0
+
+/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
+/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_ICACHE_CACHESIZE_256_M  (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256_S  0
+/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_ICACHE_CACHESIZE_512_M  (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512_S  1
+/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 1;
+ *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
+/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_DCACHE_CACHESIZE_CONF_REG register
+ *  L1 data Cache CacheSize mode configure register
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
+/** CACHE_L1_DCACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_DCACHE_CACHESIZE_256_M  (CACHE_L1_DCACHE_CACHESIZE_256_V << CACHE_L1_DCACHE_CACHESIZE_256_S)
+#define CACHE_L1_DCACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_256_S  0
+/** CACHE_L1_DCACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_DCACHE_CACHESIZE_512_M  (CACHE_L1_DCACHE_CACHESIZE_512_V << CACHE_L1_DCACHE_CACHESIZE_512_S)
+#define CACHE_L1_DCACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_512_S  1
+/** CACHE_L1_DCACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_DCACHE_CACHESIZE_1K_M  (CACHE_L1_DCACHE_CACHESIZE_1K_V << CACHE_L1_DCACHE_CACHESIZE_1K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_DCACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_DCACHE_CACHESIZE_2K_M  (CACHE_L1_DCACHE_CACHESIZE_2K_V << CACHE_L1_DCACHE_CACHESIZE_2K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_DCACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_DCACHE_CACHESIZE_4K_M  (CACHE_L1_DCACHE_CACHESIZE_4K_V << CACHE_L1_DCACHE_CACHESIZE_4K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_DCACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_DCACHE_CACHESIZE_8K_M  (CACHE_L1_DCACHE_CACHESIZE_8K_V << CACHE_L1_DCACHE_CACHESIZE_8K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_DCACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_DCACHE_CACHESIZE_16K_M  (CACHE_L1_DCACHE_CACHESIZE_16K_V << CACHE_L1_DCACHE_CACHESIZE_16K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_DCACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_DCACHE_CACHESIZE_32K_M  (CACHE_L1_DCACHE_CACHESIZE_32K_V << CACHE_L1_DCACHE_CACHESIZE_32K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_DCACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 1;
+ *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_DCACHE_CACHESIZE_64K_M  (CACHE_L1_DCACHE_CACHESIZE_64K_V << CACHE_L1_DCACHE_CACHESIZE_64K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_DCACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_DCACHE_CACHESIZE_128K_M  (CACHE_L1_DCACHE_CACHESIZE_128K_V << CACHE_L1_DCACHE_CACHESIZE_128K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_DCACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_DCACHE_CACHESIZE_256K_M  (CACHE_L1_DCACHE_CACHESIZE_256K_V << CACHE_L1_DCACHE_CACHESIZE_256K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_DCACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_DCACHE_CACHESIZE_512K_M  (CACHE_L1_DCACHE_CACHESIZE_512K_V << CACHE_L1_DCACHE_CACHESIZE_512K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_DCACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_M  (CACHE_L1_DCACHE_CACHESIZE_1024K_V << CACHE_L1_DCACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG register
+ *  L1 data Cache BlockSize mode configure register
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
+/** CACHE_L1_DCACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_M  (CACHE_L1_DCACHE_BLOCKSIZE_8_V << CACHE_L1_DCACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_DCACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_M  (CACHE_L1_DCACHE_BLOCKSIZE_16_V << CACHE_L1_DCACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_DCACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_M  (CACHE_L1_DCACHE_BLOCKSIZE_32_V << CACHE_L1_DCACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_DCACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_M  (CACHE_L1_DCACHE_BLOCKSIZE_64_V << CACHE_L1_DCACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_DCACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_M  (CACHE_L1_DCACHE_BLOCKSIZE_128_V << CACHE_L1_DCACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_DCACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_M  (CACHE_L1_DCACHE_BLOCKSIZE_256_V << CACHE_L1_DCACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x20)
+/** CACHE_L1_ICACHE0_WRAP : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache0 wrap around mode.
+ */
+#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
+#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
+#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE0_WRAP_S  0
+/** CACHE_L1_ICACHE1_WRAP : R/W; bitpos: [1]; default: 0;
+ *  Set this bit as 1 to enable L1-ICache1 wrap around mode.
+ */
+#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
+#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
+#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE1_WRAP_S  1
+/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
+#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
+#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE2_WRAP_S  2
+/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
+#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
+#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE3_WRAP_S  3
+/** CACHE_L1_DCACHE_WRAP : R/W; bitpos: [4]; default: 0;
+ *  Set this bit as 1 to enable L1-DCache wrap around mode.
+ */
+#define CACHE_L1_DCACHE_WRAP    (BIT(4))
+#define CACHE_L1_DCACHE_WRAP_M  (CACHE_L1_DCACHE_WRAP_V << CACHE_L1_DCACHE_WRAP_S)
+#define CACHE_L1_DCACHE_WRAP_V  0x00000001U
+#define CACHE_L1_DCACHE_WRAP_S  4
+
+/** CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG register
+ *  Cache tag memory power control register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x24)
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache0 tag memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_ON_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PD_S  1
+/** CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU    (BIT(2))
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_FORCE_PU_S  2
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache1 tag memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_ON_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PD_S  5
+/** CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1;
+ *  The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU    (BIT(6))
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_FORCE_PU_S  6
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_ON_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PD_S  9
+/** CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU    (BIT(10))
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_FORCE_PU_S  10
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_ON_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PD_S  13
+/** CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU    (BIT(14))
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_FORCE_PU_S  14
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to close clock gating of  L1-DCache tag memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_ON_S  16
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to power L1-DCache tag memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PD_S  17
+/** CACHE_L1_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to power L1-DCache tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_M  (CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_V << CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_S)
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_FORCE_PU_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG register
+ *  Cache data memory power control register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache0 data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_ON_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PD_S  1
+/** CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU    (BIT(2))
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_FORCE_PU_S  2
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to close clock gating of  L1-ICache1 data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_ON_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PD_S  5
+/** CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU : R/W; bitpos: [6]; default: 1;
+ *  The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU    (BIT(6))
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_FORCE_PU_S  6
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_ON_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PD_S  9
+/** CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU : HRO; bitpos: [10]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU    (BIT(10))
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_FORCE_PU_S  10
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_ON_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PD_S  13
+/** CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU : HRO; bitpos: [14]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU    (BIT(14))
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_M  (CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V << CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_FORCE_PU_S  14
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to close clock gating of  L1-DCache data memory. 1: close gating,
+ *  0: open clock gating.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON    (BIT(16))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_ON_S  16
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to power L1-DCache data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD    (BIT(17))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PD_S  17
+/** CACHE_L1_DCACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to power L1-DCache data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU    (BIT(18))
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_M  (CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_V << CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_S)
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_FORCE_PU_S  18
+
+/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x2c)
+/** CACHE_L1_ICACHE0_FREEZE_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache0. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
+#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
+/** CACHE_L1_ICACHE0_FREEZE_MODE : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
+#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
+/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
+#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
+/** CACHE_L1_ICACHE1_FREEZE_EN : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable freeze operation on L1-ICache1. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
+#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
+/** CACHE_L1_ICACHE1_FREEZE_MODE : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
+#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
+/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
+#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
+/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
+#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
+/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
+#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
+/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
+#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
+/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
+#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
+/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
+#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
+/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
+#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
+/** CACHE_L1_DCACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
+ *  The bit is used to enable freeze operation on L1-DCache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L1_DCACHE_FREEZE_EN    (BIT(16))
+#define CACHE_L1_DCACHE_FREEZE_EN_M  (CACHE_L1_DCACHE_FREEZE_EN_V << CACHE_L1_DCACHE_FREEZE_EN_S)
+#define CACHE_L1_DCACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_EN_S  16
+/** CACHE_L1_DCACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
+ *  The bit is used to configure mode of freeze operation L1-DCache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L1_DCACHE_FREEZE_MODE    (BIT(17))
+#define CACHE_L1_DCACHE_FREEZE_MODE_M  (CACHE_L1_DCACHE_FREEZE_MODE_V << CACHE_L1_DCACHE_FREEZE_MODE_S)
+#define CACHE_L1_DCACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_MODE_S  17
+/** CACHE_L1_DCACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L1-DCache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_FREEZE_DONE    (BIT(18))
+#define CACHE_L1_DCACHE_FREEZE_DONE_M  (CACHE_L1_DCACHE_FREEZE_DONE_V << CACHE_L1_DCACHE_FREEZE_DONE_S)
+#define CACHE_L1_DCACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_DONE_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x30)
+/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : R/W; bitpos: [1]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : R/W; bitpos: [5]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable,
+ *  1: enable.
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
+/** CACHE_L1_DCACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to enable config-bus read L1-DCache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_M  (CACHE_L1_DCACHE_DATA_MEM_RD_EN_V << CACHE_L1_DCACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_S  16
+/** CACHE_L1_DCACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
+ *  The bit is used to enable config-bus write L1-DCache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_M  (CACHE_L1_DCACHE_DATA_MEM_WR_EN_V << CACHE_L1_DCACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_S  17
+
+/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34)
+/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : R/W; bitpos: [1]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : R/W; bitpos: [5]; default: 1;
+ *  The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : HRO; bitpos: [8]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : HRO; bitpos: [9]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : HRO; bitpos: [12]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : HRO; bitpos: [13]; default: 1;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
+/** CACHE_L1_DCACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 1;
+ *  The bit is used to enable config-bus read L1-DCache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_M  (CACHE_L1_DCACHE_TAG_MEM_RD_EN_V << CACHE_L1_DCACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_S  16
+/** CACHE_L1_DCACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 1;
+ *  The bit is used to enable config-bus write L1-DCache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_M  (CACHE_L1_DCACHE_TAG_MEM_WR_EN_V << CACHE_L1_DCACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_S  17
+
+/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x38)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE0_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 prelock.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x3c)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache0, which should be used together with
+ *  L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x40)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache0, which should be used together with
+ *  L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x44)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x48)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE1_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 prelock.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x4c)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache1, which should be used together with
+ *  L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x50)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache1, which should be used together with
+ *  L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x54)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x58)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 prelock.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x5c)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache2, which should be used together with
+ *  L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x60)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache2, which should be used together with
+ *  L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x64)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x68)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 prelock.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x6c)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-ICache3, which should be used together with
+ *  L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x70)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-ICache3, which should be used together with
+ *  L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x74)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_DCACHE_PRELOCK_CONF_REG register
+ *  L1 data Cache prelock configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x78)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_DCACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache prelock.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_PRELOCK_RGID_M  (CACHE_L1_DCACHE_PRELOCK_RGID_V << CACHE_L1_DCACHE_PRELOCK_RGID_S)
+#define CACHE_L1_DCACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L1 data Cache prelock section0 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x7c)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L1-DCache, which should be used together with
+ *  L1_DCACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L1 data Cache prelock section1 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x80)
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L1-DCache, which should be used together with
+ *  L1_DCACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
+ *  L1 data Cache prelock section size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x84)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_LOCK_CTRL_REG register
+ *  Lock-class (manual lock) operation control register
+ */
+#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x88)
+/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable lock operation. It will be cleared by hardware after lock
+ *  operation done. Note that (1) this bit and unlock_ena bit are mutually exclusive,
+ *  that is, those bits can not be set to 1 at the same time. (2) lock operation can be
+ *  applied on LL1-ICache, L1-DCache and L2-Cache.
+ */
+#define CACHE_LOCK_ENA    (BIT(0))
+#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
+#define CACHE_LOCK_ENA_V  0x00000001U
+#define CACHE_LOCK_ENA_S  0
+/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable unlock operation. It will be cleared by hardware after
+ *  unlock operation done. Note that (1) this bit and lock_ena bit are mutually
+ *  exclusive, that is, those bits can not be set to 1 at the same time. (2) unlock
+ *  operation can be applied on L1-ICache, L1-DCache and L2-Cache.
+ */
+#define CACHE_UNLOCK_ENA    (BIT(1))
+#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
+#define CACHE_UNLOCK_ENA_V  0x00000001U
+#define CACHE_UNLOCK_ENA_S  1
+/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
+ *  The bit is used to indicate whether unlock/lock operation is finished or not. 0:
+ *  not finished. 1: finished.
+ */
+#define CACHE_LOCK_DONE    (BIT(2))
+#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
+#define CACHE_LOCK_DONE_V  0x00000001U
+#define CACHE_LOCK_DONE_S  2
+/** CACHE_LOCK_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of cache lock/unlock.
+ */
+#define CACHE_LOCK_RGID    0x0000000FU
+#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
+#define CACHE_LOCK_RGID_V  0x0000000FU
+#define CACHE_LOCK_RGID_S  3
+
+/** CACHE_LOCK_MAP_REG register
+ *  Lock (manual lock) map configure register
+ */
+#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x8c)
+/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply this lock/unlock operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]:
+ *  L1-ICache2, [3]: L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+ */
+#define CACHE_LOCK_MAP    0x0000003FU
+#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
+#define CACHE_LOCK_MAP_V  0x0000003FU
+#define CACHE_LOCK_MAP_S  0
+
+/** CACHE_LOCK_ADDR_REG register
+ *  Lock (manual lock) address configure register
+ */
+#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x90)
+/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the lock/unlock
+ *  operation, which should be used together with CACHE_LOCK_SIZE_REG
+ */
+#define CACHE_LOCK_ADDR    0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
+#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_S  0
+
+/** CACHE_LOCK_SIZE_REG register
+ *  Lock (manual lock) size configure register
+ */
+#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x94)
+/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the lock/unlock operation, which
+ *  should be used together with CACHE_LOCK_ADDR_REG
+ */
+#define CACHE_LOCK_SIZE    0x0000FFFFU
+#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
+#define CACHE_LOCK_SIZE_V  0x0000FFFFU
+#define CACHE_LOCK_SIZE_S  0
+
+/** CACHE_SYNC_CTRL_REG register
+ *  Sync-class operation control register
+ */
+#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x98)
+/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
+ *  The bit is used to enable invalidate operation. It will be cleared by hardware
+ *  after invalidate operation done. Note that this bit and the other sync-bits
+ *  (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_INVALIDATE_ENA    (BIT(0))
+#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
+#define CACHE_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_INVALIDATE_ENA_S  0
+/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  The bit is used to enable clean operation. It will be cleared by hardware after
+ *  clean operation done. Note that this bit and the other sync-bits (invalidate_ena,
+ *  writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those
+ *  bits can not be set to 1 at the same time.
+ */
+#define CACHE_CLEAN_ENA    (BIT(1))
+#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
+#define CACHE_CLEAN_ENA_V  0x00000001U
+#define CACHE_CLEAN_ENA_S  1
+/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
+ *  The bit is used to enable writeback operation. It will be cleared by hardware after
+ *  writeback operation done. Note that this bit and the other sync-bits
+ *  (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that
+ *  is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_ENA    (BIT(2))
+#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
+#define CACHE_WRITEBACK_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_ENA_S  2
+/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
+ *  The bit is used to enable writeback-invalidate operation. It will be cleared by
+ *  hardware after writeback-invalidate operation done. Note that this bit and the
+ *  other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive,
+ *  that is, those bits can not be set to 1 at the same time.
+ */
+#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
+#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
+ *  The bit is used to indicate whether sync operation (invalidate, clean, writeback,
+ *  writeback_invalidate) is finished or not. 0: not finished. 1: finished.
+ */
+#define CACHE_SYNC_DONE    (BIT(4))
+#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
+#define CACHE_SYNC_DONE_V  0x00000001U
+#define CACHE_SYNC_DONE_S  4
+/** CACHE_SYNC_RGID : R/W; bitpos: [8:5]; default: 0;
+ *  The bit is used to set  the gid of cache sync operation (invalidate, clean,
+ *  writeback, writeback_invalidate)
+ */
+#define CACHE_SYNC_RGID    0x0000000FU
+#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
+#define CACHE_SYNC_RGID_V  0x0000000FU
+#define CACHE_SYNC_RGID_S  5
+
+/** CACHE_SYNC_MAP_REG register
+ *  Sync map configure register
+ */
+#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0x9c)
+/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 31;
+ *  Those bits are used to indicate which caches in the two-level cache structure will
+ *  apply the sync operation. [0]: L1-ICache0, [1]: L1-ICache1, [2]: L1-ICache2, [3]:
+ *  L1-ICache3, [4]: L1-DCache, [5]: L2-Cache.
+ */
+#define CACHE_SYNC_MAP    0x0000003FU
+#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
+#define CACHE_SYNC_MAP_V  0x0000003FU
+#define CACHE_SYNC_MAP_S  0
+
+/** CACHE_SYNC_ADDR_REG register
+ *  Sync address configure register
+ */
+#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa0)
+/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the sync operation,
+ *  which should be used together with CACHE_SYNC_SIZE_REG
+ */
+#define CACHE_SYNC_ADDR    0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
+#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_S  0
+
+/** CACHE_SYNC_SIZE_REG register
+ *  Sync size configure register
+ */
+#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa4)
+/** CACHE_SYNC_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the sync operation, which should be
+ *  used together with CACHE_SYNC_ADDR_REG
+ */
+#define CACHE_SYNC_SIZE    0x0FFFFFFFU
+#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
+#define CACHE_SYNC_SIZE_V  0x0FFFFFFFU
+#define CACHE_SYNC_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xa8)
+/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache0. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 preload.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 0 preload address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xac)
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb0)
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb4)
+/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache1. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 preload.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 1 preload address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb8)
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xbc)
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc0)
+/** CACHE_L1_ICACHE2_PRELOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache2. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 preload.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc4)
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc8)
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xcc)
+/** CACHE_L1_ICACHE3_PRELOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-ICache3. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 preload.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
+
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd0)
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd4)
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_CTRL_REG register
+ *  L1 data Cache  preload-operation control register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd8)
+/** CACHE_L1_DCACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L1-DCache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_DCACHE_PRELOAD_ENA_M  (CACHE_L1_DCACHE_PRELOAD_ENA_V << CACHE_L1_DCACHE_PRELOAD_ENA_S)
+#define CACHE_L1_DCACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_ENA_S  0
+/** CACHE_L1_DCACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_DCACHE_PRELOAD_DONE_M  (CACHE_L1_DCACHE_PRELOAD_DONE_V << CACHE_L1_DCACHE_PRELOAD_DONE_S)
+#define CACHE_L1_DCACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_DONE_S  1
+/** CACHE_L1_DCACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_M  (CACHE_L1_DCACHE_PRELOAD_ORDER_V << CACHE_L1_DCACHE_PRELOAD_ORDER_S)
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_S  2
+/** CACHE_L1_DCACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache preload.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_PRELOAD_RGID_M  (CACHE_L1_DCACHE_PRELOAD_RGID_V << CACHE_L1_DCACHE_PRELOAD_RGID_S)
+#define CACHE_L1_DCACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_PRELOAD_RGID_S  3
+
+/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
+ *  L1 data Cache  preload address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xdc)
+/** CACHE_L1_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on L1-DCache,
+ *  which should be used together with L1_DCACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_M  (CACHE_L1_DCACHE_PRELOAD_ADDR_V << CACHE_L1_DCACHE_PRELOAD_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
+ *  L1 data Cache  preload size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe0)
+/** CACHE_L1_DCACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L1-DCache, which should be used together with L1_DCACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_M  (CACHE_L1_DCACHE_PRELOAD_SIZE_V << CACHE_L1_DCACHE_PRELOAD_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache0.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache0 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache0. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache0.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache0 autoload.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xe8)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xec)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xf0)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache0. Note that it should be used together with
+ *  L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xf8)
+/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache1.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache1 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache1. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache1.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache1 autoload.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xfc)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x100)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x104)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x108)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache1. Note that it should be used together with
+ *  L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x10c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache2.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache2. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache2 autoload.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x110)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x114)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x118)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x11c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-ICache2. Note that it should be used together with
+ *  L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x120)
+/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-ICache3.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-ICache3. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  The bit is used to set  the gid of l1 icache3 autoload.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x124)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x128)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x12c)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-ICache3. Note that it should be used together with
+ *  L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x130)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG register
+ *  L1 data Cache autoload-operation control register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x134)
+/** CACHE_L1_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L1-DCache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L1_DCACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-DCache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_M  (CACHE_L1_DCACHE_AUTOLOAD_DONE_V << CACHE_L1_DCACHE_AUTOLOAD_DONE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L1_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L1-DCache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_M  (CACHE_L1_DCACHE_AUTOLOAD_ORDER_V << CACHE_L1_DCACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-DCache.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L1-DCache.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L1_DCACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l1 dcache autoload.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_M  (CACHE_L1_DCACHE_AUTOLOAD_RGID_V << CACHE_L1_DCACHE_AUTOLOAD_RGID_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 data Cache autoload section 0 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x138)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT0_SIZE and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 data Cache autoload section 0 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x13c)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT0_ADDR and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x140)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT1_SIZE and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x144)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT1_ADDR and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L1 data Cache autoload section 2 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x148)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the third section for
+ *  autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT2_SIZE and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L1 data Cache autoload section 2 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x14c)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT2_ADDR and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x150)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the fourth section
+ *  for autoload operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT3_SIZE and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x154)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L1-DCache. Note that it should be used together with
+ *  L1_DCACHE_AUTOLOAD_SCT3_ADDR and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x158)
+/** CACHE_L1_IBUS0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
+/** CACHE_L1_DBUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_ENA    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_ENA_M  (CACHE_L1_DBUS0_OVF_INT_ENA_V << CACHE_L1_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_ENA_S  4
+/** CACHE_L1_DBUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_ENA    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_ENA_M  (CACHE_L1_DBUS1_OVF_INT_ENA_V << CACHE_L1_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_ENA_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x15c)
+/** CACHE_L1_IBUS0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+ *  to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
+/** CACHE_L1_IBUS1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+ *  to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
+/** CACHE_L1_IBUS2_OVF_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
+/** CACHE_L1_IBUS3_OVF_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
+/** CACHE_L1_DBUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_CLR    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_CLR_M  (CACHE_L1_DBUS0_OVF_INT_CLR_V << CACHE_L1_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_CLR_S  4
+/** CACHE_L1_DBUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_CLR    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_CLR_M  (CACHE_L1_DBUS1_OVF_INT_CLR_V << CACHE_L1_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_CLR_S  5
+/** CACHE_L1_DBUS2_OVF_INT_CLR : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
+/** CACHE_L1_DBUS3_OVF_INT_CLR : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x160)
+/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+ *  due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
+/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+ *  due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
+/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+ *  due to bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
+/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+ *  due to bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
+/** CACHE_L1_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_RAW    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_RAW_M  (CACHE_L1_DBUS0_OVF_INT_RAW_V << CACHE_L1_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_RAW_S  4
+/** CACHE_L1_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_RAW    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_RAW_M  (CACHE_L1_DBUS1_OVF_INT_RAW_V << CACHE_L1_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_RAW_S  5
+/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
+/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x164)
+/** CACHE_L1_IBUS0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
+#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
+#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
+#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
+#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
+/** CACHE_L1_DBUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_ST    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_ST_M  (CACHE_L1_DBUS0_OVF_INT_ST_V << CACHE_L1_DBUS0_OVF_INT_ST_S)
+#define CACHE_L1_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_ST_S  4
+/** CACHE_L1_DBUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_ST    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_ST_M  (CACHE_L1_DBUS1_OVF_INT_ST_V << CACHE_L1_DBUS1_OVF_INT_ST_S)
+#define CACHE_L1_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_ST_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ST : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
+#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ST : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
+#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
+
+/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x168)
+/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to configure l1 icache0 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S  0
+/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to configure l1 icache1 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE    (BIT(1))
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S  1
+/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure l1 icache2 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE    (BIT(2))
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S  2
+/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : R/W; bitpos: [3]; default: 0;
+ *  The bit is used to configure l1 icache3 access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE    (BIT(3))
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S  3
+/** CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to configure l1 dcache access fail check mode. 0: the access fail
+ *  is not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE    (BIT(4))
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x16c)
+/** CACHE_L1_ICACHE0_FAIL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_ENA    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_M  (CACHE_L1_DCACHE_FAIL_INT_ENA_V << CACHE_L1_DCACHE_FAIL_INT_ENA_S)
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x170)
+/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_M  (CACHE_L1_DCACHE_FAIL_INT_CLR_V << CACHE_L1_DCACHE_FAIL_INT_CLR_S)
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x174)
+/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_RAW    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_M  (CACHE_L1_DCACHE_FAIL_INT_RAW_V << CACHE_L1_DCACHE_FAIL_INT_RAW_S)
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x178)
+/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+ *  to cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_ST    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_ST_M  (CACHE_L1_DCACHE_FAIL_INT_ST_V << CACHE_L1_DCACHE_FAIL_INT_ST_S)
+#define CACHE_L1_DCACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_ST_S  4
+
+/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x17c)
+/** CACHE_L1_IBUS0_CNT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
+#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_ENA_S  0
+/** CACHE_L1_IBUS1_CNT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
+#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_ENA_S  1
+/** CACHE_L1_IBUS2_CNT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
+#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_ENA_S  2
+/** CACHE_L1_IBUS3_CNT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
+#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_ENA_S  3
+/** CACHE_L1_DBUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CNT_ENA    (BIT(4))
+#define CACHE_L1_DBUS0_CNT_ENA_M  (CACHE_L1_DBUS0_CNT_ENA_V << CACHE_L1_DBUS0_CNT_ENA_S)
+#define CACHE_L1_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS0_CNT_ENA_S  4
+/** CACHE_L1_DBUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CNT_ENA    (BIT(5))
+#define CACHE_L1_DBUS1_CNT_ENA_M  (CACHE_L1_DBUS1_CNT_ENA_V << CACHE_L1_DBUS1_CNT_ENA_S)
+#define CACHE_L1_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS1_CNT_ENA_S  5
+/** CACHE_L1_DBUS2_CNT_ENA : HRO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
+#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_ENA_S  6
+/** CACHE_L1_DBUS3_CNT_ENA : HRO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
+#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_ENA_S  7
+/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0;
+ *  The bit is used to clear ibus0 counter in L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
+#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
+#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_CLR_S  16
+/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0;
+ *  The bit is used to clear ibus1 counter in L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
+#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
+#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_CLR_S  17
+/** CACHE_L1_IBUS2_CNT_CLR : HRO; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
+#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
+#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_CLR_S  18
+/** CACHE_L1_IBUS3_CNT_CLR : HRO; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
+#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
+#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_CLR_S  19
+/** CACHE_L1_DBUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
+ *  The bit is used to clear dbus0 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CNT_CLR    (BIT(20))
+#define CACHE_L1_DBUS0_CNT_CLR_M  (CACHE_L1_DBUS0_CNT_CLR_V << CACHE_L1_DBUS0_CNT_CLR_S)
+#define CACHE_L1_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS0_CNT_CLR_S  20
+/** CACHE_L1_DBUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
+ *  The bit is used to clear dbus1 counter in L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CNT_CLR    (BIT(21))
+#define CACHE_L1_DBUS1_CNT_CLR_M  (CACHE_L1_DBUS1_CNT_CLR_V << CACHE_L1_DBUS1_CNT_CLR_S)
+#define CACHE_L1_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS1_CNT_CLR_S  21
+/** CACHE_L1_DBUS2_CNT_CLR : HRO; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
+#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
+#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_CLR_S  22
+/** CACHE_L1_DBUS3_CNT_CLR : HRO; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
+#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
+#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_CLR_S  23
+
+/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x180)
+/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
+#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x184)
+/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
+#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x188)
+/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
+/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x190)
+/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
+#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x194)
+/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
+#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x198)
+/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
+/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
+/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
+#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
+/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
+#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
+/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
+/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
+/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
+#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
+/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
+#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
+/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
+/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_HIT_CNT_REG register
+ *  L1-DCache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
+/** CACHE_L1_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_HIT_CNT_M  (CACHE_L1_DBUS0_HIT_CNT_V << CACHE_L1_DBUS0_HIT_CNT_S)
+#define CACHE_L1_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_MISS_CNT_REG register
+ *  L1-DCache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
+/** CACHE_L1_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_MISS_CNT_M  (CACHE_L1_DBUS0_MISS_CNT_V << CACHE_L1_DBUS0_MISS_CNT_S)
+#define CACHE_L1_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
+/** CACHE_L1_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_CONFLICT_CNT_M  (CACHE_L1_DBUS0_CONFLICT_CNT_V << CACHE_L1_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
+/** CACHE_L1_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS0_NXTLVL_RD_CNT_V << CACHE_L1_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
+/** CACHE_L1_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS0_NXTLVL_WR_CNT_V << CACHE_L1_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_HIT_CNT_REG register
+ *  L1-DCache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
+/** CACHE_L1_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_HIT_CNT_M  (CACHE_L1_DBUS1_HIT_CNT_V << CACHE_L1_DBUS1_HIT_CNT_S)
+#define CACHE_L1_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_MISS_CNT_REG register
+ *  L1-DCache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
+/** CACHE_L1_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_MISS_CNT_M  (CACHE_L1_DBUS1_MISS_CNT_V << CACHE_L1_DBUS1_MISS_CNT_S)
+#define CACHE_L1_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
+/** CACHE_L1_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_CONFLICT_CNT_M  (CACHE_L1_DBUS1_CONFLICT_CNT_V << CACHE_L1_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
+/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
+/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
+/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
+#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
+/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
+#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
+/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
+/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
+/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1fc)
+/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
+#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x200)
+/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
+#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x204)
+/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x208)
+/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x20c)
+/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x210)
+/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
+#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_S  0
+/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x214)
+/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x218)
+/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
+#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_S  0
+/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x21c)
+/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x220)
+/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
+#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_S  0
+/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x224)
+/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x228)
+/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
+#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_S  0
+/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x22c)
+/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L1-DCache Access Fail ID/attribution information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x230)
+/** CACHE_L1_DCACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ID_M  (CACHE_L1_DCACHE_FAIL_ID_V << CACHE_L1_DCACHE_FAIL_ID_S)
+#define CACHE_L1_DCACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ID_S  0
+/** CACHE_L1_DCACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ATTR_M  (CACHE_L1_DCACHE_FAIL_ATTR_V << CACHE_L1_DCACHE_FAIL_ATTR_S)
+#define CACHE_L1_DCACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ATTR_S  16
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
+ *  L1-DCache Access Fail Address information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x234)
+/** CACHE_L1_DCACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_FAIL_ADDR_M  (CACHE_L1_DCACHE_FAIL_ADDR_V << CACHE_L1_DCACHE_FAIL_ADDR_S)
+#define CACHE_L1_DCACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_FAIL_ADDR_S  0
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x238)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to enable interrupt of L1-DCache preload-operation. If preload
+ *  operation is done, interrupt occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V << CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S  4
+/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation done.
+ */
+#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
+#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ENA_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V << CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S  11
+/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
+#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ENA_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x23c)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-DCache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V << CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S  4
+/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ *  done.
+ */
+#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
+#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_CLR_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The bit is used to clear interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V << CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S  11
+/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
+#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_CLR_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x240)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation is
+ *  done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V << CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S  4
+/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
+#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_RAW_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V << CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S  11
+/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+ *  occurs.
+ */
+#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
+#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_RAW_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x244)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-DCache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ST_V << CACHE_L1_DCACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_S  4
+/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when Cache
+ *  sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
+#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ST_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ST_V << CACHE_L1_DCACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_S  11
+/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the status of the interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
+#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ST_S  13
+
+/** CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_SYNC_L1_CACHE_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x248)
+/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
+/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
+/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
+/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
+/** CACHE_L1_DCACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_M  (CACHE_L1_DCACHE_PLD_ERR_CODE_V << CACHE_L1_DCACHE_PLD_ERR_CODE_S)
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_S  8
+/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
+ *  The values 0-2 are available which means sync map, command conflict and size are
+ *  error in Cache System.
+ */
+#define CACHE_SYNC_ERR_CODE    0x00000003U
+#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
+#define CACHE_SYNC_ERR_CODE_V  0x00000003U
+#define CACHE_SYNC_ERR_CODE_S  12
+
+/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x24c)
+/** CACHE_L1_ICACHE0_SYNC_RST : R/W; bitpos: [0]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
+#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_SYNC_RST_S  0
+/** CACHE_L1_ICACHE1_SYNC_RST : R/W; bitpos: [1]; default: 0;
+ *  set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
+#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_SYNC_RST_S  1
+/** CACHE_L1_ICACHE2_SYNC_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
+#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_SYNC_RST_S  2
+/** CACHE_L1_ICACHE3_SYNC_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
+#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_SYNC_RST_S  3
+/** CACHE_L1_DCACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset sync-logic inside L1-DCache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_DCACHE_SYNC_RST    (BIT(4))
+#define CACHE_L1_DCACHE_SYNC_RST_M  (CACHE_L1_DCACHE_SYNC_RST_V << CACHE_L1_DCACHE_SYNC_RST_S)
+#define CACHE_L1_DCACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L1_DCACHE_SYNC_RST_S  4
+
+/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x250)
+/** CACHE_L1_ICACHE0_PLD_RST : R/W; bitpos: [0]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache0. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
+#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_RST_S  0
+/** CACHE_L1_ICACHE1_PLD_RST : R/W; bitpos: [1]; default: 0;
+ *  set this bit to reset preload-logic inside L1-ICache1. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
+#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_RST_S  1
+/** CACHE_L1_ICACHE2_PLD_RST : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
+#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_RST_S  2
+/** CACHE_L1_ICACHE3_PLD_RST : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
+#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_RST_S  3
+/** CACHE_L1_DCACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
+ *  set this bit to reset preload-logic inside L1-DCache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_RST    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_RST_M  (CACHE_L1_DCACHE_PLD_RST_V << CACHE_L1_DCACHE_PLD_RST_S)
+#define CACHE_L1_DCACHE_PLD_RST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_RST_S  4
+
+/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x254)
+/** CACHE_L1_ICACHE0_ALD_BUF_CLR : R/W; bitpos: [0]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active,
+ *  autoload will not work in L1-ICache0. This bit should not be active when autoload
+ *  works in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
+/** CACHE_L1_ICACHE1_ALD_BUF_CLR : R/W; bitpos: [1]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active,
+ *  autoload will not work in L1-ICache1. This bit should not be active when autoload
+ *  works in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
+/** CACHE_L1_ICACHE2_ALD_BUF_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
+/** CACHE_L1_ICACHE3_ALD_BUF_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
+/** CACHE_L1_DCACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
+ *  set this bit to clear autoload-buffer inside L1-DCache. If this bit is active,
+ *  autoload will not work in L1-DCache. This bit should not be active when autoload
+ *  works in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_ALD_BUF_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_M  (CACHE_L1_DCACHE_ALD_BUF_CLR_V << CACHE_L1_DCACHE_ALD_BUF_CLR_S)
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_S  4
+
+/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x258)
+/** CACHE_L1_ICACHE0_UNALLOC_CLR : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
+/** CACHE_L1_ICACHE1_UNALLOC_CLR : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
+/** CACHE_L1_ICACHE2_UNALLOC_CLR : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
+/** CACHE_L1_ICACHE3_UNALLOC_CLR : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
+/** CACHE_L1_DCACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 dcache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_DCACHE_UNALLOC_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_UNALLOC_CLR_M  (CACHE_L1_DCACHE_UNALLOC_CLR_V << CACHE_L1_DCACHE_UNALLOC_CLR_S)
+#define CACHE_L1_DCACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_UNALLOC_CLR_S  4
+
+/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x25c)
+/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
+/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
+#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
+/** CACHE_L1_ICACHE2_TAG_OBJECT : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
+#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
+/** CACHE_L1_ICACHE3_TAG_OBJECT : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
+#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
+/** CACHE_L1_DCACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to set L1-DCache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_DCACHE_TAG_OBJECT    (BIT(4))
+#define CACHE_L1_DCACHE_TAG_OBJECT_M  (CACHE_L1_DCACHE_TAG_OBJECT_V << CACHE_L1_DCACHE_TAG_OBJECT_S)
+#define CACHE_L1_DCACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_OBJECT_S  4
+/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to set L1-ICache0 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
+#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
+/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to set L1-ICache1 data memory as object. This bit should be onehot
+ *  with the others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
+#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
+/** CACHE_L1_ICACHE2_MEM_OBJECT : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
+#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
+/** CACHE_L1_ICACHE3_MEM_OBJECT : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
+#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
+/** CACHE_L1_DCACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to set L1-DCache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L1_DCACHE_MEM_OBJECT    (BIT(10))
+#define CACHE_L1_DCACHE_MEM_OBJECT_M  (CACHE_L1_DCACHE_MEM_OBJECT_V << CACHE_L1_DCACHE_MEM_OBJECT_S)
+#define CACHE_L1_DCACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_DCACHE_MEM_OBJECT_S  10
+
+/** CACHE_L1_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x260)
+/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
+#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L1_CACHE_VADDR_REG register
+ *  Cache Vaddr register
+ */
+#define CACHE_L1_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x264)
+/** CACHE_L1_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the virtual address which will decide where inside the specified
+ *  tag memory object will be accessed.
+ */
+#define CACHE_L1_CACHE_VADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_VADDR_M  (CACHE_L1_CACHE_VADDR_V << CACHE_L1_CACHE_VADDR_S)
+#define CACHE_L1_CACHE_VADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_VADDR_S  0
+
+/** CACHE_L1_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x268)
+/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 616;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
+#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_L2_CACHE_CTRL_REG register
+ *  L2 Cache(L2-Cache) control register
+ */
+#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x270)
+/** CACHE_L2_CACHE_SHUT_DMA : R/W; bitpos: [4]; default: 1;
+ *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+ */
+#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
+#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L2_CACHE_SHUT_DMA_S  4
+
+/** CACHE_L2_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x274)
+/** CACHE_BYPASS_L2_CACHE_EN : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass.
+ */
+#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
+#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
+#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L2_CACHE_EN_S  5
+
+/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
+ *  L2 Cache CacheSize mode configure register
+ */
+#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x278)
+/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L2_CACHE_CACHESIZE_256_M  (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S)
+#define CACHE_L2_CACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256_S  0
+/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L2_CACHE_CACHESIZE_512_M  (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S)
+#define CACHE_L2_CACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512_S  1
+/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1K_S  2
+/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
+#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_2K_S  3
+/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
+#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_4K_S  4
+/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
+#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_8K_S  5
+/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
+#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_16K_S  6
+/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
+#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_32K_S  7
+/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
+#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_64K_S  8
+/** CACHE_L2_CACHE_CACHESIZE_128K : R/W; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
+#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_128K_S  9
+/** CACHE_L2_CACHE_CACHESIZE_256K : R/W; bitpos: [10]; default: 1;
+ *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
+#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256K_S  10
+/** CACHE_L2_CACHE_CACHESIZE_512K : R/W; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
+#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512K_S  11
+/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
+ *  L2 Cache BlockSize mode configure register
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x27c)
+/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
+/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
+/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
+/** CACHE_L2_CACHE_BLOCKSIZE_64 : R/W; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+ *  other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
+/** CACHE_L2_CACHE_BLOCKSIZE_128 : R/W; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
+/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x280)
+/** CACHE_L2_CACHE_WRAP : R/W; bitpos: [5]; default: 0;
+ *  Set this bit as 1 to enable L2-Cache wrap around mode.
+ */
+#define CACHE_L2_CACHE_WRAP    (BIT(5))
+#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
+#define CACHE_L2_CACHE_WRAP_V  0x00000001U
+#define CACHE_L2_CACHE_WRAP_S  5
+
+/** CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG register
+ *  Cache tag memory power control register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x284)
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to close clock gating of  L2-Cache tag memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V << CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_ON_S  20
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PD_S  21
+/** CACHE_L2_CACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [22]; default: 1;
+ *  The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU    (BIT(22))
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_M  (CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V << CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S)
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_FORCE_PU_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG register
+ *  Cache data memory power control register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_POWER_CTRL_REG (DR_REG_CACHE_BASE + 0x288)
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_ON : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to close clock gating of  L2-Cache data memory. 1: close gating, 0:
+ *  open clock gating.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V << CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_ON_S  20
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_PD : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power
+ *  down
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PD_S  21
+/** CACHE_L2_CACHE_DATA_MEM_FORCE_PU : R/W; bitpos: [22]; default: 1;
+ *  The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up
+ */
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU    (BIT(22))
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_M  (CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V << CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S)
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_FORCE_PU_S  22
+
+/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28c)
+/** CACHE_L2_CACHE_FREEZE_EN : R/W; bitpos: [20]; default: 0;
+ *  The bit is used to enable freeze operation on L2-Cache. It can be cleared by
+ *  software.
+ */
+#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
+#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
+#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_EN_S  20
+/** CACHE_L2_CACHE_FREEZE_MODE : R/W; bitpos: [21]; default: 0;
+ *  The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access
+ *  will not stuck. 1: a miss-access will stuck.
+ */
+#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
+#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
+#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_MODE_S  21
+/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
+#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
+#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_DONE_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x290)
+/** CACHE_L2_CACHE_DATA_MEM_RD_EN : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_DATA_MEM_WR_EN : R/W; bitpos: [21]; default: 1;
+ *  The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x294)
+/** CACHE_L2_CACHE_TAG_MEM_RD_EN : R/W; bitpos: [20]; default: 1;
+ *  The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_TAG_MEM_WR_EN : R/W; bitpos: [21]; default: 1;
+ *  The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1:
+ *  enable.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
+ *  L2 Cache prelock configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x298)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable the first section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to enable the second section of prelock function on L2-Cache.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L2_CACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  The bit is used to set  the gid of l2 cache prelock.
+ */
+#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
+#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L2 Cache prelock section0 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x29c)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section of
+ *  prelock on L2-Cache, which should be used together with
+ *  L2_CACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L2 Cache prelock section1 address configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2a0)
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section of
+ *  prelock on L2-Cache, which should be used together with
+ *  L2_CACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
+ *  L2 Cache prelock section size configure register
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x2a4)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [15:0]; default: 65535;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [31:16]; default: 65535;
+ *  Those bits are used to configure the size of the second section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
+ *  L2 Cache preload-operation control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a8)
+/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  The bit is used to enable preload operation on L2-Cache. It will be cleared by
+ *  hardware automatically after preload operation is done.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
+#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
+/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
+#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
+/** CACHE_L2_CACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of preload operation. 0: ascending, 1:
+ *  descending.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
+#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
+/** CACHE_L2_CACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  The bit is used to set  the gid of l2 cache preload.
+ */
+#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
+#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
+
+/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
+ *  L2 Cache preload address configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2ac)
+/** CACHE_L2_CACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of preload on L2-Cache,
+ *  which should be used together with L2_CACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
+#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
+ *  L2 Cache preload size configure register
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2b0)
+/** CACHE_L2_CACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Those bits are used to configure the size of the first section of prelock on
+ *  L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
+#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
+ *  L2 Cache autoload-operation control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2b4)
+/** CACHE_L2_CACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to enable and disable autoload operation on L2-Cache.  1: enable,
+ *  0: disable.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L2_CACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  The bit is used to configure the direction of autoload operation on L2-Cache. 0:
+ *  ascending. 1: descending.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+ *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable the first section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable the second section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
+ *  The bit is used to enable the third section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
+ *  The bit is used to enable the fourth section for autoload operation on L2-Cache.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L2_CACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
+ *  The bit is used to set  the gid of l2 cache autoload.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L2 Cache autoload section 0 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the first section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L2 Cache autoload section 0 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the first section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L2 Cache autoload section 1 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the second section
+ *  for autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L2 Cache autoload section 1 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the second section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L2 Cache autoload section 2 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the third section for
+ *  autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L2 Cache autoload section 2 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the third section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L2 Cache autoload section 3 address configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2d0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start virtual address of the fourth section
+ *  for autoload operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L2 Cache autoload section 3 size configure register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2d4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Those bits are used to configure the size of the fourth section for autoload
+ *  operation on L2-Cache. Note that it should be used together with
+ *  L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d8)
+/** CACHE_L2_IBUS0_OVF_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable interrupt of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2dc)
+/** CACHE_L2_IBUS0_OVF_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
+/** CACHE_L2_IBUS1_OVF_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
+/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
+/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
+/** CACHE_L2_DBUS0_OVF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
+/** CACHE_L2_DBUS1_OVF_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
+/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
+/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2e0)
+/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-ICache0.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
+/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-ICache1.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
+/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-ICache2.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
+/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-ICache3.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
+/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
+/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
+/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
+/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-DCache.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2e4)
+/** CACHE_L2_IBUS0_OVF_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
+#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
+#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
+#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
+#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
+#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
+#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
+#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
+#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
+
+/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e8)
+/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to configure l2 cache access fail check mode. 0: the access fail is
+ *  not propagated to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2ec)
+/** CACHE_L2_CACHE_FAIL_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of access fail that occurs in L2-Cache due to
+ *  l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
+#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2f0)
+/** CACHE_L2_CACHE_FAIL_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+ *  cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
+#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2f4)
+/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
+#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f8)
+/** CACHE_L2_CACHE_FAIL_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+ *  to l1 cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
+#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
+
+/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2fc)
+/** CACHE_L2_IBUS0_CNT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The bit is used to enable ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
+#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_ENA_S  8
+/** CACHE_L2_IBUS1_CNT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The bit is used to enable ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
+#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_ENA_S  9
+/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
+#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_ENA_S  10
+/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
+#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_ENA_S  11
+/** CACHE_L2_DBUS0_CNT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
+#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_ENA_S  12
+/** CACHE_L2_DBUS1_CNT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The bit is used to enable dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
+#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_ENA_S  13
+/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
+#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_ENA_S  14
+/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
+#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_ENA_S  15
+/** CACHE_L2_IBUS0_CNT_CLR : WT; bitpos: [24]; default: 0;
+ *  The bit is used to clear ibus0 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
+#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
+#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_CLR_S  24
+/** CACHE_L2_IBUS1_CNT_CLR : WT; bitpos: [25]; default: 0;
+ *  The bit is used to clear ibus1 counter in L2-Cache.
+ */
+#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
+#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
+#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_CLR_S  25
+/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
+#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
+#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_CLR_S  26
+/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
+#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
+#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_CLR_S  27
+/** CACHE_L2_DBUS0_CNT_CLR : WT; bitpos: [28]; default: 0;
+ *  The bit is used to clear dbus0 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
+#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
+#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_CLR_S  28
+/** CACHE_L2_DBUS1_CNT_CLR : WT; bitpos: [29]; default: 0;
+ *  The bit is used to clear dbus1 counter in L2-Cache.
+ */
+#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
+#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
+#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_CLR_S  29
+/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
+#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
+#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_CLR_S  30
+/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
+#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
+#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_CLR_S  31
+
+/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
+/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
+#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x304)
+/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
+#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
+/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache0 accesses
+ *  L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
+/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+ */
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
+/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
+#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x314)
+/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
+#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
+/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache1 accesses
+ *  L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
+/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+ */
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
+/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
+#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x324)
+/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
+#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
+/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache2 accesses
+ *  L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
+/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+ */
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
+/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
+#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x334)
+/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
+#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
+/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache3 accesses
+ *  L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
+/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+ */
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
+/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
+#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x344)
+/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
+#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x348)
+/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
+/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus0 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x350)
+/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus0 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x354)
+/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
+#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x358)
+/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
+#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
+/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x360)
+/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus1 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x364)
+/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus1 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x368)
+/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
+#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x36c)
+/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
+#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x370)
+/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x374)
+/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus2 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x378)
+/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus2 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x37c)
+/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
+#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x380)
+/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
+#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x384)
+/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x388)
+/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus3 WB-Access Counter register
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x38c)
+/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus3 accessing L1-DCache.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x390)
+/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
+#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_S  0
+/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+ *  due to cache accessing L1-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
+#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_S  16
+
+/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
+ *  L2-Cache Access Fail Address information register
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x394)
+/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+ */
+#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
+#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_S  0
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x398)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The bit is used to enable interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x39c)
+/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+ *  is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x3a0)
+/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+ *  done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x3a4)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+ *  preload-operation is done.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a8)
+/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L2-Cache.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
+#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
+
+/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac)
+/** CACHE_L2_CACHE_SYNC_RST : R/W; bitpos: [5]; default: 0;
+ *  set this bit to reset sync-logic inside L2-Cache. Recommend that this should only
+ *  be used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
+#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
+#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L2_CACHE_SYNC_RST_S  5
+
+/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3b0)
+/** CACHE_L2_CACHE_PLD_RST : R/W; bitpos: [5]; default: 0;
+ *  set this bit to reset preload-logic inside L2-Cache. Recommend that this should
+ *  only be used to initialize preload-logic when some fatal error of preload-logic
+ *  occurs.
+ */
+#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
+#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_RST_S  5
+
+/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4)
+/** CACHE_L2_CACHE_ALD_BUF_CLR : R/W; bitpos: [5]; default: 0;
+ *  set this bit to clear autoload-buffer inside L2-Cache. If this bit is active,
+ *  autoload will not work in L2-Cache. This bit should not be active when autoload
+ *  works in L2-Cache.
+ */
+#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
+#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
+#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
+
+/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b8)
+/** CACHE_L2_CACHE_UNALLOC_CLR : R/W; bitpos: [5]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l2 icache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
+#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
+#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
+
+/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
+ *  L2 cache access attribute control register
+ */
+#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3bc)
+/** CACHE_L2_CACHE_ACCESS_FORCE_CC : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to force the request to l2 cache with cacheable attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+ *  non-cacheable.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
+/** CACHE_L2_CACHE_ACCESS_FORCE_WB : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-back attribute, otherwise,
+ *  the attribute is propagated from L1 cache or CPU, it could be one of write-back and
+ *  write-through.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
+/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to force the request to l2 cache with write-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  write-miss-allocate and write-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
+/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : R/W; bitpos: [3]; default: 1;
+ *  Set this bit to force the request to l2 cache with read-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  read-miss-allocate and read-miss-no-allocate.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
+
+/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3c0)
+/** CACHE_L2_CACHE_TAG_OBJECT : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to set L2-Cache tag memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
+#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
+#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_OBJECT_S  5
+/** CACHE_L2_CACHE_MEM_OBJECT : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to set L2-Cache data memory as object. This bit should be onehot with
+ *  the others fields inside this register.
+ */
+#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
+#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
+#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_MEM_OBJECT_S  11
+
+/** CACHE_L2_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3c4)
+/** CACHE_L2_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Set this bits to select which way of the tag-object will be accessed. 0: way0, 1:
+ *  way1, 2: way2, 3: way3, ?, 7: way7.
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
+#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L2_CACHE_VADDR_REG register
+ *  Cache Vaddr register
+ */
+#define CACHE_L2_CACHE_VADDR_REG (DR_REG_CACHE_BASE + 0x3c8)
+/** CACHE_L2_CACHE_VADDR : R/W; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the virtual address which will decide where inside the specified
+ *  tag memory object will be accessed.
+ */
+#define CACHE_L2_CACHE_VADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_VADDR_M  (CACHE_L2_CACHE_VADDR_V << CACHE_L2_CACHE_VADDR_S)
+#define CACHE_L2_CACHE_VADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_VADDR_S  0
+
+/** CACHE_L2_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3cc)
+/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 972;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
+#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3d4)
+/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  The bit is used to enable clock gate when access all registers in this module.
+ */
+#define CACHE_CLK_EN    (BIT(0))
+#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
+#define CACHE_CLK_EN_V  0x00000001U
+#define CACHE_CLK_EN_S  0
+
+/** CACHE_DATE_REG register
+ *  Version control register
+ */
+#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
+/** CACHE_DATE : R/W; bitpos: [27:0]; default: 36716848;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define CACHE_DATE    0x0FFFFFFFU
+#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
+#define CACHE_DATE_V  0x0FFFFFFFU
+#define CACHE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/cache_struct.h b/components/soc/esp32p4/register/soc/cache_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/cache_struct.h
rename to components/soc/esp32p4/register/soc/cache_struct.h
diff --git a/components/soc/esp32p4/include/soc/dma2d_reg.h b/components/soc/esp32p4/register/soc/dma2d_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/dma2d_reg.h
rename to components/soc/esp32p4/register/soc/dma2d_reg.h
diff --git a/components/soc/esp32p4/include/soc/dma2d_struct.h b/components/soc/esp32p4/register/soc/dma2d_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/dma2d_struct.h
rename to components/soc/esp32p4/register/soc/dma2d_struct.h
diff --git a/components/soc/esp32p4/include/soc/dma_pms_reg.h b/components/soc/esp32p4/register/soc/dma_pms_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/dma_pms_reg.h
rename to components/soc/esp32p4/register/soc/dma_pms_reg.h
diff --git a/components/soc/esp32p4/include/soc/dma_pms_struct.h b/components/soc/esp32p4/register/soc/dma_pms_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/dma_pms_struct.h
rename to components/soc/esp32p4/register/soc/dma_pms_struct.h
diff --git a/components/soc/esp32p4/include/soc/ds_reg.h b/components/soc/esp32p4/register/soc/ds_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/ds_reg.h
rename to components/soc/esp32p4/register/soc/ds_reg.h
diff --git a/components/soc/esp32p4/include/soc/ds_struct.h b/components/soc/esp32p4/register/soc/ds_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/ds_struct.h
rename to components/soc/esp32p4/register/soc/ds_struct.h
diff --git a/components/soc/esp32p4/include/soc/dw_gdma_reg.h b/components/soc/esp32p4/register/soc/dw_gdma_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/dw_gdma_reg.h
rename to components/soc/esp32p4/register/soc/dw_gdma_reg.h
diff --git a/components/soc/esp32p4/include/soc/dw_gdma_struct.h b/components/soc/esp32p4/register/soc/dw_gdma_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/dw_gdma_struct.h
rename to components/soc/esp32p4/register/soc/dw_gdma_struct.h
diff --git a/components/soc/esp32p4/register/soc/ecc_mult_reg.h b/components/soc/esp32p4/register/soc/ecc_mult_reg.h
new file mode 100644
index 00000000000..54033489df3
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/ecc_mult_reg.h
@@ -0,0 +1,185 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECC_MULT_INT_RAW_REG register
+ *  ECC interrupt raw register, valid in level.
+ */
+#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
+/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_RAW_S  0
+
+/** ECC_MULT_INT_ST_REG register
+ *  ECC interrupt status register.
+ */
+#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
+/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ST_S  0
+
+/** ECC_MULT_INT_ENA_REG register
+ *  ECC interrupt enable register.
+ */
+#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
+/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ENA_S  0
+
+/** ECC_MULT_INT_CLR_REG register
+ *  ECC interrupt clear register.
+ */
+#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
+/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecc_calc_done_int interrupt
+ */
+#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_CLR_S  0
+
+/** ECC_MULT_CONF_REG register
+ *  ECC configure register
+ */
+#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
+/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
+ *  the caculatrion is done.
+ */
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
+#define ECC_MULT_START_V  0x00000001U
+#define ECC_MULT_START_S  0
+/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
+ *  Write 1 to reset ECC Accelerator.
+ */
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
+#define ECC_MULT_RESET_V  0x00000001U
+#define ECC_MULT_RESET_S  1
+/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
+ *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
+ */
+#define ECC_MULT_KEY_LENGTH    (BIT(2))
+#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
+#define ECC_MULT_KEY_LENGTH_V  0x00000001U
+#define ECC_MULT_KEY_LENGTH_S  2
+/** ECC_MULT_MOD_BASE : R/W; bitpos: [3]; default: 0;
+ *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
+ *  1: p(mod base of curve)
+ */
+#define ECC_MULT_MOD_BASE    (BIT(3))
+#define ECC_MULT_MOD_BASE_M  (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
+#define ECC_MULT_MOD_BASE_V  0x00000001U
+#define ECC_MULT_MOD_BASE_S  3
+/** ECC_MULT_WORK_MODE : R/W; bitpos: [7:4]; default: 0;
+ *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
+ *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
+ *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
+ *  8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division.
+ */
+#define ECC_MULT_WORK_MODE    0x0000000FU
+#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
+#define ECC_MULT_WORK_MODE_V  0x0000000FU
+#define ECC_MULT_WORK_MODE_S  4
+/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define ECC_MULT_SECURITY_MODE    (BIT(8))
+#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
+#define ECC_MULT_SECURITY_MODE_V  0x00000001U
+#define ECC_MULT_SECURITY_MODE_S  8
+/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
+ *  The verification result bit of ECC Accelerator, only valid when calculation is done.
+ */
+#define ECC_MULT_VERIFICATION_RESULT    (BIT(29))
+#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
+#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
+#define ECC_MULT_VERIFICATION_RESULT_S  29
+/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECC_MULT_CLK_EN    (BIT(30))
+#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
+#define ECC_MULT_CLK_EN_V  0x00000001U
+#define ECC_MULT_CLK_EN_S  30
+/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  ECC memory clock gate force on register
+ */
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
+
+/** ECC_MULT_DATE_REG register
+ *  Version control register
+ */
+#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
+/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 36720704;
+ *  ECC mult version control register
+ */
+#define ECC_MULT_DATE    0x0FFFFFFFU
+#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
+#define ECC_MULT_DATE_V  0x0FFFFFFFU
+#define ECC_MULT_DATE_S  0
+
+/** ECC_MULT_K_MEM register
+ *  The memory that stores k.
+ */
+#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
+#define ECC_MULT_K_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_PX_MEM register
+ *  The memory that stores Px.
+ */
+#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x120)
+#define ECC_MULT_PX_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_PY_MEM register
+ *  The memory that stores Py.
+ */
+#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x140)
+#define ECC_MULT_PY_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_QX_MEM register
+ *  The memory that stores Qx.
+ */
+#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x160)
+#define ECC_MULT_QX_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_QY_MEM register
+ *  The memory that stores Qy.
+ */
+#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x180)
+#define ECC_MULT_QY_MEM_SIZE_BYTES 32
+
+/** ECC_MULT_QZ_MEM register
+ *  The memory that stores Qz.
+ */
+#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1A0)
+#define ECC_MULT_QZ_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/ecc_mult_struct.h b/components/soc/esp32p4/register/soc/ecc_mult_struct.h
new file mode 100644
index 00000000000..d868fcc8f1f
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/ecc_mult_struct.h
@@ -0,0 +1,166 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECC interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECC interrupt status register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECC interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECC interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecc_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of conf register
+ *  ECC configure register
+ */
+typedef union {
+    struct {
+        /** start : R/W/SC; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECC Accelerator. This bit will be self-cleared after
+         *  the caculatrion is done.
+         */
+        uint32_t start:1;
+        /** reset : WT; bitpos: [1]; default: 0;
+         *  Write 1 to reset ECC Accelerator.
+         */
+        uint32_t reset:1;
+        /** key_length : R/W; bitpos: [2]; default: 0;
+         *  The key length mode bit of ECC Accelerator.  0: P-192.  1: P-256.
+         */
+        uint32_t key_length:1;
+        /** mod_base : R/W; bitpos: [3]; default: 0;
+         *  The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve).
+         *  1: p(mod base of curve)
+         */
+        uint32_t mod_base:1;
+        /** work_mode : R/W; bitpos: [7:4]; default: 0;
+         *  The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
+         *  verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point
+         *  Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode.
+         *  8: mod addition. 9. mod subtraction. 10: mod multiplication. 11: mod division.
+         */
+        uint32_t work_mode:4;
+        /** security_mode : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t security_mode:1;
+        uint32_t reserved_9:20;
+        /** verification_result : RO/SS; bitpos: [29]; default: 0;
+         *  The verification result bit of ECC Accelerator, only valid when calculation is done.
+         */
+        uint32_t verification_result:1;
+        /** clk_en : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_en:1;
+        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
+         *  ECC memory clock gate force on register
+         */
+        uint32_t mem_clock_gate_force_on:1;
+    };
+    uint32_t val;
+} ecc_mult_conf_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36720704;
+         *  ECC mult version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecc_mult_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile ecc_mult_int_raw_reg_t int_raw;
+    volatile ecc_mult_int_st_reg_t int_st;
+    volatile ecc_mult_int_ena_reg_t int_ena;
+    volatile ecc_mult_int_clr_reg_t int_clr;
+    volatile ecc_mult_conf_reg_t conf;
+    uint32_t reserved_020[55];
+    volatile ecc_mult_date_reg_t date;
+    volatile uint32_t k[8];
+    volatile uint32_t px[8];
+    volatile uint32_t py[8];
+    volatile uint32_t qx[8];
+    volatile uint32_t qy[8];
+    volatile uint32_t qz[8];
+} ecc_mult_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecc_mult_dev_t) == 0x1C0, "Invalid size of ecc_mult_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/ecdsa_reg.h b/components/soc/esp32p4/register/soc/ecdsa_reg.h
new file mode 100644
index 00000000000..b5cc4f696af
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/ecdsa_reg.h
@@ -0,0 +1,318 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECDSA_CONF_REG register
+ *  ECDSA configure register
+ */
+#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
+/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+ *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+ */
+#define ECDSA_WORK_MODE    0x00000003U
+#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
+#define ECDSA_WORK_MODE_V  0x00000003U
+#define ECDSA_WORK_MODE_S  0
+/** ECDSA_ECC_CURVE : R/W; bitpos: [2]; default: 0;
+ *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
+ */
+#define ECDSA_ECC_CURVE    (BIT(2))
+#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
+#define ECDSA_ECC_CURVE_V  0x00000001U
+#define ECDSA_ECC_CURVE_S  2
+/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [3]; default: 0;
+ *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+ *  written by software.
+ */
+#define ECDSA_SOFTWARE_SET_K    (BIT(3))
+#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
+#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_K_S  3
+/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [4]; default: 0;
+ *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+ *  software.
+ */
+#define ECDSA_SOFTWARE_SET_Z    (BIT(4))
+#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
+#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_Z_S  4
+/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [5]; default: 0;
+ *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+ *  deterministic derivation algorithm.
+ */
+#define ECDSA_DETERMINISTIC_K    (BIT(5))
+#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
+#define ECDSA_DETERMINISTIC_K_V  0x00000001U
+#define ECDSA_DETERMINISTIC_K_S  5
+/** ECDSA_DETERMINISTIC_LOOP : R/W; bitpos: [21:6]; default: 0;
+ *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
+ */
+#define ECDSA_DETERMINISTIC_LOOP    0x0000FFFFU
+#define ECDSA_DETERMINISTIC_LOOP_M  (ECDSA_DETERMINISTIC_LOOP_V << ECDSA_DETERMINISTIC_LOOP_S)
+#define ECDSA_DETERMINISTIC_LOOP_V  0x0000FFFFU
+#define ECDSA_DETERMINISTIC_LOOP_S  6
+
+/** ECDSA_CLK_REG register
+ *  ECDSA clock gate register
+ */
+#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
+/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
+#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
+#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
+#define ECDSA_CLK_GATE_FORCE_ON_S  0
+
+/** ECDSA_INT_RAW_REG register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
+/** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_RAW    (BIT(0))
+#define ECDSA_CALC_DONE_INT_RAW_M  (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S)
+#define ECDSA_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_RAW_S  0
+/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
+#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_RAW_S  1
+
+/** ECDSA_INT_ST_REG register
+ *  ECDSA interrupt status register.
+ */
+#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
+/** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_ST    (BIT(0))
+#define ECDSA_CALC_DONE_INT_ST_M  (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S)
+#define ECDSA_CALC_DONE_INT_ST_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_ST_S  0
+/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ST    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
+#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ST_S  1
+
+/** ECDSA_INT_ENA_REG register
+ *  ECDSA interrupt enable register.
+ */
+#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
+/** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_ENA    (BIT(0))
+#define ECDSA_CALC_DONE_INT_ENA_M  (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S)
+#define ECDSA_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_ENA_S  0
+/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
+#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ENA_S  1
+
+/** ECDSA_INT_CLR_REG register
+ *  ECDSA interrupt clear register.
+ */
+#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
+/** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecdsa_calc_done_int interrupt
+ */
+#define ECDSA_CALC_DONE_INT_CLR    (BIT(0))
+#define ECDSA_CALC_DONE_INT_CLR_M  (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S)
+#define ECDSA_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_CALC_DONE_INT_CLR_S  0
+/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(1))
+#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
+#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_CLR_S  1
+
+/** ECDSA_START_REG register
+ *  ECDSA start register
+ */
+#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
+/** ECDSA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+ *  after configuration.
+ */
+#define ECDSA_START    (BIT(0))
+#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
+#define ECDSA_START_V  0x00000001U
+#define ECDSA_START_S  0
+/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_LOAD_DONE    (BIT(1))
+#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
+#define ECDSA_LOAD_DONE_V  0x00000001U
+#define ECDSA_LOAD_DONE_S  1
+/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_GET_DONE    (BIT(2))
+#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
+#define ECDSA_GET_DONE_V  0x00000001U
+#define ECDSA_GET_DONE_S  2
+
+/** ECDSA_STATE_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
+/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
+ *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+ *  state.
+ */
+#define ECDSA_BUSY    0x00000003U
+#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
+#define ECDSA_BUSY_V  0x00000003U
+#define ECDSA_BUSY_S  0
+
+/** ECDSA_RESULT_REG register
+ *  ECDSA result register
+ */
+#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
+/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+ *  done.
+ */
+#define ECDSA_OPERATION_RESULT    (BIT(0))
+#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
+#define ECDSA_OPERATION_RESULT_V  0x00000001U
+#define ECDSA_OPERATION_RESULT_S  0
+/** ECDSA_K_VALUE_WARNING : RO/SS; bitpos: [1]; default: 0;
+ *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
+ *  curve order, then actually taken k = k mod n.
+ */
+#define ECDSA_K_VALUE_WARNING    (BIT(1))
+#define ECDSA_K_VALUE_WARNING_M  (ECDSA_K_VALUE_WARNING_V << ECDSA_K_VALUE_WARNING_S)
+#define ECDSA_K_VALUE_WARNING_V  0x00000001U
+#define ECDSA_K_VALUE_WARNING_S  1
+
+/** ECDSA_DATE_REG register
+ *  Version control register
+ */
+#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
+/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 36716656;
+ *  ECDSA version control register
+ */
+#define ECDSA_DATE    0x0FFFFFFFU
+#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
+#define ECDSA_DATE_V  0x0FFFFFFFU
+#define ECDSA_DATE_S  0
+
+/** ECDSA_SHA_MODE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
+/** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
+ *  Others: invalid.
+ */
+#define ECDSA_SHA_MODE    0x00000007U
+#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
+#define ECDSA_SHA_MODE_V  0x00000007U
+#define ECDSA_SHA_MODE_S  0
+
+/** ECDSA_SHA_START_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
+/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_START    (BIT(0))
+#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
+#define ECDSA_SHA_START_V  0x00000001U
+#define ECDSA_SHA_START_S  0
+
+/** ECDSA_SHA_CONTINUE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
+/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_CONTINUE    (BIT(0))
+#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
+#define ECDSA_SHA_CONTINUE_V  0x00000001U
+#define ECDSA_SHA_CONTINUE_S  0
+
+/** ECDSA_SHA_BUSY_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
+/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
+ *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+ *  calculation. 0: SHA is idle.
+ */
+#define ECDSA_SHA_BUSY    (BIT(0))
+#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
+#define ECDSA_SHA_BUSY_V  0x00000001U
+#define ECDSA_SHA_BUSY_S  0
+
+/** ECDSA_MESSAGE_MEM register
+ *  The memory that stores message.
+ */
+#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
+#define ECDSA_MESSAGE_MEM_SIZE_BYTES 32
+
+/** ECDSA_R_MEM register
+ *  The memory that stores r.
+ */
+#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00)
+#define ECDSA_R_MEM_SIZE_BYTES 32
+
+/** ECDSA_S_MEM register
+ *  The memory that stores s.
+ */
+#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20)
+#define ECDSA_S_MEM_SIZE_BYTES 32
+
+/** ECDSA_Z_MEM register
+ *  The memory that stores software written z.
+ */
+#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40)
+#define ECDSA_Z_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAX_MEM register
+ *  The memory that stores x coordinates of QA or software written k.
+ */
+#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60)
+#define ECDSA_QAX_MEM_SIZE_BYTES 32
+
+/** ECDSA_QAY_MEM register
+ *  The memory that stores y coordinates of QA.
+ */
+#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80)
+#define ECDSA_QAY_MEM_SIZE_BYTES 32
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/ecdsa_struct.h b/components/soc/esp32p4/register/soc/ecdsa_struct.h
new file mode 100644
index 00000000000..67e226f86d5
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/ecdsa_struct.h
@@ -0,0 +1,323 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Data Memory */
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  ECDSA configure register
+ */
+typedef union {
+    struct {
+        /** work_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+         *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+         */
+        uint32_t work_mode:2;
+        /** ecc_curve : R/W; bitpos: [2]; default: 0;
+         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192.  1: P-256.
+         */
+        uint32_t ecc_curve:1;
+        /** software_set_k : R/W; bitpos: [3]; default: 0;
+         *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+         *  written by software.
+         */
+        uint32_t software_set_k:1;
+        /** software_set_z : R/W; bitpos: [4]; default: 0;
+         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+         *  software.
+         */
+        uint32_t software_set_z:1;
+        /** deterministic_k : R/W; bitpos: [5]; default: 0;
+         *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+         *  deterministic derivation algorithm.
+         */
+        uint32_t deterministic_k:1;
+        /** deterministic_loop : R/W; bitpos: [21:6]; default: 0;
+         *  The (loop number - 1) value in the deterministic derivation algorithm to derive k.
+         */
+        uint32_t deterministic_loop:16;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} ecdsa_conf_reg_t;
+
+/** Type of start register
+ *  ECDSA start register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+         *  after configuration.
+         */
+        uint32_t start:1;
+        /** load_done : WT; bitpos: [1]; default: 0;
+         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t load_done:1;
+        /** get_done : WT; bitpos: [2]; default: 0;
+         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t get_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_start_reg_t;
+
+
+/** Group: Clock and reset registers */
+/** Type of clk register
+ *  ECDSA clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_gate_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_raw:1;
+        /** sha_release_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECDSA interrupt status register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_st:1;
+        /** sha_release_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECDSA interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_ena:1;
+        /** sha_release_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECDSA interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecdsa_calc_done_int interrupt
+         */
+        uint32_t calc_done_int_clr:1;
+        /** sha_release_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_int_clr_reg_t;
+
+
+/** Group: Status registers */
+/** Type of state register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** busy : RO; bitpos: [1:0]; default: 0;
+         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+         *  state.
+         */
+        uint32_t busy:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of result register
+ *  ECDSA result register
+ */
+typedef union {
+    struct {
+        /** operation_result : RO/SS; bitpos: [0]; default: 0;
+         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+         *  done.
+         */
+        uint32_t operation_result:1;
+        /** k_value_warning : RO/SS; bitpos: [1]; default: 0;
+         *  The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the
+         *  curve order, then actually taken k = k mod n.
+         */
+        uint32_t k_value_warning:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_result_reg_t;
+
+
+/** Group: SHA register */
+/** Type of sha_mode register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_mode : R/W; bitpos: [2:0]; default: 0;
+         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256.
+         *  Others: invalid.
+         */
+        uint32_t sha_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_sha_mode_reg_t;
+
+/** Type of sha_start register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_start_reg_t;
+
+/** Type of sha_continue register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_continue : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_continue_reg_t;
+
+/** Type of sha_busy register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** sha_busy : RO; bitpos: [0]; default: 0;
+         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+         *  calculation. 0: SHA is idle.
+         */
+        uint32_t sha_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_busy_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36716656;
+         *  ECDSA version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecdsa_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile ecdsa_conf_reg_t conf;
+    volatile ecdsa_clk_reg_t clk;
+    volatile ecdsa_int_raw_reg_t int_raw;
+    volatile ecdsa_int_st_reg_t int_st;
+    volatile ecdsa_int_ena_reg_t int_ena;
+    volatile ecdsa_int_clr_reg_t int_clr;
+    volatile ecdsa_start_reg_t start;
+    volatile ecdsa_state_reg_t state;
+    volatile ecdsa_result_reg_t result;
+    uint32_t reserved_028[53];
+    volatile ecdsa_date_reg_t date;
+    uint32_t reserved_100[64];
+    volatile ecdsa_sha_mode_reg_t sha_mode;
+    uint32_t reserved_204[3];
+    volatile ecdsa_sha_start_reg_t sha_start;
+    volatile ecdsa_sha_continue_reg_t sha_continue;
+    volatile ecdsa_sha_busy_reg_t sha_busy;
+    uint32_t reserved_21c[25];
+    volatile uint32_t message[8];
+    uint32_t reserved_2a0[472];
+    volatile uint32_t r[8];
+    volatile uint32_t s[8];
+    volatile uint32_t z[8];
+    volatile uint32_t qax[8];
+    volatile uint32_t qay[8];
+} ecdsa_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecdsa_dev_t) == 0xaa0, "Invalid size of ecdsa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/efuse_reg.h b/components/soc/esp32p4/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..37d92689c6a
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/efuse_reg.h
@@ -0,0 +1,4653 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/efuse_defs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled or
+ *  enabled. 1: Disabled. 0 Enabled.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [7]; default: 0;
+ *  Enable usb device exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(7))
+#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
+#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_DEVICE_EXCHG_PINS_S  7
+/** EFUSE_USB_OTG11_EXCHG_PINS : RO; bitpos: [8]; default: 0;
+ *  Enable usb otg11 exchange pins of D+ and D-.
+ */
+#define EFUSE_USB_OTG11_EXCHG_PINS    (BIT(8))
+#define EFUSE_USB_OTG11_EXCHG_PINS_M  (EFUSE_USB_OTG11_EXCHG_PINS_V << EFUSE_USB_OTG11_EXCHG_PINS_S)
+#define EFUSE_USB_OTG11_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_OTG11_EXCHG_PINS_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0;
+ *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_POWERGLITCH_EN    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0;
+ *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+ *  boot_mode_download.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ *  is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+ *  enabled.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+ *  enabled.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode). 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_DEVICE_DREFH    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_M  (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S)
+#define EFUSE_USB_DEVICE_DREFH_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_S  21
+/** EFUSE_USB_OTG11_DREFH : RO; bitpos: [24:23]; default: 0;
+ *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+ */
+#define EFUSE_USB_OTG11_DREFH    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_M  (EFUSE_USB_OTG11_DREFH_V << EFUSE_USB_OTG11_DREFH_S)
+#define EFUSE_USB_OTG11_DREFH_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_S  23
+/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
+ *  TBD
+ */
+#define EFUSE_USB_PHY_SEL    (BIT(25))
+#define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
+#define EFUSE_USB_PHY_SEL_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_S  25
+/** EFUSE_KM_HUK_GEN_STATE_LOW : RO; bitpos: [31:26]; default: 0;
+ *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+ *  of 1 is valid.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_LOW    0x0000003FU
+#define EFUSE_KM_HUK_GEN_STATE_LOW_M  (EFUSE_KM_HUK_GEN_STATE_LOW_V << EFUSE_KM_HUK_GEN_STATE_LOW_S)
+#define EFUSE_KM_HUK_GEN_STATE_LOW_V  0x0000003FU
+#define EFUSE_KM_HUK_GEN_STATE_LOW_S  26
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register 2.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_KM_HUK_GEN_STATE_HIGH : RO; bitpos: [2:0]; default: 0;
+ *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+ *  of 1 is valid.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_HIGH    0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_V << EFUSE_KM_HUK_GEN_STATE_HIGH_S)
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_V  0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [4:3]; default: 0;
+ *  Set bits to control key manager random number switch cycle. 0: control by register.
+ *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_S  3
+/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [8:5]; default: 0;
+ *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+ *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  5
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [12:9]; default: 0;
+ *  Set each bit to control whether corresponding key must come from key manager.. 1 is
+ *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  9
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable software written init key, and force use efuse_init_key.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  13
+/** EFUSE_XTS_KEY_LENGTH_256 : RO; bitpos: [14]; default: 0;
+ *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_M  (EFUSE_XTS_KEY_LENGTH_256_V << EFUSE_XTS_KEY_LENGTH_256_S)
+#define EFUSE_XTS_KEY_LENGTH_256_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_S  14
+/** EFUSE_RD_RESERVE_0_79 : RW; bitpos: [15]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_79    (BIT(15))
+#define EFUSE_RD_RESERVE_0_79_M  (EFUSE_RD_RESERVE_0_79_V << EFUSE_RD_RESERVE_0_79_S)
+#define EFUSE_RD_RESERVE_0_79_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_79_S  15
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+ *  selected. 0: not selected.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+ *  1: enabled. Even number of 1: disabled.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register 3.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Represents the purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  16
+/** EFUSE_ECDSA_ENABLE_SOFT_K : RO; bitpos: [18]; default: 0;
+ *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+ *  0: not force used.
+ */
+#define EFUSE_ECDSA_ENABLE_SOFT_K    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_M  (EFUSE_ECDSA_ENABLE_SOFT_K_V << EFUSE_ECDSA_ENABLE_SOFT_K_S)
+#define EFUSE_ECDSA_ENABLE_SOFT_K_V  0x00000001U
+#define EFUSE_ECDSA_ENABLE_SOFT_K_S  18
+/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
+ *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_M  (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
+#define EFUSE_CRYPT_DPA_ENABLE_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_S  19
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+ *  enabled. 0: disabled.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RD_RESERVE_0_118 : RW; bitpos: [22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_118    (BIT(22))
+#define EFUSE_RD_RESERVE_0_118_M  (EFUSE_RD_RESERVE_0_118_V << EFUSE_RD_RESERVE_0_118_S)
+#define EFUSE_RD_RESERVE_0_118_V  0x00000001U
+#define EFUSE_RD_RESERVE_0_118_S  22
+/** EFUSE_FLASH_TYPE : RO; bitpos: [23]; default: 0;
+ *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
+ */
+#define EFUSE_FLASH_TYPE    (BIT(23))
+#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V  0x00000001U
+#define EFUSE_FLASH_TYPE_S  23
+/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [25:24]; default: 0;
+ *  Set flash page size.
+ */
+#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
+#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_S  24
+/** EFUSE_FLASH_ECC_EN : RO; bitpos: [26]; default: 0;
+ *  Set this bit to enable ecc for flash boot.
+ */
+#define EFUSE_FLASH_ECC_EN    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
+#define EFUSE_FLASH_ECC_EN_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_S  26
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [27]; default: 0;
+ *  Set this bit to disable download via USB-OTG.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  27
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+ *  is 2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register 4.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+ *  0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_LOCK_KM_KEY : RO; bitpos: [3]; default: 0;
+ *  TBD
+ */
+#define EFUSE_LOCK_KM_KEY    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
+#define EFUSE_LOCK_KM_KEY_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+ *  disabled. 0: enabled.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+ *  disabled.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Represents the type of UART printing. 00: force enable printing. 01: enable
+ *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+ *  at high level. 11: force disable printing.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+ *  forced. 0:not forced.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  8
+/** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0;
+ *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+ *  enabled. 1: disabled. 0: enabled.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  25
+/** EFUSE_HYS_EN_PAD : RO; bitpos: [26]; default: 0;
+ *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
+ *  enabled. 0:disabled.
+ */
+#define EFUSE_HYS_EN_PAD    (BIT(26))
+#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
+#define EFUSE_HYS_EN_PAD_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_S  26
+/** EFUSE_DCDC_VSET : RO; bitpos: [31:27]; default: 0;
+ *  Set the dcdc voltage default.
+ */
+#define EFUSE_DCDC_VSET    0x0000001FU
+#define EFUSE_DCDC_VSET_M  (EFUSE_DCDC_VSET_V << EFUSE_DCDC_VSET_S)
+#define EFUSE_DCDC_VSET_V  0x0000001FU
+#define EFUSE_DCDC_VSET_S  27
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register 5.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_PXA0_TIEH_SEL_0 : RO; bitpos: [1:0]; default: 0;
+ *  TBD
+ */
+#define EFUSE_PXA0_TIEH_SEL_0    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_M  (EFUSE_PXA0_TIEH_SEL_0_V << EFUSE_PXA0_TIEH_SEL_0_S)
+#define EFUSE_PXA0_TIEH_SEL_0_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_S  0
+/** EFUSE_PXA0_TIEH_SEL_1 : RO; bitpos: [3:2]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_1    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_M  (EFUSE_PXA0_TIEH_SEL_1_V << EFUSE_PXA0_TIEH_SEL_1_S)
+#define EFUSE_PXA0_TIEH_SEL_1_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_S  2
+/** EFUSE_PXA0_TIEH_SEL_2 : RO; bitpos: [5:4]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_2    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_M  (EFUSE_PXA0_TIEH_SEL_2_V << EFUSE_PXA0_TIEH_SEL_2_S)
+#define EFUSE_PXA0_TIEH_SEL_2_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_S  4
+/** EFUSE_PXA0_TIEH_SEL_3 : RO; bitpos: [7:6]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_PXA0_TIEH_SEL_3    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_M  (EFUSE_PXA0_TIEH_SEL_3_V << EFUSE_PXA0_TIEH_SEL_3_S)
+#define EFUSE_PXA0_TIEH_SEL_3_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_S  6
+/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [11:8]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  8
+/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
+ *  Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step
+ *  of 80 mV
+ */
+#define EFUSE_USB_DEVICE_DREFL    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_M  (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
+#define EFUSE_USB_DEVICE_DREFL_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_S  12
+/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
+ *  Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step
+ *  of 80 mV
+ */
+#define EFUSE_USB_OTG11_DREFL    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_M  (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
+#define EFUSE_USB_OTG11_DREFL_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_S  14
+/** EFUSE_RD_RESERVE_0_176 : RW; bitpos: [17:16]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_176    0x00000003U
+#define EFUSE_RD_RESERVE_0_176_M  (EFUSE_RD_RESERVE_0_176_V << EFUSE_RD_RESERVE_0_176_S)
+#define EFUSE_RD_RESERVE_0_176_V  0x00000003U
+#define EFUSE_RD_RESERVE_0_176_S  16
+/** EFUSE_HP_PWR_SRC_SEL : RO; bitpos: [18]; default: 0;
+ *  HP system power source select. 0:LDO. 1: DCDC.
+ */
+#define EFUSE_HP_PWR_SRC_SEL    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_M  (EFUSE_HP_PWR_SRC_SEL_V << EFUSE_HP_PWR_SRC_SEL_S)
+#define EFUSE_HP_PWR_SRC_SEL_V  0x00000001U
+#define EFUSE_HP_PWR_SRC_SEL_S  18
+/** EFUSE_DCDC_VSET_EN : RO; bitpos: [19]; default: 0;
+ *  Select dcdc vset use efuse_dcdc_vset.
+ */
+#define EFUSE_DCDC_VSET_EN    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_M  (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S)
+#define EFUSE_DCDC_VSET_EN_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_S  19
+/** EFUSE_DIS_WDT : RO; bitpos: [20]; default: 0;
+ *  Set this bit to disable watch dog.
+ */
+#define EFUSE_DIS_WDT    (BIT(20))
+#define EFUSE_DIS_WDT_M  (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S)
+#define EFUSE_DIS_WDT_V  0x00000001U
+#define EFUSE_DIS_WDT_S  20
+/** EFUSE_DIS_SWD : RO; bitpos: [21]; default: 0;
+ *  Set this bit to disable super-watchdog.
+ */
+#define EFUSE_DIS_SWD    (BIT(21))
+#define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
+#define EFUSE_DIS_SWD_V  0x00000001U
+#define EFUSE_DIS_SWD_S  21
+/** EFUSE_RD_RESERVE_0_182 : RW; bitpos: [31:22]; default: 0;
+ *  Reserved, it was created by set_missed_fields_in_regs func
+ */
+#define EFUSE_RD_RESERVE_0_182    0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_M  (EFUSE_RD_RESERVE_0_182_V << EFUSE_RD_RESERVE_0_182_S)
+#define EFUSE_RD_RESERVE_0_182_V  0x000003FFU
+#define EFUSE_RD_RESERVE_0_182_S  22
+
+/** EFUSE_RD_MAC_SYS_0_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SYS_1_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_RESERVED_1_16 : RO; bitpos: [31:16]; default: 0;
+ *  Stores the extended bits of MAC address.
+ */
+#define EFUSE_RESERVED_1_16    0x0000FFFFU
+#define EFUSE_RESERVED_1_16_M  (EFUSE_RESERVED_1_16_V << EFUSE_RESERVED_1_16_S)
+#define EFUSE_RESERVED_1_16_V  0x0000FFFFU
+#define EFUSE_RESERVED_1_16_S  16
+
+/** EFUSE_RD_MAC_SYS_2_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [3:0]; default: 0;
+ *  Minor chip version
+ */
+#define EFUSE_WAFER_VERSION_MINOR    0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_M  (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
+#define EFUSE_WAFER_VERSION_MINOR_V  0x0000000FU
+#define EFUSE_WAFER_VERSION_MINOR_S  0
+/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [5:4]; default: 0;
+ *  Major chip version
+ */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  4
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [6]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(6))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  6
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(7))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  7
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [10:8]; default: 0;
+ *  BLK_VERSION_MINOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  8
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [12:11]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  11
+/** EFUSE_PSRAM_CAP : R; bitpos: [15:13]; default: 0;
+ *  PSRAM capacity
+ */
+#define EFUSE_PSRAM_CAP    0x00000007U
+#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
+#define EFUSE_PSRAM_CAP_V  0x00000007U
+#define EFUSE_PSRAM_CAP_S  13
+/** EFUSE_TEMP : R; bitpos: [17:16]; default: 0;
+ *  Operating temperature of the ESP chip
+ */
+#define EFUSE_TEMP    0x00000003U
+#define EFUSE_TEMP_M  (EFUSE_TEMP_V << EFUSE_TEMP_S)
+#define EFUSE_TEMP_V  0x00000003U
+#define EFUSE_TEMP_S  16
+/** EFUSE_PSRAM_VENDOR : R; bitpos: [19:18]; default: 0;
+ *  PSRAM vendor
+ */
+#define EFUSE_PSRAM_VENDOR    0x00000003U
+#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
+#define EFUSE_PSRAM_VENDOR_V  0x00000003U
+#define EFUSE_PSRAM_VENDOR_S  18
+/** EFUSE_PKG_VERSION : R; bitpos: [22:20]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  20
+/** EFUSE_RESERVED_1_87 : R; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_87    (BIT(23))
+#define EFUSE_RESERVED_1_87_M  (EFUSE_RESERVED_1_87_V << EFUSE_RESERVED_1_87_S)
+#define EFUSE_RESERVED_1_87_V  0x00000001U
+#define EFUSE_RESERVED_1_87_S  23
+/** EFUSE_LDO_VO1_DREF : R; bitpos: [27:24]; default: 0;
+ *  Output VO1 parameter
+ */
+#define EFUSE_LDO_VO1_DREF    0x0000000FU
+#define EFUSE_LDO_VO1_DREF_M  (EFUSE_LDO_VO1_DREF_V << EFUSE_LDO_VO1_DREF_S)
+#define EFUSE_LDO_VO1_DREF_V  0x0000000FU
+#define EFUSE_LDO_VO1_DREF_S  24
+/** EFUSE_LDO_VO2_DREF : R; bitpos: [31:28]; default: 0;
+ *  Output VO2 parameter
+ */
+#define EFUSE_LDO_VO2_DREF    0x0000000FU
+#define EFUSE_LDO_VO2_DREF_M  (EFUSE_LDO_VO2_DREF_V << EFUSE_LDO_VO2_DREF_S)
+#define EFUSE_LDO_VO2_DREF_V  0x0000000FU
+#define EFUSE_LDO_VO2_DREF_S  28
+
+/** EFUSE_RD_MAC_SYS_3_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_LDO_VO1_MUL : R; bitpos: [2:0]; default: 0;
+ *  Output VO1 parameter
+ */
+#define EFUSE_LDO_VO1_MUL    0x00000007U
+#define EFUSE_LDO_VO1_MUL_M  (EFUSE_LDO_VO1_MUL_V << EFUSE_LDO_VO1_MUL_S)
+#define EFUSE_LDO_VO1_MUL_V  0x00000007U
+#define EFUSE_LDO_VO1_MUL_S  0
+/** EFUSE_LDO_VO2_MUL : R; bitpos: [5:3]; default: 0;
+ *  Output VO2 parameter
+ */
+#define EFUSE_LDO_VO2_MUL    0x00000007U
+#define EFUSE_LDO_VO2_MUL_M  (EFUSE_LDO_VO2_MUL_V << EFUSE_LDO_VO2_MUL_S)
+#define EFUSE_LDO_VO2_MUL_V  0x00000007U
+#define EFUSE_LDO_VO2_MUL_S  3
+/** EFUSE_LDO_VO3_K : R; bitpos: [13:6]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_K    0x000000FFU
+#define EFUSE_LDO_VO3_K_M  (EFUSE_LDO_VO3_K_V << EFUSE_LDO_VO3_K_S)
+#define EFUSE_LDO_VO3_K_V  0x000000FFU
+#define EFUSE_LDO_VO3_K_S  6
+/** EFUSE_LDO_VO3_VOS : R; bitpos: [19:14]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_VOS    0x0000003FU
+#define EFUSE_LDO_VO3_VOS_M  (EFUSE_LDO_VO3_VOS_V << EFUSE_LDO_VO3_VOS_S)
+#define EFUSE_LDO_VO3_VOS_V  0x0000003FU
+#define EFUSE_LDO_VO3_VOS_S  14
+/** EFUSE_LDO_VO3_C : R; bitpos: [25:20]; default: 0;
+ *  Output VO3 calibration parameter
+ */
+#define EFUSE_LDO_VO3_C    0x0000003FU
+#define EFUSE_LDO_VO3_C_M  (EFUSE_LDO_VO3_C_V << EFUSE_LDO_VO3_C_S)
+#define EFUSE_LDO_VO3_C_V  0x0000003FU
+#define EFUSE_LDO_VO3_C_S  20
+/** EFUSE_LDO_VO4_K : R; bitpos: [31:26]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_K    0x0000003FU
+#define EFUSE_LDO_VO4_K_M  (EFUSE_LDO_VO4_K_V << EFUSE_LDO_VO4_K_S)
+#define EFUSE_LDO_VO4_K_V  0x0000003FU
+#define EFUSE_LDO_VO4_K_S  26
+
+/** EFUSE_RD_MAC_SYS_4_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_LDO_VO4_K_1 : R; bitpos: [1:0]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_K_1    0x00000003U
+#define EFUSE_LDO_VO4_K_1_M  (EFUSE_LDO_VO4_K_1_V << EFUSE_LDO_VO4_K_1_S)
+#define EFUSE_LDO_VO4_K_1_V  0x00000003U
+#define EFUSE_LDO_VO4_K_1_S  0
+/** EFUSE_LDO_VO4_VOS : R; bitpos: [7:2]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_VOS    0x0000003FU
+#define EFUSE_LDO_VO4_VOS_M  (EFUSE_LDO_VO4_VOS_V << EFUSE_LDO_VO4_VOS_S)
+#define EFUSE_LDO_VO4_VOS_V  0x0000003FU
+#define EFUSE_LDO_VO4_VOS_S  2
+/** EFUSE_LDO_VO4_C : R; bitpos: [13:8]; default: 0;
+ *  Output VO4 calibration parameter
+ */
+#define EFUSE_LDO_VO4_C    0x0000003FU
+#define EFUSE_LDO_VO4_C_M  (EFUSE_LDO_VO4_C_V << EFUSE_LDO_VO4_C_S)
+#define EFUSE_LDO_VO4_C_V  0x0000003FU
+#define EFUSE_LDO_VO4_C_S  8
+/** EFUSE_RESERVED_1_142 : R; bitpos: [15:14]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_142    0x00000003U
+#define EFUSE_RESERVED_1_142_M  (EFUSE_RESERVED_1_142_V << EFUSE_RESERVED_1_142_S)
+#define EFUSE_RESERVED_1_142_V  0x00000003U
+#define EFUSE_RESERVED_1_142_S  14
+/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [19:16]; default: 0;
+ *  Active HP DBIAS of fixed voltage
+ */
+#define EFUSE_ACTIVE_HP_DBIAS    0x0000000FU
+#define EFUSE_ACTIVE_HP_DBIAS_M  (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
+#define EFUSE_ACTIVE_HP_DBIAS_V  0x0000000FU
+#define EFUSE_ACTIVE_HP_DBIAS_S  16
+/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [23:20]; default: 0;
+ *  Active LP DBIAS of fixed voltage
+ */
+#define EFUSE_ACTIVE_LP_DBIAS    0x0000000FU
+#define EFUSE_ACTIVE_LP_DBIAS_M  (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
+#define EFUSE_ACTIVE_LP_DBIAS_V  0x0000000FU
+#define EFUSE_ACTIVE_LP_DBIAS_S  20
+/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [27:24]; default: 0;
+ *  LSLP HP DBIAS of fixed voltage
+ */
+#define EFUSE_LSLP_HP_DBIAS    0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_M  (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
+#define EFUSE_LSLP_HP_DBIAS_V  0x0000000FU
+#define EFUSE_LSLP_HP_DBIAS_S  24
+/** EFUSE_DSLP_DBG : R; bitpos: [31:28]; default: 0;
+ *  DSLP BDG of fixed voltage
+ */
+#define EFUSE_DSLP_DBG    0x0000000FU
+#define EFUSE_DSLP_DBG_M  (EFUSE_DSLP_DBG_V << EFUSE_DSLP_DBG_S)
+#define EFUSE_DSLP_DBG_V  0x0000000FU
+#define EFUSE_DSLP_DBG_S  28
+
+/** EFUSE_RD_MAC_SYS_5_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [4:0]; default: 0;
+ *  DSLP LP DBIAS of fixed voltage
+ */
+#define EFUSE_DSLP_LP_DBIAS    0x0000001FU
+#define EFUSE_DSLP_LP_DBIAS_M  (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
+#define EFUSE_DSLP_LP_DBIAS_V  0x0000001FU
+#define EFUSE_DSLP_LP_DBIAS_S  0
+/** EFUSE_LP_DCDC_DBIAS_VOL_GAP : R; bitpos: [9:5]; default: 0;
+ *  DBIAS gap between LP and DCDC
+ */
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP    0x0000001FU
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_M  (EFUSE_LP_DCDC_DBIAS_VOL_GAP_V << EFUSE_LP_DCDC_DBIAS_VOL_GAP_S)
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_V  0x0000001FU
+#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_S  5
+/** EFUSE_RESERVED_1_170 : R; bitpos: [31:10]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_170    0x003FFFFFU
+#define EFUSE_RESERVED_1_170_M  (EFUSE_RESERVED_1_170_V << EFUSE_RESERVED_1_170_S)
+#define EFUSE_RESERVED_1_170_V  0x003FFFFFU
+#define EFUSE_RESERVED_1_170_S  10
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [9:0]; default: 0;
+ *  Average initcode of ADC1 atten0
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S  0
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [19:10]; default: 0;
+ *  Average initcode of ADC1 atten1
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S  10
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [29:20]; default: 0;
+ *  Average initcode of ADC1 atten2
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S  20
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [31:30]; default: 0;
+ *  Average initcode of ADC1 atten3
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3    0x00000003U
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V  0x00000003U
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S  30
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
+ *  Average initcode of ADC1 atten3
+ */
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1    0x000000FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_M  (EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S)
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V  0x000000FFU
+#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S  0
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN0 : R; bitpos: [17:8]; default: 0;
+ *  Average initcode of ADC2 atten0
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN0_V << EFUSE_ADC2_AVE_INITCODE_ATTEN0_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_S  8
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN1 : R; bitpos: [27:18]; default: 0;
+ *  Average initcode of ADC2 atten1
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN1_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_S  18
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN2 : R; bitpos: [31:28]; default: 0;
+ *  Average initcode of ADC2 atten2
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2    0x0000000FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN2_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_V  0x0000000FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_S  28
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 : R; bitpos: [5:0]; default: 0;
+ *  Average initcode of ADC2 atten2
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1    0x0000003FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V  0x0000003FU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S  0
+/** EFUSE_ADC2_AVE_INITCODE_ATTEN3 : R; bitpos: [15:6]; default: 0;
+ *  Average initcode of ADC2 atten3
+ */
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3    0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_M  (EFUSE_ADC2_AVE_INITCODE_ATTEN3_V << EFUSE_ADC2_AVE_INITCODE_ATTEN3_S)
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_S  6
+/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [25:16]; default: 0;
+ *  HI_DOUT of ADC1 atten0
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN0    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_M  (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN0_S  16
+/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [31:26]; default: 0;
+ *  HI_DOUT of ADC1 atten1
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1    0x0000003FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_V  0x0000003FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_S  26
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_ADC1_HI_DOUT_ATTEN1_1 : R; bitpos: [3:0]; default: 0;
+ *  HI_DOUT of ADC1 atten1
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1    0x0000000FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_M  (EFUSE_ADC1_HI_DOUT_ATTEN1_1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_1_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_V  0x0000000FU
+#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_S  0
+/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [13:4]; default: 0;
+ *  HI_DOUT of ADC1 atten2
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_M  (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN2_S  4
+/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [23:14]; default: 0;
+ *  HI_DOUT of ADC1 atten3
+ */
+#define EFUSE_ADC1_HI_DOUT_ATTEN3    0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_M  (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_V  0x000003FFU
+#define EFUSE_ADC1_HI_DOUT_ATTEN3_S  14
+/** EFUSE_RESERVED_2_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_248    0x000000FFU
+#define EFUSE_RESERVED_2_248_M  (EFUSE_RESERVED_2_248_V << EFUSE_RESERVED_2_248_S)
+#define EFUSE_RESERVED_2_248_V  0x000000FFU
+#define EFUSE_RESERVED_2_248_S  24
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_ADC2_HI_DOUT_ATTEN0 : R; bitpos: [9:0]; default: 0;
+ *  HI_DOUT of ADC2 atten0
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN0    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_M  (EFUSE_ADC2_HI_DOUT_ATTEN0_V << EFUSE_ADC2_HI_DOUT_ATTEN0_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN0_S  0
+/** EFUSE_ADC2_HI_DOUT_ATTEN1 : R; bitpos: [19:10]; default: 0;
+ *  HI_DOUT of ADC2 atten1
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN1    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_M  (EFUSE_ADC2_HI_DOUT_ATTEN1_V << EFUSE_ADC2_HI_DOUT_ATTEN1_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN1_S  10
+/** EFUSE_ADC2_HI_DOUT_ATTEN2 : R; bitpos: [29:20]; default: 0;
+ *  HI_DOUT of ADC2 atten2
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN2    0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_M  (EFUSE_ADC2_HI_DOUT_ATTEN2_V << EFUSE_ADC2_HI_DOUT_ATTEN2_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_V  0x000003FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN2_S  20
+/** EFUSE_ADC2_HI_DOUT_ATTEN3 : R; bitpos: [31:30]; default: 0;
+ *  HI_DOUT of ADC2 atten3
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN3    0x00000003U
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_M  (EFUSE_ADC2_HI_DOUT_ATTEN3_V << EFUSE_ADC2_HI_DOUT_ATTEN3_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_V  0x00000003U
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_S  30
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_ADC2_HI_DOUT_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
+ *  HI_DOUT of ADC2 atten3
+ */
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1    0x000000FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_M  (EFUSE_ADC2_HI_DOUT_ATTEN3_1_V << EFUSE_ADC2_HI_DOUT_ATTEN3_1_S)
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_V  0x000000FFU
+#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_S  0
+/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
+ *  Gap between ADC1_ch0 and average initcode
+ */
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S  8
+/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
+ *  Gap between ADC1_ch1 and average initcode
+ */
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S  12
+/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
+ *  Gap between ADC1_ch2 and average initcode
+ */
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S  16
+/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
+ *  Gap between ADC1_ch3 and average initcode
+ */
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S  20
+/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
+ *  Gap between ADC1_ch4 and average initcode
+ */
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S  24
+/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
+ *  Gap between ADC1_ch5 and average initcode
+ */
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S  28
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF : R; bitpos: [3:0]; default: 0;
+ *  Gap between ADC1_ch6 and average initcode
+ */
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S  0
+/** EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF : R; bitpos: [7:4]; default: 0;
+ *  Gap between ADC1_ch7 and average initcode
+ */
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S  4
+/** EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
+ *  Gap between ADC2_ch0 and average initcode
+ */
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S  8
+/** EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
+ *  Gap between ADC2_ch1 and average initcode
+ */
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S  12
+/** EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
+ *  Gap between ADC2_ch2 and average initcode
+ */
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S  16
+/** EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
+ *  Gap between ADC2_ch3 and average initcode
+ */
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S  20
+/** EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
+ *  Gap between ADC2_ch4 and average initcode
+ */
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S  24
+/** EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
+ *  Gap between ADC2_ch5 and average initcode
+ */
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF    0x0000000FU
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_M  (EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S)
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V  0x0000000FU
+#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S  28
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMPERATURE_SENSOR    0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_M  (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
+#define EFUSE_TEMPERATURE_SENSOR_V  0x000001FFU
+#define EFUSE_TEMPERATURE_SENSOR_S  0
+/** EFUSE_RESERVED_10_105 : R; bitpos: [31:9]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_10_105    0x007FFFFFU
+#define EFUSE_RESERVED_10_105_M  (EFUSE_RESERVED_10_105_V << EFUSE_RESERVED_10_105_S)
+#define EFUSE_RESERVED_10_105_V  0x007FFFFFU
+#define EFUSE_RESERVED_10_105_S  9
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Indicates a programming error of RD_DIS.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR : RO; bitpos: [7]; default: 0;
+ *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
+ */
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR    (BIT(7))
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S)
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DEVICE_EXCHG_PINS_ERR_S  7
+/** EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+ */
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR    (BIT(8))
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_M  (EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V << EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S)
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG11_EXCHG_PINS_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  Indicates a programming error of DIS_USB_JTAG.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
+ *  Indicates a programming error of POWERGLITCH_EN.
+ */
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(10))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_ERR_S  10
+/** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR    (BIT(11))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of DIS_TWAI.
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  Indicates a programming error of JTAG_SEL_ENABLE.
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  Indicates a programming error of SOFT_DIS_JTAG.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DIS_PAD_JTAG.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DEVICE_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFH.
+ */
+#define EFUSE_USB_DEVICE_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_M  (EFUSE_USB_DEVICE_DREFH_ERR_V << EFUSE_USB_DEVICE_DREFH_ERR_S)
+#define EFUSE_USB_DEVICE_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFH_ERR_S  21
+/** EFUSE_USB_OTG11_DREFH_ERR : RO; bitpos: [24:23]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFH.
+ */
+#define EFUSE_USB_OTG11_DREFH_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_M  (EFUSE_USB_OTG11_DREFH_ERR_V << EFUSE_USB_OTG11_DREFH_ERR_S)
+#define EFUSE_USB_OTG11_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFH_ERR_S  23
+/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of USB_PHY_SEL.
+ */
+#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
+#define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
+#define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_ERR_S  25
+/** EFUSE_HUK_GEN_STATE_LOW_ERR : RO; bitpos: [31:26]; default: 0;
+ *  Indicates a programming error of HUK_GEN_STATE_LOW.
+ */
+#define EFUSE_HUK_GEN_STATE_LOW_ERR    0x0000003FU
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_M  (EFUSE_HUK_GEN_STATE_LOW_ERR_V << EFUSE_HUK_GEN_STATE_LOW_ERR_S)
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_V  0x0000003FU
+#define EFUSE_HUK_GEN_STATE_LOW_ERR_S  26
+
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_KM_HUK_GEN_STATE_HIGH_ERR : RO; bitpos: [2:0]; default: 0;
+ *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+ */
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR    0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_M  (EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V << EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S)
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_V  0x00000007U
+#define EFUSE_KM_HUK_GEN_STATE_HIGH_ERR_S  0
+/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [4:3]; default: 0;
+ *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000003U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  3
+/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [8:5]; default: 0;
+ *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000000FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  5
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [12:9]; default: 0;
+ *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000000FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  9
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [13]; default: 0;
+ *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(13))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  13
+/** EFUSE_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [14]; default: 0;
+ *  Indicates a programming error of XTS_KEY_LENGTH_256.
+ */
+#define EFUSE_XTS_KEY_LENGTH_256_ERR    (BIT(14))
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_XTS_KEY_LENGTH_256_ERR_V << EFUSE_XTS_KEY_LENGTH_256_ERR_S)
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
+#define EFUSE_XTS_KEY_LENGTH_256_ERR_S  14
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of WDT_DELAY_SEL.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_0.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_1.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_2.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_3.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_4.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Indicates a programming error of KEY_PURPOSE_5.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  Indicates a programming error of SEC_DPA_LEVEL.
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  16
+/** EFUSE_ECDSA_ENABLE_SOFT_K_ERR : RO; bitpos: [18]; default: 0;
+ *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
+ */
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR    (BIT(18))
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_M  (EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V << EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S)
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_V  0x00000001U
+#define EFUSE_ECDSA_ENABLE_SOFT_K_ERR_S  18
+/** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of CRYPT_DPA_ENABLE.
+ */
+#define EFUSE_CRYPT_DPA_ENABLE_ERR    (BIT(19))
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_M  (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S)
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_V  0x00000001U
+#define EFUSE_CRYPT_DPA_ENABLE_ERR_S  19
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_EN.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [23]; default: 0;
+ *  Indicates a programming error of FLASH_TYPE.
+ */
+#define EFUSE_FLASH_TYPE_ERR    (BIT(23))
+#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
+#define EFUSE_FLASH_TYPE_ERR_S  23
+/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [25:24]; default: 0;
+ *  Indicates a programming error of FLASH_PAGE_SIZE.
+ */
+#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S  24
+/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of FLASH_ECC_EN.
+ */
+#define EFUSE_FLASH_ECC_EN_ERR    (BIT(26))
+#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
+#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_ERR_S  26
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [27]; default: 0;
+ *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(27))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  27
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  Indicates a programming error of FLASH_TPUW.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  Indicates a programming error of DIS_DIRECT_BOOT.
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [2]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  2
+/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [3]; default: 0;
+ *  TBD
+ */
+#define EFUSE_LOCK_KM_KEY_ERR    (BIT(3))
+#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
+#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_ERR_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of UART_PRINT_CONTROL.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0;
+ *  Indicates a programming error of FORCE_SEND_RESUME.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(8))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  8
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0;
+ *  Indicates a programming error of SECURE VERSION.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  9
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0;
+ *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(25))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  25
+/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [26]; default: 0;
+ *  Indicates a programming error of HYS_EN_PAD.
+ */
+#define EFUSE_HYS_EN_PAD_ERR    (BIT(26))
+#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
+#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_ERR_S  26
+/** EFUSE_DCDC_VSET_ERR : RO; bitpos: [31:27]; default: 0;
+ *  Indicates a programming error of DCDC_VSET.
+ */
+#define EFUSE_DCDC_VSET_ERR    0x0000001FU
+#define EFUSE_DCDC_VSET_ERR_M  (EFUSE_DCDC_VSET_ERR_V << EFUSE_DCDC_VSET_ERR_S)
+#define EFUSE_DCDC_VSET_ERR_V  0x0000001FU
+#define EFUSE_DCDC_VSET_ERR_S  27
+
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c)
+/** EFUSE_PXA0_TIEH_SEL_0_ERR : RO; bitpos: [1:0]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+ */
+#define EFUSE_PXA0_TIEH_SEL_0_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_M  (EFUSE_PXA0_TIEH_SEL_0_ERR_V << EFUSE_PXA0_TIEH_SEL_0_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_0_ERR_S  0
+/** EFUSE_PXA0_TIEH_SEL_1_ERR : RO; bitpos: [3:2]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+ */
+#define EFUSE_PXA0_TIEH_SEL_1_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_M  (EFUSE_PXA0_TIEH_SEL_1_ERR_V << EFUSE_PXA0_TIEH_SEL_1_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_1_ERR_S  2
+/** EFUSE_PXA0_TIEH_SEL_2_ERR : RO; bitpos: [5:4]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+ */
+#define EFUSE_PXA0_TIEH_SEL_2_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_M  (EFUSE_PXA0_TIEH_SEL_2_ERR_V << EFUSE_PXA0_TIEH_SEL_2_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_2_ERR_S  4
+/** EFUSE_PXA0_TIEH_SEL_3_ERR : RO; bitpos: [7:6]; default: 0;
+ *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+ */
+#define EFUSE_PXA0_TIEH_SEL_3_ERR    0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_M  (EFUSE_PXA0_TIEH_SEL_3_ERR_V << EFUSE_PXA0_TIEH_SEL_3_ERR_S)
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_V  0x00000003U
+#define EFUSE_PXA0_TIEH_SEL_3_ERR_S  6
+/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [11:8]; default: 0;
+ *  TBD.
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000000FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  8
+/** EFUSE_USB_DEVICE_DREFL_ERR : RO; bitpos: [13:12]; default: 0;
+ *  Indicates a programming error of USB_DEVICE_DREFL.
+ */
+#define EFUSE_USB_DEVICE_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_ERR_M  (EFUSE_USB_DEVICE_DREFL_ERR_V << EFUSE_USB_DEVICE_DREFL_ERR_S)
+#define EFUSE_USB_DEVICE_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DEVICE_DREFL_ERR_S  12
+/** EFUSE_USB_OTG11_DREFL_ERR : RO; bitpos: [15:14]; default: 0;
+ *  Indicates a programming error of USB_OTG11_DREFL.
+ */
+#define EFUSE_USB_OTG11_DREFL_ERR    0x00000003U
+#define EFUSE_USB_OTG11_DREFL_ERR_M  (EFUSE_USB_OTG11_DREFL_ERR_V << EFUSE_USB_OTG11_DREFL_ERR_S)
+#define EFUSE_USB_OTG11_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_OTG11_DREFL_ERR_S  14
+/** EFUSE_HP_PWR_SRC_SEL_ERR : RO; bitpos: [18]; default: 0;
+ *  Indicates a programming error of HP_PWR_SRC_SEL.
+ */
+#define EFUSE_HP_PWR_SRC_SEL_ERR    (BIT(18))
+#define EFUSE_HP_PWR_SRC_SEL_ERR_M  (EFUSE_HP_PWR_SRC_SEL_ERR_V << EFUSE_HP_PWR_SRC_SEL_ERR_S)
+#define EFUSE_HP_PWR_SRC_SEL_ERR_V  0x00000001U
+#define EFUSE_HP_PWR_SRC_SEL_ERR_S  18
+/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [19]; default: 0;
+ *  Indicates a programming error of DCDC_VSET_EN.
+ */
+#define EFUSE_DCDC_VSET_EN_ERR    (BIT(19))
+#define EFUSE_DCDC_VSET_EN_ERR_M  (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S)
+#define EFUSE_DCDC_VSET_EN_ERR_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_ERR_S  19
+/** EFUSE_DIS_WDT_ERR : RO; bitpos: [20]; default: 0;
+ *  Indicates a programming error of DIS_WDT.
+ */
+#define EFUSE_DIS_WDT_ERR    (BIT(20))
+#define EFUSE_DIS_WDT_ERR_M  (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S)
+#define EFUSE_DIS_WDT_ERR_V  0x00000001U
+#define EFUSE_DIS_WDT_ERR_S  20
+/** EFUSE_DIS_SWD_ERR : RO; bitpos: [21]; default: 0;
+ *  Indicates a programming error of DIS_SWD.
+ */
+#define EFUSE_DIS_SWD_ERR    (BIT(21))
+#define EFUSE_DIS_SWD_ERR_M  (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S)
+#define EFUSE_DIS_SWD_ERR_V  0x00000001U
+#define EFUSE_DIS_SWD_ERR_S  21
+
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SYS_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SYS_ERR_NUM_M  (EFUSE_MAC_SYS_ERR_NUM_V << EFUSE_MAC_SYS_ERR_NUM_S)
+#define EFUSE_MAC_SYS_ERR_NUM_V  0x00000007U
+#define EFUSE_MAC_SYS_ERR_NUM_S  0
+/** EFUSE_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_MAC_SYS_FAIL_M  (EFUSE_MAC_SYS_FAIL_V << EFUSE_MAC_SYS_FAIL_S)
+#define EFUSE_MAC_SYS_FAIL_V  0x00000001U
+#define EFUSE_MAC_SYS_FAIL_S  3
+/** EFUSE_SYS_PART1_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART1_ERR_NUM_M  (EFUSE_SYS_PART1_ERR_NUM_V << EFUSE_SYS_PART1_ERR_NUM_S)
+#define EFUSE_SYS_PART1_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_ERR_NUM_S  4
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+ *  key0 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+ *  key1 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+ *  key2 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+ *  key3 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+ *  key4 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  31
+
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+ *  key5 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART2_FAIL_S  7
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to force enable eFuse register configuration clock signal.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+/** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0;
+ *  Configures which block to use for ECDSA key output.
+ */
+#define EFUSE_CFG_ECDSA_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_M  (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S)
+#define EFUSE_CFG_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_BLK_S  16
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Indicates the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+/** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Indicates which block is used for ECDSA key output.
+ */
+#define EFUSE_CUR_ECDSA_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_M  (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S)
+#define EFUSE_CUR_ECDSA_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_BLK_S  20
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15;
+ *  Configures the waiting time of reading eFuse memory.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160;
+ *  Configures the active programming time.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to bypass reed solomon correction step.
+ */
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures block number of programming twice operation.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Set this bit to update multi-bit register signals.
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 36720720;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+/** EFUSE_APB2OTP_WR_DIS_REG register
+ *  eFuse apb2otp block0 data register1.
+ */
+#define EFUSE_APB2OTP_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x800)
+/** EFUSE_APB2OTP_BLOCK0_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 write disable data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_M  (EFUSE_APB2OTP_BLOCK0_WR_DIS_V << EFUSE_APB2OTP_BLOCK0_WR_DIS_S)
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_WR_DIS_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG register
+ *  eFuse apb2otp block0 data register2.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W1_REG (DR_REG_EFUSE_BASE + 0x804)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG register
+ *  eFuse apb2otp block0 data register3.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W2_REG (DR_REG_EFUSE_BASE + 0x808)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG register
+ *  eFuse apb2otp block0 data register4.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W3_REG (DR_REG_EFUSE_BASE + 0x80c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG register
+ *  eFuse apb2otp block0 data register5.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W4_REG (DR_REG_EFUSE_BASE + 0x810)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG register
+ *  eFuse apb2otp block0 data register6.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP1_W5_REG (DR_REG_EFUSE_BASE + 0x814)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup1 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG register
+ *  eFuse apb2otp block0 data register7.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W1_REG (DR_REG_EFUSE_BASE + 0x818)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG register
+ *  eFuse apb2otp block0 data register8.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W2_REG (DR_REG_EFUSE_BASE + 0x81c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG register
+ *  eFuse apb2otp block0 data register9.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W3_REG (DR_REG_EFUSE_BASE + 0x820)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG register
+ *  eFuse apb2otp block0 data register10.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W4_REG (DR_REG_EFUSE_BASE + 0x824)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG register
+ *  eFuse apb2otp block0 data register11.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP2_W5_REG (DR_REG_EFUSE_BASE + 0x828)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG register
+ *  eFuse apb2otp block0 data register12.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W1_REG (DR_REG_EFUSE_BASE + 0x82c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG register
+ *  eFuse apb2otp block0 data register13.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W2_REG (DR_REG_EFUSE_BASE + 0x830)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG register
+ *  eFuse apb2otp block0 data register14.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W3_REG (DR_REG_EFUSE_BASE + 0x834)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG register
+ *  eFuse apb2otp block0 data register15.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W4_REG (DR_REG_EFUSE_BASE + 0x838)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG register
+ *  eFuse apb2otp block0 data register16.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP3_W5_REG (DR_REG_EFUSE_BASE + 0x83c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG register
+ *  eFuse apb2otp block0 data register17.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W1_REG (DR_REG_EFUSE_BASE + 0x840)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG register
+ *  eFuse apb2otp block0 data register18.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W2_REG (DR_REG_EFUSE_BASE + 0x844)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG register
+ *  eFuse apb2otp block0 data register19.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W3_REG (DR_REG_EFUSE_BASE + 0x848)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG register
+ *  eFuse apb2otp block0 data register20.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W4_REG (DR_REG_EFUSE_BASE + 0x84c)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG register
+ *  eFuse apb2otp block0 data register21.
+ */
+#define EFUSE_APB2OTP_BLK0_BACKUP4_W5_REG (DR_REG_EFUSE_BASE + 0x850)
+/** EFUSE_APB2OTP_BLOCK0_BACKUP4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block0 backup4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_M  (EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V << EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S)
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK0_BACKUP4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W1_REG register
+ *  eFuse apb2otp block1 data register1.
+ */
+#define EFUSE_APB2OTP_BLK1_W1_REG (DR_REG_EFUSE_BASE + 0x854)
+/** EFUSE_APB2OTP_BLOCK1_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_M  (EFUSE_APB2OTP_BLOCK1_W1_V << EFUSE_APB2OTP_BLOCK1_W1_S)
+#define EFUSE_APB2OTP_BLOCK1_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W1_S  0
+
+/** EFUSE_APB2OTP_BLK1_W2_REG register
+ *  eFuse apb2otp block1 data register2.
+ */
+#define EFUSE_APB2OTP_BLK1_W2_REG (DR_REG_EFUSE_BASE + 0x858)
+/** EFUSE_APB2OTP_BLOCK1_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_M  (EFUSE_APB2OTP_BLOCK1_W2_V << EFUSE_APB2OTP_BLOCK1_W2_S)
+#define EFUSE_APB2OTP_BLOCK1_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W2_S  0
+
+/** EFUSE_APB2OTP_BLK1_W3_REG register
+ *  eFuse apb2otp block1 data register3.
+ */
+#define EFUSE_APB2OTP_BLK1_W3_REG (DR_REG_EFUSE_BASE + 0x85c)
+/** EFUSE_APB2OTP_BLOCK1_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_M  (EFUSE_APB2OTP_BLOCK1_W3_V << EFUSE_APB2OTP_BLOCK1_W3_S)
+#define EFUSE_APB2OTP_BLOCK1_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W3_S  0
+
+/** EFUSE_APB2OTP_BLK1_W4_REG register
+ *  eFuse apb2otp block1 data register4.
+ */
+#define EFUSE_APB2OTP_BLK1_W4_REG (DR_REG_EFUSE_BASE + 0x860)
+/** EFUSE_APB2OTP_BLOCK1_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_M  (EFUSE_APB2OTP_BLOCK1_W4_V << EFUSE_APB2OTP_BLOCK1_W4_S)
+#define EFUSE_APB2OTP_BLOCK1_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W4_S  0
+
+/** EFUSE_APB2OTP_BLK1_W5_REG register
+ *  eFuse apb2otp block1 data register5.
+ */
+#define EFUSE_APB2OTP_BLK1_W5_REG (DR_REG_EFUSE_BASE + 0x864)
+/** EFUSE_APB2OTP_BLOCK1_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_M  (EFUSE_APB2OTP_BLOCK1_W5_V << EFUSE_APB2OTP_BLOCK1_W5_S)
+#define EFUSE_APB2OTP_BLOCK1_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W5_S  0
+
+/** EFUSE_APB2OTP_BLK1_W6_REG register
+ *  eFuse apb2otp block1 data register6.
+ */
+#define EFUSE_APB2OTP_BLK1_W6_REG (DR_REG_EFUSE_BASE + 0x868)
+/** EFUSE_APB2OTP_BLOCK1_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_M  (EFUSE_APB2OTP_BLOCK1_W6_V << EFUSE_APB2OTP_BLOCK1_W6_S)
+#define EFUSE_APB2OTP_BLOCK1_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W6_S  0
+
+/** EFUSE_APB2OTP_BLK1_W7_REG register
+ *  eFuse apb2otp block1 data register7.
+ */
+#define EFUSE_APB2OTP_BLK1_W7_REG (DR_REG_EFUSE_BASE + 0x86c)
+/** EFUSE_APB2OTP_BLOCK1_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_M  (EFUSE_APB2OTP_BLOCK1_W7_V << EFUSE_APB2OTP_BLOCK1_W7_S)
+#define EFUSE_APB2OTP_BLOCK1_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W7_S  0
+
+/** EFUSE_APB2OTP_BLK1_W8_REG register
+ *  eFuse apb2otp block1 data register8.
+ */
+#define EFUSE_APB2OTP_BLK1_W8_REG (DR_REG_EFUSE_BASE + 0x870)
+/** EFUSE_APB2OTP_BLOCK1_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_M  (EFUSE_APB2OTP_BLOCK1_W8_V << EFUSE_APB2OTP_BLOCK1_W8_S)
+#define EFUSE_APB2OTP_BLOCK1_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W8_S  0
+
+/** EFUSE_APB2OTP_BLK1_W9_REG register
+ *  eFuse apb2otp block1 data register9.
+ */
+#define EFUSE_APB2OTP_BLK1_W9_REG (DR_REG_EFUSE_BASE + 0x874)
+/** EFUSE_APB2OTP_BLOCK1_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block1  word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK1_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_M  (EFUSE_APB2OTP_BLOCK1_W9_V << EFUSE_APB2OTP_BLOCK1_W9_S)
+#define EFUSE_APB2OTP_BLOCK1_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK1_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W1_REG register
+ *  eFuse apb2otp block2 data register1.
+ */
+#define EFUSE_APB2OTP_BLK2_W1_REG (DR_REG_EFUSE_BASE + 0x878)
+/** EFUSE_APB2OTP_BLOCK2_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_M  (EFUSE_APB2OTP_BLOCK2_W1_V << EFUSE_APB2OTP_BLOCK2_W1_S)
+#define EFUSE_APB2OTP_BLOCK2_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W1_S  0
+
+/** EFUSE_APB2OTP_BLK2_W2_REG register
+ *  eFuse apb2otp block2 data register2.
+ */
+#define EFUSE_APB2OTP_BLK2_W2_REG (DR_REG_EFUSE_BASE + 0x87c)
+/** EFUSE_APB2OTP_BLOCK2_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_M  (EFUSE_APB2OTP_BLOCK2_W2_V << EFUSE_APB2OTP_BLOCK2_W2_S)
+#define EFUSE_APB2OTP_BLOCK2_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W2_S  0
+
+/** EFUSE_APB2OTP_BLK2_W3_REG register
+ *  eFuse apb2otp block2 data register3.
+ */
+#define EFUSE_APB2OTP_BLK2_W3_REG (DR_REG_EFUSE_BASE + 0x880)
+/** EFUSE_APB2OTP_BLOCK2_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_M  (EFUSE_APB2OTP_BLOCK2_W3_V << EFUSE_APB2OTP_BLOCK2_W3_S)
+#define EFUSE_APB2OTP_BLOCK2_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W3_S  0
+
+/** EFUSE_APB2OTP_BLK2_W4_REG register
+ *  eFuse apb2otp block2 data register4.
+ */
+#define EFUSE_APB2OTP_BLK2_W4_REG (DR_REG_EFUSE_BASE + 0x884)
+/** EFUSE_APB2OTP_BLOCK2_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_M  (EFUSE_APB2OTP_BLOCK2_W4_V << EFUSE_APB2OTP_BLOCK2_W4_S)
+#define EFUSE_APB2OTP_BLOCK2_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W4_S  0
+
+/** EFUSE_APB2OTP_BLK2_W5_REG register
+ *  eFuse apb2otp block2 data register5.
+ */
+#define EFUSE_APB2OTP_BLK2_W5_REG (DR_REG_EFUSE_BASE + 0x888)
+/** EFUSE_APB2OTP_BLOCK2_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_M  (EFUSE_APB2OTP_BLOCK2_W5_V << EFUSE_APB2OTP_BLOCK2_W5_S)
+#define EFUSE_APB2OTP_BLOCK2_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W5_S  0
+
+/** EFUSE_APB2OTP_BLK2_W6_REG register
+ *  eFuse apb2otp block2 data register6.
+ */
+#define EFUSE_APB2OTP_BLK2_W6_REG (DR_REG_EFUSE_BASE + 0x88c)
+/** EFUSE_APB2OTP_BLOCK2_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_M  (EFUSE_APB2OTP_BLOCK2_W6_V << EFUSE_APB2OTP_BLOCK2_W6_S)
+#define EFUSE_APB2OTP_BLOCK2_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W6_S  0
+
+/** EFUSE_APB2OTP_BLK2_W7_REG register
+ *  eFuse apb2otp block2 data register7.
+ */
+#define EFUSE_APB2OTP_BLK2_W7_REG (DR_REG_EFUSE_BASE + 0x890)
+/** EFUSE_APB2OTP_BLOCK2_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_M  (EFUSE_APB2OTP_BLOCK2_W7_V << EFUSE_APB2OTP_BLOCK2_W7_S)
+#define EFUSE_APB2OTP_BLOCK2_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W7_S  0
+
+/** EFUSE_APB2OTP_BLK2_W8_REG register
+ *  eFuse apb2otp block2 data register8.
+ */
+#define EFUSE_APB2OTP_BLK2_W8_REG (DR_REG_EFUSE_BASE + 0x894)
+/** EFUSE_APB2OTP_BLOCK2_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_M  (EFUSE_APB2OTP_BLOCK2_W8_V << EFUSE_APB2OTP_BLOCK2_W8_S)
+#define EFUSE_APB2OTP_BLOCK2_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W8_S  0
+
+/** EFUSE_APB2OTP_BLK2_W9_REG register
+ *  eFuse apb2otp block2 data register9.
+ */
+#define EFUSE_APB2OTP_BLK2_W9_REG (DR_REG_EFUSE_BASE + 0x898)
+/** EFUSE_APB2OTP_BLOCK2_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_M  (EFUSE_APB2OTP_BLOCK2_W9_V << EFUSE_APB2OTP_BLOCK2_W9_S)
+#define EFUSE_APB2OTP_BLOCK2_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W9_S  0
+
+/** EFUSE_APB2OTP_BLK2_W10_REG register
+ *  eFuse apb2otp block2 data register10.
+ */
+#define EFUSE_APB2OTP_BLK2_W10_REG (DR_REG_EFUSE_BASE + 0x89c)
+/** EFUSE_APB2OTP_BLOCK2_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_M  (EFUSE_APB2OTP_BLOCK2_W10_V << EFUSE_APB2OTP_BLOCK2_W10_S)
+#define EFUSE_APB2OTP_BLOCK2_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W10_S  0
+
+/** EFUSE_APB2OTP_BLK2_W11_REG register
+ *  eFuse apb2otp block2 data register11.
+ */
+#define EFUSE_APB2OTP_BLK2_W11_REG (DR_REG_EFUSE_BASE + 0x8a0)
+/** EFUSE_APB2OTP_BLOCK2_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block2 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK2_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_M  (EFUSE_APB2OTP_BLOCK2_W11_V << EFUSE_APB2OTP_BLOCK2_W11_S)
+#define EFUSE_APB2OTP_BLOCK2_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK2_W11_S  0
+
+/** EFUSE_APB2OTP_BLK3_W1_REG register
+ *  eFuse apb2otp block3 data register1.
+ */
+#define EFUSE_APB2OTP_BLK3_W1_REG (DR_REG_EFUSE_BASE + 0x8a4)
+/** EFUSE_APB2OTP_BLOCK3_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_M  (EFUSE_APB2OTP_BLOCK3_W1_V << EFUSE_APB2OTP_BLOCK3_W1_S)
+#define EFUSE_APB2OTP_BLOCK3_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W1_S  0
+
+/** EFUSE_APB2OTP_BLK3_W2_REG register
+ *  eFuse apb2otp block3 data register2.
+ */
+#define EFUSE_APB2OTP_BLK3_W2_REG (DR_REG_EFUSE_BASE + 0x8a8)
+/** EFUSE_APB2OTP_BLOCK3_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_M  (EFUSE_APB2OTP_BLOCK3_W2_V << EFUSE_APB2OTP_BLOCK3_W2_S)
+#define EFUSE_APB2OTP_BLOCK3_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W2_S  0
+
+/** EFUSE_APB2OTP_BLK3_W3_REG register
+ *  eFuse apb2otp block3 data register3.
+ */
+#define EFUSE_APB2OTP_BLK3_W3_REG (DR_REG_EFUSE_BASE + 0x8ac)
+/** EFUSE_APB2OTP_BLOCK3_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_M  (EFUSE_APB2OTP_BLOCK3_W3_V << EFUSE_APB2OTP_BLOCK3_W3_S)
+#define EFUSE_APB2OTP_BLOCK3_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W3_S  0
+
+/** EFUSE_APB2OTP_BLK3_W4_REG register
+ *  eFuse apb2otp block3 data register4.
+ */
+#define EFUSE_APB2OTP_BLK3_W4_REG (DR_REG_EFUSE_BASE + 0x8b0)
+/** EFUSE_APB2OTP_BLOCK3_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_M  (EFUSE_APB2OTP_BLOCK3_W4_V << EFUSE_APB2OTP_BLOCK3_W4_S)
+#define EFUSE_APB2OTP_BLOCK3_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W4_S  0
+
+/** EFUSE_APB2OTP_BLK3_W5_REG register
+ *  eFuse apb2otp block3 data register5.
+ */
+#define EFUSE_APB2OTP_BLK3_W5_REG (DR_REG_EFUSE_BASE + 0x8b4)
+/** EFUSE_APB2OTP_BLOCK3_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_M  (EFUSE_APB2OTP_BLOCK3_W5_V << EFUSE_APB2OTP_BLOCK3_W5_S)
+#define EFUSE_APB2OTP_BLOCK3_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W5_S  0
+
+/** EFUSE_APB2OTP_BLK3_W6_REG register
+ *  eFuse apb2otp block3 data register6.
+ */
+#define EFUSE_APB2OTP_BLK3_W6_REG (DR_REG_EFUSE_BASE + 0x8b8)
+/** EFUSE_APB2OTP_BLOCK3_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_M  (EFUSE_APB2OTP_BLOCK3_W6_V << EFUSE_APB2OTP_BLOCK3_W6_S)
+#define EFUSE_APB2OTP_BLOCK3_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W6_S  0
+
+/** EFUSE_APB2OTP_BLK3_W7_REG register
+ *  eFuse apb2otp block3 data register7.
+ */
+#define EFUSE_APB2OTP_BLK3_W7_REG (DR_REG_EFUSE_BASE + 0x8bc)
+/** EFUSE_APB2OTP_BLOCK3_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_M  (EFUSE_APB2OTP_BLOCK3_W7_V << EFUSE_APB2OTP_BLOCK3_W7_S)
+#define EFUSE_APB2OTP_BLOCK3_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W7_S  0
+
+/** EFUSE_APB2OTP_BLK3_W8_REG register
+ *  eFuse apb2otp block3 data register8.
+ */
+#define EFUSE_APB2OTP_BLK3_W8_REG (DR_REG_EFUSE_BASE + 0x8c0)
+/** EFUSE_APB2OTP_BLOCK3_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_M  (EFUSE_APB2OTP_BLOCK3_W8_V << EFUSE_APB2OTP_BLOCK3_W8_S)
+#define EFUSE_APB2OTP_BLOCK3_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W8_S  0
+
+/** EFUSE_APB2OTP_BLK3_W9_REG register
+ *  eFuse apb2otp block3 data register9.
+ */
+#define EFUSE_APB2OTP_BLK3_W9_REG (DR_REG_EFUSE_BASE + 0x8c4)
+/** EFUSE_APB2OTP_BLOCK3_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_M  (EFUSE_APB2OTP_BLOCK3_W9_V << EFUSE_APB2OTP_BLOCK3_W9_S)
+#define EFUSE_APB2OTP_BLOCK3_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W9_S  0
+
+/** EFUSE_APB2OTP_BLK3_W10_REG register
+ *  eFuse apb2otp block3 data register10.
+ */
+#define EFUSE_APB2OTP_BLK3_W10_REG (DR_REG_EFUSE_BASE + 0x8c8)
+/** EFUSE_APB2OTP_BLOCK3_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_M  (EFUSE_APB2OTP_BLOCK3_W10_V << EFUSE_APB2OTP_BLOCK3_W10_S)
+#define EFUSE_APB2OTP_BLOCK3_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W10_S  0
+
+/** EFUSE_APB2OTP_BLK3_W11_REG register
+ *  eFuse apb2otp block3 data register11.
+ */
+#define EFUSE_APB2OTP_BLK3_W11_REG (DR_REG_EFUSE_BASE + 0x8cc)
+/** EFUSE_APB2OTP_BLOCK3_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block3 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK3_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_M  (EFUSE_APB2OTP_BLOCK3_W11_V << EFUSE_APB2OTP_BLOCK3_W11_S)
+#define EFUSE_APB2OTP_BLOCK3_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK3_W11_S  0
+
+/** EFUSE_APB2OTP_BLK4_W1_REG register
+ *  eFuse apb2otp block4 data register1.
+ */
+#define EFUSE_APB2OTP_BLK4_W1_REG (DR_REG_EFUSE_BASE + 0x8d0)
+/** EFUSE_APB2OTP_BLOCK4_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_M  (EFUSE_APB2OTP_BLOCK4_W1_V << EFUSE_APB2OTP_BLOCK4_W1_S)
+#define EFUSE_APB2OTP_BLOCK4_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W1_S  0
+
+/** EFUSE_APB2OTP_BLK4_W2_REG register
+ *  eFuse apb2otp block4 data register2.
+ */
+#define EFUSE_APB2OTP_BLK4_W2_REG (DR_REG_EFUSE_BASE + 0x8d4)
+/** EFUSE_APB2OTP_BLOCK4_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_M  (EFUSE_APB2OTP_BLOCK4_W2_V << EFUSE_APB2OTP_BLOCK4_W2_S)
+#define EFUSE_APB2OTP_BLOCK4_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W2_S  0
+
+/** EFUSE_APB2OTP_BLK4_W3_REG register
+ *  eFuse apb2otp block4 data register3.
+ */
+#define EFUSE_APB2OTP_BLK4_W3_REG (DR_REG_EFUSE_BASE + 0x8d8)
+/** EFUSE_APB2OTP_BLOCK4_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_M  (EFUSE_APB2OTP_BLOCK4_W3_V << EFUSE_APB2OTP_BLOCK4_W3_S)
+#define EFUSE_APB2OTP_BLOCK4_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W3_S  0
+
+/** EFUSE_APB2OTP_BLK4_W4_REG register
+ *  eFuse apb2otp block4 data register4.
+ */
+#define EFUSE_APB2OTP_BLK4_W4_REG (DR_REG_EFUSE_BASE + 0x8dc)
+/** EFUSE_APB2OTP_BLOCK4_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_M  (EFUSE_APB2OTP_BLOCK4_W4_V << EFUSE_APB2OTP_BLOCK4_W4_S)
+#define EFUSE_APB2OTP_BLOCK4_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W4_S  0
+
+/** EFUSE_APB2OTP_BLK4_W5_REG register
+ *  eFuse apb2otp block4 data register5.
+ */
+#define EFUSE_APB2OTP_BLK4_W5_REG (DR_REG_EFUSE_BASE + 0x8e0)
+/** EFUSE_APB2OTP_BLOCK4_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_M  (EFUSE_APB2OTP_BLOCK4_W5_V << EFUSE_APB2OTP_BLOCK4_W5_S)
+#define EFUSE_APB2OTP_BLOCK4_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W5_S  0
+
+/** EFUSE_APB2OTP_BLK4_W6_REG register
+ *  eFuse apb2otp block4 data register6.
+ */
+#define EFUSE_APB2OTP_BLK4_W6_REG (DR_REG_EFUSE_BASE + 0x8e4)
+/** EFUSE_APB2OTP_BLOCK4_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_M  (EFUSE_APB2OTP_BLOCK4_W6_V << EFUSE_APB2OTP_BLOCK4_W6_S)
+#define EFUSE_APB2OTP_BLOCK4_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W6_S  0
+
+/** EFUSE_APB2OTP_BLK4_W7_REG register
+ *  eFuse apb2otp block4 data register7.
+ */
+#define EFUSE_APB2OTP_BLK4_W7_REG (DR_REG_EFUSE_BASE + 0x8e8)
+/** EFUSE_APB2OTP_BLOCK4_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_M  (EFUSE_APB2OTP_BLOCK4_W7_V << EFUSE_APB2OTP_BLOCK4_W7_S)
+#define EFUSE_APB2OTP_BLOCK4_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W7_S  0
+
+/** EFUSE_APB2OTP_BLK4_W8_REG register
+ *  eFuse apb2otp block4 data register8.
+ */
+#define EFUSE_APB2OTP_BLK4_W8_REG (DR_REG_EFUSE_BASE + 0x8ec)
+/** EFUSE_APB2OTP_BLOCK4_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_M  (EFUSE_APB2OTP_BLOCK4_W8_V << EFUSE_APB2OTP_BLOCK4_W8_S)
+#define EFUSE_APB2OTP_BLOCK4_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W8_S  0
+
+/** EFUSE_APB2OTP_BLK4_W9_REG register
+ *  eFuse apb2otp block4 data register9.
+ */
+#define EFUSE_APB2OTP_BLK4_W9_REG (DR_REG_EFUSE_BASE + 0x8f0)
+/** EFUSE_APB2OTP_BLOCK4_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_M  (EFUSE_APB2OTP_BLOCK4_W9_V << EFUSE_APB2OTP_BLOCK4_W9_S)
+#define EFUSE_APB2OTP_BLOCK4_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W9_S  0
+
+/** EFUSE_APB2OTP_BLK4_W10_REG register
+ *  eFuse apb2otp block4 data registe10.
+ */
+#define EFUSE_APB2OTP_BLK4_W10_REG (DR_REG_EFUSE_BASE + 0x8f4)
+/** EFUSE_APB2OTP_BLOCK4_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_M  (EFUSE_APB2OTP_BLOCK4_W10_V << EFUSE_APB2OTP_BLOCK4_W10_S)
+#define EFUSE_APB2OTP_BLOCK4_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W10_S  0
+
+/** EFUSE_APB2OTP_BLK4_W11_REG register
+ *  eFuse apb2otp block4 data register11.
+ */
+#define EFUSE_APB2OTP_BLK4_W11_REG (DR_REG_EFUSE_BASE + 0x8f8)
+/** EFUSE_APB2OTP_BLOCK4_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block4 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK4_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_M  (EFUSE_APB2OTP_BLOCK4_W11_V << EFUSE_APB2OTP_BLOCK4_W11_S)
+#define EFUSE_APB2OTP_BLOCK4_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK4_W11_S  0
+
+/** EFUSE_APB2OTP_BLK5_W1_REG register
+ *  eFuse apb2otp block5 data register1.
+ */
+#define EFUSE_APB2OTP_BLK5_W1_REG (DR_REG_EFUSE_BASE + 0x8fc)
+/** EFUSE_APB2OTP_BLOCK5_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_M  (EFUSE_APB2OTP_BLOCK5_W1_V << EFUSE_APB2OTP_BLOCK5_W1_S)
+#define EFUSE_APB2OTP_BLOCK5_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W1_S  0
+
+/** EFUSE_APB2OTP_BLK5_W2_REG register
+ *  eFuse apb2otp block5 data register2.
+ */
+#define EFUSE_APB2OTP_BLK5_W2_REG (DR_REG_EFUSE_BASE + 0x900)
+/** EFUSE_APB2OTP_BLOCK5_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_M  (EFUSE_APB2OTP_BLOCK5_W2_V << EFUSE_APB2OTP_BLOCK5_W2_S)
+#define EFUSE_APB2OTP_BLOCK5_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W2_S  0
+
+/** EFUSE_APB2OTP_BLK5_W3_REG register
+ *  eFuse apb2otp block5 data register3.
+ */
+#define EFUSE_APB2OTP_BLK5_W3_REG (DR_REG_EFUSE_BASE + 0x904)
+/** EFUSE_APB2OTP_BLOCK5_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_M  (EFUSE_APB2OTP_BLOCK5_W3_V << EFUSE_APB2OTP_BLOCK5_W3_S)
+#define EFUSE_APB2OTP_BLOCK5_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W3_S  0
+
+/** EFUSE_APB2OTP_BLK5_W4_REG register
+ *  eFuse apb2otp block5 data register4.
+ */
+#define EFUSE_APB2OTP_BLK5_W4_REG (DR_REG_EFUSE_BASE + 0x908)
+/** EFUSE_APB2OTP_BLOCK5_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_M  (EFUSE_APB2OTP_BLOCK5_W4_V << EFUSE_APB2OTP_BLOCK5_W4_S)
+#define EFUSE_APB2OTP_BLOCK5_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W4_S  0
+
+/** EFUSE_APB2OTP_BLK5_W5_REG register
+ *  eFuse apb2otp block5 data register5.
+ */
+#define EFUSE_APB2OTP_BLK5_W5_REG (DR_REG_EFUSE_BASE + 0x90c)
+/** EFUSE_APB2OTP_BLOCK5_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_M  (EFUSE_APB2OTP_BLOCK5_W5_V << EFUSE_APB2OTP_BLOCK5_W5_S)
+#define EFUSE_APB2OTP_BLOCK5_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W5_S  0
+
+/** EFUSE_APB2OTP_BLK5_W6_REG register
+ *  eFuse apb2otp block5 data register6.
+ */
+#define EFUSE_APB2OTP_BLK5_W6_REG (DR_REG_EFUSE_BASE + 0x910)
+/** EFUSE_APB2OTP_BLOCK5_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_M  (EFUSE_APB2OTP_BLOCK5_W6_V << EFUSE_APB2OTP_BLOCK5_W6_S)
+#define EFUSE_APB2OTP_BLOCK5_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W6_S  0
+
+/** EFUSE_APB2OTP_BLK5_W7_REG register
+ *  eFuse apb2otp block5 data register7.
+ */
+#define EFUSE_APB2OTP_BLK5_W7_REG (DR_REG_EFUSE_BASE + 0x914)
+/** EFUSE_APB2OTP_BLOCK5_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_M  (EFUSE_APB2OTP_BLOCK5_W7_V << EFUSE_APB2OTP_BLOCK5_W7_S)
+#define EFUSE_APB2OTP_BLOCK5_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W7_S  0
+
+/** EFUSE_APB2OTP_BLK5_W8_REG register
+ *  eFuse apb2otp block5 data register8.
+ */
+#define EFUSE_APB2OTP_BLK5_W8_REG (DR_REG_EFUSE_BASE + 0x918)
+/** EFUSE_APB2OTP_BLOCK5_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_M  (EFUSE_APB2OTP_BLOCK5_W8_V << EFUSE_APB2OTP_BLOCK5_W8_S)
+#define EFUSE_APB2OTP_BLOCK5_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W8_S  0
+
+/** EFUSE_APB2OTP_BLK5_W9_REG register
+ *  eFuse apb2otp block5 data register9.
+ */
+#define EFUSE_APB2OTP_BLK5_W9_REG (DR_REG_EFUSE_BASE + 0x91c)
+/** EFUSE_APB2OTP_BLOCK5_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_M  (EFUSE_APB2OTP_BLOCK5_W9_V << EFUSE_APB2OTP_BLOCK5_W9_S)
+#define EFUSE_APB2OTP_BLOCK5_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W9_S  0
+
+/** EFUSE_APB2OTP_BLK5_W10_REG register
+ *  eFuse apb2otp block5 data register10.
+ */
+#define EFUSE_APB2OTP_BLK5_W10_REG (DR_REG_EFUSE_BASE + 0x920)
+/** EFUSE_APB2OTP_BLOCK5_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_M  (EFUSE_APB2OTP_BLOCK5_W10_V << EFUSE_APB2OTP_BLOCK5_W10_S)
+#define EFUSE_APB2OTP_BLOCK5_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W10_S  0
+
+/** EFUSE_APB2OTP_BLK5_W11_REG register
+ *  eFuse apb2otp block5 data register11.
+ */
+#define EFUSE_APB2OTP_BLK5_W11_REG (DR_REG_EFUSE_BASE + 0x924)
+/** EFUSE_APB2OTP_BLOCK5_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block5 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK5_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_M  (EFUSE_APB2OTP_BLOCK5_W11_V << EFUSE_APB2OTP_BLOCK5_W11_S)
+#define EFUSE_APB2OTP_BLOCK5_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK5_W11_S  0
+
+/** EFUSE_APB2OTP_BLK6_W1_REG register
+ *  eFuse apb2otp block6 data register1.
+ */
+#define EFUSE_APB2OTP_BLK6_W1_REG (DR_REG_EFUSE_BASE + 0x928)
+/** EFUSE_APB2OTP_BLOCK6_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_M  (EFUSE_APB2OTP_BLOCK6_W1_V << EFUSE_APB2OTP_BLOCK6_W1_S)
+#define EFUSE_APB2OTP_BLOCK6_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W1_S  0
+
+/** EFUSE_APB2OTP_BLK6_W2_REG register
+ *  eFuse apb2otp block6 data register2.
+ */
+#define EFUSE_APB2OTP_BLK6_W2_REG (DR_REG_EFUSE_BASE + 0x92c)
+/** EFUSE_APB2OTP_BLOCK6_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_M  (EFUSE_APB2OTP_BLOCK6_W2_V << EFUSE_APB2OTP_BLOCK6_W2_S)
+#define EFUSE_APB2OTP_BLOCK6_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W2_S  0
+
+/** EFUSE_APB2OTP_BLK6_W3_REG register
+ *  eFuse apb2otp block6 data register3.
+ */
+#define EFUSE_APB2OTP_BLK6_W3_REG (DR_REG_EFUSE_BASE + 0x930)
+/** EFUSE_APB2OTP_BLOCK6_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_M  (EFUSE_APB2OTP_BLOCK6_W3_V << EFUSE_APB2OTP_BLOCK6_W3_S)
+#define EFUSE_APB2OTP_BLOCK6_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W3_S  0
+
+/** EFUSE_APB2OTP_BLK6_W4_REG register
+ *  eFuse apb2otp block6 data register4.
+ */
+#define EFUSE_APB2OTP_BLK6_W4_REG (DR_REG_EFUSE_BASE + 0x934)
+/** EFUSE_APB2OTP_BLOCK6_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_M  (EFUSE_APB2OTP_BLOCK6_W4_V << EFUSE_APB2OTP_BLOCK6_W4_S)
+#define EFUSE_APB2OTP_BLOCK6_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W4_S  0
+
+/** EFUSE_APB2OTP_BLK6_W5_REG register
+ *  eFuse apb2otp block6 data register5.
+ */
+#define EFUSE_APB2OTP_BLK6_W5_REG (DR_REG_EFUSE_BASE + 0x938)
+/** EFUSE_APB2OTP_BLOCK6_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_M  (EFUSE_APB2OTP_BLOCK6_W5_V << EFUSE_APB2OTP_BLOCK6_W5_S)
+#define EFUSE_APB2OTP_BLOCK6_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W5_S  0
+
+/** EFUSE_APB2OTP_BLK6_W6_REG register
+ *  eFuse apb2otp block6 data register6.
+ */
+#define EFUSE_APB2OTP_BLK6_W6_REG (DR_REG_EFUSE_BASE + 0x93c)
+/** EFUSE_APB2OTP_BLOCK6_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_M  (EFUSE_APB2OTP_BLOCK6_W6_V << EFUSE_APB2OTP_BLOCK6_W6_S)
+#define EFUSE_APB2OTP_BLOCK6_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W6_S  0
+
+/** EFUSE_APB2OTP_BLK6_W7_REG register
+ *  eFuse apb2otp block6 data register7.
+ */
+#define EFUSE_APB2OTP_BLK6_W7_REG (DR_REG_EFUSE_BASE + 0x940)
+/** EFUSE_APB2OTP_BLOCK6_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_M  (EFUSE_APB2OTP_BLOCK6_W7_V << EFUSE_APB2OTP_BLOCK6_W7_S)
+#define EFUSE_APB2OTP_BLOCK6_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W7_S  0
+
+/** EFUSE_APB2OTP_BLK6_W8_REG register
+ *  eFuse apb2otp block6 data register8.
+ */
+#define EFUSE_APB2OTP_BLK6_W8_REG (DR_REG_EFUSE_BASE + 0x944)
+/** EFUSE_APB2OTP_BLOCK6_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_M  (EFUSE_APB2OTP_BLOCK6_W8_V << EFUSE_APB2OTP_BLOCK6_W8_S)
+#define EFUSE_APB2OTP_BLOCK6_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W8_S  0
+
+/** EFUSE_APB2OTP_BLK6_W9_REG register
+ *  eFuse apb2otp block6 data register9.
+ */
+#define EFUSE_APB2OTP_BLK6_W9_REG (DR_REG_EFUSE_BASE + 0x948)
+/** EFUSE_APB2OTP_BLOCK6_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_M  (EFUSE_APB2OTP_BLOCK6_W9_V << EFUSE_APB2OTP_BLOCK6_W9_S)
+#define EFUSE_APB2OTP_BLOCK6_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W9_S  0
+
+/** EFUSE_APB2OTP_BLK6_W10_REG register
+ *  eFuse apb2otp block6 data register10.
+ */
+#define EFUSE_APB2OTP_BLK6_W10_REG (DR_REG_EFUSE_BASE + 0x94c)
+/** EFUSE_APB2OTP_BLOCK6_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_M  (EFUSE_APB2OTP_BLOCK6_W10_V << EFUSE_APB2OTP_BLOCK6_W10_S)
+#define EFUSE_APB2OTP_BLOCK6_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W10_S  0
+
+/** EFUSE_APB2OTP_BLK6_W11_REG register
+ *  eFuse apb2otp block6 data register11.
+ */
+#define EFUSE_APB2OTP_BLK6_W11_REG (DR_REG_EFUSE_BASE + 0x950)
+/** EFUSE_APB2OTP_BLOCK6_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block6 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK6_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_M  (EFUSE_APB2OTP_BLOCK6_W11_V << EFUSE_APB2OTP_BLOCK6_W11_S)
+#define EFUSE_APB2OTP_BLOCK6_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK6_W11_S  0
+
+/** EFUSE_APB2OTP_BLK7_W1_REG register
+ *  eFuse apb2otp block7 data register1.
+ */
+#define EFUSE_APB2OTP_BLK7_W1_REG (DR_REG_EFUSE_BASE + 0x954)
+/** EFUSE_APB2OTP_BLOCK7_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_M  (EFUSE_APB2OTP_BLOCK7_W1_V << EFUSE_APB2OTP_BLOCK7_W1_S)
+#define EFUSE_APB2OTP_BLOCK7_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W1_S  0
+
+/** EFUSE_APB2OTP_BLK7_W2_REG register
+ *  eFuse apb2otp block7 data register2.
+ */
+#define EFUSE_APB2OTP_BLK7_W2_REG (DR_REG_EFUSE_BASE + 0x958)
+/** EFUSE_APB2OTP_BLOCK7_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_M  (EFUSE_APB2OTP_BLOCK7_W2_V << EFUSE_APB2OTP_BLOCK7_W2_S)
+#define EFUSE_APB2OTP_BLOCK7_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W2_S  0
+
+/** EFUSE_APB2OTP_BLK7_W3_REG register
+ *  eFuse apb2otp block7 data register3.
+ */
+#define EFUSE_APB2OTP_BLK7_W3_REG (DR_REG_EFUSE_BASE + 0x95c)
+/** EFUSE_APB2OTP_BLOCK7_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_M  (EFUSE_APB2OTP_BLOCK7_W3_V << EFUSE_APB2OTP_BLOCK7_W3_S)
+#define EFUSE_APB2OTP_BLOCK7_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W3_S  0
+
+/** EFUSE_APB2OTP_BLK7_W4_REG register
+ *  eFuse apb2otp block7 data register4.
+ */
+#define EFUSE_APB2OTP_BLK7_W4_REG (DR_REG_EFUSE_BASE + 0x960)
+/** EFUSE_APB2OTP_BLOCK7_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_M  (EFUSE_APB2OTP_BLOCK7_W4_V << EFUSE_APB2OTP_BLOCK7_W4_S)
+#define EFUSE_APB2OTP_BLOCK7_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W4_S  0
+
+/** EFUSE_APB2OTP_BLK7_W5_REG register
+ *  eFuse apb2otp block7 data register5.
+ */
+#define EFUSE_APB2OTP_BLK7_W5_REG (DR_REG_EFUSE_BASE + 0x964)
+/** EFUSE_APB2OTP_BLOCK7_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_M  (EFUSE_APB2OTP_BLOCK7_W5_V << EFUSE_APB2OTP_BLOCK7_W5_S)
+#define EFUSE_APB2OTP_BLOCK7_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W5_S  0
+
+/** EFUSE_APB2OTP_BLK7_W6_REG register
+ *  eFuse apb2otp block7 data register6.
+ */
+#define EFUSE_APB2OTP_BLK7_W6_REG (DR_REG_EFUSE_BASE + 0x968)
+/** EFUSE_APB2OTP_BLOCK7_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_M  (EFUSE_APB2OTP_BLOCK7_W6_V << EFUSE_APB2OTP_BLOCK7_W6_S)
+#define EFUSE_APB2OTP_BLOCK7_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W6_S  0
+
+/** EFUSE_APB2OTP_BLK7_W7_REG register
+ *  eFuse apb2otp block7 data register7.
+ */
+#define EFUSE_APB2OTP_BLK7_W7_REG (DR_REG_EFUSE_BASE + 0x96c)
+/** EFUSE_APB2OTP_BLOCK7_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_M  (EFUSE_APB2OTP_BLOCK7_W7_V << EFUSE_APB2OTP_BLOCK7_W7_S)
+#define EFUSE_APB2OTP_BLOCK7_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W7_S  0
+
+/** EFUSE_APB2OTP_BLK7_W8_REG register
+ *  eFuse apb2otp block7 data register8.
+ */
+#define EFUSE_APB2OTP_BLK7_W8_REG (DR_REG_EFUSE_BASE + 0x970)
+/** EFUSE_APB2OTP_BLOCK7_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_M  (EFUSE_APB2OTP_BLOCK7_W8_V << EFUSE_APB2OTP_BLOCK7_W8_S)
+#define EFUSE_APB2OTP_BLOCK7_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W8_S  0
+
+/** EFUSE_APB2OTP_BLK7_W9_REG register
+ *  eFuse apb2otp block7 data register9.
+ */
+#define EFUSE_APB2OTP_BLK7_W9_REG (DR_REG_EFUSE_BASE + 0x974)
+/** EFUSE_APB2OTP_BLOCK7_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_M  (EFUSE_APB2OTP_BLOCK7_W9_V << EFUSE_APB2OTP_BLOCK7_W9_S)
+#define EFUSE_APB2OTP_BLOCK7_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W9_S  0
+
+/** EFUSE_APB2OTP_BLK7_W10_REG register
+ *  eFuse apb2otp block7 data register10.
+ */
+#define EFUSE_APB2OTP_BLK7_W10_REG (DR_REG_EFUSE_BASE + 0x978)
+/** EFUSE_APB2OTP_BLOCK7_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_M  (EFUSE_APB2OTP_BLOCK7_W10_V << EFUSE_APB2OTP_BLOCK7_W10_S)
+#define EFUSE_APB2OTP_BLOCK7_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W10_S  0
+
+/** EFUSE_APB2OTP_BLK7_W11_REG register
+ *  eFuse apb2otp block7 data register11.
+ */
+#define EFUSE_APB2OTP_BLK7_W11_REG (DR_REG_EFUSE_BASE + 0x97c)
+/** EFUSE_APB2OTP_BLOCK7_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block7 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK7_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_M  (EFUSE_APB2OTP_BLOCK7_W11_V << EFUSE_APB2OTP_BLOCK7_W11_S)
+#define EFUSE_APB2OTP_BLOCK7_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK7_W11_S  0
+
+/** EFUSE_APB2OTP_BLK8_W1_REG register
+ *  eFuse apb2otp block8 data register1.
+ */
+#define EFUSE_APB2OTP_BLK8_W1_REG (DR_REG_EFUSE_BASE + 0x980)
+/** EFUSE_APB2OTP_BLOCK8_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_M  (EFUSE_APB2OTP_BLOCK8_W1_V << EFUSE_APB2OTP_BLOCK8_W1_S)
+#define EFUSE_APB2OTP_BLOCK8_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W1_S  0
+
+/** EFUSE_APB2OTP_BLK8_W2_REG register
+ *  eFuse apb2otp block8 data register2.
+ */
+#define EFUSE_APB2OTP_BLK8_W2_REG (DR_REG_EFUSE_BASE + 0x984)
+/** EFUSE_APB2OTP_BLOCK8_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_M  (EFUSE_APB2OTP_BLOCK8_W2_V << EFUSE_APB2OTP_BLOCK8_W2_S)
+#define EFUSE_APB2OTP_BLOCK8_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W2_S  0
+
+/** EFUSE_APB2OTP_BLK8_W3_REG register
+ *  eFuse apb2otp block8 data register3.
+ */
+#define EFUSE_APB2OTP_BLK8_W3_REG (DR_REG_EFUSE_BASE + 0x988)
+/** EFUSE_APB2OTP_BLOCK8_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_M  (EFUSE_APB2OTP_BLOCK8_W3_V << EFUSE_APB2OTP_BLOCK8_W3_S)
+#define EFUSE_APB2OTP_BLOCK8_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W3_S  0
+
+/** EFUSE_APB2OTP_BLK8_W4_REG register
+ *  eFuse apb2otp block8 data register4.
+ */
+#define EFUSE_APB2OTP_BLK8_W4_REG (DR_REG_EFUSE_BASE + 0x98c)
+/** EFUSE_APB2OTP_BLOCK8_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_M  (EFUSE_APB2OTP_BLOCK8_W4_V << EFUSE_APB2OTP_BLOCK8_W4_S)
+#define EFUSE_APB2OTP_BLOCK8_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W4_S  0
+
+/** EFUSE_APB2OTP_BLK8_W5_REG register
+ *  eFuse apb2otp block8 data register5.
+ */
+#define EFUSE_APB2OTP_BLK8_W5_REG (DR_REG_EFUSE_BASE + 0x990)
+/** EFUSE_APB2OTP_BLOCK8_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_M  (EFUSE_APB2OTP_BLOCK8_W5_V << EFUSE_APB2OTP_BLOCK8_W5_S)
+#define EFUSE_APB2OTP_BLOCK8_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W5_S  0
+
+/** EFUSE_APB2OTP_BLK8_W6_REG register
+ *  eFuse apb2otp block8 data register6.
+ */
+#define EFUSE_APB2OTP_BLK8_W6_REG (DR_REG_EFUSE_BASE + 0x994)
+/** EFUSE_APB2OTP_BLOCK8_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_M  (EFUSE_APB2OTP_BLOCK8_W6_V << EFUSE_APB2OTP_BLOCK8_W6_S)
+#define EFUSE_APB2OTP_BLOCK8_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W6_S  0
+
+/** EFUSE_APB2OTP_BLK8_W7_REG register
+ *  eFuse apb2otp block8 data register7.
+ */
+#define EFUSE_APB2OTP_BLK8_W7_REG (DR_REG_EFUSE_BASE + 0x998)
+/** EFUSE_APB2OTP_BLOCK8_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_M  (EFUSE_APB2OTP_BLOCK8_W7_V << EFUSE_APB2OTP_BLOCK8_W7_S)
+#define EFUSE_APB2OTP_BLOCK8_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W7_S  0
+
+/** EFUSE_APB2OTP_BLK8_W8_REG register
+ *  eFuse apb2otp block8 data register8.
+ */
+#define EFUSE_APB2OTP_BLK8_W8_REG (DR_REG_EFUSE_BASE + 0x99c)
+/** EFUSE_APB2OTP_BLOCK8_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_M  (EFUSE_APB2OTP_BLOCK8_W8_V << EFUSE_APB2OTP_BLOCK8_W8_S)
+#define EFUSE_APB2OTP_BLOCK8_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W8_S  0
+
+/** EFUSE_APB2OTP_BLK8_W9_REG register
+ *  eFuse apb2otp block8 data register9.
+ */
+#define EFUSE_APB2OTP_BLK8_W9_REG (DR_REG_EFUSE_BASE + 0x9a0)
+/** EFUSE_APB2OTP_BLOCK8_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_M  (EFUSE_APB2OTP_BLOCK8_W9_V << EFUSE_APB2OTP_BLOCK8_W9_S)
+#define EFUSE_APB2OTP_BLOCK8_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W9_S  0
+
+/** EFUSE_APB2OTP_BLK8_W10_REG register
+ *  eFuse apb2otp block8 data register10.
+ */
+#define EFUSE_APB2OTP_BLK8_W10_REG (DR_REG_EFUSE_BASE + 0x9a4)
+/** EFUSE_APB2OTP_BLOCK8_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_M  (EFUSE_APB2OTP_BLOCK8_W10_V << EFUSE_APB2OTP_BLOCK8_W10_S)
+#define EFUSE_APB2OTP_BLOCK8_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W10_S  0
+
+/** EFUSE_APB2OTP_BLK8_W11_REG register
+ *  eFuse apb2otp block8 data register11.
+ */
+#define EFUSE_APB2OTP_BLK8_W11_REG (DR_REG_EFUSE_BASE + 0x9a8)
+/** EFUSE_APB2OTP_BLOCK8_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block8 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK8_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_M  (EFUSE_APB2OTP_BLOCK8_W11_V << EFUSE_APB2OTP_BLOCK8_W11_S)
+#define EFUSE_APB2OTP_BLOCK8_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK8_W11_S  0
+
+/** EFUSE_APB2OTP_BLK9_W1_REG register
+ *  eFuse apb2otp block9 data register1.
+ */
+#define EFUSE_APB2OTP_BLK9_W1_REG (DR_REG_EFUSE_BASE + 0x9ac)
+/** EFUSE_APB2OTP_BLOCK9_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_M  (EFUSE_APB2OTP_BLOCK9_W1_V << EFUSE_APB2OTP_BLOCK9_W1_S)
+#define EFUSE_APB2OTP_BLOCK9_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W1_S  0
+
+/** EFUSE_APB2OTP_BLK9_W2_REG register
+ *  eFuse apb2otp block9 data register2.
+ */
+#define EFUSE_APB2OTP_BLK9_W2_REG (DR_REG_EFUSE_BASE + 0x9b0)
+/** EFUSE_APB2OTP_BLOCK9_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_M  (EFUSE_APB2OTP_BLOCK9_W2_V << EFUSE_APB2OTP_BLOCK9_W2_S)
+#define EFUSE_APB2OTP_BLOCK9_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W2_S  0
+
+/** EFUSE_APB2OTP_BLK9_W3_REG register
+ *  eFuse apb2otp block9 data register3.
+ */
+#define EFUSE_APB2OTP_BLK9_W3_REG (DR_REG_EFUSE_BASE + 0x9b4)
+/** EFUSE_APB2OTP_BLOCK9_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_M  (EFUSE_APB2OTP_BLOCK9_W3_V << EFUSE_APB2OTP_BLOCK9_W3_S)
+#define EFUSE_APB2OTP_BLOCK9_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W3_S  0
+
+/** EFUSE_APB2OTP_BLK9_W4_REG register
+ *  eFuse apb2otp block9 data register4.
+ */
+#define EFUSE_APB2OTP_BLK9_W4_REG (DR_REG_EFUSE_BASE + 0x9b8)
+/** EFUSE_APB2OTP_BLOCK9_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_M  (EFUSE_APB2OTP_BLOCK9_W4_V << EFUSE_APB2OTP_BLOCK9_W4_S)
+#define EFUSE_APB2OTP_BLOCK9_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W4_S  0
+
+/** EFUSE_APB2OTP_BLK9_W5_REG register
+ *  eFuse apb2otp block9 data register5.
+ */
+#define EFUSE_APB2OTP_BLK9_W5_REG (DR_REG_EFUSE_BASE + 0x9bc)
+/** EFUSE_APB2OTP_BLOCK9_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_M  (EFUSE_APB2OTP_BLOCK9_W5_V << EFUSE_APB2OTP_BLOCK9_W5_S)
+#define EFUSE_APB2OTP_BLOCK9_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W5_S  0
+
+/** EFUSE_APB2OTP_BLK9_W6_REG register
+ *  eFuse apb2otp block9 data register6.
+ */
+#define EFUSE_APB2OTP_BLK9_W6_REG (DR_REG_EFUSE_BASE + 0x9c0)
+/** EFUSE_APB2OTP_BLOCK9_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_M  (EFUSE_APB2OTP_BLOCK9_W6_V << EFUSE_APB2OTP_BLOCK9_W6_S)
+#define EFUSE_APB2OTP_BLOCK9_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W6_S  0
+
+/** EFUSE_APB2OTP_BLK9_W7_REG register
+ *  eFuse apb2otp block9 data register7.
+ */
+#define EFUSE_APB2OTP_BLK9_W7_REG (DR_REG_EFUSE_BASE + 0x9c4)
+/** EFUSE_APB2OTP_BLOCK9_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_M  (EFUSE_APB2OTP_BLOCK9_W7_V << EFUSE_APB2OTP_BLOCK9_W7_S)
+#define EFUSE_APB2OTP_BLOCK9_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W7_S  0
+
+/** EFUSE_APB2OTP_BLK9_W8_REG register
+ *  eFuse apb2otp block9 data register8.
+ */
+#define EFUSE_APB2OTP_BLK9_W8_REG (DR_REG_EFUSE_BASE + 0x9c8)
+/** EFUSE_APB2OTP_BLOCK9_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_M  (EFUSE_APB2OTP_BLOCK9_W8_V << EFUSE_APB2OTP_BLOCK9_W8_S)
+#define EFUSE_APB2OTP_BLOCK9_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W8_S  0
+
+/** EFUSE_APB2OTP_BLK9_W9_REG register
+ *  eFuse apb2otp block9 data register9.
+ */
+#define EFUSE_APB2OTP_BLK9_W9_REG (DR_REG_EFUSE_BASE + 0x9cc)
+/** EFUSE_APB2OTP_BLOCK9_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_M  (EFUSE_APB2OTP_BLOCK9_W9_V << EFUSE_APB2OTP_BLOCK9_W9_S)
+#define EFUSE_APB2OTP_BLOCK9_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W9_S  0
+
+/** EFUSE_APB2OTP_BLK9_W10_REG register
+ *  eFuse apb2otp block9 data register10.
+ */
+#define EFUSE_APB2OTP_BLK9_W10_REG (DR_REG_EFUSE_BASE + 0x9d0)
+/** EFUSE_APB2OTP_BLOCK9_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_M  (EFUSE_APB2OTP_BLOCK9_W10_V << EFUSE_APB2OTP_BLOCK9_W10_S)
+#define EFUSE_APB2OTP_BLOCK9_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W10_S  0
+
+/** EFUSE_APB2OTP_BLK9_W11_REG register
+ *  eFuse apb2otp block9 data register11.
+ */
+#define EFUSE_APB2OTP_BLK9_W11_REG (DR_REG_EFUSE_BASE + 0x9d4)
+/** EFUSE_APB2OTP_BLOCK9_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block9 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK9_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_M  (EFUSE_APB2OTP_BLOCK9_W11_V << EFUSE_APB2OTP_BLOCK9_W11_S)
+#define EFUSE_APB2OTP_BLOCK9_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK9_W11_S  0
+
+/** EFUSE_APB2OTP_BLK10_W1_REG register
+ *  eFuse apb2otp block10 data register1.
+ */
+#define EFUSE_APB2OTP_BLK10_W1_REG (DR_REG_EFUSE_BASE + 0x9d8)
+/** EFUSE_APB2OTP_BLOCK10_W1 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word1 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W1    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_M  (EFUSE_APB2OTP_BLOCK10_W1_V << EFUSE_APB2OTP_BLOCK10_W1_S)
+#define EFUSE_APB2OTP_BLOCK10_W1_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W1_S  0
+
+/** EFUSE_APB2OTP_BLK10_W2_REG register
+ *  eFuse apb2otp block10 data register2.
+ */
+#define EFUSE_APB2OTP_BLK10_W2_REG (DR_REG_EFUSE_BASE + 0x9dc)
+/** EFUSE_APB2OTP_BLOCK10_W2 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word2 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W2    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_M  (EFUSE_APB2OTP_BLOCK10_W2_V << EFUSE_APB2OTP_BLOCK10_W2_S)
+#define EFUSE_APB2OTP_BLOCK10_W2_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W2_S  0
+
+/** EFUSE_APB2OTP_BLK10_W3_REG register
+ *  eFuse apb2otp block10 data register3.
+ */
+#define EFUSE_APB2OTP_BLK10_W3_REG (DR_REG_EFUSE_BASE + 0x9e0)
+/** EFUSE_APB2OTP_BLOCK10_W3 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word3 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W3    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_M  (EFUSE_APB2OTP_BLOCK10_W3_V << EFUSE_APB2OTP_BLOCK10_W3_S)
+#define EFUSE_APB2OTP_BLOCK10_W3_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W3_S  0
+
+/** EFUSE_APB2OTP_BLK10_W4_REG register
+ *  eFuse apb2otp block10 data register4.
+ */
+#define EFUSE_APB2OTP_BLK10_W4_REG (DR_REG_EFUSE_BASE + 0x9e4)
+/** EFUSE_APB2OTP_BLOCK10_W4 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word4 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W4    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_M  (EFUSE_APB2OTP_BLOCK10_W4_V << EFUSE_APB2OTP_BLOCK10_W4_S)
+#define EFUSE_APB2OTP_BLOCK10_W4_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W4_S  0
+
+/** EFUSE_APB2OTP_BLK10_W5_REG register
+ *  eFuse apb2otp block10 data register5.
+ */
+#define EFUSE_APB2OTP_BLK10_W5_REG (DR_REG_EFUSE_BASE + 0x9e8)
+/** EFUSE_APB2OTP_BLOCK10_W5 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word5 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W5    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_M  (EFUSE_APB2OTP_BLOCK10_W5_V << EFUSE_APB2OTP_BLOCK10_W5_S)
+#define EFUSE_APB2OTP_BLOCK10_W5_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W5_S  0
+
+/** EFUSE_APB2OTP_BLK10_W6_REG register
+ *  eFuse apb2otp block10 data register6.
+ */
+#define EFUSE_APB2OTP_BLK10_W6_REG (DR_REG_EFUSE_BASE + 0x9ec)
+/** EFUSE_APB2OTP_BLOCK10_W6 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word6 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W6    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_M  (EFUSE_APB2OTP_BLOCK10_W6_V << EFUSE_APB2OTP_BLOCK10_W6_S)
+#define EFUSE_APB2OTP_BLOCK10_W6_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W6_S  0
+
+/** EFUSE_APB2OTP_BLK10_W7_REG register
+ *  eFuse apb2otp block10 data register7.
+ */
+#define EFUSE_APB2OTP_BLK10_W7_REG (DR_REG_EFUSE_BASE + 0x9f0)
+/** EFUSE_APB2OTP_BLOCK10_W7 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word7 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W7    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_M  (EFUSE_APB2OTP_BLOCK10_W7_V << EFUSE_APB2OTP_BLOCK10_W7_S)
+#define EFUSE_APB2OTP_BLOCK10_W7_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W7_S  0
+
+/** EFUSE_APB2OTP_BLK10_W8_REG register
+ *  eFuse apb2otp block10 data register8.
+ */
+#define EFUSE_APB2OTP_BLK10_W8_REG (DR_REG_EFUSE_BASE + 0x9f4)
+/** EFUSE_APB2OTP_BLOCK10_W8 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word8 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W8    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_M  (EFUSE_APB2OTP_BLOCK10_W8_V << EFUSE_APB2OTP_BLOCK10_W8_S)
+#define EFUSE_APB2OTP_BLOCK10_W8_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W8_S  0
+
+/** EFUSE_APB2OTP_BLK10_W9_REG register
+ *  eFuse apb2otp block10 data register9.
+ */
+#define EFUSE_APB2OTP_BLK10_W9_REG (DR_REG_EFUSE_BASE + 0x9f8)
+/** EFUSE_APB2OTP_BLOCK10_W9 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word9 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W9    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_M  (EFUSE_APB2OTP_BLOCK10_W9_V << EFUSE_APB2OTP_BLOCK10_W9_S)
+#define EFUSE_APB2OTP_BLOCK10_W9_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W9_S  0
+
+/** EFUSE_APB2OTP_BLK10_W10_REG register
+ *  eFuse apb2otp block10 data register10.
+ */
+#define EFUSE_APB2OTP_BLK10_W10_REG (DR_REG_EFUSE_BASE + 0x9fc)
+/** EFUSE_APB2OTP_BLOCK19_W10 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word10 data.
+ */
+#define EFUSE_APB2OTP_BLOCK19_W10    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK19_W10_M  (EFUSE_APB2OTP_BLOCK19_W10_V << EFUSE_APB2OTP_BLOCK19_W10_S)
+#define EFUSE_APB2OTP_BLOCK19_W10_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK19_W10_S  0
+
+/** EFUSE_APB2OTP_BLK10_W11_REG register
+ *  eFuse apb2otp block10 data register11.
+ */
+#define EFUSE_APB2OTP_BLK10_W11_REG (DR_REG_EFUSE_BASE + 0xa00)
+/** EFUSE_APB2OTP_BLOCK10_W11 : RO; bitpos: [31:0]; default: 0;
+ *  Otp block10 word11 data.
+ */
+#define EFUSE_APB2OTP_BLOCK10_W11    0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_M  (EFUSE_APB2OTP_BLOCK10_W11_V << EFUSE_APB2OTP_BLOCK10_W11_S)
+#define EFUSE_APB2OTP_BLOCK10_W11_V  0xFFFFFFFFU
+#define EFUSE_APB2OTP_BLOCK10_W11_S  0
+
+/** EFUSE_APB2OTP_EN_REG register
+ *  eFuse apb2otp enable configuration register.
+ */
+#define EFUSE_APB2OTP_EN_REG (DR_REG_EFUSE_BASE + 0xa08)
+/** EFUSE_APB2OTP_APB2OTP_EN : R/W; bitpos: [0]; default: 0;
+ *  Apb2otp mode enable signal.
+ */
+#define EFUSE_APB2OTP_APB2OTP_EN    (BIT(0))
+#define EFUSE_APB2OTP_APB2OTP_EN_M  (EFUSE_APB2OTP_APB2OTP_EN_V << EFUSE_APB2OTP_APB2OTP_EN_S)
+#define EFUSE_APB2OTP_APB2OTP_EN_V  0x00000001U
+#define EFUSE_APB2OTP_APB2OTP_EN_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/efuse_struct.h b/components/soc/esp32p4/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..f96653c4685
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/efuse_struct.h
@@ -0,0 +1,4735 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: ******** Registers */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled or
+         *  enabled. 1: Disabled. 0 Enabled.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block10) is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t rd_dis:7;
+        /** usb_device_exchg_pins : RO; bitpos: [7]; default: 0;
+         *  Enable usb device exchange pins of D+ and D-.
+         */
+        uint32_t usb_device_exchg_pins:1;
+        /** usb_otg11_exchg_pins : RO; bitpos: [8]; default: 0;
+         *  Enable usb otg11 exchange pins of D+ and D-.
+         */
+        uint32_t usb_otg11_exchg_pins:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** powerglitch_en : RO; bitpos: [10]; default: 0;
+         *  Represents whether power glitch function is enabled. 1: enabled. 0: disabled.
+         */
+        uint32_t powerglitch_en:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0;
+         *  Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during
+         *  boot_mode_download.
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         *  is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number:
+         *  enabled.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0:
+         *  enabled.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode). 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_device_drefh : RO; bitpos: [22:21]; default: 0;
+         *  USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_device_drefh:2;
+        /** usb_otg11_drefh : RO; bitpos: [24:23]; default: 0;
+         *  USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV
+         */
+        uint32_t usb_otg11_drefh:2;
+        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
+         *  TBD
+         */
+        uint32_t usb_phy_sel:1;
+        /** km_huk_gen_state_low : RO; bitpos: [31:26]; default: 0;
+         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t km_huk_gen_state_low:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register 2.
+ */
+typedef union {
+    struct {
+        /** km_huk_gen_state_high : RO; bitpos: [2:0]; default: 0;
+         *  Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even
+         *  of 1 is valid.
+         */
+        uint32_t km_huk_gen_state_high:3;
+        /** km_rnd_switch_cycle : RO; bitpos: [4:3]; default: 0;
+         *  Set bits to control key manager random number switch cycle. 0: control by register.
+         *  1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles.
+         */
+        uint32_t km_rnd_switch_cycle:2;
+        /** km_deploy_only_once : RO; bitpos: [8:5]; default: 0;
+         *  Set each bit to control whether corresponding key can only be deployed once. 1 is
+         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         */
+        uint32_t km_deploy_only_once:4;
+        /** force_use_key_manager_key : RO; bitpos: [12:9]; default: 0;
+         *  Set each bit to control whether corresponding key must come from key manager.. 1 is
+         *  true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds.
+         */
+        uint32_t force_use_key_manager_key:4;
+        /** force_disable_sw_init_key : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable software written init key, and force use efuse_init_key.
+         */
+        uint32_t force_disable_sw_init_key:1;
+        /** xts_key_length_256 : RO; bitpos: [14]; default: 0;
+         *  Set this bit to configure flash encryption use xts-128 key, else use xts-256 key.
+         */
+        uint32_t xts_key_length_256:1;
+        /** rd_reserve_0_79 : RW; bitpos: [15]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_79:1;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Represents whether RTC watchdog timeout threshold is selected at startup. 1:
+         *  selected. 0: not selected.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of
+         *  1: enabled. Even number of 1: disabled.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register 3.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Represents the purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** ecdsa_enable_soft_k : RO; bitpos: [18]; default: 0;
+         *  Represents whether hardware random number k is forced used in ESDCA. 1: force used.
+         *  0: not force used.
+         */
+        uint32_t ecdsa_enable_soft_k:1;
+        /** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
+         *  Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
+         */
+        uint32_t crypt_dpa_enable:1;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled. 1:
+         *  enabled. 0: disabled.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** rd_reserve_0_118 : RW; bitpos: [22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_118:1;
+        /** flash_type : RO; bitpos: [23]; default: 0;
+         *  The type of interfaced flash. 0: four data lines, 1: eight data lines.
+         */
+        uint32_t flash_type:1;
+        /** flash_page_size : RO; bitpos: [25:24]; default: 0;
+         *  Set flash page size.
+         */
+        uint32_t flash_page_size:2;
+        /** flash_ecc_en : RO; bitpos: [26]; default: 0;
+         *  Set this bit to enable ecc for flash boot.
+         */
+        uint32_t flash_ecc_en:1;
+        /** dis_usb_otg_download_mode : RO; bitpos: [27]; default: 0;
+         *  Set this bit to disable download via USB-OTG.
+         */
+        uint32_t dis_usb_otg_download_mode:1;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+         *  is 2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register 4.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
+         *  0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** lock_km_key : RO; bitpos: [3]; default: 0;
+         *  TBD
+         */
+        uint32_t lock_km_key:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1:
+         *  disabled. 0: enabled.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Represents whether security download is enabled or disabled. 1: enabled. 0:
+         *  disabled.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Represents the type of UART printing. 00: force enable printing. 01: enable
+         *  printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset
+         *  at high level. 11: force disable printing.
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [8]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot. 1:
+         *  forced. 0:not forced.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [24:9]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [25]; default: 0;
+         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+         *  enabled. 1: disabled. 0: enabled.
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [26]; default: 0;
+         *  Represents whether the hysteresis function of corresponding PAD is enabled. 1:
+         *  enabled. 0:disabled.
+         */
+        uint32_t hys_en_pad:1;
+        /** dcdc_vset : RO; bitpos: [31:27]; default: 0;
+         *  Set the dcdc voltage default.
+         */
+        uint32_t dcdc_vset:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register 5.
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0 : RO; bitpos: [1:0]; default: 0;
+         *  TBD
+         */
+        uint32_t pxa0_tieh_sel_0:2;
+        /** pxa0_tieh_sel_1 : RO; bitpos: [3:2]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_1:2;
+        /** pxa0_tieh_sel_2 : RO; bitpos: [5:4]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_2:2;
+        /** pxa0_tieh_sel_3 : RO; bitpos: [7:6]; default: 0;
+         *  TBD.
+         */
+        uint32_t pxa0_tieh_sel_3:2;
+        /** km_disable_deploy_mode : RO; bitpos: [11:8]; default: 0;
+         *  TBD.
+         */
+        uint32_t km_disable_deploy_mode:4;
+        /** usb_device_drefl : RO; bitpos: [13:12]; default: 0;
+         *  Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_device_drefl:2;
+        /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0;
+         *  Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step
+         *  of 80 mV.
+         */
+        uint32_t usb_otg11_drefl:2;
+        /** rd_reserve_0_176 : RW; bitpos: [17:16]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_176:2;
+        /** hp_pwr_src_sel : RO; bitpos: [18]; default: 0;
+         *  HP system power source select. 0:LDO. 1: DCDC.
+         */
+        uint32_t hp_pwr_src_sel:1;
+        /** dcdc_vset_en : RO; bitpos: [19]; default: 0;
+         *  Select dcdc vset use efuse_dcdc_vset.
+         */
+        uint32_t dcdc_vset_en:1;
+        /** dis_wdt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable watch dog.
+         */
+        uint32_t dis_wdt:1;
+        /** dis_swd : RO; bitpos: [21]; default: 0;
+         *  Set this bit to disable super-watchdog.
+         */
+        uint32_t dis_swd:1;
+        /** rd_reserve_0_182 : RW; bitpos: [31:22]; default: 0;
+         *  Reserved, it was created by set_missed_fields_in_regs func
+         */
+        uint32_t rd_reserve_0_182:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_sys_0 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_0_reg_t;
+
+/** Type of rd_mac_sys_1 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** reserved_1_16 : RO; bitpos: [31:16]; default: 0;
+         *  Stores the extended bits of MAC address.
+         */
+        uint32_t reserved_1_16:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_1_reg_t;
+
+/** Type of rd_mac_sys_2 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** wafer_version_minor : R; bitpos: [3:0]; default: 0;
+         *  Minor chip version
+         */
+        uint32_t wafer_version_minor:4;
+        /** wafer_version_major : R; bitpos: [5:4]; default: 0;
+         *  Major chip version
+         */
+        uint32_t wafer_version_major:2;
+        /** disable_wafer_version_major : R; bitpos: [6]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [7]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** blk_version_minor : R; bitpos: [10:8]; default: 0;
+         *  BLK_VERSION_MINOR of BLOCK2
+         */
+        uint32_t blk_version_minor:3;
+        /** blk_version_major : R; bitpos: [12:11]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2
+         */
+        uint32_t blk_version_major:2;
+        /** psram_cap : R; bitpos: [15:13]; default: 0;
+         *  PSRAM capacity
+         */
+        uint32_t psram_cap:3;
+        /** temp : R; bitpos: [17:16]; default: 0;
+         *  Operating temperature of the ESP chip
+         */
+        uint32_t temp:2;
+        /** psram_vendor : R; bitpos: [19:18]; default: 0;
+         *  PSRAM vendor
+         */
+        uint32_t psram_vendor:2;
+        /** pkg_version : R; bitpos: [22:20]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** reserved_1_87 : R; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_87:1;
+        /** ldo_vo1_dref : R; bitpos: [27:24]; default: 0;
+         *  Output VO1 parameter
+         */
+        uint32_t ldo_vo1_dref:4;
+        /** ldo_vo2_dref : R; bitpos: [31:28]; default: 0;
+         *  Output VO2 parameter
+         */
+        uint32_t ldo_vo2_dref:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_2_reg_t;
+
+/** Type of rd_mac_sys_3 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** ldo_vo1_mul : R; bitpos: [2:0]; default: 0;
+         *  Output VO1 parameter
+         */
+        uint32_t ldo_vo1_mul:3;
+        /** ldo_vo2_mul : R; bitpos: [5:3]; default: 0;
+         *  Output VO2 parameter
+         */
+        uint32_t ldo_vo2_mul:3;
+        /** ldo_vo3_k : R; bitpos: [13:6]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_k:8;
+        /** ldo_vo3_vos : R; bitpos: [19:14]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_vos:6;
+        /** ldo_vo3_c : R; bitpos: [25:20]; default: 0;
+         *  Output VO3 calibration parameter
+         */
+        uint32_t ldo_vo3_c:6;
+        /** ldo_vo4_k : R; bitpos: [31:26]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_k:6;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_3_reg_t;
+
+/** Type of rd_mac_sys_4 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** ldo_vo4_k_1 : R; bitpos: [1:0]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_k_1:2;
+        /** ldo_vo4_vos : R; bitpos: [7:2]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_vos:6;
+        /** ldo_vo4_c : R; bitpos: [13:8]; default: 0;
+         *  Output VO4 calibration parameter
+         */
+        uint32_t ldo_vo4_c:6;
+        /** reserved_1_142 : R; bitpos: [15:14]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_142:2;
+        /** active_hp_dbias : R; bitpos: [19:16]; default: 0;
+         *  Active HP DBIAS of fixed voltage
+         */
+        uint32_t active_hp_dbias:4;
+        /** active_lp_dbias : R; bitpos: [23:20]; default: 0;
+         *  Active LP DBIAS of fixed voltage
+         */
+        uint32_t active_lp_dbias:4;
+        /** lslp_hp_dbias : R; bitpos: [27:24]; default: 0;
+         *  LSLP HP DBIAS of fixed voltage
+         */
+        uint32_t lslp_hp_dbias:4;
+        /** dslp_dbg : R; bitpos: [31:28]; default: 0;
+         *  DSLP BDG of fixed voltage
+         */
+        uint32_t dslp_dbg:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_4_reg_t;
+
+/** Type of rd_mac_sys_5 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** dslp_lp_dbias : R; bitpos: [4:0]; default: 0;
+         *  DSLP LP DBIAS of fixed voltage
+         */
+        uint32_t dslp_lp_dbias:5;
+        /** lp_dcdc_dbias_vol_gap : R; bitpos: [9:5]; default: 0;
+         *  DBIAS gap between LP and DCDC
+         */
+        uint32_t lp_dcdc_dbias_vol_gap:5;
+        /** reserved_1_170 : R; bitpos: [31:10]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_170:22;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ave_initcode_atten0 : R; bitpos: [9:0]; default: 0;
+         *  Average initcode of ADC1 atten0
+         */
+        uint32_t adc1_ave_initcode_atten0:10;
+        /** adc1_ave_initcode_atten1 : R; bitpos: [19:10]; default: 0;
+         *  Average initcode of ADC1 atten1
+         */
+        uint32_t adc1_ave_initcode_atten1:10;
+        /** adc1_ave_initcode_atten2 : R; bitpos: [29:20]; default: 0;
+         *  Average initcode of ADC1 atten2
+         */
+        uint32_t adc1_ave_initcode_atten2:10;
+        /** adc1_ave_initcode_atten3 : R; bitpos: [31:30]; default: 0;
+         *  Average initcode of ADC1 atten3
+         */
+        uint32_t adc1_ave_initcode_atten3:2;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ave_initcode_atten3_1 : R; bitpos: [7:0]; default: 0;
+         *  Average initcode of ADC1 atten3
+         */
+        uint32_t adc1_ave_initcode_atten3_1:8;
+        /** adc2_ave_initcode_atten0 : R; bitpos: [17:8]; default: 0;
+         *  Average initcode of ADC2 atten0
+         */
+        uint32_t adc2_ave_initcode_atten0:10;
+        /** adc2_ave_initcode_atten1 : R; bitpos: [27:18]; default: 0;
+         *  Average initcode of ADC2 atten1
+         */
+        uint32_t adc2_ave_initcode_atten1:10;
+        /** adc2_ave_initcode_atten2 : R; bitpos: [31:28]; default: 0;
+         *  Average initcode of ADC2 atten2
+         */
+        uint32_t adc2_ave_initcode_atten2:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc2_ave_initcode_atten2_1 : R; bitpos: [5:0]; default: 0;
+         *  Average initcode of ADC2 atten2
+         */
+        uint32_t adc2_ave_initcode_atten2_1:6;
+        /** adc2_ave_initcode_atten3 : R; bitpos: [15:6]; default: 0;
+         *  Average initcode of ADC2 atten3
+         */
+        uint32_t adc2_ave_initcode_atten3:10;
+        /** adc1_hi_dout_atten0 : R; bitpos: [25:16]; default: 0;
+         *  HI_DOUT of ADC1 atten0
+         */
+        uint32_t adc1_hi_dout_atten0:10;
+        /** adc1_hi_dout_atten1 : R; bitpos: [31:26]; default: 0;
+         *  HI_DOUT of ADC1 atten1
+         */
+        uint32_t adc1_hi_dout_atten1:6;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_hi_dout_atten1_1 : R; bitpos: [3:0]; default: 0;
+         *  HI_DOUT of ADC1 atten1
+         */
+        uint32_t adc1_hi_dout_atten1_1:4;
+        /** adc1_hi_dout_atten2 : R; bitpos: [13:4]; default: 0;
+         *  HI_DOUT of ADC1 atten2
+         */
+        uint32_t adc1_hi_dout_atten2:10;
+        /** adc1_hi_dout_atten3 : R; bitpos: [23:14]; default: 0;
+         *  HI_DOUT of ADC1 atten3
+         */
+        uint32_t adc1_hi_dout_atten3:10;
+        /** reserved_2_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_248:8;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** adc2_hi_dout_atten0 : R; bitpos: [9:0]; default: 0;
+         *  HI_DOUT of ADC2 atten0
+         */
+        uint32_t adc2_hi_dout_atten0:10;
+        /** adc2_hi_dout_atten1 : R; bitpos: [19:10]; default: 0;
+         *  HI_DOUT of ADC2 atten1
+         */
+        uint32_t adc2_hi_dout_atten1:10;
+        /** adc2_hi_dout_atten2 : R; bitpos: [29:20]; default: 0;
+         *  HI_DOUT of ADC2 atten2
+         */
+        uint32_t adc2_hi_dout_atten2:10;
+        /** adc2_hi_dout_atten3 : R; bitpos: [31:30]; default: 0;
+         *  HI_DOUT of ADC2 atten3
+         */
+        uint32_t adc2_hi_dout_atten3:2;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** adc2_hi_dout_atten3_1 : R; bitpos: [7:0]; default: 0;
+         *  HI_DOUT of ADC2 atten3
+         */
+        uint32_t adc2_hi_dout_atten3_1:8;
+        /** adc1_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
+         *  Gap between ADC1_ch0 and average initcode
+         */
+        uint32_t adc1_ch0_atten0_initcode_diff:4;
+        /** adc1_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
+         *  Gap between ADC1_ch1 and average initcode
+         */
+        uint32_t adc1_ch1_atten0_initcode_diff:4;
+        /** adc1_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
+         *  Gap between ADC1_ch2 and average initcode
+         */
+        uint32_t adc1_ch2_atten0_initcode_diff:4;
+        /** adc1_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
+         *  Gap between ADC1_ch3 and average initcode
+         */
+        uint32_t adc1_ch3_atten0_initcode_diff:4;
+        /** adc1_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
+         *  Gap between ADC1_ch4 and average initcode
+         */
+        uint32_t adc1_ch4_atten0_initcode_diff:4;
+        /** adc1_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
+         *  Gap between ADC1_ch5 and average initcode
+         */
+        uint32_t adc1_ch5_atten0_initcode_diff:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_ch6_atten0_initcode_diff : R; bitpos: [3:0]; default: 0;
+         *  Gap between ADC1_ch6 and average initcode
+         */
+        uint32_t adc1_ch6_atten0_initcode_diff:4;
+        /** adc1_ch7_atten0_initcode_diff : R; bitpos: [7:4]; default: 0;
+         *  Gap between ADC1_ch7 and average initcode
+         */
+        uint32_t adc1_ch7_atten0_initcode_diff:4;
+        /** adc2_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
+         *  Gap between ADC2_ch0 and average initcode
+         */
+        uint32_t adc2_ch0_atten0_initcode_diff:4;
+        /** adc2_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
+         *  Gap between ADC2_ch1 and average initcode
+         */
+        uint32_t adc2_ch1_atten0_initcode_diff:4;
+        /** adc2_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
+         *  Gap between ADC2_ch2 and average initcode
+         */
+        uint32_t adc2_ch2_atten0_initcode_diff:4;
+        /** adc2_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
+         *  Gap between ADC2_ch3 and average initcode
+         */
+        uint32_t adc2_ch3_atten0_initcode_diff:4;
+        /** adc2_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
+         *  Gap between ADC2_ch4 and average initcode
+         */
+        uint32_t adc2_ch4_atten0_initcode_diff:4;
+        /** adc2_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
+         *  Gap between ADC2_ch5 and average initcode
+         */
+        uint32_t adc2_ch5_atten0_initcode_diff:4;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** temperature_sensor : R; bitpos: [8:0]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temperature_sensor:9;
+        /** reserved_10_105 : R; bitpos: [31:9]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_10_105:23;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Indicates a programming error of RD_DIS.
+         */
+        uint32_t rd_dis_err:7;
+        /** dis_usb_device_exchg_pins_err : RO; bitpos: [7]; default: 0;
+         *  Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS.
+         */
+        uint32_t dis_usb_device_exchg_pins_err:1;
+        /** dis_usb_otg11_exchg_pins_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS.
+         */
+        uint32_t dis_usb_otg11_exchg_pins_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  Indicates a programming error of DIS_USB_JTAG.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** powerglitch_en_err : RO; bitpos: [10]; default: 0;
+         *  Indicates a programming error of POWERGLITCH_EN.
+         */
+        uint32_t powerglitch_en_err:1;
+        /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG.
+         */
+        uint32_t dis_usb_serial_jtag_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Indicates a programming error of DIS_FORCE_DOWNLOAD.
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS.
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of DIS_TWAI.
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Indicates a programming error of JTAG_SEL_ENABLE.
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Indicates a programming error of SOFT_DIS_JTAG.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DIS_PAD_JTAG.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_device_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFH.
+         */
+        uint32_t usb_device_drefh_err:2;
+        /** usb_otg11_drefh_err : RO; bitpos: [24:23]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFH.
+         */
+        uint32_t usb_otg11_drefh_err:2;
+        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of USB_PHY_SEL.
+         */
+        uint32_t usb_phy_sel_err:1;
+        /** huk_gen_state_low_err : RO; bitpos: [31:26]; default: 0;
+         *  Indicates a programming error of HUK_GEN_STATE_LOW.
+         */
+        uint32_t huk_gen_state_low_err:6;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** km_huk_gen_state_high_err : RO; bitpos: [2:0]; default: 0;
+         *  Indicates a programming error of HUK_GEN_STATE_HIGH.
+         */
+        uint32_t km_huk_gen_state_high_err:3;
+        /** km_rnd_switch_cycle_err : RO; bitpos: [4:3]; default: 0;
+         *  Indicates a programming error of KM_RND_SWITCH_CYCLE.
+         */
+        uint32_t km_rnd_switch_cycle_err:2;
+        /** km_deploy_only_once_err : RO; bitpos: [8:5]; default: 0;
+         *  Indicates a programming error of KM_DEPLOY_ONLY_ONCE.
+         */
+        uint32_t km_deploy_only_once_err:4;
+        /** force_use_key_manager_key_err : RO; bitpos: [12:9]; default: 0;
+         *  Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY.
+         */
+        uint32_t force_use_key_manager_key_err:4;
+        /** force_disable_sw_init_key_err : RO; bitpos: [13]; default: 0;
+         *  Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY.
+         */
+        uint32_t force_disable_sw_init_key_err:1;
+        /** xts_key_length_256_err : RO; bitpos: [14]; default: 0;
+         *  Indicates a programming error of XTS_KEY_LENGTH_256.
+         */
+        uint32_t xts_key_length_256_err:1;
+        uint32_t reserved_15:1;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of WDT_DELAY_SEL.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  Indicates a programming error of SPI_BOOT_CRYPT_CNT.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE0.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE1.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_KEY_REVOKE2.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_0.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_1.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_2.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_3.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_4.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  Indicates a programming error of KEY_PURPOSE_5.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** sec_dpa_level_err : RO; bitpos: [17:16]; default: 0;
+         *  Indicates a programming error of SEC_DPA_LEVEL.
+         */
+        uint32_t sec_dpa_level_err:2;
+        /** ecdsa_enable_soft_k_err : RO; bitpos: [18]; default: 0;
+         *  Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K.
+         */
+        uint32_t ecdsa_enable_soft_k_err:1;
+        /** crypt_dpa_enable_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of CRYPT_DPA_ENABLE.
+         */
+        uint32_t crypt_dpa_enable_err:1;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_EN.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        uint32_t reserved_22:1;
+        /** flash_type_err : RO; bitpos: [23]; default: 0;
+         *  Indicates a programming error of FLASH_TYPE.
+         */
+        uint32_t flash_type_err:1;
+        /** flash_page_size_err : RO; bitpos: [25:24]; default: 0;
+         *  Indicates a programming error of FLASH_PAGE_SIZE.
+         */
+        uint32_t flash_page_size_err:2;
+        /** flash_ecc_en_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of FLASH_ECC_EN.
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** dis_usb_otg_download_mode_err : RO; bitpos: [27]; default: 0;
+         *  Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_otg_download_mode_err:1;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  Indicates a programming error of FLASH_TPUW.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  Indicates a programming error of DIS_DOWNLOAD_MODE.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [1]; default: 0;
+         *  Indicates a programming error of DIS_DIRECT_BOOT.
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [2]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** lock_km_key_err : RO; bitpos: [3]; default: 0;
+         *  TBD
+         */
+        uint32_t lock_km_key_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  Indicates a programming error of ENABLE_SECURITY_DOWNLOAD.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of UART_PRINT_CONTROL.
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [8]; default: 0;
+         *  Indicates a programming error of FORCE_SEND_RESUME.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [24:9]; default: 0;
+         *  Indicates a programming error of SECURE VERSION.
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [25]; default: 0;
+         *  Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE.
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [26]; default: 0;
+         *  Indicates a programming error of HYS_EN_PAD.
+         */
+        uint32_t hys_en_pad_err:1;
+        /** dcdc_vset_err : RO; bitpos: [31:27]; default: 0;
+         *  Indicates a programming error of DCDC_VSET.
+         */
+        uint32_t dcdc_vset_err:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** pxa0_tieh_sel_0_err : RO; bitpos: [1:0]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_0.
+         */
+        uint32_t pxa0_tieh_sel_0_err:2;
+        /** pxa0_tieh_sel_1_err : RO; bitpos: [3:2]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_1.
+         */
+        uint32_t pxa0_tieh_sel_1_err:2;
+        /** pxa0_tieh_sel_2_err : RO; bitpos: [5:4]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_2.
+         */
+        uint32_t pxa0_tieh_sel_2_err:2;
+        /** pxa0_tieh_sel_3_err : RO; bitpos: [7:6]; default: 0;
+         *  Indicates a programming error of 0PXA_TIEH_SEL_3.
+         */
+        uint32_t pxa0_tieh_sel_3_err:2;
+        /** km_disable_deploy_mode_err : RO; bitpos: [11:8]; default: 0;
+         *  TBD.
+         */
+        uint32_t km_disable_deploy_mode_err:4;
+        /** usb_device_drefl_err : RO; bitpos: [13:12]; default: 0;
+         *  Indicates a programming error of USB_DEVICE_DREFL.
+         */
+        uint32_t usb_device_drefl_err:2;
+        /** usb_otg11_drefl_err : RO; bitpos: [15:14]; default: 0;
+         *  Indicates a programming error of USB_OTG11_DREFL.
+         */
+        uint32_t usb_otg11_drefl_err:2;
+        uint32_t reserved_16:2;
+        /** hp_pwr_src_sel_err : RO; bitpos: [18]; default: 0;
+         *  Indicates a programming error of HP_PWR_SRC_SEL.
+         */
+        uint32_t hp_pwr_src_sel_err:1;
+        /** dcdc_vset_en_err : RO; bitpos: [19]; default: 0;
+         *  Indicates a programming error of DCDC_VSET_EN.
+         */
+        uint32_t dcdc_vset_en_err:1;
+        /** dis_wdt_err : RO; bitpos: [20]; default: 0;
+         *  Indicates a programming error of DIS_WDT.
+         */
+        uint32_t dis_wdt_err:1;
+        /** dis_swd_err : RO; bitpos: [21]; default: 0;
+         *  Indicates a programming error of DIS_SWD.
+         */
+        uint32_t dis_swd_err:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_sys_err_num:3;
+        /** mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_sys_fail:1;
+        /** sys_part1_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_err_num:3;
+        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** key0_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+         *  key0 failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key1_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+         *  key1 failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key2_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+         *  key2 failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key3_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+         *  key3 failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key4_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+         *  key4 failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key5_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of key5 is reliable 1: Means that programming
+         *  key5 failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part2_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to force enable eFuse register configuration clock signal.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A:  programming operation command 0x5AA5: read operation command.
+         */
+        uint32_t op_code:16;
+        /** cfg_ecdsa_blk : R/W; bitpos: [19:16]; default: 0;
+         *  Configures which block to use for ECDSA key output.
+         */
+        uint32_t cfg_ecdsa_blk:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Indicates the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        /** cur_ecdsa_blk : RO; bitpos: [23:20]; default: 0;
+         *  Indicates which block is used for ECDSA key output.
+         */
+        uint32_t cur_ecdsa_blk:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 15;
+         *  Configures the waiting time of reading eFuse memory.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 9831;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 320;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 160;
+         *  Configures the active programming time.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to bypass reed solomon correction step.
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures block number of programming twice operation.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Set this bit to update multi-bit register signals.
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36720720;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
+/** Type of apb2otp_wr_dis register
+ *  eFuse apb2otp block0 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 write disable data.
+         */
+        uint32_t apb2otp_block0_wr_dis:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_wr_dis_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word1 Data */
+/** Type of apb2otp_blk0_backup1_w1 register
+ *  eFuse apb2otp block0 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word1 data.
+         */
+        uint32_t apb2otp_block0_backup1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word2 Data */
+/** Type of apb2otp_blk0_backup1_w2 register
+ *  eFuse apb2otp block0 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word2 data.
+         */
+        uint32_t apb2otp_block0_backup1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word3 Data */
+/** Type of apb2otp_blk0_backup1_w3 register
+ *  eFuse apb2otp block0 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word3 data.
+         */
+        uint32_t apb2otp_block0_backup1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word4 Data */
+/** Type of apb2otp_blk0_backup1_w4 register
+ *  eFuse apb2otp block0 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word4 data.
+         */
+        uint32_t apb2otp_block0_backup1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup1 Word5 Data */
+/** Type of apb2otp_blk0_backup1_w5 register
+ *  eFuse apb2otp block0 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup1 word5 data.
+         */
+        uint32_t apb2otp_block0_backup1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word1 Data */
+/** Type of apb2otp_blk0_backup2_w1 register
+ *  eFuse apb2otp block0 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word1 data.
+         */
+        uint32_t apb2otp_block0_backup2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word2 Data */
+/** Type of apb2otp_blk0_backup2_w2 register
+ *  eFuse apb2otp block0 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word2 data.
+         */
+        uint32_t apb2otp_block0_backup2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word3 Data */
+/** Type of apb2otp_blk0_backup2_w3 register
+ *  eFuse apb2otp block0 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word3 data.
+         */
+        uint32_t apb2otp_block0_backup2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word4 Data */
+/** Type of apb2otp_blk0_backup2_w4 register
+ *  eFuse apb2otp block0 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word4 data.
+         */
+        uint32_t apb2otp_block0_backup2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup2 Word5 Data */
+/** Type of apb2otp_blk0_backup2_w5 register
+ *  eFuse apb2otp block0 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup2 word5 data.
+         */
+        uint32_t apb2otp_block0_backup2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word1 Data */
+/** Type of apb2otp_blk0_backup3_w1 register
+ *  eFuse apb2otp block0 data register12.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word1 data.
+         */
+        uint32_t apb2otp_block0_backup3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word2 Data */
+/** Type of apb2otp_blk0_backup3_w2 register
+ *  eFuse apb2otp block0 data register13.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word2 data.
+         */
+        uint32_t apb2otp_block0_backup3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word3 Data */
+/** Type of apb2otp_blk0_backup3_w3 register
+ *  eFuse apb2otp block0 data register14.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word3 data.
+         */
+        uint32_t apb2otp_block0_backup3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word4 Data */
+/** Type of apb2otp_blk0_backup3_w4 register
+ *  eFuse apb2otp block0 data register15.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word4 data.
+         */
+        uint32_t apb2otp_block0_backup3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup3 Word5 Data */
+/** Type of apb2otp_blk0_backup3_w5 register
+ *  eFuse apb2otp block0 data register16.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup3 word5 data.
+         */
+        uint32_t apb2otp_block0_backup3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word1 Data */
+/** Type of apb2otp_blk0_backup4_w1 register
+ *  eFuse apb2otp block0 data register17.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word1 data.
+         */
+        uint32_t apb2otp_block0_backup4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word2 Data */
+/** Type of apb2otp_blk0_backup4_w2 register
+ *  eFuse apb2otp block0 data register18.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word2 data.
+         */
+        uint32_t apb2otp_block0_backup4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word3 Data */
+/** Type of apb2otp_blk0_backup4_w3 register
+ *  eFuse apb2otp block0 data register19.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word3 data.
+         */
+        uint32_t apb2otp_block0_backup4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word4 Data */
+/** Type of apb2otp_blk0_backup4_w4 register
+ *  eFuse apb2otp block0 data register20.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word4 data.
+         */
+        uint32_t apb2otp_block0_backup4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block0 Backup4 Word5 Data */
+/** Type of apb2otp_blk0_backup4_w5 register
+ *  eFuse apb2otp block0 data register21.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block0_backup4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block0 backup4 word5 data.
+         */
+        uint32_t apb2otp_block0_backup4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk0_backup4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word1 Data */
+/** Type of apb2otp_blk1_w1 register
+ *  eFuse apb2otp block1 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word1 data.
+         */
+        uint32_t apb2otp_block1_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word2 Data */
+/** Type of apb2otp_blk1_w2 register
+ *  eFuse apb2otp block1 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word2 data.
+         */
+        uint32_t apb2otp_block1_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word3 Data */
+/** Type of apb2otp_blk1_w3 register
+ *  eFuse apb2otp block1 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word3 data.
+         */
+        uint32_t apb2otp_block1_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word4 Data */
+/** Type of apb2otp_blk1_w4 register
+ *  eFuse apb2otp block1 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word4 data.
+         */
+        uint32_t apb2otp_block1_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word5 Data */
+/** Type of apb2otp_blk1_w5 register
+ *  eFuse apb2otp block1 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word5 data.
+         */
+        uint32_t apb2otp_block1_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word6 Data */
+/** Type of apb2otp_blk1_w6 register
+ *  eFuse apb2otp block1 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word6 data.
+         */
+        uint32_t apb2otp_block1_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word7 Data */
+/** Type of apb2otp_blk1_w7 register
+ *  eFuse apb2otp block1 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word7 data.
+         */
+        uint32_t apb2otp_block1_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word8 Data */
+/** Type of apb2otp_blk1_w8 register
+ *  eFuse apb2otp block1 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word8 data.
+         */
+        uint32_t apb2otp_block1_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block1 Word9 Data */
+/** Type of apb2otp_blk1_w9 register
+ *  eFuse apb2otp block1 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block1_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block1  word9 data.
+         */
+        uint32_t apb2otp_block1_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk1_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word1 Data */
+/** Type of apb2otp_blk2_w1 register
+ *  eFuse apb2otp block2 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word1 data.
+         */
+        uint32_t apb2otp_block2_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word2 Data */
+/** Type of apb2otp_blk2_w2 register
+ *  eFuse apb2otp block2 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word2 data.
+         */
+        uint32_t apb2otp_block2_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word3 Data */
+/** Type of apb2otp_blk2_w3 register
+ *  eFuse apb2otp block2 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word3 data.
+         */
+        uint32_t apb2otp_block2_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word4 Data */
+/** Type of apb2otp_blk2_w4 register
+ *  eFuse apb2otp block2 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word4 data.
+         */
+        uint32_t apb2otp_block2_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word5 Data */
+/** Type of apb2otp_blk2_w5 register
+ *  eFuse apb2otp block2 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word5 data.
+         */
+        uint32_t apb2otp_block2_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word6 Data */
+/** Type of apb2otp_blk2_w6 register
+ *  eFuse apb2otp block2 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word6 data.
+         */
+        uint32_t apb2otp_block2_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word7 Data */
+/** Type of apb2otp_blk2_w7 register
+ *  eFuse apb2otp block2 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word7 data.
+         */
+        uint32_t apb2otp_block2_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word8 Data */
+/** Type of apb2otp_blk2_w8 register
+ *  eFuse apb2otp block2 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word8 data.
+         */
+        uint32_t apb2otp_block2_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word9 Data */
+/** Type of apb2otp_blk2_w9 register
+ *  eFuse apb2otp block2 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word9 data.
+         */
+        uint32_t apb2otp_block2_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word10 Data */
+/** Type of apb2otp_blk2_w10 register
+ *  eFuse apb2otp block2 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word10 data.
+         */
+        uint32_t apb2otp_block2_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block2 Word11 Data */
+/** Type of apb2otp_blk2_w11 register
+ *  eFuse apb2otp block2 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block2_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block2 word11 data.
+         */
+        uint32_t apb2otp_block2_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk2_w11_reg_t;
+
+/** Type of apb2otp_blk10_w11 register
+ *  eFuse apb2otp block10 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word11 data.
+         */
+        uint32_t apb2otp_block10_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word1 Data */
+/** Type of apb2otp_blk3_w1 register
+ *  eFuse apb2otp block3 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word1 data.
+         */
+        uint32_t apb2otp_block3_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word2 Data */
+/** Type of apb2otp_blk3_w2 register
+ *  eFuse apb2otp block3 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word2 data.
+         */
+        uint32_t apb2otp_block3_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word3 Data */
+/** Type of apb2otp_blk3_w3 register
+ *  eFuse apb2otp block3 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word3 data.
+         */
+        uint32_t apb2otp_block3_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word4 Data */
+/** Type of apb2otp_blk3_w4 register
+ *  eFuse apb2otp block3 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word4 data.
+         */
+        uint32_t apb2otp_block3_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word5 Data */
+/** Type of apb2otp_blk3_w5 register
+ *  eFuse apb2otp block3 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word5 data.
+         */
+        uint32_t apb2otp_block3_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word6 Data */
+/** Type of apb2otp_blk3_w6 register
+ *  eFuse apb2otp block3 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word6 data.
+         */
+        uint32_t apb2otp_block3_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word7 Data */
+/** Type of apb2otp_blk3_w7 register
+ *  eFuse apb2otp block3 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word7 data.
+         */
+        uint32_t apb2otp_block3_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word8 Data */
+/** Type of apb2otp_blk3_w8 register
+ *  eFuse apb2otp block3 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word8 data.
+         */
+        uint32_t apb2otp_block3_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word9 Data */
+/** Type of apb2otp_blk3_w9 register
+ *  eFuse apb2otp block3 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word9 data.
+         */
+        uint32_t apb2otp_block3_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word10 Data */
+/** Type of apb2otp_blk3_w10 register
+ *  eFuse apb2otp block3 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word10 data.
+         */
+        uint32_t apb2otp_block3_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block3 Word11 Data */
+/** Type of apb2otp_blk3_w11 register
+ *  eFuse apb2otp block3 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block3_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block3 word11 data.
+         */
+        uint32_t apb2otp_block3_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk3_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word1 Data */
+/** Type of apb2otp_blk4_w1 register
+ *  eFuse apb2otp block4 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word1 data.
+         */
+        uint32_t apb2otp_block4_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word2 Data */
+/** Type of apb2otp_blk4_w2 register
+ *  eFuse apb2otp block4 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word2 data.
+         */
+        uint32_t apb2otp_block4_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word3 Data */
+/** Type of apb2otp_blk4_w3 register
+ *  eFuse apb2otp block4 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word3 data.
+         */
+        uint32_t apb2otp_block4_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word4 Data */
+/** Type of apb2otp_blk4_w4 register
+ *  eFuse apb2otp block4 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word4 data.
+         */
+        uint32_t apb2otp_block4_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word5 Data */
+/** Type of apb2otp_blk4_w5 register
+ *  eFuse apb2otp block4 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word5 data.
+         */
+        uint32_t apb2otp_block4_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word6 Data */
+/** Type of apb2otp_blk4_w6 register
+ *  eFuse apb2otp block4 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word6 data.
+         */
+        uint32_t apb2otp_block4_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word7 Data */
+/** Type of apb2otp_blk4_w7 register
+ *  eFuse apb2otp block4 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word7 data.
+         */
+        uint32_t apb2otp_block4_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word8 Data */
+/** Type of apb2otp_blk4_w8 register
+ *  eFuse apb2otp block4 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word8 data.
+         */
+        uint32_t apb2otp_block4_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word9 Data */
+/** Type of apb2otp_blk4_w9 register
+ *  eFuse apb2otp block4 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word9 data.
+         */
+        uint32_t apb2otp_block4_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word10 Data */
+/** Type of apb2otp_blk4_w10 register
+ *  eFuse apb2otp block4 data registe10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word10 data.
+         */
+        uint32_t apb2otp_block4_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block4 Word11 Data */
+/** Type of apb2otp_blk4_w11 register
+ *  eFuse apb2otp block4 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block4_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block4 word11 data.
+         */
+        uint32_t apb2otp_block4_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk4_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word1 Data */
+/** Type of apb2otp_blk5_w1 register
+ *  eFuse apb2otp block5 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word1 data.
+         */
+        uint32_t apb2otp_block5_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word2 Data */
+/** Type of apb2otp_blk5_w2 register
+ *  eFuse apb2otp block5 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word2 data.
+         */
+        uint32_t apb2otp_block5_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word3 Data */
+/** Type of apb2otp_blk5_w3 register
+ *  eFuse apb2otp block5 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word3 data.
+         */
+        uint32_t apb2otp_block5_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word4 Data */
+/** Type of apb2otp_blk5_w4 register
+ *  eFuse apb2otp block5 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word4 data.
+         */
+        uint32_t apb2otp_block5_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word5 Data */
+/** Type of apb2otp_blk5_w5 register
+ *  eFuse apb2otp block5 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word5 data.
+         */
+        uint32_t apb2otp_block5_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word6 Data */
+/** Type of apb2otp_blk5_w6 register
+ *  eFuse apb2otp block5 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word6 data.
+         */
+        uint32_t apb2otp_block5_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word7 Data */
+/** Type of apb2otp_blk5_w7 register
+ *  eFuse apb2otp block5 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word7 data.
+         */
+        uint32_t apb2otp_block5_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word8 Data */
+/** Type of apb2otp_blk5_w8 register
+ *  eFuse apb2otp block5 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word8 data.
+         */
+        uint32_t apb2otp_block5_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word9 Data */
+/** Type of apb2otp_blk5_w9 register
+ *  eFuse apb2otp block5 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word9 data.
+         */
+        uint32_t apb2otp_block5_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word10 Data */
+/** Type of apb2otp_blk5_w10 register
+ *  eFuse apb2otp block5 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word10 data.
+         */
+        uint32_t apb2otp_block5_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block5 Word11 Data */
+/** Type of apb2otp_blk5_w11 register
+ *  eFuse apb2otp block5 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block5_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block5 word11 data.
+         */
+        uint32_t apb2otp_block5_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk5_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word1 Data */
+/** Type of apb2otp_blk6_w1 register
+ *  eFuse apb2otp block6 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word1 data.
+         */
+        uint32_t apb2otp_block6_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word2 Data */
+/** Type of apb2otp_blk6_w2 register
+ *  eFuse apb2otp block6 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word2 data.
+         */
+        uint32_t apb2otp_block6_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word3 Data */
+/** Type of apb2otp_blk6_w3 register
+ *  eFuse apb2otp block6 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word3 data.
+         */
+        uint32_t apb2otp_block6_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word4 Data */
+/** Type of apb2otp_blk6_w4 register
+ *  eFuse apb2otp block6 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word4 data.
+         */
+        uint32_t apb2otp_block6_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word5 Data */
+/** Type of apb2otp_blk6_w5 register
+ *  eFuse apb2otp block6 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word5 data.
+         */
+        uint32_t apb2otp_block6_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word6 Data */
+/** Type of apb2otp_blk6_w6 register
+ *  eFuse apb2otp block6 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word6 data.
+         */
+        uint32_t apb2otp_block6_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word7 Data */
+/** Type of apb2otp_blk6_w7 register
+ *  eFuse apb2otp block6 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word7 data.
+         */
+        uint32_t apb2otp_block6_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word8 Data */
+/** Type of apb2otp_blk6_w8 register
+ *  eFuse apb2otp block6 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word8 data.
+         */
+        uint32_t apb2otp_block6_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word9 Data */
+/** Type of apb2otp_blk6_w9 register
+ *  eFuse apb2otp block6 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word9 data.
+         */
+        uint32_t apb2otp_block6_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word10 Data */
+/** Type of apb2otp_blk6_w10 register
+ *  eFuse apb2otp block6 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word10 data.
+         */
+        uint32_t apb2otp_block6_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block6 Word11 Data */
+/** Type of apb2otp_blk6_w11 register
+ *  eFuse apb2otp block6 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block6_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block6 word11 data.
+         */
+        uint32_t apb2otp_block6_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk6_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word1 Data */
+/** Type of apb2otp_blk7_w1 register
+ *  eFuse apb2otp block7 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word1 data.
+         */
+        uint32_t apb2otp_block7_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word2 Data */
+/** Type of apb2otp_blk7_w2 register
+ *  eFuse apb2otp block7 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word2 data.
+         */
+        uint32_t apb2otp_block7_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word3 Data */
+/** Type of apb2otp_blk7_w3 register
+ *  eFuse apb2otp block7 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word3 data.
+         */
+        uint32_t apb2otp_block7_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word4 Data */
+/** Type of apb2otp_blk7_w4 register
+ *  eFuse apb2otp block7 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word4 data.
+         */
+        uint32_t apb2otp_block7_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word5 Data */
+/** Type of apb2otp_blk7_w5 register
+ *  eFuse apb2otp block7 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word5 data.
+         */
+        uint32_t apb2otp_block7_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word6 Data */
+/** Type of apb2otp_blk7_w6 register
+ *  eFuse apb2otp block7 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word6 data.
+         */
+        uint32_t apb2otp_block7_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word7 Data */
+/** Type of apb2otp_blk7_w7 register
+ *  eFuse apb2otp block7 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word7 data.
+         */
+        uint32_t apb2otp_block7_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word8 Data */
+/** Type of apb2otp_blk7_w8 register
+ *  eFuse apb2otp block7 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word8 data.
+         */
+        uint32_t apb2otp_block7_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word9 Data */
+/** Type of apb2otp_blk7_w9 register
+ *  eFuse apb2otp block7 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word9 data.
+         */
+        uint32_t apb2otp_block7_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word10 Data */
+/** Type of apb2otp_blk7_w10 register
+ *  eFuse apb2otp block7 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word10 data.
+         */
+        uint32_t apb2otp_block7_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block7 Word11 Data */
+/** Type of apb2otp_blk7_w11 register
+ *  eFuse apb2otp block7 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block7_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block7 word11 data.
+         */
+        uint32_t apb2otp_block7_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk7_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word1 Data */
+/** Type of apb2otp_blk8_w1 register
+ *  eFuse apb2otp block8 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word1 data.
+         */
+        uint32_t apb2otp_block8_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word2 Data */
+/** Type of apb2otp_blk8_w2 register
+ *  eFuse apb2otp block8 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word2 data.
+         */
+        uint32_t apb2otp_block8_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word3 Data */
+/** Type of apb2otp_blk8_w3 register
+ *  eFuse apb2otp block8 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word3 data.
+         */
+        uint32_t apb2otp_block8_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word4 Data */
+/** Type of apb2otp_blk8_w4 register
+ *  eFuse apb2otp block8 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word4 data.
+         */
+        uint32_t apb2otp_block8_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word5 Data */
+/** Type of apb2otp_blk8_w5 register
+ *  eFuse apb2otp block8 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word5 data.
+         */
+        uint32_t apb2otp_block8_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word6 Data */
+/** Type of apb2otp_blk8_w6 register
+ *  eFuse apb2otp block8 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word6 data.
+         */
+        uint32_t apb2otp_block8_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word7 Data */
+/** Type of apb2otp_blk8_w7 register
+ *  eFuse apb2otp block8 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word7 data.
+         */
+        uint32_t apb2otp_block8_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word8 Data */
+/** Type of apb2otp_blk8_w8 register
+ *  eFuse apb2otp block8 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word8 data.
+         */
+        uint32_t apb2otp_block8_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word9 Data */
+/** Type of apb2otp_blk8_w9 register
+ *  eFuse apb2otp block8 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word9 data.
+         */
+        uint32_t apb2otp_block8_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word10 Data */
+/** Type of apb2otp_blk8_w10 register
+ *  eFuse apb2otp block8 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word10 data.
+         */
+        uint32_t apb2otp_block8_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block8 Word11 Data */
+/** Type of apb2otp_blk8_w11 register
+ *  eFuse apb2otp block8 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block8_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block8 word11 data.
+         */
+        uint32_t apb2otp_block8_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk8_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word1 Data */
+/** Type of apb2otp_blk9_w1 register
+ *  eFuse apb2otp block9 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word1 data.
+         */
+        uint32_t apb2otp_block9_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word2 Data */
+/** Type of apb2otp_blk9_w2 register
+ *  eFuse apb2otp block9 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word2 data.
+         */
+        uint32_t apb2otp_block9_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word3 Data */
+/** Type of apb2otp_blk9_w3 register
+ *  eFuse apb2otp block9 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word3 data.
+         */
+        uint32_t apb2otp_block9_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word4 Data */
+/** Type of apb2otp_blk9_w4 register
+ *  eFuse apb2otp block9 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word4 data.
+         */
+        uint32_t apb2otp_block9_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word5 Data */
+/** Type of apb2otp_blk9_w5 register
+ *  eFuse apb2otp block9 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word5 data.
+         */
+        uint32_t apb2otp_block9_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word6 Data */
+/** Type of apb2otp_blk9_w6 register
+ *  eFuse apb2otp block9 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word6 data.
+         */
+        uint32_t apb2otp_block9_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word7 Data */
+/** Type of apb2otp_blk9_w7 register
+ *  eFuse apb2otp block9 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word7 data.
+         */
+        uint32_t apb2otp_block9_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word8 Data */
+/** Type of apb2otp_blk9_w8 register
+ *  eFuse apb2otp block9 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word8 data.
+         */
+        uint32_t apb2otp_block9_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word9 Data */
+/** Type of apb2otp_blk9_w9 register
+ *  eFuse apb2otp block9 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word9 data.
+         */
+        uint32_t apb2otp_block9_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word10 Data */
+/** Type of apb2otp_blk9_w10 register
+ *  eFuse apb2otp block9 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word10 data.
+         */
+        uint32_t apb2otp_block9_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block9 Word11 Data */
+/** Type of apb2otp_blk9_w11 register
+ *  eFuse apb2otp block9 data register11.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block9_w11 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block9 word11 data.
+         */
+        uint32_t apb2otp_block9_w11:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk9_w11_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word1 Data */
+/** Type of apb2otp_blk10_w1 register
+ *  eFuse apb2otp block10 data register1.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w1 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word1 data.
+         */
+        uint32_t apb2otp_block10_w1:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w1_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word2 Data */
+/** Type of apb2otp_blk10_w2 register
+ *  eFuse apb2otp block10 data register2.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w2 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word2 data.
+         */
+        uint32_t apb2otp_block10_w2:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w2_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word3 Data */
+/** Type of apb2otp_blk10_w3 register
+ *  eFuse apb2otp block10 data register3.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w3 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word3 data.
+         */
+        uint32_t apb2otp_block10_w3:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w3_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word4 Data */
+/** Type of apb2otp_blk10_w4 register
+ *  eFuse apb2otp block10 data register4.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w4 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word4 data.
+         */
+        uint32_t apb2otp_block10_w4:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w4_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word5 Data */
+/** Type of apb2otp_blk10_w5 register
+ *  eFuse apb2otp block10 data register5.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w5 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word5 data.
+         */
+        uint32_t apb2otp_block10_w5:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w5_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word6 Data */
+/** Type of apb2otp_blk10_w6 register
+ *  eFuse apb2otp block10 data register6.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w6 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word6 data.
+         */
+        uint32_t apb2otp_block10_w6:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w6_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word7 Data */
+/** Type of apb2otp_blk10_w7 register
+ *  eFuse apb2otp block10 data register7.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w7 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word7 data.
+         */
+        uint32_t apb2otp_block10_w7:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w7_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word8 Data */
+/** Type of apb2otp_blk10_w8 register
+ *  eFuse apb2otp block10 data register8.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w8 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word8 data.
+         */
+        uint32_t apb2otp_block10_w8:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w8_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word9 Data */
+/** Type of apb2otp_blk10_w9 register
+ *  eFuse apb2otp block10 data register9.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block10_w9 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word9 data.
+         */
+        uint32_t apb2otp_block10_w9:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w9_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Block10 Word10 Data */
+/** Type of apb2otp_blk10_w10 register
+ *  eFuse apb2otp block10 data register10.
+ */
+typedef union {
+    struct {
+        /** apb2otp_block19_w10 : RO; bitpos: [31:0]; default: 0;
+         *  Otp block10 word10 data.
+         */
+        uint32_t apb2otp_block19_w10:32;
+    };
+    uint32_t val;
+} efuse_apb2otp_blk10_w10_reg_t;
+
+
+/** Group: EFUSE_APB2OTP Function Enable Signal */
+/** Type of apb2otp_en register
+ *  eFuse apb2otp enable configuration register.
+ */
+typedef union {
+    struct {
+        /** apb2otp_apb2otp_en : R/W; bitpos: [0]; default: 0;
+         *  Apb2otp mode enable signal.
+         */
+        uint32_t apb2otp_apb2otp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_apb2otp_en_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_sys_0_reg_t rd_mac_sys_0;
+    volatile efuse_rd_mac_sys_1_reg_t rd_mac_sys_1;
+    volatile efuse_rd_mac_sys_2_reg_t rd_mac_sys_2;
+    volatile efuse_rd_mac_sys_3_reg_t rd_mac_sys_3;
+    volatile efuse_rd_mac_sys_4_reg_t rd_mac_sys_4;
+    volatile efuse_rd_mac_sys_5_reg_t rd_mac_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_190[12];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_200[384];
+    volatile efuse_apb2otp_wr_dis_reg_t apb2otp_wr_dis;
+    volatile efuse_apb2otp_blk0_backup1_w1_reg_t apb2otp_blk0_backup1_w1;
+    volatile efuse_apb2otp_blk0_backup1_w2_reg_t apb2otp_blk0_backup1_w2;
+    volatile efuse_apb2otp_blk0_backup1_w3_reg_t apb2otp_blk0_backup1_w3;
+    volatile efuse_apb2otp_blk0_backup1_w4_reg_t apb2otp_blk0_backup1_w4;
+    volatile efuse_apb2otp_blk0_backup1_w5_reg_t apb2otp_blk0_backup1_w5;
+    volatile efuse_apb2otp_blk0_backup2_w1_reg_t apb2otp_blk0_backup2_w1;
+    volatile efuse_apb2otp_blk0_backup2_w2_reg_t apb2otp_blk0_backup2_w2;
+    volatile efuse_apb2otp_blk0_backup2_w3_reg_t apb2otp_blk0_backup2_w3;
+    volatile efuse_apb2otp_blk0_backup2_w4_reg_t apb2otp_blk0_backup2_w4;
+    volatile efuse_apb2otp_blk0_backup2_w5_reg_t apb2otp_blk0_backup2_w5;
+    volatile efuse_apb2otp_blk0_backup3_w1_reg_t apb2otp_blk0_backup3_w1;
+    volatile efuse_apb2otp_blk0_backup3_w2_reg_t apb2otp_blk0_backup3_w2;
+    volatile efuse_apb2otp_blk0_backup3_w3_reg_t apb2otp_blk0_backup3_w3;
+    volatile efuse_apb2otp_blk0_backup3_w4_reg_t apb2otp_blk0_backup3_w4;
+    volatile efuse_apb2otp_blk0_backup3_w5_reg_t apb2otp_blk0_backup3_w5;
+    volatile efuse_apb2otp_blk0_backup4_w1_reg_t apb2otp_blk0_backup4_w1;
+    volatile efuse_apb2otp_blk0_backup4_w2_reg_t apb2otp_blk0_backup4_w2;
+    volatile efuse_apb2otp_blk0_backup4_w3_reg_t apb2otp_blk0_backup4_w3;
+    volatile efuse_apb2otp_blk0_backup4_w4_reg_t apb2otp_blk0_backup4_w4;
+    volatile efuse_apb2otp_blk0_backup4_w5_reg_t apb2otp_blk0_backup4_w5;
+    volatile efuse_apb2otp_blk1_w1_reg_t apb2otp_blk1_w1;
+    volatile efuse_apb2otp_blk1_w2_reg_t apb2otp_blk1_w2;
+    volatile efuse_apb2otp_blk1_w3_reg_t apb2otp_blk1_w3;
+    volatile efuse_apb2otp_blk1_w4_reg_t apb2otp_blk1_w4;
+    volatile efuse_apb2otp_blk1_w5_reg_t apb2otp_blk1_w5;
+    volatile efuse_apb2otp_blk1_w6_reg_t apb2otp_blk1_w6;
+    volatile efuse_apb2otp_blk1_w7_reg_t apb2otp_blk1_w7;
+    volatile efuse_apb2otp_blk1_w8_reg_t apb2otp_blk1_w8;
+    volatile efuse_apb2otp_blk1_w9_reg_t apb2otp_blk1_w9;
+    volatile efuse_apb2otp_blk2_w1_reg_t apb2otp_blk2_w1;
+    volatile efuse_apb2otp_blk2_w2_reg_t apb2otp_blk2_w2;
+    volatile efuse_apb2otp_blk2_w3_reg_t apb2otp_blk2_w3;
+    volatile efuse_apb2otp_blk2_w4_reg_t apb2otp_blk2_w4;
+    volatile efuse_apb2otp_blk2_w5_reg_t apb2otp_blk2_w5;
+    volatile efuse_apb2otp_blk2_w6_reg_t apb2otp_blk2_w6;
+    volatile efuse_apb2otp_blk2_w7_reg_t apb2otp_blk2_w7;
+    volatile efuse_apb2otp_blk2_w8_reg_t apb2otp_blk2_w8;
+    volatile efuse_apb2otp_blk2_w9_reg_t apb2otp_blk2_w9;
+    volatile efuse_apb2otp_blk2_w10_reg_t apb2otp_blk2_w10;
+    volatile efuse_apb2otp_blk2_w11_reg_t apb2otp_blk2_w11;
+    volatile efuse_apb2otp_blk3_w1_reg_t apb2otp_blk3_w1;
+    volatile efuse_apb2otp_blk3_w2_reg_t apb2otp_blk3_w2;
+    volatile efuse_apb2otp_blk3_w3_reg_t apb2otp_blk3_w3;
+    volatile efuse_apb2otp_blk3_w4_reg_t apb2otp_blk3_w4;
+    volatile efuse_apb2otp_blk3_w5_reg_t apb2otp_blk3_w5;
+    volatile efuse_apb2otp_blk3_w6_reg_t apb2otp_blk3_w6;
+    volatile efuse_apb2otp_blk3_w7_reg_t apb2otp_blk3_w7;
+    volatile efuse_apb2otp_blk3_w8_reg_t apb2otp_blk3_w8;
+    volatile efuse_apb2otp_blk3_w9_reg_t apb2otp_blk3_w9;
+    volatile efuse_apb2otp_blk3_w10_reg_t apb2otp_blk3_w10;
+    volatile efuse_apb2otp_blk3_w11_reg_t apb2otp_blk3_w11;
+    volatile efuse_apb2otp_blk4_w1_reg_t apb2otp_blk4_w1;
+    volatile efuse_apb2otp_blk4_w2_reg_t apb2otp_blk4_w2;
+    volatile efuse_apb2otp_blk4_w3_reg_t apb2otp_blk4_w3;
+    volatile efuse_apb2otp_blk4_w4_reg_t apb2otp_blk4_w4;
+    volatile efuse_apb2otp_blk4_w5_reg_t apb2otp_blk4_w5;
+    volatile efuse_apb2otp_blk4_w6_reg_t apb2otp_blk4_w6;
+    volatile efuse_apb2otp_blk4_w7_reg_t apb2otp_blk4_w7;
+    volatile efuse_apb2otp_blk4_w8_reg_t apb2otp_blk4_w8;
+    volatile efuse_apb2otp_blk4_w9_reg_t apb2otp_blk4_w9;
+    volatile efuse_apb2otp_blk4_w10_reg_t apb2otp_blk4_w10;
+    volatile efuse_apb2otp_blk4_w11_reg_t apb2otp_blk4_w11;
+    volatile efuse_apb2otp_blk5_w1_reg_t apb2otp_blk5_w1;
+    volatile efuse_apb2otp_blk5_w2_reg_t apb2otp_blk5_w2;
+    volatile efuse_apb2otp_blk5_w3_reg_t apb2otp_blk5_w3;
+    volatile efuse_apb2otp_blk5_w4_reg_t apb2otp_blk5_w4;
+    volatile efuse_apb2otp_blk5_w5_reg_t apb2otp_blk5_w5;
+    volatile efuse_apb2otp_blk5_w6_reg_t apb2otp_blk5_w6;
+    volatile efuse_apb2otp_blk5_w7_reg_t apb2otp_blk5_w7;
+    volatile efuse_apb2otp_blk5_w8_reg_t apb2otp_blk5_w8;
+    volatile efuse_apb2otp_blk5_w9_reg_t apb2otp_blk5_w9;
+    volatile efuse_apb2otp_blk5_w10_reg_t apb2otp_blk5_w10;
+    volatile efuse_apb2otp_blk5_w11_reg_t apb2otp_blk5_w11;
+    volatile efuse_apb2otp_blk6_w1_reg_t apb2otp_blk6_w1;
+    volatile efuse_apb2otp_blk6_w2_reg_t apb2otp_blk6_w2;
+    volatile efuse_apb2otp_blk6_w3_reg_t apb2otp_blk6_w3;
+    volatile efuse_apb2otp_blk6_w4_reg_t apb2otp_blk6_w4;
+    volatile efuse_apb2otp_blk6_w5_reg_t apb2otp_blk6_w5;
+    volatile efuse_apb2otp_blk6_w6_reg_t apb2otp_blk6_w6;
+    volatile efuse_apb2otp_blk6_w7_reg_t apb2otp_blk6_w7;
+    volatile efuse_apb2otp_blk6_w8_reg_t apb2otp_blk6_w8;
+    volatile efuse_apb2otp_blk6_w9_reg_t apb2otp_blk6_w9;
+    volatile efuse_apb2otp_blk6_w10_reg_t apb2otp_blk6_w10;
+    volatile efuse_apb2otp_blk6_w11_reg_t apb2otp_blk6_w11;
+    volatile efuse_apb2otp_blk7_w1_reg_t apb2otp_blk7_w1;
+    volatile efuse_apb2otp_blk7_w2_reg_t apb2otp_blk7_w2;
+    volatile efuse_apb2otp_blk7_w3_reg_t apb2otp_blk7_w3;
+    volatile efuse_apb2otp_blk7_w4_reg_t apb2otp_blk7_w4;
+    volatile efuse_apb2otp_blk7_w5_reg_t apb2otp_blk7_w5;
+    volatile efuse_apb2otp_blk7_w6_reg_t apb2otp_blk7_w6;
+    volatile efuse_apb2otp_blk7_w7_reg_t apb2otp_blk7_w7;
+    volatile efuse_apb2otp_blk7_w8_reg_t apb2otp_blk7_w8;
+    volatile efuse_apb2otp_blk7_w9_reg_t apb2otp_blk7_w9;
+    volatile efuse_apb2otp_blk7_w10_reg_t apb2otp_blk7_w10;
+    volatile efuse_apb2otp_blk7_w11_reg_t apb2otp_blk7_w11;
+    volatile efuse_apb2otp_blk8_w1_reg_t apb2otp_blk8_w1;
+    volatile efuse_apb2otp_blk8_w2_reg_t apb2otp_blk8_w2;
+    volatile efuse_apb2otp_blk8_w3_reg_t apb2otp_blk8_w3;
+    volatile efuse_apb2otp_blk8_w4_reg_t apb2otp_blk8_w4;
+    volatile efuse_apb2otp_blk8_w5_reg_t apb2otp_blk8_w5;
+    volatile efuse_apb2otp_blk8_w6_reg_t apb2otp_blk8_w6;
+    volatile efuse_apb2otp_blk8_w7_reg_t apb2otp_blk8_w7;
+    volatile efuse_apb2otp_blk8_w8_reg_t apb2otp_blk8_w8;
+    volatile efuse_apb2otp_blk8_w9_reg_t apb2otp_blk8_w9;
+    volatile efuse_apb2otp_blk8_w10_reg_t apb2otp_blk8_w10;
+    volatile efuse_apb2otp_blk8_w11_reg_t apb2otp_blk8_w11;
+    volatile efuse_apb2otp_blk9_w1_reg_t apb2otp_blk9_w1;
+    volatile efuse_apb2otp_blk9_w2_reg_t apb2otp_blk9_w2;
+    volatile efuse_apb2otp_blk9_w3_reg_t apb2otp_blk9_w3;
+    volatile efuse_apb2otp_blk9_w4_reg_t apb2otp_blk9_w4;
+    volatile efuse_apb2otp_blk9_w5_reg_t apb2otp_blk9_w5;
+    volatile efuse_apb2otp_blk9_w6_reg_t apb2otp_blk9_w6;
+    volatile efuse_apb2otp_blk9_w7_reg_t apb2otp_blk9_w7;
+    volatile efuse_apb2otp_blk9_w8_reg_t apb2otp_blk9_w8;
+    volatile efuse_apb2otp_blk9_w9_reg_t apb2otp_blk9_w9;
+    volatile efuse_apb2otp_blk9_w10_reg_t apb2otp_blk9_w10;
+    volatile efuse_apb2otp_blk9_w11_reg_t apb2otp_blk9_w11;
+    volatile efuse_apb2otp_blk10_w1_reg_t apb2otp_blk10_w1;
+    volatile efuse_apb2otp_blk10_w2_reg_t apb2otp_blk10_w2;
+    volatile efuse_apb2otp_blk10_w3_reg_t apb2otp_blk10_w3;
+    volatile efuse_apb2otp_blk10_w4_reg_t apb2otp_blk10_w4;
+    volatile efuse_apb2otp_blk10_w5_reg_t apb2otp_blk10_w5;
+    volatile efuse_apb2otp_blk10_w6_reg_t apb2otp_blk10_w6;
+    volatile efuse_apb2otp_blk10_w7_reg_t apb2otp_blk10_w7;
+    volatile efuse_apb2otp_blk10_w8_reg_t apb2otp_blk10_w8;
+    volatile efuse_apb2otp_blk10_w9_reg_t apb2otp_blk10_w9;
+    volatile efuse_apb2otp_blk10_w10_reg_t apb2otp_blk10_w10;
+    volatile efuse_apb2otp_blk10_w11_reg_t apb2otp_blk10_w11;
+    uint32_t reserved_a04;
+    volatile efuse_apb2otp_en_reg_t apb2otp_en;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0xa0c, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/emac_dma_struct.h b/components/soc/esp32p4/register/soc/emac_dma_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/emac_dma_struct.h
rename to components/soc/esp32p4/register/soc/emac_dma_struct.h
diff --git a/components/soc/esp32p4/include/soc/emac_mac_struct.h b/components/soc/esp32p4/register/soc/emac_mac_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/emac_mac_struct.h
rename to components/soc/esp32p4/register/soc/emac_mac_struct.h
diff --git a/components/soc/esp32p4/include/soc/gpio_ext_reg.h b/components/soc/esp32p4/register/soc/gpio_ext_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/gpio_ext_reg.h
rename to components/soc/esp32p4/register/soc/gpio_ext_reg.h
diff --git a/components/soc/esp32p4/include/soc/gpio_ext_struct.h b/components/soc/esp32p4/register/soc/gpio_ext_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/gpio_ext_struct.h
rename to components/soc/esp32p4/register/soc/gpio_ext_struct.h
diff --git a/components/soc/esp32p4/register/soc/gpio_reg.h b/components/soc/esp32p4/register/soc/gpio_reg.h
new file mode 100644
index 00000000000..06b16129929
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/gpio_reg.h
@@ -0,0 +1,12210 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO_BT_SELECT_REG register
+ *  GPIO bit select register
+ */
+#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0)
+/** GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0;
+ *  GPIO bit select register
+ */
+#define GPIO_BT_SEL    0xFFFFFFFFU
+#define GPIO_BT_SEL_M  (GPIO_BT_SEL_V << GPIO_BT_SEL_S)
+#define GPIO_BT_SEL_V  0xFFFFFFFFU
+#define GPIO_BT_SEL_S  0
+
+/** GPIO_OUT_REG register
+ *  GPIO output register for GPIO0-31
+ */
+#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
+/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO output register for GPIO0-31
+ */
+#define GPIO_OUT_DATA_ORIG    0xFFFFFFFFU
+#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
+#define GPIO_OUT_DATA_ORIG_V  0xFFFFFFFFU
+#define GPIO_OUT_DATA_ORIG_S  0
+
+/** GPIO_OUT_W1TS_REG register
+ *  GPIO output set register for GPIO0-31
+ */
+#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
+/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output set register for GPIO0-31
+ */
+#define GPIO_OUT_W1TS    0xFFFFFFFFU
+#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
+#define GPIO_OUT_W1TS_V  0xFFFFFFFFU
+#define GPIO_OUT_W1TS_S  0
+
+/** GPIO_OUT_W1TC_REG register
+ *  GPIO output clear register for GPIO0-31
+ */
+#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
+/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output clear register for GPIO0-31
+ */
+#define GPIO_OUT_W1TC    0xFFFFFFFFU
+#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
+#define GPIO_OUT_W1TC_V  0xFFFFFFFFU
+#define GPIO_OUT_W1TC_S  0
+
+/** GPIO_OUT1_REG register
+ *  GPIO output register for GPIO32-56
+ */
+#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10)
+/** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO output register for GPIO32-56
+ */
+#define GPIO_OUT1_DATA_ORIG    0x01FFFFFFU
+#define GPIO_OUT1_DATA_ORIG_M  (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S)
+#define GPIO_OUT1_DATA_ORIG_V  0x01FFFFFFU
+#define GPIO_OUT1_DATA_ORIG_S  0
+
+/** GPIO_OUT1_W1TS_REG register
+ *  GPIO output set register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14)
+/** GPIO_OUT1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output set register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TS    0x01FFFFFFU
+#define GPIO_OUT1_W1TS_M  (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S)
+#define GPIO_OUT1_W1TS_V  0x01FFFFFFU
+#define GPIO_OUT1_W1TS_S  0
+
+/** GPIO_OUT1_W1TC_REG register
+ *  GPIO output clear register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18)
+/** GPIO_OUT1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output clear register for GPIO32-56
+ */
+#define GPIO_OUT1_W1TC    0x01FFFFFFU
+#define GPIO_OUT1_W1TC_M  (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S)
+#define GPIO_OUT1_W1TC_V  0x01FFFFFFU
+#define GPIO_OUT1_W1TC_S  0
+
+/** GPIO_ENABLE_REG register
+ *  GPIO output enable register for GPIO0-31
+ */
+#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20)
+/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO output enable register for GPIO0-31
+ */
+#define GPIO_ENABLE_DATA    0xFFFFFFFFU
+#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
+#define GPIO_ENABLE_DATA_V  0xFFFFFFFFU
+#define GPIO_ENABLE_DATA_S  0
+
+/** GPIO_ENABLE_W1TS_REG register
+ *  GPIO output enable set register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24)
+/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output enable set register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TS    0xFFFFFFFFU
+#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
+#define GPIO_ENABLE_W1TS_V  0xFFFFFFFFU
+#define GPIO_ENABLE_W1TS_S  0
+
+/** GPIO_ENABLE_W1TC_REG register
+ *  GPIO output enable clear register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28)
+/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO output enable clear register for GPIO0-31
+ */
+#define GPIO_ENABLE_W1TC    0xFFFFFFFFU
+#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
+#define GPIO_ENABLE_W1TC_V  0xFFFFFFFFU
+#define GPIO_ENABLE_W1TC_S  0
+
+/** GPIO_ENABLE1_REG register
+ *  GPIO output enable register for GPIO32-56
+ */
+#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c)
+/** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO output enable register for GPIO32-56
+ */
+#define GPIO_ENABLE1_DATA    0x01FFFFFFU
+#define GPIO_ENABLE1_DATA_M  (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S)
+#define GPIO_ENABLE1_DATA_V  0x01FFFFFFU
+#define GPIO_ENABLE1_DATA_S  0
+
+/** GPIO_ENABLE1_W1TS_REG register
+ *  GPIO output enable set register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30)
+/** GPIO_ENABLE1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output enable set register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TS    0x01FFFFFFU
+#define GPIO_ENABLE1_W1TS_M  (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S)
+#define GPIO_ENABLE1_W1TS_V  0x01FFFFFFU
+#define GPIO_ENABLE1_W1TS_S  0
+
+/** GPIO_ENABLE1_W1TC_REG register
+ *  GPIO output enable clear register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34)
+/** GPIO_ENABLE1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO output enable clear register for GPIO32-56
+ */
+#define GPIO_ENABLE1_W1TC    0x01FFFFFFU
+#define GPIO_ENABLE1_W1TC_M  (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S)
+#define GPIO_ENABLE1_W1TC_V  0x01FFFFFFU
+#define GPIO_ENABLE1_W1TC_S  0
+
+/** GPIO_STRAP_REG register
+ *  pad strapping register
+ */
+#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38)
+/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
+ *  pad strapping register
+ */
+#define GPIO_STRAPPING    0x0000FFFFU
+#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
+#define GPIO_STRAPPING_V  0x0000FFFFU
+#define GPIO_STRAPPING_S  0
+
+/** GPIO_IN_REG register
+ *  GPIO input register for GPIO0-31
+ */
+#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c)
+/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  GPIO input register for GPIO0-31
+ */
+#define GPIO_IN_DATA_NEXT    0xFFFFFFFFU
+#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
+#define GPIO_IN_DATA_NEXT_V  0xFFFFFFFFU
+#define GPIO_IN_DATA_NEXT_S  0
+
+/** GPIO_IN1_REG register
+ *  GPIO input register for GPIO32-56
+ */
+#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40)
+/** GPIO_IN1_DATA_NEXT : RO; bitpos: [24:0]; default: 0;
+ *  GPIO input register for GPIO32-56
+ */
+#define GPIO_IN1_DATA_NEXT    0x01FFFFFFU
+#define GPIO_IN1_DATA_NEXT_M  (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S)
+#define GPIO_IN1_DATA_NEXT_V  0x01FFFFFFU
+#define GPIO_IN1_DATA_NEXT_S  0
+
+/** GPIO_STATUS_REG register
+ *  GPIO interrupt status register for GPIO0-31
+ */
+#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44)
+/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status register for GPIO0-31
+ */
+#define GPIO_STATUS_INTERRUPT    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
+#define GPIO_STATUS_INTERRUPT_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_S  0
+
+/** GPIO_STATUS_W1TS_REG register
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48)
+/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TS    0xFFFFFFFFU
+#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
+#define GPIO_STATUS_W1TS_V  0xFFFFFFFFU
+#define GPIO_STATUS_W1TS_S  0
+
+/** GPIO_STATUS_W1TC_REG register
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c)
+/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+#define GPIO_STATUS_W1TC    0xFFFFFFFFU
+#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
+#define GPIO_STATUS_W1TC_V  0xFFFFFFFFU
+#define GPIO_STATUS_W1TC_S  0
+
+/** GPIO_STATUS1_REG register
+ *  GPIO interrupt status register for GPIO32-56
+ */
+#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50)
+/** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status register for GPIO32-56
+ */
+#define GPIO_STATUS1_INTERRUPT    0x01FFFFFFU
+#define GPIO_STATUS1_INTERRUPT_M  (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S)
+#define GPIO_STATUS1_INTERRUPT_V  0x01FFFFFFU
+#define GPIO_STATUS1_INTERRUPT_S  0
+
+/** GPIO_STATUS1_W1TS_REG register
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54)
+/** GPIO_STATUS1_W1TS : WT; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TS    0x01FFFFFFU
+#define GPIO_STATUS1_W1TS_M  (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S)
+#define GPIO_STATUS1_W1TS_V  0x01FFFFFFU
+#define GPIO_STATUS1_W1TS_S  0
+
+/** GPIO_STATUS1_W1TC_REG register
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58)
+/** GPIO_STATUS1_W1TC : WT; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+#define GPIO_STATUS1_W1TC    0x01FFFFFFU
+#define GPIO_STATUS1_W1TC_M  (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S)
+#define GPIO_STATUS1_W1TC_V  0x01FFFFFFU
+#define GPIO_STATUS1_W1TC_S  0
+
+/** GPIO_INTR_0_REG register
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+#define GPIO_INTR_0_REG (DR_REG_GPIO_BASE + 0x5c)
+/** GPIO_INT_0 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+#define GPIO_INT_0    0xFFFFFFFFU
+#define GPIO_INT_0_M  (GPIO_INT_0_V << GPIO_INT_0_S)
+#define GPIO_INT_0_V  0xFFFFFFFFU
+#define GPIO_INT_0_S  0
+
+/** GPIO_INTR1_0_REG register
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+#define GPIO_INTR1_0_REG (DR_REG_GPIO_BASE + 0x60)
+/** GPIO_INT1_0 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+#define GPIO_INT1_0    0x01FFFFFFU
+#define GPIO_INT1_0_M  (GPIO_INT1_0_V << GPIO_INT1_0_S)
+#define GPIO_INT1_0_V  0x01FFFFFFU
+#define GPIO_INT1_0_S  0
+
+/** GPIO_INTR_1_REG register
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+#define GPIO_INTR_1_REG (DR_REG_GPIO_BASE + 0x64)
+/** GPIO_INT_1 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+#define GPIO_INT_1    0xFFFFFFFFU
+#define GPIO_INT_1_M  (GPIO_INT_1_V << GPIO_INT_1_S)
+#define GPIO_INT_1_V  0xFFFFFFFFU
+#define GPIO_INT_1_S  0
+
+/** GPIO_INTR1_1_REG register
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+#define GPIO_INTR1_1_REG (DR_REG_GPIO_BASE + 0x68)
+/** GPIO_INT1_1 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+#define GPIO_INT1_1    0x01FFFFFFU
+#define GPIO_INT1_1_M  (GPIO_INT1_1_V << GPIO_INT1_1_S)
+#define GPIO_INT1_1_V  0x01FFFFFFU
+#define GPIO_INT1_1_S  0
+
+/** GPIO_STATUS_NEXT_REG register
+ *  GPIO interrupt source register for GPIO0-31
+ */
+#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x6c)
+/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt source register for GPIO0-31
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+/** GPIO_STATUS_NEXT1_REG register
+ *  GPIO interrupt source register for GPIO32-56
+ */
+#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x70)
+/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt source register for GPIO32-56
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT1    0x01FFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT1_M  (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S)
+#define GPIO_STATUS_INTERRUPT_NEXT1_V  0x01FFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT1_S  0
+
+/** GPIO_PIN0_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74)
+/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
+#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN0_INT_TYPE    0x00000007U
+#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
+#define GPIO_PIN0_INT_TYPE_V  0x00000007U
+#define GPIO_PIN0_INT_TYPE_S  7
+/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/** GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN0_CONFIG    0x00000003U
+#define GPIO_PIN0_CONFIG_M  (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S)
+#define GPIO_PIN0_CONFIG_V  0x00000003U
+#define GPIO_PIN0_CONFIG_S  11
+/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN0_INT_ENA    0x0000001FU
+#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
+#define GPIO_PIN0_INT_ENA_V  0x0000001FU
+#define GPIO_PIN0_INT_ENA_S  13
+
+/** GPIO_PIN1_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78)
+/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
+#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN1_INT_TYPE    0x00000007U
+#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
+#define GPIO_PIN1_INT_TYPE_V  0x00000007U
+#define GPIO_PIN1_INT_TYPE_S  7
+/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/** GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN1_CONFIG    0x00000003U
+#define GPIO_PIN1_CONFIG_M  (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S)
+#define GPIO_PIN1_CONFIG_V  0x00000003U
+#define GPIO_PIN1_CONFIG_S  11
+/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN1_INT_ENA    0x0000001FU
+#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
+#define GPIO_PIN1_INT_ENA_V  0x0000001FU
+#define GPIO_PIN1_INT_ENA_S  13
+
+/** GPIO_PIN2_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c)
+/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
+#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN2_INT_TYPE    0x00000007U
+#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
+#define GPIO_PIN2_INT_TYPE_V  0x00000007U
+#define GPIO_PIN2_INT_TYPE_S  7
+/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/** GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN2_CONFIG    0x00000003U
+#define GPIO_PIN2_CONFIG_M  (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S)
+#define GPIO_PIN2_CONFIG_V  0x00000003U
+#define GPIO_PIN2_CONFIG_S  11
+/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN2_INT_ENA    0x0000001FU
+#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
+#define GPIO_PIN2_INT_ENA_V  0x0000001FU
+#define GPIO_PIN2_INT_ENA_S  13
+
+/** GPIO_PIN3_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80)
+/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
+#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN3_INT_TYPE    0x00000007U
+#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
+#define GPIO_PIN3_INT_TYPE_V  0x00000007U
+#define GPIO_PIN3_INT_TYPE_S  7
+/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/** GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN3_CONFIG    0x00000003U
+#define GPIO_PIN3_CONFIG_M  (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S)
+#define GPIO_PIN3_CONFIG_V  0x00000003U
+#define GPIO_PIN3_CONFIG_S  11
+/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN3_INT_ENA    0x0000001FU
+#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
+#define GPIO_PIN3_INT_ENA_V  0x0000001FU
+#define GPIO_PIN3_INT_ENA_S  13
+
+/** GPIO_PIN4_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84)
+/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
+#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN4_INT_TYPE    0x00000007U
+#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
+#define GPIO_PIN4_INT_TYPE_V  0x00000007U
+#define GPIO_PIN4_INT_TYPE_S  7
+/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/** GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN4_CONFIG    0x00000003U
+#define GPIO_PIN4_CONFIG_M  (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S)
+#define GPIO_PIN4_CONFIG_V  0x00000003U
+#define GPIO_PIN4_CONFIG_S  11
+/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN4_INT_ENA    0x0000001FU
+#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
+#define GPIO_PIN4_INT_ENA_V  0x0000001FU
+#define GPIO_PIN4_INT_ENA_S  13
+
+/** GPIO_PIN5_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88)
+/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
+#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN5_INT_TYPE    0x00000007U
+#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
+#define GPIO_PIN5_INT_TYPE_V  0x00000007U
+#define GPIO_PIN5_INT_TYPE_S  7
+/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/** GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN5_CONFIG    0x00000003U
+#define GPIO_PIN5_CONFIG_M  (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S)
+#define GPIO_PIN5_CONFIG_V  0x00000003U
+#define GPIO_PIN5_CONFIG_S  11
+/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN5_INT_ENA    0x0000001FU
+#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
+#define GPIO_PIN5_INT_ENA_V  0x0000001FU
+#define GPIO_PIN5_INT_ENA_S  13
+
+/** GPIO_PIN6_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c)
+/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
+#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN6_INT_TYPE    0x00000007U
+#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
+#define GPIO_PIN6_INT_TYPE_V  0x00000007U
+#define GPIO_PIN6_INT_TYPE_S  7
+/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/** GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN6_CONFIG    0x00000003U
+#define GPIO_PIN6_CONFIG_M  (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S)
+#define GPIO_PIN6_CONFIG_V  0x00000003U
+#define GPIO_PIN6_CONFIG_S  11
+/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN6_INT_ENA    0x0000001FU
+#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
+#define GPIO_PIN6_INT_ENA_V  0x0000001FU
+#define GPIO_PIN6_INT_ENA_S  13
+
+/** GPIO_PIN7_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90)
+/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
+#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN7_INT_TYPE    0x00000007U
+#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
+#define GPIO_PIN7_INT_TYPE_V  0x00000007U
+#define GPIO_PIN7_INT_TYPE_S  7
+/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/** GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN7_CONFIG    0x00000003U
+#define GPIO_PIN7_CONFIG_M  (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S)
+#define GPIO_PIN7_CONFIG_V  0x00000003U
+#define GPIO_PIN7_CONFIG_S  11
+/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN7_INT_ENA    0x0000001FU
+#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
+#define GPIO_PIN7_INT_ENA_V  0x0000001FU
+#define GPIO_PIN7_INT_ENA_S  13
+
+/** GPIO_PIN8_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94)
+/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
+#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN8_INT_TYPE    0x00000007U
+#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
+#define GPIO_PIN8_INT_TYPE_V  0x00000007U
+#define GPIO_PIN8_INT_TYPE_S  7
+/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/** GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN8_CONFIG    0x00000003U
+#define GPIO_PIN8_CONFIG_M  (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S)
+#define GPIO_PIN8_CONFIG_V  0x00000003U
+#define GPIO_PIN8_CONFIG_S  11
+/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN8_INT_ENA    0x0000001FU
+#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
+#define GPIO_PIN8_INT_ENA_V  0x0000001FU
+#define GPIO_PIN8_INT_ENA_S  13
+
+/** GPIO_PIN9_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98)
+/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
+#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN9_INT_TYPE    0x00000007U
+#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
+#define GPIO_PIN9_INT_TYPE_V  0x00000007U
+#define GPIO_PIN9_INT_TYPE_S  7
+/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/** GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN9_CONFIG    0x00000003U
+#define GPIO_PIN9_CONFIG_M  (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S)
+#define GPIO_PIN9_CONFIG_V  0x00000003U
+#define GPIO_PIN9_CONFIG_S  11
+/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN9_INT_ENA    0x0000001FU
+#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
+#define GPIO_PIN9_INT_ENA_V  0x0000001FU
+#define GPIO_PIN9_INT_ENA_S  13
+
+/** GPIO_PIN10_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c)
+/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
+#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN10_INT_TYPE    0x00000007U
+#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
+#define GPIO_PIN10_INT_TYPE_V  0x00000007U
+#define GPIO_PIN10_INT_TYPE_S  7
+/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/** GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN10_CONFIG    0x00000003U
+#define GPIO_PIN10_CONFIG_M  (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S)
+#define GPIO_PIN10_CONFIG_V  0x00000003U
+#define GPIO_PIN10_CONFIG_S  11
+/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN10_INT_ENA    0x0000001FU
+#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
+#define GPIO_PIN10_INT_ENA_V  0x0000001FU
+#define GPIO_PIN10_INT_ENA_S  13
+
+/** GPIO_PIN11_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0)
+/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
+#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN11_INT_TYPE    0x00000007U
+#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
+#define GPIO_PIN11_INT_TYPE_V  0x00000007U
+#define GPIO_PIN11_INT_TYPE_S  7
+/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/** GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN11_CONFIG    0x00000003U
+#define GPIO_PIN11_CONFIG_M  (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S)
+#define GPIO_PIN11_CONFIG_V  0x00000003U
+#define GPIO_PIN11_CONFIG_S  11
+/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN11_INT_ENA    0x0000001FU
+#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
+#define GPIO_PIN11_INT_ENA_V  0x0000001FU
+#define GPIO_PIN11_INT_ENA_S  13
+
+/** GPIO_PIN12_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4)
+/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
+#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN12_INT_TYPE    0x00000007U
+#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
+#define GPIO_PIN12_INT_TYPE_V  0x00000007U
+#define GPIO_PIN12_INT_TYPE_S  7
+/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/** GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN12_CONFIG    0x00000003U
+#define GPIO_PIN12_CONFIG_M  (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S)
+#define GPIO_PIN12_CONFIG_V  0x00000003U
+#define GPIO_PIN12_CONFIG_S  11
+/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN12_INT_ENA    0x0000001FU
+#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
+#define GPIO_PIN12_INT_ENA_V  0x0000001FU
+#define GPIO_PIN12_INT_ENA_S  13
+
+/** GPIO_PIN13_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8)
+/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
+#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN13_INT_TYPE    0x00000007U
+#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
+#define GPIO_PIN13_INT_TYPE_V  0x00000007U
+#define GPIO_PIN13_INT_TYPE_S  7
+/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/** GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN13_CONFIG    0x00000003U
+#define GPIO_PIN13_CONFIG_M  (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S)
+#define GPIO_PIN13_CONFIG_V  0x00000003U
+#define GPIO_PIN13_CONFIG_S  11
+/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN13_INT_ENA    0x0000001FU
+#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
+#define GPIO_PIN13_INT_ENA_V  0x0000001FU
+#define GPIO_PIN13_INT_ENA_S  13
+
+/** GPIO_PIN14_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac)
+/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
+#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN14_INT_TYPE    0x00000007U
+#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
+#define GPIO_PIN14_INT_TYPE_V  0x00000007U
+#define GPIO_PIN14_INT_TYPE_S  7
+/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/** GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN14_CONFIG    0x00000003U
+#define GPIO_PIN14_CONFIG_M  (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S)
+#define GPIO_PIN14_CONFIG_V  0x00000003U
+#define GPIO_PIN14_CONFIG_S  11
+/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN14_INT_ENA    0x0000001FU
+#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
+#define GPIO_PIN14_INT_ENA_V  0x0000001FU
+#define GPIO_PIN14_INT_ENA_S  13
+
+/** GPIO_PIN15_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0)
+/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
+#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN15_INT_TYPE    0x00000007U
+#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
+#define GPIO_PIN15_INT_TYPE_V  0x00000007U
+#define GPIO_PIN15_INT_TYPE_S  7
+/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/** GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN15_CONFIG    0x00000003U
+#define GPIO_PIN15_CONFIG_M  (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S)
+#define GPIO_PIN15_CONFIG_V  0x00000003U
+#define GPIO_PIN15_CONFIG_S  11
+/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN15_INT_ENA    0x0000001FU
+#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
+#define GPIO_PIN15_INT_ENA_V  0x0000001FU
+#define GPIO_PIN15_INT_ENA_S  13
+
+/** GPIO_PIN16_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4)
+/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
+#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN16_INT_TYPE    0x00000007U
+#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
+#define GPIO_PIN16_INT_TYPE_V  0x00000007U
+#define GPIO_PIN16_INT_TYPE_S  7
+/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/** GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN16_CONFIG    0x00000003U
+#define GPIO_PIN16_CONFIG_M  (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S)
+#define GPIO_PIN16_CONFIG_V  0x00000003U
+#define GPIO_PIN16_CONFIG_S  11
+/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN16_INT_ENA    0x0000001FU
+#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
+#define GPIO_PIN16_INT_ENA_V  0x0000001FU
+#define GPIO_PIN16_INT_ENA_S  13
+
+/** GPIO_PIN17_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8)
+/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
+#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN17_INT_TYPE    0x00000007U
+#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
+#define GPIO_PIN17_INT_TYPE_V  0x00000007U
+#define GPIO_PIN17_INT_TYPE_S  7
+/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/** GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN17_CONFIG    0x00000003U
+#define GPIO_PIN17_CONFIG_M  (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S)
+#define GPIO_PIN17_CONFIG_V  0x00000003U
+#define GPIO_PIN17_CONFIG_S  11
+/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN17_INT_ENA    0x0000001FU
+#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
+#define GPIO_PIN17_INT_ENA_V  0x0000001FU
+#define GPIO_PIN17_INT_ENA_S  13
+
+/** GPIO_PIN18_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc)
+/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
+#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN18_INT_TYPE    0x00000007U
+#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
+#define GPIO_PIN18_INT_TYPE_V  0x00000007U
+#define GPIO_PIN18_INT_TYPE_S  7
+/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/** GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN18_CONFIG    0x00000003U
+#define GPIO_PIN18_CONFIG_M  (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S)
+#define GPIO_PIN18_CONFIG_V  0x00000003U
+#define GPIO_PIN18_CONFIG_S  11
+/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN18_INT_ENA    0x0000001FU
+#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
+#define GPIO_PIN18_INT_ENA_V  0x0000001FU
+#define GPIO_PIN18_INT_ENA_S  13
+
+/** GPIO_PIN19_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0)
+/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
+#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN19_INT_TYPE    0x00000007U
+#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
+#define GPIO_PIN19_INT_TYPE_V  0x00000007U
+#define GPIO_PIN19_INT_TYPE_S  7
+/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/** GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN19_CONFIG    0x00000003U
+#define GPIO_PIN19_CONFIG_M  (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S)
+#define GPIO_PIN19_CONFIG_V  0x00000003U
+#define GPIO_PIN19_CONFIG_S  11
+/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN19_INT_ENA    0x0000001FU
+#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
+#define GPIO_PIN19_INT_ENA_V  0x0000001FU
+#define GPIO_PIN19_INT_ENA_S  13
+
+/** GPIO_PIN20_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4)
+/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
+#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN20_INT_TYPE    0x00000007U
+#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
+#define GPIO_PIN20_INT_TYPE_V  0x00000007U
+#define GPIO_PIN20_INT_TYPE_S  7
+/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/** GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN20_CONFIG    0x00000003U
+#define GPIO_PIN20_CONFIG_M  (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S)
+#define GPIO_PIN20_CONFIG_V  0x00000003U
+#define GPIO_PIN20_CONFIG_S  11
+/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN20_INT_ENA    0x0000001FU
+#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
+#define GPIO_PIN20_INT_ENA_V  0x0000001FU
+#define GPIO_PIN20_INT_ENA_S  13
+
+/** GPIO_PIN21_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8)
+/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
+#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN21_INT_TYPE    0x00000007U
+#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
+#define GPIO_PIN21_INT_TYPE_V  0x00000007U
+#define GPIO_PIN21_INT_TYPE_S  7
+/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/** GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN21_CONFIG    0x00000003U
+#define GPIO_PIN21_CONFIG_M  (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S)
+#define GPIO_PIN21_CONFIG_V  0x00000003U
+#define GPIO_PIN21_CONFIG_S  11
+/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN21_INT_ENA    0x0000001FU
+#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
+#define GPIO_PIN21_INT_ENA_V  0x0000001FU
+#define GPIO_PIN21_INT_ENA_S  13
+
+/** GPIO_PIN22_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc)
+/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN22_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_M  (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
+#define GPIO_PIN22_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN22_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_M  (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN22_INT_TYPE    0x00000007U
+#define GPIO_PIN22_INT_TYPE_M  (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
+#define GPIO_PIN22_INT_TYPE_V  0x00000007U
+#define GPIO_PIN22_INT_TYPE_S  7
+/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/** GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN22_CONFIG    0x00000003U
+#define GPIO_PIN22_CONFIG_M  (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S)
+#define GPIO_PIN22_CONFIG_V  0x00000003U
+#define GPIO_PIN22_CONFIG_S  11
+/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN22_INT_ENA    0x0000001FU
+#define GPIO_PIN22_INT_ENA_M  (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
+#define GPIO_PIN22_INT_ENA_V  0x0000001FU
+#define GPIO_PIN22_INT_ENA_S  13
+
+/** GPIO_PIN23_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0)
+/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN23_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_M  (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
+#define GPIO_PIN23_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN23_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_M  (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN23_INT_TYPE    0x00000007U
+#define GPIO_PIN23_INT_TYPE_M  (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
+#define GPIO_PIN23_INT_TYPE_V  0x00000007U
+#define GPIO_PIN23_INT_TYPE_S  7
+/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/** GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN23_CONFIG    0x00000003U
+#define GPIO_PIN23_CONFIG_M  (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S)
+#define GPIO_PIN23_CONFIG_V  0x00000003U
+#define GPIO_PIN23_CONFIG_S  11
+/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN23_INT_ENA    0x0000001FU
+#define GPIO_PIN23_INT_ENA_M  (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
+#define GPIO_PIN23_INT_ENA_V  0x0000001FU
+#define GPIO_PIN23_INT_ENA_S  13
+
+/** GPIO_PIN24_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4)
+/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN24_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_M  (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
+#define GPIO_PIN24_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN24_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_M  (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN24_INT_TYPE    0x00000007U
+#define GPIO_PIN24_INT_TYPE_M  (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
+#define GPIO_PIN24_INT_TYPE_V  0x00000007U
+#define GPIO_PIN24_INT_TYPE_S  7
+/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/** GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN24_CONFIG    0x00000003U
+#define GPIO_PIN24_CONFIG_M  (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S)
+#define GPIO_PIN24_CONFIG_V  0x00000003U
+#define GPIO_PIN24_CONFIG_S  11
+/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN24_INT_ENA    0x0000001FU
+#define GPIO_PIN24_INT_ENA_M  (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
+#define GPIO_PIN24_INT_ENA_V  0x0000001FU
+#define GPIO_PIN24_INT_ENA_S  13
+
+/** GPIO_PIN25_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8)
+/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN25_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN25_SYNC2_BYPASS_M  (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S)
+#define GPIO_PIN25_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN25_SYNC2_BYPASS_S  0
+/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN25_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M  (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S)
+#define GPIO_PIN25_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN25_PAD_DRIVER_S  2
+/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN25_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN25_SYNC1_BYPASS_M  (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S)
+#define GPIO_PIN25_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN25_SYNC1_BYPASS_S  3
+/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN25_INT_TYPE    0x00000007U
+#define GPIO_PIN25_INT_TYPE_M  (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S)
+#define GPIO_PIN25_INT_TYPE_V  0x00000007U
+#define GPIO_PIN25_INT_TYPE_S  7
+/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN25_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M  (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S)
+#define GPIO_PIN25_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN25_WAKEUP_ENABLE_S  10
+/** GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN25_CONFIG    0x00000003U
+#define GPIO_PIN25_CONFIG_M  (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S)
+#define GPIO_PIN25_CONFIG_V  0x00000003U
+#define GPIO_PIN25_CONFIG_S  11
+/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN25_INT_ENA    0x0000001FU
+#define GPIO_PIN25_INT_ENA_M  (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S)
+#define GPIO_PIN25_INT_ENA_V  0x0000001FU
+#define GPIO_PIN25_INT_ENA_S  13
+
+/** GPIO_PIN26_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc)
+/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN26_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN26_SYNC2_BYPASS_M  (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S)
+#define GPIO_PIN26_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN26_SYNC2_BYPASS_S  0
+/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN26_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_M  (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S)
+#define GPIO_PIN26_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN26_PAD_DRIVER_S  2
+/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN26_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN26_SYNC1_BYPASS_M  (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S)
+#define GPIO_PIN26_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN26_SYNC1_BYPASS_S  3
+/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN26_INT_TYPE    0x00000007U
+#define GPIO_PIN26_INT_TYPE_M  (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S)
+#define GPIO_PIN26_INT_TYPE_V  0x00000007U
+#define GPIO_PIN26_INT_TYPE_S  7
+/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN26_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_M  (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S)
+#define GPIO_PIN26_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN26_WAKEUP_ENABLE_S  10
+/** GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN26_CONFIG    0x00000003U
+#define GPIO_PIN26_CONFIG_M  (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S)
+#define GPIO_PIN26_CONFIG_V  0x00000003U
+#define GPIO_PIN26_CONFIG_S  11
+/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN26_INT_ENA    0x0000001FU
+#define GPIO_PIN26_INT_ENA_M  (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S)
+#define GPIO_PIN26_INT_ENA_V  0x0000001FU
+#define GPIO_PIN26_INT_ENA_S  13
+
+/** GPIO_PIN27_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0)
+/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN27_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN27_SYNC2_BYPASS_M  (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S)
+#define GPIO_PIN27_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN27_SYNC2_BYPASS_S  0
+/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN27_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_M  (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S)
+#define GPIO_PIN27_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN27_PAD_DRIVER_S  2
+/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN27_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN27_SYNC1_BYPASS_M  (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S)
+#define GPIO_PIN27_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN27_SYNC1_BYPASS_S  3
+/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN27_INT_TYPE    0x00000007U
+#define GPIO_PIN27_INT_TYPE_M  (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S)
+#define GPIO_PIN27_INT_TYPE_V  0x00000007U
+#define GPIO_PIN27_INT_TYPE_S  7
+/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN27_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_M  (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S)
+#define GPIO_PIN27_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN27_WAKEUP_ENABLE_S  10
+/** GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN27_CONFIG    0x00000003U
+#define GPIO_PIN27_CONFIG_M  (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S)
+#define GPIO_PIN27_CONFIG_V  0x00000003U
+#define GPIO_PIN27_CONFIG_S  11
+/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN27_INT_ENA    0x0000001FU
+#define GPIO_PIN27_INT_ENA_M  (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S)
+#define GPIO_PIN27_INT_ENA_V  0x0000001FU
+#define GPIO_PIN27_INT_ENA_S  13
+
+/** GPIO_PIN28_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4)
+/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN28_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN28_SYNC2_BYPASS_M  (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S)
+#define GPIO_PIN28_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN28_SYNC2_BYPASS_S  0
+/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN28_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_M  (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S)
+#define GPIO_PIN28_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN28_PAD_DRIVER_S  2
+/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN28_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN28_SYNC1_BYPASS_M  (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S)
+#define GPIO_PIN28_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN28_SYNC1_BYPASS_S  3
+/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN28_INT_TYPE    0x00000007U
+#define GPIO_PIN28_INT_TYPE_M  (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S)
+#define GPIO_PIN28_INT_TYPE_V  0x00000007U
+#define GPIO_PIN28_INT_TYPE_S  7
+/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN28_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_M  (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S)
+#define GPIO_PIN28_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN28_WAKEUP_ENABLE_S  10
+/** GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN28_CONFIG    0x00000003U
+#define GPIO_PIN28_CONFIG_M  (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S)
+#define GPIO_PIN28_CONFIG_V  0x00000003U
+#define GPIO_PIN28_CONFIG_S  11
+/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN28_INT_ENA    0x0000001FU
+#define GPIO_PIN28_INT_ENA_M  (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S)
+#define GPIO_PIN28_INT_ENA_V  0x0000001FU
+#define GPIO_PIN28_INT_ENA_S  13
+
+/** GPIO_PIN29_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8)
+/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN29_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN29_SYNC2_BYPASS_M  (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S)
+#define GPIO_PIN29_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN29_SYNC2_BYPASS_S  0
+/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN29_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_M  (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S)
+#define GPIO_PIN29_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN29_PAD_DRIVER_S  2
+/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN29_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN29_SYNC1_BYPASS_M  (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S)
+#define GPIO_PIN29_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN29_SYNC1_BYPASS_S  3
+/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN29_INT_TYPE    0x00000007U
+#define GPIO_PIN29_INT_TYPE_M  (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S)
+#define GPIO_PIN29_INT_TYPE_V  0x00000007U
+#define GPIO_PIN29_INT_TYPE_S  7
+/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN29_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_M  (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S)
+#define GPIO_PIN29_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN29_WAKEUP_ENABLE_S  10
+/** GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN29_CONFIG    0x00000003U
+#define GPIO_PIN29_CONFIG_M  (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S)
+#define GPIO_PIN29_CONFIG_V  0x00000003U
+#define GPIO_PIN29_CONFIG_S  11
+/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN29_INT_ENA    0x0000001FU
+#define GPIO_PIN29_INT_ENA_M  (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S)
+#define GPIO_PIN29_INT_ENA_V  0x0000001FU
+#define GPIO_PIN29_INT_ENA_S  13
+
+/** GPIO_PIN30_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec)
+/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN30_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN30_SYNC2_BYPASS_M  (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S)
+#define GPIO_PIN30_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN30_SYNC2_BYPASS_S  0
+/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN30_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_M  (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S)
+#define GPIO_PIN30_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN30_PAD_DRIVER_S  2
+/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN30_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN30_SYNC1_BYPASS_M  (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S)
+#define GPIO_PIN30_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN30_SYNC1_BYPASS_S  3
+/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN30_INT_TYPE    0x00000007U
+#define GPIO_PIN30_INT_TYPE_M  (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S)
+#define GPIO_PIN30_INT_TYPE_V  0x00000007U
+#define GPIO_PIN30_INT_TYPE_S  7
+/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN30_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_M  (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S)
+#define GPIO_PIN30_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN30_WAKEUP_ENABLE_S  10
+/** GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN30_CONFIG    0x00000003U
+#define GPIO_PIN30_CONFIG_M  (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S)
+#define GPIO_PIN30_CONFIG_V  0x00000003U
+#define GPIO_PIN30_CONFIG_S  11
+/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN30_INT_ENA    0x0000001FU
+#define GPIO_PIN30_INT_ENA_M  (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S)
+#define GPIO_PIN30_INT_ENA_V  0x0000001FU
+#define GPIO_PIN30_INT_ENA_S  13
+
+/** GPIO_PIN31_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0)
+/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN31_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN31_SYNC2_BYPASS_M  (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S)
+#define GPIO_PIN31_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN31_SYNC2_BYPASS_S  0
+/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN31_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_M  (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S)
+#define GPIO_PIN31_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN31_PAD_DRIVER_S  2
+/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN31_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN31_SYNC1_BYPASS_M  (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S)
+#define GPIO_PIN31_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN31_SYNC1_BYPASS_S  3
+/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN31_INT_TYPE    0x00000007U
+#define GPIO_PIN31_INT_TYPE_M  (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S)
+#define GPIO_PIN31_INT_TYPE_V  0x00000007U
+#define GPIO_PIN31_INT_TYPE_S  7
+/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN31_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_M  (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S)
+#define GPIO_PIN31_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN31_WAKEUP_ENABLE_S  10
+/** GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN31_CONFIG    0x00000003U
+#define GPIO_PIN31_CONFIG_M  (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S)
+#define GPIO_PIN31_CONFIG_V  0x00000003U
+#define GPIO_PIN31_CONFIG_S  11
+/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN31_INT_ENA    0x0000001FU
+#define GPIO_PIN31_INT_ENA_M  (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S)
+#define GPIO_PIN31_INT_ENA_V  0x0000001FU
+#define GPIO_PIN31_INT_ENA_S  13
+
+/** GPIO_PIN32_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4)
+/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN32_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN32_SYNC2_BYPASS_M  (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S)
+#define GPIO_PIN32_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN32_SYNC2_BYPASS_S  0
+/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN32_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_M  (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S)
+#define GPIO_PIN32_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN32_PAD_DRIVER_S  2
+/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN32_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN32_SYNC1_BYPASS_M  (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S)
+#define GPIO_PIN32_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN32_SYNC1_BYPASS_S  3
+/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN32_INT_TYPE    0x00000007U
+#define GPIO_PIN32_INT_TYPE_M  (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S)
+#define GPIO_PIN32_INT_TYPE_V  0x00000007U
+#define GPIO_PIN32_INT_TYPE_S  7
+/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN32_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_M  (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S)
+#define GPIO_PIN32_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN32_WAKEUP_ENABLE_S  10
+/** GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN32_CONFIG    0x00000003U
+#define GPIO_PIN32_CONFIG_M  (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S)
+#define GPIO_PIN32_CONFIG_V  0x00000003U
+#define GPIO_PIN32_CONFIG_S  11
+/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN32_INT_ENA    0x0000001FU
+#define GPIO_PIN32_INT_ENA_M  (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S)
+#define GPIO_PIN32_INT_ENA_V  0x0000001FU
+#define GPIO_PIN32_INT_ENA_S  13
+
+/** GPIO_PIN33_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8)
+/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN33_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN33_SYNC2_BYPASS_M  (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S)
+#define GPIO_PIN33_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN33_SYNC2_BYPASS_S  0
+/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN33_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_M  (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S)
+#define GPIO_PIN33_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN33_PAD_DRIVER_S  2
+/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN33_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN33_SYNC1_BYPASS_M  (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S)
+#define GPIO_PIN33_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN33_SYNC1_BYPASS_S  3
+/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN33_INT_TYPE    0x00000007U
+#define GPIO_PIN33_INT_TYPE_M  (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S)
+#define GPIO_PIN33_INT_TYPE_V  0x00000007U
+#define GPIO_PIN33_INT_TYPE_S  7
+/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN33_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_M  (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S)
+#define GPIO_PIN33_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN33_WAKEUP_ENABLE_S  10
+/** GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN33_CONFIG    0x00000003U
+#define GPIO_PIN33_CONFIG_M  (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S)
+#define GPIO_PIN33_CONFIG_V  0x00000003U
+#define GPIO_PIN33_CONFIG_S  11
+/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN33_INT_ENA    0x0000001FU
+#define GPIO_PIN33_INT_ENA_M  (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S)
+#define GPIO_PIN33_INT_ENA_V  0x0000001FU
+#define GPIO_PIN33_INT_ENA_S  13
+
+/** GPIO_PIN34_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc)
+/** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN34_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN34_SYNC2_BYPASS_M  (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S)
+#define GPIO_PIN34_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN34_SYNC2_BYPASS_S  0
+/** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN34_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_M  (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S)
+#define GPIO_PIN34_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN34_PAD_DRIVER_S  2
+/** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN34_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN34_SYNC1_BYPASS_M  (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S)
+#define GPIO_PIN34_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN34_SYNC1_BYPASS_S  3
+/** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN34_INT_TYPE    0x00000007U
+#define GPIO_PIN34_INT_TYPE_M  (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S)
+#define GPIO_PIN34_INT_TYPE_V  0x00000007U
+#define GPIO_PIN34_INT_TYPE_S  7
+/** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN34_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_M  (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S)
+#define GPIO_PIN34_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN34_WAKEUP_ENABLE_S  10
+/** GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN34_CONFIG    0x00000003U
+#define GPIO_PIN34_CONFIG_M  (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S)
+#define GPIO_PIN34_CONFIG_V  0x00000003U
+#define GPIO_PIN34_CONFIG_S  11
+/** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN34_INT_ENA    0x0000001FU
+#define GPIO_PIN34_INT_ENA_M  (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S)
+#define GPIO_PIN34_INT_ENA_V  0x0000001FU
+#define GPIO_PIN34_INT_ENA_S  13
+
+/** GPIO_PIN35_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100)
+/** GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN35_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN35_SYNC2_BYPASS_M  (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S)
+#define GPIO_PIN35_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN35_SYNC2_BYPASS_S  0
+/** GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN35_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_M  (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S)
+#define GPIO_PIN35_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN35_PAD_DRIVER_S  2
+/** GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN35_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN35_SYNC1_BYPASS_M  (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S)
+#define GPIO_PIN35_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN35_SYNC1_BYPASS_S  3
+/** GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN35_INT_TYPE    0x00000007U
+#define GPIO_PIN35_INT_TYPE_M  (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S)
+#define GPIO_PIN35_INT_TYPE_V  0x00000007U
+#define GPIO_PIN35_INT_TYPE_S  7
+/** GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN35_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_M  (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S)
+#define GPIO_PIN35_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN35_WAKEUP_ENABLE_S  10
+/** GPIO_PIN35_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN35_CONFIG    0x00000003U
+#define GPIO_PIN35_CONFIG_M  (GPIO_PIN35_CONFIG_V << GPIO_PIN35_CONFIG_S)
+#define GPIO_PIN35_CONFIG_V  0x00000003U
+#define GPIO_PIN35_CONFIG_S  11
+/** GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN35_INT_ENA    0x0000001FU
+#define GPIO_PIN35_INT_ENA_M  (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S)
+#define GPIO_PIN35_INT_ENA_V  0x0000001FU
+#define GPIO_PIN35_INT_ENA_S  13
+
+/** GPIO_PIN36_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104)
+/** GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN36_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN36_SYNC2_BYPASS_M  (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S)
+#define GPIO_PIN36_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN36_SYNC2_BYPASS_S  0
+/** GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN36_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_M  (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S)
+#define GPIO_PIN36_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN36_PAD_DRIVER_S  2
+/** GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN36_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN36_SYNC1_BYPASS_M  (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S)
+#define GPIO_PIN36_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN36_SYNC1_BYPASS_S  3
+/** GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN36_INT_TYPE    0x00000007U
+#define GPIO_PIN36_INT_TYPE_M  (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S)
+#define GPIO_PIN36_INT_TYPE_V  0x00000007U
+#define GPIO_PIN36_INT_TYPE_S  7
+/** GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN36_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_M  (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S)
+#define GPIO_PIN36_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN36_WAKEUP_ENABLE_S  10
+/** GPIO_PIN36_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN36_CONFIG    0x00000003U
+#define GPIO_PIN36_CONFIG_M  (GPIO_PIN36_CONFIG_V << GPIO_PIN36_CONFIG_S)
+#define GPIO_PIN36_CONFIG_V  0x00000003U
+#define GPIO_PIN36_CONFIG_S  11
+/** GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN36_INT_ENA    0x0000001FU
+#define GPIO_PIN36_INT_ENA_M  (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S)
+#define GPIO_PIN36_INT_ENA_V  0x0000001FU
+#define GPIO_PIN36_INT_ENA_S  13
+
+/** GPIO_PIN37_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108)
+/** GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN37_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN37_SYNC2_BYPASS_M  (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S)
+#define GPIO_PIN37_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN37_SYNC2_BYPASS_S  0
+/** GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN37_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_M  (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S)
+#define GPIO_PIN37_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN37_PAD_DRIVER_S  2
+/** GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN37_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN37_SYNC1_BYPASS_M  (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S)
+#define GPIO_PIN37_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN37_SYNC1_BYPASS_S  3
+/** GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN37_INT_TYPE    0x00000007U
+#define GPIO_PIN37_INT_TYPE_M  (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S)
+#define GPIO_PIN37_INT_TYPE_V  0x00000007U
+#define GPIO_PIN37_INT_TYPE_S  7
+/** GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN37_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_M  (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S)
+#define GPIO_PIN37_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN37_WAKEUP_ENABLE_S  10
+/** GPIO_PIN37_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN37_CONFIG    0x00000003U
+#define GPIO_PIN37_CONFIG_M  (GPIO_PIN37_CONFIG_V << GPIO_PIN37_CONFIG_S)
+#define GPIO_PIN37_CONFIG_V  0x00000003U
+#define GPIO_PIN37_CONFIG_S  11
+/** GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN37_INT_ENA    0x0000001FU
+#define GPIO_PIN37_INT_ENA_M  (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S)
+#define GPIO_PIN37_INT_ENA_V  0x0000001FU
+#define GPIO_PIN37_INT_ENA_S  13
+
+/** GPIO_PIN38_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10c)
+/** GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN38_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN38_SYNC2_BYPASS_M  (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S)
+#define GPIO_PIN38_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN38_SYNC2_BYPASS_S  0
+/** GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN38_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_M  (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S)
+#define GPIO_PIN38_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN38_PAD_DRIVER_S  2
+/** GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN38_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN38_SYNC1_BYPASS_M  (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S)
+#define GPIO_PIN38_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN38_SYNC1_BYPASS_S  3
+/** GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN38_INT_TYPE    0x00000007U
+#define GPIO_PIN38_INT_TYPE_M  (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S)
+#define GPIO_PIN38_INT_TYPE_V  0x00000007U
+#define GPIO_PIN38_INT_TYPE_S  7
+/** GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN38_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_M  (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S)
+#define GPIO_PIN38_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN38_WAKEUP_ENABLE_S  10
+/** GPIO_PIN38_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN38_CONFIG    0x00000003U
+#define GPIO_PIN38_CONFIG_M  (GPIO_PIN38_CONFIG_V << GPIO_PIN38_CONFIG_S)
+#define GPIO_PIN38_CONFIG_V  0x00000003U
+#define GPIO_PIN38_CONFIG_S  11
+/** GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN38_INT_ENA    0x0000001FU
+#define GPIO_PIN38_INT_ENA_M  (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S)
+#define GPIO_PIN38_INT_ENA_V  0x0000001FU
+#define GPIO_PIN38_INT_ENA_S  13
+
+/** GPIO_PIN39_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110)
+/** GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN39_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN39_SYNC2_BYPASS_M  (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S)
+#define GPIO_PIN39_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN39_SYNC2_BYPASS_S  0
+/** GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN39_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_M  (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S)
+#define GPIO_PIN39_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN39_PAD_DRIVER_S  2
+/** GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN39_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN39_SYNC1_BYPASS_M  (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S)
+#define GPIO_PIN39_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN39_SYNC1_BYPASS_S  3
+/** GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN39_INT_TYPE    0x00000007U
+#define GPIO_PIN39_INT_TYPE_M  (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S)
+#define GPIO_PIN39_INT_TYPE_V  0x00000007U
+#define GPIO_PIN39_INT_TYPE_S  7
+/** GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN39_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_M  (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S)
+#define GPIO_PIN39_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN39_WAKEUP_ENABLE_S  10
+/** GPIO_PIN39_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN39_CONFIG    0x00000003U
+#define GPIO_PIN39_CONFIG_M  (GPIO_PIN39_CONFIG_V << GPIO_PIN39_CONFIG_S)
+#define GPIO_PIN39_CONFIG_V  0x00000003U
+#define GPIO_PIN39_CONFIG_S  11
+/** GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN39_INT_ENA    0x0000001FU
+#define GPIO_PIN39_INT_ENA_M  (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S)
+#define GPIO_PIN39_INT_ENA_V  0x0000001FU
+#define GPIO_PIN39_INT_ENA_S  13
+
+/** GPIO_PIN40_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114)
+/** GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN40_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN40_SYNC2_BYPASS_M  (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S)
+#define GPIO_PIN40_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN40_SYNC2_BYPASS_S  0
+/** GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN40_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN40_PAD_DRIVER_M  (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S)
+#define GPIO_PIN40_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN40_PAD_DRIVER_S  2
+/** GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN40_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN40_SYNC1_BYPASS_M  (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S)
+#define GPIO_PIN40_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN40_SYNC1_BYPASS_S  3
+/** GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN40_INT_TYPE    0x00000007U
+#define GPIO_PIN40_INT_TYPE_M  (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S)
+#define GPIO_PIN40_INT_TYPE_V  0x00000007U
+#define GPIO_PIN40_INT_TYPE_S  7
+/** GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN40_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN40_WAKEUP_ENABLE_M  (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S)
+#define GPIO_PIN40_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN40_WAKEUP_ENABLE_S  10
+/** GPIO_PIN40_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN40_CONFIG    0x00000003U
+#define GPIO_PIN40_CONFIG_M  (GPIO_PIN40_CONFIG_V << GPIO_PIN40_CONFIG_S)
+#define GPIO_PIN40_CONFIG_V  0x00000003U
+#define GPIO_PIN40_CONFIG_S  11
+/** GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN40_INT_ENA    0x0000001FU
+#define GPIO_PIN40_INT_ENA_M  (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S)
+#define GPIO_PIN40_INT_ENA_V  0x0000001FU
+#define GPIO_PIN40_INT_ENA_S  13
+
+/** GPIO_PIN41_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118)
+/** GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN41_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN41_SYNC2_BYPASS_M  (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S)
+#define GPIO_PIN41_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN41_SYNC2_BYPASS_S  0
+/** GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN41_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN41_PAD_DRIVER_M  (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S)
+#define GPIO_PIN41_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN41_PAD_DRIVER_S  2
+/** GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN41_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN41_SYNC1_BYPASS_M  (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S)
+#define GPIO_PIN41_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN41_SYNC1_BYPASS_S  3
+/** GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN41_INT_TYPE    0x00000007U
+#define GPIO_PIN41_INT_TYPE_M  (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S)
+#define GPIO_PIN41_INT_TYPE_V  0x00000007U
+#define GPIO_PIN41_INT_TYPE_S  7
+/** GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN41_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN41_WAKEUP_ENABLE_M  (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S)
+#define GPIO_PIN41_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN41_WAKEUP_ENABLE_S  10
+/** GPIO_PIN41_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN41_CONFIG    0x00000003U
+#define GPIO_PIN41_CONFIG_M  (GPIO_PIN41_CONFIG_V << GPIO_PIN41_CONFIG_S)
+#define GPIO_PIN41_CONFIG_V  0x00000003U
+#define GPIO_PIN41_CONFIG_S  11
+/** GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN41_INT_ENA    0x0000001FU
+#define GPIO_PIN41_INT_ENA_M  (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S)
+#define GPIO_PIN41_INT_ENA_V  0x0000001FU
+#define GPIO_PIN41_INT_ENA_S  13
+
+/** GPIO_PIN42_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11c)
+/** GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN42_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN42_SYNC2_BYPASS_M  (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S)
+#define GPIO_PIN42_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN42_SYNC2_BYPASS_S  0
+/** GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN42_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN42_PAD_DRIVER_M  (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S)
+#define GPIO_PIN42_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN42_PAD_DRIVER_S  2
+/** GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN42_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN42_SYNC1_BYPASS_M  (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S)
+#define GPIO_PIN42_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN42_SYNC1_BYPASS_S  3
+/** GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN42_INT_TYPE    0x00000007U
+#define GPIO_PIN42_INT_TYPE_M  (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S)
+#define GPIO_PIN42_INT_TYPE_V  0x00000007U
+#define GPIO_PIN42_INT_TYPE_S  7
+/** GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN42_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN42_WAKEUP_ENABLE_M  (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S)
+#define GPIO_PIN42_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN42_WAKEUP_ENABLE_S  10
+/** GPIO_PIN42_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN42_CONFIG    0x00000003U
+#define GPIO_PIN42_CONFIG_M  (GPIO_PIN42_CONFIG_V << GPIO_PIN42_CONFIG_S)
+#define GPIO_PIN42_CONFIG_V  0x00000003U
+#define GPIO_PIN42_CONFIG_S  11
+/** GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN42_INT_ENA    0x0000001FU
+#define GPIO_PIN42_INT_ENA_M  (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S)
+#define GPIO_PIN42_INT_ENA_V  0x0000001FU
+#define GPIO_PIN42_INT_ENA_S  13
+
+/** GPIO_PIN43_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120)
+/** GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN43_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN43_SYNC2_BYPASS_M  (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S)
+#define GPIO_PIN43_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN43_SYNC2_BYPASS_S  0
+/** GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN43_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN43_PAD_DRIVER_M  (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S)
+#define GPIO_PIN43_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN43_PAD_DRIVER_S  2
+/** GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN43_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN43_SYNC1_BYPASS_M  (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S)
+#define GPIO_PIN43_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN43_SYNC1_BYPASS_S  3
+/** GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN43_INT_TYPE    0x00000007U
+#define GPIO_PIN43_INT_TYPE_M  (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S)
+#define GPIO_PIN43_INT_TYPE_V  0x00000007U
+#define GPIO_PIN43_INT_TYPE_S  7
+/** GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN43_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN43_WAKEUP_ENABLE_M  (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S)
+#define GPIO_PIN43_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN43_WAKEUP_ENABLE_S  10
+/** GPIO_PIN43_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN43_CONFIG    0x00000003U
+#define GPIO_PIN43_CONFIG_M  (GPIO_PIN43_CONFIG_V << GPIO_PIN43_CONFIG_S)
+#define GPIO_PIN43_CONFIG_V  0x00000003U
+#define GPIO_PIN43_CONFIG_S  11
+/** GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN43_INT_ENA    0x0000001FU
+#define GPIO_PIN43_INT_ENA_M  (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S)
+#define GPIO_PIN43_INT_ENA_V  0x0000001FU
+#define GPIO_PIN43_INT_ENA_S  13
+
+/** GPIO_PIN44_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124)
+/** GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN44_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN44_SYNC2_BYPASS_M  (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S)
+#define GPIO_PIN44_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN44_SYNC2_BYPASS_S  0
+/** GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN44_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN44_PAD_DRIVER_M  (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S)
+#define GPIO_PIN44_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN44_PAD_DRIVER_S  2
+/** GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN44_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN44_SYNC1_BYPASS_M  (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S)
+#define GPIO_PIN44_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN44_SYNC1_BYPASS_S  3
+/** GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN44_INT_TYPE    0x00000007U
+#define GPIO_PIN44_INT_TYPE_M  (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S)
+#define GPIO_PIN44_INT_TYPE_V  0x00000007U
+#define GPIO_PIN44_INT_TYPE_S  7
+/** GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN44_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN44_WAKEUP_ENABLE_M  (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S)
+#define GPIO_PIN44_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN44_WAKEUP_ENABLE_S  10
+/** GPIO_PIN44_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN44_CONFIG    0x00000003U
+#define GPIO_PIN44_CONFIG_M  (GPIO_PIN44_CONFIG_V << GPIO_PIN44_CONFIG_S)
+#define GPIO_PIN44_CONFIG_V  0x00000003U
+#define GPIO_PIN44_CONFIG_S  11
+/** GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN44_INT_ENA    0x0000001FU
+#define GPIO_PIN44_INT_ENA_M  (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S)
+#define GPIO_PIN44_INT_ENA_V  0x0000001FU
+#define GPIO_PIN44_INT_ENA_S  13
+
+/** GPIO_PIN45_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN45_REG (DR_REG_GPIO_BASE + 0x128)
+/** GPIO_PIN45_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN45_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN45_SYNC2_BYPASS_M  (GPIO_PIN45_SYNC2_BYPASS_V << GPIO_PIN45_SYNC2_BYPASS_S)
+#define GPIO_PIN45_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN45_SYNC2_BYPASS_S  0
+/** GPIO_PIN45_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN45_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN45_PAD_DRIVER_M  (GPIO_PIN45_PAD_DRIVER_V << GPIO_PIN45_PAD_DRIVER_S)
+#define GPIO_PIN45_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN45_PAD_DRIVER_S  2
+/** GPIO_PIN45_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN45_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN45_SYNC1_BYPASS_M  (GPIO_PIN45_SYNC1_BYPASS_V << GPIO_PIN45_SYNC1_BYPASS_S)
+#define GPIO_PIN45_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN45_SYNC1_BYPASS_S  3
+/** GPIO_PIN45_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN45_INT_TYPE    0x00000007U
+#define GPIO_PIN45_INT_TYPE_M  (GPIO_PIN45_INT_TYPE_V << GPIO_PIN45_INT_TYPE_S)
+#define GPIO_PIN45_INT_TYPE_V  0x00000007U
+#define GPIO_PIN45_INT_TYPE_S  7
+/** GPIO_PIN45_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN45_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN45_WAKEUP_ENABLE_M  (GPIO_PIN45_WAKEUP_ENABLE_V << GPIO_PIN45_WAKEUP_ENABLE_S)
+#define GPIO_PIN45_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN45_WAKEUP_ENABLE_S  10
+/** GPIO_PIN45_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN45_CONFIG    0x00000003U
+#define GPIO_PIN45_CONFIG_M  (GPIO_PIN45_CONFIG_V << GPIO_PIN45_CONFIG_S)
+#define GPIO_PIN45_CONFIG_V  0x00000003U
+#define GPIO_PIN45_CONFIG_S  11
+/** GPIO_PIN45_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN45_INT_ENA    0x0000001FU
+#define GPIO_PIN45_INT_ENA_M  (GPIO_PIN45_INT_ENA_V << GPIO_PIN45_INT_ENA_S)
+#define GPIO_PIN45_INT_ENA_V  0x0000001FU
+#define GPIO_PIN45_INT_ENA_S  13
+
+/** GPIO_PIN46_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN46_REG (DR_REG_GPIO_BASE + 0x12c)
+/** GPIO_PIN46_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN46_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN46_SYNC2_BYPASS_M  (GPIO_PIN46_SYNC2_BYPASS_V << GPIO_PIN46_SYNC2_BYPASS_S)
+#define GPIO_PIN46_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN46_SYNC2_BYPASS_S  0
+/** GPIO_PIN46_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN46_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN46_PAD_DRIVER_M  (GPIO_PIN46_PAD_DRIVER_V << GPIO_PIN46_PAD_DRIVER_S)
+#define GPIO_PIN46_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN46_PAD_DRIVER_S  2
+/** GPIO_PIN46_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN46_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN46_SYNC1_BYPASS_M  (GPIO_PIN46_SYNC1_BYPASS_V << GPIO_PIN46_SYNC1_BYPASS_S)
+#define GPIO_PIN46_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN46_SYNC1_BYPASS_S  3
+/** GPIO_PIN46_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN46_INT_TYPE    0x00000007U
+#define GPIO_PIN46_INT_TYPE_M  (GPIO_PIN46_INT_TYPE_V << GPIO_PIN46_INT_TYPE_S)
+#define GPIO_PIN46_INT_TYPE_V  0x00000007U
+#define GPIO_PIN46_INT_TYPE_S  7
+/** GPIO_PIN46_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN46_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN46_WAKEUP_ENABLE_M  (GPIO_PIN46_WAKEUP_ENABLE_V << GPIO_PIN46_WAKEUP_ENABLE_S)
+#define GPIO_PIN46_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN46_WAKEUP_ENABLE_S  10
+/** GPIO_PIN46_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN46_CONFIG    0x00000003U
+#define GPIO_PIN46_CONFIG_M  (GPIO_PIN46_CONFIG_V << GPIO_PIN46_CONFIG_S)
+#define GPIO_PIN46_CONFIG_V  0x00000003U
+#define GPIO_PIN46_CONFIG_S  11
+/** GPIO_PIN46_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN46_INT_ENA    0x0000001FU
+#define GPIO_PIN46_INT_ENA_M  (GPIO_PIN46_INT_ENA_V << GPIO_PIN46_INT_ENA_S)
+#define GPIO_PIN46_INT_ENA_V  0x0000001FU
+#define GPIO_PIN46_INT_ENA_S  13
+
+/** GPIO_PIN47_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN47_REG (DR_REG_GPIO_BASE + 0x130)
+/** GPIO_PIN47_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN47_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN47_SYNC2_BYPASS_M  (GPIO_PIN47_SYNC2_BYPASS_V << GPIO_PIN47_SYNC2_BYPASS_S)
+#define GPIO_PIN47_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN47_SYNC2_BYPASS_S  0
+/** GPIO_PIN47_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN47_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN47_PAD_DRIVER_M  (GPIO_PIN47_PAD_DRIVER_V << GPIO_PIN47_PAD_DRIVER_S)
+#define GPIO_PIN47_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN47_PAD_DRIVER_S  2
+/** GPIO_PIN47_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN47_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN47_SYNC1_BYPASS_M  (GPIO_PIN47_SYNC1_BYPASS_V << GPIO_PIN47_SYNC1_BYPASS_S)
+#define GPIO_PIN47_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN47_SYNC1_BYPASS_S  3
+/** GPIO_PIN47_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN47_INT_TYPE    0x00000007U
+#define GPIO_PIN47_INT_TYPE_M  (GPIO_PIN47_INT_TYPE_V << GPIO_PIN47_INT_TYPE_S)
+#define GPIO_PIN47_INT_TYPE_V  0x00000007U
+#define GPIO_PIN47_INT_TYPE_S  7
+/** GPIO_PIN47_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN47_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN47_WAKEUP_ENABLE_M  (GPIO_PIN47_WAKEUP_ENABLE_V << GPIO_PIN47_WAKEUP_ENABLE_S)
+#define GPIO_PIN47_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN47_WAKEUP_ENABLE_S  10
+/** GPIO_PIN47_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN47_CONFIG    0x00000003U
+#define GPIO_PIN47_CONFIG_M  (GPIO_PIN47_CONFIG_V << GPIO_PIN47_CONFIG_S)
+#define GPIO_PIN47_CONFIG_V  0x00000003U
+#define GPIO_PIN47_CONFIG_S  11
+/** GPIO_PIN47_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN47_INT_ENA    0x0000001FU
+#define GPIO_PIN47_INT_ENA_M  (GPIO_PIN47_INT_ENA_V << GPIO_PIN47_INT_ENA_S)
+#define GPIO_PIN47_INT_ENA_V  0x0000001FU
+#define GPIO_PIN47_INT_ENA_S  13
+
+/** GPIO_PIN48_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN48_REG (DR_REG_GPIO_BASE + 0x134)
+/** GPIO_PIN48_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN48_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN48_SYNC2_BYPASS_M  (GPIO_PIN48_SYNC2_BYPASS_V << GPIO_PIN48_SYNC2_BYPASS_S)
+#define GPIO_PIN48_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN48_SYNC2_BYPASS_S  0
+/** GPIO_PIN48_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN48_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN48_PAD_DRIVER_M  (GPIO_PIN48_PAD_DRIVER_V << GPIO_PIN48_PAD_DRIVER_S)
+#define GPIO_PIN48_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN48_PAD_DRIVER_S  2
+/** GPIO_PIN48_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN48_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN48_SYNC1_BYPASS_M  (GPIO_PIN48_SYNC1_BYPASS_V << GPIO_PIN48_SYNC1_BYPASS_S)
+#define GPIO_PIN48_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN48_SYNC1_BYPASS_S  3
+/** GPIO_PIN48_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN48_INT_TYPE    0x00000007U
+#define GPIO_PIN48_INT_TYPE_M  (GPIO_PIN48_INT_TYPE_V << GPIO_PIN48_INT_TYPE_S)
+#define GPIO_PIN48_INT_TYPE_V  0x00000007U
+#define GPIO_PIN48_INT_TYPE_S  7
+/** GPIO_PIN48_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN48_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN48_WAKEUP_ENABLE_M  (GPIO_PIN48_WAKEUP_ENABLE_V << GPIO_PIN48_WAKEUP_ENABLE_S)
+#define GPIO_PIN48_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN48_WAKEUP_ENABLE_S  10
+/** GPIO_PIN48_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN48_CONFIG    0x00000003U
+#define GPIO_PIN48_CONFIG_M  (GPIO_PIN48_CONFIG_V << GPIO_PIN48_CONFIG_S)
+#define GPIO_PIN48_CONFIG_V  0x00000003U
+#define GPIO_PIN48_CONFIG_S  11
+/** GPIO_PIN48_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN48_INT_ENA    0x0000001FU
+#define GPIO_PIN48_INT_ENA_M  (GPIO_PIN48_INT_ENA_V << GPIO_PIN48_INT_ENA_S)
+#define GPIO_PIN48_INT_ENA_V  0x0000001FU
+#define GPIO_PIN48_INT_ENA_S  13
+
+/** GPIO_PIN49_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN49_REG (DR_REG_GPIO_BASE + 0x138)
+/** GPIO_PIN49_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN49_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN49_SYNC2_BYPASS_M  (GPIO_PIN49_SYNC2_BYPASS_V << GPIO_PIN49_SYNC2_BYPASS_S)
+#define GPIO_PIN49_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN49_SYNC2_BYPASS_S  0
+/** GPIO_PIN49_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN49_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN49_PAD_DRIVER_M  (GPIO_PIN49_PAD_DRIVER_V << GPIO_PIN49_PAD_DRIVER_S)
+#define GPIO_PIN49_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN49_PAD_DRIVER_S  2
+/** GPIO_PIN49_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN49_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN49_SYNC1_BYPASS_M  (GPIO_PIN49_SYNC1_BYPASS_V << GPIO_PIN49_SYNC1_BYPASS_S)
+#define GPIO_PIN49_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN49_SYNC1_BYPASS_S  3
+/** GPIO_PIN49_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN49_INT_TYPE    0x00000007U
+#define GPIO_PIN49_INT_TYPE_M  (GPIO_PIN49_INT_TYPE_V << GPIO_PIN49_INT_TYPE_S)
+#define GPIO_PIN49_INT_TYPE_V  0x00000007U
+#define GPIO_PIN49_INT_TYPE_S  7
+/** GPIO_PIN49_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN49_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN49_WAKEUP_ENABLE_M  (GPIO_PIN49_WAKEUP_ENABLE_V << GPIO_PIN49_WAKEUP_ENABLE_S)
+#define GPIO_PIN49_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN49_WAKEUP_ENABLE_S  10
+/** GPIO_PIN49_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN49_CONFIG    0x00000003U
+#define GPIO_PIN49_CONFIG_M  (GPIO_PIN49_CONFIG_V << GPIO_PIN49_CONFIG_S)
+#define GPIO_PIN49_CONFIG_V  0x00000003U
+#define GPIO_PIN49_CONFIG_S  11
+/** GPIO_PIN49_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN49_INT_ENA    0x0000001FU
+#define GPIO_PIN49_INT_ENA_M  (GPIO_PIN49_INT_ENA_V << GPIO_PIN49_INT_ENA_S)
+#define GPIO_PIN49_INT_ENA_V  0x0000001FU
+#define GPIO_PIN49_INT_ENA_S  13
+
+/** GPIO_PIN50_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN50_REG (DR_REG_GPIO_BASE + 0x13c)
+/** GPIO_PIN50_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN50_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN50_SYNC2_BYPASS_M  (GPIO_PIN50_SYNC2_BYPASS_V << GPIO_PIN50_SYNC2_BYPASS_S)
+#define GPIO_PIN50_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN50_SYNC2_BYPASS_S  0
+/** GPIO_PIN50_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN50_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN50_PAD_DRIVER_M  (GPIO_PIN50_PAD_DRIVER_V << GPIO_PIN50_PAD_DRIVER_S)
+#define GPIO_PIN50_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN50_PAD_DRIVER_S  2
+/** GPIO_PIN50_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN50_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN50_SYNC1_BYPASS_M  (GPIO_PIN50_SYNC1_BYPASS_V << GPIO_PIN50_SYNC1_BYPASS_S)
+#define GPIO_PIN50_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN50_SYNC1_BYPASS_S  3
+/** GPIO_PIN50_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN50_INT_TYPE    0x00000007U
+#define GPIO_PIN50_INT_TYPE_M  (GPIO_PIN50_INT_TYPE_V << GPIO_PIN50_INT_TYPE_S)
+#define GPIO_PIN50_INT_TYPE_V  0x00000007U
+#define GPIO_PIN50_INT_TYPE_S  7
+/** GPIO_PIN50_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN50_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN50_WAKEUP_ENABLE_M  (GPIO_PIN50_WAKEUP_ENABLE_V << GPIO_PIN50_WAKEUP_ENABLE_S)
+#define GPIO_PIN50_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN50_WAKEUP_ENABLE_S  10
+/** GPIO_PIN50_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN50_CONFIG    0x00000003U
+#define GPIO_PIN50_CONFIG_M  (GPIO_PIN50_CONFIG_V << GPIO_PIN50_CONFIG_S)
+#define GPIO_PIN50_CONFIG_V  0x00000003U
+#define GPIO_PIN50_CONFIG_S  11
+/** GPIO_PIN50_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN50_INT_ENA    0x0000001FU
+#define GPIO_PIN50_INT_ENA_M  (GPIO_PIN50_INT_ENA_V << GPIO_PIN50_INT_ENA_S)
+#define GPIO_PIN50_INT_ENA_V  0x0000001FU
+#define GPIO_PIN50_INT_ENA_S  13
+
+/** GPIO_PIN51_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN51_REG (DR_REG_GPIO_BASE + 0x140)
+/** GPIO_PIN51_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN51_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN51_SYNC2_BYPASS_M  (GPIO_PIN51_SYNC2_BYPASS_V << GPIO_PIN51_SYNC2_BYPASS_S)
+#define GPIO_PIN51_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN51_SYNC2_BYPASS_S  0
+/** GPIO_PIN51_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN51_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN51_PAD_DRIVER_M  (GPIO_PIN51_PAD_DRIVER_V << GPIO_PIN51_PAD_DRIVER_S)
+#define GPIO_PIN51_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN51_PAD_DRIVER_S  2
+/** GPIO_PIN51_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN51_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN51_SYNC1_BYPASS_M  (GPIO_PIN51_SYNC1_BYPASS_V << GPIO_PIN51_SYNC1_BYPASS_S)
+#define GPIO_PIN51_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN51_SYNC1_BYPASS_S  3
+/** GPIO_PIN51_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN51_INT_TYPE    0x00000007U
+#define GPIO_PIN51_INT_TYPE_M  (GPIO_PIN51_INT_TYPE_V << GPIO_PIN51_INT_TYPE_S)
+#define GPIO_PIN51_INT_TYPE_V  0x00000007U
+#define GPIO_PIN51_INT_TYPE_S  7
+/** GPIO_PIN51_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN51_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN51_WAKEUP_ENABLE_M  (GPIO_PIN51_WAKEUP_ENABLE_V << GPIO_PIN51_WAKEUP_ENABLE_S)
+#define GPIO_PIN51_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN51_WAKEUP_ENABLE_S  10
+/** GPIO_PIN51_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN51_CONFIG    0x00000003U
+#define GPIO_PIN51_CONFIG_M  (GPIO_PIN51_CONFIG_V << GPIO_PIN51_CONFIG_S)
+#define GPIO_PIN51_CONFIG_V  0x00000003U
+#define GPIO_PIN51_CONFIG_S  11
+/** GPIO_PIN51_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN51_INT_ENA    0x0000001FU
+#define GPIO_PIN51_INT_ENA_M  (GPIO_PIN51_INT_ENA_V << GPIO_PIN51_INT_ENA_S)
+#define GPIO_PIN51_INT_ENA_V  0x0000001FU
+#define GPIO_PIN51_INT_ENA_S  13
+
+/** GPIO_PIN52_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN52_REG (DR_REG_GPIO_BASE + 0x144)
+/** GPIO_PIN52_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN52_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN52_SYNC2_BYPASS_M  (GPIO_PIN52_SYNC2_BYPASS_V << GPIO_PIN52_SYNC2_BYPASS_S)
+#define GPIO_PIN52_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN52_SYNC2_BYPASS_S  0
+/** GPIO_PIN52_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN52_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN52_PAD_DRIVER_M  (GPIO_PIN52_PAD_DRIVER_V << GPIO_PIN52_PAD_DRIVER_S)
+#define GPIO_PIN52_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN52_PAD_DRIVER_S  2
+/** GPIO_PIN52_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN52_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN52_SYNC1_BYPASS_M  (GPIO_PIN52_SYNC1_BYPASS_V << GPIO_PIN52_SYNC1_BYPASS_S)
+#define GPIO_PIN52_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN52_SYNC1_BYPASS_S  3
+/** GPIO_PIN52_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN52_INT_TYPE    0x00000007U
+#define GPIO_PIN52_INT_TYPE_M  (GPIO_PIN52_INT_TYPE_V << GPIO_PIN52_INT_TYPE_S)
+#define GPIO_PIN52_INT_TYPE_V  0x00000007U
+#define GPIO_PIN52_INT_TYPE_S  7
+/** GPIO_PIN52_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN52_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN52_WAKEUP_ENABLE_M  (GPIO_PIN52_WAKEUP_ENABLE_V << GPIO_PIN52_WAKEUP_ENABLE_S)
+#define GPIO_PIN52_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN52_WAKEUP_ENABLE_S  10
+/** GPIO_PIN52_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN52_CONFIG    0x00000003U
+#define GPIO_PIN52_CONFIG_M  (GPIO_PIN52_CONFIG_V << GPIO_PIN52_CONFIG_S)
+#define GPIO_PIN52_CONFIG_V  0x00000003U
+#define GPIO_PIN52_CONFIG_S  11
+/** GPIO_PIN52_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN52_INT_ENA    0x0000001FU
+#define GPIO_PIN52_INT_ENA_M  (GPIO_PIN52_INT_ENA_V << GPIO_PIN52_INT_ENA_S)
+#define GPIO_PIN52_INT_ENA_V  0x0000001FU
+#define GPIO_PIN52_INT_ENA_S  13
+
+/** GPIO_PIN53_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN53_REG (DR_REG_GPIO_BASE + 0x148)
+/** GPIO_PIN53_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN53_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN53_SYNC2_BYPASS_M  (GPIO_PIN53_SYNC2_BYPASS_V << GPIO_PIN53_SYNC2_BYPASS_S)
+#define GPIO_PIN53_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN53_SYNC2_BYPASS_S  0
+/** GPIO_PIN53_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN53_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN53_PAD_DRIVER_M  (GPIO_PIN53_PAD_DRIVER_V << GPIO_PIN53_PAD_DRIVER_S)
+#define GPIO_PIN53_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN53_PAD_DRIVER_S  2
+/** GPIO_PIN53_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN53_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN53_SYNC1_BYPASS_M  (GPIO_PIN53_SYNC1_BYPASS_V << GPIO_PIN53_SYNC1_BYPASS_S)
+#define GPIO_PIN53_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN53_SYNC1_BYPASS_S  3
+/** GPIO_PIN53_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN53_INT_TYPE    0x00000007U
+#define GPIO_PIN53_INT_TYPE_M  (GPIO_PIN53_INT_TYPE_V << GPIO_PIN53_INT_TYPE_S)
+#define GPIO_PIN53_INT_TYPE_V  0x00000007U
+#define GPIO_PIN53_INT_TYPE_S  7
+/** GPIO_PIN53_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN53_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN53_WAKEUP_ENABLE_M  (GPIO_PIN53_WAKEUP_ENABLE_V << GPIO_PIN53_WAKEUP_ENABLE_S)
+#define GPIO_PIN53_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN53_WAKEUP_ENABLE_S  10
+/** GPIO_PIN53_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN53_CONFIG    0x00000003U
+#define GPIO_PIN53_CONFIG_M  (GPIO_PIN53_CONFIG_V << GPIO_PIN53_CONFIG_S)
+#define GPIO_PIN53_CONFIG_V  0x00000003U
+#define GPIO_PIN53_CONFIG_S  11
+/** GPIO_PIN53_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN53_INT_ENA    0x0000001FU
+#define GPIO_PIN53_INT_ENA_M  (GPIO_PIN53_INT_ENA_V << GPIO_PIN53_INT_ENA_S)
+#define GPIO_PIN53_INT_ENA_V  0x0000001FU
+#define GPIO_PIN53_INT_ENA_S  13
+
+/** GPIO_PIN54_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN54_REG (DR_REG_GPIO_BASE + 0x14c)
+/** GPIO_PIN54_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN54_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN54_SYNC2_BYPASS_M  (GPIO_PIN54_SYNC2_BYPASS_V << GPIO_PIN54_SYNC2_BYPASS_S)
+#define GPIO_PIN54_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN54_SYNC2_BYPASS_S  0
+/** GPIO_PIN54_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN54_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN54_PAD_DRIVER_M  (GPIO_PIN54_PAD_DRIVER_V << GPIO_PIN54_PAD_DRIVER_S)
+#define GPIO_PIN54_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN54_PAD_DRIVER_S  2
+/** GPIO_PIN54_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN54_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN54_SYNC1_BYPASS_M  (GPIO_PIN54_SYNC1_BYPASS_V << GPIO_PIN54_SYNC1_BYPASS_S)
+#define GPIO_PIN54_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN54_SYNC1_BYPASS_S  3
+/** GPIO_PIN54_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN54_INT_TYPE    0x00000007U
+#define GPIO_PIN54_INT_TYPE_M  (GPIO_PIN54_INT_TYPE_V << GPIO_PIN54_INT_TYPE_S)
+#define GPIO_PIN54_INT_TYPE_V  0x00000007U
+#define GPIO_PIN54_INT_TYPE_S  7
+/** GPIO_PIN54_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN54_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN54_WAKEUP_ENABLE_M  (GPIO_PIN54_WAKEUP_ENABLE_V << GPIO_PIN54_WAKEUP_ENABLE_S)
+#define GPIO_PIN54_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN54_WAKEUP_ENABLE_S  10
+/** GPIO_PIN54_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN54_CONFIG    0x00000003U
+#define GPIO_PIN54_CONFIG_M  (GPIO_PIN54_CONFIG_V << GPIO_PIN54_CONFIG_S)
+#define GPIO_PIN54_CONFIG_V  0x00000003U
+#define GPIO_PIN54_CONFIG_S  11
+/** GPIO_PIN54_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN54_INT_ENA    0x0000001FU
+#define GPIO_PIN54_INT_ENA_M  (GPIO_PIN54_INT_ENA_V << GPIO_PIN54_INT_ENA_S)
+#define GPIO_PIN54_INT_ENA_V  0x0000001FU
+#define GPIO_PIN54_INT_ENA_S  13
+
+/** GPIO_PIN55_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN55_REG (DR_REG_GPIO_BASE + 0x150)
+/** GPIO_PIN55_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN55_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN55_SYNC2_BYPASS_M  (GPIO_PIN55_SYNC2_BYPASS_V << GPIO_PIN55_SYNC2_BYPASS_S)
+#define GPIO_PIN55_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN55_SYNC2_BYPASS_S  0
+/** GPIO_PIN55_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN55_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN55_PAD_DRIVER_M  (GPIO_PIN55_PAD_DRIVER_V << GPIO_PIN55_PAD_DRIVER_S)
+#define GPIO_PIN55_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN55_PAD_DRIVER_S  2
+/** GPIO_PIN55_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN55_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN55_SYNC1_BYPASS_M  (GPIO_PIN55_SYNC1_BYPASS_V << GPIO_PIN55_SYNC1_BYPASS_S)
+#define GPIO_PIN55_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN55_SYNC1_BYPASS_S  3
+/** GPIO_PIN55_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN55_INT_TYPE    0x00000007U
+#define GPIO_PIN55_INT_TYPE_M  (GPIO_PIN55_INT_TYPE_V << GPIO_PIN55_INT_TYPE_S)
+#define GPIO_PIN55_INT_TYPE_V  0x00000007U
+#define GPIO_PIN55_INT_TYPE_S  7
+/** GPIO_PIN55_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN55_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN55_WAKEUP_ENABLE_M  (GPIO_PIN55_WAKEUP_ENABLE_V << GPIO_PIN55_WAKEUP_ENABLE_S)
+#define GPIO_PIN55_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN55_WAKEUP_ENABLE_S  10
+/** GPIO_PIN55_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN55_CONFIG    0x00000003U
+#define GPIO_PIN55_CONFIG_M  (GPIO_PIN55_CONFIG_V << GPIO_PIN55_CONFIG_S)
+#define GPIO_PIN55_CONFIG_V  0x00000003U
+#define GPIO_PIN55_CONFIG_S  11
+/** GPIO_PIN55_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN55_INT_ENA    0x0000001FU
+#define GPIO_PIN55_INT_ENA_M  (GPIO_PIN55_INT_ENA_V << GPIO_PIN55_INT_ENA_S)
+#define GPIO_PIN55_INT_ENA_V  0x0000001FU
+#define GPIO_PIN55_INT_ENA_S  13
+
+/** GPIO_PIN56_REG register
+ *  GPIO pin configuration register
+ */
+#define GPIO_PIN56_REG (DR_REG_GPIO_BASE + 0x154)
+/** GPIO_PIN56_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN56_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN56_SYNC2_BYPASS_M  (GPIO_PIN56_SYNC2_BYPASS_V << GPIO_PIN56_SYNC2_BYPASS_S)
+#define GPIO_PIN56_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN56_SYNC2_BYPASS_S  0
+/** GPIO_PIN56_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  set this bit to select pad driver. 1:open-drain. 0:normal.
+ */
+#define GPIO_PIN56_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN56_PAD_DRIVER_M  (GPIO_PIN56_PAD_DRIVER_V << GPIO_PIN56_PAD_DRIVER_S)
+#define GPIO_PIN56_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN56_PAD_DRIVER_S  2
+/** GPIO_PIN56_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+ *  posedge.
+ */
+#define GPIO_PIN56_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN56_SYNC1_BYPASS_M  (GPIO_PIN56_SYNC1_BYPASS_V << GPIO_PIN56_SYNC1_BYPASS_S)
+#define GPIO_PIN56_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN56_SYNC1_BYPASS_S  3
+/** GPIO_PIN56_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+ *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+ *  at high level
+ */
+#define GPIO_PIN56_INT_TYPE    0x00000007U
+#define GPIO_PIN56_INT_TYPE_M  (GPIO_PIN56_INT_TYPE_V << GPIO_PIN56_INT_TYPE_S)
+#define GPIO_PIN56_INT_TYPE_V  0x00000007U
+#define GPIO_PIN56_INT_TYPE_S  7
+/** GPIO_PIN56_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+ */
+#define GPIO_PIN56_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN56_WAKEUP_ENABLE_M  (GPIO_PIN56_WAKEUP_ENABLE_V << GPIO_PIN56_WAKEUP_ENABLE_S)
+#define GPIO_PIN56_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN56_WAKEUP_ENABLE_S  10
+/** GPIO_PIN56_CONFIG : R/W; bitpos: [12:11]; default: 0;
+ *  reserved
+ */
+#define GPIO_PIN56_CONFIG    0x00000003U
+#define GPIO_PIN56_CONFIG_M  (GPIO_PIN56_CONFIG_V << GPIO_PIN56_CONFIG_S)
+#define GPIO_PIN56_CONFIG_V  0x00000003U
+#define GPIO_PIN56_CONFIG_S  11
+/** GPIO_PIN56_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+ *  interrupt.
+ */
+#define GPIO_PIN56_INT_ENA    0x0000001FU
+#define GPIO_PIN56_INT_ENA_M  (GPIO_PIN56_INT_ENA_V << GPIO_PIN56_INT_ENA_S)
+#define GPIO_PIN56_INT_ENA_V  0x0000001FU
+#define GPIO_PIN56_INT_ENA_S  13
+
+/** GPIO_FUNC1_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c)
+/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC1_IN_SEL    0x0000003FU
+#define GPIO_FUNC1_IN_SEL_M  (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S)
+#define GPIO_FUNC1_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC1_IN_SEL_S  0
+/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC1_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_M  (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S)
+#define GPIO_FUNC1_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_IN_INV_SEL_S  6
+/** GPIO_SIG1_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG1_IN_SEL    (BIT(7))
+#define GPIO_SIG1_IN_SEL_M  (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S)
+#define GPIO_SIG1_IN_SEL_V  0x00000001U
+#define GPIO_SIG1_IN_SEL_S  7
+
+/** GPIO_FUNC2_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160)
+/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC2_IN_SEL    0x0000003FU
+#define GPIO_FUNC2_IN_SEL_M  (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S)
+#define GPIO_FUNC2_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC2_IN_SEL_S  0
+/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC2_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_M  (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S)
+#define GPIO_FUNC2_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_IN_INV_SEL_S  6
+/** GPIO_SIG2_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG2_IN_SEL    (BIT(7))
+#define GPIO_SIG2_IN_SEL_M  (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S)
+#define GPIO_SIG2_IN_SEL_V  0x00000001U
+#define GPIO_SIG2_IN_SEL_S  7
+
+/** GPIO_FUNC3_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164)
+/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC3_IN_SEL    0x0000003FU
+#define GPIO_FUNC3_IN_SEL_M  (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S)
+#define GPIO_FUNC3_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC3_IN_SEL_S  0
+/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC3_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_M  (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S)
+#define GPIO_FUNC3_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_IN_INV_SEL_S  6
+/** GPIO_SIG3_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG3_IN_SEL    (BIT(7))
+#define GPIO_SIG3_IN_SEL_M  (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S)
+#define GPIO_SIG3_IN_SEL_V  0x00000001U
+#define GPIO_SIG3_IN_SEL_S  7
+
+/** GPIO_FUNC4_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168)
+/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC4_IN_SEL    0x0000003FU
+#define GPIO_FUNC4_IN_SEL_M  (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S)
+#define GPIO_FUNC4_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC4_IN_SEL_S  0
+/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC4_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_M  (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S)
+#define GPIO_FUNC4_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_IN_INV_SEL_S  6
+/** GPIO_SIG4_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG4_IN_SEL    (BIT(7))
+#define GPIO_SIG4_IN_SEL_M  (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S)
+#define GPIO_SIG4_IN_SEL_V  0x00000001U
+#define GPIO_SIG4_IN_SEL_S  7
+
+/** GPIO_FUNC5_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c)
+/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC5_IN_SEL    0x0000003FU
+#define GPIO_FUNC5_IN_SEL_M  (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S)
+#define GPIO_FUNC5_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC5_IN_SEL_S  0
+/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC5_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_M  (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S)
+#define GPIO_FUNC5_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_IN_INV_SEL_S  6
+/** GPIO_SIG5_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG5_IN_SEL    (BIT(7))
+#define GPIO_SIG5_IN_SEL_M  (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S)
+#define GPIO_SIG5_IN_SEL_V  0x00000001U
+#define GPIO_SIG5_IN_SEL_S  7
+
+/** GPIO_FUNC6_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170)
+/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC6_IN_SEL    0x0000003FU
+#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
+#define GPIO_FUNC6_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC6_IN_SEL_S  0
+/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
+#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_IN_INV_SEL_S  6
+/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG6_IN_SEL    (BIT(7))
+#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
+#define GPIO_SIG6_IN_SEL_V  0x00000001U
+#define GPIO_SIG6_IN_SEL_S  7
+
+/** GPIO_FUNC7_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174)
+/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC7_IN_SEL    0x0000003FU
+#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
+#define GPIO_FUNC7_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC7_IN_SEL_S  0
+/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
+#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_IN_INV_SEL_S  6
+/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG7_IN_SEL    (BIT(7))
+#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
+#define GPIO_SIG7_IN_SEL_V  0x00000001U
+#define GPIO_SIG7_IN_SEL_S  7
+
+/** GPIO_FUNC8_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178)
+/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC8_IN_SEL    0x0000003FU
+#define GPIO_FUNC8_IN_SEL_M  (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S)
+#define GPIO_FUNC8_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC8_IN_SEL_S  0
+/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_M  (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S)
+#define GPIO_FUNC8_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_IN_INV_SEL_S  6
+/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG8_IN_SEL    (BIT(7))
+#define GPIO_SIG8_IN_SEL_M  (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S)
+#define GPIO_SIG8_IN_SEL_V  0x00000001U
+#define GPIO_SIG8_IN_SEL_S  7
+
+/** GPIO_FUNC9_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c)
+/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC9_IN_SEL    0x0000003FU
+#define GPIO_FUNC9_IN_SEL_M  (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S)
+#define GPIO_FUNC9_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC9_IN_SEL_S  0
+/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_M  (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S)
+#define GPIO_FUNC9_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_IN_INV_SEL_S  6
+/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG9_IN_SEL    (BIT(7))
+#define GPIO_SIG9_IN_SEL_M  (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S)
+#define GPIO_SIG9_IN_SEL_V  0x00000001U
+#define GPIO_SIG9_IN_SEL_S  7
+
+/** GPIO_FUNC10_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180)
+/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC10_IN_SEL    0x0000003FU
+#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
+#define GPIO_FUNC10_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC10_IN_SEL_S  0
+/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
+#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_IN_INV_SEL_S  6
+/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG10_IN_SEL    (BIT(7))
+#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
+#define GPIO_SIG10_IN_SEL_V  0x00000001U
+#define GPIO_SIG10_IN_SEL_S  7
+
+/** GPIO_FUNC11_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184)
+/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC11_IN_SEL    0x0000003FU
+#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
+#define GPIO_FUNC11_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC11_IN_SEL_S  0
+/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
+#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_IN_INV_SEL_S  6
+/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG11_IN_SEL    (BIT(7))
+#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
+#define GPIO_SIG11_IN_SEL_V  0x00000001U
+#define GPIO_SIG11_IN_SEL_S  7
+
+/** GPIO_FUNC12_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188)
+/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC12_IN_SEL    0x0000003FU
+#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
+#define GPIO_FUNC12_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC12_IN_SEL_S  0
+/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
+#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_IN_INV_SEL_S  6
+/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG12_IN_SEL    (BIT(7))
+#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
+#define GPIO_SIG12_IN_SEL_V  0x00000001U
+#define GPIO_SIG12_IN_SEL_S  7
+
+/** GPIO_FUNC13_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c)
+/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC13_IN_SEL    0x0000003FU
+#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
+#define GPIO_FUNC13_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC13_IN_SEL_S  0
+/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
+#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_IN_INV_SEL_S  6
+/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG13_IN_SEL    (BIT(7))
+#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
+#define GPIO_SIG13_IN_SEL_V  0x00000001U
+#define GPIO_SIG13_IN_SEL_S  7
+
+/** GPIO_FUNC14_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190)
+/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC14_IN_SEL    0x0000003FU
+#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
+#define GPIO_FUNC14_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC14_IN_SEL_S  0
+/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
+#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_IN_INV_SEL_S  6
+/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG14_IN_SEL    (BIT(7))
+#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
+#define GPIO_SIG14_IN_SEL_V  0x00000001U
+#define GPIO_SIG14_IN_SEL_S  7
+
+/** GPIO_FUNC15_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194)
+/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC15_IN_SEL    0x0000003FU
+#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
+#define GPIO_FUNC15_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC15_IN_SEL_S  0
+/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
+#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_IN_INV_SEL_S  6
+/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG15_IN_SEL    (BIT(7))
+#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
+#define GPIO_SIG15_IN_SEL_V  0x00000001U
+#define GPIO_SIG15_IN_SEL_S  7
+
+/** GPIO_FUNC16_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198)
+/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC16_IN_SEL    0x0000003FU
+#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
+#define GPIO_FUNC16_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC16_IN_SEL_S  0
+/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
+#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_IN_INV_SEL_S  6
+/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG16_IN_SEL    (BIT(7))
+#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
+#define GPIO_SIG16_IN_SEL_V  0x00000001U
+#define GPIO_SIG16_IN_SEL_S  7
+
+/** GPIO_FUNC17_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c)
+/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC17_IN_SEL    0x0000003FU
+#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
+#define GPIO_FUNC17_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC17_IN_SEL_S  0
+/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
+#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_IN_INV_SEL_S  6
+/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG17_IN_SEL    (BIT(7))
+#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
+#define GPIO_SIG17_IN_SEL_V  0x00000001U
+#define GPIO_SIG17_IN_SEL_S  7
+
+/** GPIO_FUNC18_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0)
+/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC18_IN_SEL    0x0000003FU
+#define GPIO_FUNC18_IN_SEL_M  (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S)
+#define GPIO_FUNC18_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC18_IN_SEL_S  0
+/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC18_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_M  (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S)
+#define GPIO_FUNC18_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_IN_INV_SEL_S  6
+/** GPIO_SIG18_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG18_IN_SEL    (BIT(7))
+#define GPIO_SIG18_IN_SEL_M  (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S)
+#define GPIO_SIG18_IN_SEL_V  0x00000001U
+#define GPIO_SIG18_IN_SEL_S  7
+
+/** GPIO_FUNC19_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4)
+/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC19_IN_SEL    0x0000003FU
+#define GPIO_FUNC19_IN_SEL_M  (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S)
+#define GPIO_FUNC19_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC19_IN_SEL_S  0
+/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC19_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_M  (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S)
+#define GPIO_FUNC19_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_IN_INV_SEL_S  6
+/** GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG19_IN_SEL    (BIT(7))
+#define GPIO_SIG19_IN_SEL_M  (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S)
+#define GPIO_SIG19_IN_SEL_V  0x00000001U
+#define GPIO_SIG19_IN_SEL_S  7
+
+/** GPIO_FUNC20_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8)
+/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC20_IN_SEL    0x0000003FU
+#define GPIO_FUNC20_IN_SEL_M  (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S)
+#define GPIO_FUNC20_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC20_IN_SEL_S  0
+/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC20_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_M  (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S)
+#define GPIO_FUNC20_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_IN_INV_SEL_S  6
+/** GPIO_SIG20_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG20_IN_SEL    (BIT(7))
+#define GPIO_SIG20_IN_SEL_M  (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S)
+#define GPIO_SIG20_IN_SEL_V  0x00000001U
+#define GPIO_SIG20_IN_SEL_S  7
+
+/** GPIO_FUNC21_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac)
+/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC21_IN_SEL    0x0000003FU
+#define GPIO_FUNC21_IN_SEL_M  (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S)
+#define GPIO_FUNC21_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC21_IN_SEL_S  0
+/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC21_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_M  (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S)
+#define GPIO_FUNC21_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_IN_INV_SEL_S  6
+/** GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG21_IN_SEL    (BIT(7))
+#define GPIO_SIG21_IN_SEL_M  (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S)
+#define GPIO_SIG21_IN_SEL_V  0x00000001U
+#define GPIO_SIG21_IN_SEL_S  7
+
+/** GPIO_FUNC22_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0)
+/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC22_IN_SEL    0x0000003FU
+#define GPIO_FUNC22_IN_SEL_M  (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S)
+#define GPIO_FUNC22_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC22_IN_SEL_S  0
+/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC22_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_M  (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S)
+#define GPIO_FUNC22_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_IN_INV_SEL_S  6
+/** GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG22_IN_SEL    (BIT(7))
+#define GPIO_SIG22_IN_SEL_M  (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S)
+#define GPIO_SIG22_IN_SEL_V  0x00000001U
+#define GPIO_SIG22_IN_SEL_S  7
+
+/** GPIO_FUNC23_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4)
+/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC23_IN_SEL    0x0000003FU
+#define GPIO_FUNC23_IN_SEL_M  (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S)
+#define GPIO_FUNC23_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC23_IN_SEL_S  0
+/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC23_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_M  (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S)
+#define GPIO_FUNC23_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_IN_INV_SEL_S  6
+/** GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG23_IN_SEL    (BIT(7))
+#define GPIO_SIG23_IN_SEL_M  (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S)
+#define GPIO_SIG23_IN_SEL_V  0x00000001U
+#define GPIO_SIG23_IN_SEL_S  7
+
+/** GPIO_FUNC24_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8)
+/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC24_IN_SEL    0x0000003FU
+#define GPIO_FUNC24_IN_SEL_M  (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S)
+#define GPIO_FUNC24_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC24_IN_SEL_S  0
+/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC24_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_M  (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S)
+#define GPIO_FUNC24_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_IN_INV_SEL_S  6
+/** GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG24_IN_SEL    (BIT(7))
+#define GPIO_SIG24_IN_SEL_M  (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S)
+#define GPIO_SIG24_IN_SEL_V  0x00000001U
+#define GPIO_SIG24_IN_SEL_S  7
+
+/** GPIO_FUNC25_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc)
+/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC25_IN_SEL    0x0000003FU
+#define GPIO_FUNC25_IN_SEL_M  (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S)
+#define GPIO_FUNC25_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC25_IN_SEL_S  0
+/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC25_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_M  (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S)
+#define GPIO_FUNC25_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_IN_INV_SEL_S  6
+/** GPIO_SIG25_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG25_IN_SEL    (BIT(7))
+#define GPIO_SIG25_IN_SEL_M  (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S)
+#define GPIO_SIG25_IN_SEL_V  0x00000001U
+#define GPIO_SIG25_IN_SEL_S  7
+
+/** GPIO_FUNC26_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0)
+/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC26_IN_SEL    0x0000003FU
+#define GPIO_FUNC26_IN_SEL_M  (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S)
+#define GPIO_FUNC26_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC26_IN_SEL_S  0
+/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC26_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_M  (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S)
+#define GPIO_FUNC26_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_IN_INV_SEL_S  6
+/** GPIO_SIG26_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG26_IN_SEL    (BIT(7))
+#define GPIO_SIG26_IN_SEL_M  (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S)
+#define GPIO_SIG26_IN_SEL_V  0x00000001U
+#define GPIO_SIG26_IN_SEL_S  7
+
+/** GPIO_FUNC27_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4)
+/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC27_IN_SEL    0x0000003FU
+#define GPIO_FUNC27_IN_SEL_M  (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S)
+#define GPIO_FUNC27_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC27_IN_SEL_S  0
+/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC27_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_M  (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S)
+#define GPIO_FUNC27_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_IN_INV_SEL_S  6
+/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG27_IN_SEL    (BIT(7))
+#define GPIO_SIG27_IN_SEL_M  (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S)
+#define GPIO_SIG27_IN_SEL_V  0x00000001U
+#define GPIO_SIG27_IN_SEL_S  7
+
+/** GPIO_FUNC28_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8)
+/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC28_IN_SEL    0x0000003FU
+#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
+#define GPIO_FUNC28_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC28_IN_SEL_S  0
+/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
+#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_IN_INV_SEL_S  6
+/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG28_IN_SEL    (BIT(7))
+#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
+#define GPIO_SIG28_IN_SEL_V  0x00000001U
+#define GPIO_SIG28_IN_SEL_S  7
+
+/** GPIO_FUNC29_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc)
+/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC29_IN_SEL    0x0000003FU
+#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
+#define GPIO_FUNC29_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC29_IN_SEL_S  0
+/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
+#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_IN_INV_SEL_S  6
+/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG29_IN_SEL    (BIT(7))
+#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
+#define GPIO_SIG29_IN_SEL_V  0x00000001U
+#define GPIO_SIG29_IN_SEL_S  7
+
+/** GPIO_FUNC30_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0)
+/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC30_IN_SEL    0x0000003FU
+#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
+#define GPIO_FUNC30_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC30_IN_SEL_S  0
+/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
+#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_IN_INV_SEL_S  6
+/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG30_IN_SEL    (BIT(7))
+#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
+#define GPIO_SIG30_IN_SEL_V  0x00000001U
+#define GPIO_SIG30_IN_SEL_S  7
+
+/** GPIO_FUNC31_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4)
+/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC31_IN_SEL    0x0000003FU
+#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
+#define GPIO_FUNC31_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC31_IN_SEL_S  0
+/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
+#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_IN_INV_SEL_S  6
+/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG31_IN_SEL    (BIT(7))
+#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
+#define GPIO_SIG31_IN_SEL_V  0x00000001U
+#define GPIO_SIG31_IN_SEL_S  7
+
+/** GPIO_FUNC32_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8)
+/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC32_IN_SEL    0x0000003FU
+#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
+#define GPIO_FUNC32_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC32_IN_SEL_S  0
+/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
+#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_IN_INV_SEL_S  6
+/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG32_IN_SEL    (BIT(7))
+#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
+#define GPIO_SIG32_IN_SEL_V  0x00000001U
+#define GPIO_SIG32_IN_SEL_S  7
+
+/** GPIO_FUNC33_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc)
+/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC33_IN_SEL    0x0000003FU
+#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
+#define GPIO_FUNC33_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC33_IN_SEL_S  0
+/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
+#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_IN_INV_SEL_S  6
+/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG33_IN_SEL    (BIT(7))
+#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
+#define GPIO_SIG33_IN_SEL_V  0x00000001U
+#define GPIO_SIG33_IN_SEL_S  7
+
+/** GPIO_FUNC34_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0)
+/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC34_IN_SEL    0x0000003FU
+#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
+#define GPIO_FUNC34_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC34_IN_SEL_S  0
+/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
+#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_IN_INV_SEL_S  6
+/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG34_IN_SEL    (BIT(7))
+#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
+#define GPIO_SIG34_IN_SEL_V  0x00000001U
+#define GPIO_SIG34_IN_SEL_S  7
+
+/** GPIO_FUNC35_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4)
+/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC35_IN_SEL    0x0000003FU
+#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
+#define GPIO_FUNC35_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC35_IN_SEL_S  0
+/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
+#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_IN_INV_SEL_S  6
+/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG35_IN_SEL    (BIT(7))
+#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
+#define GPIO_SIG35_IN_SEL_V  0x00000001U
+#define GPIO_SIG35_IN_SEL_S  7
+
+/** GPIO_FUNC36_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8)
+/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC36_IN_SEL    0x0000003FU
+#define GPIO_FUNC36_IN_SEL_M  (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S)
+#define GPIO_FUNC36_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC36_IN_SEL_S  0
+/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC36_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_M  (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S)
+#define GPIO_FUNC36_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_IN_INV_SEL_S  6
+/** GPIO_SIG36_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG36_IN_SEL    (BIT(7))
+#define GPIO_SIG36_IN_SEL_M  (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S)
+#define GPIO_SIG36_IN_SEL_V  0x00000001U
+#define GPIO_SIG36_IN_SEL_S  7
+
+/** GPIO_FUNC37_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec)
+/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC37_IN_SEL    0x0000003FU
+#define GPIO_FUNC37_IN_SEL_M  (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S)
+#define GPIO_FUNC37_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC37_IN_SEL_S  0
+/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC37_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_M  (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S)
+#define GPIO_FUNC37_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_IN_INV_SEL_S  6
+/** GPIO_SIG37_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG37_IN_SEL    (BIT(7))
+#define GPIO_SIG37_IN_SEL_M  (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S)
+#define GPIO_SIG37_IN_SEL_V  0x00000001U
+#define GPIO_SIG37_IN_SEL_S  7
+
+/** GPIO_FUNC38_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0)
+/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC38_IN_SEL    0x0000003FU
+#define GPIO_FUNC38_IN_SEL_M  (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S)
+#define GPIO_FUNC38_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC38_IN_SEL_S  0
+/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC38_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_M  (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S)
+#define GPIO_FUNC38_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_IN_INV_SEL_S  6
+/** GPIO_SIG38_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG38_IN_SEL    (BIT(7))
+#define GPIO_SIG38_IN_SEL_M  (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S)
+#define GPIO_SIG38_IN_SEL_V  0x00000001U
+#define GPIO_SIG38_IN_SEL_S  7
+
+/** GPIO_FUNC39_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4)
+/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC39_IN_SEL    0x0000003FU
+#define GPIO_FUNC39_IN_SEL_M  (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S)
+#define GPIO_FUNC39_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC39_IN_SEL_S  0
+/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC39_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_M  (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S)
+#define GPIO_FUNC39_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_IN_INV_SEL_S  6
+/** GPIO_SIG39_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG39_IN_SEL    (BIT(7))
+#define GPIO_SIG39_IN_SEL_M  (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S)
+#define GPIO_SIG39_IN_SEL_V  0x00000001U
+#define GPIO_SIG39_IN_SEL_S  7
+
+/** GPIO_FUNC40_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8)
+/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC40_IN_SEL    0x0000003FU
+#define GPIO_FUNC40_IN_SEL_M  (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S)
+#define GPIO_FUNC40_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC40_IN_SEL_S  0
+/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC40_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_M  (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S)
+#define GPIO_FUNC40_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_IN_INV_SEL_S  6
+/** GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG40_IN_SEL    (BIT(7))
+#define GPIO_SIG40_IN_SEL_M  (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S)
+#define GPIO_SIG40_IN_SEL_V  0x00000001U
+#define GPIO_SIG40_IN_SEL_S  7
+
+/** GPIO_FUNC41_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc)
+/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC41_IN_SEL    0x0000003FU
+#define GPIO_FUNC41_IN_SEL_M  (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S)
+#define GPIO_FUNC41_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC41_IN_SEL_S  0
+/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_M  (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S)
+#define GPIO_FUNC41_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_IN_INV_SEL_S  6
+/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG41_IN_SEL    (BIT(7))
+#define GPIO_SIG41_IN_SEL_M  (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S)
+#define GPIO_SIG41_IN_SEL_V  0x00000001U
+#define GPIO_SIG41_IN_SEL_S  7
+
+/** GPIO_FUNC42_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200)
+/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC42_IN_SEL    0x0000003FU
+#define GPIO_FUNC42_IN_SEL_M  (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S)
+#define GPIO_FUNC42_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC42_IN_SEL_S  0
+/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_M  (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S)
+#define GPIO_FUNC42_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_IN_INV_SEL_S  6
+/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG42_IN_SEL    (BIT(7))
+#define GPIO_SIG42_IN_SEL_M  (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S)
+#define GPIO_SIG42_IN_SEL_V  0x00000001U
+#define GPIO_SIG42_IN_SEL_S  7
+
+/** GPIO_FUNC43_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204)
+/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC43_IN_SEL    0x0000003FU
+#define GPIO_FUNC43_IN_SEL_M  (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S)
+#define GPIO_FUNC43_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC43_IN_SEL_S  0
+/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC43_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_M  (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S)
+#define GPIO_FUNC43_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_IN_INV_SEL_S  6
+/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG43_IN_SEL    (BIT(7))
+#define GPIO_SIG43_IN_SEL_M  (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S)
+#define GPIO_SIG43_IN_SEL_V  0x00000001U
+#define GPIO_SIG43_IN_SEL_S  7
+
+/** GPIO_FUNC44_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208)
+/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC44_IN_SEL    0x0000003FU
+#define GPIO_FUNC44_IN_SEL_M  (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S)
+#define GPIO_FUNC44_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC44_IN_SEL_S  0
+/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC44_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_M  (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S)
+#define GPIO_FUNC44_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_IN_INV_SEL_S  6
+/** GPIO_SIG44_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG44_IN_SEL    (BIT(7))
+#define GPIO_SIG44_IN_SEL_M  (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S)
+#define GPIO_SIG44_IN_SEL_V  0x00000001U
+#define GPIO_SIG44_IN_SEL_S  7
+
+/** GPIO_FUNC45_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c)
+/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC45_IN_SEL    0x0000003FU
+#define GPIO_FUNC45_IN_SEL_M  (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S)
+#define GPIO_FUNC45_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC45_IN_SEL_S  0
+/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC45_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_M  (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S)
+#define GPIO_FUNC45_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_IN_INV_SEL_S  6
+/** GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG45_IN_SEL    (BIT(7))
+#define GPIO_SIG45_IN_SEL_M  (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S)
+#define GPIO_SIG45_IN_SEL_V  0x00000001U
+#define GPIO_SIG45_IN_SEL_S  7
+
+/** GPIO_FUNC47_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214)
+/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC47_IN_SEL    0x0000003FU
+#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
+#define GPIO_FUNC47_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC47_IN_SEL_S  0
+/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
+#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_IN_INV_SEL_S  6
+/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG47_IN_SEL    (BIT(7))
+#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
+#define GPIO_SIG47_IN_SEL_V  0x00000001U
+#define GPIO_SIG47_IN_SEL_S  7
+
+/** GPIO_FUNC48_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218)
+/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC48_IN_SEL    0x0000003FU
+#define GPIO_FUNC48_IN_SEL_M  (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S)
+#define GPIO_FUNC48_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC48_IN_SEL_S  0
+/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC48_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_M  (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S)
+#define GPIO_FUNC48_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_IN_INV_SEL_S  6
+/** GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG48_IN_SEL    (BIT(7))
+#define GPIO_SIG48_IN_SEL_M  (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S)
+#define GPIO_SIG48_IN_SEL_V  0x00000001U
+#define GPIO_SIG48_IN_SEL_S  7
+
+/** GPIO_FUNC49_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c)
+/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC49_IN_SEL    0x0000003FU
+#define GPIO_FUNC49_IN_SEL_M  (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S)
+#define GPIO_FUNC49_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC49_IN_SEL_S  0
+/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC49_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_M  (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S)
+#define GPIO_FUNC49_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_IN_INV_SEL_S  6
+/** GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG49_IN_SEL    (BIT(7))
+#define GPIO_SIG49_IN_SEL_M  (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S)
+#define GPIO_SIG49_IN_SEL_V  0x00000001U
+#define GPIO_SIG49_IN_SEL_S  7
+
+/** GPIO_FUNC50_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220)
+/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC50_IN_SEL    0x0000003FU
+#define GPIO_FUNC50_IN_SEL_M  (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S)
+#define GPIO_FUNC50_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC50_IN_SEL_S  0
+/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC50_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_M  (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S)
+#define GPIO_FUNC50_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_IN_INV_SEL_S  6
+/** GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG50_IN_SEL    (BIT(7))
+#define GPIO_SIG50_IN_SEL_M  (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S)
+#define GPIO_SIG50_IN_SEL_V  0x00000001U
+#define GPIO_SIG50_IN_SEL_S  7
+
+/** GPIO_FUNC51_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224)
+/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC51_IN_SEL    0x0000003FU
+#define GPIO_FUNC51_IN_SEL_M  (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S)
+#define GPIO_FUNC51_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC51_IN_SEL_S  0
+/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC51_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_M  (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S)
+#define GPIO_FUNC51_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_IN_INV_SEL_S  6
+/** GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG51_IN_SEL    (BIT(7))
+#define GPIO_SIG51_IN_SEL_M  (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S)
+#define GPIO_SIG51_IN_SEL_V  0x00000001U
+#define GPIO_SIG51_IN_SEL_S  7
+
+/** GPIO_FUNC52_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228)
+/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC52_IN_SEL    0x0000003FU
+#define GPIO_FUNC52_IN_SEL_M  (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S)
+#define GPIO_FUNC52_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC52_IN_SEL_S  0
+/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC52_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_M  (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S)
+#define GPIO_FUNC52_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_IN_INV_SEL_S  6
+/** GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG52_IN_SEL    (BIT(7))
+#define GPIO_SIG52_IN_SEL_M  (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S)
+#define GPIO_SIG52_IN_SEL_V  0x00000001U
+#define GPIO_SIG52_IN_SEL_S  7
+
+/** GPIO_FUNC53_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c)
+/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC53_IN_SEL    0x0000003FU
+#define GPIO_FUNC53_IN_SEL_M  (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S)
+#define GPIO_FUNC53_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC53_IN_SEL_S  0
+/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC53_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_M  (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S)
+#define GPIO_FUNC53_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_IN_INV_SEL_S  6
+/** GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG53_IN_SEL    (BIT(7))
+#define GPIO_SIG53_IN_SEL_M  (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S)
+#define GPIO_SIG53_IN_SEL_V  0x00000001U
+#define GPIO_SIG53_IN_SEL_S  7
+
+/** GPIO_FUNC54_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230)
+/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC54_IN_SEL    0x0000003FU
+#define GPIO_FUNC54_IN_SEL_M  (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S)
+#define GPIO_FUNC54_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC54_IN_SEL_S  0
+/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC54_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_M  (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S)
+#define GPIO_FUNC54_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_IN_INV_SEL_S  6
+/** GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG54_IN_SEL    (BIT(7))
+#define GPIO_SIG54_IN_SEL_M  (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S)
+#define GPIO_SIG54_IN_SEL_V  0x00000001U
+#define GPIO_SIG54_IN_SEL_S  7
+
+/** GPIO_FUNC55_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234)
+/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC55_IN_SEL    0x0000003FU
+#define GPIO_FUNC55_IN_SEL_M  (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S)
+#define GPIO_FUNC55_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC55_IN_SEL_S  0
+/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC55_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_M  (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S)
+#define GPIO_FUNC55_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_IN_INV_SEL_S  6
+/** GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG55_IN_SEL    (BIT(7))
+#define GPIO_SIG55_IN_SEL_M  (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S)
+#define GPIO_SIG55_IN_SEL_V  0x00000001U
+#define GPIO_SIG55_IN_SEL_S  7
+
+/** GPIO_FUNC56_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238)
+/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC56_IN_SEL    0x0000003FU
+#define GPIO_FUNC56_IN_SEL_M  (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S)
+#define GPIO_FUNC56_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC56_IN_SEL_S  0
+/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC56_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_M  (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S)
+#define GPIO_FUNC56_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_IN_INV_SEL_S  6
+/** GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG56_IN_SEL    (BIT(7))
+#define GPIO_SIG56_IN_SEL_M  (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S)
+#define GPIO_SIG56_IN_SEL_V  0x00000001U
+#define GPIO_SIG56_IN_SEL_S  7
+
+/** GPIO_FUNC57_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c)
+/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC57_IN_SEL    0x0000003FU
+#define GPIO_FUNC57_IN_SEL_M  (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S)
+#define GPIO_FUNC57_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC57_IN_SEL_S  0
+/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC57_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_M  (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S)
+#define GPIO_FUNC57_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC57_IN_INV_SEL_S  6
+/** GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG57_IN_SEL    (BIT(7))
+#define GPIO_SIG57_IN_SEL_M  (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S)
+#define GPIO_SIG57_IN_SEL_V  0x00000001U
+#define GPIO_SIG57_IN_SEL_S  7
+
+/** GPIO_FUNC58_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240)
+/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC58_IN_SEL    0x0000003FU
+#define GPIO_FUNC58_IN_SEL_M  (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S)
+#define GPIO_FUNC58_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC58_IN_SEL_S  0
+/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC58_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_M  (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S)
+#define GPIO_FUNC58_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC58_IN_INV_SEL_S  6
+/** GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG58_IN_SEL    (BIT(7))
+#define GPIO_SIG58_IN_SEL_M  (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S)
+#define GPIO_SIG58_IN_SEL_V  0x00000001U
+#define GPIO_SIG58_IN_SEL_S  7
+
+/** GPIO_FUNC59_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244)
+/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC59_IN_SEL    0x0000003FU
+#define GPIO_FUNC59_IN_SEL_M  (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S)
+#define GPIO_FUNC59_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC59_IN_SEL_S  0
+/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC59_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_M  (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S)
+#define GPIO_FUNC59_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC59_IN_INV_SEL_S  6
+/** GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG59_IN_SEL    (BIT(7))
+#define GPIO_SIG59_IN_SEL_M  (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S)
+#define GPIO_SIG59_IN_SEL_V  0x00000001U
+#define GPIO_SIG59_IN_SEL_S  7
+
+/** GPIO_FUNC60_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248)
+/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC60_IN_SEL    0x0000003FU
+#define GPIO_FUNC60_IN_SEL_M  (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S)
+#define GPIO_FUNC60_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC60_IN_SEL_S  0
+/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC60_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_M  (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S)
+#define GPIO_FUNC60_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC60_IN_INV_SEL_S  6
+/** GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG60_IN_SEL    (BIT(7))
+#define GPIO_SIG60_IN_SEL_M  (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S)
+#define GPIO_SIG60_IN_SEL_V  0x00000001U
+#define GPIO_SIG60_IN_SEL_S  7
+
+/** GPIO_FUNC61_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c)
+/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC61_IN_SEL    0x0000003FU
+#define GPIO_FUNC61_IN_SEL_M  (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S)
+#define GPIO_FUNC61_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC61_IN_SEL_S  0
+/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC61_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_M  (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S)
+#define GPIO_FUNC61_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC61_IN_INV_SEL_S  6
+/** GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG61_IN_SEL    (BIT(7))
+#define GPIO_SIG61_IN_SEL_M  (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S)
+#define GPIO_SIG61_IN_SEL_V  0x00000001U
+#define GPIO_SIG61_IN_SEL_S  7
+
+/** GPIO_FUNC62_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250)
+/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC62_IN_SEL    0x0000003FU
+#define GPIO_FUNC62_IN_SEL_M  (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S)
+#define GPIO_FUNC62_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC62_IN_SEL_S  0
+/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC62_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_M  (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S)
+#define GPIO_FUNC62_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC62_IN_INV_SEL_S  6
+/** GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG62_IN_SEL    (BIT(7))
+#define GPIO_SIG62_IN_SEL_M  (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S)
+#define GPIO_SIG62_IN_SEL_V  0x00000001U
+#define GPIO_SIG62_IN_SEL_S  7
+
+/** GPIO_FUNC63_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254)
+/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC63_IN_SEL    0x0000003FU
+#define GPIO_FUNC63_IN_SEL_M  (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S)
+#define GPIO_FUNC63_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC63_IN_SEL_S  0
+/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC63_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_M  (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S)
+#define GPIO_FUNC63_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC63_IN_INV_SEL_S  6
+/** GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG63_IN_SEL    (BIT(7))
+#define GPIO_SIG63_IN_SEL_M  (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S)
+#define GPIO_SIG63_IN_SEL_V  0x00000001U
+#define GPIO_SIG63_IN_SEL_S  7
+
+/** GPIO_FUNC64_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258)
+/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC64_IN_SEL    0x0000003FU
+#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
+#define GPIO_FUNC64_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC64_IN_SEL_S  0
+/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
+#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC64_IN_INV_SEL_S  6
+/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG64_IN_SEL    (BIT(7))
+#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
+#define GPIO_SIG64_IN_SEL_V  0x00000001U
+#define GPIO_SIG64_IN_SEL_S  7
+
+/** GPIO_FUNC65_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c)
+/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC65_IN_SEL    0x0000003FU
+#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
+#define GPIO_FUNC65_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC65_IN_SEL_S  0
+/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
+#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC65_IN_INV_SEL_S  6
+/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG65_IN_SEL    (BIT(7))
+#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
+#define GPIO_SIG65_IN_SEL_V  0x00000001U
+#define GPIO_SIG65_IN_SEL_S  7
+
+/** GPIO_FUNC66_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260)
+/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC66_IN_SEL    0x0000003FU
+#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
+#define GPIO_FUNC66_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC66_IN_SEL_S  0
+/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
+#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC66_IN_INV_SEL_S  6
+/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG66_IN_SEL    (BIT(7))
+#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
+#define GPIO_SIG66_IN_SEL_V  0x00000001U
+#define GPIO_SIG66_IN_SEL_S  7
+
+/** GPIO_FUNC68_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268)
+/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC68_IN_SEL    0x0000003FU
+#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
+#define GPIO_FUNC68_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC68_IN_SEL_S  0
+/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
+#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC68_IN_INV_SEL_S  6
+/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG68_IN_SEL    (BIT(7))
+#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
+#define GPIO_SIG68_IN_SEL_V  0x00000001U
+#define GPIO_SIG68_IN_SEL_S  7
+
+/** GPIO_FUNC69_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c)
+/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC69_IN_SEL    0x0000003FU
+#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
+#define GPIO_FUNC69_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC69_IN_SEL_S  0
+/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
+#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC69_IN_INV_SEL_S  6
+/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG69_IN_SEL    (BIT(7))
+#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
+#define GPIO_SIG69_IN_SEL_V  0x00000001U
+#define GPIO_SIG69_IN_SEL_S  7
+
+/** GPIO_FUNC70_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270)
+/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC70_IN_SEL    0x0000003FU
+#define GPIO_FUNC70_IN_SEL_M  (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S)
+#define GPIO_FUNC70_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC70_IN_SEL_S  0
+/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC70_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_M  (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S)
+#define GPIO_FUNC70_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC70_IN_INV_SEL_S  6
+/** GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG70_IN_SEL    (BIT(7))
+#define GPIO_SIG70_IN_SEL_M  (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S)
+#define GPIO_SIG70_IN_SEL_V  0x00000001U
+#define GPIO_SIG70_IN_SEL_S  7
+
+/** GPIO_FUNC71_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274)
+/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC71_IN_SEL    0x0000003FU
+#define GPIO_FUNC71_IN_SEL_M  (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S)
+#define GPIO_FUNC71_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC71_IN_SEL_S  0
+/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC71_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_M  (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S)
+#define GPIO_FUNC71_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC71_IN_INV_SEL_S  6
+/** GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG71_IN_SEL    (BIT(7))
+#define GPIO_SIG71_IN_SEL_M  (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S)
+#define GPIO_SIG71_IN_SEL_V  0x00000001U
+#define GPIO_SIG71_IN_SEL_S  7
+
+/** GPIO_FUNC74_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280)
+/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC74_IN_SEL    0x0000003FU
+#define GPIO_FUNC74_IN_SEL_M  (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S)
+#define GPIO_FUNC74_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC74_IN_SEL_S  0
+/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC74_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_M  (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S)
+#define GPIO_FUNC74_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC74_IN_INV_SEL_S  6
+/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG74_IN_SEL    (BIT(7))
+#define GPIO_SIG74_IN_SEL_M  (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S)
+#define GPIO_SIG74_IN_SEL_V  0x00000001U
+#define GPIO_SIG74_IN_SEL_S  7
+
+/** GPIO_FUNC75_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284)
+/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC75_IN_SEL    0x0000003FU
+#define GPIO_FUNC75_IN_SEL_M  (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S)
+#define GPIO_FUNC75_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC75_IN_SEL_S  0
+/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC75_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_M  (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S)
+#define GPIO_FUNC75_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC75_IN_INV_SEL_S  6
+/** GPIO_SIG75_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG75_IN_SEL    (BIT(7))
+#define GPIO_SIG75_IN_SEL_M  (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S)
+#define GPIO_SIG75_IN_SEL_V  0x00000001U
+#define GPIO_SIG75_IN_SEL_S  7
+
+/** GPIO_FUNC76_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288)
+/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC76_IN_SEL    0x0000003FU
+#define GPIO_FUNC76_IN_SEL_M  (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S)
+#define GPIO_FUNC76_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC76_IN_SEL_S  0
+/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC76_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_M  (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S)
+#define GPIO_FUNC76_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC76_IN_INV_SEL_S  6
+/** GPIO_SIG76_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG76_IN_SEL    (BIT(7))
+#define GPIO_SIG76_IN_SEL_M  (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S)
+#define GPIO_SIG76_IN_SEL_V  0x00000001U
+#define GPIO_SIG76_IN_SEL_S  7
+
+/** GPIO_FUNC77_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c)
+/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC77_IN_SEL    0x0000003FU
+#define GPIO_FUNC77_IN_SEL_M  (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S)
+#define GPIO_FUNC77_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC77_IN_SEL_S  0
+/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC77_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_M  (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S)
+#define GPIO_FUNC77_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC77_IN_INV_SEL_S  6
+/** GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG77_IN_SEL    (BIT(7))
+#define GPIO_SIG77_IN_SEL_M  (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S)
+#define GPIO_SIG77_IN_SEL_V  0x00000001U
+#define GPIO_SIG77_IN_SEL_S  7
+
+/** GPIO_FUNC78_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290)
+/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC78_IN_SEL    0x0000003FU
+#define GPIO_FUNC78_IN_SEL_M  (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S)
+#define GPIO_FUNC78_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC78_IN_SEL_S  0
+/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC78_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_M  (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S)
+#define GPIO_FUNC78_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC78_IN_INV_SEL_S  6
+/** GPIO_SIG78_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG78_IN_SEL    (BIT(7))
+#define GPIO_SIG78_IN_SEL_M  (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S)
+#define GPIO_SIG78_IN_SEL_V  0x00000001U
+#define GPIO_SIG78_IN_SEL_S  7
+
+/** GPIO_FUNC80_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298)
+/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC80_IN_SEL    0x0000003FU
+#define GPIO_FUNC80_IN_SEL_M  (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S)
+#define GPIO_FUNC80_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC80_IN_SEL_S  0
+/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC80_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_M  (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S)
+#define GPIO_FUNC80_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC80_IN_INV_SEL_S  6
+/** GPIO_SIG80_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG80_IN_SEL    (BIT(7))
+#define GPIO_SIG80_IN_SEL_M  (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S)
+#define GPIO_SIG80_IN_SEL_V  0x00000001U
+#define GPIO_SIG80_IN_SEL_S  7
+
+/** GPIO_FUNC83_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4)
+/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC83_IN_SEL    0x0000003FU
+#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
+#define GPIO_FUNC83_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC83_IN_SEL_S  0
+/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
+#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC83_IN_INV_SEL_S  6
+/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG83_IN_SEL    (BIT(7))
+#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
+#define GPIO_SIG83_IN_SEL_V  0x00000001U
+#define GPIO_SIG83_IN_SEL_S  7
+
+/** GPIO_FUNC86_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0)
+/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC86_IN_SEL    0x0000003FU
+#define GPIO_FUNC86_IN_SEL_M  (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S)
+#define GPIO_FUNC86_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC86_IN_SEL_S  0
+/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC86_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_M  (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S)
+#define GPIO_FUNC86_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC86_IN_INV_SEL_S  6
+/** GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG86_IN_SEL    (BIT(7))
+#define GPIO_SIG86_IN_SEL_M  (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S)
+#define GPIO_SIG86_IN_SEL_V  0x00000001U
+#define GPIO_SIG86_IN_SEL_S  7
+
+/** GPIO_FUNC89_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc)
+/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC89_IN_SEL    0x0000003FU
+#define GPIO_FUNC89_IN_SEL_M  (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S)
+#define GPIO_FUNC89_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC89_IN_SEL_S  0
+/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC89_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_M  (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S)
+#define GPIO_FUNC89_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC89_IN_INV_SEL_S  6
+/** GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG89_IN_SEL    (BIT(7))
+#define GPIO_SIG89_IN_SEL_M  (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S)
+#define GPIO_SIG89_IN_SEL_V  0x00000001U
+#define GPIO_SIG89_IN_SEL_S  7
+
+/** GPIO_FUNC90_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0)
+/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC90_IN_SEL    0x0000003FU
+#define GPIO_FUNC90_IN_SEL_M  (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S)
+#define GPIO_FUNC90_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC90_IN_SEL_S  0
+/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC90_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_M  (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S)
+#define GPIO_FUNC90_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC90_IN_INV_SEL_S  6
+/** GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG90_IN_SEL    (BIT(7))
+#define GPIO_SIG90_IN_SEL_M  (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S)
+#define GPIO_SIG90_IN_SEL_V  0x00000001U
+#define GPIO_SIG90_IN_SEL_S  7
+
+/** GPIO_FUNC91_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4)
+/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC91_IN_SEL    0x0000003FU
+#define GPIO_FUNC91_IN_SEL_M  (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S)
+#define GPIO_FUNC91_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC91_IN_SEL_S  0
+/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC91_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_M  (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S)
+#define GPIO_FUNC91_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC91_IN_INV_SEL_S  6
+/** GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG91_IN_SEL    (BIT(7))
+#define GPIO_SIG91_IN_SEL_M  (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S)
+#define GPIO_SIG91_IN_SEL_V  0x00000001U
+#define GPIO_SIG91_IN_SEL_S  7
+
+/** GPIO_FUNC92_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8)
+/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC92_IN_SEL    0x0000003FU
+#define GPIO_FUNC92_IN_SEL_M  (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S)
+#define GPIO_FUNC92_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC92_IN_SEL_S  0
+/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC92_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_M  (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S)
+#define GPIO_FUNC92_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC92_IN_INV_SEL_S  6
+/** GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG92_IN_SEL    (BIT(7))
+#define GPIO_SIG92_IN_SEL_M  (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S)
+#define GPIO_SIG92_IN_SEL_V  0x00000001U
+#define GPIO_SIG92_IN_SEL_S  7
+
+/** GPIO_FUNC93_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc)
+/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC93_IN_SEL    0x0000003FU
+#define GPIO_FUNC93_IN_SEL_M  (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S)
+#define GPIO_FUNC93_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC93_IN_SEL_S  0
+/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC93_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_M  (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S)
+#define GPIO_FUNC93_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC93_IN_INV_SEL_S  6
+/** GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG93_IN_SEL    (BIT(7))
+#define GPIO_SIG93_IN_SEL_M  (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S)
+#define GPIO_SIG93_IN_SEL_V  0x00000001U
+#define GPIO_SIG93_IN_SEL_S  7
+
+/** GPIO_FUNC94_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0)
+/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC94_IN_SEL    0x0000003FU
+#define GPIO_FUNC94_IN_SEL_M  (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S)
+#define GPIO_FUNC94_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC94_IN_SEL_S  0
+/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC94_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_M  (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S)
+#define GPIO_FUNC94_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC94_IN_INV_SEL_S  6
+/** GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG94_IN_SEL    (BIT(7))
+#define GPIO_SIG94_IN_SEL_M  (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S)
+#define GPIO_SIG94_IN_SEL_V  0x00000001U
+#define GPIO_SIG94_IN_SEL_S  7
+
+/** GPIO_FUNC95_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4)
+/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC95_IN_SEL    0x0000003FU
+#define GPIO_FUNC95_IN_SEL_M  (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S)
+#define GPIO_FUNC95_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC95_IN_SEL_S  0
+/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC95_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_M  (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S)
+#define GPIO_FUNC95_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC95_IN_INV_SEL_S  6
+/** GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG95_IN_SEL    (BIT(7))
+#define GPIO_SIG95_IN_SEL_M  (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S)
+#define GPIO_SIG95_IN_SEL_V  0x00000001U
+#define GPIO_SIG95_IN_SEL_S  7
+
+/** GPIO_FUNC96_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8)
+/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC96_IN_SEL    0x0000003FU
+#define GPIO_FUNC96_IN_SEL_M  (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S)
+#define GPIO_FUNC96_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC96_IN_SEL_S  0
+/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC96_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_M  (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S)
+#define GPIO_FUNC96_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC96_IN_INV_SEL_S  6
+/** GPIO_SIG96_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG96_IN_SEL    (BIT(7))
+#define GPIO_SIG96_IN_SEL_M  (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S)
+#define GPIO_SIG96_IN_SEL_V  0x00000001U
+#define GPIO_SIG96_IN_SEL_S  7
+
+/** GPIO_FUNC97_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc)
+/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC97_IN_SEL    0x0000003FU
+#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
+#define GPIO_FUNC97_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC97_IN_SEL_S  0
+/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
+#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC97_IN_INV_SEL_S  6
+/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG97_IN_SEL    (BIT(7))
+#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
+#define GPIO_SIG97_IN_SEL_V  0x00000001U
+#define GPIO_SIG97_IN_SEL_S  7
+
+/** GPIO_FUNC98_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0)
+/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC98_IN_SEL    0x0000003FU
+#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
+#define GPIO_FUNC98_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC98_IN_SEL_S  0
+/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
+#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC98_IN_INV_SEL_S  6
+/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG98_IN_SEL    (BIT(7))
+#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
+#define GPIO_SIG98_IN_SEL_V  0x00000001U
+#define GPIO_SIG98_IN_SEL_S  7
+
+/** GPIO_FUNC99_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4)
+/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC99_IN_SEL    0x0000003FU
+#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
+#define GPIO_FUNC99_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC99_IN_SEL_S  0
+/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
+#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC99_IN_INV_SEL_S  6
+/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG99_IN_SEL    (BIT(7))
+#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
+#define GPIO_SIG99_IN_SEL_V  0x00000001U
+#define GPIO_SIG99_IN_SEL_S  7
+
+/** GPIO_FUNC100_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8)
+/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC100_IN_SEL    0x0000003FU
+#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
+#define GPIO_FUNC100_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC100_IN_SEL_S  0
+/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
+#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC100_IN_INV_SEL_S  6
+/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG100_IN_SEL    (BIT(7))
+#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
+#define GPIO_SIG100_IN_SEL_V  0x00000001U
+#define GPIO_SIG100_IN_SEL_S  7
+
+/** GPIO_FUNC101_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec)
+/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC101_IN_SEL    0x0000003FU
+#define GPIO_FUNC101_IN_SEL_M  (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S)
+#define GPIO_FUNC101_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC101_IN_SEL_S  0
+/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC101_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_M  (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S)
+#define GPIO_FUNC101_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC101_IN_INV_SEL_S  6
+/** GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG101_IN_SEL    (BIT(7))
+#define GPIO_SIG101_IN_SEL_M  (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S)
+#define GPIO_SIG101_IN_SEL_V  0x00000001U
+#define GPIO_SIG101_IN_SEL_S  7
+
+/** GPIO_FUNC102_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0)
+/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC102_IN_SEL    0x0000003FU
+#define GPIO_FUNC102_IN_SEL_M  (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S)
+#define GPIO_FUNC102_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC102_IN_SEL_S  0
+/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC102_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_M  (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S)
+#define GPIO_FUNC102_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC102_IN_INV_SEL_S  6
+/** GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG102_IN_SEL    (BIT(7))
+#define GPIO_SIG102_IN_SEL_M  (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S)
+#define GPIO_SIG102_IN_SEL_V  0x00000001U
+#define GPIO_SIG102_IN_SEL_S  7
+
+/** GPIO_FUNC103_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
+/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC103_IN_SEL    0x0000003FU
+#define GPIO_FUNC103_IN_SEL_M  (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S)
+#define GPIO_FUNC103_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC103_IN_SEL_S  0
+/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC103_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_M  (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S)
+#define GPIO_FUNC103_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC103_IN_INV_SEL_S  6
+/** GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG103_IN_SEL    (BIT(7))
+#define GPIO_SIG103_IN_SEL_M  (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S)
+#define GPIO_SIG103_IN_SEL_V  0x00000001U
+#define GPIO_SIG103_IN_SEL_S  7
+
+/** GPIO_FUNC104_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
+/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC104_IN_SEL    0x0000003FU
+#define GPIO_FUNC104_IN_SEL_M  (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S)
+#define GPIO_FUNC104_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC104_IN_SEL_S  0
+/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC104_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_M  (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S)
+#define GPIO_FUNC104_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC104_IN_INV_SEL_S  6
+/** GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG104_IN_SEL    (BIT(7))
+#define GPIO_SIG104_IN_SEL_M  (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S)
+#define GPIO_SIG104_IN_SEL_V  0x00000001U
+#define GPIO_SIG104_IN_SEL_S  7
+
+/** GPIO_FUNC105_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
+/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC105_IN_SEL    0x0000003FU
+#define GPIO_FUNC105_IN_SEL_M  (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S)
+#define GPIO_FUNC105_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC105_IN_SEL_S  0
+/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC105_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_M  (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S)
+#define GPIO_FUNC105_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC105_IN_INV_SEL_S  6
+/** GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG105_IN_SEL    (BIT(7))
+#define GPIO_SIG105_IN_SEL_M  (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S)
+#define GPIO_SIG105_IN_SEL_V  0x00000001U
+#define GPIO_SIG105_IN_SEL_S  7
+
+/** GPIO_FUNC106_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
+/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC106_IN_SEL    0x0000003FU
+#define GPIO_FUNC106_IN_SEL_M  (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S)
+#define GPIO_FUNC106_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC106_IN_SEL_S  0
+/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC106_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_M  (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S)
+#define GPIO_FUNC106_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC106_IN_INV_SEL_S  6
+/** GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG106_IN_SEL    (BIT(7))
+#define GPIO_SIG106_IN_SEL_M  (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S)
+#define GPIO_SIG106_IN_SEL_V  0x00000001U
+#define GPIO_SIG106_IN_SEL_S  7
+
+/** GPIO_FUNC107_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
+/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC107_IN_SEL    0x0000003FU
+#define GPIO_FUNC107_IN_SEL_M  (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S)
+#define GPIO_FUNC107_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC107_IN_SEL_S  0
+/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC107_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_M  (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S)
+#define GPIO_FUNC107_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC107_IN_INV_SEL_S  6
+/** GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG107_IN_SEL    (BIT(7))
+#define GPIO_SIG107_IN_SEL_M  (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S)
+#define GPIO_SIG107_IN_SEL_V  0x00000001U
+#define GPIO_SIG107_IN_SEL_S  7
+
+/** GPIO_FUNC108_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
+/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC108_IN_SEL    0x0000003FU
+#define GPIO_FUNC108_IN_SEL_M  (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S)
+#define GPIO_FUNC108_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC108_IN_SEL_S  0
+/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC108_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_M  (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S)
+#define GPIO_FUNC108_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC108_IN_INV_SEL_S  6
+/** GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG108_IN_SEL    (BIT(7))
+#define GPIO_SIG108_IN_SEL_M  (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S)
+#define GPIO_SIG108_IN_SEL_V  0x00000001U
+#define GPIO_SIG108_IN_SEL_S  7
+
+/** GPIO_FUNC109_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c)
+/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC109_IN_SEL    0x0000003FU
+#define GPIO_FUNC109_IN_SEL_M  (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S)
+#define GPIO_FUNC109_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC109_IN_SEL_S  0
+/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC109_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_M  (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S)
+#define GPIO_FUNC109_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC109_IN_INV_SEL_S  6
+/** GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG109_IN_SEL    (BIT(7))
+#define GPIO_SIG109_IN_SEL_M  (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S)
+#define GPIO_SIG109_IN_SEL_V  0x00000001U
+#define GPIO_SIG109_IN_SEL_S  7
+
+/** GPIO_FUNC110_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310)
+/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC110_IN_SEL    0x0000003FU
+#define GPIO_FUNC110_IN_SEL_M  (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S)
+#define GPIO_FUNC110_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC110_IN_SEL_S  0
+/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC110_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_M  (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S)
+#define GPIO_FUNC110_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC110_IN_INV_SEL_S  6
+/** GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG110_IN_SEL    (BIT(7))
+#define GPIO_SIG110_IN_SEL_M  (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S)
+#define GPIO_SIG110_IN_SEL_V  0x00000001U
+#define GPIO_SIG110_IN_SEL_S  7
+
+/** GPIO_FUNC111_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314)
+/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC111_IN_SEL    0x0000003FU
+#define GPIO_FUNC111_IN_SEL_M  (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S)
+#define GPIO_FUNC111_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC111_IN_SEL_S  0
+/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC111_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_M  (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S)
+#define GPIO_FUNC111_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC111_IN_INV_SEL_S  6
+/** GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG111_IN_SEL    (BIT(7))
+#define GPIO_SIG111_IN_SEL_M  (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S)
+#define GPIO_SIG111_IN_SEL_V  0x00000001U
+#define GPIO_SIG111_IN_SEL_S  7
+
+/** GPIO_FUNC112_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318)
+/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC112_IN_SEL    0x0000003FU
+#define GPIO_FUNC112_IN_SEL_M  (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S)
+#define GPIO_FUNC112_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC112_IN_SEL_S  0
+/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC112_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_M  (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S)
+#define GPIO_FUNC112_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC112_IN_INV_SEL_S  6
+/** GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG112_IN_SEL    (BIT(7))
+#define GPIO_SIG112_IN_SEL_M  (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S)
+#define GPIO_SIG112_IN_SEL_V  0x00000001U
+#define GPIO_SIG112_IN_SEL_S  7
+
+/** GPIO_FUNC113_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c)
+/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC113_IN_SEL    0x0000003FU
+#define GPIO_FUNC113_IN_SEL_M  (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S)
+#define GPIO_FUNC113_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC113_IN_SEL_S  0
+/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC113_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_M  (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S)
+#define GPIO_FUNC113_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC113_IN_INV_SEL_S  6
+/** GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG113_IN_SEL    (BIT(7))
+#define GPIO_SIG113_IN_SEL_M  (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S)
+#define GPIO_SIG113_IN_SEL_V  0x00000001U
+#define GPIO_SIG113_IN_SEL_S  7
+
+/** GPIO_FUNC114_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320)
+/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC114_IN_SEL    0x0000003FU
+#define GPIO_FUNC114_IN_SEL_M  (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S)
+#define GPIO_FUNC114_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC114_IN_SEL_S  0
+/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC114_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_M  (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S)
+#define GPIO_FUNC114_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC114_IN_INV_SEL_S  6
+/** GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG114_IN_SEL    (BIT(7))
+#define GPIO_SIG114_IN_SEL_M  (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S)
+#define GPIO_SIG114_IN_SEL_V  0x00000001U
+#define GPIO_SIG114_IN_SEL_S  7
+
+/** GPIO_FUNC117_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c)
+/** GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC117_IN_SEL    0x0000003FU
+#define GPIO_FUNC117_IN_SEL_M  (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S)
+#define GPIO_FUNC117_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC117_IN_SEL_S  0
+/** GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC117_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_M  (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S)
+#define GPIO_FUNC117_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC117_IN_INV_SEL_S  6
+/** GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG117_IN_SEL    (BIT(7))
+#define GPIO_SIG117_IN_SEL_M  (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S)
+#define GPIO_SIG117_IN_SEL_V  0x00000001U
+#define GPIO_SIG117_IN_SEL_S  7
+
+/** GPIO_FUNC118_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
+/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC118_IN_SEL    0x0000003FU
+#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
+#define GPIO_FUNC118_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC118_IN_SEL_S  0
+/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
+#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC118_IN_INV_SEL_S  6
+/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG118_IN_SEL    (BIT(7))
+#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
+#define GPIO_SIG118_IN_SEL_V  0x00000001U
+#define GPIO_SIG118_IN_SEL_S  7
+
+/** GPIO_FUNC126_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
+/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC126_IN_SEL    0x0000003FU
+#define GPIO_FUNC126_IN_SEL_M  (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S)
+#define GPIO_FUNC126_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC126_IN_SEL_S  0
+/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC126_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_M  (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S)
+#define GPIO_FUNC126_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC126_IN_INV_SEL_S  6
+/** GPIO_SIG126_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG126_IN_SEL    (BIT(7))
+#define GPIO_SIG126_IN_SEL_M  (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S)
+#define GPIO_SIG126_IN_SEL_V  0x00000001U
+#define GPIO_SIG126_IN_SEL_S  7
+
+/** GPIO_FUNC127_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354)
+/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC127_IN_SEL    0x0000003FU
+#define GPIO_FUNC127_IN_SEL_M  (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S)
+#define GPIO_FUNC127_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC127_IN_SEL_S  0
+/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC127_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_M  (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S)
+#define GPIO_FUNC127_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC127_IN_INV_SEL_S  6
+/** GPIO_SIG127_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG127_IN_SEL    (BIT(7))
+#define GPIO_SIG127_IN_SEL_M  (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S)
+#define GPIO_SIG127_IN_SEL_V  0x00000001U
+#define GPIO_SIG127_IN_SEL_S  7
+
+/** GPIO_FUNC128_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358)
+/** GPIO_FUNC128_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC128_IN_SEL    0x0000003FU
+#define GPIO_FUNC128_IN_SEL_M  (GPIO_FUNC128_IN_SEL_V << GPIO_FUNC128_IN_SEL_S)
+#define GPIO_FUNC128_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC128_IN_SEL_S  0
+/** GPIO_FUNC128_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC128_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_M  (GPIO_FUNC128_IN_INV_SEL_V << GPIO_FUNC128_IN_INV_SEL_S)
+#define GPIO_FUNC128_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC128_IN_INV_SEL_S  6
+/** GPIO_SIG128_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG128_IN_SEL    (BIT(7))
+#define GPIO_SIG128_IN_SEL_M  (GPIO_SIG128_IN_SEL_V << GPIO_SIG128_IN_SEL_S)
+#define GPIO_SIG128_IN_SEL_V  0x00000001U
+#define GPIO_SIG128_IN_SEL_S  7
+
+/** GPIO_FUNC129_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c)
+/** GPIO_FUNC129_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC129_IN_SEL    0x0000003FU
+#define GPIO_FUNC129_IN_SEL_M  (GPIO_FUNC129_IN_SEL_V << GPIO_FUNC129_IN_SEL_S)
+#define GPIO_FUNC129_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC129_IN_SEL_S  0
+/** GPIO_FUNC129_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC129_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_M  (GPIO_FUNC129_IN_INV_SEL_V << GPIO_FUNC129_IN_INV_SEL_S)
+#define GPIO_FUNC129_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC129_IN_INV_SEL_S  6
+/** GPIO_SIG129_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG129_IN_SEL    (BIT(7))
+#define GPIO_SIG129_IN_SEL_M  (GPIO_SIG129_IN_SEL_V << GPIO_SIG129_IN_SEL_S)
+#define GPIO_SIG129_IN_SEL_V  0x00000001U
+#define GPIO_SIG129_IN_SEL_S  7
+
+/** GPIO_FUNC130_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360)
+/** GPIO_FUNC130_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC130_IN_SEL    0x0000003FU
+#define GPIO_FUNC130_IN_SEL_M  (GPIO_FUNC130_IN_SEL_V << GPIO_FUNC130_IN_SEL_S)
+#define GPIO_FUNC130_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC130_IN_SEL_S  0
+/** GPIO_FUNC130_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC130_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_M  (GPIO_FUNC130_IN_INV_SEL_V << GPIO_FUNC130_IN_INV_SEL_S)
+#define GPIO_FUNC130_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC130_IN_INV_SEL_S  6
+/** GPIO_SIG130_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG130_IN_SEL    (BIT(7))
+#define GPIO_SIG130_IN_SEL_M  (GPIO_SIG130_IN_SEL_V << GPIO_SIG130_IN_SEL_S)
+#define GPIO_SIG130_IN_SEL_V  0x00000001U
+#define GPIO_SIG130_IN_SEL_S  7
+
+/** GPIO_FUNC131_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x364)
+/** GPIO_FUNC131_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC131_IN_SEL    0x0000003FU
+#define GPIO_FUNC131_IN_SEL_M  (GPIO_FUNC131_IN_SEL_V << GPIO_FUNC131_IN_SEL_S)
+#define GPIO_FUNC131_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC131_IN_SEL_S  0
+/** GPIO_FUNC131_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC131_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_M  (GPIO_FUNC131_IN_INV_SEL_V << GPIO_FUNC131_IN_INV_SEL_S)
+#define GPIO_FUNC131_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC131_IN_INV_SEL_S  6
+/** GPIO_SIG131_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG131_IN_SEL    (BIT(7))
+#define GPIO_SIG131_IN_SEL_M  (GPIO_SIG131_IN_SEL_V << GPIO_SIG131_IN_SEL_S)
+#define GPIO_SIG131_IN_SEL_V  0x00000001U
+#define GPIO_SIG131_IN_SEL_S  7
+
+/** GPIO_FUNC132_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368)
+/** GPIO_FUNC132_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC132_IN_SEL    0x0000003FU
+#define GPIO_FUNC132_IN_SEL_M  (GPIO_FUNC132_IN_SEL_V << GPIO_FUNC132_IN_SEL_S)
+#define GPIO_FUNC132_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC132_IN_SEL_S  0
+/** GPIO_FUNC132_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC132_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_M  (GPIO_FUNC132_IN_INV_SEL_V << GPIO_FUNC132_IN_INV_SEL_S)
+#define GPIO_FUNC132_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC132_IN_INV_SEL_S  6
+/** GPIO_SIG132_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG132_IN_SEL    (BIT(7))
+#define GPIO_SIG132_IN_SEL_M  (GPIO_SIG132_IN_SEL_V << GPIO_SIG132_IN_SEL_S)
+#define GPIO_SIG132_IN_SEL_V  0x00000001U
+#define GPIO_SIG132_IN_SEL_S  7
+
+/** GPIO_FUNC133_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c)
+/** GPIO_FUNC133_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC133_IN_SEL    0x0000003FU
+#define GPIO_FUNC133_IN_SEL_M  (GPIO_FUNC133_IN_SEL_V << GPIO_FUNC133_IN_SEL_S)
+#define GPIO_FUNC133_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC133_IN_SEL_S  0
+/** GPIO_FUNC133_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC133_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_M  (GPIO_FUNC133_IN_INV_SEL_V << GPIO_FUNC133_IN_INV_SEL_S)
+#define GPIO_FUNC133_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC133_IN_INV_SEL_S  6
+/** GPIO_SIG133_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG133_IN_SEL    (BIT(7))
+#define GPIO_SIG133_IN_SEL_M  (GPIO_SIG133_IN_SEL_V << GPIO_SIG133_IN_SEL_S)
+#define GPIO_SIG133_IN_SEL_V  0x00000001U
+#define GPIO_SIG133_IN_SEL_S  7
+
+/** GPIO_FUNC134_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370)
+/** GPIO_FUNC134_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC134_IN_SEL    0x0000003FU
+#define GPIO_FUNC134_IN_SEL_M  (GPIO_FUNC134_IN_SEL_V << GPIO_FUNC134_IN_SEL_S)
+#define GPIO_FUNC134_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC134_IN_SEL_S  0
+/** GPIO_FUNC134_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC134_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_M  (GPIO_FUNC134_IN_INV_SEL_V << GPIO_FUNC134_IN_INV_SEL_S)
+#define GPIO_FUNC134_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC134_IN_INV_SEL_S  6
+/** GPIO_SIG134_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG134_IN_SEL    (BIT(7))
+#define GPIO_SIG134_IN_SEL_M  (GPIO_SIG134_IN_SEL_V << GPIO_SIG134_IN_SEL_S)
+#define GPIO_SIG134_IN_SEL_V  0x00000001U
+#define GPIO_SIG134_IN_SEL_S  7
+
+/** GPIO_FUNC135_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x374)
+/** GPIO_FUNC135_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC135_IN_SEL    0x0000003FU
+#define GPIO_FUNC135_IN_SEL_M  (GPIO_FUNC135_IN_SEL_V << GPIO_FUNC135_IN_SEL_S)
+#define GPIO_FUNC135_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC135_IN_SEL_S  0
+/** GPIO_FUNC135_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC135_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_M  (GPIO_FUNC135_IN_INV_SEL_V << GPIO_FUNC135_IN_INV_SEL_S)
+#define GPIO_FUNC135_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC135_IN_INV_SEL_S  6
+/** GPIO_SIG135_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG135_IN_SEL    (BIT(7))
+#define GPIO_SIG135_IN_SEL_M  (GPIO_SIG135_IN_SEL_V << GPIO_SIG135_IN_SEL_S)
+#define GPIO_SIG135_IN_SEL_V  0x00000001U
+#define GPIO_SIG135_IN_SEL_S  7
+
+/** GPIO_FUNC136_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378)
+/** GPIO_FUNC136_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC136_IN_SEL    0x0000003FU
+#define GPIO_FUNC136_IN_SEL_M  (GPIO_FUNC136_IN_SEL_V << GPIO_FUNC136_IN_SEL_S)
+#define GPIO_FUNC136_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC136_IN_SEL_S  0
+/** GPIO_FUNC136_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC136_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_M  (GPIO_FUNC136_IN_INV_SEL_V << GPIO_FUNC136_IN_INV_SEL_S)
+#define GPIO_FUNC136_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC136_IN_INV_SEL_S  6
+/** GPIO_SIG136_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG136_IN_SEL    (BIT(7))
+#define GPIO_SIG136_IN_SEL_M  (GPIO_SIG136_IN_SEL_V << GPIO_SIG136_IN_SEL_S)
+#define GPIO_SIG136_IN_SEL_V  0x00000001U
+#define GPIO_SIG136_IN_SEL_S  7
+
+/** GPIO_FUNC137_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c)
+/** GPIO_FUNC137_IN_SEL : R/W; bitpos: [5:0]; default: 63;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC137_IN_SEL    0x0000003FU
+#define GPIO_FUNC137_IN_SEL_M  (GPIO_FUNC137_IN_SEL_V << GPIO_FUNC137_IN_SEL_S)
+#define GPIO_FUNC137_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC137_IN_SEL_S  0
+/** GPIO_FUNC137_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC137_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_M  (GPIO_FUNC137_IN_INV_SEL_V << GPIO_FUNC137_IN_INV_SEL_S)
+#define GPIO_FUNC137_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC137_IN_INV_SEL_S  6
+/** GPIO_SIG137_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG137_IN_SEL    (BIT(7))
+#define GPIO_SIG137_IN_SEL_M  (GPIO_SIG137_IN_SEL_V << GPIO_SIG137_IN_SEL_S)
+#define GPIO_SIG137_IN_SEL_V  0x00000001U
+#define GPIO_SIG137_IN_SEL_S  7
+
+/** GPIO_FUNC138_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380)
+/** GPIO_FUNC138_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC138_IN_SEL    0x0000003FU
+#define GPIO_FUNC138_IN_SEL_M  (GPIO_FUNC138_IN_SEL_V << GPIO_FUNC138_IN_SEL_S)
+#define GPIO_FUNC138_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC138_IN_SEL_S  0
+/** GPIO_FUNC138_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC138_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC138_IN_INV_SEL_M  (GPIO_FUNC138_IN_INV_SEL_V << GPIO_FUNC138_IN_INV_SEL_S)
+#define GPIO_FUNC138_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC138_IN_INV_SEL_S  6
+/** GPIO_SIG138_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG138_IN_SEL    (BIT(7))
+#define GPIO_SIG138_IN_SEL_M  (GPIO_SIG138_IN_SEL_V << GPIO_SIG138_IN_SEL_S)
+#define GPIO_SIG138_IN_SEL_V  0x00000001U
+#define GPIO_SIG138_IN_SEL_S  7
+
+/** GPIO_FUNC139_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x384)
+/** GPIO_FUNC139_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC139_IN_SEL    0x0000003FU
+#define GPIO_FUNC139_IN_SEL_M  (GPIO_FUNC139_IN_SEL_V << GPIO_FUNC139_IN_SEL_S)
+#define GPIO_FUNC139_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC139_IN_SEL_S  0
+/** GPIO_FUNC139_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC139_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC139_IN_INV_SEL_M  (GPIO_FUNC139_IN_INV_SEL_V << GPIO_FUNC139_IN_INV_SEL_S)
+#define GPIO_FUNC139_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC139_IN_INV_SEL_S  6
+/** GPIO_SIG139_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG139_IN_SEL    (BIT(7))
+#define GPIO_SIG139_IN_SEL_M  (GPIO_SIG139_IN_SEL_V << GPIO_SIG139_IN_SEL_S)
+#define GPIO_SIG139_IN_SEL_V  0x00000001U
+#define GPIO_SIG139_IN_SEL_S  7
+
+/** GPIO_FUNC140_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388)
+/** GPIO_FUNC140_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC140_IN_SEL    0x0000003FU
+#define GPIO_FUNC140_IN_SEL_M  (GPIO_FUNC140_IN_SEL_V << GPIO_FUNC140_IN_SEL_S)
+#define GPIO_FUNC140_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC140_IN_SEL_S  0
+/** GPIO_FUNC140_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC140_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_M  (GPIO_FUNC140_IN_INV_SEL_V << GPIO_FUNC140_IN_INV_SEL_S)
+#define GPIO_FUNC140_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC140_IN_INV_SEL_S  6
+/** GPIO_SIG140_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG140_IN_SEL    (BIT(7))
+#define GPIO_SIG140_IN_SEL_M  (GPIO_SIG140_IN_SEL_V << GPIO_SIG140_IN_SEL_S)
+#define GPIO_SIG140_IN_SEL_V  0x00000001U
+#define GPIO_SIG140_IN_SEL_S  7
+
+/** GPIO_FUNC141_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c)
+/** GPIO_FUNC141_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC141_IN_SEL    0x0000003FU
+#define GPIO_FUNC141_IN_SEL_M  (GPIO_FUNC141_IN_SEL_V << GPIO_FUNC141_IN_SEL_S)
+#define GPIO_FUNC141_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC141_IN_SEL_S  0
+/** GPIO_FUNC141_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC141_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_M  (GPIO_FUNC141_IN_INV_SEL_V << GPIO_FUNC141_IN_INV_SEL_S)
+#define GPIO_FUNC141_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC141_IN_INV_SEL_S  6
+/** GPIO_SIG141_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG141_IN_SEL    (BIT(7))
+#define GPIO_SIG141_IN_SEL_M  (GPIO_SIG141_IN_SEL_V << GPIO_SIG141_IN_SEL_S)
+#define GPIO_SIG141_IN_SEL_V  0x00000001U
+#define GPIO_SIG141_IN_SEL_S  7
+
+/** GPIO_FUNC142_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390)
+/** GPIO_FUNC142_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC142_IN_SEL    0x0000003FU
+#define GPIO_FUNC142_IN_SEL_M  (GPIO_FUNC142_IN_SEL_V << GPIO_FUNC142_IN_SEL_S)
+#define GPIO_FUNC142_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC142_IN_SEL_S  0
+/** GPIO_FUNC142_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC142_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_M  (GPIO_FUNC142_IN_INV_SEL_V << GPIO_FUNC142_IN_INV_SEL_S)
+#define GPIO_FUNC142_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC142_IN_INV_SEL_S  6
+/** GPIO_SIG142_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG142_IN_SEL    (BIT(7))
+#define GPIO_SIG142_IN_SEL_M  (GPIO_SIG142_IN_SEL_V << GPIO_SIG142_IN_SEL_S)
+#define GPIO_SIG142_IN_SEL_V  0x00000001U
+#define GPIO_SIG142_IN_SEL_S  7
+
+/** GPIO_FUNC143_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394)
+/** GPIO_FUNC143_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC143_IN_SEL    0x0000003FU
+#define GPIO_FUNC143_IN_SEL_M  (GPIO_FUNC143_IN_SEL_V << GPIO_FUNC143_IN_SEL_S)
+#define GPIO_FUNC143_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC143_IN_SEL_S  0
+/** GPIO_FUNC143_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC143_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_M  (GPIO_FUNC143_IN_INV_SEL_V << GPIO_FUNC143_IN_INV_SEL_S)
+#define GPIO_FUNC143_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC143_IN_INV_SEL_S  6
+/** GPIO_SIG143_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG143_IN_SEL    (BIT(7))
+#define GPIO_SIG143_IN_SEL_M  (GPIO_SIG143_IN_SEL_V << GPIO_SIG143_IN_SEL_S)
+#define GPIO_SIG143_IN_SEL_V  0x00000001U
+#define GPIO_SIG143_IN_SEL_S  7
+
+/** GPIO_FUNC144_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398)
+/** GPIO_FUNC144_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC144_IN_SEL    0x0000003FU
+#define GPIO_FUNC144_IN_SEL_M  (GPIO_FUNC144_IN_SEL_V << GPIO_FUNC144_IN_SEL_S)
+#define GPIO_FUNC144_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC144_IN_SEL_S  0
+/** GPIO_FUNC144_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC144_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_M  (GPIO_FUNC144_IN_INV_SEL_V << GPIO_FUNC144_IN_INV_SEL_S)
+#define GPIO_FUNC144_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC144_IN_INV_SEL_S  6
+/** GPIO_SIG144_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG144_IN_SEL    (BIT(7))
+#define GPIO_SIG144_IN_SEL_M  (GPIO_SIG144_IN_SEL_V << GPIO_SIG144_IN_SEL_S)
+#define GPIO_SIG144_IN_SEL_V  0x00000001U
+#define GPIO_SIG144_IN_SEL_S  7
+
+/** GPIO_FUNC145_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39c)
+/** GPIO_FUNC145_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC145_IN_SEL    0x0000003FU
+#define GPIO_FUNC145_IN_SEL_M  (GPIO_FUNC145_IN_SEL_V << GPIO_FUNC145_IN_SEL_S)
+#define GPIO_FUNC145_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC145_IN_SEL_S  0
+/** GPIO_FUNC145_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC145_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_M  (GPIO_FUNC145_IN_INV_SEL_V << GPIO_FUNC145_IN_INV_SEL_S)
+#define GPIO_FUNC145_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC145_IN_INV_SEL_S  6
+/** GPIO_SIG145_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG145_IN_SEL    (BIT(7))
+#define GPIO_SIG145_IN_SEL_M  (GPIO_SIG145_IN_SEL_V << GPIO_SIG145_IN_SEL_S)
+#define GPIO_SIG145_IN_SEL_V  0x00000001U
+#define GPIO_SIG145_IN_SEL_S  7
+
+/** GPIO_FUNC146_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0)
+/** GPIO_FUNC146_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC146_IN_SEL    0x0000003FU
+#define GPIO_FUNC146_IN_SEL_M  (GPIO_FUNC146_IN_SEL_V << GPIO_FUNC146_IN_SEL_S)
+#define GPIO_FUNC146_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC146_IN_SEL_S  0
+/** GPIO_FUNC146_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC146_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_M  (GPIO_FUNC146_IN_INV_SEL_V << GPIO_FUNC146_IN_INV_SEL_S)
+#define GPIO_FUNC146_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC146_IN_INV_SEL_S  6
+/** GPIO_SIG146_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG146_IN_SEL    (BIT(7))
+#define GPIO_SIG146_IN_SEL_M  (GPIO_SIG146_IN_SEL_V << GPIO_SIG146_IN_SEL_S)
+#define GPIO_SIG146_IN_SEL_V  0x00000001U
+#define GPIO_SIG146_IN_SEL_S  7
+
+/** GPIO_FUNC147_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4)
+/** GPIO_FUNC147_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC147_IN_SEL    0x0000003FU
+#define GPIO_FUNC147_IN_SEL_M  (GPIO_FUNC147_IN_SEL_V << GPIO_FUNC147_IN_SEL_S)
+#define GPIO_FUNC147_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC147_IN_SEL_S  0
+/** GPIO_FUNC147_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC147_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_M  (GPIO_FUNC147_IN_INV_SEL_V << GPIO_FUNC147_IN_INV_SEL_S)
+#define GPIO_FUNC147_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC147_IN_INV_SEL_S  6
+/** GPIO_SIG147_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG147_IN_SEL    (BIT(7))
+#define GPIO_SIG147_IN_SEL_M  (GPIO_SIG147_IN_SEL_V << GPIO_SIG147_IN_SEL_S)
+#define GPIO_SIG147_IN_SEL_V  0x00000001U
+#define GPIO_SIG147_IN_SEL_S  7
+
+/** GPIO_FUNC148_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8)
+/** GPIO_FUNC148_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC148_IN_SEL    0x0000003FU
+#define GPIO_FUNC148_IN_SEL_M  (GPIO_FUNC148_IN_SEL_V << GPIO_FUNC148_IN_SEL_S)
+#define GPIO_FUNC148_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC148_IN_SEL_S  0
+/** GPIO_FUNC148_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC148_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_M  (GPIO_FUNC148_IN_INV_SEL_V << GPIO_FUNC148_IN_INV_SEL_S)
+#define GPIO_FUNC148_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC148_IN_INV_SEL_S  6
+/** GPIO_SIG148_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG148_IN_SEL    (BIT(7))
+#define GPIO_SIG148_IN_SEL_M  (GPIO_SIG148_IN_SEL_V << GPIO_SIG148_IN_SEL_S)
+#define GPIO_SIG148_IN_SEL_V  0x00000001U
+#define GPIO_SIG148_IN_SEL_S  7
+
+/** GPIO_FUNC149_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ac)
+/** GPIO_FUNC149_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC149_IN_SEL    0x0000003FU
+#define GPIO_FUNC149_IN_SEL_M  (GPIO_FUNC149_IN_SEL_V << GPIO_FUNC149_IN_SEL_S)
+#define GPIO_FUNC149_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC149_IN_SEL_S  0
+/** GPIO_FUNC149_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC149_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_M  (GPIO_FUNC149_IN_INV_SEL_V << GPIO_FUNC149_IN_INV_SEL_S)
+#define GPIO_FUNC149_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC149_IN_INV_SEL_S  6
+/** GPIO_SIG149_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG149_IN_SEL    (BIT(7))
+#define GPIO_SIG149_IN_SEL_M  (GPIO_SIG149_IN_SEL_V << GPIO_SIG149_IN_SEL_S)
+#define GPIO_SIG149_IN_SEL_V  0x00000001U
+#define GPIO_SIG149_IN_SEL_S  7
+
+/** GPIO_FUNC150_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0)
+/** GPIO_FUNC150_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC150_IN_SEL    0x0000003FU
+#define GPIO_FUNC150_IN_SEL_M  (GPIO_FUNC150_IN_SEL_V << GPIO_FUNC150_IN_SEL_S)
+#define GPIO_FUNC150_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC150_IN_SEL_S  0
+/** GPIO_FUNC150_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC150_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_M  (GPIO_FUNC150_IN_INV_SEL_V << GPIO_FUNC150_IN_INV_SEL_S)
+#define GPIO_FUNC150_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC150_IN_INV_SEL_S  6
+/** GPIO_SIG150_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG150_IN_SEL    (BIT(7))
+#define GPIO_SIG150_IN_SEL_M  (GPIO_SIG150_IN_SEL_V << GPIO_SIG150_IN_SEL_S)
+#define GPIO_SIG150_IN_SEL_V  0x00000001U
+#define GPIO_SIG150_IN_SEL_S  7
+
+/** GPIO_FUNC151_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4)
+/** GPIO_FUNC151_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC151_IN_SEL    0x0000003FU
+#define GPIO_FUNC151_IN_SEL_M  (GPIO_FUNC151_IN_SEL_V << GPIO_FUNC151_IN_SEL_S)
+#define GPIO_FUNC151_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC151_IN_SEL_S  0
+/** GPIO_FUNC151_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC151_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_M  (GPIO_FUNC151_IN_INV_SEL_V << GPIO_FUNC151_IN_INV_SEL_S)
+#define GPIO_FUNC151_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC151_IN_INV_SEL_S  6
+/** GPIO_SIG151_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG151_IN_SEL    (BIT(7))
+#define GPIO_SIG151_IN_SEL_M  (GPIO_SIG151_IN_SEL_V << GPIO_SIG151_IN_SEL_S)
+#define GPIO_SIG151_IN_SEL_V  0x00000001U
+#define GPIO_SIG151_IN_SEL_S  7
+
+/** GPIO_FUNC152_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8)
+/** GPIO_FUNC152_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC152_IN_SEL    0x0000003FU
+#define GPIO_FUNC152_IN_SEL_M  (GPIO_FUNC152_IN_SEL_V << GPIO_FUNC152_IN_SEL_S)
+#define GPIO_FUNC152_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC152_IN_SEL_S  0
+/** GPIO_FUNC152_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC152_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_M  (GPIO_FUNC152_IN_INV_SEL_V << GPIO_FUNC152_IN_INV_SEL_S)
+#define GPIO_FUNC152_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC152_IN_INV_SEL_S  6
+/** GPIO_SIG152_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG152_IN_SEL    (BIT(7))
+#define GPIO_SIG152_IN_SEL_M  (GPIO_SIG152_IN_SEL_V << GPIO_SIG152_IN_SEL_S)
+#define GPIO_SIG152_IN_SEL_V  0x00000001U
+#define GPIO_SIG152_IN_SEL_S  7
+
+/** GPIO_FUNC153_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc)
+/** GPIO_FUNC153_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC153_IN_SEL    0x0000003FU
+#define GPIO_FUNC153_IN_SEL_M  (GPIO_FUNC153_IN_SEL_V << GPIO_FUNC153_IN_SEL_S)
+#define GPIO_FUNC153_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC153_IN_SEL_S  0
+/** GPIO_FUNC153_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC153_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_M  (GPIO_FUNC153_IN_INV_SEL_V << GPIO_FUNC153_IN_INV_SEL_S)
+#define GPIO_FUNC153_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC153_IN_INV_SEL_S  6
+/** GPIO_SIG153_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG153_IN_SEL    (BIT(7))
+#define GPIO_SIG153_IN_SEL_M  (GPIO_SIG153_IN_SEL_V << GPIO_SIG153_IN_SEL_S)
+#define GPIO_SIG153_IN_SEL_V  0x00000001U
+#define GPIO_SIG153_IN_SEL_S  7
+
+/** GPIO_FUNC154_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0)
+/** GPIO_FUNC154_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC154_IN_SEL    0x0000003FU
+#define GPIO_FUNC154_IN_SEL_M  (GPIO_FUNC154_IN_SEL_V << GPIO_FUNC154_IN_SEL_S)
+#define GPIO_FUNC154_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC154_IN_SEL_S  0
+/** GPIO_FUNC154_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC154_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_M  (GPIO_FUNC154_IN_INV_SEL_V << GPIO_FUNC154_IN_INV_SEL_S)
+#define GPIO_FUNC154_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC154_IN_INV_SEL_S  6
+/** GPIO_SIG154_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG154_IN_SEL    (BIT(7))
+#define GPIO_SIG154_IN_SEL_M  (GPIO_SIG154_IN_SEL_V << GPIO_SIG154_IN_SEL_S)
+#define GPIO_SIG154_IN_SEL_V  0x00000001U
+#define GPIO_SIG154_IN_SEL_S  7
+
+/** GPIO_FUNC155_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4)
+/** GPIO_FUNC155_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC155_IN_SEL    0x0000003FU
+#define GPIO_FUNC155_IN_SEL_M  (GPIO_FUNC155_IN_SEL_V << GPIO_FUNC155_IN_SEL_S)
+#define GPIO_FUNC155_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC155_IN_SEL_S  0
+/** GPIO_FUNC155_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC155_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_M  (GPIO_FUNC155_IN_INV_SEL_V << GPIO_FUNC155_IN_INV_SEL_S)
+#define GPIO_FUNC155_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC155_IN_INV_SEL_S  6
+/** GPIO_SIG155_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG155_IN_SEL    (BIT(7))
+#define GPIO_SIG155_IN_SEL_M  (GPIO_SIG155_IN_SEL_V << GPIO_SIG155_IN_SEL_S)
+#define GPIO_SIG155_IN_SEL_V  0x00000001U
+#define GPIO_SIG155_IN_SEL_S  7
+
+/** GPIO_FUNC156_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8)
+/** GPIO_FUNC156_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC156_IN_SEL    0x0000003FU
+#define GPIO_FUNC156_IN_SEL_M  (GPIO_FUNC156_IN_SEL_V << GPIO_FUNC156_IN_SEL_S)
+#define GPIO_FUNC156_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC156_IN_SEL_S  0
+/** GPIO_FUNC156_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC156_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_M  (GPIO_FUNC156_IN_INV_SEL_V << GPIO_FUNC156_IN_INV_SEL_S)
+#define GPIO_FUNC156_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC156_IN_INV_SEL_S  6
+/** GPIO_SIG156_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG156_IN_SEL    (BIT(7))
+#define GPIO_SIG156_IN_SEL_M  (GPIO_SIG156_IN_SEL_V << GPIO_SIG156_IN_SEL_S)
+#define GPIO_SIG156_IN_SEL_V  0x00000001U
+#define GPIO_SIG156_IN_SEL_S  7
+
+/** GPIO_FUNC158_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0)
+/** GPIO_FUNC158_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC158_IN_SEL    0x0000003FU
+#define GPIO_FUNC158_IN_SEL_M  (GPIO_FUNC158_IN_SEL_V << GPIO_FUNC158_IN_SEL_S)
+#define GPIO_FUNC158_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC158_IN_SEL_S  0
+/** GPIO_FUNC158_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC158_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_M  (GPIO_FUNC158_IN_INV_SEL_V << GPIO_FUNC158_IN_INV_SEL_S)
+#define GPIO_FUNC158_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC158_IN_INV_SEL_S  6
+/** GPIO_SIG158_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG158_IN_SEL    (BIT(7))
+#define GPIO_SIG158_IN_SEL_M  (GPIO_SIG158_IN_SEL_V << GPIO_SIG158_IN_SEL_S)
+#define GPIO_SIG158_IN_SEL_V  0x00000001U
+#define GPIO_SIG158_IN_SEL_S  7
+
+/** GPIO_FUNC159_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4)
+/** GPIO_FUNC159_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC159_IN_SEL    0x0000003FU
+#define GPIO_FUNC159_IN_SEL_M  (GPIO_FUNC159_IN_SEL_V << GPIO_FUNC159_IN_SEL_S)
+#define GPIO_FUNC159_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC159_IN_SEL_S  0
+/** GPIO_FUNC159_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC159_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_M  (GPIO_FUNC159_IN_INV_SEL_V << GPIO_FUNC159_IN_INV_SEL_S)
+#define GPIO_FUNC159_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC159_IN_INV_SEL_S  6
+/** GPIO_SIG159_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG159_IN_SEL    (BIT(7))
+#define GPIO_SIG159_IN_SEL_M  (GPIO_SIG159_IN_SEL_V << GPIO_SIG159_IN_SEL_S)
+#define GPIO_SIG159_IN_SEL_V  0x00000001U
+#define GPIO_SIG159_IN_SEL_S  7
+
+/** GPIO_FUNC160_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8)
+/** GPIO_FUNC160_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC160_IN_SEL    0x0000003FU
+#define GPIO_FUNC160_IN_SEL_M  (GPIO_FUNC160_IN_SEL_V << GPIO_FUNC160_IN_SEL_S)
+#define GPIO_FUNC160_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC160_IN_SEL_S  0
+/** GPIO_FUNC160_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC160_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_M  (GPIO_FUNC160_IN_INV_SEL_V << GPIO_FUNC160_IN_INV_SEL_S)
+#define GPIO_FUNC160_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC160_IN_INV_SEL_S  6
+/** GPIO_SIG160_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG160_IN_SEL    (BIT(7))
+#define GPIO_SIG160_IN_SEL_M  (GPIO_SIG160_IN_SEL_V << GPIO_SIG160_IN_SEL_S)
+#define GPIO_SIG160_IN_SEL_V  0x00000001U
+#define GPIO_SIG160_IN_SEL_S  7
+
+/** GPIO_FUNC161_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc)
+/** GPIO_FUNC161_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC161_IN_SEL    0x0000003FU
+#define GPIO_FUNC161_IN_SEL_M  (GPIO_FUNC161_IN_SEL_V << GPIO_FUNC161_IN_SEL_S)
+#define GPIO_FUNC161_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC161_IN_SEL_S  0
+/** GPIO_FUNC161_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC161_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_M  (GPIO_FUNC161_IN_INV_SEL_V << GPIO_FUNC161_IN_INV_SEL_S)
+#define GPIO_FUNC161_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC161_IN_INV_SEL_S  6
+/** GPIO_SIG161_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG161_IN_SEL    (BIT(7))
+#define GPIO_SIG161_IN_SEL_M  (GPIO_SIG161_IN_SEL_V << GPIO_SIG161_IN_SEL_S)
+#define GPIO_SIG161_IN_SEL_V  0x00000001U
+#define GPIO_SIG161_IN_SEL_S  7
+
+/** GPIO_FUNC162_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0)
+/** GPIO_FUNC162_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC162_IN_SEL    0x0000003FU
+#define GPIO_FUNC162_IN_SEL_M  (GPIO_FUNC162_IN_SEL_V << GPIO_FUNC162_IN_SEL_S)
+#define GPIO_FUNC162_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC162_IN_SEL_S  0
+/** GPIO_FUNC162_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC162_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_M  (GPIO_FUNC162_IN_INV_SEL_V << GPIO_FUNC162_IN_INV_SEL_S)
+#define GPIO_FUNC162_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC162_IN_INV_SEL_S  6
+/** GPIO_SIG162_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG162_IN_SEL    (BIT(7))
+#define GPIO_SIG162_IN_SEL_M  (GPIO_SIG162_IN_SEL_V << GPIO_SIG162_IN_SEL_S)
+#define GPIO_SIG162_IN_SEL_V  0x00000001U
+#define GPIO_SIG162_IN_SEL_S  7
+
+/** GPIO_FUNC163_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4)
+/** GPIO_FUNC163_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC163_IN_SEL    0x0000003FU
+#define GPIO_FUNC163_IN_SEL_M  (GPIO_FUNC163_IN_SEL_V << GPIO_FUNC163_IN_SEL_S)
+#define GPIO_FUNC163_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC163_IN_SEL_S  0
+/** GPIO_FUNC163_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC163_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_M  (GPIO_FUNC163_IN_INV_SEL_V << GPIO_FUNC163_IN_INV_SEL_S)
+#define GPIO_FUNC163_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC163_IN_INV_SEL_S  6
+/** GPIO_SIG163_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG163_IN_SEL    (BIT(7))
+#define GPIO_SIG163_IN_SEL_M  (GPIO_SIG163_IN_SEL_V << GPIO_SIG163_IN_SEL_S)
+#define GPIO_SIG163_IN_SEL_V  0x00000001U
+#define GPIO_SIG163_IN_SEL_S  7
+
+/** GPIO_FUNC164_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8)
+/** GPIO_FUNC164_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC164_IN_SEL    0x0000003FU
+#define GPIO_FUNC164_IN_SEL_M  (GPIO_FUNC164_IN_SEL_V << GPIO_FUNC164_IN_SEL_S)
+#define GPIO_FUNC164_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC164_IN_SEL_S  0
+/** GPIO_FUNC164_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC164_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_M  (GPIO_FUNC164_IN_INV_SEL_V << GPIO_FUNC164_IN_INV_SEL_S)
+#define GPIO_FUNC164_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC164_IN_INV_SEL_S  6
+/** GPIO_SIG164_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG164_IN_SEL    (BIT(7))
+#define GPIO_SIG164_IN_SEL_M  (GPIO_SIG164_IN_SEL_V << GPIO_SIG164_IN_SEL_S)
+#define GPIO_SIG164_IN_SEL_V  0x00000001U
+#define GPIO_SIG164_IN_SEL_S  7
+
+/** GPIO_FUNC165_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec)
+/** GPIO_FUNC165_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC165_IN_SEL    0x0000003FU
+#define GPIO_FUNC165_IN_SEL_M  (GPIO_FUNC165_IN_SEL_V << GPIO_FUNC165_IN_SEL_S)
+#define GPIO_FUNC165_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC165_IN_SEL_S  0
+/** GPIO_FUNC165_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC165_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_M  (GPIO_FUNC165_IN_INV_SEL_V << GPIO_FUNC165_IN_INV_SEL_S)
+#define GPIO_FUNC165_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC165_IN_INV_SEL_S  6
+/** GPIO_SIG165_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG165_IN_SEL    (BIT(7))
+#define GPIO_SIG165_IN_SEL_M  (GPIO_SIG165_IN_SEL_V << GPIO_SIG165_IN_SEL_S)
+#define GPIO_SIG165_IN_SEL_V  0x00000001U
+#define GPIO_SIG165_IN_SEL_S  7
+
+/** GPIO_FUNC166_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f0)
+/** GPIO_FUNC166_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC166_IN_SEL    0x0000003FU
+#define GPIO_FUNC166_IN_SEL_M  (GPIO_FUNC166_IN_SEL_V << GPIO_FUNC166_IN_SEL_S)
+#define GPIO_FUNC166_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC166_IN_SEL_S  0
+/** GPIO_FUNC166_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC166_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_M  (GPIO_FUNC166_IN_INV_SEL_V << GPIO_FUNC166_IN_INV_SEL_S)
+#define GPIO_FUNC166_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC166_IN_INV_SEL_S  6
+/** GPIO_SIG166_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG166_IN_SEL    (BIT(7))
+#define GPIO_SIG166_IN_SEL_M  (GPIO_SIG166_IN_SEL_V << GPIO_SIG166_IN_SEL_S)
+#define GPIO_SIG166_IN_SEL_V  0x00000001U
+#define GPIO_SIG166_IN_SEL_S  7
+
+/** GPIO_FUNC167_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4)
+/** GPIO_FUNC167_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC167_IN_SEL    0x0000003FU
+#define GPIO_FUNC167_IN_SEL_M  (GPIO_FUNC167_IN_SEL_V << GPIO_FUNC167_IN_SEL_S)
+#define GPIO_FUNC167_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC167_IN_SEL_S  0
+/** GPIO_FUNC167_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC167_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_M  (GPIO_FUNC167_IN_INV_SEL_V << GPIO_FUNC167_IN_INV_SEL_S)
+#define GPIO_FUNC167_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC167_IN_INV_SEL_S  6
+/** GPIO_SIG167_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG167_IN_SEL    (BIT(7))
+#define GPIO_SIG167_IN_SEL_M  (GPIO_SIG167_IN_SEL_V << GPIO_SIG167_IN_SEL_S)
+#define GPIO_SIG167_IN_SEL_V  0x00000001U
+#define GPIO_SIG167_IN_SEL_S  7
+
+/** GPIO_FUNC168_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8)
+/** GPIO_FUNC168_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC168_IN_SEL    0x0000003FU
+#define GPIO_FUNC168_IN_SEL_M  (GPIO_FUNC168_IN_SEL_V << GPIO_FUNC168_IN_SEL_S)
+#define GPIO_FUNC168_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC168_IN_SEL_S  0
+/** GPIO_FUNC168_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC168_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_M  (GPIO_FUNC168_IN_INV_SEL_V << GPIO_FUNC168_IN_INV_SEL_S)
+#define GPIO_FUNC168_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC168_IN_INV_SEL_S  6
+/** GPIO_SIG168_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG168_IN_SEL    (BIT(7))
+#define GPIO_SIG168_IN_SEL_M  (GPIO_SIG168_IN_SEL_V << GPIO_SIG168_IN_SEL_S)
+#define GPIO_SIG168_IN_SEL_V  0x00000001U
+#define GPIO_SIG168_IN_SEL_S  7
+
+/** GPIO_FUNC169_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc)
+/** GPIO_FUNC169_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC169_IN_SEL    0x0000003FU
+#define GPIO_FUNC169_IN_SEL_M  (GPIO_FUNC169_IN_SEL_V << GPIO_FUNC169_IN_SEL_S)
+#define GPIO_FUNC169_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC169_IN_SEL_S  0
+/** GPIO_FUNC169_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC169_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_M  (GPIO_FUNC169_IN_INV_SEL_V << GPIO_FUNC169_IN_INV_SEL_S)
+#define GPIO_FUNC169_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC169_IN_INV_SEL_S  6
+/** GPIO_SIG169_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG169_IN_SEL    (BIT(7))
+#define GPIO_SIG169_IN_SEL_M  (GPIO_SIG169_IN_SEL_V << GPIO_SIG169_IN_SEL_S)
+#define GPIO_SIG169_IN_SEL_V  0x00000001U
+#define GPIO_SIG169_IN_SEL_S  7
+
+/** GPIO_FUNC170_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400)
+/** GPIO_FUNC170_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC170_IN_SEL    0x0000003FU
+#define GPIO_FUNC170_IN_SEL_M  (GPIO_FUNC170_IN_SEL_V << GPIO_FUNC170_IN_SEL_S)
+#define GPIO_FUNC170_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC170_IN_SEL_S  0
+/** GPIO_FUNC170_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC170_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_M  (GPIO_FUNC170_IN_INV_SEL_V << GPIO_FUNC170_IN_INV_SEL_S)
+#define GPIO_FUNC170_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC170_IN_INV_SEL_S  6
+/** GPIO_SIG170_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG170_IN_SEL    (BIT(7))
+#define GPIO_SIG170_IN_SEL_M  (GPIO_SIG170_IN_SEL_V << GPIO_SIG170_IN_SEL_S)
+#define GPIO_SIG170_IN_SEL_V  0x00000001U
+#define GPIO_SIG170_IN_SEL_S  7
+
+/** GPIO_FUNC171_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404)
+/** GPIO_FUNC171_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC171_IN_SEL    0x0000003FU
+#define GPIO_FUNC171_IN_SEL_M  (GPIO_FUNC171_IN_SEL_V << GPIO_FUNC171_IN_SEL_S)
+#define GPIO_FUNC171_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC171_IN_SEL_S  0
+/** GPIO_FUNC171_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC171_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_M  (GPIO_FUNC171_IN_INV_SEL_V << GPIO_FUNC171_IN_INV_SEL_S)
+#define GPIO_FUNC171_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC171_IN_INV_SEL_S  6
+/** GPIO_SIG171_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG171_IN_SEL    (BIT(7))
+#define GPIO_SIG171_IN_SEL_M  (GPIO_SIG171_IN_SEL_V << GPIO_SIG171_IN_SEL_S)
+#define GPIO_SIG171_IN_SEL_V  0x00000001U
+#define GPIO_SIG171_IN_SEL_S  7
+
+/** GPIO_FUNC172_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408)
+/** GPIO_FUNC172_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC172_IN_SEL    0x0000003FU
+#define GPIO_FUNC172_IN_SEL_M  (GPIO_FUNC172_IN_SEL_V << GPIO_FUNC172_IN_SEL_S)
+#define GPIO_FUNC172_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC172_IN_SEL_S  0
+/** GPIO_FUNC172_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC172_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_M  (GPIO_FUNC172_IN_INV_SEL_V << GPIO_FUNC172_IN_INV_SEL_S)
+#define GPIO_FUNC172_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC172_IN_INV_SEL_S  6
+/** GPIO_SIG172_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG172_IN_SEL    (BIT(7))
+#define GPIO_SIG172_IN_SEL_M  (GPIO_SIG172_IN_SEL_V << GPIO_SIG172_IN_SEL_S)
+#define GPIO_SIG172_IN_SEL_V  0x00000001U
+#define GPIO_SIG172_IN_SEL_S  7
+
+/** GPIO_FUNC173_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c)
+/** GPIO_FUNC173_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC173_IN_SEL    0x0000003FU
+#define GPIO_FUNC173_IN_SEL_M  (GPIO_FUNC173_IN_SEL_V << GPIO_FUNC173_IN_SEL_S)
+#define GPIO_FUNC173_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC173_IN_SEL_S  0
+/** GPIO_FUNC173_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC173_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_M  (GPIO_FUNC173_IN_INV_SEL_V << GPIO_FUNC173_IN_INV_SEL_S)
+#define GPIO_FUNC173_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC173_IN_INV_SEL_S  6
+/** GPIO_SIG173_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG173_IN_SEL    (BIT(7))
+#define GPIO_SIG173_IN_SEL_M  (GPIO_SIG173_IN_SEL_V << GPIO_SIG173_IN_SEL_S)
+#define GPIO_SIG173_IN_SEL_V  0x00000001U
+#define GPIO_SIG173_IN_SEL_S  7
+
+/** GPIO_FUNC174_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410)
+/** GPIO_FUNC174_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC174_IN_SEL    0x0000003FU
+#define GPIO_FUNC174_IN_SEL_M  (GPIO_FUNC174_IN_SEL_V << GPIO_FUNC174_IN_SEL_S)
+#define GPIO_FUNC174_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC174_IN_SEL_S  0
+/** GPIO_FUNC174_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC174_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_M  (GPIO_FUNC174_IN_INV_SEL_V << GPIO_FUNC174_IN_INV_SEL_S)
+#define GPIO_FUNC174_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC174_IN_INV_SEL_S  6
+/** GPIO_SIG174_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG174_IN_SEL    (BIT(7))
+#define GPIO_SIG174_IN_SEL_M  (GPIO_SIG174_IN_SEL_V << GPIO_SIG174_IN_SEL_S)
+#define GPIO_SIG174_IN_SEL_V  0x00000001U
+#define GPIO_SIG174_IN_SEL_S  7
+
+/** GPIO_FUNC175_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414)
+/** GPIO_FUNC175_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC175_IN_SEL    0x0000003FU
+#define GPIO_FUNC175_IN_SEL_M  (GPIO_FUNC175_IN_SEL_V << GPIO_FUNC175_IN_SEL_S)
+#define GPIO_FUNC175_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC175_IN_SEL_S  0
+/** GPIO_FUNC175_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC175_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_M  (GPIO_FUNC175_IN_INV_SEL_V << GPIO_FUNC175_IN_INV_SEL_S)
+#define GPIO_FUNC175_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC175_IN_INV_SEL_S  6
+/** GPIO_SIG175_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG175_IN_SEL    (BIT(7))
+#define GPIO_SIG175_IN_SEL_M  (GPIO_SIG175_IN_SEL_V << GPIO_SIG175_IN_SEL_S)
+#define GPIO_SIG175_IN_SEL_V  0x00000001U
+#define GPIO_SIG175_IN_SEL_S  7
+
+/** GPIO_FUNC176_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418)
+/** GPIO_FUNC176_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC176_IN_SEL    0x0000003FU
+#define GPIO_FUNC176_IN_SEL_M  (GPIO_FUNC176_IN_SEL_V << GPIO_FUNC176_IN_SEL_S)
+#define GPIO_FUNC176_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC176_IN_SEL_S  0
+/** GPIO_FUNC176_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC176_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_M  (GPIO_FUNC176_IN_INV_SEL_V << GPIO_FUNC176_IN_INV_SEL_S)
+#define GPIO_FUNC176_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC176_IN_INV_SEL_S  6
+/** GPIO_SIG176_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG176_IN_SEL    (BIT(7))
+#define GPIO_SIG176_IN_SEL_M  (GPIO_SIG176_IN_SEL_V << GPIO_SIG176_IN_SEL_S)
+#define GPIO_SIG176_IN_SEL_V  0x00000001U
+#define GPIO_SIG176_IN_SEL_S  7
+
+/** GPIO_FUNC177_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c)
+/** GPIO_FUNC177_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC177_IN_SEL    0x0000003FU
+#define GPIO_FUNC177_IN_SEL_M  (GPIO_FUNC177_IN_SEL_V << GPIO_FUNC177_IN_SEL_S)
+#define GPIO_FUNC177_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC177_IN_SEL_S  0
+/** GPIO_FUNC177_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC177_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_M  (GPIO_FUNC177_IN_INV_SEL_V << GPIO_FUNC177_IN_INV_SEL_S)
+#define GPIO_FUNC177_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC177_IN_INV_SEL_S  6
+/** GPIO_SIG177_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG177_IN_SEL    (BIT(7))
+#define GPIO_SIG177_IN_SEL_M  (GPIO_SIG177_IN_SEL_V << GPIO_SIG177_IN_SEL_S)
+#define GPIO_SIG177_IN_SEL_V  0x00000001U
+#define GPIO_SIG177_IN_SEL_S  7
+
+/** GPIO_FUNC178_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420)
+/** GPIO_FUNC178_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC178_IN_SEL    0x0000003FU
+#define GPIO_FUNC178_IN_SEL_M  (GPIO_FUNC178_IN_SEL_V << GPIO_FUNC178_IN_SEL_S)
+#define GPIO_FUNC178_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC178_IN_SEL_S  0
+/** GPIO_FUNC178_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC178_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_M  (GPIO_FUNC178_IN_INV_SEL_V << GPIO_FUNC178_IN_INV_SEL_S)
+#define GPIO_FUNC178_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC178_IN_INV_SEL_S  6
+/** GPIO_SIG178_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG178_IN_SEL    (BIT(7))
+#define GPIO_SIG178_IN_SEL_M  (GPIO_SIG178_IN_SEL_V << GPIO_SIG178_IN_SEL_S)
+#define GPIO_SIG178_IN_SEL_V  0x00000001U
+#define GPIO_SIG178_IN_SEL_S  7
+
+/** GPIO_FUNC179_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424)
+/** GPIO_FUNC179_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC179_IN_SEL    0x0000003FU
+#define GPIO_FUNC179_IN_SEL_M  (GPIO_FUNC179_IN_SEL_V << GPIO_FUNC179_IN_SEL_S)
+#define GPIO_FUNC179_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC179_IN_SEL_S  0
+/** GPIO_FUNC179_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC179_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_M  (GPIO_FUNC179_IN_INV_SEL_V << GPIO_FUNC179_IN_INV_SEL_S)
+#define GPIO_FUNC179_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC179_IN_INV_SEL_S  6
+/** GPIO_SIG179_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG179_IN_SEL    (BIT(7))
+#define GPIO_SIG179_IN_SEL_M  (GPIO_SIG179_IN_SEL_V << GPIO_SIG179_IN_SEL_S)
+#define GPIO_SIG179_IN_SEL_V  0x00000001U
+#define GPIO_SIG179_IN_SEL_S  7
+
+/** GPIO_FUNC180_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428)
+/** GPIO_FUNC180_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC180_IN_SEL    0x0000003FU
+#define GPIO_FUNC180_IN_SEL_M  (GPIO_FUNC180_IN_SEL_V << GPIO_FUNC180_IN_SEL_S)
+#define GPIO_FUNC180_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC180_IN_SEL_S  0
+/** GPIO_FUNC180_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC180_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_M  (GPIO_FUNC180_IN_INV_SEL_V << GPIO_FUNC180_IN_INV_SEL_S)
+#define GPIO_FUNC180_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC180_IN_INV_SEL_S  6
+/** GPIO_SIG180_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG180_IN_SEL    (BIT(7))
+#define GPIO_SIG180_IN_SEL_M  (GPIO_SIG180_IN_SEL_V << GPIO_SIG180_IN_SEL_S)
+#define GPIO_SIG180_IN_SEL_V  0x00000001U
+#define GPIO_SIG180_IN_SEL_S  7
+
+/** GPIO_FUNC181_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c)
+/** GPIO_FUNC181_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC181_IN_SEL    0x0000003FU
+#define GPIO_FUNC181_IN_SEL_M  (GPIO_FUNC181_IN_SEL_V << GPIO_FUNC181_IN_SEL_S)
+#define GPIO_FUNC181_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC181_IN_SEL_S  0
+/** GPIO_FUNC181_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC181_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_M  (GPIO_FUNC181_IN_INV_SEL_V << GPIO_FUNC181_IN_INV_SEL_S)
+#define GPIO_FUNC181_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC181_IN_INV_SEL_S  6
+/** GPIO_SIG181_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG181_IN_SEL    (BIT(7))
+#define GPIO_SIG181_IN_SEL_M  (GPIO_SIG181_IN_SEL_V << GPIO_SIG181_IN_SEL_S)
+#define GPIO_SIG181_IN_SEL_V  0x00000001U
+#define GPIO_SIG181_IN_SEL_S  7
+
+/** GPIO_FUNC182_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430)
+/** GPIO_FUNC182_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC182_IN_SEL    0x0000003FU
+#define GPIO_FUNC182_IN_SEL_M  (GPIO_FUNC182_IN_SEL_V << GPIO_FUNC182_IN_SEL_S)
+#define GPIO_FUNC182_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC182_IN_SEL_S  0
+/** GPIO_FUNC182_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC182_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_M  (GPIO_FUNC182_IN_INV_SEL_V << GPIO_FUNC182_IN_INV_SEL_S)
+#define GPIO_FUNC182_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC182_IN_INV_SEL_S  6
+/** GPIO_SIG182_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG182_IN_SEL    (BIT(7))
+#define GPIO_SIG182_IN_SEL_M  (GPIO_SIG182_IN_SEL_V << GPIO_SIG182_IN_SEL_S)
+#define GPIO_SIG182_IN_SEL_V  0x00000001U
+#define GPIO_SIG182_IN_SEL_S  7
+
+/** GPIO_FUNC183_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434)
+/** GPIO_FUNC183_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC183_IN_SEL    0x0000003FU
+#define GPIO_FUNC183_IN_SEL_M  (GPIO_FUNC183_IN_SEL_V << GPIO_FUNC183_IN_SEL_S)
+#define GPIO_FUNC183_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC183_IN_SEL_S  0
+/** GPIO_FUNC183_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC183_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_M  (GPIO_FUNC183_IN_INV_SEL_V << GPIO_FUNC183_IN_INV_SEL_S)
+#define GPIO_FUNC183_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC183_IN_INV_SEL_S  6
+/** GPIO_SIG183_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG183_IN_SEL    (BIT(7))
+#define GPIO_SIG183_IN_SEL_M  (GPIO_SIG183_IN_SEL_V << GPIO_SIG183_IN_SEL_S)
+#define GPIO_SIG183_IN_SEL_V  0x00000001U
+#define GPIO_SIG183_IN_SEL_S  7
+
+/** GPIO_FUNC184_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438)
+/** GPIO_FUNC184_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC184_IN_SEL    0x0000003FU
+#define GPIO_FUNC184_IN_SEL_M  (GPIO_FUNC184_IN_SEL_V << GPIO_FUNC184_IN_SEL_S)
+#define GPIO_FUNC184_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC184_IN_SEL_S  0
+/** GPIO_FUNC184_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC184_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_M  (GPIO_FUNC184_IN_INV_SEL_V << GPIO_FUNC184_IN_INV_SEL_S)
+#define GPIO_FUNC184_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC184_IN_INV_SEL_S  6
+/** GPIO_SIG184_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG184_IN_SEL    (BIT(7))
+#define GPIO_SIG184_IN_SEL_M  (GPIO_SIG184_IN_SEL_V << GPIO_SIG184_IN_SEL_S)
+#define GPIO_SIG184_IN_SEL_V  0x00000001U
+#define GPIO_SIG184_IN_SEL_S  7
+
+/** GPIO_FUNC185_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43c)
+/** GPIO_FUNC185_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC185_IN_SEL    0x0000003FU
+#define GPIO_FUNC185_IN_SEL_M  (GPIO_FUNC185_IN_SEL_V << GPIO_FUNC185_IN_SEL_S)
+#define GPIO_FUNC185_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC185_IN_SEL_S  0
+/** GPIO_FUNC185_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC185_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_M  (GPIO_FUNC185_IN_INV_SEL_V << GPIO_FUNC185_IN_INV_SEL_S)
+#define GPIO_FUNC185_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC185_IN_INV_SEL_S  6
+/** GPIO_SIG185_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG185_IN_SEL    (BIT(7))
+#define GPIO_SIG185_IN_SEL_M  (GPIO_SIG185_IN_SEL_V << GPIO_SIG185_IN_SEL_S)
+#define GPIO_SIG185_IN_SEL_V  0x00000001U
+#define GPIO_SIG185_IN_SEL_S  7
+
+/** GPIO_FUNC186_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440)
+/** GPIO_FUNC186_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC186_IN_SEL    0x0000003FU
+#define GPIO_FUNC186_IN_SEL_M  (GPIO_FUNC186_IN_SEL_V << GPIO_FUNC186_IN_SEL_S)
+#define GPIO_FUNC186_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC186_IN_SEL_S  0
+/** GPIO_FUNC186_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC186_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_M  (GPIO_FUNC186_IN_INV_SEL_V << GPIO_FUNC186_IN_INV_SEL_S)
+#define GPIO_FUNC186_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC186_IN_INV_SEL_S  6
+/** GPIO_SIG186_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG186_IN_SEL    (BIT(7))
+#define GPIO_SIG186_IN_SEL_M  (GPIO_SIG186_IN_SEL_V << GPIO_SIG186_IN_SEL_S)
+#define GPIO_SIG186_IN_SEL_V  0x00000001U
+#define GPIO_SIG186_IN_SEL_S  7
+
+/** GPIO_FUNC187_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444)
+/** GPIO_FUNC187_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC187_IN_SEL    0x0000003FU
+#define GPIO_FUNC187_IN_SEL_M  (GPIO_FUNC187_IN_SEL_V << GPIO_FUNC187_IN_SEL_S)
+#define GPIO_FUNC187_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC187_IN_SEL_S  0
+/** GPIO_FUNC187_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC187_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_M  (GPIO_FUNC187_IN_INV_SEL_V << GPIO_FUNC187_IN_INV_SEL_S)
+#define GPIO_FUNC187_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC187_IN_INV_SEL_S  6
+/** GPIO_SIG187_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG187_IN_SEL    (BIT(7))
+#define GPIO_SIG187_IN_SEL_M  (GPIO_SIG187_IN_SEL_V << GPIO_SIG187_IN_SEL_S)
+#define GPIO_SIG187_IN_SEL_V  0x00000001U
+#define GPIO_SIG187_IN_SEL_S  7
+
+/** GPIO_FUNC188_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448)
+/** GPIO_FUNC188_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC188_IN_SEL    0x0000003FU
+#define GPIO_FUNC188_IN_SEL_M  (GPIO_FUNC188_IN_SEL_V << GPIO_FUNC188_IN_SEL_S)
+#define GPIO_FUNC188_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC188_IN_SEL_S  0
+/** GPIO_FUNC188_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC188_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_M  (GPIO_FUNC188_IN_INV_SEL_V << GPIO_FUNC188_IN_INV_SEL_S)
+#define GPIO_FUNC188_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC188_IN_INV_SEL_S  6
+/** GPIO_SIG188_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG188_IN_SEL    (BIT(7))
+#define GPIO_SIG188_IN_SEL_M  (GPIO_SIG188_IN_SEL_V << GPIO_SIG188_IN_SEL_S)
+#define GPIO_SIG188_IN_SEL_V  0x00000001U
+#define GPIO_SIG188_IN_SEL_S  7
+
+/** GPIO_FUNC189_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c)
+/** GPIO_FUNC189_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC189_IN_SEL    0x0000003FU
+#define GPIO_FUNC189_IN_SEL_M  (GPIO_FUNC189_IN_SEL_V << GPIO_FUNC189_IN_SEL_S)
+#define GPIO_FUNC189_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC189_IN_SEL_S  0
+/** GPIO_FUNC189_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC189_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_M  (GPIO_FUNC189_IN_INV_SEL_V << GPIO_FUNC189_IN_INV_SEL_S)
+#define GPIO_FUNC189_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC189_IN_INV_SEL_S  6
+/** GPIO_SIG189_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG189_IN_SEL    (BIT(7))
+#define GPIO_SIG189_IN_SEL_M  (GPIO_SIG189_IN_SEL_V << GPIO_SIG189_IN_SEL_S)
+#define GPIO_SIG189_IN_SEL_V  0x00000001U
+#define GPIO_SIG189_IN_SEL_S  7
+
+/** GPIO_FUNC190_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450)
+/** GPIO_FUNC190_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC190_IN_SEL    0x0000003FU
+#define GPIO_FUNC190_IN_SEL_M  (GPIO_FUNC190_IN_SEL_V << GPIO_FUNC190_IN_SEL_S)
+#define GPIO_FUNC190_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC190_IN_SEL_S  0
+/** GPIO_FUNC190_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC190_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_M  (GPIO_FUNC190_IN_INV_SEL_V << GPIO_FUNC190_IN_INV_SEL_S)
+#define GPIO_FUNC190_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC190_IN_INV_SEL_S  6
+/** GPIO_SIG190_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG190_IN_SEL    (BIT(7))
+#define GPIO_SIG190_IN_SEL_M  (GPIO_SIG190_IN_SEL_V << GPIO_SIG190_IN_SEL_S)
+#define GPIO_SIG190_IN_SEL_V  0x00000001U
+#define GPIO_SIG190_IN_SEL_S  7
+
+/** GPIO_FUNC191_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454)
+/** GPIO_FUNC191_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC191_IN_SEL    0x0000003FU
+#define GPIO_FUNC191_IN_SEL_M  (GPIO_FUNC191_IN_SEL_V << GPIO_FUNC191_IN_SEL_S)
+#define GPIO_FUNC191_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC191_IN_SEL_S  0
+/** GPIO_FUNC191_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC191_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_M  (GPIO_FUNC191_IN_INV_SEL_V << GPIO_FUNC191_IN_INV_SEL_S)
+#define GPIO_FUNC191_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC191_IN_INV_SEL_S  6
+/** GPIO_SIG191_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG191_IN_SEL    (BIT(7))
+#define GPIO_SIG191_IN_SEL_M  (GPIO_SIG191_IN_SEL_V << GPIO_SIG191_IN_SEL_S)
+#define GPIO_SIG191_IN_SEL_V  0x00000001U
+#define GPIO_SIG191_IN_SEL_S  7
+
+/** GPIO_FUNC192_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458)
+/** GPIO_FUNC192_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC192_IN_SEL    0x0000003FU
+#define GPIO_FUNC192_IN_SEL_M  (GPIO_FUNC192_IN_SEL_V << GPIO_FUNC192_IN_SEL_S)
+#define GPIO_FUNC192_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC192_IN_SEL_S  0
+/** GPIO_FUNC192_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC192_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_M  (GPIO_FUNC192_IN_INV_SEL_V << GPIO_FUNC192_IN_INV_SEL_S)
+#define GPIO_FUNC192_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC192_IN_INV_SEL_S  6
+/** GPIO_SIG192_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG192_IN_SEL    (BIT(7))
+#define GPIO_SIG192_IN_SEL_M  (GPIO_SIG192_IN_SEL_V << GPIO_SIG192_IN_SEL_S)
+#define GPIO_SIG192_IN_SEL_V  0x00000001U
+#define GPIO_SIG192_IN_SEL_S  7
+
+/** GPIO_FUNC193_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c)
+/** GPIO_FUNC193_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC193_IN_SEL    0x0000003FU
+#define GPIO_FUNC193_IN_SEL_M  (GPIO_FUNC193_IN_SEL_V << GPIO_FUNC193_IN_SEL_S)
+#define GPIO_FUNC193_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC193_IN_SEL_S  0
+/** GPIO_FUNC193_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC193_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_M  (GPIO_FUNC193_IN_INV_SEL_V << GPIO_FUNC193_IN_INV_SEL_S)
+#define GPIO_FUNC193_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC193_IN_INV_SEL_S  6
+/** GPIO_SIG193_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG193_IN_SEL    (BIT(7))
+#define GPIO_SIG193_IN_SEL_M  (GPIO_SIG193_IN_SEL_V << GPIO_SIG193_IN_SEL_S)
+#define GPIO_SIG193_IN_SEL_V  0x00000001U
+#define GPIO_SIG193_IN_SEL_S  7
+
+/** GPIO_FUNC194_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460)
+/** GPIO_FUNC194_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC194_IN_SEL    0x0000003FU
+#define GPIO_FUNC194_IN_SEL_M  (GPIO_FUNC194_IN_SEL_V << GPIO_FUNC194_IN_SEL_S)
+#define GPIO_FUNC194_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC194_IN_SEL_S  0
+/** GPIO_FUNC194_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC194_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_M  (GPIO_FUNC194_IN_INV_SEL_V << GPIO_FUNC194_IN_INV_SEL_S)
+#define GPIO_FUNC194_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC194_IN_INV_SEL_S  6
+/** GPIO_SIG194_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG194_IN_SEL    (BIT(7))
+#define GPIO_SIG194_IN_SEL_M  (GPIO_SIG194_IN_SEL_V << GPIO_SIG194_IN_SEL_S)
+#define GPIO_SIG194_IN_SEL_V  0x00000001U
+#define GPIO_SIG194_IN_SEL_S  7
+
+/** GPIO_FUNC195_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464)
+/** GPIO_FUNC195_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC195_IN_SEL    0x0000003FU
+#define GPIO_FUNC195_IN_SEL_M  (GPIO_FUNC195_IN_SEL_V << GPIO_FUNC195_IN_SEL_S)
+#define GPIO_FUNC195_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC195_IN_SEL_S  0
+/** GPIO_FUNC195_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC195_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_M  (GPIO_FUNC195_IN_INV_SEL_V << GPIO_FUNC195_IN_INV_SEL_S)
+#define GPIO_FUNC195_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC195_IN_INV_SEL_S  6
+/** GPIO_SIG195_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG195_IN_SEL    (BIT(7))
+#define GPIO_SIG195_IN_SEL_M  (GPIO_SIG195_IN_SEL_V << GPIO_SIG195_IN_SEL_S)
+#define GPIO_SIG195_IN_SEL_V  0x00000001U
+#define GPIO_SIG195_IN_SEL_S  7
+
+/** GPIO_FUNC196_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468)
+/** GPIO_FUNC196_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC196_IN_SEL    0x0000003FU
+#define GPIO_FUNC196_IN_SEL_M  (GPIO_FUNC196_IN_SEL_V << GPIO_FUNC196_IN_SEL_S)
+#define GPIO_FUNC196_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC196_IN_SEL_S  0
+/** GPIO_FUNC196_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC196_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_M  (GPIO_FUNC196_IN_INV_SEL_V << GPIO_FUNC196_IN_INV_SEL_S)
+#define GPIO_FUNC196_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC196_IN_INV_SEL_S  6
+/** GPIO_SIG196_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG196_IN_SEL    (BIT(7))
+#define GPIO_SIG196_IN_SEL_M  (GPIO_SIG196_IN_SEL_V << GPIO_SIG196_IN_SEL_S)
+#define GPIO_SIG196_IN_SEL_V  0x00000001U
+#define GPIO_SIG196_IN_SEL_S  7
+
+/** GPIO_FUNC197_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c)
+/** GPIO_FUNC197_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC197_IN_SEL    0x0000003FU
+#define GPIO_FUNC197_IN_SEL_M  (GPIO_FUNC197_IN_SEL_V << GPIO_FUNC197_IN_SEL_S)
+#define GPIO_FUNC197_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC197_IN_SEL_S  0
+/** GPIO_FUNC197_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC197_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_M  (GPIO_FUNC197_IN_INV_SEL_V << GPIO_FUNC197_IN_INV_SEL_S)
+#define GPIO_FUNC197_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC197_IN_INV_SEL_S  6
+/** GPIO_SIG197_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG197_IN_SEL    (BIT(7))
+#define GPIO_SIG197_IN_SEL_M  (GPIO_SIG197_IN_SEL_V << GPIO_SIG197_IN_SEL_S)
+#define GPIO_SIG197_IN_SEL_V  0x00000001U
+#define GPIO_SIG197_IN_SEL_S  7
+
+/** GPIO_FUNC198_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470)
+/** GPIO_FUNC198_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC198_IN_SEL    0x0000003FU
+#define GPIO_FUNC198_IN_SEL_M  (GPIO_FUNC198_IN_SEL_V << GPIO_FUNC198_IN_SEL_S)
+#define GPIO_FUNC198_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC198_IN_SEL_S  0
+/** GPIO_FUNC198_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC198_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_M  (GPIO_FUNC198_IN_INV_SEL_V << GPIO_FUNC198_IN_INV_SEL_S)
+#define GPIO_FUNC198_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC198_IN_INV_SEL_S  6
+/** GPIO_SIG198_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG198_IN_SEL    (BIT(7))
+#define GPIO_SIG198_IN_SEL_M  (GPIO_SIG198_IN_SEL_V << GPIO_SIG198_IN_SEL_S)
+#define GPIO_SIG198_IN_SEL_V  0x00000001U
+#define GPIO_SIG198_IN_SEL_S  7
+
+/** GPIO_FUNC199_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474)
+/** GPIO_FUNC199_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC199_IN_SEL    0x0000003FU
+#define GPIO_FUNC199_IN_SEL_M  (GPIO_FUNC199_IN_SEL_V << GPIO_FUNC199_IN_SEL_S)
+#define GPIO_FUNC199_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC199_IN_SEL_S  0
+/** GPIO_FUNC199_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC199_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_M  (GPIO_FUNC199_IN_INV_SEL_V << GPIO_FUNC199_IN_INV_SEL_S)
+#define GPIO_FUNC199_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC199_IN_INV_SEL_S  6
+/** GPIO_SIG199_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG199_IN_SEL    (BIT(7))
+#define GPIO_SIG199_IN_SEL_M  (GPIO_SIG199_IN_SEL_V << GPIO_SIG199_IN_SEL_S)
+#define GPIO_SIG199_IN_SEL_V  0x00000001U
+#define GPIO_SIG199_IN_SEL_S  7
+
+/** GPIO_FUNC200_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478)
+/** GPIO_FUNC200_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC200_IN_SEL    0x0000003FU
+#define GPIO_FUNC200_IN_SEL_M  (GPIO_FUNC200_IN_SEL_V << GPIO_FUNC200_IN_SEL_S)
+#define GPIO_FUNC200_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC200_IN_SEL_S  0
+/** GPIO_FUNC200_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC200_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_M  (GPIO_FUNC200_IN_INV_SEL_V << GPIO_FUNC200_IN_INV_SEL_S)
+#define GPIO_FUNC200_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC200_IN_INV_SEL_S  6
+/** GPIO_SIG200_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG200_IN_SEL    (BIT(7))
+#define GPIO_SIG200_IN_SEL_M  (GPIO_SIG200_IN_SEL_V << GPIO_SIG200_IN_SEL_S)
+#define GPIO_SIG200_IN_SEL_V  0x00000001U
+#define GPIO_SIG200_IN_SEL_S  7
+
+/** GPIO_FUNC201_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c)
+/** GPIO_FUNC201_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC201_IN_SEL    0x0000003FU
+#define GPIO_FUNC201_IN_SEL_M  (GPIO_FUNC201_IN_SEL_V << GPIO_FUNC201_IN_SEL_S)
+#define GPIO_FUNC201_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC201_IN_SEL_S  0
+/** GPIO_FUNC201_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC201_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_M  (GPIO_FUNC201_IN_INV_SEL_V << GPIO_FUNC201_IN_INV_SEL_S)
+#define GPIO_FUNC201_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC201_IN_INV_SEL_S  6
+/** GPIO_SIG201_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG201_IN_SEL    (BIT(7))
+#define GPIO_SIG201_IN_SEL_M  (GPIO_SIG201_IN_SEL_V << GPIO_SIG201_IN_SEL_S)
+#define GPIO_SIG201_IN_SEL_V  0x00000001U
+#define GPIO_SIG201_IN_SEL_S  7
+
+/** GPIO_FUNC202_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480)
+/** GPIO_FUNC202_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC202_IN_SEL    0x0000003FU
+#define GPIO_FUNC202_IN_SEL_M  (GPIO_FUNC202_IN_SEL_V << GPIO_FUNC202_IN_SEL_S)
+#define GPIO_FUNC202_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC202_IN_SEL_S  0
+/** GPIO_FUNC202_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC202_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_M  (GPIO_FUNC202_IN_INV_SEL_V << GPIO_FUNC202_IN_INV_SEL_S)
+#define GPIO_FUNC202_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC202_IN_INV_SEL_S  6
+/** GPIO_SIG202_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG202_IN_SEL    (BIT(7))
+#define GPIO_SIG202_IN_SEL_M  (GPIO_SIG202_IN_SEL_V << GPIO_SIG202_IN_SEL_S)
+#define GPIO_SIG202_IN_SEL_V  0x00000001U
+#define GPIO_SIG202_IN_SEL_S  7
+
+/** GPIO_FUNC203_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484)
+/** GPIO_FUNC203_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC203_IN_SEL    0x0000003FU
+#define GPIO_FUNC203_IN_SEL_M  (GPIO_FUNC203_IN_SEL_V << GPIO_FUNC203_IN_SEL_S)
+#define GPIO_FUNC203_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC203_IN_SEL_S  0
+/** GPIO_FUNC203_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC203_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_M  (GPIO_FUNC203_IN_INV_SEL_V << GPIO_FUNC203_IN_INV_SEL_S)
+#define GPIO_FUNC203_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC203_IN_INV_SEL_S  6
+/** GPIO_SIG203_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG203_IN_SEL    (BIT(7))
+#define GPIO_SIG203_IN_SEL_M  (GPIO_SIG203_IN_SEL_V << GPIO_SIG203_IN_SEL_S)
+#define GPIO_SIG203_IN_SEL_V  0x00000001U
+#define GPIO_SIG203_IN_SEL_S  7
+
+/** GPIO_FUNC214_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0)
+/** GPIO_FUNC214_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC214_IN_SEL    0x0000003FU
+#define GPIO_FUNC214_IN_SEL_M  (GPIO_FUNC214_IN_SEL_V << GPIO_FUNC214_IN_SEL_S)
+#define GPIO_FUNC214_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC214_IN_SEL_S  0
+/** GPIO_FUNC214_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC214_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_M  (GPIO_FUNC214_IN_INV_SEL_V << GPIO_FUNC214_IN_INV_SEL_S)
+#define GPIO_FUNC214_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC214_IN_INV_SEL_S  6
+/** GPIO_SIG214_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG214_IN_SEL    (BIT(7))
+#define GPIO_SIG214_IN_SEL_M  (GPIO_SIG214_IN_SEL_V << GPIO_SIG214_IN_SEL_S)
+#define GPIO_SIG214_IN_SEL_V  0x00000001U
+#define GPIO_SIG214_IN_SEL_S  7
+
+/** GPIO_FUNC215_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4)
+/** GPIO_FUNC215_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC215_IN_SEL    0x0000003FU
+#define GPIO_FUNC215_IN_SEL_M  (GPIO_FUNC215_IN_SEL_V << GPIO_FUNC215_IN_SEL_S)
+#define GPIO_FUNC215_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC215_IN_SEL_S  0
+/** GPIO_FUNC215_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC215_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_M  (GPIO_FUNC215_IN_INV_SEL_V << GPIO_FUNC215_IN_INV_SEL_S)
+#define GPIO_FUNC215_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC215_IN_INV_SEL_S  6
+/** GPIO_SIG215_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG215_IN_SEL    (BIT(7))
+#define GPIO_SIG215_IN_SEL_M  (GPIO_SIG215_IN_SEL_V << GPIO_SIG215_IN_SEL_S)
+#define GPIO_SIG215_IN_SEL_V  0x00000001U
+#define GPIO_SIG215_IN_SEL_S  7
+
+/** GPIO_FUNC216_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8)
+/** GPIO_FUNC216_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC216_IN_SEL    0x0000003FU
+#define GPIO_FUNC216_IN_SEL_M  (GPIO_FUNC216_IN_SEL_V << GPIO_FUNC216_IN_SEL_S)
+#define GPIO_FUNC216_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC216_IN_SEL_S  0
+/** GPIO_FUNC216_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC216_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_M  (GPIO_FUNC216_IN_INV_SEL_V << GPIO_FUNC216_IN_INV_SEL_S)
+#define GPIO_FUNC216_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC216_IN_INV_SEL_S  6
+/** GPIO_SIG216_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG216_IN_SEL    (BIT(7))
+#define GPIO_SIG216_IN_SEL_M  (GPIO_SIG216_IN_SEL_V << GPIO_SIG216_IN_SEL_S)
+#define GPIO_SIG216_IN_SEL_V  0x00000001U
+#define GPIO_SIG216_IN_SEL_S  7
+
+/** GPIO_FUNC217_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4bc)
+/** GPIO_FUNC217_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC217_IN_SEL    0x0000003FU
+#define GPIO_FUNC217_IN_SEL_M  (GPIO_FUNC217_IN_SEL_V << GPIO_FUNC217_IN_SEL_S)
+#define GPIO_FUNC217_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC217_IN_SEL_S  0
+/** GPIO_FUNC217_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC217_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_M  (GPIO_FUNC217_IN_INV_SEL_V << GPIO_FUNC217_IN_INV_SEL_S)
+#define GPIO_FUNC217_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC217_IN_INV_SEL_S  6
+/** GPIO_SIG217_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG217_IN_SEL    (BIT(7))
+#define GPIO_SIG217_IN_SEL_M  (GPIO_SIG217_IN_SEL_V << GPIO_SIG217_IN_SEL_S)
+#define GPIO_SIG217_IN_SEL_V  0x00000001U
+#define GPIO_SIG217_IN_SEL_S  7
+
+/** GPIO_FUNC218_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c0)
+/** GPIO_FUNC218_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC218_IN_SEL    0x0000003FU
+#define GPIO_FUNC218_IN_SEL_M  (GPIO_FUNC218_IN_SEL_V << GPIO_FUNC218_IN_SEL_S)
+#define GPIO_FUNC218_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC218_IN_SEL_S  0
+/** GPIO_FUNC218_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC218_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_M  (GPIO_FUNC218_IN_INV_SEL_V << GPIO_FUNC218_IN_INV_SEL_S)
+#define GPIO_FUNC218_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC218_IN_INV_SEL_S  6
+/** GPIO_SIG218_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG218_IN_SEL    (BIT(7))
+#define GPIO_SIG218_IN_SEL_M  (GPIO_SIG218_IN_SEL_V << GPIO_SIG218_IN_SEL_S)
+#define GPIO_SIG218_IN_SEL_V  0x00000001U
+#define GPIO_SIG218_IN_SEL_S  7
+
+/** GPIO_FUNC219_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c4)
+/** GPIO_FUNC219_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC219_IN_SEL    0x0000003FU
+#define GPIO_FUNC219_IN_SEL_M  (GPIO_FUNC219_IN_SEL_V << GPIO_FUNC219_IN_SEL_S)
+#define GPIO_FUNC219_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC219_IN_SEL_S  0
+/** GPIO_FUNC219_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC219_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_M  (GPIO_FUNC219_IN_INV_SEL_V << GPIO_FUNC219_IN_INV_SEL_S)
+#define GPIO_FUNC219_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC219_IN_INV_SEL_S  6
+/** GPIO_SIG219_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG219_IN_SEL    (BIT(7))
+#define GPIO_SIG219_IN_SEL_M  (GPIO_SIG219_IN_SEL_V << GPIO_SIG219_IN_SEL_S)
+#define GPIO_SIG219_IN_SEL_V  0x00000001U
+#define GPIO_SIG219_IN_SEL_S  7
+
+/** GPIO_FUNC220_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c8)
+/** GPIO_FUNC220_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC220_IN_SEL    0x0000003FU
+#define GPIO_FUNC220_IN_SEL_M  (GPIO_FUNC220_IN_SEL_V << GPIO_FUNC220_IN_SEL_S)
+#define GPIO_FUNC220_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC220_IN_SEL_S  0
+/** GPIO_FUNC220_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC220_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_M  (GPIO_FUNC220_IN_INV_SEL_V << GPIO_FUNC220_IN_INV_SEL_S)
+#define GPIO_FUNC220_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC220_IN_INV_SEL_S  6
+/** GPIO_SIG220_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG220_IN_SEL    (BIT(7))
+#define GPIO_SIG220_IN_SEL_M  (GPIO_SIG220_IN_SEL_V << GPIO_SIG220_IN_SEL_S)
+#define GPIO_SIG220_IN_SEL_V  0x00000001U
+#define GPIO_SIG220_IN_SEL_S  7
+
+/** GPIO_FUNC221_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4cc)
+/** GPIO_FUNC221_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC221_IN_SEL    0x0000003FU
+#define GPIO_FUNC221_IN_SEL_M  (GPIO_FUNC221_IN_SEL_V << GPIO_FUNC221_IN_SEL_S)
+#define GPIO_FUNC221_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC221_IN_SEL_S  0
+/** GPIO_FUNC221_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC221_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_M  (GPIO_FUNC221_IN_INV_SEL_V << GPIO_FUNC221_IN_INV_SEL_S)
+#define GPIO_FUNC221_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC221_IN_INV_SEL_S  6
+/** GPIO_SIG221_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG221_IN_SEL    (BIT(7))
+#define GPIO_SIG221_IN_SEL_M  (GPIO_SIG221_IN_SEL_V << GPIO_SIG221_IN_SEL_S)
+#define GPIO_SIG221_IN_SEL_V  0x00000001U
+#define GPIO_SIG221_IN_SEL_S  7
+
+/** GPIO_FUNC222_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d0)
+/** GPIO_FUNC222_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC222_IN_SEL    0x0000003FU
+#define GPIO_FUNC222_IN_SEL_M  (GPIO_FUNC222_IN_SEL_V << GPIO_FUNC222_IN_SEL_S)
+#define GPIO_FUNC222_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC222_IN_SEL_S  0
+/** GPIO_FUNC222_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC222_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_M  (GPIO_FUNC222_IN_INV_SEL_V << GPIO_FUNC222_IN_INV_SEL_S)
+#define GPIO_FUNC222_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC222_IN_INV_SEL_S  6
+/** GPIO_SIG222_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG222_IN_SEL    (BIT(7))
+#define GPIO_SIG222_IN_SEL_M  (GPIO_SIG222_IN_SEL_V << GPIO_SIG222_IN_SEL_S)
+#define GPIO_SIG222_IN_SEL_V  0x00000001U
+#define GPIO_SIG222_IN_SEL_S  7
+
+/** GPIO_FUNC223_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d4)
+/** GPIO_FUNC223_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC223_IN_SEL    0x0000003FU
+#define GPIO_FUNC223_IN_SEL_M  (GPIO_FUNC223_IN_SEL_V << GPIO_FUNC223_IN_SEL_S)
+#define GPIO_FUNC223_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC223_IN_SEL_S  0
+/** GPIO_FUNC223_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC223_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_M  (GPIO_FUNC223_IN_INV_SEL_V << GPIO_FUNC223_IN_INV_SEL_S)
+#define GPIO_FUNC223_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC223_IN_INV_SEL_S  6
+/** GPIO_SIG223_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG223_IN_SEL    (BIT(7))
+#define GPIO_SIG223_IN_SEL_M  (GPIO_SIG223_IN_SEL_V << GPIO_SIG223_IN_SEL_S)
+#define GPIO_SIG223_IN_SEL_V  0x00000001U
+#define GPIO_SIG223_IN_SEL_S  7
+
+/** GPIO_FUNC224_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d8)
+/** GPIO_FUNC224_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC224_IN_SEL    0x0000003FU
+#define GPIO_FUNC224_IN_SEL_M  (GPIO_FUNC224_IN_SEL_V << GPIO_FUNC224_IN_SEL_S)
+#define GPIO_FUNC224_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC224_IN_SEL_S  0
+/** GPIO_FUNC224_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC224_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_M  (GPIO_FUNC224_IN_INV_SEL_V << GPIO_FUNC224_IN_INV_SEL_S)
+#define GPIO_FUNC224_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC224_IN_INV_SEL_S  6
+/** GPIO_SIG224_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG224_IN_SEL    (BIT(7))
+#define GPIO_SIG224_IN_SEL_M  (GPIO_SIG224_IN_SEL_V << GPIO_SIG224_IN_SEL_S)
+#define GPIO_SIG224_IN_SEL_V  0x00000001U
+#define GPIO_SIG224_IN_SEL_S  7
+
+/** GPIO_FUNC225_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4dc)
+/** GPIO_FUNC225_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC225_IN_SEL    0x0000003FU
+#define GPIO_FUNC225_IN_SEL_M  (GPIO_FUNC225_IN_SEL_V << GPIO_FUNC225_IN_SEL_S)
+#define GPIO_FUNC225_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC225_IN_SEL_S  0
+/** GPIO_FUNC225_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC225_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_M  (GPIO_FUNC225_IN_INV_SEL_V << GPIO_FUNC225_IN_INV_SEL_S)
+#define GPIO_FUNC225_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC225_IN_INV_SEL_S  6
+/** GPIO_SIG225_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG225_IN_SEL    (BIT(7))
+#define GPIO_SIG225_IN_SEL_M  (GPIO_SIG225_IN_SEL_V << GPIO_SIG225_IN_SEL_S)
+#define GPIO_SIG225_IN_SEL_V  0x00000001U
+#define GPIO_SIG225_IN_SEL_S  7
+
+/** GPIO_FUNC226_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e0)
+/** GPIO_FUNC226_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC226_IN_SEL    0x0000003FU
+#define GPIO_FUNC226_IN_SEL_M  (GPIO_FUNC226_IN_SEL_V << GPIO_FUNC226_IN_SEL_S)
+#define GPIO_FUNC226_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC226_IN_SEL_S  0
+/** GPIO_FUNC226_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC226_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_M  (GPIO_FUNC226_IN_INV_SEL_V << GPIO_FUNC226_IN_INV_SEL_S)
+#define GPIO_FUNC226_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC226_IN_INV_SEL_S  6
+/** GPIO_SIG226_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG226_IN_SEL    (BIT(7))
+#define GPIO_SIG226_IN_SEL_M  (GPIO_SIG226_IN_SEL_V << GPIO_SIG226_IN_SEL_S)
+#define GPIO_SIG226_IN_SEL_V  0x00000001U
+#define GPIO_SIG226_IN_SEL_S  7
+
+/** GPIO_FUNC227_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e4)
+/** GPIO_FUNC227_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC227_IN_SEL    0x0000003FU
+#define GPIO_FUNC227_IN_SEL_M  (GPIO_FUNC227_IN_SEL_V << GPIO_FUNC227_IN_SEL_S)
+#define GPIO_FUNC227_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC227_IN_SEL_S  0
+/** GPIO_FUNC227_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC227_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_M  (GPIO_FUNC227_IN_INV_SEL_V << GPIO_FUNC227_IN_INV_SEL_S)
+#define GPIO_FUNC227_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC227_IN_INV_SEL_S  6
+/** GPIO_SIG227_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG227_IN_SEL    (BIT(7))
+#define GPIO_SIG227_IN_SEL_M  (GPIO_SIG227_IN_SEL_V << GPIO_SIG227_IN_SEL_S)
+#define GPIO_SIG227_IN_SEL_V  0x00000001U
+#define GPIO_SIG227_IN_SEL_S  7
+
+/** GPIO_FUNC228_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e8)
+/** GPIO_FUNC228_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC228_IN_SEL    0x0000003FU
+#define GPIO_FUNC228_IN_SEL_M  (GPIO_FUNC228_IN_SEL_V << GPIO_FUNC228_IN_SEL_S)
+#define GPIO_FUNC228_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC228_IN_SEL_S  0
+/** GPIO_FUNC228_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC228_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_M  (GPIO_FUNC228_IN_INV_SEL_V << GPIO_FUNC228_IN_INV_SEL_S)
+#define GPIO_FUNC228_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC228_IN_INV_SEL_S  6
+/** GPIO_SIG228_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG228_IN_SEL    (BIT(7))
+#define GPIO_SIG228_IN_SEL_M  (GPIO_SIG228_IN_SEL_V << GPIO_SIG228_IN_SEL_S)
+#define GPIO_SIG228_IN_SEL_V  0x00000001U
+#define GPIO_SIG228_IN_SEL_S  7
+
+/** GPIO_FUNC229_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ec)
+/** GPIO_FUNC229_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC229_IN_SEL    0x0000003FU
+#define GPIO_FUNC229_IN_SEL_M  (GPIO_FUNC229_IN_SEL_V << GPIO_FUNC229_IN_SEL_S)
+#define GPIO_FUNC229_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC229_IN_SEL_S  0
+/** GPIO_FUNC229_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC229_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_M  (GPIO_FUNC229_IN_INV_SEL_V << GPIO_FUNC229_IN_INV_SEL_S)
+#define GPIO_FUNC229_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC229_IN_INV_SEL_S  6
+/** GPIO_SIG229_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG229_IN_SEL    (BIT(7))
+#define GPIO_SIG229_IN_SEL_M  (GPIO_SIG229_IN_SEL_V << GPIO_SIG229_IN_SEL_S)
+#define GPIO_SIG229_IN_SEL_V  0x00000001U
+#define GPIO_SIG229_IN_SEL_S  7
+
+/** GPIO_FUNC230_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f0)
+/** GPIO_FUNC230_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC230_IN_SEL    0x0000003FU
+#define GPIO_FUNC230_IN_SEL_M  (GPIO_FUNC230_IN_SEL_V << GPIO_FUNC230_IN_SEL_S)
+#define GPIO_FUNC230_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC230_IN_SEL_S  0
+/** GPIO_FUNC230_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC230_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_M  (GPIO_FUNC230_IN_INV_SEL_V << GPIO_FUNC230_IN_INV_SEL_S)
+#define GPIO_FUNC230_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC230_IN_INV_SEL_S  6
+/** GPIO_SIG230_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG230_IN_SEL    (BIT(7))
+#define GPIO_SIG230_IN_SEL_M  (GPIO_SIG230_IN_SEL_V << GPIO_SIG230_IN_SEL_S)
+#define GPIO_SIG230_IN_SEL_V  0x00000001U
+#define GPIO_SIG230_IN_SEL_S  7
+
+/** GPIO_FUNC231_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f4)
+/** GPIO_FUNC231_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC231_IN_SEL    0x0000003FU
+#define GPIO_FUNC231_IN_SEL_M  (GPIO_FUNC231_IN_SEL_V << GPIO_FUNC231_IN_SEL_S)
+#define GPIO_FUNC231_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC231_IN_SEL_S  0
+/** GPIO_FUNC231_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC231_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_M  (GPIO_FUNC231_IN_INV_SEL_V << GPIO_FUNC231_IN_INV_SEL_S)
+#define GPIO_FUNC231_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC231_IN_INV_SEL_S  6
+/** GPIO_SIG231_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG231_IN_SEL    (BIT(7))
+#define GPIO_SIG231_IN_SEL_M  (GPIO_SIG231_IN_SEL_V << GPIO_SIG231_IN_SEL_S)
+#define GPIO_SIG231_IN_SEL_V  0x00000001U
+#define GPIO_SIG231_IN_SEL_S  7
+
+/** GPIO_FUNC232_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f8)
+/** GPIO_FUNC232_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC232_IN_SEL    0x0000003FU
+#define GPIO_FUNC232_IN_SEL_M  (GPIO_FUNC232_IN_SEL_V << GPIO_FUNC232_IN_SEL_S)
+#define GPIO_FUNC232_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC232_IN_SEL_S  0
+/** GPIO_FUNC232_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC232_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_M  (GPIO_FUNC232_IN_INV_SEL_V << GPIO_FUNC232_IN_INV_SEL_S)
+#define GPIO_FUNC232_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC232_IN_INV_SEL_S  6
+/** GPIO_SIG232_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG232_IN_SEL    (BIT(7))
+#define GPIO_SIG232_IN_SEL_M  (GPIO_SIG232_IN_SEL_V << GPIO_SIG232_IN_SEL_S)
+#define GPIO_SIG232_IN_SEL_V  0x00000001U
+#define GPIO_SIG232_IN_SEL_S  7
+
+/** GPIO_FUNC233_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4fc)
+/** GPIO_FUNC233_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC233_IN_SEL    0x0000003FU
+#define GPIO_FUNC233_IN_SEL_M  (GPIO_FUNC233_IN_SEL_V << GPIO_FUNC233_IN_SEL_S)
+#define GPIO_FUNC233_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC233_IN_SEL_S  0
+/** GPIO_FUNC233_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC233_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_M  (GPIO_FUNC233_IN_INV_SEL_V << GPIO_FUNC233_IN_INV_SEL_S)
+#define GPIO_FUNC233_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC233_IN_INV_SEL_S  6
+/** GPIO_SIG233_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG233_IN_SEL    (BIT(7))
+#define GPIO_SIG233_IN_SEL_M  (GPIO_SIG233_IN_SEL_V << GPIO_SIG233_IN_SEL_S)
+#define GPIO_SIG233_IN_SEL_V  0x00000001U
+#define GPIO_SIG233_IN_SEL_S  7
+
+/** GPIO_FUNC234_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x500)
+/** GPIO_FUNC234_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC234_IN_SEL    0x0000003FU
+#define GPIO_FUNC234_IN_SEL_M  (GPIO_FUNC234_IN_SEL_V << GPIO_FUNC234_IN_SEL_S)
+#define GPIO_FUNC234_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC234_IN_SEL_S  0
+/** GPIO_FUNC234_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC234_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_M  (GPIO_FUNC234_IN_INV_SEL_V << GPIO_FUNC234_IN_INV_SEL_S)
+#define GPIO_FUNC234_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC234_IN_INV_SEL_S  6
+/** GPIO_SIG234_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG234_IN_SEL    (BIT(7))
+#define GPIO_SIG234_IN_SEL_M  (GPIO_SIG234_IN_SEL_V << GPIO_SIG234_IN_SEL_S)
+#define GPIO_SIG234_IN_SEL_V  0x00000001U
+#define GPIO_SIG234_IN_SEL_S  7
+
+/** GPIO_FUNC235_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x504)
+/** GPIO_FUNC235_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC235_IN_SEL    0x0000003FU
+#define GPIO_FUNC235_IN_SEL_M  (GPIO_FUNC235_IN_SEL_V << GPIO_FUNC235_IN_SEL_S)
+#define GPIO_FUNC235_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC235_IN_SEL_S  0
+/** GPIO_FUNC235_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC235_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_M  (GPIO_FUNC235_IN_INV_SEL_V << GPIO_FUNC235_IN_INV_SEL_S)
+#define GPIO_FUNC235_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC235_IN_INV_SEL_S  6
+/** GPIO_SIG235_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG235_IN_SEL    (BIT(7))
+#define GPIO_SIG235_IN_SEL_M  (GPIO_SIG235_IN_SEL_V << GPIO_SIG235_IN_SEL_S)
+#define GPIO_SIG235_IN_SEL_V  0x00000001U
+#define GPIO_SIG235_IN_SEL_S  7
+
+/** GPIO_FUNC236_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x508)
+/** GPIO_FUNC236_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC236_IN_SEL    0x0000003FU
+#define GPIO_FUNC236_IN_SEL_M  (GPIO_FUNC236_IN_SEL_V << GPIO_FUNC236_IN_SEL_S)
+#define GPIO_FUNC236_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC236_IN_SEL_S  0
+/** GPIO_FUNC236_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC236_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_M  (GPIO_FUNC236_IN_INV_SEL_V << GPIO_FUNC236_IN_INV_SEL_S)
+#define GPIO_FUNC236_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC236_IN_INV_SEL_S  6
+/** GPIO_SIG236_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG236_IN_SEL    (BIT(7))
+#define GPIO_SIG236_IN_SEL_M  (GPIO_SIG236_IN_SEL_V << GPIO_SIG236_IN_SEL_S)
+#define GPIO_SIG236_IN_SEL_V  0x00000001U
+#define GPIO_SIG236_IN_SEL_S  7
+
+/** GPIO_FUNC237_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x50c)
+/** GPIO_FUNC237_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC237_IN_SEL    0x0000003FU
+#define GPIO_FUNC237_IN_SEL_M  (GPIO_FUNC237_IN_SEL_V << GPIO_FUNC237_IN_SEL_S)
+#define GPIO_FUNC237_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC237_IN_SEL_S  0
+/** GPIO_FUNC237_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC237_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_M  (GPIO_FUNC237_IN_INV_SEL_V << GPIO_FUNC237_IN_INV_SEL_S)
+#define GPIO_FUNC237_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC237_IN_INV_SEL_S  6
+/** GPIO_SIG237_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG237_IN_SEL    (BIT(7))
+#define GPIO_SIG237_IN_SEL_M  (GPIO_SIG237_IN_SEL_V << GPIO_SIG237_IN_SEL_S)
+#define GPIO_SIG237_IN_SEL_V  0x00000001U
+#define GPIO_SIG237_IN_SEL_S  7
+
+/** GPIO_FUNC238_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x510)
+/** GPIO_FUNC238_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC238_IN_SEL    0x0000003FU
+#define GPIO_FUNC238_IN_SEL_M  (GPIO_FUNC238_IN_SEL_V << GPIO_FUNC238_IN_SEL_S)
+#define GPIO_FUNC238_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC238_IN_SEL_S  0
+/** GPIO_FUNC238_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC238_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_M  (GPIO_FUNC238_IN_INV_SEL_V << GPIO_FUNC238_IN_INV_SEL_S)
+#define GPIO_FUNC238_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC238_IN_INV_SEL_S  6
+/** GPIO_SIG238_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG238_IN_SEL    (BIT(7))
+#define GPIO_SIG238_IN_SEL_M  (GPIO_SIG238_IN_SEL_V << GPIO_SIG238_IN_SEL_S)
+#define GPIO_SIG238_IN_SEL_V  0x00000001U
+#define GPIO_SIG238_IN_SEL_S  7
+
+/** GPIO_FUNC239_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x514)
+/** GPIO_FUNC239_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC239_IN_SEL    0x0000003FU
+#define GPIO_FUNC239_IN_SEL_M  (GPIO_FUNC239_IN_SEL_V << GPIO_FUNC239_IN_SEL_S)
+#define GPIO_FUNC239_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC239_IN_SEL_S  0
+/** GPIO_FUNC239_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC239_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_M  (GPIO_FUNC239_IN_INV_SEL_V << GPIO_FUNC239_IN_INV_SEL_S)
+#define GPIO_FUNC239_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC239_IN_INV_SEL_S  6
+/** GPIO_SIG239_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG239_IN_SEL    (BIT(7))
+#define GPIO_SIG239_IN_SEL_M  (GPIO_SIG239_IN_SEL_V << GPIO_SIG239_IN_SEL_S)
+#define GPIO_SIG239_IN_SEL_V  0x00000001U
+#define GPIO_SIG239_IN_SEL_S  7
+
+/** GPIO_FUNC240_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x518)
+/** GPIO_FUNC240_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC240_IN_SEL    0x0000003FU
+#define GPIO_FUNC240_IN_SEL_M  (GPIO_FUNC240_IN_SEL_V << GPIO_FUNC240_IN_SEL_S)
+#define GPIO_FUNC240_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC240_IN_SEL_S  0
+/** GPIO_FUNC240_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC240_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_M  (GPIO_FUNC240_IN_INV_SEL_V << GPIO_FUNC240_IN_INV_SEL_S)
+#define GPIO_FUNC240_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC240_IN_INV_SEL_S  6
+/** GPIO_SIG240_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG240_IN_SEL    (BIT(7))
+#define GPIO_SIG240_IN_SEL_M  (GPIO_SIG240_IN_SEL_V << GPIO_SIG240_IN_SEL_S)
+#define GPIO_SIG240_IN_SEL_V  0x00000001U
+#define GPIO_SIG240_IN_SEL_S  7
+
+/** GPIO_FUNC241_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x51c)
+/** GPIO_FUNC241_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC241_IN_SEL    0x0000003FU
+#define GPIO_FUNC241_IN_SEL_M  (GPIO_FUNC241_IN_SEL_V << GPIO_FUNC241_IN_SEL_S)
+#define GPIO_FUNC241_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC241_IN_SEL_S  0
+/** GPIO_FUNC241_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC241_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_M  (GPIO_FUNC241_IN_INV_SEL_V << GPIO_FUNC241_IN_INV_SEL_S)
+#define GPIO_FUNC241_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC241_IN_INV_SEL_S  6
+/** GPIO_SIG241_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG241_IN_SEL    (BIT(7))
+#define GPIO_SIG241_IN_SEL_M  (GPIO_SIG241_IN_SEL_V << GPIO_SIG241_IN_SEL_S)
+#define GPIO_SIG241_IN_SEL_V  0x00000001U
+#define GPIO_SIG241_IN_SEL_S  7
+
+/** GPIO_FUNC242_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x520)
+/** GPIO_FUNC242_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC242_IN_SEL    0x0000003FU
+#define GPIO_FUNC242_IN_SEL_M  (GPIO_FUNC242_IN_SEL_V << GPIO_FUNC242_IN_SEL_S)
+#define GPIO_FUNC242_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC242_IN_SEL_S  0
+/** GPIO_FUNC242_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC242_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_M  (GPIO_FUNC242_IN_INV_SEL_V << GPIO_FUNC242_IN_INV_SEL_S)
+#define GPIO_FUNC242_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC242_IN_INV_SEL_S  6
+/** GPIO_SIG242_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG242_IN_SEL    (BIT(7))
+#define GPIO_SIG242_IN_SEL_M  (GPIO_SIG242_IN_SEL_V << GPIO_SIG242_IN_SEL_S)
+#define GPIO_SIG242_IN_SEL_V  0x00000001U
+#define GPIO_SIG242_IN_SEL_S  7
+
+/** GPIO_FUNC243_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x524)
+/** GPIO_FUNC243_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC243_IN_SEL    0x0000003FU
+#define GPIO_FUNC243_IN_SEL_M  (GPIO_FUNC243_IN_SEL_V << GPIO_FUNC243_IN_SEL_S)
+#define GPIO_FUNC243_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC243_IN_SEL_S  0
+/** GPIO_FUNC243_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC243_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_M  (GPIO_FUNC243_IN_INV_SEL_V << GPIO_FUNC243_IN_INV_SEL_S)
+#define GPIO_FUNC243_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC243_IN_INV_SEL_S  6
+/** GPIO_SIG243_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG243_IN_SEL    (BIT(7))
+#define GPIO_SIG243_IN_SEL_M  (GPIO_SIG243_IN_SEL_V << GPIO_SIG243_IN_SEL_S)
+#define GPIO_SIG243_IN_SEL_V  0x00000001U
+#define GPIO_SIG243_IN_SEL_S  7
+
+/** GPIO_FUNC244_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x528)
+/** GPIO_FUNC244_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC244_IN_SEL    0x0000003FU
+#define GPIO_FUNC244_IN_SEL_M  (GPIO_FUNC244_IN_SEL_V << GPIO_FUNC244_IN_SEL_S)
+#define GPIO_FUNC244_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC244_IN_SEL_S  0
+/** GPIO_FUNC244_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC244_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_M  (GPIO_FUNC244_IN_INV_SEL_V << GPIO_FUNC244_IN_INV_SEL_S)
+#define GPIO_FUNC244_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC244_IN_INV_SEL_S  6
+/** GPIO_SIG244_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG244_IN_SEL    (BIT(7))
+#define GPIO_SIG244_IN_SEL_M  (GPIO_SIG244_IN_SEL_V << GPIO_SIG244_IN_SEL_S)
+#define GPIO_SIG244_IN_SEL_V  0x00000001U
+#define GPIO_SIG244_IN_SEL_S  7
+
+/** GPIO_FUNC245_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x52c)
+/** GPIO_FUNC245_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC245_IN_SEL    0x0000003FU
+#define GPIO_FUNC245_IN_SEL_M  (GPIO_FUNC245_IN_SEL_V << GPIO_FUNC245_IN_SEL_S)
+#define GPIO_FUNC245_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC245_IN_SEL_S  0
+/** GPIO_FUNC245_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC245_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_M  (GPIO_FUNC245_IN_INV_SEL_V << GPIO_FUNC245_IN_INV_SEL_S)
+#define GPIO_FUNC245_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC245_IN_INV_SEL_S  6
+/** GPIO_SIG245_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG245_IN_SEL    (BIT(7))
+#define GPIO_SIG245_IN_SEL_M  (GPIO_SIG245_IN_SEL_V << GPIO_SIG245_IN_SEL_S)
+#define GPIO_SIG245_IN_SEL_V  0x00000001U
+#define GPIO_SIG245_IN_SEL_S  7
+
+/** GPIO_FUNC246_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x530)
+/** GPIO_FUNC246_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC246_IN_SEL    0x0000003FU
+#define GPIO_FUNC246_IN_SEL_M  (GPIO_FUNC246_IN_SEL_V << GPIO_FUNC246_IN_SEL_S)
+#define GPIO_FUNC246_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC246_IN_SEL_S  0
+/** GPIO_FUNC246_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC246_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_M  (GPIO_FUNC246_IN_INV_SEL_V << GPIO_FUNC246_IN_INV_SEL_S)
+#define GPIO_FUNC246_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC246_IN_INV_SEL_S  6
+/** GPIO_SIG246_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG246_IN_SEL    (BIT(7))
+#define GPIO_SIG246_IN_SEL_M  (GPIO_SIG246_IN_SEL_V << GPIO_SIG246_IN_SEL_S)
+#define GPIO_SIG246_IN_SEL_V  0x00000001U
+#define GPIO_SIG246_IN_SEL_S  7
+
+/** GPIO_FUNC247_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x534)
+/** GPIO_FUNC247_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC247_IN_SEL    0x0000003FU
+#define GPIO_FUNC247_IN_SEL_M  (GPIO_FUNC247_IN_SEL_V << GPIO_FUNC247_IN_SEL_S)
+#define GPIO_FUNC247_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC247_IN_SEL_S  0
+/** GPIO_FUNC247_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC247_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_M  (GPIO_FUNC247_IN_INV_SEL_V << GPIO_FUNC247_IN_INV_SEL_S)
+#define GPIO_FUNC247_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC247_IN_INV_SEL_S  6
+/** GPIO_SIG247_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG247_IN_SEL    (BIT(7))
+#define GPIO_SIG247_IN_SEL_M  (GPIO_SIG247_IN_SEL_V << GPIO_SIG247_IN_SEL_S)
+#define GPIO_SIG247_IN_SEL_V  0x00000001U
+#define GPIO_SIG247_IN_SEL_S  7
+
+/** GPIO_FUNC248_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x538)
+/** GPIO_FUNC248_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC248_IN_SEL    0x0000003FU
+#define GPIO_FUNC248_IN_SEL_M  (GPIO_FUNC248_IN_SEL_V << GPIO_FUNC248_IN_SEL_S)
+#define GPIO_FUNC248_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC248_IN_SEL_S  0
+/** GPIO_FUNC248_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC248_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_M  (GPIO_FUNC248_IN_INV_SEL_V << GPIO_FUNC248_IN_INV_SEL_S)
+#define GPIO_FUNC248_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC248_IN_INV_SEL_S  6
+/** GPIO_SIG248_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG248_IN_SEL    (BIT(7))
+#define GPIO_SIG248_IN_SEL_M  (GPIO_SIG248_IN_SEL_V << GPIO_SIG248_IN_SEL_S)
+#define GPIO_SIG248_IN_SEL_V  0x00000001U
+#define GPIO_SIG248_IN_SEL_S  7
+
+/** GPIO_FUNC249_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x53c)
+/** GPIO_FUNC249_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC249_IN_SEL    0x0000003FU
+#define GPIO_FUNC249_IN_SEL_M  (GPIO_FUNC249_IN_SEL_V << GPIO_FUNC249_IN_SEL_S)
+#define GPIO_FUNC249_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC249_IN_SEL_S  0
+/** GPIO_FUNC249_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC249_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_M  (GPIO_FUNC249_IN_INV_SEL_V << GPIO_FUNC249_IN_INV_SEL_S)
+#define GPIO_FUNC249_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC249_IN_INV_SEL_S  6
+/** GPIO_SIG249_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG249_IN_SEL    (BIT(7))
+#define GPIO_SIG249_IN_SEL_M  (GPIO_SIG249_IN_SEL_V << GPIO_SIG249_IN_SEL_S)
+#define GPIO_SIG249_IN_SEL_V  0x00000001U
+#define GPIO_SIG249_IN_SEL_S  7
+
+/** GPIO_FUNC250_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x540)
+/** GPIO_FUNC250_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC250_IN_SEL    0x0000003FU
+#define GPIO_FUNC250_IN_SEL_M  (GPIO_FUNC250_IN_SEL_V << GPIO_FUNC250_IN_SEL_S)
+#define GPIO_FUNC250_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC250_IN_SEL_S  0
+/** GPIO_FUNC250_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC250_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_M  (GPIO_FUNC250_IN_INV_SEL_V << GPIO_FUNC250_IN_INV_SEL_S)
+#define GPIO_FUNC250_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC250_IN_INV_SEL_S  6
+/** GPIO_SIG250_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG250_IN_SEL    (BIT(7))
+#define GPIO_SIG250_IN_SEL_M  (GPIO_SIG250_IN_SEL_V << GPIO_SIG250_IN_SEL_S)
+#define GPIO_SIG250_IN_SEL_V  0x00000001U
+#define GPIO_SIG250_IN_SEL_S  7
+
+/** GPIO_FUNC251_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x544)
+/** GPIO_FUNC251_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC251_IN_SEL    0x0000003FU
+#define GPIO_FUNC251_IN_SEL_M  (GPIO_FUNC251_IN_SEL_V << GPIO_FUNC251_IN_SEL_S)
+#define GPIO_FUNC251_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC251_IN_SEL_S  0
+/** GPIO_FUNC251_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC251_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_M  (GPIO_FUNC251_IN_INV_SEL_V << GPIO_FUNC251_IN_INV_SEL_S)
+#define GPIO_FUNC251_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC251_IN_INV_SEL_S  6
+/** GPIO_SIG251_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG251_IN_SEL    (BIT(7))
+#define GPIO_SIG251_IN_SEL_M  (GPIO_SIG251_IN_SEL_V << GPIO_SIG251_IN_SEL_S)
+#define GPIO_SIG251_IN_SEL_V  0x00000001U
+#define GPIO_SIG251_IN_SEL_S  7
+
+/** GPIO_FUNC252_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x548)
+/** GPIO_FUNC252_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC252_IN_SEL    0x0000003FU
+#define GPIO_FUNC252_IN_SEL_M  (GPIO_FUNC252_IN_SEL_V << GPIO_FUNC252_IN_SEL_S)
+#define GPIO_FUNC252_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC252_IN_SEL_S  0
+/** GPIO_FUNC252_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC252_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_M  (GPIO_FUNC252_IN_INV_SEL_V << GPIO_FUNC252_IN_INV_SEL_S)
+#define GPIO_FUNC252_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC252_IN_INV_SEL_S  6
+/** GPIO_SIG252_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG252_IN_SEL    (BIT(7))
+#define GPIO_SIG252_IN_SEL_M  (GPIO_SIG252_IN_SEL_V << GPIO_SIG252_IN_SEL_S)
+#define GPIO_SIG252_IN_SEL_V  0x00000001U
+#define GPIO_SIG252_IN_SEL_S  7
+
+/** GPIO_FUNC253_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x54c)
+/** GPIO_FUNC253_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC253_IN_SEL    0x0000003FU
+#define GPIO_FUNC253_IN_SEL_M  (GPIO_FUNC253_IN_SEL_V << GPIO_FUNC253_IN_SEL_S)
+#define GPIO_FUNC253_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC253_IN_SEL_S  0
+/** GPIO_FUNC253_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC253_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_M  (GPIO_FUNC253_IN_INV_SEL_V << GPIO_FUNC253_IN_INV_SEL_S)
+#define GPIO_FUNC253_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC253_IN_INV_SEL_S  6
+/** GPIO_SIG253_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG253_IN_SEL    (BIT(7))
+#define GPIO_SIG253_IN_SEL_M  (GPIO_SIG253_IN_SEL_V << GPIO_SIG253_IN_SEL_S)
+#define GPIO_SIG253_IN_SEL_V  0x00000001U
+#define GPIO_SIG253_IN_SEL_S  7
+
+/** GPIO_FUNC254_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x550)
+/** GPIO_FUNC254_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC254_IN_SEL    0x0000003FU
+#define GPIO_FUNC254_IN_SEL_M  (GPIO_FUNC254_IN_SEL_V << GPIO_FUNC254_IN_SEL_S)
+#define GPIO_FUNC254_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC254_IN_SEL_S  0
+/** GPIO_FUNC254_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC254_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_M  (GPIO_FUNC254_IN_INV_SEL_V << GPIO_FUNC254_IN_INV_SEL_S)
+#define GPIO_FUNC254_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC254_IN_INV_SEL_S  6
+/** GPIO_SIG254_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG254_IN_SEL    (BIT(7))
+#define GPIO_SIG254_IN_SEL_M  (GPIO_SIG254_IN_SEL_V << GPIO_SIG254_IN_SEL_S)
+#define GPIO_SIG254_IN_SEL_V  0x00000001U
+#define GPIO_SIG254_IN_SEL_S  7
+
+/** GPIO_FUNC255_IN_SEL_CFG_REG register
+ *  GPIO input function configuration register
+ */
+#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554)
+/** GPIO_FUNC255_IN_SEL : R/W; bitpos: [5:0]; default: 62;
+ *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+ *  high level. s=0x3E: set this port always low level.
+ */
+#define GPIO_FUNC255_IN_SEL    0x0000003FU
+#define GPIO_FUNC255_IN_SEL_M  (GPIO_FUNC255_IN_SEL_V << GPIO_FUNC255_IN_SEL_S)
+#define GPIO_FUNC255_IN_SEL_V  0x0000003FU
+#define GPIO_FUNC255_IN_SEL_S  0
+/** GPIO_FUNC255_IN_INV_SEL : R/W; bitpos: [6]; default: 0;
+ *  set this bit to invert input signal. 1:invert. 0:not invert.
+ */
+#define GPIO_FUNC255_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_M  (GPIO_FUNC255_IN_INV_SEL_V << GPIO_FUNC255_IN_INV_SEL_S)
+#define GPIO_FUNC255_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC255_IN_INV_SEL_S  6
+/** GPIO_SIG255_IN_SEL : R/W; bitpos: [7]; default: 0;
+ *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+ */
+#define GPIO_SIG255_IN_SEL    (BIT(7))
+#define GPIO_SIG255_IN_SEL_M  (GPIO_SIG255_IN_SEL_V << GPIO_SIG255_IN_SEL_S)
+#define GPIO_SIG255_IN_SEL_V  0x00000001U
+#define GPIO_SIG255_IN_SEL_S  7
+
+/** GPIO_FUNC0_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558)
+/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC0_OUT_SEL    0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
+#define GPIO_FUNC0_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_S  0
+/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OUT_INV_SEL_S  9
+/** GPIO_FUNC0_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC0_OEN_SEL    (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_M  (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S)
+#define GPIO_FUNC0_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC0_OEN_SEL_S  10
+/** GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC0_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_M  (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S)
+#define GPIO_FUNC0_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC1_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c)
+/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC1_OUT_SEL    0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
+#define GPIO_FUNC1_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_S  0
+/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OUT_INV_SEL_S  9
+/** GPIO_FUNC1_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC1_OEN_SEL    (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_M  (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S)
+#define GPIO_FUNC1_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC1_OEN_SEL_S  10
+/** GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC1_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_M  (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S)
+#define GPIO_FUNC1_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC2_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560)
+/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC2_OUT_SEL    0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
+#define GPIO_FUNC2_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_S  0
+/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OUT_INV_SEL_S  9
+/** GPIO_FUNC2_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC2_OEN_SEL    (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_M  (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S)
+#define GPIO_FUNC2_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC2_OEN_SEL_S  10
+/** GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC2_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_M  (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S)
+#define GPIO_FUNC2_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC3_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564)
+/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC3_OUT_SEL    0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
+#define GPIO_FUNC3_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_S  0
+/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OUT_INV_SEL_S  9
+/** GPIO_FUNC3_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC3_OEN_SEL    (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_M  (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S)
+#define GPIO_FUNC3_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC3_OEN_SEL_S  10
+/** GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC3_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_M  (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S)
+#define GPIO_FUNC3_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC4_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568)
+/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC4_OUT_SEL    0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
+#define GPIO_FUNC4_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_S  0
+/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OUT_INV_SEL_S  9
+/** GPIO_FUNC4_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC4_OEN_SEL    (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_M  (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S)
+#define GPIO_FUNC4_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC4_OEN_SEL_S  10
+/** GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC4_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_M  (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S)
+#define GPIO_FUNC4_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC5_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c)
+/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC5_OUT_SEL    0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
+#define GPIO_FUNC5_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_S  0
+/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OUT_INV_SEL_S  9
+/** GPIO_FUNC5_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC5_OEN_SEL    (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_M  (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S)
+#define GPIO_FUNC5_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC5_OEN_SEL_S  10
+/** GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC5_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_M  (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S)
+#define GPIO_FUNC5_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC6_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570)
+/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC6_OUT_SEL    0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
+#define GPIO_FUNC6_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_S  0
+/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OUT_INV_SEL_S  9
+/** GPIO_FUNC6_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC6_OEN_SEL    (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_M  (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S)
+#define GPIO_FUNC6_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC6_OEN_SEL_S  10
+/** GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC6_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_M  (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S)
+#define GPIO_FUNC6_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC7_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574)
+/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC7_OUT_SEL    0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
+#define GPIO_FUNC7_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_S  0
+/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OUT_INV_SEL_S  9
+/** GPIO_FUNC7_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC7_OEN_SEL    (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_M  (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S)
+#define GPIO_FUNC7_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC7_OEN_SEL_S  10
+/** GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC7_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_M  (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S)
+#define GPIO_FUNC7_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC8_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578)
+/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC8_OUT_SEL    0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
+#define GPIO_FUNC8_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_S  0
+/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OUT_INV_SEL_S  9
+/** GPIO_FUNC8_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC8_OEN_SEL    (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_M  (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S)
+#define GPIO_FUNC8_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC8_OEN_SEL_S  10
+/** GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC8_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_M  (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S)
+#define GPIO_FUNC8_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC9_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c)
+/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC9_OUT_SEL    0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
+#define GPIO_FUNC9_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_S  0
+/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OUT_INV_SEL_S  9
+/** GPIO_FUNC9_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC9_OEN_SEL    (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_M  (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S)
+#define GPIO_FUNC9_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC9_OEN_SEL_S  10
+/** GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC9_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_M  (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S)
+#define GPIO_FUNC9_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC10_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580)
+/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC10_OUT_SEL    0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
+#define GPIO_FUNC10_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_S  0
+/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OUT_INV_SEL_S  9
+/** GPIO_FUNC10_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC10_OEN_SEL    (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_M  (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S)
+#define GPIO_FUNC10_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC10_OEN_SEL_S  10
+/** GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC10_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_M  (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S)
+#define GPIO_FUNC10_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC11_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584)
+/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC11_OUT_SEL    0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
+#define GPIO_FUNC11_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_S  0
+/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OUT_INV_SEL_S  9
+/** GPIO_FUNC11_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC11_OEN_SEL    (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_M  (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S)
+#define GPIO_FUNC11_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC11_OEN_SEL_S  10
+/** GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC11_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_M  (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S)
+#define GPIO_FUNC11_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC12_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588)
+/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC12_OUT_SEL    0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
+#define GPIO_FUNC12_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_S  0
+/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OUT_INV_SEL_S  9
+/** GPIO_FUNC12_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC12_OEN_SEL    (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_M  (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S)
+#define GPIO_FUNC12_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC12_OEN_SEL_S  10
+/** GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC12_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_M  (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S)
+#define GPIO_FUNC12_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC13_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c)
+/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC13_OUT_SEL    0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
+#define GPIO_FUNC13_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_S  0
+/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OUT_INV_SEL_S  9
+/** GPIO_FUNC13_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC13_OEN_SEL    (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_M  (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S)
+#define GPIO_FUNC13_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC13_OEN_SEL_S  10
+/** GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC13_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_M  (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S)
+#define GPIO_FUNC13_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC14_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590)
+/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC14_OUT_SEL    0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
+#define GPIO_FUNC14_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_S  0
+/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OUT_INV_SEL_S  9
+/** GPIO_FUNC14_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC14_OEN_SEL    (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_M  (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S)
+#define GPIO_FUNC14_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC14_OEN_SEL_S  10
+/** GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC14_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_M  (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S)
+#define GPIO_FUNC14_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC15_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594)
+/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC15_OUT_SEL    0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
+#define GPIO_FUNC15_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_S  0
+/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OUT_INV_SEL_S  9
+/** GPIO_FUNC15_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC15_OEN_SEL    (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_M  (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S)
+#define GPIO_FUNC15_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC15_OEN_SEL_S  10
+/** GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC15_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_M  (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S)
+#define GPIO_FUNC15_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC16_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598)
+/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC16_OUT_SEL    0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
+#define GPIO_FUNC16_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_S  0
+/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OUT_INV_SEL_S  9
+/** GPIO_FUNC16_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC16_OEN_SEL    (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_M  (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S)
+#define GPIO_FUNC16_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC16_OEN_SEL_S  10
+/** GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC16_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_M  (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S)
+#define GPIO_FUNC16_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC17_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c)
+/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC17_OUT_SEL    0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
+#define GPIO_FUNC17_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_S  0
+/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OUT_INV_SEL_S  9
+/** GPIO_FUNC17_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC17_OEN_SEL    (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_M  (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S)
+#define GPIO_FUNC17_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC17_OEN_SEL_S  10
+/** GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC17_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_M  (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S)
+#define GPIO_FUNC17_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC18_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0)
+/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC18_OUT_SEL    0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
+#define GPIO_FUNC18_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_S  0
+/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OUT_INV_SEL_S  9
+/** GPIO_FUNC18_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC18_OEN_SEL    (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_M  (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S)
+#define GPIO_FUNC18_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC18_OEN_SEL_S  10
+/** GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC18_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_M  (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S)
+#define GPIO_FUNC18_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC19_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4)
+/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC19_OUT_SEL    0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
+#define GPIO_FUNC19_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_S  0
+/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OUT_INV_SEL_S  9
+/** GPIO_FUNC19_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC19_OEN_SEL    (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_M  (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S)
+#define GPIO_FUNC19_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC19_OEN_SEL_S  10
+/** GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC19_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_M  (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S)
+#define GPIO_FUNC19_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC20_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8)
+/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC20_OUT_SEL    0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
+#define GPIO_FUNC20_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_S  0
+/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OUT_INV_SEL_S  9
+/** GPIO_FUNC20_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC20_OEN_SEL    (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_M  (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S)
+#define GPIO_FUNC20_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC20_OEN_SEL_S  10
+/** GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC20_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_M  (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S)
+#define GPIO_FUNC20_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC21_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac)
+/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC21_OUT_SEL    0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
+#define GPIO_FUNC21_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_S  0
+/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OUT_INV_SEL_S  9
+/** GPIO_FUNC21_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC21_OEN_SEL    (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_M  (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S)
+#define GPIO_FUNC21_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC21_OEN_SEL_S  10
+/** GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC21_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_M  (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S)
+#define GPIO_FUNC21_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC22_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0)
+/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC22_OUT_SEL    0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_M  (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
+#define GPIO_FUNC22_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_S  0
+/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC22_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OUT_INV_SEL_S  9
+/** GPIO_FUNC22_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC22_OEN_SEL    (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_M  (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S)
+#define GPIO_FUNC22_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC22_OEN_SEL_S  10
+/** GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC22_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_M  (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S)
+#define GPIO_FUNC22_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC23_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4)
+/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC23_OUT_SEL    0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_M  (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
+#define GPIO_FUNC23_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_S  0
+/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC23_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OUT_INV_SEL_S  9
+/** GPIO_FUNC23_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC23_OEN_SEL    (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_M  (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S)
+#define GPIO_FUNC23_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC23_OEN_SEL_S  10
+/** GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC23_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_M  (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S)
+#define GPIO_FUNC23_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC24_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8)
+/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC24_OUT_SEL    0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_M  (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
+#define GPIO_FUNC24_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_S  0
+/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC24_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OUT_INV_SEL_S  9
+/** GPIO_FUNC24_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC24_OEN_SEL    (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_M  (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S)
+#define GPIO_FUNC24_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC24_OEN_SEL_S  10
+/** GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC24_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_M  (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S)
+#define GPIO_FUNC24_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC25_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc)
+/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC25_OUT_SEL    0x000001FFU
+#define GPIO_FUNC25_OUT_SEL_M  (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S)
+#define GPIO_FUNC25_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC25_OUT_SEL_S  0
+/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC25_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_M  (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S)
+#define GPIO_FUNC25_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_OUT_INV_SEL_S  9
+/** GPIO_FUNC25_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC25_OEN_SEL    (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_M  (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S)
+#define GPIO_FUNC25_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC25_OEN_SEL_S  10
+/** GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC25_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_M  (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S)
+#define GPIO_FUNC25_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC26_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0)
+/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC26_OUT_SEL    0x000001FFU
+#define GPIO_FUNC26_OUT_SEL_M  (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S)
+#define GPIO_FUNC26_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC26_OUT_SEL_S  0
+/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC26_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_M  (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S)
+#define GPIO_FUNC26_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_OUT_INV_SEL_S  9
+/** GPIO_FUNC26_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC26_OEN_SEL    (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_M  (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S)
+#define GPIO_FUNC26_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC26_OEN_SEL_S  10
+/** GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC26_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_M  (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S)
+#define GPIO_FUNC26_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC27_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4)
+/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC27_OUT_SEL    0x000001FFU
+#define GPIO_FUNC27_OUT_SEL_M  (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S)
+#define GPIO_FUNC27_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC27_OUT_SEL_S  0
+/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC27_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_M  (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S)
+#define GPIO_FUNC27_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_OUT_INV_SEL_S  9
+/** GPIO_FUNC27_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC27_OEN_SEL    (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_M  (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S)
+#define GPIO_FUNC27_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC27_OEN_SEL_S  10
+/** GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC27_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_M  (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S)
+#define GPIO_FUNC27_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC28_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8)
+/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC28_OUT_SEL    0x000001FFU
+#define GPIO_FUNC28_OUT_SEL_M  (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
+#define GPIO_FUNC28_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC28_OUT_SEL_S  0
+/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC28_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_M  (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S)
+#define GPIO_FUNC28_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_OUT_INV_SEL_S  9
+/** GPIO_FUNC28_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC28_OEN_SEL    (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_M  (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S)
+#define GPIO_FUNC28_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC28_OEN_SEL_S  10
+/** GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC28_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_M  (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S)
+#define GPIO_FUNC28_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC29_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc)
+/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC29_OUT_SEL    0x000001FFU
+#define GPIO_FUNC29_OUT_SEL_M  (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S)
+#define GPIO_FUNC29_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC29_OUT_SEL_S  0
+/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC29_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_M  (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S)
+#define GPIO_FUNC29_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_OUT_INV_SEL_S  9
+/** GPIO_FUNC29_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC29_OEN_SEL    (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_M  (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S)
+#define GPIO_FUNC29_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC29_OEN_SEL_S  10
+/** GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC29_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_M  (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S)
+#define GPIO_FUNC29_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC30_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0)
+/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC30_OUT_SEL    0x000001FFU
+#define GPIO_FUNC30_OUT_SEL_M  (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S)
+#define GPIO_FUNC30_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC30_OUT_SEL_S  0
+/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC30_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_M  (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S)
+#define GPIO_FUNC30_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_OUT_INV_SEL_S  9
+/** GPIO_FUNC30_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC30_OEN_SEL    (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_M  (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S)
+#define GPIO_FUNC30_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC30_OEN_SEL_S  10
+/** GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC30_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_M  (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S)
+#define GPIO_FUNC30_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC31_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4)
+/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC31_OUT_SEL    0x000001FFU
+#define GPIO_FUNC31_OUT_SEL_M  (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S)
+#define GPIO_FUNC31_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC31_OUT_SEL_S  0
+/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC31_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_M  (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S)
+#define GPIO_FUNC31_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_OUT_INV_SEL_S  9
+/** GPIO_FUNC31_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC31_OEN_SEL    (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_M  (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S)
+#define GPIO_FUNC31_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC31_OEN_SEL_S  10
+/** GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC31_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_M  (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S)
+#define GPIO_FUNC31_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC32_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8)
+/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC32_OUT_SEL    0x000001FFU
+#define GPIO_FUNC32_OUT_SEL_M  (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S)
+#define GPIO_FUNC32_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC32_OUT_SEL_S  0
+/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC32_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_M  (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S)
+#define GPIO_FUNC32_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_OUT_INV_SEL_S  9
+/** GPIO_FUNC32_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC32_OEN_SEL    (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_M  (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S)
+#define GPIO_FUNC32_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC32_OEN_SEL_S  10
+/** GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC32_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_M  (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S)
+#define GPIO_FUNC32_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC33_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc)
+/** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC33_OUT_SEL    0x000001FFU
+#define GPIO_FUNC33_OUT_SEL_M  (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S)
+#define GPIO_FUNC33_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC33_OUT_SEL_S  0
+/** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC33_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_M  (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S)
+#define GPIO_FUNC33_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_OUT_INV_SEL_S  9
+/** GPIO_FUNC33_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC33_OEN_SEL    (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_M  (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S)
+#define GPIO_FUNC33_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC33_OEN_SEL_S  10
+/** GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC33_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_M  (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S)
+#define GPIO_FUNC33_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC34_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0)
+/** GPIO_FUNC34_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC34_OUT_SEL    0x000001FFU
+#define GPIO_FUNC34_OUT_SEL_M  (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S)
+#define GPIO_FUNC34_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC34_OUT_SEL_S  0
+/** GPIO_FUNC34_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC34_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_M  (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S)
+#define GPIO_FUNC34_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_OUT_INV_SEL_S  9
+/** GPIO_FUNC34_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC34_OEN_SEL    (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_M  (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S)
+#define GPIO_FUNC34_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC34_OEN_SEL_S  10
+/** GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC34_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_M  (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S)
+#define GPIO_FUNC34_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC35_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4)
+/** GPIO_FUNC35_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC35_OUT_SEL    0x000001FFU
+#define GPIO_FUNC35_OUT_SEL_M  (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S)
+#define GPIO_FUNC35_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC35_OUT_SEL_S  0
+/** GPIO_FUNC35_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC35_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_M  (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S)
+#define GPIO_FUNC35_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_OUT_INV_SEL_S  9
+/** GPIO_FUNC35_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC35_OEN_SEL    (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_M  (GPIO_FUNC35_OEN_SEL_V << GPIO_FUNC35_OEN_SEL_S)
+#define GPIO_FUNC35_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC35_OEN_SEL_S  10
+/** GPIO_FUNC35_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC35_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_M  (GPIO_FUNC35_OEN_INV_SEL_V << GPIO_FUNC35_OEN_INV_SEL_S)
+#define GPIO_FUNC35_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC36_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8)
+/** GPIO_FUNC36_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC36_OUT_SEL    0x000001FFU
+#define GPIO_FUNC36_OUT_SEL_M  (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S)
+#define GPIO_FUNC36_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC36_OUT_SEL_S  0
+/** GPIO_FUNC36_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC36_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_M  (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S)
+#define GPIO_FUNC36_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_OUT_INV_SEL_S  9
+/** GPIO_FUNC36_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC36_OEN_SEL    (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_M  (GPIO_FUNC36_OEN_SEL_V << GPIO_FUNC36_OEN_SEL_S)
+#define GPIO_FUNC36_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC36_OEN_SEL_S  10
+/** GPIO_FUNC36_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC36_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_M  (GPIO_FUNC36_OEN_INV_SEL_V << GPIO_FUNC36_OEN_INV_SEL_S)
+#define GPIO_FUNC36_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC37_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec)
+/** GPIO_FUNC37_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC37_OUT_SEL    0x000001FFU
+#define GPIO_FUNC37_OUT_SEL_M  (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S)
+#define GPIO_FUNC37_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC37_OUT_SEL_S  0
+/** GPIO_FUNC37_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC37_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_M  (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S)
+#define GPIO_FUNC37_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_OUT_INV_SEL_S  9
+/** GPIO_FUNC37_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC37_OEN_SEL    (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_M  (GPIO_FUNC37_OEN_SEL_V << GPIO_FUNC37_OEN_SEL_S)
+#define GPIO_FUNC37_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC37_OEN_SEL_S  10
+/** GPIO_FUNC37_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC37_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_M  (GPIO_FUNC37_OEN_INV_SEL_V << GPIO_FUNC37_OEN_INV_SEL_S)
+#define GPIO_FUNC37_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC38_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0)
+/** GPIO_FUNC38_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC38_OUT_SEL    0x000001FFU
+#define GPIO_FUNC38_OUT_SEL_M  (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S)
+#define GPIO_FUNC38_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC38_OUT_SEL_S  0
+/** GPIO_FUNC38_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC38_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_M  (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S)
+#define GPIO_FUNC38_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_OUT_INV_SEL_S  9
+/** GPIO_FUNC38_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC38_OEN_SEL    (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_M  (GPIO_FUNC38_OEN_SEL_V << GPIO_FUNC38_OEN_SEL_S)
+#define GPIO_FUNC38_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC38_OEN_SEL_S  10
+/** GPIO_FUNC38_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC38_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_M  (GPIO_FUNC38_OEN_INV_SEL_V << GPIO_FUNC38_OEN_INV_SEL_S)
+#define GPIO_FUNC38_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC39_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4)
+/** GPIO_FUNC39_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC39_OUT_SEL    0x000001FFU
+#define GPIO_FUNC39_OUT_SEL_M  (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S)
+#define GPIO_FUNC39_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC39_OUT_SEL_S  0
+/** GPIO_FUNC39_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC39_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_M  (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S)
+#define GPIO_FUNC39_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_OUT_INV_SEL_S  9
+/** GPIO_FUNC39_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC39_OEN_SEL    (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_M  (GPIO_FUNC39_OEN_SEL_V << GPIO_FUNC39_OEN_SEL_S)
+#define GPIO_FUNC39_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC39_OEN_SEL_S  10
+/** GPIO_FUNC39_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC39_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_M  (GPIO_FUNC39_OEN_INV_SEL_V << GPIO_FUNC39_OEN_INV_SEL_S)
+#define GPIO_FUNC39_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC40_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8)
+/** GPIO_FUNC40_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC40_OUT_SEL    0x000001FFU
+#define GPIO_FUNC40_OUT_SEL_M  (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S)
+#define GPIO_FUNC40_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC40_OUT_SEL_S  0
+/** GPIO_FUNC40_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC40_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC40_OUT_INV_SEL_M  (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S)
+#define GPIO_FUNC40_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_OUT_INV_SEL_S  9
+/** GPIO_FUNC40_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC40_OEN_SEL    (BIT(10))
+#define GPIO_FUNC40_OEN_SEL_M  (GPIO_FUNC40_OEN_SEL_V << GPIO_FUNC40_OEN_SEL_S)
+#define GPIO_FUNC40_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC40_OEN_SEL_S  10
+/** GPIO_FUNC40_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC40_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC40_OEN_INV_SEL_M  (GPIO_FUNC40_OEN_INV_SEL_V << GPIO_FUNC40_OEN_INV_SEL_S)
+#define GPIO_FUNC40_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC41_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc)
+/** GPIO_FUNC41_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC41_OUT_SEL    0x000001FFU
+#define GPIO_FUNC41_OUT_SEL_M  (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S)
+#define GPIO_FUNC41_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC41_OUT_SEL_S  0
+/** GPIO_FUNC41_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC41_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC41_OUT_INV_SEL_M  (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S)
+#define GPIO_FUNC41_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_OUT_INV_SEL_S  9
+/** GPIO_FUNC41_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC41_OEN_SEL    (BIT(10))
+#define GPIO_FUNC41_OEN_SEL_M  (GPIO_FUNC41_OEN_SEL_V << GPIO_FUNC41_OEN_SEL_S)
+#define GPIO_FUNC41_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC41_OEN_SEL_S  10
+/** GPIO_FUNC41_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC41_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC41_OEN_INV_SEL_M  (GPIO_FUNC41_OEN_INV_SEL_V << GPIO_FUNC41_OEN_INV_SEL_S)
+#define GPIO_FUNC41_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC42_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600)
+/** GPIO_FUNC42_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC42_OUT_SEL    0x000001FFU
+#define GPIO_FUNC42_OUT_SEL_M  (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S)
+#define GPIO_FUNC42_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC42_OUT_SEL_S  0
+/** GPIO_FUNC42_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC42_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC42_OUT_INV_SEL_M  (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S)
+#define GPIO_FUNC42_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_OUT_INV_SEL_S  9
+/** GPIO_FUNC42_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC42_OEN_SEL    (BIT(10))
+#define GPIO_FUNC42_OEN_SEL_M  (GPIO_FUNC42_OEN_SEL_V << GPIO_FUNC42_OEN_SEL_S)
+#define GPIO_FUNC42_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC42_OEN_SEL_S  10
+/** GPIO_FUNC42_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC42_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC42_OEN_INV_SEL_M  (GPIO_FUNC42_OEN_INV_SEL_V << GPIO_FUNC42_OEN_INV_SEL_S)
+#define GPIO_FUNC42_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC43_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604)
+/** GPIO_FUNC43_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC43_OUT_SEL    0x000001FFU
+#define GPIO_FUNC43_OUT_SEL_M  (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S)
+#define GPIO_FUNC43_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC43_OUT_SEL_S  0
+/** GPIO_FUNC43_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC43_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC43_OUT_INV_SEL_M  (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S)
+#define GPIO_FUNC43_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_OUT_INV_SEL_S  9
+/** GPIO_FUNC43_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC43_OEN_SEL    (BIT(10))
+#define GPIO_FUNC43_OEN_SEL_M  (GPIO_FUNC43_OEN_SEL_V << GPIO_FUNC43_OEN_SEL_S)
+#define GPIO_FUNC43_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC43_OEN_SEL_S  10
+/** GPIO_FUNC43_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC43_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC43_OEN_INV_SEL_M  (GPIO_FUNC43_OEN_INV_SEL_V << GPIO_FUNC43_OEN_INV_SEL_S)
+#define GPIO_FUNC43_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC44_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x608)
+/** GPIO_FUNC44_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC44_OUT_SEL    0x000001FFU
+#define GPIO_FUNC44_OUT_SEL_M  (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S)
+#define GPIO_FUNC44_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC44_OUT_SEL_S  0
+/** GPIO_FUNC44_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC44_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC44_OUT_INV_SEL_M  (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S)
+#define GPIO_FUNC44_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_OUT_INV_SEL_S  9
+/** GPIO_FUNC44_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC44_OEN_SEL    (BIT(10))
+#define GPIO_FUNC44_OEN_SEL_M  (GPIO_FUNC44_OEN_SEL_V << GPIO_FUNC44_OEN_SEL_S)
+#define GPIO_FUNC44_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC44_OEN_SEL_S  10
+/** GPIO_FUNC44_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC44_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC44_OEN_INV_SEL_M  (GPIO_FUNC44_OEN_INV_SEL_V << GPIO_FUNC44_OEN_INV_SEL_S)
+#define GPIO_FUNC44_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC45_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC45_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x60c)
+/** GPIO_FUNC45_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC45_OUT_SEL    0x000001FFU
+#define GPIO_FUNC45_OUT_SEL_M  (GPIO_FUNC45_OUT_SEL_V << GPIO_FUNC45_OUT_SEL_S)
+#define GPIO_FUNC45_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC45_OUT_SEL_S  0
+/** GPIO_FUNC45_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC45_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC45_OUT_INV_SEL_M  (GPIO_FUNC45_OUT_INV_SEL_V << GPIO_FUNC45_OUT_INV_SEL_S)
+#define GPIO_FUNC45_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_OUT_INV_SEL_S  9
+/** GPIO_FUNC45_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC45_OEN_SEL    (BIT(10))
+#define GPIO_FUNC45_OEN_SEL_M  (GPIO_FUNC45_OEN_SEL_V << GPIO_FUNC45_OEN_SEL_S)
+#define GPIO_FUNC45_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC45_OEN_SEL_S  10
+/** GPIO_FUNC45_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC45_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC45_OEN_INV_SEL_M  (GPIO_FUNC45_OEN_INV_SEL_V << GPIO_FUNC45_OEN_INV_SEL_S)
+#define GPIO_FUNC45_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC46_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC46_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x610)
+/** GPIO_FUNC46_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC46_OUT_SEL    0x000001FFU
+#define GPIO_FUNC46_OUT_SEL_M  (GPIO_FUNC46_OUT_SEL_V << GPIO_FUNC46_OUT_SEL_S)
+#define GPIO_FUNC46_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC46_OUT_SEL_S  0
+/** GPIO_FUNC46_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC46_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC46_OUT_INV_SEL_M  (GPIO_FUNC46_OUT_INV_SEL_V << GPIO_FUNC46_OUT_INV_SEL_S)
+#define GPIO_FUNC46_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_OUT_INV_SEL_S  9
+/** GPIO_FUNC46_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC46_OEN_SEL    (BIT(10))
+#define GPIO_FUNC46_OEN_SEL_M  (GPIO_FUNC46_OEN_SEL_V << GPIO_FUNC46_OEN_SEL_S)
+#define GPIO_FUNC46_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC46_OEN_SEL_S  10
+/** GPIO_FUNC46_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC46_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC46_OEN_INV_SEL_M  (GPIO_FUNC46_OEN_INV_SEL_V << GPIO_FUNC46_OEN_INV_SEL_S)
+#define GPIO_FUNC46_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC47_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC47_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x614)
+/** GPIO_FUNC47_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC47_OUT_SEL    0x000001FFU
+#define GPIO_FUNC47_OUT_SEL_M  (GPIO_FUNC47_OUT_SEL_V << GPIO_FUNC47_OUT_SEL_S)
+#define GPIO_FUNC47_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC47_OUT_SEL_S  0
+/** GPIO_FUNC47_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC47_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC47_OUT_INV_SEL_M  (GPIO_FUNC47_OUT_INV_SEL_V << GPIO_FUNC47_OUT_INV_SEL_S)
+#define GPIO_FUNC47_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_OUT_INV_SEL_S  9
+/** GPIO_FUNC47_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC47_OEN_SEL    (BIT(10))
+#define GPIO_FUNC47_OEN_SEL_M  (GPIO_FUNC47_OEN_SEL_V << GPIO_FUNC47_OEN_SEL_S)
+#define GPIO_FUNC47_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC47_OEN_SEL_S  10
+/** GPIO_FUNC47_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC47_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC47_OEN_INV_SEL_M  (GPIO_FUNC47_OEN_INV_SEL_V << GPIO_FUNC47_OEN_INV_SEL_S)
+#define GPIO_FUNC47_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC48_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC48_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x618)
+/** GPIO_FUNC48_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC48_OUT_SEL    0x000001FFU
+#define GPIO_FUNC48_OUT_SEL_M  (GPIO_FUNC48_OUT_SEL_V << GPIO_FUNC48_OUT_SEL_S)
+#define GPIO_FUNC48_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC48_OUT_SEL_S  0
+/** GPIO_FUNC48_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC48_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC48_OUT_INV_SEL_M  (GPIO_FUNC48_OUT_INV_SEL_V << GPIO_FUNC48_OUT_INV_SEL_S)
+#define GPIO_FUNC48_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_OUT_INV_SEL_S  9
+/** GPIO_FUNC48_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC48_OEN_SEL    (BIT(10))
+#define GPIO_FUNC48_OEN_SEL_M  (GPIO_FUNC48_OEN_SEL_V << GPIO_FUNC48_OEN_SEL_S)
+#define GPIO_FUNC48_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC48_OEN_SEL_S  10
+/** GPIO_FUNC48_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC48_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC48_OEN_INV_SEL_M  (GPIO_FUNC48_OEN_INV_SEL_V << GPIO_FUNC48_OEN_INV_SEL_S)
+#define GPIO_FUNC48_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC49_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC49_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x61c)
+/** GPIO_FUNC49_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC49_OUT_SEL    0x000001FFU
+#define GPIO_FUNC49_OUT_SEL_M  (GPIO_FUNC49_OUT_SEL_V << GPIO_FUNC49_OUT_SEL_S)
+#define GPIO_FUNC49_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC49_OUT_SEL_S  0
+/** GPIO_FUNC49_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC49_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC49_OUT_INV_SEL_M  (GPIO_FUNC49_OUT_INV_SEL_V << GPIO_FUNC49_OUT_INV_SEL_S)
+#define GPIO_FUNC49_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_OUT_INV_SEL_S  9
+/** GPIO_FUNC49_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC49_OEN_SEL    (BIT(10))
+#define GPIO_FUNC49_OEN_SEL_M  (GPIO_FUNC49_OEN_SEL_V << GPIO_FUNC49_OEN_SEL_S)
+#define GPIO_FUNC49_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC49_OEN_SEL_S  10
+/** GPIO_FUNC49_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC49_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC49_OEN_INV_SEL_M  (GPIO_FUNC49_OEN_INV_SEL_V << GPIO_FUNC49_OEN_INV_SEL_S)
+#define GPIO_FUNC49_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC50_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC50_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x620)
+/** GPIO_FUNC50_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC50_OUT_SEL    0x000001FFU
+#define GPIO_FUNC50_OUT_SEL_M  (GPIO_FUNC50_OUT_SEL_V << GPIO_FUNC50_OUT_SEL_S)
+#define GPIO_FUNC50_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC50_OUT_SEL_S  0
+/** GPIO_FUNC50_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC50_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC50_OUT_INV_SEL_M  (GPIO_FUNC50_OUT_INV_SEL_V << GPIO_FUNC50_OUT_INV_SEL_S)
+#define GPIO_FUNC50_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_OUT_INV_SEL_S  9
+/** GPIO_FUNC50_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC50_OEN_SEL    (BIT(10))
+#define GPIO_FUNC50_OEN_SEL_M  (GPIO_FUNC50_OEN_SEL_V << GPIO_FUNC50_OEN_SEL_S)
+#define GPIO_FUNC50_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC50_OEN_SEL_S  10
+/** GPIO_FUNC50_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC50_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC50_OEN_INV_SEL_M  (GPIO_FUNC50_OEN_INV_SEL_V << GPIO_FUNC50_OEN_INV_SEL_S)
+#define GPIO_FUNC50_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC51_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC51_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x624)
+/** GPIO_FUNC51_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC51_OUT_SEL    0x000001FFU
+#define GPIO_FUNC51_OUT_SEL_M  (GPIO_FUNC51_OUT_SEL_V << GPIO_FUNC51_OUT_SEL_S)
+#define GPIO_FUNC51_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC51_OUT_SEL_S  0
+/** GPIO_FUNC51_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC51_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC51_OUT_INV_SEL_M  (GPIO_FUNC51_OUT_INV_SEL_V << GPIO_FUNC51_OUT_INV_SEL_S)
+#define GPIO_FUNC51_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_OUT_INV_SEL_S  9
+/** GPIO_FUNC51_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC51_OEN_SEL    (BIT(10))
+#define GPIO_FUNC51_OEN_SEL_M  (GPIO_FUNC51_OEN_SEL_V << GPIO_FUNC51_OEN_SEL_S)
+#define GPIO_FUNC51_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC51_OEN_SEL_S  10
+/** GPIO_FUNC51_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC51_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC51_OEN_INV_SEL_M  (GPIO_FUNC51_OEN_INV_SEL_V << GPIO_FUNC51_OEN_INV_SEL_S)
+#define GPIO_FUNC51_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC52_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC52_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x628)
+/** GPIO_FUNC52_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC52_OUT_SEL    0x000001FFU
+#define GPIO_FUNC52_OUT_SEL_M  (GPIO_FUNC52_OUT_SEL_V << GPIO_FUNC52_OUT_SEL_S)
+#define GPIO_FUNC52_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC52_OUT_SEL_S  0
+/** GPIO_FUNC52_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC52_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC52_OUT_INV_SEL_M  (GPIO_FUNC52_OUT_INV_SEL_V << GPIO_FUNC52_OUT_INV_SEL_S)
+#define GPIO_FUNC52_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_OUT_INV_SEL_S  9
+/** GPIO_FUNC52_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC52_OEN_SEL    (BIT(10))
+#define GPIO_FUNC52_OEN_SEL_M  (GPIO_FUNC52_OEN_SEL_V << GPIO_FUNC52_OEN_SEL_S)
+#define GPIO_FUNC52_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC52_OEN_SEL_S  10
+/** GPIO_FUNC52_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC52_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC52_OEN_INV_SEL_M  (GPIO_FUNC52_OEN_INV_SEL_V << GPIO_FUNC52_OEN_INV_SEL_S)
+#define GPIO_FUNC52_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC53_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC53_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x62c)
+/** GPIO_FUNC53_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC53_OUT_SEL    0x000001FFU
+#define GPIO_FUNC53_OUT_SEL_M  (GPIO_FUNC53_OUT_SEL_V << GPIO_FUNC53_OUT_SEL_S)
+#define GPIO_FUNC53_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC53_OUT_SEL_S  0
+/** GPIO_FUNC53_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC53_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC53_OUT_INV_SEL_M  (GPIO_FUNC53_OUT_INV_SEL_V << GPIO_FUNC53_OUT_INV_SEL_S)
+#define GPIO_FUNC53_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_OUT_INV_SEL_S  9
+/** GPIO_FUNC53_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC53_OEN_SEL    (BIT(10))
+#define GPIO_FUNC53_OEN_SEL_M  (GPIO_FUNC53_OEN_SEL_V << GPIO_FUNC53_OEN_SEL_S)
+#define GPIO_FUNC53_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC53_OEN_SEL_S  10
+/** GPIO_FUNC53_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC53_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC53_OEN_INV_SEL_M  (GPIO_FUNC53_OEN_INV_SEL_V << GPIO_FUNC53_OEN_INV_SEL_S)
+#define GPIO_FUNC53_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC54_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC54_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x630)
+/** GPIO_FUNC54_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC54_OUT_SEL    0x000001FFU
+#define GPIO_FUNC54_OUT_SEL_M  (GPIO_FUNC54_OUT_SEL_V << GPIO_FUNC54_OUT_SEL_S)
+#define GPIO_FUNC54_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC54_OUT_SEL_S  0
+/** GPIO_FUNC54_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC54_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC54_OUT_INV_SEL_M  (GPIO_FUNC54_OUT_INV_SEL_V << GPIO_FUNC54_OUT_INV_SEL_S)
+#define GPIO_FUNC54_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_OUT_INV_SEL_S  9
+/** GPIO_FUNC54_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC54_OEN_SEL    (BIT(10))
+#define GPIO_FUNC54_OEN_SEL_M  (GPIO_FUNC54_OEN_SEL_V << GPIO_FUNC54_OEN_SEL_S)
+#define GPIO_FUNC54_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC54_OEN_SEL_S  10
+/** GPIO_FUNC54_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC54_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC54_OEN_INV_SEL_M  (GPIO_FUNC54_OEN_INV_SEL_V << GPIO_FUNC54_OEN_INV_SEL_S)
+#define GPIO_FUNC54_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC55_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC55_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x634)
+/** GPIO_FUNC55_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC55_OUT_SEL    0x000001FFU
+#define GPIO_FUNC55_OUT_SEL_M  (GPIO_FUNC55_OUT_SEL_V << GPIO_FUNC55_OUT_SEL_S)
+#define GPIO_FUNC55_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC55_OUT_SEL_S  0
+/** GPIO_FUNC55_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC55_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC55_OUT_INV_SEL_M  (GPIO_FUNC55_OUT_INV_SEL_V << GPIO_FUNC55_OUT_INV_SEL_S)
+#define GPIO_FUNC55_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_OUT_INV_SEL_S  9
+/** GPIO_FUNC55_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC55_OEN_SEL    (BIT(10))
+#define GPIO_FUNC55_OEN_SEL_M  (GPIO_FUNC55_OEN_SEL_V << GPIO_FUNC55_OEN_SEL_S)
+#define GPIO_FUNC55_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC55_OEN_SEL_S  10
+/** GPIO_FUNC55_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC55_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC55_OEN_INV_SEL_M  (GPIO_FUNC55_OEN_INV_SEL_V << GPIO_FUNC55_OEN_INV_SEL_S)
+#define GPIO_FUNC55_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_OEN_INV_SEL_S  11
+
+/** GPIO_FUNC56_OUT_SEL_CFG_REG register
+ *  GPIO output function select register
+ */
+#define GPIO_FUNC56_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x638)
+/** GPIO_FUNC56_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+ *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+ *  GPIO_OUT_REG[n].
+ */
+#define GPIO_FUNC56_OUT_SEL    0x000001FFU
+#define GPIO_FUNC56_OUT_SEL_M  (GPIO_FUNC56_OUT_SEL_V << GPIO_FUNC56_OUT_SEL_S)
+#define GPIO_FUNC56_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC56_OUT_SEL_S  0
+/** GPIO_FUNC56_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  set this bit to invert output signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC56_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC56_OUT_INV_SEL_M  (GPIO_FUNC56_OUT_INV_SEL_V << GPIO_FUNC56_OUT_INV_SEL_S)
+#define GPIO_FUNC56_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_OUT_INV_SEL_S  9
+/** GPIO_FUNC56_OEN_SEL : R/W; bitpos: [10]; default: 0;
+ *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+ *  enable signal.0:use peripheral output enable signal.
+ */
+#define GPIO_FUNC56_OEN_SEL    (BIT(10))
+#define GPIO_FUNC56_OEN_SEL_M  (GPIO_FUNC56_OEN_SEL_V << GPIO_FUNC56_OEN_SEL_S)
+#define GPIO_FUNC56_OEN_SEL_V  0x00000001U
+#define GPIO_FUNC56_OEN_SEL_S  10
+/** GPIO_FUNC56_OEN_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  set this bit to invert output enable signal.1:invert.0:not invert.
+ */
+#define GPIO_FUNC56_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC56_OEN_INV_SEL_M  (GPIO_FUNC56_OEN_INV_SEL_V << GPIO_FUNC56_OEN_INV_SEL_S)
+#define GPIO_FUNC56_OEN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_OEN_INV_SEL_S  11
+
+/** GPIO_INTR_2_REG register
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+#define GPIO_INTR_2_REG (DR_REG_GPIO_BASE + 0x63c)
+/** GPIO_INT_2 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+#define GPIO_INT_2    0xFFFFFFFFU
+#define GPIO_INT_2_M  (GPIO_INT_2_V << GPIO_INT_2_S)
+#define GPIO_INT_2_V  0xFFFFFFFFU
+#define GPIO_INT_2_S  0
+
+/** GPIO_INTR1_2_REG register
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+#define GPIO_INTR1_2_REG (DR_REG_GPIO_BASE + 0x640)
+/** GPIO_INT1_2 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+#define GPIO_INT1_2    0x01FFFFFFU
+#define GPIO_INT1_2_M  (GPIO_INT1_2_V << GPIO_INT1_2_S)
+#define GPIO_INT1_2_V  0x01FFFFFFU
+#define GPIO_INT1_2_S  0
+
+/** GPIO_INTR_3_REG register
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+#define GPIO_INTR_3_REG (DR_REG_GPIO_BASE + 0x644)
+/** GPIO_INT_3 : RO; bitpos: [31:0]; default: 0;
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+#define GPIO_INT_3    0xFFFFFFFFU
+#define GPIO_INT_3_M  (GPIO_INT_3_V << GPIO_INT_3_S)
+#define GPIO_INT_3_V  0xFFFFFFFFU
+#define GPIO_INT_3_S  0
+
+/** GPIO_INTR1_3_REG register
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+#define GPIO_INTR1_3_REG (DR_REG_GPIO_BASE + 0x648)
+/** GPIO_INT1_3 : RO; bitpos: [24:0]; default: 0;
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+#define GPIO_INT1_3    0x01FFFFFFU
+#define GPIO_INT1_3_M  (GPIO_INT1_3_V << GPIO_INT1_3_S)
+#define GPIO_INT1_3_V  0x01FFFFFFU
+#define GPIO_INT1_3_S  0
+
+/** GPIO_CLOCK_GATE_REG register
+ *  GPIO clock gate register
+ */
+#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x64c)
+/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  set this bit to enable GPIO clock gate
+ */
+#define GPIO_CLK_EN    (BIT(0))
+#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
+#define GPIO_CLK_EN_V  0x00000001U
+#define GPIO_CLK_EN_S  0
+
+/** GPIO_INT_RAW_REG register
+ *  analog comparator interrupt raw
+ */
+#define GPIO_INT_RAW_REG (DR_REG_GPIO_BASE + 0x700)
+/** GPIO_COMP0_NEG_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt raw
+ */
+#define GPIO_COMP0_NEG_INT_RAW    (BIT(0))
+#define GPIO_COMP0_NEG_INT_RAW_M  (GPIO_COMP0_NEG_INT_RAW_V << GPIO_COMP0_NEG_INT_RAW_S)
+#define GPIO_COMP0_NEG_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_RAW_S  0
+/** GPIO_COMP0_POS_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt raw
+ */
+#define GPIO_COMP0_POS_INT_RAW    (BIT(1))
+#define GPIO_COMP0_POS_INT_RAW_M  (GPIO_COMP0_POS_INT_RAW_V << GPIO_COMP0_POS_INT_RAW_S)
+#define GPIO_COMP0_POS_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_POS_INT_RAW_S  1
+/** GPIO_COMP0_ALL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt raw
+ */
+#define GPIO_COMP0_ALL_INT_RAW    (BIT(2))
+#define GPIO_COMP0_ALL_INT_RAW_M  (GPIO_COMP0_ALL_INT_RAW_V << GPIO_COMP0_ALL_INT_RAW_S)
+#define GPIO_COMP0_ALL_INT_RAW_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_RAW_S  2
+/** GPIO_COMP1_NEG_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt raw
+ */
+#define GPIO_COMP1_NEG_INT_RAW    (BIT(3))
+#define GPIO_COMP1_NEG_INT_RAW_M  (GPIO_COMP1_NEG_INT_RAW_V << GPIO_COMP1_NEG_INT_RAW_S)
+#define GPIO_COMP1_NEG_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_RAW_S  3
+/** GPIO_COMP1_POS_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt raw
+ */
+#define GPIO_COMP1_POS_INT_RAW    (BIT(4))
+#define GPIO_COMP1_POS_INT_RAW_M  (GPIO_COMP1_POS_INT_RAW_V << GPIO_COMP1_POS_INT_RAW_S)
+#define GPIO_COMP1_POS_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_POS_INT_RAW_S  4
+/** GPIO_COMP1_ALL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt raw
+ */
+#define GPIO_COMP1_ALL_INT_RAW    (BIT(5))
+#define GPIO_COMP1_ALL_INT_RAW_M  (GPIO_COMP1_ALL_INT_RAW_V << GPIO_COMP1_ALL_INT_RAW_S)
+#define GPIO_COMP1_ALL_INT_RAW_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_RAW_S  5
+/** GPIO_BISTOK_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  pad bistok interrupt raw
+ */
+#define GPIO_BISTOK_INT_RAW    (BIT(6))
+#define GPIO_BISTOK_INT_RAW_M  (GPIO_BISTOK_INT_RAW_V << GPIO_BISTOK_INT_RAW_S)
+#define GPIO_BISTOK_INT_RAW_V  0x00000001U
+#define GPIO_BISTOK_INT_RAW_S  6
+/** GPIO_BISTFAIL_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt raw
+ */
+#define GPIO_BISTFAIL_INT_RAW    (BIT(7))
+#define GPIO_BISTFAIL_INT_RAW_M  (GPIO_BISTFAIL_INT_RAW_V << GPIO_BISTFAIL_INT_RAW_S)
+#define GPIO_BISTFAIL_INT_RAW_V  0x00000001U
+#define GPIO_BISTFAIL_INT_RAW_S  7
+
+/** GPIO_INT_ST_REG register
+ *  analog comparator interrupt status
+ */
+#define GPIO_INT_ST_REG (DR_REG_GPIO_BASE + 0x704)
+/** GPIO_COMP0_NEG_INT_ST : RO; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt status
+ */
+#define GPIO_COMP0_NEG_INT_ST    (BIT(0))
+#define GPIO_COMP0_NEG_INT_ST_M  (GPIO_COMP0_NEG_INT_ST_V << GPIO_COMP0_NEG_INT_ST_S)
+#define GPIO_COMP0_NEG_INT_ST_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_ST_S  0
+/** GPIO_COMP0_POS_INT_ST : RO; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt status
+ */
+#define GPIO_COMP0_POS_INT_ST    (BIT(1))
+#define GPIO_COMP0_POS_INT_ST_M  (GPIO_COMP0_POS_INT_ST_V << GPIO_COMP0_POS_INT_ST_S)
+#define GPIO_COMP0_POS_INT_ST_V  0x00000001U
+#define GPIO_COMP0_POS_INT_ST_S  1
+/** GPIO_COMP0_ALL_INT_ST : RO; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt status
+ */
+#define GPIO_COMP0_ALL_INT_ST    (BIT(2))
+#define GPIO_COMP0_ALL_INT_ST_M  (GPIO_COMP0_ALL_INT_ST_V << GPIO_COMP0_ALL_INT_ST_S)
+#define GPIO_COMP0_ALL_INT_ST_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_ST_S  2
+/** GPIO_COMP1_NEG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt status
+ */
+#define GPIO_COMP1_NEG_INT_ST    (BIT(3))
+#define GPIO_COMP1_NEG_INT_ST_M  (GPIO_COMP1_NEG_INT_ST_V << GPIO_COMP1_NEG_INT_ST_S)
+#define GPIO_COMP1_NEG_INT_ST_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_ST_S  3
+/** GPIO_COMP1_POS_INT_ST : RO; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt status
+ */
+#define GPIO_COMP1_POS_INT_ST    (BIT(4))
+#define GPIO_COMP1_POS_INT_ST_M  (GPIO_COMP1_POS_INT_ST_V << GPIO_COMP1_POS_INT_ST_S)
+#define GPIO_COMP1_POS_INT_ST_V  0x00000001U
+#define GPIO_COMP1_POS_INT_ST_S  4
+/** GPIO_COMP1_ALL_INT_ST : RO; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt status
+ */
+#define GPIO_COMP1_ALL_INT_ST    (BIT(5))
+#define GPIO_COMP1_ALL_INT_ST_M  (GPIO_COMP1_ALL_INT_ST_V << GPIO_COMP1_ALL_INT_ST_S)
+#define GPIO_COMP1_ALL_INT_ST_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_ST_S  5
+/** GPIO_BISTOK_INT_ST : RO; bitpos: [6]; default: 0;
+ *  pad bistok interrupt status
+ */
+#define GPIO_BISTOK_INT_ST    (BIT(6))
+#define GPIO_BISTOK_INT_ST_M  (GPIO_BISTOK_INT_ST_V << GPIO_BISTOK_INT_ST_S)
+#define GPIO_BISTOK_INT_ST_V  0x00000001U
+#define GPIO_BISTOK_INT_ST_S  6
+/** GPIO_BISTFAIL_INT_ST : RO; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt status
+ */
+#define GPIO_BISTFAIL_INT_ST    (BIT(7))
+#define GPIO_BISTFAIL_INT_ST_M  (GPIO_BISTFAIL_INT_ST_V << GPIO_BISTFAIL_INT_ST_S)
+#define GPIO_BISTFAIL_INT_ST_V  0x00000001U
+#define GPIO_BISTFAIL_INT_ST_S  7
+
+/** GPIO_INT_ENA_REG register
+ *  analog comparator interrupt enable
+ */
+#define GPIO_INT_ENA_REG (DR_REG_GPIO_BASE + 0x708)
+/** GPIO_COMP0_NEG_INT_ENA : R/W; bitpos: [0]; default: 1;
+ *  analog comparator pos edge interrupt enable
+ */
+#define GPIO_COMP0_NEG_INT_ENA    (BIT(0))
+#define GPIO_COMP0_NEG_INT_ENA_M  (GPIO_COMP0_NEG_INT_ENA_V << GPIO_COMP0_NEG_INT_ENA_S)
+#define GPIO_COMP0_NEG_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_ENA_S  0
+/** GPIO_COMP0_POS_INT_ENA : R/W; bitpos: [1]; default: 1;
+ *  analog comparator neg edge interrupt enable
+ */
+#define GPIO_COMP0_POS_INT_ENA    (BIT(1))
+#define GPIO_COMP0_POS_INT_ENA_M  (GPIO_COMP0_POS_INT_ENA_V << GPIO_COMP0_POS_INT_ENA_S)
+#define GPIO_COMP0_POS_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_POS_INT_ENA_S  1
+/** GPIO_COMP0_ALL_INT_ENA : R/W; bitpos: [2]; default: 1;
+ *  analog comparator neg or pos edge interrupt enable
+ */
+#define GPIO_COMP0_ALL_INT_ENA    (BIT(2))
+#define GPIO_COMP0_ALL_INT_ENA_M  (GPIO_COMP0_ALL_INT_ENA_V << GPIO_COMP0_ALL_INT_ENA_S)
+#define GPIO_COMP0_ALL_INT_ENA_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_ENA_S  2
+/** GPIO_COMP1_NEG_INT_ENA : R/W; bitpos: [3]; default: 1;
+ *  analog comparator pos edge interrupt enable
+ */
+#define GPIO_COMP1_NEG_INT_ENA    (BIT(3))
+#define GPIO_COMP1_NEG_INT_ENA_M  (GPIO_COMP1_NEG_INT_ENA_V << GPIO_COMP1_NEG_INT_ENA_S)
+#define GPIO_COMP1_NEG_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_ENA_S  3
+/** GPIO_COMP1_POS_INT_ENA : R/W; bitpos: [4]; default: 1;
+ *  analog comparator neg edge interrupt enable
+ */
+#define GPIO_COMP1_POS_INT_ENA    (BIT(4))
+#define GPIO_COMP1_POS_INT_ENA_M  (GPIO_COMP1_POS_INT_ENA_V << GPIO_COMP1_POS_INT_ENA_S)
+#define GPIO_COMP1_POS_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_POS_INT_ENA_S  4
+/** GPIO_COMP1_ALL_INT_ENA : R/W; bitpos: [5]; default: 1;
+ *  analog comparator neg or pos edge interrupt enable
+ */
+#define GPIO_COMP1_ALL_INT_ENA    (BIT(5))
+#define GPIO_COMP1_ALL_INT_ENA_M  (GPIO_COMP1_ALL_INT_ENA_V << GPIO_COMP1_ALL_INT_ENA_S)
+#define GPIO_COMP1_ALL_INT_ENA_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_ENA_S  5
+/** GPIO_BISTOK_INT_ENA : R/W; bitpos: [6]; default: 1;
+ *  pad bistok interrupt enable
+ */
+#define GPIO_BISTOK_INT_ENA    (BIT(6))
+#define GPIO_BISTOK_INT_ENA_M  (GPIO_BISTOK_INT_ENA_V << GPIO_BISTOK_INT_ENA_S)
+#define GPIO_BISTOK_INT_ENA_V  0x00000001U
+#define GPIO_BISTOK_INT_ENA_S  6
+/** GPIO_BISTFAIL_INT_ENA : R/W; bitpos: [7]; default: 1;
+ *  pad bistfail interrupt enable
+ */
+#define GPIO_BISTFAIL_INT_ENA    (BIT(7))
+#define GPIO_BISTFAIL_INT_ENA_M  (GPIO_BISTFAIL_INT_ENA_V << GPIO_BISTFAIL_INT_ENA_S)
+#define GPIO_BISTFAIL_INT_ENA_V  0x00000001U
+#define GPIO_BISTFAIL_INT_ENA_S  7
+
+/** GPIO_INT_CLR_REG register
+ *  analog comparator interrupt clear
+ */
+#define GPIO_INT_CLR_REG (DR_REG_GPIO_BASE + 0x70c)
+/** GPIO_COMP0_NEG_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  analog comparator pos edge interrupt clear
+ */
+#define GPIO_COMP0_NEG_INT_CLR    (BIT(0))
+#define GPIO_COMP0_NEG_INT_CLR_M  (GPIO_COMP0_NEG_INT_CLR_V << GPIO_COMP0_NEG_INT_CLR_S)
+#define GPIO_COMP0_NEG_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_NEG_INT_CLR_S  0
+/** GPIO_COMP0_POS_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  analog comparator neg edge interrupt clear
+ */
+#define GPIO_COMP0_POS_INT_CLR    (BIT(1))
+#define GPIO_COMP0_POS_INT_CLR_M  (GPIO_COMP0_POS_INT_CLR_V << GPIO_COMP0_POS_INT_CLR_S)
+#define GPIO_COMP0_POS_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_POS_INT_CLR_S  1
+/** GPIO_COMP0_ALL_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  analog comparator neg or pos edge interrupt clear
+ */
+#define GPIO_COMP0_ALL_INT_CLR    (BIT(2))
+#define GPIO_COMP0_ALL_INT_CLR_M  (GPIO_COMP0_ALL_INT_CLR_V << GPIO_COMP0_ALL_INT_CLR_S)
+#define GPIO_COMP0_ALL_INT_CLR_V  0x00000001U
+#define GPIO_COMP0_ALL_INT_CLR_S  2
+/** GPIO_COMP1_NEG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  analog comparator pos edge interrupt clear
+ */
+#define GPIO_COMP1_NEG_INT_CLR    (BIT(3))
+#define GPIO_COMP1_NEG_INT_CLR_M  (GPIO_COMP1_NEG_INT_CLR_V << GPIO_COMP1_NEG_INT_CLR_S)
+#define GPIO_COMP1_NEG_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_NEG_INT_CLR_S  3
+/** GPIO_COMP1_POS_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  analog comparator neg edge interrupt clear
+ */
+#define GPIO_COMP1_POS_INT_CLR    (BIT(4))
+#define GPIO_COMP1_POS_INT_CLR_M  (GPIO_COMP1_POS_INT_CLR_V << GPIO_COMP1_POS_INT_CLR_S)
+#define GPIO_COMP1_POS_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_POS_INT_CLR_S  4
+/** GPIO_COMP1_ALL_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  analog comparator neg or pos edge interrupt clear
+ */
+#define GPIO_COMP1_ALL_INT_CLR    (BIT(5))
+#define GPIO_COMP1_ALL_INT_CLR_M  (GPIO_COMP1_ALL_INT_CLR_V << GPIO_COMP1_ALL_INT_CLR_S)
+#define GPIO_COMP1_ALL_INT_CLR_V  0x00000001U
+#define GPIO_COMP1_ALL_INT_CLR_S  5
+/** GPIO_BISTOK_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  pad bistok interrupt enable
+ */
+#define GPIO_BISTOK_INT_CLR    (BIT(6))
+#define GPIO_BISTOK_INT_CLR_M  (GPIO_BISTOK_INT_CLR_V << GPIO_BISTOK_INT_CLR_S)
+#define GPIO_BISTOK_INT_CLR_V  0x00000001U
+#define GPIO_BISTOK_INT_CLR_S  6
+/** GPIO_BISTFAIL_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  pad bistfail interrupt enable
+ */
+#define GPIO_BISTFAIL_INT_CLR    (BIT(7))
+#define GPIO_BISTFAIL_INT_CLR_M  (GPIO_BISTFAIL_INT_CLR_V << GPIO_BISTFAIL_INT_CLR_S)
+#define GPIO_BISTFAIL_INT_CLR_V  0x00000001U
+#define GPIO_BISTFAIL_INT_CLR_S  7
+
+/** GPIO_ZERO_DET0_FILTER_CNT_REG register
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET0_FILTER_CNT_REG (DR_REG_GPIO_BASE + 0x710)
+/** GPIO_ZERO_DET0_FILTER_CNT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET0_FILTER_CNT    0xFFFFFFFFU
+#define GPIO_ZERO_DET0_FILTER_CNT_M  (GPIO_ZERO_DET0_FILTER_CNT_V << GPIO_ZERO_DET0_FILTER_CNT_S)
+#define GPIO_ZERO_DET0_FILTER_CNT_V  0xFFFFFFFFU
+#define GPIO_ZERO_DET0_FILTER_CNT_S  0
+
+/** GPIO_ZERO_DET1_FILTER_CNT_REG register
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET1_FILTER_CNT_REG (DR_REG_GPIO_BASE + 0x714)
+/** GPIO_ZERO_DET1_FILTER_CNT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  GPIO analog comparator zero detect filter count
+ */
+#define GPIO_ZERO_DET1_FILTER_CNT    0xFFFFFFFFU
+#define GPIO_ZERO_DET1_FILTER_CNT_M  (GPIO_ZERO_DET1_FILTER_CNT_V << GPIO_ZERO_DET1_FILTER_CNT_S)
+#define GPIO_ZERO_DET1_FILTER_CNT_V  0xFFFFFFFFU
+#define GPIO_ZERO_DET1_FILTER_CNT_S  0
+
+/** GPIO_SEND_SEQ_REG register
+ *  High speed sdio pad bist send sequence
+ */
+#define GPIO_SEND_SEQ_REG (DR_REG_GPIO_BASE + 0x718)
+/** GPIO_SEND_SEQ : R/W; bitpos: [31:0]; default: 305419896;
+ *  High speed sdio pad bist send sequence
+ */
+#define GPIO_SEND_SEQ    0xFFFFFFFFU
+#define GPIO_SEND_SEQ_M  (GPIO_SEND_SEQ_V << GPIO_SEND_SEQ_S)
+#define GPIO_SEND_SEQ_V  0xFFFFFFFFU
+#define GPIO_SEND_SEQ_S  0
+
+/** GPIO_RECIVE_SEQ_REG register
+ *  High speed sdio pad bist receive sequence
+ */
+#define GPIO_RECIVE_SEQ_REG (DR_REG_GPIO_BASE + 0x71c)
+/** GPIO_RECIVE_SEQ : RO; bitpos: [31:0]; default: 0;
+ *  High speed sdio pad bist receive sequence
+ */
+#define GPIO_RECIVE_SEQ    0xFFFFFFFFU
+#define GPIO_RECIVE_SEQ_M  (GPIO_RECIVE_SEQ_V << GPIO_RECIVE_SEQ_S)
+#define GPIO_RECIVE_SEQ_V  0xFFFFFFFFU
+#define GPIO_RECIVE_SEQ_S  0
+
+/** GPIO_BISTIN_SEL_REG register
+ *  High speed sdio pad bist in pad sel
+ */
+#define GPIO_BISTIN_SEL_REG (DR_REG_GPIO_BASE + 0x720)
+/** GPIO_BISTIN_SEL : R/W; bitpos: [3:0]; default: 15;
+ *  High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
+ */
+#define GPIO_BISTIN_SEL    0x0000000FU
+#define GPIO_BISTIN_SEL_M  (GPIO_BISTIN_SEL_V << GPIO_BISTIN_SEL_S)
+#define GPIO_BISTIN_SEL_V  0x0000000FU
+#define GPIO_BISTIN_SEL_S  0
+
+/** GPIO_BIST_CTRL_REG register
+ *  High speed sdio pad bist control
+ */
+#define GPIO_BIST_CTRL_REG (DR_REG_GPIO_BASE + 0x724)
+/** GPIO_BIST_PAD_OE : R/W; bitpos: [0]; default: 1;
+ *  High speed sdio pad bist out pad oe
+ */
+#define GPIO_BIST_PAD_OE    (BIT(0))
+#define GPIO_BIST_PAD_OE_M  (GPIO_BIST_PAD_OE_V << GPIO_BIST_PAD_OE_S)
+#define GPIO_BIST_PAD_OE_V  0x00000001U
+#define GPIO_BIST_PAD_OE_S  0
+/** GPIO_BIST_START : WT; bitpos: [1]; default: 0;
+ *  High speed sdio pad bist start
+ */
+#define GPIO_BIST_START    (BIT(1))
+#define GPIO_BIST_START_M  (GPIO_BIST_START_V << GPIO_BIST_START_S)
+#define GPIO_BIST_START_V  0x00000001U
+#define GPIO_BIST_START_S  1
+
+/** GPIO_DATE_REG register
+ *  GPIO version register
+ */
+#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x7fc)
+/** GPIO_DATE : R/W; bitpos: [27:0]; default: 2294787;
+ *  version register
+ */
+#define GPIO_DATE    0x0FFFFFFFU
+#define GPIO_DATE_M  (GPIO_DATE_V << GPIO_DATE_S)
+#define GPIO_DATE_V  0x0FFFFFFFU
+#define GPIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/gpio_struct.h b/components/soc/esp32p4/register/soc/gpio_struct.h
new file mode 100644
index 00000000000..5a9cab91712
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/gpio_struct.h
@@ -0,0 +1,878 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configuration register */
+/** Type of bt_select register
+ *  GPIO bit select register
+ */
+typedef union {
+    struct {
+        /** bt_sel : R/W; bitpos: [31:0]; default: 0;
+         *  GPIO bit select register
+         */
+        uint32_t bt_sel:32;
+    };
+    uint32_t val;
+} gpio_bt_select_reg_t;
+
+/** Type of out register
+ *  GPIO output register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO output register for GPIO0-31
+         */
+        uint32_t out_data_orig:32;
+    };
+    uint32_t val;
+} gpio_out_reg_t;
+
+/** Type of out_w1ts register
+ *  GPIO output set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output set register for GPIO0-31
+         */
+        uint32_t out_w1ts:32;
+    };
+    uint32_t val;
+} gpio_out_w1ts_reg_t;
+
+/** Type of out_w1tc register
+ *  GPIO output clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** out_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output clear register for GPIO0-31
+         */
+        uint32_t out_w1tc:32;
+    };
+    uint32_t val;
+} gpio_out_w1tc_reg_t;
+
+/** Type of out1 register
+ *  GPIO output register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_data_orig : R/W/SC/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO output register for GPIO32-56
+         */
+        uint32_t out1_data_orig:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_reg_t;
+
+/** Type of out1_w1ts register
+ *  GPIO output set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output set register for GPIO32-56
+         */
+        uint32_t out1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_w1ts_reg_t;
+
+/** Type of out1_w1tc register
+ *  GPIO output clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** out1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output clear register for GPIO32-56
+         */
+        uint32_t out1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_out1_w1tc_reg_t;
+
+/** Type of enable register
+ *  GPIO output enable register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO output enable register for GPIO0-31
+         */
+        uint32_t enable_data:32;
+    };
+    uint32_t val;
+} gpio_enable_reg_t;
+
+/** Type of enable_w1ts register
+ *  GPIO output enable set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output enable set register for GPIO0-31
+         */
+        uint32_t enable_w1ts:32;
+    };
+    uint32_t val;
+} gpio_enable_w1ts_reg_t;
+
+/** Type of enable_w1tc register
+ *  GPIO output enable clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO output enable clear register for GPIO0-31
+         */
+        uint32_t enable_w1tc:32;
+    };
+    uint32_t val;
+} gpio_enable_w1tc_reg_t;
+
+/** Type of enable1 register
+ *  GPIO output enable register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_data : R/W/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO output enable register for GPIO32-56
+         */
+        uint32_t enable1_data:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_reg_t;
+
+/** Type of enable1_w1ts register
+ *  GPIO output enable set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output enable set register for GPIO32-56
+         */
+        uint32_t enable1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_w1ts_reg_t;
+
+/** Type of enable1_w1tc register
+ *  GPIO output enable clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** enable1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO output enable clear register for GPIO32-56
+         */
+        uint32_t enable1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_enable1_w1tc_reg_t;
+
+/** Type of strap register
+ *  pad strapping register
+ */
+typedef union {
+    struct {
+        /** strapping : RO; bitpos: [15:0]; default: 0;
+         *  pad strapping register
+         */
+        uint32_t strapping:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_strap_reg_t;
+
+/** Type of in register
+ *  GPIO input register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO input register for GPIO0-31
+         */
+        uint32_t in_data_next:32;
+    };
+    uint32_t val;
+} gpio_in_reg_t;
+
+/** Type of in1 register
+ *  GPIO input register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** in1_data_next : RO; bitpos: [24:0]; default: 0;
+         *  GPIO input register for GPIO32-56
+         */
+        uint32_t in1_data_next:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_in1_reg_t;
+
+/** Type of status register
+ *  GPIO interrupt status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status register for GPIO0-31
+         */
+        uint32_t status_interrupt:32;
+    };
+    uint32_t val;
+} gpio_status_reg_t;
+
+/** Type of status_w1ts register
+ *  GPIO interrupt status set register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO0-31
+         */
+        uint32_t status_w1ts:32;
+    };
+    uint32_t val;
+} gpio_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  GPIO interrupt status clear register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO0-31
+         */
+        uint32_t status_w1tc:32;
+    };
+    uint32_t val;
+} gpio_status_w1tc_reg_t;
+
+/** Type of status1 register
+ *  GPIO interrupt status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_interrupt : R/W/WTC; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status register for GPIO32-56
+         */
+        uint32_t status1_interrupt:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_reg_t;
+
+/** Type of status1_w1ts register
+ *  GPIO interrupt status set register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_w1ts : WT; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status set register for GPIO32-56
+         */
+        uint32_t status1_w1ts:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_w1ts_reg_t;
+
+/** Type of status1_w1tc register
+ *  GPIO interrupt status clear register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status1_w1tc : WT; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt status clear register for GPIO32-56
+         */
+        uint32_t status1_w1tc:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status1_w1tc_reg_t;
+
+/** Type of intr_0 register
+ *  GPIO interrupt 0 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_0 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 0 status register for GPIO0-31
+         */
+        uint32_t int_0:32;
+    };
+    uint32_t val;
+} gpio_intr_0_reg_t;
+
+/** Type of intr1_0 register
+ *  GPIO interrupt 0 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_0 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 0 status register for GPIO32-56
+         */
+        uint32_t int1_0:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_0_reg_t;
+
+/** Type of intr_1 register
+ *  GPIO interrupt 1 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_1 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 1 status register for GPIO0-31
+         */
+        uint32_t int_1:32;
+    };
+    uint32_t val;
+} gpio_intr_1_reg_t;
+
+/** Type of intr1_1 register
+ *  GPIO interrupt 1 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_1 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 1 status register for GPIO32-56
+         */
+        uint32_t int1_1:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_1_reg_t;
+
+/** Type of status_next register
+ *  GPIO interrupt source register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt source register for GPIO0-31
+         */
+        uint32_t status_interrupt_next:32;
+    };
+    uint32_t val;
+} gpio_status_next_reg_t;
+
+/** Type of status_next1 register
+ *  GPIO interrupt source register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next1 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt source register for GPIO32-56
+         */
+        uint32_t status_interrupt_next1:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_status_next1_reg_t;
+
+/** Type of pin register
+ *  GPIO pin configuration register
+ */
+typedef union {
+    struct {
+        /** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync2_bypass:2;
+        /** pad_driver : R/W; bitpos: [2]; default: 0;
+         *  set this bit to select pad driver. 1:open-drain. 0:normal.
+         */
+        uint32_t pad_driver:1;
+        /** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
+         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync1_bypass:2;
+        uint32_t reserved_5:2;
+        /** int_type : R/W; bitpos: [9:7]; default: 0;
+         *  set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at
+         *  posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid
+         *  at high level
+         */
+        uint32_t int_type:3;
+        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+         */
+        uint32_t wakeup_enable:1;
+        /** config : R/W; bitpos: [12:11]; default: 0;
+         *  reserved
+         */
+        uint32_t config:2;
+        /** int_ena : R/W; bitpos: [17:13]; default: 0;
+         *  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+         *  interrupt.
+         */
+        uint32_t int_ena:5;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_pin_reg_t;
+
+/** Type of func_in_sel_cfg register
+ *  GPIO input function configuration register
+ */
+typedef union {
+    struct {
+        /** in_sel : R/W; bitpos: [5:0]; default: 63;
+         *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+         *  high level. s=0x3E: set this port always low level.
+         */
+        uint32_t in_sel:6;
+        /** in_inv_sel : R/W; bitpos: [6]; default: 0;
+         *  set this bit to invert input signal. 1:invert. 0:not invert.
+         */
+        uint32_t in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [7]; default: 0;
+         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+         */
+        uint32_t sig_in_sel:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_func_in_sel_cfg_reg_t;
+
+/** Type of func_out_sel_cfg register
+ *  GPIO output function select register
+ */
+typedef union {
+    struct {
+        /** out_sel : R/W/SC; bitpos: [8:0]; default: 256;
+         *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+         *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+         *  GPIO_OUT_REG[n].
+         */
+        uint32_t out_sel:9;
+        /** out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
+         *  set this bit to invert output signal.1:invert.0:not invert.
+         */
+        uint32_t out_inv_sel:1;
+        /** oen_sel : R/W; bitpos: [10]; default: 0;
+         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+         *  enable signal.0:use peripheral output enable signal.
+         */
+        uint32_t oen_sel:1;
+        /** oen_inv_sel : R/W; bitpos: [11]; default: 0;
+         *  set this bit to invert output enable signal.1:invert.0:not invert.
+         */
+        uint32_t oen_inv_sel:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} gpio_func_out_sel_cfg_reg_t;
+
+/** Type of intr_2 register
+ *  GPIO interrupt 2 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_2 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 2 status register for GPIO0-31
+         */
+        uint32_t int_2:32;
+    };
+    uint32_t val;
+} gpio_intr_2_reg_t;
+
+/** Type of intr1_2 register
+ *  GPIO interrupt 2 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_2 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 2 status register for GPIO32-56
+         */
+        uint32_t int1_2:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_2_reg_t;
+
+/** Type of intr_3 register
+ *  GPIO interrupt 3 status register for GPIO0-31
+ */
+typedef union {
+    struct {
+        /** int_3 : RO; bitpos: [31:0]; default: 0;
+         *  GPIO interrupt 3 status register for GPIO0-31
+         */
+        uint32_t int_3:32;
+    };
+    uint32_t val;
+} gpio_intr_3_reg_t;
+
+/** Type of intr1_3 register
+ *  GPIO interrupt 3 status register for GPIO32-56
+ */
+typedef union {
+    struct {
+        /** int1_3 : RO; bitpos: [24:0]; default: 0;
+         *  GPIO interrupt 3 status register for GPIO32-56
+         */
+        uint32_t int1_3:25;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} gpio_intr1_3_reg_t;
+
+/** Type of clock_gate register
+ *  GPIO clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  set this bit to enable GPIO clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_clock_gate_reg_t;
+
+/** Type of zero_det_filter_cnt register
+ *  GPIO analog comparator zero detect filter count
+ */
+typedef union {
+    struct {
+        /** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 4294967295;
+         *  GPIO analog comparator zero detect filter count
+         */
+        uint32_t zero_det_filter_cnt:32;
+    };
+    uint32_t val;
+} gpio_zero_det_filter_cnt_reg_t;
+
+/** Type of send_seq register
+ *  High speed sdio pad bist send sequence
+ */
+typedef union {
+    struct {
+        /** send_seq : R/W; bitpos: [31:0]; default: 305419896;
+         *  High speed sdio pad bist send sequence
+         */
+        uint32_t send_seq:32;
+    };
+    uint32_t val;
+} gpio_send_seq_reg_t;
+
+/** Type of recive_seq register
+ *  High speed sdio pad bist receive sequence
+ */
+typedef union {
+    struct {
+        /** recive_seq : RO; bitpos: [31:0]; default: 0;
+         *  High speed sdio pad bist receive sequence
+         */
+        uint32_t recive_seq:32;
+    };
+    uint32_t val;
+} gpio_recive_seq_reg_t;
+
+/** Type of bistin_sel register
+ *  High speed sdio pad bist in pad sel
+ */
+typedef union {
+    struct {
+        /** bistin_sel : R/W; bitpos: [3:0]; default: 15;
+         *  High speed sdio pad bist in pad sel 0:pad39, 1: pad40...
+         */
+        uint32_t bistin_sel:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} gpio_bistin_sel_reg_t;
+
+/** Type of bist_ctrl register
+ *  High speed sdio pad bist control
+ */
+typedef union {
+    struct {
+        /** bist_pad_oe : R/W; bitpos: [0]; default: 1;
+         *  High speed sdio pad bist out pad oe
+         */
+        uint32_t bist_pad_oe:1;
+        /** bist_start : WT; bitpos: [1]; default: 0;
+         *  High speed sdio pad bist start
+         */
+        uint32_t bist_start:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} gpio_bist_ctrl_reg_t;
+
+/** Type of date register
+ *  GPIO version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2294787;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_date_reg_t;
+
+
+/** Group: GPIO INT RAW REG */
+/** Type of int_raw register
+ *  analog comparator interrupt raw
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt raw
+         */
+        uint32_t comp0_neg_int_raw:1;
+        /** comp0_pos_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt raw
+         */
+        uint32_t comp0_pos_int_raw:1;
+        /** comp0_all_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt raw
+         */
+        uint32_t comp0_all_int_raw:1;
+        /** comp1_neg_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt raw
+         */
+        uint32_t comp1_neg_int_raw:1;
+        /** comp1_pos_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt raw
+         */
+        uint32_t comp1_pos_int_raw:1;
+        /** comp1_all_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt raw
+         */
+        uint32_t comp1_all_int_raw:1;
+        /** bistok_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  pad bistok interrupt raw
+         */
+        uint32_t bistok_int_raw:1;
+        /** bistfail_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt raw
+         */
+        uint32_t bistfail_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_raw_reg_t;
+
+
+/** Group: GPIO INT ST REG */
+/** Type of int_st register
+ *  analog comparator interrupt status
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_st : RO; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt status
+         */
+        uint32_t comp0_neg_int_st:1;
+        /** comp0_pos_int_st : RO; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt status
+         */
+        uint32_t comp0_pos_int_st:1;
+        /** comp0_all_int_st : RO; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt status
+         */
+        uint32_t comp0_all_int_st:1;
+        /** comp1_neg_int_st : RO; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt status
+         */
+        uint32_t comp1_neg_int_st:1;
+        /** comp1_pos_int_st : RO; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt status
+         */
+        uint32_t comp1_pos_int_st:1;
+        /** comp1_all_int_st : RO; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt status
+         */
+        uint32_t comp1_all_int_st:1;
+        /** bistok_int_st : RO; bitpos: [6]; default: 0;
+         *  pad bistok interrupt status
+         */
+        uint32_t bistok_int_st:1;
+        /** bistfail_int_st : RO; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt status
+         */
+        uint32_t bistfail_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_st_reg_t;
+
+
+/** Group: GPIO INT ENA REG */
+/** Type of int_ena register
+ *  analog comparator interrupt enable
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_ena : R/W; bitpos: [0]; default: 1;
+         *  analog comparator pos edge interrupt enable
+         */
+        uint32_t comp0_neg_int_ena:1;
+        /** comp0_pos_int_ena : R/W; bitpos: [1]; default: 1;
+         *  analog comparator neg edge interrupt enable
+         */
+        uint32_t comp0_pos_int_ena:1;
+        /** comp0_all_int_ena : R/W; bitpos: [2]; default: 1;
+         *  analog comparator neg or pos edge interrupt enable
+         */
+        uint32_t comp0_all_int_ena:1;
+        /** comp1_neg_int_ena : R/W; bitpos: [3]; default: 1;
+         *  analog comparator pos edge interrupt enable
+         */
+        uint32_t comp1_neg_int_ena:1;
+        /** comp1_pos_int_ena : R/W; bitpos: [4]; default: 1;
+         *  analog comparator neg edge interrupt enable
+         */
+        uint32_t comp1_pos_int_ena:1;
+        /** comp1_all_int_ena : R/W; bitpos: [5]; default: 1;
+         *  analog comparator neg or pos edge interrupt enable
+         */
+        uint32_t comp1_all_int_ena:1;
+        /** bistok_int_ena : R/W; bitpos: [6]; default: 1;
+         *  pad bistok interrupt enable
+         */
+        uint32_t bistok_int_ena:1;
+        /** bistfail_int_ena : R/W; bitpos: [7]; default: 1;
+         *  pad bistfail interrupt enable
+         */
+        uint32_t bistfail_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_ena_reg_t;
+
+
+/** Group: GPIO INT CLR REG */
+/** Type of int_clr register
+ *  analog comparator interrupt clear
+ */
+typedef union {
+    struct {
+        /** comp0_neg_int_clr : WT; bitpos: [0]; default: 0;
+         *  analog comparator pos edge interrupt clear
+         */
+        uint32_t comp0_neg_int_clr:1;
+        /** comp0_pos_int_clr : WT; bitpos: [1]; default: 0;
+         *  analog comparator neg edge interrupt clear
+         */
+        uint32_t comp0_pos_int_clr:1;
+        /** comp0_all_int_clr : WT; bitpos: [2]; default: 0;
+         *  analog comparator neg or pos edge interrupt clear
+         */
+        uint32_t comp0_all_int_clr:1;
+        /** comp1_neg_int_clr : WT; bitpos: [3]; default: 0;
+         *  analog comparator pos edge interrupt clear
+         */
+        uint32_t comp1_neg_int_clr:1;
+        /** comp1_pos_int_clr : WT; bitpos: [4]; default: 0;
+         *  analog comparator neg edge interrupt clear
+         */
+        uint32_t comp1_pos_int_clr:1;
+        /** comp1_all_int_clr : WT; bitpos: [5]; default: 0;
+         *  analog comparator neg or pos edge interrupt clear
+         */
+        uint32_t comp1_all_int_clr:1;
+        /** bistok_int_clr : WT; bitpos: [6]; default: 0;
+         *  pad bistok interrupt enable
+         */
+        uint32_t bistok_int_clr:1;
+        /** bistfail_int_clr : WT; bitpos: [7]; default: 0;
+         *  pad bistfail interrupt enable
+         */
+        uint32_t bistfail_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_int_clr_reg_t;
+
+
+typedef struct gpio_dev_t {
+    volatile gpio_bt_select_reg_t bt_select;
+    volatile gpio_out_reg_t out;
+    volatile gpio_out_w1ts_reg_t out_w1ts;
+    volatile gpio_out_w1tc_reg_t out_w1tc;
+    volatile gpio_out1_reg_t out1;
+    volatile gpio_out1_w1ts_reg_t out1_w1ts;
+    volatile gpio_out1_w1tc_reg_t out1_w1tc;
+    uint32_t reserved_01c;
+    volatile gpio_enable_reg_t enable;
+    volatile gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile gpio_enable_w1tc_reg_t enable_w1tc;
+    volatile gpio_enable1_reg_t enable1;
+    volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
+    volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
+    volatile gpio_strap_reg_t strap;
+    volatile gpio_in_reg_t in;
+    volatile gpio_in1_reg_t in1;
+    volatile gpio_status_reg_t status;
+    volatile gpio_status_w1ts_reg_t status_w1ts;
+    volatile gpio_status_w1tc_reg_t status_w1tc;
+    volatile gpio_status1_reg_t status1;
+    volatile gpio_status1_w1ts_reg_t status1_w1ts;
+    volatile gpio_status1_w1tc_reg_t status1_w1tc;
+    volatile gpio_intr_0_reg_t intr_0;
+    volatile gpio_intr1_0_reg_t intr1_0;
+    volatile gpio_intr_1_reg_t intr_1;
+    volatile gpio_intr1_1_reg_t intr1_1;
+    volatile gpio_status_next_reg_t status_next;
+    volatile gpio_status_next1_reg_t status_next1;
+    volatile gpio_pin_reg_t pin[57];
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; /* func0-func255: reserved for func0, 46, 67, 72, 73, 79, 81, 82, 84, 85, 87, 88, 115, 116, 119-125, 157, 204-213 */
+    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[57];
+    volatile gpio_intr_2_reg_t intr_2;
+    volatile gpio_intr1_2_reg_t intr1_2;
+    volatile gpio_intr_3_reg_t intr_3;
+    volatile gpio_intr1_3_reg_t intr1_3;
+    volatile gpio_clock_gate_reg_t clock_gate;
+    uint32_t reserved_650[44];
+    volatile gpio_int_raw_reg_t int_raw;
+    volatile gpio_int_st_reg_t int_st;
+    volatile gpio_int_ena_reg_t int_ena;
+    volatile gpio_int_clr_reg_t int_clr;
+    volatile gpio_zero_det_filter_cnt_reg_t zero_det_filter_cnt[2];
+    volatile gpio_send_seq_reg_t send_seq;
+    volatile gpio_recive_seq_reg_t recive_seq;
+    volatile gpio_bistin_sel_reg_t bistin_sel;
+    volatile gpio_bist_ctrl_reg_t bist_ctrl;
+    uint32_t reserved_728[53];
+    volatile gpio_date_reg_t date;
+} gpio_dev_t;
+
+extern gpio_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_dev_t) == 0x800, "Invalid size of gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/h264_dma_reg.h b/components/soc/esp32p4/register/soc/h264_dma_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/h264_dma_reg.h
rename to components/soc/esp32p4/register/soc/h264_dma_reg.h
diff --git a/components/soc/esp32p4/include/soc/h264_dma_struct.h b/components/soc/esp32p4/register/soc/h264_dma_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/h264_dma_struct.h
rename to components/soc/esp32p4/register/soc/h264_dma_struct.h
diff --git a/components/soc/esp32p4/include/soc/h264_reg.h b/components/soc/esp32p4/register/soc/h264_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/h264_reg.h
rename to components/soc/esp32p4/register/soc/h264_reg.h
diff --git a/components/soc/esp32p4/include/soc/h264_struct.h b/components/soc/esp32p4/register/soc/h264_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/h264_struct.h
rename to components/soc/esp32p4/register/soc/h264_struct.h
diff --git a/components/soc/esp32p4/include/soc/hmac_reg.h b/components/soc/esp32p4/register/soc/hmac_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/hmac_reg.h
rename to components/soc/esp32p4/register/soc/hmac_reg.h
diff --git a/components/soc/esp32p4/include/soc/hmac_struct.h b/components/soc/esp32p4/register/soc/hmac_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/hmac_struct.h
rename to components/soc/esp32p4/register/soc/hmac_struct.h
diff --git a/components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h b/components/soc/esp32p4/register/soc/hp2lp_peri_pms_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/hp2lp_peri_pms_reg.h
rename to components/soc/esp32p4/register/soc/hp2lp_peri_pms_reg.h
diff --git a/components/soc/esp32p4/include/soc/hp2lp_peri_pms_struct.h b/components/soc/esp32p4/register/soc/hp2lp_peri_pms_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/hp2lp_peri_pms_struct.h
rename to components/soc/esp32p4/register/soc/hp2lp_peri_pms_struct.h
diff --git a/components/soc/esp32p4/include/soc/hp_peri_pms_reg.h b/components/soc/esp32p4/register/soc/hp_peri_pms_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/hp_peri_pms_reg.h
rename to components/soc/esp32p4/register/soc/hp_peri_pms_reg.h
diff --git a/components/soc/esp32p4/include/soc/hp_peri_pms_struct.h b/components/soc/esp32p4/register/soc/hp_peri_pms_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/hp_peri_pms_struct.h
rename to components/soc/esp32p4/register/soc/hp_peri_pms_struct.h
diff --git a/components/soc/esp32p4/include/soc/hp_sys_clkrst_reg.h b/components/soc/esp32p4/register/soc/hp_sys_clkrst_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/hp_sys_clkrst_reg.h
rename to components/soc/esp32p4/register/soc/hp_sys_clkrst_reg.h
diff --git a/components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h b/components/soc/esp32p4/register/soc/hp_sys_clkrst_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/hp_sys_clkrst_struct.h
rename to components/soc/esp32p4/register/soc/hp_sys_clkrst_struct.h
diff --git a/components/soc/esp32p4/register/soc/hp_system_reg.h b/components/soc/esp32p4/register/soc/hp_system_reg.h
new file mode 100644
index 00000000000..e5d5a228e62
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/hp_system_reg.h
@@ -0,0 +1,1977 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYSTEM_VER_DATE_REG register
+ *  NA
+ */
+#define HP_SYSTEM_VER_DATE_REG (DR_REG_HP_SYS_BASE + 0x0)
+/** HP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539165977;
+ *  NA
+ */
+#define HP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
+#define HP_SYSTEM_REG_VER_DATE_M  (HP_SYSTEM_REG_VER_DATE_V << HP_SYSTEM_REG_VER_DATE_S)
+#define HP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_VER_DATE_S  0
+
+/** HP_SYSTEM_CLK_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CLK_EN_REG (DR_REG_HP_SYS_BASE + 0x4)
+/** HP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_CLK_EN    (BIT(0))
+#define HP_SYSTEM_REG_CLK_EN_M  (HP_SYSTEM_REG_CLK_EN_V << HP_SYSTEM_REG_CLK_EN_S)
+#define HP_SYSTEM_REG_CLK_EN_V  0x00000001U
+#define HP_SYSTEM_REG_CLK_EN_S  0
+
+/** HP_SYSTEM_CPU_INT_FROM_CPU_0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_REG (DR_REG_HP_SYS_BASE + 0x10)
+/** HP_SYSTEM_CPU_INT_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_M  (HP_SYSTEM_CPU_INT_FROM_CPU_0_V << HP_SYSTEM_CPU_INT_FROM_CPU_0_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_S  0
+
+/** HP_SYSTEM_CPU_INT_FROM_CPU_1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_REG (DR_REG_HP_SYS_BASE + 0x14)
+/** HP_SYSTEM_CPU_INT_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_M  (HP_SYSTEM_CPU_INT_FROM_CPU_1_V << HP_SYSTEM_CPU_INT_FROM_CPU_1_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_S  0
+
+/** HP_SYSTEM_CPU_INT_FROM_CPU_2_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_REG (DR_REG_HP_SYS_BASE + 0x18)
+/** HP_SYSTEM_CPU_INT_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_M  (HP_SYSTEM_CPU_INT_FROM_CPU_2_V << HP_SYSTEM_CPU_INT_FROM_CPU_2_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_S  0
+
+/** HP_SYSTEM_CPU_INT_FROM_CPU_3_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_REG (DR_REG_HP_SYS_BASE + 0x1c)
+/** HP_SYSTEM_CPU_INT_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_M  (HP_SYSTEM_CPU_INT_FROM_CPU_3_V << HP_SYSTEM_CPU_INT_FROM_CPU_3_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_S  0
+
+/** HP_SYSTEM_CACHE_CLK_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_CLK_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x20)
+/** HP_SYSTEM_REG_L2_CACHE_CLK_ON : R/W; bitpos: [0]; default: 1;
+ *  l2 cache clk enable
+ */
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L2_CACHE_CLK_ON_V << HP_SYSTEM_REG_L2_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_CLK_ON_S  0
+/** HP_SYSTEM_REG_L1_D_CACHE_CLK_ON : R/W; bitpos: [1]; default: 1;
+ *  l1 dcahce clk enable
+ */
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON    (BIT(1))
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_V << HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_D_CACHE_CLK_ON_S  1
+/** HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON : R/W; bitpos: [4]; default: 1;
+ *  l1 icahce1 clk enable
+ */
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON    (BIT(4))
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_V << HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I1_CACHE_CLK_ON_S  4
+/** HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON : R/W; bitpos: [5]; default: 1;
+ *  l1 icahce0 clk enable
+ */
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON    (BIT(5))
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_M  (HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_V << HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_S)
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I0_CACHE_CLK_ON_S  5
+
+/** HP_SYSTEM_CACHE_RESET_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_RESET_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x24)
+/** HP_SYSTEM_REG_L1_D_CACHE_RESET : R/W; bitpos: [1]; default: 0;
+ *  set 1 to reset l1 dcahce
+ */
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET    (BIT(1))
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_M  (HP_SYSTEM_REG_L1_D_CACHE_RESET_V << HP_SYSTEM_REG_L1_D_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_D_CACHE_RESET_S  1
+/** HP_SYSTEM_REG_L1_I1_CACHE_RESET : R/W; bitpos: [4]; default: 0;
+ *  set 1 to reset l1 icahce1
+ */
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET    (BIT(4))
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_M  (HP_SYSTEM_REG_L1_I1_CACHE_RESET_V << HP_SYSTEM_REG_L1_I1_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I1_CACHE_RESET_S  4
+/** HP_SYSTEM_REG_L1_I0_CACHE_RESET : R/W; bitpos: [5]; default: 0;
+ *  set 1 to reset l1 icahce0
+ */
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET    (BIT(5))
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_M  (HP_SYSTEM_REG_L1_I0_CACHE_RESET_V << HP_SYSTEM_REG_L1_I0_CACHE_RESET_S)
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L1_I0_CACHE_RESET_S  5
+
+/** HP_SYSTEM_DMA_ADDR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_DMA_ADDR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2c)
+/** HP_SYSTEM_REG_SYS_DMA_ADDR_SEL : R/W; bitpos: [0]; default: 0;
+ *  0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx
+ */
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL    (BIT(0))
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_M  (HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_V << HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_S)
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_V  0x00000001U
+#define HP_SYSTEM_REG_SYS_DMA_ADDR_SEL_S  0
+
+/** HP_SYSTEM_TCM_RAM_WRR_CONFIG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RAM_WRR_CONFIG_REG (DR_REG_HP_SYS_BASE + 0x34)
+/** HP_SYSTEM_REG_TCM_RAM_IBUS0_WT : R/W; bitpos: [2:0]; default: 7;
+ *  weight value of ibus0
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_M  (HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_V << HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS0_WT_S  0
+/** HP_SYSTEM_REG_TCM_RAM_IBUS1_WT : R/W; bitpos: [5:3]; default: 7;
+ *  weight value of ibus1
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_M  (HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_V << HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS1_WT_S  3
+/** HP_SYSTEM_REG_TCM_RAM_IBUS2_WT : R/W; bitpos: [8:6]; default: 4;
+ *  weight value of ibus2
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_M  (HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_V << HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS2_WT_S  6
+/** HP_SYSTEM_REG_TCM_RAM_IBUS3_WT : R/W; bitpos: [11:9]; default: 4;
+ *  weight value of ibus3
+ */
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_M  (HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_V << HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_IBUS3_WT_S  9
+/** HP_SYSTEM_REG_TCM_RAM_DBUS0_WT : R/W; bitpos: [14:12]; default: 5;
+ *  weight value of dbus0
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_M  (HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_V << HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS0_WT_S  12
+/** HP_SYSTEM_REG_TCM_RAM_DBUS1_WT : R/W; bitpos: [17:15]; default: 5;
+ *  weight value of dbus1
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_M  (HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_V << HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS1_WT_S  15
+/** HP_SYSTEM_REG_TCM_RAM_DBUS2_WT : R/W; bitpos: [20:18]; default: 3;
+ *  weight value of dbus2
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_M  (HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_V << HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS2_WT_S  18
+/** HP_SYSTEM_REG_TCM_RAM_DBUS3_WT : R/W; bitpos: [23:21]; default: 3;
+ *  weight value of dbus3
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_M  (HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_V << HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DBUS3_WT_S  21
+/** HP_SYSTEM_REG_TCM_RAM_DMA_WT : R/W; bitpos: [26:24]; default: 2;
+ *  weight value of dma
+ */
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT    0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_M  (HP_SYSTEM_REG_TCM_RAM_DMA_WT_V << HP_SYSTEM_REG_TCM_RAM_DMA_WT_S)
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_V  0x00000007U
+#define HP_SYSTEM_REG_TCM_RAM_DMA_WT_S  24
+/** HP_SYSTEM_REG_TCM_RAM_WRR_HIGH : R/W; bitpos: [31]; default: 1;
+ *  enable weighted round robin arbitration
+ */
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH    (BIT(31))
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_M  (HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_V << HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_S)
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_RAM_WRR_HIGH_S  31
+
+/** HP_SYSTEM_TCM_SW_PARITY_BWE_MASK_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_SW_PARITY_BWE_MASK_REG (DR_REG_HP_SYS_BASE + 0x38)
+/** HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to mask tcm bwe parity code bit
+ */
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL    (BIT(0))
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_M  (HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_V << HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_S)
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_SW_PARITY_BWE_MASK_CTRL_S  0
+
+/** HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x3c)
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  HP_SYSTEM_tcm clk gatig force on
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_S  0
+
+/** HP_SYSTEM_L2_ROM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_ROM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x40)
+/** HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  l2_rom clk gating force on
+ */
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_V << HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_ROM_CLK_FORCE_ON_S  0
+
+/** HP_SYSTEM_PROBEA_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBEA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x50)
+/** HP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  module's probe_out[31:0] in a mode
+ */
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (HP_SYSTEM_REG_PROBE_A_MOD_SEL_V << HP_SYSTEM_REG_PROBE_A_MOD_SEL_S)
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
+/** HP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  This field is used to selec module's probe_out[31:0] as probe out in a mode
+ */
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_A_TOP_SEL_V << HP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
+/** HP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  This field is used to selec probe_out[31:16]
+ */
+#define HP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
+#define HP_SYSTEM_REG_PROBE_L_SEL_M  (HP_SYSTEM_REG_PROBE_L_SEL_V << HP_SYSTEM_REG_PROBE_L_SEL_S)
+#define HP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
+#define HP_SYSTEM_REG_PROBE_L_SEL_S  24
+/** HP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This field is used to selec probe_out[31:16]
+ */
+#define HP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
+#define HP_SYSTEM_REG_PROBE_H_SEL_M  (HP_SYSTEM_REG_PROBE_H_SEL_V << HP_SYSTEM_REG_PROBE_H_SEL_S)
+#define HP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
+#define HP_SYSTEM_REG_PROBE_H_SEL_S  26
+/** HP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to enable global debug probe in hp system.
+ */
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (HP_SYSTEM_REG_PROBE_GLOBAL_EN_V << HP_SYSTEM_REG_PROBE_GLOBAL_EN_S)
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
+
+/** HP_SYSTEM_PROBEB_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBEB_CTRL_REG (DR_REG_HP_SYS_BASE + 0x54)
+/** HP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  module's probe_out[31:0] in b mode.
+ */
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (HP_SYSTEM_REG_PROBE_B_MOD_SEL_V << HP_SYSTEM_REG_PROBE_B_MOD_SEL_S)
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
+/** HP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
+ */
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_B_TOP_SEL_V << HP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
+/** HP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
+ */
+#define HP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
+#define HP_SYSTEM_REG_PROBE_B_EN_M  (HP_SYSTEM_REG_PROBE_B_EN_V << HP_SYSTEM_REG_PROBE_B_EN_S)
+#define HP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
+#define HP_SYSTEM_REG_PROBE_B_EN_S  24
+
+/** HP_SYSTEM_PROBE_OUT_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBE_OUT_REG (DR_REG_HP_SYS_BASE + 0x5c)
+/** HP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_M  (HP_SYSTEM_REG_PROBE_TOP_OUT_V << HP_SYSTEM_REG_PROBE_TOP_OUT_S)
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_S  0
+
+/** HP_SYSTEM_L2_MEM_RAM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x60)
+/** HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  l2ram clk_gating force on
+ */
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_V << HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_CLK_FORCE_ON_S  0
+
+/** HP_SYSTEM_CPU_CORESTALLED_ST_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_CORESTALLED_ST_REG (DR_REG_HP_SYS_BASE + 0x64)
+/** HP_SYSTEM_REG_CORE0_CORESTALLED_ST : RO; bitpos: [0]; default: 0;
+ *  hp core0 corestalled status
+ */
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST    (BIT(0))
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_M  (HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V << HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S)
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V  0x00000001U
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S  0
+/** HP_SYSTEM_REG_CORE1_CORESTALLED_ST : RO; bitpos: [1]; default: 0;
+ *  hp core1 corestalled status
+ */
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST    (BIT(1))
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_M  (HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V << HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S)
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V  0x00000001U
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S  1
+
+/** HP_SYSTEM_CRYPTO_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CRYPTO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
+/** HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+
+/** HP_SYSTEM_GPIO_O_HOLD_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HOLD_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x74)
+/** HP_SYSTEM_REG_GPIO_0_HOLD_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  hold control for gpio47~16
+ */
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_M  (HP_SYSTEM_REG_GPIO_0_HOLD_LOW_V << HP_SYSTEM_REG_GPIO_0_HOLD_LOW_S)
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_LOW_S  0
+
+/** HP_SYSTEM_GPIO_O_HOLD_CTRL1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HOLD_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x78)
+/** HP_SYSTEM_REG_GPIO_0_HOLD_HIGH : R/W; bitpos: [8:0]; default: 0;
+ *  hold control for gpio56~48
+ */
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH    0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_M  (HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_V << HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_S)
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_V  0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HOLD_HIGH_S  0
+
+/** HP_SYSTEM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0x7c)
+/** HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_M  (HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_V << HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_S  0
+/** HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_S  1
+
+/** HP_SYSTEM_CACHE_APB_POSTW_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_APB_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x80)
+/** HP_SYSTEM_REG_CACHE_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  cache apb register interface post write enable, 1 will speed up write, but will
+ *  take some time to update value to register
+ */
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_M  (HP_SYSTEM_REG_CACHE_APB_POSTW_EN_V << HP_SYSTEM_REG_CACHE_APB_POSTW_EN_S)
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_REG_CACHE_APB_POSTW_EN_S  0
+
+/** HP_SYSTEM_L2_MEM_SUBSIZE_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_SUBSIZE_REG (DR_REG_HP_SYS_BASE + 0x84)
+/** HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE : R/W; bitpos: [1:0]; default: 0;
+ *  l2mem sub block size 00=>32 01=>64 10=>128 11=>256
+ */
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE    0x00000003U
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_M  (HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_V << HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_S)
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_V  0x00000003U
+#define HP_SYSTEM_REG_L2_MEM_SUB_BLKSIZE_S  0
+
+/** HP_SYSTEM_L2_MEM_INT_RAW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x9c)
+/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  intr triggered when two bit error detected and corrected from ecc
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_RAW_S  0
+/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds
+ *  0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_RAW_S  1
+/** HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  intr triggered when err response occurs
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_M  (HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_V << HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_RAW_S  2
+
+/** HP_SYSTEM_L2_MEM_INT_ST_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_ST_REG (DR_REG_HP_SYS_BASE + 0xa0)
+/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ST_S  0
+/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ST_S  1
+/** HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_M  (HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_V << HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ST_S  2
+
+/** HP_SYSTEM_L2_MEM_INT_ENA_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0xa4)
+/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ENA_S  0
+/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ENA_S  1
+/** HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_M  (HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_V << HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_ENA_S  2
+
+/** HP_SYSTEM_L2_MEM_INT_CLR_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0xa8)
+/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_CLR_S  0
+/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_CLR_S  1
+/** HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_M  (HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_V << HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_S)
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ERR_RESP_INT_CLR_S  2
+
+/** HP_SYSTEM_L2_MEM_L2_RAM_ECC_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_L2_RAM_ECC_REG (DR_REG_HP_SYS_BASE + 0xac)
+/** HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT0_ECC_EN_S  0
+/** HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN    (BIT(1))
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT1_ECC_EN_S  1
+/** HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN    (BIT(2))
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT2_ECC_EN_S  2
+/** HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN    (BIT(3))
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT3_ECC_EN_S  3
+/** HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN    (BIT(4))
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT4_ECC_EN_S  4
+/** HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN    (BIT(5))
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_M  (HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_V << HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_RAM_UNIT5_ECC_EN_S  5
+
+/** HP_SYSTEM_L2_MEM_INT_RECORD0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RECORD0_REG (DR_REG_HP_SYS_BASE + 0xb0)
+/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR : RO; bitpos: [20:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR    0x001FFFFFU
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_V  0x001FFFFFU
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_ADDR_S  0
+/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE : RO; bitpos: [21]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE    (BIT(21))
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_WE_S  21
+/** HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER : RO; bitpos: [24:22]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER    0x00000007U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_M  (HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_V << HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_S)
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_V  0x00000007U
+#define HP_SYSTEM_REG_L2_MEM_EXCEED_ADDR_INT_MASTER_S  22
+
+/** HP_SYSTEM_L2_MEM_INT_RECORD1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_INT_RECORD1_REG (DR_REG_HP_SYS_BASE + 0xb4)
+/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR : RO; bitpos: [14:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR    0x00007FFFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_V  0x00007FFFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_INT_ADDR_S  0
+/** HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR : RO; bitpos: [15]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR    (BIT(15))
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_M  (HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_V << HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_ONE_BIT_ERR_S  15
+/** HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR : RO; bitpos: [16]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR    (BIT(16))
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_M  (HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_V << HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_ECC_TWO_BIT_ERR_S  16
+/** HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT : RO; bitpos: [25:17]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT    0x000001FFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_M  (HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_V << HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_S)
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_V  0x000001FFU
+#define HP_SYSTEM_REG_L2_MEM_ECC_ERR_BIT_S  17
+/** HP_SYSTEM_REG_L2_CACHE_ERR_BANK : RO; bitpos: [26]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK    (BIT(26))
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_M  (HP_SYSTEM_REG_L2_CACHE_ERR_BANK_V << HP_SYSTEM_REG_L2_CACHE_ERR_BANK_S)
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_ERR_BANK_S  26
+
+/** HP_SYSTEM_L2_MEM_L2_CACHE_ECC_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_L2_CACHE_ECC_REG (DR_REG_HP_SYS_BASE + 0xc4)
+/** HP_SYSTEM_REG_L2_CACHE_ECC_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_M  (HP_SYSTEM_REG_L2_CACHE_ECC_EN_V << HP_SYSTEM_REG_L2_CACHE_ECC_EN_S)
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_CACHE_ECC_EN_S  0
+
+/** HP_SYSTEM_L1CACHE_BUS0_ID_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1CACHE_BUS0_ID_REG (DR_REG_HP_SYS_BASE + 0xc8)
+/** HP_SYSTEM_REG_L1_CACHE_BUS0_ID : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID    0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_M  (HP_SYSTEM_REG_L1_CACHE_BUS0_ID_V << HP_SYSTEM_REG_L1_CACHE_BUS0_ID_S)
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_V  0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS0_ID_S  0
+
+/** HP_SYSTEM_L1CACHE_BUS1_ID_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1CACHE_BUS1_ID_REG (DR_REG_HP_SYS_BASE + 0xcc)
+/** HP_SYSTEM_REG_L1_CACHE_BUS1_ID : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID    0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_M  (HP_SYSTEM_REG_L1_CACHE_BUS1_ID_V << HP_SYSTEM_REG_L1_CACHE_BUS1_ID_S)
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_V  0x0000000FU
+#define HP_SYSTEM_REG_L1_CACHE_BUS1_ID_S  0
+
+/** HP_SYSTEM_L2_MEM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xd8)
+/** HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_M  (HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_V << HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_EN_S  0
+/** HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_RESULT_S  1
+
+/** HP_SYSTEM_L2_MEM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xdc)
+/** HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_M  (HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_V << HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_LOW_S  0
+
+/** HP_SYSTEM_L2_MEM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xe0)
+/** HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_M  (HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_V << HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_S)
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_L2_MEM_RDN_ECO_HIGH_S  0
+
+/** HP_SYSTEM_TCM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xe4)
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_S  0
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_S  1
+
+/** HP_SYSTEM_TCM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xe8)
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_S  0
+
+/** HP_SYSTEM_TCM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xec)
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_S  0
+
+/** HP_SYSTEM_GPIO_DED_HOLD_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_DED_HOLD_CTRL_REG (DR_REG_HP_SYS_BASE + 0xf0)
+/** HP_SYSTEM_REG_GPIO_DED_HOLD : R/W; bitpos: [25:0]; default: 0;
+ *  hold control for gpio63~56
+ */
+#define HP_SYSTEM_REG_GPIO_DED_HOLD    0x03FFFFFFU
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_M  (HP_SYSTEM_REG_GPIO_DED_HOLD_V << HP_SYSTEM_REG_GPIO_DED_HOLD_S)
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_V  0x03FFFFFFU
+#define HP_SYSTEM_REG_GPIO_DED_HOLD_S  0
+
+/** HP_SYSTEM_L2_MEM_SW_ECC_BWE_MASK_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_SW_ECC_BWE_MASK_REG (DR_REG_HP_SYS_BASE + 0xf4)
+/** HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to mask bwe hamming code bit
+ */
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_M  (HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_V << HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_S)
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_SW_ECC_BWE_MASK_CTRL_S  0
+
+/** HP_SYSTEM_USB20OTG_MEM_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_USB20OTG_MEM_CTRL_REG (DR_REG_HP_SYS_BASE + 0xf8)
+/** HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_V << HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_USB20_MEM_CLK_FORCE_ON_S  0
+
+/** HP_SYSTEM_TCM_INT_RAW_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0xfc)
+/** HP_SYSTEM_TCM_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_V << HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_RAW_S  31
+
+/** HP_SYSTEM_TCM_INT_ST_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x100)
+/** HP_SYSTEM_TCM_PARITY_ERR_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_ST_V << HP_SYSTEM_TCM_PARITY_ERR_INT_ST_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ST_S  31
+
+/** HP_SYSTEM_TCM_INT_ENA_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x104)
+/** HP_SYSTEM_TCM_PARITY_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_V << HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ENA_S  31
+
+/** HP_SYSTEM_TCM_INT_CLR_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x108)
+/** HP_SYSTEM_TCM_PARITY_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR    (BIT(31))
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_V << HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_CLR_S  31
+
+/** HP_SYSTEM_TCM_PARITY_INT_RECORD_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_INT_RECORD_REG (DR_REG_HP_SYS_BASE + 0x10c)
+/** HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR : RO; bitpos: [12:0]; default: 0;
+ *  hp tcm_parity_err_addr
+ */
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR    0x00001FFFU
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_M  (HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_V << HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_S)
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_V  0x00001FFFU
+#define HP_SYSTEM_TCM_PARITY_ERR_INT_ADDR_S  0
+
+/** HP_SYSTEM_L1_CACHE_PWR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L1_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x110)
+/** HP_SYSTEM_REG_L1_CACHE_MEM_FO : R/W; bitpos: [5:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO    0x0000003FU
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_M  (HP_SYSTEM_REG_L1_CACHE_MEM_FO_V << HP_SYSTEM_REG_L1_CACHE_MEM_FO_S)
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_V  0x0000003FU
+#define HP_SYSTEM_REG_L1_CACHE_MEM_FO_S  0
+
+/** HP_SYSTEM_L2_CACHE_PWR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x114)
+/** HP_SYSTEM_REG_L2_CACHE_MEM_FO : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO    0x00000003U
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_M  (HP_SYSTEM_REG_L2_CACHE_MEM_FO_V << HP_SYSTEM_REG_L2_CACHE_MEM_FO_S)
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_V  0x00000003U
+#define HP_SYSTEM_REG_L2_CACHE_MEM_FO_S  0
+
+/** HP_SYSTEM_CPU_WAITI_CONF_REG register
+ *  CPU_WAITI configuration register
+ */
+#define HP_SYSTEM_CPU_WAITI_CONF_REG (DR_REG_HP_SYS_BASE + 0x118)
+/** HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to force cpu_waiti_clk enable.
+ */
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S)
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  0
+/** HP_SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [4:1]; default: 0;
+ *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+ *  will close
+ */
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000FU
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_M  (HP_SYSTEM_CPU_WAITI_DELAY_NUM_V << HP_SYSTEM_CPU_WAITI_DELAY_NUM_S)
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000FU
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_S  1
+
+/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
+ *  Core Debug runstall configure register
+ */
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x11c)
+/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+ */
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S  0
+
+/** HP_SYSTEM_CORE_AHB_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x120)
+/** HP_SYSTEM_CORE_AHB_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 ahb timeout handle
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_M  (HP_SYSTEM_CORE_AHB_TIMEOUT_EN_V << HP_SYSTEM_CORE_AHB_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_EN_S  0
+/** HP_SYSTEM_CORE_AHB_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 ahb bus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_V << HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_AHB_TIMEOUT_THRES_S  1
+
+/** HP_SYSTEM_CORE_IBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x124)
+/** HP_SYSTEM_CORE_IBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 ibus timeout handle
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_M  (HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_V << HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_EN_S  0
+/** HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 ibus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V << HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S  1
+
+/** HP_SYSTEM_CORE_DBUS_TIMEOUT_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_REG (DR_REG_HP_SYS_BASE + 0x128)
+/** HP_SYSTEM_CORE_DBUS_TIMEOUT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 dbus timeout handle
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_M  (HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_V << HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_S)
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_EN_S  0
+/** HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 dbus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V << HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S  1
+
+/** HP_SYSTEM_ICM_CPU_H2X_CFG_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_ICM_CPU_H2X_CFG_REG (DR_REG_HP_SYS_BASE + 0x138)
+/** HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN    (BIT(0))
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_M  (HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V << HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S)
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S  0
+/** HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN    (BIT(1))
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_M  (HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V << HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S)
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S  1
+/** HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY    (BIT(2))
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_M  (HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V << HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S  2
+
+/** HP_SYSTEM_PERI1_APB_POSTW_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x13c)
+/** HP_SYSTEM_PERI1_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  HP_SYSTEM_peri1 apb register interface post write enable, 1 will speed up write, but will
+ *  take some time to update value to register
+ */
+#define HP_SYSTEM_PERI1_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_M  (HP_SYSTEM_PERI1_APB_POSTW_EN_V << HP_SYSTEM_PERI1_APB_POSTW_EN_S)
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_PERI1_APB_POSTW_EN_S  0
+
+/** HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register
+ *  Bitscrambler Peri Sel
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYS_BASE + 0x140)
+/** HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL : R/W; bitpos: [3:0]; default: 15;
+ *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0
+ *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+ *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+ *  else : none
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL    0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_M  (HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V << HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S)
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V  0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S  0
+/** HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL : R/W; bitpos: [7:4]; default: 15;
+ *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0
+ *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+ *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+ *  else : none
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL    0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_M  (HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V << HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S)
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V  0x0000000FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S  4
+
+/** HP_SYSTEM_APB_SYNC_POSTW_EN_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_APB_SYNC_POSTW_EN_REG (DR_REG_HP_SYS_BASE + 0x144)
+/** HP_SYSTEM_GMAC_APB_POSTW_EN : R/W; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_GMAC_APB_POSTW_EN    (BIT(0))
+#define HP_SYSTEM_GMAC_APB_POSTW_EN_M  (HP_SYSTEM_GMAC_APB_POSTW_EN_V << HP_SYSTEM_GMAC_APB_POSTW_EN_S)
+#define HP_SYSTEM_GMAC_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_GMAC_APB_POSTW_EN_S  0
+/** HP_SYSTEM_DSI_HOST_APB_POSTW_EN : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_DSI_HOST_APB_POSTW_EN    (BIT(1))
+#define HP_SYSTEM_DSI_HOST_APB_POSTW_EN_M  (HP_SYSTEM_DSI_HOST_APB_POSTW_EN_V << HP_SYSTEM_DSI_HOST_APB_POSTW_EN_S)
+#define HP_SYSTEM_DSI_HOST_APB_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_DSI_HOST_APB_POSTW_EN_S  1
+/** HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN : R/W; bitpos: [2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN    (BIT(2))
+#define HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_M  (HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_V << HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_S)
+#define HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_CSI_HOST_APB_SYNC_POSTW_EN_S  2
+/** HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN : R/W; bitpos: [3]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN    (BIT(3))
+#define HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_M  (HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_V << HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_S)
+#define HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_V  0x00000001U
+#define HP_SYSTEM_CSI_HOST_APB_ASYNC_POSTW_EN_S  3
+
+/** HP_SYSTEM_GDMA_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_GDMA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x148)
+/** HP_SYSTEM_DEBUG_CH_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_DEBUG_CH_NUM    0x00000003U
+#define HP_SYSTEM_DEBUG_CH_NUM_M  (HP_SYSTEM_DEBUG_CH_NUM_V << HP_SYSTEM_DEBUG_CH_NUM_S)
+#define HP_SYSTEM_DEBUG_CH_NUM_V  0x00000003U
+#define HP_SYSTEM_DEBUG_CH_NUM_S  0
+
+/** HP_SYSTEM_GMAC_CTRL0_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_GMAC_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x14c)
+/** HP_SYSTEM_PTP_PPS : RO; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PTP_PPS    (BIT(0))
+#define HP_SYSTEM_PTP_PPS_M  (HP_SYSTEM_PTP_PPS_V << HP_SYSTEM_PTP_PPS_S)
+#define HP_SYSTEM_PTP_PPS_V  0x00000001U
+#define HP_SYSTEM_PTP_PPS_S  0
+/** HP_SYSTEM_SBD_FLOWCTRL : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_SBD_FLOWCTRL    (BIT(1))
+#define HP_SYSTEM_SBD_FLOWCTRL_M  (HP_SYSTEM_SBD_FLOWCTRL_V << HP_SYSTEM_SBD_FLOWCTRL_S)
+#define HP_SYSTEM_SBD_FLOWCTRL_V  0x00000001U
+#define HP_SYSTEM_SBD_FLOWCTRL_S  1
+/** HP_SYSTEM_PHY_INTF_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PHY_INTF_SEL    0x00000007U
+#define HP_SYSTEM_PHY_INTF_SEL_M  (HP_SYSTEM_PHY_INTF_SEL_V << HP_SYSTEM_PHY_INTF_SEL_S)
+#define HP_SYSTEM_PHY_INTF_SEL_V  0x00000007U
+#define HP_SYSTEM_PHY_INTF_SEL_S  2
+/** HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON    (BIT(5))
+#define HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_V << HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_GMAC_MEM_CLK_FORCE_ON_S  5
+/** HP_SYSTEM_GMAC_RST_CLK_TX_N : RO; bitpos: [6]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_GMAC_RST_CLK_TX_N    (BIT(6))
+#define HP_SYSTEM_GMAC_RST_CLK_TX_N_M  (HP_SYSTEM_GMAC_RST_CLK_TX_N_V << HP_SYSTEM_GMAC_RST_CLK_TX_N_S)
+#define HP_SYSTEM_GMAC_RST_CLK_TX_N_V  0x00000001U
+#define HP_SYSTEM_GMAC_RST_CLK_TX_N_S  6
+/** HP_SYSTEM_GMAC_RST_CLK_RX_N : RO; bitpos: [7]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_GMAC_RST_CLK_RX_N    (BIT(7))
+#define HP_SYSTEM_GMAC_RST_CLK_RX_N_M  (HP_SYSTEM_GMAC_RST_CLK_RX_N_V << HP_SYSTEM_GMAC_RST_CLK_RX_N_S)
+#define HP_SYSTEM_GMAC_RST_CLK_RX_N_V  0x00000001U
+#define HP_SYSTEM_GMAC_RST_CLK_RX_N_S  7
+
+/** HP_SYSTEM_GMAC_CTRL1_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_GMAC_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x150)
+/** HP_SYSTEM_PTP_TIMESTAMP_L : RO; bitpos: [31:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PTP_TIMESTAMP_L    0xFFFFFFFFU
+#define HP_SYSTEM_PTP_TIMESTAMP_L_M  (HP_SYSTEM_PTP_TIMESTAMP_L_V << HP_SYSTEM_PTP_TIMESTAMP_L_S)
+#define HP_SYSTEM_PTP_TIMESTAMP_L_V  0xFFFFFFFFU
+#define HP_SYSTEM_PTP_TIMESTAMP_L_S  0
+
+/** HP_SYSTEM_GMAC_CTRL2_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_GMAC_CTRL2_REG (DR_REG_HP_SYS_BASE + 0x154)
+/** HP_SYSTEM_PTP_TIMESTAMP_H : RO; bitpos: [31:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PTP_TIMESTAMP_H    0xFFFFFFFFU
+#define HP_SYSTEM_PTP_TIMESTAMP_H_M  (HP_SYSTEM_PTP_TIMESTAMP_H_V << HP_SYSTEM_PTP_TIMESTAMP_H_S)
+#define HP_SYSTEM_PTP_TIMESTAMP_H_V  0xFFFFFFFFU
+#define HP_SYSTEM_PTP_TIMESTAMP_H_S  0
+
+/** HP_SYSTEM_VPU_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_VPU_CTRL_REG (DR_REG_HP_SYS_BASE + 0x158)
+/** HP_SYSTEM_PPA_LSLP_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PPA_LSLP_MEM_PD    (BIT(0))
+#define HP_SYSTEM_PPA_LSLP_MEM_PD_M  (HP_SYSTEM_PPA_LSLP_MEM_PD_V << HP_SYSTEM_PPA_LSLP_MEM_PD_S)
+#define HP_SYSTEM_PPA_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_PPA_LSLP_MEM_PD_S  0
+/** HP_SYSTEM_JPEG_SDSLP_MEM_PD : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_JPEG_SDSLP_MEM_PD    (BIT(1))
+#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_M  (HP_SYSTEM_JPEG_SDSLP_MEM_PD_V << HP_SYSTEM_JPEG_SDSLP_MEM_PD_S)
+#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_S  1
+/** HP_SYSTEM_JPEG_LSLP_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_JPEG_LSLP_MEM_PD    (BIT(2))
+#define HP_SYSTEM_JPEG_LSLP_MEM_PD_M  (HP_SYSTEM_JPEG_LSLP_MEM_PD_V << HP_SYSTEM_JPEG_LSLP_MEM_PD_S)
+#define HP_SYSTEM_JPEG_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_JPEG_LSLP_MEM_PD_S  2
+/** HP_SYSTEM_JPEG_DSLP_MEM_PD : R/W; bitpos: [3]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_JPEG_DSLP_MEM_PD    (BIT(3))
+#define HP_SYSTEM_JPEG_DSLP_MEM_PD_M  (HP_SYSTEM_JPEG_DSLP_MEM_PD_V << HP_SYSTEM_JPEG_DSLP_MEM_PD_S)
+#define HP_SYSTEM_JPEG_DSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_JPEG_DSLP_MEM_PD_S  3
+/** HP_SYSTEM_DMA2D_LSLP_MEM_PD : R/W; bitpos: [4]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_DMA2D_LSLP_MEM_PD    (BIT(4))
+#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_M  (HP_SYSTEM_DMA2D_LSLP_MEM_PD_V << HP_SYSTEM_DMA2D_LSLP_MEM_PD_S)
+#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_S  4
+
+/** HP_SYSTEM_USBOTG20_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_USBOTG20_CTRL_REG (DR_REG_HP_SYS_BASE + 0x15c)
+/** HP_SYSTEM_OTG_PHY_TEST_DONE : RO; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_OTG_PHY_TEST_DONE    (BIT(0))
+#define HP_SYSTEM_OTG_PHY_TEST_DONE_M  (HP_SYSTEM_OTG_PHY_TEST_DONE_V << HP_SYSTEM_OTG_PHY_TEST_DONE_S)
+#define HP_SYSTEM_OTG_PHY_TEST_DONE_V  0x00000001U
+#define HP_SYSTEM_OTG_PHY_TEST_DONE_S  0
+/** HP_SYSTEM_USB_MEM_AUX_CTRL : R/W; bitpos: [14:1]; default: 4896;
+ *  N/A
+ */
+#define HP_SYSTEM_USB_MEM_AUX_CTRL    0x00003FFFU
+#define HP_SYSTEM_USB_MEM_AUX_CTRL_M  (HP_SYSTEM_USB_MEM_AUX_CTRL_V << HP_SYSTEM_USB_MEM_AUX_CTRL_S)
+#define HP_SYSTEM_USB_MEM_AUX_CTRL_V  0x00003FFFU
+#define HP_SYSTEM_USB_MEM_AUX_CTRL_S  1
+/** HP_SYSTEM_PHY_SUSPENDM : R/W; bitpos: [15]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PHY_SUSPENDM    (BIT(15))
+#define HP_SYSTEM_PHY_SUSPENDM_M  (HP_SYSTEM_PHY_SUSPENDM_V << HP_SYSTEM_PHY_SUSPENDM_S)
+#define HP_SYSTEM_PHY_SUSPENDM_V  0x00000001U
+#define HP_SYSTEM_PHY_SUSPENDM_S  15
+/** HP_SYSTEM_PHY_SUSPEND_FORCE_EN : R/W; bitpos: [16]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PHY_SUSPEND_FORCE_EN    (BIT(16))
+#define HP_SYSTEM_PHY_SUSPEND_FORCE_EN_M  (HP_SYSTEM_PHY_SUSPEND_FORCE_EN_V << HP_SYSTEM_PHY_SUSPEND_FORCE_EN_S)
+#define HP_SYSTEM_PHY_SUSPEND_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_PHY_SUSPEND_FORCE_EN_S  16
+/** HP_SYSTEM_PHY_RSTN : R/W; bitpos: [17]; default: 1;
+ *  N/A
+ */
+#define HP_SYSTEM_PHY_RSTN    (BIT(17))
+#define HP_SYSTEM_PHY_RSTN_M  (HP_SYSTEM_PHY_RSTN_V << HP_SYSTEM_PHY_RSTN_S)
+#define HP_SYSTEM_PHY_RSTN_V  0x00000001U
+#define HP_SYSTEM_PHY_RSTN_S  17
+/** HP_SYSTEM_PHY_RESET_FORCE_EN : R/W; bitpos: [18]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PHY_RESET_FORCE_EN    (BIT(18))
+#define HP_SYSTEM_PHY_RESET_FORCE_EN_M  (HP_SYSTEM_PHY_RESET_FORCE_EN_V << HP_SYSTEM_PHY_RESET_FORCE_EN_S)
+#define HP_SYSTEM_PHY_RESET_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_PHY_RESET_FORCE_EN_S  18
+/** HP_SYSTEM_PHY_PLL_FORCE_EN : R/W; bitpos: [19]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PHY_PLL_FORCE_EN    (BIT(19))
+#define HP_SYSTEM_PHY_PLL_FORCE_EN_M  (HP_SYSTEM_PHY_PLL_FORCE_EN_V << HP_SYSTEM_PHY_PLL_FORCE_EN_S)
+#define HP_SYSTEM_PHY_PLL_FORCE_EN_V  0x00000001U
+#define HP_SYSTEM_PHY_PLL_FORCE_EN_S  19
+/** HP_SYSTEM_PHY_PLL_EN : R/W; bitpos: [20]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PHY_PLL_EN    (BIT(20))
+#define HP_SYSTEM_PHY_PLL_EN_M  (HP_SYSTEM_PHY_PLL_EN_V << HP_SYSTEM_PHY_PLL_EN_S)
+#define HP_SYSTEM_PHY_PLL_EN_V  0x00000001U
+#define HP_SYSTEM_PHY_PLL_EN_S  20
+/** HP_SYSTEM_OTG_SUSPENDM : R/W; bitpos: [21]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_OTG_SUSPENDM    (BIT(21))
+#define HP_SYSTEM_OTG_SUSPENDM_M  (HP_SYSTEM_OTG_SUSPENDM_V << HP_SYSTEM_OTG_SUSPENDM_S)
+#define HP_SYSTEM_OTG_SUSPENDM_V  0x00000001U
+#define HP_SYSTEM_OTG_SUSPENDM_S  21
+/** HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN : R/W; bitpos: [22]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN    (BIT(22))
+#define HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_M  (HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_V << HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_S)
+#define HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_V  0x00000001U
+#define HP_SYSTEM_OTG_PHY_TXBITSTUFF_EN_S  22
+/** HP_SYSTEM_OTG_PHY_REFCLK_MODE : R/W; bitpos: [23]; default: 1;
+ *  N/A
+ */
+#define HP_SYSTEM_OTG_PHY_REFCLK_MODE    (BIT(23))
+#define HP_SYSTEM_OTG_PHY_REFCLK_MODE_M  (HP_SYSTEM_OTG_PHY_REFCLK_MODE_V << HP_SYSTEM_OTG_PHY_REFCLK_MODE_S)
+#define HP_SYSTEM_OTG_PHY_REFCLK_MODE_V  0x00000001U
+#define HP_SYSTEM_OTG_PHY_REFCLK_MODE_S  23
+/** HP_SYSTEM_OTG_PHY_BISTEN : R/W; bitpos: [24]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_OTG_PHY_BISTEN    (BIT(24))
+#define HP_SYSTEM_OTG_PHY_BISTEN_M  (HP_SYSTEM_OTG_PHY_BISTEN_V << HP_SYSTEM_OTG_PHY_BISTEN_S)
+#define HP_SYSTEM_OTG_PHY_BISTEN_V  0x00000001U
+#define HP_SYSTEM_OTG_PHY_BISTEN_S  24
+
+/** HP_SYSTEM_TCM_ERR_RESP_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_ERR_RESP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x160)
+/** HP_SYSTEM_TCM_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on tcm error response
+ */
+#define HP_SYSTEM_TCM_ERR_RESP_EN    (BIT(0))
+#define HP_SYSTEM_TCM_ERR_RESP_EN_M  (HP_SYSTEM_TCM_ERR_RESP_EN_V << HP_SYSTEM_TCM_ERR_RESP_EN_S)
+#define HP_SYSTEM_TCM_ERR_RESP_EN_V  0x00000001U
+#define HP_SYSTEM_TCM_ERR_RESP_EN_S  0
+
+/** HP_SYSTEM_L2_MEM_REFRESH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_L2_MEM_REFRESH_REG (DR_REG_HP_SYS_BASE + 0x164)
+/** HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN    (BIT(0))
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFERSH_EN_S  0
+/** HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN    (BIT(1))
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFERSH_EN_S  1
+/** HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN    (BIT(2))
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFERSH_EN_S  2
+/** HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN    (BIT(3))
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFERSH_EN_S  3
+/** HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN : R/W; bitpos: [4]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN    (BIT(4))
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFERSH_EN_S  4
+/** HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN : R/W; bitpos: [5]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN    (BIT(5))
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_M  (HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_V << HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFERSH_EN_S  5
+/** HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET : R/W; bitpos: [6]; default: 1;
+ *  Set 1 to reset l2mem_refresh_cnt
+ */
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET    (BIT(6))
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_M  (HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_V << HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_S)
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_REFERSH_CNT_RESET_S  6
+/** HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE : RO; bitpos: [7]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE    (BIT(7))
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT0_REFRESH_DONE_S  7
+/** HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE : RO; bitpos: [8]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE    (BIT(8))
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT1_REFRESH_DONE_S  8
+/** HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE : RO; bitpos: [9]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE    (BIT(9))
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT2_REFRESH_DONE_S  9
+/** HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE : RO; bitpos: [10]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE    (BIT(10))
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT3_REFRESH_DONE_S  10
+/** HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE : RO; bitpos: [11]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE    (BIT(11))
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT4_REFRESH_DONE_S  11
+/** HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE : RO; bitpos: [12]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE    (BIT(12))
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_M  (HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_V << HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_S)
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_L2_MEM_UNIT5_REFRESH_DONE_S  12
+
+/** HP_SYSTEM_TCM_INIT_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_INIT_REG (DR_REG_HP_SYS_BASE + 0x168)
+/** HP_SYSTEM_REG_TCM_INIT_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_TCM_INIT_EN    (BIT(0))
+#define HP_SYSTEM_REG_TCM_INIT_EN_M  (HP_SYSTEM_REG_TCM_INIT_EN_V << HP_SYSTEM_REG_TCM_INIT_EN_S)
+#define HP_SYSTEM_REG_TCM_INIT_EN_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_EN_S  0
+/** HP_SYSTEM_REG_TCM_INIT_CNT_RESET : R/W; bitpos: [1]; default: 1;
+ *  Set 1 to reset tcm init cnt
+ */
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET    (BIT(1))
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_M  (HP_SYSTEM_REG_TCM_INIT_CNT_RESET_V << HP_SYSTEM_REG_TCM_INIT_CNT_RESET_S)
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_CNT_RESET_S  1
+/** HP_SYSTEM_REG_TCM_INIT_DONE : RO; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_TCM_INIT_DONE    (BIT(2))
+#define HP_SYSTEM_REG_TCM_INIT_DONE_M  (HP_SYSTEM_REG_TCM_INIT_DONE_V << HP_SYSTEM_REG_TCM_INIT_DONE_S)
+#define HP_SYSTEM_REG_TCM_INIT_DONE_V  0x00000001U
+#define HP_SYSTEM_REG_TCM_INIT_DONE_S  2
+
+/** HP_SYSTEM_TCM_PARITY_CHECK_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PARITY_CHECK_CTRL_REG (DR_REG_HP_SYS_BASE + 0x16c)
+/** HP_SYSTEM_TCM_PARITY_CHECK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on tcm parity check
+ */
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN    (BIT(0))
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_M  (HP_SYSTEM_TCM_PARITY_CHECK_EN_V << HP_SYSTEM_TCM_PARITY_CHECK_EN_S)
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_V  0x00000001U
+#define HP_SYSTEM_TCM_PARITY_CHECK_EN_S  0
+
+/** HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG (DR_REG_HP_SYS_BASE + 0x170)
+/** HP_SYSTEM_DFV0 : R/W; bitpos: [31:0]; default: 0;
+ *  register for DV
+ */
+#define HP_SYSTEM_DFV0    0xFFFFFFFFU
+#define HP_SYSTEM_DFV0_M  (HP_SYSTEM_DFV0_V << HP_SYSTEM_DFV0_S)
+#define HP_SYSTEM_DFV0_V  0xFFFFFFFFU
+#define HP_SYSTEM_DFV0_S  0
+
+/** HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG (DR_REG_HP_SYS_BASE + 0x174)
+/** HP_SYSTEM_DFV1 : R/W; bitpos: [31:0]; default: 0;
+ *  register for DV
+ */
+#define HP_SYSTEM_DFV1    0xFFFFFFFFU
+#define HP_SYSTEM_DFV1_M  (HP_SYSTEM_DFV1_V << HP_SYSTEM_DFV1_S)
+#define HP_SYSTEM_DFV1_V  0xFFFFFFFFU
+#define HP_SYSTEM_DFV1_S  0
+
+/** HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_REG (DR_REG_HP_SYS_BASE + 0x180)
+/** HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu
+ *  access through cache
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU    (BIT(0))
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_M  (HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_V << HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_S)
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_V  0x00000001U
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_CPU_S  0
+/** HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to enable addr interchange between psram and flash in axi matrix when dma
+ *  device access, lp core access and hp core access through ahb
+ */
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA    (BIT(1))
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_M  (HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_V << HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_S)
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_V  0x00000001U
+#define HP_SYSTEM_PSRAM_FLASH_ADDR_INTERCHANGE_DMA_S  1
+
+/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x188)
+/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+ *  post write mode in ahb2axi.
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW    (BIT(0))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S  0
+
+/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x18c)
+/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST : RO; bitpos: [31]; default: 0;
+ *  the masked interrupt status of  cpu_icm_h2x_bresp_err
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S  31
+
+/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x190)
+/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to enable cpu_icm_h2x_bresp_err int
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S  31
+
+/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x194)
+/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  Write 1 to clear cpu_icm_h2x_bresp_err  int
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S  31
+
+/** HP_SYSTEM_L2_MEM_ERR_RESP_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_L2_MEM_ERR_RESP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x198)
+/** HP_SYSTEM_L2_MEM_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on l2mem error response
+ */
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN    (BIT(0))
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_M  (HP_SYSTEM_L2_MEM_ERR_RESP_EN_V << HP_SYSTEM_L2_MEM_ERR_RESP_EN_S)
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_ERR_RESP_EN_S  0
+
+/** HP_SYSTEM_L2_MEM_AHB_BUFFER_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_L2_MEM_AHB_BUFFER_CTRL_REG (DR_REG_HP_SYS_BASE + 0x19c)
+/** HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to turn on l2mem ahb wr buffer
+ */
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN    (BIT(0))
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_M  (HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_V << HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_S)
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_AHB_WRBUFFER_EN_S  0
+/** HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to turn on l2mem ahb rd buffer
+ */
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN    (BIT(1))
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_M  (HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_V << HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_S)
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_V  0x00000001U
+#define HP_SYSTEM_L2_MEM_AHB_RDBUFFER_EN_S  1
+
+/** HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG (DR_REG_HP_SYS_BASE + 0x1a0)
+/** HP_SYSTEM_CORE_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
+ *  hp core dmactive_lpcore value
+ */
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE    (BIT(0))
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_M  (HP_SYSTEM_CORE_DMACTIVE_LPCORE_V << HP_SYSTEM_CORE_DMACTIVE_LPCORE_S)
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_V  0x00000001U
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_S  0
+
+/** HP_SYSTEM_CORE_ERR_RESP_DIS_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG (DR_REG_HP_SYS_BASE + 0x1a4)
+/** HP_SYSTEM_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
+ *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
+ *  disable ahb err resp.
+ */
+#define HP_SYSTEM_CORE_ERR_RESP_DIS    0x00000007U
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_M  (HP_SYSTEM_CORE_ERR_RESP_DIS_V << HP_SYSTEM_CORE_ERR_RESP_DIS_S)
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_V  0x00000007U
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_S  0
+
+/** HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG register
+ *  Hp core bus timeout interrupt raw register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x1a8)
+/** HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  the raw interrupt status of hp core0  ahb timeout
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_RAW_S  0
+/** HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  the raw interrupt status of hp core1  ahb timeout
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_RAW_S  1
+/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  the raw interrupt status of hp core0  ibus timeout
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S  2
+/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  the raw interrupt status of hp core1  ibus timeout
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S  3
+/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  the raw interrupt status of hp core0  dbus timeout
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S  4
+/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  the raw interrupt status of hp core1  dbus timeout
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S  5
+
+/** HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x1ac)
+/** HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of hp core0  ahb timeout
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ST_S  0
+/** HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of hp core1  ahb timeout
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ST_S  1
+/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  the masked interrupt status of hp core0  ibus timeout
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S  2
+/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  the masked interrupt status of hp core1  ibus timeout
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S  3
+/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  the masked interrupt status of hp core0  dbus timeout
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S  4
+/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST : RO; bitpos: [5]; default: 0;
+ *  the masked interrupt status of hp core1  dbus timeout
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S  5
+
+/** HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x1b0)
+/** HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable HP_SYSTEM_core0_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_ENA_S  0
+/** HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable HP_SYSTEM_core1_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_ENA_S  1
+/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable HP_SYSTEM_core0_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S  2
+/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable HP_SYSTEM_core1_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S  3
+/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable HP_SYSTEM_core0_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S  4
+/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable HP_SYSTEM_core1_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S  5
+
+/** HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x1b4)
+/** HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear HP_SYSTEM_core0_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR    (BIT(0))
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_AHB_TIMEOUT_INT_CLR_S  0
+/** HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear HP_SYSTEM_core1_ahb_timeout int
+ */
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR    (BIT(1))
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_AHB_TIMEOUT_INT_CLR_S  1
+/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear HP_SYSTEM_core0_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S  2
+/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear HP_SYSTEM_core1_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S  3
+/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear HP_SYSTEM_core0_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S  4
+/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear HP_SYSTEM_core1_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S  5
+
+/** HP_SYSTEM_GPIO_O_HYS_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HYS_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x1c0)
+/** HP_SYSTEM_REG_GPIO_0_HYS_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  hys control for gpio47~16
+ */
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_M  (HP_SYSTEM_REG_GPIO_0_HYS_LOW_V << HP_SYSTEM_REG_GPIO_0_HYS_LOW_S)
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_LOW_S  0
+
+/** HP_SYSTEM_GPIO_O_HYS_CTRL1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_GPIO_O_HYS_CTRL1_REG (DR_REG_HP_SYS_BASE + 0x1c4)
+/** HP_SYSTEM_REG_GPIO_0_HYS_HIGH : R/W; bitpos: [8:0]; default: 0;
+ *  hys control for gpio56~48
+ */
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH    0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_M  (HP_SYSTEM_REG_GPIO_0_HYS_HIGH_V << HP_SYSTEM_REG_GPIO_0_HYS_HIGH_S)
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_V  0x000001FFU
+#define HP_SYSTEM_REG_GPIO_0_HYS_HIGH_S  0
+
+/** HP_SYSTEM_RSA_PD_CTRL_REG register
+ *  rsa pd ctrl register
+ */
+#define HP_SYSTEM_RSA_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1d0)
+/** HP_SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down rsa internal memory.
+ */
+#define HP_SYSTEM_RSA_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_M  (HP_SYSTEM_RSA_MEM_FORCE_PD_V << HP_SYSTEM_RSA_MEM_FORCE_PD_S)
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_FORCE_PD_S  0
+/** HP_SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up rsa internal memory
+ */
+#define HP_SYSTEM_RSA_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_M  (HP_SYSTEM_RSA_MEM_FORCE_PU_V << HP_SYSTEM_RSA_MEM_FORCE_PU_S)
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_FORCE_PU_S  1
+/** HP_SYSTEM_RSA_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down rsa internal memory.
+ */
+#define HP_SYSTEM_RSA_MEM_PD    (BIT(2))
+#define HP_SYSTEM_RSA_MEM_PD_M  (HP_SYSTEM_RSA_MEM_PD_V << HP_SYSTEM_RSA_MEM_PD_S)
+#define HP_SYSTEM_RSA_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_PD_S  2
+
+/** HP_SYSTEM_ECC_PD_CTRL_REG register
+ *  ecc pd ctrl register
+ */
+#define HP_SYSTEM_ECC_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1d4)
+/** HP_SYSTEM_ECC_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down ecc internal memory.
+ */
+#define HP_SYSTEM_ECC_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_M  (HP_SYSTEM_ECC_MEM_FORCE_PD_V << HP_SYSTEM_ECC_MEM_FORCE_PD_S)
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_FORCE_PD_S  0
+/** HP_SYSTEM_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up ecc internal memory
+ */
+#define HP_SYSTEM_ECC_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_M  (HP_SYSTEM_ECC_MEM_FORCE_PU_V << HP_SYSTEM_ECC_MEM_FORCE_PU_S)
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_FORCE_PU_S  1
+/** HP_SYSTEM_ECC_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force power down ecc internal memory.
+ */
+#define HP_SYSTEM_ECC_MEM_PD    (BIT(2))
+#define HP_SYSTEM_ECC_MEM_PD_M  (HP_SYSTEM_ECC_MEM_PD_V << HP_SYSTEM_ECC_MEM_PD_S)
+#define HP_SYSTEM_ECC_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_PD_S  2
+
+/** HP_SYSTEM_RNG_CFG_REG register
+ *  rng cfg register
+ */
+#define HP_SYSTEM_RNG_CFG_REG (DR_REG_HP_SYS_BASE + 0x1d8)
+/** HP_SYSTEM_RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  enable rng sample chain
+ */
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE    (BIT(0))
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_M  (HP_SYSTEM_RNG_SAMPLE_ENABLE_V << HP_SYSTEM_RNG_SAMPLE_ENABLE_S)
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_V  0x00000001U
+#define HP_SYSTEM_RNG_SAMPLE_ENABLE_S  0
+/** HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
+ *  chain clk div num to pad for debug
+ */
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM    0x000000FFU
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_M  (HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V << HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S)
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S  16
+/** HP_SYSTEM_RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
+ *  debug rng sample cnt
+ */
+#define HP_SYSTEM_RNG_SAMPLE_CNT    0x000000FFU
+#define HP_SYSTEM_RNG_SAMPLE_CNT_M  (HP_SYSTEM_RNG_SAMPLE_CNT_V << HP_SYSTEM_RNG_SAMPLE_CNT_S)
+#define HP_SYSTEM_RNG_SAMPLE_CNT_V  0x000000FFU
+#define HP_SYSTEM_RNG_SAMPLE_CNT_S  24
+
+/** HP_SYSTEM_UART_PD_CTRL_REG register
+ *  ecc pd ctrl register
+ */
+#define HP_SYSTEM_UART_PD_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1dc)
+/** HP_SYSTEM_UART_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to power down hp uart internal memory.
+ */
+#define HP_SYSTEM_UART_MEM_FORCE_PD    (BIT(0))
+#define HP_SYSTEM_UART_MEM_FORCE_PD_M  (HP_SYSTEM_UART_MEM_FORCE_PD_V << HP_SYSTEM_UART_MEM_FORCE_PD_S)
+#define HP_SYSTEM_UART_MEM_FORCE_PD_V  0x00000001U
+#define HP_SYSTEM_UART_MEM_FORCE_PD_S  0
+/** HP_SYSTEM_UART_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to force power up hp uart  internal memory
+ */
+#define HP_SYSTEM_UART_MEM_FORCE_PU    (BIT(1))
+#define HP_SYSTEM_UART_MEM_FORCE_PU_M  (HP_SYSTEM_UART_MEM_FORCE_PU_V << HP_SYSTEM_UART_MEM_FORCE_PU_S)
+#define HP_SYSTEM_UART_MEM_FORCE_PU_V  0x00000001U
+#define HP_SYSTEM_UART_MEM_FORCE_PU_S  1
+
+/** HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG register
+ *  hp peri mem clk force on regpster
+ */
+#define HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG (DR_REG_HP_SYS_BASE + 0x1e0)
+/** HP_SYSTEM_RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force on mem clk in rmt
+ */
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V << HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S  0
+/** HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to force on tx mem clk in bitscrambler
+ */
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON    (BIT(1))
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V << HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S  1
+/** HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force on rx mem clk in bitscrambler
+ */
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON    (BIT(2))
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V << HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S  2
+/** HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force on mem clk in gdma
+ */
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON    (BIT(3))
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V << HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S  3
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/hp_system_struct.h b/components/soc/esp32p4/register/soc/hp_system_struct.h
new file mode 100644
index 00000000000..4e3d23f78ab
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/hp_system_struct.h
@@ -0,0 +1,2034 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: HP SYS VER DATE REG */
+/** Type of sys_ver_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [31:0]; default: 539165977;
+         *  NA
+         */
+        uint32_t reg_ver_date:32;
+    };
+    uint32_t val;
+} hp_system_ver_date_reg_t;
+
+
+/** Group: HP CLK EN REG */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_clk_en_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 0 REG */
+/** Type of cpu_int_from_cpu_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_0 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cpu_int_from_cpu_0_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 1 REG */
+/** Type of cpu_int_from_cpu_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_1 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cpu_int_from_cpu_1_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 2 REG */
+/** Type of cpu_int_from_cpu_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_2 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_2:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cpu_int_from_cpu_2_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 3 REG */
+/** Type of cpu_int_from_cpu_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_3 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_3:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cpu_int_from_cpu_3_reg_t;
+
+
+/** Group: HP CACHE CLK CONFIG REG */
+/** Type of cache_clk_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_clk_on : R/W; bitpos: [0]; default: 1;
+         *  l2 cache clk enable
+         */
+        uint32_t reg_l2_cache_clk_on:1;
+        /** reg_l1_d_cache_clk_on : R/W; bitpos: [1]; default: 1;
+         *  l1 dcahce clk enable
+         */
+        uint32_t reg_l1_d_cache_clk_on:1;
+        uint32_t reserved_2:2;
+        /** reg_l1_i1_cache_clk_on : R/W; bitpos: [4]; default: 1;
+         *  l1 icahce1 clk enable
+         */
+        uint32_t reg_l1_i1_cache_clk_on:1;
+        /** reg_l1_i0_cache_clk_on : R/W; bitpos: [5]; default: 1;
+         *  l1 icahce0 clk enable
+         */
+        uint32_t reg_l1_i0_cache_clk_on:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_cache_clk_config_reg_t;
+
+
+/** Group: HP CACHE RESET CONFIG REG */
+/** Type of cache_reset_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** reg_l1_d_cache_reset : R/W; bitpos: [1]; default: 0;
+         *  set 1 to reset l1 dcahce
+         */
+        uint32_t reg_l1_d_cache_reset:1;
+        uint32_t reserved_2:2;
+        /** reg_l1_i1_cache_reset : R/W; bitpos: [4]; default: 0;
+         *  set 1 to reset l1 icahce1
+         */
+        uint32_t reg_l1_i1_cache_reset:1;
+        /** reg_l1_i0_cache_reset : R/W; bitpos: [5]; default: 0;
+         *  set 1 to reset l1 icahce0
+         */
+        uint32_t reg_l1_i0_cache_reset:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_cache_reset_config_reg_t;
+
+
+/** Group: HP SYS DMA ADDR CTRL REG */
+/** Type of sys_dma_addr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_sys_dma_addr_sel : R/W; bitpos: [0]; default: 0;
+         *  0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx
+         */
+        uint32_t reg_sys_dma_addr_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_dma_addr_ctrl_reg_t;
+
+
+/** Group: HP TCM RAM WRR CONFIG REG */
+/** Type of tcm_ram_wrr_config register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_ram_ibus0_wt : R/W; bitpos: [2:0]; default: 7;
+         *  weight value of ibus0
+         */
+        uint32_t reg_tcm_ram_ibus0_wt:3;
+        /** reg_tcm_ram_ibus1_wt : R/W; bitpos: [5:3]; default: 7;
+         *  weight value of ibus1
+         */
+        uint32_t reg_tcm_ram_ibus1_wt:3;
+        /** reg_tcm_ram_ibus2_wt : R/W; bitpos: [8:6]; default: 4;
+         *  weight value of ibus2
+         */
+        uint32_t reg_tcm_ram_ibus2_wt:3;
+        /** reg_tcm_ram_ibus3_wt : R/W; bitpos: [11:9]; default: 4;
+         *  weight value of ibus3
+         */
+        uint32_t reg_tcm_ram_ibus3_wt:3;
+        /** reg_tcm_ram_dbus0_wt : R/W; bitpos: [14:12]; default: 5;
+         *  weight value of dbus0
+         */
+        uint32_t reg_tcm_ram_dbus0_wt:3;
+        /** reg_tcm_ram_dbus1_wt : R/W; bitpos: [17:15]; default: 5;
+         *  weight value of dbus1
+         */
+        uint32_t reg_tcm_ram_dbus1_wt:3;
+        /** reg_tcm_ram_dbus2_wt : R/W; bitpos: [20:18]; default: 3;
+         *  weight value of dbus2
+         */
+        uint32_t reg_tcm_ram_dbus2_wt:3;
+        /** reg_tcm_ram_dbus3_wt : R/W; bitpos: [23:21]; default: 3;
+         *  weight value of dbus3
+         */
+        uint32_t reg_tcm_ram_dbus3_wt:3;
+        /** reg_tcm_ram_dma_wt : R/W; bitpos: [26:24]; default: 2;
+         *  weight value of dma
+         */
+        uint32_t reg_tcm_ram_dma_wt:3;
+        uint32_t reserved_27:4;
+        /** reg_tcm_ram_wrr_high : R/W; bitpos: [31]; default: 1;
+         *  enable weighted round robin arbitration
+         */
+        uint32_t reg_tcm_ram_wrr_high:1;
+    };
+    uint32_t val;
+} hp_system_tcm_ram_wrr_config_reg_t;
+
+
+/** Group: HP TCM SW PARITY BWE MASK REG */
+/** Type of tcm_sw_parity_bwe_mask register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_sw_parity_bwe_mask_ctrl : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to mask tcm bwe parity code bit
+         */
+        uint32_t reg_tcm_sw_parity_bwe_mask_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_tcm_sw_parity_bwe_mask_reg_t;
+
+
+/** Group: HP TCM RAM PWR CTRL0 REG */
+/** Type of tcm_ram_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_tcm_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  hp_system_tcm clk gatig force on
+         */
+        uint32_t reg_hp_system_tcm_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_tcm_ram_pwr_ctrl0_reg_t;
+
+
+/** Group: HP L2 ROM PWR CTRL0 REG */
+/** Type of l2_rom_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_rom_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  l2_rom clk gating force on
+         */
+        uint32_t reg_l2_rom_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_l2_rom_pwr_ctrl0_reg_t;
+
+
+/** Group: HP PROBEA CTRL REG */
+/** Type of probea_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  module's probe_out[31:0] in a mode
+         */
+        uint32_t reg_probe_a_mod_sel:16;
+        /** reg_probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  This field is used to selec module's probe_out[31:0] as probe out in a mode
+         */
+        uint32_t reg_probe_a_top_sel:8;
+        /** reg_probe_l_sel : R/W; bitpos: [25:24]; default: 0;
+         *  This field is used to selec probe_out[31:16]
+         */
+        uint32_t reg_probe_l_sel:2;
+        /** reg_probe_h_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This field is used to selec probe_out[31:16]
+         */
+        uint32_t reg_probe_h_sel:2;
+        /** reg_probe_global_en : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable global debug probe in hp system.
+         */
+        uint32_t reg_probe_global_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_system_probea_ctrl_reg_t;
+
+
+/** Group: HP PROBEB CTRL REG */
+/** Type of probeb_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  module's probe_out[31:0] in b mode.
+         */
+        uint32_t reg_probe_b_mod_sel:16;
+        /** reg_probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
+         */
+        uint32_t reg_probe_b_top_sel:8;
+        /** reg_probe_b_en : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
+         */
+        uint32_t reg_probe_b_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_system_probeb_ctrl_reg_t;
+
+
+/** Group: HP PROBE OUT REG */
+/** Type of probe_out register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_top_out : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_probe_top_out:32;
+    };
+    uint32_t val;
+} hp_system_probe_out_reg_t;
+
+
+/** Group: HP L2 MEM RAM PWR CTRL0 REG */
+/** Type of l2_mem_ram_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  l2ram clk_gating force on
+         */
+        uint32_t reg_l2_mem_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_l2_mem_ram_pwr_ctrl0_reg_t;
+
+
+/** Group: HP CPU CORESTALLED ST REG */
+/** Type of cpu_corestalled_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_corestalled_st : RO; bitpos: [0]; default: 0;
+         *  hp core0 corestalled status
+         */
+        uint32_t reg_core0_corestalled_st:1;
+        /** reg_core1_corestalled_st : RO; bitpos: [1]; default: 0;
+         *  hp core1 corestalled status
+         */
+        uint32_t reg_core1_corestalled_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_cpu_corestalled_st_reg_t;
+
+
+/** Group: HP CRYPTO CTRL REG */
+/** Type of crypto_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_spi_manual_encrypt:1;
+        /** reg_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_db_encrypt:1;
+        /** reg_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_g0cb_decrypt:1;
+        /** reg_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_manual_encrypt:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_crypto_ctrl_reg_t;
+
+
+/** Group: HP GPIO O HOLD CTRL0 REG */
+/** Type of gpio_o_hold_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hold_low : R/W; bitpos: [31:0]; default: 0;
+         *  hold control for gpio47~16
+         */
+        uint32_t reg_gpio_0_hold_low:32;
+    };
+    uint32_t val;
+} hp_system_gpio_o_hold_ctrl0_reg_t;
+
+
+/** Group: HP GPIO O HOLD CTRL1 REG */
+/** Type of gpio_o_hold_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hold_high : R/W; bitpos: [8:0]; default: 0;
+         *  hold control for gpio56~48
+         */
+        uint32_t reg_gpio_0_hold_high:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_system_gpio_o_hold_ctrl1_reg_t;
+
+
+/** Group: HP SYS RDN ECO CS REG */
+/** Type of sys_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_rdn_eco_en:1;
+        /** reg_hp_system_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_rdn_eco_cs_reg_t;
+
+
+/** Group: HP CACHE APB POSTW EN REG */
+/** Type of cache_apb_postw_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cache_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  cache apb register interface post write enable, 1 will speed up write, but will
+         *  take some time to update value to register
+         */
+        uint32_t reg_cache_apb_postw_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cache_apb_postw_en_reg_t;
+
+
+/** Group: HP L2 MEM SUBSIZE REG */
+/** Type of l2_mem_subsize register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_sub_blksize : R/W; bitpos: [1:0]; default: 0;
+         *  l2mem sub block size 00=>32 01=>64 10=>128 11=>256
+         */
+        uint32_t reg_l2_mem_sub_blksize:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_l2_mem_subsize_reg_t;
+
+
+/** Group: HP L2 MEM INT RAW REG */
+/** Type of l2_mem_int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  intr triggered when two bit error detected and corrected from ecc
+         */
+        uint32_t reg_l2_mem_ecc_err_int_raw:1;
+        /** reg_l2_mem_exceed_addr_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds
+         *  0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_raw:1;
+        /** reg_l2_mem_err_resp_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  intr triggered when err response occurs
+         */
+        uint32_t reg_l2_mem_err_resp_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_l2_mem_int_raw_reg_t;
+
+
+/** Group: HP L2 MEM INT ST REG */
+/** Type of l2_mem_int_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_st : RO; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_st:1;
+        /** reg_l2_mem_exceed_addr_int_st : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_st:1;
+        /** reg_l2_mem_err_resp_int_st : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_l2_mem_int_st_reg_t;
+
+
+/** Group: HP L2 MEM INT ENA REG */
+/** Type of l2_mem_int_ena register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_ena : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_ena:1;
+        /** reg_l2_mem_exceed_addr_int_ena : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_ena:1;
+        /** reg_l2_mem_err_resp_int_ena : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_l2_mem_int_ena_reg_t;
+
+
+/** Group: HP L2 MEM INT CLR REG */
+/** Type of l2_mem_int_clr register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_clr : WT; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_clr:1;
+        /** reg_l2_mem_exceed_addr_int_clr : WT; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_clr:1;
+        /** reg_l2_mem_err_resp_int_clr : WT; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_err_resp_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_l2_mem_int_clr_reg_t;
+
+
+/** Group: HP L2 MEM L2 RAM ECC REG */
+/** Type of l2_mem_l2_ram_ecc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_ram_unit0_ecc_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit0_ecc_en:1;
+        /** reg_l2_ram_unit1_ecc_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit1_ecc_en:1;
+        /** reg_l2_ram_unit2_ecc_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit2_ecc_en:1;
+        /** reg_l2_ram_unit3_ecc_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit3_ecc_en:1;
+        /** reg_l2_ram_unit4_ecc_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit4_ecc_en:1;
+        /** reg_l2_ram_unit5_ecc_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_ram_unit5_ecc_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_l2_mem_l2_ram_ecc_reg_t;
+
+
+/** Group: HP L2 MEM INT RECORD0 REG */
+/** Type of l2_mem_int_record0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_exceed_addr_int_addr : RO; bitpos: [20:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_addr:21;
+        /** reg_l2_mem_exceed_addr_int_we : RO; bitpos: [21]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_we:1;
+        /** reg_l2_mem_exceed_addr_int_master : RO; bitpos: [24:22]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_exceed_addr_int_master:3;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_system_l2_mem_int_record0_reg_t;
+
+
+/** Group: HP L2 MEM INT RECORD1 REG */
+/** Type of l2_mem_int_record1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_ecc_err_int_addr : RO; bitpos: [14:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_int_addr:15;
+        /** reg_l2_mem_ecc_one_bit_err : RO; bitpos: [15]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_one_bit_err:1;
+        /** reg_l2_mem_ecc_two_bit_err : RO; bitpos: [16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_two_bit_err:1;
+        /** reg_l2_mem_ecc_err_bit : RO; bitpos: [25:17]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_ecc_err_bit:9;
+        /** reg_l2_cache_err_bank : RO; bitpos: [26]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_cache_err_bank:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_system_l2_mem_int_record1_reg_t;
+
+
+/** Group: HP L2 MEM L2 CACHE ECC REG */
+/** Type of l2_mem_l2_cache_ecc register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_ecc_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_cache_ecc_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_l2_mem_l2_cache_ecc_reg_t;
+
+
+/** Group: HP L1CACHE BUS0 ID REG */
+/** Type of l1cache_bus0_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_bus0_id : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l1_cache_bus0_id:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_l1cache_bus0_id_reg_t;
+
+
+/** Group: HP L1CACHE BUS1 ID REG */
+/** Type of l1cache_bus1_id register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_bus1_id : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l1_cache_bus1_id:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_l1cache_bus1_id_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO CS REG */
+/** Type of l2_mem_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_en:1;
+        /** reg_l2_mem_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_l2_mem_rdn_eco_cs_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO LOW REG */
+/** Type of l2_mem_rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_low:32;
+    };
+    uint32_t val;
+} hp_system_l2_mem_rdn_eco_low_reg_t;
+
+
+/** Group: HP L2 MEM RDN ECO HIGH REG */
+/** Type of l2_mem_rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t reg_l2_mem_rdn_eco_high:32;
+    };
+    uint32_t val;
+} hp_system_l2_mem_rdn_eco_high_reg_t;
+
+
+/** Group: HP TCM RDN ECO CS REG */
+/** Type of tcm_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_tcm_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_tcm_rdn_eco_en:1;
+        /** reg_hp_system_tcm_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_tcm_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_tcm_rdn_eco_cs_reg_t;
+
+
+/** Group: HP TCM RDN ECO LOW REG */
+/** Type of tcm_rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_tcm_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_tcm_rdn_eco_low:32;
+    };
+    uint32_t val;
+} hp_system_tcm_rdn_eco_low_reg_t;
+
+
+/** Group: HP TCM RDN ECO HIGH REG */
+/** Type of tcm_rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_tcm_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t reg_hp_system_tcm_rdn_eco_high:32;
+    };
+    uint32_t val;
+} hp_system_tcm_rdn_eco_high_reg_t;
+
+
+/** Group: HP GPIO DEAD HOLD CTRL REG */
+/** Type of gpio_ded_hold_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_ded_hold : R/W; bitpos: [25:0]; default: 0;
+         *  hold control for gpio63~56
+         */
+        uint32_t reg_gpio_ded_hold:26;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} hp_system_gpio_ded_hold_ctrl_reg_t;
+
+
+/** Group: HP L2 MEM SW ECC BWE MASK REG */
+/** Type of l2_mem_sw_ecc_bwe_mask register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_sw_ecc_bwe_mask_ctrl : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to mask bwe hamming code bit
+         */
+        uint32_t reg_l2_mem_sw_ecc_bwe_mask_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_l2_mem_sw_ecc_bwe_mask_reg_t;
+
+
+/** Group: HP USB20OTG MEM CTRL REG */
+/** Type of usb20otg_mem_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_usb20_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_usb20_mem_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_usb20otg_mem_ctrl_reg_t;
+
+
+/** Group: configure_register */
+/** Type of tcm_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_raw:1;
+    };
+    uint32_t val;
+} hp_system_tcm_int_raw_reg_t;
+
+/** Type of tcm_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_st:1;
+    };
+    uint32_t val;
+} hp_system_tcm_int_st_reg_t;
+
+/** Type of tcm_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_ena:1;
+    };
+    uint32_t val;
+} hp_system_tcm_int_ena_reg_t;
+
+/** Type of tcm_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tcm_parity_err_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t tcm_parity_err_int_clr:1;
+    };
+    uint32_t val;
+} hp_system_tcm_int_clr_reg_t;
+
+/** Type of core_ahb_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_ahb_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 ahb timeout handle
+         */
+        uint32_t core_ahb_timeout_en:1;
+        /** core_ahb_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 ahb bus timeout  threshold
+         */
+        uint32_t core_ahb_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_system_core_ahb_timeout_reg_t;
+
+/** Type of core_ibus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_ibus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 ibus timeout handle
+         */
+        uint32_t core_ibus_timeout_en:1;
+        /** core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 ibus timeout  threshold
+         */
+        uint32_t core_ibus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_system_core_ibus_timeout_reg_t;
+
+/** Type of core_dbus_timeout register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_dbus_timeout_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 dbus timeout handle
+         */
+        uint32_t core_dbus_timeout_en:1;
+        /** core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 dbus timeout  threshold
+         */
+        uint32_t core_dbus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_system_core_dbus_timeout_reg_t;
+
+/** Type of icm_cpu_h2x_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_icm_h2x_post_wr_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_post_wr_en:1;
+        /** cpu_icm_h2x_cut_through_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_cut_through_en:1;
+        /** cpu_icm_h2x_bridge_busy : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_bridge_busy:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_icm_cpu_h2x_cfg_reg_t;
+
+/** Type of bitscrambler_peri_sel register
+ *  Bitscrambler Peri Sel
+ */
+typedef union {
+    struct {
+        /** bitscrambler_peri_rx_sel : R/W; bitpos: [3:0]; default: 15;
+         *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler: 4'h0
+         *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+         *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+         *  else : none
+         */
+        uint32_t bitscrambler_peri_rx_sel:4;
+        /** bitscrambler_peri_tx_sel : R/W; bitpos: [7:4]; default: 15;
+         *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler: 4'h0
+         *  : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6:
+         *  adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT,
+         *  else : none
+         */
+        uint32_t bitscrambler_peri_tx_sel:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_system_bitscrambler_peri_sel_reg_t;
+
+
+/** Group: hp_system_TCM_PARITY_INT_RECORD_REG */
+/** Type of tcm_parity_int_record register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_parity_err_int_addr : RO; bitpos: [12:0]; default: 0;
+         *  hp tcm_parity_err_addr
+         */
+        uint32_t tcm_parity_err_int_addr:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} hp_system_tcm_parity_int_record_reg_t;
+
+
+/** Group: HP L1 CACHE PWR CTRL REG */
+/** Type of l1_cache_pwr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l1_cache_mem_fo : R/W; bitpos: [5:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_l1_cache_mem_fo:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_l1_cache_pwr_ctrl_reg_t;
+
+
+/** Group: HP L2 CACHE PWR CTRL REG */
+/** Type of l2_cache_pwr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_cache_mem_fo : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_l2_cache_mem_fo:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_l2_cache_pwr_ctrl_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of cpu_waiti_conf register
+ *  CPU_WAITI configuration register
+ */
+typedef union {
+    struct {
+        /** cpu_wait_mode_force_on : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to force cpu_waiti_clk enable.
+         */
+        uint32_t cpu_wait_mode_force_on:1;
+        /** cpu_waiti_delay_num : R/W; bitpos: [4:1]; default: 0;
+         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+         *  will close
+         */
+        uint32_t cpu_waiti_delay_num:4;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_system_cpu_waiti_conf_reg_t;
+
+/** Type of sys_core_debug_runstall_conf register
+ *  Core Debug runstall configure register
+ */
+typedef union {
+    struct {
+        /** sys_core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
+         *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+         */
+        uint32_t sys_core_debug_runstall_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_core_debug_runstall_conf_reg_t;
+
+/** Type of rsa_pd_ctrl register
+ *  rsa pd ctrl register
+ */
+typedef union {
+    struct {
+        /** rsa_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down rsa internal memory.
+         */
+        uint32_t rsa_mem_force_pd:1;
+        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up rsa internal memory
+         */
+        uint32_t rsa_mem_force_pu:1;
+        /** rsa_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down rsa internal memory.
+         */
+        uint32_t rsa_mem_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_rsa_pd_ctrl_reg_t;
+
+/** Type of ecc_pd_ctrl register
+ *  ecc pd ctrl register
+ */
+typedef union {
+    struct {
+        /** ecc_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down ecc internal memory.
+         */
+        uint32_t ecc_mem_force_pd:1;
+        /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up ecc internal memory
+         */
+        uint32_t ecc_mem_force_pu:1;
+        /** ecc_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force power down ecc internal memory.
+         */
+        uint32_t ecc_mem_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_ecc_pd_ctrl_reg_t;
+
+/** Type of rng_cfg register
+ *  rng cfg register
+ */
+typedef union {
+    struct {
+        /** rng_sample_enable : R/W; bitpos: [0]; default: 0;
+         *  enable rng sample chain
+         */
+        uint32_t rng_sample_enable:1;
+        uint32_t reserved_1:15;
+        /** rng_chain_clk_div_num : R/W; bitpos: [23:16]; default: 0;
+         *  chain clk div num to pad for debug
+         */
+        uint32_t rng_chain_clk_div_num:8;
+        /** rng_sample_cnt : RO; bitpos: [31:24]; default: 0;
+         *  debug rng sample cnt
+         */
+        uint32_t rng_sample_cnt:8;
+    };
+    uint32_t val;
+} hp_system_rng_cfg_reg_t;
+
+/** Type of uart_pd_ctrl register
+ *  ecc pd ctrl register
+ */
+typedef union {
+    struct {
+        /** uart_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to power down hp uart internal memory.
+         */
+        uint32_t uart_mem_force_pd:1;
+        /** uart_mem_force_pu : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to force power up hp uart  internal memory
+         */
+        uint32_t uart_mem_force_pu:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_uart_pd_ctrl_reg_t;
+
+/** Type of peri_mem_clk_force_on register
+ *  hp peri mem clk force on regpster
+ */
+typedef union {
+    struct {
+        /** rmt_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force on mem clk in rmt
+         */
+        uint32_t rmt_mem_clk_force_on:1;
+        /** bitscrambler_tx_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force on tx mem clk in bitscrambler
+         */
+        uint32_t bitscrambler_tx_mem_clk_force_on:1;
+        /** bitscrambler_rx_mem_clk_force_on : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force on rx mem clk in bitscrambler
+         */
+        uint32_t bitscrambler_rx_mem_clk_force_on:1;
+        /** gdma_mem_clk_force_on : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force on mem clk in gdma
+         */
+        uint32_t gdma_mem_clk_force_on:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_peri_mem_clk_force_on_reg_t;
+
+
+/** Group: HP PERI1 APB POSTW EN REG */
+/** Type of peri1_apb_postw_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** peri1_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  hp_system_peri1 apb register interface post write enable, 1 will speed up write, but will
+         *  take some time to update value to register
+         */
+        uint32_t peri1_apb_postw_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_peri1_apb_postw_en_reg_t;
+
+
+/** Group: APB Sync Register */
+/** Type of sys_apb_sync_postw_en register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_gmac_apb_postw_en : R/W; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_apb_postw_en:1;
+        /** sys_dsi_host_apb_postw_en : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_dsi_host_apb_postw_en:1;
+        /** sys_csi_host_apb_sync_postw_en : R/W; bitpos: [2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_csi_host_apb_sync_postw_en:1;
+        /** sys_csi_host_apb_async_postw_en : R/W; bitpos: [3]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_csi_host_apb_async_postw_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_apb_sync_postw_en_reg_t;
+
+
+/** Group: GDMA Ctonrol Register */
+/** Type of sys_gdma_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_debug_ch_num : R/W; bitpos: [1:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_debug_ch_num:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gdma_ctrl_reg_t;
+
+
+/** Group: GMAC Control Register */
+/** Type of sys_gmac_ctrl0 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_pps : RO; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_pps:1;
+        /** sys_sbd_flowctrl : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_sbd_flowctrl:1;
+        /** sys_phy_intf_sel : R/W; bitpos: [4:2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_intf_sel:3;
+        /** sys_gmac_mem_clk_force_on : R/W; bitpos: [5]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_mem_clk_force_on:1;
+        /** sys_gmac_rst_clk_tx_n : RO; bitpos: [6]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_rst_clk_tx_n:1;
+        /** sys_gmac_rst_clk_rx_n : RO; bitpos: [7]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_rst_clk_rx_n:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_system_gmac_ctrl0_reg_t;
+
+/** Type of sys_gmac_ctrl1 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_timestamp_l : RO; bitpos: [31:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_timestamp_l:32;
+    };
+    uint32_t val;
+} hp_system_gmac_ctrl1_reg_t;
+
+/** Type of sys_gmac_ctrl2 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_timestamp_h : RO; bitpos: [31:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_timestamp_h:32;
+    };
+    uint32_t val;
+} hp_system_gmac_ctrl2_reg_t;
+
+
+/** Group: VPU Control Register */
+/** Type of sys_vpu_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ppa_lslp_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ppa_lslp_mem_pd:1;
+        /** sys_jpeg_sdslp_mem_pd : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_sdslp_mem_pd:1;
+        /** sys_jpeg_lslp_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_lslp_mem_pd:1;
+        /** sys_jpeg_dslp_mem_pd : R/W; bitpos: [3]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_dslp_mem_pd:1;
+        /** sys_dma2d_lslp_mem_pd : R/W; bitpos: [4]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_dma2d_lslp_mem_pd:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_system_vpu_ctrl_reg_t;
+
+
+/** Group: USB OTG20 Control Register */
+/** Type of sys_usbotg20_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_otg_phy_test_done : RO; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_test_done:1;
+        /** sys_usb_mem_aux_ctrl : R/W; bitpos: [14:1]; default: 4896;
+         *  N/A
+         */
+        uint32_t sys_usb_mem_aux_ctrl:14;
+        /** sys_phy_suspendm : R/W; bitpos: [15]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_suspendm:1;
+        /** sys_phy_suspend_force_en : R/W; bitpos: [16]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_suspend_force_en:1;
+        /** sys_phy_rstn : R/W; bitpos: [17]; default: 1;
+         *  N/A
+         */
+        uint32_t sys_phy_rstn:1;
+        /** sys_phy_reset_force_en : R/W; bitpos: [18]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_reset_force_en:1;
+        /** sys_phy_pll_force_en : R/W; bitpos: [19]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_pll_force_en:1;
+        /** sys_phy_pll_en : R/W; bitpos: [20]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_pll_en:1;
+        /** sys_otg_suspendm : R/W; bitpos: [21]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_suspendm:1;
+        /** sys_otg_phy_txbitstuff_en : R/W; bitpos: [22]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_txbitstuff_en:1;
+        /** sys_otg_phy_refclk_mode : R/W; bitpos: [23]; default: 1;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_refclk_mode:1;
+        /** sys_otg_phy_bisten : R/W; bitpos: [24]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_otg_phy_bisten:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_system_usbotg20_ctrl_reg_t;
+
+
+/** Group: hp_system_TCM_ERR_RESP_CTRL_REG */
+/** Type of tcm_err_resp_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on tcm error response
+         */
+        uint32_t tcm_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_tcm_err_resp_ctrl_reg_t;
+
+
+/** Group: HP L2 MEM REFRESH REG */
+/** Type of l2_mem_refresh register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_l2_mem_unit0_refersh_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit0_refersh_en:1;
+        /** reg_l2_mem_unit1_refersh_en : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit1_refersh_en:1;
+        /** reg_l2_mem_unit2_refersh_en : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit2_refersh_en:1;
+        /** reg_l2_mem_unit3_refersh_en : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit3_refersh_en:1;
+        /** reg_l2_mem_unit4_refersh_en : R/W; bitpos: [4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit4_refersh_en:1;
+        /** reg_l2_mem_unit5_refersh_en : R/W; bitpos: [5]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit5_refersh_en:1;
+        /** reg_l2_mem_refersh_cnt_reset : R/W; bitpos: [6]; default: 1;
+         *  Set 1 to reset l2mem_refresh_cnt
+         */
+        uint32_t reg_l2_mem_refersh_cnt_reset:1;
+        /** reg_l2_mem_unit0_refresh_done : RO; bitpos: [7]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit0_refresh_done:1;
+        /** reg_l2_mem_unit1_refresh_done : RO; bitpos: [8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit1_refresh_done:1;
+        /** reg_l2_mem_unit2_refresh_done : RO; bitpos: [9]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit2_refresh_done:1;
+        /** reg_l2_mem_unit3_refresh_done : RO; bitpos: [10]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit3_refresh_done:1;
+        /** reg_l2_mem_unit4_refresh_done : RO; bitpos: [11]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit4_refresh_done:1;
+        /** reg_l2_mem_unit5_refresh_done : RO; bitpos: [12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_l2_mem_unit5_refresh_done:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} hp_system_l2_mem_refresh_reg_t;
+
+
+/** Group: HP TCM INIT REG */
+/** Type of tcm_init register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_tcm_init_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_tcm_init_en:1;
+        /** reg_tcm_init_cnt_reset : R/W; bitpos: [1]; default: 1;
+         *  Set 1 to reset tcm init cnt
+         */
+        uint32_t reg_tcm_init_cnt_reset:1;
+        /** reg_tcm_init_done : RO; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_tcm_init_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_tcm_init_reg_t;
+
+
+/** Group: hp_system_TCM_PARITY_CHECK_CTRL_REG */
+/** Type of tcm_parity_check_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_parity_check_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on tcm parity check
+         */
+        uint32_t tcm_parity_check_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_tcm_parity_check_ctrl_reg_t;
+
+
+/** Group: hp_system_DESIGN_FOR_VERIFICATION0 */
+/** Type of design_for_verification0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dfv0 : R/W; bitpos: [31:0]; default: 0;
+         *  register for DV
+         */
+        uint32_t dfv0:32;
+    };
+    uint32_t val;
+} hp_system_design_for_verification0_reg_t;
+
+
+/** Group: hp_system_DESIGN_FOR_VERIFICATION1 */
+/** Type of design_for_verification1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dfv1 : R/W; bitpos: [31:0]; default: 0;
+         *  register for DV
+         */
+        uint32_t dfv1:32;
+    };
+    uint32_t val;
+} hp_system_design_for_verification1_reg_t;
+
+
+/** Group: hp_system_PSRAM_FLASH_ADDR_INTERCHANGE */
+/** Type of psram_flash_addr_interchange register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** psram_flash_addr_interchange_cpu : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu
+         *  access through cache
+         */
+        uint32_t psram_flash_addr_interchange_cpu:1;
+        /** psram_flash_addr_interchange_dma : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to enable addr interchange between psram and flash in axi matrix when dma
+         *  device access, lp core access and hp core access through ahb
+         */
+        uint32_t psram_flash_addr_interchange_dma:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_psram_flash_addr_interchange_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of ahb2axi_bresp_err_int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_icm_h2x_bresp_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+         *  post write mode in ahb2axi.
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_ahb2axi_bresp_err_int_raw_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_st : RO; bitpos: [31]; default: 0;
+         *  the masked interrupt status of  cpu_icm_h2x_bresp_err
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_st:1;
+    };
+    uint32_t val;
+} hp_system_ahb2axi_bresp_err_int_st_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_ena : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to enable cpu_icm_h2x_bresp_err int
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_ena:1;
+    };
+    uint32_t val;
+} hp_system_ahb2axi_bresp_err_int_ena_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** cpu_icm_h2x_bresp_err_int_clr : WT; bitpos: [31]; default: 0;
+         *  Write 1 to clear cpu_icm_h2x_bresp_err  int
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_clr:1;
+    };
+    uint32_t val;
+} hp_system_ahb2axi_bresp_err_int_clr_reg_t;
+
+/** Type of core_timeout_int_raw register
+ *  Hp core bus timeout interrupt raw register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  the raw interrupt status of hp core0  ahb timeout
+         */
+        uint32_t core0_ahb_timeout_int_raw:1;
+        /** core1_ahb_timeout_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  the raw interrupt status of hp core1  ahb timeout
+         */
+        uint32_t core1_ahb_timeout_int_raw:1;
+        /** core0_ibus_timeout_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  the raw interrupt status of hp core0  ibus timeout
+         */
+        uint32_t core0_ibus_timeout_int_raw:1;
+        /** core1_ibus_timeout_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  the raw interrupt status of hp core1  ibus timeout
+         */
+        uint32_t core1_ibus_timeout_int_raw:1;
+        /** core0_dbus_timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  the raw interrupt status of hp core0  dbus timeout
+         */
+        uint32_t core0_dbus_timeout_int_raw:1;
+        /** core1_dbus_timeout_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  the raw interrupt status of hp core1  dbus timeout
+         */
+        uint32_t core1_dbus_timeout_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_core_timeout_int_raw_reg_t;
+
+/** Type of core_timeout_int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of hp core0  ahb timeout
+         */
+        uint32_t core0_ahb_timeout_int_st:1;
+        /** core1_ahb_timeout_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of hp core1  ahb timeout
+         */
+        uint32_t core1_ahb_timeout_int_st:1;
+        /** core0_ibus_timeout_int_st : RO; bitpos: [2]; default: 0;
+         *  the masked interrupt status of hp core0  ibus timeout
+         */
+        uint32_t core0_ibus_timeout_int_st:1;
+        /** core1_ibus_timeout_int_st : RO; bitpos: [3]; default: 0;
+         *  the masked interrupt status of hp core1  ibus timeout
+         */
+        uint32_t core1_ibus_timeout_int_st:1;
+        /** core0_dbus_timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  the masked interrupt status of hp core0  dbus timeout
+         */
+        uint32_t core0_dbus_timeout_int_st:1;
+        /** core1_dbus_timeout_int_st : RO; bitpos: [5]; default: 0;
+         *  the masked interrupt status of hp core1  dbus timeout
+         */
+        uint32_t core1_dbus_timeout_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_core_timeout_int_st_reg_t;
+
+/** Type of core_timeout_int_ena register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable hp_system_core0_ahb_timeout int
+         */
+        uint32_t core0_ahb_timeout_int_ena:1;
+        /** core1_ahb_timeout_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable hp_system_core1_ahb_timeout int
+         */
+        uint32_t core1_ahb_timeout_int_ena:1;
+        /** core0_ibus_timeout_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable hp_system_core0_ibus_timeout int
+         */
+        uint32_t core0_ibus_timeout_int_ena:1;
+        /** core1_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable hp_system_core1_ibus_timeout int
+         */
+        uint32_t core1_ibus_timeout_int_ena:1;
+        /** core0_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable hp_system_core0_dbus_timeout int
+         */
+        uint32_t core0_dbus_timeout_int_ena:1;
+        /** core1_dbus_timeout_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable hp_system_core1_dbus_timeout int
+         */
+        uint32_t core1_dbus_timeout_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_core_timeout_int_ena_reg_t;
+
+/** Type of core_timeout_int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** core0_ahb_timeout_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear hp_system_core0_ahb_timeout int
+         */
+        uint32_t core0_ahb_timeout_int_clr:1;
+        /** core1_ahb_timeout_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear hp_system_core1_ahb_timeout int
+         */
+        uint32_t core1_ahb_timeout_int_clr:1;
+        /** core0_ibus_timeout_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear hp_system_core0_ibus_timeout int
+         */
+        uint32_t core0_ibus_timeout_int_clr:1;
+        /** core1_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear hp_system_core1_ibus_timeout int
+         */
+        uint32_t core1_ibus_timeout_int_clr:1;
+        /** core0_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear hp_system_core0_dbus_timeout int
+         */
+        uint32_t core0_dbus_timeout_int_clr:1;
+        /** core1_dbus_timeout_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear hp_system_core1_dbus_timeout int
+         */
+        uint32_t core1_dbus_timeout_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_core_timeout_int_clr_reg_t;
+
+
+/** Group: hp_system_L2_MEM_ERR_RESP_CTRL_REG */
+/** Type of l2_mem_err_resp_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** l2_mem_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on l2mem error response
+         */
+        uint32_t l2_mem_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_l2_mem_err_resp_ctrl_reg_t;
+
+
+/** Group: hp_system_L2_MEM_AHB_BUFFER_CTRL_REG */
+/** Type of l2_mem_ahb_buffer_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** l2_mem_ahb_wrbuffer_en : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to turn on l2mem ahb wr buffer
+         */
+        uint32_t l2_mem_ahb_wrbuffer_en:1;
+        /** l2_mem_ahb_rdbuffer_en : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to turn on l2mem ahb rd buffer
+         */
+        uint32_t l2_mem_ahb_rdbuffer_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_l2_mem_ahb_buffer_ctrl_reg_t;
+
+
+/** Group: hp_system_CORE_DMACTIVE_LPCORE_REG */
+/** Type of core_dmactive_lpcore register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_dmactive_lpcore : RO; bitpos: [0]; default: 0;
+         *  hp core dmactive_lpcore value
+         */
+        uint32_t core_dmactive_lpcore:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_core_dmactive_lpcore_reg_t;
+
+
+/** Group: control registers */
+/** Type of core_err_resp_dis register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_err_resp_dis : R/W; bitpos: [2:0]; default: 0;
+         *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
+         *  disable ahb err resp.
+         */
+        uint32_t core_err_resp_dis:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_core_err_resp_dis_reg_t;
+
+
+/** Group: HP GPIO O HYS CTRL0 REG */
+/** Type of gpio_o_hys_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hys_low : R/W; bitpos: [31:0]; default: 0;
+         *  hys control for gpio47~16
+         */
+        uint32_t reg_gpio_0_hys_low:32;
+    };
+    uint32_t val;
+} hp_system_gpio_o_hys_ctrl0_reg_t;
+
+
+/** Group: HP GPIO O HYS CTRL1 REG */
+/** Type of gpio_o_hys_ctrl1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_gpio_0_hys_high : R/W; bitpos: [8:0]; default: 0;
+         *  hys control for gpio56~48
+         */
+        uint32_t reg_gpio_0_hys_high:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_system_gpio_o_hys_ctrl1_reg_t;
+
+
+typedef struct hp_system_dev_t {
+    volatile hp_system_ver_date_reg_t sys_ver_date;
+    volatile hp_system_clk_en_reg_t clk_en;
+    uint32_t reserved_008[2];
+    volatile hp_system_cpu_int_from_cpu_0_reg_t cpu_int_from_cpu_0;
+    volatile hp_system_cpu_int_from_cpu_1_reg_t cpu_int_from_cpu_1;
+    volatile hp_system_cpu_int_from_cpu_2_reg_t cpu_int_from_cpu_2;
+    volatile hp_system_cpu_int_from_cpu_3_reg_t cpu_int_from_cpu_3;
+    volatile hp_system_cache_clk_config_reg_t cache_clk_config;
+    volatile hp_system_cache_reset_config_reg_t cache_reset_config;
+    uint32_t reserved_028;
+    volatile hp_system_dma_addr_ctrl_reg_t sys_dma_addr_ctrl;
+    uint32_t reserved_030;
+    volatile hp_system_tcm_ram_wrr_config_reg_t tcm_ram_wrr_config;
+    volatile hp_system_tcm_sw_parity_bwe_mask_reg_t tcm_sw_parity_bwe_mask;
+    volatile hp_system_tcm_ram_pwr_ctrl0_reg_t tcm_ram_pwr_ctrl0;
+    volatile hp_system_l2_rom_pwr_ctrl0_reg_t l2_rom_pwr_ctrl0;
+    uint32_t reserved_044[3];
+    volatile hp_system_probea_ctrl_reg_t probea_ctrl;
+    volatile hp_system_probeb_ctrl_reg_t probeb_ctrl;
+    uint32_t reserved_058;
+    volatile hp_system_probe_out_reg_t probe_out;
+    volatile hp_system_l2_mem_ram_pwr_ctrl0_reg_t l2_mem_ram_pwr_ctrl0;
+    volatile hp_system_cpu_corestalled_st_reg_t cpu_corestalled_st;
+    uint32_t reserved_068[2];
+    volatile hp_system_crypto_ctrl_reg_t crypto_ctrl;
+    volatile hp_system_gpio_o_hold_ctrl0_reg_t gpio_o_hold_ctrl0;
+    volatile hp_system_gpio_o_hold_ctrl1_reg_t gpio_o_hold_ctrl1;
+    volatile hp_system_rdn_eco_cs_reg_t sys_rdn_eco_cs;
+    volatile hp_system_cache_apb_postw_en_reg_t cache_apb_postw_en;
+    volatile hp_system_l2_mem_subsize_reg_t l2_mem_subsize;
+    uint32_t reserved_088[5];
+    volatile hp_system_l2_mem_int_raw_reg_t l2_mem_int_raw;
+    volatile hp_system_l2_mem_int_st_reg_t l2_mem_int_st;
+    volatile hp_system_l2_mem_int_ena_reg_t l2_mem_int_ena;
+    volatile hp_system_l2_mem_int_clr_reg_t l2_mem_int_clr;
+    volatile hp_system_l2_mem_l2_ram_ecc_reg_t l2_mem_l2_ram_ecc;
+    volatile hp_system_l2_mem_int_record0_reg_t l2_mem_int_record0;
+    volatile hp_system_l2_mem_int_record1_reg_t l2_mem_int_record1;
+    uint32_t reserved_0b8[3];
+    volatile hp_system_l2_mem_l2_cache_ecc_reg_t l2_mem_l2_cache_ecc;
+    volatile hp_system_l1cache_bus0_id_reg_t l1cache_bus0_id;
+    volatile hp_system_l1cache_bus1_id_reg_t l1cache_bus1_id;
+    uint32_t reserved_0d0[2];
+    volatile hp_system_l2_mem_rdn_eco_cs_reg_t l2_mem_rdn_eco_cs;
+    volatile hp_system_l2_mem_rdn_eco_low_reg_t l2_mem_rdn_eco_low;
+    volatile hp_system_l2_mem_rdn_eco_high_reg_t l2_mem_rdn_eco_high;
+    volatile hp_system_tcm_rdn_eco_cs_reg_t tcm_rdn_eco_cs;
+    volatile hp_system_tcm_rdn_eco_low_reg_t tcm_rdn_eco_low;
+    volatile hp_system_tcm_rdn_eco_high_reg_t tcm_rdn_eco_high;
+    volatile hp_system_gpio_ded_hold_ctrl_reg_t gpio_ded_hold_ctrl;
+    volatile hp_system_l2_mem_sw_ecc_bwe_mask_reg_t l2_mem_sw_ecc_bwe_mask;
+    volatile hp_system_usb20otg_mem_ctrl_reg_t usb20otg_mem_ctrl;
+    volatile hp_system_tcm_int_raw_reg_t tcm_int_raw;
+    volatile hp_system_tcm_int_st_reg_t tcm_int_st;
+    volatile hp_system_tcm_int_ena_reg_t tcm_int_ena;
+    volatile hp_system_tcm_int_clr_reg_t tcm_int_clr;
+    volatile hp_system_tcm_parity_int_record_reg_t tcm_parity_int_record;
+    volatile hp_system_l1_cache_pwr_ctrl_reg_t l1_cache_pwr_ctrl;
+    volatile hp_system_l2_cache_pwr_ctrl_reg_t l2_cache_pwr_ctrl;
+    volatile hp_system_cpu_waiti_conf_reg_t cpu_waiti_conf;
+    volatile hp_system_core_debug_runstall_conf_reg_t sys_core_debug_runstall_conf;
+    volatile hp_system_core_ahb_timeout_reg_t core_ahb_timeout;
+    volatile hp_system_core_ibus_timeout_reg_t core_ibus_timeout;
+    volatile hp_system_core_dbus_timeout_reg_t core_dbus_timeout;
+    uint32_t reserved_12c[3];
+    volatile hp_system_icm_cpu_h2x_cfg_reg_t icm_cpu_h2x_cfg;
+    volatile hp_system_peri1_apb_postw_en_reg_t peri1_apb_postw_en;
+    volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
+    volatile hp_system_apb_sync_postw_en_reg_t sys_apb_sync_postw_en;
+    volatile hp_system_gdma_ctrl_reg_t sys_gdma_ctrl;
+    volatile hp_system_gmac_ctrl0_reg_t sys_gmac_ctrl0;
+    volatile hp_system_gmac_ctrl1_reg_t sys_gmac_ctrl1;
+    volatile hp_system_gmac_ctrl2_reg_t sys_gmac_ctrl2;
+    volatile hp_system_vpu_ctrl_reg_t sys_vpu_ctrl;
+    volatile hp_system_usbotg20_ctrl_reg_t sys_usbotg20_ctrl;
+    volatile hp_system_tcm_err_resp_ctrl_reg_t tcm_err_resp_ctrl;
+    volatile hp_system_l2_mem_refresh_reg_t l2_mem_refresh;
+    volatile hp_system_tcm_init_reg_t tcm_init;
+    volatile hp_system_tcm_parity_check_ctrl_reg_t tcm_parity_check_ctrl;
+    volatile hp_system_design_for_verification0_reg_t design_for_verification0;
+    volatile hp_system_design_for_verification1_reg_t design_for_verification1;
+    uint32_t reserved_178[2];
+    volatile hp_system_psram_flash_addr_interchange_reg_t psram_flash_addr_interchange;
+    uint32_t reserved_184;
+    volatile hp_system_ahb2axi_bresp_err_int_raw_reg_t ahb2axi_bresp_err_int_raw;
+    volatile hp_system_ahb2axi_bresp_err_int_st_reg_t ahb2axi_bresp_err_int_st;
+    volatile hp_system_ahb2axi_bresp_err_int_ena_reg_t ahb2axi_bresp_err_int_ena;
+    volatile hp_system_ahb2axi_bresp_err_int_clr_reg_t ahb2axi_bresp_err_int_clr;
+    volatile hp_system_l2_mem_err_resp_ctrl_reg_t l2_mem_err_resp_ctrl;
+    volatile hp_system_l2_mem_ahb_buffer_ctrl_reg_t l2_mem_ahb_buffer_ctrl;
+    volatile hp_system_core_dmactive_lpcore_reg_t core_dmactive_lpcore;
+    volatile hp_system_core_err_resp_dis_reg_t core_err_resp_dis;
+    volatile hp_system_core_timeout_int_raw_reg_t core_timeout_int_raw;
+    volatile hp_system_core_timeout_int_st_reg_t core_timeout_int_st;
+    volatile hp_system_core_timeout_int_ena_reg_t core_timeout_int_ena;
+    volatile hp_system_core_timeout_int_clr_reg_t core_timeout_int_clr;
+    uint32_t reserved_1b8[2];
+    volatile hp_system_gpio_o_hys_ctrl0_reg_t gpio_o_hys_ctrl0;
+    volatile hp_system_gpio_o_hys_ctrl1_reg_t gpio_o_hys_ctrl1;
+    uint32_t reserved_1c8[2];
+    volatile hp_system_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
+    volatile hp_system_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
+    volatile hp_system_rng_cfg_reg_t rng_cfg;
+    volatile hp_system_uart_pd_ctrl_reg_t uart_pd_ctrl;
+    volatile hp_system_peri_mem_clk_force_on_reg_t peri_mem_clk_force_on;
+} hp_system_dev_t;
+
+extern hp_system_dev_t HP_SYSTEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_system_dev_t) == 0x1e4, "Invalid size of hp_system_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/huk_reg.h b/components/soc/esp32p4/register/soc/huk_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/huk_reg.h
rename to components/soc/esp32p4/register/soc/huk_reg.h
diff --git a/components/soc/esp32p4/include/soc/huk_struct.h b/components/soc/esp32p4/register/soc/huk_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/huk_struct.h
rename to components/soc/esp32p4/register/soc/huk_struct.h
diff --git a/components/soc/esp32p4/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32p4/register/soc/i2c_ana_mst_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/i2c_ana_mst_reg.h
rename to components/soc/esp32p4/register/soc/i2c_ana_mst_reg.h
diff --git a/components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h b/components/soc/esp32p4/register/soc/i2c_ana_mst_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/i2c_ana_mst_struct.h
rename to components/soc/esp32p4/register/soc/i2c_ana_mst_struct.h
diff --git a/components/soc/esp32p4/include/soc/i2c_reg.h b/components/soc/esp32p4/register/soc/i2c_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/i2c_reg.h
rename to components/soc/esp32p4/register/soc/i2c_reg.h
diff --git a/components/soc/esp32p4/include/soc/i2c_struct.h b/components/soc/esp32p4/register/soc/i2c_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/i2c_struct.h
rename to components/soc/esp32p4/register/soc/i2c_struct.h
diff --git a/components/soc/esp32p4/register/soc/i2s_reg.h b/components/soc/esp32p4/register/soc/i2s_reg.h
new file mode 100644
index 00000000000..88ada789e78
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/i2s_reg.h
@@ -0,0 +1,1268 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2S_INT_RAW_REG register
+ *  I2S interrupt raw register, valid in level.
+ */
+#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0xc)
+/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_RAW    (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
+#define I2S_RX_DONE_INT_RAW_V  0x00000001U
+#define I2S_RX_DONE_INT_RAW_S  0
+/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_RAW    (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
+#define I2S_TX_DONE_INT_RAW_V  0x00000001U
+#define I2S_TX_DONE_INT_RAW_S  1
+/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_RAW    (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
+#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_RX_HUNG_INT_RAW_S  2
+/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_RAW    (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
+#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_TX_HUNG_INT_RAW_S  3
+
+/** I2S_INT_ST_REG register
+ *  I2S interrupt status register.
+ */
+#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x10)
+/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ST    (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
+#define I2S_RX_DONE_INT_ST_V  0x00000001U
+#define I2S_RX_DONE_INT_ST_S  0
+/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ST    (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
+#define I2S_TX_DONE_INT_ST_V  0x00000001U
+#define I2S_TX_DONE_INT_ST_S  1
+/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ST    (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
+#define I2S_RX_HUNG_INT_ST_V  0x00000001U
+#define I2S_RX_HUNG_INT_ST_S  2
+/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ST    (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
+#define I2S_TX_HUNG_INT_ST_V  0x00000001U
+#define I2S_TX_HUNG_INT_ST_S  3
+
+/** I2S_INT_ENA_REG register
+ *  I2S interrupt enable register.
+ */
+#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x14)
+/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ENA    (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
+#define I2S_RX_DONE_INT_ENA_V  0x00000001U
+#define I2S_RX_DONE_INT_ENA_S  0
+/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ENA    (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
+#define I2S_TX_DONE_INT_ENA_V  0x00000001U
+#define I2S_TX_DONE_INT_ENA_S  1
+/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ENA    (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
+#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_RX_HUNG_INT_ENA_S  2
+/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ENA    (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
+#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_TX_HUNG_INT_ENA_S  3
+
+/** I2S_INT_CLR_REG register
+ *  I2S interrupt clear register.
+ */
+#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x18)
+/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_CLR    (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
+#define I2S_RX_DONE_INT_CLR_V  0x00000001U
+#define I2S_RX_DONE_INT_CLR_S  0
+/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_CLR    (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
+#define I2S_TX_DONE_INT_CLR_V  0x00000001U
+#define I2S_TX_DONE_INT_CLR_S  1
+/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_CLR    (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
+#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_RX_HUNG_INT_CLR_S  2
+/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_CLR    (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
+#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_TX_HUNG_INT_CLR_S  3
+
+/** I2S_RX_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x20)
+/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset receiver
+ */
+#define I2S_RX_RESET    (BIT(0))
+#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
+#define I2S_RX_RESET_V  0x00000001U
+#define I2S_RX_RESET_S  0
+/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Rx AFIFO
+ */
+#define I2S_RX_FIFO_RESET    (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
+#define I2S_RX_FIFO_RESET_V  0x00000001U
+#define I2S_RX_FIFO_RESET_S  1
+/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start receiving data
+ */
+#define I2S_RX_START    (BIT(2))
+#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
+#define I2S_RX_START_V  0x00000001U
+#define I2S_RX_START_S  2
+/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave receiver mode
+ */
+#define I2S_RX_SLAVE_MOD    (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
+#define I2S_RX_SLAVE_MOD_V  0x00000001U
+#define I2S_RX_SLAVE_MOD_S  3
+/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+ *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+ */
+#define I2S_RX_STOP_MODE    0x00000003U
+#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
+#define I2S_RX_STOP_MODE_V  0x00000003U
+#define I2S_RX_STOP_MODE_S  4
+/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable receiver  in mono mode
+ */
+#define I2S_RX_MONO    (BIT(6))
+#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
+#define I2S_RX_MONO_V  0x00000001U
+#define I2S_RX_MONO_S  6
+/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+ */
+#define I2S_RX_BIG_ENDIAN    (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
+#define I2S_RX_BIG_ENDIAN_V  0x00000001U
+#define I2S_RX_BIG_ENDIAN_S  7
+/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_RX_UPDATE    (BIT(8))
+#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
+#define I2S_RX_UPDATE_V  0x00000001U
+#define I2S_RX_UPDATE_S  8
+/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+ *  channel data value is valid in I2S RX mono mode.
+ */
+#define I2S_RX_MONO_FST_VLD    (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
+#define I2S_RX_MONO_FST_VLD_V  0x00000001U
+#define I2S_RX_MONO_FST_VLD_S  9
+/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
+ *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_RX_PCM_CONF    0x00000003U
+#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
+#define I2S_RX_PCM_CONF_V  0x00000003U
+#define I2S_RX_PCM_CONF_S  10
+/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass Compress/Decompress module for received data.
+ */
+#define I2S_RX_PCM_BYPASS    (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
+#define I2S_RX_PCM_BYPASS_V  0x00000001U
+#define I2S_RX_PCM_BYPASS_S  12
+/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable receiver in Phillips standard mode
+ */
+#define I2S_RX_MSB_SHIFT    (BIT(13))
+#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
+#define I2S_RX_MSB_SHIFT_V  0x00000001U
+#define I2S_RX_MSB_SHIFT_S  13
+/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+ */
+#define I2S_RX_LEFT_ALIGN    (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
+#define I2S_RX_LEFT_ALIGN_V  0x00000001U
+#define I2S_RX_LEFT_ALIGN_S  15
+/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+ */
+#define I2S_RX_24_FILL_EN    (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
+#define I2S_RX_24_FILL_EN_V  0x00000001U
+#define I2S_RX_24_FILL_EN_S  16
+/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+ *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+ */
+#define I2S_RX_WS_IDLE_POL    (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
+#define I2S_RX_WS_IDLE_POL_V  0x00000001U
+#define I2S_RX_WS_IDLE_POL_S  17
+/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+ *  is received first.
+ */
+#define I2S_RX_BIT_ORDER    (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
+#define I2S_RX_BIT_ORDER_V  0x00000001U
+#define I2S_RX_BIT_ORDER_S  18
+/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_TDM_EN    (BIT(19))
+#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
+#define I2S_RX_TDM_EN_V  0x00000001U
+#define I2S_RX_TDM_EN_S  19
+/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_PDM_EN    (BIT(20))
+#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
+#define I2S_RX_PDM_EN_V  0x00000001U
+#define I2S_RX_PDM_EN_S  20
+/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in receiver mode.
+ */
+#define I2S_RX_BCK_DIV_NUM    0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
+#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_S  21
+
+/** I2S_TX_CONF_REG register
+ *  I2S TX configure register
+ */
+#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x24)
+/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset transmitter
+ */
+#define I2S_TX_RESET    (BIT(0))
+#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
+#define I2S_TX_RESET_V  0x00000001U
+#define I2S_TX_RESET_S  0
+/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Tx AFIFO
+ */
+#define I2S_TX_FIFO_RESET    (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
+#define I2S_TX_FIFO_RESET_V  0x00000001U
+#define I2S_TX_FIFO_RESET_S  1
+/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start transmitting data
+ */
+#define I2S_TX_START    (BIT(2))
+#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
+#define I2S_TX_START_V  0x00000001U
+#define I2S_TX_START_S  2
+/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave transmitter mode
+ */
+#define I2S_TX_SLAVE_MOD    (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
+#define I2S_TX_SLAVE_MOD_V  0x00000001U
+#define I2S_TX_SLAVE_MOD_S  3
+/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+ */
+#define I2S_TX_STOP_EN    (BIT(4))
+#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
+#define I2S_TX_STOP_EN_V  0x00000001U
+#define I2S_TX_STOP_EN_S  4
+/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
+ *  1: The value of Left channel data is equal to the value of right channel data in
+ *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+ *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+ */
+#define I2S_TX_CHAN_EQUAL    (BIT(5))
+#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
+#define I2S_TX_CHAN_EQUAL_V  0x00000001U
+#define I2S_TX_CHAN_EQUAL_S  5
+/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter in mono mode
+ */
+#define I2S_TX_MONO    (BIT(6))
+#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
+#define I2S_TX_MONO_V  0x00000001U
+#define I2S_TX_MONO_S  6
+/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+ *  value.
+ */
+#define I2S_TX_BIG_ENDIAN    (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
+#define I2S_TX_BIG_ENDIAN_V  0x00000001U
+#define I2S_TX_BIG_ENDIAN_S  7
+/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_TX_UPDATE    (BIT(8))
+#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
+#define I2S_TX_UPDATE_V  0x00000001U
+#define I2S_TX_UPDATE_S  8
+/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+ *  channel data value is valid in I2S TX mono mode.
+ */
+#define I2S_TX_MONO_FST_VLD    (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
+#define I2S_TX_MONO_FST_VLD_V  0x00000001U
+#define I2S_TX_MONO_FST_VLD_S  9
+/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
+ *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_TX_PCM_CONF    0x00000003U
+#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
+#define I2S_TX_PCM_CONF_V  0x00000003U
+#define I2S_TX_PCM_CONF_S  10
+/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+ */
+#define I2S_TX_PCM_BYPASS    (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
+#define I2S_TX_PCM_BYPASS_V  0x00000001U
+#define I2S_TX_PCM_BYPASS_S  12
+/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable transmitter in Phillips standard mode
+ */
+#define I2S_TX_MSB_SHIFT    (BIT(13))
+#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
+#define I2S_TX_MSB_SHIFT_V  0x00000001U
+#define I2S_TX_MSB_SHIFT_S  13
+/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
+ *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+ *  generate pos/neg edge in master mode.
+ */
+#define I2S_TX_BCK_NO_DLY    (BIT(14))
+#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
+#define I2S_TX_BCK_NO_DLY_V  0x00000001U
+#define I2S_TX_BCK_NO_DLY_S  14
+/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+ */
+#define I2S_TX_LEFT_ALIGN    (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
+#define I2S_TX_LEFT_ALIGN_V  0x00000001U
+#define I2S_TX_LEFT_ALIGN_S  15
+/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+ */
+#define I2S_TX_24_FILL_EN    (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
+#define I2S_TX_24_FILL_EN_V  0x00000001U
+#define I2S_TX_24_FILL_EN_S  16
+/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+ *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+ */
+#define I2S_TX_WS_IDLE_POL    (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
+#define I2S_TX_WS_IDLE_POL_V  0x00000001U
+#define I2S_TX_WS_IDLE_POL_S  17
+/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+ *  sent first.
+ */
+#define I2S_TX_BIT_ORDER    (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
+#define I2S_TX_BIT_ORDER_V  0x00000001U
+#define I2S_TX_BIT_ORDER_S  18
+/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_TDM_EN    (BIT(19))
+#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
+#define I2S_TX_TDM_EN_V  0x00000001U
+#define I2S_TX_TDM_EN_S  19
+/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_PDM_EN    (BIT(20))
+#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
+#define I2S_TX_PDM_EN_V  0x00000001U
+#define I2S_TX_PDM_EN_S  20
+/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in transmitter mode.
+ */
+#define I2S_TX_BCK_DIV_NUM    0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
+#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_S  21
+/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
+ *  I2S transmitter channel mode configuration bits.
+ */
+#define I2S_TX_CHAN_MOD    0x00000007U
+#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
+#define I2S_TX_CHAN_MOD_V  0x00000007U
+#define I2S_TX_CHAN_MOD_S  27
+/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
+ *  Enable signal loop back mode with transmitter module and receiver module sharing
+ *  the same WS and BCK signals.
+ */
+#define I2S_SIG_LOOPBACK    (BIT(30))
+#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
+#define I2S_SIG_LOOPBACK_V  0x00000001U
+#define I2S_SIG_LOOPBACK_S  30
+
+/** I2S_RX_CONF1_REG register
+ *  I2S RX configure register 1
+ */
+#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x28)
+/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
+#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_S  0
+/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+ *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_RX_BITS_MOD    0x0000001FU
+#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
+#define I2S_RX_BITS_MOD_V  0x0000001FU
+#define I2S_RX_BITS_MOD_S  14
+/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Rx half sample bits -1.
+ */
+#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_S  19
+/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Rx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
+#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_CONF1_REG register
+ *  I2S TX configure register 1
+ */
+#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x2c)
+/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
+#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_S  0
+/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+ *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_TX_BITS_MOD    0x0000001FU
+#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
+#define I2S_TX_BITS_MOD_V  0x0000001FU
+#define I2S_TX_BITS_MOD_S  14
+/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Tx half sample bits -1.
+ */
+#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_S  19
+/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Tx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
+#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_PCM2PDM_CONF_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x40)
+/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
+ *  I2S TX PDM OSR2 value
+ */
+#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
+#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
+ *  I2S TX PDM prescale for sigmadelta
+ */
+#define I2S_TX_PDM_PRESCALE    0x000000FFU
+#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
+#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
+#define I2S_TX_PDM_PRESCALE_S  5
+/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
+ *  I2S TX PDM sigmadelta dither2 value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
+ *  I2S TX PDM sigmadelta dither value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
+ *  I2S TX PDM dac mode enable
+ */
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
+ *  I2S TX PDM dac 2channel enable
+ */
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
+ *  I2S TX PDM Converter enable
+ */
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
+#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
+#define I2S_PCM2PDM_CONV_EN_S  25
+
+/** I2S_TX_PCM2PDM_CONF1_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44)
+/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
+ *  I2S TX PDM Fp
+ */
+#define I2S_TX_PDM_FP    0x000003FFU
+#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
+#define I2S_TX_PDM_FP_V  0x000003FFU
+#define I2S_TX_PDM_FP_S  0
+/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
+ *  I2S TX PDM Fs
+ */
+#define I2S_TX_PDM_FS    0x000003FFU
+#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
+#define I2S_TX_PDM_FS_V  0x000003FFU
+#define I2S_TX_PDM_FS_S  10
+/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
+#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
+#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+
+/** I2S_RX_PDM2PCM_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_PDM2PCM_CONF_REG(i) (REG_I2S_BASE(i) + 0x48)
+/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable PDM2PCM RX mode. 0: DIsable.
+ */
+#define I2S_RX_PDM2PCM_EN    (BIT(19))
+#define I2S_RX_PDM2PCM_EN_M  (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
+#define I2S_RX_PDM2PCM_EN_V  0x00000001U
+#define I2S_RX_PDM2PCM_EN_S  19
+/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
+ *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+ *  sampling rate is 128. 0: down sampling rate is 64.
+ */
+#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
+#define I2S_RX_PDM_SINC_DSR_16_EN_M  (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
+#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
+#define I2S_RX_PDM_SINC_DSR_16_EN_S  20
+/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
+ *  Configure PDM RX amplify number.
+ */
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
+/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
+ *  I2S PDM RX bypass hp filter or not.
+ */
+#define I2S_RX_PDM_HP_BYPASS    (BIT(25))
+#define I2S_RX_PDM_HP_BYPASS_M  (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
+#define I2S_RX_PDM_HP_BYPASS_V  0x00000001U
+#define I2S_RX_PDM_HP_BYPASS_S  25
+/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_RX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_RX_IIR_HP_MULT12_5_M  (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
+#define I2S_RX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_RX_IIR_HP_MULT12_5_S  26
+/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_RX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_RX_IIR_HP_MULT12_0_M  (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
+#define I2S_RX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_RX_IIR_HP_MULT12_0_S  29
+
+/** I2S_RX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x50)
+/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
+#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
+#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
+#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
+#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
+#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
+#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
+#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
+#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+
+/** I2S_TX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x54)
+/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
+#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN0_EN_S  0
+/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
+#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
+#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
+#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
+#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
+#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
+#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
+#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
+#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
+#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
+#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
+#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
+#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
+#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
+#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
+#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
+ *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+ *  only the data of the enabled channels is sent, then this bit should be set. Clear
+ *  it when all the data stored in DMA TX buffer is for enabled channels.
+ */
+#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+
+/** I2S_RX_TIMING_REG register
+ *  I2S RX timing control register
+ */
+#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x58)
+/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD_IN_DM    0x00000003U
+#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
+#define I2S_RX_SD_IN_DM_V  0x00000003U
+#define I2S_RX_SD_IN_DM_S  0
+/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD1_IN_DM    0x00000003U
+#define I2S_RX_SD1_IN_DM_M  (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S)
+#define I2S_RX_SD1_IN_DM_V  0x00000003U
+#define I2S_RX_SD1_IN_DM_S  4
+/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0;
+ *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD2_IN_DM    0x00000003U
+#define I2S_RX_SD2_IN_DM_M  (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S)
+#define I2S_RX_SD2_IN_DM_V  0x00000003U
+#define I2S_RX_SD2_IN_DM_S  8
+/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0;
+ *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD3_IN_DM    0x00000003U
+#define I2S_RX_SD3_IN_DM_M  (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S)
+#define I2S_RX_SD3_IN_DM_V  0x00000003U
+#define I2S_RX_SD3_IN_DM_S  12
+/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_OUT_DM    0x00000003U
+#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
+#define I2S_RX_WS_OUT_DM_V  0x00000003U
+#define I2S_RX_WS_OUT_DM_S  16
+/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_OUT_DM    0x00000003U
+#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
+#define I2S_RX_BCK_OUT_DM_V  0x00000003U
+#define I2S_RX_BCK_OUT_DM_S  20
+/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_IN_DM    0x00000003U
+#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
+#define I2S_RX_WS_IN_DM_V  0x00000003U
+#define I2S_RX_WS_IN_DM_S  24
+/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_IN_DM    0x00000003U
+#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
+#define I2S_RX_BCK_IN_DM_V  0x00000003U
+#define I2S_RX_BCK_IN_DM_S  28
+
+/** I2S_TX_TIMING_REG register
+ *  I2S TX timing control register
+ */
+#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x5c)
+/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD_OUT_DM    0x00000003U
+#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
+#define I2S_TX_SD_OUT_DM_V  0x00000003U
+#define I2S_TX_SD_OUT_DM_S  0
+/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD1_OUT_DM    0x00000003U
+#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
+#define I2S_TX_SD1_OUT_DM_V  0x00000003U
+#define I2S_TX_SD1_OUT_DM_S  4
+/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_OUT_DM    0x00000003U
+#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
+#define I2S_TX_WS_OUT_DM_V  0x00000003U
+#define I2S_TX_WS_OUT_DM_S  16
+/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_OUT_DM    0x00000003U
+#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
+#define I2S_TX_BCK_OUT_DM_V  0x00000003U
+#define I2S_TX_BCK_OUT_DM_S  20
+/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_IN_DM    0x00000003U
+#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
+#define I2S_TX_WS_IN_DM_V  0x00000003U
+#define I2S_TX_WS_IN_DM_S  24
+/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_IN_DM    0x00000003U
+#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
+#define I2S_TX_BCK_IN_DM_V  0x00000003U
+#define I2S_TX_BCK_IN_DM_S  28
+
+/** I2S_LC_HUNG_CONF_REG register
+ *  I2S HUNG configure register.
+ */
+#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x60)
+/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ *  when fifo hung counter is equal to this value
+ */
+#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
+#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_S  0
+/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  The bits are used to scale tick counter threshold. The tick counter is reset when
+ *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+ */
+#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  The enable bit for FIFO timeout
+ */
+#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+
+/** I2S_RXEOF_NUM_REG register
+ *  I2S RX data number control register.
+ */
+#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x64)
+/** I2S_RX_EOF_NUM : R/W; bitpos: [11:0]; default: 64;
+ *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+ *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+ */
+#define I2S_RX_EOF_NUM    0x00000FFFU
+#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
+#define I2S_RX_EOF_NUM_V  0x00000FFFU
+#define I2S_RX_EOF_NUM_S  0
+
+/** I2S_CONF_SIGLE_DATA_REG register
+ *  I2S signal data register
+ */
+#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x68)
+/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The configured constant channel data to be sent out.
+ */
+#define I2S_SINGLE_DATA    0xFFFFFFFFU
+#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
+#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
+#define I2S_SINGLE_DATA_S  0
+
+/** I2S_STATE_REG register
+ *  I2S TX status register
+ */
+#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x6c)
+/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
+ *  1: i2s_tx is idle state. 0: i2s_tx is working.
+ */
+#define I2S_TX_IDLE    (BIT(0))
+#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
+#define I2S_TX_IDLE_V  0x00000001U
+#define I2S_TX_IDLE_S  0
+
+/** I2S_ETM_CONF_REG register
+ *  I2S ETM configure register
+ */
+#define I2S_ETM_CONF_REG(i) (REG_I2S_BASE(i) + 0x70)
+/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [9:0]; default: 64;
+ *  I2S ETM send x words event. When sending word number of
+ *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_TX_SEND_WORD_NUM    0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
+#define I2S_ETM_TX_SEND_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_TX_SEND_WORD_NUM_S  0
+/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [19:10]; default: 64;
+ *  I2S ETM receive x words event. When receiving word number of
+ *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x000003FFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  10
+
+/** I2S_FIFO_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_FIFO_CNT_REG(i) (REG_I2S_BASE(i) + 0x74)
+/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx fifo counter value.
+ */
+#define I2S_TX_FIFO_CNT    0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_M  (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S)
+#define I2S_TX_FIFO_CNT_V  0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_S  0
+/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx fifo counter.
+ */
+#define I2S_TX_FIFO_CNT_RST    (BIT(31))
+#define I2S_TX_FIFO_CNT_RST_M  (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S)
+#define I2S_TX_FIFO_CNT_RST_V  0x00000001U
+#define I2S_TX_FIFO_CNT_RST_S  31
+
+/** I2S_BCK_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_BCK_CNT_REG(i) (REG_I2S_BASE(i) + 0x78)
+/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx bck counter value.
+ */
+#define I2S_TX_BCK_CNT    0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_M  (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S)
+#define I2S_TX_BCK_CNT_V  0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_S  0
+/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx bck counter.
+ */
+#define I2S_TX_BCK_CNT_RST    (BIT(31))
+#define I2S_TX_BCK_CNT_RST_M  (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S)
+#define I2S_TX_BCK_CNT_RST_V  0x00000001U
+#define I2S_TX_BCK_CNT_RST_S  31
+
+/** I2S_CLK_GATE_REG register
+ *  Clock gate register
+ */
+#define I2S_CLK_GATE_REG(i) (REG_I2S_BASE(i) + 0x7c)
+/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit to enable clock gate
+ */
+#define I2S_CLK_EN    (BIT(0))
+#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
+#define I2S_CLK_EN_V  0x00000001U
+#define I2S_CLK_EN_S  0
+
+/** I2S_DATE_REG register
+ *  Version control register
+ */
+#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x80)
+/** I2S_DATE : R/W; bitpos: [27:0]; default: 36713024;
+ *  I2S version control register
+ */
+#define I2S_DATE    0x0FFFFFFFU
+#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
+#define I2S_DATE_V  0x0FFFFFFFU
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/i2s_struct.h b/components/soc/esp32p4/register/soc/i2s_struct.h
new file mode 100644
index 00000000000..191b9dc6a1b
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/i2s_struct.h
@@ -0,0 +1,1012 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        uint32_t reserved_14:1;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t rx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:8;
+        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of rx_pdm2pcm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_5:3;
+        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_0:3;
+    };
+    uint32_t val;
+} i2s_rx_pdm2pcm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0;
+         *  I2S TX PDM bypass hp filter or not. The option has been removed.
+         */
+        uint32_t tx_pdm_hp_bypass:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rx_eof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [11:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] +
+         *  1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_rx_eof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [30]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t tx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:8;
+        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:2;
+        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd1_in_dm:2;
+        uint32_t reserved_6:2;
+        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
+         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd2_in_dm:2;
+        uint32_t reserved_10:2;
+        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
+         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd3_in_dm:2;
+        uint32_t reserved_14:2;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_single_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_single_data_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:10;
+        /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: Sync counter registers */
+/** Type of fifo_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx fifo counter value.
+         */
+        uint32_t tx_fifo_cnt:31;
+        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx fifo counter.
+         */
+        uint32_t tx_fifo_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_fifo_cnt_reg_t;
+
+/** Type of bck_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx bck counter value.
+         */
+        uint32_t tx_bck_cnt:31;
+        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx bck counter.
+         */
+        uint32_t tx_bck_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_bck_cnt_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 36713024;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    uint32_t reserved_030[4];
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
+    uint32_t reserved_04c;
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rx_eof_num_reg_t rx_eof_num;
+    volatile i2s_conf_single_data_reg_t conf_single_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    volatile i2s_fifo_cnt_reg_t fifo_cnt;
+    volatile i2s_bck_cnt_reg_t bck_cnt;
+    volatile i2s_clk_gate_reg_t clk_gate;
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+extern i2s_dev_t I2S0;
+extern i2s_dev_t I2S1;
+extern i2s_dev_t I2S2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/i3c_mst_mem_reg.h b/components/soc/esp32p4/register/soc/i3c_mst_mem_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/i3c_mst_mem_reg.h
rename to components/soc/esp32p4/register/soc/i3c_mst_mem_reg.h
diff --git a/components/soc/esp32p4/include/soc/i3c_mst_mem_struct.h b/components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/i3c_mst_mem_struct.h
rename to components/soc/esp32p4/register/soc/i3c_mst_mem_struct.h
diff --git a/components/soc/esp32p4/include/soc/i3c_mst_reg.h b/components/soc/esp32p4/register/soc/i3c_mst_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/i3c_mst_reg.h
rename to components/soc/esp32p4/register/soc/i3c_mst_reg.h
diff --git a/components/soc/esp32p4/include/soc/i3c_mst_struct.h b/components/soc/esp32p4/register/soc/i3c_mst_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/i3c_mst_struct.h
rename to components/soc/esp32p4/register/soc/i3c_mst_struct.h
diff --git a/components/soc/esp32p4/include/soc/i3c_slv_reg.h b/components/soc/esp32p4/register/soc/i3c_slv_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/i3c_slv_reg.h
rename to components/soc/esp32p4/register/soc/i3c_slv_reg.h
index a5684d88e0e..335ec44fc20 100644
--- a/components/soc/esp32p4/include/soc/i3c_slv_reg.h
+++ b/components/soc/esp32p4/register/soc/i3c_slv_reg.h
@@ -103,7 +103,7 @@ extern "C" {
 #define I3C_SLV_STNOTSTOP_V  0x00000001U
 #define I3C_SLV_STNOTSTOP_S  0
 /** I3C_SLV_STMSG : RO; bitpos: [1]; default: 0;
- *  Is 1 if this bus Slave is listening to the bus traffic or repsonding, If
+ *  Is 1 if this bus Slave is listening to the bus traffic or responding, If
  *  STNOSTOP=1, then this will be 0 when a non-matching address seen until next
  *  respeated START it STOP.
  */
diff --git a/components/soc/esp32p4/include/soc/i3c_slv_struct.h b/components/soc/esp32p4/register/soc/i3c_slv_struct.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/i3c_slv_struct.h
rename to components/soc/esp32p4/register/soc/i3c_slv_struct.h
index 125ca7d6277..7df80af8942 100644
--- a/components/soc/esp32p4/include/soc/i3c_slv_struct.h
+++ b/components/soc/esp32p4/register/soc/i3c_slv_struct.h
@@ -83,7 +83,7 @@ typedef union {
          */
         uint32_t stnotstop:1;
         /** stmsg : RO; bitpos: [1]; default: 0;
-         *  Is 1 if this bus Slave is listening to the bus traffic or repsonding, If
+         *  Is 1 if this bus Slave is listening to the bus traffic or responding, If
          *  STNOSTOP=1, then this will be 0 when a non-matching address seen until next
          *  respeated START it STOP.
          */
@@ -459,10 +459,10 @@ typedef union {
  */
 typedef union {
     struct {
-        /** capablities : RO; bitpos: [31:0]; default: 2081684508;
+        /** capabilities : RO; bitpos: [31:0]; default: 2081684508;
          *  NA
          */
-        uint32_t capablities:32;
+        uint32_t capabilities:32;
     };
     uint32_t val;
 } i3c_slv_capabilities_reg_t;
diff --git a/components/soc/esp32p4/include/soc/icm_sys_qos_reg.h b/components/soc/esp32p4/register/soc/icm_sys_qos_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/icm_sys_qos_reg.h
rename to components/soc/esp32p4/register/soc/icm_sys_qos_reg.h
diff --git a/components/soc/esp32p4/include/soc/icm_sys_qos_struct.h b/components/soc/esp32p4/register/soc/icm_sys_qos_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/icm_sys_qos_struct.h
rename to components/soc/esp32p4/register/soc/icm_sys_qos_struct.h
diff --git a/components/soc/esp32p4/include/soc/icm_sys_reg.h b/components/soc/esp32p4/register/soc/icm_sys_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/icm_sys_reg.h
rename to components/soc/esp32p4/register/soc/icm_sys_reg.h
diff --git a/components/soc/esp32p4/include/soc/icm_sys_struct.h b/components/soc/esp32p4/register/soc/icm_sys_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/icm_sys_struct.h
rename to components/soc/esp32p4/register/soc/icm_sys_struct.h
diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_reg.h b/components/soc/esp32p4/register/soc/interrupt_core0_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/interrupt_core0_reg.h
rename to components/soc/esp32p4/register/soc/interrupt_core0_reg.h
diff --git a/components/soc/esp32p4/include/soc/interrupt_core0_struct.h b/components/soc/esp32p4/register/soc/interrupt_core0_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/interrupt_core0_struct.h
rename to components/soc/esp32p4/register/soc/interrupt_core0_struct.h
diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_reg.h b/components/soc/esp32p4/register/soc/interrupt_core1_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/interrupt_core1_reg.h
rename to components/soc/esp32p4/register/soc/interrupt_core1_reg.h
diff --git a/components/soc/esp32p4/include/soc/interrupt_core1_struct.h b/components/soc/esp32p4/register/soc/interrupt_core1_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/interrupt_core1_struct.h
rename to components/soc/esp32p4/register/soc/interrupt_core1_struct.h
diff --git a/components/soc/esp32p4/register/soc/io_mux_reg.h b/components/soc/esp32p4/register/soc/io_mux_reg.h
new file mode 100644
index 00000000000..d7eba33c2cf
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/io_mux_reg.h
@@ -0,0 +1,525 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "soc/soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+
+#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_PAD_GPIO0
+#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_PAD_GPIO1
+#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_PAD_GPIO2
+#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_PAD_GPIO3
+#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_PAD_GPIO4
+#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_PAD_GPIO5
+#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_PAD_GPIO6
+#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_PAD_GPIO7
+#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_PAD_GPIO8
+#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_PAD_GPIO9
+#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_PAD_GPIO10
+#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_PAD_GPIO11
+#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_PAD_GPIO12
+#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_PAD_GPIO13
+#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_PAD_GPIO14
+#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_PAD_GPIO15
+#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_PAD_GPIO16
+#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_PAD_GPIO17
+#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_PAD_GPIO18
+#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_PAD_GPIO19
+#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_PAD_GPIO20
+#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_PAD_GPIO21
+#define IO_MUX_GPIO22_REG                   PERIPHS_IO_MUX_U_PAD_GPIO22
+#define IO_MUX_GPIO23_REG                   PERIPHS_IO_MUX_U_PAD_GPIO23
+#define IO_MUX_GPIO24_REG                   PERIPHS_IO_MUX_U_PAD_GPIO24
+#define IO_MUX_GPIO25_REG                   PERIPHS_IO_MUX_U_PAD_GPIO25
+#define IO_MUX_GPIO26_REG                   PERIPHS_IO_MUX_U_PAD_GPIO26
+#define IO_MUX_GPIO27_REG                   PERIPHS_IO_MUX_U_PAD_GPIO27
+#define IO_MUX_GPIO28_REG                   PERIPHS_IO_MUX_U_PAD_GPIO28
+#define IO_MUX_GPIO29_REG                   PERIPHS_IO_MUX_U_PAD_GPIO29
+#define IO_MUX_GPIO30_REG                   PERIPHS_IO_MUX_U_PAD_GPIO30
+#define IO_MUX_GPIO31_REG                   PERIPHS_IO_MUX_U_PAD_GPIO31
+#define IO_MUX_GPIO32_REG                   PERIPHS_IO_MUX_U_PAD_GPIO32
+#define IO_MUX_GPIO33_REG                   PERIPHS_IO_MUX_U_PAD_GPIO33
+#define IO_MUX_GPIO34_REG                   PERIPHS_IO_MUX_U_PAD_GPIO34
+#define IO_MUX_GPIO35_REG                   PERIPHS_IO_MUX_U_PAD_GPIO35
+#define IO_MUX_GPIO36_REG                   PERIPHS_IO_MUX_U_PAD_GPIO36
+#define IO_MUX_GPIO37_REG                   PERIPHS_IO_MUX_U_PAD_GPIO37
+#define IO_MUX_GPIO38_REG                   PERIPHS_IO_MUX_U_PAD_GPIO38
+#define IO_MUX_GPIO39_REG                   PERIPHS_IO_MUX_U_PAD_GPIO39
+#define IO_MUX_GPIO40_REG                   PERIPHS_IO_MUX_U_PAD_GPIO40
+#define IO_MUX_GPIO41_REG                   PERIPHS_IO_MUX_U_PAD_GPIO41
+#define IO_MUX_GPIO42_REG                   PERIPHS_IO_MUX_U_PAD_GPIO42
+#define IO_MUX_GPIO43_REG                   PERIPHS_IO_MUX_U_PAD_GPIO43
+#define IO_MUX_GPIO44_REG                   PERIPHS_IO_MUX_U_PAD_GPIO44
+#define IO_MUX_GPIO45_REG                   PERIPHS_IO_MUX_U_PAD_GPIO45
+#define IO_MUX_GPIO46_REG                   PERIPHS_IO_MUX_U_PAD_GPIO46
+#define IO_MUX_GPIO47_REG                   PERIPHS_IO_MUX_U_PAD_GPIO47
+#define IO_MUX_GPIO48_REG                   PERIPHS_IO_MUX_U_PAD_GPIO48
+#define IO_MUX_GPIO49_REG                   PERIPHS_IO_MUX_U_PAD_GPIO49
+#define IO_MUX_GPIO50_REG                   PERIPHS_IO_MUX_U_PAD_GPIO50
+#define IO_MUX_GPIO51_REG                   PERIPHS_IO_MUX_U_PAD_GPIO51
+#define IO_MUX_GPIO52_REG                   PERIPHS_IO_MUX_U_PAD_GPIO52
+#define IO_MUX_GPIO53_REG                   PERIPHS_IO_MUX_U_PAD_GPIO53
+#define IO_MUX_GPIO54_REG                   PERIPHS_IO_MUX_U_PAD_GPIO54
+
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+// TODO: IDF-7499, IDF-7495
+// SPI pins defined here are all wrong. On P4, these pins are individual pins, don't use normal GPIO pins anymore.
+// Please check iomux_mspi_pin_struct/reg.h
+#include "soc/gpio_num.h"
+#define SPI_CS1_GPIO_NUM GPIO_NUM_MAX
+#define SPI_HD_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_WP_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_CS0_GPIO_NUM GPIO_NUM_MAX
+#define SPI_CLK_GPIO_NUM GPIO_NUM_MAX
+#define SPI_Q_GPIO_NUM   GPIO_NUM_MAX
+#define SPI_D_GPIO_NUM   GPIO_NUM_MAX
+#define SPI_D4_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D5_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D6_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_D7_GPIO_NUM  GPIO_NUM_MAX
+#define SPI_DQS_GPIO_NUM GPIO_NUM_MAX
+
+#define SD_CLK_GPIO_NUM           43
+#define SD_CMD_GPIO_NUM           44
+#define SD_DATA0_GPIO_NUM         39
+#define SD_DATA1_GPIO_NUM         40
+#define SD_DATA2_GPIO_NUM         41
+#define SD_DATA3_GPIO_NUM         42
+#define SD_DATA4_GPIO_NUM         45
+#define SD_DATA5_GPIO_NUM         46
+#define SD_DATA6_GPIO_NUM         47
+#define SD_DATA7_GPIO_NUM         48
+
+#define USB_INT_PHY0_DM_GPIO_NUM  24
+#define USB_INT_PHY0_DP_GPIO_NUM  25
+#define USB_INT_PHY1_DM_GPIO_NUM  26
+#define USB_INT_PHY1_DP_GPIO_NUM  27
+
+// We would fix the USB PHY usage on P4: PHY0 -> USJ, PHY1 -> USB_OTG
+#define USB_USJ_INT_PHY_DM_GPIO_NUM     USB_INT_PHY0_DM_GPIO_NUM
+#define USB_USJ_INT_PHY_DP_GPIO_NUM     USB_INT_PHY0_DP_GPIO_NUM
+#define USB_OTG_INT_PHY_DM_GPIO_NUM     USB_INT_PHY1_DM_GPIO_NUM
+#define USB_OTG_INT_PHY_DP_GPIO_NUM     USB_INT_PHY1_DP_GPIO_NUM
+
+#define EXT_OSC_SLOW_GPIO_NUM        0 // XTAL_32K_N
+
+#define MAX_RTC_GPIO_NUM             15
+#define MAX_PAD_GPIO_NUM             54
+#define MAX_GPIO_NUM                 56
+#define HIGH_IO_HOLD_BIT_SHIFT       32
+
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_U_PAD_GPIO0                 (REG_IO_MUX_BASE + 0x4)
+#define FUNC_GPIO0_GPIO0                                                 1
+#define FUNC_GPIO0_GPIO0_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO1                 (REG_IO_MUX_BASE + 0x8)
+#define FUNC_GPIO1_GPIO1                                                 1
+#define FUNC_GPIO1_GPIO1_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO2                 (REG_IO_MUX_BASE + 0xC)
+#define FUNC_GPIO2_GPIO2                                                 1
+#define FUNC_GPIO2_MTCK                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO3                (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO3_GPIO3                                                 1
+#define FUNC_GPIO3_MTDI                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO4                (REG_IO_MUX_BASE + 0x14)
+#define FUNC_GPIO4_GPIO4                                                 1
+#define FUNC_GPIO4_MTMS                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO5                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_GPIO5_GPIO5                                                 1
+#define FUNC_GPIO5_MTDO                                                  0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO6                (REG_IO_MUX_BASE + 0x1C)
+#define FUNC_GPIO6_SPI2_HOLD_PAD                                         3
+#define FUNC_GPIO6_GPIO6                                                 1
+#define FUNC_GPIO6_GPIO6_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO7                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_GPIO7_SPI2_CS_PAD                                           3
+#define FUNC_GPIO7_GPIO7                                                 1
+#define FUNC_GPIO7_GPIO7_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO8                (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO8_SPI2_D_PAD                                            3
+#define FUNC_GPIO8_UART0_RTS_PAD                                         2
+#define FUNC_GPIO8_GPIO8                                                 1
+#define FUNC_GPIO8_GPIO8_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO9                (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO9_SPI2_CK_PAD                                           3
+#define FUNC_GPIO9_UART0_CTS_PAD                                         2
+#define FUNC_GPIO9_GPIO9                                                 1
+#define FUNC_GPIO9_GPIO9_0                                               0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO10               (REG_IO_MUX_BASE + 0x2C)
+#define FUNC_GPIO10_SPI2_Q_PAD                                           3
+#define FUNC_GPIO10_UART1_TXD_PAD                                        2
+#define FUNC_GPIO10_GPIO10                                               1
+#define FUNC_GPIO10_GPIO10_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO11               (REG_IO_MUX_BASE + 0x30)
+#define FUNC_GPIO11_SPI2_WP_PAD                                          3
+#define FUNC_GPIO11_UART1_RXD_PAD                                        2
+#define FUNC_GPIO11_GPIO11                                               1
+#define FUNC_GPIO11_GPIO11_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO12               (REG_IO_MUX_BASE + 0x34)
+#define FUNC_GPIO12_UART1_RTS_PAD                                        2
+#define FUNC_GPIO12_GPIO12                                               1
+#define FUNC_GPIO12_GPIO12_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO13               (REG_IO_MUX_BASE + 0x38)
+#define FUNC_GPIO13_UART1_CTS_PAD                                        2
+#define FUNC_GPIO13_GPIO13                                               1
+#define FUNC_GPIO13_GPIO13_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO14               (REG_IO_MUX_BASE + 0x3C)
+#define FUNC_GPIO14_GPIO14                                               1
+#define FUNC_GPIO14_GPIO14_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO15               (REG_IO_MUX_BASE + 0x40)
+#define FUNC_GPIO15_GPIO15                                               1
+#define FUNC_GPIO15_GPIO15_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO16               (REG_IO_MUX_BASE + 0x44)
+#define FUNC_GPIO16_GPIO16                                               1
+#define FUNC_GPIO16_GPIO16_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO17               (REG_IO_MUX_BASE + 0x48)
+#define FUNC_GPIO17_GPIO17                                               1
+#define FUNC_GPIO17_GPIO17_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO18               (REG_IO_MUX_BASE + 0x4C)
+#define FUNC_GPIO18_GPIO18                                               1
+#define FUNC_GPIO18_GPIO18_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO19               (REG_IO_MUX_BASE + 0x50)
+#define FUNC_GPIO19_GPIO19                                               1
+#define FUNC_GPIO19_GPIO19_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO20               (REG_IO_MUX_BASE + 0x54)
+#define FUNC_GPIO20_GPIO20                                               1
+#define FUNC_GPIO20_GPIO20_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO21               (REG_IO_MUX_BASE + 0x58)
+#define FUNC_GPIO21_GPIO21                                               1
+#define FUNC_GPIO21_GPIO21_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO22               (REG_IO_MUX_BASE + 0x5C)
+#define FUNC_GPIO22_DBG_PSRAM_CK_PAD                                     4
+#define FUNC_GPIO22_GPIO22                                               1
+#define FUNC_GPIO22_GPIO22_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO23               (REG_IO_MUX_BASE + 0x60)
+#define FUNC_GPIO23_DBG_PSRAM_CS_PAD                                     4
+#define FUNC_GPIO23_REF_50M_CLK_PAD                                      3
+#define FUNC_GPIO23_GPIO23                                               1
+#define FUNC_GPIO23_GPIO23_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO24               (REG_IO_MUX_BASE + 0x64)
+#define FUNC_GPIO24_GPIO24                                               1
+#define FUNC_GPIO24_GPIO24_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO25               (REG_IO_MUX_BASE + 0x68)
+#define FUNC_GPIO25_GPIO25                                               1
+#define FUNC_GPIO25_GPIO25_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO26               (REG_IO_MUX_BASE + 0x6C)
+#define FUNC_GPIO26_GPIO26                                               1
+#define FUNC_GPIO26_GPIO26_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO27               (REG_IO_MUX_BASE + 0x70)
+#define FUNC_GPIO27_GPIO27                                               1
+#define FUNC_GPIO27_GPIO27_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO28               (REG_IO_MUX_BASE + 0x74)
+#define FUNC_GPIO28_DBG_PSRAM_D_PAD                                      4
+#define FUNC_GPIO28_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO28_SPI2_CS_PAD                                          2
+#define FUNC_GPIO28_GPIO28                                               1
+#define FUNC_GPIO28_GPIO28_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO29               (REG_IO_MUX_BASE + 0x78)
+#define FUNC_GPIO29_DBG_PSRAM_Q_PAD                                      4
+#define FUNC_GPIO29_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO29_SPI2_D_PAD                                           2
+#define FUNC_GPIO29_GPIO29                                               1
+#define FUNC_GPIO29_GPIO29_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO30               (REG_IO_MUX_BASE + 0x7C)
+#define FUNC_GPIO30_DBG_PSRAM_WP_PAD                                     4
+#define FUNC_GPIO30_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO30_SPI2_CK_PAD                                          2
+#define FUNC_GPIO30_GPIO30                                               1
+#define FUNC_GPIO30_GPIO30_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO31               (REG_IO_MUX_BASE + 0x80)
+#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD                                   4
+#define FUNC_GPIO31_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO31_SPI2_Q_PAD                                           2
+#define FUNC_GPIO31_GPIO31                                               1
+#define FUNC_GPIO31_GPIO31_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO32               (REG_IO_MUX_BASE + 0x84)
+#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD                                    4
+#define FUNC_GPIO32_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO32_SPI2_HOLD_PAD                                        2
+#define FUNC_GPIO32_GPIO32                                               1
+#define FUNC_GPIO32_GPIO32_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO33               (REG_IO_MUX_BASE + 0x88)
+#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD                                    4
+#define FUNC_GPIO33_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO33_SPI2_WP_PAD                                          2
+#define FUNC_GPIO33_GPIO33                                               1
+#define FUNC_GPIO33_GPIO33_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO34               (REG_IO_MUX_BASE + 0x8C)
+#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD                                    4
+#define FUNC_GPIO34_EMAC_PHY_TXD0_PAD                                    3
+#define FUNC_GPIO34_SPI2_IO4_PAD                                         2
+#define FUNC_GPIO34_GPIO34                                               1
+#define FUNC_GPIO34_GPIO34_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO35               (REG_IO_MUX_BASE + 0x90)
+#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD                                    4
+#define FUNC_GPIO35_EMAC_PHY_TXD1_PAD                                    3
+#define FUNC_GPIO35_SPI2_IO5_PAD                                         2
+#define FUNC_GPIO35_GPIO35                                               1
+#define FUNC_GPIO35_GPIO35_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO36               (REG_IO_MUX_BASE + 0x94)
+#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD                                  4
+#define FUNC_GPIO36_EMAC_PHY_TXER_PAD                                    3
+#define FUNC_GPIO36_SPI2_IO6_PAD                                         2
+#define FUNC_GPIO36_GPIO36                                               1
+#define FUNC_GPIO36_GPIO36_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO37               (REG_IO_MUX_BASE + 0x98)
+#define FUNC_GPIO37_SPI2_IO7_PAD                                         2
+#define FUNC_GPIO37_GPIO37                                               1
+#define FUNC_GPIO37_UART0_TXD_PAD                                        0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO38               (REG_IO_MUX_BASE + 0x9C)
+#define FUNC_GPIO38_SPI2_DQS_PAD                                         2
+#define FUNC_GPIO38_GPIO38                                               1
+#define FUNC_GPIO38_UART0_RXD_PAD                                        0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO39               (REG_IO_MUX_BASE + 0xA0)
+#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD                                    4
+#define FUNC_GPIO39_REF_50M_CLK_PAD                                      3
+#define FUNC_GPIO39_BIST_PAD                                             2
+#define FUNC_GPIO39_GPIO39                                               1
+#define FUNC_GPIO39_SD1_CDATA0_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO40               (REG_IO_MUX_BASE + 0xA4)
+#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD                                    4
+#define FUNC_GPIO40_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO40_BIST_PAD                                             2
+#define FUNC_GPIO40_GPIO40                                               1
+#define FUNC_GPIO40_SD1_CDATA1_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO41               (REG_IO_MUX_BASE + 0xA8)
+#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD                                   4
+#define FUNC_GPIO41_EMAC_PHY_TXD0_PAD                                    3
+#define FUNC_GPIO41_BIST_PAD                                             2
+#define FUNC_GPIO41_GPIO41                                               1
+#define FUNC_GPIO41_SD1_CDATA2_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO42               (REG_IO_MUX_BASE + 0xAC)
+#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD                                   4
+#define FUNC_GPIO42_EMAC_PHY_TXD1_PAD                                    3
+#define FUNC_GPIO42_BIST_PAD                                             2
+#define FUNC_GPIO42_GPIO42                                               1
+#define FUNC_GPIO42_SD1_CDATA3_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO43               (REG_IO_MUX_BASE + 0xB0)
+#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD                                   4
+#define FUNC_GPIO43_EMAC_PHY_TXER_PAD                                    3
+#define FUNC_GPIO43_BIST_PAD                                             2
+#define FUNC_GPIO43_GPIO43                                               1
+#define FUNC_GPIO43_SD1_CCLK_PAD                                         0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO44               (REG_IO_MUX_BASE + 0xB4)
+#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD                                   4
+#define FUNC_GPIO44_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO44_BIST_PAD                                             2
+#define FUNC_GPIO44_GPIO44                                               1
+#define FUNC_GPIO44_SD1_CCMD_PAD                                         0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO45               (REG_IO_MUX_BASE + 0xB8)
+#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD                                   4
+#define FUNC_GPIO45_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO45_BIST_PAD                                             2
+#define FUNC_GPIO45_GPIO45                                               1
+#define FUNC_GPIO45_SD1_CDATA4_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO46               (REG_IO_MUX_BASE + 0xBC)
+#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD                                   4
+#define FUNC_GPIO46_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO46_BIST_PAD                                             2
+#define FUNC_GPIO46_GPIO46                                               1
+#define FUNC_GPIO46_SD1_CDATA5_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO47               (REG_IO_MUX_BASE + 0xC0)
+#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD                                  4
+#define FUNC_GPIO47_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO47_BIST_PAD                                             2
+#define FUNC_GPIO47_GPIO47                                               1
+#define FUNC_GPIO47_SD1_CDATA6_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO48               (REG_IO_MUX_BASE + 0xC4)
+#define FUNC_GPIO48_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO48_BIST_PAD                                             2
+#define FUNC_GPIO48_GPIO48                                               1
+#define FUNC_GPIO48_SD1_CDATA7_PAD                                       0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO49               (REG_IO_MUX_BASE + 0xC8)
+#define FUNC_GPIO49_DBG_FLASH_CS_PAD                                      4
+#define FUNC_GPIO49_EMAC_PHY_TXEN_PAD                                    3
+#define FUNC_GPIO49_GPIO49                                               1
+#define FUNC_GPIO49_GPIO49_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO50               (REG_IO_MUX_BASE + 0xCC)
+#define FUNC_GPIO50_DBG_FLASH_Q_PAD                                       4
+#define FUNC_GPIO50_EMAC_RMII_CLK_PAD                                    3
+#define FUNC_GPIO50_GPIO50                                               1
+#define FUNC_GPIO50_GPIO50_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO51               (REG_IO_MUX_BASE + 0xD0)
+#define FUNC_GPIO51_DBG_FLASH_WP_PAD                                     4
+#define FUNC_GPIO51_EMAC_PHY_RXDV_PAD                                    3
+#define FUNC_GPIO51_GPIO51                                               1
+#define FUNC_GPIO51_GPIO51_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO52               (REG_IO_MUX_BASE + 0xD4)
+#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD                                   4
+#define FUNC_GPIO52_EMAC_PHY_RXD0_PAD                                    3
+#define FUNC_GPIO52_GPIO52                                               1
+#define FUNC_GPIO52_GPIO52_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO53               (REG_IO_MUX_BASE + 0xD8)
+#define FUNC_GPIO53_DBG_FLASH_CK_PAD                                      4
+#define FUNC_GPIO53_EMAC_PHY_RXD1_PAD                                    3
+#define FUNC_GPIO53_GPIO53                                               1
+#define FUNC_GPIO53_GPIO53_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO54               (REG_IO_MUX_BASE + 0xDC)
+#define FUNC_GPIO54_DBG_FLASH_D_PAD                                       4
+#define FUNC_GPIO54_EMAC_PHY_RXER_PAD                                    3
+#define FUNC_GPIO54_GPIO54                                               1
+#define FUNC_GPIO54_GPIO54_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO55               (REG_IO_MUX_BASE + 0xE0)
+#define FUNC_GPIO55_GPIO55                                               1
+#define FUNC_GPIO55_GPIO55_0                                             0
+
+#define PERIPHS_IO_MUX_U_PAD_GPIO56               (REG_IO_MUX_BASE + 0xE4)
+#define FUNC_GPIO56_GPIO56                                               1
+#define FUNC_GPIO56_GPIO56_0                                             0
+
+#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0x104)
+/* IO_MUX_DATE : R/W ;bitpos:[27:0] ;default: 27'h0201222 ; */
+/*description: csv date.*/
+#define IO_MUX_DATE    0x0FFFFFFF
+#define IO_MUX_DATE_M  ((IO_MUX_DATE_V)<<(IO_MUX_DATE_S))
+#define IO_MUX_DATE_V  0xFFFFFFF
+#define IO_MUX_DATE_S  0
diff --git a/components/soc/esp32p4/include/soc/io_mux_struct.h b/components/soc/esp32p4/register/soc/io_mux_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/io_mux_struct.h
rename to components/soc/esp32p4/register/soc/io_mux_struct.h
diff --git a/components/soc/esp32p4/include/soc/iomux_mspi_pin_reg.h b/components/soc/esp32p4/register/soc/iomux_mspi_pin_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/iomux_mspi_pin_reg.h
rename to components/soc/esp32p4/register/soc/iomux_mspi_pin_reg.h
diff --git a/components/soc/esp32p4/include/soc/iomux_mspi_pin_struct.h b/components/soc/esp32p4/register/soc/iomux_mspi_pin_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/iomux_mspi_pin_struct.h
rename to components/soc/esp32p4/register/soc/iomux_mspi_pin_struct.h
diff --git a/components/soc/esp32p4/include/soc/isp_reg.h b/components/soc/esp32p4/register/soc/isp_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/isp_reg.h
rename to components/soc/esp32p4/register/soc/isp_reg.h
index 13749f014c8..c1c42d64aaf 100644
--- a/components/soc/esp32p4/include/soc/isp_reg.h
+++ b/components/soc/esp32p4/register/soc/isp_reg.h
@@ -521,56 +521,56 @@ extern "C" {
  */
 #define ISP_BF_GAU0_REG (DR_REG_ISP_BASE + 0x30)
 /** ISP_GAU_TEMPLATE21 : R/W; bitpos: [3:0]; default: 15;
- *  this field configures index 21 of gausian template
+ *  this field configures index 21 of gaussian template
  */
 #define ISP_GAU_TEMPLATE21    0x0000000FU
 #define ISP_GAU_TEMPLATE21_M  (ISP_GAU_TEMPLATE21_V << ISP_GAU_TEMPLATE21_S)
 #define ISP_GAU_TEMPLATE21_V  0x0000000FU
 #define ISP_GAU_TEMPLATE21_S  0
 /** ISP_GAU_TEMPLATE20 : R/W; bitpos: [7:4]; default: 15;
- *  this field configures index 20 of gausian template
+ *  this field configures index 20 of gaussian template
  */
 #define ISP_GAU_TEMPLATE20    0x0000000FU
 #define ISP_GAU_TEMPLATE20_M  (ISP_GAU_TEMPLATE20_V << ISP_GAU_TEMPLATE20_S)
 #define ISP_GAU_TEMPLATE20_V  0x0000000FU
 #define ISP_GAU_TEMPLATE20_S  4
 /** ISP_GAU_TEMPLATE12 : R/W; bitpos: [11:8]; default: 15;
- *  this field configures index 12 of gausian template
+ *  this field configures index 12 of gaussian template
  */
 #define ISP_GAU_TEMPLATE12    0x0000000FU
 #define ISP_GAU_TEMPLATE12_M  (ISP_GAU_TEMPLATE12_V << ISP_GAU_TEMPLATE12_S)
 #define ISP_GAU_TEMPLATE12_V  0x0000000FU
 #define ISP_GAU_TEMPLATE12_S  8
 /** ISP_GAU_TEMPLATE11 : R/W; bitpos: [15:12]; default: 15;
- *  this field configures index 11 of gausian template
+ *  this field configures index 11 of gaussian template
  */
 #define ISP_GAU_TEMPLATE11    0x0000000FU
 #define ISP_GAU_TEMPLATE11_M  (ISP_GAU_TEMPLATE11_V << ISP_GAU_TEMPLATE11_S)
 #define ISP_GAU_TEMPLATE11_V  0x0000000FU
 #define ISP_GAU_TEMPLATE11_S  12
 /** ISP_GAU_TEMPLATE10 : R/W; bitpos: [19:16]; default: 15;
- *  this field configures index 10 of gausian template
+ *  this field configures index 10 of gaussian template
  */
 #define ISP_GAU_TEMPLATE10    0x0000000FU
 #define ISP_GAU_TEMPLATE10_M  (ISP_GAU_TEMPLATE10_V << ISP_GAU_TEMPLATE10_S)
 #define ISP_GAU_TEMPLATE10_V  0x0000000FU
 #define ISP_GAU_TEMPLATE10_S  16
 /** ISP_GAU_TEMPLATE02 : R/W; bitpos: [23:20]; default: 15;
- *  this field configures index 02 of gausian template
+ *  this field configures index 02 of gaussian template
  */
 #define ISP_GAU_TEMPLATE02    0x0000000FU
 #define ISP_GAU_TEMPLATE02_M  (ISP_GAU_TEMPLATE02_V << ISP_GAU_TEMPLATE02_S)
 #define ISP_GAU_TEMPLATE02_V  0x0000000FU
 #define ISP_GAU_TEMPLATE02_S  20
 /** ISP_GAU_TEMPLATE01 : R/W; bitpos: [27:24]; default: 15;
- *  this field configures index 01 of gausian template
+ *  this field configures index 01 of gaussian template
  */
 #define ISP_GAU_TEMPLATE01    0x0000000FU
 #define ISP_GAU_TEMPLATE01_M  (ISP_GAU_TEMPLATE01_V << ISP_GAU_TEMPLATE01_S)
 #define ISP_GAU_TEMPLATE01_V  0x0000000FU
 #define ISP_GAU_TEMPLATE01_S  24
 /** ISP_GAU_TEMPLATE00 : R/W; bitpos: [31:28]; default: 15;
- *  this field configures index 00 of gausian template
+ *  this field configures index 00 of gaussian template
  */
 #define ISP_GAU_TEMPLATE00    0x0000000FU
 #define ISP_GAU_TEMPLATE00_M  (ISP_GAU_TEMPLATE00_V << ISP_GAU_TEMPLATE00_S)
@@ -582,7 +582,7 @@ extern "C" {
  */
 #define ISP_BF_GAU1_REG (DR_REG_ISP_BASE + 0x34)
 /** ISP_GAU_TEMPLATE22 : R/W; bitpos: [3:0]; default: 15;
- *  this field configures index 22 of gausian template
+ *  this field configures index 22 of gaussian template
  */
 #define ISP_GAU_TEMPLATE22    0x0000000FU
 #define ISP_GAU_TEMPLATE22_M  (ISP_GAU_TEMPLATE22_V << ISP_GAU_TEMPLATE22_S)
@@ -2584,7 +2584,7 @@ extern "C" {
 #define ISP_AE_MONITOR_TH_V  0x000000FFU
 #define ISP_AE_MONITOR_TH_S  8
 /** ISP_AE_MONITOR_PERIOD : R/W; bitpos: [21:16]; default: 0;
- *  this field cnfigures ae monitor frame period
+ *  this field configures ae monitor frame period
  */
 #define ISP_AE_MONITOR_PERIOD    0x0000003FU
 #define ISP_AE_MONITOR_PERIOD_M  (ISP_AE_MONITOR_PERIOD_V << ISP_AE_MONITOR_PERIOD_S)
@@ -3030,7 +3030,7 @@ extern "C" {
  */
 #define ISP_DMA_CNTL_REG (DR_REG_ISP_BASE + 0x10c)
 /** ISP_DMA_EN : WT; bitpos: [0]; default: 0;
- *  write 1 to triger dma to get 1 frame
+ *  write 1 to trigger dma to get 1 frame
  */
 #define ISP_DMA_EN    (BIT(0))
 #define ISP_DMA_EN_M  (ISP_DMA_EN_V << ISP_DMA_EN_S)
@@ -3090,7 +3090,7 @@ extern "C" {
  */
 #define ISP_CAM_CNTL_REG (DR_REG_ISP_BASE + 0x114)
 /** ISP_CAM_EN : R/W; bitpos: [0]; default: 0;
- *  write 1 to start recive camera data, write 0 to disable
+ *  write 1 to start receive camera data, write 0 to disable
  */
 #define ISP_CAM_EN    (BIT(0))
 #define ISP_CAM_EN_M  (ISP_CAM_EN_V << ISP_CAM_EN_S)
@@ -3111,7 +3111,7 @@ extern "C" {
 #define ISP_CAM_RESET_V  0x00000001U
 #define ISP_CAM_RESET_S  2
 /** ISP_CAM_CLK_INV : R/W; bitpos: [3]; default: 0;
- *  this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1:
+ *  this bit configures the inversion of cam clk from pad. 0: not invert cam clk, 1:
  *  invert cam clk
  */
 #define ISP_CAM_CLK_INV    (BIT(3))
@@ -3487,7 +3487,7 @@ extern "C" {
  */
 #define ISP_AWB_MODE_REG (DR_REG_ISP_BASE + 0x164)
 /** ISP_AWB_MODE : R/W; bitpos: [1:0]; default: 3;
- *  this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel
+ *  this field configures awb algo sel. 00: none selected. 01: sel algo0. 10: sel
  *  algo1. 11: sel both algo0 and algo1
  */
 #define ISP_AWB_MODE    0x00000003U
diff --git a/components/soc/esp32p4/include/soc/isp_struct.h b/components/soc/esp32p4/register/soc/isp_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/isp_struct.h
rename to components/soc/esp32p4/register/soc/isp_struct.h
diff --git a/components/soc/esp32p4/include/soc/jpeg_reg.h b/components/soc/esp32p4/register/soc/jpeg_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/jpeg_reg.h
rename to components/soc/esp32p4/register/soc/jpeg_reg.h
diff --git a/components/soc/esp32p4/include/soc/jpeg_struct.h b/components/soc/esp32p4/register/soc/jpeg_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/jpeg_struct.h
rename to components/soc/esp32p4/register/soc/jpeg_struct.h
diff --git a/components/soc/esp32p4/include/soc/keymng_reg.h b/components/soc/esp32p4/register/soc/keymng_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/keymng_reg.h
rename to components/soc/esp32p4/register/soc/keymng_reg.h
diff --git a/components/soc/esp32p4/include/soc/keymng_struct.h b/components/soc/esp32p4/register/soc/keymng_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/keymng_struct.h
rename to components/soc/esp32p4/register/soc/keymng_struct.h
diff --git a/components/soc/esp32p4/include/soc/l2mem_monitor_reg.h b/components/soc/esp32p4/register/soc/l2mem_monitor_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/l2mem_monitor_reg.h
rename to components/soc/esp32p4/register/soc/l2mem_monitor_reg.h
diff --git a/components/soc/esp32p4/include/soc/l2mem_monitor_struct.h b/components/soc/esp32p4/register/soc/l2mem_monitor_struct.h
similarity index 98%
rename from components/soc/esp32p4/include/soc/l2mem_monitor_struct.h
rename to components/soc/esp32p4/register/soc/l2mem_monitor_struct.h
index c88691215af..e3e1abf3761 100644
--- a/components/soc/esp32p4/include/soc/l2mem_monitor_struct.h
+++ b/components/soc/esp32p4/register/soc/l2mem_monitor_struct.h
@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of log_setting register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -43,7 +43,7 @@ typedef union {
 } mem_monitor_log_setting_reg_t;
 
 /** Type of log_setting1 register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -61,7 +61,7 @@ typedef union {
 } mem_monitor_log_setting1_reg_t;
 
 /** Type of log_check_data register
- *  check data regsiter
+ *  check data register
  */
 typedef union {
     struct {
@@ -89,7 +89,7 @@ typedef union {
 } mem_monitor_log_data_mask_reg_t;
 
 /** Type of log_min register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
@@ -102,7 +102,7 @@ typedef union {
 } mem_monitor_log_min_reg_t;
 
 /** Type of log_max register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
diff --git a/components/soc/esp32p4/include/soc/lcd_cam_reg.h b/components/soc/esp32p4/register/soc/lcd_cam_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lcd_cam_reg.h
rename to components/soc/esp32p4/register/soc/lcd_cam_reg.h
diff --git a/components/soc/esp32p4/include/soc/lcd_cam_struct.h b/components/soc/esp32p4/register/soc/lcd_cam_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lcd_cam_struct.h
rename to components/soc/esp32p4/register/soc/lcd_cam_struct.h
diff --git a/components/soc/esp32p4/include/soc/ledc_reg.h b/components/soc/esp32p4/register/soc/ledc_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/ledc_reg.h
rename to components/soc/esp32p4/register/soc/ledc_reg.h
diff --git a/components/soc/esp32p4/include/soc/ledc_struct.h b/components/soc/esp32p4/register/soc/ledc_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/ledc_struct.h
rename to components/soc/esp32p4/register/soc/ledc_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h b/components/soc/esp32p4/register/soc/lp2hp_peri_pms_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp2hp_peri_pms_reg.h
rename to components/soc/esp32p4/register/soc/lp2hp_peri_pms_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp2hp_peri_pms_struct.h b/components/soc/esp32p4/register/soc/lp2hp_peri_pms_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp2hp_peri_pms_struct.h
rename to components/soc/esp32p4/register/soc/lp2hp_peri_pms_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_adc_reg.h b/components/soc/esp32p4/register/soc/lp_adc_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_adc_reg.h
rename to components/soc/esp32p4/register/soc/lp_adc_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_adc_struct.h b/components/soc/esp32p4/register/soc/lp_adc_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_adc_struct.h
rename to components/soc/esp32p4/register/soc/lp_adc_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_analog_peri_reg.h b/components/soc/esp32p4/register/soc/lp_analog_peri_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_analog_peri_reg.h
rename to components/soc/esp32p4/register/soc/lp_analog_peri_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_analog_peri_struct.h b/components/soc/esp32p4/register/soc/lp_analog_peri_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_analog_peri_struct.h
rename to components/soc/esp32p4/register/soc/lp_analog_peri_struct.h
diff --git a/components/soc/esp32p4/register/soc/lp_clkrst_reg.h b/components/soc/esp32p4/register/soc/lp_clkrst_reg.h
new file mode 100644
index 00000000000..a771250be62
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/lp_clkrst_reg.h
@@ -0,0 +1,1036 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_CLKRST_LP_CLK_CONF_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_CLKRST_BASE + 0x0)
+/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_SLOW_CLK_SEL    0x00000003U
+#define LP_CLKRST_SLOW_CLK_SEL_M  (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
+#define LP_CLKRST_SLOW_CLK_SEL_V  0x00000003U
+#define LP_CLKRST_SLOW_CLK_SEL_S  0
+/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [3:2]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_FAST_CLK_SEL    0x00000003U
+#define LP_CLKRST_FAST_CLK_SEL_M  (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
+#define LP_CLKRST_FAST_CLK_SEL_V  0x00000003U
+#define LP_CLKRST_FAST_CLK_SEL_S  2
+/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [9:4]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LP_PERI_DIV_NUM    0x0000003FU
+#define LP_CLKRST_LP_PERI_DIV_NUM_M  (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
+#define LP_CLKRST_LP_PERI_DIV_NUM_V  0x0000003FU
+#define LP_CLKRST_LP_PERI_DIV_NUM_S  4
+/** LP_CLKRST_ANA_SEL_REF_PLL8M : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_ANA_SEL_REF_PLL8M    (BIT(10))
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_M  (LP_CLKRST_ANA_SEL_REF_PLL8M_V << LP_CLKRST_ANA_SEL_REF_PLL8M_S)
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_V  0x00000001U
+#define LP_CLKRST_ANA_SEL_REF_PLL8M_S  10
+
+/** LP_CLKRST_LP_CLK_PO_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_CLKRST_BASE + 0x4)
+/** LP_CLKRST_CLK_CORE_EFUSE_OEN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN    (BIT(0))
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_M  (LP_CLKRST_CLK_CORE_EFUSE_OEN_V << LP_CLKRST_CLK_CORE_EFUSE_OEN_S)
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_CORE_EFUSE_OEN_S  0
+/** LP_CLKRST_CLK_LP_BUS_OEN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_LP_BUS_OEN    (BIT(1))
+#define LP_CLKRST_CLK_LP_BUS_OEN_M  (LP_CLKRST_CLK_LP_BUS_OEN_V << LP_CLKRST_CLK_LP_BUS_OEN_S)
+#define LP_CLKRST_CLK_LP_BUS_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_LP_BUS_OEN_S  1
+/** LP_CLKRST_CLK_AON_SLOW_OEN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_AON_SLOW_OEN    (BIT(2))
+#define LP_CLKRST_CLK_AON_SLOW_OEN_M  (LP_CLKRST_CLK_AON_SLOW_OEN_V << LP_CLKRST_CLK_AON_SLOW_OEN_S)
+#define LP_CLKRST_CLK_AON_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_AON_SLOW_OEN_S  2
+/** LP_CLKRST_CLK_AON_FAST_OEN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_AON_FAST_OEN    (BIT(3))
+#define LP_CLKRST_CLK_AON_FAST_OEN_M  (LP_CLKRST_CLK_AON_FAST_OEN_V << LP_CLKRST_CLK_AON_FAST_OEN_S)
+#define LP_CLKRST_CLK_AON_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_AON_FAST_OEN_S  3
+/** LP_CLKRST_CLK_SLOW_OEN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_SLOW_OEN    (BIT(4))
+#define LP_CLKRST_CLK_SLOW_OEN_M  (LP_CLKRST_CLK_SLOW_OEN_V << LP_CLKRST_CLK_SLOW_OEN_S)
+#define LP_CLKRST_CLK_SLOW_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SLOW_OEN_S  4
+/** LP_CLKRST_CLK_FAST_OEN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_FAST_OEN    (BIT(5))
+#define LP_CLKRST_CLK_FAST_OEN_M  (LP_CLKRST_CLK_FAST_OEN_V << LP_CLKRST_CLK_FAST_OEN_S)
+#define LP_CLKRST_CLK_FAST_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_FAST_OEN_S  5
+/** LP_CLKRST_CLK_FOSC_OEN : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_FOSC_OEN    (BIT(6))
+#define LP_CLKRST_CLK_FOSC_OEN_M  (LP_CLKRST_CLK_FOSC_OEN_V << LP_CLKRST_CLK_FOSC_OEN_S)
+#define LP_CLKRST_CLK_FOSC_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_FOSC_OEN_S  6
+/** LP_CLKRST_CLK_RC32K_OEN : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_RC32K_OEN    (BIT(7))
+#define LP_CLKRST_CLK_RC32K_OEN_M  (LP_CLKRST_CLK_RC32K_OEN_V << LP_CLKRST_CLK_RC32K_OEN_S)
+#define LP_CLKRST_CLK_RC32K_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_RC32K_OEN_S  7
+/** LP_CLKRST_CLK_SXTAL_OEN : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_SXTAL_OEN    (BIT(8))
+#define LP_CLKRST_CLK_SXTAL_OEN_M  (LP_CLKRST_CLK_SXTAL_OEN_V << LP_CLKRST_CLK_SXTAL_OEN_S)
+#define LP_CLKRST_CLK_SXTAL_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SXTAL_OEN_S  8
+/** LP_CLKRST_CLK_SOSC_OEN : R/W; bitpos: [9]; default: 0;
+ *  1'b1: probe sosc clk on
+ *  1'b0: probe sosc clk off
+ */
+#define LP_CLKRST_CLK_SOSC_OEN    (BIT(9))
+#define LP_CLKRST_CLK_SOSC_OEN_M  (LP_CLKRST_CLK_SOSC_OEN_V << LP_CLKRST_CLK_SOSC_OEN_S)
+#define LP_CLKRST_CLK_SOSC_OEN_V  0x00000001U
+#define LP_CLKRST_CLK_SOSC_OEN_S  9
+
+/** LP_CLKRST_LP_CLK_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_CLKRST_BASE + 0x8)
+/** LP_CLKRST_LP_RTC_XTAL_FORCE_ON : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON    (BIT(26))
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_M  (LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V << LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S)
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_LP_RTC_XTAL_FORCE_ON_S  26
+/** LP_CLKRST_CK_EN_LP_RAM : R/W; bitpos: [27]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_CK_EN_LP_RAM    (BIT(27))
+#define LP_CLKRST_CK_EN_LP_RAM_M  (LP_CLKRST_CK_EN_LP_RAM_V << LP_CLKRST_CK_EN_LP_RAM_S)
+#define LP_CLKRST_CK_EN_LP_RAM_V  0x00000001U
+#define LP_CLKRST_CK_EN_LP_RAM_S  27
+/** LP_CLKRST_ETM_EVENT_TICK_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_ETM_EVENT_TICK_EN    (BIT(28))
+#define LP_CLKRST_ETM_EVENT_TICK_EN_M  (LP_CLKRST_ETM_EVENT_TICK_EN_V << LP_CLKRST_ETM_EVENT_TICK_EN_S)
+#define LP_CLKRST_ETM_EVENT_TICK_EN_V  0x00000001U
+#define LP_CLKRST_ETM_EVENT_TICK_EN_S  28
+/** LP_CLKRST_PLL8M_CLK_FORCE_ON : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON    (BIT(29))
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_M  (LP_CLKRST_PLL8M_CLK_FORCE_ON_V << LP_CLKRST_PLL8M_CLK_FORCE_ON_S)
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_PLL8M_CLK_FORCE_ON_S  29
+/** LP_CLKRST_XTAL_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_XTAL_CLK_FORCE_ON    (BIT(30))
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_M  (LP_CLKRST_XTAL_CLK_FORCE_ON_V << LP_CLKRST_XTAL_CLK_FORCE_ON_S)
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_XTAL_CLK_FORCE_ON_S  30
+/** LP_CLKRST_FOSC_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_CLK_FORCE_ON    (BIT(31))
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_M  (LP_CLKRST_FOSC_CLK_FORCE_ON_V << LP_CLKRST_FOSC_CLK_FORCE_ON_S)
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_FOSC_CLK_FORCE_ON_S  31
+
+/** LP_CLKRST_LP_RST_EN_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_CLKRST_BASE + 0xc)
+/** LP_CLKRST_RST_EN_LP_HUK : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_HUK    (BIT(24))
+#define LP_CLKRST_RST_EN_LP_HUK_M  (LP_CLKRST_RST_EN_LP_HUK_V << LP_CLKRST_RST_EN_LP_HUK_S)
+#define LP_CLKRST_RST_EN_LP_HUK_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_HUK_S  24
+/** LP_CLKRST_RST_EN_LP_ANAPERI : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_ANAPERI    (BIT(25))
+#define LP_CLKRST_RST_EN_LP_ANAPERI_M  (LP_CLKRST_RST_EN_LP_ANAPERI_V << LP_CLKRST_RST_EN_LP_ANAPERI_S)
+#define LP_CLKRST_RST_EN_LP_ANAPERI_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_ANAPERI_S  25
+/** LP_CLKRST_RST_EN_LP_WDT : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_WDT    (BIT(26))
+#define LP_CLKRST_RST_EN_LP_WDT_M  (LP_CLKRST_RST_EN_LP_WDT_V << LP_CLKRST_RST_EN_LP_WDT_S)
+#define LP_CLKRST_RST_EN_LP_WDT_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_WDT_S  26
+/** LP_CLKRST_RST_EN_LP_TIMER : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_TIMER    (BIT(27))
+#define LP_CLKRST_RST_EN_LP_TIMER_M  (LP_CLKRST_RST_EN_LP_TIMER_V << LP_CLKRST_RST_EN_LP_TIMER_S)
+#define LP_CLKRST_RST_EN_LP_TIMER_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_TIMER_S  27
+/** LP_CLKRST_RST_EN_LP_RTC : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_RTC    (BIT(28))
+#define LP_CLKRST_RST_EN_LP_RTC_M  (LP_CLKRST_RST_EN_LP_RTC_V << LP_CLKRST_RST_EN_LP_RTC_S)
+#define LP_CLKRST_RST_EN_LP_RTC_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_RTC_S  28
+/** LP_CLKRST_RST_EN_LP_MAILBOX : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_MAILBOX    (BIT(29))
+#define LP_CLKRST_RST_EN_LP_MAILBOX_M  (LP_CLKRST_RST_EN_LP_MAILBOX_V << LP_CLKRST_RST_EN_LP_MAILBOX_S)
+#define LP_CLKRST_RST_EN_LP_MAILBOX_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_MAILBOX_S  29
+/** LP_CLKRST_RST_EN_LP_AONEFUSEREG : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG    (BIT(30))
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_M  (LP_CLKRST_RST_EN_LP_AONEFUSEREG_V << LP_CLKRST_RST_EN_LP_AONEFUSEREG_S)
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_AONEFUSEREG_S  30
+/** LP_CLKRST_RST_EN_LP_RAM : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_RST_EN_LP_RAM    (BIT(31))
+#define LP_CLKRST_RST_EN_LP_RAM_M  (LP_CLKRST_RST_EN_LP_RAM_V << LP_CLKRST_RST_EN_LP_RAM_S)
+#define LP_CLKRST_RST_EN_LP_RAM_V  0x00000001U
+#define LP_CLKRST_RST_EN_LP_RAM_S  31
+
+/** LP_CLKRST_RESET_CAUSE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
+/** LP_CLKRST_LPCORE_RESET_CAUSE : RO; bitpos: [5:0]; default: 0;
+ *  6'h1: POR reset
+ *  6'h9: PMU LP PERI power down reset
+ *  6'ha: PMU LP CPU reset
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: software reset
+ */
+#define LP_CLKRST_LPCORE_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_LPCORE_RESET_CAUSE_M  (LP_CLKRST_LPCORE_RESET_CAUSE_V << LP_CLKRST_LPCORE_RESET_CAUSE_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_LPCORE_RESET_CAUSE_S  0
+/** LP_CLKRST_LPCORE_RESET_FLAG : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LPCORE_RESET_FLAG    (BIT(6))
+#define LP_CLKRST_LPCORE_RESET_FLAG_M  (LP_CLKRST_LPCORE_RESET_FLAG_V << LP_CLKRST_LPCORE_RESET_FLAG_S)
+#define LP_CLKRST_LPCORE_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_FLAG_S  6
+/** LP_CLKRST_HPCORE0_RESET_CAUSE : RO; bitpos: [12:7]; default: 0;
+ *  6'h1: POR reset
+ *  6'h3: digital system software reset
+ *  6'h5: PMU HP system power down reset
+ *  6'h7: HP system reset from HP watchdog
+ *  6'h9: HP system reset from LP watchdog
+ *  6'hb: HP core reset from HP watchdog
+ *  6'hc: HP core software reset
+ *  6'hd: HP core reset from LP watchdog
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: efuse crc error reset
+ *  6'h16: HP usb jtag chip reset
+ *  6'h17: HP usb uart chip reset
+ *  6'h18: HP jtag reset
+ *  6'h1a: HP core lockup
+ */
+#define LP_CLKRST_HPCORE0_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_M  (LP_CLKRST_HPCORE0_RESET_CAUSE_V << LP_CLKRST_HPCORE0_RESET_CAUSE_S)
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_S  7
+/** LP_CLKRST_HPCORE0_RESET_FLAG : RO; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_RESET_FLAG    (BIT(13))
+#define LP_CLKRST_HPCORE0_RESET_FLAG_M  (LP_CLKRST_HPCORE0_RESET_FLAG_V << LP_CLKRST_HPCORE0_RESET_FLAG_S)
+#define LP_CLKRST_HPCORE0_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_FLAG_S  13
+/** LP_CLKRST_HPCORE1_RESET_CAUSE : RO; bitpos: [19:14]; default: 0;
+ *  6'h1: POR reset
+ *  6'h3: digital system software reset
+ *  6'h5: PMU HP system power down reset
+ *  6'h7: HP system reset from HP watchdog
+ *  6'h9: HP system reset from LP watchdog
+ *  6'hb: HP core reset from HP watchdog
+ *  6'hc: HP core software reset
+ *  6'hd: HP core reset from LP watchdog
+ *  6'hf: brown out reset
+ *  6'h10: LP watchdog chip reset
+ *  6'h12: super watch dog reset
+ *  6'h13: glitch reset
+ *  6'h14: efuse crc error reset
+ *  6'h16: HP usb jtag chip reset
+ *  6'h17: HP usb uart chip reset
+ *  6'h18: HP jtag reset
+ *  6'h1a: HP core lockup
+ */
+#define LP_CLKRST_HPCORE1_RESET_CAUSE    0x0000003FU
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_M  (LP_CLKRST_HPCORE1_RESET_CAUSE_V << LP_CLKRST_HPCORE1_RESET_CAUSE_S)
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_V  0x0000003FU
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_S  14
+/** LP_CLKRST_HPCORE1_RESET_FLAG : RO; bitpos: [20]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_RESET_FLAG    (BIT(20))
+#define LP_CLKRST_HPCORE1_RESET_FLAG_M  (LP_CLKRST_HPCORE1_RESET_FLAG_V << LP_CLKRST_HPCORE1_RESET_FLAG_S)
+#define LP_CLKRST_HPCORE1_RESET_FLAG_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_FLAG_S  20
+/** LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK : R/W; bitpos: [25]; default: 1;
+ *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
+ *  pmu_lp_cpu_reset reset_cause
+ */
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK    (BIT(25))
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_M  (LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V << LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK_S  25
+/** LP_CLKRST_LPCORE_RESET_CAUSE_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR    (BIT(26))
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_M  (LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V << LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_CAUSE_CLR_S  26
+/** LP_CLKRST_LPCORE_RESET_FLAG_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR    (BIT(27))
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_M  (LP_CLKRST_LPCORE_RESET_FLAG_CLR_V << LP_CLKRST_LPCORE_RESET_FLAG_CLR_S)
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_LPCORE_RESET_FLAG_CLR_S  27
+/** LP_CLKRST_HPCORE0_RESET_CAUSE_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR    (BIT(28))
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_M  (LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_CAUSE_CLR_S  28
+/** LP_CLKRST_HPCORE0_RESET_FLAG_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR    (BIT(29))
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_M  (LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S)
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE0_RESET_FLAG_CLR_S  29
+/** LP_CLKRST_HPCORE1_RESET_CAUSE_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR    (BIT(30))
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_M  (LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V << LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S)
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_CAUSE_CLR_S  30
+/** LP_CLKRST_HPCORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR    (BIT(31))
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_M  (LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V << LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S)
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_V  0x00000001U
+#define LP_CLKRST_HPCORE1_RESET_FLAG_CLR_S  31
+
+/** LP_CLKRST_HPCPU_RESET_CTRL0_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPCPU_RESET_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x14)
+/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [0]; default: 0;
+ *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
+ *  reset feature
+ */
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN    (BIT(0))
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S  0
+/** LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH : R/W; bitpos: [3:1]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH    0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_M  (LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S)
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_V  0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_LENGTH_S  1
+/** LP_CLKRST_LP_WDT_HPCORE0_RESET_EN : R/W; bitpos: [4]; default: 0;
+ *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
+ *  hpcore0 feature
+ */
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN    (BIT(4))
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_M  (LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S)
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_V  0x00000001U
+#define LP_CLKRST_LP_WDT_HPCORE0_RESET_EN_S  4
+/** LP_CLKRST_HPCORE0_STALL_WAIT : R/W; bitpos: [11:5]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_STALL_WAIT    0x0000007FU
+#define LP_CLKRST_HPCORE0_STALL_WAIT_M  (LP_CLKRST_HPCORE0_STALL_WAIT_V << LP_CLKRST_HPCORE0_STALL_WAIT_S)
+#define LP_CLKRST_HPCORE0_STALL_WAIT_V  0x0000007FU
+#define LP_CLKRST_HPCORE0_STALL_WAIT_S  5
+/** LP_CLKRST_HPCORE0_STALL_EN : R/W; bitpos: [12]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_STALL_EN    (BIT(12))
+#define LP_CLKRST_HPCORE0_STALL_EN_M  (LP_CLKRST_HPCORE0_STALL_EN_V << LP_CLKRST_HPCORE0_STALL_EN_S)
+#define LP_CLKRST_HPCORE0_STALL_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE0_STALL_EN_S  12
+/** LP_CLKRST_HPCORE0_SW_RESET : WT; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_SW_RESET    (BIT(13))
+#define LP_CLKRST_HPCORE0_SW_RESET_M  (LP_CLKRST_HPCORE0_SW_RESET_V << LP_CLKRST_HPCORE0_SW_RESET_S)
+#define LP_CLKRST_HPCORE0_SW_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE0_SW_RESET_S  13
+/** LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET : R/W; bitpos: [14]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET    (BIT(14))
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_M  (LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S)
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE0_OCD_HALT_ON_RESET_S  14
+/** LP_CLKRST_HPCORE0_STAT_VECTOR_SEL : R/W; bitpos: [15]; default: 1;
+ *  1'b1: boot from HP TCM ROM: 0x4FC00000
+ *  1'b0: boot from LP TCM RAM:  0x50108000
+ */
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL    (BIT(15))
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_M  (LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S)
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_V  0x00000001U
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL_S  15
+/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [16]; default: 0;
+ *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
+ *  reset feature
+ */
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN    (BIT(16))
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M  (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S)
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S  16
+/** LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH : R/W; bitpos: [19:17]; default: 1;
+ *  need_des
+ */
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH    0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_M  (LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S)
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_V  0x00000007U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_LENGTH_S  17
+/** LP_CLKRST_LP_WDT_HPCORE1_RESET_EN : R/W; bitpos: [20]; default: 0;
+ *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
+ *  hpcore1 feature
+ */
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN    (BIT(20))
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_M  (LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V << LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S)
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_V  0x00000001U
+#define LP_CLKRST_LP_WDT_HPCORE1_RESET_EN_S  20
+/** LP_CLKRST_HPCORE1_STALL_WAIT : R/W; bitpos: [27:21]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_STALL_WAIT    0x0000007FU
+#define LP_CLKRST_HPCORE1_STALL_WAIT_M  (LP_CLKRST_HPCORE1_STALL_WAIT_V << LP_CLKRST_HPCORE1_STALL_WAIT_S)
+#define LP_CLKRST_HPCORE1_STALL_WAIT_V  0x0000007FU
+#define LP_CLKRST_HPCORE1_STALL_WAIT_S  21
+/** LP_CLKRST_HPCORE1_STALL_EN : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_STALL_EN    (BIT(28))
+#define LP_CLKRST_HPCORE1_STALL_EN_M  (LP_CLKRST_HPCORE1_STALL_EN_V << LP_CLKRST_HPCORE1_STALL_EN_S)
+#define LP_CLKRST_HPCORE1_STALL_EN_V  0x00000001U
+#define LP_CLKRST_HPCORE1_STALL_EN_S  28
+/** LP_CLKRST_HPCORE1_SW_RESET : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_SW_RESET    (BIT(29))
+#define LP_CLKRST_HPCORE1_SW_RESET_M  (LP_CLKRST_HPCORE1_SW_RESET_V << LP_CLKRST_HPCORE1_SW_RESET_S)
+#define LP_CLKRST_HPCORE1_SW_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE1_SW_RESET_S  29
+/** LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET    (BIT(30))
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_M  (LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V << LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S)
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_V  0x00000001U
+#define LP_CLKRST_HPCORE1_OCD_HALT_ON_RESET_S  30
+/** LP_CLKRST_HPCORE1_STAT_VECTOR_SEL : R/W; bitpos: [31]; default: 1;
+ *  1'b1: boot from HP TCM ROM: 0x4FC00000
+ *  1'b0: boot from LP TCM RAM:  0x50108000
+ */
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL    (BIT(31))
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_M  (LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V << LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S)
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_V  0x00000001U
+#define LP_CLKRST_HPCORE1_STAT_VECTOR_SEL_S  31
+
+/** LP_CLKRST_HPCPU_RESET_CTRL1_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPCPU_RESET_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x18)
+/** LP_CLKRST_HPCORE0_SW_STALL_CODE : R/W; bitpos: [23:16]; default: 0;
+ *  HP core0 software stall when set to 8'h86
+ */
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE    0x000000FFU
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_M  (LP_CLKRST_HPCORE0_SW_STALL_CODE_V << LP_CLKRST_HPCORE0_SW_STALL_CODE_S)
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_V  0x000000FFU
+#define LP_CLKRST_HPCORE0_SW_STALL_CODE_S  16
+/** LP_CLKRST_HPCORE1_SW_STALL_CODE : R/W; bitpos: [31:24]; default: 0;
+ *  HP core1 software stall when set to 8'h86
+ */
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE    0x000000FFU
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_M  (LP_CLKRST_HPCORE1_SW_STALL_CODE_V << LP_CLKRST_HPCORE1_SW_STALL_CODE_S)
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_V  0x000000FFU
+#define LP_CLKRST_HPCORE1_SW_STALL_CODE_S  24
+
+/** LP_CLKRST_FOSC_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x1c)
+/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 400;
+ *  need_des
+ */
+#define LP_CLKRST_FOSC_DFREQ    0x000003FFU
+#define LP_CLKRST_FOSC_DFREQ_M  (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
+#define LP_CLKRST_FOSC_DFREQ_V  0x000003FFU
+#define LP_CLKRST_FOSC_DFREQ_S  22
+
+/** LP_CLKRST_RC32K_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x20)
+/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:0]; default: 650;
+ *  need_des
+ */
+#define LP_CLKRST_RC32K_DFREQ    0xFFFFFFFFU
+#define LP_CLKRST_RC32K_DFREQ_M  (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
+#define LP_CLKRST_RC32K_DFREQ_V  0xFFFFFFFFU
+#define LP_CLKRST_RC32K_DFREQ_S  0
+
+/** LP_CLKRST_SOSC_CNTL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_CLKRST_BASE + 0x24)
+/** LP_CLKRST_SOSC_DFREQ : R/W; bitpos: [31:22]; default: 172;
+ *  need_des
+ */
+#define LP_CLKRST_SOSC_DFREQ    0x000003FFU
+#define LP_CLKRST_SOSC_DFREQ_M  (LP_CLKRST_SOSC_DFREQ_V << LP_CLKRST_SOSC_DFREQ_S)
+#define LP_CLKRST_SOSC_DFREQ_V  0x000003FFU
+#define LP_CLKRST_SOSC_DFREQ_S  22
+
+/** LP_CLKRST_CLK_TO_HP_REG register
+ *  need_des
+ */
+#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_CLKRST_BASE + 0x28)
+/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define LP_CLKRST_ICG_HP_XTAL32K    (BIT(28))
+#define LP_CLKRST_ICG_HP_XTAL32K_M  (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
+#define LP_CLKRST_ICG_HP_XTAL32K_V  0x00000001U
+#define LP_CLKRST_ICG_HP_XTAL32K_S  28
+/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define LP_CLKRST_ICG_HP_SOSC    (BIT(29))
+#define LP_CLKRST_ICG_HP_SOSC_M  (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
+#define LP_CLKRST_ICG_HP_SOSC_V  0x00000001U
+#define LP_CLKRST_ICG_HP_SOSC_S  29
+/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define LP_CLKRST_ICG_HP_OSC32K    (BIT(30))
+#define LP_CLKRST_ICG_HP_OSC32K_M  (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
+#define LP_CLKRST_ICG_HP_OSC32K_V  0x00000001U
+#define LP_CLKRST_ICG_HP_OSC32K_S  30
+/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
+ *  reserved
+ */
+#define LP_CLKRST_ICG_HP_FOSC    (BIT(31))
+#define LP_CLKRST_ICG_HP_FOSC_M  (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
+#define LP_CLKRST_ICG_HP_FOSC_V  0x00000001U
+#define LP_CLKRST_ICG_HP_FOSC_S  31
+
+/** LP_CLKRST_LPMEM_FORCE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_CLKRST_BASE + 0x2c)
+/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON    (BIT(31))
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M  (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V  0x00000001U
+#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S  31
+
+/** LP_CLKRST_XTAL32K_REG register
+ *  need_des
+ */
+#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_CLKRST_BASE + 0x30)
+/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DRES_XTAL32K    0x00000007U
+#define LP_CLKRST_DRES_XTAL32K_M  (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
+#define LP_CLKRST_DRES_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DRES_XTAL32K_S  22
+/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DGM_XTAL32K    0x00000007U
+#define LP_CLKRST_DGM_XTAL32K_M  (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
+#define LP_CLKRST_DGM_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DGM_XTAL32K_S  25
+/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_DBUF_XTAL32K    (BIT(28))
+#define LP_CLKRST_DBUF_XTAL32K_M  (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
+#define LP_CLKRST_DBUF_XTAL32K_V  0x00000001U
+#define LP_CLKRST_DBUF_XTAL32K_S  28
+/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
+ *  need_des
+ */
+#define LP_CLKRST_DAC_XTAL32K    0x00000007U
+#define LP_CLKRST_DAC_XTAL32K_M  (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
+#define LP_CLKRST_DAC_XTAL32K_V  0x00000007U
+#define LP_CLKRST_DAC_XTAL32K_S  29
+
+/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x34)
+/** LP_CLKRST_MUX_HPSYS_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_M  (LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V << LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S)
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_MUX_HPSYS_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HPSYS_0_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x38)
+/** LP_CLKRST_HPSYS_0_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_M  (LP_CLKRST_HPSYS_0_RESET_BYPASS_V << LP_CLKRST_HPSYS_0_RESET_BYPASS_S)
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_0_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_REG (DR_REG_LP_CLKRST_BASE + 0x3c)
+/** LP_CLKRST_HPSYS_APM_RESET_BYPASS : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS    0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_M  (LP_CLKRST_HPSYS_APM_RESET_BYPASS_V << LP_CLKRST_HPSYS_APM_RESET_BYPASS_S)
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_V  0xFFFFFFFFU
+#define LP_CLKRST_HPSYS_APM_RESET_BYPASS_S  0
+
+/** LP_CLKRST_HP_CLK_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define LP_CLKRST_HP_CLK_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x40)
+/** LP_CLKRST_HP_ROOT_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
+ */
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL    0x00000003U
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_M  (LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V << LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S)
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_V  0x00000003U
+#define LP_CLKRST_HP_ROOT_CLK_SRC_SEL_S  0
+/** LP_CLKRST_HP_ROOT_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  HP SoC Root Clock Enable.
+ */
+#define LP_CLKRST_HP_ROOT_CLK_EN    (BIT(2))
+#define LP_CLKRST_HP_ROOT_CLK_EN_M  (LP_CLKRST_HP_ROOT_CLK_EN_V << LP_CLKRST_HP_ROOT_CLK_EN_S)
+#define LP_CLKRST_HP_ROOT_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_ROOT_CLK_EN_S  2
+/** LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  PARLIO TX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN    (BIT(3))
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_M  (LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN_S  3
+/** LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  PARLIO RX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN    (BIT(4))
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_M  (LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V << LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN_S  4
+/** LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  UART4 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN    (BIT(5))
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART4_SLP_CLK_EN_S  5
+/** LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  UART3 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN    (BIT(6))
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART3_SLP_CLK_EN_S  6
+/** LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  UART2 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN    (BIT(7))
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART2_SLP_CLK_EN_S  7
+/** LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  UART1 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN    (BIT(8))
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART1_SLP_CLK_EN_S  8
+/** LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  UART0 SLP Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN    (BIT(9))
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_M  (LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V << LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_UART0_SLP_CLK_EN_S  9
+/** LP_CLKRST_HP_PAD_I2S2_MCLK_EN : R/W; bitpos: [10]; default: 1;
+ *  I2S2 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN    (BIT(10))
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S2_MCLK_EN_S  10
+/** LP_CLKRST_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [11]; default: 1;
+ *  I2S1 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN    (BIT(11))
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S1_MCLK_EN_S  11
+/** LP_CLKRST_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [12]; default: 1;
+ *  I2S0 MCLK Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN    (BIT(12))
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_M  (LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V << LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S)
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_I2S0_MCLK_EN_S  12
+/** LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN : R/W; bitpos: [13]; default: 1;
+ *  EMAC RX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN    (BIT(13))
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN_S  13
+/** LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  EMAC TX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN    (BIT(14))
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN_S  14
+/** LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  EMAC TXRX Clock From Pad Enable.
+ */
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN    (BIT(15))
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_M  (LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V << LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S)
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN_S  15
+/** LP_CLKRST_HP_XTAL_32K_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  XTAL 32K Clock Enable.
+ */
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN    (BIT(16))
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_M  (LP_CLKRST_HP_XTAL_32K_CLK_EN_V << LP_CLKRST_HP_XTAL_32K_CLK_EN_S)
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_XTAL_32K_CLK_EN_S  16
+/** LP_CLKRST_HP_RC_32K_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  RC 32K Clock Enable.
+ */
+#define LP_CLKRST_HP_RC_32K_CLK_EN    (BIT(17))
+#define LP_CLKRST_HP_RC_32K_CLK_EN_M  (LP_CLKRST_HP_RC_32K_CLK_EN_V << LP_CLKRST_HP_RC_32K_CLK_EN_S)
+#define LP_CLKRST_HP_RC_32K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_RC_32K_CLK_EN_S  17
+/** LP_CLKRST_HP_SOSC_150K_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  SOSC 150K Clock Enable.
+ */
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN    (BIT(18))
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_M  (LP_CLKRST_HP_SOSC_150K_CLK_EN_V << LP_CLKRST_HP_SOSC_150K_CLK_EN_S)
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SOSC_150K_CLK_EN_S  18
+/** LP_CLKRST_HP_PLL_8M_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  PLL 8M Clock Enable.
+ */
+#define LP_CLKRST_HP_PLL_8M_CLK_EN    (BIT(19))
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_M  (LP_CLKRST_HP_PLL_8M_CLK_EN_V << LP_CLKRST_HP_PLL_8M_CLK_EN_S)
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_PLL_8M_CLK_EN_S  19
+/** LP_CLKRST_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  AUDIO PLL Clock Enable.
+ */
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN    (BIT(20))
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_M  (LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V << LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S)
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_AUDIO_PLL_CLK_EN_S  20
+/** LP_CLKRST_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  SDIO PLL2 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN    (BIT(21))
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL2_CLK_EN_S  21
+/** LP_CLKRST_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  SDIO PLL1 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN    (BIT(22))
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL1_CLK_EN_S  22
+/** LP_CLKRST_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  SDIO PLL0 Clock Enable.
+ */
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN    (BIT(23))
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_M  (LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V << LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S)
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SDIO_PLL0_CLK_EN_S  23
+/** LP_CLKRST_HP_FOSC_20M_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  FOSC 20M Clock Enable.
+ */
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN    (BIT(24))
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_M  (LP_CLKRST_HP_FOSC_20M_CLK_EN_V << LP_CLKRST_HP_FOSC_20M_CLK_EN_S)
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_FOSC_20M_CLK_EN_S  24
+/** LP_CLKRST_HP_XTAL_40M_CLK_EN : R/W; bitpos: [25]; default: 1;
+ *  XTAL 40M Clock Enable.
+ */
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN    (BIT(25))
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_M  (LP_CLKRST_HP_XTAL_40M_CLK_EN_V << LP_CLKRST_HP_XTAL_40M_CLK_EN_S)
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_XTAL_40M_CLK_EN_S  25
+/** LP_CLKRST_HP_CPLL_400M_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  CPLL 400M Clock Enable.
+ */
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN    (BIT(26))
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_M  (LP_CLKRST_HP_CPLL_400M_CLK_EN_V << LP_CLKRST_HP_CPLL_400M_CLK_EN_S)
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_CPLL_400M_CLK_EN_S  26
+/** LP_CLKRST_HP_SPLL_480M_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  SPLL 480M Clock Enable.
+ */
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN    (BIT(27))
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_M  (LP_CLKRST_HP_SPLL_480M_CLK_EN_V << LP_CLKRST_HP_SPLL_480M_CLK_EN_S)
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_SPLL_480M_CLK_EN_S  27
+/** LP_CLKRST_HP_MPLL_500M_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  MPLL 500M Clock Enable.
+ */
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN    (BIT(28))
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_M  (LP_CLKRST_HP_MPLL_500M_CLK_EN_V << LP_CLKRST_HP_MPLL_500M_CLK_EN_S)
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_HP_MPLL_500M_CLK_EN_S  28
+
+/** LP_CLKRST_HP_USB_CLKRST_CTRL0_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define LP_CLKRST_HP_USB_CLKRST_CTRL0_REG (DR_REG_LP_CLKRST_BASE + 0x44)
+/** LP_CLKRST_USB_OTG20_SLEEP_MODE : R/W; bitpos: [0]; default: 0;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE    (BIT(0))
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_M  (LP_CLKRST_USB_OTG20_SLEEP_MODE_V << LP_CLKRST_USB_OTG20_SLEEP_MODE_S)
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_SLEEP_MODE_S  0
+/** LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN    (BIT(1))
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_M  (LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN_S  1
+/** LP_CLKRST_USB_OTG11_SLEEP_MODE : R/W; bitpos: [2]; default: 0;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE    (BIT(2))
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_M  (LP_CLKRST_USB_OTG11_SLEEP_MODE_V << LP_CLKRST_USB_OTG11_SLEEP_MODE_S)
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_SLEEP_MODE_S  2
+/** LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  unused.
+ */
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN    (BIT(3))
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_M  (LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V << LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S)
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN_S  3
+/** LP_CLKRST_USB_OTG11_48M_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  usb otg11 fs phy clock enable.
+ */
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN    (BIT(4))
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_M  (LP_CLKRST_USB_OTG11_48M_CLK_EN_V << LP_CLKRST_USB_OTG11_48M_CLK_EN_S)
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG11_48M_CLK_EN_S  4
+/** LP_CLKRST_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  usb device fs phy clock enable.
+ */
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN    (BIT(5))
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_M  (LP_CLKRST_USB_DEVICE_48M_CLK_EN_V << LP_CLKRST_USB_DEVICE_48M_CLK_EN_S)
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_DEVICE_48M_CLK_EN_S  5
+/** LP_CLKRST_USB_48M_DIV_NUM : R/W; bitpos: [13:6]; default: 9;
+ *  usb 480m to 25m divide number.
+ */
+#define LP_CLKRST_USB_48M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_48M_DIV_NUM_M  (LP_CLKRST_USB_48M_DIV_NUM_V << LP_CLKRST_USB_48M_DIV_NUM_S)
+#define LP_CLKRST_USB_48M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_48M_DIV_NUM_S  6
+/** LP_CLKRST_USB_25M_DIV_NUM : R/W; bitpos: [21:14]; default: 19;
+ *  usb 500m to 25m divide number.
+ */
+#define LP_CLKRST_USB_25M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_25M_DIV_NUM_M  (LP_CLKRST_USB_25M_DIV_NUM_V << LP_CLKRST_USB_25M_DIV_NUM_S)
+#define LP_CLKRST_USB_25M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_25M_DIV_NUM_S  14
+/** LP_CLKRST_USB_12M_DIV_NUM : R/W; bitpos: [29:22]; default: 39;
+ *  usb 480m to 12m divide number.
+ */
+#define LP_CLKRST_USB_12M_DIV_NUM    0x000000FFU
+#define LP_CLKRST_USB_12M_DIV_NUM_M  (LP_CLKRST_USB_12M_DIV_NUM_V << LP_CLKRST_USB_12M_DIV_NUM_S)
+#define LP_CLKRST_USB_12M_DIV_NUM_V  0x000000FFU
+#define LP_CLKRST_USB_12M_DIV_NUM_S  22
+
+/** LP_CLKRST_HP_USB_CLKRST_CTRL1_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define LP_CLKRST_HP_USB_CLKRST_CTRL1_REG (DR_REG_LP_CLKRST_BASE + 0x48)
+/** LP_CLKRST_RST_EN_USB_OTG20_ADP : R/W; bitpos: [0]; default: 0;
+ *  usb otg20 adp reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP    (BIT(0))
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_M  (LP_CLKRST_RST_EN_USB_OTG20_ADP_V << LP_CLKRST_RST_EN_USB_OTG20_ADP_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_ADP_S  0
+/** LP_CLKRST_RST_EN_USB_OTG20_PHY : R/W; bitpos: [1]; default: 0;
+ *  usb otg20 phy reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY    (BIT(1))
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_M  (LP_CLKRST_RST_EN_USB_OTG20_PHY_V << LP_CLKRST_RST_EN_USB_OTG20_PHY_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_PHY_S  1
+/** LP_CLKRST_RST_EN_USB_OTG20 : R/W; bitpos: [2]; default: 0;
+ *  usb otg20 reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG20    (BIT(2))
+#define LP_CLKRST_RST_EN_USB_OTG20_M  (LP_CLKRST_RST_EN_USB_OTG20_V << LP_CLKRST_RST_EN_USB_OTG20_S)
+#define LP_CLKRST_RST_EN_USB_OTG20_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG20_S  2
+/** LP_CLKRST_RST_EN_USB_OTG11 : R/W; bitpos: [3]; default: 0;
+ *  usb org11 reset en
+ */
+#define LP_CLKRST_RST_EN_USB_OTG11    (BIT(3))
+#define LP_CLKRST_RST_EN_USB_OTG11_M  (LP_CLKRST_RST_EN_USB_OTG11_V << LP_CLKRST_RST_EN_USB_OTG11_S)
+#define LP_CLKRST_RST_EN_USB_OTG11_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_OTG11_S  3
+/** LP_CLKRST_RST_EN_USB_DEVICE : R/W; bitpos: [4]; default: 0;
+ *  usb device reset en
+ */
+#define LP_CLKRST_RST_EN_USB_DEVICE    (BIT(4))
+#define LP_CLKRST_RST_EN_USB_DEVICE_M  (LP_CLKRST_RST_EN_USB_DEVICE_V << LP_CLKRST_RST_EN_USB_DEVICE_S)
+#define LP_CLKRST_RST_EN_USB_DEVICE_V  0x00000001U
+#define LP_CLKRST_RST_EN_USB_DEVICE_S  4
+/** LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [29:28]; default: 0;
+ *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
+ */
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL    0x00000003U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_M  (LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S)
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_V  0x00000003U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL_S  28
+/** LP_CLKRST_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  usb otg20 hs phy refclk enable.
+ */
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN    (BIT(30))
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_M  (LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V << LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_PHYREF_CLK_EN_S  30
+/** LP_CLKRST_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  usb otg20 ulpi clock enable.
+ */
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN    (BIT(31))
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_M  (LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V << LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S)
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_V  0x00000001U
+#define LP_CLKRST_USB_OTG20_ULPI_CLK_EN_S  31
+
+/** LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG register
+ *  need_des
+ */
+#define LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG (DR_REG_LP_CLKRST_BASE + 0x4c)
+/** LP_CLKRST_RST_EN_SDMMC : R/W; bitpos: [28]; default: 0;
+ *  hp sdmmc reset en
+ */
+#define LP_CLKRST_RST_EN_SDMMC    (BIT(28))
+#define LP_CLKRST_RST_EN_SDMMC_M  (LP_CLKRST_RST_EN_SDMMC_V << LP_CLKRST_RST_EN_SDMMC_S)
+#define LP_CLKRST_RST_EN_SDMMC_V  0x00000001U
+#define LP_CLKRST_RST_EN_SDMMC_S  28
+/** LP_CLKRST_FORCE_NORST_SDMMC : R/W; bitpos: [29]; default: 0;
+ *  hp sdmmc force norst
+ */
+#define LP_CLKRST_FORCE_NORST_SDMMC    (BIT(29))
+#define LP_CLKRST_FORCE_NORST_SDMMC_M  (LP_CLKRST_FORCE_NORST_SDMMC_V << LP_CLKRST_FORCE_NORST_SDMMC_S)
+#define LP_CLKRST_FORCE_NORST_SDMMC_V  0x00000001U
+#define LP_CLKRST_FORCE_NORST_SDMMC_S  29
+/** LP_CLKRST_RST_EN_EMAC : R/W; bitpos: [30]; default: 0;
+ *  hp emac reset en
+ */
+#define LP_CLKRST_RST_EN_EMAC    (BIT(30))
+#define LP_CLKRST_RST_EN_EMAC_M  (LP_CLKRST_RST_EN_EMAC_V << LP_CLKRST_RST_EN_EMAC_S)
+#define LP_CLKRST_RST_EN_EMAC_V  0x00000001U
+#define LP_CLKRST_RST_EN_EMAC_S  30
+/** LP_CLKRST_FORCE_NORST_EMAC : R/W; bitpos: [31]; default: 0;
+ *  hp emac force norst
+ */
+#define LP_CLKRST_FORCE_NORST_EMAC    (BIT(31))
+#define LP_CLKRST_FORCE_NORST_EMAC_M  (LP_CLKRST_FORCE_NORST_EMAC_V << LP_CLKRST_FORCE_NORST_EMAC_S)
+#define LP_CLKRST_FORCE_NORST_EMAC_V  0x00000001U
+#define LP_CLKRST_FORCE_NORST_EMAC_S  31
+
+/** LP_CLKRST_DATE_REG register
+ *  need_des
+ */
+#define LP_CLKRST_DATE_REG (DR_REG_LP_CLKRST_BASE + 0x3fc)
+/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define LP_CLKRST_CLK_EN    (BIT(31))
+#define LP_CLKRST_CLK_EN_M  (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
+#define LP_CLKRST_CLK_EN_V  0x00000001U
+#define LP_CLKRST_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/lp_clkrst_struct.h b/components/soc/esp32p4/register/soc/lp_clkrst_struct.h
new file mode 100644
index 00000000000..b21775966a1
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/lp_clkrst_struct.h
@@ -0,0 +1,797 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of lp_clk_conf register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t slow_clk_sel:2;
+        /** fast_clk_sel : R/W; bitpos: [3:2]; default: 1;
+         *  need_des
+         */
+        uint32_t fast_clk_sel:2;
+        /** lp_peri_div_num : R/W; bitpos: [9:4]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_peri_div_num:6;
+        /** ana_sel_ref_pll8m : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t ana_sel_ref_pll8m:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_conf_reg_t;
+
+/** Type of lp_clk_po_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** clk_core_efuse_oen : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_core_efuse_oen:1;
+        /** clk_lp_bus_oen : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_lp_bus_oen:1;
+        /** clk_aon_slow_oen : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_aon_slow_oen:1;
+        /** clk_aon_fast_oen : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_aon_fast_oen:1;
+        /** clk_slow_oen : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_slow_oen:1;
+        /** clk_fast_oen : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_fast_oen:1;
+        /** clk_fosc_oen : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_fosc_oen:1;
+        /** clk_rc32k_oen : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_rc32k_oen:1;
+        /** clk_sxtal_oen : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_sxtal_oen:1;
+        /** clk_sosc_oen : R/W; bitpos: [9]; default: 0;
+         *  1'b1: probe sosc clk on
+         *  1'b0: probe sosc clk off
+         */
+        uint32_t clk_sosc_oen:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_po_en_reg_t;
+
+/** Type of lp_clk_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** lp_rtc_xtal_force_on : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lp_rtc_xtal_force_on:1;
+        /** ck_en_lp_ram : R/W; bitpos: [27]; default: 1;
+         *  need_des
+         */
+        uint32_t ck_en_lp_ram:1;
+        /** etm_event_tick_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t etm_event_tick_en:1;
+        /** pll8m_clk_force_on : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t pll8m_clk_force_on:1;
+        /** xtal_clk_force_on : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t xtal_clk_force_on:1;
+        /** fosc_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t fosc_clk_force_on:1;
+    };
+    uint32_t val;
+} lp_clkrst_lp_clk_en_reg_t;
+
+/** Type of lp_rst_en register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** rst_en_lp_huk : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_huk:1;
+        /** rst_en_lp_anaperi : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_anaperi:1;
+        /** rst_en_lp_wdt : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_wdt:1;
+        /** rst_en_lp_timer : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_timer:1;
+        /** rst_en_lp_rtc : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_rtc:1;
+        /** rst_en_lp_mailbox : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_mailbox:1;
+        /** rst_en_lp_aonefusereg : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_aonefusereg:1;
+        /** rst_en_lp_ram : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t rst_en_lp_ram:1;
+    };
+    uint32_t val;
+} lp_clkrst_lp_rst_en_reg_t;
+
+/** Type of reset_cause register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** lpcore_reset_cause : RO; bitpos: [5:0]; default: 0;
+         *  6'h1: POR reset
+         *  6'h9: PMU LP PERI power down reset
+         *  6'ha: PMU LP CPU reset
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: software reset
+         */
+        uint32_t lpcore_reset_cause:6;
+        /** lpcore_reset_flag : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_flag:1;
+        /** hpcore0_reset_cause : RO; bitpos: [12:7]; default: 0;
+         *  6'h1: POR reset
+         *  6'h3: digital system software reset
+         *  6'h5: PMU HP system power down reset
+         *  6'h7: HP system reset from HP watchdog
+         *  6'h9: HP system reset from LP watchdog
+         *  6'hb: HP core reset from HP watchdog
+         *  6'hc: HP core software reset
+         *  6'hd: HP core reset from LP watchdog
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: efuse crc error reset
+         *  6'h16: HP usb jtag chip reset
+         *  6'h17: HP usb uart chip reset
+         *  6'h18: HP jtag reset
+         *  6'h1a: HP core lockup
+         */
+        uint32_t hpcore0_reset_cause:6;
+        /** hpcore0_reset_flag : RO; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_flag:1;
+        /** hpcore1_reset_cause : RO; bitpos: [19:14]; default: 0;
+         *  6'h1: POR reset
+         *  6'h3: digital system software reset
+         *  6'h5: PMU HP system power down reset
+         *  6'h7: HP system reset from HP watchdog
+         *  6'h9: HP system reset from LP watchdog
+         *  6'hb: HP core reset from HP watchdog
+         *  6'hc: HP core software reset
+         *  6'hd: HP core reset from LP watchdog
+         *  6'hf: brown out reset
+         *  6'h10: LP watchdog chip reset
+         *  6'h12: super watch dog reset
+         *  6'h13: glitch reset
+         *  6'h14: efuse crc error reset
+         *  6'h16: HP usb jtag chip reset
+         *  6'h17: HP usb uart chip reset
+         *  6'h18: HP jtag reset
+         *  6'h1a: HP core lockup
+         */
+        uint32_t hpcore1_reset_cause:6;
+        /** hpcore1_reset_flag : RO; bitpos: [20]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_flag:1;
+        uint32_t reserved_21:4;
+        /** lpcore_reset_cause_pmu_lp_cpu_mask : R/W; bitpos: [25]; default: 1;
+         *  1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore
+         *  pmu_lp_cpu_reset reset_cause
+         */
+        uint32_t lpcore_reset_cause_pmu_lp_cpu_mask:1;
+        /** lpcore_reset_cause_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_cause_clr:1;
+        /** lpcore_reset_flag_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t lpcore_reset_flag_clr:1;
+        /** hpcore0_reset_cause_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_cause_clr:1;
+        /** hpcore0_reset_flag_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_reset_flag_clr:1;
+        /** hpcore1_reset_cause_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_cause_clr:1;
+        /** hpcore1_reset_flag_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_reset_flag_clr:1;
+    };
+    uint32_t val;
+} lp_clkrst_reset_cause_reg_t;
+
+/** Type of hpcpu_reset_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpcore0_lockup_reset_en : R/W; bitpos: [0]; default: 0;
+         *  write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup
+         *  reset feature
+         */
+        uint32_t hpcore0_lockup_reset_en:1;
+        /** lp_wdt_hpcore0_reset_length : R/W; bitpos: [3:1]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_wdt_hpcore0_reset_length:3;
+        /** lp_wdt_hpcore0_reset_en : R/W; bitpos: [4]; default: 0;
+         *  write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset
+         *  hpcore0 feature
+         */
+        uint32_t lp_wdt_hpcore0_reset_en:1;
+        /** hpcore0_stall_wait : R/W; bitpos: [11:5]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_stall_wait:7;
+        /** hpcore0_stall_en : R/W; bitpos: [12]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_stall_en:1;
+        /** hpcore0_sw_reset : WT; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_sw_reset:1;
+        /** hpcore0_ocd_halt_on_reset : R/W; bitpos: [14]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore0_ocd_halt_on_reset:1;
+        /** hpcore0_stat_vector_sel : R/W; bitpos: [15]; default: 1;
+         *  1'b1: boot from HP TCM ROM: 0x4FC00000
+         *  1'b0: boot from LP TCM RAM:  0x50108000
+         */
+        uint32_t hpcore0_stat_vector_sel:1;
+        /** hpcore1_lockup_reset_en : R/W; bitpos: [16]; default: 0;
+         *  write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup
+         *  reset feature
+         */
+        uint32_t hpcore1_lockup_reset_en:1;
+        /** lp_wdt_hpcore1_reset_length : R/W; bitpos: [19:17]; default: 1;
+         *  need_des
+         */
+        uint32_t lp_wdt_hpcore1_reset_length:3;
+        /** lp_wdt_hpcore1_reset_en : R/W; bitpos: [20]; default: 0;
+         *  write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset
+         *  hpcore1 feature
+         */
+        uint32_t lp_wdt_hpcore1_reset_en:1;
+        /** hpcore1_stall_wait : R/W; bitpos: [27:21]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_stall_wait:7;
+        /** hpcore1_stall_en : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_stall_en:1;
+        /** hpcore1_sw_reset : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_sw_reset:1;
+        /** hpcore1_ocd_halt_on_reset : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t hpcore1_ocd_halt_on_reset:1;
+        /** hpcore1_stat_vector_sel : R/W; bitpos: [31]; default: 1;
+         *  1'b1: boot from HP TCM ROM: 0x4FC00000
+         *  1'b0: boot from LP TCM RAM:  0x50108000
+         */
+        uint32_t hpcore1_stat_vector_sel:1;
+    };
+    uint32_t val;
+} lp_clkrst_hpcpu_reset_ctrl0_reg_t;
+
+/** Type of hpcpu_reset_ctrl1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** hpcore0_sw_stall_code : R/W; bitpos: [23:16]; default: 0;
+         *  HP core0 software stall when set to 8'h86
+         */
+        uint32_t hpcore0_sw_stall_code:8;
+        /** hpcore1_sw_stall_code : R/W; bitpos: [31:24]; default: 0;
+         *  HP core1 software stall when set to 8'h86
+         */
+        uint32_t hpcore1_sw_stall_code:8;
+    };
+    uint32_t val;
+} lp_clkrst_hpcpu_reset_ctrl1_reg_t;
+
+/** Type of fosc_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** fosc_dfreq : R/W; bitpos: [31:22]; default: 400;
+         *  need_des
+         */
+        uint32_t fosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_clkrst_fosc_cntl_reg_t;
+
+/** Type of rc32k_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** rc32k_dfreq : R/W; bitpos: [31:0]; default: 650;
+         *  need_des
+         */
+        uint32_t rc32k_dfreq:32;
+    };
+    uint32_t val;
+} lp_clkrst_rc32k_cntl_reg_t;
+
+/** Type of sosc_cntl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** sosc_dfreq : R/W; bitpos: [31:22]; default: 172;
+         *  need_des
+         */
+        uint32_t sosc_dfreq:10;
+    };
+    uint32_t val;
+} lp_clkrst_sosc_cntl_reg_t;
+
+/** Type of clk_to_hp register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_xtal32k:1;
+        /** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_sosc:1;
+        /** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_osc32k:1;
+        /** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
+         *  reserved
+         */
+        uint32_t icg_hp_fosc:1;
+    };
+    uint32_t val;
+} lp_clkrst_clk_to_hp_reg_t;
+
+/** Type of lpmem_force register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t lpmem_clk_force_on:1;
+    };
+    uint32_t val;
+} lp_clkrst_lpmem_force_reg_t;
+
+/** Type of xtal32k register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
+         *  need_des
+         */
+        uint32_t dres_xtal32k:3;
+        /** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
+         *  need_des
+         */
+        uint32_t dgm_xtal32k:3;
+        /** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t dbuf_xtal32k:1;
+        /** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
+         *  need_des
+         */
+        uint32_t dac_xtal32k:3;
+    };
+    uint32_t val;
+} lp_clkrst_xtal32k_reg_t;
+
+/** Type of mux_hpsys_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** mux_hpsys_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t mux_hpsys_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_clkrst_mux_hpsys_reset_bypass_reg_t;
+
+/** Type of hpsys_0_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpsys_0_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t hpsys_0_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_clkrst_hpsys_0_reset_bypass_reg_t;
+
+/** Type of hpsys_apm_reset_bypass register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** hpsys_apm_reset_bypass : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t hpsys_apm_reset_bypass:32;
+    };
+    uint32_t val;
+} lp_clkrst_hpsys_apm_reset_bypass_reg_t;
+
+/** Type of hp_clk_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        /** hp_root_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m.
+         */
+        uint32_t hp_root_clk_src_sel:2;
+        /** hp_root_clk_en : R/W; bitpos: [2]; default: 1;
+         *  HP SoC Root Clock Enable.
+         */
+        uint32_t hp_root_clk_en:1;
+        /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [3]; default: 1;
+         *  PARLIO TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_tx_clk_en:1;
+        /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [4]; default: 1;
+         *  PARLIO RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_rx_clk_en:1;
+        /** hp_pad_uart4_slp_clk_en : R/W; bitpos: [5]; default: 1;
+         *  UART4 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart4_slp_clk_en:1;
+        /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [6]; default: 1;
+         *  UART3 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart3_slp_clk_en:1;
+        /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [7]; default: 1;
+         *  UART2 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart2_slp_clk_en:1;
+        /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [8]; default: 1;
+         *  UART1 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart1_slp_clk_en:1;
+        /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [9]; default: 1;
+         *  UART0 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart0_slp_clk_en:1;
+        /** hp_pad_i2s2_mclk_en : R/W; bitpos: [10]; default: 1;
+         *  I2S2 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s2_mclk_en:1;
+        /** hp_pad_i2s1_mclk_en : R/W; bitpos: [11]; default: 1;
+         *  I2S1 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s1_mclk_en:1;
+        /** hp_pad_i2s0_mclk_en : R/W; bitpos: [12]; default: 1;
+         *  I2S0 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s0_mclk_en:1;
+        /** hp_pad_emac_tx_clk_en : R/W; bitpos: [13]; default: 1;
+         *  EMAC RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_tx_clk_en:1;
+        /** hp_pad_emac_rx_clk_en : R/W; bitpos: [14]; default: 1;
+         *  EMAC TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_rx_clk_en:1;
+        /** hp_pad_emac_txrx_clk_en : R/W; bitpos: [15]; default: 1;
+         *  EMAC TXRX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_emac_txrx_clk_en:1;
+        /** hp_xtal_32k_clk_en : R/W; bitpos: [16]; default: 1;
+         *  XTAL 32K Clock Enable.
+         */
+        uint32_t hp_xtal_32k_clk_en:1;
+        /** hp_rc_32k_clk_en : R/W; bitpos: [17]; default: 1;
+         *  RC 32K Clock Enable.
+         */
+        uint32_t hp_rc_32k_clk_en:1;
+        /** hp_sosc_150k_clk_en : R/W; bitpos: [18]; default: 1;
+         *  SOSC 150K Clock Enable.
+         */
+        uint32_t hp_sosc_150k_clk_en:1;
+        /** hp_pll_8m_clk_en : R/W; bitpos: [19]; default: 1;
+         *  PLL 8M Clock Enable.
+         */
+        uint32_t hp_pll_8m_clk_en:1;
+        /** hp_audio_pll_clk_en : R/W; bitpos: [20]; default: 1;
+         *  AUDIO PLL Clock Enable.
+         */
+        uint32_t hp_audio_pll_clk_en:1;
+        /** hp_sdio_pll2_clk_en : R/W; bitpos: [21]; default: 1;
+         *  SDIO PLL2 Clock Enable.
+         */
+        uint32_t hp_sdio_pll2_clk_en:1;
+        /** hp_sdio_pll1_clk_en : R/W; bitpos: [22]; default: 1;
+         *  SDIO PLL1 Clock Enable.
+         */
+        uint32_t hp_sdio_pll1_clk_en:1;
+        /** hp_sdio_pll0_clk_en : R/W; bitpos: [23]; default: 1;
+         *  SDIO PLL0 Clock Enable.
+         */
+        uint32_t hp_sdio_pll0_clk_en:1;
+        /** hp_fosc_20m_clk_en : R/W; bitpos: [24]; default: 1;
+         *  FOSC 20M Clock Enable.
+         */
+        uint32_t hp_fosc_20m_clk_en:1;
+        /** hp_xtal_40m_clk_en : R/W; bitpos: [25]; default: 1;
+         *  XTAL 40M Clock Enable.
+         */
+        uint32_t hp_xtal_40m_clk_en:1;
+        /** hp_cpll_400m_clk_en : R/W; bitpos: [26]; default: 1;
+         *  CPLL 400M Clock Enable.
+         */
+        uint32_t hp_cpll_400m_clk_en:1;
+        /** hp_spll_480m_clk_en : R/W; bitpos: [27]; default: 1;
+         *  SPLL 480M Clock Enable.
+         */
+        uint32_t hp_spll_480m_clk_en:1;
+        /** hp_mpll_500m_clk_en : R/W; bitpos: [28]; default: 1;
+         *  MPLL 500M Clock Enable.
+         */
+        uint32_t hp_mpll_500m_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} lp_clkrst_hp_clk_ctrl_reg_t;
+
+/** Type of hp_usb_clkrst_ctrl0 register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        /** usb_otg20_sleep_mode : R/W; bitpos: [0]; default: 0;
+         *  unused.
+         */
+        uint32_t usb_otg20_sleep_mode:1;
+        /** usb_otg20_bk_sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  unused.
+         */
+        uint32_t usb_otg20_bk_sys_clk_en:1;
+        /** usb_otg11_sleep_mode : R/W; bitpos: [2]; default: 0;
+         *  unused.
+         */
+        uint32_t usb_otg11_sleep_mode:1;
+        /** usb_otg11_bk_sys_clk_en : R/W; bitpos: [3]; default: 1;
+         *  unused.
+         */
+        uint32_t usb_otg11_bk_sys_clk_en:1;
+        /** usb_otg11_48m_clk_en : R/W; bitpos: [4]; default: 1;
+         *  usb otg11 fs phy clock enable.
+         */
+        uint32_t usb_otg11_48m_clk_en:1;
+        /** usb_device_48m_clk_en : R/W; bitpos: [5]; default: 1;
+         *  usb device fs phy clock enable.
+         */
+        uint32_t usb_device_48m_clk_en:1;
+        /** usb_48m_div_num : R/W; bitpos: [13:6]; default: 9;
+         *  usb 480m to 25m divide number.
+         */
+        uint32_t usb_48m_div_num:8;
+        /** usb_25m_div_num : R/W; bitpos: [21:14]; default: 19;
+         *  usb 500m to 25m divide number.
+         */
+        uint32_t usb_25m_div_num:8;
+        /** usb_12m_div_num : R/W; bitpos: [29:22]; default: 39;
+         *  usb 480m to 12m divide number.
+         */
+        uint32_t usb_12m_div_num:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} lp_clkrst_hp_usb_clkrst_ctrl0_reg_t;
+
+/** Type of hp_usb_clkrst_ctrl1 register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        /** rst_en_usb_otg20_adp : R/W; bitpos: [0]; default: 0;
+         *  usb otg20 adp reset en
+         */
+        uint32_t rst_en_usb_otg20_adp:1;
+        /** rst_en_usb_otg20_phy : R/W; bitpos: [1]; default: 0;
+         *  usb otg20 phy reset en
+         */
+        uint32_t rst_en_usb_otg20_phy:1;
+        /** rst_en_usb_otg20 : R/W; bitpos: [2]; default: 0;
+         *  usb otg20 reset en
+         */
+        uint32_t rst_en_usb_otg20:1;
+        /** rst_en_usb_otg11 : R/W; bitpos: [3]; default: 0;
+         *  usb org11 reset en
+         */
+        uint32_t rst_en_usb_otg11:1;
+        /** rst_en_usb_device : R/W; bitpos: [4]; default: 0;
+         *  usb device reset en
+         */
+        uint32_t rst_en_usb_device:1;
+        uint32_t reserved_5:23;
+        /** usb_otg20_phyref_clk_src_sel : R/W; bitpos: [29:28]; default: 0;
+         *  usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk.
+         */
+        uint32_t usb_otg20_phyref_clk_src_sel:2;
+        /** usb_otg20_phyref_clk_en : R/W; bitpos: [30]; default: 1;
+         *  usb otg20 hs phy refclk enable.
+         */
+        uint32_t usb_otg20_phyref_clk_en:1;
+        /** usb_otg20_ulpi_clk_en : R/W; bitpos: [31]; default: 1;
+         *  usb otg20 ulpi clock enable.
+         */
+        uint32_t usb_otg20_ulpi_clk_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_hp_usb_clkrst_ctrl1_reg_t;
+
+/** Type of hp_sdmmc_emac_rst_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:28;
+        /** rst_en_sdmmc : R/W; bitpos: [28]; default: 0;
+         *  hp sdmmc reset en
+         */
+        uint32_t rst_en_sdmmc:1;
+        /** force_norst_sdmmc : R/W; bitpos: [29]; default: 0;
+         *  hp sdmmc force norst
+         */
+        uint32_t force_norst_sdmmc:1;
+        /** rst_en_emac : R/W; bitpos: [30]; default: 0;
+         *  hp emac reset en
+         */
+        uint32_t rst_en_emac:1;
+        /** force_norst_emac : R/W; bitpos: [31]; default: 0;
+         *  hp emac force norst
+         */
+        uint32_t force_norst_emac:1;
+    };
+    uint32_t val;
+} lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} lp_clkrst_date_reg_t;
+
+
+typedef struct {
+    volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
+    volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
+    volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
+    volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
+    volatile lp_clkrst_reset_cause_reg_t reset_cause;
+    volatile lp_clkrst_hpcpu_reset_ctrl0_reg_t hpcpu_reset_ctrl0;
+    volatile lp_clkrst_hpcpu_reset_ctrl1_reg_t hpcpu_reset_ctrl1;
+    volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
+    volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
+    volatile lp_clkrst_sosc_cntl_reg_t sosc_cntl;
+    volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
+    volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
+    volatile lp_clkrst_xtal32k_reg_t xtal32k;
+    volatile lp_clkrst_mux_hpsys_reset_bypass_reg_t mux_hpsys_reset_bypass;
+    volatile lp_clkrst_hpsys_0_reset_bypass_reg_t hpsys_0_reset_bypass;
+    volatile lp_clkrst_hpsys_apm_reset_bypass_reg_t hpsys_apm_reset_bypass;
+    volatile lp_clkrst_hp_clk_ctrl_reg_t hp_clk_ctrl;
+    volatile lp_clkrst_hp_usb_clkrst_ctrl0_reg_t hp_usb_clkrst_ctrl0;
+    volatile lp_clkrst_hp_usb_clkrst_ctrl1_reg_t hp_usb_clkrst_ctrl1;
+    volatile lp_clkrst_hp_sdmmc_emac_rst_ctrl_reg_t hp_sdmmc_emac_rst_ctrl;
+    uint32_t reserved_050[235];
+    volatile lp_clkrst_date_reg_t date;
+} lp_clkrst_dev_t;
+
+extern lp_clkrst_dev_t LP_AON_CLKRST;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_gpio_reg.h b/components/soc/esp32p4/register/soc/lp_gpio_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_gpio_reg.h
rename to components/soc/esp32p4/register/soc/lp_gpio_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_gpio_struct.h b/components/soc/esp32p4/register/soc/lp_gpio_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_gpio_struct.h
rename to components/soc/esp32p4/register/soc/lp_gpio_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_i2c_reg.h b/components/soc/esp32p4/register/soc/lp_i2c_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_i2c_reg.h
rename to components/soc/esp32p4/register/soc/lp_i2c_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_i2c_struct.h b/components/soc/esp32p4/register/soc/lp_i2c_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_i2c_struct.h
rename to components/soc/esp32p4/register/soc/lp_i2c_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_i2s_reg.h b/components/soc/esp32p4/register/soc/lp_i2s_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_i2s_reg.h
rename to components/soc/esp32p4/register/soc/lp_i2s_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_i2s_struct.h b/components/soc/esp32p4/register/soc/lp_i2s_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_i2s_struct.h
rename to components/soc/esp32p4/register/soc/lp_i2s_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_intr_reg.h b/components/soc/esp32p4/register/soc/lp_intr_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_intr_reg.h
rename to components/soc/esp32p4/register/soc/lp_intr_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_intr_struct.h b/components/soc/esp32p4/register/soc/lp_intr_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_intr_struct.h
rename to components/soc/esp32p4/register/soc/lp_intr_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_iomux_reg.h b/components/soc/esp32p4/register/soc/lp_iomux_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_iomux_reg.h
rename to components/soc/esp32p4/register/soc/lp_iomux_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_iomux_struct.h b/components/soc/esp32p4/register/soc/lp_iomux_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_iomux_struct.h
rename to components/soc/esp32p4/register/soc/lp_iomux_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_mailbox_reg.h b/components/soc/esp32p4/register/soc/lp_mailbox_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_mailbox_reg.h
rename to components/soc/esp32p4/register/soc/lp_mailbox_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_mailbox_struct.h b/components/soc/esp32p4/register/soc/lp_mailbox_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_mailbox_struct.h
rename to components/soc/esp32p4/register/soc/lp_mailbox_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_peri_pms_reg.h b/components/soc/esp32p4/register/soc/lp_peri_pms_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_peri_pms_reg.h
rename to components/soc/esp32p4/register/soc/lp_peri_pms_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_peri_pms_struct.h b/components/soc/esp32p4/register/soc/lp_peri_pms_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_peri_pms_struct.h
rename to components/soc/esp32p4/register/soc/lp_peri_pms_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_spi_reg.h b/components/soc/esp32p4/register/soc/lp_spi_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/lp_spi_reg.h
rename to components/soc/esp32p4/register/soc/lp_spi_reg.h
index c00998b2b82..5892adfe42c 100644
--- a/components/soc/esp32p4/include/soc/lp_spi_reg.h
+++ b/components/soc/esp32p4/register/soc/lp_spi_reg.h
@@ -126,7 +126,7 @@ extern "C" {
 #define LP_REG_CLKDIV_PRE_V  0x0000000FU
 #define LP_REG_CLKDIV_PRE_S  18
 /** LP_REG_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
- *  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system
+ *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
  *  clock. Can be configured in CONF state.
  */
 #define LP_REG_CLK_EQU_SYSCLK    (BIT(31))
@@ -1208,7 +1208,7 @@ extern "C" {
 /** LP_REG_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on. Can be configured in CONF state.
+ *  SPI clock is always on. Can be configured in CONF state.
  */
 #define LP_REG_CLK_MODE    0x00000003U
 #define LP_REG_CLK_MODE_M  (LP_REG_CLK_MODE_V << LP_REG_CLK_MODE_S)
diff --git a/components/soc/esp32p4/include/soc/lp_spi_struct.h b/components/soc/esp32p4/register/soc/lp_spi_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_spi_struct.h
rename to components/soc/esp32p4/register/soc/lp_spi_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_system_reg.h b/components/soc/esp32p4/register/soc/lp_system_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_system_reg.h
rename to components/soc/esp32p4/register/soc/lp_system_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_system_struct.h b/components/soc/esp32p4/register/soc/lp_system_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_system_struct.h
rename to components/soc/esp32p4/register/soc/lp_system_struct.h
diff --git a/components/soc/esp32p4/include/soc/lp_timer_reg.h b/components/soc/esp32p4/register/soc/lp_timer_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_timer_reg.h
rename to components/soc/esp32p4/register/soc/lp_timer_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_timer_struct.h b/components/soc/esp32p4/register/soc/lp_timer_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_timer_struct.h
rename to components/soc/esp32p4/register/soc/lp_timer_struct.h
diff --git a/components/soc/esp32p4/register/soc/lp_uart_reg.h b/components/soc/esp32p4/register/soc/lp_uart_reg.h
new file mode 100644
index 00000000000..d488866f781
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/lp_uart_reg.h
@@ -0,0 +1,1339 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** LP_UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define LP_UART_FIFO_REG (DR_REG_LP_UART_BASE + 0x0)
+/** LP_UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define LP_UART_RXFIFO_RD_BYTE    0x000000FFU
+#define LP_UART_RXFIFO_RD_BYTE_M  (LP_UART_RXFIFO_RD_BYTE_V << LP_UART_RXFIFO_RD_BYTE_S)
+#define LP_UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define LP_UART_RXFIFO_RD_BYTE_S  0
+
+/** LP_UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define LP_UART_INT_RAW_REG (DR_REG_LP_UART_BASE + 0x4)
+/** LP_UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define LP_UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_RAW_M  (LP_UART_RXFIFO_FULL_INT_RAW_V << LP_UART_RXFIFO_FULL_INT_RAW_S)
+#define LP_UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_RAW_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_M  (LP_UART_TXFIFO_EMPTY_INT_RAW_V << LP_UART_TXFIFO_EMPTY_INT_RAW_S)
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** LP_UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define LP_UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_RAW_M  (LP_UART_PARITY_ERR_INT_RAW_V << LP_UART_PARITY_ERR_INT_RAW_S)
+#define LP_UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_RAW_S  2
+/** LP_UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define LP_UART_FRM_ERR_INT_RAW    (BIT(3))
+#define LP_UART_FRM_ERR_INT_RAW_M  (LP_UART_FRM_ERR_INT_RAW_V << LP_UART_FRM_ERR_INT_RAW_S)
+#define LP_UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_RAW_S  3
+/** LP_UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define LP_UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_RAW_M  (LP_UART_RXFIFO_OVF_INT_RAW_V << LP_UART_RXFIFO_OVF_INT_RAW_S)
+#define LP_UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_RAW_S  4
+/** LP_UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define LP_UART_DSR_CHG_INT_RAW    (BIT(5))
+#define LP_UART_DSR_CHG_INT_RAW_M  (LP_UART_DSR_CHG_INT_RAW_V << LP_UART_DSR_CHG_INT_RAW_S)
+#define LP_UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_RAW_S  5
+/** LP_UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define LP_UART_CTS_CHG_INT_RAW    (BIT(6))
+#define LP_UART_CTS_CHG_INT_RAW_M  (LP_UART_CTS_CHG_INT_RAW_V << LP_UART_CTS_CHG_INT_RAW_S)
+#define LP_UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_RAW_S  6
+/** LP_UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define LP_UART_BRK_DET_INT_RAW    (BIT(7))
+#define LP_UART_BRK_DET_INT_RAW_M  (LP_UART_BRK_DET_INT_RAW_V << LP_UART_BRK_DET_INT_RAW_S)
+#define LP_UART_BRK_DET_INT_RAW_V  0x00000001U
+#define LP_UART_BRK_DET_INT_RAW_S  7
+/** LP_UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_RAW_M  (LP_UART_RXFIFO_TOUT_INT_RAW_V << LP_UART_RXFIFO_TOUT_INT_RAW_S)
+#define LP_UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_RAW_S  8
+/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define LP_UART_SW_XON_INT_RAW    (BIT(9))
+#define LP_UART_SW_XON_INT_RAW_M  (LP_UART_SW_XON_INT_RAW_V << LP_UART_SW_XON_INT_RAW_S)
+#define LP_UART_SW_XON_INT_RAW_V  0x00000001U
+#define LP_UART_SW_XON_INT_RAW_S  9
+/** LP_UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define LP_UART_SW_XOFF_INT_RAW    (BIT(10))
+#define LP_UART_SW_XOFF_INT_RAW_M  (LP_UART_SW_XOFF_INT_RAW_V << LP_UART_SW_XOFF_INT_RAW_S)
+#define LP_UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_RAW_S  10
+/** LP_UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define LP_UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_RAW_M  (LP_UART_GLITCH_DET_INT_RAW_V << LP_UART_GLITCH_DET_INT_RAW_S)
+#define LP_UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_RAW_S  11
+/** LP_UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define LP_UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_RAW_M  (LP_UART_TX_BRK_DONE_INT_RAW_V << LP_UART_TX_BRK_DONE_INT_RAW_S)
+#define LP_UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_RAW_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_M  (LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V << LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** LP_UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define LP_UART_TX_DONE_INT_RAW    (BIT(14))
+#define LP_UART_TX_DONE_INT_RAW_M  (LP_UART_TX_DONE_INT_RAW_V << LP_UART_TX_DONE_INT_RAW_S)
+#define LP_UART_TX_DONE_INT_RAW_V  0x00000001U
+#define LP_UART_TX_DONE_INT_RAW_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_M  (LP_UART_AT_CMD_CHAR_DET_INT_RAW_V << LP_UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** LP_UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define LP_UART_WAKEUP_INT_RAW    (BIT(19))
+#define LP_UART_WAKEUP_INT_RAW_M  (LP_UART_WAKEUP_INT_RAW_V << LP_UART_WAKEUP_INT_RAW_S)
+#define LP_UART_WAKEUP_INT_RAW_V  0x00000001U
+#define LP_UART_WAKEUP_INT_RAW_S  19
+
+/** LP_UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define LP_UART_INT_ST_REG (DR_REG_LP_UART_BASE + 0x8)
+/** LP_UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_ST_M  (LP_UART_RXFIFO_FULL_INT_ST_V << LP_UART_RXFIFO_FULL_INT_ST_S)
+#define LP_UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_ST_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_ST_M  (LP_UART_TXFIFO_EMPTY_INT_ST_V << LP_UART_TXFIFO_EMPTY_INT_ST_S)
+#define LP_UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_ST_S  1
+/** LP_UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define LP_UART_PARITY_ERR_INT_ST    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_ST_M  (LP_UART_PARITY_ERR_INT_ST_V << LP_UART_PARITY_ERR_INT_ST_S)
+#define LP_UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_ST_S  2
+/** LP_UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define LP_UART_FRM_ERR_INT_ST    (BIT(3))
+#define LP_UART_FRM_ERR_INT_ST_M  (LP_UART_FRM_ERR_INT_ST_V << LP_UART_FRM_ERR_INT_ST_S)
+#define LP_UART_FRM_ERR_INT_ST_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_ST_S  3
+/** LP_UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_ST_M  (LP_UART_RXFIFO_OVF_INT_ST_V << LP_UART_RXFIFO_OVF_INT_ST_S)
+#define LP_UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_ST_S  4
+/** LP_UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define LP_UART_DSR_CHG_INT_ST    (BIT(5))
+#define LP_UART_DSR_CHG_INT_ST_M  (LP_UART_DSR_CHG_INT_ST_V << LP_UART_DSR_CHG_INT_ST_S)
+#define LP_UART_DSR_CHG_INT_ST_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_ST_S  5
+/** LP_UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define LP_UART_CTS_CHG_INT_ST    (BIT(6))
+#define LP_UART_CTS_CHG_INT_ST_M  (LP_UART_CTS_CHG_INT_ST_V << LP_UART_CTS_CHG_INT_ST_S)
+#define LP_UART_CTS_CHG_INT_ST_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_ST_S  6
+/** LP_UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define LP_UART_BRK_DET_INT_ST    (BIT(7))
+#define LP_UART_BRK_DET_INT_ST_M  (LP_UART_BRK_DET_INT_ST_V << LP_UART_BRK_DET_INT_ST_S)
+#define LP_UART_BRK_DET_INT_ST_V  0x00000001U
+#define LP_UART_BRK_DET_INT_ST_S  7
+/** LP_UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_ST_M  (LP_UART_RXFIFO_TOUT_INT_ST_V << LP_UART_RXFIFO_TOUT_INT_ST_S)
+#define LP_UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_ST_S  8
+/** LP_UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define LP_UART_SW_XON_INT_ST    (BIT(9))
+#define LP_UART_SW_XON_INT_ST_M  (LP_UART_SW_XON_INT_ST_V << LP_UART_SW_XON_INT_ST_S)
+#define LP_UART_SW_XON_INT_ST_V  0x00000001U
+#define LP_UART_SW_XON_INT_ST_S  9
+/** LP_UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define LP_UART_SW_XOFF_INT_ST    (BIT(10))
+#define LP_UART_SW_XOFF_INT_ST_M  (LP_UART_SW_XOFF_INT_ST_V << LP_UART_SW_XOFF_INT_ST_S)
+#define LP_UART_SW_XOFF_INT_ST_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_ST_S  10
+/** LP_UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define LP_UART_GLITCH_DET_INT_ST    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_ST_M  (LP_UART_GLITCH_DET_INT_ST_V << LP_UART_GLITCH_DET_INT_ST_S)
+#define LP_UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_ST_S  11
+/** LP_UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define LP_UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_ST_M  (LP_UART_TX_BRK_DONE_INT_ST_V << LP_UART_TX_BRK_DONE_INT_ST_S)
+#define LP_UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_ST_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ST_V << LP_UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** LP_UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define LP_UART_TX_DONE_INT_ST    (BIT(14))
+#define LP_UART_TX_DONE_INT_ST_M  (LP_UART_TX_DONE_INT_ST_V << LP_UART_TX_DONE_INT_ST_S)
+#define LP_UART_TX_DONE_INT_ST_V  0x00000001U
+#define LP_UART_TX_DONE_INT_ST_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_M  (LP_UART_AT_CMD_CHAR_DET_INT_ST_V << LP_UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** LP_UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define LP_UART_WAKEUP_INT_ST    (BIT(19))
+#define LP_UART_WAKEUP_INT_ST_M  (LP_UART_WAKEUP_INT_ST_V << LP_UART_WAKEUP_INT_ST_S)
+#define LP_UART_WAKEUP_INT_ST_V  0x00000001U
+#define LP_UART_WAKEUP_INT_ST_S  19
+
+/** LP_UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define LP_UART_INT_ENA_REG (DR_REG_LP_UART_BASE + 0xc)
+/** LP_UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define LP_UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_ENA_M  (LP_UART_RXFIFO_FULL_INT_ENA_V << LP_UART_RXFIFO_FULL_INT_ENA_S)
+#define LP_UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_ENA_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_M  (LP_UART_TXFIFO_EMPTY_INT_ENA_V << LP_UART_TXFIFO_EMPTY_INT_ENA_S)
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** LP_UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define LP_UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_ENA_M  (LP_UART_PARITY_ERR_INT_ENA_V << LP_UART_PARITY_ERR_INT_ENA_S)
+#define LP_UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_ENA_S  2
+/** LP_UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define LP_UART_FRM_ERR_INT_ENA    (BIT(3))
+#define LP_UART_FRM_ERR_INT_ENA_M  (LP_UART_FRM_ERR_INT_ENA_V << LP_UART_FRM_ERR_INT_ENA_S)
+#define LP_UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_ENA_S  3
+/** LP_UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define LP_UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_ENA_M  (LP_UART_RXFIFO_OVF_INT_ENA_V << LP_UART_RXFIFO_OVF_INT_ENA_S)
+#define LP_UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_ENA_S  4
+/** LP_UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define LP_UART_DSR_CHG_INT_ENA    (BIT(5))
+#define LP_UART_DSR_CHG_INT_ENA_M  (LP_UART_DSR_CHG_INT_ENA_V << LP_UART_DSR_CHG_INT_ENA_S)
+#define LP_UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_ENA_S  5
+/** LP_UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define LP_UART_CTS_CHG_INT_ENA    (BIT(6))
+#define LP_UART_CTS_CHG_INT_ENA_M  (LP_UART_CTS_CHG_INT_ENA_V << LP_UART_CTS_CHG_INT_ENA_S)
+#define LP_UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_ENA_S  6
+/** LP_UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define LP_UART_BRK_DET_INT_ENA    (BIT(7))
+#define LP_UART_BRK_DET_INT_ENA_M  (LP_UART_BRK_DET_INT_ENA_V << LP_UART_BRK_DET_INT_ENA_S)
+#define LP_UART_BRK_DET_INT_ENA_V  0x00000001U
+#define LP_UART_BRK_DET_INT_ENA_S  7
+/** LP_UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_ENA_M  (LP_UART_RXFIFO_TOUT_INT_ENA_V << LP_UART_RXFIFO_TOUT_INT_ENA_S)
+#define LP_UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_ENA_S  8
+/** LP_UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define LP_UART_SW_XON_INT_ENA    (BIT(9))
+#define LP_UART_SW_XON_INT_ENA_M  (LP_UART_SW_XON_INT_ENA_V << LP_UART_SW_XON_INT_ENA_S)
+#define LP_UART_SW_XON_INT_ENA_V  0x00000001U
+#define LP_UART_SW_XON_INT_ENA_S  9
+/** LP_UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define LP_UART_SW_XOFF_INT_ENA    (BIT(10))
+#define LP_UART_SW_XOFF_INT_ENA_M  (LP_UART_SW_XOFF_INT_ENA_V << LP_UART_SW_XOFF_INT_ENA_S)
+#define LP_UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_ENA_S  10
+/** LP_UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define LP_UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_ENA_M  (LP_UART_GLITCH_DET_INT_ENA_V << LP_UART_GLITCH_DET_INT_ENA_S)
+#define LP_UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_ENA_S  11
+/** LP_UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define LP_UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_ENA_M  (LP_UART_TX_BRK_DONE_INT_ENA_V << LP_UART_TX_BRK_DONE_INT_ENA_S)
+#define LP_UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_ENA_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_M  (LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V << LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** LP_UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define LP_UART_TX_DONE_INT_ENA    (BIT(14))
+#define LP_UART_TX_DONE_INT_ENA_M  (LP_UART_TX_DONE_INT_ENA_V << LP_UART_TX_DONE_INT_ENA_S)
+#define LP_UART_TX_DONE_INT_ENA_V  0x00000001U
+#define LP_UART_TX_DONE_INT_ENA_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_M  (LP_UART_AT_CMD_CHAR_DET_INT_ENA_V << LP_UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** LP_UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define LP_UART_WAKEUP_INT_ENA    (BIT(19))
+#define LP_UART_WAKEUP_INT_ENA_M  (LP_UART_WAKEUP_INT_ENA_V << LP_UART_WAKEUP_INT_ENA_S)
+#define LP_UART_WAKEUP_INT_ENA_V  0x00000001U
+#define LP_UART_WAKEUP_INT_ENA_S  19
+
+/** LP_UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define LP_UART_INT_CLR_REG (DR_REG_LP_UART_BASE + 0x10)
+/** LP_UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define LP_UART_RXFIFO_FULL_INT_CLR_M  (LP_UART_RXFIFO_FULL_INT_CLR_V << LP_UART_RXFIFO_FULL_INT_CLR_S)
+#define LP_UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_FULL_INT_CLR_S  0
+/** LP_UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define LP_UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_M  (LP_UART_TXFIFO_EMPTY_INT_CLR_V << LP_UART_TXFIFO_EMPTY_INT_CLR_S)
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define LP_UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** LP_UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define LP_UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define LP_UART_PARITY_ERR_INT_CLR_M  (LP_UART_PARITY_ERR_INT_CLR_V << LP_UART_PARITY_ERR_INT_CLR_S)
+#define LP_UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define LP_UART_PARITY_ERR_INT_CLR_S  2
+/** LP_UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define LP_UART_FRM_ERR_INT_CLR    (BIT(3))
+#define LP_UART_FRM_ERR_INT_CLR_M  (LP_UART_FRM_ERR_INT_CLR_V << LP_UART_FRM_ERR_INT_CLR_S)
+#define LP_UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define LP_UART_FRM_ERR_INT_CLR_S  3
+/** LP_UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define LP_UART_RXFIFO_OVF_INT_CLR_M  (LP_UART_RXFIFO_OVF_INT_CLR_V << LP_UART_RXFIFO_OVF_INT_CLR_S)
+#define LP_UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_OVF_INT_CLR_S  4
+/** LP_UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define LP_UART_DSR_CHG_INT_CLR    (BIT(5))
+#define LP_UART_DSR_CHG_INT_CLR_M  (LP_UART_DSR_CHG_INT_CLR_V << LP_UART_DSR_CHG_INT_CLR_S)
+#define LP_UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define LP_UART_DSR_CHG_INT_CLR_S  5
+/** LP_UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define LP_UART_CTS_CHG_INT_CLR    (BIT(6))
+#define LP_UART_CTS_CHG_INT_CLR_M  (LP_UART_CTS_CHG_INT_CLR_V << LP_UART_CTS_CHG_INT_CLR_S)
+#define LP_UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define LP_UART_CTS_CHG_INT_CLR_S  6
+/** LP_UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define LP_UART_BRK_DET_INT_CLR    (BIT(7))
+#define LP_UART_BRK_DET_INT_CLR_M  (LP_UART_BRK_DET_INT_CLR_V << LP_UART_BRK_DET_INT_CLR_S)
+#define LP_UART_BRK_DET_INT_CLR_V  0x00000001U
+#define LP_UART_BRK_DET_INT_CLR_S  7
+/** LP_UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define LP_UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define LP_UART_RXFIFO_TOUT_INT_CLR_M  (LP_UART_RXFIFO_TOUT_INT_CLR_V << LP_UART_RXFIFO_TOUT_INT_CLR_S)
+#define LP_UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define LP_UART_RXFIFO_TOUT_INT_CLR_S  8
+/** LP_UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define LP_UART_SW_XON_INT_CLR    (BIT(9))
+#define LP_UART_SW_XON_INT_CLR_M  (LP_UART_SW_XON_INT_CLR_V << LP_UART_SW_XON_INT_CLR_S)
+#define LP_UART_SW_XON_INT_CLR_V  0x00000001U
+#define LP_UART_SW_XON_INT_CLR_S  9
+/** LP_UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define LP_UART_SW_XOFF_INT_CLR    (BIT(10))
+#define LP_UART_SW_XOFF_INT_CLR_M  (LP_UART_SW_XOFF_INT_CLR_V << LP_UART_SW_XOFF_INT_CLR_S)
+#define LP_UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define LP_UART_SW_XOFF_INT_CLR_S  10
+/** LP_UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define LP_UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define LP_UART_GLITCH_DET_INT_CLR_M  (LP_UART_GLITCH_DET_INT_CLR_V << LP_UART_GLITCH_DET_INT_CLR_S)
+#define LP_UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define LP_UART_GLITCH_DET_INT_CLR_S  11
+/** LP_UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define LP_UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define LP_UART_TX_BRK_DONE_INT_CLR_M  (LP_UART_TX_BRK_DONE_INT_CLR_V << LP_UART_TX_BRK_DONE_INT_CLR_S)
+#define LP_UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_BRK_DONE_INT_CLR_S  12
+/** LP_UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_M  (LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V << LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** LP_UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define LP_UART_TX_DONE_INT_CLR    (BIT(14))
+#define LP_UART_TX_DONE_INT_CLR_M  (LP_UART_TX_DONE_INT_CLR_V << LP_UART_TX_DONE_INT_CLR_S)
+#define LP_UART_TX_DONE_INT_CLR_V  0x00000001U
+#define LP_UART_TX_DONE_INT_CLR_S  14
+/** LP_UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_M  (LP_UART_AT_CMD_CHAR_DET_INT_CLR_V << LP_UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define LP_UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** LP_UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define LP_UART_WAKEUP_INT_CLR    (BIT(19))
+#define LP_UART_WAKEUP_INT_CLR_M  (LP_UART_WAKEUP_INT_CLR_V << LP_UART_WAKEUP_INT_CLR_S)
+#define LP_UART_WAKEUP_INT_CLR_V  0x00000001U
+#define LP_UART_WAKEUP_INT_CLR_S  19
+
+/** LP_UART_CLKDIV_SYNC_REG register
+ *  Clock divider configuration
+ */
+#define LP_UART_CLKDIV_SYNC_REG (DR_REG_LP_UART_BASE + 0x14)
+/** LP_UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define LP_UART_CLKDIV    0x00000FFFU
+#define LP_UART_CLKDIV_M  (LP_UART_CLKDIV_V << LP_UART_CLKDIV_S)
+#define LP_UART_CLKDIV_V  0x00000FFFU
+#define LP_UART_CLKDIV_S  0
+/** LP_UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define LP_UART_CLKDIV_FRAG    0x0000000FU
+#define LP_UART_CLKDIV_FRAG_M  (LP_UART_CLKDIV_FRAG_V << LP_UART_CLKDIV_FRAG_S)
+#define LP_UART_CLKDIV_FRAG_V  0x0000000FU
+#define LP_UART_CLKDIV_FRAG_S  20
+
+/** LP_UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define LP_UART_RX_FILT_REG (DR_REG_LP_UART_BASE + 0x18)
+/** LP_UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define LP_UART_GLITCH_FILT    0x000000FFU
+#define LP_UART_GLITCH_FILT_M  (LP_UART_GLITCH_FILT_V << LP_UART_GLITCH_FILT_S)
+#define LP_UART_GLITCH_FILT_V  0x000000FFU
+#define LP_UART_GLITCH_FILT_S  0
+/** LP_UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define LP_UART_GLITCH_FILT_EN    (BIT(8))
+#define LP_UART_GLITCH_FILT_EN_M  (LP_UART_GLITCH_FILT_EN_V << LP_UART_GLITCH_FILT_EN_S)
+#define LP_UART_GLITCH_FILT_EN_V  0x00000001U
+#define LP_UART_GLITCH_FILT_EN_S  8
+
+/** LP_UART_STATUS_REG register
+ *  UART status register
+ */
+#define LP_UART_STATUS_REG (DR_REG_LP_UART_BASE + 0x1c)
+/** LP_UART_RXFIFO_CNT : RO; bitpos: [7:3]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define LP_UART_RXFIFO_CNT    0x0000001FU
+#define LP_UART_RXFIFO_CNT_M  (LP_UART_RXFIFO_CNT_V << LP_UART_RXFIFO_CNT_S)
+#define LP_UART_RXFIFO_CNT_V  0x0000001FU
+#define LP_UART_RXFIFO_CNT_S  3
+/** LP_UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define LP_UART_DSRN    (BIT(13))
+#define LP_UART_DSRN_M  (LP_UART_DSRN_V << LP_UART_DSRN_S)
+#define LP_UART_DSRN_V  0x00000001U
+#define LP_UART_DSRN_S  13
+/** LP_UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define LP_UART_CTSN    (BIT(14))
+#define LP_UART_CTSN_M  (LP_UART_CTSN_V << LP_UART_CTSN_S)
+#define LP_UART_CTSN_V  0x00000001U
+#define LP_UART_CTSN_S  14
+/** LP_UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define LP_UART_RXD    (BIT(15))
+#define LP_UART_RXD_M  (LP_UART_RXD_V << LP_UART_RXD_S)
+#define LP_UART_RXD_V  0x00000001U
+#define LP_UART_RXD_S  15
+/** LP_UART_TXFIFO_CNT : RO; bitpos: [23:19]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define LP_UART_TXFIFO_CNT    0x0000001FU
+#define LP_UART_TXFIFO_CNT_M  (LP_UART_TXFIFO_CNT_V << LP_UART_TXFIFO_CNT_S)
+#define LP_UART_TXFIFO_CNT_V  0x0000001FU
+#define LP_UART_TXFIFO_CNT_S  19
+/** LP_UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define LP_UART_DTRN    (BIT(29))
+#define LP_UART_DTRN_M  (LP_UART_DTRN_V << LP_UART_DTRN_S)
+#define LP_UART_DTRN_V  0x00000001U
+#define LP_UART_DTRN_S  29
+/** LP_UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define LP_UART_RTSN    (BIT(30))
+#define LP_UART_RTSN_M  (LP_UART_RTSN_V << LP_UART_RTSN_S)
+#define LP_UART_RTSN_V  0x00000001U
+#define LP_UART_RTSN_S  30
+/** LP_UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define LP_UART_TXD    (BIT(31))
+#define LP_UART_TXD_M  (LP_UART_TXD_V << LP_UART_TXD_S)
+#define LP_UART_TXD_V  0x00000001U
+#define LP_UART_TXD_S  31
+
+/** LP_UART_CONF0_SYNC_REG register
+ *  Configuration register 0
+ */
+#define LP_UART_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x20)
+/** LP_UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define LP_UART_PARITY    (BIT(0))
+#define LP_UART_PARITY_M  (LP_UART_PARITY_V << LP_UART_PARITY_S)
+#define LP_UART_PARITY_V  0x00000001U
+#define LP_UART_PARITY_S  0
+/** LP_UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define LP_UART_PARITY_EN    (BIT(1))
+#define LP_UART_PARITY_EN_M  (LP_UART_PARITY_EN_V << LP_UART_PARITY_EN_S)
+#define LP_UART_PARITY_EN_V  0x00000001U
+#define LP_UART_PARITY_EN_S  1
+/** LP_UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define LP_UART_BIT_NUM    0x00000003U
+#define LP_UART_BIT_NUM_M  (LP_UART_BIT_NUM_V << LP_UART_BIT_NUM_S)
+#define LP_UART_BIT_NUM_V  0x00000003U
+#define LP_UART_BIT_NUM_S  2
+/** LP_UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define LP_UART_STOP_BIT_NUM    0x00000003U
+#define LP_UART_STOP_BIT_NUM_M  (LP_UART_STOP_BIT_NUM_V << LP_UART_STOP_BIT_NUM_S)
+#define LP_UART_STOP_BIT_NUM_V  0x00000003U
+#define LP_UART_STOP_BIT_NUM_S  4
+/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define LP_UART_TXD_BRK    (BIT(6))
+#define LP_UART_TXD_BRK_M  (LP_UART_TXD_BRK_V << LP_UART_TXD_BRK_S)
+#define LP_UART_TXD_BRK_V  0x00000001U
+#define LP_UART_TXD_BRK_S  6
+/** LP_UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define LP_UART_LOOPBACK    (BIT(12))
+#define LP_UART_LOOPBACK_M  (LP_UART_LOOPBACK_V << LP_UART_LOOPBACK_S)
+#define LP_UART_LOOPBACK_V  0x00000001U
+#define LP_UART_LOOPBACK_S  12
+/** LP_UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define LP_UART_TX_FLOW_EN    (BIT(13))
+#define LP_UART_TX_FLOW_EN_M  (LP_UART_TX_FLOW_EN_V << LP_UART_TX_FLOW_EN_S)
+#define LP_UART_TX_FLOW_EN_V  0x00000001U
+#define LP_UART_TX_FLOW_EN_S  13
+/** LP_UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define LP_UART_RXD_INV    (BIT(15))
+#define LP_UART_RXD_INV_M  (LP_UART_RXD_INV_V << LP_UART_RXD_INV_S)
+#define LP_UART_RXD_INV_V  0x00000001U
+#define LP_UART_RXD_INV_S  15
+/** LP_UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define LP_UART_TXD_INV    (BIT(16))
+#define LP_UART_TXD_INV_M  (LP_UART_TXD_INV_V << LP_UART_TXD_INV_S)
+#define LP_UART_TXD_INV_V  0x00000001U
+#define LP_UART_TXD_INV_S  16
+/** LP_UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define LP_UART_DIS_RX_DAT_OVF    (BIT(17))
+#define LP_UART_DIS_RX_DAT_OVF_M  (LP_UART_DIS_RX_DAT_OVF_V << LP_UART_DIS_RX_DAT_OVF_S)
+#define LP_UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define LP_UART_DIS_RX_DAT_OVF_S  17
+/** LP_UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define LP_UART_ERR_WR_MASK    (BIT(18))
+#define LP_UART_ERR_WR_MASK_M  (LP_UART_ERR_WR_MASK_V << LP_UART_ERR_WR_MASK_S)
+#define LP_UART_ERR_WR_MASK_V  0x00000001U
+#define LP_UART_ERR_WR_MASK_S  18
+/** LP_UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  UART memory clock gate enable signal.
+ */
+#define LP_UART_MEM_CLK_EN    (BIT(20))
+#define LP_UART_MEM_CLK_EN_M  (LP_UART_MEM_CLK_EN_V << LP_UART_MEM_CLK_EN_S)
+#define LP_UART_MEM_CLK_EN_V  0x00000001U
+#define LP_UART_MEM_CLK_EN_S  20
+/** LP_UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define LP_UART_SW_RTS    (BIT(21))
+#define LP_UART_SW_RTS_M  (LP_UART_SW_RTS_V << LP_UART_SW_RTS_S)
+#define LP_UART_SW_RTS_V  0x00000001U
+#define LP_UART_SW_RTS_S  21
+/** LP_UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define LP_UART_RXFIFO_RST    (BIT(22))
+#define LP_UART_RXFIFO_RST_M  (LP_UART_RXFIFO_RST_V << LP_UART_RXFIFO_RST_S)
+#define LP_UART_RXFIFO_RST_V  0x00000001U
+#define LP_UART_RXFIFO_RST_S  22
+/** LP_UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define LP_UART_TXFIFO_RST    (BIT(23))
+#define LP_UART_TXFIFO_RST_M  (LP_UART_TXFIFO_RST_V << LP_UART_TXFIFO_RST_S)
+#define LP_UART_TXFIFO_RST_V  0x00000001U
+#define LP_UART_TXFIFO_RST_S  23
+
+/** LP_UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define LP_UART_CONF1_REG (DR_REG_LP_UART_BASE + 0x24)
+/** LP_UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:3]; default: 12;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define LP_UART_RXFIFO_FULL_THRHD    0x0000001FU
+#define LP_UART_RXFIFO_FULL_THRHD_M  (LP_UART_RXFIFO_FULL_THRHD_V << LP_UART_RXFIFO_FULL_THRHD_S)
+#define LP_UART_RXFIFO_FULL_THRHD_V  0x0000001FU
+#define LP_UART_RXFIFO_FULL_THRHD_S  3
+/** LP_UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:11]; default: 12;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define LP_UART_TXFIFO_EMPTY_THRHD    0x0000001FU
+#define LP_UART_TXFIFO_EMPTY_THRHD_M  (LP_UART_TXFIFO_EMPTY_THRHD_V << LP_UART_TXFIFO_EMPTY_THRHD_S)
+#define LP_UART_TXFIFO_EMPTY_THRHD_V  0x0000001FU
+#define LP_UART_TXFIFO_EMPTY_THRHD_S  11
+/** LP_UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define LP_UART_CTS_INV    (BIT(16))
+#define LP_UART_CTS_INV_M  (LP_UART_CTS_INV_V << LP_UART_CTS_INV_S)
+#define LP_UART_CTS_INV_V  0x00000001U
+#define LP_UART_CTS_INV_S  16
+/** LP_UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define LP_UART_DSR_INV    (BIT(17))
+#define LP_UART_DSR_INV_M  (LP_UART_DSR_INV_V << LP_UART_DSR_INV_S)
+#define LP_UART_DSR_INV_V  0x00000001U
+#define LP_UART_DSR_INV_S  17
+/** LP_UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define LP_UART_RTS_INV    (BIT(18))
+#define LP_UART_RTS_INV_M  (LP_UART_RTS_INV_V << LP_UART_RTS_INV_S)
+#define LP_UART_RTS_INV_V  0x00000001U
+#define LP_UART_RTS_INV_S  18
+/** LP_UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define LP_UART_DTR_INV    (BIT(19))
+#define LP_UART_DTR_INV_M  (LP_UART_DTR_INV_V << LP_UART_DTR_INV_S)
+#define LP_UART_DTR_INV_V  0x00000001U
+#define LP_UART_DTR_INV_S  19
+/** LP_UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define LP_UART_SW_DTR    (BIT(20))
+#define LP_UART_SW_DTR_M  (LP_UART_SW_DTR_V << LP_UART_SW_DTR_S)
+#define LP_UART_SW_DTR_V  0x00000001U
+#define LP_UART_SW_DTR_S  20
+/** LP_UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define LP_UART_CLK_EN    (BIT(21))
+#define LP_UART_CLK_EN_M  (LP_UART_CLK_EN_V << LP_UART_CLK_EN_S)
+#define LP_UART_CLK_EN_V  0x00000001U
+#define LP_UART_CLK_EN_S  21
+
+/** LP_UART_HWFC_CONF_SYNC_REG register
+ *  Hardware flow-control configuration
+ */
+#define LP_UART_HWFC_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x2c)
+/** LP_UART_RX_FLOW_THRHD : R/W; bitpos: [7:3]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define LP_UART_RX_FLOW_THRHD    0x0000001FU
+#define LP_UART_RX_FLOW_THRHD_M  (LP_UART_RX_FLOW_THRHD_V << LP_UART_RX_FLOW_THRHD_S)
+#define LP_UART_RX_FLOW_THRHD_V  0x0000001FU
+#define LP_UART_RX_FLOW_THRHD_S  3
+/** LP_UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define LP_UART_RX_FLOW_EN    (BIT(8))
+#define LP_UART_RX_FLOW_EN_M  (LP_UART_RX_FLOW_EN_V << LP_UART_RX_FLOW_EN_S)
+#define LP_UART_RX_FLOW_EN_V  0x00000001U
+#define LP_UART_RX_FLOW_EN_S  8
+
+/** LP_UART_SLEEP_CONF0_REG register
+ *  UART sleep configure register 0
+ */
+#define LP_UART_SLEEP_CONF0_REG (DR_REG_LP_UART_BASE + 0x30)
+/** LP_UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define LP_UART_WK_CHAR1    0x000000FFU
+#define LP_UART_WK_CHAR1_M  (LP_UART_WK_CHAR1_V << LP_UART_WK_CHAR1_S)
+#define LP_UART_WK_CHAR1_V  0x000000FFU
+#define LP_UART_WK_CHAR1_S  0
+/** LP_UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define LP_UART_WK_CHAR2    0x000000FFU
+#define LP_UART_WK_CHAR2_M  (LP_UART_WK_CHAR2_V << LP_UART_WK_CHAR2_S)
+#define LP_UART_WK_CHAR2_V  0x000000FFU
+#define LP_UART_WK_CHAR2_S  8
+/** LP_UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define LP_UART_WK_CHAR3    0x000000FFU
+#define LP_UART_WK_CHAR3_M  (LP_UART_WK_CHAR3_V << LP_UART_WK_CHAR3_S)
+#define LP_UART_WK_CHAR3_V  0x000000FFU
+#define LP_UART_WK_CHAR3_S  16
+/** LP_UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define LP_UART_WK_CHAR4    0x000000FFU
+#define LP_UART_WK_CHAR4_M  (LP_UART_WK_CHAR4_V << LP_UART_WK_CHAR4_S)
+#define LP_UART_WK_CHAR4_V  0x000000FFU
+#define LP_UART_WK_CHAR4_S  24
+
+/** LP_UART_SLEEP_CONF1_REG register
+ *  UART sleep configure register 1
+ */
+#define LP_UART_SLEEP_CONF1_REG (DR_REG_LP_UART_BASE + 0x34)
+/** LP_UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define LP_UART_WK_CHAR0    0x000000FFU
+#define LP_UART_WK_CHAR0_M  (LP_UART_WK_CHAR0_V << LP_UART_WK_CHAR0_S)
+#define LP_UART_WK_CHAR0_V  0x000000FFU
+#define LP_UART_WK_CHAR0_S  0
+
+/** LP_UART_SLEEP_CONF2_REG register
+ *  UART sleep configure register 2
+ */
+#define LP_UART_SLEEP_CONF2_REG (DR_REG_LP_UART_BASE + 0x38)
+/** LP_UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define LP_UART_ACTIVE_THRESHOLD    0x000003FFU
+#define LP_UART_ACTIVE_THRESHOLD_M  (LP_UART_ACTIVE_THRESHOLD_V << LP_UART_ACTIVE_THRESHOLD_S)
+#define LP_UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define LP_UART_ACTIVE_THRESHOLD_S  0
+/** LP_UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:13]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define LP_UART_RX_WAKE_UP_THRHD    0x0000001FU
+#define LP_UART_RX_WAKE_UP_THRHD_M  (LP_UART_RX_WAKE_UP_THRHD_V << LP_UART_RX_WAKE_UP_THRHD_S)
+#define LP_UART_RX_WAKE_UP_THRHD_V  0x0000001FU
+#define LP_UART_RX_WAKE_UP_THRHD_S  13
+/** LP_UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define LP_UART_WK_CHAR_NUM    0x00000007U
+#define LP_UART_WK_CHAR_NUM_M  (LP_UART_WK_CHAR_NUM_V << LP_UART_WK_CHAR_NUM_S)
+#define LP_UART_WK_CHAR_NUM_V  0x00000007U
+#define LP_UART_WK_CHAR_NUM_S  18
+/** LP_UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define LP_UART_WK_CHAR_MASK    0x0000001FU
+#define LP_UART_WK_CHAR_MASK_M  (LP_UART_WK_CHAR_MASK_V << LP_UART_WK_CHAR_MASK_S)
+#define LP_UART_WK_CHAR_MASK_V  0x0000001FU
+#define LP_UART_WK_CHAR_MASK_S  21
+/** LP_UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define LP_UART_WK_MODE_SEL    0x00000003U
+#define LP_UART_WK_MODE_SEL_M  (LP_UART_WK_MODE_SEL_V << LP_UART_WK_MODE_SEL_S)
+#define LP_UART_WK_MODE_SEL_V  0x00000003U
+#define LP_UART_WK_MODE_SEL_S  26
+
+/** LP_UART_SWFC_CONF0_SYNC_REG register
+ *  Software flow-control character configuration
+ */
+#define LP_UART_SWFC_CONF0_SYNC_REG (DR_REG_LP_UART_BASE + 0x3c)
+/** LP_UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define LP_UART_XON_CHAR    0x000000FFU
+#define LP_UART_XON_CHAR_M  (LP_UART_XON_CHAR_V << LP_UART_XON_CHAR_S)
+#define LP_UART_XON_CHAR_V  0x000000FFU
+#define LP_UART_XON_CHAR_S  0
+/** LP_UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define LP_UART_XOFF_CHAR    0x000000FFU
+#define LP_UART_XOFF_CHAR_M  (LP_UART_XOFF_CHAR_V << LP_UART_XOFF_CHAR_S)
+#define LP_UART_XOFF_CHAR_V  0x000000FFU
+#define LP_UART_XOFF_CHAR_S  8
+/** LP_UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define LP_UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define LP_UART_XON_XOFF_STILL_SEND_M  (LP_UART_XON_XOFF_STILL_SEND_V << LP_UART_XON_XOFF_STILL_SEND_S)
+#define LP_UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define LP_UART_XON_XOFF_STILL_SEND_S  16
+/** LP_UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define LP_UART_SW_FLOW_CON_EN    (BIT(17))
+#define LP_UART_SW_FLOW_CON_EN_M  (LP_UART_SW_FLOW_CON_EN_V << LP_UART_SW_FLOW_CON_EN_S)
+#define LP_UART_SW_FLOW_CON_EN_V  0x00000001U
+#define LP_UART_SW_FLOW_CON_EN_S  17
+/** LP_UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define LP_UART_XONOFF_DEL    (BIT(18))
+#define LP_UART_XONOFF_DEL_M  (LP_UART_XONOFF_DEL_V << LP_UART_XONOFF_DEL_S)
+#define LP_UART_XONOFF_DEL_V  0x00000001U
+#define LP_UART_XONOFF_DEL_S  18
+/** LP_UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define LP_UART_FORCE_XON    (BIT(19))
+#define LP_UART_FORCE_XON_M  (LP_UART_FORCE_XON_V << LP_UART_FORCE_XON_S)
+#define LP_UART_FORCE_XON_V  0x00000001U
+#define LP_UART_FORCE_XON_S  19
+/** LP_UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define LP_UART_FORCE_XOFF    (BIT(20))
+#define LP_UART_FORCE_XOFF_M  (LP_UART_FORCE_XOFF_V << LP_UART_FORCE_XOFF_S)
+#define LP_UART_FORCE_XOFF_V  0x00000001U
+#define LP_UART_FORCE_XOFF_S  20
+/** LP_UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define LP_UART_SEND_XON    (BIT(21))
+#define LP_UART_SEND_XON_M  (LP_UART_SEND_XON_V << LP_UART_SEND_XON_S)
+#define LP_UART_SEND_XON_V  0x00000001U
+#define LP_UART_SEND_XON_S  21
+/** LP_UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define LP_UART_SEND_XOFF    (BIT(22))
+#define LP_UART_SEND_XOFF_M  (LP_UART_SEND_XOFF_V << LP_UART_SEND_XOFF_S)
+#define LP_UART_SEND_XOFF_V  0x00000001U
+#define LP_UART_SEND_XOFF_S  22
+
+/** LP_UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define LP_UART_SWFC_CONF1_REG (DR_REG_LP_UART_BASE + 0x40)
+/** LP_UART_XON_THRESHOLD : R/W; bitpos: [7:3]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define LP_UART_XON_THRESHOLD    0x0000001FU
+#define LP_UART_XON_THRESHOLD_M  (LP_UART_XON_THRESHOLD_V << LP_UART_XON_THRESHOLD_S)
+#define LP_UART_XON_THRESHOLD_V  0x0000001FU
+#define LP_UART_XON_THRESHOLD_S  3
+/** LP_UART_XOFF_THRESHOLD : R/W; bitpos: [15:11]; default: 12;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define LP_UART_XOFF_THRESHOLD    0x0000001FU
+#define LP_UART_XOFF_THRESHOLD_M  (LP_UART_XOFF_THRESHOLD_V << LP_UART_XOFF_THRESHOLD_S)
+#define LP_UART_XOFF_THRESHOLD_V  0x0000001FU
+#define LP_UART_XOFF_THRESHOLD_S  11
+
+/** LP_UART_TXBRK_CONF_SYNC_REG register
+ *  Tx Break character configuration
+ */
+#define LP_UART_TXBRK_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x44)
+/** LP_UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define LP_UART_TX_BRK_NUM    0x000000FFU
+#define LP_UART_TX_BRK_NUM_M  (LP_UART_TX_BRK_NUM_V << LP_UART_TX_BRK_NUM_S)
+#define LP_UART_TX_BRK_NUM_V  0x000000FFU
+#define LP_UART_TX_BRK_NUM_S  0
+
+/** LP_UART_IDLE_CONF_SYNC_REG register
+ *  Frame-end idle configuration
+ */
+#define LP_UART_IDLE_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x48)
+/** LP_UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define LP_UART_RX_IDLE_THRHD    0x000003FFU
+#define LP_UART_RX_IDLE_THRHD_M  (LP_UART_RX_IDLE_THRHD_V << LP_UART_RX_IDLE_THRHD_S)
+#define LP_UART_RX_IDLE_THRHD_V  0x000003FFU
+#define LP_UART_RX_IDLE_THRHD_S  0
+/** LP_UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define LP_UART_TX_IDLE_NUM    0x000003FFU
+#define LP_UART_TX_IDLE_NUM_M  (LP_UART_TX_IDLE_NUM_V << LP_UART_TX_IDLE_NUM_S)
+#define LP_UART_TX_IDLE_NUM_V  0x000003FFU
+#define LP_UART_TX_IDLE_NUM_S  10
+
+/** LP_UART_RS485_CONF_SYNC_REG register
+ *  RS485 mode configuration
+ */
+#define LP_UART_RS485_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x4c)
+/** LP_UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define LP_UART_DL0_EN    (BIT(1))
+#define LP_UART_DL0_EN_M  (LP_UART_DL0_EN_V << LP_UART_DL0_EN_S)
+#define LP_UART_DL0_EN_V  0x00000001U
+#define LP_UART_DL0_EN_S  1
+/** LP_UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define LP_UART_DL1_EN    (BIT(2))
+#define LP_UART_DL1_EN_M  (LP_UART_DL1_EN_V << LP_UART_DL1_EN_S)
+#define LP_UART_DL1_EN_V  0x00000001U
+#define LP_UART_DL1_EN_S  2
+
+/** LP_UART_AT_CMD_PRECNT_SYNC_REG register
+ *  Pre-sequence timing configuration
+ */
+#define LP_UART_AT_CMD_PRECNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x50)
+/** LP_UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define LP_UART_PRE_IDLE_NUM    0x0000FFFFU
+#define LP_UART_PRE_IDLE_NUM_M  (LP_UART_PRE_IDLE_NUM_V << LP_UART_PRE_IDLE_NUM_S)
+#define LP_UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define LP_UART_PRE_IDLE_NUM_S  0
+
+/** LP_UART_AT_CMD_POSTCNT_SYNC_REG register
+ *  Post-sequence timing configuration
+ */
+#define LP_UART_AT_CMD_POSTCNT_SYNC_REG (DR_REG_LP_UART_BASE + 0x54)
+/** LP_UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define LP_UART_POST_IDLE_NUM    0x0000FFFFU
+#define LP_UART_POST_IDLE_NUM_M  (LP_UART_POST_IDLE_NUM_V << LP_UART_POST_IDLE_NUM_S)
+#define LP_UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define LP_UART_POST_IDLE_NUM_S  0
+
+/** LP_UART_AT_CMD_GAPTOUT_SYNC_REG register
+ *  Timeout configuration
+ */
+#define LP_UART_AT_CMD_GAPTOUT_SYNC_REG (DR_REG_LP_UART_BASE + 0x58)
+/** LP_UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define LP_UART_RX_GAP_TOUT    0x0000FFFFU
+#define LP_UART_RX_GAP_TOUT_M  (LP_UART_RX_GAP_TOUT_V << LP_UART_RX_GAP_TOUT_S)
+#define LP_UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define LP_UART_RX_GAP_TOUT_S  0
+
+/** LP_UART_AT_CMD_CHAR_SYNC_REG register
+ *  AT escape sequence detection configuration
+ */
+#define LP_UART_AT_CMD_CHAR_SYNC_REG (DR_REG_LP_UART_BASE + 0x5c)
+/** LP_UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define LP_UART_AT_CMD_CHAR    0x000000FFU
+#define LP_UART_AT_CMD_CHAR_M  (LP_UART_AT_CMD_CHAR_V << LP_UART_AT_CMD_CHAR_S)
+#define LP_UART_AT_CMD_CHAR_V  0x000000FFU
+#define LP_UART_AT_CMD_CHAR_S  0
+/** LP_UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define LP_UART_CHAR_NUM    0x000000FFU
+#define LP_UART_CHAR_NUM_M  (LP_UART_CHAR_NUM_V << LP_UART_CHAR_NUM_S)
+#define LP_UART_CHAR_NUM_V  0x000000FFU
+#define LP_UART_CHAR_NUM_S  8
+
+/** LP_UART_MEM_CONF_REG register
+ *  UART memory power configuration
+ */
+#define LP_UART_MEM_CONF_REG (DR_REG_LP_UART_BASE + 0x60)
+/** LP_UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define LP_UART_MEM_FORCE_PD    (BIT(25))
+#define LP_UART_MEM_FORCE_PD_M  (LP_UART_MEM_FORCE_PD_V << LP_UART_MEM_FORCE_PD_S)
+#define LP_UART_MEM_FORCE_PD_V  0x00000001U
+#define LP_UART_MEM_FORCE_PD_S  25
+/** LP_UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define LP_UART_MEM_FORCE_PU    (BIT(26))
+#define LP_UART_MEM_FORCE_PU_M  (LP_UART_MEM_FORCE_PU_V << LP_UART_MEM_FORCE_PU_S)
+#define LP_UART_MEM_FORCE_PU_V  0x00000001U
+#define LP_UART_MEM_FORCE_PU_S  26
+
+/** LP_UART_TOUT_CONF_SYNC_REG register
+ *  UART threshold and allocation configuration
+ */
+#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
+/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define LP_UART_RX_TOUT_EN    (BIT(0))
+#define LP_UART_RX_TOUT_EN_M  (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)
+#define LP_UART_RX_TOUT_EN_V  0x00000001U
+#define LP_UART_RX_TOUT_EN_S  0
+/** LP_UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define LP_UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define LP_UART_RX_TOUT_FLOW_DIS_M  (LP_UART_RX_TOUT_FLOW_DIS_V << LP_UART_RX_TOUT_FLOW_DIS_S)
+#define LP_UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define LP_UART_RX_TOUT_FLOW_DIS_S  1
+/** LP_UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define LP_UART_RX_TOUT_THRHD    0x000003FFU
+#define LP_UART_RX_TOUT_THRHD_M  (LP_UART_RX_TOUT_THRHD_V << LP_UART_RX_TOUT_THRHD_S)
+#define LP_UART_RX_TOUT_THRHD_V  0x000003FFU
+#define LP_UART_RX_TOUT_THRHD_S  2
+
+/** LP_UART_MEM_TX_STATUS_REG register
+ *  Tx-SRAM write and read offset address.
+ */
+#define LP_UART_MEM_TX_STATUS_REG (DR_REG_LP_UART_BASE + 0x68)
+/** LP_UART_TX_SRAM_WADDR : RO; bitpos: [7:3]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define LP_UART_TX_SRAM_WADDR    0x0000001FU
+#define LP_UART_TX_SRAM_WADDR_M  (LP_UART_TX_SRAM_WADDR_V << LP_UART_TX_SRAM_WADDR_S)
+#define LP_UART_TX_SRAM_WADDR_V  0x0000001FU
+#define LP_UART_TX_SRAM_WADDR_S  3
+/** LP_UART_TX_SRAM_RADDR : RO; bitpos: [16:12]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define LP_UART_TX_SRAM_RADDR    0x0000001FU
+#define LP_UART_TX_SRAM_RADDR_M  (LP_UART_TX_SRAM_RADDR_V << LP_UART_TX_SRAM_RADDR_S)
+#define LP_UART_TX_SRAM_RADDR_V  0x0000001FU
+#define LP_UART_TX_SRAM_RADDR_S  12
+
+/** LP_UART_MEM_RX_STATUS_REG register
+ *  Rx-SRAM write and read offset address.
+ */
+#define LP_UART_MEM_RX_STATUS_REG (DR_REG_LP_UART_BASE + 0x6c)
+/** LP_UART_RX_SRAM_RADDR : RO; bitpos: [7:3]; default: 16;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define LP_UART_RX_SRAM_RADDR    0x0000001FU
+#define LP_UART_RX_SRAM_RADDR_M  (LP_UART_RX_SRAM_RADDR_V << LP_UART_RX_SRAM_RADDR_S)
+#define LP_UART_RX_SRAM_RADDR_V  0x0000001FU
+#define LP_UART_RX_SRAM_RADDR_S  3
+/** LP_UART_RX_SRAM_WADDR : RO; bitpos: [16:12]; default: 16;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define LP_UART_RX_SRAM_WADDR    0x0000001FU
+#define LP_UART_RX_SRAM_WADDR_M  (LP_UART_RX_SRAM_WADDR_V << LP_UART_RX_SRAM_WADDR_S)
+#define LP_UART_RX_SRAM_WADDR_V  0x0000001FU
+#define LP_UART_RX_SRAM_WADDR_S  12
+
+/** LP_UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define LP_UART_FSM_STATUS_REG (DR_REG_LP_UART_BASE + 0x70)
+/** LP_UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define LP_UART_ST_URX_OUT    0x0000000FU
+#define LP_UART_ST_URX_OUT_M  (LP_UART_ST_URX_OUT_V << LP_UART_ST_URX_OUT_S)
+#define LP_UART_ST_URX_OUT_V  0x0000000FU
+#define LP_UART_ST_URX_OUT_S  0
+/** LP_UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define LP_UART_ST_UTX_OUT    0x0000000FU
+#define LP_UART_ST_UTX_OUT_M  (LP_UART_ST_UTX_OUT_V << LP_UART_ST_UTX_OUT_S)
+#define LP_UART_ST_UTX_OUT_V  0x0000000FU
+#define LP_UART_ST_UTX_OUT_S  4
+
+/** LP_UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
+/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define LP_UART_TX_SCLK_EN    (BIT(24))
+#define LP_UART_TX_SCLK_EN_M  (LP_UART_TX_SCLK_EN_V << LP_UART_TX_SCLK_EN_S)
+#define LP_UART_TX_SCLK_EN_V  0x00000001U
+#define LP_UART_TX_SCLK_EN_S  24
+/** LP_UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define LP_UART_RX_SCLK_EN    (BIT(25))
+#define LP_UART_RX_SCLK_EN_M  (LP_UART_RX_SCLK_EN_V << LP_UART_RX_SCLK_EN_S)
+#define LP_UART_RX_SCLK_EN_V  0x00000001U
+#define LP_UART_RX_SCLK_EN_S  25
+/** LP_UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx.
+ */
+#define LP_UART_TX_RST_CORE    (BIT(26))
+#define LP_UART_TX_RST_CORE_M  (LP_UART_TX_RST_CORE_V << LP_UART_TX_RST_CORE_S)
+#define LP_UART_TX_RST_CORE_V  0x00000001U
+#define LP_UART_TX_RST_CORE_S  26
+/** LP_UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Rx.
+ */
+#define LP_UART_RX_RST_CORE    (BIT(27))
+#define LP_UART_RX_RST_CORE_M  (LP_UART_RX_RST_CORE_V << LP_UART_RX_RST_CORE_S)
+#define LP_UART_RX_RST_CORE_V  0x00000001U
+#define LP_UART_RX_RST_CORE_S  27
+
+/** LP_UART_DATE_REG register
+ *  UART Version register
+ */
+#define LP_UART_DATE_REG (DR_REG_LP_UART_BASE + 0x8c)
+/** LP_UART_DATE : R/W; bitpos: [31:0]; default: 36720720;
+ *  This is the version register.
+ */
+#define LP_UART_DATE    0xFFFFFFFFU
+#define LP_UART_DATE_M  (LP_UART_DATE_V << LP_UART_DATE_S)
+#define LP_UART_DATE_V  0xFFFFFFFFU
+#define LP_UART_DATE_S  0
+
+/** LP_UART_AFIFO_STATUS_REG register
+ *  UART AFIFO Status
+ */
+#define LP_UART_AFIFO_STATUS_REG (DR_REG_LP_UART_BASE + 0x90)
+/** LP_UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define LP_UART_TX_AFIFO_FULL    (BIT(0))
+#define LP_UART_TX_AFIFO_FULL_M  (LP_UART_TX_AFIFO_FULL_V << LP_UART_TX_AFIFO_FULL_S)
+#define LP_UART_TX_AFIFO_FULL_V  0x00000001U
+#define LP_UART_TX_AFIFO_FULL_S  0
+/** LP_UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define LP_UART_TX_AFIFO_EMPTY    (BIT(1))
+#define LP_UART_TX_AFIFO_EMPTY_M  (LP_UART_TX_AFIFO_EMPTY_V << LP_UART_TX_AFIFO_EMPTY_S)
+#define LP_UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define LP_UART_TX_AFIFO_EMPTY_S  1
+/** LP_UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define LP_UART_RX_AFIFO_FULL    (BIT(2))
+#define LP_UART_RX_AFIFO_FULL_M  (LP_UART_RX_AFIFO_FULL_V << LP_UART_RX_AFIFO_FULL_S)
+#define LP_UART_RX_AFIFO_FULL_V  0x00000001U
+#define LP_UART_RX_AFIFO_FULL_S  2
+/** LP_UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define LP_UART_RX_AFIFO_EMPTY    (BIT(3))
+#define LP_UART_RX_AFIFO_EMPTY_M  (LP_UART_RX_AFIFO_EMPTY_V << LP_UART_RX_AFIFO_EMPTY_S)
+#define LP_UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define LP_UART_RX_AFIFO_EMPTY_S  3
+
+/** LP_UART_REG_UPDATE_REG register
+ *  UART Registers Configuration Update register
+ */
+#define LP_UART_REG_UPDATE_REG (DR_REG_LP_UART_BASE + 0x98)
+/** LP_UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define LP_UART_REG_UPDATE    (BIT(0))
+#define LP_UART_REG_UPDATE_M  (LP_UART_REG_UPDATE_V << LP_UART_REG_UPDATE_S)
+#define LP_UART_REG_UPDATE_V  0x00000001U
+#define LP_UART_REG_UPDATE_S  0
+
+/** LP_UART_ID_REG register
+ *  UART ID register
+ */
+#define LP_UART_ID_REG (DR_REG_LP_UART_BASE + 0x9c)
+/** LP_UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define LP_UART_ID    0xFFFFFFFFU
+#define LP_UART_ID_M  (LP_UART_ID_V << LP_UART_ID_S)
+#define LP_UART_ID_V  0xFFFFFFFFU
+#define LP_UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/lp_uart_struct.h b/components/soc/esp32p4/register/soc/lp_uart_struct.h
new file mode 100644
index 00000000000..d86d6a0d91d
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/lp_uart_struct.h
@@ -0,0 +1,1103 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} lp_uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} lp_uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done_int_raw:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done_int_st:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done_int_ena:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done_int_clr:1;
+        uint32_t reserved_15:3;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lp_uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} lp_uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  Configuration register 0
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        uint32_t reserved_7:5;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        uint32_t reserved_14:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        uint32_t reserved_19:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} lp_uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:3]; default: 12;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:5;
+        uint32_t reserved_8:3;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:11]; default: 12;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:5;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} lp_uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rx_flow_thrhd : R/W; bitpos: [7:3]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:5;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} lp_uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        uint32_t reserved_10:3;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:13]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:5;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_char : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_char:8;
+        /** xoff_char : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_char:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} lp_uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** xon_threshold : R/W; bitpos: [7:3]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:5;
+        uint32_t reserved_8:3;
+        /** xoff_threshold : R/W; bitpos: [15:11]; default: 12;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:5;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} lp_uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} lp_uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} lp_uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rxfifo_cnt : RO; bitpos: [7:3]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:5;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        uint32_t reserved_16:3;
+        /** txfifo_cnt : RO; bitpos: [23:19]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:5;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} lp_uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** tx_sram_waddr : RO; bitpos: [7:3]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:5;
+        uint32_t reserved_8:4;
+        /** tx_sram_raddr : RO; bitpos: [16:12]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:5;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** rx_sram_raddr : RO; bitpos: [7:3]; default: 16;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:5;
+        uint32_t reserved_8:4;
+        /** rx_sram_waddr : RO; bitpos: [16:12]; default: 16;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:5;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} lp_uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} lp_uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} lp_uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t at_cmd_char:8;
+        /** char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} lp_uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36720720;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} lp_uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} lp_uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} lp_uart_id_reg_t;
+
+
+typedef struct {
+    volatile lp_uart_fifo_reg_t fifo;
+    volatile lp_uart_int_raw_reg_t int_raw;
+    volatile lp_uart_int_st_reg_t int_st;
+    volatile lp_uart_int_ena_reg_t int_ena;
+    volatile lp_uart_int_clr_reg_t int_clr;
+    volatile lp_uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile lp_uart_rx_filt_reg_t rx_filt;
+    volatile lp_uart_status_reg_t status;
+    volatile lp_uart_conf0_sync_reg_t conf0_sync;
+    volatile lp_uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile lp_uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile lp_uart_sleep_conf0_reg_t sleep_conf0;
+    volatile lp_uart_sleep_conf1_reg_t sleep_conf1;
+    volatile lp_uart_sleep_conf2_reg_t sleep_conf2;
+    volatile lp_uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile lp_uart_swfc_conf1_reg_t swfc_conf1;
+    volatile lp_uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile lp_uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile lp_uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile lp_uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile lp_uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile lp_uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile lp_uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile lp_uart_mem_conf_reg_t mem_conf;
+    volatile lp_uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile lp_uart_mem_tx_status_reg_t mem_tx_status;
+    volatile lp_uart_mem_rx_status_reg_t mem_rx_status;
+    volatile lp_uart_fsm_status_reg_t fsm_status;
+    uint32_t reserved_074[5];
+    volatile lp_uart_clk_conf_reg_t clk_conf;
+    volatile lp_uart_date_reg_t date;
+    volatile lp_uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile lp_uart_reg_update_reg_t reg_update;
+    volatile lp_uart_id_reg_t id;
+} lp_uart_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(lp_uart_dev_t) == 0xa0, "Invalid size of lp_uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/lp_wdt_reg.h b/components/soc/esp32p4/register/soc/lp_wdt_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_wdt_reg.h
rename to components/soc/esp32p4/register/soc/lp_wdt_reg.h
diff --git a/components/soc/esp32p4/include/soc/lp_wdt_struct.h b/components/soc/esp32p4/register/soc/lp_wdt_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lp_wdt_struct.h
rename to components/soc/esp32p4/register/soc/lp_wdt_struct.h
diff --git a/components/soc/esp32p4/include/soc/lpperi_reg.h b/components/soc/esp32p4/register/soc/lpperi_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lpperi_reg.h
rename to components/soc/esp32p4/register/soc/lpperi_reg.h
diff --git a/components/soc/esp32p4/include/soc/lpperi_struct.h b/components/soc/esp32p4/register/soc/lpperi_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/lpperi_struct.h
rename to components/soc/esp32p4/register/soc/lpperi_struct.h
diff --git a/components/soc/esp32p4/register/soc/mcpwm_reg.h b/components/soc/esp32p4/register/soc/mcpwm_reg.h
new file mode 100644
index 00000000000..beb5e441112
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/mcpwm_reg.h
@@ -0,0 +1,4514 @@
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** MCPWM_CLK_CFG_REG register
+ *  PWM clock prescaler register.
+ */
+#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0)
+/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
+ *  (PWM_CLK_PRESCALE + 1).
+ */
+#define MCPWM_CLK_PRESCALE    0x000000FFU
+#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
+#define MCPWM_CLK_PRESCALE_V  0x000000FFU
+#define MCPWM_CLK_PRESCALE_S  0
+
+/** MCPWM_TIMER0_CFG0_REG register
+ *  PWM timer0 period and update method configuration register.
+ */
+#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x4)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer0, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER0_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer0
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer0 period.\\0:
+ *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+ *  zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER0_CFG1_REG register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x8)
+/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+ *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+ *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+ *  stops at the next TEP.\\TEP here and below means the event that happens when the
+ *  timer equals to period
+ */
+#define MCPWM_TIMER0_START    0x00000007U
+#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
+#define MCPWM_TIMER0_START_V  0x00000007U
+#define MCPWM_TIMER0_START_S  0
+/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+ *  Decrease mode\\3: Up-down mode
+ */
+#define MCPWM_TIMER0_MOD    0x00000003U
+#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
+#define MCPWM_TIMER0_MOD_V  0x00000003U
+#define MCPWM_TIMER0_MOD_S  3
+
+/** MCPWM_TIMER0_SYNC_REG register
+ *  PWM timer$n sync function configuration register.
+ */
+#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0xc)
+/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer$n reloading with phase on sync input
+ *  event is enabled.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
+#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
+#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+ *  Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer$n reload on sync event.
+ */
+#define MCPWM_TIMER0_PHASE    0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
+#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_S  4
+/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+ *  Increase\\1: Decrease
+ */
+#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
+#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER0_STATUS_REG register
+ *  PWM timer$n status register.
+ */
+#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x10)
+/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer$n counter value.
+ */
+#define MCPWM_TIMER0_VALUE    0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
+#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_S  0
+/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+ */
+#define MCPWM_TIMER0_DIRECTION    (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
+#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_DIRECTION_S  16
+
+/** MCPWM_TIMER1_CFG0_REG register
+ *  PWM timer1 period and update method configuration register.
+ */
+#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x14)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer1, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER1_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer1
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer1 period.\\0:
+ *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+ *  zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER1_CFG1_REG register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x18)
+/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+ *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+ *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+ *  stops at the next TEP.\\TEP here and below means the event that happens when the
+ *  timer equals to period
+ */
+#define MCPWM_TIMER1_START    0x00000007U
+#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
+#define MCPWM_TIMER1_START_V  0x00000007U
+#define MCPWM_TIMER1_START_S  0
+/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+ *  Decrease mode\\3: Up-down mode
+ */
+#define MCPWM_TIMER1_MOD    0x00000003U
+#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
+#define MCPWM_TIMER1_MOD_V  0x00000003U
+#define MCPWM_TIMER1_MOD_S  3
+
+/** MCPWM_TIMER1_SYNC_REG register
+ *  PWM timer$n sync function configuration register.
+ */
+#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x1c)
+/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer$n reloading with phase on sync input
+ *  event is enabled.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
+#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
+#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+ *  Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer$n reload on sync event.
+ */
+#define MCPWM_TIMER1_PHASE    0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
+#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_S  4
+/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+ *  Increase\\1: Decrease
+ */
+#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
+#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER1_STATUS_REG register
+ *  PWM timer$n status register.
+ */
+#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x20)
+/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer$n counter value.
+ */
+#define MCPWM_TIMER1_VALUE    0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
+#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_S  0
+/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+ */
+#define MCPWM_TIMER1_DIRECTION    (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
+#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_DIRECTION_S  16
+
+/** MCPWM_TIMER2_CFG0_REG register
+ *  PWM timer2 period and update method configuration register.
+ */
+#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x24)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the prescaler value of timer2, so that the period of PT0_clk = Period of
+ *  PWM_clk * (PWM_TIMER2_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  Configures the period shadow of PWM timer2
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Configures the update method for active register of PWM timer2 period.\\0:
+ *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+ *  zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER2_CFG1_REG register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x28)
+/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+ *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+ *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+ *  stops at the next TEP.\\TEP here and below means the event that happens when the
+ *  timer equals to period
+ */
+#define MCPWM_TIMER2_START    0x00000007U
+#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
+#define MCPWM_TIMER2_START_V  0x00000007U
+#define MCPWM_TIMER2_START_S  0
+/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+ *  Decrease mode\\3: Up-down mode
+ */
+#define MCPWM_TIMER2_MOD    0x00000003U
+#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
+#define MCPWM_TIMER2_MOD_V  0x00000003U
+#define MCPWM_TIMER2_MOD_S  3
+
+/** MCPWM_TIMER2_SYNC_REG register
+ *  PWM timer$n sync function configuration register.
+ */
+#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x2c)
+/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer$n reloading with phase on sync input
+ *  event is enabled.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
+#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of software sync. Toggling this bit will trigger a
+ *  software sync.
+ */
+#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
+#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+ *  Invalid, sync_out selects noting
+ */
+#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  Configures the phase for timer$n reload on sync event.
+ */
+#define MCPWM_TIMER2_PHASE    0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
+#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_S  4
+/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+ *  Increase\\1: Decrease
+ */
+#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
+#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER2_STATUS_REG register
+ *  PWM timer$n status register.
+ */
+#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x30)
+/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  Represents current PWM timer$n counter value.
+ */
+#define MCPWM_TIMER2_VALUE    0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
+#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_S  0
+/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+ */
+#define MCPWM_TIMER2_DIRECTION    (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
+#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_DIRECTION_S  16
+
+/** MCPWM_TIMER_SYNCI_CFG_REG register
+ *  Synchronization input selection register for PWM timers.
+ */
+#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x34)
+/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
+ *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+ *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+ */
+#define MCPWM_TIMER0_SYNCISEL    0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
+#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_S  0
+/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
+ *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
+ *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+ *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+ */
+#define MCPWM_TIMER1_SYNCISEL    0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
+#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
+ *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+ *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+ */
+#define MCPWM_TIMER2_SYNCISEL    0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
+#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
+ *  Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
+ *  Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
+ *  Invert
+ */
+#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+
+/** MCPWM_OPERATOR_TIMERSEL_REG register
+ *  PWM operator's timer select register
+ */
+#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x38)
+/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
+ *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
+ *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
+ *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
+ *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+ */
+#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+
+/** MCPWM_GEN0_STMP_CFG_REG register
+ *  Generator0 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN0_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x3c)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 0 time stamp A's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 0 time stamp B's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator0 time stamp A's shadow reg is transferred.\\0:
+ *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+ *  reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator0 time stamp B's shadow reg is transferred.\\0:
+ *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+ *  reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN0_TSTMP_A_REG register
+ *  Generator$n time stamp A's shadow register
+ */
+#define MCPWM_GEN0_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x40)
+/** MCPWM_CMPR0_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp A's shadow register.
+ */
+#define MCPWM_CMPR0_A    0x0000FFFFU
+#define MCPWM_CMPR0_A_M  (MCPWM_CMPR0_A_V << MCPWM_CMPR0_A_S)
+#define MCPWM_CMPR0_A_V  0x0000FFFFU
+#define MCPWM_CMPR0_A_S  0
+
+/** MCPWM_GEN0_TSTMP_B_REG register
+ *  Generator$n time stamp B's shadow register
+ */
+#define MCPWM_GEN0_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x44)
+/** MCPWM_CMPR0_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp B's shadow register.
+ */
+#define MCPWM_CMPR0_B    0x0000FFFFU
+#define MCPWM_CMPR0_B_M  (MCPWM_CMPR0_B_V << MCPWM_CMPR0_B_S)
+#define MCPWM_CMPR0_B_V  0x0000FFFFU
+#define MCPWM_CMPR0_B_S  0
+
+/** MCPWM_GEN0_CFG0_REG register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x48)
+/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator $n's active register.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator $n event_t0, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN0_T0_SEL    0x00000007U
+#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
+#define MCPWM_GEN0_T0_SEL_V  0x00000007U
+#define MCPWM_GEN0_T0_SEL_S  4
+/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator $n event_t1, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN0_T1_SEL    0x00000007U
+#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
+#define MCPWM_GEN0_T1_SEL_V  0x00000007U
+#define MCPWM_GEN0_T1_SEL_S  7
+
+/** MCPWM_GEN0_FORCE_REG register
+ *  Generator$n output signal force mode register.
+ */
+#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x4c)
+/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator$n.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+ *  update. TEA/B here and below means an event generated when the timer's value equals
+ *  to that of register A/B.
+ */
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
+#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
+#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN0_A_REG register
+ *  PWM$n output signal A actions configuration register
+ */
+#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x50)
+/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEZ    0x00000003U
+#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
+#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_UTEZ_S  0
+/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEP    0x00000003U
+#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
+#define MCPWM_GEN0_A_UTEP_V  0x00000003U
+#define MCPWM_GEN0_A_UTEP_S  2
+/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEA    0x00000003U
+#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
+#define MCPWM_GEN0_A_UTEA_V  0x00000003U
+#define MCPWM_GEN0_A_UTEA_S  4
+/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UTEB    0x00000003U
+#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
+#define MCPWM_GEN0_A_UTEB_V  0x00000003U
+#define MCPWM_GEN0_A_UTEB_S  6
+/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UT0    0x00000003U
+#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
+#define MCPWM_GEN0_A_UT0_V  0x00000003U
+#define MCPWM_GEN0_A_UT0_S  8
+/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_UT1    0x00000003U
+#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
+#define MCPWM_GEN0_A_UT1_V  0x00000003U
+#define MCPWM_GEN0_A_UT1_S  10
+/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEZ    0x00000003U
+#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
+#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_DTEZ_S  12
+/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEP    0x00000003U
+#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
+#define MCPWM_GEN0_A_DTEP_V  0x00000003U
+#define MCPWM_GEN0_A_DTEP_S  14
+/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEA    0x00000003U
+#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
+#define MCPWM_GEN0_A_DTEA_V  0x00000003U
+#define MCPWM_GEN0_A_DTEA_S  16
+/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DTEB    0x00000003U
+#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
+#define MCPWM_GEN0_A_DTEB_V  0x00000003U
+#define MCPWM_GEN0_A_DTEB_S  18
+/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DT0    0x00000003U
+#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
+#define MCPWM_GEN0_A_DT0_V  0x00000003U
+#define MCPWM_GEN0_A_DT0_S  20
+/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_A_DT1    0x00000003U
+#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
+#define MCPWM_GEN0_A_DT1_V  0x00000003U
+#define MCPWM_GEN0_A_DT1_S  22
+
+/** MCPWM_GEN0_B_REG register
+ *  PWM$n output signal B actions configuration register
+ */
+#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x54)
+/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEZ    0x00000003U
+#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
+#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_UTEZ_S  0
+/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEP    0x00000003U
+#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
+#define MCPWM_GEN0_B_UTEP_V  0x00000003U
+#define MCPWM_GEN0_B_UTEP_S  2
+/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEA    0x00000003U
+#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
+#define MCPWM_GEN0_B_UTEA_V  0x00000003U
+#define MCPWM_GEN0_B_UTEA_S  4
+/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UTEB    0x00000003U
+#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
+#define MCPWM_GEN0_B_UTEB_V  0x00000003U
+#define MCPWM_GEN0_B_UTEB_S  6
+/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UT0    0x00000003U
+#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
+#define MCPWM_GEN0_B_UT0_V  0x00000003U
+#define MCPWM_GEN0_B_UT0_S  8
+/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_UT1    0x00000003U
+#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
+#define MCPWM_GEN0_B_UT1_V  0x00000003U
+#define MCPWM_GEN0_B_UT1_S  10
+/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEZ    0x00000003U
+#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
+#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_DTEZ_S  12
+/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEP    0x00000003U
+#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
+#define MCPWM_GEN0_B_DTEP_V  0x00000003U
+#define MCPWM_GEN0_B_DTEP_S  14
+/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEA    0x00000003U
+#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
+#define MCPWM_GEN0_B_DTEA_V  0x00000003U
+#define MCPWM_GEN0_B_DTEA_S  16
+/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DTEB    0x00000003U
+#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
+#define MCPWM_GEN0_B_DTEB_V  0x00000003U
+#define MCPWM_GEN0_B_DTEB_S  18
+/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DT0    0x00000003U
+#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
+#define MCPWM_GEN0_B_DT0_V  0x00000003U
+#define MCPWM_GEN0_B_DT0_S  20
+/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN0_B_DT1    0x00000003U
+#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
+#define MCPWM_GEN0_B_DT1_V  0x00000003U
+#define MCPWM_GEN0_B_DT1_S  22
+
+/** MCPWM_DT0_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x58)
+/** MCPWM_DB0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB0_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_M  (MCPWM_DB0_FED_UPMETHOD_V << MCPWM_DB0_FED_UPMETHOD_S)
+#define MCPWM_DB0_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_FED_UPMETHOD_S  0
+/** MCPWM_DB0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB0_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_M  (MCPWM_DB0_RED_UPMETHOD_V << MCPWM_DB0_RED_UPMETHOD_S)
+#define MCPWM_DB0_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB0_RED_UPMETHOD_S  4
+/** MCPWM_DB0_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+ *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB0_DEB_MODE    (BIT(8))
+#define MCPWM_DB0_DEB_MODE_M  (MCPWM_DB0_DEB_MODE_V << MCPWM_DB0_DEB_MODE_S)
+#define MCPWM_DB0_DEB_MODE_V  0x00000001U
+#define MCPWM_DB0_DEB_MODE_S  8
+/** MCPWM_DB0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB0_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB0_A_OUTSWAP_M  (MCPWM_DB0_A_OUTSWAP_V << MCPWM_DB0_A_OUTSWAP_S)
+#define MCPWM_DB0_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_A_OUTSWAP_S  9
+/** MCPWM_DB0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB0_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB0_B_OUTSWAP_M  (MCPWM_DB0_B_OUTSWAP_V << MCPWM_DB0_B_OUTSWAP_S)
+#define MCPWM_DB0_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB0_B_OUTSWAP_S  10
+/** MCPWM_DB0_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB0_RED_INSEL    (BIT(11))
+#define MCPWM_DB0_RED_INSEL_M  (MCPWM_DB0_RED_INSEL_V << MCPWM_DB0_RED_INSEL_S)
+#define MCPWM_DB0_RED_INSEL_V  0x00000001U
+#define MCPWM_DB0_RED_INSEL_S  11
+/** MCPWM_DB0_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB0_FED_INSEL    (BIT(12))
+#define MCPWM_DB0_FED_INSEL_M  (MCPWM_DB0_FED_INSEL_V << MCPWM_DB0_FED_INSEL_S)
+#define MCPWM_DB0_FED_INSEL_V  0x00000001U
+#define MCPWM_DB0_FED_INSEL_S  12
+/** MCPWM_DB0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB0_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB0_RED_OUTINVERT_M  (MCPWM_DB0_RED_OUTINVERT_V << MCPWM_DB0_RED_OUTINVERT_S)
+#define MCPWM_DB0_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_RED_OUTINVERT_S  13
+/** MCPWM_DB0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB0_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB0_FED_OUTINVERT_M  (MCPWM_DB0_FED_OUTINVERT_V << MCPWM_DB0_FED_OUTINVERT_S)
+#define MCPWM_DB0_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB0_FED_OUTINVERT_S  14
+/** MCPWM_DB0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB0_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB0_A_OUTBYPASS_M  (MCPWM_DB0_A_OUTBYPASS_V << MCPWM_DB0_A_OUTBYPASS_S)
+#define MCPWM_DB0_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_A_OUTBYPASS_S  15
+/** MCPWM_DB0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB0_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB0_B_OUTBYPASS_M  (MCPWM_DB0_B_OUTBYPASS_V << MCPWM_DB0_B_OUTBYPASS_S)
+#define MCPWM_DB0_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB0_B_OUTBYPASS_S  16
+/** MCPWM_DB0_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+ */
+#define MCPWM_DB0_CLK_SEL    (BIT(17))
+#define MCPWM_DB0_CLK_SEL_M  (MCPWM_DB0_CLK_SEL_V << MCPWM_DB0_CLK_SEL_S)
+#define MCPWM_DB0_CLK_SEL_V  0x00000001U
+#define MCPWM_DB0_CLK_SEL_S  17
+
+/** MCPWM_DT0_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x5c)
+/** MCPWM_DB0_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB0_FED    0x0000FFFFU
+#define MCPWM_DB0_FED_M  (MCPWM_DB0_FED_V << MCPWM_DB0_FED_S)
+#define MCPWM_DB0_FED_V  0x0000FFFFU
+#define MCPWM_DB0_FED_S  0
+
+/** MCPWM_DT0_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x60)
+/** MCPWM_DB0_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB0_RED    0x0000FFFFU
+#define MCPWM_DB0_RED_M  (MCPWM_DB0_RED_V << MCPWM_DB0_RED_S)
+#define MCPWM_DB0_RED_V  0x0000FFFFU
+#define MCPWM_DB0_RED_S  0
+
+/** MCPWM_CARRIER0_CFG_REG register
+ *  Carrier$n configuration register
+ */
+#define MCPWM_CARRIER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x64)
+/** MCPWM_CHOPPER0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+ */
+#define MCPWM_CHOPPER0_EN    (BIT(0))
+#define MCPWM_CHOPPER0_EN_M  (MCPWM_CHOPPER0_EN_V << MCPWM_CHOPPER0_EN_S)
+#define MCPWM_CHOPPER0_EN_V  0x00000001U
+#define MCPWM_CHOPPER0_EN_S  0
+/** MCPWM_CHOPPER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER0_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_M  (MCPWM_CHOPPER0_PRESCALE_V << MCPWM_CHOPPER0_PRESCALE_S)
+#define MCPWM_CHOPPER0_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER0_PRESCALE_S  1
+/** MCPWM_CHOPPER0_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+ */
+#define MCPWM_CHOPPER0_DUTY    0x00000007U
+#define MCPWM_CHOPPER0_DUTY_M  (MCPWM_CHOPPER0_DUTY_V << MCPWM_CHOPPER0_DUTY_S)
+#define MCPWM_CHOPPER0_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER0_DUTY_S  5
+/** MCPWM_CHOPPER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER0_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_M  (MCPWM_CHOPPER0_OSHTWTH_V << MCPWM_CHOPPER0_OSHTWTH_S)
+#define MCPWM_CHOPPER0_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER0_OSHTWTH_S  8
+/** MCPWM_CHOPPER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER0_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER0_OUT_INVERT_M  (MCPWM_CHOPPER0_OUT_INVERT_V << MCPWM_CHOPPER0_OUT_INVERT_S)
+#define MCPWM_CHOPPER0_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_OUT_INVERT_S  12
+/** MCPWM_CHOPPER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER0_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER0_IN_INVERT_M  (MCPWM_CHOPPER0_IN_INVERT_V << MCPWM_CHOPPER0_IN_INVERT_S)
+#define MCPWM_CHOPPER0_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER0_IN_INVERT_S  13
+
+/** MCPWM_FH0_CFG0_REG register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+#define MCPWM_FH0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x68)
+/** MCPWM_TZ0_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_SW_CBC    (BIT(0))
+#define MCPWM_TZ0_SW_CBC_M  (MCPWM_TZ0_SW_CBC_V << MCPWM_TZ0_SW_CBC_S)
+#define MCPWM_TZ0_SW_CBC_V  0x00000001U
+#define MCPWM_TZ0_SW_CBC_S  0
+/** MCPWM_TZ0_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F2_CBC    (BIT(1))
+#define MCPWM_TZ0_F2_CBC_M  (MCPWM_TZ0_F2_CBC_V << MCPWM_TZ0_F2_CBC_S)
+#define MCPWM_TZ0_F2_CBC_V  0x00000001U
+#define MCPWM_TZ0_F2_CBC_S  1
+/** MCPWM_TZ0_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F1_CBC    (BIT(2))
+#define MCPWM_TZ0_F1_CBC_M  (MCPWM_TZ0_F1_CBC_V << MCPWM_TZ0_F1_CBC_S)
+#define MCPWM_TZ0_F1_CBC_V  0x00000001U
+#define MCPWM_TZ0_F1_CBC_S  2
+/** MCPWM_TZ0_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F0_CBC    (BIT(3))
+#define MCPWM_TZ0_F0_CBC_M  (MCPWM_TZ0_F0_CBC_V << MCPWM_TZ0_F0_CBC_S)
+#define MCPWM_TZ0_F0_CBC_V  0x00000001U
+#define MCPWM_TZ0_F0_CBC_S  3
+/** MCPWM_TZ0_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_SW_OST    (BIT(4))
+#define MCPWM_TZ0_SW_OST_M  (MCPWM_TZ0_SW_OST_V << MCPWM_TZ0_SW_OST_S)
+#define MCPWM_TZ0_SW_OST_V  0x00000001U
+#define MCPWM_TZ0_SW_OST_S  4
+/** MCPWM_TZ0_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F2_OST    (BIT(5))
+#define MCPWM_TZ0_F2_OST_M  (MCPWM_TZ0_F2_OST_V << MCPWM_TZ0_F2_OST_S)
+#define MCPWM_TZ0_F2_OST_V  0x00000001U
+#define MCPWM_TZ0_F2_OST_S  5
+/** MCPWM_TZ0_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F1_OST    (BIT(6))
+#define MCPWM_TZ0_F1_OST_M  (MCPWM_TZ0_F1_OST_V << MCPWM_TZ0_F1_OST_S)
+#define MCPWM_TZ0_F1_OST_V  0x00000001U
+#define MCPWM_TZ0_F1_OST_S  6
+/** MCPWM_TZ0_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ0_F0_OST    (BIT(7))
+#define MCPWM_TZ0_F0_OST_M  (MCPWM_TZ0_F0_OST_V << MCPWM_TZ0_F0_OST_S)
+#define MCPWM_TZ0_F0_OST_V  0x00000001U
+#define MCPWM_TZ0_F0_OST_S  7
+/** MCPWM_TZ0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_A_CBC_D    0x00000003U
+#define MCPWM_TZ0_A_CBC_D_M  (MCPWM_TZ0_A_CBC_D_V << MCPWM_TZ0_A_CBC_D_S)
+#define MCPWM_TZ0_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_D_S  8
+/** MCPWM_TZ0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_A_CBC_U    0x00000003U
+#define MCPWM_TZ0_A_CBC_U_M  (MCPWM_TZ0_A_CBC_U_V << MCPWM_TZ0_A_CBC_U_S)
+#define MCPWM_TZ0_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_A_CBC_U_S  10
+/** MCPWM_TZ0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_A_OST_D    0x00000003U
+#define MCPWM_TZ0_A_OST_D_M  (MCPWM_TZ0_A_OST_D_V << MCPWM_TZ0_A_OST_D_S)
+#define MCPWM_TZ0_A_OST_D_V  0x00000003U
+#define MCPWM_TZ0_A_OST_D_S  12
+/** MCPWM_TZ0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_A_OST_U    0x00000003U
+#define MCPWM_TZ0_A_OST_U_M  (MCPWM_TZ0_A_OST_U_V << MCPWM_TZ0_A_OST_U_S)
+#define MCPWM_TZ0_A_OST_U_V  0x00000003U
+#define MCPWM_TZ0_A_OST_U_S  14
+/** MCPWM_TZ0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_B_CBC_D    0x00000003U
+#define MCPWM_TZ0_B_CBC_D_M  (MCPWM_TZ0_B_CBC_D_V << MCPWM_TZ0_B_CBC_D_S)
+#define MCPWM_TZ0_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_D_S  16
+/** MCPWM_TZ0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_B_CBC_U    0x00000003U
+#define MCPWM_TZ0_B_CBC_U_M  (MCPWM_TZ0_B_CBC_U_V << MCPWM_TZ0_B_CBC_U_S)
+#define MCPWM_TZ0_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ0_B_CBC_U_S  18
+/** MCPWM_TZ0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_B_OST_D    0x00000003U
+#define MCPWM_TZ0_B_OST_D_M  (MCPWM_TZ0_B_OST_D_V << MCPWM_TZ0_B_OST_D_S)
+#define MCPWM_TZ0_B_OST_D_V  0x00000003U
+#define MCPWM_TZ0_B_OST_D_S  20
+/** MCPWM_TZ0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ0_B_OST_U    0x00000003U
+#define MCPWM_TZ0_B_OST_U_M  (MCPWM_TZ0_B_OST_U_V << MCPWM_TZ0_B_OST_U_S)
+#define MCPWM_TZ0_B_OST_U_V  0x00000003U
+#define MCPWM_TZ0_B_OST_U_S  22
+
+/** MCPWM_FH0_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x6c)
+/** MCPWM_TZ0_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ0_CLR_OST    (BIT(0))
+#define MCPWM_TZ0_CLR_OST_M  (MCPWM_TZ0_CLR_OST_V << MCPWM_TZ0_CLR_OST_S)
+#define MCPWM_TZ0_CLR_OST_V  0x00000001U
+#define MCPWM_TZ0_CLR_OST_S  0
+/** MCPWM_TZ0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+ *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ0_CBCPULSE    0x00000003U
+#define MCPWM_TZ0_CBCPULSE_M  (MCPWM_TZ0_CBCPULSE_V << MCPWM_TZ0_CBCPULSE_S)
+#define MCPWM_TZ0_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ0_CBCPULSE_S  1
+/** MCPWM_TZ0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ0_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ0_FORCE_CBC_M  (MCPWM_TZ0_FORCE_CBC_V << MCPWM_TZ0_FORCE_CBC_S)
+#define MCPWM_TZ0_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ0_FORCE_CBC_S  3
+/** MCPWM_TZ0_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ0_FORCE_OST    (BIT(4))
+#define MCPWM_TZ0_FORCE_OST_M  (MCPWM_TZ0_FORCE_OST_V << MCPWM_TZ0_FORCE_OST_S)
+#define MCPWM_TZ0_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ0_FORCE_OST_S  4
+
+/** MCPWM_FH0_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x70)
+/** MCPWM_TZ0_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+ *  action\\1: On going
+ */
+#define MCPWM_TZ0_CBC_ON    (BIT(0))
+#define MCPWM_TZ0_CBC_ON_M  (MCPWM_TZ0_CBC_ON_V << MCPWM_TZ0_CBC_ON_S)
+#define MCPWM_TZ0_CBC_ON_V  0x00000001U
+#define MCPWM_TZ0_CBC_ON_S  0
+/** MCPWM_TZ0_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+ *  going
+ */
+#define MCPWM_TZ0_OST_ON    (BIT(1))
+#define MCPWM_TZ0_OST_ON_M  (MCPWM_TZ0_OST_ON_V << MCPWM_TZ0_OST_ON_S)
+#define MCPWM_TZ0_OST_ON_V  0x00000001U
+#define MCPWM_TZ0_OST_ON_S  1
+
+/** MCPWM_GEN1_STMP_CFG_REG register
+ *  Generator1 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN1_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x74)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 1 time stamp A's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 1 time stamp B's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator1 time stamp A's shadow reg is transferred.\\0:
+ *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+ *  reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator1 time stamp B's shadow reg is transferred.\\0:
+ *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+ *  reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN1_TSTMP_A_REG register
+ *  Generator$n time stamp A's shadow register
+ */
+#define MCPWM_GEN1_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0x78)
+/** MCPWM_CMPR1_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp A's shadow register.
+ */
+#define MCPWM_CMPR1_A    0x0000FFFFU
+#define MCPWM_CMPR1_A_M  (MCPWM_CMPR1_A_V << MCPWM_CMPR1_A_S)
+#define MCPWM_CMPR1_A_V  0x0000FFFFU
+#define MCPWM_CMPR1_A_S  0
+
+/** MCPWM_GEN1_TSTMP_B_REG register
+ *  Generator$n time stamp B's shadow register
+ */
+#define MCPWM_GEN1_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0x7c)
+/** MCPWM_CMPR1_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp B's shadow register.
+ */
+#define MCPWM_CMPR1_B    0x0000FFFFU
+#define MCPWM_CMPR1_B_M  (MCPWM_CMPR1_B_V << MCPWM_CMPR1_B_S)
+#define MCPWM_CMPR1_B_V  0x0000FFFFU
+#define MCPWM_CMPR1_B_S  0
+
+/** MCPWM_GEN1_CFG0_REG register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x80)
+/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator $n's active register.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator $n event_t0, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN1_T0_SEL    0x00000007U
+#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
+#define MCPWM_GEN1_T0_SEL_V  0x00000007U
+#define MCPWM_GEN1_T0_SEL_S  4
+/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator $n event_t1, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN1_T1_SEL    0x00000007U
+#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
+#define MCPWM_GEN1_T1_SEL_V  0x00000007U
+#define MCPWM_GEN1_T1_SEL_S  7
+
+/** MCPWM_GEN1_FORCE_REG register
+ *  Generator$n output signal force mode register.
+ */
+#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x84)
+/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator$n.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+ *  update. TEA/B here and below means an event generated when the timer's value equals
+ *  to that of register A/B.
+ */
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
+#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
+#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN1_A_REG register
+ *  PWM$n output signal A actions configuration register
+ */
+#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x88)
+/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEZ    0x00000003U
+#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
+#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_UTEZ_S  0
+/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEP    0x00000003U
+#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
+#define MCPWM_GEN1_A_UTEP_V  0x00000003U
+#define MCPWM_GEN1_A_UTEP_S  2
+/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEA    0x00000003U
+#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
+#define MCPWM_GEN1_A_UTEA_V  0x00000003U
+#define MCPWM_GEN1_A_UTEA_S  4
+/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UTEB    0x00000003U
+#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
+#define MCPWM_GEN1_A_UTEB_V  0x00000003U
+#define MCPWM_GEN1_A_UTEB_S  6
+/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UT0    0x00000003U
+#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
+#define MCPWM_GEN1_A_UT0_V  0x00000003U
+#define MCPWM_GEN1_A_UT0_S  8
+/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_UT1    0x00000003U
+#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
+#define MCPWM_GEN1_A_UT1_V  0x00000003U
+#define MCPWM_GEN1_A_UT1_S  10
+/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEZ    0x00000003U
+#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
+#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_DTEZ_S  12
+/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEP    0x00000003U
+#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
+#define MCPWM_GEN1_A_DTEP_V  0x00000003U
+#define MCPWM_GEN1_A_DTEP_S  14
+/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEA    0x00000003U
+#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
+#define MCPWM_GEN1_A_DTEA_V  0x00000003U
+#define MCPWM_GEN1_A_DTEA_S  16
+/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DTEB    0x00000003U
+#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
+#define MCPWM_GEN1_A_DTEB_V  0x00000003U
+#define MCPWM_GEN1_A_DTEB_S  18
+/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DT0    0x00000003U
+#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
+#define MCPWM_GEN1_A_DT0_V  0x00000003U
+#define MCPWM_GEN1_A_DT0_S  20
+/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_A_DT1    0x00000003U
+#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
+#define MCPWM_GEN1_A_DT1_V  0x00000003U
+#define MCPWM_GEN1_A_DT1_S  22
+
+/** MCPWM_GEN1_B_REG register
+ *  PWM$n output signal B actions configuration register
+ */
+#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x8c)
+/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEZ    0x00000003U
+#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
+#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_UTEZ_S  0
+/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEP    0x00000003U
+#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
+#define MCPWM_GEN1_B_UTEP_V  0x00000003U
+#define MCPWM_GEN1_B_UTEP_S  2
+/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEA    0x00000003U
+#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
+#define MCPWM_GEN1_B_UTEA_V  0x00000003U
+#define MCPWM_GEN1_B_UTEA_S  4
+/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UTEB    0x00000003U
+#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
+#define MCPWM_GEN1_B_UTEB_V  0x00000003U
+#define MCPWM_GEN1_B_UTEB_S  6
+/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UT0    0x00000003U
+#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
+#define MCPWM_GEN1_B_UT0_V  0x00000003U
+#define MCPWM_GEN1_B_UT0_S  8
+/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_UT1    0x00000003U
+#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
+#define MCPWM_GEN1_B_UT1_V  0x00000003U
+#define MCPWM_GEN1_B_UT1_S  10
+/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEZ    0x00000003U
+#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
+#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_DTEZ_S  12
+/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEP    0x00000003U
+#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
+#define MCPWM_GEN1_B_DTEP_V  0x00000003U
+#define MCPWM_GEN1_B_DTEP_S  14
+/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEA    0x00000003U
+#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
+#define MCPWM_GEN1_B_DTEA_V  0x00000003U
+#define MCPWM_GEN1_B_DTEA_S  16
+/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DTEB    0x00000003U
+#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
+#define MCPWM_GEN1_B_DTEB_V  0x00000003U
+#define MCPWM_GEN1_B_DTEB_S  18
+/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DT0    0x00000003U
+#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
+#define MCPWM_GEN1_B_DT0_V  0x00000003U
+#define MCPWM_GEN1_B_DT0_S  20
+/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN1_B_DT1    0x00000003U
+#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
+#define MCPWM_GEN1_B_DT1_V  0x00000003U
+#define MCPWM_GEN1_B_DT1_S  22
+
+/** MCPWM_DT1_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x90)
+/** MCPWM_DB1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB1_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_M  (MCPWM_DB1_FED_UPMETHOD_V << MCPWM_DB1_FED_UPMETHOD_S)
+#define MCPWM_DB1_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_FED_UPMETHOD_S  0
+/** MCPWM_DB1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB1_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_M  (MCPWM_DB1_RED_UPMETHOD_V << MCPWM_DB1_RED_UPMETHOD_S)
+#define MCPWM_DB1_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB1_RED_UPMETHOD_S  4
+/** MCPWM_DB1_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+ *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB1_DEB_MODE    (BIT(8))
+#define MCPWM_DB1_DEB_MODE_M  (MCPWM_DB1_DEB_MODE_V << MCPWM_DB1_DEB_MODE_S)
+#define MCPWM_DB1_DEB_MODE_V  0x00000001U
+#define MCPWM_DB1_DEB_MODE_S  8
+/** MCPWM_DB1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB1_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB1_A_OUTSWAP_M  (MCPWM_DB1_A_OUTSWAP_V << MCPWM_DB1_A_OUTSWAP_S)
+#define MCPWM_DB1_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_A_OUTSWAP_S  9
+/** MCPWM_DB1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB1_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB1_B_OUTSWAP_M  (MCPWM_DB1_B_OUTSWAP_V << MCPWM_DB1_B_OUTSWAP_S)
+#define MCPWM_DB1_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB1_B_OUTSWAP_S  10
+/** MCPWM_DB1_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB1_RED_INSEL    (BIT(11))
+#define MCPWM_DB1_RED_INSEL_M  (MCPWM_DB1_RED_INSEL_V << MCPWM_DB1_RED_INSEL_S)
+#define MCPWM_DB1_RED_INSEL_V  0x00000001U
+#define MCPWM_DB1_RED_INSEL_S  11
+/** MCPWM_DB1_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB1_FED_INSEL    (BIT(12))
+#define MCPWM_DB1_FED_INSEL_M  (MCPWM_DB1_FED_INSEL_V << MCPWM_DB1_FED_INSEL_S)
+#define MCPWM_DB1_FED_INSEL_V  0x00000001U
+#define MCPWM_DB1_FED_INSEL_S  12
+/** MCPWM_DB1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB1_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB1_RED_OUTINVERT_M  (MCPWM_DB1_RED_OUTINVERT_V << MCPWM_DB1_RED_OUTINVERT_S)
+#define MCPWM_DB1_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_RED_OUTINVERT_S  13
+/** MCPWM_DB1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB1_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB1_FED_OUTINVERT_M  (MCPWM_DB1_FED_OUTINVERT_V << MCPWM_DB1_FED_OUTINVERT_S)
+#define MCPWM_DB1_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB1_FED_OUTINVERT_S  14
+/** MCPWM_DB1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB1_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB1_A_OUTBYPASS_M  (MCPWM_DB1_A_OUTBYPASS_V << MCPWM_DB1_A_OUTBYPASS_S)
+#define MCPWM_DB1_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_A_OUTBYPASS_S  15
+/** MCPWM_DB1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB1_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB1_B_OUTBYPASS_M  (MCPWM_DB1_B_OUTBYPASS_V << MCPWM_DB1_B_OUTBYPASS_S)
+#define MCPWM_DB1_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB1_B_OUTBYPASS_S  16
+/** MCPWM_DB1_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+ */
+#define MCPWM_DB1_CLK_SEL    (BIT(17))
+#define MCPWM_DB1_CLK_SEL_M  (MCPWM_DB1_CLK_SEL_V << MCPWM_DB1_CLK_SEL_S)
+#define MCPWM_DB1_CLK_SEL_V  0x00000001U
+#define MCPWM_DB1_CLK_SEL_S  17
+
+/** MCPWM_DT1_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x94)
+/** MCPWM_DB1_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB1_FED    0x0000FFFFU
+#define MCPWM_DB1_FED_M  (MCPWM_DB1_FED_V << MCPWM_DB1_FED_S)
+#define MCPWM_DB1_FED_V  0x0000FFFFU
+#define MCPWM_DB1_FED_S  0
+
+/** MCPWM_DT1_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x98)
+/** MCPWM_DB1_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB1_RED    0x0000FFFFU
+#define MCPWM_DB1_RED_M  (MCPWM_DB1_RED_V << MCPWM_DB1_RED_S)
+#define MCPWM_DB1_RED_V  0x0000FFFFU
+#define MCPWM_DB1_RED_S  0
+
+/** MCPWM_CARRIER1_CFG_REG register
+ *  Carrier$n configuration register
+ */
+#define MCPWM_CARRIER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x9c)
+/** MCPWM_CHOPPER1_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+ */
+#define MCPWM_CHOPPER1_EN    (BIT(0))
+#define MCPWM_CHOPPER1_EN_M  (MCPWM_CHOPPER1_EN_V << MCPWM_CHOPPER1_EN_S)
+#define MCPWM_CHOPPER1_EN_V  0x00000001U
+#define MCPWM_CHOPPER1_EN_S  0
+/** MCPWM_CHOPPER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER1_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_M  (MCPWM_CHOPPER1_PRESCALE_V << MCPWM_CHOPPER1_PRESCALE_S)
+#define MCPWM_CHOPPER1_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER1_PRESCALE_S  1
+/** MCPWM_CHOPPER1_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+ */
+#define MCPWM_CHOPPER1_DUTY    0x00000007U
+#define MCPWM_CHOPPER1_DUTY_M  (MCPWM_CHOPPER1_DUTY_V << MCPWM_CHOPPER1_DUTY_S)
+#define MCPWM_CHOPPER1_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER1_DUTY_S  5
+/** MCPWM_CHOPPER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER1_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_M  (MCPWM_CHOPPER1_OSHTWTH_V << MCPWM_CHOPPER1_OSHTWTH_S)
+#define MCPWM_CHOPPER1_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER1_OSHTWTH_S  8
+/** MCPWM_CHOPPER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER1_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER1_OUT_INVERT_M  (MCPWM_CHOPPER1_OUT_INVERT_V << MCPWM_CHOPPER1_OUT_INVERT_S)
+#define MCPWM_CHOPPER1_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_OUT_INVERT_S  12
+/** MCPWM_CHOPPER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER1_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER1_IN_INVERT_M  (MCPWM_CHOPPER1_IN_INVERT_V << MCPWM_CHOPPER1_IN_INVERT_S)
+#define MCPWM_CHOPPER1_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER1_IN_INVERT_S  13
+
+/** MCPWM_FH1_CFG0_REG register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+#define MCPWM_FH1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xa0)
+/** MCPWM_TZ1_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_SW_CBC    (BIT(0))
+#define MCPWM_TZ1_SW_CBC_M  (MCPWM_TZ1_SW_CBC_V << MCPWM_TZ1_SW_CBC_S)
+#define MCPWM_TZ1_SW_CBC_V  0x00000001U
+#define MCPWM_TZ1_SW_CBC_S  0
+/** MCPWM_TZ1_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F2_CBC    (BIT(1))
+#define MCPWM_TZ1_F2_CBC_M  (MCPWM_TZ1_F2_CBC_V << MCPWM_TZ1_F2_CBC_S)
+#define MCPWM_TZ1_F2_CBC_V  0x00000001U
+#define MCPWM_TZ1_F2_CBC_S  1
+/** MCPWM_TZ1_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F1_CBC    (BIT(2))
+#define MCPWM_TZ1_F1_CBC_M  (MCPWM_TZ1_F1_CBC_V << MCPWM_TZ1_F1_CBC_S)
+#define MCPWM_TZ1_F1_CBC_V  0x00000001U
+#define MCPWM_TZ1_F1_CBC_S  2
+/** MCPWM_TZ1_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F0_CBC    (BIT(3))
+#define MCPWM_TZ1_F0_CBC_M  (MCPWM_TZ1_F0_CBC_V << MCPWM_TZ1_F0_CBC_S)
+#define MCPWM_TZ1_F0_CBC_V  0x00000001U
+#define MCPWM_TZ1_F0_CBC_S  3
+/** MCPWM_TZ1_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_SW_OST    (BIT(4))
+#define MCPWM_TZ1_SW_OST_M  (MCPWM_TZ1_SW_OST_V << MCPWM_TZ1_SW_OST_S)
+#define MCPWM_TZ1_SW_OST_V  0x00000001U
+#define MCPWM_TZ1_SW_OST_S  4
+/** MCPWM_TZ1_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F2_OST    (BIT(5))
+#define MCPWM_TZ1_F2_OST_M  (MCPWM_TZ1_F2_OST_V << MCPWM_TZ1_F2_OST_S)
+#define MCPWM_TZ1_F2_OST_V  0x00000001U
+#define MCPWM_TZ1_F2_OST_S  5
+/** MCPWM_TZ1_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F1_OST    (BIT(6))
+#define MCPWM_TZ1_F1_OST_M  (MCPWM_TZ1_F1_OST_V << MCPWM_TZ1_F1_OST_S)
+#define MCPWM_TZ1_F1_OST_V  0x00000001U
+#define MCPWM_TZ1_F1_OST_S  6
+/** MCPWM_TZ1_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ1_F0_OST    (BIT(7))
+#define MCPWM_TZ1_F0_OST_M  (MCPWM_TZ1_F0_OST_V << MCPWM_TZ1_F0_OST_S)
+#define MCPWM_TZ1_F0_OST_V  0x00000001U
+#define MCPWM_TZ1_F0_OST_S  7
+/** MCPWM_TZ1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_A_CBC_D    0x00000003U
+#define MCPWM_TZ1_A_CBC_D_M  (MCPWM_TZ1_A_CBC_D_V << MCPWM_TZ1_A_CBC_D_S)
+#define MCPWM_TZ1_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_D_S  8
+/** MCPWM_TZ1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_A_CBC_U    0x00000003U
+#define MCPWM_TZ1_A_CBC_U_M  (MCPWM_TZ1_A_CBC_U_V << MCPWM_TZ1_A_CBC_U_S)
+#define MCPWM_TZ1_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_A_CBC_U_S  10
+/** MCPWM_TZ1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_A_OST_D    0x00000003U
+#define MCPWM_TZ1_A_OST_D_M  (MCPWM_TZ1_A_OST_D_V << MCPWM_TZ1_A_OST_D_S)
+#define MCPWM_TZ1_A_OST_D_V  0x00000003U
+#define MCPWM_TZ1_A_OST_D_S  12
+/** MCPWM_TZ1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_A_OST_U    0x00000003U
+#define MCPWM_TZ1_A_OST_U_M  (MCPWM_TZ1_A_OST_U_V << MCPWM_TZ1_A_OST_U_S)
+#define MCPWM_TZ1_A_OST_U_V  0x00000003U
+#define MCPWM_TZ1_A_OST_U_S  14
+/** MCPWM_TZ1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_B_CBC_D    0x00000003U
+#define MCPWM_TZ1_B_CBC_D_M  (MCPWM_TZ1_B_CBC_D_V << MCPWM_TZ1_B_CBC_D_S)
+#define MCPWM_TZ1_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_D_S  16
+/** MCPWM_TZ1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_B_CBC_U    0x00000003U
+#define MCPWM_TZ1_B_CBC_U_M  (MCPWM_TZ1_B_CBC_U_V << MCPWM_TZ1_B_CBC_U_S)
+#define MCPWM_TZ1_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ1_B_CBC_U_S  18
+/** MCPWM_TZ1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_B_OST_D    0x00000003U
+#define MCPWM_TZ1_B_OST_D_M  (MCPWM_TZ1_B_OST_D_V << MCPWM_TZ1_B_OST_D_S)
+#define MCPWM_TZ1_B_OST_D_V  0x00000003U
+#define MCPWM_TZ1_B_OST_D_S  20
+/** MCPWM_TZ1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ1_B_OST_U    0x00000003U
+#define MCPWM_TZ1_B_OST_U_M  (MCPWM_TZ1_B_OST_U_V << MCPWM_TZ1_B_OST_U_S)
+#define MCPWM_TZ1_B_OST_U_V  0x00000003U
+#define MCPWM_TZ1_B_OST_U_S  22
+
+/** MCPWM_FH1_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xa4)
+/** MCPWM_TZ1_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ1_CLR_OST    (BIT(0))
+#define MCPWM_TZ1_CLR_OST_M  (MCPWM_TZ1_CLR_OST_V << MCPWM_TZ1_CLR_OST_S)
+#define MCPWM_TZ1_CLR_OST_V  0x00000001U
+#define MCPWM_TZ1_CLR_OST_S  0
+/** MCPWM_TZ1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+ *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ1_CBCPULSE    0x00000003U
+#define MCPWM_TZ1_CBCPULSE_M  (MCPWM_TZ1_CBCPULSE_V << MCPWM_TZ1_CBCPULSE_S)
+#define MCPWM_TZ1_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ1_CBCPULSE_S  1
+/** MCPWM_TZ1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ1_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ1_FORCE_CBC_M  (MCPWM_TZ1_FORCE_CBC_V << MCPWM_TZ1_FORCE_CBC_S)
+#define MCPWM_TZ1_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ1_FORCE_CBC_S  3
+/** MCPWM_TZ1_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ1_FORCE_OST    (BIT(4))
+#define MCPWM_TZ1_FORCE_OST_M  (MCPWM_TZ1_FORCE_OST_V << MCPWM_TZ1_FORCE_OST_S)
+#define MCPWM_TZ1_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ1_FORCE_OST_S  4
+
+/** MCPWM_FH1_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xa8)
+/** MCPWM_TZ1_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+ *  action\\1: On going
+ */
+#define MCPWM_TZ1_CBC_ON    (BIT(0))
+#define MCPWM_TZ1_CBC_ON_M  (MCPWM_TZ1_CBC_ON_V << MCPWM_TZ1_CBC_ON_S)
+#define MCPWM_TZ1_CBC_ON_V  0x00000001U
+#define MCPWM_TZ1_CBC_ON_S  0
+/** MCPWM_TZ1_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+ *  going
+ */
+#define MCPWM_TZ1_OST_ON    (BIT(1))
+#define MCPWM_TZ1_OST_ON_M  (MCPWM_TZ1_OST_ON_V << MCPWM_TZ1_OST_ON_S)
+#define MCPWM_TZ1_OST_ON_V  0x00000001U
+#define MCPWM_TZ1_OST_ON_S  1
+
+/** MCPWM_GEN2_STMP_CFG_REG register
+ *  Generator2 time stamp registers A and B transfer status and update method register
+ */
+#define MCPWM_GEN2_STMP_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xac)
+/** MCPWM_CMPR0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the update method for PWM generator 2 time stamp A's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_A_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_M  (MCPWM_CMPR0_A_UPMETHOD_V << MCPWM_CMPR0_A_UPMETHOD_S)
+#define MCPWM_CMPR0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_A_UPMETHOD_S  0
+/** MCPWM_CMPR0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the update method for PWM generator 2 time stamp B's active
+ *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+ *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_CMPR0_B_UPMETHOD    0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_M  (MCPWM_CMPR0_B_UPMETHOD_V << MCPWM_CMPR0_B_UPMETHOD_S)
+#define MCPWM_CMPR0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_CMPR0_B_UPMETHOD_S  4
+/** MCPWM_CMPR0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Represents whether or not generator2 time stamp A's shadow reg is transferred.\\0:
+ *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+ *  reg is filled and waiting to be transferred to A's active reg
+ */
+#define MCPWM_CMPR0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_CMPR0_A_SHDW_FULL_M  (MCPWM_CMPR0_A_SHDW_FULL_V << MCPWM_CMPR0_A_SHDW_FULL_S)
+#define MCPWM_CMPR0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_A_SHDW_FULL_S  8
+/** MCPWM_CMPR0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Represents whether or not generator2 time stamp B's shadow reg is transferred.\\0:
+ *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+ *  reg is filled and waiting to be transferred to B's active reg
+ */
+#define MCPWM_CMPR0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_CMPR0_B_SHDW_FULL_M  (MCPWM_CMPR0_B_SHDW_FULL_V << MCPWM_CMPR0_B_SHDW_FULL_S)
+#define MCPWM_CMPR0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_CMPR0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN2_TSTMP_A_REG register
+ *  Generator$n time stamp A's shadow register
+ */
+#define MCPWM_GEN2_TSTMP_A_REG(i) (REG_MCPWM_BASE(i) + 0xb0)
+/** MCPWM_CMPR2_A : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp A's shadow register.
+ */
+#define MCPWM_CMPR2_A    0x0000FFFFU
+#define MCPWM_CMPR2_A_M  (MCPWM_CMPR2_A_V << MCPWM_CMPR2_A_S)
+#define MCPWM_CMPR2_A_V  0x0000FFFFU
+#define MCPWM_CMPR2_A_S  0
+
+/** MCPWM_GEN2_TSTMP_B_REG register
+ *  Generator$n time stamp B's shadow register
+ */
+#define MCPWM_GEN2_TSTMP_B_REG(i) (REG_MCPWM_BASE(i) + 0xb4)
+/** MCPWM_CMPR2_B : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the value of PWM generator $n time stamp B's shadow register.
+ */
+#define MCPWM_CMPR2_B    0x0000FFFFU
+#define MCPWM_CMPR2_B_M  (MCPWM_CMPR2_B_V << MCPWM_CMPR2_B_S)
+#define MCPWM_CMPR2_B_V  0x0000FFFFU
+#define MCPWM_CMPR2_B_S  0
+
+/** MCPWM_GEN2_CFG0_REG register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xb8)
+/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for PWM generator $n's active register.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Configures source selection for PWM generator $n event_t0, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN2_T0_SEL    0x00000007U
+#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
+#define MCPWM_GEN2_T0_SEL_V  0x00000007U
+#define MCPWM_GEN2_T0_SEL_S  4
+/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Configures source selection for PWM generator $n event_t1, take effect
+ *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+ *  Invalid, Select nothing
+ */
+#define MCPWM_GEN2_T1_SEL    0x00000007U
+#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
+#define MCPWM_GEN2_T1_SEL_V  0x00000007U
+#define MCPWM_GEN2_T1_SEL_S  7
+
+/** MCPWM_GEN2_FORCE_REG register
+ *  Generator$n output signal force mode register.
+ */
+#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0xbc)
+/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Configures update method for continuous software force of PWM generator$n.\\0:
+ *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+ *  update. TEA/B here and below means an event generated when the timer's value equals
+ *  to that of register A/B.
+ */
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+ *  High\\3: Disabled
+ */
+#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n A, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
+#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Configures the generation of non-continuous immediate software-force event for
+ *  PWM$n B, a toggle will trigger a force event.
+ */
+#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
+#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+ *  Disabled\\1: Low\\2: High\\3: Disabled
+ */
+#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN2_A_REG register
+ *  PWM$n output signal A actions configuration register
+ */
+#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0xc0)
+/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEZ    0x00000003U
+#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
+#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_UTEZ_S  0
+/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEP    0x00000003U
+#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
+#define MCPWM_GEN2_A_UTEP_V  0x00000003U
+#define MCPWM_GEN2_A_UTEP_S  2
+/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEA    0x00000003U
+#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
+#define MCPWM_GEN2_A_UTEA_V  0x00000003U
+#define MCPWM_GEN2_A_UTEA_S  4
+/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UTEB    0x00000003U
+#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
+#define MCPWM_GEN2_A_UTEB_V  0x00000003U
+#define MCPWM_GEN2_A_UTEB_S  6
+/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UT0    0x00000003U
+#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
+#define MCPWM_GEN2_A_UT0_V  0x00000003U
+#define MCPWM_GEN2_A_UT0_S  8
+/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_UT1    0x00000003U
+#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
+#define MCPWM_GEN2_A_UT1_V  0x00000003U
+#define MCPWM_GEN2_A_UT1_S  10
+/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEZ    0x00000003U
+#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
+#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_DTEZ_S  12
+/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEP    0x00000003U
+#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
+#define MCPWM_GEN2_A_DTEP_V  0x00000003U
+#define MCPWM_GEN2_A_DTEP_S  14
+/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEA    0x00000003U
+#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
+#define MCPWM_GEN2_A_DTEA_V  0x00000003U
+#define MCPWM_GEN2_A_DTEA_S  16
+/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DTEB    0x00000003U
+#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
+#define MCPWM_GEN2_A_DTEB_V  0x00000003U
+#define MCPWM_GEN2_A_DTEB_S  18
+/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DT0    0x00000003U
+#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
+#define MCPWM_GEN2_A_DT0_V  0x00000003U
+#define MCPWM_GEN2_A_DT0_S  20
+/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_A_DT1    0x00000003U
+#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
+#define MCPWM_GEN2_A_DT1_V  0x00000003U
+#define MCPWM_GEN2_A_DT1_S  22
+
+/** MCPWM_GEN2_B_REG register
+ *  PWM$n output signal B actions configuration register
+ */
+#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0xc4)
+/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEZ    0x00000003U
+#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
+#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_UTEZ_S  0
+/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEP    0x00000003U
+#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
+#define MCPWM_GEN2_B_UTEP_V  0x00000003U
+#define MCPWM_GEN2_B_UTEP_S  2
+/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEA    0x00000003U
+#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
+#define MCPWM_GEN2_B_UTEA_V  0x00000003U
+#define MCPWM_GEN2_B_UTEA_S  4
+/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UTEB    0x00000003U
+#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
+#define MCPWM_GEN2_B_UTEB_V  0x00000003U
+#define MCPWM_GEN2_B_UTEB_S  6
+/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UT0    0x00000003U
+#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
+#define MCPWM_GEN2_B_UT0_V  0x00000003U
+#define MCPWM_GEN2_B_UT0_S  8
+/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer increasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_UT1    0x00000003U
+#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
+#define MCPWM_GEN2_B_UT1_V  0x00000003U
+#define MCPWM_GEN2_B_UT1_S  10
+/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEZ when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEZ    0x00000003U
+#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
+#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_DTEZ_S  12
+/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEP when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEP    0x00000003U
+#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
+#define MCPWM_GEN2_B_DTEP_V  0x00000003U
+#define MCPWM_GEN2_B_DTEP_S  14
+/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEA when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEA    0x00000003U
+#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
+#define MCPWM_GEN2_B_DTEA_V  0x00000003U
+#define MCPWM_GEN2_B_DTEA_S  16
+/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Configures action on PWM$n B triggered by event TEB when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DTEB    0x00000003U
+#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
+#define MCPWM_GEN2_B_DTEB_V  0x00000003U
+#define MCPWM_GEN2_B_DTEB_S  18
+/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t0 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DT0    0x00000003U
+#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
+#define MCPWM_GEN2_B_DT0_V  0x00000003U
+#define MCPWM_GEN2_B_DT0_S  20
+/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Configures action on PWM$n B triggered by event_t1 when timer decreasing.\\0: No
+ *  change\\1: Low\\2: High\\3: Toggle
+ */
+#define MCPWM_GEN2_B_DT1    0x00000003U
+#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
+#define MCPWM_GEN2_B_DT1_V  0x00000003U
+#define MCPWM_GEN2_B_DT1_S  22
+
+/** MCPWM_DT2_CFG_REG register
+ *  Dead time configuration register
+ */
+#define MCPWM_DT2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xc8)
+/** MCPWM_DB2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Configures update method for FED (Falling edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB2_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_M  (MCPWM_DB2_FED_UPMETHOD_V << MCPWM_DB2_FED_UPMETHOD_S)
+#define MCPWM_DB2_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_FED_UPMETHOD_S  0
+/** MCPWM_DB2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Configures update method for RED (rising edge delay) active register.\\0:
+ *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+ *  Sync\\Bit3 is set to 1: Disable the update
+ */
+#define MCPWM_DB2_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_M  (MCPWM_DB2_RED_UPMETHOD_V << MCPWM_DB2_RED_UPMETHOD_S)
+#define MCPWM_DB2_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DB2_RED_UPMETHOD_S  4
+/** MCPWM_DB2_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+ *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DB2_DEB_MODE    (BIT(8))
+#define MCPWM_DB2_DEB_MODE_M  (MCPWM_DB2_DEB_MODE_V << MCPWM_DB2_DEB_MODE_S)
+#define MCPWM_DB2_DEB_MODE_V  0x00000001U
+#define MCPWM_DB2_DEB_MODE_S  8
+/** MCPWM_DB2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  Configures S6 in table.
+ */
+#define MCPWM_DB2_A_OUTSWAP    (BIT(9))
+#define MCPWM_DB2_A_OUTSWAP_M  (MCPWM_DB2_A_OUTSWAP_V << MCPWM_DB2_A_OUTSWAP_S)
+#define MCPWM_DB2_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_A_OUTSWAP_S  9
+/** MCPWM_DB2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  Configures S7 in table.
+ */
+#define MCPWM_DB2_B_OUTSWAP    (BIT(10))
+#define MCPWM_DB2_B_OUTSWAP_M  (MCPWM_DB2_B_OUTSWAP_V << MCPWM_DB2_B_OUTSWAP_S)
+#define MCPWM_DB2_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DB2_B_OUTSWAP_S  10
+/** MCPWM_DB2_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  Configures S4 in table.
+ */
+#define MCPWM_DB2_RED_INSEL    (BIT(11))
+#define MCPWM_DB2_RED_INSEL_M  (MCPWM_DB2_RED_INSEL_V << MCPWM_DB2_RED_INSEL_S)
+#define MCPWM_DB2_RED_INSEL_V  0x00000001U
+#define MCPWM_DB2_RED_INSEL_S  11
+/** MCPWM_DB2_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  Configures S5 in table.
+ */
+#define MCPWM_DB2_FED_INSEL    (BIT(12))
+#define MCPWM_DB2_FED_INSEL_M  (MCPWM_DB2_FED_INSEL_V << MCPWM_DB2_FED_INSEL_S)
+#define MCPWM_DB2_FED_INSEL_V  0x00000001U
+#define MCPWM_DB2_FED_INSEL_S  12
+/** MCPWM_DB2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures S2 in table.
+ */
+#define MCPWM_DB2_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DB2_RED_OUTINVERT_M  (MCPWM_DB2_RED_OUTINVERT_V << MCPWM_DB2_RED_OUTINVERT_S)
+#define MCPWM_DB2_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_RED_OUTINVERT_S  13
+/** MCPWM_DB2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  Configures S3 in table.
+ */
+#define MCPWM_DB2_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DB2_FED_OUTINVERT_M  (MCPWM_DB2_FED_OUTINVERT_V << MCPWM_DB2_FED_OUTINVERT_S)
+#define MCPWM_DB2_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DB2_FED_OUTINVERT_S  14
+/** MCPWM_DB2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  Configures S1 in table.
+ */
+#define MCPWM_DB2_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DB2_A_OUTBYPASS_M  (MCPWM_DB2_A_OUTBYPASS_V << MCPWM_DB2_A_OUTBYPASS_S)
+#define MCPWM_DB2_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_A_OUTBYPASS_S  15
+/** MCPWM_DB2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  Configures S0 in table.
+ */
+#define MCPWM_DB2_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DB2_B_OUTBYPASS_M  (MCPWM_DB2_B_OUTBYPASS_V << MCPWM_DB2_B_OUTBYPASS_S)
+#define MCPWM_DB2_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DB2_B_OUTBYPASS_S  16
+/** MCPWM_DB2_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+ */
+#define MCPWM_DB2_CLK_SEL    (BIT(17))
+#define MCPWM_DB2_CLK_SEL_M  (MCPWM_DB2_CLK_SEL_V << MCPWM_DB2_CLK_SEL_S)
+#define MCPWM_DB2_CLK_SEL_V  0x00000001U
+#define MCPWM_DB2_CLK_SEL_S  17
+
+/** MCPWM_DT2_FED_CFG_REG register
+ *  Falling edge delay (FED) shadow register
+ */
+#define MCPWM_DT2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xcc)
+/** MCPWM_DB2_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for FED.
+ */
+#define MCPWM_DB2_FED    0x0000FFFFU
+#define MCPWM_DB2_FED_M  (MCPWM_DB2_FED_V << MCPWM_DB2_FED_S)
+#define MCPWM_DB2_FED_V  0x0000FFFFU
+#define MCPWM_DB2_FED_S  0
+
+/** MCPWM_DT2_RED_CFG_REG register
+ *  Rising edge delay (RED) shadow register
+ */
+#define MCPWM_DT2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd0)
+/** MCPWM_DB2_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Configures shadow register for RED.
+ */
+#define MCPWM_DB2_RED    0x0000FFFFU
+#define MCPWM_DB2_RED_M  (MCPWM_DB2_RED_V << MCPWM_DB2_RED_S)
+#define MCPWM_DB2_RED_V  0x0000FFFFU
+#define MCPWM_DB2_RED_S  0
+
+/** MCPWM_CARRIER2_CFG_REG register
+ *  Carrier$n configuration register
+ */
+#define MCPWM_CARRIER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xd4)
+/** MCPWM_CHOPPER2_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+ */
+#define MCPWM_CHOPPER2_EN    (BIT(0))
+#define MCPWM_CHOPPER2_EN_M  (MCPWM_CHOPPER2_EN_V << MCPWM_CHOPPER2_EN_S)
+#define MCPWM_CHOPPER2_EN_V  0x00000001U
+#define MCPWM_CHOPPER2_EN_S  0
+/** MCPWM_CHOPPER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+ *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+ */
+#define MCPWM_CHOPPER2_PRESCALE    0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_M  (MCPWM_CHOPPER2_PRESCALE_V << MCPWM_CHOPPER2_PRESCALE_S)
+#define MCPWM_CHOPPER2_PRESCALE_V  0x0000000FU
+#define MCPWM_CHOPPER2_PRESCALE_S  1
+/** MCPWM_CHOPPER2_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+ */
+#define MCPWM_CHOPPER2_DUTY    0x00000007U
+#define MCPWM_CHOPPER2_DUTY_M  (MCPWM_CHOPPER2_DUTY_V << MCPWM_CHOPPER2_DUTY_S)
+#define MCPWM_CHOPPER2_DUTY_V  0x00000007U
+#define MCPWM_CHOPPER2_DUTY_S  5
+/** MCPWM_CHOPPER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+ */
+#define MCPWM_CHOPPER2_OSHTWTH    0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_M  (MCPWM_CHOPPER2_OSHTWTH_V << MCPWM_CHOPPER2_OSHTWTH_S)
+#define MCPWM_CHOPPER2_OSHTWTH_V  0x0000000FU
+#define MCPWM_CHOPPER2_OSHTWTH_S  8
+/** MCPWM_CHOPPER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER2_OUT_INVERT    (BIT(12))
+#define MCPWM_CHOPPER2_OUT_INVERT_M  (MCPWM_CHOPPER2_OUT_INVERT_V << MCPWM_CHOPPER2_OUT_INVERT_S)
+#define MCPWM_CHOPPER2_OUT_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_OUT_INVERT_S  12
+/** MCPWM_CHOPPER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+ *  submodule.\\0: Normal\\1: Invert
+ */
+#define MCPWM_CHOPPER2_IN_INVERT    (BIT(13))
+#define MCPWM_CHOPPER2_IN_INVERT_M  (MCPWM_CHOPPER2_IN_INVERT_V << MCPWM_CHOPPER2_IN_INVERT_S)
+#define MCPWM_CHOPPER2_IN_INVERT_V  0x00000001U
+#define MCPWM_CHOPPER2_IN_INVERT_S  13
+
+/** MCPWM_FH2_CFG0_REG register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+#define MCPWM_FH2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0xd8)
+/** MCPWM_TZ2_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_SW_CBC    (BIT(0))
+#define MCPWM_TZ2_SW_CBC_M  (MCPWM_TZ2_SW_CBC_V << MCPWM_TZ2_SW_CBC_S)
+#define MCPWM_TZ2_SW_CBC_V  0x00000001U
+#define MCPWM_TZ2_SW_CBC_S  0
+/** MCPWM_TZ2_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F2_CBC    (BIT(1))
+#define MCPWM_TZ2_F2_CBC_M  (MCPWM_TZ2_F2_CBC_V << MCPWM_TZ2_F2_CBC_S)
+#define MCPWM_TZ2_F2_CBC_V  0x00000001U
+#define MCPWM_TZ2_F2_CBC_S  1
+/** MCPWM_TZ2_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F1_CBC    (BIT(2))
+#define MCPWM_TZ2_F1_CBC_M  (MCPWM_TZ2_F1_CBC_V << MCPWM_TZ2_F1_CBC_S)
+#define MCPWM_TZ2_F1_CBC_V  0x00000001U
+#define MCPWM_TZ2_F1_CBC_S  2
+/** MCPWM_TZ2_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F0_CBC    (BIT(3))
+#define MCPWM_TZ2_F0_CBC_M  (MCPWM_TZ2_F0_CBC_V << MCPWM_TZ2_F0_CBC_S)
+#define MCPWM_TZ2_F0_CBC_V  0x00000001U
+#define MCPWM_TZ2_F0_CBC_S  3
+/** MCPWM_TZ2_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable software force one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_SW_OST    (BIT(4))
+#define MCPWM_TZ2_SW_OST_M  (MCPWM_TZ2_SW_OST_V << MCPWM_TZ2_SW_OST_S)
+#define MCPWM_TZ2_SW_OST_V  0x00000001U
+#define MCPWM_TZ2_SW_OST_S  4
+/** MCPWM_TZ2_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F2_OST    (BIT(5))
+#define MCPWM_TZ2_F2_OST_M  (MCPWM_TZ2_F2_OST_V << MCPWM_TZ2_F2_OST_S)
+#define MCPWM_TZ2_F2_OST_V  0x00000001U
+#define MCPWM_TZ2_F2_OST_S  5
+/** MCPWM_TZ2_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F1_OST    (BIT(6))
+#define MCPWM_TZ2_F1_OST_M  (MCPWM_TZ2_F1_OST_V << MCPWM_TZ2_F1_OST_S)
+#define MCPWM_TZ2_F1_OST_V  0x00000001U
+#define MCPWM_TZ2_F1_OST_S  6
+/** MCPWM_TZ2_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TZ2_F0_OST    (BIT(7))
+#define MCPWM_TZ2_F0_OST_M  (MCPWM_TZ2_F0_OST_V << MCPWM_TZ2_F0_OST_S)
+#define MCPWM_TZ2_F0_OST_V  0x00000001U
+#define MCPWM_TZ2_F0_OST_S  7
+/** MCPWM_TZ2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_A_CBC_D    0x00000003U
+#define MCPWM_TZ2_A_CBC_D_M  (MCPWM_TZ2_A_CBC_D_V << MCPWM_TZ2_A_CBC_D_S)
+#define MCPWM_TZ2_A_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_D_S  8
+/** MCPWM_TZ2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_A_CBC_U    0x00000003U
+#define MCPWM_TZ2_A_CBC_U_M  (MCPWM_TZ2_A_CBC_U_V << MCPWM_TZ2_A_CBC_U_S)
+#define MCPWM_TZ2_A_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_A_CBC_U_S  10
+/** MCPWM_TZ2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_A_OST_D    0x00000003U
+#define MCPWM_TZ2_A_OST_D_M  (MCPWM_TZ2_A_OST_D_V << MCPWM_TZ2_A_OST_D_S)
+#define MCPWM_TZ2_A_OST_D_V  0x00000003U
+#define MCPWM_TZ2_A_OST_D_S  12
+/** MCPWM_TZ2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_A_OST_U    0x00000003U
+#define MCPWM_TZ2_A_OST_U_M  (MCPWM_TZ2_A_OST_U_V << MCPWM_TZ2_A_OST_U_S)
+#define MCPWM_TZ2_A_OST_U_V  0x00000003U
+#define MCPWM_TZ2_A_OST_U_S  14
+/** MCPWM_TZ2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_B_CBC_D    0x00000003U
+#define MCPWM_TZ2_B_CBC_D_M  (MCPWM_TZ2_B_CBC_D_V << MCPWM_TZ2_B_CBC_D_S)
+#define MCPWM_TZ2_B_CBC_D_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_D_S  16
+/** MCPWM_TZ2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+ *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_B_CBC_U    0x00000003U
+#define MCPWM_TZ2_B_CBC_U_M  (MCPWM_TZ2_B_CBC_U_V << MCPWM_TZ2_B_CBC_U_S)
+#define MCPWM_TZ2_B_CBC_U_V  0x00000003U
+#define MCPWM_TZ2_B_CBC_U_S  18
+/** MCPWM_TZ2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_B_OST_D    0x00000003U
+#define MCPWM_TZ2_B_OST_D_M  (MCPWM_TZ2_B_OST_D_V << MCPWM_TZ2_B_OST_D_S)
+#define MCPWM_TZ2_B_OST_D_V  0x00000003U
+#define MCPWM_TZ2_B_OST_D_S  20
+/** MCPWM_TZ2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+ *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+ */
+#define MCPWM_TZ2_B_OST_U    0x00000003U
+#define MCPWM_TZ2_B_OST_U_M  (MCPWM_TZ2_B_OST_U_V << MCPWM_TZ2_B_OST_U_S)
+#define MCPWM_TZ2_B_OST_U_V  0x00000003U
+#define MCPWM_TZ2_B_OST_U_S  22
+
+/** MCPWM_FH2_CFG1_REG register
+ *  Software triggers for fault handler actions configuration register
+ */
+#define MCPWM_FH2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0xdc)
+/** MCPWM_TZ2_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  Configures the generation of software one-shot mode action clear. A toggle
+ *  (software negate its value) triggers a clear for on going one-shot mode action.
+ */
+#define MCPWM_TZ2_CLR_OST    (BIT(0))
+#define MCPWM_TZ2_CLR_OST_M  (MCPWM_TZ2_CLR_OST_V << MCPWM_TZ2_CLR_OST_S)
+#define MCPWM_TZ2_CLR_OST_V  0x00000001U
+#define MCPWM_TZ2_CLR_OST_S  0
+/** MCPWM_TZ2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+ *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+ */
+#define MCPWM_TZ2_CBCPULSE    0x00000003U
+#define MCPWM_TZ2_CBCPULSE_M  (MCPWM_TZ2_CBCPULSE_V << MCPWM_TZ2_CBCPULSE_S)
+#define MCPWM_TZ2_CBCPULSE_V  0x00000003U
+#define MCPWM_TZ2_CBCPULSE_S  1
+/** MCPWM_TZ2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of software cycle-by-cycle mode action. A toggle
+ *  (software negate its value) triggers a cycle-by-cycle mode action.
+ */
+#define MCPWM_TZ2_FORCE_CBC    (BIT(3))
+#define MCPWM_TZ2_FORCE_CBC_M  (MCPWM_TZ2_FORCE_CBC_V << MCPWM_TZ2_FORCE_CBC_S)
+#define MCPWM_TZ2_FORCE_CBC_V  0x00000001U
+#define MCPWM_TZ2_FORCE_CBC_S  3
+/** MCPWM_TZ2_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  Configures the generation of software one-shot mode action. A toggle (software
+ *  negate its value) triggers a one-shot mode action.
+ */
+#define MCPWM_TZ2_FORCE_OST    (BIT(4))
+#define MCPWM_TZ2_FORCE_OST_M  (MCPWM_TZ2_FORCE_OST_V << MCPWM_TZ2_FORCE_OST_S)
+#define MCPWM_TZ2_FORCE_OST_V  0x00000001U
+#define MCPWM_TZ2_FORCE_OST_S  4
+
+/** MCPWM_FH2_STATUS_REG register
+ *  Fault events status register
+ */
+#define MCPWM_FH2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0xe0)
+/** MCPWM_TZ2_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+ *  action\\1: On going
+ */
+#define MCPWM_TZ2_CBC_ON    (BIT(0))
+#define MCPWM_TZ2_CBC_ON_M  (MCPWM_TZ2_CBC_ON_V << MCPWM_TZ2_CBC_ON_S)
+#define MCPWM_TZ2_CBC_ON_V  0x00000001U
+#define MCPWM_TZ2_CBC_ON_S  0
+/** MCPWM_TZ2_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+ *  going
+ */
+#define MCPWM_TZ2_OST_ON    (BIT(1))
+#define MCPWM_TZ2_OST_ON_M  (MCPWM_TZ2_OST_ON_V << MCPWM_TZ2_OST_ON_S)
+#define MCPWM_TZ2_OST_ON_V  0x00000001U
+#define MCPWM_TZ2_OST_ON_S  1
+
+/** MCPWM_FAULT_DETECT_REG register
+ *  Fault detection configuration and status register
+ */
+#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0xe4)
+/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
+ */
+#define MCPWM_F0_EN    (BIT(0))
+#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
+#define MCPWM_F0_EN_V  0x00000001U
+#define MCPWM_F0_EN_S  0
+/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
+ */
+#define MCPWM_F1_EN    (BIT(1))
+#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
+#define MCPWM_F1_EN_V  0x00000001U
+#define MCPWM_F1_EN_S  1
+/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
+ */
+#define MCPWM_F2_EN    (BIT(2))
+#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
+#define MCPWM_F2_EN_V  0x00000001U
+#define MCPWM_F2_EN_S  2
+/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
+ *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
+ *  low\\1: Level high
+ */
+#define MCPWM_F0_POLE    (BIT(3))
+#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
+#define MCPWM_F0_POLE_V  0x00000001U
+#define MCPWM_F0_POLE_S  3
+/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
+ *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
+ *  low\\1: Level high
+ */
+#define MCPWM_F1_POLE    (BIT(4))
+#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
+#define MCPWM_F1_POLE_V  0x00000001U
+#define MCPWM_F1_POLE_S  4
+/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
+ *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
+ *  low\\1: Level high
+ */
+#define MCPWM_F2_POLE    (BIT(5))
+#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
+#define MCPWM_F2_POLE_V  0x00000001U
+#define MCPWM_F2_POLE_S  5
+/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
+ *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
+ */
+#define MCPWM_EVENT_F0    (BIT(6))
+#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
+#define MCPWM_EVENT_F0_V  0x00000001U
+#define MCPWM_EVENT_F0_S  6
+/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
+ *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
+ */
+#define MCPWM_EVENT_F1    (BIT(7))
+#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
+#define MCPWM_EVENT_F1_V  0x00000001U
+#define MCPWM_EVENT_F1_S  7
+/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
+ *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
+ */
+#define MCPWM_EVENT_F2    (BIT(8))
+#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
+#define MCPWM_EVENT_F2_V  0x00000001U
+#define MCPWM_EVENT_F2_S  8
+
+/** MCPWM_CAP_TIMER_CFG_REG register
+ *  Capture timer configuration register
+ */
+#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xe8)
+/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP_TIMER_EN    (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
+#define MCPWM_CAP_TIMER_EN_V  0x00000001U
+#define MCPWM_CAP_TIMER_EN_S  0
+/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP_SYNCI_EN    (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
+#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
+#define MCPWM_CAP_SYNCI_EN_S  1
+/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
+ *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
+ *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
+ */
+#define MCPWM_CAP_SYNCI_SEL    0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
+#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
+ *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
+ *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
+ *  value in phase register
+ */
+#define MCPWM_CAP_SYNC_SW    (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
+#define MCPWM_CAP_SYNC_SW_V  0x00000001U
+#define MCPWM_CAP_SYNC_SW_S  5
+
+/** MCPWM_CAP_TIMER_PHASE_REG register
+ *  Capture timer sync phase register
+ */
+#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0xec)
+/** MCPWM_CAP_PHASE : R/W; bitpos: [31:0]; default: 0;
+ *  Configures phase value for capture timer sync operation.
+ */
+#define MCPWM_CAP_PHASE    0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_M  (MCPWM_CAP_PHASE_V << MCPWM_CAP_PHASE_S)
+#define MCPWM_CAP_PHASE_V  0xFFFFFFFFU
+#define MCPWM_CAP_PHASE_S  0
+
+/** MCPWM_CAP_CH0_CFG_REG register
+ *  Capture channel 0 configuration register
+ */
+#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf0)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 0.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 0 after prescaling is used.\\0:
+ *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+ *  Enable capture on the positive edge
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on positive edge of CAP0. Prescale value =
+ *  PWM_CAP0_PRESCALE + 1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP0 from GPIO matrix before prescale.\\0:
+ *  Normal\\1: Invert
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+ *  software forced capture on channel 0
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH1_CFG_REG register
+ *  Capture channel 1 configuration register
+ */
+#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf4)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 1.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 1 after prescaling is used.\\0:
+ *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+ *  Enable capture on the positive edge
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on positive edge of CAP1. Prescale value =
+ *  PWM_CAP1_PRESCALE + 1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP1 from GPIO matrix before prescale.\\0:
+ *  Normal\\1: Invert
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+ *  software forced capture on channel 1
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH2_CFG_REG register
+ *  Capture channel 2 configuration register
+ */
+#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0xf8)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable capture on channel 2.\\0: Disable\\1: Enable
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Configures which edge of capture on channel 2 after prescaling is used.\\0:
+ *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+ *  Enable capture on the positive edge
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Configures prescale value on positive edge of CAP2. Prescale value =
+ *  PWM_CAP2_PRESCALE + 1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert CAP2 from GPIO matrix before prescale.\\0:
+ *  Normal\\1: Invert
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+ *  software forced capture on channel 2
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH0_REG register
+ *  CAP0 capture value register
+ */
+#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0xfc)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP0
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_CH1_REG register
+ *  CAP1 capture value register
+ */
+#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x100)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP1
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_CH2_REG register
+ *  CAP2 capture value register
+ */
+#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x104)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Represents value of last capture on CAP2
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_STATUS_REG register
+ *  Last capture trigger edge information register
+ */
+#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x108)
+/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
+ *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
+ */
+#define MCPWM_CAP0_EDGE    (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
+#define MCPWM_CAP0_EDGE_V  0x00000001U
+#define MCPWM_CAP0_EDGE_S  0
+/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
+ *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
+ */
+#define MCPWM_CAP1_EDGE    (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
+#define MCPWM_CAP1_EDGE_V  0x00000001U
+#define MCPWM_CAP1_EDGE_S  1
+/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
+ *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
+ */
+#define MCPWM_CAP2_EDGE    (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
+#define MCPWM_CAP2_EDGE_V  0x00000001U
+#define MCPWM_CAP2_EDGE_S  2
+
+/** MCPWM_UPDATE_CFG_REG register
+ *  Generator Update configuration register
+ */
+#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x10c)
+/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether or not to enable global update for all active registers in MCPWM
+ *  module.\\0: Disable\\1: Enable
+ */
+#define MCPWM_GLOBAL_UP_EN    (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
+#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
+#define MCPWM_GLOBAL_UP_EN_S  0
+/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
+ *  Configures the generation of global forced update for all active registers in MCPWM
+ *  module. A toggle (software invert its value) will trigger a global forced update.
+ *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
+ */
+#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
+#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator$n.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+ */
+#define MCPWM_OP0_UP_EN    (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
+#define MCPWM_OP0_UP_EN_V  0x00000001U
+#define MCPWM_OP0_UP_EN_S  2
+/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator0. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
+ */
+#define MCPWM_OP0_FORCE_UP    (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
+#define MCPWM_OP0_FORCE_UP_V  0x00000001U
+#define MCPWM_OP0_FORCE_UP_S  3
+/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator$n.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+ */
+#define MCPWM_OP1_UP_EN    (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
+#define MCPWM_OP1_UP_EN_V  0x00000001U
+#define MCPWM_OP1_UP_EN_S  4
+/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator1. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
+ */
+#define MCPWM_OP1_FORCE_UP    (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
+#define MCPWM_OP1_FORCE_UP_V  0x00000001U
+#define MCPWM_OP1_FORCE_UP_S  5
+/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
+ *  Configures whether or not to enable update of active registers in PWM operator$n.
+ *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+ */
+#define MCPWM_OP2_UP_EN    (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
+#define MCPWM_OP2_UP_EN_V  0x00000001U
+#define MCPWM_OP2_UP_EN_S  6
+/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
+ *  Configures the generation of forced update for active registers in PWM operator2. A
+ *  toggle (software invert its value) will trigger a forced update. Valid only when
+ *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
+ */
+#define MCPWM_OP2_FORCE_UP    (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
+#define MCPWM_OP2_FORCE_UP_V  0x00000001U
+#define MCPWM_OP2_FORCE_UP_S  7
+
+/** MCPWM_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define MCPWM_INT_ENA_REG(i) (REG_MCPWM_BASE(i) + 0x110)
+/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ENA    (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
+#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_INT_ENA_S  9
+/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ENA    (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
+#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_INT_ENA_S  10
+/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ENA    (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
+#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_INT_ENA_S  11
+/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/** MCPWM_CMPR0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
+ */
+#define MCPWM_CMPR0_TEA_INT_ENA    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ENA_M  (MCPWM_CMPR0_TEA_INT_ENA_V << MCPWM_CMPR0_TEA_INT_ENA_S)
+#define MCPWM_CMPR0_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ENA_S  15
+/** MCPWM_CMPR1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
+ */
+#define MCPWM_CMPR1_TEA_INT_ENA    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ENA_M  (MCPWM_CMPR1_TEA_INT_ENA_V << MCPWM_CMPR1_TEA_INT_ENA_S)
+#define MCPWM_CMPR1_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ENA_S  16
+/** MCPWM_CMPR2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
+ */
+#define MCPWM_CMPR2_TEA_INT_ENA    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ENA_M  (MCPWM_CMPR2_TEA_INT_ENA_V << MCPWM_CMPR2_TEA_INT_ENA_S)
+#define MCPWM_CMPR2_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ENA_S  17
+/** MCPWM_CMPR0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
+ */
+#define MCPWM_CMPR0_TEB_INT_ENA    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ENA_M  (MCPWM_CMPR0_TEB_INT_ENA_V << MCPWM_CMPR0_TEB_INT_ENA_S)
+#define MCPWM_CMPR0_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ENA_S  18
+/** MCPWM_CMPR1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
+ */
+#define MCPWM_CMPR1_TEB_INT_ENA    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ENA_M  (MCPWM_CMPR1_TEB_INT_ENA_V << MCPWM_CMPR1_TEB_INT_ENA_S)
+#define MCPWM_CMPR1_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ENA_S  19
+/** MCPWM_CMPR2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
+ */
+#define MCPWM_CMPR2_TEB_INT_ENA    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ENA_M  (MCPWM_CMPR2_TEB_INT_ENA_V << MCPWM_CMPR2_TEB_INT_ENA_S)
+#define MCPWM_CMPR2_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ENA_S  20
+/** MCPWM_TZ0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ENA    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ENA_M  (MCPWM_TZ0_CBC_INT_ENA_V << MCPWM_TZ0_CBC_INT_ENA_S)
+#define MCPWM_TZ0_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ENA_S  21
+/** MCPWM_TZ1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ENA    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ENA_M  (MCPWM_TZ1_CBC_INT_ENA_V << MCPWM_TZ1_CBC_INT_ENA_S)
+#define MCPWM_TZ1_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ENA_S  22
+/** MCPWM_TZ2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+ *  action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ENA    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ENA_M  (MCPWM_TZ2_CBC_INT_ENA_V << MCPWM_TZ2_CBC_INT_ENA_S)
+#define MCPWM_TZ2_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ENA_S  23
+/** MCPWM_TZ0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ENA    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ENA_M  (MCPWM_TZ0_OST_INT_ENA_V << MCPWM_TZ0_OST_INT_ENA_S)
+#define MCPWM_TZ0_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ENA_S  24
+/** MCPWM_TZ1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ENA    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ENA_M  (MCPWM_TZ1_OST_INT_ENA_V << MCPWM_TZ1_OST_INT_ENA_S)
+#define MCPWM_TZ1_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ENA_S  25
+/** MCPWM_TZ2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ENA    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ENA_M  (MCPWM_TZ2_OST_INT_ENA_V << MCPWM_TZ2_OST_INT_ENA_S)
+#define MCPWM_TZ2_OST_INT_ENA_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ENA_S  26
+/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_ENA    (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
+#define MCPWM_CAP0_INT_ENA_V  0x00000001U
+#define MCPWM_CAP0_INT_ENA_S  27
+/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_ENA    (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
+#define MCPWM_CAP1_INT_ENA_V  0x00000001U
+#define MCPWM_CAP1_INT_ENA_S  28
+/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_ENA    (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
+#define MCPWM_CAP2_INT_ENA_V  0x00000001U
+#define MCPWM_CAP2_INT_ENA_S  29
+
+/** MCPWM_INT_RAW_REG register
+ *  Interrupt raw status register
+ */
+#define MCPWM_INT_RAW_REG(i) (REG_MCPWM_BASE(i) + 0x114)
+/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+ *  2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+ *  2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+ *  starts.
+ */
+#define MCPWM_FAULT0_INT_RAW    (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
+#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_INT_RAW_S  9
+/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+ *  starts.
+ */
+#define MCPWM_FAULT1_INT_RAW    (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
+#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_INT_RAW_S  10
+/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+ *  starts.
+ */
+#define MCPWM_FAULT2_INT_RAW    (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
+#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_INT_RAW_S  11
+/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+ *  clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+ *  clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+ *  clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/** MCPWM_CMPR0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_RAW    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_RAW_M  (MCPWM_CMPR0_TEA_INT_RAW_V << MCPWM_CMPR0_TEA_INT_RAW_S)
+#define MCPWM_CMPR0_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_RAW_S  15
+/** MCPWM_CMPR1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_RAW    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_RAW_M  (MCPWM_CMPR1_TEA_INT_RAW_V << MCPWM_CMPR1_TEA_INT_RAW_S)
+#define MCPWM_CMPR1_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_RAW_S  16
+/** MCPWM_CMPR2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_RAW    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_RAW_M  (MCPWM_CMPR2_TEA_INT_RAW_V << MCPWM_CMPR2_TEA_INT_RAW_S)
+#define MCPWM_CMPR2_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_RAW_S  17
+/** MCPWM_CMPR0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_RAW    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_RAW_M  (MCPWM_CMPR0_TEB_INT_RAW_V << MCPWM_CMPR0_TEB_INT_RAW_S)
+#define MCPWM_CMPR0_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_RAW_S  18
+/** MCPWM_CMPR1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_RAW    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_RAW_M  (MCPWM_CMPR1_TEB_INT_RAW_V << MCPWM_CMPR1_TEB_INT_RAW_S)
+#define MCPWM_CMPR1_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_RAW_S  19
+/** MCPWM_CMPR2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_RAW    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_RAW_M  (MCPWM_CMPR2_TEB_INT_RAW_V << MCPWM_CMPR2_TEB_INT_RAW_S)
+#define MCPWM_CMPR2_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_RAW_S  20
+/** MCPWM_TZ0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_RAW    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_RAW_M  (MCPWM_TZ0_CBC_INT_RAW_V << MCPWM_TZ0_CBC_INT_RAW_S)
+#define MCPWM_TZ0_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_RAW_S  21
+/** MCPWM_TZ1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_RAW    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_RAW_M  (MCPWM_TZ1_CBC_INT_RAW_V << MCPWM_TZ1_CBC_INT_RAW_S)
+#define MCPWM_TZ1_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_RAW_S  22
+/** MCPWM_TZ2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_RAW    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_RAW_M  (MCPWM_TZ2_CBC_INT_RAW_V << MCPWM_TZ2_CBC_INT_RAW_S)
+#define MCPWM_TZ2_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_RAW_S  23
+/** MCPWM_TZ0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_RAW    (BIT(24))
+#define MCPWM_TZ0_OST_INT_RAW_M  (MCPWM_TZ0_OST_INT_RAW_V << MCPWM_TZ0_OST_INT_RAW_S)
+#define MCPWM_TZ0_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_RAW_S  24
+/** MCPWM_TZ1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_RAW    (BIT(25))
+#define MCPWM_TZ1_OST_INT_RAW_M  (MCPWM_TZ1_OST_INT_RAW_V << MCPWM_TZ1_OST_INT_RAW_S)
+#define MCPWM_TZ1_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_RAW_S  25
+/** MCPWM_TZ2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+ *  mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_RAW    (BIT(26))
+#define MCPWM_TZ2_OST_INT_RAW_M  (MCPWM_TZ2_OST_INT_RAW_V << MCPWM_TZ2_OST_INT_RAW_S)
+#define MCPWM_TZ2_OST_INT_RAW_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_RAW_S  26
+/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP0.
+ */
+#define MCPWM_CAP0_INT_RAW    (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
+#define MCPWM_CAP0_INT_RAW_V  0x00000001U
+#define MCPWM_CAP0_INT_RAW_S  27
+/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP1.
+ */
+#define MCPWM_CAP1_INT_RAW    (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
+#define MCPWM_CAP1_INT_RAW_V  0x00000001U
+#define MCPWM_CAP1_INT_RAW_S  28
+/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+ *  CAP2.
+ */
+#define MCPWM_CAP2_INT_RAW    (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
+#define MCPWM_CAP2_INT_RAW_V  0x00000001U
+#define MCPWM_CAP2_INT_RAW_S  29
+
+/** MCPWM_INT_ST_REG register
+ *  Interrupt masked status register
+ */
+#define MCPWM_INT_ST_REG(i) (REG_MCPWM_BASE(i) + 0x118)
+/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+ *  timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_ST    (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
+#define MCPWM_FAULT0_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_INT_ST_S  9
+/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_ST    (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
+#define MCPWM_FAULT1_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_INT_ST_S  10
+/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_ST    (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
+#define MCPWM_FAULT2_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_INT_ST_S  11
+/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered when
+ *  event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/** MCPWM_CMPR0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_ST    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_ST_M  (MCPWM_CMPR0_TEA_INT_ST_V << MCPWM_CMPR0_TEA_INT_ST_S)
+#define MCPWM_CMPR0_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_ST_S  15
+/** MCPWM_CMPR1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_ST    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_ST_M  (MCPWM_CMPR1_TEA_INT_ST_V << MCPWM_CMPR1_TEA_INT_ST_S)
+#define MCPWM_CMPR1_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_ST_S  16
+/** MCPWM_CMPR2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_ST    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_ST_M  (MCPWM_CMPR2_TEA_INT_ST_V << MCPWM_CMPR2_TEA_INT_ST_S)
+#define MCPWM_CMPR2_TEA_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_ST_S  17
+/** MCPWM_CMPR0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_ST    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_ST_M  (MCPWM_CMPR0_TEB_INT_ST_V << MCPWM_CMPR0_TEB_INT_ST_S)
+#define MCPWM_CMPR0_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_ST_S  18
+/** MCPWM_CMPR1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_ST    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_ST_M  (MCPWM_CMPR1_TEB_INT_ST_V << MCPWM_CMPR1_TEB_INT_ST_S)
+#define MCPWM_CMPR1_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_ST_S  19
+/** MCPWM_CMPR2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+ *  operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_ST    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_ST_M  (MCPWM_CMPR2_TEB_INT_ST_V << MCPWM_CMPR2_TEB_INT_ST_S)
+#define MCPWM_CMPR2_TEB_INT_ST_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_ST_S  20
+/** MCPWM_TZ0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_ST    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_ST_M  (MCPWM_TZ0_CBC_INT_ST_V << MCPWM_TZ0_CBC_INT_ST_S)
+#define MCPWM_TZ0_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_ST_S  21
+/** MCPWM_TZ1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_ST    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_ST_M  (MCPWM_TZ1_CBC_INT_ST_V << MCPWM_TZ1_CBC_INT_ST_S)
+#define MCPWM_TZ1_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_ST_S  22
+/** MCPWM_TZ2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_ST    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_ST_M  (MCPWM_TZ2_CBC_INT_ST_V << MCPWM_TZ2_CBC_INT_ST_S)
+#define MCPWM_TZ2_CBC_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_ST_S  23
+/** MCPWM_TZ0_OST_INT_ST : RO; bitpos: [24]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_ST    (BIT(24))
+#define MCPWM_TZ0_OST_INT_ST_M  (MCPWM_TZ0_OST_INT_ST_V << MCPWM_TZ0_OST_INT_ST_S)
+#define MCPWM_TZ0_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_ST_S  24
+/** MCPWM_TZ1_OST_INT_ST : RO; bitpos: [25]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_ST    (BIT(25))
+#define MCPWM_TZ1_OST_INT_ST_M  (MCPWM_TZ1_OST_INT_ST_V << MCPWM_TZ1_OST_INT_ST_S)
+#define MCPWM_TZ1_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_ST_S  25
+/** MCPWM_TZ2_OST_INT_ST : RO; bitpos: [26]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+ *  one-shot mode action on PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_ST    (BIT(26))
+#define MCPWM_TZ2_OST_INT_ST_M  (MCPWM_TZ2_OST_INT_ST_V << MCPWM_TZ2_OST_INT_ST_S)
+#define MCPWM_TZ2_OST_INT_ST_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_ST_S  26
+/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_ST    (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
+#define MCPWM_CAP0_INT_ST_V  0x00000001U
+#define MCPWM_CAP0_INT_ST_S  27
+/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_ST    (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
+#define MCPWM_CAP1_INT_ST_V  0x00000001U
+#define MCPWM_CAP1_INT_ST_S  28
+/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
+ *  Masked status bit: The masked interrupt status of the interrupt triggered by
+ *  capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_ST    (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
+#define MCPWM_CAP2_INT_ST_V  0x00000001U
+#define MCPWM_CAP2_INT_ST_S  29
+
+/** MCPWM_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define MCPWM_INT_CLR_REG(i) (REG_MCPWM_BASE(i) + 0x11c)
+/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
+ */
+#define MCPWM_FAULT0_INT_CLR    (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
+#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_INT_CLR_S  9
+/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
+ */
+#define MCPWM_FAULT1_INT_CLR    (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
+#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_INT_CLR_S  10
+/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
+ */
+#define MCPWM_FAULT2_INT_CLR    (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
+#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_INT_CLR_S  11
+/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
+ */
+#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
+ */
+#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
+ */
+#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/** MCPWM_CMPR0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_CMPR0_TEA_INT_CLR    (BIT(15))
+#define MCPWM_CMPR0_TEA_INT_CLR_M  (MCPWM_CMPR0_TEA_INT_CLR_V << MCPWM_CMPR0_TEA_INT_CLR_S)
+#define MCPWM_CMPR0_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEA_INT_CLR_S  15
+/** MCPWM_CMPR1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_CMPR1_TEA_INT_CLR    (BIT(16))
+#define MCPWM_CMPR1_TEA_INT_CLR_M  (MCPWM_CMPR1_TEA_INT_CLR_V << MCPWM_CMPR1_TEA_INT_CLR_S)
+#define MCPWM_CMPR1_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEA_INT_CLR_S  16
+/** MCPWM_CMPR2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_CMPR2_TEA_INT_CLR    (BIT(17))
+#define MCPWM_CMPR2_TEA_INT_CLR_M  (MCPWM_CMPR2_TEA_INT_CLR_V << MCPWM_CMPR2_TEA_INT_CLR_S)
+#define MCPWM_CMPR2_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEA_INT_CLR_S  17
+/** MCPWM_CMPR0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_CMPR0_TEB_INT_CLR    (BIT(18))
+#define MCPWM_CMPR0_TEB_INT_CLR_M  (MCPWM_CMPR0_TEB_INT_CLR_V << MCPWM_CMPR0_TEB_INT_CLR_S)
+#define MCPWM_CMPR0_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR0_TEB_INT_CLR_S  18
+/** MCPWM_CMPR1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_CMPR1_TEB_INT_CLR    (BIT(19))
+#define MCPWM_CMPR1_TEB_INT_CLR_M  (MCPWM_CMPR1_TEB_INT_CLR_V << MCPWM_CMPR1_TEB_INT_CLR_S)
+#define MCPWM_CMPR1_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR1_TEB_INT_CLR_S  19
+/** MCPWM_CMPR2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_CMPR2_TEB_INT_CLR    (BIT(20))
+#define MCPWM_CMPR2_TEB_INT_CLR_M  (MCPWM_CMPR2_TEB_INT_CLR_V << MCPWM_CMPR2_TEB_INT_CLR_S)
+#define MCPWM_CMPR2_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_CMPR2_TEB_INT_CLR_S  20
+/** MCPWM_TZ0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM0.
+ */
+#define MCPWM_TZ0_CBC_INT_CLR    (BIT(21))
+#define MCPWM_TZ0_CBC_INT_CLR_M  (MCPWM_TZ0_CBC_INT_CLR_V << MCPWM_TZ0_CBC_INT_CLR_S)
+#define MCPWM_TZ0_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_CBC_INT_CLR_S  21
+/** MCPWM_TZ1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM1.
+ */
+#define MCPWM_TZ1_CBC_INT_CLR    (BIT(22))
+#define MCPWM_TZ1_CBC_INT_CLR_M  (MCPWM_TZ1_CBC_INT_CLR_V << MCPWM_TZ1_CBC_INT_CLR_S)
+#define MCPWM_TZ1_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_CBC_INT_CLR_S  22
+/** MCPWM_TZ2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM2.
+ */
+#define MCPWM_TZ2_CBC_INT_CLR    (BIT(23))
+#define MCPWM_TZ2_CBC_INT_CLR_M  (MCPWM_TZ2_CBC_INT_CLR_V << MCPWM_TZ2_CBC_INT_CLR_S)
+#define MCPWM_TZ2_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_CBC_INT_CLR_S  23
+/** MCPWM_TZ0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM0.
+ */
+#define MCPWM_TZ0_OST_INT_CLR    (BIT(24))
+#define MCPWM_TZ0_OST_INT_CLR_M  (MCPWM_TZ0_OST_INT_CLR_V << MCPWM_TZ0_OST_INT_CLR_S)
+#define MCPWM_TZ0_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ0_OST_INT_CLR_S  24
+/** MCPWM_TZ1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM1.
+ */
+#define MCPWM_TZ1_OST_INT_CLR    (BIT(25))
+#define MCPWM_TZ1_OST_INT_CLR_M  (MCPWM_TZ1_OST_INT_CLR_V << MCPWM_TZ1_OST_INT_CLR_S)
+#define MCPWM_TZ1_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ1_OST_INT_CLR_S  25
+/** MCPWM_TZ2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+ *  PWM2.
+ */
+#define MCPWM_TZ2_OST_INT_CLR    (BIT(26))
+#define MCPWM_TZ2_OST_INT_CLR_M  (MCPWM_TZ2_OST_INT_CLR_V << MCPWM_TZ2_OST_INT_CLR_S)
+#define MCPWM_TZ2_OST_INT_CLR_V  0x00000001U
+#define MCPWM_TZ2_OST_INT_CLR_S  26
+/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
+ */
+#define MCPWM_CAP0_INT_CLR    (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
+#define MCPWM_CAP0_INT_CLR_V  0x00000001U
+#define MCPWM_CAP0_INT_CLR_S  27
+/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
+ */
+#define MCPWM_CAP1_INT_CLR    (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
+#define MCPWM_CAP1_INT_CLR_V  0x00000001U
+#define MCPWM_CAP1_INT_CLR_S  28
+/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
+ */
+#define MCPWM_CAP2_INT_CLR    (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
+#define MCPWM_CAP2_INT_CLR_V  0x00000001U
+#define MCPWM_CAP2_INT_CLR_S  29
+
+/** MCPWM_EVT_EN_REG register
+ *  Event enable register
+ */
+#define MCPWM_EVT_EN_REG(i) (REG_MCPWM_BASE(i) + 0x120)
+/** MCPWM_EVT_TIMER0_STOP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TIMER0_STOP_EN    (BIT(0))
+#define MCPWM_EVT_TIMER0_STOP_EN_M  (MCPWM_EVT_TIMER0_STOP_EN_V << MCPWM_EVT_TIMER0_STOP_EN_S)
+#define MCPWM_EVT_TIMER0_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_STOP_EN_S  0
+/** MCPWM_EVT_TIMER1_STOP_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TIMER1_STOP_EN    (BIT(1))
+#define MCPWM_EVT_TIMER1_STOP_EN_M  (MCPWM_EVT_TIMER1_STOP_EN_V << MCPWM_EVT_TIMER1_STOP_EN_S)
+#define MCPWM_EVT_TIMER1_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_STOP_EN_S  1
+/** MCPWM_EVT_TIMER2_STOP_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TIMER2_STOP_EN    (BIT(2))
+#define MCPWM_EVT_TIMER2_STOP_EN_M  (MCPWM_EVT_TIMER2_STOP_EN_V << MCPWM_EVT_TIMER2_STOP_EN_S)
+#define MCPWM_EVT_TIMER2_STOP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_STOP_EN_S  2
+/** MCPWM_EVT_TIMER0_TEZ_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable timer0 equal zero event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER0_TEZ_EN    (BIT(3))
+#define MCPWM_EVT_TIMER0_TEZ_EN_M  (MCPWM_EVT_TIMER0_TEZ_EN_V << MCPWM_EVT_TIMER0_TEZ_EN_S)
+#define MCPWM_EVT_TIMER0_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEZ_EN_S  3
+/** MCPWM_EVT_TIMER1_TEZ_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable timer1 equal zero event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER1_TEZ_EN    (BIT(4))
+#define MCPWM_EVT_TIMER1_TEZ_EN_M  (MCPWM_EVT_TIMER1_TEZ_EN_V << MCPWM_EVT_TIMER1_TEZ_EN_S)
+#define MCPWM_EVT_TIMER1_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEZ_EN_S  4
+/** MCPWM_EVT_TIMER2_TEZ_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable timer2 equal zero event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER2_TEZ_EN    (BIT(5))
+#define MCPWM_EVT_TIMER2_TEZ_EN_M  (MCPWM_EVT_TIMER2_TEZ_EN_V << MCPWM_EVT_TIMER2_TEZ_EN_S)
+#define MCPWM_EVT_TIMER2_TEZ_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEZ_EN_S  5
+/** MCPWM_EVT_TIMER0_TEP_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable timer0 equal period event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER0_TEP_EN    (BIT(6))
+#define MCPWM_EVT_TIMER0_TEP_EN_M  (MCPWM_EVT_TIMER0_TEP_EN_V << MCPWM_EVT_TIMER0_TEP_EN_S)
+#define MCPWM_EVT_TIMER0_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER0_TEP_EN_S  6
+/** MCPWM_EVT_TIMER1_TEP_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable timer1 equal period event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER1_TEP_EN    (BIT(7))
+#define MCPWM_EVT_TIMER1_TEP_EN_M  (MCPWM_EVT_TIMER1_TEP_EN_V << MCPWM_EVT_TIMER1_TEP_EN_S)
+#define MCPWM_EVT_TIMER1_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER1_TEP_EN_S  7
+/** MCPWM_EVT_TIMER2_TEP_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable timer2 equal period event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TIMER2_TEP_EN    (BIT(8))
+#define MCPWM_EVT_TIMER2_TEP_EN_M  (MCPWM_EVT_TIMER2_TEP_EN_V << MCPWM_EVT_TIMER2_TEP_EN_S)
+#define MCPWM_EVT_TIMER2_TEP_EN_V  0x00000001U
+#define MCPWM_EVT_TIMER2_TEP_EN_S  8
+/** MCPWM_EVT_OP0_TEA_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal a event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP0_TEA_EN    (BIT(9))
+#define MCPWM_EVT_OP0_TEA_EN_M  (MCPWM_EVT_OP0_TEA_EN_V << MCPWM_EVT_OP0_TEA_EN_S)
+#define MCPWM_EVT_OP0_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEA_EN_S  9
+/** MCPWM_EVT_OP1_TEA_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal a event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP1_TEA_EN    (BIT(10))
+#define MCPWM_EVT_OP1_TEA_EN_M  (MCPWM_EVT_OP1_TEA_EN_V << MCPWM_EVT_OP1_TEA_EN_S)
+#define MCPWM_EVT_OP1_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEA_EN_S  10
+/** MCPWM_EVT_OP2_TEA_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal a event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP2_TEA_EN    (BIT(11))
+#define MCPWM_EVT_OP2_TEA_EN_M  (MCPWM_EVT_OP2_TEA_EN_V << MCPWM_EVT_OP2_TEA_EN_S)
+#define MCPWM_EVT_OP2_TEA_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEA_EN_S  11
+/** MCPWM_EVT_OP0_TEB_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal b event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP0_TEB_EN    (BIT(12))
+#define MCPWM_EVT_OP0_TEB_EN_M  (MCPWM_EVT_OP0_TEB_EN_V << MCPWM_EVT_OP0_TEB_EN_S)
+#define MCPWM_EVT_OP0_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEB_EN_S  12
+/** MCPWM_EVT_OP1_TEB_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal b event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP1_TEB_EN    (BIT(13))
+#define MCPWM_EVT_OP1_TEB_EN_M  (MCPWM_EVT_OP1_TEB_EN_V << MCPWM_EVT_OP1_TEB_EN_S)
+#define MCPWM_EVT_OP1_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEB_EN_S  13
+/** MCPWM_EVT_OP2_TEB_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal b event
+ *  generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP2_TEB_EN    (BIT(14))
+#define MCPWM_EVT_OP2_TEB_EN_M  (MCPWM_EVT_OP2_TEB_EN_V << MCPWM_EVT_OP2_TEB_EN_S)
+#define MCPWM_EVT_OP2_TEB_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEB_EN_S  14
+/** MCPWM_EVT_F0_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_F0_EN    (BIT(15))
+#define MCPWM_EVT_F0_EN_M  (MCPWM_EVT_F0_EN_V << MCPWM_EVT_F0_EN_S)
+#define MCPWM_EVT_F0_EN_V  0x00000001U
+#define MCPWM_EVT_F0_EN_S  15
+/** MCPWM_EVT_F1_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_F1_EN    (BIT(16))
+#define MCPWM_EVT_F1_EN_M  (MCPWM_EVT_F1_EN_V << MCPWM_EVT_F1_EN_S)
+#define MCPWM_EVT_F1_EN_V  0x00000001U
+#define MCPWM_EVT_F1_EN_S  16
+/** MCPWM_EVT_F2_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_F2_EN    (BIT(17))
+#define MCPWM_EVT_F2_EN_M  (MCPWM_EVT_F2_EN_V << MCPWM_EVT_F2_EN_S)
+#define MCPWM_EVT_F2_EN_V  0x00000001U
+#define MCPWM_EVT_F2_EN_S  17
+/** MCPWM_EVT_F0_CLR_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_F0_CLR_EN    (BIT(18))
+#define MCPWM_EVT_F0_CLR_EN_M  (MCPWM_EVT_F0_CLR_EN_V << MCPWM_EVT_F0_CLR_EN_S)
+#define MCPWM_EVT_F0_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F0_CLR_EN_S  18
+/** MCPWM_EVT_F1_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_F1_CLR_EN    (BIT(19))
+#define MCPWM_EVT_F1_CLR_EN_M  (MCPWM_EVT_F1_CLR_EN_V << MCPWM_EVT_F1_CLR_EN_S)
+#define MCPWM_EVT_F1_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F1_CLR_EN_S  19
+/** MCPWM_EVT_F2_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_F2_CLR_EN    (BIT(20))
+#define MCPWM_EVT_F2_CLR_EN_M  (MCPWM_EVT_F2_CLR_EN_V << MCPWM_EVT_F2_CLR_EN_S)
+#define MCPWM_EVT_F2_CLR_EN_V  0x00000001U
+#define MCPWM_EVT_F2_CLR_EN_S  20
+/** MCPWM_EVT_TZ0_CBC_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TZ0_CBC_EN    (BIT(21))
+#define MCPWM_EVT_TZ0_CBC_EN_M  (MCPWM_EVT_TZ0_CBC_EN_V << MCPWM_EVT_TZ0_CBC_EN_S)
+#define MCPWM_EVT_TZ0_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_CBC_EN_S  21
+/** MCPWM_EVT_TZ1_CBC_EN : R/W; bitpos: [22]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TZ1_CBC_EN    (BIT(22))
+#define MCPWM_EVT_TZ1_CBC_EN_M  (MCPWM_EVT_TZ1_CBC_EN_V << MCPWM_EVT_TZ1_CBC_EN_S)
+#define MCPWM_EVT_TZ1_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_CBC_EN_S  22
+/** MCPWM_EVT_TZ2_CBC_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_EVT_TZ2_CBC_EN    (BIT(23))
+#define MCPWM_EVT_TZ2_CBC_EN_M  (MCPWM_EVT_TZ2_CBC_EN_V << MCPWM_EVT_TZ2_CBC_EN_S)
+#define MCPWM_EVT_TZ2_CBC_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_CBC_EN_S  23
+/** MCPWM_EVT_TZ0_OST_EN : R/W; bitpos: [24]; default: 0;
+ *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TZ0_OST_EN    (BIT(24))
+#define MCPWM_EVT_TZ0_OST_EN_M  (MCPWM_EVT_TZ0_OST_EN_V << MCPWM_EVT_TZ0_OST_EN_S)
+#define MCPWM_EVT_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ0_OST_EN_S  24
+/** MCPWM_EVT_TZ1_OST_EN : R/W; bitpos: [25]; default: 0;
+ *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TZ1_OST_EN    (BIT(25))
+#define MCPWM_EVT_TZ1_OST_EN_M  (MCPWM_EVT_TZ1_OST_EN_V << MCPWM_EVT_TZ1_OST_EN_S)
+#define MCPWM_EVT_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ1_OST_EN_S  25
+/** MCPWM_EVT_TZ2_OST_EN : R/W; bitpos: [26]; default: 0;
+ *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_EVT_TZ2_OST_EN    (BIT(26))
+#define MCPWM_EVT_TZ2_OST_EN_M  (MCPWM_EVT_TZ2_OST_EN_V << MCPWM_EVT_TZ2_OST_EN_S)
+#define MCPWM_EVT_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_EVT_TZ2_OST_EN_S  26
+/** MCPWM_EVT_CAP0_EN : R/W; bitpos: [27]; default: 0;
+ *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_CAP0_EN    (BIT(27))
+#define MCPWM_EVT_CAP0_EN_M  (MCPWM_EVT_CAP0_EN_V << MCPWM_EVT_CAP0_EN_S)
+#define MCPWM_EVT_CAP0_EN_V  0x00000001U
+#define MCPWM_EVT_CAP0_EN_S  27
+/** MCPWM_EVT_CAP1_EN : R/W; bitpos: [28]; default: 0;
+ *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_CAP1_EN    (BIT(28))
+#define MCPWM_EVT_CAP1_EN_M  (MCPWM_EVT_CAP1_EN_V << MCPWM_EVT_CAP1_EN_S)
+#define MCPWM_EVT_CAP1_EN_V  0x00000001U
+#define MCPWM_EVT_CAP1_EN_S  28
+/** MCPWM_EVT_CAP2_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_CAP2_EN    (BIT(29))
+#define MCPWM_EVT_CAP2_EN_M  (MCPWM_EVT_CAP2_EN_V << MCPWM_EVT_CAP2_EN_S)
+#define MCPWM_EVT_CAP2_EN_V  0x00000001U
+#define MCPWM_EVT_CAP2_EN_S  29
+
+/** MCPWM_TASK_EN_REG register
+ *  Task enable register
+ */
+#define MCPWM_TASK_EN_REG(i) (REG_MCPWM_BASE(i) + 0x124)
+/** MCPWM_TASK_CMPR0_A_UP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR0_A_UP_EN    (BIT(0))
+#define MCPWM_TASK_CMPR0_A_UP_EN_M  (MCPWM_TASK_CMPR0_A_UP_EN_V << MCPWM_TASK_CMPR0_A_UP_EN_S)
+#define MCPWM_TASK_CMPR0_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_A_UP_EN_S  0
+/** MCPWM_TASK_CMPR1_A_UP_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR1_A_UP_EN    (BIT(1))
+#define MCPWM_TASK_CMPR1_A_UP_EN_M  (MCPWM_TASK_CMPR1_A_UP_EN_V << MCPWM_TASK_CMPR1_A_UP_EN_S)
+#define MCPWM_TASK_CMPR1_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_A_UP_EN_S  1
+/** MCPWM_TASK_CMPR2_A_UP_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR2_A_UP_EN    (BIT(2))
+#define MCPWM_TASK_CMPR2_A_UP_EN_M  (MCPWM_TASK_CMPR2_A_UP_EN_V << MCPWM_TASK_CMPR2_A_UP_EN_S)
+#define MCPWM_TASK_CMPR2_A_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_A_UP_EN_S  2
+/** MCPWM_TASK_CMPR0_B_UP_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR0_B_UP_EN    (BIT(3))
+#define MCPWM_TASK_CMPR0_B_UP_EN_M  (MCPWM_TASK_CMPR0_B_UP_EN_V << MCPWM_TASK_CMPR0_B_UP_EN_S)
+#define MCPWM_TASK_CMPR0_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR0_B_UP_EN_S  3
+/** MCPWM_TASK_CMPR1_B_UP_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR1_B_UP_EN    (BIT(4))
+#define MCPWM_TASK_CMPR1_B_UP_EN_M  (MCPWM_TASK_CMPR1_B_UP_EN_V << MCPWM_TASK_CMPR1_B_UP_EN_S)
+#define MCPWM_TASK_CMPR1_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR1_B_UP_EN_S  4
+/** MCPWM_TASK_CMPR2_B_UP_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
+ *  update task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CMPR2_B_UP_EN    (BIT(5))
+#define MCPWM_TASK_CMPR2_B_UP_EN_M  (MCPWM_TASK_CMPR2_B_UP_EN_V << MCPWM_TASK_CMPR2_B_UP_EN_S)
+#define MCPWM_TASK_CMPR2_B_UP_EN_V  0x00000001U
+#define MCPWM_TASK_CMPR2_B_UP_EN_S  5
+/** MCPWM_TASK_GEN_STOP_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable all PWM generate stop task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_GEN_STOP_EN    (BIT(6))
+#define MCPWM_TASK_GEN_STOP_EN_M  (MCPWM_TASK_GEN_STOP_EN_V << MCPWM_TASK_GEN_STOP_EN_S)
+#define MCPWM_TASK_GEN_STOP_EN_V  0x00000001U
+#define MCPWM_TASK_GEN_STOP_EN_S  6
+/** MCPWM_TASK_TIMER0_SYNC_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER0_SYNC_EN    (BIT(7))
+#define MCPWM_TASK_TIMER0_SYNC_EN_M  (MCPWM_TASK_TIMER0_SYNC_EN_V << MCPWM_TASK_TIMER0_SYNC_EN_S)
+#define MCPWM_TASK_TIMER0_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_SYNC_EN_S  7
+/** MCPWM_TASK_TIMER1_SYNC_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER1_SYNC_EN    (BIT(8))
+#define MCPWM_TASK_TIMER1_SYNC_EN_M  (MCPWM_TASK_TIMER1_SYNC_EN_V << MCPWM_TASK_TIMER1_SYNC_EN_S)
+#define MCPWM_TASK_TIMER1_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_SYNC_EN_S  8
+/** MCPWM_TASK_TIMER2_SYNC_EN : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER2_SYNC_EN    (BIT(9))
+#define MCPWM_TASK_TIMER2_SYNC_EN_M  (MCPWM_TASK_TIMER2_SYNC_EN_V << MCPWM_TASK_TIMER2_SYNC_EN_S)
+#define MCPWM_TASK_TIMER2_SYNC_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_SYNC_EN_S  9
+/** MCPWM_TASK_TIMER0_PERIOD_UP_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable timer0 period update task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN    (BIT(10))
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER0_PERIOD_UP_EN_V << MCPWM_TASK_TIMER0_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER0_PERIOD_UP_EN_S  10
+/** MCPWM_TASK_TIMER1_PERIOD_UP_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable timer1 period update task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN    (BIT(11))
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER1_PERIOD_UP_EN_V << MCPWM_TASK_TIMER1_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER1_PERIOD_UP_EN_S  11
+/** MCPWM_TASK_TIMER2_PERIOD_UP_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to enable timer2 period update task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN    (BIT(12))
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_M  (MCPWM_TASK_TIMER2_PERIOD_UP_EN_V << MCPWM_TASK_TIMER2_PERIOD_UP_EN_S)
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_V  0x00000001U
+#define MCPWM_TASK_TIMER2_PERIOD_UP_EN_S  12
+/** MCPWM_TASK_TZ0_OST_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_TASK_TZ0_OST_EN    (BIT(13))
+#define MCPWM_TASK_TZ0_OST_EN_M  (MCPWM_TASK_TZ0_OST_EN_V << MCPWM_TASK_TZ0_OST_EN_S)
+#define MCPWM_TASK_TZ0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ0_OST_EN_S  13
+/** MCPWM_TASK_TZ1_OST_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_TASK_TZ1_OST_EN    (BIT(14))
+#define MCPWM_TASK_TZ1_OST_EN_M  (MCPWM_TASK_TZ1_OST_EN_V << MCPWM_TASK_TZ1_OST_EN_S)
+#define MCPWM_TASK_TZ1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ1_OST_EN_S  14
+/** MCPWM_TASK_TZ2_OST_EN : R/W; bitpos: [15]; default: 0;
+ *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
+ *  Enable
+ */
+#define MCPWM_TASK_TZ2_OST_EN    (BIT(15))
+#define MCPWM_TASK_TZ2_OST_EN_M  (MCPWM_TASK_TZ2_OST_EN_V << MCPWM_TASK_TZ2_OST_EN_S)
+#define MCPWM_TASK_TZ2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_TZ2_OST_EN_S  15
+/** MCPWM_TASK_CLR0_OST_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_CLR0_OST_EN    (BIT(16))
+#define MCPWM_TASK_CLR0_OST_EN_M  (MCPWM_TASK_CLR0_OST_EN_V << MCPWM_TASK_CLR0_OST_EN_S)
+#define MCPWM_TASK_CLR0_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR0_OST_EN_S  16
+/** MCPWM_TASK_CLR1_OST_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_CLR1_OST_EN    (BIT(17))
+#define MCPWM_TASK_CLR1_OST_EN_M  (MCPWM_TASK_CLR1_OST_EN_V << MCPWM_TASK_CLR1_OST_EN_S)
+#define MCPWM_TASK_CLR1_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR1_OST_EN_S  17
+/** MCPWM_TASK_CLR2_OST_EN : R/W; bitpos: [18]; default: 0;
+ *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
+ *  Disable\\1: Enable
+ */
+#define MCPWM_TASK_CLR2_OST_EN    (BIT(18))
+#define MCPWM_TASK_CLR2_OST_EN_M  (MCPWM_TASK_CLR2_OST_EN_V << MCPWM_TASK_CLR2_OST_EN_S)
+#define MCPWM_TASK_CLR2_OST_EN_V  0x00000001U
+#define MCPWM_TASK_CLR2_OST_EN_S  18
+/** MCPWM_TASK_CAP0_EN : R/W; bitpos: [19]; default: 0;
+ *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CAP0_EN    (BIT(19))
+#define MCPWM_TASK_CAP0_EN_M  (MCPWM_TASK_CAP0_EN_V << MCPWM_TASK_CAP0_EN_S)
+#define MCPWM_TASK_CAP0_EN_V  0x00000001U
+#define MCPWM_TASK_CAP0_EN_S  19
+/** MCPWM_TASK_CAP1_EN : R/W; bitpos: [20]; default: 0;
+ *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CAP1_EN    (BIT(20))
+#define MCPWM_TASK_CAP1_EN_M  (MCPWM_TASK_CAP1_EN_V << MCPWM_TASK_CAP1_EN_S)
+#define MCPWM_TASK_CAP1_EN_V  0x00000001U
+#define MCPWM_TASK_CAP1_EN_S  20
+/** MCPWM_TASK_CAP2_EN : R/W; bitpos: [21]; default: 0;
+ *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
+ */
+#define MCPWM_TASK_CAP2_EN    (BIT(21))
+#define MCPWM_TASK_CAP2_EN_M  (MCPWM_TASK_CAP2_EN_V << MCPWM_TASK_CAP2_EN_S)
+#define MCPWM_TASK_CAP2_EN_V  0x00000001U
+#define MCPWM_TASK_CAP2_EN_S  21
+
+/** MCPWM_EVT_EN2_REG register
+ *  Event enable register2
+ */
+#define MCPWM_EVT_EN2_REG(i) (REG_MCPWM_BASE(i) + 0x128)
+/** MCPWM_EVT_OP0_TEE1_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP0_TEE1_EN    (BIT(0))
+#define MCPWM_EVT_OP0_TEE1_EN_M  (MCPWM_EVT_OP0_TEE1_EN_V << MCPWM_EVT_OP0_TEE1_EN_S)
+#define MCPWM_EVT_OP0_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEE1_EN_S  0
+/** MCPWM_EVT_OP1_TEE1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP1_TEE1_EN    (BIT(1))
+#define MCPWM_EVT_OP1_TEE1_EN_M  (MCPWM_EVT_OP1_TEE1_EN_V << MCPWM_EVT_OP1_TEE1_EN_S)
+#define MCPWM_EVT_OP1_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEE1_EN_S  1
+/** MCPWM_EVT_OP2_TEE1_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP2_TEE1_EN    (BIT(2))
+#define MCPWM_EVT_OP2_TEE1_EN_M  (MCPWM_EVT_OP2_TEE1_EN_V << MCPWM_EVT_OP2_TEE1_EN_S)
+#define MCPWM_EVT_OP2_TEE1_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEE1_EN_S  2
+/** MCPWM_EVT_OP0_TEE2_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP0_TEE2_EN    (BIT(3))
+#define MCPWM_EVT_OP0_TEE2_EN_M  (MCPWM_EVT_OP0_TEE2_EN_V << MCPWM_EVT_OP0_TEE2_EN_S)
+#define MCPWM_EVT_OP0_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP0_TEE2_EN_S  3
+/** MCPWM_EVT_OP1_TEE2_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP1_TEE2_EN    (BIT(4))
+#define MCPWM_EVT_OP1_TEE2_EN_M  (MCPWM_EVT_OP1_TEE2_EN_V << MCPWM_EVT_OP1_TEE2_EN_S)
+#define MCPWM_EVT_OP1_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP1_TEE2_EN_S  4
+/** MCPWM_EVT_OP2_TEE2_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
+ *  event generate.\\0: Disable\\1: Enable
+ */
+#define MCPWM_EVT_OP2_TEE2_EN    (BIT(5))
+#define MCPWM_EVT_OP2_TEE2_EN_M  (MCPWM_EVT_OP2_TEE2_EN_V << MCPWM_EVT_OP2_TEE2_EN_S)
+#define MCPWM_EVT_OP2_TEE2_EN_V  0x00000001U
+#define MCPWM_EVT_OP2_TEE2_EN_S  5
+
+/** MCPWM_OP0_TSTMP_E1_REG register
+ *  Generator0 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x12c)
+/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator0 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
+#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_S  0
+
+/** MCPWM_OP0_TSTMP_E2_REG register
+ *  Generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP0_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x130)
+/** MCPWM_OP0_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP0_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E2_M  (MCPWM_OP0_TSTMP_E2_V << MCPWM_OP0_TSTMP_E2_S)
+#define MCPWM_OP0_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E2_S  0
+
+/** MCPWM_OP1_TSTMP_E1_REG register
+ *  Generator1 timer stamp E1 value register
+ */
+#define MCPWM_OP1_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x134)
+/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator1 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
+#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_S  0
+
+/** MCPWM_OP1_TSTMP_E2_REG register
+ *  Generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP1_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x138)
+/** MCPWM_OP1_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP1_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP1_TSTMP_E2_M  (MCPWM_OP1_TSTMP_E2_V << MCPWM_OP1_TSTMP_E2_S)
+#define MCPWM_OP1_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP1_TSTMP_E2_S  0
+
+/** MCPWM_OP2_TSTMP_E1_REG register
+ *  Generator2 timer stamp E1 value register
+ */
+#define MCPWM_OP2_TSTMP_E1_REG(i) (REG_MCPWM_BASE(i) + 0x13c)
+/** MCPWM_OP0_TSTMP_E1 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator2 timer stamp E1 value register
+ */
+#define MCPWM_OP0_TSTMP_E1    0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_M  (MCPWM_OP0_TSTMP_E1_V << MCPWM_OP0_TSTMP_E1_S)
+#define MCPWM_OP0_TSTMP_E1_V  0x0000FFFFU
+#define MCPWM_OP0_TSTMP_E1_S  0
+
+/** MCPWM_OP2_TSTMP_E2_REG register
+ *  Generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP2_TSTMP_E2_REG(i) (REG_MCPWM_BASE(i) + 0x140)
+/** MCPWM_OP2_TSTMP_E2 : R/W; bitpos: [15:0]; default: 0;
+ *  Configures generator$n timer stamp E2 value register
+ */
+#define MCPWM_OP2_TSTMP_E2    0x0000FFFFU
+#define MCPWM_OP2_TSTMP_E2_M  (MCPWM_OP2_TSTMP_E2_V << MCPWM_OP2_TSTMP_E2_S)
+#define MCPWM_OP2_TSTMP_E2_V  0x0000FFFFU
+#define MCPWM_OP2_TSTMP_E2_S  0
+
+/** MCPWM_CLK_REG register
+ *  Global configuration register
+ */
+#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x144)
+/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
+ *  when application writes registers\\1: Force open the clock gate for register
+ */
+#define MCPWM_CLK_EN    (BIT(0))
+#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
+#define MCPWM_CLK_EN_V  0x00000001U
+#define MCPWM_CLK_EN_S  0
+
+/** MCPWM_VERSION_REG register
+ *  Version register.
+ */
+#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x148)
+/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 35725968;
+ *  Configures the version.
+ */
+#define MCPWM_DATE    0x0FFFFFFFU
+#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
+#define MCPWM_DATE_V  0x0FFFFFFFU
+#define MCPWM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/mcpwm_struct.h b/components/soc/esp32p4/register/soc/mcpwm_struct.h
new file mode 100644
index 00000000000..71a4864a9c3
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/mcpwm_struct.h
@@ -0,0 +1,1918 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_cfg */
+/** Type of clk_cfg register
+ *  PWM clock prescaler register.
+ */
+typedef union {
+    struct {
+        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns *
+         *  (PWM_CLK_PRESCALE + 1).
+         */
+        uint32_t clk_prescale:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_clk_cfg_reg_t;
+
+
+/** Group: timer */
+/** Type of timern_cfg0 register
+ *  PWM timern period and update method configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the prescaler value of timern, so that the period of PT0_clk = Period of
+         *  PWM_clk * (PWM_TIMERn_PRESCALE + 1)
+         */
+        uint32_t timer_prescale:8;
+        /** timer_period : R/W; bitpos: [23:8]; default: 255;
+         *  Configures the period shadow of PWM timern
+         */
+        uint32_t timer_period:16;
+        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
+         *  Configures the update method for active register of PWM timern period.\\0:
+         *  Immediate\\1: TEZ\\2: Sync\\3: TEZ or sync\\TEZ here and below means timer equal
+         *  zero event
+         */
+        uint32_t timer_period_upmethod:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg0_reg_t;
+
+/** Type of timer0_cfg1 register
+ *  PWM timer$n working mode and start/stop control register.
+ */
+typedef union {
+    struct {
+        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to start/stop PWM timer$n.\\0: If PWM timer$n starts,
+         *  then stops at TEZ\\1: If timer$n starts, then stops at TEP\\2: PWM timer$n starts
+         *  and runs on\\3: Timer$n starts and stops at the next TEZ\\4: Timer0 starts and
+         *  stops at the next TEP.\\TEP here and below means the event that happens when the
+         *  timer equals to period
+         */
+        uint32_t timer_start:3;
+        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the working mode of PWM timer$n.\\0: Freeze\\1: Increase mode\\2:
+         *  Decrease mode\\3: Up-down mode
+         */
+        uint32_t timer_mod:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg1_reg_t;
+
+/** Type of timer0_sync register
+ *  PWM timer$n sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer$n reloading with phase on sync input
+         *  event is enabled.\\0: Disable\\1: Enable
+         */
+        uint32_t timer_synci_en:1;
+        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of software sync. Toggling this bit will trigger a
+         *  software sync.
+         */
+        uint32_t timer_sync_sw:1;
+        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the selection of PWM timer$n sync_out.\\0: Sync_in\\1: TEZ\\2: TEP\\3:
+         *  Invalid, sync_out selects noting
+         */
+        uint32_t timer_synco_sel:2;
+        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
+         *  Configures the phase for timer$n reload on sync event.
+         */
+        uint32_t timer_phase:16;
+        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configures the PWM timer$n's direction when timer$n mode is up-down mode.\\0:
+         *  Increase\\1: Decrease
+         */
+        uint32_t timer_phase_direction:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} mcpwm_timer_sync_reg_t;
+
+/** Type of timer_status register
+ *  PWM timer$n status register.
+ */
+typedef union {
+    struct {
+        /** timer_value : RO; bitpos: [15:0]; default: 0;
+         *  Represents current PWM timer$n counter value.
+         */
+        uint32_t timer_value:16;
+        /** timer_direction : RO; bitpos: [16]; default: 0;
+         *  Represents current PWM timer$n counter direction.\\0: Increment\\1: Decrement
+         */
+        uint32_t timer_direction:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} mcpwm_timer_status_reg_t;
+
+
+/** Group: timer_synci_cfg */
+/** Type of timer_synci_cfg register
+ *  Synchronization input selection register for PWM timers.
+ */
+typedef union {
+    struct {
+        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the selection of sync input for PWM timer0.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer0_syncisel:3;
+        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
+         *  Configures the selection of sync input for PWM timer1.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer1_syncisel:3;
+        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures the selection of sync input for PWM timer2.\\1: PWM timer0 sync_out\\2:
+         *  PWM timer1 sync_out\\3: PWM timer2 sync_out\\4: SYNC0 from GPIO matrix\\5: SYNC1
+         *  from GPIO matrix\\6: SYNC2 from GPIO matrix\\Other values: No sync input selected
+         */
+        uint32_t timer2_syncisel:3;
+        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to invert SYNC0 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci0_invert:1;
+        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to invert SYNC1 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci1_invert:1;
+        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert SYNC2 from GPIO matrix.\\0: Not invert\\1:
+         *  Invert
+         */
+        uint32_t external_synci2_invert:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} mcpwm_timer_synci_cfg_reg_t;
+
+
+/** Group: operator_timersel */
+/** Type of operator_timersel register
+ *  PWM operator's timer select register
+ */
+typedef union {
+    struct {
+        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator0.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator0_timersel:2;
+        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator1.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator1_timersel:2;
+        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
+         *  Configures which PWM timer will be the timing reference for PWM operator2.\\0:
+         *  Timer0\\1: Timer1\\2: Timer2\\3: Invalid, will select timer2
+         */
+        uint32_t operator2_timersel:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_operator_timersel_reg_t;
+
+
+/** Group: operators */
+/** Type of genn_stmp_cfg register
+ *  Generatorn time stamp registers A and B transfer status and update method register
+ */
+typedef union {
+    struct {
+        /** cmpr_a_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the update method for PWM generator n time stamp A's active
+         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t cmpr_a_upmethod:4;
+        /** cmpr_b_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the update method for PWM generator n time stamp B's active
+         *  register.\\0: Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is
+         *  set to 1: Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t cmpr_b_upmethod:4;
+        /** cmpr_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
+         *  Represents whether or not generatorn time stamp A's shadow reg is transferred.\\0:
+         *  A's active reg has been updated with shadow register latest value.\\1: A's shadow
+         *  reg is filled and waiting to be transferred to A's active reg
+         */
+        uint32_t cmpr_a_shdw_full:1;
+        /** cmpr_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
+         *  Represents whether or not generatorn time stamp B's shadow reg is transferred.\\0:
+         *  B's active reg has been updated with shadow register latest value.\\1: B's shadow
+         *  reg is filled and waiting to be transferred to B's active reg
+         */
+        uint32_t cmpr_b_shdw_full:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_stmp_cfg_reg_t;
+
+/** Type of gen_tstmp_a register
+ *  Generator$n time stamp A's shadow register
+ */
+typedef union {
+    struct {
+        /** cmpr : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the value of PWM generator $n time stamp 's shadow register.
+         */
+        uint32_t cmpr:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_tstmp_reg_t;
+
+
+/** Type of gen_cfg0 register
+ *  Generator$n fault event T0 and T1 configuration register
+ */
+typedef union {
+    struct {
+        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures update method for PWM generator $n's active register.\\0:
+         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t gen_cfg_upmethod:4;
+        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
+         *  Configures source selection for PWM generator $n event_t0, take effect
+         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+         *  Invalid, Select nothing
+         */
+        uint32_t gen_t0_sel:3;
+        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
+         *  Configures source selection for PWM generator $n event_t1, take effect
+         *  immediately.\\0: fault_event0\\1: fault_event1\\2: fault_event2\\3: sync_taken\\4:
+         *  Invalid, Select nothing
+         */
+        uint32_t gen_t1_sel:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} mcpwm_gen_cfg0_reg_t;
+
+/** Type of gen_force register
+ *  Generator$n output signal force mode register.
+ */
+typedef union {
+    struct {
+        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
+         *  Configures update method for continuous software force of PWM generator$n.\\0:
+         *  Immediately\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  TEA\\Bit3 is set to 1: TEB\\Bit4 is set to 1: Sync\\Bit5 is set to 1: Disable
+         *  update. TEA/B here and below means an event generated when the timer's value equals
+         *  to that of register A/B.
+         */
+        uint32_t gen_cntuforce_upmethod:6;
+        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
+         *  Configures continuous software force mode for PWM$n A.\\0: Disabled\\1: Low\\2:
+         *  High\\3: Disabled
+         */
+        uint32_t gen_a_cntuforce_mode:2;
+        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
+         *  Configures continuous software force mode for PWM$n B.\\0: Disabled\\1: Low\\2:
+         *  High\\3: Disabled
+         */
+        uint32_t gen_b_cntuforce_mode:2;
+        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
+         *  Configures the generation of non-continuous immediate software-force event for
+         *  PWM$n A, a toggle will trigger a force event.
+         */
+        uint32_t gen_a_nciforce:1;
+        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
+         *  Configures non-continuous immediate software force mode for PWM$n A.\\0:
+         *  Disabled\\1: Low\\2: High\\3: Disabled
+         */
+        uint32_t gen_a_nciforce_mode:2;
+        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
+         *  Configures the generation of non-continuous immediate software-force event for
+         *  PWM$n B, a toggle will trigger a force event.
+         */
+        uint32_t gen_b_nciforce:1;
+        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
+         *  Configures non-continuous immediate software force mode for PWM$n B.\\0:
+         *  Disabled\\1: Low\\2: High\\3: Disabled
+         */
+        uint32_t gen_b_nciforce_mode:2;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_gen_force_reg_t;
+
+/** Type of gen register
+ *  PWM$n output signal A actions configuration register
+ */
+typedef union {
+    struct {
+        /** gen_a_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEZ when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_utez:2;
+        /** gen_a_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEP when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_utep:2;
+        /** gen_a_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEA when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_utea:2;
+        /** gen_a_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEB when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_uteb:2;
+        /** gen_a_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t0 when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_ut0:2;
+        /** gen_a_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t1 when timer increasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_ut1:2;
+        /** gen_a_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEZ when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dtez:2;
+        /** gen_a_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEP when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dtep:2;
+        /** gen_a_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEA when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dtea:2;
+        /** gen_a_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Configures action on PWM$n A triggered by event TEB when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dteb:2;
+        /** gen_a_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t0 when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dt0:2;
+        /** gen_a_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Configures action on PWM$n A triggered by event_t1 when timer decreasing.\\0: No
+         *  change\\1: Low\\2: High\\3: Toggle
+         */
+        uint32_t gen_dt1:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_gen_reg_t;
+
+/** Type of dt0_cfg register
+ *  Dead time configuration register
+ */
+typedef union {
+    struct {
+        /** db_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Configures update method for FED (Falling edge delay) active register.\\0:
+         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t db_fed_upmethod:4;
+        /** db_red_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Configures update method for RED (rising edge delay) active register.\\0:
+         *  Immediate\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP\\Bit2 is set to 1:
+         *  Sync\\Bit3 is set to 1: Disable the update
+         */
+        uint32_t db_red_upmethod:4;
+        /** db_deb_mode : R/W; bitpos: [8]; default: 0;
+         *  Configures S8 in table, dual-edge B mode.\\0: fed/red take effect on different path
+         *  separately\\1: fed/red take effect on B path, A out is in bypass or dulpB mode
+         */
+        uint32_t db_deb_mode:1;
+        /** db_a_outswap : R/W; bitpos: [9]; default: 0;
+         *  Configures S6 in table.
+         */
+        uint32_t db_a_outswap:1;
+        /** db_b_outswap : R/W; bitpos: [10]; default: 0;
+         *  Configures S7 in table.
+         */
+        uint32_t db_b_outswap:1;
+        /** db_red_insel : R/W; bitpos: [11]; default: 0;
+         *  Configures S4 in table.
+         */
+        uint32_t db_red_insel:1;
+        /** db_fed_insel : R/W; bitpos: [12]; default: 0;
+         *  Configures S5 in table.
+         */
+        uint32_t db_fed_insel:1;
+        /** db_red_outinvert : R/W; bitpos: [13]; default: 0;
+         *  Configures S2 in table.
+         */
+        uint32_t db_red_outinvert:1;
+        /** db_fed_outinvert : R/W; bitpos: [14]; default: 0;
+         *  Configures S3 in table.
+         */
+        uint32_t db_fed_outinvert:1;
+        /** db_a_outbypass : R/W; bitpos: [15]; default: 1;
+         *  Configures S1 in table.
+         */
+        uint32_t db_a_outbypass:1;
+        /** db_b_outbypass : R/W; bitpos: [16]; default: 1;
+         *  Configures S0 in table.
+         */
+        uint32_t db_b_outbypass:1;
+        /** db_clk_sel : R/W; bitpos: [17]; default: 0;
+         *  Configures dead time generator $n clock selection.\\0: PWM_clk\\1: PT_clk
+         */
+        uint32_t db_clk_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} mcpwm_dt_cfg_reg_t;
+
+/** Type of dt0_fed_cfg register
+ *  Falling edge delay (FED) shadow register
+ */
+typedef union {
+    struct {
+        /** db_fed : R/W; bitpos: [15:0]; default: 0;
+         *  Configures shadow register for FED.
+         */
+        uint32_t db_fed:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_fed_cfg_reg_t;
+
+/** Type of dt0_red_cfg register
+ *  Rising edge delay (RED) shadow register
+ */
+typedef union {
+    struct {
+        /** db_red : R/W; bitpos: [15:0]; default: 0;
+         *  Configures shadow register for RED.
+         */
+        uint32_t db_red:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_dt_red_cfg_reg_t;
+
+/** Type of carrier0_cfg register
+ *  Carrier$n configuration register
+ */
+typedef union {
+    struct {
+        /** chopper_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable carrier$n.\\0: Bypassed\\1: Enabled
+         */
+        uint32_t chopper_en:1;
+        /** chopper_prescale : R/W; bitpos: [4:1]; default: 0;
+         *  Configures the prescale value of PWM carrier$n clock (PC_clk), so that period of
+         *  PC_clk = period of PWM_clk * (PWM_CARRIER$n_PRESCALE + 1)
+         */
+        uint32_t chopper_prescale:4;
+        /** chopper_duty : R/W; bitpos: [7:5]; default: 0;
+         *  Configures carrier duty. Duty = PWM_CARRIER$n_DUTY / 8
+         */
+        uint32_t chopper_duty:3;
+        /** chopper_oshtwth : R/W; bitpos: [11:8]; default: 0;
+         *  Configures width of the first pulse. Measurement unit: Periods of the carrier.
+         */
+        uint32_t chopper_oshtwth:4;
+        /** chopper_out_invert : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to invert the output of PWM$n A and PWM$n B for this
+         *  submodule.\\0: Normal\\1: Invert
+         */
+        uint32_t chopper_out_invert:1;
+        /** chopper_in_invert : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to invert the input of PWM$n A and PWM$n B for this
+         *  submodule.\\0: Normal\\1: Invert
+         */
+        uint32_t chopper_in_invert:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} mcpwm_carrier_cfg_reg_t;
+
+/** Type of fh0_cfg0 register
+ *  PWM$n A and PWM$n B trip events actions configuration register
+ */
+typedef union {
+    struct {
+        /** tz_sw_cbc : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable software force cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_sw_cbc:1;
+        /** tz_f2_cbc : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f2_cbc:1;
+        /** tz_f1_cbc : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f1_cbc:1;
+        /** tz_f0_cbc : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f0_cbc:1;
+        /** tz_sw_ost : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable software force one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_sw_ost:1;
+        /** tz_f2_ost : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not event_f2 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f2_ost:1;
+        /** tz_f1_ost : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not event_f1 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f1_ost:1;
+        /** tz_f0_ost : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not event_f0 will trigger one-shot mode action.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t tz_f0_ost:1;
+        /** tz_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_a_cbc_d:2;
+        /** tz_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n A when fault event occurs and timer
+         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_a_cbc_u:2;
+        /** tz_a_ost_d : R/W; bitpos: [13:12]; default: 0;
+         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_a_ost_d:2;
+        /** tz_a_ost_u : R/W; bitpos: [15:14]; default: 0;
+         *  Configures one-shot mode action on PWM$n A when fault event occurs and timer is
+         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_a_ost_u:2;
+        /** tz_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+         *  is decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_b_cbc_d:2;
+        /** tz_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
+         *  Configures cycle-by-cycle mode action on PWM$n B when fault event occurs and timer
+         *  is increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_b_cbc_u:2;
+        /** tz_b_ost_d : R/W; bitpos: [21:20]; default: 0;
+         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+         *  decreasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_b_ost_d:2;
+        /** tz_b_ost_u : R/W; bitpos: [23:22]; default: 0;
+         *  Configures one-shot mode action on PWM$n B when fault event occurs and timer is
+         *  increasing.\\0: Do nothing\\1: Force low\\2: Force high\\3: Toggle
+         */
+        uint32_t tz_b_ost_u:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg0_reg_t;
+
+/** Type of fh0_cfg1 register
+ *  Software triggers for fault handler actions configuration register
+ */
+typedef union {
+    struct {
+        /** tz_clr_ost : R/W; bitpos: [0]; default: 0;
+         *  Configures the generation of software one-shot mode action clear. A toggle
+         *  (software negate its value) triggers a clear for on going one-shot mode action.
+         */
+        uint32_t tz_clr_ost:1;
+        /** tz_cbcpulse : R/W; bitpos: [2:1]; default: 0;
+         *  Configures the refresh moment selection of cycle-by-cycle mode action.\\0: Select
+         *  nothing, will not refresh\\Bit0 is set to 1: TEZ\\Bit1 is set to 1: TEP
+         */
+        uint32_t tz_cbcpulse:2;
+        /** tz_force_cbc : R/W; bitpos: [3]; default: 0;
+         *  Configures the generation of software cycle-by-cycle mode action. A toggle
+         *  (software negate its value) triggers a cycle-by-cycle mode action.
+         */
+        uint32_t tz_force_cbc:1;
+        /** tz_force_ost : R/W; bitpos: [4]; default: 0;
+         *  Configures the generation of software one-shot mode action. A toggle (software
+         *  negate its value) triggers a one-shot mode action.
+         */
+        uint32_t tz_force_ost:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg1_reg_t;
+
+/** Type of fh0_status register
+ *  Fault events status register
+ */
+typedef union {
+    struct {
+        /** tz_cbc_on : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not an cycle-by-cycle mode action is on going.\\0:No
+         *  action\\1: On going
+         */
+        uint32_t tz_cbc_on:1;
+        /** tz_ost_on : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not an one-shot mode action is on going.\\0:No action\\1: On
+         *  going
+         */
+        uint32_t tz_ost_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} mcpwm_fh_status_reg_t;
+
+/** Group: fault_detect */
+/** Type of fault_detect register
+ *  Fault detection configuration and status register
+ */
+typedef union {
+    struct {
+        /** f0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable event_f0 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f0_en:1;
+        /** f1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable event_f1 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f1_en:1;
+        /** f2_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable event_f2 generation.\\0: Disable\\1: Enable
+         */
+        uint32_t f2_en:1;
+        /** f0_pole : R/W; bitpos: [3]; default: 0;
+         *  Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f0_pole:1;
+        /** f1_pole : R/W; bitpos: [4]; default: 0;
+         *  Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f1_pole:1;
+        /** f2_pole : R/W; bitpos: [5]; default: 0;
+         *  Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\0: Level
+         *  low\\1: Level high
+         */
+        uint32_t f2_pole:1;
+        /** event_f0 : RO; bitpos: [6]; default: 0;
+         *  Represents whether or not an event_f0 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f0:1;
+        /** event_f1 : RO; bitpos: [7]; default: 0;
+         *  Represents whether or not an event_f1 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f1:1;
+        /** event_f2 : RO; bitpos: [8]; default: 0;
+         *  Represents whether or not an event_f2 is on going.\\0: No action\\1: On going
+         */
+        uint32_t event_f2:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} mcpwm_fault_detect_reg_t;
+
+
+/** Group: cap_timer_cfg */
+/** Type of cap_timer_cfg register
+ *  Capture timer configuration register
+ */
+typedef union {
+    struct {
+        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable capture timer increment.\\0: Disable\\1: Enable
+         */
+        uint32_t cap_timer_en:1;
+        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable capture timer sync.\\0: Disable\\1: Enable
+         */
+        uint32_t cap_synci_en:1;
+        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
+         *  Configures the selection of capture module sync input.\\0: None\\1: Timer0
+         *  sync_out\\2: Timer1 sync_out\\3: Timer2 sync_out\\4: SYNC0 from GPIO matrix\\5:
+         *  SYNC1 from GPIO matrix\\6: SYNC2 from GPIO matrix\\7: None
+         */
+        uint32_t cap_synci_sel:3;
+        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
+         *  Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\0:
+         *  Invalid, No effect\\1: Trigger a capture timer sync, capture timer is loaded with
+         *  value in phase register
+         */
+        uint32_t cap_sync_sw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_cfg_reg_t;
+
+
+/** Group: cap_timer_phase */
+/** Type of cap_timer_phase register
+ *  Capture timer sync phase register
+ */
+typedef union {
+    struct {
+        /** cap_phase : R/W; bitpos: [31:0]; default: 0;
+         *  Configures phase value for capture timer sync operation.
+         */
+        uint32_t cap_phase:32;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_phase_reg_t;
+
+
+/** Group: cap_chn_cfg */
+/** Type of cap_chn_cfg register
+ *  Capture channel n configuration register
+ */
+typedef union {
+    struct {
+        /** capn_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable capture on channel n.\\0: Disable\\1: Enable
+         */
+        uint32_t capn_en:1;
+        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
+         *  Configures which edge of capture on channel n after prescaling is used.\\0:
+         *  None\\Bit0 is set to 1: Rnable capture on the negative edge\\Bit1 is set to 1:
+         *  Enable capture on the positive edge
+         */
+        uint32_t capn_mode:2;
+        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
+         *  Configures prescale value on positive edge of CAPn. Prescale value =
+         *  PWM_CAPn_PRESCALE + 1
+         */
+        uint32_t capn_prescale:8;
+        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to invert CAPn from GPIO matrix before prescale.\\0:
+         *  Normal\\1: Invert
+         */
+        uint32_t capn_in_invert:1;
+        /** capn_sw : WT; bitpos: [12]; default: 0;
+         *  Configures the generation of software capture.\\0: Invalid, No effect\\1: Trigger a
+         *  software forced capture on channel n
+         */
+        uint32_t capn_sw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_cfg_reg_t;
+
+
+/** Group: cap_chn */
+/** Type of cap_chn register
+ *  CAPn capture value register
+ */
+typedef union {
+    struct {
+        /** capn_value : RO; bitpos: [31:0]; default: 0;
+         *  Represents value of last capture on CAPn
+         */
+        uint32_t capn_value:32;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_reg_t;
+
+
+/** Group: cap_status */
+/** Type of cap_status register
+ *  Last capture trigger edge information register
+ */
+typedef union {
+    struct {
+        /** cap0_edge : RO; bitpos: [0]; default: 0;
+         *  Represents edge of last capture trigger on channel0.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap0_edge:1;
+        /** cap1_edge : RO; bitpos: [1]; default: 0;
+         *  Represents edge of last capture trigger on channel1.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap1_edge:1;
+        /** cap2_edge : RO; bitpos: [2]; default: 0;
+         *  Represents edge of last capture trigger on channel2.\\0: Posedge\\1: Negedge
+         */
+        uint32_t cap2_edge:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} mcpwm_cap_status_reg_t;
+
+
+/** Group: update_cfg */
+/** Type of update_cfg register
+ *  Generator Update configuration register
+ */
+typedef union {
+    struct {
+        /** global_up_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether or not to enable global update for all active registers in MCPWM
+         *  module.\\0: Disable\\1: Enable
+         */
+        uint32_t global_up_en:1;
+        /** global_force_up : R/W; bitpos: [1]; default: 0;
+         *  Configures the generation of global forced update for all active registers in MCPWM
+         *  module. A toggle (software invert its value) will trigger a global forced update.
+         *  Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1.
+         */
+        uint32_t global_force_up:1;
+        /** op0_up_en : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op0_up_en:1;
+        /** op0_force_up : R/W; bitpos: [3]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator0. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1.
+         */
+        uint32_t op0_force_up:1;
+        /** op1_up_en : R/W; bitpos: [4]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op1_up_en:1;
+        /** op1_force_up : R/W; bitpos: [5]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator1. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1.
+         */
+        uint32_t op1_force_up:1;
+        /** op2_up_en : R/W; bitpos: [6]; default: 1;
+         *  Configures whether or not to enable update of active registers in PWM operator$n.
+         *  Valid only when PWM_GLOBAL_UP_EN is set to 1.\\0: Disable\\1: Enable
+         */
+        uint32_t op2_up_en:1;
+        /** op2_force_up : R/W; bitpos: [7]; default: 0;
+         *  Configures the generation of forced update for active registers in PWM operator2. A
+         *  toggle (software invert its value) will trigger a forced update. Valid only when
+         *  MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1.
+         */
+        uint32_t op2_force_up:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} mcpwm_update_cfg_reg_t;
+
+
+/** Group: int_ena */
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_ena:1;
+        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_ena:1;
+        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_ena:1;
+        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_ena:1;
+        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_ena:1;
+        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_ena:1;
+        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_ena:1;
+        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_ena:1;
+        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_ena:1;
+        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_ena:1;
+        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_ena:1;
+        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_ena:1;
+        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.
+         */
+        uint32_t fault0_clr_int_ena:1;
+        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.
+         */
+        uint32_t fault1_clr_int_ena:1;
+        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.
+         */
+        uint32_t fault2_clr_int_ena:1;
+        /** cmpr0_tea_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.
+         */
+        uint32_t cmpr0_tea_int_ena:1;
+        /** cmpr1_tea_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.
+         */
+        uint32_t cmpr1_tea_int_ena:1;
+        /** cmpr2_tea_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.
+         */
+        uint32_t cmpr2_tea_int_ena:1;
+        /** cmpr0_teb_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.
+         */
+        uint32_t cmpr0_teb_int_ena:1;
+        /** cmpr1_teb_int_ena : R/W; bitpos: [19]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.
+         */
+        uint32_t cmpr1_teb_int_ena:1;
+        /** cmpr2_teb_int_ena : R/W; bitpos: [20]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.
+         */
+        uint32_t cmpr2_teb_int_ena:1;
+        /** tz0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM0.
+         */
+        uint32_t tz0_cbc_int_ena:1;
+        /** tz1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM1.
+         */
+        uint32_t tz1_cbc_int_ena:1;
+        /** tz2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode
+         *  action on PWM2.
+         */
+        uint32_t tz2_cbc_int_ena:1;
+        /** tz0_ost_int_ena : R/W; bitpos: [24]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_ost_int_ena:1;
+        /** tz1_ost_int_ena : R/W; bitpos: [25]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_ost_int_ena:1;
+        /** tz2_ost_int_ena : R/W; bitpos: [26]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_ost_int_ena:1;
+        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.
+         */
+        uint32_t cap0_int_ena:1;
+        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.
+         */
+        uint32_t cap1_int_ena:1;
+        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
+         *  Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.
+         */
+        uint32_t cap2_int_ena:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_ena_reg_t;
+
+
+/** Group: int_raw */
+/** Type of int_raw register
+ *  Interrupt raw status register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  0 stops.
+         */
+        uint32_t timer0_stop_int_raw:1;
+        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  1 stops.
+         */
+        uint32_t timer1_stop_int_raw:1;
+        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when the timer
+         *  2 stops.
+         */
+        uint32_t timer2_stop_int_raw:1;
+        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  0 TEZ event.
+         */
+        uint32_t timer0_tez_int_raw:1;
+        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  1 TEZ event.
+         */
+        uint32_t timer1_tez_int_raw:1;
+        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  2 TEZ event.
+         */
+        uint32_t timer2_tez_int_raw:1;
+        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  0 TEP event.
+         */
+        uint32_t timer0_tep_int_raw:1;
+        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  1 TEP event.
+         */
+        uint32_t timer1_tep_int_raw:1;
+        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer
+         *  2 TEP event.
+         */
+        uint32_t timer2_tep_int_raw:1;
+        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+         *  starts.
+         */
+        uint32_t fault0_int_raw:1;
+        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+         *  starts.
+         */
+        uint32_t fault1_int_raw:1;
+        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+         *  starts.
+         */
+        uint32_t fault2_int_raw:1;
+        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f0
+         *  clears.
+         */
+        uint32_t fault0_clr_int_raw:1;
+        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f1
+         *  clears.
+         */
+        uint32_t fault1_clr_int_raw:1;
+        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered when event_f2
+         *  clears.
+         */
+        uint32_t fault2_clr_int_raw:1;
+        /** cmpr0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_raw:1;
+        /** cmpr1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_raw:1;
+        /** cmpr2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_raw:1;
+        /** cmpr0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_raw:1;
+        /** cmpr1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_raw:1;
+        /** cmpr2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_raw:1;
+        /** tz0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_raw:1;
+        /** tz1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_raw:1;
+        /** tz2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_raw:1;
+        /** tz0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_raw:1;
+        /** tz1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_raw:1;
+        /** tz2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot
+         *  mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_raw:1;
+        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP0.
+         */
+        uint32_t cap0_int_raw:1;
+        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP1.
+         */
+        uint32_t cap1_int_raw:1;
+        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  Raw status bit: The raw interrupt status of the interrupt triggered by capture on
+         *  CAP2.
+         */
+        uint32_t cap2_int_raw:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_raw_reg_t;
+
+
+/** Group: int_st */
+/** Type of int_st register
+ *  Interrupt masked status register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 0 stops.
+         */
+        uint32_t timer0_stop_int_st:1;
+        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 1 stops.
+         */
+        uint32_t timer1_stop_int_st:1;
+        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when the
+         *  timer 2 stops.
+         */
+        uint32_t timer2_stop_int_st:1;
+        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_st:1;
+        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_st:1;
+        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_st:1;
+        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_st:1;
+        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_st:1;
+        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_st:1;
+        /** fault0_int_st : RO; bitpos: [9]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f0 starts.
+         */
+        uint32_t fault0_int_st:1;
+        /** fault1_int_st : RO; bitpos: [10]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f1 starts.
+         */
+        uint32_t fault1_int_st:1;
+        /** fault2_int_st : RO; bitpos: [11]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f2 starts.
+         */
+        uint32_t fault2_int_st:1;
+        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f0 clears.
+         */
+        uint32_t fault0_clr_int_st:1;
+        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f1 clears.
+         */
+        uint32_t fault1_clr_int_st:1;
+        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered when
+         *  event_f2 clears.
+         */
+        uint32_t fault2_clr_int_st:1;
+        /** cmpr0_tea_int_st : RO; bitpos: [15]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_st:1;
+        /** cmpr1_tea_int_st : RO; bitpos: [16]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_st:1;
+        /** cmpr2_tea_int_st : RO; bitpos: [17]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_st:1;
+        /** cmpr0_teb_int_st : RO; bitpos: [18]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_st:1;
+        /** cmpr1_teb_int_st : RO; bitpos: [19]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_st:1;
+        /** cmpr2_teb_int_st : RO; bitpos: [20]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a PWM
+         *  operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_st:1;
+        /** tz0_cbc_int_st : RO; bitpos: [21]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t tz0_cbc_int_st:1;
+        /** tz1_cbc_int_st : RO; bitpos: [22]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t tz1_cbc_int_st:1;
+        /** tz2_cbc_int_st : RO; bitpos: [23]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t tz2_cbc_int_st:1;
+        /** tz0_ost_int_st : RO; bitpos: [24]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM0.
+         */
+        uint32_t tz0_ost_int_st:1;
+        /** tz1_ost_int_st : RO; bitpos: [25]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM1.
+         */
+        uint32_t tz1_ost_int_st:1;
+        /** tz2_ost_int_st : RO; bitpos: [26]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by a
+         *  one-shot mode action on PWM2.
+         */
+        uint32_t tz2_ost_int_st:1;
+        /** cap0_int_st : RO; bitpos: [27]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP0.
+         */
+        uint32_t cap0_int_st:1;
+        /** cap1_int_st : RO; bitpos: [28]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP1.
+         */
+        uint32_t cap1_int_st:1;
+        /** cap2_int_st : RO; bitpos: [29]; default: 0;
+         *  Masked status bit: The masked interrupt status of the interrupt triggered by
+         *  capture on CAP2.
+         */
+        uint32_t cap2_int_st:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_st_reg_t;
+
+
+/** Group: int_clr */
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_clr:1;
+        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_clr:1;
+        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_clr:1;
+        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_clr:1;
+        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_clr:1;
+        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_clr:1;
+        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_clr:1;
+        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_clr:1;
+        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_clr:1;
+        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts.
+         */
+        uint32_t fault0_int_clr:1;
+        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts.
+         */
+        uint32_t fault1_int_clr:1;
+        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts.
+         */
+        uint32_t fault2_int_clr:1;
+        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears.
+         */
+        uint32_t fault0_clr_int_clr:1;
+        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears.
+         */
+        uint32_t fault1_clr_int_clr:1;
+        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears.
+         */
+        uint32_t fault2_clr_int_clr:1;
+        /** cmpr0_tea_int_clr : WT; bitpos: [15]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t cmpr0_tea_int_clr:1;
+        /** cmpr1_tea_int_clr : WT; bitpos: [16]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t cmpr1_tea_int_clr:1;
+        /** cmpr2_tea_int_clr : WT; bitpos: [17]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t cmpr2_tea_int_clr:1;
+        /** cmpr0_teb_int_clr : WT; bitpos: [18]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t cmpr0_teb_int_clr:1;
+        /** cmpr1_teb_int_clr : WT; bitpos: [19]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t cmpr1_teb_int_clr:1;
+        /** cmpr2_teb_int_clr : WT; bitpos: [20]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t cmpr2_teb_int_clr:1;
+        /** tz0_cbc_int_clr : WT; bitpos: [21]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM0.
+         */
+        uint32_t tz0_cbc_int_clr:1;
+        /** tz1_cbc_int_clr : WT; bitpos: [22]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM1.
+         */
+        uint32_t tz1_cbc_int_clr:1;
+        /** tz2_cbc_int_clr : WT; bitpos: [23]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM2.
+         */
+        uint32_t tz2_cbc_int_clr:1;
+        /** tz0_ost_int_clr : WT; bitpos: [24]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM0.
+         */
+        uint32_t tz0_ost_int_clr:1;
+        /** tz1_ost_int_clr : WT; bitpos: [25]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM1.
+         */
+        uint32_t tz1_ost_int_clr:1;
+        /** tz2_ost_int_clr : WT; bitpos: [26]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on
+         *  PWM2.
+         */
+        uint32_t tz2_ost_int_clr:1;
+        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0.
+         */
+        uint32_t cap0_int_clr:1;
+        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1.
+         */
+        uint32_t cap1_int_clr:1;
+        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
+         *  Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2.
+         */
+        uint32_t cap2_int_clr:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_int_clr_reg_t;
+
+
+/** Group: evt_en */
+/** Type of evt_en register
+ *  Event enable register
+ */
+typedef union {
+    struct {
+        /** evt_timer0_stop_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable timer0 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer0_stop_en:1;
+        /** evt_timer1_stop_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable timer1 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer1_stop_en:1;
+        /** evt_timer2_stop_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable timer2 stop event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_timer2_stop_en:1;
+        /** evt_timer0_tez_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable timer0 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer0_tez_en:1;
+        /** evt_timer1_tez_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable timer1 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer1_tez_en:1;
+        /** evt_timer2_tez_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable timer2 equal zero event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer2_tez_en:1;
+        /** evt_timer0_tep_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable timer0 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer0_tep_en:1;
+        /** evt_timer1_tep_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable timer1 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer1_tep_en:1;
+        /** evt_timer2_tep_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable timer2 equal period event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_timer2_tep_en:1;
+        /** evt_op0_tea_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tea_en:1;
+        /** evt_op1_tea_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tea_en:1;
+        /** evt_op2_tea_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal a event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tea_en:1;
+        /** evt_op0_teb_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_teb_en:1;
+        /** evt_op1_teb_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_teb_en:1;
+        /** evt_op2_teb_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal b event
+         *  generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_teb_en:1;
+        /** evt_f0_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable fault0 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f0_en:1;
+        /** evt_f1_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable fault1 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f1_en:1;
+        /** evt_f2_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable fault2 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_f2_en:1;
+        /** evt_f0_clr_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable fault0 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f0_clr_en:1;
+        /** evt_f1_clr_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable fault1 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f1_clr_en:1;
+        /** evt_f2_clr_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable fault2 clear event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_f2_clr_en:1;
+        /** evt_tz0_cbc_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip0 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz0_cbc_en:1;
+        /** evt_tz1_cbc_en : R/W; bitpos: [22]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip1 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz1_cbc_en:1;
+        /** evt_tz2_cbc_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable cycle-by-cycle trip2 event generate.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t evt_tz2_cbc_en:1;
+        /** evt_tz0_ost_en : R/W; bitpos: [24]; default: 0;
+         *  Configures whether or not to enable one-shot trip0 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz0_ost_en:1;
+        /** evt_tz1_ost_en : R/W; bitpos: [25]; default: 0;
+         *  Configures whether or not to enable one-shot trip1 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz1_ost_en:1;
+        /** evt_tz2_ost_en : R/W; bitpos: [26]; default: 0;
+         *  Configures whether or not to enable one-shot trip2 event generate.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t evt_tz2_ost_en:1;
+        /** evt_cap0_en : R/W; bitpos: [27]; default: 0;
+         *  Configures whether or not to enable capture0 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap0_en:1;
+        /** evt_cap1_en : R/W; bitpos: [28]; default: 0;
+         *  Configures whether or not to enable capture1 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap1_en:1;
+        /** evt_cap2_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable capture2 event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_cap2_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} mcpwm_evt_en_reg_t;
+
+
+/** Group: task_en */
+/** Type of task_en register
+ *  Task enable register
+ */
+typedef union {
+    struct {
+        /** task_cmpr0_a_up_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr0_a_up_en:1;
+        /** task_cmpr1_a_up_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr1_a_up_en:1;
+        /** task_cmpr2_a_up_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer stamp A's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr2_a_up_en:1;
+        /** task_cmpr0_b_up_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr0_b_up_en:1;
+        /** task_cmpr1_b_up_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr1_b_up_en:1;
+        /** task_cmpr2_b_up_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer stamp B's shadow register
+         *  update task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cmpr2_b_up_en:1;
+        /** task_gen_stop_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable all PWM generate stop task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_gen_stop_en:1;
+        /** task_timer0_sync_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable timer0 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer0_sync_en:1;
+        /** task_timer1_sync_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not to enable timer1 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer1_sync_en:1;
+        /** task_timer2_sync_en : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable timer2 sync task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_timer2_sync_en:1;
+        /** task_timer0_period_up_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether or not to enable timer0 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer0_period_up_en:1;
+        /** task_timer1_period_up_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable timer1 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer1_period_up_en:1;
+        /** task_timer2_period_up_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to enable timer2 period update task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_timer2_period_up_en:1;
+        /** task_tz0_ost_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to enable one shot trip0 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz0_ost_en:1;
+        /** task_tz1_ost_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether or not to enable one shot trip1 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz1_ost_en:1;
+        /** task_tz2_ost_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable one shot trip2 task receive.\\0: Disable\\1:
+         *  Enable
+         */
+        uint32_t task_tz2_ost_en:1;
+        /** task_clr0_ost_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable one shot trip0 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr0_ost_en:1;
+        /** task_clr1_ost_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable one shot trip1 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr1_ost_en:1;
+        /** task_clr2_ost_en : R/W; bitpos: [18]; default: 0;
+         *  Configures whether or not to enable one shot trip2 clear task receive.\\0:
+         *  Disable\\1: Enable
+         */
+        uint32_t task_clr2_ost_en:1;
+        /** task_cap0_en : R/W; bitpos: [19]; default: 0;
+         *  Configures whether or not to enable capture0 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap0_en:1;
+        /** task_cap1_en : R/W; bitpos: [20]; default: 0;
+         *  Configures whether or not to enable capture1 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap1_en:1;
+        /** task_cap2_en : R/W; bitpos: [21]; default: 0;
+         *  Configures whether or not to enable capture2 task receive.\\0: Disable\\1: Enable
+         */
+        uint32_t task_cap2_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} mcpwm_task_en_reg_t;
+
+
+/** Group: evt_en2 */
+/** Type of evt_en2 register
+ *  Event enable register2
+ */
+typedef union {
+    struct {
+        /** evt_op0_tee1_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tee1_en:1;
+        /** evt_op1_tee1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tee1_en:1;
+        /** evt_op2_tee1_en : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tee1_en:1;
+        /** evt_op0_tee2_en : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op0_tee2_en:1;
+        /** evt_op1_tee2_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op1_tee2_en:1;
+        /** evt_op2_tee2_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG
+         *  event generate.\\0: Disable\\1: Enable
+         */
+        uint32_t evt_op2_tee2_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} mcpwm_evt_en2_reg_t;
+
+
+/** Group: Configuration register */
+/** Type of opn_tstmp_e1 register
+ *  Generatorn timer stamp E1 value register
+ */
+typedef union {
+    struct {
+        /** op_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
+         *  Configures generatorn timer stamp E1 value register
+         */
+        uint32_t op_tstmp_e:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} mcpwm_op_tstmp_reg_t;
+
+/** Type of clk register
+ *  Global configuration register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to open register clock gate.\\0: Open the clock gate only
+         *  when application writes registers\\1: Force open the clock gate for register
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} mcpwm_clk_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35725968;
+         *  Configures the version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} mcpwm_version_reg_t;
+
+typedef struct {
+    volatile mcpwm_timer_cfg0_reg_t timer_cfg0;
+    volatile mcpwm_timer_cfg1_reg_t timer_cfg1;
+    volatile mcpwm_timer_sync_reg_t timer_sync;
+    volatile mcpwm_timer_status_reg_t timer_status;
+} mcpwm_timer_regs_t;
+
+typedef struct {
+    volatile mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
+    volatile mcpwm_gen_tstmp_reg_t timestamp[2];
+    volatile mcpwm_gen_cfg0_reg_t gen_cfg0;
+    volatile mcpwm_gen_force_reg_t gen_force;
+    volatile mcpwm_gen_reg_t generator[2];
+    volatile mcpwm_dt_cfg_reg_t dt_cfg;
+    volatile mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
+    volatile mcpwm_dt_red_cfg_reg_t dt_red_cfg;
+    volatile mcpwm_carrier_cfg_reg_t carrier_cfg;
+    volatile mcpwm_fh_cfg0_reg_t fh_cfg0;
+    volatile mcpwm_fh_cfg1_reg_t fh_cfg1;
+    volatile mcpwm_fh_status_reg_t fh_status;
+} mcpwm_operator_reg_t;
+
+typedef struct {
+    volatile mcpwm_op_tstmp_reg_t timestamp[2];
+} mcpwm_operator_tstmp_reg_t;
+
+typedef struct mcpwm_dev_t {
+    volatile mcpwm_clk_cfg_reg_t clk_cfg;
+    volatile mcpwm_timer_regs_t timer[3];
+    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
+    volatile mcpwm_operator_timersel_reg_t operator_timersel;
+    volatile mcpwm_operator_reg_t operators[3];
+    volatile mcpwm_fault_detect_reg_t fault_detect;
+    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
+    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
+    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
+    volatile mcpwm_cap_chn_reg_t cap_chn[3];
+    volatile mcpwm_cap_status_reg_t cap_status;
+    volatile mcpwm_update_cfg_reg_t update_cfg;
+    volatile mcpwm_int_ena_reg_t int_ena;
+    volatile mcpwm_int_raw_reg_t int_raw;
+    volatile mcpwm_int_st_reg_t int_st;
+    volatile mcpwm_int_clr_reg_t int_clr;
+    volatile mcpwm_evt_en_reg_t evt_en;
+    volatile mcpwm_task_en_reg_t task_en;
+    volatile mcpwm_evt_en2_reg_t evt_en2;
+    volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3];
+    volatile mcpwm_clk_reg_t clk;
+    volatile mcpwm_version_reg_t version;
+} mcpwm_dev_t;
+
+extern mcpwm_dev_t MCPWM0;
+extern mcpwm_dev_t MCPWM1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/mipi_csi_bridge_reg.h b/components/soc/esp32p4/register/soc/mipi_csi_bridge_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/mipi_csi_bridge_reg.h
rename to components/soc/esp32p4/register/soc/mipi_csi_bridge_reg.h
diff --git a/components/soc/esp32p4/include/soc/mipi_csi_bridge_struct.h b/components/soc/esp32p4/register/soc/mipi_csi_bridge_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/mipi_csi_bridge_struct.h
rename to components/soc/esp32p4/register/soc/mipi_csi_bridge_struct.h
diff --git a/components/soc/esp32p4/include/soc/mipi_csi_host_reg.h b/components/soc/esp32p4/register/soc/mipi_csi_host_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/mipi_csi_host_reg.h
rename to components/soc/esp32p4/register/soc/mipi_csi_host_reg.h
diff --git a/components/soc/esp32p4/include/soc/mipi_csi_host_struct.h b/components/soc/esp32p4/register/soc/mipi_csi_host_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/mipi_csi_host_struct.h
rename to components/soc/esp32p4/register/soc/mipi_csi_host_struct.h
diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_bridge_reg.h b/components/soc/esp32p4/register/soc/mipi_dsi_bridge_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/mipi_dsi_bridge_reg.h
rename to components/soc/esp32p4/register/soc/mipi_dsi_bridge_reg.h
diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_bridge_struct.h b/components/soc/esp32p4/register/soc/mipi_dsi_bridge_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/mipi_dsi_bridge_struct.h
rename to components/soc/esp32p4/register/soc/mipi_dsi_bridge_struct.h
diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_host_reg.h b/components/soc/esp32p4/register/soc/mipi_dsi_host_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/mipi_dsi_host_reg.h
rename to components/soc/esp32p4/register/soc/mipi_dsi_host_reg.h
diff --git a/components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h b/components/soc/esp32p4/register/soc/mipi_dsi_host_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/mipi_dsi_host_struct.h
rename to components/soc/esp32p4/register/soc/mipi_dsi_host_struct.h
diff --git a/components/soc/esp32p4/register/soc/parl_io_reg.h b/components/soc/esp32p4/register/soc/parl_io_reg.h
new file mode 100644
index 00000000000..812470334d8
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/parl_io_reg.h
@@ -0,0 +1,480 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** PARL_IO_RX_MODE_CFG_REG register
+ *  Parallel RX Sampling mode configuration register.
+ */
+#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
+/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
+ *  Configures rx external enable signal selection from IO PAD.
+ */
+#define PARL_IO_RX_EXT_EN_SEL    0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_M  (PARL_IO_RX_EXT_EN_SEL_V << PARL_IO_RX_EXT_EN_SEL_S)
+#define PARL_IO_RX_EXT_EN_SEL_V  0x0000000FU
+#define PARL_IO_RX_EXT_EN_SEL_S  21
+/** PARL_IO_RX_SW_EN : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to enable data sampling by software.
+ */
+#define PARL_IO_RX_SW_EN    (BIT(25))
+#define PARL_IO_RX_SW_EN_M  (PARL_IO_RX_SW_EN_V << PARL_IO_RX_SW_EN_S)
+#define PARL_IO_RX_SW_EN_V  0x00000001U
+#define PARL_IO_RX_SW_EN_S  25
+/** PARL_IO_RX_EXT_EN_INV : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to invert the external enable signal.
+ */
+#define PARL_IO_RX_EXT_EN_INV    (BIT(26))
+#define PARL_IO_RX_EXT_EN_INV_M  (PARL_IO_RX_EXT_EN_INV_V << PARL_IO_RX_EXT_EN_INV_S)
+#define PARL_IO_RX_EXT_EN_INV_V  0x00000001U
+#define PARL_IO_RX_EXT_EN_INV_S  26
+/** PARL_IO_RX_PULSE_SUBMODE_SEL : R/W; bitpos: [29:27]; default: 0;
+ *  Configures the rxd pulse sampling submode.
+ *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
+ *  included)
+ *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
+ *  excluded)
+ *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
+ *  included)
+ *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
+ *  excluded)
+ *  4'd4: positive pulse start(data bit included) && length end
+ *  4'd5: positive pulse start(data bit excluded) && length end
+ */
+#define PARL_IO_RX_PULSE_SUBMODE_SEL    0x00000007U
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_M  (PARL_IO_RX_PULSE_SUBMODE_SEL_V << PARL_IO_RX_PULSE_SUBMODE_SEL_S)
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_V  0x00000007U
+#define PARL_IO_RX_PULSE_SUBMODE_SEL_S  27
+/** PARL_IO_RX_SMP_MODE_SEL : R/W; bitpos: [31:30]; default: 0;
+ *  Configures the rxd sampling mode.
+ *  2'b00: external level enable mode
+ *  2'b01: external pulse enable mode
+ *  2'b10: internal software enable mode
+ */
+#define PARL_IO_RX_SMP_MODE_SEL    0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_M  (PARL_IO_RX_SMP_MODE_SEL_V << PARL_IO_RX_SMP_MODE_SEL_S)
+#define PARL_IO_RX_SMP_MODE_SEL_V  0x00000003U
+#define PARL_IO_RX_SMP_MODE_SEL_S  30
+
+/** PARL_IO_RX_DATA_CFG_REG register
+ *  Parallel RX data configuration register.
+ */
+#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
+/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
+ *  Configures expected byte number of received data.
+ */
+#define PARL_IO_RX_BITLEN    0x0007FFFFU
+#define PARL_IO_RX_BITLEN_M  (PARL_IO_RX_BITLEN_V << PARL_IO_RX_BITLEN_S)
+#define PARL_IO_RX_BITLEN_V  0x0007FFFFU
+#define PARL_IO_RX_BITLEN_S  9
+/** PARL_IO_RX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
+ */
+#define PARL_IO_RX_DATA_ORDER_INV    (BIT(28))
+#define PARL_IO_RX_DATA_ORDER_INV_M  (PARL_IO_RX_DATA_ORDER_INV_V << PARL_IO_RX_DATA_ORDER_INV_S)
+#define PARL_IO_RX_DATA_ORDER_INV_V  0x00000001U
+#define PARL_IO_RX_DATA_ORDER_INV_S  28
+/** PARL_IO_RX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
+ *  Configures the rxd bus width.
+ *  3'd0: bus width is 1.
+ *  3'd1: bus width is 2.
+ *  3'd2: bus width is 4.
+ *  3'd3: bus width is 8.
+ */
+#define PARL_IO_RX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_M  (PARL_IO_RX_BUS_WID_SEL_V << PARL_IO_RX_BUS_WID_SEL_S)
+#define PARL_IO_RX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_RX_BUS_WID_SEL_S  29
+
+/** PARL_IO_RX_GENRL_CFG_REG register
+ *  Parallel RX general configuration register.
+ */
+#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
+/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable the clock gating of output rx clock.
+ */
+#define PARL_IO_RX_GATING_EN    (BIT(12))
+#define PARL_IO_RX_GATING_EN_M  (PARL_IO_RX_GATING_EN_V << PARL_IO_RX_GATING_EN_S)
+#define PARL_IO_RX_GATING_EN_V  0x00000001U
+#define PARL_IO_RX_GATING_EN_S  12
+/** PARL_IO_RX_TIMEOUT_THRES : R/W; bitpos: [28:13]; default: 4095;
+ *  Configures threshold of timeout counter.
+ */
+#define PARL_IO_RX_TIMEOUT_THRES    0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRES_M  (PARL_IO_RX_TIMEOUT_THRES_V << PARL_IO_RX_TIMEOUT_THRES_S)
+#define PARL_IO_RX_TIMEOUT_THRES_V  0x0000FFFFU
+#define PARL_IO_RX_TIMEOUT_THRES_S  13
+/** PARL_IO_RX_TIMEOUT_EN : R/W; bitpos: [29]; default: 1;
+ *  Set this bit to enable timeout function to generate error eof.
+ */
+#define PARL_IO_RX_TIMEOUT_EN    (BIT(29))
+#define PARL_IO_RX_TIMEOUT_EN_M  (PARL_IO_RX_TIMEOUT_EN_V << PARL_IO_RX_TIMEOUT_EN_S)
+#define PARL_IO_RX_TIMEOUT_EN_V  0x00000001U
+#define PARL_IO_RX_TIMEOUT_EN_S  29
+/** PARL_IO_RX_EOF_GEN_SEL : R/W; bitpos: [30]; default: 0;
+ *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
+ *  1'b1: eof generated by external enable signal.
+ */
+#define PARL_IO_RX_EOF_GEN_SEL    (BIT(30))
+#define PARL_IO_RX_EOF_GEN_SEL_M  (PARL_IO_RX_EOF_GEN_SEL_V << PARL_IO_RX_EOF_GEN_SEL_S)
+#define PARL_IO_RX_EOF_GEN_SEL_V  0x00000001U
+#define PARL_IO_RX_EOF_GEN_SEL_S  30
+
+/** PARL_IO_RX_START_CFG_REG register
+ *  Parallel RX Start configuration register.
+ */
+#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
+/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start rx data sampling.
+ */
+#define PARL_IO_RX_START    (BIT(31))
+#define PARL_IO_RX_START_M  (PARL_IO_RX_START_V << PARL_IO_RX_START_S)
+#define PARL_IO_RX_START_V  0x00000001U
+#define PARL_IO_RX_START_S  31
+
+/** PARL_IO_TX_DATA_CFG_REG register
+ *  Parallel TX data configuration register.
+ */
+#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
+/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
+ *  Configures expected byte number of sent data.
+ */
+#define PARL_IO_TX_BITLEN    0x0007FFFFU
+#define PARL_IO_TX_BITLEN_M  (PARL_IO_TX_BITLEN_V << PARL_IO_TX_BITLEN_S)
+#define PARL_IO_TX_BITLEN_V  0x0007FFFFU
+#define PARL_IO_TX_BITLEN_S  9
+/** PARL_IO_TX_DATA_ORDER_INV : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
+ */
+#define PARL_IO_TX_DATA_ORDER_INV    (BIT(28))
+#define PARL_IO_TX_DATA_ORDER_INV_M  (PARL_IO_TX_DATA_ORDER_INV_V << PARL_IO_TX_DATA_ORDER_INV_S)
+#define PARL_IO_TX_DATA_ORDER_INV_V  0x00000001U
+#define PARL_IO_TX_DATA_ORDER_INV_S  28
+/** PARL_IO_TX_BUS_WID_SEL : R/W; bitpos: [31:29]; default: 3;
+ *  Configures the txd bus width.
+ *  3'd0: bus width is 1.
+ *  3'd1: bus width is 2.
+ *  3'd2: bus width is 4.
+ *  3'd3: bus width is 8.
+ */
+#define PARL_IO_TX_BUS_WID_SEL    0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_M  (PARL_IO_TX_BUS_WID_SEL_V << PARL_IO_TX_BUS_WID_SEL_S)
+#define PARL_IO_TX_BUS_WID_SEL_V  0x00000007U
+#define PARL_IO_TX_BUS_WID_SEL_S  29
+
+/** PARL_IO_TX_START_CFG_REG register
+ *  Parallel TX Start configuration register.
+ */
+#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
+/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to start tx data transmit.
+ */
+#define PARL_IO_TX_START    (BIT(31))
+#define PARL_IO_TX_START_M  (PARL_IO_TX_START_V << PARL_IO_TX_START_S)
+#define PARL_IO_TX_START_V  0x00000001U
+#define PARL_IO_TX_START_S  31
+
+/** PARL_IO_TX_GENRL_CFG_REG register
+ *  Parallel TX general configuration register.
+ */
+#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
+/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
+ *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
+ *  1'b1: eof generated by DMA eof.
+ */
+#define PARL_IO_TX_EOF_GEN_SEL    (BIT(13))
+#define PARL_IO_TX_EOF_GEN_SEL_M  (PARL_IO_TX_EOF_GEN_SEL_V << PARL_IO_TX_EOF_GEN_SEL_S)
+#define PARL_IO_TX_EOF_GEN_SEL_V  0x00000001U
+#define PARL_IO_TX_EOF_GEN_SEL_S  13
+/** PARL_IO_TX_IDLE_VALUE : R/W; bitpos: [29:14]; default: 0;
+ *  Configures bus value of transmitter in IDLE state.
+ */
+#define PARL_IO_TX_IDLE_VALUE    0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_M  (PARL_IO_TX_IDLE_VALUE_V << PARL_IO_TX_IDLE_VALUE_S)
+#define PARL_IO_TX_IDLE_VALUE_V  0x0000FFFFU
+#define PARL_IO_TX_IDLE_VALUE_S  14
+/** PARL_IO_TX_GATING_EN : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to enable the clock gating of output tx clock.
+ */
+#define PARL_IO_TX_GATING_EN    (BIT(30))
+#define PARL_IO_TX_GATING_EN_M  (PARL_IO_TX_GATING_EN_V << PARL_IO_TX_GATING_EN_S)
+#define PARL_IO_TX_GATING_EN_V  0x00000001U
+#define PARL_IO_TX_GATING_EN_S  30
+/** PARL_IO_TX_VALID_OUTPUT_EN : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to enable the output of tx data valid signal.
+ */
+#define PARL_IO_TX_VALID_OUTPUT_EN    (BIT(31))
+#define PARL_IO_TX_VALID_OUTPUT_EN_M  (PARL_IO_TX_VALID_OUTPUT_EN_V << PARL_IO_TX_VALID_OUTPUT_EN_S)
+#define PARL_IO_TX_VALID_OUTPUT_EN_V  0x00000001U
+#define PARL_IO_TX_VALID_OUTPUT_EN_S  31
+
+/** PARL_IO_FIFO_CFG_REG register
+ *  Parallel IO FIFO configuration register.
+ */
+#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
+/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to reset async fifo in tx module.
+ */
+#define PARL_IO_TX_FIFO_SRST    (BIT(30))
+#define PARL_IO_TX_FIFO_SRST_M  (PARL_IO_TX_FIFO_SRST_V << PARL_IO_TX_FIFO_SRST_S)
+#define PARL_IO_TX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_TX_FIFO_SRST_S  30
+/** PARL_IO_RX_FIFO_SRST : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to reset async fifo in rx module.
+ */
+#define PARL_IO_RX_FIFO_SRST    (BIT(31))
+#define PARL_IO_RX_FIFO_SRST_M  (PARL_IO_RX_FIFO_SRST_V << PARL_IO_RX_FIFO_SRST_S)
+#define PARL_IO_RX_FIFO_SRST_V  0x00000001U
+#define PARL_IO_RX_FIFO_SRST_S  31
+
+/** PARL_IO_REG_UPDATE_REG register
+ *  Parallel IO FIFO configuration register.
+ */
+#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
+/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
+ *  Set this bit to update rx register configuration.
+ */
+#define PARL_IO_RX_REG_UPDATE    (BIT(31))
+#define PARL_IO_RX_REG_UPDATE_M  (PARL_IO_RX_REG_UPDATE_V << PARL_IO_RX_REG_UPDATE_S)
+#define PARL_IO_RX_REG_UPDATE_V  0x00000001U
+#define PARL_IO_RX_REG_UPDATE_S  31
+
+/** PARL_IO_ST_REG register
+ *  Parallel IO module status register0.
+ */
+#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
+/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
+ *  Represents the status that tx is ready to transmit.
+ */
+#define PARL_IO_TX_READY    (BIT(31))
+#define PARL_IO_TX_READY_M  (PARL_IO_TX_READY_V << PARL_IO_TX_READY_S)
+#define PARL_IO_TX_READY_V  0x00000001U
+#define PARL_IO_TX_READY_S  31
+
+/** PARL_IO_INT_ENA_REG register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_M  (PARL_IO_TX_FIFO_REMPTY_INT_ENA_V << PARL_IO_TX_FIFO_REMPTY_INT_ENA_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ENA_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_M  (PARL_IO_RX_FIFO_WOVF_INT_ENA_V << PARL_IO_RX_FIFO_WOVF_INT_ENA_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_ENA_S  1
+/** PARL_IO_TX_EOF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_ENA    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ENA_M  (PARL_IO_TX_EOF_INT_ENA_V << PARL_IO_TX_EOF_INT_ENA_S)
+#define PARL_IO_TX_EOF_INT_ENA_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ENA_S  2
+
+/** PARL_IO_INT_RAW_REG register
+ *  Parallel IO interrupt raw signal status register.
+ */
+#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
+/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_M  (PARL_IO_TX_FIFO_REMPTY_INT_RAW_V << PARL_IO_TX_FIFO_REMPTY_INT_RAW_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_RAW_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_M  (PARL_IO_RX_FIFO_WOVF_INT_RAW_V << PARL_IO_RX_FIFO_WOVF_INT_RAW_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_RAW_S  1
+/** PARL_IO_TX_EOF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_RAW    (BIT(2))
+#define PARL_IO_TX_EOF_INT_RAW_M  (PARL_IO_TX_EOF_INT_RAW_V << PARL_IO_TX_EOF_INT_RAW_S)
+#define PARL_IO_TX_EOF_INT_RAW_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_RAW_S  2
+
+/** PARL_IO_INT_ST_REG register
+ *  Parallel IO interrupt signal status register.
+ */
+#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
+/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_M  (PARL_IO_TX_FIFO_REMPTY_INT_ST_V << PARL_IO_TX_FIFO_REMPTY_INT_ST_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_ST_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_ST    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_M  (PARL_IO_RX_FIFO_WOVF_INT_ST_V << PARL_IO_RX_FIFO_WOVF_INT_ST_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_ST_S  1
+/** PARL_IO_TX_EOF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_ST    (BIT(2))
+#define PARL_IO_TX_EOF_INT_ST_M  (PARL_IO_TX_EOF_INT_ST_V << PARL_IO_TX_EOF_INT_ST_S)
+#define PARL_IO_TX_EOF_INT_ST_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_ST_S  2
+
+/** PARL_IO_INT_CLR_REG register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
+/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear TX_FIFO_REMPTY_INT.
+ */
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR    (BIT(0))
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_M  (PARL_IO_TX_FIFO_REMPTY_INT_CLR_V << PARL_IO_TX_FIFO_REMPTY_INT_CLR_S)
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_FIFO_REMPTY_INT_CLR_S  0
+/** PARL_IO_RX_FIFO_WOVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear RX_FIFO_WOVF_INT.
+ */
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR    (BIT(1))
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_M  (PARL_IO_RX_FIFO_WOVF_INT_CLR_V << PARL_IO_RX_FIFO_WOVF_INT_CLR_S)
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_V  0x00000001U
+#define PARL_IO_RX_FIFO_WOVF_INT_CLR_S  1
+/** PARL_IO_TX_EOF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear TX_EOF_INT.
+ */
+#define PARL_IO_TX_EOF_INT_CLR    (BIT(2))
+#define PARL_IO_TX_EOF_INT_CLR_M  (PARL_IO_TX_EOF_INT_CLR_V << PARL_IO_TX_EOF_INT_CLR_S)
+#define PARL_IO_TX_EOF_INT_CLR_V  0x00000001U
+#define PARL_IO_TX_EOF_INT_CLR_S  2
+
+/** PARL_IO_RX_ST0_REG register
+ *  Parallel IO RX status register0
+ */
+#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
+/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
+ *  Indicates the cycle number of reading Rx FIFO.
+ */
+#define PARL_IO_RX_CNT    0x0000001FU
+#define PARL_IO_RX_CNT_M  (PARL_IO_RX_CNT_V << PARL_IO_RX_CNT_S)
+#define PARL_IO_RX_CNT_V  0x0000001FU
+#define PARL_IO_RX_CNT_S  8
+/** PARL_IO_RX_FIFO_WR_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current written bit number into Rx FIFO.
+ */
+#define PARL_IO_RX_FIFO_WR_BIT_CNT    0x0007FFFFU
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_M  (PARL_IO_RX_FIFO_WR_BIT_CNT_V << PARL_IO_RX_FIFO_WR_BIT_CNT_S)
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_RX_FIFO_WR_BIT_CNT_S  13
+
+/** PARL_IO_RX_ST1_REG register
+ *  Parallel IO RX status register1
+ */
+#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
+/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current read bit number from Rx FIFO.
+ */
+#define PARL_IO_RX_FIFO_RD_BIT_CNT    0x0007FFFFU
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_M  (PARL_IO_RX_FIFO_RD_BIT_CNT_V << PARL_IO_RX_FIFO_RD_BIT_CNT_S)
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_RX_FIFO_RD_BIT_CNT_S  13
+
+/** PARL_IO_TX_ST0_REG register
+ *  Parallel IO TX status register0
+ */
+#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
+/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
+ *  Indicates the cycle number of reading Tx FIFO.
+ */
+#define PARL_IO_TX_CNT    0x0000007FU
+#define PARL_IO_TX_CNT_M  (PARL_IO_TX_CNT_V << PARL_IO_TX_CNT_S)
+#define PARL_IO_TX_CNT_V  0x0000007FU
+#define PARL_IO_TX_CNT_S  6
+/** PARL_IO_TX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
+ *  Indicates the current read bit number from Tx FIFO.
+ */
+#define PARL_IO_TX_FIFO_RD_BIT_CNT    0x0007FFFFU
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_M  (PARL_IO_TX_FIFO_RD_BIT_CNT_V << PARL_IO_TX_FIFO_RD_BIT_CNT_S)
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_V  0x0007FFFFU
+#define PARL_IO_TX_FIFO_RD_BIT_CNT_S  13
+
+/** PARL_IO_RX_CLK_CFG_REG register
+ *  Parallel IO RX clk configuration register
+ */
+#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
+/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to invert the input Rx core clock.
+ */
+#define PARL_IO_RX_CLK_I_INV    (BIT(30))
+#define PARL_IO_RX_CLK_I_INV_M  (PARL_IO_RX_CLK_I_INV_V << PARL_IO_RX_CLK_I_INV_S)
+#define PARL_IO_RX_CLK_I_INV_V  0x00000001U
+#define PARL_IO_RX_CLK_I_INV_S  30
+/** PARL_IO_RX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to invert the output Rx core clock.
+ */
+#define PARL_IO_RX_CLK_O_INV    (BIT(31))
+#define PARL_IO_RX_CLK_O_INV_M  (PARL_IO_RX_CLK_O_INV_V << PARL_IO_RX_CLK_O_INV_S)
+#define PARL_IO_RX_CLK_O_INV_V  0x00000001U
+#define PARL_IO_RX_CLK_O_INV_S  31
+
+/** PARL_IO_TX_CLK_CFG_REG register
+ *  Parallel IO TX clk configuration register
+ */
+#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
+/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
+ *  Set this bit to invert the input Tx core clock.
+ */
+#define PARL_IO_TX_CLK_I_INV    (BIT(30))
+#define PARL_IO_TX_CLK_I_INV_M  (PARL_IO_TX_CLK_I_INV_V << PARL_IO_TX_CLK_I_INV_S)
+#define PARL_IO_TX_CLK_I_INV_V  0x00000001U
+#define PARL_IO_TX_CLK_I_INV_S  30
+/** PARL_IO_TX_CLK_O_INV : R/W; bitpos: [31]; default: 0;
+ *  Set this bit to invert the output Tx core clock.
+ */
+#define PARL_IO_TX_CLK_O_INV    (BIT(31))
+#define PARL_IO_TX_CLK_O_INV_M  (PARL_IO_TX_CLK_O_INV_V << PARL_IO_TX_CLK_O_INV_S)
+#define PARL_IO_TX_CLK_O_INV_V  0x00000001U
+#define PARL_IO_TX_CLK_O_INV_S  31
+
+/** PARL_IO_CLK_REG register
+ *  Parallel IO clk configuration register
+ */
+#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
+/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Force clock on for this register file
+ */
+#define PARL_IO_CLK_EN    (BIT(31))
+#define PARL_IO_CLK_EN_M  (PARL_IO_CLK_EN_V << PARL_IO_CLK_EN_S)
+#define PARL_IO_CLK_EN_V  0x00000001U
+#define PARL_IO_CLK_EN_S  31
+
+/** PARL_IO_VERSION_REG register
+ *  Version register.
+ */
+#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
+/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920;
+ *  Version of this register file
+ */
+#define PARL_IO_DATE    0x0FFFFFFFU
+#define PARL_IO_DATE_M  (PARL_IO_DATE_V << PARL_IO_DATE_S)
+#define PARL_IO_DATE_V  0x0FFFFFFFU
+#define PARL_IO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/parl_io_struct.h b/components/soc/esp32p4/register/soc/parl_io_struct.h
new file mode 100644
index 00000000000..7304e7be2c5
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/parl_io_struct.h
@@ -0,0 +1,509 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PARL_IO RX  Mode Configuration */
+/** Type of rx_mode_cfg register
+ *  Parallel RX Sampling mode configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** rx_ext_en_sel : R/W; bitpos: [24:21]; default: 7;
+         *  Configures rx external enable signal selection from IO PAD.
+         */
+        uint32_t rx_ext_en_sel:4;
+        /** rx_sw_en : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to enable data sampling by software.
+         */
+        uint32_t rx_sw_en:1;
+        /** rx_ext_en_inv : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to invert the external enable signal.
+         */
+        uint32_t rx_ext_en_inv:1;
+        /** rx_pulse_submode_sel : R/W; bitpos: [29:27]; default: 0;
+         *  Configures the rxd pulse sampling submode.
+         *  4'd0: positive pulse start(data bit included) &&  positive pulse end(data bit
+         *  included)
+         *  4'd1: positive pulse start(data bit included) && positive pulse end (data bit
+         *  excluded)
+         *  4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit
+         *  included)
+         *  4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit
+         *  excluded)
+         *  4'd4: positive pulse start(data bit included) && length end
+         *  4'd5: positive pulse start(data bit excluded) && length end
+         */
+        uint32_t rx_pulse_submode_sel:3;
+        /** rx_smp_mode_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Configures the rxd sampling mode.
+         *  2'b00: external level enable mode
+         *  2'b01: external pulse enable mode
+         *  2'b10: internal software enable mode
+         */
+        uint32_t rx_smp_mode_sel:2;
+    };
+    uint32_t val;
+} parl_io_rx_mode_cfg_reg_t;
+
+
+/** Group: PARL_IO RX Data Configuration */
+/** Type of rx_data_cfg register
+ *  Parallel RX data configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** rx_bitlen : R/W; bitpos: [27:9]; default: 0;
+         *  Configures expected byte number of received data.
+         */
+        uint32_t rx_bitlen:19;
+        /** rx_data_order_inv : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to invert bit order of one byte sent from RX_FIFO to DMA.
+         */
+        uint32_t rx_data_order_inv:1;
+        /** rx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
+         *  Configures the rxd bus width.
+         *  3'd0: bus width is 1.
+         *  3'd1: bus width is 2.
+         *  3'd2: bus width is 4.
+         *  3'd3: bus width is 8.
+         */
+        uint32_t rx_bus_wid_sel:3;
+    };
+    uint32_t val;
+} parl_io_rx_data_cfg_reg_t;
+
+
+/** Group: PARL_IO RX General Configuration */
+/** Type of rx_genrl_cfg register
+ *  Parallel RX general configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** rx_gating_en : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable the clock gating of output rx clock.
+         */
+        uint32_t rx_gating_en:1;
+        /** rx_timeout_thres : R/W; bitpos: [28:13]; default: 4095;
+         *  Configures threshold of timeout counter.
+         */
+        uint32_t rx_timeout_thres:16;
+        /** rx_timeout_en : R/W; bitpos: [29]; default: 1;
+         *  Set this bit to enable timeout function to generate error eof.
+         */
+        uint32_t rx_timeout_en:1;
+        /** rx_eof_gen_sel : R/W; bitpos: [30]; default: 0;
+         *  Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length.
+         *  1'b1: eof generated by external enable signal.
+         */
+        uint32_t rx_eof_gen_sel:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} parl_io_rx_genrl_cfg_reg_t;
+
+
+/** Group: PARL_IO RX Start Configuration */
+/** Type of rx_start_cfg register
+ *  Parallel RX Start configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** rx_start : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start rx data sampling.
+         */
+        uint32_t rx_start:1;
+    };
+    uint32_t val;
+} parl_io_rx_start_cfg_reg_t;
+
+
+/** Group: PARL_IO TX Data Configuration */
+/** Type of tx_data_cfg register
+ *  Parallel TX data configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** tx_bitlen : R/W; bitpos: [27:9]; default: 0;
+         *  Configures expected byte number of sent data.
+         */
+        uint32_t tx_bitlen:19;
+        /** tx_data_order_inv : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to invert bit order of one byte sent from TX_FIFO to IO data.
+         */
+        uint32_t tx_data_order_inv:1;
+        /** tx_bus_wid_sel : R/W; bitpos: [31:29]; default: 3;
+         *  Configures the txd bus width.
+         *  3'd0: bus width is 1.
+         *  3'd1: bus width is 2.
+         *  3'd2: bus width is 4.
+         *  3'd3: bus width is 8.
+         */
+        uint32_t tx_bus_wid_sel:3;
+    };
+    uint32_t val;
+} parl_io_tx_data_cfg_reg_t;
+
+
+/** Group: PARL_IO TX Start Configuration */
+/** Type of tx_start_cfg register
+ *  Parallel TX Start configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_start : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to start tx data transmit.
+         */
+        uint32_t tx_start:1;
+    };
+    uint32_t val;
+} parl_io_tx_start_cfg_reg_t;
+
+
+/** Group: PARL_IO TX General Configuration */
+/** Type of tx_genrl_cfg register
+ *  Parallel TX general configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** tx_eof_gen_sel : R/W; bitpos: [13]; default: 0;
+         *  Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
+         *  1'b1: eof generated by DMA eof.
+         */
+        uint32_t tx_eof_gen_sel:1;
+        /** tx_idle_value : R/W; bitpos: [29:14]; default: 0;
+         *  Configures bus value of transmitter in IDLE state.
+         */
+        uint32_t tx_idle_value:16;
+        /** tx_gating_en : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to enable the clock gating of output tx clock.
+         */
+        uint32_t tx_gating_en:1;
+        /** tx_valid_output_en : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to enable the output of tx data valid signal.
+         */
+        uint32_t tx_valid_output_en:1;
+    };
+    uint32_t val;
+} parl_io_tx_genrl_cfg_reg_t;
+
+
+/** Group: PARL_IO FIFO Configuration */
+/** Type of fifo_cfg register
+ *  Parallel IO FIFO configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tx_fifo_srst : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to reset async fifo in tx module.
+         */
+        uint32_t tx_fifo_srst:1;
+        /** rx_fifo_srst : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to reset async fifo in rx module.
+         */
+        uint32_t rx_fifo_srst:1;
+    };
+    uint32_t val;
+} parl_io_fifo_cfg_reg_t;
+
+
+/** Group: PARL_IO Register Update Configuration */
+/** Type of reg_update register
+ *  Parallel IO FIFO configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** rx_reg_update : WT; bitpos: [31]; default: 0;
+         *  Set this bit to update rx register configuration.
+         */
+        uint32_t rx_reg_update:1;
+    };
+    uint32_t val;
+} parl_io_reg_update_reg_t;
+
+
+/** Group: PARL_IO Status */
+/** Type of st register
+ *  Parallel IO module status register0.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** tx_ready : RO; bitpos: [31]; default: 0;
+         *  Represents the status that tx is ready to transmit.
+         */
+        uint32_t tx_ready:1;
+    };
+    uint32_t val;
+} parl_io_st_reg_t;
+
+
+/** Group: PARL_IO Interrupt Configuration and Status */
+/** Type of int_ena register
+ *  Parallel IO interrupt enable signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_ena:1;
+        /** rx_fifo_wovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_ena:1;
+        /** tx_eof_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Parallel IO interrupt raw signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_raw:1;
+        /** rx_fifo_wovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_raw:1;
+        /** tx_eof_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Parallel IO interrupt signal status register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_st:1;
+        /** rx_fifo_wovf_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_st:1;
+        /** tx_eof_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Parallel IO interrupt  clear signal configuration register.
+ */
+typedef union {
+    struct {
+        /** tx_fifo_rempty_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear TX_FIFO_REMPTY_INT.
+         */
+        uint32_t tx_fifo_rempty_int_clr:1;
+        /** rx_fifo_wovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear RX_FIFO_WOVF_INT.
+         */
+        uint32_t rx_fifo_wovf_int_clr:1;
+        /** tx_eof_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear TX_EOF_INT.
+         */
+        uint32_t tx_eof_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} parl_io_int_clr_reg_t;
+
+
+/** Group: PARL_IO Rx Status0 */
+/** Type of rx_st0 register
+ *  Parallel IO RX status register0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** rx_cnt : RO; bitpos: [12:8]; default: 0;
+         *  Indicates the cycle number of reading Rx FIFO.
+         */
+        uint32_t rx_cnt:5;
+        /** rx_fifo_wr_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current written bit number into Rx FIFO.
+         */
+        uint32_t rx_fifo_wr_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_rx_st0_reg_t;
+
+
+/** Group: PARL_IO Rx Status1 */
+/** Type of rx_st1 register
+ *  Parallel IO RX status register1
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** rx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current read bit number from Rx FIFO.
+         */
+        uint32_t rx_fifo_rd_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_rx_st1_reg_t;
+
+
+/** Group: PARL_IO Tx Status0 */
+/** Type of tx_st0 register
+ *  Parallel IO TX status register0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** tx_cnt : RO; bitpos: [12:6]; default: 0;
+         *  Indicates the cycle number of reading Tx FIFO.
+         */
+        uint32_t tx_cnt:7;
+        /** tx_fifo_rd_bit_cnt : RO; bitpos: [31:13]; default: 0;
+         *  Indicates the current read bit number from Tx FIFO.
+         */
+        uint32_t tx_fifo_rd_bit_cnt:19;
+    };
+    uint32_t val;
+} parl_io_tx_st0_reg_t;
+
+
+/** Group: PARL_IO Rx Clock Configuration */
+/** Type of rx_clk_cfg register
+ *  Parallel IO RX clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** rx_clk_i_inv : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to invert the input Rx core clock.
+         */
+        uint32_t rx_clk_i_inv:1;
+        /** rx_clk_o_inv : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to invert the output Rx core clock.
+         */
+        uint32_t rx_clk_o_inv:1;
+    };
+    uint32_t val;
+} parl_io_rx_clk_cfg_reg_t;
+
+
+/** Group: PARL_IO Tx Clock Configuration */
+/** Type of tx_clk_cfg register
+ *  Parallel IO TX clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** tx_clk_i_inv : R/W; bitpos: [30]; default: 0;
+         *  Set this bit to invert the input Tx core clock.
+         */
+        uint32_t tx_clk_i_inv:1;
+        /** tx_clk_o_inv : R/W; bitpos: [31]; default: 0;
+         *  Set this bit to invert the output Tx core clock.
+         */
+        uint32_t tx_clk_o_inv:1;
+    };
+    uint32_t val;
+} parl_io_tx_clk_cfg_reg_t;
+
+
+/** Group: PARL_IO Clock Configuration */
+/** Type of clk register
+ *  Parallel IO clk configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} parl_io_clk_reg_t;
+
+
+/** Group: PARL_IO Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35725920;
+         *  Version of this register file
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} parl_io_version_reg_t;
+
+
+typedef struct parl_io_dev_t {
+    volatile parl_io_rx_mode_cfg_reg_t rx_mode_cfg;
+    volatile parl_io_rx_data_cfg_reg_t rx_data_cfg;
+    volatile parl_io_rx_genrl_cfg_reg_t rx_genrl_cfg;
+    volatile parl_io_rx_start_cfg_reg_t rx_start_cfg;
+    volatile parl_io_tx_data_cfg_reg_t tx_data_cfg;
+    volatile parl_io_tx_start_cfg_reg_t tx_start_cfg;
+    volatile parl_io_tx_genrl_cfg_reg_t tx_genrl_cfg;
+    volatile parl_io_fifo_cfg_reg_t fifo_cfg;
+    volatile parl_io_reg_update_reg_t reg_update;
+    volatile parl_io_st_reg_t st;
+    volatile parl_io_int_ena_reg_t int_ena;
+    volatile parl_io_int_raw_reg_t int_raw;
+    volatile parl_io_int_st_reg_t int_st;
+    volatile parl_io_int_clr_reg_t int_clr;
+    volatile parl_io_rx_st0_reg_t rx_st0;
+    volatile parl_io_rx_st1_reg_t rx_st1;
+    volatile parl_io_tx_st0_reg_t tx_st0;
+    volatile parl_io_rx_clk_cfg_reg_t rx_clk_cfg;
+    volatile parl_io_tx_clk_cfg_reg_t tx_clk_cfg;
+    uint32_t reserved_04c[53];
+    volatile parl_io_clk_reg_t clk;
+    uint32_t reserved_124[182];
+    volatile parl_io_version_reg_t version;
+} parl_io_dev_t;
+
+extern parl_io_dev_t PARL_IO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(parl_io_dev_t) == 0x400, "Invalid size of parl_io_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/pau_reg.h b/components/soc/esp32p4/register/soc/pau_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/pau_reg.h
rename to components/soc/esp32p4/register/soc/pau_reg.h
diff --git a/components/soc/esp32p4/include/soc/pau_struct.h b/components/soc/esp32p4/register/soc/pau_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/pau_struct.h
rename to components/soc/esp32p4/register/soc/pau_struct.h
diff --git a/components/soc/esp32p4/include/soc/pcnt_reg.h b/components/soc/esp32p4/register/soc/pcnt_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/pcnt_reg.h
rename to components/soc/esp32p4/register/soc/pcnt_reg.h
diff --git a/components/soc/esp32p4/include/soc/pcnt_struct.h b/components/soc/esp32p4/register/soc/pcnt_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/pcnt_struct.h
rename to components/soc/esp32p4/register/soc/pcnt_struct.h
diff --git a/components/soc/esp32p4/include/soc/pmu_reg.h b/components/soc/esp32p4/register/soc/pmu_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/pmu_reg.h
rename to components/soc/esp32p4/register/soc/pmu_reg.h
diff --git a/components/soc/esp32p4/register/soc/pmu_struct.h b/components/soc/esp32p4/register/soc/pmu_struct.h
new file mode 100644
index 00000000000..d8936af001e
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/pmu_struct.h
@@ -0,0 +1,940 @@
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/pmu_reg.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t dcdc_switch_pd_en :1;
+        uint32_t mem_dslp     : 1;
+        uint32_t mem_pd_en    : 1;
+        uint32_t reserved1    : 6;
+        uint32_t cnnt_pd_en   : 1;
+        uint32_t top_pd_en    : 1;
+    };
+    uint32_t val;
+} pmu_hp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 23;
+        uint32_t power_det_bypass : 1;
+        uint32_t uart_wakeup_en : 1;
+        uint32_t lp_pad_hold_all: 1;
+        uint32_t hp_pad_hold_all: 1;
+        uint32_t dig_pad_slp_sel: 1;
+        uint32_t dig_pause_wdt  : 1;
+        uint32_t dig_cpu_stall  : 1;
+        uint32_t reserved1      : 2;
+    };
+    uint32_t val;
+} pmu_hp_sys_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0    : 21;
+        uint32_t i2c_iso_en   : 1;
+        uint32_t i2c_retention: 1;
+        uint32_t xpd_pll_i2c  : 4;
+        uint32_t xpd_pll      : 4;
+        uint32_t reserved1    : 1;
+    };
+    uint32_t val;
+} pmu_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 18;
+        uint32_t dcm_vset  : 5;
+        uint32_t dcm_mode  : 2;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_hp_bias_reg_t;
+
+typedef union {
+    struct {    /* HP: Active State */
+        uint32_t reserved0                            : 4;
+        uint32_t hp_sleep2active_backup_modem_clk_code: 2;
+        uint32_t hp_modem2active_backup_modem_clk_code: 2;
+        uint32_t reserved1                            : 2;
+        uint32_t hp_active_retention_mode             : 1;
+        uint32_t hp_sleep2active_retention_en         : 1;
+        uint32_t hp_modem2active_retention_en         : 1;
+        uint32_t reserved2                            : 1;
+        uint32_t hp_sleep2active_backup_clk_sel       : 2;
+        uint32_t hp_modem2active_backup_clk_sel       : 2;
+        uint32_t reserved3                            : 2;
+        uint32_t hp_sleep2active_backup_mode          : 3;
+        uint32_t hp_modem2active_backup_mode          : 3;
+        uint32_t reserved4                            : 3;
+        uint32_t hp_sleep2active_backup_en            : 1;
+        uint32_t hp_modem2active_backup_en            : 1;
+        uint32_t reserved5                            : 1;
+    };
+    struct {    /* HP: Modem State */
+        uint32_t reserved6                            : 32;
+    };
+    struct {    /* HP: Sleep State */
+        uint32_t reserved12                           : 6;
+        uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
+        uint32_t hp_active2sleep_backup_modem_clk_code: 2;
+        uint32_t hp_sleep_retention_mode              : 1;
+        uint32_t reserved13                           : 1;
+        uint32_t hp_modem2sleep_retention_en          : 1;
+        uint32_t hp_active2sleep_retention_en         : 1;
+        uint32_t reserved14                           : 2;
+        uint32_t hp_modem2sleep_backup_clk_sel        : 2;
+        uint32_t hp_active2sleep_backup_clk_sel       : 2;
+        uint32_t reserved15                           : 3;
+        uint32_t hp_modem2sleep_backup_mode           : 3;
+        uint32_t hp_active2sleep_backup_mode          : 3;
+        uint32_t reserved16                           : 1;
+        uint32_t hp_modem2sleep_backup_en             : 1;
+        uint32_t hp_active2sleep_backup_en            : 1;
+    };
+    uint32_t val;
+} pmu_hp_backup_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0       : 26;
+        uint32_t dig_sysclk_nodiv: 1;
+        uint32_t icg_sysclk_en   : 1;
+        uint32_t sysclk_slp_sel  : 1;
+        uint32_t icg_slp_sel     : 1;
+        uint32_t dig_sysclk_sel  : 2;
+    };
+    uint32_t val;
+} pmu_hp_sysclk_reg_t;
+
+typedef union {
+    // For chip_revsion < 1.0
+    struct {
+        uint32_t reserved0      : 4;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t lp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t hp_dbias_vol   : 5;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_sel      : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t dbias_init     : 1;    /* Only HP_ACTIVE modem under hp system is valid */
+        uint32_t slp_mem_xpd    : 1;
+        uint32_t slp_logic_xpd  : 1;
+        uint32_t xpd            : 1;
+        uint32_t slp_mem_dbias  : 4;    /* slp_mem_dbias is not used on chip_revision < 100 */
+        uint32_t slp_logic_dbias: 4;
+        uint32_t dbias          : 5;
+    };
+    // For chip revision >= 100
+    struct {
+        uint32_t reserved1      : 19;
+        uint32_t xpd_0p1a       : 4;    /* slp_mem_dbias[3] is used to control the volt output of VO1 on chip_revision >= 1.0 */
+        uint32_t reserved2      : 9;
+    };
+    uint32_t val;
+} pmu_hp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 26;
+        uint32_t drv_b    : 6;
+    };
+    uint32_t val;
+} pmu_hp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_hp_xtal_reg_t;
+
+typedef struct pmu_hp_hw_regmap_t {
+    pmu_hp_dig_power_reg_t     dig_power;
+    uint32_t                   icg_func;
+    uint32_t                   icg_apb;
+    uint32_t                   icg_modem;
+    pmu_hp_sys_cntl_reg_t      syscntl;
+    pmu_hp_clk_power_reg_t     clk_power;
+    pmu_hp_bias_reg_t          bias;
+    pmu_hp_backup_reg_t        backup;
+    uint32_t                   backup_clk;
+    pmu_hp_sysclk_reg_t        sysclk;
+    pmu_hp_regulator0_reg_t    regulator0;
+    pmu_hp_regulator1_reg_t    regulator1;
+    pmu_hp_xtal_reg_t          xtal;
+} pmu_hp_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 21;
+        uint32_t slp_xpd  : 1;
+        uint32_t xpd      : 1;
+        uint32_t slp_dbias: 4;
+        uint32_t dbias    : 5;
+    };
+    uint32_t val;
+} pmu_lp_regulator0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 26;
+        uint32_t drv_b    : 6;
+    };
+    uint32_t val;
+} pmu_lp_regulator1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t xpd_xtal : 1;
+    };
+    uint32_t val;
+} pmu_lp_xtal_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 26;
+        uint32_t lp_pad_slp_sel : 1;
+        uint32_t bod_source_sel : 1;
+        uint32_t vddbat_mode : 2;
+        uint32_t mem_dslp  : 1;
+        uint32_t peri_pd_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_dig_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0  : 27;
+        uint32_t xpd_lppll  : 1;
+        uint32_t xpd_xtal32k: 1;
+        uint32_t xpd_rc32k  : 1;
+        uint32_t xpd_fosc   : 1;
+        uint32_t pd_osc     : 1;
+    };
+    uint32_t val;
+} pmu_lp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0 : 25;
+        uint32_t xpd_bias  : 1;
+        uint32_t dbg_atten : 4;
+        uint32_t pd_cur    : 1;
+        uint32_t bias_sleep: 1;
+    };
+    uint32_t val;
+} pmu_lp_bias_reg_t;
+
+typedef struct pmu_lp_hw_regmap_t {
+    pmu_lp_regulator0_reg_t    regulator0;
+    pmu_lp_regulator1_reg_t    regulator1;
+    pmu_lp_xtal_reg_t          xtal;   /* Only LP_SLEEP mode under lp system is valid */
+    pmu_lp_dig_power_reg_t     dig_power;
+    pmu_lp_clk_power_reg_t     clk_power;
+    pmu_lp_bias_reg_t          bias;   /* Only LP_SLEEP mode under lp system is valid */
+} pmu_lp_hw_regmap_t;
+
+
+typedef union {
+    struct {
+        uint32_t tie_low_cali_xtal_icg      : 1;
+        uint32_t tie_low_global_pll_icg     : 4;
+        uint32_t tie_low_global_xtal_icg    : 1;
+        uint32_t tie_low_i2c_retention      : 1;
+        uint32_t tie_low_xpd_pll_i2c        : 4;
+        uint32_t tie_low_xpd_pll            : 4;
+        uint32_t tie_low_xpd_xtal           : 1;
+        uint32_t tie_high_cali_xtal_icg     : 1;
+        uint32_t tie_high_global_pll_icg    : 4;
+        uint32_t tie_high_global_xtal_icg   : 1;
+        uint32_t tie_high_i2c_retention     : 1;
+        uint32_t tie_high_xpd_pll_i2c       : 4;
+        uint32_t tie_high_xpd_pll           : 4;
+        uint32_t tie_high_xpd_xtal          : 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_clk_power_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 28;
+        uint32_t update_dig_icg_switch: 1;
+        uint32_t tie_low_icg_slp_sel  : 1;
+        uint32_t tie_high_icg_slp_sel : 1;
+        uint32_t update_dig_sysclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_sleep_sysclk_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0             : 31;
+        uint32_t update_dig_icg_func_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_func_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0            : 31;
+        uint32_t update_dig_icg_apb_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_hp_apb_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 31;
+        uint32_t update_dig_icg_modem_en: 1;
+    };
+    uint32_t val;
+} pmu_imm_modem_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0              : 30;
+        uint32_t tie_low_lp_rootclk_sel : 1;
+        uint32_t tie_high_lp_rootclk_sel: 1;
+    };
+    uint32_t val;
+} pmu_imm_lp_icg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pad_slp_sel             : 1;
+        uint32_t lp_pad_hold_all         : 1;
+        uint32_t hp_pad_hold_all         : 1;
+        uint32_t reserved0               : 23;
+        uint32_t tie_high_pad_slp_sel    : 1;
+        uint32_t tie_low_pad_slp_sel     : 1;
+        uint32_t tie_high_lp_pad_hold_all: 1;
+        uint32_t tie_low_lp_pad_hold_all : 1;
+        uint32_t tie_high_hp_pad_hold_all: 1;
+        uint32_t tie_low_hp_pad_hold_all : 1;
+    };
+    uint32_t val;
+} pmu_imm_pad_hold_all_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 30;
+        uint32_t tie_high_i2c_iso_en: 1;
+        uint32_t tie_low_i2c_iso_en : 1;
+    };
+    uint32_t val;
+} pmu_imm_i2c_isolate_reg_t;
+
+typedef struct pmu_imm_hw_regmap_t {
+    pmu_imm_hp_clk_power_reg_t     clk_power;
+    pmu_imm_sleep_sysclk_reg_t     sleep_sysclk;
+    pmu_imm_hp_func_icg_reg_t      hp_func_icg;
+    pmu_imm_hp_apb_icg_reg_t       hp_apb_icg;
+    pmu_imm_modem_icg_reg_t        modem_icg;
+    pmu_imm_lp_icg_reg_t           lp_icg;
+    pmu_imm_pad_hold_all_reg_t     pad_hold_all;
+    pmu_imm_i2c_isolate_reg_t      i2c_iso;
+} pmu_imm_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t powerdown_timer: 9;
+        uint32_t powerup_timer  : 9;
+        uint32_t wait_timer     : 9;
+    };
+    uint32_t val;
+} pmu_power_wait_timer1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_reset   : 1;
+        uint32_t force_iso     : 1;
+        uint32_t force_pu      : 1;
+        uint32_t force_no_reset: 1;
+        uint32_t force_no_iso  : 1;
+        uint32_t force_pd      : 1;
+        uint32_t reserved0     : 26;    /* Invalid of lp peripherals */
+    };
+    uint32_t val;
+} pmu_power_domain_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pd_top_mask   : 5;
+        uint32_t reserved0     : 22;    /* Invalid of lp peripherals */
+        uint32_t top_pd_mask   : 5;
+    };
+    uint32_t val;
+} pmu_power_domain_mask_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_pu      :    1;
+        uint32_t force_pd      :    1;
+        uint32_t reserved2     :    30;
+    };
+    uint32_t val;
+} pmu_power_dcdc_switch_reg_t;
+
+typedef union {
+    struct {
+        uint32_t force_hp_pad_no_iso_all: 1;
+        uint32_t force_hp_pad_iso_all   : 1;
+        uint32_t reserved0              : 30;
+    };
+    uint32_t val;
+} pmu_power_hp_pad_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wait_xtal_stable: 16;
+        uint32_t wait_pll_stable : 16;
+    };
+    uint32_t val;
+} pmu_power_clk_wait_cntl_reg_t;
+
+typedef struct pmu_power_hw_regmap_t {
+    pmu_power_wait_timer0_reg_t    wait_timer0;
+    pmu_power_wait_timer1_reg_t    wait_timer1;
+    pmu_power_domain_cntl_reg_t    hp_pd[3];
+    pmu_power_domain_mask_reg_t    hp_pd_mask[3];
+    pmu_power_dcdc_switch_reg_t    dcdc_switch;
+    pmu_power_domain_cntl_reg_t    lp_peri;
+    pmu_power_domain_mask_reg_t    lp_peri_mask;
+    pmu_power_hp_pad_reg_t         hp_pad;
+    pmu_power_clk_wait_cntl_reg_t  clk_wait;
+} pmu_power_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_ena: 31;
+        uint32_t slp_reject_en   : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_ena: 31;
+        uint32_t reserved0 : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl2_reg_t;
+
+typedef union {
+    struct {
+        uint32_t lp_min_slp_val: 8;
+        uint32_t hp_min_slp_val: 8;
+        uint32_t sleep_prt_sel : 2;
+        uint32_t reserved0     : 14;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0           : 31;
+        uint32_t slp_reject_cause_clr: 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modem_wait_target : 20;
+        uint32_t reserved0         : 4;
+        uint32_t lp_ana_wait_target: 8;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl5_reg_t;
+
+typedef union {
+    struct {
+        uint32_t soc_wakeup_wait    : 20;
+        uint32_t reserved0          : 10;
+        uint32_t soc_wakeup_wait_cfg: 2;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl6_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 16;
+        uint32_t ana_wait_target: 16;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl7_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t lp_lite_wakeup_ena : 1;
+    };
+    uint32_t val;
+} pmu_slp_wakeup_cntl8_reg_t;
+
+typedef struct pmu_wakeup_hw_regmap_t {
+    pmu_slp_wakeup_cntl0_reg_t     cntl0;
+    pmu_slp_wakeup_cntl1_reg_t     cntl1;
+    pmu_slp_wakeup_cntl2_reg_t     cntl2;
+    pmu_slp_wakeup_cntl3_reg_t     cntl3;
+    pmu_slp_wakeup_cntl4_reg_t     cntl4;
+    pmu_slp_wakeup_cntl5_reg_t     cntl5;
+    pmu_slp_wakeup_cntl6_reg_t     cntl6;
+    pmu_slp_wakeup_cntl7_reg_t     cntl7;
+    pmu_slp_wakeup_cntl8_reg_t     cntl8;
+    uint32_t                       status0;
+    uint32_t                       status1;
+    uint32_t                       status2;
+} pmu_wakeup_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t i2c_por_wait_target: 8;
+        uint32_t reserved0          : 24;
+    };
+    uint32_t val;
+} pmu_hp_clk_poweron_reg_t;
+
+typedef union {
+    struct {
+        uint32_t modify_icg_cntl_wait: 8;
+        uint32_t switch_icg_cntl_wait: 8;
+        uint32_t reserved0           : 16;
+    };
+    uint32_t val;
+} pmu_hp_clk_cntl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t por_done : 1;
+    };
+    uint32_t val;
+} pmu_por_status_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0     : 24;
+        uint32_t mspi_phy_xpd  : 1;
+        uint32_t sdio_pll_xpd  : 1;
+        uint32_t perif_i2c_rstb: 1;
+        uint32_t xpd_perif_i2c : 1;
+        uint32_t xpd_txrf_i2c  : 1;
+        uint32_t xpd_rfrx_pbus : 1;
+        uint32_t xpd_ckgen_i2c : 1;
+        uint32_t reserved1     : 1;
+    };
+    uint32_t val;
+} pmu_rf_pwc_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0          : 31;
+        uint32_t backup_sysclk_nodiv: 1;
+    };
+    uint32_t val;
+} pmu_backup_cfg_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0   : 14;
+        uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
+        uint32_t reserved1   : 1;
+        uint32_t lp_exception: 1;
+        uint32_t sdio_idle: 1;
+        uint32_t sw       : 1;
+        uint32_t reject   : 1;
+        uint32_t wakeup   : 1;
+    };
+    uint32_t val;
+} pmu_hp_intr_reg_t;
+
+typedef struct pmu_hp_ext_hw_regmap_t {
+    pmu_hp_clk_poweron_reg_t   clk_poweron;
+    pmu_hp_clk_cntl_reg_t      clk_cntl;
+    pmu_por_status_reg_t       por_status;
+    pmu_rf_pwc_reg_t           rf_pwc;
+    pmu_backup_cfg_reg_t       backup_cfg;
+    pmu_hp_intr_reg_t          int_raw;
+    pmu_hp_intr_reg_t          int_st;
+    pmu_hp_intr_reg_t          int_ena;
+    pmu_hp_intr_reg_t          int_clr;
+} pmu_hp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0                    : 13;
+        uint32_t sleep_reject                 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p1a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p1a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p2a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p2a_cnt_target1_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_0 : 1;
+        uint32_t pmu_0p3a_cnt_target0_reach_1 : 1;
+        uint32_t pmu_0p3a_cnt_target1_reach_1 : 1;
+        uint32_t lp_wakeup                    : 1;
+        uint32_t sleep_switch_active_end      : 1;
+        uint32_t active_switch_sleep_end      : 1;
+        uint32_t sleep_switch_active_start    : 1;
+        uint32_t active_switch_sleep_start    : 1;
+        uint32_t hp_sw_trigger                : 1;
+    };
+    uint32_t val;
+} pmu_lp_intr_reg_t;
+
+typedef union {
+    struct {
+        uint32_t waiti_rdy         : 1;
+        uint32_t stall_rdy         : 1;
+        uint32_t reserved0         : 16;
+        uint32_t force_stall       : 1;
+        uint32_t slp_waiti_flag_en : 1;
+        uint32_t slp_stall_flag_en : 1;
+        uint32_t slp_stall_wait    : 8;
+        uint32_t slp_stall_en      : 1;
+        uint32_t slp_reset_en      : 1;
+        uint32_t slp_bypass_intr_en: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr0_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0: 31;
+        uint32_t sleep_req: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr1_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_en: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr2_reg_t;
+
+typedef union {
+    struct {
+        uint32_t wakeup_cause: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr3_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr4_reg_t;
+
+typedef union {
+    struct {
+        uint32_t sleep_reject_cause: 31;
+        uint32_t reserved0: 1;
+    };
+    uint32_t val;
+} pmu_lp_cpu_pwr5_reg_t;
+
+typedef struct pmu_lp_ext_hw_regmap_t {
+    pmu_lp_intr_reg_t          int_raw;
+    pmu_lp_intr_reg_t          int_st;
+    pmu_lp_intr_reg_t          int_ena;
+    pmu_lp_intr_reg_t          int_clr;
+    pmu_lp_cpu_pwr0_reg_t      pwr0;
+    pmu_lp_cpu_pwr1_reg_t      pwr1;
+    pmu_lp_cpu_pwr2_reg_t      pwr2;
+    pmu_lp_cpu_pwr3_reg_t      pwr3;
+    pmu_lp_cpu_pwr4_reg_t      pwr4;
+    pmu_lp_cpu_pwr5_reg_t      pwr5;
+} pmu_lp_ext_hw_regmap_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:7;
+        uint32_t force_tieh_sel:1;
+        uint32_t xpd:1;
+        uint32_t tieh_sel:3;
+        uint32_t tieh_pos_en:1;
+        uint32_t tieh_neg_en:1;
+        uint32_t tieh:1;
+        uint32_t target1:8;
+        uint32_t target0:8;
+        uint32_t ldo_cnt_prescaler_sel:1;
+    };
+    uint32_t val;
+} pmu_ext_ldo_reg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        uint32_t mul:3;
+        uint32_t en_vdet:1;
+        uint32_t en_cur_lim:1;
+        uint32_t dref:4;
+    };
+    uint32_t val;
+} pmu_ext_ldo_ana_reg_t;
+
+
+typedef struct pmu_ext_ldo_info_t {
+    pmu_ext_ldo_reg_t pmu_ext_ldo;
+    pmu_ext_ldo_ana_reg_t pmu_ext_ldo_ana;
+} pmu_ext_ldo_info_t;
+
+
+typedef union {
+    struct {
+        uint32_t on_req        : 1;
+        uint32_t off_req       : 1;
+        uint32_t lightslp_req  : 1;
+        uint32_t deepslp_req   : 1;
+        uint32_t reserved0     : 3;
+        uint32_t done_force    : 1;
+        uint32_t on_force_pu   : 1;
+        uint32_t on_force_pd   : 1;
+        uint32_t fb_res_force_pu   : 1;
+        uint32_t fb_res_force_pd   : 1;
+        uint32_t ls_force_pu   : 1;
+        uint32_t ls_force_pd   : 1;
+        uint32_t ds_force_pu   : 1;
+        uint32_t ds_force_pd   : 1;
+        uint32_t dcm_cur_st    : 8;
+        uint32_t reserved1     : 5;
+        uint32_t en_amux_test  : 1;
+        uint32_t reserved2     : 2;
+    };
+    uint32_t val;
+} pmu_dcm_ctrl_reg_t;
+
+typedef union {
+    struct {
+        uint32_t pre_delay      : 8;
+        uint32_t res_off_delay  : 8;
+        uint32_t stable_delay   : 10;
+        uint32_t reserved0      : 6;
+    };
+    uint32_t val;
+} pmu_dcm_wait_delay_t;
+
+typedef union {
+    struct {
+        uint32_t module     : 2;
+        uint32_t reserved1  : 29;
+        uint32_t sw_update  : 1;
+    };
+    uint32_t val;
+} pmu_vddbat_cfg_t;
+
+typedef union {
+    struct {
+        uint32_t reserved0      : 5;
+        uint32_t wait_cycles    : 9;
+        uint32_t sleep_cycles   : 16;
+        uint32_t force_done     : 1;
+        uint32_t sleep_timer_en : 1;
+    };
+    uint32_t val;
+} pmu_touch_sensor_pwr_cntl_t;
+
+typedef struct pmu_dev_t {
+    volatile pmu_hp_hw_regmap_t     hp_sys[3];
+    volatile pmu_lp_hw_regmap_t     lp_sys[2];
+    volatile pmu_imm_hw_regmap_t    imm;
+    volatile pmu_power_hw_regmap_t  power;
+    volatile pmu_wakeup_hw_regmap_t wakeup;
+    volatile pmu_hp_ext_hw_regmap_t hp_ext;
+    volatile pmu_lp_ext_hw_regmap_t lp_ext;
+
+    union {
+        struct {
+            volatile uint32_t reserved0    : 30;
+            volatile uint32_t lp_trigger_hp: 1;
+            volatile uint32_t hp_trigger_lp: 1;
+        };
+        volatile uint32_t val;
+    } hp_lp_cpu_comm;
+
+    union {
+        struct {
+            volatile uint32_t reserved0           : 31;
+            volatile uint32_t dig_regulator_en_cal: 1;
+        };
+        volatile uint32_t val;
+    } hp_regulator_cfg;
+
+    union {
+        struct {
+            volatile uint32_t en_cali_pmu_cntl : 1;
+            volatile uint32_t reserved0 : 10;
+            volatile uint32_t last_st   : 7;
+            volatile uint32_t target_st : 7;
+            volatile uint32_t current_st: 7;
+        };
+        volatile uint32_t val;
+    } main_state;
+
+    union {
+        struct {
+            volatile uint32_t reserved0: 13;
+            volatile uint32_t backup_st: 5;
+            volatile uint32_t lp_pwr_st: 5;
+            volatile uint32_t hp_pwr_st: 9;
+        };
+        volatile int32_t val;
+    } pwr_state;
+
+    union {
+        struct {
+            volatile uint32_t stable_xpd_bbpll : 3;
+            volatile uint32_t stable_xpd_xtal  : 1;
+            volatile uint32_t ana_xpd_pll_i2c  : 3;
+            volatile uint32_t reserved0        : 3;
+            volatile uint32_t sysclk_slp_sel   : 1;
+            volatile uint32_t sysclk_sel       : 2;
+            volatile uint32_t sysclk_nodiv     : 1;
+            volatile uint32_t icg_sysclk_en    : 1;
+            volatile uint32_t icg_modem_switch : 1;
+            volatile uint32_t icg_modem_code   : 2;
+            volatile uint32_t icg_slp_sel      : 1;
+            volatile uint32_t icg_global_xtal  : 1;
+            volatile uint32_t icg_global_pll   : 4;
+            volatile uint32_t ana_i2c_iso_en   : 1;
+            volatile uint32_t ana_i2c_retention: 1;
+            volatile uint32_t reserved1        : 1;
+            volatile uint32_t ana_xpd_pll      : 4;
+            volatile uint32_t ana_xpd_xtal     : 1;
+        };
+        volatile uint32_t val;
+    } clk_state0;
+
+    volatile uint32_t clk_state1;
+    volatile uint32_t clk_state2;
+
+    volatile pmu_ext_ldo_info_t ext_ldo[6];
+
+    volatile uint32_t ext_wakeup_lv;
+    volatile uint32_t ext_wakeup_sel;
+    volatile uint32_t ext_wakeup_st;
+    union {
+        struct {
+            volatile uint32_t reserved0      : 30;
+            volatile uint32_t status_clr     : 1;
+            volatile uint32_t filter         : 1;
+        };
+        volatile uint32_t val;
+    } ext_wakeup_cntl;
+
+    union {
+        struct {
+            volatile uint32_t act_dnum   : 10;
+            volatile uint32_t reserved0  : 22;
+        };
+        volatile uint32_t val;
+    } sdio_wakeup_cntl;
+
+    union {
+        struct {
+            volatile uint32_t reserved0  : 16;
+            volatile uint32_t cnt_target : 16;
+        };
+        volatile uint32_t val;
+    } xtal_slp;
+
+    union {
+        struct {
+            volatile uint32_t reserved0  : 16;
+            volatile uint32_t hpcore1_stall_code : 8;
+            volatile uint32_t hpcore0_stall_code : 8;
+        };
+        volatile uint32_t val;
+    } cpu_sw_stall;
+
+    volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
+    volatile pmu_dcm_wait_delay_t dcm_delay;
+    volatile pmu_vddbat_cfg_t vbat_cfg;
+    volatile pmu_touch_sensor_pwr_cntl_t touch_pwr_cntl;
+
+    union {
+        struct {
+            volatile uint32_t eco_result:1;
+            volatile uint32_t reserved0  : 30;
+            volatile uint32_t eco_en: 1;
+
+        };
+        volatile uint32_t val;
+    } pmu_rdn_eco;
+
+
+    uint32_t reserved[121];
+
+    union {
+        struct {
+            volatile uint32_t pmu_date: 31;
+            volatile uint32_t clk_en  : 1;
+        };
+        volatile uint32_t val;
+    } date;
+} pmu_dev_t;
+
+extern pmu_dev_t PMU;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
+
+_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_RDN_ECO_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/ppa_reg.h b/components/soc/esp32p4/register/soc/ppa_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/ppa_reg.h
rename to components/soc/esp32p4/register/soc/ppa_reg.h
index 2b17794d771..a7a64aa44fb 100644
--- a/components/soc/esp32p4/include/soc/ppa_reg.h
+++ b/components/soc/esp32p4/register/soc/ppa_reg.h
@@ -645,21 +645,21 @@ extern "C" {
  */
 #define PPA_CK_DEFAULT_REG (DR_REG_PPA_BASE + 0x60)
 /** PPA_COLORKEY_DEFAULT_B : R/W; bitpos: [7:0]; default: 0;
- *  default B channle value of color key
+ *  default B channel value of color key
  */
 #define PPA_COLORKEY_DEFAULT_B    0x000000FFU
 #define PPA_COLORKEY_DEFAULT_B_M  (PPA_COLORKEY_DEFAULT_B_V << PPA_COLORKEY_DEFAULT_B_S)
 #define PPA_COLORKEY_DEFAULT_B_V  0x000000FFU
 #define PPA_COLORKEY_DEFAULT_B_S  0
 /** PPA_COLORKEY_DEFAULT_G : R/W; bitpos: [15:8]; default: 0;
- *  default G channle value of color key
+ *  default G channel value of color key
  */
 #define PPA_COLORKEY_DEFAULT_G    0x000000FFU
 #define PPA_COLORKEY_DEFAULT_G_M  (PPA_COLORKEY_DEFAULT_G_V << PPA_COLORKEY_DEFAULT_G_S)
 #define PPA_COLORKEY_DEFAULT_G_V  0x000000FFU
 #define PPA_COLORKEY_DEFAULT_G_S  8
 /** PPA_COLORKEY_DEFAULT_R : R/W; bitpos: [23:16]; default: 0;
- *  default R channle value of color key
+ *  default R channel value of color key
  */
 #define PPA_COLORKEY_DEFAULT_R    0x000000FFU
 #define PPA_COLORKEY_DEFAULT_R_M  (PPA_COLORKEY_DEFAULT_R_V << PPA_COLORKEY_DEFAULT_R_S)
diff --git a/components/soc/esp32p4/include/soc/ppa_struct.h b/components/soc/esp32p4/register/soc/ppa_struct.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/ppa_struct.h
rename to components/soc/esp32p4/register/soc/ppa_struct.h
index 5aa064b9014..abcc3dc0a7d 100644
--- a/components/soc/esp32p4/include/soc/ppa_struct.h
+++ b/components/soc/esp32p4/register/soc/ppa_struct.h
@@ -446,15 +446,15 @@ typedef union {
 typedef union {
     struct {
         /** colorkey_default_b : R/W; bitpos: [7:0]; default: 0;
-         *  default B channle value of color key
+         *  default B channel value of color key
          */
         uint32_t colorkey_default_b:8;
         /** colorkey_default_g : R/W; bitpos: [15:8]; default: 0;
-         *  default G channle value of color key
+         *  default G channel value of color key
          */
         uint32_t colorkey_default_g:8;
         /** colorkey_default_r : R/W; bitpos: [23:16]; default: 0;
-         *  default R channle value of color key
+         *  default R channel value of color key
          */
         uint32_t colorkey_default_r:8;
         /** colorkey_fg_bg_reverse : R/W; bitpos: [24]; default: 0;
diff --git a/components/soc/esp32p4/include/soc/pvt_reg.h b/components/soc/esp32p4/register/soc/pvt_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/pvt_reg.h
rename to components/soc/esp32p4/register/soc/pvt_reg.h
diff --git a/components/soc/esp32p4/include/soc/pvt_struct.h b/components/soc/esp32p4/register/soc/pvt_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/pvt_struct.h
rename to components/soc/esp32p4/register/soc/pvt_struct.h
diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/register/soc/reg_base.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/reg_base.h
rename to components/soc/esp32p4/register/soc/reg_base.h
diff --git a/components/soc/esp32p4/include/soc/rmt_reg.h b/components/soc/esp32p4/register/soc/rmt_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/rmt_reg.h
rename to components/soc/esp32p4/register/soc/rmt_reg.h
diff --git a/components/soc/esp32p4/include/soc/rmt_struct.h b/components/soc/esp32p4/register/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/rmt_struct.h
rename to components/soc/esp32p4/register/soc/rmt_struct.h
diff --git a/components/soc/esp32p4/include/soc/rsa_reg.h b/components/soc/esp32p4/register/soc/rsa_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/rsa_reg.h
rename to components/soc/esp32p4/register/soc/rsa_reg.h
diff --git a/components/soc/esp32p4/include/soc/rsa_struct.h b/components/soc/esp32p4/register/soc/rsa_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/rsa_struct.h
rename to components/soc/esp32p4/register/soc/rsa_struct.h
diff --git a/components/soc/esp32p4/include/soc/rtclockcali_reg.h b/components/soc/esp32p4/register/soc/rtclockcali_reg.h
similarity index 98%
rename from components/soc/esp32p4/include/soc/rtclockcali_reg.h
rename to components/soc/esp32p4/register/soc/rtclockcali_reg.h
index 329ef154c4d..d9794fe943b 100644
--- a/components/soc/esp32p4/include/soc/rtclockcali_reg.h
+++ b/components/soc/esp32p4/register/soc/rtclockcali_reg.h
@@ -267,21 +267,21 @@ extern "C" {
 #define RTCLOCKCALI_DREQ_UPDATE_V  0x00000001U
 #define RTCLOCKCALI_DREQ_UPDATE_S  0
 /** RTCLOCKCALI_DREQ_INIT_32K : WT; bitpos: [2]; default: 0;
- *  Initialize the vaule of 32K OSC dfreq setting.
+ *  Initialize the value of 32K OSC dfreq setting.
  */
 #define RTCLOCKCALI_DREQ_INIT_32K    (BIT(2))
 #define RTCLOCKCALI_DREQ_INIT_32K_M  (RTCLOCKCALI_DREQ_INIT_32K_V << RTCLOCKCALI_DREQ_INIT_32K_S)
 #define RTCLOCKCALI_DREQ_INIT_32K_V  0x00000001U
 #define RTCLOCKCALI_DREQ_INIT_32K_S  2
 /** RTCLOCKCALI_DREQ_INIT_FOSC : WT; bitpos: [3]; default: 0;
- *  Initialize the vaule of FOSC  dfreq setting.
+ *  Initialize the value of FOSC  dfreq setting.
  */
 #define RTCLOCKCALI_DREQ_INIT_FOSC    (BIT(3))
 #define RTCLOCKCALI_DREQ_INIT_FOSC_M  (RTCLOCKCALI_DREQ_INIT_FOSC_V << RTCLOCKCALI_DREQ_INIT_FOSC_S)
 #define RTCLOCKCALI_DREQ_INIT_FOSC_V  0x00000001U
 #define RTCLOCKCALI_DREQ_INIT_FOSC_S  3
 /** RTCLOCKCALI_DREQ_INIT_SOSC : WT; bitpos: [4]; default: 0;
- *  Initialize the vaule of SOSC  dfreq setting.
+ *  Initialize the value of SOSC  dfreq setting.
  */
 #define RTCLOCKCALI_DREQ_INIT_SOSC    (BIT(4))
 #define RTCLOCKCALI_DREQ_INIT_SOSC_M  (RTCLOCKCALI_DREQ_INIT_SOSC_V << RTCLOCKCALI_DREQ_INIT_SOSC_S)
@@ -312,21 +312,21 @@ extern "C" {
 #define RTCLOCKCALI_SOSC_DFREQ_SEL_V  0x00000001U
 #define RTCLOCKCALI_SOSC_DFREQ_SEL_S  7
 /** RTCLOCKCALI_FINE_STEP : R/W; bitpos: [15:8]; default: 1;
- *  Frequncy fine step.
+ *  Frequency fine step.
  */
 #define RTCLOCKCALI_FINE_STEP    0x000000FFU
 #define RTCLOCKCALI_FINE_STEP_M  (RTCLOCKCALI_FINE_STEP_V << RTCLOCKCALI_FINE_STEP_S)
 #define RTCLOCKCALI_FINE_STEP_V  0x000000FFU
 #define RTCLOCKCALI_FINE_STEP_S  8
 /** RTCLOCKCALI_COARSE_STEP_FAST : R/W; bitpos: [23:16]; default: 8;
- *  Frequncy coarse step,use to decrease calibration time.
+ *  Frequency coarse step,use to decrease calibration time.
  */
 #define RTCLOCKCALI_COARSE_STEP_FAST    0x000000FFU
 #define RTCLOCKCALI_COARSE_STEP_FAST_M  (RTCLOCKCALI_COARSE_STEP_FAST_V << RTCLOCKCALI_COARSE_STEP_FAST_S)
 #define RTCLOCKCALI_COARSE_STEP_FAST_V  0x000000FFU
 #define RTCLOCKCALI_COARSE_STEP_FAST_S  16
 /** RTCLOCKCALI_COARSE_STEP_SLOW : R/W; bitpos: [31:24]; default: 8;
- *  Frequncy coarse step,use to decrease calibration time.
+ *  Frequency coarse step,use to decrease calibration time.
  */
 #define RTCLOCKCALI_COARSE_STEP_SLOW    0x000000FFU
 #define RTCLOCKCALI_COARSE_STEP_SLOW_M  (RTCLOCKCALI_COARSE_STEP_SLOW_V << RTCLOCKCALI_COARSE_STEP_SLOW_S)
@@ -409,14 +409,14 @@ extern "C" {
  */
 #define RTCLOCKCALI_INT_RAW_REG (DR_REG_RTCLOCKCALI_BASE + 0x38)
 /** RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  Indicate the xtal timeout  once happend .
+ *  Indicate the xtal timeout  once happened .
  */
 #define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW    (BIT(29))
 #define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_M  (RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V << RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S)
 #define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_V  0x00000001U
 #define RTCLOCKCALI_XTAL_TIMEOUT_INT_RAW_S  29
 /** RTCLOCKCALI_CALI_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
- *  Indicate the calibration timeout  once happend .
+ *  Indicate the calibration timeout  once happened .
  */
 #define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW    (BIT(30))
 #define RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_M  (RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_V << RTCLOCKCALI_CALI_TIMEOUT_INT_RAW_S)
diff --git a/components/soc/esp32p4/include/soc/rtclockcali_struct.h b/components/soc/esp32p4/register/soc/rtclockcali_struct.h
similarity index 97%
rename from components/soc/esp32p4/include/soc/rtclockcali_struct.h
rename to components/soc/esp32p4/register/soc/rtclockcali_struct.h
index 358ab21fc80..3898c762938 100644
--- a/components/soc/esp32p4/include/soc/rtclockcali_struct.h
+++ b/components/soc/esp32p4/register/soc/rtclockcali_struct.h
@@ -107,15 +107,15 @@ typedef union {
         uint32_t dreq_update:1;
         uint32_t reserved_1:1;
         /** dreq_init_32k : WT; bitpos: [2]; default: 0;
-         *  Initialize the vaule of 32K OSC dfreq setting.
+         *  Initialize the value of 32K OSC dfreq setting.
          */
         uint32_t dreq_init_32k:1;
         /** dreq_init_fosc : WT; bitpos: [3]; default: 0;
-         *  Initialize the vaule of FOSC  dfreq setting.
+         *  Initialize the value of FOSC  dfreq setting.
          */
         uint32_t dreq_init_fosc:1;
         /** dreq_init_sosc : WT; bitpos: [4]; default: 0;
-         *  Initialize the vaule of SOSC  dfreq setting.
+         *  Initialize the value of SOSC  dfreq setting.
          */
         uint32_t dreq_init_sosc:1;
         /** rc32k_dfreq_sel : R/W; bitpos: [5]; default: 0;
@@ -134,15 +134,15 @@ typedef union {
          */
         uint32_t sosc_dfreq_sel:1;
         /** fine_step : R/W; bitpos: [15:8]; default: 1;
-         *  Frequncy fine step.
+         *  Frequency fine step.
          */
         uint32_t fine_step:8;
         /** coarse_step_fast : R/W; bitpos: [23:16]; default: 8;
-         *  Frequncy coarse step,use to decrease calibration time.
+         *  Frequency coarse step,use to decrease calibration time.
          */
         uint32_t coarse_step_fast:8;
         /** coarse_step_slow : R/W; bitpos: [31:24]; default: 8;
-         *  Frequncy coarse step,use to decrease calibration time.
+         *  Frequency coarse step,use to decrease calibration time.
          */
         uint32_t coarse_step_slow:8;
     };
@@ -218,11 +218,11 @@ typedef union {
     struct {
         uint32_t reserved_0:29;
         /** xtal_timeout_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  Indicate the xtal timeout  once happend .
+         *  Indicate the xtal timeout  once happened .
          */
         uint32_t xtal_timeout_int_raw:1;
         /** cali_timeout_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
-         *  Indicate the calibration timeout  once happend .
+         *  Indicate the calibration timeout  once happened .
          */
         uint32_t cali_timeout_int_raw:1;
         /** cali_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
diff --git a/components/soc/esp32p4/register/soc/sdmmc_reg.h b/components/soc/esp32p4/register/soc/sdmmc_reg.h
new file mode 100644
index 00000000000..719dae8260d
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/sdmmc_reg.h
@@ -0,0 +1,1527 @@
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SDHOST_CTRL_REG register
+ *  Control register
+ */
+#define SDHOST_CTRL_REG (DR_REG_SDHOST_BASE + 0x0)
+/** SDHOST_CONTROLLER_RESET : R/W; bitpos: [0]; default: 0;
+ *  To reset controller, firmware should set this bit. This bit is auto-cleared after
+ *  two AHB and two sdhost_cclk_in clock cycles.
+ */
+#define SDHOST_CONTROLLER_RESET    (BIT(0))
+#define SDHOST_CONTROLLER_RESET_M  (SDHOST_CONTROLLER_RESET_V << SDHOST_CONTROLLER_RESET_S)
+#define SDHOST_CONTROLLER_RESET_V  0x00000001U
+#define SDHOST_CONTROLLER_RESET_S  0
+/** SDHOST_FIFO_RESET : R/W; bitpos: [1]; default: 0;
+ *  To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after
+ *  completion of reset operation.
+ *  Note: FIFO pointers will be out of reset after 2 cycles of system clocks in
+ *  addition to synchronization delay (2 cycles of card clock), after the fifo_reset is
+ *  cleared.
+ */
+#define SDHOST_FIFO_RESET    (BIT(1))
+#define SDHOST_FIFO_RESET_M  (SDHOST_FIFO_RESET_V << SDHOST_FIFO_RESET_S)
+#define SDHOST_FIFO_RESET_V  0x00000001U
+#define SDHOST_FIFO_RESET_S  1
+/** SDHOST_DMA_RESET : R/W; bitpos: [2]; default: 0;
+ *  To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared
+ *  after two AHB clocks.
+ */
+#define SDHOST_DMA_RESET    (BIT(2))
+#define SDHOST_DMA_RESET_M  (SDHOST_DMA_RESET_V << SDHOST_DMA_RESET_S)
+#define SDHOST_DMA_RESET_V  0x00000001U
+#define SDHOST_DMA_RESET_S  2
+/** SDHOST_INT_ENABLE : R/W; bitpos: [4]; default: 0;
+ *  Global interrupt enable/disable bit. 0: Disable; 1: Enable.
+ */
+#define SDHOST_INT_ENABLE    (BIT(4))
+#define SDHOST_INT_ENABLE_M  (SDHOST_INT_ENABLE_V << SDHOST_INT_ENABLE_S)
+#define SDHOST_INT_ENABLE_V  0x00000001U
+#define SDHOST_INT_ENABLE_S  4
+/** SDHOST_READ_WAIT : R/W; bitpos: [6]; default: 0;
+ *  For sending read-wait to SDIO cards.
+ */
+#define SDHOST_READ_WAIT    (BIT(6))
+#define SDHOST_READ_WAIT_M  (SDHOST_READ_WAIT_V << SDHOST_READ_WAIT_S)
+#define SDHOST_READ_WAIT_V  0x00000001U
+#define SDHOST_READ_WAIT_S  6
+/** SDHOST_SEND_IRQ_RESPONSE : R/W; bitpos: [7]; default: 0;
+ *  Bit automatically clears once response is sent. To wait for MMC card interrupts,
+ *  host issues CMD40 and waits for interrupt response from MMC card(s). In the
+ *  meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this
+ *  bit, at which time SD/MMC command state-machine sends CMD40 response on bus and
+ *  returns to idle state.
+ */
+#define SDHOST_SEND_IRQ_RESPONSE    (BIT(7))
+#define SDHOST_SEND_IRQ_RESPONSE_M  (SDHOST_SEND_IRQ_RESPONSE_V << SDHOST_SEND_IRQ_RESPONSE_S)
+#define SDHOST_SEND_IRQ_RESPONSE_V  0x00000001U
+#define SDHOST_SEND_IRQ_RESPONSE_S  7
+/** SDHOST_ABORT_READ_DATA : R/W; bitpos: [8]; default: 0;
+ *  After a suspend-command is issued during a read-operation, software polls the card
+ *  to find when the suspend-event occurred. Once the suspend-event has occurred,
+ *  software sets the bit which will reset the data state machine that is waiting for
+ *  the next block of data. This bit is automatically cleared once the data state
+ *  machine is reset to idle.
+ */
+#define SDHOST_ABORT_READ_DATA    (BIT(8))
+#define SDHOST_ABORT_READ_DATA_M  (SDHOST_ABORT_READ_DATA_V << SDHOST_ABORT_READ_DATA_S)
+#define SDHOST_ABORT_READ_DATA_V  0x00000001U
+#define SDHOST_ABORT_READ_DATA_S  8
+/** SDHOST_SEND_CCSD : R/W; bitpos: [9]; default: 0;
+ *  When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if
+ *  the current command is expecting CCS (that is, RW_BLK), and if interrupts are
+ *  enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC
+ *  automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD)
+ *  bit  in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host,
+ *  in case the Command Done interrupt is not masked.
+ *  NOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive
+ *  the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may
+ *  be sent to the CE-ATA device, even if the device has signalled CCS.
+ */
+#define SDHOST_SEND_CCSD    (BIT(9))
+#define SDHOST_SEND_CCSD_M  (SDHOST_SEND_CCSD_V << SDHOST_SEND_CCSD_S)
+#define SDHOST_SEND_CCSD_V  0x00000001U
+#define SDHOST_SEND_CCSD_S  9
+/** SDHOST_SEND_AUTO_STOP_CCSD : R/W; bitpos: [10]; default: 0;
+ *  Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together;
+ *  SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set,
+ *  SD/MMC automatically sends an internally-generated STOP command (CMD12) to the
+ *  CE-ATA device. After sending this internally-generated STOP command, the Auto
+ *  Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated
+ *  for the host, in case the ACD interrupt is not masked. After sending the Command
+ *  Completion Signal Disable (CCSD), SD/MMC automatically clears the
+ *  SDHOST_SEND_AUTO_STOP_CCSD bit.
+ */
+#define SDHOST_SEND_AUTO_STOP_CCSD    (BIT(10))
+#define SDHOST_SEND_AUTO_STOP_CCSD_M  (SDHOST_SEND_AUTO_STOP_CCSD_V << SDHOST_SEND_AUTO_STOP_CCSD_S)
+#define SDHOST_SEND_AUTO_STOP_CCSD_V  0x00000001U
+#define SDHOST_SEND_AUTO_STOP_CCSD_S  10
+/** SDHOST_CEATA_DEVICE_INTERRUPT_STATUS : R/W; bitpos: [11]; default: 0;
+ *  Software should appropriately write to this bit after the power-on reset or any
+ *  other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is
+ *  usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt,
+ *  then software should set this bit.
+ */
+#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS    (BIT(11))
+#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_M  (SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_V << SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_S)
+#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_V  0x00000001U
+#define SDHOST_CEATA_DEVICE_INTERRUPT_STATUS_S  11
+
+/** SDHOST_CLKDIV_REG register
+ *  Clock divider configuration register
+ */
+#define SDHOST_CLKDIV_REG (DR_REG_SDHOST_BASE + 0x8)
+/** SDHOST_CLK_DIVIDER0 : R/W; bitpos: [7:0]; default: 0;
+ *  Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+ *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+ *  means divided by 2*255 = 510, and so on.
+ */
+#define SDHOST_CLK_DIVIDER0    0x000000FFU
+#define SDHOST_CLK_DIVIDER0_M  (SDHOST_CLK_DIVIDER0_V << SDHOST_CLK_DIVIDER0_S)
+#define SDHOST_CLK_DIVIDER0_V  0x000000FFU
+#define SDHOST_CLK_DIVIDER0_S  0
+/** SDHOST_CLK_DIVIDER1 : R/W; bitpos: [15:8]; default: 0;
+ *  Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+ *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+ *  means divided by 2*255 = 510, and so on.
+ */
+#define SDHOST_CLK_DIVIDER1    0x000000FFU
+#define SDHOST_CLK_DIVIDER1_M  (SDHOST_CLK_DIVIDER1_V << SDHOST_CLK_DIVIDER1_S)
+#define SDHOST_CLK_DIVIDER1_V  0x000000FFU
+#define SDHOST_CLK_DIVIDER1_S  8
+/** SDHOST_CLK_DIVIDER2 : R/W; bitpos: [23:16]; default: 0;
+ *  Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+ *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+ *  means divided by 2*255 = 510, and so on.
+ */
+#define SDHOST_CLK_DIVIDER2    0x000000FFU
+#define SDHOST_CLK_DIVIDER2_M  (SDHOST_CLK_DIVIDER2_V << SDHOST_CLK_DIVIDER2_S)
+#define SDHOST_CLK_DIVIDER2_V  0x000000FFU
+#define SDHOST_CLK_DIVIDER2_S  16
+/** SDHOST_CLK_DIVIDER3 : R/W; bitpos: [31:24]; default: 0;
+ *  Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider
+ *  (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF
+ *  means divided by 2*255 = 510, and so on.
+ */
+#define SDHOST_CLK_DIVIDER3    0x000000FFU
+#define SDHOST_CLK_DIVIDER3_M  (SDHOST_CLK_DIVIDER3_V << SDHOST_CLK_DIVIDER3_S)
+#define SDHOST_CLK_DIVIDER3_V  0x000000FFU
+#define SDHOST_CLK_DIVIDER3_S  24
+
+/** SDHOST_CLKSRC_REG register
+ *  Clock source selection register
+ */
+#define SDHOST_CLKSRC_REG (DR_REG_SDHOST_BASE + 0xc)
+/** SDHOST_CLKSRC : R/W; bitpos: [3:0]; default: 0;
+ *  Clock divider source for two SD cards is supported. Each card has two bits assigned
+ *  to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for
+ *  card 1. Card 0 maps and internally routes clock divider[0:3] outputs to
+ *  cclk_out[1:0] pins, depending on bit value.
+ *  00 : Clock divider 0;
+ *  01 : Clock divider 1;
+ *  10 : Clock divider 2;
+ *  11 : Clock divider 3.
+ */
+#define SDHOST_CLKSRC    0x0000000FU
+#define SDHOST_CLKSRC_M  (SDHOST_CLKSRC_V << SDHOST_CLKSRC_S)
+#define SDHOST_CLKSRC_V  0x0000000FU
+#define SDHOST_CLKSRC_S  0
+
+/** SDHOST_CLKENA_REG register
+ *  Clock enable register
+ */
+#define SDHOST_CLKENA_REG (DR_REG_SDHOST_BASE + 0x10)
+/** SDHOST_CCLK_ENABLE : R/W; bitpos: [1:0]; default: 0;
+ *  Clock-enable control for two SD card clocks and one MMC card clock is supported.
+ *  One bit per card.
+ *  0: Clock disabled;
+ *  1: Clock enabled.
+ */
+#define SDHOST_CCLK_ENABLE    0x00000003U
+#define SDHOST_CCLK_ENABLE_M  (SDHOST_CCLK_ENABLE_V << SDHOST_CCLK_ENABLE_S)
+#define SDHOST_CCLK_ENABLE_V  0x00000003U
+#define SDHOST_CCLK_ENABLE_S  0
+/** SDHOST_LP_ENABLE : R/W; bitpos: [17:16]; default: 0;
+ *  Disable clock when the card is in IDLE state. One bit per card.
+ *  0: clock disabled;
+ *  1: clock enabled.
+ */
+#define SDHOST_LP_ENABLE    0x00000003U
+#define SDHOST_LP_ENABLE_M  (SDHOST_LP_ENABLE_V << SDHOST_LP_ENABLE_S)
+#define SDHOST_LP_ENABLE_V  0x00000003U
+#define SDHOST_LP_ENABLE_S  16
+
+/** SDHOST_TMOUT_REG register
+ *  Data and response timeout configuration register
+ */
+#define SDHOST_TMOUT_REG (DR_REG_SDHOST_BASE + 0x14)
+/** SDHOST_RESPONSE_TIMEOUT : R/W; bitpos: [7:0]; default: 64;
+ *  Response timeout value. Value is specified in terms of number of card output
+ *  clocks, i.e., sdhost_cclk_out.
+ */
+#define SDHOST_RESPONSE_TIMEOUT    0x000000FFU
+#define SDHOST_RESPONSE_TIMEOUT_M  (SDHOST_RESPONSE_TIMEOUT_V << SDHOST_RESPONSE_TIMEOUT_S)
+#define SDHOST_RESPONSE_TIMEOUT_V  0x000000FFU
+#define SDHOST_RESPONSE_TIMEOUT_S  0
+/** SDHOST_DATA_TIMEOUT : R/W; bitpos: [31:8]; default: 16777215;
+ *  Value for card data read timeout. This value is also used for data starvation by
+ *  host timeout. The timeout counter is started only after the card clock is stopped.
+ *  This value is specified in number of card output clocks, i.e. sdhost_cclk_out of
+ *  the selected card.
+ *  NOTE: The software timer should be used if the timeout value is in the order of 100
+ *  ms. In this case, read data timeout interrupt needs to be disabled.
+ */
+#define SDHOST_DATA_TIMEOUT    0x00FFFFFFU
+#define SDHOST_DATA_TIMEOUT_M  (SDHOST_DATA_TIMEOUT_V << SDHOST_DATA_TIMEOUT_S)
+#define SDHOST_DATA_TIMEOUT_V  0x00FFFFFFU
+#define SDHOST_DATA_TIMEOUT_S  8
+
+/** SDHOST_CTYPE_REG register
+ *  Card bus width configuration register
+ */
+#define SDHOST_CTYPE_REG (DR_REG_SDHOST_BASE + 0x18)
+/** SDHOST_CARD_WIDTH4 : R/W; bitpos: [1:0]; default: 0;
+ *  One bit per card indicates if card is 1-bit or 4-bit mode.
+ *  0: 1-bit mode;
+ *  1: 4-bit mode.
+ *  Bit[1:0] correspond to card[1:0] respectively.
+ */
+#define SDHOST_CARD_WIDTH4    0x00000003U
+#define SDHOST_CARD_WIDTH4_M  (SDHOST_CARD_WIDTH4_V << SDHOST_CARD_WIDTH4_S)
+#define SDHOST_CARD_WIDTH4_V  0x00000003U
+#define SDHOST_CARD_WIDTH4_S  0
+/** SDHOST_CARD_WIDTH8 : R/W; bitpos: [17:16]; default: 0;
+ *  One bit per card indicates if card is in 8-bit mode.
+ *  0: Non 8-bit mode;
+ *  1: 8-bit mode.
+ *  Bit[17:16] correspond to card[1:0] respectively.
+ */
+#define SDHOST_CARD_WIDTH8    0x00000003U
+#define SDHOST_CARD_WIDTH8_M  (SDHOST_CARD_WIDTH8_V << SDHOST_CARD_WIDTH8_S)
+#define SDHOST_CARD_WIDTH8_V  0x00000003U
+#define SDHOST_CARD_WIDTH8_S  16
+
+/** SDHOST_BLKSIZ_REG register
+ *  Card data block size configuration register
+ */
+#define SDHOST_BLKSIZ_REG (DR_REG_SDHOST_BASE + 0x1c)
+/** SDHOST_BLOCK_SIZE : R/W; bitpos: [15:0]; default: 512;
+ *  Block size.
+ */
+#define SDHOST_BLOCK_SIZE    0x0000FFFFU
+#define SDHOST_BLOCK_SIZE_M  (SDHOST_BLOCK_SIZE_V << SDHOST_BLOCK_SIZE_S)
+#define SDHOST_BLOCK_SIZE_V  0x0000FFFFU
+#define SDHOST_BLOCK_SIZE_S  0
+
+/** SDHOST_BYTCNT_REG register
+ *  Data transfer length configuration register
+ */
+#define SDHOST_BYTCNT_REG (DR_REG_SDHOST_BASE + 0x20)
+/** SDHOST_BYTE_COUNT : R/W; bitpos: [31:0]; default: 512;
+ *  Number of bytes to be transferred, should be an integral multiple of Block Size for
+ *  block transfers. For data transfers of undefined byte lengths, byte count should be
+ *  set to 0. When byte count is set to 0, it is the responsibility of host to
+ *  explicitly send stop/abort command to terminate data transfer.
+ */
+#define SDHOST_BYTE_COUNT    0xFFFFFFFFU
+#define SDHOST_BYTE_COUNT_M  (SDHOST_BYTE_COUNT_V << SDHOST_BYTE_COUNT_S)
+#define SDHOST_BYTE_COUNT_V  0xFFFFFFFFU
+#define SDHOST_BYTE_COUNT_S  0
+
+/** SDHOST_INTMASK_REG register
+ *  SDIO interrupt mask register
+ */
+#define SDHOST_INTMASK_REG (DR_REG_SDHOST_BASE + 0x24)
+/** SDHOST_INT_MASK : R/W; bitpos: [15:0]; default: 0;
+ *  These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a
+ *  value of 1 enables the interrupt.
+ *  Bit 15 (EBE): End-bit error/no CRC error;
+ *  Bit 14 (ACD): Auto command done;
+ *  Bit 13 (SBE/BCI): Rx Start Bit Error;
+ *  Bit 12 (HLE): Hardware locked write error;
+ *  Bit 11 (FRUN): FIFO underrun/overrun error;
+ *  Bit 10 (HTO): Data starvation-by-host timeout;
+ *  Bit 9 (DRTO): Data read timeout;
+ *  Bit 8 (RTO): Response timeout;
+ *  Bit 7 (DCRC): Data CRC error;
+ *  Bit 6 (RCRC): Response CRC error;
+ *  Bit 5 (RXDR): Receive FIFO data request;
+ *  Bit 4 (TXDR): Transmit FIFO data request;
+ *  Bit 3 (DTO): Data transfer over;
+ *  Bit 2 (CD): Command done;
+ *  Bit 1 (RE): Response error;
+ *  Bit 0 (CD): Card detect.
+ */
+#define SDHOST_INT_MASK    0x0000FFFFU
+#define SDHOST_INT_MASK_M  (SDHOST_INT_MASK_V << SDHOST_INT_MASK_S)
+#define SDHOST_INT_MASK_V  0x0000FFFFU
+#define SDHOST_INT_MASK_S  0
+/** SDHOST_SDIO_INT_MASK : R/W; bitpos: [17:16]; default: 0;
+ *  SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0]
+ *  respectively. When masked, SDIO interrupt detection for that card is disabled. 0
+ *  masks an interrupt, and 1 enables an interrupt.
+ */
+#define SDHOST_SDIO_INT_MASK    0x00000003U
+#define SDHOST_SDIO_INT_MASK_M  (SDHOST_SDIO_INT_MASK_V << SDHOST_SDIO_INT_MASK_S)
+#define SDHOST_SDIO_INT_MASK_V  0x00000003U
+#define SDHOST_SDIO_INT_MASK_S  16
+
+/** SDHOST_CMDARG_REG register
+ *  Command argument data register
+ */
+#define SDHOST_CMDARG_REG (DR_REG_SDHOST_BASE + 0x28)
+/** SDHOST_CMDARG : R/W; bitpos: [31:0]; default: 0;
+ *  Value indicates command argument to be passed to the card.
+ */
+#define SDHOST_CMDARG    0xFFFFFFFFU
+#define SDHOST_CMDARG_M  (SDHOST_CMDARG_V << SDHOST_CMDARG_S)
+#define SDHOST_CMDARG_V  0xFFFFFFFFU
+#define SDHOST_CMDARG_S  0
+
+/** SDHOST_CMD_REG register
+ *  Command and boot configuration register
+ */
+#define SDHOST_CMD_REG (DR_REG_SDHOST_BASE + 0x2c)
+/** SDHOST_CMD_INDEX : R/W; bitpos: [5:0]; default: 0;
+ *  Command index.
+ */
+#define SDHOST_CMD_INDEX    0x0000003FU
+#define SDHOST_CMD_INDEX_M  (SDHOST_CMD_INDEX_V << SDHOST_CMD_INDEX_S)
+#define SDHOST_CMD_INDEX_V  0x0000003FU
+#define SDHOST_CMD_INDEX_S  0
+/** SDHOST_RESPONSE_EXPECT : R/W; bitpos: [6]; default: 0;
+ *  0: No response expected from card; 1: Response expected from card.
+ */
+#define SDHOST_RESPONSE_EXPECT    (BIT(6))
+#define SDHOST_RESPONSE_EXPECT_M  (SDHOST_RESPONSE_EXPECT_V << SDHOST_RESPONSE_EXPECT_S)
+#define SDHOST_RESPONSE_EXPECT_V  0x00000001U
+#define SDHOST_RESPONSE_EXPECT_S  6
+/** SDHOST_RESPONSE_LENGTH : R/W; bitpos: [7]; default: 0;
+ *  0: Short response expected from card; 1: Long response expected from card.
+ */
+#define SDHOST_RESPONSE_LENGTH    (BIT(7))
+#define SDHOST_RESPONSE_LENGTH_M  (SDHOST_RESPONSE_LENGTH_V << SDHOST_RESPONSE_LENGTH_S)
+#define SDHOST_RESPONSE_LENGTH_V  0x00000001U
+#define SDHOST_RESPONSE_LENGTH_S  7
+/** SDHOST_CHECK_RESPONSE_CRC : R/W; bitpos: [8]; default: 0;
+ *  0: Do not check; 1: Check response CRC.
+ *  Some of command responses do not return valid CRC bits. Software should disable CRC
+ *  checks for those commands in order to disable CRC checking by controller.
+ */
+#define SDHOST_CHECK_RESPONSE_CRC    (BIT(8))
+#define SDHOST_CHECK_RESPONSE_CRC_M  (SDHOST_CHECK_RESPONSE_CRC_V << SDHOST_CHECK_RESPONSE_CRC_S)
+#define SDHOST_CHECK_RESPONSE_CRC_V  0x00000001U
+#define SDHOST_CHECK_RESPONSE_CRC_S  8
+/** SDHOST_DATA_EXPECTED : R/W; bitpos: [9]; default: 0;
+ *  0: No data transfer expected; 1: Data transfer expected.
+ */
+#define SDHOST_DATA_EXPECTED    (BIT(9))
+#define SDHOST_DATA_EXPECTED_M  (SDHOST_DATA_EXPECTED_V << SDHOST_DATA_EXPECTED_S)
+#define SDHOST_DATA_EXPECTED_V  0x00000001U
+#define SDHOST_DATA_EXPECTED_S  9
+/** SDHOST_READ_WRITE : R/W; bitpos: [10]; default: 0;
+ *  0: Read from card; 1: Write to card.
+ *  Don't care if no data is expected from card.
+ */
+#define SDHOST_READ_WRITE    (BIT(10))
+#define SDHOST_READ_WRITE_M  (SDHOST_READ_WRITE_V << SDHOST_READ_WRITE_S)
+#define SDHOST_READ_WRITE_V  0x00000001U
+#define SDHOST_READ_WRITE_S  10
+/** SDHOST_TRANSFER_MODE : R/W; bitpos: [11]; default: 0;
+ *  0: Block data transfer command; 1: Stream data transfer command.
+ *  Don't care if no data expected.
+ */
+#define SDHOST_TRANSFER_MODE    (BIT(11))
+#define SDHOST_TRANSFER_MODE_M  (SDHOST_TRANSFER_MODE_V << SDHOST_TRANSFER_MODE_S)
+#define SDHOST_TRANSFER_MODE_V  0x00000001U
+#define SDHOST_TRANSFER_MODE_S  11
+/** SDHOST_SEND_AUTO_STOP : R/W; bitpos: [12]; default: 0;
+ *  0: No stop command is sent at the end of data transfer; 1: Send stop command at the
+ *  end of data transfer.
+ */
+#define SDHOST_SEND_AUTO_STOP    (BIT(12))
+#define SDHOST_SEND_AUTO_STOP_M  (SDHOST_SEND_AUTO_STOP_V << SDHOST_SEND_AUTO_STOP_S)
+#define SDHOST_SEND_AUTO_STOP_V  0x00000001U
+#define SDHOST_SEND_AUTO_STOP_S  12
+/** SDHOST_WAIT_PRVDATA_COMPLETE : R/W; bitpos: [13]; default: 0;
+ *  0: Send command at once, even if previous data transfer has not completed; 1: Wait
+ *  for previous data transfer to complete before sending Command.
+ *  The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of
+ *  card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr
+ *  should be same as in previous command.
+ */
+#define SDHOST_WAIT_PRVDATA_COMPLETE    (BIT(13))
+#define SDHOST_WAIT_PRVDATA_COMPLETE_M  (SDHOST_WAIT_PRVDATA_COMPLETE_V << SDHOST_WAIT_PRVDATA_COMPLETE_S)
+#define SDHOST_WAIT_PRVDATA_COMPLETE_V  0x00000001U
+#define SDHOST_WAIT_PRVDATA_COMPLETE_S  13
+/** SDHOST_STOP_ABORT_CMD : R/W; bitpos: [14]; default: 0;
+ *  0: Neither stop nor abort command can stop current data transfer. If abort is sent
+ *  to function-number currently selected or not in data-transfer mode, then bit should
+ *  be set to 0; 1: Stop or abort command intended to stop current data transfer in
+ *  progress.
+ *  When open-ended or predefined data transfer is in progress, and host issues stop or
+ *  abort command to stop data transfer, bit should be set so that command/data
+ *  state-machines of CIU can return correctly to idle state.
+ */
+#define SDHOST_STOP_ABORT_CMD    (BIT(14))
+#define SDHOST_STOP_ABORT_CMD_M  (SDHOST_STOP_ABORT_CMD_V << SDHOST_STOP_ABORT_CMD_S)
+#define SDHOST_STOP_ABORT_CMD_V  0x00000001U
+#define SDHOST_STOP_ABORT_CMD_S  14
+/** SDHOST_SEND_INITIALIZATION : R/W; bitpos: [15]; default: 0;
+ *  0: Do not send initialization sequence (80 clocks of 1) before sending this
+ *  command; 1: Send initialization sequence before sending this command.
+ *  After powered on, 80 clocks must be sent to card for initialization before sending
+ *  any commands to card. Bit should be set while sending first command to card so that
+ *  controller will initialize clocks before sending command to card.
+ */
+#define SDHOST_SEND_INITIALIZATION    (BIT(15))
+#define SDHOST_SEND_INITIALIZATION_M  (SDHOST_SEND_INITIALIZATION_V << SDHOST_SEND_INITIALIZATION_S)
+#define SDHOST_SEND_INITIALIZATION_V  0x00000001U
+#define SDHOST_SEND_INITIALIZATION_S  15
+/** SDHOST_CARD_NUMBER : R/W; bitpos: [20:16]; default: 0;
+ *  Card number in use. Represents physical slot number of card being accessed. In
+ *  SD-only mode, up to two cards are supported.
+ */
+#define SDHOST_CARD_NUMBER    0x0000001FU
+#define SDHOST_CARD_NUMBER_M  (SDHOST_CARD_NUMBER_V << SDHOST_CARD_NUMBER_S)
+#define SDHOST_CARD_NUMBER_V  0x0000001FU
+#define SDHOST_CARD_NUMBER_S  16
+/** SDHOST_UPDATE_CLOCK_REGISTERS_ONLY : R/W; bitpos: [21]; default: 0;
+ *  0: Normal command sequence; 1: Do not send commands, just update clock register
+ *  value into card clock domain.
+ *  Following register values are transferred into card clock domain: CLKDIV, CLRSRC,
+ *  and CLKENA.
+ *  Changes card clocks (change frequency, truncate off or on, and set low-frequency
+ *  mode). This is provided in order to change clock frequency or stop clock without
+ *  having to send command to cards. During normal command sequence, when
+ *  sdhost_update_clock_registers_only = 0, following control registers are transferred
+ *  from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new
+ *  register values for new command sequence to card(s). When bit is set, there are no
+ *  Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
+ */
+#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY    (BIT(21))
+#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_M  (SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_V << SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_S)
+#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_V  0x00000001U
+#define SDHOST_UPDATE_CLOCK_REGISTERS_ONLY_S  21
+/** SDHOST_READ_CEATA_DEVICE : R/W; bitpos: [22]; default: 0;
+ *  Read access flag.
+ *  0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;
+ *  1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.
+ *  Software should set this bit to indicate that CE-ATA device is being accessed for
+ *  read transfer. This bit is used to disable read data timeout indication while
+ *  performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no
+ *  less than 10 seconds. SD/MMC should not indicate read data timeout while waiting
+ *  for data from CE-ATA device.
+ */
+#define SDHOST_READ_CEATA_DEVICE    (BIT(22))
+#define SDHOST_READ_CEATA_DEVICE_M  (SDHOST_READ_CEATA_DEVICE_V << SDHOST_READ_CEATA_DEVICE_S)
+#define SDHOST_READ_CEATA_DEVICE_V  0x00000001U
+#define SDHOST_READ_CEATA_DEVICE_S  22
+/** SDHOST_CCS_EXPECTED : R/W; bitpos: [23]; default: 0;
+ *  Expected Command Completion Signal (CCS) configuration.
+ *  0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register),
+ *  or command does not expect CCS from device;
+ *  1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects
+ *  command completion signal from CE-ATA device.
+ *  If the command expects Command Completion Signal (CCS) from the CE-ATA device, the
+ *  software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in
+ *  RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is
+ *  not masked.
+ */
+#define SDHOST_CCS_EXPECTED    (BIT(23))
+#define SDHOST_CCS_EXPECTED_M  (SDHOST_CCS_EXPECTED_V << SDHOST_CCS_EXPECTED_S)
+#define SDHOST_CCS_EXPECTED_V  0x00000001U
+#define SDHOST_CCS_EXPECTED_S  23
+/** SDHOST_USE_HOLE_REG : R/W; bitpos: [29]; default: 1;
+ *  Use Hold Register.
+ *  0: CMD and DATA sent to card bypassing HOLD Register;
+ *  1: CMD and DATA sent to card through the HOLD Register.
+ */
+#define SDHOST_USE_HOLE_REG    (BIT(29))
+#define SDHOST_USE_HOLE_REG_M  (SDHOST_USE_HOLE_REG_V << SDHOST_USE_HOLE_REG_S)
+#define SDHOST_USE_HOLE_REG_V  0x00000001U
+#define SDHOST_USE_HOLE_REG_S  29
+/** SDHOST_START_CMD : R/W; bitpos: [31]; default: 0;
+ *  Start command. Once command is served by the CIU, this bit is automatically
+ *  cleared. When this bit is set, host should not attempt to write to any command
+ *  registers. If a write is attempted, hardware lock error is set in raw interrupt
+ *  register. Once command is sent and a response is received from SD_MMC_CEATA cards,
+ *  Command Done bit is set in the raw interrupt Register.
+ */
+#define SDHOST_START_CMD    (BIT(31))
+#define SDHOST_START_CMD_M  (SDHOST_START_CMD_V << SDHOST_START_CMD_S)
+#define SDHOST_START_CMD_V  0x00000001U
+#define SDHOST_START_CMD_S  31
+
+/** SDHOST_RESP0_REG register
+ *  Response data register
+ */
+#define SDHOST_RESP0_REG (DR_REG_SDHOST_BASE + 0x30)
+/** SDHOST_RESPONSE0_REG : RO; bitpos: [31:0]; default: 0;
+ *  Bit[31:0] of response.
+ */
+#define SDHOST_RESPONSE0_REG    0xFFFFFFFFU
+#define SDHOST_RESPONSE0_REG_M  (SDHOST_RESPONSE0_REG_V << SDHOST_RESPONSE0_REG_S)
+#define SDHOST_RESPONSE0_REG_V  0xFFFFFFFFU
+#define SDHOST_RESPONSE0_REG_S  0
+
+/** SDHOST_RESP1_REG register
+ *  Long response data register
+ */
+#define SDHOST_RESP1_REG (DR_REG_SDHOST_BASE + 0x34)
+/** SDHOST_RESPONSE1_REG : RO; bitpos: [31:0]; default: 0;
+ *  Bit[63:32] of long response.
+ */
+#define SDHOST_RESPONSE1_REG    0xFFFFFFFFU
+#define SDHOST_RESPONSE1_REG_M  (SDHOST_RESPONSE1_REG_V << SDHOST_RESPONSE1_REG_S)
+#define SDHOST_RESPONSE1_REG_V  0xFFFFFFFFU
+#define SDHOST_RESPONSE1_REG_S  0
+
+/** SDHOST_RESP2_REG register
+ *  Long response data register
+ */
+#define SDHOST_RESP2_REG (DR_REG_SDHOST_BASE + 0x38)
+/** SDHOST_RESPONSE2_REG : RO; bitpos: [31:0]; default: 0;
+ *  Bit[95:64] of long response.
+ */
+#define SDHOST_RESPONSE2_REG    0xFFFFFFFFU
+#define SDHOST_RESPONSE2_REG_M  (SDHOST_RESPONSE2_REG_V << SDHOST_RESPONSE2_REG_S)
+#define SDHOST_RESPONSE2_REG_V  0xFFFFFFFFU
+#define SDHOST_RESPONSE2_REG_S  0
+
+/** SDHOST_RESP3_REG register
+ *  Long response data register
+ */
+#define SDHOST_RESP3_REG (DR_REG_SDHOST_BASE + 0x3c)
+/** SDHOST_RESPONSE3_REG : RO; bitpos: [31:0]; default: 0;
+ *  Bit[127:96] of long response.
+ */
+#define SDHOST_RESPONSE3_REG    0xFFFFFFFFU
+#define SDHOST_RESPONSE3_REG_M  (SDHOST_RESPONSE3_REG_V << SDHOST_RESPONSE3_REG_S)
+#define SDHOST_RESPONSE3_REG_V  0xFFFFFFFFU
+#define SDHOST_RESPONSE3_REG_S  0
+
+/** SDHOST_MINTSTS_REG register
+ *  Masked interrupt status register
+ */
+#define SDHOST_MINTSTS_REG (DR_REG_SDHOST_BASE + 0x40)
+/** SDHOST_INT_STATUS_MSK : RO; bitpos: [15:0]; default: 0;
+ *  Interrupt enabled only if corresponding bit in interrupt mask register is set.
+ *  Bit 15 (EBE): End-bit error/no CRC error;
+ *  Bit 14 (ACD): Auto command done;
+ *  Bit 13 (SBE/BCI): RX Start Bit Error;
+ *  Bit 12 (HLE): Hardware locked write error;
+ *  Bit 11 (FRUN): FIFO underrun/overrun error;
+ *  Bit 10 (HTO): Data starvation by host timeout (HTO);
+ *  Bit 9 (DTRO): Data read timeout;
+ *  Bit 8 (RTO): Response timeout;
+ *  Bit 7 (DCRC): Data CRC error;
+ *  Bit 6 (RCRC): Response CRC error;
+ *  Bit 5 (RXDR): Receive FIFO data request;
+ *  Bit 4 (TXDR): Transmit FIFO data request;
+ *  Bit 3 (DTO): Data transfer over;
+ *  Bit 2 (CD): Command done;
+ *  Bit 1 (RE): Response error;
+ *  Bit 0 (CD): Card detect.
+ */
+#define SDHOST_INT_STATUS_MSK    0x0000FFFFU
+#define SDHOST_INT_STATUS_MSK_M  (SDHOST_INT_STATUS_MSK_V << SDHOST_INT_STATUS_MSK_S)
+#define SDHOST_INT_STATUS_MSK_V  0x0000FFFFU
+#define SDHOST_INT_STATUS_MSK_S  0
+/** SDHOST_SDIO_INTERRUPT_MSK : RO; bitpos: [17:16]; default: 0;
+ *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
+ *  card0, respectively. SDIO interrupt for card is enabled only if corresponding
+ *  sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit
+ *  enables interrupt).
+ */
+#define SDHOST_SDIO_INTERRUPT_MSK    0x00000003U
+#define SDHOST_SDIO_INTERRUPT_MSK_M  (SDHOST_SDIO_INTERRUPT_MSK_V << SDHOST_SDIO_INTERRUPT_MSK_S)
+#define SDHOST_SDIO_INTERRUPT_MSK_V  0x00000003U
+#define SDHOST_SDIO_INTERRUPT_MSK_S  16
+
+/** SDHOST_RINTSTS_REG register
+ *  Raw interrupt status register
+ */
+#define SDHOST_RINTSTS_REG (DR_REG_SDHOST_BASE + 0x44)
+/** SDHOST_INT_STATUS_RAW : R/W; bitpos: [15:0]; default: 0;
+ *  Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits
+ *  are logged regardless of interrupt mask status.
+ *  Bit 15 (EBE): End-bit error/no CRC error;
+ *  Bit 14 (ACD): Auto command done;
+ *  Bit 13 (SBE/BCI): RX Start Bit Error;
+ *  Bit 12 (HLE): Hardware locked write error;
+ *  Bit 11 (FRUN): FIFO underrun/overrun error;
+ *  Bit 10 (HTO): Data starvation by host timeout (HTO);
+ *  Bit 9 (DTRO): Data read timeout;
+ *  Bit 8 (RTO): Response timeout;
+ *  Bit 7 (DCRC): Data CRC error;
+ *  Bit 6 (RCRC): Response CRC error;
+ *  Bit 5 (RXDR): Receive FIFO data request;
+ *  Bit 4 (TXDR): Transmit FIFO data request;
+ *  Bit 3 (DTO): Data transfer over;
+ *  Bit 2 (CD): Command done;
+ *  Bit 1 (RE): Response error;
+ *  Bit 0 (CD): Card detect.
+ */
+#define SDHOST_INT_STATUS_RAW    0x0000FFFFU
+#define SDHOST_INT_STATUS_RAW_M  (SDHOST_INT_STATUS_RAW_V << SDHOST_INT_STATUS_RAW_S)
+#define SDHOST_INT_STATUS_RAW_V  0x0000FFFFU
+#define SDHOST_INT_STATUS_RAW_S  0
+/** SDHOST_SDIO_INTERRUPT_RAW : R/W; bitpos: [17:16]; default: 0;
+ *  Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and
+ *  card0, respectively. Setting a bit clears the corresponding interrupt bit and
+ *  writing 0 has no effect.
+ *  0: No SDIO interrupt from card;
+ *  1: SDIO interrupt from card.
+ */
+#define SDHOST_SDIO_INTERRUPT_RAW    0x00000003U
+#define SDHOST_SDIO_INTERRUPT_RAW_M  (SDHOST_SDIO_INTERRUPT_RAW_V << SDHOST_SDIO_INTERRUPT_RAW_S)
+#define SDHOST_SDIO_INTERRUPT_RAW_V  0x00000003U
+#define SDHOST_SDIO_INTERRUPT_RAW_S  16
+
+/** SDHOST_STATUS_REG register
+ *  SD/MMC status register
+ */
+#define SDHOST_STATUS_REG (DR_REG_SDHOST_BASE + 0x48)
+/** SDHOST_FIFO_RX_WATERMARK : RO; bitpos: [0]; default: 0;
+ *  FIFO reached Receive watermark level, not qualified with data transfer.
+ */
+#define SDHOST_FIFO_RX_WATERMARK    (BIT(0))
+#define SDHOST_FIFO_RX_WATERMARK_M  (SDHOST_FIFO_RX_WATERMARK_V << SDHOST_FIFO_RX_WATERMARK_S)
+#define SDHOST_FIFO_RX_WATERMARK_V  0x00000001U
+#define SDHOST_FIFO_RX_WATERMARK_S  0
+/** SDHOST_FIFO_TX_WATERMARK : RO; bitpos: [1]; default: 1;
+ *  FIFO reached Transmit watermark level, not qualified with data transfer.
+ */
+#define SDHOST_FIFO_TX_WATERMARK    (BIT(1))
+#define SDHOST_FIFO_TX_WATERMARK_M  (SDHOST_FIFO_TX_WATERMARK_V << SDHOST_FIFO_TX_WATERMARK_S)
+#define SDHOST_FIFO_TX_WATERMARK_V  0x00000001U
+#define SDHOST_FIFO_TX_WATERMARK_S  1
+/** SDHOST_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  FIFO is empty status.
+ */
+#define SDHOST_FIFO_EMPTY    (BIT(2))
+#define SDHOST_FIFO_EMPTY_M  (SDHOST_FIFO_EMPTY_V << SDHOST_FIFO_EMPTY_S)
+#define SDHOST_FIFO_EMPTY_V  0x00000001U
+#define SDHOST_FIFO_EMPTY_S  2
+/** SDHOST_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  FIFO is full status.
+ */
+#define SDHOST_FIFO_FULL    (BIT(3))
+#define SDHOST_FIFO_FULL_M  (SDHOST_FIFO_FULL_V << SDHOST_FIFO_FULL_S)
+#define SDHOST_FIFO_FULL_V  0x00000001U
+#define SDHOST_FIFO_FULL_S  3
+/** SDHOST_COMMAND_FSM_STATES : RO; bitpos: [7:4]; default: 1;
+ *  Command FSM states.
+ *  0: Idle;
+ *  1: Send init sequence;
+ *  2: Send cmd start bit;
+ *  3: Send cmd tx bit;
+ *  4: Send cmd index + arg;
+ *  5: Send cmd crc7;
+ *  6: Send cmd end bit;
+ *  7: Receive resp start bit;
+ *  8: Receive resp IRQ response;
+ *  9: Receive resp tx bit;
+ *  10: Receive resp cmd idx;
+ *  11: Receive resp data;
+ *  12: Receive resp crc7;
+ *  13: Receive resp end bit;
+ *  14: Cmd path wait NCC;
+ *  15: Wait, cmd-to-response turnaround.
+ */
+#define SDHOST_COMMAND_FSM_STATES    0x0000000FU
+#define SDHOST_COMMAND_FSM_STATES_M  (SDHOST_COMMAND_FSM_STATES_V << SDHOST_COMMAND_FSM_STATES_S)
+#define SDHOST_COMMAND_FSM_STATES_V  0x0000000FU
+#define SDHOST_COMMAND_FSM_STATES_S  4
+/** SDHOST_DATA_3_STATUS : RO; bitpos: [8]; default: 1;
+ *  Raw selected sdhost_card_data[3], checks whether card is present.
+ *  0: card not present;
+ *  1: card present.
+ */
+#define SDHOST_DATA_3_STATUS    (BIT(8))
+#define SDHOST_DATA_3_STATUS_M  (SDHOST_DATA_3_STATUS_V << SDHOST_DATA_3_STATUS_S)
+#define SDHOST_DATA_3_STATUS_V  0x00000001U
+#define SDHOST_DATA_3_STATUS_S  8
+/** SDHOST_DATA_BUSY : RO; bitpos: [9]; default: 1;
+ *  Inverted version of raw selected sdhost_card_data[0].
+ *  0: Card data not busy;
+ *  1: Card data busy.
+ */
+#define SDHOST_DATA_BUSY    (BIT(9))
+#define SDHOST_DATA_BUSY_M  (SDHOST_DATA_BUSY_V << SDHOST_DATA_BUSY_S)
+#define SDHOST_DATA_BUSY_V  0x00000001U
+#define SDHOST_DATA_BUSY_S  9
+/** SDHOST_DATA_STATE_MC_BUSY : RO; bitpos: [10]; default: 1;
+ *  Data transmit or receive state-machine is busy.
+ */
+#define SDHOST_DATA_STATE_MC_BUSY    (BIT(10))
+#define SDHOST_DATA_STATE_MC_BUSY_M  (SDHOST_DATA_STATE_MC_BUSY_V << SDHOST_DATA_STATE_MC_BUSY_S)
+#define SDHOST_DATA_STATE_MC_BUSY_V  0x00000001U
+#define SDHOST_DATA_STATE_MC_BUSY_S  10
+/** SDHOST_RESPONSE_INDEX : RO; bitpos: [16:11]; default: 0;
+ *  Index of previous response, including any auto-stop sent by core.
+ */
+#define SDHOST_RESPONSE_INDEX    0x0000003FU
+#define SDHOST_RESPONSE_INDEX_M  (SDHOST_RESPONSE_INDEX_V << SDHOST_RESPONSE_INDEX_S)
+#define SDHOST_RESPONSE_INDEX_V  0x0000003FU
+#define SDHOST_RESPONSE_INDEX_S  11
+/** SDHOST_FIFO_COUNT : RO; bitpos: [29:17]; default: 0;
+ *  FIFO count, number of filled locations in FIFO.
+ */
+#define SDHOST_FIFO_COUNT    0x00001FFFU
+#define SDHOST_FIFO_COUNT_M  (SDHOST_FIFO_COUNT_V << SDHOST_FIFO_COUNT_S)
+#define SDHOST_FIFO_COUNT_V  0x00001FFFU
+#define SDHOST_FIFO_COUNT_S  17
+
+/** SDHOST_FIFOTH_REG register
+ *  FIFO configuration register
+ */
+#define SDHOST_FIFOTH_REG (DR_REG_SDHOST_BASE + 0x4c)
+/** SDHOST_TX_WMARK : R/W; bitpos: [11:0]; default: 0;
+ *  FIFO threshold watermark level when transmitting data to card. When FIFO data count
+ *  is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is
+ *  enabled, then interrupt  occurs. During end of packet, request or interrupt is
+ *  generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO
+ *  threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA
+ *  request. During end of packet, on last interrupt, host is responsible for filling
+ *  FIFO with only required remaining bytes (not before FIFO is full or after CIU
+ *  completes data transfers, because FIFO may not be empty).  In DMA mode, at end of
+ *  packet, if last transfer is less than burst  size, DMA controller does single
+ *  cycles until required bytes are  transferred.
+ */
+#define SDHOST_TX_WMARK    0x00000FFFU
+#define SDHOST_TX_WMARK_M  (SDHOST_TX_WMARK_V << SDHOST_TX_WMARK_S)
+#define SDHOST_TX_WMARK_V  0x00000FFFU
+#define SDHOST_TX_WMARK_S  0
+/** SDHOST_RX_WMARK : R/W; bitpos: [26:16]; default: 0;
+ *  FIFO threshold watermark level when receiving data to card.When FIFO data count
+ *  reaches greater than this number , DMA/FIFO request is raised. During end of
+ *  packet, request is generated regardless of threshold programming in order to
+ *  complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR)
+ *  interrupt is enabled, then interrupt is generated instead of DMA request.During end
+ *  of packet, interrupt is not generated if threshold programming is larger than any
+ *  remaining data. It is responsibility of host to read remaining bytes on seeing Data
+ *  Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are
+ *  less than threshold, DMA request does single transfers to flush out any remaining
+ *  bytes before Data Transfer Done interrupt is set.
+ */
+#define SDHOST_RX_WMARK    0x000007FFU
+#define SDHOST_RX_WMARK_M  (SDHOST_RX_WMARK_V << SDHOST_RX_WMARK_S)
+#define SDHOST_RX_WMARK_V  0x000007FFU
+#define SDHOST_RX_WMARK_S  16
+/** SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE : R/W; bitpos: [30:28]; default: 0;
+ *  Burst size of multiple transaction, should be programmed same as DMA controller
+ *  multiple-transaction-size SDHOST_SRC/DEST_MSIZE.
+ *  000: 1-byte transfer;
+ *  001: 4-byte transfer;
+ *  010: 8-byte transfer;
+ *  011: 16-byte transfer;
+ *  100: 32-byte transfer;
+ *  101: 64-byte transfer;
+ *  110: 128-byte transfer;
+ *  111: 256-byte transfer.
+ */
+#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE    0x00000007U
+#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_M  (SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_V << SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_S)
+#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_V  0x00000007U
+#define SDHOST_DMA_MULTIPLE_TRANSACTION_SIZE_S  28
+
+/** SDHOST_CDETECT_REG register
+ *  Card detect register
+ */
+#define SDHOST_CDETECT_REG (DR_REG_SDHOST_BASE + 0x50)
+/** SDHOST_CARD_DETECT_N : RO; bitpos: [1:0]; default: 0;
+ *  Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0
+ *  represents presence of card. Only NUM_CARDS number of bits are implemented.
+ */
+#define SDHOST_CARD_DETECT_N    0x00000003U
+#define SDHOST_CARD_DETECT_N_M  (SDHOST_CARD_DETECT_N_V << SDHOST_CARD_DETECT_N_S)
+#define SDHOST_CARD_DETECT_N_V  0x00000003U
+#define SDHOST_CARD_DETECT_N_S  0
+
+/** SDHOST_WRTPRT_REG register
+ *  Card write protection (WP) status register
+ */
+#define SDHOST_WRTPRT_REG (DR_REG_SDHOST_BASE + 0x54)
+/** SDHOST_WRITE_PROTECT : RO; bitpos: [1:0]; default: 0;
+ *  Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write
+ *  protection. Only NUM_CARDS number of bits are implemented.
+ */
+#define SDHOST_WRITE_PROTECT    0x00000003U
+#define SDHOST_WRITE_PROTECT_M  (SDHOST_WRITE_PROTECT_V << SDHOST_WRITE_PROTECT_S)
+#define SDHOST_WRITE_PROTECT_V  0x00000003U
+#define SDHOST_WRITE_PROTECT_S  0
+
+/** SDHOST_TCBCNT_REG register
+ *  Transferred byte count register
+ */
+#define SDHOST_TCBCNT_REG (DR_REG_SDHOST_BASE + 0x5c)
+/** SDHOST_TCBCNT : RO; bitpos: [31:0]; default: 0;
+ *  Number of bytes transferred by CIU unit to card.
+ */
+#define SDHOST_TCBCNT    0xFFFFFFFFU
+#define SDHOST_TCBCNT_M  (SDHOST_TCBCNT_V << SDHOST_TCBCNT_S)
+#define SDHOST_TCBCNT_V  0xFFFFFFFFU
+#define SDHOST_TCBCNT_S  0
+
+/** SDHOST_TBBCNT_REG register
+ *  Transferred byte count register
+ */
+#define SDHOST_TBBCNT_REG (DR_REG_SDHOST_BASE + 0x60)
+/** SDHOST_TBBCNT : RO; bitpos: [31:0]; default: 0;
+ *  Number of bytes transferred between Host/DMA memory and BIU FIFO.
+ */
+#define SDHOST_TBBCNT    0xFFFFFFFFU
+#define SDHOST_TBBCNT_M  (SDHOST_TBBCNT_V << SDHOST_TBBCNT_S)
+#define SDHOST_TBBCNT_V  0xFFFFFFFFU
+#define SDHOST_TBBCNT_S  0
+
+/** SDHOST_DEBNCE_REG register
+ *  Debounce filter time configuration register
+ */
+#define SDHOST_DEBNCE_REG (DR_REG_SDHOST_BASE + 0x64)
+/** SDHOST_DEBOUNCE_COUNT : R/W; bitpos: [23:0]; default: 0;
+ *  Number of host clocks (clk) used by debounce filter logic. The typical debounce
+ *  time is 5 \verb+~+ 25 ms to prevent the card instability when the card is inserted
+ *  or removed.
+ */
+#define SDHOST_DEBOUNCE_COUNT    0x00FFFFFFU
+#define SDHOST_DEBOUNCE_COUNT_M  (SDHOST_DEBOUNCE_COUNT_V << SDHOST_DEBOUNCE_COUNT_S)
+#define SDHOST_DEBOUNCE_COUNT_V  0x00FFFFFFU
+#define SDHOST_DEBOUNCE_COUNT_S  0
+
+/** SDHOST_USRID_REG register
+ *  User ID (scratchpad) register
+ */
+#define SDHOST_USRID_REG (DR_REG_SDHOST_BASE + 0x68)
+/** SDHOST_USRID : R/W; bitpos: [31:0]; default: 0;
+ *  User identification register, value set by user. Can also be used as a scratchpad
+ *  register by user.
+ */
+#define SDHOST_USRID    0xFFFFFFFFU
+#define SDHOST_USRID_M  (SDHOST_USRID_V << SDHOST_USRID_S)
+#define SDHOST_USRID_V  0xFFFFFFFFU
+#define SDHOST_USRID_S  0
+
+/** SDHOST_VERID_REG register
+ *  Version ID (scratchpad) register
+ */
+#define SDHOST_VERID_REG (DR_REG_SDHOST_BASE + 0x6c)
+/** SDHOST_VERSIONID : RO; bitpos: [31:0]; default: 1412572938;
+ *  Hardware version register. Can also be read by fireware.
+ */
+#define SDHOST_VERSIONID    0xFFFFFFFFU
+#define SDHOST_VERSIONID_M  (SDHOST_VERSIONID_V << SDHOST_VERSIONID_S)
+#define SDHOST_VERSIONID_V  0xFFFFFFFFU
+#define SDHOST_VERSIONID_S  0
+
+/** SDHOST_HCON_REG register
+ *  Hardware feature register
+ */
+#define SDHOST_HCON_REG (DR_REG_SDHOST_BASE + 0x70)
+/** SDHOST_CARD_TYPE_REG : RO; bitpos: [0]; default: 1;
+ *  Hardware support SDIO and MMC.
+ */
+#define SDHOST_CARD_TYPE_REG    (BIT(0))
+#define SDHOST_CARD_TYPE_REG_M  (SDHOST_CARD_TYPE_REG_V << SDHOST_CARD_TYPE_REG_S)
+#define SDHOST_CARD_TYPE_REG_V  0x00000001U
+#define SDHOST_CARD_TYPE_REG_S  0
+/** SDHOST_CARD_NUM_REG : RO; bitpos: [5:1]; default: 1;
+ *  Support card number is 2.
+ */
+#define SDHOST_CARD_NUM_REG    0x0000001FU
+#define SDHOST_CARD_NUM_REG_M  (SDHOST_CARD_NUM_REG_V << SDHOST_CARD_NUM_REG_S)
+#define SDHOST_CARD_NUM_REG_V  0x0000001FU
+#define SDHOST_CARD_NUM_REG_S  1
+/** SDHOST_BUS_TYPE_REG : RO; bitpos: [6]; default: 1;
+ *  Register config is APB bus.
+ */
+#define SDHOST_BUS_TYPE_REG    (BIT(6))
+#define SDHOST_BUS_TYPE_REG_M  (SDHOST_BUS_TYPE_REG_V << SDHOST_BUS_TYPE_REG_S)
+#define SDHOST_BUS_TYPE_REG_V  0x00000001U
+#define SDHOST_BUS_TYPE_REG_S  6
+/** SDHOST_DATA_WIDTH_REG : RO; bitpos: [9:7]; default: 1;
+ *  Regisger data width is 32.
+ */
+#define SDHOST_DATA_WIDTH_REG    0x00000007U
+#define SDHOST_DATA_WIDTH_REG_M  (SDHOST_DATA_WIDTH_REG_V << SDHOST_DATA_WIDTH_REG_S)
+#define SDHOST_DATA_WIDTH_REG_V  0x00000007U
+#define SDHOST_DATA_WIDTH_REG_S  7
+/** SDHOST_ADDR_WIDTH_REG : RO; bitpos: [15:10]; default: 19;
+ *  Register address width is 32.
+ */
+#define SDHOST_ADDR_WIDTH_REG    0x0000003FU
+#define SDHOST_ADDR_WIDTH_REG_M  (SDHOST_ADDR_WIDTH_REG_V << SDHOST_ADDR_WIDTH_REG_S)
+#define SDHOST_ADDR_WIDTH_REG_V  0x0000003FU
+#define SDHOST_ADDR_WIDTH_REG_S  10
+/** SDHOST_DMA_WIDTH_REG : RO; bitpos: [20:18]; default: 1;
+ *  DMA data width is 32.
+ */
+#define SDHOST_DMA_WIDTH_REG    0x00000007U
+#define SDHOST_DMA_WIDTH_REG_M  (SDHOST_DMA_WIDTH_REG_V << SDHOST_DMA_WIDTH_REG_S)
+#define SDHOST_DMA_WIDTH_REG_V  0x00000007U
+#define SDHOST_DMA_WIDTH_REG_S  18
+/** SDHOST_RAM_INDISE_REG : RO; bitpos: [21]; default: 0;
+ *  Inside RAM in SDMMC module.
+ */
+#define SDHOST_RAM_INDISE_REG    (BIT(21))
+#define SDHOST_RAM_INDISE_REG_M  (SDHOST_RAM_INDISE_REG_V << SDHOST_RAM_INDISE_REG_S)
+#define SDHOST_RAM_INDISE_REG_V  0x00000001U
+#define SDHOST_RAM_INDISE_REG_S  21
+/** SDHOST_HOLD_REG : RO; bitpos: [22]; default: 1;
+ *  Have a hold register in data path .
+ */
+#define SDHOST_HOLD_REG    (BIT(22))
+#define SDHOST_HOLD_REG_M  (SDHOST_HOLD_REG_V << SDHOST_HOLD_REG_S)
+#define SDHOST_HOLD_REG_V  0x00000001U
+#define SDHOST_HOLD_REG_S  22
+/** SDHOST_NUM_CLK_DIV_REG : RO; bitpos: [25:24]; default: 3;
+ *  Have 4 clk divider in design .
+ */
+#define SDHOST_NUM_CLK_DIV_REG    0x00000003U
+#define SDHOST_NUM_CLK_DIV_REG_M  (SDHOST_NUM_CLK_DIV_REG_V << SDHOST_NUM_CLK_DIV_REG_S)
+#define SDHOST_NUM_CLK_DIV_REG_V  0x00000003U
+#define SDHOST_NUM_CLK_DIV_REG_S  24
+
+/** SDHOST_UHS_REG register
+ *  UHS-1 register
+ */
+#define SDHOST_UHS_REG (DR_REG_SDHOST_BASE + 0x74)
+/** SDHOST_DDR_REG : R/W; bitpos: [17:16]; default: 0;
+ *  DDR mode selection,1 bit for each card.
+ *  0-Non-DDR mode.
+ *  1-DDR mode.
+ */
+#define SDHOST_DDR_REG    0x00000003U
+#define SDHOST_DDR_REG_M  (SDHOST_DDR_REG_V << SDHOST_DDR_REG_S)
+#define SDHOST_DDR_REG_V  0x00000003U
+#define SDHOST_DDR_REG_S  16
+
+/** SDHOST_RST_N_REG register
+ *  Card reset register
+ */
+#define SDHOST_RST_N_REG (DR_REG_SDHOST_BASE + 0x78)
+/** SDHOST_CARD_RESET : R/W; bitpos: [1:0]; default: 1;
+ *  Hardware reset.
+ *  1: Active mode;
+ *  0: Reset.
+ *  These bits cause the cards to enter pre-idle state, which requires them to be
+ *  re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0,
+ *  SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1.
+ */
+#define SDHOST_CARD_RESET    0x00000003U
+#define SDHOST_CARD_RESET_M  (SDHOST_CARD_RESET_V << SDHOST_CARD_RESET_S)
+#define SDHOST_CARD_RESET_V  0x00000003U
+#define SDHOST_CARD_RESET_S  0
+
+/** SDHOST_BMOD_REG register
+ *  Burst mode transfer configuration register
+ */
+#define SDHOST_BMOD_REG (DR_REG_SDHOST_BASE + 0x80)
+/** SDHOST_BMOD_SWR : R/W; bitpos: [0]; default: 0;
+ *  Software Reset. When set, the DMA Controller resets all its internal registers. It
+ *  is automatically cleared after one clock cycle.
+ */
+#define SDHOST_BMOD_SWR    (BIT(0))
+#define SDHOST_BMOD_SWR_M  (SDHOST_BMOD_SWR_V << SDHOST_BMOD_SWR_S)
+#define SDHOST_BMOD_SWR_V  0x00000001U
+#define SDHOST_BMOD_SWR_S  0
+/** SDHOST_BMOD_FB : R/W; bitpos: [1]; default: 0;
+ *  Fixed Burst. Controls whether the AHB Master interface performs fixed burst
+ *  transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16
+ *  during start of normal burst transfers. When reset, the AHB will use SINGLE and
+ *  INCR burst transfer operations.
+ */
+#define SDHOST_BMOD_FB    (BIT(1))
+#define SDHOST_BMOD_FB_M  (SDHOST_BMOD_FB_V << SDHOST_BMOD_FB_S)
+#define SDHOST_BMOD_FB_V  0x00000001U
+#define SDHOST_BMOD_FB_S  1
+/** SDHOST_BMOD_DE : R/W; bitpos: [7]; default: 0;
+ *  IDMAC Enable. When set, the IDMAC is enabled.
+ */
+#define SDHOST_BMOD_DE    (BIT(7))
+#define SDHOST_BMOD_DE_M  (SDHOST_BMOD_DE_V << SDHOST_BMOD_DE_S)
+#define SDHOST_BMOD_DE_V  0x00000001U
+#define SDHOST_BMOD_DE_S  7
+/** SDHOST_BMOD_PBL : R/W; bitpos: [10:8]; default: 0;
+ *  Programmable Burst Length. These bits indicate the maximum number of beats to be
+ *  performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always
+ *  attempt to burst as specified in PBL each time it starts a burst transfer on the
+ *  host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value
+ *  is the mirror of MSIZE of FIFOTH register. In order to change this value, write the
+ *  required value to FIFOTH register. This is an encode value as follows:
+ *  000: 1-byte transfer;
+ *  001: 4-byte transfer;
+ *  010: 8-byte transfer;
+ *  011: 16-byte transfer;
+ *  100: 32-byte transfer;
+ *  101: 64-byte transfer;
+ *  110: 128-byte transfer;
+ *  111: 256-byte transfer.
+ *  PBL is a read-only value and is applicable only for data access, it does not apply
+ *  to descriptor access.
+ */
+#define SDHOST_BMOD_PBL    0x00000007U
+#define SDHOST_BMOD_PBL_M  (SDHOST_BMOD_PBL_V << SDHOST_BMOD_PBL_S)
+#define SDHOST_BMOD_PBL_V  0x00000007U
+#define SDHOST_BMOD_PBL_S  8
+
+/** SDHOST_PLDMND_REG register
+ *  Poll demand configuration register
+ */
+#define SDHOST_PLDMND_REG (DR_REG_SDHOST_BASE + 0x84)
+/** SDHOST_PLDMND_PD : WO; bitpos: [31:0]; default: 0;
+ *  Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the
+ *  Suspend state. The host needs to write any value into this register for the IDMAC
+ *  FSM to resume normal descriptor fetch operation. This is a write only .
+ */
+#define SDHOST_PLDMND_PD    0xFFFFFFFFU
+#define SDHOST_PLDMND_PD_M  (SDHOST_PLDMND_PD_V << SDHOST_PLDMND_PD_S)
+#define SDHOST_PLDMND_PD_V  0xFFFFFFFFU
+#define SDHOST_PLDMND_PD_S  0
+
+/** SDHOST_DBADDR_REG register
+ *  Descriptor base address register
+ */
+#define SDHOST_DBADDR_REG (DR_REG_SDHOST_BASE + 0x88)
+/** SDHOST_DBADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Descriptor List. Contains the base address of the First Descriptor. The
+ *  LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence
+ *  these LSB bits may be treated as read-only.
+ */
+#define SDHOST_DBADDR    0xFFFFFFFFU
+#define SDHOST_DBADDR_M  (SDHOST_DBADDR_V << SDHOST_DBADDR_S)
+#define SDHOST_DBADDR_V  0xFFFFFFFFU
+#define SDHOST_DBADDR_S  0
+
+/** SDHOST_IDSTS_REG register
+ *  IDMAC status register
+ */
+#define SDHOST_IDSTS_REG (DR_REG_SDHOST_BASE + 0x8c)
+/** SDHOST_IDSTS_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt. Indicates that data transmission is finished for a descriptor.
+ *  Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_TI    (BIT(0))
+#define SDHOST_IDSTS_TI_M  (SDHOST_IDSTS_TI_V << SDHOST_IDSTS_TI_S)
+#define SDHOST_IDSTS_TI_V  0x00000001U
+#define SDHOST_IDSTS_TI_S  0
+/** SDHOST_IDSTS_RI : R/W; bitpos: [1]; default: 0;
+ *  Receive Interrupt. Indicates the completion of data reception for a descriptor.
+ *  Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_RI    (BIT(1))
+#define SDHOST_IDSTS_RI_M  (SDHOST_IDSTS_RI_V << SDHOST_IDSTS_RI_S)
+#define SDHOST_IDSTS_RI_V  0x00000001U
+#define SDHOST_IDSTS_RI_S  1
+/** SDHOST_IDSTS_FBE : R/W; bitpos: [2]; default: 0;
+ *  Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) .
+ *  When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this
+ *  bit.
+ */
+#define SDHOST_IDSTS_FBE    (BIT(2))
+#define SDHOST_IDSTS_FBE_M  (SDHOST_IDSTS_FBE_V << SDHOST_IDSTS_FBE_S)
+#define SDHOST_IDSTS_FBE_V  0x00000001U
+#define SDHOST_IDSTS_FBE_S  2
+/** SDHOST_IDSTS_DU : R/W; bitpos: [4]; default: 0;
+ *  Descriptor Unavailable Interrupt. This bit is set when the descriptor is
+ *  unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_DU    (BIT(4))
+#define SDHOST_IDSTS_DU_M  (SDHOST_IDSTS_DU_V << SDHOST_IDSTS_DU_S)
+#define SDHOST_IDSTS_DU_V  0x00000001U
+#define SDHOST_IDSTS_DU_S  4
+/** SDHOST_IDSTS_CES : R/W; bitpos: [5]; default: 0;
+ *  Card Error Summary. Indicates the status of the transaction to/from the card, also
+ *  present in RINTSTS. Indicates the logical OR of the following bits:
+ *  EBE : End Bit Error;
+ *  RTO : Response Timeout/Boot Ack Timeout;
+ *  RCRC : Response CRC;
+ *  SBE : Start Bit Error;
+ *  DRTO : Data Read Timeout/BDS timeout;
+ *  DCRC : Data CRC for Receive;
+ *  RE : Response Error.
+ *  Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting
+ *  of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response
+ *  error.
+ */
+#define SDHOST_IDSTS_CES    (BIT(5))
+#define SDHOST_IDSTS_CES_M  (SDHOST_IDSTS_CES_V << SDHOST_IDSTS_CES_S)
+#define SDHOST_IDSTS_CES_V  0x00000001U
+#define SDHOST_IDSTS_CES_S  5
+/** SDHOST_IDSTS_NIS : R/W; bitpos: [8]; default: 0;
+ *  Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit
+ *  Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This
+ *  is a sticky bit and must be cleared each time a corresponding bit that causes NIS
+ *  to be set is cleared. Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_NIS    (BIT(8))
+#define SDHOST_IDSTS_NIS_M  (SDHOST_IDSTS_NIS_V << SDHOST_IDSTS_NIS_S)
+#define SDHOST_IDSTS_NIS_V  0x00000001U
+#define SDHOST_IDSTS_NIS_S  8
+/** SDHOST_IDSTS_AIS : R/W; bitpos: [9]; default: 0;
+ *  Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus
+ *  Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is
+ *  a sticky bit and must be cleared each time a corresponding bit that causes AIS to
+ *  be set is cleared. Writing 1 clears this bit.
+ */
+#define SDHOST_IDSTS_AIS    (BIT(9))
+#define SDHOST_IDSTS_AIS_M  (SDHOST_IDSTS_AIS_V << SDHOST_IDSTS_AIS_S)
+#define SDHOST_IDSTS_AIS_V  0x00000001U
+#define SDHOST_IDSTS_AIS_S  9
+/** SDHOST_IDSTS_FBE_CODE : R/W; bitpos: [12:10]; default: 0;
+ *  Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid
+ *  only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an
+ *  interrupt.
+ *  001: Host Abort received during transmission;
+ *  010: Host Abort received during reception;
+ *  Others: Reserved.
+ */
+#define SDHOST_IDSTS_FBE_CODE    0x00000007U
+#define SDHOST_IDSTS_FBE_CODE_M  (SDHOST_IDSTS_FBE_CODE_V << SDHOST_IDSTS_FBE_CODE_S)
+#define SDHOST_IDSTS_FBE_CODE_V  0x00000007U
+#define SDHOST_IDSTS_FBE_CODE_S  10
+/** SDHOST_IDSTS_FSM : R/W; bitpos: [16:13]; default: 0;
+ *  DMAC FSM present state.
+ *  0: DMA_IDLE (idle state);
+ *  1: DMA_SUSPEND (suspend state);
+ *  2: DESC_RD (descriptor reading state);
+ *  3: DESC_CHK (descriptor checking state);
+ *  4: DMA_RD_REQ_WAIT (read-data request waiting state);
+ *  5: DMA_WR_REQ_WAIT (write-data request waiting state);
+ *  6: DMA_RD (data-read state);
+ *  7: DMA_WR (data-write state);
+ *  8: DESC_CLOSE (descriptor close state).
+ */
+#define SDHOST_IDSTS_FSM    0x0000000FU
+#define SDHOST_IDSTS_FSM_M  (SDHOST_IDSTS_FSM_V << SDHOST_IDSTS_FSM_S)
+#define SDHOST_IDSTS_FSM_V  0x0000000FU
+#define SDHOST_IDSTS_FSM_S  13
+
+/** SDHOST_IDINTEN_REG register
+ *  IDMAC interrupt enable register
+ */
+#define SDHOST_IDINTEN_REG (DR_REG_SDHOST_BASE + 0x90)
+/** SDHOST_IDINTEN_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
+ *  Interrupt is enabled. When reset, Transmit Interrupt is disabled.
+ */
+#define SDHOST_IDINTEN_TI    (BIT(0))
+#define SDHOST_IDINTEN_TI_M  (SDHOST_IDINTEN_TI_V << SDHOST_IDINTEN_TI_S)
+#define SDHOST_IDINTEN_TI_V  0x00000001U
+#define SDHOST_IDINTEN_TI_S  0
+/** SDHOST_IDINTEN_RI : R/W; bitpos: [1]; default: 0;
+ *  Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
+ *  Interrupt is enabled. When reset, Receive Interrupt is disabled.
+ */
+#define SDHOST_IDINTEN_RI    (BIT(1))
+#define SDHOST_IDINTEN_RI_M  (SDHOST_IDINTEN_RI_V << SDHOST_IDINTEN_RI_S)
+#define SDHOST_IDINTEN_RI_V  0x00000001U
+#define SDHOST_IDINTEN_RI_S  1
+/** SDHOST_IDINTEN_FBE : R/W; bitpos: [2]; default: 0;
+ *  Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
+ *  Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is
+ *  disabled.
+ */
+#define SDHOST_IDINTEN_FBE    (BIT(2))
+#define SDHOST_IDINTEN_FBE_M  (SDHOST_IDINTEN_FBE_V << SDHOST_IDINTEN_FBE_S)
+#define SDHOST_IDINTEN_FBE_V  0x00000001U
+#define SDHOST_IDINTEN_FBE_S  2
+/** SDHOST_IDINTEN_DU : R/W; bitpos: [4]; default: 0;
+ *  Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
+ *  Enable, the DU interrupt is enabled.
+ */
+#define SDHOST_IDINTEN_DU    (BIT(4))
+#define SDHOST_IDINTEN_DU_M  (SDHOST_IDINTEN_DU_V << SDHOST_IDINTEN_DU_S)
+#define SDHOST_IDINTEN_DU_V  0x00000001U
+#define SDHOST_IDINTEN_DU_S  4
+/** SDHOST_IDINTEN_CES : R/W; bitpos: [5]; default: 0;
+ *  Card Error summary Interrupt Enable. When set, it enables the Card Interrupt
+ *  summary.
+ */
+#define SDHOST_IDINTEN_CES    (BIT(5))
+#define SDHOST_IDINTEN_CES_M  (SDHOST_IDINTEN_CES_V << SDHOST_IDINTEN_CES_S)
+#define SDHOST_IDINTEN_CES_V  0x00000001U
+#define SDHOST_IDINTEN_CES_S  5
+/** SDHOST_IDINTEN_NI : R/W; bitpos: [8]; default: 0;
+ *  Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When
+ *  reset, a normal interrupt is disabled. This bit enables the following bits:
+ *  IDINTEN[0]: Transmit Interrupt;
+ *  IDINTEN[1]: Receive Interrupt.
+ */
+#define SDHOST_IDINTEN_NI    (BIT(8))
+#define SDHOST_IDINTEN_NI_M  (SDHOST_IDINTEN_NI_V << SDHOST_IDINTEN_NI_S)
+#define SDHOST_IDINTEN_NI_V  0x00000001U
+#define SDHOST_IDINTEN_NI_S  8
+/** SDHOST_IDINTEN_AI : R/W; bitpos: [9]; default: 0;
+ *  Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This
+ *  bit enables the following bits:
+ *  IDINTEN[2]: Fatal Bus Error Interrupt;
+ *  IDINTEN[4]: DU Interrupt.
+ */
+#define SDHOST_IDINTEN_AI    (BIT(9))
+#define SDHOST_IDINTEN_AI_M  (SDHOST_IDINTEN_AI_V << SDHOST_IDINTEN_AI_S)
+#define SDHOST_IDINTEN_AI_V  0x00000001U
+#define SDHOST_IDINTEN_AI_S  9
+
+/** SDHOST_DSCADDR_REG register
+ *  Host descriptor address pointer
+ */
+#define SDHOST_DSCADDR_REG (DR_REG_SDHOST_BASE + 0x94)
+/** SDHOST_DSCADDR : RO; bitpos: [31:0]; default: 0;
+ *  Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on
+ *  reset. This register points to the start address of the current descriptor read by
+ *  the IDMAC.
+ */
+#define SDHOST_DSCADDR    0xFFFFFFFFU
+#define SDHOST_DSCADDR_M  (SDHOST_DSCADDR_V << SDHOST_DSCADDR_S)
+#define SDHOST_DSCADDR_V  0xFFFFFFFFU
+#define SDHOST_DSCADDR_S  0
+
+/** SDHOST_BUFADDR_REG register
+ *  Host buffer address pointer register
+ */
+#define SDHOST_BUFADDR_REG (DR_REG_SDHOST_BASE + 0x98)
+/** SDHOST_BUFADDR : RO; bitpos: [31:0]; default: 0;
+ *  Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
+ *  reset. This register points to the current Data Buffer Address being accessed by
+ *  the IDMAC.
+ */
+#define SDHOST_BUFADDR    0xFFFFFFFFU
+#define SDHOST_BUFADDR_M  (SDHOST_BUFADDR_V << SDHOST_BUFADDR_S)
+#define SDHOST_BUFADDR_V  0xFFFFFFFFU
+#define SDHOST_BUFADDR_S  0
+
+/** SDHOST_CARDTHRCTL_REG register
+ *  Card Threshold Control register
+ */
+#define SDHOST_CARDTHRCTL_REG (DR_REG_SDHOST_BASE + 0x100)
+/** SDHOST_CARDRDTHREN_REG : R/W; bitpos: [0]; default: 0;
+ *  Card read threshold enable.
+ *  1'b0-Card read threshold disabled.
+ *  1'b1-Card read threshold enabled.
+ */
+#define SDHOST_CARDRDTHREN_REG    (BIT(0))
+#define SDHOST_CARDRDTHREN_REG_M  (SDHOST_CARDRDTHREN_REG_V << SDHOST_CARDRDTHREN_REG_S)
+#define SDHOST_CARDRDTHREN_REG_V  0x00000001U
+#define SDHOST_CARDRDTHREN_REG_S  0
+/** SDHOST_CARDCLRINTEN_REG : R/W; bitpos: [1]; default: 0;
+ *  Busy clear interrupt generation:
+ *  1'b0-Busy clear interrypt disabled.
+ *  1'b1-Busy clear interrypt enabled.
+ */
+#define SDHOST_CARDCLRINTEN_REG    (BIT(1))
+#define SDHOST_CARDCLRINTEN_REG_M  (SDHOST_CARDCLRINTEN_REG_V << SDHOST_CARDCLRINTEN_REG_S)
+#define SDHOST_CARDCLRINTEN_REG_V  0x00000001U
+#define SDHOST_CARDCLRINTEN_REG_S  1
+/** SDHOST_CARDWRTHREN_REG : R/W; bitpos: [2]; default: 0;
+ *  Applicable when HS400 mode is enabled.
+ *  1'b0-Card write Threshold disabled.
+ *  1'b1-Card write Threshold enabled.
+ */
+#define SDHOST_CARDWRTHREN_REG    (BIT(2))
+#define SDHOST_CARDWRTHREN_REG_M  (SDHOST_CARDWRTHREN_REG_V << SDHOST_CARDWRTHREN_REG_S)
+#define SDHOST_CARDWRTHREN_REG_V  0x00000001U
+#define SDHOST_CARDWRTHREN_REG_S  2
+/** SDHOST_CARDTHRESHOLD_REG : R/W; bitpos: [31:16]; default: 0;
+ *  The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG
+ *  is set to 1 or SDHOST_CARDRDTHREN_REG set to 1.
+ */
+#define SDHOST_CARDTHRESHOLD_REG    0x0000FFFFU
+#define SDHOST_CARDTHRESHOLD_REG_M  (SDHOST_CARDTHRESHOLD_REG_V << SDHOST_CARDTHRESHOLD_REG_S)
+#define SDHOST_CARDTHRESHOLD_REG_V  0x0000FFFFU
+#define SDHOST_CARDTHRESHOLD_REG_S  16
+
+/** SDHOST_EMMCDDR_REG register
+ *  eMMC DDR register
+ */
+#define SDHOST_EMMCDDR_REG (DR_REG_SDHOST_BASE + 0x10c)
+/** SDHOST_HALFSTARTBIT_REG : R/W; bitpos: [1:0]; default: 0;
+ *  Control for start bit detection mechanism duration of start bit.Each bit refers to
+ *  one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For
+ *  eMMC4.5,start bit can be:
+ *  1'b0-Full cycle.
+ *  1'b1-less than one full cycle.
+ */
+#define SDHOST_HALFSTARTBIT_REG    0x00000003U
+#define SDHOST_HALFSTARTBIT_REG_M  (SDHOST_HALFSTARTBIT_REG_V << SDHOST_HALFSTARTBIT_REG_S)
+#define SDHOST_HALFSTARTBIT_REG_V  0x00000003U
+#define SDHOST_HALFSTARTBIT_REG_S  0
+/** SDHOST_HS400_MODE_REG : R/W; bitpos: [31]; default: 0;
+ *  Set 1 to enable HS400 mode.
+ */
+#define SDHOST_HS400_MODE_REG    (BIT(31))
+#define SDHOST_HS400_MODE_REG_M  (SDHOST_HS400_MODE_REG_V << SDHOST_HS400_MODE_REG_S)
+#define SDHOST_HS400_MODE_REG_V  0x00000001U
+#define SDHOST_HS400_MODE_REG_S  31
+
+/** SDHOST_ENSHIFT_REG register
+ *  Enable Phase Shift register
+ */
+#define SDHOST_ENSHIFT_REG (DR_REG_SDHOST_BASE + 0x110)
+/** SDHOST_ENABLE_SHIFT_REG : R/W; bitpos: [3:0]; default: 0;
+ *  Control for the amount of phase shift provided on the default enables in the
+ *  design.Two bits assigned for each card.
+ *  2'b00-Default phase shift.
+ *  2'b01-Enables shifted to next immediate positive edge.
+ *  2'b10-Enables shifted to next immediate negative edge.
+ *  2'b11-Reserved.
+ */
+#define SDHOST_ENABLE_SHIFT_REG    0x0000000FU
+#define SDHOST_ENABLE_SHIFT_REG_M  (SDHOST_ENABLE_SHIFT_REG_V << SDHOST_ENABLE_SHIFT_REG_S)
+#define SDHOST_ENABLE_SHIFT_REG_V  0x0000000FU
+#define SDHOST_ENABLE_SHIFT_REG_S  0
+
+/** SDHOST_BUFFIFO_REG register
+ *  CPU write and read transmit data by FIFO
+ */
+#define SDHOST_BUFFIFO_REG (DR_REG_SDHOST_BASE + 0x200)
+/** SDHOST_BUFFIFO : R/W; bitpos: [31:0]; default: 0;
+ *  CPU write and read transmit data by FIFO. This register points to the current Data
+ *  FIFO .
+ */
+#define SDHOST_BUFFIFO    0xFFFFFFFFU
+#define SDHOST_BUFFIFO_M  (SDHOST_BUFFIFO_V << SDHOST_BUFFIFO_S)
+#define SDHOST_BUFFIFO_V  0xFFFFFFFFU
+#define SDHOST_BUFFIFO_S  0
+
+/** SDHOST_CLK_EDGE_SEL_REG register
+ *  SDIO control register.
+ */
+#define SDHOST_CLK_EDGE_SEL_REG (DR_REG_SDHOST_BASE + 0x800)
+/** SDHOST_CCLKIN_EDGE_DRV_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  It's used to select the clock phase of the output signal from phase 0, phase 90,
+ *  phase 180, phase 270.
+ */
+#define SDHOST_CCLKIN_EDGE_DRV_SEL    0x00000007U
+#define SDHOST_CCLKIN_EDGE_DRV_SEL_M  (SDHOST_CCLKIN_EDGE_DRV_SEL_V << SDHOST_CCLKIN_EDGE_DRV_SEL_S)
+#define SDHOST_CCLKIN_EDGE_DRV_SEL_V  0x00000007U
+#define SDHOST_CCLKIN_EDGE_DRV_SEL_S  0
+/** SDHOST_CCLKIN_EDGE_SAM_SEL : R/W; bitpos: [5:3]; default: 0;
+ *  It's used to select the clock phase of the input signal from phase 0, phase 90,
+ *  phase 180, phase 270.
+ */
+#define SDHOST_CCLKIN_EDGE_SAM_SEL    0x00000007U
+#define SDHOST_CCLKIN_EDGE_SAM_SEL_M  (SDHOST_CCLKIN_EDGE_SAM_SEL_V << SDHOST_CCLKIN_EDGE_SAM_SEL_S)
+#define SDHOST_CCLKIN_EDGE_SAM_SEL_V  0x00000007U
+#define SDHOST_CCLKIN_EDGE_SAM_SEL_S  3
+/** SDHOST_CCLKIN_EDGE_SLF_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  It's used to select the clock phase of the internal signal from phase 0, phase 90,
+ *  phase 180, phase 270.
+ */
+#define SDHOST_CCLKIN_EDGE_SLF_SEL    0x00000007U
+#define SDHOST_CCLKIN_EDGE_SLF_SEL_M  (SDHOST_CCLKIN_EDGE_SLF_SEL_V << SDHOST_CCLKIN_EDGE_SLF_SEL_S)
+#define SDHOST_CCLKIN_EDGE_SLF_SEL_V  0x00000007U
+#define SDHOST_CCLKIN_EDGE_SLF_SEL_S  6
+/** SDHOST_CCLLKIN_EDGE_H : R/W; bitpos: [12:9]; default: 1;
+ *  The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L.
+ */
+#define SDHOST_CCLLKIN_EDGE_H    0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_H_M  (SDHOST_CCLLKIN_EDGE_H_V << SDHOST_CCLLKIN_EDGE_H_S)
+#define SDHOST_CCLLKIN_EDGE_H_V  0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_H_S  9
+/** SDHOST_CCLLKIN_EDGE_L : R/W; bitpos: [16:13]; default: 0;
+ *  The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H.
+ */
+#define SDHOST_CCLLKIN_EDGE_L    0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_L_M  (SDHOST_CCLLKIN_EDGE_L_V << SDHOST_CCLLKIN_EDGE_L_S)
+#define SDHOST_CCLLKIN_EDGE_L_V  0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_L_S  13
+/** SDHOST_CCLLKIN_EDGE_N : R/W; bitpos: [20:17]; default: 1;
+ *  The clock division of cclk_in.
+ */
+#define SDHOST_CCLLKIN_EDGE_N    0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_N_M  (SDHOST_CCLLKIN_EDGE_N_V << SDHOST_CCLLKIN_EDGE_N_S)
+#define SDHOST_CCLLKIN_EDGE_N_V  0x0000000FU
+#define SDHOST_CCLLKIN_EDGE_N_S  17
+/** SDHOST_ESDIO_MODE : R/W; bitpos: [21]; default: 0;
+ *  Enable esdio mode.
+ */
+#define SDHOST_ESDIO_MODE    (BIT(21))
+#define SDHOST_ESDIO_MODE_M  (SDHOST_ESDIO_MODE_V << SDHOST_ESDIO_MODE_S)
+#define SDHOST_ESDIO_MODE_V  0x00000001U
+#define SDHOST_ESDIO_MODE_S  21
+/** SDHOST_ESD_MODE : R/W; bitpos: [22]; default: 0;
+ *  Enable esd mode.
+ */
+#define SDHOST_ESD_MODE    (BIT(22))
+#define SDHOST_ESD_MODE_M  (SDHOST_ESD_MODE_V << SDHOST_ESD_MODE_S)
+#define SDHOST_ESD_MODE_V  0x00000001U
+#define SDHOST_ESD_MODE_S  22
+/** SDHOST_CCLK_EN : R/W; bitpos: [23]; default: 1;
+ *  Sdio clock enable.
+ */
+#define SDHOST_CCLK_EN    (BIT(23))
+#define SDHOST_CCLK_EN_M  (SDHOST_CCLK_EN_V << SDHOST_CCLK_EN_S)
+#define SDHOST_CCLK_EN_V  0x00000001U
+#define SDHOST_CCLK_EN_S  23
+/** SDHOST_ULTRA_HIGH_SPEED_MODE : R/W; bitpos: [24]; default: 0;
+ *  Enable ultra high speed mode, use dll to generate clk.
+ */
+#define SDHOST_ULTRA_HIGH_SPEED_MODE    (BIT(24))
+#define SDHOST_ULTRA_HIGH_SPEED_MODE_M  (SDHOST_ULTRA_HIGH_SPEED_MODE_V << SDHOST_ULTRA_HIGH_SPEED_MODE_S)
+#define SDHOST_ULTRA_HIGH_SPEED_MODE_V  0x00000001U
+#define SDHOST_ULTRA_HIGH_SPEED_MODE_S  24
+
+/** SDHOST_RAW_INTS_REG register
+ *  SDIO raw ints register.
+ */
+#define SDHOST_RAW_INTS_REG (DR_REG_SDHOST_BASE + 0x804)
+/** SDHOST_RAW_INTS : RO; bitpos: [31:0]; default: 0;
+ *  It indicates raw ints.
+ */
+#define SDHOST_RAW_INTS    0xFFFFFFFFU
+#define SDHOST_RAW_INTS_M  (SDHOST_RAW_INTS_V << SDHOST_RAW_INTS_S)
+#define SDHOST_RAW_INTS_V  0xFFFFFFFFU
+#define SDHOST_RAW_INTS_S  0
+
+/** SDHOST_DLL_CLK_CONF_REG register
+ *  SDIO DLL clock control register.
+ */
+#define SDHOST_DLL_CLK_CONF_REG (DR_REG_SDHOST_BASE + 0x808)
+/** SDHOST_DLL_CCLK_IN_SLF_EN : R/W; bitpos: [0]; default: 0;
+ *  Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_SLF_EN    (BIT(0))
+#define SDHOST_DLL_CCLK_IN_SLF_EN_M  (SDHOST_DLL_CCLK_IN_SLF_EN_V << SDHOST_DLL_CCLK_IN_SLF_EN_S)
+#define SDHOST_DLL_CCLK_IN_SLF_EN_V  0x00000001U
+#define SDHOST_DLL_CCLK_IN_SLF_EN_S  0
+/** SDHOST_DLL_CCLK_IN_DRV_EN : R/W; bitpos: [1]; default: 0;
+ *  Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_DRV_EN    (BIT(1))
+#define SDHOST_DLL_CCLK_IN_DRV_EN_M  (SDHOST_DLL_CCLK_IN_DRV_EN_V << SDHOST_DLL_CCLK_IN_DRV_EN_S)
+#define SDHOST_DLL_CCLK_IN_DRV_EN_V  0x00000001U
+#define SDHOST_DLL_CCLK_IN_DRV_EN_S  1
+/** SDHOST_DLL_CCLK_IN_SAM_EN : R/W; bitpos: [2]; default: 0;
+ *  Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_SAM_EN    (BIT(2))
+#define SDHOST_DLL_CCLK_IN_SAM_EN_M  (SDHOST_DLL_CCLK_IN_SAM_EN_V << SDHOST_DLL_CCLK_IN_SAM_EN_S)
+#define SDHOST_DLL_CCLK_IN_SAM_EN_V  0x00000001U
+#define SDHOST_DLL_CCLK_IN_SAM_EN_S  2
+/** SDHOST_DLL_CCLK_IN_SLF_PHASE : R/W; bitpos: [8:3]; default: 0;
+ *  It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_SLF_PHASE    0x0000003FU
+#define SDHOST_DLL_CCLK_IN_SLF_PHASE_M  (SDHOST_DLL_CCLK_IN_SLF_PHASE_V << SDHOST_DLL_CCLK_IN_SLF_PHASE_S)
+#define SDHOST_DLL_CCLK_IN_SLF_PHASE_V  0x0000003FU
+#define SDHOST_DLL_CCLK_IN_SLF_PHASE_S  3
+/** SDHOST_DLL_CCLK_IN_DRV_PHASE : R/W; bitpos: [14:9]; default: 0;
+ *  It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_DRV_PHASE    0x0000003FU
+#define SDHOST_DLL_CCLK_IN_DRV_PHASE_M  (SDHOST_DLL_CCLK_IN_DRV_PHASE_V << SDHOST_DLL_CCLK_IN_DRV_PHASE_S)
+#define SDHOST_DLL_CCLK_IN_DRV_PHASE_V  0x0000003FU
+#define SDHOST_DLL_CCLK_IN_DRV_PHASE_S  9
+/** SDHOST_DLL_CCLK_IN_SAM_PHASE : R/W; bitpos: [20:15]; default: 0;
+ *  It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1.
+ */
+#define SDHOST_DLL_CCLK_IN_SAM_PHASE    0x0000003FU
+#define SDHOST_DLL_CCLK_IN_SAM_PHASE_M  (SDHOST_DLL_CCLK_IN_SAM_PHASE_V << SDHOST_DLL_CCLK_IN_SAM_PHASE_S)
+#define SDHOST_DLL_CCLK_IN_SAM_PHASE_V  0x0000003FU
+#define SDHOST_DLL_CCLK_IN_SAM_PHASE_S  15
+
+/** SDHOST_DLL_CONF_REG register
+ *  SDIO DLL configuration register.
+ */
+#define SDHOST_DLL_CONF_REG (DR_REG_SDHOST_BASE + 0x80c)
+/** SDHOST_DLL_CAL_STOP : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to stop calibration.
+ */
+#define SDHOST_DLL_CAL_STOP    (BIT(0))
+#define SDHOST_DLL_CAL_STOP_M  (SDHOST_DLL_CAL_STOP_V << SDHOST_DLL_CAL_STOP_S)
+#define SDHOST_DLL_CAL_STOP_V  0x00000001U
+#define SDHOST_DLL_CAL_STOP_S  0
+/** SDHOST_DLL_CAL_END : RO; bitpos: [1]; default: 0;
+ *  1 means calibration finished.
+ */
+#define SDHOST_DLL_CAL_END    (BIT(1))
+#define SDHOST_DLL_CAL_END_M  (SDHOST_DLL_CAL_END_V << SDHOST_DLL_CAL_END_S)
+#define SDHOST_DLL_CAL_END_V  0x00000001U
+#define SDHOST_DLL_CAL_END_S  1
+
+
+#define SDMMC_INTMASK_IO_SLOT1  BIT(17)
+#define SDMMC_INTMASK_IO_SLOT0  BIT(16)
+#define SDMMC_INTMASK_EBE       BIT(15)
+#define SDMMC_INTMASK_ACD       BIT(14)
+#define SDMMC_INTMASK_SBE       BIT(13)
+#define SDMMC_INTMASK_HLE       BIT(12)
+#define SDMMC_INTMASK_FRUN      BIT(11)
+#define SDMMC_INTMASK_HTO       BIT(10)
+#define SDMMC_INTMASK_VOLT_SW   SDMMC_INTMASK_HTO
+#define SDMMC_INTMASK_DTO       BIT(9)
+#define SDMMC_INTMASK_RTO       BIT(8)
+#define SDMMC_INTMASK_DCRC      BIT(7)
+#define SDMMC_INTMASK_RCRC      BIT(6)
+#define SDMMC_INTMASK_RXDR      BIT(5)
+#define SDMMC_INTMASK_TXDR      BIT(4)
+#define SDMMC_INTMASK_DATA_OVER BIT(3)
+#define SDMMC_INTMASK_CMD_DONE  BIT(2)
+#define SDMMC_INTMASK_RESP_ERR  BIT(1)
+#define SDMMC_INTMASK_CD        BIT(0)
+
+#define SDMMC_IDMAC_INTMASK_AI  BIT(9)
+#define SDMMC_IDMAC_INTMASK_NI  BIT(8)
+#define SDMMC_IDMAC_INTMASK_CES BIT(5)
+#define SDMMC_IDMAC_INTMASK_DU  BIT(4)
+#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
+#define SDMMC_IDMAC_INTMASK_RI  BIT(1)
+#define SDMMC_IDMAC_INTMASK_TI  BIT(0)
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/sdmmc_struct.h b/components/soc/esp32p4/register/soc/sdmmc_struct.h
similarity index 98%
rename from components/soc/esp32p4/include/soc/sdmmc_struct.h
rename to components/soc/esp32p4/register/soc/sdmmc_struct.h
index f9b5a5ed77b..6dd9dfc7af7 100644
--- a/components/soc/esp32p4/include/soc/sdmmc_struct.h
+++ b/components/soc/esp32p4/register/soc/sdmmc_struct.h
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
@@ -458,7 +458,13 @@ typedef union {
          *  not masked.
          */
         uint32_t ccs_expected:1;
-        uint32_t reserved_24:5;
+        uint32_t reserved_24:4;
+        /** volt_switch : R/W; bitpos: [28]; default: 0;
+         *  Voltage switch bit.
+         *  0: No voltage switching.
+         *  1: Voltage switching enabled; must be set for CMD11 only.
+         */
+        uint32_t volt_switch:1;
         /** use_hole_reg : R/W; bitpos: [29]; default: 1;
          *  Use Hold Register.
          *  0: CMD and DATA sent to card bypassing HOLD Register;
@@ -870,7 +876,7 @@ typedef union {
          */
         uint32_t bus_type_reg:1;
         /** data_width_reg : RO; bitpos: [9:7]; default: 1;
-         *  Regisger data widht is 32.
+         *  Regisger data width is 32.
          */
         uint32_t data_width_reg:3;
         /** addr_width_reg : RO; bitpos: [15:10]; default: 19;
@@ -879,7 +885,7 @@ typedef union {
         uint32_t addr_width_reg:6;
         uint32_t reserved_16:2;
         /** dma_width_reg : RO; bitpos: [20:18]; default: 1;
-         *  DMA data witdth is 32.
+         *  DMA data width is 32.
          */
         uint32_t dma_width_reg:3;
         /** ram_indise_reg : RO; bitpos: [21]; default: 0;
@@ -887,7 +893,7 @@ typedef union {
          */
         uint32_t ram_indise_reg:1;
         /** hold_reg : RO; bitpos: [22]; default: 1;
-         *  Have a hold regiser in data path .
+         *  Have a hold register in data path .
          */
         uint32_t hold_reg:1;
         uint32_t reserved_23:1;
@@ -907,11 +913,17 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:16;
-        /** ddr : R/W; bitpos: [17:16]; default: 0;
-         *  DDR mode selecton,1 bit for each card.
-         *  0-Non-DDR mdoe.
-         *  1-DDR mdoe.
+        /** volt: R/W; bitpos: [1:0]; default: 0;
+         *  Voltage mode selection, 1 bit for each card. On the ESP32-P4, this bit doesn't do anything, I/O voltage is controlled using LDO API instead.
+         *  0: 3.3V mode.
+         *  1: 1.8V mode.
+         */
+        uint32_t volt:2;
+        uint32_t reserved_0:14;
+        /** ddr: R/W; bitpos: [17:16]; default: 0;
+         *  DDR mode selection, 1 bit for each card.
+         *  0: Non-DDR mode.
+         *  1: DDR mode.
          */
         uint32_t ddr:2;
         uint32_t reserved_18:14;
diff --git a/components/soc/esp32p4/register/soc/sha_reg.h b/components/soc/esp32p4/register/soc/sha_reg.h
new file mode 100644
index 00000000000..40f4d53dfb0
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/sha_reg.h
@@ -0,0 +1,172 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SHA_MODE_REG register
+ *  Initial configuration register.
+ */
+#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
+/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Sha mode.
+ */
+#define SHA_MODE    0x00000007U
+#define SHA_MODE_M  (SHA_MODE_V << SHA_MODE_S)
+#define SHA_MODE_V  0x00000007U
+#define SHA_MODE_S  0
+
+/** SHA_T_STRING_REG register
+ *  SHA 512/t configuration register 0.
+ */
+#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
+/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
+ *  Sha t_string (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_STRING    0xFFFFFFFFU
+#define SHA_T_STRING_M  (SHA_T_STRING_V << SHA_T_STRING_S)
+#define SHA_T_STRING_V  0xFFFFFFFFU
+#define SHA_T_STRING_S  0
+
+/** SHA_T_LENGTH_REG register
+ *  SHA 512/t configuration register 1.
+ */
+#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
+/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
+ *  Sha t_length (used if and only if mode == SHA_512/t).
+ */
+#define SHA_T_LENGTH    0x0000003FU
+#define SHA_T_LENGTH_M  (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
+#define SHA_T_LENGTH_V  0x0000003FU
+#define SHA_T_LENGTH_S  0
+
+/** SHA_DMA_BLOCK_NUM_REG register
+ *  DMA configuration register 0.
+ */
+#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
+/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
+ *  Dma-sha block number.
+ */
+#define SHA_DMA_BLOCK_NUM    0x0000003FU
+#define SHA_DMA_BLOCK_NUM_M  (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
+#define SHA_DMA_BLOCK_NUM_V  0x0000003FU
+#define SHA_DMA_BLOCK_NUM_S  0
+
+/** SHA_START_REG register
+ *  Typical SHA configuration register 0.
+ */
+#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
+/** SHA_START : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_START    0x7FFFFFFFU
+#define SHA_START_M  (SHA_START_V << SHA_START_S)
+#define SHA_START_V  0x7FFFFFFFU
+#define SHA_START_S  1
+
+/** SHA_CONTINUE_REG register
+ *  Typical SHA configuration register 1.
+ */
+#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
+/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
+ *  Reserved.
+ */
+#define SHA_CONTINUE    0x7FFFFFFFU
+#define SHA_CONTINUE_M  (SHA_CONTINUE_V << SHA_CONTINUE_S)
+#define SHA_CONTINUE_V  0x7FFFFFFFU
+#define SHA_CONTINUE_S  1
+
+/** SHA_BUSY_REG register
+ *  Busy register.
+ */
+#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
+/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Sha busy state. 1'b0: idle. 1'b1: busy.
+ */
+#define SHA_BUSY_STATE    (BIT(0))
+#define SHA_BUSY_STATE_M  (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
+#define SHA_BUSY_STATE_V  0x00000001U
+#define SHA_BUSY_STATE_S  0
+
+/** SHA_DMA_START_REG register
+ *  DMA configuration register 1.
+ */
+#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
+/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
+ *  Start dma-sha.
+ */
+#define SHA_DMA_START    (BIT(0))
+#define SHA_DMA_START_M  (SHA_DMA_START_V << SHA_DMA_START_S)
+#define SHA_DMA_START_V  0x00000001U
+#define SHA_DMA_START_S  0
+
+/** SHA_DMA_CONTINUE_REG register
+ *  DMA configuration register 2.
+ */
+#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
+/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
+ *  Continue dma-sha.
+ */
+#define SHA_DMA_CONTINUE    (BIT(0))
+#define SHA_DMA_CONTINUE_M  (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
+#define SHA_DMA_CONTINUE_V  0x00000001U
+#define SHA_DMA_CONTINUE_S  0
+
+/** SHA_CLEAR_IRQ_REG register
+ *  Interrupt clear register.
+ */
+#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
+/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
+ *  Clear sha interrupt.
+ */
+#define SHA_CLEAR_INTERRUPT    (BIT(0))
+#define SHA_CLEAR_INTERRUPT_M  (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
+#define SHA_CLEAR_INTERRUPT_V  0x00000001U
+#define SHA_CLEAR_INTERRUPT_S  0
+
+/** SHA_IRQ_ENA_REG register
+ *  Interrupt enable register.
+ */
+#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
+/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+ */
+#define SHA_INTERRUPT_ENA    (BIT(0))
+#define SHA_INTERRUPT_ENA_M  (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
+#define SHA_INTERRUPT_ENA_V  0x00000001U
+#define SHA_INTERRUPT_ENA_S  0
+
+/** SHA_DATE_REG register
+ *  Date register.
+ */
+#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
+/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
+ *  Sha date information/ sha version information.
+ */
+#define SHA_DATE    0x3FFFFFFFU
+#define SHA_DATE_M  (SHA_DATE_V << SHA_DATE_S)
+#define SHA_DATE_V  0x3FFFFFFFU
+#define SHA_DATE_S  0
+
+/** SHA_H_MEM register
+ *  Sha H memory which contains intermediate hash or final hash.
+ */
+#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
+#define SHA_H_MEM_SIZE_BYTES 64
+
+/** SHA_M_MEM register
+ *  Sha M memory which contains message.
+ */
+#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
+#define SHA_M_MEM_SIZE_BYTES 64
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/sha_struct.h b/components/soc/esp32p4/register/soc/sha_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/sha_struct.h
rename to components/soc/esp32p4/register/soc/sha_struct.h
diff --git a/components/soc/esp32p4/include/soc/soc_etm_reg.h b/components/soc/esp32p4/register/soc/soc_etm_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/soc_etm_reg.h
rename to components/soc/esp32p4/register/soc/soc_etm_reg.h
diff --git a/components/soc/esp32p4/include/soc/soc_etm_struct.h b/components/soc/esp32p4/register/soc/soc_etm_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/soc_etm_struct.h
rename to components/soc/esp32p4/register/soc/soc_etm_struct.h
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h b/components/soc/esp32p4/register/soc/spi1_mem_c_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
rename to components/soc/esp32p4/register/soc/spi1_mem_c_reg.h
index e3bfc692140..eab9fa8a7e3 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_c_reg.h
+++ b/components/soc/esp32p4/register/soc/spi1_mem_c_reg.h
@@ -321,7 +321,7 @@ extern "C" {
 /** SPI1_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on.
+ *  SPI clock is always on.
  */
 #define SPI1_MEM_C_CLK_MODE    0x00000003U
 #define SPI1_MEM_C_CLK_MODE_M  (SPI1_MEM_C_CLK_MODE_V << SPI1_MEM_C_CLK_MODE_S)
@@ -1268,7 +1268,7 @@ extern "C" {
 #define SPI1_MEM_C_MST_ST_END_INT_RAW_S  4
 /** SPI1_MEM_C_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
  *  The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that
- *  chip is loosing power and RTC module sends out brown out close flash request to
+ *  chip is losing power and RTC module sends out brown out close flash request to
  *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  *  and MSPI returns to idle state. 0: Others.
  */
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h b/components/soc/esp32p4/register/soc/spi1_mem_c_struct.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
rename to components/soc/esp32p4/register/soc/spi1_mem_c_struct.h
index b78578c0825..6b08445b576 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_c_struct.h
+++ b/components/soc/esp32p4/register/soc/spi1_mem_c_struct.h
@@ -334,7 +334,7 @@ typedef union {
         /** clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on.
+         *  SPI clock is always on.
          */
         uint32_t clk_mode:2;
         /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
@@ -912,7 +912,7 @@ typedef union {
         uint32_t reserved_5:5;
         /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
          *  The raw bit for SPI1_MEM_C_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-         *  chip is loosing power and RTC module sends out brown out close flash request to
+         *  chip is losing power and RTC module sends out brown out close flash request to
          *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
          *  and MSPI returns to idle state. 0: Others.
          */
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_s_reg.h b/components/soc/esp32p4/register/soc/spi1_mem_s_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/spi1_mem_s_reg.h
rename to components/soc/esp32p4/register/soc/spi1_mem_s_reg.h
index 8aa91923ec7..9bc4517be9a 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_s_reg.h
+++ b/components/soc/esp32p4/register/soc/spi1_mem_s_reg.h
@@ -321,7 +321,7 @@ extern "C" {
 /** SPI1_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on.
+ *  SPI clock is always on.
  */
 #define SPI1_MEM_S_CLK_MODE    0x00000003U
 #define SPI1_MEM_S_CLK_MODE_M  (SPI1_MEM_S_CLK_MODE_V << SPI1_MEM_S_CLK_MODE_S)
@@ -1268,7 +1268,7 @@ extern "C" {
 #define SPI1_MEM_S_MST_ST_END_INT_RAW_S  4
 /** SPI1_MEM_S_BROWN_OUT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
  *  The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that
- *  chip is loosing power and RTC module sends out brown out close flash request to
+ *  chip is losing power and RTC module sends out brown out close flash request to
  *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
  *  and MSPI returns to idle state. 0: Others.
  */
diff --git a/components/soc/esp32p4/include/soc/spi1_mem_s_struct.h b/components/soc/esp32p4/register/soc/spi1_mem_s_struct.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/spi1_mem_s_struct.h
rename to components/soc/esp32p4/register/soc/spi1_mem_s_struct.h
index c2bb46eb9d2..5cbe96076ba 100644
--- a/components/soc/esp32p4/include/soc/spi1_mem_s_struct.h
+++ b/components/soc/esp32p4/register/soc/spi1_mem_s_struct.h
@@ -334,7 +334,7 @@ typedef union {
         /** clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on.
+         *  SPI clock is always on.
          */
         uint32_t clk_mode:2;
         /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023;
@@ -1123,7 +1123,7 @@ typedef union {
         uint32_t reserved_5:5;
         /** brown_out_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
          *  The raw bit for SPI1_MEM_S_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-         *  chip is loosing power and RTC module sends out brown out close flash request to
+         *  chip is losing power and RTC module sends out brown out close flash request to
          *  SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
          *  and MSPI returns to idle state. 0: Others.
          */
diff --git a/components/soc/esp32p4/include/soc/spi_mem_c_reg.h b/components/soc/esp32p4/register/soc/spi_mem_c_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/spi_mem_c_reg.h
rename to components/soc/esp32p4/register/soc/spi_mem_c_reg.h
index 89ff7ae9489..4b5c8c54e52 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_c_reg.h
+++ b/components/soc/esp32p4/register/soc/spi_mem_c_reg.h
@@ -199,7 +199,7 @@ extern "C" {
 /** SPI_MEM_C_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on.
+ *  SPI clock is always on.
  */
 #define SPI_MEM_C_CLK_MODE    0x00000003U
 #define SPI_MEM_C_CLK_MODE_M  (SPI_MEM_C_CLK_MODE_V << SPI_MEM_C_CLK_MODE_S)
@@ -2694,7 +2694,7 @@ extern "C" {
  */
 #define SPI_MEM_C_DPA_CTRL_REG (DR_REG_FLASH_SPI0_BASE + 0x388)
 /** SPI_MEM_C_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
- *  Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
+ *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
  *  The bigger the number is, the more secure the cryption is. (Note that the
  *  performance of cryption will decrease together with this number increasing)
  */
diff --git a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h b/components/soc/esp32p4/register/soc/spi_mem_c_struct.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/spi_mem_c_struct.h
rename to components/soc/esp32p4/register/soc/spi_mem_c_struct.h
index c694be7e0a3..61abcf05911 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_c_struct.h
+++ b/components/soc/esp32p4/register/soc/spi_mem_c_struct.h
@@ -167,7 +167,7 @@ typedef union {
         /** clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on.
+         *  SPI clock is always on.
          */
         uint32_t clk_mode:2;
         uint32_t reserved_2:19;
@@ -1908,7 +1908,7 @@ typedef union {
 typedef union {
     struct {
         /** crypt_security_level : R/W; bitpos: [2:0]; default: 7;
-         *  Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
+         *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
          *  The bigger the number is, the more secure the cryption is. (Note that the
          *  performance of cryption will decrease together with this number increasing)
          */
diff --git a/components/soc/esp32p4/include/soc/spi_mem_s_reg.h b/components/soc/esp32p4/register/soc/spi_mem_s_reg.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/spi_mem_s_reg.h
rename to components/soc/esp32p4/register/soc/spi_mem_s_reg.h
index 4e81aa49b4f..ec83145c771 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_s_reg.h
+++ b/components/soc/esp32p4/register/soc/spi_mem_s_reg.h
@@ -199,7 +199,7 @@ extern "C" {
 /** SPI_MEM_S_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
- *  SPI clock is alwasy on.
+ *  SPI clock is always on.
  */
 #define SPI_MEM_S_CLK_MODE    0x00000003U
 #define SPI_MEM_S_CLK_MODE_M  (SPI_MEM_S_CLK_MODE_V << SPI_MEM_S_CLK_MODE_S)
@@ -945,7 +945,7 @@ extern "C" {
 #define SPI_MEM_S_SCLKCNT_N_V  0x000000FFU
 #define SPI_MEM_S_SCLKCNT_N_S  16
 /** SPI_MEM_S_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0;
- *  For SPI0 external RAM  interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk
+ *  For SPI0 external RAM  interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk
  *  is divided from system clock.
  */
 #define SPI_MEM_S_SCLK_EQU_SYSCLK    (BIT(31))
@@ -3461,7 +3461,7 @@ extern "C" {
  */
 #define SPI_MEM_S_DPA_CTRL_REG (DR_REG_PSRAM_MSPI0_BASE + 0x388)
 /** SPI_MEM_S_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7;
- *  Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
+ *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
  *  The bigger the number is, the more secure the cryption is. (Note that the
  *  performance of cryption will decrease together with this number increasing)
  */
diff --git a/components/soc/esp32p4/include/soc/spi_mem_s_struct.h b/components/soc/esp32p4/register/soc/spi_mem_s_struct.h
similarity index 99%
rename from components/soc/esp32p4/include/soc/spi_mem_s_struct.h
rename to components/soc/esp32p4/register/soc/spi_mem_s_struct.h
index 691b30c6d7d..4948325c47c 100644
--- a/components/soc/esp32p4/include/soc/spi_mem_s_struct.h
+++ b/components/soc/esp32p4/register/soc/spi_mem_s_struct.h
@@ -167,7 +167,7 @@ typedef union {
         /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0;
          *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
          *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
-         *  SPI clock is alwasy on.
+         *  SPI clock is always on.
          */
         uint32_t mem_clk_mode:2;
         uint32_t reserved_2:19;
@@ -504,7 +504,7 @@ typedef union {
         uint32_t mem_sclkcnt_n:8;
         uint32_t reserved_24:7;
         /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0;
-         *  For SPI0 external RAM  interface, 1: spi_mem_s_clk is eqaul to system 0: spi_mem_s_clk
+         *  For SPI0 external RAM  interface, 1: spi_mem_s_clk is equal to system 0: spi_mem_s_clk
          *  is divided from system clock.
          */
         uint32_t mem_sclk_equ_sysclk:1;
@@ -2446,7 +2446,7 @@ typedef union {
 typedef union {
     struct {
         /** crypt_security_level : R/W; bitpos: [2:0]; default: 7;
-         *  Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7:
+         *  Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7:
          *  The bigger the number is, the more secure the cryption is. (Note that the
          *  performance of cryption will decrease together with this number increasing)
          */
diff --git a/components/soc/esp32p4/register/soc/spi_reg.h b/components/soc/esp32p4/register/soc/spi_reg.h
new file mode 100644
index 00000000000..ffce14740ee
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/spi_reg.h
@@ -0,0 +1,2152 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SPI_CMD_REG register
+ *  Command control register
+ */
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
+/** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CONF_BITLEN    0x0003FFFFU
+#define SPI_CONF_BITLEN_M  (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S)
+#define SPI_CONF_BITLEN_V  0x0003FFFFU
+#define SPI_CONF_BITLEN_S  0
+/** SPI_UPDATE : WT; bitpos: [23]; default: 0;
+ *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+ *  clock domain, which is only used in SPI master mode.
+ */
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (SPI_UPDATE_V << SPI_UPDATE_S)
+#define SPI_UPDATE_V  0x00000001U
+#define SPI_UPDATE_S  23
+/** SPI_USR : R/W/SC; bitpos: [24]; default: 0;
+ *  User define command enable.  An operation will be triggered when the bit is set.
+ *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+ *  changed by CONF_buf.
+ */
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (SPI_USR_V << SPI_USR_S)
+#define SPI_USR_V  0x00000001U
+#define SPI_USR_S  24
+
+/** SPI_ADDR_REG register
+ *  Address value register
+ */
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
+/** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
+ *  Address to slave. Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_M  (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S)
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFFU
+#define SPI_USR_ADDR_VALUE_S  0
+
+/** SPI_CTRL_REG register
+ *  SPI control register
+ */
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
+/** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
+ *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+ *  the FSPI bus signals are output. Can be configured in CONF state.
+ */
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S)
+#define SPI_DUMMY_OUT_V  0x00000001U
+#define SPI_DUMMY_OUT_S  3
+/** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0;
+ *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S)
+#define SPI_FADDR_DUAL_V  0x00000001U
+#define SPI_FADDR_DUAL_S  5
+/** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0;
+ *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S)
+#define SPI_FADDR_QUAD_V  0x00000001U
+#define SPI_FADDR_QUAD_S  6
+/** SPI_FADDR_OCT : R/W; bitpos: [7]; default: 0;
+ *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+//this field is only for GPSPI2
+#define SPI_FADDR_OCT    (BIT(7))
+#define SPI_FADDR_OCT_M  (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S)
+#define SPI_FADDR_OCT_V  0x00000001U
+#define SPI_FADDR_OCT_S  7
+/** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0;
+ *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S)
+#define SPI_FCMD_DUAL_V  0x00000001U
+#define SPI_FCMD_DUAL_S  8
+/** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0;
+ *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S)
+#define SPI_FCMD_QUAD_V  0x00000001U
+#define SPI_FCMD_QUAD_S  9
+/** SPI_FCMD_OCT : R/W; bitpos: [10]; default: 0;
+ *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+ *  state.
+ */
+//this field is only for GPSPI2
+#define SPI_FCMD_OCT    (BIT(10))
+#define SPI_FCMD_OCT_M  (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S)
+#define SPI_FCMD_OCT_V  0x00000001U
+#define SPI_FCMD_OCT_S  10
+/** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0;
+ *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S)
+#define SPI_FREAD_DUAL_V  0x00000001U
+#define SPI_FREAD_DUAL_S  14
+/** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0;
+ *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S)
+#define SPI_FREAD_QUAD_V  0x00000001U
+#define SPI_FREAD_QUAD_S  15
+/** SPI_FREAD_OCT : R/W; bitpos: [16]; default: 0;
+ *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+ *  be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_FREAD_OCT    (BIT(16))
+#define SPI_FREAD_OCT_M  (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S)
+#define SPI_FREAD_OCT_V  0x00000001U
+#define SPI_FREAD_OCT_S  16
+/** SPI_Q_POL : R/W; bitpos: [18]; default: 1;
+ *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (SPI_Q_POL_V << SPI_Q_POL_S)
+#define SPI_Q_POL_V  0x00000001U
+#define SPI_Q_POL_S  18
+/** SPI_D_POL : R/W; bitpos: [19]; default: 1;
+ *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+ *  CONF state.
+ */
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (SPI_D_POL_V << SPI_D_POL_S)
+#define SPI_D_POL_V  0x00000001U
+#define SPI_D_POL_S  19
+/** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1;
+ *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+ *  configured in CONF state.
+ */
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (SPI_HOLD_POL_V << SPI_HOLD_POL_S)
+#define SPI_HOLD_POL_V  0x00000001U
+#define SPI_HOLD_POL_S  20
+/** SPI_WP_POL : R/W; bitpos: [21]; default: 1;
+ *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+ *  be configured in CONF state.
+ */
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (SPI_WP_POL_V << SPI_WP_POL_S)
+#define SPI_WP_POL_V  0x00000001U
+#define SPI_WP_POL_S  21
+/** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0;
+ *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+ *  state.
+ */
+#define SPI_RD_BIT_ORDER    0x00000003U
+#define SPI_RD_BIT_ORDER_M  (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S)
+#define SPI_RD_BIT_ORDER_V  0x00000003U
+#define SPI_RD_BIT_ORDER_S  23
+/** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0;
+ *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+ *  configured in CONF state.
+ */
+#define SPI_WR_BIT_ORDER    0x00000003U
+#define SPI_WR_BIT_ORDER_M  (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S)
+#define SPI_WR_BIT_ORDER_V  0x00000003U
+#define SPI_WR_BIT_ORDER_S  25
+
+/** SPI_CLOCK_REG register
+ *  SPI clock control register
+ */
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
+/** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
+ *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+ *  0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_L    0x0000003FU
+#define SPI_CLKCNT_L_M  (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S)
+#define SPI_CLKCNT_L_V  0x0000003FU
+#define SPI_CLKCNT_L_S  0
+/** SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1;
+ *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+ *  must be 0. Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_H    0x0000003FU
+#define SPI_CLKCNT_H_M  (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S)
+#define SPI_CLKCNT_H_V  0x0000003FU
+#define SPI_CLKCNT_H_S  6
+/** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3;
+ *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+ *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+ */
+#define SPI_CLKCNT_N    0x0000003FU
+#define SPI_CLKCNT_N_M  (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S)
+#define SPI_CLKCNT_N_V  0x0000003FU
+#define SPI_CLKCNT_N_S  12
+/** SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0;
+ *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+ */
+#define SPI_CLKDIV_PRE    0x0000000FU
+#define SPI_CLKDIV_PRE_M  (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S)
+#define SPI_CLKDIV_PRE_V  0x0000000FU
+#define SPI_CLKDIV_PRE_S  18
+/** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
+ *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+ *  clock. Can be configured in CONF state.
+ */
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S)
+#define SPI_CLK_EQU_SYSCLK_V  0x00000001U
+#define SPI_CLK_EQU_SYSCLK_S  31
+
+/** SPI_USER_REG register
+ *  SPI USER control register
+ */
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
+/** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
+ *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (SPI_DOUTDIN_V << SPI_DOUTDIN_S)
+#define SPI_DOUTDIN_V  0x00000001U
+#define SPI_DOUTDIN_S  0
+/** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0;
+ *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+ *  Can be configured in CONF state.
+ */
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (SPI_QPI_MODE_V << SPI_QPI_MODE_S)
+#define SPI_QPI_MODE_V  0x00000001U
+#define SPI_QPI_MODE_S  3
+/** SPI_OPI_MODE : R/W; bitpos: [4]; default: 0;
+ *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+ *  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_OPI_MODE    (BIT(4))
+#define SPI_OPI_MODE_M  (SPI_OPI_MODE_V << SPI_OPI_MODE_S)
+#define SPI_OPI_MODE_V  0x00000001U
+#define SPI_OPI_MODE_S  4
+/** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+ *  spi_ck_i. 1:tsck = !spi_ck_i.
+ */
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S)
+#define SPI_TSCK_I_EDGE_V  0x00000001U
+#define SPI_TSCK_I_EDGE_S  5
+/** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1;
+ *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (SPI_CS_HOLD_V << SPI_CS_HOLD_S)
+#define SPI_CS_HOLD_V  0x00000001U
+#define SPI_CS_HOLD_S  6
+/** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1;
+ *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (SPI_CS_SETUP_V << SPI_CS_SETUP_S)
+#define SPI_CS_SETUP_V  0x00000001U
+#define SPI_CS_SETUP_S  7
+/** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0;
+ *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+ *  !spi_ck_i. 1:rsck = spi_ck_i.
+ */
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S)
+#define SPI_RSCK_I_EDGE_V  0x00000001U
+#define SPI_RSCK_I_EDGE_S  8
+/** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
+ *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S)
+#define SPI_CK_OUT_EDGE_V  0x00000001U
+#define SPI_CK_OUT_EDGE_S  9
+/** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0;
+ *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S)
+#define SPI_FWRITE_DUAL_V  0x00000001U
+#define SPI_FWRITE_DUAL_S  12
+/** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0;
+ *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+ *  state.
+ */
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S)
+#define SPI_FWRITE_QUAD_V  0x00000001U
+#define SPI_FWRITE_QUAD_S  13
+/** SPI_FWRITE_OCT : R/W; bitpos: [14]; default: 0;
+ *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+ *  state.
+ */
+//this field is only for GPSPI2
+#define SPI_FWRITE_OCT    (BIT(14))
+#define SPI_FWRITE_OCT_M  (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S)
+#define SPI_FWRITE_OCT_V  0x00000001U
+#define SPI_FWRITE_OCT_S  14
+/** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0;
+ *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+ *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+ *  not seg-trans mode. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S)
+#define SPI_USR_CONF_NXT_V  0x00000001U
+#define SPI_USR_CONF_NXT_S  15
+/** SPI_SIO : R/W; bitpos: [17]; default: 0;
+ *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+ *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+ */
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (SPI_SIO_V << SPI_SIO_S)
+#define SPI_SIO_V  0x00000001U
+#define SPI_SIO_S  17
+/** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0;
+ *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+ *  disable. Can be configured in CONF state.
+ */
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S)
+#define SPI_USR_MISO_HIGHPART_V  0x00000001U
+#define SPI_USR_MISO_HIGHPART_S  24
+/** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0;
+ *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ *  0: disable.  Can be configured in CONF state.
+ */
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S)
+#define SPI_USR_MOSI_HIGHPART_V  0x00000001U
+#define SPI_USR_MOSI_HIGHPART_S  25
+/** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0;
+ *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ *  CONF state.
+ */
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S)
+#define SPI_USR_DUMMY_IDLE_V  0x00000001U
+#define SPI_USR_DUMMY_IDLE_S  26
+/** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0;
+ *  This bit enable the write-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (SPI_USR_MOSI_V << SPI_USR_MOSI_S)
+#define SPI_USR_MOSI_V  0x00000001U
+#define SPI_USR_MOSI_S  27
+/** SPI_USR_MISO : R/W; bitpos: [28]; default: 0;
+ *  This bit enable the read-data phase of an operation. Can be configured in CONF
+ *  state.
+ */
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (SPI_USR_MISO_V << SPI_USR_MISO_S)
+#define SPI_USR_MISO_V  0x00000001U
+#define SPI_USR_MISO_S  28
+/** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0;
+ *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S)
+#define SPI_USR_DUMMY_V  0x00000001U
+#define SPI_USR_DUMMY_S  29
+/** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0;
+ *  This bit enable the address phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (SPI_USR_ADDR_V << SPI_USR_ADDR_S)
+#define SPI_USR_ADDR_V  0x00000001U
+#define SPI_USR_ADDR_S  30
+/** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1;
+ *  This bit enable the command phase of an operation. Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S)
+#define SPI_USR_COMMAND_V  0x00000001U
+#define SPI_USR_COMMAND_S  31
+
+/** SPI_USER1_REG register
+ *  SPI USER control register 1
+ */
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
+/** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
+ *  The length in spi_clk cycles of dummy phase. The register value shall be
+ *  (cycle_num-1). Can be configured in CONF state.
+ */
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_M  (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S)
+#define SPI_USR_DUMMY_CYCLELEN_V  0x000000FFU
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+/** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1;
+ *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+ *  GP-SPI master FD/HD-mode.
+ */
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S)
+#define SPI_MST_WFULL_ERR_END_EN_V  0x00000001U
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0;
+ *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+ *  bit. Can be configured in CONF state.
+ */
+#define SPI_CS_SETUP_TIME    0x0000001FU
+#define SPI_CS_SETUP_TIME_M  (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S)
+#define SPI_CS_SETUP_TIME_V  0x0000001FU
+#define SPI_CS_SETUP_TIME_S  17
+/** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1;
+ *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ *  Can be configured in CONF state.
+ */
+#define SPI_CS_HOLD_TIME    0x0000001FU
+#define SPI_CS_HOLD_TIME_M  (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S)
+#define SPI_CS_HOLD_TIME_V  0x0000001FU
+#define SPI_CS_HOLD_TIME_S  22
+/** SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23;
+ *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define SPI_USR_ADDR_BITLEN    0x0000001FU
+#define SPI_USR_ADDR_BITLEN_M  (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S)
+#define SPI_USR_ADDR_BITLEN_V  0x0000001FU
+#define SPI_USR_ADDR_BITLEN_S  27
+
+/** SPI_USER2_REG register
+ *  SPI USER control register 2
+ */
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
+/** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  The value of  command. Can be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_VALUE    0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_M  (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S)
+#define SPI_USR_COMMAND_VALUE_V  0x0000FFFFU
+#define SPI_USR_COMMAND_VALUE_S  0
+/** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1;
+ *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+ *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+ *  is valid in GP-SPI master FD/HD-mode.
+ */
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S)
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x00000001U
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/** SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7;
+ *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+ *  be configured in CONF state.
+ */
+#define SPI_USR_COMMAND_BITLEN    0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_M  (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S)
+#define SPI_USR_COMMAND_BITLEN_V  0x0000000FU
+#define SPI_USR_COMMAND_BITLEN_S  28
+
+/** SPI_MS_DLEN_REG register
+ *  SPI data bit length control register
+ */
+#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
+/** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
+ *  The value of these bits is the configured SPI transmission data bit length in
+ *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+ *  the configured bit length in slave mode DMA RX controlled transfer. The register
+ *  value shall be (bit_num-1). Can be configured in CONF state.
+ */
+#define SPI_MS_DATA_BITLEN    0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_M  (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S)
+#define SPI_MS_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_MS_DATA_BITLEN_S  0
+
+/** SPI_MISC_REG register
+ *  SPI misc register
+ */
+#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
+/** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (SPI_CS0_DIS_V << SPI_CS0_DIS_S)
+#define SPI_CS0_DIS_V  0x00000001U
+#define SPI_CS0_DIS_S  0
+/** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (SPI_CS1_DIS_V << SPI_CS1_DIS_S)
+#define SPI_CS1_DIS_V  0x00000001U
+#define SPI_CS1_DIS_S  1
+/** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (SPI_CS2_DIS_V << SPI_CS2_DIS_S)
+#define SPI_CS2_DIS_V  0x00000001U
+#define SPI_CS2_DIS_S  2
+/** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (SPI_CS3_DIS_V << SPI_CS3_DIS_S)
+#define SPI_CS3_DIS_V  0x00000001U
+#define SPI_CS3_DIS_S  3
+/** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (SPI_CS4_DIS_V << SPI_CS4_DIS_S)
+#define SPI_CS4_DIS_V  0x00000001U
+#define SPI_CS4_DIS_S  4
+/** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1;
+ *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+ *  be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (SPI_CS5_DIS_V << SPI_CS5_DIS_S)
+#define SPI_CS5_DIS_V  0x00000001U
+#define SPI_CS5_DIS_S  5
+/** SPI_CK_DIS : R/W; bitpos: [6]; default: 0;
+ *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+ */
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (SPI_CK_DIS_V << SPI_CK_DIS_S)
+#define SPI_CK_DIS_V  0x00000001U
+#define SPI_CK_DIS_S  6
+/** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0;
+ *  In the master mode the bits are the polarity of spi cs line, the value is
+ *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+ */
+//This field for GPSPI3 is only 3-bit-width
+#define SPI_MASTER_CS_POL    0x0000003FU
+#define SPI_MASTER_CS_POL_M  (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S)
+#define SPI_MASTER_CS_POL_V  0x0000003FU
+#define SPI_MASTER_CS_POL_S  7
+/** SPI_CLK_DATA_DTR_EN : R/W; bitpos: [16]; default: 0;
+ *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+ *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+ */
+//this field is only for GPSPI2
+#define SPI_CLK_DATA_DTR_EN    (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_M  (SPI_CLK_DATA_DTR_EN_V << SPI_CLK_DATA_DTR_EN_S)
+#define SPI_CLK_DATA_DTR_EN_V  0x00000001U
+#define SPI_CLK_DATA_DTR_EN_S  16
+/** SPI_DATA_DTR_EN : R/W; bitpos: [17]; default: 0;
+ *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+ *  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DATA_DTR_EN    (BIT(17))
+#define SPI_DATA_DTR_EN_M  (SPI_DATA_DTR_EN_V << SPI_DATA_DTR_EN_S)
+#define SPI_DATA_DTR_EN_V  0x00000001U
+#define SPI_DATA_DTR_EN_S  17
+/** SPI_ADDR_DTR_EN : R/W; bitpos: [18]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+ *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_ADDR_DTR_EN    (BIT(18))
+#define SPI_ADDR_DTR_EN_M  (SPI_ADDR_DTR_EN_V << SPI_ADDR_DTR_EN_S)
+#define SPI_ADDR_DTR_EN_V  0x00000001U
+#define SPI_ADDR_DTR_EN_S  18
+/** SPI_CMD_DTR_EN : R/W; bitpos: [19]; default: 0;
+ *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+ *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_CMD_DTR_EN    (BIT(19))
+#define SPI_CMD_DTR_EN_M  (SPI_CMD_DTR_EN_V << SPI_CMD_DTR_EN_S)
+#define SPI_CMD_DTR_EN_V  0x00000001U
+#define SPI_CMD_DTR_EN_S  19
+/** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0;
+ *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+ *  CONF state.
+ */
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S)
+#define SPI_SLAVE_CS_POL_V  0x00000001U
+#define SPI_SLAVE_CS_POL_S  23
+/** SPI_DQS_IDLE_EDGE : R/W; bitpos: [24]; default: 0;
+ *  The default value of spi_dqs. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DQS_IDLE_EDGE    (BIT(24))
+#define SPI_DQS_IDLE_EDGE_M  (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S)
+#define SPI_DQS_IDLE_EDGE_V  0x00000001U
+#define SPI_DQS_IDLE_EDGE_S  24
+/** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0;
+ *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+ *  configured in CONF state.
+ */
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S)
+#define SPI_CK_IDLE_EDGE_V  0x00000001U
+#define SPI_CK_IDLE_EDGE_S  29
+/** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0;
+ *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+ */
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S)
+#define SPI_CS_KEEP_ACTIVE_V  0x00000001U
+#define SPI_CS_KEEP_ACTIVE_S  30
+/** SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0;
+ *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+ *  spi quad input swap disable. Can be configured in CONF state.
+ */
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S)
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x00000001U
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+
+/** SPI_DIN_MODE_REG register
+ *  SPI input delay mode configuration
+ */
+#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
+/** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN0_MODE    0x00000003U
+#define SPI_DIN0_MODE_M  (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S)
+#define SPI_DIN0_MODE_V  0x00000003U
+#define SPI_DIN0_MODE_S  0
+/** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN1_MODE    0x00000003U
+#define SPI_DIN1_MODE_M  (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S)
+#define SPI_DIN1_MODE_V  0x00000003U
+#define SPI_DIN1_MODE_S  2
+/** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN2_MODE    0x00000003U
+#define SPI_DIN2_MODE_M  (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S)
+#define SPI_DIN2_MODE_V  0x00000003U
+#define SPI_DIN2_MODE_S  4
+/** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+#define SPI_DIN3_MODE    0x00000003U
+#define SPI_DIN3_MODE_M  (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S)
+#define SPI_DIN3_MODE_V  0x00000003U
+#define SPI_DIN3_MODE_S  6
+/** SPI_DIN4_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN4_MODE    0x00000003U
+#define SPI_DIN4_MODE_M  (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S)
+#define SPI_DIN4_MODE_V  0x00000003U
+#define SPI_DIN4_MODE_S  8
+/** SPI_DIN5_MODE : R/W; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN5_MODE    0x00000003U
+#define SPI_DIN5_MODE_M  (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S)
+#define SPI_DIN5_MODE_V  0x00000003U
+#define SPI_DIN5_MODE_S  10
+/** SPI_DIN6_MODE : R/W; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN6_MODE    0x00000003U
+#define SPI_DIN6_MODE_M  (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S)
+#define SPI_DIN6_MODE_V  0x00000003U
+#define SPI_DIN6_MODE_S  12
+/** SPI_DIN7_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+ *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+ *  with the spi_clk. Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN7_MODE    0x00000003U
+#define SPI_DIN7_MODE_M  (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S)
+#define SPI_DIN7_MODE_V  0x00000003U
+#define SPI_DIN7_MODE_S  14
+/** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0;
+ *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+ *  state.
+ */
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S)
+#define SPI_TIMING_HCLK_ACTIVE_V  0x00000001U
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+
+/** SPI_DIN_NUM_REG register
+ *  SPI input delay number configuration
+ */
+#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
+/** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN0_NUM    0x00000003U
+#define SPI_DIN0_NUM_M  (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S)
+#define SPI_DIN0_NUM_V  0x00000003U
+#define SPI_DIN0_NUM_S  0
+/** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN1_NUM    0x00000003U
+#define SPI_DIN1_NUM_M  (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S)
+#define SPI_DIN1_NUM_V  0x00000003U
+#define SPI_DIN1_NUM_S  2
+/** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN2_NUM    0x00000003U
+#define SPI_DIN2_NUM_M  (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S)
+#define SPI_DIN2_NUM_V  0x00000003U
+#define SPI_DIN2_NUM_S  4
+/** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+#define SPI_DIN3_NUM    0x00000003U
+#define SPI_DIN3_NUM_M  (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S)
+#define SPI_DIN3_NUM_V  0x00000003U
+#define SPI_DIN3_NUM_S  6
+/** SPI_DIN4_NUM : R/W; bitpos: [9:8]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN4_NUM    0x00000003U
+#define SPI_DIN4_NUM_M  (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S)
+#define SPI_DIN4_NUM_V  0x00000003U
+#define SPI_DIN4_NUM_S  8
+/** SPI_DIN5_NUM : R/W; bitpos: [11:10]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN5_NUM    0x00000003U
+#define SPI_DIN5_NUM_M  (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S)
+#define SPI_DIN5_NUM_V  0x00000003U
+#define SPI_DIN5_NUM_S  10
+/** SPI_DIN6_NUM : R/W; bitpos: [13:12]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN6_NUM    0x00000003U
+#define SPI_DIN6_NUM_M  (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S)
+#define SPI_DIN6_NUM_V  0x00000003U
+#define SPI_DIN6_NUM_S  12
+/** SPI_DIN7_NUM : R/W; bitpos: [15:14]; default: 0;
+ *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+ *  delayed by 2 cycles,...  Can be configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DIN7_NUM    0x00000003U
+#define SPI_DIN7_NUM_M  (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S)
+#define SPI_DIN7_NUM_V  0x00000003U
+#define SPI_DIN7_NUM_S  14
+
+/** SPI_DOUT_MODE_REG register
+ *  SPI output delay mode configuration
+ */
+#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
+/** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S)
+#define SPI_DOUT0_MODE_V  0x00000001U
+#define SPI_DOUT0_MODE_S  0
+/** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S)
+#define SPI_DOUT1_MODE_V  0x00000001U
+#define SPI_DOUT1_MODE_S  1
+/** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S)
+#define SPI_DOUT2_MODE_V  0x00000001U
+#define SPI_DOUT2_MODE_S  2
+/** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S)
+#define SPI_DOUT3_MODE_V  0x00000001U
+#define SPI_DOUT3_MODE_S  3
+/** SPI_DOUT4_MODE : R/W; bitpos: [4]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DOUT4_MODE    (BIT(4))
+#define SPI_DOUT4_MODE_M  (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S)
+#define SPI_DOUT4_MODE_V  0x00000001U
+#define SPI_DOUT4_MODE_S  4
+/** SPI_DOUT5_MODE : R/W; bitpos: [5]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DOUT5_MODE    (BIT(5))
+#define SPI_DOUT5_MODE_M  (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S)
+#define SPI_DOUT5_MODE_V  0x00000001U
+#define SPI_DOUT5_MODE_S  5
+/** SPI_DOUT6_MODE : R/W; bitpos: [6]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DOUT6_MODE    (BIT(6))
+#define SPI_DOUT6_MODE_M  (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S)
+#define SPI_DOUT6_MODE_V  0x00000001U
+#define SPI_DOUT6_MODE_S  6
+/** SPI_DOUT7_MODE : R/W; bitpos: [7]; default: 0;
+ *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+ *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_DOUT7_MODE    (BIT(7))
+#define SPI_DOUT7_MODE_M  (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S)
+#define SPI_DOUT7_MODE_V  0x00000001U
+#define SPI_DOUT7_MODE_S  7
+/** SPI_D_DQS_MODE : R/W; bitpos: [8]; default: 0;
+ *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+ *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+ *  configured in CONF state.
+ */
+//this field is only for GPSPI2
+#define SPI_D_DQS_MODE    (BIT(8))
+#define SPI_D_DQS_MODE_M  (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S)
+#define SPI_D_DQS_MODE_V  0x00000001U
+#define SPI_D_DQS_MODE_S  8
+
+/** SPI_DMA_CONF_REG register
+ *  SPI DMA control register
+ */
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
+/** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
+ *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+ *  DMA TX FIFO is ready for sending data.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S)
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
+/** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1;
+ *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+ *  0: DMA RX FIFO is ready for receiving data.
+ */
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S)
+#define SPI_DMA_INFIFO_FULL_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_S  1
+/** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0;
+ *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+ */
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S)
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x00000001U
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0;
+ *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+ *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+ */
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0;
+ *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+ *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+ */
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S)
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x00000001U
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/** SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0;
+ *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+ *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+ *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+ *  spi_dma_seg_trans_done in seg-trans.
+ */
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S)
+#define SPI_RX_EOF_EN_V  0x00000001U
+#define SPI_RX_EOF_EN_S  21
+/** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to enable SPI DMA controlled receive data mode.
+ */
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S)
+#define SPI_DMA_RX_ENA_V  0x00000001U
+#define SPI_DMA_RX_ENA_S  27
+/** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to enable SPI DMA controlled send data mode.
+ */
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S)
+#define SPI_DMA_TX_ENA_V  0x00000001U
+#define SPI_DMA_TX_ENA_S  28
+/** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0;
+ *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+ *  slave mode transfer.
+ */
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S)
+#define SPI_RX_AFIFO_RST_V  0x00000001U
+#define SPI_RX_AFIFO_RST_S  29
+/** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0;
+ *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ *  controlled mode transfer and master mode transfer.
+ */
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S)
+#define SPI_BUF_AFIFO_RST_V  0x00000001U
+#define SPI_BUF_AFIFO_RST_S  30
+/** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+ *  controlled mode transfer.
+ */
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S)
+#define SPI_DMA_AFIFO_RST_V  0x00000001U
+#define SPI_DMA_AFIFO_RST_S  31
+
+/** SPI_DMA_INT_ENA_REG register
+ *  SPI interrupt enable register
+ */
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/** SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S)
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/** SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S)
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/** SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S)
+#define SPI_SLV_CMD7_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/** SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S)
+#define SPI_SLV_CMD8_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/** SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S)
+#define SPI_SLV_CMD9_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/** SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S)
+#define SPI_SLV_CMDA_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/** SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S)
+#define SPI_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S)
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/** SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S)
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/** SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S)
+#define SPI_APP2_INT_ENA_V  0x00000001U
+#define SPI_APP2_INT_ENA_S  19
+/** SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S)
+#define SPI_APP1_INT_ENA_V  0x00000001U
+#define SPI_APP1_INT_ENA_S  20
+
+/** SPI_DMA_INT_CLR_REG register
+ *  SPI interrupt clear register
+ */
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/** SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  The clear bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S)
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/** SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  The clear bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S)
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/** SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The clear bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S)
+#define SPI_SLV_CMD7_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/** SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The clear bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S)
+#define SPI_SLV_CMD8_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/** SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The clear bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S)
+#define SPI_SLV_CMD9_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/** SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The clear bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S)
+#define SPI_SLV_CMDA_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S)
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S)
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/** SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The clear bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S)
+#define SPI_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/** SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S)
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/** SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S)
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/** SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  The clear bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S)
+#define SPI_APP2_INT_CLR_V  0x00000001U
+#define SPI_APP2_INT_CLR_S  19
+/** SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  The clear bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S)
+#define SPI_APP1_INT_CLR_V  0x00000001U
+#define SPI_APP1_INT_CLR_S  20
+
+/** SPI_DMA_INT_RAW_REG register
+ *  SPI interrupt raw register
+ */
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+ *  receive data.  0: Others.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ *  master mode and send out all 0 in slave mode.  0: Others.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/** SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+ *  is ended. 0: Others.
+ */
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S)
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/** SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+ *  is ended. 0: Others.
+ */
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S)
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/** SPI_SLV_CMD7_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S)
+#define SPI_SLV_CMD7_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/** SPI_SLV_CMD8_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S)
+#define SPI_SLV_CMD8_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/** SPI_SLV_CMD9_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S)
+#define SPI_SLV_CMD9_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/** SPI_SLV_CMDA_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ *  ended. 0: Others.
+ */
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S)
+#define SPI_SLV_CMDA_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S)
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+ *  transmission is ended. 0: Others.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S)
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/** SPI_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ *  ended. 0: others.
+ */
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S)
+#define SPI_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+ *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+ *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+ *  is not ended or not occurred.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/** SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+ *  is error in the DMA seg-conf-trans. 0: others.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S)
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+ *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+ *  bigger than 63. 0: Others.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/** SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ *  current SPI slave HD mode transmission is not supported. 0: Others.
+ */
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S)
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ *  write-full error when SPI inputs data in master mode. 0: Others.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+ *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/** SPI_APP2_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+ */
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S)
+#define SPI_APP2_INT_RAW_V  0x00000001U
+#define SPI_APP2_INT_RAW_S  19
+/** SPI_APP1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+ */
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S)
+#define SPI_APP1_INT_RAW_V  0x00000001U
+#define SPI_APP1_INT_RAW_S  20
+
+/** SPI_DMA_INT_ST_REG register
+ *  SPI interrupt status register
+ */
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/** SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The status bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S)
+#define SPI_SLV_EX_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/** SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The status bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S)
+#define SPI_SLV_EN_QPI_INT_ST_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/** SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The status bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S)
+#define SPI_SLV_CMD7_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD7_INT_ST_S  4
+/** SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The status bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S)
+#define SPI_SLV_CMD8_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD8_INT_ST_S  5
+/** SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The status bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S)
+#define SPI_SLV_CMD9_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD9_INT_ST_S  6
+/** SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The status bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S)
+#define SPI_SLV_CMDA_INT_ST_V  0x00000001U
+#define SPI_SLV_CMDA_INT_ST_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S)
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S)
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S)
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S)
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/** SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The status bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S)
+#define SPI_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_TRANS_DONE_INT_ST_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/** SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S)
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/** SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S)
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/** SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The status bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S)
+#define SPI_APP2_INT_ST_V  0x00000001U
+#define SPI_APP2_INT_ST_S  19
+/** SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The status bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S)
+#define SPI_APP1_INT_ST_V  0x00000001U
+#define SPI_APP1_INT_ST_S  20
+
+/** SPI_DMA_INT_SET_REG register
+ *  SPI interrupt software set register
+ */
+#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
+/** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
+ *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+ */
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (SPI_DMA_INFIFO_FULL_ERR_INT_SET_V << SPI_DMA_INFIFO_FULL_ERR_INT_SET_S)
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
+/** SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT; bitpos: [1]; default: 0;
+ *  The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+ */
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S)
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
+/** SPI_SLV_EX_QPI_INT_SET : WT; bitpos: [2]; default: 0;
+ *  The software set bit for SPI slave Ex_QPI interrupt.
+ */
+#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_M  (SPI_SLV_EX_QPI_INT_SET_V << SPI_SLV_EX_QPI_INT_SET_S)
+#define SPI_SLV_EX_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EX_QPI_INT_SET_S  2
+/** SPI_SLV_EN_QPI_INT_SET : WT; bitpos: [3]; default: 0;
+ *  The software set bit for SPI slave En_QPI interrupt.
+ */
+#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_M  (SPI_SLV_EN_QPI_INT_SET_V << SPI_SLV_EN_QPI_INT_SET_S)
+#define SPI_SLV_EN_QPI_INT_SET_V  0x00000001U
+#define SPI_SLV_EN_QPI_INT_SET_S  3
+/** SPI_SLV_CMD7_INT_SET : WT; bitpos: [4]; default: 0;
+ *  The software set bit for SPI slave CMD7 interrupt.
+ */
+#define SPI_SLV_CMD7_INT_SET    (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_M  (SPI_SLV_CMD7_INT_SET_V << SPI_SLV_CMD7_INT_SET_S)
+#define SPI_SLV_CMD7_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD7_INT_SET_S  4
+/** SPI_SLV_CMD8_INT_SET : WT; bitpos: [5]; default: 0;
+ *  The software set bit for SPI slave CMD8 interrupt.
+ */
+#define SPI_SLV_CMD8_INT_SET    (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_M  (SPI_SLV_CMD8_INT_SET_V << SPI_SLV_CMD8_INT_SET_S)
+#define SPI_SLV_CMD8_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD8_INT_SET_S  5
+/** SPI_SLV_CMD9_INT_SET : WT; bitpos: [6]; default: 0;
+ *  The software set bit for SPI slave CMD9 interrupt.
+ */
+#define SPI_SLV_CMD9_INT_SET    (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_M  (SPI_SLV_CMD9_INT_SET_V << SPI_SLV_CMD9_INT_SET_S)
+#define SPI_SLV_CMD9_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD9_INT_SET_S  6
+/** SPI_SLV_CMDA_INT_SET : WT; bitpos: [7]; default: 0;
+ *  The software set bit for SPI slave CMDA interrupt.
+ */
+#define SPI_SLV_CMDA_INT_SET    (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_M  (SPI_SLV_CMDA_INT_SET_V << SPI_SLV_CMDA_INT_SET_S)
+#define SPI_SLV_CMDA_INT_SET_V  0x00000001U
+#define SPI_SLV_CMDA_INT_SET_S  7
+/** SPI_SLV_RD_DMA_DONE_INT_SET : WT; bitpos: [8]; default: 0;
+ *  The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (SPI_SLV_RD_DMA_DONE_INT_SET_V << SPI_SLV_RD_DMA_DONE_INT_SET_S)
+#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
+/** SPI_SLV_WR_DMA_DONE_INT_SET : WT; bitpos: [9]; default: 0;
+ *  The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (SPI_SLV_WR_DMA_DONE_INT_SET_V << SPI_SLV_WR_DMA_DONE_INT_SET_S)
+#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
+/** SPI_SLV_RD_BUF_DONE_INT_SET : WT; bitpos: [10]; default: 0;
+ *  The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (SPI_SLV_RD_BUF_DONE_INT_SET_V << SPI_SLV_RD_BUF_DONE_INT_SET_S)
+#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/** SPI_SLV_WR_BUF_DONE_INT_SET : WT; bitpos: [11]; default: 0;
+ *  The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+ */
+#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (SPI_SLV_WR_BUF_DONE_INT_SET_V << SPI_SLV_WR_BUF_DONE_INT_SET_S)
+#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x00000001U
+#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/** SPI_TRANS_DONE_INT_SET : WT; bitpos: [12]; default: 0;
+ *  The software set bit for SPI_TRANS_DONE_INT interrupt.
+ */
+#define SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_M  (SPI_TRANS_DONE_INT_SET_V << SPI_TRANS_DONE_INT_SET_S)
+#define SPI_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_TRANS_DONE_INT_SET_S  12
+/** SPI_DMA_SEG_TRANS_DONE_INT_SET : WT; bitpos: [13]; default: 0;
+ *  The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+ */
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (SPI_DMA_SEG_TRANS_DONE_INT_SET_V << SPI_DMA_SEG_TRANS_DONE_INT_SET_S)
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x00000001U
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
+/** SPI_SEG_MAGIC_ERR_INT_SET : WT; bitpos: [14]; default: 0;
+ *  The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+ */
+//this field is only for GPSPI2
+#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_M  (SPI_SEG_MAGIC_ERR_INT_SET_V << SPI_SEG_MAGIC_ERR_INT_SET_S)
+#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x00000001U
+#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
+/** SPI_SLV_BUF_ADDR_ERR_INT_SET : WT; bitpos: [15]; default: 0;
+ *  The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+ */
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (SPI_SLV_BUF_ADDR_ERR_INT_SET_V << SPI_SLV_BUF_ADDR_ERR_INT_SET_S)
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/** SPI_SLV_CMD_ERR_INT_SET : WT; bitpos: [16]; default: 0;
+ *  The software set bit for SPI_SLV_CMD_ERR_INT interrupt.
+ */
+#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_M  (SPI_SLV_CMD_ERR_INT_SET_V << SPI_SLV_CMD_ERR_INT_SET_S)
+#define SPI_SLV_CMD_ERR_INT_SET_V  0x00000001U
+#define SPI_SLV_CMD_ERR_INT_SET_S  16
+/** SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT; bitpos: [17]; default: 0;
+ *  The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+ */
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S)
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/** SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT; bitpos: [18]; default: 0;
+ *  The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+ */
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S)
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x00000001U
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/** SPI_APP2_INT_SET : WT; bitpos: [19]; default: 0;
+ *  The software set bit for SPI_APP2_INT interrupt.
+ */
+#define SPI_APP2_INT_SET    (BIT(19))
+#define SPI_APP2_INT_SET_M  (SPI_APP2_INT_SET_V << SPI_APP2_INT_SET_S)
+#define SPI_APP2_INT_SET_V  0x00000001U
+#define SPI_APP2_INT_SET_S  19
+/** SPI_APP1_INT_SET : WT; bitpos: [20]; default: 0;
+ *  The software set bit for SPI_APP1_INT interrupt.
+ */
+#define SPI_APP1_INT_SET    (BIT(20))
+#define SPI_APP1_INT_SET_M  (SPI_APP1_INT_SET_V << SPI_APP1_INT_SET_S)
+#define SPI_APP1_INT_SET_V  0x00000001U
+#define SPI_APP1_INT_SET_S  20
+
+/** SPI_W0_REG register
+ *  SPI CPU-controlled buffer0
+ */
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
+/** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF0    0xFFFFFFFFU
+#define SPI_BUF0_M  (SPI_BUF0_V << SPI_BUF0_S)
+#define SPI_BUF0_V  0xFFFFFFFFU
+#define SPI_BUF0_S  0
+
+/** SPI_W1_REG register
+ *  SPI CPU-controlled buffer1
+ */
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
+/** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF1    0xFFFFFFFFU
+#define SPI_BUF1_M  (SPI_BUF1_V << SPI_BUF1_S)
+#define SPI_BUF1_V  0xFFFFFFFFU
+#define SPI_BUF1_S  0
+
+/** SPI_W2_REG register
+ *  SPI CPU-controlled buffer2
+ */
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
+/** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF2    0xFFFFFFFFU
+#define SPI_BUF2_M  (SPI_BUF2_V << SPI_BUF2_S)
+#define SPI_BUF2_V  0xFFFFFFFFU
+#define SPI_BUF2_S  0
+
+/** SPI_W3_REG register
+ *  SPI CPU-controlled buffer3
+ */
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
+/** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF3    0xFFFFFFFFU
+#define SPI_BUF3_M  (SPI_BUF3_V << SPI_BUF3_S)
+#define SPI_BUF3_V  0xFFFFFFFFU
+#define SPI_BUF3_S  0
+
+/** SPI_W4_REG register
+ *  SPI CPU-controlled buffer4
+ */
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
+/** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF4    0xFFFFFFFFU
+#define SPI_BUF4_M  (SPI_BUF4_V << SPI_BUF4_S)
+#define SPI_BUF4_V  0xFFFFFFFFU
+#define SPI_BUF4_S  0
+
+/** SPI_W5_REG register
+ *  SPI CPU-controlled buffer5
+ */
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
+/** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF5    0xFFFFFFFFU
+#define SPI_BUF5_M  (SPI_BUF5_V << SPI_BUF5_S)
+#define SPI_BUF5_V  0xFFFFFFFFU
+#define SPI_BUF5_S  0
+
+/** SPI_W6_REG register
+ *  SPI CPU-controlled buffer6
+ */
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
+/** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF6    0xFFFFFFFFU
+#define SPI_BUF6_M  (SPI_BUF6_V << SPI_BUF6_S)
+#define SPI_BUF6_V  0xFFFFFFFFU
+#define SPI_BUF6_S  0
+
+/** SPI_W7_REG register
+ *  SPI CPU-controlled buffer7
+ */
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
+/** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF7    0xFFFFFFFFU
+#define SPI_BUF7_M  (SPI_BUF7_V << SPI_BUF7_S)
+#define SPI_BUF7_V  0xFFFFFFFFU
+#define SPI_BUF7_S  0
+
+/** SPI_W8_REG register
+ *  SPI CPU-controlled buffer8
+ */
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
+/** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF8    0xFFFFFFFFU
+#define SPI_BUF8_M  (SPI_BUF8_V << SPI_BUF8_S)
+#define SPI_BUF8_V  0xFFFFFFFFU
+#define SPI_BUF8_S  0
+
+/** SPI_W9_REG register
+ *  SPI CPU-controlled buffer9
+ */
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
+/** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF9    0xFFFFFFFFU
+#define SPI_BUF9_M  (SPI_BUF9_V << SPI_BUF9_S)
+#define SPI_BUF9_V  0xFFFFFFFFU
+#define SPI_BUF9_S  0
+
+/** SPI_W10_REG register
+ *  SPI CPU-controlled buffer10
+ */
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
+/** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF10    0xFFFFFFFFU
+#define SPI_BUF10_M  (SPI_BUF10_V << SPI_BUF10_S)
+#define SPI_BUF10_V  0xFFFFFFFFU
+#define SPI_BUF10_S  0
+
+/** SPI_W11_REG register
+ *  SPI CPU-controlled buffer11
+ */
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
+/** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF11    0xFFFFFFFFU
+#define SPI_BUF11_M  (SPI_BUF11_V << SPI_BUF11_S)
+#define SPI_BUF11_V  0xFFFFFFFFU
+#define SPI_BUF11_S  0
+
+/** SPI_W12_REG register
+ *  SPI CPU-controlled buffer12
+ */
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
+/** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF12    0xFFFFFFFFU
+#define SPI_BUF12_M  (SPI_BUF12_V << SPI_BUF12_S)
+#define SPI_BUF12_V  0xFFFFFFFFU
+#define SPI_BUF12_S  0
+
+/** SPI_W13_REG register
+ *  SPI CPU-controlled buffer13
+ */
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
+/** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF13    0xFFFFFFFFU
+#define SPI_BUF13_M  (SPI_BUF13_V << SPI_BUF13_S)
+#define SPI_BUF13_V  0xFFFFFFFFU
+#define SPI_BUF13_S  0
+
+/** SPI_W14_REG register
+ *  SPI CPU-controlled buffer14
+ */
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
+/** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF14    0xFFFFFFFFU
+#define SPI_BUF14_M  (SPI_BUF14_V << SPI_BUF14_S)
+#define SPI_BUF14_V  0xFFFFFFFFU
+#define SPI_BUF14_S  0
+
+/** SPI_W15_REG register
+ *  SPI CPU-controlled buffer15
+ */
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
+/** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
+ *  data buffer
+ */
+#define SPI_BUF15    0xFFFFFFFFU
+#define SPI_BUF15_M  (SPI_BUF15_V << SPI_BUF15_S)
+#define SPI_BUF15_V  0xFFFFFFFFU
+#define SPI_BUF15_S  0
+
+/** SPI_SLAVE_REG register
+ *  SPI slave control register
+ */
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
+/** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+ *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+ *  SPI clock is always on. Can be configured in CONF state.
+ */
+#define SPI_CLK_MODE    0x00000003U
+#define SPI_CLK_MODE_M  (SPI_CLK_MODE_V << SPI_CLK_MODE_S)
+#define SPI_CLK_MODE_V  0x00000003U
+#define SPI_CLK_MODE_S  0
+/** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0;
+ *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+ *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+ */
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S)
+#define SPI_CLK_MODE_13_V  0x00000001U
+#define SPI_CLK_MODE_13_S  2
+/** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0;
+ *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+ *  0: output data at tsck posedge
+ */
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S)
+#define SPI_RSCK_DATA_OUT_V  0x00000001U
+#define SPI_RSCK_DATA_OUT_S  3
+/** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  DMA controlled mode(Rd_DMA). 0: others
+ */
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S)
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in DMA controlled mode(Wr_DMA). 0: others
+ */
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S)
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+ *  CPU controlled mode(Rd_BUF). 0: others
+ */
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S)
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0;
+ *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+ *  in CPU controlled mode(Wr_BUF). 0: others
+ */
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S)
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x00000001U
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/** SPI_SLV_LAST_BYTE_STRB : R/SS; bitpos: [19:12]; default: 0;
+ *  Represents the effective bit of the last received data byte in SPI slave FD and HD
+ *  mode.
+ */
+#define SPI_SLV_LAST_BYTE_STRB    0x000000FFU
+#define SPI_SLV_LAST_BYTE_STRB_M  (SPI_SLV_LAST_BYTE_STRB_V << SPI_SLV_LAST_BYTE_STRB_S)
+#define SPI_SLV_LAST_BYTE_STRB_V  0x000000FFU
+#define SPI_SLV_LAST_BYTE_STRB_S  12
+/** SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10;
+ *  The magic value of BM table in master DMA seg-trans.
+ */
+//this field is only for GPSPI2
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_M  (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S)
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0x0000000FU
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0;
+ *  Set SPI work mode. 1: slave mode 0: master mode.
+ */
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S)
+#define SPI_SLAVE_MODE_V  0x00000001U
+#define SPI_SLAVE_MODE_S  26
+/** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0;
+ *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+ *  configured in CONF state.
+ */
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S)
+#define SPI_SOFT_RESET_V  0x00000001U
+#define SPI_SOFT_RESET_S  27
+/** SPI_USR_CONF : R/W; bitpos: [28]; default: 0;
+ *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+ *  will start. 0: This is not seg-trans mode.
+ */
+//this field is only for GPSPI2
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (SPI_USR_CONF_V << SPI_USR_CONF_S)
+#define SPI_USR_CONF_V  0x00000001U
+#define SPI_USR_CONF_S  28
+/** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0;
+ *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+ *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+ *  transfer.
+ */
+#define SPI_MST_FD_WAIT_DMA_TX_DATA    (BIT(29))
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_M  (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S)
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_V  0x00000001U
+#define SPI_MST_FD_WAIT_DMA_TX_DATA_S  29
+
+/** SPI_SLAVE1_REG register
+ *  SPI slave control register 1
+ */
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
+/** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
+ *  The transferred data bit length in SPI slave FD and HD mode.
+ */
+#define SPI_SLV_DATA_BITLEN    0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_M  (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S)
+#define SPI_SLV_DATA_BITLEN_V  0x0003FFFFU
+#define SPI_SLV_DATA_BITLEN_S  0
+/** SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0;
+ *  In the slave mode it is the value of command.
+ */
+#define SPI_SLV_LAST_COMMAND    0x000000FFU
+#define SPI_SLV_LAST_COMMAND_M  (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S)
+#define SPI_SLV_LAST_COMMAND_V  0x000000FFU
+#define SPI_SLV_LAST_COMMAND_S  18
+/** SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0;
+ *  In the slave mode it is the value of address.
+ */
+#define SPI_SLV_LAST_ADDR    0x0000003FU
+#define SPI_SLV_LAST_ADDR_M  (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S)
+#define SPI_SLV_LAST_ADDR_V  0x0000003FU
+#define SPI_SLV_LAST_ADDR_S  26
+
+/** SPI_CLK_GATE_REG register
+ *  SPI module clock and register clock control
+ */
+#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
+/** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable clk gate
+ */
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (SPI_CLK_EN_V << SPI_CLK_EN_S)
+#define SPI_CLK_EN_V  0x00000001U
+#define SPI_CLK_EN_S  0
+/** SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to power on the SPI module clock.
+ */
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S)
+#define SPI_MST_CLK_ACTIVE_V  0x00000001U
+#define SPI_MST_CLK_ACTIVE_S  1
+/** SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+ *  0: XTAL CLK.
+ */
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S)
+#define SPI_MST_CLK_SEL_V  0x00000001U
+#define SPI_MST_CLK_SEL_S  2
+
+/** SPI_DATE_REG register
+ *  Version control
+ */
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
+/** SPI_DATE : R/W; bitpos: [27:0]; default: 35680770;
+ *  SPI register version.
+ */
+#define SPI_DATE    0x0FFFFFFFU
+#define SPI_DATE_M  (SPI_DATE_V << SPI_DATE_S)
+#define SPI_DATE_V  0x0FFFFFFFU
+#define SPI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/spi_struct.h b/components/soc/esp32p4/register/soc/spi_struct.h
new file mode 100644
index 00000000000..8d004e60e1d
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/spi_struct.h
@@ -0,0 +1,1026 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: User-defined control registers */
+/** Type of cmd register
+ *  Command control register
+ */
+typedef union {
+    struct {
+        /** conf_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+         */
+        uint32_t conf_bitlen:18;  //this field is only for GPSPI2
+        uint32_t reserved_18:5;
+        /** update : WT; bitpos: [23]; default: 0;
+         *  Set this bit to synchronize SPI registers from APB clock domain into SPI module
+         *  clock domain, which is only used in SPI master mode.
+         */
+        uint32_t update:1;
+        /** usr : R/W/SC; bitpos: [24]; default: 0;
+         *  User define command enable.  An operation will be triggered when the bit is set.
+         *  The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+         *  changed by CONF_buf.
+         */
+        uint32_t usr:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} spi_cmd_reg_t;
+
+/** Type of addr register
+ *  Address value register
+ */
+typedef union {
+    struct {
+        /** usr_addr_value : R/W; bitpos: [31:0]; default: 0;
+         *  Address to slave. Can be configured in CONF state.
+         */
+        uint32_t usr_addr_value:32;
+    };
+    uint32_t val;
+} spi_addr_reg_t;
+
+/** Type of user register
+ *  SPI USER control register
+ */
+typedef union {
+    struct {
+        /** doutdin : R/W; bitpos: [0]; default: 0;
+         *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t doutdin:1;
+        uint32_t reserved_1:2;
+        /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0;
+         *  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t qpi_mode:1;
+        /** opi_mode : R/W; bitpos: [4]; default: 0;
+         *  Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others.
+         *  Can be configured in CONF state.
+         */
+        uint32_t opi_mode:1;  //this field is only for GPSPI2
+        /** tsck_i_edge : R/W; bitpos: [5]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck =
+         *  spi_ck_i. 1:tsck = !spi_ck_i.
+         */
+        uint32_t tsck_i_edge:1;
+        /** cs_hold : R/W; bitpos: [6]; default: 1;
+         *  spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_hold:1;
+        /** cs_setup : R/W; bitpos: [7]; default: 1;
+         *  spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cs_setup:1;
+        /** rsck_i_edge : R/W; bitpos: [8]; default: 0;
+         *  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck =
+         *  !spi_ck_i. 1:rsck = spi_ck_i.
+         */
+        uint32_t rsck_i_edge:1;
+        /** ck_out_edge : R/W; bitpos: [9]; default: 0;
+         *  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can
+         *  be configured in CONF state.
+         */
+        uint32_t ck_out_edge:1;
+        uint32_t reserved_10:2;
+        /** fwrite_dual : R/W; bitpos: [12]; default: 0;
+         *  In the write operations read-data phase apply 2 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_dual:1;
+        /** fwrite_quad : R/W; bitpos: [13]; default: 0;
+         *  In the write operations read-data phase apply 4 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_quad:1;
+        /** fwrite_oct : R/W; bitpos: [14]; default: 0;
+         *  In the write operations read-data phase apply 8 signals. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fwrite_oct:1;  //this field is only for GPSPI2
+        /** usr_conf_nxt : R/W; bitpos: [15]; default: 0;
+         *  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+         *  will continue. 0: The seg-trans will end after the current SPI seg-trans or this is
+         *  not seg-trans mode. Can be configured in CONF state.
+         */
+        uint32_t usr_conf_nxt:1;  //this field is only for GPSPI2
+        uint32_t reserved_16:1;
+        /** sio : R/W; bitpos: [17]; default: 0;
+         *  Set the bit to enable 3-line half duplex communication mosi and miso signals share
+         *  the same pin. 1: enable 0: disable. Can be configured in CONF state.
+         */
+        uint32_t sio:1;
+        uint32_t reserved_18:6;
+        /** usr_miso_highpart : R/W; bitpos: [24]; default: 0;
+         *  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0:
+         *  disable. Can be configured in CONF state.
+         */
+        uint32_t usr_miso_highpart:1;
+        /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0;
+         *  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+         *  0: disable.  Can be configured in CONF state.
+         */
+        uint32_t usr_mosi_highpart:1;
+        /** usr_dummy_idle : R/W; bitpos: [26]; default: 0;
+         *  spi clock is disable in dummy phase when the bit is enable. Can be configured in
+         *  CONF state.
+         */
+        uint32_t usr_dummy_idle:1;
+        /** usr_mosi : R/W; bitpos: [27]; default: 0;
+         *  This bit enable the write-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_mosi:1;
+        /** usr_miso : R/W; bitpos: [28]; default: 0;
+         *  This bit enable the read-data phase of an operation. Can be configured in CONF
+         *  state.
+         */
+        uint32_t usr_miso:1;
+        /** usr_dummy : R/W; bitpos: [29]; default: 0;
+         *  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_dummy:1;
+        /** usr_addr : R/W; bitpos: [30]; default: 0;
+         *  This bit enable the address phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_addr:1;
+        /** usr_command : R/W; bitpos: [31]; default: 1;
+         *  This bit enable the command phase of an operation. Can be configured in CONF state.
+         */
+        uint32_t usr_command:1;
+    };
+    uint32_t val;
+} spi_user_reg_t;
+
+/** Type of user1 register
+ *  SPI USER control register 1
+ */
+typedef union {
+    struct {
+        /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7;
+         *  The length in spi_clk cycles of dummy phase. The register value shall be
+         *  (cycle_num-1). Can be configured in CONF state.
+         */
+        uint32_t usr_dummy_cyclelen:8;
+        uint32_t reserved_8:8;
+        /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1;
+         *  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+         *  FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in
+         *  GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_wfull_err_end_en:1;
+        /** cs_setup_time : R/W; bitpos: [21:17]; default: 0;
+         *  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup
+         *  bit. Can be configured in CONF state.
+         */
+        uint32_t cs_setup_time:5;
+        /** cs_hold_time : R/W; bitpos: [26:22]; default: 1;
+         *  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+         *  Can be configured in CONF state.
+         */
+        uint32_t cs_hold_time:5;
+        /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23;
+         *  The length in bits of address phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_addr_bitlen:5;
+    };
+    uint32_t val;
+} spi_user1_reg_t;
+
+/** Type of user2 register
+ *  SPI USER control register 2
+ */
+typedef union {
+    struct {
+        /** usr_command_value : R/W; bitpos: [15:0]; default: 0;
+         *  The value of  command. Can be configured in CONF state.
+         */
+        uint32_t usr_command_value:16;
+        uint32_t reserved_16:11;
+        /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1;
+         *  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+         *  master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+         *  is valid in GP-SPI master FD/HD-mode.
+         */
+        uint32_t mst_rempty_err_end_en:1;
+        /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7;
+         *  The length in bits of command phase. The register value shall be (bit_num-1). Can
+         *  be configured in CONF state.
+         */
+        uint32_t usr_command_bitlen:4;
+    };
+    uint32_t val;
+} spi_user2_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of ctrl register
+ *  SPI control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** dummy_out : R/W; bitpos: [3]; default: 0;
+         *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
+         *  the FSPI bus signals are output. Can be configured in CONF state.
+         */
+        uint32_t dummy_out:1;
+        uint32_t reserved_4:1;
+        /** faddr_dual : R/W; bitpos: [5]; default: 0;
+         *  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_dual:1;
+        /** faddr_quad : R/W; bitpos: [6]; default: 0;
+         *  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_quad:1;
+        /** faddr_oct : R/W; bitpos: [7]; default: 0;
+         *  Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t faddr_oct:1;  //this field is only for GPSPI2
+        /** fcmd_dual : R/W; bitpos: [8]; default: 0;
+         *  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_dual:1;
+        /** fcmd_quad : R/W; bitpos: [9]; default: 0;
+         *  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_quad:1;
+        /** fcmd_oct : R/W; bitpos: [10]; default: 0;
+         *  Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF
+         *  state.
+         */
+        uint32_t fcmd_oct:1;  //this field is only for GPSPI2
+        uint32_t reserved_11:3;
+        /** fread_dual : R/W; bitpos: [14]; default: 0;
+         *  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_dual:1;
+        /** fread_quad : R/W; bitpos: [15]; default: 0;
+         *  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_quad:1;
+        /** fread_oct : R/W; bitpos: [16]; default: 0;
+         *  In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t fread_oct:1;  //this field is only for GPSPI2
+        uint32_t reserved_17:1;
+        /** q_pol : R/W; bitpos: [18]; default: 1;
+         *  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t q_pol:1;
+        /** d_pol : R/W; bitpos: [19]; default: 1;
+         *  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+         *  CONF state.
+         */
+        uint32_t d_pol:1;
+        /** hold_pol : R/W; bitpos: [20]; default: 1;
+         *  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+         *  configured in CONF state.
+         */
+        uint32_t hold_pol:1;
+        /** wp_pol : R/W; bitpos: [21]; default: 1;
+         *  Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can
+         *  be configured in CONF state.
+         */
+        uint32_t wp_pol:1;
+        uint32_t reserved_22:1;
+        /** rd_bit_order : R/W; bitpos: [24:23]; default: 0;
+         *  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+         *  state.
+         */
+        uint32_t rd_bit_order:2;
+        /** wr_bit_order : R/W; bitpos: [26:25]; default: 0;
+         *  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+         *  configured in CONF state.
+         */
+        uint32_t wr_bit_order:2;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} spi_ctrl_reg_t;
+
+/** Type of ms_dlen register
+ *  SPI data bit length control register
+ */
+typedef union {
+    struct {
+        /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0;
+         *  The value of these bits is the configured SPI transmission data bit length in
+         *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
+         *  the configured bit length in slave mode DMA RX controlled transfer. The register
+         *  value shall be (bit_num-1). Can be configured in CONF state.
+         */
+        uint32_t ms_data_bitlen:18;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} spi_ms_dlen_reg_t;
+
+/** Type of misc register
+ *  SPI misc register
+ */
+typedef union {
+    struct {
+        /** cs0_dis : R/W; bitpos: [0]; default: 0;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs0_dis:1;
+        /** cs1_dis : R/W; bitpos: [1]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs1_dis:1;
+        /** cs2_dis : R/W; bitpos: [2]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs2_dis:1;
+        /** cs3_dis : R/W; bitpos: [3]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs3_dis:1;  //this field is only for GPSPI2
+        /** cs4_dis : R/W; bitpos: [4]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs4_dis:1;  //this field is only for GPSPI2
+        /** cs5_dis : R/W; bitpos: [5]; default: 1;
+         *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
+         *  be configured in CONF state.
+         */
+        uint32_t cs5_dis:1;  //this field is only for GPSPI2
+        /** ck_dis : R/W; bitpos: [6]; default: 0;
+         *  1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+         */
+        uint32_t ck_dis:1;
+        /** master_cs_pol : R/W; bitpos: [12:7]; default: 0;
+         *  In the master mode the bits are the polarity of spi cs line, the value is
+         *  equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+         */
+        uint32_t master_cs_pol:6;  //This field for GPSPI3 is only 3-bit-width
+        uint32_t reserved_13:3;
+        /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0;
+         *  1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR
+         *  mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19.
+         */
+        uint32_t clk_data_dtr_en:1;  //this field is only for GPSPI2
+        /** data_dtr_en : R/W; bitpos: [17]; default: 0;
+         *  1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode.
+         *  Can be configured in CONF state.
+         */
+        uint32_t data_dtr_en:1;  //this field is only for GPSPI2
+        /** addr_dtr_en : R/W; bitpos: [18]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master
+         *  1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t addr_dtr_en:1;  //this field is only for GPSPI2
+        /** cmd_dtr_en : R/W; bitpos: [19]; default: 0;
+         *  1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master
+         *  1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be
+         *  configured in CONF state.
+         */
+        uint32_t cmd_dtr_en:1;  //this field is only for GPSPI2
+        uint32_t reserved_20:3;
+        /** slave_cs_pol : R/W; bitpos: [23]; default: 0;
+         *  spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+         *  CONF state.
+         */
+        uint32_t slave_cs_pol:1;
+        /** dqs_idle_edge : R/W; bitpos: [24]; default: 0;
+         *  The default value of spi_dqs. Can be configured in CONF state.
+         */
+        uint32_t dqs_idle_edge:1;  //this field is only for GPSPI2
+        uint32_t reserved_25:4;
+        /** ck_idle_edge : R/W; bitpos: [29]; default: 0;
+         *  1: spi clk line is high when idle     0: spi clk line is low when idle. Can be
+         *  configured in CONF state.
+         */
+        uint32_t ck_idle_edge:1;
+        /** cs_keep_active : R/W; bitpos: [30]; default: 0;
+         *  spi cs line keep low when the bit is set. Can be configured in CONF state.
+         */
+        uint32_t cs_keep_active:1;
+        /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0;
+         *  1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:
+         *  spi quad input swap disable. Can be configured in CONF state.
+         */
+        uint32_t quad_din_pin_swap:1;
+    };
+    uint32_t val;
+} spi_misc_reg_t;
+
+/** Type of dma_conf register
+ *  SPI DMA control register
+ */
+typedef union {
+    struct {
+        /** dma_outfifo_empty : RO; bitpos: [0]; default: 1;
+         *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
+         *  DMA TX FIFO is ready for sending data.
+         */
+        uint32_t dma_outfifo_empty:1;
+        /** dma_infifo_full : RO; bitpos: [1]; default: 1;
+         *  Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data.
+         *  0: DMA RX FIFO is ready for receiving data.
+         */
+        uint32_t dma_infifo_full:1;
+        uint32_t reserved_2:16;
+        /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0;
+         *  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+         */
+        uint32_t dma_slv_seg_trans_en:1;
+        /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0;
+         *  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+         *  spi_dma_infifo_full_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_rx_seg_trans_clr_en:1;
+        /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0;
+         *  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+         *  spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+         */
+        uint32_t slv_tx_seg_trans_clr_en:1;
+        /** rx_eof_en : R/W; bitpos: [21]; default: 0;
+         *  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to
+         *  the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0:
+         *  spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+         *  spi_dma_seg_trans_done in seg-trans.
+         */
+        uint32_t rx_eof_en:1;
+        uint32_t reserved_22:5;
+        /** dma_rx_ena : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to enable SPI DMA controlled receive data mode.
+         */
+        uint32_t dma_rx_ena:1;
+        /** dma_tx_ena : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable SPI DMA controlled send data mode.
+         */
+        uint32_t dma_tx_ena:1;
+        /** rx_afifo_rst : WT; bitpos: [29]; default: 0;
+         *  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+         *  slave mode transfer.
+         */
+        uint32_t rx_afifo_rst:1;
+        /** buf_afifo_rst : WT; bitpos: [30]; default: 0;
+         *  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+         *  controlled mode transfer and master mode transfer.
+         */
+        uint32_t buf_afifo_rst:1;
+        /** dma_afifo_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA
+         *  controlled mode transfer.
+         */
+        uint32_t dma_afifo_rst:1;
+    };
+    uint32_t val;
+} spi_dma_conf_reg_t;
+
+/** Type of slave register
+ *  SPI slave control register
+ */
+typedef union {
+    struct {
+        /** clk_mode : R/W; bitpos: [1:0]; default: 0;
+         *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
+         *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
+         *  SPI clock is always on. Can be configured in CONF state.
+         */
+        uint32_t clk_mode:2;
+        /** clk_mode_13 : R/W; bitpos: [2]; default: 0;
+         *  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0:
+         *  support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+         */
+        uint32_t clk_mode_13:1;
+        /** rsck_data_out : R/W; bitpos: [3]; default: 0;
+         *  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge
+         *  0: output data at tsck posedge
+         */
+        uint32_t rsck_data_out:1;
+        uint32_t reserved_4:4;
+        /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  DMA controlled mode(Rd_DMA). 0: others
+         */
+        uint32_t slv_rddma_bitlen_en:1;
+        /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in DMA controlled mode(Wr_DMA). 0: others
+         */
+        uint32_t slv_wrdma_bitlen_en:1;
+        /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in
+         *  CPU controlled mode(Rd_BUF). 0: others
+         */
+        uint32_t slv_rdbuf_bitlen_en:1;
+        /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0;
+         *  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length
+         *  in CPU controlled mode(Wr_BUF). 0: others
+         */
+        uint32_t slv_wrbuf_bitlen_en:1;
+        /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0;
+         *  Represents the effective bit of the last received data byte in SPI slave FD and HD
+         *  mode.
+         */
+        uint32_t slv_last_byte_strb:8;
+        uint32_t reserved_20:2;
+        /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10;
+         *  The magic value of BM table in master DMA seg-trans.
+         */
+        uint32_t dma_seg_magic_value:4;  //this field is only for GPSPI2
+        /** slave_mode : R/W; bitpos: [26]; default: 0;
+         *  Set SPI work mode. 1: slave mode 0: master mode.
+         */
+        uint32_t slave_mode:1;
+        /** soft_reset : WT; bitpos: [27]; default: 0;
+         *  Software reset enable, reset the spi clock line cs line and data lines. Can be
+         *  configured in CONF state.
+         */
+        uint32_t soft_reset:1;
+        /** usr_conf : R/W; bitpos: [28]; default: 0;
+         *  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans
+         *  will start. 0: This is not seg-trans mode.
+         */
+        uint32_t usr_conf:1;  //this field is only for GPSPI2
+        /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0;
+         *  In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before
+         *  starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI
+         *  transfer.
+         */
+        uint32_t mst_fd_wait_dma_tx_data:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} spi_slave_reg_t;
+
+/** Type of slave1 register
+ *  SPI slave control register 1
+ */
+typedef union {
+    struct {
+        /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0;
+         *  The transferred data bit length in SPI slave FD and HD mode.
+         */
+        uint32_t slv_data_bitlen:18;
+        /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0;
+         *  In the slave mode it is the value of command.
+         */
+        uint32_t slv_last_command:8;
+        /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0;
+         *  In the slave mode it is the value of address.
+         */
+        uint32_t slv_last_addr:6;
+    };
+    uint32_t val;
+} spi_slave1_reg_t;
+
+
+/** Group: Clock control registers */
+/** Type of clock register
+ *  SPI clock control register
+ */
+typedef union {
+    struct {
+        /** clkcnt_l : R/W; bitpos: [5:0]; default: 3;
+         *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
+         *  0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_l:6;
+        /** clkcnt_h : R/W; bitpos: [11:6]; default: 1;
+         *  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+         *  must be 0. Can be configured in CONF state.
+         */
+        uint32_t clkcnt_h:6;
+        /** clkcnt_n : R/W; bitpos: [17:12]; default: 3;
+         *  In the master mode it is the divider of spi_clk. So spi_clk frequency is
+         *  system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+         */
+        uint32_t clkcnt_n:6;
+        /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0;
+         *  In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+         */
+        uint32_t clkdiv_pre:4;
+        uint32_t reserved_22:9;
+        /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
+         *  In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system
+         *  clock. Can be configured in CONF state.
+         */
+        uint32_t clk_equ_sysclk:1;
+    };
+    uint32_t val;
+} spi_clock_reg_t;
+
+/** Type of clk_gate register
+ *  SPI module clock and register clock control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable clk gate
+         */
+        uint32_t clk_en:1;
+        /** mst_clk_active : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to power on the SPI module clock.
+         */
+        uint32_t mst_clk_active:1;
+        /** mst_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M.
+         *  0: XTAL CLK.
+         */
+        uint32_t mst_clk_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} spi_clk_gate_reg_t;
+
+
+/** Group: Timing registers */
+/** Type of din_mode register
+ *  SPI input delay mode configuration
+ */
+typedef union {
+    struct {
+        /** din0_mode : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din0_mode:2;
+        /** din1_mode : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din1_mode:2;
+        /** din2_mode : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din2_mode:2;
+        /** din3_mode : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din3_mode:2;
+        /** din4_mode : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din4_mode:2;  //this field is only for GPSPI2
+        /** din5_mode : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din5_mode:2;  //this field is only for GPSPI2
+        /** din6_mode : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din6_mode:2;  //this field is only for GPSPI2
+        /** din7_mode : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
+         *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
+         *  with the spi_clk. Can be configured in CONF state.
+         */
+        uint32_t din7_mode:2;  //this field is only for GPSPI2
+        /** timing_hclk_active : R/W; bitpos: [16]; default: 0;
+         *  1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF
+         *  state.
+         */
+        uint32_t timing_hclk_active:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} spi_din_mode_reg_t;
+
+/** Type of din_num register
+ *  SPI input delay number configuration
+ */
+typedef union {
+    struct {
+        /** din0_num : R/W; bitpos: [1:0]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din0_num:2;
+        /** din1_num : R/W; bitpos: [3:2]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din1_num:2;
+        /** din2_num : R/W; bitpos: [5:4]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din2_num:2;
+        /** din3_num : R/W; bitpos: [7:6]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din3_num:2;
+        /** din4_num : R/W; bitpos: [9:8]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din4_num:2;  //this field is only for GPSPI2
+        /** din5_num : R/W; bitpos: [11:10]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din5_num:2;  //this field is only for GPSPI2
+        /** din6_num : R/W; bitpos: [13:12]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din6_num:2;  //this field is only for GPSPI2
+        /** din7_num : R/W; bitpos: [15:14]; default: 0;
+         *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
+         *  delayed by 2 cycles,...  Can be configured in CONF state.
+         */
+        uint32_t din7_num:2;  //this field is only for GPSPI2
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} spi_din_num_reg_t;
+
+/** Type of dout_mode register
+ *  SPI output delay mode configuration
+ */
+typedef union {
+    struct {
+        /** dout0_mode : R/W; bitpos: [0]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout0_mode:1;
+        /** dout1_mode : R/W; bitpos: [1]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout1_mode:1;
+        /** dout2_mode : R/W; bitpos: [2]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout2_mode:1;
+        /** dout3_mode : R/W; bitpos: [3]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout3_mode:1;
+        /** dout4_mode : R/W; bitpos: [4]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout4_mode:1;  //this field is only for GPSPI2
+        /** dout5_mode : R/W; bitpos: [5]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout5_mode:1;  //this field is only for GPSPI2
+        /** dout6_mode : R/W; bitpos: [6]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout6_mode:1;  //this field is only for GPSPI2
+        /** dout7_mode : R/W; bitpos: [7]; default: 0;
+         *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
+         *  1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t dout7_mode:1;  //this field is only for GPSPI2
+        /** d_dqs_mode : R/W; bitpos: [8]; default: 0;
+         *  The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+         *  delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be
+         *  configured in CONF state.
+         */
+        uint32_t d_dqs_mode:1;  //this field is only for GPSPI2
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} spi_dout_mode_reg_t;
+
+/** Type of dma_int register
+ *  SPI interrupt raw/ena/clr/sta/set register
+ */
+typedef union {
+    struct {
+        /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
+         *  receive data.  0: Others.
+         */
+        uint32_t dma_infifo_full_err_int:1;
+        /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+         *  master mode and send out all 0 in slave mode.  0: Others.
+         */
+        uint32_t dma_outfifo_empty_err_int:1;
+        /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_ex_qpi_int:1;
+        /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission
+         *  is ended. 0: Others.
+         */
+        uint32_t slv_en_qpi_int:1;
+        /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd7_int:1;
+        /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd8_int:1;
+        /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmd9_int:1;
+        /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+         *  ended. 0: Others.
+         */
+        uint32_t slv_cmda_int:1;
+        /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_dma_done_int:1;
+        /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_dma_done_int:1;
+        /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_rd_buf_done_int:1;
+        /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+         *  transmission is ended. 0: Others.
+         */
+        uint32_t slv_wr_buf_done_int:1;
+        /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+         *  ended. 0: others.
+         */
+        uint32_t trans_done_int:1;
+        /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA
+         *  full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+         *  And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans
+         *  is not ended or not occurred.
+         */
+        uint32_t dma_seg_trans_done_int:1;
+        /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer
+         *  is error in the DMA seg-conf-trans. 0: others.
+         */
+        uint32_t seg_magic_err_int_raw:1;  //this field is only forPI2
+        /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+         *  of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is
+         *  bigger than 63. 0: Others.
+         */
+        uint32_t slv_buf_addr_err_int:1;
+        /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+         *  current SPI slave HD mode transmission is not supported. 0: Others.
+         */
+        uint32_t slv_cmd_err_int:1;
+        /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+         *  write-full error when SPI inputs data in master mode. 0: Others.
+         */
+        uint32_t mst_rx_afifo_wfull_err_int:1;
+        /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+         *  AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+         */
+        uint32_t mst_tx_afifo_rempty_err_int:1;
+        /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app2_int:1;
+        /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.
+         */
+        uint32_t app1_int:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} spi_dma_int_reg_t;
+
+/** Type of wn register
+ *  SPI CPU-controlled buffer
+ */
+typedef union {
+    struct {
+        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
+         *  data buffer
+         */
+        uint32_t buf:32;
+    };
+    uint32_t val;
+} spi_wn_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 35680770;
+         *  SPI register version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} spi_date_reg_t;
+
+
+typedef struct {
+    volatile spi_cmd_reg_t cmd;
+    volatile spi_addr_reg_t addr;
+    volatile spi_ctrl_reg_t ctrl;
+    volatile spi_clock_reg_t clock;
+    volatile spi_user_reg_t user;
+    volatile spi_user1_reg_t user1;
+    volatile spi_user2_reg_t user2;
+    volatile spi_ms_dlen_reg_t ms_dlen;
+    volatile spi_misc_reg_t misc;
+    volatile spi_din_mode_reg_t din_mode;
+    volatile spi_din_num_reg_t din_num;
+    volatile spi_dout_mode_reg_t dout_mode;
+    volatile spi_dma_conf_reg_t dma_conf;
+    volatile spi_dma_int_reg_t dma_int_ena;
+    volatile spi_dma_int_reg_t dma_int_clr;
+    volatile spi_dma_int_reg_t dma_int_raw;
+    volatile spi_dma_int_reg_t dma_int_sta;
+    volatile spi_dma_int_reg_t dma_int_set;
+    uint32_t reserved_048[20];
+    volatile spi_wn_reg_t data_buf[16];
+    uint32_t reserved_0d8[2];
+    volatile spi_slave_reg_t slave;
+    volatile spi_slave1_reg_t slave1;
+    volatile spi_clk_gate_reg_t clk_gate;
+    uint32_t reserved_0ec;
+    volatile spi_date_reg_t date;
+} spi_dev_t;
+
+extern spi_dev_t GPSPI2;
+extern spi_dev_t GPSPI3;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/systimer_reg.h b/components/soc/esp32p4/register/soc/systimer_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/systimer_reg.h
rename to components/soc/esp32p4/register/soc/systimer_reg.h
diff --git a/components/soc/esp32p4/include/soc/systimer_struct.h b/components/soc/esp32p4/register/soc/systimer_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/systimer_struct.h
rename to components/soc/esp32p4/register/soc/systimer_struct.h
diff --git a/components/soc/esp32p4/include/soc/tcm_monitor_reg.h b/components/soc/esp32p4/register/soc/tcm_monitor_reg.h
similarity index 98%
rename from components/soc/esp32p4/include/soc/tcm_monitor_reg.h
rename to components/soc/esp32p4/register/soc/tcm_monitor_reg.h
index d89fc3009cc..f04f761def9 100644
--- a/components/soc/esp32p4/include/soc/tcm_monitor_reg.h
+++ b/components/soc/esp32p4/register/soc/tcm_monitor_reg.h
@@ -12,7 +12,7 @@ extern "C" {
 #endif
 
 /** MEM_MONITOR_LOG_SETTING_REG register
- *  log config regsiter
+ *  log config register
  */
 #define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
 /** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
@@ -53,7 +53,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_DMA_1_ENA_S  24
 
 /** MEM_MONITOR_LOG_SETTING1_REG register
- *  log config regsiter
+ *  log config register
  */
 #define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
 /** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
@@ -72,7 +72,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_DMA_3_ENA_S  8
 
 /** MEM_MONITOR_LOG_CHECK_DATA_REG register
- *  check data regsiter
+ *  check data register
  */
 #define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
 /** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
@@ -97,7 +97,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_DATA_MASK_S  0
 
 /** MEM_MONITOR_LOG_MIN_REG register
- *  log boundary regsiter
+ *  log boundary register
  */
 #define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
 /** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
@@ -109,7 +109,7 @@ extern "C" {
 #define MEM_MONITOR_LOG_MIN_S  0
 
 /** MEM_MONITOR_LOG_MAX_REG register
- *  log boundary regsiter
+ *  log boundary register
  */
 #define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
 /** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
diff --git a/components/soc/esp32p4/include/soc/tcm_monitor_struct.h b/components/soc/esp32p4/register/soc/tcm_monitor_struct.h
similarity index 98%
rename from components/soc/esp32p4/include/soc/tcm_monitor_struct.h
rename to components/soc/esp32p4/register/soc/tcm_monitor_struct.h
index c88691215af..e3e1abf3761 100644
--- a/components/soc/esp32p4/include/soc/tcm_monitor_struct.h
+++ b/components/soc/esp32p4/register/soc/tcm_monitor_struct.h
@@ -12,7 +12,7 @@ extern "C" {
 
 /** Group: configuration registers */
 /** Type of log_setting register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -43,7 +43,7 @@ typedef union {
 } mem_monitor_log_setting_reg_t;
 
 /** Type of log_setting1 register
- *  log config regsiter
+ *  log config register
  */
 typedef union {
     struct {
@@ -61,7 +61,7 @@ typedef union {
 } mem_monitor_log_setting1_reg_t;
 
 /** Type of log_check_data register
- *  check data regsiter
+ *  check data register
  */
 typedef union {
     struct {
@@ -89,7 +89,7 @@ typedef union {
 } mem_monitor_log_data_mask_reg_t;
 
 /** Type of log_min register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
@@ -102,7 +102,7 @@ typedef union {
 } mem_monitor_log_min_reg_t;
 
 /** Type of log_max register
- *  log boundary regsiter
+ *  log boundary register
  */
 typedef union {
     struct {
diff --git a/components/soc/esp32p4/include/soc/timer_group_reg.h b/components/soc/esp32p4/register/soc/timer_group_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/timer_group_reg.h
rename to components/soc/esp32p4/register/soc/timer_group_reg.h
diff --git a/components/soc/esp32p4/include/soc/timer_group_struct.h b/components/soc/esp32p4/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/timer_group_struct.h
rename to components/soc/esp32p4/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32p4/include/soc/touch_reg.h b/components/soc/esp32p4/register/soc/touch_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/touch_reg.h
rename to components/soc/esp32p4/register/soc/touch_reg.h
diff --git a/components/soc/esp32p4/include/soc/touch_struct.h b/components/soc/esp32p4/register/soc/touch_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/touch_struct.h
rename to components/soc/esp32p4/register/soc/touch_struct.h
diff --git a/components/soc/esp32p4/include/soc/trace_reg.h b/components/soc/esp32p4/register/soc/trace_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/trace_reg.h
rename to components/soc/esp32p4/register/soc/trace_reg.h
diff --git a/components/soc/esp32p4/include/soc/trace_struct.h b/components/soc/esp32p4/register/soc/trace_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/trace_struct.h
rename to components/soc/esp32p4/register/soc/trace_struct.h
diff --git a/components/soc/esp32p4/include/soc/tsens_reg.h b/components/soc/esp32p4/register/soc/tsens_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/tsens_reg.h
rename to components/soc/esp32p4/register/soc/tsens_reg.h
diff --git a/components/soc/esp32p4/include/soc/tsens_struct.h b/components/soc/esp32p4/register/soc/tsens_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/tsens_struct.h
rename to components/soc/esp32p4/register/soc/tsens_struct.h
diff --git a/components/soc/esp32p4/include/soc/twai_reg.h b/components/soc/esp32p4/register/soc/twai_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/twai_reg.h
rename to components/soc/esp32p4/register/soc/twai_reg.h
diff --git a/components/soc/esp32p4/include/soc/twai_struct.h b/components/soc/esp32p4/register/soc/twai_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/twai_struct.h
rename to components/soc/esp32p4/register/soc/twai_struct.h
diff --git a/components/soc/esp32p4/register/soc/uart_reg.h b/components/soc/esp32p4/register/soc/uart_reg.h
new file mode 100644
index 00000000000..014f8eaed29
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/uart_reg.h
@@ -0,0 +1,1579 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART $n accesses FIFO via this register.
+ */
+#define UART_RXFIFO_RD_BYTE    0x000000FFU
+#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define UART_RXFIFO_RD_BYTE_S  0
+
+/** UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
+#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
+#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_PARITY_ERR_INT_RAW_S  2
+/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
+#define UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_FRM_ERR_INT_RAW_S  3
+/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
+#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
+#define UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define UART_DSR_CHG_INT_RAW_S  5
+/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
+#define UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define UART_CTS_CHG_INT_RAW_S  6
+/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
+#define UART_BRK_DET_INT_RAW_V  0x00000001U
+#define UART_BRK_DET_INT_RAW_S  7
+/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
+#define UART_SW_XON_INT_RAW_V  0x00000001U
+#define UART_SW_XON_INT_RAW_S  9
+/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
+#define UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define UART_SW_XOFF_INT_RAW_S  10
+/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
+#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define UART_GLITCH_DET_INT_RAW_S  11
+/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters after all data in Tx-FIFO are sent.
+ */
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
+#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
+#define UART_TX_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_DONE_INT_RAW_S  14
+/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  This interrupt raw bit turns to high level when detects a clash between transmitter
+ *  and receiver in rs485 mode.
+ */
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
+#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
+#define UART_RS485_CLASH_INT_RAW_S  17
+/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
+#define UART_WAKEUP_INT_RAW_V  0x00000001U
+#define UART_WAKEUP_INT_RAW_S  19
+
+/** UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
+/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
+#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ST_S  0
+/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
+#define UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_PARITY_ERR_INT_ST_S  2
+/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
+#define UART_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_FRM_ERR_INT_ST_S  3
+/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
+#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
+#define UART_DSR_CHG_INT_ST_V  0x00000001U
+#define UART_DSR_CHG_INT_ST_S  5
+/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
+#define UART_CTS_CHG_INT_ST_V  0x00000001U
+#define UART_CTS_CHG_INT_ST_S  6
+/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
+#define UART_BRK_DET_INT_ST_V  0x00000001U
+#define UART_BRK_DET_INT_ST_S  7
+/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
+#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
+#define UART_SW_XON_INT_ST_V  0x00000001U
+#define UART_SW_XON_INT_ST_S  9
+/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
+#define UART_SW_XOFF_INT_ST_V  0x00000001U
+#define UART_SW_XOFF_INT_ST_S  10
+/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
+#define UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define UART_GLITCH_DET_INT_ST_S  11
+/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
+#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
+#define UART_TX_DONE_INT_ST_V  0x00000001U
+#define UART_TX_DONE_INT_ST_S  14
+/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ *  set to 1.
+ */
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+ *  to 1.
+ */
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
+#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
+ *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+ */
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
+#define UART_RS485_CLASH_INT_ST_V  0x00000001U
+#define UART_RS485_CLASH_INT_ST_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
+#define UART_WAKEUP_INT_ST_V  0x00000001U
+#define UART_WAKEUP_INT_ST_S  19
+
+/** UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
+/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
+#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
+#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_PARITY_ERR_INT_ENA_S  2
+/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
+#define UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_FRM_ERR_INT_ENA_S  3
+/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
+#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
+#define UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define UART_DSR_CHG_INT_ENA_S  5
+/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
+#define UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define UART_CTS_CHG_INT_ENA_S  6
+/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
+#define UART_BRK_DET_INT_ENA_V  0x00000001U
+#define UART_BRK_DET_INT_ENA_S  7
+/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
+#define UART_SW_XON_INT_ENA_V  0x00000001U
+#define UART_SW_XON_INT_ENA_S  9
+/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
+#define UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define UART_SW_XOFF_INT_ENA_S  10
+/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
+#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define UART_GLITCH_DET_INT_ENA_S  11
+/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
+#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
+#define UART_TX_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_DONE_INT_ENA_S  14
+/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  This is the enable bit for rs485_clash_int_st register.
+ */
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
+#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
+#define UART_RS485_CLASH_INT_ENA_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
+#define UART_WAKEUP_INT_ENA_V  0x00000001U
+#define UART_WAKEUP_INT_ENA_S  19
+
+/** UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
+/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
+#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
+#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_PARITY_ERR_INT_CLR_S  2
+/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
+#define UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_FRM_ERR_INT_CLR_S  3
+/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
+#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
+#define UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define UART_DSR_CHG_INT_CLR_S  5
+/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
+#define UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define UART_CTS_CHG_INT_CLR_S  6
+/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
+#define UART_BRK_DET_INT_CLR_V  0x00000001U
+#define UART_BRK_DET_INT_CLR_S  7
+/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
+#define UART_SW_XON_INT_CLR_V  0x00000001U
+#define UART_SW_XON_INT_CLR_S  9
+/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
+#define UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define UART_SW_XOFF_INT_CLR_S  10
+/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
+#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define UART_GLITCH_DET_INT_CLR_S  11
+/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
+#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
+#define UART_TX_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_DONE_INT_CLR_S  14
+/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+ */
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+ */
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the rs485_clash_int_raw interrupt.
+ */
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
+#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
+#define UART_RS485_CLASH_INT_CLR_S  17
+/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
+#define UART_WAKEUP_INT_CLR_V  0x00000001U
+#define UART_WAKEUP_INT_CLR_S  19
+
+/** UART_CLKDIV_SYNC_REG register
+ *  Clock divider configuration
+ */
+#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14)
+/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_CLKDIV    0x00000FFFU
+#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
+#define UART_CLKDIV_V  0x00000FFFU
+#define UART_CLKDIV_S  0
+/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define UART_CLKDIV_FRAG    0x0000000FU
+#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
+#define UART_CLKDIV_FRAG_V  0x0000000FU
+#define UART_CLKDIV_FRAG_S  20
+
+/** UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
+/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value the pulse is ignored.
+ */
+#define UART_GLITCH_FILT    0x000000FFU
+#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
+#define UART_GLITCH_FILT_V  0x000000FFU
+#define UART_GLITCH_FILT_S  0
+/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
+#define UART_GLITCH_FILT_EN_V  0x00000001U
+#define UART_GLITCH_FILT_EN_S  8
+
+/** UART_STATUS_REG register
+ *  UART status register
+ */
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
+/** UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define UART_RXFIFO_CNT    0x000000FFU
+#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
+#define UART_RXFIFO_CNT_V  0x000000FFU
+#define UART_RXFIFO_CNT_S  0
+/** UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
+#define UART_DSRN_V  0x00000001U
+#define UART_DSRN_S  13
+/** UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
+#define UART_CTSN_V  0x00000001U
+#define UART_CTSN_S  14
+/** UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
+#define UART_RXD_V  0x00000001U
+#define UART_RXD_S  15
+/** UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define UART_TXFIFO_CNT    0x000000FFU
+#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
+#define UART_TXFIFO_CNT_V  0x000000FFU
+#define UART_TXFIFO_CNT_S  16
+/** UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
+#define UART_DTRN_V  0x00000001U
+#define UART_DTRN_S  29
+/** UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
+#define UART_RTSN_V  0x00000001U
+#define UART_RTSN_S  30
+/** UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
+#define UART_TXD_V  0x00000001U
+#define UART_TXD_S  31
+
+/** UART_CONF0_SYNC_REG register
+ *  a
+ */
+#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20)
+/** UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
+#define UART_PARITY_V  0x00000001U
+#define UART_PARITY_S  0
+/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
+#define UART_PARITY_EN_V  0x00000001U
+#define UART_PARITY_EN_S  1
+/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define UART_BIT_NUM    0x00000003U
+#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
+#define UART_BIT_NUM_V  0x00000003U
+#define UART_BIT_NUM_S  2
+/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define UART_STOP_BIT_NUM    0x00000003U
+#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
+#define UART_STOP_BIT_NUM_V  0x00000003U
+#define UART_STOP_BIT_NUM_S  4
+/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define UART_TXD_BRK    (BIT(6))
+#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
+#define UART_TXD_BRK_V  0x00000001U
+#define UART_TXD_BRK_S  6
+/** UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to enable IrDA loopback mode.
+ */
+#define UART_IRDA_DPLX    (BIT(7))
+#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
+#define UART_IRDA_DPLX_V  0x00000001U
+#define UART_IRDA_DPLX_S  7
+/** UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the start enable bit for IrDA transmitter.
+ */
+#define UART_IRDA_TX_EN    (BIT(8))
+#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
+#define UART_IRDA_TX_EN_V  0x00000001U
+#define UART_IRDA_TX_EN_S  8
+/** UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0;
+ *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+ *  transmitter's 11th bit to 0.
+ */
+#define UART_IRDA_WCTL    (BIT(9))
+#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
+#define UART_IRDA_WCTL_V  0x00000001U
+#define UART_IRDA_WCTL_S  9
+/** UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to invert the level of  IrDA transmitter.
+ */
+#define UART_IRDA_TX_INV    (BIT(10))
+#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
+#define UART_IRDA_TX_INV_V  0x00000001U
+#define UART_IRDA_TX_INV_S  10
+/** UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to invert the level of IrDA receiver.
+ */
+#define UART_IRDA_RX_INV    (BIT(11))
+#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
+#define UART_IRDA_RX_INV_V  0x00000001U
+#define UART_IRDA_RX_INV_S  11
+/** UART_LOOPBACK : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define UART_LOOPBACK    (BIT(12))
+#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
+#define UART_LOOPBACK_V  0x00000001U
+#define UART_LOOPBACK_S  12
+/** UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define UART_TX_FLOW_EN    (BIT(13))
+#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
+#define UART_TX_FLOW_EN_V  0x00000001U
+#define UART_TX_FLOW_EN_S  13
+/** UART_IRDA_EN : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable IrDA protocol.
+ */
+#define UART_IRDA_EN    (BIT(14))
+#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
+#define UART_IRDA_EN_V  0x00000001U
+#define UART_IRDA_EN_S  14
+/** UART_RXD_INV : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define UART_RXD_INV    (BIT(15))
+#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
+#define UART_RXD_INV_V  0x00000001U
+#define UART_RXD_INV_S  15
+/** UART_TXD_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define UART_TXD_INV    (BIT(16))
+#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
+#define UART_TXD_INV_V  0x00000001U
+#define UART_TXD_INV_S  16
+/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define UART_DIS_RX_DAT_OVF    (BIT(17))
+#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
+#define UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define UART_DIS_RX_DAT_OVF_S  17
+/** UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define UART_ERR_WR_MASK    (BIT(18))
+#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
+#define UART_ERR_WR_MASK_V  0x00000001U
+#define UART_ERR_WR_MASK_S  18
+/** UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for detecting baudrate.
+ */
+#define UART_AUTOBAUD_EN    (BIT(19))
+#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
+#define UART_AUTOBAUD_EN_V  0x00000001U
+#define UART_AUTOBAUD_EN_S  19
+/** UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  UART memory clock gate enable signal.
+ */
+#define UART_MEM_CLK_EN    (BIT(20))
+#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
+#define UART_MEM_CLK_EN_V  0x00000001U
+#define UART_MEM_CLK_EN_S  20
+/** UART_SW_RTS : R/W; bitpos: [21]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_RTS    (BIT(21))
+#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
+#define UART_SW_RTS_V  0x00000001U
+#define UART_SW_RTS_S  21
+/** UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define UART_RXFIFO_RST    (BIT(22))
+#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
+#define UART_RXFIFO_RST_V  0x00000001U
+#define UART_RXFIFO_RST_S  22
+/** UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define UART_TXFIFO_RST    (BIT(23))
+#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
+#define UART_TXFIFO_RST_V  0x00000001U
+#define UART_TXFIFO_RST_S  23
+
+/** UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
+/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define UART_RXFIFO_FULL_THRHD    0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
+#define UART_RXFIFO_FULL_THRHD_V  0x000000FFU
+#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define UART_TXFIFO_EMPTY_THRHD    0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
+#define UART_TXFIFO_EMPTY_THRHD_V  0x000000FFU
+#define UART_TXFIFO_EMPTY_THRHD_S  8
+/** UART_CTS_INV : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define UART_CTS_INV    (BIT(16))
+#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
+#define UART_CTS_INV_V  0x00000001U
+#define UART_CTS_INV_S  16
+/** UART_DSR_INV : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define UART_DSR_INV    (BIT(17))
+#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
+#define UART_DSR_INV_V  0x00000001U
+#define UART_DSR_INV_S  17
+/** UART_RTS_INV : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define UART_RTS_INV    (BIT(18))
+#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
+#define UART_RTS_INV_V  0x00000001U
+#define UART_RTS_INV_S  18
+/** UART_DTR_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define UART_DTR_INV    (BIT(19))
+#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
+#define UART_DTR_INV_V  0x00000001U
+#define UART_DTR_INV_S  19
+/** UART_SW_DTR : R/W; bitpos: [20]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_DTR    (BIT(20))
+#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
+#define UART_SW_DTR_V  0x00000001U
+#define UART_SW_DTR_S  20
+/** UART_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define UART_CLK_EN    (BIT(21))
+#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
+#define UART_CLK_EN_V  0x00000001U
+#define UART_CLK_EN_S  21
+
+/** UART_HWFC_CONF_SYNC_REG register
+ *  Hardware flow-control configuration
+ */
+#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c)
+/** UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define UART_RX_FLOW_THRHD    0x000000FFU
+#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
+#define UART_RX_FLOW_THRHD_V  0x000000FFU
+#define UART_RX_FLOW_THRHD_S  0
+/** UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define UART_RX_FLOW_EN    (BIT(8))
+#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
+#define UART_RX_FLOW_EN_V  0x00000001U
+#define UART_RX_FLOW_EN_S  8
+
+/** UART_SLEEP_CONF0_REG register
+ *  UART sleep configure register 0
+ */
+#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30)
+/** UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified wake up char1 to wake up
+ */
+#define UART_WK_CHAR1    0x000000FFU
+#define UART_WK_CHAR1_M  (UART_WK_CHAR1_V << UART_WK_CHAR1_S)
+#define UART_WK_CHAR1_V  0x000000FFU
+#define UART_WK_CHAR1_S  0
+/** UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0;
+ *  This register restores the specified wake up char2 to wake up
+ */
+#define UART_WK_CHAR2    0x000000FFU
+#define UART_WK_CHAR2_M  (UART_WK_CHAR2_V << UART_WK_CHAR2_S)
+#define UART_WK_CHAR2_V  0x000000FFU
+#define UART_WK_CHAR2_S  8
+/** UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0;
+ *  This register restores the specified wake up char3 to wake up
+ */
+#define UART_WK_CHAR3    0x000000FFU
+#define UART_WK_CHAR3_M  (UART_WK_CHAR3_V << UART_WK_CHAR3_S)
+#define UART_WK_CHAR3_V  0x000000FFU
+#define UART_WK_CHAR3_S  16
+/** UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0;
+ *  This register restores the specified wake up char4 to wake up
+ */
+#define UART_WK_CHAR4    0x000000FFU
+#define UART_WK_CHAR4_M  (UART_WK_CHAR4_V << UART_WK_CHAR4_S)
+#define UART_WK_CHAR4_V  0x000000FFU
+#define UART_WK_CHAR4_S  24
+
+/** UART_SLEEP_CONF1_REG register
+ *  UART sleep configure register 1
+ */
+#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34)
+/** UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0;
+ *  This register restores the specified char0 to wake up
+ */
+#define UART_WK_CHAR0    0x000000FFU
+#define UART_WK_CHAR0_M  (UART_WK_CHAR0_V << UART_WK_CHAR0_S)
+#define UART_WK_CHAR0_V  0x000000FFU
+#define UART_WK_CHAR0_S  0
+
+/** UART_SLEEP_CONF2_REG register
+ *  UART sleep configure register 2
+ */
+#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38)
+/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define UART_ACTIVE_THRESHOLD    0x000003FFU
+#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
+#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define UART_ACTIVE_THRESHOLD_S  0
+/** UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1;
+ *  In wake up mode 1 this field is used to set the received data number threshold to
+ *  wake up chip.
+ */
+#define UART_RX_WAKE_UP_THRHD    0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_M  (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S)
+#define UART_RX_WAKE_UP_THRHD_V  0x000000FFU
+#define UART_RX_WAKE_UP_THRHD_S  10
+/** UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5;
+ *  This register is used to select number of wake up char.
+ */
+#define UART_WK_CHAR_NUM    0x00000007U
+#define UART_WK_CHAR_NUM_M  (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S)
+#define UART_WK_CHAR_NUM_V  0x00000007U
+#define UART_WK_CHAR_NUM_S  18
+/** UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0;
+ *  This register is used to mask  wake up char.
+ */
+#define UART_WK_CHAR_MASK    0x0000001FU
+#define UART_WK_CHAR_MASK_M  (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S)
+#define UART_WK_CHAR_MASK_V  0x0000001FU
+#define UART_WK_CHAR_MASK_S  21
+/** UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+ *  received data number larger than
+ */
+#define UART_WK_MODE_SEL    0x00000003U
+#define UART_WK_MODE_SEL_M  (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S)
+#define UART_WK_MODE_SEL_V  0x00000003U
+#define UART_WK_MODE_SEL_S  26
+
+/** UART_SWFC_CONF0_SYNC_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c)
+/** UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define UART_XON_CHAR    0x000000FFU
+#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
+#define UART_XON_CHAR_V  0x000000FFU
+#define UART_XON_CHAR_S  0
+/** UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define UART_XOFF_CHAR    0x000000FFU
+#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
+#define UART_XOFF_CHAR_V  0x000000FFU
+#define UART_XOFF_CHAR_S  8
+/** UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0;
+ *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+ *  this status, UART Tx can not transmit XOFF even the received data number is larger
+ *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+ *  UART Tx is disabled.
+ */
+#define UART_XON_XOFF_STILL_SEND    (BIT(16))
+#define UART_XON_XOFF_STILL_SEND_M  (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S)
+#define UART_XON_XOFF_STILL_SEND_V  0x00000001U
+#define UART_XON_XOFF_STILL_SEND_S  16
+/** UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define UART_SW_FLOW_CON_EN    (BIT(17))
+#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
+#define UART_SW_FLOW_CON_EN_V  0x00000001U
+#define UART_SW_FLOW_CON_EN_S  17
+/** UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define UART_XONOFF_DEL    (BIT(18))
+#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
+#define UART_XONOFF_DEL_V  0x00000001U
+#define UART_XONOFF_DEL_S  18
+/** UART_FORCE_XON : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define UART_FORCE_XON    (BIT(19))
+#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
+#define UART_FORCE_XON_V  0x00000001U
+#define UART_FORCE_XON_S  19
+/** UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define UART_FORCE_XOFF    (BIT(20))
+#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
+#define UART_FORCE_XOFF_V  0x00000001U
+#define UART_FORCE_XOFF_S  20
+/** UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XON    (BIT(21))
+#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
+#define UART_SEND_XON_V  0x00000001U
+#define UART_SEND_XON_S  21
+/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XOFF    (BIT(22))
+#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
+#define UART_SEND_XOFF_V  0x00000001U
+#define UART_SEND_XOFF_S  22
+
+/** UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
+/** UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+ */
+#define UART_XON_THRESHOLD    0x000000FFU
+#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
+#define UART_XON_THRESHOLD_V  0x000000FFU
+#define UART_XON_THRESHOLD_S  0
+/** UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+ */
+#define UART_XOFF_THRESHOLD    0x000000FFU
+#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
+#define UART_XOFF_THRESHOLD_V  0x000000FFU
+#define UART_XOFF_THRESHOLD_S  8
+
+/** UART_TXBRK_CONF_SYNC_REG register
+ *  Tx Break character configuration
+ */
+#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44)
+/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define UART_TX_BRK_NUM    0x000000FFU
+#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
+#define UART_TX_BRK_NUM_V  0x000000FFU
+#define UART_TX_BRK_NUM_S  0
+
+/** UART_IDLE_CONF_SYNC_REG register
+ *  Frame-end idle configuration
+ */
+#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48)
+/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define UART_RX_IDLE_THRHD    0x000003FFU
+#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
+#define UART_RX_IDLE_THRHD_V  0x000003FFU
+#define UART_RX_IDLE_THRHD_S  0
+/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define UART_TX_IDLE_NUM    0x000003FFU
+#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
+#define UART_TX_IDLE_NUM_V  0x000003FFU
+#define UART_TX_IDLE_NUM_S  10
+
+/** UART_RS485_CONF_SYNC_REG register
+ *  RS485 mode configuration
+ */
+#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c)
+/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to choose the rs485 mode.
+ */
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
+#define UART_RS485_EN_V  0x00000001U
+#define UART_RS485_EN_S  0
+/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
+#define UART_DL0_EN_V  0x00000001U
+#define UART_DL0_EN_S  1
+/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
+#define UART_DL1_EN_V  0x00000001U
+#define UART_DL1_EN_S  2
+/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable receiver could receive data when the transmitter is
+ *  transmitting data in rs485 mode.
+ */
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
+#define UART_RS485TX_RX_EN_V  0x00000001U
+#define UART_RS485TX_RX_EN_S  3
+/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+ */
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
+#define UART_RS485RXBY_TX_EN_V  0x00000001U
+#define UART_RS485RXBY_TX_EN_S  4
+/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
+ *  This register is used to delay the receiver's internal data signal.
+ */
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
+#define UART_RS485_RX_DLY_NUM_V  0x00000001U
+#define UART_RS485_RX_DLY_NUM_S  5
+/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
+ *  This register is used to delay the transmitter's internal data signal.
+ */
+#define UART_RS485_TX_DLY_NUM    0x0000000FU
+#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
+#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
+#define UART_RS485_TX_DLY_NUM_S  6
+
+/** UART_AT_CMD_PRECNT_SYNC_REG register
+ *  Pre-sequence timing configuration
+ */
+#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50)
+/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define UART_PRE_IDLE_NUM    0x0000FFFFU
+#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
+#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define UART_PRE_IDLE_NUM_S  0
+
+/** UART_AT_CMD_POSTCNT_SYNC_REG register
+ *  Post-sequence timing configuration
+ */
+#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54)
+/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define UART_POST_IDLE_NUM    0x0000FFFFU
+#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
+#define UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define UART_POST_IDLE_NUM_S  0
+
+/** UART_AT_CMD_GAPTOUT_SYNC_REG register
+ *  Timeout configuration
+ */
+#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58)
+/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define UART_RX_GAP_TOUT    0x0000FFFFU
+#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
+#define UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define UART_RX_GAP_TOUT_S  0
+
+/** UART_AT_CMD_CHAR_SYNC_REG register
+ *  AT escape sequence detection configuration
+ */
+#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c)
+/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define UART_AT_CMD_CHAR    0x000000FFU
+#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
+#define UART_AT_CMD_CHAR_V  0x000000FFU
+#define UART_AT_CMD_CHAR_S  0
+/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define UART_CHAR_NUM    0x000000FFU
+#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
+#define UART_CHAR_NUM_V  0x000000FFU
+#define UART_CHAR_NUM_S  8
+
+/** UART_MEM_CONF_REG register
+ *  UART memory power configuration
+ */
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
+/** UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define UART_MEM_FORCE_PD    (BIT(25))
+#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
+#define UART_MEM_FORCE_PD_V  0x00000001U
+#define UART_MEM_FORCE_PD_S  25
+/** UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define UART_MEM_FORCE_PU    (BIT(26))
+#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
+#define UART_MEM_FORCE_PU_V  0x00000001U
+#define UART_MEM_FORCE_PU_S  26
+
+/** UART_TOUT_CONF_SYNC_REG register
+ *  UART threshold and allocation configuration
+ */
+#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
+/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define UART_RX_TOUT_EN    (BIT(0))
+#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
+#define UART_RX_TOUT_EN_V  0x00000001U
+#define UART_RX_TOUT_EN_S  0
+/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define UART_RX_TOUT_FLOW_DIS    (BIT(1))
+#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
+#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define UART_RX_TOUT_FLOW_DIS_S  1
+/** UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define UART_RX_TOUT_THRHD    0x000003FFU
+#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
+#define UART_RX_TOUT_THRHD_V  0x000003FFU
+#define UART_RX_TOUT_THRHD_S  2
+
+/** UART_MEM_TX_STATUS_REG register
+ *  Tx-SRAM write and read offset address.
+ */
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
+/** UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0;
+ *  This register stores the offset write address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_WADDR    0x000000FFU
+#define UART_TX_SRAM_WADDR_M  (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S)
+#define UART_TX_SRAM_WADDR_V  0x000000FFU
+#define UART_TX_SRAM_WADDR_S  0
+/** UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0;
+ *  This register stores the offset read address in Tx-SRAM.
+ */
+#define UART_TX_SRAM_RADDR    0x000000FFU
+#define UART_TX_SRAM_RADDR_M  (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S)
+#define UART_TX_SRAM_RADDR_V  0x000000FFU
+#define UART_TX_SRAM_RADDR_S  9
+
+/** UART_MEM_RX_STATUS_REG register
+ *  Rx-SRAM write and read offset address.
+ */
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
+/** UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128;
+ *  This register stores the offset read address in RX-SRAM.
+ */
+#define UART_RX_SRAM_RADDR    0x000000FFU
+#define UART_RX_SRAM_RADDR_M  (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S)
+#define UART_RX_SRAM_RADDR_V  0x000000FFU
+#define UART_RX_SRAM_RADDR_S  0
+/** UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128;
+ *  This register stores the offset write address in Rx-SRAM.
+ */
+#define UART_RX_SRAM_WADDR    0x000000FFU
+#define UART_RX_SRAM_WADDR_M  (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S)
+#define UART_RX_SRAM_WADDR_V  0x000000FFU
+#define UART_RX_SRAM_WADDR_S  9
+
+/** UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70)
+/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define UART_ST_URX_OUT    0x0000000FU
+#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
+#define UART_ST_URX_OUT_V  0x0000000FU
+#define UART_ST_URX_OUT_S  0
+/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define UART_ST_UTX_OUT    0x0000000FU
+#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
+#define UART_ST_UTX_OUT_V  0x0000000FU
+#define UART_ST_UTX_OUT_S  4
+
+/** UART_POSPULSE_REG register
+ *  Autobaud high pulse register
+ */
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
+/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two positive edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_POSEDGE_MIN_CNT    0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
+#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_S  0
+
+/** UART_NEGPULSE_REG register
+ *  Autobaud low pulse register
+ */
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78)
+/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two negative edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
+#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+/** UART_LOWPULSE_REG register
+ *  Autobaud minimum low pulse duration register
+ */
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c)
+/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the value of the minimum duration time of the low level pulse.
+ *  It is used in baud rate-detect process.
+ */
+#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
+#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+/** UART_HIGHPULSE_REG register
+ *  Autobaud minimum high pulse duration register
+ */
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
+/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores  the value of the maximum duration time for the high level
+ *  pulse. It is used in baud rate-detect process.
+ */
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
+#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+/** UART_RXD_CNT_REG register
+ *  Autobaud edge change count register
+ */
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84)
+/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the count of rxd edge change. It is used in baud rate-detect
+ *  process.
+ */
+#define UART_RXD_EDGE_CNT    0x000003FFU
+#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
+#define UART_RXD_EDGE_CNT_V  0x000003FFU
+#define UART_RXD_EDGE_CNT_S  0
+
+/** UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
+/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
+#define UART_TX_SCLK_EN_V  0x00000001U
+#define UART_TX_SCLK_EN_S  24
+/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
+#define UART_RX_SCLK_EN_V  0x00000001U
+#define UART_RX_SCLK_EN_S  25
+/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Tx.
+ */
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
+#define UART_TX_RST_CORE_V  0x00000001U
+#define UART_TX_RST_CORE_S  26
+/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit to reset UART Rx.
+ */
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
+#define UART_RX_RST_CORE_V  0x00000001U
+#define UART_RX_RST_CORE_S  27
+
+/** UART_DATE_REG register
+ *  UART Version register
+ */
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c)
+/** UART_DATE : R/W; bitpos: [31:0]; default: 36720720;
+ *  This is the version register.
+ */
+#define UART_DATE    0xFFFFFFFFU
+#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
+#define UART_DATE_V  0xFFFFFFFFU
+#define UART_DATE_S  0
+
+/** UART_AFIFO_STATUS_REG register
+ *  UART AFIFO Status
+ */
+#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90)
+/** UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0;
+ *  Full signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_FULL    (BIT(0))
+#define UART_TX_AFIFO_FULL_M  (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S)
+#define UART_TX_AFIFO_FULL_V  0x00000001U
+#define UART_TX_AFIFO_FULL_S  0
+/** UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1;
+ *  Empty signal of APB TX AFIFO.
+ */
+#define UART_TX_AFIFO_EMPTY    (BIT(1))
+#define UART_TX_AFIFO_EMPTY_M  (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S)
+#define UART_TX_AFIFO_EMPTY_V  0x00000001U
+#define UART_TX_AFIFO_EMPTY_S  1
+/** UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0;
+ *  Full signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_FULL    (BIT(2))
+#define UART_RX_AFIFO_FULL_M  (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S)
+#define UART_RX_AFIFO_FULL_V  0x00000001U
+#define UART_RX_AFIFO_FULL_S  2
+/** UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1;
+ *  Empty signal of APB RX AFIFO.
+ */
+#define UART_RX_AFIFO_EMPTY    (BIT(3))
+#define UART_RX_AFIFO_EMPTY_M  (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S)
+#define UART_RX_AFIFO_EMPTY_V  0x00000001U
+#define UART_RX_AFIFO_EMPTY_S  3
+
+/** UART_REG_UPDATE_REG register
+ *  UART Registers Configuration Update register
+ */
+#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98)
+/** UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define UART_REG_UPDATE    (BIT(0))
+#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
+#define UART_REG_UPDATE_V  0x00000001U
+#define UART_REG_UPDATE_S  0
+
+/** UART_ID_REG register
+ *  UART ID register
+ */
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c)
+/** UART_ID : R/W; bitpos: [31:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define UART_ID    0xFFFFFFFFU
+#define UART_ID_M  (UART_ID_V << UART_ID_S)
+#define UART_ID_V  0xFFFFFFFFU
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/register/soc/uart_struct.h b/components/soc/esp32p4/register/soc/uart_struct.h
new file mode 100644
index 00000000000..c1b3dcb95d9
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/uart_struct.h
@@ -0,0 +1,1287 @@
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         */
+        uint32_t rxfifo_rd_byte:32;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART memory power configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** mem_force_pd : R/W; bitpos: [25]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+/** Type of tout_conf_sync register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        /** rx_tout_en : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_tout_thrhd : R/W; bitpos: [11:2]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_tout_conf_sync_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_parity_err_int_raw:1;
+        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_frm_err_int_raw:1;
+        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  This interrupt raw bit turns to high level when detects a clash between transmitter
+         *  and receiver in rs485 mode.
+         */
+        uint32_t rs485_clash_int_raw:1;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done_int_st:1;
+        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
+         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+         *  set to 1.
+         */
+        uint32_t rs485_parity_err_int_st:1;
+        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
+         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+         *  to 1.
+         */
+        uint32_t rs485_frm_err_int_st:1;
+        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
+         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+         */
+        uint32_t rs485_clash_int_st:1;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_parity_err_int_ena:1;
+        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_frm_err_int_ena:1;
+        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
+         *  This is the enable bit for rs485_clash_int_st register.
+         */
+        uint32_t rs485_clash_int_ena:1;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+         */
+        uint32_t rs485_parity_err_int_clr:1;
+        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+         */
+        uint32_t rs485_frm_err_int_clr:1;
+        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the rs485_clash_int_raw interrupt.
+         */
+        uint32_t rs485_clash_int_clr:1;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv_sync register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_sync_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0_sync register
+ *  a
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** txd_brk : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to enable IrDA loopback mode.
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [8]; default: 0;
+         *  This is the start enable bit for IrDA transmitter.
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [9]; default: 0;
+         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+         *  transmitter's 11th bit to 0.
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to invert the level of  IrDA transmitter.
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to invert the level of IrDA receiver.
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable IrDA protocol.
+         */
+        uint32_t irda_en:1;
+        /** rxd_inv : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** txd_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** dis_rx_dat_ovf : R/W; bitpos: [17]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** err_wr_mask : R/W; bitpos: [18]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for detecting baudrate.
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [20]; default: 0;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        /** sw_rts : R/W; bitpos: [21]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** rxfifo_rst : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf0_sync_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [7:0]; default: 96;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:8;
+        /** txfifo_empty_thrhd : R/W; bitpos: [15:8]; default: 96;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:8;
+        /** cts_inv : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** rts_inv : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** sw_dtr : R/W; bitpos: [20]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** clk_en : R/W; bitpos: [21]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of hwfc_conf_sync register
+ *  Hardware flow-control configuration
+ */
+typedef union {
+    struct {
+        /** rx_flow_thrhd : R/W; bitpos: [7:0]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:8;
+        /** rx_flow_en : R/W; bitpos: [8]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_hwfc_conf_sync_reg_t;
+
+/** Type of sleep_conf0 register
+ *  UART sleep configure register 0
+ */
+typedef union {
+    struct {
+        /** wk_char1 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified wake up char1 to wake up
+         */
+        uint32_t wk_char1:8;
+        /** wk_char2 : R/W; bitpos: [15:8]; default: 0;
+         *  This register restores the specified wake up char2 to wake up
+         */
+        uint32_t wk_char2:8;
+        /** wk_char3 : R/W; bitpos: [23:16]; default: 0;
+         *  This register restores the specified wake up char3 to wake up
+         */
+        uint32_t wk_char3:8;
+        /** wk_char4 : R/W; bitpos: [31:24]; default: 0;
+         *  This register restores the specified wake up char4 to wake up
+         */
+        uint32_t wk_char4:8;
+    };
+    uint32_t val;
+} uart_sleep_conf0_reg_t;
+
+/** Type of sleep_conf1 register
+ *  UART sleep configure register 1
+ */
+typedef union {
+    struct {
+        /** wk_char0 : R/W; bitpos: [7:0]; default: 0;
+         *  This register restores the specified char0 to wake up
+         */
+        uint32_t wk_char0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_sleep_conf1_reg_t;
+
+/** Type of sleep_conf2 register
+ *  UART sleep configure register 2
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        /** rx_wake_up_thrhd : R/W; bitpos: [17:10]; default: 1;
+         *  In wake up mode 1 this field is used to set the received data number threshold to
+         *  wake up chip.
+         */
+        uint32_t rx_wake_up_thrhd:8;
+        /** wk_char_num : R/W; bitpos: [20:18]; default: 5;
+         *  This register is used to select number of wake up char.
+         */
+        uint32_t wk_char_num:3;
+        /** wk_char_mask : R/W; bitpos: [25:21]; default: 0;
+         *  This register is used to mask  wake up char.
+         */
+        uint32_t wk_char_mask:5;
+        /** wk_mode_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This register is used to select wake up mode. 0: RXD toggling to wake up. 1:
+         *  received data number larger than
+         */
+        uint32_t wk_mode_sel:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_sleep_conf2_reg_t;
+
+/** Type of swfc_conf0_sync register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_character : R/W; bitpos: [7:0]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_character:8;
+        /** xoff_character : R/W; bitpos: [15:8]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_character:8;
+        /** xon_xoff_still_send : R/W; bitpos: [16]; default: 0;
+         *  In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In
+         *  this status, UART Tx can not transmit XOFF even the received data number is larger
+         *  than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when
+         *  UART Tx is disabled.
+         */
+        uint32_t xon_xoff_still_send:1;
+        /** sw_flow_con_en : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [21]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [22]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} uart_swfc_conf0_sync_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [7:0]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xon char.
+         */
+        uint32_t xon_threshold:8;
+        /** xoff_threshold : R/W; bitpos: [15:8]; default: 224;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1  it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf_sync register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_sync_reg_t;
+
+/** Type of idle_conf_sync register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_sync_reg_t;
+
+/** Type of rs485_conf_sync register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to choose the rs485 mode.
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable receiver could receive data when the transmitter is
+         *  transmitting data in rs485 mode.
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  This register is used to delay the receiver's internal data signal.
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  This register is used to delay the transmitter's internal data signal.
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_sync_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.
+         */
+        uint32_t sclk_div_b:6;      //HP UART's sclk_div_b is in hp_sys_clkrst_struct.h
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         */
+        uint32_t sclk_div_a:6;      //HP UART's sclk_div_a is in hp_sys_clkrst_struct.h
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         *  It is only used by LP UART
+         */
+        uint32_t sclk_div_num:8;    //HP UART's sclk_div_num is in hp_sys_clkrst_struct.h
+        uint32_t reserved_20:4;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit to reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [7:0]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:8;
+        uint32_t reserved_8:5;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [23:16]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:8;
+        uint32_t reserved_24:5;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** tx_sram_waddr : RO; bitpos: [7:0]; default: 0;
+         *  This register stores the offset write address in Tx-SRAM.
+         */
+        uint32_t tx_sram_waddr:8;
+        uint32_t reserved_8:1;
+        /** tx_sram_raddr : RO; bitpos: [16:9]; default: 0;
+         *  This register stores the offset read address in Tx-SRAM.
+         */
+        uint32_t tx_sram_raddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-SRAM write and read offset address.
+ */
+typedef union {
+    struct {
+        /** rx_sram_raddr : RO; bitpos: [7:0]; default: 128;
+         *  This register stores the offset read address in RX-SRAM.
+         */
+        uint32_t rx_sram_raddr:8;
+        uint32_t reserved_8:1;
+        /** rx_sram_waddr : RO; bitpos: [16:9]; default: 128;
+         *  This register stores the offset write address in Rx-SRAM.
+         */
+        uint32_t rx_sram_waddr:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+/** Type of afifo_status register
+ *  UART AFIFO Status
+ */
+typedef union {
+    struct {
+        /** tx_afifo_full : RO; bitpos: [0]; default: 0;
+         *  Full signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_full:1;
+        /** tx_afifo_empty : RO; bitpos: [1]; default: 1;
+         *  Empty signal of APB TX AFIFO.
+         */
+        uint32_t tx_afifo_empty:1;
+        /** rx_afifo_full : RO; bitpos: [2]; default: 0;
+         *  Full signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_full:1;
+        /** rx_afifo_empty : RO; bitpos: [3]; default: 1;
+         *  Empty signal of APB RX AFIFO.
+         */
+        uint32_t rx_afifo_empty:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} uart_afifo_status_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt_sync register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_sync_reg_t;
+
+/** Type of at_cmd_postcnt_sync register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_sync_reg_t;
+
+/** Type of at_cmd_gaptout_sync register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_sync_reg_t;
+
+/** Type of at_cmd_char_sync register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t at_cmd_char:8;
+        /** at_char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t at_char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_sync_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two positive edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two negative edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the value of the minimum duration time of the low level pulse.
+         *  It is used in baud rate-detect process.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores  the value of the maximum duration time for the high level
+         *  pulse. It is used in baud rate-detect process.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the count of rxd edge change. It is used in baud rate-detect
+         *  process.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36720720;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of reg_update register
+ *  UART Registers Configuration Update register
+ */
+typedef union {
+    struct {
+        /** reg_update : R/W/SC; bitpos: [0]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} uart_reg_update_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [31:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:32;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct uart_dev_t{
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_sync_reg_t clkdiv_sync;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_sync_reg_t conf0_sync;
+    volatile uart_conf1_reg_t conf1;
+    uint32_t reserved_028;
+    volatile uart_hwfc_conf_sync_reg_t hwfc_conf_sync;
+    volatile uart_sleep_conf0_reg_t sleep_conf0;
+    volatile uart_sleep_conf1_reg_t sleep_conf1;
+    volatile uart_sleep_conf2_reg_t sleep_conf2;
+    volatile uart_swfc_conf0_sync_reg_t swfc_conf0_sync;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_sync_reg_t txbrk_conf_sync;
+    volatile uart_idle_conf_sync_reg_t idle_conf_sync;
+    volatile uart_rs485_conf_sync_reg_t rs485_conf_sync;
+    volatile uart_at_cmd_precnt_sync_reg_t at_cmd_precnt_sync;
+    volatile uart_at_cmd_postcnt_sync_reg_t at_cmd_postcnt_sync;
+    volatile uart_at_cmd_gaptout_sync_reg_t at_cmd_gaptout_sync;
+    volatile uart_at_cmd_char_sync_reg_t at_cmd_char_sync;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_tout_conf_sync_reg_t tout_conf_sync;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;      /* LP_UART instance has this register reserved */
+    volatile uart_negpulse_reg_t negpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_lowpulse_reg_t lowpulse;      /* LP_UART instance has this register reserved */
+    volatile uart_highpulse_reg_t highpulse;    /* LP_UART instance has this register reserved */
+    volatile uart_rxd_cnt_reg_t rxd_cnt;        /* LP_UART instance has this register reserved */
+    volatile uart_clk_conf_reg_t clk_conf;      /* UART0/1/2/3/4 instance have this register reserved, configure in corresponding PCR registers */
+    volatile uart_date_reg_t date;
+    volatile uart_afifo_status_reg_t afifo_status;
+    uint32_t reserved_094;
+    volatile uart_reg_update_reg_t reg_update;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+extern uart_dev_t UART2;
+extern uart_dev_t UART3;
+extern uart_dev_t UART4;
+extern uart_dev_t LP_UART;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0xa0, "Invalid size of uart_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/uhci_reg.h b/components/soc/esp32p4/register/soc/uhci_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/uhci_reg.h
rename to components/soc/esp32p4/register/soc/uhci_reg.h
diff --git a/components/soc/esp32p4/include/soc/uhci_struct.h b/components/soc/esp32p4/register/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/uhci_struct.h
rename to components/soc/esp32p4/register/soc/uhci_struct.h
diff --git a/components/soc/esp32p4/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/soc/usb_serial_jtag_reg.h
new file mode 100644
index 00000000000..6de18f3a76f
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,1282 @@
+/**
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+ *  into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check
+ *  USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
+ *  received, then read data from UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB
+ *  Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when level of RTS from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M  (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when level of DTR from usb serial channel
+ *  is changed.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M  (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw interrupt bit turns to high level when level of GET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw interrupt bit turns to high level when level of SET LINE CODING request is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S  15
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S  15
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M  (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M  (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S  15
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR    (BIT(12))
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M  (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S  12
+/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR    (BIT(13))
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M  (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S)
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S  13
+/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR    (BIT(14))
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S  14
+/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR    (BIT(15))
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M  (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S)
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S  15
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFH_S  3
+/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFL_S  5
+/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
+ *  disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
+ *  through GPIO Matrix.
+ */
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(15))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S)
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  15
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1;
+ *  USB RCV value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1;
+ *  USB D+ rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+ *  detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_SERIAL_JTAG_CHIP_RST_REG register
+ *  CDC-ACM chip reset control.
+ */
+#define USB_SERIAL_JTAG_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c)
+/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0;
+ *  1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_RTS    (BIT(0))
+#define USB_SERIAL_JTAG_RTS_M  (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S)
+#define USB_SERIAL_JTAG_RTS_V  0x00000001U
+#define USB_SERIAL_JTAG_RTS_S  0
+/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0;
+ *  1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
+ */
+#define USB_SERIAL_JTAG_DTR    (BIT(1))
+#define USB_SERIAL_JTAG_DTR_M  (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S)
+#define USB_SERIAL_JTAG_DTR_V  0x00000001U
+#define USB_SERIAL_JTAG_DTR_S  1
+/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to disable chip reset from usb serial channel to reset chip.
+ */
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS    (BIT(2))
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M  (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S)
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S  2
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG register
+ *  W0 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50)
+/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_M  (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG register
+ *  W1 of SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54)
+/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_BCHAR_FORMAT_S  0
+/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_M  (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by host through SET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_M  (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_BDATA_BITS_S  16
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG register
+ *  W0 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58)
+/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0;
+ *  The value of dwDTERate set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M  (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S)
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S  0
+
+/** USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG register
+ *  W1 of GET_LINE_CODING command.
+ */
+#define USB_SERIAL_JTAG_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c)
+/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0;
+ *  The value of bCharFormat set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BDATA_BITS    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_M  (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S)
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BDATA_BITS_S  0
+/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0;
+ *  The value of bParityTpye set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M  (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S)
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S  8
+/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0;
+ *  The value of bDataBits set by software which is requested by GET_LINE_CODING
+ *  command.
+ */
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT    0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M  (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S)
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V  0x000000FFU
+#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S  16
+
+/** USB_SERIAL_JTAG_CONFIG_UPDATE_REG register
+ *  Configuration registers' value update
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60)
+/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to this register would update the value of configure registers from APB
+ *  clock domain to 48MHz clock domain.
+ */
+#define USB_SERIAL_JTAG_CONFIG_UPDATE    (BIT(0))
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_M  (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S)
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_V  0x00000001U
+#define USB_SERIAL_JTAG_CONFIG_UPDATE_S  0
+
+/** USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG register
+ *  Serial AFIFO configure register
+ */
+#define USB_SERIAL_JTAG_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64)
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR    (BIT(0))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to reset CDC_ACM IN async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S  2
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
+/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S  4
+/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0;
+ *  CDC_ACM OUT IN async FIFO empty signal in write clock domain.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL    (BIT(5))
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M  (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S  5
+
+/** USB_SERIAL_JTAG_BUS_RESET_ST_REG register
+ *  USB Bus reset status register
+ */
+#define USB_SERIAL_JTAG_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68)
+/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1;
+ *  USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
+ *  reset is released.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST    (BIT(0))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S  0
+
+/** USB_SERIAL_JTAG_ECO_LOW_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c)
+/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M  (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S)
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S  0
+
+/** USB_SERIAL_JTAG_ECO_HIGH_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70)
+/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S)
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S  0
+
+/** USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74)
+/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_RESULT_48    (BIT(0))
+#define USB_SERIAL_JTAG_RDN_RESULT_48_M  (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S)
+#define USB_SERIAL_JTAG_RDN_RESULT_48_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_RESULT_48_S  0
+/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_ENA_48    (BIT(1))
+#define USB_SERIAL_JTAG_RDN_ENA_48_M  (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S)
+#define USB_SERIAL_JTAG_RDN_ENA_48_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_ENA_48_S  1
+
+/** USB_SERIAL_JTAG_ECO_LOW_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78)
+/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M  (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S)
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S  0
+
+/** USB_SERIAL_JTAG_ECO_HIGH_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c)
+/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M  (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S)
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S  0
+
+/** USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG register
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_RESULT_APB    (BIT(0))
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_M  (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S)
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_RESULT_APB_S  0
+/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define USB_SERIAL_JTAG_RDN_ENA_APB    (BIT(1))
+#define USB_SERIAL_JTAG_RDN_ENA_APB_M  (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S)
+#define USB_SERIAL_JTAG_RDN_ENA_APB_V  0x00000001U
+#define USB_SERIAL_JTAG_RDN_ENA_APB_S  1
+
+/** USB_SERIAL_JTAG_SRAM_CTRL_REG register
+ *  PPA SRAM Control Register
+ */
+#define USB_SERIAL_JTAG_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84)
+/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896;
+ *  Control signals
+ */
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL    0x00003FFFU
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M  (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S)
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V  0x00003FFFU
+#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S  0
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  Date register
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88)
+/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752;
+ *  register version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32p4/register/soc/usb_serial_jtag_struct.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h
rename to components/soc/esp32p4/register/soc/usb_serial_jtag_struct.h
diff --git a/components/soc/esp32p4/include/soc/usb_wrap_reg.h b/components/soc/esp32p4/register/soc/usb_wrap_reg.h
similarity index 100%
rename from components/soc/esp32p4/include/soc/usb_wrap_reg.h
rename to components/soc/esp32p4/register/soc/usb_wrap_reg.h
diff --git a/components/soc/esp32p4/register/soc/usb_wrap_struct.h b/components/soc/esp32p4/register/soc/usb_wrap_struct.h
new file mode 100644
index 00000000000..dd1b234e342
--- /dev/null
+++ b/components/soc/esp32p4/register/soc/usb_wrap_struct.h
@@ -0,0 +1,181 @@
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: USB wrapper registers. */
+/** Type of otg_conf register
+ *  USB wrapper configuration registers.
+ */
+typedef union {
+    struct {
+        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to enable the software over-ride of srp session end signal. 1'b0:
+         *  the signal is controlled by the chip input, 1'b1: the signal is controlled by the
+         *  software.
+         */
+        uint32_t srp_sessend_override:1;
+        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
+         *  Software over-ride value of srp session end signal.
+         */
+        uint32_t srp_sessend_value:1;
+        /** phy_sel : R/W; bitpos: [2]; default: 0;
+         *  Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
+         */
+        uint32_t phy_sel:1;
+        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
+         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pd:1;
+        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
+         *  Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
+         */
+        uint32_t dbnce_fltr_bypass:1;
+        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
+         *  Enable software controlle USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [6]; default: 0;
+         *  USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [8:7]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV.
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [10:9]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV.
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [11]; default: 0;
+         *  Enable software controlle input  threshold.
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
+         *  Enable software controlle USB D+ D- pullup pulldown.
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [13]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [15]; default: 0;
+         *  Controlle USB D+ pullup.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
+         *  Controlle USB D+ pulldown.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [17]; default: 0;
+         *  Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [18]; default: 0;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
+         *  Force ahb clock always on.
+         */
+        uint32_t ahb_clk_force_on:1;
+        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
+         *  Force phy clock always on.
+         */
+        uint32_t phy_clk_force_on:1;
+        /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
+         *  Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
+         */
+        uint32_t phy_tx_edge_sel:1;
+        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
+         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pu:1;
+        uint32_t reserved_23:8;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Disable auto clock gating of CSR registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} usb_wrap_otg_conf_reg_t;
+
+/** Type of test_conf register
+ *  TEST relative configuration registers.
+ */
+typedef union {
+    struct {
+        /** test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable to test the USB pad.
+         */
+        uint32_t test_enable:1;
+        /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test.
+         */
+        uint32_t test_usb_wrap_oe:1;
+        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test.
+         */
+        uint32_t test_tx_dp:1;
+        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test.
+         */
+        uint32_t test_tx_dm:1;
+        /** test_rx_rcv : RO; bitpos: [4]; default: 0;
+         *  USB differential rx value in test.
+         */
+        uint32_t test_rx_rcv:1;
+        /** test_rx_dp : RO; bitpos: [5]; default: 0;
+         *  USB D+ rx value in test.
+         */
+        uint32_t test_rx_dp:1;
+        /** test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test.
+         */
+        uint32_t test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_wrap_test_conf_reg_t;
+
+/** Type of date register
+ *  Date register.
+ */
+typedef union {
+    struct {
+        /** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
+         *  Date register.
+         */
+        uint32_t usb_wrap_date:32;
+    };
+    uint32_t val;
+} usb_wrap_date_reg_t;
+
+
+typedef struct usb_wrap_dev_t {
+    volatile usb_wrap_otg_conf_reg_t otg_conf;
+    volatile usb_wrap_test_conf_reg_t test_conf;
+    uint32_t reserved_008[253];
+    volatile usb_wrap_date_reg_t date;
+} usb_wrap_dev_t;
+
+extern usb_wrap_dev_t USB_WRAP;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32p4/rmt_periph.c b/components/soc/esp32p4/rmt_periph.c
index ec8625bc945..e838ccb182a 100644
--- a/components/soc/esp32p4/rmt_periph.c
+++ b/components/soc/esp32p4/rmt_periph.c
@@ -76,6 +76,7 @@ static const regdma_entries_config_t rmt_regdma_entries[] = {
 
 const rmt_reg_retention_info_t rmt_reg_retention_info[SOC_RMT_GROUPS] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_RMT0,
         .regdma_entry_array = rmt_regdma_entries,
         .array_size = ARRAY_SIZE(rmt_regdma_entries)
     },
diff --git a/components/soc/esp32p4/spi_periph.c b/components/soc/esp32p4/spi_periph.c
index 5a629b6604c..db30a6bf689 100644
--- a/components/soc/esp32p4/spi_periph.c
+++ b/components/soc/esp32p4/spi_periph.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,29 +13,6 @@
 const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
     {
         // MSPI on P4 has dedicated iomux pins
-        .spiclk_out = -1,
-        .spiclk_in = -1,
-        .spid_out = -1,
-        .spiq_out = -1,
-        .spiwp_out = -1,
-        .spihd_out = -1,
-        .spid_in = -1,
-        .spiq_in = -1,
-        .spiwp_in = -1,
-        .spihd_in = -1,
-        .spics_out = {-1},
-        .spics_in = -1,
-        .spiclk_iomux_pin = -1,
-        .spid_iomux_pin = -1,
-        .spiq_iomux_pin = -1,
-        .spiwp_iomux_pin = -1,
-        .spihd_iomux_pin = -1,
-        .spics0_iomux_pin = -1,
-        .irq = -1,
-        .irq_dma = -1,
-        .module = -1,
-        .hw = NULL,
-        .func = -1,
     }, {
         .spiclk_out = SPI2_CK_PAD_OUT_IDX,
         .spiclk_in = SPI2_CK_PAD_IN_IDX,
@@ -65,7 +42,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
         .irq = ETS_SPI2_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_GPSPI2_MODULE,
         .hw = &GPSPI2,
         .func = SPI2_FUNC_NUM,
     }, {
@@ -73,7 +49,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spiclk_in = SPI3_CK_PAD_IN_IDX,
         .spid_out = SPI3_D_PAD_OUT_IDX,
         .spiq_out = SPI3_QO_PAD_OUT_IDX,
-        //SPI3 doesn't have wp and hd signals
         .spiwp_out = SPI3_WP_PAD_OUT_IDX,
         .spihd_out = SPI3_HOLD_PAD_OUT_IDX,
         .spid_in = SPI3_D_PAD_IN_IDX,
@@ -91,8 +66,56 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = -1,
         .irq = ETS_SPI3_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_GPSPI3_MODULE,
         .hw = &GPSPI3,
         .func = -1,
     }
 };
+
+/**
+ * Backup registers in Light sleep: (total cnt 12)
+ *
+ * cmd
+ * addr
+ * ctrl
+ * clock
+ * user
+ * user1
+ * user2
+ * ms_dlen
+ * misc
+ * dma_conf
+ * dma_int_ena
+ * slave
+ */
+#define SPI_RETENTION_REGS_CNT 12
+static const uint32_t spi_regs_map[4] = {0x31ff, 0x1000000, 0x0, 0x0};
+#define SPI_REG_RETENTION_ENTRIES(num) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
+                                               REG_SPI_BASE(num), REG_SPI_BASE(num), \
+                                               SPI_RETENTION_REGS_CNT, 0, 0, \
+                                               spi_regs_map[0], spi_regs_map[1], \
+                                               spi_regs_map[2], spi_regs_map[3]), \
+            .owner = ENTRY(0) }, \
+    /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
+                                            SPI_DMA_INT_SET_REG(num), \
+                                            SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET , \
+                                            UINT32_MAX, 1, 0), \
+            .owner = ENTRY(0) }, \
+}
+
+static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2);   // '2' for GPSPI2
+static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3);
+
+const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = {   // '-1' to except mspi
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI2,
+        .entry_array = spi2_regs_retention,
+        .array_size = ARRAY_SIZE(spi2_regs_retention),
+    },
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI3,
+        .entry_array = spi3_regs_retention,
+        .array_size = ARRAY_SIZE(spi3_regs_retention),
+    },
+};
diff --git a/components/soc/esp32p4/twai_periph.c b/components/soc/esp32p4/twai_periph.c
index 67b016fa0d6..b9fde3d047e 100644
--- a/components/soc/esp32p4/twai_periph.c
+++ b/components/soc/esp32p4/twai_periph.c
@@ -1,10 +1,11 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "soc/twai_periph.h"
+#include "soc/twai_reg.h"
 #include "soc/gpio_sig_map.h"
 
 const twai_controller_signal_conn_t twai_controller_periph_signals = {
@@ -38,3 +39,55 @@ const twai_controller_signal_conn_t twai_controller_periph_signals = {
         }
     }
 };
+
+/**
+ * TWAI Registers to be saved during sleep retention
+ * - TWAI_MODE_REG
+ * - TWAI_INTERRUPT_ENABLE_REG
+ * - TWAI_BUS_TIMING_0_REG / TWAI_BUS_TIMING_1_REG
+ * - TWAI_ERR_WARNING_LIMIT_REG
+ * - TWAI_RX_ERR_CNT_REG
+ * - TWAI_TX_ERR_CNT_REG
+ * - TWAI_DATA_x_REG
+ * - TWAI_CLOCK_DIVIDER_REG
+ * - TWAI_SW_STANDBY_CFG_REG
+ * - TWAI_HW_CFG_REG
+ * - TWAI_HW_STANDBY_CNT_REG
+ * - TWAI_IDLE_INTR_CNT_REG
+ * - TWAI_ECO_CFG_REG
+ * - TWAI_TIMESTAMP_PRESCALER_REG
+ * - TWAI_TIMESTAMP_CFG_REG
+*/
+#define TWAI_RETENTION_REGS_CNT 28
+#define TWAI_RETENTION_REGS_BASE(i) REG_TWAI_BASE(i)
+static const uint32_t twai_regs_map[4] = {0x9fffe0d1, 0xdf, 0x0, 0x0};
+#define TWAI_SLEEP_RETENTION_ENTRIES(id) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TWAI_LINK(0x00), \
+                                               TWAI_RETENTION_REGS_BASE(id), TWAI_RETENTION_REGS_BASE(id), \
+                                               TWAI_RETENTION_REGS_CNT, 0, 0, \
+                                               twai_regs_map[0], twai_regs_map[1], \
+                                               twai_regs_map[2], twai_regs_map[3]), \
+                                               .owner = ENTRY(0) }, \
+}
+
+static const regdma_entries_config_t twai0_regs_retention[] = TWAI_SLEEP_RETENTION_ENTRIES(0);
+static const regdma_entries_config_t twai1_regs_retention[] = TWAI_SLEEP_RETENTION_ENTRIES(1);
+static const regdma_entries_config_t twai2_regs_retention[] = TWAI_SLEEP_RETENTION_ENTRIES(2);
+
+const twai_reg_retention_info_t twai_reg_retention_info[SOC_TWAI_CONTROLLER_NUM] = {
+    [0] = {
+        .module_id = SLEEP_RETENTION_MODULE_TWAI0,
+        .entry_array = twai0_regs_retention,
+        .array_size = ARRAY_SIZE(twai0_regs_retention)
+    },
+    [1] = {
+        .module_id = SLEEP_RETENTION_MODULE_TWAI1,
+        .entry_array = twai1_regs_retention,
+        .array_size = ARRAY_SIZE(twai1_regs_retention)
+    },
+    [2] = {
+        .module_id = SLEEP_RETENTION_MODULE_TWAI2,
+        .entry_array = twai2_regs_retention,
+        .array_size = ARRAY_SIZE(twai2_regs_retention)
+    },
+};
diff --git a/components/soc/esp32p4/uart_periph.c b/components/soc/esp32p4/uart_periph.c
index 98d00fd4a22..c28c0be8146 100644
--- a/components/soc/esp32p4/uart_periph.c
+++ b/components/soc/esp32p4/uart_periph.c
@@ -253,22 +253,27 @@ static const regdma_entries_config_t uart4_regdma_entries[] = UART_SLEEP_RETENTI
 
 const uart_reg_retention_info_t uart_reg_retention_info[SOC_UART_HP_NUM] = {
     [0] = {
+        .module = SLEEP_RETENTION_MODULE_UART0,
         .regdma_entry_array = uart0_regdma_entries,
         .array_size = ARRAY_SIZE(uart0_regdma_entries),
     },
     [1] = {
+        .module = SLEEP_RETENTION_MODULE_UART1,
         .regdma_entry_array = uart1_regdma_entries,
         .array_size = ARRAY_SIZE(uart1_regdma_entries),
     },
     [2] = {
+        .module = SLEEP_RETENTION_MODULE_UART2,
         .regdma_entry_array = uart2_regdma_entries,
         .array_size = ARRAY_SIZE(uart2_regdma_entries),
     },
     [3] = {
+        .module = SLEEP_RETENTION_MODULE_UART3,
         .regdma_entry_array = uart3_regdma_entries,
         .array_size = ARRAY_SIZE(uart3_regdma_entries),
     },
     [4] = {
+        .module = SLEEP_RETENTION_MODULE_UART4,
         .regdma_entry_array = uart4_regdma_entries,
         .array_size = ARRAY_SIZE(uart4_regdma_entries),
     },
diff --git a/components/soc/esp32p4/usb_dwc_periph.c b/components/soc/esp32p4/usb_dwc_periph.c
new file mode 100644
index 00000000000..23fecc8afeb
--- /dev/null
+++ b/components/soc/esp32p4/usb_dwc_periph.c
@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include "soc/interrupts.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/usb_dwc_periph.h"
+#include "soc/usb_dwc_struct.h"
+
+/* -------------------------------- Private --------------------------------- */
+
+static const usb_utmi_otg_signal_conn_t dwc_fs_otg_signals = {
+    // Inputs
+    .iddig          = USB_OTG11_IDDIG_PAD_IN_IDX,
+    .avalid         = USB_OTG11_AVALID_PAD_IN_IDX,
+    .bvalid         = USB_SRP_BVALID_PAD_IN_IDX,
+    .vbusvalid      = USB_OTG11_VBUSVALID_PAD_IN_IDX,
+    .sessend        = USB_SRP_SESSEND_PAD_IN_IDX,
+    // Outputs
+    .idpullup       = USB_OTG11_IDPULLUP_PAD_OUT_IDX,
+    .dppulldown     = USB_OTG11_DPPULLDOWN_PAD_OUT_IDX,
+    .dmpulldown     = USB_OTG11_DMPULLDOWN_PAD_OUT_IDX,
+    .drvvbus        = USB_OTG11_DRVVBUS_PAD_OUT_IDX,
+    .chrgvbus       = USB_SRP_CHRGVBUS_PAD_OUT_IDX,
+    .dischrgvbus    = USB_SRP_DISCHRGVBUS_PAD_OUT_IDX,
+};
+
+/* --------------------------------- Public --------------------------------- */
+
+const usb_dwc_info_t usb_dwc_info = {
+    .controllers = {
+        // High-Speed USB-DWC
+        [0] = {
+            .fsls_signals = NULL,
+            .otg_signals = NULL,
+            .irq = ETS_USB_OTG_INTR_SOURCE,
+            .irq_2nd_cpu = ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE,
+        },
+        // Full-Speed USB-DWC
+        [1] = {
+            .fsls_signals = NULL,
+            .otg_signals = &dwc_fs_otg_signals,
+            .irq = ETS_USB_OTG11_CH0_INTR_SOURCE,
+            .irq_2nd_cpu = -1,
+        },
+    },
+};
diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
index ebb997e5406..a066b28c17f 100644
--- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
@@ -451,6 +451,10 @@ config SOC_I2C_SUPPORT_SLAVE
     bool
     default y
 
+config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+    bool
+    default y
+
 config SOC_I2C_SUPPORT_HW_CLR_BUS
     bool
     default y
@@ -535,6 +539,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 8
@@ -823,6 +831,10 @@ config SOC_TOUCH_SUPPORT_PROX_SENSING
     bool
     default y
 
+config SOC_TOUCH_SUPPORT_DENOISE_CHAN
+    bool
+    default y
+
 config SOC_TOUCH_PROXIMITY_CHANNEL_NUM
     int
     default 3
@@ -1143,6 +1155,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D4
+    bool
+    default y
+
 config SOC_COEX_HW_PTI
     bool
     default y
diff --git a/components/soc/esp32s2/include/soc/clk_tree_defs.h b/components/soc/esp32s2/include/soc/clk_tree_defs.h
index a0c170c57d8..51331a55783 100644
--- a/components/soc/esp32s2/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32s2/include/soc/clk_tree_defs.h
@@ -21,7 +21,7 @@ extern "C" {
  *
  * 2) External 40MHz Crystal Clock: XTAL
  *
- * 3) Internal 90kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
+ * 3) Internal 90kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~90kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.
@@ -84,9 +84,12 @@ typedef enum {
  */
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_XTAL_D4 = 0,      /*!< Select XTAL_D4_CLK (may referred as XTAL_CLK_DIV_4) as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 1,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< XTAL_D4_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D4, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D4` */
 } soc_rtc_fast_clk_src_t;
 
 /**
diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h
index 966adf439c8..eb4d0eef06a 100644
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -200,6 +200,7 @@
 #define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
 #define SOC_I2C_CMD_REG_NUM    (16) /*!< Number of I2C command registers */
 #define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
 
 // FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
 //ESP32-S2 support hardware clear bus
@@ -233,6 +234,7 @@
 #define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
 #define SOC_LEDC_SUPPORT_REF_TICK        (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK      (1)
+#define SOC_LEDC_TIMER_NUM               (4)
 #define SOC_LEDC_CHANNEL_NUM             (8)
 #define SOC_LEDC_TIMER_BIT_WIDTH         (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP       (1)
@@ -344,6 +346,7 @@
 #define SOC_TOUCH_SUPPORT_SLEEP_WAKEUP       (1)     /*!< Touch sensor supports sleep awake */
 #define SOC_TOUCH_SUPPORT_WATERPROOF        (1)     /*!< Touch sensor supports waterproof */
 #define SOC_TOUCH_SUPPORT_PROX_SENSING      (1)     /*!< Touch sensor supports proximity sensing */
+#define SOC_TOUCH_SUPPORT_DENOISE_CHAN      (1)     /*!< Touch sensor supports denoise channel */
 #define SOC_TOUCH_PROXIMITY_CHANNEL_NUM     (3)     /*!< Support touch proximity channel number. */
 
 #define SOC_TOUCH_SAMPLE_CFG_NUM            (1U)    /*!< The sample configuration number in total, each sampler can be used to sample on one frequency */
@@ -480,6 +483,8 @@
 
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D4           (1)     /*!< Support XTAL_D4 clock as the LP_FAST clock source */
+
 /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
 #define SOC_COEX_HW_PTI                 (1)
 /* ---------------------------- Compatibility ------------------------------- */
diff --git a/components/soc/esp32s2/include/soc/usb_dwc_struct.h b/components/soc/esp32s2/include/soc/usb_dwc_struct.h
index c6da8d901f1..4d8f3e4a797 100644
--- a/components/soc/esp32s2/include/soc/usb_dwc_struct.h
+++ b/components/soc/esp32s2/include/soc/usb_dwc_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -88,7 +88,7 @@ typedef union {
     struct {
         uint32_t toutcal: 3;
         uint32_t phyif: 1;
-        uint32_t reserved_4: 1;
+        uint32_t ulpiutmisel: 1;
         uint32_t fsintf: 1;
         uint32_t physel: 1;
         uint32_t reserved_7: 1;
diff --git a/components/soc/esp32s2/interrupts.c b/components/soc/esp32s2/interrupts.c
index 460c907ef0c..9e566ceb49e 100644
--- a/components/soc/esp32s2/interrupts.c
+++ b/components/soc/esp32s2/interrupts.c
@@ -43,7 +43,7 @@ const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
     [33] = "SPI2",
     [34] = "SPI3",
     [35] = "I2S0",
-    [36] = "I2S1",
+    [36] = "RESERVED",
     [37] = "UART0",
     [38] = "UART1",
     [39] = "UART2",
diff --git a/components/soc/esp32s2/register/soc/interrupt_reg.h b/components/soc/esp32s2/register/soc/interrupt_reg.h
index a0b7bc1a3fe..dace8948cf4 100644
--- a/components/soc/esp32s2/register/soc/interrupt_reg.h
+++ b/components/soc/esp32s2/register/soc/interrupt_reg.h
@@ -299,14 +299,6 @@ extern "C" {
 #define DPORT_PRO_I2S0_INT_MAP_V  0x1F
 #define DPORT_PRO_I2S0_INT_MAP_S  0
 
-#define DPORT_PRO_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x090)
-/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define DPORT_PRO_I2S1_INT_MAP  0x0000001F
-#define DPORT_PRO_I2S1_INT_MAP_M  ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S))
-#define DPORT_PRO_I2S1_INT_MAP_V  0x1F
-#define DPORT_PRO_I2S1_INT_MAP_S  0
-
 #define DPORT_PRO_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x094)
 /* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
 /*description: */
diff --git a/components/soc/esp32s2/register/soc/system_reg.h b/components/soc/esp32s2/register/soc/system_reg.h
index 87f02a07a61..9058fd0f462 100644
--- a/components/soc/esp32s2/register/soc/system_reg.h
+++ b/components/soc/esp32s2/register/soc/system_reg.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -236,12 +236,6 @@ extern "C" {
 #define DPORT_SPI2_DMA_CLK_EN_M  (BIT(22))
 #define DPORT_SPI2_DMA_CLK_EN_V  0x1
 #define DPORT_SPI2_DMA_CLK_EN_S  22
-/* DPORT_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_I2S1_CLK_EN  (BIT(21))
-#define DPORT_I2S1_CLK_EN_M  (BIT(21))
-#define DPORT_I2S1_CLK_EN_V  0x1
-#define DPORT_I2S1_CLK_EN_S  21
 /* DPORT_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
 /*description: */
 #define DPORT_PWM1_CLK_EN  (BIT(20))
@@ -464,12 +458,6 @@ extern "C" {
 #define DPORT_SPI2_DMA_RST_M  (BIT(22))
 #define DPORT_SPI2_DMA_RST_V  0x1
 #define DPORT_SPI2_DMA_RST_S  22
-/* DPORT_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: */
-#define DPORT_I2S1_RST  (BIT(21))
-#define DPORT_I2S1_RST_M  (BIT(21))
-#define DPORT_I2S1_RST_V  0x1
-#define DPORT_I2S1_RST_S  21
 /* DPORT_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
 /*description: */
 #define DPORT_PWM1_RST  (BIT(20))
diff --git a/components/soc/esp32s2/register/soc/uart_struct.h b/components/soc/esp32s2/register/soc/uart_struct.h
index d7e292e2b06..49659b91ecf 100644
--- a/components/soc/esp32s2/register/soc/uart_struct.h
+++ b/components/soc/esp32s2/register/soc/uart_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -241,7 +241,7 @@ typedef volatile struct uart_dev_s {
     union {
         struct {
             uint32_t xoff_threshold: 9;
-            uint32_t xoff_char:      8;
+            uint32_t xoff_character: 8;
             uint32_t reserved17:    15;
         };
         uint32_t val;
@@ -249,7 +249,7 @@ typedef volatile struct uart_dev_s {
     union {
         struct {
             uint32_t xon_threshold: 9;
-            uint32_t xon_char:      8;
+            uint32_t xon_character: 8;
             uint32_t reserved17:   15;
         };
         uint32_t val;
@@ -300,7 +300,7 @@ typedef volatile struct uart_dev_s {
     union {
         struct {
             uint32_t data:        8;
-            uint32_t char_num:    8;
+            uint32_t at_char_num: 8;
             uint32_t reserved16: 16;
         };
         uint32_t val;
diff --git a/components/soc/esp32s2/spi_periph.c b/components/soc/esp32s2/spi_periph.c
index 2dfcdfb20bc..c1ed623608c 100644
--- a/components/soc/esp32s2/spi_periph.c
+++ b/components/soc/esp32s2/spi_periph.c
@@ -32,7 +32,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = MSPI_IOMUX_PIN_NUM_CS0,
         .irq = ETS_SPI1_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_SPI_MODULE,
         .hw = (spi_dev_t *) &SPIMEM1,
         .func = MSPI_FUNC_NUM,
 
@@ -65,7 +64,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS,
         .irq = ETS_SPI2_INTR_SOURCE,
         .irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
-        .module = PERIPH_FSPI_MODULE,
         .hw = &GPSPI2,
         .func = FSPI_FUNC_NUM,
     }, {
@@ -91,7 +89,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = -1,
         .irq = ETS_SPI3_INTR_SOURCE,
         .irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
-        .module = PERIPH_HSPI_MODULE,
         .hw = &GPSPI3,
         .func = -1,
     }
diff --git a/components/soc/esp32s2/usb_dwc_periph.c b/components/soc/esp32s2/usb_dwc_periph.c
index eba3eaaf60b..2cb76077e76 100644
--- a/components/soc/esp32s2/usb_dwc_periph.c
+++ b/components/soc/esp32s2/usb_dwc_periph.c
@@ -4,8 +4,78 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/usb_dwc_periph.h"
 #include "soc/gpio_sig_map.h"
+#include "soc/usb_periph.h"
+#include "soc/interrupts.h"
+#include "soc/usb_dwc_periph.h"
+
+/* -------------------------------- Private --------------------------------- */
+
+static const usb_fsls_serial_signal_conn_t fsls_signals = {
+    // Inputs
+    .rx_dp          = USB_EXTPHY_VP_IDX,
+    .rx_dm          = USB_EXTPHY_VM_IDX,
+    .rx_rcv         = USB_EXTPHY_RCV_IDX,
+    // Outputs
+    .suspend_n      = USB_EXTPHY_SUSPND_IDX,
+    .tx_enable_n    = USB_EXTPHY_OEN_IDX,
+    .tx_dp          = USB_EXTPHY_VPO_IDX,
+    .tx_dm          = USB_EXTPHY_VMO_IDX,
+    .fs_edge_sel    = USB_EXTPHY_SPEED_IDX,
+};
+
+static const usb_utmi_otg_signal_conn_t otg_signals = {
+    // Inputs
+    .iddig          = USB_OTG_IDDIG_IN_IDX,
+    .avalid         = USB_OTG_AVALID_IN_IDX,
+    .bvalid         = USB_SRP_BVALID_IN_IDX,
+    .vbusvalid      = USB_OTG_VBUSVALID_IN_IDX,
+    .sessend        = USB_SRP_SESSEND_IN_IDX,
+    // Outputs
+    .idpullup       = USB_OTG_IDPULLUP_IDX,
+    .dppulldown     = USB_OTG_DPPULLDOWN_IDX,
+    .dmpulldown     = USB_OTG_DMPULLDOWN_IDX,
+    .drvvbus        = USB_OTG_DRVVBUS_IDX,
+    .chrgvbus       = USB_SRP_CHRGVBUS_IDX,
+    .dischrgvbus    = USB_SRP_DISCHRGVBUS_IDX,
+};
+
+/* --------------------------------- Public --------------------------------- */
+
+const usb_dwc_info_t usb_dwc_info = {
+    .controllers = {
+        [0] = {
+            .fsls_signals = &fsls_signals,
+            .otg_signals = &otg_signals,
+            .irq = ETS_USB_INTR_SOURCE,
+            .irq_2nd_cpu = -1,
+        },
+    },
+};
+
+/* ------------------------------- Deprecated ------------------------------- */
+
+/*
+Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
+PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
+matrix. Thus, this mapping of signals to IO pins is meaningless.
+
+Todo: Remove in IDF v6.0 (IDF-9029)
+*/
+const usb_iopin_dsc_t usb_periph_iopins[] = {
+    {USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
+    {USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
+    {USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
+    {USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
+    {USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
+    {USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
+    {GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0},     //connected connector is mini-B
+    //connected connector is mini-B
+    {GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0},    //HIGH to force USB device mode
+    {GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
+    {GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
+    {-1, -1, 0, 0}
+};
 
 /*
  Bunch of constants for USB peripheral: GPIO signals
diff --git a/components/soc/esp32s2/usb_periph.c b/components/soc/esp32s2/usb_periph.c
deleted file mode 100644
index a3fda7193e3..00000000000
--- a/components/soc/esp32s2/usb_periph.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/soc_caps.h"
-#include "soc/usb_periph.h"
-
-/*
-Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
-PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
-matrix. Thus, this mapping of signals to IO pins is meaningless.
-
-Todo: Remove in IDF v6.0 (IDF-9029)
-*/
-const usb_iopin_dsc_t usb_periph_iopins[] = {
-    {USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
-    {USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
-    {USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
-    {USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
-    {USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
-    {USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
-    {GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0},     //connected connector is mini-B
-    //connected connector is mini-B
-    {GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0},    //HIGH to force USB device mode
-    {GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
-    {GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
-    {-1, -1, 0, 0}
-};
diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
index 649a3da6ca8..45e03084baa 100644
--- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
@@ -551,6 +551,10 @@ config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
     bool
     default y
 
+config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
+    bool
+    default y
+
 config SOC_I2S_NUM
     int
     default 2
@@ -603,6 +607,10 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK
     bool
     default y
 
+config SOC_LEDC_TIMER_NUM
+    int
+    default 4
+
 config SOC_LEDC_CHANNEL_NUM
     int
     default 8
@@ -999,6 +1007,10 @@ config SOC_TOUCH_SUPPORT_PROX_SENSING
     bool
     default y
 
+config SOC_TOUCH_SUPPORT_DENOISE_CHAN
+    bool
+    default y
+
 config SOC_TOUCH_PROXIMITY_CHANNEL_NUM
     int
     default 3
@@ -1235,6 +1247,10 @@ config SOC_CLK_XTAL32K_SUPPORTED
     bool
     default y
 
+config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
+    bool
+    default y
+
 config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
     bool
     default y
diff --git a/components/soc/esp32s3/include/soc/apb_ctrl_reg.h b/components/soc/esp32s3/include/soc/apb_ctrl_reg.h
deleted file mode 100644
index 845394f702e..00000000000
--- a/components/soc/esp32s3/include/soc/apb_ctrl_reg.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_APB_CTRL_REG_H_
-#define _SOC_APB_CTRL_REG_H_
-
-#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x0)
-/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_RST_TICK_CNT    (BIT(12))
-#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
-#define APB_CTRL_RST_TICK_CNT_V  0x1
-#define APB_CTRL_RST_TICK_CNT_S  12
-/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_CLK_EN    (BIT(11))
-#define APB_CTRL_CLK_EN_M  (BIT(11))
-#define APB_CTRL_CLK_EN_V  0x1
-#define APB_CTRL_CLK_EN_S  11
-/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_CLK_320M_EN    (BIT(10))
-#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
-#define APB_CTRL_CLK_320M_EN_V  0x1
-#define APB_CTRL_CLK_320M_EN_S  10
-/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
-/*description: .*/
-#define APB_CTRL_PRE_DIV_CNT    0x000003FF
-#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
-#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
-#define APB_CTRL_PRE_DIV_CNT_S  0
-
-#define APB_CTRL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x4)
-/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: .*/
-#define APB_CTRL_TICK_ENABLE    (BIT(16))
-#define APB_CTRL_TICK_ENABLE_M  (BIT(16))
-#define APB_CTRL_TICK_ENABLE_V  0x1
-#define APB_CTRL_TICK_ENABLE_S  16
-/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
-/*description: .*/
-#define APB_CTRL_CK8M_TICK_NUM    0x000000FF
-#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
-#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
-#define APB_CTRL_CK8M_TICK_NUM_S  8
-/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
-/*description: .*/
-#define APB_CTRL_XTAL_TICK_NUM    0x000000FF
-#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
-#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
-#define APB_CTRL_XTAL_TICK_NUM_S  0
-
-#define APB_CTRL_CLK_OUT_EN_REG          (DR_REG_APB_CTRL_BASE + 0x8)
-/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK_XTAL_OEN    (BIT(10))
-#define APB_CTRL_CLK_XTAL_OEN_M  (BIT(10))
-#define APB_CTRL_CLK_XTAL_OEN_V  0x1
-#define APB_CTRL_CLK_XTAL_OEN_S  10
-/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK40X_BB_OEN    (BIT(9))
-#define APB_CTRL_CLK40X_BB_OEN_M  (BIT(9))
-#define APB_CTRL_CLK40X_BB_OEN_V  0x1
-#define APB_CTRL_CLK40X_BB_OEN_S  9
-/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK_DAC_CPU_OEN    (BIT(8))
-#define APB_CTRL_CLK_DAC_CPU_OEN_M  (BIT(8))
-#define APB_CTRL_CLK_DAC_CPU_OEN_V  0x1
-#define APB_CTRL_CLK_DAC_CPU_OEN_S  8
-/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK_ADC_INF_OEN    (BIT(7))
-#define APB_CTRL_CLK_ADC_INF_OEN_M  (BIT(7))
-#define APB_CTRL_CLK_ADC_INF_OEN_V  0x1
-#define APB_CTRL_CLK_ADC_INF_OEN_S  7
-/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK_320M_OEN    (BIT(6))
-#define APB_CTRL_CLK_320M_OEN_M  (BIT(6))
-#define APB_CTRL_CLK_320M_OEN_V  0x1
-#define APB_CTRL_CLK_320M_OEN_S  6
-/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK160_OEN    (BIT(5))
-#define APB_CTRL_CLK160_OEN_M  (BIT(5))
-#define APB_CTRL_CLK160_OEN_V  0x1
-#define APB_CTRL_CLK160_OEN_S  5
-/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK80_OEN    (BIT(4))
-#define APB_CTRL_CLK80_OEN_M  (BIT(4))
-#define APB_CTRL_CLK80_OEN_V  0x1
-#define APB_CTRL_CLK80_OEN_S  4
-/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK_BB_OEN    (BIT(3))
-#define APB_CTRL_CLK_BB_OEN_M  (BIT(3))
-#define APB_CTRL_CLK_BB_OEN_V  0x1
-#define APB_CTRL_CLK_BB_OEN_S  3
-/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK44_OEN    (BIT(2))
-#define APB_CTRL_CLK44_OEN_M  (BIT(2))
-#define APB_CTRL_CLK44_OEN_V  0x1
-#define APB_CTRL_CLK44_OEN_S  2
-/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK22_OEN    (BIT(1))
-#define APB_CTRL_CLK22_OEN_M  (BIT(1))
-#define APB_CTRL_CLK22_OEN_V  0x1
-#define APB_CTRL_CLK22_OEN_S  1
-/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_CLK20_OEN    (BIT(0))
-#define APB_CTRL_CLK20_OEN_M  (BIT(0))
-#define APB_CTRL_CLK20_OEN_V  0x1
-#define APB_CTRL_CLK20_OEN_S  0
-
-#define APB_CTRL_WIFI_BB_CFG_REG          (DR_REG_APB_CTRL_BASE + 0xC)
-/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define APB_CTRL_WIFI_BB_CFG    0xFFFFFFFF
-#define APB_CTRL_WIFI_BB_CFG_M  ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
-#define APB_CTRL_WIFI_BB_CFG_V  0xFFFFFFFF
-#define APB_CTRL_WIFI_BB_CFG_S  0
-
-#define APB_CTRL_WIFI_BB_CFG_2_REG          (DR_REG_APB_CTRL_BASE + 0x10)
-/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define APB_CTRL_WIFI_BB_CFG_2    0xFFFFFFFF
-#define APB_CTRL_WIFI_BB_CFG_2_M  ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
-#define APB_CTRL_WIFI_BB_CFG_2_V  0xFFFFFFFF
-#define APB_CTRL_WIFI_BB_CFG_2_S  0
-
-#define APB_CTRL_WIFI_CLK_EN_REG          (DR_REG_APB_CTRL_BASE + 0x14)
-/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: .*/
-#define APB_CTRL_WIFI_CLK_EN    0xFFFFFFFF
-#define APB_CTRL_WIFI_CLK_EN_M  ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
-#define APB_CTRL_WIFI_CLK_EN_V  0xFFFFFFFF
-#define APB_CTRL_WIFI_CLK_EN_S  0
-
-#define APB_CTRL_WIFI_RST_EN_REG          (DR_REG_APB_CTRL_BASE + 0x18)
-/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define APB_CTRL_WIFI_RST    0xFFFFFFFF
-#define APB_CTRL_WIFI_RST_M  ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
-#define APB_CTRL_WIFI_RST_V  0xFFFFFFFF
-#define APB_CTRL_WIFI_RST_S  0
-
-#define APB_CTRL_HOST_INF_SEL_REG          (DR_REG_APB_CTRL_BASE + 0x1C)
-/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define APB_CTRL_PERI_IO_SWAP    0x000000FF
-#define APB_CTRL_PERI_IO_SWAP_M  ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
-#define APB_CTRL_PERI_IO_SWAP_V  0xFF
-#define APB_CTRL_PERI_IO_SWAP_S  0
-
-#define APB_CTRL_EXT_MEM_PMS_LOCK_REG          (DR_REG_APB_CTRL_BASE + 0x20)
-/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_EXT_MEM_PMS_LOCK    (BIT(0))
-#define APB_CTRL_EXT_MEM_PMS_LOCK_M  (BIT(0))
-#define APB_CTRL_EXT_MEM_PMS_LOCK_V  0x1
-#define APB_CTRL_EXT_MEM_PMS_LOCK_S  0
-
-#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG          (DR_REG_APB_CTRL_BASE + 0x24)
-/* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set 1 to bypass cache writeback request to external memory so that spi will not
-check its attribute..*/
-#define APB_CTRL_WRITEBACK_BYPASS    (BIT(0))
-#define APB_CTRL_WRITEBACK_BYPASS_M  (BIT(0))
-#define APB_CTRL_WRITEBACK_BYPASS_V  0x1
-#define APB_CTRL_WRITEBACK_BYPASS_S  0
-
-#define APB_CTRL_FLASH_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x28)
-/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE0_ATTR    0x000001FF
-#define APB_CTRL_FLASH_ACE0_ATTR_M  ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
-#define APB_CTRL_FLASH_ACE0_ATTR_V  0x1FF
-#define APB_CTRL_FLASH_ACE0_ATTR_S  0
-
-#define APB_CTRL_FLASH_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x2C)
-/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE1_ATTR    0x000001FF
-#define APB_CTRL_FLASH_ACE1_ATTR_M  ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
-#define APB_CTRL_FLASH_ACE1_ATTR_V  0x1FF
-#define APB_CTRL_FLASH_ACE1_ATTR_S  0
-
-#define APB_CTRL_FLASH_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x30)
-/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE2_ATTR    0x000001FF
-#define APB_CTRL_FLASH_ACE2_ATTR_M  ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
-#define APB_CTRL_FLASH_ACE2_ATTR_V  0x1FF
-#define APB_CTRL_FLASH_ACE2_ATTR_S  0
-
-#define APB_CTRL_FLASH_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x34)
-/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE3_ATTR    0x000001FF
-#define APB_CTRL_FLASH_ACE3_ATTR_M  ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
-#define APB_CTRL_FLASH_ACE3_ATTR_V  0x1FF
-#define APB_CTRL_FLASH_ACE3_ATTR_S  0
-
-#define APB_CTRL_FLASH_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x38)
-/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE0_ADDR_S    0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE0_ADDR_S_M  ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
-#define APB_CTRL_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE0_ADDR_S_S  0
-
-#define APB_CTRL_FLASH_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x3C)
-/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE1_ADDR_S    0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE1_ADDR_S_M  ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
-#define APB_CTRL_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE1_ADDR_S_S  0
-
-#define APB_CTRL_FLASH_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x40)
-/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE2_ADDR_S    0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE2_ADDR_S_M  ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
-#define APB_CTRL_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE2_ADDR_S_S  0
-
-#define APB_CTRL_FLASH_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x44)
-/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE3_ADDR_S    0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE3_ADDR_S_M  ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
-#define APB_CTRL_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_FLASH_ACE3_ADDR_S_S  0
-
-#define APB_CTRL_FLASH_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x48)
-/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE0_SIZE    0x0000FFFF
-#define APB_CTRL_FLASH_ACE0_SIZE_M  ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
-#define APB_CTRL_FLASH_ACE0_SIZE_V  0xFFFF
-#define APB_CTRL_FLASH_ACE0_SIZE_S  0
-
-#define APB_CTRL_FLASH_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x4C)
-/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE1_SIZE    0x0000FFFF
-#define APB_CTRL_FLASH_ACE1_SIZE_M  ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
-#define APB_CTRL_FLASH_ACE1_SIZE_V  0xFFFF
-#define APB_CTRL_FLASH_ACE1_SIZE_S  0
-
-#define APB_CTRL_FLASH_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x50)
-/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE2_SIZE    0x0000FFFF
-#define APB_CTRL_FLASH_ACE2_SIZE_M  ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
-#define APB_CTRL_FLASH_ACE2_SIZE_V  0xFFFF
-#define APB_CTRL_FLASH_ACE2_SIZE_S  0
-
-#define APB_CTRL_FLASH_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x54)
-/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define APB_CTRL_FLASH_ACE3_SIZE    0x0000FFFF
-#define APB_CTRL_FLASH_ACE3_SIZE_M  ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
-#define APB_CTRL_FLASH_ACE3_SIZE_V  0xFFFF
-#define APB_CTRL_FLASH_ACE3_SIZE_S  0
-
-#define APB_CTRL_SRAM_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x58)
-/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE0_ATTR    0x000001FF
-#define APB_CTRL_SRAM_ACE0_ATTR_M  ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S))
-#define APB_CTRL_SRAM_ACE0_ATTR_V  0x1FF
-#define APB_CTRL_SRAM_ACE0_ATTR_S  0
-
-#define APB_CTRL_SRAM_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x5C)
-/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE1_ATTR    0x000001FF
-#define APB_CTRL_SRAM_ACE1_ATTR_M  ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S))
-#define APB_CTRL_SRAM_ACE1_ATTR_V  0x1FF
-#define APB_CTRL_SRAM_ACE1_ATTR_S  0
-
-#define APB_CTRL_SRAM_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x60)
-/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE2_ATTR    0x000001FF
-#define APB_CTRL_SRAM_ACE2_ATTR_M  ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S))
-#define APB_CTRL_SRAM_ACE2_ATTR_V  0x1FF
-#define APB_CTRL_SRAM_ACE2_ATTR_S  0
-
-#define APB_CTRL_SRAM_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x64)
-/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE3_ATTR    0x000001FF
-#define APB_CTRL_SRAM_ACE3_ATTR_M  ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S))
-#define APB_CTRL_SRAM_ACE3_ATTR_V  0x1FF
-#define APB_CTRL_SRAM_ACE3_ATTR_S  0
-
-#define APB_CTRL_SRAM_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x68)
-/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE0_ADDR_S    0xFFFFFFFF
-#define APB_CTRL_SRAM_ACE0_ADDR_S_M  ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S))
-#define APB_CTRL_SRAM_ACE0_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_SRAM_ACE0_ADDR_S_S  0
-
-#define APB_CTRL_SRAM_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x6C)
-/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE1_ADDR_S    0xFFFFFFFF
-#define APB_CTRL_SRAM_ACE1_ADDR_S_M  ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S))
-#define APB_CTRL_SRAM_ACE1_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_SRAM_ACE1_ADDR_S_S  0
-
-#define APB_CTRL_SRAM_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x70)
-/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE2_ADDR_S    0xFFFFFFFF
-#define APB_CTRL_SRAM_ACE2_ADDR_S_M  ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S))
-#define APB_CTRL_SRAM_ACE2_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_SRAM_ACE2_ADDR_S_S  0
-
-#define APB_CTRL_SRAM_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x74)
-/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE3_ADDR_S    0xFFFFFFFF
-#define APB_CTRL_SRAM_ACE3_ADDR_S_M  ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S))
-#define APB_CTRL_SRAM_ACE3_ADDR_S_V  0xFFFFFFFF
-#define APB_CTRL_SRAM_ACE3_ADDR_S_S  0
-
-#define APB_CTRL_SRAM_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x78)
-/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE0_SIZE    0x0000FFFF
-#define APB_CTRL_SRAM_ACE0_SIZE_M  ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S))
-#define APB_CTRL_SRAM_ACE0_SIZE_V  0xFFFF
-#define APB_CTRL_SRAM_ACE0_SIZE_S  0
-
-#define APB_CTRL_SRAM_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x7C)
-/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE1_SIZE    0x0000FFFF
-#define APB_CTRL_SRAM_ACE1_SIZE_M  ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S))
-#define APB_CTRL_SRAM_ACE1_SIZE_V  0xFFFF
-#define APB_CTRL_SRAM_ACE1_SIZE_S  0
-
-#define APB_CTRL_SRAM_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x80)
-/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE2_SIZE    0x0000FFFF
-#define APB_CTRL_SRAM_ACE2_SIZE_M  ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S))
-#define APB_CTRL_SRAM_ACE2_SIZE_V  0xFFFF
-#define APB_CTRL_SRAM_ACE2_SIZE_S  0
-
-#define APB_CTRL_SRAM_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x84)
-/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_ACE3_SIZE    0x0000FFFF
-#define APB_CTRL_SRAM_ACE3_SIZE_M  ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S))
-#define APB_CTRL_SRAM_ACE3_SIZE_V  0xFFFF
-#define APB_CTRL_SRAM_ACE3_SIZE_S  0
-
-#define APB_CTRL_SPI_MEM_PMS_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x88)
-/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
-/*description: .*/
-#define APB_CTRL_SPI_MEM_REJECT_CDE    0x0000001F
-#define APB_CTRL_SPI_MEM_REJECT_CDE_M  ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
-#define APB_CTRL_SPI_MEM_REJECT_CDE_V  0x1F
-#define APB_CTRL_SPI_MEM_REJECT_CDE_S  2
-/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_SPI_MEM_REJECT_CLR    (BIT(1))
-#define APB_CTRL_SPI_MEM_REJECT_CLR_M  (BIT(1))
-#define APB_CTRL_SPI_MEM_REJECT_CLR_V  0x1
-#define APB_CTRL_SPI_MEM_REJECT_CLR_S  1
-/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_SPI_MEM_REJECT_INT    (BIT(0))
-#define APB_CTRL_SPI_MEM_REJECT_INT_M  (BIT(0))
-#define APB_CTRL_SPI_MEM_REJECT_INT_V  0x1
-#define APB_CTRL_SPI_MEM_REJECT_INT_S  0
-
-#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x8C)
-/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define APB_CTRL_SPI_MEM_REJECT_ADDR    0xFFFFFFFF
-#define APB_CTRL_SPI_MEM_REJECT_ADDR_M  ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
-#define APB_CTRL_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
-#define APB_CTRL_SPI_MEM_REJECT_ADDR_S  0
-
-#define APB_CTRL_SDIO_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x90)
-/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: .*/
-#define APB_CTRL_SDIO_WIN_ACCESS_EN    (BIT(0))
-#define APB_CTRL_SDIO_WIN_ACCESS_EN_M  (BIT(0))
-#define APB_CTRL_SDIO_WIN_ACCESS_EN_V  0x1
-#define APB_CTRL_SDIO_WIN_ACCESS_EN_S  0
-
-#define APB_CTRL_REDCY_SIG0_REG          (DR_REG_APB_CTRL_BASE + 0x94)
-/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define APB_CTRL_REDCY_ANDOR    (BIT(31))
-#define APB_CTRL_REDCY_ANDOR_M  (BIT(31))
-#define APB_CTRL_REDCY_ANDOR_V  0x1
-#define APB_CTRL_REDCY_ANDOR_S  31
-/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: .*/
-#define APB_CTRL_REDCY_SIG0    0x7FFFFFFF
-#define APB_CTRL_REDCY_SIG0_M  ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
-#define APB_CTRL_REDCY_SIG0_V  0x7FFFFFFF
-#define APB_CTRL_REDCY_SIG0_S  0
-
-#define APB_CTRL_REDCY_SIG1_REG          (DR_REG_APB_CTRL_BASE + 0x98)
-/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define APB_CTRL_REDCY_NANDOR    (BIT(31))
-#define APB_CTRL_REDCY_NANDOR_M  (BIT(31))
-#define APB_CTRL_REDCY_NANDOR_V  0x1
-#define APB_CTRL_REDCY_NANDOR_S  31
-/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: .*/
-#define APB_CTRL_REDCY_SIG1    0x7FFFFFFF
-#define APB_CTRL_REDCY_SIG1_M  ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
-#define APB_CTRL_REDCY_SIG1_V  0x7FFFFFFF
-#define APB_CTRL_REDCY_SIG1_S  0
-
-#define APB_CTRL_FRONT_END_MEM_PD_REG          (DR_REG_APB_CTRL_BASE + 0x9C)
-/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_FREQ_MEM_FORCE_PD    (BIT(7))
-#define APB_CTRL_FREQ_MEM_FORCE_PD_M  (BIT(7))
-#define APB_CTRL_FREQ_MEM_FORCE_PD_V  0x1
-#define APB_CTRL_FREQ_MEM_FORCE_PD_S  7
-/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_FREQ_MEM_FORCE_PU    (BIT(6))
-#define APB_CTRL_FREQ_MEM_FORCE_PU_M  (BIT(6))
-#define APB_CTRL_FREQ_MEM_FORCE_PU_V  0x1
-#define APB_CTRL_FREQ_MEM_FORCE_PU_S  6
-/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_DC_MEM_FORCE_PD    (BIT(5))
-#define APB_CTRL_DC_MEM_FORCE_PD_M  (BIT(5))
-#define APB_CTRL_DC_MEM_FORCE_PD_V  0x1
-#define APB_CTRL_DC_MEM_FORCE_PD_S  5
-/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_DC_MEM_FORCE_PU    (BIT(4))
-#define APB_CTRL_DC_MEM_FORCE_PU_M  (BIT(4))
-#define APB_CTRL_DC_MEM_FORCE_PU_V  0x1
-#define APB_CTRL_DC_MEM_FORCE_PU_S  4
-/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_PBUS_MEM_FORCE_PD    (BIT(3))
-#define APB_CTRL_PBUS_MEM_FORCE_PD_M  (BIT(3))
-#define APB_CTRL_PBUS_MEM_FORCE_PD_V  0x1
-#define APB_CTRL_PBUS_MEM_FORCE_PD_S  3
-/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_PBUS_MEM_FORCE_PU    (BIT(2))
-#define APB_CTRL_PBUS_MEM_FORCE_PU_M  (BIT(2))
-#define APB_CTRL_PBUS_MEM_FORCE_PU_V  0x1
-#define APB_CTRL_PBUS_MEM_FORCE_PU_S  2
-/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_AGC_MEM_FORCE_PD    (BIT(1))
-#define APB_CTRL_AGC_MEM_FORCE_PD_M  (BIT(1))
-#define APB_CTRL_AGC_MEM_FORCE_PD_V  0x1
-#define APB_CTRL_AGC_MEM_FORCE_PD_S  1
-/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_CTRL_AGC_MEM_FORCE_PU    (BIT(0))
-#define APB_CTRL_AGC_MEM_FORCE_PU_M  (BIT(0))
-#define APB_CTRL_AGC_MEM_FORCE_PU_V  0x1
-#define APB_CTRL_AGC_MEM_FORCE_PU_S  0
-
-#define APB_CTRL_SPI_MEM_ECC_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0xA0)
-/* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
-/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2:
-1024 bytes. 3: 2048 bytes..*/
-#define APB_CTRL_SRAM_PAGE_SIZE    0x00000003
-#define APB_CTRL_SRAM_PAGE_SIZE_M  ((APB_CTRL_SRAM_PAGE_SIZE_V)<<(APB_CTRL_SRAM_PAGE_SIZE_S))
-#define APB_CTRL_SRAM_PAGE_SIZE_V  0x3
-#define APB_CTRL_SRAM_PAGE_SIZE_S  20
-/* APB_CTRL_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by
-tes. 3: 2048 bytes..*/
-#define APB_CTRL_FLASH_PAGE_SIZE    0x00000003
-#define APB_CTRL_FLASH_PAGE_SIZE_M  ((APB_CTRL_FLASH_PAGE_SIZE_V)<<(APB_CTRL_FLASH_PAGE_SIZE_S))
-#define APB_CTRL_FLASH_PAGE_SIZE_V  0x3
-#define APB_CTRL_FLASH_PAGE_SIZE_S  18
-
-#define APB_CTRL_CLKGATE_FORCE_ON_REG          (DR_REG_APB_CTRL_BASE + 0xA8)
-/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_CLKGATE_FORCE_ON    0x000007FF
-#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M  ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
-#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V  0x7FF
-#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S  3
-/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define APB_CTRL_ROM_CLKGATE_FORCE_ON    0x00000007
-#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M  ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
-#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V  0x7
-#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S  0
-
-#define APB_CTRL_MEM_POWER_DOWN_REG          (DR_REG_APB_CTRL_BASE + 0xAC)
-/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_POWER_DOWN    0x000007FF
-#define APB_CTRL_SRAM_POWER_DOWN_M  ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
-#define APB_CTRL_SRAM_POWER_DOWN_V  0x7FF
-#define APB_CTRL_SRAM_POWER_DOWN_S  3
-/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: .*/
-#define APB_CTRL_ROM_POWER_DOWN    0x00000007
-#define APB_CTRL_ROM_POWER_DOWN_M  ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
-#define APB_CTRL_ROM_POWER_DOWN_V  0x7
-#define APB_CTRL_ROM_POWER_DOWN_S  0
-
-#define APB_CTRL_MEM_POWER_UP_REG          (DR_REG_APB_CTRL_BASE + 0xB0)
-/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
-/*description: .*/
-#define APB_CTRL_SRAM_POWER_UP    0x000007FF
-#define APB_CTRL_SRAM_POWER_UP_M  ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
-#define APB_CTRL_SRAM_POWER_UP_V  0x7FF
-#define APB_CTRL_SRAM_POWER_UP_S  3
-/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define APB_CTRL_ROM_POWER_UP    0x00000007
-#define APB_CTRL_ROM_POWER_UP_M  ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
-#define APB_CTRL_ROM_POWER_UP_V  0x7
-#define APB_CTRL_ROM_POWER_UP_S  0
-
-#define APB_CTRL_RETENTION_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0xB4)
-/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_NOBYPASS_CPU_ISO_RST    (BIT(27))
-#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
-#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V  0x1
-#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S  27
-/* APB_CTRL_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
-/*description: .*/
-#define APB_CTRL_RETENTION_CPU_LINK_ADDR    0x07FFFFFF
-#define APB_CTRL_RETENTION_CPU_LINK_ADDR_M  ((APB_CTRL_RETENTION_CPU_LINK_ADDR_V)<<(APB_CTRL_RETENTION_CPU_LINK_ADDR_S))
-#define APB_CTRL_RETENTION_CPU_LINK_ADDR_V  0x7FFFFFF
-#define APB_CTRL_RETENTION_CPU_LINK_ADDR_S  0
-
-#define APB_CTRL_RETENTION_CTRL1_REG          (DR_REG_APB_CTRL_BASE + 0xB8)
-/* APB_CTRL_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
-/*description: .*/
-#define APB_CTRL_RETENTION_TAG_LINK_ADDR    0x07FFFFFF
-#define APB_CTRL_RETENTION_TAG_LINK_ADDR_M  ((APB_CTRL_RETENTION_TAG_LINK_ADDR_V)<<(APB_CTRL_RETENTION_TAG_LINK_ADDR_S))
-#define APB_CTRL_RETENTION_TAG_LINK_ADDR_V  0x7FFFFFF
-#define APB_CTRL_RETENTION_TAG_LINK_ADDR_S  0
-
-#define APB_CTRL_RETENTION_CTRL2_REG          (DR_REG_APB_CTRL_BASE + 0xBC)
-/* APB_CTRL_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_RET_ICACHE_ENABLE    (BIT(31))
-#define APB_CTRL_RET_ICACHE_ENABLE_M  (BIT(31))
-#define APB_CTRL_RET_ICACHE_ENABLE_V  0x1
-#define APB_CTRL_RET_ICACHE_ENABLE_S  31
-/* APB_CTRL_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
-/*description: .*/
-#define APB_CTRL_RET_ICACHE_START_POINT    0x000000FF
-#define APB_CTRL_RET_ICACHE_START_POINT_M  ((APB_CTRL_RET_ICACHE_START_POINT_V)<<(APB_CTRL_RET_ICACHE_START_POINT_S))
-#define APB_CTRL_RET_ICACHE_START_POINT_V  0xFF
-#define APB_CTRL_RET_ICACHE_START_POINT_S  22
-/* APB_CTRL_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
-/*description: .*/
-#define APB_CTRL_RET_ICACHE_VLD_SIZE    0x000000FF
-#define APB_CTRL_RET_ICACHE_VLD_SIZE_M  ((APB_CTRL_RET_ICACHE_VLD_SIZE_V)<<(APB_CTRL_RET_ICACHE_VLD_SIZE_S))
-#define APB_CTRL_RET_ICACHE_VLD_SIZE_V  0xFF
-#define APB_CTRL_RET_ICACHE_VLD_SIZE_S  13
-/* APB_CTRL_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
-/*description: .*/
-#define APB_CTRL_RET_ICACHE_SIZE    0x000000FF
-#define APB_CTRL_RET_ICACHE_SIZE_M  ((APB_CTRL_RET_ICACHE_SIZE_V)<<(APB_CTRL_RET_ICACHE_SIZE_S))
-#define APB_CTRL_RET_ICACHE_SIZE_V  0xFF
-#define APB_CTRL_RET_ICACHE_SIZE_S  4
-
-#define APB_CTRL_RETENTION_CTRL3_REG          (DR_REG_APB_CTRL_BASE + 0xC0)
-/* APB_CTRL_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_RET_DCACHE_ENABLE    (BIT(31))
-#define APB_CTRL_RET_DCACHE_ENABLE_M  (BIT(31))
-#define APB_CTRL_RET_DCACHE_ENABLE_V  0x1
-#define APB_CTRL_RET_DCACHE_ENABLE_S  31
-/* APB_CTRL_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
-/*description: .*/
-#define APB_CTRL_RET_DCACHE_START_POINT    0x000001FF
-#define APB_CTRL_RET_DCACHE_START_POINT_M  ((APB_CTRL_RET_DCACHE_START_POINT_V)<<(APB_CTRL_RET_DCACHE_START_POINT_S))
-#define APB_CTRL_RET_DCACHE_START_POINT_V  0x1FF
-#define APB_CTRL_RET_DCACHE_START_POINT_S  22
-/* APB_CTRL_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
-/*description: .*/
-#define APB_CTRL_RET_DCACHE_VLD_SIZE    0x000001FF
-#define APB_CTRL_RET_DCACHE_VLD_SIZE_M  ((APB_CTRL_RET_DCACHE_VLD_SIZE_V)<<(APB_CTRL_RET_DCACHE_VLD_SIZE_S))
-#define APB_CTRL_RET_DCACHE_VLD_SIZE_V  0x1FF
-#define APB_CTRL_RET_DCACHE_VLD_SIZE_S  13
-/* APB_CTRL_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
-/*description: .*/
-#define APB_CTRL_RET_DCACHE_SIZE    0x000001FF
-#define APB_CTRL_RET_DCACHE_SIZE_M  ((APB_CTRL_RET_DCACHE_SIZE_V)<<(APB_CTRL_RET_DCACHE_SIZE_S))
-#define APB_CTRL_RET_DCACHE_SIZE_V  0x1FF
-#define APB_CTRL_RET_DCACHE_SIZE_S  4
-
-#define APB_CTRL_RETENTION_CTRL4_REG          (DR_REG_APB_CTRL_BASE + 0xC4)
-/* APB_CTRL_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */
-/*description: .*/
-#define APB_CTRL_RETENTION_INV_CFG    0xFFFFFFFF
-#define APB_CTRL_RETENTION_INV_CFG_M  ((APB_CTRL_RETENTION_INV_CFG_V)<<(APB_CTRL_RETENTION_INV_CFG_S))
-#define APB_CTRL_RETENTION_INV_CFG_V  0xFFFFFFFF
-#define APB_CTRL_RETENTION_INV_CFG_S  0
-
-#define APB_CTRL_RETENTION_CTRL5_REG          (DR_REG_APB_CTRL_BASE + 0xC8)
-/* APB_CTRL_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_CTRL_RETENTION_DISABLE    (BIT(0))
-#define APB_CTRL_RETENTION_DISABLE_M  (BIT(0))
-#define APB_CTRL_RETENTION_DISABLE_V  0x1
-#define APB_CTRL_RETENTION_DISABLE_S  0
-
-#define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x3FC)
-/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
-/*description: Version control.*/
-#define APB_CTRL_DATE    0xFFFFFFFF
-#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
-#define APB_CTRL_DATE_V  0xFFFFFFFF
-#define APB_CTRL_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_APB_CTRL_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/apb_saradc_reg.h b/components/soc/esp32s3/include/soc/apb_saradc_reg.h
deleted file mode 100644
index b9c88f22547..00000000000
--- a/components/soc/esp32s3/include/soc/apb_saradc_reg.h
+++ /dev/null
@@ -1,646 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_APB_SARADC_REG_H_
-#define _SOC_APB_SARADC_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x0)
-/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
-/*description: wait arbit signal stable after sar_done.*/
-#define APB_SARADC_WAIT_ARB_CYCLE    0x00000003
-#define APB_SARADC_WAIT_ARB_CYCLE_M  ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
-#define APB_SARADC_WAIT_ARB_CYCLE_V  0x3
-#define APB_SARADC_WAIT_ARB_CYCLE_S  30
-/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
-/*description: force option to xpd sar blocks.*/
-#define APB_SARADC_XPD_SAR_FORCE    0x00000003
-#define APB_SARADC_XPD_SAR_FORCE_M  ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
-#define APB_SARADC_XPD_SAR_FORCE_V  0x3
-#define APB_SARADC_XPD_SAR_FORCE_S  27
-/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matr
-ix.*/
-#define APB_SARADC_DATA_TO_I2S    (BIT(26))
-#define APB_SARADC_DATA_TO_I2S_M  (BIT(26))
-#define APB_SARADC_DATA_TO_I2S_V  0x1
-#define APB_SARADC_DATA_TO_I2S_S  26
-/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
-resolution should not be larger than 11 bits..*/
-#define APB_SARADC_DATA_SAR_SEL    (BIT(25))
-#define APB_SARADC_DATA_SAR_SEL_M  (BIT(25))
-#define APB_SARADC_DATA_SAR_SEL_V  0x1
-#define APB_SARADC_DATA_SAR_SEL_S  25
-/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: clear the pointer of pattern table for DIG ADC2 CTRL.*/
-#define APB_SARADC_SAR2_PATT_P_CLEAR    (BIT(24))
-#define APB_SARADC_SAR2_PATT_P_CLEAR_M  (BIT(24))
-#define APB_SARADC_SAR2_PATT_P_CLEAR_V  0x1
-#define APB_SARADC_SAR2_PATT_P_CLEAR_S  24
-/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: clear the pointer of pattern table for DIG ADC1 CTRL.*/
-#define APB_SARADC_SAR1_PATT_P_CLEAR    (BIT(23))
-#define APB_SARADC_SAR1_PATT_P_CLEAR_M  (BIT(23))
-#define APB_SARADC_SAR1_PATT_P_CLEAR_V  0x1
-#define APB_SARADC_SAR1_PATT_P_CLEAR_S  23
-/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
-/*description:  0 ~ 15 means length 1 ~ 16.*/
-#define APB_SARADC_SAR2_PATT_LEN    0x0000000F
-#define APB_SARADC_SAR2_PATT_LEN_M  ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S))
-#define APB_SARADC_SAR2_PATT_LEN_V  0xF
-#define APB_SARADC_SAR2_PATT_LEN_S  19
-/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
-/*description:  0 ~ 15 means length 1 ~ 16.*/
-#define APB_SARADC_SAR1_PATT_LEN    0x0000000F
-#define APB_SARADC_SAR1_PATT_LEN_M  ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S))
-#define APB_SARADC_SAR1_PATT_LEN_V  0xF
-#define APB_SARADC_SAR1_PATT_LEN_S  15
-/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
-/*description: SAR clock divider.*/
-#define APB_SARADC_SAR_CLK_DIV    0x000000FF
-#define APB_SARADC_SAR_CLK_DIV_M  ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
-#define APB_SARADC_SAR_CLK_DIV_V  0xFF
-#define APB_SARADC_SAR_CLK_DIV_S  7
-/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define APB_SARADC_SAR_CLK_GATED    (BIT(6))
-#define APB_SARADC_SAR_CLK_GATED_M  (BIT(6))
-#define APB_SARADC_SAR_CLK_GATED_V  0x1
-#define APB_SARADC_SAR_CLK_GATED_S  6
-/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description:  0: SAR1, 1: SAR2, only work for single SAR mode.*/
-#define APB_SARADC_SAR_SEL    (BIT(5))
-#define APB_SARADC_SAR_SEL_M  (BIT(5))
-#define APB_SARADC_SAR_SEL_V  0x1
-#define APB_SARADC_SAR_SEL_S  5
-/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
-/*description:  0: single mode, 1: double mode, 2: alternate mode.*/
-#define APB_SARADC_WORK_MODE    0x00000003
-#define APB_SARADC_WORK_MODE_M  ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S))
-#define APB_SARADC_WORK_MODE_V  0x3
-#define APB_SARADC_WORK_MODE_S  3
-/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
-/*description: .*/
-#define APB_SARADC_START    (BIT(1))
-#define APB_SARADC_START_M  (BIT(1))
-#define APB_SARADC_START_V  0x1
-#define APB_SARADC_START_S  1
-/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: .*/
-#define APB_SARADC_START_FORCE    (BIT(0))
-#define APB_SARADC_START_FORCE_M  (BIT(0))
-#define APB_SARADC_START_FORCE_V  0x1
-#define APB_SARADC_START_FORCE_S  0
-
-#define APB_SARADC_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x4)
-/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: to enable saradc timer trigger.*/
-#define APB_SARADC_TIMER_EN    (BIT(24))
-#define APB_SARADC_TIMER_EN_M  (BIT(24))
-#define APB_SARADC_TIMER_EN_V  0x1
-#define APB_SARADC_TIMER_EN_S  24
-/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
-/*description: to set saradc timer target.*/
-#define APB_SARADC_TIMER_TARGET    0x00000FFF
-#define APB_SARADC_TIMER_TARGET_M  ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
-#define APB_SARADC_TIMER_TARGET_V  0xFFF
-#define APB_SARADC_TIMER_TARGET_S  12
-/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: 1: select saradc timer 0: i2s_ws trigger.*/
-#define APB_SARADC_TIMER_SEL    (BIT(11))
-#define APB_SARADC_TIMER_SEL_M  (BIT(11))
-#define APB_SARADC_TIMER_SEL_V  0x1
-#define APB_SARADC_TIMER_SEL_S  11
-/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/
-#define APB_SARADC_SAR2_INV    (BIT(10))
-#define APB_SARADC_SAR2_INV_M  (BIT(10))
-#define APB_SARADC_SAR2_INV_V  0x1
-#define APB_SARADC_SAR2_INV_S  10
-/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: 1: data to DIG ADC1 CTRL is inverted, otherwise not.*/
-#define APB_SARADC_SAR1_INV    (BIT(9))
-#define APB_SARADC_SAR1_INV_M  (BIT(9))
-#define APB_SARADC_SAR1_INV_V  0x1
-#define APB_SARADC_SAR1_INV_S  9
-/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
-/*description: max conversion number.*/
-#define APB_SARADC_MAX_MEAS_NUM    0x000000FF
-#define APB_SARADC_MAX_MEAS_NUM_M  ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
-#define APB_SARADC_MAX_MEAS_NUM_V  0xFF
-#define APB_SARADC_MAX_MEAS_NUM_S  1
-/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: .*/
-#define APB_SARADC_MEAS_NUM_LIMIT    (BIT(0))
-#define APB_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
-#define APB_SARADC_MEAS_NUM_LIMIT_V  0x1
-#define APB_SARADC_MEAS_NUM_LIMIT_S  0
-
-#define APB_SARADC_FILTER_CTRL1_REG          (DR_REG_APB_SARADC_BASE + 0x8)
-/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
-/*description: .*/
-#define APB_SARADC_FILTER_FACTOR0    0x00000007
-#define APB_SARADC_FILTER_FACTOR0_M  ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
-#define APB_SARADC_FILTER_FACTOR0_V  0x7
-#define APB_SARADC_FILTER_FACTOR0_S  29
-/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
-/*description: .*/
-#define APB_SARADC_FILTER_FACTOR1    0x00000007
-#define APB_SARADC_FILTER_FACTOR1_M  ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
-#define APB_SARADC_FILTER_FACTOR1_V  0x7
-#define APB_SARADC_FILTER_FACTOR1_S  26
-
-#define APB_SARADC_FSM_WAIT_REG          (DR_REG_APB_SARADC_BASE + 0xC)
-/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
-/*description: .*/
-#define APB_SARADC_STANDBY_WAIT    0x000000FF
-#define APB_SARADC_STANDBY_WAIT_M  ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
-#define APB_SARADC_STANDBY_WAIT_V  0xFF
-#define APB_SARADC_STANDBY_WAIT_S  16
-/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
-/*description: .*/
-#define APB_SARADC_RSTB_WAIT    0x000000FF
-#define APB_SARADC_RSTB_WAIT_M  ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
-#define APB_SARADC_RSTB_WAIT_V  0xFF
-#define APB_SARADC_RSTB_WAIT_S  8
-/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
-/*description: .*/
-#define APB_SARADC_XPD_WAIT    0x000000FF
-#define APB_SARADC_XPD_WAIT_M  ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
-#define APB_SARADC_XPD_WAIT_V  0xFF
-#define APB_SARADC_XPD_WAIT_S  0
-
-#define APB_SARADC_SAR1_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x10)
-/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: .*/
-#define APB_SARADC_SAR1_STATUS    0xFFFFFFFF
-#define APB_SARADC_SAR1_STATUS_M  ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
-#define APB_SARADC_SAR1_STATUS_V  0xFFFFFFFF
-#define APB_SARADC_SAR1_STATUS_S  0
-
-#define APB_SARADC_SAR2_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x14)
-/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: .*/
-#define APB_SARADC_SAR2_STATUS    0xFFFFFFFF
-#define APB_SARADC_SAR2_STATUS_M  ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
-#define APB_SARADC_SAR2_STATUS_V  0xFFFFFFFF
-#define APB_SARADC_SAR2_STATUS_S  0
-
-#define APB_SARADC_SAR1_PATT_TAB1_REG          (DR_REG_APB_SARADC_BASE + 0x18)
-/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: item 0 ~ 3 for pattern table 1 (each item one byte).*/
-#define APB_SARADC_SAR1_PATT_TAB1    0x00FFFFFF
-#define APB_SARADC_SAR1_PATT_TAB1_M  ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S))
-#define APB_SARADC_SAR1_PATT_TAB1_V  0xFFFFFF
-#define APB_SARADC_SAR1_PATT_TAB1_S  0
-
-#define APB_SARADC_SAR1_PATT_TAB2_REG          (DR_REG_APB_SARADC_BASE + 0x1C)
-/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Item 4 ~ 7 for pattern table 1 (each item one byte).*/
-#define APB_SARADC_SAR1_PATT_TAB2    0x00FFFFFF
-#define APB_SARADC_SAR1_PATT_TAB2_M  ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S))
-#define APB_SARADC_SAR1_PATT_TAB2_V  0xFFFFFF
-#define APB_SARADC_SAR1_PATT_TAB2_S  0
-
-#define APB_SARADC_SAR1_PATT_TAB3_REG          (DR_REG_APB_SARADC_BASE + 0x20)
-/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Item 8 ~ 11 for pattern table 1 (each item one byte).*/
-#define APB_SARADC_SAR1_PATT_TAB3    0x00FFFFFF
-#define APB_SARADC_SAR1_PATT_TAB3_M  ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S))
-#define APB_SARADC_SAR1_PATT_TAB3_V  0xFFFFFF
-#define APB_SARADC_SAR1_PATT_TAB3_S  0
-
-#define APB_SARADC_SAR1_PATT_TAB4_REG          (DR_REG_APB_SARADC_BASE + 0x24)
-/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Item 12 ~ 15 for pattern table 1 (each item one byte).*/
-#define APB_SARADC_SAR1_PATT_TAB4    0x00FFFFFF
-#define APB_SARADC_SAR1_PATT_TAB4_M  ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S))
-#define APB_SARADC_SAR1_PATT_TAB4_V  0xFFFFFF
-#define APB_SARADC_SAR1_PATT_TAB4_S  0
-
-#define APB_SARADC_SAR2_PATT_TAB1_REG          (DR_REG_APB_SARADC_BASE + 0x28)
-/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: item 0 ~ 3 for pattern table 2 (each item one byte).*/
-#define APB_SARADC_SAR2_PATT_TAB1    0x00FFFFFF
-#define APB_SARADC_SAR2_PATT_TAB1_M  ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S))
-#define APB_SARADC_SAR2_PATT_TAB1_V  0xFFFFFF
-#define APB_SARADC_SAR2_PATT_TAB1_S  0
-
-#define APB_SARADC_SAR2_PATT_TAB2_REG          (DR_REG_APB_SARADC_BASE + 0x2C)
-/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Item 4 ~ 7 for pattern table 2 (each item one byte).*/
-#define APB_SARADC_SAR2_PATT_TAB2    0x00FFFFFF
-#define APB_SARADC_SAR2_PATT_TAB2_M  ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S))
-#define APB_SARADC_SAR2_PATT_TAB2_V  0xFFFFFF
-#define APB_SARADC_SAR2_PATT_TAB2_S  0
-
-#define APB_SARADC_SAR2_PATT_TAB3_REG          (DR_REG_APB_SARADC_BASE + 0x30)
-/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Item 8 ~ 11 for pattern table 2 (each item one byte).*/
-#define APB_SARADC_SAR2_PATT_TAB3    0x00FFFFFF
-#define APB_SARADC_SAR2_PATT_TAB3_M  ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S))
-#define APB_SARADC_SAR2_PATT_TAB3_V  0xFFFFFF
-#define APB_SARADC_SAR2_PATT_TAB3_S  0
-
-#define APB_SARADC_SAR2_PATT_TAB4_REG          (DR_REG_APB_SARADC_BASE + 0x34)
-/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: Item 12 ~ 15 for pattern table 2 (each item one byte).*/
-#define APB_SARADC_SAR2_PATT_TAB4    0x00FFFFFF
-#define APB_SARADC_SAR2_PATT_TAB4_M  ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S))
-#define APB_SARADC_SAR2_PATT_TAB4_V  0xFFFFFF
-#define APB_SARADC_SAR2_PATT_TAB4_S  0
-
-#define APB_SARADC_APB_ADC_ARB_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x38)
-/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: adc2 arbiter uses fixed priority.*/
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY    (BIT(12))
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (BIT(12))
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x1
-#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
-/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
-/*description: Set adc2 arbiter wifi priority.*/
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY    0x00000003
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x3
-#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
-/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
-/*description: Set adc2 arbiter rtc priority.*/
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY    0x00000003
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x3
-#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
-/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
-/*description: Set adc2 arbiterapb priority.*/
-#define APB_SARADC_ADC_ARB_APB_PRIORITY    0x00000003
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x3
-#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
-/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: adc2 arbiter force grant.*/
-#define APB_SARADC_ADC_ARB_GRANT_FORCE    (BIT(5))
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (BIT(5))
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x1
-#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
-/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: adc2 arbiter force to enable wifi controller.*/
-#define APB_SARADC_ADC_ARB_WIFI_FORCE    (BIT(4))
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (BIT(4))
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x1
-#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
-/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: adc2 arbiter force to enable rtc controller.*/
-#define APB_SARADC_ADC_ARB_RTC_FORCE    (BIT(3))
-#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (BIT(3))
-#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x1
-#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
-/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: adc2 arbiter force to enableapb controller.*/
-#define APB_SARADC_ADC_ARB_APB_FORCE    (BIT(2))
-#define APB_SARADC_ADC_ARB_APB_FORCE_M  (BIT(2))
-#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x1
-#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
-
-#define APB_SARADC_FILTER_CTRL0_REG          (DR_REG_APB_SARADC_BASE + 0x3C)
-/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: enable apb_adc1_filter.*/
-#define APB_SARADC_FILTER_RESET    (BIT(31))
-#define APB_SARADC_FILTER_RESET_M  (BIT(31))
-#define APB_SARADC_FILTER_RESET_V  0x1
-#define APB_SARADC_FILTER_RESET_S  31
-/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[23:19] ;default: 5'hd ; */
-/*description: apb_adc1_filter_factor.*/
-#define APB_SARADC_FILTER_CHANNEL0    0x0000001F
-#define APB_SARADC_FILTER_CHANNEL0_M  ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
-#define APB_SARADC_FILTER_CHANNEL0_V  0x1F
-#define APB_SARADC_FILTER_CHANNEL0_S  19
-/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[18:14] ;default: 5'hd ; */
-/*description: .*/
-#define APB_SARADC_FILTER_CHANNEL1    0x0000001F
-#define APB_SARADC_FILTER_CHANNEL1_M  ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
-#define APB_SARADC_FILTER_CHANNEL1_V  0x1F
-#define APB_SARADC_FILTER_CHANNEL1_S  14
-
-#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x40)
-/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
-/*description: .*/
-#define APB_SARADC_ADC1_DATA    0x0001FFFF
-#define APB_SARADC_ADC1_DATA_M  ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
-#define APB_SARADC_ADC1_DATA_V  0x1FFFF
-#define APB_SARADC_ADC1_DATA_S  0
-
-#define APB_SARADC_THRES0_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x44)
-/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
-/*description: saradc1's thres0 monitor thres.*/
-#define APB_SARADC_THRES0_LOW    0x00001FFF
-#define APB_SARADC_THRES0_LOW_M  ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
-#define APB_SARADC_THRES0_LOW_V  0x1FFF
-#define APB_SARADC_THRES0_LOW_S  18
-/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
-/*description: saradc1's thres0 monitor thres.*/
-#define APB_SARADC_THRES0_HIGH    0x00001FFF
-#define APB_SARADC_THRES0_HIGH_M  ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
-#define APB_SARADC_THRES0_HIGH_V  0x1FFF
-#define APB_SARADC_THRES0_HIGH_S  5
-/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_CHANNEL    0x0000001F
-#define APB_SARADC_THRES0_CHANNEL_M  ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
-#define APB_SARADC_THRES0_CHANNEL_V  0x1F
-#define APB_SARADC_THRES0_CHANNEL_S  0
-
-#define APB_SARADC_THRES1_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x48)
-/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
-/*description: saradc1's thres0 monitor thres.*/
-#define APB_SARADC_THRES1_LOW    0x00001FFF
-#define APB_SARADC_THRES1_LOW_M  ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
-#define APB_SARADC_THRES1_LOW_V  0x1FFF
-#define APB_SARADC_THRES1_LOW_S  18
-/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
-/*description: saradc1's thres0 monitor thres.*/
-#define APB_SARADC_THRES1_HIGH    0x00001FFF
-#define APB_SARADC_THRES1_HIGH_M  ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
-#define APB_SARADC_THRES1_HIGH_V  0x1FFF
-#define APB_SARADC_THRES1_HIGH_S  5
-/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_CHANNEL    0x0000001F
-#define APB_SARADC_THRES1_CHANNEL_M  ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
-#define APB_SARADC_THRES1_CHANNEL_V  0x1F
-#define APB_SARADC_THRES1_CHANNEL_S  0
-
-#define APB_SARADC_THRES_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x58)
-/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_EN    (BIT(31))
-#define APB_SARADC_THRES0_EN_M  (BIT(31))
-#define APB_SARADC_THRES0_EN_V  0x1
-#define APB_SARADC_THRES0_EN_S  31
-/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_EN    (BIT(30))
-#define APB_SARADC_THRES1_EN_M  (BIT(30))
-#define APB_SARADC_THRES1_EN_V  0x1
-#define APB_SARADC_THRES1_EN_S  30
-/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES2_EN    (BIT(29))
-#define APB_SARADC_THRES2_EN_M  (BIT(29))
-#define APB_SARADC_THRES2_EN_V  0x1
-#define APB_SARADC_THRES2_EN_S  29
-/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES3_EN    (BIT(28))
-#define APB_SARADC_THRES3_EN_M  (BIT(28))
-#define APB_SARADC_THRES3_EN_V  0x1
-#define APB_SARADC_THRES3_EN_S  28
-/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: .*/
-#define APB_SARADC_THRES_ALL_EN    (BIT(27))
-#define APB_SARADC_THRES_ALL_EN_M  (BIT(27))
-#define APB_SARADC_THRES_ALL_EN_V  0x1
-#define APB_SARADC_THRES_ALL_EN_S  27
-
-#define APB_SARADC_INT_ENA_REG          (DR_REG_APB_SARADC_BASE + 0x5C)
-/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_ADC1_DONE_INT_ENA    (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_ENA_M  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_ENA_V  0x1
-#define APB_SARADC_ADC1_DONE_INT_ENA_S  31
-/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_ADC2_DONE_INT_ENA    (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_ENA_M  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_ENA_V  0x1
-#define APB_SARADC_ADC2_DONE_INT_ENA_S  30
-/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_HIGH_INT_ENA    (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_ENA_M  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_ENA_V  0x1
-#define APB_SARADC_THRES0_HIGH_INT_ENA_S  29
-/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_HIGH_INT_ENA    (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_ENA_M  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_ENA_V  0x1
-#define APB_SARADC_THRES1_HIGH_INT_ENA_S  28
-/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_LOW_INT_ENA    (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_ENA_M  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_ENA_V  0x1
-#define APB_SARADC_THRES0_LOW_INT_ENA_S  27
-/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_LOW_INT_ENA    (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_ENA_M  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_ENA_V  0x1
-#define APB_SARADC_THRES1_LOW_INT_ENA_S  26
-
-#define APB_SARADC_INT_RAW_REG          (DR_REG_APB_SARADC_BASE + 0x60)
-/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_ADC1_DONE_INT_RAW    (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_RAW_M  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_RAW_V  0x1
-#define APB_SARADC_ADC1_DONE_INT_RAW_S  31
-/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_ADC2_DONE_INT_RAW    (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_RAW_M  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_RAW_V  0x1
-#define APB_SARADC_ADC2_DONE_INT_RAW_S  30
-/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_HIGH_INT_RAW    (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_RAW_M  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_RAW_V  0x1
-#define APB_SARADC_THRES0_HIGH_INT_RAW_S  29
-/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_HIGH_INT_RAW    (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_RAW_M  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_RAW_V  0x1
-#define APB_SARADC_THRES1_HIGH_INT_RAW_S  28
-/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_LOW_INT_RAW    (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_RAW_M  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_RAW_V  0x1
-#define APB_SARADC_THRES0_LOW_INT_RAW_S  27
-/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_LOW_INT_RAW    (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_RAW_M  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_RAW_V  0x1
-#define APB_SARADC_THRES1_LOW_INT_RAW_S  26
-
-#define APB_SARADC_INT_ST_REG          (DR_REG_APB_SARADC_BASE + 0x64)
-/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_ADC1_DONE_INT_ST    (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_ST_M  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_ST_V  0x1
-#define APB_SARADC_ADC1_DONE_INT_ST_S  31
-/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_ADC2_DONE_INT_ST    (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_ST_M  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_ST_V  0x1
-#define APB_SARADC_ADC2_DONE_INT_ST_S  30
-/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_HIGH_INT_ST    (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_ST_M  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_ST_V  0x1
-#define APB_SARADC_THRES0_HIGH_INT_ST_S  29
-/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_HIGH_INT_ST    (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_ST_M  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_ST_V  0x1
-#define APB_SARADC_THRES1_HIGH_INT_ST_S  28
-/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_LOW_INT_ST    (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_ST_M  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_ST_V  0x1
-#define APB_SARADC_THRES0_LOW_INT_ST_S  27
-/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_LOW_INT_ST    (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_ST_M  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_ST_V  0x1
-#define APB_SARADC_THRES1_LOW_INT_ST_S  26
-
-#define APB_SARADC_INT_CLR_REG          (DR_REG_APB_SARADC_BASE + 0x68)
-/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_ADC1_DONE_INT_CLR    (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_CLR_M  (BIT(31))
-#define APB_SARADC_ADC1_DONE_INT_CLR_V  0x1
-#define APB_SARADC_ADC1_DONE_INT_CLR_S  31
-/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_ADC2_DONE_INT_CLR    (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_CLR_M  (BIT(30))
-#define APB_SARADC_ADC2_DONE_INT_CLR_V  0x1
-#define APB_SARADC_ADC2_DONE_INT_CLR_S  30
-/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_HIGH_INT_CLR    (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_CLR_M  (BIT(29))
-#define APB_SARADC_THRES0_HIGH_INT_CLR_V  0x1
-#define APB_SARADC_THRES0_HIGH_INT_CLR_S  29
-/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_HIGH_INT_CLR    (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_CLR_M  (BIT(28))
-#define APB_SARADC_THRES1_HIGH_INT_CLR_V  0x1
-#define APB_SARADC_THRES1_HIGH_INT_CLR_S  28
-/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES0_LOW_INT_CLR    (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_CLR_M  (BIT(27))
-#define APB_SARADC_THRES0_LOW_INT_CLR_V  0x1
-#define APB_SARADC_THRES0_LOW_INT_CLR_S  27
-/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define APB_SARADC_THRES1_LOW_INT_CLR    (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_CLR_M  (BIT(26))
-#define APB_SARADC_THRES1_LOW_INT_CLR_V  0x1
-#define APB_SARADC_THRES1_LOW_INT_CLR_S  26
-
-#define APB_SARADC_DMA_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x6C)
-/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: enable apb_adc use spi_dma.*/
-#define APB_SARADC_APB_ADC_TRANS    (BIT(31))
-#define APB_SARADC_APB_ADC_TRANS_M  (BIT(31))
-#define APB_SARADC_APB_ADC_TRANS_V  0x1
-#define APB_SARADC_APB_ADC_TRANS_S  31
-/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: reset_apb_adc_state.*/
-#define APB_SARADC_APB_ADC_RESET_FSM    (BIT(30))
-#define APB_SARADC_APB_ADC_RESET_FSM_M  (BIT(30))
-#define APB_SARADC_APB_ADC_RESET_FSM_V  0x1
-#define APB_SARADC_APB_ADC_RESET_FSM_S  30
-/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
-/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num.*/
-#define APB_SARADC_APB_ADC_EOF_NUM    0x0000FFFF
-#define APB_SARADC_APB_ADC_EOF_NUM_M  ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
-#define APB_SARADC_APB_ADC_EOF_NUM_V  0xFFFF
-#define APB_SARADC_APB_ADC_EOF_NUM_S  0
-
-#define APB_SARADC_APB_ADC_CLKM_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x70)
-/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
-/*description: Set this bit to enable clk_apll.*/
-#define APB_SARADC_CLK_SEL    0x00000003
-#define APB_SARADC_CLK_SEL_M  ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
-#define APB_SARADC_CLK_SEL_V  0x3
-#define APB_SARADC_CLK_SEL_S  21
-/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: .*/
-#define APB_SARADC_CLK_EN    (BIT(20))
-#define APB_SARADC_CLK_EN_M  (BIT(20))
-#define APB_SARADC_CLK_EN_V  0x1
-#define APB_SARADC_CLK_EN_S  20
-/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
-/*description: Fractional clock divider denominator value.*/
-#define APB_SARADC_CLKM_DIV_A    0x0000003F
-#define APB_SARADC_CLKM_DIV_A_M  ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
-#define APB_SARADC_CLKM_DIV_A_V  0x3F
-#define APB_SARADC_CLKM_DIV_A_S  14
-/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
-/*description: Fractional clock divider numerator value.*/
-#define APB_SARADC_CLKM_DIV_B    0x0000003F
-#define APB_SARADC_CLKM_DIV_B_M  ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
-#define APB_SARADC_CLKM_DIV_B_V  0x3F
-#define APB_SARADC_CLKM_DIV_B_S  8
-/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
-/*description: Integral I2S clock divider value.*/
-#define APB_SARADC_CLKM_DIV_NUM    0x000000FF
-#define APB_SARADC_CLKM_DIV_NUM_M  ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
-#define APB_SARADC_CLKM_DIV_NUM_V  0xFF
-#define APB_SARADC_CLKM_DIV_NUM_S  0
-
-#define APB_SARADC_APB_SARADC2_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x78)
-/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
-/*description: .*/
-#define APB_SARADC_ADC2_DATA    0x0001FFFF
-#define APB_SARADC_ADC2_DATA_M  ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
-#define APB_SARADC_ADC2_DATA_V  0x1FFFF
-#define APB_SARADC_ADC2_DATA_S  0
-
-#define APB_SARADC_APB_CTRL_DATE_REG          (DR_REG_APB_SARADC_BASE + 0x3FC)
-/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02101180 ; */
-/*description: .*/
-#define APB_SARADC_APB_CTRL_DATE    0xFFFFFFFF
-#define APB_SARADC_APB_CTRL_DATE_M  ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S))
-#define APB_SARADC_APB_CTRL_DATE_V  0xFFFFFFFF
-#define APB_SARADC_APB_CTRL_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_APB_SARADC_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/assist_debug_reg.h b/components/soc/esp32s3/include/soc/assist_debug_reg.h
deleted file mode 100644
index 0bf71c44d33..00000000000
--- a/components/soc/esp32s3/include/soc/assist_debug_reg.h
+++ /dev/null
@@ -1,1338 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_ASSIST_DEBUG_REG_H_
-#define _SOC_ASSIST_DEBUG_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ASSIST_DEBUG_CORE_0_INTERRUPT_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x0)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
-
-#define ASSIST_DEBUG_CORE_0_INTERRUPT_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x4)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
-
-#define ASSIST_DEBUG_CORE_0_INTERRUPT_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x8)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
-
-#define ASSIST_DEBUG_CORE_0_INTERRUPT_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x10)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x14)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x18)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1C)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x20)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x24)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x28)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x2C)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x30)
-/* ASSIST_DEBUG_CORE_0_AREA_SP : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M  ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
-
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x34)
-/* ASSIST_DEBUG_CORE_0_AREA_PC : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M  ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
-
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x38)
-/* ASSIST_DEBUG_CORE_0_SP_UNSTABLE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE    0x000000FF
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_M  ((ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V)<<(ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S))
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V  0xFF
-#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S  0
-
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x3C)
-/* ASSIST_DEBUG_CORE_0_SP_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x40)
-/* ASSIST_DEBUG_CORE_0_SP_MAX : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x44)
-/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x48)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_V  0x1
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x4C)
-/* ASSIST_DEBUG_CORE_0_RCD_RECORDING : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_V  0x1
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x50)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x54)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS    0x000000FF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V  0xFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x58)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x5C)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x60)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x64)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x68)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S  0
-
-#define ASSIST_DEBUG_CORE_0_RCD_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x6C)
-/* ASSIST_DEBUG_CORE_0_RCD_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_RCD_SP    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_SP_M  ((ASSIST_DEBUG_CORE_0_RCD_SP_V)<<(ASSIST_DEBUG_CORE_0_RCD_SP_S))
-#define ASSIST_DEBUG_CORE_0_RCD_SP_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_SP_S  0
-
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x70)
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
-
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x74)
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x78)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(22))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (BIT(22))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  22
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x003FFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x3FFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x7C)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000FFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0xFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x80)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x84)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(22))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (BIT(22))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  22
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x003FFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x3FFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x88)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000FFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0xFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  0
-
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x8C)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
-
-#define ASSIST_DEBUG_CORE_1_INTERRUPT_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x90)
-/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_S  11
-/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_S  10
-/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S  9
-/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S  8
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S  7
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S  6
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S  5
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S  4
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S  3
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S  2
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S  1
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S  0
-
-#define ASSIST_DEBUG_CORE_1_INTERRUPT_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x94)
-/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_S  11
-/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_S  10
-/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S  9
-/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S  8
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S  7
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S  6
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S  5
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S  4
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S  3
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S  2
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S  1
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S  0
-
-#define ASSIST_DEBUG_CORE_1_INTERRUPT_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x98)
-/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_S  11
-/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_S  10
-/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS    (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S  9
-/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS    (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S  8
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS    (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S  7
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS    (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S  6
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS    (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S  5
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS    (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S  4
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS    (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S  3
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS    (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S  2
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S  1
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S  0
-
-#define ASSIST_DEBUG_CORE_1_INTERRUPT_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x9C)
-/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_S  11
-/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_S  10
-/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S  9
-/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S  8
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S  7
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S  6
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S  5
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S  4
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S  3
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S  2
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S  1
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA0)
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA4)
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA8)
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xAC)
-/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S))
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB0)
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB4)
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB8)
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xBC)
-/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC0)
-/* ASSIST_DEBUG_CORE_1_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_PC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PC_M  ((ASSIST_DEBUG_CORE_1_AREA_PC_V)<<(ASSIST_DEBUG_CORE_1_AREA_PC_S))
-#define ASSIST_DEBUG_CORE_1_AREA_PC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_PC_S  0
-
-#define ASSIST_DEBUG_CORE_1_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC4)
-/* ASSIST_DEBUG_CORE_1_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_AREA_SP    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_SP_M  ((ASSIST_DEBUG_CORE_1_AREA_SP_V)<<(ASSIST_DEBUG_CORE_1_AREA_SP_S))
-#define ASSIST_DEBUG_CORE_1_AREA_SP_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_AREA_SP_S  0
-
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC8)
-/* ASSIST_DEBUG_CORE_1_SP_UNSTABLE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE    0x000000FF
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_M  ((ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V)<<(ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S))
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V  0xFF
-#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S  0
-
-#define ASSIST_DEBUG_CORE_1_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xCC)
-/* ASSIST_DEBUG_CORE_1_SP_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_MIN_M  ((ASSIST_DEBUG_CORE_1_SP_MIN_V)<<(ASSIST_DEBUG_CORE_1_SP_MIN_S))
-#define ASSIST_DEBUG_CORE_1_SP_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_MIN_S  0
-
-#define ASSIST_DEBUG_CORE_1_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD0)
-/* ASSIST_DEBUG_CORE_1_SP_MAX : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_MAX_M  ((ASSIST_DEBUG_CORE_1_SP_MAX_V)<<(ASSIST_DEBUG_CORE_1_SP_MAX_S))
-#define ASSIST_DEBUG_CORE_1_SP_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_MAX_S  0
-
-#define ASSIST_DEBUG_CORE_1_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD4)
-/* ASSIST_DEBUG_CORE_1_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_SP_PC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_PC_M  ((ASSIST_DEBUG_CORE_1_SP_PC_V)<<(ASSIST_DEBUG_CORE_1_SP_PC_S))
-#define ASSIST_DEBUG_CORE_1_SP_PC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_SP_PC_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD8)
-/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_V  0x1
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xDC)
-/* ASSIST_DEBUG_CORE_1_RCD_RECORDING : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING    (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_V  0x1
-#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE0)
-/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE4)
-/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS    0x000000FF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V  0xFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE8)
-/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xEC)
-/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF0)
-/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF4)
-/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF8)
-/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S))
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S  0
-
-#define ASSIST_DEBUG_CORE_1_RCD_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xFC)
-/* ASSIST_DEBUG_CORE_1_RCD_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_RCD_SP    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_SP_M  ((ASSIST_DEBUG_CORE_1_RCD_SP_V)<<(ASSIST_DEBUG_CORE_1_RCD_SP_S))
-#define ASSIST_DEBUG_CORE_1_RCD_SP_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_RCD_SP_S  0
-
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x100)
-/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V  0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S  25
-/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V  0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S  24
-/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0    0x00FFFFFF
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S  0
-
-#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x104)
-/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V  0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S  25
-/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V  0x1
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S  24
-/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1    0x00FFFFFF
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S  0
-
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x108)
-/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0    (BIT(22))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M  (BIT(22))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V  0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S  22
-/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0    0x003FFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V  0x3FFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S  0
-
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x10C)
-/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0    0x0000FFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V  0xFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S  0
-
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x110)
-/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S  0
-
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x114)
-/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1    (BIT(22))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M  (BIT(22))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V  0x1
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S  22
-/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1    0x003FFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V  0x3FFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S  0
-
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x118)
-/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1    0x0000FFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V  0xFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S  0
-
-#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x11C)
-/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S))
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S  0
-
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x120)
-/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: ~20'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0xFFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
-
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x124)
-/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: ~20'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0xFFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
-
-#define ASSIST_DEBUG_LOG_SETTING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x128)
-/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE    (BIT(6))
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M  (BIT(6))
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V  0x1
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S  6
-/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_MODE    0x00000007
-#define ASSIST_DEBUG_LOG_MODE_M  ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
-#define ASSIST_DEBUG_LOG_MODE_V  0x7
-#define ASSIST_DEBUG_LOG_MODE_S  3
-/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_ENA    0x00000007
-#define ASSIST_DEBUG_LOG_ENA_M  ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
-#define ASSIST_DEBUG_LOG_ENA_V  0x7
-#define ASSIST_DEBUG_LOG_ENA_S  0
-
-#define ASSIST_DEBUG_LOG_DATA_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x12C)
-/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_DATA_0    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_0_M  ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
-#define ASSIST_DEBUG_LOG_DATA_0_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_0_S  0
-
-#define ASSIST_DEBUG_LOG_DATA_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x130)
-/* ASSIST_DEBUG_LOG_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_DATA_1    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_1_M  ((ASSIST_DEBUG_LOG_DATA_1_V)<<(ASSIST_DEBUG_LOG_DATA_1_S))
-#define ASSIST_DEBUG_LOG_DATA_1_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_1_S  0
-
-#define ASSIST_DEBUG_LOG_DATA_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x134)
-/* ASSIST_DEBUG_LOG_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_DATA_2    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_2_M  ((ASSIST_DEBUG_LOG_DATA_2_V)<<(ASSIST_DEBUG_LOG_DATA_2_S))
-#define ASSIST_DEBUG_LOG_DATA_2_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_2_S  0
-
-#define ASSIST_DEBUG_LOG_DATA_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x138)
-/* ASSIST_DEBUG_LOG_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_DATA_3    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_3_M  ((ASSIST_DEBUG_LOG_DATA_3_V)<<(ASSIST_DEBUG_LOG_DATA_3_S))
-#define ASSIST_DEBUG_LOG_DATA_3_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_3_S  0
-
-#define ASSIST_DEBUG_LOG_DATA_MASK_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x13C)
-/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_DATA_SIZE    0x0000FFFF
-#define ASSIST_DEBUG_LOG_DATA_SIZE_M  ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
-#define ASSIST_DEBUG_LOG_DATA_SIZE_V  0xFFFF
-#define ASSIST_DEBUG_LOG_DATA_SIZE_S  0
-
-#define ASSIST_DEBUG_LOG_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x140)
-/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MIN_M  ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
-#define ASSIST_DEBUG_LOG_MIN_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MIN_S  0
-
-#define ASSIST_DEBUG_LOG_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x144)
-/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MAX_M  ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
-#define ASSIST_DEBUG_LOG_MAX_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MAX_S  0
-
-#define ASSIST_DEBUG_LOG_MEM_START_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x148)
-/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_MEM_START    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_START_M  ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
-#define ASSIST_DEBUG_LOG_MEM_START_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_START_S  0
-
-#define ASSIST_DEBUG_LOG_MEM_END_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x14C)
-/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_MEM_END    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_END_M  ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
-#define ASSIST_DEBUG_LOG_MEM_END_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_END_S  0
-
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x150)
-/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M  ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V  0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S  0
-
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x154)
-/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG    (BIT(0))
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M  (BIT(0))
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V  0x1
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S  0
-
-#define ASSIST_DEBUG_REG_DATE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
-/* ASSIST_DEBUG_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003040 ; */
-/*description: .*/
-#define ASSIST_DEBUG_REG_DATE    0x0FFFFFFF
-#define ASSIST_DEBUG_REG_DATE_M  ((ASSIST_DEBUG_REG_DATE_V)<<(ASSIST_DEBUG_REG_DATE_S))
-#define ASSIST_DEBUG_REG_DATE_V  0xFFFFFFF
-#define ASSIST_DEBUG_REG_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_ASSIST_DEBUG_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/assist_debug_struct.h b/components/soc/esp32s3/include/soc/assist_debug_struct.h
deleted file mode 100644
index a6152af468c..00000000000
--- a/components/soc/esp32s3/include/soc/assist_debug_struct.h
+++ /dev/null
@@ -1,466 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_ASSIST_DEBUG_STRUCT_H_
-#define _SOC_ASSIST_DEBUG_STRUCT_H_
-
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct assist_debug_dev_s {
-    union {
-        struct {
-            uint32_t core_0_area_dram0_0_rd        :    1;
-            uint32_t core_0_area_dram0_0_wr        :    1;
-            uint32_t core_0_area_dram0_1_rd        :    1;
-            uint32_t core_0_area_dram0_1_wr        :    1;
-            uint32_t core_0_area_pif_0_rd          :    1;
-            uint32_t core_0_area_pif_0_wr          :    1;
-            uint32_t core_0_area_pif_1_rd          :    1;
-            uint32_t core_0_area_pif_1_wr          :    1;
-            uint32_t core_0_sp_spill_min           :    1;
-            uint32_t core_0_sp_spill_max           :    1;
-            uint32_t core_0_iram0_exception_monitor:    1;
-            uint32_t core_0_dram0_exception_monitor:    1;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_0_interrupt_ena;
-    union {
-        struct {
-            uint32_t core_0_area_dram0_0_rd        :    1;
-            uint32_t core_0_area_dram0_0_wr        :    1;
-            uint32_t core_0_area_dram0_1_rd        :    1;
-            uint32_t core_0_area_dram0_1_wr        :    1;
-            uint32_t core_0_area_pif_0_rd          :    1;
-            uint32_t core_0_area_pif_0_wr          :    1;
-            uint32_t core_0_area_pif_1_rd          :    1;
-            uint32_t core_0_area_pif_1_wr          :    1;
-            uint32_t core_0_sp_spill_min           :    1;
-            uint32_t core_0_sp_spill_max           :    1;
-            uint32_t core_0_iram0_exception_monitor:    1;
-            uint32_t core_0_dram0_exception_monitor:    1;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_0_interrupt_raw;
-    union {
-        struct {
-            uint32_t core_0_area_dram0_0_rd        :    1;
-            uint32_t core_0_area_dram0_0_wr        :    1;
-            uint32_t core_0_area_dram0_1_rd        :    1;
-            uint32_t core_0_area_dram0_1_wr        :    1;
-            uint32_t core_0_area_pif_0_rd          :    1;
-            uint32_t core_0_area_pif_0_wr          :    1;
-            uint32_t core_0_area_pif_1_rd          :    1;
-            uint32_t core_0_area_pif_1_wr          :    1;
-            uint32_t core_0_sp_spill_min           :    1;
-            uint32_t core_0_sp_spill_max           :    1;
-            uint32_t core_0_iram0_exception_monitor:    1;
-            uint32_t core_0_dram0_exception_monitor:    1;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_0_interrupt_rls;
-    union {
-        struct {
-            uint32_t core_0_area_dram0_0_rd        :    1;
-            uint32_t core_0_area_dram0_0_wr        :    1;
-            uint32_t core_0_area_dram0_1_rd        :    1;
-            uint32_t core_0_area_dram0_1_wr        :    1;
-            uint32_t core_0_area_pif_0_rd          :    1;
-            uint32_t core_0_area_pif_0_wr          :    1;
-            uint32_t core_0_area_pif_1_rd          :    1;
-            uint32_t core_0_area_pif_1_wr          :    1;
-            uint32_t core_0_sp_spill_min           :    1;
-            uint32_t core_0_sp_spill_max           :    1;
-            uint32_t core_0_iram0_exception_monitor:    1;
-            uint32_t core_0_dram0_exception_monitor:    1;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_0_interrupt_clr;
-    uint32_t core_0_area_dram0_0_min;
-    uint32_t core_0_area_dram0_0_max;
-    uint32_t core_0_area_dram0_1_min;
-    uint32_t core_0_area_dram0_1_max;
-    uint32_t core_0_area_pif_0_min;
-    uint32_t core_0_area_pif_0_max;
-    uint32_t core_0_area_pif_1_min;
-    uint32_t core_0_area_pif_1_max;
-    uint32_t core_0_area_sp;
-    uint32_t core_0_area_pc;
-    union {
-        struct {
-            uint32_t core_0_sp_unstable            :    8;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } core_0_sp_unstable;
-    uint32_t core_0_sp_min;
-    uint32_t core_0_sp_max;
-    uint32_t core_0_sp_pc;
-    union {
-        struct {
-            uint32_t core_0_rcd_pdebugenable       :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_rcd_pdebugenable;
-    union {
-        struct {
-            uint32_t core_0_rcd_recording          :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_rcd_recording;
-    uint32_t core_0_rcd_pdebuginst;
-    union {
-        struct {
-            uint32_t core_0_rcd_pdebugstatus       :    8;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } core_0_rcd_pdebugstatus;
-    uint32_t core_0_rcd_pdebugdata;
-    uint32_t core_0_rcd_pdebugpc;
-    uint32_t core_0_rcd_pdebugls0stat;
-    uint32_t core_0_rcd_pdebugls0addr;
-    uint32_t core_0_rcd_pdebugls0data;
-    uint32_t core_0_rcd_sp;
-    union {
-        struct {
-            uint32_t core_0_iram0_recording_addr_0 :    24;
-            uint32_t core_0_iram0_recording_wr_0   :    1;
-            uint32_t core_0_iram0_recording_loadstore_0:    1;
-            uint32_t reserved26                    :    6;
-        };
-        uint32_t val;
-    } core_0_iram0_exception_monitor_0;
-    union {
-        struct {
-            uint32_t core_0_iram0_recording_addr_1 :    24;
-            uint32_t core_0_iram0_recording_wr_1   :    1;
-            uint32_t core_0_iram0_recording_loadstore_1:    1;
-            uint32_t reserved26                    :    6;
-        };
-        uint32_t val;
-    } core_0_iram0_exception_monitor_1;
-    union {
-        struct {
-            uint32_t core_0_dram0_recording_addr_0 :    22;
-            uint32_t core_0_dram0_recording_wr_0   :    1;
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } core_0_dram0_exception_monitor_0;
-    union {
-        struct {
-            uint32_t core_0_dram0_recording_byteen_0:    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } core_0_dram0_exception_monitor_1;
-    uint32_t core_0_dram0_exception_monitor_2;
-    union {
-        struct {
-            uint32_t core_0_dram0_recording_addr_1 :    22;
-            uint32_t core_0_dram0_recording_wr_1   :    1;
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } core_0_dram0_exception_monitor_3;
-    union {
-        struct {
-            uint32_t core_0_dram0_recording_byteen_1:    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } core_0_dram0_exception_monitor_4;
-    uint32_t core_0_dram0_exception_monitor_5;
-    union {
-        struct {
-            uint32_t core_1_area_dram0_0_rd        :    1;
-            uint32_t core_1_area_dram0_0_wr        :    1;
-            uint32_t core_1_area_dram0_1_rd        :    1;
-            uint32_t core_1_area_dram0_1_wr        :    1;
-            uint32_t core_1_area_pif_0_rd          :    1;
-            uint32_t core_1_area_pif_0_wr          :    1;
-            uint32_t core_1_area_pif_1_rd          :    1;
-            uint32_t core_1_area_pif_1_wr          :    1;
-            uint32_t core_1_sp_spill_min           :    1;
-            uint32_t core_1_sp_spill_max           :    1;
-            uint32_t core_1_iram0_exception_monitor:    1;
-            uint32_t core_1_dram0_exception_monitor:    1;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_1_interrupt_ena;
-    union {
-        struct {
-            uint32_t core_1_area_dram0_0_rd        :    1;
-            uint32_t core_1_area_dram0_0_wr        :    1;
-            uint32_t core_1_area_dram0_1_rd        :    1;
-            uint32_t core_1_area_dram0_1_wr        :    1;
-            uint32_t core_1_area_pif_0_rd          :    1;
-            uint32_t core_1_area_pif_0_wr          :    1;
-            uint32_t core_1_area_pif_1_rd          :    1;
-            uint32_t core_1_area_pif_1_wr          :    1;
-            uint32_t core_1_sp_spill_min           :    1;
-            uint32_t core_1_sp_spill_max           :    1;
-            uint32_t core_1_iram0_exception_monitor:    1;
-            uint32_t core_1_dram0_exception_monitor:    1;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_1_interrupt_raw;
-    union {
-        struct {
-            uint32_t core_1_area_dram0_0_rd        :    1;
-            uint32_t core_1_area_dram0_0_wr        :    1;
-            uint32_t core_1_area_dram0_1_rd        :    1;
-            uint32_t core_1_area_dram0_1_wr        :    1;
-            uint32_t core_1_area_pif_0_rd          :    1;
-            uint32_t core_1_area_pif_0_wr          :    1;
-            uint32_t core_1_area_pif_1_rd          :    1;
-            uint32_t core_1_area_pif_1_wr          :    1;
-            uint32_t core_1_sp_spill_min           :    1;
-            uint32_t core_1_sp_spill_max           :    1;
-            uint32_t core_1_iram0_exception_monitor:    1;
-            uint32_t core_1_dram0_exception_monitor:    1;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_1_interrupt_rls;
-    union {
-        struct {
-            uint32_t core_1_area_dram0_0_rd        :    1;
-            uint32_t core_1_area_dram0_0_wr        :    1;
-            uint32_t core_1_area_dram0_1_rd        :    1;
-            uint32_t core_1_area_dram0_1_wr        :    1;
-            uint32_t core_1_area_pif_0_rd          :    1;
-            uint32_t core_1_area_pif_0_wr          :    1;
-            uint32_t core_1_area_pif_1_rd          :    1;
-            uint32_t core_1_area_pif_1_wr          :    1;
-            uint32_t core_1_sp_spill_min           :    1;
-            uint32_t core_1_sp_spill_max           :    1;
-            uint32_t core_1_iram0_exception_monitor:    1;
-            uint32_t core_1_dram0_exception_monitor:    1;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_1_interrupt_clr;
-    uint32_t core_1_area_dram0_0_min;
-    uint32_t core_1_area_dram0_0_max;
-    uint32_t core_1_area_dram0_1_min;
-    uint32_t core_1_area_dram0_1_max;
-    uint32_t core_1_area_pif_0_min;
-    uint32_t core_1_area_pif_0_max;
-    uint32_t core_1_area_pif_1_min;
-    uint32_t core_1_area_pif_1_max;
-    uint32_t core_1_area_pc;
-    uint32_t core_1_area_sp;
-    union {
-        struct {
-            uint32_t core_1_sp_unstable            :    8;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } core_1_sp_unstable;
-    uint32_t core_1_sp_min;
-    uint32_t core_1_sp_max;
-    uint32_t core_1_sp_pc;
-    union {
-        struct {
-            uint32_t core_1_rcd_pdebugenable       :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_rcd_pdebugenable;
-    union {
-        struct {
-            uint32_t core_1_rcd_recording          :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_rcd_recording;
-    uint32_t core_1_rcd_pdebuginst;
-    union {
-        struct {
-            uint32_t core_1_rcd_pdebugstatus       :    8;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } core_1_rcd_pdebugstatus;
-    uint32_t core_1_rcd_pdebugdata;
-    uint32_t core_1_rcd_pdebugpc;
-    uint32_t core_1_rcd_pdebugls0stat;
-    uint32_t core_1_rcd_pdebugls0addr;
-    uint32_t core_1_rcd_pdebugls0data;
-    uint32_t core_1_rcd_sp;
-    union {
-        struct {
-            uint32_t core_1_iram0_recording_addr_0 :    24;
-            uint32_t core_1_iram0_recording_wr_0   :    1;
-            uint32_t core_1_iram0_recording_loadstore_0:    1;
-            uint32_t reserved26                    :    6;
-        };
-        uint32_t val;
-    } core_1_iram0_exception_monitor_0;
-    union {
-        struct {
-            uint32_t core_1_iram0_recording_addr_1 :    24;
-            uint32_t core_1_iram0_recording_wr_1   :    1;
-            uint32_t core_1_iram0_recording_loadstore_1:    1;
-            uint32_t reserved26                    :    6;
-        };
-        uint32_t val;
-    } core_1_iram0_exception_monitor_1;
-    union {
-        struct {
-            uint32_t core_1_dram0_recording_addr_0 :    22;
-            uint32_t core_1_dram0_recording_wr_0   :    1;
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } core_1_dram0_exception_monitor_0;
-    union {
-        struct {
-            uint32_t core_1_dram0_recording_byteen_0:    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } core_1_dram0_exception_monitor_1;
-    uint32_t core_1_dram0_exception_monitor_2;
-    union {
-        struct {
-            uint32_t core_1_dram0_recording_addr_1 :    22;
-            uint32_t core_1_dram0_recording_wr_1   :    1;
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } core_1_dram0_exception_monitor_3;
-    union {
-        struct {
-            uint32_t core_1_dram0_recording_byteen_1:    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } core_1_dram0_exception_monitor_4;
-    uint32_t core_1_dram0_exception_monitor_5;
-    union {
-        struct {
-            uint32_t core_x_iram0_dram0_limit_cycle_0:    20;
-            uint32_t reserved20                    :    12;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_exception_monitor_0;
-    union {
-        struct {
-            uint32_t core_x_iram0_dram0_limit_cycle_1:    20;
-            uint32_t reserved20                    :    12;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_exception_monitor_1;
-    union {
-        struct {
-            uint32_t log                           :    3;
-            uint32_t log_mode                      :    3;
-            uint32_t log_mem_loopble               :    1;
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } log_setting;
-    uint32_t log_data_0;
-    uint32_t log_data_1;
-    uint32_t log_data_2;
-    uint32_t log_data_3;
-    union {
-        struct {
-            uint32_t log_data_size                 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } log_data_mask;
-    uint32_t log_min;
-    uint32_t log_max;
-    uint32_t log_mem_start;
-    uint32_t log_mem_end;
-    uint32_t log_mem_writing_addr;
-    union {
-        struct {
-            uint32_t log_mem_full_flag             :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } log_mem_full_flag;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    union {
-        struct {
-            uint32_t assist_debug_reg_date         :    28;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } reg_date;
-} assist_debug_dev_t;
-extern assist_debug_dev_t ASSIST_DEBUG;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_ASSIST_DEBUG_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/clk_tree_defs.h b/components/soc/esp32s3/include/soc/clk_tree_defs.h
index dc74e9ad564..4f3bea99858 100644
--- a/components/soc/esp32s3/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32s3/include/soc/clk_tree_defs.h
@@ -21,7 +21,7 @@ extern "C" {
  *
  * 2) External 40MHz Crystal Clock: XTAL
  *
- * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.
@@ -83,9 +83,12 @@ typedef enum {
  */
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0,      /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 1,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
 } soc_rtc_fast_clk_src_t;
 
 /**
diff --git a/components/soc/esp32s3/include/soc/dport_reg.h b/components/soc/esp32s3/include/soc/dport_reg.h
index e17afb79b5c..e9f3de4c442 100644
--- a/components/soc/esp32s3/include/soc/dport_reg.h
+++ b/components/soc/esp32s3/include/soc/dport_reg.h
@@ -5,20 +5,19 @@
  */
 #pragma once
 
-#include "soc.h"
+#include "soc/interrupt_reg.h"
+#include "soc/system_reg.h"
+#include "soc/sensitive_reg.h"
+#include "soc/soc.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include "interrupt_reg.h"
-#include "system_reg.h"
-#include "sensitive_reg.h"
-#include "soc.h"
-
 #define DPORT_DATE_REG SYSTEM_DATE_REG
 
 #ifndef __ASSEMBLER__
-#include "dport_access.h"
+#include "soc/dport_access.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h
deleted file mode 100644
index c4b8a5ed47a..00000000000
--- a/components/soc/esp32s3/include/soc/efuse_reg.h
+++ /dev/null
@@ -1,2899 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#include "efuse_defs.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** EFUSE_PGM_DATA0_REG register
- *  Register 0 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
-/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 0th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
-#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_0_S  0
-
-/** EFUSE_PGM_DATA1_REG register
- *  Register 1 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
-/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 1st 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
-#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_1_S  0
-
-/** EFUSE_PGM_DATA2_REG register
- *  Register 2 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
-/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 2nd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
-#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_2_S  0
-
-/** EFUSE_PGM_DATA3_REG register
- *  Register 3 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
-/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 3rd 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
-#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_3_S  0
-
-/** EFUSE_PGM_DATA4_REG register
- *  Register 4 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
-/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 4th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
-#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_4_S  0
-
-/** EFUSE_PGM_DATA5_REG register
- *  Register 5 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
-/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 5th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
-#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_5_S  0
-
-/** EFUSE_PGM_DATA6_REG register
- *  Register 6 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
-/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 6th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
-#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_6_S  0
-
-/** EFUSE_PGM_DATA7_REG register
- *  Register 7 that stores data to be programmed.
- */
-#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
-/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 7th 32-bit data to be programmed.
- */
-#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
-#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
-#define EFUSE_PGM_DATA_7_S  0
-
-/** EFUSE_PGM_CHECK_VALUE0_REG register
- *  Register 0 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
-/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 0th 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
-#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_0_S  0
-
-/** EFUSE_PGM_CHECK_VALUE1_REG register
- *  Register 1 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
-/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 1st 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
-#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_1_S  0
-
-/** EFUSE_PGM_CHECK_VALUE2_REG register
- *  Register 2 that stores the RS code to be programmed.
- */
-#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
-/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
- *  The content of the 2nd 32-bit RS code to be programmed.
- */
-#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
-#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
-#define EFUSE_PGM_RS_DATA_2_S  0
-
-/** EFUSE_RD_WR_DIS_REG register
- *  BLOCK0 data register 0.
- */
-#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
-/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
- *  Disable programming of individual eFuses.
- */
-#define EFUSE_WR_DIS    0xFFFFFFFFU
-#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
-#define EFUSE_WR_DIS_V  0xFFFFFFFFU
-#define EFUSE_WR_DIS_S  0
-
-/** EFUSE_RD_REPEAT_DATA0_REG register
- *  BLOCK0 data register 1.
- */
-#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
-/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
- *  Set this bit to disable reading from BlOCK4-10.
- */
-#define EFUSE_RD_DIS    0x0000007FU
-#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
-#define EFUSE_RD_DIS_V  0x0000007FU
-#define EFUSE_RD_DIS_S  0
-/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0;
- *  Set this bit to disable boot from RTC RAM.
- */
-#define EFUSE_DIS_RTC_RAM_BOOT    (BIT(7))
-#define EFUSE_DIS_RTC_RAM_BOOT_M  (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S)
-#define EFUSE_DIS_RTC_RAM_BOOT_V  0x00000001U
-#define EFUSE_DIS_RTC_RAM_BOOT_S  7
-/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
- *  Set this bit to disable Icache.
- */
-#define EFUSE_DIS_ICACHE    (BIT(8))
-#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
-#define EFUSE_DIS_ICACHE_V  0x00000001U
-#define EFUSE_DIS_ICACHE_S  8
-/** EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0;
- *  Set this bit to disable Dcache.
- */
-#define EFUSE_DIS_DCACHE    (BIT(9))
-#define EFUSE_DIS_DCACHE_M  (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S)
-#define EFUSE_DIS_DCACHE_V  0x00000001U
-#define EFUSE_DIS_DCACHE_S  9
-/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0;
- *  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6,
- *  7).
- */
-#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(10))
-#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
-#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
-/** EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0;
- *  Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6,
- *  7).
- */
-#define EFUSE_DIS_DOWNLOAD_DCACHE    (BIT(11))
-#define EFUSE_DIS_DOWNLOAD_DCACHE_M  (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S)
-#define EFUSE_DIS_DOWNLOAD_DCACHE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_DCACHE_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
- *  Set this bit to disable the function that forces chip into download mode.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
-/** EFUSE_DIS_USB_OTG : RO; bitpos: [13]; default: 0;
- *  Set this bit to disable USB function.
- */
-#define EFUSE_DIS_USB_OTG    (BIT(13))
-#define EFUSE_DIS_USB_OTG_M  (EFUSE_DIS_USB_OTG_V << EFUSE_DIS_USB_OTG_S)
-#define EFUSE_DIS_USB_OTG_V  0x00000001U
-#define EFUSE_DIS_USB_OTG_S  13
-/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
- *  Set this bit to disable CAN function.
- */
-#define EFUSE_DIS_TWAI    (BIT(14))
-#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
-#define EFUSE_DIS_TWAI_V  0x00000001U
-#define EFUSE_DIS_TWAI_S  14
-/** EFUSE_DIS_APP_CPU : RO; bitpos: [15]; default: 0;
- *  Disable app cpu.
- */
-#define EFUSE_DIS_APP_CPU    (BIT(15))
-#define EFUSE_DIS_APP_CPU_M  (EFUSE_DIS_APP_CPU_V << EFUSE_DIS_APP_CPU_S)
-#define EFUSE_DIS_APP_CPU_V  0x00000001U
-#define EFUSE_DIS_APP_CPU_S  15
-/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
- *  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG
- *  can be enabled in HMAC module.
- */
-#define EFUSE_SOFT_DIS_JTAG    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
-#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_S  16
-/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
- *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
- */
-#define EFUSE_DIS_PAD_JTAG    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
-#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
- *  Set this bit to disable flash encryption when in download boot modes.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
-/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
- *  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored
- *  in eFuse.
- */
-#define EFUSE_USB_DREFH    0x00000003U
-#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
-#define EFUSE_USB_DREFH_V  0x00000003U
-#define EFUSE_USB_DREFH_S  21
-/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
- *  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
- *  stored in eFuse.
- */
-#define EFUSE_USB_DREFL    0x00000003U
-#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
-#define EFUSE_USB_DREFL_V  0x00000003U
-#define EFUSE_USB_DREFL_S  23
-/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
- *  Set this bit to exchange USB D+ and D- pins.
- */
-#define EFUSE_USB_EXCHG_PINS    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
-#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_S  25
-/** EFUSE_USB_EXT_PHY_ENABLE : RO; bitpos: [26]; default: 0;
- *  Set this bit to enable external PHY.
- */
-#define EFUSE_USB_EXT_PHY_ENABLE    (BIT(26))
-#define EFUSE_USB_EXT_PHY_ENABLE_M  (EFUSE_USB_EXT_PHY_ENABLE_V << EFUSE_USB_EXT_PHY_ENABLE_S)
-#define EFUSE_USB_EXT_PHY_ENABLE_V  0x00000001U
-#define EFUSE_USB_EXT_PHY_ENABLE_S  26
-/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0;
- *  Bluetooth GPIO signal output security level control.
- */
-#define EFUSE_BTLC_GPIO_ENABLE    0x00000003U
-#define EFUSE_BTLC_GPIO_ENABLE_M  (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S)
-#define EFUSE_BTLC_GPIO_ENABLE_V  0x00000003U
-#define EFUSE_BTLC_GPIO_ENABLE_S  27
-/** EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0;
- *  SPI regulator switches current limit mode.
- */
-#define EFUSE_VDD_SPI_MODECURLIM    (BIT(29))
-#define EFUSE_VDD_SPI_MODECURLIM_M  (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S)
-#define EFUSE_VDD_SPI_MODECURLIM_V  0x00000001U
-#define EFUSE_VDD_SPI_MODECURLIM_S  29
-/** EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0;
- *  SPI regulator high voltage reference.
- */
-#define EFUSE_VDD_SPI_DREFH    0x00000003U
-#define EFUSE_VDD_SPI_DREFH_M  (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S)
-#define EFUSE_VDD_SPI_DREFH_V  0x00000003U
-#define EFUSE_VDD_SPI_DREFH_S  30
-
-/** EFUSE_RD_REPEAT_DATA1_REG register
- *  BLOCK0 data register 2.
- */
-#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
-/** EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0;
- *  SPI regulator medium voltage reference.
- */
-#define EFUSE_VDD_SPI_DREFM    0x00000003U
-#define EFUSE_VDD_SPI_DREFM_M  (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S)
-#define EFUSE_VDD_SPI_DREFM_V  0x00000003U
-#define EFUSE_VDD_SPI_DREFM_S  0
-/** EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0;
- *  SPI regulator low voltage reference.
- */
-#define EFUSE_VDD_SPI_DREFL    0x00000003U
-#define EFUSE_VDD_SPI_DREFL_M  (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S)
-#define EFUSE_VDD_SPI_DREFL_V  0x00000003U
-#define EFUSE_VDD_SPI_DREFL_S  2
-/** EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0;
- *  SPI regulator power up signal.
- */
-#define EFUSE_VDD_SPI_XPD    (BIT(4))
-#define EFUSE_VDD_SPI_XPD_M  (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S)
-#define EFUSE_VDD_SPI_XPD_V  0x00000001U
-#define EFUSE_VDD_SPI_XPD_S  4
-/** EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0;
- *  SPI regulator output is short connected to VDD3P3_RTC_IO.
- */
-#define EFUSE_VDD_SPI_TIEH    (BIT(5))
-#define EFUSE_VDD_SPI_TIEH_M  (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S)
-#define EFUSE_VDD_SPI_TIEH_V  0x00000001U
-#define EFUSE_VDD_SPI_TIEH_S  5
-/** EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0;
- *  Set this bit and force to use the configuration of eFuse to configure VDD_SPI.
- */
-#define EFUSE_VDD_SPI_FORCE    (BIT(6))
-#define EFUSE_VDD_SPI_FORCE_M  (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S)
-#define EFUSE_VDD_SPI_FORCE_V  0x00000001U
-#define EFUSE_VDD_SPI_FORCE_S  6
-/** EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0;
- *  Set SPI regulator to 0 to configure init[1:0]=0.
- */
-#define EFUSE_VDD_SPI_EN_INIT    (BIT(7))
-#define EFUSE_VDD_SPI_EN_INIT_M  (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S)
-#define EFUSE_VDD_SPI_EN_INIT_V  0x00000001U
-#define EFUSE_VDD_SPI_EN_INIT_S  7
-/** EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0;
- *  Set SPI regulator to 1 to enable output current limit.
- */
-#define EFUSE_VDD_SPI_ENCURLIM    (BIT(8))
-#define EFUSE_VDD_SPI_ENCURLIM_M  (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S)
-#define EFUSE_VDD_SPI_ENCURLIM_V  0x00000001U
-#define EFUSE_VDD_SPI_ENCURLIM_S  8
-/** EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0;
- *  Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).
- */
-#define EFUSE_VDD_SPI_DCURLIM    0x00000007U
-#define EFUSE_VDD_SPI_DCURLIM_M  (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S)
-#define EFUSE_VDD_SPI_DCURLIM_V  0x00000007U
-#define EFUSE_VDD_SPI_DCURLIM_S  9
-/** EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0;
- *  Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.
- */
-#define EFUSE_VDD_SPI_INIT    0x00000003U
-#define EFUSE_VDD_SPI_INIT_M  (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S)
-#define EFUSE_VDD_SPI_INIT_V  0x00000003U
-#define EFUSE_VDD_SPI_INIT_S  12
-/** EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0;
- *  Prevents SPI regulator from overshoot.
- */
-#define EFUSE_VDD_SPI_DCAP    0x00000003U
-#define EFUSE_VDD_SPI_DCAP_M  (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S)
-#define EFUSE_VDD_SPI_DCAP_V  0x00000003U
-#define EFUSE_VDD_SPI_DCAP_S  14
-/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
- *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
- *  80000. 2: 160000. 3:320000.
- */
-#define EFUSE_WDT_DELAY_SEL    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
-#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
- *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
- *  number of 1: disable.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
- *  Set this bit to enable revoking first secure boot key.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
- *  Set this bit to enable revoking second secure boot key.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
- *  Set this bit to enable revoking third secure boot key.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
-/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
- *  Purpose of Key0.
- */
-#define EFUSE_KEY_PURPOSE_0    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
-#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_S  24
-/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
- *  Purpose of Key1.
- */
-#define EFUSE_KEY_PURPOSE_1    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
-#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_S  28
-
-/** EFUSE_RD_REPEAT_DATA2_REG register
- *  BLOCK0 data register 3.
- */
-#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
-/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
- *  Purpose of Key2.
- */
-#define EFUSE_KEY_PURPOSE_2    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
-#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_S  0
-/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
- *  Purpose of Key3.
- */
-#define EFUSE_KEY_PURPOSE_3    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
-#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_S  4
-/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
- *  Purpose of Key4.
- */
-#define EFUSE_KEY_PURPOSE_4    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
-#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_S  8
-/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
- *  Purpose of Key5.
- */
-#define EFUSE_KEY_PURPOSE_5    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
-#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_S  12
-/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [19:16]; default: 0;
- *  Reserved (used for four backups method).
- */
-#define EFUSE_RPT4_RESERVED0    0x0000000FU
-#define EFUSE_RPT4_RESERVED0_M  (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S)
-#define EFUSE_RPT4_RESERVED0_V  0x0000000FU
-#define EFUSE_RPT4_RESERVED0_S  16
-/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
- *  Set this bit to enable secure boot.
- */
-#define EFUSE_SECURE_BOOT_EN    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
-#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
- *  Set this bit to enable revoking aggressive secure boot.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
-/** EFUSE_DIS_USB_JTAG : RO; bitpos: [22]; default: 0;
- *  Set this bit to disable function of usb switch to jtag in module of usb device.
- */
-#define EFUSE_DIS_USB_JTAG    (BIT(22))
-#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
-#define EFUSE_DIS_USB_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_S  22
-/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [23]; default: 0;
- *  Set this bit to disable usb device.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(23))
-#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_S  23
-/** EFUSE_STRAP_JTAG_SEL : RO; bitpos: [24]; default: 0;
- *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
- *  strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
- */
-#define EFUSE_STRAP_JTAG_SEL    (BIT(24))
-#define EFUSE_STRAP_JTAG_SEL_M  (EFUSE_STRAP_JTAG_SEL_V << EFUSE_STRAP_JTAG_SEL_S)
-#define EFUSE_STRAP_JTAG_SEL_V  0x00000001U
-#define EFUSE_STRAP_JTAG_SEL_S  24
-/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
- *  This bit is used to switch internal PHY and external PHY for USB OTG and USB
- *  Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to
- *  USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to
- *  USB Device.
- */
-#define EFUSE_USB_PHY_SEL    (BIT(25))
-#define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
-#define EFUSE_USB_PHY_SEL_V  0x00000001U
-#define EFUSE_USB_PHY_SEL_S  25
-/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [27:26]; default: 0;
- *  Sample delay configuration of power glitch.
- */
-#define EFUSE_POWER_GLITCH_DSENSE    0x00000003U
-#define EFUSE_POWER_GLITCH_DSENSE_M  (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S)
-#define EFUSE_POWER_GLITCH_DSENSE_V  0x00000003U
-#define EFUSE_POWER_GLITCH_DSENSE_S  26
-/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
- *  Configures flash waiting time after power-up, in unit of ms. If the value is less
- *  than 15, the waiting time is the configurable value.  Otherwise, the waiting time
- *  is twice the configurable value.
- */
-#define EFUSE_FLASH_TPUW    0x0000000FU
-#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
-#define EFUSE_FLASH_TPUW_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_S  28
-
-/** EFUSE_RD_REPEAT_DATA3_REG register
- *  BLOCK0 data register 4.
- */
-#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
-/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
- *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
- */
-#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_S  0
-/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
- *  Disable direct boot mode
- */
-#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
-#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
-#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
-#define EFUSE_DIS_DIRECT_BOOT_S  1
-/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
- *  Selectes the default UART print channel. 0: UART0. 1: UART1.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
-/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0;
- *  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
- *  use 16to17 byte mode.
- */
-#define EFUSE_FLASH_ECC_MODE    (BIT(3))
-#define EFUSE_FLASH_ECC_MODE_M  (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S)
-#define EFUSE_FLASH_ECC_MODE_V  0x00000001U
-#define EFUSE_FLASH_ECC_MODE_S  3
-/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
- *  Set this bit to disable UART download mode through USB.
- */
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
- *  Set this bit to enable secure UART download mode.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
-/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
- *  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8
- *  is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
- */
-#define EFUSE_UART_PRINT_CONTROL    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
-#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_S  6
-/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0;
- *  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
- */
-#define EFUSE_PIN_POWER_SELECTION    (BIT(8))
-#define EFUSE_PIN_POWER_SELECTION_M  (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S)
-#define EFUSE_PIN_POWER_SELECTION_V  0x00000001U
-#define EFUSE_PIN_POWER_SELECTION_S  8
-/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0;
- *  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
- */
-#define EFUSE_FLASH_TYPE    (BIT(9))
-#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
-#define EFUSE_FLASH_TYPE_V  0x00000001U
-#define EFUSE_FLASH_TYPE_S  9
-/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0;
- *  Set Flash page size.
- */
-#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
-#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_S  10
-/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0;
- *  Set 1 to enable ECC for flash boot.
- */
-#define EFUSE_FLASH_ECC_EN    (BIT(12))
-#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
-#define EFUSE_FLASH_ECC_EN_V  0x00000001U
-#define EFUSE_FLASH_ECC_EN_S  12
-/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
- *  Set this bit to force ROM code to send a resume command during SPI boot.
- */
-#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
-#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
-#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_S  13
-/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0;
- *  Secure version (used by ESP-IDF anti-rollback feature).
- */
-#define EFUSE_SECURE_VERSION    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
-#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_S  14
-/** EFUSE_POWERGLITCH_EN : RO; bitpos: [30]; default: 0;
- *  Set this bit to enable power glitch function.
- */
-#define EFUSE_POWERGLITCH_EN    (BIT(30))
-#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
-#define EFUSE_POWERGLITCH_EN_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_S  30
-/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : R; bitpos: [31]; default: 0;
- *  Set this bit to disable download through USB-OTG
- */
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(31))
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
-#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  31
-
-/** EFUSE_RD_REPEAT_DATA4_REG register
- *  BLOCK0 data register 5.
- */
-#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
-/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0;
- *  Disables check of wafer version major
- */
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(0))
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  0
-/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0;
- *  Disables check of blk version major
- */
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(1))
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
-#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  1
-/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_0_162    0x003FFFFFU
-#define EFUSE_RESERVED_0_162_M  (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S)
-#define EFUSE_RESERVED_0_162_V  0x003FFFFFU
-#define EFUSE_RESERVED_0_162_S  2
-
-/** EFUSE_RD_MAC_SPI_SYS_0_REG register
- *  BLOCK1 data register 0.
- */
-#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
-/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the low 32 bits of MAC address.
- */
-#define EFUSE_MAC_0    0xFFFFFFFFU
-#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
-#define EFUSE_MAC_0_V  0xFFFFFFFFU
-#define EFUSE_MAC_0_S  0
-
-/** EFUSE_RD_MAC_SPI_SYS_1_REG register
- *  BLOCK1 data register 1.
- */
-#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
-/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
- *  Stores the high 16 bits of MAC address.
- */
-#define EFUSE_MAC_1    0x0000FFFFU
-#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
-#define EFUSE_MAC_1_V  0x0000FFFFU
-#define EFUSE_MAC_1_S  0
-/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0;
- *  SPI_PAD_configure CLK
- */
-#define EFUSE_SPI_PAD_CONFIG_CLK    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_CLK_M  (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S)
-#define EFUSE_SPI_PAD_CONFIG_CLK_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_CLK_S  16
-/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0;
- *  SPI_PAD_configure Q(D1)
- */
-#define EFUSE_SPI_PAD_CONFIG_Q    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_Q_M  (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S)
-#define EFUSE_SPI_PAD_CONFIG_Q_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_Q_S  22
-/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0;
- *  SPI_PAD_configure D(D0)
- */
-#define EFUSE_SPI_PAD_CONFIG_D    0x0000000FU
-#define EFUSE_SPI_PAD_CONFIG_D_M  (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S)
-#define EFUSE_SPI_PAD_CONFIG_D_V  0x0000000FU
-#define EFUSE_SPI_PAD_CONFIG_D_S  28
-
-/** EFUSE_RD_MAC_SPI_SYS_2_REG register
- *  BLOCK1 data register 2.
- */
-#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
-/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Stores the first part of SPI_PAD_CONF..*/
-#define EFUSE_SPI_PAD_CONF_1    0xFFFFFFFF
-#define EFUSE_SPI_PAD_CONF_1_M  ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S))
-#define EFUSE_SPI_PAD_CONF_1_V  0xFFFFFFFF
-#define EFUSE_SPI_PAD_CONF_1_S  0
-/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0;
- *  SPI_PAD_configure D(D0)
- */
-#define EFUSE_SPI_PAD_CONFIG_D_1    0x00000003U
-#define EFUSE_SPI_PAD_CONFIG_D_1_M  (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S)
-#define EFUSE_SPI_PAD_CONFIG_D_1_V  0x00000003U
-#define EFUSE_SPI_PAD_CONFIG_D_1_S  0
-/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0;
- *  SPI_PAD_configure CS
- */
-#define EFUSE_SPI_PAD_CONFIG_CS    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_CS_M  (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S)
-#define EFUSE_SPI_PAD_CONFIG_CS_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_CS_S  2
-/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0;
- *  SPI_PAD_configure HD(D3)
- */
-#define EFUSE_SPI_PAD_CONFIG_HD    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_HD_M  (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S)
-#define EFUSE_SPI_PAD_CONFIG_HD_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_HD_S  8
-/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0;
- *  SPI_PAD_configure WP(D2)
- */
-#define EFUSE_SPI_PAD_CONFIG_WP    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_WP_M  (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S)
-#define EFUSE_SPI_PAD_CONFIG_WP_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_WP_S  14
-/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0;
- *  SPI_PAD_configure DQS
- */
-#define EFUSE_SPI_PAD_CONFIG_DQS    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_DQS_M  (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S)
-#define EFUSE_SPI_PAD_CONFIG_DQS_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_DQS_S  20
-/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0;
- *  SPI_PAD_configure D4
- */
-#define EFUSE_SPI_PAD_CONFIG_D4    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D4_M  (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S)
-#define EFUSE_SPI_PAD_CONFIG_D4_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D4_S  26
-
-/** EFUSE_RD_MAC_SPI_SYS_3_REG register
- *  BLOCK1 data register 3.
- */
-#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
-/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0;
- *  SPI_PAD_configure D5
- */
-#define EFUSE_SPI_PAD_CONFIG_D5    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D5_M  (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S)
-#define EFUSE_SPI_PAD_CONFIG_D5_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D5_S  0
-/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0;
- *  SPI_PAD_configure D6
- */
-#define EFUSE_SPI_PAD_CONFIG_D6    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D6_M  (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S)
-#define EFUSE_SPI_PAD_CONFIG_D6_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D6_S  6
-/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0;
- *  SPI_PAD_configure D7
- */
-#define EFUSE_SPI_PAD_CONFIG_D7    0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D7_M  (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S)
-#define EFUSE_SPI_PAD_CONFIG_D7_V  0x0000003FU
-#define EFUSE_SPI_PAD_CONFIG_D7_S  12
-/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0;
- *  WAFER_VERSION_MINOR least significant bits
- */
-#define EFUSE_WAFER_VERSION_MINOR_LO    0x00000007U
-#define EFUSE_WAFER_VERSION_MINOR_LO_M  (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S)
-#define EFUSE_WAFER_VERSION_MINOR_LO_V  0x00000007U
-#define EFUSE_WAFER_VERSION_MINOR_LO_S  18
-/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0;
- *  Package version
- */
-#define EFUSE_PKG_VERSION    0x00000007U
-#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
-#define EFUSE_PKG_VERSION_V  0x00000007U
-#define EFUSE_PKG_VERSION_S  21
-/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0;
- *  BLK_VERSION_MINOR
- */
-#define EFUSE_BLK_VERSION_MINOR    0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
-#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
-#define EFUSE_BLK_VERSION_MINOR_S  24
-/** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0;
- *  Flash capacity
- */
-#define EFUSE_FLASH_CAP    0x00000007U
-#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
-#define EFUSE_FLASH_CAP_V  0x00000007U
-#define EFUSE_FLASH_CAP_S  27
-/** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0;
- *  Flash temperature
- */
-#define EFUSE_FLASH_TEMP    0x00000003U
-#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
-#define EFUSE_FLASH_TEMP_V  0x00000003U
-#define EFUSE_FLASH_TEMP_S  30
-
-/** EFUSE_RD_MAC_SPI_SYS_4_REG register
- *  BLOCK1 data register 4.
- */
-#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
-/** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0;
- *  Flash vendor
- */
-#define EFUSE_FLASH_VENDOR    0x00000007U
-#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
-#define EFUSE_FLASH_VENDOR_V  0x00000007U
-#define EFUSE_FLASH_VENDOR_S  0
-/** EFUSE_PSRAM_CAP : R; bitpos: [4:3]; default: 0;
- *  PSRAM capacity
- */
-#define EFUSE_PSRAM_CAP    0x00000003U
-#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
-#define EFUSE_PSRAM_CAP_V  0x00000003U
-#define EFUSE_PSRAM_CAP_S  3
-/** EFUSE_PSRAM_TEMP : R; bitpos: [6:5]; default: 0;
- *  PSRAM temperature
- */
-#define EFUSE_PSRAM_TEMP    0x00000003U
-#define EFUSE_PSRAM_TEMP_M  (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S)
-#define EFUSE_PSRAM_TEMP_V  0x00000003U
-#define EFUSE_PSRAM_TEMP_S  5
-/** EFUSE_PSRAM_VENDOR : R; bitpos: [8:7]; default: 0;
- *  PSRAM vendor
- */
-#define EFUSE_PSRAM_VENDOR    0x00000003U
-#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
-#define EFUSE_PSRAM_VENDOR_V  0x00000003U
-#define EFUSE_PSRAM_VENDOR_S  7
-/** EFUSE_RESERVED_1_137 : R; bitpos: [12:9]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_137    0x0000000FU
-#define EFUSE_RESERVED_1_137_M  (EFUSE_RESERVED_1_137_V << EFUSE_RESERVED_1_137_S)
-#define EFUSE_RESERVED_1_137_V  0x0000000FU
-#define EFUSE_RESERVED_1_137_S  9
-/** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0;
- *  BLOCK1 K_RTC_LDO
- */
-#define EFUSE_K_RTC_LDO    0x0000007FU
-#define EFUSE_K_RTC_LDO_M  (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S)
-#define EFUSE_K_RTC_LDO_V  0x0000007FU
-#define EFUSE_K_RTC_LDO_S  13
-/** EFUSE_K_DIG_LDO : R; bitpos: [26:20]; default: 0;
- *  BLOCK1 K_DIG_LDO
- */
-#define EFUSE_K_DIG_LDO    0x0000007FU
-#define EFUSE_K_DIG_LDO_M  (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S)
-#define EFUSE_K_DIG_LDO_V  0x0000007FU
-#define EFUSE_K_DIG_LDO_S  20
-/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [31:27]; default: 0;
- *  BLOCK1 voltage of rtc dbias20
- */
-#define EFUSE_V_RTC_DBIAS20    0x0000001FU
-#define EFUSE_V_RTC_DBIAS20_M  (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S)
-#define EFUSE_V_RTC_DBIAS20_V  0x0000001FU
-#define EFUSE_V_RTC_DBIAS20_S  27
-
-/** EFUSE_RD_MAC_SPI_SYS_5_REG register
- *  BLOCK1 data register 5.
- */
-#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
-/** EFUSE_V_RTC_DBIAS20_1 : R; bitpos: [2:0]; default: 0;
- *  BLOCK1 voltage of rtc dbias20
- */
-#define EFUSE_V_RTC_DBIAS20_1    0x00000007U
-#define EFUSE_V_RTC_DBIAS20_1_M  (EFUSE_V_RTC_DBIAS20_1_V << EFUSE_V_RTC_DBIAS20_1_S)
-#define EFUSE_V_RTC_DBIAS20_1_V  0x00000007U
-#define EFUSE_V_RTC_DBIAS20_1_S  0
-/** EFUSE_V_DIG_DBIAS20 : R; bitpos: [10:3]; default: 0;
- *  BLOCK1 voltage of digital dbias20
- */
-#define EFUSE_V_DIG_DBIAS20    0x000000FFU
-#define EFUSE_V_DIG_DBIAS20_M  (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S)
-#define EFUSE_V_DIG_DBIAS20_V  0x000000FFU
-#define EFUSE_V_DIG_DBIAS20_S  3
-/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [15:11]; default: 0;
- *  BLOCK1 digital dbias when hvt
- */
-#define EFUSE_DIG_DBIAS_HVT    0x0000001FU
-#define EFUSE_DIG_DBIAS_HVT_M  (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
-#define EFUSE_DIG_DBIAS_HVT_V  0x0000001FU
-#define EFUSE_DIG_DBIAS_HVT_S  11
-/** EFUSE_RESERVED_1_176 : R; bitpos: [22:16]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_1_176    0x0000007FU
-#define EFUSE_RESERVED_1_176_M  (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S)
-#define EFUSE_RESERVED_1_176_V  0x0000007FU
-#define EFUSE_RESERVED_1_176_S  16
-/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0;
- *  WAFER_VERSION_MINOR most significant bit
- */
-#define EFUSE_WAFER_VERSION_MINOR_HI    (BIT(23))
-#define EFUSE_WAFER_VERSION_MINOR_HI_M  (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S)
-#define EFUSE_WAFER_VERSION_MINOR_HI_V  0x00000001U
-#define EFUSE_WAFER_VERSION_MINOR_HI_S  23
-/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0;
- *  WAFER_VERSION_MAJOR
- */
-#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
-#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_WAFER_VERSION_MAJOR_S  24
-/** EFUSE_ADC2_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0;
- *  ADC2 calibration voltage at atten3
- */
-#define EFUSE_ADC2_CAL_VOL_ATTEN3    0x0000003FU
-#define EFUSE_ADC2_CAL_VOL_ATTEN3_M  (EFUSE_ADC2_CAL_VOL_ATTEN3_V << EFUSE_ADC2_CAL_VOL_ATTEN3_S)
-#define EFUSE_ADC2_CAL_VOL_ATTEN3_V  0x0000003FU
-#define EFUSE_ADC2_CAL_VOL_ATTEN3_S  26
-
-/** EFUSE_RD_SYS_PART1_DATA0_REG register
- *  Register 0 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
-/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA1_REG register
- *  Register 1 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
-/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA2_REG register
- *  Register 2 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
-/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA3_REG register
- *  Register 3 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
-/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
- *  Optional unique 128-bit ID
- */
-#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
-#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
-
-/** EFUSE_RD_SYS_PART1_DATA4_REG register
- *  Register 4 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
-/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0;
- *  BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
- */
-#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
-#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
-#define EFUSE_BLK_VERSION_MAJOR_S  0
-/** EFUSE_RESERVED_2_130 : R; bitpos: [3:2]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_130    0x00000003U
-#define EFUSE_RESERVED_2_130_M  (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S)
-#define EFUSE_RESERVED_2_130_V  0x00000003U
-#define EFUSE_RESERVED_2_130_S  2
-/** EFUSE_TEMP_CALIB : R; bitpos: [12:4]; default: 0;
- *  Temperature calibration data
- */
-#define EFUSE_TEMP_CALIB    0x000001FFU
-#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
-#define EFUSE_TEMP_CALIB_V  0x000001FFU
-#define EFUSE_TEMP_CALIB_S  4
-/** EFUSE_OCODE : R; bitpos: [20:13]; default: 0;
- *  ADC OCode
- */
-#define EFUSE_OCODE    0x000000FFU
-#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
-#define EFUSE_OCODE_V  0x000000FFU
-#define EFUSE_OCODE_S  13
-/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [28:21]; default: 0;
- *  ADC1 init code at atten0
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN0    0x000000FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_V  0x000000FFU
-#define EFUSE_ADC1_INIT_CODE_ATTEN0_S  21
-/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:29]; default: 0;
- *  ADC1 init code at atten1
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN1    0x00000007U
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_V  0x00000007U
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_S  29
-
-/** EFUSE_RD_SYS_PART1_DATA5_REG register
- *  Register 5 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
-/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [2:0]; default: 0;
- *  ADC1 init code at atten1
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1    0x00000007U
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V  0x00000007U
-#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S  0
-/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [8:3]; default: 0;
- *  ADC1 init code at atten2
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN2    0x0000003FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_M  (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_V  0x0000003FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN2_S  3
-/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [14:9]; default: 0;
- *  ADC1 init code at atten3
- */
-#define EFUSE_ADC1_INIT_CODE_ATTEN3    0x0000003FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_V  0x0000003FU
-#define EFUSE_ADC1_INIT_CODE_ATTEN3_S  9
-/** EFUSE_ADC2_INIT_CODE_ATTEN0 : R; bitpos: [22:15]; default: 0;
- *  ADC2 init code at atten0
- */
-#define EFUSE_ADC2_INIT_CODE_ATTEN0    0x000000FFU
-#define EFUSE_ADC2_INIT_CODE_ATTEN0_M  (EFUSE_ADC2_INIT_CODE_ATTEN0_V << EFUSE_ADC2_INIT_CODE_ATTEN0_S)
-#define EFUSE_ADC2_INIT_CODE_ATTEN0_V  0x000000FFU
-#define EFUSE_ADC2_INIT_CODE_ATTEN0_S  15
-/** EFUSE_ADC2_INIT_CODE_ATTEN1 : R; bitpos: [28:23]; default: 0;
- *  ADC2 init code at atten1
- */
-#define EFUSE_ADC2_INIT_CODE_ATTEN1    0x0000003FU
-#define EFUSE_ADC2_INIT_CODE_ATTEN1_M  (EFUSE_ADC2_INIT_CODE_ATTEN1_V << EFUSE_ADC2_INIT_CODE_ATTEN1_S)
-#define EFUSE_ADC2_INIT_CODE_ATTEN1_V  0x0000003FU
-#define EFUSE_ADC2_INIT_CODE_ATTEN1_S  23
-/** EFUSE_ADC2_INIT_CODE_ATTEN2 : R; bitpos: [31:29]; default: 0;
- *  ADC2 init code at atten2
- */
-#define EFUSE_ADC2_INIT_CODE_ATTEN2    0x00000007U
-#define EFUSE_ADC2_INIT_CODE_ATTEN2_M  (EFUSE_ADC2_INIT_CODE_ATTEN2_V << EFUSE_ADC2_INIT_CODE_ATTEN2_S)
-#define EFUSE_ADC2_INIT_CODE_ATTEN2_V  0x00000007U
-#define EFUSE_ADC2_INIT_CODE_ATTEN2_S  29
-
-/** EFUSE_RD_SYS_PART1_DATA6_REG register
- *  Register 6 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
-/** EFUSE_ADC2_INIT_CODE_ATTEN2_1 : R; bitpos: [2:0]; default: 0;
- *  ADC2 init code at atten2
- */
-#define EFUSE_ADC2_INIT_CODE_ATTEN2_1    0x00000007U
-#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_M  (EFUSE_ADC2_INIT_CODE_ATTEN2_1_V << EFUSE_ADC2_INIT_CODE_ATTEN2_1_S)
-#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_V  0x00000007U
-#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_S  0
-/** EFUSE_ADC2_INIT_CODE_ATTEN3 : R; bitpos: [8:3]; default: 0;
- *  ADC2 init code at atten3
- */
-#define EFUSE_ADC2_INIT_CODE_ATTEN3    0x0000003FU
-#define EFUSE_ADC2_INIT_CODE_ATTEN3_M  (EFUSE_ADC2_INIT_CODE_ATTEN3_V << EFUSE_ADC2_INIT_CODE_ATTEN3_S)
-#define EFUSE_ADC2_INIT_CODE_ATTEN3_V  0x0000003FU
-#define EFUSE_ADC2_INIT_CODE_ATTEN3_S  3
-/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0;
- *  ADC1 calibration voltage at atten0
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN0    0x000000FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_V  0x000000FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN0_S  9
-/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [24:17]; default: 0;
- *  ADC1 calibration voltage at atten1
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN1    0x000000FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_M  (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_V  0x000000FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN1_S  17
-/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [31:25]; default: 0;
- *  ADC1 calibration voltage at atten2
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN2    0x0000007FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_M  (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_V  0x0000007FU
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_S  25
-
-/** EFUSE_RD_SYS_PART1_DATA7_REG register
- *  Register 7 of BLOCK2 (system).
- */
-#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
-/** EFUSE_ADC1_CAL_VOL_ATTEN2_1 : R; bitpos: [0]; default: 0;
- *  ADC1 calibration voltage at atten2
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_1    (BIT(0))
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN2_1_V << EFUSE_ADC1_CAL_VOL_ATTEN2_1_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_V  0x00000001U
-#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_S  0
-/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:1]; default: 0;
- *  ADC1 calibration voltage at atten3
- */
-#define EFUSE_ADC1_CAL_VOL_ATTEN3    0x000000FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_V  0x000000FFU
-#define EFUSE_ADC1_CAL_VOL_ATTEN3_S  1
-/** EFUSE_ADC2_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0;
- *  ADC2 calibration voltage at atten0
- */
-#define EFUSE_ADC2_CAL_VOL_ATTEN0    0x000000FFU
-#define EFUSE_ADC2_CAL_VOL_ATTEN0_M  (EFUSE_ADC2_CAL_VOL_ATTEN0_V << EFUSE_ADC2_CAL_VOL_ATTEN0_S)
-#define EFUSE_ADC2_CAL_VOL_ATTEN0_V  0x000000FFU
-#define EFUSE_ADC2_CAL_VOL_ATTEN0_S  9
-/** EFUSE_ADC2_CAL_VOL_ATTEN1 : R; bitpos: [23:17]; default: 0;
- *  ADC2 calibration voltage at atten1
- */
-#define EFUSE_ADC2_CAL_VOL_ATTEN1    0x0000007FU
-#define EFUSE_ADC2_CAL_VOL_ATTEN1_M  (EFUSE_ADC2_CAL_VOL_ATTEN1_V << EFUSE_ADC2_CAL_VOL_ATTEN1_S)
-#define EFUSE_ADC2_CAL_VOL_ATTEN1_V  0x0000007FU
-#define EFUSE_ADC2_CAL_VOL_ATTEN1_S  17
-/** EFUSE_ADC2_CAL_VOL_ATTEN2 : R; bitpos: [30:24]; default: 0;
- *  ADC2 calibration voltage at atten2
- */
-#define EFUSE_ADC2_CAL_VOL_ATTEN2    0x0000007FU
-#define EFUSE_ADC2_CAL_VOL_ATTEN2_M  (EFUSE_ADC2_CAL_VOL_ATTEN2_V << EFUSE_ADC2_CAL_VOL_ATTEN2_S)
-#define EFUSE_ADC2_CAL_VOL_ATTEN2_V  0x0000007FU
-#define EFUSE_ADC2_CAL_VOL_ATTEN2_S  24
-/** EFUSE_RESERVED_2_255 : R; bitpos: [31]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_2_255    (BIT(31))
-#define EFUSE_RESERVED_2_255_M  (EFUSE_RESERVED_2_255_V << EFUSE_RESERVED_2_255_S)
-#define EFUSE_RESERVED_2_255_V  0x00000001U
-#define EFUSE_RESERVED_2_255_S  31
-
-/** EFUSE_RD_USR_DATA0_REG register
- *  Register 0 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
-/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA0    0xFFFFFFFFU
-#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
-#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA0_S  0
-
-/** EFUSE_RD_USR_DATA1_REG register
- *  Register 1 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
-/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA1    0xFFFFFFFFU
-#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
-#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA1_S  0
-
-/** EFUSE_RD_USR_DATA2_REG register
- *  Register 2 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
-/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA2    0xFFFFFFFFU
-#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
-#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA2_S  0
-
-/** EFUSE_RD_USR_DATA3_REG register
- *  Register 3 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
-/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA3    0xFFFFFFFFU
-#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
-#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA3_S  0
-
-/** EFUSE_RD_USR_DATA4_REG register
- *  Register 4 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
-/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA4    0xFFFFFFFFU
-#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
-#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA4_S  0
-
-/** EFUSE_RD_USR_DATA5_REG register
- *  Register 5 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
-/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of BLOCK3 (user).
- */
-#define EFUSE_USR_DATA5    0xFFFFFFFFU
-#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
-#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
-#define EFUSE_USR_DATA5_S  0
-
-/** EFUSE_RD_USR_DATA6_REG register
- *  Register 6 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
-/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_192    0x000000FFU
-#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
-#define EFUSE_RESERVED_3_192_V  0x000000FFU
-#define EFUSE_RESERVED_3_192_S  0
-/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
-#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_S  8
-
-/** EFUSE_RD_USR_DATA7_REG register
- *  Register 7 of BLOCK3 (user).
- */
-#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
-/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
- *  Custom MAC
- */
-#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
-#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
-#define EFUSE_CUSTOM_MAC_1_S  0
-/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
- *  reserved
- */
-#define EFUSE_RESERVED_3_248    0x000000FFU
-#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
-#define EFUSE_RESERVED_3_248_V  0x000000FFU
-#define EFUSE_RESERVED_3_248_S  24
-
-/** EFUSE_RD_KEY0_DATA0_REG register
- *  Register 0 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
-/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
-#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA0_S  0
-
-/** EFUSE_RD_KEY0_DATA1_REG register
- *  Register 1 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
-/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
-#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA1_S  0
-
-/** EFUSE_RD_KEY0_DATA2_REG register
- *  Register 2 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
-/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
-#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA2_S  0
-
-/** EFUSE_RD_KEY0_DATA3_REG register
- *  Register 3 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
-/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
-#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA3_S  0
-
-/** EFUSE_RD_KEY0_DATA4_REG register
- *  Register 4 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
-/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
-#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA4_S  0
-
-/** EFUSE_RD_KEY0_DATA5_REG register
- *  Register 5 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
-/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
-#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA5_S  0
-
-/** EFUSE_RD_KEY0_DATA6_REG register
- *  Register 6 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
-/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
-#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA6_S  0
-
-/** EFUSE_RD_KEY0_DATA7_REG register
- *  Register 7 of BLOCK4 (KEY0).
- */
-#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
-/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY0.
- */
-#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
-#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY0_DATA7_S  0
-
-/** EFUSE_RD_KEY1_DATA0_REG register
- *  Register 0 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
-/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
-#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA0_S  0
-
-/** EFUSE_RD_KEY1_DATA1_REG register
- *  Register 1 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
-/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
-#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA1_S  0
-
-/** EFUSE_RD_KEY1_DATA2_REG register
- *  Register 2 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
-/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
-#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA2_S  0
-
-/** EFUSE_RD_KEY1_DATA3_REG register
- *  Register 3 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
-/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
-#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA3_S  0
-
-/** EFUSE_RD_KEY1_DATA4_REG register
- *  Register 4 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
-/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
-#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA4_S  0
-
-/** EFUSE_RD_KEY1_DATA5_REG register
- *  Register 5 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
-/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
-#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA5_S  0
-
-/** EFUSE_RD_KEY1_DATA6_REG register
- *  Register 6 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
-/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
-#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA6_S  0
-
-/** EFUSE_RD_KEY1_DATA7_REG register
- *  Register 7 of BLOCK5 (KEY1).
- */
-#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
-/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY1.
- */
-#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
-#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY1_DATA7_S  0
-
-/** EFUSE_RD_KEY2_DATA0_REG register
- *  Register 0 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
-/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
-#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA0_S  0
-
-/** EFUSE_RD_KEY2_DATA1_REG register
- *  Register 1 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
-/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
-#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA1_S  0
-
-/** EFUSE_RD_KEY2_DATA2_REG register
- *  Register 2 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
-/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
-#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA2_S  0
-
-/** EFUSE_RD_KEY2_DATA3_REG register
- *  Register 3 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
-/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
-#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA3_S  0
-
-/** EFUSE_RD_KEY2_DATA4_REG register
- *  Register 4 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
-/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
-#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA4_S  0
-
-/** EFUSE_RD_KEY2_DATA5_REG register
- *  Register 5 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
-/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
-#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA5_S  0
-
-/** EFUSE_RD_KEY2_DATA6_REG register
- *  Register 6 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
-/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
-#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA6_S  0
-
-/** EFUSE_RD_KEY2_DATA7_REG register
- *  Register 7 of BLOCK6 (KEY2).
- */
-#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
-/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY2.
- */
-#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
-#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY2_DATA7_S  0
-
-/** EFUSE_RD_KEY3_DATA0_REG register
- *  Register 0 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
-/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
-#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA0_S  0
-
-/** EFUSE_RD_KEY3_DATA1_REG register
- *  Register 1 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
-/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
-#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA1_S  0
-
-/** EFUSE_RD_KEY3_DATA2_REG register
- *  Register 2 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
-/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
-#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA2_S  0
-
-/** EFUSE_RD_KEY3_DATA3_REG register
- *  Register 3 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
-/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
-#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA3_S  0
-
-/** EFUSE_RD_KEY3_DATA4_REG register
- *  Register 4 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
-/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
-#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA4_S  0
-
-/** EFUSE_RD_KEY3_DATA5_REG register
- *  Register 5 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
-/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
-#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA5_S  0
-
-/** EFUSE_RD_KEY3_DATA6_REG register
- *  Register 6 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
-/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
-#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA6_S  0
-
-/** EFUSE_RD_KEY3_DATA7_REG register
- *  Register 7 of BLOCK7 (KEY3).
- */
-#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
-/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY3.
- */
-#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
-#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY3_DATA7_S  0
-
-/** EFUSE_RD_KEY4_DATA0_REG register
- *  Register 0 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
-/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
-#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA0_S  0
-
-/** EFUSE_RD_KEY4_DATA1_REG register
- *  Register 1 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
-/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
-#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA1_S  0
-
-/** EFUSE_RD_KEY4_DATA2_REG register
- *  Register 2 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
-/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
-#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA2_S  0
-
-/** EFUSE_RD_KEY4_DATA3_REG register
- *  Register 3 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
-/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
-#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA3_S  0
-
-/** EFUSE_RD_KEY4_DATA4_REG register
- *  Register 4 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
-/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
-#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA4_S  0
-
-/** EFUSE_RD_KEY4_DATA5_REG register
- *  Register 5 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
-/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
-#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA5_S  0
-
-/** EFUSE_RD_KEY4_DATA6_REG register
- *  Register 6 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
-/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
-#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA6_S  0
-
-/** EFUSE_RD_KEY4_DATA7_REG register
- *  Register 7 of BLOCK8 (KEY4).
- */
-#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
-/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY4.
- */
-#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
-#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY4_DATA7_S  0
-
-/** EFUSE_RD_KEY5_DATA0_REG register
- *  Register 0 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
-/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the zeroth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
-#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA0_S  0
-
-/** EFUSE_RD_KEY5_DATA1_REG register
- *  Register 1 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
-/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the first 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
-#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA1_S  0
-
-/** EFUSE_RD_KEY5_DATA2_REG register
- *  Register 2 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
-/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the second 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
-#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA2_S  0
-
-/** EFUSE_RD_KEY5_DATA3_REG register
- *  Register 3 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
-/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the third 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
-#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA3_S  0
-
-/** EFUSE_RD_KEY5_DATA4_REG register
- *  Register 4 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
-/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fourth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
-#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA4_S  0
-
-/** EFUSE_RD_KEY5_DATA5_REG register
- *  Register 5 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
-/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the fifth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
-#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA5_S  0
-
-/** EFUSE_RD_KEY5_DATA6_REG register
- *  Register 6 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
-/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the sixth 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
-#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA6_S  0
-
-/** EFUSE_RD_KEY5_DATA7_REG register
- *  Register 7 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
-/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the seventh 32 bits of KEY5.
- */
-#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
-#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
-#define EFUSE_KEY5_DATA7_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA0_REG register
- *  Register 0 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
-/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 0th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
-#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_0_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA1_REG register
- *  Register 1 of BLOCK9 (KEY5).
- */
-#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
-/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 1st 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
-#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_1_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA2_REG register
- *  Register 2 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
-/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 2nd 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
-#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_2_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA3_REG register
- *  Register 3 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
-/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 3rd 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
-#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_3_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA4_REG register
- *  Register 4 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
-/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 4th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
-#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_4_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA5_REG register
- *  Register 5 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
-/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 5th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
-#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_5_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA6_REG register
- *  Register 6 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
-/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 6th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
-#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_6_S  0
-
-/** EFUSE_RD_SYS_PART2_DATA7_REG register
- *  Register 7 of BLOCK10 (system).
- */
-#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
-/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
- *  Stores the 7th 32 bits of the 2nd part of system data.
- */
-#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
-#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
-#define EFUSE_SYS_DATA_PART2_7_S  0
-
-/** EFUSE_RD_REPEAT_ERR0_REG register
- *  Programming error record register 0 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
-/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_RD_DIS_ERR    0x0000007FU
-#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
-#define EFUSE_RD_DIS_ERR_V  0x0000007FU
-#define EFUSE_RD_DIS_ERR_S  0
-/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_RTC_RAM_BOOT_ERR    (BIT(7))
-#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M  (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S)
-#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S  7
-/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
-#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
-#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_ICACHE_ERR_S  8
-/** EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DCACHE_ERR    (BIT(9))
-#define EFUSE_DIS_DCACHE_ERR_M  (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S)
-#define EFUSE_DIS_DCACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_DCACHE_ERR_S  9
-/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(10))
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  10
-/** EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR    (BIT(11))
-#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S  11
-/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
-/** EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_USB_ERR    (BIT(13))
-#define EFUSE_DIS_USB_ERR_M  (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S)
-#define EFUSE_DIS_USB_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_ERR_S  13
-/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_CAN_ERR    (BIT(14))
-#define EFUSE_DIS_CAN_ERR_M  (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S)
-#define EFUSE_DIS_CAN_ERR_V  0x00000001U
-#define EFUSE_DIS_CAN_ERR_S  14
-/** EFUSE_DIS_APP_CPU_ERR : RO; bitpos: [15]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_APP_CPU_ERR    (BIT(15))
-#define EFUSE_DIS_APP_CPU_ERR_M  (EFUSE_DIS_APP_CPU_ERR_V << EFUSE_DIS_APP_CPU_ERR_S)
-#define EFUSE_DIS_APP_CPU_ERR_V  0x00000001U
-#define EFUSE_DIS_APP_CPU_ERR_S  15
-/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
-#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
-#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
-/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
-#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
-#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_PAD_JTAG_ERR_S  19
-/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
-/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_USB_DREFH_ERR    0x00000003U
-#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
-#define EFUSE_USB_DREFH_ERR_V  0x00000003U
-#define EFUSE_USB_DREFH_ERR_S  21
-/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_USB_DREFL_ERR    0x00000003U
-#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
-#define EFUSE_USB_DREFL_ERR_V  0x00000003U
-#define EFUSE_USB_DREFL_ERR_S  23
-/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
-#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
-#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
-#define EFUSE_USB_EXCHG_PINS_ERR_S  25
-/** EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [26]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_EXT_PHY_ENABLE_ERR    (BIT(26))
-#define EFUSE_EXT_PHY_ENABLE_ERR_M  (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S)
-#define EFUSE_EXT_PHY_ENABLE_ERR_V  0x00000001U
-#define EFUSE_EXT_PHY_ENABLE_ERR_S  26
-/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_BTLC_GPIO_ENABLE_ERR    0x00000003U
-#define EFUSE_BTLC_GPIO_ENABLE_ERR_M  (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S)
-#define EFUSE_BTLC_GPIO_ENABLE_ERR_V  0x00000003U
-#define EFUSE_BTLC_GPIO_ENABLE_ERR_S  27
-/** EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_MODECURLIM_ERR    (BIT(29))
-#define EFUSE_VDD_SPI_MODECURLIM_ERR_M  (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S)
-#define EFUSE_VDD_SPI_MODECURLIM_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_MODECURLIM_ERR_S  29
-/** EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_DREFH_ERR    0x00000003U
-#define EFUSE_VDD_SPI_DREFH_ERR_M  (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S)
-#define EFUSE_VDD_SPI_DREFH_ERR_V  0x00000003U
-#define EFUSE_VDD_SPI_DREFH_ERR_S  30
-
-/** EFUSE_RD_REPEAT_ERR1_REG register
- *  Programming error record register 1 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
-/** EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_DREFM_ERR    0x00000003U
-#define EFUSE_VDD_SPI_DREFM_ERR_M  (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S)
-#define EFUSE_VDD_SPI_DREFM_ERR_V  0x00000003U
-#define EFUSE_VDD_SPI_DREFM_ERR_S  0
-/** EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_DREFL_ERR    0x00000003U
-#define EFUSE_VDD_SPI_DREFL_ERR_M  (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S)
-#define EFUSE_VDD_SPI_DREFL_ERR_V  0x00000003U
-#define EFUSE_VDD_SPI_DREFL_ERR_S  2
-/** EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_XPD_ERR    (BIT(4))
-#define EFUSE_VDD_SPI_XPD_ERR_M  (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S)
-#define EFUSE_VDD_SPI_XPD_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_XPD_ERR_S  4
-/** EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_TIEH_ERR    (BIT(5))
-#define EFUSE_VDD_SPI_TIEH_ERR_M  (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S)
-#define EFUSE_VDD_SPI_TIEH_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_TIEH_ERR_S  5
-/** EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_FORCE_ERR    (BIT(6))
-#define EFUSE_VDD_SPI_FORCE_ERR_M  (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S)
-#define EFUSE_VDD_SPI_FORCE_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_FORCE_ERR_S  6
-/** EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_EN_INIT_ERR    (BIT(7))
-#define EFUSE_VDD_SPI_EN_INIT_ERR_M  (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S)
-#define EFUSE_VDD_SPI_EN_INIT_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_EN_INIT_ERR_S  7
-/** EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_ENCURLIM_ERR    (BIT(8))
-#define EFUSE_VDD_SPI_ENCURLIM_ERR_M  (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S)
-#define EFUSE_VDD_SPI_ENCURLIM_ERR_V  0x00000001U
-#define EFUSE_VDD_SPI_ENCURLIM_ERR_S  8
-/** EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_DCURLIM_ERR    0x00000007U
-#define EFUSE_VDD_SPI_DCURLIM_ERR_M  (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S)
-#define EFUSE_VDD_SPI_DCURLIM_ERR_V  0x00000007U
-#define EFUSE_VDD_SPI_DCURLIM_ERR_S  9
-/** EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_INIT_ERR    0x00000003U
-#define EFUSE_VDD_SPI_INIT_ERR_M  (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S)
-#define EFUSE_VDD_SPI_INIT_ERR_V  0x00000003U
-#define EFUSE_VDD_SPI_INIT_ERR_S  12
-/** EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_VDD_SPI_DCAP_ERR    0x00000003U
-#define EFUSE_VDD_SPI_DCAP_ERR_M  (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S)
-#define EFUSE_VDD_SPI_DCAP_ERR_V  0x00000003U
-#define EFUSE_VDD_SPI_DCAP_ERR_S  14
-/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
-#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
-#define EFUSE_WDT_DELAY_SEL_ERR_S  16
-/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
-#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
-/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
-/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
-/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
-/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
-#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_0_ERR_S  24
-/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
-#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_1_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR2_REG register
- *  Programming error record register 2 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
-/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
-#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_2_ERR_S  0
-/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
-#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_3_ERR_S  4
-/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
-#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_4_ERR_S  8
-/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
-#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
-#define EFUSE_KEY_PURPOSE_5_ERR_S  12
-/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [19:16]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_RPT4_RESERVED0_ERR    0x0000000FU
-#define EFUSE_RPT4_RESERVED0_ERR_M  (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S)
-#define EFUSE_RPT4_RESERVED0_ERR_V  0x0000000FU
-#define EFUSE_RPT4_RESERVED0_ERR_S  16
-/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
-#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
-#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_EN_ERR_S  20
-/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
-#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
-/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [22]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_USB_JTAG_ERR    (BIT(22))
-#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
-#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_JTAG_ERR_S  22
-/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [23]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_USB_DEVICE_ERR    (BIT(23))
-#define EFUSE_DIS_USB_DEVICE_ERR_M  (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S)
-#define EFUSE_DIS_USB_DEVICE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_DEVICE_ERR_S  23
-/** EFUSE_STRAP_JTAG_SEL_ERR : RO; bitpos: [24]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_STRAP_JTAG_SEL_ERR    (BIT(24))
-#define EFUSE_STRAP_JTAG_SEL_ERR_M  (EFUSE_STRAP_JTAG_SEL_ERR_V << EFUSE_STRAP_JTAG_SEL_ERR_S)
-#define EFUSE_STRAP_JTAG_SEL_ERR_V  0x00000001U
-#define EFUSE_STRAP_JTAG_SEL_ERR_S  24
-/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
-#define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
-#define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
-#define EFUSE_USB_PHY_SEL_ERR_S  25
-/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [27:26]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_POWER_GLITCH_DSENSE_ERR    0x00000003U
-#define EFUSE_POWER_GLITCH_DSENSE_ERR_M  (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S)
-#define EFUSE_POWER_GLITCH_DSENSE_ERR_V  0x00000003U
-#define EFUSE_POWER_GLITCH_DSENSE_ERR_S  26
-/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
-#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
-#define EFUSE_FLASH_TPUW_ERR_S  28
-
-/** EFUSE_RD_REPEAT_ERR3_REG register
- *  Programming error record register 3 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
-/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
-/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR    (BIT(1))
-#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M  (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S)
-#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V  0x00000001U
-#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S  1
-/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_UART_PRINT_CHANNEL_ERR    (BIT(2))
-#define EFUSE_UART_PRINT_CHANNEL_ERR_M  (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S)
-#define EFUSE_UART_PRINT_CHANNEL_ERR_V  0x00000001U
-#define EFUSE_UART_PRINT_CHANNEL_ERR_S  2
-/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_ECC_MODE_ERR    (BIT(3))
-#define EFUSE_FLASH_ECC_MODE_ERR_M  (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S)
-#define EFUSE_FLASH_ECC_MODE_ERR_V  0x00000001U
-#define EFUSE_FLASH_ECC_MODE_ERR_S  3
-/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR    (BIT(4))
-#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S)
-#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V  0x00000001U
-#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S  4
-/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
-#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
-/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
-#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
-#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
-/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_PIN_POWER_SELECTION_ERR    (BIT(8))
-#define EFUSE_PIN_POWER_SELECTION_ERR_M  (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S)
-#define EFUSE_PIN_POWER_SELECTION_ERR_V  0x00000001U
-#define EFUSE_PIN_POWER_SELECTION_ERR_S  8
-/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_TYPE_ERR    (BIT(9))
-#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
-#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
-#define EFUSE_FLASH_TYPE_ERR_S  9
-/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
-#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
-#define EFUSE_FLASH_PAGE_SIZE_ERR_S  10
-/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_FLASH_ECC_EN_ERR    (BIT(12))
-#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
-#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
-#define EFUSE_FLASH_ECC_EN_ERR_S  12
-/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
-#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
-#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
-#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
-/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
-#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
-#define EFUSE_SECURE_VERSION_ERR_S  14
-/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [30]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_POWERGLITCH_EN_ERR    (BIT(30))
-#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
-#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
-#define EFUSE_POWERGLITCH_EN_ERR_S  30
-/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31]; default: 0;
- *  Reserved.
- */
-#define EFUSE_RPT4_RESERVED1_ERR    (BIT(31))
-#define EFUSE_RPT4_RESERVED1_ERR_M  (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S)
-#define EFUSE_RPT4_RESERVED1_ERR_V  0x00000001U
-#define EFUSE_RPT4_RESERVED1_ERR_S  31
-
-/** EFUSE_RD_REPEAT_ERR4_REG register
- *  Programming error record register 4 of BLOCK0.
- */
-#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
-/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [23:0]; default: 0;
- *  If any bits in this filed are 1, then it indicates a programming error.
- */
-#define EFUSE_RPT4_RESERVED2_ERR    0x00FFFFFFU
-#define EFUSE_RPT4_RESERVED2_ERR_M  (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S)
-#define EFUSE_RPT4_RESERVED2_ERR_V  0x00FFFFFFU
-#define EFUSE_RPT4_RESERVED2_ERR_S  0
-
-/** EFUSE_RD_RS_ERR0_REG register
- *  Programming error record register 0 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
-/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
-#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
-#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
-#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
-/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_MAC_SPI_8M_FAIL    (BIT(3))
-#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
-#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
-#define EFUSE_MAC_SPI_8M_FAIL_S  3
-/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART1_NUM    0x00000007U
-#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
-#define EFUSE_SYS_PART1_NUM_V  0x00000007U
-#define EFUSE_SYS_PART1_NUM_S  4
-/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part1 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART1_FAIL    (BIT(7))
-#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
-#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART1_FAIL_S  7
-/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
-#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
-#define EFUSE_USR_DATA_ERR_NUM_S  8
-/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
- *  0: Means no failure and that the user data is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_USR_DATA_FAIL    (BIT(11))
-#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
-#define EFUSE_USR_DATA_FAIL_V  0x00000001U
-#define EFUSE_USR_DATA_FAIL_S  11
-/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY0_ERR_NUM    0x00000007U
-#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
-#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY0_ERR_NUM_S  12
-/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
- *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
- *  key0 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY0_FAIL    (BIT(15))
-#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
-#define EFUSE_KEY0_FAIL_V  0x00000001U
-#define EFUSE_KEY0_FAIL_S  15
-/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY1_ERR_NUM    0x00000007U
-#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
-#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY1_ERR_NUM_S  16
-/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
- *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
- *  key1 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY1_FAIL    (BIT(19))
-#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
-#define EFUSE_KEY1_FAIL_V  0x00000001U
-#define EFUSE_KEY1_FAIL_S  19
-/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY2_ERR_NUM    0x00000007U
-#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
-#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY2_ERR_NUM_S  20
-/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
- *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
- *  key2 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY2_FAIL    (BIT(23))
-#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
-#define EFUSE_KEY2_FAIL_V  0x00000001U
-#define EFUSE_KEY2_FAIL_S  23
-/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY3_ERR_NUM    0x00000007U
-#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
-#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY3_ERR_NUM_S  24
-/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
- *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
- *  key3 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY3_FAIL    (BIT(27))
-#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
-#define EFUSE_KEY3_FAIL_V  0x00000001U
-#define EFUSE_KEY3_FAIL_S  27
-/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY4_ERR_NUM    0x00000007U
-#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
-#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY4_ERR_NUM_S  28
-/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
- *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
- *  key4 failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY4_FAIL    (BIT(31))
-#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
-#define EFUSE_KEY4_FAIL_V  0x00000001U
-#define EFUSE_KEY4_FAIL_S  31
-
-/** EFUSE_RD_RS_ERR1_REG register
- *  Programming error record register 1 of BLOCK1-10.
- */
-#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
-/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_KEY5_ERR_NUM    0x00000007U
-#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
-#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
-#define EFUSE_KEY5_ERR_NUM_S  0
-/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
- *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
- *  user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_KEY5_FAIL    (BIT(3))
-#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
-#define EFUSE_KEY5_FAIL_V  0x00000001U
-#define EFUSE_KEY5_FAIL_S  3
-/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
- *  The value of this signal means the number of error bytes.
- */
-#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
-#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
-#define EFUSE_SYS_PART2_ERR_NUM_S  4
-/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
- *  0: Means no failure and that the data of system part2 is reliable 1: Means that
- *  programming user data failed and the number of error bytes is over 6.
- */
-#define EFUSE_SYS_PART2_FAIL    (BIT(7))
-#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
-#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
-#define EFUSE_SYS_PART2_FAIL_S  7
-
-/** EFUSE_CLK_REG register
- *  eFuse clcok configuration register.
- */
-#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
-/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
- *  Set this bit to force eFuse SRAM into power-saving mode.
- */
-#define EFUSE_EFUSE_MEM_FORCE_PD    (BIT(0))
-#define EFUSE_EFUSE_MEM_FORCE_PD_M  (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S)
-#define EFUSE_EFUSE_MEM_FORCE_PD_V  0x00000001U
-#define EFUSE_EFUSE_MEM_FORCE_PD_S  0
-/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
- *  Set this bit and force to activate clock signal of eFuse SRAM.
- */
-#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
-#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
-#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
-#define EFUSE_MEM_CLK_FORCE_ON_S  1
-/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
- *  Set this bit to force eFuse SRAM into working mode.
- */
-#define EFUSE_EFUSE_MEM_FORCE_PU    (BIT(2))
-#define EFUSE_EFUSE_MEM_FORCE_PU_M  (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S)
-#define EFUSE_EFUSE_MEM_FORCE_PU_V  0x00000001U
-#define EFUSE_EFUSE_MEM_FORCE_PU_S  2
-/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit and force to enable clock signal of eFuse memory.
- */
-#define EFUSE_CLK_EN    (BIT(16))
-#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
-#define EFUSE_CLK_EN_V  0x00000001U
-#define EFUSE_CLK_EN_S  16
-
-/** EFUSE_CONF_REG register
- *  eFuse operation mode configuraiton register
- */
-#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
-/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
- *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
- */
-#define EFUSE_OP_CODE    0x0000FFFFU
-#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
-#define EFUSE_OP_CODE_V  0x0000FFFFU
-#define EFUSE_OP_CODE_S  0
-
-/** EFUSE_STATUS_REG register
- *  eFuse status register.
- */
-#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
-/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
- *  Indicates the state of the eFuse state machine.
- */
-#define EFUSE_STATE    0x0000000FU
-#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
-#define EFUSE_STATE_V  0x0000000FU
-#define EFUSE_STATE_S  0
-/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
- *  The value of OTP_LOAD_SW.
- */
-#define EFUSE_OTP_LOAD_SW    (BIT(4))
-#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
-#define EFUSE_OTP_LOAD_SW_V  0x00000001U
-#define EFUSE_OTP_LOAD_SW_S  4
-/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
- *  The value of OTP_VDDQ_C_SYNC2.
- */
-#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
-#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
-#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
-#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
-/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
- *  The value of OTP_STROBE_SW.
- */
-#define EFUSE_OTP_STROBE_SW    (BIT(6))
-#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
-#define EFUSE_OTP_STROBE_SW_V  0x00000001U
-#define EFUSE_OTP_STROBE_SW_S  6
-/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
- *  The value of OTP_CSB_SW.
- */
-#define EFUSE_OTP_CSB_SW    (BIT(7))
-#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
-#define EFUSE_OTP_CSB_SW_V  0x00000001U
-#define EFUSE_OTP_CSB_SW_S  7
-/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
- *  The value of OTP_PGENB_SW.
- */
-#define EFUSE_OTP_PGENB_SW    (BIT(8))
-#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
-#define EFUSE_OTP_PGENB_SW_V  0x00000001U
-#define EFUSE_OTP_PGENB_SW_S  8
-/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
- *  The value of OTP_VDDQ_IS_SW.
- */
-#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
-#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
-#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
-#define EFUSE_OTP_VDDQ_IS_SW_S  9
-/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0;
- *  Indicates the number of error bits during programming BLOCK0.
- */
-#define EFUSE_REPEAT_ERR_CNT    0x000000FFU
-#define EFUSE_REPEAT_ERR_CNT_M  (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S)
-#define EFUSE_REPEAT_ERR_CNT_V  0x000000FFU
-#define EFUSE_REPEAT_ERR_CNT_S  10
-
-/** EFUSE_CMD_REG register
- *  eFuse command register.
- */
-#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
-/** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0;
- *  Set this bit to send read command.
- */
-#define EFUSE_READ_CMD    (BIT(0))
-#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
-#define EFUSE_READ_CMD_V  0x00000001U
-#define EFUSE_READ_CMD_S  0
-/** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0;
- *  Set this bit to send programming command.
- */
-#define EFUSE_PGM_CMD    (BIT(1))
-#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
-#define EFUSE_PGM_CMD_V  0x00000001U
-#define EFUSE_PGM_CMD_S  1
-/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
- *  The serial number of the block to be programmed. Value 0-10 corresponds to block
- *  number 0-10, respectively.
- */
-#define EFUSE_BLK_NUM    0x0000000FU
-#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
-#define EFUSE_BLK_NUM_V  0x0000000FU
-#define EFUSE_BLK_NUM_S  2
-
-/** EFUSE_INT_RAW_REG register
- *  eFuse raw interrupt register.
- */
-#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
-/** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0;
- *  The raw bit signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
-#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
-#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_READ_DONE_INT_RAW_S  0
-/** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0;
- *  The raw bit signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
-#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
-#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_RAW_S  1
-
-/** EFUSE_INT_ST_REG register
- *  eFuse interrupt status register.
- */
-#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
-/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
- *  The status signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ST    (BIT(0))
-#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
-#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ST_S  0
-/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
- *  The status signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
-#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ST_S  1
-
-/** EFUSE_INT_ENA_REG register
- *  eFuse interrupt enable register.
- */
-#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
-/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
-#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
-#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_READ_DONE_INT_ENA_S  0
-/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
-#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
-#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_ENA_S  1
-
-/** EFUSE_INT_CLR_REG register
- *  eFuse interrupt clear register.
- */
-#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
-/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
- *  The clear signal for read_done interrupt.
- */
-#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
-#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
-#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_READ_DONE_INT_CLR_S  0
-/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
- *  The clear signal for pgm_done interrupt.
- */
-#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
-#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
-#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
-#define EFUSE_PGM_DONE_INT_CLR_S  1
-
-/** EFUSE_DAC_CONF_REG register
- *  Controls the eFuse programming voltage.
- */
-#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
-/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
- *  Controls the division factor of the rising clock of the programming voltage.
- */
-#define EFUSE_DAC_CLK_DIV    0x000000FFU
-#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
-#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
-#define EFUSE_DAC_CLK_DIV_S  0
-/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
- *  Don't care.
- */
-#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
-#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
-#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
-#define EFUSE_DAC_CLK_PAD_SEL_S  8
-/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
- *  Controls the rising period of the programming voltage.
- */
-#define EFUSE_DAC_NUM    0x000000FFU
-#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
-#define EFUSE_DAC_NUM_V  0x000000FFU
-#define EFUSE_DAC_NUM_S  9
-/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
- *  Reduces the power supply of the programming voltage.
- */
-#define EFUSE_OE_CLR    (BIT(17))
-#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
-#define EFUSE_OE_CLR_V  0x00000001U
-#define EFUSE_OE_CLR_S  17
-
-/** EFUSE_RD_TIM_CONF_REG register
- *  Configures read timing parameters.
- */
-#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
-/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
- *  Configures the initial read time of eFuse.
- */
-#define EFUSE_READ_INIT_NUM    0x000000FFU
-#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
-#define EFUSE_READ_INIT_NUM_V  0x000000FFU
-#define EFUSE_READ_INIT_NUM_S  24
-
-/** EFUSE_WR_TIM_CONF1_REG register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4)
-/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368;
- *  Configures the power up time for VDDQ.
- */
-#define EFUSE_PWR_ON_NUM    0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
-#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_ON_NUM_S  8
-
-/** EFUSE_WR_TIM_CONF2_REG register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8)
-/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
- *  Configures the power outage time for VDDQ.
- */
-#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
-#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
-#define EFUSE_PWR_OFF_NUM_S  0
-
-/** EFUSE_DATE_REG register
- *  eFuse version register.
- */
-#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
-/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34607760;
- *  Stores eFuse version.
- */
-#define EFUSE_DATE    0x0FFFFFFFU
-#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
-#define EFUSE_DATE_V  0x0FFFFFFFU
-#define EFUSE_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h
deleted file mode 100644
index a3c589f543c..00000000000
--- a/components/soc/esp32s3/include/soc/efuse_struct.h
+++ /dev/null
@@ -1,2535 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: PGM Data Register */
-/** Type of pgm_data0 register
- *  Register 0 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 0th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_data0_reg_t;
-
-/** Type of pgm_data1 register
- *  Register 1 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 1st 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_data1_reg_t;
-
-/** Type of pgm_data2 register
- *  Register 2 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 2nd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_data2_reg_t;
-
-/** Type of pgm_data3 register
- *  Register 3 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 3rd 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_3:32;
-    };
-    uint32_t val;
-} efuse_pgm_data3_reg_t;
-
-/** Type of pgm_data4 register
- *  Register 4 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 4th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_4:32;
-    };
-    uint32_t val;
-} efuse_pgm_data4_reg_t;
-
-/** Type of pgm_data5 register
- *  Register 5 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 5th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_5:32;
-    };
-    uint32_t val;
-} efuse_pgm_data5_reg_t;
-
-/** Type of pgm_data6 register
- *  Register 6 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 6th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_6:32;
-    };
-    uint32_t val;
-} efuse_pgm_data6_reg_t;
-
-/** Type of pgm_data7 register
- *  Register 7 that stores data to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 7th 32-bit data to be programmed.
-         */
-        uint32_t pgm_data_7:32;
-    };
-    uint32_t val;
-} efuse_pgm_data7_reg_t;
-
-/** Type of pgm_check_value0 register
- *  Register 0 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 0th 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_0:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value0_reg_t;
-
-/** Type of pgm_check_value1 register
- *  Register 1 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 1st 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_1:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value1_reg_t;
-
-/** Type of pgm_check_value2 register
- *  Register 2 that stores the RS code to be programmed.
- */
-typedef union {
-    struct {
-        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
-         *  The content of the 2nd 32-bit RS code to be programmed.
-         */
-        uint32_t pgm_rs_data_2:32;
-    };
-    uint32_t val;
-} efuse_pgm_check_value2_reg_t;
-
-
-/** Group: Read Data Register */
-/** Type of rd_wr_dis register
- *  BLOCK0 data register 0.
- */
-typedef union {
-    struct {
-        /** wr_dis : RO; bitpos: [31:0]; default: 0;
-         *  Disable programming of individual eFuses.
-         */
-        uint32_t wr_dis:32;
-    };
-    uint32_t val;
-} efuse_rd_wr_dis_reg_t;
-
-/** Type of rd_repeat_data0 register
- *  BLOCK0 data register 1.
- */
-typedef union {
-    struct {
-        /** rd_dis : RO; bitpos: [6:0]; default: 0;
-         *  Set this bit to disable reading from BlOCK4-10.
-         */
-        uint32_t rd_dis:7;
-        /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0;
-         *  Set this bit to disable boot from RTC RAM.
-         */
-        uint32_t dis_rtc_ram_boot:1;
-        /** dis_icache : RO; bitpos: [8]; default: 0;
-         *  Set this bit to disable Icache.
-         */
-        uint32_t dis_icache:1;
-        /** dis_dcache : RO; bitpos: [9]; default: 0;
-         *  Set this bit to disable Dcache.
-         */
-        uint32_t dis_dcache:1;
-        /** dis_download_icache : RO; bitpos: [10]; default: 0;
-         *  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6,
-         *  7).
-         */
-        uint32_t dis_download_icache:1;
-        /** dis_download_dcache : RO; bitpos: [11]; default: 0;
-         *  Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6,
-         *  7).
-         */
-        uint32_t dis_download_dcache:1;
-        /** dis_force_download : RO; bitpos: [12]; default: 0;
-         *  Set this bit to disable the function that forces chip into download mode.
-         */
-        uint32_t dis_force_download:1;
-        /** dis_usb_otg : RO; bitpos: [13]; default: 0;
-         *  Set this bit to disable USB function.
-         */
-        uint32_t dis_usb_otg:1;
-        /** dis_twai : RO; bitpos: [14]; default: 0;
-         *  Set this bit to disable CAN function.
-         */
-        uint32_t dis_twai:1;
-        /** dis_app_cpu : RO; bitpos: [15]; default: 0;
-         *  Disable app cpu.
-         */
-        uint32_t dis_app_cpu:1;
-        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
-         *  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG
-         *  can be enabled in HMAC module.
-         */
-        uint32_t soft_dis_jtag:3;
-        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
-         *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
-         */
-        uint32_t dis_pad_jtag:1;
-        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
-         *  Set this bit to disable flash encryption when in download boot modes.
-         */
-        uint32_t dis_download_manual_encrypt:1;
-        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
-         *  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored
-         *  in eFuse.
-         */
-        uint32_t usb_drefh:2;
-        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
-         *  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
-         *  stored in eFuse.
-         */
-        uint32_t usb_drefl:2;
-        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
-         *  Set this bit to exchange USB D+ and D- pins.
-         */
-        uint32_t usb_exchg_pins:1;
-        /** usb_ext_phy_enable : RO; bitpos: [26]; default: 0;
-         *  Set this bit to enable external PHY.
-         */
-        uint32_t usb_ext_phy_enable:1;
-        /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0;
-         *  Bluetooth GPIO signal output security level control.
-         */
-        uint32_t btlc_gpio_enable:2;
-        /** vdd_spi_modecurlim : RO; bitpos: [29]; default: 0;
-         *  SPI regulator switches current limit mode.
-         */
-        uint32_t vdd_spi_modecurlim:1;
-        /** vdd_spi_drefh : RO; bitpos: [31:30]; default: 0;
-         *  SPI regulator high voltage reference.
-         */
-        uint32_t vdd_spi_drefh:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data0_reg_t;
-
-/** Type of rd_repeat_data1 register
- *  BLOCK0 data register 2.
- */
-typedef union {
-    struct {
-        /** vdd_spi_drefm : RO; bitpos: [1:0]; default: 0;
-         *  SPI regulator medium voltage reference.
-         */
-        uint32_t vdd_spi_drefm:2;
-        /** vdd_spi_drefl : RO; bitpos: [3:2]; default: 0;
-         *  SPI regulator low voltage reference.
-         */
-        uint32_t vdd_spi_drefl:2;
-        /** vdd_spi_xpd : RO; bitpos: [4]; default: 0;
-         *  SPI regulator power up signal.
-         */
-        uint32_t vdd_spi_xpd:1;
-        /** vdd_spi_tieh : RO; bitpos: [5]; default: 0;
-         *  SPI regulator output is short connected to VDD3P3_RTC_IO.
-         */
-        uint32_t vdd_spi_tieh:1;
-        /** vdd_spi_force : RO; bitpos: [6]; default: 0;
-         *  Set this bit and force to use the configuration of eFuse to configure VDD_SPI.
-         */
-        uint32_t vdd_spi_force:1;
-        /** vdd_spi_en_init : RO; bitpos: [7]; default: 0;
-         *  Set SPI regulator to 0 to configure init[1:0]=0.
-         */
-        uint32_t vdd_spi_en_init:1;
-        /** vdd_spi_encurlim : RO; bitpos: [8]; default: 0;
-         *  Set SPI regulator to 1 to enable output current limit.
-         */
-        uint32_t vdd_spi_encurlim:1;
-        /** vdd_spi_dcurlim : RO; bitpos: [11:9]; default: 0;
-         *  Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).
-         */
-        uint32_t vdd_spi_dcurlim:3;
-        /** vdd_spi_init : RO; bitpos: [13:12]; default: 0;
-         *  Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.
-         */
-        uint32_t vdd_spi_init:2;
-        /** vdd_spi_dcap : RO; bitpos: [15:14]; default: 0;
-         *  Prevents SPI regulator from overshoot.
-         */
-        uint32_t vdd_spi_dcap:2;
-        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
-         *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
-         *  80000. 2: 160000. 3:320000.
-         */
-        uint32_t wdt_delay_sel:2;
-        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
-         *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
-         *  number of 1: disable.
-         */
-        uint32_t spi_boot_crypt_cnt:3;
-        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
-         *  Set this bit to enable revoking first secure boot key.
-         */
-        uint32_t secure_boot_key_revoke0:1;
-        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
-         *  Set this bit to enable revoking second secure boot key.
-         */
-        uint32_t secure_boot_key_revoke1:1;
-        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
-         *  Set this bit to enable revoking third secure boot key.
-         */
-        uint32_t secure_boot_key_revoke2:1;
-        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
-         *  Purpose of Key0.
-         */
-        uint32_t key_purpose_0:4;
-        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
-         *  Purpose of Key1.
-         */
-        uint32_t key_purpose_1:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data1_reg_t;
-
-/** Type of rd_repeat_data2 register
- *  BLOCK0 data register 3.
- */
-typedef union {
-    struct {
-        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
-         *  Purpose of Key2.
-         */
-        uint32_t key_purpose_2:4;
-        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
-         *  Purpose of Key3.
-         */
-        uint32_t key_purpose_3:4;
-        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
-         *  Purpose of Key4.
-         */
-        uint32_t key_purpose_4:4;
-        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
-         *  Purpose of Key5.
-         */
-        uint32_t key_purpose_5:4;
-        /** rpt4_reserved0 : RO; bitpos: [19:16]; default: 0;
-         *  Reserved (used for four backups method).
-         */
-        uint32_t rpt4_reserved0:4;
-        /** secure_boot_en : RO; bitpos: [20]; default: 0;
-         *  Set this bit to enable secure boot.
-         */
-        uint32_t secure_boot_en:1;
-        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
-         *  Set this bit to enable revoking aggressive secure boot.
-         */
-        uint32_t secure_boot_aggressive_revoke:1;
-        /** dis_usb_jtag : RO; bitpos: [22]; default: 0;
-         *  Set this bit to disable function of usb switch to jtag in module of usb device.
-         */
-        uint32_t dis_usb_jtag:1;
-        /** dis_usb_serial_jtag : RO; bitpos: [23]; default: 0;
-         *  Set this bit to disable usb device.
-         */
-        uint32_t dis_usb_serial_jtag:1;
-        /** strap_jtag_sel : RO; bitpos: [24]; default: 0;
-         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
-         *  strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
-         */
-        uint32_t strap_jtag_sel:1;
-        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
-         *  This bit is used to switch internal PHY and external PHY for USB OTG and USB
-         *  Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to
-         *  USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to
-         *  USB Device.
-         */
-        uint32_t usb_phy_sel:1;
-        /** power_glitch_dsense : RO; bitpos: [27:26]; default: 0;
-         *  Sample delay configuration of power glitch.
-         */
-        uint32_t power_glitch_dsense:2;
-        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
-         *  Configures flash waiting time after power-up, in unit of ms. If the value is less
-         *  than 15, the waiting time is the configurable value.  Otherwise, the waiting time
-         *  is twice the configurable value.
-         */
-        uint32_t flash_tpuw:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data2_reg_t;
-
-/** Type of rd_repeat_data3 register
- *  BLOCK0 data register 4.
- */
-typedef union {
-    struct {
-        /** dis_download_mode : RO; bitpos: [0]; default: 0;
-         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
-         */
-        uint32_t dis_download_mode:1;
-        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
-         *  Disable direct boot mode
-         */
-        uint32_t dis_direct_boot:1;
-        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
-         *  Selectes the default UART print channel. 0: UART0. 1: UART1.
-         */
-        uint32_t dis_usb_serial_jtag_rom_print:1;
-        /** flash_ecc_mode : RO; bitpos: [3]; default: 0;
-         *  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
-         *  use 16to17 byte mode.
-         */
-        uint32_t flash_ecc_mode:1;
-        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
-         *  Set this bit to disable UART download mode through USB.
-         */
-        uint32_t dis_usb_serial_jtag_download_mode:1;
-        /** enable_security_download : RO; bitpos: [5]; default: 0;
-         *  Set this bit to enable secure UART download mode.
-         */
-        uint32_t enable_security_download:1;
-        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
-         *  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8
-         *  is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
-         */
-        uint32_t uart_print_control:2;
-        /** pin_power_selection : RO; bitpos: [8]; default: 0;
-         *  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
-         */
-        uint32_t pin_power_selection:1;
-        /** flash_type : RO; bitpos: [9]; default: 0;
-         *  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
-         */
-        uint32_t flash_type:1;
-        /** flash_page_size : RO; bitpos: [11:10]; default: 0;
-         *  Set Flash page size.
-         */
-        uint32_t flash_page_size:2;
-        /** flash_ecc_en : RO; bitpos: [12]; default: 0;
-         *  Set 1 to enable ECC for flash boot.
-         */
-        uint32_t flash_ecc_en:1;
-        /** force_send_resume : RO; bitpos: [13]; default: 0;
-         *  Set this bit to force ROM code to send a resume command during SPI boot.
-         */
-        uint32_t force_send_resume:1;
-        /** secure_version : RO; bitpos: [29:14]; default: 0;
-         *  Secure version (used by ESP-IDF anti-rollback feature).
-         */
-        uint32_t secure_version:16;
-        /** powerglitch_en : RO; bitpos: [30]; default: 0;
-         *  Set this bit to enable power glitch function.
-         */
-        uint32_t powerglitch_en:1;
-        /** dis_usb_otg_download_mode : R; bitpos: [31]; default: 0;
-         *  Set this bit to disable download through USB-OTG
-         */
-        uint32_t dis_usb_otg_download_mode:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data3_reg_t;
-
-/** Type of rd_repeat_data4 register
- *  BLOCK0 data register 5.
- */
-typedef union {
-    struct {
-        /** disable_wafer_version_major : R; bitpos: [0]; default: 0;
-         *  Disables check of wafer version major
-         */
-        uint32_t disable_wafer_version_major:1;
-        /** disable_blk_version_major : R; bitpos: [1]; default: 0;
-         *  Disables check of blk version major
-         */
-        uint32_t disable_blk_version_major:1;
-        /** reserved_0_162 : R; bitpos: [23:2]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_0_162:22;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_data4_reg_t;
-
-/** Type of rd_mac_spi_sys_0 register
- *  BLOCK1 data register 0.
- */
-typedef union {
-    struct {
-        /** mac_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the low 32 bits of MAC address.
-         */
-        uint32_t mac_0:32;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_0_reg_t;
-
-/** Type of rd_mac_spi_sys_1 register
- *  BLOCK1 data register 1.
- */
-typedef union {
-    struct {
-        /** mac_1 : RO; bitpos: [15:0]; default: 0;
-         *  Stores the high 16 bits of MAC address.
-         */
-        uint32_t mac_1:16;
-        /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0;
-         *  SPI_PAD_configure CLK
-         */
-        uint32_t spi_pad_config_clk:6;
-        /** spi_pad_config_q : R; bitpos: [27:22]; default: 0;
-         *  SPI_PAD_configure Q(D1)
-         */
-        uint32_t spi_pad_config_q:6;
-        /** spi_pad_config_d : R; bitpos: [31:28]; default: 0;
-         *  SPI_PAD_configure D(D0)
-         */
-        uint32_t spi_pad_config_d:4;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_1_reg_t;
-
-/** Type of rd_mac_spi_sys_2 register
- *  BLOCK1 data register 2.
- */
-typedef union {
-    struct {
-        /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0;
-         *  SPI_PAD_configure D(D0)
-         */
-        uint32_t spi_pad_config_d_1:2;
-        /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0;
-         *  SPI_PAD_configure CS
-         */
-        uint32_t spi_pad_config_cs:6;
-        /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0;
-         *  SPI_PAD_configure HD(D3)
-         */
-        uint32_t spi_pad_config_hd:6;
-        /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0;
-         *  SPI_PAD_configure WP(D2)
-         */
-        uint32_t spi_pad_config_wp:6;
-        /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0;
-         *  SPI_PAD_configure DQS
-         */
-        uint32_t spi_pad_config_dqs:6;
-        /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0;
-         *  SPI_PAD_configure D4
-         */
-        uint32_t spi_pad_config_d4:6;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_2_reg_t;
-
-/** Type of rd_mac_spi_sys_3 register
- *  BLOCK1 data register 3.
- */
-typedef union {
-    struct {
-        /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0;
-         *  SPI_PAD_configure D5
-         */
-        uint32_t spi_pad_config_d5:6;
-        /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0;
-         *  SPI_PAD_configure D6
-         */
-        uint32_t spi_pad_config_d6:6;
-        /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0;
-         *  SPI_PAD_configure D7
-         */
-        uint32_t spi_pad_config_d7:6;
-        /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0;
-         *  WAFER_VERSION_MINOR least significant bits
-         */
-        uint32_t wafer_version_minor_lo:3;
-        /** pkg_version : R; bitpos: [23:21]; default: 0;
-         *  Package version
-         */
-        uint32_t pkg_version:3;
-        /** blk_version_minor : R; bitpos: [26:24]; default: 0;
-         *  BLK_VERSION_MINOR
-         */
-        uint32_t blk_version_minor:3;
-        /** flash_cap : R; bitpos: [29:27]; default: 0;
-         *  Flash capacity
-         */
-        uint32_t flash_cap:3;
-        /** flash_temp : R; bitpos: [31:30]; default: 0;
-         *  Flash temperature
-         */
-        uint32_t flash_temp:2;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_3_reg_t;
-
-/** Type of rd_mac_spi_sys_4 register
- *  BLOCK1 data register 4.
- */
-typedef union {
-    struct {
-        /** flash_vendor : R; bitpos: [2:0]; default: 0;
-         *  Flash vendor
-         */
-        uint32_t flash_vendor:3;
-        /** psram_cap : R; bitpos: [4:3]; default: 0;
-         *  PSRAM capacity
-         */
-        uint32_t psram_cap:2;
-        /** psram_temp : R; bitpos: [6:5]; default: 0;
-         *  PSRAM temperature
-         */
-        uint32_t psram_temp:2;
-        /** psram_vendor : R; bitpos: [8:7]; default: 0;
-         *  PSRAM vendor
-         */
-        uint32_t psram_vendor:2;
-        /** reserved_1_137 : R; bitpos: [12:9]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_137:4;
-        /** k_rtc_ldo : R; bitpos: [19:13]; default: 0;
-         *  BLOCK1 K_RTC_LDO
-         */
-        uint32_t k_rtc_ldo:7;
-        /** k_dig_ldo : R; bitpos: [26:20]; default: 0;
-         *  BLOCK1 K_DIG_LDO
-         */
-        uint32_t k_dig_ldo:7;
-        /** v_rtc_dbias20 : R; bitpos: [31:27]; default: 0;
-         *  BLOCK1 voltage of rtc dbias20
-         */
-        uint32_t v_rtc_dbias20:5;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_4_reg_t;
-
-/** Type of rd_mac_spi_sys_5 register
- *  BLOCK1 data register 5.
- */
-typedef union {
-    struct {
-        /** v_rtc_dbias20_1 : R; bitpos: [2:0]; default: 0;
-         *  BLOCK1 voltage of rtc dbias20
-         */
-        uint32_t v_rtc_dbias20_1:3;
-        /** v_dig_dbias20 : R; bitpos: [10:3]; default: 0;
-         *  BLOCK1 voltage of digital dbias20
-         */
-        uint32_t v_dig_dbias20:8;
-        /** dig_dbias_hvt : R; bitpos: [15:11]; default: 0;
-         *  BLOCK1 digital dbias when hvt
-         */
-        uint32_t dig_dbias_hvt:5;
-        /** reserved_1_176 : R; bitpos: [22:16]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_1_176:7;
-        /** wafer_version_minor_hi : R; bitpos: [23]; default: 0;
-         *  WAFER_VERSION_MINOR most significant bit
-         */
-        uint32_t wafer_version_minor_hi:1;
-        /** wafer_version_major : R; bitpos: [25:24]; default: 0;
-         *  WAFER_VERSION_MAJOR
-         */
-        uint32_t wafer_version_major:2;
-        /** adc2_cal_vol_atten3 : R; bitpos: [31:26]; default: 0;
-         *  ADC2 calibration voltage at atten3
-         */
-        uint32_t adc2_cal_vol_atten3:6;
-    };
-    uint32_t val;
-} efuse_rd_mac_spi_sys_5_reg_t;
-
-/** Type of rd_sys_part1_data0 register
- *  Register 0 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data0_reg_t;
-
-/** Type of rd_sys_part1_data1 register
- *  Register 1 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data1_reg_t;
-
-/** Type of rd_sys_part1_data2 register
- *  Register 2 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data2_reg_t;
-
-/** Type of rd_sys_part1_data3 register
- *  Register 3 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
-         *  Optional unique 128-bit ID
-         */
-        uint32_t optional_unique_id_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data3_reg_t;
-
-/** Type of rd_sys_part1_data4 register
- *  Register 4 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** blk_version_major : R; bitpos: [1:0]; default: 0;
-         *  BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
-         */
-        uint32_t blk_version_major:2;
-        /** reserved_2_130 : R; bitpos: [3:2]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_130:2;
-        /** temp_calib : R; bitpos: [12:4]; default: 0;
-         *  Temperature calibration data
-         */
-        uint32_t temp_calib:9;
-        /** ocode : R; bitpos: [20:13]; default: 0;
-         *  ADC OCode
-         */
-        uint32_t ocode:8;
-        /** adc1_init_code_atten0 : R; bitpos: [28:21]; default: 0;
-         *  ADC1 init code at atten0
-         */
-        uint32_t adc1_init_code_atten0:8;
-        /** adc1_init_code_atten1 : R; bitpos: [31:29]; default: 0;
-         *  ADC1 init code at atten1
-         */
-        uint32_t adc1_init_code_atten1:3;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data4_reg_t;
-
-/** Type of rd_sys_part1_data5 register
- *  Register 5 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_init_code_atten1_1 : R; bitpos: [2:0]; default: 0;
-         *  ADC1 init code at atten1
-         */
-        uint32_t adc1_init_code_atten1_1:3;
-        /** adc1_init_code_atten2 : R; bitpos: [8:3]; default: 0;
-         *  ADC1 init code at atten2
-         */
-        uint32_t adc1_init_code_atten2:6;
-        /** adc1_init_code_atten3 : R; bitpos: [14:9]; default: 0;
-         *  ADC1 init code at atten3
-         */
-        uint32_t adc1_init_code_atten3:6;
-        /** adc2_init_code_atten0 : R; bitpos: [22:15]; default: 0;
-         *  ADC2 init code at atten0
-         */
-        uint32_t adc2_init_code_atten0:8;
-        /** adc2_init_code_atten1 : R; bitpos: [28:23]; default: 0;
-         *  ADC2 init code at atten1
-         */
-        uint32_t adc2_init_code_atten1:6;
-        /** adc2_init_code_atten2 : R; bitpos: [31:29]; default: 0;
-         *  ADC2 init code at atten2
-         */
-        uint32_t adc2_init_code_atten2:3;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data5_reg_t;
-
-/** Type of rd_sys_part1_data6 register
- *  Register 6 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc2_init_code_atten2_1 : R; bitpos: [2:0]; default: 0;
-         *  ADC2 init code at atten2
-         */
-        uint32_t adc2_init_code_atten2_1:3;
-        /** adc2_init_code_atten3 : R; bitpos: [8:3]; default: 0;
-         *  ADC2 init code at atten3
-         */
-        uint32_t adc2_init_code_atten3:6;
-        /** adc1_cal_vol_atten0 : R; bitpos: [16:9]; default: 0;
-         *  ADC1 calibration voltage at atten0
-         */
-        uint32_t adc1_cal_vol_atten0:8;
-        /** adc1_cal_vol_atten1 : R; bitpos: [24:17]; default: 0;
-         *  ADC1 calibration voltage at atten1
-         */
-        uint32_t adc1_cal_vol_atten1:8;
-        /** adc1_cal_vol_atten2 : R; bitpos: [31:25]; default: 0;
-         *  ADC1 calibration voltage at atten2
-         */
-        uint32_t adc1_cal_vol_atten2:7;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data6_reg_t;
-
-/** Type of rd_sys_part1_data7 register
- *  Register 7 of BLOCK2 (system).
- */
-typedef union {
-    struct {
-        /** adc1_cal_vol_atten2_1 : R; bitpos: [0]; default: 0;
-         *  ADC1 calibration voltage at atten2
-         */
-        uint32_t adc1_cal_vol_atten2_1:1;
-        /** adc1_cal_vol_atten3 : R; bitpos: [8:1]; default: 0;
-         *  ADC1 calibration voltage at atten3
-         */
-        uint32_t adc1_cal_vol_atten3:8;
-        /** adc2_cal_vol_atten0 : R; bitpos: [16:9]; default: 0;
-         *  ADC2 calibration voltage at atten0
-         */
-        uint32_t adc2_cal_vol_atten0:8;
-        /** adc2_cal_vol_atten1 : R; bitpos: [23:17]; default: 0;
-         *  ADC2 calibration voltage at atten1
-         */
-        uint32_t adc2_cal_vol_atten1:7;
-        /** adc2_cal_vol_atten2 : R; bitpos: [30:24]; default: 0;
-         *  ADC2 calibration voltage at atten2
-         */
-        uint32_t adc2_cal_vol_atten2:7;
-        /** reserved_2_255 : R; bitpos: [31]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_2_255:1;
-    };
-    uint32_t val;
-} efuse_rd_sys_part1_data7_reg_t;
-
-/** Type of rd_usr_data0 register
- *  Register 0 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data0_reg_t;
-
-/** Type of rd_usr_data1 register
- *  Register 1 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data1_reg_t;
-
-/** Type of rd_usr_data2 register
- *  Register 2 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data2_reg_t;
-
-/** Type of rd_usr_data3 register
- *  Register 3 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data3_reg_t;
-
-/** Type of rd_usr_data4 register
- *  Register 4 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data4_reg_t;
-
-/** Type of rd_usr_data5 register
- *  Register 5 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of BLOCK3 (user).
-         */
-        uint32_t usr_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_usr_data5_reg_t;
-
-/** Type of rd_usr_data6 register
- *  Register 6 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_192:8;
-        /** custom_mac : R; bitpos: [31:8]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac:24;
-    };
-    uint32_t val;
-} efuse_rd_usr_data6_reg_t;
-
-/** Type of rd_usr_data7 register
- *  Register 7 of BLOCK3 (user).
- */
-typedef union {
-    struct {
-        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
-         *  Custom MAC
-         */
-        uint32_t custom_mac_1:24;
-        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
-         *  reserved
-         */
-        uint32_t reserved_3_248:8;
-    };
-    uint32_t val;
-} efuse_rd_usr_data7_reg_t;
-
-/** Type of rd_key0_data0 register
- *  Register 0 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY0.
-         */
-        uint32_t key0_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data0_reg_t;
-
-/** Type of rd_key0_data1 register
- *  Register 1 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY0.
-         */
-        uint32_t key0_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data1_reg_t;
-
-/** Type of rd_key0_data2 register
- *  Register 2 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY0.
-         */
-        uint32_t key0_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data2_reg_t;
-
-/** Type of rd_key0_data3 register
- *  Register 3 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY0.
-         */
-        uint32_t key0_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data3_reg_t;
-
-/** Type of rd_key0_data4 register
- *  Register 4 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY0.
-         */
-        uint32_t key0_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data4_reg_t;
-
-/** Type of rd_key0_data5 register
- *  Register 5 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY0.
-         */
-        uint32_t key0_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data5_reg_t;
-
-/** Type of rd_key0_data6 register
- *  Register 6 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY0.
-         */
-        uint32_t key0_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data6_reg_t;
-
-/** Type of rd_key0_data7 register
- *  Register 7 of BLOCK4 (KEY0).
- */
-typedef union {
-    struct {
-        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY0.
-         */
-        uint32_t key0_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key0_data7_reg_t;
-
-/** Type of rd_key1_data0 register
- *  Register 0 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY1.
-         */
-        uint32_t key1_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data0_reg_t;
-
-/** Type of rd_key1_data1 register
- *  Register 1 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY1.
-         */
-        uint32_t key1_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data1_reg_t;
-
-/** Type of rd_key1_data2 register
- *  Register 2 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY1.
-         */
-        uint32_t key1_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data2_reg_t;
-
-/** Type of rd_key1_data3 register
- *  Register 3 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY1.
-         */
-        uint32_t key1_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data3_reg_t;
-
-/** Type of rd_key1_data4 register
- *  Register 4 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY1.
-         */
-        uint32_t key1_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data4_reg_t;
-
-/** Type of rd_key1_data5 register
- *  Register 5 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY1.
-         */
-        uint32_t key1_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data5_reg_t;
-
-/** Type of rd_key1_data6 register
- *  Register 6 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY1.
-         */
-        uint32_t key1_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data6_reg_t;
-
-/** Type of rd_key1_data7 register
- *  Register 7 of BLOCK5 (KEY1).
- */
-typedef union {
-    struct {
-        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY1.
-         */
-        uint32_t key1_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key1_data7_reg_t;
-
-/** Type of rd_key2_data0 register
- *  Register 0 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY2.
-         */
-        uint32_t key2_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data0_reg_t;
-
-/** Type of rd_key2_data1 register
- *  Register 1 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY2.
-         */
-        uint32_t key2_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data1_reg_t;
-
-/** Type of rd_key2_data2 register
- *  Register 2 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY2.
-         */
-        uint32_t key2_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data2_reg_t;
-
-/** Type of rd_key2_data3 register
- *  Register 3 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY2.
-         */
-        uint32_t key2_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data3_reg_t;
-
-/** Type of rd_key2_data4 register
- *  Register 4 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY2.
-         */
-        uint32_t key2_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data4_reg_t;
-
-/** Type of rd_key2_data5 register
- *  Register 5 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY2.
-         */
-        uint32_t key2_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data5_reg_t;
-
-/** Type of rd_key2_data6 register
- *  Register 6 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY2.
-         */
-        uint32_t key2_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data6_reg_t;
-
-/** Type of rd_key2_data7 register
- *  Register 7 of BLOCK6 (KEY2).
- */
-typedef union {
-    struct {
-        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY2.
-         */
-        uint32_t key2_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key2_data7_reg_t;
-
-/** Type of rd_key3_data0 register
- *  Register 0 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY3.
-         */
-        uint32_t key3_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data0_reg_t;
-
-/** Type of rd_key3_data1 register
- *  Register 1 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY3.
-         */
-        uint32_t key3_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data1_reg_t;
-
-/** Type of rd_key3_data2 register
- *  Register 2 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY3.
-         */
-        uint32_t key3_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data2_reg_t;
-
-/** Type of rd_key3_data3 register
- *  Register 3 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY3.
-         */
-        uint32_t key3_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data3_reg_t;
-
-/** Type of rd_key3_data4 register
- *  Register 4 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY3.
-         */
-        uint32_t key3_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data4_reg_t;
-
-/** Type of rd_key3_data5 register
- *  Register 5 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY3.
-         */
-        uint32_t key3_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data5_reg_t;
-
-/** Type of rd_key3_data6 register
- *  Register 6 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY3.
-         */
-        uint32_t key3_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data6_reg_t;
-
-/** Type of rd_key3_data7 register
- *  Register 7 of BLOCK7 (KEY3).
- */
-typedef union {
-    struct {
-        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY3.
-         */
-        uint32_t key3_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key3_data7_reg_t;
-
-/** Type of rd_key4_data0 register
- *  Register 0 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY4.
-         */
-        uint32_t key4_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data0_reg_t;
-
-/** Type of rd_key4_data1 register
- *  Register 1 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY4.
-         */
-        uint32_t key4_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data1_reg_t;
-
-/** Type of rd_key4_data2 register
- *  Register 2 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY4.
-         */
-        uint32_t key4_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data2_reg_t;
-
-/** Type of rd_key4_data3 register
- *  Register 3 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY4.
-         */
-        uint32_t key4_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data3_reg_t;
-
-/** Type of rd_key4_data4 register
- *  Register 4 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY4.
-         */
-        uint32_t key4_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data4_reg_t;
-
-/** Type of rd_key4_data5 register
- *  Register 5 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY4.
-         */
-        uint32_t key4_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data5_reg_t;
-
-/** Type of rd_key4_data6 register
- *  Register 6 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY4.
-         */
-        uint32_t key4_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data6_reg_t;
-
-/** Type of rd_key4_data7 register
- *  Register 7 of BLOCK8 (KEY4).
- */
-typedef union {
-    struct {
-        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY4.
-         */
-        uint32_t key4_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key4_data7_reg_t;
-
-/** Type of rd_key5_data0 register
- *  Register 0 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the zeroth 32 bits of KEY5.
-         */
-        uint32_t key5_data0:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data0_reg_t;
-
-/** Type of rd_key5_data1 register
- *  Register 1 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the first 32 bits of KEY5.
-         */
-        uint32_t key5_data1:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data1_reg_t;
-
-/** Type of rd_key5_data2 register
- *  Register 2 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the second 32 bits of KEY5.
-         */
-        uint32_t key5_data2:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data2_reg_t;
-
-/** Type of rd_key5_data3 register
- *  Register 3 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the third 32 bits of KEY5.
-         */
-        uint32_t key5_data3:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data3_reg_t;
-
-/** Type of rd_key5_data4 register
- *  Register 4 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fourth 32 bits of KEY5.
-         */
-        uint32_t key5_data4:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data4_reg_t;
-
-/** Type of rd_key5_data5 register
- *  Register 5 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the fifth 32 bits of KEY5.
-         */
-        uint32_t key5_data5:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data5_reg_t;
-
-/** Type of rd_key5_data6 register
- *  Register 6 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the sixth 32 bits of KEY5.
-         */
-        uint32_t key5_data6:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data6_reg_t;
-
-/** Type of rd_key5_data7 register
- *  Register 7 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the seventh 32 bits of KEY5.
-         */
-        uint32_t key5_data7:32;
-    };
-    uint32_t val;
-} efuse_rd_key5_data7_reg_t;
-
-/** Type of rd_sys_part2_data0 register
- *  Register 0 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 0th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_0:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data0_reg_t;
-
-/** Type of rd_sys_part2_data1 register
- *  Register 1 of BLOCK9 (KEY5).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 1st 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_1:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data1_reg_t;
-
-/** Type of rd_sys_part2_data2 register
- *  Register 2 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 2nd 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_2:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data2_reg_t;
-
-/** Type of rd_sys_part2_data3 register
- *  Register 3 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 3rd 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_3:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data3_reg_t;
-
-/** Type of rd_sys_part2_data4 register
- *  Register 4 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 4th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_4:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data4_reg_t;
-
-/** Type of rd_sys_part2_data5 register
- *  Register 5 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 5th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_5:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data5_reg_t;
-
-/** Type of rd_sys_part2_data6 register
- *  Register 6 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 6th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_6:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data6_reg_t;
-
-/** Type of rd_sys_part2_data7 register
- *  Register 7 of BLOCK10 (system).
- */
-typedef union {
-    struct {
-        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
-         *  Stores the 7th 32 bits of the 2nd part of system data.
-         */
-        uint32_t sys_data_part2_7:32;
-    };
-    uint32_t val;
-} efuse_rd_sys_part2_data7_reg_t;
-
-
-/** Group: Report Register */
-/** Type of rd_repeat_err0 register
- *  Programming error record register 0 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t rd_dis_err:7;
-        /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_rtc_ram_boot_err:1;
-        /** dis_icache_err : RO; bitpos: [8]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_icache_err:1;
-        /** dis_dcache_err : RO; bitpos: [9]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_dcache_err:1;
-        /** dis_download_icache_err : RO; bitpos: [10]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_icache_err:1;
-        /** dis_download_dcache_err : RO; bitpos: [11]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_dcache_err:1;
-        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_force_download_err:1;
-        /** dis_usb_err : RO; bitpos: [13]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_usb_err:1;
-        /** dis_can_err : RO; bitpos: [14]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_can_err:1;
-        /** dis_app_cpu_err : RO; bitpos: [15]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_app_cpu_err:1;
-        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t soft_dis_jtag_err:3;
-        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_pad_jtag_err:1;
-        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_manual_encrypt_err:1;
-        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t usb_drefh_err:2;
-        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t usb_drefl_err:2;
-        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t usb_exchg_pins_err:1;
-        /** ext_phy_enable_err : RO; bitpos: [26]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t ext_phy_enable_err:1;
-        /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t btlc_gpio_enable_err:2;
-        /** vdd_spi_modecurlim_err : RO; bitpos: [29]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_modecurlim_err:1;
-        /** vdd_spi_drefh_err : RO; bitpos: [31:30]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_drefh_err:2;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err0_reg_t;
-
-/** Type of rd_repeat_err1 register
- *  Programming error record register 1 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** vdd_spi_drefm_err : RO; bitpos: [1:0]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_drefm_err:2;
-        /** vdd_spi_drefl_err : RO; bitpos: [3:2]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_drefl_err:2;
-        /** vdd_spi_xpd_err : RO; bitpos: [4]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_xpd_err:1;
-        /** vdd_spi_tieh_err : RO; bitpos: [5]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_tieh_err:1;
-        /** vdd_spi_force_err : RO; bitpos: [6]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_force_err:1;
-        /** vdd_spi_en_init_err : RO; bitpos: [7]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_en_init_err:1;
-        /** vdd_spi_encurlim_err : RO; bitpos: [8]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_encurlim_err:1;
-        /** vdd_spi_dcurlim_err : RO; bitpos: [11:9]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_dcurlim_err:3;
-        /** vdd_spi_init_err : RO; bitpos: [13:12]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_init_err:2;
-        /** vdd_spi_dcap_err : RO; bitpos: [15:14]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t vdd_spi_dcap_err:2;
-        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t wdt_delay_sel_err:2;
-        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t spi_boot_crypt_cnt_err:3;
-        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_key_revoke0_err:1;
-        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_key_revoke1_err:1;
-        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_key_revoke2_err:1;
-        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_0_err:4;
-        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_1_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err1_reg_t;
-
-/** Type of rd_repeat_err2 register
- *  Programming error record register 2 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_2_err:4;
-        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_3_err:4;
-        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_4_err:4;
-        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t key_purpose_5_err:4;
-        /** rpt4_reserved0_err : RO; bitpos: [19:16]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t rpt4_reserved0_err:4;
-        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_en_err:1;
-        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t secure_boot_aggressive_revoke_err:1;
-        /** dis_usb_jtag_err : RO; bitpos: [22]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_usb_jtag_err:1;
-        /** dis_usb_device_err : RO; bitpos: [23]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_usb_device_err:1;
-        /** strap_jtag_sel_err : RO; bitpos: [24]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t strap_jtag_sel_err:1;
-        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t usb_phy_sel_err:1;
-        /** power_glitch_dsense_err : RO; bitpos: [27:26]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t power_glitch_dsense_err:2;
-        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t flash_tpuw_err:4;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err2_reg_t;
-
-/** Type of rd_repeat_err3 register
- *  Programming error record register 3 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_download_mode_err:1;
-        /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_legacy_spi_boot_err:1;
-        /** uart_print_channel_err : RO; bitpos: [2]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t uart_print_channel_err:1;
-        /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t flash_ecc_mode_err:1;
-        /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t dis_usb_download_mode_err:1;
-        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t enable_security_download_err:1;
-        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t uart_print_control_err:2;
-        /** pin_power_selection_err : RO; bitpos: [8]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t pin_power_selection_err:1;
-        /** flash_type_err : RO; bitpos: [9]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t flash_type_err:1;
-        /** flash_page_size_err : RO; bitpos: [11:10]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t flash_page_size_err:2;
-        /** flash_ecc_en_err : RO; bitpos: [12]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t flash_ecc_en_err:1;
-        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t force_send_resume_err:1;
-        /** secure_version_err : RO; bitpos: [29:14]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t secure_version_err:16;
-        /** powerglitch_en_err : RO; bitpos: [30]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t powerglitch_en_err:1;
-        /** rpt4_reserved1_err : RO; bitpos: [31]; default: 0;
-         *  Reserved.
-         */
-        uint32_t rpt4_reserved1_err:1;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err3_reg_t;
-
-/** Type of rd_repeat_err4 register
- *  Programming error record register 4 of BLOCK0.
- */
-typedef union {
-    struct {
-        /** rpt4_reserved2_err : RO; bitpos: [23:0]; default: 0;
-         *  If any bits in this filed are 1, then it indicates a programming error.
-         */
-        uint32_t rpt4_reserved2_err:24;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_rd_repeat_err4_reg_t;
-
-/** Type of rd_rs_err0 register
- *  Programming error record register 0 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t mac_spi_8m_err_num:3;
-        /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t mac_spi_8m_fail:1;
-        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part1_num:3;
-        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part1_fail:1;
-        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t usr_data_err_num:3;
-        /** usr_data_fail : RO; bitpos: [11]; default: 0;
-         *  0: Means no failure and that the user data is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t usr_data_fail:1;
-        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key0_err_num:3;
-        /** key0_fail : RO; bitpos: [15]; default: 0;
-         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
-         *  key0 failed and the number of error bytes is over 6.
-         */
-        uint32_t key0_fail:1;
-        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key1_err_num:3;
-        /** key1_fail : RO; bitpos: [19]; default: 0;
-         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
-         *  key1 failed and the number of error bytes is over 6.
-         */
-        uint32_t key1_fail:1;
-        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key2_err_num:3;
-        /** key2_fail : RO; bitpos: [23]; default: 0;
-         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
-         *  key2 failed and the number of error bytes is over 6.
-         */
-        uint32_t key2_fail:1;
-        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key3_err_num:3;
-        /** key3_fail : RO; bitpos: [27]; default: 0;
-         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
-         *  key3 failed and the number of error bytes is over 6.
-         */
-        uint32_t key3_fail:1;
-        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key4_err_num:3;
-        /** key4_fail : RO; bitpos: [31]; default: 0;
-         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
-         *  key4 failed and the number of error bytes is over 6.
-         */
-        uint32_t key4_fail:1;
-    };
-    uint32_t val;
-} efuse_rd_rs_err0_reg_t;
-
-/** Type of rd_rs_err1 register
- *  Programming error record register 1 of BLOCK1-10.
- */
-typedef union {
-    struct {
-        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t key5_err_num:3;
-        /** key5_fail : RO; bitpos: [3]; default: 0;
-         *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
-         *  user data failed and the number of error bytes is over 6.
-         */
-        uint32_t key5_fail:1;
-        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
-         *  The value of this signal means the number of error bytes.
-         */
-        uint32_t sys_part2_err_num:3;
-        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
-         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
-         *  programming user data failed and the number of error bytes is over 6.
-         */
-        uint32_t sys_part2_fail:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} efuse_rd_rs_err1_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clk register
- *  eFuse clcok configuration register.
- */
-typedef union {
-    struct {
-        /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to force eFuse SRAM into power-saving mode.
-         */
-        uint32_t efuse_mem_force_pd:1;
-        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
-         *  Set this bit and force to activate clock signal of eFuse SRAM.
-         */
-        uint32_t mem_clk_force_on:1;
-        /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to force eFuse SRAM into working mode.
-         */
-        uint32_t efuse_mem_force_pu:1;
-        uint32_t reserved_3:13;
-        /** clk_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit and force to enable clock signal of eFuse memory.
-         */
-        uint32_t clk_en:1;
-        uint32_t reserved_17:15;
-    };
-    uint32_t val;
-} efuse_clk_reg_t;
-
-/** Type of conf register
- *  eFuse operation mode configuraiton register
- */
-typedef union {
-    struct {
-        /** op_code : R/W; bitpos: [15:0]; default: 0;
-         *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
-         */
-        uint32_t op_code:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_conf_reg_t;
-
-/** Type of cmd register
- *  eFuse command register.
- */
-typedef union {
-    struct {
-        /** read_cmd : R/WS/SC; bitpos: [0]; default: 0;
-         *  Set this bit to send read command.
-         */
-        uint32_t read_cmd:1;
-        /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0;
-         *  Set this bit to send programming command.
-         */
-        uint32_t pgm_cmd:1;
-        /** blk_num : R/W; bitpos: [5:2]; default: 0;
-         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
-         *  number 0-10, respectively.
-         */
-        uint32_t blk_num:4;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} efuse_cmd_reg_t;
-
-/** Type of dac_conf register
- *  Controls the eFuse programming voltage.
- */
-typedef union {
-    struct {
-        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
-         *  Controls the division factor of the rising clock of the programming voltage.
-         */
-        uint32_t dac_clk_div:8;
-        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
-         *  Don't care.
-         */
-        uint32_t dac_clk_pad_sel:1;
-        /** dac_num : R/W; bitpos: [16:9]; default: 255;
-         *  Controls the rising period of the programming voltage.
-         */
-        uint32_t dac_num:8;
-        /** oe_clr : R/W; bitpos: [17]; default: 0;
-         *  Reduces the power supply of the programming voltage.
-         */
-        uint32_t oe_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_dac_conf_reg_t;
-
-/** Type of rd_tim_conf register
- *  Configures read timing parameters.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:24;
-        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
-         *  Configures the initial read time of eFuse.
-         */
-        uint32_t read_init_num:8;
-    };
-    uint32_t val;
-} efuse_rd_tim_conf_reg_t;
-
-/** Type of wr_tim_conf1 register
- *  Configurarion register 1 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:8;
-        /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368;
-         *  Configures the power up time for VDDQ.
-         */
-        uint32_t pwr_on_num:16;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf1_reg_t;
-
-/** Type of wr_tim_conf2 register
- *  Configurarion register 2 of eFuse programming timing parameters.
- */
-typedef union {
-    struct {
-        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
-         *  Configures the power outage time for VDDQ.
-         */
-        uint32_t pwr_off_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} efuse_wr_tim_conf2_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  eFuse status register.
- */
-typedef union {
-    struct {
-        /** state : RO; bitpos: [3:0]; default: 0;
-         *  Indicates the state of the eFuse state machine.
-         */
-        uint32_t state:4;
-        /** otp_load_sw : RO; bitpos: [4]; default: 0;
-         *  The value of OTP_LOAD_SW.
-         */
-        uint32_t otp_load_sw:1;
-        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
-         *  The value of OTP_VDDQ_C_SYNC2.
-         */
-        uint32_t otp_vddq_c_sync2:1;
-        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
-         *  The value of OTP_STROBE_SW.
-         */
-        uint32_t otp_strobe_sw:1;
-        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
-         *  The value of OTP_CSB_SW.
-         */
-        uint32_t otp_csb_sw:1;
-        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
-         *  The value of OTP_PGENB_SW.
-         */
-        uint32_t otp_pgenb_sw:1;
-        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
-         *  The value of OTP_VDDQ_IS_SW.
-         */
-        uint32_t otp_vddq_is_sw:1;
-        /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0;
-         *  Indicates the number of error bits during programming BLOCK0.
-         */
-        uint32_t repeat_err_cnt:8;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} efuse_status_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  eFuse raw interrupt register.
- */
-typedef union {
-    struct {
-        /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0;
-         *  The raw bit signal for read_done interrupt.
-         */
-        uint32_t read_done_int_raw:1;
-        /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0;
-         *  The raw bit signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_raw:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_raw_reg_t;
-
-/** Type of int_st register
- *  eFuse interrupt status register.
- */
-typedef union {
-    struct {
-        /** read_done_int_st : RO; bitpos: [0]; default: 0;
-         *  The status signal for read_done interrupt.
-         */
-        uint32_t read_done_int_st:1;
-        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_st:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_st_reg_t;
-
-/** Type of int_ena register
- *  eFuse interrupt enable register.
- */
-typedef union {
-    struct {
-        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable signal for read_done interrupt.
-         */
-        uint32_t read_done_int_ena:1;
-        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_ena:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_ena_reg_t;
-
-/** Type of int_clr register
- *  eFuse interrupt clear register.
- */
-typedef union {
-    struct {
-        /** read_done_int_clr : WO; bitpos: [0]; default: 0;
-         *  The clear signal for read_done interrupt.
-         */
-        uint32_t read_done_int_clr:1;
-        /** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
-         *  The clear signal for pgm_done interrupt.
-         */
-        uint32_t pgm_done_int_clr:1;
-        uint32_t reserved_2:30;
-    };
-    uint32_t val;
-} efuse_int_clr_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  eFuse version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 34607760;
-         *  Stores eFuse version.
-         */
-        uint32_t date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} efuse_date_reg_t;
-
-
-typedef struct {
-    volatile efuse_pgm_data0_reg_t pgm_data0;
-    volatile efuse_pgm_data1_reg_t pgm_data1;
-    volatile efuse_pgm_data2_reg_t pgm_data2;
-    volatile efuse_pgm_data3_reg_t pgm_data3;
-    volatile efuse_pgm_data4_reg_t pgm_data4;
-    volatile efuse_pgm_data5_reg_t pgm_data5;
-    volatile efuse_pgm_data6_reg_t pgm_data6;
-    volatile efuse_pgm_data7_reg_t pgm_data7;
-    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
-    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
-    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
-    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
-    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
-    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
-    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
-    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
-    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
-    volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0;
-    volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1;
-    volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2;
-    volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3;
-    volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4;
-    volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5;
-    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
-    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
-    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
-    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
-    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
-    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
-    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
-    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
-    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
-    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
-    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
-    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
-    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
-    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
-    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
-    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
-    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
-    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
-    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
-    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
-    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
-    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
-    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
-    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
-    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
-    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
-    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
-    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
-    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
-    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
-    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
-    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
-    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
-    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
-    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
-    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
-    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
-    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
-    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
-    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
-    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
-    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
-    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
-    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
-    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
-    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
-    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
-    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
-    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
-    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
-    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
-    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
-    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
-    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
-    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
-    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
-    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
-    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
-    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
-    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
-    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
-    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
-    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
-    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
-    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
-    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
-    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
-    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
-    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
-    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
-    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
-    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
-    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
-    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
-    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
-    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
-    uint32_t reserved_18c;
-    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
-    uint32_t reserved_194[11];
-    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
-    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
-    volatile efuse_clk_reg_t clk;
-    volatile efuse_conf_reg_t conf;
-    volatile efuse_status_reg_t status;
-    volatile efuse_cmd_reg_t cmd;
-    volatile efuse_int_raw_reg_t int_raw;
-    volatile efuse_int_st_reg_t int_st;
-    volatile efuse_int_ena_reg_t int_ena;
-    volatile efuse_int_clr_reg_t int_clr;
-    volatile efuse_dac_conf_reg_t dac_conf;
-    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
-    uint32_t reserved_1f0;
-    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
-    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
-    volatile efuse_date_reg_t date;
-} efuse_dev_t;
-
-extern efuse_dev_t EFUSE;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/extmem_reg.h b/components/soc/esp32s3/include/soc/extmem_reg.h
deleted file mode 100644
index 5763ec6df77..00000000000
--- a/components/soc/esp32s3/include/soc/extmem_reg.h
+++ /dev/null
@@ -1,1676 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_EXTMEM_REG_H_
-#define _SOC_EXTMEM_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define EXTMEM_DCACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0)
-/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 byt
-es.*/
-#define EXTMEM_DCACHE_BLOCKSIZE_MODE    0x00000003
-#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M  ((EXTMEM_DCACHE_BLOCKSIZE_MODE_V)<<(EXTMEM_DCACHE_BLOCKSIZE_MODE_S))
-#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V  0x3
-#define EXTMEM_DCACHE_BLOCKSIZE_MODE_S  3
-/* EXTMEM_DCACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to configure cache memory size.0: 32KB, 1: 64KB.*/
-#define EXTMEM_DCACHE_SIZE_MODE    (BIT(2))
-#define EXTMEM_DCACHE_SIZE_MODE_M  (BIT(2))
-#define EXTMEM_DCACHE_SIZE_MODE_V  0x1
-#define EXTMEM_DCACHE_SIZE_MODE_S  2
-/* EXTMEM_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/
-#define EXTMEM_DCACHE_ENABLE    (BIT(0))
-#define EXTMEM_DCACHE_ENABLE_M  (BIT(0))
-#define EXTMEM_DCACHE_ENABLE_V  0x1
-#define EXTMEM_DCACHE_ENABLE_S  0
-
-#define EXTMEM_DCACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x4)
-/* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to disable core1 dbus, 0: enable, 1: disable.*/
-#define EXTMEM_DCACHE_SHUT_CORE1_BUS    (BIT(1))
-#define EXTMEM_DCACHE_SHUT_CORE1_BUS_M  (BIT(1))
-#define EXTMEM_DCACHE_SHUT_CORE1_BUS_V  0x1
-#define EXTMEM_DCACHE_SHUT_CORE1_BUS_S  1
-/* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to disable core0 dbus, 0: enable, 1: disable.*/
-#define EXTMEM_DCACHE_SHUT_CORE0_BUS    (BIT(0))
-#define EXTMEM_DCACHE_SHUT_CORE0_BUS_M  (BIT(0))
-#define EXTMEM_DCACHE_SHUT_CORE0_BUS_V  0x1
-#define EXTMEM_DCACHE_SHUT_CORE0_BUS_S  0
-
-#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x8)
-/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to power dcache tag memory up, 0: follow  rtc_lslp_pd, 1: power
-up.*/
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU    (BIT(2))
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V  0x1
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S  2
-/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to power dcache tag memory down, 0: follow  rtc_lslp_pd, 1: powe
-r down.*/
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD    (BIT(1))
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V  0x1
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S  1
-/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of dcache tag memory. 1: close gating, 0:
-open clock gating..*/
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON    (BIT(0))
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V  0x1
-#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S  0
-
-#define EXTMEM_DCACHE_PRELOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xC)
-/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section of prelock function..*/
-#define EXTMEM_DCACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M  (BIT(1))
-#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V  0x1
-#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S  1
-/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section of prelock function..*/
-#define EXTMEM_DCACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M  (BIT(0))
-#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V  0x1
-#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S  0
-
-#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x10)
-/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to configure the first start virtual address of data prelock,
-which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG.*/
-#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
-#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S))
-#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S  0
-
-#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x14)
-/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to configure the second start virtual address of data prelock,
- which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG.*/
-#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
-#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S))
-#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S  0
-
-#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x18)
-/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: The bits are used to configure the first length of data locking, which is combin
-ed with DCACHE_PRELOCK_SCT0_ADDR_REG.*/
-#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE    0x0000FFFF
-#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S))
-#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V  0xFFFF
-#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S  16
-/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the second length of data locking, which is combi
-ned with DCACHE_PRELOCK_SCT1_ADDR_REG.*/
-#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE    0x0000FFFF
-#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S))
-#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V  0xFFFF
-#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S  0
-
-#define EXTMEM_DCACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x1C)
-/* EXTMEM_DCACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to indicate unlock/lock operation is finished..*/
-#define EXTMEM_DCACHE_LOCK_DONE    (BIT(2))
-#define EXTMEM_DCACHE_LOCK_DONE_M  (BIT(2))
-#define EXTMEM_DCACHE_LOCK_DONE_V  0x1
-#define EXTMEM_DCACHE_LOCK_DONE_S  2
-/* EXTMEM_DCACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
- unlock operation done..*/
-#define EXTMEM_DCACHE_UNLOCK_ENA    (BIT(1))
-#define EXTMEM_DCACHE_UNLOCK_ENA_M  (BIT(1))
-#define EXTMEM_DCACHE_UNLOCK_ENA_V  0x1
-#define EXTMEM_DCACHE_UNLOCK_ENA_S  1
-/* EXTMEM_DCACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
-ock operation done..*/
-#define EXTMEM_DCACHE_LOCK_ENA    (BIT(0))
-#define EXTMEM_DCACHE_LOCK_ENA_M  (BIT(0))
-#define EXTMEM_DCACHE_LOCK_ENA_V  0x1
-#define EXTMEM_DCACHE_LOCK_ENA_S  0
-
-#define EXTMEM_DCACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x20)
-/* EXTMEM_DCACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for lock operations. It
- should be combined with DCACHE_LOCK_SIZE_REG..*/
-#define EXTMEM_DCACHE_LOCK_ADDR    0xFFFFFFFF
-#define EXTMEM_DCACHE_LOCK_ADDR_M  ((EXTMEM_DCACHE_LOCK_ADDR_V)<<(EXTMEM_DCACHE_LOCK_ADDR_S))
-#define EXTMEM_DCACHE_LOCK_ADDR_V  0xFFFFFFFF
-#define EXTMEM_DCACHE_LOCK_ADDR_S  0
-
-#define EXTMEM_DCACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x24)
-/* EXTMEM_DCACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the length for lock operations. The bits are the
-counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG..*/
-#define EXTMEM_DCACHE_LOCK_SIZE    0x0000FFFF
-#define EXTMEM_DCACHE_LOCK_SIZE_M  ((EXTMEM_DCACHE_LOCK_SIZE_V)<<(EXTMEM_DCACHE_LOCK_SIZE_S))
-#define EXTMEM_DCACHE_LOCK_SIZE_V  0xFFFF
-#define EXTMEM_DCACHE_LOCK_SIZE_S  0
-
-#define EXTMEM_DCACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x28)
-/* EXTMEM_DCACHE_SYNC_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate clean/writeback/invalidate operation is finished..*/
-#define EXTMEM_DCACHE_SYNC_DONE    (BIT(3))
-#define EXTMEM_DCACHE_SYNC_DONE_M  (BIT(3))
-#define EXTMEM_DCACHE_SYNC_DONE_V  0x1
-#define EXTMEM_DCACHE_SYNC_DONE_S  3
-/* EXTMEM_DCACHE_CLEAN_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable clean operation. It will be cleared by hardware after
-clean operation done..*/
-#define EXTMEM_DCACHE_CLEAN_ENA    (BIT(2))
-#define EXTMEM_DCACHE_CLEAN_ENA_M  (BIT(2))
-#define EXTMEM_DCACHE_CLEAN_ENA_V  0x1
-#define EXTMEM_DCACHE_CLEAN_ENA_S  2
-/* EXTMEM_DCACHE_WRITEBACK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
-ter writeback operation done..*/
-#define EXTMEM_DCACHE_WRITEBACK_ENA    (BIT(1))
-#define EXTMEM_DCACHE_WRITEBACK_ENA_M  (BIT(1))
-#define EXTMEM_DCACHE_WRITEBACK_ENA_V  0x1
-#define EXTMEM_DCACHE_WRITEBACK_ENA_S  1
-/* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
-fter invalidate operation done..*/
-#define EXTMEM_DCACHE_INVALIDATE_ENA    (BIT(0))
-#define EXTMEM_DCACHE_INVALIDATE_ENA_M  (BIT(0))
-#define EXTMEM_DCACHE_INVALIDATE_ENA_V  0x1
-#define EXTMEM_DCACHE_INVALIDATE_ENA_S  0
-
-#define EXTMEM_DCACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x2C)
-/* EXTMEM_DCACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for clean operations. I
-t should be combined with DCACHE_SYNC_SIZE_REG..*/
-#define EXTMEM_DCACHE_SYNC_ADDR    0xFFFFFFFF
-#define EXTMEM_DCACHE_SYNC_ADDR_M  ((EXTMEM_DCACHE_SYNC_ADDR_V)<<(EXTMEM_DCACHE_SYNC_ADDR_S))
-#define EXTMEM_DCACHE_SYNC_ADDR_V  0xFFFFFFFF
-#define EXTMEM_DCACHE_SYNC_ADDR_S  0
-
-#define EXTMEM_DCACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x30)
-/* EXTMEM_DCACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
-/*description: The bits are used to configure the length for sync operations. The bits are the
-counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG..*/
-#define EXTMEM_DCACHE_SYNC_SIZE    0x007FFFFF
-#define EXTMEM_DCACHE_SYNC_SIZE_M  ((EXTMEM_DCACHE_SYNC_SIZE_V)<<(EXTMEM_DCACHE_SYNC_SIZE_S))
-#define EXTMEM_DCACHE_SYNC_SIZE_V  0x7FFFFF
-#define EXTMEM_DCACHE_SYNC_SIZE_S  0
-
-#define EXTMEM_DCACHE_OCCUPY_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x34)
-/* EXTMEM_DCACHE_OCCUPY_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to indicate occupy operation is finished..*/
-#define EXTMEM_DCACHE_OCCUPY_DONE    (BIT(1))
-#define EXTMEM_DCACHE_OCCUPY_DONE_M  (BIT(1))
-#define EXTMEM_DCACHE_OCCUPY_DONE_V  0x1
-#define EXTMEM_DCACHE_OCCUPY_DONE_S  1
-/* EXTMEM_DCACHE_OCCUPY_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable occupy operation. It will be cleared by hardware after
- issuing Auot-Invalidate Operation..*/
-#define EXTMEM_DCACHE_OCCUPY_ENA    (BIT(0))
-#define EXTMEM_DCACHE_OCCUPY_ENA_M  (BIT(0))
-#define EXTMEM_DCACHE_OCCUPY_ENA_V  0x1
-#define EXTMEM_DCACHE_OCCUPY_ENA_S  0
-
-#define EXTMEM_DCACHE_OCCUPY_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x38)
-/* EXTMEM_DCACHE_OCCUPY_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for occupy operation. I
-t should be combined with DCACHE_OCCUPY_SIZE_REG..*/
-#define EXTMEM_DCACHE_OCCUPY_ADDR    0xFFFFFFFF
-#define EXTMEM_DCACHE_OCCUPY_ADDR_M  ((EXTMEM_DCACHE_OCCUPY_ADDR_V)<<(EXTMEM_DCACHE_OCCUPY_ADDR_S))
-#define EXTMEM_DCACHE_OCCUPY_ADDR_V  0xFFFFFFFF
-#define EXTMEM_DCACHE_OCCUPY_ADDR_S  0
-
-#define EXTMEM_DCACHE_OCCUPY_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x3C)
-/* EXTMEM_DCACHE_OCCUPY_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the length for occupy operation. The bits are the
- counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG..*/
-#define EXTMEM_DCACHE_OCCUPY_SIZE    0x0000FFFF
-#define EXTMEM_DCACHE_OCCUPY_SIZE_M  ((EXTMEM_DCACHE_OCCUPY_SIZE_V)<<(EXTMEM_DCACHE_OCCUPY_SIZE_S))
-#define EXTMEM_DCACHE_OCCUPY_SIZE_V  0xFFFF
-#define EXTMEM_DCACHE_OCCUPY_SIZE_S  0
-
-#define EXTMEM_DCACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x40)
-/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to configure the direction of preload operation. 1: descending,
-0: ascending..*/
-#define EXTMEM_DCACHE_PRELOAD_ORDER    (BIT(2))
-#define EXTMEM_DCACHE_PRELOAD_ORDER_M  (BIT(2))
-#define EXTMEM_DCACHE_PRELOAD_ORDER_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_ORDER_S  2
-/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to indicate preload operation is finished..*/
-#define EXTMEM_DCACHE_PRELOAD_DONE    (BIT(1))
-#define EXTMEM_DCACHE_PRELOAD_DONE_M  (BIT(1))
-#define EXTMEM_DCACHE_PRELOAD_DONE_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_DONE_S  1
-/* EXTMEM_DCACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable preload operation. It will be cleared by hardware afte
-r preload operation done..*/
-#define EXTMEM_DCACHE_PRELOAD_ENA    (BIT(0))
-#define EXTMEM_DCACHE_PRELOAD_ENA_M  (BIT(0))
-#define EXTMEM_DCACHE_PRELOAD_ENA_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_ENA_S  0
-
-#define EXTMEM_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x44)
-/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for preload operation.
-It should be combined with DCACHE_PRELOAD_SIZE_REG..*/
-#define EXTMEM_DCACHE_PRELOAD_ADDR    0xFFFFFFFF
-#define EXTMEM_DCACHE_PRELOAD_ADDR_M  ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S))
-#define EXTMEM_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFF
-#define EXTMEM_DCACHE_PRELOAD_ADDR_S  0
-
-#define EXTMEM_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x48)
-/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the length for preload operation. The bits are th
-e counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG...*/
-#define EXTMEM_DCACHE_PRELOAD_SIZE    0x0000FFFF
-#define EXTMEM_DCACHE_PRELOAD_SIZE_M  ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S))
-#define EXTMEM_DCACHE_PRELOAD_SIZE_V  0xFFFF
-#define EXTMEM_DCACHE_PRELOAD_SIZE_S  0
-
-#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x4C)
-/* EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit is used to clear autoload buffer in dcache..*/
-#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR    (BIT(9))
-#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_M  (BIT(9))
-#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V  0x1
-#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S  9
-/* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */
-/*description: The bits are used to configure the numbers of the cache block for the issuing au
-toload operation..*/
-#define EXTMEM_DCACHE_AUTOLOAD_SIZE    0x00000003
-#define EXTMEM_DCACHE_AUTOLOAD_SIZE_M  ((EXTMEM_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SIZE_S))
-#define EXTMEM_DCACHE_AUTOLOAD_SIZE_V  0x3
-#define EXTMEM_DCACHE_AUTOLOAD_SIZE_S  7
-/* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
-/*description: The bits are used to configure trigger conditions for autoload. 0/3: cache miss,
- 1: cache hit, 2: both cache miss and hit..*/
-#define EXTMEM_DCACHE_AUTOLOAD_RQST    0x00000003
-#define EXTMEM_DCACHE_AUTOLOAD_RQST_M  ((EXTMEM_DCACHE_AUTOLOAD_RQST_V)<<(EXTMEM_DCACHE_AUTOLOAD_RQST_S))
-#define EXTMEM_DCACHE_AUTOLOAD_RQST_V  0x3
-#define EXTMEM_DCACHE_AUTOLOAD_RQST_S  5
-/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bits are used to configure the direction of autoload. 1: descending, 0: asce
-nding..*/
-#define EXTMEM_DCACHE_AUTOLOAD_ORDER    (BIT(4))
-#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M  (BIT(4))
-#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V  0x1
-#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S  4
-/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
-/*description: The bit is used to indicate autoload operation is finished..*/
-#define EXTMEM_DCACHE_AUTOLOAD_DONE    (BIT(3))
-#define EXTMEM_DCACHE_AUTOLOAD_DONE_M  (BIT(3))
-#define EXTMEM_DCACHE_AUTOLOAD_DONE_V  0x1
-#define EXTMEM_DCACHE_AUTOLOAD_DONE_S  3
-/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable and disable autoload operation. It is combined with dc
-ache_autoload_done. 1: enable, 0: disable. .*/
-#define EXTMEM_DCACHE_AUTOLOAD_ENA    (BIT(2))
-#define EXTMEM_DCACHE_AUTOLOAD_ENA_M  (BIT(2))
-#define EXTMEM_DCACHE_AUTOLOAD_ENA_V  0x1
-#define EXTMEM_DCACHE_AUTOLOAD_ENA_S  2
-/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bits are used to enable the second section for autoload operation..*/
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA    (BIT(1))
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M  (BIT(1))
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V  0x1
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S  1
-/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bits are used to enable the first section for autoload operation..*/
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA    (BIT(0))
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M  (BIT(0))
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V  0x1
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S  0
-
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x50)
-/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address of the first section fo
-r autoload operation. It should be combined with dcache_autoload_sct0_ena..*/
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S))
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x54)
-/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: The bits are used to configure the length of the first section for autoload oper
-ation. It should be combined with dcache_autoload_sct0_ena..*/
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE    0x07FFFFFF
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S))
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V  0x7FFFFFF
-#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x58)
-/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address of the second section f
-or autoload operation. It should be combined with dcache_autoload_sct1_ena..*/
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S))
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x5C)
-/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: The bits are used to configure the length of the second section for autoload ope
-ration. It should be combined with dcache_autoload_sct1_ena..*/
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE    0x07FFFFFF
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S))
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V  0x7FFFFFF
-#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-#define EXTMEM_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x60)
-/* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes.*/
-#define EXTMEM_ICACHE_BLOCKSIZE_MODE    (BIT(3))
-#define EXTMEM_ICACHE_BLOCKSIZE_MODE_M  (BIT(3))
-#define EXTMEM_ICACHE_BLOCKSIZE_MODE_V  0x1
-#define EXTMEM_ICACHE_BLOCKSIZE_MODE_S  3
-/* EXTMEM_ICACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to configure cache memory size.0: 16KB, 1: 32KB.*/
-#define EXTMEM_ICACHE_SIZE_MODE    (BIT(2))
-#define EXTMEM_ICACHE_SIZE_MODE_M  (BIT(2))
-#define EXTMEM_ICACHE_SIZE_MODE_V  0x1
-#define EXTMEM_ICACHE_SIZE_MODE_S  2
-/* EXTMEM_ICACHE_WAY_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to configure cache way mode.0: 4-way, 1: 8-way.*/
-#define EXTMEM_ICACHE_WAY_MODE    (BIT(1))
-#define EXTMEM_ICACHE_WAY_MODE_M  (BIT(1))
-#define EXTMEM_ICACHE_WAY_MODE_V  0x1
-#define EXTMEM_ICACHE_WAY_MODE_S  1
-/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/
-#define EXTMEM_ICACHE_ENABLE    (BIT(0))
-#define EXTMEM_ICACHE_ENABLE_M  (BIT(0))
-#define EXTMEM_ICACHE_ENABLE_V  0x1
-#define EXTMEM_ICACHE_ENABLE_S  0
-
-#define EXTMEM_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x64)
-/* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to disable core1 ibus, 0: enable, 1: disable.*/
-#define EXTMEM_ICACHE_SHUT_CORE1_BUS    (BIT(1))
-#define EXTMEM_ICACHE_SHUT_CORE1_BUS_M  (BIT(1))
-#define EXTMEM_ICACHE_SHUT_CORE1_BUS_V  0x1
-#define EXTMEM_ICACHE_SHUT_CORE1_BUS_S  1
-/* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to disable core0 ibus, 0: enable, 1: disable.*/
-#define EXTMEM_ICACHE_SHUT_CORE0_BUS    (BIT(0))
-#define EXTMEM_ICACHE_SHUT_CORE0_BUS_M  (BIT(0))
-#define EXTMEM_ICACHE_SHUT_CORE0_BUS_V  0x1
-#define EXTMEM_ICACHE_SHUT_CORE0_BUS_S  0
-
-#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x68)
-/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up.*/
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU    (BIT(2))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V  0x1
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S  2
-/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power d
-own.*/
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD    (BIT(1))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V  0x1
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S  1
-/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of  icache tag memory. 1: close gating, 0:
- open clock gating..*/
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON    (BIT(0))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V  0x1
-#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S  0
-
-#define EXTMEM_ICACHE_PRELOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x6C)
-/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: The bit is used to enable the second section of prelock function..*/
-#define EXTMEM_ICACHE_PRELOCK_SCT1_EN    (BIT(1))
-#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V  0x1
-#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S  1
-/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The bit is used to enable the first section of prelock function..*/
-#define EXTMEM_ICACHE_PRELOCK_SCT0_EN    (BIT(0))
-#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M  (BIT(0))
-#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V  0x1
-#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S  0
-
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x70)
-/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to configure the first start virtual address of data prelock,
-which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG.*/
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S))
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S  0
-
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x74)
-/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to configure the second start virtual address of data prelock,
- which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG.*/
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S))
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S  0
-
-#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x78)
-/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
-/*description: The bits are used to configure the first length of data locking, which is combin
-ed with ICACHE_PRELOCK_SCT0_ADDR_REG.*/
-#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE    0x0000FFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S))
-#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V  0xFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S  16
-/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the second length of data locking, which is combi
-ned with ICACHE_PRELOCK_SCT1_ADDR_REG.*/
-#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE    0x0000FFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S))
-#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V  0xFFFF
-#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S  0
-
-#define EXTMEM_ICACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x7C)
-/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to indicate unlock/lock operation is finished..*/
-#define EXTMEM_ICACHE_LOCK_DONE    (BIT(2))
-#define EXTMEM_ICACHE_LOCK_DONE_M  (BIT(2))
-#define EXTMEM_ICACHE_LOCK_DONE_V  0x1
-#define EXTMEM_ICACHE_LOCK_DONE_S  2
-/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
- unlock operation done..*/
-#define EXTMEM_ICACHE_UNLOCK_ENA    (BIT(1))
-#define EXTMEM_ICACHE_UNLOCK_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_UNLOCK_ENA_V  0x1
-#define EXTMEM_ICACHE_UNLOCK_ENA_S  1
-/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
-ock operation done..*/
-#define EXTMEM_ICACHE_LOCK_ENA    (BIT(0))
-#define EXTMEM_ICACHE_LOCK_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_LOCK_ENA_V  0x1
-#define EXTMEM_ICACHE_LOCK_ENA_S  0
-
-#define EXTMEM_ICACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x80)
-/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for lock operations. It
- should be combined with ICACHE_LOCK_SIZE_REG..*/
-#define EXTMEM_ICACHE_LOCK_ADDR    0xFFFFFFFF
-#define EXTMEM_ICACHE_LOCK_ADDR_M  ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S))
-#define EXTMEM_ICACHE_LOCK_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_LOCK_ADDR_S  0
-
-#define EXTMEM_ICACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x84)
-/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the length for lock operations. The bits are the
-counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG..*/
-#define EXTMEM_ICACHE_LOCK_SIZE    0x0000FFFF
-#define EXTMEM_ICACHE_LOCK_SIZE_M  ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S))
-#define EXTMEM_ICACHE_LOCK_SIZE_V  0xFFFF
-#define EXTMEM_ICACHE_LOCK_SIZE_S  0
-
-#define EXTMEM_ICACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x88)
-/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to indicate invalidate operation is finished..*/
-#define EXTMEM_ICACHE_SYNC_DONE    (BIT(1))
-#define EXTMEM_ICACHE_SYNC_DONE_M  (BIT(1))
-#define EXTMEM_ICACHE_SYNC_DONE_V  0x1
-#define EXTMEM_ICACHE_SYNC_DONE_S  1
-/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
-fter invalidate operation done..*/
-#define EXTMEM_ICACHE_INVALIDATE_ENA    (BIT(0))
-#define EXTMEM_ICACHE_INVALIDATE_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_INVALIDATE_ENA_V  0x1
-#define EXTMEM_ICACHE_INVALIDATE_ENA_S  0
-
-#define EXTMEM_ICACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x8C)
-/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for clean operations. I
-t should be combined with ICACHE_SYNC_SIZE_REG..*/
-#define EXTMEM_ICACHE_SYNC_ADDR    0xFFFFFFFF
-#define EXTMEM_ICACHE_SYNC_ADDR_M  ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
-#define EXTMEM_ICACHE_SYNC_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_SYNC_ADDR_S  0
-
-#define EXTMEM_ICACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x90)
-/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
-/*description: The bits are used to configure the length for sync operations. The bits are the
-counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG..*/
-#define EXTMEM_ICACHE_SYNC_SIZE    0x007FFFFF
-#define EXTMEM_ICACHE_SYNC_SIZE_M  ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
-#define EXTMEM_ICACHE_SYNC_SIZE_V  0x7FFFFF
-#define EXTMEM_ICACHE_SYNC_SIZE_S  0
-
-#define EXTMEM_ICACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x94)
-/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to configure the direction of preload operation. 1: descending,
-0: ascending..*/
-#define EXTMEM_ICACHE_PRELOAD_ORDER    (BIT(2))
-#define EXTMEM_ICACHE_PRELOAD_ORDER_M  (BIT(2))
-#define EXTMEM_ICACHE_PRELOAD_ORDER_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_ORDER_S  2
-/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to indicate preload operation is finished..*/
-#define EXTMEM_ICACHE_PRELOAD_DONE    (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_DONE_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_DONE_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_DONE_S  1
-/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable preload operation. It will be cleared by hardware afte
-r preload operation done..*/
-#define EXTMEM_ICACHE_PRELOAD_ENA    (BIT(0))
-#define EXTMEM_ICACHE_PRELOAD_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_PRELOAD_ENA_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_ENA_S  0
-
-#define EXTMEM_ICACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x98)
-/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address for preload operation.
-It should be combined with ICACHE_PRELOAD_SIZE_REG..*/
-#define EXTMEM_ICACHE_PRELOAD_ADDR    0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOAD_ADDR_M  ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S))
-#define EXTMEM_ICACHE_PRELOAD_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_PRELOAD_ADDR_S  0
-
-#define EXTMEM_ICACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x9C)
-/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: The bits are used to configure the length for preload operation. The bits are th
-e counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG...*/
-#define EXTMEM_ICACHE_PRELOAD_SIZE    0x0000FFFF
-#define EXTMEM_ICACHE_PRELOAD_SIZE_M  ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S))
-#define EXTMEM_ICACHE_PRELOAD_SIZE_V  0xFFFF
-#define EXTMEM_ICACHE_PRELOAD_SIZE_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xA0)
-/* EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit is used to clear autoload buffer in icache..*/
-#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR    (BIT(9))
-#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_M  (BIT(9))
-#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S  9
-/* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */
-/*description: The bits are used to configure the numbers of the cache block for the issuing au
-toload operation..*/
-#define EXTMEM_ICACHE_AUTOLOAD_SIZE    0x00000003
-#define EXTMEM_ICACHE_AUTOLOAD_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SIZE_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SIZE_V  0x3
-#define EXTMEM_ICACHE_AUTOLOAD_SIZE_S  7
-/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
-/*description: The bits are used to configure trigger conditions for autoload. 0/3: cache miss,
- 1: cache hit, 2: both cache miss and hit..*/
-#define EXTMEM_ICACHE_AUTOLOAD_RQST    0x00000003
-#define EXTMEM_ICACHE_AUTOLOAD_RQST_M  ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S))
-#define EXTMEM_ICACHE_AUTOLOAD_RQST_V  0x3
-#define EXTMEM_ICACHE_AUTOLOAD_RQST_S  5
-/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bits are used to configure the direction of autoload. 1: descending, 0: asce
-nding..*/
-#define EXTMEM_ICACHE_AUTOLOAD_ORDER    (BIT(4))
-#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M  (BIT(4))
-#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S  4
-/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
-/*description: The bit is used to indicate autoload operation is finished..*/
-#define EXTMEM_ICACHE_AUTOLOAD_DONE    (BIT(3))
-#define EXTMEM_ICACHE_AUTOLOAD_DONE_M  (BIT(3))
-#define EXTMEM_ICACHE_AUTOLOAD_DONE_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_DONE_S  3
-/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable and disable autoload operation. It is combined with ic
-ache_autoload_done. 1: enable, 0: disable. .*/
-#define EXTMEM_ICACHE_AUTOLOAD_ENA    (BIT(2))
-#define EXTMEM_ICACHE_AUTOLOAD_ENA_M  (BIT(2))
-#define EXTMEM_ICACHE_AUTOLOAD_ENA_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_ENA_S  2
-/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bits are used to enable the second section for autoload operation..*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA    (BIT(1))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S  1
-/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bits are used to enable the first section for autoload operation..*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA    (BIT(0))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V  0x1
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xA4)
-/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address of the first section fo
-r autoload operation. It should be combined with icache_autoload_sct0_ena..*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xA8)
-/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: The bits are used to configure the length of the first section for autoload oper
-ation. It should be combined with icache_autoload_sct0_ena..*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE    0x07FFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V  0x7FFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xAC)
-/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address of the second section f
-or autoload operation. It should be combined with icache_autoload_sct1_ena..*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S  0
-
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xB0)
-/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
-/*description: The bits are used to configure the length of the second section for autoload ope
-ration. It should be combined with icache_autoload_sct1_ena..*/
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE    0x07FFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S))
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V  0x7FFFFFF
-#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S  0
-
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xB4)
-/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h44000000 ; */
-/*description: The bits are used to configure the start virtual address of ibus to access flash
-. The register is used to give constraints to ibus access counter..*/
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR    0xFFFFFFFF
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S))
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
-#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S  0
-
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xB8)
-/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h47ffffff ; */
-/*description: The bits are used to configure the end virtual address of ibus to access flash.
-The register is used to give constraints to ibus access counter..*/
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR    0xFFFFFFFF
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
-#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S  0
-
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xBC)
-/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the start virtual address of dbus to access flash
-. The register is used to give constraints to dbus access counter..*/
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR    0xFFFFFFFF
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S))
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
-#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S  0
-
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xC0)
-/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The bits are used to configure the end virtual address of dbus to access flash.
-The register is used to give constraints to dbus access counter..*/
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR    0xFFFFFFFF
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
-#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S  0
-
-#define EXTMEM_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0xC4)
-/* EXTMEM_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to clear icache counter..*/
-#define EXTMEM_ICACHE_ACS_CNT_CLR    (BIT(1))
-#define EXTMEM_ICACHE_ACS_CNT_CLR_M  (BIT(1))
-#define EXTMEM_ICACHE_ACS_CNT_CLR_V  0x1
-#define EXTMEM_ICACHE_ACS_CNT_CLR_S  1
-/* EXTMEM_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to clear dcache counter..*/
-#define EXTMEM_DCACHE_ACS_CNT_CLR    (BIT(0))
-#define EXTMEM_DCACHE_ACS_CNT_CLR_M  (BIT(0))
-#define EXTMEM_DCACHE_ACS_CNT_CLR_V  0x1
-#define EXTMEM_DCACHE_ACS_CNT_CLR_S  0
-
-#define EXTMEM_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xC8)
-/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of the cache miss caused by ibus access fl
-ash/spiram..*/
-#define EXTMEM_IBUS_ACS_MISS_CNT    0xFFFFFFFF
-#define EXTMEM_IBUS_ACS_MISS_CNT_M  ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S))
-#define EXTMEM_IBUS_ACS_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_IBUS_ACS_MISS_CNT_S  0
-
-#define EXTMEM_IBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xCC)
-/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of ibus access flash/spiram through icache
-..*/
-#define EXTMEM_IBUS_ACS_CNT    0xFFFFFFFF
-#define EXTMEM_IBUS_ACS_CNT_M  ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S))
-#define EXTMEM_IBUS_ACS_CNT_V  0xFFFFFFFF
-#define EXTMEM_IBUS_ACS_CNT_S  0
-
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xD0)
-/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of the cache miss caused by dbus access fl
-ash..*/
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT    0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M  ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S))
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S  0
-
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xD4)
-/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of the cache miss caused by dbus access sp
-iram..*/
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT    0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M  ((EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S))
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V  0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S  0
-
-#define EXTMEM_DBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xD8)
-/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to count the number of dbus access flash/spiram through dcache
-..*/
-#define EXTMEM_DBUS_ACS_CNT    0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_CNT_M  ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S))
-#define EXTMEM_DBUS_ACS_CNT_V  0xFFFFFFFF
-#define EXTMEM_DBUS_ACS_CNT_S  0
-
-#define EXTMEM_CACHE_ILG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0xDC)
-/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by dbus counter overflow..*/
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA    (BIT(8))
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M  (BIT(8))
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V  0x1
-#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S  8
-/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by ibus counter overflow..*/
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA    (BIT(7))
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M  (BIT(7))
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V  0x1
-#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S  7
-/* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by dcache trying to replace a line whose blo
-cks all have been occupied by occupy-mode..*/
-#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA    (BIT(6))
-#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M  (BIT(6))
-#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V  0x1
-#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S  6
-/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by mmu entry fault..*/
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA    (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V  0x1
-#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S  5
-/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by dcache trying to write flash..*/
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA    (BIT(4))
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M  (BIT(4))
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V  0x1
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S  4
-/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by preload configurations fault..*/
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA    (BIT(3))
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M  (BIT(3))
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S  3
-/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by sync configurations fault..*/
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA    (BIT(2))
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M  (BIT(2))
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V  0x1
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S  2
-/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by preload configurations fault..*/
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA    (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S  1
-/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by sync configurations fault..*/
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA    (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V  0x1
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S  0
-
-#define EXTMEM_CACHE_ILG_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0xE0)
-/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by dbus counter overflow..*/
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR    (BIT(8))
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M  (BIT(8))
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V  0x1
-#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S  8
-/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by ibus counter overflow..*/
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR    (BIT(7))
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M  (BIT(7))
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V  0x1
-#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S  7
-/* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by dcache trying to replace a line whose bloc
-ks all have been occupied by occupy-mode..*/
-#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR    (BIT(6))
-#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M  (BIT(6))
-#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V  0x1
-#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S  6
-/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by mmu entry fault..*/
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR    (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V  0x1
-#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S  5
-/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by dcache trying to write flash..*/
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR    (BIT(4))
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M  (BIT(4))
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V  0x1
-#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S  4
-/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by preload configurations fault..*/
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR    (BIT(3))
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M  (BIT(3))
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S  3
-/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by sync configurations fault..*/
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR    (BIT(2))
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M  (BIT(2))
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V  0x1
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S  2
-/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by preload configurations fault..*/
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR    (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S  1
-/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by sync configurations fault..*/
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR    (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V  0x1
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S  0
-
-#define EXTMEM_CACHE_ILG_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0xE4)
-/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by dbus access spiram miss counter overflo
-w..*/
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST    (BIT(11))
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_M  (BIT(11))
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V  0x1
-#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S  11
-/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by dbus access flash miss counter overflow
-..*/
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST    (BIT(10))
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M  (BIT(10))
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V  0x1
-#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S  10
-/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overfl
-ow..*/
-#define EXTMEM_DBUS_ACS_CNT_OVF_ST    (BIT(9))
-#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M  (BIT(9))
-#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V  0x1
-#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S  9
-/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter o
-verflow..*/
-#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST    (BIT(8))
-#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
-#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V  0x1
-#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S  8
-/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overfl
-ow..*/
-#define EXTMEM_IBUS_ACS_CNT_OVF_ST    (BIT(7))
-#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M  (BIT(7))
-#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V  0x1
-#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S  7
-/* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by dcache trying to replace a line whose b
-locks all have been occupied by occupy-mode..*/
-#define EXTMEM_DCACHE_OCCUPY_EXC_ST    (BIT(6))
-#define EXTMEM_DCACHE_OCCUPY_EXC_ST_M  (BIT(6))
-#define EXTMEM_DCACHE_OCCUPY_EXC_ST_V  0x1
-#define EXTMEM_DCACHE_OCCUPY_EXC_ST_S  6
-/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by mmu entry fault..*/
-#define EXTMEM_MMU_ENTRY_FAULT_ST    (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_ST_M  (BIT(5))
-#define EXTMEM_MMU_ENTRY_FAULT_ST_V  0x1
-#define EXTMEM_MMU_ENTRY_FAULT_ST_S  5
-/* EXTMEM_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by dcache trying to write flash..*/
-#define EXTMEM_DCACHE_WRITE_FLASH_ST    (BIT(4))
-#define EXTMEM_DCACHE_WRITE_FLASH_ST_M  (BIT(4))
-#define EXTMEM_DCACHE_WRITE_FLASH_ST_V  0x1
-#define EXTMEM_DCACHE_WRITE_FLASH_ST_S  4
-/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by preload configurations fault..*/
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST    (BIT(3))
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_M  (BIT(3))
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S  3
-/* EXTMEM_DCACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by sync configurations fault..*/
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST    (BIT(2))
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_M  (BIT(2))
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V  0x1
-#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S  2
-/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by preload configurations fault..*/
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST    (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S  1
-/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by sync configurations fault..*/
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST    (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V  0x1
-#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S  0
-
-#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0xE8)
-/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by authentication fail..*/
-#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA    (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V  0x1
-#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S  4
-/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by cpu access dcache while the corresponding
- dbus is disabled which include speculative access..*/
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA    (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V  0x1
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S  3
-/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by authentication fail..*/
-#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA    (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V  0x1
-#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S  2
-/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by ibus trying to write icache.*/
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA    (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V  0x1
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S  1
-/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by cpu access icache while the corresponding
- ibus is disabled which include speculative access..*/
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA    (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S  0
-
-#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0xEC)
-/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by authentication fail..*/
-#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR    (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V  0x1
-#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S  4
-/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by cpu access dcache while the corresponding
-dbus is disabled or dcache is disabled which include speculative access..*/
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR    (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_M  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V  0x1
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S  3
-/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by authentication fail..*/
-#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR    (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V  0x1
-#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S  2
-/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by ibus trying to write icache.*/
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR    (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V  0x1
-#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S  1
-/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by cpu access icache while the corresponding
-ibus is disabled or icache is disabled which include speculative access..*/
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR    (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
-#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S  0
-
-#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0xF0)
-/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by authentication fail..*/
-#define EXTMEM_CORE0_DBUS_REJECT_ST    (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_ST_M  (BIT(4))
-#define EXTMEM_CORE0_DBUS_REJECT_ST_V  0x1
-#define EXTMEM_CORE0_DBUS_REJECT_ST_S  4
-/* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by cpu access dcache while the core0_dbus
-is disabled or dcache is disabled which include speculative access..*/
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST    (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_M  (BIT(3))
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V  0x1
-#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S  3
-/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by authentication fail..*/
-#define EXTMEM_CORE0_IBUS_REJECT_ST    (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_ST_M  (BIT(2))
-#define EXTMEM_CORE0_IBUS_REJECT_ST_V  0x1
-#define EXTMEM_CORE0_IBUS_REJECT_ST_S  2
-/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/
-#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST    (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M  (BIT(1))
-#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V  0x1
-#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S  1
-/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by cpu access  icache while the core0_ibus
- is disabled or icache is disabled which include speculative access..*/
-#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST    (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M  (BIT(0))
-#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V  0x1
-#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S  0
-
-#define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0xF4)
-/* EXTMEM_CORE1_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by authentication fail..*/
-#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA    (BIT(4))
-#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_M  (BIT(4))
-#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V  0x1
-#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S  4
-/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by cpu access dcache while the corresponding
- dbus is disabled which include speculative access..*/
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA    (BIT(3))
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M  (BIT(3))
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V  0x1
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S  3
-/* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by authentication fail..*/
-#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA    (BIT(2))
-#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_M  (BIT(2))
-#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V  0x1
-#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S  2
-/* EXTMEM_CORE1_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by ibus trying to write icache.*/
-#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA    (BIT(1))
-#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_M  (BIT(1))
-#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V  0x1
-#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S  1
-/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable interrupt by cpu access icache while the corresponding
- ibus is disabled which include speculative access..*/
-#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA    (BIT(0))
-#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(0))
-#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
-#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S  0
-
-#define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0xF8)
-/* EXTMEM_CORE1_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by authentication fail..*/
-#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR    (BIT(4))
-#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_M  (BIT(4))
-#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V  0x1
-#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S  4
-/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by cpu access dcache while the corresponding
-dbus is disabled or dcache is disabled which include speculative access..*/
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR    (BIT(3))
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_M  (BIT(3))
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V  0x1
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S  3
-/* EXTMEM_CORE1_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by authentication fail..*/
-#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR    (BIT(2))
-#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M  (BIT(2))
-#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V  0x1
-#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S  2
-/* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by ibus trying to write icache.*/
-#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR    (BIT(1))
-#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_M  (BIT(1))
-#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V  0x1
-#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S  1
-/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to clear interrupt by cpu access icache while the corresponding
-ibus is disabled or icache is disabled which include speculative access..*/
-#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR    (BIT(0))
-#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
-#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
-#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S  0
-
-#define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0xFC)
-/* EXTMEM_CORE1_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by authentication fail..*/
-#define EXTMEM_CORE1_DBUS_REJECT_ST    (BIT(4))
-#define EXTMEM_CORE1_DBUS_REJECT_ST_M  (BIT(4))
-#define EXTMEM_CORE1_DBUS_REJECT_ST_V  0x1
-#define EXTMEM_CORE1_DBUS_REJECT_ST_S  4
-/* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by cpu access dcache while the core1_dbus
-is disabled or dcache is disabled which include speculative access..*/
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST    (BIT(3))
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_M  (BIT(3))
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V  0x1
-#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S  3
-/* EXTMEM_CORE1_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by authentication fail..*/
-#define EXTMEM_CORE1_IBUS_REJECT_ST    (BIT(2))
-#define EXTMEM_CORE1_IBUS_REJECT_ST_M  (BIT(2))
-#define EXTMEM_CORE1_IBUS_REJECT_ST_V  0x1
-#define EXTMEM_CORE1_IBUS_REJECT_ST_S  2
-/* EXTMEM_CORE1_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/
-#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST    (BIT(1))
-#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M  (BIT(1))
-#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V  0x1
-#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S  1
-/* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate interrupt by cpu access  icache while the core1_ibus
- is disabled or  icache is disabled which include speculative access..*/
-#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST    (BIT(0))
-#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_M  (BIT(0))
-#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V  0x1
-#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S  0
-
-#define EXTMEM_CORE0_DBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x100)
-/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the world of CPU access dbus when authentication fai
-l. 0: WORLD0, 1: WORLD1.*/
-#define EXTMEM_CORE0_DBUS_WORLD    (BIT(6))
-#define EXTMEM_CORE0_DBUS_WORLD_M  (BIT(6))
-#define EXTMEM_CORE0_DBUS_WORLD_V  0x1
-#define EXTMEM_CORE0_DBUS_WORLD_S  6
-/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati
-on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
-#define EXTMEM_CORE0_DBUS_ATTR    0x00000007
-#define EXTMEM_CORE0_DBUS_ATTR_M  ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
-#define EXTMEM_CORE0_DBUS_ATTR_V  0x7
-#define EXTMEM_CORE0_DBUS_ATTR_S  3
-/* EXTMEM_CORE0_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of data from external memory when au
-thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
-#define EXTMEM_CORE0_DBUS_TAG_ATTR    0x00000007
-#define EXTMEM_CORE0_DBUS_TAG_ATTR_M  ((EXTMEM_CORE0_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_DBUS_TAG_ATTR_S))
-#define EXTMEM_CORE0_DBUS_TAG_ATTR_V  0x7
-#define EXTMEM_CORE0_DBUS_TAG_ATTR_S  0
-
-#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x104)
-/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: The bits are used to indicate the virtual address of CPU access dbus when authen
-tication fail..*/
-#define EXTMEM_CORE0_DBUS_VADDR    0xFFFFFFFF
-#define EXTMEM_CORE0_DBUS_VADDR_M  ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
-#define EXTMEM_CORE0_DBUS_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CORE0_DBUS_VADDR_S  0
-
-#define EXTMEM_CORE0_IBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x108)
-/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the world of CPU access ibus when authentication fai
-l. 0: WORLD0, 1: WORLD1.*/
-#define EXTMEM_CORE0_IBUS_WORLD    (BIT(6))
-#define EXTMEM_CORE0_IBUS_WORLD_M  (BIT(6))
-#define EXTMEM_CORE0_IBUS_WORLD_V  0x1
-#define EXTMEM_CORE0_IBUS_WORLD_S  6
-/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati
-on fail. 0: invalidate, 1: execute-able, 2: read-able.*/
-#define EXTMEM_CORE0_IBUS_ATTR    0x00000007
-#define EXTMEM_CORE0_IBUS_ATTR_M  ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S))
-#define EXTMEM_CORE0_IBUS_ATTR_V  0x7
-#define EXTMEM_CORE0_IBUS_ATTR_S  3
-/* EXTMEM_CORE0_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of data from external memory when au
-thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
-#define EXTMEM_CORE0_IBUS_TAG_ATTR    0x00000007
-#define EXTMEM_CORE0_IBUS_TAG_ATTR_M  ((EXTMEM_CORE0_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_IBUS_TAG_ATTR_S))
-#define EXTMEM_CORE0_IBUS_TAG_ATTR_V  0x7
-#define EXTMEM_CORE0_IBUS_TAG_ATTR_S  0
-
-#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x10C)
-/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: The bits are used to indicate the virtual address of CPU access  ibus when authe
-ntication fail..*/
-#define EXTMEM_CORE0_IBUS_VADDR    0xFFFFFFFF
-#define EXTMEM_CORE0_IBUS_VADDR_M  ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
-#define EXTMEM_CORE0_IBUS_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CORE0_IBUS_VADDR_S  0
-
-#define EXTMEM_CORE1_DBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x110)
-/* EXTMEM_CORE1_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the world of CPU access dbus when authentication fai
-l. 0: WORLD0, 1: WORLD1.*/
-#define EXTMEM_CORE1_DBUS_WORLD    (BIT(6))
-#define EXTMEM_CORE1_DBUS_WORLD_M  (BIT(6))
-#define EXTMEM_CORE1_DBUS_WORLD_V  0x1
-#define EXTMEM_CORE1_DBUS_WORLD_S  6
-/* EXTMEM_CORE1_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati
-on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
-#define EXTMEM_CORE1_DBUS_ATTR    0x00000007
-#define EXTMEM_CORE1_DBUS_ATTR_M  ((EXTMEM_CORE1_DBUS_ATTR_V)<<(EXTMEM_CORE1_DBUS_ATTR_S))
-#define EXTMEM_CORE1_DBUS_ATTR_V  0x7
-#define EXTMEM_CORE1_DBUS_ATTR_S  3
-/* EXTMEM_CORE1_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of data from external memory when au
-thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
-#define EXTMEM_CORE1_DBUS_TAG_ATTR    0x00000007
-#define EXTMEM_CORE1_DBUS_TAG_ATTR_M  ((EXTMEM_CORE1_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_DBUS_TAG_ATTR_S))
-#define EXTMEM_CORE1_DBUS_TAG_ATTR_V  0x7
-#define EXTMEM_CORE1_DBUS_TAG_ATTR_S  0
-
-#define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x114)
-/* EXTMEM_CORE1_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: The bits are used to indicate the virtual address of CPU access dbus when authen
-tication fail..*/
-#define EXTMEM_CORE1_DBUS_VADDR    0xFFFFFFFF
-#define EXTMEM_CORE1_DBUS_VADDR_M  ((EXTMEM_CORE1_DBUS_VADDR_V)<<(EXTMEM_CORE1_DBUS_VADDR_S))
-#define EXTMEM_CORE1_DBUS_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CORE1_DBUS_VADDR_S  0
-
-#define EXTMEM_CORE1_IBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x118)
-/* EXTMEM_CORE1_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the world of CPU access ibus when authentication fai
-l. 0: WORLD0, 1: WORLD1.*/
-#define EXTMEM_CORE1_IBUS_WORLD    (BIT(6))
-#define EXTMEM_CORE1_IBUS_WORLD_M  (BIT(6))
-#define EXTMEM_CORE1_IBUS_WORLD_V  0x1
-#define EXTMEM_CORE1_IBUS_WORLD_S  6
-/* EXTMEM_CORE1_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati
-on fail. 0: invalidate, 1: execute-able, 2: read-able.*/
-#define EXTMEM_CORE1_IBUS_ATTR    0x00000007
-#define EXTMEM_CORE1_IBUS_ATTR_M  ((EXTMEM_CORE1_IBUS_ATTR_V)<<(EXTMEM_CORE1_IBUS_ATTR_S))
-#define EXTMEM_CORE1_IBUS_ATTR_V  0x7
-#define EXTMEM_CORE1_IBUS_ATTR_S  3
-/* EXTMEM_CORE1_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: The bits are used to indicate the attribute of data from external memory when au
-thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
-#define EXTMEM_CORE1_IBUS_TAG_ATTR    0x00000007
-#define EXTMEM_CORE1_IBUS_TAG_ATTR_M  ((EXTMEM_CORE1_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_IBUS_TAG_ATTR_S))
-#define EXTMEM_CORE1_IBUS_TAG_ATTR_V  0x7
-#define EXTMEM_CORE1_IBUS_TAG_ATTR_S  0
-
-#define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x11C)
-/* EXTMEM_CORE1_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: The bits are used to indicate the virtual address of CPU access  ibus when authe
-ntication fail..*/
-#define EXTMEM_CORE1_IBUS_VADDR    0xFFFFFFFF
-#define EXTMEM_CORE1_IBUS_VADDR_M  ((EXTMEM_CORE1_IBUS_VADDR_V)<<(EXTMEM_CORE1_IBUS_VADDR_S))
-#define EXTMEM_CORE1_IBUS_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CORE1_IBUS_VADDR_S  0
-
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x120)
-/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[19:16] ;default: 4'h0 ; */
-/*description: The right-most 3 bits are used to indicate the operations which cause mmu fault
-occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
-evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
- 7: external dma rx. The most significant bit is used to indicate this operation
- occurs in which one icache. .*/
-#define EXTMEM_CACHE_MMU_FAULT_CODE    0x0000000F
-#define EXTMEM_CACHE_MMU_FAULT_CODE_M  ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S))
-#define EXTMEM_CACHE_MMU_FAULT_CODE_V  0xF
-#define EXTMEM_CACHE_MMU_FAULT_CODE_S  16
-/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[15:0] ;default: 17'h0 ; */
-/*description: The bits are used to indicate the content of mmu entry which cause mmu fault...*/
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT    0x0000FFFF
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M  ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V  0xFFFF
-#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S  0
-
-#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x124)
-/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: The bits are used to indicate the virtual address which cause mmu fault...*/
-#define EXTMEM_CACHE_MMU_FAULT_VADDR    0xFFFFFFFF
-#define EXTMEM_CACHE_MMU_FAULT_VADDR_M  ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
-#define EXTMEM_CACHE_MMU_FAULT_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CACHE_MMU_FAULT_VADDR_S  0
-
-#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x128)
-/* EXTMEM_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable wrap around mode when read data from spiram..*/
-#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND    (BIT(1))
-#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_M  (BIT(1))
-#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V  0x1
-#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S  1
-/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable wrap around mode when read data from flash..*/
-#define EXTMEM_CACHE_FLASH_WRAP_AROUND    (BIT(0))
-#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
-#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V  0x1
-#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S  0
-
-#define EXTMEM_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x12C)
-/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up.*/
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PU    (BIT(2))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M  (BIT(2))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V  0x1
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S  2
-/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down.*/
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PD    (BIT(1))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M  (BIT(1))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V  0x1
-#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S  1
-/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to enable clock gating to save power when access mmu memory, 0:
-enable, 1: disable.*/
-#define EXTMEM_CACHE_MMU_MEM_FORCE_ON    (BIT(0))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
-#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V  0x1
-#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S  0
-
-#define EXTMEM_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x130)
-/* EXTMEM_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h001 ; */
-/*description: The bit is used to indicate whether dcache main fsm is in idle state or not. 1:
-in idle state,  0: not in idle state.*/
-#define EXTMEM_DCACHE_STATE    0x00000FFF
-#define EXTMEM_DCACHE_STATE_M  ((EXTMEM_DCACHE_STATE_V)<<(EXTMEM_DCACHE_STATE_S))
-#define EXTMEM_DCACHE_STATE_V  0xFFF
-#define EXTMEM_DCACHE_STATE_S  12
-/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h001 ; */
-/*description: The bit is used to indicate whether  icache main fsm is in idle state or not. 1:
- in idle state,  0: not in idle state.*/
-#define EXTMEM_ICACHE_STATE    0x00000FFF
-#define EXTMEM_ICACHE_STATE_M  ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
-#define EXTMEM_ICACHE_STATE_V  0xFFF
-#define EXTMEM_ICACHE_STATE_S  0
-
-#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0x134)
-/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Reserved..*/
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT    (BIT(1))
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
-#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S  1
-/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Reserved..*/
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT    (BIT(0))
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V  0x1
-#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S  0
-
-#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0x138)
-/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of external memory encrypt and decrypt clo
-ck. 1: close gating, 0: open clock gating..*/
-#define EXTMEM_CLK_FORCE_ON_CRYPT    (BIT(2))
-#define EXTMEM_CLK_FORCE_ON_CRYPT_M  (BIT(2))
-#define EXTMEM_CLK_FORCE_ON_CRYPT_V  0x1
-#define EXTMEM_CLK_FORCE_ON_CRYPT_S  2
-/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of automatic crypt clock. 1: close gating,
- 0: open clock gating..*/
-#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT    (BIT(1))
-#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M  (BIT(1))
-#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V  0x1
-#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S  1
-/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to close clock gating of manual crypt clock. 1: close gating, 0:
- open clock gating..*/
-#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT    (BIT(0))
-#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M  (BIT(0))
-#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V  0x1
-#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S  0
-
-#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x13C)
-/* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Reserved..*/
-#define EXTMEM_ALLOC_WB_HOLD_ARBITER    (BIT(0))
-#define EXTMEM_ALLOC_WB_HOLD_ARBITER_M  (BIT(0))
-#define EXTMEM_ALLOC_WB_HOLD_ARBITER_V  0x1
-#define EXTMEM_ALLOC_WB_HOLD_ARBITER_S  0
-
-#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x140)
-/* EXTMEM_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear the interrupt by dcache pre-load done..*/
-#define EXTMEM_DCACHE_PRELOAD_INT_CLR    (BIT(5))
-#define EXTMEM_DCACHE_PRELOAD_INT_CLR_M  (BIT(5))
-#define EXTMEM_DCACHE_PRELOAD_INT_CLR_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_INT_CLR_S  5
-/* EXTMEM_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt by dcache pre-load done..*/
-#define EXTMEM_DCACHE_PRELOAD_INT_ENA    (BIT(4))
-#define EXTMEM_DCACHE_PRELOAD_INT_ENA_M  (BIT(4))
-#define EXTMEM_DCACHE_PRELOAD_INT_ENA_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_INT_ENA_S  4
-/* EXTMEM_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the interrupt by dcache pre-load done..*/
-#define EXTMEM_DCACHE_PRELOAD_INT_ST    (BIT(3))
-#define EXTMEM_DCACHE_PRELOAD_INT_ST_M  (BIT(3))
-#define EXTMEM_DCACHE_PRELOAD_INT_ST_V  0x1
-#define EXTMEM_DCACHE_PRELOAD_INT_ST_S  3
-/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to clear the interrupt by  icache pre-load done..*/
-#define EXTMEM_ICACHE_PRELOAD_INT_CLR    (BIT(2))
-#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
-#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S  2
-/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt by  icache pre-load done..*/
-#define EXTMEM_ICACHE_PRELOAD_INT_ENA    (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S  1
-/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the interrupt by  icache pre-load done..*/
-#define EXTMEM_ICACHE_PRELOAD_INT_ST    (BIT(0))
-#define EXTMEM_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
-#define EXTMEM_ICACHE_PRELOAD_INT_ST_V  0x1
-#define EXTMEM_ICACHE_PRELOAD_INT_ST_S  0
-
-#define EXTMEM_CACHE_SYNC_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x144)
-/* EXTMEM_DCACHE_SYNC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The bit is used to clear the interrupt by dcache sync done..*/
-#define EXTMEM_DCACHE_SYNC_INT_CLR    (BIT(5))
-#define EXTMEM_DCACHE_SYNC_INT_CLR_M  (BIT(5))
-#define EXTMEM_DCACHE_SYNC_INT_CLR_V  0x1
-#define EXTMEM_DCACHE_SYNC_INT_CLR_S  5
-/* EXTMEM_DCACHE_SYNC_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt by dcache sync done..*/
-#define EXTMEM_DCACHE_SYNC_INT_ENA    (BIT(4))
-#define EXTMEM_DCACHE_SYNC_INT_ENA_M  (BIT(4))
-#define EXTMEM_DCACHE_SYNC_INT_ENA_V  0x1
-#define EXTMEM_DCACHE_SYNC_INT_ENA_S  4
-/* EXTMEM_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the interrupt by dcache sync done..*/
-#define EXTMEM_DCACHE_SYNC_INT_ST    (BIT(3))
-#define EXTMEM_DCACHE_SYNC_INT_ST_M  (BIT(3))
-#define EXTMEM_DCACHE_SYNC_INT_ST_V  0x1
-#define EXTMEM_DCACHE_SYNC_INT_ST_S  3
-/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The bit is used to clear the interrupt by  icache sync done..*/
-#define EXTMEM_ICACHE_SYNC_INT_CLR    (BIT(2))
-#define EXTMEM_ICACHE_SYNC_INT_CLR_M  (BIT(2))
-#define EXTMEM_ICACHE_SYNC_INT_CLR_V  0x1
-#define EXTMEM_ICACHE_SYNC_INT_CLR_S  2
-/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to enable the interrupt by  icache sync done..*/
-#define EXTMEM_ICACHE_SYNC_INT_ENA    (BIT(1))
-#define EXTMEM_ICACHE_SYNC_INT_ENA_M  (BIT(1))
-#define EXTMEM_ICACHE_SYNC_INT_ENA_V  0x1
-#define EXTMEM_ICACHE_SYNC_INT_ENA_S  1
-/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to indicate the interrupt by  icache sync done..*/
-#define EXTMEM_ICACHE_SYNC_INT_ST    (BIT(0))
-#define EXTMEM_ICACHE_SYNC_INT_ST_M  (BIT(0))
-#define EXTMEM_ICACHE_SYNC_INT_ST_V  0x1
-#define EXTMEM_ICACHE_SYNC_INT_ST_S  0
-
-#define EXTMEM_CACHE_MMU_OWNER_REG          (DR_REG_EXTMEM_BASE + 0x148)
-/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
-/*description: The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2:
-dma, bit3: reserved..*/
-#define EXTMEM_CACHE_MMU_OWNER    0x00FFFFFF
-#define EXTMEM_CACHE_MMU_OWNER_M  ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
-#define EXTMEM_CACHE_MMU_OWNER_V  0xFFFFFF
-#define EXTMEM_CACHE_MMU_OWNER_S  0
-
-#define EXTMEM_CACHE_CONF_MISC_REG          (DR_REG_EXTMEM_BASE + 0x14C)
-/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to enable cache trace function..*/
-#define EXTMEM_CACHE_TRACE_ENA    (BIT(2))
-#define EXTMEM_CACHE_TRACE_ENA_M  (BIT(2))
-#define EXTMEM_CACHE_TRACE_ENA_V  0x1
-#define EXTMEM_CACHE_TRACE_ENA_S  2
-/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: The bit is used to disable checking mmu entry fault by sync operation..*/
-#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT    (BIT(1))
-#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M  (BIT(1))
-#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V  0x1
-#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S  1
-/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to disable checking mmu entry fault by preload operation..*/
-#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT    (BIT(0))
-#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M  (BIT(0))
-#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V  0x1
-#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S  0
-
-#define EXTMEM_DCACHE_FREEZE_REG          (DR_REG_EXTMEM_BASE + 0x150)
-/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to indicate dcache freeze success.*/
-#define EXTMEM_DCACHE_FREEZE_DONE    (BIT(2))
-#define EXTMEM_DCACHE_FREEZE_DONE_M  (BIT(2))
-#define EXTMEM_DCACHE_FREEZE_DONE_V  0x1
-#define EXTMEM_DCACHE_FREEZE_DONE_S  2
-/* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert
-hit if CPU miss.*/
-#define EXTMEM_DCACHE_FREEZE_MODE    (BIT(1))
-#define EXTMEM_DCACHE_FREEZE_MODE_M  (BIT(1))
-#define EXTMEM_DCACHE_FREEZE_MODE_V  0x1
-#define EXTMEM_DCACHE_FREEZE_MODE_S  1
-/* EXTMEM_DCACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable dcache freeze mode.*/
-#define EXTMEM_DCACHE_FREEZE_ENA    (BIT(0))
-#define EXTMEM_DCACHE_FREEZE_ENA_M  (BIT(0))
-#define EXTMEM_DCACHE_FREEZE_ENA_V  0x1
-#define EXTMEM_DCACHE_FREEZE_ENA_S  0
-
-#define EXTMEM_ICACHE_FREEZE_REG          (DR_REG_EXTMEM_BASE + 0x154)
-/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
-/*description: The bit is used to indicate icache freeze success.*/
-#define EXTMEM_ICACHE_FREEZE_DONE    (BIT(2))
-#define EXTMEM_ICACHE_FREEZE_DONE_M  (BIT(2))
-#define EXTMEM_ICACHE_FREEZE_DONE_V  0x1
-#define EXTMEM_ICACHE_FREEZE_DONE_S  2
-/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert
-hit if CPU miss.*/
-#define EXTMEM_ICACHE_FREEZE_MODE    (BIT(1))
-#define EXTMEM_ICACHE_FREEZE_MODE_M  (BIT(1))
-#define EXTMEM_ICACHE_FREEZE_MODE_V  0x1
-#define EXTMEM_ICACHE_FREEZE_MODE_S  1
-/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to enable icache freeze mode.*/
-#define EXTMEM_ICACHE_FREEZE_ENA    (BIT(0))
-#define EXTMEM_ICACHE_FREEZE_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_FREEZE_ENA_V  0x1
-#define EXTMEM_ICACHE_FREEZE_ENA_S  0
-
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG          (DR_REG_EXTMEM_BASE + 0x158)
-/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to activate icache atomic operation protection. In this case, sy
-nc/lock operation can not interrupt miss-work. This feature does not work during
- invalidateAll operation..*/
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA    (BIT(0))
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M  (BIT(0))
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V  0x1
-#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S  0
-
-#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG          (DR_REG_EXTMEM_BASE + 0x15C)
-/* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: The bit is used to activate dcache atomic operation protection. In this case, sy
-nc/lock/occupy operation can not interrupt miss-work. This feature does not work
- during invalidateAll operation..*/
-#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA    (BIT(0))
-#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M  (BIT(0))
-#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V  0x1
-#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S  0
-
-#define EXTMEM_CACHE_REQUEST_REG          (DR_REG_EXTMEM_BASE + 0x160)
-/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The bit is used to disable request recording which could cause performance issue.*/
-#define EXTMEM_CACHE_REQUEST_BYPASS    (BIT(0))
-#define EXTMEM_CACHE_REQUEST_BYPASS_M  (BIT(0))
-#define EXTMEM_CACHE_REQUEST_BYPASS_V  0x1
-#define EXTMEM_CACHE_REQUEST_BYPASS_S  0
-
-#define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x164)
-/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Reserved..*/
-#define EXTMEM_CLK_EN    (BIT(0))
-#define EXTMEM_CLK_EN_M  (BIT(0))
-#define EXTMEM_CLK_EN_V  0x1
-#define EXTMEM_CLK_EN_S  0
-
-#define EXTMEM_CACHE_TAG_OBJECT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x180)
-/* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to set dcache tag memory as object. This bit should be onehot with
-the others fields inside this register..*/
-#define EXTMEM_DCACHE_TAG_OBJECT    (BIT(1))
-#define EXTMEM_DCACHE_TAG_OBJECT_M  (BIT(1))
-#define EXTMEM_DCACHE_TAG_OBJECT_V  0x1
-#define EXTMEM_DCACHE_TAG_OBJECT_S  1
-/* EXTMEM_ICACHE_TAG_OBJECT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to set icache tag memory as object. This bit should be onehot with
-the others fields inside this register..*/
-#define EXTMEM_ICACHE_TAG_OBJECT    (BIT(0))
-#define EXTMEM_ICACHE_TAG_OBJECT_M  (BIT(0))
-#define EXTMEM_ICACHE_TAG_OBJECT_V  0x1
-#define EXTMEM_ICACHE_TAG_OBJECT_S  0
-
-#define EXTMEM_CACHE_TAG_WAY_OBJECT_REG          (DR_REG_EXTMEM_BASE + 0x184)
-/* EXTMEM_CACHE_TAG_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
-: way1, 2: way2, 3: way3, .., 7: way7..*/
-#define EXTMEM_CACHE_TAG_WAY_OBJECT    0x00000007
-#define EXTMEM_CACHE_TAG_WAY_OBJECT_M  ((EXTMEM_CACHE_TAG_WAY_OBJECT_V)<<(EXTMEM_CACHE_TAG_WAY_OBJECT_S))
-#define EXTMEM_CACHE_TAG_WAY_OBJECT_V  0x7
-#define EXTMEM_CACHE_TAG_WAY_OBJECT_S  0
-
-#define EXTMEM_CACHE_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x188)
-/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */
-/*description: Those bits stores the virtual address which will decide where inside the specifi
-ed tag memory object will be accessed..*/
-#define EXTMEM_CACHE_VADDR    0xFFFFFFFF
-#define EXTMEM_CACHE_VADDR_M  ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S))
-#define EXTMEM_CACHE_VADDR_V  0xFFFFFFFF
-#define EXTMEM_CACHE_VADDR_S  0
-
-#define EXTMEM_CACHE_TAG_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x18C)
-/* EXTMEM_CACHE_TAG_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: This is a constant place where we can write data to or read data from the tag me
-mory on the specified cache..*/
-#define EXTMEM_CACHE_TAG_CONTENT    0xFFFFFFFF
-#define EXTMEM_CACHE_TAG_CONTENT_M  ((EXTMEM_CACHE_TAG_CONTENT_V)<<(EXTMEM_CACHE_TAG_CONTENT_S))
-#define EXTMEM_CACHE_TAG_CONTENT_V  0xFFFFFFFF
-#define EXTMEM_CACHE_TAG_CONTENT_S  0
-
-#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
-/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012310 ; */
-/*description: version information..*/
-#define EXTMEM_DATE    0x0FFFFFFF
-#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
-#define EXTMEM_DATE_V  0xFFFFFFF
-#define EXTMEM_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_EXTMEM_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/extmem_struct.h b/components/soc/esp32s3/include/soc/extmem_struct.h
deleted file mode 100644
index 58ca6462942..00000000000
--- a/components/soc/esp32s3/include/soc/extmem_struct.h
+++ /dev/null
@@ -1,798 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_EXTMEM_STRUCT_H_
-#define _SOC_EXTMEM_STRUCT_H_
-
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct extmem_dev_s {
-    union {
-        struct {
-            uint32_t dcache_enable                 :    1;  /*The bit is used to activate the data cache. 0: disable, 1: enable*/
-            uint32_t reserved1                     :    1;  /*Reserved*/
-            uint32_t dcache_size_mode              :    1;  /*The bit is used to configure cache memory size.0: 32KB, 1: 64KB*/
-            uint32_t dcache_blocksize_mode         :    2;  /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } dcache_ctrl;
-    union {
-        struct {
-            uint32_t dcache_shut_core0_bus         :    1;  /*The bit is used to disable core0 dbus, 0: enable, 1: disable*/
-            uint32_t dcache_shut_core1_bus         :    1;  /*The bit is used to disable core1 dbus, 0: enable, 1: disable*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } dcache_ctrl1;
-    union {
-        struct {
-            uint32_t dcache_tag_mem_force_on       :    1;  /*The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.*/
-            uint32_t dcache_tag_mem_force_pd       :    1;  /*The bit is used to power dcache tag memory down, 0: follow  rtc_lslp_pd, 1: power down*/
-            uint32_t dcache_tag_mem_force_pu       :    1;  /*The bit is used to power dcache tag memory up, 0: follow  rtc_lslp_pd, 1: power up*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } dcache_tag_power_ctrl;
-    union {
-        struct {
-            uint32_t dcache_prelock_sct0_en        :    1;  /*The bit is used to enable the first section of prelock function.*/
-            uint32_t dcache_prelock_sct1_en        :    1;  /*The bit is used to enable the second section of prelock function.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } dcache_prelock_ctrl;
-    uint32_t dcache_prelock_sct0_addr;
-    uint32_t dcache_prelock_sct1_addr;
-    union {
-        struct {
-            uint32_t dcache_prelock_sct1_size      :    16;  /*The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/
-            uint32_t dcache_prelock_sct0_size      :    16;  /*The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/
-        };
-        uint32_t val;
-    } dcache_prelock_sct_size;
-    union {
-        struct {
-            uint32_t dcache_lock_ena               :    1;  /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
-            uint32_t dcache_unlock_ena             :    1;  /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
-            uint32_t dcache_lock_done              :    1;  /*The bit is used to indicate unlock/lock operation is finished.*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } dcache_lock_ctrl;
-    uint32_t dcache_lock_addr;
-    union {
-        struct {
-            uint32_t dcache_lock_size              :    16;  /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } dcache_lock_size;
-    union {
-        struct {
-            uint32_t dcache_invalidate_ena         :    1;  /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
-            uint32_t dcache_writeback_ena          :    1;  /*The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.*/
-            uint32_t dcache_clean_ena              :    1;  /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/
-            uint32_t dcache_sync_done              :    1;  /*The bit is used to indicate clean/writeback/invalidate operation is finished.*/
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } dcache_sync_ctrl;
-    uint32_t dcache_sync_addr;
-    union {
-        struct {
-            uint32_t dcache_sync_size              :    23;  /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } dcache_sync_size;
-    union {
-        struct {
-            uint32_t dcache_occupy_ena             :    1;  /*The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.*/
-            uint32_t dcache_occupy_done            :    1;  /*The bit is used to indicate occupy operation is finished.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } dcache_occupy_ctrl;
-    uint32_t dcache_occupy_addr;
-    union {
-        struct {
-            uint32_t dcache_occupy_size            :    16;  /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } dcache_occupy_size;
-    union {
-        struct {
-            uint32_t dcache_preload_ena            :    1;  /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
-            uint32_t dcache_preload_done           :    1;  /*The bit is used to indicate preload operation is finished.*/
-            uint32_t dcache_preload_order          :    1;  /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } dcache_preload_ctrl;
-    uint32_t dcache_preload_addr;
-    union {
-        struct {
-            uint32_t dcache_preload_size           :    16;  /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } dcache_preload_size;
-    union {
-        struct {
-            uint32_t dcache_autoload_sct0_ena      :    1;  /*The bits are used to enable the first section for autoload operation.*/
-            uint32_t dcache_autoload_sct1_ena      :    1;  /*The bits are used to enable the second section for autoload operation.*/
-            uint32_t dcache_autoload_ena           :    1;  /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. */
-            uint32_t dcache_autoload_done          :    1;  /*The bit is used to indicate autoload operation is finished.*/
-            uint32_t dcache_autoload_order         :    1;  /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/
-            uint32_t dcache_autoload_rqst          :    2;  /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
-            uint32_t dcache_autoload_size          :    2;  /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
-            uint32_t dcache_autoload_buffer_clear  :    1;  /*The bit is used to clear autoload buffer in dcache.*/
-            uint32_t reserved10                    :    22;
-        };
-        uint32_t val;
-    } dcache_autoload_ctrl;
-    uint32_t dcache_autoload_sct0_addr;
-    union {
-        struct {
-            uint32_t dcache_autoload_sct0_size     :    27;  /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
-            uint32_t reserved27                    :    5;
-        };
-        uint32_t val;
-    } dcache_autoload_sct0_size;
-    uint32_t dcache_autoload_sct1_addr;
-    union {
-        struct {
-            uint32_t dcache_autoload_sct1_size     :    27;  /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
-            uint32_t reserved27                    :    5;
-        };
-        uint32_t val;
-    } dcache_autoload_sct1_size;
-    union {
-        struct {
-            uint32_t icache_enable                 :    1;  /*The bit is used to activate the data cache. 0: disable, 1: enable*/
-            uint32_t icache_way_mode               :    1;  /*The bit is used to configure cache way mode.0: 4-way, 1: 8-way*/
-            uint32_t icache_size_mode              :    1;  /*The bit is used to configure cache memory size.0: 16KB, 1: 32KB*/
-            uint32_t icache_blocksize_mode         :    1;  /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes*/
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } icache_ctrl;
-    union {
-        struct {
-            uint32_t icache_shut_core0_bus         :    1;  /*The bit is used to disable core0 ibus, 0: enable, 1: disable*/
-            uint32_t icache_shut_core1_bus         :    1;  /*The bit is used to disable core1 ibus, 0: enable, 1: disable*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } icache_ctrl1;
-    union {
-        struct {
-            uint32_t icache_tag_mem_force_on       :    1;  /*The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.*/
-            uint32_t icache_tag_mem_force_pd       :    1;  /*The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down*/
-            uint32_t icache_tag_mem_force_pu       :    1;  /*The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } icache_tag_power_ctrl;
-    union {
-        struct {
-            uint32_t icache_prelock_sct0_en        :    1;  /*The bit is used to enable the first section of prelock function.*/
-            uint32_t icache_prelock_sct1_en        :    1;  /*The bit is used to enable the second section of prelock function.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } icache_prelock_ctrl;
-    uint32_t icache_prelock_sct0_addr;
-    uint32_t icache_prelock_sct1_addr;
-    union {
-        struct {
-            uint32_t icache_prelock_sct1_size      :    16;  /*The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
-            uint32_t icache_prelock_sct0_size      :    16;  /*The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
-        };
-        uint32_t val;
-    } icache_prelock_sct_size;
-    union {
-        struct {
-            uint32_t icache_lock_ena               :    1;  /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
-            uint32_t icache_unlock_ena             :    1;  /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
-            uint32_t icache_lock_done              :    1;  /*The bit is used to indicate unlock/lock operation is finished.*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } icache_lock_ctrl;
-    uint32_t icache_lock_addr;
-    union {
-        struct {
-            uint32_t icache_lock_size              :    16;  /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } icache_lock_size;
-    union {
-        struct {
-            uint32_t icache_invalidate_ena         :    1;  /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
-            uint32_t icache_sync_done              :    1;  /*The bit is used to indicate invalidate operation is finished.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } icache_sync_ctrl;
-    uint32_t icache_sync_addr;
-    union {
-        struct {
-            uint32_t icache_sync_size              :    23;  /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } icache_sync_size;
-    union {
-        struct {
-            uint32_t icache_preload_ena            :    1;  /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
-            uint32_t icache_preload_done           :    1;  /*The bit is used to indicate preload operation is finished.*/
-            uint32_t icache_preload_order          :    1;  /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } icache_preload_ctrl;
-    uint32_t icache_preload_addr;
-    union {
-        struct {
-            uint32_t icache_preload_size           :    16;  /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } icache_preload_size;
-    union {
-        struct {
-            uint32_t icache_autoload_sct0_ena      :    1;  /*The bits are used to enable the first section for autoload operation.*/
-            uint32_t icache_autoload_sct1_ena      :    1;  /*The bits are used to enable the second section for autoload operation.*/
-            uint32_t icache_autoload_ena           :    1;  /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. */
-            uint32_t icache_autoload_done          :    1;  /*The bit is used to indicate autoload operation is finished.*/
-            uint32_t icache_autoload_order         :    1;  /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/
-            uint32_t icache_autoload_rqst          :    2;  /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
-            uint32_t icache_autoload_size          :    2;  /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
-            uint32_t icache_autoload_buffer_clear  :    1;  /*The bit is used to clear autoload buffer in icache.*/
-            uint32_t reserved10                    :    22;
-        };
-        uint32_t val;
-    } icache_autoload_ctrl;
-    uint32_t icache_autoload_sct0_addr;
-    union {
-        struct {
-            uint32_t icache_autoload_sct0_size     :    27;  /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
-            uint32_t reserved27                    :    5;
-        };
-        uint32_t val;
-    } icache_autoload_sct0_size;
-    uint32_t icache_autoload_sct1_addr;
-    union {
-        struct {
-            uint32_t icache_autoload_sct1_size     :    27;  /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
-            uint32_t reserved27                    :    5;
-        };
-        uint32_t val;
-    } icache_autoload_sct1_size;
-    uint32_t ibus_to_flash_start_vaddr;
-    uint32_t ibus_to_flash_end_vaddr;
-    uint32_t dbus_to_flash_start_vaddr;
-    uint32_t dbus_to_flash_end_vaddr;
-    union {
-        struct {
-            uint32_t dcache_acs_cnt_clr            :    1;  /*The bit is used to clear dcache counter.*/
-            uint32_t icache_acs_cnt_clr            :    1;  /*The bit is used to clear icache counter.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } cache_acs_cnt_clr;
-    uint32_t ibus_acs_miss_cnt;
-    uint32_t ibus_acs_cnt;
-    uint32_t dbus_acs_flash_miss_cnt;
-    uint32_t dbus_acs_spiram_miss_cnt;
-    uint32_t dbus_acs_cnt;
-    union {
-        struct {
-            uint32_t icache_sync_op_fault          :    1;  /*The bit is used to enable interrupt by sync configurations fault.*/
-            uint32_t icache_preload_op_fault       :    1;  /*The bit is used to enable interrupt by preload configurations fault.*/
-            uint32_t dcache_sync_op_fault          :    1;  /*The bit is used to enable interrupt by sync configurations fault.*/
-            uint32_t dcache_preload_op_fault       :    1;  /*The bit is used to enable interrupt by preload configurations fault.*/
-            uint32_t dcache_write_flash            :    1;  /*The bit is used to enable interrupt by dcache trying to write flash.*/
-            uint32_t mmu_entry_fault               :    1;  /*The bit is used to enable interrupt by mmu entry fault.*/
-            uint32_t dcache_occupy_exc             :    1;  /*The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
-            uint32_t ibus_cnt_ovf                  :    1;  /*The bit is used to enable interrupt by ibus counter overflow.*/
-            uint32_t dbus_cnt_ovf                  :    1;  /*The bit is used to enable interrupt by dbus counter overflow.*/
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } cache_ilg_int_ena;
-    union {
-        struct {
-            uint32_t icache_sync_op_fault          :    1;  /*The bit is used to clear interrupt by sync configurations fault.*/
-            uint32_t icache_preload_op_fault       :    1;  /*The bit is used to clear interrupt by preload configurations fault.*/
-            uint32_t dcache_sync_op_fault          :    1;  /*The bit is used to clear interrupt by sync configurations fault.*/
-            uint32_t dcache_preload_op_fault       :    1;  /*The bit is used to clear interrupt by preload configurations fault.*/
-            uint32_t dcache_write_flash            :    1;  /*The bit is used to clear interrupt by dcache trying to write flash.*/
-            uint32_t mmu_entry_fault               :    1;  /*The bit is used to clear interrupt by mmu entry fault.*/
-            uint32_t dcache_occupy_exc             :    1;  /*The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
-            uint32_t ibus_cnt_ovf                  :    1;  /*The bit is used to clear interrupt by ibus counter overflow.*/
-            uint32_t dbus_cnt_ovf                  :    1;  /*The bit is used to clear interrupt by dbus counter overflow.*/
-            uint32_t reserved9                     :    23;
-        };
-        uint32_t val;
-    } cache_ilg_int_clr;
-    union {
-        struct {
-            uint32_t icache_sync_op_fault_st       :    1;  /*The bit is used to indicate interrupt by sync configurations fault.*/
-            uint32_t icache_preload_op_fault_st    :    1;  /*The bit is used to indicate interrupt by preload configurations fault.*/
-            uint32_t dcache_sync_op_fault_st       :    1;  /*The bit is used to indicate interrupt by sync configurations fault.*/
-            uint32_t dcache_preload_op_fault_st    :    1;  /*The bit is used to indicate interrupt by preload configurations fault.*/
-            uint32_t dcache_write_flash_st         :    1;  /*The bit is used to indicate interrupt by dcache trying to write flash.*/
-            uint32_t mmu_entry_fault_st            :    1;  /*The bit is used to indicate interrupt by mmu entry fault.*/
-            uint32_t dcache_occupy_exc_st          :    1;  /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
-            uint32_t ibus_acs_cnt_ovf_st           :    1;  /*The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.*/
-            uint32_t ibus_acs_miss_cnt_ovf_st      :    1;  /*The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.*/
-            uint32_t dbus_acs_cnt_ovf_st           :    1;  /*The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.*/
-            uint32_t dbus_acs_flash_miss_cnt_ovf_st:    1;  /*The bit is used to indicate interrupt by dbus access flash miss counter overflow.*/
-            uint32_t dbus_acs_spiram_miss_cnt_ovf_st:    1;  /*The bit is used to indicate interrupt by dbus access spiram miss counter overflow.*/
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } cache_ilg_int_st;
-    union {
-        struct {
-            uint32_t core0_ibus_acs_msk_ic         :    1;  /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
-            uint32_t core0_ibus_wr_ic              :    1;  /*The bit is used to enable interrupt by ibus trying to write icache*/
-            uint32_t core0_ibus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
-            uint32_t core0_dbus_acs_msk_dc         :    1;  /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
-            uint32_t core0_dbus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core0_acs_cache_int_ena;
-    union {
-        struct {
-            uint32_t core0_ibus_acs_msk_ic         :    1;  /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
-            uint32_t core0_ibus_wr_ic              :    1;  /*The bit is used to clear interrupt by ibus trying to write icache*/
-            uint32_t core0_ibus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
-            uint32_t core0_dbus_acs_msk_dc         :    1;  /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
-            uint32_t core0_dbus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core0_acs_cache_int_clr;
-    union {
-        struct {
-            uint32_t core0_ibus_acs_msk_icache_st  :    1;  /*The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.*/
-            uint32_t core0_ibus_wr_icache_st       :    1;  /*The bit is used to indicate interrupt by ibus trying to write icache*/
-            uint32_t core0_ibus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
-            uint32_t core0_dbus_acs_msk_dcache_st  :    1;  /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/
-            uint32_t core0_dbus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core0_acs_cache_int_st;
-    union {
-        struct {
-            uint32_t core1_ibus_acs_msk_ic         :    1;  /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
-            uint32_t core1_ibus_wr_ic              :    1;  /*The bit is used to enable interrupt by ibus trying to write icache*/
-            uint32_t core1_ibus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
-            uint32_t core1_dbus_acs_msk_dc         :    1;  /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
-            uint32_t core1_dbus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core1_acs_cache_int_ena;
-    union {
-        struct {
-            uint32_t core1_ibus_acs_msk_ic         :    1;  /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
-            uint32_t core1_ibus_wr_ic              :    1;  /*The bit is used to clear interrupt by ibus trying to write icache*/
-            uint32_t core1_ibus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
-            uint32_t core1_dbus_acs_msk_dc         :    1;  /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
-            uint32_t core1_dbus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core1_acs_cache_int_clr;
-    union {
-        struct {
-            uint32_t core1_ibus_acs_msk_icache_st  :    1;  /*The bit is used to indicate interrupt by cpu access  icache while the core1_ibus is disabled or  icache is disabled which include speculative access.*/
-            uint32_t core1_ibus_wr_icache_st       :    1;  /*The bit is used to indicate interrupt by ibus trying to write icache*/
-            uint32_t core1_ibus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
-            uint32_t core1_dbus_acs_msk_dcache_st  :    1;  /*The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.*/
-            uint32_t core1_dbus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core1_acs_cache_int_st;
-    union {
-        struct {
-            uint32_t core0_dbus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
-            uint32_t core0_dbus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
-            uint32_t core0_dbus_world              :    1;  /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } core0_dbus_reject_st;
-    uint32_t core0_dbus_reject_vaddr;
-    union {
-        struct {
-            uint32_t core0_ibus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
-            uint32_t core0_ibus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
-            uint32_t core0_ibus_world              :    1;  /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } core0_ibus_reject_st;
-    uint32_t core0_ibus_reject_vaddr;
-    union {
-        struct {
-            uint32_t core1_dbus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
-            uint32_t core1_dbus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
-            uint32_t core1_dbus_world              :    1;  /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } core1_dbus_reject_st;
-    uint32_t core1_dbus_reject_vaddr;
-    union {
-        struct {
-            uint32_t core1_ibus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
-            uint32_t core1_ibus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
-            uint32_t core1_ibus_world              :    1;  /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } core1_ibus_reject_st;
-    uint32_t core1_ibus_reject_vaddr;
-    union {
-        struct {
-            uint32_t cache_mmu_fault_content       :    16;  /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/
-            uint32_t cache_mmu_fault_code          :    4;  /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. */
-            uint32_t reserved20                    :    12;
-        };
-        uint32_t val;
-    } cache_mmu_fault_content;
-    uint32_t cache_mmu_fault_vaddr;
-    union {
-        struct {
-            uint32_t cache_flash_wrap_around       :    1;  /*The bit is used to enable wrap around mode when read data from flash.*/
-            uint32_t cache_sram_rd_wrap_around     :    1;  /*The bit is used to enable wrap around mode when read data from spiram.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } cache_wrap_around_ctrl;
-    union {
-        struct {
-            uint32_t cache_mmu_mem_force_on        :    1;  /*The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable*/
-            uint32_t cache_mmu_mem_force_pd        :    1;  /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down*/
-            uint32_t cache_mmu_mem_force_pu        :    1;  /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } cache_mmu_power_ctrl;
-    union {
-        struct {
-            uint32_t icache_state                  :    12;  /*The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state*/
-            uint32_t dcache_state                  :    12;  /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state,  0: not in idle state*/
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } cache_state;
-    union {
-        struct {
-            uint32_t record_disable_db_encrypt     :    1;  /*Reserved.*/
-            uint32_t record_disable_g0cb_decrypt   :    1;  /*Reserved.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } cache_encrypt_decrypt_record_disable;
-    union {
-        struct {
-            uint32_t clk_force_on_manual_crypt     :    1;  /*The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.*/
-            uint32_t clk_force_on_auto_crypt       :    1;  /*The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.*/
-            uint32_t clk_force_on_crypt            :    1;  /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } cache_encrypt_decrypt_clk_force_on;
-    union {
-        struct {
-            uint32_t alloc_wb_hold_arbiter         :    1;  /*Reserved.*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cache_bridge_arbiter_ctrl;
-    union {
-        struct {
-            uint32_t icache_preload_ist            :    1;  /*The bit is used to indicate the interrupt by  icache pre-load done.*/
-            uint32_t icache_preload_iena           :    1;  /*The bit is used to enable the interrupt by  icache pre-load done.*/
-            uint32_t icache_preload_iclr           :    1;  /*The bit is used to clear the interrupt by  icache pre-load done.*/
-            uint32_t dcache_preload_ist            :    1;  /*The bit is used to indicate the interrupt by dcache pre-load done.*/
-            uint32_t dcache_preload_iena           :    1;  /*The bit is used to enable the interrupt by dcache pre-load done.*/
-            uint32_t dcache_preload_iclr           :    1;  /*The bit is used to clear the interrupt by dcache pre-load done.*/
-            uint32_t reserved6                     :    26;
-        };
-        uint32_t val;
-    } cache_preload_int_ctrl;
-    union {
-        struct {
-            uint32_t icache_sync_ist               :    1;  /*The bit is used to indicate the interrupt by  icache sync done.*/
-            uint32_t icache_sync_iena              :    1;  /*The bit is used to enable the interrupt by  icache sync done.*/
-            uint32_t icache_sync_iclr              :    1;  /*The bit is used to clear the interrupt by  icache sync done.*/
-            uint32_t dcache_sync_ist               :    1;  /*The bit is used to indicate the interrupt by dcache sync done.*/
-            uint32_t dcache_sync_iena              :    1;  /*The bit is used to enable the interrupt by dcache sync done.*/
-            uint32_t dcache_sync_iclr              :    1;  /*The bit is used to clear the interrupt by dcache sync done.*/
-            uint32_t reserved6                     :    26;
-        };
-        uint32_t val;
-    } cache_sync_int_ctrl;
-    union {
-        struct {
-            uint32_t cache_mmu_owner               :    24;  /*The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.*/
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } cache_mmu_owner;
-    union {
-        struct {
-            uint32_t cache_ignore_preload_mmu_entry_fault:    1;  /*The bit is used to disable checking mmu entry fault by preload operation.*/
-            uint32_t cache_ignore_sync_mmu_entry_fault:    1;  /*The bit is used to disable checking mmu entry fault by sync operation.*/
-            uint32_t cache_trace_ena               :    1;  /*The bit is used to enable cache trace function.*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } cache_conf_misc;
-    union {
-        struct {
-            uint32_t dcache_freeze_ena             :    1;  /*The bit is used to enable dcache freeze mode*/
-            uint32_t dcache_freeze_mode            :    1;  /*The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss*/
-            uint32_t dcache_freeze_done            :    1;  /*The bit is used to indicate dcache freeze success*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } dcache_freeze;
-    union {
-        struct {
-            uint32_t icache_freeze_ena             :    1;  /*The bit is used to enable icache freeze mode*/
-            uint32_t icache_freeze_mode            :    1;  /*The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss*/
-            uint32_t icache_freeze_done            :    1;  /*The bit is used to indicate icache freeze success*/
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } icache_freeze;
-    union {
-        struct {
-            uint32_t icache_atomic_operate_ena     :    1;  /*The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } icache_atomic_operate_ena;
-    union {
-        struct {
-            uint32_t dcache_atomic_operate_ena     :    1;  /*The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dcache_atomic_operate_ena;
-    union {
-        struct {
-            uint32_t cache_request_bypass          :    1;  /*The bit is used to disable request recording which could cause performance issue*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cache_request;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;  /*Reserved.*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } clock_gate;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    union {
-        struct {
-            uint32_t icache_tag_object             :    1;  /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/
-            uint32_t dcache_tag_object             :    1;  /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/
-            uint32_t reserved2                     :    30;  /*Reserved*/
-        };
-        uint32_t val;
-    } cache_tag_object_ctrl;
-    union {
-        struct {
-            uint32_t cache_tag_way_object          :    3;  /*Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7.*/
-            uint32_t reserved3                     :    29;  /*Reserved*/
-        };
-        uint32_t val;
-    } cache_tag_way_object;
-    uint32_t cache_vaddr;
-    uint32_t cache_tag_content;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t extmem_reg_date               :    28;  /*version information.*/
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } date;
-} extmem_dev_t;
-extern extmem_dev_t EXTMEM;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_EXTMEM_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/gpio_reg.h b/components/soc/esp32s3/include/soc/gpio_reg.h
deleted file mode 100644
index 39656ffce35..00000000000
--- a/components/soc/esp32s3/include/soc/gpio_reg.h
+++ /dev/null
@@ -1,9224 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_GPIO_REG_H_
-#define _SOC_GPIO_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "soc.h"
-
-#define GPIO_PIN_CONFIG_MSB                    12
-#define GPIO_PIN_CONFIG_LSB                     11
-#define GPIO_PIN_CONFIG_MASK                   0x00001800
-#define GPIO_PIN_CONFIG_GET(x)                 (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
-#define GPIO_PIN_CONFIG_SET(x)                  (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
-
-#define GPIO_WAKEUP_ENABLE                     1
-#define GPIO_WAKEUP_DISABLE                    (~GPIO_WAKEUP_ENABLE)
-#define GPIO_PIN_WAKEUP_ENABLE_MSB             10
-#define GPIO_PIN_WAKEUP_ENABLE_LSB              10
-#define GPIO_PIN_WAKEUP_ENABLE_MASK            0x00000400
-#define GPIO_PIN_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
-
-#define GPIO_PIN_INT_TYPE_MASK                 0x380
-#define GPIO_PIN_INT_TYPE_MSB                  9
-#define GPIO_PIN_INT_TYPE_LSB                  7
-#define GPIO_PIN_INT_TYPE_GET(x)               (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
-#define GPIO_PIN_INT_TYPE_SET(x)               (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
-
-#define GPIO_PAD_DRIVER_ENABLE                 1
-#define GPIO_PAD_DRIVER_DISABLE                        (~GPIO_PAD_DRIVER_ENABLE)
-#define GPIO_PIN_PAD_DRIVER_MSB                        2
-#define GPIO_PIN_PAD_DRIVER_LSB                        2
-#define GPIO_PIN_PAD_DRIVER_MASK               0x00000004
-#define GPIO_PIN_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
-#define GPIO_PIN_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
-
-#define GPIO_BT_SELECT_REG          (DR_REG_GPIO_BASE + 0x0)
-/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_BT_SEL    0xFFFFFFFF
-#define GPIO_BT_SEL_M  ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
-#define GPIO_BT_SEL_V  0xFFFFFFFF
-#define GPIO_BT_SEL_S  0
-
-#define GPIO_OUT_REG          (DR_REG_GPIO_BASE + 0x4)
-/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_OUT_DATA    0xFFFFFFFF
-#define GPIO_OUT_DATA_M  ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
-#define GPIO_OUT_DATA_V  0xFFFFFFFF
-#define GPIO_OUT_DATA_S  0
-
-#define GPIO_OUT_W1TS_REG          (DR_REG_GPIO_BASE + 0x8)
-/* GPIO_OUT_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_OUT_W1TS    0xFFFFFFFF
-#define GPIO_OUT_W1TS_M  ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S))
-#define GPIO_OUT_W1TS_V  0xFFFFFFFF
-#define GPIO_OUT_W1TS_S  0
-
-#define GPIO_OUT_W1TC_REG          (DR_REG_GPIO_BASE + 0xC)
-/* GPIO_OUT_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_OUT_W1TC    0xFFFFFFFF
-#define GPIO_OUT_W1TC_M  ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S))
-#define GPIO_OUT_W1TC_V  0xFFFFFFFF
-#define GPIO_OUT_W1TC_S  0
-
-#define GPIO_OUT1_REG          (DR_REG_GPIO_BASE + 0x10)
-/* GPIO_OUT1_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_OUT1_DATA    0x003FFFFF
-#define GPIO_OUT1_DATA_M  ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S))
-#define GPIO_OUT1_DATA_V  0x3FFFFF
-#define GPIO_OUT1_DATA_S  0
-
-#define GPIO_OUT1_W1TS_REG          (DR_REG_GPIO_BASE + 0x14)
-/* GPIO_OUT1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_OUT1_W1TS    0x003FFFFF
-#define GPIO_OUT1_W1TS_M  ((GPIO_OUT1_W1TS_V)<<(GPIO_OUT1_W1TS_S))
-#define GPIO_OUT1_W1TS_V  0x3FFFFF
-#define GPIO_OUT1_W1TS_S  0
-
-#define GPIO_OUT1_W1TC_REG          (DR_REG_GPIO_BASE + 0x18)
-/* GPIO_OUT1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_OUT1_W1TC    0x003FFFFF
-#define GPIO_OUT1_W1TC_M  ((GPIO_OUT1_W1TC_V)<<(GPIO_OUT1_W1TC_S))
-#define GPIO_OUT1_W1TC_V  0x3FFFFF
-#define GPIO_OUT1_W1TC_S  0
-
-#define GPIO_SDIO_SELECT_REG          (DR_REG_GPIO_BASE + 0x1C)
-/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SDIO_SEL    0x000000FF
-#define GPIO_SDIO_SEL_M  ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
-#define GPIO_SDIO_SEL_V  0xFF
-#define GPIO_SDIO_SEL_S  0
-
-#define GPIO_ENABLE_REG          (DR_REG_GPIO_BASE + 0x20)
-/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_ENABLE_DATA    0xFFFFFFFF
-#define GPIO_ENABLE_DATA_M  ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
-#define GPIO_ENABLE_DATA_V  0xFFFFFFFF
-#define GPIO_ENABLE_DATA_S  0
-
-#define GPIO_ENABLE_W1TS_REG          (DR_REG_GPIO_BASE + 0x24)
-/* GPIO_ENABLE_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_ENABLE_W1TS    0xFFFFFFFF
-#define GPIO_ENABLE_W1TS_M  ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S))
-#define GPIO_ENABLE_W1TS_V  0xFFFFFFFF
-#define GPIO_ENABLE_W1TS_S  0
-
-#define GPIO_ENABLE_W1TC_REG          (DR_REG_GPIO_BASE + 0x28)
-/* GPIO_ENABLE_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_ENABLE_W1TC    0xFFFFFFFF
-#define GPIO_ENABLE_W1TC_M  ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S))
-#define GPIO_ENABLE_W1TC_V  0xFFFFFFFF
-#define GPIO_ENABLE_W1TC_S  0
-
-#define GPIO_ENABLE1_REG          (DR_REG_GPIO_BASE + 0x2C)
-/* GPIO_ENABLE_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_ENABLE1_DATA    0x003FFFFF
-#define GPIO_ENABLE1_DATA_M  ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S))
-#define GPIO_ENABLE1_DATA_V  0x3FFFFF
-#define GPIO_ENABLE1_DATA_S  0
-
-#define GPIO_ENABLE1_W1TS_REG          (DR_REG_GPIO_BASE + 0x30)
-/* GPIO_ENABLE1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_ENABLE1_W1TS    0x003FFFFF
-#define GPIO_ENABLE1_W1TS_M  ((GPIO_ENABLE1_W1TS_V)<<(GPIO_ENABLE1_W1TS_S))
-#define GPIO_ENABLE1_W1TS_V  0x3FFFFF
-#define GPIO_ENABLE1_W1TS_S  0
-
-#define GPIO_ENABLE1_W1TC_REG          (DR_REG_GPIO_BASE + 0x34)
-/* GPIO_ENABLE1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_ENABLE1_W1TC    0x003FFFFF
-#define GPIO_ENABLE1_W1TC_M  ((GPIO_ENABLE1_W1TC_V)<<(GPIO_ENABLE1_W1TC_S))
-#define GPIO_ENABLE1_W1TC_V  0x3FFFFF
-#define GPIO_ENABLE1_W1TC_S  0
-
-#define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x38)
-/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
-/*description: .*/
-#define GPIO_STRAPPING    0x0000FFFF
-#define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
-#define GPIO_STRAPPING_V  0xFFFF
-#define GPIO_STRAPPING_S  0
-
-#define GPIO_IN_REG          (DR_REG_GPIO_BASE + 0x3C)
-/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default:  ; */
-/*description: .*/
-#define GPIO_IN_DATA    0xFFFFFFFF
-#define GPIO_IN_DATA_M  ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
-#define GPIO_IN_DATA_V  0xFFFFFFFF
-#define GPIO_IN_DATA_S  0
-
-#define GPIO_IN1_REG          (DR_REG_GPIO_BASE + 0x40)
-/* GPIO_IN_DATA : RO ;bitpos:[21:0] ;default:  ; */
-/*description: .*/
-#define GPIO_IN1_DATA    0x003FFFFF
-#define GPIO_IN1_DATA_M  ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S))
-#define GPIO_IN1_DATA_V  0x3FFFFF
-#define GPIO_IN1_DATA_S  0
-
-#define GPIO_STATUS_REG          (DR_REG_GPIO_BASE + 0x44)
-/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_STATUS_INT    0xFFFFFFFF
-#define GPIO_STATUS_INT_M  ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
-#define GPIO_STATUS_INT_V  0xFFFFFFFF
-#define GPIO_STATUS_INT_S  0
-
-#define GPIO_STATUS_W1TS_REG          (DR_REG_GPIO_BASE + 0x48)
-/* GPIO_STATUS_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_STATUS_W1TS    0xFFFFFFFF
-#define GPIO_STATUS_W1TS_M  ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S))
-#define GPIO_STATUS_W1TS_V  0xFFFFFFFF
-#define GPIO_STATUS_W1TS_S  0
-
-#define GPIO_STATUS_W1TC_REG          (DR_REG_GPIO_BASE + 0x4C)
-/* GPIO_STATUS_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_STATUS_W1TC    0xFFFFFFFF
-#define GPIO_STATUS_W1TC_M  ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S))
-#define GPIO_STATUS_W1TC_V  0xFFFFFFFF
-#define GPIO_STATUS_W1TC_S  0
-
-#define GPIO_STATUS1_REG          (DR_REG_GPIO_BASE + 0x50)
-/* GPIO_STATUS_INT : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_STATUS1_INT    0x003FFFFF
-#define GPIO_STATUS1_INT_M  ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S))
-#define GPIO_STATUS1_INT_V  0x3FFFFF
-#define GPIO_STATUS1_INT_S  0
-
-#define GPIO_STATUS1_W1TS_REG          (DR_REG_GPIO_BASE + 0x54)
-/* GPIO_STATUS1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_STATUS1_W1TS    0x003FFFFF
-#define GPIO_STATUS1_W1TS_M  ((GPIO_STATUS1_W1TS_V)<<(GPIO_STATUS1_W1TS_S))
-#define GPIO_STATUS1_W1TS_V  0x3FFFFF
-#define GPIO_STATUS1_W1TS_S  0
-
-#define GPIO_STATUS1_W1TC_REG          (DR_REG_GPIO_BASE + 0x58)
-/* GPIO_STATUS1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: .*/
-#define GPIO_STATUS1_W1TC    0x003FFFFF
-#define GPIO_STATUS1_W1TC_M  ((GPIO_STATUS1_W1TC_V)<<(GPIO_STATUS1_W1TC_S))
-#define GPIO_STATUS1_W1TC_V  0x3FFFFF
-#define GPIO_STATUS1_W1TC_S  0
-
-#define GPIO_PCPU_INT_REG          (DR_REG_GPIO_BASE + 0x5C)
-/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_PROCPU_INT    0xFFFFFFFF
-#define GPIO_PROCPU_INT_M  ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
-#define GPIO_PROCPU_INT_V  0xFFFFFFFF
-#define GPIO_PROCPU_INT_S  0
-
-#define GPIO_PCPU_NMI_INT_REG          (DR_REG_GPIO_BASE + 0x60)
-/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_PROCPU_NMI_INT    0xFFFFFFFF
-#define GPIO_PROCPU_NMI_INT_M  ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
-#define GPIO_PROCPU_NMI_INT_V  0xFFFFFFFF
-#define GPIO_PROCPU_NMI_INT_S  0
-
-#define GPIO_CPUSDIO_INT_REG          (DR_REG_GPIO_BASE + 0x64)
-/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_SDIO_INT    0xFFFFFFFF
-#define GPIO_SDIO_INT_M  ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
-#define GPIO_SDIO_INT_V  0xFFFFFFFF
-#define GPIO_SDIO_INT_S  0
-
-#define GPIO_PCPU_INT1_REG          (DR_REG_GPIO_BASE + 0x68)
-/* GPIO_PROCPU_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: */
-#define GPIO_PROCPU_INT_H  0x003FFFFF
-#define GPIO_PROCPU_INT_H_M  ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S))
-#define GPIO_PROCPU_INT_H_V  0x3FFFFF
-#define GPIO_PROCPU_INT_H_S  0
-
-#define GPIO_PCPU_NMI_INT1_REG          (DR_REG_GPIO_BASE + 0x6C)
-/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: */
-#define GPIO_PROCPU_NMI_INT_H  0x003FFFFF
-#define GPIO_PROCPU_NMI_INT_H_M  ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S))
-#define GPIO_PROCPU_NMI_INT_H_V  0x3FFFFF
-#define GPIO_PROCPU_NMI_INT_H_S  0
-
-#define GPIO_CPUSDIO_INT1_REG          (DR_REG_GPIO_BASE + 0x70)
-/* GPIO_SDIO_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: */
-#define GPIO_SDIO_INT_H  0x003FFFFF
-#define GPIO_SDIO_INT_H_M  ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S))
-#define GPIO_SDIO_INT_H_V  0x3FFFFF
-#define GPIO_SDIO_INT_H_S  0
-
-#define GPIO_PIN0_REG          (DR_REG_GPIO_BASE + 0x74)
-/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN0_INT_ENA    0x0000001F
-#define GPIO_PIN0_INT_ENA_M  ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
-#define GPIO_PIN0_INT_ENA_V  0x1F
-#define GPIO_PIN0_INT_ENA_S  13
-/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN0_CONFIG    0x00000003
-#define GPIO_PIN0_CONFIG_M  ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
-#define GPIO_PIN0_CONFIG_V  0x3
-#define GPIO_PIN0_CONFIG_S  11
-/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN0_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN0_WAKEUP_ENABLE_S  10
-/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN0_INT_TYPE    0x00000007
-#define GPIO_PIN0_INT_TYPE_M  ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
-#define GPIO_PIN0_INT_TYPE_V  0x7
-#define GPIO_PIN0_INT_TYPE_S  7
-/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN0_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN0_SYNC1_BYPASS_M  ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
-#define GPIO_PIN0_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN0_SYNC1_BYPASS_S  3
-/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN0_PAD_DRIVER_V  0x1
-#define GPIO_PIN0_PAD_DRIVER_S  2
-/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN0_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN0_SYNC2_BYPASS_M  ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S))
-#define GPIO_PIN0_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN0_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN1_REG          (DR_REG_GPIO_BASE + 0x78)
-/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN1_INT_ENA    0x0000001F
-#define GPIO_PIN1_INT_ENA_M  ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
-#define GPIO_PIN1_INT_ENA_V  0x1F
-#define GPIO_PIN1_INT_ENA_S  13
-/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN1_CONFIG    0x00000003
-#define GPIO_PIN1_CONFIG_M  ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
-#define GPIO_PIN1_CONFIG_V  0x3
-#define GPIO_PIN1_CONFIG_S  11
-/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN1_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN1_WAKEUP_ENABLE_S  10
-/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN1_INT_TYPE    0x00000007
-#define GPIO_PIN1_INT_TYPE_M  ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
-#define GPIO_PIN1_INT_TYPE_V  0x7
-#define GPIO_PIN1_INT_TYPE_S  7
-/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN1_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN1_SYNC1_BYPASS_M  ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S))
-#define GPIO_PIN1_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN1_SYNC1_BYPASS_S  3
-/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN1_PAD_DRIVER_V  0x1
-#define GPIO_PIN1_PAD_DRIVER_S  2
-/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN1_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN1_SYNC2_BYPASS_M  ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S))
-#define GPIO_PIN1_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN1_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN2_REG          (DR_REG_GPIO_BASE + 0x7C)
-/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN2_INT_ENA    0x0000001F
-#define GPIO_PIN2_INT_ENA_M  ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
-#define GPIO_PIN2_INT_ENA_V  0x1F
-#define GPIO_PIN2_INT_ENA_S  13
-/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN2_CONFIG    0x00000003
-#define GPIO_PIN2_CONFIG_M  ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
-#define GPIO_PIN2_CONFIG_V  0x3
-#define GPIO_PIN2_CONFIG_S  11
-/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN2_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN2_WAKEUP_ENABLE_S  10
-/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN2_INT_TYPE    0x00000007
-#define GPIO_PIN2_INT_TYPE_M  ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
-#define GPIO_PIN2_INT_TYPE_V  0x7
-#define GPIO_PIN2_INT_TYPE_S  7
-/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN2_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN2_SYNC1_BYPASS_M  ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S))
-#define GPIO_PIN2_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN2_SYNC1_BYPASS_S  3
-/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN2_PAD_DRIVER_V  0x1
-#define GPIO_PIN2_PAD_DRIVER_S  2
-/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN2_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN2_SYNC2_BYPASS_M  ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S))
-#define GPIO_PIN2_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN2_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN3_REG          (DR_REG_GPIO_BASE + 0x80)
-/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN3_INT_ENA    0x0000001F
-#define GPIO_PIN3_INT_ENA_M  ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
-#define GPIO_PIN3_INT_ENA_V  0x1F
-#define GPIO_PIN3_INT_ENA_S  13
-/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN3_CONFIG    0x00000003
-#define GPIO_PIN3_CONFIG_M  ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
-#define GPIO_PIN3_CONFIG_V  0x3
-#define GPIO_PIN3_CONFIG_S  11
-/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN3_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN3_WAKEUP_ENABLE_S  10
-/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN3_INT_TYPE    0x00000007
-#define GPIO_PIN3_INT_TYPE_M  ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
-#define GPIO_PIN3_INT_TYPE_V  0x7
-#define GPIO_PIN3_INT_TYPE_S  7
-/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN3_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN3_SYNC1_BYPASS_M  ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S))
-#define GPIO_PIN3_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN3_SYNC1_BYPASS_S  3
-/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN3_PAD_DRIVER_V  0x1
-#define GPIO_PIN3_PAD_DRIVER_S  2
-/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN3_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN3_SYNC2_BYPASS_M  ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S))
-#define GPIO_PIN3_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN3_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN4_REG          (DR_REG_GPIO_BASE + 0x84)
-/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN4_INT_ENA    0x0000001F
-#define GPIO_PIN4_INT_ENA_M  ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
-#define GPIO_PIN4_INT_ENA_V  0x1F
-#define GPIO_PIN4_INT_ENA_S  13
-/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN4_CONFIG    0x00000003
-#define GPIO_PIN4_CONFIG_M  ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
-#define GPIO_PIN4_CONFIG_V  0x3
-#define GPIO_PIN4_CONFIG_S  11
-/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN4_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN4_WAKEUP_ENABLE_S  10
-/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN4_INT_TYPE    0x00000007
-#define GPIO_PIN4_INT_TYPE_M  ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
-#define GPIO_PIN4_INT_TYPE_V  0x7
-#define GPIO_PIN4_INT_TYPE_S  7
-/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN4_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN4_SYNC1_BYPASS_M  ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S))
-#define GPIO_PIN4_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN4_SYNC1_BYPASS_S  3
-/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN4_PAD_DRIVER_V  0x1
-#define GPIO_PIN4_PAD_DRIVER_S  2
-/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN4_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN4_SYNC2_BYPASS_M  ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S))
-#define GPIO_PIN4_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN4_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN5_REG          (DR_REG_GPIO_BASE + 0x88)
-/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN5_INT_ENA    0x0000001F
-#define GPIO_PIN5_INT_ENA_M  ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
-#define GPIO_PIN5_INT_ENA_V  0x1F
-#define GPIO_PIN5_INT_ENA_S  13
-/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN5_CONFIG    0x00000003
-#define GPIO_PIN5_CONFIG_M  ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
-#define GPIO_PIN5_CONFIG_V  0x3
-#define GPIO_PIN5_CONFIG_S  11
-/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN5_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN5_WAKEUP_ENABLE_S  10
-/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN5_INT_TYPE    0x00000007
-#define GPIO_PIN5_INT_TYPE_M  ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
-#define GPIO_PIN5_INT_TYPE_V  0x7
-#define GPIO_PIN5_INT_TYPE_S  7
-/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN5_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN5_SYNC1_BYPASS_M  ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S))
-#define GPIO_PIN5_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN5_SYNC1_BYPASS_S  3
-/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN5_PAD_DRIVER_V  0x1
-#define GPIO_PIN5_PAD_DRIVER_S  2
-/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN5_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN5_SYNC2_BYPASS_M  ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S))
-#define GPIO_PIN5_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN5_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN6_REG          (DR_REG_GPIO_BASE + 0x8C)
-/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN6_INT_ENA    0x0000001F
-#define GPIO_PIN6_INT_ENA_M  ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
-#define GPIO_PIN6_INT_ENA_V  0x1F
-#define GPIO_PIN6_INT_ENA_S  13
-/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN6_CONFIG    0x00000003
-#define GPIO_PIN6_CONFIG_M  ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
-#define GPIO_PIN6_CONFIG_V  0x3
-#define GPIO_PIN6_CONFIG_S  11
-/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN6_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN6_WAKEUP_ENABLE_S  10
-/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN6_INT_TYPE    0x00000007
-#define GPIO_PIN6_INT_TYPE_M  ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
-#define GPIO_PIN6_INT_TYPE_V  0x7
-#define GPIO_PIN6_INT_TYPE_S  7
-/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN6_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN6_SYNC1_BYPASS_M  ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S))
-#define GPIO_PIN6_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN6_SYNC1_BYPASS_S  3
-/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN6_PAD_DRIVER_V  0x1
-#define GPIO_PIN6_PAD_DRIVER_S  2
-/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN6_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN6_SYNC2_BYPASS_M  ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S))
-#define GPIO_PIN6_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN6_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN7_REG          (DR_REG_GPIO_BASE + 0x90)
-/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN7_INT_ENA    0x0000001F
-#define GPIO_PIN7_INT_ENA_M  ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
-#define GPIO_PIN7_INT_ENA_V  0x1F
-#define GPIO_PIN7_INT_ENA_S  13
-/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN7_CONFIG    0x00000003
-#define GPIO_PIN7_CONFIG_M  ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
-#define GPIO_PIN7_CONFIG_V  0x3
-#define GPIO_PIN7_CONFIG_S  11
-/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN7_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN7_WAKEUP_ENABLE_S  10
-/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN7_INT_TYPE    0x00000007
-#define GPIO_PIN7_INT_TYPE_M  ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
-#define GPIO_PIN7_INT_TYPE_V  0x7
-#define GPIO_PIN7_INT_TYPE_S  7
-/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN7_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN7_SYNC1_BYPASS_M  ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S))
-#define GPIO_PIN7_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN7_SYNC1_BYPASS_S  3
-/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN7_PAD_DRIVER_V  0x1
-#define GPIO_PIN7_PAD_DRIVER_S  2
-/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN7_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN7_SYNC2_BYPASS_M  ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S))
-#define GPIO_PIN7_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN7_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN8_REG          (DR_REG_GPIO_BASE + 0x94)
-/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN8_INT_ENA    0x0000001F
-#define GPIO_PIN8_INT_ENA_M  ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
-#define GPIO_PIN8_INT_ENA_V  0x1F
-#define GPIO_PIN8_INT_ENA_S  13
-/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN8_CONFIG    0x00000003
-#define GPIO_PIN8_CONFIG_M  ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
-#define GPIO_PIN8_CONFIG_V  0x3
-#define GPIO_PIN8_CONFIG_S  11
-/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN8_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN8_WAKEUP_ENABLE_S  10
-/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN8_INT_TYPE    0x00000007
-#define GPIO_PIN8_INT_TYPE_M  ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
-#define GPIO_PIN8_INT_TYPE_V  0x7
-#define GPIO_PIN8_INT_TYPE_S  7
-/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN8_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN8_SYNC1_BYPASS_M  ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S))
-#define GPIO_PIN8_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN8_SYNC1_BYPASS_S  3
-/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN8_PAD_DRIVER_V  0x1
-#define GPIO_PIN8_PAD_DRIVER_S  2
-/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN8_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN8_SYNC2_BYPASS_M  ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S))
-#define GPIO_PIN8_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN8_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN9_REG          (DR_REG_GPIO_BASE + 0x98)
-/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN9_INT_ENA    0x0000001F
-#define GPIO_PIN9_INT_ENA_M  ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
-#define GPIO_PIN9_INT_ENA_V  0x1F
-#define GPIO_PIN9_INT_ENA_S  13
-/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN9_CONFIG    0x00000003
-#define GPIO_PIN9_CONFIG_M  ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
-#define GPIO_PIN9_CONFIG_V  0x3
-#define GPIO_PIN9_CONFIG_S  11
-/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN9_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN9_WAKEUP_ENABLE_S  10
-/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN9_INT_TYPE    0x00000007
-#define GPIO_PIN9_INT_TYPE_M  ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
-#define GPIO_PIN9_INT_TYPE_V  0x7
-#define GPIO_PIN9_INT_TYPE_S  7
-/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN9_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN9_SYNC1_BYPASS_M  ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S))
-#define GPIO_PIN9_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN9_SYNC1_BYPASS_S  3
-/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN9_PAD_DRIVER_V  0x1
-#define GPIO_PIN9_PAD_DRIVER_S  2
-/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN9_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN9_SYNC2_BYPASS_M  ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S))
-#define GPIO_PIN9_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN9_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN10_REG          (DR_REG_GPIO_BASE + 0x9C)
-/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN10_INT_ENA    0x0000001F
-#define GPIO_PIN10_INT_ENA_M  ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
-#define GPIO_PIN10_INT_ENA_V  0x1F
-#define GPIO_PIN10_INT_ENA_S  13
-/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN10_CONFIG    0x00000003
-#define GPIO_PIN10_CONFIG_M  ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
-#define GPIO_PIN10_CONFIG_V  0x3
-#define GPIO_PIN10_CONFIG_S  11
-/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN10_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN10_WAKEUP_ENABLE_S  10
-/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN10_INT_TYPE    0x00000007
-#define GPIO_PIN10_INT_TYPE_M  ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
-#define GPIO_PIN10_INT_TYPE_V  0x7
-#define GPIO_PIN10_INT_TYPE_S  7
-/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN10_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN10_SYNC1_BYPASS_M  ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S))
-#define GPIO_PIN10_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN10_SYNC1_BYPASS_S  3
-/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN10_PAD_DRIVER_V  0x1
-#define GPIO_PIN10_PAD_DRIVER_S  2
-/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN10_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN10_SYNC2_BYPASS_M  ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S))
-#define GPIO_PIN10_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN10_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN11_REG          (DR_REG_GPIO_BASE + 0xA0)
-/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN11_INT_ENA    0x0000001F
-#define GPIO_PIN11_INT_ENA_M  ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
-#define GPIO_PIN11_INT_ENA_V  0x1F
-#define GPIO_PIN11_INT_ENA_S  13
-/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN11_CONFIG    0x00000003
-#define GPIO_PIN11_CONFIG_M  ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
-#define GPIO_PIN11_CONFIG_V  0x3
-#define GPIO_PIN11_CONFIG_S  11
-/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN11_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN11_WAKEUP_ENABLE_S  10
-/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN11_INT_TYPE    0x00000007
-#define GPIO_PIN11_INT_TYPE_M  ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
-#define GPIO_PIN11_INT_TYPE_V  0x7
-#define GPIO_PIN11_INT_TYPE_S  7
-/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN11_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN11_SYNC1_BYPASS_M  ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S))
-#define GPIO_PIN11_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN11_SYNC1_BYPASS_S  3
-/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN11_PAD_DRIVER_V  0x1
-#define GPIO_PIN11_PAD_DRIVER_S  2
-/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN11_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN11_SYNC2_BYPASS_M  ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S))
-#define GPIO_PIN11_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN11_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN12_REG          (DR_REG_GPIO_BASE + 0xA4)
-/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN12_INT_ENA    0x0000001F
-#define GPIO_PIN12_INT_ENA_M  ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
-#define GPIO_PIN12_INT_ENA_V  0x1F
-#define GPIO_PIN12_INT_ENA_S  13
-/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN12_CONFIG    0x00000003
-#define GPIO_PIN12_CONFIG_M  ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
-#define GPIO_PIN12_CONFIG_V  0x3
-#define GPIO_PIN12_CONFIG_S  11
-/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN12_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN12_WAKEUP_ENABLE_S  10
-/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN12_INT_TYPE    0x00000007
-#define GPIO_PIN12_INT_TYPE_M  ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
-#define GPIO_PIN12_INT_TYPE_V  0x7
-#define GPIO_PIN12_INT_TYPE_S  7
-/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN12_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN12_SYNC1_BYPASS_M  ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S))
-#define GPIO_PIN12_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN12_SYNC1_BYPASS_S  3
-/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN12_PAD_DRIVER_V  0x1
-#define GPIO_PIN12_PAD_DRIVER_S  2
-/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN12_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN12_SYNC2_BYPASS_M  ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S))
-#define GPIO_PIN12_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN12_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN13_REG          (DR_REG_GPIO_BASE + 0xA8)
-/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN13_INT_ENA    0x0000001F
-#define GPIO_PIN13_INT_ENA_M  ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
-#define GPIO_PIN13_INT_ENA_V  0x1F
-#define GPIO_PIN13_INT_ENA_S  13
-/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN13_CONFIG    0x00000003
-#define GPIO_PIN13_CONFIG_M  ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
-#define GPIO_PIN13_CONFIG_V  0x3
-#define GPIO_PIN13_CONFIG_S  11
-/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN13_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN13_WAKEUP_ENABLE_S  10
-/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN13_INT_TYPE    0x00000007
-#define GPIO_PIN13_INT_TYPE_M  ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
-#define GPIO_PIN13_INT_TYPE_V  0x7
-#define GPIO_PIN13_INT_TYPE_S  7
-/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN13_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN13_SYNC1_BYPASS_M  ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S))
-#define GPIO_PIN13_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN13_SYNC1_BYPASS_S  3
-/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN13_PAD_DRIVER_V  0x1
-#define GPIO_PIN13_PAD_DRIVER_S  2
-/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN13_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN13_SYNC2_BYPASS_M  ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S))
-#define GPIO_PIN13_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN13_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN14_REG          (DR_REG_GPIO_BASE + 0xAC)
-/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN14_INT_ENA    0x0000001F
-#define GPIO_PIN14_INT_ENA_M  ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
-#define GPIO_PIN14_INT_ENA_V  0x1F
-#define GPIO_PIN14_INT_ENA_S  13
-/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN14_CONFIG    0x00000003
-#define GPIO_PIN14_CONFIG_M  ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
-#define GPIO_PIN14_CONFIG_V  0x3
-#define GPIO_PIN14_CONFIG_S  11
-/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN14_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN14_WAKEUP_ENABLE_S  10
-/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN14_INT_TYPE    0x00000007
-#define GPIO_PIN14_INT_TYPE_M  ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
-#define GPIO_PIN14_INT_TYPE_V  0x7
-#define GPIO_PIN14_INT_TYPE_S  7
-/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN14_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN14_SYNC1_BYPASS_M  ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S))
-#define GPIO_PIN14_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN14_SYNC1_BYPASS_S  3
-/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN14_PAD_DRIVER_V  0x1
-#define GPIO_PIN14_PAD_DRIVER_S  2
-/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN14_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN14_SYNC2_BYPASS_M  ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S))
-#define GPIO_PIN14_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN14_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN15_REG          (DR_REG_GPIO_BASE + 0xB0)
-/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN15_INT_ENA    0x0000001F
-#define GPIO_PIN15_INT_ENA_M  ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
-#define GPIO_PIN15_INT_ENA_V  0x1F
-#define GPIO_PIN15_INT_ENA_S  13
-/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN15_CONFIG    0x00000003
-#define GPIO_PIN15_CONFIG_M  ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
-#define GPIO_PIN15_CONFIG_V  0x3
-#define GPIO_PIN15_CONFIG_S  11
-/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN15_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN15_WAKEUP_ENABLE_S  10
-/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN15_INT_TYPE    0x00000007
-#define GPIO_PIN15_INT_TYPE_M  ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
-#define GPIO_PIN15_INT_TYPE_V  0x7
-#define GPIO_PIN15_INT_TYPE_S  7
-/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN15_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN15_SYNC1_BYPASS_M  ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S))
-#define GPIO_PIN15_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN15_SYNC1_BYPASS_S  3
-/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN15_PAD_DRIVER_V  0x1
-#define GPIO_PIN15_PAD_DRIVER_S  2
-/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN15_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN15_SYNC2_BYPASS_M  ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S))
-#define GPIO_PIN15_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN15_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN16_REG          (DR_REG_GPIO_BASE + 0xB4)
-/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN16_INT_ENA    0x0000001F
-#define GPIO_PIN16_INT_ENA_M  ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
-#define GPIO_PIN16_INT_ENA_V  0x1F
-#define GPIO_PIN16_INT_ENA_S  13
-/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN16_CONFIG    0x00000003
-#define GPIO_PIN16_CONFIG_M  ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
-#define GPIO_PIN16_CONFIG_V  0x3
-#define GPIO_PIN16_CONFIG_S  11
-/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN16_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN16_WAKEUP_ENABLE_S  10
-/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN16_INT_TYPE    0x00000007
-#define GPIO_PIN16_INT_TYPE_M  ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
-#define GPIO_PIN16_INT_TYPE_V  0x7
-#define GPIO_PIN16_INT_TYPE_S  7
-/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN16_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN16_SYNC1_BYPASS_M  ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S))
-#define GPIO_PIN16_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN16_SYNC1_BYPASS_S  3
-/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN16_PAD_DRIVER_V  0x1
-#define GPIO_PIN16_PAD_DRIVER_S  2
-/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN16_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN16_SYNC2_BYPASS_M  ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S))
-#define GPIO_PIN16_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN16_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN17_REG          (DR_REG_GPIO_BASE + 0xB8)
-/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN17_INT_ENA    0x0000001F
-#define GPIO_PIN17_INT_ENA_M  ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
-#define GPIO_PIN17_INT_ENA_V  0x1F
-#define GPIO_PIN17_INT_ENA_S  13
-/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN17_CONFIG    0x00000003
-#define GPIO_PIN17_CONFIG_M  ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
-#define GPIO_PIN17_CONFIG_V  0x3
-#define GPIO_PIN17_CONFIG_S  11
-/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN17_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN17_WAKEUP_ENABLE_S  10
-/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN17_INT_TYPE    0x00000007
-#define GPIO_PIN17_INT_TYPE_M  ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
-#define GPIO_PIN17_INT_TYPE_V  0x7
-#define GPIO_PIN17_INT_TYPE_S  7
-/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN17_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN17_SYNC1_BYPASS_M  ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S))
-#define GPIO_PIN17_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN17_SYNC1_BYPASS_S  3
-/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN17_PAD_DRIVER_V  0x1
-#define GPIO_PIN17_PAD_DRIVER_S  2
-/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN17_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN17_SYNC2_BYPASS_M  ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S))
-#define GPIO_PIN17_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN17_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN18_REG          (DR_REG_GPIO_BASE + 0xBC)
-/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN18_INT_ENA    0x0000001F
-#define GPIO_PIN18_INT_ENA_M  ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
-#define GPIO_PIN18_INT_ENA_V  0x1F
-#define GPIO_PIN18_INT_ENA_S  13
-/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN18_CONFIG    0x00000003
-#define GPIO_PIN18_CONFIG_M  ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
-#define GPIO_PIN18_CONFIG_V  0x3
-#define GPIO_PIN18_CONFIG_S  11
-/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN18_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN18_WAKEUP_ENABLE_S  10
-/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN18_INT_TYPE    0x00000007
-#define GPIO_PIN18_INT_TYPE_M  ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
-#define GPIO_PIN18_INT_TYPE_V  0x7
-#define GPIO_PIN18_INT_TYPE_S  7
-/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN18_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN18_SYNC1_BYPASS_M  ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S))
-#define GPIO_PIN18_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN18_SYNC1_BYPASS_S  3
-/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN18_PAD_DRIVER_V  0x1
-#define GPIO_PIN18_PAD_DRIVER_S  2
-/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN18_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN18_SYNC2_BYPASS_M  ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S))
-#define GPIO_PIN18_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN18_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN19_REG          (DR_REG_GPIO_BASE + 0xC0)
-/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN19_INT_ENA    0x0000001F
-#define GPIO_PIN19_INT_ENA_M  ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
-#define GPIO_PIN19_INT_ENA_V  0x1F
-#define GPIO_PIN19_INT_ENA_S  13
-/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN19_CONFIG    0x00000003
-#define GPIO_PIN19_CONFIG_M  ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
-#define GPIO_PIN19_CONFIG_V  0x3
-#define GPIO_PIN19_CONFIG_S  11
-/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN19_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN19_WAKEUP_ENABLE_S  10
-/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN19_INT_TYPE    0x00000007
-#define GPIO_PIN19_INT_TYPE_M  ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
-#define GPIO_PIN19_INT_TYPE_V  0x7
-#define GPIO_PIN19_INT_TYPE_S  7
-/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN19_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN19_SYNC1_BYPASS_M  ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S))
-#define GPIO_PIN19_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN19_SYNC1_BYPASS_S  3
-/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN19_PAD_DRIVER_V  0x1
-#define GPIO_PIN19_PAD_DRIVER_S  2
-/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN19_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN19_SYNC2_BYPASS_M  ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S))
-#define GPIO_PIN19_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN19_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN20_REG          (DR_REG_GPIO_BASE + 0xC4)
-/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN20_INT_ENA    0x0000001F
-#define GPIO_PIN20_INT_ENA_M  ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
-#define GPIO_PIN20_INT_ENA_V  0x1F
-#define GPIO_PIN20_INT_ENA_S  13
-/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN20_CONFIG    0x00000003
-#define GPIO_PIN20_CONFIG_M  ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
-#define GPIO_PIN20_CONFIG_V  0x3
-#define GPIO_PIN20_CONFIG_S  11
-/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN20_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN20_WAKEUP_ENABLE_S  10
-/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN20_INT_TYPE    0x00000007
-#define GPIO_PIN20_INT_TYPE_M  ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
-#define GPIO_PIN20_INT_TYPE_V  0x7
-#define GPIO_PIN20_INT_TYPE_S  7
-/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN20_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN20_SYNC1_BYPASS_M  ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S))
-#define GPIO_PIN20_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN20_SYNC1_BYPASS_S  3
-/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN20_PAD_DRIVER_V  0x1
-#define GPIO_PIN20_PAD_DRIVER_S  2
-/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN20_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN20_SYNC2_BYPASS_M  ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S))
-#define GPIO_PIN20_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN20_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN21_REG          (DR_REG_GPIO_BASE + 0xC8)
-/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN21_INT_ENA    0x0000001F
-#define GPIO_PIN21_INT_ENA_M  ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
-#define GPIO_PIN21_INT_ENA_V  0x1F
-#define GPIO_PIN21_INT_ENA_S  13
-/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN21_CONFIG    0x00000003
-#define GPIO_PIN21_CONFIG_M  ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
-#define GPIO_PIN21_CONFIG_V  0x3
-#define GPIO_PIN21_CONFIG_S  11
-/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN21_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN21_WAKEUP_ENABLE_S  10
-/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN21_INT_TYPE    0x00000007
-#define GPIO_PIN21_INT_TYPE_M  ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
-#define GPIO_PIN21_INT_TYPE_V  0x7
-#define GPIO_PIN21_INT_TYPE_S  7
-/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN21_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN21_SYNC1_BYPASS_M  ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S))
-#define GPIO_PIN21_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN21_SYNC1_BYPASS_S  3
-/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN21_PAD_DRIVER_V  0x1
-#define GPIO_PIN21_PAD_DRIVER_S  2
-/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN21_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN21_SYNC2_BYPASS_M  ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S))
-#define GPIO_PIN21_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN21_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN22_REG          (DR_REG_GPIO_BASE + 0xCC)
-/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN22_INT_ENA    0x0000001F
-#define GPIO_PIN22_INT_ENA_M  ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
-#define GPIO_PIN22_INT_ENA_V  0x1F
-#define GPIO_PIN22_INT_ENA_S  13
-/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN22_CONFIG    0x00000003
-#define GPIO_PIN22_CONFIG_M  ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
-#define GPIO_PIN22_CONFIG_V  0x3
-#define GPIO_PIN22_CONFIG_S  11
-/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN22_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN22_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN22_WAKEUP_ENABLE_S  10
-/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN22_INT_TYPE    0x00000007
-#define GPIO_PIN22_INT_TYPE_M  ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
-#define GPIO_PIN22_INT_TYPE_V  0x7
-#define GPIO_PIN22_INT_TYPE_S  7
-/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN22_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN22_SYNC1_BYPASS_M  ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S))
-#define GPIO_PIN22_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN22_SYNC1_BYPASS_S  3
-/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN22_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN22_PAD_DRIVER_V  0x1
-#define GPIO_PIN22_PAD_DRIVER_S  2
-/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN22_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN22_SYNC2_BYPASS_M  ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S))
-#define GPIO_PIN22_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN22_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN23_REG          (DR_REG_GPIO_BASE + 0xD0)
-/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN23_INT_ENA    0x0000001F
-#define GPIO_PIN23_INT_ENA_M  ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
-#define GPIO_PIN23_INT_ENA_V  0x1F
-#define GPIO_PIN23_INT_ENA_S  13
-/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN23_CONFIG    0x00000003
-#define GPIO_PIN23_CONFIG_M  ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
-#define GPIO_PIN23_CONFIG_V  0x3
-#define GPIO_PIN23_CONFIG_S  11
-/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN23_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN23_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN23_WAKEUP_ENABLE_S  10
-/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN23_INT_TYPE    0x00000007
-#define GPIO_PIN23_INT_TYPE_M  ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
-#define GPIO_PIN23_INT_TYPE_V  0x7
-#define GPIO_PIN23_INT_TYPE_S  7
-/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN23_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN23_SYNC1_BYPASS_M  ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S))
-#define GPIO_PIN23_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN23_SYNC1_BYPASS_S  3
-/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN23_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN23_PAD_DRIVER_V  0x1
-#define GPIO_PIN23_PAD_DRIVER_S  2
-/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN23_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN23_SYNC2_BYPASS_M  ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S))
-#define GPIO_PIN23_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN23_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN24_REG          (DR_REG_GPIO_BASE + 0xD4)
-/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN24_INT_ENA    0x0000001F
-#define GPIO_PIN24_INT_ENA_M  ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
-#define GPIO_PIN24_INT_ENA_V  0x1F
-#define GPIO_PIN24_INT_ENA_S  13
-/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN24_CONFIG    0x00000003
-#define GPIO_PIN24_CONFIG_M  ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
-#define GPIO_PIN24_CONFIG_V  0x3
-#define GPIO_PIN24_CONFIG_S  11
-/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN24_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN24_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN24_WAKEUP_ENABLE_S  10
-/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN24_INT_TYPE    0x00000007
-#define GPIO_PIN24_INT_TYPE_M  ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
-#define GPIO_PIN24_INT_TYPE_V  0x7
-#define GPIO_PIN24_INT_TYPE_S  7
-/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN24_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN24_SYNC1_BYPASS_M  ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S))
-#define GPIO_PIN24_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN24_SYNC1_BYPASS_S  3
-/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN24_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN24_PAD_DRIVER_V  0x1
-#define GPIO_PIN24_PAD_DRIVER_S  2
-/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN24_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN24_SYNC2_BYPASS_M  ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S))
-#define GPIO_PIN24_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN24_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN25_REG          (DR_REG_GPIO_BASE + 0xD8)
-/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN25_INT_ENA    0x0000001F
-#define GPIO_PIN25_INT_ENA_M  ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
-#define GPIO_PIN25_INT_ENA_V  0x1F
-#define GPIO_PIN25_INT_ENA_S  13
-/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN25_CONFIG    0x00000003
-#define GPIO_PIN25_CONFIG_M  ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
-#define GPIO_PIN25_CONFIG_V  0x3
-#define GPIO_PIN25_CONFIG_S  11
-/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN25_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN25_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN25_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN25_WAKEUP_ENABLE_S  10
-/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN25_INT_TYPE    0x00000007
-#define GPIO_PIN25_INT_TYPE_M  ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
-#define GPIO_PIN25_INT_TYPE_V  0x7
-#define GPIO_PIN25_INT_TYPE_S  7
-/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN25_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN25_SYNC1_BYPASS_M  ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S))
-#define GPIO_PIN25_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN25_SYNC1_BYPASS_S  3
-/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN25_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN25_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN25_PAD_DRIVER_V  0x1
-#define GPIO_PIN25_PAD_DRIVER_S  2
-/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN25_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN25_SYNC2_BYPASS_M  ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S))
-#define GPIO_PIN25_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN25_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN26_REG          (DR_REG_GPIO_BASE + 0xDC)
-/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN26_INT_ENA    0x0000001F
-#define GPIO_PIN26_INT_ENA_M  ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S))
-#define GPIO_PIN26_INT_ENA_V  0x1F
-#define GPIO_PIN26_INT_ENA_S  13
-/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN26_CONFIG    0x00000003
-#define GPIO_PIN26_CONFIG_M  ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S))
-#define GPIO_PIN26_CONFIG_V  0x3
-#define GPIO_PIN26_CONFIG_S  11
-/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN26_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN26_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN26_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN26_WAKEUP_ENABLE_S  10
-/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN26_INT_TYPE    0x00000007
-#define GPIO_PIN26_INT_TYPE_M  ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S))
-#define GPIO_PIN26_INT_TYPE_V  0x7
-#define GPIO_PIN26_INT_TYPE_S  7
-/* GPIO_PIN26_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN26_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN26_SYNC1_BYPASS_M  ((GPIO_PIN26_SYNC1_BYPASS_V)<<(GPIO_PIN26_SYNC1_BYPASS_S))
-#define GPIO_PIN26_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN26_SYNC1_BYPASS_S  3
-/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN26_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN26_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN26_PAD_DRIVER_V  0x1
-#define GPIO_PIN26_PAD_DRIVER_S  2
-/* GPIO_PIN26_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN26_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN26_SYNC2_BYPASS_M  ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S))
-#define GPIO_PIN26_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN26_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN27_REG          (DR_REG_GPIO_BASE + 0xE0)
-/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN27_INT_ENA    0x0000001F
-#define GPIO_PIN27_INT_ENA_M  ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S))
-#define GPIO_PIN27_INT_ENA_V  0x1F
-#define GPIO_PIN27_INT_ENA_S  13
-/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN27_CONFIG    0x00000003
-#define GPIO_PIN27_CONFIG_M  ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S))
-#define GPIO_PIN27_CONFIG_V  0x3
-#define GPIO_PIN27_CONFIG_S  11
-/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN27_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN27_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN27_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN27_WAKEUP_ENABLE_S  10
-/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN27_INT_TYPE    0x00000007
-#define GPIO_PIN27_INT_TYPE_M  ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S))
-#define GPIO_PIN27_INT_TYPE_V  0x7
-#define GPIO_PIN27_INT_TYPE_S  7
-/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN27_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN27_SYNC1_BYPASS_M  ((GPIO_PIN27_SYNC1_BYPASS_V)<<(GPIO_PIN27_SYNC1_BYPASS_S))
-#define GPIO_PIN27_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN27_SYNC1_BYPASS_S  3
-/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN27_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN27_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN27_PAD_DRIVER_V  0x1
-#define GPIO_PIN27_PAD_DRIVER_S  2
-/* GPIO_PIN27_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN27_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN27_SYNC2_BYPASS_M  ((GPIO_PIN27_SYNC2_BYPASS_V)<<(GPIO_PIN27_SYNC2_BYPASS_S))
-#define GPIO_PIN27_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN27_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN28_REG          (DR_REG_GPIO_BASE + 0xE4)
-/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN28_INT_ENA    0x0000001F
-#define GPIO_PIN28_INT_ENA_M  ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S))
-#define GPIO_PIN28_INT_ENA_V  0x1F
-#define GPIO_PIN28_INT_ENA_S  13
-/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN28_CONFIG    0x00000003
-#define GPIO_PIN28_CONFIG_M  ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S))
-#define GPIO_PIN28_CONFIG_V  0x3
-#define GPIO_PIN28_CONFIG_S  11
-/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN28_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN28_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN28_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN28_WAKEUP_ENABLE_S  10
-/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN28_INT_TYPE    0x00000007
-#define GPIO_PIN28_INT_TYPE_M  ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S))
-#define GPIO_PIN28_INT_TYPE_V  0x7
-#define GPIO_PIN28_INT_TYPE_S  7
-/* GPIO_PIN28_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN28_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN28_SYNC1_BYPASS_M  ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S))
-#define GPIO_PIN28_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN28_SYNC1_BYPASS_S  3
-/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN28_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN28_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN28_PAD_DRIVER_V  0x1
-#define GPIO_PIN28_PAD_DRIVER_S  2
-/* GPIO_PIN28_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN28_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN28_SYNC2_BYPASS_M  ((GPIO_PIN28_SYNC2_BYPASS_V)<<(GPIO_PIN28_SYNC2_BYPASS_S))
-#define GPIO_PIN28_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN28_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN29_REG          (DR_REG_GPIO_BASE + 0xE8)
-/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN29_INT_ENA    0x0000001F
-#define GPIO_PIN29_INT_ENA_M  ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S))
-#define GPIO_PIN29_INT_ENA_V  0x1F
-#define GPIO_PIN29_INT_ENA_S  13
-/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN29_CONFIG    0x00000003
-#define GPIO_PIN29_CONFIG_M  ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S))
-#define GPIO_PIN29_CONFIG_V  0x3
-#define GPIO_PIN29_CONFIG_S  11
-/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN29_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN29_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN29_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN29_WAKEUP_ENABLE_S  10
-/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN29_INT_TYPE    0x00000007
-#define GPIO_PIN29_INT_TYPE_M  ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S))
-#define GPIO_PIN29_INT_TYPE_V  0x7
-#define GPIO_PIN29_INT_TYPE_S  7
-/* GPIO_PIN29_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN29_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN29_SYNC1_BYPASS_M  ((GPIO_PIN29_SYNC1_BYPASS_V)<<(GPIO_PIN29_SYNC1_BYPASS_S))
-#define GPIO_PIN29_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN29_SYNC1_BYPASS_S  3
-/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN29_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN29_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN29_PAD_DRIVER_V  0x1
-#define GPIO_PIN29_PAD_DRIVER_S  2
-/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN29_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN29_SYNC2_BYPASS_M  ((GPIO_PIN29_SYNC2_BYPASS_V)<<(GPIO_PIN29_SYNC2_BYPASS_S))
-#define GPIO_PIN29_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN29_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN30_REG          (DR_REG_GPIO_BASE + 0xEC)
-/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN30_INT_ENA    0x0000001F
-#define GPIO_PIN30_INT_ENA_M  ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S))
-#define GPIO_PIN30_INT_ENA_V  0x1F
-#define GPIO_PIN30_INT_ENA_S  13
-/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN30_CONFIG    0x00000003
-#define GPIO_PIN30_CONFIG_M  ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S))
-#define GPIO_PIN30_CONFIG_V  0x3
-#define GPIO_PIN30_CONFIG_S  11
-/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN30_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN30_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN30_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN30_WAKEUP_ENABLE_S  10
-/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN30_INT_TYPE    0x00000007
-#define GPIO_PIN30_INT_TYPE_M  ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S))
-#define GPIO_PIN30_INT_TYPE_V  0x7
-#define GPIO_PIN30_INT_TYPE_S  7
-/* GPIO_PIN30_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN30_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN30_SYNC1_BYPASS_M  ((GPIO_PIN30_SYNC1_BYPASS_V)<<(GPIO_PIN30_SYNC1_BYPASS_S))
-#define GPIO_PIN30_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN30_SYNC1_BYPASS_S  3
-/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN30_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN30_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN30_PAD_DRIVER_V  0x1
-#define GPIO_PIN30_PAD_DRIVER_S  2
-/* GPIO_PIN30_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN30_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN30_SYNC2_BYPASS_M  ((GPIO_PIN30_SYNC2_BYPASS_V)<<(GPIO_PIN30_SYNC2_BYPASS_S))
-#define GPIO_PIN30_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN30_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN31_REG          (DR_REG_GPIO_BASE + 0xF0)
-/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN31_INT_ENA    0x0000001F
-#define GPIO_PIN31_INT_ENA_M  ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S))
-#define GPIO_PIN31_INT_ENA_V  0x1F
-#define GPIO_PIN31_INT_ENA_S  13
-/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN31_CONFIG    0x00000003
-#define GPIO_PIN31_CONFIG_M  ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S))
-#define GPIO_PIN31_CONFIG_V  0x3
-#define GPIO_PIN31_CONFIG_S  11
-/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN31_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN31_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN31_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN31_WAKEUP_ENABLE_S  10
-/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN31_INT_TYPE    0x00000007
-#define GPIO_PIN31_INT_TYPE_M  ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S))
-#define GPIO_PIN31_INT_TYPE_V  0x7
-#define GPIO_PIN31_INT_TYPE_S  7
-/* GPIO_PIN31_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN31_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN31_SYNC1_BYPASS_M  ((GPIO_PIN31_SYNC1_BYPASS_V)<<(GPIO_PIN31_SYNC1_BYPASS_S))
-#define GPIO_PIN31_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN31_SYNC1_BYPASS_S  3
-/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN31_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN31_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN31_PAD_DRIVER_V  0x1
-#define GPIO_PIN31_PAD_DRIVER_S  2
-/* GPIO_PIN31_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN31_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN31_SYNC2_BYPASS_M  ((GPIO_PIN31_SYNC2_BYPASS_V)<<(GPIO_PIN31_SYNC2_BYPASS_S))
-#define GPIO_PIN31_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN31_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN32_REG          (DR_REG_GPIO_BASE + 0xF4)
-/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN32_INT_ENA    0x0000001F
-#define GPIO_PIN32_INT_ENA_M  ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S))
-#define GPIO_PIN32_INT_ENA_V  0x1F
-#define GPIO_PIN32_INT_ENA_S  13
-/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN32_CONFIG    0x00000003
-#define GPIO_PIN32_CONFIG_M  ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S))
-#define GPIO_PIN32_CONFIG_V  0x3
-#define GPIO_PIN32_CONFIG_S  11
-/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN32_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN32_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN32_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN32_WAKEUP_ENABLE_S  10
-/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN32_INT_TYPE    0x00000007
-#define GPIO_PIN32_INT_TYPE_M  ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S))
-#define GPIO_PIN32_INT_TYPE_V  0x7
-#define GPIO_PIN32_INT_TYPE_S  7
-/* GPIO_PIN32_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN32_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN32_SYNC1_BYPASS_M  ((GPIO_PIN32_SYNC1_BYPASS_V)<<(GPIO_PIN32_SYNC1_BYPASS_S))
-#define GPIO_PIN32_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN32_SYNC1_BYPASS_S  3
-/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN32_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN32_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN32_PAD_DRIVER_V  0x1
-#define GPIO_PIN32_PAD_DRIVER_S  2
-/* GPIO_PIN32_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN32_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN32_SYNC2_BYPASS_M  ((GPIO_PIN32_SYNC2_BYPASS_V)<<(GPIO_PIN32_SYNC2_BYPASS_S))
-#define GPIO_PIN32_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN32_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN33_REG          (DR_REG_GPIO_BASE + 0xF8)
-/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN33_INT_ENA    0x0000001F
-#define GPIO_PIN33_INT_ENA_M  ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S))
-#define GPIO_PIN33_INT_ENA_V  0x1F
-#define GPIO_PIN33_INT_ENA_S  13
-/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN33_CONFIG    0x00000003
-#define GPIO_PIN33_CONFIG_M  ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S))
-#define GPIO_PIN33_CONFIG_V  0x3
-#define GPIO_PIN33_CONFIG_S  11
-/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN33_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN33_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN33_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN33_WAKEUP_ENABLE_S  10
-/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN33_INT_TYPE    0x00000007
-#define GPIO_PIN33_INT_TYPE_M  ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S))
-#define GPIO_PIN33_INT_TYPE_V  0x7
-#define GPIO_PIN33_INT_TYPE_S  7
-/* GPIO_PIN33_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN33_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN33_SYNC1_BYPASS_M  ((GPIO_PIN33_SYNC1_BYPASS_V)<<(GPIO_PIN33_SYNC1_BYPASS_S))
-#define GPIO_PIN33_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN33_SYNC1_BYPASS_S  3
-/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN33_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN33_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN33_PAD_DRIVER_V  0x1
-#define GPIO_PIN33_PAD_DRIVER_S  2
-/* GPIO_PIN33_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN33_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN33_SYNC2_BYPASS_M  ((GPIO_PIN33_SYNC2_BYPASS_V)<<(GPIO_PIN33_SYNC2_BYPASS_S))
-#define GPIO_PIN33_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN33_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN34_REG          (DR_REG_GPIO_BASE + 0xFC)
-/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN34_INT_ENA    0x0000001F
-#define GPIO_PIN34_INT_ENA_M  ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S))
-#define GPIO_PIN34_INT_ENA_V  0x1F
-#define GPIO_PIN34_INT_ENA_S  13
-/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN34_CONFIG    0x00000003
-#define GPIO_PIN34_CONFIG_M  ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S))
-#define GPIO_PIN34_CONFIG_V  0x3
-#define GPIO_PIN34_CONFIG_S  11
-/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN34_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN34_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN34_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN34_WAKEUP_ENABLE_S  10
-/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN34_INT_TYPE    0x00000007
-#define GPIO_PIN34_INT_TYPE_M  ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S))
-#define GPIO_PIN34_INT_TYPE_V  0x7
-#define GPIO_PIN34_INT_TYPE_S  7
-/* GPIO_PIN34_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN34_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN34_SYNC1_BYPASS_M  ((GPIO_PIN34_SYNC1_BYPASS_V)<<(GPIO_PIN34_SYNC1_BYPASS_S))
-#define GPIO_PIN34_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN34_SYNC1_BYPASS_S  3
-/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN34_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN34_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN34_PAD_DRIVER_V  0x1
-#define GPIO_PIN34_PAD_DRIVER_S  2
-/* GPIO_PIN34_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN34_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN34_SYNC2_BYPASS_M  ((GPIO_PIN34_SYNC2_BYPASS_V)<<(GPIO_PIN34_SYNC2_BYPASS_S))
-#define GPIO_PIN34_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN34_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN35_REG          (DR_REG_GPIO_BASE + 0x100)
-/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN35_INT_ENA    0x0000001F
-#define GPIO_PIN35_INT_ENA_M  ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S))
-#define GPIO_PIN35_INT_ENA_V  0x1F
-#define GPIO_PIN35_INT_ENA_S  13
-/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN35_CONFIG    0x00000003
-#define GPIO_PIN35_CONFIG_M  ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S))
-#define GPIO_PIN35_CONFIG_V  0x3
-#define GPIO_PIN35_CONFIG_S  11
-/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN35_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN35_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN35_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN35_WAKEUP_ENABLE_S  10
-/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN35_INT_TYPE    0x00000007
-#define GPIO_PIN35_INT_TYPE_M  ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S))
-#define GPIO_PIN35_INT_TYPE_V  0x7
-#define GPIO_PIN35_INT_TYPE_S  7
-/* GPIO_PIN35_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN35_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN35_SYNC1_BYPASS_M  ((GPIO_PIN35_SYNC1_BYPASS_V)<<(GPIO_PIN35_SYNC1_BYPASS_S))
-#define GPIO_PIN35_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN35_SYNC1_BYPASS_S  3
-/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN35_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN35_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN35_PAD_DRIVER_V  0x1
-#define GPIO_PIN35_PAD_DRIVER_S  2
-/* GPIO_PIN35_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN35_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN35_SYNC2_BYPASS_M  ((GPIO_PIN35_SYNC2_BYPASS_V)<<(GPIO_PIN35_SYNC2_BYPASS_S))
-#define GPIO_PIN35_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN35_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN36_REG          (DR_REG_GPIO_BASE + 0x104)
-/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN36_INT_ENA    0x0000001F
-#define GPIO_PIN36_INT_ENA_M  ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S))
-#define GPIO_PIN36_INT_ENA_V  0x1F
-#define GPIO_PIN36_INT_ENA_S  13
-/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN36_CONFIG    0x00000003
-#define GPIO_PIN36_CONFIG_M  ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S))
-#define GPIO_PIN36_CONFIG_V  0x3
-#define GPIO_PIN36_CONFIG_S  11
-/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN36_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN36_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN36_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN36_WAKEUP_ENABLE_S  10
-/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN36_INT_TYPE    0x00000007
-#define GPIO_PIN36_INT_TYPE_M  ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S))
-#define GPIO_PIN36_INT_TYPE_V  0x7
-#define GPIO_PIN36_INT_TYPE_S  7
-/* GPIO_PIN36_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN36_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN36_SYNC1_BYPASS_M  ((GPIO_PIN36_SYNC1_BYPASS_V)<<(GPIO_PIN36_SYNC1_BYPASS_S))
-#define GPIO_PIN36_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN36_SYNC1_BYPASS_S  3
-/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN36_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN36_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN36_PAD_DRIVER_V  0x1
-#define GPIO_PIN36_PAD_DRIVER_S  2
-/* GPIO_PIN36_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN36_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN36_SYNC2_BYPASS_M  ((GPIO_PIN36_SYNC2_BYPASS_V)<<(GPIO_PIN36_SYNC2_BYPASS_S))
-#define GPIO_PIN36_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN36_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN37_REG          (DR_REG_GPIO_BASE + 0x108)
-/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN37_INT_ENA    0x0000001F
-#define GPIO_PIN37_INT_ENA_M  ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S))
-#define GPIO_PIN37_INT_ENA_V  0x1F
-#define GPIO_PIN37_INT_ENA_S  13
-/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN37_CONFIG    0x00000003
-#define GPIO_PIN37_CONFIG_M  ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S))
-#define GPIO_PIN37_CONFIG_V  0x3
-#define GPIO_PIN37_CONFIG_S  11
-/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN37_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN37_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN37_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN37_WAKEUP_ENABLE_S  10
-/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN37_INT_TYPE    0x00000007
-#define GPIO_PIN37_INT_TYPE_M  ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S))
-#define GPIO_PIN37_INT_TYPE_V  0x7
-#define GPIO_PIN37_INT_TYPE_S  7
-/* GPIO_PIN37_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN37_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN37_SYNC1_BYPASS_M  ((GPIO_PIN37_SYNC1_BYPASS_V)<<(GPIO_PIN37_SYNC1_BYPASS_S))
-#define GPIO_PIN37_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN37_SYNC1_BYPASS_S  3
-/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN37_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN37_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN37_PAD_DRIVER_V  0x1
-#define GPIO_PIN37_PAD_DRIVER_S  2
-/* GPIO_PIN37_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN37_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN37_SYNC2_BYPASS_M  ((GPIO_PIN37_SYNC2_BYPASS_V)<<(GPIO_PIN37_SYNC2_BYPASS_S))
-#define GPIO_PIN37_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN37_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN38_REG          (DR_REG_GPIO_BASE + 0x10C)
-/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN38_INT_ENA    0x0000001F
-#define GPIO_PIN38_INT_ENA_M  ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S))
-#define GPIO_PIN38_INT_ENA_V  0x1F
-#define GPIO_PIN38_INT_ENA_S  13
-/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN38_CONFIG    0x00000003
-#define GPIO_PIN38_CONFIG_M  ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S))
-#define GPIO_PIN38_CONFIG_V  0x3
-#define GPIO_PIN38_CONFIG_S  11
-/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN38_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN38_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN38_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN38_WAKEUP_ENABLE_S  10
-/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN38_INT_TYPE    0x00000007
-#define GPIO_PIN38_INT_TYPE_M  ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S))
-#define GPIO_PIN38_INT_TYPE_V  0x7
-#define GPIO_PIN38_INT_TYPE_S  7
-/* GPIO_PIN38_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN38_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN38_SYNC1_BYPASS_M  ((GPIO_PIN38_SYNC1_BYPASS_V)<<(GPIO_PIN38_SYNC1_BYPASS_S))
-#define GPIO_PIN38_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN38_SYNC1_BYPASS_S  3
-/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN38_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN38_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN38_PAD_DRIVER_V  0x1
-#define GPIO_PIN38_PAD_DRIVER_S  2
-/* GPIO_PIN38_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN38_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN38_SYNC2_BYPASS_M  ((GPIO_PIN38_SYNC2_BYPASS_V)<<(GPIO_PIN38_SYNC2_BYPASS_S))
-#define GPIO_PIN38_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN38_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN39_REG          (DR_REG_GPIO_BASE + 0x110)
-/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN39_INT_ENA    0x0000001F
-#define GPIO_PIN39_INT_ENA_M  ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S))
-#define GPIO_PIN39_INT_ENA_V  0x1F
-#define GPIO_PIN39_INT_ENA_S  13
-/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN39_CONFIG    0x00000003
-#define GPIO_PIN39_CONFIG_M  ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S))
-#define GPIO_PIN39_CONFIG_V  0x3
-#define GPIO_PIN39_CONFIG_S  11
-/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN39_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN39_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN39_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN39_WAKEUP_ENABLE_S  10
-/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN39_INT_TYPE    0x00000007
-#define GPIO_PIN39_INT_TYPE_M  ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S))
-#define GPIO_PIN39_INT_TYPE_V  0x7
-#define GPIO_PIN39_INT_TYPE_S  7
-/* GPIO_PIN39_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN39_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN39_SYNC1_BYPASS_M  ((GPIO_PIN39_SYNC1_BYPASS_V)<<(GPIO_PIN39_SYNC1_BYPASS_S))
-#define GPIO_PIN39_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN39_SYNC1_BYPASS_S  3
-/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN39_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN39_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN39_PAD_DRIVER_V  0x1
-#define GPIO_PIN39_PAD_DRIVER_S  2
-/* GPIO_PIN39_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN39_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN39_SYNC2_BYPASS_M  ((GPIO_PIN39_SYNC2_BYPASS_V)<<(GPIO_PIN39_SYNC2_BYPASS_S))
-#define GPIO_PIN39_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN39_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN40_REG          (DR_REG_GPIO_BASE + 0x114)
-/* GPIO_PIN40_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN40_INT_ENA    0x0000001F
-#define GPIO_PIN40_INT_ENA_M  ((GPIO_PIN40_INT_ENA_V)<<(GPIO_PIN40_INT_ENA_S))
-#define GPIO_PIN40_INT_ENA_V  0x1F
-#define GPIO_PIN40_INT_ENA_S  13
-/* GPIO_PIN40_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN40_CONFIG    0x00000003
-#define GPIO_PIN40_CONFIG_M  ((GPIO_PIN40_CONFIG_V)<<(GPIO_PIN40_CONFIG_S))
-#define GPIO_PIN40_CONFIG_V  0x3
-#define GPIO_PIN40_CONFIG_S  11
-/* GPIO_PIN40_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN40_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN40_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN40_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN40_WAKEUP_ENABLE_S  10
-/* GPIO_PIN40_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN40_INT_TYPE    0x00000007
-#define GPIO_PIN40_INT_TYPE_M  ((GPIO_PIN40_INT_TYPE_V)<<(GPIO_PIN40_INT_TYPE_S))
-#define GPIO_PIN40_INT_TYPE_V  0x7
-#define GPIO_PIN40_INT_TYPE_S  7
-/* GPIO_PIN40_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN40_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN40_SYNC1_BYPASS_M  ((GPIO_PIN40_SYNC1_BYPASS_V)<<(GPIO_PIN40_SYNC1_BYPASS_S))
-#define GPIO_PIN40_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN40_SYNC1_BYPASS_S  3
-/* GPIO_PIN40_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN40_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN40_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN40_PAD_DRIVER_V  0x1
-#define GPIO_PIN40_PAD_DRIVER_S  2
-/* GPIO_PIN40_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN40_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN40_SYNC2_BYPASS_M  ((GPIO_PIN40_SYNC2_BYPASS_V)<<(GPIO_PIN40_SYNC2_BYPASS_S))
-#define GPIO_PIN40_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN40_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN41_REG          (DR_REG_GPIO_BASE + 0x118)
-/* GPIO_PIN41_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN41_INT_ENA    0x0000001F
-#define GPIO_PIN41_INT_ENA_M  ((GPIO_PIN41_INT_ENA_V)<<(GPIO_PIN41_INT_ENA_S))
-#define GPIO_PIN41_INT_ENA_V  0x1F
-#define GPIO_PIN41_INT_ENA_S  13
-/* GPIO_PIN41_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN41_CONFIG    0x00000003
-#define GPIO_PIN41_CONFIG_M  ((GPIO_PIN41_CONFIG_V)<<(GPIO_PIN41_CONFIG_S))
-#define GPIO_PIN41_CONFIG_V  0x3
-#define GPIO_PIN41_CONFIG_S  11
-/* GPIO_PIN41_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN41_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN41_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN41_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN41_WAKEUP_ENABLE_S  10
-/* GPIO_PIN41_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN41_INT_TYPE    0x00000007
-#define GPIO_PIN41_INT_TYPE_M  ((GPIO_PIN41_INT_TYPE_V)<<(GPIO_PIN41_INT_TYPE_S))
-#define GPIO_PIN41_INT_TYPE_V  0x7
-#define GPIO_PIN41_INT_TYPE_S  7
-/* GPIO_PIN41_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN41_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN41_SYNC1_BYPASS_M  ((GPIO_PIN41_SYNC1_BYPASS_V)<<(GPIO_PIN41_SYNC1_BYPASS_S))
-#define GPIO_PIN41_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN41_SYNC1_BYPASS_S  3
-/* GPIO_PIN41_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN41_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN41_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN41_PAD_DRIVER_V  0x1
-#define GPIO_PIN41_PAD_DRIVER_S  2
-/* GPIO_PIN41_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN41_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN41_SYNC2_BYPASS_M  ((GPIO_PIN41_SYNC2_BYPASS_V)<<(GPIO_PIN41_SYNC2_BYPASS_S))
-#define GPIO_PIN41_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN41_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN42_REG          (DR_REG_GPIO_BASE + 0x11C)
-/* GPIO_PIN42_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN42_INT_ENA    0x0000001F
-#define GPIO_PIN42_INT_ENA_M  ((GPIO_PIN42_INT_ENA_V)<<(GPIO_PIN42_INT_ENA_S))
-#define GPIO_PIN42_INT_ENA_V  0x1F
-#define GPIO_PIN42_INT_ENA_S  13
-/* GPIO_PIN42_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN42_CONFIG    0x00000003
-#define GPIO_PIN42_CONFIG_M  ((GPIO_PIN42_CONFIG_V)<<(GPIO_PIN42_CONFIG_S))
-#define GPIO_PIN42_CONFIG_V  0x3
-#define GPIO_PIN42_CONFIG_S  11
-/* GPIO_PIN42_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN42_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN42_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN42_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN42_WAKEUP_ENABLE_S  10
-/* GPIO_PIN42_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN42_INT_TYPE    0x00000007
-#define GPIO_PIN42_INT_TYPE_M  ((GPIO_PIN42_INT_TYPE_V)<<(GPIO_PIN42_INT_TYPE_S))
-#define GPIO_PIN42_INT_TYPE_V  0x7
-#define GPIO_PIN42_INT_TYPE_S  7
-/* GPIO_PIN42_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN42_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN42_SYNC1_BYPASS_M  ((GPIO_PIN42_SYNC1_BYPASS_V)<<(GPIO_PIN42_SYNC1_BYPASS_S))
-#define GPIO_PIN42_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN42_SYNC1_BYPASS_S  3
-/* GPIO_PIN42_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN42_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN42_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN42_PAD_DRIVER_V  0x1
-#define GPIO_PIN42_PAD_DRIVER_S  2
-/* GPIO_PIN42_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN42_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN42_SYNC2_BYPASS_M  ((GPIO_PIN42_SYNC2_BYPASS_V)<<(GPIO_PIN42_SYNC2_BYPASS_S))
-#define GPIO_PIN42_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN42_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN43_REG          (DR_REG_GPIO_BASE + 0x120)
-/* GPIO_PIN43_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN43_INT_ENA    0x0000001F
-#define GPIO_PIN43_INT_ENA_M  ((GPIO_PIN43_INT_ENA_V)<<(GPIO_PIN43_INT_ENA_S))
-#define GPIO_PIN43_INT_ENA_V  0x1F
-#define GPIO_PIN43_INT_ENA_S  13
-/* GPIO_PIN43_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN43_CONFIG    0x00000003
-#define GPIO_PIN43_CONFIG_M  ((GPIO_PIN43_CONFIG_V)<<(GPIO_PIN43_CONFIG_S))
-#define GPIO_PIN43_CONFIG_V  0x3
-#define GPIO_PIN43_CONFIG_S  11
-/* GPIO_PIN43_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN43_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN43_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN43_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN43_WAKEUP_ENABLE_S  10
-/* GPIO_PIN43_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN43_INT_TYPE    0x00000007
-#define GPIO_PIN43_INT_TYPE_M  ((GPIO_PIN43_INT_TYPE_V)<<(GPIO_PIN43_INT_TYPE_S))
-#define GPIO_PIN43_INT_TYPE_V  0x7
-#define GPIO_PIN43_INT_TYPE_S  7
-/* GPIO_PIN43_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN43_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN43_SYNC1_BYPASS_M  ((GPIO_PIN43_SYNC1_BYPASS_V)<<(GPIO_PIN43_SYNC1_BYPASS_S))
-#define GPIO_PIN43_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN43_SYNC1_BYPASS_S  3
-/* GPIO_PIN43_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN43_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN43_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN43_PAD_DRIVER_V  0x1
-#define GPIO_PIN43_PAD_DRIVER_S  2
-/* GPIO_PIN43_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN43_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN43_SYNC2_BYPASS_M  ((GPIO_PIN43_SYNC2_BYPASS_V)<<(GPIO_PIN43_SYNC2_BYPASS_S))
-#define GPIO_PIN43_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN43_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN44_REG          (DR_REG_GPIO_BASE + 0x124)
-/* GPIO_PIN44_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN44_INT_ENA    0x0000001F
-#define GPIO_PIN44_INT_ENA_M  ((GPIO_PIN44_INT_ENA_V)<<(GPIO_PIN44_INT_ENA_S))
-#define GPIO_PIN44_INT_ENA_V  0x1F
-#define GPIO_PIN44_INT_ENA_S  13
-/* GPIO_PIN44_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN44_CONFIG    0x00000003
-#define GPIO_PIN44_CONFIG_M  ((GPIO_PIN44_CONFIG_V)<<(GPIO_PIN44_CONFIG_S))
-#define GPIO_PIN44_CONFIG_V  0x3
-#define GPIO_PIN44_CONFIG_S  11
-/* GPIO_PIN44_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN44_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN44_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN44_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN44_WAKEUP_ENABLE_S  10
-/* GPIO_PIN44_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN44_INT_TYPE    0x00000007
-#define GPIO_PIN44_INT_TYPE_M  ((GPIO_PIN44_INT_TYPE_V)<<(GPIO_PIN44_INT_TYPE_S))
-#define GPIO_PIN44_INT_TYPE_V  0x7
-#define GPIO_PIN44_INT_TYPE_S  7
-/* GPIO_PIN44_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN44_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN44_SYNC1_BYPASS_M  ((GPIO_PIN44_SYNC1_BYPASS_V)<<(GPIO_PIN44_SYNC1_BYPASS_S))
-#define GPIO_PIN44_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN44_SYNC1_BYPASS_S  3
-/* GPIO_PIN44_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN44_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN44_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN44_PAD_DRIVER_V  0x1
-#define GPIO_PIN44_PAD_DRIVER_S  2
-/* GPIO_PIN44_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN44_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN44_SYNC2_BYPASS_M  ((GPIO_PIN44_SYNC2_BYPASS_V)<<(GPIO_PIN44_SYNC2_BYPASS_S))
-#define GPIO_PIN44_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN44_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN45_REG          (DR_REG_GPIO_BASE + 0x128)
-/* GPIO_PIN45_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN45_INT_ENA    0x0000001F
-#define GPIO_PIN45_INT_ENA_M  ((GPIO_PIN45_INT_ENA_V)<<(GPIO_PIN45_INT_ENA_S))
-#define GPIO_PIN45_INT_ENA_V  0x1F
-#define GPIO_PIN45_INT_ENA_S  13
-/* GPIO_PIN45_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN45_CONFIG    0x00000003
-#define GPIO_PIN45_CONFIG_M  ((GPIO_PIN45_CONFIG_V)<<(GPIO_PIN45_CONFIG_S))
-#define GPIO_PIN45_CONFIG_V  0x3
-#define GPIO_PIN45_CONFIG_S  11
-/* GPIO_PIN45_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN45_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN45_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN45_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN45_WAKEUP_ENABLE_S  10
-/* GPIO_PIN45_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN45_INT_TYPE    0x00000007
-#define GPIO_PIN45_INT_TYPE_M  ((GPIO_PIN45_INT_TYPE_V)<<(GPIO_PIN45_INT_TYPE_S))
-#define GPIO_PIN45_INT_TYPE_V  0x7
-#define GPIO_PIN45_INT_TYPE_S  7
-/* GPIO_PIN45_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN45_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN45_SYNC1_BYPASS_M  ((GPIO_PIN45_SYNC1_BYPASS_V)<<(GPIO_PIN45_SYNC1_BYPASS_S))
-#define GPIO_PIN45_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN45_SYNC1_BYPASS_S  3
-/* GPIO_PIN45_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN45_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN45_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN45_PAD_DRIVER_V  0x1
-#define GPIO_PIN45_PAD_DRIVER_S  2
-/* GPIO_PIN45_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN45_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN45_SYNC2_BYPASS_M  ((GPIO_PIN45_SYNC2_BYPASS_V)<<(GPIO_PIN45_SYNC2_BYPASS_S))
-#define GPIO_PIN45_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN45_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN46_REG          (DR_REG_GPIO_BASE + 0x12C)
-/* GPIO_PIN46_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN46_INT_ENA    0x0000001F
-#define GPIO_PIN46_INT_ENA_M  ((GPIO_PIN46_INT_ENA_V)<<(GPIO_PIN46_INT_ENA_S))
-#define GPIO_PIN46_INT_ENA_V  0x1F
-#define GPIO_PIN46_INT_ENA_S  13
-/* GPIO_PIN46_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN46_CONFIG    0x00000003
-#define GPIO_PIN46_CONFIG_M  ((GPIO_PIN46_CONFIG_V)<<(GPIO_PIN46_CONFIG_S))
-#define GPIO_PIN46_CONFIG_V  0x3
-#define GPIO_PIN46_CONFIG_S  11
-/* GPIO_PIN46_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN46_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN46_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN46_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN46_WAKEUP_ENABLE_S  10
-/* GPIO_PIN46_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN46_INT_TYPE    0x00000007
-#define GPIO_PIN46_INT_TYPE_M  ((GPIO_PIN46_INT_TYPE_V)<<(GPIO_PIN46_INT_TYPE_S))
-#define GPIO_PIN46_INT_TYPE_V  0x7
-#define GPIO_PIN46_INT_TYPE_S  7
-/* GPIO_PIN46_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN46_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN46_SYNC1_BYPASS_M  ((GPIO_PIN46_SYNC1_BYPASS_V)<<(GPIO_PIN46_SYNC1_BYPASS_S))
-#define GPIO_PIN46_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN46_SYNC1_BYPASS_S  3
-/* GPIO_PIN46_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN46_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN46_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN46_PAD_DRIVER_V  0x1
-#define GPIO_PIN46_PAD_DRIVER_S  2
-/* GPIO_PIN46_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN46_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN46_SYNC2_BYPASS_M  ((GPIO_PIN46_SYNC2_BYPASS_V)<<(GPIO_PIN46_SYNC2_BYPASS_S))
-#define GPIO_PIN46_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN46_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN47_REG          (DR_REG_GPIO_BASE + 0x130)
-/* GPIO_PIN47_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN47_INT_ENA    0x0000001F
-#define GPIO_PIN47_INT_ENA_M  ((GPIO_PIN47_INT_ENA_V)<<(GPIO_PIN47_INT_ENA_S))
-#define GPIO_PIN47_INT_ENA_V  0x1F
-#define GPIO_PIN47_INT_ENA_S  13
-/* GPIO_PIN47_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN47_CONFIG    0x00000003
-#define GPIO_PIN47_CONFIG_M  ((GPIO_PIN47_CONFIG_V)<<(GPIO_PIN47_CONFIG_S))
-#define GPIO_PIN47_CONFIG_V  0x3
-#define GPIO_PIN47_CONFIG_S  11
-/* GPIO_PIN47_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN47_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN47_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN47_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN47_WAKEUP_ENABLE_S  10
-/* GPIO_PIN47_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN47_INT_TYPE    0x00000007
-#define GPIO_PIN47_INT_TYPE_M  ((GPIO_PIN47_INT_TYPE_V)<<(GPIO_PIN47_INT_TYPE_S))
-#define GPIO_PIN47_INT_TYPE_V  0x7
-#define GPIO_PIN47_INT_TYPE_S  7
-/* GPIO_PIN47_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN47_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN47_SYNC1_BYPASS_M  ((GPIO_PIN47_SYNC1_BYPASS_V)<<(GPIO_PIN47_SYNC1_BYPASS_S))
-#define GPIO_PIN47_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN47_SYNC1_BYPASS_S  3
-/* GPIO_PIN47_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN47_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN47_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN47_PAD_DRIVER_V  0x1
-#define GPIO_PIN47_PAD_DRIVER_S  2
-/* GPIO_PIN47_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN47_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN47_SYNC2_BYPASS_M  ((GPIO_PIN47_SYNC2_BYPASS_V)<<(GPIO_PIN47_SYNC2_BYPASS_S))
-#define GPIO_PIN47_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN47_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN48_REG          (DR_REG_GPIO_BASE + 0x134)
-/* GPIO_PIN48_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN48_INT_ENA    0x0000001F
-#define GPIO_PIN48_INT_ENA_M  ((GPIO_PIN48_INT_ENA_V)<<(GPIO_PIN48_INT_ENA_S))
-#define GPIO_PIN48_INT_ENA_V  0x1F
-#define GPIO_PIN48_INT_ENA_S  13
-/* GPIO_PIN48_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN48_CONFIG    0x00000003
-#define GPIO_PIN48_CONFIG_M  ((GPIO_PIN48_CONFIG_V)<<(GPIO_PIN48_CONFIG_S))
-#define GPIO_PIN48_CONFIG_V  0x3
-#define GPIO_PIN48_CONFIG_S  11
-/* GPIO_PIN48_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN48_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN48_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN48_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN48_WAKEUP_ENABLE_S  10
-/* GPIO_PIN48_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN48_INT_TYPE    0x00000007
-#define GPIO_PIN48_INT_TYPE_M  ((GPIO_PIN48_INT_TYPE_V)<<(GPIO_PIN48_INT_TYPE_S))
-#define GPIO_PIN48_INT_TYPE_V  0x7
-#define GPIO_PIN48_INT_TYPE_S  7
-/* GPIO_PIN48_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN48_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN48_SYNC1_BYPASS_M  ((GPIO_PIN48_SYNC1_BYPASS_V)<<(GPIO_PIN48_SYNC1_BYPASS_S))
-#define GPIO_PIN48_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN48_SYNC1_BYPASS_S  3
-/* GPIO_PIN48_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN48_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN48_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN48_PAD_DRIVER_V  0x1
-#define GPIO_PIN48_PAD_DRIVER_S  2
-/* GPIO_PIN48_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN48_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN48_SYNC2_BYPASS_M  ((GPIO_PIN48_SYNC2_BYPASS_V)<<(GPIO_PIN48_SYNC2_BYPASS_S))
-#define GPIO_PIN48_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN48_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN49_REG          (DR_REG_GPIO_BASE + 0x138)
-/* GPIO_PIN49_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN49_INT_ENA    0x0000001F
-#define GPIO_PIN49_INT_ENA_M  ((GPIO_PIN49_INT_ENA_V)<<(GPIO_PIN49_INT_ENA_S))
-#define GPIO_PIN49_INT_ENA_V  0x1F
-#define GPIO_PIN49_INT_ENA_S  13
-/* GPIO_PIN49_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN49_CONFIG    0x00000003
-#define GPIO_PIN49_CONFIG_M  ((GPIO_PIN49_CONFIG_V)<<(GPIO_PIN49_CONFIG_S))
-#define GPIO_PIN49_CONFIG_V  0x3
-#define GPIO_PIN49_CONFIG_S  11
-/* GPIO_PIN49_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN49_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN49_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN49_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN49_WAKEUP_ENABLE_S  10
-/* GPIO_PIN49_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN49_INT_TYPE    0x00000007
-#define GPIO_PIN49_INT_TYPE_M  ((GPIO_PIN49_INT_TYPE_V)<<(GPIO_PIN49_INT_TYPE_S))
-#define GPIO_PIN49_INT_TYPE_V  0x7
-#define GPIO_PIN49_INT_TYPE_S  7
-/* GPIO_PIN49_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN49_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN49_SYNC1_BYPASS_M  ((GPIO_PIN49_SYNC1_BYPASS_V)<<(GPIO_PIN49_SYNC1_BYPASS_S))
-#define GPIO_PIN49_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN49_SYNC1_BYPASS_S  3
-/* GPIO_PIN49_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN49_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN49_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN49_PAD_DRIVER_V  0x1
-#define GPIO_PIN49_PAD_DRIVER_S  2
-/* GPIO_PIN49_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN49_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN49_SYNC2_BYPASS_M  ((GPIO_PIN49_SYNC2_BYPASS_V)<<(GPIO_PIN49_SYNC2_BYPASS_S))
-#define GPIO_PIN49_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN49_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN50_REG          (DR_REG_GPIO_BASE + 0x13C)
-/* GPIO_PIN50_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN50_INT_ENA    0x0000001F
-#define GPIO_PIN50_INT_ENA_M  ((GPIO_PIN50_INT_ENA_V)<<(GPIO_PIN50_INT_ENA_S))
-#define GPIO_PIN50_INT_ENA_V  0x1F
-#define GPIO_PIN50_INT_ENA_S  13
-/* GPIO_PIN50_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN50_CONFIG    0x00000003
-#define GPIO_PIN50_CONFIG_M  ((GPIO_PIN50_CONFIG_V)<<(GPIO_PIN50_CONFIG_S))
-#define GPIO_PIN50_CONFIG_V  0x3
-#define GPIO_PIN50_CONFIG_S  11
-/* GPIO_PIN50_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN50_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN50_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN50_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN50_WAKEUP_ENABLE_S  10
-/* GPIO_PIN50_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN50_INT_TYPE    0x00000007
-#define GPIO_PIN50_INT_TYPE_M  ((GPIO_PIN50_INT_TYPE_V)<<(GPIO_PIN50_INT_TYPE_S))
-#define GPIO_PIN50_INT_TYPE_V  0x7
-#define GPIO_PIN50_INT_TYPE_S  7
-/* GPIO_PIN50_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN50_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN50_SYNC1_BYPASS_M  ((GPIO_PIN50_SYNC1_BYPASS_V)<<(GPIO_PIN50_SYNC1_BYPASS_S))
-#define GPIO_PIN50_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN50_SYNC1_BYPASS_S  3
-/* GPIO_PIN50_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN50_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN50_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN50_PAD_DRIVER_V  0x1
-#define GPIO_PIN50_PAD_DRIVER_S  2
-/* GPIO_PIN50_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN50_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN50_SYNC2_BYPASS_M  ((GPIO_PIN50_SYNC2_BYPASS_V)<<(GPIO_PIN50_SYNC2_BYPASS_S))
-#define GPIO_PIN50_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN50_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN51_REG          (DR_REG_GPIO_BASE + 0x140)
-/* GPIO_PIN51_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN51_INT_ENA    0x0000001F
-#define GPIO_PIN51_INT_ENA_M  ((GPIO_PIN51_INT_ENA_V)<<(GPIO_PIN51_INT_ENA_S))
-#define GPIO_PIN51_INT_ENA_V  0x1F
-#define GPIO_PIN51_INT_ENA_S  13
-/* GPIO_PIN51_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN51_CONFIG    0x00000003
-#define GPIO_PIN51_CONFIG_M  ((GPIO_PIN51_CONFIG_V)<<(GPIO_PIN51_CONFIG_S))
-#define GPIO_PIN51_CONFIG_V  0x3
-#define GPIO_PIN51_CONFIG_S  11
-/* GPIO_PIN51_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN51_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN51_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN51_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN51_WAKEUP_ENABLE_S  10
-/* GPIO_PIN51_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN51_INT_TYPE    0x00000007
-#define GPIO_PIN51_INT_TYPE_M  ((GPIO_PIN51_INT_TYPE_V)<<(GPIO_PIN51_INT_TYPE_S))
-#define GPIO_PIN51_INT_TYPE_V  0x7
-#define GPIO_PIN51_INT_TYPE_S  7
-/* GPIO_PIN51_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN51_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN51_SYNC1_BYPASS_M  ((GPIO_PIN51_SYNC1_BYPASS_V)<<(GPIO_PIN51_SYNC1_BYPASS_S))
-#define GPIO_PIN51_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN51_SYNC1_BYPASS_S  3
-/* GPIO_PIN51_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN51_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN51_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN51_PAD_DRIVER_V  0x1
-#define GPIO_PIN51_PAD_DRIVER_S  2
-/* GPIO_PIN51_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN51_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN51_SYNC2_BYPASS_M  ((GPIO_PIN51_SYNC2_BYPASS_V)<<(GPIO_PIN51_SYNC2_BYPASS_S))
-#define GPIO_PIN51_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN51_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN52_REG          (DR_REG_GPIO_BASE + 0x144)
-/* GPIO_PIN52_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN52_INT_ENA    0x0000001F
-#define GPIO_PIN52_INT_ENA_M  ((GPIO_PIN52_INT_ENA_V)<<(GPIO_PIN52_INT_ENA_S))
-#define GPIO_PIN52_INT_ENA_V  0x1F
-#define GPIO_PIN52_INT_ENA_S  13
-/* GPIO_PIN52_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN52_CONFIG    0x00000003
-#define GPIO_PIN52_CONFIG_M  ((GPIO_PIN52_CONFIG_V)<<(GPIO_PIN52_CONFIG_S))
-#define GPIO_PIN52_CONFIG_V  0x3
-#define GPIO_PIN52_CONFIG_S  11
-/* GPIO_PIN52_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN52_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN52_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN52_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN52_WAKEUP_ENABLE_S  10
-/* GPIO_PIN52_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN52_INT_TYPE    0x00000007
-#define GPIO_PIN52_INT_TYPE_M  ((GPIO_PIN52_INT_TYPE_V)<<(GPIO_PIN52_INT_TYPE_S))
-#define GPIO_PIN52_INT_TYPE_V  0x7
-#define GPIO_PIN52_INT_TYPE_S  7
-/* GPIO_PIN52_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN52_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN52_SYNC1_BYPASS_M  ((GPIO_PIN52_SYNC1_BYPASS_V)<<(GPIO_PIN52_SYNC1_BYPASS_S))
-#define GPIO_PIN52_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN52_SYNC1_BYPASS_S  3
-/* GPIO_PIN52_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN52_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN52_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN52_PAD_DRIVER_V  0x1
-#define GPIO_PIN52_PAD_DRIVER_S  2
-/* GPIO_PIN52_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN52_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN52_SYNC2_BYPASS_M  ((GPIO_PIN52_SYNC2_BYPASS_V)<<(GPIO_PIN52_SYNC2_BYPASS_S))
-#define GPIO_PIN52_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN52_SYNC2_BYPASS_S  0
-
-#define GPIO_PIN53_REG          (DR_REG_GPIO_BASE + 0x148)
-/* GPIO_PIN53_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
-/*description: .*/
-#define GPIO_PIN53_INT_ENA    0x0000001F
-#define GPIO_PIN53_INT_ENA_M  ((GPIO_PIN53_INT_ENA_V)<<(GPIO_PIN53_INT_ENA_S))
-#define GPIO_PIN53_INT_ENA_V  0x1F
-#define GPIO_PIN53_INT_ENA_S  13
-/* GPIO_PIN53_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN53_CONFIG    0x00000003
-#define GPIO_PIN53_CONFIG_M  ((GPIO_PIN53_CONFIG_V)<<(GPIO_PIN53_CONFIG_S))
-#define GPIO_PIN53_CONFIG_V  0x3
-#define GPIO_PIN53_CONFIG_S  11
-/* GPIO_PIN53_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN53_WAKEUP_ENABLE    (BIT(10))
-#define GPIO_PIN53_WAKEUP_ENABLE_M  (BIT(10))
-#define GPIO_PIN53_WAKEUP_ENABLE_V  0x1
-#define GPIO_PIN53_WAKEUP_ENABLE_S  10
-/* GPIO_PIN53_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
-/*description: .*/
-#define GPIO_PIN53_INT_TYPE    0x00000007
-#define GPIO_PIN53_INT_TYPE_M  ((GPIO_PIN53_INT_TYPE_V)<<(GPIO_PIN53_INT_TYPE_S))
-#define GPIO_PIN53_INT_TYPE_V  0x7
-#define GPIO_PIN53_INT_TYPE_S  7
-/* GPIO_PIN53_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN53_SYNC1_BYPASS    0x00000003
-#define GPIO_PIN53_SYNC1_BYPASS_M  ((GPIO_PIN53_SYNC1_BYPASS_V)<<(GPIO_PIN53_SYNC1_BYPASS_S))
-#define GPIO_PIN53_SYNC1_BYPASS_V  0x3
-#define GPIO_PIN53_SYNC1_BYPASS_S  3
-/* GPIO_PIN53_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_PIN53_PAD_DRIVER    (BIT(2))
-#define GPIO_PIN53_PAD_DRIVER_M  (BIT(2))
-#define GPIO_PIN53_PAD_DRIVER_V  0x1
-#define GPIO_PIN53_PAD_DRIVER_S  2
-/* GPIO_PIN53_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: .*/
-#define GPIO_PIN53_SYNC2_BYPASS    0x00000003
-#define GPIO_PIN53_SYNC2_BYPASS_M  ((GPIO_PIN53_SYNC2_BYPASS_V)<<(GPIO_PIN53_SYNC2_BYPASS_S))
-#define GPIO_PIN53_SYNC2_BYPASS_V  0x3
-#define GPIO_PIN53_SYNC2_BYPASS_S  0
-
-#define GPIO_STATUS_NEXT_REG          (DR_REG_GPIO_BASE + 0x14C)
-/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define GPIO_STATUS_INTERRUPT_NEXT    0xFFFFFFFF
-#define GPIO_STATUS_INTERRUPT_NEXT_M  ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S))
-#define GPIO_STATUS_INTERRUPT_NEXT_V  0xFFFFFFFF
-#define GPIO_STATUS_INTERRUPT_NEXT_S  0
-
-#define GPIO_STATUS_NEXT1_REG          (DR_REG_GPIO_BASE + 0x150)
-/* GPIO_STATUS_INTERRUPT_NEXT1 : RO ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: */
-#define GPIO_STATUS_INTERRUPT_NEXT1  0x003FFFFF
-#define GPIO_STATUS_INTERRUPT_NEXT1_M  ((GPIO_STATUS_INTERRUPT_NEXT1_V)<<(GPIO_STATUS_INTERRUPT_NEXT1_S))
-#define GPIO_STATUS_INTERRUPT_NEXT1_V  0x3FFFFF
-#define GPIO_STATUS_INTERRUPT_NEXT1_S  0
-
-#define GPIO_FUNC0_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x154)
-/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG0_IN_SEL    (BIT(7))
-#define GPIO_SIG0_IN_SEL_M  (BIT(7))
-#define GPIO_SIG0_IN_SEL_V  0x1
-#define GPIO_SIG0_IN_SEL_S  7
-/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC0_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC0_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC0_IN_INV_SEL_V  0x1
-#define GPIO_FUNC0_IN_INV_SEL_S  6
-/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC0_IN_SEL    0x0000003F
-#define GPIO_FUNC0_IN_SEL_M  ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
-#define GPIO_FUNC0_IN_SEL_V  0x3F
-#define GPIO_FUNC0_IN_SEL_S  0
-
-#define GPIO_FUNC1_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x158)
-/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG1_IN_SEL    (BIT(7))
-#define GPIO_SIG1_IN_SEL_M  (BIT(7))
-#define GPIO_SIG1_IN_SEL_V  0x1
-#define GPIO_SIG1_IN_SEL_S  7
-/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC1_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC1_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC1_IN_INV_SEL_V  0x1
-#define GPIO_FUNC1_IN_INV_SEL_S  6
-/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC1_IN_SEL    0x0000003F
-#define GPIO_FUNC1_IN_SEL_M  ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
-#define GPIO_FUNC1_IN_SEL_V  0x3F
-#define GPIO_FUNC1_IN_SEL_S  0
-
-#define GPIO_FUNC2_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x15C)
-/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG2_IN_SEL    (BIT(7))
-#define GPIO_SIG2_IN_SEL_M  (BIT(7))
-#define GPIO_SIG2_IN_SEL_V  0x1
-#define GPIO_SIG2_IN_SEL_S  7
-/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC2_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC2_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC2_IN_INV_SEL_V  0x1
-#define GPIO_FUNC2_IN_INV_SEL_S  6
-/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC2_IN_SEL    0x0000003F
-#define GPIO_FUNC2_IN_SEL_M  ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
-#define GPIO_FUNC2_IN_SEL_V  0x3F
-#define GPIO_FUNC2_IN_SEL_S  0
-
-#define GPIO_FUNC3_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x160)
-/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG3_IN_SEL    (BIT(7))
-#define GPIO_SIG3_IN_SEL_M  (BIT(7))
-#define GPIO_SIG3_IN_SEL_V  0x1
-#define GPIO_SIG3_IN_SEL_S  7
-/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC3_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC3_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC3_IN_INV_SEL_V  0x1
-#define GPIO_FUNC3_IN_INV_SEL_S  6
-/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC3_IN_SEL    0x0000003F
-#define GPIO_FUNC3_IN_SEL_M  ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
-#define GPIO_FUNC3_IN_SEL_V  0x3F
-#define GPIO_FUNC3_IN_SEL_S  0
-
-#define GPIO_FUNC4_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x164)
-/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG4_IN_SEL    (BIT(7))
-#define GPIO_SIG4_IN_SEL_M  (BIT(7))
-#define GPIO_SIG4_IN_SEL_V  0x1
-#define GPIO_SIG4_IN_SEL_S  7
-/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC4_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC4_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC4_IN_INV_SEL_V  0x1
-#define GPIO_FUNC4_IN_INV_SEL_S  6
-/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC4_IN_SEL    0x0000003F
-#define GPIO_FUNC4_IN_SEL_M  ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
-#define GPIO_FUNC4_IN_SEL_V  0x3F
-#define GPIO_FUNC4_IN_SEL_S  0
-
-#define GPIO_FUNC5_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x168)
-/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG5_IN_SEL    (BIT(7))
-#define GPIO_SIG5_IN_SEL_M  (BIT(7))
-#define GPIO_SIG5_IN_SEL_V  0x1
-#define GPIO_SIG5_IN_SEL_S  7
-/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC5_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC5_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC5_IN_INV_SEL_V  0x1
-#define GPIO_FUNC5_IN_INV_SEL_S  6
-/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC5_IN_SEL    0x0000003F
-#define GPIO_FUNC5_IN_SEL_M  ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
-#define GPIO_FUNC5_IN_SEL_V  0x3F
-#define GPIO_FUNC5_IN_SEL_S  0
-
-#define GPIO_FUNC6_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x16C)
-/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG6_IN_SEL    (BIT(7))
-#define GPIO_SIG6_IN_SEL_M  (BIT(7))
-#define GPIO_SIG6_IN_SEL_V  0x1
-#define GPIO_SIG6_IN_SEL_S  7
-/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC6_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC6_IN_INV_SEL_V  0x1
-#define GPIO_FUNC6_IN_INV_SEL_S  6
-/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC6_IN_SEL    0x0000003F
-#define GPIO_FUNC6_IN_SEL_M  ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
-#define GPIO_FUNC6_IN_SEL_V  0x3F
-#define GPIO_FUNC6_IN_SEL_S  0
-
-#define GPIO_FUNC7_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x170)
-/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG7_IN_SEL    (BIT(7))
-#define GPIO_SIG7_IN_SEL_M  (BIT(7))
-#define GPIO_SIG7_IN_SEL_V  0x1
-#define GPIO_SIG7_IN_SEL_S  7
-/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC7_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC7_IN_INV_SEL_V  0x1
-#define GPIO_FUNC7_IN_INV_SEL_S  6
-/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC7_IN_SEL    0x0000003F
-#define GPIO_FUNC7_IN_SEL_M  ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
-#define GPIO_FUNC7_IN_SEL_V  0x3F
-#define GPIO_FUNC7_IN_SEL_S  0
-
-#define GPIO_FUNC8_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x174)
-/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG8_IN_SEL    (BIT(7))
-#define GPIO_SIG8_IN_SEL_M  (BIT(7))
-#define GPIO_SIG8_IN_SEL_V  0x1
-#define GPIO_SIG8_IN_SEL_S  7
-/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC8_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC8_IN_INV_SEL_V  0x1
-#define GPIO_FUNC8_IN_INV_SEL_S  6
-/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC8_IN_SEL    0x0000003F
-#define GPIO_FUNC8_IN_SEL_M  ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
-#define GPIO_FUNC8_IN_SEL_V  0x3F
-#define GPIO_FUNC8_IN_SEL_S  0
-
-#define GPIO_FUNC9_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x178)
-/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG9_IN_SEL    (BIT(7))
-#define GPIO_SIG9_IN_SEL_M  (BIT(7))
-#define GPIO_SIG9_IN_SEL_V  0x1
-#define GPIO_SIG9_IN_SEL_S  7
-/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC9_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC9_IN_INV_SEL_V  0x1
-#define GPIO_FUNC9_IN_INV_SEL_S  6
-/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC9_IN_SEL    0x0000003F
-#define GPIO_FUNC9_IN_SEL_M  ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
-#define GPIO_FUNC9_IN_SEL_V  0x3F
-#define GPIO_FUNC9_IN_SEL_S  0
-
-#define GPIO_FUNC10_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x17C)
-/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG10_IN_SEL    (BIT(7))
-#define GPIO_SIG10_IN_SEL_M  (BIT(7))
-#define GPIO_SIG10_IN_SEL_V  0x1
-#define GPIO_SIG10_IN_SEL_S  7
-/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC10_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC10_IN_INV_SEL_V  0x1
-#define GPIO_FUNC10_IN_INV_SEL_S  6
-/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC10_IN_SEL    0x0000003F
-#define GPIO_FUNC10_IN_SEL_M  ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
-#define GPIO_FUNC10_IN_SEL_V  0x3F
-#define GPIO_FUNC10_IN_SEL_S  0
-
-#define GPIO_FUNC11_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x180)
-/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG11_IN_SEL    (BIT(7))
-#define GPIO_SIG11_IN_SEL_M  (BIT(7))
-#define GPIO_SIG11_IN_SEL_V  0x1
-#define GPIO_SIG11_IN_SEL_S  7
-/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC11_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC11_IN_INV_SEL_V  0x1
-#define GPIO_FUNC11_IN_INV_SEL_S  6
-/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC11_IN_SEL    0x0000003F
-#define GPIO_FUNC11_IN_SEL_M  ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
-#define GPIO_FUNC11_IN_SEL_V  0x3F
-#define GPIO_FUNC11_IN_SEL_S  0
-
-#define GPIO_FUNC12_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x184)
-/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG12_IN_SEL    (BIT(7))
-#define GPIO_SIG12_IN_SEL_M  (BIT(7))
-#define GPIO_SIG12_IN_SEL_V  0x1
-#define GPIO_SIG12_IN_SEL_S  7
-/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC12_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC12_IN_INV_SEL_V  0x1
-#define GPIO_FUNC12_IN_INV_SEL_S  6
-/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC12_IN_SEL    0x0000003F
-#define GPIO_FUNC12_IN_SEL_M  ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
-#define GPIO_FUNC12_IN_SEL_V  0x3F
-#define GPIO_FUNC12_IN_SEL_S  0
-
-#define GPIO_FUNC13_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x188)
-/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG13_IN_SEL    (BIT(7))
-#define GPIO_SIG13_IN_SEL_M  (BIT(7))
-#define GPIO_SIG13_IN_SEL_V  0x1
-#define GPIO_SIG13_IN_SEL_S  7
-/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC13_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC13_IN_INV_SEL_V  0x1
-#define GPIO_FUNC13_IN_INV_SEL_S  6
-/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC13_IN_SEL    0x0000003F
-#define GPIO_FUNC13_IN_SEL_M  ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
-#define GPIO_FUNC13_IN_SEL_V  0x3F
-#define GPIO_FUNC13_IN_SEL_S  0
-
-#define GPIO_FUNC14_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x18C)
-/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG14_IN_SEL    (BIT(7))
-#define GPIO_SIG14_IN_SEL_M  (BIT(7))
-#define GPIO_SIG14_IN_SEL_V  0x1
-#define GPIO_SIG14_IN_SEL_S  7
-/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC14_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC14_IN_INV_SEL_V  0x1
-#define GPIO_FUNC14_IN_INV_SEL_S  6
-/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC14_IN_SEL    0x0000003F
-#define GPIO_FUNC14_IN_SEL_M  ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
-#define GPIO_FUNC14_IN_SEL_V  0x3F
-#define GPIO_FUNC14_IN_SEL_S  0
-
-#define GPIO_FUNC15_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x190)
-/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG15_IN_SEL    (BIT(7))
-#define GPIO_SIG15_IN_SEL_M  (BIT(7))
-#define GPIO_SIG15_IN_SEL_V  0x1
-#define GPIO_SIG15_IN_SEL_S  7
-/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC15_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC15_IN_INV_SEL_V  0x1
-#define GPIO_FUNC15_IN_INV_SEL_S  6
-/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC15_IN_SEL    0x0000003F
-#define GPIO_FUNC15_IN_SEL_M  ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
-#define GPIO_FUNC15_IN_SEL_V  0x3F
-#define GPIO_FUNC15_IN_SEL_S  0
-
-#define GPIO_FUNC16_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x194)
-/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG16_IN_SEL    (BIT(7))
-#define GPIO_SIG16_IN_SEL_M  (BIT(7))
-#define GPIO_SIG16_IN_SEL_V  0x1
-#define GPIO_SIG16_IN_SEL_S  7
-/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC16_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC16_IN_INV_SEL_V  0x1
-#define GPIO_FUNC16_IN_INV_SEL_S  6
-/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC16_IN_SEL    0x0000003F
-#define GPIO_FUNC16_IN_SEL_M  ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
-#define GPIO_FUNC16_IN_SEL_V  0x3F
-#define GPIO_FUNC16_IN_SEL_S  0
-
-#define GPIO_FUNC17_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x198)
-/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG17_IN_SEL    (BIT(7))
-#define GPIO_SIG17_IN_SEL_M  (BIT(7))
-#define GPIO_SIG17_IN_SEL_V  0x1
-#define GPIO_SIG17_IN_SEL_S  7
-/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC17_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC17_IN_INV_SEL_V  0x1
-#define GPIO_FUNC17_IN_INV_SEL_S  6
-/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC17_IN_SEL    0x0000003F
-#define GPIO_FUNC17_IN_SEL_M  ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
-#define GPIO_FUNC17_IN_SEL_V  0x3F
-#define GPIO_FUNC17_IN_SEL_S  0
-
-#define GPIO_FUNC18_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x19C)
-/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG18_IN_SEL    (BIT(7))
-#define GPIO_SIG18_IN_SEL_M  (BIT(7))
-#define GPIO_SIG18_IN_SEL_V  0x1
-#define GPIO_SIG18_IN_SEL_S  7
-/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC18_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC18_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC18_IN_INV_SEL_V  0x1
-#define GPIO_FUNC18_IN_INV_SEL_S  6
-/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC18_IN_SEL    0x0000003F
-#define GPIO_FUNC18_IN_SEL_M  ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
-#define GPIO_FUNC18_IN_SEL_V  0x3F
-#define GPIO_FUNC18_IN_SEL_S  0
-
-#define GPIO_FUNC19_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A0)
-/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG19_IN_SEL    (BIT(7))
-#define GPIO_SIG19_IN_SEL_M  (BIT(7))
-#define GPIO_SIG19_IN_SEL_V  0x1
-#define GPIO_SIG19_IN_SEL_S  7
-/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC19_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC19_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC19_IN_INV_SEL_V  0x1
-#define GPIO_FUNC19_IN_INV_SEL_S  6
-/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC19_IN_SEL    0x0000003F
-#define GPIO_FUNC19_IN_SEL_M  ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
-#define GPIO_FUNC19_IN_SEL_V  0x3F
-#define GPIO_FUNC19_IN_SEL_S  0
-
-#define GPIO_FUNC20_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A4)
-/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG20_IN_SEL    (BIT(7))
-#define GPIO_SIG20_IN_SEL_M  (BIT(7))
-#define GPIO_SIG20_IN_SEL_V  0x1
-#define GPIO_SIG20_IN_SEL_S  7
-/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC20_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC20_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC20_IN_INV_SEL_V  0x1
-#define GPIO_FUNC20_IN_INV_SEL_S  6
-/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC20_IN_SEL    0x0000003F
-#define GPIO_FUNC20_IN_SEL_M  ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
-#define GPIO_FUNC20_IN_SEL_V  0x3F
-#define GPIO_FUNC20_IN_SEL_S  0
-
-#define GPIO_FUNC21_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A8)
-/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG21_IN_SEL    (BIT(7))
-#define GPIO_SIG21_IN_SEL_M  (BIT(7))
-#define GPIO_SIG21_IN_SEL_V  0x1
-#define GPIO_SIG21_IN_SEL_S  7
-/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC21_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC21_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC21_IN_INV_SEL_V  0x1
-#define GPIO_FUNC21_IN_INV_SEL_S  6
-/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC21_IN_SEL    0x0000003F
-#define GPIO_FUNC21_IN_SEL_M  ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
-#define GPIO_FUNC21_IN_SEL_V  0x3F
-#define GPIO_FUNC21_IN_SEL_S  0
-
-#define GPIO_FUNC22_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1AC)
-/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG22_IN_SEL    (BIT(7))
-#define GPIO_SIG22_IN_SEL_M  (BIT(7))
-#define GPIO_SIG22_IN_SEL_V  0x1
-#define GPIO_SIG22_IN_SEL_S  7
-/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC22_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC22_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC22_IN_INV_SEL_V  0x1
-#define GPIO_FUNC22_IN_INV_SEL_S  6
-/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC22_IN_SEL    0x0000003F
-#define GPIO_FUNC22_IN_SEL_M  ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
-#define GPIO_FUNC22_IN_SEL_V  0x3F
-#define GPIO_FUNC22_IN_SEL_S  0
-
-#define GPIO_FUNC23_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B0)
-/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG23_IN_SEL    (BIT(7))
-#define GPIO_SIG23_IN_SEL_M  (BIT(7))
-#define GPIO_SIG23_IN_SEL_V  0x1
-#define GPIO_SIG23_IN_SEL_S  7
-/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC23_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC23_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC23_IN_INV_SEL_V  0x1
-#define GPIO_FUNC23_IN_INV_SEL_S  6
-/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC23_IN_SEL    0x0000003F
-#define GPIO_FUNC23_IN_SEL_M  ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
-#define GPIO_FUNC23_IN_SEL_V  0x3F
-#define GPIO_FUNC23_IN_SEL_S  0
-
-#define GPIO_FUNC24_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B4)
-/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG24_IN_SEL    (BIT(7))
-#define GPIO_SIG24_IN_SEL_M  (BIT(7))
-#define GPIO_SIG24_IN_SEL_V  0x1
-#define GPIO_SIG24_IN_SEL_S  7
-/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC24_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC24_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC24_IN_INV_SEL_V  0x1
-#define GPIO_FUNC24_IN_INV_SEL_S  6
-/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC24_IN_SEL    0x0000003F
-#define GPIO_FUNC24_IN_SEL_M  ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
-#define GPIO_FUNC24_IN_SEL_V  0x3F
-#define GPIO_FUNC24_IN_SEL_S  0
-
-#define GPIO_FUNC25_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B8)
-/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG25_IN_SEL    (BIT(7))
-#define GPIO_SIG25_IN_SEL_M  (BIT(7))
-#define GPIO_SIG25_IN_SEL_V  0x1
-#define GPIO_SIG25_IN_SEL_S  7
-/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC25_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC25_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC25_IN_INV_SEL_V  0x1
-#define GPIO_FUNC25_IN_INV_SEL_S  6
-/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC25_IN_SEL    0x0000003F
-#define GPIO_FUNC25_IN_SEL_M  ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
-#define GPIO_FUNC25_IN_SEL_V  0x3F
-#define GPIO_FUNC25_IN_SEL_S  0
-
-#define GPIO_FUNC26_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1BC)
-/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG26_IN_SEL    (BIT(7))
-#define GPIO_SIG26_IN_SEL_M  (BIT(7))
-#define GPIO_SIG26_IN_SEL_V  0x1
-#define GPIO_SIG26_IN_SEL_S  7
-/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC26_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC26_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC26_IN_INV_SEL_V  0x1
-#define GPIO_FUNC26_IN_INV_SEL_S  6
-/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC26_IN_SEL    0x0000003F
-#define GPIO_FUNC26_IN_SEL_M  ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
-#define GPIO_FUNC26_IN_SEL_V  0x3F
-#define GPIO_FUNC26_IN_SEL_S  0
-
-#define GPIO_FUNC27_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C0)
-/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG27_IN_SEL    (BIT(7))
-#define GPIO_SIG27_IN_SEL_M  (BIT(7))
-#define GPIO_SIG27_IN_SEL_V  0x1
-#define GPIO_SIG27_IN_SEL_S  7
-/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC27_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC27_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC27_IN_INV_SEL_V  0x1
-#define GPIO_FUNC27_IN_INV_SEL_S  6
-/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC27_IN_SEL    0x0000003F
-#define GPIO_FUNC27_IN_SEL_M  ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
-#define GPIO_FUNC27_IN_SEL_V  0x3F
-#define GPIO_FUNC27_IN_SEL_S  0
-
-#define GPIO_FUNC28_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C4)
-/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG28_IN_SEL    (BIT(7))
-#define GPIO_SIG28_IN_SEL_M  (BIT(7))
-#define GPIO_SIG28_IN_SEL_V  0x1
-#define GPIO_SIG28_IN_SEL_S  7
-/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC28_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC28_IN_INV_SEL_V  0x1
-#define GPIO_FUNC28_IN_INV_SEL_S  6
-/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC28_IN_SEL    0x0000003F
-#define GPIO_FUNC28_IN_SEL_M  ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
-#define GPIO_FUNC28_IN_SEL_V  0x3F
-#define GPIO_FUNC28_IN_SEL_S  0
-
-#define GPIO_FUNC29_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C8)
-/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG29_IN_SEL    (BIT(7))
-#define GPIO_SIG29_IN_SEL_M  (BIT(7))
-#define GPIO_SIG29_IN_SEL_V  0x1
-#define GPIO_SIG29_IN_SEL_S  7
-/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC29_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC29_IN_INV_SEL_V  0x1
-#define GPIO_FUNC29_IN_INV_SEL_S  6
-/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC29_IN_SEL    0x0000003F
-#define GPIO_FUNC29_IN_SEL_M  ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
-#define GPIO_FUNC29_IN_SEL_V  0x3F
-#define GPIO_FUNC29_IN_SEL_S  0
-
-#define GPIO_FUNC30_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1CC)
-/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG30_IN_SEL    (BIT(7))
-#define GPIO_SIG30_IN_SEL_M  (BIT(7))
-#define GPIO_SIG30_IN_SEL_V  0x1
-#define GPIO_SIG30_IN_SEL_S  7
-/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC30_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC30_IN_INV_SEL_V  0x1
-#define GPIO_FUNC30_IN_INV_SEL_S  6
-/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC30_IN_SEL    0x0000003F
-#define GPIO_FUNC30_IN_SEL_M  ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
-#define GPIO_FUNC30_IN_SEL_V  0x3F
-#define GPIO_FUNC30_IN_SEL_S  0
-
-#define GPIO_FUNC31_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D0)
-/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG31_IN_SEL    (BIT(7))
-#define GPIO_SIG31_IN_SEL_M  (BIT(7))
-#define GPIO_SIG31_IN_SEL_V  0x1
-#define GPIO_SIG31_IN_SEL_S  7
-/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC31_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC31_IN_INV_SEL_V  0x1
-#define GPIO_FUNC31_IN_INV_SEL_S  6
-/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC31_IN_SEL    0x0000003F
-#define GPIO_FUNC31_IN_SEL_M  ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
-#define GPIO_FUNC31_IN_SEL_V  0x3F
-#define GPIO_FUNC31_IN_SEL_S  0
-
-#define GPIO_FUNC32_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D4)
-/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG32_IN_SEL    (BIT(7))
-#define GPIO_SIG32_IN_SEL_M  (BIT(7))
-#define GPIO_SIG32_IN_SEL_V  0x1
-#define GPIO_SIG32_IN_SEL_S  7
-/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC32_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC32_IN_INV_SEL_V  0x1
-#define GPIO_FUNC32_IN_INV_SEL_S  6
-/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC32_IN_SEL    0x0000003F
-#define GPIO_FUNC32_IN_SEL_M  ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
-#define GPIO_FUNC32_IN_SEL_V  0x3F
-#define GPIO_FUNC32_IN_SEL_S  0
-
-#define GPIO_FUNC33_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D8)
-/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG33_IN_SEL    (BIT(7))
-#define GPIO_SIG33_IN_SEL_M  (BIT(7))
-#define GPIO_SIG33_IN_SEL_V  0x1
-#define GPIO_SIG33_IN_SEL_S  7
-/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC33_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC33_IN_INV_SEL_V  0x1
-#define GPIO_FUNC33_IN_INV_SEL_S  6
-/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC33_IN_SEL    0x0000003F
-#define GPIO_FUNC33_IN_SEL_M  ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
-#define GPIO_FUNC33_IN_SEL_V  0x3F
-#define GPIO_FUNC33_IN_SEL_S  0
-
-#define GPIO_FUNC34_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1DC)
-/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG34_IN_SEL    (BIT(7))
-#define GPIO_SIG34_IN_SEL_M  (BIT(7))
-#define GPIO_SIG34_IN_SEL_V  0x1
-#define GPIO_SIG34_IN_SEL_S  7
-/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC34_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC34_IN_INV_SEL_V  0x1
-#define GPIO_FUNC34_IN_INV_SEL_S  6
-/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC34_IN_SEL    0x0000003F
-#define GPIO_FUNC34_IN_SEL_M  ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
-#define GPIO_FUNC34_IN_SEL_V  0x3F
-#define GPIO_FUNC34_IN_SEL_S  0
-
-#define GPIO_FUNC35_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E0)
-/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG35_IN_SEL    (BIT(7))
-#define GPIO_SIG35_IN_SEL_M  (BIT(7))
-#define GPIO_SIG35_IN_SEL_V  0x1
-#define GPIO_SIG35_IN_SEL_S  7
-/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC35_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC35_IN_INV_SEL_V  0x1
-#define GPIO_FUNC35_IN_INV_SEL_S  6
-/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC35_IN_SEL    0x0000003F
-#define GPIO_FUNC35_IN_SEL_M  ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
-#define GPIO_FUNC35_IN_SEL_V  0x3F
-#define GPIO_FUNC35_IN_SEL_S  0
-
-#define GPIO_FUNC36_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E4)
-/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG36_IN_SEL    (BIT(7))
-#define GPIO_SIG36_IN_SEL_M  (BIT(7))
-#define GPIO_SIG36_IN_SEL_V  0x1
-#define GPIO_SIG36_IN_SEL_S  7
-/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC36_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC36_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC36_IN_INV_SEL_V  0x1
-#define GPIO_FUNC36_IN_INV_SEL_S  6
-/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC36_IN_SEL    0x0000003F
-#define GPIO_FUNC36_IN_SEL_M  ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
-#define GPIO_FUNC36_IN_SEL_V  0x3F
-#define GPIO_FUNC36_IN_SEL_S  0
-
-#define GPIO_FUNC37_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E8)
-/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG37_IN_SEL    (BIT(7))
-#define GPIO_SIG37_IN_SEL_M  (BIT(7))
-#define GPIO_SIG37_IN_SEL_V  0x1
-#define GPIO_SIG37_IN_SEL_S  7
-/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC37_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC37_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC37_IN_INV_SEL_V  0x1
-#define GPIO_FUNC37_IN_INV_SEL_S  6
-/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC37_IN_SEL    0x0000003F
-#define GPIO_FUNC37_IN_SEL_M  ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
-#define GPIO_FUNC37_IN_SEL_V  0x3F
-#define GPIO_FUNC37_IN_SEL_S  0
-
-#define GPIO_FUNC38_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1EC)
-/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG38_IN_SEL    (BIT(7))
-#define GPIO_SIG38_IN_SEL_M  (BIT(7))
-#define GPIO_SIG38_IN_SEL_V  0x1
-#define GPIO_SIG38_IN_SEL_S  7
-/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC38_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC38_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC38_IN_INV_SEL_V  0x1
-#define GPIO_FUNC38_IN_INV_SEL_S  6
-/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC38_IN_SEL    0x0000003F
-#define GPIO_FUNC38_IN_SEL_M  ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
-#define GPIO_FUNC38_IN_SEL_V  0x3F
-#define GPIO_FUNC38_IN_SEL_S  0
-
-#define GPIO_FUNC39_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F0)
-/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG39_IN_SEL    (BIT(7))
-#define GPIO_SIG39_IN_SEL_M  (BIT(7))
-#define GPIO_SIG39_IN_SEL_V  0x1
-#define GPIO_SIG39_IN_SEL_S  7
-/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC39_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC39_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC39_IN_INV_SEL_V  0x1
-#define GPIO_FUNC39_IN_INV_SEL_S  6
-/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC39_IN_SEL    0x0000003F
-#define GPIO_FUNC39_IN_SEL_M  ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
-#define GPIO_FUNC39_IN_SEL_V  0x3F
-#define GPIO_FUNC39_IN_SEL_S  0
-
-#define GPIO_FUNC40_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F4)
-/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG40_IN_SEL    (BIT(7))
-#define GPIO_SIG40_IN_SEL_M  (BIT(7))
-#define GPIO_SIG40_IN_SEL_V  0x1
-#define GPIO_SIG40_IN_SEL_S  7
-/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC40_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC40_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC40_IN_INV_SEL_V  0x1
-#define GPIO_FUNC40_IN_INV_SEL_S  6
-/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC40_IN_SEL    0x0000003F
-#define GPIO_FUNC40_IN_SEL_M  ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
-#define GPIO_FUNC40_IN_SEL_V  0x3F
-#define GPIO_FUNC40_IN_SEL_S  0
-
-#define GPIO_FUNC41_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F8)
-/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG41_IN_SEL    (BIT(7))
-#define GPIO_SIG41_IN_SEL_M  (BIT(7))
-#define GPIO_SIG41_IN_SEL_V  0x1
-#define GPIO_SIG41_IN_SEL_S  7
-/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC41_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC41_IN_INV_SEL_V  0x1
-#define GPIO_FUNC41_IN_INV_SEL_S  6
-/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC41_IN_SEL    0x0000003F
-#define GPIO_FUNC41_IN_SEL_M  ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
-#define GPIO_FUNC41_IN_SEL_V  0x3F
-#define GPIO_FUNC41_IN_SEL_S  0
-
-#define GPIO_FUNC42_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1FC)
-/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG42_IN_SEL    (BIT(7))
-#define GPIO_SIG42_IN_SEL_M  (BIT(7))
-#define GPIO_SIG42_IN_SEL_V  0x1
-#define GPIO_SIG42_IN_SEL_S  7
-/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC42_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC42_IN_INV_SEL_V  0x1
-#define GPIO_FUNC42_IN_INV_SEL_S  6
-/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC42_IN_SEL    0x0000003F
-#define GPIO_FUNC42_IN_SEL_M  ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
-#define GPIO_FUNC42_IN_SEL_V  0x3F
-#define GPIO_FUNC42_IN_SEL_S  0
-
-#define GPIO_FUNC43_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x200)
-/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG43_IN_SEL    (BIT(7))
-#define GPIO_SIG43_IN_SEL_M  (BIT(7))
-#define GPIO_SIG43_IN_SEL_V  0x1
-#define GPIO_SIG43_IN_SEL_S  7
-/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC43_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC43_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC43_IN_INV_SEL_V  0x1
-#define GPIO_FUNC43_IN_INV_SEL_S  6
-/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC43_IN_SEL    0x0000003F
-#define GPIO_FUNC43_IN_SEL_M  ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
-#define GPIO_FUNC43_IN_SEL_V  0x3F
-#define GPIO_FUNC43_IN_SEL_S  0
-
-#define GPIO_FUNC44_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x204)
-/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG44_IN_SEL    (BIT(7))
-#define GPIO_SIG44_IN_SEL_M  (BIT(7))
-#define GPIO_SIG44_IN_SEL_V  0x1
-#define GPIO_SIG44_IN_SEL_S  7
-/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC44_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC44_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC44_IN_INV_SEL_V  0x1
-#define GPIO_FUNC44_IN_INV_SEL_S  6
-/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC44_IN_SEL    0x0000003F
-#define GPIO_FUNC44_IN_SEL_M  ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
-#define GPIO_FUNC44_IN_SEL_V  0x3F
-#define GPIO_FUNC44_IN_SEL_S  0
-
-#define GPIO_FUNC45_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x208)
-/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG45_IN_SEL    (BIT(7))
-#define GPIO_SIG45_IN_SEL_M  (BIT(7))
-#define GPIO_SIG45_IN_SEL_V  0x1
-#define GPIO_SIG45_IN_SEL_S  7
-/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC45_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC45_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC45_IN_INV_SEL_V  0x1
-#define GPIO_FUNC45_IN_INV_SEL_S  6
-/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC45_IN_SEL    0x0000003F
-#define GPIO_FUNC45_IN_SEL_M  ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
-#define GPIO_FUNC45_IN_SEL_V  0x3F
-#define GPIO_FUNC45_IN_SEL_S  0
-
-#define GPIO_FUNC46_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x20C)
-/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG46_IN_SEL    (BIT(7))
-#define GPIO_SIG46_IN_SEL_M  (BIT(7))
-#define GPIO_SIG46_IN_SEL_V  0x1
-#define GPIO_SIG46_IN_SEL_S  7
-/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC46_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC46_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC46_IN_INV_SEL_V  0x1
-#define GPIO_FUNC46_IN_INV_SEL_S  6
-/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC46_IN_SEL    0x0000003F
-#define GPIO_FUNC46_IN_SEL_M  ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
-#define GPIO_FUNC46_IN_SEL_V  0x3F
-#define GPIO_FUNC46_IN_SEL_S  0
-
-#define GPIO_FUNC47_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x210)
-/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG47_IN_SEL    (BIT(7))
-#define GPIO_SIG47_IN_SEL_M  (BIT(7))
-#define GPIO_SIG47_IN_SEL_V  0x1
-#define GPIO_SIG47_IN_SEL_S  7
-/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC47_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC47_IN_INV_SEL_V  0x1
-#define GPIO_FUNC47_IN_INV_SEL_S  6
-/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC47_IN_SEL    0x0000003F
-#define GPIO_FUNC47_IN_SEL_M  ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
-#define GPIO_FUNC47_IN_SEL_V  0x3F
-#define GPIO_FUNC47_IN_SEL_S  0
-
-#define GPIO_FUNC48_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x214)
-/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG48_IN_SEL    (BIT(7))
-#define GPIO_SIG48_IN_SEL_M  (BIT(7))
-#define GPIO_SIG48_IN_SEL_V  0x1
-#define GPIO_SIG48_IN_SEL_S  7
-/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC48_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC48_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC48_IN_INV_SEL_V  0x1
-#define GPIO_FUNC48_IN_INV_SEL_S  6
-/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC48_IN_SEL    0x0000003F
-#define GPIO_FUNC48_IN_SEL_M  ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
-#define GPIO_FUNC48_IN_SEL_V  0x3F
-#define GPIO_FUNC48_IN_SEL_S  0
-
-#define GPIO_FUNC49_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x218)
-/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG49_IN_SEL    (BIT(7))
-#define GPIO_SIG49_IN_SEL_M  (BIT(7))
-#define GPIO_SIG49_IN_SEL_V  0x1
-#define GPIO_SIG49_IN_SEL_S  7
-/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC49_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC49_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC49_IN_INV_SEL_V  0x1
-#define GPIO_FUNC49_IN_INV_SEL_S  6
-/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC49_IN_SEL    0x0000003F
-#define GPIO_FUNC49_IN_SEL_M  ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
-#define GPIO_FUNC49_IN_SEL_V  0x3F
-#define GPIO_FUNC49_IN_SEL_S  0
-
-#define GPIO_FUNC50_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x21C)
-/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG50_IN_SEL    (BIT(7))
-#define GPIO_SIG50_IN_SEL_M  (BIT(7))
-#define GPIO_SIG50_IN_SEL_V  0x1
-#define GPIO_SIG50_IN_SEL_S  7
-/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC50_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC50_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC50_IN_INV_SEL_V  0x1
-#define GPIO_FUNC50_IN_INV_SEL_S  6
-/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC50_IN_SEL    0x0000003F
-#define GPIO_FUNC50_IN_SEL_M  ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
-#define GPIO_FUNC50_IN_SEL_V  0x3F
-#define GPIO_FUNC50_IN_SEL_S  0
-
-#define GPIO_FUNC51_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x220)
-/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG51_IN_SEL    (BIT(7))
-#define GPIO_SIG51_IN_SEL_M  (BIT(7))
-#define GPIO_SIG51_IN_SEL_V  0x1
-#define GPIO_SIG51_IN_SEL_S  7
-/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC51_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC51_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC51_IN_INV_SEL_V  0x1
-#define GPIO_FUNC51_IN_INV_SEL_S  6
-/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC51_IN_SEL    0x0000003F
-#define GPIO_FUNC51_IN_SEL_M  ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
-#define GPIO_FUNC51_IN_SEL_V  0x3F
-#define GPIO_FUNC51_IN_SEL_S  0
-
-#define GPIO_FUNC52_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x224)
-/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG52_IN_SEL    (BIT(7))
-#define GPIO_SIG52_IN_SEL_M  (BIT(7))
-#define GPIO_SIG52_IN_SEL_V  0x1
-#define GPIO_SIG52_IN_SEL_S  7
-/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC52_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC52_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC52_IN_INV_SEL_V  0x1
-#define GPIO_FUNC52_IN_INV_SEL_S  6
-/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC52_IN_SEL    0x0000003F
-#define GPIO_FUNC52_IN_SEL_M  ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
-#define GPIO_FUNC52_IN_SEL_V  0x3F
-#define GPIO_FUNC52_IN_SEL_S  0
-
-#define GPIO_FUNC53_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x228)
-/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG53_IN_SEL    (BIT(7))
-#define GPIO_SIG53_IN_SEL_M  (BIT(7))
-#define GPIO_SIG53_IN_SEL_V  0x1
-#define GPIO_SIG53_IN_SEL_S  7
-/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC53_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC53_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC53_IN_INV_SEL_V  0x1
-#define GPIO_FUNC53_IN_INV_SEL_S  6
-/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC53_IN_SEL    0x0000003F
-#define GPIO_FUNC53_IN_SEL_M  ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
-#define GPIO_FUNC53_IN_SEL_V  0x3F
-#define GPIO_FUNC53_IN_SEL_S  0
-
-#define GPIO_FUNC54_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x22C)
-/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG54_IN_SEL    (BIT(7))
-#define GPIO_SIG54_IN_SEL_M  (BIT(7))
-#define GPIO_SIG54_IN_SEL_V  0x1
-#define GPIO_SIG54_IN_SEL_S  7
-/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC54_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC54_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC54_IN_INV_SEL_V  0x1
-#define GPIO_FUNC54_IN_INV_SEL_S  6
-/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC54_IN_SEL    0x0000003F
-#define GPIO_FUNC54_IN_SEL_M  ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
-#define GPIO_FUNC54_IN_SEL_V  0x3F
-#define GPIO_FUNC54_IN_SEL_S  0
-
-#define GPIO_FUNC55_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x230)
-/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG55_IN_SEL    (BIT(7))
-#define GPIO_SIG55_IN_SEL_M  (BIT(7))
-#define GPIO_SIG55_IN_SEL_V  0x1
-#define GPIO_SIG55_IN_SEL_S  7
-/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC55_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC55_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC55_IN_INV_SEL_V  0x1
-#define GPIO_FUNC55_IN_INV_SEL_S  6
-/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC55_IN_SEL    0x0000003F
-#define GPIO_FUNC55_IN_SEL_M  ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
-#define GPIO_FUNC55_IN_SEL_V  0x3F
-#define GPIO_FUNC55_IN_SEL_S  0
-
-#define GPIO_FUNC56_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x234)
-/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG56_IN_SEL    (BIT(7))
-#define GPIO_SIG56_IN_SEL_M  (BIT(7))
-#define GPIO_SIG56_IN_SEL_V  0x1
-#define GPIO_SIG56_IN_SEL_S  7
-/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC56_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC56_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC56_IN_INV_SEL_V  0x1
-#define GPIO_FUNC56_IN_INV_SEL_S  6
-/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC56_IN_SEL    0x0000003F
-#define GPIO_FUNC56_IN_SEL_M  ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
-#define GPIO_FUNC56_IN_SEL_V  0x3F
-#define GPIO_FUNC56_IN_SEL_S  0
-
-#define GPIO_FUNC57_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x238)
-/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG57_IN_SEL    (BIT(7))
-#define GPIO_SIG57_IN_SEL_M  (BIT(7))
-#define GPIO_SIG57_IN_SEL_V  0x1
-#define GPIO_SIG57_IN_SEL_S  7
-/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC57_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC57_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC57_IN_INV_SEL_V  0x1
-#define GPIO_FUNC57_IN_INV_SEL_S  6
-/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC57_IN_SEL    0x0000003F
-#define GPIO_FUNC57_IN_SEL_M  ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
-#define GPIO_FUNC57_IN_SEL_V  0x3F
-#define GPIO_FUNC57_IN_SEL_S  0
-
-#define GPIO_FUNC58_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x23C)
-/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG58_IN_SEL    (BIT(7))
-#define GPIO_SIG58_IN_SEL_M  (BIT(7))
-#define GPIO_SIG58_IN_SEL_V  0x1
-#define GPIO_SIG58_IN_SEL_S  7
-/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC58_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC58_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC58_IN_INV_SEL_V  0x1
-#define GPIO_FUNC58_IN_INV_SEL_S  6
-/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC58_IN_SEL    0x0000003F
-#define GPIO_FUNC58_IN_SEL_M  ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
-#define GPIO_FUNC58_IN_SEL_V  0x3F
-#define GPIO_FUNC58_IN_SEL_S  0
-
-#define GPIO_FUNC59_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x240)
-/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG59_IN_SEL    (BIT(7))
-#define GPIO_SIG59_IN_SEL_M  (BIT(7))
-#define GPIO_SIG59_IN_SEL_V  0x1
-#define GPIO_SIG59_IN_SEL_S  7
-/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC59_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC59_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC59_IN_INV_SEL_V  0x1
-#define GPIO_FUNC59_IN_INV_SEL_S  6
-/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC59_IN_SEL    0x0000003F
-#define GPIO_FUNC59_IN_SEL_M  ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
-#define GPIO_FUNC59_IN_SEL_V  0x3F
-#define GPIO_FUNC59_IN_SEL_S  0
-
-#define GPIO_FUNC60_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x244)
-/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG60_IN_SEL    (BIT(7))
-#define GPIO_SIG60_IN_SEL_M  (BIT(7))
-#define GPIO_SIG60_IN_SEL_V  0x1
-#define GPIO_SIG60_IN_SEL_S  7
-/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC60_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC60_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC60_IN_INV_SEL_V  0x1
-#define GPIO_FUNC60_IN_INV_SEL_S  6
-/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC60_IN_SEL    0x0000003F
-#define GPIO_FUNC60_IN_SEL_M  ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
-#define GPIO_FUNC60_IN_SEL_V  0x3F
-#define GPIO_FUNC60_IN_SEL_S  0
-
-#define GPIO_FUNC61_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x248)
-/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG61_IN_SEL    (BIT(7))
-#define GPIO_SIG61_IN_SEL_M  (BIT(7))
-#define GPIO_SIG61_IN_SEL_V  0x1
-#define GPIO_SIG61_IN_SEL_S  7
-/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC61_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC61_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC61_IN_INV_SEL_V  0x1
-#define GPIO_FUNC61_IN_INV_SEL_S  6
-/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC61_IN_SEL    0x0000003F
-#define GPIO_FUNC61_IN_SEL_M  ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
-#define GPIO_FUNC61_IN_SEL_V  0x3F
-#define GPIO_FUNC61_IN_SEL_S  0
-
-#define GPIO_FUNC62_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x24C)
-/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG62_IN_SEL    (BIT(7))
-#define GPIO_SIG62_IN_SEL_M  (BIT(7))
-#define GPIO_SIG62_IN_SEL_V  0x1
-#define GPIO_SIG62_IN_SEL_S  7
-/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC62_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC62_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC62_IN_INV_SEL_V  0x1
-#define GPIO_FUNC62_IN_INV_SEL_S  6
-/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC62_IN_SEL    0x0000003F
-#define GPIO_FUNC62_IN_SEL_M  ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
-#define GPIO_FUNC62_IN_SEL_V  0x3F
-#define GPIO_FUNC62_IN_SEL_S  0
-
-#define GPIO_FUNC63_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x250)
-/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG63_IN_SEL    (BIT(7))
-#define GPIO_SIG63_IN_SEL_M  (BIT(7))
-#define GPIO_SIG63_IN_SEL_V  0x1
-#define GPIO_SIG63_IN_SEL_S  7
-/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC63_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC63_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC63_IN_INV_SEL_V  0x1
-#define GPIO_FUNC63_IN_INV_SEL_S  6
-/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC63_IN_SEL    0x0000003F
-#define GPIO_FUNC63_IN_SEL_M  ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
-#define GPIO_FUNC63_IN_SEL_V  0x3F
-#define GPIO_FUNC63_IN_SEL_S  0
-
-#define GPIO_FUNC64_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x254)
-/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG64_IN_SEL    (BIT(7))
-#define GPIO_SIG64_IN_SEL_M  (BIT(7))
-#define GPIO_SIG64_IN_SEL_V  0x1
-#define GPIO_SIG64_IN_SEL_S  7
-/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC64_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC64_IN_INV_SEL_V  0x1
-#define GPIO_FUNC64_IN_INV_SEL_S  6
-/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC64_IN_SEL    0x0000003F
-#define GPIO_FUNC64_IN_SEL_M  ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
-#define GPIO_FUNC64_IN_SEL_V  0x3F
-#define GPIO_FUNC64_IN_SEL_S  0
-
-#define GPIO_FUNC65_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x258)
-/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG65_IN_SEL    (BIT(7))
-#define GPIO_SIG65_IN_SEL_M  (BIT(7))
-#define GPIO_SIG65_IN_SEL_V  0x1
-#define GPIO_SIG65_IN_SEL_S  7
-/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC65_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC65_IN_INV_SEL_V  0x1
-#define GPIO_FUNC65_IN_INV_SEL_S  6
-/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC65_IN_SEL    0x0000003F
-#define GPIO_FUNC65_IN_SEL_M  ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
-#define GPIO_FUNC65_IN_SEL_V  0x3F
-#define GPIO_FUNC65_IN_SEL_S  0
-
-#define GPIO_FUNC66_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x25C)
-/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG66_IN_SEL    (BIT(7))
-#define GPIO_SIG66_IN_SEL_M  (BIT(7))
-#define GPIO_SIG66_IN_SEL_V  0x1
-#define GPIO_SIG66_IN_SEL_S  7
-/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC66_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC66_IN_INV_SEL_V  0x1
-#define GPIO_FUNC66_IN_INV_SEL_S  6
-/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC66_IN_SEL    0x0000003F
-#define GPIO_FUNC66_IN_SEL_M  ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
-#define GPIO_FUNC66_IN_SEL_V  0x3F
-#define GPIO_FUNC66_IN_SEL_S  0
-
-#define GPIO_FUNC67_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x260)
-/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG67_IN_SEL    (BIT(7))
-#define GPIO_SIG67_IN_SEL_M  (BIT(7))
-#define GPIO_SIG67_IN_SEL_V  0x1
-#define GPIO_SIG67_IN_SEL_S  7
-/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC67_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC67_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC67_IN_INV_SEL_V  0x1
-#define GPIO_FUNC67_IN_INV_SEL_S  6
-/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC67_IN_SEL    0x0000003F
-#define GPIO_FUNC67_IN_SEL_M  ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
-#define GPIO_FUNC67_IN_SEL_V  0x3F
-#define GPIO_FUNC67_IN_SEL_S  0
-
-#define GPIO_FUNC68_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x264)
-/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG68_IN_SEL    (BIT(7))
-#define GPIO_SIG68_IN_SEL_M  (BIT(7))
-#define GPIO_SIG68_IN_SEL_V  0x1
-#define GPIO_SIG68_IN_SEL_S  7
-/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC68_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC68_IN_INV_SEL_V  0x1
-#define GPIO_FUNC68_IN_INV_SEL_S  6
-/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC68_IN_SEL    0x0000003F
-#define GPIO_FUNC68_IN_SEL_M  ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
-#define GPIO_FUNC68_IN_SEL_V  0x3F
-#define GPIO_FUNC68_IN_SEL_S  0
-
-#define GPIO_FUNC69_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x268)
-/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG69_IN_SEL    (BIT(7))
-#define GPIO_SIG69_IN_SEL_M  (BIT(7))
-#define GPIO_SIG69_IN_SEL_V  0x1
-#define GPIO_SIG69_IN_SEL_S  7
-/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC69_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC69_IN_INV_SEL_V  0x1
-#define GPIO_FUNC69_IN_INV_SEL_S  6
-/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC69_IN_SEL    0x0000003F
-#define GPIO_FUNC69_IN_SEL_M  ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
-#define GPIO_FUNC69_IN_SEL_V  0x3F
-#define GPIO_FUNC69_IN_SEL_S  0
-
-#define GPIO_FUNC70_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x26C)
-/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG70_IN_SEL    (BIT(7))
-#define GPIO_SIG70_IN_SEL_M  (BIT(7))
-#define GPIO_SIG70_IN_SEL_V  0x1
-#define GPIO_SIG70_IN_SEL_S  7
-/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC70_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC70_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC70_IN_INV_SEL_V  0x1
-#define GPIO_FUNC70_IN_INV_SEL_S  6
-/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC70_IN_SEL    0x0000003F
-#define GPIO_FUNC70_IN_SEL_M  ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
-#define GPIO_FUNC70_IN_SEL_V  0x3F
-#define GPIO_FUNC70_IN_SEL_S  0
-
-#define GPIO_FUNC71_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x270)
-/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG71_IN_SEL    (BIT(7))
-#define GPIO_SIG71_IN_SEL_M  (BIT(7))
-#define GPIO_SIG71_IN_SEL_V  0x1
-#define GPIO_SIG71_IN_SEL_S  7
-/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC71_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC71_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC71_IN_INV_SEL_V  0x1
-#define GPIO_FUNC71_IN_INV_SEL_S  6
-/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC71_IN_SEL    0x0000003F
-#define GPIO_FUNC71_IN_SEL_M  ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
-#define GPIO_FUNC71_IN_SEL_V  0x3F
-#define GPIO_FUNC71_IN_SEL_S  0
-
-#define GPIO_FUNC72_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x274)
-/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG72_IN_SEL    (BIT(7))
-#define GPIO_SIG72_IN_SEL_M  (BIT(7))
-#define GPIO_SIG72_IN_SEL_V  0x1
-#define GPIO_SIG72_IN_SEL_S  7
-/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC72_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC72_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC72_IN_INV_SEL_V  0x1
-#define GPIO_FUNC72_IN_INV_SEL_S  6
-/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC72_IN_SEL    0x0000003F
-#define GPIO_FUNC72_IN_SEL_M  ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
-#define GPIO_FUNC72_IN_SEL_V  0x3F
-#define GPIO_FUNC72_IN_SEL_S  0
-
-#define GPIO_FUNC73_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x278)
-/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG73_IN_SEL    (BIT(7))
-#define GPIO_SIG73_IN_SEL_M  (BIT(7))
-#define GPIO_SIG73_IN_SEL_V  0x1
-#define GPIO_SIG73_IN_SEL_S  7
-/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC73_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC73_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC73_IN_INV_SEL_V  0x1
-#define GPIO_FUNC73_IN_INV_SEL_S  6
-/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC73_IN_SEL    0x0000003F
-#define GPIO_FUNC73_IN_SEL_M  ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
-#define GPIO_FUNC73_IN_SEL_V  0x3F
-#define GPIO_FUNC73_IN_SEL_S  0
-
-#define GPIO_FUNC74_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x27C)
-/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG74_IN_SEL    (BIT(7))
-#define GPIO_SIG74_IN_SEL_M  (BIT(7))
-#define GPIO_SIG74_IN_SEL_V  0x1
-#define GPIO_SIG74_IN_SEL_S  7
-/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC74_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC74_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC74_IN_INV_SEL_V  0x1
-#define GPIO_FUNC74_IN_INV_SEL_S  6
-/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC74_IN_SEL    0x0000003F
-#define GPIO_FUNC74_IN_SEL_M  ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
-#define GPIO_FUNC74_IN_SEL_V  0x3F
-#define GPIO_FUNC74_IN_SEL_S  0
-
-#define GPIO_FUNC75_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x280)
-/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG75_IN_SEL    (BIT(7))
-#define GPIO_SIG75_IN_SEL_M  (BIT(7))
-#define GPIO_SIG75_IN_SEL_V  0x1
-#define GPIO_SIG75_IN_SEL_S  7
-/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC75_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC75_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC75_IN_INV_SEL_V  0x1
-#define GPIO_FUNC75_IN_INV_SEL_S  6
-/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC75_IN_SEL    0x0000003F
-#define GPIO_FUNC75_IN_SEL_M  ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
-#define GPIO_FUNC75_IN_SEL_V  0x3F
-#define GPIO_FUNC75_IN_SEL_S  0
-
-#define GPIO_FUNC76_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x284)
-/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG76_IN_SEL    (BIT(7))
-#define GPIO_SIG76_IN_SEL_M  (BIT(7))
-#define GPIO_SIG76_IN_SEL_V  0x1
-#define GPIO_SIG76_IN_SEL_S  7
-/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC76_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC76_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC76_IN_INV_SEL_V  0x1
-#define GPIO_FUNC76_IN_INV_SEL_S  6
-/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC76_IN_SEL    0x0000003F
-#define GPIO_FUNC76_IN_SEL_M  ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
-#define GPIO_FUNC76_IN_SEL_V  0x3F
-#define GPIO_FUNC76_IN_SEL_S  0
-
-#define GPIO_FUNC77_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x288)
-/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG77_IN_SEL    (BIT(7))
-#define GPIO_SIG77_IN_SEL_M  (BIT(7))
-#define GPIO_SIG77_IN_SEL_V  0x1
-#define GPIO_SIG77_IN_SEL_S  7
-/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC77_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC77_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC77_IN_INV_SEL_V  0x1
-#define GPIO_FUNC77_IN_INV_SEL_S  6
-/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC77_IN_SEL    0x0000003F
-#define GPIO_FUNC77_IN_SEL_M  ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
-#define GPIO_FUNC77_IN_SEL_V  0x3F
-#define GPIO_FUNC77_IN_SEL_S  0
-
-#define GPIO_FUNC78_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x28C)
-/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG78_IN_SEL    (BIT(7))
-#define GPIO_SIG78_IN_SEL_M  (BIT(7))
-#define GPIO_SIG78_IN_SEL_V  0x1
-#define GPIO_SIG78_IN_SEL_S  7
-/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC78_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC78_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC78_IN_INV_SEL_V  0x1
-#define GPIO_FUNC78_IN_INV_SEL_S  6
-/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC78_IN_SEL    0x0000003F
-#define GPIO_FUNC78_IN_SEL_M  ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
-#define GPIO_FUNC78_IN_SEL_V  0x3F
-#define GPIO_FUNC78_IN_SEL_S  0
-
-#define GPIO_FUNC79_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x290)
-/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG79_IN_SEL    (BIT(7))
-#define GPIO_SIG79_IN_SEL_M  (BIT(7))
-#define GPIO_SIG79_IN_SEL_V  0x1
-#define GPIO_SIG79_IN_SEL_S  7
-/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC79_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC79_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC79_IN_INV_SEL_V  0x1
-#define GPIO_FUNC79_IN_INV_SEL_S  6
-/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC79_IN_SEL    0x0000003F
-#define GPIO_FUNC79_IN_SEL_M  ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
-#define GPIO_FUNC79_IN_SEL_V  0x3F
-#define GPIO_FUNC79_IN_SEL_S  0
-
-#define GPIO_FUNC80_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x294)
-/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG80_IN_SEL    (BIT(7))
-#define GPIO_SIG80_IN_SEL_M  (BIT(7))
-#define GPIO_SIG80_IN_SEL_V  0x1
-#define GPIO_SIG80_IN_SEL_S  7
-/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC80_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC80_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC80_IN_INV_SEL_V  0x1
-#define GPIO_FUNC80_IN_INV_SEL_S  6
-/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC80_IN_SEL    0x0000003F
-#define GPIO_FUNC80_IN_SEL_M  ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
-#define GPIO_FUNC80_IN_SEL_V  0x3F
-#define GPIO_FUNC80_IN_SEL_S  0
-
-#define GPIO_FUNC81_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x298)
-/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG81_IN_SEL    (BIT(7))
-#define GPIO_SIG81_IN_SEL_M  (BIT(7))
-#define GPIO_SIG81_IN_SEL_V  0x1
-#define GPIO_SIG81_IN_SEL_S  7
-/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC81_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC81_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC81_IN_INV_SEL_V  0x1
-#define GPIO_FUNC81_IN_INV_SEL_S  6
-/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC81_IN_SEL    0x0000003F
-#define GPIO_FUNC81_IN_SEL_M  ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
-#define GPIO_FUNC81_IN_SEL_V  0x3F
-#define GPIO_FUNC81_IN_SEL_S  0
-
-#define GPIO_FUNC82_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x29C)
-/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG82_IN_SEL    (BIT(7))
-#define GPIO_SIG82_IN_SEL_M  (BIT(7))
-#define GPIO_SIG82_IN_SEL_V  0x1
-#define GPIO_SIG82_IN_SEL_S  7
-/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC82_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC82_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC82_IN_INV_SEL_V  0x1
-#define GPIO_FUNC82_IN_INV_SEL_S  6
-/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC82_IN_SEL    0x0000003F
-#define GPIO_FUNC82_IN_SEL_M  ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
-#define GPIO_FUNC82_IN_SEL_V  0x3F
-#define GPIO_FUNC82_IN_SEL_S  0
-
-#define GPIO_FUNC83_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A0)
-/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG83_IN_SEL    (BIT(7))
-#define GPIO_SIG83_IN_SEL_M  (BIT(7))
-#define GPIO_SIG83_IN_SEL_V  0x1
-#define GPIO_SIG83_IN_SEL_S  7
-/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC83_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC83_IN_INV_SEL_V  0x1
-#define GPIO_FUNC83_IN_INV_SEL_S  6
-/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC83_IN_SEL    0x0000003F
-#define GPIO_FUNC83_IN_SEL_M  ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
-#define GPIO_FUNC83_IN_SEL_V  0x3F
-#define GPIO_FUNC83_IN_SEL_S  0
-
-#define GPIO_FUNC84_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A4)
-/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG84_IN_SEL    (BIT(7))
-#define GPIO_SIG84_IN_SEL_M  (BIT(7))
-#define GPIO_SIG84_IN_SEL_V  0x1
-#define GPIO_SIG84_IN_SEL_S  7
-/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC84_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC84_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC84_IN_INV_SEL_V  0x1
-#define GPIO_FUNC84_IN_INV_SEL_S  6
-/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC84_IN_SEL    0x0000003F
-#define GPIO_FUNC84_IN_SEL_M  ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
-#define GPIO_FUNC84_IN_SEL_V  0x3F
-#define GPIO_FUNC84_IN_SEL_S  0
-
-#define GPIO_FUNC85_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A8)
-/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG85_IN_SEL    (BIT(7))
-#define GPIO_SIG85_IN_SEL_M  (BIT(7))
-#define GPIO_SIG85_IN_SEL_V  0x1
-#define GPIO_SIG85_IN_SEL_S  7
-/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC85_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC85_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC85_IN_INV_SEL_V  0x1
-#define GPIO_FUNC85_IN_INV_SEL_S  6
-/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC85_IN_SEL    0x0000003F
-#define GPIO_FUNC85_IN_SEL_M  ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
-#define GPIO_FUNC85_IN_SEL_V  0x3F
-#define GPIO_FUNC85_IN_SEL_S  0
-
-#define GPIO_FUNC86_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2AC)
-/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG86_IN_SEL    (BIT(7))
-#define GPIO_SIG86_IN_SEL_M  (BIT(7))
-#define GPIO_SIG86_IN_SEL_V  0x1
-#define GPIO_SIG86_IN_SEL_S  7
-/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC86_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC86_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC86_IN_INV_SEL_V  0x1
-#define GPIO_FUNC86_IN_INV_SEL_S  6
-/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC86_IN_SEL    0x0000003F
-#define GPIO_FUNC86_IN_SEL_M  ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
-#define GPIO_FUNC86_IN_SEL_V  0x3F
-#define GPIO_FUNC86_IN_SEL_S  0
-
-#define GPIO_FUNC87_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B0)
-/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG87_IN_SEL    (BIT(7))
-#define GPIO_SIG87_IN_SEL_M  (BIT(7))
-#define GPIO_SIG87_IN_SEL_V  0x1
-#define GPIO_SIG87_IN_SEL_S  7
-/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC87_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC87_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC87_IN_INV_SEL_V  0x1
-#define GPIO_FUNC87_IN_INV_SEL_S  6
-/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC87_IN_SEL    0x0000003F
-#define GPIO_FUNC87_IN_SEL_M  ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
-#define GPIO_FUNC87_IN_SEL_V  0x3F
-#define GPIO_FUNC87_IN_SEL_S  0
-
-#define GPIO_FUNC88_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B4)
-/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG88_IN_SEL    (BIT(7))
-#define GPIO_SIG88_IN_SEL_M  (BIT(7))
-#define GPIO_SIG88_IN_SEL_V  0x1
-#define GPIO_SIG88_IN_SEL_S  7
-/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC88_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC88_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC88_IN_INV_SEL_V  0x1
-#define GPIO_FUNC88_IN_INV_SEL_S  6
-/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC88_IN_SEL    0x0000003F
-#define GPIO_FUNC88_IN_SEL_M  ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
-#define GPIO_FUNC88_IN_SEL_V  0x3F
-#define GPIO_FUNC88_IN_SEL_S  0
-
-#define GPIO_FUNC89_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B8)
-/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG89_IN_SEL    (BIT(7))
-#define GPIO_SIG89_IN_SEL_M  (BIT(7))
-#define GPIO_SIG89_IN_SEL_V  0x1
-#define GPIO_SIG89_IN_SEL_S  7
-/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC89_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC89_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC89_IN_INV_SEL_V  0x1
-#define GPIO_FUNC89_IN_INV_SEL_S  6
-/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC89_IN_SEL    0x0000003F
-#define GPIO_FUNC89_IN_SEL_M  ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
-#define GPIO_FUNC89_IN_SEL_V  0x3F
-#define GPIO_FUNC89_IN_SEL_S  0
-
-#define GPIO_FUNC90_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2BC)
-/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG90_IN_SEL    (BIT(7))
-#define GPIO_SIG90_IN_SEL_M  (BIT(7))
-#define GPIO_SIG90_IN_SEL_V  0x1
-#define GPIO_SIG90_IN_SEL_S  7
-/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC90_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC90_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC90_IN_INV_SEL_V  0x1
-#define GPIO_FUNC90_IN_INV_SEL_S  6
-/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC90_IN_SEL    0x0000003F
-#define GPIO_FUNC90_IN_SEL_M  ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
-#define GPIO_FUNC90_IN_SEL_V  0x3F
-#define GPIO_FUNC90_IN_SEL_S  0
-
-#define GPIO_FUNC91_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C0)
-/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG91_IN_SEL    (BIT(7))
-#define GPIO_SIG91_IN_SEL_M  (BIT(7))
-#define GPIO_SIG91_IN_SEL_V  0x1
-#define GPIO_SIG91_IN_SEL_S  7
-/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC91_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC91_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC91_IN_INV_SEL_V  0x1
-#define GPIO_FUNC91_IN_INV_SEL_S  6
-/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC91_IN_SEL    0x0000003F
-#define GPIO_FUNC91_IN_SEL_M  ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
-#define GPIO_FUNC91_IN_SEL_V  0x3F
-#define GPIO_FUNC91_IN_SEL_S  0
-
-#define GPIO_FUNC92_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C4)
-/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG92_IN_SEL    (BIT(7))
-#define GPIO_SIG92_IN_SEL_M  (BIT(7))
-#define GPIO_SIG92_IN_SEL_V  0x1
-#define GPIO_SIG92_IN_SEL_S  7
-/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC92_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC92_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC92_IN_INV_SEL_V  0x1
-#define GPIO_FUNC92_IN_INV_SEL_S  6
-/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC92_IN_SEL    0x0000003F
-#define GPIO_FUNC92_IN_SEL_M  ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
-#define GPIO_FUNC92_IN_SEL_V  0x3F
-#define GPIO_FUNC92_IN_SEL_S  0
-
-#define GPIO_FUNC93_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C8)
-/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG93_IN_SEL    (BIT(7))
-#define GPIO_SIG93_IN_SEL_M  (BIT(7))
-#define GPIO_SIG93_IN_SEL_V  0x1
-#define GPIO_SIG93_IN_SEL_S  7
-/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC93_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC93_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC93_IN_INV_SEL_V  0x1
-#define GPIO_FUNC93_IN_INV_SEL_S  6
-/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC93_IN_SEL    0x0000003F
-#define GPIO_FUNC93_IN_SEL_M  ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
-#define GPIO_FUNC93_IN_SEL_V  0x3F
-#define GPIO_FUNC93_IN_SEL_S  0
-
-#define GPIO_FUNC94_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2CC)
-/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG94_IN_SEL    (BIT(7))
-#define GPIO_SIG94_IN_SEL_M  (BIT(7))
-#define GPIO_SIG94_IN_SEL_V  0x1
-#define GPIO_SIG94_IN_SEL_S  7
-/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC94_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC94_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC94_IN_INV_SEL_V  0x1
-#define GPIO_FUNC94_IN_INV_SEL_S  6
-/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC94_IN_SEL    0x0000003F
-#define GPIO_FUNC94_IN_SEL_M  ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
-#define GPIO_FUNC94_IN_SEL_V  0x3F
-#define GPIO_FUNC94_IN_SEL_S  0
-
-#define GPIO_FUNC95_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D0)
-/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG95_IN_SEL    (BIT(7))
-#define GPIO_SIG95_IN_SEL_M  (BIT(7))
-#define GPIO_SIG95_IN_SEL_V  0x1
-#define GPIO_SIG95_IN_SEL_S  7
-/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC95_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC95_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC95_IN_INV_SEL_V  0x1
-#define GPIO_FUNC95_IN_INV_SEL_S  6
-/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC95_IN_SEL    0x0000003F
-#define GPIO_FUNC95_IN_SEL_M  ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
-#define GPIO_FUNC95_IN_SEL_V  0x3F
-#define GPIO_FUNC95_IN_SEL_S  0
-
-#define GPIO_FUNC96_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D4)
-/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG96_IN_SEL    (BIT(7))
-#define GPIO_SIG96_IN_SEL_M  (BIT(7))
-#define GPIO_SIG96_IN_SEL_V  0x1
-#define GPIO_SIG96_IN_SEL_S  7
-/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC96_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC96_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC96_IN_INV_SEL_V  0x1
-#define GPIO_FUNC96_IN_INV_SEL_S  6
-/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC96_IN_SEL    0x0000003F
-#define GPIO_FUNC96_IN_SEL_M  ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
-#define GPIO_FUNC96_IN_SEL_V  0x3F
-#define GPIO_FUNC96_IN_SEL_S  0
-
-#define GPIO_FUNC97_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D8)
-/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG97_IN_SEL    (BIT(7))
-#define GPIO_SIG97_IN_SEL_M  (BIT(7))
-#define GPIO_SIG97_IN_SEL_V  0x1
-#define GPIO_SIG97_IN_SEL_S  7
-/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC97_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC97_IN_INV_SEL_V  0x1
-#define GPIO_FUNC97_IN_INV_SEL_S  6
-/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC97_IN_SEL    0x0000003F
-#define GPIO_FUNC97_IN_SEL_M  ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
-#define GPIO_FUNC97_IN_SEL_V  0x3F
-#define GPIO_FUNC97_IN_SEL_S  0
-
-#define GPIO_FUNC98_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2DC)
-/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG98_IN_SEL    (BIT(7))
-#define GPIO_SIG98_IN_SEL_M  (BIT(7))
-#define GPIO_SIG98_IN_SEL_V  0x1
-#define GPIO_SIG98_IN_SEL_S  7
-/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC98_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC98_IN_INV_SEL_V  0x1
-#define GPIO_FUNC98_IN_INV_SEL_S  6
-/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC98_IN_SEL    0x0000003F
-#define GPIO_FUNC98_IN_SEL_M  ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
-#define GPIO_FUNC98_IN_SEL_V  0x3F
-#define GPIO_FUNC98_IN_SEL_S  0
-
-#define GPIO_FUNC99_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E0)
-/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG99_IN_SEL    (BIT(7))
-#define GPIO_SIG99_IN_SEL_M  (BIT(7))
-#define GPIO_SIG99_IN_SEL_V  0x1
-#define GPIO_SIG99_IN_SEL_S  7
-/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC99_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC99_IN_INV_SEL_V  0x1
-#define GPIO_FUNC99_IN_INV_SEL_S  6
-/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC99_IN_SEL    0x0000003F
-#define GPIO_FUNC99_IN_SEL_M  ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
-#define GPIO_FUNC99_IN_SEL_V  0x3F
-#define GPIO_FUNC99_IN_SEL_S  0
-
-#define GPIO_FUNC100_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E4)
-/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG100_IN_SEL    (BIT(7))
-#define GPIO_SIG100_IN_SEL_M  (BIT(7))
-#define GPIO_SIG100_IN_SEL_V  0x1
-#define GPIO_SIG100_IN_SEL_S  7
-/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC100_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC100_IN_INV_SEL_V  0x1
-#define GPIO_FUNC100_IN_INV_SEL_S  6
-/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC100_IN_SEL    0x0000003F
-#define GPIO_FUNC100_IN_SEL_M  ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
-#define GPIO_FUNC100_IN_SEL_V  0x3F
-#define GPIO_FUNC100_IN_SEL_S  0
-
-#define GPIO_FUNC101_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E8)
-/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG101_IN_SEL    (BIT(7))
-#define GPIO_SIG101_IN_SEL_M  (BIT(7))
-#define GPIO_SIG101_IN_SEL_V  0x1
-#define GPIO_SIG101_IN_SEL_S  7
-/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC101_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC101_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC101_IN_INV_SEL_V  0x1
-#define GPIO_FUNC101_IN_INV_SEL_S  6
-/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC101_IN_SEL    0x0000003F
-#define GPIO_FUNC101_IN_SEL_M  ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
-#define GPIO_FUNC101_IN_SEL_V  0x3F
-#define GPIO_FUNC101_IN_SEL_S  0
-
-#define GPIO_FUNC102_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2EC)
-/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG102_IN_SEL    (BIT(7))
-#define GPIO_SIG102_IN_SEL_M  (BIT(7))
-#define GPIO_SIG102_IN_SEL_V  0x1
-#define GPIO_SIG102_IN_SEL_S  7
-/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC102_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC102_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC102_IN_INV_SEL_V  0x1
-#define GPIO_FUNC102_IN_INV_SEL_S  6
-/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC102_IN_SEL    0x0000003F
-#define GPIO_FUNC102_IN_SEL_M  ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
-#define GPIO_FUNC102_IN_SEL_V  0x3F
-#define GPIO_FUNC102_IN_SEL_S  0
-
-#define GPIO_FUNC103_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F0)
-/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG103_IN_SEL    (BIT(7))
-#define GPIO_SIG103_IN_SEL_M  (BIT(7))
-#define GPIO_SIG103_IN_SEL_V  0x1
-#define GPIO_SIG103_IN_SEL_S  7
-/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC103_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC103_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC103_IN_INV_SEL_V  0x1
-#define GPIO_FUNC103_IN_INV_SEL_S  6
-/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC103_IN_SEL    0x0000003F
-#define GPIO_FUNC103_IN_SEL_M  ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
-#define GPIO_FUNC103_IN_SEL_V  0x3F
-#define GPIO_FUNC103_IN_SEL_S  0
-
-#define GPIO_FUNC104_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F4)
-/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG104_IN_SEL    (BIT(7))
-#define GPIO_SIG104_IN_SEL_M  (BIT(7))
-#define GPIO_SIG104_IN_SEL_V  0x1
-#define GPIO_SIG104_IN_SEL_S  7
-/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC104_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC104_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC104_IN_INV_SEL_V  0x1
-#define GPIO_FUNC104_IN_INV_SEL_S  6
-/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC104_IN_SEL    0x0000003F
-#define GPIO_FUNC104_IN_SEL_M  ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
-#define GPIO_FUNC104_IN_SEL_V  0x3F
-#define GPIO_FUNC104_IN_SEL_S  0
-
-#define GPIO_FUNC105_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F8)
-/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG105_IN_SEL    (BIT(7))
-#define GPIO_SIG105_IN_SEL_M  (BIT(7))
-#define GPIO_SIG105_IN_SEL_V  0x1
-#define GPIO_SIG105_IN_SEL_S  7
-/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC105_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC105_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC105_IN_INV_SEL_V  0x1
-#define GPIO_FUNC105_IN_INV_SEL_S  6
-/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC105_IN_SEL    0x0000003F
-#define GPIO_FUNC105_IN_SEL_M  ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
-#define GPIO_FUNC105_IN_SEL_V  0x3F
-#define GPIO_FUNC105_IN_SEL_S  0
-
-#define GPIO_FUNC106_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2FC)
-/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG106_IN_SEL    (BIT(7))
-#define GPIO_SIG106_IN_SEL_M  (BIT(7))
-#define GPIO_SIG106_IN_SEL_V  0x1
-#define GPIO_SIG106_IN_SEL_S  7
-/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC106_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC106_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC106_IN_INV_SEL_V  0x1
-#define GPIO_FUNC106_IN_INV_SEL_S  6
-/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC106_IN_SEL    0x0000003F
-#define GPIO_FUNC106_IN_SEL_M  ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
-#define GPIO_FUNC106_IN_SEL_V  0x3F
-#define GPIO_FUNC106_IN_SEL_S  0
-
-#define GPIO_FUNC107_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x300)
-/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG107_IN_SEL    (BIT(7))
-#define GPIO_SIG107_IN_SEL_M  (BIT(7))
-#define GPIO_SIG107_IN_SEL_V  0x1
-#define GPIO_SIG107_IN_SEL_S  7
-/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC107_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC107_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC107_IN_INV_SEL_V  0x1
-#define GPIO_FUNC107_IN_INV_SEL_S  6
-/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC107_IN_SEL    0x0000003F
-#define GPIO_FUNC107_IN_SEL_M  ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
-#define GPIO_FUNC107_IN_SEL_V  0x3F
-#define GPIO_FUNC107_IN_SEL_S  0
-
-#define GPIO_FUNC108_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x304)
-/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG108_IN_SEL    (BIT(7))
-#define GPIO_SIG108_IN_SEL_M  (BIT(7))
-#define GPIO_SIG108_IN_SEL_V  0x1
-#define GPIO_SIG108_IN_SEL_S  7
-/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC108_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC108_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC108_IN_INV_SEL_V  0x1
-#define GPIO_FUNC108_IN_INV_SEL_S  6
-/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC108_IN_SEL    0x0000003F
-#define GPIO_FUNC108_IN_SEL_M  ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
-#define GPIO_FUNC108_IN_SEL_V  0x3F
-#define GPIO_FUNC108_IN_SEL_S  0
-
-#define GPIO_FUNC109_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x308)
-/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG109_IN_SEL    (BIT(7))
-#define GPIO_SIG109_IN_SEL_M  (BIT(7))
-#define GPIO_SIG109_IN_SEL_V  0x1
-#define GPIO_SIG109_IN_SEL_S  7
-/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC109_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC109_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC109_IN_INV_SEL_V  0x1
-#define GPIO_FUNC109_IN_INV_SEL_S  6
-/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC109_IN_SEL    0x0000003F
-#define GPIO_FUNC109_IN_SEL_M  ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
-#define GPIO_FUNC109_IN_SEL_V  0x3F
-#define GPIO_FUNC109_IN_SEL_S  0
-
-#define GPIO_FUNC110_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x30C)
-/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG110_IN_SEL    (BIT(7))
-#define GPIO_SIG110_IN_SEL_M  (BIT(7))
-#define GPIO_SIG110_IN_SEL_V  0x1
-#define GPIO_SIG110_IN_SEL_S  7
-/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC110_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC110_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC110_IN_INV_SEL_V  0x1
-#define GPIO_FUNC110_IN_INV_SEL_S  6
-/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC110_IN_SEL    0x0000003F
-#define GPIO_FUNC110_IN_SEL_M  ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
-#define GPIO_FUNC110_IN_SEL_V  0x3F
-#define GPIO_FUNC110_IN_SEL_S  0
-
-#define GPIO_FUNC111_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x310)
-/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG111_IN_SEL    (BIT(7))
-#define GPIO_SIG111_IN_SEL_M  (BIT(7))
-#define GPIO_SIG111_IN_SEL_V  0x1
-#define GPIO_SIG111_IN_SEL_S  7
-/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC111_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC111_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC111_IN_INV_SEL_V  0x1
-#define GPIO_FUNC111_IN_INV_SEL_S  6
-/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC111_IN_SEL    0x0000003F
-#define GPIO_FUNC111_IN_SEL_M  ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
-#define GPIO_FUNC111_IN_SEL_V  0x3F
-#define GPIO_FUNC111_IN_SEL_S  0
-
-#define GPIO_FUNC112_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x314)
-/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG112_IN_SEL    (BIT(7))
-#define GPIO_SIG112_IN_SEL_M  (BIT(7))
-#define GPIO_SIG112_IN_SEL_V  0x1
-#define GPIO_SIG112_IN_SEL_S  7
-/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC112_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC112_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC112_IN_INV_SEL_V  0x1
-#define GPIO_FUNC112_IN_INV_SEL_S  6
-/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC112_IN_SEL    0x0000003F
-#define GPIO_FUNC112_IN_SEL_M  ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
-#define GPIO_FUNC112_IN_SEL_V  0x3F
-#define GPIO_FUNC112_IN_SEL_S  0
-
-#define GPIO_FUNC113_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x318)
-/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG113_IN_SEL    (BIT(7))
-#define GPIO_SIG113_IN_SEL_M  (BIT(7))
-#define GPIO_SIG113_IN_SEL_V  0x1
-#define GPIO_SIG113_IN_SEL_S  7
-/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC113_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC113_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC113_IN_INV_SEL_V  0x1
-#define GPIO_FUNC113_IN_INV_SEL_S  6
-/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC113_IN_SEL    0x0000003F
-#define GPIO_FUNC113_IN_SEL_M  ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
-#define GPIO_FUNC113_IN_SEL_V  0x3F
-#define GPIO_FUNC113_IN_SEL_S  0
-
-#define GPIO_FUNC114_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x31C)
-/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG114_IN_SEL    (BIT(7))
-#define GPIO_SIG114_IN_SEL_M  (BIT(7))
-#define GPIO_SIG114_IN_SEL_V  0x1
-#define GPIO_SIG114_IN_SEL_S  7
-/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC114_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC114_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC114_IN_INV_SEL_V  0x1
-#define GPIO_FUNC114_IN_INV_SEL_S  6
-/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC114_IN_SEL    0x0000003F
-#define GPIO_FUNC114_IN_SEL_M  ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
-#define GPIO_FUNC114_IN_SEL_V  0x3F
-#define GPIO_FUNC114_IN_SEL_S  0
-
-#define GPIO_FUNC115_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x320)
-/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG115_IN_SEL    (BIT(7))
-#define GPIO_SIG115_IN_SEL_M  (BIT(7))
-#define GPIO_SIG115_IN_SEL_V  0x1
-#define GPIO_SIG115_IN_SEL_S  7
-/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC115_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC115_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC115_IN_INV_SEL_V  0x1
-#define GPIO_FUNC115_IN_INV_SEL_S  6
-/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC115_IN_SEL    0x0000003F
-#define GPIO_FUNC115_IN_SEL_M  ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
-#define GPIO_FUNC115_IN_SEL_V  0x3F
-#define GPIO_FUNC115_IN_SEL_S  0
-
-#define GPIO_FUNC116_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x324)
-/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG116_IN_SEL    (BIT(7))
-#define GPIO_SIG116_IN_SEL_M  (BIT(7))
-#define GPIO_SIG116_IN_SEL_V  0x1
-#define GPIO_SIG116_IN_SEL_S  7
-/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC116_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC116_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC116_IN_INV_SEL_V  0x1
-#define GPIO_FUNC116_IN_INV_SEL_S  6
-/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC116_IN_SEL    0x0000003F
-#define GPIO_FUNC116_IN_SEL_M  ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
-#define GPIO_FUNC116_IN_SEL_V  0x3F
-#define GPIO_FUNC116_IN_SEL_S  0
-
-#define GPIO_FUNC117_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x328)
-/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG117_IN_SEL    (BIT(7))
-#define GPIO_SIG117_IN_SEL_M  (BIT(7))
-#define GPIO_SIG117_IN_SEL_V  0x1
-#define GPIO_SIG117_IN_SEL_S  7
-/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC117_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC117_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC117_IN_INV_SEL_V  0x1
-#define GPIO_FUNC117_IN_INV_SEL_S  6
-/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC117_IN_SEL    0x0000003F
-#define GPIO_FUNC117_IN_SEL_M  ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
-#define GPIO_FUNC117_IN_SEL_V  0x3F
-#define GPIO_FUNC117_IN_SEL_S  0
-
-#define GPIO_FUNC118_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x32C)
-/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG118_IN_SEL    (BIT(7))
-#define GPIO_SIG118_IN_SEL_M  (BIT(7))
-#define GPIO_SIG118_IN_SEL_V  0x1
-#define GPIO_SIG118_IN_SEL_S  7
-/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC118_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC118_IN_INV_SEL_V  0x1
-#define GPIO_FUNC118_IN_INV_SEL_S  6
-/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC118_IN_SEL    0x0000003F
-#define GPIO_FUNC118_IN_SEL_M  ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
-#define GPIO_FUNC118_IN_SEL_V  0x3F
-#define GPIO_FUNC118_IN_SEL_S  0
-
-#define GPIO_FUNC119_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x330)
-/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG119_IN_SEL    (BIT(7))
-#define GPIO_SIG119_IN_SEL_M  (BIT(7))
-#define GPIO_SIG119_IN_SEL_V  0x1
-#define GPIO_SIG119_IN_SEL_S  7
-/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC119_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC119_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC119_IN_INV_SEL_V  0x1
-#define GPIO_FUNC119_IN_INV_SEL_S  6
-/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC119_IN_SEL    0x0000003F
-#define GPIO_FUNC119_IN_SEL_M  ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
-#define GPIO_FUNC119_IN_SEL_V  0x3F
-#define GPIO_FUNC119_IN_SEL_S  0
-
-#define GPIO_FUNC120_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x334)
-/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG120_IN_SEL    (BIT(7))
-#define GPIO_SIG120_IN_SEL_M  (BIT(7))
-#define GPIO_SIG120_IN_SEL_V  0x1
-#define GPIO_SIG120_IN_SEL_S  7
-/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC120_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC120_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC120_IN_INV_SEL_V  0x1
-#define GPIO_FUNC120_IN_INV_SEL_S  6
-/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC120_IN_SEL    0x0000003F
-#define GPIO_FUNC120_IN_SEL_M  ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
-#define GPIO_FUNC120_IN_SEL_V  0x3F
-#define GPIO_FUNC120_IN_SEL_S  0
-
-#define GPIO_FUNC121_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x338)
-/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG121_IN_SEL    (BIT(7))
-#define GPIO_SIG121_IN_SEL_M  (BIT(7))
-#define GPIO_SIG121_IN_SEL_V  0x1
-#define GPIO_SIG121_IN_SEL_S  7
-/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC121_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC121_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC121_IN_INV_SEL_V  0x1
-#define GPIO_FUNC121_IN_INV_SEL_S  6
-/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC121_IN_SEL    0x0000003F
-#define GPIO_FUNC121_IN_SEL_M  ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
-#define GPIO_FUNC121_IN_SEL_V  0x3F
-#define GPIO_FUNC121_IN_SEL_S  0
-
-#define GPIO_FUNC122_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x33C)
-/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG122_IN_SEL    (BIT(7))
-#define GPIO_SIG122_IN_SEL_M  (BIT(7))
-#define GPIO_SIG122_IN_SEL_V  0x1
-#define GPIO_SIG122_IN_SEL_S  7
-/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC122_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC122_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC122_IN_INV_SEL_V  0x1
-#define GPIO_FUNC122_IN_INV_SEL_S  6
-/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC122_IN_SEL    0x0000003F
-#define GPIO_FUNC122_IN_SEL_M  ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
-#define GPIO_FUNC122_IN_SEL_V  0x3F
-#define GPIO_FUNC122_IN_SEL_S  0
-
-#define GPIO_FUNC123_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x340)
-/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG123_IN_SEL    (BIT(7))
-#define GPIO_SIG123_IN_SEL_M  (BIT(7))
-#define GPIO_SIG123_IN_SEL_V  0x1
-#define GPIO_SIG123_IN_SEL_S  7
-/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC123_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC123_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC123_IN_INV_SEL_V  0x1
-#define GPIO_FUNC123_IN_INV_SEL_S  6
-/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC123_IN_SEL    0x0000003F
-#define GPIO_FUNC123_IN_SEL_M  ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
-#define GPIO_FUNC123_IN_SEL_V  0x3F
-#define GPIO_FUNC123_IN_SEL_S  0
-
-#define GPIO_FUNC124_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x344)
-/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG124_IN_SEL    (BIT(7))
-#define GPIO_SIG124_IN_SEL_M  (BIT(7))
-#define GPIO_SIG124_IN_SEL_V  0x1
-#define GPIO_SIG124_IN_SEL_S  7
-/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC124_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC124_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC124_IN_INV_SEL_V  0x1
-#define GPIO_FUNC124_IN_INV_SEL_S  6
-/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC124_IN_SEL    0x0000003F
-#define GPIO_FUNC124_IN_SEL_M  ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
-#define GPIO_FUNC124_IN_SEL_V  0x3F
-#define GPIO_FUNC124_IN_SEL_S  0
-
-#define GPIO_FUNC125_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x348)
-/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG125_IN_SEL    (BIT(7))
-#define GPIO_SIG125_IN_SEL_M  (BIT(7))
-#define GPIO_SIG125_IN_SEL_V  0x1
-#define GPIO_SIG125_IN_SEL_S  7
-/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC125_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC125_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC125_IN_INV_SEL_V  0x1
-#define GPIO_FUNC125_IN_INV_SEL_S  6
-/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC125_IN_SEL    0x0000003F
-#define GPIO_FUNC125_IN_SEL_M  ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
-#define GPIO_FUNC125_IN_SEL_V  0x3F
-#define GPIO_FUNC125_IN_SEL_S  0
-
-#define GPIO_FUNC126_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x34C)
-/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG126_IN_SEL    (BIT(7))
-#define GPIO_SIG126_IN_SEL_M  (BIT(7))
-#define GPIO_SIG126_IN_SEL_V  0x1
-#define GPIO_SIG126_IN_SEL_S  7
-/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC126_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC126_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC126_IN_INV_SEL_V  0x1
-#define GPIO_FUNC126_IN_INV_SEL_S  6
-/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC126_IN_SEL    0x0000003F
-#define GPIO_FUNC126_IN_SEL_M  ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
-#define GPIO_FUNC126_IN_SEL_V  0x3F
-#define GPIO_FUNC126_IN_SEL_S  0
-
-#define GPIO_FUNC127_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x350)
-/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG127_IN_SEL    (BIT(7))
-#define GPIO_SIG127_IN_SEL_M  (BIT(7))
-#define GPIO_SIG127_IN_SEL_V  0x1
-#define GPIO_SIG127_IN_SEL_S  7
-/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC127_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC127_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC127_IN_INV_SEL_V  0x1
-#define GPIO_FUNC127_IN_INV_SEL_S  6
-/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC127_IN_SEL    0x0000003F
-#define GPIO_FUNC127_IN_SEL_M  ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
-#define GPIO_FUNC127_IN_SEL_V  0x3F
-#define GPIO_FUNC127_IN_SEL_S  0
-
-#define GPIO_FUNC128_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x354)
-/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG128_IN_SEL    (BIT(7))
-#define GPIO_SIG128_IN_SEL_M  (BIT(7))
-#define GPIO_SIG128_IN_SEL_V  0x1
-#define GPIO_SIG128_IN_SEL_S  7
-/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC128_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC128_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC128_IN_INV_SEL_V  0x1
-#define GPIO_FUNC128_IN_INV_SEL_S  6
-/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC128_IN_SEL    0x0000003F
-#define GPIO_FUNC128_IN_SEL_M  ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S))
-#define GPIO_FUNC128_IN_SEL_V  0x3F
-#define GPIO_FUNC128_IN_SEL_S  0
-
-#define GPIO_FUNC129_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x358)
-/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG129_IN_SEL    (BIT(7))
-#define GPIO_SIG129_IN_SEL_M  (BIT(7))
-#define GPIO_SIG129_IN_SEL_V  0x1
-#define GPIO_SIG129_IN_SEL_S  7
-/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC129_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC129_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC129_IN_INV_SEL_V  0x1
-#define GPIO_FUNC129_IN_INV_SEL_S  6
-/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC129_IN_SEL    0x0000003F
-#define GPIO_FUNC129_IN_SEL_M  ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S))
-#define GPIO_FUNC129_IN_SEL_V  0x3F
-#define GPIO_FUNC129_IN_SEL_S  0
-
-#define GPIO_FUNC130_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x35C)
-/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG130_IN_SEL    (BIT(7))
-#define GPIO_SIG130_IN_SEL_M  (BIT(7))
-#define GPIO_SIG130_IN_SEL_V  0x1
-#define GPIO_SIG130_IN_SEL_S  7
-/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC130_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC130_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC130_IN_INV_SEL_V  0x1
-#define GPIO_FUNC130_IN_INV_SEL_S  6
-/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC130_IN_SEL    0x0000003F
-#define GPIO_FUNC130_IN_SEL_M  ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S))
-#define GPIO_FUNC130_IN_SEL_V  0x3F
-#define GPIO_FUNC130_IN_SEL_S  0
-
-#define GPIO_FUNC131_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x360)
-/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG131_IN_SEL    (BIT(7))
-#define GPIO_SIG131_IN_SEL_M  (BIT(7))
-#define GPIO_SIG131_IN_SEL_V  0x1
-#define GPIO_SIG131_IN_SEL_S  7
-/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC131_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC131_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC131_IN_INV_SEL_V  0x1
-#define GPIO_FUNC131_IN_INV_SEL_S  6
-/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC131_IN_SEL    0x0000003F
-#define GPIO_FUNC131_IN_SEL_M  ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S))
-#define GPIO_FUNC131_IN_SEL_V  0x3F
-#define GPIO_FUNC131_IN_SEL_S  0
-
-#define GPIO_FUNC132_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x364)
-/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG132_IN_SEL    (BIT(7))
-#define GPIO_SIG132_IN_SEL_M  (BIT(7))
-#define GPIO_SIG132_IN_SEL_V  0x1
-#define GPIO_SIG132_IN_SEL_S  7
-/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC132_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC132_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC132_IN_INV_SEL_V  0x1
-#define GPIO_FUNC132_IN_INV_SEL_S  6
-/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC132_IN_SEL    0x0000003F
-#define GPIO_FUNC132_IN_SEL_M  ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S))
-#define GPIO_FUNC132_IN_SEL_V  0x3F
-#define GPIO_FUNC132_IN_SEL_S  0
-
-#define GPIO_FUNC133_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x368)
-/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG133_IN_SEL    (BIT(7))
-#define GPIO_SIG133_IN_SEL_M  (BIT(7))
-#define GPIO_SIG133_IN_SEL_V  0x1
-#define GPIO_SIG133_IN_SEL_S  7
-/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC133_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC133_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC133_IN_INV_SEL_V  0x1
-#define GPIO_FUNC133_IN_INV_SEL_S  6
-/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC133_IN_SEL    0x0000003F
-#define GPIO_FUNC133_IN_SEL_M  ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S))
-#define GPIO_FUNC133_IN_SEL_V  0x3F
-#define GPIO_FUNC133_IN_SEL_S  0
-
-#define GPIO_FUNC134_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x36C)
-/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG134_IN_SEL    (BIT(7))
-#define GPIO_SIG134_IN_SEL_M  (BIT(7))
-#define GPIO_SIG134_IN_SEL_V  0x1
-#define GPIO_SIG134_IN_SEL_S  7
-/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC134_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC134_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC134_IN_INV_SEL_V  0x1
-#define GPIO_FUNC134_IN_INV_SEL_S  6
-/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC134_IN_SEL    0x0000003F
-#define GPIO_FUNC134_IN_SEL_M  ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S))
-#define GPIO_FUNC134_IN_SEL_V  0x3F
-#define GPIO_FUNC134_IN_SEL_S  0
-
-#define GPIO_FUNC135_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x370)
-/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG135_IN_SEL    (BIT(7))
-#define GPIO_SIG135_IN_SEL_M  (BIT(7))
-#define GPIO_SIG135_IN_SEL_V  0x1
-#define GPIO_SIG135_IN_SEL_S  7
-/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC135_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC135_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC135_IN_INV_SEL_V  0x1
-#define GPIO_FUNC135_IN_INV_SEL_S  6
-/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC135_IN_SEL    0x0000003F
-#define GPIO_FUNC135_IN_SEL_M  ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S))
-#define GPIO_FUNC135_IN_SEL_V  0x3F
-#define GPIO_FUNC135_IN_SEL_S  0
-
-#define GPIO_FUNC136_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x374)
-/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG136_IN_SEL    (BIT(7))
-#define GPIO_SIG136_IN_SEL_M  (BIT(7))
-#define GPIO_SIG136_IN_SEL_V  0x1
-#define GPIO_SIG136_IN_SEL_S  7
-/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC136_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC136_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC136_IN_INV_SEL_V  0x1
-#define GPIO_FUNC136_IN_INV_SEL_S  6
-/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC136_IN_SEL    0x0000003F
-#define GPIO_FUNC136_IN_SEL_M  ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S))
-#define GPIO_FUNC136_IN_SEL_V  0x3F
-#define GPIO_FUNC136_IN_SEL_S  0
-
-#define GPIO_FUNC137_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x378)
-/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG137_IN_SEL    (BIT(7))
-#define GPIO_SIG137_IN_SEL_M  (BIT(7))
-#define GPIO_SIG137_IN_SEL_V  0x1
-#define GPIO_SIG137_IN_SEL_S  7
-/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC137_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC137_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC137_IN_INV_SEL_V  0x1
-#define GPIO_FUNC137_IN_INV_SEL_S  6
-/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC137_IN_SEL    0x0000003F
-#define GPIO_FUNC137_IN_SEL_M  ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S))
-#define GPIO_FUNC137_IN_SEL_V  0x3F
-#define GPIO_FUNC137_IN_SEL_S  0
-
-#define GPIO_FUNC138_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x37C)
-/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG138_IN_SEL    (BIT(7))
-#define GPIO_SIG138_IN_SEL_M  (BIT(7))
-#define GPIO_SIG138_IN_SEL_V  0x1
-#define GPIO_SIG138_IN_SEL_S  7
-/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC138_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC138_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC138_IN_INV_SEL_V  0x1
-#define GPIO_FUNC138_IN_INV_SEL_S  6
-/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC138_IN_SEL    0x0000003F
-#define GPIO_FUNC138_IN_SEL_M  ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S))
-#define GPIO_FUNC138_IN_SEL_V  0x3F
-#define GPIO_FUNC138_IN_SEL_S  0
-
-#define GPIO_FUNC139_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x380)
-/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG139_IN_SEL    (BIT(7))
-#define GPIO_SIG139_IN_SEL_M  (BIT(7))
-#define GPIO_SIG139_IN_SEL_V  0x1
-#define GPIO_SIG139_IN_SEL_S  7
-/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC139_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC139_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC139_IN_INV_SEL_V  0x1
-#define GPIO_FUNC139_IN_INV_SEL_S  6
-/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC139_IN_SEL    0x0000003F
-#define GPIO_FUNC139_IN_SEL_M  ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S))
-#define GPIO_FUNC139_IN_SEL_V  0x3F
-#define GPIO_FUNC139_IN_SEL_S  0
-
-#define GPIO_FUNC140_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x384)
-/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG140_IN_SEL    (BIT(7))
-#define GPIO_SIG140_IN_SEL_M  (BIT(7))
-#define GPIO_SIG140_IN_SEL_V  0x1
-#define GPIO_SIG140_IN_SEL_S  7
-/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC140_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC140_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC140_IN_INV_SEL_V  0x1
-#define GPIO_FUNC140_IN_INV_SEL_S  6
-/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC140_IN_SEL    0x0000003F
-#define GPIO_FUNC140_IN_SEL_M  ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S))
-#define GPIO_FUNC140_IN_SEL_V  0x3F
-#define GPIO_FUNC140_IN_SEL_S  0
-
-#define GPIO_FUNC141_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x388)
-/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG141_IN_SEL    (BIT(7))
-#define GPIO_SIG141_IN_SEL_M  (BIT(7))
-#define GPIO_SIG141_IN_SEL_V  0x1
-#define GPIO_SIG141_IN_SEL_S  7
-/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC141_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC141_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC141_IN_INV_SEL_V  0x1
-#define GPIO_FUNC141_IN_INV_SEL_S  6
-/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC141_IN_SEL    0x0000003F
-#define GPIO_FUNC141_IN_SEL_M  ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S))
-#define GPIO_FUNC141_IN_SEL_V  0x3F
-#define GPIO_FUNC141_IN_SEL_S  0
-
-#define GPIO_FUNC142_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x38C)
-/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG142_IN_SEL    (BIT(7))
-#define GPIO_SIG142_IN_SEL_M  (BIT(7))
-#define GPIO_SIG142_IN_SEL_V  0x1
-#define GPIO_SIG142_IN_SEL_S  7
-/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC142_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC142_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC142_IN_INV_SEL_V  0x1
-#define GPIO_FUNC142_IN_INV_SEL_S  6
-/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC142_IN_SEL    0x0000003F
-#define GPIO_FUNC142_IN_SEL_M  ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S))
-#define GPIO_FUNC142_IN_SEL_V  0x3F
-#define GPIO_FUNC142_IN_SEL_S  0
-
-#define GPIO_FUNC143_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x390)
-/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG143_IN_SEL    (BIT(7))
-#define GPIO_SIG143_IN_SEL_M  (BIT(7))
-#define GPIO_SIG143_IN_SEL_V  0x1
-#define GPIO_SIG143_IN_SEL_S  7
-/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC143_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC143_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC143_IN_INV_SEL_V  0x1
-#define GPIO_FUNC143_IN_INV_SEL_S  6
-/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC143_IN_SEL    0x0000003F
-#define GPIO_FUNC143_IN_SEL_M  ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S))
-#define GPIO_FUNC143_IN_SEL_V  0x3F
-#define GPIO_FUNC143_IN_SEL_S  0
-
-#define GPIO_FUNC144_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x394)
-/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG144_IN_SEL    (BIT(7))
-#define GPIO_SIG144_IN_SEL_M  (BIT(7))
-#define GPIO_SIG144_IN_SEL_V  0x1
-#define GPIO_SIG144_IN_SEL_S  7
-/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC144_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC144_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC144_IN_INV_SEL_V  0x1
-#define GPIO_FUNC144_IN_INV_SEL_S  6
-/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC144_IN_SEL    0x0000003F
-#define GPIO_FUNC144_IN_SEL_M  ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S))
-#define GPIO_FUNC144_IN_SEL_V  0x3F
-#define GPIO_FUNC144_IN_SEL_S  0
-
-#define GPIO_FUNC145_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x398)
-/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG145_IN_SEL    (BIT(7))
-#define GPIO_SIG145_IN_SEL_M  (BIT(7))
-#define GPIO_SIG145_IN_SEL_V  0x1
-#define GPIO_SIG145_IN_SEL_S  7
-/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC145_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC145_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC145_IN_INV_SEL_V  0x1
-#define GPIO_FUNC145_IN_INV_SEL_S  6
-/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC145_IN_SEL    0x0000003F
-#define GPIO_FUNC145_IN_SEL_M  ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S))
-#define GPIO_FUNC145_IN_SEL_V  0x3F
-#define GPIO_FUNC145_IN_SEL_S  0
-
-#define GPIO_FUNC146_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x39C)
-/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG146_IN_SEL    (BIT(7))
-#define GPIO_SIG146_IN_SEL_M  (BIT(7))
-#define GPIO_SIG146_IN_SEL_V  0x1
-#define GPIO_SIG146_IN_SEL_S  7
-/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC146_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC146_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC146_IN_INV_SEL_V  0x1
-#define GPIO_FUNC146_IN_INV_SEL_S  6
-/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC146_IN_SEL    0x0000003F
-#define GPIO_FUNC146_IN_SEL_M  ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S))
-#define GPIO_FUNC146_IN_SEL_V  0x3F
-#define GPIO_FUNC146_IN_SEL_S  0
-
-#define GPIO_FUNC147_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A0)
-/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG147_IN_SEL    (BIT(7))
-#define GPIO_SIG147_IN_SEL_M  (BIT(7))
-#define GPIO_SIG147_IN_SEL_V  0x1
-#define GPIO_SIG147_IN_SEL_S  7
-/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC147_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC147_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC147_IN_INV_SEL_V  0x1
-#define GPIO_FUNC147_IN_INV_SEL_S  6
-/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC147_IN_SEL    0x0000003F
-#define GPIO_FUNC147_IN_SEL_M  ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S))
-#define GPIO_FUNC147_IN_SEL_V  0x3F
-#define GPIO_FUNC147_IN_SEL_S  0
-
-#define GPIO_FUNC148_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A4)
-/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG148_IN_SEL    (BIT(7))
-#define GPIO_SIG148_IN_SEL_M  (BIT(7))
-#define GPIO_SIG148_IN_SEL_V  0x1
-#define GPIO_SIG148_IN_SEL_S  7
-/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC148_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC148_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC148_IN_INV_SEL_V  0x1
-#define GPIO_FUNC148_IN_INV_SEL_S  6
-/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC148_IN_SEL    0x0000003F
-#define GPIO_FUNC148_IN_SEL_M  ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S))
-#define GPIO_FUNC148_IN_SEL_V  0x3F
-#define GPIO_FUNC148_IN_SEL_S  0
-
-#define GPIO_FUNC149_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A8)
-/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG149_IN_SEL    (BIT(7))
-#define GPIO_SIG149_IN_SEL_M  (BIT(7))
-#define GPIO_SIG149_IN_SEL_V  0x1
-#define GPIO_SIG149_IN_SEL_S  7
-/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC149_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC149_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC149_IN_INV_SEL_V  0x1
-#define GPIO_FUNC149_IN_INV_SEL_S  6
-/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC149_IN_SEL    0x0000003F
-#define GPIO_FUNC149_IN_SEL_M  ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S))
-#define GPIO_FUNC149_IN_SEL_V  0x3F
-#define GPIO_FUNC149_IN_SEL_S  0
-
-#define GPIO_FUNC150_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3AC)
-/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG150_IN_SEL    (BIT(7))
-#define GPIO_SIG150_IN_SEL_M  (BIT(7))
-#define GPIO_SIG150_IN_SEL_V  0x1
-#define GPIO_SIG150_IN_SEL_S  7
-/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC150_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC150_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC150_IN_INV_SEL_V  0x1
-#define GPIO_FUNC150_IN_INV_SEL_S  6
-/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC150_IN_SEL    0x0000003F
-#define GPIO_FUNC150_IN_SEL_M  ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S))
-#define GPIO_FUNC150_IN_SEL_V  0x3F
-#define GPIO_FUNC150_IN_SEL_S  0
-
-#define GPIO_FUNC151_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B0)
-/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG151_IN_SEL    (BIT(7))
-#define GPIO_SIG151_IN_SEL_M  (BIT(7))
-#define GPIO_SIG151_IN_SEL_V  0x1
-#define GPIO_SIG151_IN_SEL_S  7
-/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC151_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC151_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC151_IN_INV_SEL_V  0x1
-#define GPIO_FUNC151_IN_INV_SEL_S  6
-/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC151_IN_SEL    0x0000003F
-#define GPIO_FUNC151_IN_SEL_M  ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S))
-#define GPIO_FUNC151_IN_SEL_V  0x3F
-#define GPIO_FUNC151_IN_SEL_S  0
-
-#define GPIO_FUNC152_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B4)
-/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG152_IN_SEL    (BIT(7))
-#define GPIO_SIG152_IN_SEL_M  (BIT(7))
-#define GPIO_SIG152_IN_SEL_V  0x1
-#define GPIO_SIG152_IN_SEL_S  7
-/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC152_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC152_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC152_IN_INV_SEL_V  0x1
-#define GPIO_FUNC152_IN_INV_SEL_S  6
-/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC152_IN_SEL    0x0000003F
-#define GPIO_FUNC152_IN_SEL_M  ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S))
-#define GPIO_FUNC152_IN_SEL_V  0x3F
-#define GPIO_FUNC152_IN_SEL_S  0
-
-#define GPIO_FUNC153_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B8)
-/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG153_IN_SEL    (BIT(7))
-#define GPIO_SIG153_IN_SEL_M  (BIT(7))
-#define GPIO_SIG153_IN_SEL_V  0x1
-#define GPIO_SIG153_IN_SEL_S  7
-/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC153_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC153_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC153_IN_INV_SEL_V  0x1
-#define GPIO_FUNC153_IN_INV_SEL_S  6
-/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC153_IN_SEL    0x0000003F
-#define GPIO_FUNC153_IN_SEL_M  ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S))
-#define GPIO_FUNC153_IN_SEL_V  0x3F
-#define GPIO_FUNC153_IN_SEL_S  0
-
-#define GPIO_FUNC154_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3BC)
-/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG154_IN_SEL    (BIT(7))
-#define GPIO_SIG154_IN_SEL_M  (BIT(7))
-#define GPIO_SIG154_IN_SEL_V  0x1
-#define GPIO_SIG154_IN_SEL_S  7
-/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC154_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC154_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC154_IN_INV_SEL_V  0x1
-#define GPIO_FUNC154_IN_INV_SEL_S  6
-/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC154_IN_SEL    0x0000003F
-#define GPIO_FUNC154_IN_SEL_M  ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S))
-#define GPIO_FUNC154_IN_SEL_V  0x3F
-#define GPIO_FUNC154_IN_SEL_S  0
-
-#define GPIO_FUNC155_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C0)
-/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG155_IN_SEL    (BIT(7))
-#define GPIO_SIG155_IN_SEL_M  (BIT(7))
-#define GPIO_SIG155_IN_SEL_V  0x1
-#define GPIO_SIG155_IN_SEL_S  7
-/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC155_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC155_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC155_IN_INV_SEL_V  0x1
-#define GPIO_FUNC155_IN_INV_SEL_S  6
-/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC155_IN_SEL    0x0000003F
-#define GPIO_FUNC155_IN_SEL_M  ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S))
-#define GPIO_FUNC155_IN_SEL_V  0x3F
-#define GPIO_FUNC155_IN_SEL_S  0
-
-#define GPIO_FUNC156_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C4)
-/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG156_IN_SEL    (BIT(7))
-#define GPIO_SIG156_IN_SEL_M  (BIT(7))
-#define GPIO_SIG156_IN_SEL_V  0x1
-#define GPIO_SIG156_IN_SEL_S  7
-/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC156_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC156_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC156_IN_INV_SEL_V  0x1
-#define GPIO_FUNC156_IN_INV_SEL_S  6
-/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC156_IN_SEL    0x0000003F
-#define GPIO_FUNC156_IN_SEL_M  ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S))
-#define GPIO_FUNC156_IN_SEL_V  0x3F
-#define GPIO_FUNC156_IN_SEL_S  0
-
-#define GPIO_FUNC157_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C8)
-/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG157_IN_SEL    (BIT(7))
-#define GPIO_SIG157_IN_SEL_M  (BIT(7))
-#define GPIO_SIG157_IN_SEL_V  0x1
-#define GPIO_SIG157_IN_SEL_S  7
-/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC157_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC157_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC157_IN_INV_SEL_V  0x1
-#define GPIO_FUNC157_IN_INV_SEL_S  6
-/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC157_IN_SEL    0x0000003F
-#define GPIO_FUNC157_IN_SEL_M  ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S))
-#define GPIO_FUNC157_IN_SEL_V  0x3F
-#define GPIO_FUNC157_IN_SEL_S  0
-
-#define GPIO_FUNC158_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3CC)
-/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG158_IN_SEL    (BIT(7))
-#define GPIO_SIG158_IN_SEL_M  (BIT(7))
-#define GPIO_SIG158_IN_SEL_V  0x1
-#define GPIO_SIG158_IN_SEL_S  7
-/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC158_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC158_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC158_IN_INV_SEL_V  0x1
-#define GPIO_FUNC158_IN_INV_SEL_S  6
-/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC158_IN_SEL    0x0000003F
-#define GPIO_FUNC158_IN_SEL_M  ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S))
-#define GPIO_FUNC158_IN_SEL_V  0x3F
-#define GPIO_FUNC158_IN_SEL_S  0
-
-#define GPIO_FUNC159_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D0)
-/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG159_IN_SEL    (BIT(7))
-#define GPIO_SIG159_IN_SEL_M  (BIT(7))
-#define GPIO_SIG159_IN_SEL_V  0x1
-#define GPIO_SIG159_IN_SEL_S  7
-/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC159_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC159_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC159_IN_INV_SEL_V  0x1
-#define GPIO_FUNC159_IN_INV_SEL_S  6
-/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC159_IN_SEL    0x0000003F
-#define GPIO_FUNC159_IN_SEL_M  ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S))
-#define GPIO_FUNC159_IN_SEL_V  0x3F
-#define GPIO_FUNC159_IN_SEL_S  0
-
-#define GPIO_FUNC160_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D4)
-/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG160_IN_SEL    (BIT(7))
-#define GPIO_SIG160_IN_SEL_M  (BIT(7))
-#define GPIO_SIG160_IN_SEL_V  0x1
-#define GPIO_SIG160_IN_SEL_S  7
-/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC160_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC160_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC160_IN_INV_SEL_V  0x1
-#define GPIO_FUNC160_IN_INV_SEL_S  6
-/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC160_IN_SEL    0x0000003F
-#define GPIO_FUNC160_IN_SEL_M  ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S))
-#define GPIO_FUNC160_IN_SEL_V  0x3F
-#define GPIO_FUNC160_IN_SEL_S  0
-
-#define GPIO_FUNC161_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D8)
-/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG161_IN_SEL    (BIT(7))
-#define GPIO_SIG161_IN_SEL_M  (BIT(7))
-#define GPIO_SIG161_IN_SEL_V  0x1
-#define GPIO_SIG161_IN_SEL_S  7
-/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC161_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC161_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC161_IN_INV_SEL_V  0x1
-#define GPIO_FUNC161_IN_INV_SEL_S  6
-/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC161_IN_SEL    0x0000003F
-#define GPIO_FUNC161_IN_SEL_M  ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S))
-#define GPIO_FUNC161_IN_SEL_V  0x3F
-#define GPIO_FUNC161_IN_SEL_S  0
-
-#define GPIO_FUNC162_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3DC)
-/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG162_IN_SEL    (BIT(7))
-#define GPIO_SIG162_IN_SEL_M  (BIT(7))
-#define GPIO_SIG162_IN_SEL_V  0x1
-#define GPIO_SIG162_IN_SEL_S  7
-/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC162_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC162_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC162_IN_INV_SEL_V  0x1
-#define GPIO_FUNC162_IN_INV_SEL_S  6
-/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC162_IN_SEL    0x0000003F
-#define GPIO_FUNC162_IN_SEL_M  ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S))
-#define GPIO_FUNC162_IN_SEL_V  0x3F
-#define GPIO_FUNC162_IN_SEL_S  0
-
-#define GPIO_FUNC163_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E0)
-/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG163_IN_SEL    (BIT(7))
-#define GPIO_SIG163_IN_SEL_M  (BIT(7))
-#define GPIO_SIG163_IN_SEL_V  0x1
-#define GPIO_SIG163_IN_SEL_S  7
-/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC163_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC163_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC163_IN_INV_SEL_V  0x1
-#define GPIO_FUNC163_IN_INV_SEL_S  6
-/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC163_IN_SEL    0x0000003F
-#define GPIO_FUNC163_IN_SEL_M  ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S))
-#define GPIO_FUNC163_IN_SEL_V  0x3F
-#define GPIO_FUNC163_IN_SEL_S  0
-
-#define GPIO_FUNC164_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E4)
-/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG164_IN_SEL    (BIT(7))
-#define GPIO_SIG164_IN_SEL_M  (BIT(7))
-#define GPIO_SIG164_IN_SEL_V  0x1
-#define GPIO_SIG164_IN_SEL_S  7
-/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC164_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC164_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC164_IN_INV_SEL_V  0x1
-#define GPIO_FUNC164_IN_INV_SEL_S  6
-/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC164_IN_SEL    0x0000003F
-#define GPIO_FUNC164_IN_SEL_M  ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S))
-#define GPIO_FUNC164_IN_SEL_V  0x3F
-#define GPIO_FUNC164_IN_SEL_S  0
-
-#define GPIO_FUNC165_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E8)
-/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG165_IN_SEL    (BIT(7))
-#define GPIO_SIG165_IN_SEL_M  (BIT(7))
-#define GPIO_SIG165_IN_SEL_V  0x1
-#define GPIO_SIG165_IN_SEL_S  7
-/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC165_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC165_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC165_IN_INV_SEL_V  0x1
-#define GPIO_FUNC165_IN_INV_SEL_S  6
-/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC165_IN_SEL    0x0000003F
-#define GPIO_FUNC165_IN_SEL_M  ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S))
-#define GPIO_FUNC165_IN_SEL_V  0x3F
-#define GPIO_FUNC165_IN_SEL_S  0
-
-#define GPIO_FUNC166_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3EC)
-/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG166_IN_SEL    (BIT(7))
-#define GPIO_SIG166_IN_SEL_M  (BIT(7))
-#define GPIO_SIG166_IN_SEL_V  0x1
-#define GPIO_SIG166_IN_SEL_S  7
-/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC166_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC166_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC166_IN_INV_SEL_V  0x1
-#define GPIO_FUNC166_IN_INV_SEL_S  6
-/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC166_IN_SEL    0x0000003F
-#define GPIO_FUNC166_IN_SEL_M  ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S))
-#define GPIO_FUNC166_IN_SEL_V  0x3F
-#define GPIO_FUNC166_IN_SEL_S  0
-
-#define GPIO_FUNC167_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F0)
-/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG167_IN_SEL    (BIT(7))
-#define GPIO_SIG167_IN_SEL_M  (BIT(7))
-#define GPIO_SIG167_IN_SEL_V  0x1
-#define GPIO_SIG167_IN_SEL_S  7
-/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC167_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC167_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC167_IN_INV_SEL_V  0x1
-#define GPIO_FUNC167_IN_INV_SEL_S  6
-/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC167_IN_SEL    0x0000003F
-#define GPIO_FUNC167_IN_SEL_M  ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S))
-#define GPIO_FUNC167_IN_SEL_V  0x3F
-#define GPIO_FUNC167_IN_SEL_S  0
-
-#define GPIO_FUNC168_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F4)
-/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG168_IN_SEL    (BIT(7))
-#define GPIO_SIG168_IN_SEL_M  (BIT(7))
-#define GPIO_SIG168_IN_SEL_V  0x1
-#define GPIO_SIG168_IN_SEL_S  7
-/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC168_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC168_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC168_IN_INV_SEL_V  0x1
-#define GPIO_FUNC168_IN_INV_SEL_S  6
-/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC168_IN_SEL    0x0000003F
-#define GPIO_FUNC168_IN_SEL_M  ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S))
-#define GPIO_FUNC168_IN_SEL_V  0x3F
-#define GPIO_FUNC168_IN_SEL_S  0
-
-#define GPIO_FUNC169_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F8)
-/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG169_IN_SEL    (BIT(7))
-#define GPIO_SIG169_IN_SEL_M  (BIT(7))
-#define GPIO_SIG169_IN_SEL_V  0x1
-#define GPIO_SIG169_IN_SEL_S  7
-/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC169_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC169_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC169_IN_INV_SEL_V  0x1
-#define GPIO_FUNC169_IN_INV_SEL_S  6
-/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC169_IN_SEL    0x0000003F
-#define GPIO_FUNC169_IN_SEL_M  ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S))
-#define GPIO_FUNC169_IN_SEL_V  0x3F
-#define GPIO_FUNC169_IN_SEL_S  0
-
-#define GPIO_FUNC170_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3FC)
-/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG170_IN_SEL    (BIT(7))
-#define GPIO_SIG170_IN_SEL_M  (BIT(7))
-#define GPIO_SIG170_IN_SEL_V  0x1
-#define GPIO_SIG170_IN_SEL_S  7
-/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC170_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC170_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC170_IN_INV_SEL_V  0x1
-#define GPIO_FUNC170_IN_INV_SEL_S  6
-/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC170_IN_SEL    0x0000003F
-#define GPIO_FUNC170_IN_SEL_M  ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S))
-#define GPIO_FUNC170_IN_SEL_V  0x3F
-#define GPIO_FUNC170_IN_SEL_S  0
-
-#define GPIO_FUNC171_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x400)
-/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG171_IN_SEL    (BIT(7))
-#define GPIO_SIG171_IN_SEL_M  (BIT(7))
-#define GPIO_SIG171_IN_SEL_V  0x1
-#define GPIO_SIG171_IN_SEL_S  7
-/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC171_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC171_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC171_IN_INV_SEL_V  0x1
-#define GPIO_FUNC171_IN_INV_SEL_S  6
-/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC171_IN_SEL    0x0000003F
-#define GPIO_FUNC171_IN_SEL_M  ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S))
-#define GPIO_FUNC171_IN_SEL_V  0x3F
-#define GPIO_FUNC171_IN_SEL_S  0
-
-#define GPIO_FUNC172_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x404)
-/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG172_IN_SEL    (BIT(7))
-#define GPIO_SIG172_IN_SEL_M  (BIT(7))
-#define GPIO_SIG172_IN_SEL_V  0x1
-#define GPIO_SIG172_IN_SEL_S  7
-/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC172_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC172_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC172_IN_INV_SEL_V  0x1
-#define GPIO_FUNC172_IN_INV_SEL_S  6
-/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC172_IN_SEL    0x0000003F
-#define GPIO_FUNC172_IN_SEL_M  ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S))
-#define GPIO_FUNC172_IN_SEL_V  0x3F
-#define GPIO_FUNC172_IN_SEL_S  0
-
-#define GPIO_FUNC173_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x408)
-/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG173_IN_SEL    (BIT(7))
-#define GPIO_SIG173_IN_SEL_M  (BIT(7))
-#define GPIO_SIG173_IN_SEL_V  0x1
-#define GPIO_SIG173_IN_SEL_S  7
-/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC173_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC173_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC173_IN_INV_SEL_V  0x1
-#define GPIO_FUNC173_IN_INV_SEL_S  6
-/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC173_IN_SEL    0x0000003F
-#define GPIO_FUNC173_IN_SEL_M  ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S))
-#define GPIO_FUNC173_IN_SEL_V  0x3F
-#define GPIO_FUNC173_IN_SEL_S  0
-
-#define GPIO_FUNC174_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x40C)
-/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG174_IN_SEL    (BIT(7))
-#define GPIO_SIG174_IN_SEL_M  (BIT(7))
-#define GPIO_SIG174_IN_SEL_V  0x1
-#define GPIO_SIG174_IN_SEL_S  7
-/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC174_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC174_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC174_IN_INV_SEL_V  0x1
-#define GPIO_FUNC174_IN_INV_SEL_S  6
-/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC174_IN_SEL    0x0000003F
-#define GPIO_FUNC174_IN_SEL_M  ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S))
-#define GPIO_FUNC174_IN_SEL_V  0x3F
-#define GPIO_FUNC174_IN_SEL_S  0
-
-#define GPIO_FUNC175_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x410)
-/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG175_IN_SEL    (BIT(7))
-#define GPIO_SIG175_IN_SEL_M  (BIT(7))
-#define GPIO_SIG175_IN_SEL_V  0x1
-#define GPIO_SIG175_IN_SEL_S  7
-/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC175_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC175_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC175_IN_INV_SEL_V  0x1
-#define GPIO_FUNC175_IN_INV_SEL_S  6
-/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC175_IN_SEL    0x0000003F
-#define GPIO_FUNC175_IN_SEL_M  ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S))
-#define GPIO_FUNC175_IN_SEL_V  0x3F
-#define GPIO_FUNC175_IN_SEL_S  0
-
-#define GPIO_FUNC176_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x414)
-/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG176_IN_SEL    (BIT(7))
-#define GPIO_SIG176_IN_SEL_M  (BIT(7))
-#define GPIO_SIG176_IN_SEL_V  0x1
-#define GPIO_SIG176_IN_SEL_S  7
-/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC176_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC176_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC176_IN_INV_SEL_V  0x1
-#define GPIO_FUNC176_IN_INV_SEL_S  6
-/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC176_IN_SEL    0x0000003F
-#define GPIO_FUNC176_IN_SEL_M  ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S))
-#define GPIO_FUNC176_IN_SEL_V  0x3F
-#define GPIO_FUNC176_IN_SEL_S  0
-
-#define GPIO_FUNC177_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x418)
-/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG177_IN_SEL    (BIT(7))
-#define GPIO_SIG177_IN_SEL_M  (BIT(7))
-#define GPIO_SIG177_IN_SEL_V  0x1
-#define GPIO_SIG177_IN_SEL_S  7
-/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC177_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC177_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC177_IN_INV_SEL_V  0x1
-#define GPIO_FUNC177_IN_INV_SEL_S  6
-/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC177_IN_SEL    0x0000003F
-#define GPIO_FUNC177_IN_SEL_M  ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S))
-#define GPIO_FUNC177_IN_SEL_V  0x3F
-#define GPIO_FUNC177_IN_SEL_S  0
-
-#define GPIO_FUNC178_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x41C)
-/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG178_IN_SEL    (BIT(7))
-#define GPIO_SIG178_IN_SEL_M  (BIT(7))
-#define GPIO_SIG178_IN_SEL_V  0x1
-#define GPIO_SIG178_IN_SEL_S  7
-/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC178_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC178_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC178_IN_INV_SEL_V  0x1
-#define GPIO_FUNC178_IN_INV_SEL_S  6
-/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC178_IN_SEL    0x0000003F
-#define GPIO_FUNC178_IN_SEL_M  ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S))
-#define GPIO_FUNC178_IN_SEL_V  0x3F
-#define GPIO_FUNC178_IN_SEL_S  0
-
-#define GPIO_FUNC179_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x420)
-/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG179_IN_SEL    (BIT(7))
-#define GPIO_SIG179_IN_SEL_M  (BIT(7))
-#define GPIO_SIG179_IN_SEL_V  0x1
-#define GPIO_SIG179_IN_SEL_S  7
-/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC179_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC179_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC179_IN_INV_SEL_V  0x1
-#define GPIO_FUNC179_IN_INV_SEL_S  6
-/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC179_IN_SEL    0x0000003F
-#define GPIO_FUNC179_IN_SEL_M  ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S))
-#define GPIO_FUNC179_IN_SEL_V  0x3F
-#define GPIO_FUNC179_IN_SEL_S  0
-
-#define GPIO_FUNC180_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x424)
-/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG180_IN_SEL    (BIT(7))
-#define GPIO_SIG180_IN_SEL_M  (BIT(7))
-#define GPIO_SIG180_IN_SEL_V  0x1
-#define GPIO_SIG180_IN_SEL_S  7
-/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC180_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC180_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC180_IN_INV_SEL_V  0x1
-#define GPIO_FUNC180_IN_INV_SEL_S  6
-/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC180_IN_SEL    0x0000003F
-#define GPIO_FUNC180_IN_SEL_M  ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S))
-#define GPIO_FUNC180_IN_SEL_V  0x3F
-#define GPIO_FUNC180_IN_SEL_S  0
-
-#define GPIO_FUNC181_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x428)
-/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG181_IN_SEL    (BIT(7))
-#define GPIO_SIG181_IN_SEL_M  (BIT(7))
-#define GPIO_SIG181_IN_SEL_V  0x1
-#define GPIO_SIG181_IN_SEL_S  7
-/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC181_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC181_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC181_IN_INV_SEL_V  0x1
-#define GPIO_FUNC181_IN_INV_SEL_S  6
-/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC181_IN_SEL    0x0000003F
-#define GPIO_FUNC181_IN_SEL_M  ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S))
-#define GPIO_FUNC181_IN_SEL_V  0x3F
-#define GPIO_FUNC181_IN_SEL_S  0
-
-#define GPIO_FUNC182_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x42C)
-/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG182_IN_SEL    (BIT(7))
-#define GPIO_SIG182_IN_SEL_M  (BIT(7))
-#define GPIO_SIG182_IN_SEL_V  0x1
-#define GPIO_SIG182_IN_SEL_S  7
-/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC182_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC182_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC182_IN_INV_SEL_V  0x1
-#define GPIO_FUNC182_IN_INV_SEL_S  6
-/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC182_IN_SEL    0x0000003F
-#define GPIO_FUNC182_IN_SEL_M  ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S))
-#define GPIO_FUNC182_IN_SEL_V  0x3F
-#define GPIO_FUNC182_IN_SEL_S  0
-
-#define GPIO_FUNC183_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x430)
-/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG183_IN_SEL    (BIT(7))
-#define GPIO_SIG183_IN_SEL_M  (BIT(7))
-#define GPIO_SIG183_IN_SEL_V  0x1
-#define GPIO_SIG183_IN_SEL_S  7
-/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC183_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC183_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC183_IN_INV_SEL_V  0x1
-#define GPIO_FUNC183_IN_INV_SEL_S  6
-/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC183_IN_SEL    0x0000003F
-#define GPIO_FUNC183_IN_SEL_M  ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S))
-#define GPIO_FUNC183_IN_SEL_V  0x3F
-#define GPIO_FUNC183_IN_SEL_S  0
-
-#define GPIO_FUNC184_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x434)
-/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG184_IN_SEL    (BIT(7))
-#define GPIO_SIG184_IN_SEL_M  (BIT(7))
-#define GPIO_SIG184_IN_SEL_V  0x1
-#define GPIO_SIG184_IN_SEL_S  7
-/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC184_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC184_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC184_IN_INV_SEL_V  0x1
-#define GPIO_FUNC184_IN_INV_SEL_S  6
-/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC184_IN_SEL    0x0000003F
-#define GPIO_FUNC184_IN_SEL_M  ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S))
-#define GPIO_FUNC184_IN_SEL_V  0x3F
-#define GPIO_FUNC184_IN_SEL_S  0
-
-#define GPIO_FUNC185_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x438)
-/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG185_IN_SEL    (BIT(7))
-#define GPIO_SIG185_IN_SEL_M  (BIT(7))
-#define GPIO_SIG185_IN_SEL_V  0x1
-#define GPIO_SIG185_IN_SEL_S  7
-/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC185_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC185_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC185_IN_INV_SEL_V  0x1
-#define GPIO_FUNC185_IN_INV_SEL_S  6
-/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC185_IN_SEL    0x0000003F
-#define GPIO_FUNC185_IN_SEL_M  ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S))
-#define GPIO_FUNC185_IN_SEL_V  0x3F
-#define GPIO_FUNC185_IN_SEL_S  0
-
-#define GPIO_FUNC186_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x43C)
-/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG186_IN_SEL    (BIT(7))
-#define GPIO_SIG186_IN_SEL_M  (BIT(7))
-#define GPIO_SIG186_IN_SEL_V  0x1
-#define GPIO_SIG186_IN_SEL_S  7
-/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC186_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC186_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC186_IN_INV_SEL_V  0x1
-#define GPIO_FUNC186_IN_INV_SEL_S  6
-/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC186_IN_SEL    0x0000003F
-#define GPIO_FUNC186_IN_SEL_M  ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S))
-#define GPIO_FUNC186_IN_SEL_V  0x3F
-#define GPIO_FUNC186_IN_SEL_S  0
-
-#define GPIO_FUNC187_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x440)
-/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG187_IN_SEL    (BIT(7))
-#define GPIO_SIG187_IN_SEL_M  (BIT(7))
-#define GPIO_SIG187_IN_SEL_V  0x1
-#define GPIO_SIG187_IN_SEL_S  7
-/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC187_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC187_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC187_IN_INV_SEL_V  0x1
-#define GPIO_FUNC187_IN_INV_SEL_S  6
-/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC187_IN_SEL    0x0000003F
-#define GPIO_FUNC187_IN_SEL_M  ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S))
-#define GPIO_FUNC187_IN_SEL_V  0x3F
-#define GPIO_FUNC187_IN_SEL_S  0
-
-#define GPIO_FUNC188_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x444)
-/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG188_IN_SEL    (BIT(7))
-#define GPIO_SIG188_IN_SEL_M  (BIT(7))
-#define GPIO_SIG188_IN_SEL_V  0x1
-#define GPIO_SIG188_IN_SEL_S  7
-/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC188_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC188_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC188_IN_INV_SEL_V  0x1
-#define GPIO_FUNC188_IN_INV_SEL_S  6
-/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC188_IN_SEL    0x0000003F
-#define GPIO_FUNC188_IN_SEL_M  ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S))
-#define GPIO_FUNC188_IN_SEL_V  0x3F
-#define GPIO_FUNC188_IN_SEL_S  0
-
-#define GPIO_FUNC189_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x448)
-/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG189_IN_SEL    (BIT(7))
-#define GPIO_SIG189_IN_SEL_M  (BIT(7))
-#define GPIO_SIG189_IN_SEL_V  0x1
-#define GPIO_SIG189_IN_SEL_S  7
-/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC189_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC189_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC189_IN_INV_SEL_V  0x1
-#define GPIO_FUNC189_IN_INV_SEL_S  6
-/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC189_IN_SEL    0x0000003F
-#define GPIO_FUNC189_IN_SEL_M  ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S))
-#define GPIO_FUNC189_IN_SEL_V  0x3F
-#define GPIO_FUNC189_IN_SEL_S  0
-
-#define GPIO_FUNC190_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x44C)
-/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG190_IN_SEL    (BIT(7))
-#define GPIO_SIG190_IN_SEL_M  (BIT(7))
-#define GPIO_SIG190_IN_SEL_V  0x1
-#define GPIO_SIG190_IN_SEL_S  7
-/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC190_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC190_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC190_IN_INV_SEL_V  0x1
-#define GPIO_FUNC190_IN_INV_SEL_S  6
-/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC190_IN_SEL    0x0000003F
-#define GPIO_FUNC190_IN_SEL_M  ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S))
-#define GPIO_FUNC190_IN_SEL_V  0x3F
-#define GPIO_FUNC190_IN_SEL_S  0
-
-#define GPIO_FUNC191_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x450)
-/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG191_IN_SEL    (BIT(7))
-#define GPIO_SIG191_IN_SEL_M  (BIT(7))
-#define GPIO_SIG191_IN_SEL_V  0x1
-#define GPIO_SIG191_IN_SEL_S  7
-/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC191_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC191_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC191_IN_INV_SEL_V  0x1
-#define GPIO_FUNC191_IN_INV_SEL_S  6
-/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC191_IN_SEL    0x0000003F
-#define GPIO_FUNC191_IN_SEL_M  ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S))
-#define GPIO_FUNC191_IN_SEL_V  0x3F
-#define GPIO_FUNC191_IN_SEL_S  0
-
-#define GPIO_FUNC192_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x454)
-/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG192_IN_SEL    (BIT(7))
-#define GPIO_SIG192_IN_SEL_M  (BIT(7))
-#define GPIO_SIG192_IN_SEL_V  0x1
-#define GPIO_SIG192_IN_SEL_S  7
-/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC192_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC192_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC192_IN_INV_SEL_V  0x1
-#define GPIO_FUNC192_IN_INV_SEL_S  6
-/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC192_IN_SEL    0x0000003F
-#define GPIO_FUNC192_IN_SEL_M  ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S))
-#define GPIO_FUNC192_IN_SEL_V  0x3F
-#define GPIO_FUNC192_IN_SEL_S  0
-
-#define GPIO_FUNC193_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x458)
-/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG193_IN_SEL    (BIT(7))
-#define GPIO_SIG193_IN_SEL_M  (BIT(7))
-#define GPIO_SIG193_IN_SEL_V  0x1
-#define GPIO_SIG193_IN_SEL_S  7
-/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC193_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC193_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC193_IN_INV_SEL_V  0x1
-#define GPIO_FUNC193_IN_INV_SEL_S  6
-/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC193_IN_SEL    0x0000003F
-#define GPIO_FUNC193_IN_SEL_M  ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S))
-#define GPIO_FUNC193_IN_SEL_V  0x3F
-#define GPIO_FUNC193_IN_SEL_S  0
-
-#define GPIO_FUNC194_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x45C)
-/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG194_IN_SEL    (BIT(7))
-#define GPIO_SIG194_IN_SEL_M  (BIT(7))
-#define GPIO_SIG194_IN_SEL_V  0x1
-#define GPIO_SIG194_IN_SEL_S  7
-/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC194_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC194_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC194_IN_INV_SEL_V  0x1
-#define GPIO_FUNC194_IN_INV_SEL_S  6
-/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC194_IN_SEL    0x0000003F
-#define GPIO_FUNC194_IN_SEL_M  ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S))
-#define GPIO_FUNC194_IN_SEL_V  0x3F
-#define GPIO_FUNC194_IN_SEL_S  0
-
-#define GPIO_FUNC195_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x460)
-/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG195_IN_SEL    (BIT(7))
-#define GPIO_SIG195_IN_SEL_M  (BIT(7))
-#define GPIO_SIG195_IN_SEL_V  0x1
-#define GPIO_SIG195_IN_SEL_S  7
-/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC195_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC195_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC195_IN_INV_SEL_V  0x1
-#define GPIO_FUNC195_IN_INV_SEL_S  6
-/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC195_IN_SEL    0x0000003F
-#define GPIO_FUNC195_IN_SEL_M  ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S))
-#define GPIO_FUNC195_IN_SEL_V  0x3F
-#define GPIO_FUNC195_IN_SEL_S  0
-
-#define GPIO_FUNC196_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x464)
-/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG196_IN_SEL    (BIT(7))
-#define GPIO_SIG196_IN_SEL_M  (BIT(7))
-#define GPIO_SIG196_IN_SEL_V  0x1
-#define GPIO_SIG196_IN_SEL_S  7
-/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC196_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC196_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC196_IN_INV_SEL_V  0x1
-#define GPIO_FUNC196_IN_INV_SEL_S  6
-/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC196_IN_SEL    0x0000003F
-#define GPIO_FUNC196_IN_SEL_M  ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S))
-#define GPIO_FUNC196_IN_SEL_V  0x3F
-#define GPIO_FUNC196_IN_SEL_S  0
-
-#define GPIO_FUNC197_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x468)
-/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG197_IN_SEL    (BIT(7))
-#define GPIO_SIG197_IN_SEL_M  (BIT(7))
-#define GPIO_SIG197_IN_SEL_V  0x1
-#define GPIO_SIG197_IN_SEL_S  7
-/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC197_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC197_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC197_IN_INV_SEL_V  0x1
-#define GPIO_FUNC197_IN_INV_SEL_S  6
-/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC197_IN_SEL    0x0000003F
-#define GPIO_FUNC197_IN_SEL_M  ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S))
-#define GPIO_FUNC197_IN_SEL_V  0x3F
-#define GPIO_FUNC197_IN_SEL_S  0
-
-#define GPIO_FUNC198_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x46C)
-/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG198_IN_SEL    (BIT(7))
-#define GPIO_SIG198_IN_SEL_M  (BIT(7))
-#define GPIO_SIG198_IN_SEL_V  0x1
-#define GPIO_SIG198_IN_SEL_S  7
-/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC198_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC198_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC198_IN_INV_SEL_V  0x1
-#define GPIO_FUNC198_IN_INV_SEL_S  6
-/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC198_IN_SEL    0x0000003F
-#define GPIO_FUNC198_IN_SEL_M  ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S))
-#define GPIO_FUNC198_IN_SEL_V  0x3F
-#define GPIO_FUNC198_IN_SEL_S  0
-
-#define GPIO_FUNC199_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x470)
-/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG199_IN_SEL    (BIT(7))
-#define GPIO_SIG199_IN_SEL_M  (BIT(7))
-#define GPIO_SIG199_IN_SEL_V  0x1
-#define GPIO_SIG199_IN_SEL_S  7
-/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC199_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC199_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC199_IN_INV_SEL_V  0x1
-#define GPIO_FUNC199_IN_INV_SEL_S  6
-/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC199_IN_SEL    0x0000003F
-#define GPIO_FUNC199_IN_SEL_M  ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S))
-#define GPIO_FUNC199_IN_SEL_V  0x3F
-#define GPIO_FUNC199_IN_SEL_S  0
-
-#define GPIO_FUNC200_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x474)
-/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG200_IN_SEL    (BIT(7))
-#define GPIO_SIG200_IN_SEL_M  (BIT(7))
-#define GPIO_SIG200_IN_SEL_V  0x1
-#define GPIO_SIG200_IN_SEL_S  7
-/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC200_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC200_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC200_IN_INV_SEL_V  0x1
-#define GPIO_FUNC200_IN_INV_SEL_S  6
-/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC200_IN_SEL    0x0000003F
-#define GPIO_FUNC200_IN_SEL_M  ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S))
-#define GPIO_FUNC200_IN_SEL_V  0x3F
-#define GPIO_FUNC200_IN_SEL_S  0
-
-#define GPIO_FUNC201_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x478)
-/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG201_IN_SEL    (BIT(7))
-#define GPIO_SIG201_IN_SEL_M  (BIT(7))
-#define GPIO_SIG201_IN_SEL_V  0x1
-#define GPIO_SIG201_IN_SEL_S  7
-/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC201_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC201_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC201_IN_INV_SEL_V  0x1
-#define GPIO_FUNC201_IN_INV_SEL_S  6
-/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC201_IN_SEL    0x0000003F
-#define GPIO_FUNC201_IN_SEL_M  ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S))
-#define GPIO_FUNC201_IN_SEL_V  0x3F
-#define GPIO_FUNC201_IN_SEL_S  0
-
-#define GPIO_FUNC202_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x47C)
-/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG202_IN_SEL    (BIT(7))
-#define GPIO_SIG202_IN_SEL_M  (BIT(7))
-#define GPIO_SIG202_IN_SEL_V  0x1
-#define GPIO_SIG202_IN_SEL_S  7
-/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC202_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC202_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC202_IN_INV_SEL_V  0x1
-#define GPIO_FUNC202_IN_INV_SEL_S  6
-/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC202_IN_SEL    0x0000003F
-#define GPIO_FUNC202_IN_SEL_M  ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S))
-#define GPIO_FUNC202_IN_SEL_V  0x3F
-#define GPIO_FUNC202_IN_SEL_S  0
-
-#define GPIO_FUNC203_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x480)
-/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG203_IN_SEL    (BIT(7))
-#define GPIO_SIG203_IN_SEL_M  (BIT(7))
-#define GPIO_SIG203_IN_SEL_V  0x1
-#define GPIO_SIG203_IN_SEL_S  7
-/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC203_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC203_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC203_IN_INV_SEL_V  0x1
-#define GPIO_FUNC203_IN_INV_SEL_S  6
-/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC203_IN_SEL    0x0000003F
-#define GPIO_FUNC203_IN_SEL_M  ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S))
-#define GPIO_FUNC203_IN_SEL_V  0x3F
-#define GPIO_FUNC203_IN_SEL_S  0
-
-#define GPIO_FUNC204_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x484)
-/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG204_IN_SEL    (BIT(7))
-#define GPIO_SIG204_IN_SEL_M  (BIT(7))
-#define GPIO_SIG204_IN_SEL_V  0x1
-#define GPIO_SIG204_IN_SEL_S  7
-/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC204_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC204_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC204_IN_INV_SEL_V  0x1
-#define GPIO_FUNC204_IN_INV_SEL_S  6
-/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC204_IN_SEL    0x0000003F
-#define GPIO_FUNC204_IN_SEL_M  ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S))
-#define GPIO_FUNC204_IN_SEL_V  0x3F
-#define GPIO_FUNC204_IN_SEL_S  0
-
-#define GPIO_FUNC205_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x488)
-/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG205_IN_SEL    (BIT(7))
-#define GPIO_SIG205_IN_SEL_M  (BIT(7))
-#define GPIO_SIG205_IN_SEL_V  0x1
-#define GPIO_SIG205_IN_SEL_S  7
-/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC205_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC205_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC205_IN_INV_SEL_V  0x1
-#define GPIO_FUNC205_IN_INV_SEL_S  6
-/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC205_IN_SEL    0x0000003F
-#define GPIO_FUNC205_IN_SEL_M  ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S))
-#define GPIO_FUNC205_IN_SEL_V  0x3F
-#define GPIO_FUNC205_IN_SEL_S  0
-
-#define GPIO_FUNC206_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x48C)
-/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG206_IN_SEL    (BIT(7))
-#define GPIO_SIG206_IN_SEL_M  (BIT(7))
-#define GPIO_SIG206_IN_SEL_V  0x1
-#define GPIO_SIG206_IN_SEL_S  7
-/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC206_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC206_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC206_IN_INV_SEL_V  0x1
-#define GPIO_FUNC206_IN_INV_SEL_S  6
-/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC206_IN_SEL    0x0000003F
-#define GPIO_FUNC206_IN_SEL_M  ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S))
-#define GPIO_FUNC206_IN_SEL_V  0x3F
-#define GPIO_FUNC206_IN_SEL_S  0
-
-#define GPIO_FUNC207_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x490)
-/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG207_IN_SEL    (BIT(7))
-#define GPIO_SIG207_IN_SEL_M  (BIT(7))
-#define GPIO_SIG207_IN_SEL_V  0x1
-#define GPIO_SIG207_IN_SEL_S  7
-/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC207_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC207_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC207_IN_INV_SEL_V  0x1
-#define GPIO_FUNC207_IN_INV_SEL_S  6
-/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC207_IN_SEL    0x0000003F
-#define GPIO_FUNC207_IN_SEL_M  ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S))
-#define GPIO_FUNC207_IN_SEL_V  0x3F
-#define GPIO_FUNC207_IN_SEL_S  0
-
-#define GPIO_FUNC208_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x494)
-/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG208_IN_SEL    (BIT(7))
-#define GPIO_SIG208_IN_SEL_M  (BIT(7))
-#define GPIO_SIG208_IN_SEL_V  0x1
-#define GPIO_SIG208_IN_SEL_S  7
-/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC208_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC208_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC208_IN_INV_SEL_V  0x1
-#define GPIO_FUNC208_IN_INV_SEL_S  6
-/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC208_IN_SEL    0x0000003F
-#define GPIO_FUNC208_IN_SEL_M  ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S))
-#define GPIO_FUNC208_IN_SEL_V  0x3F
-#define GPIO_FUNC208_IN_SEL_S  0
-
-#define GPIO_FUNC209_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x498)
-/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG209_IN_SEL    (BIT(7))
-#define GPIO_SIG209_IN_SEL_M  (BIT(7))
-#define GPIO_SIG209_IN_SEL_V  0x1
-#define GPIO_SIG209_IN_SEL_S  7
-/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC209_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC209_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC209_IN_INV_SEL_V  0x1
-#define GPIO_FUNC209_IN_INV_SEL_S  6
-/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC209_IN_SEL    0x0000003F
-#define GPIO_FUNC209_IN_SEL_M  ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S))
-#define GPIO_FUNC209_IN_SEL_V  0x3F
-#define GPIO_FUNC209_IN_SEL_S  0
-
-#define GPIO_FUNC210_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x49C)
-/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG210_IN_SEL    (BIT(7))
-#define GPIO_SIG210_IN_SEL_M  (BIT(7))
-#define GPIO_SIG210_IN_SEL_V  0x1
-#define GPIO_SIG210_IN_SEL_S  7
-/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC210_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC210_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC210_IN_INV_SEL_V  0x1
-#define GPIO_FUNC210_IN_INV_SEL_S  6
-/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC210_IN_SEL    0x0000003F
-#define GPIO_FUNC210_IN_SEL_M  ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S))
-#define GPIO_FUNC210_IN_SEL_V  0x3F
-#define GPIO_FUNC210_IN_SEL_S  0
-
-#define GPIO_FUNC211_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A0)
-/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG211_IN_SEL    (BIT(7))
-#define GPIO_SIG211_IN_SEL_M  (BIT(7))
-#define GPIO_SIG211_IN_SEL_V  0x1
-#define GPIO_SIG211_IN_SEL_S  7
-/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC211_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC211_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC211_IN_INV_SEL_V  0x1
-#define GPIO_FUNC211_IN_INV_SEL_S  6
-/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC211_IN_SEL    0x0000003F
-#define GPIO_FUNC211_IN_SEL_M  ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S))
-#define GPIO_FUNC211_IN_SEL_V  0x3F
-#define GPIO_FUNC211_IN_SEL_S  0
-
-#define GPIO_FUNC212_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A4)
-/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG212_IN_SEL    (BIT(7))
-#define GPIO_SIG212_IN_SEL_M  (BIT(7))
-#define GPIO_SIG212_IN_SEL_V  0x1
-#define GPIO_SIG212_IN_SEL_S  7
-/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC212_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC212_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC212_IN_INV_SEL_V  0x1
-#define GPIO_FUNC212_IN_INV_SEL_S  6
-/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC212_IN_SEL    0x0000003F
-#define GPIO_FUNC212_IN_SEL_M  ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S))
-#define GPIO_FUNC212_IN_SEL_V  0x3F
-#define GPIO_FUNC212_IN_SEL_S  0
-
-#define GPIO_FUNC213_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A8)
-/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG213_IN_SEL    (BIT(7))
-#define GPIO_SIG213_IN_SEL_M  (BIT(7))
-#define GPIO_SIG213_IN_SEL_V  0x1
-#define GPIO_SIG213_IN_SEL_S  7
-/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC213_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC213_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC213_IN_INV_SEL_V  0x1
-#define GPIO_FUNC213_IN_INV_SEL_S  6
-/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC213_IN_SEL    0x0000003F
-#define GPIO_FUNC213_IN_SEL_M  ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S))
-#define GPIO_FUNC213_IN_SEL_V  0x3F
-#define GPIO_FUNC213_IN_SEL_S  0
-
-#define GPIO_FUNC214_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4AC)
-/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG214_IN_SEL    (BIT(7))
-#define GPIO_SIG214_IN_SEL_M  (BIT(7))
-#define GPIO_SIG214_IN_SEL_V  0x1
-#define GPIO_SIG214_IN_SEL_S  7
-/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC214_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC214_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC214_IN_INV_SEL_V  0x1
-#define GPIO_FUNC214_IN_INV_SEL_S  6
-/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC214_IN_SEL    0x0000003F
-#define GPIO_FUNC214_IN_SEL_M  ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S))
-#define GPIO_FUNC214_IN_SEL_V  0x3F
-#define GPIO_FUNC214_IN_SEL_S  0
-
-#define GPIO_FUNC215_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B0)
-/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG215_IN_SEL    (BIT(7))
-#define GPIO_SIG215_IN_SEL_M  (BIT(7))
-#define GPIO_SIG215_IN_SEL_V  0x1
-#define GPIO_SIG215_IN_SEL_S  7
-/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC215_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC215_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC215_IN_INV_SEL_V  0x1
-#define GPIO_FUNC215_IN_INV_SEL_S  6
-/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC215_IN_SEL    0x0000003F
-#define GPIO_FUNC215_IN_SEL_M  ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S))
-#define GPIO_FUNC215_IN_SEL_V  0x3F
-#define GPIO_FUNC215_IN_SEL_S  0
-
-#define GPIO_FUNC216_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B4)
-/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG216_IN_SEL    (BIT(7))
-#define GPIO_SIG216_IN_SEL_M  (BIT(7))
-#define GPIO_SIG216_IN_SEL_V  0x1
-#define GPIO_SIG216_IN_SEL_S  7
-/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC216_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC216_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC216_IN_INV_SEL_V  0x1
-#define GPIO_FUNC216_IN_INV_SEL_S  6
-/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC216_IN_SEL    0x0000003F
-#define GPIO_FUNC216_IN_SEL_M  ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S))
-#define GPIO_FUNC216_IN_SEL_V  0x3F
-#define GPIO_FUNC216_IN_SEL_S  0
-
-#define GPIO_FUNC217_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B8)
-/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG217_IN_SEL    (BIT(7))
-#define GPIO_SIG217_IN_SEL_M  (BIT(7))
-#define GPIO_SIG217_IN_SEL_V  0x1
-#define GPIO_SIG217_IN_SEL_S  7
-/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC217_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC217_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC217_IN_INV_SEL_V  0x1
-#define GPIO_FUNC217_IN_INV_SEL_S  6
-/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC217_IN_SEL    0x0000003F
-#define GPIO_FUNC217_IN_SEL_M  ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S))
-#define GPIO_FUNC217_IN_SEL_V  0x3F
-#define GPIO_FUNC217_IN_SEL_S  0
-
-#define GPIO_FUNC218_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4BC)
-/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG218_IN_SEL    (BIT(7))
-#define GPIO_SIG218_IN_SEL_M  (BIT(7))
-#define GPIO_SIG218_IN_SEL_V  0x1
-#define GPIO_SIG218_IN_SEL_S  7
-/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC218_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC218_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC218_IN_INV_SEL_V  0x1
-#define GPIO_FUNC218_IN_INV_SEL_S  6
-/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC218_IN_SEL    0x0000003F
-#define GPIO_FUNC218_IN_SEL_M  ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S))
-#define GPIO_FUNC218_IN_SEL_V  0x3F
-#define GPIO_FUNC218_IN_SEL_S  0
-
-#define GPIO_FUNC219_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C0)
-/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG219_IN_SEL    (BIT(7))
-#define GPIO_SIG219_IN_SEL_M  (BIT(7))
-#define GPIO_SIG219_IN_SEL_V  0x1
-#define GPIO_SIG219_IN_SEL_S  7
-/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC219_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC219_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC219_IN_INV_SEL_V  0x1
-#define GPIO_FUNC219_IN_INV_SEL_S  6
-/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC219_IN_SEL    0x0000003F
-#define GPIO_FUNC219_IN_SEL_M  ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S))
-#define GPIO_FUNC219_IN_SEL_V  0x3F
-#define GPIO_FUNC219_IN_SEL_S  0
-
-#define GPIO_FUNC220_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C4)
-/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG220_IN_SEL    (BIT(7))
-#define GPIO_SIG220_IN_SEL_M  (BIT(7))
-#define GPIO_SIG220_IN_SEL_V  0x1
-#define GPIO_SIG220_IN_SEL_S  7
-/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC220_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC220_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC220_IN_INV_SEL_V  0x1
-#define GPIO_FUNC220_IN_INV_SEL_S  6
-/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC220_IN_SEL    0x0000003F
-#define GPIO_FUNC220_IN_SEL_M  ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S))
-#define GPIO_FUNC220_IN_SEL_V  0x3F
-#define GPIO_FUNC220_IN_SEL_S  0
-
-#define GPIO_FUNC221_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C8)
-/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG221_IN_SEL    (BIT(7))
-#define GPIO_SIG221_IN_SEL_M  (BIT(7))
-#define GPIO_SIG221_IN_SEL_V  0x1
-#define GPIO_SIG221_IN_SEL_S  7
-/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC221_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC221_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC221_IN_INV_SEL_V  0x1
-#define GPIO_FUNC221_IN_INV_SEL_S  6
-/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC221_IN_SEL    0x0000003F
-#define GPIO_FUNC221_IN_SEL_M  ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S))
-#define GPIO_FUNC221_IN_SEL_V  0x3F
-#define GPIO_FUNC221_IN_SEL_S  0
-
-#define GPIO_FUNC222_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4CC)
-/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG222_IN_SEL    (BIT(7))
-#define GPIO_SIG222_IN_SEL_M  (BIT(7))
-#define GPIO_SIG222_IN_SEL_V  0x1
-#define GPIO_SIG222_IN_SEL_S  7
-/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC222_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC222_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC222_IN_INV_SEL_V  0x1
-#define GPIO_FUNC222_IN_INV_SEL_S  6
-/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC222_IN_SEL    0x0000003F
-#define GPIO_FUNC222_IN_SEL_M  ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S))
-#define GPIO_FUNC222_IN_SEL_V  0x3F
-#define GPIO_FUNC222_IN_SEL_S  0
-
-#define GPIO_FUNC223_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D0)
-/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG223_IN_SEL    (BIT(7))
-#define GPIO_SIG223_IN_SEL_M  (BIT(7))
-#define GPIO_SIG223_IN_SEL_V  0x1
-#define GPIO_SIG223_IN_SEL_S  7
-/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC223_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC223_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC223_IN_INV_SEL_V  0x1
-#define GPIO_FUNC223_IN_INV_SEL_S  6
-/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC223_IN_SEL    0x0000003F
-#define GPIO_FUNC223_IN_SEL_M  ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S))
-#define GPIO_FUNC223_IN_SEL_V  0x3F
-#define GPIO_FUNC223_IN_SEL_S  0
-
-#define GPIO_FUNC224_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D4)
-/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG224_IN_SEL    (BIT(7))
-#define GPIO_SIG224_IN_SEL_M  (BIT(7))
-#define GPIO_SIG224_IN_SEL_V  0x1
-#define GPIO_SIG224_IN_SEL_S  7
-/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC224_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC224_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC224_IN_INV_SEL_V  0x1
-#define GPIO_FUNC224_IN_INV_SEL_S  6
-/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC224_IN_SEL    0x0000003F
-#define GPIO_FUNC224_IN_SEL_M  ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S))
-#define GPIO_FUNC224_IN_SEL_V  0x3F
-#define GPIO_FUNC224_IN_SEL_S  0
-
-#define GPIO_FUNC225_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D8)
-/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG225_IN_SEL    (BIT(7))
-#define GPIO_SIG225_IN_SEL_M  (BIT(7))
-#define GPIO_SIG225_IN_SEL_V  0x1
-#define GPIO_SIG225_IN_SEL_S  7
-/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC225_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC225_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC225_IN_INV_SEL_V  0x1
-#define GPIO_FUNC225_IN_INV_SEL_S  6
-/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC225_IN_SEL    0x0000003F
-#define GPIO_FUNC225_IN_SEL_M  ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S))
-#define GPIO_FUNC225_IN_SEL_V  0x3F
-#define GPIO_FUNC225_IN_SEL_S  0
-
-#define GPIO_FUNC226_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4DC)
-/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG226_IN_SEL    (BIT(7))
-#define GPIO_SIG226_IN_SEL_M  (BIT(7))
-#define GPIO_SIG226_IN_SEL_V  0x1
-#define GPIO_SIG226_IN_SEL_S  7
-/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC226_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC226_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC226_IN_INV_SEL_V  0x1
-#define GPIO_FUNC226_IN_INV_SEL_S  6
-/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC226_IN_SEL    0x0000003F
-#define GPIO_FUNC226_IN_SEL_M  ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S))
-#define GPIO_FUNC226_IN_SEL_V  0x3F
-#define GPIO_FUNC226_IN_SEL_S  0
-
-#define GPIO_FUNC227_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E0)
-/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG227_IN_SEL    (BIT(7))
-#define GPIO_SIG227_IN_SEL_M  (BIT(7))
-#define GPIO_SIG227_IN_SEL_V  0x1
-#define GPIO_SIG227_IN_SEL_S  7
-/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC227_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC227_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC227_IN_INV_SEL_V  0x1
-#define GPIO_FUNC227_IN_INV_SEL_S  6
-/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC227_IN_SEL    0x0000003F
-#define GPIO_FUNC227_IN_SEL_M  ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S))
-#define GPIO_FUNC227_IN_SEL_V  0x3F
-#define GPIO_FUNC227_IN_SEL_S  0
-
-#define GPIO_FUNC228_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E4)
-/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG228_IN_SEL    (BIT(7))
-#define GPIO_SIG228_IN_SEL_M  (BIT(7))
-#define GPIO_SIG228_IN_SEL_V  0x1
-#define GPIO_SIG228_IN_SEL_S  7
-/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC228_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC228_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC228_IN_INV_SEL_V  0x1
-#define GPIO_FUNC228_IN_INV_SEL_S  6
-/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC228_IN_SEL    0x0000003F
-#define GPIO_FUNC228_IN_SEL_M  ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S))
-#define GPIO_FUNC228_IN_SEL_V  0x3F
-#define GPIO_FUNC228_IN_SEL_S  0
-
-#define GPIO_FUNC229_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E8)
-/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG229_IN_SEL    (BIT(7))
-#define GPIO_SIG229_IN_SEL_M  (BIT(7))
-#define GPIO_SIG229_IN_SEL_V  0x1
-#define GPIO_SIG229_IN_SEL_S  7
-/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC229_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC229_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC229_IN_INV_SEL_V  0x1
-#define GPIO_FUNC229_IN_INV_SEL_S  6
-/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC229_IN_SEL    0x0000003F
-#define GPIO_FUNC229_IN_SEL_M  ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S))
-#define GPIO_FUNC229_IN_SEL_V  0x3F
-#define GPIO_FUNC229_IN_SEL_S  0
-
-#define GPIO_FUNC230_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4EC)
-/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG230_IN_SEL    (BIT(7))
-#define GPIO_SIG230_IN_SEL_M  (BIT(7))
-#define GPIO_SIG230_IN_SEL_V  0x1
-#define GPIO_SIG230_IN_SEL_S  7
-/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC230_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC230_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC230_IN_INV_SEL_V  0x1
-#define GPIO_FUNC230_IN_INV_SEL_S  6
-/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC230_IN_SEL    0x0000003F
-#define GPIO_FUNC230_IN_SEL_M  ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S))
-#define GPIO_FUNC230_IN_SEL_V  0x3F
-#define GPIO_FUNC230_IN_SEL_S  0
-
-#define GPIO_FUNC231_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F0)
-/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG231_IN_SEL    (BIT(7))
-#define GPIO_SIG231_IN_SEL_M  (BIT(7))
-#define GPIO_SIG231_IN_SEL_V  0x1
-#define GPIO_SIG231_IN_SEL_S  7
-/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC231_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC231_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC231_IN_INV_SEL_V  0x1
-#define GPIO_FUNC231_IN_INV_SEL_S  6
-/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC231_IN_SEL    0x0000003F
-#define GPIO_FUNC231_IN_SEL_M  ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S))
-#define GPIO_FUNC231_IN_SEL_V  0x3F
-#define GPIO_FUNC231_IN_SEL_S  0
-
-#define GPIO_FUNC232_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F4)
-/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG232_IN_SEL    (BIT(7))
-#define GPIO_SIG232_IN_SEL_M  (BIT(7))
-#define GPIO_SIG232_IN_SEL_V  0x1
-#define GPIO_SIG232_IN_SEL_S  7
-/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC232_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC232_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC232_IN_INV_SEL_V  0x1
-#define GPIO_FUNC232_IN_INV_SEL_S  6
-/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC232_IN_SEL    0x0000003F
-#define GPIO_FUNC232_IN_SEL_M  ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S))
-#define GPIO_FUNC232_IN_SEL_V  0x3F
-#define GPIO_FUNC232_IN_SEL_S  0
-
-#define GPIO_FUNC233_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F8)
-/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG233_IN_SEL    (BIT(7))
-#define GPIO_SIG233_IN_SEL_M  (BIT(7))
-#define GPIO_SIG233_IN_SEL_V  0x1
-#define GPIO_SIG233_IN_SEL_S  7
-/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC233_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC233_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC233_IN_INV_SEL_V  0x1
-#define GPIO_FUNC233_IN_INV_SEL_S  6
-/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC233_IN_SEL    0x0000003F
-#define GPIO_FUNC233_IN_SEL_M  ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S))
-#define GPIO_FUNC233_IN_SEL_V  0x3F
-#define GPIO_FUNC233_IN_SEL_S  0
-
-#define GPIO_FUNC234_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4FC)
-/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG234_IN_SEL    (BIT(7))
-#define GPIO_SIG234_IN_SEL_M  (BIT(7))
-#define GPIO_SIG234_IN_SEL_V  0x1
-#define GPIO_SIG234_IN_SEL_S  7
-/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC234_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC234_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC234_IN_INV_SEL_V  0x1
-#define GPIO_FUNC234_IN_INV_SEL_S  6
-/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC234_IN_SEL    0x0000003F
-#define GPIO_FUNC234_IN_SEL_M  ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S))
-#define GPIO_FUNC234_IN_SEL_V  0x3F
-#define GPIO_FUNC234_IN_SEL_S  0
-
-#define GPIO_FUNC235_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x500)
-/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG235_IN_SEL    (BIT(7))
-#define GPIO_SIG235_IN_SEL_M  (BIT(7))
-#define GPIO_SIG235_IN_SEL_V  0x1
-#define GPIO_SIG235_IN_SEL_S  7
-/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC235_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC235_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC235_IN_INV_SEL_V  0x1
-#define GPIO_FUNC235_IN_INV_SEL_S  6
-/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC235_IN_SEL    0x0000003F
-#define GPIO_FUNC235_IN_SEL_M  ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S))
-#define GPIO_FUNC235_IN_SEL_V  0x3F
-#define GPIO_FUNC235_IN_SEL_S  0
-
-#define GPIO_FUNC236_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x504)
-/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG236_IN_SEL    (BIT(7))
-#define GPIO_SIG236_IN_SEL_M  (BIT(7))
-#define GPIO_SIG236_IN_SEL_V  0x1
-#define GPIO_SIG236_IN_SEL_S  7
-/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC236_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC236_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC236_IN_INV_SEL_V  0x1
-#define GPIO_FUNC236_IN_INV_SEL_S  6
-/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC236_IN_SEL    0x0000003F
-#define GPIO_FUNC236_IN_SEL_M  ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S))
-#define GPIO_FUNC236_IN_SEL_V  0x3F
-#define GPIO_FUNC236_IN_SEL_S  0
-
-#define GPIO_FUNC237_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x508)
-/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG237_IN_SEL    (BIT(7))
-#define GPIO_SIG237_IN_SEL_M  (BIT(7))
-#define GPIO_SIG237_IN_SEL_V  0x1
-#define GPIO_SIG237_IN_SEL_S  7
-/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC237_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC237_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC237_IN_INV_SEL_V  0x1
-#define GPIO_FUNC237_IN_INV_SEL_S  6
-/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC237_IN_SEL    0x0000003F
-#define GPIO_FUNC237_IN_SEL_M  ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S))
-#define GPIO_FUNC237_IN_SEL_V  0x3F
-#define GPIO_FUNC237_IN_SEL_S  0
-
-#define GPIO_FUNC238_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x50C)
-/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG238_IN_SEL    (BIT(7))
-#define GPIO_SIG238_IN_SEL_M  (BIT(7))
-#define GPIO_SIG238_IN_SEL_V  0x1
-#define GPIO_SIG238_IN_SEL_S  7
-/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC238_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC238_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC238_IN_INV_SEL_V  0x1
-#define GPIO_FUNC238_IN_INV_SEL_S  6
-/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC238_IN_SEL    0x0000003F
-#define GPIO_FUNC238_IN_SEL_M  ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S))
-#define GPIO_FUNC238_IN_SEL_V  0x3F
-#define GPIO_FUNC238_IN_SEL_S  0
-
-#define GPIO_FUNC239_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x510)
-/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG239_IN_SEL    (BIT(7))
-#define GPIO_SIG239_IN_SEL_M  (BIT(7))
-#define GPIO_SIG239_IN_SEL_V  0x1
-#define GPIO_SIG239_IN_SEL_S  7
-/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC239_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC239_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC239_IN_INV_SEL_V  0x1
-#define GPIO_FUNC239_IN_INV_SEL_S  6
-/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC239_IN_SEL    0x0000003F
-#define GPIO_FUNC239_IN_SEL_M  ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S))
-#define GPIO_FUNC239_IN_SEL_V  0x3F
-#define GPIO_FUNC239_IN_SEL_S  0
-
-#define GPIO_FUNC240_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x514)
-/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG240_IN_SEL    (BIT(7))
-#define GPIO_SIG240_IN_SEL_M  (BIT(7))
-#define GPIO_SIG240_IN_SEL_V  0x1
-#define GPIO_SIG240_IN_SEL_S  7
-/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC240_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC240_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC240_IN_INV_SEL_V  0x1
-#define GPIO_FUNC240_IN_INV_SEL_S  6
-/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC240_IN_SEL    0x0000003F
-#define GPIO_FUNC240_IN_SEL_M  ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S))
-#define GPIO_FUNC240_IN_SEL_V  0x3F
-#define GPIO_FUNC240_IN_SEL_S  0
-
-#define GPIO_FUNC241_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x518)
-/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG241_IN_SEL    (BIT(7))
-#define GPIO_SIG241_IN_SEL_M  (BIT(7))
-#define GPIO_SIG241_IN_SEL_V  0x1
-#define GPIO_SIG241_IN_SEL_S  7
-/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC241_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC241_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC241_IN_INV_SEL_V  0x1
-#define GPIO_FUNC241_IN_INV_SEL_S  6
-/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC241_IN_SEL    0x0000003F
-#define GPIO_FUNC241_IN_SEL_M  ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S))
-#define GPIO_FUNC241_IN_SEL_V  0x3F
-#define GPIO_FUNC241_IN_SEL_S  0
-
-#define GPIO_FUNC242_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x51C)
-/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG242_IN_SEL    (BIT(7))
-#define GPIO_SIG242_IN_SEL_M  (BIT(7))
-#define GPIO_SIG242_IN_SEL_V  0x1
-#define GPIO_SIG242_IN_SEL_S  7
-/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC242_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC242_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC242_IN_INV_SEL_V  0x1
-#define GPIO_FUNC242_IN_INV_SEL_S  6
-/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC242_IN_SEL    0x0000003F
-#define GPIO_FUNC242_IN_SEL_M  ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S))
-#define GPIO_FUNC242_IN_SEL_V  0x3F
-#define GPIO_FUNC242_IN_SEL_S  0
-
-#define GPIO_FUNC243_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x520)
-/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG243_IN_SEL    (BIT(7))
-#define GPIO_SIG243_IN_SEL_M  (BIT(7))
-#define GPIO_SIG243_IN_SEL_V  0x1
-#define GPIO_SIG243_IN_SEL_S  7
-/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC243_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC243_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC243_IN_INV_SEL_V  0x1
-#define GPIO_FUNC243_IN_INV_SEL_S  6
-/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC243_IN_SEL    0x0000003F
-#define GPIO_FUNC243_IN_SEL_M  ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S))
-#define GPIO_FUNC243_IN_SEL_V  0x3F
-#define GPIO_FUNC243_IN_SEL_S  0
-
-#define GPIO_FUNC244_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x524)
-/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG244_IN_SEL    (BIT(7))
-#define GPIO_SIG244_IN_SEL_M  (BIT(7))
-#define GPIO_SIG244_IN_SEL_V  0x1
-#define GPIO_SIG244_IN_SEL_S  7
-/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC244_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC244_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC244_IN_INV_SEL_V  0x1
-#define GPIO_FUNC244_IN_INV_SEL_S  6
-/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC244_IN_SEL    0x0000003F
-#define GPIO_FUNC244_IN_SEL_M  ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S))
-#define GPIO_FUNC244_IN_SEL_V  0x3F
-#define GPIO_FUNC244_IN_SEL_S  0
-
-#define GPIO_FUNC245_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x528)
-/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG245_IN_SEL    (BIT(7))
-#define GPIO_SIG245_IN_SEL_M  (BIT(7))
-#define GPIO_SIG245_IN_SEL_V  0x1
-#define GPIO_SIG245_IN_SEL_S  7
-/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC245_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC245_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC245_IN_INV_SEL_V  0x1
-#define GPIO_FUNC245_IN_INV_SEL_S  6
-/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC245_IN_SEL    0x0000003F
-#define GPIO_FUNC245_IN_SEL_M  ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S))
-#define GPIO_FUNC245_IN_SEL_V  0x3F
-#define GPIO_FUNC245_IN_SEL_S  0
-
-#define GPIO_FUNC246_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x52C)
-/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG246_IN_SEL    (BIT(7))
-#define GPIO_SIG246_IN_SEL_M  (BIT(7))
-#define GPIO_SIG246_IN_SEL_V  0x1
-#define GPIO_SIG246_IN_SEL_S  7
-/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC246_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC246_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC246_IN_INV_SEL_V  0x1
-#define GPIO_FUNC246_IN_INV_SEL_S  6
-/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC246_IN_SEL    0x0000003F
-#define GPIO_FUNC246_IN_SEL_M  ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S))
-#define GPIO_FUNC246_IN_SEL_V  0x3F
-#define GPIO_FUNC246_IN_SEL_S  0
-
-#define GPIO_FUNC247_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x530)
-/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG247_IN_SEL    (BIT(7))
-#define GPIO_SIG247_IN_SEL_M  (BIT(7))
-#define GPIO_SIG247_IN_SEL_V  0x1
-#define GPIO_SIG247_IN_SEL_S  7
-/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC247_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC247_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC247_IN_INV_SEL_V  0x1
-#define GPIO_FUNC247_IN_INV_SEL_S  6
-/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC247_IN_SEL    0x0000003F
-#define GPIO_FUNC247_IN_SEL_M  ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S))
-#define GPIO_FUNC247_IN_SEL_V  0x3F
-#define GPIO_FUNC247_IN_SEL_S  0
-
-#define GPIO_FUNC248_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x534)
-/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG248_IN_SEL    (BIT(7))
-#define GPIO_SIG248_IN_SEL_M  (BIT(7))
-#define GPIO_SIG248_IN_SEL_V  0x1
-#define GPIO_SIG248_IN_SEL_S  7
-/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC248_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC248_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC248_IN_INV_SEL_V  0x1
-#define GPIO_FUNC248_IN_INV_SEL_S  6
-/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC248_IN_SEL    0x0000003F
-#define GPIO_FUNC248_IN_SEL_M  ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S))
-#define GPIO_FUNC248_IN_SEL_V  0x3F
-#define GPIO_FUNC248_IN_SEL_S  0
-
-#define GPIO_FUNC249_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x538)
-/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG249_IN_SEL    (BIT(7))
-#define GPIO_SIG249_IN_SEL_M  (BIT(7))
-#define GPIO_SIG249_IN_SEL_V  0x1
-#define GPIO_SIG249_IN_SEL_S  7
-/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC249_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC249_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC249_IN_INV_SEL_V  0x1
-#define GPIO_FUNC249_IN_INV_SEL_S  6
-/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC249_IN_SEL    0x0000003F
-#define GPIO_FUNC249_IN_SEL_M  ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S))
-#define GPIO_FUNC249_IN_SEL_V  0x3F
-#define GPIO_FUNC249_IN_SEL_S  0
-
-#define GPIO_FUNC250_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x53C)
-/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG250_IN_SEL    (BIT(7))
-#define GPIO_SIG250_IN_SEL_M  (BIT(7))
-#define GPIO_SIG250_IN_SEL_V  0x1
-#define GPIO_SIG250_IN_SEL_S  7
-/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC250_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC250_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC250_IN_INV_SEL_V  0x1
-#define GPIO_FUNC250_IN_INV_SEL_S  6
-/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC250_IN_SEL    0x0000003F
-#define GPIO_FUNC250_IN_SEL_M  ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S))
-#define GPIO_FUNC250_IN_SEL_V  0x3F
-#define GPIO_FUNC250_IN_SEL_S  0
-
-#define GPIO_FUNC251_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x540)
-/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG251_IN_SEL    (BIT(7))
-#define GPIO_SIG251_IN_SEL_M  (BIT(7))
-#define GPIO_SIG251_IN_SEL_V  0x1
-#define GPIO_SIG251_IN_SEL_S  7
-/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC251_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC251_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC251_IN_INV_SEL_V  0x1
-#define GPIO_FUNC251_IN_INV_SEL_S  6
-/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC251_IN_SEL    0x0000003F
-#define GPIO_FUNC251_IN_SEL_M  ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S))
-#define GPIO_FUNC251_IN_SEL_V  0x3F
-#define GPIO_FUNC251_IN_SEL_S  0
-
-#define GPIO_FUNC252_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x544)
-/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG252_IN_SEL    (BIT(7))
-#define GPIO_SIG252_IN_SEL_M  (BIT(7))
-#define GPIO_SIG252_IN_SEL_V  0x1
-#define GPIO_SIG252_IN_SEL_S  7
-/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC252_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC252_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC252_IN_INV_SEL_V  0x1
-#define GPIO_FUNC252_IN_INV_SEL_S  6
-/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC252_IN_SEL    0x0000003F
-#define GPIO_FUNC252_IN_SEL_M  ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S))
-#define GPIO_FUNC252_IN_SEL_V  0x3F
-#define GPIO_FUNC252_IN_SEL_S  0
-
-#define GPIO_FUNC253_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x548)
-/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG253_IN_SEL    (BIT(7))
-#define GPIO_SIG253_IN_SEL_M  (BIT(7))
-#define GPIO_SIG253_IN_SEL_V  0x1
-#define GPIO_SIG253_IN_SEL_S  7
-/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC253_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC253_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC253_IN_INV_SEL_V  0x1
-#define GPIO_FUNC253_IN_INV_SEL_S  6
-/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC253_IN_SEL    0x0000003F
-#define GPIO_FUNC253_IN_SEL_M  ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S))
-#define GPIO_FUNC253_IN_SEL_V  0x3F
-#define GPIO_FUNC253_IN_SEL_S  0
-
-#define GPIO_FUNC254_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x54C)
-/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG254_IN_SEL    (BIT(7))
-#define GPIO_SIG254_IN_SEL_M  (BIT(7))
-#define GPIO_SIG254_IN_SEL_V  0x1
-#define GPIO_SIG254_IN_SEL_S  7
-/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC254_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC254_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC254_IN_INV_SEL_V  0x1
-#define GPIO_FUNC254_IN_INV_SEL_S  6
-/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC254_IN_SEL    0x0000003F
-#define GPIO_FUNC254_IN_SEL_M  ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S))
-#define GPIO_FUNC254_IN_SEL_V  0x3F
-#define GPIO_FUNC254_IN_SEL_S  0
-
-#define GPIO_FUNC255_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x550)
-/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SIG255_IN_SEL    (BIT(7))
-#define GPIO_SIG255_IN_SEL_M  (BIT(7))
-#define GPIO_SIG255_IN_SEL_V  0x1
-#define GPIO_SIG255_IN_SEL_S  7
-/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC255_IN_INV_SEL    (BIT(6))
-#define GPIO_FUNC255_IN_INV_SEL_M  (BIT(6))
-#define GPIO_FUNC255_IN_INV_SEL_V  0x1
-#define GPIO_FUNC255_IN_INV_SEL_S  6
-/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
-/*description: .*/
-#define GPIO_FUNC255_IN_SEL    0x0000003F
-#define GPIO_FUNC255_IN_SEL_M  ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S))
-#define GPIO_FUNC255_IN_SEL_V  0x3F
-#define GPIO_FUNC255_IN_SEL_S  0
-
-#define GPIO_FUNC0_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x554)
-/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC0_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC0_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC0_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC0_OEN_INV_SEL_S  11
-/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC0_OEN_SEL    (BIT(10))
-#define GPIO_FUNC0_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC0_OEN_SEL_V  0x1
-#define GPIO_FUNC0_OEN_SEL_S  10
-/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC0_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC0_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC0_OUT_INV_SEL_S  9
-/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC0_OUT_SEL    0x000001FF
-#define GPIO_FUNC0_OUT_SEL_M  ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
-#define GPIO_FUNC0_OUT_SEL_V  0x1FF
-#define GPIO_FUNC0_OUT_SEL_S  0
-
-#define GPIO_FUNC1_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x558)
-/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC1_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC1_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC1_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC1_OEN_INV_SEL_S  11
-/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC1_OEN_SEL    (BIT(10))
-#define GPIO_FUNC1_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC1_OEN_SEL_V  0x1
-#define GPIO_FUNC1_OEN_SEL_S  10
-/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC1_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC1_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC1_OUT_INV_SEL_S  9
-/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC1_OUT_SEL    0x000001FF
-#define GPIO_FUNC1_OUT_SEL_M  ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
-#define GPIO_FUNC1_OUT_SEL_V  0x1FF
-#define GPIO_FUNC1_OUT_SEL_S  0
-
-#define GPIO_FUNC2_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x55C)
-/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC2_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC2_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC2_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC2_OEN_INV_SEL_S  11
-/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC2_OEN_SEL    (BIT(10))
-#define GPIO_FUNC2_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC2_OEN_SEL_V  0x1
-#define GPIO_FUNC2_OEN_SEL_S  10
-/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC2_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC2_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC2_OUT_INV_SEL_S  9
-/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC2_OUT_SEL    0x000001FF
-#define GPIO_FUNC2_OUT_SEL_M  ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
-#define GPIO_FUNC2_OUT_SEL_V  0x1FF
-#define GPIO_FUNC2_OUT_SEL_S  0
-
-#define GPIO_FUNC3_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x560)
-/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC3_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC3_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC3_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC3_OEN_INV_SEL_S  11
-/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC3_OEN_SEL    (BIT(10))
-#define GPIO_FUNC3_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC3_OEN_SEL_V  0x1
-#define GPIO_FUNC3_OEN_SEL_S  10
-/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC3_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC3_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC3_OUT_INV_SEL_S  9
-/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC3_OUT_SEL    0x000001FF
-#define GPIO_FUNC3_OUT_SEL_M  ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
-#define GPIO_FUNC3_OUT_SEL_V  0x1FF
-#define GPIO_FUNC3_OUT_SEL_S  0
-
-#define GPIO_FUNC4_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x564)
-/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC4_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC4_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC4_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC4_OEN_INV_SEL_S  11
-/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC4_OEN_SEL    (BIT(10))
-#define GPIO_FUNC4_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC4_OEN_SEL_V  0x1
-#define GPIO_FUNC4_OEN_SEL_S  10
-/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC4_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC4_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC4_OUT_INV_SEL_S  9
-/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC4_OUT_SEL    0x000001FF
-#define GPIO_FUNC4_OUT_SEL_M  ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
-#define GPIO_FUNC4_OUT_SEL_V  0x1FF
-#define GPIO_FUNC4_OUT_SEL_S  0
-
-#define GPIO_FUNC5_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x568)
-/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC5_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC5_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC5_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC5_OEN_INV_SEL_S  11
-/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC5_OEN_SEL    (BIT(10))
-#define GPIO_FUNC5_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC5_OEN_SEL_V  0x1
-#define GPIO_FUNC5_OEN_SEL_S  10
-/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC5_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC5_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC5_OUT_INV_SEL_S  9
-/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC5_OUT_SEL    0x000001FF
-#define GPIO_FUNC5_OUT_SEL_M  ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
-#define GPIO_FUNC5_OUT_SEL_V  0x1FF
-#define GPIO_FUNC5_OUT_SEL_S  0
-
-#define GPIO_FUNC6_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x56C)
-/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC6_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC6_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC6_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC6_OEN_INV_SEL_S  11
-/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC6_OEN_SEL    (BIT(10))
-#define GPIO_FUNC6_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC6_OEN_SEL_V  0x1
-#define GPIO_FUNC6_OEN_SEL_S  10
-/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC6_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC6_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC6_OUT_INV_SEL_S  9
-/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC6_OUT_SEL    0x000001FF
-#define GPIO_FUNC6_OUT_SEL_M  ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
-#define GPIO_FUNC6_OUT_SEL_V  0x1FF
-#define GPIO_FUNC6_OUT_SEL_S  0
-
-#define GPIO_FUNC7_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x570)
-/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC7_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC7_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC7_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC7_OEN_INV_SEL_S  11
-/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC7_OEN_SEL    (BIT(10))
-#define GPIO_FUNC7_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC7_OEN_SEL_V  0x1
-#define GPIO_FUNC7_OEN_SEL_S  10
-/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC7_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC7_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC7_OUT_INV_SEL_S  9
-/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC7_OUT_SEL    0x000001FF
-#define GPIO_FUNC7_OUT_SEL_M  ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
-#define GPIO_FUNC7_OUT_SEL_V  0x1FF
-#define GPIO_FUNC7_OUT_SEL_S  0
-
-#define GPIO_FUNC8_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x574)
-/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC8_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC8_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC8_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC8_OEN_INV_SEL_S  11
-/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC8_OEN_SEL    (BIT(10))
-#define GPIO_FUNC8_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC8_OEN_SEL_V  0x1
-#define GPIO_FUNC8_OEN_SEL_S  10
-/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC8_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC8_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC8_OUT_INV_SEL_S  9
-/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC8_OUT_SEL    0x000001FF
-#define GPIO_FUNC8_OUT_SEL_M  ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
-#define GPIO_FUNC8_OUT_SEL_V  0x1FF
-#define GPIO_FUNC8_OUT_SEL_S  0
-
-#define GPIO_FUNC9_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x578)
-/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC9_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC9_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC9_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC9_OEN_INV_SEL_S  11
-/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC9_OEN_SEL    (BIT(10))
-#define GPIO_FUNC9_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC9_OEN_SEL_V  0x1
-#define GPIO_FUNC9_OEN_SEL_S  10
-/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC9_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC9_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC9_OUT_INV_SEL_S  9
-/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC9_OUT_SEL    0x000001FF
-#define GPIO_FUNC9_OUT_SEL_M  ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
-#define GPIO_FUNC9_OUT_SEL_V  0x1FF
-#define GPIO_FUNC9_OUT_SEL_S  0
-
-#define GPIO_FUNC10_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x57C)
-/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC10_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC10_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC10_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC10_OEN_INV_SEL_S  11
-/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC10_OEN_SEL    (BIT(10))
-#define GPIO_FUNC10_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC10_OEN_SEL_V  0x1
-#define GPIO_FUNC10_OEN_SEL_S  10
-/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC10_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC10_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC10_OUT_INV_SEL_S  9
-/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC10_OUT_SEL    0x000001FF
-#define GPIO_FUNC10_OUT_SEL_M  ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
-#define GPIO_FUNC10_OUT_SEL_V  0x1FF
-#define GPIO_FUNC10_OUT_SEL_S  0
-
-#define GPIO_FUNC11_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x580)
-/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC11_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC11_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC11_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC11_OEN_INV_SEL_S  11
-/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC11_OEN_SEL    (BIT(10))
-#define GPIO_FUNC11_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC11_OEN_SEL_V  0x1
-#define GPIO_FUNC11_OEN_SEL_S  10
-/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC11_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC11_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC11_OUT_INV_SEL_S  9
-/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC11_OUT_SEL    0x000001FF
-#define GPIO_FUNC11_OUT_SEL_M  ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
-#define GPIO_FUNC11_OUT_SEL_V  0x1FF
-#define GPIO_FUNC11_OUT_SEL_S  0
-
-#define GPIO_FUNC12_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x584)
-/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC12_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC12_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC12_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC12_OEN_INV_SEL_S  11
-/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC12_OEN_SEL    (BIT(10))
-#define GPIO_FUNC12_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC12_OEN_SEL_V  0x1
-#define GPIO_FUNC12_OEN_SEL_S  10
-/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC12_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC12_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC12_OUT_INV_SEL_S  9
-/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC12_OUT_SEL    0x000001FF
-#define GPIO_FUNC12_OUT_SEL_M  ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
-#define GPIO_FUNC12_OUT_SEL_V  0x1FF
-#define GPIO_FUNC12_OUT_SEL_S  0
-
-#define GPIO_FUNC13_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x588)
-/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC13_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC13_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC13_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC13_OEN_INV_SEL_S  11
-/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC13_OEN_SEL    (BIT(10))
-#define GPIO_FUNC13_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC13_OEN_SEL_V  0x1
-#define GPIO_FUNC13_OEN_SEL_S  10
-/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC13_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC13_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC13_OUT_INV_SEL_S  9
-/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC13_OUT_SEL    0x000001FF
-#define GPIO_FUNC13_OUT_SEL_M  ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
-#define GPIO_FUNC13_OUT_SEL_V  0x1FF
-#define GPIO_FUNC13_OUT_SEL_S  0
-
-#define GPIO_FUNC14_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x58C)
-/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC14_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC14_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC14_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC14_OEN_INV_SEL_S  11
-/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC14_OEN_SEL    (BIT(10))
-#define GPIO_FUNC14_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC14_OEN_SEL_V  0x1
-#define GPIO_FUNC14_OEN_SEL_S  10
-/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC14_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC14_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC14_OUT_INV_SEL_S  9
-/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC14_OUT_SEL    0x000001FF
-#define GPIO_FUNC14_OUT_SEL_M  ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
-#define GPIO_FUNC14_OUT_SEL_V  0x1FF
-#define GPIO_FUNC14_OUT_SEL_S  0
-
-#define GPIO_FUNC15_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x590)
-/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC15_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC15_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC15_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC15_OEN_INV_SEL_S  11
-/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC15_OEN_SEL    (BIT(10))
-#define GPIO_FUNC15_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC15_OEN_SEL_V  0x1
-#define GPIO_FUNC15_OEN_SEL_S  10
-/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC15_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC15_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC15_OUT_INV_SEL_S  9
-/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC15_OUT_SEL    0x000001FF
-#define GPIO_FUNC15_OUT_SEL_M  ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
-#define GPIO_FUNC15_OUT_SEL_V  0x1FF
-#define GPIO_FUNC15_OUT_SEL_S  0
-
-#define GPIO_FUNC16_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x594)
-/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC16_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC16_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC16_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC16_OEN_INV_SEL_S  11
-/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC16_OEN_SEL    (BIT(10))
-#define GPIO_FUNC16_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC16_OEN_SEL_V  0x1
-#define GPIO_FUNC16_OEN_SEL_S  10
-/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC16_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC16_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC16_OUT_INV_SEL_S  9
-/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC16_OUT_SEL    0x000001FF
-#define GPIO_FUNC16_OUT_SEL_M  ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
-#define GPIO_FUNC16_OUT_SEL_V  0x1FF
-#define GPIO_FUNC16_OUT_SEL_S  0
-
-#define GPIO_FUNC17_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x598)
-/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC17_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC17_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC17_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC17_OEN_INV_SEL_S  11
-/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC17_OEN_SEL    (BIT(10))
-#define GPIO_FUNC17_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC17_OEN_SEL_V  0x1
-#define GPIO_FUNC17_OEN_SEL_S  10
-/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC17_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC17_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC17_OUT_INV_SEL_S  9
-/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC17_OUT_SEL    0x000001FF
-#define GPIO_FUNC17_OUT_SEL_M  ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
-#define GPIO_FUNC17_OUT_SEL_V  0x1FF
-#define GPIO_FUNC17_OUT_SEL_S  0
-
-#define GPIO_FUNC18_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x59C)
-/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC18_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC18_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC18_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC18_OEN_INV_SEL_S  11
-/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC18_OEN_SEL    (BIT(10))
-#define GPIO_FUNC18_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC18_OEN_SEL_V  0x1
-#define GPIO_FUNC18_OEN_SEL_S  10
-/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC18_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC18_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC18_OUT_INV_SEL_S  9
-/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC18_OUT_SEL    0x000001FF
-#define GPIO_FUNC18_OUT_SEL_M  ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
-#define GPIO_FUNC18_OUT_SEL_V  0x1FF
-#define GPIO_FUNC18_OUT_SEL_S  0
-
-#define GPIO_FUNC19_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A0)
-/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC19_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC19_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC19_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC19_OEN_INV_SEL_S  11
-/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC19_OEN_SEL    (BIT(10))
-#define GPIO_FUNC19_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC19_OEN_SEL_V  0x1
-#define GPIO_FUNC19_OEN_SEL_S  10
-/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC19_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC19_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC19_OUT_INV_SEL_S  9
-/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC19_OUT_SEL    0x000001FF
-#define GPIO_FUNC19_OUT_SEL_M  ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
-#define GPIO_FUNC19_OUT_SEL_V  0x1FF
-#define GPIO_FUNC19_OUT_SEL_S  0
-
-#define GPIO_FUNC20_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A4)
-/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC20_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC20_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC20_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC20_OEN_INV_SEL_S  11
-/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC20_OEN_SEL    (BIT(10))
-#define GPIO_FUNC20_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC20_OEN_SEL_V  0x1
-#define GPIO_FUNC20_OEN_SEL_S  10
-/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC20_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC20_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC20_OUT_INV_SEL_S  9
-/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC20_OUT_SEL    0x000001FF
-#define GPIO_FUNC20_OUT_SEL_M  ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
-#define GPIO_FUNC20_OUT_SEL_V  0x1FF
-#define GPIO_FUNC20_OUT_SEL_S  0
-
-#define GPIO_FUNC21_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A8)
-/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC21_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC21_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC21_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC21_OEN_INV_SEL_S  11
-/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC21_OEN_SEL    (BIT(10))
-#define GPIO_FUNC21_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC21_OEN_SEL_V  0x1
-#define GPIO_FUNC21_OEN_SEL_S  10
-/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC21_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC21_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC21_OUT_INV_SEL_S  9
-/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC21_OUT_SEL    0x000001FF
-#define GPIO_FUNC21_OUT_SEL_M  ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
-#define GPIO_FUNC21_OUT_SEL_V  0x1FF
-#define GPIO_FUNC21_OUT_SEL_S  0
-
-#define GPIO_FUNC22_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5AC)
-/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC22_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC22_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC22_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC22_OEN_INV_SEL_S  11
-/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC22_OEN_SEL    (BIT(10))
-#define GPIO_FUNC22_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC22_OEN_SEL_V  0x1
-#define GPIO_FUNC22_OEN_SEL_S  10
-/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC22_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC22_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC22_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC22_OUT_INV_SEL_S  9
-/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC22_OUT_SEL    0x000001FF
-#define GPIO_FUNC22_OUT_SEL_M  ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
-#define GPIO_FUNC22_OUT_SEL_V  0x1FF
-#define GPIO_FUNC22_OUT_SEL_S  0
-
-#define GPIO_FUNC23_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B0)
-/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC23_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC23_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC23_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC23_OEN_INV_SEL_S  11
-/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC23_OEN_SEL    (BIT(10))
-#define GPIO_FUNC23_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC23_OEN_SEL_V  0x1
-#define GPIO_FUNC23_OEN_SEL_S  10
-/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC23_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC23_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC23_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC23_OUT_INV_SEL_S  9
-/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC23_OUT_SEL    0x000001FF
-#define GPIO_FUNC23_OUT_SEL_M  ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
-#define GPIO_FUNC23_OUT_SEL_V  0x1FF
-#define GPIO_FUNC23_OUT_SEL_S  0
-
-#define GPIO_FUNC24_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B4)
-/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC24_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC24_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC24_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC24_OEN_INV_SEL_S  11
-/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC24_OEN_SEL    (BIT(10))
-#define GPIO_FUNC24_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC24_OEN_SEL_V  0x1
-#define GPIO_FUNC24_OEN_SEL_S  10
-/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC24_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC24_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC24_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC24_OUT_INV_SEL_S  9
-/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC24_OUT_SEL    0x000001FF
-#define GPIO_FUNC24_OUT_SEL_M  ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
-#define GPIO_FUNC24_OUT_SEL_V  0x1FF
-#define GPIO_FUNC24_OUT_SEL_S  0
-
-#define GPIO_FUNC25_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B8)
-/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC25_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC25_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC25_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC25_OEN_INV_SEL_S  11
-/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC25_OEN_SEL    (BIT(10))
-#define GPIO_FUNC25_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC25_OEN_SEL_V  0x1
-#define GPIO_FUNC25_OEN_SEL_S  10
-/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC25_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC25_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC25_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC25_OUT_INV_SEL_S  9
-/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC25_OUT_SEL    0x000001FF
-#define GPIO_FUNC25_OUT_SEL_M  ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
-#define GPIO_FUNC25_OUT_SEL_V  0x1FF
-#define GPIO_FUNC25_OUT_SEL_S  0
-
-#define GPIO_FUNC26_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5BC)
-/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC26_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC26_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC26_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC26_OEN_INV_SEL_S  11
-/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC26_OEN_SEL    (BIT(10))
-#define GPIO_FUNC26_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC26_OEN_SEL_V  0x1
-#define GPIO_FUNC26_OEN_SEL_S  10
-/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC26_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC26_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC26_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC26_OUT_INV_SEL_S  9
-/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC26_OUT_SEL    0x000001FF
-#define GPIO_FUNC26_OUT_SEL_M  ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S))
-#define GPIO_FUNC26_OUT_SEL_V  0x1FF
-#define GPIO_FUNC26_OUT_SEL_S  0
-
-#define GPIO_FUNC27_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C0)
-/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC27_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC27_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC27_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC27_OEN_INV_SEL_S  11
-/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC27_OEN_SEL    (BIT(10))
-#define GPIO_FUNC27_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC27_OEN_SEL_V  0x1
-#define GPIO_FUNC27_OEN_SEL_S  10
-/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC27_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC27_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC27_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC27_OUT_INV_SEL_S  9
-/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC27_OUT_SEL    0x000001FF
-#define GPIO_FUNC27_OUT_SEL_M  ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S))
-#define GPIO_FUNC27_OUT_SEL_V  0x1FF
-#define GPIO_FUNC27_OUT_SEL_S  0
-
-#define GPIO_FUNC28_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C4)
-/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC28_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC28_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC28_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC28_OEN_INV_SEL_S  11
-/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC28_OEN_SEL    (BIT(10))
-#define GPIO_FUNC28_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC28_OEN_SEL_V  0x1
-#define GPIO_FUNC28_OEN_SEL_S  10
-/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC28_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC28_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC28_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC28_OUT_INV_SEL_S  9
-/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC28_OUT_SEL    0x000001FF
-#define GPIO_FUNC28_OUT_SEL_M  ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S))
-#define GPIO_FUNC28_OUT_SEL_V  0x1FF
-#define GPIO_FUNC28_OUT_SEL_S  0
-
-#define GPIO_FUNC29_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C8)
-/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC29_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC29_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC29_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC29_OEN_INV_SEL_S  11
-/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC29_OEN_SEL    (BIT(10))
-#define GPIO_FUNC29_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC29_OEN_SEL_V  0x1
-#define GPIO_FUNC29_OEN_SEL_S  10
-/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC29_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC29_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC29_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC29_OUT_INV_SEL_S  9
-/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC29_OUT_SEL    0x000001FF
-#define GPIO_FUNC29_OUT_SEL_M  ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S))
-#define GPIO_FUNC29_OUT_SEL_V  0x1FF
-#define GPIO_FUNC29_OUT_SEL_S  0
-
-#define GPIO_FUNC30_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5CC)
-/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC30_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC30_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC30_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC30_OEN_INV_SEL_S  11
-/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC30_OEN_SEL    (BIT(10))
-#define GPIO_FUNC30_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC30_OEN_SEL_V  0x1
-#define GPIO_FUNC30_OEN_SEL_S  10
-/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC30_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC30_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC30_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC30_OUT_INV_SEL_S  9
-/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC30_OUT_SEL    0x000001FF
-#define GPIO_FUNC30_OUT_SEL_M  ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S))
-#define GPIO_FUNC30_OUT_SEL_V  0x1FF
-#define GPIO_FUNC30_OUT_SEL_S  0
-
-#define GPIO_FUNC31_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D0)
-/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC31_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC31_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC31_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC31_OEN_INV_SEL_S  11
-/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC31_OEN_SEL    (BIT(10))
-#define GPIO_FUNC31_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC31_OEN_SEL_V  0x1
-#define GPIO_FUNC31_OEN_SEL_S  10
-/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC31_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC31_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC31_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC31_OUT_INV_SEL_S  9
-/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC31_OUT_SEL    0x000001FF
-#define GPIO_FUNC31_OUT_SEL_M  ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S))
-#define GPIO_FUNC31_OUT_SEL_V  0x1FF
-#define GPIO_FUNC31_OUT_SEL_S  0
-
-#define GPIO_FUNC32_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D4)
-/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC32_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC32_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC32_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC32_OEN_INV_SEL_S  11
-/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC32_OEN_SEL    (BIT(10))
-#define GPIO_FUNC32_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC32_OEN_SEL_V  0x1
-#define GPIO_FUNC32_OEN_SEL_S  10
-/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC32_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC32_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC32_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC32_OUT_INV_SEL_S  9
-/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC32_OUT_SEL    0x000001FF
-#define GPIO_FUNC32_OUT_SEL_M  ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S))
-#define GPIO_FUNC32_OUT_SEL_V  0x1FF
-#define GPIO_FUNC32_OUT_SEL_S  0
-
-#define GPIO_FUNC33_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D8)
-/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC33_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC33_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC33_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC33_OEN_INV_SEL_S  11
-/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC33_OEN_SEL    (BIT(10))
-#define GPIO_FUNC33_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC33_OEN_SEL_V  0x1
-#define GPIO_FUNC33_OEN_SEL_S  10
-/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC33_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC33_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC33_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC33_OUT_INV_SEL_S  9
-/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC33_OUT_SEL    0x000001FF
-#define GPIO_FUNC33_OUT_SEL_M  ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S))
-#define GPIO_FUNC33_OUT_SEL_V  0x1FF
-#define GPIO_FUNC33_OUT_SEL_S  0
-
-#define GPIO_FUNC34_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5DC)
-/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC34_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC34_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC34_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC34_OEN_INV_SEL_S  11
-/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC34_OEN_SEL    (BIT(10))
-#define GPIO_FUNC34_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC34_OEN_SEL_V  0x1
-#define GPIO_FUNC34_OEN_SEL_S  10
-/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC34_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC34_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC34_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC34_OUT_INV_SEL_S  9
-/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC34_OUT_SEL    0x000001FF
-#define GPIO_FUNC34_OUT_SEL_M  ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S))
-#define GPIO_FUNC34_OUT_SEL_V  0x1FF
-#define GPIO_FUNC34_OUT_SEL_S  0
-
-#define GPIO_FUNC35_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E0)
-/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC35_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC35_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC35_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC35_OEN_INV_SEL_S  11
-/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC35_OEN_SEL    (BIT(10))
-#define GPIO_FUNC35_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC35_OEN_SEL_V  0x1
-#define GPIO_FUNC35_OEN_SEL_S  10
-/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC35_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC35_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC35_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC35_OUT_INV_SEL_S  9
-/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC35_OUT_SEL    0x000001FF
-#define GPIO_FUNC35_OUT_SEL_M  ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S))
-#define GPIO_FUNC35_OUT_SEL_V  0x1FF
-#define GPIO_FUNC35_OUT_SEL_S  0
-
-#define GPIO_FUNC36_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E4)
-/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC36_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC36_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC36_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC36_OEN_INV_SEL_S  11
-/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC36_OEN_SEL    (BIT(10))
-#define GPIO_FUNC36_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC36_OEN_SEL_V  0x1
-#define GPIO_FUNC36_OEN_SEL_S  10
-/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC36_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC36_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC36_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC36_OUT_INV_SEL_S  9
-/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC36_OUT_SEL    0x000001FF
-#define GPIO_FUNC36_OUT_SEL_M  ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S))
-#define GPIO_FUNC36_OUT_SEL_V  0x1FF
-#define GPIO_FUNC36_OUT_SEL_S  0
-
-#define GPIO_FUNC37_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E8)
-/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC37_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC37_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC37_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC37_OEN_INV_SEL_S  11
-/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC37_OEN_SEL    (BIT(10))
-#define GPIO_FUNC37_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC37_OEN_SEL_V  0x1
-#define GPIO_FUNC37_OEN_SEL_S  10
-/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC37_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC37_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC37_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC37_OUT_INV_SEL_S  9
-/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC37_OUT_SEL    0x000001FF
-#define GPIO_FUNC37_OUT_SEL_M  ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S))
-#define GPIO_FUNC37_OUT_SEL_V  0x1FF
-#define GPIO_FUNC37_OUT_SEL_S  0
-
-#define GPIO_FUNC38_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5EC)
-/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC38_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC38_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC38_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC38_OEN_INV_SEL_S  11
-/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC38_OEN_SEL    (BIT(10))
-#define GPIO_FUNC38_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC38_OEN_SEL_V  0x1
-#define GPIO_FUNC38_OEN_SEL_S  10
-/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC38_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC38_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC38_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC38_OUT_INV_SEL_S  9
-/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC38_OUT_SEL    0x000001FF
-#define GPIO_FUNC38_OUT_SEL_M  ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S))
-#define GPIO_FUNC38_OUT_SEL_V  0x1FF
-#define GPIO_FUNC38_OUT_SEL_S  0
-
-#define GPIO_FUNC39_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F0)
-/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC39_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC39_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC39_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC39_OEN_INV_SEL_S  11
-/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC39_OEN_SEL    (BIT(10))
-#define GPIO_FUNC39_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC39_OEN_SEL_V  0x1
-#define GPIO_FUNC39_OEN_SEL_S  10
-/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC39_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC39_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC39_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC39_OUT_INV_SEL_S  9
-/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC39_OUT_SEL    0x000001FF
-#define GPIO_FUNC39_OUT_SEL_M  ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S))
-#define GPIO_FUNC39_OUT_SEL_V  0x1FF
-#define GPIO_FUNC39_OUT_SEL_S  0
-
-#define GPIO_FUNC40_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F4)
-/* GPIO_FUNC40_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC40_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC40_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC40_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC40_OEN_INV_SEL_S  11
-/* GPIO_FUNC40_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC40_OEN_SEL    (BIT(10))
-#define GPIO_FUNC40_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC40_OEN_SEL_V  0x1
-#define GPIO_FUNC40_OEN_SEL_S  10
-/* GPIO_FUNC40_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC40_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC40_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC40_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC40_OUT_INV_SEL_S  9
-/* GPIO_FUNC40_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC40_OUT_SEL    0x000001FF
-#define GPIO_FUNC40_OUT_SEL_M  ((GPIO_FUNC40_OUT_SEL_V)<<(GPIO_FUNC40_OUT_SEL_S))
-#define GPIO_FUNC40_OUT_SEL_V  0x1FF
-#define GPIO_FUNC40_OUT_SEL_S  0
-
-#define GPIO_FUNC41_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F8)
-/* GPIO_FUNC41_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC41_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC41_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC41_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC41_OEN_INV_SEL_S  11
-/* GPIO_FUNC41_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC41_OEN_SEL    (BIT(10))
-#define GPIO_FUNC41_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC41_OEN_SEL_V  0x1
-#define GPIO_FUNC41_OEN_SEL_S  10
-/* GPIO_FUNC41_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC41_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC41_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC41_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC41_OUT_INV_SEL_S  9
-/* GPIO_FUNC41_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC41_OUT_SEL    0x000001FF
-#define GPIO_FUNC41_OUT_SEL_M  ((GPIO_FUNC41_OUT_SEL_V)<<(GPIO_FUNC41_OUT_SEL_S))
-#define GPIO_FUNC41_OUT_SEL_V  0x1FF
-#define GPIO_FUNC41_OUT_SEL_S  0
-
-#define GPIO_FUNC42_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5FC)
-/* GPIO_FUNC42_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC42_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC42_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC42_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC42_OEN_INV_SEL_S  11
-/* GPIO_FUNC42_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC42_OEN_SEL    (BIT(10))
-#define GPIO_FUNC42_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC42_OEN_SEL_V  0x1
-#define GPIO_FUNC42_OEN_SEL_S  10
-/* GPIO_FUNC42_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC42_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC42_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC42_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC42_OUT_INV_SEL_S  9
-/* GPIO_FUNC42_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC42_OUT_SEL    0x000001FF
-#define GPIO_FUNC42_OUT_SEL_M  ((GPIO_FUNC42_OUT_SEL_V)<<(GPIO_FUNC42_OUT_SEL_S))
-#define GPIO_FUNC42_OUT_SEL_V  0x1FF
-#define GPIO_FUNC42_OUT_SEL_S  0
-
-#define GPIO_FUNC43_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x600)
-/* GPIO_FUNC43_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC43_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC43_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC43_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC43_OEN_INV_SEL_S  11
-/* GPIO_FUNC43_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC43_OEN_SEL    (BIT(10))
-#define GPIO_FUNC43_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC43_OEN_SEL_V  0x1
-#define GPIO_FUNC43_OEN_SEL_S  10
-/* GPIO_FUNC43_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC43_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC43_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC43_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC43_OUT_INV_SEL_S  9
-/* GPIO_FUNC43_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC43_OUT_SEL    0x000001FF
-#define GPIO_FUNC43_OUT_SEL_M  ((GPIO_FUNC43_OUT_SEL_V)<<(GPIO_FUNC43_OUT_SEL_S))
-#define GPIO_FUNC43_OUT_SEL_V  0x1FF
-#define GPIO_FUNC43_OUT_SEL_S  0
-
-#define GPIO_FUNC44_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x604)
-/* GPIO_FUNC44_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC44_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC44_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC44_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC44_OEN_INV_SEL_S  11
-/* GPIO_FUNC44_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC44_OEN_SEL    (BIT(10))
-#define GPIO_FUNC44_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC44_OEN_SEL_V  0x1
-#define GPIO_FUNC44_OEN_SEL_S  10
-/* GPIO_FUNC44_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC44_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC44_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC44_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC44_OUT_INV_SEL_S  9
-/* GPIO_FUNC44_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC44_OUT_SEL    0x000001FF
-#define GPIO_FUNC44_OUT_SEL_M  ((GPIO_FUNC44_OUT_SEL_V)<<(GPIO_FUNC44_OUT_SEL_S))
-#define GPIO_FUNC44_OUT_SEL_V  0x1FF
-#define GPIO_FUNC44_OUT_SEL_S  0
-
-#define GPIO_FUNC45_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x608)
-/* GPIO_FUNC45_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC45_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC45_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC45_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC45_OEN_INV_SEL_S  11
-/* GPIO_FUNC45_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC45_OEN_SEL    (BIT(10))
-#define GPIO_FUNC45_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC45_OEN_SEL_V  0x1
-#define GPIO_FUNC45_OEN_SEL_S  10
-/* GPIO_FUNC45_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC45_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC45_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC45_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC45_OUT_INV_SEL_S  9
-/* GPIO_FUNC45_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC45_OUT_SEL    0x000001FF
-#define GPIO_FUNC45_OUT_SEL_M  ((GPIO_FUNC45_OUT_SEL_V)<<(GPIO_FUNC45_OUT_SEL_S))
-#define GPIO_FUNC45_OUT_SEL_V  0x1FF
-#define GPIO_FUNC45_OUT_SEL_S  0
-
-#define GPIO_FUNC46_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x60C)
-/* GPIO_FUNC46_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC46_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC46_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC46_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC46_OEN_INV_SEL_S  11
-/* GPIO_FUNC46_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC46_OEN_SEL    (BIT(10))
-#define GPIO_FUNC46_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC46_OEN_SEL_V  0x1
-#define GPIO_FUNC46_OEN_SEL_S  10
-/* GPIO_FUNC46_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC46_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC46_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC46_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC46_OUT_INV_SEL_S  9
-/* GPIO_FUNC46_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC46_OUT_SEL    0x000001FF
-#define GPIO_FUNC46_OUT_SEL_M  ((GPIO_FUNC46_OUT_SEL_V)<<(GPIO_FUNC46_OUT_SEL_S))
-#define GPIO_FUNC46_OUT_SEL_V  0x1FF
-#define GPIO_FUNC46_OUT_SEL_S  0
-
-#define GPIO_FUNC47_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x610)
-/* GPIO_FUNC47_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC47_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC47_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC47_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC47_OEN_INV_SEL_S  11
-/* GPIO_FUNC47_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC47_OEN_SEL    (BIT(10))
-#define GPIO_FUNC47_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC47_OEN_SEL_V  0x1
-#define GPIO_FUNC47_OEN_SEL_S  10
-/* GPIO_FUNC47_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC47_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC47_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC47_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC47_OUT_INV_SEL_S  9
-/* GPIO_FUNC47_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC47_OUT_SEL    0x000001FF
-#define GPIO_FUNC47_OUT_SEL_M  ((GPIO_FUNC47_OUT_SEL_V)<<(GPIO_FUNC47_OUT_SEL_S))
-#define GPIO_FUNC47_OUT_SEL_V  0x1FF
-#define GPIO_FUNC47_OUT_SEL_S  0
-
-#define GPIO_FUNC48_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x614)
-/* GPIO_FUNC48_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC48_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC48_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC48_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC48_OEN_INV_SEL_S  11
-/* GPIO_FUNC48_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC48_OEN_SEL    (BIT(10))
-#define GPIO_FUNC48_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC48_OEN_SEL_V  0x1
-#define GPIO_FUNC48_OEN_SEL_S  10
-/* GPIO_FUNC48_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC48_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC48_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC48_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC48_OUT_INV_SEL_S  9
-/* GPIO_FUNC48_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC48_OUT_SEL    0x000001FF
-#define GPIO_FUNC48_OUT_SEL_M  ((GPIO_FUNC48_OUT_SEL_V)<<(GPIO_FUNC48_OUT_SEL_S))
-#define GPIO_FUNC48_OUT_SEL_V  0x1FF
-#define GPIO_FUNC48_OUT_SEL_S  0
-
-#define GPIO_FUNC49_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x618)
-/* GPIO_FUNC49_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC49_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC49_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC49_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC49_OEN_INV_SEL_S  11
-/* GPIO_FUNC49_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC49_OEN_SEL    (BIT(10))
-#define GPIO_FUNC49_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC49_OEN_SEL_V  0x1
-#define GPIO_FUNC49_OEN_SEL_S  10
-/* GPIO_FUNC49_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC49_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC49_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC49_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC49_OUT_INV_SEL_S  9
-/* GPIO_FUNC49_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC49_OUT_SEL    0x000001FF
-#define GPIO_FUNC49_OUT_SEL_M  ((GPIO_FUNC49_OUT_SEL_V)<<(GPIO_FUNC49_OUT_SEL_S))
-#define GPIO_FUNC49_OUT_SEL_V  0x1FF
-#define GPIO_FUNC49_OUT_SEL_S  0
-
-#define GPIO_FUNC50_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x61C)
-/* GPIO_FUNC50_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC50_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC50_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC50_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC50_OEN_INV_SEL_S  11
-/* GPIO_FUNC50_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC50_OEN_SEL    (BIT(10))
-#define GPIO_FUNC50_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC50_OEN_SEL_V  0x1
-#define GPIO_FUNC50_OEN_SEL_S  10
-/* GPIO_FUNC50_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC50_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC50_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC50_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC50_OUT_INV_SEL_S  9
-/* GPIO_FUNC50_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC50_OUT_SEL    0x000001FF
-#define GPIO_FUNC50_OUT_SEL_M  ((GPIO_FUNC50_OUT_SEL_V)<<(GPIO_FUNC50_OUT_SEL_S))
-#define GPIO_FUNC50_OUT_SEL_V  0x1FF
-#define GPIO_FUNC50_OUT_SEL_S  0
-
-#define GPIO_FUNC51_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x620)
-/* GPIO_FUNC51_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC51_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC51_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC51_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC51_OEN_INV_SEL_S  11
-/* GPIO_FUNC51_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC51_OEN_SEL    (BIT(10))
-#define GPIO_FUNC51_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC51_OEN_SEL_V  0x1
-#define GPIO_FUNC51_OEN_SEL_S  10
-/* GPIO_FUNC51_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC51_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC51_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC51_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC51_OUT_INV_SEL_S  9
-/* GPIO_FUNC51_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC51_OUT_SEL    0x000001FF
-#define GPIO_FUNC51_OUT_SEL_M  ((GPIO_FUNC51_OUT_SEL_V)<<(GPIO_FUNC51_OUT_SEL_S))
-#define GPIO_FUNC51_OUT_SEL_V  0x1FF
-#define GPIO_FUNC51_OUT_SEL_S  0
-
-#define GPIO_FUNC52_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x624)
-/* GPIO_FUNC52_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC52_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC52_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC52_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC52_OEN_INV_SEL_S  11
-/* GPIO_FUNC52_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC52_OEN_SEL    (BIT(10))
-#define GPIO_FUNC52_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC52_OEN_SEL_V  0x1
-#define GPIO_FUNC52_OEN_SEL_S  10
-/* GPIO_FUNC52_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC52_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC52_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC52_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC52_OUT_INV_SEL_S  9
-/* GPIO_FUNC52_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC52_OUT_SEL    0x000001FF
-#define GPIO_FUNC52_OUT_SEL_M  ((GPIO_FUNC52_OUT_SEL_V)<<(GPIO_FUNC52_OUT_SEL_S))
-#define GPIO_FUNC52_OUT_SEL_V  0x1FF
-#define GPIO_FUNC52_OUT_SEL_S  0
-
-#define GPIO_FUNC53_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x628)
-/* GPIO_FUNC53_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC53_OEN_INV_SEL    (BIT(11))
-#define GPIO_FUNC53_OEN_INV_SEL_M  (BIT(11))
-#define GPIO_FUNC53_OEN_INV_SEL_V  0x1
-#define GPIO_FUNC53_OEN_INV_SEL_S  11
-/* GPIO_FUNC53_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC53_OEN_SEL    (BIT(10))
-#define GPIO_FUNC53_OEN_SEL_M  (BIT(10))
-#define GPIO_FUNC53_OEN_SEL_V  0x1
-#define GPIO_FUNC53_OEN_SEL_S  10
-/* GPIO_FUNC53_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_FUNC53_OUT_INV_SEL    (BIT(9))
-#define GPIO_FUNC53_OUT_INV_SEL_M  (BIT(9))
-#define GPIO_FUNC53_OUT_INV_SEL_V  0x1
-#define GPIO_FUNC53_OUT_INV_SEL_S  9
-/* GPIO_FUNC53_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
-/*description: .*/
-#define GPIO_FUNC53_OUT_SEL    0x000001FF
-#define GPIO_FUNC53_OUT_SEL_M  ((GPIO_FUNC53_OUT_SEL_V)<<(GPIO_FUNC53_OUT_SEL_S))
-#define GPIO_FUNC53_OUT_SEL_V  0x1FF
-#define GPIO_FUNC53_OUT_SEL_S  0
-
-#define GPIO_CLOCK_GATE_REG          (DR_REG_GPIO_BASE + 0x62C)
-/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define GPIO_CLK_EN    (BIT(0))
-#define GPIO_CLK_EN_M  (BIT(0))
-#define GPIO_CLK_EN_V  0x1
-#define GPIO_CLK_EN_S  0
-
-#define GPIO_DATE_REG          (DR_REG_GPIO_BASE + 0x6FC)
-/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1907040 ; */
-/*description: .*/
-#define GPIO_DATE    0x0FFFFFFF
-#define GPIO_DATE_M  ((GPIO_DATE_V)<<(GPIO_DATE_S))
-#define GPIO_DATE_V  0xFFFFFFF
-#define GPIO_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_GPIO_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/gpio_sd_reg.h b/components/soc/esp32s3/include/soc/gpio_sd_reg.h
deleted file mode 100644
index 4aa1fe8f86f..00000000000
--- a/components/soc/esp32s3/include/soc/gpio_sd_reg.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "soc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0)
-/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: .*/
-#define GPIO_SD0_PRESCALE    0x000000FF
-#define GPIO_SD0_PRESCALE_M  ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
-#define GPIO_SD0_PRESCALE_V  0xFF
-#define GPIO_SD0_PRESCALE_S  8
-/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SD0_IN    0x000000FF
-#define GPIO_SD0_IN_M  ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
-#define GPIO_SD0_IN_V  0xFF
-#define GPIO_SD0_IN_S  0
-
-#define GPIO_SIGMADELTA1_REG          (DR_REG_GPIO_SD_BASE + 0x4)
-/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: .*/
-#define GPIO_SD1_PRESCALE    0x000000FF
-#define GPIO_SD1_PRESCALE_M  ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
-#define GPIO_SD1_PRESCALE_V  0xFF
-#define GPIO_SD1_PRESCALE_S  8
-/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SD1_IN    0x000000FF
-#define GPIO_SD1_IN_M  ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
-#define GPIO_SD1_IN_V  0xFF
-#define GPIO_SD1_IN_S  0
-
-#define GPIO_SIGMADELTA2_REG          (DR_REG_GPIO_SD_BASE + 0x8)
-/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: .*/
-#define GPIO_SD2_PRESCALE    0x000000FF
-#define GPIO_SD2_PRESCALE_M  ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
-#define GPIO_SD2_PRESCALE_V  0xFF
-#define GPIO_SD2_PRESCALE_S  8
-/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SD2_IN    0x000000FF
-#define GPIO_SD2_IN_M  ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
-#define GPIO_SD2_IN_V  0xFF
-#define GPIO_SD2_IN_S  0
-
-#define GPIO_SIGMADELTA3_REG          (DR_REG_GPIO_SD_BASE + 0xC)
-/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: .*/
-#define GPIO_SD3_PRESCALE    0x000000FF
-#define GPIO_SD3_PRESCALE_M  ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
-#define GPIO_SD3_PRESCALE_V  0xFF
-#define GPIO_SD3_PRESCALE_S  8
-/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SD3_IN    0x000000FF
-#define GPIO_SD3_IN_M  ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
-#define GPIO_SD3_IN_V  0xFF
-#define GPIO_SD3_IN_S  0
-
-#define GPIO_SIGMADELTA4_REG          (DR_REG_GPIO_SD_BASE + 0x10)
-/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: .*/
-#define GPIO_SD4_PRESCALE    0x000000FF
-#define GPIO_SD4_PRESCALE_M  ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
-#define GPIO_SD4_PRESCALE_V  0xFF
-#define GPIO_SD4_PRESCALE_S  8
-/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SD4_IN    0x000000FF
-#define GPIO_SD4_IN_M  ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
-#define GPIO_SD4_IN_V  0xFF
-#define GPIO_SD4_IN_S  0
-
-#define GPIO_SIGMADELTA5_REG          (DR_REG_GPIO_SD_BASE + 0x14)
-/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: .*/
-#define GPIO_SD5_PRESCALE    0x000000FF
-#define GPIO_SD5_PRESCALE_M  ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
-#define GPIO_SD5_PRESCALE_V  0xFF
-#define GPIO_SD5_PRESCALE_S  8
-/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SD5_IN    0x000000FF
-#define GPIO_SD5_IN_M  ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
-#define GPIO_SD5_IN_V  0xFF
-#define GPIO_SD5_IN_S  0
-
-#define GPIO_SIGMADELTA6_REG          (DR_REG_GPIO_SD_BASE + 0x18)
-/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: .*/
-#define GPIO_SD6_PRESCALE    0x000000FF
-#define GPIO_SD6_PRESCALE_M  ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
-#define GPIO_SD6_PRESCALE_V  0xFF
-#define GPIO_SD6_PRESCALE_S  8
-/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SD6_IN    0x000000FF
-#define GPIO_SD6_IN_M  ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
-#define GPIO_SD6_IN_V  0xFF
-#define GPIO_SD6_IN_S  0
-
-#define GPIO_SIGMADELTA7_REG          (DR_REG_GPIO_SD_BASE + 0x1C)
-/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: .*/
-#define GPIO_SD7_PRESCALE    0x000000FF
-#define GPIO_SD7_PRESCALE_M  ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
-#define GPIO_SD7_PRESCALE_V  0xFF
-#define GPIO_SD7_PRESCALE_S  8
-/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define GPIO_SD7_IN    0x000000FF
-#define GPIO_SD7_IN_M  ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
-#define GPIO_SD7_IN_V  0xFF
-#define GPIO_SD7_IN_S  0
-
-#define GPIO_SIGMADELTA_CG_REG          (DR_REG_GPIO_SD_BASE + 0x20)
-/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SD_CLK_EN    (BIT(31))
-#define GPIO_SD_CLK_EN_M  (BIT(31))
-#define GPIO_SD_CLK_EN_V  0x1
-#define GPIO_SD_CLK_EN_S  31
-
-#define GPIO_SIGMADELTA_MISC_REG          (DR_REG_GPIO_SD_BASE + 0x24)
-/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define GPIO_SPI_SWAP    (BIT(31))
-#define GPIO_SPI_SWAP_M  (BIT(31))
-#define GPIO_SPI_SWAP_V  0x1
-#define GPIO_SPI_SWAP_S  31
-/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: .*/
-#define GPIO_FUNCTION_CLK_EN    (BIT(30))
-#define GPIO_FUNCTION_CLK_EN_M  (BIT(30))
-#define GPIO_FUNCTION_CLK_EN_V  0x1
-#define GPIO_FUNCTION_CLK_EN_S  30
-
-#define GPIO_SIGMADELTA_VERSION_REG          (DR_REG_GPIO_SD_BASE + 0x28)
-/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
-/*description: .*/
-#define GPIO_SD_DATE    0x0FFFFFFF
-#define GPIO_SD_DATE_M  ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
-#define GPIO_SD_DATE_V  0xFFFFFFF
-#define GPIO_SD_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/i2c_reg.h b/components/soc/esp32s3/include/soc/i2c_reg.h
deleted file mode 100644
index 5d19afa1c32..00000000000
--- a/components/soc/esp32s3/include/soc/i2c_reg.h
+++ /dev/null
@@ -1,1431 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** I2C_SCL_LOW_PERIOD_REG register
- *  Configures the low level width of the SCL
- *  Clock
- */
-#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
-/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
- *  This register is used to configure for how long SCL remains low in master mode, in
- *  I2C module clock cycles.
- */
-#define I2C_SCL_LOW_PERIOD    0x000001FFU
-#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
-#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
-#define I2C_SCL_LOW_PERIOD_S  0
-
-/** I2C_CTR_REG register
- *  Transmission setting
- */
-#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
-/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 1;
- *  0: direct output; 1: open drain output.
- */
-#define I2C_SDA_FORCE_OUT    (BIT(0))
-#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
-#define I2C_SDA_FORCE_OUT_V  0x00000001U
-#define I2C_SDA_FORCE_OUT_S  0
-/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 1;
- *  0: direct output; 1: open drain output.
- */
-#define I2C_SCL_FORCE_OUT    (BIT(1))
-#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
-#define I2C_SCL_FORCE_OUT_V  0x00000001U
-#define I2C_SCL_FORCE_OUT_S  1
-/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
- *  This register is used to select the sample mode.
- *  1: sample SDA data on the SCL low level.
- *  0: sample SDA data on the SCL high level.
- */
-#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
-#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
-#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
-#define I2C_SAMPLE_SCL_LEVEL_S  2
-/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
- *  This register is used to configure the ACK value that need to sent by master when
- *  the rx_fifo_cnt has reached the threshold.
- */
-#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
-#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
-#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
-#define I2C_RX_FULL_ACK_LEVEL_S  3
-/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
- *  Set this bit to configure the module as an I2C Master. Clear this bit to configure
- *  the
- *  module as an I2C Slave.
- */
-#define I2C_MS_MODE    (BIT(4))
-#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
-#define I2C_MS_MODE_V  0x00000001U
-#define I2C_MS_MODE_S  4
-/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
- *  Set this bit to start sending the data in txfifo.
- */
-#define I2C_TRANS_START    (BIT(5))
-#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
-#define I2C_TRANS_START_V  0x00000001U
-#define I2C_TRANS_START_S  5
-/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
- *  This bit is used to control the sending mode for data needing to be sent.
- *  1: send data from the least significant bit;
- *  0: send data from the most significant bit.
- */
-#define I2C_TX_LSB_FIRST    (BIT(6))
-#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
-#define I2C_TX_LSB_FIRST_V  0x00000001U
-#define I2C_TX_LSB_FIRST_S  6
-/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
- *  This bit is used to control the storage mode for received data.
- *  1: receive data from the least significant bit;
- *  0: receive data from the most significant bit.
- */
-#define I2C_RX_LSB_FIRST    (BIT(7))
-#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
-#define I2C_RX_LSB_FIRST_V  0x00000001U
-#define I2C_RX_LSB_FIRST_S  7
-/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
- *  Reserved
- */
-#define I2C_CLK_EN    (BIT(8))
-#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
-#define I2C_CLK_EN_V  0x00000001U
-#define I2C_CLK_EN_S  8
-/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
- *  This is the enable bit for arbitration_lost.
- */
-#define I2C_ARBITRATION_EN    (BIT(9))
-#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
-#define I2C_ARBITRATION_EN_V  0x00000001U
-#define I2C_ARBITRATION_EN_S  9
-/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
- *  This register is used to reset the scl FMS.
- */
-#define I2C_FSM_RST    (BIT(10))
-#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
-#define I2C_FSM_RST_V  0x00000001U
-#define I2C_FSM_RST_S  10
-/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
- *  synchronization bit
- */
-#define I2C_CONF_UPGATE    (BIT(11))
-#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
-#define I2C_CONF_UPGATE_V  0x00000001U
-#define I2C_CONF_UPGATE_S  11
-/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for slave to send data automatically
- */
-#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
-#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
-#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001U
-#define I2C_SLV_TX_AUTO_START_EN_S  12
-/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit to check if the r/w bit of 10bit addressing consists with
- *  I2C protocol
- */
-#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
-#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S)
-#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x00000001U
-#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
-/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit to support the 7bit general call function.
- */
-#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
-#define I2C_ADDR_BROADCASTING_EN_M  (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
-#define I2C_ADDR_BROADCASTING_EN_V  0x00000001U
-#define I2C_ADDR_BROADCASTING_EN_S  14
-
-/** I2C_SR_REG register
- *  Describe I2C work status.
- */
-#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
-/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
- *  The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
- */
-#define I2C_RESP_REC    (BIT(0))
-#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
-#define I2C_RESP_REC_V  0x00000001U
-#define I2C_RESP_REC_S  0
-/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
- *  When in slave mode, 1: master reads from slave; 0: master writes to slave.
- */
-#define I2C_SLAVE_RW    (BIT(1))
-#define I2C_SLAVE_RW_M  (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S)
-#define I2C_SLAVE_RW_V  0x00000001U
-#define I2C_SLAVE_RW_S  1
-/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
- *  When the I2C controller loses control of SCL line, this register changes to 1.
- */
-#define I2C_ARB_LOST    (BIT(3))
-#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
-#define I2C_ARB_LOST_V  0x00000001U
-#define I2C_ARB_LOST_S  3
-/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
- *  1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state.
- */
-#define I2C_BUS_BUSY    (BIT(4))
-#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
-#define I2C_BUS_BUSY_V  0x00000001U
-#define I2C_BUS_BUSY_S  4
-/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
- *  When configured as an I2C Slave, and the address sent by the master is
- *  equal to the address of the slave, then this bit will be of high level.
- */
-#define I2C_SLAVE_ADDRESSED    (BIT(5))
-#define I2C_SLAVE_ADDRESSED_M  (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
-#define I2C_SLAVE_ADDRESSED_V  0x00000001U
-#define I2C_SLAVE_ADDRESSED_S  5
-/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0;
- *  This field represents the amount of data needed to be sent.
- */
-#define I2C_RXFIFO_CNT    0x0000003FU
-#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
-#define I2C_RXFIFO_CNT_V  0x0000003FU
-#define I2C_RXFIFO_CNT_S  8
-/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
- *  The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the
- *  beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty
- *  in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.
- */
-#define I2C_STRETCH_CAUSE    0x00000003U
-#define I2C_STRETCH_CAUSE_M  (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S)
-#define I2C_STRETCH_CAUSE_V  0x00000003U
-#define I2C_STRETCH_CAUSE_S  14
-/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0;
- *  This field stores the amount of received data in RAM.
- */
-#define I2C_TXFIFO_CNT    0x0000003FU
-#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
-#define I2C_TXFIFO_CNT_V  0x0000003FU
-#define I2C_TXFIFO_CNT_S  18
-/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
- *  This field indicates the states of the I2C module state machine.
- *  0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6:
- *  Wait ACK
- */
-#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
-#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
-#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
-#define I2C_SCL_MAIN_STATE_LAST_S  24
-/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
- *  This field indicates the states of the state machine used to produce SCL.
- *  0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop
- */
-#define I2C_SCL_STATE_LAST    0x00000007U
-#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
-#define I2C_SCL_STATE_LAST_V  0x00000007U
-#define I2C_SCL_STATE_LAST_S  28
-
-/** I2C_TO_REG register
- *  Setting time out control for receiving data.
- */
-#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
-/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
- *  This register is used to configure the timeout for receiving a data bit in APB
- *  clock cycles.
- */
-#define I2C_TIME_OUT_VALUE    0x0000001FU
-#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
-#define I2C_TIME_OUT_VALUE_V  0x0000001FU
-#define I2C_TIME_OUT_VALUE_S  0
-/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for time out control.
- */
-#define I2C_TIME_OUT_EN    (BIT(5))
-#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
-#define I2C_TIME_OUT_EN_V  0x00000001U
-#define I2C_TIME_OUT_EN_S  5
-
-/** I2C_SLAVE_ADDR_REG register
- *  Local slave address setting
- */
-#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
-/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
- *  When configured as an I2C Slave, this field is used to configure the slave address.
- */
-#define I2C_SLAVE_ADDR    0x00007FFFU
-#define I2C_SLAVE_ADDR_M  (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
-#define I2C_SLAVE_ADDR_V  0x00007FFFU
-#define I2C_SLAVE_ADDR_S  0
-/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
- *  This field is used to enable the slave 10-bit addressing mode in master mode.
- */
-#define I2C_ADDR_10BIT_EN    (BIT(31))
-#define I2C_ADDR_10BIT_EN_M  (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
-#define I2C_ADDR_10BIT_EN_V  0x00000001U
-#define I2C_ADDR_10BIT_EN_S  31
-
-/** I2C_FIFO_ST_REG register
- *  FIFO status register.
- */
-#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
-/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
- *  This is the offset address of the APB reading from rxfifo
- */
-#define I2C_RXFIFO_RADDR    0x0000001FU
-#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
-#define I2C_RXFIFO_RADDR_V  0x0000001FU
-#define I2C_RXFIFO_RADDR_S  0
-/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0;
- *  This is the offset address of i2c module receiving data and writing to rxfifo.
- */
-#define I2C_RXFIFO_WADDR    0x0000001FU
-#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
-#define I2C_RXFIFO_WADDR_V  0x0000001FU
-#define I2C_RXFIFO_WADDR_S  5
-/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0;
- *  This is the offset address of i2c module reading from txfifo.
- */
-#define I2C_TXFIFO_RADDR    0x0000001FU
-#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
-#define I2C_TXFIFO_RADDR_V  0x0000001FU
-#define I2C_TXFIFO_RADDR_S  10
-/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0;
- *  This is the offset address of APB bus writing to txfifo.
- */
-#define I2C_TXFIFO_WADDR    0x0000001FU
-#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
-#define I2C_TXFIFO_WADDR_V  0x0000001FU
-#define I2C_TXFIFO_WADDR_S  15
-/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0;
- *  The received data in I2C slave mode.
- */
-#define I2C_SLAVE_RW_POINT    0x000000FFU
-#define I2C_SLAVE_RW_POINT_M  (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S)
-#define I2C_SLAVE_RW_POINT_V  0x000000FFU
-#define I2C_SLAVE_RW_POINT_S  22
-
-/** I2C_FIFO_CONF_REG register
- *  FIFO configuration register.
- */
-#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
-/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
- *  The water mark threshold of rx FIFO in nonfifo access mode. When
- *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
- *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
- */
-#define I2C_RXFIFO_WM_THRHD    0x0000001FU
-#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
-#define I2C_RXFIFO_WM_THRHD_V  0x0000001FU
-#define I2C_RXFIFO_WM_THRHD_S  0
-/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4;
- *  The water mark threshold of tx FIFO in nonfifo access mode. When
- *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
- *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
- */
-#define I2C_TXFIFO_WM_THRHD    0x0000001FU
-#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
-#define I2C_TXFIFO_WM_THRHD_V  0x0000001FU
-#define I2C_TXFIFO_WM_THRHD_S  5
-/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
- *  Set this bit to enable APB nonfifo access.
- */
-#define I2C_NONFIFO_EN    (BIT(10))
-#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
-#define I2C_NONFIFO_EN_V  0x00000001U
-#define I2C_NONFIFO_EN_S  10
-/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
- *  When this bit is set to 1, the byte received after the I2C address byte represents
- *  the offset address in the I2C Slave RAM.
- */
-#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
-#define I2C_FIFO_ADDR_CFG_EN_M  (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
-#define I2C_FIFO_ADDR_CFG_EN_V  0x00000001U
-#define I2C_FIFO_ADDR_CFG_EN_S  11
-/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
- *  Set this bit to reset rx-fifo.
- */
-#define I2C_RX_FIFO_RST    (BIT(12))
-#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
-#define I2C_RX_FIFO_RST_V  0x00000001U
-#define I2C_RX_FIFO_RST_S  12
-/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
- *  Set this bit to reset tx-fifo.
- */
-#define I2C_TX_FIFO_RST    (BIT(13))
-#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
-#define I2C_TX_FIFO_RST_V  0x00000001U
-#define I2C_TX_FIFO_RST_S  13
-/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
- *  The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
- *  the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
- */
-#define I2C_FIFO_PRT_EN    (BIT(14))
-#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
-#define I2C_FIFO_PRT_EN_V  0x00000001U
-#define I2C_FIFO_PRT_EN_S  14
-
-/** I2C_DATA_REG register
- *  Rx FIFO read data.
- */
-#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
-/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0;
- *  The value of rx FIFO read data.
- */
-#define I2C_FIFO_RDATA    0x000000FFU
-#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
-#define I2C_FIFO_RDATA_V  0x000000FFU
-#define I2C_FIFO_RDATA_S  0
-
-/** I2C_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
-/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
- *  The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
-#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
-#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_RAW_S  0
-/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
- *  The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
-#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
-#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_RAW_S  1
-/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
- *  The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
-#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_RAW_S  2
-/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
- *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_RAW    (BIT(3))
-#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
-#define I2C_END_DETECT_INT_RAW_V  0x00000001U
-#define I2C_END_DETECT_INT_RAW_S  3
-/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
- *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
-#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
-/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
- *  The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
-#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_RAW_S  5
-/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
- *  The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
-#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
-/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
- *  The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
-#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_RAW_S  7
-/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
- *  The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_RAW    (BIT(8))
-#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
-#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
-#define I2C_TIME_OUT_INT_RAW_S  8
-/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
- *  The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_RAW    (BIT(9))
-#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
-#define I2C_TRANS_START_INT_RAW_V  0x00000001U
-#define I2C_TRANS_START_INT_RAW_S  9
-/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
- *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_RAW    (BIT(10))
-#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
-#define I2C_NACK_INT_RAW_V  0x00000001U
-#define I2C_NACK_INT_RAW_S  10
-/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
- *  The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
-#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_RAW_S  11
-/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
- *  The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
-#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_RAW_S  12
-/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
- *  The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
-#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
-#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_RAW_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
- *  The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
-/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
- *  The raw interrupt bit for I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_RAW    (BIT(15))
-#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
-#define I2C_DET_START_INT_RAW_V  0x00000001U
-#define I2C_DET_START_INT_RAW_S  15
-/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
- *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_RAW_M  (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S)
-#define I2C_SLAVE_STRETCH_INT_RAW_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_RAW_S  16
-/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
- *  The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
-#define I2C_GENERAL_CALL_INT_RAW_M  (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S)
-#define I2C_GENERAL_CALL_INT_RAW_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_RAW_S  17
-
-/** I2C_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
-/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
-#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
-#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_CLR_S  0
-/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
-#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
-#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_CLR_S  1
-/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
-#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_CLR_S  2
-/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_CLR    (BIT(3))
-#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
-#define I2C_END_DETECT_INT_CLR_V  0x00000001U
-#define I2C_END_DETECT_INT_CLR_S  3
-/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
-#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
-/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
-#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_CLR_S  5
-/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
-#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
-/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
-#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_CLR_S  7
-/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_CLR    (BIT(8))
-#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
-#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
-#define I2C_TIME_OUT_INT_CLR_S  8
-/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_CLR    (BIT(9))
-#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
-#define I2C_TRANS_START_INT_CLR_V  0x00000001U
-#define I2C_TRANS_START_INT_CLR_S  9
-/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_CLR    (BIT(10))
-#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
-#define I2C_NACK_INT_CLR_V  0x00000001U
-#define I2C_NACK_INT_CLR_S  10
-/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
-#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_CLR_S  11
-/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
-#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_CLR_S  12
-/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
-#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
-#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_CLR_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
-/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_CLR    (BIT(15))
-#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
-#define I2C_DET_START_INT_CLR_V  0x00000001U
-#define I2C_DET_START_INT_CLR_S  15
-/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_CLR_M  (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S)
-#define I2C_SLAVE_STRETCH_INT_CLR_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_CLR_S  16
-/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit for I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
-#define I2C_GENERAL_CALL_INT_CLR_M  (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S)
-#define I2C_GENERAL_CALL_INT_CLR_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_CLR_S  17
-
-/** I2C_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
-/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
-#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
-#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_ENA_S  0
-/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
-#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
-#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_ENA_S  1
-/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
-#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_ENA_S  2
-/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_ENA    (BIT(3))
-#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
-#define I2C_END_DETECT_INT_ENA_V  0x00000001U
-#define I2C_END_DETECT_INT_ENA_S  3
-/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
-#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
-/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
-#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_ENA_S  5
-/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
-#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
-/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
-#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_ENA_S  7
-/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_ENA    (BIT(8))
-#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
-#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
-#define I2C_TIME_OUT_INT_ENA_S  8
-/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_ENA    (BIT(9))
-#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
-#define I2C_TRANS_START_INT_ENA_V  0x00000001U
-#define I2C_TRANS_START_INT_ENA_S  9
-/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_ENA    (BIT(10))
-#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
-#define I2C_NACK_INT_ENA_V  0x00000001U
-#define I2C_NACK_INT_ENA_S  10
-/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
-#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_ENA_S  11
-/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
-#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_ENA_S  12
-/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
-#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
-#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_ENA_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
-/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The interrupt enable bit for I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_ENA    (BIT(15))
-#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
-#define I2C_DET_START_INT_ENA_V  0x00000001U
-#define I2C_DET_START_INT_ENA_S  15
-/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ENA_M  (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S)
-#define I2C_SLAVE_STRETCH_INT_ENA_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_ENA_S  16
-/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
-#define I2C_GENERAL_CALL_INT_ENA_M  (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S)
-#define I2C_GENERAL_CALL_INT_ENA_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_ENA_S  17
-
-/** I2C_INT_STATUS_REG register
- *  Status of captured I2C communication events
- */
-#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
-/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
- */
-#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
-#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
-#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_WM_INT_ST_S  0
-/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
- */
-#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
-#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
-#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
-#define I2C_TXFIFO_WM_INT_ST_S  1
-/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
- */
-#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
-#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
-#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_OVF_INT_ST_S  2
-/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_END_DETECT_INT_ST    (BIT(3))
-#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
-#define I2C_END_DETECT_INT_ST_V  0x00000001U
-#define I2C_END_DETECT_INT_ST_S  3
-/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
- *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
- */
-#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
-#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
-#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
-#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
-/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
- */
-#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
-#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
-#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
-#define I2C_ARBITRATION_LOST_INT_ST_S  5
-/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
-#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
-#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
-#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
-/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
- */
-#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
-#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
-#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
-#define I2C_TRANS_COMPLETE_INT_ST_S  7
-/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
- */
-#define I2C_TIME_OUT_INT_ST    (BIT(8))
-#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
-#define I2C_TIME_OUT_INT_ST_V  0x00000001U
-#define I2C_TIME_OUT_INT_ST_S  8
-/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
- */
-#define I2C_TRANS_START_INT_ST    (BIT(9))
-#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
-#define I2C_TRANS_START_INT_ST_V  0x00000001U
-#define I2C_TRANS_START_INT_ST_S  9
-/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_NACK_INT_ST    (BIT(10))
-#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
-#define I2C_NACK_INT_ST_V  0x00000001U
-#define I2C_NACK_INT_ST_S  10
-/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
- */
-#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
-#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
-#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
-#define I2C_TXFIFO_OVF_INT_ST_S  11
-/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.
- */
-#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
-#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
-#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
-#define I2C_RXFIFO_UDF_INT_ST_S  12
-/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
- *  The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
- */
-#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
-#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
-#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
-#define I2C_SCL_ST_TO_INT_ST_S  13
-/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
- *  The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
- */
-#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
-#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
-#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
-#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
-/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
- *  The masked interrupt status bit for I2C_DET_START_INT interrupt.
- */
-#define I2C_DET_START_INT_ST    (BIT(15))
-#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
-#define I2C_DET_START_INT_ST_V  0x00000001U
-#define I2C_DET_START_INT_ST_S  15
-/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0;
- *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
- */
-#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
-#define I2C_SLAVE_STRETCH_INT_ST_M  (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S)
-#define I2C_SLAVE_STRETCH_INT_ST_V  0x00000001U
-#define I2C_SLAVE_STRETCH_INT_ST_S  16
-/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0;
- *  The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.
- */
-#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
-#define I2C_GENERAL_CALL_INT_ST_M  (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S)
-#define I2C_GENERAL_CALL_INT_ST_V  0x00000001U
-#define I2C_GENERAL_CALL_INT_ST_S  17
-
-/** I2C_SDA_HOLD_REG register
- *  Configures the hold time after a negative SCL edge.
- */
-#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
-/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
- *  This register is used to configure the time to hold the data after the negative
- *  edge of SCL, in I2C module clock cycles.
- */
-#define I2C_SDA_HOLD_TIME    0x000001FFU
-#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
-#define I2C_SDA_HOLD_TIME_V  0x000001FFU
-#define I2C_SDA_HOLD_TIME_S  0
-
-/** I2C_SDA_SAMPLE_REG register
- *  Configures the sample time after a positive SCL edge.
- */
-#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
-/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
- *  This register is used to configure for how long SDA is sampled, in I2C module clock
- *  cycles.
- */
-#define I2C_SDA_SAMPLE_TIME    0x000001FFU
-#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
-#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
-#define I2C_SDA_SAMPLE_TIME_S  0
-
-/** I2C_SCL_HIGH_PERIOD_REG register
- *  Configures the high level width of SCL
- */
-#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
-/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
- *  This register is used to configure for how long SCL remains high in master mode, in
- *  I2C module clock cycles.
- */
-#define I2C_SCL_HIGH_PERIOD    0x000001FFU
-#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
-#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
-#define I2C_SCL_HIGH_PERIOD_S  0
-/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
- *  This register is used to configure for the SCL_FSM's waiting period for SCL high
- *  level in master mode, in I2C module clock cycles.
- */
-#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
-#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
-#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
-#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
-
-/** I2C_SCL_START_HOLD_REG register
- *  Configures the delay between the SDA and SCL negative edge for a start condition
- */
-#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
-/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
- *  This register is used to configure the time between the negative edge
- *  of SDA and the negative edge of SCL for a START condition, in I2C module clock
- *  cycles.
- */
-#define I2C_SCL_START_HOLD_TIME    0x000001FFU
-#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
-#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
-#define I2C_SCL_START_HOLD_TIME_S  0
-
-/** I2C_SCL_RSTART_SETUP_REG register
- *  Configures the delay between the positive
- *  edge of SCL and the negative edge of SDA
- */
-#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
-/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
- *  This register is used to configure the time between the positive
- *  edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
- *  clock cycles.
- */
-#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
-#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
-#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
-#define I2C_SCL_RSTART_SETUP_TIME_S  0
-
-/** I2C_SCL_STOP_HOLD_REG register
- *  Configures the delay after the SCL clock
- *  edge for a stop condition
- */
-#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
-/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
- *  This register is used to configure the delay after the STOP condition,
- *  in I2C module clock cycles.
- */
-#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
-#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
-#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
-#define I2C_SCL_STOP_HOLD_TIME_S  0
-
-/** I2C_SCL_STOP_SETUP_REG register
- *  Configures the delay between the SDA and
- *  SCL positive edge for a stop condition
- */
-#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
-/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
- *  This register is used to configure the time between the positive edge
- *  of SCL and the positive edge of SDA, in I2C module clock cycles.
- */
-#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
-#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
-#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
-#define I2C_SCL_STOP_SETUP_TIME_S  0
-
-/** I2C_FILTER_CFG_REG register
- *  SCL and SDA filter configuration register
- */
-#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
-/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
- *  When a pulse on the SCL input has smaller width than this register value
- *  in I2C module clock cycles, the I2C controller will ignore that pulse.
- */
-#define I2C_SCL_FILTER_THRES    0x0000000FU
-#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
-#define I2C_SCL_FILTER_THRES_V  0x0000000FU
-#define I2C_SCL_FILTER_THRES_S  0
-/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
- *  When a pulse on the SDA input has smaller width than this register value
- *  in I2C module clock cycles, the I2C controller will ignore that pulse.
- */
-#define I2C_SDA_FILTER_THRES    0x0000000FU
-#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
-#define I2C_SDA_FILTER_THRES_V  0x0000000FU
-#define I2C_SDA_FILTER_THRES_S  4
-/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
- *  This is the filter enable bit for SCL.
- */
-#define I2C_SCL_FILTER_EN    (BIT(8))
-#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
-#define I2C_SCL_FILTER_EN_V  0x00000001U
-#define I2C_SCL_FILTER_EN_S  8
-/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
- *  This is the filter enable bit for SDA.
- */
-#define I2C_SDA_FILTER_EN    (BIT(9))
-#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
-#define I2C_SDA_FILTER_EN_V  0x00000001U
-#define I2C_SDA_FILTER_EN_S  9
-
-/** I2C_CLK_CONF_REG register
- *  I2C CLK configuration register
- */
-#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54)
-/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
- *  the integral part of the fractional divisor for i2c module
- */
-#define I2C_SCLK_DIV_NUM    0x000000FFU
-#define I2C_SCLK_DIV_NUM_M  (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S)
-#define I2C_SCLK_DIV_NUM_V  0x000000FFU
-#define I2C_SCLK_DIV_NUM_S  0
-/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0;
- *  the numerator of the fractional part of the fractional divisor for i2c module
- */
-#define I2C_SCLK_DIV_A    0x0000003FU
-#define I2C_SCLK_DIV_A_M  (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S)
-#define I2C_SCLK_DIV_A_V  0x0000003FU
-#define I2C_SCLK_DIV_A_S  8
-/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0;
- *  the denominator of the fractional part of the fractional divisor for i2c module
- */
-#define I2C_SCLK_DIV_B    0x0000003FU
-#define I2C_SCLK_DIV_B_M  (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S)
-#define I2C_SCLK_DIV_B_V  0x0000003FU
-#define I2C_SCLK_DIV_B_S  14
-/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
- *  The clock selection for i2c module:0-XTAL;1-CLK_8MHz.
- */
-#define I2C_SCLK_SEL    (BIT(20))
-#define I2C_SCLK_SEL_M  (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S)
-#define I2C_SCLK_SEL_V  0x00000001U
-#define I2C_SCLK_SEL_S  20
-/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1;
- *  The clock switch for i2c module
- */
-#define I2C_SCLK_ACTIVE    (BIT(21))
-#define I2C_SCLK_ACTIVE_M  (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S)
-#define I2C_SCLK_ACTIVE_V  0x00000001U
-#define I2C_SCLK_ACTIVE_S  21
-
-/** I2C_COMD0_REG register
- *  I2C command register 0
- */
-#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
-/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
- *  This is the content of command 0. It consists of three parts:
- *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more
- *  Information.
- */
-#define I2C_COMMAND0    0x00003FFFU
-#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
-#define I2C_COMMAND0_V  0x00003FFFU
-#define I2C_COMMAND0_S  0
-/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  When command 0 is done in I2C Master mode, this bit changes to high
- *  level.
- */
-#define I2C_COMMAND0_DONE    (BIT(31))
-#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
-#define I2C_COMMAND0_DONE_V  0x00000001U
-#define I2C_COMMAND0_DONE_S  31
-
-/** I2C_COMD1_REG register
- *  I2C command register 1
- */
-#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
-/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
- *  This is the content of command 1. It consists of three parts:
- *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more
- *  Information.
- */
-#define I2C_COMMAND1    0x00003FFFU
-#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
-#define I2C_COMMAND1_V  0x00003FFFU
-#define I2C_COMMAND1_S  0
-/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  When command 1 is done in I2C Master mode, this bit changes to high
- *  level.
- */
-#define I2C_COMMAND1_DONE    (BIT(31))
-#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
-#define I2C_COMMAND1_DONE_V  0x00000001U
-#define I2C_COMMAND1_DONE_S  31
-
-/** I2C_COMD2_REG register
- *  I2C command register 2
- */
-#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
-/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
- *  This is the content of command 2. It consists of three parts:
- *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more
- *  Information.
- */
-#define I2C_COMMAND2    0x00003FFFU
-#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
-#define I2C_COMMAND2_V  0x00003FFFU
-#define I2C_COMMAND2_S  0
-/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  When command 2 is done in I2C Master mode, this bit changes to high
- *  Level.
- */
-#define I2C_COMMAND2_DONE    (BIT(31))
-#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
-#define I2C_COMMAND2_DONE_V  0x00000001U
-#define I2C_COMMAND2_DONE_S  31
-
-/** I2C_COMD3_REG register
- *  I2C command register 3
- */
-#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
-/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
- *  This is the content of command 3. It consists of three parts:
- *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more
- *  Information.
- */
-#define I2C_COMMAND3    0x00003FFFU
-#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
-#define I2C_COMMAND3_V  0x00003FFFU
-#define I2C_COMMAND3_S  0
-/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  When command 3 is done in I2C Master mode, this bit changes to high
- *  level.
- */
-#define I2C_COMMAND3_DONE    (BIT(31))
-#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
-#define I2C_COMMAND3_DONE_V  0x00000001U
-#define I2C_COMMAND3_DONE_S  31
-
-/** I2C_COMD4_REG register
- *  I2C command register 4
- */
-#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
-/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
- *  This is the content of command 4. It consists of three parts:
- *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more
- *  Information.
- */
-#define I2C_COMMAND4    0x00003FFFU
-#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
-#define I2C_COMMAND4_V  0x00003FFFU
-#define I2C_COMMAND4_S  0
-/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  When command 4 is done in I2C Master mode, this bit changes to high
- *  level.
- */
-#define I2C_COMMAND4_DONE    (BIT(31))
-#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
-#define I2C_COMMAND4_DONE_V  0x00000001U
-#define I2C_COMMAND4_DONE_S  31
-
-/** I2C_COMD5_REG register
- *  I2C command register 5
- */
-#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
-/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
- *  This is the content of command 5. It consists of three parts:
- *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more
- *  Information.
- */
-#define I2C_COMMAND5    0x00003FFFU
-#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
-#define I2C_COMMAND5_V  0x00003FFFU
-#define I2C_COMMAND5_S  0
-/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  When command 5 is done in I2C Master mode, this bit changes to high level.
- */
-#define I2C_COMMAND5_DONE    (BIT(31))
-#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
-#define I2C_COMMAND5_DONE_V  0x00000001U
-#define I2C_COMMAND5_DONE_S  31
-
-/** I2C_COMD6_REG register
- *  I2C command register 6
- */
-#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
-/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
- *  This is the content of command 6. It consists of three parts:
- *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more
- *  Information.
- */
-#define I2C_COMMAND6    0x00003FFFU
-#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
-#define I2C_COMMAND6_V  0x00003FFFU
-#define I2C_COMMAND6_S  0
-/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  When command 6 is done in I2C Master mode, this bit changes to high level.
- */
-#define I2C_COMMAND6_DONE    (BIT(31))
-#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
-#define I2C_COMMAND6_DONE_V  0x00000001U
-#define I2C_COMMAND6_DONE_S  31
-
-/** I2C_COMD7_REG register
- *  I2C command register 7
- */
-#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
-/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
- *  This is the content of command 7. It consists of three parts:
- *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
- *  Byte_num represents the number of bytes that need to be sent or received.
- *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
- *  structure for more
- *  Information.
- */
-#define I2C_COMMAND7    0x00003FFFU
-#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
-#define I2C_COMMAND7_V  0x00003FFFU
-#define I2C_COMMAND7_S  0
-/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
- *  When command 7 is done in I2C Master mode, this bit changes to high level.
- */
-#define I2C_COMMAND7_DONE    (BIT(31))
-#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
-#define I2C_COMMAND7_DONE_V  0x00000001U
-#define I2C_COMMAND7_DONE_S  31
-
-/** I2C_SCL_ST_TIME_OUT_REG register
- *  SCL status time out register
- */
-#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
-/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
- *  The threshold value of SCL_FSM state unchanged period. It should be o more than 23
- */
-#define I2C_SCL_ST_TO_I2C    0x0000001FU
-#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
-#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
-#define I2C_SCL_ST_TO_I2C_S  0
-
-/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
- *  SCL main status time out register
- */
-#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
-/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
- *  The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
- *  than 23
- */
-#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
-#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
-#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
-#define I2C_SCL_MAIN_ST_TO_I2C_S  0
-
-/** I2C_SCL_SP_CONF_REG register
- *  Power configuration register
- */
-#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
-/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
- *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
- *  equals to reg_scl_rst_slv_num[4:0].
- */
-#define I2C_SCL_RST_SLV_EN    (BIT(0))
-#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
-#define I2C_SCL_RST_SLV_EN_V  0x00000001U
-#define I2C_SCL_RST_SLV_EN_S  0
-/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
- *  Configure the pulses of SCL generated in I2C master mode. Valid when
- *  reg_scl_rst_slv_en is 1.
- */
-#define I2C_SCL_RST_SLV_NUM    0x0000001FU
-#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
-#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
-#define I2C_SCL_RST_SLV_NUM_S  1
-/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
- *  The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
- *  down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
- */
-#define I2C_SCL_PD_EN    (BIT(6))
-#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
-#define I2C_SCL_PD_EN_V  0x00000001U
-#define I2C_SCL_PD_EN_S  6
-/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
- *  The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
- *  down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
- */
-#define I2C_SDA_PD_EN    (BIT(7))
-#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
-#define I2C_SDA_PD_EN_V  0x00000001U
-#define I2C_SDA_PD_EN_S  7
-
-/** I2C_SCL_STRETCH_CONF_REG register
- *  Set SCL stretch of I2C slave
- */
-#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
-/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
- *  Configure the period of I2C slave stretching SCL line.
- */
-#define I2C_STRETCH_PROTECT_NUM    0x000003FFU
-#define I2C_STRETCH_PROTECT_NUM_M  (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
-#define I2C_STRETCH_PROTECT_NUM_V  0x000003FFU
-#define I2C_STRETCH_PROTECT_NUM_S  0
-/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
- *  The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL
- *  output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch
- *  event happens. The stretch cause can be seen in reg_stretch_cause.
- */
-#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
-#define I2C_SLAVE_SCL_STRETCH_EN_M  (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
-#define I2C_SLAVE_SCL_STRETCH_EN_V  0x00000001U
-#define I2C_SLAVE_SCL_STRETCH_EN_S  10
-/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the I2C slave SCL stretch function.
- */
-#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
-#define I2C_SLAVE_SCL_STRETCH_CLR_M  (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
-#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x00000001U
-#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
-/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
- *  The enable bit for slave to control ACK level function.
- */
-#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x00000001U
-#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
-/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
- *  Set the ACK level when slave controlling ACK level function enables.
- */
-#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
-#define I2C_SLAVE_BYTE_ACK_LVL_M  (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
-#define I2C_SLAVE_BYTE_ACK_LVL_V  0x00000001U
-#define I2C_SLAVE_BYTE_ACK_LVL_S  13
-
-/** I2C_DATE_REG register
- *  Version register
- */
-#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
-/** I2C_DATE : R/W; bitpos: [31:0]; default: 537330177;
- *  This is the the version register.
- */
-#define I2C_DATE    0xFFFFFFFFU
-#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
-#define I2C_DATE_V  0xFFFFFFFFU
-#define I2C_DATE_S  0
-
-/** I2C_TXFIFO_START_ADDR_REG register
- *  I2C TXFIFO base address register
- */
-#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
-/** I2C_TXFIFO_START_ADDR : RO; bitpos: [31:0]; default: 0;
- *  This is the I2C txfifo first address.
- */
-#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
-#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
-#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
-#define I2C_TXFIFO_START_ADDR_S  0
-
-/** I2C_RXFIFO_START_ADDR_REG register
- *  I2C RXFIFO base address register
- */
-#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
-/** I2C_RXFIFO_START_ADDR : RO; bitpos: [31:0]; default: 0;
- *  This is the I2C rxfifo first address.
- */
-#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
-#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
-#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
-#define I2C_RXFIFO_START_ADDR_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/i2c_struct.h b/components/soc/esp32s3/include/soc/i2c_struct.h
deleted file mode 100644
index 807ffa508d1..00000000000
--- a/components/soc/esp32s3/include/soc/i2c_struct.h
+++ /dev/null
@@ -1,988 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) CO LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Timing registers */
-/** Type of scl_low_period register
- *  Configures the low level width of the SCL
- *  Clock
- */
-typedef union {
-    struct {
-        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
-         *  This register is used to configure for how long SCL remains low in master mode, in
-         *  I2C module clock cycles.
-         */
-        uint32_t scl_low_period:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_low_period_reg_t;
-
-/** Type of sda_hold register
- *  Configures the hold time after a negative SCL edge.
- */
-typedef union {
-    struct {
-        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
-         *  This register is used to configure the time to hold the data after the negative
-         *  edge of SCL, in I2C module clock cycles.
-         */
-        uint32_t sda_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_sda_hold_reg_t;
-
-/** Type of sda_sample register
- *  Configures the sample time after a positive SCL edge.
- */
-typedef union {
-    struct {
-        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
-         *  This register is used to configure for how long SDA is sampled, in I2C module clock
-         *  cycles.
-         */
-        uint32_t sda_sample_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_sda_sample_reg_t;
-
-/** Type of scl_high_period register
- *  Configures the high level width of SCL
- */
-typedef union {
-    struct {
-        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
-         *  This register is used to configure for how long SCL remains high in master mode, in
-         *  I2C module clock cycles.
-         */
-        uint32_t scl_high_period:9;
-        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
-         *  This register is used to configure for the SCL_FSM's waiting period for SCL high
-         *  level in master mode, in I2C module clock cycles.
-         */
-        uint32_t scl_wait_high_period:7;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} i2c_scl_high_period_reg_t;
-
-/** Type of scl_start_hold register
- *  Configures the delay between the SDA and SCL negative edge for a start condition
- */
-typedef union {
-    struct {
-        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
-         *  This register is used to configure the time between the negative edge
-         *  of SDA and the negative edge of SCL for a START condition, in I2C module clock
-         *  cycles.
-         */
-        uint32_t scl_start_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_start_hold_reg_t;
-
-/** Type of scl_rstart_setup register
- *  Configures the delay between the positive
- *  edge of SCL and the negative edge of SDA
- */
-typedef union {
-    struct {
-        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
-         *  This register is used to configure the time between the positive
-         *  edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
-         *  clock cycles.
-         */
-        uint32_t scl_rstart_setup_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_rstart_setup_reg_t;
-
-/** Type of scl_stop_hold register
- *  Configures the delay after the SCL clock
- *  edge for a stop condition
- */
-typedef union {
-    struct {
-        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
-         *  This register is used to configure the delay after the STOP condition,
-         *  in I2C module clock cycles.
-         */
-        uint32_t scl_stop_hold_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_stop_hold_reg_t;
-
-/** Type of scl_stop_setup register
- *  Configures the delay between the SDA and
- *  SCL positive edge for a stop condition
- */
-typedef union {
-    struct {
-        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
-         *  This register is used to configure the time between the positive edge
-         *  of SCL and the positive edge of SDA, in I2C module clock cycles.
-         */
-        uint32_t scl_stop_setup_time:9;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} i2c_scl_stop_setup_reg_t;
-
-/** Type of scl_st_time_out register
- *  SCL status time out register
- */
-typedef union {
-    struct {
-        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
-         *  The threshold value of SCL_FSM state unchanged period. It should be o more than 23
-         */
-        uint32_t scl_st_to_i2c:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} i2c_scl_st_time_out_reg_t;
-
-/** Type of scl_main_st_time_out register
- *  SCL main status time out register
- */
-typedef union {
-    struct {
-        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
-         *  The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
-         *  than 23
-         */
-        uint32_t scl_main_st_to_i2c:5;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} i2c_scl_main_st_time_out_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of ctr register
- *  Transmission setting
- */
-typedef union {
-    struct {
-        /** sda_force_out : R/W; bitpos: [0]; default: 1;
-         *  0: direct output; 1: open drain output.
-         */
-        uint32_t sda_force_out:1;
-        /** scl_force_out : R/W; bitpos: [1]; default: 1;
-         *  0: direct output; 1: open drain output.
-         */
-        uint32_t scl_force_out:1;
-        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
-         *  This register is used to select the sample mode.
-         *  1: sample SDA data on the SCL low level.
-         *  0: sample SDA data on the SCL high level.
-         */
-        uint32_t sample_scl_level:1;
-        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
-         *  This register is used to configure the ACK value that need to sent by master when
-         *  the rx_fifo_cnt has reached the threshold.
-         */
-        uint32_t rx_full_ack_level:1;
-        /** ms_mode : R/W; bitpos: [4]; default: 0;
-         *  Set this bit to configure the module as an I2C Master. Clear this bit to configure
-         *  the
-         *  module as an I2C Slave.
-         */
-        uint32_t ms_mode:1;
-        /** trans_start : WT; bitpos: [5]; default: 0;
-         *  Set this bit to start sending the data in txfifo.
-         */
-        uint32_t trans_start:1;
-        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
-         *  This bit is used to control the sending mode for data needing to be sent.
-         *  1: send data from the least significant bit;
-         *  0: send data from the most significant bit.
-         */
-        uint32_t tx_lsb_first:1;
-        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
-         *  This bit is used to control the storage mode for received data.
-         *  1: receive data from the least significant bit;
-         *  0: receive data from the most significant bit.
-         */
-        uint32_t rx_lsb_first:1;
-        /** clk_en : R/W; bitpos: [8]; default: 0;
-         *  Reserved
-         */
-        uint32_t clk_en:1;
-        /** arbitration_en : R/W; bitpos: [9]; default: 1;
-         *  This is the enable bit for arbitration_lost.
-         */
-        uint32_t arbitration_en:1;
-        /** fsm_rst : WT; bitpos: [10]; default: 0;
-         *  This register is used to reset the scl FMS.
-         */
-        uint32_t fsm_rst:1;
-        /** conf_upgate : WT; bitpos: [11]; default: 0;
-         *  synchronization bit
-         */
-        uint32_t conf_upgate:1;
-        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for slave to send data automatically
-         */
-        uint32_t slv_tx_auto_start_en:1;
-        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit to check if the r/w bit of 10bit addressing consists with
-         *  I2C protocol
-         */
-        uint32_t addr_10bit_rw_check_en:1;
-        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit to support the 7bit general call function.
-         */
-        uint32_t addr_broadcasting_en:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} i2c_ctr_reg_t;
-
-/** Type of to register
- *  Setting time out control for receiving data.
- */
-typedef union {
-    struct {
-        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
-         *  This register is used to configure the timeout for receiving a data bit in APB
-         *  clock cycles.
-         */
-        uint32_t time_out_value:5;
-        /** time_out_en : R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for time out control.
-         */
-        uint32_t time_out_en:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} i2c_to_reg_t;
-
-/** Type of slave_addr register
- *  Local slave address setting
- */
-typedef union {
-    struct {
-        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
-         *  When configured as an I2C Slave, this field is used to configure the slave address.
-         */
-        uint32_t slave_addr:15;
-        uint32_t reserved_15:16;
-        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
-         *  This field is used to enable the slave 10-bit addressing mode in master mode.
-         */
-        uint32_t addr_10bit_en:1;
-    };
-    uint32_t val;
-} i2c_slave_addr_reg_t;
-
-/** Type of fifo_conf register
- *  FIFO configuration register.
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
-         *  The water mark threshold of rx FIFO in nonfifo access mode. When
-         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
-         *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
-         */
-        uint32_t rxfifo_wm_thrhd:5;
-        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
-         *  The water mark threshold of tx FIFO in nonfifo access mode. When
-         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
-         *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
-         */
-        uint32_t txfifo_wm_thrhd:5;
-        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
-         *  Set this bit to enable APB nonfifo access.
-         */
-        uint32_t nonfifo_en:1;
-        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
-         *  When this bit is set to 1, the byte received after the I2C address byte represents
-         *  the offset address in the I2C Slave RAM.
-         */
-        uint32_t fifo_addr_cfg_en:1;
-        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to reset rx-fifo.
-         */
-        uint32_t rx_fifo_rst:1;
-        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to reset tx-fifo.
-         */
-        uint32_t tx_fifo_rst:1;
-        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
-         *  The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
-         *  the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
-         */
-        uint32_t fifo_prt_en:1;
-        uint32_t reserved_15:17;
-    };
-    uint32_t val;
-} i2c_fifo_conf_reg_t;
-
-/** Type of filter_cfg register
- *  SCL and SDA filter configuration register
- */
-typedef union {
-    struct {
-        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
-         *  When a pulse on the SCL input has smaller width than this register value
-         *  in I2C module clock cycles, the I2C controller will ignore that pulse.
-         */
-        uint32_t scl_filter_thres:4;
-        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
-         *  When a pulse on the SDA input has smaller width than this register value
-         *  in I2C module clock cycles, the I2C controller will ignore that pulse.
-         */
-        uint32_t sda_filter_thres:4;
-        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
-         *  This is the filter enable bit for SCL.
-         */
-        uint32_t scl_filter_en:1;
-        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
-         *  This is the filter enable bit for SDA.
-         */
-        uint32_t sda_filter_en:1;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} i2c_filter_cfg_reg_t;
-
-/** Type of clk_conf register
- *  I2C CLK configuration register
- */
-typedef union {
-    struct {
-        /** sclk_div_num : R/W; bitpos: [7:0]; default: 0;
-         *  the integral part of the fractional divisor for i2c module
-         */
-        uint32_t sclk_div_num:8;
-        /** sclk_div_a : R/W; bitpos: [13:8]; default: 0;
-         *  the numerator of the fractional part of the fractional divisor for i2c module
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_b : R/W; bitpos: [19:14]; default: 0;
-         *  the denominator of the fractional part of the fractional divisor for i2c module
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_sel : R/W; bitpos: [20]; default: 0;
-         *  The clock selection for i2c module:0-XTAL;1-CLK_8MHz.
-         */
-        uint32_t sclk_sel:1;
-        /** sclk_active : R/W; bitpos: [21]; default: 1;
-         *  The clock switch for i2c module
-         */
-        uint32_t sclk_active:1;
-        uint32_t reserved_22:10;
-    };
-    uint32_t val;
-} i2c_clk_conf_reg_t;
-
-/** Type of scl_sp_conf register
- *  Power configuration register
- */
-typedef union {
-    struct {
-        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
-         *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
-         *  equals to reg_scl_rst_slv_num[4:0].
-         */
-        uint32_t scl_rst_slv_en:1;
-        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
-         *  Configure the pulses of SCL generated in I2C master mode. Valid when
-         *  reg_scl_rst_slv_en is 1.
-         */
-        uint32_t scl_rst_slv_num:5;
-        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
-         *  The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
-         *  down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
-         */
-        uint32_t scl_pd_en:1;
-        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
-         *  The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
-         *  down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
-         */
-        uint32_t sda_pd_en:1;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} i2c_scl_sp_conf_reg_t;
-
-/** Type of scl_stretch_conf register
- *  Set SCL stretch of I2C slave
- */
-typedef union {
-    struct {
-        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
-         *  Configure the period of I2C slave stretching SCL line.
-         */
-        uint32_t stretch_protect_num:10;
-        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL
-         *  output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch
-         *  event happens. The stretch cause can be seen in reg_stretch_cause.
-         */
-        uint32_t slave_scl_stretch_en:1;
-        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the I2C slave SCL stretch function.
-         */
-        uint32_t slave_scl_stretch_clr:1;
-        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
-         *  The enable bit for slave to control ACK level function.
-         */
-        uint32_t slave_byte_ack_ctl_en:1;
-        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
-         *  Set the ACK level when slave controlling ACK level function enables.
-         */
-        uint32_t slave_byte_ack_lvl:1;
-        uint32_t reserved_14:18;
-    };
-    uint32_t val;
-} i2c_scl_stretch_conf_reg_t;
-
-
-/** Group: Status registers */
-/** Type of sr register
- *  Describe I2C work status.
- */
-typedef union {
-    struct {
-        /** resp_rec : RO; bitpos: [0]; default: 0;
-         *  The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
-         */
-        uint32_t resp_rec:1;
-        /** slave_rw : RO; bitpos: [1]; default: 0;
-         *  When in slave mode, 1: master reads from slave; 0: master writes to slave.
-         */
-        uint32_t slave_rw:1;
-        uint32_t reserved_2:1;
-        /** arb_lost : RO; bitpos: [3]; default: 0;
-         *  When the I2C controller loses control of SCL line, this register changes to 1.
-         */
-        uint32_t arb_lost:1;
-        /** bus_busy : RO; bitpos: [4]; default: 0;
-         *  1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state.
-         */
-        uint32_t bus_busy:1;
-        /** slave_addressed : RO; bitpos: [5]; default: 0;
-         *  When configured as an I2C Slave, and the address sent by the master is
-         *  equal to the address of the slave, then this bit will be of high level.
-         */
-        uint32_t slave_addressed:1;
-        uint32_t reserved_6:2;
-        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
-         *  This field represents the amount of data needed to be sent.
-         */
-        uint32_t rxfifo_cnt:6;
-        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
-         *  The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the
-         *  beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty
-         *  in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.
-         */
-        uint32_t stretch_cause:2;
-        uint32_t reserved_16:2;
-        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
-         *  This field stores the amount of received data in RAM.
-         */
-        uint32_t txfifo_cnt:6;
-        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
-         *  This field indicates the states of the I2C module state machine.
-         *  0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6:
-         *  Wait ACK
-         */
-        uint32_t scl_main_state_last:3;
-        uint32_t reserved_27:1;
-        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
-         *  This field indicates the states of the state machine used to produce SCL.
-         *  0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop
-         */
-        uint32_t scl_state_last:3;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} i2c_sr_reg_t;
-
-/** Type of fifo_st register
- *  FIFO status register.
- */
-typedef union {
-    struct {
-        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
-         *  This is the offset address of the APB reading from rxfifo
-         */
-        uint32_t rxfifo_raddr:5;
-        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
-         *  This is the offset address of i2c module receiving data and writing to rxfifo.
-         */
-        uint32_t rxfifo_waddr:5;
-        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
-         *  This is the offset address of i2c module reading from txfifo.
-         */
-        uint32_t txfifo_raddr:5;
-        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
-         *  This is the offset address of APB bus writing to txfifo.
-         */
-        uint32_t txfifo_waddr:5;
-        uint32_t reserved_20:2;
-        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
-         *  The received data in I2C slave mode.
-         */
-        uint32_t slave_rw_point:8;
-        uint32_t reserved_30:2;
-    };
-    uint32_t val;
-} i2c_fifo_st_reg_t;
-
-/** Type of data register
- *  Rx FIFO read data.
- */
-typedef union {
-    struct {
-        /** fifo_rdata : RO; bitpos: [7:0]; default: 0;
-         *  The value of rx FIFO read data.
-         */
-        uint32_t fifo_rdata:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} i2c_data_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
-         *  The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_raw:1;
-        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
-         *  The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
-         *  The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
-         *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_raw:1;
-        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
-         *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_raw:1;
-        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
-         *  The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_raw:1;
-        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
-         *  The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_raw:1;
-        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
-         *  The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_raw:1;
-        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
-         *  The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_raw:1;
-        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
-         *  The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_raw:1;
-        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
-         *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_raw:1;
-        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
-         *  The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_raw:1;
-        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
-         *  The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_raw:1;
-        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
-         *  The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_raw:1;
-        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
-         *  The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_raw:1;
-        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
-         *  The raw interrupt bit for I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_raw:1;
-        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
-         *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_raw:1;
-        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
-         *  The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_raw:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} i2c_int_raw_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_clr:1;
-        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_clr:1;
-        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_clr:1;
-        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_clr:1;
-        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_clr:1;
-        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_clr:1;
-        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_clr:1;
-        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_clr:1;
-        /** nack_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_clr:1;
-        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_clr:1;
-        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_clr:1;
-        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_clr:1;
-        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_clr:1;
-        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_clr:1;
-        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_clr:1;
-        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
-         *  Set this bit for I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_clr:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} i2c_int_clr_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_ena:1;
-        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_ena:1;
-        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_ena:1;
-        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_ena:1;
-        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_ena:1;
-        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_ena:1;
-        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_ena:1;
-        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_ena:1;
-        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_ena:1;
-        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_ena:1;
-        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_ena:1;
-        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_ena:1;
-        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_ena:1;
-        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The interrupt enable bit for I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_ena:1;
-        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
-         *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_ena:1;
-        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
-         *  The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_ena:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} i2c_int_ena_reg_t;
-
-/** Type of int_status register
- *  Status of captured I2C communication events
- */
-typedef union {
-    struct {
-        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
-         */
-        uint32_t rxfifo_wm_int_st:1;
-        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
-         */
-        uint32_t txfifo_wm_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t end_detect_int_st:1;
-        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
-         */
-        uint32_t byte_trans_done_int_st:1;
-        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
-         */
-        uint32_t arbitration_lost_int_st:1;
-        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t mst_txfifo_udf_int_st:1;
-        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
-         */
-        uint32_t trans_complete_int_st:1;
-        /** time_out_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
-         */
-        uint32_t time_out_int_st:1;
-        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
-         */
-        uint32_t trans_start_int_st:1;
-        /** nack_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t nack_int_st:1;
-        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
-         */
-        uint32_t txfifo_ovf_int_st:1;
-        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.
-         */
-        uint32_t rxfifo_udf_int_st:1;
-        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
-         */
-        uint32_t scl_st_to_int_st:1;
-        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
-         */
-        uint32_t scl_main_st_to_int_st:1;
-        /** det_start_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked interrupt status bit for I2C_DET_START_INT interrupt.
-         */
-        uint32_t det_start_int_st:1;
-        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
-         *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
-         */
-        uint32_t slave_stretch_int_st:1;
-        /** general_call_int_st : RO; bitpos: [17]; default: 0;
-         *  The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.
-         */
-        uint32_t general_call_int_st:1;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} i2c_int_status_reg_t;
-
-
-/** Group: Command registers */
-/** Type of command register
- *  I2C command register
- */
-typedef union {
-    struct {
-        /** command0 : R/W; bitpos: [13:0]; default: 0;
-         *  This is the content of command 0. It consists of three parts:
-         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
-         *  Byte_num represents the number of bytes that need to be sent or received.
-         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
-         *  structure for more
-         *  Information.
-         */
-        uint32_t command:14;
-        uint32_t reserved_14:17;
-        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
-         *  When command 0 is done in I2C Master mode, this bit changes to high
-         *  level.
-         */
-        uint32_t command_done:1;
-    };
-    uint32_t val;
-} i2c_comd_reg_t;
-
-
-/** Group: Version register */
-/** Type of date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 537330177;
-         *  This is the the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} i2c_date_reg_t;
-
-typedef struct {
-    volatile i2c_scl_low_period_reg_t scl_low_period;
-    volatile i2c_ctr_reg_t ctr;
-    volatile i2c_sr_reg_t sr;
-    volatile i2c_to_reg_t to;
-    volatile i2c_slave_addr_reg_t slave_addr;
-    volatile i2c_fifo_st_reg_t fifo_st;
-    volatile i2c_fifo_conf_reg_t fifo_conf;
-    volatile i2c_data_reg_t data;
-    volatile i2c_int_raw_reg_t int_raw;
-    volatile i2c_int_clr_reg_t int_clr;
-    volatile i2c_int_ena_reg_t int_ena;
-    volatile i2c_int_status_reg_t int_status;
-    volatile i2c_sda_hold_reg_t sda_hold;
-    volatile i2c_sda_sample_reg_t sda_sample;
-    volatile i2c_scl_high_period_reg_t scl_high_period;
-    uint32_t reserved_03c;
-    volatile i2c_scl_start_hold_reg_t scl_start_hold;
-    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
-    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
-    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
-    volatile i2c_filter_cfg_reg_t filter_cfg;
-    volatile i2c_clk_conf_reg_t clk_conf;
-    volatile i2c_comd_reg_t comd[8];
-    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
-    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
-    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
-    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
-    uint32_t reserved_088[28];
-    volatile i2c_date_reg_t date;
-    uint32_t reserved_0fc;
-    volatile uint32_t txfifo_mem[32];
-    volatile uint32_t rxfifo_mem[32];
-} i2c_dev_t;
-
-extern i2c_dev_t I2C0;
-extern i2c_dev_t I2C1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/i2s_reg.h b/components/soc/esp32s3/include/soc/i2s_reg.h
deleted file mode 100644
index 3200bd25bc8..00000000000
--- a/components/soc/esp32s3/include/soc/i2s_reg.h
+++ /dev/null
@@ -1,1098 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_I2S_REG_H_
-#define _SOC_I2S_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0xC)
-/* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt.*/
-#define I2S_TX_HUNG_INT_RAW    (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_M  (BIT(3))
-#define I2S_TX_HUNG_INT_RAW_V  0x1
-#define I2S_TX_HUNG_INT_RAW_S  3
-/* I2S_RX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_rx_hung_int interrupt.*/
-#define I2S_RX_HUNG_INT_RAW    (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_M  (BIT(2))
-#define I2S_RX_HUNG_INT_RAW_V  0x1
-#define I2S_RX_HUNG_INT_RAW_S  2
-/* I2S_TX_DONE_INT_RAW : RO/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_tx_done_int interrupt.*/
-#define I2S_TX_DONE_INT_RAW    (BIT(1))
-#define I2S_TX_DONE_INT_RAW_M  (BIT(1))
-#define I2S_TX_DONE_INT_RAW_V  0x1
-#define I2S_TX_DONE_INT_RAW_S  1
-/* I2S_RX_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit  for the i2s_rx_done_int interrupt.*/
-#define I2S_RX_DONE_INT_RAW    (BIT(0))
-#define I2S_RX_DONE_INT_RAW_M  (BIT(0))
-#define I2S_RX_DONE_INT_RAW_V  0x1
-#define I2S_RX_DONE_INT_RAW_S  0
-
-#define I2S_INT_ST_REG(i)          (REG_I2S_BASE(i) + 0x10)
-/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_tx_hung_int interrupt.*/
-#define I2S_TX_HUNG_INT_ST    (BIT(3))
-#define I2S_TX_HUNG_INT_ST_M  (BIT(3))
-#define I2S_TX_HUNG_INT_ST_V  0x1
-#define I2S_TX_HUNG_INT_ST_S  3
-/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_rx_hung_int interrupt.*/
-#define I2S_RX_HUNG_INT_ST    (BIT(2))
-#define I2S_RX_HUNG_INT_ST_M  (BIT(2))
-#define I2S_RX_HUNG_INT_ST_V  0x1
-#define I2S_RX_HUNG_INT_ST_S  2
-/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_tx_done_int interrupt.*/
-#define I2S_TX_DONE_INT_ST    (BIT(1))
-#define I2S_TX_DONE_INT_ST_M  (BIT(1))
-#define I2S_TX_DONE_INT_ST_V  0x1
-#define I2S_TX_DONE_INT_ST_S  1
-/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The masked interrupt status bit  for the i2s_rx_done_int interrupt.*/
-#define I2S_RX_DONE_INT_ST    (BIT(0))
-#define I2S_RX_DONE_INT_ST_M  (BIT(0))
-#define I2S_RX_DONE_INT_ST_V  0x1
-#define I2S_RX_DONE_INT_ST_S  0
-
-#define I2S_INT_ENA_REG(i)          (REG_I2S_BASE(i) + 0x14)
-/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_tx_hung_int interrupt.*/
-#define I2S_TX_HUNG_INT_ENA    (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_M  (BIT(3))
-#define I2S_TX_HUNG_INT_ENA_V  0x1
-#define I2S_TX_HUNG_INT_ENA_S  3
-/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_rx_hung_int interrupt.*/
-#define I2S_RX_HUNG_INT_ENA    (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_M  (BIT(2))
-#define I2S_RX_HUNG_INT_ENA_V  0x1
-#define I2S_RX_HUNG_INT_ENA_S  2
-/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_tx_done_int interrupt.*/
-#define I2S_TX_DONE_INT_ENA    (BIT(1))
-#define I2S_TX_DONE_INT_ENA_M  (BIT(1))
-#define I2S_TX_DONE_INT_ENA_V  0x1
-#define I2S_TX_DONE_INT_ENA_S  1
-/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt enable bit  for the i2s_rx_done_int interrupt.*/
-#define I2S_RX_DONE_INT_ENA    (BIT(0))
-#define I2S_RX_DONE_INT_ENA_M  (BIT(0))
-#define I2S_RX_DONE_INT_ENA_V  0x1
-#define I2S_RX_DONE_INT_ENA_S  0
-
-#define I2S_INT_CLR_REG(i)          (REG_I2S_BASE(i) + 0x18)
-/* I2S_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_tx_hung_int interrupt.*/
-#define I2S_TX_HUNG_INT_CLR    (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_M  (BIT(3))
-#define I2S_TX_HUNG_INT_CLR_V  0x1
-#define I2S_TX_HUNG_INT_CLR_S  3
-/* I2S_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_rx_hung_int interrupt.*/
-#define I2S_RX_HUNG_INT_CLR    (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_M  (BIT(2))
-#define I2S_RX_HUNG_INT_CLR_V  0x1
-#define I2S_RX_HUNG_INT_CLR_S  2
-/* I2S_TX_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_tx_done_int interrupt.*/
-#define I2S_TX_DONE_INT_CLR    (BIT(1))
-#define I2S_TX_DONE_INT_CLR_M  (BIT(1))
-#define I2S_TX_DONE_INT_CLR_V  0x1
-#define I2S_TX_DONE_INT_CLR_S  1
-/* I2S_RX_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the i2s_rx_done_int interrupt.*/
-#define I2S_RX_DONE_INT_CLR    (BIT(0))
-#define I2S_RX_DONE_INT_CLR_M  (BIT(0))
-#define I2S_RX_DONE_INT_CLR_V  0x1
-#define I2S_RX_DONE_INT_CLR_S  0
-
-#define I2S_RX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x20)
-/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
-/*description: Configure the down sampling rate of PDM RX filter group1 module. 1: The  down sa
-mpling rate is 128. 0: down sampling rate is 64..*/
-#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(22))
-#define I2S_RX_PDM_SINC_DSR_16_EN_M  (BIT(22))
-#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x1
-#define I2S_RX_PDM_SINC_DSR_16_EN_S  22
-/* I2S_RX_PDM2PCM_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
-/*description: 1: Enable PDM2PCM RX mode. 0: DIsable..*/
-#define I2S_RX_PDM2PCM_EN    (BIT(21))
-#define I2S_RX_PDM2PCM_EN_M  (BIT(21))
-#define I2S_RX_PDM2PCM_EN_V  0x1
-#define I2S_RX_PDM2PCM_EN_S  21
-/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: 1: Enable I2S PDM Rx mode . 0: Disable..*/
-#define I2S_RX_PDM_EN    (BIT(20))
-#define I2S_RX_PDM_EN_M  (BIT(20))
-#define I2S_RX_PDM_EN_V  0x1
-#define I2S_RX_PDM_EN_S  20
-/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: 1: Enable I2S TDM Rx mode . 0: Disable..*/
-#define I2S_RX_TDM_EN    (BIT(19))
-#define I2S_RX_TDM_EN_M  (BIT(19))
-#define I2S_RX_TDM_EN_V  0x1
-#define I2S_RX_TDM_EN_S  19
-/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the
-MSB is received first..*/
-#define I2S_RX_BIT_ORDER    (BIT(18))
-#define I2S_RX_BIT_ORDER_M  (BIT(18))
-#define I2S_RX_BIT_ORDER_V  0x1
-#define I2S_RX_BIT_ORDER_S  18
-/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: 0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
-  1: WS should be 1 when receiving left channel data, and WS is 0in right channe
-l. .*/
-#define I2S_RX_WS_IDLE_POL    (BIT(17))
-#define I2S_RX_WS_IDLE_POL_M  (BIT(17))
-#define I2S_RX_WS_IDLE_POL_V  0x1
-#define I2S_RX_WS_IDLE_POL_S  17
-/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits..*/
-#define I2S_RX_24_FILL_EN    (BIT(16))
-#define I2S_RX_24_FILL_EN_M  (BIT(16))
-#define I2S_RX_24_FILL_EN_V  0x1
-#define I2S_RX_24_FILL_EN_S  16
-/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode..*/
-#define I2S_RX_LEFT_ALIGN    (BIT(15))
-#define I2S_RX_LEFT_ALIGN_M  (BIT(15))
-#define I2S_RX_LEFT_ALIGN_V  0x1
-#define I2S_RX_LEFT_ALIGN_S  15
-/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */
-/*description: 0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start
-is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is
-full..*/
-#define I2S_RX_STOP_MODE    0x00000003
-#define I2S_RX_STOP_MODE_M  ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S))
-#define I2S_RX_STOP_MODE_V  0x3
-#define I2S_RX_STOP_MODE_S  13
-/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to bypass Compress/Decompress module for received data..*/
-#define I2S_RX_PCM_BYPASS    (BIT(12))
-#define I2S_RX_PCM_BYPASS_M  (BIT(12))
-#define I2S_RX_PCM_BYPASS_V  0x1
-#define I2S_RX_PCM_BYPASS_S  12
-/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */
-/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (l
-toa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &.*/
-#define I2S_RX_PCM_CONF    0x00000003
-#define I2S_RX_PCM_CONF_M  ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
-#define I2S_RX_PCM_CONF_V  0x3
-#define I2S_RX_PCM_CONF_S  10
-/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: 1: The first channel data value is valid in I2S RX mono mode.   0: The second ch
-annel data value is valid in I2S RX mono mode..*/
-#define I2S_RX_MONO_FST_VLD    (BIT(9))
-#define I2S_RX_MONO_FST_VLD_M  (BIT(9))
-#define I2S_RX_MONO_FST_VLD_V  0x1
-#define I2S_RX_MONO_FST_VLD_S  9
-/* I2S_RX_UPDATE : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. T
-his bit will be cleared by hardware after update register done..*/
-#define I2S_RX_UPDATE    (BIT(8))
-#define I2S_RX_UPDATE_M  (BIT(8))
-#define I2S_RX_UPDATE_V  0x1
-#define I2S_RX_UPDATE_S  8
-/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr va
-lue..*/
-#define I2S_RX_BIG_ENDIAN    (BIT(7))
-#define I2S_RX_BIG_ENDIAN_M  (BIT(7))
-#define I2S_RX_BIG_ENDIAN_V  0x1
-#define I2S_RX_BIG_ENDIAN_S  7
-/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable receiver  in mono mode.*/
-#define I2S_RX_MONO    (BIT(5))
-#define I2S_RX_MONO_M  (BIT(5))
-#define I2S_RX_MONO_V  0x1
-#define I2S_RX_MONO_S  5
-/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable slave receiver mode.*/
-#define I2S_RX_SLAVE_MOD    (BIT(3))
-#define I2S_RX_SLAVE_MOD_M  (BIT(3))
-#define I2S_RX_SLAVE_MOD_V  0x1
-#define I2S_RX_SLAVE_MOD_S  3
-/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to start receiving data.*/
-#define I2S_RX_START    (BIT(2))
-#define I2S_RX_START_M  (BIT(2))
-#define I2S_RX_START_V  0x1
-#define I2S_RX_START_S  2
-/* I2S_RX_FIFO_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to reset Rx AFIFO.*/
-#define I2S_RX_FIFO_RESET    (BIT(1))
-#define I2S_RX_FIFO_RESET_M  (BIT(1))
-#define I2S_RX_FIFO_RESET_V  0x1
-#define I2S_RX_FIFO_RESET_S  1
-/* I2S_RX_RESET : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to reset receiver.*/
-#define I2S_RX_RESET    (BIT(0))
-#define I2S_RX_RESET_M  (BIT(0))
-#define I2S_RX_RESET_V  0x1
-#define I2S_RX_RESET_S  0
-
-#define I2S_TX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x24)
-/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Enable signal loop back mode with transmitter module and receiver module sharing
- the same WS and BCK signals..*/
-#define I2S_SIG_LOOPBACK    (BIT(27))
-#define I2S_SIG_LOOPBACK_M  (BIT(27))
-#define I2S_SIG_LOOPBACK_V  0x1
-#define I2S_SIG_LOOPBACK_S  27
-/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */
-/*description: I2S transmitter channel mode configuration bits..*/
-#define I2S_TX_CHAN_MOD    0x00000007
-#define I2S_TX_CHAN_MOD_M  ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S))
-#define I2S_TX_CHAN_MOD_V  0x7
-#define I2S_TX_CHAN_MOD_S  24
-/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
-/*description: 1: Enable I2S PDM Tx mode . 0: Disable..*/
-#define I2S_TX_PDM_EN    (BIT(20))
-#define I2S_TX_PDM_EN_M  (BIT(20))
-#define I2S_TX_PDM_EN_V  0x1
-#define I2S_TX_PDM_EN_S  20
-/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
-/*description: 1: Enable I2S TDM Tx mode . 0: Disable..*/
-#define I2S_TX_TDM_EN    (BIT(19))
-#define I2S_TX_TDM_EN_M  (BIT(19))
-#define I2S_TX_TDM_EN_V  0x1
-#define I2S_TX_TDM_EN_S  19
-/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
-/*description: I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB
-is sent first..*/
-#define I2S_TX_BIT_ORDER    (BIT(18))
-#define I2S_TX_BIT_ORDER_M  (BIT(18))
-#define I2S_TX_BIT_ORDER_V  0x1
-#define I2S_TX_BIT_ORDER_S  18
-/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
-/*description: 0: WS should be 0 when sending left channel data, and WS is 1in right channel.
-1: WS should be 1 when sending left channel data, and WS is 0in right channel. .*/
-#define I2S_TX_WS_IDLE_POL    (BIT(17))
-#define I2S_TX_WS_IDLE_POL_M  (BIT(17))
-#define I2S_TX_WS_IDLE_POL_V  0x1
-#define I2S_TX_WS_IDLE_POL_S  17
-/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
-/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode.*/
-#define I2S_TX_24_FILL_EN    (BIT(16))
-#define I2S_TX_24_FILL_EN_M  (BIT(16))
-#define I2S_TX_24_FILL_EN_V  0x1
-#define I2S_TX_24_FILL_EN_S  16
-/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode..*/
-#define I2S_TX_LEFT_ALIGN    (BIT(15))
-#define I2S_TX_LEFT_ALIGN_M  (BIT(15))
-#define I2S_TX_LEFT_ALIGN_V  0x1
-#define I2S_TX_LEFT_ALIGN_S  15
-/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emt
-py.*/
-#define I2S_TX_STOP_EN    (BIT(13))
-#define I2S_TX_STOP_EN_M  (BIT(13))
-#define I2S_TX_STOP_EN_V  0x1
-#define I2S_TX_STOP_EN_S  13
-/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to bypass  Compress/Decompress module for transmitted data..*/
-#define I2S_TX_PCM_BYPASS    (BIT(12))
-#define I2S_TX_PCM_BYPASS_M  (BIT(12))
-#define I2S_TX_PCM_BYPASS_V  0x1
-#define I2S_TX_PCM_BYPASS_S  12
-/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (l
-toa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &.*/
-#define I2S_TX_PCM_CONF    0x00000003
-#define I2S_TX_PCM_CONF_M  ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
-#define I2S_TX_PCM_CONF_V  0x3
-#define I2S_TX_PCM_CONF_S  10
-/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: 1: The first channel data value is valid in I2S TX mono mode.   0: The second ch
-annel data value is valid in I2S TX mono mode..*/
-#define I2S_TX_MONO_FST_VLD    (BIT(9))
-#define I2S_TX_MONO_FST_VLD_M  (BIT(9))
-#define I2S_TX_MONO_FST_VLD_V  0x1
-#define I2S_TX_MONO_FST_VLD_S  9
-/* I2S_TX_UPDATE : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. T
-his bit will be cleared by hardware after update register done..*/
-#define I2S_TX_UPDATE    (BIT(8))
-#define I2S_TX_UPDATE_M  (BIT(8))
-#define I2S_TX_UPDATE_V  0x1
-#define I2S_TX_UPDATE_S  8
-/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr v
-alue..*/
-#define I2S_TX_BIG_ENDIAN    (BIT(7))
-#define I2S_TX_BIG_ENDIAN_M  (BIT(7))
-#define I2S_TX_BIG_ENDIAN_V  0x1
-#define I2S_TX_BIG_ENDIAN_S  7
-/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: 1: The value of Left channel data is equal to the value of right channel data in
- I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg
-_i2s_single_data in I2S TX mono mode or TDM channel select mode..*/
-#define I2S_TX_CHAN_EQUAL    (BIT(6))
-#define I2S_TX_CHAN_EQUAL_M  (BIT(6))
-#define I2S_TX_CHAN_EQUAL_V  0x1
-#define I2S_TX_CHAN_EQUAL_S  6
-/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable transmitter in mono mode  .*/
-#define I2S_TX_MONO    (BIT(5))
-#define I2S_TX_MONO_M  (BIT(5))
-#define I2S_TX_MONO_V  0x1
-#define I2S_TX_MONO_S  5
-/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to enable slave transmitter mode  .*/
-#define I2S_TX_SLAVE_MOD    (BIT(3))
-#define I2S_TX_SLAVE_MOD_M  (BIT(3))
-#define I2S_TX_SLAVE_MOD_V  0x1
-#define I2S_TX_SLAVE_MOD_S  3
-/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to start transmitting data .*/
-#define I2S_TX_START    (BIT(2))
-#define I2S_TX_START_M  (BIT(2))
-#define I2S_TX_START_V  0x1
-#define I2S_TX_START_S  2
-/* I2S_TX_FIFO_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to reset Tx AFIFO.*/
-#define I2S_TX_FIFO_RESET    (BIT(1))
-#define I2S_TX_FIFO_RESET_M  (BIT(1))
-#define I2S_TX_FIFO_RESET_V  0x1
-#define I2S_TX_FIFO_RESET_S  1
-/* I2S_TX_RESET : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to reset transmitter.*/
-#define I2S_TX_RESET    (BIT(0))
-#define I2S_TX_RESET_M  (BIT(0))
-#define I2S_TX_RESET_V  0x1
-#define I2S_TX_RESET_S  0
-
-#define I2S_RX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x28)
-/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to enable receiver in Phillips standard mode.*/
-#define I2S_RX_MSB_SHIFT    (BIT(29))
-#define I2S_RX_MSB_SHIFT_M  (BIT(29))
-#define I2S_RX_MSB_SHIFT_V  0x1
-#define I2S_RX_MSB_SHIFT_S  29
-/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hf ; */
-/*description: The Rx bit number for each channel minus 1in TDM mode..*/
-#define I2S_RX_TDM_CHAN_BITS    0x0000001F
-#define I2S_RX_TDM_CHAN_BITS_M  ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S))
-#define I2S_RX_TDM_CHAN_BITS_V  0x1F
-#define I2S_RX_TDM_CHAN_BITS_S  24
-/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hf ; */
-/*description: I2S Rx half sample bits -1..*/
-#define I2S_RX_HALF_SAMPLE_BITS    0x0000003F
-#define I2S_RX_HALF_SAMPLE_BITS_M  ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S))
-#define I2S_RX_HALF_SAMPLE_BITS_V  0x3F
-#define I2S_RX_HALF_SAMPLE_BITS_S  18
-/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hf ; */
-/*description: Set the bits to configure the valid data bit length of I2S receiver channel. 7:
-all the valid channel data is in 8-bit-mode. 15: all the valid channel data is i
-n 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the vali
-d channel data is in 32-bit-mode..*/
-#define I2S_RX_BITS_MOD    0x0000001F
-#define I2S_RX_BITS_MOD_M  ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
-#define I2S_RX_BITS_MOD_V  0x1F
-#define I2S_RX_BITS_MOD_S  13
-/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
-/*description: Bit clock configuration bits in receiver mode. .*/
-#define I2S_RX_BCK_DIV_NUM    0x0000003F
-#define I2S_RX_BCK_DIV_NUM_M  ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S))
-#define I2S_RX_BCK_DIV_NUM_V  0x3F
-#define I2S_RX_BCK_DIV_NUM_S  7
-/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
-/*description:  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck.*/
-#define I2S_RX_TDM_WS_WIDTH    0x0000007F
-#define I2S_RX_TDM_WS_WIDTH_M  ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S))
-#define I2S_RX_TDM_WS_WIDTH_V  0x7F
-#define I2S_RX_TDM_WS_WIDTH_S  0
-
-#define I2S_TX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x2C)
-/* I2S_TX_BCK_NO_DLY : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed
- to generate pos/neg edge in master mode..*/
-#define I2S_TX_BCK_NO_DLY    (BIT(30))
-#define I2S_TX_BCK_NO_DLY_M  (BIT(30))
-#define I2S_TX_BCK_NO_DLY_V  0x1
-#define I2S_TX_BCK_NO_DLY_S  30
-/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: Set this bit to enable transmitter in Phillips standard mode.*/
-#define I2S_TX_MSB_SHIFT    (BIT(29))
-#define I2S_TX_MSB_SHIFT_M  (BIT(29))
-#define I2S_TX_MSB_SHIFT_V  0x1
-#define I2S_TX_MSB_SHIFT_S  29
-/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hf ; */
-/*description: The Tx bit number for each channel minus 1in TDM mode..*/
-#define I2S_TX_TDM_CHAN_BITS    0x0000001F
-#define I2S_TX_TDM_CHAN_BITS_M  ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S))
-#define I2S_TX_TDM_CHAN_BITS_V  0x1F
-#define I2S_TX_TDM_CHAN_BITS_S  24
-/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hf ; */
-/*description:  I2S Tx half sample bits -1..*/
-#define I2S_TX_HALF_SAMPLE_BITS    0x0000003F
-#define I2S_TX_HALF_SAMPLE_BITS_M  ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S))
-#define I2S_TX_HALF_SAMPLE_BITS_V  0x3F
-#define I2S_TX_HALF_SAMPLE_BITS_S  18
-/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hf ; */
-/*description: Set the bits to configure the valid data bit length of I2S transmitter channel.
-7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data i
-s in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the v
-alid channel data is in 32-bit-mode..*/
-#define I2S_TX_BITS_MOD    0x0000001F
-#define I2S_TX_BITS_MOD_M  ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S))
-#define I2S_TX_BITS_MOD_V  0x1F
-#define I2S_TX_BITS_MOD_S  13
-/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
-/*description: Bit clock configuration bits in transmitter mode. .*/
-#define I2S_TX_BCK_DIV_NUM    0x0000003F
-#define I2S_TX_BCK_DIV_NUM_M  ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S))
-#define I2S_TX_BCK_DIV_NUM_V  0x3F
-#define I2S_TX_BCK_DIV_NUM_S  7
-/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
-/*description:  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck.*/
-#define I2S_TX_TDM_WS_WIDTH    0x0000007F
-#define I2S_TX_TDM_WS_WIDTH_M  ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S))
-#define I2S_TX_TDM_WS_WIDTH_V  0x7F
-#define I2S_TX_TDM_WS_WIDTH_S  0
-
-#define I2S_RX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x30)
-/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description:  0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MC
-LK_OUT. .*/
-#define I2S_MCLK_SEL    (BIT(29))
-#define I2S_MCLK_SEL_M  (BIT(29))
-#define I2S_MCLK_SEL_V  0x1
-#define I2S_MCLK_SEL_S  29
-/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
-/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_
-in..*/
-#define I2S_RX_CLK_SEL    0x00000003
-#define I2S_RX_CLK_SEL_M  ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S))
-#define I2S_RX_CLK_SEL_V  0x3
-#define I2S_RX_CLK_SEL_S  27
-/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: I2S Rx module clock enable signal..*/
-#define I2S_RX_CLK_ACTIVE    (BIT(26))
-#define I2S_RX_CLK_ACTIVE_M  (BIT(26))
-#define I2S_RX_CLK_ACTIVE_V  0x1
-#define I2S_RX_CLK_ACTIVE_S  26
-/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
-/*description: Integral I2S clock divider value.*/
-#define I2S_RX_CLKM_DIV_NUM    0x000000FF
-#define I2S_RX_CLKM_DIV_NUM_M  ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S))
-#define I2S_RX_CLKM_DIV_NUM_V  0xFF
-#define I2S_RX_CLKM_DIV_NUM_S  0
-
-#define I2S_TX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x34)
-/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable clk gate.*/
-#define I2S_CLK_EN    (BIT(29))
-#define I2S_CLK_EN_M  (BIT(29))
-#define I2S_CLK_EN_V  0x1
-#define I2S_CLK_EN_S  29
-/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
-/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCL
-K_in..*/
-#define I2S_TX_CLK_SEL    0x00000003
-#define I2S_TX_CLK_SEL_M  ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S))
-#define I2S_TX_CLK_SEL_V  0x3
-#define I2S_TX_CLK_SEL_S  27
-/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: I2S Tx module clock enable signal..*/
-#define I2S_TX_CLK_ACTIVE    (BIT(26))
-#define I2S_TX_CLK_ACTIVE_M  (BIT(26))
-#define I2S_TX_CLK_ACTIVE_V  0x1
-#define I2S_TX_CLK_ACTIVE_S  26
-/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
-/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will
- be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b
- <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
-(n+1)-div] + y * (n+1)-div. .*/
-#define I2S_TX_CLKM_DIV_NUM    0x000000FF
-#define I2S_TX_CLKM_DIV_NUM_M  ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S))
-#define I2S_TX_CLKM_DIV_NUM_V  0xFF
-#define I2S_TX_CLKM_DIV_NUM_S  0
-
-#define I2S_RX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x38)
-/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-I2S_RX_CLKM_DIV_YN1 is 1. .*/
-#define I2S_RX_CLKM_DIV_YN1    (BIT(27))
-#define I2S_RX_CLKM_DIV_YN1_M  (BIT(27))
-#define I2S_RX_CLKM_DIV_YN1_V  0x1
-#define I2S_RX_CLKM_DIV_YN1_S  27
-/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
-/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the valu
-e of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. .*/
-#define I2S_RX_CLKM_DIV_X    0x000001FF
-#define I2S_RX_CLKM_DIV_X_M  ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S))
-#define I2S_RX_CLKM_DIV_X_V  0x1FF
-#define I2S_RX_CLKM_DIV_X_S  18
-/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
-/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value o
-f I2S_RX_CLKM_DIV_Y is (a%(a-b)). .*/
-#define I2S_RX_CLKM_DIV_Y    0x000001FF
-#define I2S_RX_CLKM_DIV_Y_M  ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S))
-#define I2S_RX_CLKM_DIV_Y_V  0x1FF
-#define I2S_RX_CLKM_DIV_Y_S  9
-/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S
-_RX_CLKM_DIV_Z is (a-b). .*/
-#define I2S_RX_CLKM_DIV_Z    0x000001FF
-#define I2S_RX_CLKM_DIV_Z_M  ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S))
-#define I2S_RX_CLKM_DIV_Z_V  0x1FF
-#define I2S_RX_CLKM_DIV_Z_S  0
-
-#define I2S_TX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x3C)
-/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-I2S_TX_CLKM_DIV_YN1 is 1. .*/
-#define I2S_TX_CLKM_DIV_YN1    (BIT(27))
-#define I2S_TX_CLKM_DIV_YN1_M  (BIT(27))
-#define I2S_TX_CLKM_DIV_YN1_V  0x1
-#define I2S_TX_CLKM_DIV_YN1_S  27
-/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
-/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the valu
-e of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. .*/
-#define I2S_TX_CLKM_DIV_X    0x000001FF
-#define I2S_TX_CLKM_DIV_X_M  ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S))
-#define I2S_TX_CLKM_DIV_X_V  0x1FF
-#define I2S_TX_CLKM_DIV_X_S  18
-/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
-/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value o
-f I2S_TX_CLKM_DIV_Y is (a%(a-b)). .*/
-#define I2S_TX_CLKM_DIV_Y    0x000001FF
-#define I2S_TX_CLKM_DIV_Y_M  ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S))
-#define I2S_TX_CLKM_DIV_Y_V  0x1FF
-#define I2S_TX_CLKM_DIV_Y_S  9
-/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
-/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S
-_TX_CLKM_DIV_Z is (a-b). .*/
-#define I2S_TX_CLKM_DIV_Z    0x000001FF
-#define I2S_TX_CLKM_DIV_Z_M  ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S))
-#define I2S_TX_CLKM_DIV_Z_V  0x1FF
-#define I2S_TX_CLKM_DIV_Z_S  0
-
-#define I2S_TX_PCM2PDM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x40)
-/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: I2S TX PDM Converter enable.*/
-#define I2S_PCM2PDM_CONV_EN    (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_M  (BIT(25))
-#define I2S_PCM2PDM_CONV_EN_V  0x1
-#define I2S_PCM2PDM_CONV_EN_S  25
-/* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: I2S TX PDM dac 2channel enable.*/
-#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_M  (BIT(24))
-#define I2S_TX_PDM_DAC_MODE_EN_V  0x1
-#define I2S_TX_PDM_DAC_MODE_EN_S  24
-/* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: I2S TX PDM dac mode enable.*/
-#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_M  (BIT(23))
-#define I2S_TX_PDM_DAC_2OUT_EN_V  0x1
-#define I2S_TX_PDM_DAC_2OUT_EN_S  23
-/* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: I2S TX PDM sigmadelta dither value.*/
-#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (BIT(22))
-#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x1
-#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
-/* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: I2S TX PDM sigmadelta dither2 value.*/
-#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (BIT(21))
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x1
-#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
-/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */
-/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
-/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */
-/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
-#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003
-#define I2S_TX_PDM_SINC_IN_SHIFT_M  ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
-#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
-/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */
-/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
-#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003
-#define I2S_TX_PDM_LP_IN_SHIFT_M  ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
-#define I2S_TX_PDM_LP_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_LP_IN_SHIFT_S  15
-/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
-/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
-#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003
-#define I2S_TX_PDM_HP_IN_SHIFT_M  ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
-#define I2S_TX_PDM_HP_IN_SHIFT_V  0x3
-#define I2S_TX_PDM_HP_IN_SHIFT_S  13
-/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */
-/*description: I2S TX PDM prescale for sigmadelta.*/
-#define I2S_TX_PDM_PRESCALE    0x000000FF
-#define I2S_TX_PDM_PRESCALE_M  ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
-#define I2S_TX_PDM_PRESCALE_V  0xFF
-#define I2S_TX_PDM_PRESCALE_S  5
-/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */
-/*description: I2S TX PDM OSR2 value.*/
-#define I2S_TX_PDM_SINC_OSR2    0x0000000F
-#define I2S_TX_PDM_SINC_OSR2_M  ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
-#define I2S_TX_PDM_SINC_OSR2_V  0xF
-#define I2S_TX_PDM_SINC_OSR2_S  1
-/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/
-#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
-#define I2S_TX_PDM_HP_BYPASS_M  (BIT(0))
-#define I2S_TX_PDM_HP_BYPASS_V  0x1
-#define I2S_TX_PDM_HP_BYPASS_S  0
-
-#define I2S_TX_PCM2PDM_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x44)
-/* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */
-/*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL
-T12_0[2:0]).*/
-#define I2S_TX_IIR_HP_MULT12_0    0x00000007
-#define I2S_TX_IIR_HP_MULT12_0_M  ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S))
-#define I2S_TX_IIR_HP_MULT12_0_V  0x7
-#define I2S_TX_IIR_HP_MULT12_0_S  23
-/* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */
-/*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL
-T12_5[2:0]).*/
-#define I2S_TX_IIR_HP_MULT12_5    0x00000007
-#define I2S_TX_IIR_HP_MULT12_5_M  ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S))
-#define I2S_TX_IIR_HP_MULT12_5_V  0x7
-#define I2S_TX_IIR_HP_MULT12_5_S  20
-/* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */
-/*description: I2S TX PDM Fs.*/
-#define I2S_TX_PDM_FS    0x000003FF
-#define I2S_TX_PDM_FS_M  ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
-#define I2S_TX_PDM_FS_V  0x3FF
-#define I2S_TX_PDM_FS_S  10
-/* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */
-/*description: I2S TX PDM Fp.*/
-#define I2S_TX_PDM_FP    0x000003FF
-#define I2S_TX_PDM_FP_M  ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
-#define I2S_TX_PDM_FP_V  0x3FF
-#define I2S_TX_PDM_FP_S  0
-
-#define I2S_RX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x50)
-/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
-/*description: The total channel number of I2S TX TDM mode..*/
-#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000F
-#define I2S_RX_TDM_TOT_CHAN_NUM_M  ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S))
-#define I2S_RX_TDM_TOT_CHAN_NUM_V  0xF
-#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
-/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
- 0 in this channel..*/
-#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_M  (BIT(15))
-#define I2S_RX_TDM_CHAN15_EN_V  0x1
-#define I2S_RX_TDM_CHAN15_EN_S  15
-/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
- 0 in this channel..*/
-#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_M  (BIT(14))
-#define I2S_RX_TDM_CHAN14_EN_V  0x1
-#define I2S_RX_TDM_CHAN14_EN_S  14
-/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
- 0 in this channel..*/
-#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_M  (BIT(13))
-#define I2S_RX_TDM_CHAN13_EN_V  0x1
-#define I2S_RX_TDM_CHAN13_EN_S  13
-/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
- 0 in this channel..*/
-#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_M  (BIT(12))
-#define I2S_RX_TDM_CHAN12_EN_V  0x1
-#define I2S_RX_TDM_CHAN12_EN_S  12
-/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
- 0 in this channel..*/
-#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_M  (BIT(11))
-#define I2S_RX_TDM_CHAN11_EN_V  0x1
-#define I2S_RX_TDM_CHAN11_EN_S  11
-/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
- 0 in this channel..*/
-#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_M  (BIT(10))
-#define I2S_RX_TDM_CHAN10_EN_V  0x1
-#define I2S_RX_TDM_CHAN10_EN_S  10
-/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
- 0 in this channel..*/
-#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_M  (BIT(9))
-#define I2S_RX_TDM_CHAN9_EN_V  0x1
-#define I2S_RX_TDM_CHAN9_EN_S  9
-/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
- 0 in this channel..*/
-#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_M  (BIT(8))
-#define I2S_RX_TDM_CHAN8_EN_V  0x1
-#define I2S_RX_TDM_CHAN8_EN_S  8
-/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, jus
-t input 0 in this channel..*/
-#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_M  (BIT(7))
-#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
-/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, jus
-t input 0 in this channel..*/
-#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_M  (BIT(6))
-#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
-/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, jus
-t input 0 in this channel..*/
-#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_M  (BIT(5))
-#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
-/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, jus
-t input 0 in this channel..*/
-#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_M  (BIT(4))
-#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
-/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, jus
-t input 0 in this channel..*/
-#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_M  (BIT(3))
-#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
-/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, jus
-t input 0 in this channel..*/
-#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_M  (BIT(2))
-#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
-/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, jus
-t input 0 in this channel..*/
-#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_M  (BIT(1))
-#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
-/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, jus
-t input 0 in this channel..*/
-#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_M  (BIT(0))
-#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x1
-#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
-
-#define I2S_TX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x54)
-/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, a
-nd only the data of the enabled channels is sent, then this bit should be set. C
-lear it when all the data stored in DMA TX buffer is for enabled channels..*/
-#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_M  (BIT(20))
-#define I2S_TX_TDM_SKIP_MSK_EN_V  0x1
-#define I2S_TX_TDM_SKIP_MSK_EN_S  20
-/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
-/*description: The total channel number of I2S TX TDM mode..*/
-#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000F
-#define I2S_TX_TDM_TOT_CHAN_NUM_M  ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S))
-#define I2S_TX_TDM_TOT_CHAN_NUM_V  0xF
-#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
-/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_M  (BIT(15))
-#define I2S_TX_TDM_CHAN15_EN_V  0x1
-#define I2S_TX_TDM_CHAN15_EN_S  15
-/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_M  (BIT(14))
-#define I2S_TX_TDM_CHAN14_EN_V  0x1
-#define I2S_TX_TDM_CHAN14_EN_S  14
-/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_M  (BIT(13))
-#define I2S_TX_TDM_CHAN13_EN_V  0x1
-#define I2S_TX_TDM_CHAN13_EN_S  13
-/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_M  (BIT(12))
-#define I2S_TX_TDM_CHAN12_EN_V  0x1
-#define I2S_TX_TDM_CHAN12_EN_S  12
-/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_M  (BIT(11))
-#define I2S_TX_TDM_CHAN11_EN_V  0x1
-#define I2S_TX_TDM_CHAN11_EN_S  11
-/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_M  (BIT(10))
-#define I2S_TX_TDM_CHAN10_EN_V  0x1
-#define I2S_TX_TDM_CHAN10_EN_S  10
-/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_M  (BIT(9))
-#define I2S_TX_TDM_CHAN9_EN_V  0x1
-#define I2S_TX_TDM_CHAN9_EN_S  9
-/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_M  (BIT(8))
-#define I2S_TX_TDM_CHAN8_EN_V  0x1
-#define I2S_TX_TDM_CHAN8_EN_S  8
-/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_M  (BIT(7))
-#define I2S_TX_TDM_CHAN7_EN_V  0x1
-#define I2S_TX_TDM_CHAN7_EN_S  7
-/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_M  (BIT(6))
-#define I2S_TX_TDM_CHAN6_EN_V  0x1
-#define I2S_TX_TDM_CHAN6_EN_S  6
-/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_M  (BIT(5))
-#define I2S_TX_TDM_CHAN5_EN_V  0x1
-#define I2S_TX_TDM_CHAN5_EN_S  5
-/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_M  (BIT(4))
-#define I2S_TX_TDM_CHAN4_EN_V  0x1
-#define I2S_TX_TDM_CHAN4_EN_S  4
-/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_M  (BIT(3))
-#define I2S_TX_TDM_CHAN3_EN_V  0x1
-#define I2S_TX_TDM_CHAN3_EN_S  3
-/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_M  (BIT(2))
-#define I2S_TX_TDM_CHAN2_EN_V  0x1
-#define I2S_TX_TDM_CHAN2_EN_S  2
-/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_M  (BIT(1))
-#define I2S_TX_TDM_CHAN1_EN_V  0x1
-#define I2S_TX_TDM_CHAN1_EN_S  1
-/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
-/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
-ut 0 in this channel..*/
-#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_M  (BIT(0))
-#define I2S_TX_TDM_CHAN0_EN_V  0x1
-#define I2S_TX_TDM_CHAN0_EN_S  0
-
-#define I2S_RX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x58)
-/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-delay by neg edge. 3: not used..*/
-#define I2S_RX_BCK_IN_DM    0x00000003
-#define I2S_RX_BCK_IN_DM_M  ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S))
-#define I2S_RX_BCK_IN_DM_V  0x3
-#define I2S_RX_BCK_IN_DM_S  28
-/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: d
-elay by neg edge. 3: not used..*/
-#define I2S_RX_WS_IN_DM    0x00000003
-#define I2S_RX_WS_IN_DM_M  ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S))
-#define I2S_RX_WS_IN_DM_V  0x3
-#define I2S_RX_WS_IN_DM_S  24
-/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- delay by neg edge. 3: not used..*/
-#define I2S_RX_BCK_OUT_DM    0x00000003
-#define I2S_RX_BCK_OUT_DM_M  ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S))
-#define I2S_RX_BCK_OUT_DM_V  0x3
-#define I2S_RX_BCK_OUT_DM_S  20
-/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
-delay by neg edge. 3: not used..*/
-#define I2S_RX_WS_OUT_DM    0x00000003
-#define I2S_RX_WS_OUT_DM_M  ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S))
-#define I2S_RX_WS_OUT_DM_V  0x3
-#define I2S_RX_WS_OUT_DM_S  16
-/* I2S_RX_SD3_IN_DM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
-delay by neg edge. 3: not used..*/
-#define I2S_RX_SD3_IN_DM    0x00000003
-#define I2S_RX_SD3_IN_DM_M  ((I2S_RX_SD3_IN_DM_V)<<(I2S_RX_SD3_IN_DM_S))
-#define I2S_RX_SD3_IN_DM_V  0x3
-#define I2S_RX_SD3_IN_DM_S  12
-/* I2S_RX_SD2_IN_DM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
-delay by neg edge. 3: not used..*/
-#define I2S_RX_SD2_IN_DM    0x00000003
-#define I2S_RX_SD2_IN_DM_M  ((I2S_RX_SD2_IN_DM_V)<<(I2S_RX_SD2_IN_DM_S))
-#define I2S_RX_SD2_IN_DM_V  0x3
-#define I2S_RX_SD2_IN_DM_S  8
-/* I2S_RX_SD1_IN_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
-delay by neg edge. 3: not used..*/
-#define I2S_RX_SD1_IN_DM    0x00000003
-#define I2S_RX_SD1_IN_DM_M  ((I2S_RX_SD1_IN_DM_V)<<(I2S_RX_SD1_IN_DM_S))
-#define I2S_RX_SD1_IN_DM_V  0x3
-#define I2S_RX_SD1_IN_DM_S  4
-/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: d
-elay by neg edge. 3: not used..*/
-#define I2S_RX_SD_IN_DM    0x00000003
-#define I2S_RX_SD_IN_DM_M  ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S))
-#define I2S_RX_SD_IN_DM_V  0x3
-#define I2S_RX_SD_IN_DM_S  0
-
-#define I2S_TX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x5C)
-/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
-/*description: The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
-delay by neg edge. 3: not used..*/
-#define I2S_TX_BCK_IN_DM    0x00000003
-#define I2S_TX_BCK_IN_DM_M  ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S))
-#define I2S_TX_BCK_IN_DM_V  0x3
-#define I2S_TX_BCK_IN_DM_S  28
-/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
-/*description: The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: d
-elay by neg edge. 3: not used..*/
-#define I2S_TX_WS_IN_DM    0x00000003
-#define I2S_TX_WS_IN_DM_M  ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S))
-#define I2S_TX_WS_IN_DM_V  0x3
-#define I2S_TX_WS_IN_DM_S  24
-/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
-/*description: The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
- delay by neg edge. 3: not used..*/
-#define I2S_TX_BCK_OUT_DM    0x00000003
-#define I2S_TX_BCK_OUT_DM_M  ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S))
-#define I2S_TX_BCK_OUT_DM_V  0x3
-#define I2S_TX_BCK_OUT_DM_S  20
-/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
-delay by neg edge. 3: not used..*/
-#define I2S_TX_WS_OUT_DM    0x00000003
-#define I2S_TX_WS_OUT_DM_M  ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S))
-#define I2S_TX_WS_OUT_DM_V  0x3
-#define I2S_TX_WS_OUT_DM_S  16
-/* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
- delay by neg edge. 3: not used..*/
-#define I2S_TX_SD1_OUT_DM    0x00000003
-#define I2S_TX_SD1_OUT_DM_M  ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S))
-#define I2S_TX_SD1_OUT_DM_V  0x3
-#define I2S_TX_SD1_OUT_DM_S  4
-/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
-delay by neg edge. 3: not used..*/
-#define I2S_TX_SD_OUT_DM    0x00000003
-#define I2S_TX_SD_OUT_DM_M  ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S))
-#define I2S_TX_SD_OUT_DM_V  0x3
-#define I2S_TX_SD_OUT_DM_S  0
-
-#define I2S_LC_HUNG_CONF_REG(i)          (REG_I2S_BASE(i) + 0x60)
-/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: The enable bit for FIFO timeout.*/
-#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_M  (BIT(11))
-#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x1
-#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
-/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
-/*description: The bits are used to scale tick counter threshold. The tick counter is reset whe
-n counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/
-#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x7
-#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
-/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
-/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
- when fifo hung counter is equal to this value  .*/
-#define I2S_LC_FIFO_TIMEOUT    0x000000FF
-#define I2S_LC_FIFO_TIMEOUT_M  ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S))
-#define I2S_LC_FIFO_TIMEOUT_V  0xFF
-#define I2S_LC_FIFO_TIMEOUT_S  0
-
-#define I2S_RXEOF_NUM_REG(i)          (REG_I2S_BASE(i) + 0x64)
-/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */
-/*description: The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0
-] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel..*/
-#define I2S_RX_EOF_NUM    0x00000FFF
-#define I2S_RX_EOF_NUM_M  ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
-#define I2S_RX_EOF_NUM_V  0xFFF
-#define I2S_RX_EOF_NUM_S  0
-
-#define I2S_CONF_SIGLE_DATA_REG(i)          (REG_I2S_BASE(i) + 0x68)
-/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: The configured constant channel data to be sent out..*/
-#define I2S_SINGLE_DATA    0xFFFFFFFF
-#define I2S_SINGLE_DATA_M  ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S))
-#define I2S_SINGLE_DATA_V  0xFFFFFFFF
-#define I2S_SINGLE_DATA_S  0
-
-#define I2S_STATE_REG(i)          (REG_I2S_BASE(i) + 0x6C)
-/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: 1: i2s_tx is idle state. 0: i2s_tx is working..*/
-#define I2S_TX_IDLE    (BIT(0))
-#define I2S_TX_IDLE_M  (BIT(0))
-#define I2S_TX_IDLE_V  0x1
-#define I2S_TX_IDLE_S  0
-
-#define I2S_DATE_REG(i)          (REG_I2S_BASE(i) + 0x80)
-/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2009070 ; */
-/*description: I2S version control register.*/
-#define I2S_DATE    0x0FFFFFFF
-#define I2S_DATE_M  ((I2S_DATE_V)<<(I2S_DATE_S))
-#define I2S_DATE_V  0xFFFFFFF
-#define I2S_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_I2S_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/i2s_struct.h b/components/soc/esp32s3/include/soc/i2s_struct.h
deleted file mode 100644
index 2ad9b84d512..00000000000
--- a/components/soc/esp32s3/include/soc/i2s_struct.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct i2s_dev_s {
-    uint32_t reserved_0;
-    uint32_t reserved_4;
-    uint32_t reserved_8;
-    union {
-        struct {
-            uint32_t rx_done                       :    1;  /*The raw interrupt status bit  for the i2s_rx_done_int interrupt*/
-            uint32_t tx_done                       :    1;  /*The raw interrupt status bit  for the i2s_tx_done_int interrupt*/
-            uint32_t rx_hung                       :    1;  /*The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
-            uint32_t tx_hung                       :    1;  /*The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
-            uint32_t reserved4                     :    28;  /*Reserve*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t rx_done                       :    1;  /*The masked interrupt status bit  for the i2s_rx_done_int interrupt*/
-            uint32_t tx_done                       :    1;  /*The masked interrupt status bit  for the i2s_tx_done_int interrupt*/
-            uint32_t rx_hung                       :    1;  /*The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
-            uint32_t tx_hung                       :    1;  /*The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
-            uint32_t reserved4                     :    28;  /*Reserve*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t rx_done                       :    1;  /*The interrupt enable bit  for the i2s_rx_done_int interrupt*/
-            uint32_t tx_done                       :    1;  /*The interrupt enable bit  for the i2s_tx_done_int interrupt*/
-            uint32_t rx_hung                       :    1;  /*The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
-            uint32_t tx_hung                       :    1;  /*The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
-            uint32_t reserved4                     :    28;  /*Reserve*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t rx_done                       :    1;  /*Set this bit to clear the i2s_rx_done_int interrupt*/
-            uint32_t tx_done                       :    1;  /*Set this bit to clear the i2s_tx_done_int interrupt*/
-            uint32_t rx_hung                       :    1;  /*Set this bit to clear the i2s_rx_hung_int interrupt*/
-            uint32_t tx_hung                       :    1;  /*Set this bit to clear the i2s_tx_hung_int interrupt*/
-            uint32_t reserved4                     :    28;  /*Reserve*/
-        };
-        uint32_t val;
-    } int_clr;
-    uint32_t reserved_1c;
-    union {
-        struct {
-            uint32_t rx_reset                      :    1;  /*Set this bit to reset receiver*/
-            uint32_t rx_fifo_reset                 :    1;  /*Set this bit to reset Rx AFIFO*/
-            uint32_t rx_start                      :    1;  /*Set this bit to start receiving data*/
-            uint32_t rx_slave_mod                  :    1;  /*Set this bit to enable slave receiver mode*/
-            uint32_t reserved4                     :    1;  /* Reserved*/
-            uint32_t rx_mono                       :    1;  /*Set this bit to enable receiver  in mono mode*/
-            uint32_t reserved6                     :    1;  /*Reserve*/
-            uint32_t rx_big_endian                 :    1;  /*I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
-            uint32_t rx_update                     :    1;  /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
-            uint32_t rx_mono_fst_vld               :    1;  /*1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.*/
-            uint32_t rx_pcm_conf                   :    2;  /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
-            uint32_t rx_pcm_bypass                 :    1;  /*Set this bit to bypass Compress/Decompress module for received data.*/
-            uint32_t rx_stop_mode                  :    2;  /*0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
-            uint32_t rx_left_align                 :    1;  /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
-            uint32_t rx_24_fill_en                 :    1;  /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
-            uint32_t rx_ws_idle_pol                :    1;  /*0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel. */
-            uint32_t rx_bit_order                  :    1;  /*I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.*/
-            uint32_t rx_tdm_en                     :    1;  /*1: Enable I2S TDM Rx mode . 0: Disable.*/
-            uint32_t rx_pdm_en                     :    1;  /*1: Enable I2S PDM Rx mode . 0: Disable.*/
-            uint32_t rx_pdm2pcm_en                 :    1;  /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
-            uint32_t rx_pdm_sinc_dsr_16_en         :    1;  /*Configure the down sampling rate of PDM RX filter group1 module. 1: The  down sampling rate is 128. 0: down sampling rate is 64.*/
-            uint32_t reserved23                    :    9;  /*Reserve*/
-        };
-        uint32_t val;
-    } rx_conf;
-    union {
-        struct {
-            uint32_t tx_reset                      :    1;  /*Set this bit to reset transmitter*/
-            uint32_t tx_fifo_reset                 :    1;  /*Set this bit to reset Tx AFIFO*/
-            uint32_t tx_start                      :    1;  /*Set this bit to start transmitting data */
-            uint32_t tx_slave_mod                  :    1;  /*Set this bit to enable slave transmitter mode  */
-            uint32_t reserved4                     :    1;  /* Reserved*/
-            uint32_t tx_mono                       :    1;  /*Set this bit to enable transmitter in mono mode  */
-            uint32_t tx_chan_equal                 :    1;  /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
-            uint32_t tx_big_endian                 :    1;  /*I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.*/
-            uint32_t tx_update                     :    1;  /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
-            uint32_t tx_mono_fst_vld               :    1;  /*1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.*/
-            uint32_t tx_pcm_conf                   :    2;  /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
-            uint32_t tx_pcm_bypass                 :    1;  /*Set this bit to bypass  Compress/Decompress module for transmitted data.*/
-            uint32_t tx_stop_en                    :    1;  /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
-            uint32_t reserved14                    :    1;  /* Reserved*/
-            uint32_t tx_left_align                 :    1;  /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
-            uint32_t tx_24_fill_en                 :    1;  /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
-            uint32_t tx_ws_idle_pol                :    1;  /*0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel. */
-            uint32_t tx_bit_order                  :    1;  /*I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.*/
-            uint32_t tx_tdm_en                     :    1;  /*1: Enable I2S TDM Tx mode . 0: Disable.*/
-            uint32_t tx_pdm_en                     :    1;  /*1: Enable I2S PDM Tx mode . 0: Disable.*/
-            uint32_t reserved21                    :    3;  /*Reserved*/
-            uint32_t tx_chan_mod                   :    3;  /*I2S transmitter channel mode configuration bits.*/
-            uint32_t sig_loopback                  :    1;  /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
-            uint32_t reserved28                    :    4;  /*Reserve*/
-        };
-        uint32_t val;
-    } tx_conf;
-    union {
-        struct {
-            uint32_t rx_tdm_ws_width               :    7;  /* The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
-            uint32_t rx_bck_div_num                :    6;  /*Bit clock configuration bits in receiver mode. */
-            uint32_t rx_bits_mod                   :    5;  /*Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
-            uint32_t rx_half_sample_bits           :    6;  /*I2S Rx half sample bits -1.*/
-            uint32_t rx_tdm_chan_bits              :    5;  /*The Rx bit number for each channel minus 1in TDM mode.*/
-            uint32_t rx_msb_shift                  :    1;  /*Set this bit to enable receiver in Phillips standard mode*/
-            uint32_t reserved30                    :    2;  /* Reserved*/
-        };
-        uint32_t val;
-    } rx_conf1;
-    union {
-        struct {
-            uint32_t tx_tdm_ws_width               :    7;  /* The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
-            uint32_t tx_bck_div_num                :    6;  /*Bit clock configuration bits in transmitter mode. */
-            uint32_t tx_bits_mod                   :    5;  /*Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
-            uint32_t tx_half_sample_bits           :    6;  /* I2S Tx half sample bits -1.*/
-            uint32_t tx_tdm_chan_bits              :    5;  /*The Tx bit number for each channel minus 1in TDM mode.*/
-            uint32_t tx_msb_shift                  :    1;  /*Set this bit to enable transmitter in Phillips standard mode*/
-            uint32_t tx_bck_no_dly                 :    1;  /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
-            uint32_t reserved31                    :    1;  /* Reserved*/
-        };
-        uint32_t val;
-    } tx_conf1;
-    union {
-        struct {
-            uint32_t rx_clkm_div_num               :    8;  /*Integral I2S clock divider value*/
-            uint32_t reserved8                     :    18;  /* Reserved*/
-            uint32_t rx_clk_active                 :    1;  /*I2S Rx module clock enable signal.*/
-            uint32_t rx_clk_sel                    :    2;  /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
-            uint32_t mclk_sel                      :    1;  /* 0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT. */
-            uint32_t reserved30                    :    2;  /* Reserved*/
-        };
-        uint32_t val;
-    } rx_clkm_conf;
-    union {
-        struct {
-            uint32_t tx_clkm_div_num               :    8;  /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. */
-            uint32_t reserved8                     :    18;  /* Reserved*/
-            uint32_t tx_clk_active                 :    1;  /*I2S Tx module clock enable signal.*/
-            uint32_t tx_clk_sel                    :    2;  /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
-            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
-            uint32_t reserved30                    :    2;  /* Reserved*/
-        };
-        uint32_t val;
-    } tx_clkm_conf;
-    union {
-        struct {
-            uint32_t rx_clkm_div_z                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). */
-            uint32_t rx_clkm_div_y                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). */
-            uint32_t rx_clkm_div_x                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. */
-            uint32_t rx_clkm_div_yn1               :    1;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. */
-            uint32_t reserved28                    :    4;  /* Reserved*/
-        };
-        uint32_t val;
-    } rx_clkm_div_conf;
-    union {
-        struct {
-            uint32_t tx_clkm_div_z                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). */
-            uint32_t tx_clkm_div_y                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). */
-            uint32_t tx_clkm_div_x                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. */
-            uint32_t tx_clkm_div_yn1               :    1;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. */
-            uint32_t reserved28                    :    4;  /* Reserved*/
-        };
-        uint32_t val;
-    } tx_clkm_div_conf;
-    union {
-        struct {
-            uint32_t tx_hp_bypass                  :    1;  /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
-            uint32_t tx_sinc_osr2                  :    4;  /*I2S TX PDM OSR2 value*/
-            uint32_t tx_prescale                   :    8;  /*I2S TX PDM prescale for sigmadelta*/
-            uint32_t tx_hp_in_shift                :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
-            uint32_t tx_lp_in_shift                :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
-            uint32_t tx_sinc_in_shift              :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
-            uint32_t tx_sigmadelta_in_shift        :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
-            uint32_t tx_sigmadelta_dither2         :    1;  /*I2S TX PDM sigmadelta dither2 value*/
-            uint32_t tx_sigmadelta_dither          :    1;  /*I2S TX PDM sigmadelta dither value*/
-            uint32_t tx_dac_2out_en                :    1;  /*I2S TX PDM dac mode enable*/
-            uint32_t tx_dac_mode_en                :    1;  /*I2S TX PDM dac 2channel enable*/
-            uint32_t pcm2pdm_conv_en               :    1;  /*I2S TX PDM Converter enable*/
-            uint32_t reserved26                    :    6;  /*Reserved*/
-        };
-        uint32_t val;
-    } tx_pcm2pdm_conf; // Only available on I2S0
-    union {
-        struct {
-            uint32_t tx_pdm_fp                     :    10;  /*I2S TX PDM Fp*/
-            uint32_t tx_pdm_fs                     :    10;  /*I2S TX PDM Fs*/
-            uint32_t tx_iir_hp_mult12_5            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
-            uint32_t tx_iir_hp_mult12_0            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
-            uint32_t reserved26                    :    6;  /*Reserved*/
-        };
-        uint32_t val;
-    } tx_pcm2pdm_conf1; // Only available on I2S0
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    union {
-        struct {
-            uint32_t rx_tdm_chan0_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan1_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan2_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan3_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan4_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan5_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan6_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan7_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan8_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan9_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan10_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan11_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan12_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan13_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan14_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_chan15_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
-            uint32_t rx_tdm_tot_chan_num           :    4;  /*The total channel number of I2S TX TDM mode.*/
-            uint32_t reserved20                    :    12;  /* Reserved*/
-        };
-        uint32_t val;
-    } rx_tdm_ctrl;
-    union {
-        struct {
-            uint32_t tx_tdm_chan0_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan1_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan2_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan3_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan4_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan5_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan6_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan7_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan8_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan9_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan10_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan11_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan12_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan13_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan14_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_chan15_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
-            uint32_t tx_tdm_tot_chan_num           :    4;  /*The total channel number of I2S TX TDM mode.*/
-            uint32_t tx_tdm_skip_msk_en            :    1;  /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
-            uint32_t reserved21                    :    11;  /* Reserved*/
-        };
-        uint32_t val;
-    } tx_tdm_ctrl;
-    union {
-        struct {
-            uint32_t rx_sd_in_dm                   :    2;  /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved2                     :    2;
-            uint32_t rx_sd1_in_dm                  :    2;  /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved6                     :    2;
-            uint32_t rx_sd2_in_dm                  :    2;  /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved10                    :    2;
-            uint32_t rx_sd3_in_dm                  :    2;  /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved14                    :    2;
-            uint32_t rx_ws_out_dm                  :    2;  /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved18                    :    2;  /* Reserved*/
-            uint32_t rx_bck_out_dm                 :    2;  /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved22                    :    2;  /* Reserved*/
-            uint32_t rx_ws_in_dm                   :    2;  /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved26                    :    2;  /* Reserved*/
-            uint32_t rx_bck_in_dm                  :    2;  /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved30                    :    2;  /* Reserved*/
-        };
-        uint32_t val;
-    } rx_timing;
-    union {
-        struct {
-            uint32_t tx_sd_out_dm                  :    2;  /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved2                     :    2;  /* Reserved*/
-            uint32_t tx_sd1_out_dm                 :    2;  /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved6                     :    10;  /* Reserved*/
-            uint32_t tx_ws_out_dm                  :    2;  /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved18                    :    2;  /* Reserved*/
-            uint32_t tx_bck_out_dm                 :    2;  /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved22                    :    2;  /* Reserved*/
-            uint32_t tx_ws_in_dm                   :    2;  /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved26                    :    2;  /* Reserved*/
-            uint32_t tx_bck_in_dm                  :    2;  /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
-            uint32_t reserved30                    :    2;  /* Reserved*/
-        };
-        uint32_t val;
-    } tx_timing;
-    union {
-        struct {
-            uint32_t fifo_timeout                  :    8;  /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value  */
-            uint32_t fifo_timeout_shift            :    3;  /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
-            uint32_t fifo_timeout_ena              :    1;  /*The enable bit for FIFO timeout*/
-            uint32_t reserved12                    :    20;  /* Reserved*/
-        };
-        uint32_t val;
-    } lc_hung_conf;
-    union {
-        struct {
-            uint32_t rx_eof_num                    :    12;  /*The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/
-            uint32_t reserved12                    :    20;  /* Reserved*/
-        };
-        uint32_t val;
-    } rx_eof_num;
-    uint32_t conf_single_data;                               /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
-    union {
-        struct {
-            uint32_t tx_idle                       :    1;  /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
-            uint32_t reserved1                     :    31;  /* Reserved*/
-        };
-        uint32_t val;
-    } state;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*I2S version control register*/
-            uint32_t reserved28                    :    4;  /* Reserved*/
-        };
-        uint32_t val;
-    } date;
-} i2s_dev_t;
-extern i2s_dev_t I2S0;
-extern i2s_dev_t I2S1;
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/interrupt_core0_reg.h b/components/soc/esp32s3/include/soc/interrupt_core0_reg.h
deleted file mode 100644
index f686720be44..00000000000
--- a/components/soc/esp32s3/include/soc/interrupt_core0_reg.h
+++ /dev/null
@@ -1,871 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_INTERRUPT_CORE0_REG_H_
-#define _SOC_INTERRUPT_CORE0_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DR_REG_INTERRUPT_CORE0_BASE                 DR_REG_INTERRUPT_BASE
-
-#define INTERRUPT_CORE0_MAC_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
-/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_MAC_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_MAC_INTR_MAP_M  ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
-#define INTERRUPT_CORE0_MAC_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_MAC_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_MAC_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
-/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_MAC_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_MAC_NMI_MAP_M  ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
-#define INTERRUPT_CORE0_MAC_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_MAC_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_PWR_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
-/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_PWR_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_PWR_INTR_MAP_M  ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
-#define INTERRUPT_CORE0_PWR_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_PWR_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
-/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_BB_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_BB_INT_MAP_M  ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
-#define INTERRUPT_CORE0_BB_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_BB_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
-/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M  ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
-/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_BT_BB_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_M  ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
-/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
-/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP  0x0000001F
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V  0x1F
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S  0
-
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
-/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP  0x0000001F
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V  0x1F
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S  0
-
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x024)
-/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_RWBT_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_M  ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x028)
-/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M  ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x02C)
-/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x030)
-/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SLC0_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_M  ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x034)
-/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SLC1_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_M  ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x038)
-/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_UHCI1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x03C)
-/* INTERRUPT_CORE0_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_UHCI1_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_UHCI1_INTR_MAP_M  ((INTERRUPT_CORE0_UHCI1_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI1_INTR_MAP_S))
-#define INTERRUPT_CORE0_UHCI1_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_UHCI1_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x040)
-/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP  0x0000001F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x1F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
-
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x044)
-/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x048)
-/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP  0x0000001F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V  0x1F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S  0
-
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x04C)
-/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V  0x1F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
-/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
-/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI_INTR_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x058)
-/* INTERRUPT_CORE0_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI_INTR_3_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI_INTR_3_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_3_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_3_MAP_S))
-#define INTERRUPT_CORE0_SPI_INTR_3_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI_INTR_3_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI_INTR_4_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x05C)
-/* INTERRUPT_CORE0_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI_INTR_4_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI_INTR_4_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_4_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_4_MAP_S))
-#define INTERRUPT_CORE0_SPI_INTR_4_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI_INTR_4_MAP_S  0
-
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x060)
-/* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M  ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE0_LCD_CAM_INT_MAP_S))
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_I2S0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
-/* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_I2S0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_I2S0_INT_MAP_M  ((INTERRUPT_CORE0_I2S0_INT_MAP_V)<<(INTERRUPT_CORE0_I2S0_INT_MAP_S))
-#define INTERRUPT_CORE0_I2S0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_I2S0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
-/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_I2S1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_I2S1_INT_MAP_M  ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
-#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_I2S1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x06C)
-/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_UART_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_UART_INTR_MAP_M  ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
-#define INTERRUPT_CORE0_UART_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_UART_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_UART1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x070)
-/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_UART1_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_UART1_INTR_MAP_M  ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
-#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_UART2_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x074)
-/* INTERRUPT_CORE0_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_UART2_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_UART2_INTR_MAP_M  ((INTERRUPT_CORE0_UART2_INTR_MAP_V)<<(INTERRUPT_CORE0_UART2_INTR_MAP_S))
-#define INTERRUPT_CORE0_UART2_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_UART2_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x078)
-/* INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_M  ((INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V)<<(INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S))
-#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S  0
-
-#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x07C)
-/* INTERRUPT_CORE0_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_PWM0_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_PWM0_INTR_MAP_M  ((INTERRUPT_CORE0_PWM0_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM0_INTR_MAP_S))
-#define INTERRUPT_CORE0_PWM0_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_PWM0_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x080)
-/* INTERRUPT_CORE0_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_PWM1_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_PWM1_INTR_MAP_M  ((INTERRUPT_CORE0_PWM1_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM1_INTR_MAP_S))
-#define INTERRUPT_CORE0_PWM1_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_PWM1_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x084)
-/* INTERRUPT_CORE0_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_PWM2_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_PWM2_INTR_MAP_M  ((INTERRUPT_CORE0_PWM2_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM2_INTR_MAP_S))
-#define INTERRUPT_CORE0_PWM2_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_PWM2_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x088)
-/* INTERRUPT_CORE0_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_PWM3_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_PWM3_INTR_MAP_M  ((INTERRUPT_CORE0_PWM3_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM3_INTR_MAP_S))
-#define INTERRUPT_CORE0_PWM3_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_PWM3_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x08C)
-/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_LEDC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
-#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x090)
-/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_EFUSE_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_CAN_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
-/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CAN_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_CAN_INT_MAP_M  ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
-#define INTERRUPT_CORE0_CAN_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CAN_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_USB_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
-/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_USB_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_USB_INTR_MAP_M  ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
-#define INTERRUPT_CORE0_USB_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_USB_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x09C)
-/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M  ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_RMT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0)
-/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_RMT_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_RMT_INTR_MAP_M  ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
-#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4)
-/* INTERRUPT_CORE0_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_PCNT_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_M  ((INTERRUPT_CORE0_PCNT_INTR_MAP_V)<<(INTERRUPT_CORE0_PCNT_INTR_MAP_S))
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_PCNT_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8)
-/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC)
-/* INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S))
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0)
-/* INTERRUPT_CORE0_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_M  ((INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S))
-#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4)
-/* INTERRUPT_CORE0_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_M  ((INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S))
-#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8)
-/* INTERRUPT_CORE0_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_M  ((INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S))
-#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_WDG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC)
-/* INTERRUPT_CORE0_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_WDG_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_WDG_INT_MAP_M  ((INTERRUPT_CORE0_WDG_INT_MAP_V)<<(INTERRUPT_CORE0_WDG_INT_MAP_S))
-#define INTERRUPT_CORE0_WDG_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_WDG_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0)
-/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_TIMER_INT1_MAP  0x0000001F
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_M  ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_V  0x1F
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_S  0
-
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4)
-/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_TIMER_INT2_MAP  0x0000001F
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_M  ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_V  0x1F
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_S  0
-
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8)
-/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG_T0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TG_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC)
-/* INTERRUPT_CORE0_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG_T1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG_T1_INT_MAP_M  ((INTERRUPT_CORE0_TG_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T1_INT_MAP_S))
-#define INTERRUPT_CORE0_TG_T1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG_T1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0)
-/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4)
-/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TG1_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8)
-/* INTERRUPT_CORE0_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG1_T1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG1_T1_INT_MAP_M  ((INTERRUPT_CORE0_TG1_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T1_INT_MAP_S))
-#define INTERRUPT_CORE0_TG1_T1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG1_T1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC)
-/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0)
-/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0)
-/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M  ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4)
-/* INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S))
-#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
-/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
-/* INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S))
-#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
-/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
-/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M  ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
-/* INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
-/* INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
-/* INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
-/* INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
-/* INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
-/* INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
-/* INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
-/* INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
-/* INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
-/* INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
-/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_RSA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_RSA_INT_MAP_M  ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
-#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_RSA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
-/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_AES_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_AES_INT_MAP_M  ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
-#define INTERRUPT_CORE0_AES_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_AES_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
-/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_SHA_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
-#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_SHA_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
-
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
-
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
-/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
-/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
-/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
-/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
-/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
-/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
-/* INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
-/* INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
-/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
-/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
-/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V  0x1F
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S  0
-
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
-/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
-/* INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S))
-#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
-/* INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M  ((INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S))
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
-/* INTERRUPT_CORE0_PERI_BACKUP_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_M  ((INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V)<<(INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S))
-#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
-/* INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
-/*description: */
-#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_M  ((INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_INTR_STATUS_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
-/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define INTERRUPT_CORE0_INTR_STATUS_0  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
-#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_0_S  0
-
-#define INTERRUPT_CORE0_INTR_STATUS_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
-/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define INTERRUPT_CORE0_INTR_STATUS_1  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
-#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_1_S  0
-
-#define INTERRUPT_CORE0_INTR_STATUS_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
-/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define INTERRUPT_CORE0_INTR_STATUS_2  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_2_M  ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S))
-#define INTERRUPT_CORE0_INTR_STATUS_2_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_2_S  0
-
-#define INTERRUPT_CORE0_INTR_STATUS_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
-/* INTERRUPT_CORE0_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define INTERRUPT_CORE0_INTR_STATUS_3  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_3_M  ((INTERRUPT_CORE0_INTR_STATUS_3_V)<<(INTERRUPT_CORE0_INTR_STATUS_3_S))
-#define INTERRUPT_CORE0_INTR_STATUS_3_V  0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_3_S  0
-
-#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
-/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: */
-#define INTERRUPT_CORE0_CLK_EN  (BIT(0))
-#define INTERRUPT_CORE0_CLK_EN_M  (BIT(0))
-#define INTERRUPT_CORE0_CLK_EN_V  0x1
-#define INTERRUPT_CORE0_CLK_EN_S  0
-
-#define INTERRUPT_CORE0_INTERRUPT_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
-/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
-/*description: */
-#define INTERRUPT_CORE0_INTERRUPT_DATE  0x0FFFFFFF
-#define INTERRUPT_CORE0_INTERRUPT_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
-#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0xFFFFFFF
-#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/io_mux_reg.h b/components/soc/esp32s3/include/soc/io_mux_reg.h
deleted file mode 100644
index 3ca2cd04989..00000000000
--- a/components/soc/esp32s3/include/soc/io_mux_reg.h
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include "soc.h"
-
-/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
-/* Output enable in sleep mode */
-#define SLP_OE (BIT(0))
-#define SLP_OE_M (BIT(0))
-#define SLP_OE_V 1
-#define SLP_OE_S 0
-/* Pin used for wakeup from sleep */
-#define SLP_SEL (BIT(1))
-#define SLP_SEL_M (BIT(1))
-#define SLP_SEL_V 1
-#define SLP_SEL_S 1
-/* Pulldown enable in sleep mode */
-#define SLP_PD (BIT(2))
-#define SLP_PD_M (BIT(2))
-#define SLP_PD_V 1
-#define SLP_PD_S 2
-/* Pullup enable in sleep mode */
-#define SLP_PU (BIT(3))
-#define SLP_PU_M (BIT(3))
-#define SLP_PU_V 1
-#define SLP_PU_S 3
-/* Input enable in sleep mode */
-#define SLP_IE (BIT(4))
-#define SLP_IE_M (BIT(4))
-#define SLP_IE_V 1
-#define SLP_IE_S 4
-/* Drive strength in sleep mode */
-#define SLP_DRV 0x3
-#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
-#define SLP_DRV_V 0x3
-#define SLP_DRV_S 5
-/* Pulldown enable */
-#define FUN_PD (BIT(7))
-#define FUN_PD_M (BIT(7))
-#define FUN_PD_V 1
-#define FUN_PD_S 7
-/* Pullup enable */
-#define FUN_PU (BIT(8))
-#define FUN_PU_M (BIT(8))
-#define FUN_PU_V 1
-#define FUN_PU_S 8
-/* Input enable */
-#define FUN_IE (BIT(9))
-#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
-#define FUN_IE_V 1
-#define FUN_IE_S 9
-/* Drive strength */
-#define FUN_DRV 0x3
-#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
-#define FUN_DRV_V 0x3
-#define FUN_DRV_S 10
-/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
-#define MCU_SEL 0x7
-#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
-#define MCU_SEL_V 0x7
-#define MCU_SEL_S 12
-/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
-#define FILTER_EN (BIT(15))
-#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
-#define FILTER_EN_V 1
-#define FILTER_EN_S 15
-
-#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
-#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
-#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
-#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
-#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
-
-#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
-#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
-#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
-
-#define IO_MUX_GPIO0_REG        PERIPHS_IO_MUX_GPIO0_U
-#define IO_MUX_GPIO1_REG        PERIPHS_IO_MUX_GPIO1_U
-#define IO_MUX_GPIO2_REG        PERIPHS_IO_MUX_GPIO2_U
-#define IO_MUX_GPIO3_REG        PERIPHS_IO_MUX_GPIO3_U
-#define IO_MUX_GPIO4_REG        PERIPHS_IO_MUX_GPIO4_U
-#define IO_MUX_GPIO5_REG        PERIPHS_IO_MUX_GPIO5_U
-#define IO_MUX_GPIO6_REG        PERIPHS_IO_MUX_GPIO6_U
-#define IO_MUX_GPIO7_REG        PERIPHS_IO_MUX_GPIO7_U
-#define IO_MUX_GPIO8_REG        PERIPHS_IO_MUX_GPIO8_U
-#define IO_MUX_GPIO9_REG        PERIPHS_IO_MUX_GPIO9_U
-#define IO_MUX_GPIO10_REG       PERIPHS_IO_MUX_GPIO10_U
-#define IO_MUX_GPIO11_REG       PERIPHS_IO_MUX_GPIO11_U
-#define IO_MUX_GPIO12_REG       PERIPHS_IO_MUX_GPIO12_U
-#define IO_MUX_GPIO13_REG       PERIPHS_IO_MUX_GPIO13_U
-#define IO_MUX_GPIO14_REG       PERIPHS_IO_MUX_GPIO14_U
-#define IO_MUX_GPIO15_REG       PERIPHS_IO_MUX_XTAL_32K_P_U
-#define IO_MUX_GPIO16_REG       PERIPHS_IO_MUX_XTAL_32K_N_U
-#define IO_MUX_GPIO17_REG       PERIPHS_IO_MUX_DAC_1_U
-#define IO_MUX_GPIO18_REG       PERIPHS_IO_MUX_DAC_2_U
-#define IO_MUX_GPIO19_REG       PERIPHS_IO_MUX_GPIO19_U
-#define IO_MUX_GPIO20_REG       PERIPHS_IO_MUX_GPIO20_U
-#define IO_MUX_GPIO21_REG       PERIPHS_IO_MUX_GPIO21_U
-#define IO_MUX_GPIO26_REG       PERIPHS_IO_MUX_SPICS1_U
-#define IO_MUX_GPIO27_REG       PERIPHS_IO_MUX_SPIHD_U
-#define IO_MUX_GPIO28_REG       PERIPHS_IO_MUX_SPIWP_U
-#define IO_MUX_GPIO29_REG       PERIPHS_IO_MUX_SPICS0_U
-#define IO_MUX_GPIO30_REG       PERIPHS_IO_MUX_SPICLK_U
-#define IO_MUX_GPIO31_REG       PERIPHS_IO_MUX_SPIQ_U
-#define IO_MUX_GPIO32_REG       PERIPHS_IO_MUX_SPID_U
-#define IO_MUX_GPIO33_REG       PERIPHS_IO_MUX_GPIO33_U
-#define IO_MUX_GPIO34_REG       PERIPHS_IO_MUX_GPIO34_U
-#define IO_MUX_GPIO35_REG       PERIPHS_IO_MUX_GPIO35_U
-#define IO_MUX_GPIO36_REG       PERIPHS_IO_MUX_GPIO36_U
-#define IO_MUX_GPIO37_REG       PERIPHS_IO_MUX_GPIO37_U
-#define IO_MUX_GPIO38_REG       PERIPHS_IO_MUX_GPIO38_U
-#define IO_MUX_GPIO39_REG       PERIPHS_IO_MUX_MTCK_U
-#define IO_MUX_GPIO40_REG       PERIPHS_IO_MUX_MTDO_U
-#define IO_MUX_GPIO41_REG       PERIPHS_IO_MUX_MTDI_U
-#define IO_MUX_GPIO42_REG       PERIPHS_IO_MUX_MTMS_U
-#define IO_MUX_GPIO43_REG       PERIPHS_IO_MUX_U0TXD_U
-#define IO_MUX_GPIO44_REG       PERIPHS_IO_MUX_U0RXD_U
-#define IO_MUX_GPIO45_REG       PERIPHS_IO_MUX_GPIO45_U
-#define IO_MUX_GPIO46_REG       PERIPHS_IO_MUX_GPIO46_U
-#define IO_MUX_GPIO47_REG       PERIPHS_IO_MUX_SPICLK_P_U
-#define IO_MUX_GPIO48_REG       PERIPHS_IO_MUX_SPICLK_N_U
-
-#define PIN_FUNC_GPIO                               1
-
-#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
-#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
-
-#define SPI_CS1_GPIO_NUM 26
-#define SPI_HD_GPIO_NUM  27
-#define SPI_WP_GPIO_NUM  28
-#define SPI_CS0_GPIO_NUM 29
-#define SPI_CLK_GPIO_NUM 30
-#define SPI_Q_GPIO_NUM   31
-#define SPI_D_GPIO_NUM   32
-#define SPI_D4_GPIO_NUM  33
-#define SPI_D5_GPIO_NUM  34
-#define SPI_D6_GPIO_NUM  35
-#define SPI_D7_GPIO_NUM  36
-#define SPI_DQS_GPIO_NUM 37
-#define SD_CLK_GPIO_NUM 12
-#define SD_CMD_GPIO_NUM 11
-#define SD_DATA0_GPIO_NUM 13
-#define SD_DATA1_GPIO_NUM 14
-#define SD_DATA2_GPIO_NUM 9
-#define SD_DATA3_GPIO_NUM 10
-#define USB_INT_PHY0_DM_GPIO_NUM   19
-#define USB_INT_PHY0_DP_GPIO_NUM   20
-#define XTAL32K_P_GPIO_NUM 15
-#define XTAL32K_N_GPIO_NUM 16
-
-#define MAX_RTC_GPIO_NUM 21
-#define MAX_PAD_GPIO_NUM 48
-#define MAX_GPIO_NUM    53
-
-#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
-#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
-#define PAD_POWER_SEL                               BIT(15)
-#define PAD_POWER_SEL_V                             0x1
-#define PAD_POWER_SEL_M                             BIT(15)
-#define PAD_POWER_SEL_S                             15
-
-
-#define PAD_POWER_SWITCH_DELAY                      0x7
-#define PAD_POWER_SWITCH_DELAY_V                    0x7
-#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
-#define PAD_POWER_SWITCH_DELAY_S                    12
-
-
-#define CLK_OUT3                                    0xf
-#define CLK_OUT3_V                                  CLK_OUT3
-#define CLK_OUT3_S                                  8
-#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
-#define CLK_OUT2                                    0xf
-#define CLK_OUT2_V                                  CLK_OUT2
-#define CLK_OUT2_S                                  4
-#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
-#define CLK_OUT1                                    0xf
-#define CLK_OUT1_V                                  CLK_OUT1
-#define CLK_OUT1_S                                  0
-#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
-
-#define PERIPHS_IO_MUX_GPIO0_U            (REG_IO_MUX_BASE +0x04)
-#define FUNC_GPIO0_GPIO0                            1
-#define FUNC_GPIO0_GPIO0_0                          0
-
-#define PERIPHS_IO_MUX_GPIO1_U            (REG_IO_MUX_BASE +0x08)
-#define FUNC_GPIO1_GPIO1                            1
-#define FUNC_GPIO1_GPIO1_0                          0
-
-#define PERIPHS_IO_MUX_GPIO2_U            (REG_IO_MUX_BASE +0x0c)
-#define FUNC_GPIO2_GPIO2                            1
-#define FUNC_GPIO2_GPIO2_0                          0
-
-#define PERIPHS_IO_MUX_GPIO3_U            (REG_IO_MUX_BASE +0x10)
-#define FUNC_GPIO3_GPIO3                            1
-#define FUNC_GPIO3_GPIO3_0                          0
-
-#define PERIPHS_IO_MUX_GPIO4_U            (REG_IO_MUX_BASE +0x14)
-#define FUNC_GPIO4_GPIO4                            1
-#define FUNC_GPIO4_GPIO4_0                          0
-
-#define PERIPHS_IO_MUX_GPIO5_U            (REG_IO_MUX_BASE +0x18)
-#define FUNC_GPIO5_GPIO5                            1
-#define FUNC_GPIO5_GPIO5_0                          0
-
-#define PERIPHS_IO_MUX_GPIO6_U            (REG_IO_MUX_BASE +0x1c)
-#define FUNC_GPIO6_GPIO6                            1
-#define FUNC_GPIO6_GPIO6_0                          0
-
-#define PERIPHS_IO_MUX_GPIO7_U            (REG_IO_MUX_BASE +0x20)
-#define FUNC_GPIO7_GPIO7                            1
-#define FUNC_GPIO7_GPIO7_0                          0
-
-#define PERIPHS_IO_MUX_GPIO8_U            (REG_IO_MUX_BASE +0x24)
-#define FUNC_GPIO8_SUBSPICS1                        3
-#define FUNC_GPIO8_GPIO8                            1
-#define FUNC_GPIO8_GPIO8_0                          0
-
-#define PERIPHS_IO_MUX_GPIO9_U            (REG_IO_MUX_BASE +0x28)
-#define FUNC_GPIO9_FSPIHD                           4
-#define FUNC_GPIO9_SUBSPIHD                         3
-#define FUNC_GPIO9_GPIO9                            1
-#define FUNC_GPIO9_GPIO9_0                          0
-
-#define PERIPHS_IO_MUX_GPIO10_U           (REG_IO_MUX_BASE +0x2c)
-#define FUNC_GPIO10_FSPICS0                         4
-#define FUNC_GPIO10_SUBSPICS0                       3
-#define FUNC_GPIO10_FSPIIO4                         2
-#define FUNC_GPIO10_GPIO10                          1
-#define FUNC_GPIO10_GPIO10_0                        0
-
-#define PERIPHS_IO_MUX_GPIO11_U           (REG_IO_MUX_BASE +0x30)
-#define FUNC_GPIO11_FSPID                           4
-#define FUNC_GPIO11_SUBSPID                         3
-#define FUNC_GPIO11_FSPIIO5                         2
-#define FUNC_GPIO11_GPIO11                          1
-#define FUNC_GPIO11_GPIO11_0                        0
-
-#define PERIPHS_IO_MUX_GPIO12_U           (REG_IO_MUX_BASE +0x34)
-#define FUNC_GPIO12_FSPICLK                         4
-#define FUNC_GPIO12_SUBSPICLK                       3
-#define FUNC_GPIO12_FSPIIO6                         2
-#define FUNC_GPIO12_GPIO12                          1
-#define FUNC_GPIO12_GPIO12_0                        0
-
-#define PERIPHS_IO_MUX_GPIO13_U           (REG_IO_MUX_BASE +0x38)
-#define FUNC_GPIO13_FSPIQ                           4
-#define FUNC_GPIO13_SUBSPIQ                         3
-#define FUNC_GPIO13_FSPIIO7                         2
-#define FUNC_GPIO13_GPIO13                          1
-#define FUNC_GPIO13_GPIO13_0                        0
-
-#define PERIPHS_IO_MUX_GPIO14_U           (REG_IO_MUX_BASE +0x3c)
-#define FUNC_GPIO14_FSPIWP                          4
-#define FUNC_GPIO14_SUBSPIWP                        3
-#define FUNC_GPIO14_FSPIDQS                         2
-#define FUNC_GPIO14_GPIO14                          1
-#define FUNC_GPIO14_GPIO14_0                        0
-
-#define PERIPHS_IO_MUX_XTAL_32K_P_U       (REG_IO_MUX_BASE +0x40)
-#define FUNC_XTAL_32K_P_U0RTS                       2
-#define FUNC_XTAL_32K_P_GPIO15                      1
-#define FUNC_XTAL_32K_P_GPIO15_0                    0
-
-#define PERIPHS_IO_MUX_XTAL_32K_N_U       (REG_IO_MUX_BASE +0x44)
-#define FUNC_XTAL_32K_N_U0CTS                       2
-#define FUNC_XTAL_32K_N_GPIO16                      1
-#define FUNC_XTAL_32K_N_GPIO16_0                    0
-
-#define PERIPHS_IO_MUX_DAC_1_U            (REG_IO_MUX_BASE +0x48)
-#define FUNC_DAC_1_U1TXD                            2
-#define FUNC_DAC_1_GPIO17                           1
-#define FUNC_DAC_1_GPIO17_0                         0
-
-#define PERIPHS_IO_MUX_DAC_2_U            (REG_IO_MUX_BASE +0x4c)
-#define FUNC_DAC_2_CLK_OUT3                         3
-#define FUNC_DAC_2_U1RXD                            2
-#define FUNC_DAC_2_GPIO18                           1
-#define FUNC_DAC_2_GPIO18_0                         0
-
-#define PERIPHS_IO_MUX_GPIO19_U           (REG_IO_MUX_BASE +0x50)
-#define FUNC_GPIO19_CLK_OUT2                        3
-#define FUNC_GPIO19_U1RTS                           2
-#define FUNC_GPIO19_GPIO19                          1
-#define FUNC_GPIO19_GPIO19_0                        0
-
-#define PERIPHS_IO_MUX_GPIO20_U           (REG_IO_MUX_BASE +0x54)
-#define FUNC_GPIO20_CLK_OUT1                        3
-#define FUNC_GPIO20_U1CTS                           2
-#define FUNC_GPIO20_GPIO20                          1
-#define FUNC_GPIO20_GPIO20_0                        0
-
-#define PERIPHS_IO_MUX_GPIO21_U           (REG_IO_MUX_BASE +0x58)
-#define FUNC_GPIO21_GPIO21                          1
-#define FUNC_GPIO21_GPIO21_0                        0
-
-#define PERIPHS_IO_MUX_SPICS1_U           (REG_IO_MUX_BASE +0x6c)
-#define FUNC_SPICS1_GPIO26                          1
-#define FUNC_SPICS1_SPICS1                          0
-
-#define PERIPHS_IO_MUX_SPIHD_U            (REG_IO_MUX_BASE +0x70)
-#define FUNC_SPIHD_GPIO27                           1
-#define FUNC_SPIHD_SPIHD                            0
-
-#define PERIPHS_IO_MUX_SPIWP_U            (REG_IO_MUX_BASE +0x74)
-#define FUNC_SPIWP_GPIO28                           1
-#define FUNC_SPIWP_SPIWP                            0
-
-#define PERIPHS_IO_MUX_SPICS0_U           (REG_IO_MUX_BASE +0x78)
-#define FUNC_SPICS0_GPIO29                          1
-#define FUNC_SPICS0_SPICS0                          0
-
-#define PERIPHS_IO_MUX_SPICLK_U           (REG_IO_MUX_BASE +0x7c)
-#define FUNC_SPICLK_GPIO30                          1
-#define FUNC_SPICLK_SPICLK                          0
-
-#define PERIPHS_IO_MUX_SPIQ_U             (REG_IO_MUX_BASE +0x80)
-#define FUNC_SPIQ_GPIO31                            1
-#define FUNC_SPIQ_SPIQ                              0
-
-#define PERIPHS_IO_MUX_SPID_U             (REG_IO_MUX_BASE +0x84)
-#define FUNC_SPID_GPIO32                            1
-#define FUNC_SPID_SPID                              0
-
-#define PERIPHS_IO_MUX_GPIO33_U           (REG_IO_MUX_BASE +0x88)
-#define FUNC_GPIO33_SPIIO4                          4
-#define FUNC_GPIO33_SUBSPIHD                        3
-#define FUNC_GPIO33_FSPIHD                          2
-#define FUNC_GPIO33_GPIO33                          1
-#define FUNC_GPIO33_GPIO33_0                        0
-
-#define PERIPHS_IO_MUX_GPIO34_U           (REG_IO_MUX_BASE +0x8c)
-#define FUNC_GPIO34_SPIIO5                          4
-#define FUNC_GPIO34_SUBSPICS0                       3
-#define FUNC_GPIO34_FSPICS0                         2
-#define FUNC_GPIO34_GPIO34                          1
-#define FUNC_GPIO34_GPIO34_0                        0
-
-#define PERIPHS_IO_MUX_GPIO35_U           (REG_IO_MUX_BASE +0x90)
-#define FUNC_GPIO35_SPIIO6                          4
-#define FUNC_GPIO35_SUBSPID                         3
-#define FUNC_GPIO35_FSPID                           2
-#define FUNC_GPIO35_GPIO35                          1
-#define FUNC_GPIO35_GPIO35_0                        0
-
-#define PERIPHS_IO_MUX_GPIO36_U           (REG_IO_MUX_BASE +0x94)
-#define FUNC_GPIO36_SPIIO7                          4
-#define FUNC_GPIO36_SUBSPICLK                       3
-#define FUNC_GPIO36_FSPICLK                         2
-#define FUNC_GPIO36_GPIO36                          1
-#define FUNC_GPIO36_GPIO36_0                        0
-
-#define PERIPHS_IO_MUX_GPIO37_U           (REG_IO_MUX_BASE +0x98)
-#define FUNC_GPIO37_SPIDQS                          4
-#define FUNC_GPIO37_SUBSPIQ                         3
-#define FUNC_GPIO37_FSPIQ                           2
-#define FUNC_GPIO37_GPIO37                          1
-#define FUNC_GPIO37_GPIO37_0                        0
-
-#define PERIPHS_IO_MUX_GPIO38_U           (REG_IO_MUX_BASE +0x9c)
-#define FUNC_GPIO38_SUBSPIWP                        3
-#define FUNC_GPIO38_FSPIWP                          2
-#define FUNC_GPIO38_GPIO38                          1
-#define FUNC_GPIO38_GPIO38_0                        0
-
-#define PERIPHS_IO_MUX_MTCK_U             (REG_IO_MUX_BASE +0xa0)
-#define FUNC_MTCK_SUBSPICS1                         3
-#define FUNC_MTCK_CLK_OUT3                          2
-#define FUNC_MTCK_GPIO39                            1
-#define FUNC_MTCK_MTCK                              0
-
-#define PERIPHS_IO_MUX_MTDO_U             (REG_IO_MUX_BASE +0xa4)
-#define FUNC_MTDO_CLK_OUT2                          2
-#define FUNC_MTDO_GPIO40                            1
-#define FUNC_MTDO_MTDO                              0
-
-#define PERIPHS_IO_MUX_MTDI_U             (REG_IO_MUX_BASE +0xa8)
-#define FUNC_MTDI_CLK_OUT1                          2
-#define FUNC_MTDI_GPIO41                            1
-#define FUNC_MTDI_MTDI                              0
-
-#define PERIPHS_IO_MUX_MTMS_U             (REG_IO_MUX_BASE +0xac)
-#define FUNC_MTMS_GPIO42                            1
-#define FUNC_MTMS_MTMS                              0
-
-#define PERIPHS_IO_MUX_U0TXD_U            (REG_IO_MUX_BASE +0xb0)
-#define FUNC_U0TXD_CLK_OUT1                         2
-#define FUNC_U0TXD_GPIO43                           1
-#define FUNC_U0TXD_U0TXD                            0
-
-#define PERIPHS_IO_MUX_U0RXD_U            (REG_IO_MUX_BASE +0xb4)
-#define FUNC_U0RXD_CLK_OUT2                         2
-#define FUNC_U0RXD_GPIO44                           1
-#define FUNC_U0RXD_U0RXD                            0
-
-#define PERIPHS_IO_MUX_GPIO45_U           (REG_IO_MUX_BASE +0xb8)
-#define FUNC_GPIO45_GPIO45                          1
-#define FUNC_GPIO45_GPIO45_0                        0
-
-#define PERIPHS_IO_MUX_GPIO46_U           (REG_IO_MUX_BASE +0xbc)
-#define FUNC_GPIO46_GPIO46                          1
-#define FUNC_GPIO46_GPIO46_0                        0
-
-#define PERIPHS_IO_MUX_SPICLK_P_U         (REG_IO_MUX_BASE +0xc0)
-#define FUNC_SPICLK_P_SUBSPICLK_DIFF                2
-#define FUNC_SPICLK_P_GPIO47                        1
-#define FUNC_SPICLK_P_SPICLK_DIFF                   0
-
-#define PERIPHS_IO_MUX_SPICLK_N_U         (REG_IO_MUX_BASE +0xc4)
-#define FUNC_SPICLK_N_SUBSPICLK_DIFF                2
-#define FUNC_SPICLK_N_GPIO48                        1
-#define FUNC_SPICLK_N_SPICLK_DIFF                   0
-
-
-#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
-#define IO_MUX_DATE 0xFFFFFFFF
-#define IO_MUX_DATE_S 0
-#define IO_MUX_DATE_VERSION 0x1907160
diff --git a/components/soc/esp32s3/include/soc/ledc_reg.h b/components/soc/esp32s3/include/soc/ledc_reg.h
deleted file mode 100644
index 23f5a5f8899..00000000000
--- a/components/soc/esp32s3/include/soc/ledc_reg.h
+++ /dev/null
@@ -1,1567 +0,0 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "soc.h"
-
-#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)
-/* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_ST_LSCH0 (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH0_M (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH0_V 0x1
-#define LEDC_OVF_CNT_RESET_ST_LSCH0_S 17
-/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH0 (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH0_M (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH0_V 0x1
-#define LEDC_OVF_CNT_RESET_LSCH0_S 16
-/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH0 (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH0_M (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH0_V 0x1
-#define LEDC_OVF_CNT_EN_LSCH0_S 15
-/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH0 0x000003FF
-#define LEDC_OVF_NUM_LSCH0_M ((LEDC_OVF_NUM_LSCH0_V) << (LEDC_OVF_NUM_LSCH0_S))
-#define LEDC_OVF_NUM_LSCH0_V 0x3FF
-#define LEDC_OVF_NUM_LSCH0_S 5
-/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH0 (BIT(4))
-#define LEDC_PARA_UP_LSCH0_M (BIT(4))
-#define LEDC_PARA_UP_LSCH0_V 0x1
-#define LEDC_PARA_UP_LSCH0_S 4
-/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH0 (BIT(3))
-#define LEDC_IDLE_LV_LSCH0_M (BIT(3))
-#define LEDC_IDLE_LV_LSCH0_V 0x1
-#define LEDC_IDLE_LV_LSCH0_S 3
-/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH0_V 0x1
-#define LEDC_SIG_OUT_EN_LSCH0_S 2
-/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH0 0x00000003
-#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V) << (LEDC_TIMER_SEL_LSCH0_S))
-#define LEDC_TIMER_SEL_LSCH0_V 0x3
-#define LEDC_TIMER_SEL_LSCH0_S 0
-
-#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004)
-/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH0 0x00003FFF
-#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V) << (LEDC_HPOINT_LSCH0_S))
-#define LEDC_HPOINT_LSCH0_V 0x3FFF
-#define LEDC_HPOINT_LSCH0_S 0
-
-#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008)
-/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH0 0x0007FFFF
-#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V) << (LEDC_DUTY_LSCH0_S))
-#define LEDC_DUTY_LSCH0_V 0x7FFFF
-#define LEDC_DUTY_LSCH0_S 0
-
-#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C)
-/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH0 (BIT(31))
-#define LEDC_DUTY_START_LSCH0_M (BIT(31))
-#define LEDC_DUTY_START_LSCH0_V 0x1
-#define LEDC_DUTY_START_LSCH0_S 31
-/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH0 (BIT(30))
-#define LEDC_DUTY_INC_LSCH0_M (BIT(30))
-#define LEDC_DUTY_INC_LSCH0_V 0x1
-#define LEDC_DUTY_INC_LSCH0_S 30
-/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH0 0x000003FF
-#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V) << (LEDC_DUTY_NUM_LSCH0_S))
-#define LEDC_DUTY_NUM_LSCH0_V 0x3FF
-#define LEDC_DUTY_NUM_LSCH0_S 20
-/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V) << (LEDC_DUTY_CYCLE_LSCH0_S))
-#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF
-#define LEDC_DUTY_CYCLE_LSCH0_S 10
-/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH0 0x000003FF
-#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V) << (LEDC_DUTY_SCALE_LSCH0_S))
-#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF
-#define LEDC_DUTY_SCALE_LSCH0_S 0
-
-#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010)
-/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH0 0x0007FFFF
-#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V) << (LEDC_DUTY_LSCH0_S))
-#define LEDC_DUTY_LSCH0_V 0x7FFFF
-#define LEDC_DUTY_LSCH0_S 0
-
-#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014)
-/* LEDC_OVF_CNT_RESET_ST_LSCH1 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_ST_LSCH1 (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH1_M (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH1_V 0x1
-#define LEDC_OVF_CNT_RESET_ST_LSCH1_S 17
-/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH1 (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH1_M (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH1_V 0x1
-#define LEDC_OVF_CNT_RESET_LSCH1_S 16
-/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH1 (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH1_M (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH1_V 0x1
-#define LEDC_OVF_CNT_EN_LSCH1_S 15
-/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH1 0x000003FF
-#define LEDC_OVF_NUM_LSCH1_M ((LEDC_OVF_NUM_LSCH1_V) << (LEDC_OVF_NUM_LSCH1_S))
-#define LEDC_OVF_NUM_LSCH1_V 0x3FF
-#define LEDC_OVF_NUM_LSCH1_S 5
-/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH1 (BIT(4))
-#define LEDC_PARA_UP_LSCH1_M (BIT(4))
-#define LEDC_PARA_UP_LSCH1_V 0x1
-#define LEDC_PARA_UP_LSCH1_S 4
-/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH1 (BIT(3))
-#define LEDC_IDLE_LV_LSCH1_M (BIT(3))
-#define LEDC_IDLE_LV_LSCH1_V 0x1
-#define LEDC_IDLE_LV_LSCH1_S 3
-/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH1_V 0x1
-#define LEDC_SIG_OUT_EN_LSCH1_S 2
-/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH1 0x00000003
-#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V) << (LEDC_TIMER_SEL_LSCH1_S))
-#define LEDC_TIMER_SEL_LSCH1_V 0x3
-#define LEDC_TIMER_SEL_LSCH1_S 0
-
-#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018)
-/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH1 0x00003FFF
-#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V) << (LEDC_HPOINT_LSCH1_S))
-#define LEDC_HPOINT_LSCH1_V 0x3FFF
-#define LEDC_HPOINT_LSCH1_S 0
-
-#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C)
-/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH1 0x0007FFFF
-#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V) << (LEDC_DUTY_LSCH1_S))
-#define LEDC_DUTY_LSCH1_V 0x7FFFF
-#define LEDC_DUTY_LSCH1_S 0
-
-#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020)
-/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH1 (BIT(31))
-#define LEDC_DUTY_START_LSCH1_M (BIT(31))
-#define LEDC_DUTY_START_LSCH1_V 0x1
-#define LEDC_DUTY_START_LSCH1_S 31
-/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH1 (BIT(30))
-#define LEDC_DUTY_INC_LSCH1_M (BIT(30))
-#define LEDC_DUTY_INC_LSCH1_V 0x1
-#define LEDC_DUTY_INC_LSCH1_S 30
-/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH1 0x000003FF
-#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V) << (LEDC_DUTY_NUM_LSCH1_S))
-#define LEDC_DUTY_NUM_LSCH1_V 0x3FF
-#define LEDC_DUTY_NUM_LSCH1_S 20
-/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V) << (LEDC_DUTY_CYCLE_LSCH1_S))
-#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF
-#define LEDC_DUTY_CYCLE_LSCH1_S 10
-/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH1 0x000003FF
-#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V) << (LEDC_DUTY_SCALE_LSCH1_S))
-#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF
-#define LEDC_DUTY_SCALE_LSCH1_S 0
-
-#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024)
-/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH1 0x0007FFFF
-#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V) << (LEDC_DUTY_LSCH1_S))
-#define LEDC_DUTY_LSCH1_V 0x7FFFF
-#define LEDC_DUTY_LSCH1_S 0
-
-#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028)
-/* LEDC_OVF_CNT_RESET_ST_LSCH2 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_ST_LSCH2 (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH2_M (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH2_V 0x1
-#define LEDC_OVF_CNT_RESET_ST_LSCH2_S 17
-/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH2 (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH2_M (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH2_V 0x1
-#define LEDC_OVF_CNT_RESET_LSCH2_S 16
-/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH2 (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH2_M (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH2_V 0x1
-#define LEDC_OVF_CNT_EN_LSCH2_S 15
-/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH2 0x000003FF
-#define LEDC_OVF_NUM_LSCH2_M ((LEDC_OVF_NUM_LSCH2_V) << (LEDC_OVF_NUM_LSCH2_S))
-#define LEDC_OVF_NUM_LSCH2_V 0x3FF
-#define LEDC_OVF_NUM_LSCH2_S 5
-/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH2 (BIT(4))
-#define LEDC_PARA_UP_LSCH2_M (BIT(4))
-#define LEDC_PARA_UP_LSCH2_V 0x1
-#define LEDC_PARA_UP_LSCH2_S 4
-/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH2 (BIT(3))
-#define LEDC_IDLE_LV_LSCH2_M (BIT(3))
-#define LEDC_IDLE_LV_LSCH2_V 0x1
-#define LEDC_IDLE_LV_LSCH2_S 3
-/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH2_V 0x1
-#define LEDC_SIG_OUT_EN_LSCH2_S 2
-/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH2 0x00000003
-#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V) << (LEDC_TIMER_SEL_LSCH2_S))
-#define LEDC_TIMER_SEL_LSCH2_V 0x3
-#define LEDC_TIMER_SEL_LSCH2_S 0
-
-#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C)
-/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH2 0x00003FFF
-#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V) << (LEDC_HPOINT_LSCH2_S))
-#define LEDC_HPOINT_LSCH2_V 0x3FFF
-#define LEDC_HPOINT_LSCH2_S 0
-
-#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030)
-/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH2 0x0007FFFF
-#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V) << (LEDC_DUTY_LSCH2_S))
-#define LEDC_DUTY_LSCH2_V 0x7FFFF
-#define LEDC_DUTY_LSCH2_S 0
-
-#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034)
-/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH2 (BIT(31))
-#define LEDC_DUTY_START_LSCH2_M (BIT(31))
-#define LEDC_DUTY_START_LSCH2_V 0x1
-#define LEDC_DUTY_START_LSCH2_S 31
-/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH2 (BIT(30))
-#define LEDC_DUTY_INC_LSCH2_M (BIT(30))
-#define LEDC_DUTY_INC_LSCH2_V 0x1
-#define LEDC_DUTY_INC_LSCH2_S 30
-/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH2 0x000003FF
-#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V) << (LEDC_DUTY_NUM_LSCH2_S))
-#define LEDC_DUTY_NUM_LSCH2_V 0x3FF
-#define LEDC_DUTY_NUM_LSCH2_S 20
-/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V) << (LEDC_DUTY_CYCLE_LSCH2_S))
-#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF
-#define LEDC_DUTY_CYCLE_LSCH2_S 10
-/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH2 0x000003FF
-#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V) << (LEDC_DUTY_SCALE_LSCH2_S))
-#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF
-#define LEDC_DUTY_SCALE_LSCH2_S 0
-
-#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038)
-/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH2 0x0007FFFF
-#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V) << (LEDC_DUTY_LSCH2_S))
-#define LEDC_DUTY_LSCH2_V 0x7FFFF
-#define LEDC_DUTY_LSCH2_S 0
-
-#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C)
-/* LEDC_OVF_CNT_RESET_ST_LSCH3 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_ST_LSCH3 (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH3_M (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH3_V 0x1
-#define LEDC_OVF_CNT_RESET_ST_LSCH3_S 17
-/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH3 (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH3_M (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH3_V 0x1
-#define LEDC_OVF_CNT_RESET_LSCH3_S 16
-/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH3 (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH3_M (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH3_V 0x1
-#define LEDC_OVF_CNT_EN_LSCH3_S 15
-/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH3 0x000003FF
-#define LEDC_OVF_NUM_LSCH3_M ((LEDC_OVF_NUM_LSCH3_V) << (LEDC_OVF_NUM_LSCH3_S))
-#define LEDC_OVF_NUM_LSCH3_V 0x3FF
-#define LEDC_OVF_NUM_LSCH3_S 5
-/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH3 (BIT(4))
-#define LEDC_PARA_UP_LSCH3_M (BIT(4))
-#define LEDC_PARA_UP_LSCH3_V 0x1
-#define LEDC_PARA_UP_LSCH3_S 4
-/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH3 (BIT(3))
-#define LEDC_IDLE_LV_LSCH3_M (BIT(3))
-#define LEDC_IDLE_LV_LSCH3_V 0x1
-#define LEDC_IDLE_LV_LSCH3_S 3
-/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH3_V 0x1
-#define LEDC_SIG_OUT_EN_LSCH3_S 2
-/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH3 0x00000003
-#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V) << (LEDC_TIMER_SEL_LSCH3_S))
-#define LEDC_TIMER_SEL_LSCH3_V 0x3
-#define LEDC_TIMER_SEL_LSCH3_S 0
-
-#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040)
-/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH3 0x00003FFF
-#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V) << (LEDC_HPOINT_LSCH3_S))
-#define LEDC_HPOINT_LSCH3_V 0x3FFF
-#define LEDC_HPOINT_LSCH3_S 0
-
-#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044)
-/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH3 0x0007FFFF
-#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V) << (LEDC_DUTY_LSCH3_S))
-#define LEDC_DUTY_LSCH3_V 0x7FFFF
-#define LEDC_DUTY_LSCH3_S 0
-
-#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048)
-/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH3 (BIT(31))
-#define LEDC_DUTY_START_LSCH3_M (BIT(31))
-#define LEDC_DUTY_START_LSCH3_V 0x1
-#define LEDC_DUTY_START_LSCH3_S 31
-/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH3 (BIT(30))
-#define LEDC_DUTY_INC_LSCH3_M (BIT(30))
-#define LEDC_DUTY_INC_LSCH3_V 0x1
-#define LEDC_DUTY_INC_LSCH3_S 30
-/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH3 0x000003FF
-#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V) << (LEDC_DUTY_NUM_LSCH3_S))
-#define LEDC_DUTY_NUM_LSCH3_V 0x3FF
-#define LEDC_DUTY_NUM_LSCH3_S 20
-/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V) << (LEDC_DUTY_CYCLE_LSCH3_S))
-#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF
-#define LEDC_DUTY_CYCLE_LSCH3_S 10
-/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH3 0x000003FF
-#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V) << (LEDC_DUTY_SCALE_LSCH3_S))
-#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF
-#define LEDC_DUTY_SCALE_LSCH3_S 0
-
-#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C)
-/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH3 0x0007FFFF
-#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V) << (LEDC_DUTY_LSCH3_S))
-#define LEDC_DUTY_LSCH3_V 0x7FFFF
-#define LEDC_DUTY_LSCH3_S 0
-
-#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050)
-/* LEDC_OVF_CNT_RESET_ST_LSCH4 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_ST_LSCH4 (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH4_M (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH4_V 0x1
-#define LEDC_OVF_CNT_RESET_ST_LSCH4_S 17
-/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH4 (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH4_M (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH4_V 0x1
-#define LEDC_OVF_CNT_RESET_LSCH4_S 16
-/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH4 (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH4_M (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH4_V 0x1
-#define LEDC_OVF_CNT_EN_LSCH4_S 15
-/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH4 0x000003FF
-#define LEDC_OVF_NUM_LSCH4_M ((LEDC_OVF_NUM_LSCH4_V) << (LEDC_OVF_NUM_LSCH4_S))
-#define LEDC_OVF_NUM_LSCH4_V 0x3FF
-#define LEDC_OVF_NUM_LSCH4_S 5
-/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH4 (BIT(4))
-#define LEDC_PARA_UP_LSCH4_M (BIT(4))
-#define LEDC_PARA_UP_LSCH4_V 0x1
-#define LEDC_PARA_UP_LSCH4_S 4
-/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH4 (BIT(3))
-#define LEDC_IDLE_LV_LSCH4_M (BIT(3))
-#define LEDC_IDLE_LV_LSCH4_V 0x1
-#define LEDC_IDLE_LV_LSCH4_S 3
-/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH4_V 0x1
-#define LEDC_SIG_OUT_EN_LSCH4_S 2
-/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH4 0x00000003
-#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V) << (LEDC_TIMER_SEL_LSCH4_S))
-#define LEDC_TIMER_SEL_LSCH4_V 0x3
-#define LEDC_TIMER_SEL_LSCH4_S 0
-
-#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054)
-/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH4 0x00003FFF
-#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V) << (LEDC_HPOINT_LSCH4_S))
-#define LEDC_HPOINT_LSCH4_V 0x3FFF
-#define LEDC_HPOINT_LSCH4_S 0
-
-#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058)
-/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH4 0x0007FFFF
-#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V) << (LEDC_DUTY_LSCH4_S))
-#define LEDC_DUTY_LSCH4_V 0x7FFFF
-#define LEDC_DUTY_LSCH4_S 0
-
-#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C)
-/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH4 (BIT(31))
-#define LEDC_DUTY_START_LSCH4_M (BIT(31))
-#define LEDC_DUTY_START_LSCH4_V 0x1
-#define LEDC_DUTY_START_LSCH4_S 31
-/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH4 (BIT(30))
-#define LEDC_DUTY_INC_LSCH4_M (BIT(30))
-#define LEDC_DUTY_INC_LSCH4_V 0x1
-#define LEDC_DUTY_INC_LSCH4_S 30
-/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH4 0x000003FF
-#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V) << (LEDC_DUTY_NUM_LSCH4_S))
-#define LEDC_DUTY_NUM_LSCH4_V 0x3FF
-#define LEDC_DUTY_NUM_LSCH4_S 20
-/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V) << (LEDC_DUTY_CYCLE_LSCH4_S))
-#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF
-#define LEDC_DUTY_CYCLE_LSCH4_S 10
-/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH4 0x000003FF
-#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V) << (LEDC_DUTY_SCALE_LSCH4_S))
-#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF
-#define LEDC_DUTY_SCALE_LSCH4_S 0
-
-#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060)
-/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH4 0x0007FFFF
-#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V) << (LEDC_DUTY_LSCH4_S))
-#define LEDC_DUTY_LSCH4_V 0x7FFFF
-#define LEDC_DUTY_LSCH4_S 0
-
-#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064)
-/* LEDC_OVF_CNT_RESET_ST_LSCH5 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_ST_LSCH5 (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH5_M (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH5_V 0x1
-#define LEDC_OVF_CNT_RESET_ST_LSCH5_S 17
-/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH5 (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH5_M (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH5_V 0x1
-#define LEDC_OVF_CNT_RESET_LSCH5_S 16
-/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH5 (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH5_M (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH5_V 0x1
-#define LEDC_OVF_CNT_EN_LSCH5_S 15
-/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH5 0x000003FF
-#define LEDC_OVF_NUM_LSCH5_M ((LEDC_OVF_NUM_LSCH5_V) << (LEDC_OVF_NUM_LSCH5_S))
-#define LEDC_OVF_NUM_LSCH5_V 0x3FF
-#define LEDC_OVF_NUM_LSCH5_S 5
-/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH5 (BIT(4))
-#define LEDC_PARA_UP_LSCH5_M (BIT(4))
-#define LEDC_PARA_UP_LSCH5_V 0x1
-#define LEDC_PARA_UP_LSCH5_S 4
-/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH5 (BIT(3))
-#define LEDC_IDLE_LV_LSCH5_M (BIT(3))
-#define LEDC_IDLE_LV_LSCH5_V 0x1
-#define LEDC_IDLE_LV_LSCH5_S 3
-/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH5_V 0x1
-#define LEDC_SIG_OUT_EN_LSCH5_S 2
-/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH5 0x00000003
-#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V) << (LEDC_TIMER_SEL_LSCH5_S))
-#define LEDC_TIMER_SEL_LSCH5_V 0x3
-#define LEDC_TIMER_SEL_LSCH5_S 0
-
-#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068)
-/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH5 0x00003FFF
-#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V) << (LEDC_HPOINT_LSCH5_S))
-#define LEDC_HPOINT_LSCH5_V 0x3FFF
-#define LEDC_HPOINT_LSCH5_S 0
-
-#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C)
-/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH5 0x0007FFFF
-#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V) << (LEDC_DUTY_LSCH5_S))
-#define LEDC_DUTY_LSCH5_V 0x7FFFF
-#define LEDC_DUTY_LSCH5_S 0
-
-#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070)
-/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH5 (BIT(31))
-#define LEDC_DUTY_START_LSCH5_M (BIT(31))
-#define LEDC_DUTY_START_LSCH5_V 0x1
-#define LEDC_DUTY_START_LSCH5_S 31
-/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH5 (BIT(30))
-#define LEDC_DUTY_INC_LSCH5_M (BIT(30))
-#define LEDC_DUTY_INC_LSCH5_V 0x1
-#define LEDC_DUTY_INC_LSCH5_S 30
-/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH5 0x000003FF
-#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V) << (LEDC_DUTY_NUM_LSCH5_S))
-#define LEDC_DUTY_NUM_LSCH5_V 0x3FF
-#define LEDC_DUTY_NUM_LSCH5_S 20
-/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V) << (LEDC_DUTY_CYCLE_LSCH5_S))
-#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF
-#define LEDC_DUTY_CYCLE_LSCH5_S 10
-/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH5 0x000003FF
-#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V) << (LEDC_DUTY_SCALE_LSCH5_S))
-#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF
-#define LEDC_DUTY_SCALE_LSCH5_S 0
-
-#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074)
-/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH5 0x0007FFFF
-#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V) << (LEDC_DUTY_LSCH5_S))
-#define LEDC_DUTY_LSCH5_V 0x7FFFF
-#define LEDC_DUTY_LSCH5_S 0
-
-#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078)
-/* LEDC_OVF_CNT_RESET_ST_LSCH6 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_ST_LSCH6 (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH6_M (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH6_V 0x1
-#define LEDC_OVF_CNT_RESET_ST_LSCH6_S 17
-/* LEDC_OVF_CNT_RESET_LSCH6 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH6 (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH6_M (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH6_V 0x1
-#define LEDC_OVF_CNT_RESET_LSCH6_S 16
-/* LEDC_OVF_CNT_EN_LSCH6 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH6 (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH6_M (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH6_V 0x1
-#define LEDC_OVF_CNT_EN_LSCH6_S 15
-/* LEDC_OVF_NUM_LSCH6 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH6 0x000003FF
-#define LEDC_OVF_NUM_LSCH6_M ((LEDC_OVF_NUM_LSCH6_V) << (LEDC_OVF_NUM_LSCH6_S))
-#define LEDC_OVF_NUM_LSCH6_V 0x3FF
-#define LEDC_OVF_NUM_LSCH6_S 5
-/* LEDC_PARA_UP_LSCH6 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH6 (BIT(4))
-#define LEDC_PARA_UP_LSCH6_M (BIT(4))
-#define LEDC_PARA_UP_LSCH6_V 0x1
-#define LEDC_PARA_UP_LSCH6_S 4
-/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH6 (BIT(3))
-#define LEDC_IDLE_LV_LSCH6_M (BIT(3))
-#define LEDC_IDLE_LV_LSCH6_V 0x1
-#define LEDC_IDLE_LV_LSCH6_S 3
-/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH6_V 0x1
-#define LEDC_SIG_OUT_EN_LSCH6_S 2
-/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH6 0x00000003
-#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V) << (LEDC_TIMER_SEL_LSCH6_S))
-#define LEDC_TIMER_SEL_LSCH6_V 0x3
-#define LEDC_TIMER_SEL_LSCH6_S 0
-
-#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C)
-/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH6 0x00003FFF
-#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V) << (LEDC_HPOINT_LSCH6_S))
-#define LEDC_HPOINT_LSCH6_V 0x3FFF
-#define LEDC_HPOINT_LSCH6_S 0
-
-#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080)
-/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH6 0x0007FFFF
-#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V) << (LEDC_DUTY_LSCH6_S))
-#define LEDC_DUTY_LSCH6_V 0x7FFFF
-#define LEDC_DUTY_LSCH6_S 0
-
-#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084)
-/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH6 (BIT(31))
-#define LEDC_DUTY_START_LSCH6_M (BIT(31))
-#define LEDC_DUTY_START_LSCH6_V 0x1
-#define LEDC_DUTY_START_LSCH6_S 31
-/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH6 (BIT(30))
-#define LEDC_DUTY_INC_LSCH6_M (BIT(30))
-#define LEDC_DUTY_INC_LSCH6_V 0x1
-#define LEDC_DUTY_INC_LSCH6_S 30
-/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH6 0x000003FF
-#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V) << (LEDC_DUTY_NUM_LSCH6_S))
-#define LEDC_DUTY_NUM_LSCH6_V 0x3FF
-#define LEDC_DUTY_NUM_LSCH6_S 20
-/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V) << (LEDC_DUTY_CYCLE_LSCH6_S))
-#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF
-#define LEDC_DUTY_CYCLE_LSCH6_S 10
-/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH6 0x000003FF
-#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V) << (LEDC_DUTY_SCALE_LSCH6_S))
-#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF
-#define LEDC_DUTY_SCALE_LSCH6_S 0
-
-#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088)
-/* LEDC_DUTY_LSCH6 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH6 0x0007FFFF
-#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V) << (LEDC_DUTY_LSCH6_S))
-#define LEDC_DUTY_LSCH6_V 0x7FFFF
-#define LEDC_DUTY_LSCH6_S 0
-
-#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C)
-/* LEDC_OVF_CNT_RESET_ST_LSCH7 : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_ST_LSCH7 (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH7_M (BIT(17))
-#define LEDC_OVF_CNT_RESET_ST_LSCH7_V 0x1
-#define LEDC_OVF_CNT_RESET_ST_LSCH7_S 17
-/* LEDC_OVF_CNT_RESET_LSCH7 : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_RESET_LSCH7 (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH7_M (BIT(16))
-#define LEDC_OVF_CNT_RESET_LSCH7_V 0x1
-#define LEDC_OVF_CNT_RESET_LSCH7_S 16
-/* LEDC_OVF_CNT_EN_LSCH7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_EN_LSCH7 (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH7_M (BIT(15))
-#define LEDC_OVF_CNT_EN_LSCH7_V 0x1
-#define LEDC_OVF_CNT_EN_LSCH7_S 15
-/* LEDC_OVF_NUM_LSCH7 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
-/*description: */
-#define LEDC_OVF_NUM_LSCH7 0x000003FF
-#define LEDC_OVF_NUM_LSCH7_M ((LEDC_OVF_NUM_LSCH7_V) << (LEDC_OVF_NUM_LSCH7_S))
-#define LEDC_OVF_NUM_LSCH7_V 0x3FF
-#define LEDC_OVF_NUM_LSCH7_S 5
-/* LEDC_PARA_UP_LSCH7 : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_PARA_UP_LSCH7 (BIT(4))
-#define LEDC_PARA_UP_LSCH7_M (BIT(4))
-#define LEDC_PARA_UP_LSCH7_V 0x1
-#define LEDC_PARA_UP_LSCH7_S 4
-/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_IDLE_LV_LSCH7 (BIT(3))
-#define LEDC_IDLE_LV_LSCH7_M (BIT(3))
-#define LEDC_IDLE_LV_LSCH7_V 0x1
-#define LEDC_IDLE_LV_LSCH7_S 3
-/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2))
-#define LEDC_SIG_OUT_EN_LSCH7_V 0x1
-#define LEDC_SIG_OUT_EN_LSCH7_S 2
-/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: */
-#define LEDC_TIMER_SEL_LSCH7 0x00000003
-#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V) << (LEDC_TIMER_SEL_LSCH7_S))
-#define LEDC_TIMER_SEL_LSCH7_V 0x3
-#define LEDC_TIMER_SEL_LSCH7_S 0
-
-#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090)
-/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
-/*description: */
-#define LEDC_HPOINT_LSCH7 0x00003FFF
-#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V) << (LEDC_HPOINT_LSCH7_S))
-#define LEDC_HPOINT_LSCH7_V 0x3FFF
-#define LEDC_HPOINT_LSCH7_S 0
-
-#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094)
-/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH7 0x0007FFFF
-#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V) << (LEDC_DUTY_LSCH7_S))
-#define LEDC_DUTY_LSCH7_V 0x7FFFF
-#define LEDC_DUTY_LSCH7_S 0
-
-#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098)
-/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_START_LSCH7 (BIT(31))
-#define LEDC_DUTY_START_LSCH7_M (BIT(31))
-#define LEDC_DUTY_START_LSCH7_V 0x1
-#define LEDC_DUTY_START_LSCH7_S 31
-/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_DUTY_INC_LSCH7 (BIT(30))
-#define LEDC_DUTY_INC_LSCH7_M (BIT(30))
-#define LEDC_DUTY_INC_LSCH7_V 0x1
-#define LEDC_DUTY_INC_LSCH7_S 30
-/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_NUM_LSCH7 0x000003FF
-#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V) << (LEDC_DUTY_NUM_LSCH7_S))
-#define LEDC_DUTY_NUM_LSCH7_V 0x3FF
-#define LEDC_DUTY_NUM_LSCH7_S 20
-/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF
-#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V) << (LEDC_DUTY_CYCLE_LSCH7_S))
-#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF
-#define LEDC_DUTY_CYCLE_LSCH7_S 10
-/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: */
-#define LEDC_DUTY_SCALE_LSCH7 0x000003FF
-#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V) << (LEDC_DUTY_SCALE_LSCH7_S))
-#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF
-#define LEDC_DUTY_SCALE_LSCH7_S 0
-
-#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C)
-/* LEDC_DUTY_LSCH7 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
-/*description: */
-#define LEDC_DUTY_LSCH7 0x0007FFFF
-#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V) << (LEDC_DUTY_LSCH7_S))
-#define LEDC_DUTY_LSCH7_V 0x7FFFF
-#define LEDC_DUTY_LSCH7_S 0
-
-#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x00a0)
-/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER0_PARA_UP (BIT(25))
-#define LEDC_LSTIMER0_PARA_UP_M (BIT(25))
-#define LEDC_LSTIMER0_PARA_UP_V 0x1
-#define LEDC_LSTIMER0_PARA_UP_S 25
-/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER0 (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER0_M (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER0_V 0x1
-#define LEDC_TICK_SEL_LSTIMER0_S 24
-/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER0_RST (BIT(23))
-#define LEDC_LSTIMER0_RST_M (BIT(23))
-#define LEDC_LSTIMER0_RST_V 0x1
-#define LEDC_LSTIMER0_RST_S 23
-/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_PAUSE (BIT(22))
-#define LEDC_LSTIMER0_PAUSE_M (BIT(22))
-#define LEDC_LSTIMER0_PAUSE_V 0x1
-#define LEDC_LSTIMER0_PAUSE_S 22
-/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER0 0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER0_M ((LEDC_CLK_DIV_LSTIMER0_V) << (LEDC_CLK_DIV_LSTIMER0_S))
-#define LEDC_CLK_DIV_LSTIMER0_V 0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER0_S 4
-/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER0_DUTY_RES 0x0000000F
-#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V) << (LEDC_LSTIMER0_DUTY_RES_S))
-#define LEDC_LSTIMER0_DUTY_RES_V 0xF
-#define LEDC_LSTIMER0_DUTY_RES_S 0
-
-#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x00a4)
-/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_CNT 0x00003FFF
-#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V) << (LEDC_LSTIMER0_CNT_S))
-#define LEDC_LSTIMER0_CNT_V 0x3FFF
-#define LEDC_LSTIMER0_CNT_S 0
-
-#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x00a8)
-/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER1_PARA_UP (BIT(25))
-#define LEDC_LSTIMER1_PARA_UP_M (BIT(25))
-#define LEDC_LSTIMER1_PARA_UP_V 0x1
-#define LEDC_LSTIMER1_PARA_UP_S 25
-/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER1 (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER1_M (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER1_V 0x1
-#define LEDC_TICK_SEL_LSTIMER1_S 24
-/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER1_RST (BIT(23))
-#define LEDC_LSTIMER1_RST_M (BIT(23))
-#define LEDC_LSTIMER1_RST_V 0x1
-#define LEDC_LSTIMER1_RST_S 23
-/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_PAUSE (BIT(22))
-#define LEDC_LSTIMER1_PAUSE_M (BIT(22))
-#define LEDC_LSTIMER1_PAUSE_V 0x1
-#define LEDC_LSTIMER1_PAUSE_S 22
-/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER1 0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER1_M ((LEDC_CLK_DIV_LSTIMER1_V) << (LEDC_CLK_DIV_LSTIMER1_S))
-#define LEDC_CLK_DIV_LSTIMER1_V 0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER1_S 4
-/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER1_DUTY_RES 0x0000000F
-#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V) << (LEDC_LSTIMER1_DUTY_RES_S))
-#define LEDC_LSTIMER1_DUTY_RES_V 0xF
-#define LEDC_LSTIMER1_DUTY_RES_S 0
-
-#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x00aC)
-/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_CNT 0x00003FFF
-#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V) << (LEDC_LSTIMER1_CNT_S))
-#define LEDC_LSTIMER1_CNT_V 0x3FFF
-#define LEDC_LSTIMER1_CNT_S 0
-
-#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x00b0)
-/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER2_PARA_UP (BIT(25))
-#define LEDC_LSTIMER2_PARA_UP_M (BIT(25))
-#define LEDC_LSTIMER2_PARA_UP_V 0x1
-#define LEDC_LSTIMER2_PARA_UP_S 25
-/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER2 (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER2_M (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER2_V 0x1
-#define LEDC_TICK_SEL_LSTIMER2_S 24
-/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER2_RST (BIT(23))
-#define LEDC_LSTIMER2_RST_M (BIT(23))
-#define LEDC_LSTIMER2_RST_V 0x1
-#define LEDC_LSTIMER2_RST_S 23
-/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_PAUSE (BIT(22))
-#define LEDC_LSTIMER2_PAUSE_M (BIT(22))
-#define LEDC_LSTIMER2_PAUSE_V 0x1
-#define LEDC_LSTIMER2_PAUSE_S 22
-/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER2 0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER2_M ((LEDC_CLK_DIV_LSTIMER2_V) << (LEDC_CLK_DIV_LSTIMER2_S))
-#define LEDC_CLK_DIV_LSTIMER2_V 0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER2_S 4
-/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER2_DUTY_RES 0x0000000F
-#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V) << (LEDC_LSTIMER2_DUTY_RES_S))
-#define LEDC_LSTIMER2_DUTY_RES_V 0xF
-#define LEDC_LSTIMER2_DUTY_RES_S 0
-
-#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x00b4)
-/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_CNT 0x00003FFF
-#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V) << (LEDC_LSTIMER2_CNT_S))
-#define LEDC_LSTIMER2_CNT_V 0x3FFF
-#define LEDC_LSTIMER2_CNT_S 0
-
-#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x00b8)
-/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_LSTIMER3_PARA_UP (BIT(25))
-#define LEDC_LSTIMER3_PARA_UP_M (BIT(25))
-#define LEDC_LSTIMER3_PARA_UP_V 0x1
-#define LEDC_LSTIMER3_PARA_UP_S 25
-/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_TICK_SEL_LSTIMER3 (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER3_M (BIT(24))
-#define LEDC_TICK_SEL_LSTIMER3_V 0x1
-#define LEDC_TICK_SEL_LSTIMER3_S 24
-/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: */
-#define LEDC_LSTIMER3_RST (BIT(23))
-#define LEDC_LSTIMER3_RST_M (BIT(23))
-#define LEDC_LSTIMER3_RST_V 0x1
-#define LEDC_LSTIMER3_RST_S 23
-/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_PAUSE (BIT(22))
-#define LEDC_LSTIMER3_PAUSE_M (BIT(22))
-#define LEDC_LSTIMER3_PAUSE_V 0x1
-#define LEDC_LSTIMER3_PAUSE_S 22
-/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
-/*description: */
-#define LEDC_CLK_DIV_LSTIMER3 0x0003FFFF
-#define LEDC_CLK_DIV_LSTIMER3_M ((LEDC_CLK_DIV_LSTIMER3_V) << (LEDC_CLK_DIV_LSTIMER3_S))
-#define LEDC_CLK_DIV_LSTIMER3_V 0x3FFFF
-#define LEDC_CLK_DIV_LSTIMER3_S 4
-/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: */
-#define LEDC_LSTIMER3_DUTY_RES 0x0000000F
-#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V) << (LEDC_LSTIMER3_DUTY_RES_S))
-#define LEDC_LSTIMER3_DUTY_RES_V 0xF
-#define LEDC_LSTIMER3_DUTY_RES_S 0
-
-#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x00bC)
-/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_CNT 0x00003FFF
-#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V) << (LEDC_LSTIMER3_CNT_S))
-#define LEDC_LSTIMER3_CNT_V 0x3FFF
-#define LEDC_LSTIMER3_CNT_S 0
-
-#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x00c0)
-/* LEDC_OVF_CNT_LSCH7_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH7_INT_RAW (BIT(19))
-#define LEDC_OVF_CNT_LSCH7_INT_RAW_M (BIT(19))
-#define LEDC_OVF_CNT_LSCH7_INT_RAW_V 0x1
-#define LEDC_OVF_CNT_LSCH7_INT_RAW_S 19
-/* LEDC_OVF_CNT_LSCH6_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH6_INT_RAW (BIT(18))
-#define LEDC_OVF_CNT_LSCH6_INT_RAW_M (BIT(18))
-#define LEDC_OVF_CNT_LSCH6_INT_RAW_V 0x1
-#define LEDC_OVF_CNT_LSCH6_INT_RAW_S 18
-/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_RAW (BIT(17))
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_M (BIT(17))
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_V 0x1
-#define LEDC_OVF_CNT_LSCH5_INT_RAW_S 17
-/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_RAW (BIT(16))
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_M (BIT(16))
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_V 0x1
-#define LEDC_OVF_CNT_LSCH4_INT_RAW_S 16
-/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_RAW (BIT(15))
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_M (BIT(15))
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_V 0x1
-#define LEDC_OVF_CNT_LSCH3_INT_RAW_S 15
-/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_RAW (BIT(14))
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_M (BIT(14))
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_V 0x1
-#define LEDC_OVF_CNT_LSCH2_INT_RAW_S 14
-/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_RAW (BIT(13))
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_M (BIT(13))
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_V 0x1
-#define LEDC_OVF_CNT_LSCH1_INT_RAW_S 13
-/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_RAW (BIT(12))
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_M (BIT(12))
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_V 0x1
-#define LEDC_OVF_CNT_LSCH0_INT_RAW_S 12
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(11))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(11))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 11
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(10))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(10))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 4
-/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1
-#define LEDC_LSTIMER3_OVF_INT_RAW_S 3
-/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1
-#define LEDC_LSTIMER2_OVF_INT_RAW_S 2
-/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1
-#define LEDC_LSTIMER1_OVF_INT_RAW_S 1
-/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1
-#define LEDC_LSTIMER0_OVF_INT_RAW_S 0
-
-#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x00c4)
-/* LEDC_OVF_CNT_LSCH7_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH7_INT_ST (BIT(19))
-#define LEDC_OVF_CNT_LSCH7_INT_ST_M (BIT(19))
-#define LEDC_OVF_CNT_LSCH7_INT_ST_V 0x1
-#define LEDC_OVF_CNT_LSCH7_INT_ST_S 19
-/* LEDC_OVF_CNT_LSCH6_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH6_INT_ST (BIT(18))
-#define LEDC_OVF_CNT_LSCH6_INT_ST_M (BIT(18))
-#define LEDC_OVF_CNT_LSCH6_INT_ST_V 0x1
-#define LEDC_OVF_CNT_LSCH6_INT_ST_S 18
-/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_ST (BIT(17))
-#define LEDC_OVF_CNT_LSCH5_INT_ST_M (BIT(17))
-#define LEDC_OVF_CNT_LSCH5_INT_ST_V 0x1
-#define LEDC_OVF_CNT_LSCH5_INT_ST_S 17
-/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_ST (BIT(16))
-#define LEDC_OVF_CNT_LSCH4_INT_ST_M (BIT(16))
-#define LEDC_OVF_CNT_LSCH4_INT_ST_V 0x1
-#define LEDC_OVF_CNT_LSCH4_INT_ST_S 16
-/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_ST (BIT(15))
-#define LEDC_OVF_CNT_LSCH3_INT_ST_M (BIT(15))
-#define LEDC_OVF_CNT_LSCH3_INT_ST_V 0x1
-#define LEDC_OVF_CNT_LSCH3_INT_ST_S 15
-/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_ST (BIT(14))
-#define LEDC_OVF_CNT_LSCH2_INT_ST_M (BIT(14))
-#define LEDC_OVF_CNT_LSCH2_INT_ST_V 0x1
-#define LEDC_OVF_CNT_LSCH2_INT_ST_S 14
-/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_ST (BIT(13))
-#define LEDC_OVF_CNT_LSCH1_INT_ST_M (BIT(13))
-#define LEDC_OVF_CNT_LSCH1_INT_ST_V 0x1
-#define LEDC_OVF_CNT_LSCH1_INT_ST_S 13
-/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_ST (BIT(12))
-#define LEDC_OVF_CNT_LSCH0_INT_ST_M (BIT(12))
-#define LEDC_OVF_CNT_LSCH0_INT_ST_V 0x1
-#define LEDC_OVF_CNT_LSCH0_INT_ST_S 12
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[11] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(11))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(11))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 11
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(10))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(10))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 4
-/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_ST (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1
-#define LEDC_LSTIMER3_OVF_INT_ST_S 3
-/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_ST (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1
-#define LEDC_LSTIMER2_OVF_INT_ST_S 2
-/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_ST (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1
-#define LEDC_LSTIMER1_OVF_INT_ST_S 1
-/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_ST (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1
-#define LEDC_LSTIMER0_OVF_INT_ST_S 0
-
-#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x00c8)
-/* LEDC_OVF_CNT_LSCH7_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH7_INT_ENA (BIT(19))
-#define LEDC_OVF_CNT_LSCH7_INT_ENA_M (BIT(19))
-#define LEDC_OVF_CNT_LSCH7_INT_ENA_V 0x1
-#define LEDC_OVF_CNT_LSCH7_INT_ENA_S 19
-/* LEDC_OVF_CNT_LSCH6_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH6_INT_ENA (BIT(18))
-#define LEDC_OVF_CNT_LSCH6_INT_ENA_M (BIT(18))
-#define LEDC_OVF_CNT_LSCH6_INT_ENA_V 0x1
-#define LEDC_OVF_CNT_LSCH6_INT_ENA_S 18
-/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_ENA (BIT(17))
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_M (BIT(17))
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_V 0x1
-#define LEDC_OVF_CNT_LSCH5_INT_ENA_S 17
-/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_ENA (BIT(16))
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_M (BIT(16))
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_V 0x1
-#define LEDC_OVF_CNT_LSCH4_INT_ENA_S 16
-/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_ENA (BIT(15))
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_M (BIT(15))
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_V 0x1
-#define LEDC_OVF_CNT_LSCH3_INT_ENA_S 15
-/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_ENA (BIT(14))
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_M (BIT(14))
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_V 0x1
-#define LEDC_OVF_CNT_LSCH2_INT_ENA_S 14
-/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_ENA (BIT(13))
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_M (BIT(13))
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_V 0x1
-#define LEDC_OVF_CNT_LSCH1_INT_ENA_S 13
-/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_ENA (BIT(12))
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_M (BIT(12))
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_V 0x1
-#define LEDC_OVF_CNT_LSCH0_INT_ENA_S 12
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[11] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(11))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(11))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 11
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(10))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(10))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 4
-/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1
-#define LEDC_LSTIMER3_OVF_INT_ENA_S 3
-/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1
-#define LEDC_LSTIMER2_OVF_INT_ENA_S 2
-/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1
-#define LEDC_LSTIMER1_OVF_INT_ENA_S 1
-/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1
-#define LEDC_LSTIMER0_OVF_INT_ENA_S 0
-
-#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x00cC)
-/* LEDC_OVF_CNT_LSCH7_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH7_INT_CLR (BIT(19))
-#define LEDC_OVF_CNT_LSCH7_INT_CLR_M (BIT(19))
-#define LEDC_OVF_CNT_LSCH7_INT_CLR_V 0x1
-#define LEDC_OVF_CNT_LSCH7_INT_CLR_S 19
-/* LEDC_OVF_CNT_LSCH6_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH6_INT_CLR (BIT(18))
-#define LEDC_OVF_CNT_LSCH6_INT_CLR_M (BIT(18))
-#define LEDC_OVF_CNT_LSCH6_INT_CLR_V 0x1
-#define LEDC_OVF_CNT_LSCH6_INT_CLR_S 18
-/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH5_INT_CLR (BIT(17))
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_M (BIT(17))
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_V 0x1
-#define LEDC_OVF_CNT_LSCH5_INT_CLR_S 17
-/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH4_INT_CLR (BIT(16))
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_M (BIT(16))
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_V 0x1
-#define LEDC_OVF_CNT_LSCH4_INT_CLR_S 16
-/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH3_INT_CLR (BIT(15))
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_M (BIT(15))
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_V 0x1
-#define LEDC_OVF_CNT_LSCH3_INT_CLR_S 15
-/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH2_INT_CLR (BIT(14))
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_M (BIT(14))
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_V 0x1
-#define LEDC_OVF_CNT_LSCH2_INT_CLR_S 14
-/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH1_INT_CLR (BIT(13))
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_M (BIT(13))
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_V 0x1
-#define LEDC_OVF_CNT_LSCH1_INT_CLR_S 13
-/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_OVF_CNT_LSCH0_INT_CLR (BIT(12))
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_M (BIT(12))
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_V 0x1
-#define LEDC_OVF_CNT_LSCH0_INT_CLR_S 12
-/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[11] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(11))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(11))
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 11
-/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(10))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(10))
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 10
-/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(9))
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 9
-/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(8))
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 8
-/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(7))
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 7
-/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(6))
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 6
-/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(5))
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 5
-/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(4))
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1
-#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 4
-/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(3))
-#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1
-#define LEDC_LSTIMER3_OVF_INT_CLR_S 3
-/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(2))
-#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1
-#define LEDC_LSTIMER2_OVF_INT_CLR_S 2
-/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(1))
-#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1
-#define LEDC_LSTIMER1_OVF_INT_CLR_S 1
-/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: */
-#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(0))
-#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1
-#define LEDC_LSTIMER0_OVF_INT_CLR_S 0
-
-#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x00d0)
-/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: */
-#define LEDC_CLK_EN (BIT(31))
-#define LEDC_CLK_EN_M (BIT(31))
-#define LEDC_CLK_EN_V 0x1
-#define LEDC_CLK_EN_S 31
-/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: */
-#define LEDC_APB_CLK_SEL 0x00000003
-#define LEDC_APB_CLK_SEL_M ((LEDC_APB_CLK_SEL_V) << (LEDC_APB_CLK_SEL_S))
-#define LEDC_APB_CLK_SEL_V 0x3
-#define LEDC_APB_CLK_SEL_S 0
-
-#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x00FC)
-/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19040200 ; */
-/*description: */
-#define LEDC_DATE 0xFFFFFFFF
-#define LEDC_DATE_M ((LEDC_DATE_V) << (LEDC_DATE_S))
-#define LEDC_DATE_V 0xFFFFFFFF
-#define LEDC_DATE_S 0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/mcpwm_reg.h b/components/soc/esp32s3/include/soc/mcpwm_reg.h
deleted file mode 100644
index 6a370aa6910..00000000000
--- a/components/soc/esp32s3/include/soc/mcpwm_reg.h
+++ /dev/null
@@ -1,3829 +0,0 @@
-/**
- *  SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define DR_REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000))
-
-/** MCPWM_CLK_CFG_REG register
- *  PWM clock prescaler register.
- */
-#define MCPWM_CLK_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x0)
-/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
- */
-#define MCPWM_CLK_PRESCALE    0x000000FFU
-#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
-#define MCPWM_CLK_PRESCALE_V  0x000000FFU
-#define MCPWM_CLK_PRESCALE_S  0
-
-/** MCPWM_TIMER0_CFG0_REG register
- *  PWM timer0 period and update method configuration register.
- */
-#define MCPWM_TIMER0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4)
-/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configure the divisor of PT0_clk, takes effect when PWM timer0 stops and starts
- *  agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)
- */
-#define MCPWM_TIMER0_PRESCALE    0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
-#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER0_PRESCALE_S  0
-/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer0
- */
-#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
-#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER0_PERIOD_S  8
-/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ or sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER0_CFG1_REG register
- *  PWM timer0 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8)
-/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1:
- *  if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0
- *  starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER0_START    0x00000007U
-#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
-#define MCPWM_TIMER0_START_V  0x00000007U
-#define MCPWM_TIMER0_START_S  0
-/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER0_MOD    0x00000003U
-#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
-#define MCPWM_TIMER0_MOD_V  0x00000003U
-#define MCPWM_TIMER0_MOD_S  3
-
-/** MCPWM_TIMER0_SYNC_REG register
- *  PWM timer0 sync function configuration register.
- */
-#define MCPWM_TIMER0_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc)
-/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
-#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER0_SYNCI_EN_S  0
-/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
-#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER0_SYNC_SW_S  1
-/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer0_sync_sw bit
- */
-#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
-#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER0_SYNCO_SEL_S  2
-/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER0_PHASE    0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
-#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER0_PHASE_S  4
-/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer0's direction at the time sync event occurs when timer0 mode
- *  is up-down mode: 0-increase,1-decrease
- */
-#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
-#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER0_STATUS_REG register
- *  PWM timer0 status register.
- */
-#define MCPWM_TIMER0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10)
-/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer0 counter value
- */
-#define MCPWM_TIMER0_VALUE    0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
-#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER0_VALUE_S  0
-/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer0 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER0_DIRECTION    (BIT(16))
-#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
-#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER0_DIRECTION_S  16
-
-/** MCPWM_TIMER1_CFG0_REG register
- *  PWM timer1 period and update method configuration register.
- */
-#define MCPWM_TIMER1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x14)
-/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configure the divisor of PT1_clk, takes effect when PWM timer1 stops and starts
- *  agsin. period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)
- */
-#define MCPWM_TIMER1_PRESCALE    0x000000FFU
-#define MCPWM_TIMER1_PRESCALE_M  (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S)
-#define MCPWM_TIMER1_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER1_PRESCALE_S  0
-/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer1
- */
-#define MCPWM_TIMER1_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER1_PERIOD_M  (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S)
-#define MCPWM_TIMER1_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER1_PERIOD_S  8
-/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER1_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER1_CFG1_REG register
- *  PWM timer1 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x18)
-/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1:
- *  if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1
- *  starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER1_START    0x00000007U
-#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
-#define MCPWM_TIMER1_START_V  0x00000007U
-#define MCPWM_TIMER1_START_S  0
-/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER1_MOD    0x00000003U
-#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
-#define MCPWM_TIMER1_MOD_V  0x00000003U
-#define MCPWM_TIMER1_MOD_S  3
-
-/** MCPWM_TIMER1_SYNC_REG register
- *  PWM timer1 sync function configuration register.
- */
-#define MCPWM_TIMER1_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x1c)
-/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
-#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER1_SYNCI_EN_S  0
-/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
-#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER1_SYNC_SW_S  1
-/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer1_sync_sw bit
- */
-#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
-#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER1_SYNCO_SEL_S  2
-/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER1_PHASE    0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
-#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER1_PHASE_S  4
-/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer1's direction at the time sync event occurs when timer1 mode
- *  is up-down mode: 0-increase,1-decrease
- */
-#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
-#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER1_STATUS_REG register
- *  PWM timer1 status register.
- */
-#define MCPWM_TIMER1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x20)
-/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer1 counter value
- */
-#define MCPWM_TIMER1_VALUE    0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
-#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER1_VALUE_S  0
-/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer1 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER1_DIRECTION    (BIT(16))
-#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
-#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER1_DIRECTION_S  16
-
-/** MCPWM_TIMER2_CFG0_REG register
- *  PWM timer2 period and update method configuration register.
- */
-#define MCPWM_TIMER2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x24)
-/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
- *  Configure the divisor of PT2_clk, takes effect when PWM timer2 stops and starts
- *  agsin. period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)
- */
-#define MCPWM_TIMER2_PRESCALE    0x000000FFU
-#define MCPWM_TIMER2_PRESCALE_M  (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S)
-#define MCPWM_TIMER2_PRESCALE_V  0x000000FFU
-#define MCPWM_TIMER2_PRESCALE_S  0
-/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255;
- *  period shadow register of PWM timer2
- */
-#define MCPWM_TIMER2_PERIOD    0x0000FFFFU
-#define MCPWM_TIMER2_PERIOD_M  (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S)
-#define MCPWM_TIMER2_PERIOD_V  0x0000FFFFU
-#define MCPWM_TIMER2_PERIOD_S  8
-/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
- *  Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2:
- *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
- */
-#define MCPWM_TIMER2_PERIOD_UPMETHOD    0x00000003U
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S)
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x00000003U
-#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
-
-/** MCPWM_TIMER2_CFG1_REG register
- *  PWM timer2 working mode and start/stop control configuration register.
- */
-#define MCPWM_TIMER2_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x28)
-/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
- *  PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1:
- *  if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2
- *  starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP
- *  here and below means the event that happens when the timer equals to period
- */
-#define MCPWM_TIMER2_START    0x00000007U
-#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
-#define MCPWM_TIMER2_START_V  0x00000007U
-#define MCPWM_TIMER2_START_S  0
-/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
- *  PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
- *  mode
- */
-#define MCPWM_TIMER2_MOD    0x00000003U
-#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
-#define MCPWM_TIMER2_MOD_V  0x00000003U
-#define MCPWM_TIMER2_MOD_S  3
-
-/** MCPWM_TIMER2_SYNC_REG register
- *  PWM timer2 sync function configuration register.
- */
-#define MCPWM_TIMER2_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x2c)
-/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
- *  When set, timer reloading with phase on sync input event is enabled.
- */
-#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
-#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
-#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
-#define MCPWM_TIMER2_SYNCI_EN_S  0
-/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
- *  Toggling this bit will trigger a software sync.
- */
-#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
-#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
-#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
-#define MCPWM_TIMER2_SYNC_SW_S  1
-/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
- *  PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
- *  generate when toggling the reg_timer0_sync_sw bit
- */
-#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
-#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
-#define MCPWM_TIMER2_SYNCO_SEL_S  2
-/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
- *  phase for timer reload on sync event
- */
-#define MCPWM_TIMER2_PHASE    0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
-#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
-#define MCPWM_TIMER2_PHASE_S  4
-/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
- *  Configure the PWM timer2's direction at the time sync event occurs when timer2 mode
- *  is up-down mode: 0-increase,1-decrease
- */
-#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
-#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
-#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
-
-/** MCPWM_TIMER2_STATUS_REG register
- *  PWM timer2 status register.
- */
-#define MCPWM_TIMER2_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x30)
-/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
- *  current PWM timer2 counter value
- */
-#define MCPWM_TIMER2_VALUE    0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
-#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
-#define MCPWM_TIMER2_VALUE_S  0
-/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
- *  current PWM timer2 counter direction, 0: increment 1: decrement
- */
-#define MCPWM_TIMER2_DIRECTION    (BIT(16))
-#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
-#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
-#define MCPWM_TIMER2_DIRECTION_S  16
-
-/** MCPWM_TIMER_SYNCI_CFG_REG register
- *  Synchronization input selection for three PWM timers.
- */
-#define MCPWM_TIMER_SYNCI_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x34)
-/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
- *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER0_SYNCISEL    0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
-#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER0_SYNCISEL_S  0
-/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
- *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER1_SYNCISEL    0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
-#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER1_SYNCISEL_S  3
-/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
- *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
- *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
- *  SYNC2 from GPIO matrix, other values: no sync input selected
- */
-#define MCPWM_TIMER2_SYNCISEL    0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
-#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
-#define MCPWM_TIMER2_SYNCISEL_S  6
-/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
- *  invert SYNC0 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
-/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
- *  invert SYNC1 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
-/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
- *  invert SYNC2 from GPIO matrix
- */
-#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
-#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
-
-/** MCPWM_OPERATOR_TIMERSEL_REG register
- *  Select specific timer for PWM operators.
- */
-#define MCPWM_OPERATOR_TIMERSEL_REG(i) (DR_REG_MCPWM_BASE(i) + 0x38)
-/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
- *  Select which PWM timer is the timing reference for PWM operator0, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
-#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR0_TIMERSEL_S  0
-/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
- *  Select which PWM timer is the timing reference for PWM operator1, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
-#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR1_TIMERSEL_S  2
-/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
- *  Select which PWM timer is the timing reference for PWM operator2, 0: timer0, 1:
- *  timer1, 2: timer2
- */
-#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
-#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
-#define MCPWM_OPERATOR2_TIMERSEL_S  4
-
-/** MCPWM_GEN0_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN0_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x3c)
-/** MCPWM_GEN0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 0 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_GEN0_A_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_A_UPMETHOD_M  (MCPWM_GEN0_A_UPMETHOD_V << MCPWM_GEN0_A_UPMETHOD_S)
-#define MCPWM_GEN0_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_A_UPMETHOD_S  0
-/** MCPWM_GEN0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 0 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_GEN0_B_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_B_UPMETHOD_M  (MCPWM_GEN0_B_UPMETHOD_V << MCPWM_GEN0_B_UPMETHOD_S)
-#define MCPWM_GEN0_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_B_UPMETHOD_S  4
-/** MCPWM_GEN0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_GEN0_A_SHDW_FULL    (BIT(8))
-#define MCPWM_GEN0_A_SHDW_FULL_M  (MCPWM_GEN0_A_SHDW_FULL_V << MCPWM_GEN0_A_SHDW_FULL_S)
-#define MCPWM_GEN0_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN0_A_SHDW_FULL_S  8
-/** MCPWM_GEN0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_GEN0_B_SHDW_FULL    (BIT(9))
-#define MCPWM_GEN0_B_SHDW_FULL_M  (MCPWM_GEN0_B_SHDW_FULL_V << MCPWM_GEN0_B_SHDW_FULL_S)
-#define MCPWM_GEN0_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN0_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN0_TSTMP_A_REG register
- *  PWM generator 0 shadow register for timer stamp A.
- */
-#define MCPWM_GEN0_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x40)
-/** MCPWM_GEN0_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 0 time stamp A's shadow register
- */
-#define MCPWM_GEN0_A    0x0000FFFFU
-#define MCPWM_GEN0_A_M  (MCPWM_GEN0_A_V << MCPWM_GEN0_A_S)
-#define MCPWM_GEN0_A_V  0x0000FFFFU
-#define MCPWM_GEN0_A_S  0
-
-/** MCPWM_GEN0_TSTMP_B_REG register
- *  PWM generator 0 shadow register for timer stamp B.
- */
-#define MCPWM_GEN0_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x44)
-/** MCPWM_GEN0_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 0 time stamp B's shadow register
- */
-#define MCPWM_GEN0_B    0x0000FFFFU
-#define MCPWM_GEN0_B_M  (MCPWM_GEN0_B_V << MCPWM_GEN0_B_S)
-#define MCPWM_GEN0_B_V  0x0000FFFFU
-#define MCPWM_GEN0_B_S  0
-
-/** MCPWM_GEN0_CFG0_REG register
- *  PWM generator 0  event T0 and T1 handling
- */
-#define MCPWM_GEN0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x48)
-/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 0's active register of configuration. When all bits
- *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
- *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
- */
-#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
-#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN0_CFG_UPMETHOD_S  0
-/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 0 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN0_T0_SEL    0x00000007U
-#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
-#define MCPWM_GEN0_T0_SEL_V  0x00000007U
-#define MCPWM_GEN0_T0_SEL_S  4
-/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 0 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN0_T1_SEL    0x00000007U
-#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
-#define MCPWM_GEN0_T1_SEL_V  0x00000007U
-#define MCPWM_GEN0_T1_SEL_S  7
-
-/** MCPWM_GEN0_FORCE_REG register
- *  Permissives to force PWM0A and PWM0B outputs by software
- */
-#define MCPWM_GEN0_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4c)
-/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator0. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM0A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
-#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_A_NCIFORCE_S  10
-/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM0B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
-#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN0_B_NCIFORCE_S  13
-/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN0_A_REG register
- *  Actions triggered by events on PWM0A
- */
-#define MCPWM_GEN0_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x50)
-/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM0A triggered by event TEZ when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_UTEZ    0x00000003U
-#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
-#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_UTEZ_S  0
-/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM0A triggered by event TEP when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_UTEP    0x00000003U
-#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
-#define MCPWM_GEN0_A_UTEP_V  0x00000003U
-#define MCPWM_GEN0_A_UTEP_S  2
-/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM0A triggered by event TEA when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_UTEA    0x00000003U
-#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
-#define MCPWM_GEN0_A_UTEA_V  0x00000003U
-#define MCPWM_GEN0_A_UTEA_S  4
-/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM0A triggered by event TEB when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_UTEB    0x00000003U
-#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
-#define MCPWM_GEN0_A_UTEB_V  0x00000003U
-#define MCPWM_GEN0_A_UTEB_S  6
-/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM0A triggered by event_t0 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_UT0    0x00000003U
-#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
-#define MCPWM_GEN0_A_UT0_V  0x00000003U
-#define MCPWM_GEN0_A_UT0_S  8
-/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM0A triggered by event_t1 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_UT1    0x00000003U
-#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
-#define MCPWM_GEN0_A_UT1_V  0x00000003U
-#define MCPWM_GEN0_A_UT1_S  10
-/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM0A triggered by event TEZ when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_DTEZ    0x00000003U
-#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
-#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_A_DTEZ_S  12
-/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM0A triggered by event TEP when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_DTEP    0x00000003U
-#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
-#define MCPWM_GEN0_A_DTEP_V  0x00000003U
-#define MCPWM_GEN0_A_DTEP_S  14
-/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM0A triggered by event TEA when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_DTEA    0x00000003U
-#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
-#define MCPWM_GEN0_A_DTEA_V  0x00000003U
-#define MCPWM_GEN0_A_DTEA_S  16
-/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM0A triggered by event TEB when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_DTEB    0x00000003U
-#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
-#define MCPWM_GEN0_A_DTEB_V  0x00000003U
-#define MCPWM_GEN0_A_DTEB_S  18
-/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM0A triggered by event_t0 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_DT0    0x00000003U
-#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
-#define MCPWM_GEN0_A_DT0_V  0x00000003U
-#define MCPWM_GEN0_A_DT0_S  20
-/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_A_DT1    0x00000003U
-#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
-#define MCPWM_GEN0_A_DT1_V  0x00000003U
-#define MCPWM_GEN0_A_DT1_S  22
-
-/** MCPWM_GEN0_B_REG register
- *  Actions triggered by events on PWM0B
- */
-#define MCPWM_GEN0_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x54)
-/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM0B triggered by event TEZ when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_UTEZ    0x00000003U
-#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
-#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_UTEZ_S  0
-/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM0B triggered by event TEP when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_UTEP    0x00000003U
-#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
-#define MCPWM_GEN0_B_UTEP_V  0x00000003U
-#define MCPWM_GEN0_B_UTEP_S  2
-/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM0B triggered by event TEA when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_UTEA    0x00000003U
-#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
-#define MCPWM_GEN0_B_UTEA_V  0x00000003U
-#define MCPWM_GEN0_B_UTEA_S  4
-/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM0B triggered by event TEB when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_UTEB    0x00000003U
-#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
-#define MCPWM_GEN0_B_UTEB_V  0x00000003U
-#define MCPWM_GEN0_B_UTEB_S  6
-/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM0B triggered by event_t0 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_UT0    0x00000003U
-#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
-#define MCPWM_GEN0_B_UT0_V  0x00000003U
-#define MCPWM_GEN0_B_UT0_S  8
-/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM0B triggered by event_t1 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_UT1    0x00000003U
-#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
-#define MCPWM_GEN0_B_UT1_V  0x00000003U
-#define MCPWM_GEN0_B_UT1_S  10
-/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM0B triggered by event TEZ when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_DTEZ    0x00000003U
-#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
-#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN0_B_DTEZ_S  12
-/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM0B triggered by event TEP when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_DTEP    0x00000003U
-#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
-#define MCPWM_GEN0_B_DTEP_V  0x00000003U
-#define MCPWM_GEN0_B_DTEP_S  14
-/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM0B triggered by event TEA when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_DTEA    0x00000003U
-#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
-#define MCPWM_GEN0_B_DTEA_V  0x00000003U
-#define MCPWM_GEN0_B_DTEA_S  16
-/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM0B triggered by event TEB when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_DTEB    0x00000003U
-#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
-#define MCPWM_GEN0_B_DTEB_V  0x00000003U
-#define MCPWM_GEN0_B_DTEB_S  18
-/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM0B triggered by event_t0 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_DT0    0x00000003U
-#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
-#define MCPWM_GEN0_B_DT0_V  0x00000003U
-#define MCPWM_GEN0_B_DT0_S  20
-/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN0_B_DT1    0x00000003U
-#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
-#define MCPWM_GEN0_B_DT1_V  0x00000003U
-#define MCPWM_GEN0_B_DT1_S  22
-
-/** MCPWM_DT0_CFG_REG register
- *  PWM generator 0 dead time type selection and configuration
- */
-#define MCPWM_DT0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x58)
-/** MCPWM_DT0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DT0_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DT0_FED_UPMETHOD_M  (MCPWM_DT0_FED_UPMETHOD_V << MCPWM_DT0_FED_UPMETHOD_S)
-#define MCPWM_DT0_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT0_FED_UPMETHOD_S  0
-/** MCPWM_DT0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DT0_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DT0_RED_UPMETHOD_M  (MCPWM_DT0_RED_UPMETHOD_V << MCPWM_DT0_RED_UPMETHOD_S)
-#define MCPWM_DT0_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT0_RED_UPMETHOD_S  4
-/** MCPWM_DT0_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DT0_DEB_MODE    (BIT(8))
-#define MCPWM_DT0_DEB_MODE_M  (MCPWM_DT0_DEB_MODE_V << MCPWM_DT0_DEB_MODE_S)
-#define MCPWM_DT0_DEB_MODE_V  0x00000001U
-#define MCPWM_DT0_DEB_MODE_S  8
-/** MCPWM_DT0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DT0_A_OUTSWAP    (BIT(9))
-#define MCPWM_DT0_A_OUTSWAP_M  (MCPWM_DT0_A_OUTSWAP_V << MCPWM_DT0_A_OUTSWAP_S)
-#define MCPWM_DT0_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DT0_A_OUTSWAP_S  9
-/** MCPWM_DT0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DT0_B_OUTSWAP    (BIT(10))
-#define MCPWM_DT0_B_OUTSWAP_M  (MCPWM_DT0_B_OUTSWAP_V << MCPWM_DT0_B_OUTSWAP_S)
-#define MCPWM_DT0_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DT0_B_OUTSWAP_S  10
-/** MCPWM_DT0_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DT0_RED_INSEL    (BIT(11))
-#define MCPWM_DT0_RED_INSEL_M  (MCPWM_DT0_RED_INSEL_V << MCPWM_DT0_RED_INSEL_S)
-#define MCPWM_DT0_RED_INSEL_V  0x00000001U
-#define MCPWM_DT0_RED_INSEL_S  11
-/** MCPWM_DT0_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DT0_FED_INSEL    (BIT(12))
-#define MCPWM_DT0_FED_INSEL_M  (MCPWM_DT0_FED_INSEL_V << MCPWM_DT0_FED_INSEL_S)
-#define MCPWM_DT0_FED_INSEL_V  0x00000001U
-#define MCPWM_DT0_FED_INSEL_S  12
-/** MCPWM_DT0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DT0_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DT0_RED_OUTINVERT_M  (MCPWM_DT0_RED_OUTINVERT_V << MCPWM_DT0_RED_OUTINVERT_S)
-#define MCPWM_DT0_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT0_RED_OUTINVERT_S  13
-/** MCPWM_DT0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DT0_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DT0_FED_OUTINVERT_M  (MCPWM_DT0_FED_OUTINVERT_V << MCPWM_DT0_FED_OUTINVERT_S)
-#define MCPWM_DT0_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT0_FED_OUTINVERT_S  14
-/** MCPWM_DT0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DT0_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DT0_A_OUTBYPASS_M  (MCPWM_DT0_A_OUTBYPASS_V << MCPWM_DT0_A_OUTBYPASS_S)
-#define MCPWM_DT0_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT0_A_OUTBYPASS_S  15
-/** MCPWM_DT0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DT0_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DT0_B_OUTBYPASS_M  (MCPWM_DT0_B_OUTBYPASS_V << MCPWM_DT0_B_OUTBYPASS_S)
-#define MCPWM_DT0_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT0_B_OUTBYPASS_S  16
-/** MCPWM_DT0_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DT0_CLK_SEL    (BIT(17))
-#define MCPWM_DT0_CLK_SEL_M  (MCPWM_DT0_CLK_SEL_V << MCPWM_DT0_CLK_SEL_S)
-#define MCPWM_DT0_CLK_SEL_V  0x00000001U
-#define MCPWM_DT0_CLK_SEL_S  17
-
-/** MCPWM_DT0_FED_CFG_REG register
- *  PWM generator 0 shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT0_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x5c)
-/** MCPWM_DT0_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DT0_FED    0x0000FFFFU
-#define MCPWM_DT0_FED_M  (MCPWM_DT0_FED_V << MCPWM_DT0_FED_S)
-#define MCPWM_DT0_FED_V  0x0000FFFFU
-#define MCPWM_DT0_FED_S  0
-
-/** MCPWM_DT0_RED_CFG_REG register
- *  PWM generator 0 shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT0_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x60)
-/** MCPWM_DT0_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DT0_RED    0x0000FFFFU
-#define MCPWM_DT0_RED_M  (MCPWM_DT0_RED_V << MCPWM_DT0_RED_S)
-#define MCPWM_DT0_RED_V  0x0000FFFFU
-#define MCPWM_DT0_RED_S  0
-
-/** MCPWM_CARRIER0_CFG_REG register
- *  PWM generator 0 carrier enable and configuratoin
- */
-#define MCPWM_CARRIER0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x64)
-/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
- */
-#define MCPWM_CARRIER0_EN    (BIT(0))
-#define MCPWM_CARRIER0_EN_M  (MCPWM_CARRIER0_EN_V << MCPWM_CARRIER0_EN_S)
-#define MCPWM_CARRIER0_EN_V  0x00000001U
-#define MCPWM_CARRIER0_EN_S  0
-/** MCPWM_CARRIER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CARRIER0_PRESCALE    0x0000000FU
-#define MCPWM_CARRIER0_PRESCALE_M  (MCPWM_CARRIER0_PRESCALE_V << MCPWM_CARRIER0_PRESCALE_S)
-#define MCPWM_CARRIER0_PRESCALE_V  0x0000000FU
-#define MCPWM_CARRIER0_PRESCALE_S  1
-/** MCPWM_CARRIER0_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CARRIER0_DUTY    0x00000007U
-#define MCPWM_CARRIER0_DUTY_M  (MCPWM_CARRIER0_DUTY_V << MCPWM_CARRIER0_DUTY_S)
-#define MCPWM_CARRIER0_DUTY_V  0x00000007U
-#define MCPWM_CARRIER0_DUTY_S  5
-/** MCPWM_CARRIER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CARRIER0_OSHTWTH    0x0000000FU
-#define MCPWM_CARRIER0_OSHTWTH_M  (MCPWM_CARRIER0_OSHTWTH_V << MCPWM_CARRIER0_OSHTWTH_S)
-#define MCPWM_CARRIER0_OSHTWTH_V  0x0000000FU
-#define MCPWM_CARRIER0_OSHTWTH_S  8
-/** MCPWM_CARRIER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM0A and PWM0B for this submodule
- */
-#define MCPWM_CARRIER0_OUT_INVERT    (BIT(12))
-#define MCPWM_CARRIER0_OUT_INVERT_M  (MCPWM_CARRIER0_OUT_INVERT_V << MCPWM_CARRIER0_OUT_INVERT_S)
-#define MCPWM_CARRIER0_OUT_INVERT_V  0x00000001U
-#define MCPWM_CARRIER0_OUT_INVERT_S  12
-/** MCPWM_CARRIER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM0A and PWM0B for this submodule
- */
-#define MCPWM_CARRIER0_IN_INVERT    (BIT(13))
-#define MCPWM_CARRIER0_IN_INVERT_M  (MCPWM_CARRIER0_IN_INVERT_V << MCPWM_CARRIER0_IN_INVERT_S)
-#define MCPWM_CARRIER0_IN_INVERT_V  0x00000001U
-#define MCPWM_CARRIER0_IN_INVERT_S  13
-
-/** MCPWM_FH0_CFG0_REG register
- *  Actions on PWM0A and PWM0B trip events
- */
-#define MCPWM_FH0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x68)
-/** MCPWM_FH0_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH0_SW_CBC    (BIT(0))
-#define MCPWM_FH0_SW_CBC_M  (MCPWM_FH0_SW_CBC_V << MCPWM_FH0_SW_CBC_S)
-#define MCPWM_FH0_SW_CBC_V  0x00000001U
-#define MCPWM_FH0_SW_CBC_S  0
-/** MCPWM_FH0_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH0_F2_CBC    (BIT(1))
-#define MCPWM_FH0_F2_CBC_M  (MCPWM_FH0_F2_CBC_V << MCPWM_FH0_F2_CBC_S)
-#define MCPWM_FH0_F2_CBC_V  0x00000001U
-#define MCPWM_FH0_F2_CBC_S  1
-/** MCPWM_FH0_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH0_F1_CBC    (BIT(2))
-#define MCPWM_FH0_F1_CBC_M  (MCPWM_FH0_F1_CBC_V << MCPWM_FH0_F1_CBC_S)
-#define MCPWM_FH0_F1_CBC_V  0x00000001U
-#define MCPWM_FH0_F1_CBC_S  2
-/** MCPWM_FH0_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH0_F0_CBC    (BIT(3))
-#define MCPWM_FH0_F0_CBC_M  (MCPWM_FH0_F0_CBC_V << MCPWM_FH0_F0_CBC_S)
-#define MCPWM_FH0_F0_CBC_V  0x00000001U
-#define MCPWM_FH0_F0_CBC_S  3
-/** MCPWM_FH0_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH0_SW_OST    (BIT(4))
-#define MCPWM_FH0_SW_OST_M  (MCPWM_FH0_SW_OST_V << MCPWM_FH0_SW_OST_S)
-#define MCPWM_FH0_SW_OST_V  0x00000001U
-#define MCPWM_FH0_SW_OST_S  4
-/** MCPWM_FH0_F2_OST : R/W; bitpos: [5]; default: 0;
- *  fault_event2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH0_F2_OST    (BIT(5))
-#define MCPWM_FH0_F2_OST_M  (MCPWM_FH0_F2_OST_V << MCPWM_FH0_F2_OST_S)
-#define MCPWM_FH0_F2_OST_V  0x00000001U
-#define MCPWM_FH0_F2_OST_S  5
-/** MCPWM_FH0_F1_OST : R/W; bitpos: [6]; default: 0;
- *  fault_event1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH0_F1_OST    (BIT(6))
-#define MCPWM_FH0_F1_OST_M  (MCPWM_FH0_F1_OST_V << MCPWM_FH0_F1_OST_S)
-#define MCPWM_FH0_F1_OST_V  0x00000001U
-#define MCPWM_FH0_F1_OST_S  6
-/** MCPWM_FH0_F0_OST : R/W; bitpos: [7]; default: 0;
- *  fault_event0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH0_F0_OST    (BIT(7))
-#define MCPWM_FH0_F0_OST_M  (MCPWM_FH0_F0_OST_V << MCPWM_FH0_F0_OST_S)
-#define MCPWM_FH0_F0_OST_V  0x00000001U
-#define MCPWM_FH0_F0_OST_S  7
-/** MCPWM_FH0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH0_A_CBC_D    0x00000003U
-#define MCPWM_FH0_A_CBC_D_M  (MCPWM_FH0_A_CBC_D_V << MCPWM_FH0_A_CBC_D_S)
-#define MCPWM_FH0_A_CBC_D_V  0x00000003U
-#define MCPWM_FH0_A_CBC_D_S  8
-/** MCPWM_FH0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH0_A_CBC_U    0x00000003U
-#define MCPWM_FH0_A_CBC_U_M  (MCPWM_FH0_A_CBC_U_V << MCPWM_FH0_A_CBC_U_S)
-#define MCPWM_FH0_A_CBC_U_V  0x00000003U
-#define MCPWM_FH0_A_CBC_U_S  10
-/** MCPWM_FH0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH0_A_OST_D    0x00000003U
-#define MCPWM_FH0_A_OST_D_M  (MCPWM_FH0_A_OST_D_V << MCPWM_FH0_A_OST_D_S)
-#define MCPWM_FH0_A_OST_D_V  0x00000003U
-#define MCPWM_FH0_A_OST_D_S  12
-/** MCPWM_FH0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH0_A_OST_U    0x00000003U
-#define MCPWM_FH0_A_OST_U_M  (MCPWM_FH0_A_OST_U_V << MCPWM_FH0_A_OST_U_S)
-#define MCPWM_FH0_A_OST_U_V  0x00000003U
-#define MCPWM_FH0_A_OST_U_S  14
-/** MCPWM_FH0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH0_B_CBC_D    0x00000003U
-#define MCPWM_FH0_B_CBC_D_M  (MCPWM_FH0_B_CBC_D_V << MCPWM_FH0_B_CBC_D_S)
-#define MCPWM_FH0_B_CBC_D_V  0x00000003U
-#define MCPWM_FH0_B_CBC_D_S  16
-/** MCPWM_FH0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
- *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH0_B_CBC_U    0x00000003U
-#define MCPWM_FH0_B_CBC_U_M  (MCPWM_FH0_B_CBC_U_V << MCPWM_FH0_B_CBC_U_S)
-#define MCPWM_FH0_B_CBC_U_V  0x00000003U
-#define MCPWM_FH0_B_CBC_U_S  18
-/** MCPWM_FH0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH0_B_OST_D    0x00000003U
-#define MCPWM_FH0_B_OST_D_M  (MCPWM_FH0_B_OST_D_V << MCPWM_FH0_B_OST_D_S)
-#define MCPWM_FH0_B_OST_D_V  0x00000003U
-#define MCPWM_FH0_B_OST_D_S  20
-/** MCPWM_FH0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH0_B_OST_U    0x00000003U
-#define MCPWM_FH0_B_OST_U_M  (MCPWM_FH0_B_OST_U_V << MCPWM_FH0_B_OST_U_S)
-#define MCPWM_FH0_B_OST_U_V  0x00000003U
-#define MCPWM_FH0_B_OST_U_S  22
-
-/** MCPWM_FH0_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x6c)
-/** MCPWM_FH0_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_FH0_CLR_OST    (BIT(0))
-#define MCPWM_FH0_CLR_OST_M  (MCPWM_FH0_CLR_OST_V << MCPWM_FH0_CLR_OST_S)
-#define MCPWM_FH0_CLR_OST_V  0x00000001U
-#define MCPWM_FH0_CLR_OST_S  0
-/** MCPWM_FH0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when
- *  bit0 and bit1 both set to 1: refresh at TEP/TEZ
- */
-#define MCPWM_FH0_CBCPULSE    0x00000003U
-#define MCPWM_FH0_CBCPULSE_M  (MCPWM_FH0_CBCPULSE_V << MCPWM_FH0_CBCPULSE_S)
-#define MCPWM_FH0_CBCPULSE_V  0x00000003U
-#define MCPWM_FH0_CBCPULSE_S  1
-/** MCPWM_FH0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_FH0_FORCE_CBC    (BIT(3))
-#define MCPWM_FH0_FORCE_CBC_M  (MCPWM_FH0_FORCE_CBC_V << MCPWM_FH0_FORCE_CBC_S)
-#define MCPWM_FH0_FORCE_CBC_V  0x00000001U
-#define MCPWM_FH0_FORCE_CBC_S  3
-/** MCPWM_FH0_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_FH0_FORCE_OST    (BIT(4))
-#define MCPWM_FH0_FORCE_OST_M  (MCPWM_FH0_FORCE_OST_V << MCPWM_FH0_FORCE_OST_S)
-#define MCPWM_FH0_FORCE_OST_V  0x00000001U
-#define MCPWM_FH0_FORCE_OST_S  4
-
-/** MCPWM_FH0_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x70)
-/** MCPWM_FH0_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_FH0_CBC_ON    (BIT(0))
-#define MCPWM_FH0_CBC_ON_M  (MCPWM_FH0_CBC_ON_V << MCPWM_FH0_CBC_ON_S)
-#define MCPWM_FH0_CBC_ON_V  0x00000001U
-#define MCPWM_FH0_CBC_ON_S  0
-/** MCPWM_FH0_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_FH0_OST_ON    (BIT(1))
-#define MCPWM_FH0_OST_ON_M  (MCPWM_FH0_OST_ON_V << MCPWM_FH0_OST_ON_S)
-#define MCPWM_FH0_OST_ON_V  0x00000001U
-#define MCPWM_FH0_OST_ON_S  1
-
-/** MCPWM_GEN1_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN1_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x74)
-/** MCPWM_GEN1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 1 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_GEN1_A_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_A_UPMETHOD_M  (MCPWM_GEN1_A_UPMETHOD_V << MCPWM_GEN1_A_UPMETHOD_S)
-#define MCPWM_GEN1_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_A_UPMETHOD_S  0
-/** MCPWM_GEN1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 1 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_GEN1_B_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_B_UPMETHOD_M  (MCPWM_GEN1_B_UPMETHOD_V << MCPWM_GEN1_B_UPMETHOD_S)
-#define MCPWM_GEN1_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_B_UPMETHOD_S  4
-/** MCPWM_GEN1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_GEN1_A_SHDW_FULL    (BIT(8))
-#define MCPWM_GEN1_A_SHDW_FULL_M  (MCPWM_GEN1_A_SHDW_FULL_V << MCPWM_GEN1_A_SHDW_FULL_S)
-#define MCPWM_GEN1_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN1_A_SHDW_FULL_S  8
-/** MCPWM_GEN1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_GEN1_B_SHDW_FULL    (BIT(9))
-#define MCPWM_GEN1_B_SHDW_FULL_M  (MCPWM_GEN1_B_SHDW_FULL_V << MCPWM_GEN1_B_SHDW_FULL_S)
-#define MCPWM_GEN1_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN1_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN1_TSTMP_A_REG register
- *  PWM generator 1 shadow register for timer stamp A.
- */
-#define MCPWM_GEN1_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x78)
-/** MCPWM_GEN1_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 1 time stamp A's shadow register
- */
-#define MCPWM_GEN1_A    0x0000FFFFU
-#define MCPWM_GEN1_A_M  (MCPWM_GEN1_A_V << MCPWM_GEN1_A_S)
-#define MCPWM_GEN1_A_V  0x0000FFFFU
-#define MCPWM_GEN1_A_S  0
-
-/** MCPWM_GEN1_TSTMP_B_REG register
- *  PWM generator 1 shadow register for timer stamp B.
- */
-#define MCPWM_GEN1_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x7c)
-/** MCPWM_GEN1_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 1 time stamp B's shadow register
- */
-#define MCPWM_GEN1_B    0x0000FFFFU
-#define MCPWM_GEN1_B_M  (MCPWM_GEN1_B_V << MCPWM_GEN1_B_S)
-#define MCPWM_GEN1_B_V  0x0000FFFFU
-#define MCPWM_GEN1_B_S  0
-
-/** MCPWM_GEN1_CFG0_REG register
- *  PWM generator 1 event T0 and T1 handling
- */
-#define MCPWM_GEN1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x80)
-/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 1's active register of configuration. When all bits
- *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
- *  1:sync;when bit3 is set to 1:disable the update.
- */
-#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
-#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN1_CFG_UPMETHOD_S  0
-/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 1 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN1_T0_SEL    0x00000007U
-#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
-#define MCPWM_GEN1_T0_SEL_V  0x00000007U
-#define MCPWM_GEN1_T0_SEL_S  4
-/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 1 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN1_T1_SEL    0x00000007U
-#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
-#define MCPWM_GEN1_T1_SEL_V  0x00000007U
-#define MCPWM_GEN1_T1_SEL_S  7
-
-/** MCPWM_GEN1_FORCE_REG register
- *  Permissives to force PWM1A and PWM1B outputs by software
- */
-#define MCPWM_GEN1_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0x84)
-/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator 1. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM1A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
-#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_A_NCIFORCE_S  10
-/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM1B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
-#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN1_B_NCIFORCE_S  13
-/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN1_A_REG register
- *  Actions triggered by events on PWM1A
- */
-#define MCPWM_GEN1_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x88)
-/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM1A triggered by event TEZ when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_UTEZ    0x00000003U
-#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
-#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_UTEZ_S  0
-/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM1A triggered by event TEP when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_UTEP    0x00000003U
-#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
-#define MCPWM_GEN1_A_UTEP_V  0x00000003U
-#define MCPWM_GEN1_A_UTEP_S  2
-/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM1A triggered by event TEA when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_UTEA    0x00000003U
-#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
-#define MCPWM_GEN1_A_UTEA_V  0x00000003U
-#define MCPWM_GEN1_A_UTEA_S  4
-/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM1A triggered by event TEB when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_UTEB    0x00000003U
-#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
-#define MCPWM_GEN1_A_UTEB_V  0x00000003U
-#define MCPWM_GEN1_A_UTEB_S  6
-/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM1A triggered by event_t0 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_UT0    0x00000003U
-#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
-#define MCPWM_GEN1_A_UT0_V  0x00000003U
-#define MCPWM_GEN1_A_UT0_S  8
-/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM1A triggered by event_t1 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_UT1    0x00000003U
-#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
-#define MCPWM_GEN1_A_UT1_V  0x00000003U
-#define MCPWM_GEN1_A_UT1_S  10
-/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM1A triggered by event TEZ when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_DTEZ    0x00000003U
-#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
-#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_A_DTEZ_S  12
-/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM1A triggered by event TEP when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_DTEP    0x00000003U
-#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
-#define MCPWM_GEN1_A_DTEP_V  0x00000003U
-#define MCPWM_GEN1_A_DTEP_S  14
-/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM1A triggered by event TEA when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_DTEA    0x00000003U
-#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
-#define MCPWM_GEN1_A_DTEA_V  0x00000003U
-#define MCPWM_GEN1_A_DTEA_S  16
-/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM1A triggered by event TEB when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_DTEB    0x00000003U
-#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
-#define MCPWM_GEN1_A_DTEB_V  0x00000003U
-#define MCPWM_GEN1_A_DTEB_S  18
-/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM1A triggered by event_t0 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_DT0    0x00000003U
-#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
-#define MCPWM_GEN1_A_DT0_V  0x00000003U
-#define MCPWM_GEN1_A_DT0_S  20
-/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_A_DT1    0x00000003U
-#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
-#define MCPWM_GEN1_A_DT1_V  0x00000003U
-#define MCPWM_GEN1_A_DT1_S  22
-
-/** MCPWM_GEN1_B_REG register
- *  Actions triggered by events on PWM1B
- */
-#define MCPWM_GEN1_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8c)
-/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM1B triggered by event TEZ when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_UTEZ    0x00000003U
-#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
-#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_UTEZ_S  0
-/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM1B triggered by event TEP when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_UTEP    0x00000003U
-#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
-#define MCPWM_GEN1_B_UTEP_V  0x00000003U
-#define MCPWM_GEN1_B_UTEP_S  2
-/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM1B triggered by event TEA when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_UTEA    0x00000003U
-#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
-#define MCPWM_GEN1_B_UTEA_V  0x00000003U
-#define MCPWM_GEN1_B_UTEA_S  4
-/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM1B triggered by event TEB when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_UTEB    0x00000003U
-#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
-#define MCPWM_GEN1_B_UTEB_V  0x00000003U
-#define MCPWM_GEN1_B_UTEB_S  6
-/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM1B triggered by event_t0 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_UT0    0x00000003U
-#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
-#define MCPWM_GEN1_B_UT0_V  0x00000003U
-#define MCPWM_GEN1_B_UT0_S  8
-/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM1B triggered by event_t1 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_UT1    0x00000003U
-#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
-#define MCPWM_GEN1_B_UT1_V  0x00000003U
-#define MCPWM_GEN1_B_UT1_S  10
-/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM1B triggered by event TEZ when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_DTEZ    0x00000003U
-#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
-#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN1_B_DTEZ_S  12
-/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM1B triggered by event TEP when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_DTEP    0x00000003U
-#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
-#define MCPWM_GEN1_B_DTEP_V  0x00000003U
-#define MCPWM_GEN1_B_DTEP_S  14
-/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM1B triggered by event TEA when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_DTEA    0x00000003U
-#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
-#define MCPWM_GEN1_B_DTEA_V  0x00000003U
-#define MCPWM_GEN1_B_DTEA_S  16
-/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM1B triggered by event TEB when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_DTEB    0x00000003U
-#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
-#define MCPWM_GEN1_B_DTEB_V  0x00000003U
-#define MCPWM_GEN1_B_DTEB_S  18
-/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM1B triggered by event_t0 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_DT0    0x00000003U
-#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
-#define MCPWM_GEN1_B_DT0_V  0x00000003U
-#define MCPWM_GEN1_B_DT0_S  20
-/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN1_B_DT1    0x00000003U
-#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
-#define MCPWM_GEN1_B_DT1_V  0x00000003U
-#define MCPWM_GEN1_B_DT1_S  22
-
-/** MCPWM_DT1_CFG_REG register
- *  PWM generator 1 dead time type selection and configuration
- */
-#define MCPWM_DT1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x90)
-/** MCPWM_DT1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (falling edge delay) active register. 0: immediate, when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DT1_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DT1_FED_UPMETHOD_M  (MCPWM_DT1_FED_UPMETHOD_V << MCPWM_DT1_FED_UPMETHOD_S)
-#define MCPWM_DT1_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT1_FED_UPMETHOD_S  0
-/** MCPWM_DT1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register. 0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DT1_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DT1_RED_UPMETHOD_M  (MCPWM_DT1_RED_UPMETHOD_V << MCPWM_DT1_RED_UPMETHOD_S)
-#define MCPWM_DT1_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT1_RED_UPMETHOD_S  4
-/** MCPWM_DT1_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DT1_DEB_MODE    (BIT(8))
-#define MCPWM_DT1_DEB_MODE_M  (MCPWM_DT1_DEB_MODE_V << MCPWM_DT1_DEB_MODE_S)
-#define MCPWM_DT1_DEB_MODE_V  0x00000001U
-#define MCPWM_DT1_DEB_MODE_S  8
-/** MCPWM_DT1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DT1_A_OUTSWAP    (BIT(9))
-#define MCPWM_DT1_A_OUTSWAP_M  (MCPWM_DT1_A_OUTSWAP_V << MCPWM_DT1_A_OUTSWAP_S)
-#define MCPWM_DT1_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DT1_A_OUTSWAP_S  9
-/** MCPWM_DT1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DT1_B_OUTSWAP    (BIT(10))
-#define MCPWM_DT1_B_OUTSWAP_M  (MCPWM_DT1_B_OUTSWAP_V << MCPWM_DT1_B_OUTSWAP_S)
-#define MCPWM_DT1_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DT1_B_OUTSWAP_S  10
-/** MCPWM_DT1_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DT1_RED_INSEL    (BIT(11))
-#define MCPWM_DT1_RED_INSEL_M  (MCPWM_DT1_RED_INSEL_V << MCPWM_DT1_RED_INSEL_S)
-#define MCPWM_DT1_RED_INSEL_V  0x00000001U
-#define MCPWM_DT1_RED_INSEL_S  11
-/** MCPWM_DT1_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DT1_FED_INSEL    (BIT(12))
-#define MCPWM_DT1_FED_INSEL_M  (MCPWM_DT1_FED_INSEL_V << MCPWM_DT1_FED_INSEL_S)
-#define MCPWM_DT1_FED_INSEL_V  0x00000001U
-#define MCPWM_DT1_FED_INSEL_S  12
-/** MCPWM_DT1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DT1_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DT1_RED_OUTINVERT_M  (MCPWM_DT1_RED_OUTINVERT_V << MCPWM_DT1_RED_OUTINVERT_S)
-#define MCPWM_DT1_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT1_RED_OUTINVERT_S  13
-/** MCPWM_DT1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DT1_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DT1_FED_OUTINVERT_M  (MCPWM_DT1_FED_OUTINVERT_V << MCPWM_DT1_FED_OUTINVERT_S)
-#define MCPWM_DT1_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT1_FED_OUTINVERT_S  14
-/** MCPWM_DT1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DT1_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DT1_A_OUTBYPASS_M  (MCPWM_DT1_A_OUTBYPASS_V << MCPWM_DT1_A_OUTBYPASS_S)
-#define MCPWM_DT1_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT1_A_OUTBYPASS_S  15
-/** MCPWM_DT1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DT1_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DT1_B_OUTBYPASS_M  (MCPWM_DT1_B_OUTBYPASS_V << MCPWM_DT1_B_OUTBYPASS_S)
-#define MCPWM_DT1_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT1_B_OUTBYPASS_S  16
-/** MCPWM_DT1_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DT1_CLK_SEL    (BIT(17))
-#define MCPWM_DT1_CLK_SEL_M  (MCPWM_DT1_CLK_SEL_V << MCPWM_DT1_CLK_SEL_S)
-#define MCPWM_DT1_CLK_SEL_V  0x00000001U
-#define MCPWM_DT1_CLK_SEL_S  17
-
-/** MCPWM_DT1_FED_CFG_REG register
- *  PWM generator 1 shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT1_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x94)
-/** MCPWM_DT1_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DT1_FED    0x0000FFFFU
-#define MCPWM_DT1_FED_M  (MCPWM_DT1_FED_V << MCPWM_DT1_FED_S)
-#define MCPWM_DT1_FED_V  0x0000FFFFU
-#define MCPWM_DT1_FED_S  0
-
-/** MCPWM_DT1_RED_CFG_REG register
- *  PWM generator 1 shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT1_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x98)
-/** MCPWM_DT1_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DT1_RED    0x0000FFFFU
-#define MCPWM_DT1_RED_M  (MCPWM_DT1_RED_V << MCPWM_DT1_RED_S)
-#define MCPWM_DT1_RED_V  0x0000FFFFU
-#define MCPWM_DT1_RED_S  0
-
-/** MCPWM_CARRIER1_CFG_REG register
- *  PWM generator 1 carrier enable and configuratoin
- */
-#define MCPWM_CARRIER1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x9c)
-/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier1 function is enabled. When cleared, carrier1 is bypassed
- */
-#define MCPWM_CARRIER1_EN    (BIT(0))
-#define MCPWM_CARRIER1_EN_M  (MCPWM_CARRIER1_EN_V << MCPWM_CARRIER1_EN_S)
-#define MCPWM_CARRIER1_EN_V  0x00000001U
-#define MCPWM_CARRIER1_EN_S  0
-/** MCPWM_CARRIER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CARRIER1_PRESCALE    0x0000000FU
-#define MCPWM_CARRIER1_PRESCALE_M  (MCPWM_CARRIER1_PRESCALE_V << MCPWM_CARRIER1_PRESCALE_S)
-#define MCPWM_CARRIER1_PRESCALE_V  0x0000000FU
-#define MCPWM_CARRIER1_PRESCALE_S  1
-/** MCPWM_CARRIER1_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CARRIER1_DUTY    0x00000007U
-#define MCPWM_CARRIER1_DUTY_M  (MCPWM_CARRIER1_DUTY_V << MCPWM_CARRIER1_DUTY_S)
-#define MCPWM_CARRIER1_DUTY_V  0x00000007U
-#define MCPWM_CARRIER1_DUTY_S  5
-/** MCPWM_CARRIER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CARRIER1_OSHTWTH    0x0000000FU
-#define MCPWM_CARRIER1_OSHTWTH_M  (MCPWM_CARRIER1_OSHTWTH_V << MCPWM_CARRIER1_OSHTWTH_S)
-#define MCPWM_CARRIER1_OSHTWTH_V  0x0000000FU
-#define MCPWM_CARRIER1_OSHTWTH_S  8
-/** MCPWM_CARRIER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM1A and PWM1B for this submodule
- */
-#define MCPWM_CARRIER1_OUT_INVERT    (BIT(12))
-#define MCPWM_CARRIER1_OUT_INVERT_M  (MCPWM_CARRIER1_OUT_INVERT_V << MCPWM_CARRIER1_OUT_INVERT_S)
-#define MCPWM_CARRIER1_OUT_INVERT_V  0x00000001U
-#define MCPWM_CARRIER1_OUT_INVERT_S  12
-/** MCPWM_CARRIER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM1A and PWM1B for this submodule
- */
-#define MCPWM_CARRIER1_IN_INVERT    (BIT(13))
-#define MCPWM_CARRIER1_IN_INVERT_M  (MCPWM_CARRIER1_IN_INVERT_V << MCPWM_CARRIER1_IN_INVERT_S)
-#define MCPWM_CARRIER1_IN_INVERT_V  0x00000001U
-#define MCPWM_CARRIER1_IN_INVERT_S  13
-
-/** MCPWM_FH1_CFG0_REG register
- *  Actions on PWM1A and PWM1B trip events
- */
-#define MCPWM_FH1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa0)
-/** MCPWM_FH1_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH1_SW_CBC    (BIT(0))
-#define MCPWM_FH1_SW_CBC_M  (MCPWM_FH1_SW_CBC_V << MCPWM_FH1_SW_CBC_S)
-#define MCPWM_FH1_SW_CBC_V  0x00000001U
-#define MCPWM_FH1_SW_CBC_S  0
-/** MCPWM_FH1_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH1_F2_CBC    (BIT(1))
-#define MCPWM_FH1_F2_CBC_M  (MCPWM_FH1_F2_CBC_V << MCPWM_FH1_F2_CBC_S)
-#define MCPWM_FH1_F2_CBC_V  0x00000001U
-#define MCPWM_FH1_F2_CBC_S  1
-/** MCPWM_FH1_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH1_F1_CBC    (BIT(2))
-#define MCPWM_FH1_F1_CBC_M  (MCPWM_FH1_F1_CBC_V << MCPWM_FH1_F1_CBC_S)
-#define MCPWM_FH1_F1_CBC_V  0x00000001U
-#define MCPWM_FH1_F1_CBC_S  2
-/** MCPWM_FH1_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH1_F0_CBC    (BIT(3))
-#define MCPWM_FH1_F0_CBC_M  (MCPWM_FH1_F0_CBC_V << MCPWM_FH1_F0_CBC_S)
-#define MCPWM_FH1_F0_CBC_V  0x00000001U
-#define MCPWM_FH1_F0_CBC_S  3
-/** MCPWM_FH1_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH1_SW_OST    (BIT(4))
-#define MCPWM_FH1_SW_OST_M  (MCPWM_FH1_SW_OST_V << MCPWM_FH1_SW_OST_S)
-#define MCPWM_FH1_SW_OST_V  0x00000001U
-#define MCPWM_FH1_SW_OST_S  4
-/** MCPWM_FH1_F2_OST : R/W; bitpos: [5]; default: 0;
- *  fault_event2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH1_F2_OST    (BIT(5))
-#define MCPWM_FH1_F2_OST_M  (MCPWM_FH1_F2_OST_V << MCPWM_FH1_F2_OST_S)
-#define MCPWM_FH1_F2_OST_V  0x00000001U
-#define MCPWM_FH1_F2_OST_S  5
-/** MCPWM_FH1_F1_OST : R/W; bitpos: [6]; default: 0;
- *  fault_event1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH1_F1_OST    (BIT(6))
-#define MCPWM_FH1_F1_OST_M  (MCPWM_FH1_F1_OST_V << MCPWM_FH1_F1_OST_S)
-#define MCPWM_FH1_F1_OST_V  0x00000001U
-#define MCPWM_FH1_F1_OST_S  6
-/** MCPWM_FH1_F0_OST : R/W; bitpos: [7]; default: 0;
- *  fault_event0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH1_F0_OST    (BIT(7))
-#define MCPWM_FH1_F0_OST_M  (MCPWM_FH1_F0_OST_V << MCPWM_FH1_F0_OST_S)
-#define MCPWM_FH1_F0_OST_V  0x00000001U
-#define MCPWM_FH1_F0_OST_S  7
-/** MCPWM_FH1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH1_A_CBC_D    0x00000003U
-#define MCPWM_FH1_A_CBC_D_M  (MCPWM_FH1_A_CBC_D_V << MCPWM_FH1_A_CBC_D_S)
-#define MCPWM_FH1_A_CBC_D_V  0x00000003U
-#define MCPWM_FH1_A_CBC_D_S  8
-/** MCPWM_FH1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH1_A_CBC_U    0x00000003U
-#define MCPWM_FH1_A_CBC_U_M  (MCPWM_FH1_A_CBC_U_V << MCPWM_FH1_A_CBC_U_S)
-#define MCPWM_FH1_A_CBC_U_V  0x00000003U
-#define MCPWM_FH1_A_CBC_U_S  10
-/** MCPWM_FH1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0:
- *  do nothing,1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH1_A_OST_D    0x00000003U
-#define MCPWM_FH1_A_OST_D_M  (MCPWM_FH1_A_OST_D_V << MCPWM_FH1_A_OST_D_S)
-#define MCPWM_FH1_A_OST_D_V  0x00000003U
-#define MCPWM_FH1_A_OST_D_S  12
-/** MCPWM_FH1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH1_A_OST_U    0x00000003U
-#define MCPWM_FH1_A_OST_U_M  (MCPWM_FH1_A_OST_U_V << MCPWM_FH1_A_OST_U_S)
-#define MCPWM_FH1_A_OST_U_V  0x00000003U
-#define MCPWM_FH1_A_OST_U_S  14
-/** MCPWM_FH1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH1_B_CBC_D    0x00000003U
-#define MCPWM_FH1_B_CBC_D_M  (MCPWM_FH1_B_CBC_D_V << MCPWM_FH1_B_CBC_D_S)
-#define MCPWM_FH1_B_CBC_D_V  0x00000003U
-#define MCPWM_FH1_B_CBC_D_S  16
-/** MCPWM_FH1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH1_B_CBC_U    0x00000003U
-#define MCPWM_FH1_B_CBC_U_M  (MCPWM_FH1_B_CBC_U_V << MCPWM_FH1_B_CBC_U_S)
-#define MCPWM_FH1_B_CBC_U_V  0x00000003U
-#define MCPWM_FH1_B_CBC_U_S  18
-/** MCPWM_FH1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH1_B_OST_D    0x00000003U
-#define MCPWM_FH1_B_OST_D_M  (MCPWM_FH1_B_OST_D_V << MCPWM_FH1_B_OST_D_S)
-#define MCPWM_FH1_B_OST_D_V  0x00000003U
-#define MCPWM_FH1_B_OST_D_S  20
-/** MCPWM_FH1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH1_B_OST_U    0x00000003U
-#define MCPWM_FH1_B_OST_U_M  (MCPWM_FH1_B_OST_U_V << MCPWM_FH1_B_OST_U_S)
-#define MCPWM_FH1_B_OST_U_V  0x00000003U
-#define MCPWM_FH1_B_OST_U_S  22
-
-/** MCPWM_FH1_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa4)
-/** MCPWM_FH1_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_FH1_CLR_OST    (BIT(0))
-#define MCPWM_FH1_CLR_OST_M  (MCPWM_FH1_CLR_OST_V << MCPWM_FH1_CLR_OST_S)
-#define MCPWM_FH1_CLR_OST_V  0x00000001U
-#define MCPWM_FH1_CLR_OST_S  0
-/** MCPWM_FH1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP
- */
-#define MCPWM_FH1_CBCPULSE    0x00000003U
-#define MCPWM_FH1_CBCPULSE_M  (MCPWM_FH1_CBCPULSE_V << MCPWM_FH1_CBCPULSE_S)
-#define MCPWM_FH1_CBCPULSE_V  0x00000003U
-#define MCPWM_FH1_CBCPULSE_S  1
-/** MCPWM_FH1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_FH1_FORCE_CBC    (BIT(3))
-#define MCPWM_FH1_FORCE_CBC_M  (MCPWM_FH1_FORCE_CBC_V << MCPWM_FH1_FORCE_CBC_S)
-#define MCPWM_FH1_FORCE_CBC_V  0x00000001U
-#define MCPWM_FH1_FORCE_CBC_S  3
-/** MCPWM_FH1_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_FH1_FORCE_OST    (BIT(4))
-#define MCPWM_FH1_FORCE_OST_M  (MCPWM_FH1_FORCE_OST_V << MCPWM_FH1_FORCE_OST_S)
-#define MCPWM_FH1_FORCE_OST_V  0x00000001U
-#define MCPWM_FH1_FORCE_OST_S  4
-
-/** MCPWM_FH1_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa8)
-/** MCPWM_FH1_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_FH1_CBC_ON    (BIT(0))
-#define MCPWM_FH1_CBC_ON_M  (MCPWM_FH1_CBC_ON_V << MCPWM_FH1_CBC_ON_S)
-#define MCPWM_FH1_CBC_ON_V  0x00000001U
-#define MCPWM_FH1_CBC_ON_S  0
-/** MCPWM_FH1_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_FH1_OST_ON    (BIT(1))
-#define MCPWM_FH1_OST_ON_M  (MCPWM_FH1_OST_ON_V << MCPWM_FH1_OST_ON_S)
-#define MCPWM_FH1_OST_ON_V  0x00000001U
-#define MCPWM_FH1_OST_ON_S  1
-
-/** MCPWM_GEN2_STMP_CFG_REG register
- *  Transfer status and update method for time stamp registers A and B
- */
-#define MCPWM_GEN2_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xac)
-/** MCPWM_GEN2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 2 time stamp A's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_GEN2_A_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_A_UPMETHOD_M  (MCPWM_GEN2_A_UPMETHOD_V << MCPWM_GEN2_A_UPMETHOD_S)
-#define MCPWM_GEN2_A_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_A_UPMETHOD_S  0
-/** MCPWM_GEN2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for PWM generator 2 time stamp B's active register. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
- *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
- */
-#define MCPWM_GEN2_B_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_B_UPMETHOD_M  (MCPWM_GEN2_B_UPMETHOD_V << MCPWM_GEN2_B_UPMETHOD_S)
-#define MCPWM_GEN2_B_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_B_UPMETHOD_S  4
-/** MCPWM_GEN2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is
- *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_GEN2_A_SHDW_FULL    (BIT(8))
-#define MCPWM_GEN2_A_SHDW_FULL_M  (MCPWM_GEN2_A_SHDW_FULL_V << MCPWM_GEN2_A_SHDW_FULL_S)
-#define MCPWM_GEN2_A_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN2_A_SHDW_FULL_S  8
-/** MCPWM_GEN2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
- *  Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is
- *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
- *  has been updated with shadow register latest value
- */
-#define MCPWM_GEN2_B_SHDW_FULL    (BIT(9))
-#define MCPWM_GEN2_B_SHDW_FULL_M  (MCPWM_GEN2_B_SHDW_FULL_V << MCPWM_GEN2_B_SHDW_FULL_S)
-#define MCPWM_GEN2_B_SHDW_FULL_V  0x00000001U
-#define MCPWM_GEN2_B_SHDW_FULL_S  9
-
-/** MCPWM_GEN2_TSTMP_A_REG register
- *  PWM generator 2 shadow register for timer stamp A.
- */
-#define MCPWM_GEN2_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb0)
-/** MCPWM_GEN2_A : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 2 time stamp A's shadow register
- */
-#define MCPWM_GEN2_A    0x0000FFFFU
-#define MCPWM_GEN2_A_M  (MCPWM_GEN2_A_V << MCPWM_GEN2_A_S)
-#define MCPWM_GEN2_A_V  0x0000FFFFU
-#define MCPWM_GEN2_A_S  0
-
-/** MCPWM_GEN2_TSTMP_B_REG register
- *  PWM generator 2 shadow register for timer stamp A.
- */
-#define MCPWM_GEN2_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb4)
-/** MCPWM_GEN2_B : R/W; bitpos: [15:0]; default: 0;
- *  PWM generator 2 time stamp B's shadow register
- */
-#define MCPWM_GEN2_B    0x0000FFFFU
-#define MCPWM_GEN2_B_M  (MCPWM_GEN2_B_V << MCPWM_GEN2_B_S)
-#define MCPWM_GEN2_B_V  0x0000FFFFU
-#define MCPWM_GEN2_B_S  0
-
-/** MCPWM_GEN2_CFG0_REG register
- *  PWM generator 2 event T0 and T1 handling
- */
-#define MCPWM_GEN2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb8)
-/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for PWM generator 2's active register of configuration. 0:
- *  immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is
- *  set to 1:disable the update.
- */
-#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
-#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
-#define MCPWM_GEN2_CFG_UPMETHOD_S  0
-/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
- *  Source selection for PWM generator 2 event_t0, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN2_T0_SEL    0x00000007U
-#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
-#define MCPWM_GEN2_T0_SEL_V  0x00000007U
-#define MCPWM_GEN2_T0_SEL_S  4
-/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
- *  Source selection for PWM generator 2 event_t1, take effect immediately, 0:
- *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
- */
-#define MCPWM_GEN2_T1_SEL    0x00000007U
-#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
-#define MCPWM_GEN2_T1_SEL_V  0x00000007U
-#define MCPWM_GEN2_T1_SEL_S  7
-
-/** MCPWM_GEN2_FORCE_REG register
- *  Permissives to force PWM2A and PWM2B outputs by software
- */
-#define MCPWM_GEN2_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0xbc)
-/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
- *  Updating method for continuous software force of PWM generator 2. When all bits are
- *  set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when
- *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
- *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
- *  generated when the timer's value equals to that of register A/B.)
- */
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
-#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
-/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
- *  Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
-/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
- *  Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled
- */
-#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
-/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM2A, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
-#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
-#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_A_NCIFORCE_S  10
-/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
- *  non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
-/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
- *  Trigger of non-continuous immediate software-force event for PWM2B, a toggle will
- *  trigger a force event.
- */
-#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
-#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
-#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
-#define MCPWM_GEN2_B_NCIFORCE_S  13
-/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
- *  non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2:
- *  high, 3: disabled
- */
-#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
-#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
-#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
-
-/** MCPWM_GEN2_A_REG register
- *  Actions triggered by events on PWM2A
- */
-#define MCPWM_GEN2_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc0)
-/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM2A triggered by event TEZ when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_UTEZ    0x00000003U
-#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
-#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_UTEZ_S  0
-/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM2A triggered by event TEP when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_UTEP    0x00000003U
-#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
-#define MCPWM_GEN2_A_UTEP_V  0x00000003U
-#define MCPWM_GEN2_A_UTEP_S  2
-/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM2A triggered by event TEA when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_UTEA    0x00000003U
-#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
-#define MCPWM_GEN2_A_UTEA_V  0x00000003U
-#define MCPWM_GEN2_A_UTEA_S  4
-/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM2A triggered by event TEB when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_UTEB    0x00000003U
-#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
-#define MCPWM_GEN2_A_UTEB_V  0x00000003U
-#define MCPWM_GEN2_A_UTEB_S  6
-/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM2A triggered by event_t0 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_UT0    0x00000003U
-#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
-#define MCPWM_GEN2_A_UT0_V  0x00000003U
-#define MCPWM_GEN2_A_UT0_S  8
-/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM2A triggered by event_t1 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_UT1    0x00000003U
-#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
-#define MCPWM_GEN2_A_UT1_V  0x00000003U
-#define MCPWM_GEN2_A_UT1_S  10
-/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM2A triggered by event TEZ when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_DTEZ    0x00000003U
-#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
-#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_A_DTEZ_S  12
-/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM2A triggered by event TEP when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_DTEP    0x00000003U
-#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
-#define MCPWM_GEN2_A_DTEP_V  0x00000003U
-#define MCPWM_GEN2_A_DTEP_S  14
-/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM2A triggered by event TEA when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_DTEA    0x00000003U
-#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
-#define MCPWM_GEN2_A_DTEA_V  0x00000003U
-#define MCPWM_GEN2_A_DTEA_S  16
-/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM2A triggered by event TEB when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_DTEB    0x00000003U
-#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
-#define MCPWM_GEN2_A_DTEB_V  0x00000003U
-#define MCPWM_GEN2_A_DTEB_S  18
-/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM2A triggered by event_t0 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_DT0    0x00000003U
-#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
-#define MCPWM_GEN2_A_DT0_V  0x00000003U
-#define MCPWM_GEN2_A_DT0_S  20
-/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_A_DT1    0x00000003U
-#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
-#define MCPWM_GEN2_A_DT1_V  0x00000003U
-#define MCPWM_GEN2_A_DT1_S  22
-
-/** MCPWM_GEN2_B_REG register
- *  Actions triggered by events on PWM2B
- */
-#define MCPWM_GEN2_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc4)
-/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
- *  Action on PWM2B triggered by event TEZ when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_UTEZ    0x00000003U
-#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
-#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_UTEZ_S  0
-/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
- *  Action on PWM2B triggered by event TEP when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_UTEP    0x00000003U
-#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
-#define MCPWM_GEN2_B_UTEP_V  0x00000003U
-#define MCPWM_GEN2_B_UTEP_S  2
-/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
- *  Action on PWM2B triggered by event TEA when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_UTEA    0x00000003U
-#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
-#define MCPWM_GEN2_B_UTEA_V  0x00000003U
-#define MCPWM_GEN2_B_UTEA_S  4
-/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
- *  Action on PWM2B triggered by event TEB when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_UTEB    0x00000003U
-#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
-#define MCPWM_GEN2_B_UTEB_V  0x00000003U
-#define MCPWM_GEN2_B_UTEB_S  6
-/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
- *  Action on PWM2B triggered by event_t0 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_UT0    0x00000003U
-#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
-#define MCPWM_GEN2_B_UT0_V  0x00000003U
-#define MCPWM_GEN2_B_UT0_S  8
-/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
- *  Action on PWM2B triggered by event_t1 when timer increasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_UT1    0x00000003U
-#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
-#define MCPWM_GEN2_B_UT1_V  0x00000003U
-#define MCPWM_GEN2_B_UT1_S  10
-/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
- *  Action on PWM2B triggered by event TEZ when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_DTEZ    0x00000003U
-#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
-#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
-#define MCPWM_GEN2_B_DTEZ_S  12
-/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
- *  Action on PWM2B triggered by event TEP when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_DTEP    0x00000003U
-#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
-#define MCPWM_GEN2_B_DTEP_V  0x00000003U
-#define MCPWM_GEN2_B_DTEP_S  14
-/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
- *  Action on PWM2B triggered by event TEA when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_DTEA    0x00000003U
-#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
-#define MCPWM_GEN2_B_DTEA_V  0x00000003U
-#define MCPWM_GEN2_B_DTEA_S  16
-/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
- *  Action on PWM2B triggered by event TEB when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_DTEB    0x00000003U
-#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
-#define MCPWM_GEN2_B_DTEB_V  0x00000003U
-#define MCPWM_GEN2_B_DTEB_S  18
-/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
- *  Action on PWM2B triggered by event_t0 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_DT0    0x00000003U
-#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
-#define MCPWM_GEN2_B_DT0_V  0x00000003U
-#define MCPWM_GEN2_B_DT0_S  20
-/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
- *  Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
- *  2: high, 3: toggle
- */
-#define MCPWM_GEN2_B_DT1    0x00000003U
-#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
-#define MCPWM_GEN2_B_DT1_V  0x00000003U
-#define MCPWM_GEN2_B_DT1_S  22
-
-/** MCPWM_DT2_CFG_REG register
- *  PWM generator 2 dead time type selection and configuration
- */
-#define MCPWM_DT2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc8)
-/** MCPWM_DT2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
- *  Update method for FED (falling edge delay) active register.  0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DT2_FED_UPMETHOD    0x0000000FU
-#define MCPWM_DT2_FED_UPMETHOD_M  (MCPWM_DT2_FED_UPMETHOD_V << MCPWM_DT2_FED_UPMETHOD_S)
-#define MCPWM_DT2_FED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT2_FED_UPMETHOD_S  0
-/** MCPWM_DT2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
- *  Update method for RED (rising edge delay) active register.  0: immediate,when bit0
- *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
- *  bit3 is set to 1: disable the update
- */
-#define MCPWM_DT2_RED_UPMETHOD    0x0000000FU
-#define MCPWM_DT2_RED_UPMETHOD_M  (MCPWM_DT2_RED_UPMETHOD_V << MCPWM_DT2_RED_UPMETHOD_S)
-#define MCPWM_DT2_RED_UPMETHOD_V  0x0000000FU
-#define MCPWM_DT2_RED_UPMETHOD_S  4
-/** MCPWM_DT2_DEB_MODE : R/W; bitpos: [8]; default: 0;
- *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
- *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
- */
-#define MCPWM_DT2_DEB_MODE    (BIT(8))
-#define MCPWM_DT2_DEB_MODE_M  (MCPWM_DT2_DEB_MODE_V << MCPWM_DT2_DEB_MODE_S)
-#define MCPWM_DT2_DEB_MODE_V  0x00000001U
-#define MCPWM_DT2_DEB_MODE_S  8
-/** MCPWM_DT2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
- *  S6 in table
- */
-#define MCPWM_DT2_A_OUTSWAP    (BIT(9))
-#define MCPWM_DT2_A_OUTSWAP_M  (MCPWM_DT2_A_OUTSWAP_V << MCPWM_DT2_A_OUTSWAP_S)
-#define MCPWM_DT2_A_OUTSWAP_V  0x00000001U
-#define MCPWM_DT2_A_OUTSWAP_S  9
-/** MCPWM_DT2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
- *  S7 in table
- */
-#define MCPWM_DT2_B_OUTSWAP    (BIT(10))
-#define MCPWM_DT2_B_OUTSWAP_M  (MCPWM_DT2_B_OUTSWAP_V << MCPWM_DT2_B_OUTSWAP_S)
-#define MCPWM_DT2_B_OUTSWAP_V  0x00000001U
-#define MCPWM_DT2_B_OUTSWAP_S  10
-/** MCPWM_DT2_RED_INSEL : R/W; bitpos: [11]; default: 0;
- *  S4 in table
- */
-#define MCPWM_DT2_RED_INSEL    (BIT(11))
-#define MCPWM_DT2_RED_INSEL_M  (MCPWM_DT2_RED_INSEL_V << MCPWM_DT2_RED_INSEL_S)
-#define MCPWM_DT2_RED_INSEL_V  0x00000001U
-#define MCPWM_DT2_RED_INSEL_S  11
-/** MCPWM_DT2_FED_INSEL : R/W; bitpos: [12]; default: 0;
- *  S5 in table
- */
-#define MCPWM_DT2_FED_INSEL    (BIT(12))
-#define MCPWM_DT2_FED_INSEL_M  (MCPWM_DT2_FED_INSEL_V << MCPWM_DT2_FED_INSEL_S)
-#define MCPWM_DT2_FED_INSEL_V  0x00000001U
-#define MCPWM_DT2_FED_INSEL_S  12
-/** MCPWM_DT2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
- *  S2 in table
- */
-#define MCPWM_DT2_RED_OUTINVERT    (BIT(13))
-#define MCPWM_DT2_RED_OUTINVERT_M  (MCPWM_DT2_RED_OUTINVERT_V << MCPWM_DT2_RED_OUTINVERT_S)
-#define MCPWM_DT2_RED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT2_RED_OUTINVERT_S  13
-/** MCPWM_DT2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
- *  S3 in table
- */
-#define MCPWM_DT2_FED_OUTINVERT    (BIT(14))
-#define MCPWM_DT2_FED_OUTINVERT_M  (MCPWM_DT2_FED_OUTINVERT_V << MCPWM_DT2_FED_OUTINVERT_S)
-#define MCPWM_DT2_FED_OUTINVERT_V  0x00000001U
-#define MCPWM_DT2_FED_OUTINVERT_S  14
-/** MCPWM_DT2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
- *  S1 in table
- */
-#define MCPWM_DT2_A_OUTBYPASS    (BIT(15))
-#define MCPWM_DT2_A_OUTBYPASS_M  (MCPWM_DT2_A_OUTBYPASS_V << MCPWM_DT2_A_OUTBYPASS_S)
-#define MCPWM_DT2_A_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT2_A_OUTBYPASS_S  15
-/** MCPWM_DT2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
- *  S0 in table
- */
-#define MCPWM_DT2_B_OUTBYPASS    (BIT(16))
-#define MCPWM_DT2_B_OUTBYPASS_M  (MCPWM_DT2_B_OUTBYPASS_V << MCPWM_DT2_B_OUTBYPASS_S)
-#define MCPWM_DT2_B_OUTBYPASS_V  0x00000001U
-#define MCPWM_DT2_B_OUTBYPASS_S  16
-/** MCPWM_DT2_CLK_SEL : R/W; bitpos: [17]; default: 0;
- *  Dead time clock selection. 0: PWM_clk, 1: PT_clk
- */
-#define MCPWM_DT2_CLK_SEL    (BIT(17))
-#define MCPWM_DT2_CLK_SEL_M  (MCPWM_DT2_CLK_SEL_V << MCPWM_DT2_CLK_SEL_S)
-#define MCPWM_DT2_CLK_SEL_V  0x00000001U
-#define MCPWM_DT2_CLK_SEL_S  17
-
-/** MCPWM_DT2_FED_CFG_REG register
- *  PWM generator 2 shadow register for falling edge delay (FED).
- */
-#define MCPWM_DT2_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xcc)
-/** MCPWM_DT2_FED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for FED
- */
-#define MCPWM_DT2_FED    0x0000FFFFU
-#define MCPWM_DT2_FED_M  (MCPWM_DT2_FED_V << MCPWM_DT2_FED_S)
-#define MCPWM_DT2_FED_V  0x0000FFFFU
-#define MCPWM_DT2_FED_S  0
-
-/** MCPWM_DT2_RED_CFG_REG register
- *  PWM generator 2 shadow register for rising edge delay (RED).
- */
-#define MCPWM_DT2_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd0)
-/** MCPWM_DT2_RED : R/W; bitpos: [15:0]; default: 0;
- *  Shadow register for RED
- */
-#define MCPWM_DT2_RED    0x0000FFFFU
-#define MCPWM_DT2_RED_M  (MCPWM_DT2_RED_V << MCPWM_DT2_RED_S)
-#define MCPWM_DT2_RED_V  0x0000FFFFU
-#define MCPWM_DT2_RED_S  0
-
-/** MCPWM_CARRIER2_CFG_REG register
- *  PWM generator 2 carrier enable and configuratoin
- */
-#define MCPWM_CARRIER2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd4)
-/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0;
- *  When set, carrier2 function is enabled. When cleared, carrier2 is bypassed
- */
-#define MCPWM_CARRIER2_EN    (BIT(0))
-#define MCPWM_CARRIER2_EN_M  (MCPWM_CARRIER2_EN_V << MCPWM_CARRIER2_EN_S)
-#define MCPWM_CARRIER2_EN_V  0x00000001U
-#define MCPWM_CARRIER2_EN_S  0
-/** MCPWM_CARRIER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
- *  PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
- *  (PWM_CARRIER0_PRESCALE + 1)
- */
-#define MCPWM_CARRIER2_PRESCALE    0x0000000FU
-#define MCPWM_CARRIER2_PRESCALE_M  (MCPWM_CARRIER2_PRESCALE_V << MCPWM_CARRIER2_PRESCALE_S)
-#define MCPWM_CARRIER2_PRESCALE_V  0x0000000FU
-#define MCPWM_CARRIER2_PRESCALE_S  1
-/** MCPWM_CARRIER2_DUTY : R/W; bitpos: [7:5]; default: 0;
- *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
- */
-#define MCPWM_CARRIER2_DUTY    0x00000007U
-#define MCPWM_CARRIER2_DUTY_M  (MCPWM_CARRIER2_DUTY_V << MCPWM_CARRIER2_DUTY_S)
-#define MCPWM_CARRIER2_DUTY_V  0x00000007U
-#define MCPWM_CARRIER2_DUTY_S  5
-/** MCPWM_CARRIER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
- *  width of the first pulse in number of periods of the carrier
- */
-#define MCPWM_CARRIER2_OSHTWTH    0x0000000FU
-#define MCPWM_CARRIER2_OSHTWTH_M  (MCPWM_CARRIER2_OSHTWTH_V << MCPWM_CARRIER2_OSHTWTH_S)
-#define MCPWM_CARRIER2_OSHTWTH_V  0x0000000FU
-#define MCPWM_CARRIER2_OSHTWTH_S  8
-/** MCPWM_CARRIER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
- *  when set, invert the output of PWM2A and PWM2B for this submodule
- */
-#define MCPWM_CARRIER2_OUT_INVERT    (BIT(12))
-#define MCPWM_CARRIER2_OUT_INVERT_M  (MCPWM_CARRIER2_OUT_INVERT_V << MCPWM_CARRIER2_OUT_INVERT_S)
-#define MCPWM_CARRIER2_OUT_INVERT_V  0x00000001U
-#define MCPWM_CARRIER2_OUT_INVERT_S  12
-/** MCPWM_CARRIER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
- *  when set, invert the input of PWM2A and PWM2B for this submodule
- */
-#define MCPWM_CARRIER2_IN_INVERT    (BIT(13))
-#define MCPWM_CARRIER2_IN_INVERT_M  (MCPWM_CARRIER2_IN_INVERT_V << MCPWM_CARRIER2_IN_INVERT_S)
-#define MCPWM_CARRIER2_IN_INVERT_V  0x00000001U
-#define MCPWM_CARRIER2_IN_INVERT_S  13
-
-/** MCPWM_FH2_CFG0_REG register
- *  Actions on PWM2A and PWM2B trip events
- */
-#define MCPWM_FH2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd8)
-/** MCPWM_FH2_SW_CBC : R/W; bitpos: [0]; default: 0;
- *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH2_SW_CBC    (BIT(0))
-#define MCPWM_FH2_SW_CBC_M  (MCPWM_FH2_SW_CBC_V << MCPWM_FH2_SW_CBC_S)
-#define MCPWM_FH2_SW_CBC_V  0x00000001U
-#define MCPWM_FH2_SW_CBC_S  0
-/** MCPWM_FH2_F2_CBC : R/W; bitpos: [1]; default: 0;
- *  fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH2_F2_CBC    (BIT(1))
-#define MCPWM_FH2_F2_CBC_M  (MCPWM_FH2_F2_CBC_V << MCPWM_FH2_F2_CBC_S)
-#define MCPWM_FH2_F2_CBC_V  0x00000001U
-#define MCPWM_FH2_F2_CBC_S  1
-/** MCPWM_FH2_F1_CBC : R/W; bitpos: [2]; default: 0;
- *  fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH2_F1_CBC    (BIT(2))
-#define MCPWM_FH2_F1_CBC_M  (MCPWM_FH2_F1_CBC_V << MCPWM_FH2_F1_CBC_S)
-#define MCPWM_FH2_F1_CBC_V  0x00000001U
-#define MCPWM_FH2_F1_CBC_S  2
-/** MCPWM_FH2_F0_CBC : R/W; bitpos: [3]; default: 0;
- *  fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH2_F0_CBC    (BIT(3))
-#define MCPWM_FH2_F0_CBC_M  (MCPWM_FH2_F0_CBC_V << MCPWM_FH2_F0_CBC_S)
-#define MCPWM_FH2_F0_CBC_V  0x00000001U
-#define MCPWM_FH2_F0_CBC_S  3
-/** MCPWM_FH2_SW_OST : R/W; bitpos: [4]; default: 0;
- *  Enable register for software force one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH2_SW_OST    (BIT(4))
-#define MCPWM_FH2_SW_OST_M  (MCPWM_FH2_SW_OST_V << MCPWM_FH2_SW_OST_S)
-#define MCPWM_FH2_SW_OST_V  0x00000001U
-#define MCPWM_FH2_SW_OST_S  4
-/** MCPWM_FH2_F2_OST : R/W; bitpos: [5]; default: 0;
- *  fault_event2 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH2_F2_OST    (BIT(5))
-#define MCPWM_FH2_F2_OST_M  (MCPWM_FH2_F2_OST_V << MCPWM_FH2_F2_OST_S)
-#define MCPWM_FH2_F2_OST_V  0x00000001U
-#define MCPWM_FH2_F2_OST_S  5
-/** MCPWM_FH2_F1_OST : R/W; bitpos: [6]; default: 0;
- *  fault_event1 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH2_F1_OST    (BIT(6))
-#define MCPWM_FH2_F1_OST_M  (MCPWM_FH2_F1_OST_V << MCPWM_FH2_F1_OST_S)
-#define MCPWM_FH2_F1_OST_V  0x00000001U
-#define MCPWM_FH2_F1_OST_S  6
-/** MCPWM_FH2_F0_OST : R/W; bitpos: [7]; default: 0;
- *  fault_event0 will trigger one-shot mode action. 0: disable, 1: enable
- */
-#define MCPWM_FH2_F0_OST    (BIT(7))
-#define MCPWM_FH2_F0_OST_M  (MCPWM_FH2_F0_OST_V << MCPWM_FH2_F0_OST_S)
-#define MCPWM_FH2_F0_OST_V  0x00000001U
-#define MCPWM_FH2_F0_OST_S  7
-/** MCPWM_FH2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
- *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH2_A_CBC_D    0x00000003U
-#define MCPWM_FH2_A_CBC_D_M  (MCPWM_FH2_A_CBC_D_V << MCPWM_FH2_A_CBC_D_S)
-#define MCPWM_FH2_A_CBC_D_V  0x00000003U
-#define MCPWM_FH2_A_CBC_D_S  8
-/** MCPWM_FH2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
- *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH2_A_CBC_U    0x00000003U
-#define MCPWM_FH2_A_CBC_U_M  (MCPWM_FH2_A_CBC_U_V << MCPWM_FH2_A_CBC_U_S)
-#define MCPWM_FH2_A_CBC_U_V  0x00000003U
-#define MCPWM_FH2_A_CBC_U_S  10
-/** MCPWM_FH2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
- *  One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH2_A_OST_D    0x00000003U
-#define MCPWM_FH2_A_OST_D_M  (MCPWM_FH2_A_OST_D_V << MCPWM_FH2_A_OST_D_S)
-#define MCPWM_FH2_A_OST_D_V  0x00000003U
-#define MCPWM_FH2_A_OST_D_S  12
-/** MCPWM_FH2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
- *  One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH2_A_OST_U    0x00000003U
-#define MCPWM_FH2_A_OST_U_M  (MCPWM_FH2_A_OST_U_V << MCPWM_FH2_A_OST_U_S)
-#define MCPWM_FH2_A_OST_U_V  0x00000003U
-#define MCPWM_FH2_A_OST_U_S  14
-/** MCPWM_FH2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
- *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
- *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH2_B_CBC_D    0x00000003U
-#define MCPWM_FH2_B_CBC_D_M  (MCPWM_FH2_B_CBC_D_V << MCPWM_FH2_B_CBC_D_S)
-#define MCPWM_FH2_B_CBC_D_V  0x00000003U
-#define MCPWM_FH2_B_CBC_D_S  16
-/** MCPWM_FH2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
- *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
- *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH2_B_CBC_U    0x00000003U
-#define MCPWM_FH2_B_CBC_U_M  (MCPWM_FH2_B_CBC_U_V << MCPWM_FH2_B_CBC_U_S)
-#define MCPWM_FH2_B_CBC_U_V  0x00000003U
-#define MCPWM_FH2_B_CBC_U_S  18
-/** MCPWM_FH2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
- *  One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH2_B_OST_D    0x00000003U
-#define MCPWM_FH2_B_OST_D_M  (MCPWM_FH2_B_OST_D_V << MCPWM_FH2_B_OST_D_S)
-#define MCPWM_FH2_B_OST_D_V  0x00000003U
-#define MCPWM_FH2_B_OST_D_S  20
-/** MCPWM_FH2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
- *  One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0:
- *  do nothing, 1: force low, 2: force high, 3: toggle
- */
-#define MCPWM_FH2_B_OST_U    0x00000003U
-#define MCPWM_FH2_B_OST_U_M  (MCPWM_FH2_B_OST_U_V << MCPWM_FH2_B_OST_U_S)
-#define MCPWM_FH2_B_OST_U_V  0x00000003U
-#define MCPWM_FH2_B_OST_U_S  22
-
-/** MCPWM_FH2_CFG1_REG register
- *  Software triggers for fault handler actions
- */
-#define MCPWM_FH2_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0xdc)
-/** MCPWM_FH2_CLR_OST : R/W; bitpos: [0]; default: 0;
- *  a rising edge will clear on going one-shot mode action
- */
-#define MCPWM_FH2_CLR_OST    (BIT(0))
-#define MCPWM_FH2_CLR_OST_M  (MCPWM_FH2_CLR_OST_V << MCPWM_FH2_CLR_OST_S)
-#define MCPWM_FH2_CLR_OST_V  0x00000001U
-#define MCPWM_FH2_CLR_OST_S  0
-/** MCPWM_FH2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
- *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
- *  when bit1 is set to 1:TEP
- */
-#define MCPWM_FH2_CBCPULSE    0x00000003U
-#define MCPWM_FH2_CBCPULSE_M  (MCPWM_FH2_CBCPULSE_V << MCPWM_FH2_CBCPULSE_S)
-#define MCPWM_FH2_CBCPULSE_V  0x00000003U
-#define MCPWM_FH2_CBCPULSE_S  1
-/** MCPWM_FH2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
- *  a toggle trigger a cycle-by-cycle mode action
- */
-#define MCPWM_FH2_FORCE_CBC    (BIT(3))
-#define MCPWM_FH2_FORCE_CBC_M  (MCPWM_FH2_FORCE_CBC_V << MCPWM_FH2_FORCE_CBC_S)
-#define MCPWM_FH2_FORCE_CBC_V  0x00000001U
-#define MCPWM_FH2_FORCE_CBC_S  3
-/** MCPWM_FH2_FORCE_OST : R/W; bitpos: [4]; default: 0;
- *  a toggle (software negate its value) triggers a one-shot mode action
- */
-#define MCPWM_FH2_FORCE_OST    (BIT(4))
-#define MCPWM_FH2_FORCE_OST_M  (MCPWM_FH2_FORCE_OST_V << MCPWM_FH2_FORCE_OST_S)
-#define MCPWM_FH2_FORCE_OST_V  0x00000001U
-#define MCPWM_FH2_FORCE_OST_S  4
-
-/** MCPWM_FH2_STATUS_REG register
- *  Status of fault events.
- */
-#define MCPWM_FH2_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe0)
-/** MCPWM_FH2_CBC_ON : RO; bitpos: [0]; default: 0;
- *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
- */
-#define MCPWM_FH2_CBC_ON    (BIT(0))
-#define MCPWM_FH2_CBC_ON_M  (MCPWM_FH2_CBC_ON_V << MCPWM_FH2_CBC_ON_S)
-#define MCPWM_FH2_CBC_ON_V  0x00000001U
-#define MCPWM_FH2_CBC_ON_S  0
-/** MCPWM_FH2_OST_ON : RO; bitpos: [1]; default: 0;
- *  Set and reset by hardware. If set, an one-shot mode action is on going
- */
-#define MCPWM_FH2_OST_ON    (BIT(1))
-#define MCPWM_FH2_OST_ON_M  (MCPWM_FH2_OST_ON_V << MCPWM_FH2_OST_ON_S)
-#define MCPWM_FH2_OST_ON_V  0x00000001U
-#define MCPWM_FH2_OST_ON_S  1
-
-/** MCPWM_FAULT_DETECT_REG register
- *  Fault detection configuration and status
- */
-#define MCPWM_FAULT_DETECT_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe4)
-/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, fault_event0 generation is enabled
- */
-#define MCPWM_F0_EN    (BIT(0))
-#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
-#define MCPWM_F0_EN_V  0x00000001U
-#define MCPWM_F0_EN_S  0
-/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
- *  When set, fault_event1 generation is enabled
- */
-#define MCPWM_F1_EN    (BIT(1))
-#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
-#define MCPWM_F1_EN_V  0x00000001U
-#define MCPWM_F1_EN_S  1
-/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
- *  When set, fault_event2 generation is enabled
- */
-#define MCPWM_F2_EN    (BIT(2))
-#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
-#define MCPWM_F2_EN_V  0x00000001U
-#define MCPWM_F2_EN_S  2
-/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
- *  Set fault_event0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
- *  1: level high
- */
-#define MCPWM_F0_POLE    (BIT(3))
-#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
-#define MCPWM_F0_POLE_V  0x00000001U
-#define MCPWM_F0_POLE_S  3
-/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
- *  Set fault_event1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
- *  1: level high
- */
-#define MCPWM_F1_POLE    (BIT(4))
-#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
-#define MCPWM_F1_POLE_V  0x00000001U
-#define MCPWM_F1_POLE_S  4
-/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
- *  Set fault_event2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
- *  1: level high
- */
-#define MCPWM_F2_POLE    (BIT(5))
-#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
-#define MCPWM_F2_POLE_V  0x00000001U
-#define MCPWM_F2_POLE_S  5
-/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
- *  Set and reset by hardware. If set, fault_event0 is on going
- */
-#define MCPWM_EVENT_F0    (BIT(6))
-#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
-#define MCPWM_EVENT_F0_V  0x00000001U
-#define MCPWM_EVENT_F0_S  6
-/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
- *  Set and reset by hardware. If set, fault_event1 is on going
- */
-#define MCPWM_EVENT_F1    (BIT(7))
-#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
-#define MCPWM_EVENT_F1_V  0x00000001U
-#define MCPWM_EVENT_F1_S  7
-/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
- *  Set and reset by hardware. If set, fault_event2 is on going
- */
-#define MCPWM_EVENT_F2    (BIT(8))
-#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
-#define MCPWM_EVENT_F2_V  0x00000001U
-#define MCPWM_EVENT_F2_S  8
-
-/** MCPWM_CAP_TIMER_CFG_REG register
- *  Configure capture timer
- */
-#define MCPWM_CAP_TIMER_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe8)
-/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture timer incrementing under APB_clk is enabled.
- */
-#define MCPWM_CAP_TIMER_EN    (BIT(0))
-#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
-#define MCPWM_CAP_TIMER_EN_V  0x00000001U
-#define MCPWM_CAP_TIMER_EN_S  0
-/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
- *  When set, capture timer sync is enabled.
- */
-#define MCPWM_CAP_SYNCI_EN    (BIT(1))
-#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
-#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
-#define MCPWM_CAP_SYNCI_EN_S  1
-/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
- *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
- *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
- *  6: SYNC2 from GPIO matrix
- */
-#define MCPWM_CAP_SYNCI_SEL    0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
-#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
-#define MCPWM_CAP_SYNCI_SEL_S  2
-/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
- *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
- *  timer is loaded with value in phase register.
- */
-#define MCPWM_CAP_SYNC_SW    (BIT(5))
-#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
-#define MCPWM_CAP_SYNC_SW_V  0x00000001U
-#define MCPWM_CAP_SYNC_SW_S  5
-
-/** MCPWM_CAP_TIMER_PHASE_REG register
- *  Phase for capture timer sync
- */
-#define MCPWM_CAP_TIMER_PHASE_REG(i) (DR_REG_MCPWM_BASE(i) + 0xec)
-/** MCPWM_CAP_TIMER_PHASE : R/W; bitpos: [31:0]; default: 0;
- *  Phase value for capture timer sync operation.
- */
-#define MCPWM_CAP_TIMER_PHASE    0xFFFFFFFFU
-#define MCPWM_CAP_TIMER_PHASE_M  (MCPWM_CAP_TIMER_PHASE_V << MCPWM_CAP_TIMER_PHASE_S)
-#define MCPWM_CAP_TIMER_PHASE_V  0xFFFFFFFFU
-#define MCPWM_CAP_TIMER_PHASE_S  0
-
-/** MCPWM_CAP_CH0_CFG_REG register
- *  Capture channel 0 configuration and enable
- */
-#define MCPWM_CAP_CH0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf0)
-/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 0 is enabled
- */
-#define MCPWM_CAP0_EN    (BIT(0))
-#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
-#define MCPWM_CAP0_EN_V  0x00000001U
-#define MCPWM_CAP0_EN_S  0
-/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP0_MODE    0x00000003U
-#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
-#define MCPWM_CAP0_MODE_V  0x00000003U
-#define MCPWM_CAP0_MODE_S  1
-/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
- *  1
- */
-#define MCPWM_CAP0_PRESCALE    0x000000FFU
-#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
-#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP0_PRESCALE_S  3
-/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP0 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP0_IN_INVERT    (BIT(11))
-#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
-#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP0_IN_INVERT_S  11
-/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 0
- */
-#define MCPWM_CAP0_SW    (BIT(12))
-#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
-#define MCPWM_CAP0_SW_V  0x00000001U
-#define MCPWM_CAP0_SW_S  12
-
-/** MCPWM_CAP_CH1_CFG_REG register
- *  Capture channel 1 configuration and enable
- */
-#define MCPWM_CAP_CH1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf4)
-/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 2 is enabled
- */
-#define MCPWM_CAP1_EN    (BIT(0))
-#define MCPWM_CAP1_EN_M  (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S)
-#define MCPWM_CAP1_EN_V  0x00000001U
-#define MCPWM_CAP1_EN_S  0
-/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP1_MODE    0x00000003U
-#define MCPWM_CAP1_MODE_M  (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S)
-#define MCPWM_CAP1_MODE_V  0x00000003U
-#define MCPWM_CAP1_MODE_S  1
-/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
- *  1
- */
-#define MCPWM_CAP1_PRESCALE    0x000000FFU
-#define MCPWM_CAP1_PRESCALE_M  (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S)
-#define MCPWM_CAP1_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP1_PRESCALE_S  3
-/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP1 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP1_IN_INVERT    (BIT(11))
-#define MCPWM_CAP1_IN_INVERT_M  (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S)
-#define MCPWM_CAP1_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP1_IN_INVERT_S  11
-/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 1
- */
-#define MCPWM_CAP1_SW    (BIT(12))
-#define MCPWM_CAP1_SW_M  (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S)
-#define MCPWM_CAP1_SW_V  0x00000001U
-#define MCPWM_CAP1_SW_S  12
-
-/** MCPWM_CAP_CH2_CFG_REG register
- *  Capture channel 2 configuration and enable
- */
-#define MCPWM_CAP_CH2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf8)
-/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
- *  When set, capture on channel 2 is enabled
- */
-#define MCPWM_CAP2_EN    (BIT(0))
-#define MCPWM_CAP2_EN_M  (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S)
-#define MCPWM_CAP2_EN_V  0x00000001U
-#define MCPWM_CAP2_EN_S  0
-/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0;
- *  Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable
- *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
- *  edge.
- */
-#define MCPWM_CAP2_MODE    0x00000003U
-#define MCPWM_CAP2_MODE_M  (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S)
-#define MCPWM_CAP2_MODE_V  0x00000003U
-#define MCPWM_CAP2_MODE_S  1
-/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
- *  Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
- *  1
- */
-#define MCPWM_CAP2_PRESCALE    0x000000FFU
-#define MCPWM_CAP2_PRESCALE_M  (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S)
-#define MCPWM_CAP2_PRESCALE_V  0x000000FFU
-#define MCPWM_CAP2_PRESCALE_S  3
-/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0;
- *  when set, CAP2 form GPIO matrix is inverted before prescale
- */
-#define MCPWM_CAP2_IN_INVERT    (BIT(11))
-#define MCPWM_CAP2_IN_INVERT_M  (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S)
-#define MCPWM_CAP2_IN_INVERT_V  0x00000001U
-#define MCPWM_CAP2_IN_INVERT_S  11
-/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0;
- *  Write 1 will trigger a software forced capture on channel 2
- */
-#define MCPWM_CAP2_SW    (BIT(12))
-#define MCPWM_CAP2_SW_M  (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S)
-#define MCPWM_CAP2_SW_V  0x00000001U
-#define MCPWM_CAP2_SW_S  12
-
-/** MCPWM_CAP_CH0_REG register
- *  ch0 capture value status register
- */
-#define MCPWM_CAP_CH0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xfc)
-/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 0
- */
-#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
-#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP0_VALUE_S  0
-
-/** MCPWM_CAP_CH1_REG register
- *  ch1 capture value status register
- */
-#define MCPWM_CAP_CH1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x100)
-/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 1
- */
-#define MCPWM_CAP1_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP1_VALUE_M  (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S)
-#define MCPWM_CAP1_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP1_VALUE_S  0
-
-/** MCPWM_CAP_CH2_REG register
- *  ch2 capture value status register
- */
-#define MCPWM_CAP_CH2_REG(i) (DR_REG_MCPWM_BASE(i) + 0x104)
-/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
- *  Value of last capture on channel 2
- */
-#define MCPWM_CAP2_VALUE    0xFFFFFFFFU
-#define MCPWM_CAP2_VALUE_M  (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S)
-#define MCPWM_CAP2_VALUE_V  0xFFFFFFFFU
-#define MCPWM_CAP2_VALUE_S  0
-
-/** MCPWM_CAP_STATUS_REG register
- *  Edge of last capture trigger
- */
-#define MCPWM_CAP_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x108)
-/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
- *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP0_EDGE    (BIT(0))
-#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
-#define MCPWM_CAP0_EDGE_V  0x00000001U
-#define MCPWM_CAP0_EDGE_S  0
-/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
- *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP1_EDGE    (BIT(1))
-#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
-#define MCPWM_CAP1_EDGE_V  0x00000001U
-#define MCPWM_CAP1_EDGE_S  1
-/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
- *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
- */
-#define MCPWM_CAP2_EDGE    (BIT(2))
-#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
-#define MCPWM_CAP2_EDGE_V  0x00000001U
-#define MCPWM_CAP2_EDGE_S  2
-
-/** MCPWM_UPDATE_CFG_REG register
- *  Enable update.
- */
-#define MCPWM_UPDATE_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10c)
-/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
- *  The global enable of update of all active registers in MCPWM module
- */
-#define MCPWM_GLOBAL_UP_EN    (BIT(0))
-#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
-#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
-#define MCPWM_GLOBAL_UP_EN_S  0
-/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of all active
- *  registers in MCPWM module
- */
-#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
-#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
-#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
-#define MCPWM_GLOBAL_FORCE_UP_S  1
-/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
- *  are enabled
- */
-#define MCPWM_OP0_UP_EN    (BIT(2))
-#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
-#define MCPWM_OP0_UP_EN_V  0x00000001U
-#define MCPWM_OP0_UP_EN_S  2
-/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 0
- */
-#define MCPWM_OP0_FORCE_UP    (BIT(3))
-#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
-#define MCPWM_OP0_FORCE_UP_V  0x00000001U
-#define MCPWM_OP0_FORCE_UP_S  3
-/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
- *  are enabled
- */
-#define MCPWM_OP1_UP_EN    (BIT(4))
-#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
-#define MCPWM_OP1_UP_EN_V  0x00000001U
-#define MCPWM_OP1_UP_EN_S  4
-/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 1
- */
-#define MCPWM_OP1_FORCE_UP    (BIT(5))
-#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
-#define MCPWM_OP1_FORCE_UP_V  0x00000001U
-#define MCPWM_OP1_FORCE_UP_S  5
-/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
- *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
- *  are enabled
- */
-#define MCPWM_OP2_UP_EN    (BIT(6))
-#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
-#define MCPWM_OP2_UP_EN_V  0x00000001U
-#define MCPWM_OP2_UP_EN_S  6
-/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
- *  a toggle (software invert its value) will trigger a forced update of active
- *  registers in PWM operator 2
- */
-#define MCPWM_OP2_FORCE_UP    (BIT(7))
-#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
-#define MCPWM_OP2_FORCE_UP_V  0x00000001U
-#define MCPWM_OP2_FORCE_UP_S  7
-
-/** MCPWM_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define MCPWM_INT_ENA_REG(i) (DR_REG_MCPWM_BASE(i) + 0x110)
-/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
-#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ENA_S  0
-/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
-#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ENA_S  1
-/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  The enable bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
-#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ENA_S  2
-/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
-#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
-/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
-#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
-/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
-#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
-/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
-#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ENA_S  6
-/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
-#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ENA_S  7
-/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
-#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ENA_S  8
-/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  The enable bit for the interrupt triggered when fault_event0 starts.
- */
-#define MCPWM_FAULT0_INT_ENA    (BIT(9))
-#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
-#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_INT_ENA_S  9
-/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  The enable bit for the interrupt triggered when fault_event1 starts.
- */
-#define MCPWM_FAULT1_INT_ENA    (BIT(10))
-#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
-#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_INT_ENA_S  10
-/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  The enable bit for the interrupt triggered when fault_event2 starts.
- */
-#define MCPWM_FAULT2_INT_ENA    (BIT(11))
-#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
-#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_INT_ENA_S  11
-/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  The enable bit for the interrupt triggered when fault_event0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
-#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ENA_S  12
-/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  The enable bit for the interrupt triggered when fault_event1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
-#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ENA_S  13
-/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  The enable bit for the interrupt triggered when fault_event2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
-#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ENA_S  14
-/** MCPWM_OP0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_OP0_TEA_INT_ENA    (BIT(15))
-#define MCPWM_OP0_TEA_INT_ENA_M  (MCPWM_OP0_TEA_INT_ENA_V << MCPWM_OP0_TEA_INT_ENA_S)
-#define MCPWM_OP0_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_OP0_TEA_INT_ENA_S  15
-/** MCPWM_OP1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_OP1_TEA_INT_ENA    (BIT(16))
-#define MCPWM_OP1_TEA_INT_ENA_M  (MCPWM_OP1_TEA_INT_ENA_V << MCPWM_OP1_TEA_INT_ENA_S)
-#define MCPWM_OP1_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_OP1_TEA_INT_ENA_S  16
-/** MCPWM_OP2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_OP2_TEA_INT_ENA    (BIT(17))
-#define MCPWM_OP2_TEA_INT_ENA_M  (MCPWM_OP2_TEA_INT_ENA_V << MCPWM_OP2_TEA_INT_ENA_S)
-#define MCPWM_OP2_TEA_INT_ENA_V  0x00000001U
-#define MCPWM_OP2_TEA_INT_ENA_S  17
-/** MCPWM_OP0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_OP0_TEB_INT_ENA    (BIT(18))
-#define MCPWM_OP0_TEB_INT_ENA_M  (MCPWM_OP0_TEB_INT_ENA_V << MCPWM_OP0_TEB_INT_ENA_S)
-#define MCPWM_OP0_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_OP0_TEB_INT_ENA_S  18
-/** MCPWM_OP1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_OP1_TEB_INT_ENA    (BIT(19))
-#define MCPWM_OP1_TEB_INT_ENA_M  (MCPWM_OP1_TEB_INT_ENA_V << MCPWM_OP1_TEB_INT_ENA_S)
-#define MCPWM_OP1_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_OP1_TEB_INT_ENA_S  19
-/** MCPWM_OP2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
- *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_OP2_TEB_INT_ENA    (BIT(20))
-#define MCPWM_OP2_TEB_INT_ENA_M  (MCPWM_OP2_TEB_INT_ENA_V << MCPWM_OP2_TEB_INT_ENA_S)
-#define MCPWM_OP2_TEB_INT_ENA_V  0x00000001U
-#define MCPWM_OP2_TEB_INT_ENA_S  20
-/** MCPWM_FH0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
- */
-#define MCPWM_FH0_CBC_INT_ENA    (BIT(21))
-#define MCPWM_FH0_CBC_INT_ENA_M  (MCPWM_FH0_CBC_INT_ENA_V << MCPWM_FH0_CBC_INT_ENA_S)
-#define MCPWM_FH0_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_FH0_CBC_INT_ENA_S  21
-/** MCPWM_FH1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
- */
-#define MCPWM_FH1_CBC_INT_ENA    (BIT(22))
-#define MCPWM_FH1_CBC_INT_ENA_M  (MCPWM_FH1_CBC_INT_ENA_V << MCPWM_FH1_CBC_INT_ENA_S)
-#define MCPWM_FH1_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_FH1_CBC_INT_ENA_S  22
-/** MCPWM_FH2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
- *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
- */
-#define MCPWM_FH2_CBC_INT_ENA    (BIT(23))
-#define MCPWM_FH2_CBC_INT_ENA_M  (MCPWM_FH2_CBC_INT_ENA_V << MCPWM_FH2_CBC_INT_ENA_S)
-#define MCPWM_FH2_CBC_INT_ENA_V  0x00000001U
-#define MCPWM_FH2_CBC_INT_ENA_S  23
-/** MCPWM_FH0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_FH0_OST_INT_ENA    (BIT(24))
-#define MCPWM_FH0_OST_INT_ENA_M  (MCPWM_FH0_OST_INT_ENA_V << MCPWM_FH0_OST_INT_ENA_S)
-#define MCPWM_FH0_OST_INT_ENA_V  0x00000001U
-#define MCPWM_FH0_OST_INT_ENA_S  24
-/** MCPWM_FH1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_FH1_OST_INT_ENA    (BIT(25))
-#define MCPWM_FH1_OST_INT_ENA_M  (MCPWM_FH1_OST_INT_ENA_V << MCPWM_FH1_OST_INT_ENA_S)
-#define MCPWM_FH1_OST_INT_ENA_V  0x00000001U
-#define MCPWM_FH1_OST_INT_ENA_S  25
-/** MCPWM_FH2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
- *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_FH2_OST_INT_ENA    (BIT(26))
-#define MCPWM_FH2_OST_INT_ENA_M  (MCPWM_FH2_OST_INT_ENA_V << MCPWM_FH2_OST_INT_ENA_S)
-#define MCPWM_FH2_OST_INT_ENA_V  0x00000001U
-#define MCPWM_FH2_OST_INT_ENA_S  26
-/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_ENA    (BIT(27))
-#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
-#define MCPWM_CAP0_INT_ENA_V  0x00000001U
-#define MCPWM_CAP0_INT_ENA_S  27
-/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_ENA    (BIT(28))
-#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
-#define MCPWM_CAP1_INT_ENA_V  0x00000001U
-#define MCPWM_CAP1_INT_ENA_S  28
-/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
- *  The enable bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_ENA    (BIT(29))
-#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
-#define MCPWM_CAP2_INT_ENA_V  0x00000001U
-#define MCPWM_CAP2_INT_ENA_S  29
-
-/** MCPWM_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define MCPWM_INT_RAW_REG(i) (DR_REG_MCPWM_BASE(i) + 0x114)
-/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
-#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_RAW_S  0
-/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
-#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_RAW_S  1
-/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  The raw status bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
-#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_RAW_S  2
-/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
-#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
-/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
-#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
-/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
-#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
-/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
-#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_RAW_S  6
-/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
-#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_RAW_S  7
-/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
-#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_RAW_S  8
-/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  The raw status bit for the interrupt triggered when fault_event0 starts.
- */
-#define MCPWM_FAULT0_INT_RAW    (BIT(9))
-#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
-#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_INT_RAW_S  9
-/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  The raw status bit for the interrupt triggered when fault_event1 starts.
- */
-#define MCPWM_FAULT1_INT_RAW    (BIT(10))
-#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
-#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_INT_RAW_S  10
-/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  The raw status bit for the interrupt triggered when fault_event2 starts.
- */
-#define MCPWM_FAULT2_INT_RAW    (BIT(11))
-#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
-#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_INT_RAW_S  11
-/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  The raw status bit for the interrupt triggered when fault_event0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
-#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_RAW_S  12
-/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  The raw status bit for the interrupt triggered when fault_event1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
-#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_RAW_S  13
-/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  The raw status bit for the interrupt triggered when fault_event2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
-#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_RAW_S  14
-/** MCPWM_OP0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_OP0_TEA_INT_RAW    (BIT(15))
-#define MCPWM_OP0_TEA_INT_RAW_M  (MCPWM_OP0_TEA_INT_RAW_V << MCPWM_OP0_TEA_INT_RAW_S)
-#define MCPWM_OP0_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_OP0_TEA_INT_RAW_S  15
-/** MCPWM_OP1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_OP1_TEA_INT_RAW    (BIT(16))
-#define MCPWM_OP1_TEA_INT_RAW_M  (MCPWM_OP1_TEA_INT_RAW_V << MCPWM_OP1_TEA_INT_RAW_S)
-#define MCPWM_OP1_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_OP1_TEA_INT_RAW_S  16
-/** MCPWM_OP2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_OP2_TEA_INT_RAW    (BIT(17))
-#define MCPWM_OP2_TEA_INT_RAW_M  (MCPWM_OP2_TEA_INT_RAW_V << MCPWM_OP2_TEA_INT_RAW_S)
-#define MCPWM_OP2_TEA_INT_RAW_V  0x00000001U
-#define MCPWM_OP2_TEA_INT_RAW_S  17
-/** MCPWM_OP0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_OP0_TEB_INT_RAW    (BIT(18))
-#define MCPWM_OP0_TEB_INT_RAW_M  (MCPWM_OP0_TEB_INT_RAW_V << MCPWM_OP0_TEB_INT_RAW_S)
-#define MCPWM_OP0_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_OP0_TEB_INT_RAW_S  18
-/** MCPWM_OP1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_OP1_TEB_INT_RAW    (BIT(19))
-#define MCPWM_OP1_TEB_INT_RAW_M  (MCPWM_OP1_TEB_INT_RAW_V << MCPWM_OP1_TEB_INT_RAW_S)
-#define MCPWM_OP1_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_OP1_TEB_INT_RAW_S  19
-/** MCPWM_OP2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
- *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_OP2_TEB_INT_RAW    (BIT(20))
-#define MCPWM_OP2_TEB_INT_RAW_M  (MCPWM_OP2_TEB_INT_RAW_V << MCPWM_OP2_TEB_INT_RAW_S)
-#define MCPWM_OP2_TEB_INT_RAW_V  0x00000001U
-#define MCPWM_OP2_TEB_INT_RAW_S  20
-/** MCPWM_FH0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM0.
- */
-#define MCPWM_FH0_CBC_INT_RAW    (BIT(21))
-#define MCPWM_FH0_CBC_INT_RAW_M  (MCPWM_FH0_CBC_INT_RAW_V << MCPWM_FH0_CBC_INT_RAW_S)
-#define MCPWM_FH0_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_FH0_CBC_INT_RAW_S  21
-/** MCPWM_FH1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM1.
- */
-#define MCPWM_FH1_CBC_INT_RAW    (BIT(22))
-#define MCPWM_FH1_CBC_INT_RAW_M  (MCPWM_FH1_CBC_INT_RAW_V << MCPWM_FH1_CBC_INT_RAW_S)
-#define MCPWM_FH1_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_FH1_CBC_INT_RAW_S  22
-/** MCPWM_FH2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
- *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM2.
- */
-#define MCPWM_FH2_CBC_INT_RAW    (BIT(23))
-#define MCPWM_FH2_CBC_INT_RAW_M  (MCPWM_FH2_CBC_INT_RAW_V << MCPWM_FH2_CBC_INT_RAW_S)
-#define MCPWM_FH2_CBC_INT_RAW_V  0x00000001U
-#define MCPWM_FH2_CBC_INT_RAW_S  23
-/** MCPWM_FH0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_FH0_OST_INT_RAW    (BIT(24))
-#define MCPWM_FH0_OST_INT_RAW_M  (MCPWM_FH0_OST_INT_RAW_V << MCPWM_FH0_OST_INT_RAW_S)
-#define MCPWM_FH0_OST_INT_RAW_V  0x00000001U
-#define MCPWM_FH0_OST_INT_RAW_S  24
-/** MCPWM_FH1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_FH1_OST_INT_RAW    (BIT(25))
-#define MCPWM_FH1_OST_INT_RAW_M  (MCPWM_FH1_OST_INT_RAW_V << MCPWM_FH1_OST_INT_RAW_S)
-#define MCPWM_FH1_OST_INT_RAW_V  0x00000001U
-#define MCPWM_FH1_OST_INT_RAW_S  25
-/** MCPWM_FH2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
- *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_FH2_OST_INT_RAW    (BIT(26))
-#define MCPWM_FH2_OST_INT_RAW_M  (MCPWM_FH2_OST_INT_RAW_V << MCPWM_FH2_OST_INT_RAW_S)
-#define MCPWM_FH2_OST_INT_RAW_V  0x00000001U
-#define MCPWM_FH2_OST_INT_RAW_S  26
-/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_RAW    (BIT(27))
-#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
-#define MCPWM_CAP0_INT_RAW_V  0x00000001U
-#define MCPWM_CAP0_INT_RAW_S  27
-/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_RAW    (BIT(28))
-#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
-#define MCPWM_CAP1_INT_RAW_V  0x00000001U
-#define MCPWM_CAP1_INT_RAW_S  28
-/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
- *  The raw status bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_RAW    (BIT(29))
-#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
-#define MCPWM_CAP2_INT_RAW_V  0x00000001U
-#define MCPWM_CAP2_INT_RAW_S  29
-
-/** MCPWM_INT_ST_REG register
- *  Masked interrupt status
- */
-#define MCPWM_INT_ST_REG(i) (DR_REG_MCPWM_BASE(i) + 0x118)
-/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
-#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_ST_S  0
-/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
-#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_ST_S  1
-/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
- *  The masked status bit for the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
-#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_ST_S  2
-/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
-#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_ST_S  3
-/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
-#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_ST_S  4
-/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
-#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_ST_S  5
-/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
-#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_ST_S  6
-/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
-#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_ST_S  7
-/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
-#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_ST_S  8
-/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
- *  The masked status bit for the interrupt triggered when fault_event0 starts.
- */
-#define MCPWM_FAULT0_INT_ST    (BIT(9))
-#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
-#define MCPWM_FAULT0_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_INT_ST_S  9
-/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
- *  The masked status bit for the interrupt triggered when fault_event1 starts.
- */
-#define MCPWM_FAULT1_INT_ST    (BIT(10))
-#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
-#define MCPWM_FAULT1_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_INT_ST_S  10
-/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
- *  The masked status bit for the interrupt triggered when fault_event2 starts.
- */
-#define MCPWM_FAULT2_INT_ST    (BIT(11))
-#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
-#define MCPWM_FAULT2_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_INT_ST_S  11
-/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
- *  The masked status bit for the interrupt triggered when fault_event0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
-#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_ST_S  12
-/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
- *  The masked status bit for the interrupt triggered when fault_event1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
-#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_ST_S  13
-/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
- *  The masked status bit for the interrupt triggered when fault_event2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
-#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_ST_S  14
-/** MCPWM_OP0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_OP0_TEA_INT_ST    (BIT(15))
-#define MCPWM_OP0_TEA_INT_ST_M  (MCPWM_OP0_TEA_INT_ST_V << MCPWM_OP0_TEA_INT_ST_S)
-#define MCPWM_OP0_TEA_INT_ST_V  0x00000001U
-#define MCPWM_OP0_TEA_INT_ST_S  15
-/** MCPWM_OP1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_OP1_TEA_INT_ST    (BIT(16))
-#define MCPWM_OP1_TEA_INT_ST_M  (MCPWM_OP1_TEA_INT_ST_V << MCPWM_OP1_TEA_INT_ST_S)
-#define MCPWM_OP1_TEA_INT_ST_V  0x00000001U
-#define MCPWM_OP1_TEA_INT_ST_S  16
-/** MCPWM_OP2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_OP2_TEA_INT_ST    (BIT(17))
-#define MCPWM_OP2_TEA_INT_ST_M  (MCPWM_OP2_TEA_INT_ST_V << MCPWM_OP2_TEA_INT_ST_S)
-#define MCPWM_OP2_TEA_INT_ST_V  0x00000001U
-#define MCPWM_OP2_TEA_INT_ST_S  17
-/** MCPWM_OP0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_OP0_TEB_INT_ST    (BIT(18))
-#define MCPWM_OP0_TEB_INT_ST_M  (MCPWM_OP0_TEB_INT_ST_V << MCPWM_OP0_TEB_INT_ST_S)
-#define MCPWM_OP0_TEB_INT_ST_V  0x00000001U
-#define MCPWM_OP0_TEB_INT_ST_S  18
-/** MCPWM_OP1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_OP1_TEB_INT_ST    (BIT(19))
-#define MCPWM_OP1_TEB_INT_ST_M  (MCPWM_OP1_TEB_INT_ST_V << MCPWM_OP1_TEB_INT_ST_S)
-#define MCPWM_OP1_TEB_INT_ST_V  0x00000001U
-#define MCPWM_OP1_TEB_INT_ST_S  19
-/** MCPWM_OP2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
- *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_OP2_TEB_INT_ST    (BIT(20))
-#define MCPWM_OP2_TEB_INT_ST_M  (MCPWM_OP2_TEB_INT_ST_V << MCPWM_OP2_TEB_INT_ST_S)
-#define MCPWM_OP2_TEB_INT_ST_V  0x00000001U
-#define MCPWM_OP2_TEB_INT_ST_S  20
-/** MCPWM_FH0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM0.
- */
-#define MCPWM_FH0_CBC_INT_ST    (BIT(21))
-#define MCPWM_FH0_CBC_INT_ST_M  (MCPWM_FH0_CBC_INT_ST_V << MCPWM_FH0_CBC_INT_ST_S)
-#define MCPWM_FH0_CBC_INT_ST_V  0x00000001U
-#define MCPWM_FH0_CBC_INT_ST_S  21
-/** MCPWM_FH1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM1.
- */
-#define MCPWM_FH1_CBC_INT_ST    (BIT(22))
-#define MCPWM_FH1_CBC_INT_ST_M  (MCPWM_FH1_CBC_INT_ST_V << MCPWM_FH1_CBC_INT_ST_S)
-#define MCPWM_FH1_CBC_INT_ST_V  0x00000001U
-#define MCPWM_FH1_CBC_INT_ST_S  22
-/** MCPWM_FH2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
- *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
- *  on PWM2.
- */
-#define MCPWM_FH2_CBC_INT_ST    (BIT(23))
-#define MCPWM_FH2_CBC_INT_ST_M  (MCPWM_FH2_CBC_INT_ST_V << MCPWM_FH2_CBC_INT_ST_S)
-#define MCPWM_FH2_CBC_INT_ST_V  0x00000001U
-#define MCPWM_FH2_CBC_INT_ST_S  23
-/** MCPWM_FH0_OST_INT_ST : RO; bitpos: [24]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_FH0_OST_INT_ST    (BIT(24))
-#define MCPWM_FH0_OST_INT_ST_M  (MCPWM_FH0_OST_INT_ST_V << MCPWM_FH0_OST_INT_ST_S)
-#define MCPWM_FH0_OST_INT_ST_V  0x00000001U
-#define MCPWM_FH0_OST_INT_ST_S  24
-/** MCPWM_FH1_OST_INT_ST : RO; bitpos: [25]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_FH1_OST_INT_ST    (BIT(25))
-#define MCPWM_FH1_OST_INT_ST_M  (MCPWM_FH1_OST_INT_ST_V << MCPWM_FH1_OST_INT_ST_S)
-#define MCPWM_FH1_OST_INT_ST_V  0x00000001U
-#define MCPWM_FH1_OST_INT_ST_S  25
-/** MCPWM_FH2_OST_INT_ST : RO; bitpos: [26]; default: 0;
- *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_FH2_OST_INT_ST    (BIT(26))
-#define MCPWM_FH2_OST_INT_ST_M  (MCPWM_FH2_OST_INT_ST_V << MCPWM_FH2_OST_INT_ST_S)
-#define MCPWM_FH2_OST_INT_ST_V  0x00000001U
-#define MCPWM_FH2_OST_INT_ST_S  26
-/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_ST    (BIT(27))
-#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
-#define MCPWM_CAP0_INT_ST_V  0x00000001U
-#define MCPWM_CAP0_INT_ST_S  27
-/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_ST    (BIT(28))
-#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
-#define MCPWM_CAP1_INT_ST_V  0x00000001U
-#define MCPWM_CAP1_INT_ST_S  28
-/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
- *  The masked status bit for the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_ST    (BIT(29))
-#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
-#define MCPWM_CAP2_INT_ST_V  0x00000001U
-#define MCPWM_CAP2_INT_ST_S  29
-
-/** MCPWM_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define MCPWM_INT_CLR_REG(i) (DR_REG_MCPWM_BASE(i) + 0x11c)
-/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 0 stops.
- */
-#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
-#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
-#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_STOP_INT_CLR_S  0
-/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 1 stops.
- */
-#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
-#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
-#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_STOP_INT_CLR_S  1
-/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear the interrupt triggered when the timer 2 stops.
- */
-#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
-#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
-#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_STOP_INT_CLR_S  2
-/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
- */
-#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
-#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
-#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
-/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
- */
-#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
-#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
-#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
-/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
- */
-#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
-#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
-#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
-/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
- */
-#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
-#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
-#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER0_TEP_INT_CLR_S  6
-/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
- */
-#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
-#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
-#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER1_TEP_INT_CLR_S  7
-/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
- */
-#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
-#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
-#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
-#define MCPWM_TIMER2_TEP_INT_CLR_S  8
-/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the interrupt triggered when fault_event0 starts.
- */
-#define MCPWM_FAULT0_INT_CLR    (BIT(9))
-#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
-#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_INT_CLR_S  9
-/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the interrupt triggered when fault_event1 starts.
- */
-#define MCPWM_FAULT1_INT_CLR    (BIT(10))
-#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
-#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_INT_CLR_S  10
-/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the interrupt triggered when fault_event2 starts.
- */
-#define MCPWM_FAULT2_INT_CLR    (BIT(11))
-#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
-#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_INT_CLR_S  11
-/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the interrupt triggered when fault_event0 ends.
- */
-#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
-#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
-#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT0_CLR_INT_CLR_S  12
-/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the interrupt triggered when fault_event1 ends.
- */
-#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
-#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
-#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT1_CLR_INT_CLR_S  13
-/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the interrupt triggered when fault_event2 ends.
- */
-#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
-#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
-#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
-#define MCPWM_FAULT2_CLR_INT_CLR_S  14
-/** MCPWM_OP0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
- */
-#define MCPWM_OP0_TEA_INT_CLR    (BIT(15))
-#define MCPWM_OP0_TEA_INT_CLR_M  (MCPWM_OP0_TEA_INT_CLR_V << MCPWM_OP0_TEA_INT_CLR_S)
-#define MCPWM_OP0_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_OP0_TEA_INT_CLR_S  15
-/** MCPWM_OP1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
- */
-#define MCPWM_OP1_TEA_INT_CLR    (BIT(16))
-#define MCPWM_OP1_TEA_INT_CLR_M  (MCPWM_OP1_TEA_INT_CLR_V << MCPWM_OP1_TEA_INT_CLR_S)
-#define MCPWM_OP1_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_OP1_TEA_INT_CLR_S  16
-/** MCPWM_OP2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
- */
-#define MCPWM_OP2_TEA_INT_CLR    (BIT(17))
-#define MCPWM_OP2_TEA_INT_CLR_M  (MCPWM_OP2_TEA_INT_CLR_V << MCPWM_OP2_TEA_INT_CLR_S)
-#define MCPWM_OP2_TEA_INT_CLR_V  0x00000001U
-#define MCPWM_OP2_TEA_INT_CLR_S  17
-/** MCPWM_OP0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
- */
-#define MCPWM_OP0_TEB_INT_CLR    (BIT(18))
-#define MCPWM_OP0_TEB_INT_CLR_M  (MCPWM_OP0_TEB_INT_CLR_V << MCPWM_OP0_TEB_INT_CLR_S)
-#define MCPWM_OP0_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_OP0_TEB_INT_CLR_S  18
-/** MCPWM_OP1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
- */
-#define MCPWM_OP1_TEB_INT_CLR    (BIT(19))
-#define MCPWM_OP1_TEB_INT_CLR_M  (MCPWM_OP1_TEB_INT_CLR_V << MCPWM_OP1_TEB_INT_CLR_S)
-#define MCPWM_OP1_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_OP1_TEB_INT_CLR_S  19
-/** MCPWM_OP2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
- *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
- */
-#define MCPWM_OP2_TEB_INT_CLR    (BIT(20))
-#define MCPWM_OP2_TEB_INT_CLR_M  (MCPWM_OP2_TEB_INT_CLR_V << MCPWM_OP2_TEB_INT_CLR_S)
-#define MCPWM_OP2_TEB_INT_CLR_V  0x00000001U
-#define MCPWM_OP2_TEB_INT_CLR_S  20
-/** MCPWM_FH0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM0.
- */
-#define MCPWM_FH0_CBC_INT_CLR    (BIT(21))
-#define MCPWM_FH0_CBC_INT_CLR_M  (MCPWM_FH0_CBC_INT_CLR_V << MCPWM_FH0_CBC_INT_CLR_S)
-#define MCPWM_FH0_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_FH0_CBC_INT_CLR_S  21
-/** MCPWM_FH1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM1.
- */
-#define MCPWM_FH1_CBC_INT_CLR    (BIT(22))
-#define MCPWM_FH1_CBC_INT_CLR_M  (MCPWM_FH1_CBC_INT_CLR_V << MCPWM_FH1_CBC_INT_CLR_S)
-#define MCPWM_FH1_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_FH1_CBC_INT_CLR_S  22
-/** MCPWM_FH2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
- *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
- *  PWM2.
- */
-#define MCPWM_FH2_CBC_INT_CLR    (BIT(23))
-#define MCPWM_FH2_CBC_INT_CLR_M  (MCPWM_FH2_CBC_INT_CLR_V << MCPWM_FH2_CBC_INT_CLR_S)
-#define MCPWM_FH2_CBC_INT_CLR_V  0x00000001U
-#define MCPWM_FH2_CBC_INT_CLR_S  23
-/** MCPWM_FH0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
- */
-#define MCPWM_FH0_OST_INT_CLR    (BIT(24))
-#define MCPWM_FH0_OST_INT_CLR_M  (MCPWM_FH0_OST_INT_CLR_V << MCPWM_FH0_OST_INT_CLR_S)
-#define MCPWM_FH0_OST_INT_CLR_V  0x00000001U
-#define MCPWM_FH0_OST_INT_CLR_S  24
-/** MCPWM_FH1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
- */
-#define MCPWM_FH1_OST_INT_CLR    (BIT(25))
-#define MCPWM_FH1_OST_INT_CLR_M  (MCPWM_FH1_OST_INT_CLR_V << MCPWM_FH1_OST_INT_CLR_S)
-#define MCPWM_FH1_OST_INT_CLR_V  0x00000001U
-#define MCPWM_FH1_OST_INT_CLR_S  25
-/** MCPWM_FH2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
- *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
- */
-#define MCPWM_FH2_OST_INT_CLR    (BIT(26))
-#define MCPWM_FH2_OST_INT_CLR_M  (MCPWM_FH2_OST_INT_CLR_V << MCPWM_FH2_OST_INT_CLR_S)
-#define MCPWM_FH2_OST_INT_CLR_V  0x00000001U
-#define MCPWM_FH2_OST_INT_CLR_S  26
-/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 0.
- */
-#define MCPWM_CAP0_INT_CLR    (BIT(27))
-#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
-#define MCPWM_CAP0_INT_CLR_V  0x00000001U
-#define MCPWM_CAP0_INT_CLR_S  27
-/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 1.
- */
-#define MCPWM_CAP1_INT_CLR    (BIT(28))
-#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
-#define MCPWM_CAP1_INT_CLR_V  0x00000001U
-#define MCPWM_CAP1_INT_CLR_S  28
-/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
- *  Set this bit to clear the interrupt triggered by capture on channel 2.
- */
-#define MCPWM_CAP2_INT_CLR    (BIT(29))
-#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
-#define MCPWM_CAP2_INT_CLR_V  0x00000001U
-#define MCPWM_CAP2_INT_CLR_S  29
-
-/** MCPWM_CLK_REG register
- *  MCPWM APB configuration register
- */
-#define MCPWM_CLK_REG(i) (DR_REG_MCPWM_BASE(i) + 0x120)
-/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
- *  Force clock on for this register file
- */
-#define MCPWM_CLK_EN    (BIT(0))
-#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
-#define MCPWM_CLK_EN_V  0x00000001U
-#define MCPWM_CLK_EN_S  0
-
-/** MCPWM_VERSION_REG register
- *  Version register.
- */
-#define MCPWM_VERSION_REG(i) (DR_REG_MCPWM_BASE(i) + 0x124)
-/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 34632240;
- *  Version of this register file
- */
-#define MCPWM_DATE    0x0FFFFFFFU
-#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
-#define MCPWM_DATE_V  0x0FFFFFFFU
-#define MCPWM_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/mcpwm_struct.h b/components/soc/esp32s3/include/soc/mcpwm_struct.h
deleted file mode 100644
index e2f4d32eba9..00000000000
--- a/components/soc/esp32s3/include/soc/mcpwm_struct.h
+++ /dev/null
@@ -1,1468 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Prescaler configuration */
-/** Type of clk_cfg register
- *  PWM clock prescaler register.
- */
-typedef union {
-    struct {
-        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
-         */
-        uint32_t clk_prescale: 8;
-        uint32_t reserved_8: 24;
-    };
-    uint32_t val;
-} mcpwm_clk_cfg_reg_t;
-
-
-/** Group: MCPWM Timer Configuration and status */
-/** Type of timer_cfg0 register
- *  PWM timer period and update method configuration register.
- */
-typedef union {
-    struct {
-        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
-         *  Configure the divisor of PT0_clk, takes effect when PWM timer stops and starts
-         *  agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1)
-         */
-        uint32_t timer_prescale: 8;
-        /** timer_period : R/W; bitpos: [23:8]; default: 255;
-         *  period shadow register of PWM timer
-         */
-        uint32_t timer_period: 16;
-        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
-         *  Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2:
-         *  sync, 3: TEZ or sync. TEZ here and below means timer equal zero event
-         */
-        uint32_t timer_period_upmethod: 2;
-        uint32_t reserved_26: 6;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg0_reg_t;
-
-/** Type of timer_cfg1 register
- *  PWM timer working mode and start/stop control configuration register.
- */
-typedef union {
-    struct {
-        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
-         *  PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1:
-         *  if timer starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer
-         *  starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP
-         *  here and below means the event that happens when the timer equals to period
-         */
-        uint32_t timer_start: 3;
-        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
-         *  PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
-         *  mode
-         */
-        uint32_t timer_mod: 2;
-        uint32_t reserved_5: 27;
-    };
-    uint32_t val;
-} mcpwm_timer_cfg1_reg_t;
-
-/** Type of timer_sync register
- *  PWM timer sync function configuration register.
- */
-typedef union {
-    struct {
-        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
-         *  When set, timer reloading with phase on sync input event is enabled.
-         */
-        uint32_t timer_synci_en: 1;
-        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
-         *  Toggling this bit will trigger a software sync.
-         */
-        uint32_t timer_sync_sw: 1;
-        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
-         *  PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
-         *  generate when toggling the reg_timer_sync_sw bit
-         */
-        uint32_t timer_synco_sel: 2;
-        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
-         *  phase for timer reload on sync event
-         */
-        uint32_t timer_phase: 16;
-        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
-         *  Configure the PWM timer's direction at the time sync event occurs when timer mode
-         *  is up-down mode: 0-increase,1-decrease
-         */
-        uint32_t timer_phase_direction: 1;
-        uint32_t reserved_21: 11;
-    };
-    uint32_t val;
-} mcpwm_timer_sync_reg_t;
-
-/** Type of timer_status register
- *  PWM timer status register.
- */
-typedef union {
-    struct {
-        /** timer_value : RO; bitpos: [15:0]; default: 0;
-         *  current PWM timer counter value
-         */
-        uint32_t timer_value: 16;
-        /** timer_direction : RO; bitpos: [16]; default: 0;
-         *  current PWM timer counter direction, 0: increment 1: decrement
-         */
-        uint32_t timer_direction: 1;
-        uint32_t reserved_17: 15;
-    };
-    uint32_t val;
-} mcpwm_timer_status_reg_t;
-
-
-/** Group: Common configuration for MCPWM timers */
-/** Type of timer_synci_cfg register
- *  Synchronization input selection for three PWM timers.
- */
-typedef union {
-    struct {
-        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
-         *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer0_syncisel: 3;
-        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
-         *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer1_syncisel: 3;
-        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
-         *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
-         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
-         *  SYNC2 from GPIO matrix, other values: no sync input selected
-         */
-        uint32_t timer2_syncisel: 3;
-        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
-         *  invert SYNC0 from GPIO matrix
-         */
-        uint32_t external_synci0_invert: 1;
-        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
-         *  invert SYNC1 from GPIO matrix
-         */
-        uint32_t external_synci1_invert: 1;
-        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
-         *  invert SYNC2 from GPIO matrix
-         */
-        uint32_t external_synci2_invert: 1;
-        uint32_t reserved_12: 20;
-    };
-    uint32_t val;
-} mcpwm_timer_synci_cfg_reg_t;
-
-/** Type of operator_timersel register
- *  Select specific timer for PWM operators.
- */
-typedef union {
-    struct {
-        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
-         *  Select which PWM timer is the timing reference for PWM operator0, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator0_timersel: 2;
-        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
-         *  Select which PWM timer is the timing reference for PWM operator1, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator1_timersel: 2;
-        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
-         *  Select which PWM timer is the timing reference for PWM operator2, 0: timer0, 1:
-         *  timer1, 2: timer2
-         */
-        uint32_t operator2_timersel: 2;
-        uint32_t reserved_6: 26;
-    };
-    uint32_t val;
-} mcpwm_operator_timersel_reg_t;
-
-
-/** Group: MCPWM Operator Configuration and Status */
-/** Type of gen_stmp_cfg register
- *  Transfer status and update method for time stamp registers A and B
- */
-typedef union {
-    struct {
-        /** gen_a_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for PWM generator time stamp A's active register. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
-         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
-         */
-        uint32_t gen_a_upmethod: 4;
-        /** gen_b_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Update method for PWM generator time stamp B's active register. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
-         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
-         */
-        uint32_t gen_b_upmethod: 4;
-        /** gen_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
-         *  Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is
-         *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
-         *  has been updated with shadow register latest value
-         */
-        uint32_t gen_a_shdw_full: 1;
-        /** gen_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
-         *  Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is
-         *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
-         *  has been updated with shadow register latest value
-         */
-        uint32_t gen_b_shdw_full: 1;
-        uint32_t reserved_10: 22;
-    };
-    uint32_t val;
-} mcpwm_gen_stmp_cfg_reg_t;
-
-/** Type of gen_tstmp register
- *  PWM generator shadow register for timer stamp
- */
-typedef union {
-    struct {
-        /** gen : R/W; bitpos: [15:0]; default: 0;
-         *  PWM generator time stamp's shadow register
-         */
-        uint32_t gen: 16;
-        uint32_t reserved_16: 16;
-    };
-    uint32_t val;
-} mcpwm_gen_tstmp_reg_t;
-
-/** Type of gen_cfg0 register
- *  PWM generator event T0 and T1 handling
- */
-typedef union {
-    struct {
-        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for PWM generator's active register of configuration. When all bits
-         *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
-         *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
-         */
-        uint32_t gen_cfg_upmethod: 4;
-        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
-         *  Source selection for PWM generator event_t0, take effect immediately, 0:
-         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
-         */
-        uint32_t gen_t0_sel: 3;
-        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
-         *  Source selection for PWM generator event_t1, take effect immediately, 0:
-         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
-         */
-        uint32_t gen_t1_sel: 3;
-        uint32_t reserved_10: 22;
-    };
-    uint32_t val;
-} mcpwm_gen_cfg0_reg_t;
-
-/** Type of gen_force register
- *  Permissives to force PWM0A and PWM0B outputs by software
- */
-typedef union {
-    struct {
-        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
-         *  Updating method for continuous software force of PWM generator0. When all bits are
-         *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
-         *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
-         *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
-         *  generated when the timer's value equals to that of register A/B.)
-         */
-        uint32_t gen_cntuforce_upmethod: 6;
-        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
-         *  Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled
-         */
-        uint32_t gen_a_cntuforce_mode: 2;
-        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
-         *  Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled
-         */
-        uint32_t gen_b_cntuforce_mode: 2;
-        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
-         *  Trigger of non-continuous immediate software-force event for PWM0A, a toggle will
-         *  trigger a force event.
-         */
-        uint32_t gen_a_nciforce: 1;
-        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
-         *  non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2:
-         *  high, 3: disabled
-         */
-        uint32_t gen_a_nciforce_mode: 2;
-        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
-         *  Trigger of non-continuous immediate software-force event for PWM0B, a toggle will
-         *  trigger a force event.
-         */
-        uint32_t gen_b_nciforce: 1;
-        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
-         *  non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2:
-         *  high, 3: disabled
-         */
-        uint32_t gen_b_nciforce_mode: 2;
-        uint32_t reserved_16: 16;
-    };
-    uint32_t val;
-} mcpwm_gen_force_reg_t;
-
-/** Type of generator register
- *  Actions triggered by events on PWM0A
- */
-typedef union {
-    struct {
-        /** gen_utez : R/W; bitpos: [1:0]; default: 0;
-         *  Action on PWM0A triggered by event TEZ when timer increasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_utez: 2;
-        /** gen_utep : R/W; bitpos: [3:2]; default: 0;
-         *  Action on PWM0A triggered by event TEP when timer increasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_utep: 2;
-        /** gen_utea : R/W; bitpos: [5:4]; default: 0;
-         *  Action on PWM0A triggered by event TEA when timer increasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_utea: 2;
-        /** gen_uteb : R/W; bitpos: [7:6]; default: 0;
-         *  Action on PWM0A triggered by event TEB when timer increasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_uteb: 2;
-        /** gen_ut0 : R/W; bitpos: [9:8]; default: 0;
-         *  Action on PWM0A triggered by event_t0 when timer increasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_ut0: 2;
-        /** gen_ut1 : R/W; bitpos: [11:10]; default: 0;
-         *  Action on PWM0A triggered by event_t1 when timer increasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_ut1: 2;
-        /** gen_dtez : R/W; bitpos: [13:12]; default: 0;
-         *  Action on PWM0A triggered by event TEZ when timer decreasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_dtez: 2;
-        /** gen_dtep : R/W; bitpos: [15:14]; default: 0;
-         *  Action on PWM0A triggered by event TEP when timer decreasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_dtep: 2;
-        /** gen_dtea : R/W; bitpos: [17:16]; default: 0;
-         *  Action on PWM0A triggered by event TEA when timer decreasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_dtea: 2;
-        /** gen_dteb : R/W; bitpos: [19:18]; default: 0;
-         *  Action on PWM0A triggered by event TEB when timer decreasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_dteb: 2;
-        /** gen_dt0 : R/W; bitpos: [21:20]; default: 0;
-         *  Action on PWM0A triggered by event_t0 when timer decreasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_dt0: 2;
-        /** gen_dt1 : R/W; bitpos: [23:22]; default: 0;
-         *  Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
-         *  2: high, 3: toggle
-         */
-        uint32_t gen_dt1: 2;
-        uint32_t reserved_24: 8;
-    };
-    uint32_t val;
-} mcpwm_gen_reg_t;
-
-/** Type of dt_cfg register
- *  PWM generator dead time type selection and configuration
- */
-typedef union {
-    struct {
-        /** dt_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
-         *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
-         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
-         *  bit3 is set to 1: disable the update
-         */
-        uint32_t dt_fed_upmethod: 4;
-        /** dt_red_upmethod : R/W; bitpos: [7:4]; default: 0;
-         *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
-         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
-         *  bit3 is set to 1: disable the update
-         */
-        uint32_t dt_red_upmethod: 4;
-        /** dt_deb_mode : R/W; bitpos: [8]; default: 0;
-         *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
-         *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
-         */
-        uint32_t dt_deb_mode: 1;
-        /** dt_a_outswap : R/W; bitpos: [9]; default: 0;
-         *  S6 in table
-         */
-        uint32_t dt_a_outswap: 1;
-        /** dt_b_outswap : R/W; bitpos: [10]; default: 0;
-         *  S7 in table
-         */
-        uint32_t dt_b_outswap: 1;
-        /** dt_red_insel : R/W; bitpos: [11]; default: 0;
-         *  S4 in table
-         */
-        uint32_t dt_red_insel: 1;
-        /** dt_fed_insel : R/W; bitpos: [12]; default: 0;
-         *  S5 in table
-         */
-        uint32_t dt_fed_insel: 1;
-        /** dt_red_outinvert : R/W; bitpos: [13]; default: 0;
-         *  S2 in table
-         */
-        uint32_t dt_red_outinvert: 1;
-        /** dt_fed_outinvert : R/W; bitpos: [14]; default: 0;
-         *  S3 in table
-         */
-        uint32_t dt_fed_outinvert: 1;
-        /** dt_a_outbypass : R/W; bitpos: [15]; default: 1;
-         *  S1 in table
-         */
-        uint32_t dt_a_outbypass: 1;
-        /** dt_b_outbypass : R/W; bitpos: [16]; default: 1;
-         *  S0 in table
-         */
-        uint32_t dt_b_outbypass: 1;
-        /** dt_clk_sel : R/W; bitpos: [17]; default: 0;
-         *  Dead time clock selection. 0: PWM_clk, 1: PT_clk
-         */
-        uint32_t dt_clk_sel: 1;
-        uint32_t reserved_18: 14;
-    };
-    uint32_t val;
-} mcpwm_dt_cfg_reg_t;
-
-/** Type of dt_fed_cfg register
- *  PWM generator shadow register for falling edge delay (FED).
- */
-typedef union {
-    struct {
-        /** dt_fed : R/W; bitpos: [15:0]; default: 0;
-         *  Shadow register for FED
-         */
-        uint32_t dt_fed: 16;
-        uint32_t reserved_16: 16;
-    };
-    uint32_t val;
-} mcpwm_dt_fed_cfg_reg_t;
-
-/** Type of dt_red_cfg register
- *  PWM generator shadow register for rising edge delay (RED).
- */
-typedef union {
-    struct {
-        /** dt_red : R/W; bitpos: [15:0]; default: 0;
-         *  Shadow register for RED
-         */
-        uint32_t dt_red: 16;
-        uint32_t reserved_16: 16;
-    };
-    uint32_t val;
-} mcpwm_dt_red_cfg_reg_t;
-
-/** Type of carrier_cfg register
- *  PWM generator carrier enable and configuratoin
- */
-typedef union {
-    struct {
-        /** carrier_en : R/W; bitpos: [0]; default: 0;
-         *  When set, carrier function is enabled. When cleared, carrier is bypassed
-         */
-        uint32_t carrier_en: 1;
-        /** carrier_prescale : R/W; bitpos: [4:1]; default: 0;
-         *  PWM carrier clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
-         *  (PWM_CARRIER_PRESCALE + 1)
-         */
-        uint32_t carrier_prescale: 4;
-        /** carrier_duty : R/W; bitpos: [7:5]; default: 0;
-         *  carrier duty selection. Duty = PWM_CARRIER_DUTY / 8
-         */
-        uint32_t carrier_duty: 3;
-        /** carrier_oshtwth : R/W; bitpos: [11:8]; default: 0;
-         *  width of the first pulse in number of periods of the carrier
-         */
-        uint32_t carrier_oshtwth: 4;
-        /** carrier_out_invert : R/W; bitpos: [12]; default: 0;
-         *  when set, invert the output of PWM0A and PWM0B for this submodule
-         */
-        uint32_t carrier_out_invert: 1;
-        /** carrier_in_invert : R/W; bitpos: [13]; default: 0;
-         *  when set, invert the input of PWM0A and PWM0B for this submodule
-         */
-        uint32_t carrier_in_invert: 1;
-        uint32_t reserved_14: 18;
-    };
-    uint32_t val;
-} mcpwm_carrier_cfg_reg_t;
-
-/** Type of fh_cfg0 register
- *  Actions on PWM0A and PWM0B trip events
- */
-typedef union {
-    struct {
-        /** fh_sw_cbc : R/W; bitpos: [0]; default: 0;
-         *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t fh_sw_cbc: 1;
-        /** fh_f2_cbc : R/W; bitpos: [1]; default: 0;
-         *  fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t fh_f2_cbc: 1;
-        /** fh_f1_cbc : R/W; bitpos: [2]; default: 0;
-         *  fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t fh_f1_cbc: 1;
-        /** fh_f0_cbc : R/W; bitpos: [3]; default: 0;
-         *  fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
-         */
-        uint32_t fh_f0_cbc: 1;
-        /** fh_sw_ost : R/W; bitpos: [4]; default: 0;
-         *  Enable register for software force one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t fh_sw_ost: 1;
-        /** fh_f2_ost : R/W; bitpos: [5]; default: 0;
-         *  fault_event2 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t fh_f2_ost: 1;
-        /** fh_f1_ost : R/W; bitpos: [6]; default: 0;
-         *  fault_event1 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t fh_f1_ost: 1;
-        /** fh_f0_ost : R/W; bitpos: [7]; default: 0;
-         *  fault_event0 will trigger one-shot mode action. 0: disable, 1: enable
-         */
-        uint32_t fh_f0_ost: 1;
-        /** fh_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
-         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t fh_a_cbc_d: 2;
-        /** fh_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
-         *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t fh_a_cbc_u: 2;
-        /** fh_a_ost_d : R/W; bitpos: [13:12]; default: 0;
-         *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t fh_a_ost_d: 2;
-        /** fh_a_ost_u : R/W; bitpos: [15:14]; default: 0;
-         *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t fh_a_ost_u: 2;
-        /** fh_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
-         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t fh_b_cbc_d: 2;
-        /** fh_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
-         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
-         *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
-         */
-        uint32_t fh_b_cbc_u: 2;
-        /** fh_b_ost_d : R/W; bitpos: [21:20]; default: 0;
-         *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t fh_b_ost_d: 2;
-        /** fh_b_ost_u : R/W; bitpos: [23:22]; default: 0;
-         *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
-         *  do nothing, 1: force low, 2: force high, 3: toggle
-         */
-        uint32_t fh_b_ost_u: 2;
-        uint32_t reserved_24: 8;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg0_reg_t;
-
-/** Type of fh_cfg1 register
- *  Software triggers for fault handler actions
- */
-typedef union {
-    struct {
-        /** fh_clr_ost : R/W; bitpos: [0]; default: 0;
-         *  a rising edge will clear on going one-shot mode action
-         */
-        uint32_t fh_clr_ost: 1;
-        /** fh_cbcpulse : R/W; bitpos: [2:1]; default: 0;
-         *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
-         *  when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when
-         *  bit0 and bit1 both set to 1: refresh at TEP/TEZ
-         */
-        uint32_t fh_cbcpulse: 2;
-        /** fh_force_cbc : R/W; bitpos: [3]; default: 0;
-         *  a toggle trigger a cycle-by-cycle mode action
-         */
-        uint32_t fh_force_cbc: 1;
-        /** fh_force_ost : R/W; bitpos: [4]; default: 0;
-         *  a toggle (software negate its value) triggers a one-shot mode action
-         */
-        uint32_t fh_force_ost: 1;
-        uint32_t reserved_5: 27;
-    };
-    uint32_t val;
-} mcpwm_fh_cfg1_reg_t;
-
-/** Type of fh_status register
- *  Status of fault events.
- */
-typedef union {
-    struct {
-        /** fh_cbc_on : RO; bitpos: [0]; default: 0;
-         *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
-         */
-        uint32_t fh_cbc_on: 1;
-        /** fh_ost_on : RO; bitpos: [1]; default: 0;
-         *  Set and reset by hardware. If set, an one-shot mode action is on going
-         */
-        uint32_t fh_ost_on: 1;
-        uint32_t reserved_2: 30;
-    };
-    uint32_t val;
-} mcpwm_fh_status_reg_t;
-
-/** Group: Fault Detection Configuration and Status */
-/** Type of fault_detect register
- *  Fault detection configuration and status
- */
-typedef union {
-    struct {
-        /** f0_en : R/W; bitpos: [0]; default: 0;
-         *  When set, fault_event0 generation is enabled
-         */
-        uint32_t f0_en: 1;
-        /** f1_en : R/W; bitpos: [1]; default: 0;
-         *  When set, fault_event1 generation is enabled
-         */
-        uint32_t f1_en: 1;
-        /** f2_en : R/W; bitpos: [2]; default: 0;
-         *  When set, fault_event2 generation is enabled
-         */
-        uint32_t f2_en: 1;
-        /** f0_pole : R/W; bitpos: [3]; default: 0;
-         *  Set fault_event0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
-         *  1: level high
-         */
-        uint32_t f0_pole: 1;
-        /** f1_pole : R/W; bitpos: [4]; default: 0;
-         *  Set fault_event1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
-         *  1: level high
-         */
-        uint32_t f1_pole: 1;
-        /** f2_pole : R/W; bitpos: [5]; default: 0;
-         *  Set fault_event2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
-         *  1: level high
-         */
-        uint32_t f2_pole: 1;
-        /** event_f0 : RO; bitpos: [6]; default: 0;
-         *  Set and reset by hardware. If set, fault_event0 is on going
-         */
-        uint32_t event_f0: 1;
-        /** event_f1 : RO; bitpos: [7]; default: 0;
-         *  Set and reset by hardware. If set, fault_event1 is on going
-         */
-        uint32_t event_f1: 1;
-        /** event_f2 : RO; bitpos: [8]; default: 0;
-         *  Set and reset by hardware. If set, fault_event2 is on going
-         */
-        uint32_t event_f2: 1;
-        uint32_t reserved_9: 23;
-    };
-    uint32_t val;
-} mcpwm_fault_detect_reg_t;
-
-
-/** Group: Capture Configuration and Status */
-/** Type of cap_timer_cfg register
- *  Configure capture timer
- */
-typedef union {
-    struct {
-        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
-         *  When set, capture timer incrementing under APB_clk is enabled.
-         */
-        uint32_t cap_timer_en: 1;
-        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
-         *  When set, capture timer sync is enabled.
-         */
-        uint32_t cap_synci_en: 1;
-        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
-         *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
-         *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
-         *  6: SYNC2 from GPIO matrix
-         */
-        uint32_t cap_synci_sel: 3;
-        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
-         *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
-         *  timer is loaded with value in phase register.
-         */
-        uint32_t cap_sync_sw: 1;
-        uint32_t reserved_6: 26;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_cfg_reg_t;
-
-/** Type of cap_timer_phase register
- *  Phase for capture timer sync
- */
-typedef union {
-    struct {
-        /** cap_timer_phase : R/W; bitpos: [31:0]; default: 0;
-         *  Phase value for capture timer sync operation.
-         */
-        uint32_t cap_timer_phase: 32;
-    };
-    uint32_t val;
-} mcpwm_cap_timer_phase_reg_t;
-
-/** Type of cap_chn_cfg register
- *  Capture channel 0 configuration and enable
- */
-typedef union {
-    struct {
-        /** capn_en : R/W; bitpos: [0]; default: 0;
-         *  When set, capture on channel 0 is enabled
-         */
-        uint32_t capn_en: 1;
-        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
-         *  Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
-         *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
-         *  edge.
-         */
-        uint32_t capn_mode: 2;
-        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
-         *  Value of prescaling on possitive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE +
-         *  1
-         */
-        uint32_t capn_prescale: 8;
-        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
-         *  when set, CAPn form GPIO matrix is inverted before prescale
-         */
-        uint32_t capn_in_invert: 1;
-        /** capn_sw : WT; bitpos: [12]; default: 0;
-         *  Write 1 will trigger a software forced capture on channel 0
-         */
-        uint32_t capn_sw: 1;
-        uint32_t reserved_13: 19;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_cfg_reg_t;
-
-/** Type of cap_chn register
- *  chn capture value status register
- */
-typedef union {
-    struct {
-        /** capn_value : RO; bitpos: [31:0]; default: 0;
-         *  Value of last capture on channel n
-         */
-        uint32_t capn_value: 32;
-    };
-    uint32_t val;
-} mcpwm_cap_chn_reg_t;
-
-/** Type of cap_status register
- *  Edge of last capture trigger
- */
-typedef union {
-    struct {
-        /** cap0_edge : RO; bitpos: [0]; default: 0;
-         *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
-         */
-        uint32_t cap0_edge: 1;
-        /** cap1_edge : RO; bitpos: [1]; default: 0;
-         *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
-         */
-        uint32_t cap1_edge: 1;
-        /** cap2_edge : RO; bitpos: [2]; default: 0;
-         *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
-         */
-        uint32_t cap2_edge: 1;
-        uint32_t reserved_3: 29;
-    };
-    uint32_t val;
-} mcpwm_cap_status_reg_t;
-
-
-/** Group: Enable update of active registers */
-/** Type of update_cfg register
- *  Enable update.
- */
-typedef union {
-    struct {
-        /** global_up_en : R/W; bitpos: [0]; default: 1;
-         *  The global enable of update of all active registers in MCPWM module
-         */
-        uint32_t global_up_en: 1;
-        /** global_force_up : R/W; bitpos: [1]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of all active
-         *  registers in MCPWM module
-         */
-        uint32_t global_force_up: 1;
-        /** op0_up_en : R/W; bitpos: [2]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
-         *  are enabled
-         */
-        uint32_t op0_up_en: 1;
-        /** op0_force_up : R/W; bitpos: [3]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 0
-         */
-        uint32_t op0_force_up: 1;
-        /** op1_up_en : R/W; bitpos: [4]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
-         *  are enabled
-         */
-        uint32_t op1_up_en: 1;
-        /** op1_force_up : R/W; bitpos: [5]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 1
-         */
-        uint32_t op1_force_up: 1;
-        /** op2_up_en : R/W; bitpos: [6]; default: 1;
-         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
-         *  are enabled
-         */
-        uint32_t op2_up_en: 1;
-        /** op2_force_up : R/W; bitpos: [7]; default: 0;
-         *  a toggle (software invert its value) will trigger a forced update of active
-         *  registers in PWM operator 2
-         */
-        uint32_t op2_force_up: 1;
-        uint32_t reserved_8: 24;
-    };
-    uint32_t val;
-} mcpwm_update_cfg_reg_t;
-
-
-/** Group: Manage Interrupts */
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_ena: 1;
-        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_ena: 1;
-        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_ena: 1;
-        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_ena: 1;
-        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_ena: 1;
-        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_ena: 1;
-        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_ena: 1;
-        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_ena: 1;
-        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_ena: 1;
-        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
-         *  The enable bit for the interrupt triggered when fault_event0 starts.
-         */
-        uint32_t fault0_int_ena: 1;
-        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
-         *  The enable bit for the interrupt triggered when fault_event1 starts.
-         */
-        uint32_t fault1_int_ena: 1;
-        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
-         *  The enable bit for the interrupt triggered when fault_event2 starts.
-         */
-        uint32_t fault2_int_ena: 1;
-        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
-         *  The enable bit for the interrupt triggered when fault_event0 ends.
-         */
-        uint32_t fault0_clr_int_ena: 1;
-        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
-         *  The enable bit for the interrupt triggered when fault_event1 ends.
-         */
-        uint32_t fault1_clr_int_ena: 1;
-        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
-         *  The enable bit for the interrupt triggered when fault_event2 ends.
-         */
-        uint32_t fault2_clr_int_ena: 1;
-        /** op0_tea_int_ena : R/W; bitpos: [15]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t op0_tea_int_ena: 1;
-        /** op1_tea_int_ena : R/W; bitpos: [16]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t op1_tea_int_ena: 1;
-        /** op2_tea_int_ena : R/W; bitpos: [17]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t op2_tea_int_ena: 1;
-        /** op0_teb_int_ena : R/W; bitpos: [18]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t op0_teb_int_ena: 1;
-        /** op1_teb_int_ena : R/W; bitpos: [19]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t op1_teb_int_ena: 1;
-        /** op2_teb_int_ena : R/W; bitpos: [20]; default: 0;
-         *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t op2_teb_int_ena: 1;
-        /** fh0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
-         */
-        uint32_t fh0_cbc_int_ena: 1;
-        /** fh1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
-         */
-        uint32_t fh1_cbc_int_ena: 1;
-        /** fh2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
-         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
-         */
-        uint32_t fh2_cbc_int_ena: 1;
-        /** fh0_ost_int_ena : R/W; bitpos: [24]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t fh0_ost_int_ena: 1;
-        /** fh1_ost_int_ena : R/W; bitpos: [25]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t fh1_ost_int_ena: 1;
-        /** fh2_ost_int_ena : R/W; bitpos: [26]; default: 0;
-         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t fh2_ost_int_ena: 1;
-        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_ena: 1;
-        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_ena: 1;
-        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
-         *  The enable bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_ena: 1;
-        uint32_t reserved_30: 2;
-    };
-    uint32_t val;
-} mcpwm_int_ena_reg_t;
-
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_raw: 1;
-        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_raw: 1;
-        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw status bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_raw: 1;
-        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_raw: 1;
-        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_raw: 1;
-        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_raw: 1;
-        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_raw: 1;
-        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_raw: 1;
-        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_raw: 1;
-        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  The raw status bit for the interrupt triggered when fault_event0 starts.
-         */
-        uint32_t fault0_int_raw: 1;
-        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  The raw status bit for the interrupt triggered when fault_event1 starts.
-         */
-        uint32_t fault1_int_raw: 1;
-        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  The raw status bit for the interrupt triggered when fault_event2 starts.
-         */
-        uint32_t fault2_int_raw: 1;
-        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  The raw status bit for the interrupt triggered when fault_event0 ends.
-         */
-        uint32_t fault0_clr_int_raw: 1;
-        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  The raw status bit for the interrupt triggered when fault_event1 ends.
-         */
-        uint32_t fault1_clr_int_raw: 1;
-        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  The raw status bit for the interrupt triggered when fault_event2 ends.
-         */
-        uint32_t fault2_clr_int_raw: 1;
-        /** op0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t op0_tea_int_raw: 1;
-        /** op1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t op1_tea_int_raw: 1;
-        /** op2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t op2_tea_int_raw: 1;
-        /** op0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t op0_teb_int_raw: 1;
-        /** op1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t op1_teb_int_raw: 1;
-        /** op2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
-         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t op2_teb_int_raw: 1;
-        /** fh0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM0.
-         */
-        uint32_t fh0_cbc_int_raw: 1;
-        /** fh1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM1.
-         */
-        uint32_t fh1_cbc_int_raw: 1;
-        /** fh2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
-         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM2.
-         */
-        uint32_t fh2_cbc_int_raw: 1;
-        /** fh0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t fh0_ost_int_raw: 1;
-        /** fh1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t fh1_ost_int_raw: 1;
-        /** fh2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
-         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t fh2_ost_int_raw: 1;
-        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_raw: 1;
-        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_raw: 1;
-        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
-         *  The raw status bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_raw: 1;
-        uint32_t reserved_30: 2;
-    };
-    uint32_t val;
-} mcpwm_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_st: 1;
-        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_st: 1;
-        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
-         *  The masked status bit for the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_st: 1;
-        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_st: 1;
-        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_st: 1;
-        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_st: 1;
-        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_st: 1;
-        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_st: 1;
-        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_st: 1;
-        /** fault0_int_st : RO; bitpos: [9]; default: 0;
-         *  The masked status bit for the interrupt triggered when fault_event0 starts.
-         */
-        uint32_t fault0_int_st: 1;
-        /** fault1_int_st : RO; bitpos: [10]; default: 0;
-         *  The masked status bit for the interrupt triggered when fault_event1 starts.
-         */
-        uint32_t fault1_int_st: 1;
-        /** fault2_int_st : RO; bitpos: [11]; default: 0;
-         *  The masked status bit for the interrupt triggered when fault_event2 starts.
-         */
-        uint32_t fault2_int_st: 1;
-        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
-         *  The masked status bit for the interrupt triggered when fault_event0 ends.
-         */
-        uint32_t fault0_clr_int_st: 1;
-        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
-         *  The masked status bit for the interrupt triggered when fault_event1 ends.
-         */
-        uint32_t fault1_clr_int_st: 1;
-        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
-         *  The masked status bit for the interrupt triggered when fault_event2 ends.
-         */
-        uint32_t fault2_clr_int_st: 1;
-        /** op0_tea_int_st : RO; bitpos: [15]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t op0_tea_int_st: 1;
-        /** op1_tea_int_st : RO; bitpos: [16]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t op1_tea_int_st: 1;
-        /** op2_tea_int_st : RO; bitpos: [17]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t op2_tea_int_st: 1;
-        /** op0_teb_int_st : RO; bitpos: [18]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t op0_teb_int_st: 1;
-        /** op1_teb_int_st : RO; bitpos: [19]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t op1_teb_int_st: 1;
-        /** op2_teb_int_st : RO; bitpos: [20]; default: 0;
-         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t op2_teb_int_st: 1;
-        /** fh0_cbc_int_st : RO; bitpos: [21]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM0.
-         */
-        uint32_t fh0_cbc_int_st: 1;
-        /** fh1_cbc_int_st : RO; bitpos: [22]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM1.
-         */
-        uint32_t fh1_cbc_int_st: 1;
-        /** fh2_cbc_int_st : RO; bitpos: [23]; default: 0;
-         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
-         *  on PWM2.
-         */
-        uint32_t fh2_cbc_int_st: 1;
-        /** fh0_ost_int_st : RO; bitpos: [24]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t fh0_ost_int_st: 1;
-        /** fh1_ost_int_st : RO; bitpos: [25]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t fh1_ost_int_st: 1;
-        /** fh2_ost_int_st : RO; bitpos: [26]; default: 0;
-         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t fh2_ost_int_st: 1;
-        /** cap0_int_st : RO; bitpos: [27]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_st: 1;
-        /** cap1_int_st : RO; bitpos: [28]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_st: 1;
-        /** cap2_int_st : RO; bitpos: [29]; default: 0;
-         *  The masked status bit for the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_st: 1;
-        uint32_t reserved_30: 2;
-    };
-    uint32_t val;
-} mcpwm_int_st_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 0 stops.
-         */
-        uint32_t timer0_stop_int_clr: 1;
-        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 1 stops.
-         */
-        uint32_t timer1_stop_int_clr: 1;
-        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear the interrupt triggered when the timer 2 stops.
-         */
-        uint32_t timer2_stop_int_clr: 1;
-        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
-         */
-        uint32_t timer0_tez_int_clr: 1;
-        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
-         */
-        uint32_t timer1_tez_int_clr: 1;
-        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
-         */
-        uint32_t timer2_tez_int_clr: 1;
-        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
-         */
-        uint32_t timer0_tep_int_clr: 1;
-        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
-         */
-        uint32_t timer1_tep_int_clr: 1;
-        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
-         */
-        uint32_t timer2_tep_int_clr: 1;
-        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the interrupt triggered when fault_event0 starts.
-         */
-        uint32_t fault0_int_clr: 1;
-        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the interrupt triggered when fault_event1 starts.
-         */
-        uint32_t fault1_int_clr: 1;
-        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the interrupt triggered when fault_event2 starts.
-         */
-        uint32_t fault2_int_clr: 1;
-        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the interrupt triggered when fault_event0 ends.
-         */
-        uint32_t fault0_clr_int_clr: 1;
-        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the interrupt triggered when fault_event1 ends.
-         */
-        uint32_t fault1_clr_int_clr: 1;
-        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the interrupt triggered when fault_event2 ends.
-         */
-        uint32_t fault2_clr_int_clr: 1;
-        /** op0_tea_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
-         */
-        uint32_t op0_tea_int_clr: 1;
-        /** op1_tea_int_clr : WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
-         */
-        uint32_t op1_tea_int_clr: 1;
-        /** op2_tea_int_clr : WT; bitpos: [17]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
-         */
-        uint32_t op2_tea_int_clr: 1;
-        /** op0_teb_int_clr : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
-         */
-        uint32_t op0_teb_int_clr: 1;
-        /** op1_teb_int_clr : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
-         */
-        uint32_t op1_teb_int_clr: 1;
-        /** op2_teb_int_clr : WT; bitpos: [20]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
-         */
-        uint32_t op2_teb_int_clr: 1;
-        /** fh0_cbc_int_clr : WT; bitpos: [21]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM0.
-         */
-        uint32_t fh0_cbc_int_clr: 1;
-        /** fh1_cbc_int_clr : WT; bitpos: [22]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM1.
-         */
-        uint32_t fh1_cbc_int_clr: 1;
-        /** fh2_cbc_int_clr : WT; bitpos: [23]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
-         *  PWM2.
-         */
-        uint32_t fh2_cbc_int_clr: 1;
-        /** fh0_ost_int_clr : WT; bitpos: [24]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
-         */
-        uint32_t fh0_ost_int_clr: 1;
-        /** fh1_ost_int_clr : WT; bitpos: [25]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
-         */
-        uint32_t fh1_ost_int_clr: 1;
-        /** fh2_ost_int_clr : WT; bitpos: [26]; default: 0;
-         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
-         */
-        uint32_t fh2_ost_int_clr: 1;
-        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 0.
-         */
-        uint32_t cap0_int_clr: 1;
-        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 1.
-         */
-        uint32_t cap1_int_clr: 1;
-        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
-         *  Set this bit to clear the interrupt triggered by capture on channel 2.
-         */
-        uint32_t cap2_int_clr: 1;
-        uint32_t reserved_30: 2;
-    };
-    uint32_t val;
-} mcpwm_int_clr_reg_t;
-
-
-/** Group: MCMCPWM APB configuration register */
-/** Type of clk register
- *  MCPWM APB configuration register
- */
-typedef union {
-    struct {
-        /** clk_en : R/W; bitpos: [0]; default: 0;
-         *  Force clock on for this register file
-         */
-        uint32_t clk_en: 1;
-        uint32_t reserved_1: 31;
-    };
-    uint32_t val;
-} mcpwm_clk_reg_t;
-
-
-/** Group: Version Register */
-/** Type of version register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [27:0]; default: 34632240;
-         *  Version of this register file
-         */
-        uint32_t date: 28;
-        uint32_t reserved_28: 4;
-    };
-    uint32_t val;
-} mcpwm_version_reg_t;
-
-
-typedef struct {
-    mcpwm_timer_cfg0_reg_t timer_cfg0;
-    mcpwm_timer_cfg1_reg_t timer_cfg1;
-    mcpwm_timer_sync_reg_t timer_sync;
-    mcpwm_timer_status_reg_t timer_status;
-} mcpwm_timer_regs_t;
-
-typedef struct {
-    mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
-    mcpwm_gen_tstmp_reg_t timestamp[2];
-    mcpwm_gen_cfg0_reg_t gen_cfg0;
-    mcpwm_gen_force_reg_t gen_force;
-    mcpwm_gen_reg_t generator[2];
-    mcpwm_dt_cfg_reg_t dt_cfg;
-    mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
-    mcpwm_dt_red_cfg_reg_t dt_red_cfg;
-    mcpwm_carrier_cfg_reg_t carrier_cfg;
-    mcpwm_fh_cfg0_reg_t fh_cfg0;
-    mcpwm_fh_cfg1_reg_t fh_cfg1;
-    mcpwm_fh_status_reg_t fh_status;
-} mcpwm_operator_reg_t;
-
-typedef struct mcpwm_dev_t {
-    volatile mcpwm_clk_cfg_reg_t clk_cfg;
-    volatile mcpwm_timer_regs_t timer[3];
-    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
-    volatile mcpwm_operator_timersel_reg_t operator_timersel;
-    volatile mcpwm_operator_reg_t operators[3];
-    volatile mcpwm_fault_detect_reg_t fault_detect;
-    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
-    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
-    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
-    volatile mcpwm_cap_chn_reg_t cap_chn[3];
-    volatile mcpwm_cap_status_reg_t cap_status;
-    volatile mcpwm_update_cfg_reg_t update_cfg;
-    volatile mcpwm_int_ena_reg_t int_ena;
-    volatile mcpwm_int_raw_reg_t int_raw;
-    volatile mcpwm_int_st_reg_t int_st;
-    volatile mcpwm_int_clr_reg_t int_clr;
-    volatile mcpwm_clk_reg_t clk;
-    volatile mcpwm_version_reg_t version;
-} mcpwm_dev_t;
-
-extern mcpwm_dev_t MCPWM0;
-extern mcpwm_dev_t MCPWM1;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(mcpwm_dev_t) == 0x128, "Invalid size of mcpwm_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/esp32s3/include/soc/rtc_cntl_reg.h
deleted file mode 100644
index 33e0fd40629..00000000000
--- a/components/soc/esp32s3/include/soc/rtc_cntl_reg.h
+++ /dev/null
@@ -1,3702 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _SOC_RTC_CNTL_REG_H_
-#define _SOC_RTC_CNTL_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
-#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
-
-#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
-#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
-
-#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
-/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
-/*description: SW system reset.*/
-#define RTC_CNTL_SW_SYS_RST    (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
-#define RTC_CNTL_SW_SYS_RST_V  0x1
-#define RTC_CNTL_SW_SYS_RST_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: digital core force no reset in deep sleep.*/
-#define RTC_CNTL_DG_WRAP_FORCE_NORST    (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
-/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: digital wrap force reset in deep sleep.*/
-#define RTC_CNTL_DG_WRAP_FORCE_RST    (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
-#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
-/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: .*/
-#define RTC_CNTL_ANALOG_FORCE_NOISO    (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
-#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
-#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
-/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: .*/
-#define RTC_CNTL_PLL_FORCE_NOISO    (BIT(27))
-#define RTC_CNTL_PLL_FORCE_NOISO_M  (BIT(27))
-#define RTC_CNTL_PLL_FORCE_NOISO_V  0x1
-#define RTC_CNTL_PLL_FORCE_NOISO_S  27
-/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
-/*description: .*/
-#define RTC_CNTL_XTL_FORCE_NOISO    (BIT(26))
-#define RTC_CNTL_XTL_FORCE_NOISO_M  (BIT(26))
-#define RTC_CNTL_XTL_FORCE_NOISO_V  0x1
-#define RTC_CNTL_XTL_FORCE_NOISO_S  26
-/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_ANALOG_FORCE_ISO    (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
-#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
-#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
-/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_PLL_FORCE_ISO    (BIT(24))
-#define RTC_CNTL_PLL_FORCE_ISO_M  (BIT(24))
-#define RTC_CNTL_PLL_FORCE_ISO_V  0x1
-#define RTC_CNTL_PLL_FORCE_ISO_S  24
-/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_XTL_FORCE_ISO    (BIT(23))
-#define RTC_CNTL_XTL_FORCE_ISO_M  (BIT(23))
-#define RTC_CNTL_XTL_FORCE_ISO_V  0x1
-#define RTC_CNTL_XTL_FORCE_ISO_S  23
-/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */
-/*description: wait bias_sleep and current source wakeup.*/
-#define RTC_CNTL_XTL_EN_WAIT    0x0000000F
-#define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
-#define RTC_CNTL_XTL_EN_WAIT_V  0xF
-#define RTC_CNTL_XTL_EN_WAIT_S  14
-/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
-/*description: crystall force power up.*/
-#define RTC_CNTL_XTL_FORCE_PU    (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
-#define RTC_CNTL_XTL_FORCE_PU_V  0x1
-#define RTC_CNTL_XTL_FORCE_PU_S  13
-/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: crystall force power down.*/
-#define RTC_CNTL_XTL_FORCE_PD    (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
-#define RTC_CNTL_XTL_FORCE_PD_V  0x1
-#define RTC_CNTL_XTL_FORCE_PD_S  12
-/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: BB_PLL force power up.*/
-#define RTC_CNTL_BBPLL_FORCE_PU    (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
-#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
-#define RTC_CNTL_BBPLL_FORCE_PU_S  11
-/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: BB_PLL force power down.*/
-#define RTC_CNTL_BBPLL_FORCE_PD    (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
-#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
-#define RTC_CNTL_BBPLL_FORCE_PD_S  10
-/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: BB_PLL_I2C force power up.*/
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU    (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
-/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: BB_PLL _I2C force power down.*/
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD    (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
-/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: BB_I2C force power up.*/
-#define RTC_CNTL_BB_I2C_FORCE_PU    (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
-#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
-#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
-/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: BB_I2C force power down.*/
-#define RTC_CNTL_BB_I2C_FORCE_PD    (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
-#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
-#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
-/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: PRO CPU SW reset.*/
-#define RTC_CNTL_SW_PROCPU_RST    (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
-#define RTC_CNTL_SW_PROCPU_RST_V  0x1
-#define RTC_CNTL_SW_PROCPU_RST_S  5
-/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: APP CPU SW reset.*/
-#define RTC_CNTL_SW_APPCPU_RST    (BIT(4))
-#define RTC_CNTL_SW_APPCPU_RST_M  (BIT(4))
-#define RTC_CNTL_SW_APPCPU_RST_V  0x1
-#define RTC_CNTL_SW_APPCPU_RST_S  4
-/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P
-RO CPU.*/
-#define RTC_CNTL_SW_STALL_PROCPU_C0    0x00000003
-#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
-#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
-#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
-/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: {reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A
-PP CPU.*/
-#define RTC_CNTL_SW_STALL_APPCPU_C0    0x00000003
-#define RTC_CNTL_SW_STALL_APPCPU_C0_M  ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
-#define RTC_CNTL_SW_STALL_APPCPU_C0_V  0x3
-#define RTC_CNTL_SW_STALL_APPCPU_C0_S  0
-
-#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x4)
-/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define RTC_CNTL_SLP_VAL_LO    0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
-#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
-#define RTC_CNTL_SLP_VAL_LO_S  0
-
-#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x8)
-/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */
-/*description: timer alarm enable bit.*/
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN    (BIT(16))
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
-#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
-/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC sleep timer high 16 bits.*/
-#define RTC_CNTL_SLP_VAL_HI    0x0000FFFF
-#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
-#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
-#define RTC_CNTL_SLP_VAL_HI_S  0
-
-#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0xC)
-/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Set 1: to update register with RTC timer.*/
-#define RTC_CNTL_TIME_UPDATE    (BIT(31))
-#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
-#define RTC_CNTL_TIME_UPDATE_V  0x1
-#define RTC_CNTL_TIME_UPDATE_S  31
-/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: enable to record system reset time.*/
-#define RTC_CNTL_TIMER_SYS_RST    (BIT(29))
-#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
-#define RTC_CNTL_TIMER_SYS_RST_V  0x1
-#define RTC_CNTL_TIMER_SYS_RST_S  29
-/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Enable to record 40M XTAL OFF time.*/
-#define RTC_CNTL_TIMER_XTL_OFF    (BIT(28))
-#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
-#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
-#define RTC_CNTL_TIMER_XTL_OFF_S  28
-/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Enable to record system stall time.*/
-#define RTC_CNTL_TIMER_SYS_STALL    (BIT(27))
-#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
-#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
-#define RTC_CNTL_TIMER_SYS_STALL_S  27
-
-#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x10)
-/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: RTC timer low 32 bits.*/
-#define RTC_CNTL_TIMER_VALUE0_LOW    0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
-#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
-
-#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x14)
-/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC timer high 16 bits.*/
-#define RTC_CNTL_TIMER_VALUE0_HIGH    0x0000FFFF
-#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
-#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
-#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
-
-#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
-/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: sleep enable bit.*/
-#define RTC_CNTL_SLEEP_EN    (BIT(31))
-#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
-#define RTC_CNTL_SLEEP_EN_V  0x1
-#define RTC_CNTL_SLEEP_EN_S  31
-/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: leep reject bit.*/
-#define RTC_CNTL_SLP_REJECT    (BIT(30))
-#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
-#define RTC_CNTL_SLP_REJECT_V  0x1
-#define RTC_CNTL_SLP_REJECT_S  30
-/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: leep wakeup bit.*/
-#define RTC_CNTL_SLP_WAKEUP    (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
-#define RTC_CNTL_SLP_WAKEUP_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_S  29
-/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
-/*description: SDIO active indication.*/
-#define RTC_CNTL_SDIO_ACTIVE_IND    (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
-#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
-#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
-/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: 1: APB to RTC using bridge.*/
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL    (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
-#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
-/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: clear rtc sleep reject cause.*/
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
-#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
-/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: rtc software interrupt to main cpu.*/
-#define RTC_CNTL_SW_CPU_INT    (BIT(0))
-#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
-#define RTC_CNTL_SW_CPU_INT_V  0x1
-#define RTC_CNTL_SW_CPU_INT_S  0
-
-#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1C)
-/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
-/*description: PLL wait cycles in slow_clk_rtc.*/
-#define RTC_CNTL_PLL_BUF_WAIT    0x000000FF
-#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
-#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
-#define RTC_CNTL_PLL_BUF_WAIT_S  24
-/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
-/*description: XTAL wait cycles in slow_clk_rtc.*/
-#define RTC_CNTL_XTL_BUF_WAIT    0x000003FF
-#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
-#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
-#define RTC_CNTL_XTL_BUF_WAIT_S  14
-/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
-/*description: CK8M wait cycles in slow_clk_rtc.*/
-#define RTC_CNTL_CK8M_WAIT    0x000000FF
-#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
-#define RTC_CNTL_CK8M_WAIT_V  0xFF
-#define RTC_CNTL_CK8M_WAIT_S  6
-/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
-/*description: CPU stall wait cycles in fast_clk_rtc.*/
-#define RTC_CNTL_CPU_STALL_WAIT    0x0000001F
-#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
-#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
-#define RTC_CNTL_CPU_STALL_WAIT_S  1
-/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
-/*description: CPU stall enable bit.*/
-#define RTC_CNTL_CPU_STALL_EN    (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
-#define RTC_CNTL_CPU_STALL_EN_V  0x1
-#define RTC_CNTL_CPU_STALL_EN_S  0
-
-#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
-/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
-/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/
-#define RTC_CNTL_MIN_TIME_CK8M_OFF    0x000000FF
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
-#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
-/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */
-/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to w
-ork.*/
-#define RTC_CNTL_ULPCP_TOUCH_START_WAIT    0x000001FF
-#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M  ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S))
-#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V  0x1FF
-#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S  15
-
-#define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x24)
-/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */
-/*description: .*/
-#define RTC_CNTL_BT_POWERUP_TIMER    0x0000007F
-#define RTC_CNTL_BT_POWERUP_TIMER_M  ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S))
-#define RTC_CNTL_BT_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_BT_POWERUP_TIMER_S  25
-/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */
-/*description: .*/
-#define RTC_CNTL_BT_WAIT_TIMER    0x000001FF
-#define RTC_CNTL_BT_WAIT_TIMER_M  ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S))
-#define RTC_CNTL_BT_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_BT_WAIT_TIMER_S  16
-/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
-/*description: .*/
-#define RTC_CNTL_WIFI_POWERUP_TIMER    0x0000007F
-#define RTC_CNTL_WIFI_POWERUP_TIMER_M  ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
-#define RTC_CNTL_WIFI_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_WIFI_POWERUP_TIMER_S  9
-/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
-/*description: .*/
-#define RTC_CNTL_WIFI_WAIT_TIMER    0x000001FF
-#define RTC_CNTL_WIFI_WAIT_TIMER_M  ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
-#define RTC_CNTL_WIFI_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_WIFI_WAIT_TIMER_S  0
-
-#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x28)
-/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
-/*description: .*/
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER    0x0000007F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
-/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
-/*description: .*/
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER    0x000001FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
-/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
-/*description: .*/
-#define RTC_CNTL_POWERUP_TIMER    0x0000007F
-#define RTC_CNTL_POWERUP_TIMER_M  ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S))
-#define RTC_CNTL_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_POWERUP_TIMER_S  9
-/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
-/*description: .*/
-#define RTC_CNTL_WAIT_TIMER    0x000001FF
-#define RTC_CNTL_WAIT_TIMER_M  ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S))
-#define RTC_CNTL_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_WAIT_TIMER_S  0
-
-#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x2C)
-/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
-/*description: minimal sleep cycles in slow_clk_rtc.*/
-#define RTC_CNTL_MIN_SLP_VAL    0x000000FF
-#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
-#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
-#define RTC_CNTL_MIN_SLP_VAL_S  8
-
-#define RTC_CNTL_TIMER6_REG          (DR_REG_RTCCNTL_BASE + 0x30)
-/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
-/*description: .*/
-#define RTC_CNTL_DG_PERI_POWERUP_TIMER    0x0000007F
-#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M  ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S))
-#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S  25
-/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
-/*description: .*/
-#define RTC_CNTL_DG_PERI_WAIT_TIMER    0x000001FF
-#define RTC_CNTL_DG_PERI_WAIT_TIMER_M  ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S))
-#define RTC_CNTL_DG_PERI_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_DG_PERI_WAIT_TIMER_S  16
-/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
-/*description: .*/
-#define RTC_CNTL_CPU_TOP_POWERUP_TIMER    0x0000007F
-#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M  ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S))
-#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V  0x7F
-#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S  9
-/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
-/*description: .*/
-#define RTC_CNTL_CPU_TOP_WAIT_TIMER    0x000001FF
-#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M  ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S))
-#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V  0x1FF
-#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S  0
-
-#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x34)
-/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_PLL_I2C_PU    (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
-#define RTC_CNTL_PLL_I2C_PU_V  0x1
-#define RTC_CNTL_PLL_I2C_PU_S  31
-/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: 1: CKGEN_I2C power up.*/
-#define RTC_CNTL_CKGEN_I2C_PU    (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
-#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
-#define RTC_CNTL_CKGEN_I2C_PU_S  30
-/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: 1: RFRX_PBUS power up.*/
-#define RTC_CNTL_RFRX_PBUS_PU    (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
-#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
-#define RTC_CNTL_RFRX_PBUS_PU_S  28
-/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: 1: TXRF_I2C power up.*/
-#define RTC_CNTL_TXRF_I2C_PU    (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
-#define RTC_CNTL_TXRF_I2C_PU_V  0x1
-#define RTC_CNTL_TXRF_I2C_PU_S  27
-/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: 1: PVTMON power up.*/
-#define RTC_CNTL_PVTMON_PU    (BIT(26))
-#define RTC_CNTL_PVTMON_PU_M  (BIT(26))
-#define RTC_CNTL_PVTMON_PU_V  0x1
-#define RTC_CNTL_PVTMON_PU_S  26
-/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: start BBPLL calibration during sleep.*/
-#define RTC_CNTL_BBPLL_CAL_SLP_START    (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
-#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
-#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
-/* RTC_CNTL_ANALOG_TOP_ISO_MONITOR : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: PLLA force power up.*/
-#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR    (BIT(24))
-#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_M  (BIT(24))
-#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V  0x1
-#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S  24
-/* RTC_CNTL_ANALOG_TOP_ISO_SLEEP : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: PLLA force power down.*/
-#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP    (BIT(23))
-#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_M  (BIT(23))
-#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V  0x1
-#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S  23
-/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: PLLA force power up.*/
-#define RTC_CNTL_SAR_I2C_PU    (BIT(22))
-#define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
-#define RTC_CNTL_SAR_I2C_PU_V  0x1
-#define RTC_CNTL_SAR_I2C_PU_S  22
-/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_GLITCH_RST_EN    (BIT(20))
-#define RTC_CNTL_GLITCH_RST_EN_M  (BIT(20))
-#define RTC_CNTL_GLITCH_RST_EN_V  0x1
-#define RTC_CNTL_GLITCH_RST_EN_S  20
-/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU    (BIT(19))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
-/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: .*/
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD    (BIT(18))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
-#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
-
-#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x38)
-/* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_PRO_DRESET_MASK    (BIT(25))
-#define RTC_CNTL_PRO_DRESET_MASK_M  (BIT(25))
-#define RTC_CNTL_PRO_DRESET_MASK_V  0x1
-#define RTC_CNTL_PRO_DRESET_MASK_S  25
-/* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_APP_DRESET_MASK    (BIT(24))
-#define RTC_CNTL_APP_DRESET_MASK_M  (BIT(24))
-#define RTC_CNTL_APP_DRESET_MASK_V  0x1
-#define RTC_CNTL_APP_DRESET_MASK_S  24
-/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR    (BIT(23))
-#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M  (BIT(23))
-#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V  0x1
-#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S  23
-/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR    (BIT(22))
-#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M  (BIT(22))
-#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V  0x1
-#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S  22
-/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU    (BIT(21))
-#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M  (BIT(21))
-#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V  0x1
-#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S  21
-/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU    (BIT(20))
-#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M  (BIT(20))
-#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V  0x1
-#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S  20
-/* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: PROCPU OcdHaltOnReset.*/
-#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET    (BIT(19))
-#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M  (BIT(19))
-#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V  0x1
-#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S  19
-/* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: APPCPU OcdHaltOnReset.*/
-#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET    (BIT(18))
-#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M  (BIT(18))
-#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V  0x1
-#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S  18
-/* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: clear APP CPU reset flag.*/
-#define RTC_CNTL_RESET_FLAG_APPCPU_CLR    (BIT(17))
-#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M  (BIT(17))
-#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V  0x1
-#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S  17
-/* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: clear PRO CPU reset_flag.*/
-#define RTC_CNTL_RESET_FLAG_PROCPU_CLR    (BIT(16))
-#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M  (BIT(16))
-#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V  0x1
-#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S  16
-/* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: APP CPU reset flag.*/
-#define RTC_CNTL_RESET_FLAG_APPCPU    (BIT(15))
-#define RTC_CNTL_RESET_FLAG_APPCPU_M  (BIT(15))
-#define RTC_CNTL_RESET_FLAG_APPCPU_V  0x1
-#define RTC_CNTL_RESET_FLAG_APPCPU_S  15
-/* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: PRO CPU reset_flag.*/
-#define RTC_CNTL_RESET_FLAG_PROCPU    (BIT(14))
-#define RTC_CNTL_RESET_FLAG_PROCPU_M  (BIT(14))
-#define RTC_CNTL_RESET_FLAG_PROCPU_V  0x1
-#define RTC_CNTL_RESET_FLAG_PROCPU_S  14
-/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: PRO CPU state vector sel.*/
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL    (BIT(13))
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M  (BIT(13))
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V  0x1
-#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S  13
-/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */
-/*description: APP CPU state vector sel.*/
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL    (BIT(12))
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M  (BIT(12))
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V  0x1
-#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S  12
-/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
-/*description: reset cause of APP CPU.*/
-#define RTC_CNTL_RESET_CAUSE_APPCPU    0x0000003F
-#define RTC_CNTL_RESET_CAUSE_APPCPU_M  ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
-#define RTC_CNTL_RESET_CAUSE_APPCPU_V  0x3F
-#define RTC_CNTL_RESET_CAUSE_APPCPU_S  6
-/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
-/*description: reset cause of PRO CPU.*/
-#define RTC_CNTL_RESET_CAUSE_PROCPU    0x0000003F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
-#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
-#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
-
-#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x3C)
-/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */
-/*description: wakeup enable bitmap.*/
-#define RTC_CNTL_WAKEUP_ENA    0x0001FFFF
-#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
-#define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
-#define RTC_CNTL_WAKEUP_ENA_S  15
-
-#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x40)
-/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA    (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M  (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V  0x1
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S  20
-/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: enable gitch det interrupt.*/
-#define RTC_CNTL_GLITCH_DET_INT_ENA    (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_ENA_S  19
-/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: enable touch timeout interrupt.*/
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA    (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M  (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V  0x1
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S  18
-/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: enable cocpu trap interrupt.*/
-#define RTC_CNTL_COCPU_TRAP_INT_ENA    (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_M  (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_V  0x1
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_S  17
-/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: enable xtal32k_dead  interrupt.*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA    (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S  16
-/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define RTC_CNTL_SWD_INT_ENA    (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_S  15
-/* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: enable saradc2 interrupt.*/
-#define RTC_CNTL_SARADC2_INT_ENA    (BIT(14))
-#define RTC_CNTL_SARADC2_INT_ENA_M  (BIT(14))
-#define RTC_CNTL_SARADC2_INT_ENA_V  0x1
-#define RTC_CNTL_SARADC2_INT_ENA_S  14
-/* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: enable riscV cocpu interrupt.*/
-#define RTC_CNTL_COCPU_INT_ENA    (BIT(13))
-#define RTC_CNTL_COCPU_INT_ENA_M  (BIT(13))
-#define RTC_CNTL_COCPU_INT_ENA_V  0x1
-#define RTC_CNTL_COCPU_INT_ENA_S  13
-/* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: enable tsens interrupt.*/
-#define RTC_CNTL_TSENS_INT_ENA    (BIT(12))
-#define RTC_CNTL_TSENS_INT_ENA_M  (BIT(12))
-#define RTC_CNTL_TSENS_INT_ENA_V  0x1
-#define RTC_CNTL_TSENS_INT_ENA_S  12
-/* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: enable saradc1 interrupt.*/
-#define RTC_CNTL_SARADC1_INT_ENA    (BIT(11))
-#define RTC_CNTL_SARADC1_INT_ENA_M  (BIT(11))
-#define RTC_CNTL_SARADC1_INT_ENA_V  0x1
-#define RTC_CNTL_SARADC1_INT_ENA_S  11
-/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt.*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt.*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
-/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: enable touch inactive interrupt.*/
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA    (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M  (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V  0x1
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S  8
-/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: enable touch active interrupt.*/
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA    (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M  (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V  0x1
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S  7
-/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: enable touch done interrupt.*/
-#define RTC_CNTL_TOUCH_DONE_INT_ENA    (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_M  (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_V  0x1
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_S  6
-/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: enable ULP-coprocessor interrupt.*/
-#define RTC_CNTL_ULP_CP_INT_ENA    (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ENA_M  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ENA_V  0x1
-#define RTC_CNTL_ULP_CP_INT_ENA_S  5
-/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: enable touch scan done interrupt.*/
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA    (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M  (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V  0x1
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S  4
-/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define RTC_CNTL_WDT_INT_ENA    (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: enable SDIO idle interrupt.*/
-#define RTC_CNTL_SDIO_IDLE_INT_ENA    (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_S  2
-/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt.*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
-
-#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x44)
-/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW    (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M  (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V  0x1
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S  20
-/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: glitch_det_interrupt_raw.*/
-#define RTC_CNTL_GLITCH_DET_INT_RAW    (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_RAW_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_RAW_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_RAW_S  19
-/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: touch timeout interrupt raw.*/
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW    (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M  (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V  0x1
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S  18
-/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: cocpu trap interrupt raw.*/
-#define RTC_CNTL_COCPU_TRAP_INT_RAW    (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_RAW_M  (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_RAW_V  0x1
-#define RTC_CNTL_COCPU_TRAP_INT_RAW_S  17
-/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: xtal32k dead detection interrupt raw.*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_RAW    (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S  16
-/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: super watch dog interrupt raw.*/
-#define RTC_CNTL_SWD_INT_RAW    (BIT(15))
-#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_RAW_V  0x1
-#define RTC_CNTL_SWD_INT_RAW_S  15
-/* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: saradc2 interrupt raw.*/
-#define RTC_CNTL_SARADC2_INT_RAW    (BIT(14))
-#define RTC_CNTL_SARADC2_INT_RAW_M  (BIT(14))
-#define RTC_CNTL_SARADC2_INT_RAW_V  0x1
-#define RTC_CNTL_SARADC2_INT_RAW_S  14
-/* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: riscV cocpu interrupt raw.*/
-#define RTC_CNTL_COCPU_INT_RAW    (BIT(13))
-#define RTC_CNTL_COCPU_INT_RAW_M  (BIT(13))
-#define RTC_CNTL_COCPU_INT_RAW_V  0x1
-#define RTC_CNTL_COCPU_INT_RAW_S  13
-/* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: tsens interrupt raw.*/
-#define RTC_CNTL_TSENS_INT_RAW    (BIT(12))
-#define RTC_CNTL_TSENS_INT_RAW_M  (BIT(12))
-#define RTC_CNTL_TSENS_INT_RAW_V  0x1
-#define RTC_CNTL_TSENS_INT_RAW_S  12
-/* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: saradc1 interrupt raw.*/
-#define RTC_CNTL_SARADC1_INT_RAW    (BIT(11))
-#define RTC_CNTL_SARADC1_INT_RAW_M  (BIT(11))
-#define RTC_CNTL_SARADC1_INT_RAW_V  0x1
-#define RTC_CNTL_SARADC1_INT_RAW_S  11
-/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: RTC main timer interrupt raw.*/
-#define RTC_CNTL_MAIN_TIMER_INT_RAW    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
-/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: brown out interrupt raw.*/
-#define RTC_CNTL_BROWN_OUT_INT_RAW    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
-/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: touch inactive interrupt raw.*/
-#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW    (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M  (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V  0x1
-#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S  8
-/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: touch active interrupt raw.*/
-#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW    (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M  (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V  0x1
-#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S  7
-/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: touch interrupt raw.*/
-#define RTC_CNTL_TOUCH_DONE_INT_RAW    (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_RAW_M  (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_RAW_V  0x1
-#define RTC_CNTL_TOUCH_DONE_INT_RAW_S  6
-/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: ULP-coprocessor interrupt raw.*/
-#define RTC_CNTL_ULP_CP_INT_RAW    (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_RAW_M  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_RAW_V  0x1
-#define RTC_CNTL_ULP_CP_INT_RAW_S  5
-/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW    (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M  (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V  0x1
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S  4
-/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt raw.*/
-#define RTC_CNTL_WDT_INT_RAW    (BIT(3))
-#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_RAW_V  0x1
-#define RTC_CNTL_WDT_INT_RAW_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SDIO idle interrupt raw.*/
-#define RTC_CNTL_SDIO_IDLE_INT_RAW    (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_RAW_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_RAW_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_RAW_S  2
-/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: sleep reject interrupt raw.*/
-#define RTC_CNTL_SLP_REJECT_INT_RAW    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: sleep wakeup interrupt raw.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
-
-#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x48)
-/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST    (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M  (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V  0x1
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S  20
-/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: glitch_det_interrupt state.*/
-#define RTC_CNTL_GLITCH_DET_INT_ST    (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ST_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ST_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_ST_S  19
-/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Touch timeout interrupt state.*/
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST    (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M  (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V  0x1
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S  18
-/* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: cocpu trap interrupt state.*/
-#define RTC_CNTL_COCPU_TRAP_INT_ST    (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_ST_M  (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_ST_V  0x1
-#define RTC_CNTL_COCPU_TRAP_INT_ST_S  17
-/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: xtal32k dead detection interrupt state.*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_ST    (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S  16
-/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: super watch dog interrupt state.*/
-#define RTC_CNTL_SWD_INT_ST    (BIT(15))
-#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ST_V  0x1
-#define RTC_CNTL_SWD_INT_ST_S  15
-/* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: saradc2 interrupt state.*/
-#define RTC_CNTL_SARADC2_INT_ST    (BIT(14))
-#define RTC_CNTL_SARADC2_INT_ST_M  (BIT(14))
-#define RTC_CNTL_SARADC2_INT_ST_V  0x1
-#define RTC_CNTL_SARADC2_INT_ST_S  14
-/* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: riscV cocpu interrupt state.*/
-#define RTC_CNTL_COCPU_INT_ST    (BIT(13))
-#define RTC_CNTL_COCPU_INT_ST_M  (BIT(13))
-#define RTC_CNTL_COCPU_INT_ST_V  0x1
-#define RTC_CNTL_COCPU_INT_ST_S  13
-/* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: tsens interrupt state.*/
-#define RTC_CNTL_TSENS_INT_ST    (BIT(12))
-#define RTC_CNTL_TSENS_INT_ST_M  (BIT(12))
-#define RTC_CNTL_TSENS_INT_ST_V  0x1
-#define RTC_CNTL_TSENS_INT_ST_S  12
-/* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: saradc1 interrupt state.*/
-#define RTC_CNTL_SARADC1_INT_ST    (BIT(11))
-#define RTC_CNTL_SARADC1_INT_ST_M  (BIT(11))
-#define RTC_CNTL_SARADC1_INT_ST_V  0x1
-#define RTC_CNTL_SARADC1_INT_ST_S  11
-/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: RTC main timer interrupt state.*/
-#define RTC_CNTL_MAIN_TIMER_INT_ST    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: brown out interrupt state.*/
-#define RTC_CNTL_BROWN_OUT_INT_ST    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
-/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: touch inactive interrupt state.*/
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ST    (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M  (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V  0x1
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S  8
-/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: touch active interrupt state.*/
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ST    (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M  (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V  0x1
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S  7
-/* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: touch done interrupt state.*/
-#define RTC_CNTL_TOUCH_DONE_INT_ST    (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_ST_M  (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_ST_V  0x1
-#define RTC_CNTL_TOUCH_DONE_INT_ST_S  6
-/* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: ULP-coprocessor interrupt state.*/
-#define RTC_CNTL_ULP_CP_INT_ST    (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ST_M  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ST_V  0x1
-#define RTC_CNTL_ULP_CP_INT_ST_S  5
-/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST    (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M  (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V  0x1
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S  4
-/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC WDT interrupt state.*/
-#define RTC_CNTL_WDT_INT_ST    (BIT(3))
-#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ST_V  0x1
-#define RTC_CNTL_WDT_INT_ST_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: SDIO idle interrupt state.*/
-#define RTC_CNTL_SDIO_IDLE_INT_ST    (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ST_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ST_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_ST_S  2
-/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: sleep reject interrupt state.*/
-#define RTC_CNTL_SLP_REJECT_INT_ST    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: sleep wakeup interrupt state.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ST    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
-
-#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x4C)
-/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR    (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M  (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V  0x1
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S  20
-/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Clear glitch det interrupt state.*/
-#define RTC_CNTL_GLITCH_DET_INT_CLR    (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_CLR_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_CLR_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_CLR_S  19
-/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Clear touch timeout interrupt state.*/
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR    (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M  (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V  0x1
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S  18
-/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Clear cocpu trap interrupt state.*/
-#define RTC_CNTL_COCPU_TRAP_INT_CLR    (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_CLR_M  (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_CLR_V  0x1
-#define RTC_CNTL_COCPU_TRAP_INT_CLR_S  17
-/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Clear RTC WDT interrupt state.*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_CLR    (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S  16
-/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Clear super watch dog interrupt state.*/
-#define RTC_CNTL_SWD_INT_CLR    (BIT(15))
-#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_CLR_V  0x1
-#define RTC_CNTL_SWD_INT_CLR_S  15
-/* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Clear saradc2 interrupt state.*/
-#define RTC_CNTL_SARADC2_INT_CLR    (BIT(14))
-#define RTC_CNTL_SARADC2_INT_CLR_M  (BIT(14))
-#define RTC_CNTL_SARADC2_INT_CLR_V  0x1
-#define RTC_CNTL_SARADC2_INT_CLR_S  14
-/* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Clear riscV cocpu interrupt state.*/
-#define RTC_CNTL_COCPU_INT_CLR    (BIT(13))
-#define RTC_CNTL_COCPU_INT_CLR_M  (BIT(13))
-#define RTC_CNTL_COCPU_INT_CLR_V  0x1
-#define RTC_CNTL_COCPU_INT_CLR_S  13
-/* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Clear tsens interrupt state.*/
-#define RTC_CNTL_TSENS_INT_CLR    (BIT(12))
-#define RTC_CNTL_TSENS_INT_CLR_M  (BIT(12))
-#define RTC_CNTL_TSENS_INT_CLR_V  0x1
-#define RTC_CNTL_TSENS_INT_CLR_S  12
-/* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Clear saradc1 interrupt state.*/
-#define RTC_CNTL_SARADC1_INT_CLR    (BIT(11))
-#define RTC_CNTL_SARADC1_INT_CLR_M  (BIT(11))
-#define RTC_CNTL_SARADC1_INT_CLR_V  0x1
-#define RTC_CNTL_SARADC1_INT_CLR_S  11
-/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Clear RTC main timer interrupt state.*/
-#define RTC_CNTL_MAIN_TIMER_INT_CLR    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
-/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Clear brown out interrupt state.*/
-#define RTC_CNTL_BROWN_OUT_INT_CLR    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
-/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Clear touch inactive interrupt state.*/
-#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR    (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M  (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V  0x1
-#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S  8
-/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Clear touch active interrupt state.*/
-#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR    (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M  (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V  0x1
-#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S  7
-/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Clear touch done interrupt state.*/
-#define RTC_CNTL_TOUCH_DONE_INT_CLR    (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_CLR_M  (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_CLR_V  0x1
-#define RTC_CNTL_TOUCH_DONE_INT_CLR_S  6
-/* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Clear ULP-coprocessor interrupt state.*/
-#define RTC_CNTL_ULP_CP_INT_CLR    (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_CLR_M  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_CLR_V  0x1
-#define RTC_CNTL_ULP_CP_INT_CLR_S  5
-/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR    (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M  (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V  0x1
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S  4
-/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Clear RTC WDT interrupt state.*/
-#define RTC_CNTL_WDT_INT_CLR    (BIT(3))
-#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_CLR_V  0x1
-#define RTC_CNTL_WDT_INT_CLR_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Clear SDIO idle interrupt state.*/
-#define RTC_CNTL_SDIO_IDLE_INT_CLR    (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_CLR_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_CLR_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_CLR_S  2
-/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Clear sleep reject interrupt state.*/
-#define RTC_CNTL_SLP_REJECT_INT_CLR    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Clear sleep wakeup interrupt state.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
-
-#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x50)
-/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_SCRATCH0    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
-#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH0_S  0
-
-#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x54)
-/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_SCRATCH1    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
-#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH1_S  0
-
-#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x58)
-/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_SCRATCH2    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
-#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH2_S  0
-
-#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x5C)
-/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_SCRATCH3    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
-#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH3_S  0
-
-#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
-/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_XTL_EXT_CTR_EN    (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
-#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
-#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
-/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: power down XTAL at high level.*/
-#define RTC_CNTL_XTL_EXT_CTR_LV    (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
-#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
-#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
-/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: XTAL_32K sel. 0: external XTAL_32K.*/
-#define RTC_CNTL_XTAL32K_GPIO_SEL    (BIT(23))
-#define RTC_CNTL_XTAL32K_GPIO_SEL_M  (BIT(23))
-#define RTC_CNTL_XTAL32K_GPIO_SEL_V  0x1
-#define RTC_CNTL_XTAL32K_GPIO_SEL_S  23
-/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
-/*description: state of 32k_wdt.*/
-#define RTC_CNTL_WDT_STATE    0x00000007
-#define RTC_CNTL_WDT_STATE_M  ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S))
-#define RTC_CNTL_WDT_STATE_V  0x7
-#define RTC_CNTL_WDT_STATE_S  20
-/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
-/*description: DAC_XTAL_32K.*/
-#define RTC_CNTL_DAC_XTAL_32K    0x00000007
-#define RTC_CNTL_DAC_XTAL_32K_M  ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S))
-#define RTC_CNTL_DAC_XTAL_32K_V  0x7
-#define RTC_CNTL_DAC_XTAL_32K_S  17
-/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: XPD_XTAL_32K.*/
-#define RTC_CNTL_XPD_XTAL_32K    (BIT(16))
-#define RTC_CNTL_XPD_XTAL_32K_M  (BIT(16))
-#define RTC_CNTL_XPD_XTAL_32K_V  0x1
-#define RTC_CNTL_XPD_XTAL_32K_S  16
-/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
-/*description: DRES_XTAL_32K.*/
-#define RTC_CNTL_DRES_XTAL_32K    0x00000007
-#define RTC_CNTL_DRES_XTAL_32K_M  ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S))
-#define RTC_CNTL_DRES_XTAL_32K_V  0x7
-#define RTC_CNTL_DRES_XTAL_32K_S  13
-/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: xtal_32k gm control.*/
-#define RTC_CNTL_DGM_XTAL_32K    0x00000007
-#define RTC_CNTL_DGM_XTAL_32K_M  ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S))
-#define RTC_CNTL_DGM_XTAL_32K_V  0x7
-#define RTC_CNTL_DGM_XTAL_32K_S  10
-/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 0: single-end buffer 1: differential buffer.*/
-#define RTC_CNTL_DBUF_XTAL_32K    (BIT(9))
-#define RTC_CNTL_DBUF_XTAL_32K_M  (BIT(9))
-#define RTC_CNTL_DBUF_XTAL_32K_V  0x1
-#define RTC_CNTL_DBUF_XTAL_32K_S  9
-/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: apply an internal clock to help xtal 32k to start.*/
-#define RTC_CNTL_ENCKINIT_XTAL_32K    (BIT(8))
-#define RTC_CNTL_ENCKINIT_XTAL_32K_M  (BIT(8))
-#define RTC_CNTL_ENCKINIT_XTAL_32K_V  0x1
-#define RTC_CNTL_ENCKINIT_XTAL_32K_S  8
-/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: Xtal 32k xpd control by sw or fsm.*/
-#define RTC_CNTL_XTAL32K_XPD_FORCE    (BIT(7))
-#define RTC_CNTL_XTAL32K_XPD_FORCE_M  (BIT(7))
-#define RTC_CNTL_XTAL32K_XPD_FORCE_V  0x1
-#define RTC_CNTL_XTAL32K_XPD_FORCE_S  7
-/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: xtal 32k switch back xtal when xtal is restarted.*/
-#define RTC_CNTL_XTAL32K_AUTO_RETURN    (BIT(6))
-#define RTC_CNTL_XTAL32K_AUTO_RETURN_M  (BIT(6))
-#define RTC_CNTL_XTAL32K_AUTO_RETURN_V  0x1
-#define RTC_CNTL_XTAL32K_AUTO_RETURN_S  6
-/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: xtal 32k restart xtal when xtal is dead.*/
-#define RTC_CNTL_XTAL32K_AUTO_RESTART    (BIT(5))
-#define RTC_CNTL_XTAL32K_AUTO_RESTART_M  (BIT(5))
-#define RTC_CNTL_XTAL32K_AUTO_RESTART_V  0x1
-#define RTC_CNTL_XTAL32K_AUTO_RESTART_S  5
-/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: xtal 32k switch to back up clock when xtal is dead.*/
-#define RTC_CNTL_XTAL32K_AUTO_BACKUP    (BIT(4))
-#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M  (BIT(4))
-#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V  0x1
-#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S  4
-/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: xtal 32k external xtal clock force on.*/
-#define RTC_CNTL_XTAL32K_EXT_CLK_FO    (BIT(3))
-#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M  (BIT(3))
-#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V  0x1
-#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S  3
-/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog sw reset.*/
-#define RTC_CNTL_XTAL32K_WDT_RESET    (BIT(2))
-#define RTC_CNTL_XTAL32K_WDT_RESET_M  (BIT(2))
-#define RTC_CNTL_XTAL32K_WDT_RESET_V  0x1
-#define RTC_CNTL_XTAL32K_WDT_RESET_S  2
-/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog clock force on.*/
-#define RTC_CNTL_XTAL32K_WDT_CLK_FO    (BIT(1))
-#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M  (BIT(1))
-#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V  0x1
-#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S  1
-/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: xtal 32k watch dog enable.*/
-#define RTC_CNTL_XTAL32K_WDT_EN    (BIT(0))
-#define RTC_CNTL_XTAL32K_WDT_EN_M  (BIT(0))
-#define RTC_CNTL_XTAL32K_WDT_EN_V  0x1
-#define RTC_CNTL_XTAL32K_WDT_EN_S  0
-
-#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x64)
-/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_EXT_WAKEUP1_LV    (BIT(31))
-#define RTC_CNTL_EXT_WAKEUP1_LV_M  (BIT(31))
-#define RTC_CNTL_EXT_WAKEUP1_LV_V  0x1
-#define RTC_CNTL_EXT_WAKEUP1_LV_S  31
-/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: 0: external wakeup at low level.*/
-#define RTC_CNTL_EXT_WAKEUP0_LV    (BIT(30))
-#define RTC_CNTL_EXT_WAKEUP0_LV_M  (BIT(30))
-#define RTC_CNTL_EXT_WAKEUP0_LV_V  0x1
-#define RTC_CNTL_EXT_WAKEUP0_LV_S  30
-/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: enable filter for gpio wakeup event.*/
-#define RTC_CNTL_GPIO_WAKEUP_FILTER    (BIT(29))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(29))
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
-#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  29
-
-#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x68)
-/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: enable reject for deep sleep.*/
-#define RTC_CNTL_DEEP_SLP_REJECT_EN    (BIT(31))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
-#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
-/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: enable reject for light sleep.*/
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN    (BIT(30))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
-#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
-/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */
-/*description: sleep reject enable.*/
-#define RTC_CNTL_SLEEP_REJECT_ENA    0x0003FFFF
-#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
-#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
-#define RTC_CNTL_SLEEP_REJECT_ENA_S  12
-
-#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x6C)
-/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
-/*description: .*/
-#define RTC_CNTL_CPUPERIOD_SEL    0x00000003
-#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
-#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
-#define RTC_CNTL_CPUPERIOD_SEL_S  30
-/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: CPU sel option.*/
-#define RTC_CNTL_CPUSEL_CONF    (BIT(29))
-#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
-#define RTC_CNTL_CPUSEL_CONF_V  0x1
-#define RTC_CNTL_CPUSEL_CONF_S  29
-
-#define RTC_CNTL_SDIO_ACT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
-/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */
-/*description: .*/
-#define RTC_CNTL_SDIO_ACT_DNUM    0x000003FF
-#define RTC_CNTL_SDIO_ACT_DNUM_M  ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S))
-#define RTC_CNTL_SDIO_ACT_DNUM_V  0x3FF
-#define RTC_CNTL_SDIO_ACT_DNUM_S  22
-
-#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x74)
-/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: .*/
-#define RTC_CNTL_ANA_CLK_RTC_SEL    0x00000003
-#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
-#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
-#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
-/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: fast_clk_rtc sel. 0: XTAL div 2.*/
-#define RTC_CNTL_FAST_CLK_RTC_SEL    (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
-#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
-#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
-/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: .*/
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING    (BIT(28))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
-/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING    (BIT(27))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
-#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
-/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: CK8M force power up.*/
-#define RTC_CNTL_CK8M_FORCE_PU    (BIT(26))
-#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
-#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
-#define RTC_CNTL_CK8M_FORCE_PU_S  26
-/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: CK8M force power down.*/
-#define RTC_CNTL_CK8M_FORCE_PD    (BIT(25))
-#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
-#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
-#define RTC_CNTL_CK8M_FORCE_PD_S  25
-/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */
-/*description: CK8M_DFREQ.*/
-#define RTC_CNTL_CK8M_DFREQ    0x000000FF
-#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
-#define RTC_CNTL_CK8M_DFREQ_V  0xFF
-#define RTC_CNTL_CK8M_DFREQ_S  17
-/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: CK8M force no gating during sleep.*/
-#define RTC_CNTL_CK8M_FORCE_NOGATING    (BIT(16))
-#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
-#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
-/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: XTAL force no gating during sleep.*/
-#define RTC_CNTL_XTAL_FORCE_NOGATING    (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
-#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
-/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: divider = reg_ck8m_div_sel + 1.*/
-#define RTC_CNTL_CK8M_DIV_SEL    0x00000007
-#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
-#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
-#define RTC_CNTL_CK8M_DIV_SEL_S  12
-/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: enable CK8M for digital core (no relationship with RTC core).*/
-#define RTC_CNTL_DIG_CLK8M_EN    (BIT(10))
-#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
-#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
-#define RTC_CNTL_DIG_CLK8M_EN_S  10
-/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
-/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/
-#define RTC_CNTL_DIG_CLK8M_D256_EN    (BIT(9))
-#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
-#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
-#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
-/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/
-#define RTC_CNTL_DIG_XTAL32K_EN    (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
-#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
-#define RTC_CNTL_DIG_XTAL32K_EN_S  8
-/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: 1: CK8M_D256_OUT is actually CK8M.*/
-#define RTC_CNTL_ENB_CK8M_DIV    (BIT(7))
-#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
-#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
-#define RTC_CNTL_ENB_CK8M_DIV_S  7
-/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: disable CK8M and CK8M_D256_OUT.*/
-#define RTC_CNTL_ENB_CK8M    (BIT(6))
-#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
-#define RTC_CNTL_ENB_CK8M_V  0x1
-#define RTC_CNTL_ENB_CK8M_S  6
-/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
-/*description: CK8M_D256_OUT divider. 00: div128.*/
-#define RTC_CNTL_CK8M_DIV    0x00000003
-#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
-#define RTC_CNTL_CK8M_DIV_V  0x3
-#define RTC_CNTL_CK8M_DIV_S  4
-/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/
-#define RTC_CNTL_CK8M_DIV_SEL_VLD    (BIT(3))
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
-#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
-/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING    (BIT(2))
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
-#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
-/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING    (BIT(1))
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
-#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
-
-#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x78)
-/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE    (BIT(31))
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
-#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
-/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */
-/*description: .*/
-#define RTC_CNTL_ANA_CLK_DIV    0x000000FF
-#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
-#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
-#define RTC_CNTL_ANA_CLK_DIV_S  23
-/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/
-#define RTC_CNTL_ANA_CLK_DIV_VLD    (BIT(22))
-#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
-#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
-#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
-
-#define RTC_CNTL_SDIO_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x7C)
-/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_XPD_SDIO_REG    (BIT(31))
-#define RTC_CNTL_XPD_SDIO_REG_M  (BIT(31))
-#define RTC_CNTL_XPD_SDIO_REG_V  0x1
-#define RTC_CNTL_XPD_SDIO_REG_S  31
-/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
-/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1.*/
-#define RTC_CNTL_DREFH_SDIO    0x00000003
-#define RTC_CNTL_DREFH_SDIO_M  ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
-#define RTC_CNTL_DREFH_SDIO_V  0x3
-#define RTC_CNTL_DREFH_SDIO_S  29
-/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */
-/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1.*/
-#define RTC_CNTL_DREFM_SDIO    0x00000003
-#define RTC_CNTL_DREFM_SDIO_M  ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
-#define RTC_CNTL_DREFM_SDIO_V  0x3
-#define RTC_CNTL_DREFM_SDIO_S  27
-/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
-/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1.*/
-#define RTC_CNTL_DREFL_SDIO    0x00000003
-#define RTC_CNTL_DREFL_SDIO_M  ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
-#define RTC_CNTL_DREFL_SDIO_V  0x3
-#define RTC_CNTL_DREFL_SDIO_S  25
-/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
-/*description: read only register for REG1P8_READY.*/
-#define RTC_CNTL_REG1P8_READY    (BIT(24))
-#define RTC_CNTL_REG1P8_READY_M  (BIT(24))
-#define RTC_CNTL_REG1P8_READY_V  0x1
-#define RTC_CNTL_REG1P8_READY_S  24
-/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
-/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/
-#define RTC_CNTL_SDIO_TIEH    (BIT(23))
-#define RTC_CNTL_SDIO_TIEH_M  (BIT(23))
-#define RTC_CNTL_SDIO_TIEH_V  0x1
-#define RTC_CNTL_SDIO_TIEH_S  23
-/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: 1: use SW option to control SDIO_REG.*/
-#define RTC_CNTL_SDIO_FORCE    (BIT(22))
-#define RTC_CNTL_SDIO_FORCE_M  (BIT(22))
-#define RTC_CNTL_SDIO_FORCE_V  0x1
-#define RTC_CNTL_SDIO_FORCE_S  22
-/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
-/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0.*/
-#define RTC_CNTL_SDIO_PD_EN    (BIT(21))
-#define RTC_CNTL_SDIO_PD_EN_M  (BIT(21))
-#define RTC_CNTL_SDIO_PD_EN_V  0x1
-#define RTC_CNTL_SDIO_PD_EN_S  21
-/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */
-/*description: enable current limit.*/
-#define RTC_CNTL_SDIO_ENCURLIM    (BIT(20))
-#define RTC_CNTL_SDIO_ENCURLIM_M  (BIT(20))
-#define RTC_CNTL_SDIO_ENCURLIM_V  0x1
-#define RTC_CNTL_SDIO_ENCURLIM_S  20
-/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: select current limit mode.*/
-#define RTC_CNTL_SDIO_MODECURLIM    (BIT(19))
-#define RTC_CNTL_SDIO_MODECURLIM_M  (BIT(19))
-#define RTC_CNTL_SDIO_MODECURLIM_V  0x1
-#define RTC_CNTL_SDIO_MODECURLIM_S  19
-/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */
-/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d).*/
-#define RTC_CNTL_SDIO_DCURLIM    0x00000007
-#define RTC_CNTL_SDIO_DCURLIM_M  ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S))
-#define RTC_CNTL_SDIO_DCURLIM_V  0x7
-#define RTC_CNTL_SDIO_DCURLIM_S  16
-/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */
-/*description: 0 to set init[1:0]=0.*/
-#define RTC_CNTL_SDIO_EN_INITI    (BIT(15))
-#define RTC_CNTL_SDIO_EN_INITI_M  (BIT(15))
-#define RTC_CNTL_SDIO_EN_INITI_V  0x1
-#define RTC_CNTL_SDIO_EN_INITI_S  15
-/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */
-/*description: add resistor from ldo output to ground. 0: no res.*/
-#define RTC_CNTL_SDIO_INITI    0x00000003
-#define RTC_CNTL_SDIO_INITI_M  ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
-#define RTC_CNTL_SDIO_INITI_V  0x3
-#define RTC_CNTL_SDIO_INITI_S  13
-/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
-/*description: ability to prevent LDO from overshoot.*/
-#define RTC_CNTL_SDIO_DCAP    0x00000003
-#define RTC_CNTL_SDIO_DCAP_M  ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S))
-#define RTC_CNTL_SDIO_DCAP_V  0x3
-#define RTC_CNTL_SDIO_DCAP_S  11
-/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */
-/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current.*/
-#define RTC_CNTL_SDIO_DTHDRV    0x00000003
-#define RTC_CNTL_SDIO_DTHDRV_M  ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S))
-#define RTC_CNTL_SDIO_DTHDRV_V  0x3
-#define RTC_CNTL_SDIO_DTHDRV_S  9
-/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
-/*description: timer count to apply reg_sdio_dcap after sdio power on.*/
-#define RTC_CNTL_SDIO_TIMER_TARGET    0x000000FF
-#define RTC_CNTL_SDIO_TIMER_TARGET_M  ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S))
-#define RTC_CNTL_SDIO_TIMER_TARGET_V  0xFF
-#define RTC_CNTL_SDIO_TIMER_TARGET_S  0
-
-#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x80)
-/* RTC_CNTL_DBG_ATTEN_WAKEUP : R/W ;bitpos:[29:26] ;default: 4'd0 ; */
-/*description: .*/
-#define RTC_CNTL_DBG_ATTEN_WAKEUP    0x0000000F
-#define RTC_CNTL_DBG_ATTEN_WAKEUP_M  ((RTC_CNTL_DBG_ATTEN_WAKEUP_V)<<(RTC_CNTL_DBG_ATTEN_WAKEUP_S))
-#define RTC_CNTL_DBG_ATTEN_WAKEUP_V  0xF
-#define RTC_CNTL_DBG_ATTEN_WAKEUP_S  26
-/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */
-/*description: DBG_ATTEN when rtc in monitor state.*/
-#define RTC_CNTL_DBG_ATTEN_MONITOR    0x0000000F
-#define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
-#define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
-#define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
-/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */
-/*description: DBG_ATTEN when rtc in sleep state.*/
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP    0x0000000F
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
-#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
-/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: bias_sleep when rtc in monitor state.*/
-#define RTC_CNTL_BIAS_SLEEP_MONITOR    (BIT(17))
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
-#define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
-/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: bias_sleep when rtc in sleep_state.*/
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP    (BIT(16))
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
-#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
-/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: xpd cur when rtc in monitor state.*/
-#define RTC_CNTL_PD_CUR_MONITOR    (BIT(15))
-#define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
-#define RTC_CNTL_PD_CUR_MONITOR_V  0x1
-#define RTC_CNTL_PD_CUR_MONITOR_S  15
-/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: xpd cur when rtc in sleep_state.*/
-#define RTC_CNTL_PD_CUR_DEEP_SLP    (BIT(14))
-#define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
-#define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
-#define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
-/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_BIAS_BUF_MONITOR    (BIT(13))
-#define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
-#define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
-#define RTC_CNTL_BIAS_BUF_MONITOR_S  13
-/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP    (BIT(12))
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
-#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
-/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: .*/
-#define RTC_CNTL_BIAS_BUF_WAKE    (BIT(11))
-#define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
-#define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
-#define RTC_CNTL_BIAS_BUF_WAKE_S  11
-/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_BIAS_BUF_IDLE    (BIT(10))
-#define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
-#define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
-#define RTC_CNTL_BIAS_BUF_IDLE_S  10
-
-#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x84)
-/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
-/*description: .*/
-#define RTC_CNTL_REGULATOR_FORCE_PU    (BIT(31))
-#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
-#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
-#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
-/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0
-.8v or lower ).*/
-#define RTC_CNTL_REGULATOR_FORCE_PD    (BIT(30))
-#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
-#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
-#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
-/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
-/*description: RTC_DBOOST force power up.*/
-#define RTC_CNTL_DBOOST_FORCE_PU    (BIT(29))
-#define RTC_CNTL_DBOOST_FORCE_PU_M  (BIT(29))
-#define RTC_CNTL_DBOOST_FORCE_PU_V  0x1
-#define RTC_CNTL_DBOOST_FORCE_PU_S  29
-/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: RTC_DBOOST force power down.*/
-#define RTC_CNTL_DBOOST_FORCE_PD    (BIT(28))
-#define RTC_CNTL_DBOOST_FORCE_PD_M  (BIT(28))
-#define RTC_CNTL_DBOOST_FORCE_PD_V  0x1
-#define RTC_CNTL_DBOOST_FORCE_PD_S  28
-/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
- * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
- * Valid if RTC_CNTL_DBG_ATTEN is 0.
- */
-#define RTC_CNTL_DIG_DBIAS_0V85  0
-#define RTC_CNTL_DIG_DBIAS_0V90  1
-#define RTC_CNTL_DIG_DBIAS_0V95  2
-#define RTC_CNTL_DIG_DBIAS_1V00  3
-#define RTC_CNTL_DIG_DBIAS_1V05  4
-#define RTC_CNTL_DIG_DBIAS_1V10  5
-#define RTC_CNTL_DIG_DBIAS_1V15  6
-#define RTC_CNTL_DIG_DBIAS_1V20  7
-
-
-/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
-/*description: SCK_DCAP.*/
-#define RTC_CNTL_SCK_DCAP    0x000000FF
-#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
-#define RTC_CNTL_SCK_DCAP_V  0xFF
-#define RTC_CNTL_SCK_DCAP_S  14
-/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_DIG_CAL_EN    (BIT(7))
-#define RTC_CNTL_DIG_CAL_EN_M  (BIT(7))
-#define RTC_CNTL_DIG_CAL_EN_V  0x1
-#define RTC_CNTL_DIG_CAL_EN_S  7
-
-#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x88)
-/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: rtc pad force hold.*/
-#define RTC_CNTL_PAD_FORCE_HOLD    (BIT(21))
-#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
-#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
-#define RTC_CNTL_PAD_FORCE_HOLD_S  21
-/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: enable power down rtc_peri in sleep .*/
-#define RTC_CNTL_PD_EN    (BIT(20))
-#define RTC_CNTL_PD_EN_M  (BIT(20))
-#define RTC_CNTL_PD_EN_V  0x1
-#define RTC_CNTL_PD_EN_S  20
-/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: rtc_peri force power up.*/
-#define RTC_CNTL_FORCE_PU    (BIT(19))
-#define RTC_CNTL_FORCE_PU_M  (BIT(19))
-#define RTC_CNTL_FORCE_PU_V  0x1
-#define RTC_CNTL_FORCE_PU_S  19
-/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: rtc_peri force power down.*/
-#define RTC_CNTL_FORCE_PD    (BIT(18))
-#define RTC_CNTL_FORCE_PD_M  (BIT(18))
-#define RTC_CNTL_FORCE_PD_V  0x1
-#define RTC_CNTL_FORCE_PD_S  18
-/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: RTC memory force no PD.*/
-#define RTC_CNTL_SLOWMEM_FORCE_LPU    (BIT(11))
-#define RTC_CNTL_SLOWMEM_FORCE_LPU_M  (BIT(11))
-#define RTC_CNTL_SLOWMEM_FORCE_LPU_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_LPU_S  11
-/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: RTC memory force PD.*/
-#define RTC_CNTL_SLOWMEM_FORCE_LPD    (BIT(10))
-#define RTC_CNTL_SLOWMEM_FORCE_LPD_M  (BIT(10))
-#define RTC_CNTL_SLOWMEM_FORCE_LPD_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_LPD_S  10
-/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: RTC memory  PD following CPU.*/
-#define RTC_CNTL_SLOWMEM_FOLW_CPU    (BIT(9))
-#define RTC_CNTL_SLOWMEM_FOLW_CPU_M  (BIT(9))
-#define RTC_CNTL_SLOWMEM_FOLW_CPU_V  0x1
-#define RTC_CNTL_SLOWMEM_FOLW_CPU_S  9
-/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: Fast RTC memory force no PD.*/
-#define RTC_CNTL_FASTMEM_FORCE_LPU    (BIT(8))
-#define RTC_CNTL_FASTMEM_FORCE_LPU_M  (BIT(8))
-#define RTC_CNTL_FASTMEM_FORCE_LPU_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_LPU_S  8
-/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Fast RTC memory force PD.*/
-#define RTC_CNTL_FASTMEM_FORCE_LPD    (BIT(7))
-#define RTC_CNTL_FASTMEM_FORCE_LPD_M  (BIT(7))
-#define RTC_CNTL_FASTMEM_FORCE_LPD_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_LPD_S  7
-/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: 1: Fast RTC memory PD following CPU.*/
-#define RTC_CNTL_FASTMEM_FOLW_CPU    (BIT(6))
-#define RTC_CNTL_FASTMEM_FOLW_CPU_M  (BIT(6))
-#define RTC_CNTL_FASTMEM_FOLW_CPU_V  0x1
-#define RTC_CNTL_FASTMEM_FOLW_CPU_S  6
-/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */
-/*description: rtc_peri force no ISO.*/
-#define RTC_CNTL_FORCE_NOISO    (BIT(5))
-#define RTC_CNTL_FORCE_NOISO_M  (BIT(5))
-#define RTC_CNTL_FORCE_NOISO_V  0x1
-#define RTC_CNTL_FORCE_NOISO_S  5
-/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: rtc_peri force ISO.*/
-#define RTC_CNTL_FORCE_ISO    (BIT(4))
-#define RTC_CNTL_FORCE_ISO_M  (BIT(4))
-#define RTC_CNTL_FORCE_ISO_V  0x1
-#define RTC_CNTL_FORCE_ISO_S  4
-/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: RTC memory force ISO.*/
-#define RTC_CNTL_SLOWMEM_FORCE_ISO    (BIT(3))
-#define RTC_CNTL_SLOWMEM_FORCE_ISO_M  (BIT(3))
-#define RTC_CNTL_SLOWMEM_FORCE_ISO_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_ISO_S  3
-/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: RTC memory force no ISO.*/
-#define RTC_CNTL_SLOWMEM_FORCE_NOISO    (BIT(2))
-#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M  (BIT(2))
-#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V  0x1
-#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S  2
-/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Fast RTC memory force ISO.*/
-#define RTC_CNTL_FASTMEM_FORCE_ISO    (BIT(1))
-#define RTC_CNTL_FASTMEM_FORCE_ISO_M  (BIT(1))
-#define RTC_CNTL_FASTMEM_FORCE_ISO_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_ISO_S  1
-/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Fast RTC memory force no ISO.*/
-#define RTC_CNTL_FASTMEM_FORCE_NOISO    (BIT(0))
-#define RTC_CNTL_FASTMEM_FORCE_NOISO_M  (BIT(0))
-#define RTC_CNTL_FASTMEM_FORCE_NOISO_V  0x1
-#define RTC_CNTL_FASTMEM_FORCE_NOISO_S  0
-
-#define RTC_CNTL_REGULATOR_DRV_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x8C)
-/* RTC_CNTL_DG_VDD_DRV_B_MONITOR : R/W ;bitpos:[27:20] ;default: 8'h0 ; */
-/*description: .*/
-#define RTC_CNTL_DG_VDD_DRV_B_MONITOR    0x000000FF
-#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_M  ((RTC_CNTL_DG_VDD_DRV_B_MONITOR_V)<<(RTC_CNTL_DG_VDD_DRV_B_MONITOR_S))
-#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_V  0xFF
-#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_S  20
-/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[19:12] ;default: 8'h0 ; */
-/*description: .*/
-#define RTC_CNTL_DG_VDD_DRV_B_SLP    0x000000FF
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
-#define RTC_CNTL_DG_VDD_DRV_B_SLP_S  12
-/* RTC_CNTL_REGULATOR_DRV_B_SLP : R/W ;bitpos:[11:6] ;default: 6'b0 ; */
-/*description: .*/
-#define RTC_CNTL_REGULATOR_DRV_B_SLP    0x0000003F
-#define RTC_CNTL_REGULATOR_DRV_B_SLP_M  ((RTC_CNTL_REGULATOR_DRV_B_SLP_V)<<(RTC_CNTL_REGULATOR_DRV_B_SLP_S))
-#define RTC_CNTL_REGULATOR_DRV_B_SLP_V  0x3F
-#define RTC_CNTL_REGULATOR_DRV_B_SLP_S  6
-/* RTC_CNTL_REGULATOR_DRV_B_MONITOR : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
-/*description: .*/
-#define RTC_CNTL_REGULATOR_DRV_B_MONITOR    0x0000003F
-#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_M  ((RTC_CNTL_REGULATOR_DRV_B_MONITOR_V)<<(RTC_CNTL_REGULATOR_DRV_B_MONITOR_S))
-#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_V  0x3F
-#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_S  0
-
-#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x90)
-/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_DG_WRAP_PD_EN    (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
-#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
-#define RTC_CNTL_DG_WRAP_PD_EN_S  31
-/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */
-/*description: enable power down wifi in sleep.*/
-#define RTC_CNTL_WIFI_PD_EN    (BIT(30))
-#define RTC_CNTL_WIFI_PD_EN_M  (BIT(30))
-#define RTC_CNTL_WIFI_PD_EN_V  0x1
-#define RTC_CNTL_WIFI_PD_EN_S  30
-/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */
-/*description: enable power down internal SRAM 4 in sleep.*/
-#define RTC_CNTL_CPU_TOP_PD_EN    (BIT(29))
-#define RTC_CNTL_CPU_TOP_PD_EN_M  (BIT(29))
-#define RTC_CNTL_CPU_TOP_PD_EN_V  0x1
-#define RTC_CNTL_CPU_TOP_PD_EN_S  29
-/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */
-/*description: enable power down internal SRAM 3 in sleep.*/
-#define RTC_CNTL_DG_PERI_PD_EN    (BIT(28))
-#define RTC_CNTL_DG_PERI_PD_EN_M  (BIT(28))
-#define RTC_CNTL_DG_PERI_PD_EN_V  0x1
-#define RTC_CNTL_DG_PERI_PD_EN_S  28
-/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */
-/*description: digital dcdc force power up.*/
-#define RTC_CNTL_CPU_TOP_FORCE_PU    (BIT(22))
-#define RTC_CNTL_CPU_TOP_FORCE_PU_M  (BIT(22))
-#define RTC_CNTL_CPU_TOP_FORCE_PU_V  0x1
-#define RTC_CNTL_CPU_TOP_FORCE_PU_S  22
-/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: digital dcdc force power down.*/
-#define RTC_CNTL_CPU_TOP_FORCE_PD    (BIT(21))
-#define RTC_CNTL_CPU_TOP_FORCE_PD_M  (BIT(21))
-#define RTC_CNTL_CPU_TOP_FORCE_PD_V  0x1
-#define RTC_CNTL_CPU_TOP_FORCE_PD_S  21
-/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
-/*description: digital core force power up.*/
-#define RTC_CNTL_DG_WRAP_FORCE_PU    (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
-#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
-/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: digital core force power down.*/
-#define RTC_CNTL_DG_WRAP_FORCE_PD    (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
-#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
-/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
-/*description: wifi force power up.*/
-#define RTC_CNTL_WIFI_FORCE_PU    (BIT(18))
-#define RTC_CNTL_WIFI_FORCE_PU_M  (BIT(18))
-#define RTC_CNTL_WIFI_FORCE_PU_V  0x1
-#define RTC_CNTL_WIFI_FORCE_PU_S  18
-/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: wifi force power down.*/
-#define RTC_CNTL_WIFI_FORCE_PD    (BIT(17))
-#define RTC_CNTL_WIFI_FORCE_PD_M  (BIT(17))
-#define RTC_CNTL_WIFI_FORCE_PD_V  0x1
-#define RTC_CNTL_WIFI_FORCE_PD_S  17
-/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */
-/*description: internal SRAM 3 force power up.*/
-#define RTC_CNTL_DG_PERI_FORCE_PU    (BIT(14))
-#define RTC_CNTL_DG_PERI_FORCE_PU_M  (BIT(14))
-#define RTC_CNTL_DG_PERI_FORCE_PU_V  0x1
-#define RTC_CNTL_DG_PERI_FORCE_PU_S  14
-/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: internal SRAM 3 force power down.*/
-#define RTC_CNTL_DG_PERI_FORCE_PD    (BIT(13))
-#define RTC_CNTL_DG_PERI_FORCE_PD_M  (BIT(13))
-#define RTC_CNTL_DG_PERI_FORCE_PD_V  0x1
-#define RTC_CNTL_DG_PERI_FORCE_PD_S  13
-/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
-/*description: internal SRAM 2 force power up.*/
-#define RTC_CNTL_BT_FORCE_PU    (BIT(12))
-#define RTC_CNTL_BT_FORCE_PU_M  (BIT(12))
-#define RTC_CNTL_BT_FORCE_PU_V  0x1
-#define RTC_CNTL_BT_FORCE_PU_S  12
-/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: internal SRAM 2 force power down.*/
-#define RTC_CNTL_BT_FORCE_PD    (BIT(11))
-#define RTC_CNTL_BT_FORCE_PD_M  (BIT(11))
-#define RTC_CNTL_BT_FORCE_PD_V  0x1
-#define RTC_CNTL_BT_FORCE_PD_S  11
-/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: memories in digital core force no PD in sleep.*/
-#define RTC_CNTL_LSLP_MEM_FORCE_PU    (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(4))
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
-#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  4
-/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: memories in digital core force PD in sleep.*/
-#define RTC_CNTL_LSLP_MEM_FORCE_PD    (BIT(3))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(3))
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
-#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
-
-#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x94)
-/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
-/*description: .*/
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO    (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
-/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: digital core force ISO.*/
-#define RTC_CNTL_DG_WRAP_FORCE_ISO    (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
-/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
-/*description: wifi force no ISO.*/
-#define RTC_CNTL_WIFI_FORCE_NOISO    (BIT(29))
-#define RTC_CNTL_WIFI_FORCE_NOISO_M  (BIT(29))
-#define RTC_CNTL_WIFI_FORCE_NOISO_V  0x1
-#define RTC_CNTL_WIFI_FORCE_NOISO_S  29
-/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: wifi force ISO.*/
-#define RTC_CNTL_WIFI_FORCE_ISO    (BIT(28))
-#define RTC_CNTL_WIFI_FORCE_ISO_M  (BIT(28))
-#define RTC_CNTL_WIFI_FORCE_ISO_V  0x1
-#define RTC_CNTL_WIFI_FORCE_ISO_S  28
-/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: internal SRAM 4 force no ISO.*/
-#define RTC_CNTL_CPU_TOP_FORCE_NOISO    (BIT(27))
-#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M  (BIT(27))
-#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V  0x1
-#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S  27
-/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: internal SRAM 4 force ISO.*/
-#define RTC_CNTL_CPU_TOP_FORCE_ISO    (BIT(26))
-#define RTC_CNTL_CPU_TOP_FORCE_ISO_M  (BIT(26))
-#define RTC_CNTL_CPU_TOP_FORCE_ISO_V  0x1
-#define RTC_CNTL_CPU_TOP_FORCE_ISO_S  26
-/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
-/*description: internal SRAM 3 force no ISO.*/
-#define RTC_CNTL_DG_PERI_FORCE_NOISO    (BIT(25))
-#define RTC_CNTL_DG_PERI_FORCE_NOISO_M  (BIT(25))
-#define RTC_CNTL_DG_PERI_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_PERI_FORCE_NOISO_S  25
-/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: internal SRAM 3 force ISO.*/
-#define RTC_CNTL_DG_PERI_FORCE_ISO    (BIT(24))
-#define RTC_CNTL_DG_PERI_FORCE_ISO_M  (BIT(24))
-#define RTC_CNTL_DG_PERI_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_PERI_FORCE_ISO_S  24
-/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
-/*description: internal SRAM 2 force no ISO.*/
-#define RTC_CNTL_BT_FORCE_NOISO    (BIT(23))
-#define RTC_CNTL_BT_FORCE_NOISO_M  (BIT(23))
-#define RTC_CNTL_BT_FORCE_NOISO_V  0x1
-#define RTC_CNTL_BT_FORCE_NOISO_S  23
-/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: internal SRAM 2 force ISO.*/
-#define RTC_CNTL_BT_FORCE_ISO    (BIT(22))
-#define RTC_CNTL_BT_FORCE_ISO_M  (BIT(22))
-#define RTC_CNTL_BT_FORCE_ISO_V  0x1
-#define RTC_CNTL_BT_FORCE_ISO_S  22
-/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: digital pad force hold.*/
-#define RTC_CNTL_DG_PAD_FORCE_HOLD    (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
-/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
-/*description: digital pad force un-hold.*/
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD    (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
-/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: digital pad force ISO.*/
-#define RTC_CNTL_DG_PAD_FORCE_ISO    (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
-#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
-/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
-/*description: digital pad force no ISO.*/
-#define RTC_CNTL_DG_PAD_FORCE_NOISO    (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
-#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
-/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: digital pad enable auto-hold.*/
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN    (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
-#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
-/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
-/*description: wtite only register to clear digital pad auto-hold.*/
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD    (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
-#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
-/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
-/*description: read only register to indicate digital pad auto-hold status.*/
-#define RTC_CNTL_DG_PAD_AUTOHOLD    (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
-#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
-#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
-/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_DIG_ISO_FORCE_ON    (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
-#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
-#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
-/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */
-/*description: .*/
-#define RTC_CNTL_DIG_ISO_FORCE_OFF    (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
-#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
-
-#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x98)
-/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define RTC_CNTL_WDT_EN    (BIT(31))
-#define RTC_CNTL_WDT_EN_M  (BIT(31))
-#define RTC_CNTL_WDT_EN_V  0x1
-#define RTC_CNTL_WDT_EN_S  31
-/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en.*/
-#define RTC_CNTL_WDT_STG0    0x00000007
-#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
-#define RTC_CNTL_WDT_STG0_V  0x7
-#define RTC_CNTL_WDT_STG0_S  28
-/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en.*/
-#define RTC_CNTL_WDT_STG1    0x00000007
-#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
-#define RTC_CNTL_WDT_STG1_V  0x7
-#define RTC_CNTL_WDT_STG1_S  25
-/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en.*/
-#define RTC_CNTL_WDT_STG2    0x00000007
-#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
-#define RTC_CNTL_WDT_STG2_V  0x7
-#define RTC_CNTL_WDT_STG2_S  22
-/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
-/*description: 1: interrupt stage en.*/
-#define RTC_CNTL_WDT_STG3    0x00000007
-#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
-#define RTC_CNTL_WDT_STG3_V  0x7
-#define RTC_CNTL_WDT_STG3_S  19
-
-/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
-/*description: CPU reset counter length.*/
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH    0x00000007
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
-#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
-/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
-/*description: system reset counter length.*/
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH    0x00000007
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
-#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
-/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: enable WDT in flash boot.*/
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN    (BIT(12))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
-#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
-/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: enable WDT reset PRO CPU.*/
-#define RTC_CNTL_WDT_PROCPU_RESET_EN    (BIT(11))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
-/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: enable WDT reset APP CPU.*/
-#define RTC_CNTL_WDT_APPCPU_RESET_EN    (BIT(10))
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_M  (BIT(10))
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_APPCPU_RESET_EN_S  10
-/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */
-/*description: pause WDT in sleep.*/
-#define RTC_CNTL_WDT_PAUSE_IN_SLP    (BIT(9))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
-#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
-/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: wdt reset whole chip enable.*/
-#define RTC_CNTL_WDT_CHIP_RESET_EN    (BIT(8))
-#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
-#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
-#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
-/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */
-/*description: chip reset siginal pulse width.*/
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH    0x000000FF
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
-#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
-
-#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x9C)
-/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
-/*description: .*/
-#define RTC_CNTL_WDT_STG0_HOLD    0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
-#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG0_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0xA0)
-/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
-/*description: .*/
-#define RTC_CNTL_WDT_STG1_HOLD    0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
-#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG1_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0xA4)
-/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: .*/
-#define RTC_CNTL_WDT_STG2_HOLD    0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
-#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG2_HOLD_S  0
-
-#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0xA8)
-/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
-/*description: .*/
-#define RTC_CNTL_WDT_STG3_HOLD    0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
-#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_STG3_HOLD_S  0
-
-#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0xAC)
-/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_WDT_FEED    (BIT(31))
-#define RTC_CNTL_WDT_FEED_M  (BIT(31))
-#define RTC_CNTL_WDT_FEED_V  0x1
-#define RTC_CNTL_WDT_FEED_S  31
-
-#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xB0)
-/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
-/*description: .*/
-#define RTC_CNTL_WDT_WKEY    0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
-#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
-#define RTC_CNTL_WDT_WKEY_S  0
-
-#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xB4)
-/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: automatically feed swd when int comes.*/
-#define RTC_CNTL_SWD_AUTO_FEED_EN    (BIT(31))
-#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
-#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
-#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
-/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: disable SWD.*/
-#define RTC_CNTL_SWD_DISABLE    (BIT(30))
-#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
-#define RTC_CNTL_SWD_DISABLE_V  0x1
-#define RTC_CNTL_SWD_DISABLE_S  30
-/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Sw feed swd.*/
-#define RTC_CNTL_SWD_FEED    (BIT(29))
-#define RTC_CNTL_SWD_FEED_M  (BIT(29))
-#define RTC_CNTL_SWD_FEED_V  0x1
-#define RTC_CNTL_SWD_FEED_S  29
-/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
-/*description: reset swd reset flag.*/
-#define RTC_CNTL_SWD_RST_FLAG_CLR    (BIT(28))
-#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
-#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
-#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
-/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
-/*description: adjust signal width send to swd.*/
-#define RTC_CNTL_SWD_SIGNAL_WIDTH    0x000003FF
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
-#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
-/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_SWD_BYPASS_RST    (BIT(17))
-#define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
-#define RTC_CNTL_SWD_BYPASS_RST_V  0x1
-#define RTC_CNTL_SWD_BYPASS_RST_S  17
-/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: swd interrupt for feeding.*/
-#define RTC_CNTL_SWD_FEED_INT    (BIT(1))
-#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
-#define RTC_CNTL_SWD_FEED_INT_V  0x1
-#define RTC_CNTL_SWD_FEED_INT_S  1
-/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: swd reset flag.*/
-#define RTC_CNTL_SWD_RESET_FLAG    (BIT(0))
-#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
-#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
-#define RTC_CNTL_SWD_RESET_FLAG_S  0
-
-#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xB8)
-/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
-/*description: .*/
-#define RTC_CNTL_SWD_WKEY    0xFFFFFFFF
-#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
-#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
-#define RTC_CNTL_SWD_WKEY_S  0
-
-#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0xBC)
-/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
-/*description: .*/
-#define RTC_CNTL_SW_STALL_PROCPU_C1    0x0000003F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
-#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
-#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
-/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
-/*description: {reg_sw_stall_appcpu_c1[5:0].*/
-#define RTC_CNTL_SW_STALL_APPCPU_C1    0x0000003F
-#define RTC_CNTL_SW_STALL_APPCPU_C1_M  ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
-#define RTC_CNTL_SW_STALL_APPCPU_C1_V  0x3F
-#define RTC_CNTL_SW_STALL_APPCPU_C1_S  20
-
-#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0xC0)
-/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_SCRATCH4    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
-#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH4_S  0
-
-#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0xC4)
-/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_SCRATCH5    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
-#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH5_S  0
-
-#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0xC8)
-/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_SCRATCH6    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
-#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH6_S  0
-
-#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0xCC)
-/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_SCRATCH7    0xFFFFFFFF
-#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
-#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
-#define RTC_CNTL_SCRATCH7_S  0
-
-#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0xD0)
-/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */
-/*description: rtc main state machine status.*/
-#define RTC_CNTL_MAIN_STATE    0x0000000F
-#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
-#define RTC_CNTL_MAIN_STATE_V  0xF
-#define RTC_CNTL_MAIN_STATE_S  28
-/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */
-/*description: rtc main state machine is in idle state.*/
-#define RTC_CNTL_MAIN_STATE_IN_IDLE    (BIT(27))
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
-/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: rtc main state machine is in sleep state.*/
-#define RTC_CNTL_MAIN_STATE_IN_SLP    (BIT(26))
-#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
-#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait xtal state.*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL    (BIT(25))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait pll state.*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL    (BIT(24))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
-/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */
-/*description: rtc main state machine is in wait 8m state.*/
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M    (BIT(23))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
-#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
-/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */
-/*description: rtc main state machine is in the states of low power.*/
-#define RTC_CNTL_IN_LOW_POWER_STATE    (BIT(22))
-#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
-#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
-#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
-/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */
-/*description: rtc main state machine is in the states of wakeup process.*/
-#define RTC_CNTL_IN_WAKEUP_STATE    (BIT(21))
-#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
-#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
-#define RTC_CNTL_IN_WAKEUP_STATE_S  21
-/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: rtc main state machine has been waited for some cycles.*/
-#define RTC_CNTL_MAIN_STATE_WAIT_END    (BIT(20))
-#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
-#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
-#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
-/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: rtc is ready to receive wake up trigger from wake up source.*/
-#define RTC_CNTL_RDY_FOR_WAKEUP    (BIT(19))
-#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
-#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
-#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
-/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: rtc main state machine is in states that pll should be running.*/
-#define RTC_CNTL_MAIN_STATE_PLL_ON    (BIT(18))
-#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
-#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
-#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
-/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: no use any more.*/
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO    (BIT(17))
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
-#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
-/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: ulp/cocpu is done.*/
-#define RTC_CNTL_COCPU_STATE_DONE    (BIT(16))
-#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
-#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
-#define RTC_CNTL_COCPU_STATE_DONE_S  16
-/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: ulp/cocpu is in sleep state.*/
-#define RTC_CNTL_COCPU_STATE_SLP    (BIT(15))
-#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
-#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
-#define RTC_CNTL_COCPU_STATE_SLP_S  15
-/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: ulp/cocpu is about to working. Switch rtc main state.*/
-#define RTC_CNTL_COCPU_STATE_SWITCH    (BIT(14))
-#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
-#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
-#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
-/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: ulp/cocpu should start to work.*/
-#define RTC_CNTL_COCPU_STATE_START    (BIT(13))
-#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
-#define RTC_CNTL_COCPU_STATE_START_V  0x1
-#define RTC_CNTL_COCPU_STATE_START_S  13
-/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: touch is done.*/
-#define RTC_CNTL_TOUCH_STATE_DONE    (BIT(12))
-#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
-#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
-#define RTC_CNTL_TOUCH_STATE_DONE_S  12
-/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: touch is in sleep state.*/
-#define RTC_CNTL_TOUCH_STATE_SLP    (BIT(11))
-#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
-#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
-#define RTC_CNTL_TOUCH_STATE_SLP_S  11
-/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: touch is about to working. Switch rtc main state.*/
-#define RTC_CNTL_TOUCH_STATE_SWITCH    (BIT(10))
-#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
-#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
-#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
-/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: touch should start to work.*/
-#define RTC_CNTL_TOUCH_STATE_START    (BIT(9))
-#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
-#define RTC_CNTL_TOUCH_STATE_START_V  0x1
-#define RTC_CNTL_TOUCH_STATE_START_S  9
-/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: digital wrap power down.*/
-#define RTC_CNTL_XPD_DIG    (BIT(8))
-#define RTC_CNTL_XPD_DIG_M  (BIT(8))
-#define RTC_CNTL_XPD_DIG_V  0x1
-#define RTC_CNTL_XPD_DIG_S  8
-/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: digital wrap iso.*/
-#define RTC_CNTL_DIG_ISO    (BIT(7))
-#define RTC_CNTL_DIG_ISO_M  (BIT(7))
-#define RTC_CNTL_DIG_ISO_V  0x1
-#define RTC_CNTL_DIG_ISO_S  7
-/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: wifi wrap power down.*/
-#define RTC_CNTL_XPD_WIFI    (BIT(6))
-#define RTC_CNTL_XPD_WIFI_M  (BIT(6))
-#define RTC_CNTL_XPD_WIFI_V  0x1
-#define RTC_CNTL_XPD_WIFI_S  6
-/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: wifi iso.*/
-#define RTC_CNTL_WIFI_ISO    (BIT(5))
-#define RTC_CNTL_WIFI_ISO_M  (BIT(5))
-#define RTC_CNTL_WIFI_ISO_V  0x1
-#define RTC_CNTL_WIFI_ISO_S  5
-/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: rtc peripheral power down .*/
-#define RTC_CNTL_XPD_RTC_PERI    (BIT(4))
-#define RTC_CNTL_XPD_RTC_PERI_M  (BIT(4))
-#define RTC_CNTL_XPD_RTC_PERI_V  0x1
-#define RTC_CNTL_XPD_RTC_PERI_S  4
-/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: rtc peripheral iso.*/
-#define RTC_CNTL_PERI_ISO    (BIT(3))
-#define RTC_CNTL_PERI_ISO_M  (BIT(3))
-#define RTC_CNTL_PERI_ISO_V  0x1
-#define RTC_CNTL_PERI_ISO_S  3
-/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: External DCDC power down.*/
-#define RTC_CNTL_XPD_DIG_DCDC    (BIT(2))
-#define RTC_CNTL_XPD_DIG_DCDC_M  (BIT(2))
-#define RTC_CNTL_XPD_DIG_DCDC_V  0x1
-#define RTC_CNTL_XPD_DIG_DCDC_S  2
-/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: rom0 power down.*/
-#define RTC_CNTL_XPD_ROM0    (BIT(0))
-#define RTC_CNTL_XPD_ROM0_M  (BIT(0))
-#define RTC_CNTL_XPD_ROM0_V  0x1
-#define RTC_CNTL_XPD_ROM0_S  0
-
-#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0xD4)
-/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
-/*description: .*/
-#define RTC_CNTL_LOW_POWER_DIAG1    0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
-#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
-#define RTC_CNTL_LOW_POWER_DIAG1_S  0
-
-#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xD8)
-/* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_PAD21_HOLD    (BIT(21))
-#define RTC_CNTL_PAD21_HOLD_M  (BIT(21))
-#define RTC_CNTL_PAD21_HOLD_V  0x1
-#define RTC_CNTL_PAD21_HOLD_S  21
-/* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_PAD20_HOLD    (BIT(20))
-#define RTC_CNTL_PAD20_HOLD_M  (BIT(20))
-#define RTC_CNTL_PAD20_HOLD_V  0x1
-#define RTC_CNTL_PAD20_HOLD_S  20
-/* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_PAD19_HOLD    (BIT(19))
-#define RTC_CNTL_PAD19_HOLD_M  (BIT(19))
-#define RTC_CNTL_PAD19_HOLD_V  0x1
-#define RTC_CNTL_PAD19_HOLD_S  19
-/* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_PDAC2_HOLD    (BIT(18))
-#define RTC_CNTL_PDAC2_HOLD_M  (BIT(18))
-#define RTC_CNTL_PDAC2_HOLD_V  0x1
-#define RTC_CNTL_PDAC2_HOLD_S  18
-/* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_PDAC1_HOLD    (BIT(17))
-#define RTC_CNTL_PDAC1_HOLD_M  (BIT(17))
-#define RTC_CNTL_PDAC1_HOLD_V  0x1
-#define RTC_CNTL_PDAC1_HOLD_S  17
-/* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_X32N_HOLD    (BIT(16))
-#define RTC_CNTL_X32N_HOLD_M  (BIT(16))
-#define RTC_CNTL_X32N_HOLD_V  0x1
-#define RTC_CNTL_X32N_HOLD_S  16
-/* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_X32P_HOLD    (BIT(15))
-#define RTC_CNTL_X32P_HOLD_M  (BIT(15))
-#define RTC_CNTL_X32P_HOLD_V  0x1
-#define RTC_CNTL_X32P_HOLD_S  15
-/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD14_HOLD    (BIT(14))
-#define RTC_CNTL_TOUCH_PAD14_HOLD_M  (BIT(14))
-#define RTC_CNTL_TOUCH_PAD14_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD14_HOLD_S  14
-/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD13_HOLD    (BIT(13))
-#define RTC_CNTL_TOUCH_PAD13_HOLD_M  (BIT(13))
-#define RTC_CNTL_TOUCH_PAD13_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD13_HOLD_S  13
-/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD12_HOLD    (BIT(12))
-#define RTC_CNTL_TOUCH_PAD12_HOLD_M  (BIT(12))
-#define RTC_CNTL_TOUCH_PAD12_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD12_HOLD_S  12
-/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD11_HOLD    (BIT(11))
-#define RTC_CNTL_TOUCH_PAD11_HOLD_M  (BIT(11))
-#define RTC_CNTL_TOUCH_PAD11_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD11_HOLD_S  11
-/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD10_HOLD    (BIT(10))
-#define RTC_CNTL_TOUCH_PAD10_HOLD_M  (BIT(10))
-#define RTC_CNTL_TOUCH_PAD10_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD10_HOLD_S  10
-/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD9_HOLD    (BIT(9))
-#define RTC_CNTL_TOUCH_PAD9_HOLD_M  (BIT(9))
-#define RTC_CNTL_TOUCH_PAD9_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD9_HOLD_S  9
-/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD8_HOLD    (BIT(8))
-#define RTC_CNTL_TOUCH_PAD8_HOLD_M  (BIT(8))
-#define RTC_CNTL_TOUCH_PAD8_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD8_HOLD_S  8
-/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD7_HOLD    (BIT(7))
-#define RTC_CNTL_TOUCH_PAD7_HOLD_M  (BIT(7))
-#define RTC_CNTL_TOUCH_PAD7_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD7_HOLD_S  7
-/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD6_HOLD    (BIT(6))
-#define RTC_CNTL_TOUCH_PAD6_HOLD_M  (BIT(6))
-#define RTC_CNTL_TOUCH_PAD6_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD6_HOLD_S  6
-/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD5_HOLD    (BIT(5))
-#define RTC_CNTL_TOUCH_PAD5_HOLD_M  (BIT(5))
-#define RTC_CNTL_TOUCH_PAD5_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD5_HOLD_S  5
-/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD4_HOLD    (BIT(4))
-#define RTC_CNTL_TOUCH_PAD4_HOLD_M  (BIT(4))
-#define RTC_CNTL_TOUCH_PAD4_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD4_HOLD_S  4
-/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD3_HOLD    (BIT(3))
-#define RTC_CNTL_TOUCH_PAD3_HOLD_M  (BIT(3))
-#define RTC_CNTL_TOUCH_PAD3_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD3_HOLD_S  3
-/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD2_HOLD    (BIT(2))
-#define RTC_CNTL_TOUCH_PAD2_HOLD_M  (BIT(2))
-#define RTC_CNTL_TOUCH_PAD2_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD2_HOLD_S  2
-/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD1_HOLD    (BIT(1))
-#define RTC_CNTL_TOUCH_PAD1_HOLD_M  (BIT(1))
-#define RTC_CNTL_TOUCH_PAD1_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD1_HOLD_S  1
-/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD0_HOLD    (BIT(0))
-#define RTC_CNTL_TOUCH_PAD0_HOLD_M  (BIT(0))
-#define RTC_CNTL_TOUCH_PAD0_HOLD_V  0x1
-#define RTC_CNTL_TOUCH_PAD0_HOLD_S  0
-
-#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xDC)
-/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define RTC_CNTL_DIG_PAD_HOLD    0xFFFFFFFF
-#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
-#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
-#define RTC_CNTL_DIG_PAD_HOLD_S  0
-
-#define RTC_CNTL_EXT_WAKEUP1_REG          (DR_REG_RTCCNTL_BASE + 0xE0)
-/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
-/*description: clear ext wakeup1 status.*/
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR    (BIT(22))
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M  (BIT(22))
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V  0x1
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S  22
-/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */
-/*description: Bitmap to select RTC pads for ext wakeup1.*/
-#define RTC_CNTL_EXT_WAKEUP1_SEL    0x003FFFFF
-#define RTC_CNTL_EXT_WAKEUP1_SEL_M  ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S))
-#define RTC_CNTL_EXT_WAKEUP1_SEL_V  0x3FFFFF
-#define RTC_CNTL_EXT_WAKEUP1_SEL_S  0
-
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG          (DR_REG_RTCCNTL_BASE + 0xE4)
-/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */
-/*description: ext wakeup1 status.*/
-#define RTC_CNTL_EXT_WAKEUP1_STATUS    0x003FFFFF
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_M  ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S))
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_V  0x3FFFFF
-#define RTC_CNTL_EXT_WAKEUP1_STATUS_S  0
-
-#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0xE8)
-/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_BROWN_OUT_DET    (BIT(31))
-#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
-#define RTC_CNTL_BROWN_OUT_DET_V  0x1
-#define RTC_CNTL_BROWN_OUT_DET_S  31
-/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: enable brown out.*/
-#define RTC_CNTL_BROWN_OUT_ENA    (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
-#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_ENA_S  30
-/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
-/*description: clear brown out counter.*/
-#define RTC_CNTL_BROWN_OUT_CNT_CLR    (BIT(29))
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
-#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
-/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN    (BIT(28))
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
-#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
-/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: 1:  4-pos reset.*/
-#define RTC_CNTL_BROWN_OUT_RST_SEL    (BIT(27))
-#define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
-#define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
-#define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
-/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: enable brown out reset.*/
-#define RTC_CNTL_BROWN_OUT_RST_ENA    (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
-#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
-/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
-/*description: brown out reset wait cycles.*/
-#define RTC_CNTL_BROWN_OUT_RST_WAIT    0x000003FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
-#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
-/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable power down RF when brown out happens.*/
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA    (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
-/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: enable close flash when brown out happens.*/
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA    (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
-#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
-/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */
-/*description: brown out interrupt wait cycles.*/
-#define RTC_CNTL_BROWN_OUT_INT_WAIT    0x000003FF
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
-#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
-
-#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0xEC)
-/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: RTC timer low 32 bits.*/
-#define RTC_CNTL_TIMER_VALUE1_LOW    0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
-#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
-#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
-
-#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0xF0)
-/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: RTC timer high 16 bits.*/
-#define RTC_CNTL_TIMER_VALUE1_HIGH    0x0000FFFF
-#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
-#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
-#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
-
-#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG          (DR_REG_RTCCNTL_BASE + 0xF4)
-/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: xtal 32k watch dog backup clock factor.*/
-#define RTC_CNTL_XTAL32K_CLK_FACTOR    0xFFFFFFFF
-#define RTC_CNTL_XTAL32K_CLK_FACTOR_M  ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S))
-#define RTC_CNTL_XTAL32K_CLK_FACTOR_V  0xFFFFFFFF
-#define RTC_CNTL_XTAL32K_CLK_FACTOR_S  0
-
-#define RTC_CNTL_XTAL32K_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xF8)
-/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: if restarted xtal32k period is smaller than this.*/
-#define RTC_CNTL_XTAL32K_STABLE_THRES    0x0000000F
-#define RTC_CNTL_XTAL32K_STABLE_THRES_M  ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S))
-#define RTC_CNTL_XTAL32K_STABLE_THRES_V  0xF
-#define RTC_CNTL_XTAL32K_STABLE_THRES_S  28
-/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
-/*description: If no clock detected for this amount of time.*/
-#define RTC_CNTL_XTAL32K_WDT_TIMEOUT    0x000000FF
-#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M  ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S))
-#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V  0xFF
-#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S  20
-/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
-/*description: cycles to wait to repower on xtal 32k.*/
-#define RTC_CNTL_XTAL32K_RESTART_WAIT    0x0000FFFF
-#define RTC_CNTL_XTAL32K_RESTART_WAIT_M  ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S))
-#define RTC_CNTL_XTAL32K_RESTART_WAIT_V  0xFFFF
-#define RTC_CNTL_XTAL32K_RESTART_WAIT_S  4
-/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
-/*description: cycles to wait to return normal xtal 32k.*/
-#define RTC_CNTL_XTAL32K_RETURN_WAIT    0x0000000F
-#define RTC_CNTL_XTAL32K_RETURN_WAIT_M  ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S))
-#define RTC_CNTL_XTAL32K_RETURN_WAIT_V  0xF
-#define RTC_CNTL_XTAL32K_RETURN_WAIT_S  0
-
-#define RTC_CNTL_ULP_CP_TIMER_REG          (DR_REG_RTCCNTL_BASE + 0xFC)
-/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: ULP-coprocessor timer enable bit.*/
-#define RTC_CNTL_ULP_CP_SLP_TIMER_EN    (BIT(31))
-#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M  (BIT(31))
-#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V  0x1
-#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S  31
-/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */
-/*description: ULP-coprocessor wakeup by GPIO state clear.*/
-#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR    (BIT(30))
-#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M  (BIT(30))
-#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V  0x1
-#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S  30
-/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: ULP-coprocessor wakeup by GPIO enable.*/
-#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA    (BIT(29))
-#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M  (BIT(29))
-#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V  0x1
-#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S  29
-/* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */
-/*description: ULP-coprocessor PC initial address.*/
-#define RTC_CNTL_ULP_CP_PC_INIT    0x000007FF
-#define RTC_CNTL_ULP_CP_PC_INIT_M  ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S))
-#define RTC_CNTL_ULP_CP_PC_INIT_V  0x7FF
-#define RTC_CNTL_ULP_CP_PC_INIT_S  0
-
-#define RTC_CNTL_ULP_CP_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x100)
-/* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: Write 1 to start ULP-coprocessor.*/
-#define RTC_CNTL_ULP_CP_START_TOP    (BIT(31))
-#define RTC_CNTL_ULP_CP_START_TOP_M  (BIT(31))
-#define RTC_CNTL_ULP_CP_START_TOP_V  0x1
-#define RTC_CNTL_ULP_CP_START_TOP_S  31
-/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: 1: ULP-coprocessor is started by SW.*/
-#define RTC_CNTL_ULP_CP_FORCE_START_TOP    (BIT(30))
-#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M  (BIT(30))
-#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V  0x1
-#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S  30
-/* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: ulp coprocessor clk software reset.*/
-#define RTC_CNTL_ULP_CP_RESET    (BIT(29))
-#define RTC_CNTL_ULP_CP_RESET_M  (BIT(29))
-#define RTC_CNTL_ULP_CP_RESET_V  0x1
-#define RTC_CNTL_ULP_CP_RESET_S  29
-/* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: ulp coprocessor clk force on.*/
-#define RTC_CNTL_ULP_CP_CLK_FO    (BIT(28))
-#define RTC_CNTL_ULP_CP_CLK_FO_M  (BIT(28))
-#define RTC_CNTL_ULP_CP_CLK_FO_V  0x1
-#define RTC_CNTL_ULP_CP_CLK_FO_S  28
-/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR    (BIT(22))
-#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M  (BIT(22))
-#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V  0x1
-#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S  22
-/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */
-/*description: .*/
-#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE    0x000007FF
-#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M  ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S))
-#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V  0x7FF
-#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S  11
-/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */
-/*description: .*/
-#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT    0x000007FF
-#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M  ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S))
-#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V  0x7FF
-#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S  0
-
-#define RTC_CNTL_COCPU_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x104)
-/* RTC_CNTL_COCPU_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_COCPU_CLKGATE_EN    (BIT(27))
-#define RTC_CNTL_COCPU_CLKGATE_EN_M  (BIT(27))
-#define RTC_CNTL_COCPU_CLKGATE_EN_V  0x1
-#define RTC_CNTL_COCPU_CLKGATE_EN_S  27
-/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */
-/*description: trigger cocpu register interrupt.*/
-#define RTC_CNTL_COCPU_SW_INT_TRIGGER    (BIT(26))
-#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M  (BIT(26))
-#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V  0x1
-#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S  26
-/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: done signal used by riscv to control timer. .*/
-#define RTC_CNTL_COCPU_DONE    (BIT(25))
-#define RTC_CNTL_COCPU_DONE_M  (BIT(25))
-#define RTC_CNTL_COCPU_DONE_V  0x1
-#define RTC_CNTL_COCPU_DONE_S  25
-/* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: 1: select riscv done 0: select ulp done.*/
-#define RTC_CNTL_COCPU_DONE_FORCE    (BIT(24))
-#define RTC_CNTL_COCPU_DONE_FORCE_M  (BIT(24))
-#define RTC_CNTL_COCPU_DONE_FORCE_V  0x1
-#define RTC_CNTL_COCPU_DONE_FORCE_S  24
-/* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: 1: old ULP 0: new riscV.*/
-#define RTC_CNTL_COCPU_SEL    (BIT(23))
-#define RTC_CNTL_COCPU_SEL_M  (BIT(23))
-#define RTC_CNTL_COCPU_SEL_V  0x1
-#define RTC_CNTL_COCPU_SEL_S  23
-/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: to reset cocpu.*/
-#define RTC_CNTL_COCPU_SHUT_RESET_EN    (BIT(22))
-#define RTC_CNTL_COCPU_SHUT_RESET_EN_M  (BIT(22))
-#define RTC_CNTL_COCPU_SHUT_RESET_EN_V  0x1
-#define RTC_CNTL_COCPU_SHUT_RESET_EN_S  22
-/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */
-/*description: time from shut cocpu to disable clk.*/
-#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS    0x000000FF
-#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M  ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S))
-#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V  0xFF
-#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S  14
-/* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: to shut cocpu.*/
-#define RTC_CNTL_COCPU_SHUT    (BIT(13))
-#define RTC_CNTL_COCPU_SHUT_M  (BIT(13))
-#define RTC_CNTL_COCPU_SHUT_V  0x1
-#define RTC_CNTL_COCPU_SHUT_S  13
-/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */
-/*description: time from start cocpu to give start interrupt.*/
-#define RTC_CNTL_COCPU_START_2_INTR_EN    0x0000003F
-#define RTC_CNTL_COCPU_START_2_INTR_EN_M  ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S))
-#define RTC_CNTL_COCPU_START_2_INTR_EN_V  0x3F
-#define RTC_CNTL_COCPU_START_2_INTR_EN_S  7
-/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */
-/*description: time from start cocpu to pull down reset.*/
-#define RTC_CNTL_COCPU_START_2_RESET_DIS    0x0000003F
-#define RTC_CNTL_COCPU_START_2_RESET_DIS_M  ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S))
-#define RTC_CNTL_COCPU_START_2_RESET_DIS_V  0x3F
-#define RTC_CNTL_COCPU_START_2_RESET_DIS_S  1
-/* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: cocpu clk force on.*/
-#define RTC_CNTL_COCPU_CLK_FO    (BIT(0))
-#define RTC_CNTL_COCPU_CLK_FO_M  (BIT(0))
-#define RTC_CNTL_COCPU_CLK_FO_V  0x1
-#define RTC_CNTL_COCPU_CLK_FO_S  0
-
-#define RTC_CNTL_TOUCH_CTRL1_REG          (DR_REG_RTCCNTL_BASE + 0x108)
-/* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */
-/*description: the meas length (in 8MHz).*/
-#define RTC_CNTL_TOUCH_MEAS_NUM    0x0000FFFF
-#define RTC_CNTL_TOUCH_MEAS_NUM_M  ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S))
-#define RTC_CNTL_TOUCH_MEAS_NUM_V  0xFFFF
-#define RTC_CNTL_TOUCH_MEAS_NUM_S  16
-/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */
-/*description: sleep cycles for timer.*/
-#define RTC_CNTL_TOUCH_SLEEP_CYCLES    0x0000FFFF
-#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M  ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S))
-#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V  0xFFFF
-#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S  0
-
-#define RTC_CNTL_TOUCH_CTRL2_REG          (DR_REG_RTCCNTL_BASE + 0x10C)
-/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: touch clock enable.*/
-#define RTC_CNTL_TOUCH_CLKGATE_EN    (BIT(31))
-#define RTC_CNTL_TOUCH_CLKGATE_EN_M  (BIT(31))
-#define RTC_CNTL_TOUCH_CLKGATE_EN_V  0x1
-#define RTC_CNTL_TOUCH_CLKGATE_EN_S  31
-/* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: touch clock force on.*/
-#define RTC_CNTL_TOUCH_CLK_FO    (BIT(30))
-#define RTC_CNTL_TOUCH_CLK_FO_M  (BIT(30))
-#define RTC_CNTL_TOUCH_CLK_FO_V  0x1
-#define RTC_CNTL_TOUCH_CLK_FO_S  30
-/* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: reset upgrade touch.*/
-#define RTC_CNTL_TOUCH_RESET    (BIT(29))
-#define RTC_CNTL_TOUCH_RESET_M  (BIT(29))
-#define RTC_CNTL_TOUCH_RESET_V  0x1
-#define RTC_CNTL_TOUCH_RESET_S  29
-/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
-/*description: force touch timer done.*/
-#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE    0x00000003
-#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M  ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S))
-#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V  0x3
-#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S  27
-/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */
-/*description: when a touch pad is active.*/
-#define RTC_CNTL_TOUCH_SLP_CYC_DIV    0x00000003
-#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M  ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S))
-#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V  0x3
-#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S  25
-/* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */
-/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD.*/
-#define RTC_CNTL_TOUCH_XPD_WAIT    0x000000FF
-#define RTC_CNTL_TOUCH_XPD_WAIT_M  ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S))
-#define RTC_CNTL_TOUCH_XPD_WAIT_V  0xFF
-#define RTC_CNTL_TOUCH_XPD_WAIT_S  17
-/* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: 1: to start touch fsm by SW.*/
-#define RTC_CNTL_TOUCH_START_FORCE    (BIT(16))
-#define RTC_CNTL_TOUCH_START_FORCE_M  (BIT(16))
-#define RTC_CNTL_TOUCH_START_FORCE_V  0x1
-#define RTC_CNTL_TOUCH_START_FORCE_S  16
-/* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 1: start touch fsm.*/
-#define RTC_CNTL_TOUCH_START_EN    (BIT(15))
-#define RTC_CNTL_TOUCH_START_EN_M  (BIT(15))
-#define RTC_CNTL_TOUCH_START_EN_V  0x1
-#define RTC_CNTL_TOUCH_START_EN_S  15
-/* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm.*/
-#define RTC_CNTL_TOUCH_START_FSM_EN    (BIT(14))
-#define RTC_CNTL_TOUCH_START_FSM_EN_M  (BIT(14))
-#define RTC_CNTL_TOUCH_START_FSM_EN_V  0x1
-#define RTC_CNTL_TOUCH_START_FSM_EN_S  14
-/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: touch timer enable bit.*/
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN    (BIT(13))
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M  (BIT(13))
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V  0x1
-#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S  13
-/* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: 1:use self bias 0:use bandgap bias.*/
-#define RTC_CNTL_TOUCH_DBIAS    (BIT(12))
-#define RTC_CNTL_TOUCH_DBIAS_M  (BIT(12))
-#define RTC_CNTL_TOUCH_DBIAS_V  0x1
-#define RTC_CNTL_TOUCH_DBIAS_S  12
-/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: TOUCH pad0 reference cap.*/
-#define RTC_CNTL_TOUCH_REFC    0x00000007
-#define RTC_CNTL_TOUCH_REFC_M  ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S))
-#define RTC_CNTL_TOUCH_REFC_V  0x7
-#define RTC_CNTL_TOUCH_REFC_S  9
-/* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: TOUCH_XPD_BIAS.*/
-#define RTC_CNTL_TOUCH_XPD_BIAS    (BIT(8))
-#define RTC_CNTL_TOUCH_XPD_BIAS_M  (BIT(8))
-#define RTC_CNTL_TOUCH_XPD_BIAS_V  0x1
-#define RTC_CNTL_TOUCH_XPD_BIAS_S  8
-/* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: TOUCH_DREFH.*/
-#define RTC_CNTL_TOUCH_DREFH    0x00000003
-#define RTC_CNTL_TOUCH_DREFH_M  ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S))
-#define RTC_CNTL_TOUCH_DREFH_V  0x3
-#define RTC_CNTL_TOUCH_DREFH_S  6
-/* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */
-/*description: TOUCH_DREFL.*/
-#define RTC_CNTL_TOUCH_DREFL    0x00000003
-#define RTC_CNTL_TOUCH_DREFL_M  ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S))
-#define RTC_CNTL_TOUCH_DREFL_V  0x3
-#define RTC_CNTL_TOUCH_DREFL_S  4
-/* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: TOUCH_DRANGE.*/
-#define RTC_CNTL_TOUCH_DRANGE    0x00000003
-#define RTC_CNTL_TOUCH_DRANGE_M  ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S))
-#define RTC_CNTL_TOUCH_DRANGE_V  0x3
-#define RTC_CNTL_TOUCH_DRANGE_S  2
-
-#define RTC_CNTL_TOUCH_SCAN_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x110)
-/* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */
-/*description: select out ring pad.*/
-#define RTC_CNTL_TOUCH_OUT_RING    0x0000000F
-#define RTC_CNTL_TOUCH_OUT_RING_M  ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S))
-#define RTC_CNTL_TOUCH_OUT_RING_V  0xF
-#define RTC_CNTL_TOUCH_OUT_RING_S  28
-/* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
-/*description: touch7 buffer driver strength.*/
-#define RTC_CNTL_TOUCH_BUFDRV    0x00000007
-#define RTC_CNTL_TOUCH_BUFDRV_M  ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S))
-#define RTC_CNTL_TOUCH_BUFDRV_V  0x7
-#define RTC_CNTL_TOUCH_BUFDRV_S  25
-/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */
-/*description: touch scan mode pad enable map.*/
-#define RTC_CNTL_TOUCH_SCAN_PAD_MAP    0x00007FFF
-#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M  ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S))
-#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V  0x7FFF
-#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S  10
-/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: touch pad14 will be used as shield.*/
-#define RTC_CNTL_TOUCH_SHIELD_PAD_EN    (BIT(9))
-#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M  (BIT(9))
-#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V  0x1
-#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S  9
-/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: inactive touch pads connect to 1: gnd 0: HighZ.*/
-#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION    (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M  (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V  0x1
-#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S  8
-/* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: touch pad0 will be used to de-noise.*/
-#define RTC_CNTL_TOUCH_DENOISE_EN    (BIT(2))
-#define RTC_CNTL_TOUCH_DENOISE_EN_M  (BIT(2))
-#define RTC_CNTL_TOUCH_DENOISE_EN_V  0x1
-#define RTC_CNTL_TOUCH_DENOISE_EN_S  2
-/* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */
-/*description: De-noise resolution: 12/10/8/4 bit.*/
-#define RTC_CNTL_TOUCH_DENOISE_RES    0x00000003
-#define RTC_CNTL_TOUCH_DENOISE_RES_M  ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S))
-#define RTC_CNTL_TOUCH_DENOISE_RES_V  0x3
-#define RTC_CNTL_TOUCH_DENOISE_RES_S  0
-
-#define RTC_CNTL_TOUCH_SLP_THRES_REG          (DR_REG_RTCCNTL_BASE + 0x114)
-/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hf ; */
-/*description:  .*/
-#define RTC_CNTL_TOUCH_SLP_PAD    0x0000001F
-#define RTC_CNTL_TOUCH_SLP_PAD_M  ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S))
-#define RTC_CNTL_TOUCH_SLP_PAD_V  0x1F
-#define RTC_CNTL_TOUCH_SLP_PAD_S  27
-/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: sleep pad approach function enable.*/
-#define RTC_CNTL_TOUCH_SLP_APPROACH_EN    (BIT(26))
-#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M  (BIT(26))
-#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V  0x1
-#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S  26
-/* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
-/*description: the threshold for sleep touch pad.*/
-#define RTC_CNTL_TOUCH_SLP_TH    0x003FFFFF
-#define RTC_CNTL_TOUCH_SLP_TH_M  ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S))
-#define RTC_CNTL_TOUCH_SLP_TH_V  0x3FFFFF
-#define RTC_CNTL_TOUCH_SLP_TH_S  0
-
-#define RTC_CNTL_TOUCH_APPROACH_REG          (DR_REG_RTCCNTL_BASE + 0x118)
-/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */
-/*description: approach pads total meas times.*/
-#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME    0x000000FF
-#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M  ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S))
-#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V  0xFF
-#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S  24
-/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */
-/*description: clear touch slp channel.*/
-#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR    (BIT(23))
-#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M  (BIT(23))
-#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V  0x1
-#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S  23
-
-#define RTC_CNTL_TOUCH_FILTER_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x11C)
-/* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: touch filter enable.*/
-#define RTC_CNTL_TOUCH_FILTER_EN    (BIT(31))
-#define RTC_CNTL_TOUCH_FILTER_EN_M  (BIT(31))
-#define RTC_CNTL_TOUCH_FILTER_EN_V  0x1
-#define RTC_CNTL_TOUCH_FILTER_EN_S  31
-/* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */
-/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter.*/
-#define RTC_CNTL_TOUCH_FILTER_MODE    0x00000007
-#define RTC_CNTL_TOUCH_FILTER_MODE_M  ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S))
-#define RTC_CNTL_TOUCH_FILTER_MODE_V  0x7
-#define RTC_CNTL_TOUCH_FILTER_MODE_S  28
-/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */
-/*description: debounce counter.*/
-#define RTC_CNTL_TOUCH_DEBOUNCE    0x00000007
-#define RTC_CNTL_TOUCH_DEBOUNCE_M  ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S))
-#define RTC_CNTL_TOUCH_DEBOUNCE_V  0x7
-#define RTC_CNTL_TOUCH_DEBOUNCE_S  25
-/* RTC_CNTL_TOUCH_CONFIG3 : R/W ;bitpos:[24:23] ;default: 2'd1 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_CONFIG3 0x00000003
-#define RTC_CNTL_TOUCH_CONFIG3_M ((RTC_CNTL_TOUCH_CONFIG3_V) << (RTC_CNTL_TOUCH_CONFIG3_S))
-#define RTC_CNTL_TOUCH_CONFIG3_V 0x3
-#define RTC_CNTL_TOUCH_CONFIG3_S 23
-/* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_NOISE_THRES    0x00000003
-#define RTC_CNTL_TOUCH_NOISE_THRES_M  ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S))
-#define RTC_CNTL_TOUCH_NOISE_THRES_V  0x3
-#define RTC_CNTL_TOUCH_NOISE_THRES_S  21
-/* RTC_CNTL_TOUCH_CONFIG2 : R/W ;bitpos:[20:19] ;default: 2'd1 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_CONFIG2 0x00000003
-#define RTC_CNTL_TOUCH_CONFIG2_M ((RTC_CNTL_TOUCH_CONFIG2_V) << (RTC_CNTL_TOUCH_CONFIG2_S))
-#define RTC_CNTL_TOUCH_CONFIG2_V 0x3
-#define RTC_CNTL_TOUCH_CONFIG2_S 19
-/* RTC_CNTL_TOUCH_CONFIG1 : R/W ;bitpos:[18:15] ;default: 4'd5 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_CONFIG1 0x0000000F
-#define RTC_CNTL_TOUCH_CONFIG1_M ((RTC_CNTL_TOUCH_CONFIG1_V) << (RTC_CNTL_TOUCH_CONFIG1_S))
-#define RTC_CNTL_TOUCH_CONFIG1_V 0xF
-#define RTC_CNTL_TOUCH_CONFIG1_S 15
-/* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */
-/*description: touch jitter step.*/
-#define RTC_CNTL_TOUCH_JITTER_STEP    0x0000000F
-#define RTC_CNTL_TOUCH_JITTER_STEP_M  ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S))
-#define RTC_CNTL_TOUCH_JITTER_STEP_V  0xF
-#define RTC_CNTL_TOUCH_JITTER_STEP_S  11
-/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_SMOOTH_LVL    0x00000003
-#define RTC_CNTL_TOUCH_SMOOTH_LVL_M  ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S))
-#define RTC_CNTL_TOUCH_SMOOTH_LVL_V  0x3
-#define RTC_CNTL_TOUCH_SMOOTH_LVL_S  9
-/* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES    (BIT(8))
-#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M  (BIT(8))
-#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V  0x1
-#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S  8
-/* RTC_CNTL_TOUCH_BYPASS_NEG_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: */
-#define RTC_CNTL_TOUCH_BYPASS_NEG_THRES (BIT(7))
-#define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_M (BIT(7))
-#define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_V 0x1
-#define RTC_CNTL_TOUCH_BYPASS_NEG_THRES_S 7
-
-#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x120)
-/* RTC_CNTL_SW_HW_USB_PHY_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_SW_HW_USB_PHY_SEL    (BIT(20))
-#define RTC_CNTL_SW_HW_USB_PHY_SEL_M  (BIT(20))
-#define RTC_CNTL_SW_HW_USB_PHY_SEL_V  0x1
-#define RTC_CNTL_SW_HW_USB_PHY_SEL_S  20
-/* RTC_CNTL_SW_USB_PHY_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_SW_USB_PHY_SEL    (BIT(19))
-#define RTC_CNTL_SW_USB_PHY_SEL_M  (BIT(19))
-#define RTC_CNTL_SW_USB_PHY_SEL_V  0x1
-#define RTC_CNTL_SW_USB_PHY_SEL_S  19
-/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_IO_MUX_RESET_DISABLE    (BIT(18))
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
-#define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
-/* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_RESET_DISABLE    (BIT(17))
-#define RTC_CNTL_USB_RESET_DISABLE_M  (BIT(17))
-#define RTC_CNTL_USB_RESET_DISABLE_V  0x1
-#define RTC_CNTL_USB_RESET_DISABLE_S  17
-/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_TX_EN_OVERRIDE    (BIT(16))
-#define RTC_CNTL_USB_TX_EN_OVERRIDE_M  (BIT(16))
-#define RTC_CNTL_USB_TX_EN_OVERRIDE_V  0x1
-#define RTC_CNTL_USB_TX_EN_OVERRIDE_S  16
-/* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_TX_EN    (BIT(15))
-#define RTC_CNTL_USB_TX_EN_M  (BIT(15))
-#define RTC_CNTL_USB_TX_EN_V  0x1
-#define RTC_CNTL_USB_TX_EN_S  15
-/* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_TXP    (BIT(14))
-#define RTC_CNTL_USB_TXP_M  (BIT(14))
-#define RTC_CNTL_USB_TXP_V  0x1
-#define RTC_CNTL_USB_TXP_S  14
-/* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_TXM    (BIT(13))
-#define RTC_CNTL_USB_TXM_M  (BIT(13))
-#define RTC_CNTL_USB_TXM_V  0x1
-#define RTC_CNTL_USB_TXM_S  13
-/* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_PAD_ENABLE    (BIT(12))
-#define RTC_CNTL_USB_PAD_ENABLE_M  (BIT(12))
-#define RTC_CNTL_USB_PAD_ENABLE_V  0x1
-#define RTC_CNTL_USB_PAD_ENABLE_S  12
-/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE    (BIT(11))
-#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M  (BIT(11))
-#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V  0x1
-#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S  11
-/* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_PULLUP_VALUE    (BIT(10))
-#define RTC_CNTL_USB_PULLUP_VALUE_M  (BIT(10))
-#define RTC_CNTL_USB_PULLUP_VALUE_V  0x1
-#define RTC_CNTL_USB_PULLUP_VALUE_S  10
-/* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_DM_PULLDOWN    (BIT(9))
-#define RTC_CNTL_USB_DM_PULLDOWN_M  (BIT(9))
-#define RTC_CNTL_USB_DM_PULLDOWN_V  0x1
-#define RTC_CNTL_USB_DM_PULLDOWN_S  9
-/* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_DM_PULLUP    (BIT(8))
-#define RTC_CNTL_USB_DM_PULLUP_M  (BIT(8))
-#define RTC_CNTL_USB_DM_PULLUP_V  0x1
-#define RTC_CNTL_USB_DM_PULLUP_S  8
-/* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_DP_PULLDOWN    (BIT(7))
-#define RTC_CNTL_USB_DP_PULLDOWN_M  (BIT(7))
-#define RTC_CNTL_USB_DP_PULLDOWN_V  0x1
-#define RTC_CNTL_USB_DP_PULLDOWN_S  7
-/* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_DP_PULLUP    (BIT(6))
-#define RTC_CNTL_USB_DP_PULLUP_M  (BIT(6))
-#define RTC_CNTL_USB_DP_PULLUP_V  0x1
-#define RTC_CNTL_USB_DP_PULLUP_S  6
-/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_PAD_PULL_OVERRIDE    (BIT(5))
-#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M  (BIT(5))
-#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V  0x1
-#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S  5
-/* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_VREF_OVERRIDE    (BIT(4))
-#define RTC_CNTL_USB_VREF_OVERRIDE_M  (BIT(4))
-#define RTC_CNTL_USB_VREF_OVERRIDE_V  0x1
-#define RTC_CNTL_USB_VREF_OVERRIDE_S  4
-/* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_VREFL    0x00000003
-#define RTC_CNTL_USB_VREFL_M  ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S))
-#define RTC_CNTL_USB_VREFL_V  0x3
-#define RTC_CNTL_USB_VREFL_S  2
-/* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: .*/
-#define RTC_CNTL_USB_VREFH    0x00000003
-#define RTC_CNTL_USB_VREFH_M  ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S))
-#define RTC_CNTL_USB_VREFH_V  0x3
-#define RTC_CNTL_USB_VREFH_S  0
-
-#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x124)
-/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_TIMEOUT_EN    (BIT(22))
-#define RTC_CNTL_TOUCH_TIMEOUT_EN_M  (BIT(22))
-#define RTC_CNTL_TOUCH_TIMEOUT_EN_V  0x1
-#define RTC_CNTL_TOUCH_TIMEOUT_EN_S  22
-/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_TIMEOUT_NUM    0x003FFFFF
-#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M  ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S))
-#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V  0x3FFFFF
-#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S  0
-
-#define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x128)
-/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: sleep reject cause.*/
-#define RTC_CNTL_REJECT_CAUSE    0x0003FFFF
-#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
-#define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
-#define RTC_CNTL_REJECT_CAUSE_S  0
-
-#define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0x12C)
-/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT    (BIT(0))
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
-#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
-
-#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x130)
-/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */
-/*description: sleep wakeup cause.*/
-#define RTC_CNTL_WAKEUP_CAUSE    0x0001FFFF
-#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
-#define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
-#define RTC_CNTL_WAKEUP_CAUSE_S  0
-
-#define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0x134)
-/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */
-/*description: sleep cycles for ULP-coprocessor timer.*/
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE    0x00FFFFFF
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
-#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
-
-#define RTC_CNTL_INT_ENA_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0x138)
-/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS    (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M  (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S  20
-/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: enable gitch det interrupt.*/
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS    (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S  19
-/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: enable touch timeout interrupt.*/
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS    (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M  (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S  18
-/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: enable cocpu trap interrupt.*/
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS    (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M  (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S  17
-/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: enable xtal32k_dead  interrupt.*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS    (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S  16
-/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define RTC_CNTL_SWD_INT_ENA_W1TS    (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
-/* RTC_CNTL_SARADC2_INT_ENA_W1TS : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: enable saradc2 interrupt.*/
-#define RTC_CNTL_SARADC2_INT_ENA_W1TS    (BIT(14))
-#define RTC_CNTL_SARADC2_INT_ENA_W1TS_M  (BIT(14))
-#define RTC_CNTL_SARADC2_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SARADC2_INT_ENA_W1TS_S  14
-/* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: enable riscV cocpu interrupt.*/
-#define RTC_CNTL_COCPU_INT_ENA_W1TS    (BIT(13))
-#define RTC_CNTL_COCPU_INT_ENA_W1TS_M  (BIT(13))
-#define RTC_CNTL_COCPU_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_COCPU_INT_ENA_W1TS_S  13
-/* RTC_CNTL_TSENS_INT_ENA_W1TS : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: enable tsens interrupt.*/
-#define RTC_CNTL_TSENS_INT_ENA_W1TS    (BIT(12))
-#define RTC_CNTL_TSENS_INT_ENA_W1TS_M  (BIT(12))
-#define RTC_CNTL_TSENS_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_TSENS_INT_ENA_W1TS_S  12
-/* RTC_CNTL_SARADC1_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: enable saradc1 interrupt.*/
-#define RTC_CNTL_SARADC1_INT_ENA_W1TS    (BIT(11))
-#define RTC_CNTL_SARADC1_INT_ENA_W1TS_M  (BIT(11))
-#define RTC_CNTL_SARADC1_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SARADC1_INT_ENA_W1TS_S  11
-/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt.*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt.*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
-/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: enable touch inactive interrupt.*/
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS    (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M  (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S  8
-/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: enable touch active interrupt.*/
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS    (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M  (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S  7
-/* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: enable touch done interrupt.*/
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS    (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M  (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S  6
-/* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: enable ULP-coprocessor interrupt.*/
-#define RTC_CNTL_ULP_CP_INT_ENA_W1TS    (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S  5
-/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: enable touch scan done interrupt.*/
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS    (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M  (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S  4
-/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define RTC_CNTL_WDT_INT_ENA_W1TS    (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: enable SDIO idle interrupt.*/
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS    (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S  2
-/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt.*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
-
-#define RTC_CNTL_INT_ENA_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0x13C)
-/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC    (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M  (BIT(20))
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S  20
-/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: enable gitch det interrupt.*/
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC    (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M  (BIT(19))
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S  19
-/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: enable touch timeout interrupt.*/
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC    (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M  (BIT(18))
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S  18
-/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC : WO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: enable cocpu trap interrupt.*/
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC    (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M  (BIT(17))
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S  17
-/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: enable xtal32k_dead  interrupt.*/
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC    (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M  (BIT(16))
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S  16
-/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: enable super watch dog interrupt.*/
-#define RTC_CNTL_SWD_INT_ENA_W1TC    (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
-#define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
-/* RTC_CNTL_SARADC2_INT_ENA_W1TC : WO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: enable saradc2 interrupt.*/
-#define RTC_CNTL_SARADC2_INT_ENA_W1TC    (BIT(14))
-#define RTC_CNTL_SARADC2_INT_ENA_W1TC_M  (BIT(14))
-#define RTC_CNTL_SARADC2_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SARADC2_INT_ENA_W1TC_S  14
-/* RTC_CNTL_COCPU_INT_ENA_W1TC : WO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: enable riscV cocpu interrupt.*/
-#define RTC_CNTL_COCPU_INT_ENA_W1TC    (BIT(13))
-#define RTC_CNTL_COCPU_INT_ENA_W1TC_M  (BIT(13))
-#define RTC_CNTL_COCPU_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_COCPU_INT_ENA_W1TC_S  13
-/* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: enable tsens interrupt.*/
-#define RTC_CNTL_TSENS_INT_ENA_W1TC    (BIT(12))
-#define RTC_CNTL_TSENS_INT_ENA_W1TC_M  (BIT(12))
-#define RTC_CNTL_TSENS_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_TSENS_INT_ENA_W1TC_S  12
-/* RTC_CNTL_SARADC1_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: enable saradc1 interrupt.*/
-#define RTC_CNTL_SARADC1_INT_ENA_W1TC    (BIT(11))
-#define RTC_CNTL_SARADC1_INT_ENA_W1TC_M  (BIT(11))
-#define RTC_CNTL_SARADC1_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SARADC1_INT_ENA_W1TC_S  11
-/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: enable RTC main timer interrupt.*/
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC    (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
-/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: enable brown out interrupt.*/
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC    (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
-/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: enable touch inactive interrupt.*/
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC    (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M  (BIT(8))
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S  8
-/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: enable touch active interrupt.*/
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC    (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M  (BIT(7))
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S  7
-/* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: enable touch done interrupt.*/
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC    (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M  (BIT(6))
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S  6
-/* RTC_CNTL_ULP_CP_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: enable ULP-coprocessor interrupt.*/
-#define RTC_CNTL_ULP_CP_INT_ENA_W1TC    (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M  (BIT(5))
-#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S  5
-/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: enable touch scan done interrupt.*/
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC    (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M  (BIT(4))
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S  4
-/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: enable RTC WDT interrupt.*/
-#define RTC_CNTL_WDT_INT_ENA_W1TC    (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
-#define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
-/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: enable SDIO idle interrupt.*/
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC    (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M  (BIT(2))
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S  2
-/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable sleep reject interrupt.*/
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC    (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
-/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable sleep wakeup interrupt.*/
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC    (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
-#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
-
-#define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x140)
-/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:25] ;default: 7'd20 ; */
-/*description: wait cycles for rention operation.*/
-#define RTC_CNTL_RETENTION_WAIT    0x0000007F
-#define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
-#define RTC_CNTL_RETENTION_WAIT_V  0x7F
-#define RTC_CNTL_RETENTION_WAIT_S  25
-/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: .*/
-#define RTC_CNTL_RETENTION_EN    (BIT(24))
-#define RTC_CNTL_RETENTION_EN_M  (BIT(24))
-#define RTC_CNTL_RETENTION_EN_V  0x1
-#define RTC_CNTL_RETENTION_EN_S  24
-/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[23:20] ;default: 4'd3 ; */
-/*description: .*/
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT    0x0000000F
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
-#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  20
-/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[19:17] ;default: 3'd2 ; */
-/*description: .*/
-#define RTC_CNTL_RETENTION_DONE_WAIT    0x00000007
-#define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
-#define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
-#define RTC_CNTL_RETENTION_DONE_WAIT_S  17
-/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_RETENTION_CLK_SEL    (BIT(16))
-#define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(16))
-#define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
-#define RTC_CNTL_RETENTION_CLK_SEL_S  16
-/* RTC_CNTL_RETENTION_TARGET : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
-/*description: .*/
-#define RTC_CNTL_RETENTION_TARGET    0x00000003
-#define RTC_CNTL_RETENTION_TARGET_M  ((RTC_CNTL_RETENTION_TARGET_V)<<(RTC_CNTL_RETENTION_TARGET_S))
-#define RTC_CNTL_RETENTION_TARGET_V  0x3
-#define RTC_CNTL_RETENTION_TARGET_S  14
-/* RTC_CNTL_RETENTION_TAG_MODE : R/W ;bitpos:[13:10] ;default: 4'd0 ; */
-/*description: .*/
-#define RTC_CNTL_RETENTION_TAG_MODE    0x0000000F
-#define RTC_CNTL_RETENTION_TAG_MODE_M  ((RTC_CNTL_RETENTION_TAG_MODE_V)<<(RTC_CNTL_RETENTION_TAG_MODE_S))
-#define RTC_CNTL_RETENTION_TAG_MODE_V  0xF
-#define RTC_CNTL_RETENTION_TAG_MODE_S  10
-
-#define RTC_CNTL_PG_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x144)
-/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_POWER_GLITCH_EN    (BIT(31))
-#define RTC_CNTL_POWER_GLITCH_EN_M  (BIT(31))
-#define RTC_CNTL_POWER_GLITCH_EN_V  0x1
-#define RTC_CNTL_POWER_GLITCH_EN_S  31
-/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: select use analog fib signal.*/
-#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL    (BIT(30))
-#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M  (BIT(30))
-#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V  0x1
-#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S  30
-/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_POWER_GLITCH_FORCE_PU    (BIT(29))
-#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M  (BIT(29))
-#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V  0x1
-#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S  29
-/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_POWER_GLITCH_FORCE_PD    (BIT(28))
-#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M  (BIT(28))
-#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V  0x1
-#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S  28
-/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */
-/*description: .*/
-#define RTC_CNTL_POWER_GLITCH_DSENSE    0x00000003
-#define RTC_CNTL_POWER_GLITCH_DSENSE_M  ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S))
-#define RTC_CNTL_POWER_GLITCH_DSENSE_V  0x3
-#define RTC_CNTL_POWER_GLITCH_DSENSE_S  26
-
-#define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x148)
-/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: .*/
-#define RTC_CNTL_FIB_SEL    0x00000007
-#define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
-#define RTC_CNTL_FIB_SEL_V  0x7
-#define RTC_CNTL_FIB_SEL_S  0
-
-#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
-#define RTC_CNTL_FIB_BOD_RST BIT(1)
-#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
-
-#define RTC_CNTL_TOUCH_DAC_REG          (DR_REG_RTCCNTL_BASE + 0x14C)
-/* RTC_CNTL_TOUCH_PAD0_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD0_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD0_DAC_M  ((RTC_CNTL_TOUCH_PAD0_DAC_V)<<(RTC_CNTL_TOUCH_PAD0_DAC_S))
-#define RTC_CNTL_TOUCH_PAD0_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD0_DAC_S  29
-/* RTC_CNTL_TOUCH_PAD1_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD1_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD1_DAC_M  ((RTC_CNTL_TOUCH_PAD1_DAC_V)<<(RTC_CNTL_TOUCH_PAD1_DAC_S))
-#define RTC_CNTL_TOUCH_PAD1_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD1_DAC_S  26
-/* RTC_CNTL_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD2_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD2_DAC_M  ((RTC_CNTL_TOUCH_PAD2_DAC_V)<<(RTC_CNTL_TOUCH_PAD2_DAC_S))
-#define RTC_CNTL_TOUCH_PAD2_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD2_DAC_S  23
-/* RTC_CNTL_TOUCH_PAD3_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD3_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD3_DAC_M  ((RTC_CNTL_TOUCH_PAD3_DAC_V)<<(RTC_CNTL_TOUCH_PAD3_DAC_S))
-#define RTC_CNTL_TOUCH_PAD3_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD3_DAC_S  20
-/* RTC_CNTL_TOUCH_PAD4_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD4_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD4_DAC_M  ((RTC_CNTL_TOUCH_PAD4_DAC_V)<<(RTC_CNTL_TOUCH_PAD4_DAC_S))
-#define RTC_CNTL_TOUCH_PAD4_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD4_DAC_S  17
-/* RTC_CNTL_TOUCH_PAD5_DAC : R/W ;bitpos:[16:14] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD5_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD5_DAC_M  ((RTC_CNTL_TOUCH_PAD5_DAC_V)<<(RTC_CNTL_TOUCH_PAD5_DAC_S))
-#define RTC_CNTL_TOUCH_PAD5_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD5_DAC_S  14
-/* RTC_CNTL_TOUCH_PAD6_DAC : R/W ;bitpos:[13:11] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD6_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD6_DAC_M  ((RTC_CNTL_TOUCH_PAD6_DAC_V)<<(RTC_CNTL_TOUCH_PAD6_DAC_S))
-#define RTC_CNTL_TOUCH_PAD6_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD6_DAC_S  11
-/* RTC_CNTL_TOUCH_PAD7_DAC : R/W ;bitpos:[10:8] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD7_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD7_DAC_M  ((RTC_CNTL_TOUCH_PAD7_DAC_V)<<(RTC_CNTL_TOUCH_PAD7_DAC_S))
-#define RTC_CNTL_TOUCH_PAD7_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD7_DAC_S  8
-/* RTC_CNTL_TOUCH_PAD8_DAC : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD8_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD8_DAC_M  ((RTC_CNTL_TOUCH_PAD8_DAC_V)<<(RTC_CNTL_TOUCH_PAD8_DAC_S))
-#define RTC_CNTL_TOUCH_PAD8_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD8_DAC_S  5
-/* RTC_CNTL_TOUCH_PAD9_DAC : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD9_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD9_DAC_M  ((RTC_CNTL_TOUCH_PAD9_DAC_V)<<(RTC_CNTL_TOUCH_PAD9_DAC_S))
-#define RTC_CNTL_TOUCH_PAD9_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD9_DAC_S  2
-
-#define RTC_CNTL_TOUCH_DAC1_REG          (DR_REG_RTCCNTL_BASE + 0x150)
-/* RTC_CNTL_TOUCH_PAD10_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD10_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD10_DAC_M  ((RTC_CNTL_TOUCH_PAD10_DAC_V)<<(RTC_CNTL_TOUCH_PAD10_DAC_S))
-#define RTC_CNTL_TOUCH_PAD10_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD10_DAC_S  29
-/* RTC_CNTL_TOUCH_PAD11_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD11_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD11_DAC_M  ((RTC_CNTL_TOUCH_PAD11_DAC_V)<<(RTC_CNTL_TOUCH_PAD11_DAC_S))
-#define RTC_CNTL_TOUCH_PAD11_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD11_DAC_S  26
-/* RTC_CNTL_TOUCH_PAD12_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD12_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD12_DAC_M  ((RTC_CNTL_TOUCH_PAD12_DAC_V)<<(RTC_CNTL_TOUCH_PAD12_DAC_S))
-#define RTC_CNTL_TOUCH_PAD12_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD12_DAC_S  23
-/* RTC_CNTL_TOUCH_PAD13_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD13_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD13_DAC_M  ((RTC_CNTL_TOUCH_PAD13_DAC_V)<<(RTC_CNTL_TOUCH_PAD13_DAC_S))
-#define RTC_CNTL_TOUCH_PAD13_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD13_DAC_S  20
-/* RTC_CNTL_TOUCH_PAD14_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */
-/*description: .*/
-#define RTC_CNTL_TOUCH_PAD14_DAC    0x00000007
-#define RTC_CNTL_TOUCH_PAD14_DAC_M  ((RTC_CNTL_TOUCH_PAD14_DAC_V)<<(RTC_CNTL_TOUCH_PAD14_DAC_S))
-#define RTC_CNTL_TOUCH_PAD14_DAC_V  0x7
-#define RTC_CNTL_TOUCH_PAD14_DAC_S  17
-
-#define RTC_CNTL_COCPU_DISABLE_REG          (DR_REG_RTCCNTL_BASE + 0x154)
-/* RTC_CNTL_DISABLE_RTC_CPU : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define RTC_CNTL_DISABLE_RTC_CPU    (BIT(31))
-#define RTC_CNTL_DISABLE_RTC_CPU_M  (BIT(31))
-#define RTC_CNTL_DISABLE_RTC_CPU_V  0x1
-#define RTC_CNTL_DISABLE_RTC_CPU_S  31
-
-/*
-Due to the LDO slaves, RTC_CNTL_DATE_REG[18:13] can only be used for LDO adjustment.
-*/
-#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x1FC)
-/* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101271 ; */
-/*description: .*/
-#define RTC_CNTL_DATE    0x0FFFFFFF
-#define RTC_CNTL_DATE_M  ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S))
-#define RTC_CNTL_DATE_V  0xFFFFFFF
-#define RTC_CNTL_DATE_S  0
-/*LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ;*/
-/*description: .*/
-#define RTC_CNTL_SLAVE_PD    0x0000003F
-#define RTC_CNTL_SLAVE_PD_M  ((RTC_CNTL_SLAVE_PD_V)<<(RTC_CNTL_SLAVE_PD_S))
-#define RTC_CNTL_SLAVE_PD_V  0x3F
-#define RTC_CNTL_SLAVE_PD_S  13
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_RTC_CNTL_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h b/components/soc/esp32s3/include/soc/rtc_cntl_struct.h
deleted file mode 100644
index 56e5f2d47e8..00000000000
--- a/components/soc/esp32s3/include/soc/rtc_cntl_struct.h
+++ /dev/null
@@ -1,1051 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _SOC_RTC_CNTL_STRUCT_H_
-#define _SOC_RTC_CNTL_STRUCT_H_
-
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct rtc_cntl_dev_s {
-    union {
-        struct {
-            uint32_t sw_stall_appcpu_c0            :    2;  /*{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
-            uint32_t sw_stall_procpu_c0            :    2;  /*{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
-            uint32_t sw_appcpu_rst                 :    1;  /*APP CPU SW reset*/
-            uint32_t sw_procpu_rst                 :    1;  /*PRO CPU SW reset*/
-            uint32_t bb_i2c_force_pd               :    1;  /*BB_I2C force power down*/
-            uint32_t bb_i2c_force_pu               :    1;  /*BB_I2C force power up*/
-            uint32_t bbpll_i2c_force_pd            :    1;  /*BB_PLL _I2C force power down*/
-            uint32_t bbpll_i2c_force_pu            :    1;  /*BB_PLL_I2C force power up*/
-            uint32_t bbpll_force_pd                :    1;  /*BB_PLL force power down*/
-            uint32_t bbpll_force_pu                :    1;  /*BB_PLL force power up*/
-            uint32_t xtl_force_pd                  :    1;  /*crystall force power down*/
-            uint32_t xtl_force_pu                  :    1;  /*crystall force power up*/
-            uint32_t xtl_en_wait                   :    4;  /*wait bias_sleep and current source wakeup*/
-            uint32_t reserved18                    :    5;
-            uint32_t xtl_force_iso                 :    1;
-            uint32_t pll_force_iso                 :    1;
-            uint32_t analog_force_iso              :    1;
-            uint32_t xtl_force_noiso               :    1;
-            uint32_t pll_force_noiso               :    1;
-            uint32_t analog_force_noiso            :    1;
-            uint32_t dg_wrap_force_rst             :    1;  /*digital wrap force reset in deep sleep*/
-            uint32_t dg_wrap_force_norst           :    1;  /*digital core force no reset in deep sleep*/
-            uint32_t sw_sys_rst                    :    1;  /*SW system reset*/
-        };
-        uint32_t val;
-    } options0;
-    uint32_t slp_timer0;
-    union {
-        struct {
-            uint32_t slp_val_hi                    :    16;  /*RTC sleep timer high 16 bits*/
-            uint32_t main_timer_alarm_en           :    1;  /*timer alarm enable bit*/
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } slp_timer1;
-    union {
-        struct {
-            uint32_t reserved0                     :    27;
-            uint32_t timer_sys_stall               :    1;  /*Enable to record system stall time*/
-            uint32_t timer_xtl_off                 :    1;  /*Enable to record 40M XTAL OFF time*/
-            uint32_t timer_sys_rst                 :    1;  /*enable to record system reset time*/
-            uint32_t reserved30                    :    1;
-            uint32_t update                        :    1;  /*Set 1: to update register with RTC timer*/
-        };
-        uint32_t val;
-    } time_update;
-    uint32_t time_low0;
-    union {
-        struct {
-            uint32_t rtc_timer_value0_high         :    16;  /*RTC timer high 16 bits*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } time_high0;
-    union {
-        struct {
-            uint32_t rtc_sw_cpu_int                :    1;  /*rtc software interrupt to main cpu*/
-            uint32_t rtc_slp_reject_cause_clr      :    1;  /*clear rtc sleep reject cause*/
-            uint32_t reserved2                     :    20;
-            uint32_t apb2rtc_bridge_sel            :    1;  /*1: APB to RTC using bridge*/
-            uint32_t reserved23                    :    5;
-            uint32_t sdio_active_ind               :    1;  /*SDIO active indication*/
-            uint32_t slp_wakeup                    :    1;  /*leep wakeup bit*/
-            uint32_t slp_reject                    :    1;  /*leep reject bit*/
-            uint32_t sleep_en                      :    1;  /*sleep enable bit*/
-        };
-        uint32_t val;
-    } state0;
-    union {
-        struct {
-            uint32_t cpu_stall_en                  :    1;  /*CPU stall enable bit*/
-            uint32_t cpu_stall_wait                :    5;  /*CPU stall wait cycles in fast_clk_rtc*/
-            uint32_t ck8m_wait                     :    8;  /*CK8M wait cycles in slow_clk_rtc*/
-            uint32_t xtl_buf_wait                  :    10;  /*XTAL wait cycles in slow_clk_rtc*/
-            uint32_t pll_buf_wait                  :    8;  /*PLL wait cycles in slow_clk_rtc*/
-        };
-        uint32_t val;
-    } timer1;
-    union {
-        struct {
-            uint32_t reserved0                     :    15;
-            uint32_t ulpcp_touch_start_wait        :    9;  /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/
-            uint32_t min_time_ck8m_off             :    8;  /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
-        };
-        uint32_t val;
-    } timer2;
-    union {
-        struct {
-            uint32_t wifi_wait_timer               :    9;
-            uint32_t wifi_powerup_timer            :    7;
-            uint32_t bt_wait_timer                 :    9;
-            uint32_t bt_powerup_timer              :    7;
-        };
-        uint32_t val;
-    } timer3;
-    union {
-        struct {
-            uint32_t rtc_wait_timer                :    9;
-            uint32_t rtc_powerup_timer             :    7;
-            uint32_t dg_wrap_wait_timer            :    9;
-            uint32_t dg_wrap_powerup_timer         :    7;
-        };
-        uint32_t val;
-    } timer4;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;
-            uint32_t min_slp_val                   :    8;  /*minimal sleep cycles in slow_clk_rtc*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } timer5;
-    union {
-        struct {
-            uint32_t cpu_top_wait_timer            :    9;
-            uint32_t cpu_top_powerup_timer         :    7;
-            uint32_t dg_peri_wait_timer            :    9;
-            uint32_t dg_peri_powerup_timer         :    7;
-        };
-        uint32_t val;
-    } timer6;
-    union {
-        struct {
-            uint32_t reserved0                     :    18;
-            uint32_t i2c_reset_por_force_pd        :    1;
-            uint32_t i2c_reset_por_force_pu        :    1;
-            uint32_t glitch_rst_en                 :    1;
-            uint32_t reserved21                    :    1;  /*PLLA force power down*/
-            uint32_t sar_i2c_pu                    :    1;  /*PLLA force power up*/
-            uint32_t analog_top_iso_sleep          :    1;  /*PLLA force power down*/
-            uint32_t analog_top_iso_monitor        :    1;  /*PLLA force power up*/
-            uint32_t bbpll_cal_slp_start           :    1;  /*start BBPLL calibration during sleep*/
-            uint32_t pvtmon_pu                     :    1;  /*1: PVTMON power up*/
-            uint32_t txrf_i2c_pu                   :    1;  /*1: TXRF_I2C power up*/
-            uint32_t rfrx_pbus_pu                  :    1;  /*1: RFRX_PBUS power up*/
-            uint32_t reserved29                    :    1;
-            uint32_t ckgen_i2c_pu                  :    1;  /*1: CKGEN_I2C power up*/
-            uint32_t pll_i2c_pu                    :    1;
-        };
-        uint32_t val;
-    } ana_conf;
-    union {
-        struct {
-            uint32_t reset_cause_procpu            :    6;  /*reset cause of PRO CPU*/
-            uint32_t reset_cause_appcpu            :    6;  /*reset cause of APP CPU*/
-            uint32_t appcpu_stat_vector_sel        :    1;  /*APP CPU state vector sel*/
-            uint32_t procpu_stat_vector_sel        :    1;  /*PRO CPU state vector sel*/
-            uint32_t reset_flag_procpu             :    1;  /*PRO CPU reset_flag*/
-            uint32_t reset_flag_appcpu             :    1;  /*APP CPU reset flag*/
-            uint32_t reset_flag_procpu_clr         :    1;  /*clear PRO CPU reset_flag*/
-            uint32_t reset_flag_appcpu_clr         :    1;  /*clear APP CPU reset flag*/
-            uint32_t appcpu_ocd_halt_on_reset      :    1;  /*APPCPU OcdHaltOnReset*/
-            uint32_t procpu_ocd_halt_on_reset      :    1;  /*PROCPU OcdHaltOnReset*/
-            uint32_t reset_flag_jtag_procpu        :    1;
-            uint32_t reset_flag_jtag_appcpu        :    1;
-            uint32_t reset_flag_jtag_procpu_clr    :    1;
-            uint32_t reset_flag_jtag_appcpu_clr    :    1;
-            uint32_t rtc_app_dreset_mask           :    1;
-            uint32_t rtc_pro_dreset_mask           :    1;
-            uint32_t reserved26                    :    6;
-        };
-        uint32_t val;
-    } reset_state;
-    union {
-        struct {
-            uint32_t reserved0                     :    15;
-            uint32_t rtc_wakeup_ena                :    17;  /*wakeup enable bitmap*/
-        };
-        uint32_t val;
-    } wakeup_state;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject                    :    1;  /*enable sleep reject interrupt*/
-            uint32_t sdio_idle                     :    1;  /*enable SDIO idle interrupt*/
-            uint32_t rtc_wdt                       :    1;  /*enable RTC WDT interrupt*/
-            uint32_t rtc_touch_scan_done           :    1;  /*enable touch scan done interrupt*/
-            uint32_t rtc_ulp_cp                    :    1;  /*enable ULP-coprocessor interrupt*/
-            uint32_t rtc_touch_done                :    1;  /*enable touch done interrupt*/
-            uint32_t rtc_touch_active              :    1;  /*enable touch active interrupt*/
-            uint32_t rtc_touch_inactive            :    1;  /*enable touch inactive interrupt*/
-            uint32_t rtc_brown_out                 :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer                :    1;  /*enable RTC main timer interrupt*/
-            uint32_t rtc_saradc1                   :    1;  /*enable saradc1 interrupt*/
-            uint32_t rtc_tsens                     :    1;  /*enable tsens interrupt*/
-            uint32_t rtc_cocpu                     :    1;  /*enable riscV cocpu interrupt*/
-            uint32_t rtc_saradc2                   :    1;  /*enable saradc2 interrupt*/
-            uint32_t rtc_swd                       :    1;  /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead              :    1;  /*enable xtal32k_dead  interrupt*/
-            uint32_t rtc_cocpu_trap                :    1;  /*enable cocpu trap interrupt*/
-            uint32_t rtc_touch_timeout             :    1;  /*enable touch timeout interrupt*/
-            uint32_t rtc_glitch_det                :    1;  /*enbale gitch det interrupt*/
-            uint32_t rtc_touch_approach_loop_done  :    1;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt raw*/
-            uint32_t slp_reject                    :    1;  /*sleep reject interrupt raw*/
-            uint32_t sdio_idle                     :    1;  /*SDIO idle interrupt raw*/
-            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt raw*/
-            uint32_t rtc_touch_scan_done           :    1;
-            uint32_t rtc_ulp_cp                    :    1;  /*ULP-coprocessor interrupt raw*/
-            uint32_t rtc_touch_done                :    1;  /*touch interrupt raw*/
-            uint32_t rtc_touch_active              :    1;  /*touch active interrupt raw*/
-            uint32_t rtc_touch_inactive            :    1;  /*touch inactive interrupt raw*/
-            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt raw*/
-            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt raw*/
-            uint32_t rtc_saradc1                   :    1;  /*saradc1 interrupt raw*/
-            uint32_t rtc_tsens                     :    1;  /*tsens interrupt raw*/
-            uint32_t rtc_cocpu                     :    1;  /*riscV cocpu interrupt raw*/
-            uint32_t rtc_saradc2                   :    1;  /*saradc2 interrupt raw*/
-            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt raw*/
-            uint32_t rtc_xtal32k_dead              :    1;  /*xtal32k dead detection interrupt raw*/
-            uint32_t rtc_cocpu_trap                :    1;  /*cocpu trap interrupt raw*/
-            uint32_t rtc_touch_timeout             :    1;  /*touch timeout interrupt raw*/
-            uint32_t rtc_glitch_det                :    1;  /*glitch_det_interrupt_raw*/
-            uint32_t rtc_touch_approach_loop_done  :    1;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt state*/
-            uint32_t slp_reject                    :    1;  /*sleep reject interrupt state*/
-            uint32_t sdio_idle                     :    1;  /*SDIO idle interrupt state*/
-            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt state*/
-            uint32_t rtc_touch_scan_done           :    1;
-            uint32_t rtc_ulp_cp                    :    1;  /*ULP-coprocessor interrupt state*/
-            uint32_t rtc_touch_done                :    1;  /*touch done interrupt state*/
-            uint32_t rtc_touch_active              :    1;  /*touch active interrupt state*/
-            uint32_t rtc_touch_inactive            :    1;  /*touch inactive interrupt state*/
-            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt state*/
-            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt state*/
-            uint32_t rtc_saradc1                   :    1;  /*saradc1 interrupt state*/
-            uint32_t rtc_tsens                     :    1;  /*tsens interrupt state*/
-            uint32_t rtc_cocpu                     :    1;  /*riscV cocpu interrupt state*/
-            uint32_t rtc_saradc2                   :    1;  /*saradc2 interrupt state*/
-            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt state*/
-            uint32_t rtc_xtal32k_dead              :    1;  /*xtal32k dead detection interrupt state*/
-            uint32_t rtc_cocpu_trap                :    1;  /*cocpu trap interrupt state*/
-            uint32_t rtc_touch_timeout             :    1;  /*Touch timeout interrupt state*/
-            uint32_t rtc_glitch_det                :    1;  /*glitch_det_interrupt state*/
-            uint32_t rtc_touch_approach_loop_done  :    1;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*Clear sleep wakeup interrupt state*/
-            uint32_t slp_reject                    :    1;  /*Clear sleep reject interrupt state*/
-            uint32_t sdio_idle                     :    1;  /*Clear SDIO idle interrupt state*/
-            uint32_t rtc_wdt                       :    1;  /*Clear RTC WDT interrupt state*/
-            uint32_t rtc_touch_scan_done           :    1;
-            uint32_t rtc_ulp_cp                    :    1;  /*Clear ULP-coprocessor interrupt state*/
-            uint32_t rtc_touch_done                :    1;  /*Clear touch done interrupt state*/
-            uint32_t rtc_touch_active              :    1;  /*Clear touch active interrupt state*/
-            uint32_t rtc_touch_inactive            :    1;  /*Clear touch inactive interrupt state*/
-            uint32_t rtc_brown_out                 :    1;  /*Clear brown out interrupt state*/
-            uint32_t rtc_main_timer                :    1;  /*Clear RTC main timer interrupt state*/
-            uint32_t rtc_saradc1                   :    1;  /*Clear saradc1 interrupt state*/
-            uint32_t rtc_tsens                     :    1;  /*Clear tsens interrupt state*/
-            uint32_t rtc_cocpu                     :    1;  /*Clear riscV cocpu interrupt state*/
-            uint32_t rtc_saradc2                   :    1;  /*Clear saradc2 interrupt state*/
-            uint32_t rtc_swd                       :    1;  /*Clear super watch dog interrupt state*/
-            uint32_t rtc_xtal32k_dead              :    1;  /*Clear RTC WDT interrupt state*/
-            uint32_t rtc_cocpu_trap                :    1;  /*Clear cocpu trap interrupt state*/
-            uint32_t rtc_touch_timeout             :    1;  /*Clear touch timeout interrupt state*/
-            uint32_t rtc_glitch_det                :    1;  /*Clear glitch det interrupt state*/
-            uint32_t rtc_touch_approach_loop_done  :    1;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } int_clr;
-    uint32_t store[4];
-    union {
-        struct {
-            uint32_t xtal32k_wdt_en                :    1;  /*xtal 32k watch dog enable*/
-            uint32_t xtal32k_wdt_clk_fo            :    1;  /*xtal 32k watch dog clock force on*/
-            uint32_t xtal32k_wdt_reset             :    1;  /*xtal 32k watch dog sw reset*/
-            uint32_t xtal32k_ext_clk_fo            :    1;  /*xtal 32k external xtal clock force on*/
-            uint32_t xtal32k_auto_backup           :    1;  /*xtal 32k switch to back up clock when xtal is dead*/
-            uint32_t xtal32k_auto_restart          :    1;  /*xtal 32k restart xtal when xtal is dead*/
-            uint32_t xtal32k_auto_return           :    1;  /*xtal 32k switch back xtal when xtal is restarted*/
-            uint32_t xtal32k_xpd_force             :    1;  /*Xtal 32k xpd control by sw or fsm*/
-            uint32_t enckinit_xtal_32k             :    1;  /*apply an internal clock to help xtal 32k to start*/
-            uint32_t dbuf_xtal_32k                 :    1;  /*0: single-end buffer 1: differential buffer*/
-            uint32_t dgm_xtal_32k                  :    3;  /*xtal_32k gm control*/
-            uint32_t dres_xtal_32k                 :    3;  /*DRES_XTAL_32K*/
-            uint32_t xpd_xtal_32k                  :    1;  /*XPD_XTAL_32K*/
-            uint32_t dac_xtal_32k                  :    3;  /*DAC_XTAL_32K*/
-            uint32_t rtc_wdt_state                 :    3;  /*state of 32k_wdt*/
-            uint32_t rtc_xtal32k_gpio_sel          :    1;  /*XTAL_32K sel. 0: external XTAL_32K*/
-            uint32_t reserved24                    :    6;
-            uint32_t ctr_lv                        :    1;  /*0: power down XTAL at high level*/
-            uint32_t ctr_en                        :    1;
-        };
-        uint32_t val;
-    } ext_xtl_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    29;
-            uint32_t gpio_wakeup_filter            :    1;  /*enable filter for gpio wakeup event*/
-            uint32_t ext_wakeup0_lv                :    1;  /*0: external wakeup at low level*/
-            uint32_t ext_wakeup1_lv                :    1;
-        };
-        uint32_t val;
-    } ext_wakeup_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    12;
-            uint32_t rtc_sleep_reject_ena          :    18;  /*sleep reject enable*/
-            uint32_t light_slp_reject_en           :    1;  /*enable reject for light sleep*/
-            uint32_t deep_slp_reject_en            :    1;  /*enable reject for deep sleep*/
-        };
-        uint32_t val;
-    } slp_reject_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    29;
-            uint32_t cpusel_conf                   :    1;  /*CPU sel option*/
-            uint32_t cpuperiod_sel                 :    2;
-        };
-        uint32_t val;
-    } cpu_period_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    22;
-            uint32_t sdio_act_dnum                 :    10;
-        };
-        uint32_t val;
-    } sdio_act_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;
-            uint32_t efuse_clk_force_gating        :    1;
-            uint32_t efuse_clk_force_nogating      :    1;
-            uint32_t ck8m_div_sel_vld              :    1;  /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
-            uint32_t ck8m_div                      :    2;  /*CK8M_D256_OUT divider. 00: div128*/
-            uint32_t enb_ck8m                      :    1;  /*disable CK8M and CK8M_D256_OUT*/
-            uint32_t enb_ck8m_div                  :    1;  /*1: CK8M_D256_OUT is actually CK8M*/
-            uint32_t dig_xtal32k_en                :    1;  /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_d256_en             :    1;  /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_en                  :    1;  /*enable CK8M for digital core (no relationship with RTC core)*/
-            uint32_t reserved11                    :    1;
-            uint32_t ck8m_div_sel                  :    3;  /*divider = reg_ck8m_div_sel + 1*/
-            uint32_t xtal_force_nogating           :    1;  /*XTAL force no gating during sleep*/
-            uint32_t ck8m_force_nogating           :    1;  /*CK8M force no gating during sleep*/
-            uint32_t ck8m_dfreq                    :    8;  /*CK8M_DFREQ*/
-            uint32_t ck8m_force_pd                 :    1;  /*CK8M force power down*/
-            uint32_t ck8m_force_pu                 :    1;  /*CK8M force power up*/
-            uint32_t xtal_global_force_gating      :    1;
-            uint32_t xtal_global_force_nogating    :    1;
-            uint32_t fast_clk_rtc_sel              :    1;  /*fast_clk_rtc sel. 0: XTAL div 2*/
-            uint32_t ana_clk_rtc_sel               :    2;
-        };
-        uint32_t val;
-    } clk_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    22;
-            uint32_t rtc_ana_clk_div_vld           :    1;  /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
-            uint32_t rtc_ana_clk_div               :    8;
-            uint32_t slow_clk_next_edge            :    1;
-        };
-        uint32_t val;
-    } slow_clk_conf;
-    union {
-        struct {
-            uint32_t sdio_timer_target             :    8;  /*timer count to apply reg_sdio_dcap after sdio power on*/
-            uint32_t reserved8                     :    1;
-            uint32_t sdio_dthdrv                   :    2;  /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
-            uint32_t sdio_dcap                     :    2;  /*ability to prevent LDO from overshoot*/
-            uint32_t sdio_initi                    :    2;  /*add resistor from ldo output to ground. 0: no res*/
-            uint32_t sdio_en_initi                 :    1;  /*0 to set init[1:0]=0*/
-            uint32_t sdio_dcurlim                  :    3;  /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
-            uint32_t sdio_modecurlim               :    1;  /*select current limit mode*/
-            uint32_t sdio_encurlim                 :    1;  /*enable current limit*/
-            uint32_t sdio_pd_en                    :    1;  /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
-            uint32_t sdio_force                    :    1;  /*1: use SW option to control SDIO_REG*/
-            uint32_t sdio_tieh                     :    1;  /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
-            uint32_t reg1p8_ready                  :    1;  /*read only register for REG1P8_READY*/
-            uint32_t drefl_sdio                    :    2;  /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t drefm_sdio                    :    2;  /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t drefh_sdio                    :    2;  /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t xpd_sdio                      :    1;
-        };
-        uint32_t val;
-    } sdio_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    10;
-            uint32_t bias_buf_idle                 :    1;
-            uint32_t bias_buf_wake                 :    1;
-            uint32_t bias_buf_deep_slp             :    1;
-            uint32_t bias_buf_monitor              :    1;
-            uint32_t pd_cur_deep_slp               :    1;  /*xpd cur when rtc in sleep_state*/
-            uint32_t pd_cur_monitor                :    1;  /*xpd cur when rtc in monitor state*/
-            uint32_t bias_sleep_deep_slp           :    1;  /*bias_sleep when rtc in sleep_state*/
-            uint32_t bias_sleep_monitor            :    1;  /*bias_sleep when rtc in monitor state*/
-            uint32_t dbg_atten_deep_slp            :    4;  /*DBG_ATTEN when rtc in sleep state*/
-            uint32_t dbg_atten_monitor             :    4;  /*DBG_ATTEN when rtc in monitor state*/
-            uint32_t dbg_atten_wakeup              :    4;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } bias_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;
-            uint32_t dig_cal_en                    :    1;
-            uint32_t reserved8                     :    6;
-            uint32_t sck_dcap                      :    8;  /*SCK_DCAP*/
-            uint32_t reserved22                    :    6;
-            uint32_t rtc_dboost_force_pd           :    1;  /*RTC_DBOOST force power down*/
-            uint32_t rtc_dboost_force_pu           :    1;  /*RTC_DBOOST force power up*/
-            uint32_t rtculator_force_pd            :    1;  /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
-            uint32_t rtculator_force_pu            :    1;
-        };
-        uint32_t val;
-    } rtc;
-    union {
-        struct {
-            uint32_t rtc_fastmem_force_noiso       :    1;  /*Fast RTC memory force no ISO*/
-            uint32_t rtc_fastmem_force_iso         :    1;  /*Fast RTC memory force ISO*/
-            uint32_t rtc_slowmem_force_noiso       :    1;  /*RTC memory force no ISO*/
-            uint32_t rtc_slowmem_force_iso         :    1;  /*RTC memory force ISO*/
-            uint32_t rtc_force_iso                 :    1;  /*rtc_peri force ISO*/
-            uint32_t rtc_force_noiso               :    1;  /*rtc_peri force no ISO*/
-            uint32_t rtc_fastmem_folw_cpu          :    1;  /*1: Fast RTC memory PD following CPU*/
-            uint32_t fastmem_force_lpd             :    1;  /*Fast RTC memory force PD*/
-            uint32_t fastmem_force_lpu             :    1;  /*Fast RTC memory force no PD*/
-            uint32_t rtc_slowmem_folw_cpu          :    1;  /*1: RTC memory  PD following CPU*/
-            uint32_t rtc_slowmem_force_lpd         :    1;  /*RTC memory force PD*/
-            uint32_t rtc_slowmem_force_lpu         :    1;  /*RTC memory force no PD*/
-            uint32_t reserved12                    :    6;  /*enable power down RTC memory in sleep*/
-            uint32_t rtc_force_pd                  :    1;  /*rtc_peri force power down*/
-            uint32_t rtc_force_pu                  :    1;  /*rtc_peri force power up*/
-            uint32_t rtc_pd_en                     :    1;  /*enable power down rtc_peri in sleep */
-            uint32_t rtc_pad_force_hold            :    1;  /*rtc pad force hold*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } pwc;
-    union {
-        struct {
-            uint32_t rtculator_drv_b_monitor       :    6;
-            uint32_t rtculator_drv_b_slp           :    6;
-            uint32_t dg_vdd_drv_b_slp              :    8;
-            uint32_t dg_vdd_drv_b_monitor          :    8;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } regulator_drv_ctrl;
-    union {
-        struct {
-            uint32_t reserved0                     :    3;
-            uint32_t lslp_mem_force_pd             :    1;  /*memories in digital core force PD in sleep*/
-            uint32_t lslp_mem_force_pu             :    1;  /*memories in digital core force no PD in sleep*/
-            uint32_t reserved5                     :    6;  /*internal SRAM 1 force power up*/
-            uint32_t bt_force_pd                   :    1;  /*internal SRAM 2 force power down*/
-            uint32_t bt_force_pu                   :    1;  /*internal SRAM 2 force power up*/
-            uint32_t dg_peri_force_pd              :    1;  /*internal SRAM 3 force power down*/
-            uint32_t dg_peri_force_pu              :    1;  /*internal SRAM 3 force power up*/
-            uint32_t reserved15                    :    2;  /*internal SRAM 4 force power up*/
-            uint32_t wifi_force_pd                 :    1;  /*wifi force power down*/
-            uint32_t wifi_force_pu                 :    1;  /*wifi force power up*/
-            uint32_t dg_wrap_force_pd              :    1;  /*digital core force power down*/
-            uint32_t dg_wrap_force_pu              :    1;  /*digital core force power up*/
-            uint32_t cpu_top_force_pd              :    1;  /*digital dcdc force power down*/
-            uint32_t cpu_top_force_pu              :    1;  /*digital dcdc force power up*/
-            uint32_t reserved23                    :    4;  /*enable power down internal SRAM 1 in sleep*/
-            uint32_t bt_pd_en                      :    1;  /*enable power down internal SRAM 2 in sleep*/
-            uint32_t dg_peri_pd_en                 :    1;  /*enable power down internal SRAM 3 in sleep*/
-            uint32_t cpu_top_pd_en                 :    1;  /*enable power down internal SRAM 4 in sleep*/
-            uint32_t wifi_pd_en                    :    1;  /*enable power down wifi in sleep*/
-            uint32_t dg_wrap_pd_en                 :    1;
-        };
-        uint32_t val;
-    } dig_pwc;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;
-            uint32_t dig_iso_force_off             :    1;
-            uint32_t dig_iso_force_on              :    1;
-            uint32_t dg_pad_autohold               :    1;  /*read only register to indicate digital pad auto-hold status*/
-            uint32_t clr_dg_pad_autohold           :    1;  /*wtite only register to clear digital pad auto-hold*/
-            uint32_t dg_pad_autohold_en            :    1;  /*digital pad enable auto-hold*/
-            uint32_t dg_pad_force_noiso            :    1;  /*digital pad force no ISO*/
-            uint32_t dg_pad_force_iso              :    1;  /*digital pad force ISO*/
-            uint32_t dg_pad_force_unhold           :    1;  /*digital pad force un-hold*/
-            uint32_t dg_pad_force_hold             :    1;  /*digital pad force hold*/
-            uint32_t reserved16                    :    6;  /*internal SRAM 1 force no ISO*/
-            uint32_t bt_force_iso                  :    1;  /*internal SRAM 2 force ISO*/
-            uint32_t bt_force_noiso                :    1;  /*internal SRAM 2 force no ISO*/
-            uint32_t dg_peri_force_iso             :    1;  /*internal SRAM 3 force ISO*/
-            uint32_t dg_peri_force_noiso           :    1;  /*internal SRAM 3 force no ISO*/
-            uint32_t cpu_top_force_iso             :    1;  /*internal SRAM 4 force ISO*/
-            uint32_t cpu_top_force_noiso           :    1;  /*internal SRAM 4 force no ISO*/
-            uint32_t wifi_force_iso                :    1;  /*wifi force ISO*/
-            uint32_t wifi_force_noiso              :    1;  /*wifi force no ISO*/
-            uint32_t dg_wrap_force_iso             :    1;  /*digital core force ISO*/
-            uint32_t dg_wrap_force_noiso           :    1;
-        };
-        uint32_t val;
-    } dig_iso;
-    union {
-        struct {
-            uint32_t chip_reset_width              :    8;  /*chip reset siginal pulse width*/
-            uint32_t chip_reset_en                 :    1;  /*wdt reset whole chip enable*/
-            uint32_t pause_in_slp                  :    1;  /*pause WDT in sleep*/
-            uint32_t appcpu_reset_en               :    1;  /*enable WDT reset APP CPU*/
-            uint32_t procpu_reset_en               :    1;  /*enable WDT reset PRO CPU*/
-            uint32_t flashboot_mod_en              :    1;  /*enable WDT in flash boot*/
-            uint32_t sys_reset_length              :    3;  /*system reset counter length*/
-            uint32_t cpu_reset_length              :    3;  /*CPU reset counter length*/
-            uint32_t stg3                          :    3;  /*1: interrupt stage en*/
-            uint32_t stg2                          :    3;  /*1: interrupt stage en*/
-            uint32_t stg1                          :    3;  /*1: interrupt stage en*/
-            uint32_t stg0                          :    3;  /*1: interrupt stage en*/
-            uint32_t en                            :    1;
-        };
-        uint32_t val;
-    } wdt_config0;
-    uint32_t wdt_config1;
-    uint32_t wdt_config2;
-    uint32_t wdt_config3;
-    uint32_t wdt_config4;
-    union {
-        struct {
-            uint32_t reserved0                     :    31;
-            uint32_t feed                          :    1;
-        };
-        uint32_t val;
-    } wdt_feed;
-    uint32_t wdt_wprotect;
-    union {
-        struct {
-            uint32_t swd_reset_flag                :    1;  /*swd reset flag*/
-            uint32_t swd_feed_int                  :    1;  /*swd interrupt for feeding*/
-            uint32_t reserved2                     :    15;
-            uint32_t swd_bypass_rst                :    1;
-            uint32_t swd_signal_width              :    10;  /*adjust signal width send to swd*/
-            uint32_t swd_rst_flag_clr              :    1;  /*reset swd reset flag*/
-            uint32_t swd_feed                      :    1;  /*Sw feed swd*/
-            uint32_t swd_disable                   :    1;  /*disabel SWD*/
-            uint32_t swd_auto_feed_en              :    1;  /*automatically feed swd when int comes*/
-        };
-        uint32_t val;
-    } swd_conf;
-    uint32_t swd_wprotect;
-    union {
-        struct {
-            uint32_t reserved0                     :    20;
-            uint32_t appcpu_c1                     :    6;  /*{reg_sw_stall_appcpu_c1[5:0]*/
-            uint32_t procpu_c1                     :    6;
-        };
-        uint32_t val;
-    } sw_cpu_stall;
-    uint32_t store4;
-    uint32_t store5;
-    uint32_t store6;
-    uint32_t store7;
-    union {
-        struct {
-            uint32_t xpd_rom0                      :    1;  /*rom0 power down*/
-            uint32_t reserved1                     :    1;
-            uint32_t xpd_dig_dcdc                  :    1;  /*External DCDC power down*/
-            uint32_t rtc_peri_iso                  :    1;  /*rtc peripheral iso*/
-            uint32_t xpd_rtc_peri                  :    1;  /*rtc peripheral power down */
-            uint32_t wifi_iso                      :    1;  /*wifi iso*/
-            uint32_t xpd_wifi                      :    1;  /*wifi wrap power down*/
-            uint32_t dig_iso                       :    1;  /*digital wrap iso*/
-            uint32_t xpd_dig                       :    1;  /*digital wrap power down*/
-            uint32_t rtc_touch_state_start         :    1;  /*touch should start to work*/
-            uint32_t rtc_touch_state_switch        :    1;  /*touch is about to working. Switch rtc main state*/
-            uint32_t rtc_touch_state_slp           :    1;  /*touch is in sleep state*/
-            uint32_t rtc_touch_state_done          :    1;  /*touch is done*/
-            uint32_t rtc_cocpu_state_start         :    1;  /*ulp/cocpu should start to work*/
-            uint32_t rtc_cocpu_state_switch        :    1;  /*ulp/cocpu is about to working. Switch rtc main state*/
-            uint32_t rtc_cocpu_state_slp           :    1;  /*ulp/cocpu is in sleep state*/
-            uint32_t rtc_cocpu_state_done          :    1;  /*ulp/cocpu is done*/
-            uint32_t rtc_main_state_xtal_iso       :    1;  /*no use any more*/
-            uint32_t rtc_main_state_pll_on         :    1;  /*rtc main state machine is in states that pll should be running*/
-            uint32_t rtc_rdy_for_wakeup            :    1;  /*rtc is ready to receive wake up trigger from wake up source*/
-            uint32_t rtc_main_state_wait_end       :    1;  /*rtc main state machine has been waited for some cycles*/
-            uint32_t rtc_in_wakeup_state           :    1;  /*rtc main state machine is in the states of wakeup process*/
-            uint32_t rtc_in_low_power_state        :    1;  /*rtc main state machine is in the states of low power*/
-            uint32_t rtc_main_state_in_wait_8m     :    1;  /*rtc main state machine is in wait 8m state*/
-            uint32_t rtc_main_state_in_wait_pll    :    1;  /*rtc main state machine is in wait pll state*/
-            uint32_t rtc_main_state_in_wait_xtl    :    1;  /*rtc main state machine is in wait xtal state*/
-            uint32_t rtc_main_state_in_slp         :    1;  /*rtc main state machine is in sleep state*/
-            uint32_t rtc_main_state_in_idle        :    1;  /*rtc main state machine is in idle state*/
-            uint32_t rtc_main_state                :    4;  /*rtc main state machine status*/
-        };
-        uint32_t val;
-    } low_power_st;
-    uint32_t diag0;
-    union {
-        struct {
-            uint32_t touch_pad0_hold               :    1;
-            uint32_t touch_pad1_hold               :    1;
-            uint32_t touch_pad2_hold               :    1;
-            uint32_t touch_pad3_hold               :    1;
-            uint32_t touch_pad4_hold               :    1;
-            uint32_t touch_pad5_hold               :    1;
-            uint32_t touch_pad6_hold               :    1;
-            uint32_t touch_pad7_hold               :    1;
-            uint32_t touch_pad8_hold               :    1;
-            uint32_t touch_pad9_hold               :    1;
-            uint32_t touch_pad10_hold              :    1;
-            uint32_t touch_pad11_hold              :    1;
-            uint32_t touch_pad12_hold              :    1;
-            uint32_t touch_pad13_hold              :    1;
-            uint32_t touch_pad14_hold              :    1;
-            uint32_t x32p_hold                     :    1;
-            uint32_t x32n_hold                     :    1;
-            uint32_t pdac1_hold                    :    1;
-            uint32_t pdac2_hold                    :    1;
-            uint32_t rtc_pad19_hold                :    1;
-            uint32_t rtc_pad20_hold                :    1;
-            uint32_t rtc_pad21_hold                :    1;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } pad_hold;
-    uint32_t dig_pad_hold;
-    union {
-        struct {
-            uint32_t ext_wakeup1_sel               :    22;  /*Bitmap to select RTC pads for ext wakeup1*/
-            uint32_t ext_wakeup1_status_clr        :    1;  /*clear ext wakeup1 status*/
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } ext_wakeup1;
-    union {
-        struct {
-            uint32_t ext_wakeup1_status            :    22;  /*ext wakeup1 status*/
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } ext_wakeup1_status;
-    union {
-        struct {
-            uint32_t reserved0                     :    4;
-            uint32_t int_wait                      :    10;  /*brown out interrupt wait cycles*/
-            uint32_t close_flash_ena               :    1;  /*enable close flash when brown out happens*/
-            uint32_t pd_rf_ena                     :    1;  /*enable power down RF when brown out happens*/
-            uint32_t rst_wait                      :    10;  /*brown out reset wait cycles*/
-            uint32_t rst_ena                       :    1;  /*enable brown out reset*/
-            uint32_t rst_sel                       :    1;  /*1:  4-pos reset*/
-            uint32_t ana_rst_en                    :    1;
-            uint32_t cnt_clr                       :    1;  /*clear brown out counter*/
-            uint32_t ena                           :    1;  /*enable brown out*/
-            uint32_t det                           :    1;
-        };
-        uint32_t val;
-    } brown_out;
-    uint32_t time_low1;
-    union {
-        struct {
-            uint32_t rtc_timer_value1_high         :    16;  /*RTC timer high 16 bits*/
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } time_high1;
-    uint32_t xtal32k_clk_factor;
-    union {
-        struct {
-            uint32_t xtal32k_return_wait           :    4;  /*cycles to wait to return noral xtal 32k*/
-            uint32_t xtal32k_restart_wait          :    16;  /*cycles to wait to repower on xtal 32k*/
-            uint32_t xtal32k_wdt_timeout           :    8;  /*If no clock detected for this amount of time*/
-            uint32_t xtal32k_stable_thres          :    4;  /*if restarted xtal32k period is smaller than this*/
-        };
-        uint32_t val;
-    } xtal32k_conf;
-    union {
-        struct {
-            uint32_t ulp_cp_pc_init                :    11;  /*ULP-coprocessor PC initial address*/
-            uint32_t reserved11                    :    18;
-            uint32_t ulp_cp_gpio_wakeup_ena        :    1;  /*ULP-coprocessor wakeup by GPIO enable*/
-            uint32_t ulp_cp_gpio_wakeup_clr        :    1;  /*ULP-coprocessor wakeup by GPIO state clear*/
-            uint32_t ulp_cp_slp_timer_en           :    1;  /*ULP-coprocessor timer enable bit*/
-        };
-        uint32_t val;
-    } ulp_cp_timer;
-    union {
-        struct {
-            uint32_t ulp_cp_mem_addr_init          :    11;
-            uint32_t ulp_cp_mem_addr_size          :    11;
-            uint32_t ulp_cp_mem_offst_clr          :    1;
-            uint32_t reserved23                    :    5;
-            uint32_t ulp_cp_clk_fo                 :    1;  /*ulp coprocessor clk force on*/
-            uint32_t ulp_cp_reset                  :    1;  /*ulp coprocessor clk software reset*/
-            uint32_t ulp_cp_force_start_top        :    1;  /*1: ULP-coprocessor is started by SW*/
-            uint32_t ulp_cp_start_top              :    1;  /*Write 1 to start ULP-coprocessor*/
-        };
-        uint32_t val;
-    } ulp_cp_ctrl;
-    union {
-        struct {
-            uint32_t cocpu_clk_fo                  :    1;  /*cocpu clk force on*/
-            uint32_t cocpu_start_2_reset_dis       :    6;  /*time from start cocpu to pull down reset*/
-            uint32_t cocpu_start_2_intr_en         :    6;  /*time from start cocpu to give start interrupt*/
-            uint32_t cocpu_shut                    :    1;  /*to shut cocpu*/
-            uint32_t cocpu_shut_2_clk_dis          :    8;  /*time from shut cocpu to disable clk*/
-            uint32_t cocpu_shut_reset_en           :    1;  /*to reset cocpu*/
-            uint32_t cocpu_sel                     :    1;  /*1: old ULP 0: new riscV*/
-            uint32_t cocpu_done_force              :    1;  /*1: select riscv done 0: select ulp done*/
-            uint32_t cocpu_done                    :    1;  /*done signal used by riscv to control timer. */
-            uint32_t cocpu_sw_int_trigger          :    1;  /*trigger cocpu register interrupt*/
-            uint32_t cocpu_clkgate_en              :    1;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } cocpu_ctrl;
-    union {
-        struct {
-            uint32_t touch_sleep_cycles            :    16;  /*sleep cycles for timer*/
-            uint32_t touch_meas_num                :    16;  /*the meas length (in 8MHz)*/
-        };
-        uint32_t val;
-    } touch_ctrl1;
-    union {
-        struct {
-            uint32_t reserved0                     :    2;
-            uint32_t touch_drange                  :    2;  /*TOUCH_DRANGE*/
-            uint32_t touch_drefl                   :    2;  /*TOUCH_DREFL*/
-            uint32_t touch_drefh                   :    2;  /*TOUCH_DREFH*/
-            uint32_t touch_xpd_bias                :    1;  /*TOUCH_XPD_BIAS*/
-            uint32_t touch_refc                    :    3;  /*TOUCH pad0 reference cap*/
-            uint32_t touch_dbias                   :    1;  /*1:use self bias 0:use bandgap bias*/
-            uint32_t touch_slp_timer_en            :    1;  /*touch timer enable bit*/
-            uint32_t touch_start_fsm_en            :    1;  /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/
-            uint32_t touch_start_en                :    1;  /*1: start touch fsm*/
-            uint32_t touch_start_force             :    1;  /*1: to start touch fsm by SW*/
-            uint32_t touch_xpd_wait                :    8;  /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
-            uint32_t touch_slp_cyc_div             :    2;  /*when a touch pad is active*/
-            uint32_t touch_timer_force_done        :    2;  /*force touch timer done*/
-            uint32_t touch_reset                   :    1;  /*reset upgrade touch*/
-            uint32_t touch_clk_fo                  :    1;  /*touch clock force on*/
-            uint32_t touch_clkgate_en              :    1;  /*touch clock enable*/
-        };
-        uint32_t val;
-    } touch_ctrl2;
-    union {
-        struct {
-            uint32_t touch_denoise_res             :    2;  /*De-noise resolution: 12/10/8/4 bit*/
-            uint32_t touch_denoise_en              :    1;  /*touch pad0 will be used to de-noise*/
-            uint32_t reserved3                     :    5;
-            uint32_t touch_inactive_connection     :    1;  /*inactive touch pads connect to 1: gnd 0: HighZ*/
-            uint32_t touch_shield_pad_en           :    1;  /*touch pad14 will be used as shield*/
-            uint32_t touch_scan_pad_map            :    15;  /*touch scan mode pad enable map*/
-            uint32_t touch_bufdrv                  :    3;  /*touch7 buffer driver strength*/
-            uint32_t touch_out_ring                :    4;  /*select out ring pad*/
-        };
-        uint32_t val;
-    } touch_scan_ctrl;
-    union {
-        struct {
-            uint32_t touch_slp_th                  :    22;  /*the threshold for sleep touch pad*/
-            uint32_t reserved22                    :    4;
-            uint32_t touch_slp_approach_en         :    1;  /*sleep pad approach function enable*/
-            uint32_t touch_slp_pad                 :    5;  /* */
-        };
-        uint32_t val;
-    } touch_slp_thres;
-    union {
-        struct {
-            uint32_t reserved0                     :    23;
-            uint32_t touch_slp_channel_clr         :    1;  /*clear touch slp channel*/
-            uint32_t touch_approach_meas_time      :    8;  /*approach pads total meas times*/
-        };
-        uint32_t val;
-    } touch_approach;
-    union {
-        struct {
-            uint32_t reserved0                     :    7;
-            uint32_t touch_bypass_neg_noise_thres  :    1;
-            uint32_t touch_bypass_noise_thres      :    1;
-            uint32_t touch_smooth_lvl              :    2;
-            uint32_t touch_jitter_step             :    4;  /*touch jitter step*/
-            uint32_t config1:               4;
-            uint32_t config2:               2;
-            uint32_t touch_noise_thres             :    2;
-            uint32_t config3:               2;
-            uint32_t touch_debounce                :    3;  /*debounce counter*/
-            uint32_t touch_filter_mode             :    3;  /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/
-            uint32_t touch_filter_en               :    1;  /*touch filter enable*/
-        };
-        uint32_t val;
-    } touch_filter_ctrl;
-    union {
-        struct {
-            uint32_t usb_vrefh                     :    2;
-            uint32_t usb_vrefl                     :    2;
-            uint32_t usb_vref_override             :    1;
-            uint32_t usb_pad_pull_override         :    1;
-            uint32_t usb_dp_pullup                 :    1;
-            uint32_t usb_dp_pulldown               :    1;
-            uint32_t usb_dm_pullup                 :    1;
-            uint32_t usb_dm_pulldown               :    1;
-            uint32_t usb_pullup_value              :    1;
-            uint32_t usb_pad_enable_override       :    1;
-            uint32_t usb_pad_enable                :    1;
-            uint32_t usb_txm                       :    1;
-            uint32_t usb_txp                       :    1;
-            uint32_t usb_tx_en                     :    1;
-            uint32_t usb_tx_en_override            :    1;
-            uint32_t usb_reset_disable             :    1;
-            uint32_t io_mux_reset_disable          :    1;
-            uint32_t sw_usb_phy_sel                :    1;
-            uint32_t sw_hw_usb_phy_sel             :    1;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } usb_conf;
-    union {
-        struct {
-            uint32_t touch_timeout_num             :    22;
-            uint32_t touch_timeout_en              :    1;
-            uint32_t reserved23                    :    9;
-        };
-        uint32_t val;
-    } touch_timeout_ctrl;
-    union {
-        struct {
-            uint32_t reject_cause                  :    18;  /*sleep reject cause*/
-            uint32_t reserved18                    :    14;
-        };
-        uint32_t val;
-    } slp_reject_cause;
-    union {
-        struct {
-            uint32_t force_download_boot           :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } option1;
-    union {
-        struct {
-            uint32_t wakeup_cause                  :    17;  /*sleep wakeup cause*/
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } slp_wakeup_cause;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;
-            uint32_t ulp_cp_timer_slp_cycle        :    24;  /*sleep cycles for ULP-coprocessor timer*/
-        };
-        uint32_t val;
-    } ulp_cp_timer_1;
-    union {
-        struct {
-            uint32_t slp_wakeup_w1ts               :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject_w1ts               :    1;  /*enable sleep reject interrupt*/
-            uint32_t sdio_idle_w1ts                :    1;  /*enable SDIO idle interrupt*/
-            uint32_t rtc_wdt_w1ts                  :    1;  /*enable RTC WDT interrupt*/
-            uint32_t rtc_touch_scan_done_w1ts      :    1;  /*enable touch scan done interrupt*/
-            uint32_t rtc_ulp_cp_w1ts               :    1;  /*enable ULP-coprocessor interrupt*/
-            uint32_t rtc_touch_done_w1ts           :    1;  /*enable touch done interrupt*/
-            uint32_t rtc_touch_active_w1ts         :    1;  /*enable touch active interrupt*/
-            uint32_t rtc_touch_inactive_w1ts       :    1;  /*enable touch inactive interrupt*/
-            uint32_t w1ts                          :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer_w1ts           :    1;  /*enable RTC main timer interrupt*/
-            uint32_t rtc_saradc1_w1ts              :    1;  /*enable saradc1 interrupt*/
-            uint32_t rtc_tsens_w1ts                :    1;  /*enable tsens interrupt*/
-            uint32_t rtc_cocpu_w1ts                :    1;  /*enable riscV cocpu interrupt*/
-            uint32_t rtc_saradc2_w1ts              :    1;  /*enable saradc2 interrupt*/
-            uint32_t rtc_swd_w1ts                  :    1;  /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead_w1ts         :    1;  /*enable xtal32k_dead  interrupt*/
-            uint32_t rtc_cocpu_trap_w1ts           :    1;  /*enable cocpu trap interrupt*/
-            uint32_t rtc_touch_timeout_w1ts        :    1;  /*enable touch timeout interrupt*/
-            uint32_t rtc_glitch_det_w1ts           :    1;  /*enbale gitch det interrupt*/
-            uint32_t rtc_touch_approach_loop_done_w1ts:    1;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } int_ena_w1ts;
-    union {
-        struct {
-            uint32_t slp_wakeup_w1tc               :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject_w1tc               :    1;  /*enable sleep reject interrupt*/
-            uint32_t sdio_idle_w1tc                :    1;  /*enable SDIO idle interrupt*/
-            uint32_t rtc_wdt_w1tc                  :    1;  /*enable RTC WDT interrupt*/
-            uint32_t rtc_touch_scan_done_w1tc      :    1;  /*enable touch scan done interrupt*/
-            uint32_t rtc_ulp_cp_w1tc               :    1;  /*enable ULP-coprocessor interrupt*/
-            uint32_t rtc_touch_done_w1tc           :    1;  /*enable touch done interrupt*/
-            uint32_t rtc_touch_active_w1tc         :    1;  /*enable touch active interrupt*/
-            uint32_t rtc_touch_inactive_w1tc       :    1;  /*enable touch inactive interrupt*/
-            uint32_t w1tc                          :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer_w1tc           :    1;  /*enable RTC main timer interrupt*/
-            uint32_t rtc_saradc1_w1tc              :    1;  /*enable saradc1 interrupt*/
-            uint32_t rtc_tsens_w1tc                :    1;  /*enable tsens interrupt*/
-            uint32_t rtc_cocpu_w1tc                :    1;  /*enable riscV cocpu interrupt*/
-            uint32_t rtc_saradc2_w1tc              :    1;  /*enable saradc2 interrupt*/
-            uint32_t rtc_swd_w1tc                  :    1;  /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead_w1tc         :    1;  /*enable xtal32k_dead  interrupt*/
-            uint32_t rtc_cocpu_trap_w1tc           :    1;  /*enable cocpu trap interrupt*/
-            uint32_t rtc_touch_timeout_w1tc        :    1;  /*enable touch timeout interrupt*/
-            uint32_t rtc_glitch_det_w1tc           :    1;  /*enbale gitch det interrupt*/
-            uint32_t rtc_touch_approach_loop_done_w1tc:    1;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } int_ena_w1tc;
-    union {
-        struct {
-            uint32_t reserved0                     :    10;
-            uint32_t retention_tag_mode            :    4;
-            uint32_t retention_target              :    2;
-            uint32_t retention_clk_sel             :    1;
-            uint32_t retention_done_wait           :    3;
-            uint32_t retention_clkoff_wait         :    4;
-            uint32_t retention_en                  :    1;
-            uint32_t retention_wait                :    7;  /*wait cycles for rention operation*/
-        };
-        uint32_t val;
-    } retention_ctrl;
-    union {
-        struct {
-            uint32_t reserved0                     :    26;
-            uint32_t power_glitch_dsense           :    2;
-            uint32_t power_glitch_force_pd         :    1;
-            uint32_t power_glitch_force_pu         :    1;
-            uint32_t power_glitch_efuse_sel        :    1;  /*select use analog fib signal*/
-            uint32_t power_glitch_en               :    1;
-        };
-        uint32_t val;
-    } pg_ctrl;
-    union {
-        struct {
-            uint32_t rtc_fib_sel                   :    3;
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } fib_sel;
-    union {
-        struct {
-            uint32_t reserved0                     :    2;
-            uint32_t touch_pad9_dac                :    3;
-            uint32_t touch_pad8_dac                :    3;
-            uint32_t touch_pad7_dac                :    3;
-            uint32_t touch_pad6_dac                :    3;
-            uint32_t touch_pad5_dac                :    3;
-            uint32_t touch_pad4_dac                :    3;
-            uint32_t touch_pad3_dac                :    3;
-            uint32_t touch_pad2_dac                :    3;
-            uint32_t touch_pad1_dac                :    3;
-            uint32_t touch_pad0_dac                :    3;
-        };
-        uint32_t val;
-    } touch_dac;
-    union {
-        struct {
-            uint32_t reserved0                     :    17;
-            uint32_t touch_pad14_dac               :    3;
-            uint32_t touch_pad13_dac               :    3;
-            uint32_t touch_pad12_dac               :    3;
-            uint32_t touch_pad11_dac               :    3;
-            uint32_t touch_pad10_dac               :    3;
-        };
-        uint32_t val;
-    } touch_dac1;
-    union {
-        struct {
-            uint32_t reserved0                     :    31;
-            uint32_t disable_rtc_cpu               :    1;
-        };
-        uint32_t val;
-    } cocpu_disable;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    union {
-        struct {
-            uint32_t date                          :    28;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } date;
-} rtc_cntl_dev_t;
-extern rtc_cntl_dev_t RTCCNTL;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_RTC_CNTL_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h b/components/soc/esp32s3/include/soc/rtc_i2c_reg.h
deleted file mode 100644
index 322f28192e2..00000000000
--- a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h
+++ /dev/null
@@ -1,873 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** RTC_I2C_SCL_LOW_REG register
- *  configure low scl period
- */
-#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_I2C_BASE + 0x0)
-/** RTC_I2C_SCL_LOW_PERIOD_REG : R/W; bitpos: [19:0]; default: 256;
- *  time period that scl =0
- */
-#define RTC_I2C_SCL_LOW_PERIOD_REG    0x000FFFFFU
-#define RTC_I2C_SCL_LOW_PERIOD_REG_M  (RTC_I2C_SCL_LOW_PERIOD_REG_V << RTC_I2C_SCL_LOW_PERIOD_REG_S)
-#define RTC_I2C_SCL_LOW_PERIOD_REG_V  0x000FFFFFU
-#define RTC_I2C_SCL_LOW_PERIOD_REG_S  0
-
-/** RTC_I2C_CTRL_REG register
- *  configure i2c ctrl
- */
-#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x4)
-/** RTC_I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
- *  1=push pull,0=open drain
- */
-#define RTC_I2C_SDA_FORCE_OUT    (BIT(0))
-#define RTC_I2C_SDA_FORCE_OUT_M  (RTC_I2C_SDA_FORCE_OUT_V << RTC_I2C_SDA_FORCE_OUT_S)
-#define RTC_I2C_SDA_FORCE_OUT_V  0x00000001U
-#define RTC_I2C_SDA_FORCE_OUT_S  0
-/** RTC_I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
- *  1=push pull,0=open drain
- */
-#define RTC_I2C_SCL_FORCE_OUT    (BIT(1))
-#define RTC_I2C_SCL_FORCE_OUT_M  (RTC_I2C_SCL_FORCE_OUT_V << RTC_I2C_SCL_FORCE_OUT_S)
-#define RTC_I2C_SCL_FORCE_OUT_V  0x00000001U
-#define RTC_I2C_SCL_FORCE_OUT_S  1
-/** RTC_I2C_MS_MODE : R/W; bitpos: [2]; default: 0;
- *  1=master,0=slave
- */
-#define RTC_I2C_MS_MODE    (BIT(2))
-#define RTC_I2C_MS_MODE_M  (RTC_I2C_MS_MODE_V << RTC_I2C_MS_MODE_S)
-#define RTC_I2C_MS_MODE_V  0x00000001U
-#define RTC_I2C_MS_MODE_S  2
-/** RTC_I2C_TRANS_START : R/W; bitpos: [3]; default: 0;
- *  force start
- */
-#define RTC_I2C_TRANS_START    (BIT(3))
-#define RTC_I2C_TRANS_START_M  (RTC_I2C_TRANS_START_V << RTC_I2C_TRANS_START_S)
-#define RTC_I2C_TRANS_START_V  0x00000001U
-#define RTC_I2C_TRANS_START_S  3
-/** RTC_I2C_TX_LSB_FIRST : R/W; bitpos: [4]; default: 0;
- *  transit lsb first
- */
-#define RTC_I2C_TX_LSB_FIRST    (BIT(4))
-#define RTC_I2C_TX_LSB_FIRST_M  (RTC_I2C_TX_LSB_FIRST_V << RTC_I2C_TX_LSB_FIRST_S)
-#define RTC_I2C_TX_LSB_FIRST_V  0x00000001U
-#define RTC_I2C_TX_LSB_FIRST_S  4
-/** RTC_I2C_RX_LSB_FIRST : R/W; bitpos: [5]; default: 0;
- *  receive lsb first
- */
-#define RTC_I2C_RX_LSB_FIRST    (BIT(5))
-#define RTC_I2C_RX_LSB_FIRST_M  (RTC_I2C_RX_LSB_FIRST_V << RTC_I2C_RX_LSB_FIRST_S)
-#define RTC_I2C_RX_LSB_FIRST_V  0x00000001U
-#define RTC_I2C_RX_LSB_FIRST_S  5
-/** RTC_I2C_I2C_CTRL_CLK_GATE_EN : R/W; bitpos: [29]; default: 0;
- *  configure i2c ctrl clk enable
- */
-#define RTC_I2C_I2C_CTRL_CLK_GATE_EN    (BIT(29))
-#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_M  (RTC_I2C_I2C_CTRL_CLK_GATE_EN_V << RTC_I2C_I2C_CTRL_CLK_GATE_EN_S)
-#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_V  0x00000001U
-#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_S  29
-/** RTC_I2C_I2C_RESET : R/W; bitpos: [30]; default: 0;
- *  rtc i2c sw reset
- */
-#define RTC_I2C_I2C_RESET    (BIT(30))
-#define RTC_I2C_I2C_RESET_M  (RTC_I2C_I2C_RESET_V << RTC_I2C_I2C_RESET_S)
-#define RTC_I2C_I2C_RESET_V  0x00000001U
-#define RTC_I2C_I2C_RESET_S  30
-/** RTC_I2C_I2CCLK_EN : R/W; bitpos: [31]; default: 0;
- *  rtc i2c reg clk gating
- */
-#define RTC_I2C_I2CCLK_EN    (BIT(31))
-#define RTC_I2C_I2CCLK_EN_M  (RTC_I2C_I2CCLK_EN_V << RTC_I2C_I2CCLK_EN_S)
-#define RTC_I2C_I2CCLK_EN_V  0x00000001U
-#define RTC_I2C_I2CCLK_EN_S  31
-
-/** RTC_I2C_STATUS_REG register
- *  get i2c status
- */
-#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x8)
-/** RTC_I2C_ACK_REC : RO; bitpos: [0]; default: 0;
- *  ack response
- */
-#define RTC_I2C_ACK_REC    (BIT(0))
-#define RTC_I2C_ACK_REC_M  (RTC_I2C_ACK_REC_V << RTC_I2C_ACK_REC_S)
-#define RTC_I2C_ACK_REC_V  0x00000001U
-#define RTC_I2C_ACK_REC_S  0
-/** RTC_I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
- *  slave read or write
- */
-#define RTC_I2C_SLAVE_RW    (BIT(1))
-#define RTC_I2C_SLAVE_RW_M  (RTC_I2C_SLAVE_RW_V << RTC_I2C_SLAVE_RW_S)
-#define RTC_I2C_SLAVE_RW_V  0x00000001U
-#define RTC_I2C_SLAVE_RW_S  1
-/** RTC_I2C_ARB_LOST : RO; bitpos: [2]; default: 0;
- *  arbitration is lost
- */
-#define RTC_I2C_ARB_LOST    (BIT(2))
-#define RTC_I2C_ARB_LOST_M  (RTC_I2C_ARB_LOST_V << RTC_I2C_ARB_LOST_S)
-#define RTC_I2C_ARB_LOST_V  0x00000001U
-#define RTC_I2C_ARB_LOST_S  2
-/** RTC_I2C_BUS_BUSY : RO; bitpos: [3]; default: 0;
- *  bus is busy
- */
-#define RTC_I2C_BUS_BUSY    (BIT(3))
-#define RTC_I2C_BUS_BUSY_M  (RTC_I2C_BUS_BUSY_V << RTC_I2C_BUS_BUSY_S)
-#define RTC_I2C_BUS_BUSY_V  0x00000001U
-#define RTC_I2C_BUS_BUSY_S  3
-/** RTC_I2C_SLAVE_ADDRESSED : RO; bitpos: [4]; default: 0;
- *  slave reg sub address
- */
-#define RTC_I2C_SLAVE_ADDRESSED    (BIT(4))
-#define RTC_I2C_SLAVE_ADDRESSED_M  (RTC_I2C_SLAVE_ADDRESSED_V << RTC_I2C_SLAVE_ADDRESSED_S)
-#define RTC_I2C_SLAVE_ADDRESSED_V  0x00000001U
-#define RTC_I2C_SLAVE_ADDRESSED_S  4
-/** RTC_I2C_BYTE_TRANS : RO; bitpos: [5]; default: 0;
- *  One byte transit done
- */
-#define RTC_I2C_BYTE_TRANS    (BIT(5))
-#define RTC_I2C_BYTE_TRANS_M  (RTC_I2C_BYTE_TRANS_V << RTC_I2C_BYTE_TRANS_S)
-#define RTC_I2C_BYTE_TRANS_V  0x00000001U
-#define RTC_I2C_BYTE_TRANS_S  5
-/** RTC_I2C_OP_CNT : RO; bitpos: [7:6]; default: 0;
- *  which operation is working
- */
-#define RTC_I2C_OP_CNT    0x00000003U
-#define RTC_I2C_OP_CNT_M  (RTC_I2C_OP_CNT_V << RTC_I2C_OP_CNT_S)
-#define RTC_I2C_OP_CNT_V  0x00000003U
-#define RTC_I2C_OP_CNT_S  6
-/** RTC_I2C_SHIFT_REG : RO; bitpos: [23:16]; default: 0;
- *  shifter content
- */
-#define RTC_I2C_SHIFT_REG    0x000000FFU
-#define RTC_I2C_SHIFT_REG_M  (RTC_I2C_SHIFT_REG_V << RTC_I2C_SHIFT_REG_S)
-#define RTC_I2C_SHIFT_REG_V  0x000000FFU
-#define RTC_I2C_SHIFT_REG_S  16
-/** RTC_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
- *  i2c last main status
- */
-#define RTC_I2C_SCL_MAIN_STATE_LAST    0x00000007U
-#define RTC_I2C_SCL_MAIN_STATE_LAST_M  (RTC_I2C_SCL_MAIN_STATE_LAST_V << RTC_I2C_SCL_MAIN_STATE_LAST_S)
-#define RTC_I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
-#define RTC_I2C_SCL_MAIN_STATE_LAST_S  24
-/** RTC_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
- *  scl last status
- */
-#define RTC_I2C_SCL_STATE_LAST    0x00000007U
-#define RTC_I2C_SCL_STATE_LAST_M  (RTC_I2C_SCL_STATE_LAST_V << RTC_I2C_SCL_STATE_LAST_S)
-#define RTC_I2C_SCL_STATE_LAST_V  0x00000007U
-#define RTC_I2C_SCL_STATE_LAST_S  28
-
-/** RTC_I2C_TO_REG register
- *  configure time out
- */
-#define RTC_I2C_TO_REG (DR_REG_RTC_I2C_BASE + 0xc)
-/** RTC_I2C_TIME_OUT_REG : R/W; bitpos: [19:0]; default: 65536;
- *  time out threshold
- */
-#define RTC_I2C_TIME_OUT_REG    0x000FFFFFU
-#define RTC_I2C_TIME_OUT_REG_M  (RTC_I2C_TIME_OUT_REG_V << RTC_I2C_TIME_OUT_REG_S)
-#define RTC_I2C_TIME_OUT_REG_V  0x000FFFFFU
-#define RTC_I2C_TIME_OUT_REG_S  0
-
-/** RTC_I2C_SLAVE_ADDR_REG register
- *  configure slave id
- */
-#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x10)
-/** RTC_I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
- *  slave address
- */
-#define RTC_I2C_SLAVE_ADDR    0x00007FFFU
-#define RTC_I2C_SLAVE_ADDR_M  (RTC_I2C_SLAVE_ADDR_V << RTC_I2C_SLAVE_ADDR_S)
-#define RTC_I2C_SLAVE_ADDR_V  0x00007FFFU
-#define RTC_I2C_SLAVE_ADDR_S  0
-/** RTC_I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
- *  i2c 10bit mode enable
- */
-#define RTC_I2C_ADDR_10BIT_EN    (BIT(31))
-#define RTC_I2C_ADDR_10BIT_EN_M  (RTC_I2C_ADDR_10BIT_EN_V << RTC_I2C_ADDR_10BIT_EN_S)
-#define RTC_I2C_ADDR_10BIT_EN_V  0x00000001U
-#define RTC_I2C_ADDR_10BIT_EN_S  31
-
-/** RTC_I2C_SCL_HIGH_REG register
- *  configure high scl period
- */
-#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x14)
-/** RTC_I2C_SCL_HIGH_PERIOD_REG : R/W; bitpos: [19:0]; default: 256;
- *  time period that scl = 1
- */
-#define RTC_I2C_SCL_HIGH_PERIOD_REG    0x000FFFFFU
-#define RTC_I2C_SCL_HIGH_PERIOD_REG_M  (RTC_I2C_SCL_HIGH_PERIOD_REG_V << RTC_I2C_SCL_HIGH_PERIOD_REG_S)
-#define RTC_I2C_SCL_HIGH_PERIOD_REG_V  0x000FFFFFU
-#define RTC_I2C_SCL_HIGH_PERIOD_REG_S  0
-
-/** RTC_I2C_SDA_DUTY_REG register
- *  configure sda duty
- */
-#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x18)
-/** RTC_I2C_SDA_DUTY_NUM : R/W; bitpos: [19:0]; default: 16;
- *  time period for SDA to toggle after SCL goes low
- */
-#define RTC_I2C_SDA_DUTY_NUM    0x000FFFFFU
-#define RTC_I2C_SDA_DUTY_NUM_M  (RTC_I2C_SDA_DUTY_NUM_V << RTC_I2C_SDA_DUTY_NUM_S)
-#define RTC_I2C_SDA_DUTY_NUM_V  0x000FFFFFU
-#define RTC_I2C_SDA_DUTY_NUM_S  0
-
-/** RTC_I2C_SCL_START_PERIOD_REG register
- *  configure scl start period
- */
-#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x1c)
-/** RTC_I2C_SCL_START_PERIOD : R/W; bitpos: [19:0]; default: 8;
- *  time period for SCL to toggle after I2C start is triggered
- */
-#define RTC_I2C_SCL_START_PERIOD    0x000FFFFFU
-#define RTC_I2C_SCL_START_PERIOD_M  (RTC_I2C_SCL_START_PERIOD_V << RTC_I2C_SCL_START_PERIOD_S)
-#define RTC_I2C_SCL_START_PERIOD_V  0x000FFFFFU
-#define RTC_I2C_SCL_START_PERIOD_S  0
-
-/** RTC_I2C_SCL_STOP_PERIOD_REG register
- *  configure scl stop period
- */
-#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x20)
-/** RTC_I2C_SCL_STOP_PERIOD : R/W; bitpos: [19:0]; default: 8;
- *  time period for SCL to stop after I2C end is triggered
- */
-#define RTC_I2C_SCL_STOP_PERIOD    0x000FFFFFU
-#define RTC_I2C_SCL_STOP_PERIOD_M  (RTC_I2C_SCL_STOP_PERIOD_V << RTC_I2C_SCL_STOP_PERIOD_S)
-#define RTC_I2C_SCL_STOP_PERIOD_V  0x000FFFFFU
-#define RTC_I2C_SCL_STOP_PERIOD_S  0
-
-/** RTC_I2C_INT_CLR_REG register
- *  interrupt clear register
- */
-#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x24)
-/** RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO; bitpos: [0]; default: 0;
- *  clear slave transit complete interrupt
- */
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR    (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M  (RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V << RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S)
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x00000001U
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S  0
-/** RTC_I2C_ARBITRATION_LOST_INT_CLR : WO; bitpos: [1]; default: 0;
- *  clear arbitration lost interrupt
- */
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR    (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M  (RTC_I2C_ARBITRATION_LOST_INT_CLR_V << RTC_I2C_ARBITRATION_LOST_INT_CLR_S)
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
-#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S  1
-/** RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO; bitpos: [2]; default: 0;
- *  clear master transit complete interrupt
- */
-#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR    (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M  (RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V << RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S)
-#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V  0x00000001U
-#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S  2
-/** RTC_I2C_TRANS_COMPLETE_INT_CLR : WO; bitpos: [3]; default: 0;
- *  clear transit complete interrupt
- */
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR    (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M  (RTC_I2C_TRANS_COMPLETE_INT_CLR_V << RTC_I2C_TRANS_COMPLETE_INT_CLR_S)
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
-#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S  3
-/** RTC_I2C_TIME_OUT_INT_CLR : WO; bitpos: [4]; default: 0;
- *  clear time out interrupt
- */
-#define RTC_I2C_TIME_OUT_INT_CLR    (BIT(4))
-#define RTC_I2C_TIME_OUT_INT_CLR_M  (RTC_I2C_TIME_OUT_INT_CLR_V << RTC_I2C_TIME_OUT_INT_CLR_S)
-#define RTC_I2C_TIME_OUT_INT_CLR_V  0x00000001U
-#define RTC_I2C_TIME_OUT_INT_CLR_S  4
-/** RTC_I2C_ACK_ERR_INT_CLR : WO; bitpos: [5]; default: 0;
- *  clear ack error interrupt
- */
-#define RTC_I2C_ACK_ERR_INT_CLR    (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_CLR_M  (RTC_I2C_ACK_ERR_INT_CLR_V << RTC_I2C_ACK_ERR_INT_CLR_S)
-#define RTC_I2C_ACK_ERR_INT_CLR_V  0x00000001U
-#define RTC_I2C_ACK_ERR_INT_CLR_S  5
-/** RTC_I2C_RX_DATA_INT_CLR : WO; bitpos: [6]; default: 0;
- *  clear receive data interrupt
- */
-#define RTC_I2C_RX_DATA_INT_CLR    (BIT(6))
-#define RTC_I2C_RX_DATA_INT_CLR_M  (RTC_I2C_RX_DATA_INT_CLR_V << RTC_I2C_RX_DATA_INT_CLR_S)
-#define RTC_I2C_RX_DATA_INT_CLR_V  0x00000001U
-#define RTC_I2C_RX_DATA_INT_CLR_S  6
-/** RTC_I2C_TX_DATA_INT_CLR : WO; bitpos: [7]; default: 0;
- *  clear transit load data complete interrupt
- */
-#define RTC_I2C_TX_DATA_INT_CLR    (BIT(7))
-#define RTC_I2C_TX_DATA_INT_CLR_M  (RTC_I2C_TX_DATA_INT_CLR_V << RTC_I2C_TX_DATA_INT_CLR_S)
-#define RTC_I2C_TX_DATA_INT_CLR_V  0x00000001U
-#define RTC_I2C_TX_DATA_INT_CLR_S  7
-/** RTC_I2C_DETECT_START_INT_CLR : WO; bitpos: [8]; default: 0;
- *  clear detect start interrupt
- */
-#define RTC_I2C_DETECT_START_INT_CLR    (BIT(8))
-#define RTC_I2C_DETECT_START_INT_CLR_M  (RTC_I2C_DETECT_START_INT_CLR_V << RTC_I2C_DETECT_START_INT_CLR_S)
-#define RTC_I2C_DETECT_START_INT_CLR_V  0x00000001U
-#define RTC_I2C_DETECT_START_INT_CLR_S  8
-
-/** RTC_I2C_INT_RAW_REG register
- *  interrupt raw register
- */
-#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x28)
-/** RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO; bitpos: [0]; default: 0;
- *  slave transit complete interrupt raw
- */
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW    (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M  (RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V << RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S)
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x00000001U
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S  0
-/** RTC_I2C_ARBITRATION_LOST_INT_RAW : RO; bitpos: [1]; default: 0;
- *  arbitration lost interrupt raw
- */
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW    (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M  (RTC_I2C_ARBITRATION_LOST_INT_RAW_V << RTC_I2C_ARBITRATION_LOST_INT_RAW_S)
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
-#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S  1
-/** RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO; bitpos: [2]; default: 0;
- *  master transit complete interrupt raw
- */
-#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW    (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M  (RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V << RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S)
-#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V  0x00000001U
-#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S  2
-/** RTC_I2C_TRANS_COMPLETE_INT_RAW : RO; bitpos: [3]; default: 0;
- *  transit complete interrupt raw
- */
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW    (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M  (RTC_I2C_TRANS_COMPLETE_INT_RAW_V << RTC_I2C_TRANS_COMPLETE_INT_RAW_S)
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
-#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S  3
-/** RTC_I2C_TIME_OUT_INT_RAW : RO; bitpos: [4]; default: 0;
- *  time out interrupt raw
- */
-#define RTC_I2C_TIME_OUT_INT_RAW    (BIT(4))
-#define RTC_I2C_TIME_OUT_INT_RAW_M  (RTC_I2C_TIME_OUT_INT_RAW_V << RTC_I2C_TIME_OUT_INT_RAW_S)
-#define RTC_I2C_TIME_OUT_INT_RAW_V  0x00000001U
-#define RTC_I2C_TIME_OUT_INT_RAW_S  4
-/** RTC_I2C_ACK_ERR_INT_RAW : RO; bitpos: [5]; default: 0;
- *  ack error interrupt raw
- */
-#define RTC_I2C_ACK_ERR_INT_RAW    (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_RAW_M  (RTC_I2C_ACK_ERR_INT_RAW_V << RTC_I2C_ACK_ERR_INT_RAW_S)
-#define RTC_I2C_ACK_ERR_INT_RAW_V  0x00000001U
-#define RTC_I2C_ACK_ERR_INT_RAW_S  5
-/** RTC_I2C_RX_DATA_INT_RAW : RO; bitpos: [6]; default: 0;
- *  receive data interrupt raw
- */
-#define RTC_I2C_RX_DATA_INT_RAW    (BIT(6))
-#define RTC_I2C_RX_DATA_INT_RAW_M  (RTC_I2C_RX_DATA_INT_RAW_V << RTC_I2C_RX_DATA_INT_RAW_S)
-#define RTC_I2C_RX_DATA_INT_RAW_V  0x00000001U
-#define RTC_I2C_RX_DATA_INT_RAW_S  6
-/** RTC_I2C_TX_DATA_INT_RAW : RO; bitpos: [7]; default: 0;
- *  transit data interrupt raw
- */
-#define RTC_I2C_TX_DATA_INT_RAW    (BIT(7))
-#define RTC_I2C_TX_DATA_INT_RAW_M  (RTC_I2C_TX_DATA_INT_RAW_V << RTC_I2C_TX_DATA_INT_RAW_S)
-#define RTC_I2C_TX_DATA_INT_RAW_V  0x00000001U
-#define RTC_I2C_TX_DATA_INT_RAW_S  7
-/** RTC_I2C_DETECT_START_INT_RAW : RO; bitpos: [8]; default: 0;
- *  detect start interrupt raw
- */
-#define RTC_I2C_DETECT_START_INT_RAW    (BIT(8))
-#define RTC_I2C_DETECT_START_INT_RAW_M  (RTC_I2C_DETECT_START_INT_RAW_V << RTC_I2C_DETECT_START_INT_RAW_S)
-#define RTC_I2C_DETECT_START_INT_RAW_V  0x00000001U
-#define RTC_I2C_DETECT_START_INT_RAW_S  8
-
-/** RTC_I2C_INT_ST_REG register
- *  interrupt state register
- */
-#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x2c)
-/** RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO; bitpos: [0]; default: 0;
- *  slave transit complete interrupt state
- */
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST    (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M  (RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V << RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S)
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V  0x00000001U
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S  0
-/** RTC_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [1]; default: 0;
- *  arbitration lost interrupt state
- */
-#define RTC_I2C_ARBITRATION_LOST_INT_ST    (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_ST_M  (RTC_I2C_ARBITRATION_LOST_INT_ST_V << RTC_I2C_ARBITRATION_LOST_INT_ST_S)
-#define RTC_I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
-#define RTC_I2C_ARBITRATION_LOST_INT_ST_S  1
-/** RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO; bitpos: [2]; default: 0;
- *  master transit complete interrupt state
- */
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ST    (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M  (RTC_I2C_MASTER_TRAN_COMP_INT_ST_V << RTC_I2C_MASTER_TRAN_COMP_INT_ST_S)
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V  0x00000001U
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S  2
-/** RTC_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [3]; default: 0;
- *  transit complete interrupt state
- */
-#define RTC_I2C_TRANS_COMPLETE_INT_ST    (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_ST_M  (RTC_I2C_TRANS_COMPLETE_INT_ST_V << RTC_I2C_TRANS_COMPLETE_INT_ST_S)
-#define RTC_I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
-#define RTC_I2C_TRANS_COMPLETE_INT_ST_S  3
-/** RTC_I2C_TIME_OUT_INT_ST : RO; bitpos: [4]; default: 0;
- *  time out interrupt state
- */
-#define RTC_I2C_TIME_OUT_INT_ST    (BIT(4))
-#define RTC_I2C_TIME_OUT_INT_ST_M  (RTC_I2C_TIME_OUT_INT_ST_V << RTC_I2C_TIME_OUT_INT_ST_S)
-#define RTC_I2C_TIME_OUT_INT_ST_V  0x00000001U
-#define RTC_I2C_TIME_OUT_INT_ST_S  4
-/** RTC_I2C_ACK_ERR_INT_ST : RO; bitpos: [5]; default: 0;
- *  ack error interrupt state
- */
-#define RTC_I2C_ACK_ERR_INT_ST    (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_ST_M  (RTC_I2C_ACK_ERR_INT_ST_V << RTC_I2C_ACK_ERR_INT_ST_S)
-#define RTC_I2C_ACK_ERR_INT_ST_V  0x00000001U
-#define RTC_I2C_ACK_ERR_INT_ST_S  5
-/** RTC_I2C_RX_DATA_INT_ST : RO; bitpos: [6]; default: 0;
- *  receive data interrupt state
- */
-#define RTC_I2C_RX_DATA_INT_ST    (BIT(6))
-#define RTC_I2C_RX_DATA_INT_ST_M  (RTC_I2C_RX_DATA_INT_ST_V << RTC_I2C_RX_DATA_INT_ST_S)
-#define RTC_I2C_RX_DATA_INT_ST_V  0x00000001U
-#define RTC_I2C_RX_DATA_INT_ST_S  6
-/** RTC_I2C_TX_DATA_INT_ST : RO; bitpos: [7]; default: 0;
- *  transit data interrupt state
- */
-#define RTC_I2C_TX_DATA_INT_ST    (BIT(7))
-#define RTC_I2C_TX_DATA_INT_ST_M  (RTC_I2C_TX_DATA_INT_ST_V << RTC_I2C_TX_DATA_INT_ST_S)
-#define RTC_I2C_TX_DATA_INT_ST_V  0x00000001U
-#define RTC_I2C_TX_DATA_INT_ST_S  7
-/** RTC_I2C_DETECT_START_INT_ST : RO; bitpos: [8]; default: 0;
- *  detect start interrupt state
- */
-#define RTC_I2C_DETECT_START_INT_ST    (BIT(8))
-#define RTC_I2C_DETECT_START_INT_ST_M  (RTC_I2C_DETECT_START_INT_ST_V << RTC_I2C_DETECT_START_INT_ST_S)
-#define RTC_I2C_DETECT_START_INT_ST_V  0x00000001U
-#define RTC_I2C_DETECT_START_INT_ST_S  8
-
-/** RTC_I2C_INT_ENA_REG register
- *  interrupt enable register
- */
-#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x30)
-/** RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  enable slave transit complete interrupt
- */
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA    (BIT(0))
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M  (RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V << RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S)
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x00000001U
-#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S  0
-/** RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  enable arbitration lost interrupt
- */
-#define RTC_I2C_ARBITRATION_LOST_INT_ENA    (BIT(1))
-#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M  (RTC_I2C_ARBITRATION_LOST_INT_ENA_V << RTC_I2C_ARBITRATION_LOST_INT_ENA_S)
-#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
-#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S  1
-/** RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  enable master transit complete interrupt
- */
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA    (BIT(2))
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M  (RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V << RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S)
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V  0x00000001U
-#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S  2
-/** RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  enable transit complete interrupt
- */
-#define RTC_I2C_TRANS_COMPLETE_INT_ENA    (BIT(3))
-#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M  (RTC_I2C_TRANS_COMPLETE_INT_ENA_V << RTC_I2C_TRANS_COMPLETE_INT_ENA_S)
-#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
-#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S  3
-/** RTC_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  enable time out interrupt
- */
-#define RTC_I2C_TIME_OUT_INT_ENA    (BIT(4))
-#define RTC_I2C_TIME_OUT_INT_ENA_M  (RTC_I2C_TIME_OUT_INT_ENA_V << RTC_I2C_TIME_OUT_INT_ENA_S)
-#define RTC_I2C_TIME_OUT_INT_ENA_V  0x00000001U
-#define RTC_I2C_TIME_OUT_INT_ENA_S  4
-/** RTC_I2C_ACK_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  enable eack error interrupt
- */
-#define RTC_I2C_ACK_ERR_INT_ENA    (BIT(5))
-#define RTC_I2C_ACK_ERR_INT_ENA_M  (RTC_I2C_ACK_ERR_INT_ENA_V << RTC_I2C_ACK_ERR_INT_ENA_S)
-#define RTC_I2C_ACK_ERR_INT_ENA_V  0x00000001U
-#define RTC_I2C_ACK_ERR_INT_ENA_S  5
-/** RTC_I2C_RX_DATA_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  enable receive data interrupt
- */
-#define RTC_I2C_RX_DATA_INT_ENA    (BIT(6))
-#define RTC_I2C_RX_DATA_INT_ENA_M  (RTC_I2C_RX_DATA_INT_ENA_V << RTC_I2C_RX_DATA_INT_ENA_S)
-#define RTC_I2C_RX_DATA_INT_ENA_V  0x00000001U
-#define RTC_I2C_RX_DATA_INT_ENA_S  6
-/** RTC_I2C_TX_DATA_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  enable transit data interrupt
- */
-#define RTC_I2C_TX_DATA_INT_ENA    (BIT(7))
-#define RTC_I2C_TX_DATA_INT_ENA_M  (RTC_I2C_TX_DATA_INT_ENA_V << RTC_I2C_TX_DATA_INT_ENA_S)
-#define RTC_I2C_TX_DATA_INT_ENA_V  0x00000001U
-#define RTC_I2C_TX_DATA_INT_ENA_S  7
-/** RTC_I2C_DETECT_START_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  enable detect start interrupt
- */
-#define RTC_I2C_DETECT_START_INT_ENA    (BIT(8))
-#define RTC_I2C_DETECT_START_INT_ENA_M  (RTC_I2C_DETECT_START_INT_ENA_V << RTC_I2C_DETECT_START_INT_ENA_S)
-#define RTC_I2C_DETECT_START_INT_ENA_V  0x00000001U
-#define RTC_I2C_DETECT_START_INT_ENA_S  8
-
-/** RTC_I2C_DATA_REG register
- *  get i2c data status
- */
-#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x34)
-/** RTC_I2C_I2C_RDATA : RO; bitpos: [7:0]; default: 0;
- *  data received
- */
-#define RTC_I2C_I2C_RDATA    0x000000FFU
-#define RTC_I2C_I2C_RDATA_M  (RTC_I2C_I2C_RDATA_V << RTC_I2C_I2C_RDATA_S)
-#define RTC_I2C_I2C_RDATA_V  0x000000FFU
-#define RTC_I2C_I2C_RDATA_S  0
-/** RTC_I2C_SLAVE_TX_DATA : R/W; bitpos: [15:8]; default: 0;
- *  data sent by slave
- */
-#define RTC_I2C_SLAVE_TX_DATA    0x000000FFU
-#define RTC_I2C_SLAVE_TX_DATA_M  (RTC_I2C_SLAVE_TX_DATA_V << RTC_I2C_SLAVE_TX_DATA_S)
-#define RTC_I2C_SLAVE_TX_DATA_V  0x000000FFU
-#define RTC_I2C_SLAVE_TX_DATA_S  8
-/** RTC_I2C_I2C_DONE : RO; bitpos: [31]; default: 0;
- *  i2c done
- */
-#define RTC_I2C_I2C_DONE    (BIT(31))
-#define RTC_I2C_I2C_DONE_M  (RTC_I2C_I2C_DONE_V << RTC_I2C_I2C_DONE_S)
-#define RTC_I2C_I2C_DONE_V  0x00000001U
-#define RTC_I2C_I2C_DONE_S  31
-
-/** RTC_I2C_CMD0_REG register
- *  i2c commond0 register
- */
-#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x38)
-/** RTC_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 2307;
- *  command0
- */
-#define RTC_I2C_COMMAND0    0x00003FFFU
-#define RTC_I2C_COMMAND0_M  (RTC_I2C_COMMAND0_V << RTC_I2C_COMMAND0_S)
-#define RTC_I2C_COMMAND0_V  0x00003FFFU
-#define RTC_I2C_COMMAND0_S  0
-/** RTC_I2C_COMMAND0_DONE : RO; bitpos: [31]; default: 0;
- *  command0_done
- */
-#define RTC_I2C_COMMAND0_DONE    (BIT(31))
-#define RTC_I2C_COMMAND0_DONE_M  (RTC_I2C_COMMAND0_DONE_V << RTC_I2C_COMMAND0_DONE_S)
-#define RTC_I2C_COMMAND0_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND0_DONE_S  31
-
-/** RTC_I2C_CMD1_REG register
- *  i2c commond1 register
- */
-#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x3c)
-/** RTC_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 6401;
- *  command1
- */
-#define RTC_I2C_COMMAND1    0x00003FFFU
-#define RTC_I2C_COMMAND1_M  (RTC_I2C_COMMAND1_V << RTC_I2C_COMMAND1_S)
-#define RTC_I2C_COMMAND1_V  0x00003FFFU
-#define RTC_I2C_COMMAND1_S  0
-/** RTC_I2C_COMMAND1_DONE : RO; bitpos: [31]; default: 0;
- *  command1_done
- */
-#define RTC_I2C_COMMAND1_DONE    (BIT(31))
-#define RTC_I2C_COMMAND1_DONE_M  (RTC_I2C_COMMAND1_DONE_V << RTC_I2C_COMMAND1_DONE_S)
-#define RTC_I2C_COMMAND1_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND1_DONE_S  31
-
-/** RTC_I2C_CMD2_REG register
- *  i2c commond2 register
- */
-#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x40)
-/** RTC_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 2306;
- *  command2
- */
-#define RTC_I2C_COMMAND2    0x00003FFFU
-#define RTC_I2C_COMMAND2_M  (RTC_I2C_COMMAND2_V << RTC_I2C_COMMAND2_S)
-#define RTC_I2C_COMMAND2_V  0x00003FFFU
-#define RTC_I2C_COMMAND2_S  0
-/** RTC_I2C_COMMAND2_DONE : RO; bitpos: [31]; default: 0;
- *  command2_done
- */
-#define RTC_I2C_COMMAND2_DONE    (BIT(31))
-#define RTC_I2C_COMMAND2_DONE_M  (RTC_I2C_COMMAND2_DONE_V << RTC_I2C_COMMAND2_DONE_S)
-#define RTC_I2C_COMMAND2_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND2_DONE_S  31
-
-/** RTC_I2C_CMD3_REG register
- *  i2c commond3 register
- */
-#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x44)
-/** RTC_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 257;
- *  command3
- */
-#define RTC_I2C_COMMAND3    0x00003FFFU
-#define RTC_I2C_COMMAND3_M  (RTC_I2C_COMMAND3_V << RTC_I2C_COMMAND3_S)
-#define RTC_I2C_COMMAND3_V  0x00003FFFU
-#define RTC_I2C_COMMAND3_S  0
-/** RTC_I2C_COMMAND3_DONE : RO; bitpos: [31]; default: 0;
- *  command3_done
- */
-#define RTC_I2C_COMMAND3_DONE    (BIT(31))
-#define RTC_I2C_COMMAND3_DONE_M  (RTC_I2C_COMMAND3_DONE_V << RTC_I2C_COMMAND3_DONE_S)
-#define RTC_I2C_COMMAND3_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND3_DONE_S  31
-
-/** RTC_I2C_CMD4_REG register
- *  i2c commond4 register
- */
-#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x48)
-/** RTC_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 2305;
- *  command4
- */
-#define RTC_I2C_COMMAND4    0x00003FFFU
-#define RTC_I2C_COMMAND4_M  (RTC_I2C_COMMAND4_V << RTC_I2C_COMMAND4_S)
-#define RTC_I2C_COMMAND4_V  0x00003FFFU
-#define RTC_I2C_COMMAND4_S  0
-/** RTC_I2C_COMMAND4_DONE : RO; bitpos: [31]; default: 0;
- *  command4_done
- */
-#define RTC_I2C_COMMAND4_DONE    (BIT(31))
-#define RTC_I2C_COMMAND4_DONE_M  (RTC_I2C_COMMAND4_DONE_V << RTC_I2C_COMMAND4_DONE_S)
-#define RTC_I2C_COMMAND4_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND4_DONE_S  31
-
-/** RTC_I2C_CMD5_REG register
- *  i2c commond5_register
- */
-#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x4c)
-/** RTC_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 5889;
- *  command5
- */
-#define RTC_I2C_COMMAND5    0x00003FFFU
-#define RTC_I2C_COMMAND5_M  (RTC_I2C_COMMAND5_V << RTC_I2C_COMMAND5_S)
-#define RTC_I2C_COMMAND5_V  0x00003FFFU
-#define RTC_I2C_COMMAND5_S  0
-/** RTC_I2C_COMMAND5_DONE : RO; bitpos: [31]; default: 0;
- *  command5_done
- */
-#define RTC_I2C_COMMAND5_DONE    (BIT(31))
-#define RTC_I2C_COMMAND5_DONE_M  (RTC_I2C_COMMAND5_DONE_V << RTC_I2C_COMMAND5_DONE_S)
-#define RTC_I2C_COMMAND5_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND5_DONE_S  31
-
-/** RTC_I2C_CMD6_REG register
- *  i2c commond6 register
- */
-#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x50)
-/** RTC_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 6401;
- *  command6
- */
-#define RTC_I2C_COMMAND6    0x00003FFFU
-#define RTC_I2C_COMMAND6_M  (RTC_I2C_COMMAND6_V << RTC_I2C_COMMAND6_S)
-#define RTC_I2C_COMMAND6_V  0x00003FFFU
-#define RTC_I2C_COMMAND6_S  0
-/** RTC_I2C_COMMAND6_DONE : RO; bitpos: [31]; default: 0;
- *  command6_done
- */
-#define RTC_I2C_COMMAND6_DONE    (BIT(31))
-#define RTC_I2C_COMMAND6_DONE_M  (RTC_I2C_COMMAND6_DONE_V << RTC_I2C_COMMAND6_DONE_S)
-#define RTC_I2C_COMMAND6_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND6_DONE_S  31
-
-/** RTC_I2C_CMD7_REG register
- *  i2c commond7 register
- */
-#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x54)
-/** RTC_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 2308;
- *  command7
- */
-#define RTC_I2C_COMMAND7    0x00003FFFU
-#define RTC_I2C_COMMAND7_M  (RTC_I2C_COMMAND7_V << RTC_I2C_COMMAND7_S)
-#define RTC_I2C_COMMAND7_V  0x00003FFFU
-#define RTC_I2C_COMMAND7_S  0
-/** RTC_I2C_COMMAND7_DONE : RO; bitpos: [31]; default: 0;
- *  command7_done
- */
-#define RTC_I2C_COMMAND7_DONE    (BIT(31))
-#define RTC_I2C_COMMAND7_DONE_M  (RTC_I2C_COMMAND7_DONE_V << RTC_I2C_COMMAND7_DONE_S)
-#define RTC_I2C_COMMAND7_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND7_DONE_S  31
-
-/** RTC_I2C_CMD8_REG register
- *  i2c commond8 register
- */
-#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x58)
-/** RTC_I2C_COMMAND8 : R/W; bitpos: [13:0]; default: 6401;
- *  command8
- */
-#define RTC_I2C_COMMAND8    0x00003FFFU
-#define RTC_I2C_COMMAND8_M  (RTC_I2C_COMMAND8_V << RTC_I2C_COMMAND8_S)
-#define RTC_I2C_COMMAND8_V  0x00003FFFU
-#define RTC_I2C_COMMAND8_S  0
-/** RTC_I2C_COMMAND8_DONE : RO; bitpos: [31]; default: 0;
- *  command8_done
- */
-#define RTC_I2C_COMMAND8_DONE    (BIT(31))
-#define RTC_I2C_COMMAND8_DONE_M  (RTC_I2C_COMMAND8_DONE_V << RTC_I2C_COMMAND8_DONE_S)
-#define RTC_I2C_COMMAND8_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND8_DONE_S  31
-
-/** RTC_I2C_CMD9_REG register
- *  i2c commond9 register
- */
-#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x5c)
-/** RTC_I2C_COMMAND9 : R/W; bitpos: [13:0]; default: 2307;
- *  command9
- */
-#define RTC_I2C_COMMAND9    0x00003FFFU
-#define RTC_I2C_COMMAND9_M  (RTC_I2C_COMMAND9_V << RTC_I2C_COMMAND9_S)
-#define RTC_I2C_COMMAND9_V  0x00003FFFU
-#define RTC_I2C_COMMAND9_S  0
-/** RTC_I2C_COMMAND9_DONE : RO; bitpos: [31]; default: 0;
- *  command9_done
- */
-#define RTC_I2C_COMMAND9_DONE    (BIT(31))
-#define RTC_I2C_COMMAND9_DONE_M  (RTC_I2C_COMMAND9_DONE_V << RTC_I2C_COMMAND9_DONE_S)
-#define RTC_I2C_COMMAND9_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND9_DONE_S  31
-
-/** RTC_I2C_CMD10_REG register
- *  i2c commond10 register
- */
-#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x60)
-/** RTC_I2C_COMMAND10 : R/W; bitpos: [13:0]; default: 257;
- *  command10
- */
-#define RTC_I2C_COMMAND10    0x00003FFFU
-#define RTC_I2C_COMMAND10_M  (RTC_I2C_COMMAND10_V << RTC_I2C_COMMAND10_S)
-#define RTC_I2C_COMMAND10_V  0x00003FFFU
-#define RTC_I2C_COMMAND10_S  0
-/** RTC_I2C_COMMAND10_DONE : RO; bitpos: [31]; default: 0;
- *  command10_done
- */
-#define RTC_I2C_COMMAND10_DONE    (BIT(31))
-#define RTC_I2C_COMMAND10_DONE_M  (RTC_I2C_COMMAND10_DONE_V << RTC_I2C_COMMAND10_DONE_S)
-#define RTC_I2C_COMMAND10_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND10_DONE_S  31
-
-/** RTC_I2C_CMD11_REG register
- *  i2c commond11 register
- */
-#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x64)
-/** RTC_I2C_COMMAND11 : R/W; bitpos: [13:0]; default: 2305;
- *  command11
- */
-#define RTC_I2C_COMMAND11    0x00003FFFU
-#define RTC_I2C_COMMAND11_M  (RTC_I2C_COMMAND11_V << RTC_I2C_COMMAND11_S)
-#define RTC_I2C_COMMAND11_V  0x00003FFFU
-#define RTC_I2C_COMMAND11_S  0
-/** RTC_I2C_COMMAND11_DONE : RO; bitpos: [31]; default: 0;
- *  command11_done
- */
-#define RTC_I2C_COMMAND11_DONE    (BIT(31))
-#define RTC_I2C_COMMAND11_DONE_M  (RTC_I2C_COMMAND11_DONE_V << RTC_I2C_COMMAND11_DONE_S)
-#define RTC_I2C_COMMAND11_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND11_DONE_S  31
-
-/** RTC_I2C_CMD12_REG register
- *  i2c commond12 register
- */
-#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x68)
-/** RTC_I2C_COMMAND12 : R/W; bitpos: [13:0]; default: 5889;
- *  command12
- */
-#define RTC_I2C_COMMAND12    0x00003FFFU
-#define RTC_I2C_COMMAND12_M  (RTC_I2C_COMMAND12_V << RTC_I2C_COMMAND12_S)
-#define RTC_I2C_COMMAND12_V  0x00003FFFU
-#define RTC_I2C_COMMAND12_S  0
-/** RTC_I2C_COMMAND12_DONE : RO; bitpos: [31]; default: 0;
- *  command12_done
- */
-#define RTC_I2C_COMMAND12_DONE    (BIT(31))
-#define RTC_I2C_COMMAND12_DONE_M  (RTC_I2C_COMMAND12_DONE_V << RTC_I2C_COMMAND12_DONE_S)
-#define RTC_I2C_COMMAND12_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND12_DONE_S  31
-
-/** RTC_I2C_CMD13_REG register
- *  i2c commond13 register
- */
-#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x6c)
-/** RTC_I2C_COMMAND13 : R/W; bitpos: [13:0]; default: 6401;
- *  command13
- */
-#define RTC_I2C_COMMAND13    0x00003FFFU
-#define RTC_I2C_COMMAND13_M  (RTC_I2C_COMMAND13_V << RTC_I2C_COMMAND13_S)
-#define RTC_I2C_COMMAND13_V  0x00003FFFU
-#define RTC_I2C_COMMAND13_S  0
-/** RTC_I2C_COMMAND13_DONE : RO; bitpos: [31]; default: 0;
- *  command13_done
- */
-#define RTC_I2C_COMMAND13_DONE    (BIT(31))
-#define RTC_I2C_COMMAND13_DONE_M  (RTC_I2C_COMMAND13_DONE_V << RTC_I2C_COMMAND13_DONE_S)
-#define RTC_I2C_COMMAND13_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND13_DONE_S  31
-
-/** RTC_I2C_CMD14_REG register
- *  i2c commond14 register
- */
-#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x70)
-/** RTC_I2C_COMMAND14 : R/W; bitpos: [13:0]; default: 0;
- *  command14
- */
-#define RTC_I2C_COMMAND14    0x00003FFFU
-#define RTC_I2C_COMMAND14_M  (RTC_I2C_COMMAND14_V << RTC_I2C_COMMAND14_S)
-#define RTC_I2C_COMMAND14_V  0x00003FFFU
-#define RTC_I2C_COMMAND14_S  0
-/** RTC_I2C_COMMAND14_DONE : RO; bitpos: [31]; default: 0;
- *  command14_done
- */
-#define RTC_I2C_COMMAND14_DONE    (BIT(31))
-#define RTC_I2C_COMMAND14_DONE_M  (RTC_I2C_COMMAND14_DONE_V << RTC_I2C_COMMAND14_DONE_S)
-#define RTC_I2C_COMMAND14_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND14_DONE_S  31
-
-/** RTC_I2C_CMD15_REG register
- *  i2c commond15 register
- */
-#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x74)
-/** RTC_I2C_COMMAND15 : R/W; bitpos: [13:0]; default: 0;
- *  command15
- */
-#define RTC_I2C_COMMAND15    0x00003FFFU
-#define RTC_I2C_COMMAND15_M  (RTC_I2C_COMMAND15_V << RTC_I2C_COMMAND15_S)
-#define RTC_I2C_COMMAND15_V  0x00003FFFU
-#define RTC_I2C_COMMAND15_S  0
-/** RTC_I2C_COMMAND15_DONE : RO; bitpos: [31]; default: 0;
- *  command15_done
- */
-#define RTC_I2C_COMMAND15_DONE    (BIT(31))
-#define RTC_I2C_COMMAND15_DONE_M  (RTC_I2C_COMMAND15_DONE_V << RTC_I2C_COMMAND15_DONE_S)
-#define RTC_I2C_COMMAND15_DONE_V  0x00000001U
-#define RTC_I2C_COMMAND15_DONE_S  31
-
-/** RTC_I2C_DATE_REG register
- *  version register
- */
-#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0xfc)
-/** RTC_I2C_I2C_DATE : R/W; bitpos: [27:0]; default: 26235664;
- *  version
- */
-#define RTC_I2C_I2C_DATE    0x0FFFFFFFU
-#define RTC_I2C_I2C_DATE_M  (RTC_I2C_I2C_DATE_V << RTC_I2C_I2C_DATE_S)
-#define RTC_I2C_I2C_DATE_V  0x0FFFFFFFU
-#define RTC_I2C_I2C_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/sdmmc_reg.h b/components/soc/esp32s3/include/soc/sdmmc_reg.h
deleted file mode 100644
index 41c191eb68f..00000000000
--- a/components/soc/esp32s3/include/soc/sdmmc_reg.h
+++ /dev/null
@@ -1,94 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#pragma once
-
-#include "soc.h"
-
-#define SDMMC_CTRL_REG          (DR_REG_SDMMC_BASE + 0x00)
-#define SDMMC_PWREN_REG         (DR_REG_SDMMC_BASE + 0x04)
-#define SDMMC_CLKDIV_REG        (DR_REG_SDMMC_BASE + 0x08)
-#define SDMMC_CLKSRC_REG        (DR_REG_SDMMC_BASE + 0x0c)
-#define SDMMC_CLKENA_REG        (DR_REG_SDMMC_BASE + 0x10)
-#define SDMMC_TMOUT_REG         (DR_REG_SDMMC_BASE + 0x14)
-#define SDMMC_CTYPE_REG         (DR_REG_SDMMC_BASE + 0x18)
-#define SDMMC_BLKSIZ_REG        (DR_REG_SDMMC_BASE + 0x1c)
-#define SDMMC_BYTCNT_REG        (DR_REG_SDMMC_BASE + 0x20)
-#define SDMMC_INTMASK_REG       (DR_REG_SDMMC_BASE + 0x24)
-#define SDMMC_CMDARG_REG        (DR_REG_SDMMC_BASE + 0x28)
-#define SDMMC_CMD_REG           (DR_REG_SDMMC_BASE + 0x2c)
-#define SDMMC_RESP0_REG         (DR_REG_SDMMC_BASE + 0x30)
-#define SDMMC_RESP1_REG         (DR_REG_SDMMC_BASE + 0x34)
-#define SDMMC_RESP2_REG         (DR_REG_SDMMC_BASE + 0x38)
-#define SDMMC_RESP3_REG         (DR_REG_SDMMC_BASE + 0x3c)
-
-#define SDMMC_MINTSTS_REG       (DR_REG_SDMMC_BASE + 0x40)
-#define SDMMC_RINTSTS_REG       (DR_REG_SDMMC_BASE + 0x44)
-#define SDMMC_STATUS_REG        (DR_REG_SDMMC_BASE + 0x48)
-#define SDMMC_FIFOTH_REG        (DR_REG_SDMMC_BASE + 0x4c)
-#define SDMMC_CDETECT_REG       (DR_REG_SDMMC_BASE + 0x50)
-#define SDMMC_WRTPRT_REG        (DR_REG_SDMMC_BASE + 0x54)
-#define SDMMC_GPIO_REG          (DR_REG_SDMMC_BASE + 0x58)
-#define SDMMC_TCBCNT_REG        (DR_REG_SDMMC_BASE + 0x5c)
-#define SDMMC_TBBCNT_REG        (DR_REG_SDMMC_BASE + 0x60)
-#define SDMMC_DEBNCE_REG        (DR_REG_SDMMC_BASE + 0x64)
-#define SDMMC_USRID_REG         (DR_REG_SDMMC_BASE + 0x68)
-#define SDMMC_VERID_REG         (DR_REG_SDMMC_BASE + 0x6c)
-#define SDMMC_HCON_REG          (DR_REG_SDMMC_BASE + 0x70)
-#define SDMMC_UHS_REG_REG       (DR_REG_SDMMC_BASE + 0x74)
-#define SDMMC_RST_N_REG         (DR_REG_SDMMC_BASE + 0x78)
-#define SDMMC_BMOD_REG          (DR_REG_SDMMC_BASE + 0x80)
-#define SDMMC_PLDMND_REG        (DR_REG_SDMMC_BASE + 0x84)
-#define SDMMC_DBADDR_REG        (DR_REG_SDMMC_BASE + 0x88)
-#define SDMMC_DBADDRU_REG       (DR_REG_SDMMC_BASE + 0x8c)
-#define SDMMC_IDSTS_REG         (DR_REG_SDMMC_BASE + 0x8c)
-#define SDMMC_IDINTEN_REG       (DR_REG_SDMMC_BASE + 0x90)
-#define SDMMC_DSCADDR_REG       (DR_REG_SDMMC_BASE + 0x94)
-#define SDMMC_DSCADDRL_REG      (DR_REG_SDMMC_BASE + 0x98)
-#define SDMMC_DSCADDRU_REG      (DR_REG_SDMMC_BASE + 0x9c)
-#define SDMMC_BUFADDRL_REG      (DR_REG_SDMMC_BASE + 0xa0)
-#define SDMMC_BUFADDRU_REG      (DR_REG_SDMMC_BASE + 0xa4)
-#define SDMMC_CARDTHRCTL_REG    (DR_REG_SDMMC_BASE + 0x100)
-#define SDMMC_BACK_END_POWER_REG    (DR_REG_SDMMC_BASE + 0x104)
-#define SDMMC_UHS_REG_EXT_REG   (DR_REG_SDMMC_BASE + 0x108)
-#define SDMMC_EMMC_DDR_REG_REG  (DR_REG_SDMMC_BASE + 0x10c)
-#define SDMMC_ENABLE_SHIFT_REG  (DR_REG_SDMMC_BASE + 0x110)
-
-#define SDMMC_CLOCK_REG         (DR_REG_SDMMC_BASE + 0x800)
-
-#define SDMMC_INTMASK_IO_SLOT1  BIT(17)
-#define SDMMC_INTMASK_IO_SLOT0  BIT(16)
-#define SDMMC_INTMASK_EBE       BIT(15)
-#define SDMMC_INTMASK_ACD       BIT(14)
-#define SDMMC_INTMASK_SBE       BIT(13)
-#define SDMMC_INTMASK_HLE       BIT(12)
-#define SDMMC_INTMASK_FRUN      BIT(11)
-#define SDMMC_INTMASK_HTO       BIT(10)
-#define SDMMC_INTMASK_DTO       BIT(9)
-#define SDMMC_INTMASK_RTO       BIT(8)
-#define SDMMC_INTMASK_DCRC      BIT(7)
-#define SDMMC_INTMASK_RCRC      BIT(6)
-#define SDMMC_INTMASK_RXDR      BIT(5)
-#define SDMMC_INTMASK_TXDR      BIT(4)
-#define SDMMC_INTMASK_DATA_OVER BIT(3)
-#define SDMMC_INTMASK_CMD_DONE  BIT(2)
-#define SDMMC_INTMASK_RESP_ERR  BIT(1)
-#define SDMMC_INTMASK_CD        BIT(0)
-
-#define SDMMC_IDMAC_INTMASK_AI  BIT(9)
-#define SDMMC_IDMAC_INTMASK_NI  BIT(8)
-#define SDMMC_IDMAC_INTMASK_CES BIT(5)
-#define SDMMC_IDMAC_INTMASK_DU  BIT(4)
-#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
-#define SDMMC_IDMAC_INTMASK_RI  BIT(1)
-#define SDMMC_IDMAC_INTMASK_TI  BIT(0)
diff --git a/components/soc/esp32s3/include/soc/sensitive_reg.h b/components/soc/esp32s3/include/soc/sensitive_reg.h
deleted file mode 100644
index a3393c5c056..00000000000
--- a/components/soc/esp32s3/include/soc/sensitive_reg.h
+++ /dev/null
@@ -1,4726 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SENSITIVE_REG_H_
-#define _SOC_SENSITIVE_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG          (DR_REG_SENSITIVE_BASE + 0x0)
-/* SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK    (BIT(0))
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_M  (BIT(0))
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V  0x1
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S  0
-
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG          (DR_REG_SENSITIVE_BASE + 0x4)
-/* SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN : R/W ;bitpos:[7:0] ;default: ~8'b0 ; */
-/*description: .*/
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN    0x000000FF
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_M  ((SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V)<<(SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S))
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V  0xFF
-#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S  0
-
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x8)
-/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK    (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x1
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S  0
-
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0xC)
-/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST    (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x1
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG          (DR_REG_SENSITIVE_BASE + 0x10)
-/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK    (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x1
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG          (DR_REG_SENSITIVE_BASE + 0x14)
-/* SENSITIVE_INTERNAL_SRAM_CPU_USAGE : R/W ;bitpos:[10:4] ;default: ~7'h0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE    0x0000007F
-#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S))
-#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V  0x7F
-#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S  4
-/* SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE : R/W ;bitpos:[3:2] ;default: ~2'h0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE    0x00000003
-#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S))
-#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V  0x3
-#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S  2
-/* SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE : R/W ;bitpos:[1:0] ;default: ~2'h0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE    0x00000003
-#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S))
-#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V  0x3
-#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG          (DR_REG_SENSITIVE_BASE + 0x18)
-/* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC    0x00000003
-#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_M  ((SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V)<<(SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S))
-#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V  0x3
-#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S  16
-/* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC    0x00000003
-#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_M  ((SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V)<<(SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S))
-#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V  0x3
-#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S  14
-/* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE : R/W ;bitpos:[13:7] ;default: 7'b0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE    0x0000007F
-#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S))
-#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V  0x7F
-#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S  7
-/* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE    0x0000007F
-#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S))
-#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V  0x7F
-#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG          (DR_REG_SENSITIVE_BASE + 0x1C)
-/* SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE    0x0000000F
-#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S))
-#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V  0xF
-#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S  0
-
-#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG          (DR_REG_SENSITIVE_BASE + 0x20)
-/* SENSITIVE_INTERNAL_SRAM_LOG_USAGE : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
-/*description: .*/
-#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE    0x0000007F
-#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S))
-#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V  0x7F
-#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S  0
-
-#define SENSITIVE_RETENTION_DISABLE_REG          (DR_REG_SENSITIVE_BASE + 0x24)
-/* SENSITIVE_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_RETENTION_DISABLE    (BIT(0))
-#define SENSITIVE_RETENTION_DISABLE_M  (BIT(0))
-#define SENSITIVE_RETENTION_DISABLE_V  0x1
-#define SENSITIVE_RETENTION_DISABLE_S  0
-
-#define SENSITIVE_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x28)
-/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK    (BIT(0))
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x1
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S  0
-
-#define SENSITIVE_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x2C)
-/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_PRO_D_TAG_WR_ACS    (BIT(3))
-#define SENSITIVE_PRO_D_TAG_WR_ACS_M  (BIT(3))
-#define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x1
-#define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
-/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_PRO_D_TAG_RD_ACS    (BIT(2))
-#define SENSITIVE_PRO_D_TAG_RD_ACS_M  (BIT(2))
-#define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x1
-#define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
-/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_PRO_I_TAG_WR_ACS    (BIT(1))
-#define SENSITIVE_PRO_I_TAG_WR_ACS_M  (BIT(1))
-#define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x1
-#define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
-/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_PRO_I_TAG_RD_ACS    (BIT(0))
-#define SENSITIVE_PRO_I_TAG_RD_ACS_M  (BIT(0))
-#define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x1
-#define SENSITIVE_PRO_I_TAG_RD_ACS_S  0
-
-#define SENSITIVE_CACHE_MMU_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x30)
-/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK    (BIT(0))
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x1
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S  0
-
-#define SENSITIVE_CACHE_MMU_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x34)
-/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SENSITIVE_PRO_MMU_WR_ACS    (BIT(1))
-#define SENSITIVE_PRO_MMU_WR_ACS_M  (BIT(1))
-#define SENSITIVE_PRO_MMU_WR_ACS_V  0x1
-#define SENSITIVE_PRO_MMU_WR_ACS_S  1
-/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SENSITIVE_PRO_MMU_RD_ACS    (BIT(0))
-#define SENSITIVE_PRO_MMU_RD_ACS_M  (BIT(0))
-#define SENSITIVE_PRO_MMU_RD_ACS_V  0x1
-#define SENSITIVE_PRO_MMU_RD_ACS_S  0
-
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x38)
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x3C)
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x40)
-/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x44)
-/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x48)
-/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x4C)
-/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x50)
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x54)
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x58)
-/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x5C)
-/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x60)
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x64)
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x68)
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x6C)
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x70)
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x74)
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x78)
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x7C)
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x80)
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x84)
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x88)
-/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x8C)
-/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x90)
-/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x94)
-/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x98)
-/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x9C)
-/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xA0)
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xA4)
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xA8)
-/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xAC)
-/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S  0
-
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xB0)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xB4)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xB8)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[24:3] ;default: 22'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  3
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0xBC)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xC0)
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xC4)
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S  12
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S  10
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S  8
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S  6
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xC8)
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S  12
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S  10
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S  8
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S  6
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0xCC)
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S  12
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S  10
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S  8
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S  6
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0xD0)
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S  12
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S  10
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S  8
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S  6
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0xD4)
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S  12
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S  10
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S  8
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S  6
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xD8)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xDC)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  18
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S  15
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  12
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  9
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  6
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  3
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  0
-
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xE0)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  18
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S  15
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  12
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  9
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  6
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  3
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xE4)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xE8)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xEC)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE    (BIT(2))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xF0)
-/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xF4)
-/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xF8)
-/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
-/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
-/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE    (BIT(2))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
-/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(1))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
-/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xFC)
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x100)
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  26
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  24
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S  22
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  20
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S  10
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  8
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
-
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x104)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x108)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x10C)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK    (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x110)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
-
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x114)
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x118)
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x11C)
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK    (BIT(1))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x120)
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
-/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x124)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x128)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S  20
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x12C)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x130)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x134)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x138)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S  20
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x13C)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x140)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x144)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x148)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1    0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0    0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x14C)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x150)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1    0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S  11
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0    0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x154)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S  9
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S  3
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x158)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1    0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S  11
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0    0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x15C)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S  9
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S  3
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x160)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x164)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S  20
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S  18
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S  16
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S  14
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x168)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S  20
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S  18
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S  16
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S  14
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0    0x00000003
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x16C)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x170)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x174)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x178)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x17C)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x180)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x184)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x188)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x18C)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x190)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x194)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S  0
-
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x198)
-/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11    0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S))
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V  0x3FFFFFFF
-#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x19C)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x1A0)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x1A4)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(5))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0    (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x1A8)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR    0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x1AC)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x1B0)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x1B4)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
-
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x1B8)
-/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V  0x1
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S  0
-
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x1BC)
-/* SENSITIVE_CORE_0_VECBASE_WORLD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK    (BIT(0))
-#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_M  (BIT(0))
-#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_V  0x1
-#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_S  0
-
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x1C0)
-/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL    0x00000003
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S))
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V  0x3
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S  22
-/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE    0x003FFFFF
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S))
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V  0x3FFFFF
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S  0
-
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_REG          (DR_REG_SENSITIVE_BASE + 0x1C4)
-/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE    0x003FFFFF
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S))
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V  0x3FFFFF
-#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S  0
-
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x1C8)
-/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V  0x1
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S  0
-
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x1CC)
-/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE    (BIT(0))
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_M  (BIT(0))
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V  0x1
-#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x1D0)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x1D4)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S  28
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S  20
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x1D8)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S  24
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S  18
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S  12
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S  8
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x1DC)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S  16
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S  12
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S  8
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S  2
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x1E0)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S  10
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x1E4)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S  28
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S  20
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x1E8)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S  24
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S  18
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S  12
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S  8
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x1EC)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S  16
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S  12
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S  8
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S  2
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x1F0)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S  14
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S  10
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x1F4)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1    0x000007FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0    0x000007FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x1F8)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x1FC)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1    0x000007FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V  0x7FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S  11
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0    0x000007FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V  0x7FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x200)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S  9
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S  3
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x204)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1    0x000007FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V  0x7FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S  11
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0    0x000007FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V  0x7FF
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x208)
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S  9
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S  3
-/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S))
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x20C)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x210)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S  20
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S  18
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S  16
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S  14
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x214)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S  20
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S  18
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S  16
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S  14
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0    0x00000003
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x218)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x21C)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x220)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x224)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x228)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x22C)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x230)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x234)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x238)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x23C)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x240)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S  0
-
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x244)
-/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11    0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S))
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V  0x3FFFFFFF
-#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x248)
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x24C)
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x250)
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(5))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0    (BIT(1))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x254)
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR    0xFFFFFFFF
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x258)
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x25C)
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
-
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x260)
-/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFF
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
-#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
-
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x264)
-/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK    (BIT(0))
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V  0x1
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S  0
-
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x268)
-/* SENSITIVE_CORE_1_VECBASE_WORLD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK    (BIT(0))
-#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_M  (BIT(0))
-#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_V  0x1
-#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_S  0
-
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x26C)
-/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL    0x00000003
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S))
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V  0x3
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S  22
-/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE    0x003FFFFF
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S))
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V  0x3FFFFF
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S  0
-
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_2_REG          (DR_REG_SENSITIVE_BASE + 0x270)
-/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE    0x003FFFFF
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S))
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V  0x3FFFFF
-#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S  0
-
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x274)
-/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK    (BIT(0))
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V  0x1
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S  0
-
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x278)
-/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE    (BIT(0))
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_M  (BIT(0))
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V  0x1
-#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x27C)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x280)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S  30
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S  28
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S  24
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S  20
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S  8
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S  2
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x284)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S  30
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S  28
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S  24
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S  22
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S  18
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S  12
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S  8
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x288)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S  28
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S  22
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S  12
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S  8
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S  2
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x28C)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S  30
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S  28
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S  24
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S  22
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S  20
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S  18
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S  12
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S  8
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S  2
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x290)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR    0x000007FF
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V  0x7FF
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x294)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H    0x00000007
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V  0x7
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S  3
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L    0x00000007
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V  0x7
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x298)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x29C)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x2A0)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(6))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(6))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  3
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S  1
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S  0
-
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x2A4)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR    0xFFFFFFFF
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V  0xFFFFFFFF
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S  0
-
-#define SENSITIVE_EDMA_BOUNDARY_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2A8)
-/* SENSITIVE_EDMA_BOUNDARY_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_BOUNDARY_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_BOUNDARY_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_BOUNDARY_LOCK_V  0x1
-#define SENSITIVE_EDMA_BOUNDARY_LOCK_S  0
-
-#define SENSITIVE_EDMA_BOUNDARY_0_REG          (DR_REG_SENSITIVE_BASE + 0x2AC)
-/* SENSITIVE_EDMA_BOUNDARY_0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_BOUNDARY_0    0x00003FFF
-#define SENSITIVE_EDMA_BOUNDARY_0_M  ((SENSITIVE_EDMA_BOUNDARY_0_V)<<(SENSITIVE_EDMA_BOUNDARY_0_S))
-#define SENSITIVE_EDMA_BOUNDARY_0_V  0x3FFF
-#define SENSITIVE_EDMA_BOUNDARY_0_S  0
-
-#define SENSITIVE_EDMA_BOUNDARY_1_REG          (DR_REG_SENSITIVE_BASE + 0x2B0)
-/* SENSITIVE_EDMA_BOUNDARY_1 : R/W ;bitpos:[13:0] ;default: 14'h2000 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_BOUNDARY_1    0x00003FFF
-#define SENSITIVE_EDMA_BOUNDARY_1_M  ((SENSITIVE_EDMA_BOUNDARY_1_V)<<(SENSITIVE_EDMA_BOUNDARY_1_S))
-#define SENSITIVE_EDMA_BOUNDARY_1_V  0x3FFF
-#define SENSITIVE_EDMA_BOUNDARY_1_S  0
-
-#define SENSITIVE_EDMA_BOUNDARY_2_REG          (DR_REG_SENSITIVE_BASE + 0x2B4)
-/* SENSITIVE_EDMA_BOUNDARY_2 : R/W ;bitpos:[13:0] ;default: 14'h2000 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_BOUNDARY_2    0x00003FFF
-#define SENSITIVE_EDMA_BOUNDARY_2_M  ((SENSITIVE_EDMA_BOUNDARY_2_V)<<(SENSITIVE_EDMA_BOUNDARY_2_S))
-#define SENSITIVE_EDMA_BOUNDARY_2_V  0x3FFF
-#define SENSITIVE_EDMA_BOUNDARY_2_S  0
-
-#define SENSITIVE_EDMA_PMS_SPI2_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2B8)
-/* SENSITIVE_EDMA_PMS_SPI2_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SPI2_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_SPI2_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_SPI2_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_SPI2_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_SPI2_REG          (DR_REG_SENSITIVE_BASE + 0x2BC)
-/* SENSITIVE_EDMA_PMS_SPI2_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SPI2_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_M  ((SENSITIVE_EDMA_PMS_SPI2_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_SPI2_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SPI2_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_M  ((SENSITIVE_EDMA_PMS_SPI2_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_SPI3_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2C0)
-/* SENSITIVE_EDMA_PMS_SPI3_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SPI3_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_SPI3_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_SPI3_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_SPI3_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_SPI3_REG          (DR_REG_SENSITIVE_BASE + 0x2C4)
-/* SENSITIVE_EDMA_PMS_SPI3_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SPI3_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_M  ((SENSITIVE_EDMA_PMS_SPI3_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_SPI3_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SPI3_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_M  ((SENSITIVE_EDMA_PMS_SPI3_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2C8)
-/* SENSITIVE_EDMA_PMS_UHCI0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_UHCI0_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_UHCI0_REG          (DR_REG_SENSITIVE_BASE + 0x2CC)
-/* SENSITIVE_EDMA_PMS_UHCI0_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_M  ((SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_UHCI0_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_M  ((SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_I2S0_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2D0)
-/* SENSITIVE_EDMA_PMS_I2S0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_I2S0_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_I2S0_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_I2S0_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_I2S0_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_I2S0_REG          (DR_REG_SENSITIVE_BASE + 0x2D4)
-/* SENSITIVE_EDMA_PMS_I2S0_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_I2S0_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_M  ((SENSITIVE_EDMA_PMS_I2S0_ATTR2_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_I2S0_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_I2S0_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_M  ((SENSITIVE_EDMA_PMS_I2S0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_I2S1_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2D8)
-/* SENSITIVE_EDMA_PMS_I2S1_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_I2S1_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_I2S1_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_I2S1_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_I2S1_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_I2S1_REG          (DR_REG_SENSITIVE_BASE + 0x2DC)
-/* SENSITIVE_EDMA_PMS_I2S1_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_I2S1_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_M  ((SENSITIVE_EDMA_PMS_I2S1_ATTR2_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_I2S1_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_I2S1_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_M  ((SENSITIVE_EDMA_PMS_I2S1_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2E0)
-/* SENSITIVE_EDMA_PMS_LCD_CAM_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_LCD_CAM_REG          (DR_REG_SENSITIVE_BASE + 0x2E4)
-/* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_M  ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_M  ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_AES_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2E8)
-/* SENSITIVE_EDMA_PMS_AES_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_AES_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_AES_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_AES_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_AES_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_AES_REG          (DR_REG_SENSITIVE_BASE + 0x2EC)
-/* SENSITIVE_EDMA_PMS_AES_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_AES_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_AES_ATTR2_M  ((SENSITIVE_EDMA_PMS_AES_ATTR2_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_AES_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_AES_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_AES_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_AES_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_AES_ATTR1_M  ((SENSITIVE_EDMA_PMS_AES_ATTR1_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_AES_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_AES_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_SHA_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2F0)
-/* SENSITIVE_EDMA_PMS_SHA_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SHA_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_SHA_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_SHA_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_SHA_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_SHA_REG          (DR_REG_SENSITIVE_BASE + 0x2F4)
-/* SENSITIVE_EDMA_PMS_SHA_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SHA_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_SHA_ATTR2_M  ((SENSITIVE_EDMA_PMS_SHA_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_SHA_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_SHA_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_SHA_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_SHA_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_SHA_ATTR1_M  ((SENSITIVE_EDMA_PMS_SHA_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_SHA_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_SHA_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2F8)
-/* SENSITIVE_EDMA_PMS_ADC_DAC_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_ADC_DAC_REG          (DR_REG_SENSITIVE_BASE + 0x2FC)
-/* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_M  ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_M  ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S  0
-
-#define SENSITIVE_EDMA_PMS_RMT_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x300)
-/* SENSITIVE_EDMA_PMS_RMT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_RMT_LOCK    (BIT(0))
-#define SENSITIVE_EDMA_PMS_RMT_LOCK_M  (BIT(0))
-#define SENSITIVE_EDMA_PMS_RMT_LOCK_V  0x1
-#define SENSITIVE_EDMA_PMS_RMT_LOCK_S  0
-
-#define SENSITIVE_EDMA_PMS_RMT_REG          (DR_REG_SENSITIVE_BASE + 0x304)
-/* SENSITIVE_EDMA_PMS_RMT_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_RMT_ATTR2    0x00000003
-#define SENSITIVE_EDMA_PMS_RMT_ATTR2_M  ((SENSITIVE_EDMA_PMS_RMT_ATTR2_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR2_S))
-#define SENSITIVE_EDMA_PMS_RMT_ATTR2_V  0x3
-#define SENSITIVE_EDMA_PMS_RMT_ATTR2_S  2
-/* SENSITIVE_EDMA_PMS_RMT_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: .*/
-#define SENSITIVE_EDMA_PMS_RMT_ATTR1    0x00000003
-#define SENSITIVE_EDMA_PMS_RMT_ATTR1_M  ((SENSITIVE_EDMA_PMS_RMT_ATTR1_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR1_S))
-#define SENSITIVE_EDMA_PMS_RMT_ATTR1_V  0x3
-#define SENSITIVE_EDMA_PMS_RMT_ATTR1_S  0
-
-#define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x308)
-/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SENSITIVE_CLK_EN    (BIT(0))
-#define SENSITIVE_CLK_EN_M  (BIT(0))
-#define SENSITIVE_CLK_EN_V  0x1
-#define SENSITIVE_CLK_EN_S  0
-
-#define SENSITIVE_RTC_PMS_REG          (DR_REG_SENSITIVE_BASE + 0x30C)
-/* SENSITIVE_DIS_RTC_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SENSITIVE_DIS_RTC_CPU    (BIT(0))
-#define SENSITIVE_DIS_RTC_CPU_M  (BIT(0))
-#define SENSITIVE_DIS_RTC_CPU_V  0x1
-#define SENSITIVE_DIS_RTC_CPU_S  0
-
-#define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
-/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101280 ; */
-/*description: .*/
-#define SENSITIVE_DATE    0x0FFFFFFF
-#define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
-#define SENSITIVE_DATE_V  0xFFFFFFF
-#define SENSITIVE_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SENSITIVE_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/sensitive_struct.h b/components/soc/esp32s3/include/soc/sensitive_struct.h
deleted file mode 100644
index e9919cb0a69..00000000000
--- a/components/soc/esp32s3/include/soc/sensitive_struct.h
+++ /dev/null
@@ -1,2753 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SENSITIVE_STRUCT_H_
-#define _SOC_SENSITIVE_STRUCT_H_
-
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct sensitive_dev_s {
-    union {
-        struct {
-            uint32_t cache_dataarray_connect_lock  :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cache_dataarray_connect_0;
-    union {
-        struct {
-            uint32_t cache_dataarray_connect_flatten:    8;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } cache_dataarray_connect_1;
-    union {
-        struct {
-            uint32_t apb_peripheral_access_lock    :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } apb_peripheral_access_0;
-    union {
-        struct {
-            uint32_t apb_peripheral_access_split_burst:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } apb_peripheral_access_1;
-    union {
-        struct {
-            uint32_t internal_sram_usage_lock      :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } internal_sram_usage_0;
-    union {
-        struct {
-            uint32_t internal_sram_icache_usage    :    2;
-            uint32_t internal_sram_dcache_usage    :    2;
-            uint32_t internal_sram_cpu_usage       :    7;
-            uint32_t reserved11                    :    21;
-        };
-        uint32_t val;
-    } internal_sram_usage_1;
-    union {
-        struct {
-            uint32_t internal_sram_core0_trace_usage:    7;
-            uint32_t internal_sram_core1_trace_usage:    7;
-            uint32_t internal_sram_core0_trace_alloc:    2;
-            uint32_t internal_sram_core1_trace_alloc:    2;
-            uint32_t reserved18                    :    14;
-        };
-        uint32_t val;
-    } internal_sram_usage_2;
-    union {
-        struct {
-            uint32_t internal_sram_mac_dump_usage  :    4;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } internal_sram_usage_3;
-    union {
-        struct {
-            uint32_t internal_sram_log_usage       :    7;
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } internal_sram_usage_4;
-    union {
-        struct {
-            uint32_t retention_disable             :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } retention_disable;
-    union {
-        struct {
-            uint32_t cache_tag_access_lock         :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cache_tag_access_0;
-    union {
-        struct {
-            uint32_t pro_i_tag_rd_acs              :    1;
-            uint32_t pro_i_tag_wr_acs              :    1;
-            uint32_t pro_d_tag_rd_acs              :    1;
-            uint32_t pro_d_tag_wr_acs              :    1;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } cache_tag_access_1;
-    union {
-        struct {
-            uint32_t cache_mmu_access_lock         :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cache_mmu_access_0;
-    union {
-        struct {
-            uint32_t pro_mmu_rd_acs                :    1;
-            uint32_t pro_mmu_wr_acs                :    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } cache_mmu_access_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_spi2_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_spi2_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_spi2_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_spi3_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_spi3_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_spi3_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_uhci0_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_uhci0_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_uhci0_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_i2s0_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_i2s0_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_i2s0_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_i2s1_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_i2s1_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_i2s1_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_mac_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_mac_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_mac_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_mac_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_mac_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_mac_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_mac_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_backup_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_backup_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_backup_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_backup_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_backup_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_backup_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_backup_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_aes_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_aes_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_aes_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_aes_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_aes_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_aes_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_aes_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_sha_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_sha_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_sha_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_sha_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_sha_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_sha_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_sha_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_adc_dac_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_adc_dac_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_adc_dac_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_rmt_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_rmt_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_rmt_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_lcd_cam_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_lcd_cam_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_lcd_cam_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_usb_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_usb_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_usb_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_usb_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_usb_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_usb_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_usb_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_lc_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_lc_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_lc_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_lc_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_lc_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_lc_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_lc_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_sdio_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_sdio_pms_constrain_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_0:    2;
-            uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_1:    2;
-            uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_2:    2;
-            uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_3:    2;
-            uint32_t dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_0:    2;
-            uint32_t dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_1:    2;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } dma_apbperi_sdio_pms_constrain_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_pms_monitor_lock  :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } dma_apbperi_pms_monitor_0;
-    union {
-        struct {
-            uint32_t dma_apbperi_pms_monitor_violate_clr:    1;
-            uint32_t dma_apbperi_pms_monitor_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } dma_apbperi_pms_monitor_1;
-    union {
-        struct {
-            uint32_t dma_apbperi_pms_monitor_violate_intr:    1;
-            uint32_t dma_apbperi_pms_monitor_violate_status_world:    2;
-            uint32_t dma_apbperi_pms_monitor_violate_status_addr:    22;
-            uint32_t reserved25                    :    7;
-        };
-        uint32_t val;
-    } dma_apbperi_pms_monitor_2;
-    union {
-        struct {
-            uint32_t dma_apbperi_pms_monitor_violate_status_wr:    1;
-            uint32_t dma_apbperi_pms_monitor_violate_status_byteen:    16;
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } dma_apbperi_pms_monitor_3;
-    union {
-        struct {
-            uint32_t core_x_iram0_dram0_dma_split_line_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_0;
-    union {
-        struct {
-            uint32_t core_x_iram0_dram0_dma_sram_category_0:    2;
-            uint32_t core_x_iram0_dram0_dma_sram_category_1:    2;
-            uint32_t core_x_iram0_dram0_dma_sram_category_2:    2;
-            uint32_t core_x_iram0_dram0_dma_sram_category_3:    2;
-            uint32_t core_x_iram0_dram0_dma_sram_category_4:    2;
-            uint32_t core_x_iram0_dram0_dma_sram_category_5:    2;
-            uint32_t core_x_iram0_dram0_dma_sram_category_6:    2;
-            uint32_t core_x_iram0_dram0_dma_sram_splitaddr:    8;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_1;
-    union {
-        struct {
-            uint32_t core_x_iram0_sram_line_0_category_0:    2;
-            uint32_t core_x_iram0_sram_line_0_category_1:    2;
-            uint32_t core_x_iram0_sram_line_0_category_2:    2;
-            uint32_t core_x_iram0_sram_line_0_category_3:    2;
-            uint32_t core_x_iram0_sram_line_0_category_4:    2;
-            uint32_t core_x_iram0_sram_line_0_category_5:    2;
-            uint32_t core_x_iram0_sram_line_0_category_6:    2;
-            uint32_t core_x_iram0_sram_line_0_splitaddr:    8;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_2;
-    union {
-        struct {
-            uint32_t core_x_iram0_sram_line_1_category_0:    2;
-            uint32_t core_x_iram0_sram_line_1_category_1:    2;
-            uint32_t core_x_iram0_sram_line_1_category_2:    2;
-            uint32_t core_x_iram0_sram_line_1_category_3:    2;
-            uint32_t core_x_iram0_sram_line_1_category_4:    2;
-            uint32_t core_x_iram0_sram_line_1_category_5:    2;
-            uint32_t core_x_iram0_sram_line_1_category_6:    2;
-            uint32_t core_x_iram0_sram_line_1_splitaddr:    8;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_3;
-    union {
-        struct {
-            uint32_t core_x_dram0_dma_sram_line_0_category_0:    2;
-            uint32_t core_x_dram0_dma_sram_line_0_category_1:    2;
-            uint32_t core_x_dram0_dma_sram_line_0_category_2:    2;
-            uint32_t core_x_dram0_dma_sram_line_0_category_3:    2;
-            uint32_t core_x_dram0_dma_sram_line_0_category_4:    2;
-            uint32_t core_x_dram0_dma_sram_line_0_category_5:    2;
-            uint32_t core_x_dram0_dma_sram_line_0_category_6:    2;
-            uint32_t core_x_dram0_dma_sram_line_0_splitaddr:    8;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_4;
-    union {
-        struct {
-            uint32_t core_x_dram0_dma_sram_line_1_category_0:    2;
-            uint32_t core_x_dram0_dma_sram_line_1_category_1:    2;
-            uint32_t core_x_dram0_dma_sram_line_1_category_2:    2;
-            uint32_t core_x_dram0_dma_sram_line_1_category_3:    2;
-            uint32_t core_x_dram0_dma_sram_line_1_category_4:    2;
-            uint32_t core_x_dram0_dma_sram_line_1_category_5:    2;
-            uint32_t core_x_dram0_dma_sram_line_1_category_6:    2;
-            uint32_t core_x_dram0_dma_sram_line_1_splitaddr:    8;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_x_iram0_dram0_dma_split_line_constrain_5;
-    union {
-        struct {
-            uint32_t core_x_iram0_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_x_iram0_pms_constrain_0;
-    union {
-        struct {
-            uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_0:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_1:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_2:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_3:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1:    3;
-            uint32_t core_x_iram0_pms_constrain_rom_world_1_pms:    3;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } core_x_iram0_pms_constrain_1;
-    union {
-        struct {
-            uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_0:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_1:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_2:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_3:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0:    3;
-            uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1:    3;
-            uint32_t core_x_iram0_pms_constrain_rom_world_0_pms:    3;
-            uint32_t reserved21                    :    11;
-        };
-        uint32_t val;
-    } core_x_iram0_pms_constrain_2;
-    union {
-        struct {
-            uint32_t core_0_iram0_pms_monitor_lock :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_iram0_pms_monitor_0;
-    union {
-        struct {
-            uint32_t core_0_iram0_pms_monitor_violate_clr:    1;
-            uint32_t core_0_iram0_pms_monitor_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_0_iram0_pms_monitor_1;
-    union {
-        struct {
-            uint32_t core_0_iram0_pms_monitor_violate_intr:    1;
-            uint32_t core_0_iram0_pms_monitor_violate_status_wr:    1;
-            uint32_t core_0_iram0_pms_monitor_violate_status_loadstore:    1;
-            uint32_t core_0_iram0_pms_monitor_violate_status_world:    2;
-            uint32_t core_0_iram0_pms_monitor_violate_status_addr:    24;
-            uint32_t reserved29                    :    3;
-        };
-        uint32_t val;
-    } core_0_iram0_pms_monitor_2;
-    union {
-        struct {
-            uint32_t core_1_iram0_pms_monitor_lock :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_iram0_pms_monitor_0;
-    union {
-        struct {
-            uint32_t core_1_iram0_pms_monitor_violate_clr:    1;
-            uint32_t core_1_iram0_pms_monitor_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_1_iram0_pms_monitor_1;
-    union {
-        struct {
-            uint32_t core_1_iram0_pms_monitor_violate_intr:    1;
-            uint32_t core_1_iram0_pms_monitor_violate_status_wr:    1;
-            uint32_t core_1_iram0_pms_monitor_violate_status_loadstore:    1;
-            uint32_t core_1_iram0_pms_monitor_violate_status_world:    2;
-            uint32_t core_1_iram0_pms_monitor_violate_status_addr:    24;
-            uint32_t reserved29                    :    3;
-        };
-        uint32_t val;
-    } core_1_iram0_pms_monitor_2;
-    union {
-        struct {
-            uint32_t core_x_dram0_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_x_dram0_pms_constrain_0;
-    union {
-        struct {
-            uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_0:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_1:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_2:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_3:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_0:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_1:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_2:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_3:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0:    2;
-            uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1:    2;
-            uint32_t core_x_dram0_pms_constrain_rom_world_0_pms:    2;
-            uint32_t core_x_dram0_pms_constrain_rom_world_1_pms:    2;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } core_x_dram0_pms_constrain_1;
-    union {
-        struct {
-            uint32_t core_0_dram0_pms_monitor_lock :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_dram0_pms_monitor_0;
-    union {
-        struct {
-            uint32_t core_0_dram0_pms_monitor_violate_clr:    1;
-            uint32_t core_0_dram0_pms_monitor_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_0_dram0_pms_monitor_1;
-    union {
-        struct {
-            uint32_t core_0_dram0_pms_monitor_violate_intr:    1;
-            uint32_t core_0_dram0_pms_monitor_violate_status_lock:    1;
-            uint32_t core_0_dram0_pms_monitor_violate_status_world:    2;
-            uint32_t core_0_dram0_pms_monitor_violate_status_addr:    22;
-            uint32_t reserved26                    :    6;
-        };
-        uint32_t val;
-    } core_0_dram0_pms_monitor_2;
-    union {
-        struct {
-            uint32_t core_0_dram0_pms_monitor_violate_status_wr:    1;
-            uint32_t core_0_dram0_pms_monitor_violate_status_byteen:    16;
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } core_0_dram0_pms_monitor_3;
-    union {
-        struct {
-            uint32_t core_1_dram0_pms_monitor_lock :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_dram0_pms_monitor_0;
-    union {
-        struct {
-            uint32_t core_1_dram0_pms_monitor_violate_clr:    1;
-            uint32_t core_1_dram0_pms_monitor_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_1_dram0_pms_monitor_1;
-    union {
-        struct {
-            uint32_t core_1_dram0_pms_monitor_violate_intr:    1;
-            uint32_t core_1_dram0_pms_monitor_violate_status_lock:    1;
-            uint32_t core_1_dram0_pms_monitor_violate_status_world:    2;
-            uint32_t core_1_dram0_pms_monitor_violate_status_addr:    22;
-            uint32_t reserved26                    :    6;
-        };
-        uint32_t val;
-    } core_1_dram0_pms_monitor_2;
-    union {
-        struct {
-            uint32_t core_1_dram0_pms_monitor_violate_status_wr:    1;
-            uint32_t core_1_dram0_pms_monitor_violate_status_byteen:    16;
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } core_1_dram0_pms_monitor_3;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_lock :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_0;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_world_0_uart:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_g0spi_1:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_g0spi_0:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_gpio:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_fe2:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_fe:    2;
-            uint32_t reserved12                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_0_rtc:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_io_mux:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_0_hinf:    2;
-            uint32_t reserved22                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_0_misc:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_i2c:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_i2s0:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_uart1:    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_1;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_world_0_bt:    2;
-            uint32_t reserved2                     :    2;
-            uint32_t core_0_pif_pms_constrain_world_0_i2c_ext0:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_uhci0:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_slchost:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_rmt:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_pcnt:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_slc:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_ledc:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_backup:    2;
-            uint32_t reserved20                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_0_bb:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_pwm0:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_timergroup:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_timergroup1:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_systimer:    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_2;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_world_0_spi_2:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_spi_3:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_apb_ctrl:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_i2c_ext1:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_sdio_host:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_can:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_pwm1:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_i2s1:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_uart2:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t reserved20                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_0_rwbt:    2;
-            uint32_t reserved24                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_0_wifimac:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_pwr:    2;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_3;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_world_0_usb_device:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_usb_wrap:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_crypto_peri:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_crypto_dma:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_apb_adc:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_lcd_cam:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_bt_pwr:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_usb:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_system:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_sensitive:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_interrupt:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_dma_copy:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_cache_config:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_ad:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_dio:    2;
-            uint32_t core_0_pif_pms_constrain_world_0_world_controller:    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_4;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_world_1_uart:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_g0spi_1:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_g0spi_0:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_gpio:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_fe2:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_fe:    2;
-            uint32_t reserved12                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_1_rtc:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_io_mux:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_1_hinf:    2;
-            uint32_t reserved22                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_1_misc:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_i2c:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_i2s0:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_uart1:    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_5;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_world_1_bt:    2;
-            uint32_t reserved2                     :    2;
-            uint32_t core_0_pif_pms_constrain_world_1_i2c_ext0:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_uhci0:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_slchost:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_rmt:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_pcnt:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_slc:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_ledc:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_backup:    2;
-            uint32_t reserved20                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_1_bb:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_pwm0:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_timergroup:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_timergroup1:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_systimer:    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_6;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_world_1_spi_2:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_spi_3:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_apb_ctrl:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_i2c_ext1:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_sdio_host:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_can:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_pwm1:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_i2s1:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_uart2:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t reserved20                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_1_rwbt:    2;
-            uint32_t reserved24                    :    2;
-            uint32_t core_0_pif_pms_constrain_world_1_wifimac:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_pwr:    2;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_7;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_world_1_usb_device:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_usb_wrap:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_crypto_peri:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_crypto_dma:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_apb_adc:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_lcd_cam:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_bt_pwr:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_usb:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_system:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_sensitive:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_interrupt:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_dma_copy:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_cache_config:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_ad:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_dio:    2;
-            uint32_t core_0_pif_pms_constrain_world_1_world_controller:    2;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_8;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:    11;
-            uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_1:    11;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_9;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_rtcfast_world_0_l:    3;
-            uint32_t core_0_pif_pms_constrain_rtcfast_world_0_h:    3;
-            uint32_t core_0_pif_pms_constrain_rtcfast_world_1_l:    3;
-            uint32_t core_0_pif_pms_constrain_rtcfast_world_1_h:    3;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_10;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0:    11;
-            uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1:    11;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_11;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_l:    3;
-            uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_h:    3;
-            uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_l:    3;
-            uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_h:    3;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_12;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0:    11;
-            uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1:    11;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_13;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_l:    3;
-            uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_h:    3;
-            uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_l:    3;
-            uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_h:    3;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_0_pif_pms_constrain_14;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_0;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_world_0_area_0:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_1:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_2:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_3:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_4:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_5:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_6:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_7:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_8:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_9:    2;
-            uint32_t core_0_region_pms_constrain_world_0_area_10:    2;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_1;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_world_1_area_0:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_1:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_2:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_3:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_4:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_5:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_6:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_7:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_8:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_9:    2;
-            uint32_t core_0_region_pms_constrain_world_1_area_10:    2;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_2;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_0:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_3;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_1:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_4;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_2:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_5;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_3:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_6;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_4:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_7;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_5:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_8;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_6:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_9;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_7:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_10;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_8:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_11;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_9:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_12;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_10:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_13;
-    union {
-        struct {
-            uint32_t core_0_region_pms_constrain_addr_11:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_0_region_pms_constrain_14;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_monitor_lock   :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_0;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_monitor_violate_clr:    1;
-            uint32_t core_0_pif_pms_monitor_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_1;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_monitor_violate_intr:    1;
-            uint32_t core_0_pif_pms_monitor_violate_status_hport_0:    1;
-            uint32_t core_0_pif_pms_monitor_violate_status_hsize:    3;
-            uint32_t core_0_pif_pms_monitor_violate_status_hwrite:    1;
-            uint32_t core_0_pif_pms_monitor_violate_status_hworld:    2;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_2;
-    uint32_t core_0_pif_pms_monitor_3;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_monitor_nonword_violate_clr:    1;
-            uint32_t core_0_pif_pms_monitor_nonword_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_4;
-    union {
-        struct {
-            uint32_t core_0_pif_pms_monitor_nonword_violate_intr:    1;
-            uint32_t core_0_pif_pms_monitor_nonword_violate_status_hsize:    2;
-            uint32_t core_0_pif_pms_monitor_nonword_violate_status_hworld:    2;
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core_0_pif_pms_monitor_5;
-    uint32_t core_0_pif_pms_monitor_6;
-    union {
-        struct {
-            uint32_t core_0_vecbase_override_lock  :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_vecbase_override_lock;
-    union {
-        struct {
-            uint32_t core_0_vecbase_world_mask     :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_vecbase_override_0;
-    union {
-        struct {
-            uint32_t core_0_vecbase_override_world0_value:    22;
-            uint32_t core_0_vecbase_override_sel   :    2;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } core_0_vecbase_override_1;
-    union {
-        struct {
-            uint32_t core_0_vecbase_override_world1_value:    22;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_0_vecbase_override_2;
-    union {
-        struct {
-            uint32_t core_0_toomanyexceptions_m_override_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_toomanyexceptions_m_override_0;
-    union {
-        struct {
-            uint32_t core_0_toomanyexceptions_m_override:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_0_toomanyexceptions_m_override_1;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_lock :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_0;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_world_0_uart:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_g0spi_1:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_g0spi_0:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_gpio:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_fe2:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_fe:    2;
-            uint32_t reserved12                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_0_rtc:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_io_mux:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_0_hinf:    2;
-            uint32_t reserved22                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_0_misc:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_i2c:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_i2s0:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_uart1:    2;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_1;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_world_0_bt:    2;
-            uint32_t reserved2                     :    2;
-            uint32_t core_1_pif_pms_constrain_world_0_i2c_ext0:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_uhci0:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_slchost:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_rmt:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_pcnt:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_slc:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_ledc:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_backup:    2;
-            uint32_t reserved20                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_0_bb:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_pwm0:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_timergroup:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_timergroup1:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_systimer:    2;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_2;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_world_0_spi_2:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_spi_3:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_apb_ctrl:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_i2c_ext1:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_sdio_host:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_can:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_pwm1:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_i2s1:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_uart2:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t reserved20                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_0_rwbt:    2;
-            uint32_t reserved24                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_0_wifimac:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_pwr:    2;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_3;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_world_0_usb_device:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_usb_wrap:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_crypto_peri:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_crypto_dma:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_apb_adc:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_lcd_cam:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_bt_pwr:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_usb:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_system:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_sensitive:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_interrupt:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_dma_copy:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_cache_config:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_ad:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_dio:    2;
-            uint32_t core_1_pif_pms_constrain_world_0_world_controller:    2;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_4;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_world_1_uart:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_g0spi_1:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_g0spi_0:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_gpio:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_fe2:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_fe:    2;
-            uint32_t reserved12                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_1_rtc:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_io_mux:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_1_hinf:    2;
-            uint32_t reserved22                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_1_misc:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_i2c:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_i2s0:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_uart1:    2;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_5;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_world_1_bt:    2;
-            uint32_t reserved2                     :    2;
-            uint32_t core_1_pif_pms_constrain_world_1_i2c_ext0:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_uhci0:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_slchost:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_rmt:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_pcnt:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_slc:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_ledc:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_backup:    2;
-            uint32_t reserved20                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_1_bb:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_pwm0:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_timergroup:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_timergroup1:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_systimer:    2;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_6;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_world_1_spi_2:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_spi_3:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_apb_ctrl:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_i2c_ext1:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_sdio_host:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_can:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_pwm1:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_i2s1:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_uart2:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t reserved20                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_1_rwbt:    2;
-            uint32_t reserved24                    :    2;
-            uint32_t core_1_pif_pms_constrain_world_1_wifimac:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_pwr:    2;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_7;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_world_1_usb_device:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_usb_wrap:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_crypto_peri:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_crypto_dma:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_apb_adc:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_lcd_cam:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_bt_pwr:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_usb:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_system:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_sensitive:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_interrupt:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_dma_copy:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_cache_config:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_ad:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_dio:    2;
-            uint32_t core_1_pif_pms_constrain_world_1_world_controller:    2;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_8;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_0:    11;
-            uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_1:    11;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_9;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_rtcfast_world_0_l:    3;
-            uint32_t core_1_pif_pms_constrain_rtcfast_world_0_h:    3;
-            uint32_t core_1_pif_pms_constrain_rtcfast_world_1_l:    3;
-            uint32_t core_1_pif_pms_constrain_rtcfast_world_1_h:    3;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_10;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0:    11;
-            uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1:    11;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_11;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_rtcslow_0_world_0_l:    3;
-            uint32_t core_1_pif_pms_constrain_rtcslow_0_world_0_h:    3;
-            uint32_t core_1_pif_pms_constrain_rtcslow_0_world_1_l:    3;
-            uint32_t core_1_pif_pms_constrain_rtcslow_0_world_1_h:    3;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_12;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0:    11;
-            uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1:    11;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_13;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_constrain_rtcslow_1_world_0_l:    3;
-            uint32_t core_1_pif_pms_constrain_rtcslow_1_world_0_h:    3;
-            uint32_t core_1_pif_pms_constrain_rtcslow_1_world_1_l:    3;
-            uint32_t core_1_pif_pms_constrain_rtcslow_1_world_1_h:    3;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } core_1_pif_pms_constrain_14;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_0;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_world_0_area_0:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_1:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_2:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_3:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_4:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_5:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_6:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_7:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_8:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_9:    2;
-            uint32_t core_1_region_pms_constrain_world_0_area_10:    2;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_1;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_world_1_area_0:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_1:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_2:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_3:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_4:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_5:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_6:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_7:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_8:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_9:    2;
-            uint32_t core_1_region_pms_constrain_world_1_area_10:    2;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_2;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_0:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_3;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_1:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_4;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_2:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_5;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_3:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_6;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_4:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_7;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_5:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_8;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_6:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_9;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_7:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_10;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_8:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_11;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_9:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_12;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_10:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_13;
-    union {
-        struct {
-            uint32_t core_1_region_pms_constrain_addr_11:    30;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } core_1_region_pms_constrain_14;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_monitor_lock   :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_pif_pms_monitor_0;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_monitor_violate_clr:    1;
-            uint32_t core_1_pif_pms_monitor_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_1_pif_pms_monitor_1;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_monitor_violate_intr:    1;
-            uint32_t core_1_pif_pms_monitor_violate_status_hport_0:    1;
-            uint32_t core_1_pif_pms_monitor_violate_status_hsize:    3;
-            uint32_t core_1_pif_pms_monitor_violate_status_hwrite:    1;
-            uint32_t core_1_pif_pms_monitor_violate_status_hworld:    2;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } core_1_pif_pms_monitor_2;
-    uint32_t core_1_pif_pms_monitor_3;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_monitor_nonword_violate_clr:    1;
-            uint32_t core_1_pif_pms_monitor_nonword_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } core_1_pif_pms_monitor_4;
-    union {
-        struct {
-            uint32_t core_1_pif_pms_monitor_nonword_violate_intr:    1;
-            uint32_t core_1_pif_pms_monitor_nonword_violate_status_hsize:    2;
-            uint32_t core_1_pif_pms_monitor_nonword_violate_status_hworld:    2;
-            uint32_t reserved5                     :    27;
-        };
-        uint32_t val;
-    } core_1_pif_pms_monitor_5;
-    uint32_t core_1_pif_pms_monitor_6;
-    union {
-        struct {
-            uint32_t core_1_vecbase_override_lock  :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_vecbase_override_lock;
-    union {
-        struct {
-            uint32_t core_1_vecbase_world_mask     :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_vecbase_override_0;
-    union {
-        struct {
-            uint32_t core_1_vecbase_override_world0_value:    22;
-            uint32_t core_1_vecbase_override_sel   :    2;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } core_1_vecbase_override_1;
-    union {
-        struct {
-            uint32_t core_1_vecbase_override_world1_value:    22;
-            uint32_t reserved22                    :    10;
-        };
-        uint32_t val;
-    } core_1_vecbase_override_2;
-    union {
-        struct {
-            uint32_t core_1_toomanyexceptions_m_override_lock:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_toomanyexceptions_m_override_0;
-    union {
-        struct {
-            uint32_t core_1_toomanyexceptions_m_override:    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } core_1_toomanyexceptions_m_override_1;
-    union {
-        struct {
-            uint32_t backup_bus_pms_constrain_lock :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_0;
-    union {
-        struct {
-            uint32_t backup_bus_pms_constrain_uart :    2;
-            uint32_t backup_bus_pms_constrain_g0spi_1:    2;
-            uint32_t backup_bus_pms_constrain_g0spi_0:    2;
-            uint32_t backup_bus_pms_constrain_gpio :    2;
-            uint32_t backup_bus_pms_constrain_fe2  :    2;
-            uint32_t backup_bus_pms_constrain_fe   :    2;
-            uint32_t reserved12                    :    2;
-            uint32_t backup_bus_pms_constrain_rtc  :    2;
-            uint32_t backup_bus_pms_constrain_io_mux:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t backup_bus_pms_constrain_hinf :    2;
-            uint32_t reserved22                    :    2;
-            uint32_t backup_bus_pms_constrain_misc :    2;
-            uint32_t backup_bus_pms_constrain_i2c  :    2;
-            uint32_t backup_bus_pms_constrain_i2s0 :    2;
-            uint32_t backup_bus_pms_constrain_uart1:    2;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_1;
-    union {
-        struct {
-            uint32_t backup_bus_pms_constrain_bt   :    2;
-            uint32_t reserved2                     :    2;
-            uint32_t backup_bus_pms_constrain_i2c_ext0:    2;
-            uint32_t backup_bus_pms_constrain_uhci0:    2;
-            uint32_t backup_bus_pms_constrain_slchost:    2;
-            uint32_t backup_bus_pms_constrain_rmt  :    2;
-            uint32_t backup_bus_pms_constrain_pcnt :    2;
-            uint32_t backup_bus_pms_constrain_slc  :    2;
-            uint32_t backup_bus_pms_constrain_ledc :    2;
-            uint32_t backup_bus_pms_constrain_backup:    2;
-            uint32_t reserved20                    :    2;
-            uint32_t backup_bus_pms_constrain_bb   :    2;
-            uint32_t backup_bus_pms_constrain_pwm0 :    2;
-            uint32_t backup_bus_pms_constrain_timergroup:    2;
-            uint32_t backup_bus_pms_constrain_timergroup1:    2;
-            uint32_t backup_bus_pms_constrain_systimer:    2;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_2;
-    union {
-        struct {
-            uint32_t backup_bus_pms_constrain_spi_2:    2;
-            uint32_t backup_bus_pms_constrain_spi_3:    2;
-            uint32_t backup_bus_pms_constrain_apb_ctrl:    2;
-            uint32_t backup_bus_pms_constrain_i2c_ext1:    2;
-            uint32_t backup_bus_pms_constrain_sdio_host:    2;
-            uint32_t backup_bus_pms_constrain_can  :    2;
-            uint32_t backup_bus_pms_constrain_pwm1 :    2;
-            uint32_t backup_bus_pms_constrain_i2s1 :    2;
-            uint32_t backup_bus_pms_constrain_uart2:    2;
-            uint32_t reserved18                    :    2;
-            uint32_t reserved20                    :    2;
-            uint32_t backup_bus_pms_constrain_rwbt :    2;
-            uint32_t reserved24                    :    2;
-            uint32_t backup_bus_pms_constrain_wifimac:    2;
-            uint32_t backup_bus_pms_constrain_pwr  :    2;
-            uint32_t reserved30                    :    2;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_3;
-    union {
-        struct {
-            uint32_t backup_bus_pms_constrain_usb_device:    2;
-            uint32_t backup_bus_pms_constrain_usb_wrap:    2;
-            uint32_t backup_bus_pms_constrain_crypto_peri:    2;
-            uint32_t backup_bus_pms_constrain_crypto_dma:    2;
-            uint32_t backup_bus_pms_constrain_apb_adc:    2;
-            uint32_t backup_bus_pms_constrain_lcd_cam:    2;
-            uint32_t backup_bus_pms_constrain_bt_pwr:    2;
-            uint32_t backup_bus_pms_constrain_usb  :    2;
-            uint32_t backup_bus_pms_constrain_system:    2;
-            uint32_t backup_bus_pms_constrain_sensitive:    2;
-            uint32_t backup_bus_pms_constrain_interrupt:    2;
-            uint32_t backup_bus_pms_constrain_dma_copy:    2;
-            uint32_t backup_bus_pms_constrain_cache_config:    2;
-            uint32_t backup_bus_pms_constrain_ad   :    2;
-            uint32_t backup_bus_pms_constrain_dio  :    2;
-            uint32_t backup_bus_pms_constrain_world_controller:    2;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_4;
-    union {
-        struct {
-            uint32_t backup_bus_pms_constrain_rtcfast_spltaddr:    11;
-            uint32_t reserved11                    :    21;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_5;
-    union {
-        struct {
-            uint32_t backup_bus_pms_constrain_rtcfast_l:    3;
-            uint32_t backup_bus_pms_constrain_rtcfast_h:    3;
-            uint32_t reserved6                     :    26;
-        };
-        uint32_t val;
-    } backup_bus_pms_constrain_6;
-    union {
-        struct {
-            uint32_t backup_bus_pms_monitor_lock   :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } backup_bus_pms_monitor_0;
-    union {
-        struct {
-            uint32_t backup_bus_pms_monitor_violate_clr:    1;
-            uint32_t backup_bus_pms_monitor_violate_en:    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } backup_bus_pms_monitor_1;
-    union {
-        struct {
-            uint32_t backup_bus_pms_monitor_violate_intr:    1;
-            uint32_t backup_bus_pms_monitor_violate_status_htrans:    2;
-            uint32_t backup_bus_pms_monitor_violate_status_hsize:    3;
-            uint32_t backup_bus_pms_monitor_violate_status_hwrite:    1;
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } backup_bus_pms_monitor_2;
-    uint32_t backup_bus_pms_monitor_3;
-    union {
-        struct {
-            uint32_t edma_boundary_lock            :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_boundary_lock;
-    union {
-        struct {
-            uint32_t edma_boundary_0               :    14;
-            uint32_t reserved14                    :    18;
-        };
-        uint32_t val;
-    } edma_boundary_0;
-    union {
-        struct {
-            uint32_t edma_boundary_1               :    14;
-            uint32_t reserved14                    :    18;
-        };
-        uint32_t val;
-    } edma_boundary_1;
-    union {
-        struct {
-            uint32_t edma_boundary_2               :    14;
-            uint32_t reserved14                    :    18;
-        };
-        uint32_t val;
-    } edma_boundary_2;
-    union {
-        struct {
-            uint32_t edma_pms_spi2_lock            :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_spi2_lock;
-    union {
-        struct {
-            uint32_t edma_pms_spi2_attr1           :    2;
-            uint32_t edma_pms_spi2_attr2           :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_spi2;
-    union {
-        struct {
-            uint32_t edma_pms_spi3_lock            :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_spi3_lock;
-    union {
-        struct {
-            uint32_t edma_pms_spi3_attr1           :    2;
-            uint32_t edma_pms_spi3_attr2           :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_spi3;
-    union {
-        struct {
-            uint32_t edma_pms_uhci0_lock           :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_uhci0_lock;
-    union {
-        struct {
-            uint32_t edma_pms_uhci0_attr1          :    2;
-            uint32_t edma_pms_uhci0_attr2          :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_uhci0;
-    union {
-        struct {
-            uint32_t edma_pms_i2s0_lock            :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_i2s0_lock;
-    union {
-        struct {
-            uint32_t edma_pms_i2s0_attr1           :    2;
-            uint32_t edma_pms_i2s0_attr2           :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_i2s0;
-    union {
-        struct {
-            uint32_t edma_pms_i2s1_lock            :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_i2s1_lock;
-    union {
-        struct {
-            uint32_t edma_pms_i2s1_attr1           :    2;
-            uint32_t edma_pms_i2s1_attr2           :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_i2s1;
-    union {
-        struct {
-            uint32_t edma_pms_lcd_cam_lock         :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_lcd_cam_lock;
-    union {
-        struct {
-            uint32_t edma_pms_lcd_cam_attr1        :    2;
-            uint32_t edma_pms_lcd_cam_attr2        :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_lcd_cam;
-    union {
-        struct {
-            uint32_t edma_pms_aes_lock             :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_aes_lock;
-    union {
-        struct {
-            uint32_t edma_pms_aes_attr1            :    2;
-            uint32_t edma_pms_aes_attr2            :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_aes;
-    union {
-        struct {
-            uint32_t edma_pms_sha_lock             :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_sha_lock;
-    union {
-        struct {
-            uint32_t edma_pms_sha_attr1            :    2;
-            uint32_t edma_pms_sha_attr2            :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_sha;
-    union {
-        struct {
-            uint32_t edma_pms_adc_dac_lock         :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_adc_dac_lock;
-    union {
-        struct {
-            uint32_t edma_pms_adc_dac_attr1        :    2;
-            uint32_t edma_pms_adc_dac_attr2        :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_adc_dac;
-    union {
-        struct {
-            uint32_t edma_pms_rmt_lock             :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } edma_pms_rmt_lock;
-    union {
-        struct {
-            uint32_t edma_pms_rmt_attr1            :    2;
-            uint32_t edma_pms_rmt_attr2            :    2;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } edma_pms_rmt;
-    union {
-        struct {
-            uint32_t reg_clk_en                    :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } clock_gate;
-    union {
-        struct {
-            uint32_t dis_rtc_cpu                   :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } rtc_pms;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    uint32_t reserved_3fc;
-    uint32_t reserved_400;
-    uint32_t reserved_404;
-    uint32_t reserved_408;
-    uint32_t reserved_40c;
-    uint32_t reserved_410;
-    uint32_t reserved_414;
-    uint32_t reserved_418;
-    uint32_t reserved_41c;
-    uint32_t reserved_420;
-    uint32_t reserved_424;
-    uint32_t reserved_428;
-    uint32_t reserved_42c;
-    uint32_t reserved_430;
-    uint32_t reserved_434;
-    uint32_t reserved_438;
-    uint32_t reserved_43c;
-    uint32_t reserved_440;
-    uint32_t reserved_444;
-    uint32_t reserved_448;
-    uint32_t reserved_44c;
-    uint32_t reserved_450;
-    uint32_t reserved_454;
-    uint32_t reserved_458;
-    uint32_t reserved_45c;
-    uint32_t reserved_460;
-    uint32_t reserved_464;
-    uint32_t reserved_468;
-    uint32_t reserved_46c;
-    uint32_t reserved_470;
-    uint32_t reserved_474;
-    uint32_t reserved_478;
-    uint32_t reserved_47c;
-    uint32_t reserved_480;
-    uint32_t reserved_484;
-    uint32_t reserved_488;
-    uint32_t reserved_48c;
-    uint32_t reserved_490;
-    uint32_t reserved_494;
-    uint32_t reserved_498;
-    uint32_t reserved_49c;
-    uint32_t reserved_4a0;
-    uint32_t reserved_4a4;
-    uint32_t reserved_4a8;
-    uint32_t reserved_4ac;
-    uint32_t reserved_4b0;
-    uint32_t reserved_4b4;
-    uint32_t reserved_4b8;
-    uint32_t reserved_4bc;
-    uint32_t reserved_4c0;
-    uint32_t reserved_4c4;
-    uint32_t reserved_4c8;
-    uint32_t reserved_4cc;
-    uint32_t reserved_4d0;
-    uint32_t reserved_4d4;
-    uint32_t reserved_4d8;
-    uint32_t reserved_4dc;
-    uint32_t reserved_4e0;
-    uint32_t reserved_4e4;
-    uint32_t reserved_4e8;
-    uint32_t reserved_4ec;
-    uint32_t reserved_4f0;
-    uint32_t reserved_4f4;
-    uint32_t reserved_4f8;
-    uint32_t reserved_4fc;
-    uint32_t reserved_500;
-    uint32_t reserved_504;
-    uint32_t reserved_508;
-    uint32_t reserved_50c;
-    uint32_t reserved_510;
-    uint32_t reserved_514;
-    uint32_t reserved_518;
-    uint32_t reserved_51c;
-    uint32_t reserved_520;
-    uint32_t reserved_524;
-    uint32_t reserved_528;
-    uint32_t reserved_52c;
-    uint32_t reserved_530;
-    uint32_t reserved_534;
-    uint32_t reserved_538;
-    uint32_t reserved_53c;
-    uint32_t reserved_540;
-    uint32_t reserved_544;
-    uint32_t reserved_548;
-    uint32_t reserved_54c;
-    uint32_t reserved_550;
-    uint32_t reserved_554;
-    uint32_t reserved_558;
-    uint32_t reserved_55c;
-    uint32_t reserved_560;
-    uint32_t reserved_564;
-    uint32_t reserved_568;
-    uint32_t reserved_56c;
-    uint32_t reserved_570;
-    uint32_t reserved_574;
-    uint32_t reserved_578;
-    uint32_t reserved_57c;
-    uint32_t reserved_580;
-    uint32_t reserved_584;
-    uint32_t reserved_588;
-    uint32_t reserved_58c;
-    uint32_t reserved_590;
-    uint32_t reserved_594;
-    uint32_t reserved_598;
-    uint32_t reserved_59c;
-    uint32_t reserved_5a0;
-    uint32_t reserved_5a4;
-    uint32_t reserved_5a8;
-    uint32_t reserved_5ac;
-    uint32_t reserved_5b0;
-    uint32_t reserved_5b4;
-    uint32_t reserved_5b8;
-    uint32_t reserved_5bc;
-    uint32_t reserved_5c0;
-    uint32_t reserved_5c4;
-    uint32_t reserved_5c8;
-    uint32_t reserved_5cc;
-    uint32_t reserved_5d0;
-    uint32_t reserved_5d4;
-    uint32_t reserved_5d8;
-    uint32_t reserved_5dc;
-    uint32_t reserved_5e0;
-    uint32_t reserved_5e4;
-    uint32_t reserved_5e8;
-    uint32_t reserved_5ec;
-    uint32_t reserved_5f0;
-    uint32_t reserved_5f4;
-    uint32_t reserved_5f8;
-    uint32_t reserved_5fc;
-    uint32_t reserved_600;
-    uint32_t reserved_604;
-    uint32_t reserved_608;
-    uint32_t reserved_60c;
-    uint32_t reserved_610;
-    uint32_t reserved_614;
-    uint32_t reserved_618;
-    uint32_t reserved_61c;
-    uint32_t reserved_620;
-    uint32_t reserved_624;
-    uint32_t reserved_628;
-    uint32_t reserved_62c;
-    uint32_t reserved_630;
-    uint32_t reserved_634;
-    uint32_t reserved_638;
-    uint32_t reserved_63c;
-    uint32_t reserved_640;
-    uint32_t reserved_644;
-    uint32_t reserved_648;
-    uint32_t reserved_64c;
-    uint32_t reserved_650;
-    uint32_t reserved_654;
-    uint32_t reserved_658;
-    uint32_t reserved_65c;
-    uint32_t reserved_660;
-    uint32_t reserved_664;
-    uint32_t reserved_668;
-    uint32_t reserved_66c;
-    uint32_t reserved_670;
-    uint32_t reserved_674;
-    uint32_t reserved_678;
-    uint32_t reserved_67c;
-    uint32_t reserved_680;
-    uint32_t reserved_684;
-    uint32_t reserved_688;
-    uint32_t reserved_68c;
-    uint32_t reserved_690;
-    uint32_t reserved_694;
-    uint32_t reserved_698;
-    uint32_t reserved_69c;
-    uint32_t reserved_6a0;
-    uint32_t reserved_6a4;
-    uint32_t reserved_6a8;
-    uint32_t reserved_6ac;
-    uint32_t reserved_6b0;
-    uint32_t reserved_6b4;
-    uint32_t reserved_6b8;
-    uint32_t reserved_6bc;
-    uint32_t reserved_6c0;
-    uint32_t reserved_6c4;
-    uint32_t reserved_6c8;
-    uint32_t reserved_6cc;
-    uint32_t reserved_6d0;
-    uint32_t reserved_6d4;
-    uint32_t reserved_6d8;
-    uint32_t reserved_6dc;
-    uint32_t reserved_6e0;
-    uint32_t reserved_6e4;
-    uint32_t reserved_6e8;
-    uint32_t reserved_6ec;
-    uint32_t reserved_6f0;
-    uint32_t reserved_6f4;
-    uint32_t reserved_6f8;
-    uint32_t reserved_6fc;
-    uint32_t reserved_700;
-    uint32_t reserved_704;
-    uint32_t reserved_708;
-    uint32_t reserved_70c;
-    uint32_t reserved_710;
-    uint32_t reserved_714;
-    uint32_t reserved_718;
-    uint32_t reserved_71c;
-    uint32_t reserved_720;
-    uint32_t reserved_724;
-    uint32_t reserved_728;
-    uint32_t reserved_72c;
-    uint32_t reserved_730;
-    uint32_t reserved_734;
-    uint32_t reserved_738;
-    uint32_t reserved_73c;
-    uint32_t reserved_740;
-    uint32_t reserved_744;
-    uint32_t reserved_748;
-    uint32_t reserved_74c;
-    uint32_t reserved_750;
-    uint32_t reserved_754;
-    uint32_t reserved_758;
-    uint32_t reserved_75c;
-    uint32_t reserved_760;
-    uint32_t reserved_764;
-    uint32_t reserved_768;
-    uint32_t reserved_76c;
-    uint32_t reserved_770;
-    uint32_t reserved_774;
-    uint32_t reserved_778;
-    uint32_t reserved_77c;
-    uint32_t reserved_780;
-    uint32_t reserved_784;
-    uint32_t reserved_788;
-    uint32_t reserved_78c;
-    uint32_t reserved_790;
-    uint32_t reserved_794;
-    uint32_t reserved_798;
-    uint32_t reserved_79c;
-    uint32_t reserved_7a0;
-    uint32_t reserved_7a4;
-    uint32_t reserved_7a8;
-    uint32_t reserved_7ac;
-    uint32_t reserved_7b0;
-    uint32_t reserved_7b4;
-    uint32_t reserved_7b8;
-    uint32_t reserved_7bc;
-    uint32_t reserved_7c0;
-    uint32_t reserved_7c4;
-    uint32_t reserved_7c8;
-    uint32_t reserved_7cc;
-    uint32_t reserved_7d0;
-    uint32_t reserved_7d4;
-    uint32_t reserved_7d8;
-    uint32_t reserved_7dc;
-    uint32_t reserved_7e0;
-    uint32_t reserved_7e4;
-    uint32_t reserved_7e8;
-    uint32_t reserved_7ec;
-    uint32_t reserved_7f0;
-    uint32_t reserved_7f4;
-    uint32_t reserved_7f8;
-    uint32_t reserved_7fc;
-    uint32_t reserved_800;
-    uint32_t reserved_804;
-    uint32_t reserved_808;
-    uint32_t reserved_80c;
-    uint32_t reserved_810;
-    uint32_t reserved_814;
-    uint32_t reserved_818;
-    uint32_t reserved_81c;
-    uint32_t reserved_820;
-    uint32_t reserved_824;
-    uint32_t reserved_828;
-    uint32_t reserved_82c;
-    uint32_t reserved_830;
-    uint32_t reserved_834;
-    uint32_t reserved_838;
-    uint32_t reserved_83c;
-    uint32_t reserved_840;
-    uint32_t reserved_844;
-    uint32_t reserved_848;
-    uint32_t reserved_84c;
-    uint32_t reserved_850;
-    uint32_t reserved_854;
-    uint32_t reserved_858;
-    uint32_t reserved_85c;
-    uint32_t reserved_860;
-    uint32_t reserved_864;
-    uint32_t reserved_868;
-    uint32_t reserved_86c;
-    uint32_t reserved_870;
-    uint32_t reserved_874;
-    uint32_t reserved_878;
-    uint32_t reserved_87c;
-    uint32_t reserved_880;
-    uint32_t reserved_884;
-    uint32_t reserved_888;
-    uint32_t reserved_88c;
-    uint32_t reserved_890;
-    uint32_t reserved_894;
-    uint32_t reserved_898;
-    uint32_t reserved_89c;
-    uint32_t reserved_8a0;
-    uint32_t reserved_8a4;
-    uint32_t reserved_8a8;
-    uint32_t reserved_8ac;
-    uint32_t reserved_8b0;
-    uint32_t reserved_8b4;
-    uint32_t reserved_8b8;
-    uint32_t reserved_8bc;
-    uint32_t reserved_8c0;
-    uint32_t reserved_8c4;
-    uint32_t reserved_8c8;
-    uint32_t reserved_8cc;
-    uint32_t reserved_8d0;
-    uint32_t reserved_8d4;
-    uint32_t reserved_8d8;
-    uint32_t reserved_8dc;
-    uint32_t reserved_8e0;
-    uint32_t reserved_8e4;
-    uint32_t reserved_8e8;
-    uint32_t reserved_8ec;
-    uint32_t reserved_8f0;
-    uint32_t reserved_8f4;
-    uint32_t reserved_8f8;
-    uint32_t reserved_8fc;
-    uint32_t reserved_900;
-    uint32_t reserved_904;
-    uint32_t reserved_908;
-    uint32_t reserved_90c;
-    uint32_t reserved_910;
-    uint32_t reserved_914;
-    uint32_t reserved_918;
-    uint32_t reserved_91c;
-    uint32_t reserved_920;
-    uint32_t reserved_924;
-    uint32_t reserved_928;
-    uint32_t reserved_92c;
-    uint32_t reserved_930;
-    uint32_t reserved_934;
-    uint32_t reserved_938;
-    uint32_t reserved_93c;
-    uint32_t reserved_940;
-    uint32_t reserved_944;
-    uint32_t reserved_948;
-    uint32_t reserved_94c;
-    uint32_t reserved_950;
-    uint32_t reserved_954;
-    uint32_t reserved_958;
-    uint32_t reserved_95c;
-    uint32_t reserved_960;
-    uint32_t reserved_964;
-    uint32_t reserved_968;
-    uint32_t reserved_96c;
-    uint32_t reserved_970;
-    uint32_t reserved_974;
-    uint32_t reserved_978;
-    uint32_t reserved_97c;
-    uint32_t reserved_980;
-    uint32_t reserved_984;
-    uint32_t reserved_988;
-    uint32_t reserved_98c;
-    uint32_t reserved_990;
-    uint32_t reserved_994;
-    uint32_t reserved_998;
-    uint32_t reserved_99c;
-    uint32_t reserved_9a0;
-    uint32_t reserved_9a4;
-    uint32_t reserved_9a8;
-    uint32_t reserved_9ac;
-    uint32_t reserved_9b0;
-    uint32_t reserved_9b4;
-    uint32_t reserved_9b8;
-    uint32_t reserved_9bc;
-    uint32_t reserved_9c0;
-    uint32_t reserved_9c4;
-    uint32_t reserved_9c8;
-    uint32_t reserved_9cc;
-    uint32_t reserved_9d0;
-    uint32_t reserved_9d4;
-    uint32_t reserved_9d8;
-    uint32_t reserved_9dc;
-    uint32_t reserved_9e0;
-    uint32_t reserved_9e4;
-    uint32_t reserved_9e8;
-    uint32_t reserved_9ec;
-    uint32_t reserved_9f0;
-    uint32_t reserved_9f4;
-    uint32_t reserved_9f8;
-    uint32_t reserved_9fc;
-    uint32_t reserved_a00;
-    uint32_t reserved_a04;
-    uint32_t reserved_a08;
-    uint32_t reserved_a0c;
-    uint32_t reserved_a10;
-    uint32_t reserved_a14;
-    uint32_t reserved_a18;
-    uint32_t reserved_a1c;
-    uint32_t reserved_a20;
-    uint32_t reserved_a24;
-    uint32_t reserved_a28;
-    uint32_t reserved_a2c;
-    uint32_t reserved_a30;
-    uint32_t reserved_a34;
-    uint32_t reserved_a38;
-    uint32_t reserved_a3c;
-    uint32_t reserved_a40;
-    uint32_t reserved_a44;
-    uint32_t reserved_a48;
-    uint32_t reserved_a4c;
-    uint32_t reserved_a50;
-    uint32_t reserved_a54;
-    uint32_t reserved_a58;
-    uint32_t reserved_a5c;
-    uint32_t reserved_a60;
-    uint32_t reserved_a64;
-    uint32_t reserved_a68;
-    uint32_t reserved_a6c;
-    uint32_t reserved_a70;
-    uint32_t reserved_a74;
-    uint32_t reserved_a78;
-    uint32_t reserved_a7c;
-    uint32_t reserved_a80;
-    uint32_t reserved_a84;
-    uint32_t reserved_a88;
-    uint32_t reserved_a8c;
-    uint32_t reserved_a90;
-    uint32_t reserved_a94;
-    uint32_t reserved_a98;
-    uint32_t reserved_a9c;
-    uint32_t reserved_aa0;
-    uint32_t reserved_aa4;
-    uint32_t reserved_aa8;
-    uint32_t reserved_aac;
-    uint32_t reserved_ab0;
-    uint32_t reserved_ab4;
-    uint32_t reserved_ab8;
-    uint32_t reserved_abc;
-    uint32_t reserved_ac0;
-    uint32_t reserved_ac4;
-    uint32_t reserved_ac8;
-    uint32_t reserved_acc;
-    uint32_t reserved_ad0;
-    uint32_t reserved_ad4;
-    uint32_t reserved_ad8;
-    uint32_t reserved_adc;
-    uint32_t reserved_ae0;
-    uint32_t reserved_ae4;
-    uint32_t reserved_ae8;
-    uint32_t reserved_aec;
-    uint32_t reserved_af0;
-    uint32_t reserved_af4;
-    uint32_t reserved_af8;
-    uint32_t reserved_afc;
-    uint32_t reserved_b00;
-    uint32_t reserved_b04;
-    uint32_t reserved_b08;
-    uint32_t reserved_b0c;
-    uint32_t reserved_b10;
-    uint32_t reserved_b14;
-    uint32_t reserved_b18;
-    uint32_t reserved_b1c;
-    uint32_t reserved_b20;
-    uint32_t reserved_b24;
-    uint32_t reserved_b28;
-    uint32_t reserved_b2c;
-    uint32_t reserved_b30;
-    uint32_t reserved_b34;
-    uint32_t reserved_b38;
-    uint32_t reserved_b3c;
-    uint32_t reserved_b40;
-    uint32_t reserved_b44;
-    uint32_t reserved_b48;
-    uint32_t reserved_b4c;
-    uint32_t reserved_b50;
-    uint32_t reserved_b54;
-    uint32_t reserved_b58;
-    uint32_t reserved_b5c;
-    uint32_t reserved_b60;
-    uint32_t reserved_b64;
-    uint32_t reserved_b68;
-    uint32_t reserved_b6c;
-    uint32_t reserved_b70;
-    uint32_t reserved_b74;
-    uint32_t reserved_b78;
-    uint32_t reserved_b7c;
-    uint32_t reserved_b80;
-    uint32_t reserved_b84;
-    uint32_t reserved_b88;
-    uint32_t reserved_b8c;
-    uint32_t reserved_b90;
-    uint32_t reserved_b94;
-    uint32_t reserved_b98;
-    uint32_t reserved_b9c;
-    uint32_t reserved_ba0;
-    uint32_t reserved_ba4;
-    uint32_t reserved_ba8;
-    uint32_t reserved_bac;
-    uint32_t reserved_bb0;
-    uint32_t reserved_bb4;
-    uint32_t reserved_bb8;
-    uint32_t reserved_bbc;
-    uint32_t reserved_bc0;
-    uint32_t reserved_bc4;
-    uint32_t reserved_bc8;
-    uint32_t reserved_bcc;
-    uint32_t reserved_bd0;
-    uint32_t reserved_bd4;
-    uint32_t reserved_bd8;
-    uint32_t reserved_bdc;
-    uint32_t reserved_be0;
-    uint32_t reserved_be4;
-    uint32_t reserved_be8;
-    uint32_t reserved_bec;
-    uint32_t reserved_bf0;
-    uint32_t reserved_bf4;
-    uint32_t reserved_bf8;
-    uint32_t reserved_bfc;
-    uint32_t reserved_c00;
-    uint32_t reserved_c04;
-    uint32_t reserved_c08;
-    uint32_t reserved_c0c;
-    uint32_t reserved_c10;
-    uint32_t reserved_c14;
-    uint32_t reserved_c18;
-    uint32_t reserved_c1c;
-    uint32_t reserved_c20;
-    uint32_t reserved_c24;
-    uint32_t reserved_c28;
-    uint32_t reserved_c2c;
-    uint32_t reserved_c30;
-    uint32_t reserved_c34;
-    uint32_t reserved_c38;
-    uint32_t reserved_c3c;
-    uint32_t reserved_c40;
-    uint32_t reserved_c44;
-    uint32_t reserved_c48;
-    uint32_t reserved_c4c;
-    uint32_t reserved_c50;
-    uint32_t reserved_c54;
-    uint32_t reserved_c58;
-    uint32_t reserved_c5c;
-    uint32_t reserved_c60;
-    uint32_t reserved_c64;
-    uint32_t reserved_c68;
-    uint32_t reserved_c6c;
-    uint32_t reserved_c70;
-    uint32_t reserved_c74;
-    uint32_t reserved_c78;
-    uint32_t reserved_c7c;
-    uint32_t reserved_c80;
-    uint32_t reserved_c84;
-    uint32_t reserved_c88;
-    uint32_t reserved_c8c;
-    uint32_t reserved_c90;
-    uint32_t reserved_c94;
-    uint32_t reserved_c98;
-    uint32_t reserved_c9c;
-    uint32_t reserved_ca0;
-    uint32_t reserved_ca4;
-    uint32_t reserved_ca8;
-    uint32_t reserved_cac;
-    uint32_t reserved_cb0;
-    uint32_t reserved_cb4;
-    uint32_t reserved_cb8;
-    uint32_t reserved_cbc;
-    uint32_t reserved_cc0;
-    uint32_t reserved_cc4;
-    uint32_t reserved_cc8;
-    uint32_t reserved_ccc;
-    uint32_t reserved_cd0;
-    uint32_t reserved_cd4;
-    uint32_t reserved_cd8;
-    uint32_t reserved_cdc;
-    uint32_t reserved_ce0;
-    uint32_t reserved_ce4;
-    uint32_t reserved_ce8;
-    uint32_t reserved_cec;
-    uint32_t reserved_cf0;
-    uint32_t reserved_cf4;
-    uint32_t reserved_cf8;
-    uint32_t reserved_cfc;
-    uint32_t reserved_d00;
-    uint32_t reserved_d04;
-    uint32_t reserved_d08;
-    uint32_t reserved_d0c;
-    uint32_t reserved_d10;
-    uint32_t reserved_d14;
-    uint32_t reserved_d18;
-    uint32_t reserved_d1c;
-    uint32_t reserved_d20;
-    uint32_t reserved_d24;
-    uint32_t reserved_d28;
-    uint32_t reserved_d2c;
-    uint32_t reserved_d30;
-    uint32_t reserved_d34;
-    uint32_t reserved_d38;
-    uint32_t reserved_d3c;
-    uint32_t reserved_d40;
-    uint32_t reserved_d44;
-    uint32_t reserved_d48;
-    uint32_t reserved_d4c;
-    uint32_t reserved_d50;
-    uint32_t reserved_d54;
-    uint32_t reserved_d58;
-    uint32_t reserved_d5c;
-    uint32_t reserved_d60;
-    uint32_t reserved_d64;
-    uint32_t reserved_d68;
-    uint32_t reserved_d6c;
-    uint32_t reserved_d70;
-    uint32_t reserved_d74;
-    uint32_t reserved_d78;
-    uint32_t reserved_d7c;
-    uint32_t reserved_d80;
-    uint32_t reserved_d84;
-    uint32_t reserved_d88;
-    uint32_t reserved_d8c;
-    uint32_t reserved_d90;
-    uint32_t reserved_d94;
-    uint32_t reserved_d98;
-    uint32_t reserved_d9c;
-    uint32_t reserved_da0;
-    uint32_t reserved_da4;
-    uint32_t reserved_da8;
-    uint32_t reserved_dac;
-    uint32_t reserved_db0;
-    uint32_t reserved_db4;
-    uint32_t reserved_db8;
-    uint32_t reserved_dbc;
-    uint32_t reserved_dc0;
-    uint32_t reserved_dc4;
-    uint32_t reserved_dc8;
-    uint32_t reserved_dcc;
-    uint32_t reserved_dd0;
-    uint32_t reserved_dd4;
-    uint32_t reserved_dd8;
-    uint32_t reserved_ddc;
-    uint32_t reserved_de0;
-    uint32_t reserved_de4;
-    uint32_t reserved_de8;
-    uint32_t reserved_dec;
-    uint32_t reserved_df0;
-    uint32_t reserved_df4;
-    uint32_t reserved_df8;
-    uint32_t reserved_dfc;
-    uint32_t reserved_e00;
-    uint32_t reserved_e04;
-    uint32_t reserved_e08;
-    uint32_t reserved_e0c;
-    uint32_t reserved_e10;
-    uint32_t reserved_e14;
-    uint32_t reserved_e18;
-    uint32_t reserved_e1c;
-    uint32_t reserved_e20;
-    uint32_t reserved_e24;
-    uint32_t reserved_e28;
-    uint32_t reserved_e2c;
-    uint32_t reserved_e30;
-    uint32_t reserved_e34;
-    uint32_t reserved_e38;
-    uint32_t reserved_e3c;
-    uint32_t reserved_e40;
-    uint32_t reserved_e44;
-    uint32_t reserved_e48;
-    uint32_t reserved_e4c;
-    uint32_t reserved_e50;
-    uint32_t reserved_e54;
-    uint32_t reserved_e58;
-    uint32_t reserved_e5c;
-    uint32_t reserved_e60;
-    uint32_t reserved_e64;
-    uint32_t reserved_e68;
-    uint32_t reserved_e6c;
-    uint32_t reserved_e70;
-    uint32_t reserved_e74;
-    uint32_t reserved_e78;
-    uint32_t reserved_e7c;
-    uint32_t reserved_e80;
-    uint32_t reserved_e84;
-    uint32_t reserved_e88;
-    uint32_t reserved_e8c;
-    uint32_t reserved_e90;
-    uint32_t reserved_e94;
-    uint32_t reserved_e98;
-    uint32_t reserved_e9c;
-    uint32_t reserved_ea0;
-    uint32_t reserved_ea4;
-    uint32_t reserved_ea8;
-    uint32_t reserved_eac;
-    uint32_t reserved_eb0;
-    uint32_t reserved_eb4;
-    uint32_t reserved_eb8;
-    uint32_t reserved_ebc;
-    uint32_t reserved_ec0;
-    uint32_t reserved_ec4;
-    uint32_t reserved_ec8;
-    uint32_t reserved_ecc;
-    uint32_t reserved_ed0;
-    uint32_t reserved_ed4;
-    uint32_t reserved_ed8;
-    uint32_t reserved_edc;
-    uint32_t reserved_ee0;
-    uint32_t reserved_ee4;
-    uint32_t reserved_ee8;
-    uint32_t reserved_eec;
-    uint32_t reserved_ef0;
-    uint32_t reserved_ef4;
-    uint32_t reserved_ef8;
-    uint32_t reserved_efc;
-    uint32_t reserved_f00;
-    uint32_t reserved_f04;
-    uint32_t reserved_f08;
-    uint32_t reserved_f0c;
-    uint32_t reserved_f10;
-    uint32_t reserved_f14;
-    uint32_t reserved_f18;
-    uint32_t reserved_f1c;
-    uint32_t reserved_f20;
-    uint32_t reserved_f24;
-    uint32_t reserved_f28;
-    uint32_t reserved_f2c;
-    uint32_t reserved_f30;
-    uint32_t reserved_f34;
-    uint32_t reserved_f38;
-    uint32_t reserved_f3c;
-    uint32_t reserved_f40;
-    uint32_t reserved_f44;
-    uint32_t reserved_f48;
-    uint32_t reserved_f4c;
-    uint32_t reserved_f50;
-    uint32_t reserved_f54;
-    uint32_t reserved_f58;
-    uint32_t reserved_f5c;
-    uint32_t reserved_f60;
-    uint32_t reserved_f64;
-    uint32_t reserved_f68;
-    uint32_t reserved_f6c;
-    uint32_t reserved_f70;
-    uint32_t reserved_f74;
-    uint32_t reserved_f78;
-    uint32_t reserved_f7c;
-    uint32_t reserved_f80;
-    uint32_t reserved_f84;
-    uint32_t reserved_f88;
-    uint32_t reserved_f8c;
-    uint32_t reserved_f90;
-    uint32_t reserved_f94;
-    uint32_t reserved_f98;
-    uint32_t reserved_f9c;
-    uint32_t reserved_fa0;
-    uint32_t reserved_fa4;
-    uint32_t reserved_fa8;
-    uint32_t reserved_fac;
-    uint32_t reserved_fb0;
-    uint32_t reserved_fb4;
-    uint32_t reserved_fb8;
-    uint32_t reserved_fbc;
-    uint32_t reserved_fc0;
-    uint32_t reserved_fc4;
-    uint32_t reserved_fc8;
-    uint32_t reserved_fcc;
-    uint32_t reserved_fd0;
-    uint32_t reserved_fd4;
-    uint32_t reserved_fd8;
-    uint32_t reserved_fdc;
-    uint32_t reserved_fe0;
-    uint32_t reserved_fe4;
-    uint32_t reserved_fe8;
-    uint32_t reserved_fec;
-    uint32_t reserved_ff0;
-    uint32_t reserved_ff4;
-    uint32_t reserved_ff8;
-    union {
-        struct {
-            uint32_t sensitive_reg_date            :    28;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } reg_date;
-} sensitive_dev_t;
-extern sensitive_dev_t SENSITIVE;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SENSITIVE_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h
index 056c6d9f4e5..78a29ee2c30 100644
--- a/components/soc/esp32s3/include/soc/soc.h
+++ b/components/soc/esp32s3/include/soc/soc.h
@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 #define APP_CPU_NUM (1)
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index aef115bfe30..fc00755fa0e 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -219,6 +219,7 @@
 #define SOC_I2C_SUPPORT_10BIT_ADDR  (1)
 #define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
 #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_NUM                 (2U)
@@ -236,6 +237,7 @@
 /*-------------------------- LEDC CAPS ---------------------------------------*/
 #define SOC_LEDC_SUPPORT_APB_CLOCK       (1)
 #define SOC_LEDC_SUPPORT_XTAL_CLOCK      (1)
+#define SOC_LEDC_TIMER_NUM               (4)
 #define SOC_LEDC_CHANNEL_NUM             (8)
 #define SOC_LEDC_TIMER_BIT_WIDTH         (14)
 #define SOC_LEDC_SUPPORT_FADE_STOP       (1)
@@ -384,6 +386,7 @@
 #define SOC_TOUCH_SUPPORT_SLEEP_WAKEUP               (1)  /*!< Touch sensor supports sleep awake */
 #define SOC_TOUCH_SUPPORT_WATERPROOF                (1)  /*!< Touch sensor supports waterproof */
 #define SOC_TOUCH_SUPPORT_PROX_SENSING              (1)  /*!< Touch sensor supports proximity sensing */
+#define SOC_TOUCH_SUPPORT_DENOISE_CHAN              (1)  /*!< Touch sensor supports denoise channel */
 #define SOC_TOUCH_PROXIMITY_CHANNEL_NUM             (3)  /*!< Support touch proximity sensing channel number. */
 #define SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED     (1)  /*!< Support touch proximity sensing measure done interrupt type. */
 
@@ -482,6 +485,8 @@
 
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 
+#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2           (1)     /*!< Support XTAL_D2 clock as the LP_FAST clock source */
+
 /*-------------------------- eFuse CAPS----------------------------*/
 #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
 #define SOC_EFUSE_DIS_DOWNLOAD_DCACHE 1
diff --git a/components/soc/esp32s3/include/soc/spi_mem_reg.h b/components/soc/esp32s3/include/soc/spi_mem_reg.h
deleted file mode 100644
index aa4639ed8d8..00000000000
--- a/components/soc/esp32s3/include/soc/spi_mem_reg.h
+++ /dev/null
@@ -1,2241 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SPI_MEM_REG_H_
-#define _SOC_SPI_MEM_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
-/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done. 1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_READ    (BIT(31))
-#define SPI_MEM_FLASH_READ_M  (BIT(31))
-#define SPI_MEM_FLASH_READ_V  0x1
-#define SPI_MEM_FLASH_READ_S  31
-/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
-bit will be cleared once the operation done. 1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_WREN    (BIT(30))
-#define SPI_MEM_FLASH_WREN_M  (BIT(30))
-#define SPI_MEM_FLASH_WREN_V  0x1
-#define SPI_MEM_FLASH_WREN_S  30
-/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Write flash disable. Write disable command will be sent when the bit is set. The
- bit will be cleared once the operation done. 1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_WRDI    (BIT(29))
-#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
-#define SPI_MEM_FLASH_WRDI_V  0x1
-#define SPI_MEM_FLASH_WRDI_S  29
-/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
-e cleared once the operation done. 1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_RDID    (BIT(28))
-#define SPI_MEM_FLASH_RDID_M  (BIT(28))
-#define SPI_MEM_FLASH_RDID_V  0x1
-#define SPI_MEM_FLASH_RDID_S  28
-/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Read status register-1.  Read status operation will be triggered when the bit is
- set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_RDSR    (BIT(27))
-#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
-#define SPI_MEM_FLASH_RDSR_V  0x1
-#define SPI_MEM_FLASH_RDSR_S  27
-/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Write status register enable.   Write status operation  will be triggered when t
-he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
-ble. .*/
-#define SPI_MEM_FLASH_WRSR    (BIT(26))
-#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
-#define SPI_MEM_FLASH_WRSR_V  0x1
-#define SPI_MEM_FLASH_WRSR_S  26
-/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Page program enable(1 byte ~64 bytes data to be programmed). Page program operat
-ion  will be triggered when the bit is set. The bit will be cleared once the ope
-ration done .1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_PP    (BIT(25))
-#define SPI_MEM_FLASH_PP_M  (BIT(25))
-#define SPI_MEM_FLASH_PP_V  0x1
-#define SPI_MEM_FLASH_PP_S  25
-/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
-is set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_SE    (BIT(24))
-#define SPI_MEM_FLASH_SE_M  (BIT(24))
-#define SPI_MEM_FLASH_SE_V  0x1
-#define SPI_MEM_FLASH_SE_S  24
-/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
- is set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_BE    (BIT(23))
-#define SPI_MEM_FLASH_BE_M  (BIT(23))
-#define SPI_MEM_FLASH_BE_V  0x1
-#define SPI_MEM_FLASH_BE_S  23
-/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
-he bit will be cleared once the operation done.1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_CE    (BIT(22))
-#define SPI_MEM_FLASH_CE_M  (BIT(22))
-#define SPI_MEM_FLASH_CE_V  0x1
-#define SPI_MEM_FLASH_CE_S  22
-/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
-. The bit will be cleared once the operation done.1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_DP    (BIT(21))
-#define SPI_MEM_FLASH_DP_M  (BIT(21))
-#define SPI_MEM_FLASH_DP_V  0x1
-#define SPI_MEM_FLASH_DP_S  21
-/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
-/*description: This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down
-state or high performance mode and obtains the devices ID. The bit will be clear
-ed once the operation done.1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_RES    (BIT(20))
-#define SPI_MEM_FLASH_RES_M  (BIT(20))
-#define SPI_MEM_FLASH_RES_V  0x1
-#define SPI_MEM_FLASH_RES_S  20
-/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
-/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
-ion done.1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_HPM    (BIT(19))
-#define SPI_MEM_FLASH_HPM_M  (BIT(19))
-#define SPI_MEM_FLASH_HPM_V  0x1
-#define SPI_MEM_FLASH_HPM_S  19
-/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
-/*description: User define command enable.  An operation will be triggered when the bit is set.
- The bit will be cleared once the operation done.1: enable 0: disable. .*/
-#define SPI_MEM_USR    (BIT(18))
-#define SPI_MEM_USR_M  (BIT(18))
-#define SPI_MEM_USR_V  0x1
-#define SPI_MEM_USR_S  18
-/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
-/*description: In user mode, it is set to indicate that program/erase operation will be trigger
-ed. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the o
-peration done.1: enable 0: disable. .*/
-#define SPI_MEM_FLASH_PE    (BIT(17))
-#define SPI_MEM_FLASH_PE_M  (BIT(17))
-#define SPI_MEM_FLASH_PE_V  0x1
-#define SPI_MEM_FLASH_PE_S  17
-
-#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
-/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
-address, the bit24-bit31 are the byte length of a transfer..*/
-#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
-#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_MEM_USR_ADDR_VALUE_S  0
-
-#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
-/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-
-mode). 1: enable 0: disable. .*/
-#define SPI_MEM_FREAD_QIO    (BIT(24))
-#define SPI_MEM_FREAD_QIO_M  (BIT(24))
-#define SPI_MEM_FREAD_QIO_V  0x1
-#define SPI_MEM_FREAD_QIO_S  24
-/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-
-mode). 1: enable 0: disable. .*/
-#define SPI_MEM_FREAD_DIO    (BIT(23))
-#define SPI_MEM_FREAD_DIO_M  (BIT(23))
-#define SPI_MEM_FREAD_DIO_V  0x1
-#define SPI_MEM_FREAD_DIO_S  23
-/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: Two bytes data will be written to status register when it is set. 1: enable 0: d
-isable. .*/
-#define SPI_MEM_WRSR_2B    (BIT(22))
-#define SPI_MEM_WRSR_2B_M  (BIT(22))
-#define SPI_MEM_WRSR_2B_V  0x1
-#define SPI_MEM_WRSR_2B_S  22
-/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low. .*/
-#define SPI_MEM_WP_REG    (BIT(21))
-#define SPI_MEM_WP_REG_M  (BIT(21))
-#define SPI_MEM_WP_REG_V  0x1
-#define SPI_MEM_WP_REG_S  21
-/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enabl
-e 0: disable. .*/
-#define SPI_MEM_FREAD_QUAD    (BIT(20))
-#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
-#define SPI_MEM_FREAD_QUAD_V  0x1
-#define SPI_MEM_FREAD_QUAD_S  20
-/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
-#define SPI_MEM_D_POL    (BIT(19))
-#define SPI_MEM_D_POL_M  (BIT(19))
-#define SPI_MEM_D_POL_V  0x1
-#define SPI_MEM_D_POL_S  19
-/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
-#define SPI_MEM_Q_POL    (BIT(18))
-#define SPI_MEM_Q_POL_M  (BIT(18))
-#define SPI_MEM_Q_POL_V  0x1
-#define SPI_MEM_Q_POL_S  18
-/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
-spi_mem_flash_res bit. 1: enable 0: disable. .*/
-#define SPI_MEM_RESANDRES    (BIT(15))
-#define SPI_MEM_RESANDRES_M  (BIT(15))
-#define SPI_MEM_RESANDRES_V  0x1
-#define SPI_MEM_RESANDRES_S  15
-/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable
-. .*/
-#define SPI_MEM_FREAD_DUAL    (BIT(14))
-#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
-#define SPI_MEM_FREAD_DUAL_V  0x1
-#define SPI_MEM_FREAD_DUAL_S  14
-/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_
-QUAD or SPI_MEM_FREAD_DUAL is set..*/
-#define SPI_MEM_FASTRD_MODE    (BIT(13))
-#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
-#define SPI_MEM_FASTRD_MODE_V  0x1
-#define SPI_MEM_FASTRD_MODE_S  13
-/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
-e.*/
-#define SPI_MEM_TX_CRC_EN    (BIT(11))
-#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
-#define SPI_MEM_TX_CRC_EN_V  0x1
-#define SPI_MEM_TX_CRC_EN_S  11
-/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Activ
-e low..*/
-#define SPI_MEM_FCS_CRC_EN    (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
-#define SPI_MEM_FCS_CRC_EN_V  0x1
-#define SPI_MEM_FCS_CRC_EN_S  10
-/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase..*/
-#define SPI_MEM_FCMD_OCT    (BIT(9))
-#define SPI_MEM_FCMD_OCT_M  (BIT(9))
-#define SPI_MEM_FCMD_OCT_V  0x1
-#define SPI_MEM_FCMD_OCT_S  9
-/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase..*/
-#define SPI_MEM_FCMD_QUAD    (BIT(8))
-#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
-#define SPI_MEM_FCMD_QUAD_V  0x1
-#define SPI_MEM_FCMD_QUAD_S  8
-/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase..*/
-#define SPI_MEM_FCMD_DUAL    (BIT(7))
-#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
-#define SPI_MEM_FCMD_DUAL_V  0x1
-#define SPI_MEM_FCMD_DUAL_S  7
-/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase..*/
-#define SPI_MEM_FADDR_OCT    (BIT(6))
-#define SPI_MEM_FADDR_OCT_M  (BIT(6))
-#define SPI_MEM_FADDR_OCT_V  0x1
-#define SPI_MEM_FADDR_OCT_S  6
-/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase..*/
-#define SPI_MEM_FDIN_OCT    (BIT(5))
-#define SPI_MEM_FDIN_OCT_M  (BIT(5))
-#define SPI_MEM_FDIN_OCT_V  0x1
-#define SPI_MEM_FDIN_OCT_S  5
-/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase..*/
-#define SPI_MEM_FDOUT_OCT    (BIT(4))
-#define SPI_MEM_FDOUT_OCT_M  (BIT(4))
-#define SPI_MEM_FDOUT_OCT_V  0x1
-#define SPI_MEM_FDOUT_OCT_S  4
-/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller..*/
-#define SPI_MEM_FDUMMY_OUT    (BIT(3))
-#define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
-#define SPI_MEM_FDUMMY_OUT_V  0x1
-#define SPI_MEM_FDUMMY_OUT_S  3
-
-#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
-/* SPI_MEM_RXFIFO_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts
-..*/
-#define SPI_MEM_RXFIFO_RST    (BIT(30))
-#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
-#define SPI_MEM_RXFIFO_RST_V  0x1
-#define SPI_MEM_RXFIFO_RST_S  30
-/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
-/*description: After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 4 or * 256) SPI_CLK cycles..*/
-#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
-#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
-#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
-#define SPI_MEM_CS_HOLD_DLY_RES_S  2
-/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS ina
-ctive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delaye
-d two cycles after SPI_CS inactive 3: SPI_CLK is always on..*/
-#define SPI_MEM_CLK_MODE    0x00000003
-#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
-#define SPI_MEM_CLK_MODE_V  0x3
-#define SPI_MEM_CLK_MODE_S  0
-
-#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
-/* SPI_MEM_SYNC_RESET : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
-/*description: The FSM will be reset..*/
-#define SPI_MEM_SYNC_RESET    (BIT(31))
-#define SPI_MEM_SYNC_RESET_M  (BIT(31))
-#define SPI_MEM_SYNC_RESET_V  0x1
-#define SPI_MEM_SYNC_RESET_S  31
-/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
- clock cycles..*/
-#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse
-s flash..*/
-#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
-#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
-#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
-/* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when acce
-sses flash..*/
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
-/* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
-/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC
-mode when accessed flash..*/
-#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
-#define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
-#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
-#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
-/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
-/*description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), wh
-ich is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_ME
-M_CS_HOLD bit..*/
-#define SPI_MEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
-#define SPI_MEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_CS_HOLD_TIME_S  5
-/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
-/*description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits
-are combined with SPI_MEM_CS_SETUP bit..*/
-#define SPI_MEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
-#define SPI_MEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_CS_SETUP_TIME_S  0
-
-#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
-/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK
- = f_MSPI_CORE_CLK..*/
-#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_CLK_EQU_SYSCLK_S  31
-/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLK
-CNT_N+1).*/
-#define SPI_MEM_CLKCNT_N    0x000000FF
-#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
-#define SPI_MEM_CLKCNT_N_V  0xFF
-#define SPI_MEM_CLKCNT_N_S  16
-/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1)..*/
-#define SPI_MEM_CLKCNT_H    0x000000FF
-#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
-#define SPI_MEM_CLKCNT_H_V  0xFF
-#define SPI_MEM_CLKCNT_H_S  8
-/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: It must equal to the value of SPI_MEM_CLKCNT_N. .*/
-#define SPI_MEM_CLKCNT_L    0x000000FF
-#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
-#define SPI_MEM_CLKCNT_L_V  0xFF
-#define SPI_MEM_CLKCNT_L_S  0
-
-#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
-/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: Set this bit to enable enable the CMD phase of an operation..*/
-#define SPI_MEM_USR_COMMAND    (BIT(31))
-#define SPI_MEM_USR_COMMAND_M  (BIT(31))
-#define SPI_MEM_USR_COMMAND_V  0x1
-#define SPI_MEM_USR_COMMAND_S  31
-/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable enable the ADDR phase of an operation..*/
-#define SPI_MEM_USR_ADDR    (BIT(30))
-#define SPI_MEM_USR_ADDR_M  (BIT(30))
-#define SPI_MEM_USR_ADDR_V  0x1
-#define SPI_MEM_USR_ADDR_S  30
-/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable enable the DUMMY phase of an operation..*/
-#define SPI_MEM_USR_DUMMY    (BIT(29))
-#define SPI_MEM_USR_DUMMY_M  (BIT(29))
-#define SPI_MEM_USR_DUMMY_V  0x1
-#define SPI_MEM_USR_DUMMY_S  29
-/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable enable the DIN phase of a read-data operation..*/
-#define SPI_MEM_USR_MISO    (BIT(28))
-#define SPI_MEM_USR_MISO_M  (BIT(28))
-#define SPI_MEM_USR_MISO_V  0x1
-#define SPI_MEM_USR_MISO_S  28
-/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the DOUT phase of an write-data operation..*/
-#define SPI_MEM_USR_MOSI    (BIT(27))
-#define SPI_MEM_USR_MOSI_M  (BIT(27))
-#define SPI_MEM_USR_MOSI_V  0x1
-#define SPI_MEM_USR_MOSI_S  27
-/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable..*/
-#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
-#define SPI_MEM_USR_DUMMY_IDLE_S  26
-/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG
-. 1: enable 0: disable. .*/
-#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
-#define SPI_MEM_USR_MOSI_HIGHPART_S  25
-/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG.
- 1: enable 0: disable. .*/
-#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
-#define SPI_MEM_USR_MISO_HIGHPART_S  24
-/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write ope
-ration..*/
-#define SPI_MEM_FWRITE_QIO    (BIT(15))
-#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
-#define SPI_MEM_FWRITE_QIO_V  0x1
-#define SPI_MEM_FWRITE_QIO_S  15
-/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation..*/
-#define SPI_MEM_FWRITE_DIO    (BIT(14))
-#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
-#define SPI_MEM_FWRITE_DIO_V  0x1
-#define SPI_MEM_FWRITE_DIO_S  14
-/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Set this bit to enable 4-bm in DOUT phase in SPI1 write operation..*/
-#define SPI_MEM_FWRITE_QUAD    (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
-#define SPI_MEM_FWRITE_QUAD_V  0x1
-#define SPI_MEM_FWRITE_QUAD_S  13
-/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Set this bit to enable 2-bm in DOUT phase in SPI1 write operation..*/
-#define SPI_MEM_FWRITE_DUAL    (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
-#define SPI_MEM_FWRITE_DUAL_V  0x1
-#define SPI_MEM_FWRITE_DUAL_S  12
-/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mo
-de 0~3 of SPI_CLK. .*/
-#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_OUT_EDGE_V  0x1
-#define SPI_MEM_CK_OUT_EDGE_S  9
-/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/
-#define SPI_MEM_CS_SETUP    (BIT(7))
-#define SPI_MEM_CS_SETUP_M  (BIT(7))
-#define SPI_MEM_CS_SETUP_V  0x1
-#define SPI_MEM_CS_SETUP_S  7
-/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/
-#define SPI_MEM_CS_HOLD    (BIT(6))
-#define SPI_MEM_CS_HOLD_M  (BIT(6))
-#define SPI_MEM_CS_HOLD_V  0x1
-#define SPI_MEM_CS_HOLD_S  6
-
-#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
-/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
-/*description: The length in bits of ADDR phase. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
-#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_USR_ADDR_BITLEN_S  26
-/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
-/*description: The SPI_CLK cycle length minus 1 of DUMMY phase..*/
-#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
-#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
-/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of CMD phase. The register value shall be (bit_num-1).*/
-#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
-#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
-#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
-#define SPI_MEM_USR_COMMAND_BITLEN_S  28
-/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of user defined(USR) command..*/
-#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
-#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
-#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_MEM_USR_COMMAND_VALUE_S  0
-
-#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
-/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of DOUT phase. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
-#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MOSI_DBITLEN_S  0
-
-#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
-/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
-/*description: The length in bits of DIN phase. The register value shall be (bit_num-1)..*/
-#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
-#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
-#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
-#define SPI_MEM_USR_MISO_DBITLEN_S  0
-
-#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
-/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
-/*description: Mode bits in the flash fast read mode  it is combined with SPI_MEM_FASTRD_MODE b
-it..*/
-#define SPI_MEM_WB_MODE    0x000000FF
-#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
-#define SPI_MEM_WB_MODE_V  0xFF
-#define SPI_MEM_WB_MODE_S  16
-/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit..*/
-#define SPI_MEM_STATUS    0x0000FFFF
-#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
-#define SPI_MEM_STATUS_V  0xFFFF
-#define SPI_MEM_STATUS_S  0
-
-#define SPI_MEM_EXT_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x30)
-/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: The register are the higher 32bits in the 64 bits address mode..*/
-#define SPI_MEM_EXT_ADDR    0xFFFFFFFF
-#define SPI_MEM_EXT_ADDR_M  ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S))
-#define SPI_MEM_EXT_ADDR_V  0xFFFFFFFF
-#define SPI_MEM_EXT_ADDR_S  0
-
-#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
-/* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to enable auto PER function. Hardware will sent out PER command if
-PES command is sent..*/
-#define SPI_MEM_AUTO_PER    (BIT(11))
-#define SPI_MEM_AUTO_PER_M  (BIT(11))
-#define SPI_MEM_AUTO_PER_V  0x1
-#define SPI_MEM_AUTO_PER_S  11
-/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: SPI_CS line keep low when the bit is set..*/
-#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
-#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
-#define SPI_MEM_CS_KEEP_ACTIVE_S  10
-/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is i
-dle..*/
-#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
-#define SPI_MEM_CK_IDLE_EDGE_V  0x1
-#define SPI_MEM_CK_IDLE_EDGE_S  9
-/* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Ext_RAM is connected to SPI SUBPIN bus..*/
-#define SPI_MEM_SSUB_PIN    (BIT(8))
-#define SPI_MEM_SSUB_PIN_M  (BIT(8))
-#define SPI_MEM_SSUB_PIN_V  0x1
-#define SPI_MEM_SSUB_PIN_S  8
-/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Flash is connected to SPI SUBPIN bus..*/
-#define SPI_MEM_FSUB_PIN    (BIT(7))
-#define SPI_MEM_FSUB_PIN_M  (BIT(7))
-#define SPI_MEM_FSUB_PIN_V  0x1
-#define SPI_MEM_FSUB_PIN_S  7
-/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM)
- connected to SPI_CS1 is in low level when SPI1 transfer starts..*/
-#define SPI_MEM_CS1_DIS    (BIT(1))
-#define SPI_MEM_CS1_DIS_M  (BIT(1))
-#define SPI_MEM_CS1_DIS_V  0x1
-#define SPI_MEM_CS1_DIS_S  1
-/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) co
-nnected to SPI_CS is in low level when SPI1 transfer starts..*/
-#define SPI_MEM_CS0_DIS    (BIT(0))
-#define SPI_MEM_CS0_DIS_M  (BIT(0))
-#define SPI_MEM_CS0_DIS_V  0x1
-#define SPI_MEM_CS0_DIS_S  0
-
-#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
-/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: For SPI1, the value of crc32..*/
-#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
-#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
-#define SPI_MEM_TX_CRC_DATA_S  0
-
-#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
-/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phas
-e..*/
-#define SPI_MEM_FADDR_QUAD    (BIT(8))
-#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
-#define SPI_MEM_FADDR_QUAD_V  0x1
-#define SPI_MEM_FADDR_QUAD_S  8
-/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phas
-e..*/
-#define SPI_MEM_FDOUT_QUAD    (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
-#define SPI_MEM_FDOUT_QUAD_V  0x1
-#define SPI_MEM_FDOUT_QUAD_S  7
-/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase
-..*/
-#define SPI_MEM_FDIN_QUAD    (BIT(6))
-#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
-#define SPI_MEM_FDIN_QUAD_V  0x1
-#define SPI_MEM_FDIN_QUAD_S  6
-/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phas
-e..*/
-#define SPI_MEM_FADDR_DUAL    (BIT(5))
-#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
-#define SPI_MEM_FADDR_DUAL_V  0x1
-#define SPI_MEM_FADDR_DUAL_S  5
-/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phas
-e..*/
-#define SPI_MEM_FDOUT_DUAL    (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
-#define SPI_MEM_FDOUT_DUAL_V  0x1
-#define SPI_MEM_FDOUT_DUAL_S  4
-/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase
-..*/
-#define SPI_MEM_FDIN_DUAL    (BIT(3))
-#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
-#define SPI_MEM_FDIN_DUAL_V  0x1
-#define SPI_MEM_FDIN_DUAL_S  3
-/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardwa
-re read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_M
-EM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits..*/
-#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
-#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
-#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
-/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_
-USR_ADDR_BITLEN should be 31..*/
-#define SPI_MEM_CACHE_USR_CMD_4BYTE    (BIT(1))
-#define SPI_MEM_CACHE_USR_CMD_4BYTE_M  (BIT(1))
-#define SPI_MEM_CACHE_USR_CMD_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_CMD_4BYTE_S  1
-/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable Cache's access and SPI0's transfer..*/
-#define SPI_MEM_CACHE_REQ_EN    (BIT(0))
-#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
-#define SPI_MEM_CACHE_REQ_EN_V  0x1
-#define SPI_MEM_CACHE_REQ_EN_S  0
-
-#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
-/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */
-/*description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase i
-n write data transfer..*/
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
-/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer..*/
-#define SPI_MEM_SRAM_OCT    (BIT(21))
-#define SPI_MEM_SRAM_OCT_M  (BIT(21))
-#define SPI_MEM_SRAM_OCT_V  0x1
-#define SPI_MEM_SRAM_OCT_S  21
-/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALU
-E. 0: The value is 0x3..*/
-#define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
-#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
-/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */
-/*description: When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The regis
-ter value shall be (bit_num-1)..*/
-#define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
-#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
-#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
-#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
-/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */
-/*description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase i
-n read data transfer..*/
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
-/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE
-. 0: The value is 0x2..*/
-#define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
-#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
-/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operat
-ions..*/
-#define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
-#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
-#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
-#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
-/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write opera
-tions..*/
-#define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
-#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
-#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
-#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
-/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer..*/
-#define SPI_MEM_USR_SRAM_QIO    (BIT(2))
-#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
-#define SPI_MEM_USR_SRAM_QIO_V  0x1
-#define SPI_MEM_USR_SRAM_QIO_S  2
-/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer..*/
-#define SPI_MEM_USR_SRAM_DIO    (BIT(1))
-#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
-#define SPI_MEM_USR_SRAM_DIO_V  0x1
-#define SPI_MEM_USR_SRAM_DIO_S  1
-/* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_
-MEM_SRAM_ADDR_BITLEN should be 31..*/
-#define SPI_MEM_CACHE_USR_SCMD_4BYTE    (BIT(0))
-#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M  (BIT(0))
-#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V  0x1
-#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S  0
-
-#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
-/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is
- output by the SPI0 controller..*/
-#define SPI_MEM_SDUMMY_OUT    (BIT(22))
-#define SPI_MEM_SDUMMY_OUT_M  (BIT(22))
-#define SPI_MEM_SDUMMY_OUT_V  0x1
-#define SPI_MEM_SDUMMY_OUT_S  22
-/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase..*/
-#define SPI_MEM_SCMD_OCT    (BIT(21))
-#define SPI_MEM_SCMD_OCT_M  (BIT(21))
-#define SPI_MEM_SCMD_OCT_V  0x1
-#define SPI_MEM_SCMD_OCT_S  21
-/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase..*/
-#define SPI_MEM_SADDR_OCT    (BIT(20))
-#define SPI_MEM_SADDR_OCT_M  (BIT(20))
-#define SPI_MEM_SADDR_OCT_V  0x1
-#define SPI_MEM_SADDR_OCT_S  20
-/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase..*/
-#define SPI_MEM_SDOUT_OCT    (BIT(19))
-#define SPI_MEM_SDOUT_OCT_M  (BIT(19))
-#define SPI_MEM_SDOUT_OCT_V  0x1
-#define SPI_MEM_SDOUT_OCT_S  19
-/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase..*/
-#define SPI_MEM_SDIN_OCT    (BIT(18))
-#define SPI_MEM_SDIN_OCT_M  (BIT(18))
-#define SPI_MEM_SDIN_OCT_V  0x1
-#define SPI_MEM_SDIN_OCT_S  18
-/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase..*/
-#define SPI_MEM_SCMD_QUAD    (BIT(17))
-#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
-#define SPI_MEM_SCMD_QUAD_V  0x1
-#define SPI_MEM_SCMD_QUAD_S  17
-/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase..*/
-#define SPI_MEM_SADDR_QUAD    (BIT(16))
-#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
-#define SPI_MEM_SADDR_QUAD_V  0x1
-#define SPI_MEM_SADDR_QUAD_S  16
-/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase..*/
-#define SPI_MEM_SDOUT_QUAD    (BIT(15))
-#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
-#define SPI_MEM_SDOUT_QUAD_V  0x1
-#define SPI_MEM_SDOUT_QUAD_S  15
-/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase..*/
-#define SPI_MEM_SDIN_QUAD    (BIT(14))
-#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
-#define SPI_MEM_SDIN_QUAD_V  0x1
-#define SPI_MEM_SDIN_QUAD_S  14
-/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase..*/
-#define SPI_MEM_SCMD_DUAL    (BIT(13))
-#define SPI_MEM_SCMD_DUAL_M  (BIT(13))
-#define SPI_MEM_SCMD_DUAL_V  0x1
-#define SPI_MEM_SCMD_DUAL_S  13
-/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase..*/
-#define SPI_MEM_SADDR_DUAL    (BIT(12))
-#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
-#define SPI_MEM_SADDR_DUAL_V  0x1
-#define SPI_MEM_SADDR_DUAL_S  12
-/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase..*/
-#define SPI_MEM_SDOUT_DUAL    (BIT(11))
-#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
-#define SPI_MEM_SDOUT_DUAL_V  0x1
-#define SPI_MEM_SDOUT_DUAL_S  11
-/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase..*/
-#define SPI_MEM_SDIN_DUAL    (BIT(10))
-#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
-#define SPI_MEM_SDIN_DUAL_V  0x1
-#define SPI_MEM_SDIN_DUAL_S  10
-/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
-/*description: Mode bits when SPI0 accesses to Ext_RAM..*/
-#define SPI_MEM_SWB_MODE    0x000000FF
-#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
-#define SPI_MEM_SWB_MODE_V  0xFF
-#define SPI_MEM_SWB_MODE_S  2
-/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: SPI_CLK mode bits  when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inac
-tive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two
- cycles after CS inactive 3: SPI_CLK is always on..*/
-#define SPI_MEM_SCLK_MODE    0x00000003
-#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
-#define SPI_MEM_SCLK_MODE_V  0x3
-#define SPI_MEM_SCLK_MODE_S  0
-
-#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
-/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register val
-ue shall be (bit_num-1)..*/
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
-/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: When SPI0 reads Ext_RAM, it is the command value of CMD phase..*/
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
-#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
-
-#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
-/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
-/*description: When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register va
-lue shall be (bit_num-1)..*/
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
-/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: When SPI0 writes Ext_RAM, it is the command value of CMD phase..*/
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
-#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
-
-#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
-/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MS
-PI_CORE_CLK..*/
-#define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
-#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
-#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
-/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
-/*description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1).*/
-#define SPI_MEM_SCLKCNT_N    0x000000FF
-#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
-#define SPI_MEM_SCLKCNT_N_V  0xFF
-#define SPI_MEM_SCLKCNT_N_S  16
-/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
-/*description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1)..*/
-#define SPI_MEM_SCLKCNT_H    0x000000FF
-#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
-#define SPI_MEM_SCLKCNT_H_V  0xFF
-#define SPI_MEM_SCLKCNT_H_S  8
-/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
-/*description: It must equal to the value of SPI_MEM_SCLKCNT_N. .*/
-#define SPI_MEM_SCLKCNT_L    0x000000FF
-#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
-#define SPI_MEM_SCLKCNT_L_V  0xFF
-#define SPI_MEM_SCLKCNT_L_S  0
-
-#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
-/* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP
-), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DI
-N), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE)..*/
-#define SPI_MEM_ST    0x00000007
-#define SPI_MEM_ST_M  ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S))
-#define SPI_MEM_ST_V  0x7
-#define SPI_MEM_ST_S  0
-
-#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
-/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF0    0xFFFFFFFF
-#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
-#define SPI_MEM_BUF0_V  0xFFFFFFFF
-#define SPI_MEM_BUF0_S  0
-
-#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
-/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF1    0xFFFFFFFF
-#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
-#define SPI_MEM_BUF1_V  0xFFFFFFFF
-#define SPI_MEM_BUF1_S  0
-
-#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
-/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF2    0xFFFFFFFF
-#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
-#define SPI_MEM_BUF2_V  0xFFFFFFFF
-#define SPI_MEM_BUF2_S  0
-
-#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
-/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF3    0xFFFFFFFF
-#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
-#define SPI_MEM_BUF3_V  0xFFFFFFFF
-#define SPI_MEM_BUF3_S  0
-
-#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
-/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF4    0xFFFFFFFF
-#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
-#define SPI_MEM_BUF4_V  0xFFFFFFFF
-#define SPI_MEM_BUF4_S  0
-
-#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
-/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF5    0xFFFFFFFF
-#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
-#define SPI_MEM_BUF5_V  0xFFFFFFFF
-#define SPI_MEM_BUF5_S  0
-
-#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
-/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF6    0xFFFFFFFF
-#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
-#define SPI_MEM_BUF6_V  0xFFFFFFFF
-#define SPI_MEM_BUF6_S  0
-
-#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
-/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF7    0xFFFFFFFF
-#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
-#define SPI_MEM_BUF7_V  0xFFFFFFFF
-#define SPI_MEM_BUF7_S  0
-
-#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
-/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF8    0xFFFFFFFF
-#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
-#define SPI_MEM_BUF8_V  0xFFFFFFFF
-#define SPI_MEM_BUF8_S  0
-
-#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
-/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF9    0xFFFFFFFF
-#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
-#define SPI_MEM_BUF9_V  0xFFFFFFFF
-#define SPI_MEM_BUF9_S  0
-
-#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
-/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF10    0xFFFFFFFF
-#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
-#define SPI_MEM_BUF10_V  0xFFFFFFFF
-#define SPI_MEM_BUF10_S  0
-
-#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
-/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF11    0xFFFFFFFF
-#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
-#define SPI_MEM_BUF11_V  0xFFFFFFFF
-#define SPI_MEM_BUF11_S  0
-
-#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
-/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF12    0xFFFFFFFF
-#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
-#define SPI_MEM_BUF12_V  0xFFFFFFFF
-#define SPI_MEM_BUF12_S  0
-
-#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
-/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF13    0xFFFFFFFF
-#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
-#define SPI_MEM_BUF13_V  0xFFFFFFFF
-#define SPI_MEM_BUF13_S  0
-
-#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
-/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF14    0xFFFFFFFF
-#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
-#define SPI_MEM_BUF14_V  0xFFFFFFFF
-#define SPI_MEM_BUF14_S  0
-
-#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
-/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: data buffer.*/
-#define SPI_MEM_BUF15    0xFFFFFFFF
-#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
-#define SPI_MEM_BUF15_V  0xFFFFFFFF
-#define SPI_MEM_BUF15_S  0
-
-#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
-/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
-/*description: The dummy cycle length when wait flash idle(RDSR)..*/
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
-#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
-/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
-/*description: The command value of auto wait flash idle transfer(RDSR)..*/
-#define SPI_MEM_WAITI_CMD    0x000000FF
-#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
-#define SPI_MEM_WAITI_CMD_V  0xFF
-#define SPI_MEM_WAITI_CMD_S  2
-/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR)..*/
-#define SPI_MEM_WAITI_DUMMY    (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
-#define SPI_MEM_WAITI_DUMMY_V  0x1
-#define SPI_MEM_WAITI_DUMMY_S  1
-/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/P
-ES command is sent..*/
-#define SPI_MEM_WAITI_EN    (BIT(0))
-#define SPI_MEM_WAITI_EN_M  (BIT(0))
-#define SPI_MEM_WAITI_EN_V  0x1
-#define SPI_MEM_WAITI_EN_S  0
-
-#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
-/* SPI_MEM_PESR_IDLE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate..*/
-#define SPI_MEM_PESR_IDLE_EN    (BIT(5))
-#define SPI_MEM_PESR_IDLE_EN_M  (BIT(5))
-#define SPI_MEM_PESR_IDLE_EN_V  0x1
-#define SPI_MEM_PESR_IDLE_EN_S  5
-/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to enable PES transfer trigger PES transfer option..*/
-#define SPI_MEM_PES_PER_EN    (BIT(4))
-#define SPI_MEM_PES_PER_EN_M  (BIT(4))
-#define SPI_MEM_PES_PER_EN_V  0x1
-#define SPI_MEM_PES_PER_EN_S  4
-/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to add delay time after program erase suspend(PES) command is sent..*/
-#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
-#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
-/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to add delay time after program erase resume(PER) is sent..*/
-#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
-#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
-#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
-/* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */
-/*description: program erase suspend bit, program erase suspend operation will be triggered whe
-n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
-isable. .*/
-#define SPI_MEM_FLASH_PES    (BIT(1))
-#define SPI_MEM_FLASH_PES_M  (BIT(1))
-#define SPI_MEM_FLASH_PES_V  0x1
-#define SPI_MEM_FLASH_PES_S  1
-/* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */
-/*description: program erase resume bit, program erase suspend operation will be triggered when
- the bit is set. The bit will be cleared once the operation done.1: enable 0: di
-sable. .*/
-#define SPI_MEM_FLASH_PER    (BIT(0))
-#define SPI_MEM_FLASH_PER_M  (BIT(0))
-#define SPI_MEM_FLASH_PER_V  0x1
-#define SPI_MEM_FLASH_PER_S  0
-
-#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
-/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */
-/*description: Program/Erase suspend command value..*/
-#define SPI_MEM_FLASH_PES_COMMAND    0x000000FF
-#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
-#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
-#define SPI_MEM_FLASH_PES_COMMAND_S  9
-/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */
-/*description: Program/Erase resume command value..*/
-#define SPI_MEM_FLASH_PER_COMMAND    0x000000FF
-#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
-#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
-#define SPI_MEM_FLASH_PER_COMMAND_S  1
-/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable auto-suspend function..*/
-#define SPI_MEM_FLASH_PES_EN    (BIT(0))
-#define SPI_MEM_FLASH_PES_EN_M  (BIT(0))
-#define SPI_MEM_FLASH_PES_EN_V  0x1
-#define SPI_MEM_FLASH_PES_EN_S  0
-
-#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
-/* SPI_MEM_FLASH_PES_DLY_256 : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
-#define SPI_MEM_FLASH_PES_DLY_256    (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_256_M  (BIT(6))
-#define SPI_MEM_FLASH_PES_DLY_256_V  0x1
-#define SPI_MEM_FLASH_PES_DLY_256_S  6
-/* SPI_MEM_FLASH_PER_DLY_256 : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
-RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
-_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
-#define SPI_MEM_FLASH_PER_DLY_256    (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_256_M  (BIT(5))
-#define SPI_MEM_FLASH_PER_DLY_256_V  0x1
-#define SPI_MEM_FLASH_PER_DLY_256_S  5
-/* SPI_MEM_FLASH_DP_DLY_256 : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP com
-mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
-after DP command is sent..*/
-#define SPI_MEM_FLASH_DP_DLY_256    (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_256_M  (BIT(4))
-#define SPI_MEM_FLASH_DP_DLY_256_V  0x1
-#define SPI_MEM_FLASH_DP_DLY_256_S  4
-/* SPI_MEM_FLASH_RES_DLY_256 : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after RES command is sent..*/
-#define SPI_MEM_FLASH_RES_DLY_256    (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_256_M  (BIT(3))
-#define SPI_MEM_FLASH_RES_DLY_256_V  0x1
-#define SPI_MEM_FLASH_RES_DLY_256_S  3
-/* SPI_MEM_FLASH_HPM_DLY_256 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM co
-mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
- after HPM command is sent..*/
-#define SPI_MEM_FLASH_HPM_DLY_256    (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_256_M  (BIT(2))
-#define SPI_MEM_FLASH_HPM_DLY_256_V  0x1
-#define SPI_MEM_FLASH_HPM_DLY_256_S  2
-/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
-/*description: The status of flash suspend. This bit is set when PES command is sent, and clear
-ed when PER is sent. Only used in SPI1..*/
-#define SPI_MEM_FLASH_SUS    (BIT(0))
-#define SPI_MEM_FLASH_SUS_M  (BIT(0))
-#define SPI_MEM_FLASH_SUS_V  0x1
-#define SPI_MEM_FLASH_SUS_S  0
-
-#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA8)
-/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when S
-PI_MEM_TIMING_CALI bit is set..*/
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio
-ns..*/
-#define SPI_MEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_TIMING_CALI_V  0x1
-#define SPI_MEM_TIMING_CALI_S  1
-/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
-als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
-#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xAC)
-/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles
-at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK
- positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
-EM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negat
-ive edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one
- cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles
-at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DINS_MODE    0x00000007
-#define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
-#define SPI_MEM_DINS_MODE_V  0x7
-#define SPI_MEM_DINS_MODE_S  24
-/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
- at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
-LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
-_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
-gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
- one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
-cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DIN7_MODE    0x00000007
-#define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
-#define SPI_MEM_DIN7_MODE_V  0x7
-#define SPI_MEM_DIN7_MODE_S  21
-/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
- at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
-LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
-_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
-gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
- one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
-cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DIN6_MODE    0x00000007
-#define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
-#define SPI_MEM_DIN6_MODE_V  0x7
-#define SPI_MEM_DIN6_MODE_S  18
-/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
- at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
-LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
-_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
-gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
- one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
-cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DIN5_MODE    0x00000007
-#define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
-#define SPI_MEM_DIN5_MODE_V  0x7
-#define SPI_MEM_DIN5_MODE_S  15
-/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
- at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
-LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
-_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
-gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
- one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
-cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DIN4_MODE    0x00000007
-#define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
-#define SPI_MEM_DIN4_MODE_V  0x7
-#define SPI_MEM_DIN4_MODE_S  12
-/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
-at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL
-K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_
-MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg
-ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
-one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
-les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DIN3_MODE    0x00000007
-#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
-#define SPI_MEM_DIN3_MODE_V  0x7
-#define SPI_MEM_DIN3_MODE_S  9
-/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
-at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL
-K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_
-MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK neg
-ative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
-one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
-les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DIN2_MODE    0x00000007
-#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
-#define SPI_MEM_DIN2_MODE_V  0x7
-#define SPI_MEM_DIN2_MODE_S  6
-/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a
-t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK
- positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
-EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega
-tive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o
-ne cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycl
-es at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DIN1_MODE    0x00000007
-#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
-#define SPI_MEM_DIN1_MODE_V  0x7
-#define SPI_MEM_DIN1_MODE_S  3
-/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a
-t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK
- positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
-EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega
-tive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o
-ne cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycl
-es at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_DIN0_MODE    0x00000007
-#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
-#define SPI_MEM_DIN0_MODE_V  0x7
-#define SPI_MEM_DIN0_MODE_S  0
-
-#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB0)
-/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: SPI_DQS input delay number..*/
-#define SPI_MEM_DINS_NUM    0x00000003
-#define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
-#define SPI_MEM_DINS_NUM_V  0x3
-#define SPI_MEM_DINS_NUM_S  16
-/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: SPI_IO7 input delay number..*/
-#define SPI_MEM_DIN7_NUM    0x00000003
-#define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
-#define SPI_MEM_DIN7_NUM_V  0x3
-#define SPI_MEM_DIN7_NUM_S  14
-/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: SPI_IO6 input delay number..*/
-#define SPI_MEM_DIN6_NUM    0x00000003
-#define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
-#define SPI_MEM_DIN6_NUM_V  0x3
-#define SPI_MEM_DIN6_NUM_S  12
-/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: SPI_IO5 input delay number..*/
-#define SPI_MEM_DIN5_NUM    0x00000003
-#define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
-#define SPI_MEM_DIN5_NUM_V  0x3
-#define SPI_MEM_DIN5_NUM_S  10
-/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: SPI_IO4 input delay number..*/
-#define SPI_MEM_DIN4_NUM    0x00000003
-#define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
-#define SPI_MEM_DIN4_NUM_V  0x3
-#define SPI_MEM_DIN4_NUM_S  8
-/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: SPI_HD input delay number..*/
-#define SPI_MEM_DIN3_NUM    0x00000003
-#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
-#define SPI_MEM_DIN3_NUM_V  0x3
-#define SPI_MEM_DIN3_NUM_S  6
-/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: SPI_WP input delay number..*/
-#define SPI_MEM_DIN2_NUM    0x00000003
-#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
-#define SPI_MEM_DIN2_NUM_V  0x3
-#define SPI_MEM_DIN2_NUM_S  4
-/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: SPI_Q input delay number..*/
-#define SPI_MEM_DIN1_NUM    0x00000003
-#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
-#define SPI_MEM_DIN1_NUM_V  0x3
-#define SPI_MEM_DIN1_NUM_S  2
-/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI_D input delay number..*/
-#define SPI_MEM_DIN0_NUM    0x00000003
-#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
-#define SPI_MEM_DIN0_NUM_V  0x3
-#define SPI_MEM_DIN0_NUM_S  0
-
-#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB4)
-/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_DOUTS_MODE_M  (BIT(8))
-#define SPI_MEM_DOUTS_MODE_V  0x1
-#define SPI_MEM_DOUTS_MODE_S  8
-/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_DOUT7_MODE_M  (BIT(7))
-#define SPI_MEM_DOUT7_MODE_V  0x1
-#define SPI_MEM_DOUT7_MODE_S  7
-/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_DOUT6_MODE_M  (BIT(6))
-#define SPI_MEM_DOUT6_MODE_V  0x1
-#define SPI_MEM_DOUT6_MODE_S  6
-/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_DOUT5_MODE_M  (BIT(5))
-#define SPI_MEM_DOUT5_MODE_V  0x1
-#define SPI_MEM_DOUT5_MODE_S  5
-/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_DOUT4_MODE_M  (BIT(4))
-#define SPI_MEM_DOUT4_MODE_V  0x1
-#define SPI_MEM_DOUT4_MODE_S  4
-/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
-ive edge..*/
-#define SPI_MEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_DOUT3_MODE_S  3
-/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
-ive edge..*/
-#define SPI_MEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_DOUT2_MODE_S  2
-/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
-ve edge..*/
-#define SPI_MEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_DOUT1_MODE_S  1
-/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
-ve edge..*/
-#define SPI_MEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xBC)
-/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
-/*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 acc
-esses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set..*/
-#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
-#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
-#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
-#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
-/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operatio
-ns..*/
-#define SPI_MEM_SPI_SMEM_TIMING_CALI    (BIT(1))
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_V  0x1
-#define SPI_MEM_SPI_SMEM_TIMING_CALI_S  1
-/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
-als to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
-#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
-#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V  0x1
-#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
-/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
-/*description: SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles
- at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HC
-LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
-_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
-gative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and
- one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cy
-cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DINS_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DINS_MODE_M  ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S))
-#define SPI_MEM_SPI_SMEM_DINS_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DINS_MODE_S  24
-/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
-/*description: SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
-s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
-HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
-PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
- negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
- and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
-1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DIN7_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN7_MODE_M  ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN7_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN7_MODE_S  21
-/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
-/*description: SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
-s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
-HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
-PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
- negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
- and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
-1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DIN6_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN6_MODE_M  ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN6_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN6_MODE_S  18
-/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
-/*description: SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
-s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
-HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
-PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
- negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
- and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
-1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DIN5_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN5_MODE_M  ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN5_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN5_MODE_S  15
-/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
-/*description: SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
-s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
-HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
-PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
- negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
- and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
-1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DIN4_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN4_MODE_M  ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN4_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN4_MODE_S  12
-/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
-/*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
- at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at H
-CLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SP
-I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
-negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
-and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1
-) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DIN3_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN3_MODE_M  ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN3_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN3_MODE_S  9
-/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
-/*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
- at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at H
-CLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SP
-I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
-negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
-and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1
-) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DIN2_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN2_MODE_M  ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN2_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN2_MODE_S  6
-/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
-/*description: SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
-at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
-LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
-_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
-egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a
-nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
- cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DIN1_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN1_MODE_M  ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN1_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN1_MODE_S  3
-/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
-at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
-LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
-_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
-egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge a
-nd one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
- cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
-#define SPI_MEM_SPI_SMEM_DIN0_MODE    0x00000007
-#define SPI_MEM_SPI_SMEM_DIN0_MODE_M  ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S))
-#define SPI_MEM_SPI_SMEM_DIN0_MODE_V  0x7
-#define SPI_MEM_SPI_SMEM_DIN0_MODE_S  0
-
-#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
-/* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
-/*description: SPI_DQS input delay number..*/
-#define SPI_MEM_SPI_SMEM_DINS_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DINS_NUM_M  ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S))
-#define SPI_MEM_SPI_SMEM_DINS_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DINS_NUM_S  16
-/* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
-/*description: SPI_IO7 input delay number..*/
-#define SPI_MEM_SPI_SMEM_DIN7_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN7_NUM_M  ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN7_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN7_NUM_S  14
-/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
-/*description: SPI_IO6 input delay number..*/
-#define SPI_MEM_SPI_SMEM_DIN6_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN6_NUM_M  ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN6_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN6_NUM_S  12
-/* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
-/*description: SPI_IO5 input delay number..*/
-#define SPI_MEM_SPI_SMEM_DIN5_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN5_NUM_M  ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN5_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN5_NUM_S  10
-/* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
-/*description: SPI_IO4 input delay number..*/
-#define SPI_MEM_SPI_SMEM_DIN4_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN4_NUM_M  ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN4_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN4_NUM_S  8
-/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
-/*description: SPI_HD input delay number..*/
-#define SPI_MEM_SPI_SMEM_DIN3_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN3_NUM_M  ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN3_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN3_NUM_S  6
-/* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: SPI_WP input delay number..*/
-#define SPI_MEM_SPI_SMEM_DIN2_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN2_NUM_M  ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN2_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN2_NUM_S  4
-/* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: SPI_Q input delay number..*/
-#define SPI_MEM_SPI_SMEM_DIN1_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN1_NUM_M  ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN1_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN1_NUM_S  2
-/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
-/*description: SPI_D input delay number..*/
-#define SPI_MEM_SPI_SMEM_DIN0_NUM    0x00000003
-#define SPI_MEM_SPI_SMEM_DIN0_NUM_M  ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S))
-#define SPI_MEM_SPI_SMEM_DIN0_NUM_V  0x3
-#define SPI_MEM_SPI_SMEM_DIN0_NUM_S  0
-
-#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
-/* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
-/*description: SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_SPI_SMEM_DOUTS_MODE    (BIT(8))
-#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M  (BIT(8))
-#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S  8
-/* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
-/*description: SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_SPI_SMEM_DOUT7_MODE    (BIT(7))
-#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M  (BIT(7))
-#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S  7
-/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
-/*description: SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_SPI_SMEM_DOUT6_MODE    (BIT(6))
-#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M  (BIT(6))
-#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S  6
-/* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
-/*description: SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_SPI_SMEM_DOUT5_MODE    (BIT(5))
-#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M  (BIT(5))
-#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S  5
-/* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
-/*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
-tive edge..*/
-#define SPI_MEM_SPI_SMEM_DOUT4_MODE    (BIT(4))
-#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M  (BIT(4))
-#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S  4
-/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
-/*description: SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
-ive edge..*/
-#define SPI_MEM_SPI_SMEM_DOUT3_MODE    (BIT(3))
-#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M  (BIT(3))
-#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S  3
-/* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
-ive edge..*/
-#define SPI_MEM_SPI_SMEM_DOUT2_MODE    (BIT(2))
-#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S  2
-/* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
-ve edge..*/
-#define SPI_MEM_SPI_SMEM_DOUT1_MODE    (BIT(1))
-#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S  1
-/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
-ve edge..*/
-#define SPI_MEM_SPI_SMEM_DOUT0_MODE    (BIT(0))
-#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S  0
-
-#define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
-/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
-h..*/
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN    (BIT(8))
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M  (BIT(8))
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S  8
-/* SPI_MEM_ECC_ERR_INT_NUM : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
-/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
-upt..*/
-#define SPI_MEM_ECC_ERR_INT_NUM    0x000000FF
-#define SPI_MEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_ECC_ERR_INT_NUM_S))
-#define SPI_MEM_ECC_ERR_INT_NUM_V  0xFF
-#define SPI_MEM_ECC_ERR_INT_NUM_S  0
-
-#define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD0)
-/* SPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SP
-I_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte e
-rror and data error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/
-#define SPI_MEM_ECC_ERR_ADDR    0xFFFFFFFF
-#define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
-#define SPI_MEM_ECC_ERR_ADDR_V  0xFFFFFFFF
-#define SPI_MEM_ECC_ERR_ADDR_S  0
-
-#define SPI_MEM_ECC_ERR_BIT_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
-/* SPI_MEM_ECC_ERR_CNT : RO ;bitpos:[24:17] ;default: 8'd0 ; */
-/*description: This bits show the error times of MSPI ECC read, including ECC byte error and da
-ta byte error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/
-#define SPI_MEM_ECC_ERR_CNT    0x000000FF
-#define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
-#define SPI_MEM_ECC_ERR_CNT_V  0xFF
-#define SPI_MEM_ECC_ERR_CNT_S  17
-/* SPI_MEM_ECC_BYTE_ERR : R/SS/WTC ;bitpos:[16] ;default: 1'd0 ; */
-/*description: It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ER
-R_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_
-INT_CLR bit..*/
-#define SPI_MEM_ECC_BYTE_ERR    (BIT(16))
-#define SPI_MEM_ECC_BYTE_ERR_M  (BIT(16))
-#define SPI_MEM_ECC_BYTE_ERR_V  0x1
-#define SPI_MEM_ECC_BYTE_ERR_S  16
-/* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */
-/*description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC by
-te..*/
-#define SPI_MEM_ECC_CHK_ERR_BIT    0x00000007
-#define SPI_MEM_ECC_CHK_ERR_BIT_M  ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S))
-#define SPI_MEM_ECC_CHK_ERR_BIT_V  0x7
-#define SPI_MEM_ECC_CHK_ERR_BIT_S  13
-/* SPI_MEM_ECC_DATA_ERR_BIT : R/SS/WTC ;bitpos:[12:6] ;default: 7'd0 ; */
-/*description: It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_
-SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from
-0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_ME
-M_ECC_ERR_INT_CLR bit..*/
-#define SPI_MEM_ECC_DATA_ERR_BIT    0x0000007F
-#define SPI_MEM_ECC_DATA_ERR_BIT_M  ((SPI_MEM_ECC_DATA_ERR_BIT_V)<<(SPI_MEM_ECC_DATA_ERR_BIT_S))
-#define SPI_MEM_ECC_DATA_ERR_BIT_V  0x7F
-#define SPI_MEM_ECC_DATA_ERR_BIT_S  6
-
-#define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0xDC)
-/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
-/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
-sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
-SPI core clock cycles..*/
-#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY    0x0000003F
-#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S))
-#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V  0x3F
-#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S  25
-/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
-rnal RAM..*/
-#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN    (BIT(24))
-#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M  (BIT(24))
-#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S  24
-/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse
-s to external RAM..*/
-#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
-#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
-#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S  16
-/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner
- when accesses to external RAM..*/
-#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
-#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
-#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
-#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
-/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
-/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in
-ECC mode when accesses to external RAM..*/
-#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME    0x00000007
-#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S))
-#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V  0x7
-#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S  12
-/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */
-/*description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), wh
-ich is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_ME
-M_CS_HOLD bit..*/
-#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME    0x0000001F
-#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S))
-#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V  0x1F
-#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S  7
-/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */
-/*description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits
-are combined with SPI_MEM_CS_SETUP bit..*/
-#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME    0x0000001F
-#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S))
-#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V  0x1F
-#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S  2
-/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/
-#define SPI_MEM_SPI_SMEM_CS_HOLD    (BIT(1))
-#define SPI_MEM_SPI_SMEM_CS_HOLD_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_CS_HOLD_V  0x1
-#define SPI_MEM_SPI_SMEM_CS_HOLD_S  1
-/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/
-#define SPI_MEM_SPI_SMEM_CS_SETUP    (BIT(0))
-#define SPI_MEM_SPI_SMEM_CS_SETUP_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_CS_SETUP_V  0x1
-#define SPI_MEM_SPI_SMEM_CS_SETUP_S  0
-
-#define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE0)
-/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
-#define SPI_MEM_SPI_FMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M  (BIT(30))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V  0x1
-#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S  30
-/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
-ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
-..*/
-#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V  0x1
-#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S  29
-/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M  (BIT(28))
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V  0x1
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S  28
-/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses flash or SPI1 accesses flash or sram..*/
-#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S  27
-/* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define SPI_MEM_SPI_FMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M  (BIT(26))
-#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V  0x1
-#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S  26
-/* SPI_MEM_SPI_FMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to enable the SPI HyperBus mode..*/
-#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE    (BIT(25))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M  (BIT(25))
-#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V  0x1
-#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S  25
-/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M  (BIT(24))
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S  24
-/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK
- as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is
- not active..*/
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE    (BIT(22))
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M  (BIT(22))
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S  22
-/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Use internal signal  as data strobe, the strobe can not be delayed by input t
-iming module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe ca
-n be delayed by input timing module.*/
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S  21
-/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI_CLK..*/
-#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD    0x0000007F
-#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S))
-#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V  0x7F
-#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S  14
-/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when
-accesses to flash..*/
-#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S  13
-/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when
- accesses to flash..*/
-#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S  12
-/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the panda device..*/
-#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN    0x0000007F
-#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S))
-#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V  0x7F
-#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S  5
-/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
-#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
-#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S  4
-/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder TX data of the word in DDR mode..*/
-#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S  3
-/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder RX data of the word in DDR mode..*/
-#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S  2
-/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in DDRmode..*/
-#define SPI_MEM_SPI_FMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M  (BIT(1))
-#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V  0x1
-#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S  1
-/* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in DDR mode,  0: in SDR mode..*/
-#define SPI_MEM_SPI_FMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_SPI_FMEM_DDR_EN_M  (BIT(0))
-#define SPI_MEM_SPI_FMEM_DDR_EN_V  0x1
-#define SPI_MEM_SPI_FMEM_DDR_EN_S  0
-
-#define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE4)
-/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
-]}..*/
-#define SPI_MEM_SPI_SMEM_HYPERBUS_CA    (BIT(30))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M  (BIT(30))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V  0x1
-#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S  30
-/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
- means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
-, 1'b0}..*/
-#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
-#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
-#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V  0x1
-#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S  29
-/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV    (BIT(28))
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M  (BIT(28))
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V  0x1
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S  28
-/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
-ccesses to flash or SPI1 accesses flash or sram..*/
-#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V  0x1
-#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S  27
-/* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
-..*/
-#define SPI_MEM_SPI_SMEM_DQS_CA_IN    (BIT(26))
-#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M  (BIT(26))
-#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V  0x1
-#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S  26
-/* SPI_MEM_SPI_SMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Set this bit to enable the SPI HyperBus mode..*/
-#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE    (BIT(25))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M  (BIT(25))
-#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S  25
-/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Set this bit to enable the differential SPI_CLK#..*/
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN    (BIT(24))
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M  (BIT(24))
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S  24
-/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK
- as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is
- not active..*/
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE    (BIT(22))
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M  (BIT(22))
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S  22
-/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: Use internal signal  as data strobe, the strobe can not be delayed by input t
-iming module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe ca
-n be delayed by input timing module.*/
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP    (BIT(21))
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M  (BIT(21))
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S  21
-/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
-/*description: The delay number of data strobe which from memory based on SPI_CLK..*/
-#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD    0x0000007F
-#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S))
-#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V  0x7F
-#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S  14
-/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when
-accesses to external RAM..*/
-#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
-#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
-#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S  13
-/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
-/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when
- accesses to external RAM..*/
-#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
-#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
-#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S  12
-/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
-/*description: It is the minimum output data length in the ddr psram..*/
-#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN    0x0000007F
-#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S))
-#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V  0x7F
-#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S  5
-/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: the bit is used to disable dual edge in CMD phase when ddr mode..*/
-#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS    (BIT(4))
-#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M  (BIT(4))
-#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S  4
-/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set the bit to reorder tx data of the word in spi ddr mode..*/
-#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP    (BIT(3))
-#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M  (BIT(3))
-#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S  3
-/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set the bit to reorder rx data of the word in spi ddr mode..*/
-#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP    (BIT(2))
-#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M  (BIT(2))
-#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S  2
-/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set the bit to enable variable dummy cycle in spi ddr mode..*/
-#define SPI_MEM_SPI_SMEM_VAR_DUMMY    (BIT(1))
-#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M  (BIT(1))
-#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V  0x1
-#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S  1
-/* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: in ddr mode,  0 in sdr mode.*/
-#define SPI_MEM_SPI_SMEM_DDR_EN    (BIT(0))
-#define SPI_MEM_SPI_SMEM_DDR_EN_M  (BIT(0))
-#define SPI_MEM_SPI_SMEM_DDR_EN_V  0x1
-#define SPI_MEM_SPI_SMEM_DDR_EN_S  0
-
-#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE8)
-/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
-#define SPI_MEM_CLK_EN    (BIT(0))
-#define SPI_MEM_CLK_EN_M  (BIT(0))
-#define SPI_MEM_CLK_EN_V  0x1
-#define SPI_MEM_CLK_EN_S  0
-
-#define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xEC)
-/* SPI_MEM_CORE_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: When the digital system clock selects PLL clock and the frequency of PLL clock i
-s 480MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: SPI0/1 module clock (MSPI_CORE_
-CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz.  2: MSPI_CORE_CLK is 160MHz. 3: MSPI_
-CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the freq
-uency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: MSPI_CORE_C
-LK is 80MHz. 1: MSPI_CORE_CLK is 80MHz.  2: MSPI_CORE_CLK 160MHz. 3: Not used. .*/
-#define SPI_MEM_CORE_CLK_SEL    0x00000003
-#define SPI_MEM_CORE_CLK_SEL_M  ((SPI_MEM_CORE_CLK_SEL_V)<<(SPI_MEM_CORE_CLK_SEL_S))
-#define SPI_MEM_CORE_CLK_SEL_V  0x3
-#define SPI_MEM_CORE_CLK_SEL_S  0
-
-#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF0)
-/* SPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(4))
-#define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(4))
-#define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
-#define SPI_MEM_ECC_ERR_INT_ENA_S  4
-/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(3))
-#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(3))
-#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ENA_S  3
-/* SPI_MEM_TOTAL_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
-#define SPI_MEM_TOTAL_TRANS_END_INT_ENA    (BIT(2))
-#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_M  (BIT(2))
-#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_V  0x1
-#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_S  2
-/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ENA_V  0x1
-#define SPI_MEM_PES_END_INT_ENA_S  1
-/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ENA_V  0x1
-#define SPI_MEM_PER_END_INT_ENA_S  0
-
-#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF4)
-/* SPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_ME
-M_ECC_ERR_CNT will be cleared by the pulse of this bit..*/
-#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(4))
-#define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(4))
-#define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
-#define SPI_MEM_ECC_ERR_INT_CLR_S  4
-/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(3))
-#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(3))
-#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_CLR_S  3
-/* SPI_MEM_TOTAL_TRANS_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
-#define SPI_MEM_TOTAL_TRANS_END_INT_CLR    (BIT(2))
-#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_M  (BIT(2))
-#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_V  0x1
-#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_S  2
-/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_CLR_V  0x1
-#define SPI_MEM_PES_END_INT_CLR_S  1
-/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_CLR_V  0x1
-#define SPI_MEM_PER_END_INT_CLR_S  0
-
-#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF8)
-/* SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is
-set and  APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the err
-or times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_
-NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and  APB_CTRL_SECC_ERR_INT_EN is s
-et, this bit is triggered when the error times of SPI0/1 ECC read external RAM a
-re equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN
-and  APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total erro
-r times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_C
-TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN
- are cleared, this bit will not be triggered..*/
-#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(4))
-#define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(4))
-#define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
-#define SPI_MEM_ECC_ERR_INT_RAW_S  4
-/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
-chip is loosing power and RTC module sends out brown out close flash request to
-SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
- and MSPI returns to idle state. 0: Others..*/
-#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(3))
-#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(3))
-#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_RAW_S  3
-/* SPI_MEM_TOTAL_TRANS_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 tr
-ansfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/
-PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success.  0: Other
-s..*/
-#define SPI_MEM_TOTAL_TRANS_END_INT_RAW    (BIT(2))
-#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_M  (BIT(2))
-#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_V  0x1
-#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_S  2
-/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
-mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
-#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_RAW_V  0x1
-#define SPI_MEM_PES_END_INT_RAW_S  1
-/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
-mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
-#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_RAW_V  0x1
-#define SPI_MEM_PER_END_INT_RAW_S  0
-
-#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xFC)
-/* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
-#define SPI_MEM_ECC_ERR_INT_ST    (BIT(4))
-#define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(4))
-#define SPI_MEM_ECC_ERR_INT_ST_V  0x1
-#define SPI_MEM_ECC_ERR_INT_ST_S  4
-/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
-#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(3))
-#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(3))
-#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
-#define SPI_MEM_BROWN_OUT_INT_ST_S  3
-/* SPI_MEM_TOTAL_TRANS_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
-#define SPI_MEM_TOTAL_TRANS_END_INT_ST    (BIT(2))
-#define SPI_MEM_TOTAL_TRANS_END_INT_ST_M  (BIT(2))
-#define SPI_MEM_TOTAL_TRANS_END_INT_ST_V  0x1
-#define SPI_MEM_TOTAL_TRANS_END_INT_ST_S  2
-/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
-#define SPI_MEM_PES_END_INT_ST    (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
-#define SPI_MEM_PES_END_INT_ST_V  0x1
-#define SPI_MEM_PES_END_INT_ST_S  1
-/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
-#define SPI_MEM_PER_END_INT_ST    (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
-#define SPI_MEM_PER_END_INT_ST_V  0x1
-#define SPI_MEM_PER_END_INT_ST_S  0
-
-#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
-/* SPI_MEM_DATE : R/W ;bitpos:[27:5] ;default: 23'h108082 ; */
-/*description: SPI register version..*/
-#define SPI_MEM_DATE    0x007FFFFF
-#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
-#define SPI_MEM_DATE_V  0x7FFFFF
-#define SPI_MEM_DATE_S  5
-/* SPI_MEM_SPICLK_PAD_DRV_CTL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD  is controlled b
-y the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The
- driver of SPI_CLK PAD  is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK
- PAD..*/
-#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN    (BIT(4))
-#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_M  (BIT(4))
-#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V  0x1
-#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S  4
-/* SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0
-] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash..*/
-#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV    0x00000003
-#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_M  ((SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S))
-#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V  0x3
-#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S  2
-/* SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: The driver of SPI_CLK PAD  is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0
-] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RA
-M..*/
-#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV    0x00000003
-#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_M  ((SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S))
-#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V  0x3
-#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/spi_mem_struct.h b/components/soc/esp32s3/include/soc/spi_mem_struct.h
deleted file mode 100644
index aa6f388653c..00000000000
--- a/components/soc/esp32s3/include/soc/spi_mem_struct.h
+++ /dev/null
@@ -1,781 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SPI_MEM_STRUCT_H_
-#define _SOC_SPI_MEM_STRUCT_H_
-
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct spi_mem_dev_s {
-    union {
-        struct {
-            uint32_t reserved0                     :    17;  /*reserved*/
-            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_res                     :    1;  /*This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~64 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
-            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    3;  /*reserved*/
-            uint32_t fdummy_out                    :    1;  /*In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
-            uint32_t fdout_oct                     :    1;  /*Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.*/
-            uint32_t fdin_oct                      :    1;  /*Set this bit to enable 8-bit-mode(8-bm) in DIN phase.*/
-            uint32_t faddr_oct                     :    1;  /*Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.*/
-            uint32_t fcmd_dual                     :    1;  /*Set this bit to enable 2-bit-mode(2-bm) in CMD phase.*/
-            uint32_t fcmd_quad                     :    1;  /*Set this bit to enable 4-bit-mode(4-bm) in CMD phase.*/
-            uint32_t fcmd_oct                      :    1;  /*Set this bit to enable 8-bit-mode(8-bm) in CMD phase.*/
-            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
-            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
-            uint32_t reserved12                    :    1;  /*reserved*/
-            uint32_t fastrd_mode                   :    1;  /*This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.*/
-            uint32_t fread_dual                    :    1;  /*In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. */
-            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
-            uint32_t reserved16                    :    2;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
-            uint32_t fread_quad                    :    1;  /*In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
-            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
-            uint32_t wrsr_2b                       :    1;  /*Two bytes data will be written to status register when it is set. 1: enable 0: disable. */
-            uint32_t fread_dio                     :    1;  /*In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. */
-            uint32_t fread_qio                     :    1;  /*In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.*/
-            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.*/
-            uint32_t reserved2                     :    18;  /*reserved*/
-            uint32_t rxfifo_rst                    :    1;  /*SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } ctrl1;
-    union {
-        struct {
-            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
-            uint32_t cs_hold_time                  :    5;  /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
-            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.*/
-            uint32_t ecc_skip_page_corner          :    1;  /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
-            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
-            uint32_t reserved15                    :    10;  /*reserved*/
-            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t sync_reset                    :    1;  /*The FSM will be reset.*/
-        };
-        uint32_t val;
-    } ctrl2;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    8;  /*It must equal to the value of SPI_MEM_CLKCNT_N. */
-            uint32_t clkcnt_h                      :    8;  /*It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).*/
-            uint32_t clkcnt_n                      :    8;  /*When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/
-            uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t clk_equ_sysclk                :    1;  /*When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t cs_hold                       :    1;  /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
-            uint32_t cs_setup                      :    1;  /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
-            uint32_t reserved8                     :    1;  /*reserved*/
-            uint32_t ck_out_edge                   :    1;  /*This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. */
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.*/
-            uint32_t fwrite_quad                   :    1;  /*Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.*/
-            uint32_t fwrite_dio                    :    1;  /*Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.*/
-            uint32_t fwrite_qio                    :    1;  /*Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.*/
-            uint32_t reserved16                    :    8;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
-            uint32_t usr_mosi_highpart             :    1;  /*DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
-            uint32_t usr_dummy_idle                :    1;  /*SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.*/
-            uint32_t usr_mosi                      :    1;  /*Set this bit to enable the DOUT phase of an write-data operation.*/
-            uint32_t usr_miso                      :    1;  /*Set this bit to enable enable the DIN phase of a read-data operation.*/
-            uint32_t usr_dummy                     :    1;  /*Set this bit to enable enable the DUMMY phase of an operation.*/
-            uint32_t usr_addr                      :    1;  /*Set this bit to enable enable the ADDR phase of an operation.*/
-            uint32_t usr_command                   :    1;  /*Set this bit to enable enable the CMD phase of an operation.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    6;  /*The SPI_CLK cycle length minus 1 of DUMMY phase.*/
-            uint32_t reserved6                     :    20;  /*reserved*/
-            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of ADDR phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of user defined(USR) command.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of CMD phase. The register value shall be (bit_num-1)*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of DOUT phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } mosi_dlen;
-    union {
-        struct {
-            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of DIN phase. The register value shall be (bit_num-1).*/
-            uint32_t reserved10                    :    22;  /*reserved*/
-        };
-        uint32_t val;
-    } miso_dlen;
-    union {
-        struct {
-            uint32_t status                        :    16;  /*The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit.*/
-            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with SPI_MEM_FASTRD_MODE bit.*/
-            uint32_t reserved24                    :    8;  /*reserved*/
-        };
-        uint32_t val;
-    } rd_status;
-    uint32_t ext_addr;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts.*/
-            uint32_t cs1_dis                       :    1;  /*Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts.*/
-            uint32_t reserved0                     :    5;  /*reserved*/
-            uint32_t fsub_pin                      :    1;  /*Flash is connected to SPI SUBPIN bus.*/
-            uint32_t ssub_pin                      :    1;  /*Ext_RAM is connected to SPI SUBPIN bus.*/
-            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle */
-            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
-            uint32_t auto_per                      :    1;  /*Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } misc;
-    uint32_t tx_crc;
-    union {
-        struct {
-            uint32_t req_en                        :    1;  /*Set this bit to enable Cache's access and SPI0's transfer.*/
-            uint32_t usr_cmd_4byte                 :    1;  /*Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.*/
-            uint32_t flash_usr_cmd                 :    1;  /*1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.*/
-            uint32_t fdin_dual                     :    1;  /*When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.*/
-            uint32_t fdout_dual                    :    1;  /*When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.*/
-            uint32_t faddr_dual                    :    1;  /*When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.*/
-            uint32_t fdin_quad                     :    1;  /*When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.*/
-            uint32_t fdout_quad                    :    1;  /*When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.*/
-            uint32_t faddr_quad                    :    1;  /*When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } cache_fctrl;
-    union {
-        struct {
-            uint32_t usr_scmd_4byte                :    1;  /*Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.*/
-            uint32_t usr_sram_dio                  :    1;  /*Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.*/
-            uint32_t usr_sram_qio                  :    1;  /*Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.*/
-            uint32_t usr_wr_sram_dummy             :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.*/
-            uint32_t usr_rd_sram_dummy             :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.*/
-            uint32_t usr_rcmd                      :    1;  /*1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.*/
-            uint32_t sram_rdummy_cyclelen          :    6;  /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.*/
-            uint32_t reserved12                    :    2;  /*reserved*/
-            uint32_t sram_addr_bitlen              :    6;  /*When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).*/
-            uint32_t usr_wcmd                      :    1;  /*1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.*/
-            uint32_t sram_oct                      :    1;  /*Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.*/
-            uint32_t sram_wdummy_cyclelen          :    6;  /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } cache_sctrl;
-    union {
-        struct {
-            uint32_t sclk_mode                     :    2;  /*SPI_CLK mode bits  when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.*/
-            uint32_t swb_mode                      :    8;  /*Mode bits when SPI0 accesses to Ext_RAM.*/
-            uint32_t sdin_dual                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.*/
-            uint32_t sdout_dual                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.*/
-            uint32_t saddr_dual                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.*/
-            uint32_t scmd_dual                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.*/
-            uint32_t sdin_quad                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.*/
-            uint32_t sdout_quad                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.*/
-            uint32_t saddr_quad                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.*/
-            uint32_t scmd_quad                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.*/
-            uint32_t sdin_oct                      :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.*/
-            uint32_t sdout_oct                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.*/
-            uint32_t saddr_oct                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.*/
-            uint32_t scmd_oct                      :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.*/
-            uint32_t sdummy_out                    :    1;  /*When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
-            uint32_t reserved23                    :    9;  /*reserved*/
-        };
-        uint32_t val;
-    } sram_cmd;
-    union {
-        struct {
-            uint32_t usr_rd_cmd_value              :    16;  /*When SPI0 reads Ext_RAM, it is the command value of CMD phase.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_rd_cmd_bitlen             :    4;  /*When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_drd_cmd;
-    union {
-        struct {
-            uint32_t usr_wr_cmd_value              :    16;  /*When SPI0 writes Ext_RAM, it is the command value of CMD phase.*/
-            uint32_t reserved16                    :    12;  /*reserved*/
-            uint32_t usr_wr_cmd_bitlen             :    4;  /*When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
-        };
-        uint32_t val;
-    } sram_dwr_cmd;
-    union {
-        struct {
-            uint32_t cnt_l                         :    8;  /*It must equal to the value of SPI_MEM_SCLKCNT_N. */
-            uint32_t cnt_h                         :    8;  /*It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1).*/
-            uint32_t cnt_n                         :    8;  /*When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)*/
-            uint32_t reserved24                    :    7;  /*reserved*/
-            uint32_t equ_sysclk                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
-        };
-        uint32_t val;
-    } sram_clk;
-    union {
-        struct {
-            uint32_t st                            :    3;  /*The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } fsm;
-    uint32_t data_buf[16];                                                /*data buffer*/
-    union {
-        struct {
-            uint32_t waiti_en                      :    1;  /*Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.*/
-            uint32_t waiti_dummy                   :    1;  /*Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR).*/
-            uint32_t waiti_cmd                     :    8;  /*The command value of auto wait flash idle transfer(RDSR).*/
-            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } flash_waiti_ctrl;
-    union {
-        struct {
-            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
-            uint32_t flash_per_wait_en             :    1;  /*Set this bit to add delay time after program erase resume(PER) is sent.*/
-            uint32_t flash_pes_wait_en             :    1;  /*Set this bit to add delay time after program erase suspend(PES) command is sent.*/
-            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES transfer trigger PES transfer option.*/
-            uint32_t pesr_idle_en                  :    1;  /*1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.*/
-            uint32_t reserved6                     :    26;  /*reserved*/
-        };
-        uint32_t val;
-    } flash_sus_cmd;
-    union {
-        struct {
-            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable auto-suspend function.*/
-            uint32_t flash_per_command             :    8;  /*Program/Erase resume command value.*/
-            uint32_t flash_pes_command             :    8;  /*Program/Erase suspend command value.*/
-            uint32_t reserved17                    :    15;  /*reserved*/
-        };
-        uint32_t val;
-    } flash_sus_ctrl;
-    union {
-        struct {
-            uint32_t flash_sus                     :    1;  /*The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1.*/
-            uint32_t reserved1                     :    1;  /*reserved*/
-            uint32_t flash_hpm_dly_256             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
-            uint32_t flash_res_dly_256             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
-            uint32_t flash_dp_dly_256              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
-            uint32_t flash_per_dly_256             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
-            uint32_t flash_pes_dly_256             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
-            uint32_t reserved7                     :    25;  /*reserved*/
-        };
-        uint32_t val;
-    } sus_status;
-    union {
-        struct {
-            uint32_t timing_clk_ena                :    1;  /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
-            uint32_t timing_cali                   :    1;  /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
-            uint32_t extra_dummy_cyclelen          :    3;  /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } timing_cali;
-    union {
-        struct {
-            uint32_t din0_mode                     :    3;  /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t din1_mode                     :    3;  /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t din2_mode                     :    3;  /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t din3_mode                     :    3;  /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t din4_mode                     :    3;  /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t din5_mode                     :    3;  /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t din6_mode                     :    3;  /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t din7_mode                     :    3;  /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t dins_mode                     :    3;  /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*SPI_D input delay number.*/
-            uint32_t din1_num                      :    2;  /*SPI_Q input delay number.*/
-            uint32_t din2_num                      :    2;  /*SPI_WP input delay number.*/
-            uint32_t din3_num                      :    2;  /*SPI_HD input delay number.*/
-            uint32_t din4_num                      :    2;  /*SPI_IO4 input delay number.*/
-            uint32_t din5_num                      :    2;  /*SPI_IO5 input delay number.*/
-            uint32_t din6_num                      :    2;  /*SPI_IO6 input delay number.*/
-            uint32_t din7_num                      :    2;  /*SPI_IO7 input delay number.*/
-            uint32_t dins_num                      :    2;  /*SPI_DQS input delay number.*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t dout1_mode                    :    1;  /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t dout2_mode                    :    1;  /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t dout3_mode                    :    1;  /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t dout4_mode                    :    1;  /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t dout5_mode                    :    1;  /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t dout6_mode                    :    1;  /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t dout7_mode                    :    1;  /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t douts_mode                    :    1;  /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    uint32_t reserved_b8;
-    union {
-        struct {
-            uint32_t smem_timing_clk_ena           :    1;  /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
-            uint32_t smem_timing_cali              :    1;  /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
-            uint32_t smem_extra_dummy_cyclelen     :    3;  /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_timing_cali;
-    union {
-        struct {
-            uint32_t smem_din0_mode                :    3;  /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_din1_mode                :    3;  /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_din2_mode                :    3;  /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_din3_mode                :    3;  /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_din4_mode                :    3;  /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_din5_mode                :    3;  /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_din6_mode                :    3;  /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_din7_mode                :    3;  /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_dins_mode                :    3;  /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_mode;
-    union {
-        struct {
-            uint32_t smem_din0_num                 :    2;  /*SPI_D input delay number.*/
-            uint32_t smem_din1_num                 :    2;  /*SPI_Q input delay number.*/
-            uint32_t smem_din2_num                 :    2;  /*SPI_WP input delay number.*/
-            uint32_t smem_din3_num                 :    2;  /*SPI_HD input delay number.*/
-            uint32_t smem_din4_num                 :    2;  /*SPI_IO4 input delay number.*/
-            uint32_t smem_din5_num                 :    2;  /*SPI_IO5 input delay number.*/
-            uint32_t smem_din6_num                 :    2;  /*SPI_IO6 input delay number.*/
-            uint32_t smem_din7_num                 :    2;  /*SPI_IO7 input delay number.*/
-            uint32_t smem_dins_num                 :    2;  /*SPI_DQS input delay number.*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_din_num;
-    union {
-        struct {
-            uint32_t smem_dout0_mode               :    1;  /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_dout1_mode               :    1;  /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_dout2_mode               :    1;  /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_dout3_mode               :    1;  /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_dout4_mode               :    1;  /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_dout5_mode               :    1;  /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_dout6_mode               :    1;  /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_dout7_mode               :    1;  /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t smem_douts_mode               :    1;  /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_dout_mode;
-    union {
-        struct {
-            uint32_t ecc_err_int_num               :    8;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t fmem_ecc_err_int_en           :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } ecc_ctrl;
-    uint32_t ecc_err_addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;  /*reserved*/
-            uint32_t ecc_data_err_bit              :    7;  /*It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
-            uint32_t ecc_chk_err_bit               :    3;  /*When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte.*/
-            uint32_t ecc_byte_err                  :    1;  /*It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
-            uint32_t ecc_err_cnt                   :    8;  /*This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } ecc_err_bit;
-    uint32_t reserved_d8;
-    union {
-        struct {
-            uint32_t smem_cs_setup                 :    1;  /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
-            uint32_t smem_cs_hold                  :    1;  /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
-            uint32_t smem_cs_setup_time            :    5;  /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
-            uint32_t smem_cs_hold_time             :    5;  /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
-            uint32_t smem_ecc_cs_hold_time         :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM.*/
-            uint32_t smem_ecc_skip_page_corner     :    1;  /*1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM.*/
-            uint32_t smem_ecc_16to18_byte_en       :    1;  /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM.*/
-            uint32_t reserved17                    :    7;  /*reserved*/
-            uint32_t smem_ecc_err_int_en           :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
-            uint32_t smem_cs_hold_delay            :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ac;
-    union {
-        struct {
-            uint32_t fmem_ddr_en                   :    1;  /*1: in ddr mode,  0 in sdr mode*/
-            uint32_t fmem_var_dummy                :    1;  /*Set the bit to enable variable dummy cycle in DDR mode.*/
-            uint32_t fmem_ddr_rdat_swp             :    1;  /*Set the bit to reorder RX data of the word in DDR mode.*/
-            uint32_t fmem_ddr_wdat_swp             :    1;  /*Set the bit to swap TX data of a word in DDR mode.*/
-            uint32_t fmem_ddr_cmd_dis              :    1;  /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
-            uint32_t fmem_outminbytelen            :    7;  /*It is the minimum output data length in the panda device.*/
-            uint32_t fmem_tx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.*/
-            uint32_t fmem_rx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.*/
-            uint32_t fmem_usr_ddr_dqs_thd          :    7;  /*The delay number of data strobe which from memory based on SPI_CLK.*/
-            uint32_t fmem_ddr_dqs_loop             :    1;  /*1: Use internal signal  as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
-            uint32_t fmem_ddr_dqs_loop_mode        :    1;  /*When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is not active.*/
-            uint32_t reserved23                    :    1;  /*reserved*/
-            uint32_t fmem_clk_diff_en              :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t fmem_hyperbus_mode            :    1;  /*Set this bit to enable the SPI HyperBus mode.*/
-            uint32_t fmem_dqs_ca_in                :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t fmem_hyperbus_dummy_2x        :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
-            uint32_t fmem_clk_diff_inv             :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
-            uint32_t fmem_octa_ram_addr            :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t fmem_hyperbus_ca              :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } ddr;
-    union {
-        struct {
-            uint32_t smem_ddr_en                   :    1;  /*1: in ddr mode,  0 in sdr mode*/
-            uint32_t smem_var_dummy                :    1;  /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
-            uint32_t smem_ddr_rdat_swp             :    1;  /*Set the bit to reorder rx data of the word in spi ddr mode.*/
-            uint32_t smem_ddr_wdat_swp             :    1;  /*Set the bit to reorder tx data of the word in spi ddr mode.*/
-            uint32_t smem_ddr_cmd_dis              :    1;  /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
-            uint32_t smem_outminbytelen            :    7;  /*It is the minimum output data length in the ddr psram.*/
-            uint32_t smem_tx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM.*/
-            uint32_t smem_rx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM.*/
-            uint32_t smem_usr_ddr_dqs_thd          :    7;  /*The delay number of data strobe which from memory based on SPI_CLK.*/
-            uint32_t smem_ddr_dqs_loop             :    1;  /*1: Use internal signal  as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
-            uint32_t smem_ddr_dqs_loop_mode        :    1;  /*When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is not active.*/
-            uint32_t reserved23                    :    1;  /*reserved*/
-            uint32_t smem_clk_diff_en              :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
-            uint32_t smem_hyperbus_mode            :    1;  /*Set this bit to enable the SPI HyperBus mode.*/
-            uint32_t smem_dqs_ca_in                :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
-            uint32_t smem_hyperbus_dummy_2x        :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
-            uint32_t smem_clk_diff_inv             :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
-            uint32_t smem_octa_ram_addr            :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
-            uint32_t smem_hyperbus_ca              :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
-            uint32_t reserved31                    :    1;  /*reserved*/
-        };
-        uint32_t val;
-    } spi_smem_ddr;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
-            uint32_t reserved1                     :    31;  /*reserved*/
-        };
-        uint32_t val;
-    } clock_gate;
-    union {
-        struct {
-            uint32_t core_clk_sel                  :    2;  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz.  2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz.  2: MSPI_CORE_CLK 160MHz. 3: Not used. */
-            uint32_t reserved2                     :    30;  /*reserved*/
-        };
-        uint32_t val;
-    } core_clk_sel;
-    union {
-        struct {
-            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t total_trans_end_en            :    1;  /*The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
-            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t per_end_int_clr               :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_int_clr               :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t total_trans_end_int_clr       :    1;  /*The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
-            uint32_t brown_out_int_clr             :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t ecc_err_int_clr               :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t per_end_int_raw               :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
-            uint32_t pes_end_int_raw               :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
-            uint32_t total_trans_end_int_raw       :    1;  /*The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success.  0: Others.*/
-            uint32_t brown_out_int_raw             :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
-            uint32_t ecc_err_int_raw               :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and  APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and  APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t per_end_int_st                :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
-            uint32_t pes_end_int_st                :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
-            uint32_t total_trans_end_int_st        :    1;  /*The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
-            uint32_t brown_out_int_st              :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
-            uint32_t ecc_err_int_st                :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
-            uint32_t reserved5                     :    27;  /*reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    union {
-        struct {
-            uint32_t reg_smem_spiclk_fun_drv       :    2;  /*The driver of SPI_CLK PAD  is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM.*/
-            uint32_t fmem_spiclk_fun_drv           :    2;  /*The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash.*/
-            uint32_t reg_spiclk_pad_drv_ctl_en     :    1;  /*SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD  is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD.*/
-            uint32_t date                          :    23;  /*SPI register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_mem_dev_t;
-extern spi_mem_dev_t SPIMEM0;
-extern spi_mem_dev_t SPIMEM1;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_MEM_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/spi_reg.h b/components/soc/esp32s3/include/soc/spi_reg.h
deleted file mode 100644
index 533158870ae..00000000000
--- a/components/soc/esp32s3/include/soc/spi_reg.h
+++ /dev/null
@@ -1,1757 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SPI_REG_H_
-#define _SOC_SPI_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
-/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
-/*description: User define command enable.  An operation will be triggered when the bit is set.
- The bit will be cleared once the operation done.1: enable 0: disable. Can not b
-e changed by CONF_buf..*/
-#define SPI_USR    (BIT(24))
-#define SPI_USR_M  (BIT(24))
-#define SPI_USR_V  0x1
-#define SPI_USR_S  24
-/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
-/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
-clock domain, which is only used in SPI master mode..*/
-#define SPI_UPDATE    (BIT(23))
-#define SPI_UPDATE_M  (BIT(23))
-#define SPI_UPDATE_V  0x1
-#define SPI_UPDATE_S  23
-/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: Define the APB cycles of  SPI_CONF state. Can be configured in CONF state..*/
-#define SPI_CONF_BITLEN    0x0003FFFF
-#define SPI_CONF_BITLEN_M  ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
-#define SPI_CONF_BITLEN_V  0x3FFFF
-#define SPI_CONF_BITLEN_S  0
-
-#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
-/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Address to slave. Can be configured in CONF state..*/
-#define SPI_USR_ADDR_VALUE    0xFFFFFFFF
-#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
-#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
-#define SPI_USR_ADDR_VALUE_S  0
-
-#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
-/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */
-/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
-figured in CONF state..*/
-#define SPI_WR_BIT_ORDER    0x00000003
-#define SPI_WR_BIT_ORDER_M  ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
-#define SPI_WR_BIT_ORDER_V  0x3
-#define SPI_WR_BIT_ORDER_S  25
-/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
-/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
-tate..*/
-#define SPI_RD_BIT_ORDER    0x00000003
-#define SPI_RD_BIT_ORDER_M  ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
-#define SPI_RD_BIT_ORDER_V  0x3
-#define SPI_RD_BIT_ORDER_S  23
-/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
-/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
-an be configured in CONF state..*/
-#define SPI_WP_POL    (BIT(21))
-#define SPI_WP_POL_M  (BIT(21))
-#define SPI_WP_POL_V  0x1
-#define SPI_WP_POL_S  21
-/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
-/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co
-nfigured in CONF state..*/
-#define SPI_HOLD_POL    (BIT(20))
-#define SPI_HOLD_POL_M  (BIT(20))
-#define SPI_HOLD_POL_V  0x1
-#define SPI_HOLD_POL_S  20
-/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
-/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-CONF state..*/
-#define SPI_D_POL    (BIT(19))
-#define SPI_D_POL_M  (BIT(19))
-#define SPI_D_POL_V  0x1
-#define SPI_D_POL_S  19
-/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
-/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-CONF state..*/
-#define SPI_Q_POL    (BIT(18))
-#define SPI_Q_POL_M  (BIT(18))
-#define SPI_Q_POL_V  0x1
-#define SPI_Q_POL_S  18
-/* SPI_FREAD_OCT : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  C
-an be configured in CONF state..*/
-#define SPI_FREAD_OCT    (BIT(16))
-#define SPI_FREAD_OCT_M  (BIT(16))
-#define SPI_FREAD_OCT_V  0x1
-#define SPI_FREAD_OCT_S  16
-/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  C
-an be configured in CONF state..*/
-#define SPI_FREAD_QUAD    (BIT(15))
-#define SPI_FREAD_QUAD_M  (BIT(15))
-#define SPI_FREAD_QUAD_V  0x1
-#define SPI_FREAD_QUAD_S  15
-/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C
-an be configured in CONF state..*/
-#define SPI_FREAD_DUAL    (BIT(14))
-#define SPI_FREAD_DUAL_M  (BIT(14))
-#define SPI_FREAD_DUAL_V  0x1
-#define SPI_FREAD_DUAL_S  14
-/* SPI_FCMD_OCT : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Apply 8 signals during command phase 1:enable 0: disable. Can be configured in C
-ONF state..*/
-#define SPI_FCMD_OCT    (BIT(10))
-#define SPI_FCMD_OCT_M  (BIT(10))
-#define SPI_FCMD_OCT_V  0x1
-#define SPI_FCMD_OCT_S  10
-/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
-ONF state..*/
-#define SPI_FCMD_QUAD    (BIT(9))
-#define SPI_FCMD_QUAD_M  (BIT(9))
-#define SPI_FCMD_QUAD_V  0x1
-#define SPI_FCMD_QUAD_S  9
-/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C
-ONF state..*/
-#define SPI_FCMD_DUAL    (BIT(8))
-#define SPI_FCMD_DUAL_M  (BIT(8))
-#define SPI_FCMD_DUAL_V  0x1
-#define SPI_FCMD_DUAL_S  8
-/* SPI_FADDR_OCT : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- state..*/
-#define SPI_FADDR_OCT    (BIT(7))
-#define SPI_FADDR_OCT_M  (BIT(7))
-#define SPI_FADDR_OCT_V  0x1
-#define SPI_FADDR_OCT_S  7
-/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- state..*/
-#define SPI_FADDR_QUAD    (BIT(6))
-#define SPI_FADDR_QUAD_M  (BIT(6))
-#define SPI_FADDR_QUAD_V  0x1
-#define SPI_FADDR_QUAD_S  6
-/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
- state..*/
-#define SPI_FADDR_DUAL    (BIT(5))
-#define SPI_FADDR_DUAL_M  (BIT(5))
-#define SPI_FADDR_DUAL_V  0x1
-#define SPI_FADDR_DUAL_S  5
-/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phas
-e, the FSPI bus signals are output. Can be configured in CONF state..*/
-#define SPI_DUMMY_OUT    (BIT(3))
-#define SPI_DUMMY_OUT_M  (BIT(3))
-#define SPI_DUMMY_OUT_V  0x1
-#define SPI_DUMMY_OUT_S  3
-
-#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0xC)
-/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst
-em clock. Can be configured in CONF state..*/
-#define SPI_CLK_EQU_SYSCLK    (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
-#define SPI_CLK_EQU_SYSCLK_V  0x1
-#define SPI_CLK_EQU_SYSCLK_S  31
-/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
-/*description: In the master mode it is pre-divider of spi_clk.  Can be configured in CONF stat
-e..*/
-#define SPI_CLKDIV_PRE    0x0000000F
-#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
-#define SPI_CLKDIV_PRE_V  0xF
-#define SPI_CLKDIV_PRE_S  18
-/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
-/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/
-(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
-#define SPI_CLKCNT_N    0x0000003F
-#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
-#define SPI_CLKCNT_N_V  0x3F
-#define SPI_CLKCNT_N_S  12
-/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
-/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-must be 0. Can be configured in CONF state..*/
-#define SPI_CLKCNT_H    0x0000003F
-#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
-#define SPI_CLKCNT_H_V  0x3F
-#define SPI_CLKCNT_H_S  6
-/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
-/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b
-e 0. Can be configured in CONF state..*/
-#define SPI_CLKCNT_L    0x0000003F
-#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
-#define SPI_CLKCNT_L_V  0x3F
-#define SPI_CLKCNT_L_S  0
-
-#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x10)
-/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
-/*description: This bit enable the command phase of an operation. Can be configured in CONF sta
-te..*/
-#define SPI_USR_COMMAND    (BIT(31))
-#define SPI_USR_COMMAND_M  (BIT(31))
-#define SPI_USR_COMMAND_V  0x1
-#define SPI_USR_COMMAND_S  31
-/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: This bit enable the address phase of an operation. Can be configured in CONF sta
-te..*/
-#define SPI_USR_ADDR    (BIT(30))
-#define SPI_USR_ADDR_M  (BIT(30))
-#define SPI_USR_ADDR_V  0x1
-#define SPI_USR_ADDR_S  30
-/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
-..*/
-#define SPI_USR_DUMMY    (BIT(29))
-#define SPI_USR_DUMMY_M  (BIT(29))
-#define SPI_USR_DUMMY_V  0x1
-#define SPI_USR_DUMMY_S  29
-/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s
-tate..*/
-#define SPI_USR_MISO    (BIT(28))
-#define SPI_USR_MISO_M  (BIT(28))
-#define SPI_USR_MISO_V  0x1
-#define SPI_USR_MISO_S  28
-/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: This bit enable the write-data phase of an operation. Can be configured in CONF
-state..*/
-#define SPI_USR_MOSI    (BIT(27))
-#define SPI_USR_MOSI_M  (BIT(27))
-#define SPI_USR_MOSI_V  0x1
-#define SPI_USR_MOSI_S  27
-/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
- CONF state..*/
-#define SPI_USR_DUMMY_IDLE    (BIT(26))
-#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
-#define SPI_USR_DUMMY_IDLE_V  0x1
-#define SPI_USR_DUMMY_IDLE_S  26
-/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl
-e 0: disable.  Can be configured in CONF state..*/
-#define SPI_USR_MOSI_HIGHPART    (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
-#define SPI_USR_MOSI_HIGHPART_V  0x1
-#define SPI_USR_MOSI_HIGHPART_S  25
-/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
- 0: disable. Can be configured in CONF state..*/
-#define SPI_USR_MISO_HIGHPART    (BIT(24))
-#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
-#define SPI_USR_MISO_HIGHPART_V  0x1
-#define SPI_USR_MISO_HIGHPART_S  24
-/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha
-re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/
-#define SPI_SIO    (BIT(17))
-#define SPI_SIO_M  (BIT(17))
-#define SPI_SIO_V  0x1
-#define SPI_SIO_S  17
-/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-will continue. 0: The seg-trans will end after the current SPI seg-trans or this
- is not seg-trans mode. Can be configured in CONF state..*/
-#define SPI_USR_CONF_NXT    (BIT(15))
-#define SPI_USR_CONF_NXT_M  (BIT(15))
-#define SPI_USR_CONF_NXT_V  0x1
-#define SPI_USR_CONF_NXT_S  15
-/* SPI_FWRITE_OCT : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 8 signals. Can be configured in CO
-NF state..*/
-#define SPI_FWRITE_OCT    (BIT(14))
-#define SPI_FWRITE_OCT_M  (BIT(14))
-#define SPI_FWRITE_OCT_V  0x1
-#define SPI_FWRITE_OCT_S  14
-/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO
-NF state..*/
-#define SPI_FWRITE_QUAD    (BIT(13))
-#define SPI_FWRITE_QUAD_M  (BIT(13))
-#define SPI_FWRITE_QUAD_V  0x1
-#define SPI_FWRITE_QUAD_S  13
-/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO
-NF state..*/
-#define SPI_FWRITE_DUAL    (BIT(12))
-#define SPI_FWRITE_DUAL_M  (BIT(12))
-#define SPI_FWRITE_DUAL_V  0x1
-#define SPI_FWRITE_DUAL_S  12
-/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca
-n be configured in CONF state..*/
-#define SPI_CK_OUT_EDGE    (BIT(9))
-#define SPI_CK_OUT_EDGE_M  (BIT(9))
-#define SPI_CK_OUT_EDGE_V  0x1
-#define SPI_CK_OUT_EDGE_S  9
-/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
-= !spi_ck_i. 1:rsck = spi_ck_i..*/
-#define SPI_RSCK_I_EDGE    (BIT(8))
-#define SPI_RSCK_I_EDGE_M  (BIT(8))
-#define SPI_RSCK_I_EDGE_V  0x1
-#define SPI_RSCK_I_EDGE_S  8
-/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be co
-nfigured in CONF state..*/
-#define SPI_CS_SETUP    (BIT(7))
-#define SPI_CS_SETUP_M  (BIT(7))
-#define SPI_CS_SETUP_V  0x1
-#define SPI_CS_SETUP_S  7
-/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be config
-ured in CONF state..*/
-#define SPI_CS_HOLD    (BIT(6))
-#define SPI_CS_HOLD_M  (BIT(6))
-#define SPI_CS_HOLD_V  0x1
-#define SPI_CS_HOLD_S  6
-/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
-= spi_ck_i. 1:tsck = !spi_ck_i..*/
-#define SPI_TSCK_I_EDGE    (BIT(5))
-#define SPI_TSCK_I_EDGE_M  (BIT(5))
-#define SPI_TSCK_I_EDGE_V  0x1
-#define SPI_TSCK_I_EDGE_S  5
-/* SPI_OPI_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others
-. Can be configured in CONF state..*/
-#define SPI_OPI_MODE    (BIT(4))
-#define SPI_OPI_MODE_M  (BIT(4))
-#define SPI_OPI_MODE_V  0x1
-#define SPI_OPI_MODE_S  4
-/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others
-. Can be configured in CONF state..*/
-#define SPI_QPI_MODE    (BIT(3))
-#define SPI_QPI_MODE_M  (BIT(3))
-#define SPI_QPI_MODE_V  0x1
-#define SPI_QPI_MODE_S  3
-/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUTDIN    (BIT(0))
-#define SPI_DOUTDIN_M  (BIT(0))
-#define SPI_DOUTDIN_V  0x1
-#define SPI_DOUTDIN_S  0
-
-#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x14)
-/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */
-/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca
-n be configured in CONF state..*/
-#define SPI_USR_ADDR_BITLEN    0x0000001F
-#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
-#define SPI_USR_ADDR_BITLEN_V  0x1F
-#define SPI_USR_ADDR_BITLEN_S  27
-/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */
-/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
- Can be configured in CONF state..*/
-#define SPI_CS_HOLD_TIME    0x0000001F
-#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
-#define SPI_CS_HOLD_TIME_V  0x1F
-#define SPI_CS_HOLD_TIME_S  22
-/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
-/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu
-p bit. Can be configured in CONF state..*/
-#define SPI_CS_SETUP_TIME    0x0000001F
-#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
-#define SPI_CS_SETUP_TIME_V  0x1F
-#define SPI_CS_SETUP_TIME_S  17
-/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
- FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
- in GP-SPI master FD/HD-mode..*/
-#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_M  (BIT(16))
-#define SPI_MST_WFULL_ERR_END_EN_V  0x1
-#define SPI_MST_WFULL_ERR_END_EN_S  16
-/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
-/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_
-num-1). Can be configured in CONF state..*/
-#define SPI_USR_DUMMY_CYCLELEN    0x000000FF
-#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
-#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
-#define SPI_USR_DUMMY_CYCLELEN_S  0
-
-#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x18)
-/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
-/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca
-n be configured in CONF state..*/
-#define SPI_USR_COMMAND_BITLEN    0x0000000F
-#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
-#define SPI_USR_COMMAND_BITLEN_V  0xF
-#define SPI_USR_COMMAND_BITLEN_S  28
-/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
-/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
-aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro
-r is valid in GP-SPI master FD/HD-mode..*/
-#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_M  (BIT(27))
-#define SPI_MST_REMPTY_ERR_END_EN_V  0x1
-#define SPI_MST_REMPTY_ERR_END_EN_S  27
-/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: The value of  command. Can be configured in CONF state..*/
-#define SPI_USR_COMMAND_VALUE    0x0000FFFF
-#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
-#define SPI_USR_COMMAND_VALUE_V  0xFFFF
-#define SPI_USR_COMMAND_VALUE_S  0
-
-#define SPI_MS_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x1C)
-/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
-/*description: The value of these bits is the configured SPI transmission data bit length in ma
-ster mode DMA controlled transfer or CPU controlled transfer. The value is also
-the configured bit length in slave mode DMA RX controlled transfer. The register
- value shall be (bit_num-1). Can be configured in CONF state..*/
-#define SPI_MS_DATA_BITLEN    0x0003FFFF
-#define SPI_MS_DATA_BITLEN_M  ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
-#define SPI_MS_DATA_BITLEN_V  0x3FFFF
-#define SPI_MS_DATA_BITLEN_S  0
-
-#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
-/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0
-:  spi quad input swap disable. Can be configured in CONF state..*/
-#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
-#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
-#define SPI_QUAD_DIN_PIN_SWAP_S  31
-/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/
-#define SPI_CS_KEEP_ACTIVE    (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
-#define SPI_CS_KEEP_ACTIVE_V  0x1
-#define SPI_CS_KEEP_ACTIVE_S  30
-/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle. Can be c
-onfigured in CONF state..*/
-#define SPI_CK_IDLE_EDGE    (BIT(29))
-#define SPI_CK_IDLE_EDGE_M  (BIT(29))
-#define SPI_CK_IDLE_EDGE_V  0x1
-#define SPI_CK_IDLE_EDGE_S  29
-/* SPI_DQS_IDLE_EDGE : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: The default value of spi_dqs. Can be configured in CONF state..*/
-#define SPI_DQS_IDLE_EDGE    (BIT(24))
-#define SPI_DQS_IDLE_EDGE_M  (BIT(24))
-#define SPI_DQS_IDLE_EDGE_V  0x1
-#define SPI_DQS_IDLE_EDGE_S  24
-/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
-CONF state..*/
-#define SPI_SLAVE_CS_POL    (BIT(23))
-#define SPI_SLAVE_CS_POL_M  (BIT(23))
-#define SPI_SLAVE_CS_POL_V  0x1
-#define SPI_SLAVE_CS_POL_S  23
-/* SPI_CMD_DTR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/
-4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be confi
-gured in CONF state..*/
-#define SPI_CMD_DTR_EN    (BIT(19))
-#define SPI_CMD_DTR_EN_M  (BIT(19))
-#define SPI_CMD_DTR_EN_V  0x1
-#define SPI_CMD_DTR_EN_S  19
-/* SPI_ADDR_DTR_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2
-/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be co
-nfigured in CONF state..*/
-#define SPI_ADDR_DTR_EN    (BIT(18))
-#define SPI_ADDR_DTR_EN_M  (BIT(18))
-#define SPI_ADDR_DTR_EN_V  0x1
-#define SPI_ADDR_DTR_EN_S  18
-/* SPI_DATA_DTR_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including mas
-ter 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR m
-ode. Can be configured in CONF state..*/
-#define SPI_DATA_DTR_EN    (BIT(17))
-#define SPI_DATA_DTR_EN_M  (BIT(17))
-#define SPI_DATA_DTR_EN_V  0x1
-#define SPI_DATA_DTR_EN_S  17
-/* SPI_CLK_DATA_DTR_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master D
-TR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19. .*/
-#define SPI_CLK_DATA_DTR_EN    (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_M  (BIT(16))
-#define SPI_CLK_DATA_DTR_EN_V  0x1
-#define SPI_CLK_DATA_DTR_EN_S  16
-/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
-/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva
-lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/
-#define SPI_MASTER_CS_POL    0x0000003F
-#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
-#define SPI_MASTER_CS_POL_V  0x3F
-#define SPI_MASTER_CS_POL_S  7
-/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: 1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state..*/
-#define SPI_CK_DIS    (BIT(6))
-#define SPI_CK_DIS_M  (BIT(6))
-#define SPI_CK_DIS_V  0x1
-#define SPI_CK_DIS_S  6
-/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS5_DIS    (BIT(5))
-#define SPI_CS5_DIS_M  (BIT(5))
-#define SPI_CS5_DIS_V  0x1
-#define SPI_CS5_DIS_S  5
-/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS4_DIS    (BIT(4))
-#define SPI_CS4_DIS_M  (BIT(4))
-#define SPI_CS4_DIS_V  0x1
-#define SPI_CS4_DIS_S  4
-/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS3_DIS    (BIT(3))
-#define SPI_CS3_DIS_M  (BIT(3))
-#define SPI_CS3_DIS_V  0x1
-#define SPI_CS3_DIS_S  3
-/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS2_DIS    (BIT(2))
-#define SPI_CS2_DIS_M  (BIT(2))
-#define SPI_CS2_DIS_V  0x1
-#define SPI_CS2_DIS_S  2
-/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS1_DIS    (BIT(1))
-#define SPI_CS1_DIS_M  (BIT(1))
-#define SPI_CS1_DIS_V  0x1
-#define SPI_CS1_DIS_S  1
-/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
-n be configured in CONF state..*/
-#define SPI_CS0_DIS    (BIT(0))
-#define SPI_CS0_DIS_M  (BIT(0))
-#define SPI_CS0_DIS_V  0x1
-#define SPI_CS0_DIS_S  0
-
-#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x24)
-/* SPI_TIMING_HCLK_ACTIVE : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: 1:enable hclk in SPI input timing module.  0: disable it. Can be configured in C
-ONF state..*/
-#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_M  (BIT(16))
-#define SPI_TIMING_HCLK_ACTIVE_V  0x1
-#define SPI_TIMING_HCLK_ACTIVE_S  16
-/* SPI_DIN7_MODE : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN7_MODE    0x00000003
-#define SPI_DIN7_MODE_M  ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S))
-#define SPI_DIN7_MODE_V  0x3
-#define SPI_DIN7_MODE_S  14
-/* SPI_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN6_MODE    0x00000003
-#define SPI_DIN6_MODE_M  ((SPI_DIN6_MODE_V)<<(SPI_DIN6_MODE_S))
-#define SPI_DIN6_MODE_V  0x3
-#define SPI_DIN6_MODE_S  12
-/* SPI_DIN5_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN5_MODE    0x00000003
-#define SPI_DIN5_MODE_M  ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S))
-#define SPI_DIN5_MODE_V  0x3
-#define SPI_DIN5_MODE_S  10
-/* SPI_DIN4_MODE : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN4_MODE    0x00000003
-#define SPI_DIN4_MODE_M  ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S))
-#define SPI_DIN4_MODE_V  0x3
-#define SPI_DIN4_MODE_S  8
-/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN3_MODE    0x00000003
-#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
-#define SPI_DIN3_MODE_V  0x3
-#define SPI_DIN3_MODE_S  6
-/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN2_MODE    0x00000003
-#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
-#define SPI_DIN2_MODE_V  0x3
-#define SPI_DIN2_MODE_S  4
-/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN1_MODE    0x00000003
-#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
-#define SPI_DIN1_MODE_V  0x3
-#define SPI_DIN1_MODE_S  2
-/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
-ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
- input with the spi_clk. Can be configured in CONF state..*/
-#define SPI_DIN0_MODE    0x00000003
-#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
-#define SPI_DIN0_MODE_V  0x3
-#define SPI_DIN0_MODE_S  0
-
-#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x28)
-/* SPI_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN7_NUM    0x00000003
-#define SPI_DIN7_NUM_M  ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S))
-#define SPI_DIN7_NUM_V  0x3
-#define SPI_DIN7_NUM_S  14
-/* SPI_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN6_NUM    0x00000003
-#define SPI_DIN6_NUM_M  ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S))
-#define SPI_DIN6_NUM_V  0x3
-#define SPI_DIN6_NUM_S  12
-/* SPI_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN5_NUM    0x00000003
-#define SPI_DIN5_NUM_M  ((SPI_DIN5_NUM_V)<<(SPI_DIN5_NUM_S))
-#define SPI_DIN5_NUM_V  0x3
-#define SPI_DIN5_NUM_S  10
-/* SPI_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN4_NUM    0x00000003
-#define SPI_DIN4_NUM_M  ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S))
-#define SPI_DIN4_NUM_V  0x3
-#define SPI_DIN4_NUM_S  8
-/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN3_NUM    0x00000003
-#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
-#define SPI_DIN3_NUM_V  0x3
-#define SPI_DIN3_NUM_S  6
-/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN2_NUM    0x00000003
-#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
-#define SPI_DIN2_NUM_V  0x3
-#define SPI_DIN2_NUM_S  4
-/* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN1_NUM    0x00000003
-#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
-#define SPI_DIN1_NUM_V  0x3
-#define SPI_DIN1_NUM_S  2
-/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
- 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
-#define SPI_DIN0_NUM    0x00000003
-#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
-#define SPI_DIN0_NUM_V  0x3
-#define SPI_DIN0_NUM_S  0
-
-#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x2C)
-/* SPI_D_DQS_MODE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
-delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-be configured in CONF state..*/
-#define SPI_D_DQS_MODE    (BIT(8))
-#define SPI_D_DQS_MODE_M  (BIT(8))
-#define SPI_D_DQS_MODE_V  0x1
-#define SPI_D_DQS_MODE_S  8
-/* SPI_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT7_MODE    (BIT(7))
-#define SPI_DOUT7_MODE_M  (BIT(7))
-#define SPI_DOUT7_MODE_V  0x1
-#define SPI_DOUT7_MODE_S  7
-/* SPI_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT6_MODE    (BIT(6))
-#define SPI_DOUT6_MODE_M  (BIT(6))
-#define SPI_DOUT6_MODE_V  0x1
-#define SPI_DOUT6_MODE_S  6
-/* SPI_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT5_MODE    (BIT(5))
-#define SPI_DOUT5_MODE_M  (BIT(5))
-#define SPI_DOUT5_MODE_V  0x1
-#define SPI_DOUT5_MODE_S  5
-/* SPI_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT4_MODE    (BIT(4))
-#define SPI_DOUT4_MODE_M  (BIT(4))
-#define SPI_DOUT4_MODE_V  0x1
-#define SPI_DOUT4_MODE_S  4
-/* SPI_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT3_MODE    (BIT(3))
-#define SPI_DOUT3_MODE_M  (BIT(3))
-#define SPI_DOUT3_MODE_V  0x1
-#define SPI_DOUT3_MODE_S  3
-/* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT2_MODE    (BIT(2))
-#define SPI_DOUT2_MODE_M  (BIT(2))
-#define SPI_DOUT2_MODE_V  0x1
-#define SPI_DOUT2_MODE_S  2
-/* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT1_MODE    (BIT(1))
-#define SPI_DOUT1_MODE_M  (BIT(1))
-#define SPI_DOUT1_MODE_V  0x1
-#define SPI_DOUT1_MODE_S  1
-/* SPI_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
-ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
-nfigured in CONF state..*/
-#define SPI_DOUT0_MODE    (BIT(0))
-#define SPI_DOUT0_MODE_M  (BIT(0))
-#define SPI_DOUT0_MODE_V  0x1
-#define SPI_DOUT0_MODE_S  0
-
-#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x30)
-/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
-/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
-DMA controlled mode transfer..*/
-#define SPI_DMA_AFIFO_RST    (BIT(31))
-#define SPI_DMA_AFIFO_RST_M  (BIT(31))
-#define SPI_DMA_AFIFO_RST_V  0x1
-#define SPI_DMA_AFIFO_RST_S  31
-/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
-/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
- controlled mode transfer and master mode transfer..*/
-#define SPI_BUF_AFIFO_RST    (BIT(30))
-#define SPI_BUF_AFIFO_RST_M  (BIT(30))
-#define SPI_BUF_AFIFO_RST_V  0x1
-#define SPI_BUF_AFIFO_RST_S  30
-/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */
-/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-slave mode transfer..*/
-#define SPI_RX_AFIFO_RST    (BIT(29))
-#define SPI_RX_AFIFO_RST_M  (BIT(29))
-#define SPI_RX_AFIFO_RST_V  0x1
-#define SPI_RX_AFIFO_RST_S  29
-/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: Set this bit to enable SPI DMA controlled send data mode..*/
-#define SPI_DMA_TX_ENA    (BIT(28))
-#define SPI_DMA_TX_ENA_M  (BIT(28))
-#define SPI_DMA_TX_ENA_V  0x1
-#define SPI_DMA_TX_ENA_S  28
-/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: Set this bit to enable SPI DMA controlled receive data mode..*/
-#define SPI_DMA_RX_ENA    (BIT(27))
-#define SPI_DMA_RX_ENA_M  (BIT(27))
-#define SPI_DMA_RX_ENA_V  0x1
-#define SPI_DMA_RX_ENA_S  27
-/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
-o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_d
-ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don
-e in seg-trans..*/
-#define SPI_RX_EOF_EN    (BIT(21))
-#define SPI_RX_EOF_EN_M  (BIT(21))
-#define SPI_RX_EOF_EN_V  0x1
-#define SPI_RX_EOF_EN_S  21
-/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
-mpty_vld is cleared by spi_trans_done..*/
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (BIT(20))
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x1
-#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
-/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full
-_vld is cleared by spi_trans_done..*/
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (BIT(19))
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x1
-#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
-/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/
-#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
-#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
-#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
-/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat
-a. 0: DMA RX FIFO is ready for receiving data..*/
-#define SPI_DMA_INFIFO_FULL    (BIT(1))
-#define SPI_DMA_INFIFO_FULL_M  (BIT(1))
-#define SPI_DMA_INFIFO_FULL_V  0x1
-#define SPI_DMA_INFIFO_FULL_S  1
-/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data.
- 0: DMA TX FIFO is ready for sending data..*/
-#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_M  (BIT(0))
-#define SPI_DMA_OUTFIFO_EMPTY_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_S  0
-
-#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
-/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_ENA    (BIT(20))
-#define SPI_APP1_INT_ENA_M  (BIT(20))
-#define SPI_APP1_INT_ENA_V  0x1
-#define SPI_APP1_INT_ENA_S  20
-/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_ENA    (BIT(19))
-#define SPI_APP2_INT_ENA_M  (BIT(19))
-#define SPI_APP2_INT_ENA_V  0x1
-#define SPI_APP2_INT_ENA_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
-/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ENA_V  0x1
-#define SPI_SLV_CMD_ERR_INT_ENA_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
-/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
-/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_ENA_V  0x1
-#define SPI_TRANS_DONE_INT_ENA_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
-/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_ENA_V  0x1
-#define SPI_SLV_CMDA_INT_ENA_S  7
-/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_ENA_V  0x1
-#define SPI_SLV_CMD9_INT_ENA_S  6
-/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_ENA_V  0x1
-#define SPI_SLV_CMD8_INT_ENA_S  5
-/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_ENA_V  0x1
-#define SPI_SLV_CMD7_INT_ENA_S  4
-/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ENA_V  0x1
-#define SPI_SLV_EN_QPI_INT_ENA_S  3
-/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The enable bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ENA_V  0x1
-#define SPI_SLV_EX_QPI_INT_ENA_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
-
-#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x38)
-/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_CLR    (BIT(20))
-#define SPI_APP1_INT_CLR_M  (BIT(20))
-#define SPI_APP1_INT_CLR_V  0x1
-#define SPI_APP1_INT_CLR_S  20
-/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_CLR    (BIT(19))
-#define SPI_APP2_INT_CLR_M  (BIT(19))
-#define SPI_APP2_INT_CLR_V  0x1
-#define SPI_APP2_INT_CLR_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
-/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_CLR_V  0x1
-#define SPI_SLV_CMD_ERR_INT_CLR_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
-/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
-/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_CLR_V  0x1
-#define SPI_TRANS_DONE_INT_CLR_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
-/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_CLR_V  0x1
-#define SPI_SLV_CMDA_INT_CLR_S  7
-/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_CLR_V  0x1
-#define SPI_SLV_CMD9_INT_CLR_S  6
-/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_CLR_V  0x1
-#define SPI_SLV_CMD8_INT_CLR_S  5
-/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_CLR_V  0x1
-#define SPI_SLV_CMD7_INT_CLR_S  4
-/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_CLR_V  0x1
-#define SPI_SLV_EN_QPI_INT_CLR_S  3
-/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The clear bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_CLR_V  0x1
-#define SPI_SLV_EX_QPI_INT_CLR_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
-
-#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x3C)
-/* SPI_APP1_INT_RAW : R/WTC/SS ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software
-..*/
-#define SPI_APP1_INT_RAW    (BIT(20))
-#define SPI_APP1_INT_RAW_M  (BIT(20))
-#define SPI_APP1_INT_RAW_V  0x1
-#define SPI_APP1_INT_RAW_S  20
-/* SPI_APP2_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software
-..*/
-#define SPI_APP2_INT_RAW    (BIT(19))
-#define SPI_APP2_INT_RAW_M  (BIT(19))
-#define SPI_APP2_INT_RAW_V  0x1
-#define SPI_APP2_INT_RAW_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
- write-full error when SPI inputs data in master mode. 0: Others..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
-/* SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
- current SPI slave HD mode transmission is not supported. 0: Others..*/
-#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_RAW_V  0x1
-#define SPI_SLV_CMD_ERR_INT_RAW_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres
-s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
- is bigger than 63. 0: Others..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
-/* SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff
-er is error in the DMA seg-conf-trans. 0: others..*/
-#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-du
-plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
-ta has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is
-not ended or not occurred. .*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
-/* SPI_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
- ended. 0: others..*/
-#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_RAW_V  0x1
-#define SPI_TRANS_DONE_INT_RAW_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran
-smission is ended. 0: Others..*/
-#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
-/* SPI_SLV_CMDA_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_RAW_V  0x1
-#define SPI_SLV_CMDA_INT_RAW_S  7
-/* SPI_SLV_CMD9_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_RAW_V  0x1
-#define SPI_SLV_CMD9_INT_RAW_S  6
-/* SPI_SLV_CMD8_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_RAW_V  0x1
-#define SPI_SLV_CMD8_INT_RAW_S  5
-/* SPI_SLV_CMD7_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
- ended. 0: Others..*/
-#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_RAW_V  0x1
-#define SPI_SLV_CMD7_INT_RAW_S  4
-/* SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio
-n is ended. 0: Others..*/
-#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_RAW_V  0x1
-#define SPI_SLV_EN_QPI_INT_RAW_S  3
-/* SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio
-n is ended. 0: Others..*/
-#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_RAW_V  0x1
-#define SPI_SLV_EX_QPI_INT_RAW_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
- master mode and send out all 0 in slave mode.  0: Others.  .*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
-the receive data.  0: Others.  .*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
-
-#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x40)
-/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The status bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_ST    (BIT(20))
-#define SPI_APP1_INT_ST_M  (BIT(20))
-#define SPI_APP1_INT_ST_V  0x1
-#define SPI_APP1_INT_ST_S  20
-/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The status bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_ST    (BIT(19))
-#define SPI_APP2_INT_ST_M  (BIT(19))
-#define SPI_APP2_INT_ST_V  0x1
-#define SPI_APP2_INT_ST_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
-/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_ST_V  0x1
-#define SPI_SLV_CMD_ERR_INT_ST_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
-/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
-/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_ST    (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_ST_V  0x1
-#define SPI_TRANS_DONE_INT_ST_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
-/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_ST    (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_ST_V  0x1
-#define SPI_SLV_CMDA_INT_ST_S  7
-/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_ST    (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_ST_V  0x1
-#define SPI_SLV_CMD9_INT_ST_S  6
-/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_ST    (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_ST_V  0x1
-#define SPI_SLV_CMD8_INT_ST_S  5
-/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_ST    (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_ST_V  0x1
-#define SPI_SLV_CMD7_INT_ST_S  4
-/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_ST_V  0x1
-#define SPI_SLV_EN_QPI_INT_ST_S  3
-/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The status bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_ST_V  0x1
-#define SPI_SLV_EX_QPI_INT_ST_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
-
-#define SPI_DMA_INT_SET_REG(i)          (REG_SPI_BASE(i) + 0x44)
-/* SPI_APP1_INT_SET : WT ;bitpos:[20] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_APP1_INT interrupt..*/
-#define SPI_APP1_INT_SET    (BIT(20))
-#define SPI_APP1_INT_SET_M  (BIT(20))
-#define SPI_APP1_INT_SET_V  0x1
-#define SPI_APP1_INT_SET_S  20
-/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_APP2_INT interrupt..*/
-#define SPI_APP2_INT_SET    (BIT(19))
-#define SPI_APP2_INT_SET_M  (BIT(19))
-#define SPI_APP2_INT_SET_V  0x1
-#define SPI_APP2_INT_SET_S  19
-/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT ;bitpos:[18] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (BIT(18))
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x1
-#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
-/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT ;bitpos:[17] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (BIT(17))
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x1
-#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
-/* SPI_SLV_CMD_ERR_INT_SET : WT ;bitpos:[16] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt..*/
-#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_M  (BIT(16))
-#define SPI_SLV_CMD_ERR_INT_SET_V  0x1
-#define SPI_SLV_CMD_ERR_INT_SET_S  16
-/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (BIT(15))
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x1
-#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
-/* SPI_SEG_MAGIC_ERR_INT_SET : WT ;bitpos:[14] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
-#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_M  (BIT(14))
-#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x1
-#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
-/* SPI_DMA_SEG_TRANS_DONE_INT_SET : WT ;bitpos:[13] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (BIT(13))
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x1
-#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
-/* SPI_TRANS_DONE_INT_SET : WT ;bitpos:[12] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_TRANS_DONE_INT interrupt..*/
-#define SPI_TRANS_DONE_INT_SET    (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_M  (BIT(12))
-#define SPI_TRANS_DONE_INT_SET_V  0x1
-#define SPI_TRANS_DONE_INT_SET_S  12
-/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (BIT(11))
-#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x1
-#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
-/* SPI_SLV_RD_BUF_DONE_INT_SET : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
-#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (BIT(10))
-#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x1
-#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
-/* SPI_SLV_WR_DMA_DONE_INT_SET : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (BIT(9))
-#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x1
-#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
-/* SPI_SLV_RD_DMA_DONE_INT_SET : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
-#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (BIT(8))
-#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x1
-#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
-/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave CMDA interrupt..*/
-#define SPI_SLV_CMDA_INT_SET    (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_M  (BIT(7))
-#define SPI_SLV_CMDA_INT_SET_V  0x1
-#define SPI_SLV_CMDA_INT_SET_S  7
-/* SPI_SLV_CMD9_INT_SET : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave CMD9 interrupt..*/
-#define SPI_SLV_CMD9_INT_SET    (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_M  (BIT(6))
-#define SPI_SLV_CMD9_INT_SET_V  0x1
-#define SPI_SLV_CMD9_INT_SET_S  6
-/* SPI_SLV_CMD8_INT_SET : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave CMD8 interrupt..*/
-#define SPI_SLV_CMD8_INT_SET    (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_M  (BIT(5))
-#define SPI_SLV_CMD8_INT_SET_V  0x1
-#define SPI_SLV_CMD8_INT_SET_S  5
-/* SPI_SLV_CMD7_INT_SET : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave CMD7 interrupt..*/
-#define SPI_SLV_CMD7_INT_SET    (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_M  (BIT(4))
-#define SPI_SLV_CMD7_INT_SET_V  0x1
-#define SPI_SLV_CMD7_INT_SET_S  4
-/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave En_QPI interrupt..*/
-#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_M  (BIT(3))
-#define SPI_SLV_EN_QPI_INT_SET_V  0x1
-#define SPI_SLV_EN_QPI_INT_SET_S  3
-/* SPI_SLV_EX_QPI_INT_SET : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The software set bit for SPI slave Ex_QPI interrupt..*/
-#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_M  (BIT(2))
-#define SPI_SLV_EX_QPI_INT_SET_V  0x1
-#define SPI_SLV_EX_QPI_INT_SET_S  2
-/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (BIT(1))
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x1
-#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
-/* SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (BIT(0))
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x1
-#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
-
-#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x98)
-/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF0    0xFFFFFFFF
-#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
-#define SPI_BUF0_V  0xFFFFFFFF
-#define SPI_BUF0_S  0
-
-#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x9C)
-/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF1    0xFFFFFFFF
-#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
-#define SPI_BUF1_V  0xFFFFFFFF
-#define SPI_BUF1_S  0
-
-#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0xA0)
-/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF2    0xFFFFFFFF
-#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
-#define SPI_BUF2_V  0xFFFFFFFF
-#define SPI_BUF2_S  0
-
-#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0xA4)
-/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF3    0xFFFFFFFF
-#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
-#define SPI_BUF3_V  0xFFFFFFFF
-#define SPI_BUF3_S  0
-
-#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0xA8)
-/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF4    0xFFFFFFFF
-#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
-#define SPI_BUF4_V  0xFFFFFFFF
-#define SPI_BUF4_S  0
-
-#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0xAC)
-/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF5    0xFFFFFFFF
-#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
-#define SPI_BUF5_V  0xFFFFFFFF
-#define SPI_BUF5_S  0
-
-#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0xB0)
-/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF6    0xFFFFFFFF
-#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
-#define SPI_BUF6_V  0xFFFFFFFF
-#define SPI_BUF6_S  0
-
-#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0xB4)
-/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF7    0xFFFFFFFF
-#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
-#define SPI_BUF7_V  0xFFFFFFFF
-#define SPI_BUF7_S  0
-
-#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xB8)
-/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF8    0xFFFFFFFF
-#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
-#define SPI_BUF8_V  0xFFFFFFFF
-#define SPI_BUF8_S  0
-
-#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xBC)
-/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF9    0xFFFFFFFF
-#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
-#define SPI_BUF9_V  0xFFFFFFFF
-#define SPI_BUF9_S  0
-
-#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xC0)
-/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF10    0xFFFFFFFF
-#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
-#define SPI_BUF10_V  0xFFFFFFFF
-#define SPI_BUF10_S  0
-
-#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xC4)
-/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF11    0xFFFFFFFF
-#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
-#define SPI_BUF11_V  0xFFFFFFFF
-#define SPI_BUF11_S  0
-
-#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xC8)
-/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF12    0xFFFFFFFF
-#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
-#define SPI_BUF12_V  0xFFFFFFFF
-#define SPI_BUF12_S  0
-
-#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xCC)
-/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF13    0xFFFFFFFF
-#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
-#define SPI_BUF13_V  0xFFFFFFFF
-#define SPI_BUF13_S  0
-
-#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xD0)
-/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF14    0xFFFFFFFF
-#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
-#define SPI_BUF14_V  0xFFFFFFFF
-#define SPI_BUF14_S  0
-
-#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xD4)
-/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
-/*description: data buffer.*/
-#define SPI_BUF15    0xFFFFFFFF
-#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
-#define SPI_BUF15_V  0xFFFFFFFF
-#define SPI_BUF15_S  0
-
-#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0xE0)
-/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
-ns will start. 0: This is not seg-trans mode..*/
-#define SPI_USR_CONF    (BIT(28))
-#define SPI_USR_CONF_M  (BIT(28))
-#define SPI_USR_CONF_V  0x1
-#define SPI_USR_CONF_S  28
-/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
-/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
-onfigured in CONF state..*/
-#define SPI_SOFT_RESET    (BIT(27))
-#define SPI_SOFT_RESET_M  (BIT(27))
-#define SPI_SOFT_RESET_V  0x1
-#define SPI_SOFT_RESET_S  27
-/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
-#define SPI_SLAVE_MODE    (BIT(26))
-#define SPI_SLAVE_MODE_M  (BIT(26))
-#define SPI_SLAVE_MODE_V  0x1
-#define SPI_SLAVE_MODE_S  26
-/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
-/*description: The magic value of BM table in master DMA seg-trans..*/
-#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000F
-#define SPI_DMA_SEG_MAGIC_VALUE_M  ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
-#define SPI_DMA_SEG_MAGIC_VALUE_V  0xF
-#define SPI_DMA_SEG_MAGIC_VALUE_S  22
-/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
-th in CPU controlled mode(Wr_BUF). 0: others.*/
-#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_M  (BIT(11))
-#define SPI_SLV_WRBUF_BITLEN_EN_V  0x1
-#define SPI_SLV_WRBUF_BITLEN_EN_S  11
-/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
-n CPU controlled mode(Rd_BUF). 0: others.*/
-#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_M  (BIT(10))
-#define SPI_SLV_RDBUF_BITLEN_EN_V  0x1
-#define SPI_SLV_RDBUF_BITLEN_EN_S  10
-/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
-th in DMA controlled mode(Wr_DMA). 0: others.*/
-#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_M  (BIT(9))
-#define SPI_SLV_WRDMA_BITLEN_EN_V  0x1
-#define SPI_SLV_WRDMA_BITLEN_EN_S  9
-/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
-n DMA controlled mode(Rd_DMA). 0: others.*/
-#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_M  (BIT(8))
-#define SPI_SLV_RDDMA_BITLEN_EN_V  0x1
-#define SPI_SLV_RDDMA_BITLEN_EN_S  8
-/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
-dge   0: output data at tsck posedge .*/
-#define SPI_RSCK_DATA_OUT    (BIT(3))
-#define SPI_RSCK_DATA_OUT_M  (BIT(3))
-#define SPI_RSCK_DATA_OUT_V  0x1
-#define SPI_RSCK_DATA_OUT_S  3
-/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
- 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
-#define SPI_CLK_MODE_13    (BIT(2))
-#define SPI_CLK_MODE_13_M  (BIT(2))
-#define SPI_CLK_MODE_13_V  0x1
-#define SPI_CLK_MODE_13_S  2
-/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
-d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
-ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/
-#define SPI_CLK_MODE    0x00000003
-#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
-#define SPI_CLK_MODE_V  0x3
-#define SPI_CLK_MODE_S  0
-
-#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0xE4)
-/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
-/*description: In the slave mode it is the value of address..*/
-#define SPI_SLV_LAST_ADDR    0x0000003F
-#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
-#define SPI_SLV_LAST_ADDR_V  0x3F
-#define SPI_SLV_LAST_ADDR_S  26
-/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
-/*description: In the slave mode it is the value of command..*/
-#define SPI_SLV_LAST_COMMAND    0x000000FF
-#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
-#define SPI_SLV_LAST_COMMAND_V  0xFF
-#define SPI_SLV_LAST_COMMAND_S  18
-/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
-/*description: The transferred data bit length in SPI slave FD and HD mode. .*/
-#define SPI_SLV_DATA_BITLEN    0x0003FFFF
-#define SPI_SLV_DATA_BITLEN_M  ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
-#define SPI_SLV_DATA_BITLEN_V  0x3FFFF
-#define SPI_SLV_DATA_BITLEN_S  0
-
-#define SPI_CLK_GATE_REG(i)          (REG_SPI_BASE(i) + 0xE8)
-/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
-M. 0: XTAL CLK..*/
-#define SPI_MST_CLK_SEL    (BIT(2))
-#define SPI_MST_CLK_SEL_M  (BIT(2))
-#define SPI_MST_CLK_SEL_V  0x1
-#define SPI_MST_CLK_SEL_S  2
-/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to power on the SPI module clock..*/
-#define SPI_MST_CLK_ACTIVE    (BIT(1))
-#define SPI_MST_CLK_ACTIVE_M  (BIT(1))
-#define SPI_MST_CLK_ACTIVE_V  0x1
-#define SPI_MST_CLK_ACTIVE_S  1
-/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to enable clk gate.*/
-#define SPI_CLK_EN    (BIT(0))
-#define SPI_CLK_EN_M  (BIT(0))
-#define SPI_CLK_EN_V  0x1
-#define SPI_CLK_EN_S  0
-
-#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
-/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101190 ; */
-/*description: SPI register version..*/
-#define SPI_DATE    0x0FFFFFFF
-#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
-#define SPI_DATE_V  0xFFFFFFF
-#define SPI_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/spi_struct.h b/components/soc/esp32s3/include/soc/spi_struct.h
deleted file mode 100644
index 2a3abd257c1..00000000000
--- a/components/soc/esp32s3/include/soc/spi_struct.h
+++ /dev/null
@@ -1,428 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SPI_STRUCT_H_
-#define _SOC_SPI_STRUCT_H_
-
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct spi_dev_s {
-    union {
-        struct {
-            uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
-            uint32_t reserved18                    :    5;  /*reserved*/
-            uint32_t update                        :    1;  /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
-            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
-            uint32_t reserved25                    :    7;  /*reserved*/
-        };
-        uint32_t val;
-    } cmd;
-    uint32_t addr;
-    union {
-        struct {
-            uint32_t reserved0                     :    3;  /*reserved*/
-            uint32_t dummy_out                     :    1;  /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
-            uint32_t reserved4                     :    1;  /*reserved*/
-            uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved11                    :    3;  /*reserved*/
-            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
-            uint32_t fread_oct                     :    1;  /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
-            uint32_t reserved17                    :    1;  /*reserved*/
-            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
-            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
-            uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
-            uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
-            uint32_t reserved22                    :    1;  /*reserved*/
-            uint32_t rd_bit_order                  :    2;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
-            uint32_t wr_bit_order                  :    2;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
-            uint32_t reserved27                    :    5;  /*reserved*/
-        };
-        uint32_t val;
-    } ctrl;
-    union {
-        struct {
-            uint32_t clkcnt_l                      :    6;  /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
-            uint32_t clkcnt_h                      :    6;  /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
-            uint32_t clkcnt_n                      :    6;  /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
-            uint32_t clkdiv_pre                    :    4;  /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
-            uint32_t reserved22                    :    9;  /*reserved*/
-            uint32_t clk_equ_sysclk                :    1;  /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } clock;
-    union {
-        struct {
-            uint32_t doutdin                       :    1;  /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved1                     :    2;  /*reserved*/
-            uint32_t qpi_mode                      :    1;  /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
-            uint32_t opi_mode                      :    1;  /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
-            uint32_t tsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
-            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t rsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
-            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
-            uint32_t reserved10                    :    2;  /*reserved*/
-            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
-            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
-            uint32_t fwrite_oct                    :    1;  /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
-            uint32_t usr_conf_nxt                  :    1;  /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
-            uint32_t reserved16                    :    1;  /*reserved*/
-            uint32_t sio                           :    1;  /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t reserved18                    :    6;  /*reserved*/
-            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
-            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.*/
-            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
-            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
-            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user;
-    union {
-        struct {
-            uint32_t usr_dummy_cyclelen            :    8;  /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
-            uint32_t reserved8                     :    8;  /*reserved*/
-            uint32_t mst_wfull_err_end_en          :    1;  /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
-            uint32_t cs_setup_time                 :    5;  /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
-            uint32_t cs_hold_time                  :    5;  /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
-            uint32_t usr_addr_bitlen               :    5;  /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user1;
-    union {
-        struct {
-            uint32_t usr_command_value             :    16;  /*The value of  command. Can be configured in CONF state.*/
-            uint32_t reserved16                    :    11;  /*reserved*/
-            uint32_t mst_rempty_err_end_en         :    1;  /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
-            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } user2;
-    union {
-        struct {
-            uint32_t ms_data_bitlen                :    18;  /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
-            uint32_t reserved18                    :    14;  /*reserved*/
-        };
-        uint32_t val;
-    } ms_dlen;
-    union {
-        struct {
-            uint32_t cs0_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs1_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs2_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs3_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs4_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t cs5_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
-            uint32_t ck_dis                        :    1;  /*1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.*/
-            uint32_t master_cs_pol                 :    6;  /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
-            uint32_t reserved13                    :    3;  /*reserved*/
-            uint32_t clk_data_dtr_en               :    1;  /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19. */
-            uint32_t data_dtr_en                   :    1;  /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
-            uint32_t addr_dtr_en                   :    1;  /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
-            uint32_t cmd_dtr_en                    :    1;  /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
-            uint32_t reserved20                    :    3;  /*reserved*/
-            uint32_t slave_cs_pol                  :    1;  /*spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.*/
-            uint32_t dqs_idle_edge                 :    1;  /*The default value of spi_dqs. Can be configured in CONF state.*/
-            uint32_t reserved25                    :    4;  /*reserved*/
-            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
-            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
-            uint32_t quad_din_pin_swap             :    1;  /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.*/
-        };
-        uint32_t val;
-    } misc;
-    union {
-        struct {
-            uint32_t din0_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din1_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din2_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din3_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din4_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din5_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din6_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t din7_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
-            uint32_t timing_hclk_active            :    1;  /*1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.*/
-            uint32_t reserved17                    :    15;  /*reserved*/
-        };
-        uint32_t val;
-    } din_mode;
-    union {
-        struct {
-            uint32_t din0_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din1_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din2_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din3_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din4_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din5_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din6_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t din7_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } din_num;
-    union {
-        struct {
-            uint32_t dout0_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout1_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout2_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout3_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout4_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout5_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout6_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t dout7_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t d_dqs_mode                    :    1;  /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
-            uint32_t reserved9                     :    23;  /*reserved*/
-        };
-        uint32_t val;
-    } dout_mode;
-    union {
-        struct {
-            uint32_t outfifo_empty                 :    1;  /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
-            uint32_t infifo_full                   :    1;  /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
-            uint32_t reserved2                     :    16;  /*reserved*/
-            uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
-            uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
-            uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
-            uint32_t rx_eof_en                     :    1;  /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
-            uint32_t reserved22                    :    5;  /*reserved*/
-            uint32_t dma_rx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled receive data mode.*/
-            uint32_t dma_tx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled send data mode.*/
-            uint32_t rx_afifo_rst                  :    1;  /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
-            uint32_t buf_afifo_rst                 :    1;  /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
-            uint32_t dma_afifo_rst                 :    1;  /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
-        };
-        uint32_t val;
-    } dma_conf;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The enable bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The enable bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The enable bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The enable bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The enable bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The enable bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The enable bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The enable bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_ena;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The clear bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The clear bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The clear bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The clear bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The clear bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The clear bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The clear bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The clear bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_clr;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.  */
-            uint32_t outfifo_empty_err             :    1;  /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.  */
-            uint32_t ex_qpi                        :    1;  /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
-            uint32_t en_qpi                        :    1;  /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
-            uint32_t cmd7                          :    1;  /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
-            uint32_t cmd8                          :    1;  /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
-            uint32_t cmd9                          :    1;  /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
-            uint32_t cmda                          :    1;  /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
-            uint32_t rd_dma_done                   :    1;  /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
-            uint32_t wr_dma_done                   :    1;  /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
-            uint32_t rd_buf_done                   :    1;  /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
-            uint32_t wr_buf_done                   :    1;  /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
-            uint32_t trans_done                    :    1;  /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred. */
-            uint32_t seg_magic_err                 :    1;  /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
-            uint32_t buf_addr_err                  :    1;  /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
-            uint32_t cmd_err                       :    1;  /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
-            uint32_t app2                          :    1;  /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
-            uint32_t app1                          :    1;  /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_raw;
-    union {
-        struct {
-            uint32_t infifo_full_err               :    1;  /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err             :    1;  /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi                        :    1;  /*The status bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi                        :    1;  /*The status bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7                          :    1;  /*The status bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8                          :    1;  /*The status bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9                          :    1;  /*The status bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda                          :    1;  /*The status bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done                   :    1;  /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done                   :    1;  /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done                   :    1;  /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done                   :    1;  /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done                    :    1;  /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done            :    1;  /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err                 :    1;  /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err                  :    1;  /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err                       :    1;  /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2                          :    1;  /*The status bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1                          :    1;  /*The status bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_st;
-    union {
-        struct {
-            uint32_t infifo_full_err_int_set       :    1;  /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
-            uint32_t outfifo_empty_err_int_set     :    1;  /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
-            uint32_t ex_qpi_int_set                :    1;  /*The software set bit for SPI slave Ex_QPI interrupt.*/
-            uint32_t en_qpi_int_set                :    1;  /*The software set bit for SPI slave En_QPI interrupt.*/
-            uint32_t cmd7_int_set                  :    1;  /*The software set bit for SPI slave CMD7 interrupt.*/
-            uint32_t cmd8_int_set                  :    1;  /*The software set bit for SPI slave CMD8 interrupt.*/
-            uint32_t cmd9_int_set                  :    1;  /*The software set bit for SPI slave CMD9 interrupt.*/
-            uint32_t cmda_int_set                  :    1;  /*The software set bit for SPI slave CMDA interrupt.*/
-            uint32_t rd_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
-            uint32_t wr_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
-            uint32_t rd_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
-            uint32_t wr_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
-            uint32_t trans_done_int_set            :    1;  /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
-            uint32_t dma_seg_trans_done_int_set    :    1;  /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
-            uint32_t seg_magic_err_int_set         :    1;  /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
-            uint32_t buf_addr_err_int_set          :    1;  /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
-            uint32_t cmd_err_int_set               :    1;  /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
-            uint32_t mst_rx_afifo_wfull_err_int_set:    1;  /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
-            uint32_t mst_tx_afifo_rempty_err_int_set:    1;  /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
-            uint32_t app2_int_set                  :    1;  /*The software set bit for SPI_APP2_INT interrupt.*/
-            uint32_t app1_int_set                  :    1;  /*The software set bit for SPI_APP1_INT interrupt.*/
-            uint32_t reserved21                    :    11;  /*reserved*/
-        };
-        uint32_t val;
-    } dma_int_set;
-    uint32_t reserved_48;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t reserved_80;
-    uint32_t reserved_84;
-    uint32_t reserved_88;
-    uint32_t reserved_8c;
-    uint32_t reserved_90;
-    uint32_t reserved_94;
-    uint32_t data_buf[16];                                               /*SPI CPU-controlled buffer0*/
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    union {
-        struct {
-            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
-            uint32_t clk_mode_13                   :    1;  /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
-            uint32_t rsck_data_out                 :    1;  /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge */
-            uint32_t reserved4                     :    4;  /*reserved*/
-            uint32_t rddma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
-            uint32_t wrdma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
-            uint32_t rdbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
-            uint32_t wrbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
-            uint32_t reserved12                    :    10;  /*reserved*/
-            uint32_t dma_seg_magic_value           :    4;  /*The magic value of BM table in master DMA seg-trans.*/
-            uint32_t slave_mode                    :    1;  /*Set SPI work mode. 1: slave mode 0: master mode.*/
-            uint32_t soft_reset                    :    1;  /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
-            uint32_t usr_conf                      :    1;  /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
-            uint32_t reserved29                    :    3;  /*reserved*/
-        };
-        uint32_t val;
-    } slave;
-    union {
-        struct {
-            uint32_t data_bitlen                   :    18;  /*The transferred data bit length in SPI slave FD and HD mode. */
-            uint32_t last_command                  :    8;  /*In the slave mode it is the value of command.*/
-            uint32_t last_addr                     :    6;  /*In the slave mode it is the value of address.*/
-        };
-        uint32_t val;
-    } slave1;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
-            uint32_t mst_clk_active                :    1;  /*Set this bit to power on the SPI module clock.*/
-            uint32_t mst_clk_sel                   :    1;  /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } clk_gate;
-    uint32_t reserved_ec;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*SPI register version.*/
-            uint32_t reserved28                    :    4;  /*reserved*/
-        };
-        uint32_t val;
-    } date;
-} spi_dev_t;
-extern spi_dev_t GPSPI2;
-extern spi_dev_t GPSPI3;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SPI_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/syscon_reg.h b/components/soc/esp32s3/include/soc/syscon_reg.h
deleted file mode 100644
index e22f18c92ee..00000000000
--- a/components/soc/esp32s3/include/soc/syscon_reg.h
+++ /dev/null
@@ -1,720 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _SOC_SYSCON_REG_H_
-#define _SOC_SYSCON_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x0)
-/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_RST_TICK_CNT    (BIT(12))
-#define SYSCON_RST_TICK_CNT_M  (BIT(12))
-#define SYSCON_RST_TICK_CNT_V  0x1
-#define SYSCON_RST_TICK_CNT_S  12
-/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_CLK_EN    (BIT(11))
-#define SYSCON_CLK_EN_M  (BIT(11))
-#define SYSCON_CLK_EN_V  0x1
-#define SYSCON_CLK_EN_S  11
-/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_CLK_320M_EN    (BIT(10))
-#define SYSCON_CLK_320M_EN_M  (BIT(10))
-#define SYSCON_CLK_320M_EN_V  0x1
-#define SYSCON_CLK_320M_EN_S  10
-/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
-/*description: .*/
-#define SYSCON_PRE_DIV_CNT    0x000003FF
-#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
-#define SYSCON_PRE_DIV_CNT_V  0x3FF
-#define SYSCON_PRE_DIV_CNT_S  0
-
-#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x4)
-/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
-/*description: .*/
-#define SYSCON_TICK_ENABLE    (BIT(16))
-#define SYSCON_TICK_ENABLE_M  (BIT(16))
-#define SYSCON_TICK_ENABLE_V  0x1
-#define SYSCON_TICK_ENABLE_S  16
-/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
-/*description: .*/
-#define SYSCON_CK8M_TICK_NUM    0x000000FF
-#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
-#define SYSCON_CK8M_TICK_NUM_V  0xFF
-#define SYSCON_CK8M_TICK_NUM_S  8
-/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
-/*description: .*/
-#define SYSCON_XTAL_TICK_NUM    0x000000FF
-#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
-#define SYSCON_XTAL_TICK_NUM_V  0xFF
-#define SYSCON_XTAL_TICK_NUM_S  0
-
-#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x8)
-/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK_XTAL_OEN    (BIT(10))
-#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
-#define SYSCON_CLK_XTAL_OEN_V  0x1
-#define SYSCON_CLK_XTAL_OEN_S  10
-/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK40X_BB_OEN    (BIT(9))
-#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
-#define SYSCON_CLK40X_BB_OEN_V  0x1
-#define SYSCON_CLK40X_BB_OEN_S  9
-/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK_DAC_CPU_OEN    (BIT(8))
-#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
-#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
-#define SYSCON_CLK_DAC_CPU_OEN_S  8
-/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK_ADC_INF_OEN    (BIT(7))
-#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
-#define SYSCON_CLK_ADC_INF_OEN_V  0x1
-#define SYSCON_CLK_ADC_INF_OEN_S  7
-/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK_320M_OEN    (BIT(6))
-#define SYSCON_CLK_320M_OEN_M  (BIT(6))
-#define SYSCON_CLK_320M_OEN_V  0x1
-#define SYSCON_CLK_320M_OEN_S  6
-/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK160_OEN    (BIT(5))
-#define SYSCON_CLK160_OEN_M  (BIT(5))
-#define SYSCON_CLK160_OEN_V  0x1
-#define SYSCON_CLK160_OEN_S  5
-/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK80_OEN    (BIT(4))
-#define SYSCON_CLK80_OEN_M  (BIT(4))
-#define SYSCON_CLK80_OEN_V  0x1
-#define SYSCON_CLK80_OEN_S  4
-/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK_BB_OEN    (BIT(3))
-#define SYSCON_CLK_BB_OEN_M  (BIT(3))
-#define SYSCON_CLK_BB_OEN_V  0x1
-#define SYSCON_CLK_BB_OEN_S  3
-/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK44_OEN    (BIT(2))
-#define SYSCON_CLK44_OEN_M  (BIT(2))
-#define SYSCON_CLK44_OEN_V  0x1
-#define SYSCON_CLK44_OEN_S  2
-/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK22_OEN    (BIT(1))
-#define SYSCON_CLK22_OEN_M  (BIT(1))
-#define SYSCON_CLK22_OEN_V  0x1
-#define SYSCON_CLK22_OEN_S  1
-/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_CLK20_OEN    (BIT(0))
-#define SYSCON_CLK20_OEN_M  (BIT(0))
-#define SYSCON_CLK20_OEN_V  0x1
-#define SYSCON_CLK20_OEN_S  0
-
-#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0xC)
-/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SYSCON_WIFI_BB_CFG    0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
-#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_S  0
-
-#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x10)
-/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SYSCON_WIFI_BB_CFG_2    0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
-#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
-#define SYSCON_WIFI_BB_CFG_2_S  0
-
-#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x14)
-/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: .*/
-#define SYSCON_WIFI_CLK_EN    0xFFFFFFFF
-#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
-#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
-#define SYSCON_WIFI_CLK_EN_S  0
-
-#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x18)
-/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SYSCON_WIFI_RST    0xFFFFFFFF
-#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
-#define SYSCON_WIFI_RST_V  0xFFFFFFFF
-#define SYSCON_WIFI_RST_S  0
-
-#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
-/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
-/*description: */
-#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
-#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S))
-#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
-#define SYSTEM_WIFI_CLK_EN_S 0
-
-/* Mask for all Wifi clock bits, 6 */
-#define SYSTEM_WIFI_CLK_WIFI_EN  0x0
-#define SYSTEM_WIFI_CLK_WIFI_EN_M  ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
-#define SYSTEM_WIFI_CLK_WIFI_EN_V  0x0
-#define SYSTEM_WIFI_CLK_WIFI_EN_S  0
-/* Mask for all Bluetooth clock bits, 11, 16, 17 */
-#define SYSTEM_WIFI_CLK_BT_EN  0x0
-#define SYSTEM_WIFI_CLK_BT_EN_M  ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
-#define SYSTEM_WIFI_CLK_BT_EN_V  0x0
-#define SYSTEM_WIFI_CLK_BT_EN_S  0
-/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
-#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
-
-//bluetooth baseband bit11
-#define SYSTEM_BT_BASEBAND_EN BIT(11)
-//bluetooth LC bit16 and bit17
-#define SYSTEM_BT_LC_EN (BIT(16) | BIT(17))
-
-/* Remaining single bit clock masks */
-#define SYSTEM_WIFI_CLK_I2C_CLK_EN BIT(5)
-#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12)
-#define SYSTEM_WIFI_CLK_SDIO_HOST_EN BIT(13)
-#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14)
-#define SYSTEM_WIFI_CLK_RNG_EN BIT(15)
-
-#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
-#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
-/* SYSTEM_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: */
-#define SYSTEM_WIFI_RST 0xFFFFFFFF
-#define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S))
-#define SYSTEM_WIFI_RST_V 0xFFFFFFFF
-#define SYSTEM_WIFI_RST_S 0
-
-#define SYSTEM_WIFIBB_RST           BIT(0)
-#define SYSTEM_FE_RST               BIT(1)
-#define SYSTEM_WIFIMAC_RST          BIT(2)
-#define SYSTEM_BTBB_RST             BIT(3)    /* Bluetooth Baseband */
-#define SYSTEM_BTMAC_RST            BIT(4)    /* deprecated */
-#define SYSTEM_SDIO_RST             BIT(5)
-#define SYSTEM_EMAC_RST             BIT(7)
-#define SYSTEM_MACPWR_RST           BIT(8)
-#define SYSTEM_RW_BTMAC_RST         BIT(9)    /* Bluetooth MAC */
-#define SYSTEM_RW_BTLP_RST          BIT(10)   /* Bluetooth Low Power Module */
-#define SYSTEM_RW_BTMAC_REG_RST     BIT(11)   /* Bluetooth MAC Regsiters */
-#define SYSTEM_RW_BTLP_REG_RST      BIT(12)   /* Bluetooth Low Power Registers */
-#define SYSTEM_BTBB_REG_RST         BIT(13)   /* Bluetooth Baseband Registers */
-
-#define MODEM_RESET_FIELD_WHEN_PU   (SYSTEM_WIFIBB_RST       | \
-                                     SYSTEM_FE_RST           | \
-                                     SYSTEM_WIFIMAC_RST      | \
-                                     SYSTEM_BTBB_RST         | \
-                                     SYSTEM_BTMAC_RST        | \
-                                     SYSTEM_RW_BTMAC_RST     | \
-                                     SYSTEM_RW_BTMAC_REG_RST | \
-                                     SYSTEM_BTBB_REG_RST)
-
-#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x1C)
-/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: .*/
-#define SYSCON_PERI_IO_SWAP    0x000000FF
-#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
-#define SYSCON_PERI_IO_SWAP_V  0xFF
-#define SYSCON_PERI_IO_SWAP_S  0
-
-#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x20)
-/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_EXT_MEM_PMS_LOCK    (BIT(0))
-#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
-#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
-#define SYSCON_EXT_MEM_PMS_LOCK_S  0
-
-#define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG          (DR_REG_SYSCON_BASE + 0x24)
-/* SYSCON_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set 1 to bypass cache writeback request to external memory so that spi will not
-check its attribute..*/
-#define SYSCON_WRITEBACK_BYPASS    (BIT(0))
-#define SYSCON_WRITEBACK_BYPASS_M  (BIT(0))
-#define SYSCON_WRITEBACK_BYPASS_V  0x1
-#define SYSCON_WRITEBACK_BYPASS_S  0
-
-#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x28)
-/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE0_ATTR    0x000001FF
-#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
-#define SYSCON_FLASH_ACE0_ATTR_V  0x1FF
-#define SYSCON_FLASH_ACE0_ATTR_S  0
-
-#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x2C)
-/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE1_ATTR    0x000001FF
-#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
-#define SYSCON_FLASH_ACE1_ATTR_V  0x1FF
-#define SYSCON_FLASH_ACE1_ATTR_S  0
-
-#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x30)
-/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE2_ATTR    0x000001FF
-#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
-#define SYSCON_FLASH_ACE2_ATTR_V  0x1FF
-#define SYSCON_FLASH_ACE2_ATTR_S  0
-
-#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x34)
-/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE3_ATTR    0x000001FF
-#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
-#define SYSCON_FLASH_ACE3_ATTR_V  0x1FF
-#define SYSCON_FLASH_ACE3_ATTR_S  0
-
-#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x38)
-/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE0_ADDR_S    0xFFFFFFFF
-#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
-#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE0_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x3C)
-/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE1_ADDR_S    0xFFFFFFFF
-#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
-#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE1_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x40)
-/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE2_ADDR_S    0xFFFFFFFF
-#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
-#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE2_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x44)
-/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE3_ADDR_S    0xFFFFFFFF
-#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
-#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_FLASH_ACE3_ADDR_S_S  0
-
-#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x48)
-/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE0_SIZE    0x0000FFFF
-#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
-#define SYSCON_FLASH_ACE0_SIZE_V  0xFFFF
-#define SYSCON_FLASH_ACE0_SIZE_S  0
-
-#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x4C)
-/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE1_SIZE    0x0000FFFF
-#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
-#define SYSCON_FLASH_ACE1_SIZE_V  0xFFFF
-#define SYSCON_FLASH_ACE1_SIZE_S  0
-
-#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x50)
-/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE2_SIZE    0x0000FFFF
-#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
-#define SYSCON_FLASH_ACE2_SIZE_V  0xFFFF
-#define SYSCON_FLASH_ACE2_SIZE_S  0
-
-#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x54)
-/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define SYSCON_FLASH_ACE3_SIZE    0x0000FFFF
-#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
-#define SYSCON_FLASH_ACE3_SIZE_V  0xFFFF
-#define SYSCON_FLASH_ACE3_SIZE_S  0
-
-#define SYSCON_SRAM_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x58)
-/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE0_ATTR    0x000001FF
-#define SYSCON_SRAM_ACE0_ATTR_M  ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S))
-#define SYSCON_SRAM_ACE0_ATTR_V  0x1FF
-#define SYSCON_SRAM_ACE0_ATTR_S  0
-
-#define SYSCON_SRAM_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x5C)
-/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE1_ATTR    0x000001FF
-#define SYSCON_SRAM_ACE1_ATTR_M  ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S))
-#define SYSCON_SRAM_ACE1_ATTR_V  0x1FF
-#define SYSCON_SRAM_ACE1_ATTR_S  0
-
-#define SYSCON_SRAM_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x60)
-/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE2_ATTR    0x000001FF
-#define SYSCON_SRAM_ACE2_ATTR_M  ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S))
-#define SYSCON_SRAM_ACE2_ATTR_V  0x1FF
-#define SYSCON_SRAM_ACE2_ATTR_S  0
-
-#define SYSCON_SRAM_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x64)
-/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE3_ATTR    0x000001FF
-#define SYSCON_SRAM_ACE3_ATTR_M  ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S))
-#define SYSCON_SRAM_ACE3_ATTR_V  0x1FF
-#define SYSCON_SRAM_ACE3_ATTR_S  0
-
-#define SYSCON_SRAM_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x68)
-/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE0_ADDR_S    0xFFFFFFFF
-#define SYSCON_SRAM_ACE0_ADDR_S_M  ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S))
-#define SYSCON_SRAM_ACE0_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_SRAM_ACE0_ADDR_S_S  0
-
-#define SYSCON_SRAM_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x6C)
-/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE1_ADDR_S    0xFFFFFFFF
-#define SYSCON_SRAM_ACE1_ADDR_S_M  ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S))
-#define SYSCON_SRAM_ACE1_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_SRAM_ACE1_ADDR_S_S  0
-
-#define SYSCON_SRAM_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x70)
-/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE2_ADDR_S    0xFFFFFFFF
-#define SYSCON_SRAM_ACE2_ADDR_S_M  ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S))
-#define SYSCON_SRAM_ACE2_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_SRAM_ACE2_ADDR_S_S  0
-
-#define SYSCON_SRAM_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x74)
-/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE3_ADDR_S    0xFFFFFFFF
-#define SYSCON_SRAM_ACE3_ADDR_S_M  ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S))
-#define SYSCON_SRAM_ACE3_ADDR_S_V  0xFFFFFFFF
-#define SYSCON_SRAM_ACE3_ADDR_S_S  0
-
-#define SYSCON_SRAM_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x78)
-/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE0_SIZE    0x0000FFFF
-#define SYSCON_SRAM_ACE0_SIZE_M  ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S))
-#define SYSCON_SRAM_ACE0_SIZE_V  0xFFFF
-#define SYSCON_SRAM_ACE0_SIZE_S  0
-
-#define SYSCON_SRAM_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x7C)
-/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE1_SIZE    0x0000FFFF
-#define SYSCON_SRAM_ACE1_SIZE_M  ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S))
-#define SYSCON_SRAM_ACE1_SIZE_V  0xFFFF
-#define SYSCON_SRAM_ACE1_SIZE_S  0
-
-#define SYSCON_SRAM_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x80)
-/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE2_SIZE    0x0000FFFF
-#define SYSCON_SRAM_ACE2_SIZE_M  ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S))
-#define SYSCON_SRAM_ACE2_SIZE_V  0xFFFF
-#define SYSCON_SRAM_ACE2_SIZE_S  0
-
-#define SYSCON_SRAM_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x84)
-/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
-/*description: .*/
-#define SYSCON_SRAM_ACE3_SIZE    0x0000FFFF
-#define SYSCON_SRAM_ACE3_SIZE_M  ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S))
-#define SYSCON_SRAM_ACE3_SIZE_V  0xFFFF
-#define SYSCON_SRAM_ACE3_SIZE_S  0
-
-#define SYSCON_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x88)
-/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
-/*description: .*/
-#define SYSCON_SPI_MEM_REJECT_CDE    0x0000001F
-#define SYSCON_SPI_MEM_REJECT_CDE_M  ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
-#define SYSCON_SPI_MEM_REJECT_CDE_V  0x1F
-#define SYSCON_SPI_MEM_REJECT_CDE_S  2
-/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_SPI_MEM_REJECT_CLR    (BIT(1))
-#define SYSCON_SPI_MEM_REJECT_CLR_M  (BIT(1))
-#define SYSCON_SPI_MEM_REJECT_CLR_V  0x1
-#define SYSCON_SPI_MEM_REJECT_CLR_S  1
-/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_SPI_MEM_REJECT_INT    (BIT(0))
-#define SYSCON_SPI_MEM_REJECT_INT_M  (BIT(0))
-#define SYSCON_SPI_MEM_REJECT_INT_V  0x1
-#define SYSCON_SPI_MEM_REJECT_INT_S  0
-
-#define SYSCON_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x8C)
-/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define SYSCON_SPI_MEM_REJECT_ADDR    0xFFFFFFFF
-#define SYSCON_SPI_MEM_REJECT_ADDR_M  ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
-#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
-#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
-
-#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x90)
-/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: .*/
-#define SYSCON_SDIO_WIN_ACCESS_EN    (BIT(0))
-#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
-#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
-#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
-
-#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x94)
-/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define SYSCON_REDCY_ANDOR    (BIT(31))
-#define SYSCON_REDCY_ANDOR_M  (BIT(31))
-#define SYSCON_REDCY_ANDOR_V  0x1
-#define SYSCON_REDCY_ANDOR_S  31
-/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: .*/
-#define SYSCON_REDCY_SIG0    0x7FFFFFFF
-#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
-#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
-#define SYSCON_REDCY_SIG0_S  0
-
-#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x98)
-/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define SYSCON_REDCY_NANDOR    (BIT(31))
-#define SYSCON_REDCY_NANDOR_M  (BIT(31))
-#define SYSCON_REDCY_NANDOR_V  0x1
-#define SYSCON_REDCY_NANDOR_S  31
-/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
-/*description: .*/
-#define SYSCON_REDCY_SIG1    0x7FFFFFFF
-#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
-#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
-#define SYSCON_REDCY_SIG1_S  0
-
-#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x9C)
-/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_FREQ_MEM_FORCE_PD    (BIT(7))
-#define SYSCON_FREQ_MEM_FORCE_PD_M  (BIT(7))
-#define SYSCON_FREQ_MEM_FORCE_PD_V  0x1
-#define SYSCON_FREQ_MEM_FORCE_PD_S  7
-/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_FREQ_MEM_FORCE_PU    (BIT(6))
-#define SYSCON_FREQ_MEM_FORCE_PU_M  (BIT(6))
-#define SYSCON_FREQ_MEM_FORCE_PU_V  0x1
-#define SYSCON_FREQ_MEM_FORCE_PU_S  6
-/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_DC_MEM_FORCE_PD    (BIT(5))
-#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
-#define SYSCON_DC_MEM_FORCE_PD_V  0x1
-#define SYSCON_DC_MEM_FORCE_PD_S  5
-/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_DC_MEM_FORCE_PU    (BIT(4))
-#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
-#define SYSCON_DC_MEM_FORCE_PU_V  0x1
-#define SYSCON_DC_MEM_FORCE_PU_S  4
-/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_PBUS_MEM_FORCE_PD    (BIT(3))
-#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
-#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
-#define SYSCON_PBUS_MEM_FORCE_PD_S  3
-/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_PBUS_MEM_FORCE_PU    (BIT(2))
-#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
-#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
-#define SYSCON_PBUS_MEM_FORCE_PU_S  2
-/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_AGC_MEM_FORCE_PD    (BIT(1))
-#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
-#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
-#define SYSCON_AGC_MEM_FORCE_PD_S  1
-/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSCON_AGC_MEM_FORCE_PU    (BIT(0))
-#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
-#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
-#define SYSCON_AGC_MEM_FORCE_PU_S  0
-
-#define SYSCON_SPI_MEM_ECC_CTRL_REG          (DR_REG_SYSCON_BASE + 0xA0)
-/* SYSCON_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
-/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2:
-1024 bytes. 3: 2048 bytes..*/
-#define SYSCON_SRAM_PAGE_SIZE    0x00000003
-#define SYSCON_SRAM_PAGE_SIZE_M  ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S))
-#define SYSCON_SRAM_PAGE_SIZE_V  0x3
-#define SYSCON_SRAM_PAGE_SIZE_S  20
-/* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
-/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by
-tes. 3: 2048 bytes..*/
-#define SYSCON_FLASH_PAGE_SIZE    0x00000003
-#define SYSCON_FLASH_PAGE_SIZE_M  ((SYSCON_FLASH_PAGE_SIZE_V)<<(SYSCON_FLASH_PAGE_SIZE_S))
-#define SYSCON_FLASH_PAGE_SIZE_V  0x3
-#define SYSCON_FLASH_PAGE_SIZE_S  18
-
-#define SYSCON_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0xA8)
-/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
-/*description: .*/
-#define SYSCON_SRAM_CLKGATE_FORCE_ON    0x000007FF
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0x7FF
-#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  3
-/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SYSCON_ROM_CLKGATE_FORCE_ON    0x00000007
-#define SYSCON_ROM_CLKGATE_FORCE_ON_M  ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
-#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x7
-#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
-
-#define SYSCON_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0xAC)
-/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
-/*description: .*/
-#define SYSCON_SRAM_POWER_DOWN    0x000007FF
-#define SYSCON_SRAM_POWER_DOWN_M  ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
-#define SYSCON_SRAM_POWER_DOWN_V  0x7FF
-#define SYSCON_SRAM_POWER_DOWN_S  3
-/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: .*/
-#define SYSCON_ROM_POWER_DOWN    0x00000007
-#define SYSCON_ROM_POWER_DOWN_M  ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
-#define SYSCON_ROM_POWER_DOWN_V  0x7
-#define SYSCON_ROM_POWER_DOWN_S  0
-
-#define SYSCON_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0xB0)
-/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
-/*description: .*/
-#define SYSCON_SRAM_POWER_UP    0x000007FF
-#define SYSCON_SRAM_POWER_UP_M  ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
-#define SYSCON_SRAM_POWER_UP_V  0x7FF
-#define SYSCON_SRAM_POWER_UP_S  3
-/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
-/*description: .*/
-#define SYSCON_ROM_POWER_UP    0x00000007
-#define SYSCON_ROM_POWER_UP_M  ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
-#define SYSCON_ROM_POWER_UP_V  0x7
-#define SYSCON_ROM_POWER_UP_S  0
-
-#define SYSCON_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0xB4)
-/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_NOBYPASS_CPU_ISO_RST    (BIT(27))
-#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
-#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x1
-#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
-/* SYSCON_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
-/*description: .*/
-#define SYSCON_RETENTION_CPU_LINK_ADDR    0x07FFFFFF
-#define SYSCON_RETENTION_CPU_LINK_ADDR_M  ((SYSCON_RETENTION_CPU_LINK_ADDR_V)<<(SYSCON_RETENTION_CPU_LINK_ADDR_S))
-#define SYSCON_RETENTION_CPU_LINK_ADDR_V  0x7FFFFFF
-#define SYSCON_RETENTION_CPU_LINK_ADDR_S  0
-
-#define SYSCON_RETENTION_CTRL1_REG          (DR_REG_SYSCON_BASE + 0xB8)
-/* SYSCON_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
-/*description: .*/
-#define SYSCON_RETENTION_TAG_LINK_ADDR    0x07FFFFFF
-#define SYSCON_RETENTION_TAG_LINK_ADDR_M  ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S))
-#define SYSCON_RETENTION_TAG_LINK_ADDR_V  0x7FFFFFF
-#define SYSCON_RETENTION_TAG_LINK_ADDR_S  0
-
-#define SYSCON_RETENTION_CTRL2_REG          (DR_REG_SYSCON_BASE + 0xBC)
-/* SYSCON_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_RET_ICACHE_ENABLE    (BIT(31))
-#define SYSCON_RET_ICACHE_ENABLE_M  (BIT(31))
-#define SYSCON_RET_ICACHE_ENABLE_V  0x1
-#define SYSCON_RET_ICACHE_ENABLE_S  31
-/* SYSCON_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
-/*description: .*/
-#define SYSCON_RET_ICACHE_START_POINT    0x000000FF
-#define SYSCON_RET_ICACHE_START_POINT_M  ((SYSCON_RET_ICACHE_START_POINT_V)<<(SYSCON_RET_ICACHE_START_POINT_S))
-#define SYSCON_RET_ICACHE_START_POINT_V  0xFF
-#define SYSCON_RET_ICACHE_START_POINT_S  22
-/* SYSCON_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
-/*description: .*/
-#define SYSCON_RET_ICACHE_VLD_SIZE    0x000000FF
-#define SYSCON_RET_ICACHE_VLD_SIZE_M  ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S))
-#define SYSCON_RET_ICACHE_VLD_SIZE_V  0xFF
-#define SYSCON_RET_ICACHE_VLD_SIZE_S  13
-/* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
-/*description: .*/
-#define SYSCON_RET_ICACHE_SIZE    0x000000FF
-#define SYSCON_RET_ICACHE_SIZE_M  ((SYSCON_RET_ICACHE_SIZE_V)<<(SYSCON_RET_ICACHE_SIZE_S))
-#define SYSCON_RET_ICACHE_SIZE_V  0xFF
-#define SYSCON_RET_ICACHE_SIZE_S  4
-
-#define SYSCON_RETENTION_CTRL3_REG          (DR_REG_SYSCON_BASE + 0xC0)
-/* SYSCON_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_RET_DCACHE_ENABLE    (BIT(31))
-#define SYSCON_RET_DCACHE_ENABLE_M  (BIT(31))
-#define SYSCON_RET_DCACHE_ENABLE_V  0x1
-#define SYSCON_RET_DCACHE_ENABLE_S  31
-/* SYSCON_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
-/*description: .*/
-#define SYSCON_RET_DCACHE_START_POINT    0x000001FF
-#define SYSCON_RET_DCACHE_START_POINT_M  ((SYSCON_RET_DCACHE_START_POINT_V)<<(SYSCON_RET_DCACHE_START_POINT_S))
-#define SYSCON_RET_DCACHE_START_POINT_V  0x1FF
-#define SYSCON_RET_DCACHE_START_POINT_S  22
-/* SYSCON_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
-/*description: .*/
-#define SYSCON_RET_DCACHE_VLD_SIZE    0x000001FF
-#define SYSCON_RET_DCACHE_VLD_SIZE_M  ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S))
-#define SYSCON_RET_DCACHE_VLD_SIZE_V  0x1FF
-#define SYSCON_RET_DCACHE_VLD_SIZE_S  13
-/* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
-/*description: .*/
-#define SYSCON_RET_DCACHE_SIZE    0x000001FF
-#define SYSCON_RET_DCACHE_SIZE_M  ((SYSCON_RET_DCACHE_SIZE_V)<<(SYSCON_RET_DCACHE_SIZE_S))
-#define SYSCON_RET_DCACHE_SIZE_V  0x1FF
-#define SYSCON_RET_DCACHE_SIZE_S  4
-
-#define SYSCON_RETENTION_CTRL4_REG          (DR_REG_SYSCON_BASE + 0xC4)
-/* SYSCON_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */
-/*description: .*/
-#define SYSCON_RETENTION_INV_CFG    0xFFFFFFFF
-#define SYSCON_RETENTION_INV_CFG_M  ((SYSCON_RETENTION_INV_CFG_V)<<(SYSCON_RETENTION_INV_CFG_S))
-#define SYSCON_RETENTION_INV_CFG_V  0xFFFFFFFF
-#define SYSCON_RETENTION_INV_CFG_S  0
-
-#define SYSCON_RETENTION_CTRL5_REG          (DR_REG_SYSCON_BASE + 0xC8)
-/* SYSCON_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSCON_RETENTION_DISABLE    (BIT(0))
-#define SYSCON_RETENTION_DISABLE_M  (BIT(0))
-#define SYSCON_RETENTION_DISABLE_V  0x1
-#define SYSCON_RETENTION_DISABLE_S  0
-
-#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
-/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
-/*description: Version control.*/
-#define SYSCON_DATE    0xFFFFFFFF
-#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
-#define SYSCON_DATE_V  0xFFFFFFFF
-#define SYSCON_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SYSCON_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/system_reg.h b/components/soc/esp32s3/include/soc/system_reg.h
deleted file mode 100644
index 49a02b007eb..00000000000
--- a/components/soc/esp32s3/include/soc/system_reg.h
+++ /dev/null
@@ -1,1092 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SYSTEM_REG_H_
-#define _SOC_SYSTEM_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define SYSTEM_CORE_1_CONTROL_0_REG          (DR_REG_SYSTEM_BASE + 0x0)
-/* SYSTEM_CONTROL_CORE_1_RESETING : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_CONTROL_CORE_1_RESETING    (BIT(2))
-#define SYSTEM_CONTROL_CORE_1_RESETING_M  (BIT(2))
-#define SYSTEM_CONTROL_CORE_1_RESETING_V  0x1
-#define SYSTEM_CONTROL_CORE_1_RESETING_S  2
-/* SYSTEM_CONTROL_CORE_1_CLKGATE_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN    (BIT(1))
-#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M  (BIT(1))
-#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V  0x1
-#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S  1
-/* SYSTEM_CONTROL_CORE_1_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CONTROL_CORE_1_RUNSTALL    (BIT(0))
-#define SYSTEM_CONTROL_CORE_1_RUNSTALL_M  (BIT(0))
-#define SYSTEM_CONTROL_CORE_1_RUNSTALL_V  0x1
-#define SYSTEM_CONTROL_CORE_1_RUNSTALL_S  0
-
-#define SYSTEM_CORE_1_CONTROL_1_REG          (DR_REG_SYSTEM_BASE + 0x4)
-/* SYSTEM_CONTROL_CORE_1_MESSAGE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SYSTEM_CONTROL_CORE_1_MESSAGE    0xFFFFFFFF
-#define SYSTEM_CONTROL_CORE_1_MESSAGE_M  ((SYSTEM_CONTROL_CORE_1_MESSAGE_V)<<(SYSTEM_CONTROL_CORE_1_MESSAGE_S))
-#define SYSTEM_CONTROL_CORE_1_MESSAGE_V  0xFFFFFFFF
-#define SYSTEM_CONTROL_CORE_1_MESSAGE_S  0
-
-#define SYSTEM_CPU_PERI_CLK_EN_REG          (DR_REG_SYSTEM_BASE + 0x8)
-/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CLK_EN_DEDICATED_GPIO    (BIT(7))
-#define SYSTEM_CLK_EN_DEDICATED_GPIO_M  (BIT(7))
-#define SYSTEM_CLK_EN_DEDICATED_GPIO_V  0x1
-#define SYSTEM_CLK_EN_DEDICATED_GPIO_S  7
-/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CLK_EN_ASSIST_DEBUG    (BIT(6))
-#define SYSTEM_CLK_EN_ASSIST_DEBUG_M  (BIT(6))
-#define SYSTEM_CLK_EN_ASSIST_DEBUG_V  0x1
-#define SYSTEM_CLK_EN_ASSIST_DEBUG_S  6
-
-#define SYSTEM_CPU_PERI_RST_EN_REG          (DR_REG_SYSTEM_BASE + 0xC)
-/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_RST_EN_DEDICATED_GPIO    (BIT(7))
-#define SYSTEM_RST_EN_DEDICATED_GPIO_M  (BIT(7))
-#define SYSTEM_RST_EN_DEDICATED_GPIO_V  0x1
-#define SYSTEM_RST_EN_DEDICATED_GPIO_S  7
-/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_RST_EN_ASSIST_DEBUG    (BIT(6))
-#define SYSTEM_RST_EN_ASSIST_DEBUG_M  (BIT(6))
-#define SYSTEM_RST_EN_ASSIST_DEBUG_V  0x1
-#define SYSTEM_RST_EN_ASSIST_DEBUG_S  6
-
-#define SYSTEM_CPU_PER_CONF_REG          (DR_REG_SYSTEM_BASE + 0x10)
-/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
-/*description: .*/
-#define SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000F
-#define SYSTEM_CPU_WAITI_DELAY_NUM_M  ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S))
-#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0xF
-#define SYSTEM_CPU_WAITI_DELAY_NUM_S  4
-/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
-#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (BIT(3))
-#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x1
-#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  3
-/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_PLL_FREQ_SEL    (BIT(2))
-#define SYSTEM_PLL_FREQ_SEL_M  (BIT(2))
-#define SYSTEM_PLL_FREQ_SEL_V  0x1
-#define SYSTEM_PLL_FREQ_SEL_S  2
-/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: .*/
-#define SYSTEM_CPUPERIOD_SEL    0x00000003
-#define SYSTEM_CPUPERIOD_SEL_M  ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S))
-#define SYSTEM_CPUPERIOD_SEL_V  0x3
-#define SYSTEM_CPUPERIOD_SEL_S  0
-
-#define SYSTEM_MEM_PD_MASK_REG          (DR_REG_SYSTEM_BASE + 0x14)
-/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_LSLP_MEM_PD_MASK    (BIT(0))
-#define SYSTEM_LSLP_MEM_PD_MASK_M  (BIT(0))
-#define SYSTEM_LSLP_MEM_PD_MASK_V  0x1
-#define SYSTEM_LSLP_MEM_PD_MASK_S  0
-
-#define SYSTEM_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x18)
-/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
-/*description: .*/
-#define SYSTEM_SPI4_CLK_EN    (BIT(31))
-#define SYSTEM_SPI4_CLK_EN_M  (BIT(31))
-#define SYSTEM_SPI4_CLK_EN_V  0x1
-#define SYSTEM_SPI4_CLK_EN_S  31
-/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_ADC2_ARB_CLK_EN    (BIT(30))
-#define SYSTEM_ADC2_ARB_CLK_EN_M  (BIT(30))
-#define SYSTEM_ADC2_ARB_CLK_EN_V  0x1
-#define SYSTEM_ADC2_ARB_CLK_EN_S  30
-/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_SYSTIMER_CLK_EN    (BIT(29))
-#define SYSTEM_SYSTIMER_CLK_EN_M  (BIT(29))
-#define SYSTEM_SYSTIMER_CLK_EN_V  0x1
-#define SYSTEM_SYSTIMER_CLK_EN_S  29
-/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_APB_SARADC_CLK_EN    (BIT(28))
-#define SYSTEM_APB_SARADC_CLK_EN_M  (BIT(28))
-#define SYSTEM_APB_SARADC_CLK_EN_V  0x1
-#define SYSTEM_APB_SARADC_CLK_EN_S  28
-/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_SPI3_DMA_CLK_EN    (BIT(27))
-#define SYSTEM_SPI3_DMA_CLK_EN_M  (BIT(27))
-#define SYSTEM_SPI3_DMA_CLK_EN_V  0x1
-#define SYSTEM_SPI3_DMA_CLK_EN_S  27
-/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PWM3_CLK_EN    (BIT(26))
-#define SYSTEM_PWM3_CLK_EN_M  (BIT(26))
-#define SYSTEM_PWM3_CLK_EN_V  0x1
-#define SYSTEM_PWM3_CLK_EN_S  26
-/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PWM2_CLK_EN    (BIT(25))
-#define SYSTEM_PWM2_CLK_EN_M  (BIT(25))
-#define SYSTEM_PWM2_CLK_EN_V  0x1
-#define SYSTEM_PWM2_CLK_EN_S  25
-/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_UART_MEM_CLK_EN    (BIT(24))
-#define SYSTEM_UART_MEM_CLK_EN_M  (BIT(24))
-#define SYSTEM_UART_MEM_CLK_EN_V  0x1
-#define SYSTEM_UART_MEM_CLK_EN_S  24
-/* SYSTEM_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_USB_CLK_EN    (BIT(23))
-#define SYSTEM_USB_CLK_EN_M  (BIT(23))
-#define SYSTEM_USB_CLK_EN_V  0x1
-#define SYSTEM_USB_CLK_EN_S  23
-/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_SPI2_DMA_CLK_EN    (BIT(22))
-#define SYSTEM_SPI2_DMA_CLK_EN_M  (BIT(22))
-#define SYSTEM_SPI2_DMA_CLK_EN_V  0x1
-#define SYSTEM_SPI2_DMA_CLK_EN_S  22
-/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_I2S1_CLK_EN    (BIT(21))
-#define SYSTEM_I2S1_CLK_EN_M  (BIT(21))
-#define SYSTEM_I2S1_CLK_EN_V  0x1
-#define SYSTEM_I2S1_CLK_EN_S  21
-/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PWM1_CLK_EN    (BIT(20))
-#define SYSTEM_PWM1_CLK_EN_M  (BIT(20))
-#define SYSTEM_PWM1_CLK_EN_V  0x1
-#define SYSTEM_PWM1_CLK_EN_S  20
-/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_TWAI_CLK_EN    (BIT(19))
-#define SYSTEM_TWAI_CLK_EN_M  (BIT(19))
-#define SYSTEM_TWAI_CLK_EN_V  0x1
-#define SYSTEM_TWAI_CLK_EN_S  19
-/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_I2C_EXT1_CLK_EN    (BIT(18))
-#define SYSTEM_I2C_EXT1_CLK_EN_M  (BIT(18))
-#define SYSTEM_I2C_EXT1_CLK_EN_V  0x1
-#define SYSTEM_I2C_EXT1_CLK_EN_S  18
-/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PWM0_CLK_EN    (BIT(17))
-#define SYSTEM_PWM0_CLK_EN_M  (BIT(17))
-#define SYSTEM_PWM0_CLK_EN_V  0x1
-#define SYSTEM_PWM0_CLK_EN_S  17
-/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_SPI3_CLK_EN    (BIT(16))
-#define SYSTEM_SPI3_CLK_EN_M  (BIT(16))
-#define SYSTEM_SPI3_CLK_EN_V  0x1
-#define SYSTEM_SPI3_CLK_EN_S  16
-/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_TIMERGROUP1_CLK_EN    (BIT(15))
-#define SYSTEM_TIMERGROUP1_CLK_EN_M  (BIT(15))
-#define SYSTEM_TIMERGROUP1_CLK_EN_V  0x1
-#define SYSTEM_TIMERGROUP1_CLK_EN_S  15
-/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_EFUSE_CLK_EN    (BIT(14))
-#define SYSTEM_EFUSE_CLK_EN_M  (BIT(14))
-#define SYSTEM_EFUSE_CLK_EN_V  0x1
-#define SYSTEM_EFUSE_CLK_EN_S  14
-/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_TIMERGROUP_CLK_EN    (BIT(13))
-#define SYSTEM_TIMERGROUP_CLK_EN_M  (BIT(13))
-#define SYSTEM_TIMERGROUP_CLK_EN_V  0x1
-#define SYSTEM_TIMERGROUP_CLK_EN_S  13
-/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_UHCI1_CLK_EN    (BIT(12))
-#define SYSTEM_UHCI1_CLK_EN_M  (BIT(12))
-#define SYSTEM_UHCI1_CLK_EN_V  0x1
-#define SYSTEM_UHCI1_CLK_EN_S  12
-/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_LEDC_CLK_EN    (BIT(11))
-#define SYSTEM_LEDC_CLK_EN_M  (BIT(11))
-#define SYSTEM_LEDC_CLK_EN_V  0x1
-#define SYSTEM_LEDC_CLK_EN_S  11
-/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PCNT_CLK_EN    (BIT(10))
-#define SYSTEM_PCNT_CLK_EN_M  (BIT(10))
-#define SYSTEM_PCNT_CLK_EN_V  0x1
-#define SYSTEM_PCNT_CLK_EN_S  10
-/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_RMT_CLK_EN    (BIT(9))
-#define SYSTEM_RMT_CLK_EN_M  (BIT(9))
-#define SYSTEM_RMT_CLK_EN_V  0x1
-#define SYSTEM_RMT_CLK_EN_S  9
-/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_UHCI0_CLK_EN    (BIT(8))
-#define SYSTEM_UHCI0_CLK_EN_M  (BIT(8))
-#define SYSTEM_UHCI0_CLK_EN_V  0x1
-#define SYSTEM_UHCI0_CLK_EN_S  8
-/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_I2C_EXT0_CLK_EN    (BIT(7))
-#define SYSTEM_I2C_EXT0_CLK_EN_M  (BIT(7))
-#define SYSTEM_I2C_EXT0_CLK_EN_V  0x1
-#define SYSTEM_I2C_EXT0_CLK_EN_S  7
-/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_SPI2_CLK_EN    (BIT(6))
-#define SYSTEM_SPI2_CLK_EN_M  (BIT(6))
-#define SYSTEM_SPI2_CLK_EN_V  0x1
-#define SYSTEM_SPI2_CLK_EN_S  6
-/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_UART1_CLK_EN    (BIT(5))
-#define SYSTEM_UART1_CLK_EN_M  (BIT(5))
-#define SYSTEM_UART1_CLK_EN_V  0x1
-#define SYSTEM_UART1_CLK_EN_S  5
-/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_I2S0_CLK_EN    (BIT(4))
-#define SYSTEM_I2S0_CLK_EN_M  (BIT(4))
-#define SYSTEM_I2S0_CLK_EN_V  0x1
-#define SYSTEM_I2S0_CLK_EN_S  4
-/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_WDG_CLK_EN    (BIT(3))
-#define SYSTEM_WDG_CLK_EN_M  (BIT(3))
-#define SYSTEM_WDG_CLK_EN_V  0x1
-#define SYSTEM_WDG_CLK_EN_S  3
-/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_UART_CLK_EN    (BIT(2))
-#define SYSTEM_UART_CLK_EN_M  (BIT(2))
-#define SYSTEM_UART_CLK_EN_V  0x1
-#define SYSTEM_UART_CLK_EN_S  2
-/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_SPI01_CLK_EN    (BIT(1))
-#define SYSTEM_SPI01_CLK_EN_M  (BIT(1))
-#define SYSTEM_SPI01_CLK_EN_V  0x1
-#define SYSTEM_SPI01_CLK_EN_S  1
-/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_TIMERS_CLK_EN    (BIT(0))
-#define SYSTEM_TIMERS_CLK_EN_M  (BIT(0))
-#define SYSTEM_TIMERS_CLK_EN_V  0x1
-#define SYSTEM_TIMERS_CLK_EN_S  0
-
-#define SYSTEM_PERIP_CLK_EN1_REG          (DR_REG_SYSTEM_BASE + 0x1C)
-/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_USB_DEVICE_CLK_EN    (BIT(10))
-#define SYSTEM_USB_DEVICE_CLK_EN_M  (BIT(10))
-#define SYSTEM_USB_DEVICE_CLK_EN_V  0x1
-#define SYSTEM_USB_DEVICE_CLK_EN_S  10
-/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_UART2_CLK_EN    (BIT(9))
-#define SYSTEM_UART2_CLK_EN_M  (BIT(9))
-#define SYSTEM_UART2_CLK_EN_V  0x1
-#define SYSTEM_UART2_CLK_EN_S  9
-/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_LCD_CAM_CLK_EN    (BIT(8))
-#define SYSTEM_LCD_CAM_CLK_EN_M  (BIT(8))
-#define SYSTEM_LCD_CAM_CLK_EN_V  0x1
-#define SYSTEM_LCD_CAM_CLK_EN_S  8
-/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_SDIO_HOST_CLK_EN    (BIT(7))
-#define SYSTEM_SDIO_HOST_CLK_EN_M  (BIT(7))
-#define SYSTEM_SDIO_HOST_CLK_EN_V  0x1
-#define SYSTEM_SDIO_HOST_CLK_EN_S  7
-/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_DMA_CLK_EN    (BIT(6))
-#define SYSTEM_DMA_CLK_EN_M  (BIT(6))
-#define SYSTEM_DMA_CLK_EN_V  0x1
-#define SYSTEM_DMA_CLK_EN_S  6
-/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_HMAC_CLK_EN    (BIT(5))
-#define SYSTEM_CRYPTO_HMAC_CLK_EN_M  (BIT(5))
-#define SYSTEM_CRYPTO_HMAC_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_HMAC_CLK_EN_S  5
-/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_DS_CLK_EN    (BIT(4))
-#define SYSTEM_CRYPTO_DS_CLK_EN_M  (BIT(4))
-#define SYSTEM_CRYPTO_DS_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_DS_CLK_EN_S  4
-/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_RSA_CLK_EN    (BIT(3))
-#define SYSTEM_CRYPTO_RSA_CLK_EN_M  (BIT(3))
-#define SYSTEM_CRYPTO_RSA_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_RSA_CLK_EN_S  3
-/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_SHA_CLK_EN    (BIT(2))
-#define SYSTEM_CRYPTO_SHA_CLK_EN_M  (BIT(2))
-#define SYSTEM_CRYPTO_SHA_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_SHA_CLK_EN_S  2
-/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_AES_CLK_EN    (BIT(1))
-#define SYSTEM_CRYPTO_AES_CLK_EN_M  (BIT(1))
-#define SYSTEM_CRYPTO_AES_CLK_EN_V  0x1
-#define SYSTEM_CRYPTO_AES_CLK_EN_S  1
-/* SYSTEM_PERI_BACKUP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PERI_BACKUP_CLK_EN    (BIT(0))
-#define SYSTEM_PERI_BACKUP_CLK_EN_M  (BIT(0))
-#define SYSTEM_PERI_BACKUP_CLK_EN_V  0x1
-#define SYSTEM_PERI_BACKUP_CLK_EN_S  0
-
-#define SYSTEM_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x20)
-/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: .*/
-#define SYSTEM_SPI4_RST    (BIT(31))
-#define SYSTEM_SPI4_RST_M  (BIT(31))
-#define SYSTEM_SPI4_RST_V  0x1
-#define SYSTEM_SPI4_RST_S  31
-/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_ADC2_ARB_RST    (BIT(30))
-#define SYSTEM_ADC2_ARB_RST_M  (BIT(30))
-#define SYSTEM_ADC2_ARB_RST_V  0x1
-#define SYSTEM_ADC2_ARB_RST_S  30
-/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_SYSTIMER_RST    (BIT(29))
-#define SYSTEM_SYSTIMER_RST_M  (BIT(29))
-#define SYSTEM_SYSTIMER_RST_V  0x1
-#define SYSTEM_SYSTIMER_RST_S  29
-/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_APB_SARADC_RST    (BIT(28))
-#define SYSTEM_APB_SARADC_RST_M  (BIT(28))
-#define SYSTEM_APB_SARADC_RST_V  0x1
-#define SYSTEM_APB_SARADC_RST_S  28
-/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_SPI3_DMA_RST    (BIT(27))
-#define SYSTEM_SPI3_DMA_RST_M  (BIT(27))
-#define SYSTEM_SPI3_DMA_RST_V  0x1
-#define SYSTEM_SPI3_DMA_RST_S  27
-/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PWM3_RST    (BIT(26))
-#define SYSTEM_PWM3_RST_M  (BIT(26))
-#define SYSTEM_PWM3_RST_V  0x1
-#define SYSTEM_PWM3_RST_S  26
-/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PWM2_RST    (BIT(25))
-#define SYSTEM_PWM2_RST_M  (BIT(25))
-#define SYSTEM_PWM2_RST_V  0x1
-#define SYSTEM_PWM2_RST_S  25
-/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_UART_MEM_RST    (BIT(24))
-#define SYSTEM_UART_MEM_RST_M  (BIT(24))
-#define SYSTEM_UART_MEM_RST_V  0x1
-#define SYSTEM_UART_MEM_RST_S  24
-/* SYSTEM_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_USB_RST    (BIT(23))
-#define SYSTEM_USB_RST_M  (BIT(23))
-#define SYSTEM_USB_RST_V  0x1
-#define SYSTEM_USB_RST_S  23
-/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_SPI2_DMA_RST    (BIT(22))
-#define SYSTEM_SPI2_DMA_RST_M  (BIT(22))
-#define SYSTEM_SPI2_DMA_RST_V  0x1
-#define SYSTEM_SPI2_DMA_RST_S  22
-/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_I2S1_RST    (BIT(21))
-#define SYSTEM_I2S1_RST_M  (BIT(21))
-#define SYSTEM_I2S1_RST_V  0x1
-#define SYSTEM_I2S1_RST_S  21
-/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PWM1_RST    (BIT(20))
-#define SYSTEM_PWM1_RST_M  (BIT(20))
-#define SYSTEM_PWM1_RST_V  0x1
-#define SYSTEM_PWM1_RST_S  20
-/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_TWAI_RST    (BIT(19))
-#define SYSTEM_TWAI_RST_M  (BIT(19))
-#define SYSTEM_TWAI_RST_V  0x1
-#define SYSTEM_TWAI_RST_S  19
-/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_I2C_EXT1_RST    (BIT(18))
-#define SYSTEM_I2C_EXT1_RST_M  (BIT(18))
-#define SYSTEM_I2C_EXT1_RST_V  0x1
-#define SYSTEM_I2C_EXT1_RST_S  18
-/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PWM0_RST    (BIT(17))
-#define SYSTEM_PWM0_RST_M  (BIT(17))
-#define SYSTEM_PWM0_RST_V  0x1
-#define SYSTEM_PWM0_RST_S  17
-/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_SPI3_RST    (BIT(16))
-#define SYSTEM_SPI3_RST_M  (BIT(16))
-#define SYSTEM_SPI3_RST_V  0x1
-#define SYSTEM_SPI3_RST_S  16
-/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_TIMERGROUP1_RST    (BIT(15))
-#define SYSTEM_TIMERGROUP1_RST_M  (BIT(15))
-#define SYSTEM_TIMERGROUP1_RST_V  0x1
-#define SYSTEM_TIMERGROUP1_RST_S  15
-/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_EFUSE_RST    (BIT(14))
-#define SYSTEM_EFUSE_RST_M  (BIT(14))
-#define SYSTEM_EFUSE_RST_V  0x1
-#define SYSTEM_EFUSE_RST_S  14
-/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_TIMERGROUP_RST    (BIT(13))
-#define SYSTEM_TIMERGROUP_RST_M  (BIT(13))
-#define SYSTEM_TIMERGROUP_RST_V  0x1
-#define SYSTEM_TIMERGROUP_RST_S  13
-/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_UHCI1_RST    (BIT(12))
-#define SYSTEM_UHCI1_RST_M  (BIT(12))
-#define SYSTEM_UHCI1_RST_V  0x1
-#define SYSTEM_UHCI1_RST_S  12
-/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_LEDC_RST    (BIT(11))
-#define SYSTEM_LEDC_RST_M  (BIT(11))
-#define SYSTEM_LEDC_RST_V  0x1
-#define SYSTEM_LEDC_RST_S  11
-/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PCNT_RST    (BIT(10))
-#define SYSTEM_PCNT_RST_M  (BIT(10))
-#define SYSTEM_PCNT_RST_V  0x1
-#define SYSTEM_PCNT_RST_S  10
-/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_RMT_RST    (BIT(9))
-#define SYSTEM_RMT_RST_M  (BIT(9))
-#define SYSTEM_RMT_RST_V  0x1
-#define SYSTEM_RMT_RST_S  9
-/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_UHCI0_RST    (BIT(8))
-#define SYSTEM_UHCI0_RST_M  (BIT(8))
-#define SYSTEM_UHCI0_RST_V  0x1
-#define SYSTEM_UHCI0_RST_S  8
-/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_I2C_EXT0_RST    (BIT(7))
-#define SYSTEM_I2C_EXT0_RST_M  (BIT(7))
-#define SYSTEM_I2C_EXT0_RST_V  0x1
-#define SYSTEM_I2C_EXT0_RST_S  7
-/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_SPI2_RST    (BIT(6))
-#define SYSTEM_SPI2_RST_M  (BIT(6))
-#define SYSTEM_SPI2_RST_V  0x1
-#define SYSTEM_SPI2_RST_S  6
-/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_UART1_RST    (BIT(5))
-#define SYSTEM_UART1_RST_M  (BIT(5))
-#define SYSTEM_UART1_RST_V  0x1
-#define SYSTEM_UART1_RST_S  5
-/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_I2S0_RST    (BIT(4))
-#define SYSTEM_I2S0_RST_M  (BIT(4))
-#define SYSTEM_I2S0_RST_V  0x1
-#define SYSTEM_I2S0_RST_S  4
-/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_WDG_RST    (BIT(3))
-#define SYSTEM_WDG_RST_M  (BIT(3))
-#define SYSTEM_WDG_RST_V  0x1
-#define SYSTEM_WDG_RST_S  3
-/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_UART_RST    (BIT(2))
-#define SYSTEM_UART_RST_M  (BIT(2))
-#define SYSTEM_UART_RST_V  0x1
-#define SYSTEM_UART_RST_S  2
-/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_SPI01_RST    (BIT(1))
-#define SYSTEM_SPI01_RST_M  (BIT(1))
-#define SYSTEM_SPI01_RST_V  0x1
-#define SYSTEM_SPI01_RST_S  1
-/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_TIMERS_RST    (BIT(0))
-#define SYSTEM_TIMERS_RST_M  (BIT(0))
-#define SYSTEM_TIMERS_RST_V  0x1
-#define SYSTEM_TIMERS_RST_S  0
-
-#define SYSTEM_PERIP_RST_EN1_REG          (DR_REG_SYSTEM_BASE + 0x24)
-/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_USB_DEVICE_RST    (BIT(10))
-#define SYSTEM_USB_DEVICE_RST_M  (BIT(10))
-#define SYSTEM_USB_DEVICE_RST_V  0x1
-#define SYSTEM_USB_DEVICE_RST_S  10
-/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_UART2_RST    (BIT(9))
-#define SYSTEM_UART2_RST_M  (BIT(9))
-#define SYSTEM_UART2_RST_V  0x1
-#define SYSTEM_UART2_RST_S  9
-/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_LCD_CAM_RST    (BIT(8))
-#define SYSTEM_LCD_CAM_RST_M  (BIT(8))
-#define SYSTEM_LCD_CAM_RST_V  0x1
-#define SYSTEM_LCD_CAM_RST_S  8
-/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_SDIO_HOST_RST    (BIT(7))
-#define SYSTEM_SDIO_HOST_RST_M  (BIT(7))
-#define SYSTEM_SDIO_HOST_RST_V  0x1
-#define SYSTEM_SDIO_HOST_RST_S  7
-/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_DMA_RST    (BIT(6))
-#define SYSTEM_DMA_RST_M  (BIT(6))
-#define SYSTEM_DMA_RST_V  0x1
-#define SYSTEM_DMA_RST_S  6
-/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_HMAC_RST    (BIT(5))
-#define SYSTEM_CRYPTO_HMAC_RST_M  (BIT(5))
-#define SYSTEM_CRYPTO_HMAC_RST_V  0x1
-#define SYSTEM_CRYPTO_HMAC_RST_S  5
-/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_DS_RST    (BIT(4))
-#define SYSTEM_CRYPTO_DS_RST_M  (BIT(4))
-#define SYSTEM_CRYPTO_DS_RST_V  0x1
-#define SYSTEM_CRYPTO_DS_RST_S  4
-/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_RSA_RST    (BIT(3))
-#define SYSTEM_CRYPTO_RSA_RST_M  (BIT(3))
-#define SYSTEM_CRYPTO_RSA_RST_V  0x1
-#define SYSTEM_CRYPTO_RSA_RST_S  3
-/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_SHA_RST    (BIT(2))
-#define SYSTEM_CRYPTO_SHA_RST_M  (BIT(2))
-#define SYSTEM_CRYPTO_SHA_RST_V  0x1
-#define SYSTEM_CRYPTO_SHA_RST_S  2
-/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_CRYPTO_AES_RST    (BIT(1))
-#define SYSTEM_CRYPTO_AES_RST_M  (BIT(1))
-#define SYSTEM_CRYPTO_AES_RST_V  0x1
-#define SYSTEM_CRYPTO_AES_RST_S  1
-/* SYSTEM_PERI_BACKUP_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_PERI_BACKUP_RST    (BIT(0))
-#define SYSTEM_PERI_BACKUP_RST_M  (BIT(0))
-#define SYSTEM_PERI_BACKUP_RST_V  0x1
-#define SYSTEM_PERI_BACKUP_RST_S  0
-
-#define SYSTEM_BT_LPCK_DIV_INT_REG          (DR_REG_SYSTEM_BASE + 0x28)
-/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
-/*description: .*/
-#define SYSTEM_BT_LPCK_DIV_NUM    0x00000FFF
-#define SYSTEM_BT_LPCK_DIV_NUM_M  ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
-#define SYSTEM_BT_LPCK_DIV_NUM_V  0xFFF
-#define SYSTEM_BT_LPCK_DIV_NUM_S  0
-
-#define SYSTEM_BT_LPCK_DIV_FRAC_REG          (DR_REG_SYSTEM_BASE + 0x2C)
-/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_LPCLK_RTC_EN    (BIT(28))
-#define SYSTEM_LPCLK_RTC_EN_M  (BIT(28))
-#define SYSTEM_LPCLK_RTC_EN_V  0x1
-#define SYSTEM_LPCLK_RTC_EN_S  28
-/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_LPCLK_SEL_XTAL32K    (BIT(27))
-#define SYSTEM_LPCLK_SEL_XTAL32K_M  (BIT(27))
-#define SYSTEM_LPCLK_SEL_XTAL32K_V  0x1
-#define SYSTEM_LPCLK_SEL_XTAL32K_S  27
-/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_LPCLK_SEL_XTAL    (BIT(26))
-#define SYSTEM_LPCLK_SEL_XTAL_M  (BIT(26))
-#define SYSTEM_LPCLK_SEL_XTAL_V  0x1
-#define SYSTEM_LPCLK_SEL_XTAL_S  26
-/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_LPCLK_SEL_8M    (BIT(25))
-#define SYSTEM_LPCLK_SEL_8M_M  (BIT(25))
-#define SYSTEM_LPCLK_SEL_8M_V  0x1
-#define SYSTEM_LPCLK_SEL_8M_S  25
-/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_LPCLK_SEL_RTC_SLOW    (BIT(24))
-#define SYSTEM_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
-#define SYSTEM_LPCLK_SEL_RTC_SLOW_V  0x1
-#define SYSTEM_LPCLK_SEL_RTC_SLOW_S  24
-/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
-/*description: .*/
-#define SYSTEM_BT_LPCK_DIV_A    0x00000FFF
-#define SYSTEM_BT_LPCK_DIV_A_M  ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S))
-#define SYSTEM_BT_LPCK_DIV_A_V  0xFFF
-#define SYSTEM_BT_LPCK_DIV_A_S  12
-/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
-/*description: .*/
-#define SYSTEM_BT_LPCK_DIV_B    0x00000FFF
-#define SYSTEM_BT_LPCK_DIV_B_M  ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S))
-#define SYSTEM_BT_LPCK_DIV_B_V  0xFFF
-#define SYSTEM_BT_LPCK_DIV_B_S  0
-
-#define SYSTEM_CPU_INTR_FROM_CPU_0_REG          (DR_REG_SYSTEM_BASE + 0x30)
-/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CPU_INTR_FROM_CPU_0    (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_0_M  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_0_V  0x1
-#define SYSTEM_CPU_INTR_FROM_CPU_0_S  0
-
-#define SYSTEM_CPU_INTR_FROM_CPU_1_REG          (DR_REG_SYSTEM_BASE + 0x34)
-/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CPU_INTR_FROM_CPU_1    (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_1_M  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_1_V  0x1
-#define SYSTEM_CPU_INTR_FROM_CPU_1_S  0
-
-#define SYSTEM_CPU_INTR_FROM_CPU_2_REG          (DR_REG_SYSTEM_BASE + 0x38)
-/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CPU_INTR_FROM_CPU_2    (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_2_M  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_2_V  0x1
-#define SYSTEM_CPU_INTR_FROM_CPU_2_S  0
-
-#define SYSTEM_CPU_INTR_FROM_CPU_3_REG          (DR_REG_SYSTEM_BASE + 0x3C)
-/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_CPU_INTR_FROM_CPU_3    (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_3_M  (BIT(0))
-#define SYSTEM_CPU_INTR_FROM_CPU_3_V  0x1
-#define SYSTEM_CPU_INTR_FROM_CPU_3_S  0
-
-#define SYSTEM_RSA_PD_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x40)
-/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_RSA_MEM_FORCE_PD    (BIT(2))
-#define SYSTEM_RSA_MEM_FORCE_PD_M  (BIT(2))
-#define SYSTEM_RSA_MEM_FORCE_PD_V  0x1
-#define SYSTEM_RSA_MEM_FORCE_PD_S  2
-/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_RSA_MEM_FORCE_PU    (BIT(1))
-#define SYSTEM_RSA_MEM_FORCE_PU_M  (BIT(1))
-#define SYSTEM_RSA_MEM_FORCE_PU_V  0x1
-#define SYSTEM_RSA_MEM_FORCE_PU_S  1
-/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_RSA_MEM_PD    (BIT(0))
-#define SYSTEM_RSA_MEM_PD_M  (BIT(0))
-#define SYSTEM_RSA_MEM_PD_V  0x1
-#define SYSTEM_RSA_MEM_PD_S  0
-
-#define SYSTEM_EDMA_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x44)
-/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_EDMA_RESET    (BIT(1))
-#define SYSTEM_EDMA_RESET_M  (BIT(1))
-#define SYSTEM_EDMA_RESET_V  0x1
-#define SYSTEM_EDMA_RESET_S  1
-/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_EDMA_CLK_ON    (BIT(0))
-#define SYSTEM_EDMA_CLK_ON_M  (BIT(0))
-#define SYSTEM_EDMA_CLK_ON_V  0x1
-#define SYSTEM_EDMA_CLK_ON_S  0
-
-#define SYSTEM_CACHE_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x48)
-/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_DCACHE_RESET    (BIT(3))
-#define SYSTEM_DCACHE_RESET_M  (BIT(3))
-#define SYSTEM_DCACHE_RESET_V  0x1
-#define SYSTEM_DCACHE_RESET_S  3
-/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_DCACHE_CLK_ON    (BIT(2))
-#define SYSTEM_DCACHE_CLK_ON_M  (BIT(2))
-#define SYSTEM_DCACHE_CLK_ON_V  0x1
-#define SYSTEM_DCACHE_CLK_ON_S  2
-/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_ICACHE_RESET    (BIT(1))
-#define SYSTEM_ICACHE_RESET_M  (BIT(1))
-#define SYSTEM_ICACHE_RESET_V  0x1
-#define SYSTEM_ICACHE_RESET_S  1
-/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_ICACHE_CLK_ON    (BIT(0))
-#define SYSTEM_ICACHE_CLK_ON_M  (BIT(0))
-#define SYSTEM_ICACHE_CLK_ON_V  0x1
-#define SYSTEM_ICACHE_CLK_ON_S  0
-
-#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x4C)
-/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
-#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(3))
-#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
-#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
-/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
-#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (BIT(2))
-#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x1
-#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
-/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
-#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (BIT(1))
-#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x1
-#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
-/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
-#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (BIT(0))
-#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x1
-#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
-
-#define SYSTEM_RTC_FASTMEM_CONFIG_REG          (DR_REG_SYSTEM_BASE + 0x50)
-/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_RTC_MEM_CRC_FINISH    (BIT(31))
-#define SYSTEM_RTC_MEM_CRC_FINISH_M  (BIT(31))
-#define SYSTEM_RTC_MEM_CRC_FINISH_V  0x1
-#define SYSTEM_RTC_MEM_CRC_FINISH_S  31
-/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
-/*description: .*/
-#define SYSTEM_RTC_MEM_CRC_LEN    0x000007FF
-#define SYSTEM_RTC_MEM_CRC_LEN_M  ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S))
-#define SYSTEM_RTC_MEM_CRC_LEN_V  0x7FF
-#define SYSTEM_RTC_MEM_CRC_LEN_S  20
-/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
-/*description: .*/
-#define SYSTEM_RTC_MEM_CRC_ADDR    0x000007FF
-#define SYSTEM_RTC_MEM_CRC_ADDR_M  ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S))
-#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x7FF
-#define SYSTEM_RTC_MEM_CRC_ADDR_S  9
-/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_RTC_MEM_CRC_START    (BIT(8))
-#define SYSTEM_RTC_MEM_CRC_START_M  (BIT(8))
-#define SYSTEM_RTC_MEM_CRC_START_V  0x1
-#define SYSTEM_RTC_MEM_CRC_START_S  8
-
-#define SYSTEM_RTC_FASTMEM_CRC_REG          (DR_REG_SYSTEM_BASE + 0x54)
-/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: .*/
-#define SYSTEM_RTC_MEM_CRC_RES    0xFFFFFFFF
-#define SYSTEM_RTC_MEM_CRC_RES_M  ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S))
-#define SYSTEM_RTC_MEM_CRC_RES_V  0xFFFFFFFF
-#define SYSTEM_RTC_MEM_CRC_RES_S  0
-
-#define SYSTEM_REDUNDANT_ECO_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x58)
-/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_REDUNDANT_ECO_RESULT    (BIT(1))
-#define SYSTEM_REDUNDANT_ECO_RESULT_M  (BIT(1))
-#define SYSTEM_REDUNDANT_ECO_RESULT_V  0x1
-#define SYSTEM_REDUNDANT_ECO_RESULT_S  1
-/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_REDUNDANT_ECO_DRIVE    (BIT(0))
-#define SYSTEM_REDUNDANT_ECO_DRIVE_M  (BIT(0))
-#define SYSTEM_REDUNDANT_ECO_DRIVE_V  0x1
-#define SYSTEM_REDUNDANT_ECO_DRIVE_S  0
-
-#define SYSTEM_CLOCK_GATE_REG          (DR_REG_SYSTEM_BASE + 0x5C)
-/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define SYSTEM_CLK_EN    (BIT(0))
-#define SYSTEM_CLK_EN_M  (BIT(0))
-#define SYSTEM_CLK_EN_V  0x1
-#define SYSTEM_CLK_EN_S  0
-
-#define SYSTEM_SYSCLK_CONF_REG          (DR_REG_SYSTEM_BASE + 0x60)
-/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
-/*description: .*/
-#define SYSTEM_CLK_DIV_EN    (BIT(19))
-#define SYSTEM_CLK_DIV_EN_M  (BIT(19))
-#define SYSTEM_CLK_DIV_EN_V  0x1
-#define SYSTEM_CLK_DIV_EN_S  19
-/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */
-/*description: .*/
-#define SYSTEM_CLK_XTAL_FREQ    0x0000007F
-#define SYSTEM_CLK_XTAL_FREQ_M  ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S))
-#define SYSTEM_CLK_XTAL_FREQ_V  0x7F
-#define SYSTEM_CLK_XTAL_FREQ_S  12
-/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
-/*description: .*/
-#define SYSTEM_SOC_CLK_SEL    0x00000003
-#define SYSTEM_SOC_CLK_SEL_M  ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S))
-#define SYSTEM_SOC_CLK_SEL_V  0x3
-#define SYSTEM_SOC_CLK_SEL_S  10
-/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
-/*description: .*/
-#define SYSTEM_PRE_DIV_CNT    0x000003FF
-#define SYSTEM_PRE_DIV_CNT_M  ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
-#define SYSTEM_PRE_DIV_CNT_V  0x3FF
-#define SYSTEM_PRE_DIV_CNT_S  0
-
-#define SYSTEM_MEM_PVT_REG          (DR_REG_SYSTEM_BASE + 0x64)
-/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: .*/
-#define SYSTEM_MEM_VT_SEL    0x00000003
-#define SYSTEM_MEM_VT_SEL_M  ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S))
-#define SYSTEM_MEM_VT_SEL_V  0x3
-#define SYSTEM_MEM_VT_SEL_S  22
-/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_MEM_TIMING_ERR_CNT    0x0000FFFF
-#define SYSTEM_MEM_TIMING_ERR_CNT_M  ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S))
-#define SYSTEM_MEM_TIMING_ERR_CNT_V  0xFFFF
-#define SYSTEM_MEM_TIMING_ERR_CNT_S  6
-/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_MEM_PVT_MONITOR_EN    (BIT(5))
-#define SYSTEM_MEM_PVT_MONITOR_EN_M  (BIT(5))
-#define SYSTEM_MEM_PVT_MONITOR_EN_V  0x1
-#define SYSTEM_MEM_PVT_MONITOR_EN_S  5
-/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_MEM_ERR_CNT_CLR    (BIT(4))
-#define SYSTEM_MEM_ERR_CNT_CLR_M  (BIT(4))
-#define SYSTEM_MEM_ERR_CNT_CLR_V  0x1
-#define SYSTEM_MEM_ERR_CNT_CLR_S  4
-/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */
-/*description: .*/
-#define SYSTEM_MEM_PATH_LEN    0x0000000F
-#define SYSTEM_MEM_PATH_LEN_M  ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S))
-#define SYSTEM_MEM_PATH_LEN_V  0xF
-#define SYSTEM_MEM_PATH_LEN_S  0
-
-#define SYSTEM_COMB_PVT_LVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x68)
-/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_COMB_PVT_MONITOR_EN_LVT    (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V  0x1
-#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S  6
-/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_COMB_ERR_CNT_CLR_LVT    (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V  0x1
-#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S  5
-/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
-/*description: .*/
-#define SYSTEM_COMB_PATH_LEN_LVT    0x0000001F
-#define SYSTEM_COMB_PATH_LEN_LVT_M  ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
-#define SYSTEM_COMB_PATH_LEN_LVT_V  0x1F
-#define SYSTEM_COMB_PATH_LEN_LVT_S  0
-
-#define SYSTEM_COMB_PVT_NVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x6C)
-/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_COMB_PVT_MONITOR_EN_NVT    (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V  0x1
-#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S  6
-/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_COMB_ERR_CNT_CLR_NVT    (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V  0x1
-#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S  5
-/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
-/*description: .*/
-#define SYSTEM_COMB_PATH_LEN_NVT    0x0000001F
-#define SYSTEM_COMB_PATH_LEN_NVT_M  ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S))
-#define SYSTEM_COMB_PATH_LEN_NVT_V  0x1F
-#define SYSTEM_COMB_PATH_LEN_NVT_S  0
-
-#define SYSTEM_COMB_PVT_HVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x70)
-/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_COMB_PVT_MONITOR_EN_HVT    (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M  (BIT(6))
-#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V  0x1
-#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S  6
-/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define SYSTEM_COMB_ERR_CNT_CLR_HVT    (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M  (BIT(5))
-#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V  0x1
-#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S  5
-/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
-/*description: .*/
-#define SYSTEM_COMB_PATH_LEN_HVT    0x0000001F
-#define SYSTEM_COMB_PATH_LEN_HVT_M  ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S))
-#define SYSTEM_COMB_PATH_LEN_HVT_V  0x1F
-#define SYSTEM_COMB_PATH_LEN_HVT_S  0
-
-#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x74)
-/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S  0
-
-#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x78)
-/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S  0
-
-#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x7C)
-/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S  0
-
-#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x80)
-/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S  0
-
-#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x84)
-/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S  0
-
-#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x88)
-/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S  0
-
-#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x8C)
-/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S  0
-
-#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x90)
-/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S  0
-
-#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x94)
-/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S  0
-
-#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x98)
-/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S  0
-
-#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x9C)
-/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S  0
-
-#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0xA0)
-/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
-/*description: .*/
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3    0x0000FFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S))
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V  0xFFFF
-#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S  0
-
-#define SYSTEM_DATE_REG          (DR_REG_SYSTEM_BASE + 0xFFC)
-/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101220 ; */
-/*description: .*/
-#define SYSTEM_DATE    0x0FFFFFFF
-#define SYSTEM_DATE_M  ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
-#define SYSTEM_DATE_V  0xFFFFFFF
-#define SYSTEM_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SYSTEM_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/system_struct.h b/components/soc/esp32s3/include/soc/system_struct.h
deleted file mode 100644
index 6c4ce1f1182..00000000000
--- a/components/soc/esp32s3/include/soc/system_struct.h
+++ /dev/null
@@ -1,1420 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_SYSTEM_STRUCT_H_
-#define _SOC_SYSTEM_STRUCT_H_
-
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef volatile struct system_dev_s {
-    union {
-        struct {
-            uint32_t control_core_1_runstall       :    1;
-            uint32_t control_core_1_clkgate_en     :    1;
-            uint32_t control_core_1_reseting       :    1;
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } core_1_control_0;
-    uint32_t core_1_control_1;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;
-            uint32_t clk_en_assist_debug           :    1;
-            uint32_t clk_en_dedicated_gpio         :    1;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } cpu_peri_clk_en;
-    union {
-        struct {
-            uint32_t reserved0                     :    6;
-            uint32_t rst_en_assist_debug           :    1;
-            uint32_t rst_en_dedicated_gpio         :    1;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } cpu_peri_rst_en;
-    union {
-        struct {
-            uint32_t cpuperiod_sel                 :    2;
-            uint32_t pll_freq_sel                  :    1;
-            uint32_t cpu_wait_mode_force_on        :    1;
-            uint32_t cpu_waiti_delay_num           :    4;
-            uint32_t reserved8                     :    24;
-        };
-        uint32_t val;
-    } cpu_per_conf;
-    union {
-        struct {
-            uint32_t lslp_mem_pd_mask              :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } mem_pd_mask;
-    union {
-        struct {
-            uint32_t timers_clk_en                 :    1;
-            uint32_t spi01_clk_en                  :    1;
-            uint32_t uart_clk_en                   :    1;
-            uint32_t wdg_clk_en                    :    1;
-            uint32_t i2s0_clk_en                   :    1;
-            uint32_t uart1_clk_en                  :    1;
-            uint32_t spi2_clk_en                   :    1;
-            uint32_t i2c_ext0_clk_en               :    1;
-            uint32_t uhci0_clk_en                  :    1;
-            uint32_t rmt_clk_en                    :    1;
-            uint32_t pcnt_clk_en                   :    1;
-            uint32_t ledc_clk_en                   :    1;
-            uint32_t uhci1_clk_en                  :    1;
-            uint32_t timergroup_clk_en             :    1;
-            uint32_t efuse_clk_en                  :    1;
-            uint32_t timergroup1_clk_en            :    1;
-            uint32_t spi3_clk_en                   :    1;
-            uint32_t pwm0_clk_en                   :    1;
-            uint32_t i2c_ext1_clk_en               :    1;
-            uint32_t can_clk_en                    :    1;
-            uint32_t pwm1_clk_en                   :    1;
-            uint32_t i2s1_clk_en                   :    1;
-            uint32_t spi2_dma_clk_en               :    1;
-            uint32_t usb_clk_en                    :    1;
-            uint32_t uart_mem_clk_en               :    1;
-            uint32_t pwm2_clk_en                   :    1;
-            uint32_t pwm3_clk_en                   :    1;
-            uint32_t spi3_dma_clk_en               :    1;
-            uint32_t apb_saradc_clk_en             :    1;
-            uint32_t systimer_clk_en               :    1;
-            uint32_t adc2_arb_clk_en               :    1;
-            uint32_t spi4_clk_en                   :    1;
-        };
-        uint32_t val;
-    } perip_clk_en0;
-    union {
-        struct {
-            uint32_t peri_backup_clk_en            :    1;
-            uint32_t crypto_aes_clk_en             :    1;
-            uint32_t crypto_sha_clk_en             :    1;
-            uint32_t crypto_rsa_clk_en             :    1;
-            uint32_t crypto_ds_clk_en              :    1;
-            uint32_t crypto_hmac_clk_en            :    1;
-            uint32_t dma_clk_en                    :    1;
-            uint32_t sdio_host_clk_en              :    1;
-            uint32_t lcd_cam_clk_en                :    1;
-            uint32_t uart2_clk_en                  :    1;
-            uint32_t usb_device_clk_en             :    1;
-            uint32_t reserved11                    :    21;
-        };
-        uint32_t val;
-    } perip_clk_en1;
-    union {
-        struct {
-            uint32_t timers_rst                    :    1;
-            uint32_t spi01_rst                     :    1;
-            uint32_t uart_rst                      :    1;
-            uint32_t wdg_rst                       :    1;
-            uint32_t i2s0_rst                      :    1;
-            uint32_t uart1_rst                     :    1;
-            uint32_t spi2_rst                      :    1;
-            uint32_t i2c_ext0_rst                  :    1;
-            uint32_t uhci0_rst                     :    1;
-            uint32_t rmt_rst                       :    1;
-            uint32_t pcnt_rst                      :    1;
-            uint32_t ledc_rst                      :    1;
-            uint32_t uhci1_rst                     :    1;
-            uint32_t timergroup_rst                :    1;
-            uint32_t efuse_rst                     :    1;
-            uint32_t timergroup1_rst               :    1;
-            uint32_t spi3_rst                      :    1;
-            uint32_t pwm0_rst                      :    1;
-            uint32_t i2c_ext1_rst                  :    1;
-            uint32_t can_rst                       :    1;
-            uint32_t pwm1_rst                      :    1;
-            uint32_t i2s1_rst                      :    1;
-            uint32_t spi2_dma_rst                  :    1;
-            uint32_t usb_rst                       :    1;
-            uint32_t uart_mem_rst                  :    1;
-            uint32_t pwm2_rst                      :    1;
-            uint32_t pwm3_rst                      :    1;
-            uint32_t spi3_dma_rst                  :    1;
-            uint32_t apb_saradc_rst                :    1;
-            uint32_t systimer_rst                  :    1;
-            uint32_t adc2_arb_rst                  :    1;
-            uint32_t spi4_rst                      :    1;
-        };
-        uint32_t val;
-    } perip_rst_en0;
-    union {
-        struct {
-            uint32_t peri_backup_rst               :    1;
-            uint32_t crypto_aes_rst                :    1;
-            uint32_t crypto_sha_rst                :    1;
-            uint32_t crypto_rsa_rst                :    1;
-            uint32_t crypto_ds_rst                 :    1;
-            uint32_t crypto_hmac_rst               :    1;
-            uint32_t dma_rst                       :    1;
-            uint32_t sdio_host_rst                 :    1;
-            uint32_t lcd_cam_rst                   :    1;
-            uint32_t uart2_rst                     :    1;
-            uint32_t usb_device_rst                :    1;
-            uint32_t reserved11                    :    21;
-        };
-        uint32_t val;
-    } perip_rst_en1;
-    union {
-        struct {
-            uint32_t bt_lpck_div_num               :    12;
-            uint32_t reserved12                    :    20;
-        };
-        uint32_t val;
-    } bt_lpck_div_int;
-    union {
-        struct {
-            uint32_t bt_lpck_div_b                 :    12;
-            uint32_t bt_lpck_div_a                 :    12;
-            uint32_t lpclk_sel_rtc_slow            :    1;
-            uint32_t lpclk_sel_8m                  :    1;
-            uint32_t lpclk_sel_xtal                :    1;
-            uint32_t lpclk_sel_xtal32k             :    1;
-            uint32_t lpclk_rtc_en                  :    1;
-            uint32_t reserved29                    :    3;
-        };
-        uint32_t val;
-    } bt_lpck_div_frac;
-    union {
-        struct {
-            uint32_t cpu_intr_from_cpu_0           :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cpu_intr_from_cpu_0;
-    union {
-        struct {
-            uint32_t cpu_intr_from_cpu_1           :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cpu_intr_from_cpu_1;
-    union {
-        struct {
-            uint32_t cpu_intr_from_cpu_2           :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cpu_intr_from_cpu_2;
-    union {
-        struct {
-            uint32_t cpu_intr_from_cpu_3           :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } cpu_intr_from_cpu_3;
-    union {
-        struct {
-            uint32_t rsa_mem_pd                    :    1;
-            uint32_t rsa_mem_force_pu              :    1;
-            uint32_t rsa_mem_force_pd              :    1;
-            uint32_t reserved3                     :    29;
-        };
-        uint32_t val;
-    } rsa_pd_ctrl;
-    union {
-        struct {
-            uint32_t edma_clk_on                   :    1;
-            uint32_t edma_reset                    :    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } edma_ctrl;
-    union {
-        struct {
-            uint32_t icache_clk_on                 :    1;
-            uint32_t icache_reset                  :    1;
-            uint32_t dcache_clk_on                 :    1;
-            uint32_t dcache_reset                  :    1;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } cache_control;
-    union {
-        struct {
-            uint32_t enable_spi_manual_encrypt     :    1;
-            uint32_t enable_download_db_encrypt    :    1;
-            uint32_t enable_download_g0cb_decrypt  :    1;
-            uint32_t enable_download_manual_encrypt:    1;
-            uint32_t reserved4                     :    28;
-        };
-        uint32_t val;
-    } external_device_encrypt_decrypt_control;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;
-            uint32_t rtc_mem_crc_start             :    1;
-            uint32_t rtc_mem_crc_addr              :    11;
-            uint32_t rtc_mem_crc_len               :    11;
-            uint32_t rtc_mem_crc_finish            :    1;
-        };
-        uint32_t val;
-    } rtc_fastmem_config;
-    uint32_t rtc_fastmem_crc;
-    union {
-        struct {
-            uint32_t redundant_eco_drive           :    1;
-            uint32_t redundant_eco_result          :    1;
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } redundant_eco_ctrl;
-    union {
-        struct {
-            uint32_t clk_en                        :    1;
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } clock_gate;
-    union {
-        struct {
-            uint32_t pre_div_cnt                   :    10;
-            uint32_t soc_clk_sel                   :    2;
-            uint32_t clk_xtal_freq                 :    7;
-            uint32_t clk_div_en                    :    1;
-            uint32_t reserved20                    :    12;
-        };
-        uint32_t val;
-    } sysclk_conf;
-    union {
-        struct {
-            uint32_t mem_path_len                  :    4;
-            uint32_t mem_err_cnt_clr               :    1;
-            uint32_t mem_pvt_monitor_en            :    1;
-            uint32_t mem_timing_err_cnt            :    16;
-            uint32_t mem_vt_sel                    :    2;
-            uint32_t reserved24                    :    8;
-        };
-        uint32_t val;
-    } mem_pvt;
-    union {
-        struct {
-            uint32_t comb_path_len_lvt             :    5;
-            uint32_t comb_err_cnt_clr_lvt          :    1;
-            uint32_t comb_pvt_monitor_en_lvt       :    1;
-            uint32_t reserved7                     :    18;
-            uint32_t reserved25                    :    7;
-        };
-        uint32_t val;
-    } comb_pvt_lvt_conf;
-    union {
-        struct {
-            uint32_t comb_path_len_nvt             :    5;
-            uint32_t comb_err_cnt_clr_nvt          :    1;
-            uint32_t comb_pvt_monitor_en_nvt       :    1;
-            uint32_t reserved7                     :    18;
-            uint32_t reserved25                    :    7;
-        };
-        uint32_t val;
-    } comb_pvt_nvt_conf;
-    union {
-        struct {
-            uint32_t comb_path_len_hvt             :    5;
-            uint32_t comb_err_cnt_clr_hvt          :    1;
-            uint32_t comb_pvt_monitor_en_hvt       :    1;
-            uint32_t reserved7                     :    18;
-            uint32_t reserved25                    :    7;
-        };
-        uint32_t val;
-    } comb_pvt_hvt_conf;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_lvt_site0 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_lvt_site0;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_nvt_site0 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_nvt_site0;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_hvt_site0 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_hvt_site0;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_lvt_site1 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_lvt_site1;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_nvt_site1 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_nvt_site1;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_hvt_site1 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_hvt_site1;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_lvt_site2 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_lvt_site2;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_nvt_site2 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_nvt_site2;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_hvt_site2 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_hvt_site2;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_lvt_site3 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_lvt_site3;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_nvt_site3 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_nvt_site3;
-    union {
-        struct {
-            uint32_t comb_timing_err_cnt_hvt_site3 :    16;
-            uint32_t reserved16                    :    16;
-        };
-        uint32_t val;
-    } comb_pvt_err_hvt_site3;
-    uint32_t reserved_a4;
-    uint32_t reserved_a8;
-    uint32_t reserved_ac;
-    uint32_t reserved_b0;
-    uint32_t reserved_b4;
-    uint32_t reserved_b8;
-    uint32_t reserved_bc;
-    uint32_t reserved_c0;
-    uint32_t reserved_c4;
-    uint32_t reserved_c8;
-    uint32_t reserved_cc;
-    uint32_t reserved_d0;
-    uint32_t reserved_d4;
-    uint32_t reserved_d8;
-    uint32_t reserved_dc;
-    uint32_t reserved_e0;
-    uint32_t reserved_e4;
-    uint32_t reserved_e8;
-    uint32_t reserved_ec;
-    uint32_t reserved_f0;
-    uint32_t reserved_f4;
-    uint32_t reserved_f8;
-    uint32_t reserved_fc;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    uint32_t reserved_3fc;
-    uint32_t reserved_400;
-    uint32_t reserved_404;
-    uint32_t reserved_408;
-    uint32_t reserved_40c;
-    uint32_t reserved_410;
-    uint32_t reserved_414;
-    uint32_t reserved_418;
-    uint32_t reserved_41c;
-    uint32_t reserved_420;
-    uint32_t reserved_424;
-    uint32_t reserved_428;
-    uint32_t reserved_42c;
-    uint32_t reserved_430;
-    uint32_t reserved_434;
-    uint32_t reserved_438;
-    uint32_t reserved_43c;
-    uint32_t reserved_440;
-    uint32_t reserved_444;
-    uint32_t reserved_448;
-    uint32_t reserved_44c;
-    uint32_t reserved_450;
-    uint32_t reserved_454;
-    uint32_t reserved_458;
-    uint32_t reserved_45c;
-    uint32_t reserved_460;
-    uint32_t reserved_464;
-    uint32_t reserved_468;
-    uint32_t reserved_46c;
-    uint32_t reserved_470;
-    uint32_t reserved_474;
-    uint32_t reserved_478;
-    uint32_t reserved_47c;
-    uint32_t reserved_480;
-    uint32_t reserved_484;
-    uint32_t reserved_488;
-    uint32_t reserved_48c;
-    uint32_t reserved_490;
-    uint32_t reserved_494;
-    uint32_t reserved_498;
-    uint32_t reserved_49c;
-    uint32_t reserved_4a0;
-    uint32_t reserved_4a4;
-    uint32_t reserved_4a8;
-    uint32_t reserved_4ac;
-    uint32_t reserved_4b0;
-    uint32_t reserved_4b4;
-    uint32_t reserved_4b8;
-    uint32_t reserved_4bc;
-    uint32_t reserved_4c0;
-    uint32_t reserved_4c4;
-    uint32_t reserved_4c8;
-    uint32_t reserved_4cc;
-    uint32_t reserved_4d0;
-    uint32_t reserved_4d4;
-    uint32_t reserved_4d8;
-    uint32_t reserved_4dc;
-    uint32_t reserved_4e0;
-    uint32_t reserved_4e4;
-    uint32_t reserved_4e8;
-    uint32_t reserved_4ec;
-    uint32_t reserved_4f0;
-    uint32_t reserved_4f4;
-    uint32_t reserved_4f8;
-    uint32_t reserved_4fc;
-    uint32_t reserved_500;
-    uint32_t reserved_504;
-    uint32_t reserved_508;
-    uint32_t reserved_50c;
-    uint32_t reserved_510;
-    uint32_t reserved_514;
-    uint32_t reserved_518;
-    uint32_t reserved_51c;
-    uint32_t reserved_520;
-    uint32_t reserved_524;
-    uint32_t reserved_528;
-    uint32_t reserved_52c;
-    uint32_t reserved_530;
-    uint32_t reserved_534;
-    uint32_t reserved_538;
-    uint32_t reserved_53c;
-    uint32_t reserved_540;
-    uint32_t reserved_544;
-    uint32_t reserved_548;
-    uint32_t reserved_54c;
-    uint32_t reserved_550;
-    uint32_t reserved_554;
-    uint32_t reserved_558;
-    uint32_t reserved_55c;
-    uint32_t reserved_560;
-    uint32_t reserved_564;
-    uint32_t reserved_568;
-    uint32_t reserved_56c;
-    uint32_t reserved_570;
-    uint32_t reserved_574;
-    uint32_t reserved_578;
-    uint32_t reserved_57c;
-    uint32_t reserved_580;
-    uint32_t reserved_584;
-    uint32_t reserved_588;
-    uint32_t reserved_58c;
-    uint32_t reserved_590;
-    uint32_t reserved_594;
-    uint32_t reserved_598;
-    uint32_t reserved_59c;
-    uint32_t reserved_5a0;
-    uint32_t reserved_5a4;
-    uint32_t reserved_5a8;
-    uint32_t reserved_5ac;
-    uint32_t reserved_5b0;
-    uint32_t reserved_5b4;
-    uint32_t reserved_5b8;
-    uint32_t reserved_5bc;
-    uint32_t reserved_5c0;
-    uint32_t reserved_5c4;
-    uint32_t reserved_5c8;
-    uint32_t reserved_5cc;
-    uint32_t reserved_5d0;
-    uint32_t reserved_5d4;
-    uint32_t reserved_5d8;
-    uint32_t reserved_5dc;
-    uint32_t reserved_5e0;
-    uint32_t reserved_5e4;
-    uint32_t reserved_5e8;
-    uint32_t reserved_5ec;
-    uint32_t reserved_5f0;
-    uint32_t reserved_5f4;
-    uint32_t reserved_5f8;
-    uint32_t reserved_5fc;
-    uint32_t reserved_600;
-    uint32_t reserved_604;
-    uint32_t reserved_608;
-    uint32_t reserved_60c;
-    uint32_t reserved_610;
-    uint32_t reserved_614;
-    uint32_t reserved_618;
-    uint32_t reserved_61c;
-    uint32_t reserved_620;
-    uint32_t reserved_624;
-    uint32_t reserved_628;
-    uint32_t reserved_62c;
-    uint32_t reserved_630;
-    uint32_t reserved_634;
-    uint32_t reserved_638;
-    uint32_t reserved_63c;
-    uint32_t reserved_640;
-    uint32_t reserved_644;
-    uint32_t reserved_648;
-    uint32_t reserved_64c;
-    uint32_t reserved_650;
-    uint32_t reserved_654;
-    uint32_t reserved_658;
-    uint32_t reserved_65c;
-    uint32_t reserved_660;
-    uint32_t reserved_664;
-    uint32_t reserved_668;
-    uint32_t reserved_66c;
-    uint32_t reserved_670;
-    uint32_t reserved_674;
-    uint32_t reserved_678;
-    uint32_t reserved_67c;
-    uint32_t reserved_680;
-    uint32_t reserved_684;
-    uint32_t reserved_688;
-    uint32_t reserved_68c;
-    uint32_t reserved_690;
-    uint32_t reserved_694;
-    uint32_t reserved_698;
-    uint32_t reserved_69c;
-    uint32_t reserved_6a0;
-    uint32_t reserved_6a4;
-    uint32_t reserved_6a8;
-    uint32_t reserved_6ac;
-    uint32_t reserved_6b0;
-    uint32_t reserved_6b4;
-    uint32_t reserved_6b8;
-    uint32_t reserved_6bc;
-    uint32_t reserved_6c0;
-    uint32_t reserved_6c4;
-    uint32_t reserved_6c8;
-    uint32_t reserved_6cc;
-    uint32_t reserved_6d0;
-    uint32_t reserved_6d4;
-    uint32_t reserved_6d8;
-    uint32_t reserved_6dc;
-    uint32_t reserved_6e0;
-    uint32_t reserved_6e4;
-    uint32_t reserved_6e8;
-    uint32_t reserved_6ec;
-    uint32_t reserved_6f0;
-    uint32_t reserved_6f4;
-    uint32_t reserved_6f8;
-    uint32_t reserved_6fc;
-    uint32_t reserved_700;
-    uint32_t reserved_704;
-    uint32_t reserved_708;
-    uint32_t reserved_70c;
-    uint32_t reserved_710;
-    uint32_t reserved_714;
-    uint32_t reserved_718;
-    uint32_t reserved_71c;
-    uint32_t reserved_720;
-    uint32_t reserved_724;
-    uint32_t reserved_728;
-    uint32_t reserved_72c;
-    uint32_t reserved_730;
-    uint32_t reserved_734;
-    uint32_t reserved_738;
-    uint32_t reserved_73c;
-    uint32_t reserved_740;
-    uint32_t reserved_744;
-    uint32_t reserved_748;
-    uint32_t reserved_74c;
-    uint32_t reserved_750;
-    uint32_t reserved_754;
-    uint32_t reserved_758;
-    uint32_t reserved_75c;
-    uint32_t reserved_760;
-    uint32_t reserved_764;
-    uint32_t reserved_768;
-    uint32_t reserved_76c;
-    uint32_t reserved_770;
-    uint32_t reserved_774;
-    uint32_t reserved_778;
-    uint32_t reserved_77c;
-    uint32_t reserved_780;
-    uint32_t reserved_784;
-    uint32_t reserved_788;
-    uint32_t reserved_78c;
-    uint32_t reserved_790;
-    uint32_t reserved_794;
-    uint32_t reserved_798;
-    uint32_t reserved_79c;
-    uint32_t reserved_7a0;
-    uint32_t reserved_7a4;
-    uint32_t reserved_7a8;
-    uint32_t reserved_7ac;
-    uint32_t reserved_7b0;
-    uint32_t reserved_7b4;
-    uint32_t reserved_7b8;
-    uint32_t reserved_7bc;
-    uint32_t reserved_7c0;
-    uint32_t reserved_7c4;
-    uint32_t reserved_7c8;
-    uint32_t reserved_7cc;
-    uint32_t reserved_7d0;
-    uint32_t reserved_7d4;
-    uint32_t reserved_7d8;
-    uint32_t reserved_7dc;
-    uint32_t reserved_7e0;
-    uint32_t reserved_7e4;
-    uint32_t reserved_7e8;
-    uint32_t reserved_7ec;
-    uint32_t reserved_7f0;
-    uint32_t reserved_7f4;
-    uint32_t reserved_7f8;
-    uint32_t reserved_7fc;
-    uint32_t reserved_800;
-    uint32_t reserved_804;
-    uint32_t reserved_808;
-    uint32_t reserved_80c;
-    uint32_t reserved_810;
-    uint32_t reserved_814;
-    uint32_t reserved_818;
-    uint32_t reserved_81c;
-    uint32_t reserved_820;
-    uint32_t reserved_824;
-    uint32_t reserved_828;
-    uint32_t reserved_82c;
-    uint32_t reserved_830;
-    uint32_t reserved_834;
-    uint32_t reserved_838;
-    uint32_t reserved_83c;
-    uint32_t reserved_840;
-    uint32_t reserved_844;
-    uint32_t reserved_848;
-    uint32_t reserved_84c;
-    uint32_t reserved_850;
-    uint32_t reserved_854;
-    uint32_t reserved_858;
-    uint32_t reserved_85c;
-    uint32_t reserved_860;
-    uint32_t reserved_864;
-    uint32_t reserved_868;
-    uint32_t reserved_86c;
-    uint32_t reserved_870;
-    uint32_t reserved_874;
-    uint32_t reserved_878;
-    uint32_t reserved_87c;
-    uint32_t reserved_880;
-    uint32_t reserved_884;
-    uint32_t reserved_888;
-    uint32_t reserved_88c;
-    uint32_t reserved_890;
-    uint32_t reserved_894;
-    uint32_t reserved_898;
-    uint32_t reserved_89c;
-    uint32_t reserved_8a0;
-    uint32_t reserved_8a4;
-    uint32_t reserved_8a8;
-    uint32_t reserved_8ac;
-    uint32_t reserved_8b0;
-    uint32_t reserved_8b4;
-    uint32_t reserved_8b8;
-    uint32_t reserved_8bc;
-    uint32_t reserved_8c0;
-    uint32_t reserved_8c4;
-    uint32_t reserved_8c8;
-    uint32_t reserved_8cc;
-    uint32_t reserved_8d0;
-    uint32_t reserved_8d4;
-    uint32_t reserved_8d8;
-    uint32_t reserved_8dc;
-    uint32_t reserved_8e0;
-    uint32_t reserved_8e4;
-    uint32_t reserved_8e8;
-    uint32_t reserved_8ec;
-    uint32_t reserved_8f0;
-    uint32_t reserved_8f4;
-    uint32_t reserved_8f8;
-    uint32_t reserved_8fc;
-    uint32_t reserved_900;
-    uint32_t reserved_904;
-    uint32_t reserved_908;
-    uint32_t reserved_90c;
-    uint32_t reserved_910;
-    uint32_t reserved_914;
-    uint32_t reserved_918;
-    uint32_t reserved_91c;
-    uint32_t reserved_920;
-    uint32_t reserved_924;
-    uint32_t reserved_928;
-    uint32_t reserved_92c;
-    uint32_t reserved_930;
-    uint32_t reserved_934;
-    uint32_t reserved_938;
-    uint32_t reserved_93c;
-    uint32_t reserved_940;
-    uint32_t reserved_944;
-    uint32_t reserved_948;
-    uint32_t reserved_94c;
-    uint32_t reserved_950;
-    uint32_t reserved_954;
-    uint32_t reserved_958;
-    uint32_t reserved_95c;
-    uint32_t reserved_960;
-    uint32_t reserved_964;
-    uint32_t reserved_968;
-    uint32_t reserved_96c;
-    uint32_t reserved_970;
-    uint32_t reserved_974;
-    uint32_t reserved_978;
-    uint32_t reserved_97c;
-    uint32_t reserved_980;
-    uint32_t reserved_984;
-    uint32_t reserved_988;
-    uint32_t reserved_98c;
-    uint32_t reserved_990;
-    uint32_t reserved_994;
-    uint32_t reserved_998;
-    uint32_t reserved_99c;
-    uint32_t reserved_9a0;
-    uint32_t reserved_9a4;
-    uint32_t reserved_9a8;
-    uint32_t reserved_9ac;
-    uint32_t reserved_9b0;
-    uint32_t reserved_9b4;
-    uint32_t reserved_9b8;
-    uint32_t reserved_9bc;
-    uint32_t reserved_9c0;
-    uint32_t reserved_9c4;
-    uint32_t reserved_9c8;
-    uint32_t reserved_9cc;
-    uint32_t reserved_9d0;
-    uint32_t reserved_9d4;
-    uint32_t reserved_9d8;
-    uint32_t reserved_9dc;
-    uint32_t reserved_9e0;
-    uint32_t reserved_9e4;
-    uint32_t reserved_9e8;
-    uint32_t reserved_9ec;
-    uint32_t reserved_9f0;
-    uint32_t reserved_9f4;
-    uint32_t reserved_9f8;
-    uint32_t reserved_9fc;
-    uint32_t reserved_a00;
-    uint32_t reserved_a04;
-    uint32_t reserved_a08;
-    uint32_t reserved_a0c;
-    uint32_t reserved_a10;
-    uint32_t reserved_a14;
-    uint32_t reserved_a18;
-    uint32_t reserved_a1c;
-    uint32_t reserved_a20;
-    uint32_t reserved_a24;
-    uint32_t reserved_a28;
-    uint32_t reserved_a2c;
-    uint32_t reserved_a30;
-    uint32_t reserved_a34;
-    uint32_t reserved_a38;
-    uint32_t reserved_a3c;
-    uint32_t reserved_a40;
-    uint32_t reserved_a44;
-    uint32_t reserved_a48;
-    uint32_t reserved_a4c;
-    uint32_t reserved_a50;
-    uint32_t reserved_a54;
-    uint32_t reserved_a58;
-    uint32_t reserved_a5c;
-    uint32_t reserved_a60;
-    uint32_t reserved_a64;
-    uint32_t reserved_a68;
-    uint32_t reserved_a6c;
-    uint32_t reserved_a70;
-    uint32_t reserved_a74;
-    uint32_t reserved_a78;
-    uint32_t reserved_a7c;
-    uint32_t reserved_a80;
-    uint32_t reserved_a84;
-    uint32_t reserved_a88;
-    uint32_t reserved_a8c;
-    uint32_t reserved_a90;
-    uint32_t reserved_a94;
-    uint32_t reserved_a98;
-    uint32_t reserved_a9c;
-    uint32_t reserved_aa0;
-    uint32_t reserved_aa4;
-    uint32_t reserved_aa8;
-    uint32_t reserved_aac;
-    uint32_t reserved_ab0;
-    uint32_t reserved_ab4;
-    uint32_t reserved_ab8;
-    uint32_t reserved_abc;
-    uint32_t reserved_ac0;
-    uint32_t reserved_ac4;
-    uint32_t reserved_ac8;
-    uint32_t reserved_acc;
-    uint32_t reserved_ad0;
-    uint32_t reserved_ad4;
-    uint32_t reserved_ad8;
-    uint32_t reserved_adc;
-    uint32_t reserved_ae0;
-    uint32_t reserved_ae4;
-    uint32_t reserved_ae8;
-    uint32_t reserved_aec;
-    uint32_t reserved_af0;
-    uint32_t reserved_af4;
-    uint32_t reserved_af8;
-    uint32_t reserved_afc;
-    uint32_t reserved_b00;
-    uint32_t reserved_b04;
-    uint32_t reserved_b08;
-    uint32_t reserved_b0c;
-    uint32_t reserved_b10;
-    uint32_t reserved_b14;
-    uint32_t reserved_b18;
-    uint32_t reserved_b1c;
-    uint32_t reserved_b20;
-    uint32_t reserved_b24;
-    uint32_t reserved_b28;
-    uint32_t reserved_b2c;
-    uint32_t reserved_b30;
-    uint32_t reserved_b34;
-    uint32_t reserved_b38;
-    uint32_t reserved_b3c;
-    uint32_t reserved_b40;
-    uint32_t reserved_b44;
-    uint32_t reserved_b48;
-    uint32_t reserved_b4c;
-    uint32_t reserved_b50;
-    uint32_t reserved_b54;
-    uint32_t reserved_b58;
-    uint32_t reserved_b5c;
-    uint32_t reserved_b60;
-    uint32_t reserved_b64;
-    uint32_t reserved_b68;
-    uint32_t reserved_b6c;
-    uint32_t reserved_b70;
-    uint32_t reserved_b74;
-    uint32_t reserved_b78;
-    uint32_t reserved_b7c;
-    uint32_t reserved_b80;
-    uint32_t reserved_b84;
-    uint32_t reserved_b88;
-    uint32_t reserved_b8c;
-    uint32_t reserved_b90;
-    uint32_t reserved_b94;
-    uint32_t reserved_b98;
-    uint32_t reserved_b9c;
-    uint32_t reserved_ba0;
-    uint32_t reserved_ba4;
-    uint32_t reserved_ba8;
-    uint32_t reserved_bac;
-    uint32_t reserved_bb0;
-    uint32_t reserved_bb4;
-    uint32_t reserved_bb8;
-    uint32_t reserved_bbc;
-    uint32_t reserved_bc0;
-    uint32_t reserved_bc4;
-    uint32_t reserved_bc8;
-    uint32_t reserved_bcc;
-    uint32_t reserved_bd0;
-    uint32_t reserved_bd4;
-    uint32_t reserved_bd8;
-    uint32_t reserved_bdc;
-    uint32_t reserved_be0;
-    uint32_t reserved_be4;
-    uint32_t reserved_be8;
-    uint32_t reserved_bec;
-    uint32_t reserved_bf0;
-    uint32_t reserved_bf4;
-    uint32_t reserved_bf8;
-    uint32_t reserved_bfc;
-    uint32_t reserved_c00;
-    uint32_t reserved_c04;
-    uint32_t reserved_c08;
-    uint32_t reserved_c0c;
-    uint32_t reserved_c10;
-    uint32_t reserved_c14;
-    uint32_t reserved_c18;
-    uint32_t reserved_c1c;
-    uint32_t reserved_c20;
-    uint32_t reserved_c24;
-    uint32_t reserved_c28;
-    uint32_t reserved_c2c;
-    uint32_t reserved_c30;
-    uint32_t reserved_c34;
-    uint32_t reserved_c38;
-    uint32_t reserved_c3c;
-    uint32_t reserved_c40;
-    uint32_t reserved_c44;
-    uint32_t reserved_c48;
-    uint32_t reserved_c4c;
-    uint32_t reserved_c50;
-    uint32_t reserved_c54;
-    uint32_t reserved_c58;
-    uint32_t reserved_c5c;
-    uint32_t reserved_c60;
-    uint32_t reserved_c64;
-    uint32_t reserved_c68;
-    uint32_t reserved_c6c;
-    uint32_t reserved_c70;
-    uint32_t reserved_c74;
-    uint32_t reserved_c78;
-    uint32_t reserved_c7c;
-    uint32_t reserved_c80;
-    uint32_t reserved_c84;
-    uint32_t reserved_c88;
-    uint32_t reserved_c8c;
-    uint32_t reserved_c90;
-    uint32_t reserved_c94;
-    uint32_t reserved_c98;
-    uint32_t reserved_c9c;
-    uint32_t reserved_ca0;
-    uint32_t reserved_ca4;
-    uint32_t reserved_ca8;
-    uint32_t reserved_cac;
-    uint32_t reserved_cb0;
-    uint32_t reserved_cb4;
-    uint32_t reserved_cb8;
-    uint32_t reserved_cbc;
-    uint32_t reserved_cc0;
-    uint32_t reserved_cc4;
-    uint32_t reserved_cc8;
-    uint32_t reserved_ccc;
-    uint32_t reserved_cd0;
-    uint32_t reserved_cd4;
-    uint32_t reserved_cd8;
-    uint32_t reserved_cdc;
-    uint32_t reserved_ce0;
-    uint32_t reserved_ce4;
-    uint32_t reserved_ce8;
-    uint32_t reserved_cec;
-    uint32_t reserved_cf0;
-    uint32_t reserved_cf4;
-    uint32_t reserved_cf8;
-    uint32_t reserved_cfc;
-    uint32_t reserved_d00;
-    uint32_t reserved_d04;
-    uint32_t reserved_d08;
-    uint32_t reserved_d0c;
-    uint32_t reserved_d10;
-    uint32_t reserved_d14;
-    uint32_t reserved_d18;
-    uint32_t reserved_d1c;
-    uint32_t reserved_d20;
-    uint32_t reserved_d24;
-    uint32_t reserved_d28;
-    uint32_t reserved_d2c;
-    uint32_t reserved_d30;
-    uint32_t reserved_d34;
-    uint32_t reserved_d38;
-    uint32_t reserved_d3c;
-    uint32_t reserved_d40;
-    uint32_t reserved_d44;
-    uint32_t reserved_d48;
-    uint32_t reserved_d4c;
-    uint32_t reserved_d50;
-    uint32_t reserved_d54;
-    uint32_t reserved_d58;
-    uint32_t reserved_d5c;
-    uint32_t reserved_d60;
-    uint32_t reserved_d64;
-    uint32_t reserved_d68;
-    uint32_t reserved_d6c;
-    uint32_t reserved_d70;
-    uint32_t reserved_d74;
-    uint32_t reserved_d78;
-    uint32_t reserved_d7c;
-    uint32_t reserved_d80;
-    uint32_t reserved_d84;
-    uint32_t reserved_d88;
-    uint32_t reserved_d8c;
-    uint32_t reserved_d90;
-    uint32_t reserved_d94;
-    uint32_t reserved_d98;
-    uint32_t reserved_d9c;
-    uint32_t reserved_da0;
-    uint32_t reserved_da4;
-    uint32_t reserved_da8;
-    uint32_t reserved_dac;
-    uint32_t reserved_db0;
-    uint32_t reserved_db4;
-    uint32_t reserved_db8;
-    uint32_t reserved_dbc;
-    uint32_t reserved_dc0;
-    uint32_t reserved_dc4;
-    uint32_t reserved_dc8;
-    uint32_t reserved_dcc;
-    uint32_t reserved_dd0;
-    uint32_t reserved_dd4;
-    uint32_t reserved_dd8;
-    uint32_t reserved_ddc;
-    uint32_t reserved_de0;
-    uint32_t reserved_de4;
-    uint32_t reserved_de8;
-    uint32_t reserved_dec;
-    uint32_t reserved_df0;
-    uint32_t reserved_df4;
-    uint32_t reserved_df8;
-    uint32_t reserved_dfc;
-    uint32_t reserved_e00;
-    uint32_t reserved_e04;
-    uint32_t reserved_e08;
-    uint32_t reserved_e0c;
-    uint32_t reserved_e10;
-    uint32_t reserved_e14;
-    uint32_t reserved_e18;
-    uint32_t reserved_e1c;
-    uint32_t reserved_e20;
-    uint32_t reserved_e24;
-    uint32_t reserved_e28;
-    uint32_t reserved_e2c;
-    uint32_t reserved_e30;
-    uint32_t reserved_e34;
-    uint32_t reserved_e38;
-    uint32_t reserved_e3c;
-    uint32_t reserved_e40;
-    uint32_t reserved_e44;
-    uint32_t reserved_e48;
-    uint32_t reserved_e4c;
-    uint32_t reserved_e50;
-    uint32_t reserved_e54;
-    uint32_t reserved_e58;
-    uint32_t reserved_e5c;
-    uint32_t reserved_e60;
-    uint32_t reserved_e64;
-    uint32_t reserved_e68;
-    uint32_t reserved_e6c;
-    uint32_t reserved_e70;
-    uint32_t reserved_e74;
-    uint32_t reserved_e78;
-    uint32_t reserved_e7c;
-    uint32_t reserved_e80;
-    uint32_t reserved_e84;
-    uint32_t reserved_e88;
-    uint32_t reserved_e8c;
-    uint32_t reserved_e90;
-    uint32_t reserved_e94;
-    uint32_t reserved_e98;
-    uint32_t reserved_e9c;
-    uint32_t reserved_ea0;
-    uint32_t reserved_ea4;
-    uint32_t reserved_ea8;
-    uint32_t reserved_eac;
-    uint32_t reserved_eb0;
-    uint32_t reserved_eb4;
-    uint32_t reserved_eb8;
-    uint32_t reserved_ebc;
-    uint32_t reserved_ec0;
-    uint32_t reserved_ec4;
-    uint32_t reserved_ec8;
-    uint32_t reserved_ecc;
-    uint32_t reserved_ed0;
-    uint32_t reserved_ed4;
-    uint32_t reserved_ed8;
-    uint32_t reserved_edc;
-    uint32_t reserved_ee0;
-    uint32_t reserved_ee4;
-    uint32_t reserved_ee8;
-    uint32_t reserved_eec;
-    uint32_t reserved_ef0;
-    uint32_t reserved_ef4;
-    uint32_t reserved_ef8;
-    uint32_t reserved_efc;
-    uint32_t reserved_f00;
-    uint32_t reserved_f04;
-    uint32_t reserved_f08;
-    uint32_t reserved_f0c;
-    uint32_t reserved_f10;
-    uint32_t reserved_f14;
-    uint32_t reserved_f18;
-    uint32_t reserved_f1c;
-    uint32_t reserved_f20;
-    uint32_t reserved_f24;
-    uint32_t reserved_f28;
-    uint32_t reserved_f2c;
-    uint32_t reserved_f30;
-    uint32_t reserved_f34;
-    uint32_t reserved_f38;
-    uint32_t reserved_f3c;
-    uint32_t reserved_f40;
-    uint32_t reserved_f44;
-    uint32_t reserved_f48;
-    uint32_t reserved_f4c;
-    uint32_t reserved_f50;
-    uint32_t reserved_f54;
-    uint32_t reserved_f58;
-    uint32_t reserved_f5c;
-    uint32_t reserved_f60;
-    uint32_t reserved_f64;
-    uint32_t reserved_f68;
-    uint32_t reserved_f6c;
-    uint32_t reserved_f70;
-    uint32_t reserved_f74;
-    uint32_t reserved_f78;
-    uint32_t reserved_f7c;
-    uint32_t reserved_f80;
-    uint32_t reserved_f84;
-    uint32_t reserved_f88;
-    uint32_t reserved_f8c;
-    uint32_t reserved_f90;
-    uint32_t reserved_f94;
-    uint32_t reserved_f98;
-    uint32_t reserved_f9c;
-    uint32_t reserved_fa0;
-    uint32_t reserved_fa4;
-    uint32_t reserved_fa8;
-    uint32_t reserved_fac;
-    uint32_t reserved_fb0;
-    uint32_t reserved_fb4;
-    uint32_t reserved_fb8;
-    uint32_t reserved_fbc;
-    uint32_t reserved_fc0;
-    uint32_t reserved_fc4;
-    uint32_t reserved_fc8;
-    uint32_t reserved_fcc;
-    uint32_t reserved_fd0;
-    uint32_t reserved_fd4;
-    uint32_t reserved_fd8;
-    uint32_t reserved_fdc;
-    uint32_t reserved_fe0;
-    uint32_t reserved_fe4;
-    uint32_t reserved_fe8;
-    uint32_t reserved_fec;
-    uint32_t reserved_ff0;
-    uint32_t reserved_ff4;
-    uint32_t reserved_ff8;
-    union {
-        struct {
-            uint32_t date                          :    28;
-            uint32_t reserved28                    :    4;
-        };
-        uint32_t val;
-    } date;
-} system_dev_t;
-extern system_dev_t SYSTEM;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_SYSTEM_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/systimer_reg.h b/components/soc/esp32s3/include/soc/systimer_reg.h
deleted file mode 100644
index 869012065b0..00000000000
--- a/components/soc/esp32s3/include/soc/systimer_reg.h
+++ /dev/null
@@ -1,639 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SYSTIMER_CONF_REG register
- *  Configure system timer clock
- */
-#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
-/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
- *  systimer clock force on
- */
-#define SYSTIMER_SYSTIMER_CLK_FO    (BIT(0))
-#define SYSTIMER_SYSTIMER_CLK_FO_M  (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
-#define SYSTIMER_SYSTIMER_CLK_FO_V  0x00000001
-#define SYSTIMER_SYSTIMER_CLK_FO_S  0
-/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
- *  target2 work enable
- */
-#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
-#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
-#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001
-#define SYSTIMER_TARGET2_WORK_EN_S  22
-/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
- *  target1 work enable
- */
-#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
-#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
-#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001
-#define SYSTIMER_TARGET1_WORK_EN_S  23
-/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
- *  target0 work enable
- */
-#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
-#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
-#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001
-#define SYSTIMER_TARGET0_WORK_EN_S  24
-/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
- *  If timer unit1 is stalled when core1 stalled
- */
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
-/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
- *  If timer unit1 is stalled when core0 stalled
- */
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
-/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
- *  If timer unit0 is stalled when core1 stalled
- */
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
-/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
- *  If timer unit0 is stalled when core0 stalled
- */
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
-/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
- *  timer unit1 work enable
- */
-#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
-/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
- *  timer unit0 work enable
- */
-#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
-/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
- *  register file clk gating
- */
-#define SYSTIMER_CLK_EN    (BIT(31))
-#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
-#define SYSTIMER_CLK_EN_V  0x00000001
-#define SYSTIMER_CLK_EN_S  31
-
-/** SYSTIMER_UNIT0_OP_REG register
- *  system timer unit0 value update register
- */
-#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
-/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  timer value is sync and valid
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
-/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
- *  update timer_unit0
- */
-#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
-#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
-
-/** SYSTIMER_UNIT1_OP_REG register
- *  system timer unit1 value update register
- */
-#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
-/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
- *  timer value is sync and valid
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
-/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
- *  update timer unit1
- */
-#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
-#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
-#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
-
-/** SYSTIMER_UNIT0_LOAD_HI_REG register
- *  system timer unit0 value high load register
- */
-#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
-/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit0 load high 20 bits
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFF
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
-
-/** SYSTIMER_UNIT0_LOAD_LO_REG register
- *  system timer unit0 value low load register
- */
-#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
-/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit0 load low 32 bits
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
-
-/** SYSTIMER_UNIT1_LOAD_HI_REG register
- *  system timer unit1 value high load register
- */
-#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
-/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer unit1 load high 20 bits
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFF
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
-
-/** SYSTIMER_UNIT1_LOAD_LO_REG register
- *  system timer unit1 value low load register
- */
-#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
-/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer unit1 load low 32 bits
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
-
-/** SYSTIMER_TARGET0_HI_REG register
- *  system timer comp0 value high register
- */
-#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
-/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget0 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFF
-#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
-#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_TARGET0_HI_S  0
-
-/** SYSTIMER_TARGET0_LO_REG register
- *  system timer comp0 value low register
- */
-#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
-/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget0 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
-#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET0_LO_S  0
-
-/** SYSTIMER_TARGET1_HI_REG register
- *  system timer comp1 value high register
- */
-#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
-/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget1 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFF
-#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
-#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_TARGET1_HI_S  0
-
-/** SYSTIMER_TARGET1_LO_REG register
- *  system timer comp1 value low register
- */
-#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
-/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget1 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
-#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET1_LO_S  0
-
-/** SYSTIMER_TARGET2_HI_REG register
- *  system timer comp2 value high register
- */
-#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
-/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
- *  timer taget2 high 20 bits
- */
-#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFF
-#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
-#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_TARGET2_HI_S  0
-
-/** SYSTIMER_TARGET2_LO_REG register
- *  system timer comp2 value low register
- */
-#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
-/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
- *  timer taget2 low 32 bits
- */
-#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
-#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_TARGET2_LO_S  0
-
-/** SYSTIMER_TARGET0_CONF_REG register
- *  system timer comp0 target mode register
- */
-#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
-/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target0 period
- */
-#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFF
-#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
-#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFF
-#define SYSTIMER_TARGET0_PERIOD_S  0
-/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target0 to period mode
- */
-#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
-#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001
-#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001
-#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_TARGET1_CONF_REG register
- *  system timer comp1 target mode register
- */
-#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
-/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target1 period
- */
-#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFF
-#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
-#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFF
-#define SYSTIMER_TARGET1_PERIOD_S  0
-/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target1 to period mode
- */
-#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
-#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001
-#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001
-#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_TARGET2_CONF_REG register
- *  system timer comp2 target mode register
- */
-#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
-/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
- *  target2 period
- */
-#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFF
-#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
-#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFF
-#define SYSTIMER_TARGET2_PERIOD_S  0
-/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
- *  Set target2 to period mode
- */
-#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
-#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
-#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001
-#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
-/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
- *  select which unit to compare
- */
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001
-#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
-
-/** SYSTIMER_UNIT0_VALUE_HI_REG register
- *  system timer unit0 value high register
- */
-#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
-/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 20bits
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFF
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
-
-/** SYSTIMER_UNIT0_VALUE_LO_REG register
- *  system timer unit0 value low register
- */
-#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
-/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bits
- */
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
-
-/** SYSTIMER_UNIT1_VALUE_HI_REG register
- *  system timer unit1 value high register
- */
-#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
-/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
- *  timer read value high 20bits
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFF
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFF
-#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
-
-/** SYSTIMER_UNIT1_VALUE_LO_REG register
- *  system timer unit1 value low register
- */
-#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
-/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
- *  timer read value low 32bits
- */
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFF
-#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
-
-/** SYSTIMER_COMP0_LOAD_REG register
- *  system timer comp0 conf sync register
- */
-#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
-/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp0 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
-#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_COMP0_LOAD_S  0
-
-/** SYSTIMER_COMP1_LOAD_REG register
- *  system timer comp1 conf sync register
- */
-#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
-/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp1 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
-#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_COMP1_LOAD_S  0
-
-/** SYSTIMER_COMP2_LOAD_REG register
- *  system timer comp2 conf sync register
- */
-#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
-/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
- *  timer comp2 sync enable signal
- */
-#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
-#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_COMP2_LOAD_S  0
-
-/** SYSTIMER_UNIT0_LOAD_REG register
- *  system timer unit0 conf sync register
- */
-#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
-/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit0 sync enable signal
- */
-#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
-#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
-
-/** SYSTIMER_UNIT1_LOAD_REG register
- *  system timer unit1 conf sync register
- */
-#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
-/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
- *  timer unit1 sync enable signal
- */
-#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
-#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
-#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001
-#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
-
-/** SYSTIMER_INT_ENA_REG register
- *  systimer interrupt enable register
- */
-#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
-/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  interupt0 enable
- */
-#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
-#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
-#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001
-#define SYSTIMER_TARGET0_INT_ENA_S  0
-/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  interupt1 enable
- */
-#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
-#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
-#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001
-#define SYSTIMER_TARGET1_INT_ENA_S  1
-/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  interupt2 enable
- */
-#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
-#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
-#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001
-#define SYSTIMER_TARGET2_INT_ENA_S  2
-
-/** SYSTIMER_INT_RAW_REG register
- *  systimer interrupt raw register
- */
-#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
-/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  interupt0 raw
- */
-#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
-#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
-#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001
-#define SYSTIMER_TARGET0_INT_RAW_S  0
-/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
- *  interupt1 raw
- */
-#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
-#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
-#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001
-#define SYSTIMER_TARGET1_INT_RAW_S  1
-/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  interupt2 raw
- */
-#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
-#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
-#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001
-#define SYSTIMER_TARGET2_INT_RAW_S  2
-
-/** SYSTIMER_INT_CLR_REG register
- *  systimer interrupt clear register
- */
-#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
-/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
- *  interupt0 clear
- */
-#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
-#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
-#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001
-#define SYSTIMER_TARGET0_INT_CLR_S  0
-/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
- *  interupt1 clear
- */
-#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
-#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
-#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001
-#define SYSTIMER_TARGET1_INT_CLR_S  1
-/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
- *  interupt2 clear
- */
-#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
-#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
-#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001
-#define SYSTIMER_TARGET2_INT_CLR_S  2
-
-/** SYSTIMER_INT_ST_REG register
- *  systimer interrupt status register
- */
-#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
-/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
- *  interupt0 status
- */
-#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
-#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
-#define SYSTIMER_TARGET0_INT_ST_V  0x00000001
-#define SYSTIMER_TARGET0_INT_ST_S  0
-/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
- *  interupt1 status
- */
-#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
-#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
-#define SYSTIMER_TARGET1_INT_ST_V  0x00000001
-#define SYSTIMER_TARGET1_INT_ST_S  1
-/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
- *  interupt2 status
- */
-#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
-#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
-#define SYSTIMER_TARGET2_INT_ST_V  0x00000001
-#define SYSTIMER_TARGET2_INT_ST_S  2
-
-/** SYSTIMER_REAL_TARGET0_LO_REG register
- *  system timer comp0 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
-/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET0_LO_RO    0xFFFFFFFF
-#define SYSTIMER_TARGET0_LO_RO_M  (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
-#define SYSTIMER_TARGET0_LO_RO_V  0xFFFFFFFF
-#define SYSTIMER_TARGET0_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET0_HI_REG register
- *  system timer comp0 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
-/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET0_HI_RO    0x000FFFFF
-#define SYSTIMER_TARGET0_HI_RO_M  (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
-#define SYSTIMER_TARGET0_HI_RO_V  0x000FFFFF
-#define SYSTIMER_TARGET0_HI_RO_S  0
-
-/** SYSTIMER_REAL_TARGET1_LO_REG register
- *  system timer comp1 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
-/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET1_LO_RO    0xFFFFFFFF
-#define SYSTIMER_TARGET1_LO_RO_M  (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
-#define SYSTIMER_TARGET1_LO_RO_V  0xFFFFFFFF
-#define SYSTIMER_TARGET1_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET1_HI_REG register
- *  system timer comp1 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
-/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET1_HI_RO    0x000FFFFF
-#define SYSTIMER_TARGET1_HI_RO_M  (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
-#define SYSTIMER_TARGET1_HI_RO_V  0x000FFFFF
-#define SYSTIMER_TARGET1_HI_RO_S  0
-
-/** SYSTIMER_REAL_TARGET2_LO_REG register
- *  system timer comp2 actual target value low register
- */
-#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
-/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
- *  actual target value value low 32bits
- */
-#define SYSTIMER_TARGET2_LO_RO    0xFFFFFFFF
-#define SYSTIMER_TARGET2_LO_RO_M  (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
-#define SYSTIMER_TARGET2_LO_RO_V  0xFFFFFFFF
-#define SYSTIMER_TARGET2_LO_RO_S  0
-
-/** SYSTIMER_REAL_TARGET2_HI_REG register
- *  system timer comp2 actual target value high register
- */
-#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
-/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
- *  actual target value value high 20bits
- */
-#define SYSTIMER_TARGET2_HI_RO    0x000FFFFF
-#define SYSTIMER_TARGET2_HI_RO_M  (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
-#define SYSTIMER_TARGET2_HI_RO_V  0x000FFFFF
-#define SYSTIMER_TARGET2_HI_RO_S  0
-
-/** SYSTIMER_DATE_REG register
- *  system timer version control register
- */
-#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
-/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33628753;
- *  systimer register version
- */
-#define SYSTIMER_DATE    0xFFFFFFFF
-#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
-#define SYSTIMER_DATE_V  0xFFFFFFFF
-#define SYSTIMER_DATE_S  0
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/systimer_struct.h b/components/soc/esp32s3/include/soc/systimer_struct.h
deleted file mode 100644
index a28ef359f16..00000000000
--- a/components/soc/esp32s3/include/soc/systimer_struct.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** SYSTEM TIMER CLK CONTROL REGISTER */
-/** Type of conf register
- *  Configure system timer clock
- */
-typedef union {
-    struct {
-        /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
-         *  systimer clock force on
-         */
-        uint32_t systimer_clk_fo: 1;
-        uint32_t reserved_1: 21;
-        /** target2_work_en : R/W; bitpos: [22]; default: 0;
-         *  target2 work enable
-         */
-        uint32_t target2_work_en: 1;
-        /** target1_work_en : R/W; bitpos: [23]; default: 0;
-         *  target1 work enable
-         */
-        uint32_t target1_work_en: 1;
-        /** target0_work_en : R/W; bitpos: [24]; default: 0;
-         *  target0 work enable
-         */
-        uint32_t target0_work_en: 1;
-        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
-         *  If timer unit1 is stalled when core1 stalled
-         */
-        uint32_t timer_unit1_core1_stall_en: 1;
-        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
-         *  If timer unit1 is stalled when core0 stalled
-         */
-        uint32_t timer_unit1_core0_stall_en: 1;
-        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
-         *  If timer unit0 is stalled when core1 stalled
-         */
-        uint32_t timer_unit0_core1_stall_en: 1;
-        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
-         *  If timer unit0 is stalled when core0 stalled
-         */
-        uint32_t timer_unit0_core0_stall_en: 1;
-        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
-         *  timer unit1 work enable
-         */
-        uint32_t timer_unit1_work_en: 1;
-        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
-         *  timer unit0 work enable
-         */
-        uint32_t timer_unit0_work_en: 1;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  register file clk gating
-         */
-        uint32_t clk_en: 1;
-    };
-    uint32_t val;
-} systimer_conf_reg_t;
-
-
-/** Type of unit_op register
- *  SYSTIMER_UNIT_OP.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0: 29;
-        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
-         *  reg_timer_unit0_value_valid
-         */
-        uint32_t timer_unit_value_valid: 1;
-        /** timer_unit_update : WT; bitpos: [30]; default: 0;
-         *  update timer_unit0
-         */
-        uint32_t timer_unit_update: 1;
-        uint32_t reserved_32: 1;
-    };
-    uint32_t val;
-} systimer_unit_op_reg_t;
-
-/** Type of unit_load register
- *  SYSTIMER_UNIT_LOAD
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
-             *  timer unit load high 32 bit
-             */
-            uint32_t timer_unit_load_hi: 20;
-            uint32_t reserved_20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
-             *  timer unit load low 32 bit
-             */
-            uint32_t timer_unit_load_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_unit_load_val_reg_t;
-
-
-/** Type of target register
- *  SYSTIMER_TARGET.
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
-             *  timer target high 32 bit
-             */
-            uint32_t timer_target_hi: 20;
-            uint32_t reserved_20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
-             *  timer target low 32 bit
-             */
-            uint32_t timer_target_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_target_val_reg_t;
-
-
-/** Type of target_conf register
- *  SYSTIMER_TARGET_CONF.
- */
-typedef union {
-    struct {
-        /** target_period : R/W; bitpos: [25:0]; default: 0;
-         *  target period
-         */
-        uint32_t target_period: 26;
-        uint32_t reserved_26: 4;
-        /** target_period_mode : R/W; bitpos: [30]; default: 0;
-         *  Set target to period mode
-         */
-        uint32_t target_period_mode: 1;
-        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
-         *  select which unit to compare
-         */
-        uint32_t target_timer_unit_sel: 1;
-    };
-    uint32_t val;
-} systimer_target_conf_reg_t;
-
-
-/** Type of unit_value_hi register
- *  SYSTIMER_UNIT_VALUE_HI.
- */
-typedef struct {
-    union {
-        struct {
-            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
-             *  timer read value high 20bit
-             */
-            uint32_t timer_unit_value_hi: 20;
-            uint32_t reserved_20: 12;
-        };
-        uint32_t val;
-    } hi;
-    union {
-        struct {
-            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
-             *  timer read value low 32bit
-             */
-            uint32_t timer_unit_value_lo: 32;
-        };
-        uint32_t val;
-    } lo;
-} systimer_unit_value_reg_t;
-
-
-/** Type of comp_load register
- *  SYSTIMER_COMP_LOAD.
- */
-typedef union {
-    struct {
-        /** timer_comp_load : WT; bitpos: [0]; default: 0;
-         *  timer comp load value
-         */
-        uint32_t timer_comp_load: 1;
-        uint32_t reserved_1: 31;
-    };
-    uint32_t val;
-} systimer_comp_load_reg_t;
-
-
-/** Type of unit_load register
- *  SYSTIMER_UNIT_LOAD.
- */
-typedef union {
-    struct {
-        /** timer_unit_load : WT; bitpos: [0]; default: 0;
-         *  timer unit load value
-         */
-        uint32_t timer_unit_load: 1;
-        uint32_t reserved_1: 31;
-    };
-    uint32_t val;
-} systimer_unit_load_reg_t;
-
-
-/** SYSTEM TIMER INTERRUPT REGISTER */
-/** Type of int_ena register
- *  systimer interrupt enable register
- */
-typedef union {
-    struct {
-        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
-         *  interupt0 enable
-         */
-        uint32_t target0_int_ena: 1;
-        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
-         *  interupt1 enable
-         */
-        uint32_t target1_int_ena: 1;
-        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
-         *  interupt2 enable
-         */
-        uint32_t target2_int_ena: 1;
-        uint32_t reserved_3: 29;
-    };
-    uint32_t val;
-} systimer_int_ena_reg_t;
-
-/** Type of int_raw register
- *  systimer interrupt raw register
- */
-typedef union {
-    struct {
-        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  interupt0 raw
-         */
-        uint32_t target0_int_raw: 1;
-        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
-         *  interupt1 raw
-         */
-        uint32_t target1_int_raw: 1;
-        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  interupt2 raw
-         */
-        uint32_t target2_int_raw: 1;
-        uint32_t reserved_3: 29;
-    };
-    uint32_t val;
-} systimer_int_raw_reg_t;
-
-/** Type of int_clr register
- *  systimer interrupt clear register
- */
-typedef union {
-    struct {
-        /** target0_int_clr : WT; bitpos: [0]; default: 0;
-         *  interupt0 clear
-         */
-        uint32_t target0_int_clr: 1;
-        /** target1_int_clr : WT; bitpos: [1]; default: 0;
-         *  interupt1 clear
-         */
-        uint32_t target1_int_clr: 1;
-        /** target2_int_clr : WT; bitpos: [2]; default: 0;
-         *  interupt2 clear
-         */
-        uint32_t target2_int_clr: 1;
-        uint32_t reserved_3: 29;
-    };
-    uint32_t val;
-} systimer_int_clr_reg_t;
-
-/** Type of int_st register
- *  systimer interrupt status register
- */
-typedef union {
-    struct {
-        /** target0_int_st : RO; bitpos: [0]; default: 0;
-         *  interupt0 status
-         */
-        uint32_t target0_int_st: 1;
-        /** target1_int_st : RO; bitpos: [1]; default: 0;
-         *  interupt1 status
-         */
-        uint32_t target1_int_st: 1;
-        /** target2_int_st : RO; bitpos: [2]; default: 0;
-         *  interupt2 status
-         */
-        uint32_t target2_int_st: 1;
-        uint32_t reserved_3: 29;
-    };
-    uint32_t val;
-} systimer_int_st_reg_t;
-
-
-/** SYSTEM TIMER COMP STATUS REGISTER
- *  systimer comp actual target value low register
- */
-typedef struct {
-    union {
-        struct {
-            /** target_lo_ro : RO; bitpos: [31:0]; default: 0;
-             *  actual target value value low 32bits
-             */
-            uint32_t target_lo_ro: 32;
-        };
-        uint32_t val;
-    } lo;
-    union {
-        struct {
-            /** target_hi_ro : RO; bitpos: [19:0]; default: 0;
-             *  actual target value value high 20bits
-             */
-            uint32_t target_hi_ro: 20;
-            uint32_t reserved_20: 12;
-        };
-        uint32_t val;
-    } hi;
-} systimer_real_target_val_reg_t;
-
-
-/** VERSION REGISTER */
-/** Type of date register
- *  system timer version control register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 33628753;
-         *  systimer register version
-         */
-        uint32_t date: 32;
-    };
-    uint32_t val;
-} systimer_date_reg_t;
-
-
-typedef struct systimer_dev_t {
-    volatile systimer_conf_reg_t conf;
-    volatile systimer_unit_op_reg_t unit_op[2];
-    volatile systimer_unit_load_val_reg_t unit_load_val[2];
-    volatile systimer_target_val_reg_t target_val[3];
-    volatile systimer_target_conf_reg_t target_conf[3];
-    volatile systimer_unit_value_reg_t unit_val[2];
-    volatile systimer_comp_load_reg_t comp_load[3];
-    volatile systimer_unit_load_reg_t unit_load[2];
-    volatile systimer_int_ena_reg_t int_ena;
-    volatile systimer_int_raw_reg_t int_raw;
-    volatile systimer_int_clr_reg_t int_clr;
-    volatile systimer_int_st_reg_t int_st;
-    volatile systimer_real_target_val_reg_t real_target_val[3];
-    uint32_t reserved_08c;
-    uint32_t reserved_090;
-    uint32_t reserved_094;
-    uint32_t reserved_098;
-    uint32_t reserved_09c;
-    uint32_t reserved_0a0;
-    uint32_t reserved_0a4;
-    uint32_t reserved_0a8;
-    uint32_t reserved_0ac;
-    uint32_t reserved_0b0;
-    uint32_t reserved_0b4;
-    uint32_t reserved_0b8;
-    uint32_t reserved_0bc;
-    uint32_t reserved_0c0;
-    uint32_t reserved_0c4;
-    uint32_t reserved_0c8;
-    uint32_t reserved_0cc;
-    uint32_t reserved_0d0;
-    uint32_t reserved_0d4;
-    uint32_t reserved_0d8;
-    uint32_t reserved_0dc;
-    uint32_t reserved_0e0;
-    uint32_t reserved_0e4;
-    uint32_t reserved_0e8;
-    uint32_t reserved_0ec;
-    uint32_t reserved_0f0;
-    uint32_t reserved_0f4;
-    uint32_t reserved_0f8;
-    volatile systimer_date_reg_t date;
-} systimer_dev_t;
-
-extern systimer_dev_t SYSTIMER;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/uart_reg.h b/components/soc/esp32s3/include/soc/uart_reg.h
deleted file mode 100644
index 73c2d80b9d8..00000000000
--- a/components/soc/esp32s3/include/soc/uart_reg.h
+++ /dev/null
@@ -1,1532 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#include "soc/soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** UART_FIFO_REG register
- *  FIFO data register
- */
-#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
-/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
- *  UART(i) accesses FIFO via this register.
- */
-#define UART_RXFIFO_RD_BYTE    0x000000FFU
-#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
-#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
-#define UART_RXFIFO_RD_BYTE_S  0
-
-/** UART_INT_RAW_REG register
- *  Raw interrupt status
- */
-#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
-/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  what rxfifo_full_thrhd specifies.
- */
-#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
-#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
-#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_RAW_S  0
-/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
- *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
- *  less than what txfifo_empty_thrhd specifies .
- */
-#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
-#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_RAW_S  1
-/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error in
- *  the data.
- */
-#define UART_PARITY_ERR_INT_RAW    (BIT(2))
-#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
-#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_PARITY_ERR_INT_RAW_S  2
-/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  .
- */
-#define UART_FRM_ERR_INT_RAW    (BIT(3))
-#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
-#define UART_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_FRM_ERR_INT_RAW_S  3
-/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives more data than
- *  the FIFO can store.
- */
-#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
-#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
-#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_RAW_S  4
-/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  DSRn signal.
- */
-#define UART_DSR_CHG_INT_RAW    (BIT(5))
-#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
-#define UART_DSR_CHG_INT_RAW_V  0x00000001U
-#define UART_DSR_CHG_INT_RAW_S  5
-/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the edge change of
- *  CTSn signal.
- */
-#define UART_CTS_CHG_INT_RAW    (BIT(6))
-#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
-#define UART_CTS_CHG_INT_RAW_V  0x00000001U
-#define UART_CTS_CHG_INT_RAW_S  6
-/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
- *  bit.
- */
-#define UART_BRK_DET_INT_RAW    (BIT(7))
-#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
-#define UART_BRK_DET_INT_RAW_V  0x00000001U
-#define UART_BRK_DET_INT_RAW_S  7
-/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
- *  This interrupt raw bit turns to high level when receiver takes more time than
- *  rx_tout_thrhd to receive a byte.
- */
-#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
-#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_RAW_S  8
-/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
- *  This interrupt raw bit turns to high level when receiver recevies Xon char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XON_INT_RAW    (BIT(9))
-#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
-#define UART_SW_XON_INT_RAW_V  0x00000001U
-#define UART_SW_XON_INT_RAW_S  9
-/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
- *  This interrupt raw bit turns to high level when receiver receives Xoff char when
- *  uart_sw_flow_con_en is set to 1.
- */
-#define UART_SW_XOFF_INT_RAW    (BIT(10))
-#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
-#define UART_SW_XOFF_INT_RAW_V  0x00000001U
-#define UART_SW_XOFF_INT_RAW_S  10
-/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a glitch in the
- *  middle of a start bit.
- */
-#define UART_GLITCH_DET_INT_RAW    (BIT(11))
-#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
-#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
-#define UART_GLITCH_DET_INT_RAW_S  11
-/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter completes  sending
- *  NULL characters, after all data in Tx-FIFO are sent.
- */
-#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
-#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
-#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_RAW_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has kept the shortest
- *  duration after sending the  last data.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
-/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
- *  This interrupt raw bit turns to high level when transmitter has send out all data
- *  in FIFO.
- */
-#define UART_TX_DONE_INT_RAW    (BIT(14))
-#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
-#define UART_TX_DONE_INT_RAW_V  0x00000001U
-#define UART_TX_DONE_INT_RAW_S  14
-/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a parity error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
-#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_RAW_S  15
-/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects a data frame error
- *  from the echo of transmitter in rs485 mode.
- */
-#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
-#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_RAW_S  16
-/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
- *  This interrupt raw bit turns to high level when detects a clash between transmitter
- *  and receiver in rs485 mode.
- */
-#define UART_RS485_CLASH_INT_RAW    (BIT(17))
-#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
-#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
-#define UART_RS485_CLASH_INT_RAW_S  17
-/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
- *  This interrupt raw bit turns to high level when receiver detects the configured
- *  at_cmd char.
- */
-#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
-#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
-/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
- *  This interrupt raw bit turns to high level when input rxd edge changes more times
- *  than what reg_active_threshold specifies in light sleeping mode.
- */
-#define UART_WAKEUP_INT_RAW    (BIT(19))
-#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
-#define UART_WAKEUP_INT_RAW_V  0x00000001U
-#define UART_WAKEUP_INT_RAW_S  19
-
-/** UART_INT_ST_REG register
- *  Masked interrupt status
- */
-#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
-/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
- *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
- */
-#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
-#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ST_S  0
-/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
- *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
- *  to 1.
- */
-#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
-#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ST_S  1
-/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
- *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
- */
-#define UART_PARITY_ERR_INT_ST    (BIT(2))
-#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
-#define UART_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_PARITY_ERR_INT_ST_S  2
-/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
- *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
- */
-#define UART_FRM_ERR_INT_ST    (BIT(3))
-#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
-#define UART_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_FRM_ERR_INT_ST_S  3
-/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
- *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
- */
-#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
-#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ST_S  4
-/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
- *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
- */
-#define UART_DSR_CHG_INT_ST    (BIT(5))
-#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
-#define UART_DSR_CHG_INT_ST_V  0x00000001U
-#define UART_DSR_CHG_INT_ST_S  5
-/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
- *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
- */
-#define UART_CTS_CHG_INT_ST    (BIT(6))
-#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
-#define UART_CTS_CHG_INT_ST_V  0x00000001U
-#define UART_CTS_CHG_INT_ST_S  6
-/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
- *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
- */
-#define UART_BRK_DET_INT_ST    (BIT(7))
-#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
-#define UART_BRK_DET_INT_ST_V  0x00000001U
-#define UART_BRK_DET_INT_ST_S  7
-/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
- *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
- */
-#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
-#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ST_S  8
-/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
- *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
- */
-#define UART_SW_XON_INT_ST    (BIT(9))
-#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
-#define UART_SW_XON_INT_ST_V  0x00000001U
-#define UART_SW_XON_INT_ST_S  9
-/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
- *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
- */
-#define UART_SW_XOFF_INT_ST    (BIT(10))
-#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
-#define UART_SW_XOFF_INT_ST_V  0x00000001U
-#define UART_SW_XOFF_INT_ST_S  10
-/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
- *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
- */
-#define UART_GLITCH_DET_INT_ST    (BIT(11))
-#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
-#define UART_GLITCH_DET_INT_ST_V  0x00000001U
-#define UART_GLITCH_DET_INT_ST_S  11
-/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
- *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
- */
-#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
-#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ST_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
- *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
- *  is set to 1.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
-/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
- *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
- */
-#define UART_TX_DONE_INT_ST    (BIT(14))
-#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
-#define UART_TX_DONE_INT_ST_V  0x00000001U
-#define UART_TX_DONE_INT_ST_S  14
-/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
- *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
- *  set to 1.
- */
-#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
-#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ST_S  15
-/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
- *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
- *  to 1.
- */
-#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
-#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ST_S  16
-/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
- *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
- */
-#define UART_RS485_CLASH_INT_ST    (BIT(17))
-#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
-#define UART_RS485_CLASH_INT_ST_V  0x00000001U
-#define UART_RS485_CLASH_INT_ST_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
- *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
- *  to 1.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
-#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
-/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
- *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
- */
-#define UART_WAKEUP_INT_ST    (BIT(19))
-#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
-#define UART_WAKEUP_INT_ST_V  0x00000001U
-#define UART_WAKEUP_INT_ST_S  19
-
-/** UART_INT_ENA_REG register
- *  Interrupt enable bits
- */
-#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
-/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
- *  This is the enable bit for rxfifo_full_int_st register.
- */
-#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
-#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
-#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_ENA_S  0
-/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
- *  This is the enable bit for txfifo_empty_int_st register.
- */
-#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
-#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_ENA_S  1
-/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
- *  This is the enable bit for parity_err_int_st register.
- */
-#define UART_PARITY_ERR_INT_ENA    (BIT(2))
-#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
-#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_PARITY_ERR_INT_ENA_S  2
-/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
- *  This is the enable bit for frm_err_int_st register.
- */
-#define UART_FRM_ERR_INT_ENA    (BIT(3))
-#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
-#define UART_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_FRM_ERR_INT_ENA_S  3
-/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
- *  This is the enable bit for rxfifo_ovf_int_st register.
- */
-#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
-#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
-#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_ENA_S  4
-/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
- *  This is the enable bit for dsr_chg_int_st register.
- */
-#define UART_DSR_CHG_INT_ENA    (BIT(5))
-#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
-#define UART_DSR_CHG_INT_ENA_V  0x00000001U
-#define UART_DSR_CHG_INT_ENA_S  5
-/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
- *  This is the enable bit for cts_chg_int_st register.
- */
-#define UART_CTS_CHG_INT_ENA    (BIT(6))
-#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
-#define UART_CTS_CHG_INT_ENA_V  0x00000001U
-#define UART_CTS_CHG_INT_ENA_S  6
-/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
- *  This is the enable bit for brk_det_int_st register.
- */
-#define UART_BRK_DET_INT_ENA    (BIT(7))
-#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
-#define UART_BRK_DET_INT_ENA_V  0x00000001U
-#define UART_BRK_DET_INT_ENA_S  7
-/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
- *  This is the enable bit for rxfifo_tout_int_st register.
- */
-#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
-#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_ENA_S  8
-/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
- *  This is the enable bit for sw_xon_int_st register.
- */
-#define UART_SW_XON_INT_ENA    (BIT(9))
-#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
-#define UART_SW_XON_INT_ENA_V  0x00000001U
-#define UART_SW_XON_INT_ENA_S  9
-/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
- *  This is the enable bit for sw_xoff_int_st register.
- */
-#define UART_SW_XOFF_INT_ENA    (BIT(10))
-#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
-#define UART_SW_XOFF_INT_ENA_V  0x00000001U
-#define UART_SW_XOFF_INT_ENA_S  10
-/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
- *  This is the enable bit for glitch_det_int_st register.
- */
-#define UART_GLITCH_DET_INT_ENA    (BIT(11))
-#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
-#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
-#define UART_GLITCH_DET_INT_ENA_S  11
-/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
- *  This is the enable bit for tx_brk_done_int_st register.
- */
-#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
-#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
-#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_ENA_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
- *  This is the enable bit for tx_brk_idle_done_int_st register.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
-/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
- *  This is the enable bit for tx_done_int_st register.
- */
-#define UART_TX_DONE_INT_ENA    (BIT(14))
-#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
-#define UART_TX_DONE_INT_ENA_V  0x00000001U
-#define UART_TX_DONE_INT_ENA_S  14
-/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
-#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_ENA_S  15
-/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
- *  This is the enable bit for rs485_parity_err_int_st register.
- */
-#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
-#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_ENA_S  16
-/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
- *  This is the enable bit for rs485_clash_int_st register.
- */
-#define UART_RS485_CLASH_INT_ENA    (BIT(17))
-#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
-#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
-#define UART_RS485_CLASH_INT_ENA_S  17
-/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
- *  This is the enable bit for at_cmd_char_det_int_st register.
- */
-#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
-#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
-/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
- *  This is the enable bit for uart_wakeup_int_st register.
- */
-#define UART_WAKEUP_INT_ENA    (BIT(19))
-#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
-#define UART_WAKEUP_INT_ENA_V  0x00000001U
-#define UART_WAKEUP_INT_ENA_S  19
-
-/** UART_INT_CLR_REG register
- *  Interrupt clear bits
- */
-#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
-/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
- *  Set this bit to clear the rxfifo_full_int_raw interrupt.
- */
-#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
-#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
-#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_FULL_INT_CLR_S  0
-/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
- *  Set this bit to clear txfifo_empty_int_raw interrupt.
- */
-#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
-#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
-#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
-#define UART_TXFIFO_EMPTY_INT_CLR_S  1
-/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
- *  Set this bit to clear parity_err_int_raw interrupt.
- */
-#define UART_PARITY_ERR_INT_CLR    (BIT(2))
-#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
-#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_PARITY_ERR_INT_CLR_S  2
-/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
- *  Set this bit to clear frm_err_int_raw interrupt.
- */
-#define UART_FRM_ERR_INT_CLR    (BIT(3))
-#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
-#define UART_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_FRM_ERR_INT_CLR_S  3
-/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
- *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
- */
-#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
-#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
-#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_OVF_INT_CLR_S  4
-/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
- *  Set this bit to clear the dsr_chg_int_raw interrupt.
- */
-#define UART_DSR_CHG_INT_CLR    (BIT(5))
-#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
-#define UART_DSR_CHG_INT_CLR_V  0x00000001U
-#define UART_DSR_CHG_INT_CLR_S  5
-/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
- *  Set this bit to clear the cts_chg_int_raw interrupt.
- */
-#define UART_CTS_CHG_INT_CLR    (BIT(6))
-#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
-#define UART_CTS_CHG_INT_CLR_V  0x00000001U
-#define UART_CTS_CHG_INT_CLR_S  6
-/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
- *  Set this bit to clear the brk_det_int_raw interrupt.
- */
-#define UART_BRK_DET_INT_CLR    (BIT(7))
-#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
-#define UART_BRK_DET_INT_CLR_V  0x00000001U
-#define UART_BRK_DET_INT_CLR_S  7
-/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
- *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
- */
-#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
-#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
-#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
-#define UART_RXFIFO_TOUT_INT_CLR_S  8
-/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
- *  Set this bit to clear the sw_xon_int_raw interrupt.
- */
-#define UART_SW_XON_INT_CLR    (BIT(9))
-#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
-#define UART_SW_XON_INT_CLR_V  0x00000001U
-#define UART_SW_XON_INT_CLR_S  9
-/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
- *  Set this bit to clear the sw_xoff_int_raw interrupt.
- */
-#define UART_SW_XOFF_INT_CLR    (BIT(10))
-#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
-#define UART_SW_XOFF_INT_CLR_V  0x00000001U
-#define UART_SW_XOFF_INT_CLR_S  10
-/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
- *  Set this bit to clear the glitch_det_int_raw interrupt.
- */
-#define UART_GLITCH_DET_INT_CLR    (BIT(11))
-#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
-#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
-#define UART_GLITCH_DET_INT_CLR_S  11
-/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
- *  Set this bit to clear the tx_brk_done_int_raw interrupt..
- */
-#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
-#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
-#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_DONE_INT_CLR_S  12
-/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
- *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
- */
-#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
-/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
- *  Set this bit to clear the tx_done_int_raw interrupt.
- */
-#define UART_TX_DONE_INT_CLR    (BIT(14))
-#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
-#define UART_TX_DONE_INT_CLR_V  0x00000001U
-#define UART_TX_DONE_INT_CLR_S  14
-/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
- *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
- */
-#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
-#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
-#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_PARITY_ERR_INT_CLR_S  15
-/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
- *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
- */
-#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
-#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
-#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
-#define UART_RS485_FRM_ERR_INT_CLR_S  16
-/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
- *  Set this bit to clear the rs485_clash_int_raw interrupt.
- */
-#define UART_RS485_CLASH_INT_CLR    (BIT(17))
-#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
-#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
-#define UART_RS485_CLASH_INT_CLR_S  17
-/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
- *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
- */
-#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
-#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
-#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
-#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
-/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
- *  Set this bit to clear the uart_wakeup_int_raw interrupt.
- */
-#define UART_WAKEUP_INT_CLR    (BIT(19))
-#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
-#define UART_WAKEUP_INT_CLR_V  0x00000001U
-#define UART_WAKEUP_INT_CLR_S  19
-
-/** UART_CLKDIV_REG register
- *  Clock divider configuration
- */
-#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)
-/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
- *  The integral part of the frequency divider factor.
- */
-#define UART_CLKDIV    0x00000FFFU
-#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
-#define UART_CLKDIV_V  0x00000FFFU
-#define UART_CLKDIV_S  0
-/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
- *  The decimal part of the frequency divider factor.
- */
-#define UART_CLKDIV_FRAG    0x0000000FU
-#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
-#define UART_CLKDIV_FRAG_V  0x0000000FU
-#define UART_CLKDIV_FRAG_S  20
-
-/** UART_RX_FILT_REG register
- *  Rx Filter configuration
- */
-#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
-/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
- *  when input pulse width is lower than this value, the pulse is ignored.
- */
-#define UART_GLITCH_FILT    0x000000FFU
-#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
-#define UART_GLITCH_FILT_V  0x000000FFU
-#define UART_GLITCH_FILT_S  0
-/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enable Rx signal filter.
- */
-#define UART_GLITCH_FILT_EN    (BIT(8))
-#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
-#define UART_GLITCH_FILT_EN_V  0x00000001U
-#define UART_GLITCH_FILT_EN_S  8
-
-/** UART_STATUS_REG register
- *  UART status register
- */
-#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
-/** UART_RXFIFO_CNT : RO; bitpos: [9:0]; default: 0;
- *  Stores the byte number of valid data in Rx-FIFO.
- */
-#define UART_RXFIFO_CNT    0x000003FFU
-#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
-#define UART_RXFIFO_CNT_V  0x000003FFU
-#define UART_RXFIFO_CNT_S  0
-/** UART_DSRN : RO; bitpos: [13]; default: 0;
- *  The register represent the level value of the internal uart dsr signal.
- */
-#define UART_DSRN    (BIT(13))
-#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
-#define UART_DSRN_V  0x00000001U
-#define UART_DSRN_S  13
-/** UART_CTSN : RO; bitpos: [14]; default: 1;
- *  This register represent the level value of the internal uart cts signal.
- */
-#define UART_CTSN    (BIT(14))
-#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
-#define UART_CTSN_V  0x00000001U
-#define UART_CTSN_S  14
-/** UART_RXD : RO; bitpos: [15]; default: 1;
- *  This register represent the  level value of the internal uart rxd signal.
- */
-#define UART_RXD    (BIT(15))
-#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
-#define UART_RXD_V  0x00000001U
-#define UART_RXD_S  15
-/** UART_TXFIFO_CNT : RO; bitpos: [25:16]; default: 0;
- *  Stores the byte number of data in Tx-FIFO.
- */
-#define UART_TXFIFO_CNT    0x000003FFU
-#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
-#define UART_TXFIFO_CNT_V  0x000003FFU
-#define UART_TXFIFO_CNT_S  16
-/** UART_DTRN : RO; bitpos: [29]; default: 1;
- *  This bit represents the level of the internal uart dtr signal.
- */
-#define UART_DTRN    (BIT(29))
-#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
-#define UART_DTRN_V  0x00000001U
-#define UART_DTRN_S  29
-/** UART_RTSN : RO; bitpos: [30]; default: 1;
- *  This bit represents the level of the internal uart rts signal.
- */
-#define UART_RTSN    (BIT(30))
-#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
-#define UART_RTSN_V  0x00000001U
-#define UART_RTSN_S  30
-/** UART_TXD : RO; bitpos: [31]; default: 1;
- *  This bit represents the  level of the internal uart txd signal.
- */
-#define UART_TXD    (BIT(31))
-#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
-#define UART_TXD_V  0x00000001U
-#define UART_TXD_S  31
-
-/** UART_CONF0_REG register
- *  a
- */
-#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)
-/** UART_PARITY : R/W; bitpos: [0]; default: 0;
- *  This register is used to configure the parity check mode.
- */
-#define UART_PARITY    (BIT(0))
-#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
-#define UART_PARITY_V  0x00000001U
-#define UART_PARITY_S  0
-/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to enable uart parity check.
- */
-#define UART_PARITY_EN    (BIT(1))
-#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
-#define UART_PARITY_EN_V  0x00000001U
-#define UART_PARITY_EN_S  1
-/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
- *  This register is used to set the length of data.
- */
-#define UART_BIT_NUM    0x00000003U
-#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
-#define UART_BIT_NUM_V  0x00000003U
-#define UART_BIT_NUM_S  2
-/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
- *  This register is used to set the length of  stop bit.
- */
-#define UART_STOP_BIT_NUM    0x00000003U
-#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
-#define UART_STOP_BIT_NUM_V  0x00000003U
-#define UART_STOP_BIT_NUM_S  4
-/** UART_SW_RTS : R/W; bitpos: [6]; default: 0;
- *  This register is used to configure the software rts signal which is used in
- *  software flow control.
- */
-#define UART_SW_RTS    (BIT(6))
-#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
-#define UART_SW_RTS_V  0x00000001U
-#define UART_SW_RTS_S  6
-/** UART_SW_DTR : R/W; bitpos: [7]; default: 0;
- *  This register is used to configure the software dtr signal which is used in
- *  software flow control.
- */
-#define UART_SW_DTR    (BIT(7))
-#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
-#define UART_SW_DTR_V  0x00000001U
-#define UART_SW_DTR_S  7
-/** UART_TXD_BRK : R/W; bitpos: [8]; default: 0;
- *  Set this bit to enbale transmitter to  send NULL when the process of sending data
- *  is done.
- */
-#define UART_TXD_BRK    (BIT(8))
-#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
-#define UART_TXD_BRK_V  0x00000001U
-#define UART_TXD_BRK_S  8
-/** UART_IRDA_DPLX : R/W; bitpos: [9]; default: 0;
- *  Set this bit to enable IrDA loopback mode.
- */
-#define UART_IRDA_DPLX    (BIT(9))
-#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
-#define UART_IRDA_DPLX_V  0x00000001U
-#define UART_IRDA_DPLX_S  9
-/** UART_IRDA_TX_EN : R/W; bitpos: [10]; default: 0;
- *  This is the start enable bit for IrDA transmitter.
- */
-#define UART_IRDA_TX_EN    (BIT(10))
-#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
-#define UART_IRDA_TX_EN_V  0x00000001U
-#define UART_IRDA_TX_EN_S  10
-/** UART_IRDA_WCTL : R/W; bitpos: [11]; default: 0;
- *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
- *  transmitter's 11th bit to 0.
- */
-#define UART_IRDA_WCTL    (BIT(11))
-#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
-#define UART_IRDA_WCTL_V  0x00000001U
-#define UART_IRDA_WCTL_S  11
-/** UART_IRDA_TX_INV : R/W; bitpos: [12]; default: 0;
- *  Set this bit to invert the level of  IrDA transmitter.
- */
-#define UART_IRDA_TX_INV    (BIT(12))
-#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
-#define UART_IRDA_TX_INV_V  0x00000001U
-#define UART_IRDA_TX_INV_S  12
-/** UART_IRDA_RX_INV : R/W; bitpos: [13]; default: 0;
- *  Set this bit to invert the level of IrDA receiver.
- */
-#define UART_IRDA_RX_INV    (BIT(13))
-#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
-#define UART_IRDA_RX_INV_V  0x00000001U
-#define UART_IRDA_RX_INV_S  13
-/** UART_LOOPBACK : R/W; bitpos: [14]; default: 0;
- *  Set this bit to enable uart loopback test mode.
- */
-#define UART_LOOPBACK    (BIT(14))
-#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
-#define UART_LOOPBACK_V  0x00000001U
-#define UART_LOOPBACK_S  14
-/** UART_TX_FLOW_EN : R/W; bitpos: [15]; default: 0;
- *  Set this bit to enable flow control function for transmitter.
- */
-#define UART_TX_FLOW_EN    (BIT(15))
-#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
-#define UART_TX_FLOW_EN_V  0x00000001U
-#define UART_TX_FLOW_EN_S  15
-/** UART_IRDA_EN : R/W; bitpos: [16]; default: 0;
- *  Set this bit to enable IrDA protocol.
- */
-#define UART_IRDA_EN    (BIT(16))
-#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
-#define UART_IRDA_EN_V  0x00000001U
-#define UART_IRDA_EN_S  16
-/** UART_RXFIFO_RST : R/W; bitpos: [17]; default: 0;
- *  Set this bit to reset the uart receive-FIFO.
- */
-#define UART_RXFIFO_RST    (BIT(17))
-#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
-#define UART_RXFIFO_RST_V  0x00000001U
-#define UART_RXFIFO_RST_S  17
-/** UART_TXFIFO_RST : R/W; bitpos: [18]; default: 0;
- *  Set this bit to reset the uart transmit-FIFO.
- */
-#define UART_TXFIFO_RST    (BIT(18))
-#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
-#define UART_TXFIFO_RST_V  0x00000001U
-#define UART_TXFIFO_RST_S  18
-/** UART_RXD_INV : R/W; bitpos: [19]; default: 0;
- *  Set this bit to inverse the level value of uart rxd signal.
- */
-#define UART_RXD_INV    (BIT(19))
-#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
-#define UART_RXD_INV_V  0x00000001U
-#define UART_RXD_INV_S  19
-/** UART_CTS_INV : R/W; bitpos: [20]; default: 0;
- *  Set this bit to inverse the level value of uart cts signal.
- */
-#define UART_CTS_INV    (BIT(20))
-#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
-#define UART_CTS_INV_V  0x00000001U
-#define UART_CTS_INV_S  20
-/** UART_DSR_INV : R/W; bitpos: [21]; default: 0;
- *  Set this bit to inverse the level value of uart dsr signal.
- */
-#define UART_DSR_INV    (BIT(21))
-#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
-#define UART_DSR_INV_V  0x00000001U
-#define UART_DSR_INV_S  21
-/** UART_TXD_INV : R/W; bitpos: [22]; default: 0;
- *  Set this bit to inverse the level value of uart txd signal.
- */
-#define UART_TXD_INV    (BIT(22))
-#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
-#define UART_TXD_INV_V  0x00000001U
-#define UART_TXD_INV_S  22
-/** UART_RTS_INV : R/W; bitpos: [23]; default: 0;
- *  Set this bit to inverse the level value of uart rts signal.
- */
-#define UART_RTS_INV    (BIT(23))
-#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
-#define UART_RTS_INV_V  0x00000001U
-#define UART_RTS_INV_S  23
-/** UART_DTR_INV : R/W; bitpos: [24]; default: 0;
- *  Set this bit to inverse the level value of uart dtr signal.
- */
-#define UART_DTR_INV    (BIT(24))
-#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
-#define UART_DTR_INV_V  0x00000001U
-#define UART_DTR_INV_S  24
-/** UART_CLK_EN : R/W; bitpos: [25]; default: 0;
- *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
- *  registers.
- */
-#define UART_CLK_EN    (BIT(25))
-#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
-#define UART_CLK_EN_V  0x00000001U
-#define UART_CLK_EN_S  25
-/** UART_ERR_WR_MASK : R/W; bitpos: [26]; default: 0;
- *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
- *  stores the data even if the  received data is wrong.
- */
-#define UART_ERR_WR_MASK    (BIT(26))
-#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
-#define UART_ERR_WR_MASK_V  0x00000001U
-#define UART_ERR_WR_MASK_S  26
-/** UART_AUTOBAUD_EN : R/W; bitpos: [27]; default: 0;
- *  This is the enable bit for detecting baudrate.
- */
-#define UART_AUTOBAUD_EN    (BIT(27))
-#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
-#define UART_AUTOBAUD_EN_V  0x00000001U
-#define UART_AUTOBAUD_EN_S  27
-/** UART_MEM_CLK_EN : R/W; bitpos: [28]; default: 1;
- *  UART memory clock gate enable signal.
- */
-#define UART_MEM_CLK_EN    (BIT(28))
-#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
-#define UART_MEM_CLK_EN_V  0x00000001U
-#define UART_MEM_CLK_EN_S  28
-
-/** UART_CONF1_REG register
- *  Configuration register 1
- */
-#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
-/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [9:0]; default: 96;
- *  It will produce rxfifo_full_int interrupt when receiver receives more data than
- *  this register value.
- */
-#define UART_RXFIFO_FULL_THRHD    0x000003FFU
-#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
-#define UART_RXFIFO_FULL_THRHD_V  0x000003FFU
-#define UART_RXFIFO_FULL_THRHD_S  0
-/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [19:10]; default: 96;
- *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
- *  than this register value.
- */
-#define UART_TXFIFO_EMPTY_THRHD    0x000003FFU
-#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
-#define UART_TXFIFO_EMPTY_THRHD_V  0x000003FFU
-#define UART_TXFIFO_EMPTY_THRHD_S  10
-/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [20]; default: 0;
- *  Disable UART Rx data overflow detect.
- */
-#define UART_DIS_RX_DAT_OVF    (BIT(20))
-#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
-#define UART_DIS_RX_DAT_OVF_V  0x00000001U
-#define UART_DIS_RX_DAT_OVF_S  20
-/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [21]; default: 0;
- *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
- */
-#define UART_RX_TOUT_FLOW_DIS    (BIT(21))
-#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
-#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
-#define UART_RX_TOUT_FLOW_DIS_S  21
-/** UART_RX_FLOW_EN : R/W; bitpos: [22]; default: 0;
- *  This is the flow enable bit for UART receiver.
- */
-#define UART_RX_FLOW_EN    (BIT(22))
-#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
-#define UART_RX_FLOW_EN_V  0x00000001U
-#define UART_RX_FLOW_EN_S  22
-/** UART_RX_TOUT_EN : R/W; bitpos: [23]; default: 0;
- *  This is the enble bit for uart receiver's timeout function.
- */
-#define UART_RX_TOUT_EN    (BIT(23))
-#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
-#define UART_RX_TOUT_EN_V  0x00000001U
-#define UART_RX_TOUT_EN_S  23
-
-/** UART_LOWPULSE_REG register
- *  Autobaud minimum low pulse duration register
- */
-#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)
-/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the value of the minimum duration time of the low level pulse.
- *  It is used in baud rate-detect process.
- */
-#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
-#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_LOWPULSE_MIN_CNT_S  0
-
-/** UART_HIGHPULSE_REG register
- *  Autobaud minimum high pulse duration register
- */
-#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c)
-/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores  the value of the maxinum duration time for the high level
- *  pulse. It is used in baud rate-detect process.
- */
-#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
-#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
-#define UART_HIGHPULSE_MIN_CNT_S  0
-
-/** UART_RXD_CNT_REG register
- *  Autobaud edge change count register
- */
-#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
-/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
- *  This register stores the count of rxd edge change. It is used in baud rate-detect
- *  process.
- */
-#define UART_RXD_EDGE_CNT    0x000003FFU
-#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
-#define UART_RXD_EDGE_CNT_V  0x000003FFU
-#define UART_RXD_EDGE_CNT_S  0
-
-/** UART_FLOW_CONF_REG register
- *  Software flow-control configuration
- */
-#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)
-/** UART_SW_FLOW_CON_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to enable software flow control. It is used with register sw_xon or
- *  sw_xoff.
- */
-#define UART_SW_FLOW_CON_EN    (BIT(0))
-#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
-#define UART_SW_FLOW_CON_EN_V  0x00000001U
-#define UART_SW_FLOW_CON_EN_S  0
-/** UART_XONOFF_DEL : R/W; bitpos: [1]; default: 0;
- *  Set this bit to remove flow control char from the received data.
- */
-#define UART_XONOFF_DEL    (BIT(1))
-#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
-#define UART_XONOFF_DEL_V  0x00000001U
-#define UART_XONOFF_DEL_S  1
-/** UART_FORCE_XON : R/W; bitpos: [2]; default: 0;
- *  Set this bit to enable the transmitter to go on sending data.
- */
-#define UART_FORCE_XON    (BIT(2))
-#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
-#define UART_FORCE_XON_V  0x00000001U
-#define UART_FORCE_XON_S  2
-/** UART_FORCE_XOFF : R/W; bitpos: [3]; default: 0;
- *  Set this bit to stop the  transmitter from sending data.
- */
-#define UART_FORCE_XOFF    (BIT(3))
-#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
-#define UART_FORCE_XOFF_V  0x00000001U
-#define UART_FORCE_XOFF_S  3
-/** UART_SEND_XON : R/W/SS/SC; bitpos: [4]; default: 0;
- *  Set this bit to send Xon char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XON    (BIT(4))
-#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
-#define UART_SEND_XON_V  0x00000001U
-#define UART_SEND_XON_S  4
-/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [5]; default: 0;
- *  Set this bit to send Xoff char. It is cleared by hardware automatically.
- */
-#define UART_SEND_XOFF    (BIT(5))
-#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
-#define UART_SEND_XOFF_V  0x00000001U
-#define UART_SEND_XOFF_S  5
-
-/** UART_SLEEP_CONF_REG register
- *  Sleep-mode configuration
- */
-#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
-/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
- *  The uart is activated from light sleeping mode when the input rxd edge changes more
- *  times than this register value.
- */
-#define UART_ACTIVE_THRESHOLD    0x000003FFU
-#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
-#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
-#define UART_ACTIVE_THRESHOLD_S  0
-
-/** UART_SWFC_CONF0_REG register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3c)
-/** UART_XOFF_THRESHOLD : R/W; bitpos: [9:0]; default: 224;
- *  When the data amount in Rx-FIFO is more than this register value with
- *  uart_sw_flow_con_en set to 1, it will send a Xoff char.
- */
-#define UART_XOFF_THRESHOLD    0x000003FFU
-#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
-#define UART_XOFF_THRESHOLD_V  0x000003FFU
-#define UART_XOFF_THRESHOLD_S  0
-/** UART_XOFF_CHAR : R/W; bitpos: [17:10]; default: 19;
- *  This register stores the Xoff flow control char.
- */
-#define UART_XOFF_CHAR    0x000000FFU
-#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
-#define UART_XOFF_CHAR_V  0x000000FFU
-#define UART_XOFF_CHAR_S  10
-
-/** UART_SWFC_CONF1_REG register
- *  Software flow-control character configuration
- */
-#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
-/** UART_XON_THRESHOLD : R/W; bitpos: [9:0]; default: 0;
- *  When the data amount in Rx-FIFO is less than this register value with
- *  uart_sw_flow_con_en set to 1, it will send a Xon char.
- */
-#define UART_XON_THRESHOLD    0x000003FFU
-#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
-#define UART_XON_THRESHOLD_V  0x000003FFU
-#define UART_XON_THRESHOLD_S  0
-/** UART_XON_CHAR : R/W; bitpos: [17:10]; default: 17;
- *  This register stores the Xon flow control char.
- */
-#define UART_XON_CHAR    0x000000FFU
-#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
-#define UART_XON_CHAR_V  0x000000FFU
-#define UART_XON_CHAR_S  10
-
-/** UART_TXBRK_CONF_REG register
- *  Tx Break character configuration
- */
-#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44)
-/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
- *  This register is used to configure the number of 0 to be sent after the process of
- *  sending data is done. It is active when txd_brk is set to 1.
- */
-#define UART_TX_BRK_NUM    0x000000FFU
-#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
-#define UART_TX_BRK_NUM_V  0x000000FFU
-#define UART_TX_BRK_NUM_S  0
-
-/** UART_IDLE_CONF_REG register
- *  Frame-end idle configuration
- */
-#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48)
-/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
- *  It will produce frame end signal when receiver takes more time to receive one byte
- *  data than this register value.
- */
-#define UART_RX_IDLE_THRHD    0x000003FFU
-#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
-#define UART_RX_IDLE_THRHD_V  0x000003FFU
-#define UART_RX_IDLE_THRHD_S  0
-/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
- *  This register is used to configure the duration time between transfers.
- */
-#define UART_TX_IDLE_NUM    0x000003FFU
-#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
-#define UART_TX_IDLE_NUM_V  0x000003FFU
-#define UART_TX_IDLE_NUM_S  10
-
-/** UART_RS485_CONF_REG register
- *  RS485 mode configuration
- */
-#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4c)
-/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
- *  Set this bit to choose the rs485 mode.
- */
-#define UART_RS485_EN    (BIT(0))
-#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
-#define UART_RS485_EN_V  0x00000001U
-#define UART_RS485_EN_S  0
-/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL0_EN    (BIT(1))
-#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
-#define UART_DL0_EN_V  0x00000001U
-#define UART_DL0_EN_S  1
-/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
- *  Set this bit to delay the stop bit by 1 bit.
- */
-#define UART_DL1_EN    (BIT(2))
-#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
-#define UART_DL1_EN_V  0x00000001U
-#define UART_DL1_EN_S  2
-/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
- *  Set this bit to enable receiver could receive data when the transmitter is
- *  transmitting data in rs485 mode.
- */
-#define UART_RS485TX_RX_EN    (BIT(3))
-#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
-#define UART_RS485TX_RX_EN_V  0x00000001U
-#define UART_RS485TX_RX_EN_S  3
-/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
- *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
- */
-#define UART_RS485RXBY_TX_EN    (BIT(4))
-#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
-#define UART_RS485RXBY_TX_EN_V  0x00000001U
-#define UART_RS485RXBY_TX_EN_S  4
-/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
- *  This register is used to delay the receiver's internal data signal.
- */
-#define UART_RS485_RX_DLY_NUM    (BIT(5))
-#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
-#define UART_RS485_RX_DLY_NUM_V  0x00000001U
-#define UART_RS485_RX_DLY_NUM_S  5
-/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
- *  This register is used to delay the transmitter's internal data signal.
- */
-#define UART_RS485_TX_DLY_NUM    0x0000000FU
-#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
-#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
-#define UART_RS485_TX_DLY_NUM_S  6
-
-/** UART_AT_CMD_PRECNT_REG register
- *  Pre-sequence timing configuration
- */
-#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50)
-/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the idle duration time before the first at_cmd
- *  is received by receiver.
- */
-#define UART_PRE_IDLE_NUM    0x0000FFFFU
-#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
-#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
-#define UART_PRE_IDLE_NUM_S  0
-
-/** UART_AT_CMD_POSTCNT_REG register
- *  Post-sequence timing configuration
- */
-#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54)
-/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
- *  This register is used to configure the duration time between the last at_cmd and
- *  the next data.
- */
-#define UART_POST_IDLE_NUM    0x0000FFFFU
-#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
-#define UART_POST_IDLE_NUM_V  0x0000FFFFU
-#define UART_POST_IDLE_NUM_S  0
-
-/** UART_AT_CMD_GAPTOUT_REG register
- *  Timeout configuration
- */
-#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58)
-/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
- *  This register is used to configure the duration time between the at_cmd chars.
- */
-#define UART_RX_GAP_TOUT    0x0000FFFFU
-#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
-#define UART_RX_GAP_TOUT_V  0x0000FFFFU
-#define UART_RX_GAP_TOUT_S  0
-
-/** UART_AT_CMD_CHAR_REG register
- *  AT escape sequence detection configuration
- */
-#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c)
-/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
- *  This register is used to configure the content of at_cmd char.
- */
-#define UART_AT_CMD_CHAR    0x000000FFU
-#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
-#define UART_AT_CMD_CHAR_V  0x000000FFU
-#define UART_AT_CMD_CHAR_S  0
-/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
- *  This register is used to configure the num of continuous at_cmd chars received by
- *  receiver.
- */
-#define UART_CHAR_NUM    0x000000FFU
-#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
-#define UART_CHAR_NUM_V  0x000000FFU
-#define UART_CHAR_NUM_S  8
-
-/** UART_MEM_CONF_REG register
- *  UART threshold and allocation configuration
- */
-#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
-/** UART_RX_SIZE : R/W; bitpos: [3:1]; default: 1;
- *  This register is used to configure the amount of mem allocated for receive-FIFO.
- *  The default number is 128 bytes.
- */
-#define UART_RX_SIZE    0x00000007U
-#define UART_RX_SIZE_M  (UART_RX_SIZE_V << UART_RX_SIZE_S)
-#define UART_RX_SIZE_V  0x00000007U
-#define UART_RX_SIZE_S  1
-/** UART_TX_SIZE : R/W; bitpos: [6:4]; default: 1;
- *  This register is used to configure the amount of mem allocated for transmit-FIFO.
- *  The default number is 128 bytes.
- */
-#define UART_TX_SIZE    0x00000007U
-#define UART_TX_SIZE_M  (UART_TX_SIZE_V << UART_TX_SIZE_S)
-#define UART_TX_SIZE_V  0x00000007U
-#define UART_TX_SIZE_S  4
-/** UART_RX_FLOW_THRHD : R/W; bitpos: [16:7]; default: 0;
- *  This register is used to configure the maximum amount of data that can be received
- *  when hardware flow control works.
- */
-#define UART_RX_FLOW_THRHD    0x000003FFU
-#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
-#define UART_RX_FLOW_THRHD_V  0x000003FFU
-#define UART_RX_FLOW_THRHD_S  7
-/** UART_RX_TOUT_THRHD : R/W; bitpos: [26:17]; default: 10;
- *  This register is used to configure the threshold time that receiver takes to
- *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
- *  takes more time to receive one byte with rx_tout_en set to 1.
- */
-#define UART_RX_TOUT_THRHD    0x000003FFU
-#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
-#define UART_RX_TOUT_THRHD_V  0x000003FFU
-#define UART_RX_TOUT_THRHD_S  17
-/** UART_MEM_FORCE_PD : R/W; bitpos: [27]; default: 0;
- *  Set this bit to force power down UART memory.
- */
-#define UART_MEM_FORCE_PD    (BIT(27))
-#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
-#define UART_MEM_FORCE_PD_V  0x00000001U
-#define UART_MEM_FORCE_PD_S  27
-/** UART_MEM_FORCE_PU : R/W; bitpos: [28]; default: 0;
- *  Set this bit to force power up UART memory.
- */
-#define UART_MEM_FORCE_PU    (BIT(28))
-#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
-#define UART_MEM_FORCE_PU_V  0x00000001U
-#define UART_MEM_FORCE_PU_S  28
-
-/** UART_MEM_TX_STATUS_REG register
- *  Tx-FIFO write and read offset address.
- */
-#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
-/** UART_APB_TX_WADDR : RO; bitpos: [9:0]; default: 0;
- *  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via
- *  APB.
- */
-#define UART_APB_TX_WADDR    0x000003FFU
-#define UART_APB_TX_WADDR_M  (UART_APB_TX_WADDR_V << UART_APB_TX_WADDR_S)
-#define UART_APB_TX_WADDR_V  0x000003FFU
-#define UART_APB_TX_WADDR_S  0
-/** UART_TX_RADDR : RO; bitpos: [20:11]; default: 0;
- *  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
- *  Tx-FIFO_Ctrl.
- */
-#define UART_TX_RADDR    0x000003FFU
-#define UART_TX_RADDR_M  (UART_TX_RADDR_V << UART_TX_RADDR_S)
-#define UART_TX_RADDR_V  0x000003FFU
-#define UART_TX_RADDR_S  11
-
-/** UART_MEM_RX_STATUS_REG register
- *  Rx-FIFO write and read offset address.
- */
-#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
-/** UART_APB_RX_RADDR : RO; bitpos: [9:0]; default: 512;
- *  This register stores the offset address in RX-FIFO when software reads data from
- *  Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
- */
-#define UART_APB_RX_RADDR    0x000003FFU
-#define UART_APB_RX_RADDR_M  (UART_APB_RX_RADDR_V << UART_APB_RX_RADDR_S)
-#define UART_APB_RX_RADDR_V  0x000003FFU
-#define UART_APB_RX_RADDR_S  0
-/** UART_RX_WADDR : RO; bitpos: [20:11]; default: 512;
- *  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
- *  Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
- */
-#define UART_RX_WADDR    0x000003FFU
-#define UART_RX_WADDR_M  (UART_RX_WADDR_V << UART_RX_WADDR_S)
-#define UART_RX_WADDR_V  0x000003FFU
-#define UART_RX_WADDR_S  11
-
-/** UART_FSM_STATUS_REG register
- *  UART transmit and receive status.
- */
-#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
-/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
- *  This is the status register of receiver.
- */
-#define UART_ST_URX_OUT    0x0000000FU
-#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
-#define UART_ST_URX_OUT_V  0x0000000FU
-#define UART_ST_URX_OUT_S  0
-/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
- *  This is the status register of transmitter.
- */
-#define UART_ST_UTX_OUT    0x0000000FU
-#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
-#define UART_ST_UTX_OUT_V  0x0000000FU
-#define UART_ST_UTX_OUT_S  4
-
-/** UART_POSPULSE_REG register
- *  Autobaud high pulse register
- */
-#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70)
-/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two positive edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_POSEDGE_MIN_CNT    0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
-#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_POSEDGE_MIN_CNT_S  0
-
-/** UART_NEGPULSE_REG register
- *  Autobaud low pulse register
- */
-#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
-/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
- *  This register stores the minimal input clock count between two negative edges. It
- *  is used in boudrate-detect process.
- */
-#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
-#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
-#define UART_NEGEDGE_MIN_CNT_S  0
-
-/** UART_CLK_CONF_REG register
- *  UART core clock configuration
- */
-#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78)
-/** UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
- *  The  denominator of the frequency divider factor.
- */
-#define UART_SCLK_DIV_B    0x0000003FU
-#define UART_SCLK_DIV_B_M  (UART_SCLK_DIV_B_V << UART_SCLK_DIV_B_S)
-#define UART_SCLK_DIV_B_V  0x0000003FU
-#define UART_SCLK_DIV_B_S  0
-/** UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
- *  The numerator of the frequency divider factor.
- */
-#define UART_SCLK_DIV_A    0x0000003FU
-#define UART_SCLK_DIV_A_M  (UART_SCLK_DIV_A_V << UART_SCLK_DIV_A_S)
-#define UART_SCLK_DIV_A_V  0x0000003FU
-#define UART_SCLK_DIV_A_S  6
-/** UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
- *  The integral part of the frequency divider factor.
- */
-#define UART_SCLK_DIV_NUM    0x000000FFU
-#define UART_SCLK_DIV_NUM_M  (UART_SCLK_DIV_NUM_V << UART_SCLK_DIV_NUM_S)
-#define UART_SCLK_DIV_NUM_V  0x000000FFU
-#define UART_SCLK_DIV_NUM_S  12
-/** UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
- *  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
- */
-#define UART_SCLK_SEL    0x00000003U
-#define UART_SCLK_SEL_M  (UART_SCLK_SEL_V << UART_SCLK_SEL_S)
-#define UART_SCLK_SEL_V  0x00000003U
-#define UART_SCLK_SEL_S  20
-/** UART_SCLK_EN : R/W; bitpos: [22]; default: 1;
- *  Set this bit to enable UART Tx/Rx clock.
- */
-#define UART_SCLK_EN    (BIT(22))
-#define UART_SCLK_EN_M  (UART_SCLK_EN_V << UART_SCLK_EN_S)
-#define UART_SCLK_EN_V  0x00000001U
-#define UART_SCLK_EN_S  22
-/** UART_RST_CORE : R/W; bitpos: [23]; default: 0;
- *  Write 1 then write 0 to this bit, reset UART Tx/Rx.
- */
-#define UART_RST_CORE    (BIT(23))
-#define UART_RST_CORE_M  (UART_RST_CORE_V << UART_RST_CORE_S)
-#define UART_RST_CORE_V  0x00000001U
-#define UART_RST_CORE_S  23
-/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
- *  Set this bit to enable UART Tx clock.
- */
-#define UART_TX_SCLK_EN    (BIT(24))
-#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
-#define UART_TX_SCLK_EN_V  0x00000001U
-#define UART_TX_SCLK_EN_S  24
-/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
- *  Set this bit to enable UART Rx clock.
- */
-#define UART_RX_SCLK_EN    (BIT(25))
-#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
-#define UART_RX_SCLK_EN_V  0x00000001U
-#define UART_RX_SCLK_EN_S  25
-/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
- *  Write 1 then write 0 to this bit, reset UART Tx.
- */
-#define UART_TX_RST_CORE    (BIT(26))
-#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
-#define UART_TX_RST_CORE_V  0x00000001U
-#define UART_TX_RST_CORE_S  26
-/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
- *  Write 1 then write 0 to this bit, reset UART Rx.
- */
-#define UART_RX_RST_CORE    (BIT(27))
-#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
-#define UART_RX_RST_CORE_V  0x00000001U
-#define UART_RX_RST_CORE_S  27
-
-/** UART_DATE_REG register
- *  UART Version register
- */
-#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c)
-/** UART_DATE : R/W; bitpos: [31:0]; default: 33587824;
- *  This is the version register.
- */
-#define UART_DATE    0xFFFFFFFFU
-#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
-#define UART_DATE_V  0xFFFFFFFFU
-#define UART_DATE_S  0
-
-/** UART_ID_REG register
- *  UART ID register
- */
-#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80)
-/** UART_ID : R/W; bitpos: [29:0]; default: 1280;
- *  This register is used to configure the uart_id.
- */
-#define UART_ID    0x3FFFFFFFU
-#define UART_ID_M  (UART_ID_V << UART_ID_S)
-#define UART_ID_V  0x3FFFFFFFU
-#define UART_ID_S  0
-/** UART_HIGH_SPEED : R/W; bitpos: [30]; default: 1;
- *  This bit used to select synchronize mode. 1: Registers are auto synchronized into
- *  UART Core clock and UART core should be keep the same with APB clock. 0: After
- *  configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize
- *  registers.
- */
-#define UART_HIGH_SPEED    (BIT(30))
-#define UART_HIGH_SPEED_M  (UART_HIGH_SPEED_V << UART_HIGH_SPEED_S)
-#define UART_HIGH_SPEED_V  0x00000001U
-#define UART_HIGH_SPEED_S  30
-/** UART_REG_UPDATE : R/W/SC; bitpos: [31]; default: 0;
- *  Software write 1 would synchronize registers into UART Core clock domain and would
- *  be cleared by hardware after synchronization is done.
- */
-#define UART_REG_UPDATE    (BIT(31))
-#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
-#define UART_REG_UPDATE_V  0x00000001U
-#define UART_REG_UPDATE_S  31
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/uart_struct.h b/components/soc/esp32s3/include/soc/uart_struct.h
deleted file mode 100644
index 23d6d15450e..00000000000
--- a/components/soc/esp32s3/include/soc/uart_struct.h
+++ /dev/null
@@ -1,1213 +0,0 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: FIFO Configuration */
-/** Type of fifo register
- *  FIFO data register
- */
-typedef union {
-    struct {
-        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
-         *  UART $n accesses FIFO via this register.
-         *  Must be a unit32_t not a bitfield as to avoid
-         *  a read->write operation during writing. Reading
-         *  during writing would impact RX fifo
-         */
-        uint32_t rxfifo_rd_byte;
-    };
-    uint32_t val;
-} uart_fifo_reg_t;
-
-/** Type of mem_conf register
- *  UART threshold and allocation configuration
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:1;
-        /** rx_size : R/W; bitpos: [3:1]; default: 1;
-         *  This register is used to configure the amount of mem allocated for receive-FIFO.
-         *  The default number is 128 bytes.
-         */
-        uint32_t rx_size:3;
-        /** tx_size : R/W; bitpos: [6:4]; default: 1;
-         *  This register is used to configure the amount of mem allocated for transmit-FIFO.
-         *  The default number is 128 bytes.
-         */
-        uint32_t tx_size:3;
-        /** rx_flow_thrhd : R/W; bitpos: [16:7]; default: 0;
-         *  This register is used to configure the maximum amount of data that can be received
-         *  when hardware flow control works.
-         */
-        uint32_t rx_flow_thrhd:10;
-        /** rx_tout_thrhd : R/W; bitpos: [26:17]; default: 10;
-         *  This register is used to configure the threshold time that receiver takes to
-         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
-         *  takes more time to receive one byte with rx_tout_en set to 1.
-         */
-        uint32_t rx_tout_thrhd:10;
-        /** mem_force_pd : R/W; bitpos: [27]; default: 0;
-         *  Set this bit to force power down UART memory.
-         */
-        uint32_t mem_force_pd:1;
-        /** mem_force_pu : R/W; bitpos: [28]; default: 0;
-         *  Set this bit to force power up UART memory.
-         */
-        uint32_t mem_force_pu:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} uart_mem_conf_reg_t;
-
-
-/** Group: Interrupt Register */
-/** Type of int_raw register
- *  Raw interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  what rxfifo_full_thrhd specifies.
-         */
-        uint32_t rxfifo_full_int_raw:1;
-        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
-         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-         *  less than what txfifo_empty_thrhd specifies .
-         */
-        uint32_t txfifo_empty_int_raw:1;
-        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error in
-         *  the data.
-         */
-        uint32_t parity_err_int_raw:1;
-        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  .
-         */
-        uint32_t frm_err_int_raw:1;
-        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives more data than
-         *  the FIFO can store.
-         */
-        uint32_t rxfifo_ovf_int_raw:1;
-        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  DSRn signal.
-         */
-        uint32_t dsr_chg_int_raw:1;
-        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the edge change of
-         *  CTSn signal.
-         */
-        uint32_t cts_chg_int_raw:1;
-        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
-         *  bit.
-         */
-        uint32_t brk_det_int_raw:1;
-        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver takes more time than
-         *  rx_tout_thrhd to receive a byte.
-         */
-        uint32_t rxfifo_tout_int_raw:1;
-        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver recevies Xon char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xon_int_raw:1;
-        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
-         *  uart_sw_flow_con_en is set to 1.
-         */
-        uint32_t sw_xoff_int_raw:1;
-        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
-         *  middle of a start bit.
-         */
-        uint32_t glitch_det_int_raw:1;
-        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter completes  sending
-         *  NULL characters, after all data in Tx-FIFO are sent.
-         */
-        uint32_t tx_brk_done_int_raw:1;
-        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
-         *  duration after sending the  last data.
-         */
-        uint32_t tx_brk_idle_done_int_raw:1;
-        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
-         *  This interrupt raw bit turns to high level when transmitter has send out all data
-         *  in FIFO.
-         */
-        uint32_t tx_done_int_raw:1;
-        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a parity error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_parity_err_int_raw:1;
-        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects a data frame error
-         *  from the echo of transmitter in rs485 mode.
-         */
-        uint32_t rs485_frm_err_int_raw:1;
-        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
-         *  This interrupt raw bit turns to high level when detects a clash between transmitter
-         *  and receiver in rs485 mode.
-         */
-        uint32_t rs485_clash_int_raw:1;
-        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
-         *  This interrupt raw bit turns to high level when receiver detects the configured
-         *  at_cmd char.
-         */
-        uint32_t at_cmd_char_det_int_raw:1;
-        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
-         *  This interrupt raw bit turns to high level when input rxd edge changes more times
-         *  than what reg_active_threshold specifies in light sleeping mode.
-         */
-        uint32_t wakeup_int_raw:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_raw_reg_t;
-
-/** Type of int_st register
- *  Masked interrupt status
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
-         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-         */
-        uint32_t rxfifo_full_int_st:1;
-        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
-         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
-         *  to 1.
-         */
-        uint32_t txfifo_empty_int_st:1;
-        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
-         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-         */
-        uint32_t parity_err_int_st:1;
-        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
-         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-         */
-        uint32_t frm_err_int_st:1;
-        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
-         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-         */
-        uint32_t rxfifo_ovf_int_st:1;
-        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
-         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-         */
-        uint32_t dsr_chg_int_st:1;
-        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
-         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-         */
-        uint32_t cts_chg_int_st:1;
-        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
-         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-         */
-        uint32_t brk_det_int_st:1;
-        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
-         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-         */
-        uint32_t rxfifo_tout_int_st:1;
-        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
-         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-         */
-        uint32_t sw_xon_int_st:1;
-        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
-         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-         */
-        uint32_t sw_xoff_int_st:1;
-        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
-         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-         */
-        uint32_t glitch_det_int_st:1;
-        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
-         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-         */
-        uint32_t tx_brk_done_int_st:1;
-        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
-         *  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
-         *  is set to 1.
-         */
-        uint32_t tx_brk_idle_done_int_st:1;
-        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
-         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-         */
-        uint32_t tx_done_int_st:1;
-        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
-         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-         *  set to 1.
-         */
-        uint32_t rs485_parity_err_int_st:1;
-        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
-         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
-         *  to 1.
-         */
-        uint32_t rs485_frm_err_int_st:1;
-        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
-         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
-         */
-        uint32_t rs485_clash_int_st:1;
-        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
-         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
-         *  to 1.
-         */
-        uint32_t at_cmd_char_det_int_st:1;
-        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
-         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-         */
-        uint32_t wakeup_int_st:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_st_reg_t;
-
-/** Type of int_ena register
- *  Interrupt enable bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
-         *  This is the enable bit for rxfifo_full_int_st register.
-         */
-        uint32_t rxfifo_full_int_ena:1;
-        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
-         *  This is the enable bit for txfifo_empty_int_st register.
-         */
-        uint32_t txfifo_empty_int_ena:1;
-        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
-         *  This is the enable bit for parity_err_int_st register.
-         */
-        uint32_t parity_err_int_ena:1;
-        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
-         *  This is the enable bit for frm_err_int_st register.
-         */
-        uint32_t frm_err_int_ena:1;
-        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
-         *  This is the enable bit for rxfifo_ovf_int_st register.
-         */
-        uint32_t rxfifo_ovf_int_ena:1;
-        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
-         *  This is the enable bit for dsr_chg_int_st register.
-         */
-        uint32_t dsr_chg_int_ena:1;
-        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
-         *  This is the enable bit for cts_chg_int_st register.
-         */
-        uint32_t cts_chg_int_ena:1;
-        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
-         *  This is the enable bit for brk_det_int_st register.
-         */
-        uint32_t brk_det_int_ena:1;
-        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
-         *  This is the enable bit for rxfifo_tout_int_st register.
-         */
-        uint32_t rxfifo_tout_int_ena:1;
-        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
-         *  This is the enable bit for sw_xon_int_st register.
-         */
-        uint32_t sw_xon_int_ena:1;
-        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
-         *  This is the enable bit for sw_xoff_int_st register.
-         */
-        uint32_t sw_xoff_int_ena:1;
-        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
-         *  This is the enable bit for glitch_det_int_st register.
-         */
-        uint32_t glitch_det_int_ena:1;
-        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
-         *  This is the enable bit for tx_brk_done_int_st register.
-         */
-        uint32_t tx_brk_done_int_ena:1;
-        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
-         *  This is the enable bit for tx_brk_idle_done_int_st register.
-         */
-        uint32_t tx_brk_idle_done_int_ena:1;
-        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
-         *  This is the enable bit for tx_done_int_st register.
-         */
-        uint32_t tx_done_int_ena:1;
-        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_parity_err_int_ena:1;
-        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
-         *  This is the enable bit for rs485_parity_err_int_st register.
-         */
-        uint32_t rs485_frm_err_int_ena:1;
-        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
-         *  This is the enable bit for rs485_clash_int_st register.
-         */
-        uint32_t rs485_clash_int_ena:1;
-        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
-         *  This is the enable bit for at_cmd_char_det_int_st register.
-         */
-        uint32_t at_cmd_char_det_int_ena:1;
-        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
-         *  This is the enable bit for uart_wakeup_int_st register.
-         */
-        uint32_t wakeup_int_ena:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_ena_reg_t;
-
-/** Type of int_clr register
- *  Interrupt clear bits
- */
-typedef union {
-    struct {
-        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
-         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
-         */
-        uint32_t rxfifo_full_int_clr:1;
-        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
-         *  Set this bit to clear txfifo_empty_int_raw interrupt.
-         */
-        uint32_t txfifo_empty_int_clr:1;
-        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
-         *  Set this bit to clear parity_err_int_raw interrupt.
-         */
-        uint32_t parity_err_int_clr:1;
-        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
-         *  Set this bit to clear frm_err_int_raw interrupt.
-         */
-        uint32_t frm_err_int_clr:1;
-        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
-         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-         */
-        uint32_t rxfifo_ovf_int_clr:1;
-        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
-         *  Set this bit to clear the dsr_chg_int_raw interrupt.
-         */
-        uint32_t dsr_chg_int_clr:1;
-        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
-         *  Set this bit to clear the cts_chg_int_raw interrupt.
-         */
-        uint32_t cts_chg_int_clr:1;
-        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
-         *  Set this bit to clear the brk_det_int_raw interrupt.
-         */
-        uint32_t brk_det_int_clr:1;
-        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
-         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-         */
-        uint32_t rxfifo_tout_int_clr:1;
-        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
-         *  Set this bit to clear the sw_xon_int_raw interrupt.
-         */
-        uint32_t sw_xon_int_clr:1;
-        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
-         *  Set this bit to clear the sw_xoff_int_raw interrupt.
-         */
-        uint32_t sw_xoff_int_clr:1;
-        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
-         *  Set this bit to clear the glitch_det_int_raw interrupt.
-         */
-        uint32_t glitch_det_int_clr:1;
-        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
-         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
-         */
-        uint32_t tx_brk_done_int_clr:1;
-        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
-         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-         */
-        uint32_t tx_brk_idle_done_int_clr:1;
-        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
-         *  Set this bit to clear the tx_done_int_raw interrupt.
-         */
-        uint32_t tx_done_int_clr:1;
-        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
-         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
-         */
-        uint32_t rs485_parity_err_int_clr:1;
-        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
-         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
-         */
-        uint32_t rs485_frm_err_int_clr:1;
-        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
-         *  Set this bit to clear the rs485_clash_int_raw interrupt.
-         */
-        uint32_t rs485_clash_int_clr:1;
-        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
-         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-         */
-        uint32_t at_cmd_char_det_int_clr:1;
-        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
-         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
-         */
-        uint32_t wakeup_int_clr:1;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_int_clr_reg_t;
-
-
-/** Group: Configuration Register */
-/** Type of clkdiv register
- *  Clock divider configuration
- */
-typedef union {
-    struct {
-        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t clkdiv:12;
-        uint32_t reserved_12:8;
-        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
-         *  The decimal part of the frequency divider factor.
-         */
-        uint32_t clkdiv_frag:4;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_clkdiv_reg_t;
-
-/** Type of rx_filt register
- *  Rx Filter configuration
- */
-typedef union {
-    struct {
-        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
-         *  when input pulse width is lower than this value, the pulse is ignored.
-         */
-        uint32_t glitch_filt:8;
-        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enable Rx signal filter.
-         */
-        uint32_t glitch_filt_en:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} uart_rx_filt_reg_t;
-
-/** Type of conf0 register
- *  a
- */
-typedef union {
-    struct {
-        /** parity : R/W; bitpos: [0]; default: 0;
-         *  This register is used to configure the parity check mode.
-         */
-        uint32_t parity:1;
-        /** parity_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to enable uart parity check.
-         */
-        uint32_t parity_en:1;
-        /** bit_num : R/W; bitpos: [3:2]; default: 3;
-         *  This register is used to set the length of data.
-         */
-        uint32_t bit_num:2;
-        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
-         *  This register is used to set the length of  stop bit.
-         */
-        uint32_t stop_bit_num:2;
-        /** sw_rts : R/W; bitpos: [6]; default: 0;
-         *  This register is used to configure the software rts signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_rts:1;
-        /** sw_dtr : R/W; bitpos: [7]; default: 0;
-         *  This register is used to configure the software dtr signal which is used in
-         *  software flow control.
-         */
-        uint32_t sw_dtr:1;
-        /** txd_brk : R/W; bitpos: [8]; default: 0;
-         *  Set this bit to enbale transmitter to  send NULL when the process of sending data
-         *  is done.
-         */
-        uint32_t txd_brk:1;
-        /** irda_dplx : R/W; bitpos: [9]; default: 0;
-         *  Set this bit to enable IrDA loopback mode.
-         */
-        uint32_t irda_dplx:1;
-        /** irda_tx_en : R/W; bitpos: [10]; default: 0;
-         *  This is the start enable bit for IrDA transmitter.
-         */
-        uint32_t irda_tx_en:1;
-        /** irda_wctl : R/W; bitpos: [11]; default: 0;
-         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-         *  transmitter's 11th bit to 0.
-         */
-        uint32_t irda_wctl:1;
-        /** irda_tx_inv : R/W; bitpos: [12]; default: 0;
-         *  Set this bit to invert the level of  IrDA transmitter.
-         */
-        uint32_t irda_tx_inv:1;
-        /** irda_rx_inv : R/W; bitpos: [13]; default: 0;
-         *  Set this bit to invert the level of IrDA receiver.
-         */
-        uint32_t irda_rx_inv:1;
-        /** loopback : R/W; bitpos: [14]; default: 0;
-         *  Set this bit to enable uart loopback test mode.
-         */
-        uint32_t loopback:1;
-        /** tx_flow_en : R/W; bitpos: [15]; default: 0;
-         *  Set this bit to enable flow control function for transmitter.
-         */
-        uint32_t tx_flow_en:1;
-        /** irda_en : R/W; bitpos: [16]; default: 0;
-         *  Set this bit to enable IrDA protocol.
-         */
-        uint32_t irda_en:1;
-        /** rxfifo_rst : R/W; bitpos: [17]; default: 0;
-         *  Set this bit to reset the uart receive-FIFO.
-         */
-        uint32_t rxfifo_rst:1;
-        /** txfifo_rst : R/W; bitpos: [18]; default: 0;
-         *  Set this bit to reset the uart transmit-FIFO.
-         */
-        uint32_t txfifo_rst:1;
-        /** rxd_inv : R/W; bitpos: [19]; default: 0;
-         *  Set this bit to inverse the level value of uart rxd signal.
-         */
-        uint32_t rxd_inv:1;
-        /** cts_inv : R/W; bitpos: [20]; default: 0;
-         *  Set this bit to inverse the level value of uart cts signal.
-         */
-        uint32_t cts_inv:1;
-        /** dsr_inv : R/W; bitpos: [21]; default: 0;
-         *  Set this bit to inverse the level value of uart dsr signal.
-         */
-        uint32_t dsr_inv:1;
-        /** txd_inv : R/W; bitpos: [22]; default: 0;
-         *  Set this bit to inverse the level value of uart txd signal.
-         */
-        uint32_t txd_inv:1;
-        /** rts_inv : R/W; bitpos: [23]; default: 0;
-         *  Set this bit to inverse the level value of uart rts signal.
-         */
-        uint32_t rts_inv:1;
-        /** dtr_inv : R/W; bitpos: [24]; default: 0;
-         *  Set this bit to inverse the level value of uart dtr signal.
-         */
-        uint32_t dtr_inv:1;
-        /** clk_en : R/W; bitpos: [25]; default: 0;
-         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
-         *  registers.
-         */
-        uint32_t clk_en:1;
-        /** err_wr_mask : R/W; bitpos: [26]; default: 0;
-         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-         *  stores the data even if the  received data is wrong.
-         */
-        uint32_t err_wr_mask:1;
-        /** autobaud_en : R/W; bitpos: [27]; default: 0;
-         *  This is the enable bit for detecting baudrate.
-         */
-        uint32_t autobaud_en:1;
-        /** mem_clk_en : R/W; bitpos: [28]; default: 1;
-         *  UART memory clock gate enable signal.
-         */
-        uint32_t mem_clk_en:1;
-        uint32_t reserved_29:3;
-    };
-    uint32_t val;
-} uart_conf0_reg_t;
-
-/** Type of conf1 register
- *  Configuration register 1
- */
-typedef union {
-    struct {
-        /** rxfifo_full_thrhd : R/W; bitpos: [9:0]; default: 96;
-         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
-         *  this register value.
-         */
-        uint32_t rxfifo_full_thrhd:10;
-        /** txfifo_empty_thrhd : R/W; bitpos: [19:10]; default: 96;
-         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
-         *  than this register value.
-         */
-        uint32_t txfifo_empty_thrhd:10;
-        /** dis_rx_dat_ovf : R/W; bitpos: [20]; default: 0;
-         *  Disable UART Rx data overflow detect.
-         */
-        uint32_t dis_rx_dat_ovf:1;
-        /** rx_tout_flow_dis : R/W; bitpos: [21]; default: 0;
-         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-         */
-        uint32_t rx_tout_flow_dis:1;
-        /** rx_flow_en : R/W; bitpos: [22]; default: 0;
-         *  This is the flow enable bit for UART receiver.
-         */
-        uint32_t rx_flow_en:1;
-        /** rx_tout_en : R/W; bitpos: [23]; default: 0;
-         *  This is the enble bit for uart receiver's timeout function.
-         */
-        uint32_t rx_tout_en:1;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} uart_conf1_reg_t;
-
-/** Type of flow_conf register
- *  Software flow-control configuration
- */
-typedef union {
-    struct {
-        /** sw_flow_con_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to enable software flow control. It is used with register sw_xon or
-         *  sw_xoff.
-         */
-        uint32_t sw_flow_con_en:1;
-        /** xonoff_del : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to remove flow control char from the received data.
-         */
-        uint32_t xonoff_del:1;
-        /** force_xon : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to enable the transmitter to go on sending data.
-         */
-        uint32_t force_xon:1;
-        /** force_xoff : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to stop the  transmitter from sending data.
-         */
-        uint32_t force_xoff:1;
-        /** send_xon : R/W/SS/SC; bitpos: [4]; default: 0;
-         *  Set this bit to send Xon char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xon:1;
-        /** send_xoff : R/W/SS/SC; bitpos: [5]; default: 0;
-         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
-         */
-        uint32_t send_xoff:1;
-        uint32_t reserved_6:26;
-    };
-    uint32_t val;
-} uart_flow_conf_reg_t;
-
-/** Type of sleep_conf register
- *  Sleep-mode configuration
- */
-typedef union {
-    struct {
-        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
-         *  The uart is activated from light sleeping mode when the input rxd edge changes more
-         *  times than this register value.
-         */
-        uint32_t active_threshold:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_sleep_conf_reg_t;
-
-/** Type of swfc_conf0 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xoff_threshold : R/W; bitpos: [9:0]; default: 224;
-         *  When the data amount in Rx-FIFO is more than this register value with
-         *  uart_sw_flow_con_en set to 1, it will send a Xoff char.
-         */
-        uint32_t xoff_threshold:10;
-        /** xoff_char : R/W; bitpos: [17:10]; default: 19;
-         *  This register stores the Xoff flow control char.
-         */
-        uint32_t xoff_char:8;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} uart_swfc_conf0_reg_t;
-
-/** Type of swfc_conf1 register
- *  Software flow-control character configuration
- */
-typedef union {
-    struct {
-        /** xon_threshold : R/W; bitpos: [9:0]; default: 0;
-         *  When the data amount in Rx-FIFO is less than this register value with
-         *  uart_sw_flow_con_en set to 1, it will send a Xon char.
-         */
-        uint32_t xon_threshold:10;
-        /** xon_char : R/W; bitpos: [17:10]; default: 17;
-         *  This register stores the Xon flow control char.
-         */
-        uint32_t xon_char:8;
-        uint32_t reserved_18:14;
-    };
-    uint32_t val;
-} uart_swfc_conf1_reg_t;
-
-/** Type of txbrk_conf register
- *  Tx Break character configuration
- */
-typedef union {
-    struct {
-        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
-         *  This register is used to configure the number of 0 to be sent after the process of
-         *  sending data is done. It is active when txd_brk is set to 1.
-         */
-        uint32_t tx_brk_num:8;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_txbrk_conf_reg_t;
-
-/** Type of idle_conf register
- *  Frame-end idle configuration
- */
-typedef union {
-    struct {
-        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
-         *  It will produce frame end signal when receiver takes more time to receive one byte
-         *  data than this register value.
-         */
-        uint32_t rx_idle_thrhd:10;
-        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
-         *  This register is used to configure the duration time between transfers.
-         */
-        uint32_t tx_idle_num:10;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} uart_idle_conf_reg_t;
-
-/** Type of rs485_conf register
- *  RS485 mode configuration
- */
-typedef union {
-    struct {
-        /** rs485_en : R/W; bitpos: [0]; default: 0;
-         *  Set this bit to choose the rs485 mode.
-         */
-        uint32_t rs485_en:1;
-        /** dl0_en : R/W; bitpos: [1]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl0_en:1;
-        /** dl1_en : R/W; bitpos: [2]; default: 0;
-         *  Set this bit to delay the stop bit by 1 bit.
-         */
-        uint32_t dl1_en:1;
-        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
-         *  Set this bit to enable receiver could receive data when the transmitter is
-         *  transmitting data in rs485 mode.
-         */
-        uint32_t rs485tx_rx_en:1;
-        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
-         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-         */
-        uint32_t rs485rxby_tx_en:1;
-        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
-         *  This register is used to delay the receiver's internal data signal.
-         */
-        uint32_t rs485_rx_dly_num:1;
-        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
-         *  This register is used to delay the transmitter's internal data signal.
-         */
-        uint32_t rs485_tx_dly_num:4;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rs485_conf_reg_t;
-
-/** Type of clk_conf register
- *  UART core clock configuration
- */
-typedef union {
-    struct {
-        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
-         *  The  denominator of the frequency divider factor.
-         */
-        uint32_t sclk_div_b:6;
-        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
-         *  The numerator of the frequency divider factor.
-         */
-        uint32_t sclk_div_a:6;
-        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
-         *  The integral part of the frequency divider factor.
-         */
-        uint32_t sclk_div_num:8;
-        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
-         *  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
-         */
-        uint32_t sclk_sel:2;
-        /** sclk_en : R/W; bitpos: [22]; default: 1;
-         *  Set this bit to enable UART Tx/Rx clock.
-         */
-        uint32_t sclk_en:1;
-        /** rst_core : R/W; bitpos: [23]; default: 0;
-         *  Write 1 then write 0 to this bit, reset UART Tx/Rx.
-         */
-        uint32_t rst_core:1;
-        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
-         *  Set this bit to enable UART Tx clock.
-         */
-        uint32_t tx_sclk_en:1;
-        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
-         *  Set this bit to enable UART Rx clock.
-         */
-        uint32_t rx_sclk_en:1;
-        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
-         *  Write 1 then write 0 to this bit, reset UART Tx.
-         */
-        uint32_t tx_rst_core:1;
-        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
-         *  Write 1 then write 0 to this bit, reset UART Rx.
-         */
-        uint32_t rx_rst_core:1;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} uart_clk_conf_reg_t;
-
-
-/** Group: Status Register */
-/** Type of status register
- *  UART status register
- */
-typedef union {
-    struct {
-        /** rxfifo_cnt : RO; bitpos: [9:0]; default: 0;
-         *  Stores the byte number of valid data in Rx-FIFO.
-         */
-        uint32_t rxfifo_cnt:10;
-        uint32_t reserved_10:3;
-        /** dsrn : RO; bitpos: [13]; default: 0;
-         *  The register represent the level value of the internal uart dsr signal.
-         */
-        uint32_t dsrn:1;
-        /** ctsn : RO; bitpos: [14]; default: 1;
-         *  This register represent the level value of the internal uart cts signal.
-         */
-        uint32_t ctsn:1;
-        /** rxd : RO; bitpos: [15]; default: 1;
-         *  This register represent the  level value of the internal uart rxd signal.
-         */
-        uint32_t rxd:1;
-        /** txfifo_cnt : RO; bitpos: [25:16]; default: 0;
-         *  Stores the byte number of data in Tx-FIFO.
-         */
-        uint32_t txfifo_cnt:10;
-        uint32_t reserved_26:3;
-        /** dtrn : RO; bitpos: [29]; default: 1;
-         *  This bit represents the level of the internal uart dtr signal.
-         */
-        uint32_t dtrn:1;
-        /** rtsn : RO; bitpos: [30]; default: 1;
-         *  This bit represents the level of the internal uart rts signal.
-         */
-        uint32_t rtsn:1;
-        /** txd : RO; bitpos: [31]; default: 1;
-         *  This bit represents the  level of the internal uart txd signal.
-         */
-        uint32_t txd:1;
-    };
-    uint32_t val;
-} uart_status_reg_t;
-
-/** Type of mem_tx_status register
- *  Tx-FIFO write and read offset address.
- */
-typedef union {
-    struct {
-        /** apb_tx_waddr : RO; bitpos: [9:0]; default: 0;
-         *  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via
-         *  APB.
-         */
-        uint32_t apb_tx_waddr:10;
-        uint32_t reserved_10:1;
-        /** tx_raddr : RO; bitpos: [20:11]; default: 0;
-         *  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
-         *  Tx-FIFO_Ctrl.
-         */
-        uint32_t tx_raddr:10;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} uart_mem_tx_status_reg_t;
-
-/** Type of mem_rx_status register
- *  Rx-FIFO write and read offset address.
- */
-typedef union {
-    struct {
-        /** apb_rx_raddr : RO; bitpos: [9:0]; default: 512;
-         *  This register stores the offset address in RX-FIFO when software reads data from
-         *  Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
-         */
-        uint32_t apb_rx_raddr:10;
-        uint32_t reserved_10:1;
-        /** rx_waddr : RO; bitpos: [20:11]; default: 512;
-         *  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
-         *  Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
-         */
-        uint32_t rx_waddr:10;
-        uint32_t reserved_21:11;
-    };
-    uint32_t val;
-} uart_mem_rx_status_reg_t;
-
-/** Type of fsm_status register
- *  UART transmit and receive status.
- */
-typedef union {
-    struct {
-        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
-         *  This is the status register of receiver.
-         */
-        uint32_t st_urx_out:4;
-        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
-         *  This is the status register of transmitter.
-         */
-        uint32_t st_utx_out:4;
-        uint32_t reserved_8:24;
-    };
-    uint32_t val;
-} uart_fsm_status_reg_t;
-
-
-/** Group: Autobaud Register */
-/** Type of lowpulse register
- *  Autobaud minimum low pulse duration register
- */
-typedef union {
-    struct {
-        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the value of the minimum duration time of the low level pulse.
-         *  It is used in baud rate-detect process.
-         */
-        uint32_t lowpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_lowpulse_reg_t;
-
-/** Type of highpulse register
- *  Autobaud minimum high pulse duration register
- */
-typedef union {
-    struct {
-        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores  the value of the maxinum duration time for the high level
-         *  pulse. It is used in baud rate-detect process.
-         */
-        uint32_t highpulse_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_highpulse_reg_t;
-
-/** Type of rxd_cnt register
- *  Autobaud edge change count register
- */
-typedef union {
-    struct {
-        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
-         *  This register stores the count of rxd edge change. It is used in baud rate-detect
-         *  process.
-         */
-        uint32_t rxd_edge_cnt:10;
-        uint32_t reserved_10:22;
-    };
-    uint32_t val;
-} uart_rxd_cnt_reg_t;
-
-/** Type of pospulse register
- *  Autobaud high pulse register
- */
-typedef union {
-    struct {
-        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two positive edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t posedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_pospulse_reg_t;
-
-/** Type of negpulse register
- *  Autobaud low pulse register
- */
-typedef union {
-    struct {
-        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
-         *  This register stores the minimal input clock count between two negative edges. It
-         *  is used in boudrate-detect process.
-         */
-        uint32_t negedge_min_cnt:12;
-        uint32_t reserved_12:20;
-    };
-    uint32_t val;
-} uart_negpulse_reg_t;
-
-
-/** Group: AT Escape Sequence Selection Configuration */
-/** Type of at_cmd_precnt register
- *  Pre-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the idle duration time before the first at_cmd
-         *  is received by receiver.
-         */
-        uint32_t pre_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_precnt_reg_t;
-
-/** Type of at_cmd_postcnt register
- *  Post-sequence timing configuration
- */
-typedef union {
-    struct {
-        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
-         *  This register is used to configure the duration time between the last at_cmd and
-         *  the next data.
-         */
-        uint32_t post_idle_num:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_postcnt_reg_t;
-
-/** Type of at_cmd_gaptout register
- *  Timeout configuration
- */
-typedef union {
-    struct {
-        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
-         *  This register is used to configure the duration time between the at_cmd chars.
-         */
-        uint32_t rx_gap_tout:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_gaptout_reg_t;
-
-/** Type of at_cmd_char register
- *  AT escape sequence detection configuration
- */
-typedef union {
-    struct {
-        /** at_cmd_char : R/W; bitpos: [7:0]; default: 43;
-         *  This register is used to configure the content of at_cmd char.
-         */
-        uint32_t at_cmd_char:8;
-        /** char_num : R/W; bitpos: [15:8]; default: 3;
-         *  This register is used to configure the num of continuous at_cmd chars received by
-         *  receiver.
-         */
-        uint32_t char_num:8;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} uart_at_cmd_char_reg_t;
-
-
-/** Group: Version Register */
-/** Type of date register
- *  UART Version register
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 33587824;
-         *  This is the version register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} uart_date_reg_t;
-
-/** Type of id register
- *  UART ID register
- */
-typedef union {
-    struct {
-        /** id : R/W; bitpos: [29:0]; default: 1280;
-         *  This register is used to configure the uart_id.
-         */
-        uint32_t id:30;
-        /** high_speed : R/W; bitpos: [30]; default: 1;
-         *  This bit used to select synchronize mode. 1: Registers are auto synchronized into
-         *  UART Core clock and UART core should be keep the same with APB clock. 0: After
-         *  configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize
-         *  registers.
-         */
-        uint32_t high_speed:1;
-        /** reg_update : R/W/SC; bitpos: [31]; default: 0;
-         *  Software write 1 would synchronize registers into UART Core clock domain and would
-         *  be cleared by hardware after synchronization is done.
-         */
-        uint32_t reg_update:1;
-    };
-    uint32_t val;
-} uart_id_reg_t;
-
-
-typedef struct {
-    volatile uart_fifo_reg_t fifo;
-    volatile uart_int_raw_reg_t int_raw;
-    volatile uart_int_st_reg_t int_st;
-    volatile uart_int_ena_reg_t int_ena;
-    volatile uart_int_clr_reg_t int_clr;
-    volatile uart_clkdiv_reg_t clkdiv;
-    volatile uart_rx_filt_reg_t rx_filt;
-    volatile uart_status_reg_t status;
-    volatile uart_conf0_reg_t conf0;
-    volatile uart_conf1_reg_t conf1;
-    volatile uart_lowpulse_reg_t lowpulse;
-    volatile uart_highpulse_reg_t highpulse;
-    volatile uart_rxd_cnt_reg_t rxd_cnt;
-    volatile uart_flow_conf_reg_t flow_conf;
-    volatile uart_sleep_conf_reg_t sleep_conf;
-    volatile uart_swfc_conf0_reg_t swfc_conf0;
-    volatile uart_swfc_conf1_reg_t swfc_conf1;
-    volatile uart_txbrk_conf_reg_t txbrk_conf;
-    volatile uart_idle_conf_reg_t idle_conf;
-    volatile uart_rs485_conf_reg_t rs485_conf;
-    volatile uart_at_cmd_precnt_reg_t at_cmd_precnt;
-    volatile uart_at_cmd_postcnt_reg_t at_cmd_postcnt;
-    volatile uart_at_cmd_gaptout_reg_t at_cmd_gaptout;
-    volatile uart_at_cmd_char_reg_t at_cmd_char;
-    volatile uart_mem_conf_reg_t mem_conf;
-    volatile uart_mem_tx_status_reg_t mem_tx_status;
-    volatile uart_mem_rx_status_reg_t mem_rx_status;
-    volatile uart_fsm_status_reg_t fsm_status;
-    volatile uart_pospulse_reg_t pospulse;
-    volatile uart_negpulse_reg_t negpulse;
-    volatile uart_clk_conf_reg_t clk_conf;
-    volatile uart_date_reg_t date;
-    volatile uart_id_reg_t id;
-} uart_dev_t;
-
-extern uart_dev_t UART0;
-extern uart_dev_t UART1;
-extern uart_dev_t UART2;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(uart_dev_t) == 0x84, "Invalid size of uart_dev_t structure");
-_Static_assert(sizeof(UART0.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
-_Static_assert(sizeof(UART1.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
-_Static_assert(sizeof(UART2.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/uhci_reg.h b/components/soc/esp32s3/include/soc/uhci_reg.h
deleted file mode 100644
index 280bafd55c7..00000000000
--- a/components/soc/esp32s3/include/soc/uhci_reg.h
+++ /dev/null
@@ -1,764 +0,0 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_UHCI_REG_H_
-#define _SOC_UHCI_REG_H_
-
-
-#include "soc.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
-/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_UART_RX_BRK_EOF_EN    (BIT(12))
-#define UHCI_UART_RX_BRK_EOF_EN_M  (BIT(12))
-#define UHCI_UART_RX_BRK_EOF_EN_V  0x1
-#define UHCI_UART_RX_BRK_EOF_EN_S  12
-/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_CLK_EN    (BIT(11))
-#define UHCI_CLK_EN_M  (BIT(11))
-#define UHCI_CLK_EN_V  0x1
-#define UHCI_CLK_EN_S  11
-/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_ENCODE_CRC_EN    (BIT(10))
-#define UHCI_ENCODE_CRC_EN_M  (BIT(10))
-#define UHCI_ENCODE_CRC_EN_V  0x1
-#define UHCI_ENCODE_CRC_EN_S  10
-/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_LEN_EOF_EN    (BIT(9))
-#define UHCI_LEN_EOF_EN_M  (BIT(9))
-#define UHCI_LEN_EOF_EN_V  0x1
-#define UHCI_LEN_EOF_EN_S  9
-/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_UART_IDLE_EOF_EN    (BIT(8))
-#define UHCI_UART_IDLE_EOF_EN_M  (BIT(8))
-#define UHCI_UART_IDLE_EOF_EN_V  0x1
-#define UHCI_UART_IDLE_EOF_EN_S  8
-/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_CRC_REC_EN    (BIT(7))
-#define UHCI_CRC_REC_EN_M  (BIT(7))
-#define UHCI_CRC_REC_EN_V  0x1
-#define UHCI_CRC_REC_EN_S  7
-/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_HEAD_EN    (BIT(6))
-#define UHCI_HEAD_EN_M  (BIT(6))
-#define UHCI_HEAD_EN_V  0x1
-#define UHCI_HEAD_EN_S  6
-/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_SEPER_EN    (BIT(5))
-#define UHCI_SEPER_EN_M  (BIT(5))
-#define UHCI_SEPER_EN_V  0x1
-#define UHCI_SEPER_EN_S  5
-/* UHCI_UART2_CE : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_UART2_CE    (BIT(4))
-#define UHCI_UART2_CE_M  (BIT(4))
-#define UHCI_UART2_CE_V  0x1
-#define UHCI_UART2_CE_S  4
-/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_UART1_CE    (BIT(3))
-#define UHCI_UART1_CE_M  (BIT(3))
-#define UHCI_UART1_CE_V  0x1
-#define UHCI_UART1_CE_S  3
-/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
-/*description: .*/
-#define UHCI_UART0_CE    (BIT(2))
-#define UHCI_UART0_CE_M  (BIT(2))
-#define UHCI_UART0_CE_V  0x1
-#define UHCI_UART0_CE_S  2
-/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_RST    (BIT(1))
-#define UHCI_RX_RST_M  (BIT(1))
-#define UHCI_RX_RST_V  0x1
-#define UHCI_RX_RST_S  1
-/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: .*/
-#define UHCI_TX_RST    (BIT(0))
-#define UHCI_TX_RST_M  (BIT(0))
-#define UHCI_TX_RST_V  0x1
-#define UHCI_TX_RST_S  0
-
-#define UHCI_INT_RAW_REG(i)          (REG_UHCI_BASE(i) + 0x4)
-/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL1_INT_RAW    (BIT(8))
-#define UHCI_APP_CTRL1_INT_RAW_M  (BIT(8))
-#define UHCI_APP_CTRL1_INT_RAW_V  0x1
-#define UHCI_APP_CTRL1_INT_RAW_S  8
-/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL0_INT_RAW    (BIT(7))
-#define UHCI_APP_CTRL0_INT_RAW_M  (BIT(7))
-#define UHCI_APP_CTRL0_INT_RAW_V  0x1
-#define UHCI_APP_CTRL0_INT_RAW_S  7
-/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW    (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S  6
-/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SEND_A_Q_INT_RAW    (BIT(5))
-#define UHCI_SEND_A_Q_INT_RAW_M  (BIT(5))
-#define UHCI_SEND_A_Q_INT_RAW_V  0x1
-#define UHCI_SEND_A_Q_INT_RAW_S  5
-/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SEND_S_Q_INT_RAW    (BIT(4))
-#define UHCI_SEND_S_Q_INT_RAW_M  (BIT(4))
-#define UHCI_SEND_S_Q_INT_RAW_V  0x1
-#define UHCI_SEND_S_Q_INT_RAW_S  4
-/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_HUNG_INT_RAW    (BIT(3))
-#define UHCI_TX_HUNG_INT_RAW_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_RAW_V  0x1
-#define UHCI_TX_HUNG_INT_RAW_S  3
-/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_HUNG_INT_RAW    (BIT(2))
-#define UHCI_RX_HUNG_INT_RAW_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_RAW_V  0x1
-#define UHCI_RX_HUNG_INT_RAW_S  2
-/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_START_INT_RAW    (BIT(1))
-#define UHCI_TX_START_INT_RAW_M  (BIT(1))
-#define UHCI_TX_START_INT_RAW_V  0x1
-#define UHCI_TX_START_INT_RAW_S  1
-/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_START_INT_RAW    (BIT(0))
-#define UHCI_RX_START_INT_RAW_M  (BIT(0))
-#define UHCI_RX_START_INT_RAW_V  0x1
-#define UHCI_RX_START_INT_RAW_S  0
-
-#define UHCI_INT_ST_REG(i)          (REG_UHCI_BASE(i) + 0x8)
-/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL1_INT_ST    (BIT(8))
-#define UHCI_APP_CTRL1_INT_ST_M  (BIT(8))
-#define UHCI_APP_CTRL1_INT_ST_V  0x1
-#define UHCI_APP_CTRL1_INT_ST_S  8
-/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL0_INT_ST    (BIT(7))
-#define UHCI_APP_CTRL0_INT_ST_M  (BIT(7))
-#define UHCI_APP_CTRL0_INT_ST_V  0x1
-#define UHCI_APP_CTRL0_INT_ST_S  7
-/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_OUTLINK_EOF_ERR_INT_ST    (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
-/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SEND_A_Q_INT_ST    (BIT(5))
-#define UHCI_SEND_A_Q_INT_ST_M  (BIT(5))
-#define UHCI_SEND_A_Q_INT_ST_V  0x1
-#define UHCI_SEND_A_Q_INT_ST_S  5
-/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SEND_S_Q_INT_ST    (BIT(4))
-#define UHCI_SEND_S_Q_INT_ST_M  (BIT(4))
-#define UHCI_SEND_S_Q_INT_ST_V  0x1
-#define UHCI_SEND_S_Q_INT_ST_S  4
-/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_HUNG_INT_ST    (BIT(3))
-#define UHCI_TX_HUNG_INT_ST_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_ST_V  0x1
-#define UHCI_TX_HUNG_INT_ST_S  3
-/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_HUNG_INT_ST    (BIT(2))
-#define UHCI_RX_HUNG_INT_ST_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_ST_V  0x1
-#define UHCI_RX_HUNG_INT_ST_S  2
-/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_START_INT_ST    (BIT(1))
-#define UHCI_TX_START_INT_ST_M  (BIT(1))
-#define UHCI_TX_START_INT_ST_V  0x1
-#define UHCI_TX_START_INT_ST_S  1
-/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_START_INT_ST    (BIT(0))
-#define UHCI_RX_START_INT_ST_M  (BIT(0))
-#define UHCI_RX_START_INT_ST_V  0x1
-#define UHCI_RX_START_INT_ST_S  0
-
-#define UHCI_INT_ENA_REG(i)          (REG_UHCI_BASE(i) + 0xC)
-/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL1_INT_ENA    (BIT(8))
-#define UHCI_APP_CTRL1_INT_ENA_M  (BIT(8))
-#define UHCI_APP_CTRL1_INT_ENA_V  0x1
-#define UHCI_APP_CTRL1_INT_ENA_S  8
-/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL0_INT_ENA    (BIT(7))
-#define UHCI_APP_CTRL0_INT_ENA_M  (BIT(7))
-#define UHCI_APP_CTRL0_INT_ENA_V  0x1
-#define UHCI_APP_CTRL0_INT_ENA_S  7
-/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA    (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
-/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SEND_A_Q_INT_ENA    (BIT(5))
-#define UHCI_SEND_A_Q_INT_ENA_M  (BIT(5))
-#define UHCI_SEND_A_Q_INT_ENA_V  0x1
-#define UHCI_SEND_A_Q_INT_ENA_S  5
-/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SEND_S_Q_INT_ENA    (BIT(4))
-#define UHCI_SEND_S_Q_INT_ENA_M  (BIT(4))
-#define UHCI_SEND_S_Q_INT_ENA_V  0x1
-#define UHCI_SEND_S_Q_INT_ENA_S  4
-/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_HUNG_INT_ENA    (BIT(3))
-#define UHCI_TX_HUNG_INT_ENA_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_ENA_V  0x1
-#define UHCI_TX_HUNG_INT_ENA_S  3
-/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_HUNG_INT_ENA    (BIT(2))
-#define UHCI_RX_HUNG_INT_ENA_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_ENA_V  0x1
-#define UHCI_RX_HUNG_INT_ENA_S  2
-/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_START_INT_ENA    (BIT(1))
-#define UHCI_TX_START_INT_ENA_M  (BIT(1))
-#define UHCI_TX_START_INT_ENA_V  0x1
-#define UHCI_TX_START_INT_ENA_S  1
-/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_START_INT_ENA    (BIT(0))
-#define UHCI_RX_START_INT_ENA_M  (BIT(0))
-#define UHCI_RX_START_INT_ENA_V  0x1
-#define UHCI_RX_START_INT_ENA_S  0
-
-#define UHCI_INT_CLR_REG(i)          (REG_UHCI_BASE(i) + 0x10)
-/* UHCI_APP_CTRL1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL1_INT_CLR    (BIT(8))
-#define UHCI_APP_CTRL1_INT_CLR_M  (BIT(8))
-#define UHCI_APP_CTRL1_INT_CLR_V  0x1
-#define UHCI_APP_CTRL1_INT_CLR_S  8
-/* UHCI_APP_CTRL0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL0_INT_CLR    (BIT(7))
-#define UHCI_APP_CTRL0_INT_CLR_M  (BIT(7))
-#define UHCI_APP_CTRL0_INT_CLR_V  0x1
-#define UHCI_APP_CTRL0_INT_CLR_S  7
-/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR    (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (BIT(6))
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x1
-#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
-/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SEND_A_Q_INT_CLR    (BIT(5))
-#define UHCI_SEND_A_Q_INT_CLR_M  (BIT(5))
-#define UHCI_SEND_A_Q_INT_CLR_V  0x1
-#define UHCI_SEND_A_Q_INT_CLR_S  5
-/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SEND_S_Q_INT_CLR    (BIT(4))
-#define UHCI_SEND_S_Q_INT_CLR_M  (BIT(4))
-#define UHCI_SEND_S_Q_INT_CLR_V  0x1
-#define UHCI_SEND_S_Q_INT_CLR_S  4
-/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_HUNG_INT_CLR    (BIT(3))
-#define UHCI_TX_HUNG_INT_CLR_M  (BIT(3))
-#define UHCI_TX_HUNG_INT_CLR_V  0x1
-#define UHCI_TX_HUNG_INT_CLR_S  3
-/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_HUNG_INT_CLR    (BIT(2))
-#define UHCI_RX_HUNG_INT_CLR_M  (BIT(2))
-#define UHCI_RX_HUNG_INT_CLR_V  0x1
-#define UHCI_RX_HUNG_INT_CLR_S  2
-/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_START_INT_CLR    (BIT(1))
-#define UHCI_TX_START_INT_CLR_M  (BIT(1))
-#define UHCI_TX_START_INT_CLR_V  0x1
-#define UHCI_TX_START_INT_CLR_S  1
-/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_START_INT_CLR    (BIT(0))
-#define UHCI_RX_START_INT_CLR_M  (BIT(0))
-#define UHCI_RX_START_INT_CLR_V  0x1
-#define UHCI_RX_START_INT_CLR_S  0
-
-#define UHCI_APP_INT_SET_REG(i)          (REG_UHCI_BASE(i) + 0x14)
-/* UHCI_APP_CTRL1_INT_SET : WO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL1_INT_SET    (BIT(1))
-#define UHCI_APP_CTRL1_INT_SET_M  (BIT(1))
-#define UHCI_APP_CTRL1_INT_SET_V  0x1
-#define UHCI_APP_CTRL1_INT_SET_S  1
-/* UHCI_APP_CTRL0_INT_SET : WO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_APP_CTRL0_INT_SET    (BIT(0))
-#define UHCI_APP_CTRL0_INT_SET_M  (BIT(0))
-#define UHCI_APP_CTRL0_INT_SET_V  0x1
-#define UHCI_APP_CTRL0_INT_SET_S  0
-
-#define UHCI_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x18)
-/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SW_START    (BIT(8))
-#define UHCI_SW_START_M  (BIT(8))
-#define UHCI_SW_START_V  0x1
-#define UHCI_SW_START_S  8
-/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_WAIT_SW_START    (BIT(7))
-#define UHCI_WAIT_SW_START_M  (BIT(7))
-#define UHCI_WAIT_SW_START_V  0x1
-#define UHCI_WAIT_SW_START_S  7
-/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_TX_ACK_NUM_RE    (BIT(5))
-#define UHCI_TX_ACK_NUM_RE_M  (BIT(5))
-#define UHCI_TX_ACK_NUM_RE_V  0x1
-#define UHCI_TX_ACK_NUM_RE_S  5
-/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_TX_CHECK_SUM_RE    (BIT(4))
-#define UHCI_TX_CHECK_SUM_RE_M  (BIT(4))
-#define UHCI_TX_CHECK_SUM_RE_V  0x1
-#define UHCI_TX_CHECK_SUM_RE_S  4
-/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SAVE_HEAD    (BIT(3))
-#define UHCI_SAVE_HEAD_M  (BIT(3))
-#define UHCI_SAVE_HEAD_V  0x1
-#define UHCI_SAVE_HEAD_S  3
-/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_CRC_DISABLE    (BIT(2))
-#define UHCI_CRC_DISABLE_M  (BIT(2))
-#define UHCI_CRC_DISABLE_V  0x1
-#define UHCI_CRC_DISABLE_S  2
-/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_CHECK_SEQ_EN    (BIT(1))
-#define UHCI_CHECK_SEQ_EN_M  (BIT(1))
-#define UHCI_CHECK_SEQ_EN_V  0x1
-#define UHCI_CHECK_SEQ_EN_S  1
-/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_CHECK_SUM_EN    (BIT(0))
-#define UHCI_CHECK_SUM_EN_M  (BIT(0))
-#define UHCI_CHECK_SUM_EN_V  0x1
-#define UHCI_CHECK_SUM_EN_S  0
-
-#define UHCI_STATE0_REG(i)          (REG_UHCI_BASE(i) + 0x1C)
-/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: .*/
-#define UHCI_DECODE_STATE    0x00000007
-#define UHCI_DECODE_STATE_M  ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
-#define UHCI_DECODE_STATE_V  0x7
-#define UHCI_DECODE_STATE_S  3
-/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: .*/
-#define UHCI_RX_ERR_CAUSE    0x00000007
-#define UHCI_RX_ERR_CAUSE_M  ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
-#define UHCI_RX_ERR_CAUSE_V  0x7
-#define UHCI_RX_ERR_CAUSE_S  0
-
-#define UHCI_STATE1_REG(i)          (REG_UHCI_BASE(i) + 0x20)
-/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: .*/
-#define UHCI_ENCODE_STATE    0x00000007
-#define UHCI_ENCODE_STATE_M  ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
-#define UHCI_ENCODE_STATE_V  0x7
-#define UHCI_ENCODE_STATE_S  0
-
-#define UHCI_ESCAPE_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x24)
-/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_13_ESC_EN    (BIT(7))
-#define UHCI_RX_13_ESC_EN_M  (BIT(7))
-#define UHCI_RX_13_ESC_EN_V  0x1
-#define UHCI_RX_13_ESC_EN_S  7
-/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_RX_11_ESC_EN    (BIT(6))
-#define UHCI_RX_11_ESC_EN_M  (BIT(6))
-#define UHCI_RX_11_ESC_EN_V  0x1
-#define UHCI_RX_11_ESC_EN_S  6
-/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_RX_DB_ESC_EN    (BIT(5))
-#define UHCI_RX_DB_ESC_EN_M  (BIT(5))
-#define UHCI_RX_DB_ESC_EN_V  0x1
-#define UHCI_RX_DB_ESC_EN_S  5
-/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_RX_C0_ESC_EN    (BIT(4))
-#define UHCI_RX_C0_ESC_EN_M  (BIT(4))
-#define UHCI_RX_C0_ESC_EN_V  0x1
-#define UHCI_RX_C0_ESC_EN_S  4
-/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_13_ESC_EN    (BIT(3))
-#define UHCI_TX_13_ESC_EN_M  (BIT(3))
-#define UHCI_TX_13_ESC_EN_V  0x1
-#define UHCI_TX_13_ESC_EN_S  3
-/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_TX_11_ESC_EN    (BIT(2))
-#define UHCI_TX_11_ESC_EN_M  (BIT(2))
-#define UHCI_TX_11_ESC_EN_V  0x1
-#define UHCI_TX_11_ESC_EN_S  2
-/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_TX_DB_ESC_EN    (BIT(1))
-#define UHCI_TX_DB_ESC_EN_M  (BIT(1))
-#define UHCI_TX_DB_ESC_EN_V  0x1
-#define UHCI_TX_DB_ESC_EN_S  1
-/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_TX_C0_ESC_EN    (BIT(0))
-#define UHCI_TX_C0_ESC_EN_M  (BIT(0))
-#define UHCI_TX_C0_ESC_EN_V  0x1
-#define UHCI_TX_C0_ESC_EN_S  0
-
-#define UHCI_HUNG_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x28)
-/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_RXFIFO_TIMEOUT_ENA    (BIT(23))
-#define UHCI_RXFIFO_TIMEOUT_ENA_M  (BIT(23))
-#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x1
-#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
-/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
-/*description: .*/
-#define UHCI_RXFIFO_TIMEOUT_SHIFT    0x00000007
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x7
-#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
-/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
-/*description: .*/
-#define UHCI_RXFIFO_TIMEOUT    0x000000FF
-#define UHCI_RXFIFO_TIMEOUT_M  ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
-#define UHCI_RXFIFO_TIMEOUT_V  0xFF
-#define UHCI_RXFIFO_TIMEOUT_S  12
-/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_TXFIFO_TIMEOUT_ENA    (BIT(11))
-#define UHCI_TXFIFO_TIMEOUT_ENA_M  (BIT(11))
-#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x1
-#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
-/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
-/*description: .*/
-#define UHCI_TXFIFO_TIMEOUT_SHIFT    0x00000007
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x7
-#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
-/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
-/*description: .*/
-#define UHCI_TXFIFO_TIMEOUT    0x000000FF
-#define UHCI_TXFIFO_TIMEOUT_M  ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
-#define UHCI_TXFIFO_TIMEOUT_V  0xFF
-#define UHCI_TXFIFO_TIMEOUT_S  0
-
-#define UHCI_ACK_NUM_REG(i)          (REG_UHCI_BASE(i) + 0x2C)
-/* UHCI_ACK_NUM_LOAD : WO ;bitpos:[3] ;default: 1'b1 ; */
-/*description: .*/
-#define UHCI_ACK_NUM_LOAD    (BIT(3))
-#define UHCI_ACK_NUM_LOAD_M  (BIT(3))
-#define UHCI_ACK_NUM_LOAD_V  0x1
-#define UHCI_ACK_NUM_LOAD_S  3
-/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: .*/
-#define UHCI_ACK_NUM    0x00000007
-#define UHCI_ACK_NUM_M  ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S))
-#define UHCI_ACK_NUM_V  0x7
-#define UHCI_ACK_NUM_S  0
-
-#define UHCI_RX_HEAD_REG(i)          (REG_UHCI_BASE(i) + 0x30)
-/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_RX_HEAD    0xFFFFFFFF
-#define UHCI_RX_HEAD_M  ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
-#define UHCI_RX_HEAD_V  0xFFFFFFFF
-#define UHCI_RX_HEAD_S  0
-
-#define UHCI_QUICK_SENT_REG(i)          (REG_UHCI_BASE(i) + 0x34)
-/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_ALWAYS_SEND_EN    (BIT(7))
-#define UHCI_ALWAYS_SEND_EN_M  (BIT(7))
-#define UHCI_ALWAYS_SEND_EN_V  0x1
-#define UHCI_ALWAYS_SEND_EN_S  7
-/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
-/*description: .*/
-#define UHCI_ALWAYS_SEND_NUM    0x00000007
-#define UHCI_ALWAYS_SEND_NUM_M  ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
-#define UHCI_ALWAYS_SEND_NUM_V  0x7
-#define UHCI_ALWAYS_SEND_NUM_S  4
-/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: .*/
-#define UHCI_SINGLE_SEND_EN    (BIT(3))
-#define UHCI_SINGLE_SEND_EN_M  (BIT(3))
-#define UHCI_SINGLE_SEND_EN_V  0x1
-#define UHCI_SINGLE_SEND_EN_S  3
-/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
-/*description: .*/
-#define UHCI_SINGLE_SEND_NUM    0x00000007
-#define UHCI_SINGLE_SEND_NUM_M  ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
-#define UHCI_SINGLE_SEND_NUM_V  0x7
-#define UHCI_SINGLE_SEND_NUM_S  0
-
-#define UHCI_Q0_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x38)
-/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q0_WORD0    0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD0_M  ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
-#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD0_S  0
-
-#define UHCI_Q0_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x3C)
-/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q0_WORD1    0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD1_M  ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
-#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q0_WORD1_S  0
-
-#define UHCI_Q1_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x40)
-/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q1_WORD0    0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD0_M  ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
-#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD0_S  0
-
-#define UHCI_Q1_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x44)
-/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q1_WORD1    0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD1_M  ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
-#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q1_WORD1_S  0
-
-#define UHCI_Q2_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x48)
-/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q2_WORD0    0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD0_M  ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
-#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD0_S  0
-
-#define UHCI_Q2_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x4C)
-/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q2_WORD1    0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD1_M  ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
-#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q2_WORD1_S  0
-
-#define UHCI_Q3_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x50)
-/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q3_WORD0    0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD0_M  ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
-#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD0_S  0
-
-#define UHCI_Q3_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x54)
-/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q3_WORD1    0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD1_M  ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
-#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q3_WORD1_S  0
-
-#define UHCI_Q4_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x58)
-/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q4_WORD0    0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD0_M  ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
-#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD0_S  0
-
-#define UHCI_Q4_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x5C)
-/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q4_WORD1    0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD1_M  ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
-#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q4_WORD1_S  0
-
-#define UHCI_Q5_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x60)
-/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q5_WORD0    0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD0_M  ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
-#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD0_S  0
-
-#define UHCI_Q5_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x64)
-/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q5_WORD1    0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD1_M  ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
-#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q5_WORD1_S  0
-
-#define UHCI_Q6_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x68)
-/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q6_WORD0    0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD0_M  ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
-#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD0_S  0
-
-#define UHCI_Q6_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x6C)
-/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: .*/
-#define UHCI_SEND_Q6_WORD1    0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD1_M  ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
-#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFF
-#define UHCI_SEND_Q6_WORD1_S  0
-
-#define UHCI_ESC_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x70)
-/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
-/*description: .*/
-#define UHCI_SEPER_ESC_CHAR1    0x000000FF
-#define UHCI_SEPER_ESC_CHAR1_M  ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
-#define UHCI_SEPER_ESC_CHAR1_V  0xFF
-#define UHCI_SEPER_ESC_CHAR1_S  16
-/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: .*/
-#define UHCI_SEPER_ESC_CHAR0    0x000000FF
-#define UHCI_SEPER_ESC_CHAR0_M  ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
-#define UHCI_SEPER_ESC_CHAR0_V  0xFF
-#define UHCI_SEPER_ESC_CHAR0_S  8
-/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
-/*description: .*/
-#define UHCI_SEPER_CHAR    0x000000FF
-#define UHCI_SEPER_CHAR_M  ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
-#define UHCI_SEPER_CHAR_V  0xFF
-#define UHCI_SEPER_CHAR_S  0
-
-#define UHCI_ESC_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x74)
-/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
-/*description: .*/
-#define UHCI_ESC_SEQ0_CHAR1    0x000000FF
-#define UHCI_ESC_SEQ0_CHAR1_M  ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
-#define UHCI_ESC_SEQ0_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ0_CHAR1_S  16
-/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: .*/
-#define UHCI_ESC_SEQ0_CHAR0    0x000000FF
-#define UHCI_ESC_SEQ0_CHAR0_M  ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
-#define UHCI_ESC_SEQ0_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ0_CHAR0_S  8
-/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
-/*description: .*/
-#define UHCI_ESC_SEQ0    0x000000FF
-#define UHCI_ESC_SEQ0_M  ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
-#define UHCI_ESC_SEQ0_V  0xFF
-#define UHCI_ESC_SEQ0_S  0
-
-#define UHCI_ESC_CONF2_REG(i)          (REG_UHCI_BASE(i) + 0x78)
-/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
-/*description: .*/
-#define UHCI_ESC_SEQ1_CHAR1    0x000000FF
-#define UHCI_ESC_SEQ1_CHAR1_M  ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
-#define UHCI_ESC_SEQ1_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ1_CHAR1_S  16
-/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: .*/
-#define UHCI_ESC_SEQ1_CHAR0    0x000000FF
-#define UHCI_ESC_SEQ1_CHAR0_M  ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
-#define UHCI_ESC_SEQ1_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ1_CHAR0_S  8
-/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
-/*description: .*/
-#define UHCI_ESC_SEQ1    0x000000FF
-#define UHCI_ESC_SEQ1_M  ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
-#define UHCI_ESC_SEQ1_V  0xFF
-#define UHCI_ESC_SEQ1_S  0
-
-#define UHCI_ESC_CONF3_REG(i)          (REG_UHCI_BASE(i) + 0x7C)
-/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
-/*description: .*/
-#define UHCI_ESC_SEQ2_CHAR1    0x000000FF
-#define UHCI_ESC_SEQ2_CHAR1_M  ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
-#define UHCI_ESC_SEQ2_CHAR1_V  0xFF
-#define UHCI_ESC_SEQ2_CHAR1_S  16
-/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
-/*description: .*/
-#define UHCI_ESC_SEQ2_CHAR0    0x000000FF
-#define UHCI_ESC_SEQ2_CHAR0_M  ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
-#define UHCI_ESC_SEQ2_CHAR0_V  0xFF
-#define UHCI_ESC_SEQ2_CHAR0_S  8
-/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
-/*description: .*/
-#define UHCI_ESC_SEQ2    0x000000FF
-#define UHCI_ESC_SEQ2_M  ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
-#define UHCI_ESC_SEQ2_V  0xFF
-#define UHCI_ESC_SEQ2_S  0
-
-#define UHCI_PKT_THRES_REG(i)          (REG_UHCI_BASE(i) + 0x80)
-/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
-/*description: .*/
-#define UHCI_PKT_THRS    0x00001FFF
-#define UHCI_PKT_THRS_M  ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
-#define UHCI_PKT_THRS_V  0x1FFF
-#define UHCI_PKT_THRS_S  0
-
-#define UHCI_DATE_REG(i)          (REG_UHCI_BASE(i) + 0x84)
-/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2010090 ; */
-/*description: .*/
-#define UHCI_DATE    0xFFFFFFFF
-#define UHCI_DATE_M  ((UHCI_DATE_V)<<(UHCI_DATE_S))
-#define UHCI_DATE_V  0xFFFFFFFF
-#define UHCI_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_UHCI_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/usb_dwc_struct.h b/components/soc/esp32s3/include/soc/usb_dwc_struct.h
index 5fd5800715e..1910ca20493 100644
--- a/components/soc/esp32s3/include/soc/usb_dwc_struct.h
+++ b/components/soc/esp32s3/include/soc/usb_dwc_struct.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,7 +33,7 @@ typedef union {
         uint32_t hnpreq: 1;
         uint32_t hstsethnpen: 1;
         uint32_t devhnpen: 1;
-        uint32_t ehen: 1;
+        uint32_t ehen: 1;       // codespell:ignore ehen
         uint32_t reserved_13: 2;
         uint32_t dbncefltrbypass: 1;
         uint32_t conidsts: 1;
@@ -88,7 +88,7 @@ typedef union {
     struct {
         uint32_t toutcal: 3;
         uint32_t phyif: 1;
-        uint32_t reserved_4: 1;
+        uint32_t ulpiutmisel: 1;
         uint32_t fsintf: 1;
         uint32_t physel: 1;
         uint32_t reserved_7: 1;
diff --git a/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h b/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h
deleted file mode 100644
index 5774f2d711a..00000000000
--- a/components/soc/esp32s3/include/soc/usb_serial_jtag_reg.h
+++ /dev/null
@@ -1,732 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-#define USB_SERIAL_JTAG_EP1_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
-/* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE
-VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into
-UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB
-_DEVICE_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is rece
-ived, then read data from UART Rx FIFO..*/
-#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FF
-#define USB_SERIAL_JTAG_RDWR_BYTE_M  ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S))
-#define USB_SERIAL_JTAG_RDWR_BYTE_V  0xFF
-#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
-
-#define USB_SERIAL_JTAG_EP1_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
-/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: 1'b1: Indicate there is data in UART Rx FIFO..*/
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
-/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */
-/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin
-g USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
-USB Host..*/
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (BIT(1))
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
-/* USB_SERIAL_JTAG_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done..*/
-#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_M  (BIT(0))
-#define USB_SERIAL_JTAG_WR_DONE_V  0x1
-#define USB_SERIAL_JTAG_WR_DONE_S  0
-
-#define USB_SERIAL_JTAG_INT_RAW_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
-/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi
-th zero palyload..*/
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
-/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet wi
-th zero palyload..*/
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
-/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when usb bus reset is detected..*/
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
-/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is rec
-eived..*/
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
-/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when stuff error is detected..*/
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
-/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when CRC16 error is detected..*/
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
-/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when CRC5 error is detected..*/
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
-/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when pid error is detected..*/
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
-/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */
-/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty..*/
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
-/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
- one packet..*/
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
-/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when SOF frame is received..*/
-#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
-/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp
-oint 2 of JTAG..*/
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x1
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
-
-#define USB_SERIAL_JTAG_INT_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0xC)
-/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interru
-pt..*/
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
-/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interru
-pt..*/
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
-/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
-/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrup
-t..*/
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
-/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
-/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
-/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
-/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
-/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
-/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrup
-t..*/
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
-/* USB_SERIAL_JTAG_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt..*/
-#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_M  (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
-/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x1
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
-
-#define USB_SERIAL_JTAG_INT_ENA_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
-/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
-/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
-/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
-/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt..*/
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
-/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
-/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
-/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
-/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
-/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
-/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt..*/
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
-/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt..*/
-#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
-/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x1
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
-
-#define USB_SERIAL_JTAG_INT_CLR_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
-/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (BIT(11))
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
-/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (BIT(10))
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
-/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (BIT(9))
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
-/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt..*/
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (BIT(8))
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
-/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (BIT(7))
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
-/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (BIT(6))
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
-/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (BIT(5))
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
-/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (BIT(4))
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
-/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (BIT(3))
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
-/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt..*/
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (BIT(2))
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
-/* USB_SERIAL_JTAG_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt..*/
-#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (BIT(1))
-#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
-/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (BIT(0))
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x1
-#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
-
-#define USB_SERIAL_JTAG_CONF0_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
-/* USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
-/*description: Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disc
-onnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input thr
-ough GPIO Matrix..*/
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(16))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (BIT(16))
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x1
-#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  16
-/* USB_SERIAL_JTAG_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
-/*description: 0: TX output at clock negedge. 1: Tx output at clock posedge..*/
-#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL    (BIT(15))
-#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_M  (BIT(15))
-#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V  0x1
-#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S  15
-/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */
-/*description: Enable USB pad function..*/
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (BIT(14))
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x1
-#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
-/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */
-/*description: Control pull up value..*/
-#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (BIT(13))
-#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x1
-#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
-/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */
-/*description: Control USB D- pull down..*/
-#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (BIT(12))
-#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x1
-#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
-/* USB_SERIAL_JTAG_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Control USB D- pull up..*/
-#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_M  (BIT(11))
-#define USB_SERIAL_JTAG_DM_PULLUP_V  0x1
-#define USB_SERIAL_JTAG_DM_PULLUP_S  11
-/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Control USB D+ pull down..*/
-#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (BIT(10))
-#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x1
-#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
-/* USB_SERIAL_JTAG_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */
-/*description: Control USB D+ pull up..*/
-#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_M  (BIT(9))
-#define USB_SERIAL_JTAG_DP_PULLUP_V  0x1
-#define USB_SERIAL_JTAG_DP_PULLUP_S  9
-/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Enable software control USB D+ D- pullup pulldown.*/
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (BIT(8))
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x1
-#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
-/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Enable software control input  threshold.*/
-#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (BIT(7))
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x1
-#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
-/* USB_SERIAL_JTAG_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
-/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/
-#define USB_SERIAL_JTAG_VREFL    0x00000003
-#define USB_SERIAL_JTAG_VREFL_M  ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S))
-#define USB_SERIAL_JTAG_VREFL_V  0x3
-#define USB_SERIAL_JTAG_VREFL_S  5
-/* USB_SERIAL_JTAG_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/
-#define USB_SERIAL_JTAG_VREFH    0x00000003
-#define USB_SERIAL_JTAG_VREFH_M  ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S))
-#define USB_SERIAL_JTAG_VREFH_V  0x3
-#define USB_SERIAL_JTAG_VREFH_S  3
-/* USB_SERIAL_JTAG_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: USB D+ D- exchange.*/
-#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_M  (BIT(2))
-#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x1
-#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
-/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Enable software control USB D+ D- exchange.*/
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (BIT(1))
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x1
-#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
-/* USB_SERIAL_JTAG_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Select internal/external PHY.*/
-#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_M  (BIT(0))
-#define USB_SERIAL_JTAG_PHY_SEL_V  0x1
-#define USB_SERIAL_JTAG_PHY_SEL_S  0
-
-#define USB_SERIAL_JTAG_TEST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x1C)
-/* USB_SERIAL_JTAG_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: USB D- rx value in test.*/
-#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_M  (BIT(6))
-#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x1
-#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
-/* USB_SERIAL_JTAG_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: USB D+ rx value in test.*/
-#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_M  (BIT(5))
-#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x1
-#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
-/* USB_SERIAL_JTAG_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: USB differential rx value in test.*/
-#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (BIT(4))
-#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x1
-#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
-/* USB_SERIAL_JTAG_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: USB D- tx value in test.*/
-#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_M  (BIT(3))
-#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x1
-#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
-/* USB_SERIAL_JTAG_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: USB D+ tx value in test.*/
-#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_M  (BIT(2))
-#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x1
-#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
-/* USB_SERIAL_JTAG_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: USB pad oen in test.*/
-#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_M  (BIT(1))
-#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x1
-#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
-/* USB_SERIAL_JTAG_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Enable test of the USB pad.*/
-#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_M  (BIT(0))
-#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x1
-#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
-
-#define USB_SERIAL_JTAG_JFIFO_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
-/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Write 1 to reset JTAG out fifo..*/
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (BIT(9))
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x1
-#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
-/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Write 1 to reset JTAG in fifo..*/
-#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (BIT(8))
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x1
-#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
-/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: 1: JTAG out fifo is full..*/
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (BIT(7))
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x1
-#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
-/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */
-/*description: 1: JTAG out fifo is empty..*/
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (BIT(6))
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x1
-#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
-/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */
-/*description: JTAT out fifo counter..*/
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S))
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x3
-#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
-/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: 1: JTAG in fifo is full..*/
-#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (BIT(3))
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x1
-#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
-/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */
-/*description: 1: JTAG in fifo is empty..*/
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (BIT(2))
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x1
-#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
-/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */
-/*description: JTAT in fifo counter..*/
-#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S))
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x3
-#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
-
-#define USB_SERIAL_JTAG_FRAM_NUM_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
-/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */
-/*description: Frame index of received SOF frame..*/
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FF
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S))
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x7FF
-#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
-
-#define USB_SERIAL_JTAG_IN_EP0_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
-/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of IN endpoint 0..*/
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S))
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
-/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of IN endpoint 0..*/
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S))
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: State of IN Endpoint 0..*/
-#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003
-#define USB_SERIAL_JTAG_IN_EP0_STATE_M  ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S))
-#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x3
-#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
-
-#define USB_SERIAL_JTAG_IN_EP1_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x2C)
-/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of IN endpoint 1..*/
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S))
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
-/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of IN endpoint 1..*/
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S))
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: State of IN Endpoint 1..*/
-#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003
-#define USB_SERIAL_JTAG_IN_EP1_STATE_M  ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S))
-#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x3
-#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
-
-#define USB_SERIAL_JTAG_IN_EP2_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
-/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of IN endpoint 2..*/
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S))
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
-/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of IN endpoint 2..*/
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S))
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: State of IN Endpoint 2..*/
-#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003
-#define USB_SERIAL_JTAG_IN_EP2_STATE_M  ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S))
-#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x3
-#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
-
-#define USB_SERIAL_JTAG_IN_EP3_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
-/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of IN endpoint 3..*/
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S))
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
-/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of IN endpoint 3..*/
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S))
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
-/*description: State of IN Endpoint 3..*/
-#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003
-#define USB_SERIAL_JTAG_IN_EP3_STATE_M  ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S))
-#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x3
-#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
-
-#define USB_SERIAL_JTAG_OUT_EP0_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
-/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of OUT endpoint 0..*/
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S))
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
-/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
- detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0..*/
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S))
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: State of OUT Endpoint 0..*/
-#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S))
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x3
-#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
-
-#define USB_SERIAL_JTAG_OUT_EP1_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x3C)
-/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */
-/*description: Data count in OUT endpoint 1 when one packet is received..*/
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S))
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x7F
-#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
-/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of OUT endpoint 1..*/
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S))
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
-/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
- detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S))
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: State of OUT Endpoint 1..*/
-#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S))
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x3
-#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
-
-#define USB_SERIAL_JTAG_OUT_EP2_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
-/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
-/*description: Read data address of OUT endpoint 2..*/
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S))
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
-/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
-/*description: Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
- detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007F
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S))
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x7F
-#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
-/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: State of OUT Endpoint 2..*/
-#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S))
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x3
-#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
-
-#define USB_SERIAL_JTAG_MISC_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
-/* USB_SERIAL_JTAG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
-tes registers..*/
-#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_M  (BIT(0))
-#define USB_SERIAL_JTAG_CLK_EN_V  0x1
-#define USB_SERIAL_JTAG_CLK_EN_S  0
-
-#define USB_SERIAL_JTAG_MEM_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
-/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: 1: Force clock on for usb memory..*/
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (BIT(1))
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x1
-#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
-/* USB_SERIAL_JTAG_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: 1: power down usb memory..*/
-#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_M  (BIT(0))
-#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x1
-#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
-
-#define USB_SERIAL_JTAG_DATE_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
-/* USB_SERIAL_JTAG_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101200 ; */
-/*description: register version..*/
-#define USB_SERIAL_JTAG_DATE    0xFFFFFFFF
-#define USB_SERIAL_JTAG_DATE_M  ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S))
-#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFF
-#define USB_SERIAL_JTAG_DATE_S  0
-
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h b/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
deleted file mode 100644
index 539717f267b..00000000000
--- a/components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
+++ /dev/null
@@ -1,267 +0,0 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
-#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "soc.h"
-
-typedef volatile struct usb_serial_jtag_dev_s {
-    union {
-        struct {
-            uint32_t rdwr_byte                 :    32;  /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.*/
-        };
-        uint32_t val;
-    } ep1;
-    union {
-        struct {
-            uint32_t wr_done                   :    1;  /*Set this bit to indicate writing byte data to UART Tx FIFO is done.*/
-            uint32_t serial_in_ep_data_free    :    1;  /*1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.*/
-            uint32_t serial_out_ep_data_avail  :    1;  /*1'b1: Indicate there is data in UART Rx FIFO.*/
-            uint32_t reserved3                     :    29;  /*reserved*/
-        };
-        uint32_t val;
-    } ep1_conf;
-    union {
-        struct {
-            uint32_t jtag_in_flush_int_raw     :    1;  /*The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.*/
-            uint32_t sof_int_raw               :    1;  /*The raw interrupt bit turns to high level when SOF frame is received.*/
-            uint32_t serial_out_recv_pkt_int_raw:    1;  /*The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.*/
-            uint32_t serial_in_empty_int_raw   :    1;  /*The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.*/
-            uint32_t pid_err_int_raw           :    1;  /*The raw interrupt bit turns to high level when pid error is detected.*/
-            uint32_t crc5_err_int_raw          :    1;  /*The raw interrupt bit turns to high level when CRC5 error is detected.*/
-            uint32_t crc16_err_int_raw         :    1;  /*The raw interrupt bit turns to high level when CRC16 error is detected.*/
-            uint32_t stuff_err_int_raw         :    1;  /*The raw interrupt bit turns to high level when stuff error is detected.*/
-            uint32_t in_token_rec_in_ep1_int_raw:    1;  /*The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.*/
-            uint32_t usb_bus_reset_int_raw     :    1;  /*The raw interrupt bit turns to high level when usb bus reset is detected.*/
-            uint32_t out_ep1_zero_payload_int_raw:    1;  /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.*/
-            uint32_t out_ep2_zero_payload_int_raw:    1;  /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t jtag_in_flush_int_st      :    1;  /*The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
-            uint32_t sof_int_st                :    1;  /*The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.*/
-            uint32_t serial_out_recv_pkt_int_st:    1;  /*The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
-            uint32_t serial_in_empty_int_st    :    1;  /*The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
-            uint32_t pid_err_int_st            :    1;  /*The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
-            uint32_t crc5_err_int_st           :    1;  /*The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/
-            uint32_t crc16_err_int_st          :    1;  /*The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
-            uint32_t stuff_err_int_st          :    1;  /*The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
-            uint32_t in_token_rec_in_ep1_int_st:    1;  /*The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
-            uint32_t usb_bus_reset_int_st      :    1;  /*The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
-            uint32_t out_ep1_zero_payload_int_st:    1;  /*The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t out_ep2_zero_payload_int_st:    1;  /*The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t jtag_in_flush_int_ena     :    1;  /*The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
-            uint32_t sof_int_ena               :    1;  /*The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.*/
-            uint32_t serial_out_recv_pkt_int_ena:    1;  /*The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
-            uint32_t serial_in_empty_int_ena   :    1;  /*The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
-            uint32_t pid_err_int_ena           :    1;  /*The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
-            uint32_t crc5_err_int_ena          :    1;  /*The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/
-            uint32_t crc16_err_int_ena         :    1;  /*The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
-            uint32_t stuff_err_int_ena         :    1;  /*The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
-            uint32_t in_token_rec_in_ep1_int_ena:    1;  /*The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
-            uint32_t usb_bus_reset_int_ena     :    1;  /*The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
-            uint32_t out_ep1_zero_payload_int_ena:    1;  /*The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t out_ep2_zero_payload_int_ena:    1;  /*The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t jtag_in_flush_int_clr     :    1;  /*Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
-            uint32_t sof_int_clr               :    1;  /*Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.*/
-            uint32_t serial_out_recv_pkt_int_clr:    1;  /*Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
-            uint32_t serial_in_empty_int_clr   :    1;  /*Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
-            uint32_t pid_err_int_clr           :    1;  /*Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.*/
-            uint32_t crc5_err_int_clr          :    1;  /*Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.*/
-            uint32_t crc16_err_int_clr         :    1;  /*Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.*/
-            uint32_t stuff_err_int_clr         :    1;  /*Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.*/
-            uint32_t in_token_rec_in_ep1_int_clr:    1;  /*Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.*/
-            uint32_t usb_bus_reset_int_clr     :    1;  /*Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
-            uint32_t out_ep1_zero_payload_int_clr:    1;  /*Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t out_ep2_zero_payload_int_clr:    1;  /*Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
-            uint32_t reserved12                    :    20;  /*reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    union {
-        struct {
-            uint32_t phy_sel                   :    1;  /*Select internal/external PHY*/
-            uint32_t exchg_pins_override       :    1;  /*Enable software control USB D+ D- exchange*/
-            uint32_t exchg_pins                :    1;  /*USB D+ D- exchange*/
-            uint32_t vrefh                     :    2;  /*Control single-end input high threshold,1.76V to 2V, step 80mV*/
-            uint32_t vrefl                     :    2;  /*Control single-end input low threshold,0.8V to 1.04V, step 80mV*/
-            uint32_t vref_override             :    1;  /*Enable software control input  threshold*/
-            uint32_t pad_pull_override         :    1;  /*Enable software control USB D+ D- pullup pulldown*/
-            uint32_t dp_pullup                 :    1;  /*Control USB D+ pull up.*/
-            uint32_t dp_pulldown               :    1;  /*Control USB D+ pull down.*/
-            uint32_t dm_pullup                 :    1;  /*Control USB D- pull up.*/
-            uint32_t dm_pulldown               :    1;  /*Control USB D- pull down.*/
-            uint32_t pullup_value              :    1;  /*Control pull up value.*/
-            uint32_t usb_pad_enable            :    1;  /*Enable USB pad function.*/
-            uint32_t phy_tx_edge_sel           :    1;  /*0: TX output at clock negedge. 1: Tx output at clock posedge.*/
-            uint32_t usb_jtag_bridge_en        :    1;  /*Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix.*/
-            uint32_t reserved17                    :    15;
-        };
-        uint32_t val;
-    } conf0;
-    union {
-        struct {
-            uint32_t test_enable               :    1;  /*Enable test of the USB pad*/
-            uint32_t test_usb_oe               :    1;  /*USB pad oen in test*/
-            uint32_t test_tx_dp                :    1;  /*USB D+ tx value in test*/
-            uint32_t test_tx_dm                :    1;  /*USB D- tx value in test*/
-            uint32_t test_rx_rcv               :    1;  /*USB differential rx value in test*/
-            uint32_t test_rx_dp                :    1;  /*USB D+ rx value in test*/
-            uint32_t test_rx_dm                :    1;  /*USB D- rx value in test*/
-            uint32_t reserved7                     :    25;
-        };
-        uint32_t val;
-    } test;
-    union {
-        struct {
-            uint32_t in_fifo_cnt               :    2;  /*JTAT in fifo counter.*/
-            uint32_t in_fifo_empty             :    1;  /*1: JTAG in fifo is empty.*/
-            uint32_t in_fifo_full              :    1;  /*1: JTAG in fifo is full.*/
-            uint32_t out_fifo_cnt              :    2;  /*JTAT out fifo counter.*/
-            uint32_t out_fifo_empty            :    1;  /*1: JTAG out fifo is empty.*/
-            uint32_t out_fifo_full             :    1;  /*1: JTAG out fifo is full.*/
-            uint32_t in_fifo_reset             :    1;  /*Write 1 to reset JTAG in fifo.*/
-            uint32_t out_fifo_reset            :    1;  /*Write 1 to reset JTAG out fifo.*/
-            uint32_t reserved10                    :    22;
-        };
-        uint32_t val;
-    } jfifo_st;
-    union {
-        struct {
-            uint32_t sof_frame_index           :    11;  /*Frame index of received SOF frame.*/
-            uint32_t reserved11                    :    21;
-        };
-        uint32_t val;
-    } fram_num;
-    union {
-        struct {
-            uint32_t in_ep0_state              :    2;  /*State of IN Endpoint 0.*/
-            uint32_t in_ep0_wr_addr            :    7;  /*Write data address of IN endpoint 0.*/
-            uint32_t in_ep0_rd_addr            :    7;  /*Read data address of IN endpoint 0.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } in_ep0_st;
-    union {
-        struct {
-            uint32_t in_ep1_state              :    2;  /*State of IN Endpoint 1.*/
-            uint32_t in_ep1_wr_addr            :    7;  /*Write data address of IN endpoint 1.*/
-            uint32_t in_ep1_rd_addr            :    7;  /*Read data address of IN endpoint 1.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } in_ep1_st;
-    union {
-        struct {
-            uint32_t in_ep2_state              :    2;  /*State of IN Endpoint 2.*/
-            uint32_t in_ep2_wr_addr            :    7;  /*Write data address of IN endpoint 2.*/
-            uint32_t in_ep2_rd_addr            :    7;  /*Read data address of IN endpoint 2.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } in_ep2_st;
-    union {
-        struct {
-            uint32_t in_ep3_state              :    2;  /*State of IN Endpoint 3.*/
-            uint32_t in_ep3_wr_addr            :    7;  /*Write data address of IN endpoint 3.*/
-            uint32_t in_ep3_rd_addr            :    7;  /*Read data address of IN endpoint 3.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } in_ep3_st;
-    union {
-        struct {
-            uint32_t out_ep0_state             :    2;  /*State of OUT Endpoint 0.*/
-            uint32_t out_ep0_wr_addr           :    7;  /*Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.*/
-            uint32_t out_ep0_rd_addr           :    7;  /*Read data address of OUT endpoint 0.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } out_ep0_st;
-    union {
-        struct {
-            uint32_t out_ep1_state             :    2;  /*State of OUT Endpoint 1.*/
-            uint32_t out_ep1_wr_addr           :    7;  /*Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
-            uint32_t out_ep1_rd_addr           :    7;  /*Read data address of OUT endpoint 1.*/
-            uint32_t out_ep1_rec_data_cnt      :    7;  /*Data count in OUT endpoint 1 when one packet is received.*/
-            uint32_t reserved23                    :    9;  /*reserved*/
-        };
-        uint32_t val;
-    } out_ep1_st;
-    union {
-        struct {
-            uint32_t out_ep2_state             :    2;  /*State of OUT Endpoint 2.*/
-            uint32_t out_ep2_wr_addr           :    7;  /*Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
-            uint32_t out_ep2_rd_addr           :    7;  /*Read data address of OUT endpoint 2.*/
-            uint32_t reserved16                    :    16;  /*reserved*/
-        };
-        uint32_t val;
-    } out_ep2_st;
-    union {
-        struct {
-            uint32_t clk_en                    :    1;  /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
-            uint32_t reserved1                     :    31;
-        };
-        uint32_t val;
-    } misc_conf;
-    union {
-        struct {
-            uint32_t usb_mem_pd                :    1;  /*1: power down usb memory.*/
-            uint32_t usb_mem_clk_en            :    1;  /*1: Force clock on for usb memory.*/
-            uint32_t reserved2                     :    30;
-        };
-        uint32_t val;
-    } mem_conf;
-    uint32_t reserved_4c;
-    uint32_t reserved_50;
-    uint32_t reserved_54;
-    uint32_t reserved_58;
-    uint32_t reserved_5c;
-    uint32_t reserved_60;
-    uint32_t reserved_64;
-    uint32_t reserved_68;
-    uint32_t reserved_6c;
-    uint32_t reserved_70;
-    uint32_t reserved_74;
-    uint32_t reserved_78;
-    uint32_t reserved_7c;
-    uint32_t date;
-} usb_serial_jtag_dev_t;
-extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
-#ifdef __cplusplus
-}
-#endif
-
-
-
-#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/usb_wrap_struct.h b/components/soc/esp32s3/include/soc/usb_wrap_struct.h
deleted file mode 100644
index 71013fe25f7..00000000000
--- a/components/soc/esp32s3/include/soc/usb_wrap_struct.h
+++ /dev/null
@@ -1,445 +0,0 @@
-/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
- *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- */
-#pragma once
-
-#include <stdint.h>
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Control/Status registers */
-/** Type of otg_conf register
- *  PAD/DFIFO/PHY configuration register.
- */
-typedef union {
-    struct {
-        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
-         *  This bit is used to enable the software override of srp session end signal.1'b0:
-         *  the signal is controlled by the chip input.1'b1: the signal is controlled by the
-         *  software.
-         */
-        uint32_t srp_sessend_override:1;
-        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
-         *  Software override value of srp session end signal.
-         */
-        uint32_t srp_sessend_value:1;
-        /** phy_sel : R/W; bitpos: [2]; default: 0;
-         *  Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY
-         */
-        uint32_t phy_sel:1;
-        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
-         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
-         */
-        uint32_t dfifo_force_pd:1;
-        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
-         *  Bypass Debounce filters for avalid.
-         */
-        uint32_t dbnce_fltr_bypass:1;
-        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
-         *  Enable software to control USB D+ D- exchange
-         */
-        uint32_t exchg_pins_override:1;
-        /** exchg_pins : R/W; bitpos: [6]; default: 0;
-         *  USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-.
-         */
-        uint32_t exchg_pins:1;
-        /** vrefh : R/W; bitpos: [8:7]; default: 0;
-         *  Control single-end input high threshold.
-         */
-        uint32_t vrefh:2;
-        /** vrefl : R/W; bitpos: [10:9]; default: 0;
-         *  Control single-end input low threshold.
-         */
-        uint32_t vrefl:2;
-        /** vref_override : R/W; bitpos: [11]; default: 0;
-         *  Enable software to control input  threshold.
-         */
-        uint32_t vref_override:1;
-        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
-         *  Enable software to control USB pad in pullup or pulldown mode.
-         */
-        uint32_t pad_pull_override:1;
-        /** dp_pullup : R/W; bitpos: [13]; default: 0;
-         *  Control USB D+ pullup.
-         */
-        uint32_t dp_pullup:1;
-        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
-         *  Control USB D+ pulldown.
-         */
-        uint32_t dp_pulldown:1;
-        /** dm_pullup : R/W; bitpos: [15]; default: 0;
-         *  Control USB D+ pullup.
-         */
-        uint32_t dm_pullup:1;
-        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
-         *  Control USB D+ pulldown.
-         */
-        uint32_t dm_pulldown:1;
-        /** pullup_value : R/W; bitpos: [17]; default: 0;
-         *  Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K.
-         */
-        uint32_t pullup_value:1;
-        /** pad_enable : R/W; bitpos: [18]; default: 0;
-         *  Enable USB pad function.
-         */
-        uint32_t pad_enable:1;
-        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 1;
-         *  Force AHB clock always on.
-         */
-        uint32_t ahb_clk_force_on:1;
-        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
-         *  Force PHY clock always on.
-         */
-        uint32_t phy_clk_force_on:1;
-        /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
-         *  Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
-         */
-        uint32_t phy_tx_edge_sel:1;
-        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
-         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
-         */
-        uint32_t dfifo_force_pu:1;
-        uint32_t reserved_23:8;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Disable auto clock gating of CSR registers.
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} usb_wrap_otg_conf_reg_t;
-
-/** Type of test_conf register
- *  TEST relative configuration registers.
- */
-typedef union {
-    struct {
-        /** test_enable : R/W; bitpos: [0]; default: 0;
-         *  Enable to test the USB pad.
-         */
-        uint32_t test_enable:1;
-        /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
-         *  USB pad oen in test.
-         */
-        uint32_t test_usb_wrap_oe:1;
-        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
-         *  USB D+ tx value in test.
-         */
-        uint32_t test_tx_dp:1;
-        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
-         *  USB D- tx value in test.
-         */
-        uint32_t test_tx_dm:1;
-        /** test_rx_rcv : RO; bitpos: [4]; default: 0;
-         *  USB differential rx value in test.
-         */
-        uint32_t test_rx_rcv:1;
-        /** test_rx_dp : RO; bitpos: [5]; default: 0;
-         *  USB D+ rx value in test.
-         */
-        uint32_t test_rx_dp:1;
-        /** test_rx_dm : RO; bitpos: [6]; default: 0;
-         *  USB D- rx value in test.
-         */
-        uint32_t test_rx_dm:1;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} usb_wrap_test_conf_reg_t;
-
-
-/** Status registers */
-/** Type of date register
- *  Version register.
- */
-typedef union {
-    struct {
-        /** date : R/W; bitpos: [31:0]; default: 419631616;
-         *  data register.
-         */
-        uint32_t date:32;
-    };
-    uint32_t val;
-} usb_wrap_date_reg_t;
-
-
-typedef struct {
-    volatile usb_wrap_otg_conf_reg_t otg_conf;
-    volatile usb_wrap_test_conf_reg_t test_conf;
-    uint32_t reserved_008;
-    uint32_t reserved_00c;
-    uint32_t reserved_010;
-    uint32_t reserved_014;
-    uint32_t reserved_018;
-    uint32_t reserved_01c;
-    uint32_t reserved_020;
-    uint32_t reserved_024;
-    uint32_t reserved_028;
-    uint32_t reserved_02c;
-    uint32_t reserved_030;
-    uint32_t reserved_034;
-    uint32_t reserved_038;
-    uint32_t reserved_03c;
-    uint32_t reserved_040;
-    uint32_t reserved_044;
-    uint32_t reserved_048;
-    uint32_t reserved_04c;
-    uint32_t reserved_050;
-    uint32_t reserved_054;
-    uint32_t reserved_058;
-    uint32_t reserved_05c;
-    uint32_t reserved_060;
-    uint32_t reserved_064;
-    uint32_t reserved_068;
-    uint32_t reserved_06c;
-    uint32_t reserved_070;
-    uint32_t reserved_074;
-    uint32_t reserved_078;
-    uint32_t reserved_07c;
-    uint32_t reserved_080;
-    uint32_t reserved_084;
-    uint32_t reserved_088;
-    uint32_t reserved_08c;
-    uint32_t reserved_090;
-    uint32_t reserved_094;
-    uint32_t reserved_098;
-    uint32_t reserved_09c;
-    uint32_t reserved_0a0;
-    uint32_t reserved_0a4;
-    uint32_t reserved_0a8;
-    uint32_t reserved_0ac;
-    uint32_t reserved_0b0;
-    uint32_t reserved_0b4;
-    uint32_t reserved_0b8;
-    uint32_t reserved_0bc;
-    uint32_t reserved_0c0;
-    uint32_t reserved_0c4;
-    uint32_t reserved_0c8;
-    uint32_t reserved_0cc;
-    uint32_t reserved_0d0;
-    uint32_t reserved_0d4;
-    uint32_t reserved_0d8;
-    uint32_t reserved_0dc;
-    uint32_t reserved_0e0;
-    uint32_t reserved_0e4;
-    uint32_t reserved_0e8;
-    uint32_t reserved_0ec;
-    uint32_t reserved_0f0;
-    uint32_t reserved_0f4;
-    uint32_t reserved_0f8;
-    uint32_t reserved_0fc;
-    uint32_t reserved_100;
-    uint32_t reserved_104;
-    uint32_t reserved_108;
-    uint32_t reserved_10c;
-    uint32_t reserved_110;
-    uint32_t reserved_114;
-    uint32_t reserved_118;
-    uint32_t reserved_11c;
-    uint32_t reserved_120;
-    uint32_t reserved_124;
-    uint32_t reserved_128;
-    uint32_t reserved_12c;
-    uint32_t reserved_130;
-    uint32_t reserved_134;
-    uint32_t reserved_138;
-    uint32_t reserved_13c;
-    uint32_t reserved_140;
-    uint32_t reserved_144;
-    uint32_t reserved_148;
-    uint32_t reserved_14c;
-    uint32_t reserved_150;
-    uint32_t reserved_154;
-    uint32_t reserved_158;
-    uint32_t reserved_15c;
-    uint32_t reserved_160;
-    uint32_t reserved_164;
-    uint32_t reserved_168;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    uint32_t reserved_1fc;
-    uint32_t reserved_200;
-    uint32_t reserved_204;
-    uint32_t reserved_208;
-    uint32_t reserved_20c;
-    uint32_t reserved_210;
-    uint32_t reserved_214;
-    uint32_t reserved_218;
-    uint32_t reserved_21c;
-    uint32_t reserved_220;
-    uint32_t reserved_224;
-    uint32_t reserved_228;
-    uint32_t reserved_22c;
-    uint32_t reserved_230;
-    uint32_t reserved_234;
-    uint32_t reserved_238;
-    uint32_t reserved_23c;
-    uint32_t reserved_240;
-    uint32_t reserved_244;
-    uint32_t reserved_248;
-    uint32_t reserved_24c;
-    uint32_t reserved_250;
-    uint32_t reserved_254;
-    uint32_t reserved_258;
-    uint32_t reserved_25c;
-    uint32_t reserved_260;
-    uint32_t reserved_264;
-    uint32_t reserved_268;
-    uint32_t reserved_26c;
-    uint32_t reserved_270;
-    uint32_t reserved_274;
-    uint32_t reserved_278;
-    uint32_t reserved_27c;
-    uint32_t reserved_280;
-    uint32_t reserved_284;
-    uint32_t reserved_288;
-    uint32_t reserved_28c;
-    uint32_t reserved_290;
-    uint32_t reserved_294;
-    uint32_t reserved_298;
-    uint32_t reserved_29c;
-    uint32_t reserved_2a0;
-    uint32_t reserved_2a4;
-    uint32_t reserved_2a8;
-    uint32_t reserved_2ac;
-    uint32_t reserved_2b0;
-    uint32_t reserved_2b4;
-    uint32_t reserved_2b8;
-    uint32_t reserved_2bc;
-    uint32_t reserved_2c0;
-    uint32_t reserved_2c4;
-    uint32_t reserved_2c8;
-    uint32_t reserved_2cc;
-    uint32_t reserved_2d0;
-    uint32_t reserved_2d4;
-    uint32_t reserved_2d8;
-    uint32_t reserved_2dc;
-    uint32_t reserved_2e0;
-    uint32_t reserved_2e4;
-    uint32_t reserved_2e8;
-    uint32_t reserved_2ec;
-    uint32_t reserved_2f0;
-    uint32_t reserved_2f4;
-    uint32_t reserved_2f8;
-    uint32_t reserved_2fc;
-    uint32_t reserved_300;
-    uint32_t reserved_304;
-    uint32_t reserved_308;
-    uint32_t reserved_30c;
-    uint32_t reserved_310;
-    uint32_t reserved_314;
-    uint32_t reserved_318;
-    uint32_t reserved_31c;
-    uint32_t reserved_320;
-    uint32_t reserved_324;
-    uint32_t reserved_328;
-    uint32_t reserved_32c;
-    uint32_t reserved_330;
-    uint32_t reserved_334;
-    uint32_t reserved_338;
-    uint32_t reserved_33c;
-    uint32_t reserved_340;
-    uint32_t reserved_344;
-    uint32_t reserved_348;
-    uint32_t reserved_34c;
-    uint32_t reserved_350;
-    uint32_t reserved_354;
-    uint32_t reserved_358;
-    uint32_t reserved_35c;
-    uint32_t reserved_360;
-    uint32_t reserved_364;
-    uint32_t reserved_368;
-    uint32_t reserved_36c;
-    uint32_t reserved_370;
-    uint32_t reserved_374;
-    uint32_t reserved_378;
-    uint32_t reserved_37c;
-    uint32_t reserved_380;
-    uint32_t reserved_384;
-    uint32_t reserved_388;
-    uint32_t reserved_38c;
-    uint32_t reserved_390;
-    uint32_t reserved_394;
-    uint32_t reserved_398;
-    uint32_t reserved_39c;
-    uint32_t reserved_3a0;
-    uint32_t reserved_3a4;
-    uint32_t reserved_3a8;
-    uint32_t reserved_3ac;
-    uint32_t reserved_3b0;
-    uint32_t reserved_3b4;
-    uint32_t reserved_3b8;
-    uint32_t reserved_3bc;
-    uint32_t reserved_3c0;
-    uint32_t reserved_3c4;
-    uint32_t reserved_3c8;
-    uint32_t reserved_3cc;
-    uint32_t reserved_3d0;
-    uint32_t reserved_3d4;
-    uint32_t reserved_3d8;
-    uint32_t reserved_3dc;
-    uint32_t reserved_3e0;
-    uint32_t reserved_3e4;
-    uint32_t reserved_3e8;
-    uint32_t reserved_3ec;
-    uint32_t reserved_3f0;
-    uint32_t reserved_3f4;
-    uint32_t reserved_3f8;
-    volatile usb_wrap_date_reg_t date;
-} usb_wrap_dev_t;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(usb_wrap_dev_t)==0x400, "Invalid USB_WRAP size");
-#endif
-
-extern usb_wrap_dev_t USB_WRAP;
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32s3/register/soc/.gitkeep b/components/soc/esp32s3/register/soc/.gitkeep
deleted file mode 100644
index e69de29bb2d..00000000000
diff --git a/components/soc/esp32s3/register/soc/apb_ctrl_reg.h b/components/soc/esp32s3/register/soc/apb_ctrl_reg.h
new file mode 100644
index 00000000000..809463766ae
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/apb_ctrl_reg.h
@@ -0,0 +1,656 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_APB_CTRL_REG_H_
+#define _SOC_APB_CTRL_REG_H_
+
+#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x0)
+/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_RST_TICK_CNT    (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_V  0x1
+#define APB_CTRL_RST_TICK_CNT_S  12
+/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_CLK_EN    (BIT(11))
+#define APB_CTRL_CLK_EN_M  (BIT(11))
+#define APB_CTRL_CLK_EN_V  0x1
+#define APB_CTRL_CLK_EN_S  11
+/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_CLK_320M_EN    (BIT(10))
+#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_V  0x1
+#define APB_CTRL_CLK_320M_EN_S  10
+/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: .*/
+#define APB_CTRL_PRE_DIV_CNT    0x000003FF
+#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
+#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
+#define APB_CTRL_PRE_DIV_CNT_S  0
+
+#define APB_CTRL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x4)
+/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: .*/
+#define APB_CTRL_TICK_ENABLE    (BIT(16))
+#define APB_CTRL_TICK_ENABLE_M  (BIT(16))
+#define APB_CTRL_TICK_ENABLE_V  0x1
+#define APB_CTRL_TICK_ENABLE_S  16
+/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: .*/
+#define APB_CTRL_CK8M_TICK_NUM    0x000000FF
+#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
+#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
+#define APB_CTRL_CK8M_TICK_NUM_S  8
+/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: .*/
+#define APB_CTRL_XTAL_TICK_NUM    0x000000FF
+#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
+#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
+#define APB_CTRL_XTAL_TICK_NUM_S  0
+
+#define APB_CTRL_CLK_OUT_EN_REG          (DR_REG_APB_CTRL_BASE + 0x8)
+/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK_XTAL_OEN    (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_M  (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_V  0x1
+#define APB_CTRL_CLK_XTAL_OEN_S  10
+/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK40X_BB_OEN    (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_M  (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_V  0x1
+#define APB_CTRL_CLK40X_BB_OEN_S  9
+/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK_DAC_CPU_OEN    (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_V  0x1
+#define APB_CTRL_CLK_DAC_CPU_OEN_S  8
+/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK_ADC_INF_OEN    (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_M  (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_V  0x1
+#define APB_CTRL_CLK_ADC_INF_OEN_S  7
+/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK_320M_OEN    (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_M  (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_V  0x1
+#define APB_CTRL_CLK_320M_OEN_S  6
+/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK160_OEN    (BIT(5))
+#define APB_CTRL_CLK160_OEN_M  (BIT(5))
+#define APB_CTRL_CLK160_OEN_V  0x1
+#define APB_CTRL_CLK160_OEN_S  5
+/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK80_OEN    (BIT(4))
+#define APB_CTRL_CLK80_OEN_M  (BIT(4))
+#define APB_CTRL_CLK80_OEN_V  0x1
+#define APB_CTRL_CLK80_OEN_S  4
+/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK_BB_OEN    (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_M  (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_V  0x1
+#define APB_CTRL_CLK_BB_OEN_S  3
+/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK44_OEN    (BIT(2))
+#define APB_CTRL_CLK44_OEN_M  (BIT(2))
+#define APB_CTRL_CLK44_OEN_V  0x1
+#define APB_CTRL_CLK44_OEN_S  2
+/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK22_OEN    (BIT(1))
+#define APB_CTRL_CLK22_OEN_M  (BIT(1))
+#define APB_CTRL_CLK22_OEN_V  0x1
+#define APB_CTRL_CLK22_OEN_S  1
+/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_CLK20_OEN    (BIT(0))
+#define APB_CTRL_CLK20_OEN_M  (BIT(0))
+#define APB_CTRL_CLK20_OEN_V  0x1
+#define APB_CTRL_CLK20_OEN_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_REG          (DR_REG_APB_CTRL_BASE + 0xC)
+/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define APB_CTRL_WIFI_BB_CFG    0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_M  ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
+#define APB_CTRL_WIFI_BB_CFG_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_2_REG          (DR_REG_APB_CTRL_BASE + 0x10)
+/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define APB_CTRL_WIFI_BB_CFG_2    0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_M  ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
+#define APB_CTRL_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_S  0
+
+#define APB_CTRL_WIFI_CLK_EN_REG          (DR_REG_APB_CTRL_BASE + 0x14)
+/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: .*/
+#define APB_CTRL_WIFI_CLK_EN    0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_M  ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
+#define APB_CTRL_WIFI_CLK_EN_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_S  0
+
+#define APB_CTRL_WIFI_RST_EN_REG          (DR_REG_APB_CTRL_BASE + 0x18)
+/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define APB_CTRL_WIFI_RST    0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_M  ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
+#define APB_CTRL_WIFI_RST_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_S  0
+
+#define APB_CTRL_HOST_INF_SEL_REG          (DR_REG_APB_CTRL_BASE + 0x1C)
+/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define APB_CTRL_PERI_IO_SWAP    0x000000FF
+#define APB_CTRL_PERI_IO_SWAP_M  ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
+#define APB_CTRL_PERI_IO_SWAP_V  0xFF
+#define APB_CTRL_PERI_IO_SWAP_S  0
+
+#define APB_CTRL_EXT_MEM_PMS_LOCK_REG          (DR_REG_APB_CTRL_BASE + 0x20)
+/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_EXT_MEM_PMS_LOCK    (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_V  0x1
+#define APB_CTRL_EXT_MEM_PMS_LOCK_S  0
+
+#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG          (DR_REG_APB_CTRL_BASE + 0x24)
+/* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to bypass cache writeback request to external memory so that spi will not
+check its attribute..*/
+#define APB_CTRL_WRITEBACK_BYPASS    (BIT(0))
+#define APB_CTRL_WRITEBACK_BYPASS_M  (BIT(0))
+#define APB_CTRL_WRITEBACK_BYPASS_V  0x1
+#define APB_CTRL_WRITEBACK_BYPASS_S  0
+
+#define APB_CTRL_FLASH_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x28)
+/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE0_ATTR    0x000001FF
+#define APB_CTRL_FLASH_ACE0_ATTR_M  ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
+#define APB_CTRL_FLASH_ACE0_ATTR_V  0x1FF
+#define APB_CTRL_FLASH_ACE0_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x2C)
+/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE1_ATTR    0x000001FF
+#define APB_CTRL_FLASH_ACE1_ATTR_M  ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
+#define APB_CTRL_FLASH_ACE1_ATTR_V  0x1FF
+#define APB_CTRL_FLASH_ACE1_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x30)
+/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE2_ATTR    0x000001FF
+#define APB_CTRL_FLASH_ACE2_ATTR_M  ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
+#define APB_CTRL_FLASH_ACE2_ATTR_V  0x1FF
+#define APB_CTRL_FLASH_ACE2_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x34)
+/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE3_ATTR    0x000001FF
+#define APB_CTRL_FLASH_ACE3_ATTR_M  ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
+#define APB_CTRL_FLASH_ACE3_ATTR_V  0x1FF
+#define APB_CTRL_FLASH_ACE3_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x38)
+/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE0_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_M  ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x3C)
+/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE1_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_M  ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x40)
+/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE2_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_M  ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x44)
+/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE3_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_M  ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x48)
+/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE0_SIZE    0x0000FFFF
+#define APB_CTRL_FLASH_ACE0_SIZE_M  ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
+#define APB_CTRL_FLASH_ACE0_SIZE_V  0xFFFF
+#define APB_CTRL_FLASH_ACE0_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x4C)
+/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE1_SIZE    0x0000FFFF
+#define APB_CTRL_FLASH_ACE1_SIZE_M  ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
+#define APB_CTRL_FLASH_ACE1_SIZE_V  0xFFFF
+#define APB_CTRL_FLASH_ACE1_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x50)
+/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE2_SIZE    0x0000FFFF
+#define APB_CTRL_FLASH_ACE2_SIZE_M  ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
+#define APB_CTRL_FLASH_ACE2_SIZE_V  0xFFFF
+#define APB_CTRL_FLASH_ACE2_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x54)
+/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define APB_CTRL_FLASH_ACE3_SIZE    0x0000FFFF
+#define APB_CTRL_FLASH_ACE3_SIZE_M  ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
+#define APB_CTRL_FLASH_ACE3_SIZE_V  0xFFFF
+#define APB_CTRL_FLASH_ACE3_SIZE_S  0
+
+#define APB_CTRL_SRAM_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x58)
+/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE0_ATTR    0x000001FF
+#define APB_CTRL_SRAM_ACE0_ATTR_M  ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S))
+#define APB_CTRL_SRAM_ACE0_ATTR_V  0x1FF
+#define APB_CTRL_SRAM_ACE0_ATTR_S  0
+
+#define APB_CTRL_SRAM_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x5C)
+/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE1_ATTR    0x000001FF
+#define APB_CTRL_SRAM_ACE1_ATTR_M  ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S))
+#define APB_CTRL_SRAM_ACE1_ATTR_V  0x1FF
+#define APB_CTRL_SRAM_ACE1_ATTR_S  0
+
+#define APB_CTRL_SRAM_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x60)
+/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE2_ATTR    0x000001FF
+#define APB_CTRL_SRAM_ACE2_ATTR_M  ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S))
+#define APB_CTRL_SRAM_ACE2_ATTR_V  0x1FF
+#define APB_CTRL_SRAM_ACE2_ATTR_S  0
+
+#define APB_CTRL_SRAM_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x64)
+/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE3_ATTR    0x000001FF
+#define APB_CTRL_SRAM_ACE3_ATTR_M  ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S))
+#define APB_CTRL_SRAM_ACE3_ATTR_V  0x1FF
+#define APB_CTRL_SRAM_ACE3_ATTR_S  0
+
+#define APB_CTRL_SRAM_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x68)
+/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE0_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE0_ADDR_S_M  ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S))
+#define APB_CTRL_SRAM_ACE0_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE0_ADDR_S_S  0
+
+#define APB_CTRL_SRAM_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x6C)
+/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE1_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE1_ADDR_S_M  ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S))
+#define APB_CTRL_SRAM_ACE1_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE1_ADDR_S_S  0
+
+#define APB_CTRL_SRAM_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x70)
+/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE2_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE2_ADDR_S_M  ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S))
+#define APB_CTRL_SRAM_ACE2_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE2_ADDR_S_S  0
+
+#define APB_CTRL_SRAM_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x74)
+/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE3_ADDR_S    0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE3_ADDR_S_M  ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S))
+#define APB_CTRL_SRAM_ACE3_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE3_ADDR_S_S  0
+
+#define APB_CTRL_SRAM_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x78)
+/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE0_SIZE    0x0000FFFF
+#define APB_CTRL_SRAM_ACE0_SIZE_M  ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S))
+#define APB_CTRL_SRAM_ACE0_SIZE_V  0xFFFF
+#define APB_CTRL_SRAM_ACE0_SIZE_S  0
+
+#define APB_CTRL_SRAM_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x7C)
+/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE1_SIZE    0x0000FFFF
+#define APB_CTRL_SRAM_ACE1_SIZE_M  ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S))
+#define APB_CTRL_SRAM_ACE1_SIZE_V  0xFFFF
+#define APB_CTRL_SRAM_ACE1_SIZE_S  0
+
+#define APB_CTRL_SRAM_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x80)
+/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE2_SIZE    0x0000FFFF
+#define APB_CTRL_SRAM_ACE2_SIZE_M  ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S))
+#define APB_CTRL_SRAM_ACE2_SIZE_V  0xFFFF
+#define APB_CTRL_SRAM_ACE2_SIZE_S  0
+
+#define APB_CTRL_SRAM_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x84)
+/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_ACE3_SIZE    0x0000FFFF
+#define APB_CTRL_SRAM_ACE3_SIZE_M  ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S))
+#define APB_CTRL_SRAM_ACE3_SIZE_V  0xFFFF
+#define APB_CTRL_SRAM_ACE3_SIZE_S  0
+
+#define APB_CTRL_SPI_MEM_PMS_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x88)
+/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: .*/
+#define APB_CTRL_SPI_MEM_REJECT_CDE    0x0000001F
+#define APB_CTRL_SPI_MEM_REJECT_CDE_M  ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
+#define APB_CTRL_SPI_MEM_REJECT_CDE_V  0x1F
+#define APB_CTRL_SPI_MEM_REJECT_CDE_S  2
+/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_SPI_MEM_REJECT_CLR    (BIT(1))
+#define APB_CTRL_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define APB_CTRL_SPI_MEM_REJECT_CLR_V  0x1
+#define APB_CTRL_SPI_MEM_REJECT_CLR_S  1
+/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_SPI_MEM_REJECT_INT    (BIT(0))
+#define APB_CTRL_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define APB_CTRL_SPI_MEM_REJECT_INT_V  0x1
+#define APB_CTRL_SPI_MEM_REJECT_INT_S  0
+
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x8C)
+/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define APB_CTRL_SPI_MEM_REJECT_ADDR    0xFFFFFFFF
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_M  ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_SPI_MEM_REJECT_ADDR_S  0
+
+#define APB_CTRL_SDIO_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x90)
+/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: .*/
+#define APB_CTRL_SDIO_WIN_ACCESS_EN    (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_V  0x1
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_S  0
+
+#define APB_CTRL_REDCY_SIG0_REG          (DR_REG_APB_CTRL_BASE + 0x94)
+/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define APB_CTRL_REDCY_ANDOR    (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_V  0x1
+#define APB_CTRL_REDCY_ANDOR_S  31
+/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: .*/
+#define APB_CTRL_REDCY_SIG0    0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_M  ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
+#define APB_CTRL_REDCY_SIG0_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_S  0
+
+#define APB_CTRL_REDCY_SIG1_REG          (DR_REG_APB_CTRL_BASE + 0x98)
+/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define APB_CTRL_REDCY_NANDOR    (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_V  0x1
+#define APB_CTRL_REDCY_NANDOR_S  31
+/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: .*/
+#define APB_CTRL_REDCY_SIG1    0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_M  ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
+#define APB_CTRL_REDCY_SIG1_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_S  0
+
+#define APB_CTRL_FRONT_END_MEM_PD_REG          (DR_REG_APB_CTRL_BASE + 0x9C)
+/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_FREQ_MEM_FORCE_PD    (BIT(7))
+#define APB_CTRL_FREQ_MEM_FORCE_PD_M  (BIT(7))
+#define APB_CTRL_FREQ_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_FREQ_MEM_FORCE_PD_S  7
+/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_FREQ_MEM_FORCE_PU    (BIT(6))
+#define APB_CTRL_FREQ_MEM_FORCE_PU_M  (BIT(6))
+#define APB_CTRL_FREQ_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_FREQ_MEM_FORCE_PU_S  6
+/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_DC_MEM_FORCE_PD    (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_M  (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PD_S  5
+/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_DC_MEM_FORCE_PU    (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_M  (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PU_S  4
+/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_PBUS_MEM_FORCE_PD    (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PD_S  3
+/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_PBUS_MEM_FORCE_PU    (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PU_S  2
+/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_AGC_MEM_FORCE_PD    (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PD_S  1
+/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_CTRL_AGC_MEM_FORCE_PU    (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PU_S  0
+
+#define APB_CTRL_SPI_MEM_ECC_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0xA0)
+/* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
+/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2:
+1024 bytes. 3: 2048 bytes..*/
+#define APB_CTRL_SRAM_PAGE_SIZE    0x00000003
+#define APB_CTRL_SRAM_PAGE_SIZE_M  ((APB_CTRL_SRAM_PAGE_SIZE_V)<<(APB_CTRL_SRAM_PAGE_SIZE_S))
+#define APB_CTRL_SRAM_PAGE_SIZE_V  0x3
+#define APB_CTRL_SRAM_PAGE_SIZE_S  20
+/* APB_CTRL_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by
+tes. 3: 2048 bytes..*/
+#define APB_CTRL_FLASH_PAGE_SIZE    0x00000003
+#define APB_CTRL_FLASH_PAGE_SIZE_M  ((APB_CTRL_FLASH_PAGE_SIZE_V)<<(APB_CTRL_FLASH_PAGE_SIZE_S))
+#define APB_CTRL_FLASH_PAGE_SIZE_V  0x3
+#define APB_CTRL_FLASH_PAGE_SIZE_S  18
+
+#define APB_CTRL_CLKGATE_FORCE_ON_REG          (DR_REG_APB_CTRL_BASE + 0xA8)
+/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON    0x000007FF
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M  ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V  0x7FF
+#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S  3
+/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON    0x00000007
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M  ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V  0x7
+#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S  0
+
+#define APB_CTRL_MEM_POWER_DOWN_REG          (DR_REG_APB_CTRL_BASE + 0xAC)
+/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_POWER_DOWN    0x000007FF
+#define APB_CTRL_SRAM_POWER_DOWN_M  ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
+#define APB_CTRL_SRAM_POWER_DOWN_V  0x7FF
+#define APB_CTRL_SRAM_POWER_DOWN_S  3
+/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: .*/
+#define APB_CTRL_ROM_POWER_DOWN    0x00000007
+#define APB_CTRL_ROM_POWER_DOWN_M  ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
+#define APB_CTRL_ROM_POWER_DOWN_V  0x7
+#define APB_CTRL_ROM_POWER_DOWN_S  0
+
+#define APB_CTRL_MEM_POWER_UP_REG          (DR_REG_APB_CTRL_BASE + 0xB0)
+/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
+/*description: .*/
+#define APB_CTRL_SRAM_POWER_UP    0x000007FF
+#define APB_CTRL_SRAM_POWER_UP_M  ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
+#define APB_CTRL_SRAM_POWER_UP_V  0x7FF
+#define APB_CTRL_SRAM_POWER_UP_S  3
+/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define APB_CTRL_ROM_POWER_UP    0x00000007
+#define APB_CTRL_ROM_POWER_UP_M  ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
+#define APB_CTRL_ROM_POWER_UP_V  0x7
+#define APB_CTRL_ROM_POWER_UP_S  0
+
+#define APB_CTRL_RETENTION_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0xB4)
+/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST    (BIT(27))
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V  0x1
+#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S  27
+/* APB_CTRL_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: .*/
+#define APB_CTRL_RETENTION_CPU_LINK_ADDR    0x07FFFFFF
+#define APB_CTRL_RETENTION_CPU_LINK_ADDR_M  ((APB_CTRL_RETENTION_CPU_LINK_ADDR_V)<<(APB_CTRL_RETENTION_CPU_LINK_ADDR_S))
+#define APB_CTRL_RETENTION_CPU_LINK_ADDR_V  0x7FFFFFF
+#define APB_CTRL_RETENTION_CPU_LINK_ADDR_S  0
+
+#define APB_CTRL_RETENTION_CTRL1_REG          (DR_REG_APB_CTRL_BASE + 0xB8)
+/* APB_CTRL_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: .*/
+#define APB_CTRL_RETENTION_TAG_LINK_ADDR    0x07FFFFFF
+#define APB_CTRL_RETENTION_TAG_LINK_ADDR_M  ((APB_CTRL_RETENTION_TAG_LINK_ADDR_V)<<(APB_CTRL_RETENTION_TAG_LINK_ADDR_S))
+#define APB_CTRL_RETENTION_TAG_LINK_ADDR_V  0x7FFFFFF
+#define APB_CTRL_RETENTION_TAG_LINK_ADDR_S  0
+
+#define APB_CTRL_RETENTION_CTRL2_REG          (DR_REG_APB_CTRL_BASE + 0xBC)
+/* APB_CTRL_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_RET_ICACHE_ENABLE    (BIT(31))
+#define APB_CTRL_RET_ICACHE_ENABLE_M  (BIT(31))
+#define APB_CTRL_RET_ICACHE_ENABLE_V  0x1
+#define APB_CTRL_RET_ICACHE_ENABLE_S  31
+/* APB_CTRL_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
+/*description: .*/
+#define APB_CTRL_RET_ICACHE_START_POINT    0x000000FF
+#define APB_CTRL_RET_ICACHE_START_POINT_M  ((APB_CTRL_RET_ICACHE_START_POINT_V)<<(APB_CTRL_RET_ICACHE_START_POINT_S))
+#define APB_CTRL_RET_ICACHE_START_POINT_V  0xFF
+#define APB_CTRL_RET_ICACHE_START_POINT_S  22
+/* APB_CTRL_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
+/*description: .*/
+#define APB_CTRL_RET_ICACHE_VLD_SIZE    0x000000FF
+#define APB_CTRL_RET_ICACHE_VLD_SIZE_M  ((APB_CTRL_RET_ICACHE_VLD_SIZE_V)<<(APB_CTRL_RET_ICACHE_VLD_SIZE_S))
+#define APB_CTRL_RET_ICACHE_VLD_SIZE_V  0xFF
+#define APB_CTRL_RET_ICACHE_VLD_SIZE_S  13
+/* APB_CTRL_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
+/*description: .*/
+#define APB_CTRL_RET_ICACHE_SIZE    0x000000FF
+#define APB_CTRL_RET_ICACHE_SIZE_M  ((APB_CTRL_RET_ICACHE_SIZE_V)<<(APB_CTRL_RET_ICACHE_SIZE_S))
+#define APB_CTRL_RET_ICACHE_SIZE_V  0xFF
+#define APB_CTRL_RET_ICACHE_SIZE_S  4
+
+#define APB_CTRL_RETENTION_CTRL3_REG          (DR_REG_APB_CTRL_BASE + 0xC0)
+/* APB_CTRL_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_RET_DCACHE_ENABLE    (BIT(31))
+#define APB_CTRL_RET_DCACHE_ENABLE_M  (BIT(31))
+#define APB_CTRL_RET_DCACHE_ENABLE_V  0x1
+#define APB_CTRL_RET_DCACHE_ENABLE_S  31
+/* APB_CTRL_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
+/*description: .*/
+#define APB_CTRL_RET_DCACHE_START_POINT    0x000001FF
+#define APB_CTRL_RET_DCACHE_START_POINT_M  ((APB_CTRL_RET_DCACHE_START_POINT_V)<<(APB_CTRL_RET_DCACHE_START_POINT_S))
+#define APB_CTRL_RET_DCACHE_START_POINT_V  0x1FF
+#define APB_CTRL_RET_DCACHE_START_POINT_S  22
+/* APB_CTRL_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
+/*description: .*/
+#define APB_CTRL_RET_DCACHE_VLD_SIZE    0x000001FF
+#define APB_CTRL_RET_DCACHE_VLD_SIZE_M  ((APB_CTRL_RET_DCACHE_VLD_SIZE_V)<<(APB_CTRL_RET_DCACHE_VLD_SIZE_S))
+#define APB_CTRL_RET_DCACHE_VLD_SIZE_V  0x1FF
+#define APB_CTRL_RET_DCACHE_VLD_SIZE_S  13
+/* APB_CTRL_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
+/*description: .*/
+#define APB_CTRL_RET_DCACHE_SIZE    0x000001FF
+#define APB_CTRL_RET_DCACHE_SIZE_M  ((APB_CTRL_RET_DCACHE_SIZE_V)<<(APB_CTRL_RET_DCACHE_SIZE_S))
+#define APB_CTRL_RET_DCACHE_SIZE_V  0x1FF
+#define APB_CTRL_RET_DCACHE_SIZE_S  4
+
+#define APB_CTRL_RETENTION_CTRL4_REG          (DR_REG_APB_CTRL_BASE + 0xC4)
+/* APB_CTRL_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */
+/*description: .*/
+#define APB_CTRL_RETENTION_INV_CFG    0xFFFFFFFF
+#define APB_CTRL_RETENTION_INV_CFG_M  ((APB_CTRL_RETENTION_INV_CFG_V)<<(APB_CTRL_RETENTION_INV_CFG_S))
+#define APB_CTRL_RETENTION_INV_CFG_V  0xFFFFFFFF
+#define APB_CTRL_RETENTION_INV_CFG_S  0
+
+#define APB_CTRL_RETENTION_CTRL5_REG          (DR_REG_APB_CTRL_BASE + 0xC8)
+/* APB_CTRL_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_CTRL_RETENTION_DISABLE    (BIT(0))
+#define APB_CTRL_RETENTION_DISABLE_M  (BIT(0))
+#define APB_CTRL_RETENTION_DISABLE_V  0x1
+#define APB_CTRL_RETENTION_DISABLE_S  0
+
+#define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x3FC)
+/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
+/*description: Version control.*/
+#define APB_CTRL_DATE    0xFFFFFFFF
+#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
+#define APB_CTRL_DATE_V  0xFFFFFFFF
+#define APB_CTRL_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_CTRL_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/apb_ctrl_struct.h b/components/soc/esp32s3/register/soc/apb_ctrl_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/apb_ctrl_struct.h
rename to components/soc/esp32s3/register/soc/apb_ctrl_struct.h
diff --git a/components/soc/esp32s3/register/soc/apb_saradc_reg.h b/components/soc/esp32s3/register/soc/apb_saradc_reg.h
new file mode 100644
index 00000000000..61d99974db4
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/apb_saradc_reg.h
@@ -0,0 +1,638 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_APB_SARADC_REG_H_
+#define _SOC_APB_SARADC_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define APB_SARADC_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x0)
+/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
+/*description: wait arbit signal stable after sar_done.*/
+#define APB_SARADC_WAIT_ARB_CYCLE    0x00000003
+#define APB_SARADC_WAIT_ARB_CYCLE_M  ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
+#define APB_SARADC_WAIT_ARB_CYCLE_V  0x3
+#define APB_SARADC_WAIT_ARB_CYCLE_S  30
+/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
+/*description: force option to xpd sar blocks.*/
+#define APB_SARADC_XPD_SAR_FORCE    0x00000003
+#define APB_SARADC_XPD_SAR_FORCE_M  ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
+#define APB_SARADC_XPD_SAR_FORCE_V  0x3
+#define APB_SARADC_XPD_SAR_FORCE_S  27
+/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matr
+ix.*/
+#define APB_SARADC_DATA_TO_I2S    (BIT(26))
+#define APB_SARADC_DATA_TO_I2S_M  (BIT(26))
+#define APB_SARADC_DATA_TO_I2S_V  0x1
+#define APB_SARADC_DATA_TO_I2S_S  26
+/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+resolution should not be larger than 11 bits..*/
+#define APB_SARADC_DATA_SAR_SEL    (BIT(25))
+#define APB_SARADC_DATA_SAR_SEL_M  (BIT(25))
+#define APB_SARADC_DATA_SAR_SEL_V  0x1
+#define APB_SARADC_DATA_SAR_SEL_S  25
+/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC2 CTRL.*/
+#define APB_SARADC_SAR2_PATT_P_CLEAR    (BIT(24))
+#define APB_SARADC_SAR2_PATT_P_CLEAR_M  (BIT(24))
+#define APB_SARADC_SAR2_PATT_P_CLEAR_V  0x1
+#define APB_SARADC_SAR2_PATT_P_CLEAR_S  24
+/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC1 CTRL.*/
+#define APB_SARADC_SAR1_PATT_P_CLEAR    (BIT(23))
+#define APB_SARADC_SAR1_PATT_P_CLEAR_M  (BIT(23))
+#define APB_SARADC_SAR1_PATT_P_CLEAR_V  0x1
+#define APB_SARADC_SAR1_PATT_P_CLEAR_S  23
+/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
+/*description:  0 ~ 15 means length 1 ~ 16.*/
+#define APB_SARADC_SAR2_PATT_LEN    0x0000000F
+#define APB_SARADC_SAR2_PATT_LEN_M  ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S))
+#define APB_SARADC_SAR2_PATT_LEN_V  0xF
+#define APB_SARADC_SAR2_PATT_LEN_S  19
+/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
+/*description:  0 ~ 15 means length 1 ~ 16.*/
+#define APB_SARADC_SAR1_PATT_LEN    0x0000000F
+#define APB_SARADC_SAR1_PATT_LEN_M  ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S))
+#define APB_SARADC_SAR1_PATT_LEN_V  0xF
+#define APB_SARADC_SAR1_PATT_LEN_S  15
+/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
+/*description: SAR clock divider.*/
+#define APB_SARADC_SAR_CLK_DIV    0x000000FF
+#define APB_SARADC_SAR_CLK_DIV_M  ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
+#define APB_SARADC_SAR_CLK_DIV_V  0xFF
+#define APB_SARADC_SAR_CLK_DIV_S  7
+/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define APB_SARADC_SAR_CLK_GATED    (BIT(6))
+#define APB_SARADC_SAR_CLK_GATED_M  (BIT(6))
+#define APB_SARADC_SAR_CLK_GATED_V  0x1
+#define APB_SARADC_SAR_CLK_GATED_S  6
+/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description:  0: SAR1, 1: SAR2, only work for single SAR mode.*/
+#define APB_SARADC_SAR_SEL    (BIT(5))
+#define APB_SARADC_SAR_SEL_M  (BIT(5))
+#define APB_SARADC_SAR_SEL_V  0x1
+#define APB_SARADC_SAR_SEL_S  5
+/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
+/*description:  0: single mode, 1: double mode, 2: alternate mode.*/
+#define APB_SARADC_WORK_MODE    0x00000003
+#define APB_SARADC_WORK_MODE_M  ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S))
+#define APB_SARADC_WORK_MODE_V  0x3
+#define APB_SARADC_WORK_MODE_S  3
+/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: .*/
+#define APB_SARADC_START    (BIT(1))
+#define APB_SARADC_START_M  (BIT(1))
+#define APB_SARADC_START_V  0x1
+#define APB_SARADC_START_S  1
+/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: .*/
+#define APB_SARADC_START_FORCE    (BIT(0))
+#define APB_SARADC_START_FORCE_M  (BIT(0))
+#define APB_SARADC_START_FORCE_V  0x1
+#define APB_SARADC_START_FORCE_S  0
+
+#define APB_SARADC_CTRL2_REG          (DR_REG_APB_SARADC_BASE + 0x4)
+/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: to enable saradc timer trigger.*/
+#define APB_SARADC_TIMER_EN    (BIT(24))
+#define APB_SARADC_TIMER_EN_M  (BIT(24))
+#define APB_SARADC_TIMER_EN_V  0x1
+#define APB_SARADC_TIMER_EN_S  24
+/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
+/*description: to set saradc timer target.*/
+#define APB_SARADC_TIMER_TARGET    0x00000FFF
+#define APB_SARADC_TIMER_TARGET_M  ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
+#define APB_SARADC_TIMER_TARGET_V  0xFFF
+#define APB_SARADC_TIMER_TARGET_S  12
+/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: 1: select saradc timer 0: i2s_ws trigger.*/
+#define APB_SARADC_TIMER_SEL    (BIT(11))
+#define APB_SARADC_TIMER_SEL_M  (BIT(11))
+#define APB_SARADC_TIMER_SEL_V  0x1
+#define APB_SARADC_TIMER_SEL_S  11
+/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/
+#define APB_SARADC_SAR2_INV    (BIT(10))
+#define APB_SARADC_SAR2_INV_M  (BIT(10))
+#define APB_SARADC_SAR2_INV_V  0x1
+#define APB_SARADC_SAR2_INV_S  10
+/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC1 CTRL is inverted, otherwise not.*/
+#define APB_SARADC_SAR1_INV    (BIT(9))
+#define APB_SARADC_SAR1_INV_M  (BIT(9))
+#define APB_SARADC_SAR1_INV_V  0x1
+#define APB_SARADC_SAR1_INV_S  9
+/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
+/*description: max conversion number.*/
+#define APB_SARADC_MAX_MEAS_NUM    0x000000FF
+#define APB_SARADC_MAX_MEAS_NUM_M  ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
+#define APB_SARADC_MAX_MEAS_NUM_V  0xFF
+#define APB_SARADC_MAX_MEAS_NUM_S  1
+/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: .*/
+#define APB_SARADC_MEAS_NUM_LIMIT    (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
+#define APB_SARADC_MEAS_NUM_LIMIT_V  0x1
+#define APB_SARADC_MEAS_NUM_LIMIT_S  0
+
+#define APB_SARADC_FILTER_CTRL1_REG          (DR_REG_APB_SARADC_BASE + 0x8)
+/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: .*/
+#define APB_SARADC_FILTER_FACTOR0    0x00000007
+#define APB_SARADC_FILTER_FACTOR0_M  ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
+#define APB_SARADC_FILTER_FACTOR0_V  0x7
+#define APB_SARADC_FILTER_FACTOR0_S  29
+/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
+/*description: .*/
+#define APB_SARADC_FILTER_FACTOR1    0x00000007
+#define APB_SARADC_FILTER_FACTOR1_M  ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
+#define APB_SARADC_FILTER_FACTOR1_V  0x7
+#define APB_SARADC_FILTER_FACTOR1_S  26
+
+#define APB_SARADC_FSM_WAIT_REG          (DR_REG_APB_SARADC_BASE + 0xC)
+/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
+/*description: .*/
+#define APB_SARADC_STANDBY_WAIT    0x000000FF
+#define APB_SARADC_STANDBY_WAIT_M  ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
+#define APB_SARADC_STANDBY_WAIT_V  0xFF
+#define APB_SARADC_STANDBY_WAIT_S  16
+/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
+/*description: .*/
+#define APB_SARADC_RSTB_WAIT    0x000000FF
+#define APB_SARADC_RSTB_WAIT_M  ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
+#define APB_SARADC_RSTB_WAIT_V  0xFF
+#define APB_SARADC_RSTB_WAIT_S  8
+/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: .*/
+#define APB_SARADC_XPD_WAIT    0x000000FF
+#define APB_SARADC_XPD_WAIT_M  ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
+#define APB_SARADC_XPD_WAIT_V  0xFF
+#define APB_SARADC_XPD_WAIT_S  0
+
+#define APB_SARADC_SAR1_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x10)
+/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: .*/
+#define APB_SARADC_SAR1_STATUS    0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS_M  ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
+#define APB_SARADC_SAR1_STATUS_V  0xFFFFFFFF
+#define APB_SARADC_SAR1_STATUS_S  0
+
+#define APB_SARADC_SAR2_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x14)
+/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: .*/
+#define APB_SARADC_SAR2_STATUS    0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS_M  ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
+#define APB_SARADC_SAR2_STATUS_V  0xFFFFFFFF
+#define APB_SARADC_SAR2_STATUS_S  0
+
+#define APB_SARADC_SAR1_PATT_TAB1_REG          (DR_REG_APB_SARADC_BASE + 0x18)
+/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: item 0 ~ 3 for pattern table 1 (each item one byte).*/
+#define APB_SARADC_SAR1_PATT_TAB1    0x00FFFFFF
+#define APB_SARADC_SAR1_PATT_TAB1_M  ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S))
+#define APB_SARADC_SAR1_PATT_TAB1_V  0xFFFFFF
+#define APB_SARADC_SAR1_PATT_TAB1_S  0
+
+#define APB_SARADC_SAR1_PATT_TAB2_REG          (DR_REG_APB_SARADC_BASE + 0x1C)
+/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Item 4 ~ 7 for pattern table 1 (each item one byte).*/
+#define APB_SARADC_SAR1_PATT_TAB2    0x00FFFFFF
+#define APB_SARADC_SAR1_PATT_TAB2_M  ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S))
+#define APB_SARADC_SAR1_PATT_TAB2_V  0xFFFFFF
+#define APB_SARADC_SAR1_PATT_TAB2_S  0
+
+#define APB_SARADC_SAR1_PATT_TAB3_REG          (DR_REG_APB_SARADC_BASE + 0x20)
+/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Item 8 ~ 11 for pattern table 1 (each item one byte).*/
+#define APB_SARADC_SAR1_PATT_TAB3    0x00FFFFFF
+#define APB_SARADC_SAR1_PATT_TAB3_M  ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S))
+#define APB_SARADC_SAR1_PATT_TAB3_V  0xFFFFFF
+#define APB_SARADC_SAR1_PATT_TAB3_S  0
+
+#define APB_SARADC_SAR1_PATT_TAB4_REG          (DR_REG_APB_SARADC_BASE + 0x24)
+/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Item 12 ~ 15 for pattern table 1 (each item one byte).*/
+#define APB_SARADC_SAR1_PATT_TAB4    0x00FFFFFF
+#define APB_SARADC_SAR1_PATT_TAB4_M  ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S))
+#define APB_SARADC_SAR1_PATT_TAB4_V  0xFFFFFF
+#define APB_SARADC_SAR1_PATT_TAB4_S  0
+
+#define APB_SARADC_SAR2_PATT_TAB1_REG          (DR_REG_APB_SARADC_BASE + 0x28)
+/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: item 0 ~ 3 for pattern table 2 (each item one byte).*/
+#define APB_SARADC_SAR2_PATT_TAB1    0x00FFFFFF
+#define APB_SARADC_SAR2_PATT_TAB1_M  ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S))
+#define APB_SARADC_SAR2_PATT_TAB1_V  0xFFFFFF
+#define APB_SARADC_SAR2_PATT_TAB1_S  0
+
+#define APB_SARADC_SAR2_PATT_TAB2_REG          (DR_REG_APB_SARADC_BASE + 0x2C)
+/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Item 4 ~ 7 for pattern table 2 (each item one byte).*/
+#define APB_SARADC_SAR2_PATT_TAB2    0x00FFFFFF
+#define APB_SARADC_SAR2_PATT_TAB2_M  ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S))
+#define APB_SARADC_SAR2_PATT_TAB2_V  0xFFFFFF
+#define APB_SARADC_SAR2_PATT_TAB2_S  0
+
+#define APB_SARADC_SAR2_PATT_TAB3_REG          (DR_REG_APB_SARADC_BASE + 0x30)
+/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Item 8 ~ 11 for pattern table 2 (each item one byte).*/
+#define APB_SARADC_SAR2_PATT_TAB3    0x00FFFFFF
+#define APB_SARADC_SAR2_PATT_TAB3_M  ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S))
+#define APB_SARADC_SAR2_PATT_TAB3_V  0xFFFFFF
+#define APB_SARADC_SAR2_PATT_TAB3_S  0
+
+#define APB_SARADC_SAR2_PATT_TAB4_REG          (DR_REG_APB_SARADC_BASE + 0x34)
+/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: Item 12 ~ 15 for pattern table 2 (each item one byte).*/
+#define APB_SARADC_SAR2_PATT_TAB4    0x00FFFFFF
+#define APB_SARADC_SAR2_PATT_TAB4_M  ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S))
+#define APB_SARADC_SAR2_PATT_TAB4_V  0xFFFFFF
+#define APB_SARADC_SAR2_PATT_TAB4_S  0
+
+#define APB_SARADC_APB_ADC_ARB_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x38)
+/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: adc2 arbiter uses fixed priority.*/
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY    (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M  (BIT(12))
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V  0x1
+#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S  12
+/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
+/*description: Set adc2 arbiter wifi priority.*/
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY    0x00000003
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M  ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S  10
+/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
+/*description: Set adc2 arbiter rtc priority.*/
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY    0x00000003
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M  ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S  8
+/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Set adc2 arbiterapb priority.*/
+#define APB_SARADC_ADC_ARB_APB_PRIORITY    0x00000003
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_M  ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_V  0x3
+#define APB_SARADC_ADC_ARB_APB_PRIORITY_S  6
+/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: adc2 arbiter force grant.*/
+#define APB_SARADC_ADC_ARB_GRANT_FORCE    (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_M  (BIT(5))
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_GRANT_FORCE_S  5
+/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable wifi controller.*/
+#define APB_SARADC_ADC_ARB_WIFI_FORCE    (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_M  (BIT(4))
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_WIFI_FORCE_S  4
+/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable rtc controller.*/
+#define APB_SARADC_ADC_ARB_RTC_FORCE    (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_M  (BIT(3))
+#define APB_SARADC_ADC_ARB_RTC_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_RTC_FORCE_S  3
+/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enableapb controller.*/
+#define APB_SARADC_ADC_ARB_APB_FORCE    (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_M  (BIT(2))
+#define APB_SARADC_ADC_ARB_APB_FORCE_V  0x1
+#define APB_SARADC_ADC_ARB_APB_FORCE_S  2
+
+#define APB_SARADC_FILTER_CTRL0_REG          (DR_REG_APB_SARADC_BASE + 0x3C)
+/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable apb_adc1_filter.*/
+#define APB_SARADC_FILTER_RESET    (BIT(31))
+#define APB_SARADC_FILTER_RESET_M  (BIT(31))
+#define APB_SARADC_FILTER_RESET_V  0x1
+#define APB_SARADC_FILTER_RESET_S  31
+/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[23:19] ;default: 5'hd ; */
+/*description: apb_adc1_filter_factor.*/
+#define APB_SARADC_FILTER_CHANNEL0    0x0000001F
+#define APB_SARADC_FILTER_CHANNEL0_M  ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
+#define APB_SARADC_FILTER_CHANNEL0_V  0x1F
+#define APB_SARADC_FILTER_CHANNEL0_S  19
+/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[18:14] ;default: 5'hd ; */
+/*description: .*/
+#define APB_SARADC_FILTER_CHANNEL1    0x0000001F
+#define APB_SARADC_FILTER_CHANNEL1_M  ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
+#define APB_SARADC_FILTER_CHANNEL1_V  0x1F
+#define APB_SARADC_FILTER_CHANNEL1_S  14
+
+#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x40)
+/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: .*/
+#define APB_SARADC_ADC1_DATA    0x0001FFFF
+#define APB_SARADC_ADC1_DATA_M  ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
+#define APB_SARADC_ADC1_DATA_V  0x1FFFF
+#define APB_SARADC_ADC1_DATA_S  0
+
+#define APB_SARADC_THRES0_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x44)
+/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
+/*description: saradc1's thres0 monitor thres.*/
+#define APB_SARADC_THRES0_LOW    0x00001FFF
+#define APB_SARADC_THRES0_LOW_M  ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
+#define APB_SARADC_THRES0_LOW_V  0x1FFF
+#define APB_SARADC_THRES0_LOW_S  18
+/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
+/*description: saradc1's thres0 monitor thres.*/
+#define APB_SARADC_THRES0_HIGH    0x00001FFF
+#define APB_SARADC_THRES0_HIGH_M  ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
+#define APB_SARADC_THRES0_HIGH_V  0x1FFF
+#define APB_SARADC_THRES0_HIGH_S  5
+/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_CHANNEL    0x0000001F
+#define APB_SARADC_THRES0_CHANNEL_M  ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
+#define APB_SARADC_THRES0_CHANNEL_V  0x1F
+#define APB_SARADC_THRES0_CHANNEL_S  0
+
+#define APB_SARADC_THRES1_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x48)
+/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
+/*description: saradc1's thres0 monitor thres.*/
+#define APB_SARADC_THRES1_LOW    0x00001FFF
+#define APB_SARADC_THRES1_LOW_M  ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
+#define APB_SARADC_THRES1_LOW_V  0x1FFF
+#define APB_SARADC_THRES1_LOW_S  18
+/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
+/*description: saradc1's thres0 monitor thres.*/
+#define APB_SARADC_THRES1_HIGH    0x00001FFF
+#define APB_SARADC_THRES1_HIGH_M  ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
+#define APB_SARADC_THRES1_HIGH_V  0x1FFF
+#define APB_SARADC_THRES1_HIGH_S  5
+/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_CHANNEL    0x0000001F
+#define APB_SARADC_THRES1_CHANNEL_M  ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
+#define APB_SARADC_THRES1_CHANNEL_V  0x1F
+#define APB_SARADC_THRES1_CHANNEL_S  0
+
+#define APB_SARADC_THRES_CTRL_REG          (DR_REG_APB_SARADC_BASE + 0x58)
+/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_EN    (BIT(31))
+#define APB_SARADC_THRES0_EN_M  (BIT(31))
+#define APB_SARADC_THRES0_EN_V  0x1
+#define APB_SARADC_THRES0_EN_S  31
+/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_EN    (BIT(30))
+#define APB_SARADC_THRES1_EN_M  (BIT(30))
+#define APB_SARADC_THRES1_EN_V  0x1
+#define APB_SARADC_THRES1_EN_S  30
+/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES2_EN    (BIT(29))
+#define APB_SARADC_THRES2_EN_M  (BIT(29))
+#define APB_SARADC_THRES2_EN_V  0x1
+#define APB_SARADC_THRES2_EN_S  29
+/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES3_EN    (BIT(28))
+#define APB_SARADC_THRES3_EN_M  (BIT(28))
+#define APB_SARADC_THRES3_EN_V  0x1
+#define APB_SARADC_THRES3_EN_S  28
+/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: .*/
+#define APB_SARADC_THRES_ALL_EN    (BIT(27))
+#define APB_SARADC_THRES_ALL_EN_M  (BIT(27))
+#define APB_SARADC_THRES_ALL_EN_V  0x1
+#define APB_SARADC_THRES_ALL_EN_S  27
+
+#define APB_SARADC_INT_ENA_REG          (DR_REG_APB_SARADC_BASE + 0x5C)
+/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_ADC1_DONE_INT_ENA    (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ENA_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_ENA_S  31
+/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_ADC2_DONE_INT_ENA    (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ENA_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_ENA_S  30
+/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_HIGH_INT_ENA    (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ENA_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_ENA_S  29
+/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_HIGH_INT_ENA    (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ENA_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_ENA_S  28
+/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_LOW_INT_ENA    (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ENA_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_ENA_S  27
+/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_LOW_INT_ENA    (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ENA_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_ENA_S  26
+
+#define APB_SARADC_INT_RAW_REG          (DR_REG_APB_SARADC_BASE + 0x60)
+/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_ADC1_DONE_INT_RAW    (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_RAW_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_RAW_S  31
+/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_ADC2_DONE_INT_RAW    (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_RAW_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_RAW_S  30
+/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_HIGH_INT_RAW    (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_RAW_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_RAW_S  29
+/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_HIGH_INT_RAW    (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_RAW_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_RAW_S  28
+/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_LOW_INT_RAW    (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_RAW_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_RAW_S  27
+/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_LOW_INT_RAW    (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_RAW_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_RAW_S  26
+
+#define APB_SARADC_INT_ST_REG          (DR_REG_APB_SARADC_BASE + 0x64)
+/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_ADC1_DONE_INT_ST    (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_ST_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_ST_S  31
+/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_ADC2_DONE_INT_ST    (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_ST_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_ST_S  30
+/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_HIGH_INT_ST    (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_ST_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_ST_S  29
+/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_HIGH_INT_ST    (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_ST_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_ST_S  28
+/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_LOW_INT_ST    (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_ST_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_ST_S  27
+/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_LOW_INT_ST    (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_ST_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_ST_S  26
+
+#define APB_SARADC_INT_CLR_REG          (DR_REG_APB_SARADC_BASE + 0x68)
+/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_ADC1_DONE_INT_CLR    (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR_M  (BIT(31))
+#define APB_SARADC_ADC1_DONE_INT_CLR_V  0x1
+#define APB_SARADC_ADC1_DONE_INT_CLR_S  31
+/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_ADC2_DONE_INT_CLR    (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR_M  (BIT(30))
+#define APB_SARADC_ADC2_DONE_INT_CLR_V  0x1
+#define APB_SARADC_ADC2_DONE_INT_CLR_S  30
+/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_HIGH_INT_CLR    (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR_M  (BIT(29))
+#define APB_SARADC_THRES0_HIGH_INT_CLR_V  0x1
+#define APB_SARADC_THRES0_HIGH_INT_CLR_S  29
+/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_HIGH_INT_CLR    (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR_M  (BIT(28))
+#define APB_SARADC_THRES1_HIGH_INT_CLR_V  0x1
+#define APB_SARADC_THRES1_HIGH_INT_CLR_S  28
+/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES0_LOW_INT_CLR    (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR_M  (BIT(27))
+#define APB_SARADC_THRES0_LOW_INT_CLR_V  0x1
+#define APB_SARADC_THRES0_LOW_INT_CLR_S  27
+/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define APB_SARADC_THRES1_LOW_INT_CLR    (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR_M  (BIT(26))
+#define APB_SARADC_THRES1_LOW_INT_CLR_V  0x1
+#define APB_SARADC_THRES1_LOW_INT_CLR_S  26
+
+#define APB_SARADC_DMA_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x6C)
+/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: enable apb_adc use spi_dma.*/
+#define APB_SARADC_APB_ADC_TRANS    (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_M  (BIT(31))
+#define APB_SARADC_APB_ADC_TRANS_V  0x1
+#define APB_SARADC_APB_ADC_TRANS_S  31
+/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: reset_apb_adc_state.*/
+#define APB_SARADC_APB_ADC_RESET_FSM    (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_M  (BIT(30))
+#define APB_SARADC_APB_ADC_RESET_FSM_V  0x1
+#define APB_SARADC_APB_ADC_RESET_FSM_S  30
+/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
+/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num.*/
+#define APB_SARADC_APB_ADC_EOF_NUM    0x0000FFFF
+#define APB_SARADC_APB_ADC_EOF_NUM_M  ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
+#define APB_SARADC_APB_ADC_EOF_NUM_V  0xFFFF
+#define APB_SARADC_APB_ADC_EOF_NUM_S  0
+
+#define APB_SARADC_APB_ADC_CLKM_CONF_REG          (DR_REG_APB_SARADC_BASE + 0x70)
+/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
+/*description: Set this bit to enable clk_apll.*/
+#define APB_SARADC_CLK_SEL    0x00000003
+#define APB_SARADC_CLK_SEL_M  ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
+#define APB_SARADC_CLK_SEL_V  0x3
+#define APB_SARADC_CLK_SEL_S  21
+/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: .*/
+#define APB_SARADC_CLK_EN    (BIT(20))
+#define APB_SARADC_CLK_EN_M  (BIT(20))
+#define APB_SARADC_CLK_EN_V  0x1
+#define APB_SARADC_CLK_EN_S  20
+/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
+/*description: Fractional clock divider denominator value.*/
+#define APB_SARADC_CLKM_DIV_A    0x0000003F
+#define APB_SARADC_CLKM_DIV_A_M  ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
+#define APB_SARADC_CLKM_DIV_A_V  0x3F
+#define APB_SARADC_CLKM_DIV_A_S  14
+/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
+/*description: Fractional clock divider numerator value.*/
+#define APB_SARADC_CLKM_DIV_B    0x0000003F
+#define APB_SARADC_CLKM_DIV_B_M  ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
+#define APB_SARADC_CLKM_DIV_B_V  0x3F
+#define APB_SARADC_CLKM_DIV_B_S  8
+/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
+/*description: Integral I2S clock divider value.*/
+#define APB_SARADC_CLKM_DIV_NUM    0x000000FF
+#define APB_SARADC_CLKM_DIV_NUM_M  ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
+#define APB_SARADC_CLKM_DIV_NUM_V  0xFF
+#define APB_SARADC_CLKM_DIV_NUM_S  0
+
+#define APB_SARADC_APB_SARADC2_DATA_STATUS_REG          (DR_REG_APB_SARADC_BASE + 0x78)
+/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: .*/
+#define APB_SARADC_ADC2_DATA    0x0001FFFF
+#define APB_SARADC_ADC2_DATA_M  ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
+#define APB_SARADC_ADC2_DATA_V  0x1FFFF
+#define APB_SARADC_ADC2_DATA_S  0
+
+#define APB_SARADC_APB_CTRL_DATE_REG          (DR_REG_APB_SARADC_BASE + 0x3FC)
+/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02101180 ; */
+/*description: .*/
+#define APB_SARADC_APB_CTRL_DATE    0xFFFFFFFF
+#define APB_SARADC_APB_CTRL_DATE_M  ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S))
+#define APB_SARADC_APB_CTRL_DATE_V  0xFFFFFFFF
+#define APB_SARADC_APB_CTRL_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_SARADC_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/apb_saradc_struct.h b/components/soc/esp32s3/register/soc/apb_saradc_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/apb_saradc_struct.h
rename to components/soc/esp32s3/register/soc/apb_saradc_struct.h
diff --git a/components/soc/esp32s3/register/soc/assist_debug_reg.h b/components/soc/esp32s3/register/soc/assist_debug_reg.h
new file mode 100644
index 00000000000..35a89cadabb
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/assist_debug_reg.h
@@ -0,0 +1,1330 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_ASSIST_DEBUG_REG_H_
+#define _SOC_ASSIST_DEBUG_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ASSIST_DEBUG_CORE_0_INTERRUPT_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTERRUPT_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTERRUPT_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+
+#define ASSIST_DEBUG_CORE_0_INTERRUPT_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC)
+/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
+/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1C)
+/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x2C)
+/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/* ASSIST_DEBUG_CORE_0_AREA_SP : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
+
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x34)
+/* ASSIST_DEBUG_CORE_0_AREA_PC : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x38)
+/* ASSIST_DEBUG_CORE_0_SP_UNSTABLE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE    0x000000FF
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_M  ((ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V)<<(ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S))
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V  0xFF
+#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x3C)
+/* ASSIST_DEBUG_CORE_0_SP_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x40)
+/* ASSIST_DEBUG_CORE_0_SP_MAX : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x44)
+/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_SP_PC_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x48)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x4C)
+/* ASSIST_DEBUG_CORE_0_RCD_RECORDING : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING    (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x50)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x54)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS    0x000000FF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V  0xFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x58)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x5C)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x60)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x64)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x68)
+/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S  0
+
+#define ASSIST_DEBUG_CORE_0_RCD_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x6C)
+/* ASSIST_DEBUG_CORE_0_RCD_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_RCD_SP    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_SP_M  ((ASSIST_DEBUG_CORE_0_RCD_SP_V)<<(ASSIST_DEBUG_CORE_0_RCD_SP_S))
+#define ASSIST_DEBUG_CORE_0_RCD_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_RCD_SP_S  0
+
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x70)
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x74)
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
+/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x78)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(22))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (BIT(22))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  22
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x003FFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x3FFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x7C)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000FFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0xFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x80)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x84)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(22))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (BIT(22))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  22
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x003FFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x3FFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x88)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000FFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0xFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  0
+
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x8C)
+/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
+
+#define ASSIST_DEBUG_CORE_1_INTERRUPT_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x90)
+/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_S  11
+/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_S  10
+/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S  9
+/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S  8
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S  7
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S  6
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S  5
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S  4
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S  3
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S  2
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S  1
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S  0
+
+#define ASSIST_DEBUG_CORE_1_INTERRUPT_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x94)
+/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_S  11
+/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_S  10
+/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S  9
+/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S  8
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S  7
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S  6
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S  5
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S  4
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S  3
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S  2
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S  1
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S  0
+
+#define ASSIST_DEBUG_CORE_1_INTERRUPT_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x98)
+/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_S  11
+/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_S  10
+/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S  9
+/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S  8
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S  7
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S  6
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S  5
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S  4
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S  3
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S  2
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S  1
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S  0
+
+#define ASSIST_DEBUG_CORE_1_INTERRUPT_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x9C)
+/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_S  11
+/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_S  10
+/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M  (BIT(9))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S  9
+/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M  (BIT(8))
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S  8
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M  (BIT(7))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S  7
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M  (BIT(6))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S  6
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M  (BIT(5))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S  5
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M  (BIT(4))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S  4
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S  3
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S  2
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S  1
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA0)
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA4)
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xA8)
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xAC)
+/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S))
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB0)
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB4)
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xB8)
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xBC)
+/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC0)
+/* ASSIST_DEBUG_CORE_1_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_PC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PC_M  ((ASSIST_DEBUG_CORE_1_AREA_PC_V)<<(ASSIST_DEBUG_CORE_1_AREA_PC_S))
+#define ASSIST_DEBUG_CORE_1_AREA_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_PC_S  0
+
+#define ASSIST_DEBUG_CORE_1_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC4)
+/* ASSIST_DEBUG_CORE_1_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_AREA_SP    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_SP_M  ((ASSIST_DEBUG_CORE_1_AREA_SP_V)<<(ASSIST_DEBUG_CORE_1_AREA_SP_S))
+#define ASSIST_DEBUG_CORE_1_AREA_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_AREA_SP_S  0
+
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC8)
+/* ASSIST_DEBUG_CORE_1_SP_UNSTABLE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE    0x000000FF
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_M  ((ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V)<<(ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S))
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V  0xFF
+#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S  0
+
+#define ASSIST_DEBUG_CORE_1_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xCC)
+/* ASSIST_DEBUG_CORE_1_SP_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_MIN_M  ((ASSIST_DEBUG_CORE_1_SP_MIN_V)<<(ASSIST_DEBUG_CORE_1_SP_MIN_S))
+#define ASSIST_DEBUG_CORE_1_SP_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_MIN_S  0
+
+#define ASSIST_DEBUG_CORE_1_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD0)
+/* ASSIST_DEBUG_CORE_1_SP_MAX : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_MAX_M  ((ASSIST_DEBUG_CORE_1_SP_MAX_V)<<(ASSIST_DEBUG_CORE_1_SP_MAX_S))
+#define ASSIST_DEBUG_CORE_1_SP_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_MAX_S  0
+
+#define ASSIST_DEBUG_CORE_1_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD4)
+/* ASSIST_DEBUG_CORE_1_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_SP_PC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_PC_M  ((ASSIST_DEBUG_CORE_1_SP_PC_V)<<(ASSIST_DEBUG_CORE_1_SP_PC_S))
+#define ASSIST_DEBUG_CORE_1_SP_PC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_SP_PC_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xD8)
+/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_V  0x1
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xDC)
+/* ASSIST_DEBUG_CORE_1_RCD_RECORDING : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING    (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_M  (BIT(0))
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_V  0x1
+#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE0)
+/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE4)
+/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS    0x000000FF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V  0xFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xE8)
+/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xEC)
+/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF0)
+/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF4)
+/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xF8)
+/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_M  ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V)<<(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S))
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S  0
+
+#define ASSIST_DEBUG_CORE_1_RCD_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xFC)
+/* ASSIST_DEBUG_CORE_1_RCD_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_RCD_SP    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_SP_M  ((ASSIST_DEBUG_CORE_1_RCD_SP_V)<<(ASSIST_DEBUG_CORE_1_RCD_SP_S))
+#define ASSIST_DEBUG_CORE_1_RCD_SP_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_RCD_SP_S  0
+
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x100)
+/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S  25
+/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S  24
+/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0    0x00FFFFFF
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S  0
+
+#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x104)
+/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S  25
+/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1    (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M  (BIT(24))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S  24
+/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1    0x00FFFFFF
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
+#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S  0
+
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x108)
+/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0    (BIT(22))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M  (BIT(22))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S  22
+/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0    0x003FFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V  0x3FFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S  0
+
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x10C)
+/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0    0x0000FFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V  0xFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S  0
+
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x110)
+/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S  0
+
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x114)
+/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1    (BIT(22))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M  (BIT(22))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S  22
+/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[21:0] ;default: 24'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1    0x003FFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V  0x3FFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S  0
+
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x118)
+/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[15:0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1    0x0000FFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V  0xFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S  0
+
+#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x11C)
+/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1    0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S))
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
+#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S  0
+
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x120)
+/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: ~20'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0xFFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x124)
+/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: ~20'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0xFFFFF
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
+
+#define ASSIST_DEBUG_LOG_SETTING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x128)
+/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE    (BIT(6))
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M  (BIT(6))
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S  6
+/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MODE    0x00000007
+#define ASSIST_DEBUG_LOG_MODE_M  ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
+#define ASSIST_DEBUG_LOG_MODE_V  0x7
+#define ASSIST_DEBUG_LOG_MODE_S  3
+/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_ENA    0x00000007
+#define ASSIST_DEBUG_LOG_ENA_M  ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
+#define ASSIST_DEBUG_LOG_ENA_V  0x7
+#define ASSIST_DEBUG_LOG_ENA_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x12C)
+/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_0    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_0_M  ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
+#define ASSIST_DEBUG_LOG_DATA_0_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_0_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x130)
+/* ASSIST_DEBUG_LOG_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_1    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_1_M  ((ASSIST_DEBUG_LOG_DATA_1_V)<<(ASSIST_DEBUG_LOG_DATA_1_S))
+#define ASSIST_DEBUG_LOG_DATA_1_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_1_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x134)
+/* ASSIST_DEBUG_LOG_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_2    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_2_M  ((ASSIST_DEBUG_LOG_DATA_2_V)<<(ASSIST_DEBUG_LOG_DATA_2_S))
+#define ASSIST_DEBUG_LOG_DATA_2_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_2_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x138)
+/* ASSIST_DEBUG_LOG_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_3    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_3_M  ((ASSIST_DEBUG_LOG_DATA_3_V)<<(ASSIST_DEBUG_LOG_DATA_3_S))
+#define ASSIST_DEBUG_LOG_DATA_3_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_DATA_3_S  0
+
+#define ASSIST_DEBUG_LOG_DATA_MASK_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x13C)
+/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_DATA_SIZE    0x0000FFFF
+#define ASSIST_DEBUG_LOG_DATA_SIZE_M  ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
+#define ASSIST_DEBUG_LOG_DATA_SIZE_V  0xFFFF
+#define ASSIST_DEBUG_LOG_DATA_SIZE_S  0
+
+#define ASSIST_DEBUG_LOG_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x140)
+/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MIN    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MIN_M  ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
+#define ASSIST_DEBUG_LOG_MIN_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MIN_S  0
+
+#define ASSIST_DEBUG_LOG_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x144)
+/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MAX    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MAX_M  ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
+#define ASSIST_DEBUG_LOG_MAX_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MAX_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_START_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x148)
+/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_START    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_START_M  ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
+#define ASSIST_DEBUG_LOG_MEM_START_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_START_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_END_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x14C)
+/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_END    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_END_M  ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
+#define ASSIST_DEBUG_LOG_MEM_END_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_END_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x150)
+/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR    0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M  ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V  0xFFFFFFFF
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S  0
+
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x154)
+/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG    (BIT(0))
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M  (BIT(0))
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S  0
+
+#define ASSIST_DEBUG_REG_DATE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
+/* ASSIST_DEBUG_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003040 ; */
+/*description: .*/
+#define ASSIST_DEBUG_REG_DATE    0x0FFFFFFF
+#define ASSIST_DEBUG_REG_DATE_M  ((ASSIST_DEBUG_REG_DATE_V)<<(ASSIST_DEBUG_REG_DATE_S))
+#define ASSIST_DEBUG_REG_DATE_V  0xFFFFFFF
+#define ASSIST_DEBUG_REG_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_ASSIST_DEBUG_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/assist_debug_struct.h b/components/soc/esp32s3/register/soc/assist_debug_struct.h
new file mode 100644
index 00000000000..a66c4ecb772
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/assist_debug_struct.h
@@ -0,0 +1,458 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_ASSIST_DEBUG_STRUCT_H_
+#define _SOC_ASSIST_DEBUG_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct assist_debug_dev_s {
+    union {
+        struct {
+            uint32_t core_0_area_dram0_0_rd        :    1;
+            uint32_t core_0_area_dram0_0_wr        :    1;
+            uint32_t core_0_area_dram0_1_rd        :    1;
+            uint32_t core_0_area_dram0_1_wr        :    1;
+            uint32_t core_0_area_pif_0_rd          :    1;
+            uint32_t core_0_area_pif_0_wr          :    1;
+            uint32_t core_0_area_pif_1_rd          :    1;
+            uint32_t core_0_area_pif_1_wr          :    1;
+            uint32_t core_0_sp_spill_min           :    1;
+            uint32_t core_0_sp_spill_max           :    1;
+            uint32_t core_0_iram0_exception_monitor:    1;
+            uint32_t core_0_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_interrupt_ena;
+    union {
+        struct {
+            uint32_t core_0_area_dram0_0_rd        :    1;
+            uint32_t core_0_area_dram0_0_wr        :    1;
+            uint32_t core_0_area_dram0_1_rd        :    1;
+            uint32_t core_0_area_dram0_1_wr        :    1;
+            uint32_t core_0_area_pif_0_rd          :    1;
+            uint32_t core_0_area_pif_0_wr          :    1;
+            uint32_t core_0_area_pif_1_rd          :    1;
+            uint32_t core_0_area_pif_1_wr          :    1;
+            uint32_t core_0_sp_spill_min           :    1;
+            uint32_t core_0_sp_spill_max           :    1;
+            uint32_t core_0_iram0_exception_monitor:    1;
+            uint32_t core_0_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_interrupt_raw;
+    union {
+        struct {
+            uint32_t core_0_area_dram0_0_rd        :    1;
+            uint32_t core_0_area_dram0_0_wr        :    1;
+            uint32_t core_0_area_dram0_1_rd        :    1;
+            uint32_t core_0_area_dram0_1_wr        :    1;
+            uint32_t core_0_area_pif_0_rd          :    1;
+            uint32_t core_0_area_pif_0_wr          :    1;
+            uint32_t core_0_area_pif_1_rd          :    1;
+            uint32_t core_0_area_pif_1_wr          :    1;
+            uint32_t core_0_sp_spill_min           :    1;
+            uint32_t core_0_sp_spill_max           :    1;
+            uint32_t core_0_iram0_exception_monitor:    1;
+            uint32_t core_0_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_interrupt_rls;
+    union {
+        struct {
+            uint32_t core_0_area_dram0_0_rd        :    1;
+            uint32_t core_0_area_dram0_0_wr        :    1;
+            uint32_t core_0_area_dram0_1_rd        :    1;
+            uint32_t core_0_area_dram0_1_wr        :    1;
+            uint32_t core_0_area_pif_0_rd          :    1;
+            uint32_t core_0_area_pif_0_wr          :    1;
+            uint32_t core_0_area_pif_1_rd          :    1;
+            uint32_t core_0_area_pif_1_wr          :    1;
+            uint32_t core_0_sp_spill_min           :    1;
+            uint32_t core_0_sp_spill_max           :    1;
+            uint32_t core_0_iram0_exception_monitor:    1;
+            uint32_t core_0_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_interrupt_clr;
+    uint32_t core_0_area_dram0_0_min;
+    uint32_t core_0_area_dram0_0_max;
+    uint32_t core_0_area_dram0_1_min;
+    uint32_t core_0_area_dram0_1_max;
+    uint32_t core_0_area_pif_0_min;
+    uint32_t core_0_area_pif_0_max;
+    uint32_t core_0_area_pif_1_min;
+    uint32_t core_0_area_pif_1_max;
+    uint32_t core_0_area_sp;
+    uint32_t core_0_area_pc;
+    union {
+        struct {
+            uint32_t core_0_sp_unstable            :    8;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } core_0_sp_unstable;
+    uint32_t core_0_sp_min;
+    uint32_t core_0_sp_max;
+    uint32_t core_0_sp_pc;
+    union {
+        struct {
+            uint32_t core_0_rcd_pdebugenable       :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_rcd_pdebugenable;
+    union {
+        struct {
+            uint32_t core_0_rcd_recording          :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_rcd_recording;
+    uint32_t core_0_rcd_pdebuginst;
+    union {
+        struct {
+            uint32_t core_0_rcd_pdebugstatus       :    8;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } core_0_rcd_pdebugstatus;
+    uint32_t core_0_rcd_pdebugdata;
+    uint32_t core_0_rcd_pdebugpc;
+    uint32_t core_0_rcd_pdebugls0stat;
+    uint32_t core_0_rcd_pdebugls0addr;
+    uint32_t core_0_rcd_pdebugls0data;
+    uint32_t core_0_rcd_sp;
+    union {
+        struct {
+            uint32_t core_0_iram0_recording_addr_0 :    24;
+            uint32_t core_0_iram0_recording_wr_0   :    1;
+            uint32_t core_0_iram0_recording_loadstore_0:    1;
+            uint32_t reserved26                    :    6;
+        };
+        uint32_t val;
+    } core_0_iram0_exception_monitor_0;
+    union {
+        struct {
+            uint32_t core_0_iram0_recording_addr_1 :    24;
+            uint32_t core_0_iram0_recording_wr_1   :    1;
+            uint32_t core_0_iram0_recording_loadstore_1:    1;
+            uint32_t reserved26                    :    6;
+        };
+        uint32_t val;
+    } core_0_iram0_exception_monitor_1;
+    union {
+        struct {
+            uint32_t core_0_dram0_recording_addr_0 :    22;
+            uint32_t core_0_dram0_recording_wr_0   :    1;
+            uint32_t reserved23                    :    9;
+        };
+        uint32_t val;
+    } core_0_dram0_exception_monitor_0;
+    union {
+        struct {
+            uint32_t core_0_dram0_recording_byteen_0:    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } core_0_dram0_exception_monitor_1;
+    uint32_t core_0_dram0_exception_monitor_2;
+    union {
+        struct {
+            uint32_t core_0_dram0_recording_addr_1 :    22;
+            uint32_t core_0_dram0_recording_wr_1   :    1;
+            uint32_t reserved23                    :    9;
+        };
+        uint32_t val;
+    } core_0_dram0_exception_monitor_3;
+    union {
+        struct {
+            uint32_t core_0_dram0_recording_byteen_1:    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } core_0_dram0_exception_monitor_4;
+    uint32_t core_0_dram0_exception_monitor_5;
+    union {
+        struct {
+            uint32_t core_1_area_dram0_0_rd        :    1;
+            uint32_t core_1_area_dram0_0_wr        :    1;
+            uint32_t core_1_area_dram0_1_rd        :    1;
+            uint32_t core_1_area_dram0_1_wr        :    1;
+            uint32_t core_1_area_pif_0_rd          :    1;
+            uint32_t core_1_area_pif_0_wr          :    1;
+            uint32_t core_1_area_pif_1_rd          :    1;
+            uint32_t core_1_area_pif_1_wr          :    1;
+            uint32_t core_1_sp_spill_min           :    1;
+            uint32_t core_1_sp_spill_max           :    1;
+            uint32_t core_1_iram0_exception_monitor:    1;
+            uint32_t core_1_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_1_interrupt_ena;
+    union {
+        struct {
+            uint32_t core_1_area_dram0_0_rd        :    1;
+            uint32_t core_1_area_dram0_0_wr        :    1;
+            uint32_t core_1_area_dram0_1_rd        :    1;
+            uint32_t core_1_area_dram0_1_wr        :    1;
+            uint32_t core_1_area_pif_0_rd          :    1;
+            uint32_t core_1_area_pif_0_wr          :    1;
+            uint32_t core_1_area_pif_1_rd          :    1;
+            uint32_t core_1_area_pif_1_wr          :    1;
+            uint32_t core_1_sp_spill_min           :    1;
+            uint32_t core_1_sp_spill_max           :    1;
+            uint32_t core_1_iram0_exception_monitor:    1;
+            uint32_t core_1_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_1_interrupt_raw;
+    union {
+        struct {
+            uint32_t core_1_area_dram0_0_rd        :    1;
+            uint32_t core_1_area_dram0_0_wr        :    1;
+            uint32_t core_1_area_dram0_1_rd        :    1;
+            uint32_t core_1_area_dram0_1_wr        :    1;
+            uint32_t core_1_area_pif_0_rd          :    1;
+            uint32_t core_1_area_pif_0_wr          :    1;
+            uint32_t core_1_area_pif_1_rd          :    1;
+            uint32_t core_1_area_pif_1_wr          :    1;
+            uint32_t core_1_sp_spill_min           :    1;
+            uint32_t core_1_sp_spill_max           :    1;
+            uint32_t core_1_iram0_exception_monitor:    1;
+            uint32_t core_1_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_1_interrupt_rls;
+    union {
+        struct {
+            uint32_t core_1_area_dram0_0_rd        :    1;
+            uint32_t core_1_area_dram0_0_wr        :    1;
+            uint32_t core_1_area_dram0_1_rd        :    1;
+            uint32_t core_1_area_dram0_1_wr        :    1;
+            uint32_t core_1_area_pif_0_rd          :    1;
+            uint32_t core_1_area_pif_0_wr          :    1;
+            uint32_t core_1_area_pif_1_rd          :    1;
+            uint32_t core_1_area_pif_1_wr          :    1;
+            uint32_t core_1_sp_spill_min           :    1;
+            uint32_t core_1_sp_spill_max           :    1;
+            uint32_t core_1_iram0_exception_monitor:    1;
+            uint32_t core_1_dram0_exception_monitor:    1;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_1_interrupt_clr;
+    uint32_t core_1_area_dram0_0_min;
+    uint32_t core_1_area_dram0_0_max;
+    uint32_t core_1_area_dram0_1_min;
+    uint32_t core_1_area_dram0_1_max;
+    uint32_t core_1_area_pif_0_min;
+    uint32_t core_1_area_pif_0_max;
+    uint32_t core_1_area_pif_1_min;
+    uint32_t core_1_area_pif_1_max;
+    uint32_t core_1_area_pc;
+    uint32_t core_1_area_sp;
+    union {
+        struct {
+            uint32_t core_1_sp_unstable            :    8;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } core_1_sp_unstable;
+    uint32_t core_1_sp_min;
+    uint32_t core_1_sp_max;
+    uint32_t core_1_sp_pc;
+    union {
+        struct {
+            uint32_t core_1_rcd_pdebugenable       :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_rcd_pdebugenable;
+    union {
+        struct {
+            uint32_t core_1_rcd_recording          :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_rcd_recording;
+    uint32_t core_1_rcd_pdebuginst;
+    union {
+        struct {
+            uint32_t core_1_rcd_pdebugstatus       :    8;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } core_1_rcd_pdebugstatus;
+    uint32_t core_1_rcd_pdebugdata;
+    uint32_t core_1_rcd_pdebugpc;
+    uint32_t core_1_rcd_pdebugls0stat;
+    uint32_t core_1_rcd_pdebugls0addr;
+    uint32_t core_1_rcd_pdebugls0data;
+    uint32_t core_1_rcd_sp;
+    union {
+        struct {
+            uint32_t core_1_iram0_recording_addr_0 :    24;
+            uint32_t core_1_iram0_recording_wr_0   :    1;
+            uint32_t core_1_iram0_recording_loadstore_0:    1;
+            uint32_t reserved26                    :    6;
+        };
+        uint32_t val;
+    } core_1_iram0_exception_monitor_0;
+    union {
+        struct {
+            uint32_t core_1_iram0_recording_addr_1 :    24;
+            uint32_t core_1_iram0_recording_wr_1   :    1;
+            uint32_t core_1_iram0_recording_loadstore_1:    1;
+            uint32_t reserved26                    :    6;
+        };
+        uint32_t val;
+    } core_1_iram0_exception_monitor_1;
+    union {
+        struct {
+            uint32_t core_1_dram0_recording_addr_0 :    22;
+            uint32_t core_1_dram0_recording_wr_0   :    1;
+            uint32_t reserved23                    :    9;
+        };
+        uint32_t val;
+    } core_1_dram0_exception_monitor_0;
+    union {
+        struct {
+            uint32_t core_1_dram0_recording_byteen_0:    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } core_1_dram0_exception_monitor_1;
+    uint32_t core_1_dram0_exception_monitor_2;
+    union {
+        struct {
+            uint32_t core_1_dram0_recording_addr_1 :    22;
+            uint32_t core_1_dram0_recording_wr_1   :    1;
+            uint32_t reserved23                    :    9;
+        };
+        uint32_t val;
+    } core_1_dram0_exception_monitor_3;
+    union {
+        struct {
+            uint32_t core_1_dram0_recording_byteen_1:    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } core_1_dram0_exception_monitor_4;
+    uint32_t core_1_dram0_exception_monitor_5;
+    union {
+        struct {
+            uint32_t core_x_iram0_dram0_limit_cycle_0:    20;
+            uint32_t reserved20                    :    12;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_exception_monitor_0;
+    union {
+        struct {
+            uint32_t core_x_iram0_dram0_limit_cycle_1:    20;
+            uint32_t reserved20                    :    12;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_exception_monitor_1;
+    union {
+        struct {
+            uint32_t log                           :    3;
+            uint32_t log_mode                      :    3;
+            uint32_t log_mem_loopble               :    1;
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } log_setting;
+    uint32_t log_data_0;
+    uint32_t log_data_1;
+    uint32_t log_data_2;
+    uint32_t log_data_3;
+    union {
+        struct {
+            uint32_t log_data_size                 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } log_data_mask;
+    uint32_t log_min;
+    uint32_t log_max;
+    uint32_t log_mem_start;
+    uint32_t log_mem_end;
+    uint32_t log_mem_writing_addr;
+    union {
+        struct {
+            uint32_t log_mem_full_flag             :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } log_mem_full_flag;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t assist_debug_reg_date         :    28;
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } reg_date;
+} assist_debug_dev_t;
+extern assist_debug_dev_t ASSIST_DEBUG;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_ASSIST_DEBUG_STRUCT_H_ */
diff --git a/components/soc/esp32s3/register/soc/efuse_reg.h b/components/soc/esp32s3/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..a4f5cff40dc
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/efuse_reg.h
@@ -0,0 +1,2913 @@
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/efuse_defs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register 0.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Disable programming of individual eFuses.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register 1.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Set this bit to disable reading from BlOCK4-10.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0;
+ *  Set this bit to disable boot from RTC RAM.
+ */
+#define EFUSE_DIS_RTC_RAM_BOOT    (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S)
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x00000001U
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
+ *  Set this bit to disable Icache.
+ */
+#define EFUSE_DIS_ICACHE    (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
+#define EFUSE_DIS_ICACHE_V  0x00000001U
+#define EFUSE_DIS_ICACHE_S  8
+/** EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0;
+ *  Set this bit to disable Dcache.
+ */
+#define EFUSE_DIS_DCACHE    (BIT(9))
+#define EFUSE_DIS_DCACHE_M  (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S)
+#define EFUSE_DIS_DCACHE_V  0x00000001U
+#define EFUSE_DIS_DCACHE_S  9
+/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0;
+ *  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6,
+ *  7).
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/** EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0;
+ *  Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6,
+ *  7).
+ */
+#define EFUSE_DIS_DOWNLOAD_DCACHE    (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_M  (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S)
+#define EFUSE_DIS_DOWNLOAD_DCACHE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_DCACHE_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Set this bit to disable the function that forces chip into download mode.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_DIS_USB_OTG : RO; bitpos: [13]; default: 0;
+ *  Set this bit to disable USB function.
+ */
+#define EFUSE_DIS_USB_OTG    (BIT(13))
+#define EFUSE_DIS_USB_OTG_M  (EFUSE_DIS_USB_OTG_V << EFUSE_DIS_USB_OTG_S)
+#define EFUSE_DIS_USB_OTG_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Set this bit to disable CAN function.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_DIS_APP_CPU : RO; bitpos: [15]; default: 0;
+ *  Disable app cpu.
+ */
+#define EFUSE_DIS_APP_CPU    (BIT(15))
+#define EFUSE_DIS_APP_CPU_M  (EFUSE_DIS_APP_CPU_V << EFUSE_DIS_APP_CPU_S)
+#define EFUSE_DIS_APP_CPU_V  0x00000001U
+#define EFUSE_DIS_APP_CPU_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG
+ *  can be enabled in HMAC module.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Set this bit to disable flash encryption when in download boot modes.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored
+ *  in eFuse.
+ */
+#define EFUSE_USB_DREFH    0x00000003U
+#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
+#define EFUSE_USB_DREFH_V  0x00000003U
+#define EFUSE_USB_DREFH_S  21
+/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
+ *  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
+ *  stored in eFuse.
+ */
+#define EFUSE_USB_DREFL    0x00000003U
+#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
+#define EFUSE_USB_DREFL_V  0x00000003U
+#define EFUSE_USB_DREFL_S  23
+/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
+ *  Set this bit to exchange USB D+ and D- pins.
+ */
+#define EFUSE_USB_EXCHG_PINS    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
+#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_S  25
+/** EFUSE_USB_EXT_PHY_ENABLE : RO; bitpos: [26]; default: 0;
+ *  Set this bit to enable external PHY.
+ */
+#define EFUSE_USB_EXT_PHY_ENABLE    (BIT(26))
+#define EFUSE_USB_EXT_PHY_ENABLE_M  (EFUSE_USB_EXT_PHY_ENABLE_V << EFUSE_USB_EXT_PHY_ENABLE_S)
+#define EFUSE_USB_EXT_PHY_ENABLE_V  0x00000001U
+#define EFUSE_USB_EXT_PHY_ENABLE_S  26
+/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0;
+ *  Bluetooth GPIO signal output security level control.
+ */
+#define EFUSE_BTLC_GPIO_ENABLE    0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_M  (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S)
+#define EFUSE_BTLC_GPIO_ENABLE_V  0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_S  27
+/** EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0;
+ *  SPI regulator switches current limit mode.
+ */
+#define EFUSE_VDD_SPI_MODECURLIM    (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_M  (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S)
+#define EFUSE_VDD_SPI_MODECURLIM_V  0x00000001U
+#define EFUSE_VDD_SPI_MODECURLIM_S  29
+/** EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0;
+ *  SPI regulator high voltage reference.
+ */
+#define EFUSE_VDD_SPI_DREFH    0x00000003U
+#define EFUSE_VDD_SPI_DREFH_M  (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S)
+#define EFUSE_VDD_SPI_DREFH_V  0x00000003U
+#define EFUSE_VDD_SPI_DREFH_S  30
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register 2.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0;
+ *  SPI regulator medium voltage reference.
+ */
+#define EFUSE_VDD_SPI_DREFM    0x00000003U
+#define EFUSE_VDD_SPI_DREFM_M  (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S)
+#define EFUSE_VDD_SPI_DREFM_V  0x00000003U
+#define EFUSE_VDD_SPI_DREFM_S  0
+/** EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0;
+ *  SPI regulator low voltage reference.
+ */
+#define EFUSE_VDD_SPI_DREFL    0x00000003U
+#define EFUSE_VDD_SPI_DREFL_M  (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S)
+#define EFUSE_VDD_SPI_DREFL_V  0x00000003U
+#define EFUSE_VDD_SPI_DREFL_S  2
+/** EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0;
+ *  SPI regulator power up signal.
+ */
+#define EFUSE_VDD_SPI_XPD    (BIT(4))
+#define EFUSE_VDD_SPI_XPD_M  (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S)
+#define EFUSE_VDD_SPI_XPD_V  0x00000001U
+#define EFUSE_VDD_SPI_XPD_S  4
+/** EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0;
+ *  SPI regulator output is short connected to VDD3P3_RTC_IO.
+ */
+#define EFUSE_VDD_SPI_TIEH    (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_M  (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S)
+#define EFUSE_VDD_SPI_TIEH_V  0x00000001U
+#define EFUSE_VDD_SPI_TIEH_S  5
+/** EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0;
+ *  Set this bit and force to use the configuration of eFuse to configure VDD_SPI.
+ */
+#define EFUSE_VDD_SPI_FORCE    (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_M  (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S)
+#define EFUSE_VDD_SPI_FORCE_V  0x00000001U
+#define EFUSE_VDD_SPI_FORCE_S  6
+/** EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0;
+ *  Set SPI regulator to 0 to configure init[1:0]=0.
+ */
+#define EFUSE_VDD_SPI_EN_INIT    (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_M  (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S)
+#define EFUSE_VDD_SPI_EN_INIT_V  0x00000001U
+#define EFUSE_VDD_SPI_EN_INIT_S  7
+/** EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0;
+ *  Set SPI regulator to 1 to enable output current limit.
+ */
+#define EFUSE_VDD_SPI_ENCURLIM    (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_M  (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S)
+#define EFUSE_VDD_SPI_ENCURLIM_V  0x00000001U
+#define EFUSE_VDD_SPI_ENCURLIM_S  8
+/** EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0;
+ *  Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).
+ */
+#define EFUSE_VDD_SPI_DCURLIM    0x00000007U
+#define EFUSE_VDD_SPI_DCURLIM_M  (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S)
+#define EFUSE_VDD_SPI_DCURLIM_V  0x00000007U
+#define EFUSE_VDD_SPI_DCURLIM_S  9
+/** EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0;
+ *  Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.
+ */
+#define EFUSE_VDD_SPI_INIT    0x00000003U
+#define EFUSE_VDD_SPI_INIT_M  (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S)
+#define EFUSE_VDD_SPI_INIT_V  0x00000003U
+#define EFUSE_VDD_SPI_INIT_S  12
+/** EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0;
+ *  Prevents SPI regulator from overshoot.
+ */
+#define EFUSE_VDD_SPI_DCAP    0x00000003U
+#define EFUSE_VDD_SPI_DCAP_M  (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S)
+#define EFUSE_VDD_SPI_DCAP_V  0x00000003U
+#define EFUSE_VDD_SPI_DCAP_S  14
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
+ *  80000. 2: 160000. 3:320000.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+ *  number of 1: disable.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  Set this bit to enable revoking first secure boot key.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  Set this bit to enable revoking second secure boot key.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  Set this bit to enable revoking third secure boot key.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  Purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  Purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register 3.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  Purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  Purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  Purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  Purpose of Key5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [19:16]; default: 0;
+ *  Reserved (used for four backups method).
+ */
+#define EFUSE_RPT4_RESERVED0    0x0000000FU
+#define EFUSE_RPT4_RESERVED0_M  (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S)
+#define EFUSE_RPT4_RESERVED0_V  0x0000000FU
+#define EFUSE_RPT4_RESERVED0_S  16
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  Set this bit to enable secure boot.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  Set this bit to enable revoking aggressive secure boot.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [22]; default: 0;
+ *  Set this bit to disable function of usb switch to jtag in module of usb device.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(22))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  22
+/** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [23]; default: 0;
+ *  Set this bit to disable usb device.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG    (BIT(23))
+#define EFUSE_DIS_USB_SERIAL_JTAG_M  (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_S  23
+/** EFUSE_STRAP_JTAG_SEL : RO; bitpos: [24]; default: 0;
+ *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+ */
+#define EFUSE_STRAP_JTAG_SEL    (BIT(24))
+#define EFUSE_STRAP_JTAG_SEL_M  (EFUSE_STRAP_JTAG_SEL_V << EFUSE_STRAP_JTAG_SEL_S)
+#define EFUSE_STRAP_JTAG_SEL_V  0x00000001U
+#define EFUSE_STRAP_JTAG_SEL_S  24
+/** EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0;
+ *  This bit is used to switch internal PHY and external PHY for USB OTG and USB
+ *  Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to
+ *  USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to
+ *  USB Device.
+ */
+#define EFUSE_USB_PHY_SEL    (BIT(25))
+#define EFUSE_USB_PHY_SEL_M  (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S)
+#define EFUSE_USB_PHY_SEL_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_S  25
+/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [27:26]; default: 0;
+ *  Sample delay configuration of power glitch.
+ */
+#define EFUSE_POWER_GLITCH_DSENSE    0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_M  (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S)
+#define EFUSE_POWER_GLITCH_DSENSE_V  0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_S  26
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  Configures flash waiting time after power-up, in unit of ms. If the value is less
+ *  than 15, the waiting time is the configurable value.  Otherwise, the waiting time
+ *  is twice the configurable value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register 4.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0;
+ *  Disable direct boot mode
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(1))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  1
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
+ *  Selects the default UART print channel. 0: UART0. 1: UART1.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(2))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  2
+/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0;
+ *  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
+ *  use 16to17 byte mode.
+ */
+#define EFUSE_FLASH_ECC_MODE    (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_M  (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S)
+#define EFUSE_FLASH_ECC_MODE_V  0x00000001U
+#define EFUSE_FLASH_ECC_MODE_S  3
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  Set this bit to disable UART download mode through USB.
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  Set this bit to enable secure UART download mode.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8
+ *  is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0;
+ *  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+ */
+#define EFUSE_PIN_POWER_SELECTION    (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_M  (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S)
+#define EFUSE_PIN_POWER_SELECTION_V  0x00000001U
+#define EFUSE_PIN_POWER_SELECTION_S  8
+/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0;
+ *  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+ */
+#define EFUSE_FLASH_TYPE    (BIT(9))
+#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V  0x00000001U
+#define EFUSE_FLASH_TYPE_S  9
+/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0;
+ *  Set Flash page size.
+ */
+#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
+#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0;
+ *  Set 1 to enable ECC for flash boot.
+ */
+#define EFUSE_FLASH_ECC_EN    (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
+#define EFUSE_FLASH_ECC_EN_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_S  12
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
+ *  Set this bit to force ROM code to send a resume command during SPI boot.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0;
+ *  Secure version (used by ESP-IDF anti-rollback feature).
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  14
+/** EFUSE_POWERGLITCH_EN : RO; bitpos: [30]; default: 0;
+ *  Set this bit to enable power glitch function.
+ */
+#define EFUSE_POWERGLITCH_EN    (BIT(30))
+#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_S  30
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : R; bitpos: [31]; default: 0;
+ *  Set this bit to disable download through USB-OTG
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(31))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  31
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register 5.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0;
+ *  Disables check of wafer version major
+ */
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR    (BIT(0))
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M  (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S  0
+/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0;
+ *  Disables check of blk version major
+ */
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR    (BIT(1))
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M  (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V  0x00000001U
+#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S  1
+/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_0_162    0x003FFFFFU
+#define EFUSE_RESERVED_0_162_M  (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S)
+#define EFUSE_RESERVED_0_162_V  0x003FFFFFU
+#define EFUSE_RESERVED_0_162_S  2
+
+/** EFUSE_RD_MAC_SPI_SYS_0_REG register
+ *  BLOCK1 data register 0.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SPI_SYS_1_REG register
+ *  BLOCK1 data register 1.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [21:16]; default: 0;
+ *  SPI_PAD_configure CLK
+ */
+#define EFUSE_SPI_PAD_CONFIG_CLK    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_CLK_M  (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S)
+#define EFUSE_SPI_PAD_CONFIG_CLK_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_CLK_S  16
+/** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [27:22]; default: 0;
+ *  SPI_PAD_configure Q(D1)
+ */
+#define EFUSE_SPI_PAD_CONFIG_Q    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_Q_M  (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S)
+#define EFUSE_SPI_PAD_CONFIG_Q_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_Q_S  22
+/** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [31:28]; default: 0;
+ *  SPI_PAD_configure D(D0)
+ */
+#define EFUSE_SPI_PAD_CONFIG_D    0x0000000FU
+#define EFUSE_SPI_PAD_CONFIG_D_M  (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S)
+#define EFUSE_SPI_PAD_CONFIG_D_V  0x0000000FU
+#define EFUSE_SPI_PAD_CONFIG_D_S  28
+
+/** EFUSE_RD_MAC_SPI_SYS_2_REG register
+ *  BLOCK1 data register 2.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: Stores the first part of SPI_PAD_CONF..*/
+#define EFUSE_SPI_PAD_CONF_1    0xFFFFFFFF
+#define EFUSE_SPI_PAD_CONF_1_M  ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S))
+#define EFUSE_SPI_PAD_CONF_1_V  0xFFFFFFFF
+#define EFUSE_SPI_PAD_CONF_1_S  0
+/** EFUSE_SPI_PAD_CONFIG_D_1 : R; bitpos: [1:0]; default: 0;
+ *  SPI_PAD_configure D(D0)
+ */
+#define EFUSE_SPI_PAD_CONFIG_D_1    0x00000003U
+#define EFUSE_SPI_PAD_CONFIG_D_1_M  (EFUSE_SPI_PAD_CONFIG_D_1_V << EFUSE_SPI_PAD_CONFIG_D_1_S)
+#define EFUSE_SPI_PAD_CONFIG_D_1_V  0x00000003U
+#define EFUSE_SPI_PAD_CONFIG_D_1_S  0
+/** EFUSE_SPI_PAD_CONFIG_CS : R; bitpos: [7:2]; default: 0;
+ *  SPI_PAD_configure CS
+ */
+#define EFUSE_SPI_PAD_CONFIG_CS    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_CS_M  (EFUSE_SPI_PAD_CONFIG_CS_V << EFUSE_SPI_PAD_CONFIG_CS_S)
+#define EFUSE_SPI_PAD_CONFIG_CS_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_CS_S  2
+/** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [13:8]; default: 0;
+ *  SPI_PAD_configure HD(D3)
+ */
+#define EFUSE_SPI_PAD_CONFIG_HD    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_HD_M  (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S)
+#define EFUSE_SPI_PAD_CONFIG_HD_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_HD_S  8
+/** EFUSE_SPI_PAD_CONFIG_WP : R; bitpos: [19:14]; default: 0;
+ *  SPI_PAD_configure WP(D2)
+ */
+#define EFUSE_SPI_PAD_CONFIG_WP    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_WP_M  (EFUSE_SPI_PAD_CONFIG_WP_V << EFUSE_SPI_PAD_CONFIG_WP_S)
+#define EFUSE_SPI_PAD_CONFIG_WP_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_WP_S  14
+/** EFUSE_SPI_PAD_CONFIG_DQS : R; bitpos: [25:20]; default: 0;
+ *  SPI_PAD_configure DQS
+ */
+#define EFUSE_SPI_PAD_CONFIG_DQS    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_DQS_M  (EFUSE_SPI_PAD_CONFIG_DQS_V << EFUSE_SPI_PAD_CONFIG_DQS_S)
+#define EFUSE_SPI_PAD_CONFIG_DQS_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_DQS_S  20
+/** EFUSE_SPI_PAD_CONFIG_D4 : R; bitpos: [31:26]; default: 0;
+ *  SPI_PAD_configure D4
+ */
+#define EFUSE_SPI_PAD_CONFIG_D4    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D4_M  (EFUSE_SPI_PAD_CONFIG_D4_V << EFUSE_SPI_PAD_CONFIG_D4_S)
+#define EFUSE_SPI_PAD_CONFIG_D4_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D4_S  26
+
+/** EFUSE_RD_MAC_SPI_SYS_3_REG register
+ *  BLOCK1 data register 3.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_SPI_PAD_CONFIG_D5 : R; bitpos: [5:0]; default: 0;
+ *  SPI_PAD_configure D5
+ */
+#define EFUSE_SPI_PAD_CONFIG_D5    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D5_M  (EFUSE_SPI_PAD_CONFIG_D5_V << EFUSE_SPI_PAD_CONFIG_D5_S)
+#define EFUSE_SPI_PAD_CONFIG_D5_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D5_S  0
+/** EFUSE_SPI_PAD_CONFIG_D6 : R; bitpos: [11:6]; default: 0;
+ *  SPI_PAD_configure D6
+ */
+#define EFUSE_SPI_PAD_CONFIG_D6    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D6_M  (EFUSE_SPI_PAD_CONFIG_D6_V << EFUSE_SPI_PAD_CONFIG_D6_S)
+#define EFUSE_SPI_PAD_CONFIG_D6_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D6_S  6
+/** EFUSE_SPI_PAD_CONFIG_D7 : R; bitpos: [17:12]; default: 0;
+ *  SPI_PAD_configure D7
+ */
+#define EFUSE_SPI_PAD_CONFIG_D7    0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D7_M  (EFUSE_SPI_PAD_CONFIG_D7_V << EFUSE_SPI_PAD_CONFIG_D7_S)
+#define EFUSE_SPI_PAD_CONFIG_D7_V  0x0000003FU
+#define EFUSE_SPI_PAD_CONFIG_D7_S  12
+/** EFUSE_WAFER_VERSION_MINOR_LO : R; bitpos: [20:18]; default: 0;
+ *  WAFER_VERSION_MINOR least significant bits
+ */
+#define EFUSE_WAFER_VERSION_MINOR_LO    0x00000007U
+#define EFUSE_WAFER_VERSION_MINOR_LO_M  (EFUSE_WAFER_VERSION_MINOR_LO_V << EFUSE_WAFER_VERSION_MINOR_LO_S)
+#define EFUSE_WAFER_VERSION_MINOR_LO_V  0x00000007U
+#define EFUSE_WAFER_VERSION_MINOR_LO_S  18
+/** EFUSE_PKG_VERSION : R; bitpos: [23:21]; default: 0;
+ *  Package version
+ */
+#define EFUSE_PKG_VERSION    0x00000007U
+#define EFUSE_PKG_VERSION_M  (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
+#define EFUSE_PKG_VERSION_V  0x00000007U
+#define EFUSE_PKG_VERSION_S  21
+/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0;
+ *  BLK_VERSION_MINOR
+ */
+#define EFUSE_BLK_VERSION_MINOR    0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_M  (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
+#define EFUSE_BLK_VERSION_MINOR_V  0x00000007U
+#define EFUSE_BLK_VERSION_MINOR_S  24
+/** EFUSE_FLASH_CAP : R; bitpos: [29:27]; default: 0;
+ *  Flash capacity
+ */
+#define EFUSE_FLASH_CAP    0x00000007U
+#define EFUSE_FLASH_CAP_M  (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
+#define EFUSE_FLASH_CAP_V  0x00000007U
+#define EFUSE_FLASH_CAP_S  27
+/** EFUSE_FLASH_TEMP : R; bitpos: [31:30]; default: 0;
+ *  Flash temperature
+ */
+#define EFUSE_FLASH_TEMP    0x00000003U
+#define EFUSE_FLASH_TEMP_M  (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
+#define EFUSE_FLASH_TEMP_V  0x00000003U
+#define EFUSE_FLASH_TEMP_S  30
+
+/** EFUSE_RD_MAC_SPI_SYS_4_REG register
+ *  BLOCK1 data register 4.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_FLASH_VENDOR : R; bitpos: [2:0]; default: 0;
+ *  Flash vendor
+ */
+#define EFUSE_FLASH_VENDOR    0x00000007U
+#define EFUSE_FLASH_VENDOR_M  (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
+#define EFUSE_FLASH_VENDOR_V  0x00000007U
+#define EFUSE_FLASH_VENDOR_S  0
+/** EFUSE_PSRAM_CAP : R; bitpos: [4:3]; default: 0;
+ *  PSRAM capacity
+ */
+#define EFUSE_PSRAM_CAP    0x00000003U
+#define EFUSE_PSRAM_CAP_M  (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S)
+#define EFUSE_PSRAM_CAP_V  0x00000003U
+#define EFUSE_PSRAM_CAP_S  3
+/** EFUSE_PSRAM_TEMP : R; bitpos: [6:5]; default: 0;
+ *  PSRAM temperature
+ */
+#define EFUSE_PSRAM_TEMP    0x00000003U
+#define EFUSE_PSRAM_TEMP_M  (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S)
+#define EFUSE_PSRAM_TEMP_V  0x00000003U
+#define EFUSE_PSRAM_TEMP_S  5
+/** EFUSE_PSRAM_VENDOR : R; bitpos: [8:7]; default: 0;
+ *  PSRAM vendor
+ */
+#define EFUSE_PSRAM_VENDOR    0x00000003U
+#define EFUSE_PSRAM_VENDOR_M  (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S)
+#define EFUSE_PSRAM_VENDOR_V  0x00000003U
+#define EFUSE_PSRAM_VENDOR_S  7
+/** EFUSE_RESERVED_1_137 : R; bitpos: [12:9]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_137    0x0000000FU
+#define EFUSE_RESERVED_1_137_M  (EFUSE_RESERVED_1_137_V << EFUSE_RESERVED_1_137_S)
+#define EFUSE_RESERVED_1_137_V  0x0000000FU
+#define EFUSE_RESERVED_1_137_S  9
+/** EFUSE_K_RTC_LDO : R; bitpos: [19:13]; default: 0;
+ *  BLOCK1 K_RTC_LDO
+ */
+#define EFUSE_K_RTC_LDO    0x0000007FU
+#define EFUSE_K_RTC_LDO_M  (EFUSE_K_RTC_LDO_V << EFUSE_K_RTC_LDO_S)
+#define EFUSE_K_RTC_LDO_V  0x0000007FU
+#define EFUSE_K_RTC_LDO_S  13
+/** EFUSE_K_DIG_LDO : R; bitpos: [26:20]; default: 0;
+ *  BLOCK1 K_DIG_LDO
+ */
+#define EFUSE_K_DIG_LDO    0x0000007FU
+#define EFUSE_K_DIG_LDO_M  (EFUSE_K_DIG_LDO_V << EFUSE_K_DIG_LDO_S)
+#define EFUSE_K_DIG_LDO_V  0x0000007FU
+#define EFUSE_K_DIG_LDO_S  20
+/** EFUSE_V_RTC_DBIAS20 : R; bitpos: [31:27]; default: 0;
+ *  BLOCK1 voltage of rtc dbias20
+ */
+#define EFUSE_V_RTC_DBIAS20    0x0000001FU
+#define EFUSE_V_RTC_DBIAS20_M  (EFUSE_V_RTC_DBIAS20_V << EFUSE_V_RTC_DBIAS20_S)
+#define EFUSE_V_RTC_DBIAS20_V  0x0000001FU
+#define EFUSE_V_RTC_DBIAS20_S  27
+
+/** EFUSE_RD_MAC_SPI_SYS_5_REG register
+ *  BLOCK1 data register 5.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_V_RTC_DBIAS20_1 : R; bitpos: [2:0]; default: 0;
+ *  BLOCK1 voltage of rtc dbias20
+ */
+#define EFUSE_V_RTC_DBIAS20_1    0x00000007U
+#define EFUSE_V_RTC_DBIAS20_1_M  (EFUSE_V_RTC_DBIAS20_1_V << EFUSE_V_RTC_DBIAS20_1_S)
+#define EFUSE_V_RTC_DBIAS20_1_V  0x00000007U
+#define EFUSE_V_RTC_DBIAS20_1_S  0
+/** EFUSE_V_DIG_DBIAS20 : R; bitpos: [10:3]; default: 0;
+ *  BLOCK1 voltage of digital dbias20
+ */
+#define EFUSE_V_DIG_DBIAS20    0x000000FFU
+#define EFUSE_V_DIG_DBIAS20_M  (EFUSE_V_DIG_DBIAS20_V << EFUSE_V_DIG_DBIAS20_S)
+#define EFUSE_V_DIG_DBIAS20_V  0x000000FFU
+#define EFUSE_V_DIG_DBIAS20_S  3
+/** EFUSE_DIG_DBIAS_HVT : R; bitpos: [15:11]; default: 0;
+ *  BLOCK1 digital dbias when hvt
+ */
+#define EFUSE_DIG_DBIAS_HVT    0x0000001FU
+#define EFUSE_DIG_DBIAS_HVT_M  (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S)
+#define EFUSE_DIG_DBIAS_HVT_V  0x0000001FU
+#define EFUSE_DIG_DBIAS_HVT_S  11
+/** EFUSE_RESERVED_1_176 : R; bitpos: [18:16]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_176    0x00000007U
+#define EFUSE_RESERVED_1_176_M  (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S)
+#define EFUSE_RESERVED_1_176_V  0x00000007U
+#define EFUSE_RESERVED_1_176_S  16
+/** EFUSE_PSRAM_CAP_3 : R; bitpos: [19]; default: 0;
+ *  PSRAM capacity bit 3
+ */
+#define EFUSE_PSRAM_CAP_3    (BIT(19))
+#define EFUSE_PSRAM_CAP_3_M  (EFUSE_PSRAM_CAP_3_V << EFUSE_PSRAM_CAP_3_S)
+#define EFUSE_PSRAM_CAP_3_V  0x00000001U
+#define EFUSE_PSRAM_CAP_3_S  19
+/** EFUSE_RESERVED_1_180 : R; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_1_180    0x00000007U
+#define EFUSE_RESERVED_1_180_M  (EFUSE_RESERVED_1_180_V << EFUSE_RESERVED_1_180_S)
+#define EFUSE_RESERVED_1_180_V  0x00000007U
+#define EFUSE_RESERVED_1_180_S  20
+/** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0;
+ *  WAFER_VERSION_MINOR most significant bit
+ */
+#define EFUSE_WAFER_VERSION_MINOR_HI    (BIT(23))
+#define EFUSE_WAFER_VERSION_MINOR_HI_M  (EFUSE_WAFER_VERSION_MINOR_HI_V << EFUSE_WAFER_VERSION_MINOR_HI_S)
+#define EFUSE_WAFER_VERSION_MINOR_HI_V  0x00000001U
+#define EFUSE_WAFER_VERSION_MINOR_HI_S  23
+/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [25:24]; default: 0;
+ *  WAFER_VERSION_MAJOR
+ */
+#define EFUSE_WAFER_VERSION_MAJOR    0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_M  (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
+#define EFUSE_WAFER_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_WAFER_VERSION_MAJOR_S  24
+/** EFUSE_ADC2_CAL_VOL_ATTEN3 : R; bitpos: [31:26]; default: 0;
+ *  ADC2 calibration voltage at atten3
+ */
+#define EFUSE_ADC2_CAL_VOL_ATTEN3    0x0000003FU
+#define EFUSE_ADC2_CAL_VOL_ATTEN3_M  (EFUSE_ADC2_CAL_VOL_ATTEN3_V << EFUSE_ADC2_CAL_VOL_ATTEN3_S)
+#define EFUSE_ADC2_CAL_VOL_ATTEN3_V  0x0000003FU
+#define EFUSE_ADC2_CAL_VOL_ATTEN3_S  26
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register 0 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_M  (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register 1 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_1    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_M  (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register 2 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_2    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_M  (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register 3 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
+ *  Optional unique 128-bit ID
+ */
+#define EFUSE_OPTIONAL_UNIQUE_ID_3    0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_M  (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_V  0xFFFFFFFFU
+#define EFUSE_OPTIONAL_UNIQUE_ID_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register 4 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [1:0]; default: 0;
+ *  BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
+ */
+#define EFUSE_BLK_VERSION_MAJOR    0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_M  (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
+#define EFUSE_BLK_VERSION_MAJOR_V  0x00000003U
+#define EFUSE_BLK_VERSION_MAJOR_S  0
+/** EFUSE_RESERVED_2_130 : R; bitpos: [3:2]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_130    0x00000003U
+#define EFUSE_RESERVED_2_130_M  (EFUSE_RESERVED_2_130_V << EFUSE_RESERVED_2_130_S)
+#define EFUSE_RESERVED_2_130_V  0x00000003U
+#define EFUSE_RESERVED_2_130_S  2
+/** EFUSE_TEMP_CALIB : R; bitpos: [12:4]; default: 0;
+ *  Temperature calibration data
+ */
+#define EFUSE_TEMP_CALIB    0x000001FFU
+#define EFUSE_TEMP_CALIB_M  (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S)
+#define EFUSE_TEMP_CALIB_V  0x000001FFU
+#define EFUSE_TEMP_CALIB_S  4
+/** EFUSE_OCODE : R; bitpos: [20:13]; default: 0;
+ *  ADC OCode
+ */
+#define EFUSE_OCODE    0x000000FFU
+#define EFUSE_OCODE_M  (EFUSE_OCODE_V << EFUSE_OCODE_S)
+#define EFUSE_OCODE_V  0x000000FFU
+#define EFUSE_OCODE_S  13
+/** EFUSE_ADC1_INIT_CODE_ATTEN0 : R; bitpos: [28:21]; default: 0;
+ *  ADC1 init code at atten0
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN0    0x000000FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_M  (EFUSE_ADC1_INIT_CODE_ATTEN0_V << EFUSE_ADC1_INIT_CODE_ATTEN0_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_V  0x000000FFU
+#define EFUSE_ADC1_INIT_CODE_ATTEN0_S  21
+/** EFUSE_ADC1_INIT_CODE_ATTEN1 : R; bitpos: [31:29]; default: 0;
+ *  ADC1 init code at atten1
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN1    0x00000007U
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_V  0x00000007U
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_S  29
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register 5 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_ADC1_INIT_CODE_ATTEN1_1 : R; bitpos: [2:0]; default: 0;
+ *  ADC1 init code at atten1
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1    0x00000007U
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_M  (EFUSE_ADC1_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_INIT_CODE_ATTEN1_1_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_V  0x00000007U
+#define EFUSE_ADC1_INIT_CODE_ATTEN1_1_S  0
+/** EFUSE_ADC1_INIT_CODE_ATTEN2 : R; bitpos: [8:3]; default: 0;
+ *  ADC1 init code at atten2
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN2    0x0000003FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_M  (EFUSE_ADC1_INIT_CODE_ATTEN2_V << EFUSE_ADC1_INIT_CODE_ATTEN2_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_V  0x0000003FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN2_S  3
+/** EFUSE_ADC1_INIT_CODE_ATTEN3 : R; bitpos: [14:9]; default: 0;
+ *  ADC1 init code at atten3
+ */
+#define EFUSE_ADC1_INIT_CODE_ATTEN3    0x0000003FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_M  (EFUSE_ADC1_INIT_CODE_ATTEN3_V << EFUSE_ADC1_INIT_CODE_ATTEN3_S)
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_V  0x0000003FU
+#define EFUSE_ADC1_INIT_CODE_ATTEN3_S  9
+/** EFUSE_ADC2_INIT_CODE_ATTEN0 : R; bitpos: [22:15]; default: 0;
+ *  ADC2 init code at atten0
+ */
+#define EFUSE_ADC2_INIT_CODE_ATTEN0    0x000000FFU
+#define EFUSE_ADC2_INIT_CODE_ATTEN0_M  (EFUSE_ADC2_INIT_CODE_ATTEN0_V << EFUSE_ADC2_INIT_CODE_ATTEN0_S)
+#define EFUSE_ADC2_INIT_CODE_ATTEN0_V  0x000000FFU
+#define EFUSE_ADC2_INIT_CODE_ATTEN0_S  15
+/** EFUSE_ADC2_INIT_CODE_ATTEN1 : R; bitpos: [28:23]; default: 0;
+ *  ADC2 init code at atten1
+ */
+#define EFUSE_ADC2_INIT_CODE_ATTEN1    0x0000003FU
+#define EFUSE_ADC2_INIT_CODE_ATTEN1_M  (EFUSE_ADC2_INIT_CODE_ATTEN1_V << EFUSE_ADC2_INIT_CODE_ATTEN1_S)
+#define EFUSE_ADC2_INIT_CODE_ATTEN1_V  0x0000003FU
+#define EFUSE_ADC2_INIT_CODE_ATTEN1_S  23
+/** EFUSE_ADC2_INIT_CODE_ATTEN2 : R; bitpos: [31:29]; default: 0;
+ *  ADC2 init code at atten2
+ */
+#define EFUSE_ADC2_INIT_CODE_ATTEN2    0x00000007U
+#define EFUSE_ADC2_INIT_CODE_ATTEN2_M  (EFUSE_ADC2_INIT_CODE_ATTEN2_V << EFUSE_ADC2_INIT_CODE_ATTEN2_S)
+#define EFUSE_ADC2_INIT_CODE_ATTEN2_V  0x00000007U
+#define EFUSE_ADC2_INIT_CODE_ATTEN2_S  29
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register 6 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_ADC2_INIT_CODE_ATTEN2_1 : R; bitpos: [2:0]; default: 0;
+ *  ADC2 init code at atten2
+ */
+#define EFUSE_ADC2_INIT_CODE_ATTEN2_1    0x00000007U
+#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_M  (EFUSE_ADC2_INIT_CODE_ATTEN2_1_V << EFUSE_ADC2_INIT_CODE_ATTEN2_1_S)
+#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_V  0x00000007U
+#define EFUSE_ADC2_INIT_CODE_ATTEN2_1_S  0
+/** EFUSE_ADC2_INIT_CODE_ATTEN3 : R; bitpos: [8:3]; default: 0;
+ *  ADC2 init code at atten3
+ */
+#define EFUSE_ADC2_INIT_CODE_ATTEN3    0x0000003FU
+#define EFUSE_ADC2_INIT_CODE_ATTEN3_M  (EFUSE_ADC2_INIT_CODE_ATTEN3_V << EFUSE_ADC2_INIT_CODE_ATTEN3_S)
+#define EFUSE_ADC2_INIT_CODE_ATTEN3_V  0x0000003FU
+#define EFUSE_ADC2_INIT_CODE_ATTEN3_S  3
+/** EFUSE_ADC1_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0;
+ *  ADC1 calibration voltage at atten0
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN0    0x000000FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_M  (EFUSE_ADC1_CAL_VOL_ATTEN0_V << EFUSE_ADC1_CAL_VOL_ATTEN0_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_V  0x000000FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN0_S  9
+/** EFUSE_ADC1_CAL_VOL_ATTEN1 : R; bitpos: [24:17]; default: 0;
+ *  ADC1 calibration voltage at atten1
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN1    0x000000FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_M  (EFUSE_ADC1_CAL_VOL_ATTEN1_V << EFUSE_ADC1_CAL_VOL_ATTEN1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_V  0x000000FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN1_S  17
+/** EFUSE_ADC1_CAL_VOL_ATTEN2 : R; bitpos: [31:25]; default: 0;
+ *  ADC1 calibration voltage at atten2
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN2    0x0000007FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_M  (EFUSE_ADC1_CAL_VOL_ATTEN2_V << EFUSE_ADC1_CAL_VOL_ATTEN2_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_V  0x0000007FU
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_S  25
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register 7 of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_ADC1_CAL_VOL_ATTEN2_1 : R; bitpos: [0]; default: 0;
+ *  ADC1 calibration voltage at atten2
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_1    (BIT(0))
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_M  (EFUSE_ADC1_CAL_VOL_ATTEN2_1_V << EFUSE_ADC1_CAL_VOL_ATTEN2_1_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_V  0x00000001U
+#define EFUSE_ADC1_CAL_VOL_ATTEN2_1_S  0
+/** EFUSE_ADC1_CAL_VOL_ATTEN3 : R; bitpos: [8:1]; default: 0;
+ *  ADC1 calibration voltage at atten3
+ */
+#define EFUSE_ADC1_CAL_VOL_ATTEN3    0x000000FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_M  (EFUSE_ADC1_CAL_VOL_ATTEN3_V << EFUSE_ADC1_CAL_VOL_ATTEN3_S)
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_V  0x000000FFU
+#define EFUSE_ADC1_CAL_VOL_ATTEN3_S  1
+/** EFUSE_ADC2_CAL_VOL_ATTEN0 : R; bitpos: [16:9]; default: 0;
+ *  ADC2 calibration voltage at atten0
+ */
+#define EFUSE_ADC2_CAL_VOL_ATTEN0    0x000000FFU
+#define EFUSE_ADC2_CAL_VOL_ATTEN0_M  (EFUSE_ADC2_CAL_VOL_ATTEN0_V << EFUSE_ADC2_CAL_VOL_ATTEN0_S)
+#define EFUSE_ADC2_CAL_VOL_ATTEN0_V  0x000000FFU
+#define EFUSE_ADC2_CAL_VOL_ATTEN0_S  9
+/** EFUSE_ADC2_CAL_VOL_ATTEN1 : R; bitpos: [23:17]; default: 0;
+ *  ADC2 calibration voltage at atten1
+ */
+#define EFUSE_ADC2_CAL_VOL_ATTEN1    0x0000007FU
+#define EFUSE_ADC2_CAL_VOL_ATTEN1_M  (EFUSE_ADC2_CAL_VOL_ATTEN1_V << EFUSE_ADC2_CAL_VOL_ATTEN1_S)
+#define EFUSE_ADC2_CAL_VOL_ATTEN1_V  0x0000007FU
+#define EFUSE_ADC2_CAL_VOL_ATTEN1_S  17
+/** EFUSE_ADC2_CAL_VOL_ATTEN2 : R; bitpos: [30:24]; default: 0;
+ *  ADC2 calibration voltage at atten2
+ */
+#define EFUSE_ADC2_CAL_VOL_ATTEN2    0x0000007FU
+#define EFUSE_ADC2_CAL_VOL_ATTEN2_M  (EFUSE_ADC2_CAL_VOL_ATTEN2_V << EFUSE_ADC2_CAL_VOL_ATTEN2_S)
+#define EFUSE_ADC2_CAL_VOL_ATTEN2_V  0x0000007FU
+#define EFUSE_ADC2_CAL_VOL_ATTEN2_S  24
+/** EFUSE_RESERVED_2_255 : R; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_2_255    (BIT(31))
+#define EFUSE_RESERVED_2_255_M  (EFUSE_RESERVED_2_255_V << EFUSE_RESERVED_2_255_S)
+#define EFUSE_RESERVED_2_255_V  0x00000001U
+#define EFUSE_RESERVED_2_255_S  31
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register 0 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register 1 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register 2 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register 3 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register 4 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register 5 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register 6 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_192    0x000000FFU
+#define EFUSE_RESERVED_3_192_M  (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
+#define EFUSE_RESERVED_3_192_V  0x000000FFU
+#define EFUSE_RESERVED_3_192_S  0
+/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_M  (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
+#define EFUSE_CUSTOM_MAC_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_S  8
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register 7 of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
+ *  Custom MAC
+ */
+#define EFUSE_CUSTOM_MAC_1    0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_M  (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
+#define EFUSE_CUSTOM_MAC_1_V  0x00FFFFFFU
+#define EFUSE_CUSTOM_MAC_1_S  0
+/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
+ *  reserved
+ */
+#define EFUSE_RESERVED_3_248    0x000000FFU
+#define EFUSE_RESERVED_3_248_M  (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
+#define EFUSE_RESERVED_3_248_V  0x000000FFU
+#define EFUSE_RESERVED_3_248_S  24
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register 0 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register 1 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register 2 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register 3 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register 4 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register 5 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register 6 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register 7 of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register 0 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register 1 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register 2 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register 3 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register 4 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register 5 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register 6 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register 7 of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register 0 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register 1 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register 2 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register 3 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register 4 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register 5 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register 6 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register 7 of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register 0 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register 1 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register 2 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register 3 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register 4 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register 5 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register 6 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register 7 of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register 0 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register 1 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register 2 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register 3 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register 4 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register 5 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register 6 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register 7 of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register 0 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register 1 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register 2 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register 3 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register 4 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register 5 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register 6 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register 7 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register 0 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 0th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register 1 of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 1st 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register 2 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 2nd 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register 3 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 3rd 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register 4 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 4th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register 5 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 5th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register 6 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 6th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register 7 of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the 7th 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR    (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M  (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S)
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S  7
+/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
+#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_ICACHE_ERR_S  8
+/** EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DCACHE_ERR    (BIT(9))
+#define EFUSE_DIS_DCACHE_ERR_M  (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S)
+#define EFUSE_DIS_DCACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_DCACHE_ERR_S  9
+/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  10
+/** EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR    (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_ERR    (BIT(13))
+#define EFUSE_DIS_USB_ERR_M  (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S)
+#define EFUSE_DIS_USB_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_ERR_S  13
+/** EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_CAN_ERR    (BIT(14))
+#define EFUSE_DIS_CAN_ERR_M  (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S)
+#define EFUSE_DIS_CAN_ERR_V  0x00000001U
+#define EFUSE_DIS_CAN_ERR_S  14
+/** EFUSE_DIS_APP_CPU_ERR : RO; bitpos: [15]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_APP_CPU_ERR    (BIT(15))
+#define EFUSE_DIS_APP_CPU_ERR_M  (EFUSE_DIS_APP_CPU_ERR_V << EFUSE_DIS_APP_CPU_ERR_S)
+#define EFUSE_DIS_APP_CPU_ERR_V  0x00000001U
+#define EFUSE_DIS_APP_CPU_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
+#define EFUSE_USB_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DREFH_ERR_S  21
+/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
+#define EFUSE_USB_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DREFL_ERR_S  23
+/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_ERR_S  25
+/** EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [26]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_EXT_PHY_ENABLE_ERR    (BIT(26))
+#define EFUSE_EXT_PHY_ENABLE_ERR_M  (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S)
+#define EFUSE_EXT_PHY_ENABLE_ERR_V  0x00000001U
+#define EFUSE_EXT_PHY_ENABLE_ERR_S  26
+/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_BTLC_GPIO_ENABLE_ERR    0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_M  (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S)
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_V  0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_S  27
+/** EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_MODECURLIM_ERR    (BIT(29))
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_M  (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S)
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_MODECURLIM_ERR_S  29
+/** EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_DREFH_ERR    0x00000003U
+#define EFUSE_VDD_SPI_DREFH_ERR_M  (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S)
+#define EFUSE_VDD_SPI_DREFH_ERR_V  0x00000003U
+#define EFUSE_VDD_SPI_DREFH_ERR_S  30
+
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_DREFM_ERR    0x00000003U
+#define EFUSE_VDD_SPI_DREFM_ERR_M  (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S)
+#define EFUSE_VDD_SPI_DREFM_ERR_V  0x00000003U
+#define EFUSE_VDD_SPI_DREFM_ERR_S  0
+/** EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_DREFL_ERR    0x00000003U
+#define EFUSE_VDD_SPI_DREFL_ERR_M  (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S)
+#define EFUSE_VDD_SPI_DREFL_ERR_V  0x00000003U
+#define EFUSE_VDD_SPI_DREFL_ERR_S  2
+/** EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_XPD_ERR    (BIT(4))
+#define EFUSE_VDD_SPI_XPD_ERR_M  (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S)
+#define EFUSE_VDD_SPI_XPD_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_XPD_ERR_S  4
+/** EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_TIEH_ERR    (BIT(5))
+#define EFUSE_VDD_SPI_TIEH_ERR_M  (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S)
+#define EFUSE_VDD_SPI_TIEH_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_TIEH_ERR_S  5
+/** EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_FORCE_ERR    (BIT(6))
+#define EFUSE_VDD_SPI_FORCE_ERR_M  (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S)
+#define EFUSE_VDD_SPI_FORCE_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_FORCE_ERR_S  6
+/** EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_EN_INIT_ERR    (BIT(7))
+#define EFUSE_VDD_SPI_EN_INIT_ERR_M  (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S)
+#define EFUSE_VDD_SPI_EN_INIT_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_EN_INIT_ERR_S  7
+/** EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_ENCURLIM_ERR    (BIT(8))
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_M  (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S)
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_ENCURLIM_ERR_S  8
+/** EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_DCURLIM_ERR    0x00000007U
+#define EFUSE_VDD_SPI_DCURLIM_ERR_M  (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S)
+#define EFUSE_VDD_SPI_DCURLIM_ERR_V  0x00000007U
+#define EFUSE_VDD_SPI_DCURLIM_ERR_S  9
+/** EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_INIT_ERR    0x00000003U
+#define EFUSE_VDD_SPI_INIT_ERR_M  (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S)
+#define EFUSE_VDD_SPI_INIT_ERR_V  0x00000003U
+#define EFUSE_VDD_SPI_INIT_ERR_S  12
+/** EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_DCAP_ERR    0x00000003U
+#define EFUSE_VDD_SPI_DCAP_ERR_M  (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S)
+#define EFUSE_VDD_SPI_DCAP_ERR_V  0x00000003U
+#define EFUSE_VDD_SPI_DCAP_ERR_S  14
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [19:16]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR    0x0000000FU
+#define EFUSE_RPT4_RESERVED0_ERR_M  (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S)
+#define EFUSE_RPT4_RESERVED0_ERR_V  0x0000000FU
+#define EFUSE_RPT4_RESERVED0_ERR_S  16
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [22]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(22))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  22
+/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [23]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_DEVICE_ERR    (BIT(23))
+#define EFUSE_DIS_USB_DEVICE_ERR_M  (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S)
+#define EFUSE_DIS_USB_DEVICE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DEVICE_ERR_S  23
+/** EFUSE_STRAP_JTAG_SEL_ERR : RO; bitpos: [24]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_STRAP_JTAG_SEL_ERR    (BIT(24))
+#define EFUSE_STRAP_JTAG_SEL_ERR_M  (EFUSE_STRAP_JTAG_SEL_ERR_V << EFUSE_STRAP_JTAG_SEL_ERR_S)
+#define EFUSE_STRAP_JTAG_SEL_ERR_V  0x00000001U
+#define EFUSE_STRAP_JTAG_SEL_ERR_S  24
+/** EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_PHY_SEL_ERR    (BIT(25))
+#define EFUSE_USB_PHY_SEL_ERR_M  (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S)
+#define EFUSE_USB_PHY_SEL_ERR_V  0x00000001U
+#define EFUSE_USB_PHY_SEL_ERR_S  25
+/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [27:26]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_POWER_GLITCH_DSENSE_ERR    0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_M  (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S)
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_V  0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_S  26
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M  (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S)
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S  1
+/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_UART_PRINT_CHANNEL_ERR    (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_ERR_M  (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S)
+#define EFUSE_UART_PRINT_CHANNEL_ERR_V  0x00000001U
+#define EFUSE_UART_PRINT_CHANNEL_ERR_S  2
+/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_ECC_MODE_ERR    (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_ERR_M  (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S)
+#define EFUSE_FLASH_ECC_MODE_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_MODE_ERR_S  3
+/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_PIN_POWER_SELECTION_ERR    (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_ERR_M  (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S)
+#define EFUSE_PIN_POWER_SELECTION_ERR_V  0x00000001U
+#define EFUSE_PIN_POWER_SELECTION_ERR_S  8
+/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_TYPE_ERR    (BIT(9))
+#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
+#define EFUSE_FLASH_TYPE_ERR_S  9
+/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S  10
+/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_ECC_EN_ERR    (BIT(12))
+#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
+#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_ERR_S  12
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  14
+/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [30]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(30))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_ERR_S  30
+/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED1_ERR    (BIT(31))
+#define EFUSE_RPT4_RESERVED1_ERR_M  (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S)
+#define EFUSE_RPT4_RESERVED1_ERR_V  0x00000001U
+#define EFUSE_RPT4_RESERVED1_ERR_S  31
+
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
+/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [23:0]; default: 0;
+ *  If any bits in this filed are 1, then it indicates a programming error.
+ */
+#define EFUSE_RPT4_RESERVED2_ERR    0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED2_ERR_M  (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S)
+#define EFUSE_RPT4_RESERVED2_ERR_V  0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED2_ERR_S  0
+
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
+#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
+/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SPI_8M_FAIL    (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
+#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
+#define EFUSE_MAC_SPI_8M_FAIL_S  3
+/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_NUM    0x00000007U
+#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
+#define EFUSE_SYS_PART1_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_NUM_S  4
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+ *  key0 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+ *  key1 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+ *  key2 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+ *  key3 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+ *  key4 failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  31
+
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART2_FAIL_S  7
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_EFUSE_MEM_FORCE_PD_M  (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_EFUSE_MEM_FORCE_PU_M  (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit and force to enable clock signal of eFuse memory.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0;
+ *  Indicates the number of error bits during programming BLOCK0.
+ */
+#define EFUSE_REPEAT_ERR_CNT    0x000000FFU
+#define EFUSE_REPEAT_ERR_CNT_M  (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S)
+#define EFUSE_REPEAT_ERR_CNT_V  0x000000FFU
+#define EFUSE_REPEAT_ERR_CNT_S  10
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
+ *  Configures the initial read time of eFuse.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 34607760;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/efuse_struct.h b/components/soc/esp32s3/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..a83ab2b03af
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/efuse_struct.h
@@ -0,0 +1,2543 @@
+/**
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: Read Data Register */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register 0.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Disable programming of individual eFuses.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register 1.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Set this bit to disable reading from BlOCK4-10.
+         */
+        uint32_t rd_dis:7;
+        /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0;
+         *  Set this bit to disable boot from RTC RAM.
+         */
+        uint32_t dis_rtc_ram_boot:1;
+        /** dis_icache : RO; bitpos: [8]; default: 0;
+         *  Set this bit to disable Icache.
+         */
+        uint32_t dis_icache:1;
+        /** dis_dcache : RO; bitpos: [9]; default: 0;
+         *  Set this bit to disable Dcache.
+         */
+        uint32_t dis_dcache:1;
+        /** dis_download_icache : RO; bitpos: [10]; default: 0;
+         *  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6,
+         *  7).
+         */
+        uint32_t dis_download_icache:1;
+        /** dis_download_dcache : RO; bitpos: [11]; default: 0;
+         *  Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6,
+         *  7).
+         */
+        uint32_t dis_download_dcache:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Set this bit to disable the function that forces chip into download mode.
+         */
+        uint32_t dis_force_download:1;
+        /** dis_usb_otg : RO; bitpos: [13]; default: 0;
+         *  Set this bit to disable USB function.
+         */
+        uint32_t dis_usb_otg:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Set this bit to disable CAN function.
+         */
+        uint32_t dis_twai:1;
+        /** dis_app_cpu : RO; bitpos: [15]; default: 0;
+         *  Disable app cpu.
+         */
+        uint32_t dis_app_cpu:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG
+         *  can be enabled in HMAC module.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Set this bit to disable flash encryption when in download boot modes.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
+         *  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored
+         *  in eFuse.
+         */
+        uint32_t usb_drefh:2;
+        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
+         *  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
+         *  stored in eFuse.
+         */
+        uint32_t usb_drefl:2;
+        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
+         *  Set this bit to exchange USB D+ and D- pins.
+         */
+        uint32_t usb_exchg_pins:1;
+        /** usb_ext_phy_enable : RO; bitpos: [26]; default: 0;
+         *  Set this bit to enable external PHY.
+         */
+        uint32_t usb_ext_phy_enable:1;
+        /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0;
+         *  Bluetooth GPIO signal output security level control.
+         */
+        uint32_t btlc_gpio_enable:2;
+        /** vdd_spi_modecurlim : RO; bitpos: [29]; default: 0;
+         *  SPI regulator switches current limit mode.
+         */
+        uint32_t vdd_spi_modecurlim:1;
+        /** vdd_spi_drefh : RO; bitpos: [31:30]; default: 0;
+         *  SPI regulator high voltage reference.
+         */
+        uint32_t vdd_spi_drefh:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register 2.
+ */
+typedef union {
+    struct {
+        /** vdd_spi_drefm : RO; bitpos: [1:0]; default: 0;
+         *  SPI regulator medium voltage reference.
+         */
+        uint32_t vdd_spi_drefm:2;
+        /** vdd_spi_drefl : RO; bitpos: [3:2]; default: 0;
+         *  SPI regulator low voltage reference.
+         */
+        uint32_t vdd_spi_drefl:2;
+        /** vdd_spi_xpd : RO; bitpos: [4]; default: 0;
+         *  SPI regulator power up signal.
+         */
+        uint32_t vdd_spi_xpd:1;
+        /** vdd_spi_tieh : RO; bitpos: [5]; default: 0;
+         *  SPI regulator output is short connected to VDD3P3_RTC_IO.
+         */
+        uint32_t vdd_spi_tieh:1;
+        /** vdd_spi_force : RO; bitpos: [6]; default: 0;
+         *  Set this bit and force to use the configuration of eFuse to configure VDD_SPI.
+         */
+        uint32_t vdd_spi_force:1;
+        /** vdd_spi_en_init : RO; bitpos: [7]; default: 0;
+         *  Set SPI regulator to 0 to configure init[1:0]=0.
+         */
+        uint32_t vdd_spi_en_init:1;
+        /** vdd_spi_encurlim : RO; bitpos: [8]; default: 0;
+         *  Set SPI regulator to 1 to enable output current limit.
+         */
+        uint32_t vdd_spi_encurlim:1;
+        /** vdd_spi_dcurlim : RO; bitpos: [11:9]; default: 0;
+         *  Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).
+         */
+        uint32_t vdd_spi_dcurlim:3;
+        /** vdd_spi_init : RO; bitpos: [13:12]; default: 0;
+         *  Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.
+         */
+        uint32_t vdd_spi_init:2;
+        /** vdd_spi_dcap : RO; bitpos: [15:14]; default: 0;
+         *  Prevents SPI regulator from overshoot.
+         */
+        uint32_t vdd_spi_dcap:2;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1:
+         *  80000. 2: 160000. 3:320000.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+         *  number of 1: disable.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  Set this bit to enable revoking first secure boot key.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  Set this bit to enable revoking second secure boot key.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  Set this bit to enable revoking third secure boot key.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  Purpose of Key0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  Purpose of Key1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register 3.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  Purpose of Key2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  Purpose of Key3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  Purpose of Key4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  Purpose of Key5.
+         */
+        uint32_t key_purpose_5:4;
+        /** rpt4_reserved0 : RO; bitpos: [19:16]; default: 0;
+         *  Reserved (used for four backups method).
+         */
+        uint32_t rpt4_reserved0:4;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  Set this bit to enable secure boot.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  Set this bit to enable revoking aggressive secure boot.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** dis_usb_jtag : RO; bitpos: [22]; default: 0;
+         *  Set this bit to disable function of usb switch to jtag in module of usb device.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** dis_usb_serial_jtag : RO; bitpos: [23]; default: 0;
+         *  Set this bit to disable usb device.
+         */
+        uint32_t dis_usb_serial_jtag:1;
+        /** strap_jtag_sel : RO; bitpos: [24]; default: 0;
+         *  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+         */
+        uint32_t strap_jtag_sel:1;
+        /** usb_phy_sel : RO; bitpos: [25]; default: 0;
+         *  This bit is used to switch internal PHY and external PHY for USB OTG and USB
+         *  Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to
+         *  USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to
+         *  USB Device.
+         */
+        uint32_t usb_phy_sel:1;
+        /** power_glitch_dsense : RO; bitpos: [27:26]; default: 0;
+         *  Sample delay configuration of power glitch.
+         */
+        uint32_t power_glitch_dsense:2;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  Configures flash waiting time after power-up, in unit of ms. If the value is less
+         *  than 15, the waiting time is the configurable value.  Otherwise, the waiting time
+         *  is twice the configurable value.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register 4.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [1]; default: 0;
+         *  Disable direct boot mode
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
+         *  Selects the default UART print channel. 0: UART0. 1: UART1.
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** flash_ecc_mode : RO; bitpos: [3]; default: 0;
+         *  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
+         *  use 16to17 byte mode.
+         */
+        uint32_t flash_ecc_mode:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [4]; default: 0;
+         *  Set this bit to disable UART download mode through USB.
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  Set this bit to enable secure UART download mode.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8
+         *  is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+         */
+        uint32_t uart_print_control:2;
+        /** pin_power_selection : RO; bitpos: [8]; default: 0;
+         *  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+         */
+        uint32_t pin_power_selection:1;
+        /** flash_type : RO; bitpos: [9]; default: 0;
+         *  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+         */
+        uint32_t flash_type:1;
+        /** flash_page_size : RO; bitpos: [11:10]; default: 0;
+         *  Set Flash page size.
+         */
+        uint32_t flash_page_size:2;
+        /** flash_ecc_en : RO; bitpos: [12]; default: 0;
+         *  Set 1 to enable ECC for flash boot.
+         */
+        uint32_t flash_ecc_en:1;
+        /** force_send_resume : RO; bitpos: [13]; default: 0;
+         *  Set this bit to force ROM code to send a resume command during SPI boot.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [29:14]; default: 0;
+         *  Secure version (used by ESP-IDF anti-rollback feature).
+         */
+        uint32_t secure_version:16;
+        /** powerglitch_en : RO; bitpos: [30]; default: 0;
+         *  Set this bit to enable power glitch function.
+         */
+        uint32_t powerglitch_en:1;
+        /** dis_usb_otg_download_mode : R; bitpos: [31]; default: 0;
+         *  Set this bit to disable download through USB-OTG
+         */
+        uint32_t dis_usb_otg_download_mode:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register 5.
+ */
+typedef union {
+    struct {
+        /** disable_wafer_version_major : R; bitpos: [0]; default: 0;
+         *  Disables check of wafer version major
+         */
+        uint32_t disable_wafer_version_major:1;
+        /** disable_blk_version_major : R; bitpos: [1]; default: 0;
+         *  Disables check of blk version major
+         */
+        uint32_t disable_blk_version_major:1;
+        /** reserved_0_162 : R; bitpos: [23:2]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_0_162:22;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_spi_sys_0 register
+ *  BLOCK1 data register 0.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_0_reg_t;
+
+/** Type of rd_mac_spi_sys_1 register
+ *  BLOCK1 data register 1.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0;
+         *  SPI_PAD_configure CLK
+         */
+        uint32_t spi_pad_config_clk:6;
+        /** spi_pad_config_q : R; bitpos: [27:22]; default: 0;
+         *  SPI_PAD_configure Q(D1)
+         */
+        uint32_t spi_pad_config_q:6;
+        /** spi_pad_config_d : R; bitpos: [31:28]; default: 0;
+         *  SPI_PAD_configure D(D0)
+         */
+        uint32_t spi_pad_config_d:4;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_1_reg_t;
+
+/** Type of rd_mac_spi_sys_2 register
+ *  BLOCK1 data register 2.
+ */
+typedef union {
+    struct {
+        /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0;
+         *  SPI_PAD_configure D(D0)
+         */
+        uint32_t spi_pad_config_d_1:2;
+        /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0;
+         *  SPI_PAD_configure CS
+         */
+        uint32_t spi_pad_config_cs:6;
+        /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0;
+         *  SPI_PAD_configure HD(D3)
+         */
+        uint32_t spi_pad_config_hd:6;
+        /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0;
+         *  SPI_PAD_configure WP(D2)
+         */
+        uint32_t spi_pad_config_wp:6;
+        /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0;
+         *  SPI_PAD_configure DQS
+         */
+        uint32_t spi_pad_config_dqs:6;
+        /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0;
+         *  SPI_PAD_configure D4
+         */
+        uint32_t spi_pad_config_d4:6;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_2_reg_t;
+
+/** Type of rd_mac_spi_sys_3 register
+ *  BLOCK1 data register 3.
+ */
+typedef union {
+    struct {
+        /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0;
+         *  SPI_PAD_configure D5
+         */
+        uint32_t spi_pad_config_d5:6;
+        /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0;
+         *  SPI_PAD_configure D6
+         */
+        uint32_t spi_pad_config_d6:6;
+        /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0;
+         *  SPI_PAD_configure D7
+         */
+        uint32_t spi_pad_config_d7:6;
+        /** wafer_version_minor_lo : R; bitpos: [20:18]; default: 0;
+         *  WAFER_VERSION_MINOR least significant bits
+         */
+        uint32_t wafer_version_minor_lo:3;
+        /** pkg_version : R; bitpos: [23:21]; default: 0;
+         *  Package version
+         */
+        uint32_t pkg_version:3;
+        /** blk_version_minor : R; bitpos: [26:24]; default: 0;
+         *  BLK_VERSION_MINOR
+         */
+        uint32_t blk_version_minor:3;
+        /** flash_cap : R; bitpos: [29:27]; default: 0;
+         *  Flash capacity
+         */
+        uint32_t flash_cap:3;
+        /** flash_temp : R; bitpos: [31:30]; default: 0;
+         *  Flash temperature
+         */
+        uint32_t flash_temp:2;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_3_reg_t;
+
+/** Type of rd_mac_spi_sys_4 register
+ *  BLOCK1 data register 4.
+ */
+typedef union {
+    struct {
+        /** flash_vendor : R; bitpos: [2:0]; default: 0;
+         *  Flash vendor
+         */
+        uint32_t flash_vendor:3;
+        /** psram_cap : R; bitpos: [4:3]; default: 0;
+         *  PSRAM capacity
+         */
+        uint32_t psram_cap:2;
+        /** psram_temp : R; bitpos: [6:5]; default: 0;
+         *  PSRAM temperature
+         */
+        uint32_t psram_temp:2;
+        /** psram_vendor : R; bitpos: [8:7]; default: 0;
+         *  PSRAM vendor
+         */
+        uint32_t psram_vendor:2;
+        /** reserved_1_137 : R; bitpos: [12:9]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_137:4;
+        /** k_rtc_ldo : R; bitpos: [19:13]; default: 0;
+         *  BLOCK1 K_RTC_LDO
+         */
+        uint32_t k_rtc_ldo:7;
+        /** k_dig_ldo : R; bitpos: [26:20]; default: 0;
+         *  BLOCK1 K_DIG_LDO
+         */
+        uint32_t k_dig_ldo:7;
+        /** v_rtc_dbias20 : R; bitpos: [31:27]; default: 0;
+         *  BLOCK1 voltage of rtc dbias20
+         */
+        uint32_t v_rtc_dbias20:5;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_4_reg_t;
+
+/** Type of rd_mac_spi_sys_5 register
+ *  BLOCK1 data register 5.
+ */
+typedef union {
+    struct {
+        /** v_rtc_dbias20_1 : R; bitpos: [2:0]; default: 0;
+         *  BLOCK1 voltage of rtc dbias20
+         */
+        uint32_t v_rtc_dbias20_1:3;
+        /** v_dig_dbias20 : R; bitpos: [10:3]; default: 0;
+         *  BLOCK1 voltage of digital dbias20
+         */
+        uint32_t v_dig_dbias20:8;
+        /** dig_dbias_hvt : R; bitpos: [15:11]; default: 0;
+         *  BLOCK1 digital dbias when hvt
+         */
+        uint32_t dig_dbias_hvt:5;
+        /** reserved_1_176 : R; bitpos: [18:16]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_176:3;
+        /** psram_cap_3 : R; bitpos: [19]; default: 0;
+         *  PSRAM capacity bit 3
+         */
+        uint32_t psram_cap_3:1;
+        /** reserved_1_180 : R; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_1_180:3;
+        /** wafer_version_minor_hi : R; bitpos: [23]; default: 0;
+         *  WAFER_VERSION_MINOR most significant bit
+         */
+        uint32_t wafer_version_minor_hi:1;
+        /** wafer_version_major : R; bitpos: [25:24]; default: 0;
+         *  WAFER_VERSION_MAJOR
+         */
+        uint32_t wafer_version_major:2;
+        /** adc2_cal_vol_atten3 : R; bitpos: [31:26]; default: 0;
+         *  ADC2 calibration voltage at atten3
+         */
+        uint32_t adc2_cal_vol_atten3:6;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register 0 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register 1 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register 2 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register 3 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
+         *  Optional unique 128-bit ID
+         */
+        uint32_t optional_unique_id_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register 4 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** blk_version_major : R; bitpos: [1:0]; default: 0;
+         *  BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
+         */
+        uint32_t blk_version_major:2;
+        /** reserved_2_130 : R; bitpos: [3:2]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_130:2;
+        /** temp_calib : R; bitpos: [12:4]; default: 0;
+         *  Temperature calibration data
+         */
+        uint32_t temp_calib:9;
+        /** ocode : R; bitpos: [20:13]; default: 0;
+         *  ADC OCode
+         */
+        uint32_t ocode:8;
+        /** adc1_init_code_atten0 : R; bitpos: [28:21]; default: 0;
+         *  ADC1 init code at atten0
+         */
+        uint32_t adc1_init_code_atten0:8;
+        /** adc1_init_code_atten1 : R; bitpos: [31:29]; default: 0;
+         *  ADC1 init code at atten1
+         */
+        uint32_t adc1_init_code_atten1:3;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register 5 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_init_code_atten1_1 : R; bitpos: [2:0]; default: 0;
+         *  ADC1 init code at atten1
+         */
+        uint32_t adc1_init_code_atten1_1:3;
+        /** adc1_init_code_atten2 : R; bitpos: [8:3]; default: 0;
+         *  ADC1 init code at atten2
+         */
+        uint32_t adc1_init_code_atten2:6;
+        /** adc1_init_code_atten3 : R; bitpos: [14:9]; default: 0;
+         *  ADC1 init code at atten3
+         */
+        uint32_t adc1_init_code_atten3:6;
+        /** adc2_init_code_atten0 : R; bitpos: [22:15]; default: 0;
+         *  ADC2 init code at atten0
+         */
+        uint32_t adc2_init_code_atten0:8;
+        /** adc2_init_code_atten1 : R; bitpos: [28:23]; default: 0;
+         *  ADC2 init code at atten1
+         */
+        uint32_t adc2_init_code_atten1:6;
+        /** adc2_init_code_atten2 : R; bitpos: [31:29]; default: 0;
+         *  ADC2 init code at atten2
+         */
+        uint32_t adc2_init_code_atten2:3;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register 6 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc2_init_code_atten2_1 : R; bitpos: [2:0]; default: 0;
+         *  ADC2 init code at atten2
+         */
+        uint32_t adc2_init_code_atten2_1:3;
+        /** adc2_init_code_atten3 : R; bitpos: [8:3]; default: 0;
+         *  ADC2 init code at atten3
+         */
+        uint32_t adc2_init_code_atten3:6;
+        /** adc1_cal_vol_atten0 : R; bitpos: [16:9]; default: 0;
+         *  ADC1 calibration voltage at atten0
+         */
+        uint32_t adc1_cal_vol_atten0:8;
+        /** adc1_cal_vol_atten1 : R; bitpos: [24:17]; default: 0;
+         *  ADC1 calibration voltage at atten1
+         */
+        uint32_t adc1_cal_vol_atten1:8;
+        /** adc1_cal_vol_atten2 : R; bitpos: [31:25]; default: 0;
+         *  ADC1 calibration voltage at atten2
+         */
+        uint32_t adc1_cal_vol_atten2:7;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register 7 of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** adc1_cal_vol_atten2_1 : R; bitpos: [0]; default: 0;
+         *  ADC1 calibration voltage at atten2
+         */
+        uint32_t adc1_cal_vol_atten2_1:1;
+        /** adc1_cal_vol_atten3 : R; bitpos: [8:1]; default: 0;
+         *  ADC1 calibration voltage at atten3
+         */
+        uint32_t adc1_cal_vol_atten3:8;
+        /** adc2_cal_vol_atten0 : R; bitpos: [16:9]; default: 0;
+         *  ADC2 calibration voltage at atten0
+         */
+        uint32_t adc2_cal_vol_atten0:8;
+        /** adc2_cal_vol_atten1 : R; bitpos: [23:17]; default: 0;
+         *  ADC2 calibration voltage at atten1
+         */
+        uint32_t adc2_cal_vol_atten1:7;
+        /** adc2_cal_vol_atten2 : R; bitpos: [30:24]; default: 0;
+         *  ADC2 calibration voltage at atten2
+         */
+        uint32_t adc2_cal_vol_atten2:7;
+        /** reserved_2_255 : R; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_2_255:1;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register 0 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register 1 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register 2 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register 3 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register 4 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register 5 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register 6 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** reserved_3_192 : R; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_192:8;
+        /** custom_mac : R; bitpos: [31:8]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac:24;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register 7 of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** custom_mac_1 : R; bitpos: [23:0]; default: 0;
+         *  Custom MAC
+         */
+        uint32_t custom_mac_1:24;
+        /** reserved_3_248 : R; bitpos: [31:24]; default: 0;
+         *  reserved
+         */
+        uint32_t reserved_3_248:8;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register 0 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register 1 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register 2 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register 3 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register 4 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register 5 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register 6 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register 7 of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register 0 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register 1 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register 2 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register 3 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register 4 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register 5 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register 6 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register 7 of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register 0 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register 1 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register 2 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register 3 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register 4 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register 5 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register 6 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register 7 of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register 0 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register 1 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register 2 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register 3 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register 4 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register 5 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register 6 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register 7 of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register 0 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register 1 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register 2 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register 3 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register 4 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register 5 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register 6 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register 7 of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register 0 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register 1 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register 2 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register 3 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register 4 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register 5 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register 6 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register 7 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register 0 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 0th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register 1 of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 1st 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register 2 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 2nd 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register 3 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 3rd 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register 4 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 4th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register 5 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 5th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register 6 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 6th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register 7 of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the 7th 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+
+/** Group: Report Register */
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t rd_dis_err:7;
+        /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_rtc_ram_boot_err:1;
+        /** dis_icache_err : RO; bitpos: [8]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_icache_err:1;
+        /** dis_dcache_err : RO; bitpos: [9]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_dcache_err:1;
+        /** dis_download_icache_err : RO; bitpos: [10]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_icache_err:1;
+        /** dis_download_dcache_err : RO; bitpos: [11]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_dcache_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_force_download_err:1;
+        /** dis_usb_err : RO; bitpos: [13]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_err:1;
+        /** dis_can_err : RO; bitpos: [14]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_can_err:1;
+        /** dis_app_cpu_err : RO; bitpos: [15]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_app_cpu_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t usb_drefh_err:2;
+        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t usb_drefl_err:2;
+        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t usb_exchg_pins_err:1;
+        /** ext_phy_enable_err : RO; bitpos: [26]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t ext_phy_enable_err:1;
+        /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t btlc_gpio_enable_err:2;
+        /** vdd_spi_modecurlim_err : RO; bitpos: [29]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_modecurlim_err:1;
+        /** vdd_spi_drefh_err : RO; bitpos: [31:30]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_drefh_err:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** vdd_spi_drefm_err : RO; bitpos: [1:0]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_drefm_err:2;
+        /** vdd_spi_drefl_err : RO; bitpos: [3:2]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_drefl_err:2;
+        /** vdd_spi_xpd_err : RO; bitpos: [4]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_xpd_err:1;
+        /** vdd_spi_tieh_err : RO; bitpos: [5]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_tieh_err:1;
+        /** vdd_spi_force_err : RO; bitpos: [6]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_force_err:1;
+        /** vdd_spi_en_init_err : RO; bitpos: [7]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_en_init_err:1;
+        /** vdd_spi_encurlim_err : RO; bitpos: [8]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_encurlim_err:1;
+        /** vdd_spi_dcurlim_err : RO; bitpos: [11:9]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_dcurlim_err:3;
+        /** vdd_spi_init_err : RO; bitpos: [13:12]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_init_err:2;
+        /** vdd_spi_dcap_err : RO; bitpos: [15:14]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_dcap_err:2;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** rpt4_reserved0_err : RO; bitpos: [19:16]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t rpt4_reserved0_err:4;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [22]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** dis_usb_device_err : RO; bitpos: [23]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_device_err:1;
+        /** strap_jtag_sel_err : RO; bitpos: [24]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t strap_jtag_sel_err:1;
+        /** usb_phy_sel_err : RO; bitpos: [25]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t usb_phy_sel_err:1;
+        /** power_glitch_dsense_err : RO; bitpos: [27:26]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t power_glitch_dsense_err:2;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_legacy_spi_boot_err:1;
+        /** uart_print_channel_err : RO; bitpos: [2]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t uart_print_channel_err:1;
+        /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t flash_ecc_mode_err:1;
+        /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t uart_print_control_err:2;
+        /** pin_power_selection_err : RO; bitpos: [8]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t pin_power_selection_err:1;
+        /** flash_type_err : RO; bitpos: [9]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t flash_type_err:1;
+        /** flash_page_size_err : RO; bitpos: [11:10]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t flash_page_size_err:2;
+        /** flash_ecc_en_err : RO; bitpos: [12]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [29:14]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t secure_version_err:16;
+        /** powerglitch_en_err : RO; bitpos: [30]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t powerglitch_en_err:1;
+        /** rpt4_reserved1_err : RO; bitpos: [31]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved1_err:1;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved2_err : RO; bitpos: [23:0]; default: 0;
+         *  If any bits in this filed are 1, then it indicates a programming error.
+         */
+        uint32_t rpt4_reserved2_err:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_spi_8m_err_num:3;
+        /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_spi_8m_fail:1;
+        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_num:3;
+        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** key0_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key0 is reliable 1: Means that programming
+         *  key0 failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key1_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key1 is reliable 1: Means that programming
+         *  key1 failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key2_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key2 is reliable 1: Means that programming
+         *  key2 failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key3_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key3 is reliable 1: Means that programming
+         *  key3 failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key4_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key4 is reliable 1: Means that programming
+         *  key4 failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key5_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part2_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t efuse_mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t efuse_mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit and force to enable clock signal of eFuse memory.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+         */
+        uint32_t op_code:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/WS/SC; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/WS/SC; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
+         *  Configures the initial read time of eFuse.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0;
+         *  Indicates the number of error bits during programming BLOCK0.
+         */
+        uint32_t repeat_err_cnt:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/WC/SS; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/WC/SS; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WO; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 34607760;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0;
+    volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1;
+    volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2;
+    volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3;
+    volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4;
+    volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    uint32_t reserved_18c;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_194[11];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    uint32_t reserved_1f0;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_date_reg_t date;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/extmem_reg.h b/components/soc/esp32s3/register/soc/extmem_reg.h
new file mode 100644
index 00000000000..4929c47f86c
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/extmem_reg.h
@@ -0,0 +1,1668 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_EXTMEM_REG_H_
+#define _SOC_EXTMEM_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define EXTMEM_DCACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x0)
+/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 byt
+es.*/
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE    0x00000003
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M  ((EXTMEM_DCACHE_BLOCKSIZE_MODE_V)<<(EXTMEM_DCACHE_BLOCKSIZE_MODE_S))
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V  0x3
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_S  3
+/* EXTMEM_DCACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to configure cache memory size.0: 32KB, 1: 64KB.*/
+#define EXTMEM_DCACHE_SIZE_MODE    (BIT(2))
+#define EXTMEM_DCACHE_SIZE_MODE_M  (BIT(2))
+#define EXTMEM_DCACHE_SIZE_MODE_V  0x1
+#define EXTMEM_DCACHE_SIZE_MODE_S  2
+/* EXTMEM_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/
+#define EXTMEM_DCACHE_ENABLE    (BIT(0))
+#define EXTMEM_DCACHE_ENABLE_M  (BIT(0))
+#define EXTMEM_DCACHE_ENABLE_V  0x1
+#define EXTMEM_DCACHE_ENABLE_S  0
+
+#define EXTMEM_DCACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x4)
+/* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable core1 dbus, 0: enable, 1: disable.*/
+#define EXTMEM_DCACHE_SHUT_CORE1_BUS    (BIT(1))
+#define EXTMEM_DCACHE_SHUT_CORE1_BUS_M  (BIT(1))
+#define EXTMEM_DCACHE_SHUT_CORE1_BUS_V  0x1
+#define EXTMEM_DCACHE_SHUT_CORE1_BUS_S  1
+/* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable core0 dbus, 0: enable, 1: disable.*/
+#define EXTMEM_DCACHE_SHUT_CORE0_BUS    (BIT(0))
+#define EXTMEM_DCACHE_SHUT_CORE0_BUS_M  (BIT(0))
+#define EXTMEM_DCACHE_SHUT_CORE0_BUS_V  0x1
+#define EXTMEM_DCACHE_SHUT_CORE0_BUS_S  0
+
+#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x8)
+/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power dcache tag memory up, 0: follow  rtc_lslp_pd, 1: power
+up.*/
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU    (BIT(2))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V  0x1
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S  2
+/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power dcache tag memory down, 0: follow  rtc_lslp_pd, 1: powe
+r down.*/
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD    (BIT(1))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V  0x1
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S  1
+/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of dcache tag memory. 1: close gating, 0:
+open clock gating..*/
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON    (BIT(0))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V  0x1
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S  0
+
+#define EXTMEM_DCACHE_PRELOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xC)
+/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section of prelock function..*/
+#define EXTMEM_DCACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M  (BIT(1))
+#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V  0x1
+#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S  1
+/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section of prelock function..*/
+#define EXTMEM_DCACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M  (BIT(0))
+#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V  0x1
+#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S  0
+
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x10)
+/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to configure the first start virtual address of data prelock,
+which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG.*/
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S))
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S  0
+
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x14)
+/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to configure the second start virtual address of data prelock,
+ which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG.*/
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S))
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S  0
+
+#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x18)
+/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: The bits are used to configure the first length of data locking, which is
+combined with DCACHE_PRELOCK_SCT0_ADDR_REG.*/
+#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE    0x0000FFFF
+#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S))
+#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V  0xFFFF
+#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S  16
+/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the second length of data locking, which is
+combined with DCACHE_PRELOCK_SCT1_ADDR_REG.*/
+#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE    0x0000FFFF
+#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S))
+#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V  0xFFFF
+#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S  0
+
+#define EXTMEM_DCACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x1C)
+/* EXTMEM_DCACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to indicate unlock/lock operation is finished..*/
+#define EXTMEM_DCACHE_LOCK_DONE    (BIT(2))
+#define EXTMEM_DCACHE_LOCK_DONE_M  (BIT(2))
+#define EXTMEM_DCACHE_LOCK_DONE_V  0x1
+#define EXTMEM_DCACHE_LOCK_DONE_S  2
+/* EXTMEM_DCACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
+ unlock operation done..*/
+#define EXTMEM_DCACHE_UNLOCK_ENA    (BIT(1))
+#define EXTMEM_DCACHE_UNLOCK_ENA_M  (BIT(1))
+#define EXTMEM_DCACHE_UNLOCK_ENA_V  0x1
+#define EXTMEM_DCACHE_UNLOCK_ENA_S  1
+/* EXTMEM_DCACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
+ock operation done..*/
+#define EXTMEM_DCACHE_LOCK_ENA    (BIT(0))
+#define EXTMEM_DCACHE_LOCK_ENA_M  (BIT(0))
+#define EXTMEM_DCACHE_LOCK_ENA_V  0x1
+#define EXTMEM_DCACHE_LOCK_ENA_S  0
+
+#define EXTMEM_DCACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x20)
+/* EXTMEM_DCACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for lock operations. It
+ should be combined with DCACHE_LOCK_SIZE_REG..*/
+#define EXTMEM_DCACHE_LOCK_ADDR    0xFFFFFFFF
+#define EXTMEM_DCACHE_LOCK_ADDR_M  ((EXTMEM_DCACHE_LOCK_ADDR_V)<<(EXTMEM_DCACHE_LOCK_ADDR_S))
+#define EXTMEM_DCACHE_LOCK_ADDR_V  0xFFFFFFFF
+#define EXTMEM_DCACHE_LOCK_ADDR_S  0
+
+#define EXTMEM_DCACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x24)
+/* EXTMEM_DCACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for lock operations. The bits are the
+counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG..*/
+#define EXTMEM_DCACHE_LOCK_SIZE    0x0000FFFF
+#define EXTMEM_DCACHE_LOCK_SIZE_M  ((EXTMEM_DCACHE_LOCK_SIZE_V)<<(EXTMEM_DCACHE_LOCK_SIZE_S))
+#define EXTMEM_DCACHE_LOCK_SIZE_V  0xFFFF
+#define EXTMEM_DCACHE_LOCK_SIZE_S  0
+
+#define EXTMEM_DCACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x28)
+/* EXTMEM_DCACHE_SYNC_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate clean/writeback/invalidate operation is finished..*/
+#define EXTMEM_DCACHE_SYNC_DONE    (BIT(3))
+#define EXTMEM_DCACHE_SYNC_DONE_M  (BIT(3))
+#define EXTMEM_DCACHE_SYNC_DONE_V  0x1
+#define EXTMEM_DCACHE_SYNC_DONE_S  3
+/* EXTMEM_DCACHE_CLEAN_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable clean operation. It will be cleared by hardware after
+clean operation done..*/
+#define EXTMEM_DCACHE_CLEAN_ENA    (BIT(2))
+#define EXTMEM_DCACHE_CLEAN_ENA_M  (BIT(2))
+#define EXTMEM_DCACHE_CLEAN_ENA_V  0x1
+#define EXTMEM_DCACHE_CLEAN_ENA_S  2
+/* EXTMEM_DCACHE_WRITEBACK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable writeback operation. It will be cleared by hardware af
+ter writeback operation done..*/
+#define EXTMEM_DCACHE_WRITEBACK_ENA    (BIT(1))
+#define EXTMEM_DCACHE_WRITEBACK_ENA_M  (BIT(1))
+#define EXTMEM_DCACHE_WRITEBACK_ENA_V  0x1
+#define EXTMEM_DCACHE_WRITEBACK_ENA_S  1
+/* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
+after invalidate operation done..*/
+#define EXTMEM_DCACHE_INVALIDATE_ENA    (BIT(0))
+#define EXTMEM_DCACHE_INVALIDATE_ENA_M  (BIT(0))
+#define EXTMEM_DCACHE_INVALIDATE_ENA_V  0x1
+#define EXTMEM_DCACHE_INVALIDATE_ENA_S  0
+
+#define EXTMEM_DCACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x2C)
+/* EXTMEM_DCACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for clean operations. I
+t should be combined with DCACHE_SYNC_SIZE_REG..*/
+#define EXTMEM_DCACHE_SYNC_ADDR    0xFFFFFFFF
+#define EXTMEM_DCACHE_SYNC_ADDR_M  ((EXTMEM_DCACHE_SYNC_ADDR_V)<<(EXTMEM_DCACHE_SYNC_ADDR_S))
+#define EXTMEM_DCACHE_SYNC_ADDR_V  0xFFFFFFFF
+#define EXTMEM_DCACHE_SYNC_ADDR_S  0
+
+#define EXTMEM_DCACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x30)
+/* EXTMEM_DCACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
+/*description: The bits are used to configure the length for sync operations. The bits are the
+counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG..*/
+#define EXTMEM_DCACHE_SYNC_SIZE    0x007FFFFF
+#define EXTMEM_DCACHE_SYNC_SIZE_M  ((EXTMEM_DCACHE_SYNC_SIZE_V)<<(EXTMEM_DCACHE_SYNC_SIZE_S))
+#define EXTMEM_DCACHE_SYNC_SIZE_V  0x7FFFFF
+#define EXTMEM_DCACHE_SYNC_SIZE_S  0
+
+#define EXTMEM_DCACHE_OCCUPY_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x34)
+/* EXTMEM_DCACHE_OCCUPY_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to indicate occupy operation is finished..*/
+#define EXTMEM_DCACHE_OCCUPY_DONE    (BIT(1))
+#define EXTMEM_DCACHE_OCCUPY_DONE_M  (BIT(1))
+#define EXTMEM_DCACHE_OCCUPY_DONE_V  0x1
+#define EXTMEM_DCACHE_OCCUPY_DONE_S  1
+/* EXTMEM_DCACHE_OCCUPY_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable occupy operation. It will be cleared by hardware after
+ issuing Auot-Invalidate Operation..*/
+#define EXTMEM_DCACHE_OCCUPY_ENA    (BIT(0))
+#define EXTMEM_DCACHE_OCCUPY_ENA_M  (BIT(0))
+#define EXTMEM_DCACHE_OCCUPY_ENA_V  0x1
+#define EXTMEM_DCACHE_OCCUPY_ENA_S  0
+
+#define EXTMEM_DCACHE_OCCUPY_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x38)
+/* EXTMEM_DCACHE_OCCUPY_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for occupy operation. I
+t should be combined with DCACHE_OCCUPY_SIZE_REG..*/
+#define EXTMEM_DCACHE_OCCUPY_ADDR    0xFFFFFFFF
+#define EXTMEM_DCACHE_OCCUPY_ADDR_M  ((EXTMEM_DCACHE_OCCUPY_ADDR_V)<<(EXTMEM_DCACHE_OCCUPY_ADDR_S))
+#define EXTMEM_DCACHE_OCCUPY_ADDR_V  0xFFFFFFFF
+#define EXTMEM_DCACHE_OCCUPY_ADDR_S  0
+
+#define EXTMEM_DCACHE_OCCUPY_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x3C)
+/* EXTMEM_DCACHE_OCCUPY_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for occupy operation. The bits are the
+ counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG..*/
+#define EXTMEM_DCACHE_OCCUPY_SIZE    0x0000FFFF
+#define EXTMEM_DCACHE_OCCUPY_SIZE_M  ((EXTMEM_DCACHE_OCCUPY_SIZE_V)<<(EXTMEM_DCACHE_OCCUPY_SIZE_S))
+#define EXTMEM_DCACHE_OCCUPY_SIZE_V  0xFFFF
+#define EXTMEM_DCACHE_OCCUPY_SIZE_S  0
+
+#define EXTMEM_DCACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x40)
+/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to configure the direction of preload operation. 1: descending,
+0: ascending..*/
+#define EXTMEM_DCACHE_PRELOAD_ORDER    (BIT(2))
+#define EXTMEM_DCACHE_PRELOAD_ORDER_M  (BIT(2))
+#define EXTMEM_DCACHE_PRELOAD_ORDER_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_ORDER_S  2
+/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to indicate preload operation is finished..*/
+#define EXTMEM_DCACHE_PRELOAD_DONE    (BIT(1))
+#define EXTMEM_DCACHE_PRELOAD_DONE_M  (BIT(1))
+#define EXTMEM_DCACHE_PRELOAD_DONE_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_DONE_S  1
+/* EXTMEM_DCACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable preload operation. It will be cleared by hardware afte
+r preload operation done..*/
+#define EXTMEM_DCACHE_PRELOAD_ENA    (BIT(0))
+#define EXTMEM_DCACHE_PRELOAD_ENA_M  (BIT(0))
+#define EXTMEM_DCACHE_PRELOAD_ENA_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_ENA_S  0
+
+#define EXTMEM_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x44)
+/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for preload operation.
+It should be combined with DCACHE_PRELOAD_SIZE_REG..*/
+#define EXTMEM_DCACHE_PRELOAD_ADDR    0xFFFFFFFF
+#define EXTMEM_DCACHE_PRELOAD_ADDR_M  ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S))
+#define EXTMEM_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define EXTMEM_DCACHE_PRELOAD_ADDR_S  0
+
+#define EXTMEM_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x48)
+/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for preload operation. The bits are th
+e counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG...*/
+#define EXTMEM_DCACHE_PRELOAD_SIZE    0x0000FFFF
+#define EXTMEM_DCACHE_PRELOAD_SIZE_M  ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S))
+#define EXTMEM_DCACHE_PRELOAD_SIZE_V  0xFFFF
+#define EXTMEM_DCACHE_PRELOAD_SIZE_S  0
+
+#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x4C)
+/* EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit is used to clear autoload buffer in dcache..*/
+#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR    (BIT(9))
+#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_M  (BIT(9))
+#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V  0x1
+#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S  9
+/* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */
+/*description: The bits are used to configure the numbers of the cache block for the issuing au
+toload operation..*/
+#define EXTMEM_DCACHE_AUTOLOAD_SIZE    0x00000003
+#define EXTMEM_DCACHE_AUTOLOAD_SIZE_M  ((EXTMEM_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SIZE_S))
+#define EXTMEM_DCACHE_AUTOLOAD_SIZE_V  0x3
+#define EXTMEM_DCACHE_AUTOLOAD_SIZE_S  7
+/* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
+/*description: The bits are used to configure trigger conditions for autoload. 0/3: cache miss,
+ 1: cache hit, 2: both cache miss and hit..*/
+#define EXTMEM_DCACHE_AUTOLOAD_RQST    0x00000003
+#define EXTMEM_DCACHE_AUTOLOAD_RQST_M  ((EXTMEM_DCACHE_AUTOLOAD_RQST_V)<<(EXTMEM_DCACHE_AUTOLOAD_RQST_S))
+#define EXTMEM_DCACHE_AUTOLOAD_RQST_V  0x3
+#define EXTMEM_DCACHE_AUTOLOAD_RQST_S  5
+/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bits are used to configure the direction of autoload. 1: descending, 0: asce
+nding..*/
+#define EXTMEM_DCACHE_AUTOLOAD_ORDER    (BIT(4))
+#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M  (BIT(4))
+#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V  0x1
+#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S  4
+/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
+/*description: The bit is used to indicate autoload operation is finished..*/
+#define EXTMEM_DCACHE_AUTOLOAD_DONE    (BIT(3))
+#define EXTMEM_DCACHE_AUTOLOAD_DONE_M  (BIT(3))
+#define EXTMEM_DCACHE_AUTOLOAD_DONE_V  0x1
+#define EXTMEM_DCACHE_AUTOLOAD_DONE_S  3
+/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable and disable autoload operation. It is combined with dc
+ache_autoload_done. 1: enable, 0: disable. .*/
+#define EXTMEM_DCACHE_AUTOLOAD_ENA    (BIT(2))
+#define EXTMEM_DCACHE_AUTOLOAD_ENA_M  (BIT(2))
+#define EXTMEM_DCACHE_AUTOLOAD_ENA_V  0x1
+#define EXTMEM_DCACHE_AUTOLOAD_ENA_S  2
+/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bits are used to enable the second section for autoload operation..*/
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA    (BIT(1))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M  (BIT(1))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V  0x1
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S  1
+/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bits are used to enable the first section for autoload operation..*/
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA    (BIT(0))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M  (BIT(0))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V  0x1
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S  0
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x50)
+/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of the first section
+for autoload operation. It should be combined with dcache_autoload_sct0_ena..*/
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x54)
+/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: The bits are used to configure the length of the first section for autoload oper
+ation. It should be combined with dcache_autoload_sct0_ena..*/
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE    0x07FFFFFF
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V  0x7FFFFFF
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x58)
+/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of the second section f
+or autoload operation. It should be combined with dcache_autoload_sct1_ena..*/
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x5C)
+/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: The bits are used to configure the length of the second section for autoload ope
+ration. It should be combined with dcache_autoload_sct1_ena..*/
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE    0x07FFFFFF
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V  0x7FFFFFF
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define EXTMEM_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x60)
+/* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes.*/
+#define EXTMEM_ICACHE_BLOCKSIZE_MODE    (BIT(3))
+#define EXTMEM_ICACHE_BLOCKSIZE_MODE_M  (BIT(3))
+#define EXTMEM_ICACHE_BLOCKSIZE_MODE_V  0x1
+#define EXTMEM_ICACHE_BLOCKSIZE_MODE_S  3
+/* EXTMEM_ICACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to configure cache memory size.0: 16KB, 1: 32KB.*/
+#define EXTMEM_ICACHE_SIZE_MODE    (BIT(2))
+#define EXTMEM_ICACHE_SIZE_MODE_M  (BIT(2))
+#define EXTMEM_ICACHE_SIZE_MODE_V  0x1
+#define EXTMEM_ICACHE_SIZE_MODE_S  2
+/* EXTMEM_ICACHE_WAY_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to configure cache way mode.0: 4-way, 1: 8-way.*/
+#define EXTMEM_ICACHE_WAY_MODE    (BIT(1))
+#define EXTMEM_ICACHE_WAY_MODE_M  (BIT(1))
+#define EXTMEM_ICACHE_WAY_MODE_V  0x1
+#define EXTMEM_ICACHE_WAY_MODE_S  1
+/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to activate the data cache. 0: disable, 1: enable.*/
+#define EXTMEM_ICACHE_ENABLE    (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_M  (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_V  0x1
+#define EXTMEM_ICACHE_ENABLE_S  0
+
+#define EXTMEM_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x64)
+/* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable core1 ibus, 0: enable, 1: disable.*/
+#define EXTMEM_ICACHE_SHUT_CORE1_BUS    (BIT(1))
+#define EXTMEM_ICACHE_SHUT_CORE1_BUS_M  (BIT(1))
+#define EXTMEM_ICACHE_SHUT_CORE1_BUS_V  0x1
+#define EXTMEM_ICACHE_SHUT_CORE1_BUS_S  1
+/* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable core0 ibus, 0: enable, 1: disable.*/
+#define EXTMEM_ICACHE_SHUT_CORE0_BUS    (BIT(0))
+#define EXTMEM_ICACHE_SHUT_CORE0_BUS_M  (BIT(0))
+#define EXTMEM_ICACHE_SHUT_CORE0_BUS_V  0x1
+#define EXTMEM_ICACHE_SHUT_CORE0_BUS_S  0
+
+#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x68)
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up.*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU    (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S  2
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power d
+own.*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD    (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S  1
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of  icache tag memory. 1: close gating, 0:
+ open clock gating..*/
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON    (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V  0x1
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x6C)
+/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The bit is used to enable the second section of prelock function..*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V  0x1
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S  1
+/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The bit is used to enable the first section of prelock function..*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V  0x1
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x70)
+/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to configure the first start virtual address of data prelock,
+which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG.*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x74)
+/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to configure the second start virtual address of data prelock,
+ which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG.*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x78)
+/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: The bits are used to configure the first length of data locking, which is
+combined with ICACHE_PRELOCK_SCT0_ADDR_REG.*/
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE    0x0000FFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S  16
+/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the second length of data locking, which is
+combined with ICACHE_PRELOCK_SCT1_ADDR_REG.*/
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE    0x0000FFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M  ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S  0
+
+#define EXTMEM_ICACHE_LOCK_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x7C)
+/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to indicate unlock/lock operation is finished..*/
+#define EXTMEM_ICACHE_LOCK_DONE    (BIT(2))
+#define EXTMEM_ICACHE_LOCK_DONE_M  (BIT(2))
+#define EXTMEM_ICACHE_LOCK_DONE_V  0x1
+#define EXTMEM_ICACHE_LOCK_DONE_S  2
+/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable unlock operation. It will be cleared by hardware after
+ unlock operation done..*/
+#define EXTMEM_ICACHE_UNLOCK_ENA    (BIT(1))
+#define EXTMEM_ICACHE_UNLOCK_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_UNLOCK_ENA_V  0x1
+#define EXTMEM_ICACHE_UNLOCK_ENA_S  1
+/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable lock operation. It will be cleared by hardware after l
+ock operation done..*/
+#define EXTMEM_ICACHE_LOCK_ENA    (BIT(0))
+#define EXTMEM_ICACHE_LOCK_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_LOCK_ENA_V  0x1
+#define EXTMEM_ICACHE_LOCK_ENA_S  0
+
+#define EXTMEM_ICACHE_LOCK_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x80)
+/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for lock operations. It
+ should be combined with ICACHE_LOCK_SIZE_REG..*/
+#define EXTMEM_ICACHE_LOCK_ADDR    0xFFFFFFFF
+#define EXTMEM_ICACHE_LOCK_ADDR_M  ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S))
+#define EXTMEM_ICACHE_LOCK_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_LOCK_ADDR_S  0
+
+#define EXTMEM_ICACHE_LOCK_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x84)
+/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for lock operations. The bits are the
+counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG..*/
+#define EXTMEM_ICACHE_LOCK_SIZE    0x0000FFFF
+#define EXTMEM_ICACHE_LOCK_SIZE_M  ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S))
+#define EXTMEM_ICACHE_LOCK_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_LOCK_SIZE_S  0
+
+#define EXTMEM_ICACHE_SYNC_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x88)
+/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate invalidate operation is finished..*/
+#define EXTMEM_ICACHE_SYNC_DONE    (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_M  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_V  0x1
+#define EXTMEM_ICACHE_SYNC_DONE_S  1
+/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable invalidate operation. It will be cleared by hardware a
+after invalidate operation done..*/
+#define EXTMEM_ICACHE_INVALIDATE_ENA    (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_V  0x1
+#define EXTMEM_ICACHE_INVALIDATE_ENA_S  0
+
+#define EXTMEM_ICACHE_SYNC_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x8C)
+/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for clean operations. I
+t should be combined with ICACHE_SYNC_SIZE_REG..*/
+#define EXTMEM_ICACHE_SYNC_ADDR    0xFFFFFFFF
+#define EXTMEM_ICACHE_SYNC_ADDR_M  ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
+#define EXTMEM_ICACHE_SYNC_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_SYNC_ADDR_S  0
+
+#define EXTMEM_ICACHE_SYNC_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x90)
+/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
+/*description: The bits are used to configure the length for sync operations. The bits are the
+counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG..*/
+#define EXTMEM_ICACHE_SYNC_SIZE    0x007FFFFF
+#define EXTMEM_ICACHE_SYNC_SIZE_M  ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
+#define EXTMEM_ICACHE_SYNC_SIZE_V  0x7FFFFF
+#define EXTMEM_ICACHE_SYNC_SIZE_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x94)
+/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to configure the direction of preload operation. 1: descending,
+0: ascending..*/
+#define EXTMEM_ICACHE_PRELOAD_ORDER    (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_ORDER_M  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_ORDER_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_ORDER_S  2
+/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to indicate preload operation is finished..*/
+#define EXTMEM_ICACHE_PRELOAD_DONE    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_DONE_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_DONE_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_DONE_S  1
+/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable preload operation. It will be cleared by hardware afte
+r preload operation done..*/
+#define EXTMEM_ICACHE_PRELOAD_ENA    (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_ENA_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x98)
+/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address for preload operation.
+It should be combined with ICACHE_PRELOAD_SIZE_REG..*/
+#define EXTMEM_ICACHE_PRELOAD_ADDR    0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOAD_ADDR_M  ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S))
+#define EXTMEM_ICACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_PRELOAD_ADDR_S  0
+
+#define EXTMEM_ICACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x9C)
+/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: The bits are used to configure the length for preload operation. The bits are th
+e counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG...*/
+#define EXTMEM_ICACHE_PRELOAD_SIZE    0x0000FFFF
+#define EXTMEM_ICACHE_PRELOAD_SIZE_M  ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S))
+#define EXTMEM_ICACHE_PRELOAD_SIZE_V  0xFFFF
+#define EXTMEM_ICACHE_PRELOAD_SIZE_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG          (DR_REG_EXTMEM_BASE + 0xA0)
+/* EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit is used to clear autoload buffer in icache..*/
+#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR    (BIT(9))
+#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_M  (BIT(9))
+#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S  9
+/* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */
+/*description: The bits are used to configure the numbers of the cache block for the issuing au
+toload operation..*/
+#define EXTMEM_ICACHE_AUTOLOAD_SIZE    0x00000003
+#define EXTMEM_ICACHE_AUTOLOAD_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SIZE_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SIZE_V  0x3
+#define EXTMEM_ICACHE_AUTOLOAD_SIZE_S  7
+/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
+/*description: The bits are used to configure trigger conditions for autoload. 0/3: cache miss,
+ 1: cache hit, 2: both cache miss and hit..*/
+#define EXTMEM_ICACHE_AUTOLOAD_RQST    0x00000003
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_M  ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S))
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_V  0x3
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_S  5
+/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bits are used to configure the direction of autoload. 1: descending, 0: asce
+nding..*/
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER    (BIT(4))
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M  (BIT(4))
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S  4
+/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
+/*description: The bit is used to indicate autoload operation is finished..*/
+#define EXTMEM_ICACHE_AUTOLOAD_DONE    (BIT(3))
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_M  (BIT(3))
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_S  3
+/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable and disable autoload operation. It is combined with ic
+ache_autoload_done. 1: enable, 0: disable. .*/
+#define EXTMEM_ICACHE_AUTOLOAD_ENA    (BIT(2))
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_M  (BIT(2))
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_S  2
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bits are used to enable the second section for autoload operation..*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA    (BIT(1))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S  1
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bits are used to enable the first section for autoload operation..*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA    (BIT(0))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V  0x1
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xA4)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of the first section
+for autoload operation. It should be combined with icache_autoload_sct0_ena..*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xA8)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: The bits are used to configure the length of the first section for autoload oper
+ation. It should be combined with icache_autoload_sct0_ena..*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE    0x07FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V  0x7FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0xAC)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of the second section f
+or autoload operation. It should be combined with icache_autoload_sct1_ena..*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0xB0)
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
+/*description: The bits are used to configure the length of the second section for autoload ope
+ration. It should be combined with icache_autoload_sct1_ena..*/
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE    0x07FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M  ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V  0x7FFFFFF
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xB4)
+/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h44000000 ; */
+/*description: The bits are used to configure the start virtual address of ibus to access flash
+. The register is used to give constraints to ibus access counter..*/
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR    0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S))
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S  0
+
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xB8)
+/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h47ffffff ; */
+/*description: The bits are used to configure the end virtual address of ibus to access flash.
+The register is used to give constraints to ibus access counter..*/
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR    0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S  0
+
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xBC)
+/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the start virtual address of dbus to access flash
+. The register is used to give constraints to dbus access counter..*/
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR    0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S))
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S  0
+
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG          (DR_REG_EXTMEM_BASE + 0xC0)
+/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The bits are used to configure the end virtual address of dbus to access flash.
+The register is used to give constraints to dbus access counter..*/
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR    0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M  ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V  0xFFFFFFFF
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S  0
+
+#define EXTMEM_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0xC4)
+/* EXTMEM_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear icache counter..*/
+#define EXTMEM_ICACHE_ACS_CNT_CLR    (BIT(1))
+#define EXTMEM_ICACHE_ACS_CNT_CLR_M  (BIT(1))
+#define EXTMEM_ICACHE_ACS_CNT_CLR_V  0x1
+#define EXTMEM_ICACHE_ACS_CNT_CLR_S  1
+/* EXTMEM_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear dcache counter..*/
+#define EXTMEM_DCACHE_ACS_CNT_CLR    (BIT(0))
+#define EXTMEM_DCACHE_ACS_CNT_CLR_M  (BIT(0))
+#define EXTMEM_DCACHE_ACS_CNT_CLR_V  0x1
+#define EXTMEM_DCACHE_ACS_CNT_CLR_S  0
+
+#define EXTMEM_IBUS_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xC8)
+/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of the cache miss caused by ibus access fl
+ash/spiram..*/
+#define EXTMEM_IBUS_ACS_MISS_CNT    0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_MISS_CNT_M  ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S))
+#define EXTMEM_IBUS_ACS_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_MISS_CNT_S  0
+
+#define EXTMEM_IBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xCC)
+/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of ibus access flash/spiram through icache
+..*/
+#define EXTMEM_IBUS_ACS_CNT    0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_CNT_M  ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S))
+#define EXTMEM_IBUS_ACS_CNT_V  0xFFFFFFFF
+#define EXTMEM_IBUS_ACS_CNT_S  0
+
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xD0)
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of the cache miss caused by dbus access fl
+ash..*/
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT    0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M  ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S  0
+
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xD4)
+/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of the cache miss caused by dbus access sp
+iram..*/
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT    0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M  ((EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S))
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S  0
+
+#define EXTMEM_DBUS_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0xD8)
+/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to count the number of dbus access flash/spiram through dcache
+..*/
+#define EXTMEM_DBUS_ACS_CNT    0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_CNT_M  ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S))
+#define EXTMEM_DBUS_ACS_CNT_V  0xFFFFFFFF
+#define EXTMEM_DBUS_ACS_CNT_S  0
+
+#define EXTMEM_CACHE_ILG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0xDC)
+/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dbus counter overflow..*/
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA    (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V  0x1
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S  8
+/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus counter overflow..*/
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA    (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V  0x1
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S  7
+/* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dcache trying to replace a line whose blo
+cks all have been occupied by occupy-mode..*/
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA    (BIT(6))
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M  (BIT(6))
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V  0x1
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S  6
+/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by mmu entry fault..*/
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA    (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S  5
+/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by dcache trying to write flash..*/
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA    (BIT(4))
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M  (BIT(4))
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V  0x1
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S  4
+/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by preload configurations fault..*/
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA    (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M  (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S  3
+/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by sync configurations fault..*/
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA    (BIT(2))
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M  (BIT(2))
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S  2
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by preload configurations fault..*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by sync configurations fault..*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA    (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S  0
+
+#define EXTMEM_CACHE_ILG_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0xE0)
+/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dbus counter overflow..*/
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR    (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M  (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V  0x1
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S  8
+/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus counter overflow..*/
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR    (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M  (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V  0x1
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S  7
+/* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dcache trying to replace a line whose block
+ks all have been occupied by occupy-mode..*/
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR    (BIT(6))
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M  (BIT(6))
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V  0x1
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S  6
+/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by mmu entry fault..*/
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR    (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S  5
+/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by dcache trying to write flash..*/
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR    (BIT(4))
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M  (BIT(4))
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V  0x1
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S  4
+/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by preload configurations fault..*/
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR    (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M  (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S  3
+/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by sync configurations fault..*/
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR    (BIT(2))
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M  (BIT(2))
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S  2
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by preload configurations fault..*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by sync configurations fault..*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR    (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S  0
+
+#define EXTMEM_CACHE_ILG_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0xE4)
+/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access spiram miss counter overflo
+w..*/
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST    (BIT(11))
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_M  (BIT(11))
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S  11
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access flash miss counter overflow
+..*/
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST    (BIT(10))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M  (BIT(10))
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S  10
+/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dbus access flash/spiram counter overflow
+ow..*/
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST    (BIT(9))
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M  (BIT(9))
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V  0x1
+#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S  9
+/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter o
+verflow..*/
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST    (BIT(8))
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V  0x1
+#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S  8
+/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus access flash/spiram counter overflow
+ow..*/
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST    (BIT(7))
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M  (BIT(7))
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V  0x1
+#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S  7
+/* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dcache trying to replace a line whose b
+locks all have been occupied by occupy-mode..*/
+#define EXTMEM_DCACHE_OCCUPY_EXC_ST    (BIT(6))
+#define EXTMEM_DCACHE_OCCUPY_EXC_ST_M  (BIT(6))
+#define EXTMEM_DCACHE_OCCUPY_EXC_ST_V  0x1
+#define EXTMEM_DCACHE_OCCUPY_EXC_ST_S  6
+/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by mmu entry fault..*/
+#define EXTMEM_MMU_ENTRY_FAULT_ST    (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_ST_M  (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_ST_V  0x1
+#define EXTMEM_MMU_ENTRY_FAULT_ST_S  5
+/* EXTMEM_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by dcache trying to write flash..*/
+#define EXTMEM_DCACHE_WRITE_FLASH_ST    (BIT(4))
+#define EXTMEM_DCACHE_WRITE_FLASH_ST_M  (BIT(4))
+#define EXTMEM_DCACHE_WRITE_FLASH_ST_V  0x1
+#define EXTMEM_DCACHE_WRITE_FLASH_ST_S  4
+/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by preload configurations fault..*/
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST    (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_M  (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S  3
+/* EXTMEM_DCACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by sync configurations fault..*/
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST    (BIT(2))
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_M  (BIT(2))
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V  0x1
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S  2
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by preload configurations fault..*/
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S  1
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by sync configurations fault..*/
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST    (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V  0x1
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0xE8)
+/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail..*/
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA    (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access dcache while the corresponding
+ dbus is disabled which include speculative access..*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA    (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail..*/
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA    (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S  2
+/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA    (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access icache while the corresponding
+ ibus is disabled which include speculative access..*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA    (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0xEC)
+/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail..*/
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR    (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access dcache while the corresponding
+dbus is disabled or dcache is disabled which include speculative access..*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR    (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail..*/
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR    (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S  2
+/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR    (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access icache while the corresponding
+ibus is disabled or icache is disabled which include speculative access..*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR    (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S  0
+
+#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0xF0)
+/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail..*/
+#define EXTMEM_CORE0_DBUS_REJECT_ST    (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_ST_M  (BIT(4))
+#define EXTMEM_CORE0_DBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_REJECT_ST_S  4
+/* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access dcache while the core0_dbus
+is disabled or dcache is disabled which include speculative access..*/
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST    (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_M  (BIT(3))
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V  0x1
+#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S  3
+/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail..*/
+#define EXTMEM_CORE0_IBUS_REJECT_ST    (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_ST_M  (BIT(2))
+#define EXTMEM_CORE0_IBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_REJECT_ST_S  2
+/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST    (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M  (BIT(1))
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S  1
+/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access  icache while the core0_ibus
+ is disabled or icache is disabled which include speculative access..*/
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST    (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M  (BIT(0))
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V  0x1
+#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S  0
+
+#define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0xF4)
+/* EXTMEM_CORE1_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail..*/
+#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA    (BIT(4))
+#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_M  (BIT(4))
+#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S  4
+/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access dcache while the corresponding
+ dbus is disabled which include speculative access..*/
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA    (BIT(3))
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M  (BIT(3))
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V  0x1
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S  3
+/* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by authentication fail..*/
+#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA    (BIT(2))
+#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_M  (BIT(2))
+#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V  0x1
+#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S  2
+/* EXTMEM_CORE1_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA    (BIT(1))
+#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_M  (BIT(1))
+#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S  1
+/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable interrupt by cpu access icache while the corresponding
+ ibus is disabled which include speculative access..*/
+#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA    (BIT(0))
+#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(0))
+#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S  0
+
+#define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG          (DR_REG_EXTMEM_BASE + 0xF8)
+/* EXTMEM_CORE1_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail..*/
+#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR    (BIT(4))
+#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_M  (BIT(4))
+#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S  4
+/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access dcache while the corresponding
+dbus is disabled or dcache is disabled which include speculative access..*/
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR    (BIT(3))
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_M  (BIT(3))
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V  0x1
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S  3
+/* EXTMEM_CORE1_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by authentication fail..*/
+#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR    (BIT(2))
+#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M  (BIT(2))
+#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V  0x1
+#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S  2
+/* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR    (BIT(1))
+#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_M  (BIT(1))
+#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S  1
+/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to clear interrupt by cpu access icache while the corresponding
+ibus is disabled or icache is disabled which include speculative access..*/
+#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR    (BIT(0))
+#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_M  (BIT(0))
+#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V  0x1
+#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S  0
+
+#define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG          (DR_REG_EXTMEM_BASE + 0xFC)
+/* EXTMEM_CORE1_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail..*/
+#define EXTMEM_CORE1_DBUS_REJECT_ST    (BIT(4))
+#define EXTMEM_CORE1_DBUS_REJECT_ST_M  (BIT(4))
+#define EXTMEM_CORE1_DBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE1_DBUS_REJECT_ST_S  4
+/* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access dcache while the core1_dbus
+is disabled or dcache is disabled which include speculative access..*/
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST    (BIT(3))
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_M  (BIT(3))
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V  0x1
+#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S  3
+/* EXTMEM_CORE1_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by authentication fail..*/
+#define EXTMEM_CORE1_IBUS_REJECT_ST    (BIT(2))
+#define EXTMEM_CORE1_IBUS_REJECT_ST_M  (BIT(2))
+#define EXTMEM_CORE1_IBUS_REJECT_ST_V  0x1
+#define EXTMEM_CORE1_IBUS_REJECT_ST_S  2
+/* EXTMEM_CORE1_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by ibus trying to write icache.*/
+#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST    (BIT(1))
+#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M  (BIT(1))
+#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V  0x1
+#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S  1
+/* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate interrupt by cpu access  icache while the core1_ibus
+ is disabled or  icache is disabled which include speculative access..*/
+#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST    (BIT(0))
+#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_M  (BIT(0))
+#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V  0x1
+#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S  0
+
+#define EXTMEM_CORE0_DBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x100)
+/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access dbus when authentication fai
+l. 0: WORLD0, 1: WORLD1.*/
+#define EXTMEM_CORE0_DBUS_WORLD    (BIT(6))
+#define EXTMEM_CORE0_DBUS_WORLD_M  (BIT(6))
+#define EXTMEM_CORE0_DBUS_WORLD_V  0x1
+#define EXTMEM_CORE0_DBUS_WORLD_S  6
+/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati
+on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
+#define EXTMEM_CORE0_DBUS_ATTR    0x00000007
+#define EXTMEM_CORE0_DBUS_ATTR_M  ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
+#define EXTMEM_CORE0_DBUS_ATTR_V  0x7
+#define EXTMEM_CORE0_DBUS_ATTR_S  3
+/* EXTMEM_CORE0_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of data from external memory when au
+thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
+#define EXTMEM_CORE0_DBUS_TAG_ATTR    0x00000007
+#define EXTMEM_CORE0_DBUS_TAG_ATTR_M  ((EXTMEM_CORE0_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_DBUS_TAG_ATTR_S))
+#define EXTMEM_CORE0_DBUS_TAG_ATTR_V  0x7
+#define EXTMEM_CORE0_DBUS_TAG_ATTR_S  0
+
+#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x104)
+/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access dbus when authen
+tication fail..*/
+#define EXTMEM_CORE0_DBUS_VADDR    0xFFFFFFFF
+#define EXTMEM_CORE0_DBUS_VADDR_M  ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
+#define EXTMEM_CORE0_DBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE0_DBUS_VADDR_S  0
+
+#define EXTMEM_CORE0_IBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x108)
+/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access ibus when authentication fai
+l. 0: WORLD0, 1: WORLD1.*/
+#define EXTMEM_CORE0_IBUS_WORLD    (BIT(6))
+#define EXTMEM_CORE0_IBUS_WORLD_M  (BIT(6))
+#define EXTMEM_CORE0_IBUS_WORLD_V  0x1
+#define EXTMEM_CORE0_IBUS_WORLD_S  6
+/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati
+on fail. 0: invalidate, 1: execute-able, 2: read-able.*/
+#define EXTMEM_CORE0_IBUS_ATTR    0x00000007
+#define EXTMEM_CORE0_IBUS_ATTR_M  ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S))
+#define EXTMEM_CORE0_IBUS_ATTR_V  0x7
+#define EXTMEM_CORE0_IBUS_ATTR_S  3
+/* EXTMEM_CORE0_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of data from external memory when au
+thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
+#define EXTMEM_CORE0_IBUS_TAG_ATTR    0x00000007
+#define EXTMEM_CORE0_IBUS_TAG_ATTR_M  ((EXTMEM_CORE0_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_IBUS_TAG_ATTR_S))
+#define EXTMEM_CORE0_IBUS_TAG_ATTR_V  0x7
+#define EXTMEM_CORE0_IBUS_TAG_ATTR_S  0
+
+#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x10C)
+/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access  ibus when authe
+ntication fail..*/
+#define EXTMEM_CORE0_IBUS_VADDR    0xFFFFFFFF
+#define EXTMEM_CORE0_IBUS_VADDR_M  ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
+#define EXTMEM_CORE0_IBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE0_IBUS_VADDR_S  0
+
+#define EXTMEM_CORE1_DBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x110)
+/* EXTMEM_CORE1_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access dbus when authentication fai
+l. 0: WORLD0, 1: WORLD1.*/
+#define EXTMEM_CORE1_DBUS_WORLD    (BIT(6))
+#define EXTMEM_CORE1_DBUS_WORLD_M  (BIT(6))
+#define EXTMEM_CORE1_DBUS_WORLD_V  0x1
+#define EXTMEM_CORE1_DBUS_WORLD_S  6
+/* EXTMEM_CORE1_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access dbus when authenticati
+on fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
+#define EXTMEM_CORE1_DBUS_ATTR    0x00000007
+#define EXTMEM_CORE1_DBUS_ATTR_M  ((EXTMEM_CORE1_DBUS_ATTR_V)<<(EXTMEM_CORE1_DBUS_ATTR_S))
+#define EXTMEM_CORE1_DBUS_ATTR_V  0x7
+#define EXTMEM_CORE1_DBUS_ATTR_S  3
+/* EXTMEM_CORE1_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of data from external memory when au
+thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
+#define EXTMEM_CORE1_DBUS_TAG_ATTR    0x00000007
+#define EXTMEM_CORE1_DBUS_TAG_ATTR_M  ((EXTMEM_CORE1_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_DBUS_TAG_ATTR_S))
+#define EXTMEM_CORE1_DBUS_TAG_ATTR_V  0x7
+#define EXTMEM_CORE1_DBUS_TAG_ATTR_S  0
+
+#define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x114)
+/* EXTMEM_CORE1_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access dbus when authen
+tication fail..*/
+#define EXTMEM_CORE1_DBUS_VADDR    0xFFFFFFFF
+#define EXTMEM_CORE1_DBUS_VADDR_M  ((EXTMEM_CORE1_DBUS_VADDR_V)<<(EXTMEM_CORE1_DBUS_VADDR_S))
+#define EXTMEM_CORE1_DBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE1_DBUS_VADDR_S  0
+
+#define EXTMEM_CORE1_IBUS_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x118)
+/* EXTMEM_CORE1_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the world of CPU access ibus when authentication fai
+l. 0: WORLD0, 1: WORLD1.*/
+#define EXTMEM_CORE1_IBUS_WORLD    (BIT(6))
+#define EXTMEM_CORE1_IBUS_WORLD_M  (BIT(6))
+#define EXTMEM_CORE1_IBUS_WORLD_V  0x1
+#define EXTMEM_CORE1_IBUS_WORLD_S  6
+/* EXTMEM_CORE1_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of CPU access ibus when authenticati
+on fail. 0: invalidate, 1: execute-able, 2: read-able.*/
+#define EXTMEM_CORE1_IBUS_ATTR    0x00000007
+#define EXTMEM_CORE1_IBUS_ATTR_M  ((EXTMEM_CORE1_IBUS_ATTR_V)<<(EXTMEM_CORE1_IBUS_ATTR_S))
+#define EXTMEM_CORE1_IBUS_ATTR_V  0x7
+#define EXTMEM_CORE1_IBUS_ATTR_S  3
+/* EXTMEM_CORE1_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The bits are used to indicate the attribute of data from external memory when au
+thentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able..*/
+#define EXTMEM_CORE1_IBUS_TAG_ATTR    0x00000007
+#define EXTMEM_CORE1_IBUS_TAG_ATTR_M  ((EXTMEM_CORE1_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_IBUS_TAG_ATTR_S))
+#define EXTMEM_CORE1_IBUS_TAG_ATTR_V  0x7
+#define EXTMEM_CORE1_IBUS_TAG_ATTR_S  0
+
+#define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x11C)
+/* EXTMEM_CORE1_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: The bits are used to indicate the virtual address of CPU access  ibus when authe
+ntication fail..*/
+#define EXTMEM_CORE1_IBUS_VADDR    0xFFFFFFFF
+#define EXTMEM_CORE1_IBUS_VADDR_M  ((EXTMEM_CORE1_IBUS_VADDR_V)<<(EXTMEM_CORE1_IBUS_VADDR_S))
+#define EXTMEM_CORE1_IBUS_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CORE1_IBUS_VADDR_S  0
+
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x120)
+/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: The right-most 3 bits are used to indicate the operations which cause mmu fault
+occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
+evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
+ 7: external dma rx. The most significant bit is used to indicate this operation
+ occurs in which one icache. .*/
+#define EXTMEM_CACHE_MMU_FAULT_CODE    0x0000000F
+#define EXTMEM_CACHE_MMU_FAULT_CODE_M  ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S))
+#define EXTMEM_CACHE_MMU_FAULT_CODE_V  0xF
+#define EXTMEM_CACHE_MMU_FAULT_CODE_S  16
+/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[15:0] ;default: 17'h0 ; */
+/*description: The bits are used to indicate the content of mmu entry which cause mmu fault...*/
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT    0x0000FFFF
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M  ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V  0xFFFF
+#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S  0
+
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x124)
+/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The bits are used to indicate the virtual address which cause mmu fault...*/
+#define EXTMEM_CACHE_MMU_FAULT_VADDR    0xFFFFFFFF
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_M  ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CACHE_MMU_FAULT_VADDR_S  0
+
+#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x128)
+/* EXTMEM_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable wrap around mode when read data from spiram..*/
+#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND    (BIT(1))
+#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_M  (BIT(1))
+#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V  0x1
+#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S  1
+/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable wrap around mode when read data from flash..*/
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND    (BIT(0))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V  0x1
+#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S  0
+
+#define EXTMEM_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x12C)
+/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up.*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU    (BIT(2))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M  (BIT(2))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S  2
+/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down.*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD    (BIT(1))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M  (BIT(1))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S  1
+/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable clock gating to save power when access mmu memory, 0:
+enable, 1: disable.*/
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON    (BIT(0))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V  0x1
+#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S  0
+
+#define EXTMEM_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x130)
+/* EXTMEM_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h001 ; */
+/*description: The bit is used to indicate whether dcache main fsm is in idle state or not. 1:
+in idle state,  0: not in idle state.*/
+#define EXTMEM_DCACHE_STATE    0x00000FFF
+#define EXTMEM_DCACHE_STATE_M  ((EXTMEM_DCACHE_STATE_V)<<(EXTMEM_DCACHE_STATE_S))
+#define EXTMEM_DCACHE_STATE_V  0xFFF
+#define EXTMEM_DCACHE_STATE_S  12
+/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h001 ; */
+/*description: The bit is used to indicate whether  icache main fsm is in idle state or not. 1:
+ in idle state,  0: not in idle state.*/
+#define EXTMEM_ICACHE_STATE    0x00000FFF
+#define EXTMEM_ICACHE_STATE_M  ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
+#define EXTMEM_ICACHE_STATE_V  0xFFF
+#define EXTMEM_ICACHE_STATE_S  0
+
+#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0x134)
+/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Reserved..*/
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT    (BIT(1))
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
+#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S  1
+/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Reserved..*/
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT    (BIT(0))
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V  0x1
+#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S  0
+
+#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0x138)
+/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of external memory encrypt and decrypt clo
+ck. 1: close gating, 0: open clock gating..*/
+#define EXTMEM_CLK_FORCE_ON_CRYPT    (BIT(2))
+#define EXTMEM_CLK_FORCE_ON_CRYPT_M  (BIT(2))
+#define EXTMEM_CLK_FORCE_ON_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_CRYPT_S  2
+/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of automatic crypt clock. 1: close gating,
+ 0: open clock gating..*/
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT    (BIT(1))
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M  (BIT(1))
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S  1
+/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to close clock gating of manual crypt clock. 1: close gating, 0:
+ open clock gating..*/
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT    (BIT(0))
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M  (BIT(0))
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V  0x1
+#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S  0
+
+#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x13C)
+/* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Reserved..*/
+#define EXTMEM_ALLOC_WB_HOLD_ARBITER    (BIT(0))
+#define EXTMEM_ALLOC_WB_HOLD_ARBITER_M  (BIT(0))
+#define EXTMEM_ALLOC_WB_HOLD_ARBITER_V  0x1
+#define EXTMEM_ALLOC_WB_HOLD_ARBITER_S  0
+
+#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x140)
+/* EXTMEM_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by dcache pre-load done..*/
+#define EXTMEM_DCACHE_PRELOAD_INT_CLR    (BIT(5))
+#define EXTMEM_DCACHE_PRELOAD_INT_CLR_M  (BIT(5))
+#define EXTMEM_DCACHE_PRELOAD_INT_CLR_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_INT_CLR_S  5
+/* EXTMEM_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by dcache pre-load done..*/
+#define EXTMEM_DCACHE_PRELOAD_INT_ENA    (BIT(4))
+#define EXTMEM_DCACHE_PRELOAD_INT_ENA_M  (BIT(4))
+#define EXTMEM_DCACHE_PRELOAD_INT_ENA_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_INT_ENA_S  4
+/* EXTMEM_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by dcache pre-load done..*/
+#define EXTMEM_DCACHE_PRELOAD_INT_ST    (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_INT_ST_M  (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_INT_ST_V  0x1
+#define EXTMEM_DCACHE_PRELOAD_INT_ST_S  3
+/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by  icache pre-load done..*/
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR    (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S  2
+/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by  icache pre-load done..*/
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA    (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S  1
+/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by  icache pre-load done..*/
+#define EXTMEM_ICACHE_PRELOAD_INT_ST    (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_V  0x1
+#define EXTMEM_ICACHE_PRELOAD_INT_ST_S  0
+
+#define EXTMEM_CACHE_SYNC_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x144)
+/* EXTMEM_DCACHE_SYNC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by dcache sync done..*/
+#define EXTMEM_DCACHE_SYNC_INT_CLR    (BIT(5))
+#define EXTMEM_DCACHE_SYNC_INT_CLR_M  (BIT(5))
+#define EXTMEM_DCACHE_SYNC_INT_CLR_V  0x1
+#define EXTMEM_DCACHE_SYNC_INT_CLR_S  5
+/* EXTMEM_DCACHE_SYNC_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by dcache sync done..*/
+#define EXTMEM_DCACHE_SYNC_INT_ENA    (BIT(4))
+#define EXTMEM_DCACHE_SYNC_INT_ENA_M  (BIT(4))
+#define EXTMEM_DCACHE_SYNC_INT_ENA_V  0x1
+#define EXTMEM_DCACHE_SYNC_INT_ENA_S  4
+/* EXTMEM_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by dcache sync done..*/
+#define EXTMEM_DCACHE_SYNC_INT_ST    (BIT(3))
+#define EXTMEM_DCACHE_SYNC_INT_ST_M  (BIT(3))
+#define EXTMEM_DCACHE_SYNC_INT_ST_V  0x1
+#define EXTMEM_DCACHE_SYNC_INT_ST_S  3
+/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to clear the interrupt by  icache sync done..*/
+#define EXTMEM_ICACHE_SYNC_INT_CLR    (BIT(2))
+#define EXTMEM_ICACHE_SYNC_INT_CLR_M  (BIT(2))
+#define EXTMEM_ICACHE_SYNC_INT_CLR_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_CLR_S  2
+/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable the interrupt by  icache sync done..*/
+#define EXTMEM_ICACHE_SYNC_INT_ENA    (BIT(1))
+#define EXTMEM_ICACHE_SYNC_INT_ENA_M  (BIT(1))
+#define EXTMEM_ICACHE_SYNC_INT_ENA_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_ENA_S  1
+/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the interrupt by  icache sync done..*/
+#define EXTMEM_ICACHE_SYNC_INT_ST    (BIT(0))
+#define EXTMEM_ICACHE_SYNC_INT_ST_M  (BIT(0))
+#define EXTMEM_ICACHE_SYNC_INT_ST_V  0x1
+#define EXTMEM_ICACHE_SYNC_INT_ST_S  0
+
+#define EXTMEM_CACHE_MMU_OWNER_REG          (DR_REG_EXTMEM_BASE + 0x148)
+/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2:
+dma, bit3: reserved..*/
+#define EXTMEM_CACHE_MMU_OWNER    0x00FFFFFF
+#define EXTMEM_CACHE_MMU_OWNER_M  ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
+#define EXTMEM_CACHE_MMU_OWNER_V  0xFFFFFF
+#define EXTMEM_CACHE_MMU_OWNER_S  0
+
+#define EXTMEM_CACHE_CONF_MISC_REG          (DR_REG_EXTMEM_BASE + 0x14C)
+/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to enable cache trace function..*/
+#define EXTMEM_CACHE_TRACE_ENA    (BIT(2))
+#define EXTMEM_CACHE_TRACE_ENA_M  (BIT(2))
+#define EXTMEM_CACHE_TRACE_ENA_V  0x1
+#define EXTMEM_CACHE_TRACE_ENA_S  2
+/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: The bit is used to disable checking mmu entry fault by sync operation..*/
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT    (BIT(1))
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M  (BIT(1))
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V  0x1
+#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S  1
+/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to disable checking mmu entry fault by preload operation..*/
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT    (BIT(0))
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M  (BIT(0))
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V  0x1
+#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S  0
+
+#define EXTMEM_DCACHE_FREEZE_REG          (DR_REG_EXTMEM_BASE + 0x150)
+/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to indicate dcache freeze success.*/
+#define EXTMEM_DCACHE_FREEZE_DONE    (BIT(2))
+#define EXTMEM_DCACHE_FREEZE_DONE_M  (BIT(2))
+#define EXTMEM_DCACHE_FREEZE_DONE_V  0x1
+#define EXTMEM_DCACHE_FREEZE_DONE_S  2
+/* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert
+hit if CPU miss.*/
+#define EXTMEM_DCACHE_FREEZE_MODE    (BIT(1))
+#define EXTMEM_DCACHE_FREEZE_MODE_M  (BIT(1))
+#define EXTMEM_DCACHE_FREEZE_MODE_V  0x1
+#define EXTMEM_DCACHE_FREEZE_MODE_S  1
+/* EXTMEM_DCACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable dcache freeze mode.*/
+#define EXTMEM_DCACHE_FREEZE_ENA    (BIT(0))
+#define EXTMEM_DCACHE_FREEZE_ENA_M  (BIT(0))
+#define EXTMEM_DCACHE_FREEZE_ENA_V  0x1
+#define EXTMEM_DCACHE_FREEZE_ENA_S  0
+
+#define EXTMEM_ICACHE_FREEZE_REG          (DR_REG_EXTMEM_BASE + 0x154)
+/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
+/*description: The bit is used to indicate icache freeze success.*/
+#define EXTMEM_ICACHE_FREEZE_DONE    (BIT(2))
+#define EXTMEM_ICACHE_FREEZE_DONE_M  (BIT(2))
+#define EXTMEM_ICACHE_FREEZE_DONE_V  0x1
+#define EXTMEM_ICACHE_FREEZE_DONE_S  2
+/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert
+hit if CPU miss.*/
+#define EXTMEM_ICACHE_FREEZE_MODE    (BIT(1))
+#define EXTMEM_ICACHE_FREEZE_MODE_M  (BIT(1))
+#define EXTMEM_ICACHE_FREEZE_MODE_V  0x1
+#define EXTMEM_ICACHE_FREEZE_MODE_S  1
+/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to enable icache freeze mode.*/
+#define EXTMEM_ICACHE_FREEZE_ENA    (BIT(0))
+#define EXTMEM_ICACHE_FREEZE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_FREEZE_ENA_V  0x1
+#define EXTMEM_ICACHE_FREEZE_ENA_S  0
+
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG          (DR_REG_EXTMEM_BASE + 0x158)
+/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to activate icache atomic operation protection. In this case, sy
+nc/lock operation can not interrupt miss-work. This feature does not work during
+ invalidateAll operation..*/
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA    (BIT(0))
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M  (BIT(0))
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V  0x1
+#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S  0
+
+#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG          (DR_REG_EXTMEM_BASE + 0x15C)
+/* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to activate dcache atomic operation protection. In this case, sy
+nc/lock/occupy operation can not interrupt miss-work. This feature does not work
+ during invalidateAll operation..*/
+#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA    (BIT(0))
+#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M  (BIT(0))
+#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V  0x1
+#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S  0
+
+#define EXTMEM_CACHE_REQUEST_REG          (DR_REG_EXTMEM_BASE + 0x160)
+/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The bit is used to disable request recording which could cause performance issue.*/
+#define EXTMEM_CACHE_REQUEST_BYPASS    (BIT(0))
+#define EXTMEM_CACHE_REQUEST_BYPASS_M  (BIT(0))
+#define EXTMEM_CACHE_REQUEST_BYPASS_V  0x1
+#define EXTMEM_CACHE_REQUEST_BYPASS_S  0
+
+#define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x164)
+/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Reserved..*/
+#define EXTMEM_CLK_EN    (BIT(0))
+#define EXTMEM_CLK_EN_M  (BIT(0))
+#define EXTMEM_CLK_EN_V  0x1
+#define EXTMEM_CLK_EN_S  0
+
+#define EXTMEM_CACHE_TAG_OBJECT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x180)
+/* EXTMEM_DCACHE_TAG_OBJECT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to set dcache tag memory as object. This bit should be onehot with
+the others fields inside this register..*/
+#define EXTMEM_DCACHE_TAG_OBJECT    (BIT(1))
+#define EXTMEM_DCACHE_TAG_OBJECT_M  (BIT(1))
+#define EXTMEM_DCACHE_TAG_OBJECT_V  0x1
+#define EXTMEM_DCACHE_TAG_OBJECT_S  1
+/* EXTMEM_ICACHE_TAG_OBJECT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to set icache tag memory as object. This bit should be onehot with
+the others fields inside this register..*/
+#define EXTMEM_ICACHE_TAG_OBJECT    (BIT(0))
+#define EXTMEM_ICACHE_TAG_OBJECT_M  (BIT(0))
+#define EXTMEM_ICACHE_TAG_OBJECT_V  0x1
+#define EXTMEM_ICACHE_TAG_OBJECT_S  0
+
+#define EXTMEM_CACHE_TAG_WAY_OBJECT_REG          (DR_REG_EXTMEM_BASE + 0x184)
+/* EXTMEM_CACHE_TAG_WAY_OBJECT : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: Set this bits to select which way of the tag-object will be accessed. 0: way0, 1
+: way1, 2: way2, 3: way3, .., 7: way7..*/
+#define EXTMEM_CACHE_TAG_WAY_OBJECT    0x00000007
+#define EXTMEM_CACHE_TAG_WAY_OBJECT_M  ((EXTMEM_CACHE_TAG_WAY_OBJECT_V)<<(EXTMEM_CACHE_TAG_WAY_OBJECT_S))
+#define EXTMEM_CACHE_TAG_WAY_OBJECT_V  0x7
+#define EXTMEM_CACHE_TAG_WAY_OBJECT_S  0
+
+#define EXTMEM_CACHE_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x188)
+/* EXTMEM_CACHE_VADDR : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */
+/*description: Those bits stores the virtual address which will decide where inside the
+specified tag memory object will be accessed..*/
+#define EXTMEM_CACHE_VADDR    0xFFFFFFFF
+#define EXTMEM_CACHE_VADDR_M  ((EXTMEM_CACHE_VADDR_V)<<(EXTMEM_CACHE_VADDR_S))
+#define EXTMEM_CACHE_VADDR_V  0xFFFFFFFF
+#define EXTMEM_CACHE_VADDR_S  0
+
+#define EXTMEM_CACHE_TAG_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x18C)
+/* EXTMEM_CACHE_TAG_CONTENT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: This is a constant place where we can write data to or read data from the tag me
+mory on the specified cache..*/
+#define EXTMEM_CACHE_TAG_CONTENT    0xFFFFFFFF
+#define EXTMEM_CACHE_TAG_CONTENT_M  ((EXTMEM_CACHE_TAG_CONTENT_V)<<(EXTMEM_CACHE_TAG_CONTENT_S))
+#define EXTMEM_CACHE_TAG_CONTENT_V  0xFFFFFFFF
+#define EXTMEM_CACHE_TAG_CONTENT_S  0
+
+#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
+/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012310 ; */
+/*description: version information..*/
+#define EXTMEM_DATE    0x0FFFFFFF
+#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
+#define EXTMEM_DATE_V  0xFFFFFFF
+#define EXTMEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EXTMEM_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/extmem_struct.h b/components/soc/esp32s3/register/soc/extmem_struct.h
new file mode 100644
index 00000000000..8e2a9aad3c2
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/extmem_struct.h
@@ -0,0 +1,790 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_EXTMEM_STRUCT_H_
+#define _SOC_EXTMEM_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct extmem_dev_s {
+    union {
+        struct {
+            uint32_t dcache_enable                 :    1;  /*The bit is used to activate the data cache. 0: disable, 1: enable*/
+            uint32_t reserved1                     :    1;  /*Reserved*/
+            uint32_t dcache_size_mode              :    1;  /*The bit is used to configure cache memory size.0: 32KB, 1: 64KB*/
+            uint32_t dcache_blocksize_mode         :    2;  /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } dcache_ctrl;
+    union {
+        struct {
+            uint32_t dcache_shut_core0_bus         :    1;  /*The bit is used to disable core0 dbus, 0: enable, 1: disable*/
+            uint32_t dcache_shut_core1_bus         :    1;  /*The bit is used to disable core1 dbus, 0: enable, 1: disable*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } dcache_ctrl1;
+    union {
+        struct {
+            uint32_t dcache_tag_mem_force_on       :    1;  /*The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.*/
+            uint32_t dcache_tag_mem_force_pd       :    1;  /*The bit is used to power dcache tag memory down, 0: follow  rtc_lslp_pd, 1: power down*/
+            uint32_t dcache_tag_mem_force_pu       :    1;  /*The bit is used to power dcache tag memory up, 0: follow  rtc_lslp_pd, 1: power up*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } dcache_tag_power_ctrl;
+    union {
+        struct {
+            uint32_t dcache_prelock_sct0_en        :    1;  /*The bit is used to enable the first section of prelock function.*/
+            uint32_t dcache_prelock_sct1_en        :    1;  /*The bit is used to enable the second section of prelock function.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } dcache_prelock_ctrl;
+    uint32_t dcache_prelock_sct0_addr;
+    uint32_t dcache_prelock_sct1_addr;
+    union {
+        struct {
+            uint32_t dcache_prelock_sct1_size      :    16;  /*The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/
+            uint32_t dcache_prelock_sct0_size      :    16;  /*The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/
+        };
+        uint32_t val;
+    } dcache_prelock_sct_size;
+    union {
+        struct {
+            uint32_t dcache_lock_ena               :    1;  /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
+            uint32_t dcache_unlock_ena             :    1;  /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
+            uint32_t dcache_lock_done              :    1;  /*The bit is used to indicate unlock/lock operation is finished.*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } dcache_lock_ctrl;
+    uint32_t dcache_lock_addr;
+    union {
+        struct {
+            uint32_t dcache_lock_size              :    16;  /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } dcache_lock_size;
+    union {
+        struct {
+            uint32_t dcache_invalidate_ena         :    1;  /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
+            uint32_t dcache_writeback_ena          :    1;  /*The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.*/
+            uint32_t dcache_clean_ena              :    1;  /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/
+            uint32_t dcache_sync_done              :    1;  /*The bit is used to indicate clean/writeback/invalidate operation is finished.*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } dcache_sync_ctrl;
+    uint32_t dcache_sync_addr;
+    union {
+        struct {
+            uint32_t dcache_sync_size              :    23;  /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/
+            uint32_t reserved23                    :    9;
+        };
+        uint32_t val;
+    } dcache_sync_size;
+    union {
+        struct {
+            uint32_t dcache_occupy_ena             :    1;  /*The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.*/
+            uint32_t dcache_occupy_done            :    1;  /*The bit is used to indicate occupy operation is finished.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } dcache_occupy_ctrl;
+    uint32_t dcache_occupy_addr;
+    union {
+        struct {
+            uint32_t dcache_occupy_size            :    16;  /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } dcache_occupy_size;
+    union {
+        struct {
+            uint32_t dcache_preload_ena            :    1;  /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
+            uint32_t dcache_preload_done           :    1;  /*The bit is used to indicate preload operation is finished.*/
+            uint32_t dcache_preload_order          :    1;  /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } dcache_preload_ctrl;
+    uint32_t dcache_preload_addr;
+    union {
+        struct {
+            uint32_t dcache_preload_size           :    16;  /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } dcache_preload_size;
+    union {
+        struct {
+            uint32_t dcache_autoload_sct0_ena      :    1;  /*The bits are used to enable the first section for autoload operation.*/
+            uint32_t dcache_autoload_sct1_ena      :    1;  /*The bits are used to enable the second section for autoload operation.*/
+            uint32_t dcache_autoload_ena           :    1;  /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. */
+            uint32_t dcache_autoload_done          :    1;  /*The bit is used to indicate autoload operation is finished.*/
+            uint32_t dcache_autoload_order         :    1;  /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/
+            uint32_t dcache_autoload_rqst          :    2;  /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
+            uint32_t dcache_autoload_size          :    2;  /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
+            uint32_t dcache_autoload_buffer_clear  :    1;  /*The bit is used to clear autoload buffer in dcache.*/
+            uint32_t reserved10                    :    22;
+        };
+        uint32_t val;
+    } dcache_autoload_ctrl;
+    uint32_t dcache_autoload_sct0_addr;
+    union {
+        struct {
+            uint32_t dcache_autoload_sct0_size     :    27;  /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
+            uint32_t reserved27                    :    5;
+        };
+        uint32_t val;
+    } dcache_autoload_sct0_size;
+    uint32_t dcache_autoload_sct1_addr;
+    union {
+        struct {
+            uint32_t dcache_autoload_sct1_size     :    27;  /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
+            uint32_t reserved27                    :    5;
+        };
+        uint32_t val;
+    } dcache_autoload_sct1_size;
+    union {
+        struct {
+            uint32_t icache_enable                 :    1;  /*The bit is used to activate the data cache. 0: disable, 1: enable*/
+            uint32_t icache_way_mode               :    1;  /*The bit is used to configure cache way mode.0: 4-way, 1: 8-way*/
+            uint32_t icache_size_mode              :    1;  /*The bit is used to configure cache memory size.0: 16KB, 1: 32KB*/
+            uint32_t icache_blocksize_mode         :    1;  /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes*/
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } icache_ctrl;
+    union {
+        struct {
+            uint32_t icache_shut_core0_bus         :    1;  /*The bit is used to disable core0 ibus, 0: enable, 1: disable*/
+            uint32_t icache_shut_core1_bus         :    1;  /*The bit is used to disable core1 ibus, 0: enable, 1: disable*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } icache_ctrl1;
+    union {
+        struct {
+            uint32_t icache_tag_mem_force_on       :    1;  /*The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.*/
+            uint32_t icache_tag_mem_force_pd       :    1;  /*The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down*/
+            uint32_t icache_tag_mem_force_pu       :    1;  /*The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } icache_tag_power_ctrl;
+    union {
+        struct {
+            uint32_t icache_prelock_sct0_en        :    1;  /*The bit is used to enable the first section of prelock function.*/
+            uint32_t icache_prelock_sct1_en        :    1;  /*The bit is used to enable the second section of prelock function.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } icache_prelock_ctrl;
+    uint32_t icache_prelock_sct0_addr;
+    uint32_t icache_prelock_sct1_addr;
+    union {
+        struct {
+            uint32_t icache_prelock_sct1_size      :    16;  /*The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
+            uint32_t icache_prelock_sct0_size      :    16;  /*The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
+        };
+        uint32_t val;
+    } icache_prelock_sct_size;
+    union {
+        struct {
+            uint32_t icache_lock_ena               :    1;  /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
+            uint32_t icache_unlock_ena             :    1;  /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
+            uint32_t icache_lock_done              :    1;  /*The bit is used to indicate unlock/lock operation is finished.*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } icache_lock_ctrl;
+    uint32_t icache_lock_addr;
+    union {
+        struct {
+            uint32_t icache_lock_size              :    16;  /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } icache_lock_size;
+    union {
+        struct {
+            uint32_t icache_invalidate_ena         :    1;  /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
+            uint32_t icache_sync_done              :    1;  /*The bit is used to indicate invalidate operation is finished.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } icache_sync_ctrl;
+    uint32_t icache_sync_addr;
+    union {
+        struct {
+            uint32_t icache_sync_size              :    23;  /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
+            uint32_t reserved23                    :    9;
+        };
+        uint32_t val;
+    } icache_sync_size;
+    union {
+        struct {
+            uint32_t icache_preload_ena            :    1;  /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
+            uint32_t icache_preload_done           :    1;  /*The bit is used to indicate preload operation is finished.*/
+            uint32_t icache_preload_order          :    1;  /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } icache_preload_ctrl;
+    uint32_t icache_preload_addr;
+    union {
+        struct {
+            uint32_t icache_preload_size           :    16;  /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } icache_preload_size;
+    union {
+        struct {
+            uint32_t icache_autoload_sct0_ena      :    1;  /*The bits are used to enable the first section for autoload operation.*/
+            uint32_t icache_autoload_sct1_ena      :    1;  /*The bits are used to enable the second section for autoload operation.*/
+            uint32_t icache_autoload_ena           :    1;  /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. */
+            uint32_t icache_autoload_done          :    1;  /*The bit is used to indicate autoload operation is finished.*/
+            uint32_t icache_autoload_order         :    1;  /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/
+            uint32_t icache_autoload_rqst          :    2;  /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
+            uint32_t icache_autoload_size          :    2;  /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
+            uint32_t icache_autoload_buffer_clear  :    1;  /*The bit is used to clear autoload buffer in icache.*/
+            uint32_t reserved10                    :    22;
+        };
+        uint32_t val;
+    } icache_autoload_ctrl;
+    uint32_t icache_autoload_sct0_addr;
+    union {
+        struct {
+            uint32_t icache_autoload_sct0_size     :    27;  /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
+            uint32_t reserved27                    :    5;
+        };
+        uint32_t val;
+    } icache_autoload_sct0_size;
+    uint32_t icache_autoload_sct1_addr;
+    union {
+        struct {
+            uint32_t icache_autoload_sct1_size     :    27;  /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
+            uint32_t reserved27                    :    5;
+        };
+        uint32_t val;
+    } icache_autoload_sct1_size;
+    uint32_t ibus_to_flash_start_vaddr;
+    uint32_t ibus_to_flash_end_vaddr;
+    uint32_t dbus_to_flash_start_vaddr;
+    uint32_t dbus_to_flash_end_vaddr;
+    union {
+        struct {
+            uint32_t dcache_acs_cnt_clr            :    1;  /*The bit is used to clear dcache counter.*/
+            uint32_t icache_acs_cnt_clr            :    1;  /*The bit is used to clear icache counter.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } cache_acs_cnt_clr;
+    uint32_t ibus_acs_miss_cnt;
+    uint32_t ibus_acs_cnt;
+    uint32_t dbus_acs_flash_miss_cnt;
+    uint32_t dbus_acs_spiram_miss_cnt;
+    uint32_t dbus_acs_cnt;
+    union {
+        struct {
+            uint32_t icache_sync_op_fault          :    1;  /*The bit is used to enable interrupt by sync configurations fault.*/
+            uint32_t icache_preload_op_fault       :    1;  /*The bit is used to enable interrupt by preload configurations fault.*/
+            uint32_t dcache_sync_op_fault          :    1;  /*The bit is used to enable interrupt by sync configurations fault.*/
+            uint32_t dcache_preload_op_fault       :    1;  /*The bit is used to enable interrupt by preload configurations fault.*/
+            uint32_t dcache_write_flash            :    1;  /*The bit is used to enable interrupt by dcache trying to write flash.*/
+            uint32_t mmu_entry_fault               :    1;  /*The bit is used to enable interrupt by mmu entry fault.*/
+            uint32_t dcache_occupy_exc             :    1;  /*The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
+            uint32_t ibus_cnt_ovf                  :    1;  /*The bit is used to enable interrupt by ibus counter overflow.*/
+            uint32_t dbus_cnt_ovf                  :    1;  /*The bit is used to enable interrupt by dbus counter overflow.*/
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } cache_ilg_int_ena;
+    union {
+        struct {
+            uint32_t icache_sync_op_fault          :    1;  /*The bit is used to clear interrupt by sync configurations fault.*/
+            uint32_t icache_preload_op_fault       :    1;  /*The bit is used to clear interrupt by preload configurations fault.*/
+            uint32_t dcache_sync_op_fault          :    1;  /*The bit is used to clear interrupt by sync configurations fault.*/
+            uint32_t dcache_preload_op_fault       :    1;  /*The bit is used to clear interrupt by preload configurations fault.*/
+            uint32_t dcache_write_flash            :    1;  /*The bit is used to clear interrupt by dcache trying to write flash.*/
+            uint32_t mmu_entry_fault               :    1;  /*The bit is used to clear interrupt by mmu entry fault.*/
+            uint32_t dcache_occupy_exc             :    1;  /*The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
+            uint32_t ibus_cnt_ovf                  :    1;  /*The bit is used to clear interrupt by ibus counter overflow.*/
+            uint32_t dbus_cnt_ovf                  :    1;  /*The bit is used to clear interrupt by dbus counter overflow.*/
+            uint32_t reserved9                     :    23;
+        };
+        uint32_t val;
+    } cache_ilg_int_clr;
+    union {
+        struct {
+            uint32_t icache_sync_op_fault_st       :    1;  /*The bit is used to indicate interrupt by sync configurations fault.*/
+            uint32_t icache_preload_op_fault_st    :    1;  /*The bit is used to indicate interrupt by preload configurations fault.*/
+            uint32_t dcache_sync_op_fault_st       :    1;  /*The bit is used to indicate interrupt by sync configurations fault.*/
+            uint32_t dcache_preload_op_fault_st    :    1;  /*The bit is used to indicate interrupt by preload configurations fault.*/
+            uint32_t dcache_write_flash_st         :    1;  /*The bit is used to indicate interrupt by dcache trying to write flash.*/
+            uint32_t mmu_entry_fault_st            :    1;  /*The bit is used to indicate interrupt by mmu entry fault.*/
+            uint32_t dcache_occupy_exc_st          :    1;  /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
+            uint32_t ibus_acs_cnt_ovf_st           :    1;  /*The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.*/
+            uint32_t ibus_acs_miss_cnt_ovf_st      :    1;  /*The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.*/
+            uint32_t dbus_acs_cnt_ovf_st           :    1;  /*The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.*/
+            uint32_t dbus_acs_flash_miss_cnt_ovf_st:    1;  /*The bit is used to indicate interrupt by dbus access flash miss counter overflow.*/
+            uint32_t dbus_acs_spiram_miss_cnt_ovf_st:    1;  /*The bit is used to indicate interrupt by dbus access spiram miss counter overflow.*/
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } cache_ilg_int_st;
+    union {
+        struct {
+            uint32_t core0_ibus_acs_msk_ic         :    1;  /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
+            uint32_t core0_ibus_wr_ic              :    1;  /*The bit is used to enable interrupt by ibus trying to write icache*/
+            uint32_t core0_ibus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
+            uint32_t core0_dbus_acs_msk_dc         :    1;  /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
+            uint32_t core0_dbus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core0_acs_cache_int_ena;
+    union {
+        struct {
+            uint32_t core0_ibus_acs_msk_ic         :    1;  /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
+            uint32_t core0_ibus_wr_ic              :    1;  /*The bit is used to clear interrupt by ibus trying to write icache*/
+            uint32_t core0_ibus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
+            uint32_t core0_dbus_acs_msk_dc         :    1;  /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
+            uint32_t core0_dbus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core0_acs_cache_int_clr;
+    union {
+        struct {
+            uint32_t core0_ibus_acs_msk_icache_st  :    1;  /*The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.*/
+            uint32_t core0_ibus_wr_icache_st       :    1;  /*The bit is used to indicate interrupt by ibus trying to write icache*/
+            uint32_t core0_ibus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
+            uint32_t core0_dbus_acs_msk_dcache_st  :    1;  /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/
+            uint32_t core0_dbus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core0_acs_cache_int_st;
+    union {
+        struct {
+            uint32_t core1_ibus_acs_msk_ic         :    1;  /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
+            uint32_t core1_ibus_wr_ic              :    1;  /*The bit is used to enable interrupt by ibus trying to write icache*/
+            uint32_t core1_ibus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
+            uint32_t core1_dbus_acs_msk_dc         :    1;  /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
+            uint32_t core1_dbus_reject             :    1;  /*The bit is used to enable interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core1_acs_cache_int_ena;
+    union {
+        struct {
+            uint32_t core1_ibus_acs_msk_ic         :    1;  /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
+            uint32_t core1_ibus_wr_ic              :    1;  /*The bit is used to clear interrupt by ibus trying to write icache*/
+            uint32_t core1_ibus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
+            uint32_t core1_dbus_acs_msk_dc         :    1;  /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
+            uint32_t core1_dbus_reject             :    1;  /*The bit is used to clear interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core1_acs_cache_int_clr;
+    union {
+        struct {
+            uint32_t core1_ibus_acs_msk_icache_st  :    1;  /*The bit is used to indicate interrupt by cpu access  icache while the core1_ibus is disabled or  icache is disabled which include speculative access.*/
+            uint32_t core1_ibus_wr_icache_st       :    1;  /*The bit is used to indicate interrupt by ibus trying to write icache*/
+            uint32_t core1_ibus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
+            uint32_t core1_dbus_acs_msk_dcache_st  :    1;  /*The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.*/
+            uint32_t core1_dbus_reject_st          :    1;  /*The bit is used to indicate interrupt by authentication fail.*/
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core1_acs_cache_int_st;
+    union {
+        struct {
+            uint32_t core0_dbus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core0_dbus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core0_dbus_world              :    1;  /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } core0_dbus_reject_st;
+    uint32_t core0_dbus_reject_vaddr;
+    union {
+        struct {
+            uint32_t core0_ibus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core0_ibus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
+            uint32_t core0_ibus_world              :    1;  /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } core0_ibus_reject_st;
+    uint32_t core0_ibus_reject_vaddr;
+    union {
+        struct {
+            uint32_t core1_dbus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core1_dbus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core1_dbus_world              :    1;  /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } core1_dbus_reject_st;
+    uint32_t core1_dbus_reject_vaddr;
+    union {
+        struct {
+            uint32_t core1_ibus_tag_attr           :    3;  /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
+            uint32_t core1_ibus_attr               :    3;  /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
+            uint32_t core1_ibus_world              :    1;  /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } core1_ibus_reject_st;
+    uint32_t core1_ibus_reject_vaddr;
+    union {
+        struct {
+            uint32_t cache_mmu_fault_content       :    16;  /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/
+            uint32_t cache_mmu_fault_code          :    4;  /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. */
+            uint32_t reserved20                    :    12;
+        };
+        uint32_t val;
+    } cache_mmu_fault_content;
+    uint32_t cache_mmu_fault_vaddr;
+    union {
+        struct {
+            uint32_t cache_flash_wrap_around       :    1;  /*The bit is used to enable wrap around mode when read data from flash.*/
+            uint32_t cache_sram_rd_wrap_around     :    1;  /*The bit is used to enable wrap around mode when read data from spiram.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } cache_wrap_around_ctrl;
+    union {
+        struct {
+            uint32_t cache_mmu_mem_force_on        :    1;  /*The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable*/
+            uint32_t cache_mmu_mem_force_pd        :    1;  /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down*/
+            uint32_t cache_mmu_mem_force_pu        :    1;  /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } cache_mmu_power_ctrl;
+    union {
+        struct {
+            uint32_t icache_state                  :    12;  /*The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state*/
+            uint32_t dcache_state                  :    12;  /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state,  0: not in idle state*/
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } cache_state;
+    union {
+        struct {
+            uint32_t record_disable_db_encrypt     :    1;  /*Reserved.*/
+            uint32_t record_disable_g0cb_decrypt   :    1;  /*Reserved.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } cache_encrypt_decrypt_record_disable;
+    union {
+        struct {
+            uint32_t clk_force_on_manual_crypt     :    1;  /*The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.*/
+            uint32_t clk_force_on_auto_crypt       :    1;  /*The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.*/
+            uint32_t clk_force_on_crypt            :    1;  /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } cache_encrypt_decrypt_clk_force_on;
+    union {
+        struct {
+            uint32_t alloc_wb_hold_arbiter         :    1;  /*Reserved.*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_bridge_arbiter_ctrl;
+    union {
+        struct {
+            uint32_t icache_preload_ist            :    1;  /*The bit is used to indicate the interrupt by  icache pre-load done.*/
+            uint32_t icache_preload_iena           :    1;  /*The bit is used to enable the interrupt by  icache pre-load done.*/
+            uint32_t icache_preload_iclr           :    1;  /*The bit is used to clear the interrupt by  icache pre-load done.*/
+            uint32_t dcache_preload_ist            :    1;  /*The bit is used to indicate the interrupt by dcache pre-load done.*/
+            uint32_t dcache_preload_iena           :    1;  /*The bit is used to enable the interrupt by dcache pre-load done.*/
+            uint32_t dcache_preload_iclr           :    1;  /*The bit is used to clear the interrupt by dcache pre-load done.*/
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } cache_preload_int_ctrl;
+    union {
+        struct {
+            uint32_t icache_sync_ist               :    1;  /*The bit is used to indicate the interrupt by  icache sync done.*/
+            uint32_t icache_sync_iena              :    1;  /*The bit is used to enable the interrupt by  icache sync done.*/
+            uint32_t icache_sync_iclr              :    1;  /*The bit is used to clear the interrupt by  icache sync done.*/
+            uint32_t dcache_sync_ist               :    1;  /*The bit is used to indicate the interrupt by dcache sync done.*/
+            uint32_t dcache_sync_iena              :    1;  /*The bit is used to enable the interrupt by dcache sync done.*/
+            uint32_t dcache_sync_iclr              :    1;  /*The bit is used to clear the interrupt by dcache sync done.*/
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } cache_sync_int_ctrl;
+    union {
+        struct {
+            uint32_t cache_mmu_owner               :    24;  /*The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.*/
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } cache_mmu_owner;
+    union {
+        struct {
+            uint32_t cache_ignore_preload_mmu_entry_fault:    1;  /*The bit is used to disable checking mmu entry fault by preload operation.*/
+            uint32_t cache_ignore_sync_mmu_entry_fault:    1;  /*The bit is used to disable checking mmu entry fault by sync operation.*/
+            uint32_t cache_trace_ena               :    1;  /*The bit is used to enable cache trace function.*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } cache_conf_misc;
+    union {
+        struct {
+            uint32_t dcache_freeze_ena             :    1;  /*The bit is used to enable dcache freeze mode*/
+            uint32_t dcache_freeze_mode            :    1;  /*The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss*/
+            uint32_t dcache_freeze_done            :    1;  /*The bit is used to indicate dcache freeze success*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } dcache_freeze;
+    union {
+        struct {
+            uint32_t icache_freeze_ena             :    1;  /*The bit is used to enable icache freeze mode*/
+            uint32_t icache_freeze_mode            :    1;  /*The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss*/
+            uint32_t icache_freeze_done            :    1;  /*The bit is used to indicate icache freeze success*/
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } icache_freeze;
+    union {
+        struct {
+            uint32_t icache_atomic_operate_ena     :    1;  /*The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } icache_atomic_operate_ena;
+    union {
+        struct {
+            uint32_t dcache_atomic_operate_ena     :    1;  /*The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dcache_atomic_operate_ena;
+    union {
+        struct {
+            uint32_t cache_request_bypass          :    1;  /*The bit is used to disable request recording which could cause performance issue*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_request;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Reserved.*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    union {
+        struct {
+            uint32_t icache_tag_object             :    1;  /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/
+            uint32_t dcache_tag_object             :    1;  /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/
+            uint32_t reserved2                     :    30;  /*Reserved*/
+        };
+        uint32_t val;
+    } cache_tag_object_ctrl;
+    union {
+        struct {
+            uint32_t cache_tag_way_object          :    3;  /*Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7.*/
+            uint32_t reserved3                     :    29;  /*Reserved*/
+        };
+        uint32_t val;
+    } cache_tag_way_object;
+    uint32_t cache_vaddr;
+    uint32_t cache_tag_content;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t extmem_reg_date               :    28;  /*version information.*/
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } date;
+} extmem_dev_t;
+extern extmem_dev_t EXTMEM;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EXTMEM_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/gdma_reg.h b/components/soc/esp32s3/register/soc/gdma_reg.h
similarity index 99%
rename from components/soc/esp32s3/include/soc/gdma_reg.h
rename to components/soc/esp32s3/register/soc/gdma_reg.h
index 53e76bdc6ff..7c37c513ef9 100644
--- a/components/soc/esp32s3/include/soc/gdma_reg.h
+++ b/components/soc/esp32s3/register/soc/gdma_reg.h
@@ -7,7 +7,7 @@
 #define _SOC_GDMA_REG_H_
 
 
-#include "soc.h"
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32s3/include/soc/gdma_struct.h b/components/soc/esp32s3/register/soc/gdma_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/gdma_struct.h
rename to components/soc/esp32s3/register/soc/gdma_struct.h
diff --git a/components/soc/esp32s3/register/soc/gpio_reg.h b/components/soc/esp32s3/register/soc/gpio_reg.h
new file mode 100644
index 00000000000..8a109f6dd20
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/gpio_reg.h
@@ -0,0 +1,9216 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_GPIO_REG_H_
+#define _SOC_GPIO_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "soc/soc.h"
+
+#define GPIO_PIN_CONFIG_MSB                    12
+#define GPIO_PIN_CONFIG_LSB                     11
+#define GPIO_PIN_CONFIG_MASK                   0x00001800
+#define GPIO_PIN_CONFIG_GET(x)                 (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_CONFIG_SET(x)                  (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
+
+#define GPIO_WAKEUP_ENABLE                     1
+#define GPIO_WAKEUP_DISABLE                    (~GPIO_WAKEUP_ENABLE)
+#define GPIO_PIN_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
+
+#define GPIO_PIN_INT_TYPE_MASK                 0x380
+#define GPIO_PIN_INT_TYPE_MSB                  9
+#define GPIO_PIN_INT_TYPE_LSB                  7
+#define GPIO_PIN_INT_TYPE_GET(x)               (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_INT_TYPE_SET(x)               (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
+
+#define GPIO_PAD_DRIVER_ENABLE                 1
+#define GPIO_PAD_DRIVER_DISABLE                        (~GPIO_PAD_DRIVER_ENABLE)
+#define GPIO_PIN_PAD_DRIVER_MSB                        2
+#define GPIO_PIN_PAD_DRIVER_LSB                        2
+#define GPIO_PIN_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
+#define GPIO_PIN_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
+
+#define GPIO_BT_SELECT_REG          (DR_REG_GPIO_BASE + 0x0)
+/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_BT_SEL    0xFFFFFFFF
+#define GPIO_BT_SEL_M  ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
+#define GPIO_BT_SEL_V  0xFFFFFFFF
+#define GPIO_BT_SEL_S  0
+
+#define GPIO_OUT_REG          (DR_REG_GPIO_BASE + 0x4)
+/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_OUT_DATA    0xFFFFFFFF
+#define GPIO_OUT_DATA_M  ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
+#define GPIO_OUT_DATA_V  0xFFFFFFFF
+#define GPIO_OUT_DATA_S  0
+
+#define GPIO_OUT_W1TS_REG          (DR_REG_GPIO_BASE + 0x8)
+/* GPIO_OUT_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_OUT_W1TS    0xFFFFFFFF
+#define GPIO_OUT_W1TS_M  ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S))
+#define GPIO_OUT_W1TS_V  0xFFFFFFFF
+#define GPIO_OUT_W1TS_S  0
+
+#define GPIO_OUT_W1TC_REG          (DR_REG_GPIO_BASE + 0xC)
+/* GPIO_OUT_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_OUT_W1TC    0xFFFFFFFF
+#define GPIO_OUT_W1TC_M  ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S))
+#define GPIO_OUT_W1TC_V  0xFFFFFFFF
+#define GPIO_OUT_W1TC_S  0
+
+#define GPIO_OUT1_REG          (DR_REG_GPIO_BASE + 0x10)
+/* GPIO_OUT1_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_OUT1_DATA    0x003FFFFF
+#define GPIO_OUT1_DATA_M  ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S))
+#define GPIO_OUT1_DATA_V  0x3FFFFF
+#define GPIO_OUT1_DATA_S  0
+
+#define GPIO_OUT1_W1TS_REG          (DR_REG_GPIO_BASE + 0x14)
+/* GPIO_OUT1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_OUT1_W1TS    0x003FFFFF
+#define GPIO_OUT1_W1TS_M  ((GPIO_OUT1_W1TS_V)<<(GPIO_OUT1_W1TS_S))
+#define GPIO_OUT1_W1TS_V  0x3FFFFF
+#define GPIO_OUT1_W1TS_S  0
+
+#define GPIO_OUT1_W1TC_REG          (DR_REG_GPIO_BASE + 0x18)
+/* GPIO_OUT1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_OUT1_W1TC    0x003FFFFF
+#define GPIO_OUT1_W1TC_M  ((GPIO_OUT1_W1TC_V)<<(GPIO_OUT1_W1TC_S))
+#define GPIO_OUT1_W1TC_V  0x3FFFFF
+#define GPIO_OUT1_W1TC_S  0
+
+#define GPIO_SDIO_SELECT_REG          (DR_REG_GPIO_BASE + 0x1C)
+/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SDIO_SEL    0x000000FF
+#define GPIO_SDIO_SEL_M  ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
+#define GPIO_SDIO_SEL_V  0xFF
+#define GPIO_SDIO_SEL_S  0
+
+#define GPIO_ENABLE_REG          (DR_REG_GPIO_BASE + 0x20)
+/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_ENABLE_DATA    0xFFFFFFFF
+#define GPIO_ENABLE_DATA_M  ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
+#define GPIO_ENABLE_DATA_V  0xFFFFFFFF
+#define GPIO_ENABLE_DATA_S  0
+
+#define GPIO_ENABLE_W1TS_REG          (DR_REG_GPIO_BASE + 0x24)
+/* GPIO_ENABLE_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_ENABLE_W1TS    0xFFFFFFFF
+#define GPIO_ENABLE_W1TS_M  ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S))
+#define GPIO_ENABLE_W1TS_V  0xFFFFFFFF
+#define GPIO_ENABLE_W1TS_S  0
+
+#define GPIO_ENABLE_W1TC_REG          (DR_REG_GPIO_BASE + 0x28)
+/* GPIO_ENABLE_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_ENABLE_W1TC    0xFFFFFFFF
+#define GPIO_ENABLE_W1TC_M  ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S))
+#define GPIO_ENABLE_W1TC_V  0xFFFFFFFF
+#define GPIO_ENABLE_W1TC_S  0
+
+#define GPIO_ENABLE1_REG          (DR_REG_GPIO_BASE + 0x2C)
+/* GPIO_ENABLE_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_ENABLE1_DATA    0x003FFFFF
+#define GPIO_ENABLE1_DATA_M  ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S))
+#define GPIO_ENABLE1_DATA_V  0x3FFFFF
+#define GPIO_ENABLE1_DATA_S  0
+
+#define GPIO_ENABLE1_W1TS_REG          (DR_REG_GPIO_BASE + 0x30)
+/* GPIO_ENABLE1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_ENABLE1_W1TS    0x003FFFFF
+#define GPIO_ENABLE1_W1TS_M  ((GPIO_ENABLE1_W1TS_V)<<(GPIO_ENABLE1_W1TS_S))
+#define GPIO_ENABLE1_W1TS_V  0x3FFFFF
+#define GPIO_ENABLE1_W1TS_S  0
+
+#define GPIO_ENABLE1_W1TC_REG          (DR_REG_GPIO_BASE + 0x34)
+/* GPIO_ENABLE1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_ENABLE1_W1TC    0x003FFFFF
+#define GPIO_ENABLE1_W1TC_M  ((GPIO_ENABLE1_W1TC_V)<<(GPIO_ENABLE1_W1TC_S))
+#define GPIO_ENABLE1_W1TC_V  0x3FFFFF
+#define GPIO_ENABLE1_W1TC_S  0
+
+#define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x38)
+/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
+/*description: .*/
+#define GPIO_STRAPPING    0x0000FFFF
+#define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
+#define GPIO_STRAPPING_V  0xFFFF
+#define GPIO_STRAPPING_S  0
+
+#define GPIO_IN_REG          (DR_REG_GPIO_BASE + 0x3C)
+/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default:  ; */
+/*description: .*/
+#define GPIO_IN_DATA    0xFFFFFFFF
+#define GPIO_IN_DATA_M  ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
+#define GPIO_IN_DATA_V  0xFFFFFFFF
+#define GPIO_IN_DATA_S  0
+
+#define GPIO_IN1_REG          (DR_REG_GPIO_BASE + 0x40)
+/* GPIO_IN_DATA : RO ;bitpos:[21:0] ;default:  ; */
+/*description: .*/
+#define GPIO_IN1_DATA    0x003FFFFF
+#define GPIO_IN1_DATA_M  ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S))
+#define GPIO_IN1_DATA_V  0x3FFFFF
+#define GPIO_IN1_DATA_S  0
+
+#define GPIO_STATUS_REG          (DR_REG_GPIO_BASE + 0x44)
+/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_STATUS_INT    0xFFFFFFFF
+#define GPIO_STATUS_INT_M  ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
+#define GPIO_STATUS_INT_V  0xFFFFFFFF
+#define GPIO_STATUS_INT_S  0
+
+#define GPIO_STATUS_W1TS_REG          (DR_REG_GPIO_BASE + 0x48)
+/* GPIO_STATUS_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_STATUS_W1TS    0xFFFFFFFF
+#define GPIO_STATUS_W1TS_M  ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S))
+#define GPIO_STATUS_W1TS_V  0xFFFFFFFF
+#define GPIO_STATUS_W1TS_S  0
+
+#define GPIO_STATUS_W1TC_REG          (DR_REG_GPIO_BASE + 0x4C)
+/* GPIO_STATUS_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_STATUS_W1TC    0xFFFFFFFF
+#define GPIO_STATUS_W1TC_M  ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S))
+#define GPIO_STATUS_W1TC_V  0xFFFFFFFF
+#define GPIO_STATUS_W1TC_S  0
+
+#define GPIO_STATUS1_REG          (DR_REG_GPIO_BASE + 0x50)
+/* GPIO_STATUS_INT : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_STATUS1_INT    0x003FFFFF
+#define GPIO_STATUS1_INT_M  ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S))
+#define GPIO_STATUS1_INT_V  0x3FFFFF
+#define GPIO_STATUS1_INT_S  0
+
+#define GPIO_STATUS1_W1TS_REG          (DR_REG_GPIO_BASE + 0x54)
+/* GPIO_STATUS1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_STATUS1_W1TS    0x003FFFFF
+#define GPIO_STATUS1_W1TS_M  ((GPIO_STATUS1_W1TS_V)<<(GPIO_STATUS1_W1TS_S))
+#define GPIO_STATUS1_W1TS_V  0x3FFFFF
+#define GPIO_STATUS1_W1TS_S  0
+
+#define GPIO_STATUS1_W1TC_REG          (DR_REG_GPIO_BASE + 0x58)
+/* GPIO_STATUS1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: .*/
+#define GPIO_STATUS1_W1TC    0x003FFFFF
+#define GPIO_STATUS1_W1TC_M  ((GPIO_STATUS1_W1TC_V)<<(GPIO_STATUS1_W1TC_S))
+#define GPIO_STATUS1_W1TC_V  0x3FFFFF
+#define GPIO_STATUS1_W1TC_S  0
+
+#define GPIO_PCPU_INT_REG          (DR_REG_GPIO_BASE + 0x5C)
+/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_PROCPU_INT    0xFFFFFFFF
+#define GPIO_PROCPU_INT_M  ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
+#define GPIO_PROCPU_INT_V  0xFFFFFFFF
+#define GPIO_PROCPU_INT_S  0
+
+#define GPIO_PCPU_NMI_INT_REG          (DR_REG_GPIO_BASE + 0x60)
+/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_PROCPU_NMI_INT    0xFFFFFFFF
+#define GPIO_PROCPU_NMI_INT_M  ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
+#define GPIO_PROCPU_NMI_INT_V  0xFFFFFFFF
+#define GPIO_PROCPU_NMI_INT_S  0
+
+#define GPIO_CPUSDIO_INT_REG          (DR_REG_GPIO_BASE + 0x64)
+/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_SDIO_INT    0xFFFFFFFF
+#define GPIO_SDIO_INT_M  ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
+#define GPIO_SDIO_INT_V  0xFFFFFFFF
+#define GPIO_SDIO_INT_S  0
+
+#define GPIO_PCPU_INT1_REG          (DR_REG_GPIO_BASE + 0x68)
+/* GPIO_PROCPU_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_PROCPU_INT_H  0x003FFFFF
+#define GPIO_PROCPU_INT_H_M  ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S))
+#define GPIO_PROCPU_INT_H_V  0x3FFFFF
+#define GPIO_PROCPU_INT_H_S  0
+
+#define GPIO_PCPU_NMI_INT1_REG          (DR_REG_GPIO_BASE + 0x6C)
+/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_PROCPU_NMI_INT_H  0x003FFFFF
+#define GPIO_PROCPU_NMI_INT_H_M  ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S))
+#define GPIO_PROCPU_NMI_INT_H_V  0x3FFFFF
+#define GPIO_PROCPU_NMI_INT_H_S  0
+
+#define GPIO_CPUSDIO_INT1_REG          (DR_REG_GPIO_BASE + 0x70)
+/* GPIO_SDIO_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_SDIO_INT_H  0x003FFFFF
+#define GPIO_SDIO_INT_H_M  ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S))
+#define GPIO_SDIO_INT_H_V  0x3FFFFF
+#define GPIO_SDIO_INT_H_S  0
+
+#define GPIO_PIN0_REG          (DR_REG_GPIO_BASE + 0x74)
+/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN0_INT_ENA    0x0000001F
+#define GPIO_PIN0_INT_ENA_M  ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
+#define GPIO_PIN0_INT_ENA_V  0x1F
+#define GPIO_PIN0_INT_ENA_S  13
+/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN0_CONFIG    0x00000003
+#define GPIO_PIN0_CONFIG_M  ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
+#define GPIO_PIN0_CONFIG_V  0x3
+#define GPIO_PIN0_CONFIG_S  11
+/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN0_INT_TYPE    0x00000007
+#define GPIO_PIN0_INT_TYPE_M  ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
+#define GPIO_PIN0_INT_TYPE_V  0x7
+#define GPIO_PIN0_INT_TYPE_S  7
+/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN0_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN0_SYNC1_BYPASS_M  ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_V  0x1
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN0_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN0_SYNC2_BYPASS_M  ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S))
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN1_REG          (DR_REG_GPIO_BASE + 0x78)
+/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN1_INT_ENA    0x0000001F
+#define GPIO_PIN1_INT_ENA_M  ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
+#define GPIO_PIN1_INT_ENA_V  0x1F
+#define GPIO_PIN1_INT_ENA_S  13
+/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN1_CONFIG    0x00000003
+#define GPIO_PIN1_CONFIG_M  ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
+#define GPIO_PIN1_CONFIG_V  0x3
+#define GPIO_PIN1_CONFIG_S  11
+/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN1_INT_TYPE    0x00000007
+#define GPIO_PIN1_INT_TYPE_M  ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
+#define GPIO_PIN1_INT_TYPE_V  0x7
+#define GPIO_PIN1_INT_TYPE_S  7
+/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN1_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN1_SYNC1_BYPASS_M  ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S))
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_V  0x1
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN1_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN1_SYNC2_BYPASS_M  ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S))
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN2_REG          (DR_REG_GPIO_BASE + 0x7C)
+/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN2_INT_ENA    0x0000001F
+#define GPIO_PIN2_INT_ENA_M  ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
+#define GPIO_PIN2_INT_ENA_V  0x1F
+#define GPIO_PIN2_INT_ENA_S  13
+/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN2_CONFIG    0x00000003
+#define GPIO_PIN2_CONFIG_M  ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
+#define GPIO_PIN2_CONFIG_V  0x3
+#define GPIO_PIN2_CONFIG_S  11
+/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN2_INT_TYPE    0x00000007
+#define GPIO_PIN2_INT_TYPE_M  ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
+#define GPIO_PIN2_INT_TYPE_V  0x7
+#define GPIO_PIN2_INT_TYPE_S  7
+/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN2_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN2_SYNC1_BYPASS_M  ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S))
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_V  0x1
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN2_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN2_SYNC2_BYPASS_M  ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S))
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN3_REG          (DR_REG_GPIO_BASE + 0x80)
+/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN3_INT_ENA    0x0000001F
+#define GPIO_PIN3_INT_ENA_M  ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
+#define GPIO_PIN3_INT_ENA_V  0x1F
+#define GPIO_PIN3_INT_ENA_S  13
+/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN3_CONFIG    0x00000003
+#define GPIO_PIN3_CONFIG_M  ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
+#define GPIO_PIN3_CONFIG_V  0x3
+#define GPIO_PIN3_CONFIG_S  11
+/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN3_INT_TYPE    0x00000007
+#define GPIO_PIN3_INT_TYPE_M  ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
+#define GPIO_PIN3_INT_TYPE_V  0x7
+#define GPIO_PIN3_INT_TYPE_S  7
+/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN3_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN3_SYNC1_BYPASS_M  ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S))
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_V  0x1
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN3_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN3_SYNC2_BYPASS_M  ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S))
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN4_REG          (DR_REG_GPIO_BASE + 0x84)
+/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN4_INT_ENA    0x0000001F
+#define GPIO_PIN4_INT_ENA_M  ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
+#define GPIO_PIN4_INT_ENA_V  0x1F
+#define GPIO_PIN4_INT_ENA_S  13
+/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN4_CONFIG    0x00000003
+#define GPIO_PIN4_CONFIG_M  ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
+#define GPIO_PIN4_CONFIG_V  0x3
+#define GPIO_PIN4_CONFIG_S  11
+/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN4_INT_TYPE    0x00000007
+#define GPIO_PIN4_INT_TYPE_M  ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
+#define GPIO_PIN4_INT_TYPE_V  0x7
+#define GPIO_PIN4_INT_TYPE_S  7
+/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN4_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN4_SYNC1_BYPASS_M  ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S))
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_V  0x1
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN4_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN4_SYNC2_BYPASS_M  ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S))
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN5_REG          (DR_REG_GPIO_BASE + 0x88)
+/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN5_INT_ENA    0x0000001F
+#define GPIO_PIN5_INT_ENA_M  ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
+#define GPIO_PIN5_INT_ENA_V  0x1F
+#define GPIO_PIN5_INT_ENA_S  13
+/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN5_CONFIG    0x00000003
+#define GPIO_PIN5_CONFIG_M  ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
+#define GPIO_PIN5_CONFIG_V  0x3
+#define GPIO_PIN5_CONFIG_S  11
+/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN5_INT_TYPE    0x00000007
+#define GPIO_PIN5_INT_TYPE_M  ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
+#define GPIO_PIN5_INT_TYPE_V  0x7
+#define GPIO_PIN5_INT_TYPE_S  7
+/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN5_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN5_SYNC1_BYPASS_M  ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S))
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_V  0x1
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN5_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN5_SYNC2_BYPASS_M  ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S))
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN6_REG          (DR_REG_GPIO_BASE + 0x8C)
+/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN6_INT_ENA    0x0000001F
+#define GPIO_PIN6_INT_ENA_M  ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
+#define GPIO_PIN6_INT_ENA_V  0x1F
+#define GPIO_PIN6_INT_ENA_S  13
+/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN6_CONFIG    0x00000003
+#define GPIO_PIN6_CONFIG_M  ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
+#define GPIO_PIN6_CONFIG_V  0x3
+#define GPIO_PIN6_CONFIG_S  11
+/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN6_INT_TYPE    0x00000007
+#define GPIO_PIN6_INT_TYPE_M  ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
+#define GPIO_PIN6_INT_TYPE_V  0x7
+#define GPIO_PIN6_INT_TYPE_S  7
+/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN6_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN6_SYNC1_BYPASS_M  ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S))
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_V  0x1
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN6_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN6_SYNC2_BYPASS_M  ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S))
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN7_REG          (DR_REG_GPIO_BASE + 0x90)
+/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN7_INT_ENA    0x0000001F
+#define GPIO_PIN7_INT_ENA_M  ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
+#define GPIO_PIN7_INT_ENA_V  0x1F
+#define GPIO_PIN7_INT_ENA_S  13
+/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN7_CONFIG    0x00000003
+#define GPIO_PIN7_CONFIG_M  ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
+#define GPIO_PIN7_CONFIG_V  0x3
+#define GPIO_PIN7_CONFIG_S  11
+/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN7_INT_TYPE    0x00000007
+#define GPIO_PIN7_INT_TYPE_M  ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
+#define GPIO_PIN7_INT_TYPE_V  0x7
+#define GPIO_PIN7_INT_TYPE_S  7
+/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN7_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN7_SYNC1_BYPASS_M  ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S))
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_V  0x1
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN7_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN7_SYNC2_BYPASS_M  ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S))
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN8_REG          (DR_REG_GPIO_BASE + 0x94)
+/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN8_INT_ENA    0x0000001F
+#define GPIO_PIN8_INT_ENA_M  ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
+#define GPIO_PIN8_INT_ENA_V  0x1F
+#define GPIO_PIN8_INT_ENA_S  13
+/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN8_CONFIG    0x00000003
+#define GPIO_PIN8_CONFIG_M  ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
+#define GPIO_PIN8_CONFIG_V  0x3
+#define GPIO_PIN8_CONFIG_S  11
+/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN8_INT_TYPE    0x00000007
+#define GPIO_PIN8_INT_TYPE_M  ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
+#define GPIO_PIN8_INT_TYPE_V  0x7
+#define GPIO_PIN8_INT_TYPE_S  7
+/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN8_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN8_SYNC1_BYPASS_M  ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S))
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_V  0x1
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN8_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN8_SYNC2_BYPASS_M  ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S))
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN9_REG          (DR_REG_GPIO_BASE + 0x98)
+/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN9_INT_ENA    0x0000001F
+#define GPIO_PIN9_INT_ENA_M  ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
+#define GPIO_PIN9_INT_ENA_V  0x1F
+#define GPIO_PIN9_INT_ENA_S  13
+/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN9_CONFIG    0x00000003
+#define GPIO_PIN9_CONFIG_M  ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
+#define GPIO_PIN9_CONFIG_V  0x3
+#define GPIO_PIN9_CONFIG_S  11
+/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN9_INT_TYPE    0x00000007
+#define GPIO_PIN9_INT_TYPE_M  ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
+#define GPIO_PIN9_INT_TYPE_V  0x7
+#define GPIO_PIN9_INT_TYPE_S  7
+/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN9_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN9_SYNC1_BYPASS_M  ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S))
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_V  0x1
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN9_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN9_SYNC2_BYPASS_M  ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S))
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN10_REG          (DR_REG_GPIO_BASE + 0x9C)
+/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN10_INT_ENA    0x0000001F
+#define GPIO_PIN10_INT_ENA_M  ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
+#define GPIO_PIN10_INT_ENA_V  0x1F
+#define GPIO_PIN10_INT_ENA_S  13
+/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN10_CONFIG    0x00000003
+#define GPIO_PIN10_CONFIG_M  ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
+#define GPIO_PIN10_CONFIG_V  0x3
+#define GPIO_PIN10_CONFIG_S  11
+/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN10_INT_TYPE    0x00000007
+#define GPIO_PIN10_INT_TYPE_M  ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
+#define GPIO_PIN10_INT_TYPE_V  0x7
+#define GPIO_PIN10_INT_TYPE_S  7
+/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN10_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN10_SYNC1_BYPASS_M  ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S))
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_V  0x1
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN10_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN10_SYNC2_BYPASS_M  ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S))
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN11_REG          (DR_REG_GPIO_BASE + 0xA0)
+/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN11_INT_ENA    0x0000001F
+#define GPIO_PIN11_INT_ENA_M  ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
+#define GPIO_PIN11_INT_ENA_V  0x1F
+#define GPIO_PIN11_INT_ENA_S  13
+/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN11_CONFIG    0x00000003
+#define GPIO_PIN11_CONFIG_M  ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
+#define GPIO_PIN11_CONFIG_V  0x3
+#define GPIO_PIN11_CONFIG_S  11
+/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN11_INT_TYPE    0x00000007
+#define GPIO_PIN11_INT_TYPE_M  ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
+#define GPIO_PIN11_INT_TYPE_V  0x7
+#define GPIO_PIN11_INT_TYPE_S  7
+/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN11_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN11_SYNC1_BYPASS_M  ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S))
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_V  0x1
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN11_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN11_SYNC2_BYPASS_M  ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S))
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN12_REG          (DR_REG_GPIO_BASE + 0xA4)
+/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN12_INT_ENA    0x0000001F
+#define GPIO_PIN12_INT_ENA_M  ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
+#define GPIO_PIN12_INT_ENA_V  0x1F
+#define GPIO_PIN12_INT_ENA_S  13
+/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN12_CONFIG    0x00000003
+#define GPIO_PIN12_CONFIG_M  ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
+#define GPIO_PIN12_CONFIG_V  0x3
+#define GPIO_PIN12_CONFIG_S  11
+/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN12_INT_TYPE    0x00000007
+#define GPIO_PIN12_INT_TYPE_M  ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
+#define GPIO_PIN12_INT_TYPE_V  0x7
+#define GPIO_PIN12_INT_TYPE_S  7
+/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN12_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN12_SYNC1_BYPASS_M  ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S))
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_V  0x1
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN12_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN12_SYNC2_BYPASS_M  ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S))
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN13_REG          (DR_REG_GPIO_BASE + 0xA8)
+/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN13_INT_ENA    0x0000001F
+#define GPIO_PIN13_INT_ENA_M  ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
+#define GPIO_PIN13_INT_ENA_V  0x1F
+#define GPIO_PIN13_INT_ENA_S  13
+/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN13_CONFIG    0x00000003
+#define GPIO_PIN13_CONFIG_M  ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
+#define GPIO_PIN13_CONFIG_V  0x3
+#define GPIO_PIN13_CONFIG_S  11
+/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN13_INT_TYPE    0x00000007
+#define GPIO_PIN13_INT_TYPE_M  ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
+#define GPIO_PIN13_INT_TYPE_V  0x7
+#define GPIO_PIN13_INT_TYPE_S  7
+/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN13_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN13_SYNC1_BYPASS_M  ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S))
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_V  0x1
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN13_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN13_SYNC2_BYPASS_M  ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S))
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN14_REG          (DR_REG_GPIO_BASE + 0xAC)
+/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN14_INT_ENA    0x0000001F
+#define GPIO_PIN14_INT_ENA_M  ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
+#define GPIO_PIN14_INT_ENA_V  0x1F
+#define GPIO_PIN14_INT_ENA_S  13
+/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN14_CONFIG    0x00000003
+#define GPIO_PIN14_CONFIG_M  ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
+#define GPIO_PIN14_CONFIG_V  0x3
+#define GPIO_PIN14_CONFIG_S  11
+/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN14_INT_TYPE    0x00000007
+#define GPIO_PIN14_INT_TYPE_M  ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
+#define GPIO_PIN14_INT_TYPE_V  0x7
+#define GPIO_PIN14_INT_TYPE_S  7
+/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN14_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN14_SYNC1_BYPASS_M  ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S))
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_V  0x1
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN14_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN14_SYNC2_BYPASS_M  ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S))
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN15_REG          (DR_REG_GPIO_BASE + 0xB0)
+/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN15_INT_ENA    0x0000001F
+#define GPIO_PIN15_INT_ENA_M  ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
+#define GPIO_PIN15_INT_ENA_V  0x1F
+#define GPIO_PIN15_INT_ENA_S  13
+/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN15_CONFIG    0x00000003
+#define GPIO_PIN15_CONFIG_M  ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
+#define GPIO_PIN15_CONFIG_V  0x3
+#define GPIO_PIN15_CONFIG_S  11
+/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN15_INT_TYPE    0x00000007
+#define GPIO_PIN15_INT_TYPE_M  ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
+#define GPIO_PIN15_INT_TYPE_V  0x7
+#define GPIO_PIN15_INT_TYPE_S  7
+/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN15_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN15_SYNC1_BYPASS_M  ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S))
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_V  0x1
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN15_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN15_SYNC2_BYPASS_M  ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S))
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN16_REG          (DR_REG_GPIO_BASE + 0xB4)
+/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN16_INT_ENA    0x0000001F
+#define GPIO_PIN16_INT_ENA_M  ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
+#define GPIO_PIN16_INT_ENA_V  0x1F
+#define GPIO_PIN16_INT_ENA_S  13
+/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN16_CONFIG    0x00000003
+#define GPIO_PIN16_CONFIG_M  ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
+#define GPIO_PIN16_CONFIG_V  0x3
+#define GPIO_PIN16_CONFIG_S  11
+/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN16_INT_TYPE    0x00000007
+#define GPIO_PIN16_INT_TYPE_M  ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
+#define GPIO_PIN16_INT_TYPE_V  0x7
+#define GPIO_PIN16_INT_TYPE_S  7
+/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN16_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN16_SYNC1_BYPASS_M  ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S))
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_V  0x1
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN16_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN16_SYNC2_BYPASS_M  ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S))
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN17_REG          (DR_REG_GPIO_BASE + 0xB8)
+/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN17_INT_ENA    0x0000001F
+#define GPIO_PIN17_INT_ENA_M  ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
+#define GPIO_PIN17_INT_ENA_V  0x1F
+#define GPIO_PIN17_INT_ENA_S  13
+/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN17_CONFIG    0x00000003
+#define GPIO_PIN17_CONFIG_M  ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
+#define GPIO_PIN17_CONFIG_V  0x3
+#define GPIO_PIN17_CONFIG_S  11
+/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN17_INT_TYPE    0x00000007
+#define GPIO_PIN17_INT_TYPE_M  ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
+#define GPIO_PIN17_INT_TYPE_V  0x7
+#define GPIO_PIN17_INT_TYPE_S  7
+/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN17_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN17_SYNC1_BYPASS_M  ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S))
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_V  0x1
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN17_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN17_SYNC2_BYPASS_M  ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S))
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN18_REG          (DR_REG_GPIO_BASE + 0xBC)
+/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN18_INT_ENA    0x0000001F
+#define GPIO_PIN18_INT_ENA_M  ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
+#define GPIO_PIN18_INT_ENA_V  0x1F
+#define GPIO_PIN18_INT_ENA_S  13
+/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN18_CONFIG    0x00000003
+#define GPIO_PIN18_CONFIG_M  ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
+#define GPIO_PIN18_CONFIG_V  0x3
+#define GPIO_PIN18_CONFIG_S  11
+/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN18_INT_TYPE    0x00000007
+#define GPIO_PIN18_INT_TYPE_M  ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
+#define GPIO_PIN18_INT_TYPE_V  0x7
+#define GPIO_PIN18_INT_TYPE_S  7
+/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN18_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN18_SYNC1_BYPASS_M  ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S))
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_V  0x1
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN18_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN18_SYNC2_BYPASS_M  ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S))
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN19_REG          (DR_REG_GPIO_BASE + 0xC0)
+/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN19_INT_ENA    0x0000001F
+#define GPIO_PIN19_INT_ENA_M  ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
+#define GPIO_PIN19_INT_ENA_V  0x1F
+#define GPIO_PIN19_INT_ENA_S  13
+/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN19_CONFIG    0x00000003
+#define GPIO_PIN19_CONFIG_M  ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
+#define GPIO_PIN19_CONFIG_V  0x3
+#define GPIO_PIN19_CONFIG_S  11
+/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN19_INT_TYPE    0x00000007
+#define GPIO_PIN19_INT_TYPE_M  ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
+#define GPIO_PIN19_INT_TYPE_V  0x7
+#define GPIO_PIN19_INT_TYPE_S  7
+/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN19_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN19_SYNC1_BYPASS_M  ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S))
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_V  0x1
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN19_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN19_SYNC2_BYPASS_M  ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S))
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN20_REG          (DR_REG_GPIO_BASE + 0xC4)
+/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN20_INT_ENA    0x0000001F
+#define GPIO_PIN20_INT_ENA_M  ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
+#define GPIO_PIN20_INT_ENA_V  0x1F
+#define GPIO_PIN20_INT_ENA_S  13
+/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN20_CONFIG    0x00000003
+#define GPIO_PIN20_CONFIG_M  ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
+#define GPIO_PIN20_CONFIG_V  0x3
+#define GPIO_PIN20_CONFIG_S  11
+/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN20_INT_TYPE    0x00000007
+#define GPIO_PIN20_INT_TYPE_M  ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
+#define GPIO_PIN20_INT_TYPE_V  0x7
+#define GPIO_PIN20_INT_TYPE_S  7
+/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN20_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN20_SYNC1_BYPASS_M  ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S))
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_V  0x1
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN20_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN20_SYNC2_BYPASS_M  ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S))
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN21_REG          (DR_REG_GPIO_BASE + 0xC8)
+/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN21_INT_ENA    0x0000001F
+#define GPIO_PIN21_INT_ENA_M  ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
+#define GPIO_PIN21_INT_ENA_V  0x1F
+#define GPIO_PIN21_INT_ENA_S  13
+/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN21_CONFIG    0x00000003
+#define GPIO_PIN21_CONFIG_M  ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
+#define GPIO_PIN21_CONFIG_V  0x3
+#define GPIO_PIN21_CONFIG_S  11
+/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN21_INT_TYPE    0x00000007
+#define GPIO_PIN21_INT_TYPE_M  ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
+#define GPIO_PIN21_INT_TYPE_V  0x7
+#define GPIO_PIN21_INT_TYPE_S  7
+/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN21_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN21_SYNC1_BYPASS_M  ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S))
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_V  0x1
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN21_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN21_SYNC2_BYPASS_M  ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S))
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN22_REG          (DR_REG_GPIO_BASE + 0xCC)
+/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN22_INT_ENA    0x0000001F
+#define GPIO_PIN22_INT_ENA_M  ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
+#define GPIO_PIN22_INT_ENA_V  0x1F
+#define GPIO_PIN22_INT_ENA_S  13
+/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN22_CONFIG    0x00000003
+#define GPIO_PIN22_CONFIG_M  ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
+#define GPIO_PIN22_CONFIG_V  0x3
+#define GPIO_PIN22_CONFIG_S  11
+/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN22_INT_TYPE    0x00000007
+#define GPIO_PIN22_INT_TYPE_M  ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
+#define GPIO_PIN22_INT_TYPE_V  0x7
+#define GPIO_PIN22_INT_TYPE_S  7
+/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN22_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN22_SYNC1_BYPASS_M  ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S))
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_V  0x1
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN22_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN22_SYNC2_BYPASS_M  ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S))
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN23_REG          (DR_REG_GPIO_BASE + 0xD0)
+/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN23_INT_ENA    0x0000001F
+#define GPIO_PIN23_INT_ENA_M  ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
+#define GPIO_PIN23_INT_ENA_V  0x1F
+#define GPIO_PIN23_INT_ENA_S  13
+/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN23_CONFIG    0x00000003
+#define GPIO_PIN23_CONFIG_M  ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
+#define GPIO_PIN23_CONFIG_V  0x3
+#define GPIO_PIN23_CONFIG_S  11
+/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN23_INT_TYPE    0x00000007
+#define GPIO_PIN23_INT_TYPE_M  ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
+#define GPIO_PIN23_INT_TYPE_V  0x7
+#define GPIO_PIN23_INT_TYPE_S  7
+/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN23_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN23_SYNC1_BYPASS_M  ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S))
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_V  0x1
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN23_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN23_SYNC2_BYPASS_M  ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S))
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN24_REG          (DR_REG_GPIO_BASE + 0xD4)
+/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN24_INT_ENA    0x0000001F
+#define GPIO_PIN24_INT_ENA_M  ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
+#define GPIO_PIN24_INT_ENA_V  0x1F
+#define GPIO_PIN24_INT_ENA_S  13
+/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN24_CONFIG    0x00000003
+#define GPIO_PIN24_CONFIG_M  ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
+#define GPIO_PIN24_CONFIG_V  0x3
+#define GPIO_PIN24_CONFIG_S  11
+/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN24_INT_TYPE    0x00000007
+#define GPIO_PIN24_INT_TYPE_M  ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
+#define GPIO_PIN24_INT_TYPE_V  0x7
+#define GPIO_PIN24_INT_TYPE_S  7
+/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN24_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN24_SYNC1_BYPASS_M  ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S))
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_V  0x1
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN24_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN24_SYNC2_BYPASS_M  ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S))
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN25_REG          (DR_REG_GPIO_BASE + 0xD8)
+/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN25_INT_ENA    0x0000001F
+#define GPIO_PIN25_INT_ENA_M  ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
+#define GPIO_PIN25_INT_ENA_V  0x1F
+#define GPIO_PIN25_INT_ENA_S  13
+/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN25_CONFIG    0x00000003
+#define GPIO_PIN25_CONFIG_M  ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
+#define GPIO_PIN25_CONFIG_V  0x3
+#define GPIO_PIN25_CONFIG_S  11
+/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN25_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN25_WAKEUP_ENABLE_S  10
+/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN25_INT_TYPE    0x00000007
+#define GPIO_PIN25_INT_TYPE_M  ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
+#define GPIO_PIN25_INT_TYPE_V  0x7
+#define GPIO_PIN25_INT_TYPE_S  7
+/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN25_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN25_SYNC1_BYPASS_M  ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S))
+#define GPIO_PIN25_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN25_SYNC1_BYPASS_S  3
+/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN25_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_V  0x1
+#define GPIO_PIN25_PAD_DRIVER_S  2
+/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN25_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN25_SYNC2_BYPASS_M  ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S))
+#define GPIO_PIN25_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN25_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN26_REG          (DR_REG_GPIO_BASE + 0xDC)
+/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN26_INT_ENA    0x0000001F
+#define GPIO_PIN26_INT_ENA_M  ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S))
+#define GPIO_PIN26_INT_ENA_V  0x1F
+#define GPIO_PIN26_INT_ENA_S  13
+/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN26_CONFIG    0x00000003
+#define GPIO_PIN26_CONFIG_M  ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S))
+#define GPIO_PIN26_CONFIG_V  0x3
+#define GPIO_PIN26_CONFIG_S  11
+/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN26_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN26_WAKEUP_ENABLE_S  10
+/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN26_INT_TYPE    0x00000007
+#define GPIO_PIN26_INT_TYPE_M  ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S))
+#define GPIO_PIN26_INT_TYPE_V  0x7
+#define GPIO_PIN26_INT_TYPE_S  7
+/* GPIO_PIN26_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN26_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN26_SYNC1_BYPASS_M  ((GPIO_PIN26_SYNC1_BYPASS_V)<<(GPIO_PIN26_SYNC1_BYPASS_S))
+#define GPIO_PIN26_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN26_SYNC1_BYPASS_S  3
+/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN26_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_V  0x1
+#define GPIO_PIN26_PAD_DRIVER_S  2
+/* GPIO_PIN26_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN26_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN26_SYNC2_BYPASS_M  ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S))
+#define GPIO_PIN26_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN26_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN27_REG          (DR_REG_GPIO_BASE + 0xE0)
+/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN27_INT_ENA    0x0000001F
+#define GPIO_PIN27_INT_ENA_M  ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S))
+#define GPIO_PIN27_INT_ENA_V  0x1F
+#define GPIO_PIN27_INT_ENA_S  13
+/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN27_CONFIG    0x00000003
+#define GPIO_PIN27_CONFIG_M  ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S))
+#define GPIO_PIN27_CONFIG_V  0x3
+#define GPIO_PIN27_CONFIG_S  11
+/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN27_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN27_WAKEUP_ENABLE_S  10
+/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN27_INT_TYPE    0x00000007
+#define GPIO_PIN27_INT_TYPE_M  ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S))
+#define GPIO_PIN27_INT_TYPE_V  0x7
+#define GPIO_PIN27_INT_TYPE_S  7
+/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN27_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN27_SYNC1_BYPASS_M  ((GPIO_PIN27_SYNC1_BYPASS_V)<<(GPIO_PIN27_SYNC1_BYPASS_S))
+#define GPIO_PIN27_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN27_SYNC1_BYPASS_S  3
+/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN27_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_V  0x1
+#define GPIO_PIN27_PAD_DRIVER_S  2
+/* GPIO_PIN27_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN27_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN27_SYNC2_BYPASS_M  ((GPIO_PIN27_SYNC2_BYPASS_V)<<(GPIO_PIN27_SYNC2_BYPASS_S))
+#define GPIO_PIN27_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN27_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN28_REG          (DR_REG_GPIO_BASE + 0xE4)
+/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN28_INT_ENA    0x0000001F
+#define GPIO_PIN28_INT_ENA_M  ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S))
+#define GPIO_PIN28_INT_ENA_V  0x1F
+#define GPIO_PIN28_INT_ENA_S  13
+/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN28_CONFIG    0x00000003
+#define GPIO_PIN28_CONFIG_M  ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S))
+#define GPIO_PIN28_CONFIG_V  0x3
+#define GPIO_PIN28_CONFIG_S  11
+/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN28_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN28_WAKEUP_ENABLE_S  10
+/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN28_INT_TYPE    0x00000007
+#define GPIO_PIN28_INT_TYPE_M  ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S))
+#define GPIO_PIN28_INT_TYPE_V  0x7
+#define GPIO_PIN28_INT_TYPE_S  7
+/* GPIO_PIN28_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN28_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN28_SYNC1_BYPASS_M  ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S))
+#define GPIO_PIN28_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN28_SYNC1_BYPASS_S  3
+/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN28_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_V  0x1
+#define GPIO_PIN28_PAD_DRIVER_S  2
+/* GPIO_PIN28_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN28_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN28_SYNC2_BYPASS_M  ((GPIO_PIN28_SYNC2_BYPASS_V)<<(GPIO_PIN28_SYNC2_BYPASS_S))
+#define GPIO_PIN28_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN28_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN29_REG          (DR_REG_GPIO_BASE + 0xE8)
+/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN29_INT_ENA    0x0000001F
+#define GPIO_PIN29_INT_ENA_M  ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S))
+#define GPIO_PIN29_INT_ENA_V  0x1F
+#define GPIO_PIN29_INT_ENA_S  13
+/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN29_CONFIG    0x00000003
+#define GPIO_PIN29_CONFIG_M  ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S))
+#define GPIO_PIN29_CONFIG_V  0x3
+#define GPIO_PIN29_CONFIG_S  11
+/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN29_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN29_WAKEUP_ENABLE_S  10
+/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN29_INT_TYPE    0x00000007
+#define GPIO_PIN29_INT_TYPE_M  ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S))
+#define GPIO_PIN29_INT_TYPE_V  0x7
+#define GPIO_PIN29_INT_TYPE_S  7
+/* GPIO_PIN29_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN29_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN29_SYNC1_BYPASS_M  ((GPIO_PIN29_SYNC1_BYPASS_V)<<(GPIO_PIN29_SYNC1_BYPASS_S))
+#define GPIO_PIN29_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN29_SYNC1_BYPASS_S  3
+/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN29_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_V  0x1
+#define GPIO_PIN29_PAD_DRIVER_S  2
+/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN29_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN29_SYNC2_BYPASS_M  ((GPIO_PIN29_SYNC2_BYPASS_V)<<(GPIO_PIN29_SYNC2_BYPASS_S))
+#define GPIO_PIN29_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN29_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN30_REG          (DR_REG_GPIO_BASE + 0xEC)
+/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN30_INT_ENA    0x0000001F
+#define GPIO_PIN30_INT_ENA_M  ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S))
+#define GPIO_PIN30_INT_ENA_V  0x1F
+#define GPIO_PIN30_INT_ENA_S  13
+/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN30_CONFIG    0x00000003
+#define GPIO_PIN30_CONFIG_M  ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S))
+#define GPIO_PIN30_CONFIG_V  0x3
+#define GPIO_PIN30_CONFIG_S  11
+/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN30_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN30_WAKEUP_ENABLE_S  10
+/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN30_INT_TYPE    0x00000007
+#define GPIO_PIN30_INT_TYPE_M  ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S))
+#define GPIO_PIN30_INT_TYPE_V  0x7
+#define GPIO_PIN30_INT_TYPE_S  7
+/* GPIO_PIN30_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN30_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN30_SYNC1_BYPASS_M  ((GPIO_PIN30_SYNC1_BYPASS_V)<<(GPIO_PIN30_SYNC1_BYPASS_S))
+#define GPIO_PIN30_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN30_SYNC1_BYPASS_S  3
+/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN30_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_V  0x1
+#define GPIO_PIN30_PAD_DRIVER_S  2
+/* GPIO_PIN30_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN30_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN30_SYNC2_BYPASS_M  ((GPIO_PIN30_SYNC2_BYPASS_V)<<(GPIO_PIN30_SYNC2_BYPASS_S))
+#define GPIO_PIN30_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN30_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN31_REG          (DR_REG_GPIO_BASE + 0xF0)
+/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN31_INT_ENA    0x0000001F
+#define GPIO_PIN31_INT_ENA_M  ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S))
+#define GPIO_PIN31_INT_ENA_V  0x1F
+#define GPIO_PIN31_INT_ENA_S  13
+/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN31_CONFIG    0x00000003
+#define GPIO_PIN31_CONFIG_M  ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S))
+#define GPIO_PIN31_CONFIG_V  0x3
+#define GPIO_PIN31_CONFIG_S  11
+/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN31_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN31_WAKEUP_ENABLE_S  10
+/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN31_INT_TYPE    0x00000007
+#define GPIO_PIN31_INT_TYPE_M  ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S))
+#define GPIO_PIN31_INT_TYPE_V  0x7
+#define GPIO_PIN31_INT_TYPE_S  7
+/* GPIO_PIN31_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN31_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN31_SYNC1_BYPASS_M  ((GPIO_PIN31_SYNC1_BYPASS_V)<<(GPIO_PIN31_SYNC1_BYPASS_S))
+#define GPIO_PIN31_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN31_SYNC1_BYPASS_S  3
+/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN31_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_V  0x1
+#define GPIO_PIN31_PAD_DRIVER_S  2
+/* GPIO_PIN31_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN31_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN31_SYNC2_BYPASS_M  ((GPIO_PIN31_SYNC2_BYPASS_V)<<(GPIO_PIN31_SYNC2_BYPASS_S))
+#define GPIO_PIN31_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN31_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN32_REG          (DR_REG_GPIO_BASE + 0xF4)
+/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN32_INT_ENA    0x0000001F
+#define GPIO_PIN32_INT_ENA_M  ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S))
+#define GPIO_PIN32_INT_ENA_V  0x1F
+#define GPIO_PIN32_INT_ENA_S  13
+/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN32_CONFIG    0x00000003
+#define GPIO_PIN32_CONFIG_M  ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S))
+#define GPIO_PIN32_CONFIG_V  0x3
+#define GPIO_PIN32_CONFIG_S  11
+/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN32_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN32_WAKEUP_ENABLE_S  10
+/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN32_INT_TYPE    0x00000007
+#define GPIO_PIN32_INT_TYPE_M  ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S))
+#define GPIO_PIN32_INT_TYPE_V  0x7
+#define GPIO_PIN32_INT_TYPE_S  7
+/* GPIO_PIN32_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN32_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN32_SYNC1_BYPASS_M  ((GPIO_PIN32_SYNC1_BYPASS_V)<<(GPIO_PIN32_SYNC1_BYPASS_S))
+#define GPIO_PIN32_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN32_SYNC1_BYPASS_S  3
+/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN32_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_V  0x1
+#define GPIO_PIN32_PAD_DRIVER_S  2
+/* GPIO_PIN32_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN32_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN32_SYNC2_BYPASS_M  ((GPIO_PIN32_SYNC2_BYPASS_V)<<(GPIO_PIN32_SYNC2_BYPASS_S))
+#define GPIO_PIN32_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN32_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN33_REG          (DR_REG_GPIO_BASE + 0xF8)
+/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN33_INT_ENA    0x0000001F
+#define GPIO_PIN33_INT_ENA_M  ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S))
+#define GPIO_PIN33_INT_ENA_V  0x1F
+#define GPIO_PIN33_INT_ENA_S  13
+/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN33_CONFIG    0x00000003
+#define GPIO_PIN33_CONFIG_M  ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S))
+#define GPIO_PIN33_CONFIG_V  0x3
+#define GPIO_PIN33_CONFIG_S  11
+/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN33_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN33_WAKEUP_ENABLE_S  10
+/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN33_INT_TYPE    0x00000007
+#define GPIO_PIN33_INT_TYPE_M  ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S))
+#define GPIO_PIN33_INT_TYPE_V  0x7
+#define GPIO_PIN33_INT_TYPE_S  7
+/* GPIO_PIN33_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN33_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN33_SYNC1_BYPASS_M  ((GPIO_PIN33_SYNC1_BYPASS_V)<<(GPIO_PIN33_SYNC1_BYPASS_S))
+#define GPIO_PIN33_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN33_SYNC1_BYPASS_S  3
+/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN33_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_V  0x1
+#define GPIO_PIN33_PAD_DRIVER_S  2
+/* GPIO_PIN33_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN33_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN33_SYNC2_BYPASS_M  ((GPIO_PIN33_SYNC2_BYPASS_V)<<(GPIO_PIN33_SYNC2_BYPASS_S))
+#define GPIO_PIN33_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN33_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN34_REG          (DR_REG_GPIO_BASE + 0xFC)
+/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN34_INT_ENA    0x0000001F
+#define GPIO_PIN34_INT_ENA_M  ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S))
+#define GPIO_PIN34_INT_ENA_V  0x1F
+#define GPIO_PIN34_INT_ENA_S  13
+/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN34_CONFIG    0x00000003
+#define GPIO_PIN34_CONFIG_M  ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S))
+#define GPIO_PIN34_CONFIG_V  0x3
+#define GPIO_PIN34_CONFIG_S  11
+/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN34_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN34_WAKEUP_ENABLE_S  10
+/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN34_INT_TYPE    0x00000007
+#define GPIO_PIN34_INT_TYPE_M  ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S))
+#define GPIO_PIN34_INT_TYPE_V  0x7
+#define GPIO_PIN34_INT_TYPE_S  7
+/* GPIO_PIN34_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN34_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN34_SYNC1_BYPASS_M  ((GPIO_PIN34_SYNC1_BYPASS_V)<<(GPIO_PIN34_SYNC1_BYPASS_S))
+#define GPIO_PIN34_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN34_SYNC1_BYPASS_S  3
+/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN34_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_V  0x1
+#define GPIO_PIN34_PAD_DRIVER_S  2
+/* GPIO_PIN34_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN34_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN34_SYNC2_BYPASS_M  ((GPIO_PIN34_SYNC2_BYPASS_V)<<(GPIO_PIN34_SYNC2_BYPASS_S))
+#define GPIO_PIN34_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN34_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN35_REG          (DR_REG_GPIO_BASE + 0x100)
+/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN35_INT_ENA    0x0000001F
+#define GPIO_PIN35_INT_ENA_M  ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S))
+#define GPIO_PIN35_INT_ENA_V  0x1F
+#define GPIO_PIN35_INT_ENA_S  13
+/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN35_CONFIG    0x00000003
+#define GPIO_PIN35_CONFIG_M  ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S))
+#define GPIO_PIN35_CONFIG_V  0x3
+#define GPIO_PIN35_CONFIG_S  11
+/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN35_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN35_WAKEUP_ENABLE_S  10
+/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN35_INT_TYPE    0x00000007
+#define GPIO_PIN35_INT_TYPE_M  ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S))
+#define GPIO_PIN35_INT_TYPE_V  0x7
+#define GPIO_PIN35_INT_TYPE_S  7
+/* GPIO_PIN35_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN35_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN35_SYNC1_BYPASS_M  ((GPIO_PIN35_SYNC1_BYPASS_V)<<(GPIO_PIN35_SYNC1_BYPASS_S))
+#define GPIO_PIN35_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN35_SYNC1_BYPASS_S  3
+/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN35_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_V  0x1
+#define GPIO_PIN35_PAD_DRIVER_S  2
+/* GPIO_PIN35_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN35_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN35_SYNC2_BYPASS_M  ((GPIO_PIN35_SYNC2_BYPASS_V)<<(GPIO_PIN35_SYNC2_BYPASS_S))
+#define GPIO_PIN35_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN35_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN36_REG          (DR_REG_GPIO_BASE + 0x104)
+/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN36_INT_ENA    0x0000001F
+#define GPIO_PIN36_INT_ENA_M  ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S))
+#define GPIO_PIN36_INT_ENA_V  0x1F
+#define GPIO_PIN36_INT_ENA_S  13
+/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN36_CONFIG    0x00000003
+#define GPIO_PIN36_CONFIG_M  ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S))
+#define GPIO_PIN36_CONFIG_V  0x3
+#define GPIO_PIN36_CONFIG_S  11
+/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN36_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN36_WAKEUP_ENABLE_S  10
+/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN36_INT_TYPE    0x00000007
+#define GPIO_PIN36_INT_TYPE_M  ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S))
+#define GPIO_PIN36_INT_TYPE_V  0x7
+#define GPIO_PIN36_INT_TYPE_S  7
+/* GPIO_PIN36_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN36_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN36_SYNC1_BYPASS_M  ((GPIO_PIN36_SYNC1_BYPASS_V)<<(GPIO_PIN36_SYNC1_BYPASS_S))
+#define GPIO_PIN36_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN36_SYNC1_BYPASS_S  3
+/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN36_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_V  0x1
+#define GPIO_PIN36_PAD_DRIVER_S  2
+/* GPIO_PIN36_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN36_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN36_SYNC2_BYPASS_M  ((GPIO_PIN36_SYNC2_BYPASS_V)<<(GPIO_PIN36_SYNC2_BYPASS_S))
+#define GPIO_PIN36_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN36_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN37_REG          (DR_REG_GPIO_BASE + 0x108)
+/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN37_INT_ENA    0x0000001F
+#define GPIO_PIN37_INT_ENA_M  ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S))
+#define GPIO_PIN37_INT_ENA_V  0x1F
+#define GPIO_PIN37_INT_ENA_S  13
+/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN37_CONFIG    0x00000003
+#define GPIO_PIN37_CONFIG_M  ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S))
+#define GPIO_PIN37_CONFIG_V  0x3
+#define GPIO_PIN37_CONFIG_S  11
+/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN37_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN37_WAKEUP_ENABLE_S  10
+/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN37_INT_TYPE    0x00000007
+#define GPIO_PIN37_INT_TYPE_M  ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S))
+#define GPIO_PIN37_INT_TYPE_V  0x7
+#define GPIO_PIN37_INT_TYPE_S  7
+/* GPIO_PIN37_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN37_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN37_SYNC1_BYPASS_M  ((GPIO_PIN37_SYNC1_BYPASS_V)<<(GPIO_PIN37_SYNC1_BYPASS_S))
+#define GPIO_PIN37_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN37_SYNC1_BYPASS_S  3
+/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN37_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_V  0x1
+#define GPIO_PIN37_PAD_DRIVER_S  2
+/* GPIO_PIN37_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN37_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN37_SYNC2_BYPASS_M  ((GPIO_PIN37_SYNC2_BYPASS_V)<<(GPIO_PIN37_SYNC2_BYPASS_S))
+#define GPIO_PIN37_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN37_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN38_REG          (DR_REG_GPIO_BASE + 0x10C)
+/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN38_INT_ENA    0x0000001F
+#define GPIO_PIN38_INT_ENA_M  ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S))
+#define GPIO_PIN38_INT_ENA_V  0x1F
+#define GPIO_PIN38_INT_ENA_S  13
+/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN38_CONFIG    0x00000003
+#define GPIO_PIN38_CONFIG_M  ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S))
+#define GPIO_PIN38_CONFIG_V  0x3
+#define GPIO_PIN38_CONFIG_S  11
+/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN38_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN38_WAKEUP_ENABLE_S  10
+/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN38_INT_TYPE    0x00000007
+#define GPIO_PIN38_INT_TYPE_M  ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S))
+#define GPIO_PIN38_INT_TYPE_V  0x7
+#define GPIO_PIN38_INT_TYPE_S  7
+/* GPIO_PIN38_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN38_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN38_SYNC1_BYPASS_M  ((GPIO_PIN38_SYNC1_BYPASS_V)<<(GPIO_PIN38_SYNC1_BYPASS_S))
+#define GPIO_PIN38_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN38_SYNC1_BYPASS_S  3
+/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN38_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_V  0x1
+#define GPIO_PIN38_PAD_DRIVER_S  2
+/* GPIO_PIN38_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN38_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN38_SYNC2_BYPASS_M  ((GPIO_PIN38_SYNC2_BYPASS_V)<<(GPIO_PIN38_SYNC2_BYPASS_S))
+#define GPIO_PIN38_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN38_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN39_REG          (DR_REG_GPIO_BASE + 0x110)
+/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN39_INT_ENA    0x0000001F
+#define GPIO_PIN39_INT_ENA_M  ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S))
+#define GPIO_PIN39_INT_ENA_V  0x1F
+#define GPIO_PIN39_INT_ENA_S  13
+/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN39_CONFIG    0x00000003
+#define GPIO_PIN39_CONFIG_M  ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S))
+#define GPIO_PIN39_CONFIG_V  0x3
+#define GPIO_PIN39_CONFIG_S  11
+/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN39_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN39_WAKEUP_ENABLE_S  10
+/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN39_INT_TYPE    0x00000007
+#define GPIO_PIN39_INT_TYPE_M  ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S))
+#define GPIO_PIN39_INT_TYPE_V  0x7
+#define GPIO_PIN39_INT_TYPE_S  7
+/* GPIO_PIN39_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN39_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN39_SYNC1_BYPASS_M  ((GPIO_PIN39_SYNC1_BYPASS_V)<<(GPIO_PIN39_SYNC1_BYPASS_S))
+#define GPIO_PIN39_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN39_SYNC1_BYPASS_S  3
+/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN39_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_V  0x1
+#define GPIO_PIN39_PAD_DRIVER_S  2
+/* GPIO_PIN39_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN39_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN39_SYNC2_BYPASS_M  ((GPIO_PIN39_SYNC2_BYPASS_V)<<(GPIO_PIN39_SYNC2_BYPASS_S))
+#define GPIO_PIN39_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN39_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN40_REG          (DR_REG_GPIO_BASE + 0x114)
+/* GPIO_PIN40_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN40_INT_ENA    0x0000001F
+#define GPIO_PIN40_INT_ENA_M  ((GPIO_PIN40_INT_ENA_V)<<(GPIO_PIN40_INT_ENA_S))
+#define GPIO_PIN40_INT_ENA_V  0x1F
+#define GPIO_PIN40_INT_ENA_S  13
+/* GPIO_PIN40_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN40_CONFIG    0x00000003
+#define GPIO_PIN40_CONFIG_M  ((GPIO_PIN40_CONFIG_V)<<(GPIO_PIN40_CONFIG_S))
+#define GPIO_PIN40_CONFIG_V  0x3
+#define GPIO_PIN40_CONFIG_S  11
+/* GPIO_PIN40_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN40_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN40_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN40_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN40_WAKEUP_ENABLE_S  10
+/* GPIO_PIN40_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN40_INT_TYPE    0x00000007
+#define GPIO_PIN40_INT_TYPE_M  ((GPIO_PIN40_INT_TYPE_V)<<(GPIO_PIN40_INT_TYPE_S))
+#define GPIO_PIN40_INT_TYPE_V  0x7
+#define GPIO_PIN40_INT_TYPE_S  7
+/* GPIO_PIN40_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN40_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN40_SYNC1_BYPASS_M  ((GPIO_PIN40_SYNC1_BYPASS_V)<<(GPIO_PIN40_SYNC1_BYPASS_S))
+#define GPIO_PIN40_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN40_SYNC1_BYPASS_S  3
+/* GPIO_PIN40_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN40_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN40_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN40_PAD_DRIVER_V  0x1
+#define GPIO_PIN40_PAD_DRIVER_S  2
+/* GPIO_PIN40_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN40_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN40_SYNC2_BYPASS_M  ((GPIO_PIN40_SYNC2_BYPASS_V)<<(GPIO_PIN40_SYNC2_BYPASS_S))
+#define GPIO_PIN40_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN40_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN41_REG          (DR_REG_GPIO_BASE + 0x118)
+/* GPIO_PIN41_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN41_INT_ENA    0x0000001F
+#define GPIO_PIN41_INT_ENA_M  ((GPIO_PIN41_INT_ENA_V)<<(GPIO_PIN41_INT_ENA_S))
+#define GPIO_PIN41_INT_ENA_V  0x1F
+#define GPIO_PIN41_INT_ENA_S  13
+/* GPIO_PIN41_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN41_CONFIG    0x00000003
+#define GPIO_PIN41_CONFIG_M  ((GPIO_PIN41_CONFIG_V)<<(GPIO_PIN41_CONFIG_S))
+#define GPIO_PIN41_CONFIG_V  0x3
+#define GPIO_PIN41_CONFIG_S  11
+/* GPIO_PIN41_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN41_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN41_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN41_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN41_WAKEUP_ENABLE_S  10
+/* GPIO_PIN41_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN41_INT_TYPE    0x00000007
+#define GPIO_PIN41_INT_TYPE_M  ((GPIO_PIN41_INT_TYPE_V)<<(GPIO_PIN41_INT_TYPE_S))
+#define GPIO_PIN41_INT_TYPE_V  0x7
+#define GPIO_PIN41_INT_TYPE_S  7
+/* GPIO_PIN41_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN41_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN41_SYNC1_BYPASS_M  ((GPIO_PIN41_SYNC1_BYPASS_V)<<(GPIO_PIN41_SYNC1_BYPASS_S))
+#define GPIO_PIN41_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN41_SYNC1_BYPASS_S  3
+/* GPIO_PIN41_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN41_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN41_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN41_PAD_DRIVER_V  0x1
+#define GPIO_PIN41_PAD_DRIVER_S  2
+/* GPIO_PIN41_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN41_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN41_SYNC2_BYPASS_M  ((GPIO_PIN41_SYNC2_BYPASS_V)<<(GPIO_PIN41_SYNC2_BYPASS_S))
+#define GPIO_PIN41_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN41_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN42_REG          (DR_REG_GPIO_BASE + 0x11C)
+/* GPIO_PIN42_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN42_INT_ENA    0x0000001F
+#define GPIO_PIN42_INT_ENA_M  ((GPIO_PIN42_INT_ENA_V)<<(GPIO_PIN42_INT_ENA_S))
+#define GPIO_PIN42_INT_ENA_V  0x1F
+#define GPIO_PIN42_INT_ENA_S  13
+/* GPIO_PIN42_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN42_CONFIG    0x00000003
+#define GPIO_PIN42_CONFIG_M  ((GPIO_PIN42_CONFIG_V)<<(GPIO_PIN42_CONFIG_S))
+#define GPIO_PIN42_CONFIG_V  0x3
+#define GPIO_PIN42_CONFIG_S  11
+/* GPIO_PIN42_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN42_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN42_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN42_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN42_WAKEUP_ENABLE_S  10
+/* GPIO_PIN42_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN42_INT_TYPE    0x00000007
+#define GPIO_PIN42_INT_TYPE_M  ((GPIO_PIN42_INT_TYPE_V)<<(GPIO_PIN42_INT_TYPE_S))
+#define GPIO_PIN42_INT_TYPE_V  0x7
+#define GPIO_PIN42_INT_TYPE_S  7
+/* GPIO_PIN42_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN42_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN42_SYNC1_BYPASS_M  ((GPIO_PIN42_SYNC1_BYPASS_V)<<(GPIO_PIN42_SYNC1_BYPASS_S))
+#define GPIO_PIN42_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN42_SYNC1_BYPASS_S  3
+/* GPIO_PIN42_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN42_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN42_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN42_PAD_DRIVER_V  0x1
+#define GPIO_PIN42_PAD_DRIVER_S  2
+/* GPIO_PIN42_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN42_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN42_SYNC2_BYPASS_M  ((GPIO_PIN42_SYNC2_BYPASS_V)<<(GPIO_PIN42_SYNC2_BYPASS_S))
+#define GPIO_PIN42_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN42_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN43_REG          (DR_REG_GPIO_BASE + 0x120)
+/* GPIO_PIN43_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN43_INT_ENA    0x0000001F
+#define GPIO_PIN43_INT_ENA_M  ((GPIO_PIN43_INT_ENA_V)<<(GPIO_PIN43_INT_ENA_S))
+#define GPIO_PIN43_INT_ENA_V  0x1F
+#define GPIO_PIN43_INT_ENA_S  13
+/* GPIO_PIN43_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN43_CONFIG    0x00000003
+#define GPIO_PIN43_CONFIG_M  ((GPIO_PIN43_CONFIG_V)<<(GPIO_PIN43_CONFIG_S))
+#define GPIO_PIN43_CONFIG_V  0x3
+#define GPIO_PIN43_CONFIG_S  11
+/* GPIO_PIN43_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN43_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN43_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN43_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN43_WAKEUP_ENABLE_S  10
+/* GPIO_PIN43_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN43_INT_TYPE    0x00000007
+#define GPIO_PIN43_INT_TYPE_M  ((GPIO_PIN43_INT_TYPE_V)<<(GPIO_PIN43_INT_TYPE_S))
+#define GPIO_PIN43_INT_TYPE_V  0x7
+#define GPIO_PIN43_INT_TYPE_S  7
+/* GPIO_PIN43_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN43_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN43_SYNC1_BYPASS_M  ((GPIO_PIN43_SYNC1_BYPASS_V)<<(GPIO_PIN43_SYNC1_BYPASS_S))
+#define GPIO_PIN43_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN43_SYNC1_BYPASS_S  3
+/* GPIO_PIN43_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN43_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN43_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN43_PAD_DRIVER_V  0x1
+#define GPIO_PIN43_PAD_DRIVER_S  2
+/* GPIO_PIN43_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN43_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN43_SYNC2_BYPASS_M  ((GPIO_PIN43_SYNC2_BYPASS_V)<<(GPIO_PIN43_SYNC2_BYPASS_S))
+#define GPIO_PIN43_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN43_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN44_REG          (DR_REG_GPIO_BASE + 0x124)
+/* GPIO_PIN44_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN44_INT_ENA    0x0000001F
+#define GPIO_PIN44_INT_ENA_M  ((GPIO_PIN44_INT_ENA_V)<<(GPIO_PIN44_INT_ENA_S))
+#define GPIO_PIN44_INT_ENA_V  0x1F
+#define GPIO_PIN44_INT_ENA_S  13
+/* GPIO_PIN44_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN44_CONFIG    0x00000003
+#define GPIO_PIN44_CONFIG_M  ((GPIO_PIN44_CONFIG_V)<<(GPIO_PIN44_CONFIG_S))
+#define GPIO_PIN44_CONFIG_V  0x3
+#define GPIO_PIN44_CONFIG_S  11
+/* GPIO_PIN44_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN44_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN44_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN44_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN44_WAKEUP_ENABLE_S  10
+/* GPIO_PIN44_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN44_INT_TYPE    0x00000007
+#define GPIO_PIN44_INT_TYPE_M  ((GPIO_PIN44_INT_TYPE_V)<<(GPIO_PIN44_INT_TYPE_S))
+#define GPIO_PIN44_INT_TYPE_V  0x7
+#define GPIO_PIN44_INT_TYPE_S  7
+/* GPIO_PIN44_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN44_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN44_SYNC1_BYPASS_M  ((GPIO_PIN44_SYNC1_BYPASS_V)<<(GPIO_PIN44_SYNC1_BYPASS_S))
+#define GPIO_PIN44_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN44_SYNC1_BYPASS_S  3
+/* GPIO_PIN44_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN44_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN44_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN44_PAD_DRIVER_V  0x1
+#define GPIO_PIN44_PAD_DRIVER_S  2
+/* GPIO_PIN44_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN44_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN44_SYNC2_BYPASS_M  ((GPIO_PIN44_SYNC2_BYPASS_V)<<(GPIO_PIN44_SYNC2_BYPASS_S))
+#define GPIO_PIN44_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN44_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN45_REG          (DR_REG_GPIO_BASE + 0x128)
+/* GPIO_PIN45_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN45_INT_ENA    0x0000001F
+#define GPIO_PIN45_INT_ENA_M  ((GPIO_PIN45_INT_ENA_V)<<(GPIO_PIN45_INT_ENA_S))
+#define GPIO_PIN45_INT_ENA_V  0x1F
+#define GPIO_PIN45_INT_ENA_S  13
+/* GPIO_PIN45_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN45_CONFIG    0x00000003
+#define GPIO_PIN45_CONFIG_M  ((GPIO_PIN45_CONFIG_V)<<(GPIO_PIN45_CONFIG_S))
+#define GPIO_PIN45_CONFIG_V  0x3
+#define GPIO_PIN45_CONFIG_S  11
+/* GPIO_PIN45_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN45_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN45_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN45_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN45_WAKEUP_ENABLE_S  10
+/* GPIO_PIN45_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN45_INT_TYPE    0x00000007
+#define GPIO_PIN45_INT_TYPE_M  ((GPIO_PIN45_INT_TYPE_V)<<(GPIO_PIN45_INT_TYPE_S))
+#define GPIO_PIN45_INT_TYPE_V  0x7
+#define GPIO_PIN45_INT_TYPE_S  7
+/* GPIO_PIN45_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN45_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN45_SYNC1_BYPASS_M  ((GPIO_PIN45_SYNC1_BYPASS_V)<<(GPIO_PIN45_SYNC1_BYPASS_S))
+#define GPIO_PIN45_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN45_SYNC1_BYPASS_S  3
+/* GPIO_PIN45_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN45_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN45_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN45_PAD_DRIVER_V  0x1
+#define GPIO_PIN45_PAD_DRIVER_S  2
+/* GPIO_PIN45_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN45_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN45_SYNC2_BYPASS_M  ((GPIO_PIN45_SYNC2_BYPASS_V)<<(GPIO_PIN45_SYNC2_BYPASS_S))
+#define GPIO_PIN45_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN45_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN46_REG          (DR_REG_GPIO_BASE + 0x12C)
+/* GPIO_PIN46_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN46_INT_ENA    0x0000001F
+#define GPIO_PIN46_INT_ENA_M  ((GPIO_PIN46_INT_ENA_V)<<(GPIO_PIN46_INT_ENA_S))
+#define GPIO_PIN46_INT_ENA_V  0x1F
+#define GPIO_PIN46_INT_ENA_S  13
+/* GPIO_PIN46_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN46_CONFIG    0x00000003
+#define GPIO_PIN46_CONFIG_M  ((GPIO_PIN46_CONFIG_V)<<(GPIO_PIN46_CONFIG_S))
+#define GPIO_PIN46_CONFIG_V  0x3
+#define GPIO_PIN46_CONFIG_S  11
+/* GPIO_PIN46_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN46_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN46_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN46_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN46_WAKEUP_ENABLE_S  10
+/* GPIO_PIN46_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN46_INT_TYPE    0x00000007
+#define GPIO_PIN46_INT_TYPE_M  ((GPIO_PIN46_INT_TYPE_V)<<(GPIO_PIN46_INT_TYPE_S))
+#define GPIO_PIN46_INT_TYPE_V  0x7
+#define GPIO_PIN46_INT_TYPE_S  7
+/* GPIO_PIN46_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN46_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN46_SYNC1_BYPASS_M  ((GPIO_PIN46_SYNC1_BYPASS_V)<<(GPIO_PIN46_SYNC1_BYPASS_S))
+#define GPIO_PIN46_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN46_SYNC1_BYPASS_S  3
+/* GPIO_PIN46_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN46_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN46_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN46_PAD_DRIVER_V  0x1
+#define GPIO_PIN46_PAD_DRIVER_S  2
+/* GPIO_PIN46_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN46_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN46_SYNC2_BYPASS_M  ((GPIO_PIN46_SYNC2_BYPASS_V)<<(GPIO_PIN46_SYNC2_BYPASS_S))
+#define GPIO_PIN46_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN46_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN47_REG          (DR_REG_GPIO_BASE + 0x130)
+/* GPIO_PIN47_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN47_INT_ENA    0x0000001F
+#define GPIO_PIN47_INT_ENA_M  ((GPIO_PIN47_INT_ENA_V)<<(GPIO_PIN47_INT_ENA_S))
+#define GPIO_PIN47_INT_ENA_V  0x1F
+#define GPIO_PIN47_INT_ENA_S  13
+/* GPIO_PIN47_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN47_CONFIG    0x00000003
+#define GPIO_PIN47_CONFIG_M  ((GPIO_PIN47_CONFIG_V)<<(GPIO_PIN47_CONFIG_S))
+#define GPIO_PIN47_CONFIG_V  0x3
+#define GPIO_PIN47_CONFIG_S  11
+/* GPIO_PIN47_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN47_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN47_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN47_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN47_WAKEUP_ENABLE_S  10
+/* GPIO_PIN47_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN47_INT_TYPE    0x00000007
+#define GPIO_PIN47_INT_TYPE_M  ((GPIO_PIN47_INT_TYPE_V)<<(GPIO_PIN47_INT_TYPE_S))
+#define GPIO_PIN47_INT_TYPE_V  0x7
+#define GPIO_PIN47_INT_TYPE_S  7
+/* GPIO_PIN47_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN47_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN47_SYNC1_BYPASS_M  ((GPIO_PIN47_SYNC1_BYPASS_V)<<(GPIO_PIN47_SYNC1_BYPASS_S))
+#define GPIO_PIN47_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN47_SYNC1_BYPASS_S  3
+/* GPIO_PIN47_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN47_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN47_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN47_PAD_DRIVER_V  0x1
+#define GPIO_PIN47_PAD_DRIVER_S  2
+/* GPIO_PIN47_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN47_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN47_SYNC2_BYPASS_M  ((GPIO_PIN47_SYNC2_BYPASS_V)<<(GPIO_PIN47_SYNC2_BYPASS_S))
+#define GPIO_PIN47_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN47_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN48_REG          (DR_REG_GPIO_BASE + 0x134)
+/* GPIO_PIN48_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN48_INT_ENA    0x0000001F
+#define GPIO_PIN48_INT_ENA_M  ((GPIO_PIN48_INT_ENA_V)<<(GPIO_PIN48_INT_ENA_S))
+#define GPIO_PIN48_INT_ENA_V  0x1F
+#define GPIO_PIN48_INT_ENA_S  13
+/* GPIO_PIN48_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN48_CONFIG    0x00000003
+#define GPIO_PIN48_CONFIG_M  ((GPIO_PIN48_CONFIG_V)<<(GPIO_PIN48_CONFIG_S))
+#define GPIO_PIN48_CONFIG_V  0x3
+#define GPIO_PIN48_CONFIG_S  11
+/* GPIO_PIN48_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN48_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN48_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN48_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN48_WAKEUP_ENABLE_S  10
+/* GPIO_PIN48_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN48_INT_TYPE    0x00000007
+#define GPIO_PIN48_INT_TYPE_M  ((GPIO_PIN48_INT_TYPE_V)<<(GPIO_PIN48_INT_TYPE_S))
+#define GPIO_PIN48_INT_TYPE_V  0x7
+#define GPIO_PIN48_INT_TYPE_S  7
+/* GPIO_PIN48_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN48_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN48_SYNC1_BYPASS_M  ((GPIO_PIN48_SYNC1_BYPASS_V)<<(GPIO_PIN48_SYNC1_BYPASS_S))
+#define GPIO_PIN48_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN48_SYNC1_BYPASS_S  3
+/* GPIO_PIN48_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN48_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN48_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN48_PAD_DRIVER_V  0x1
+#define GPIO_PIN48_PAD_DRIVER_S  2
+/* GPIO_PIN48_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN48_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN48_SYNC2_BYPASS_M  ((GPIO_PIN48_SYNC2_BYPASS_V)<<(GPIO_PIN48_SYNC2_BYPASS_S))
+#define GPIO_PIN48_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN48_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN49_REG          (DR_REG_GPIO_BASE + 0x138)
+/* GPIO_PIN49_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN49_INT_ENA    0x0000001F
+#define GPIO_PIN49_INT_ENA_M  ((GPIO_PIN49_INT_ENA_V)<<(GPIO_PIN49_INT_ENA_S))
+#define GPIO_PIN49_INT_ENA_V  0x1F
+#define GPIO_PIN49_INT_ENA_S  13
+/* GPIO_PIN49_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN49_CONFIG    0x00000003
+#define GPIO_PIN49_CONFIG_M  ((GPIO_PIN49_CONFIG_V)<<(GPIO_PIN49_CONFIG_S))
+#define GPIO_PIN49_CONFIG_V  0x3
+#define GPIO_PIN49_CONFIG_S  11
+/* GPIO_PIN49_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN49_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN49_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN49_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN49_WAKEUP_ENABLE_S  10
+/* GPIO_PIN49_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN49_INT_TYPE    0x00000007
+#define GPIO_PIN49_INT_TYPE_M  ((GPIO_PIN49_INT_TYPE_V)<<(GPIO_PIN49_INT_TYPE_S))
+#define GPIO_PIN49_INT_TYPE_V  0x7
+#define GPIO_PIN49_INT_TYPE_S  7
+/* GPIO_PIN49_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN49_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN49_SYNC1_BYPASS_M  ((GPIO_PIN49_SYNC1_BYPASS_V)<<(GPIO_PIN49_SYNC1_BYPASS_S))
+#define GPIO_PIN49_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN49_SYNC1_BYPASS_S  3
+/* GPIO_PIN49_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN49_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN49_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN49_PAD_DRIVER_V  0x1
+#define GPIO_PIN49_PAD_DRIVER_S  2
+/* GPIO_PIN49_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN49_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN49_SYNC2_BYPASS_M  ((GPIO_PIN49_SYNC2_BYPASS_V)<<(GPIO_PIN49_SYNC2_BYPASS_S))
+#define GPIO_PIN49_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN49_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN50_REG          (DR_REG_GPIO_BASE + 0x13C)
+/* GPIO_PIN50_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN50_INT_ENA    0x0000001F
+#define GPIO_PIN50_INT_ENA_M  ((GPIO_PIN50_INT_ENA_V)<<(GPIO_PIN50_INT_ENA_S))
+#define GPIO_PIN50_INT_ENA_V  0x1F
+#define GPIO_PIN50_INT_ENA_S  13
+/* GPIO_PIN50_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN50_CONFIG    0x00000003
+#define GPIO_PIN50_CONFIG_M  ((GPIO_PIN50_CONFIG_V)<<(GPIO_PIN50_CONFIG_S))
+#define GPIO_PIN50_CONFIG_V  0x3
+#define GPIO_PIN50_CONFIG_S  11
+/* GPIO_PIN50_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN50_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN50_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN50_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN50_WAKEUP_ENABLE_S  10
+/* GPIO_PIN50_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN50_INT_TYPE    0x00000007
+#define GPIO_PIN50_INT_TYPE_M  ((GPIO_PIN50_INT_TYPE_V)<<(GPIO_PIN50_INT_TYPE_S))
+#define GPIO_PIN50_INT_TYPE_V  0x7
+#define GPIO_PIN50_INT_TYPE_S  7
+/* GPIO_PIN50_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN50_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN50_SYNC1_BYPASS_M  ((GPIO_PIN50_SYNC1_BYPASS_V)<<(GPIO_PIN50_SYNC1_BYPASS_S))
+#define GPIO_PIN50_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN50_SYNC1_BYPASS_S  3
+/* GPIO_PIN50_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN50_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN50_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN50_PAD_DRIVER_V  0x1
+#define GPIO_PIN50_PAD_DRIVER_S  2
+/* GPIO_PIN50_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN50_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN50_SYNC2_BYPASS_M  ((GPIO_PIN50_SYNC2_BYPASS_V)<<(GPIO_PIN50_SYNC2_BYPASS_S))
+#define GPIO_PIN50_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN50_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN51_REG          (DR_REG_GPIO_BASE + 0x140)
+/* GPIO_PIN51_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN51_INT_ENA    0x0000001F
+#define GPIO_PIN51_INT_ENA_M  ((GPIO_PIN51_INT_ENA_V)<<(GPIO_PIN51_INT_ENA_S))
+#define GPIO_PIN51_INT_ENA_V  0x1F
+#define GPIO_PIN51_INT_ENA_S  13
+/* GPIO_PIN51_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN51_CONFIG    0x00000003
+#define GPIO_PIN51_CONFIG_M  ((GPIO_PIN51_CONFIG_V)<<(GPIO_PIN51_CONFIG_S))
+#define GPIO_PIN51_CONFIG_V  0x3
+#define GPIO_PIN51_CONFIG_S  11
+/* GPIO_PIN51_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN51_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN51_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN51_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN51_WAKEUP_ENABLE_S  10
+/* GPIO_PIN51_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN51_INT_TYPE    0x00000007
+#define GPIO_PIN51_INT_TYPE_M  ((GPIO_PIN51_INT_TYPE_V)<<(GPIO_PIN51_INT_TYPE_S))
+#define GPIO_PIN51_INT_TYPE_V  0x7
+#define GPIO_PIN51_INT_TYPE_S  7
+/* GPIO_PIN51_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN51_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN51_SYNC1_BYPASS_M  ((GPIO_PIN51_SYNC1_BYPASS_V)<<(GPIO_PIN51_SYNC1_BYPASS_S))
+#define GPIO_PIN51_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN51_SYNC1_BYPASS_S  3
+/* GPIO_PIN51_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN51_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN51_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN51_PAD_DRIVER_V  0x1
+#define GPIO_PIN51_PAD_DRIVER_S  2
+/* GPIO_PIN51_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN51_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN51_SYNC2_BYPASS_M  ((GPIO_PIN51_SYNC2_BYPASS_V)<<(GPIO_PIN51_SYNC2_BYPASS_S))
+#define GPIO_PIN51_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN51_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN52_REG          (DR_REG_GPIO_BASE + 0x144)
+/* GPIO_PIN52_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN52_INT_ENA    0x0000001F
+#define GPIO_PIN52_INT_ENA_M  ((GPIO_PIN52_INT_ENA_V)<<(GPIO_PIN52_INT_ENA_S))
+#define GPIO_PIN52_INT_ENA_V  0x1F
+#define GPIO_PIN52_INT_ENA_S  13
+/* GPIO_PIN52_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN52_CONFIG    0x00000003
+#define GPIO_PIN52_CONFIG_M  ((GPIO_PIN52_CONFIG_V)<<(GPIO_PIN52_CONFIG_S))
+#define GPIO_PIN52_CONFIG_V  0x3
+#define GPIO_PIN52_CONFIG_S  11
+/* GPIO_PIN52_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN52_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN52_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN52_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN52_WAKEUP_ENABLE_S  10
+/* GPIO_PIN52_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN52_INT_TYPE    0x00000007
+#define GPIO_PIN52_INT_TYPE_M  ((GPIO_PIN52_INT_TYPE_V)<<(GPIO_PIN52_INT_TYPE_S))
+#define GPIO_PIN52_INT_TYPE_V  0x7
+#define GPIO_PIN52_INT_TYPE_S  7
+/* GPIO_PIN52_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN52_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN52_SYNC1_BYPASS_M  ((GPIO_PIN52_SYNC1_BYPASS_V)<<(GPIO_PIN52_SYNC1_BYPASS_S))
+#define GPIO_PIN52_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN52_SYNC1_BYPASS_S  3
+/* GPIO_PIN52_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN52_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN52_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN52_PAD_DRIVER_V  0x1
+#define GPIO_PIN52_PAD_DRIVER_S  2
+/* GPIO_PIN52_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN52_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN52_SYNC2_BYPASS_M  ((GPIO_PIN52_SYNC2_BYPASS_V)<<(GPIO_PIN52_SYNC2_BYPASS_S))
+#define GPIO_PIN52_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN52_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN53_REG          (DR_REG_GPIO_BASE + 0x148)
+/* GPIO_PIN53_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: .*/
+#define GPIO_PIN53_INT_ENA    0x0000001F
+#define GPIO_PIN53_INT_ENA_M  ((GPIO_PIN53_INT_ENA_V)<<(GPIO_PIN53_INT_ENA_S))
+#define GPIO_PIN53_INT_ENA_V  0x1F
+#define GPIO_PIN53_INT_ENA_S  13
+/* GPIO_PIN53_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN53_CONFIG    0x00000003
+#define GPIO_PIN53_CONFIG_M  ((GPIO_PIN53_CONFIG_V)<<(GPIO_PIN53_CONFIG_S))
+#define GPIO_PIN53_CONFIG_V  0x3
+#define GPIO_PIN53_CONFIG_S  11
+/* GPIO_PIN53_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN53_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN53_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN53_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN53_WAKEUP_ENABLE_S  10
+/* GPIO_PIN53_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: .*/
+#define GPIO_PIN53_INT_TYPE    0x00000007
+#define GPIO_PIN53_INT_TYPE_M  ((GPIO_PIN53_INT_TYPE_V)<<(GPIO_PIN53_INT_TYPE_S))
+#define GPIO_PIN53_INT_TYPE_V  0x7
+#define GPIO_PIN53_INT_TYPE_S  7
+/* GPIO_PIN53_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN53_SYNC1_BYPASS    0x00000003
+#define GPIO_PIN53_SYNC1_BYPASS_M  ((GPIO_PIN53_SYNC1_BYPASS_V)<<(GPIO_PIN53_SYNC1_BYPASS_S))
+#define GPIO_PIN53_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN53_SYNC1_BYPASS_S  3
+/* GPIO_PIN53_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_PIN53_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN53_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN53_PAD_DRIVER_V  0x1
+#define GPIO_PIN53_PAD_DRIVER_S  2
+/* GPIO_PIN53_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: .*/
+#define GPIO_PIN53_SYNC2_BYPASS    0x00000003
+#define GPIO_PIN53_SYNC2_BYPASS_M  ((GPIO_PIN53_SYNC2_BYPASS_V)<<(GPIO_PIN53_SYNC2_BYPASS_S))
+#define GPIO_PIN53_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN53_SYNC2_BYPASS_S  0
+
+#define GPIO_STATUS_NEXT_REG          (DR_REG_GPIO_BASE + 0x14C)
+/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define GPIO_STATUS_INTERRUPT_NEXT    0xFFFFFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT_M  ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S))
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0xFFFFFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+#define GPIO_STATUS_NEXT1_REG          (DR_REG_GPIO_BASE + 0x150)
+/* GPIO_STATUS_INTERRUPT_NEXT1 : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_STATUS_INTERRUPT_NEXT1  0x003FFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT1_M  ((GPIO_STATUS_INTERRUPT_NEXT1_V)<<(GPIO_STATUS_INTERRUPT_NEXT1_S))
+#define GPIO_STATUS_INTERRUPT_NEXT1_V  0x3FFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT1_S  0
+
+#define GPIO_FUNC0_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x154)
+/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG0_IN_SEL    (BIT(7))
+#define GPIO_SIG0_IN_SEL_M  (BIT(7))
+#define GPIO_SIG0_IN_SEL_V  0x1
+#define GPIO_SIG0_IN_SEL_S  7
+/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC0_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC0_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC0_IN_INV_SEL_V  0x1
+#define GPIO_FUNC0_IN_INV_SEL_S  6
+/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC0_IN_SEL    0x0000003F
+#define GPIO_FUNC0_IN_SEL_M  ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
+#define GPIO_FUNC0_IN_SEL_V  0x3F
+#define GPIO_FUNC0_IN_SEL_S  0
+
+#define GPIO_FUNC1_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x158)
+/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG1_IN_SEL    (BIT(7))
+#define GPIO_SIG1_IN_SEL_M  (BIT(7))
+#define GPIO_SIG1_IN_SEL_V  0x1
+#define GPIO_SIG1_IN_SEL_S  7
+/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC1_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_V  0x1
+#define GPIO_FUNC1_IN_INV_SEL_S  6
+/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC1_IN_SEL    0x0000003F
+#define GPIO_FUNC1_IN_SEL_M  ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
+#define GPIO_FUNC1_IN_SEL_V  0x3F
+#define GPIO_FUNC1_IN_SEL_S  0
+
+#define GPIO_FUNC2_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x15C)
+/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG2_IN_SEL    (BIT(7))
+#define GPIO_SIG2_IN_SEL_M  (BIT(7))
+#define GPIO_SIG2_IN_SEL_V  0x1
+#define GPIO_SIG2_IN_SEL_S  7
+/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC2_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_V  0x1
+#define GPIO_FUNC2_IN_INV_SEL_S  6
+/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC2_IN_SEL    0x0000003F
+#define GPIO_FUNC2_IN_SEL_M  ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
+#define GPIO_FUNC2_IN_SEL_V  0x3F
+#define GPIO_FUNC2_IN_SEL_S  0
+
+#define GPIO_FUNC3_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x160)
+/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG3_IN_SEL    (BIT(7))
+#define GPIO_SIG3_IN_SEL_M  (BIT(7))
+#define GPIO_SIG3_IN_SEL_V  0x1
+#define GPIO_SIG3_IN_SEL_S  7
+/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC3_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_V  0x1
+#define GPIO_FUNC3_IN_INV_SEL_S  6
+/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC3_IN_SEL    0x0000003F
+#define GPIO_FUNC3_IN_SEL_M  ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
+#define GPIO_FUNC3_IN_SEL_V  0x3F
+#define GPIO_FUNC3_IN_SEL_S  0
+
+#define GPIO_FUNC4_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x164)
+/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG4_IN_SEL    (BIT(7))
+#define GPIO_SIG4_IN_SEL_M  (BIT(7))
+#define GPIO_SIG4_IN_SEL_V  0x1
+#define GPIO_SIG4_IN_SEL_S  7
+/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC4_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_V  0x1
+#define GPIO_FUNC4_IN_INV_SEL_S  6
+/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC4_IN_SEL    0x0000003F
+#define GPIO_FUNC4_IN_SEL_M  ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
+#define GPIO_FUNC4_IN_SEL_V  0x3F
+#define GPIO_FUNC4_IN_SEL_S  0
+
+#define GPIO_FUNC5_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x168)
+/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG5_IN_SEL    (BIT(7))
+#define GPIO_SIG5_IN_SEL_M  (BIT(7))
+#define GPIO_SIG5_IN_SEL_V  0x1
+#define GPIO_SIG5_IN_SEL_S  7
+/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC5_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_V  0x1
+#define GPIO_FUNC5_IN_INV_SEL_S  6
+/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC5_IN_SEL    0x0000003F
+#define GPIO_FUNC5_IN_SEL_M  ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
+#define GPIO_FUNC5_IN_SEL_V  0x3F
+#define GPIO_FUNC5_IN_SEL_S  0
+
+#define GPIO_FUNC6_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x16C)
+/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG6_IN_SEL    (BIT(7))
+#define GPIO_SIG6_IN_SEL_M  (BIT(7))
+#define GPIO_SIG6_IN_SEL_V  0x1
+#define GPIO_SIG6_IN_SEL_S  7
+/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC6_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_V  0x1
+#define GPIO_FUNC6_IN_INV_SEL_S  6
+/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC6_IN_SEL    0x0000003F
+#define GPIO_FUNC6_IN_SEL_M  ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
+#define GPIO_FUNC6_IN_SEL_V  0x3F
+#define GPIO_FUNC6_IN_SEL_S  0
+
+#define GPIO_FUNC7_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x170)
+/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG7_IN_SEL    (BIT(7))
+#define GPIO_SIG7_IN_SEL_M  (BIT(7))
+#define GPIO_SIG7_IN_SEL_V  0x1
+#define GPIO_SIG7_IN_SEL_S  7
+/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC7_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_V  0x1
+#define GPIO_FUNC7_IN_INV_SEL_S  6
+/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC7_IN_SEL    0x0000003F
+#define GPIO_FUNC7_IN_SEL_M  ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
+#define GPIO_FUNC7_IN_SEL_V  0x3F
+#define GPIO_FUNC7_IN_SEL_S  0
+
+#define GPIO_FUNC8_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x174)
+/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG8_IN_SEL    (BIT(7))
+#define GPIO_SIG8_IN_SEL_M  (BIT(7))
+#define GPIO_SIG8_IN_SEL_V  0x1
+#define GPIO_SIG8_IN_SEL_S  7
+/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC8_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_V  0x1
+#define GPIO_FUNC8_IN_INV_SEL_S  6
+/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC8_IN_SEL    0x0000003F
+#define GPIO_FUNC8_IN_SEL_M  ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
+#define GPIO_FUNC8_IN_SEL_V  0x3F
+#define GPIO_FUNC8_IN_SEL_S  0
+
+#define GPIO_FUNC9_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x178)
+/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG9_IN_SEL    (BIT(7))
+#define GPIO_SIG9_IN_SEL_M  (BIT(7))
+#define GPIO_SIG9_IN_SEL_V  0x1
+#define GPIO_SIG9_IN_SEL_S  7
+/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC9_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_V  0x1
+#define GPIO_FUNC9_IN_INV_SEL_S  6
+/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC9_IN_SEL    0x0000003F
+#define GPIO_FUNC9_IN_SEL_M  ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
+#define GPIO_FUNC9_IN_SEL_V  0x3F
+#define GPIO_FUNC9_IN_SEL_S  0
+
+#define GPIO_FUNC10_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x17C)
+/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG10_IN_SEL    (BIT(7))
+#define GPIO_SIG10_IN_SEL_M  (BIT(7))
+#define GPIO_SIG10_IN_SEL_V  0x1
+#define GPIO_SIG10_IN_SEL_S  7
+/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC10_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_V  0x1
+#define GPIO_FUNC10_IN_INV_SEL_S  6
+/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC10_IN_SEL    0x0000003F
+#define GPIO_FUNC10_IN_SEL_M  ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
+#define GPIO_FUNC10_IN_SEL_V  0x3F
+#define GPIO_FUNC10_IN_SEL_S  0
+
+#define GPIO_FUNC11_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x180)
+/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG11_IN_SEL    (BIT(7))
+#define GPIO_SIG11_IN_SEL_M  (BIT(7))
+#define GPIO_SIG11_IN_SEL_V  0x1
+#define GPIO_SIG11_IN_SEL_S  7
+/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC11_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_V  0x1
+#define GPIO_FUNC11_IN_INV_SEL_S  6
+/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC11_IN_SEL    0x0000003F
+#define GPIO_FUNC11_IN_SEL_M  ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
+#define GPIO_FUNC11_IN_SEL_V  0x3F
+#define GPIO_FUNC11_IN_SEL_S  0
+
+#define GPIO_FUNC12_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x184)
+/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG12_IN_SEL    (BIT(7))
+#define GPIO_SIG12_IN_SEL_M  (BIT(7))
+#define GPIO_SIG12_IN_SEL_V  0x1
+#define GPIO_SIG12_IN_SEL_S  7
+/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC12_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_V  0x1
+#define GPIO_FUNC12_IN_INV_SEL_S  6
+/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC12_IN_SEL    0x0000003F
+#define GPIO_FUNC12_IN_SEL_M  ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
+#define GPIO_FUNC12_IN_SEL_V  0x3F
+#define GPIO_FUNC12_IN_SEL_S  0
+
+#define GPIO_FUNC13_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x188)
+/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG13_IN_SEL    (BIT(7))
+#define GPIO_SIG13_IN_SEL_M  (BIT(7))
+#define GPIO_SIG13_IN_SEL_V  0x1
+#define GPIO_SIG13_IN_SEL_S  7
+/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC13_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_V  0x1
+#define GPIO_FUNC13_IN_INV_SEL_S  6
+/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC13_IN_SEL    0x0000003F
+#define GPIO_FUNC13_IN_SEL_M  ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
+#define GPIO_FUNC13_IN_SEL_V  0x3F
+#define GPIO_FUNC13_IN_SEL_S  0
+
+#define GPIO_FUNC14_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x18C)
+/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG14_IN_SEL    (BIT(7))
+#define GPIO_SIG14_IN_SEL_M  (BIT(7))
+#define GPIO_SIG14_IN_SEL_V  0x1
+#define GPIO_SIG14_IN_SEL_S  7
+/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC14_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_V  0x1
+#define GPIO_FUNC14_IN_INV_SEL_S  6
+/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC14_IN_SEL    0x0000003F
+#define GPIO_FUNC14_IN_SEL_M  ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
+#define GPIO_FUNC14_IN_SEL_V  0x3F
+#define GPIO_FUNC14_IN_SEL_S  0
+
+#define GPIO_FUNC15_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x190)
+/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG15_IN_SEL    (BIT(7))
+#define GPIO_SIG15_IN_SEL_M  (BIT(7))
+#define GPIO_SIG15_IN_SEL_V  0x1
+#define GPIO_SIG15_IN_SEL_S  7
+/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC15_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_V  0x1
+#define GPIO_FUNC15_IN_INV_SEL_S  6
+/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC15_IN_SEL    0x0000003F
+#define GPIO_FUNC15_IN_SEL_M  ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
+#define GPIO_FUNC15_IN_SEL_V  0x3F
+#define GPIO_FUNC15_IN_SEL_S  0
+
+#define GPIO_FUNC16_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x194)
+/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG16_IN_SEL    (BIT(7))
+#define GPIO_SIG16_IN_SEL_M  (BIT(7))
+#define GPIO_SIG16_IN_SEL_V  0x1
+#define GPIO_SIG16_IN_SEL_S  7
+/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC16_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_V  0x1
+#define GPIO_FUNC16_IN_INV_SEL_S  6
+/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC16_IN_SEL    0x0000003F
+#define GPIO_FUNC16_IN_SEL_M  ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
+#define GPIO_FUNC16_IN_SEL_V  0x3F
+#define GPIO_FUNC16_IN_SEL_S  0
+
+#define GPIO_FUNC17_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x198)
+/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG17_IN_SEL    (BIT(7))
+#define GPIO_SIG17_IN_SEL_M  (BIT(7))
+#define GPIO_SIG17_IN_SEL_V  0x1
+#define GPIO_SIG17_IN_SEL_S  7
+/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC17_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_V  0x1
+#define GPIO_FUNC17_IN_INV_SEL_S  6
+/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC17_IN_SEL    0x0000003F
+#define GPIO_FUNC17_IN_SEL_M  ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
+#define GPIO_FUNC17_IN_SEL_V  0x3F
+#define GPIO_FUNC17_IN_SEL_S  0
+
+#define GPIO_FUNC18_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x19C)
+/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG18_IN_SEL    (BIT(7))
+#define GPIO_SIG18_IN_SEL_M  (BIT(7))
+#define GPIO_SIG18_IN_SEL_V  0x1
+#define GPIO_SIG18_IN_SEL_S  7
+/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC18_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_V  0x1
+#define GPIO_FUNC18_IN_INV_SEL_S  6
+/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC18_IN_SEL    0x0000003F
+#define GPIO_FUNC18_IN_SEL_M  ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
+#define GPIO_FUNC18_IN_SEL_V  0x3F
+#define GPIO_FUNC18_IN_SEL_S  0
+
+#define GPIO_FUNC19_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A0)
+/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG19_IN_SEL    (BIT(7))
+#define GPIO_SIG19_IN_SEL_M  (BIT(7))
+#define GPIO_SIG19_IN_SEL_V  0x1
+#define GPIO_SIG19_IN_SEL_S  7
+/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC19_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_V  0x1
+#define GPIO_FUNC19_IN_INV_SEL_S  6
+/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC19_IN_SEL    0x0000003F
+#define GPIO_FUNC19_IN_SEL_M  ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
+#define GPIO_FUNC19_IN_SEL_V  0x3F
+#define GPIO_FUNC19_IN_SEL_S  0
+
+#define GPIO_FUNC20_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A4)
+/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG20_IN_SEL    (BIT(7))
+#define GPIO_SIG20_IN_SEL_M  (BIT(7))
+#define GPIO_SIG20_IN_SEL_V  0x1
+#define GPIO_SIG20_IN_SEL_S  7
+/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC20_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_V  0x1
+#define GPIO_FUNC20_IN_INV_SEL_S  6
+/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC20_IN_SEL    0x0000003F
+#define GPIO_FUNC20_IN_SEL_M  ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
+#define GPIO_FUNC20_IN_SEL_V  0x3F
+#define GPIO_FUNC20_IN_SEL_S  0
+
+#define GPIO_FUNC21_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A8)
+/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG21_IN_SEL    (BIT(7))
+#define GPIO_SIG21_IN_SEL_M  (BIT(7))
+#define GPIO_SIG21_IN_SEL_V  0x1
+#define GPIO_SIG21_IN_SEL_S  7
+/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC21_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_V  0x1
+#define GPIO_FUNC21_IN_INV_SEL_S  6
+/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC21_IN_SEL    0x0000003F
+#define GPIO_FUNC21_IN_SEL_M  ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
+#define GPIO_FUNC21_IN_SEL_V  0x3F
+#define GPIO_FUNC21_IN_SEL_S  0
+
+#define GPIO_FUNC22_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1AC)
+/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG22_IN_SEL    (BIT(7))
+#define GPIO_SIG22_IN_SEL_M  (BIT(7))
+#define GPIO_SIG22_IN_SEL_V  0x1
+#define GPIO_SIG22_IN_SEL_S  7
+/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC22_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_V  0x1
+#define GPIO_FUNC22_IN_INV_SEL_S  6
+/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC22_IN_SEL    0x0000003F
+#define GPIO_FUNC22_IN_SEL_M  ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
+#define GPIO_FUNC22_IN_SEL_V  0x3F
+#define GPIO_FUNC22_IN_SEL_S  0
+
+#define GPIO_FUNC23_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B0)
+/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG23_IN_SEL    (BIT(7))
+#define GPIO_SIG23_IN_SEL_M  (BIT(7))
+#define GPIO_SIG23_IN_SEL_V  0x1
+#define GPIO_SIG23_IN_SEL_S  7
+/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC23_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_V  0x1
+#define GPIO_FUNC23_IN_INV_SEL_S  6
+/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC23_IN_SEL    0x0000003F
+#define GPIO_FUNC23_IN_SEL_M  ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
+#define GPIO_FUNC23_IN_SEL_V  0x3F
+#define GPIO_FUNC23_IN_SEL_S  0
+
+#define GPIO_FUNC24_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B4)
+/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG24_IN_SEL    (BIT(7))
+#define GPIO_SIG24_IN_SEL_M  (BIT(7))
+#define GPIO_SIG24_IN_SEL_V  0x1
+#define GPIO_SIG24_IN_SEL_S  7
+/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC24_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_V  0x1
+#define GPIO_FUNC24_IN_INV_SEL_S  6
+/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC24_IN_SEL    0x0000003F
+#define GPIO_FUNC24_IN_SEL_M  ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
+#define GPIO_FUNC24_IN_SEL_V  0x3F
+#define GPIO_FUNC24_IN_SEL_S  0
+
+#define GPIO_FUNC25_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B8)
+/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG25_IN_SEL    (BIT(7))
+#define GPIO_SIG25_IN_SEL_M  (BIT(7))
+#define GPIO_SIG25_IN_SEL_V  0x1
+#define GPIO_SIG25_IN_SEL_S  7
+/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC25_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_V  0x1
+#define GPIO_FUNC25_IN_INV_SEL_S  6
+/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC25_IN_SEL    0x0000003F
+#define GPIO_FUNC25_IN_SEL_M  ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
+#define GPIO_FUNC25_IN_SEL_V  0x3F
+#define GPIO_FUNC25_IN_SEL_S  0
+
+#define GPIO_FUNC26_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1BC)
+/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG26_IN_SEL    (BIT(7))
+#define GPIO_SIG26_IN_SEL_M  (BIT(7))
+#define GPIO_SIG26_IN_SEL_V  0x1
+#define GPIO_SIG26_IN_SEL_S  7
+/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC26_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_V  0x1
+#define GPIO_FUNC26_IN_INV_SEL_S  6
+/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC26_IN_SEL    0x0000003F
+#define GPIO_FUNC26_IN_SEL_M  ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
+#define GPIO_FUNC26_IN_SEL_V  0x3F
+#define GPIO_FUNC26_IN_SEL_S  0
+
+#define GPIO_FUNC27_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C0)
+/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG27_IN_SEL    (BIT(7))
+#define GPIO_SIG27_IN_SEL_M  (BIT(7))
+#define GPIO_SIG27_IN_SEL_V  0x1
+#define GPIO_SIG27_IN_SEL_S  7
+/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC27_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_V  0x1
+#define GPIO_FUNC27_IN_INV_SEL_S  6
+/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC27_IN_SEL    0x0000003F
+#define GPIO_FUNC27_IN_SEL_M  ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
+#define GPIO_FUNC27_IN_SEL_V  0x3F
+#define GPIO_FUNC27_IN_SEL_S  0
+
+#define GPIO_FUNC28_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C4)
+/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG28_IN_SEL    (BIT(7))
+#define GPIO_SIG28_IN_SEL_M  (BIT(7))
+#define GPIO_SIG28_IN_SEL_V  0x1
+#define GPIO_SIG28_IN_SEL_S  7
+/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC28_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_V  0x1
+#define GPIO_FUNC28_IN_INV_SEL_S  6
+/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC28_IN_SEL    0x0000003F
+#define GPIO_FUNC28_IN_SEL_M  ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
+#define GPIO_FUNC28_IN_SEL_V  0x3F
+#define GPIO_FUNC28_IN_SEL_S  0
+
+#define GPIO_FUNC29_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C8)
+/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG29_IN_SEL    (BIT(7))
+#define GPIO_SIG29_IN_SEL_M  (BIT(7))
+#define GPIO_SIG29_IN_SEL_V  0x1
+#define GPIO_SIG29_IN_SEL_S  7
+/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC29_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_V  0x1
+#define GPIO_FUNC29_IN_INV_SEL_S  6
+/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC29_IN_SEL    0x0000003F
+#define GPIO_FUNC29_IN_SEL_M  ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
+#define GPIO_FUNC29_IN_SEL_V  0x3F
+#define GPIO_FUNC29_IN_SEL_S  0
+
+#define GPIO_FUNC30_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1CC)
+/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG30_IN_SEL    (BIT(7))
+#define GPIO_SIG30_IN_SEL_M  (BIT(7))
+#define GPIO_SIG30_IN_SEL_V  0x1
+#define GPIO_SIG30_IN_SEL_S  7
+/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC30_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_V  0x1
+#define GPIO_FUNC30_IN_INV_SEL_S  6
+/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC30_IN_SEL    0x0000003F
+#define GPIO_FUNC30_IN_SEL_M  ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
+#define GPIO_FUNC30_IN_SEL_V  0x3F
+#define GPIO_FUNC30_IN_SEL_S  0
+
+#define GPIO_FUNC31_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D0)
+/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG31_IN_SEL    (BIT(7))
+#define GPIO_SIG31_IN_SEL_M  (BIT(7))
+#define GPIO_SIG31_IN_SEL_V  0x1
+#define GPIO_SIG31_IN_SEL_S  7
+/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC31_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_V  0x1
+#define GPIO_FUNC31_IN_INV_SEL_S  6
+/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC31_IN_SEL    0x0000003F
+#define GPIO_FUNC31_IN_SEL_M  ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
+#define GPIO_FUNC31_IN_SEL_V  0x3F
+#define GPIO_FUNC31_IN_SEL_S  0
+
+#define GPIO_FUNC32_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D4)
+/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG32_IN_SEL    (BIT(7))
+#define GPIO_SIG32_IN_SEL_M  (BIT(7))
+#define GPIO_SIG32_IN_SEL_V  0x1
+#define GPIO_SIG32_IN_SEL_S  7
+/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC32_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_V  0x1
+#define GPIO_FUNC32_IN_INV_SEL_S  6
+/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC32_IN_SEL    0x0000003F
+#define GPIO_FUNC32_IN_SEL_M  ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
+#define GPIO_FUNC32_IN_SEL_V  0x3F
+#define GPIO_FUNC32_IN_SEL_S  0
+
+#define GPIO_FUNC33_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D8)
+/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG33_IN_SEL    (BIT(7))
+#define GPIO_SIG33_IN_SEL_M  (BIT(7))
+#define GPIO_SIG33_IN_SEL_V  0x1
+#define GPIO_SIG33_IN_SEL_S  7
+/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC33_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_V  0x1
+#define GPIO_FUNC33_IN_INV_SEL_S  6
+/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC33_IN_SEL    0x0000003F
+#define GPIO_FUNC33_IN_SEL_M  ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
+#define GPIO_FUNC33_IN_SEL_V  0x3F
+#define GPIO_FUNC33_IN_SEL_S  0
+
+#define GPIO_FUNC34_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1DC)
+/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG34_IN_SEL    (BIT(7))
+#define GPIO_SIG34_IN_SEL_M  (BIT(7))
+#define GPIO_SIG34_IN_SEL_V  0x1
+#define GPIO_SIG34_IN_SEL_S  7
+/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC34_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_V  0x1
+#define GPIO_FUNC34_IN_INV_SEL_S  6
+/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC34_IN_SEL    0x0000003F
+#define GPIO_FUNC34_IN_SEL_M  ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
+#define GPIO_FUNC34_IN_SEL_V  0x3F
+#define GPIO_FUNC34_IN_SEL_S  0
+
+#define GPIO_FUNC35_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E0)
+/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG35_IN_SEL    (BIT(7))
+#define GPIO_SIG35_IN_SEL_M  (BIT(7))
+#define GPIO_SIG35_IN_SEL_V  0x1
+#define GPIO_SIG35_IN_SEL_S  7
+/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC35_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_V  0x1
+#define GPIO_FUNC35_IN_INV_SEL_S  6
+/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC35_IN_SEL    0x0000003F
+#define GPIO_FUNC35_IN_SEL_M  ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
+#define GPIO_FUNC35_IN_SEL_V  0x3F
+#define GPIO_FUNC35_IN_SEL_S  0
+
+#define GPIO_FUNC36_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E4)
+/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG36_IN_SEL    (BIT(7))
+#define GPIO_SIG36_IN_SEL_M  (BIT(7))
+#define GPIO_SIG36_IN_SEL_V  0x1
+#define GPIO_SIG36_IN_SEL_S  7
+/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC36_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_V  0x1
+#define GPIO_FUNC36_IN_INV_SEL_S  6
+/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC36_IN_SEL    0x0000003F
+#define GPIO_FUNC36_IN_SEL_M  ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
+#define GPIO_FUNC36_IN_SEL_V  0x3F
+#define GPIO_FUNC36_IN_SEL_S  0
+
+#define GPIO_FUNC37_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E8)
+/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG37_IN_SEL    (BIT(7))
+#define GPIO_SIG37_IN_SEL_M  (BIT(7))
+#define GPIO_SIG37_IN_SEL_V  0x1
+#define GPIO_SIG37_IN_SEL_S  7
+/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC37_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_V  0x1
+#define GPIO_FUNC37_IN_INV_SEL_S  6
+/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC37_IN_SEL    0x0000003F
+#define GPIO_FUNC37_IN_SEL_M  ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
+#define GPIO_FUNC37_IN_SEL_V  0x3F
+#define GPIO_FUNC37_IN_SEL_S  0
+
+#define GPIO_FUNC38_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1EC)
+/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG38_IN_SEL    (BIT(7))
+#define GPIO_SIG38_IN_SEL_M  (BIT(7))
+#define GPIO_SIG38_IN_SEL_V  0x1
+#define GPIO_SIG38_IN_SEL_S  7
+/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC38_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_V  0x1
+#define GPIO_FUNC38_IN_INV_SEL_S  6
+/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC38_IN_SEL    0x0000003F
+#define GPIO_FUNC38_IN_SEL_M  ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
+#define GPIO_FUNC38_IN_SEL_V  0x3F
+#define GPIO_FUNC38_IN_SEL_S  0
+
+#define GPIO_FUNC39_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F0)
+/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG39_IN_SEL    (BIT(7))
+#define GPIO_SIG39_IN_SEL_M  (BIT(7))
+#define GPIO_SIG39_IN_SEL_V  0x1
+#define GPIO_SIG39_IN_SEL_S  7
+/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC39_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_V  0x1
+#define GPIO_FUNC39_IN_INV_SEL_S  6
+/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC39_IN_SEL    0x0000003F
+#define GPIO_FUNC39_IN_SEL_M  ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
+#define GPIO_FUNC39_IN_SEL_V  0x3F
+#define GPIO_FUNC39_IN_SEL_S  0
+
+#define GPIO_FUNC40_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F4)
+/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG40_IN_SEL    (BIT(7))
+#define GPIO_SIG40_IN_SEL_M  (BIT(7))
+#define GPIO_SIG40_IN_SEL_V  0x1
+#define GPIO_SIG40_IN_SEL_S  7
+/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC40_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_V  0x1
+#define GPIO_FUNC40_IN_INV_SEL_S  6
+/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC40_IN_SEL    0x0000003F
+#define GPIO_FUNC40_IN_SEL_M  ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
+#define GPIO_FUNC40_IN_SEL_V  0x3F
+#define GPIO_FUNC40_IN_SEL_S  0
+
+#define GPIO_FUNC41_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F8)
+/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG41_IN_SEL    (BIT(7))
+#define GPIO_SIG41_IN_SEL_M  (BIT(7))
+#define GPIO_SIG41_IN_SEL_V  0x1
+#define GPIO_SIG41_IN_SEL_S  7
+/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC41_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_V  0x1
+#define GPIO_FUNC41_IN_INV_SEL_S  6
+/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC41_IN_SEL    0x0000003F
+#define GPIO_FUNC41_IN_SEL_M  ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
+#define GPIO_FUNC41_IN_SEL_V  0x3F
+#define GPIO_FUNC41_IN_SEL_S  0
+
+#define GPIO_FUNC42_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1FC)
+/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG42_IN_SEL    (BIT(7))
+#define GPIO_SIG42_IN_SEL_M  (BIT(7))
+#define GPIO_SIG42_IN_SEL_V  0x1
+#define GPIO_SIG42_IN_SEL_S  7
+/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC42_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_V  0x1
+#define GPIO_FUNC42_IN_INV_SEL_S  6
+/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC42_IN_SEL    0x0000003F
+#define GPIO_FUNC42_IN_SEL_M  ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
+#define GPIO_FUNC42_IN_SEL_V  0x3F
+#define GPIO_FUNC42_IN_SEL_S  0
+
+#define GPIO_FUNC43_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x200)
+/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG43_IN_SEL    (BIT(7))
+#define GPIO_SIG43_IN_SEL_M  (BIT(7))
+#define GPIO_SIG43_IN_SEL_V  0x1
+#define GPIO_SIG43_IN_SEL_S  7
+/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC43_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_V  0x1
+#define GPIO_FUNC43_IN_INV_SEL_S  6
+/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC43_IN_SEL    0x0000003F
+#define GPIO_FUNC43_IN_SEL_M  ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
+#define GPIO_FUNC43_IN_SEL_V  0x3F
+#define GPIO_FUNC43_IN_SEL_S  0
+
+#define GPIO_FUNC44_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x204)
+/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG44_IN_SEL    (BIT(7))
+#define GPIO_SIG44_IN_SEL_M  (BIT(7))
+#define GPIO_SIG44_IN_SEL_V  0x1
+#define GPIO_SIG44_IN_SEL_S  7
+/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC44_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_V  0x1
+#define GPIO_FUNC44_IN_INV_SEL_S  6
+/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC44_IN_SEL    0x0000003F
+#define GPIO_FUNC44_IN_SEL_M  ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
+#define GPIO_FUNC44_IN_SEL_V  0x3F
+#define GPIO_FUNC44_IN_SEL_S  0
+
+#define GPIO_FUNC45_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x208)
+/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG45_IN_SEL    (BIT(7))
+#define GPIO_SIG45_IN_SEL_M  (BIT(7))
+#define GPIO_SIG45_IN_SEL_V  0x1
+#define GPIO_SIG45_IN_SEL_S  7
+/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC45_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_V  0x1
+#define GPIO_FUNC45_IN_INV_SEL_S  6
+/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC45_IN_SEL    0x0000003F
+#define GPIO_FUNC45_IN_SEL_M  ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
+#define GPIO_FUNC45_IN_SEL_V  0x3F
+#define GPIO_FUNC45_IN_SEL_S  0
+
+#define GPIO_FUNC46_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x20C)
+/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG46_IN_SEL    (BIT(7))
+#define GPIO_SIG46_IN_SEL_M  (BIT(7))
+#define GPIO_SIG46_IN_SEL_V  0x1
+#define GPIO_SIG46_IN_SEL_S  7
+/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC46_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC46_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC46_IN_INV_SEL_V  0x1
+#define GPIO_FUNC46_IN_INV_SEL_S  6
+/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC46_IN_SEL    0x0000003F
+#define GPIO_FUNC46_IN_SEL_M  ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
+#define GPIO_FUNC46_IN_SEL_V  0x3F
+#define GPIO_FUNC46_IN_SEL_S  0
+
+#define GPIO_FUNC47_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x210)
+/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG47_IN_SEL    (BIT(7))
+#define GPIO_SIG47_IN_SEL_M  (BIT(7))
+#define GPIO_SIG47_IN_SEL_V  0x1
+#define GPIO_SIG47_IN_SEL_S  7
+/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC47_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_V  0x1
+#define GPIO_FUNC47_IN_INV_SEL_S  6
+/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC47_IN_SEL    0x0000003F
+#define GPIO_FUNC47_IN_SEL_M  ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
+#define GPIO_FUNC47_IN_SEL_V  0x3F
+#define GPIO_FUNC47_IN_SEL_S  0
+
+#define GPIO_FUNC48_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x214)
+/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG48_IN_SEL    (BIT(7))
+#define GPIO_SIG48_IN_SEL_M  (BIT(7))
+#define GPIO_SIG48_IN_SEL_V  0x1
+#define GPIO_SIG48_IN_SEL_S  7
+/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC48_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_V  0x1
+#define GPIO_FUNC48_IN_INV_SEL_S  6
+/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC48_IN_SEL    0x0000003F
+#define GPIO_FUNC48_IN_SEL_M  ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
+#define GPIO_FUNC48_IN_SEL_V  0x3F
+#define GPIO_FUNC48_IN_SEL_S  0
+
+#define GPIO_FUNC49_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x218)
+/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG49_IN_SEL    (BIT(7))
+#define GPIO_SIG49_IN_SEL_M  (BIT(7))
+#define GPIO_SIG49_IN_SEL_V  0x1
+#define GPIO_SIG49_IN_SEL_S  7
+/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC49_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_V  0x1
+#define GPIO_FUNC49_IN_INV_SEL_S  6
+/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC49_IN_SEL    0x0000003F
+#define GPIO_FUNC49_IN_SEL_M  ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
+#define GPIO_FUNC49_IN_SEL_V  0x3F
+#define GPIO_FUNC49_IN_SEL_S  0
+
+#define GPIO_FUNC50_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x21C)
+/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG50_IN_SEL    (BIT(7))
+#define GPIO_SIG50_IN_SEL_M  (BIT(7))
+#define GPIO_SIG50_IN_SEL_V  0x1
+#define GPIO_SIG50_IN_SEL_S  7
+/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC50_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_V  0x1
+#define GPIO_FUNC50_IN_INV_SEL_S  6
+/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC50_IN_SEL    0x0000003F
+#define GPIO_FUNC50_IN_SEL_M  ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
+#define GPIO_FUNC50_IN_SEL_V  0x3F
+#define GPIO_FUNC50_IN_SEL_S  0
+
+#define GPIO_FUNC51_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x220)
+/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG51_IN_SEL    (BIT(7))
+#define GPIO_SIG51_IN_SEL_M  (BIT(7))
+#define GPIO_SIG51_IN_SEL_V  0x1
+#define GPIO_SIG51_IN_SEL_S  7
+/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC51_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_V  0x1
+#define GPIO_FUNC51_IN_INV_SEL_S  6
+/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC51_IN_SEL    0x0000003F
+#define GPIO_FUNC51_IN_SEL_M  ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
+#define GPIO_FUNC51_IN_SEL_V  0x3F
+#define GPIO_FUNC51_IN_SEL_S  0
+
+#define GPIO_FUNC52_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x224)
+/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG52_IN_SEL    (BIT(7))
+#define GPIO_SIG52_IN_SEL_M  (BIT(7))
+#define GPIO_SIG52_IN_SEL_V  0x1
+#define GPIO_SIG52_IN_SEL_S  7
+/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC52_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_V  0x1
+#define GPIO_FUNC52_IN_INV_SEL_S  6
+/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC52_IN_SEL    0x0000003F
+#define GPIO_FUNC52_IN_SEL_M  ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
+#define GPIO_FUNC52_IN_SEL_V  0x3F
+#define GPIO_FUNC52_IN_SEL_S  0
+
+#define GPIO_FUNC53_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x228)
+/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG53_IN_SEL    (BIT(7))
+#define GPIO_SIG53_IN_SEL_M  (BIT(7))
+#define GPIO_SIG53_IN_SEL_V  0x1
+#define GPIO_SIG53_IN_SEL_S  7
+/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC53_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_V  0x1
+#define GPIO_FUNC53_IN_INV_SEL_S  6
+/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC53_IN_SEL    0x0000003F
+#define GPIO_FUNC53_IN_SEL_M  ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
+#define GPIO_FUNC53_IN_SEL_V  0x3F
+#define GPIO_FUNC53_IN_SEL_S  0
+
+#define GPIO_FUNC54_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x22C)
+/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG54_IN_SEL    (BIT(7))
+#define GPIO_SIG54_IN_SEL_M  (BIT(7))
+#define GPIO_SIG54_IN_SEL_V  0x1
+#define GPIO_SIG54_IN_SEL_S  7
+/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC54_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_V  0x1
+#define GPIO_FUNC54_IN_INV_SEL_S  6
+/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC54_IN_SEL    0x0000003F
+#define GPIO_FUNC54_IN_SEL_M  ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
+#define GPIO_FUNC54_IN_SEL_V  0x3F
+#define GPIO_FUNC54_IN_SEL_S  0
+
+#define GPIO_FUNC55_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x230)
+/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG55_IN_SEL    (BIT(7))
+#define GPIO_SIG55_IN_SEL_M  (BIT(7))
+#define GPIO_SIG55_IN_SEL_V  0x1
+#define GPIO_SIG55_IN_SEL_S  7
+/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC55_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_V  0x1
+#define GPIO_FUNC55_IN_INV_SEL_S  6
+/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC55_IN_SEL    0x0000003F
+#define GPIO_FUNC55_IN_SEL_M  ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
+#define GPIO_FUNC55_IN_SEL_V  0x3F
+#define GPIO_FUNC55_IN_SEL_S  0
+
+#define GPIO_FUNC56_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x234)
+/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG56_IN_SEL    (BIT(7))
+#define GPIO_SIG56_IN_SEL_M  (BIT(7))
+#define GPIO_SIG56_IN_SEL_V  0x1
+#define GPIO_SIG56_IN_SEL_S  7
+/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC56_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_V  0x1
+#define GPIO_FUNC56_IN_INV_SEL_S  6
+/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC56_IN_SEL    0x0000003F
+#define GPIO_FUNC56_IN_SEL_M  ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
+#define GPIO_FUNC56_IN_SEL_V  0x3F
+#define GPIO_FUNC56_IN_SEL_S  0
+
+#define GPIO_FUNC57_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x238)
+/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG57_IN_SEL    (BIT(7))
+#define GPIO_SIG57_IN_SEL_M  (BIT(7))
+#define GPIO_SIG57_IN_SEL_V  0x1
+#define GPIO_SIG57_IN_SEL_S  7
+/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC57_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_V  0x1
+#define GPIO_FUNC57_IN_INV_SEL_S  6
+/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC57_IN_SEL    0x0000003F
+#define GPIO_FUNC57_IN_SEL_M  ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
+#define GPIO_FUNC57_IN_SEL_V  0x3F
+#define GPIO_FUNC57_IN_SEL_S  0
+
+#define GPIO_FUNC58_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x23C)
+/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG58_IN_SEL    (BIT(7))
+#define GPIO_SIG58_IN_SEL_M  (BIT(7))
+#define GPIO_SIG58_IN_SEL_V  0x1
+#define GPIO_SIG58_IN_SEL_S  7
+/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC58_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_V  0x1
+#define GPIO_FUNC58_IN_INV_SEL_S  6
+/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC58_IN_SEL    0x0000003F
+#define GPIO_FUNC58_IN_SEL_M  ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
+#define GPIO_FUNC58_IN_SEL_V  0x3F
+#define GPIO_FUNC58_IN_SEL_S  0
+
+#define GPIO_FUNC59_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x240)
+/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG59_IN_SEL    (BIT(7))
+#define GPIO_SIG59_IN_SEL_M  (BIT(7))
+#define GPIO_SIG59_IN_SEL_V  0x1
+#define GPIO_SIG59_IN_SEL_S  7
+/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC59_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_V  0x1
+#define GPIO_FUNC59_IN_INV_SEL_S  6
+/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC59_IN_SEL    0x0000003F
+#define GPIO_FUNC59_IN_SEL_M  ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
+#define GPIO_FUNC59_IN_SEL_V  0x3F
+#define GPIO_FUNC59_IN_SEL_S  0
+
+#define GPIO_FUNC60_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x244)
+/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG60_IN_SEL    (BIT(7))
+#define GPIO_SIG60_IN_SEL_M  (BIT(7))
+#define GPIO_SIG60_IN_SEL_V  0x1
+#define GPIO_SIG60_IN_SEL_S  7
+/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC60_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_V  0x1
+#define GPIO_FUNC60_IN_INV_SEL_S  6
+/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC60_IN_SEL    0x0000003F
+#define GPIO_FUNC60_IN_SEL_M  ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
+#define GPIO_FUNC60_IN_SEL_V  0x3F
+#define GPIO_FUNC60_IN_SEL_S  0
+
+#define GPIO_FUNC61_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x248)
+/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG61_IN_SEL    (BIT(7))
+#define GPIO_SIG61_IN_SEL_M  (BIT(7))
+#define GPIO_SIG61_IN_SEL_V  0x1
+#define GPIO_SIG61_IN_SEL_S  7
+/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC61_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_V  0x1
+#define GPIO_FUNC61_IN_INV_SEL_S  6
+/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC61_IN_SEL    0x0000003F
+#define GPIO_FUNC61_IN_SEL_M  ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
+#define GPIO_FUNC61_IN_SEL_V  0x3F
+#define GPIO_FUNC61_IN_SEL_S  0
+
+#define GPIO_FUNC62_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x24C)
+/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG62_IN_SEL    (BIT(7))
+#define GPIO_SIG62_IN_SEL_M  (BIT(7))
+#define GPIO_SIG62_IN_SEL_V  0x1
+#define GPIO_SIG62_IN_SEL_S  7
+/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC62_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_V  0x1
+#define GPIO_FUNC62_IN_INV_SEL_S  6
+/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC62_IN_SEL    0x0000003F
+#define GPIO_FUNC62_IN_SEL_M  ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
+#define GPIO_FUNC62_IN_SEL_V  0x3F
+#define GPIO_FUNC62_IN_SEL_S  0
+
+#define GPIO_FUNC63_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x250)
+/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG63_IN_SEL    (BIT(7))
+#define GPIO_SIG63_IN_SEL_M  (BIT(7))
+#define GPIO_SIG63_IN_SEL_V  0x1
+#define GPIO_SIG63_IN_SEL_S  7
+/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC63_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_V  0x1
+#define GPIO_FUNC63_IN_INV_SEL_S  6
+/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC63_IN_SEL    0x0000003F
+#define GPIO_FUNC63_IN_SEL_M  ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
+#define GPIO_FUNC63_IN_SEL_V  0x3F
+#define GPIO_FUNC63_IN_SEL_S  0
+
+#define GPIO_FUNC64_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x254)
+/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG64_IN_SEL    (BIT(7))
+#define GPIO_SIG64_IN_SEL_M  (BIT(7))
+#define GPIO_SIG64_IN_SEL_V  0x1
+#define GPIO_SIG64_IN_SEL_S  7
+/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC64_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_V  0x1
+#define GPIO_FUNC64_IN_INV_SEL_S  6
+/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC64_IN_SEL    0x0000003F
+#define GPIO_FUNC64_IN_SEL_M  ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
+#define GPIO_FUNC64_IN_SEL_V  0x3F
+#define GPIO_FUNC64_IN_SEL_S  0
+
+#define GPIO_FUNC65_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x258)
+/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG65_IN_SEL    (BIT(7))
+#define GPIO_SIG65_IN_SEL_M  (BIT(7))
+#define GPIO_SIG65_IN_SEL_V  0x1
+#define GPIO_SIG65_IN_SEL_S  7
+/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC65_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_V  0x1
+#define GPIO_FUNC65_IN_INV_SEL_S  6
+/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC65_IN_SEL    0x0000003F
+#define GPIO_FUNC65_IN_SEL_M  ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
+#define GPIO_FUNC65_IN_SEL_V  0x3F
+#define GPIO_FUNC65_IN_SEL_S  0
+
+#define GPIO_FUNC66_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x25C)
+/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG66_IN_SEL    (BIT(7))
+#define GPIO_SIG66_IN_SEL_M  (BIT(7))
+#define GPIO_SIG66_IN_SEL_V  0x1
+#define GPIO_SIG66_IN_SEL_S  7
+/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC66_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_V  0x1
+#define GPIO_FUNC66_IN_INV_SEL_S  6
+/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC66_IN_SEL    0x0000003F
+#define GPIO_FUNC66_IN_SEL_M  ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
+#define GPIO_FUNC66_IN_SEL_V  0x3F
+#define GPIO_FUNC66_IN_SEL_S  0
+
+#define GPIO_FUNC67_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x260)
+/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG67_IN_SEL    (BIT(7))
+#define GPIO_SIG67_IN_SEL_M  (BIT(7))
+#define GPIO_SIG67_IN_SEL_V  0x1
+#define GPIO_SIG67_IN_SEL_S  7
+/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC67_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC67_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC67_IN_INV_SEL_V  0x1
+#define GPIO_FUNC67_IN_INV_SEL_S  6
+/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC67_IN_SEL    0x0000003F
+#define GPIO_FUNC67_IN_SEL_M  ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
+#define GPIO_FUNC67_IN_SEL_V  0x3F
+#define GPIO_FUNC67_IN_SEL_S  0
+
+#define GPIO_FUNC68_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x264)
+/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG68_IN_SEL    (BIT(7))
+#define GPIO_SIG68_IN_SEL_M  (BIT(7))
+#define GPIO_SIG68_IN_SEL_V  0x1
+#define GPIO_SIG68_IN_SEL_S  7
+/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC68_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_V  0x1
+#define GPIO_FUNC68_IN_INV_SEL_S  6
+/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC68_IN_SEL    0x0000003F
+#define GPIO_FUNC68_IN_SEL_M  ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
+#define GPIO_FUNC68_IN_SEL_V  0x3F
+#define GPIO_FUNC68_IN_SEL_S  0
+
+#define GPIO_FUNC69_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x268)
+/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG69_IN_SEL    (BIT(7))
+#define GPIO_SIG69_IN_SEL_M  (BIT(7))
+#define GPIO_SIG69_IN_SEL_V  0x1
+#define GPIO_SIG69_IN_SEL_S  7
+/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC69_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_V  0x1
+#define GPIO_FUNC69_IN_INV_SEL_S  6
+/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC69_IN_SEL    0x0000003F
+#define GPIO_FUNC69_IN_SEL_M  ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
+#define GPIO_FUNC69_IN_SEL_V  0x3F
+#define GPIO_FUNC69_IN_SEL_S  0
+
+#define GPIO_FUNC70_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x26C)
+/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG70_IN_SEL    (BIT(7))
+#define GPIO_SIG70_IN_SEL_M  (BIT(7))
+#define GPIO_SIG70_IN_SEL_V  0x1
+#define GPIO_SIG70_IN_SEL_S  7
+/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC70_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_V  0x1
+#define GPIO_FUNC70_IN_INV_SEL_S  6
+/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC70_IN_SEL    0x0000003F
+#define GPIO_FUNC70_IN_SEL_M  ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
+#define GPIO_FUNC70_IN_SEL_V  0x3F
+#define GPIO_FUNC70_IN_SEL_S  0
+
+#define GPIO_FUNC71_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x270)
+/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG71_IN_SEL    (BIT(7))
+#define GPIO_SIG71_IN_SEL_M  (BIT(7))
+#define GPIO_SIG71_IN_SEL_V  0x1
+#define GPIO_SIG71_IN_SEL_S  7
+/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC71_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_V  0x1
+#define GPIO_FUNC71_IN_INV_SEL_S  6
+/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC71_IN_SEL    0x0000003F
+#define GPIO_FUNC71_IN_SEL_M  ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
+#define GPIO_FUNC71_IN_SEL_V  0x3F
+#define GPIO_FUNC71_IN_SEL_S  0
+
+#define GPIO_FUNC72_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x274)
+/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG72_IN_SEL    (BIT(7))
+#define GPIO_SIG72_IN_SEL_M  (BIT(7))
+#define GPIO_SIG72_IN_SEL_V  0x1
+#define GPIO_SIG72_IN_SEL_S  7
+/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC72_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC72_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC72_IN_INV_SEL_V  0x1
+#define GPIO_FUNC72_IN_INV_SEL_S  6
+/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC72_IN_SEL    0x0000003F
+#define GPIO_FUNC72_IN_SEL_M  ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
+#define GPIO_FUNC72_IN_SEL_V  0x3F
+#define GPIO_FUNC72_IN_SEL_S  0
+
+#define GPIO_FUNC73_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x278)
+/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG73_IN_SEL    (BIT(7))
+#define GPIO_SIG73_IN_SEL_M  (BIT(7))
+#define GPIO_SIG73_IN_SEL_V  0x1
+#define GPIO_SIG73_IN_SEL_S  7
+/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC73_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC73_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC73_IN_INV_SEL_V  0x1
+#define GPIO_FUNC73_IN_INV_SEL_S  6
+/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC73_IN_SEL    0x0000003F
+#define GPIO_FUNC73_IN_SEL_M  ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
+#define GPIO_FUNC73_IN_SEL_V  0x3F
+#define GPIO_FUNC73_IN_SEL_S  0
+
+#define GPIO_FUNC74_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x27C)
+/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG74_IN_SEL    (BIT(7))
+#define GPIO_SIG74_IN_SEL_M  (BIT(7))
+#define GPIO_SIG74_IN_SEL_V  0x1
+#define GPIO_SIG74_IN_SEL_S  7
+/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC74_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_V  0x1
+#define GPIO_FUNC74_IN_INV_SEL_S  6
+/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC74_IN_SEL    0x0000003F
+#define GPIO_FUNC74_IN_SEL_M  ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
+#define GPIO_FUNC74_IN_SEL_V  0x3F
+#define GPIO_FUNC74_IN_SEL_S  0
+
+#define GPIO_FUNC75_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x280)
+/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG75_IN_SEL    (BIT(7))
+#define GPIO_SIG75_IN_SEL_M  (BIT(7))
+#define GPIO_SIG75_IN_SEL_V  0x1
+#define GPIO_SIG75_IN_SEL_S  7
+/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC75_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_V  0x1
+#define GPIO_FUNC75_IN_INV_SEL_S  6
+/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC75_IN_SEL    0x0000003F
+#define GPIO_FUNC75_IN_SEL_M  ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
+#define GPIO_FUNC75_IN_SEL_V  0x3F
+#define GPIO_FUNC75_IN_SEL_S  0
+
+#define GPIO_FUNC76_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x284)
+/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG76_IN_SEL    (BIT(7))
+#define GPIO_SIG76_IN_SEL_M  (BIT(7))
+#define GPIO_SIG76_IN_SEL_V  0x1
+#define GPIO_SIG76_IN_SEL_S  7
+/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC76_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_V  0x1
+#define GPIO_FUNC76_IN_INV_SEL_S  6
+/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC76_IN_SEL    0x0000003F
+#define GPIO_FUNC76_IN_SEL_M  ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
+#define GPIO_FUNC76_IN_SEL_V  0x3F
+#define GPIO_FUNC76_IN_SEL_S  0
+
+#define GPIO_FUNC77_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x288)
+/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG77_IN_SEL    (BIT(7))
+#define GPIO_SIG77_IN_SEL_M  (BIT(7))
+#define GPIO_SIG77_IN_SEL_V  0x1
+#define GPIO_SIG77_IN_SEL_S  7
+/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC77_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_V  0x1
+#define GPIO_FUNC77_IN_INV_SEL_S  6
+/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC77_IN_SEL    0x0000003F
+#define GPIO_FUNC77_IN_SEL_M  ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
+#define GPIO_FUNC77_IN_SEL_V  0x3F
+#define GPIO_FUNC77_IN_SEL_S  0
+
+#define GPIO_FUNC78_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x28C)
+/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG78_IN_SEL    (BIT(7))
+#define GPIO_SIG78_IN_SEL_M  (BIT(7))
+#define GPIO_SIG78_IN_SEL_V  0x1
+#define GPIO_SIG78_IN_SEL_S  7
+/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC78_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_V  0x1
+#define GPIO_FUNC78_IN_INV_SEL_S  6
+/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC78_IN_SEL    0x0000003F
+#define GPIO_FUNC78_IN_SEL_M  ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
+#define GPIO_FUNC78_IN_SEL_V  0x3F
+#define GPIO_FUNC78_IN_SEL_S  0
+
+#define GPIO_FUNC79_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x290)
+/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG79_IN_SEL    (BIT(7))
+#define GPIO_SIG79_IN_SEL_M  (BIT(7))
+#define GPIO_SIG79_IN_SEL_V  0x1
+#define GPIO_SIG79_IN_SEL_S  7
+/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC79_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC79_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC79_IN_INV_SEL_V  0x1
+#define GPIO_FUNC79_IN_INV_SEL_S  6
+/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC79_IN_SEL    0x0000003F
+#define GPIO_FUNC79_IN_SEL_M  ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
+#define GPIO_FUNC79_IN_SEL_V  0x3F
+#define GPIO_FUNC79_IN_SEL_S  0
+
+#define GPIO_FUNC80_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x294)
+/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG80_IN_SEL    (BIT(7))
+#define GPIO_SIG80_IN_SEL_M  (BIT(7))
+#define GPIO_SIG80_IN_SEL_V  0x1
+#define GPIO_SIG80_IN_SEL_S  7
+/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC80_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_V  0x1
+#define GPIO_FUNC80_IN_INV_SEL_S  6
+/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC80_IN_SEL    0x0000003F
+#define GPIO_FUNC80_IN_SEL_M  ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
+#define GPIO_FUNC80_IN_SEL_V  0x3F
+#define GPIO_FUNC80_IN_SEL_S  0
+
+#define GPIO_FUNC81_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x298)
+/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG81_IN_SEL    (BIT(7))
+#define GPIO_SIG81_IN_SEL_M  (BIT(7))
+#define GPIO_SIG81_IN_SEL_V  0x1
+#define GPIO_SIG81_IN_SEL_S  7
+/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC81_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC81_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC81_IN_INV_SEL_V  0x1
+#define GPIO_FUNC81_IN_INV_SEL_S  6
+/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC81_IN_SEL    0x0000003F
+#define GPIO_FUNC81_IN_SEL_M  ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
+#define GPIO_FUNC81_IN_SEL_V  0x3F
+#define GPIO_FUNC81_IN_SEL_S  0
+
+#define GPIO_FUNC82_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x29C)
+/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG82_IN_SEL    (BIT(7))
+#define GPIO_SIG82_IN_SEL_M  (BIT(7))
+#define GPIO_SIG82_IN_SEL_V  0x1
+#define GPIO_SIG82_IN_SEL_S  7
+/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC82_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC82_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC82_IN_INV_SEL_V  0x1
+#define GPIO_FUNC82_IN_INV_SEL_S  6
+/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC82_IN_SEL    0x0000003F
+#define GPIO_FUNC82_IN_SEL_M  ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
+#define GPIO_FUNC82_IN_SEL_V  0x3F
+#define GPIO_FUNC82_IN_SEL_S  0
+
+#define GPIO_FUNC83_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A0)
+/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG83_IN_SEL    (BIT(7))
+#define GPIO_SIG83_IN_SEL_M  (BIT(7))
+#define GPIO_SIG83_IN_SEL_V  0x1
+#define GPIO_SIG83_IN_SEL_S  7
+/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC83_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_V  0x1
+#define GPIO_FUNC83_IN_INV_SEL_S  6
+/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC83_IN_SEL    0x0000003F
+#define GPIO_FUNC83_IN_SEL_M  ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
+#define GPIO_FUNC83_IN_SEL_V  0x3F
+#define GPIO_FUNC83_IN_SEL_S  0
+
+#define GPIO_FUNC84_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A4)
+/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG84_IN_SEL    (BIT(7))
+#define GPIO_SIG84_IN_SEL_M  (BIT(7))
+#define GPIO_SIG84_IN_SEL_V  0x1
+#define GPIO_SIG84_IN_SEL_S  7
+/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC84_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC84_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC84_IN_INV_SEL_V  0x1
+#define GPIO_FUNC84_IN_INV_SEL_S  6
+/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC84_IN_SEL    0x0000003F
+#define GPIO_FUNC84_IN_SEL_M  ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
+#define GPIO_FUNC84_IN_SEL_V  0x3F
+#define GPIO_FUNC84_IN_SEL_S  0
+
+#define GPIO_FUNC85_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A8)
+/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG85_IN_SEL    (BIT(7))
+#define GPIO_SIG85_IN_SEL_M  (BIT(7))
+#define GPIO_SIG85_IN_SEL_V  0x1
+#define GPIO_SIG85_IN_SEL_S  7
+/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC85_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC85_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC85_IN_INV_SEL_V  0x1
+#define GPIO_FUNC85_IN_INV_SEL_S  6
+/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC85_IN_SEL    0x0000003F
+#define GPIO_FUNC85_IN_SEL_M  ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
+#define GPIO_FUNC85_IN_SEL_V  0x3F
+#define GPIO_FUNC85_IN_SEL_S  0
+
+#define GPIO_FUNC86_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2AC)
+/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG86_IN_SEL    (BIT(7))
+#define GPIO_SIG86_IN_SEL_M  (BIT(7))
+#define GPIO_SIG86_IN_SEL_V  0x1
+#define GPIO_SIG86_IN_SEL_S  7
+/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC86_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_V  0x1
+#define GPIO_FUNC86_IN_INV_SEL_S  6
+/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC86_IN_SEL    0x0000003F
+#define GPIO_FUNC86_IN_SEL_M  ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
+#define GPIO_FUNC86_IN_SEL_V  0x3F
+#define GPIO_FUNC86_IN_SEL_S  0
+
+#define GPIO_FUNC87_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B0)
+/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG87_IN_SEL    (BIT(7))
+#define GPIO_SIG87_IN_SEL_M  (BIT(7))
+#define GPIO_SIG87_IN_SEL_V  0x1
+#define GPIO_SIG87_IN_SEL_S  7
+/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC87_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC87_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC87_IN_INV_SEL_V  0x1
+#define GPIO_FUNC87_IN_INV_SEL_S  6
+/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC87_IN_SEL    0x0000003F
+#define GPIO_FUNC87_IN_SEL_M  ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
+#define GPIO_FUNC87_IN_SEL_V  0x3F
+#define GPIO_FUNC87_IN_SEL_S  0
+
+#define GPIO_FUNC88_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B4)
+/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG88_IN_SEL    (BIT(7))
+#define GPIO_SIG88_IN_SEL_M  (BIT(7))
+#define GPIO_SIG88_IN_SEL_V  0x1
+#define GPIO_SIG88_IN_SEL_S  7
+/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC88_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC88_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC88_IN_INV_SEL_V  0x1
+#define GPIO_FUNC88_IN_INV_SEL_S  6
+/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC88_IN_SEL    0x0000003F
+#define GPIO_FUNC88_IN_SEL_M  ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
+#define GPIO_FUNC88_IN_SEL_V  0x3F
+#define GPIO_FUNC88_IN_SEL_S  0
+
+#define GPIO_FUNC89_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B8)
+/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG89_IN_SEL    (BIT(7))
+#define GPIO_SIG89_IN_SEL_M  (BIT(7))
+#define GPIO_SIG89_IN_SEL_V  0x1
+#define GPIO_SIG89_IN_SEL_S  7
+/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC89_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_V  0x1
+#define GPIO_FUNC89_IN_INV_SEL_S  6
+/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC89_IN_SEL    0x0000003F
+#define GPIO_FUNC89_IN_SEL_M  ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
+#define GPIO_FUNC89_IN_SEL_V  0x3F
+#define GPIO_FUNC89_IN_SEL_S  0
+
+#define GPIO_FUNC90_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2BC)
+/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG90_IN_SEL    (BIT(7))
+#define GPIO_SIG90_IN_SEL_M  (BIT(7))
+#define GPIO_SIG90_IN_SEL_V  0x1
+#define GPIO_SIG90_IN_SEL_S  7
+/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC90_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_V  0x1
+#define GPIO_FUNC90_IN_INV_SEL_S  6
+/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC90_IN_SEL    0x0000003F
+#define GPIO_FUNC90_IN_SEL_M  ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
+#define GPIO_FUNC90_IN_SEL_V  0x3F
+#define GPIO_FUNC90_IN_SEL_S  0
+
+#define GPIO_FUNC91_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C0)
+/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG91_IN_SEL    (BIT(7))
+#define GPIO_SIG91_IN_SEL_M  (BIT(7))
+#define GPIO_SIG91_IN_SEL_V  0x1
+#define GPIO_SIG91_IN_SEL_S  7
+/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC91_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_V  0x1
+#define GPIO_FUNC91_IN_INV_SEL_S  6
+/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC91_IN_SEL    0x0000003F
+#define GPIO_FUNC91_IN_SEL_M  ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
+#define GPIO_FUNC91_IN_SEL_V  0x3F
+#define GPIO_FUNC91_IN_SEL_S  0
+
+#define GPIO_FUNC92_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C4)
+/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG92_IN_SEL    (BIT(7))
+#define GPIO_SIG92_IN_SEL_M  (BIT(7))
+#define GPIO_SIG92_IN_SEL_V  0x1
+#define GPIO_SIG92_IN_SEL_S  7
+/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC92_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_V  0x1
+#define GPIO_FUNC92_IN_INV_SEL_S  6
+/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC92_IN_SEL    0x0000003F
+#define GPIO_FUNC92_IN_SEL_M  ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
+#define GPIO_FUNC92_IN_SEL_V  0x3F
+#define GPIO_FUNC92_IN_SEL_S  0
+
+#define GPIO_FUNC93_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C8)
+/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG93_IN_SEL    (BIT(7))
+#define GPIO_SIG93_IN_SEL_M  (BIT(7))
+#define GPIO_SIG93_IN_SEL_V  0x1
+#define GPIO_SIG93_IN_SEL_S  7
+/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC93_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_V  0x1
+#define GPIO_FUNC93_IN_INV_SEL_S  6
+/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC93_IN_SEL    0x0000003F
+#define GPIO_FUNC93_IN_SEL_M  ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
+#define GPIO_FUNC93_IN_SEL_V  0x3F
+#define GPIO_FUNC93_IN_SEL_S  0
+
+#define GPIO_FUNC94_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2CC)
+/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG94_IN_SEL    (BIT(7))
+#define GPIO_SIG94_IN_SEL_M  (BIT(7))
+#define GPIO_SIG94_IN_SEL_V  0x1
+#define GPIO_SIG94_IN_SEL_S  7
+/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC94_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_V  0x1
+#define GPIO_FUNC94_IN_INV_SEL_S  6
+/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC94_IN_SEL    0x0000003F
+#define GPIO_FUNC94_IN_SEL_M  ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
+#define GPIO_FUNC94_IN_SEL_V  0x3F
+#define GPIO_FUNC94_IN_SEL_S  0
+
+#define GPIO_FUNC95_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D0)
+/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG95_IN_SEL    (BIT(7))
+#define GPIO_SIG95_IN_SEL_M  (BIT(7))
+#define GPIO_SIG95_IN_SEL_V  0x1
+#define GPIO_SIG95_IN_SEL_S  7
+/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC95_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_V  0x1
+#define GPIO_FUNC95_IN_INV_SEL_S  6
+/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC95_IN_SEL    0x0000003F
+#define GPIO_FUNC95_IN_SEL_M  ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
+#define GPIO_FUNC95_IN_SEL_V  0x3F
+#define GPIO_FUNC95_IN_SEL_S  0
+
+#define GPIO_FUNC96_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D4)
+/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG96_IN_SEL    (BIT(7))
+#define GPIO_SIG96_IN_SEL_M  (BIT(7))
+#define GPIO_SIG96_IN_SEL_V  0x1
+#define GPIO_SIG96_IN_SEL_S  7
+/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC96_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_V  0x1
+#define GPIO_FUNC96_IN_INV_SEL_S  6
+/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC96_IN_SEL    0x0000003F
+#define GPIO_FUNC96_IN_SEL_M  ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
+#define GPIO_FUNC96_IN_SEL_V  0x3F
+#define GPIO_FUNC96_IN_SEL_S  0
+
+#define GPIO_FUNC97_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D8)
+/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG97_IN_SEL    (BIT(7))
+#define GPIO_SIG97_IN_SEL_M  (BIT(7))
+#define GPIO_SIG97_IN_SEL_V  0x1
+#define GPIO_SIG97_IN_SEL_S  7
+/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC97_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_V  0x1
+#define GPIO_FUNC97_IN_INV_SEL_S  6
+/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC97_IN_SEL    0x0000003F
+#define GPIO_FUNC97_IN_SEL_M  ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
+#define GPIO_FUNC97_IN_SEL_V  0x3F
+#define GPIO_FUNC97_IN_SEL_S  0
+
+#define GPIO_FUNC98_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2DC)
+/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG98_IN_SEL    (BIT(7))
+#define GPIO_SIG98_IN_SEL_M  (BIT(7))
+#define GPIO_SIG98_IN_SEL_V  0x1
+#define GPIO_SIG98_IN_SEL_S  7
+/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC98_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_V  0x1
+#define GPIO_FUNC98_IN_INV_SEL_S  6
+/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC98_IN_SEL    0x0000003F
+#define GPIO_FUNC98_IN_SEL_M  ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
+#define GPIO_FUNC98_IN_SEL_V  0x3F
+#define GPIO_FUNC98_IN_SEL_S  0
+
+#define GPIO_FUNC99_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E0)
+/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG99_IN_SEL    (BIT(7))
+#define GPIO_SIG99_IN_SEL_M  (BIT(7))
+#define GPIO_SIG99_IN_SEL_V  0x1
+#define GPIO_SIG99_IN_SEL_S  7
+/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC99_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_V  0x1
+#define GPIO_FUNC99_IN_INV_SEL_S  6
+/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC99_IN_SEL    0x0000003F
+#define GPIO_FUNC99_IN_SEL_M  ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
+#define GPIO_FUNC99_IN_SEL_V  0x3F
+#define GPIO_FUNC99_IN_SEL_S  0
+
+#define GPIO_FUNC100_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E4)
+/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG100_IN_SEL    (BIT(7))
+#define GPIO_SIG100_IN_SEL_M  (BIT(7))
+#define GPIO_SIG100_IN_SEL_V  0x1
+#define GPIO_SIG100_IN_SEL_S  7
+/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC100_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_V  0x1
+#define GPIO_FUNC100_IN_INV_SEL_S  6
+/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC100_IN_SEL    0x0000003F
+#define GPIO_FUNC100_IN_SEL_M  ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
+#define GPIO_FUNC100_IN_SEL_V  0x3F
+#define GPIO_FUNC100_IN_SEL_S  0
+
+#define GPIO_FUNC101_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E8)
+/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG101_IN_SEL    (BIT(7))
+#define GPIO_SIG101_IN_SEL_M  (BIT(7))
+#define GPIO_SIG101_IN_SEL_V  0x1
+#define GPIO_SIG101_IN_SEL_S  7
+/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC101_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_V  0x1
+#define GPIO_FUNC101_IN_INV_SEL_S  6
+/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC101_IN_SEL    0x0000003F
+#define GPIO_FUNC101_IN_SEL_M  ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
+#define GPIO_FUNC101_IN_SEL_V  0x3F
+#define GPIO_FUNC101_IN_SEL_S  0
+
+#define GPIO_FUNC102_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2EC)
+/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG102_IN_SEL    (BIT(7))
+#define GPIO_SIG102_IN_SEL_M  (BIT(7))
+#define GPIO_SIG102_IN_SEL_V  0x1
+#define GPIO_SIG102_IN_SEL_S  7
+/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC102_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_V  0x1
+#define GPIO_FUNC102_IN_INV_SEL_S  6
+/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC102_IN_SEL    0x0000003F
+#define GPIO_FUNC102_IN_SEL_M  ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
+#define GPIO_FUNC102_IN_SEL_V  0x3F
+#define GPIO_FUNC102_IN_SEL_S  0
+
+#define GPIO_FUNC103_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F0)
+/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG103_IN_SEL    (BIT(7))
+#define GPIO_SIG103_IN_SEL_M  (BIT(7))
+#define GPIO_SIG103_IN_SEL_V  0x1
+#define GPIO_SIG103_IN_SEL_S  7
+/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC103_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_V  0x1
+#define GPIO_FUNC103_IN_INV_SEL_S  6
+/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC103_IN_SEL    0x0000003F
+#define GPIO_FUNC103_IN_SEL_M  ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
+#define GPIO_FUNC103_IN_SEL_V  0x3F
+#define GPIO_FUNC103_IN_SEL_S  0
+
+#define GPIO_FUNC104_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F4)
+/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG104_IN_SEL    (BIT(7))
+#define GPIO_SIG104_IN_SEL_M  (BIT(7))
+#define GPIO_SIG104_IN_SEL_V  0x1
+#define GPIO_SIG104_IN_SEL_S  7
+/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC104_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_V  0x1
+#define GPIO_FUNC104_IN_INV_SEL_S  6
+/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC104_IN_SEL    0x0000003F
+#define GPIO_FUNC104_IN_SEL_M  ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
+#define GPIO_FUNC104_IN_SEL_V  0x3F
+#define GPIO_FUNC104_IN_SEL_S  0
+
+#define GPIO_FUNC105_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F8)
+/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG105_IN_SEL    (BIT(7))
+#define GPIO_SIG105_IN_SEL_M  (BIT(7))
+#define GPIO_SIG105_IN_SEL_V  0x1
+#define GPIO_SIG105_IN_SEL_S  7
+/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC105_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_V  0x1
+#define GPIO_FUNC105_IN_INV_SEL_S  6
+/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC105_IN_SEL    0x0000003F
+#define GPIO_FUNC105_IN_SEL_M  ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
+#define GPIO_FUNC105_IN_SEL_V  0x3F
+#define GPIO_FUNC105_IN_SEL_S  0
+
+#define GPIO_FUNC106_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2FC)
+/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG106_IN_SEL    (BIT(7))
+#define GPIO_SIG106_IN_SEL_M  (BIT(7))
+#define GPIO_SIG106_IN_SEL_V  0x1
+#define GPIO_SIG106_IN_SEL_S  7
+/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC106_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_V  0x1
+#define GPIO_FUNC106_IN_INV_SEL_S  6
+/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC106_IN_SEL    0x0000003F
+#define GPIO_FUNC106_IN_SEL_M  ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
+#define GPIO_FUNC106_IN_SEL_V  0x3F
+#define GPIO_FUNC106_IN_SEL_S  0
+
+#define GPIO_FUNC107_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x300)
+/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG107_IN_SEL    (BIT(7))
+#define GPIO_SIG107_IN_SEL_M  (BIT(7))
+#define GPIO_SIG107_IN_SEL_V  0x1
+#define GPIO_SIG107_IN_SEL_S  7
+/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC107_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_V  0x1
+#define GPIO_FUNC107_IN_INV_SEL_S  6
+/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC107_IN_SEL    0x0000003F
+#define GPIO_FUNC107_IN_SEL_M  ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
+#define GPIO_FUNC107_IN_SEL_V  0x3F
+#define GPIO_FUNC107_IN_SEL_S  0
+
+#define GPIO_FUNC108_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x304)
+/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG108_IN_SEL    (BIT(7))
+#define GPIO_SIG108_IN_SEL_M  (BIT(7))
+#define GPIO_SIG108_IN_SEL_V  0x1
+#define GPIO_SIG108_IN_SEL_S  7
+/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC108_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_V  0x1
+#define GPIO_FUNC108_IN_INV_SEL_S  6
+/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC108_IN_SEL    0x0000003F
+#define GPIO_FUNC108_IN_SEL_M  ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
+#define GPIO_FUNC108_IN_SEL_V  0x3F
+#define GPIO_FUNC108_IN_SEL_S  0
+
+#define GPIO_FUNC109_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x308)
+/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG109_IN_SEL    (BIT(7))
+#define GPIO_SIG109_IN_SEL_M  (BIT(7))
+#define GPIO_SIG109_IN_SEL_V  0x1
+#define GPIO_SIG109_IN_SEL_S  7
+/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC109_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_V  0x1
+#define GPIO_FUNC109_IN_INV_SEL_S  6
+/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC109_IN_SEL    0x0000003F
+#define GPIO_FUNC109_IN_SEL_M  ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
+#define GPIO_FUNC109_IN_SEL_V  0x3F
+#define GPIO_FUNC109_IN_SEL_S  0
+
+#define GPIO_FUNC110_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x30C)
+/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG110_IN_SEL    (BIT(7))
+#define GPIO_SIG110_IN_SEL_M  (BIT(7))
+#define GPIO_SIG110_IN_SEL_V  0x1
+#define GPIO_SIG110_IN_SEL_S  7
+/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC110_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_V  0x1
+#define GPIO_FUNC110_IN_INV_SEL_S  6
+/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC110_IN_SEL    0x0000003F
+#define GPIO_FUNC110_IN_SEL_M  ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
+#define GPIO_FUNC110_IN_SEL_V  0x3F
+#define GPIO_FUNC110_IN_SEL_S  0
+
+#define GPIO_FUNC111_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x310)
+/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG111_IN_SEL    (BIT(7))
+#define GPIO_SIG111_IN_SEL_M  (BIT(7))
+#define GPIO_SIG111_IN_SEL_V  0x1
+#define GPIO_SIG111_IN_SEL_S  7
+/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC111_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_V  0x1
+#define GPIO_FUNC111_IN_INV_SEL_S  6
+/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC111_IN_SEL    0x0000003F
+#define GPIO_FUNC111_IN_SEL_M  ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
+#define GPIO_FUNC111_IN_SEL_V  0x3F
+#define GPIO_FUNC111_IN_SEL_S  0
+
+#define GPIO_FUNC112_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x314)
+/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG112_IN_SEL    (BIT(7))
+#define GPIO_SIG112_IN_SEL_M  (BIT(7))
+#define GPIO_SIG112_IN_SEL_V  0x1
+#define GPIO_SIG112_IN_SEL_S  7
+/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC112_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_V  0x1
+#define GPIO_FUNC112_IN_INV_SEL_S  6
+/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC112_IN_SEL    0x0000003F
+#define GPIO_FUNC112_IN_SEL_M  ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
+#define GPIO_FUNC112_IN_SEL_V  0x3F
+#define GPIO_FUNC112_IN_SEL_S  0
+
+#define GPIO_FUNC113_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x318)
+/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG113_IN_SEL    (BIT(7))
+#define GPIO_SIG113_IN_SEL_M  (BIT(7))
+#define GPIO_SIG113_IN_SEL_V  0x1
+#define GPIO_SIG113_IN_SEL_S  7
+/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC113_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_V  0x1
+#define GPIO_FUNC113_IN_INV_SEL_S  6
+/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC113_IN_SEL    0x0000003F
+#define GPIO_FUNC113_IN_SEL_M  ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
+#define GPIO_FUNC113_IN_SEL_V  0x3F
+#define GPIO_FUNC113_IN_SEL_S  0
+
+#define GPIO_FUNC114_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x31C)
+/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG114_IN_SEL    (BIT(7))
+#define GPIO_SIG114_IN_SEL_M  (BIT(7))
+#define GPIO_SIG114_IN_SEL_V  0x1
+#define GPIO_SIG114_IN_SEL_S  7
+/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC114_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_V  0x1
+#define GPIO_FUNC114_IN_INV_SEL_S  6
+/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC114_IN_SEL    0x0000003F
+#define GPIO_FUNC114_IN_SEL_M  ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
+#define GPIO_FUNC114_IN_SEL_V  0x3F
+#define GPIO_FUNC114_IN_SEL_S  0
+
+#define GPIO_FUNC115_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x320)
+/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG115_IN_SEL    (BIT(7))
+#define GPIO_SIG115_IN_SEL_M  (BIT(7))
+#define GPIO_SIG115_IN_SEL_V  0x1
+#define GPIO_SIG115_IN_SEL_S  7
+/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC115_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC115_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC115_IN_INV_SEL_V  0x1
+#define GPIO_FUNC115_IN_INV_SEL_S  6
+/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC115_IN_SEL    0x0000003F
+#define GPIO_FUNC115_IN_SEL_M  ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
+#define GPIO_FUNC115_IN_SEL_V  0x3F
+#define GPIO_FUNC115_IN_SEL_S  0
+
+#define GPIO_FUNC116_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x324)
+/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG116_IN_SEL    (BIT(7))
+#define GPIO_SIG116_IN_SEL_M  (BIT(7))
+#define GPIO_SIG116_IN_SEL_V  0x1
+#define GPIO_SIG116_IN_SEL_S  7
+/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC116_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC116_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC116_IN_INV_SEL_V  0x1
+#define GPIO_FUNC116_IN_INV_SEL_S  6
+/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC116_IN_SEL    0x0000003F
+#define GPIO_FUNC116_IN_SEL_M  ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
+#define GPIO_FUNC116_IN_SEL_V  0x3F
+#define GPIO_FUNC116_IN_SEL_S  0
+
+#define GPIO_FUNC117_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x328)
+/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG117_IN_SEL    (BIT(7))
+#define GPIO_SIG117_IN_SEL_M  (BIT(7))
+#define GPIO_SIG117_IN_SEL_V  0x1
+#define GPIO_SIG117_IN_SEL_S  7
+/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC117_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_V  0x1
+#define GPIO_FUNC117_IN_INV_SEL_S  6
+/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC117_IN_SEL    0x0000003F
+#define GPIO_FUNC117_IN_SEL_M  ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
+#define GPIO_FUNC117_IN_SEL_V  0x3F
+#define GPIO_FUNC117_IN_SEL_S  0
+
+#define GPIO_FUNC118_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x32C)
+/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG118_IN_SEL    (BIT(7))
+#define GPIO_SIG118_IN_SEL_M  (BIT(7))
+#define GPIO_SIG118_IN_SEL_V  0x1
+#define GPIO_SIG118_IN_SEL_S  7
+/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC118_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_V  0x1
+#define GPIO_FUNC118_IN_INV_SEL_S  6
+/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC118_IN_SEL    0x0000003F
+#define GPIO_FUNC118_IN_SEL_M  ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
+#define GPIO_FUNC118_IN_SEL_V  0x3F
+#define GPIO_FUNC118_IN_SEL_S  0
+
+#define GPIO_FUNC119_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x330)
+/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG119_IN_SEL    (BIT(7))
+#define GPIO_SIG119_IN_SEL_M  (BIT(7))
+#define GPIO_SIG119_IN_SEL_V  0x1
+#define GPIO_SIG119_IN_SEL_S  7
+/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC119_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC119_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC119_IN_INV_SEL_V  0x1
+#define GPIO_FUNC119_IN_INV_SEL_S  6
+/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC119_IN_SEL    0x0000003F
+#define GPIO_FUNC119_IN_SEL_M  ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
+#define GPIO_FUNC119_IN_SEL_V  0x3F
+#define GPIO_FUNC119_IN_SEL_S  0
+
+#define GPIO_FUNC120_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x334)
+/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG120_IN_SEL    (BIT(7))
+#define GPIO_SIG120_IN_SEL_M  (BIT(7))
+#define GPIO_SIG120_IN_SEL_V  0x1
+#define GPIO_SIG120_IN_SEL_S  7
+/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC120_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC120_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC120_IN_INV_SEL_V  0x1
+#define GPIO_FUNC120_IN_INV_SEL_S  6
+/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC120_IN_SEL    0x0000003F
+#define GPIO_FUNC120_IN_SEL_M  ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
+#define GPIO_FUNC120_IN_SEL_V  0x3F
+#define GPIO_FUNC120_IN_SEL_S  0
+
+#define GPIO_FUNC121_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x338)
+/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG121_IN_SEL    (BIT(7))
+#define GPIO_SIG121_IN_SEL_M  (BIT(7))
+#define GPIO_SIG121_IN_SEL_V  0x1
+#define GPIO_SIG121_IN_SEL_S  7
+/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC121_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC121_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC121_IN_INV_SEL_V  0x1
+#define GPIO_FUNC121_IN_INV_SEL_S  6
+/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC121_IN_SEL    0x0000003F
+#define GPIO_FUNC121_IN_SEL_M  ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
+#define GPIO_FUNC121_IN_SEL_V  0x3F
+#define GPIO_FUNC121_IN_SEL_S  0
+
+#define GPIO_FUNC122_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x33C)
+/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG122_IN_SEL    (BIT(7))
+#define GPIO_SIG122_IN_SEL_M  (BIT(7))
+#define GPIO_SIG122_IN_SEL_V  0x1
+#define GPIO_SIG122_IN_SEL_S  7
+/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC122_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC122_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC122_IN_INV_SEL_V  0x1
+#define GPIO_FUNC122_IN_INV_SEL_S  6
+/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC122_IN_SEL    0x0000003F
+#define GPIO_FUNC122_IN_SEL_M  ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
+#define GPIO_FUNC122_IN_SEL_V  0x3F
+#define GPIO_FUNC122_IN_SEL_S  0
+
+#define GPIO_FUNC123_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x340)
+/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG123_IN_SEL    (BIT(7))
+#define GPIO_SIG123_IN_SEL_M  (BIT(7))
+#define GPIO_SIG123_IN_SEL_V  0x1
+#define GPIO_SIG123_IN_SEL_S  7
+/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC123_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC123_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC123_IN_INV_SEL_V  0x1
+#define GPIO_FUNC123_IN_INV_SEL_S  6
+/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC123_IN_SEL    0x0000003F
+#define GPIO_FUNC123_IN_SEL_M  ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
+#define GPIO_FUNC123_IN_SEL_V  0x3F
+#define GPIO_FUNC123_IN_SEL_S  0
+
+#define GPIO_FUNC124_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x344)
+/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG124_IN_SEL    (BIT(7))
+#define GPIO_SIG124_IN_SEL_M  (BIT(7))
+#define GPIO_SIG124_IN_SEL_V  0x1
+#define GPIO_SIG124_IN_SEL_S  7
+/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC124_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC124_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC124_IN_INV_SEL_V  0x1
+#define GPIO_FUNC124_IN_INV_SEL_S  6
+/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC124_IN_SEL    0x0000003F
+#define GPIO_FUNC124_IN_SEL_M  ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
+#define GPIO_FUNC124_IN_SEL_V  0x3F
+#define GPIO_FUNC124_IN_SEL_S  0
+
+#define GPIO_FUNC125_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x348)
+/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG125_IN_SEL    (BIT(7))
+#define GPIO_SIG125_IN_SEL_M  (BIT(7))
+#define GPIO_SIG125_IN_SEL_V  0x1
+#define GPIO_SIG125_IN_SEL_S  7
+/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC125_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC125_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC125_IN_INV_SEL_V  0x1
+#define GPIO_FUNC125_IN_INV_SEL_S  6
+/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC125_IN_SEL    0x0000003F
+#define GPIO_FUNC125_IN_SEL_M  ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
+#define GPIO_FUNC125_IN_SEL_V  0x3F
+#define GPIO_FUNC125_IN_SEL_S  0
+
+#define GPIO_FUNC126_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x34C)
+/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG126_IN_SEL    (BIT(7))
+#define GPIO_SIG126_IN_SEL_M  (BIT(7))
+#define GPIO_SIG126_IN_SEL_V  0x1
+#define GPIO_SIG126_IN_SEL_S  7
+/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC126_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_V  0x1
+#define GPIO_FUNC126_IN_INV_SEL_S  6
+/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC126_IN_SEL    0x0000003F
+#define GPIO_FUNC126_IN_SEL_M  ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
+#define GPIO_FUNC126_IN_SEL_V  0x3F
+#define GPIO_FUNC126_IN_SEL_S  0
+
+#define GPIO_FUNC127_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x350)
+/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG127_IN_SEL    (BIT(7))
+#define GPIO_SIG127_IN_SEL_M  (BIT(7))
+#define GPIO_SIG127_IN_SEL_V  0x1
+#define GPIO_SIG127_IN_SEL_S  7
+/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC127_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_V  0x1
+#define GPIO_FUNC127_IN_INV_SEL_S  6
+/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC127_IN_SEL    0x0000003F
+#define GPIO_FUNC127_IN_SEL_M  ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
+#define GPIO_FUNC127_IN_SEL_V  0x3F
+#define GPIO_FUNC127_IN_SEL_S  0
+
+#define GPIO_FUNC128_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x354)
+/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG128_IN_SEL    (BIT(7))
+#define GPIO_SIG128_IN_SEL_M  (BIT(7))
+#define GPIO_SIG128_IN_SEL_V  0x1
+#define GPIO_SIG128_IN_SEL_S  7
+/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC128_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_V  0x1
+#define GPIO_FUNC128_IN_INV_SEL_S  6
+/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC128_IN_SEL    0x0000003F
+#define GPIO_FUNC128_IN_SEL_M  ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S))
+#define GPIO_FUNC128_IN_SEL_V  0x3F
+#define GPIO_FUNC128_IN_SEL_S  0
+
+#define GPIO_FUNC129_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x358)
+/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG129_IN_SEL    (BIT(7))
+#define GPIO_SIG129_IN_SEL_M  (BIT(7))
+#define GPIO_SIG129_IN_SEL_V  0x1
+#define GPIO_SIG129_IN_SEL_S  7
+/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC129_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_V  0x1
+#define GPIO_FUNC129_IN_INV_SEL_S  6
+/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC129_IN_SEL    0x0000003F
+#define GPIO_FUNC129_IN_SEL_M  ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S))
+#define GPIO_FUNC129_IN_SEL_V  0x3F
+#define GPIO_FUNC129_IN_SEL_S  0
+
+#define GPIO_FUNC130_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x35C)
+/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG130_IN_SEL    (BIT(7))
+#define GPIO_SIG130_IN_SEL_M  (BIT(7))
+#define GPIO_SIG130_IN_SEL_V  0x1
+#define GPIO_SIG130_IN_SEL_S  7
+/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC130_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_V  0x1
+#define GPIO_FUNC130_IN_INV_SEL_S  6
+/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC130_IN_SEL    0x0000003F
+#define GPIO_FUNC130_IN_SEL_M  ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S))
+#define GPIO_FUNC130_IN_SEL_V  0x3F
+#define GPIO_FUNC130_IN_SEL_S  0
+
+#define GPIO_FUNC131_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x360)
+/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG131_IN_SEL    (BIT(7))
+#define GPIO_SIG131_IN_SEL_M  (BIT(7))
+#define GPIO_SIG131_IN_SEL_V  0x1
+#define GPIO_SIG131_IN_SEL_S  7
+/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC131_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_V  0x1
+#define GPIO_FUNC131_IN_INV_SEL_S  6
+/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC131_IN_SEL    0x0000003F
+#define GPIO_FUNC131_IN_SEL_M  ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S))
+#define GPIO_FUNC131_IN_SEL_V  0x3F
+#define GPIO_FUNC131_IN_SEL_S  0
+
+#define GPIO_FUNC132_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x364)
+/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG132_IN_SEL    (BIT(7))
+#define GPIO_SIG132_IN_SEL_M  (BIT(7))
+#define GPIO_SIG132_IN_SEL_V  0x1
+#define GPIO_SIG132_IN_SEL_S  7
+/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC132_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_V  0x1
+#define GPIO_FUNC132_IN_INV_SEL_S  6
+/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC132_IN_SEL    0x0000003F
+#define GPIO_FUNC132_IN_SEL_M  ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S))
+#define GPIO_FUNC132_IN_SEL_V  0x3F
+#define GPIO_FUNC132_IN_SEL_S  0
+
+#define GPIO_FUNC133_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x368)
+/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG133_IN_SEL    (BIT(7))
+#define GPIO_SIG133_IN_SEL_M  (BIT(7))
+#define GPIO_SIG133_IN_SEL_V  0x1
+#define GPIO_SIG133_IN_SEL_S  7
+/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC133_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_V  0x1
+#define GPIO_FUNC133_IN_INV_SEL_S  6
+/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC133_IN_SEL    0x0000003F
+#define GPIO_FUNC133_IN_SEL_M  ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S))
+#define GPIO_FUNC133_IN_SEL_V  0x3F
+#define GPIO_FUNC133_IN_SEL_S  0
+
+#define GPIO_FUNC134_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x36C)
+/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG134_IN_SEL    (BIT(7))
+#define GPIO_SIG134_IN_SEL_M  (BIT(7))
+#define GPIO_SIG134_IN_SEL_V  0x1
+#define GPIO_SIG134_IN_SEL_S  7
+/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC134_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_V  0x1
+#define GPIO_FUNC134_IN_INV_SEL_S  6
+/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC134_IN_SEL    0x0000003F
+#define GPIO_FUNC134_IN_SEL_M  ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S))
+#define GPIO_FUNC134_IN_SEL_V  0x3F
+#define GPIO_FUNC134_IN_SEL_S  0
+
+#define GPIO_FUNC135_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x370)
+/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG135_IN_SEL    (BIT(7))
+#define GPIO_SIG135_IN_SEL_M  (BIT(7))
+#define GPIO_SIG135_IN_SEL_V  0x1
+#define GPIO_SIG135_IN_SEL_S  7
+/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC135_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_V  0x1
+#define GPIO_FUNC135_IN_INV_SEL_S  6
+/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC135_IN_SEL    0x0000003F
+#define GPIO_FUNC135_IN_SEL_M  ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S))
+#define GPIO_FUNC135_IN_SEL_V  0x3F
+#define GPIO_FUNC135_IN_SEL_S  0
+
+#define GPIO_FUNC136_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x374)
+/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG136_IN_SEL    (BIT(7))
+#define GPIO_SIG136_IN_SEL_M  (BIT(7))
+#define GPIO_SIG136_IN_SEL_V  0x1
+#define GPIO_SIG136_IN_SEL_S  7
+/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC136_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_V  0x1
+#define GPIO_FUNC136_IN_INV_SEL_S  6
+/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC136_IN_SEL    0x0000003F
+#define GPIO_FUNC136_IN_SEL_M  ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S))
+#define GPIO_FUNC136_IN_SEL_V  0x3F
+#define GPIO_FUNC136_IN_SEL_S  0
+
+#define GPIO_FUNC137_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x378)
+/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG137_IN_SEL    (BIT(7))
+#define GPIO_SIG137_IN_SEL_M  (BIT(7))
+#define GPIO_SIG137_IN_SEL_V  0x1
+#define GPIO_SIG137_IN_SEL_S  7
+/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC137_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_V  0x1
+#define GPIO_FUNC137_IN_INV_SEL_S  6
+/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC137_IN_SEL    0x0000003F
+#define GPIO_FUNC137_IN_SEL_M  ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S))
+#define GPIO_FUNC137_IN_SEL_V  0x3F
+#define GPIO_FUNC137_IN_SEL_S  0
+
+#define GPIO_FUNC138_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x37C)
+/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG138_IN_SEL    (BIT(7))
+#define GPIO_SIG138_IN_SEL_M  (BIT(7))
+#define GPIO_SIG138_IN_SEL_V  0x1
+#define GPIO_SIG138_IN_SEL_S  7
+/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC138_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC138_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC138_IN_INV_SEL_V  0x1
+#define GPIO_FUNC138_IN_INV_SEL_S  6
+/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC138_IN_SEL    0x0000003F
+#define GPIO_FUNC138_IN_SEL_M  ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S))
+#define GPIO_FUNC138_IN_SEL_V  0x3F
+#define GPIO_FUNC138_IN_SEL_S  0
+
+#define GPIO_FUNC139_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x380)
+/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG139_IN_SEL    (BIT(7))
+#define GPIO_SIG139_IN_SEL_M  (BIT(7))
+#define GPIO_SIG139_IN_SEL_V  0x1
+#define GPIO_SIG139_IN_SEL_S  7
+/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC139_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC139_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC139_IN_INV_SEL_V  0x1
+#define GPIO_FUNC139_IN_INV_SEL_S  6
+/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC139_IN_SEL    0x0000003F
+#define GPIO_FUNC139_IN_SEL_M  ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S))
+#define GPIO_FUNC139_IN_SEL_V  0x3F
+#define GPIO_FUNC139_IN_SEL_S  0
+
+#define GPIO_FUNC140_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x384)
+/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG140_IN_SEL    (BIT(7))
+#define GPIO_SIG140_IN_SEL_M  (BIT(7))
+#define GPIO_SIG140_IN_SEL_V  0x1
+#define GPIO_SIG140_IN_SEL_S  7
+/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC140_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_V  0x1
+#define GPIO_FUNC140_IN_INV_SEL_S  6
+/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC140_IN_SEL    0x0000003F
+#define GPIO_FUNC140_IN_SEL_M  ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S))
+#define GPIO_FUNC140_IN_SEL_V  0x3F
+#define GPIO_FUNC140_IN_SEL_S  0
+
+#define GPIO_FUNC141_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x388)
+/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG141_IN_SEL    (BIT(7))
+#define GPIO_SIG141_IN_SEL_M  (BIT(7))
+#define GPIO_SIG141_IN_SEL_V  0x1
+#define GPIO_SIG141_IN_SEL_S  7
+/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC141_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_V  0x1
+#define GPIO_FUNC141_IN_INV_SEL_S  6
+/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC141_IN_SEL    0x0000003F
+#define GPIO_FUNC141_IN_SEL_M  ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S))
+#define GPIO_FUNC141_IN_SEL_V  0x3F
+#define GPIO_FUNC141_IN_SEL_S  0
+
+#define GPIO_FUNC142_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x38C)
+/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG142_IN_SEL    (BIT(7))
+#define GPIO_SIG142_IN_SEL_M  (BIT(7))
+#define GPIO_SIG142_IN_SEL_V  0x1
+#define GPIO_SIG142_IN_SEL_S  7
+/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC142_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_V  0x1
+#define GPIO_FUNC142_IN_INV_SEL_S  6
+/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC142_IN_SEL    0x0000003F
+#define GPIO_FUNC142_IN_SEL_M  ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S))
+#define GPIO_FUNC142_IN_SEL_V  0x3F
+#define GPIO_FUNC142_IN_SEL_S  0
+
+#define GPIO_FUNC143_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x390)
+/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG143_IN_SEL    (BIT(7))
+#define GPIO_SIG143_IN_SEL_M  (BIT(7))
+#define GPIO_SIG143_IN_SEL_V  0x1
+#define GPIO_SIG143_IN_SEL_S  7
+/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC143_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_V  0x1
+#define GPIO_FUNC143_IN_INV_SEL_S  6
+/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC143_IN_SEL    0x0000003F
+#define GPIO_FUNC143_IN_SEL_M  ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S))
+#define GPIO_FUNC143_IN_SEL_V  0x3F
+#define GPIO_FUNC143_IN_SEL_S  0
+
+#define GPIO_FUNC144_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x394)
+/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG144_IN_SEL    (BIT(7))
+#define GPIO_SIG144_IN_SEL_M  (BIT(7))
+#define GPIO_SIG144_IN_SEL_V  0x1
+#define GPIO_SIG144_IN_SEL_S  7
+/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC144_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_V  0x1
+#define GPIO_FUNC144_IN_INV_SEL_S  6
+/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC144_IN_SEL    0x0000003F
+#define GPIO_FUNC144_IN_SEL_M  ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S))
+#define GPIO_FUNC144_IN_SEL_V  0x3F
+#define GPIO_FUNC144_IN_SEL_S  0
+
+#define GPIO_FUNC145_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x398)
+/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG145_IN_SEL    (BIT(7))
+#define GPIO_SIG145_IN_SEL_M  (BIT(7))
+#define GPIO_SIG145_IN_SEL_V  0x1
+#define GPIO_SIG145_IN_SEL_S  7
+/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC145_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_V  0x1
+#define GPIO_FUNC145_IN_INV_SEL_S  6
+/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC145_IN_SEL    0x0000003F
+#define GPIO_FUNC145_IN_SEL_M  ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S))
+#define GPIO_FUNC145_IN_SEL_V  0x3F
+#define GPIO_FUNC145_IN_SEL_S  0
+
+#define GPIO_FUNC146_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x39C)
+/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG146_IN_SEL    (BIT(7))
+#define GPIO_SIG146_IN_SEL_M  (BIT(7))
+#define GPIO_SIG146_IN_SEL_V  0x1
+#define GPIO_SIG146_IN_SEL_S  7
+/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC146_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_V  0x1
+#define GPIO_FUNC146_IN_INV_SEL_S  6
+/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC146_IN_SEL    0x0000003F
+#define GPIO_FUNC146_IN_SEL_M  ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S))
+#define GPIO_FUNC146_IN_SEL_V  0x3F
+#define GPIO_FUNC146_IN_SEL_S  0
+
+#define GPIO_FUNC147_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A0)
+/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG147_IN_SEL    (BIT(7))
+#define GPIO_SIG147_IN_SEL_M  (BIT(7))
+#define GPIO_SIG147_IN_SEL_V  0x1
+#define GPIO_SIG147_IN_SEL_S  7
+/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC147_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_V  0x1
+#define GPIO_FUNC147_IN_INV_SEL_S  6
+/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC147_IN_SEL    0x0000003F
+#define GPIO_FUNC147_IN_SEL_M  ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S))
+#define GPIO_FUNC147_IN_SEL_V  0x3F
+#define GPIO_FUNC147_IN_SEL_S  0
+
+#define GPIO_FUNC148_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A4)
+/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG148_IN_SEL    (BIT(7))
+#define GPIO_SIG148_IN_SEL_M  (BIT(7))
+#define GPIO_SIG148_IN_SEL_V  0x1
+#define GPIO_SIG148_IN_SEL_S  7
+/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC148_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_V  0x1
+#define GPIO_FUNC148_IN_INV_SEL_S  6
+/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC148_IN_SEL    0x0000003F
+#define GPIO_FUNC148_IN_SEL_M  ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S))
+#define GPIO_FUNC148_IN_SEL_V  0x3F
+#define GPIO_FUNC148_IN_SEL_S  0
+
+#define GPIO_FUNC149_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A8)
+/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG149_IN_SEL    (BIT(7))
+#define GPIO_SIG149_IN_SEL_M  (BIT(7))
+#define GPIO_SIG149_IN_SEL_V  0x1
+#define GPIO_SIG149_IN_SEL_S  7
+/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC149_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_V  0x1
+#define GPIO_FUNC149_IN_INV_SEL_S  6
+/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC149_IN_SEL    0x0000003F
+#define GPIO_FUNC149_IN_SEL_M  ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S))
+#define GPIO_FUNC149_IN_SEL_V  0x3F
+#define GPIO_FUNC149_IN_SEL_S  0
+
+#define GPIO_FUNC150_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3AC)
+/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG150_IN_SEL    (BIT(7))
+#define GPIO_SIG150_IN_SEL_M  (BIT(7))
+#define GPIO_SIG150_IN_SEL_V  0x1
+#define GPIO_SIG150_IN_SEL_S  7
+/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC150_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_V  0x1
+#define GPIO_FUNC150_IN_INV_SEL_S  6
+/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC150_IN_SEL    0x0000003F
+#define GPIO_FUNC150_IN_SEL_M  ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S))
+#define GPIO_FUNC150_IN_SEL_V  0x3F
+#define GPIO_FUNC150_IN_SEL_S  0
+
+#define GPIO_FUNC151_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B0)
+/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG151_IN_SEL    (BIT(7))
+#define GPIO_SIG151_IN_SEL_M  (BIT(7))
+#define GPIO_SIG151_IN_SEL_V  0x1
+#define GPIO_SIG151_IN_SEL_S  7
+/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC151_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_V  0x1
+#define GPIO_FUNC151_IN_INV_SEL_S  6
+/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC151_IN_SEL    0x0000003F
+#define GPIO_FUNC151_IN_SEL_M  ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S))
+#define GPIO_FUNC151_IN_SEL_V  0x3F
+#define GPIO_FUNC151_IN_SEL_S  0
+
+#define GPIO_FUNC152_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B4)
+/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG152_IN_SEL    (BIT(7))
+#define GPIO_SIG152_IN_SEL_M  (BIT(7))
+#define GPIO_SIG152_IN_SEL_V  0x1
+#define GPIO_SIG152_IN_SEL_S  7
+/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC152_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_V  0x1
+#define GPIO_FUNC152_IN_INV_SEL_S  6
+/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC152_IN_SEL    0x0000003F
+#define GPIO_FUNC152_IN_SEL_M  ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S))
+#define GPIO_FUNC152_IN_SEL_V  0x3F
+#define GPIO_FUNC152_IN_SEL_S  0
+
+#define GPIO_FUNC153_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B8)
+/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG153_IN_SEL    (BIT(7))
+#define GPIO_SIG153_IN_SEL_M  (BIT(7))
+#define GPIO_SIG153_IN_SEL_V  0x1
+#define GPIO_SIG153_IN_SEL_S  7
+/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC153_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_V  0x1
+#define GPIO_FUNC153_IN_INV_SEL_S  6
+/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC153_IN_SEL    0x0000003F
+#define GPIO_FUNC153_IN_SEL_M  ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S))
+#define GPIO_FUNC153_IN_SEL_V  0x3F
+#define GPIO_FUNC153_IN_SEL_S  0
+
+#define GPIO_FUNC154_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3BC)
+/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG154_IN_SEL    (BIT(7))
+#define GPIO_SIG154_IN_SEL_M  (BIT(7))
+#define GPIO_SIG154_IN_SEL_V  0x1
+#define GPIO_SIG154_IN_SEL_S  7
+/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC154_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_V  0x1
+#define GPIO_FUNC154_IN_INV_SEL_S  6
+/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC154_IN_SEL    0x0000003F
+#define GPIO_FUNC154_IN_SEL_M  ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S))
+#define GPIO_FUNC154_IN_SEL_V  0x3F
+#define GPIO_FUNC154_IN_SEL_S  0
+
+#define GPIO_FUNC155_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C0)
+/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG155_IN_SEL    (BIT(7))
+#define GPIO_SIG155_IN_SEL_M  (BIT(7))
+#define GPIO_SIG155_IN_SEL_V  0x1
+#define GPIO_SIG155_IN_SEL_S  7
+/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC155_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_V  0x1
+#define GPIO_FUNC155_IN_INV_SEL_S  6
+/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC155_IN_SEL    0x0000003F
+#define GPIO_FUNC155_IN_SEL_M  ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S))
+#define GPIO_FUNC155_IN_SEL_V  0x3F
+#define GPIO_FUNC155_IN_SEL_S  0
+
+#define GPIO_FUNC156_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C4)
+/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG156_IN_SEL    (BIT(7))
+#define GPIO_SIG156_IN_SEL_M  (BIT(7))
+#define GPIO_SIG156_IN_SEL_V  0x1
+#define GPIO_SIG156_IN_SEL_S  7
+/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC156_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_V  0x1
+#define GPIO_FUNC156_IN_INV_SEL_S  6
+/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC156_IN_SEL    0x0000003F
+#define GPIO_FUNC156_IN_SEL_M  ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S))
+#define GPIO_FUNC156_IN_SEL_V  0x3F
+#define GPIO_FUNC156_IN_SEL_S  0
+
+#define GPIO_FUNC157_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C8)
+/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG157_IN_SEL    (BIT(7))
+#define GPIO_SIG157_IN_SEL_M  (BIT(7))
+#define GPIO_SIG157_IN_SEL_V  0x1
+#define GPIO_SIG157_IN_SEL_S  7
+/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC157_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC157_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC157_IN_INV_SEL_V  0x1
+#define GPIO_FUNC157_IN_INV_SEL_S  6
+/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC157_IN_SEL    0x0000003F
+#define GPIO_FUNC157_IN_SEL_M  ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S))
+#define GPIO_FUNC157_IN_SEL_V  0x3F
+#define GPIO_FUNC157_IN_SEL_S  0
+
+#define GPIO_FUNC158_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3CC)
+/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG158_IN_SEL    (BIT(7))
+#define GPIO_SIG158_IN_SEL_M  (BIT(7))
+#define GPIO_SIG158_IN_SEL_V  0x1
+#define GPIO_SIG158_IN_SEL_S  7
+/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC158_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_V  0x1
+#define GPIO_FUNC158_IN_INV_SEL_S  6
+/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC158_IN_SEL    0x0000003F
+#define GPIO_FUNC158_IN_SEL_M  ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S))
+#define GPIO_FUNC158_IN_SEL_V  0x3F
+#define GPIO_FUNC158_IN_SEL_S  0
+
+#define GPIO_FUNC159_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D0)
+/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG159_IN_SEL    (BIT(7))
+#define GPIO_SIG159_IN_SEL_M  (BIT(7))
+#define GPIO_SIG159_IN_SEL_V  0x1
+#define GPIO_SIG159_IN_SEL_S  7
+/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC159_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_V  0x1
+#define GPIO_FUNC159_IN_INV_SEL_S  6
+/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC159_IN_SEL    0x0000003F
+#define GPIO_FUNC159_IN_SEL_M  ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S))
+#define GPIO_FUNC159_IN_SEL_V  0x3F
+#define GPIO_FUNC159_IN_SEL_S  0
+
+#define GPIO_FUNC160_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D4)
+/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG160_IN_SEL    (BIT(7))
+#define GPIO_SIG160_IN_SEL_M  (BIT(7))
+#define GPIO_SIG160_IN_SEL_V  0x1
+#define GPIO_SIG160_IN_SEL_S  7
+/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC160_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_V  0x1
+#define GPIO_FUNC160_IN_INV_SEL_S  6
+/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC160_IN_SEL    0x0000003F
+#define GPIO_FUNC160_IN_SEL_M  ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S))
+#define GPIO_FUNC160_IN_SEL_V  0x3F
+#define GPIO_FUNC160_IN_SEL_S  0
+
+#define GPIO_FUNC161_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D8)
+/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG161_IN_SEL    (BIT(7))
+#define GPIO_SIG161_IN_SEL_M  (BIT(7))
+#define GPIO_SIG161_IN_SEL_V  0x1
+#define GPIO_SIG161_IN_SEL_S  7
+/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC161_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_V  0x1
+#define GPIO_FUNC161_IN_INV_SEL_S  6
+/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC161_IN_SEL    0x0000003F
+#define GPIO_FUNC161_IN_SEL_M  ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S))
+#define GPIO_FUNC161_IN_SEL_V  0x3F
+#define GPIO_FUNC161_IN_SEL_S  0
+
+#define GPIO_FUNC162_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3DC)
+/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG162_IN_SEL    (BIT(7))
+#define GPIO_SIG162_IN_SEL_M  (BIT(7))
+#define GPIO_SIG162_IN_SEL_V  0x1
+#define GPIO_SIG162_IN_SEL_S  7
+/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC162_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_V  0x1
+#define GPIO_FUNC162_IN_INV_SEL_S  6
+/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC162_IN_SEL    0x0000003F
+#define GPIO_FUNC162_IN_SEL_M  ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S))
+#define GPIO_FUNC162_IN_SEL_V  0x3F
+#define GPIO_FUNC162_IN_SEL_S  0
+
+#define GPIO_FUNC163_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E0)
+/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG163_IN_SEL    (BIT(7))
+#define GPIO_SIG163_IN_SEL_M  (BIT(7))
+#define GPIO_SIG163_IN_SEL_V  0x1
+#define GPIO_SIG163_IN_SEL_S  7
+/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC163_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_V  0x1
+#define GPIO_FUNC163_IN_INV_SEL_S  6
+/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC163_IN_SEL    0x0000003F
+#define GPIO_FUNC163_IN_SEL_M  ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S))
+#define GPIO_FUNC163_IN_SEL_V  0x3F
+#define GPIO_FUNC163_IN_SEL_S  0
+
+#define GPIO_FUNC164_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E4)
+/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG164_IN_SEL    (BIT(7))
+#define GPIO_SIG164_IN_SEL_M  (BIT(7))
+#define GPIO_SIG164_IN_SEL_V  0x1
+#define GPIO_SIG164_IN_SEL_S  7
+/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC164_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_V  0x1
+#define GPIO_FUNC164_IN_INV_SEL_S  6
+/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC164_IN_SEL    0x0000003F
+#define GPIO_FUNC164_IN_SEL_M  ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S))
+#define GPIO_FUNC164_IN_SEL_V  0x3F
+#define GPIO_FUNC164_IN_SEL_S  0
+
+#define GPIO_FUNC165_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E8)
+/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG165_IN_SEL    (BIT(7))
+#define GPIO_SIG165_IN_SEL_M  (BIT(7))
+#define GPIO_SIG165_IN_SEL_V  0x1
+#define GPIO_SIG165_IN_SEL_S  7
+/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC165_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_V  0x1
+#define GPIO_FUNC165_IN_INV_SEL_S  6
+/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC165_IN_SEL    0x0000003F
+#define GPIO_FUNC165_IN_SEL_M  ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S))
+#define GPIO_FUNC165_IN_SEL_V  0x3F
+#define GPIO_FUNC165_IN_SEL_S  0
+
+#define GPIO_FUNC166_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3EC)
+/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG166_IN_SEL    (BIT(7))
+#define GPIO_SIG166_IN_SEL_M  (BIT(7))
+#define GPIO_SIG166_IN_SEL_V  0x1
+#define GPIO_SIG166_IN_SEL_S  7
+/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC166_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_V  0x1
+#define GPIO_FUNC166_IN_INV_SEL_S  6
+/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC166_IN_SEL    0x0000003F
+#define GPIO_FUNC166_IN_SEL_M  ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S))
+#define GPIO_FUNC166_IN_SEL_V  0x3F
+#define GPIO_FUNC166_IN_SEL_S  0
+
+#define GPIO_FUNC167_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F0)
+/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG167_IN_SEL    (BIT(7))
+#define GPIO_SIG167_IN_SEL_M  (BIT(7))
+#define GPIO_SIG167_IN_SEL_V  0x1
+#define GPIO_SIG167_IN_SEL_S  7
+/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC167_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_V  0x1
+#define GPIO_FUNC167_IN_INV_SEL_S  6
+/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC167_IN_SEL    0x0000003F
+#define GPIO_FUNC167_IN_SEL_M  ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S))
+#define GPIO_FUNC167_IN_SEL_V  0x3F
+#define GPIO_FUNC167_IN_SEL_S  0
+
+#define GPIO_FUNC168_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F4)
+/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG168_IN_SEL    (BIT(7))
+#define GPIO_SIG168_IN_SEL_M  (BIT(7))
+#define GPIO_SIG168_IN_SEL_V  0x1
+#define GPIO_SIG168_IN_SEL_S  7
+/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC168_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_V  0x1
+#define GPIO_FUNC168_IN_INV_SEL_S  6
+/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC168_IN_SEL    0x0000003F
+#define GPIO_FUNC168_IN_SEL_M  ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S))
+#define GPIO_FUNC168_IN_SEL_V  0x3F
+#define GPIO_FUNC168_IN_SEL_S  0
+
+#define GPIO_FUNC169_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F8)
+/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG169_IN_SEL    (BIT(7))
+#define GPIO_SIG169_IN_SEL_M  (BIT(7))
+#define GPIO_SIG169_IN_SEL_V  0x1
+#define GPIO_SIG169_IN_SEL_S  7
+/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC169_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_V  0x1
+#define GPIO_FUNC169_IN_INV_SEL_S  6
+/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC169_IN_SEL    0x0000003F
+#define GPIO_FUNC169_IN_SEL_M  ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S))
+#define GPIO_FUNC169_IN_SEL_V  0x3F
+#define GPIO_FUNC169_IN_SEL_S  0
+
+#define GPIO_FUNC170_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3FC)
+/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG170_IN_SEL    (BIT(7))
+#define GPIO_SIG170_IN_SEL_M  (BIT(7))
+#define GPIO_SIG170_IN_SEL_V  0x1
+#define GPIO_SIG170_IN_SEL_S  7
+/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC170_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_V  0x1
+#define GPIO_FUNC170_IN_INV_SEL_S  6
+/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC170_IN_SEL    0x0000003F
+#define GPIO_FUNC170_IN_SEL_M  ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S))
+#define GPIO_FUNC170_IN_SEL_V  0x3F
+#define GPIO_FUNC170_IN_SEL_S  0
+
+#define GPIO_FUNC171_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x400)
+/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG171_IN_SEL    (BIT(7))
+#define GPIO_SIG171_IN_SEL_M  (BIT(7))
+#define GPIO_SIG171_IN_SEL_V  0x1
+#define GPIO_SIG171_IN_SEL_S  7
+/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC171_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_V  0x1
+#define GPIO_FUNC171_IN_INV_SEL_S  6
+/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC171_IN_SEL    0x0000003F
+#define GPIO_FUNC171_IN_SEL_M  ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S))
+#define GPIO_FUNC171_IN_SEL_V  0x3F
+#define GPIO_FUNC171_IN_SEL_S  0
+
+#define GPIO_FUNC172_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x404)
+/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG172_IN_SEL    (BIT(7))
+#define GPIO_SIG172_IN_SEL_M  (BIT(7))
+#define GPIO_SIG172_IN_SEL_V  0x1
+#define GPIO_SIG172_IN_SEL_S  7
+/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC172_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_V  0x1
+#define GPIO_FUNC172_IN_INV_SEL_S  6
+/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC172_IN_SEL    0x0000003F
+#define GPIO_FUNC172_IN_SEL_M  ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S))
+#define GPIO_FUNC172_IN_SEL_V  0x3F
+#define GPIO_FUNC172_IN_SEL_S  0
+
+#define GPIO_FUNC173_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x408)
+/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG173_IN_SEL    (BIT(7))
+#define GPIO_SIG173_IN_SEL_M  (BIT(7))
+#define GPIO_SIG173_IN_SEL_V  0x1
+#define GPIO_SIG173_IN_SEL_S  7
+/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC173_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_V  0x1
+#define GPIO_FUNC173_IN_INV_SEL_S  6
+/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC173_IN_SEL    0x0000003F
+#define GPIO_FUNC173_IN_SEL_M  ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S))
+#define GPIO_FUNC173_IN_SEL_V  0x3F
+#define GPIO_FUNC173_IN_SEL_S  0
+
+#define GPIO_FUNC174_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x40C)
+/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG174_IN_SEL    (BIT(7))
+#define GPIO_SIG174_IN_SEL_M  (BIT(7))
+#define GPIO_SIG174_IN_SEL_V  0x1
+#define GPIO_SIG174_IN_SEL_S  7
+/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC174_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_V  0x1
+#define GPIO_FUNC174_IN_INV_SEL_S  6
+/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC174_IN_SEL    0x0000003F
+#define GPIO_FUNC174_IN_SEL_M  ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S))
+#define GPIO_FUNC174_IN_SEL_V  0x3F
+#define GPIO_FUNC174_IN_SEL_S  0
+
+#define GPIO_FUNC175_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x410)
+/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG175_IN_SEL    (BIT(7))
+#define GPIO_SIG175_IN_SEL_M  (BIT(7))
+#define GPIO_SIG175_IN_SEL_V  0x1
+#define GPIO_SIG175_IN_SEL_S  7
+/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC175_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_V  0x1
+#define GPIO_FUNC175_IN_INV_SEL_S  6
+/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC175_IN_SEL    0x0000003F
+#define GPIO_FUNC175_IN_SEL_M  ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S))
+#define GPIO_FUNC175_IN_SEL_V  0x3F
+#define GPIO_FUNC175_IN_SEL_S  0
+
+#define GPIO_FUNC176_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x414)
+/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG176_IN_SEL    (BIT(7))
+#define GPIO_SIG176_IN_SEL_M  (BIT(7))
+#define GPIO_SIG176_IN_SEL_V  0x1
+#define GPIO_SIG176_IN_SEL_S  7
+/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC176_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_V  0x1
+#define GPIO_FUNC176_IN_INV_SEL_S  6
+/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC176_IN_SEL    0x0000003F
+#define GPIO_FUNC176_IN_SEL_M  ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S))
+#define GPIO_FUNC176_IN_SEL_V  0x3F
+#define GPIO_FUNC176_IN_SEL_S  0
+
+#define GPIO_FUNC177_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x418)
+/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG177_IN_SEL    (BIT(7))
+#define GPIO_SIG177_IN_SEL_M  (BIT(7))
+#define GPIO_SIG177_IN_SEL_V  0x1
+#define GPIO_SIG177_IN_SEL_S  7
+/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC177_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_V  0x1
+#define GPIO_FUNC177_IN_INV_SEL_S  6
+/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC177_IN_SEL    0x0000003F
+#define GPIO_FUNC177_IN_SEL_M  ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S))
+#define GPIO_FUNC177_IN_SEL_V  0x3F
+#define GPIO_FUNC177_IN_SEL_S  0
+
+#define GPIO_FUNC178_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x41C)
+/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG178_IN_SEL    (BIT(7))
+#define GPIO_SIG178_IN_SEL_M  (BIT(7))
+#define GPIO_SIG178_IN_SEL_V  0x1
+#define GPIO_SIG178_IN_SEL_S  7
+/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC178_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_V  0x1
+#define GPIO_FUNC178_IN_INV_SEL_S  6
+/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC178_IN_SEL    0x0000003F
+#define GPIO_FUNC178_IN_SEL_M  ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S))
+#define GPIO_FUNC178_IN_SEL_V  0x3F
+#define GPIO_FUNC178_IN_SEL_S  0
+
+#define GPIO_FUNC179_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x420)
+/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG179_IN_SEL    (BIT(7))
+#define GPIO_SIG179_IN_SEL_M  (BIT(7))
+#define GPIO_SIG179_IN_SEL_V  0x1
+#define GPIO_SIG179_IN_SEL_S  7
+/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC179_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_V  0x1
+#define GPIO_FUNC179_IN_INV_SEL_S  6
+/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC179_IN_SEL    0x0000003F
+#define GPIO_FUNC179_IN_SEL_M  ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S))
+#define GPIO_FUNC179_IN_SEL_V  0x3F
+#define GPIO_FUNC179_IN_SEL_S  0
+
+#define GPIO_FUNC180_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x424)
+/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG180_IN_SEL    (BIT(7))
+#define GPIO_SIG180_IN_SEL_M  (BIT(7))
+#define GPIO_SIG180_IN_SEL_V  0x1
+#define GPIO_SIG180_IN_SEL_S  7
+/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC180_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_V  0x1
+#define GPIO_FUNC180_IN_INV_SEL_S  6
+/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC180_IN_SEL    0x0000003F
+#define GPIO_FUNC180_IN_SEL_M  ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S))
+#define GPIO_FUNC180_IN_SEL_V  0x3F
+#define GPIO_FUNC180_IN_SEL_S  0
+
+#define GPIO_FUNC181_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x428)
+/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG181_IN_SEL    (BIT(7))
+#define GPIO_SIG181_IN_SEL_M  (BIT(7))
+#define GPIO_SIG181_IN_SEL_V  0x1
+#define GPIO_SIG181_IN_SEL_S  7
+/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC181_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_V  0x1
+#define GPIO_FUNC181_IN_INV_SEL_S  6
+/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC181_IN_SEL    0x0000003F
+#define GPIO_FUNC181_IN_SEL_M  ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S))
+#define GPIO_FUNC181_IN_SEL_V  0x3F
+#define GPIO_FUNC181_IN_SEL_S  0
+
+#define GPIO_FUNC182_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x42C)
+/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG182_IN_SEL    (BIT(7))
+#define GPIO_SIG182_IN_SEL_M  (BIT(7))
+#define GPIO_SIG182_IN_SEL_V  0x1
+#define GPIO_SIG182_IN_SEL_S  7
+/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC182_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_V  0x1
+#define GPIO_FUNC182_IN_INV_SEL_S  6
+/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC182_IN_SEL    0x0000003F
+#define GPIO_FUNC182_IN_SEL_M  ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S))
+#define GPIO_FUNC182_IN_SEL_V  0x3F
+#define GPIO_FUNC182_IN_SEL_S  0
+
+#define GPIO_FUNC183_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x430)
+/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG183_IN_SEL    (BIT(7))
+#define GPIO_SIG183_IN_SEL_M  (BIT(7))
+#define GPIO_SIG183_IN_SEL_V  0x1
+#define GPIO_SIG183_IN_SEL_S  7
+/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC183_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_V  0x1
+#define GPIO_FUNC183_IN_INV_SEL_S  6
+/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC183_IN_SEL    0x0000003F
+#define GPIO_FUNC183_IN_SEL_M  ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S))
+#define GPIO_FUNC183_IN_SEL_V  0x3F
+#define GPIO_FUNC183_IN_SEL_S  0
+
+#define GPIO_FUNC184_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x434)
+/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG184_IN_SEL    (BIT(7))
+#define GPIO_SIG184_IN_SEL_M  (BIT(7))
+#define GPIO_SIG184_IN_SEL_V  0x1
+#define GPIO_SIG184_IN_SEL_S  7
+/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC184_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_V  0x1
+#define GPIO_FUNC184_IN_INV_SEL_S  6
+/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC184_IN_SEL    0x0000003F
+#define GPIO_FUNC184_IN_SEL_M  ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S))
+#define GPIO_FUNC184_IN_SEL_V  0x3F
+#define GPIO_FUNC184_IN_SEL_S  0
+
+#define GPIO_FUNC185_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x438)
+/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG185_IN_SEL    (BIT(7))
+#define GPIO_SIG185_IN_SEL_M  (BIT(7))
+#define GPIO_SIG185_IN_SEL_V  0x1
+#define GPIO_SIG185_IN_SEL_S  7
+/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC185_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_V  0x1
+#define GPIO_FUNC185_IN_INV_SEL_S  6
+/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC185_IN_SEL    0x0000003F
+#define GPIO_FUNC185_IN_SEL_M  ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S))
+#define GPIO_FUNC185_IN_SEL_V  0x3F
+#define GPIO_FUNC185_IN_SEL_S  0
+
+#define GPIO_FUNC186_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x43C)
+/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG186_IN_SEL    (BIT(7))
+#define GPIO_SIG186_IN_SEL_M  (BIT(7))
+#define GPIO_SIG186_IN_SEL_V  0x1
+#define GPIO_SIG186_IN_SEL_S  7
+/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC186_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_V  0x1
+#define GPIO_FUNC186_IN_INV_SEL_S  6
+/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC186_IN_SEL    0x0000003F
+#define GPIO_FUNC186_IN_SEL_M  ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S))
+#define GPIO_FUNC186_IN_SEL_V  0x3F
+#define GPIO_FUNC186_IN_SEL_S  0
+
+#define GPIO_FUNC187_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x440)
+/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG187_IN_SEL    (BIT(7))
+#define GPIO_SIG187_IN_SEL_M  (BIT(7))
+#define GPIO_SIG187_IN_SEL_V  0x1
+#define GPIO_SIG187_IN_SEL_S  7
+/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC187_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_V  0x1
+#define GPIO_FUNC187_IN_INV_SEL_S  6
+/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC187_IN_SEL    0x0000003F
+#define GPIO_FUNC187_IN_SEL_M  ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S))
+#define GPIO_FUNC187_IN_SEL_V  0x3F
+#define GPIO_FUNC187_IN_SEL_S  0
+
+#define GPIO_FUNC188_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x444)
+/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG188_IN_SEL    (BIT(7))
+#define GPIO_SIG188_IN_SEL_M  (BIT(7))
+#define GPIO_SIG188_IN_SEL_V  0x1
+#define GPIO_SIG188_IN_SEL_S  7
+/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC188_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_V  0x1
+#define GPIO_FUNC188_IN_INV_SEL_S  6
+/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC188_IN_SEL    0x0000003F
+#define GPIO_FUNC188_IN_SEL_M  ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S))
+#define GPIO_FUNC188_IN_SEL_V  0x3F
+#define GPIO_FUNC188_IN_SEL_S  0
+
+#define GPIO_FUNC189_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x448)
+/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG189_IN_SEL    (BIT(7))
+#define GPIO_SIG189_IN_SEL_M  (BIT(7))
+#define GPIO_SIG189_IN_SEL_V  0x1
+#define GPIO_SIG189_IN_SEL_S  7
+/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC189_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_V  0x1
+#define GPIO_FUNC189_IN_INV_SEL_S  6
+/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC189_IN_SEL    0x0000003F
+#define GPIO_FUNC189_IN_SEL_M  ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S))
+#define GPIO_FUNC189_IN_SEL_V  0x3F
+#define GPIO_FUNC189_IN_SEL_S  0
+
+#define GPIO_FUNC190_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x44C)
+/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG190_IN_SEL    (BIT(7))
+#define GPIO_SIG190_IN_SEL_M  (BIT(7))
+#define GPIO_SIG190_IN_SEL_V  0x1
+#define GPIO_SIG190_IN_SEL_S  7
+/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC190_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_V  0x1
+#define GPIO_FUNC190_IN_INV_SEL_S  6
+/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC190_IN_SEL    0x0000003F
+#define GPIO_FUNC190_IN_SEL_M  ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S))
+#define GPIO_FUNC190_IN_SEL_V  0x3F
+#define GPIO_FUNC190_IN_SEL_S  0
+
+#define GPIO_FUNC191_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x450)
+/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG191_IN_SEL    (BIT(7))
+#define GPIO_SIG191_IN_SEL_M  (BIT(7))
+#define GPIO_SIG191_IN_SEL_V  0x1
+#define GPIO_SIG191_IN_SEL_S  7
+/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC191_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_V  0x1
+#define GPIO_FUNC191_IN_INV_SEL_S  6
+/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC191_IN_SEL    0x0000003F
+#define GPIO_FUNC191_IN_SEL_M  ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S))
+#define GPIO_FUNC191_IN_SEL_V  0x3F
+#define GPIO_FUNC191_IN_SEL_S  0
+
+#define GPIO_FUNC192_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x454)
+/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG192_IN_SEL    (BIT(7))
+#define GPIO_SIG192_IN_SEL_M  (BIT(7))
+#define GPIO_SIG192_IN_SEL_V  0x1
+#define GPIO_SIG192_IN_SEL_S  7
+/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC192_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_V  0x1
+#define GPIO_FUNC192_IN_INV_SEL_S  6
+/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC192_IN_SEL    0x0000003F
+#define GPIO_FUNC192_IN_SEL_M  ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S))
+#define GPIO_FUNC192_IN_SEL_V  0x3F
+#define GPIO_FUNC192_IN_SEL_S  0
+
+#define GPIO_FUNC193_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x458)
+/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG193_IN_SEL    (BIT(7))
+#define GPIO_SIG193_IN_SEL_M  (BIT(7))
+#define GPIO_SIG193_IN_SEL_V  0x1
+#define GPIO_SIG193_IN_SEL_S  7
+/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC193_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_V  0x1
+#define GPIO_FUNC193_IN_INV_SEL_S  6
+/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC193_IN_SEL    0x0000003F
+#define GPIO_FUNC193_IN_SEL_M  ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S))
+#define GPIO_FUNC193_IN_SEL_V  0x3F
+#define GPIO_FUNC193_IN_SEL_S  0
+
+#define GPIO_FUNC194_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x45C)
+/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG194_IN_SEL    (BIT(7))
+#define GPIO_SIG194_IN_SEL_M  (BIT(7))
+#define GPIO_SIG194_IN_SEL_V  0x1
+#define GPIO_SIG194_IN_SEL_S  7
+/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC194_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_V  0x1
+#define GPIO_FUNC194_IN_INV_SEL_S  6
+/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC194_IN_SEL    0x0000003F
+#define GPIO_FUNC194_IN_SEL_M  ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S))
+#define GPIO_FUNC194_IN_SEL_V  0x3F
+#define GPIO_FUNC194_IN_SEL_S  0
+
+#define GPIO_FUNC195_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x460)
+/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG195_IN_SEL    (BIT(7))
+#define GPIO_SIG195_IN_SEL_M  (BIT(7))
+#define GPIO_SIG195_IN_SEL_V  0x1
+#define GPIO_SIG195_IN_SEL_S  7
+/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC195_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_V  0x1
+#define GPIO_FUNC195_IN_INV_SEL_S  6
+/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC195_IN_SEL    0x0000003F
+#define GPIO_FUNC195_IN_SEL_M  ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S))
+#define GPIO_FUNC195_IN_SEL_V  0x3F
+#define GPIO_FUNC195_IN_SEL_S  0
+
+#define GPIO_FUNC196_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x464)
+/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG196_IN_SEL    (BIT(7))
+#define GPIO_SIG196_IN_SEL_M  (BIT(7))
+#define GPIO_SIG196_IN_SEL_V  0x1
+#define GPIO_SIG196_IN_SEL_S  7
+/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC196_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_V  0x1
+#define GPIO_FUNC196_IN_INV_SEL_S  6
+/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC196_IN_SEL    0x0000003F
+#define GPIO_FUNC196_IN_SEL_M  ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S))
+#define GPIO_FUNC196_IN_SEL_V  0x3F
+#define GPIO_FUNC196_IN_SEL_S  0
+
+#define GPIO_FUNC197_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x468)
+/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG197_IN_SEL    (BIT(7))
+#define GPIO_SIG197_IN_SEL_M  (BIT(7))
+#define GPIO_SIG197_IN_SEL_V  0x1
+#define GPIO_SIG197_IN_SEL_S  7
+/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC197_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_V  0x1
+#define GPIO_FUNC197_IN_INV_SEL_S  6
+/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC197_IN_SEL    0x0000003F
+#define GPIO_FUNC197_IN_SEL_M  ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S))
+#define GPIO_FUNC197_IN_SEL_V  0x3F
+#define GPIO_FUNC197_IN_SEL_S  0
+
+#define GPIO_FUNC198_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x46C)
+/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG198_IN_SEL    (BIT(7))
+#define GPIO_SIG198_IN_SEL_M  (BIT(7))
+#define GPIO_SIG198_IN_SEL_V  0x1
+#define GPIO_SIG198_IN_SEL_S  7
+/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC198_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_V  0x1
+#define GPIO_FUNC198_IN_INV_SEL_S  6
+/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC198_IN_SEL    0x0000003F
+#define GPIO_FUNC198_IN_SEL_M  ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S))
+#define GPIO_FUNC198_IN_SEL_V  0x3F
+#define GPIO_FUNC198_IN_SEL_S  0
+
+#define GPIO_FUNC199_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x470)
+/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG199_IN_SEL    (BIT(7))
+#define GPIO_SIG199_IN_SEL_M  (BIT(7))
+#define GPIO_SIG199_IN_SEL_V  0x1
+#define GPIO_SIG199_IN_SEL_S  7
+/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC199_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_V  0x1
+#define GPIO_FUNC199_IN_INV_SEL_S  6
+/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC199_IN_SEL    0x0000003F
+#define GPIO_FUNC199_IN_SEL_M  ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S))
+#define GPIO_FUNC199_IN_SEL_V  0x3F
+#define GPIO_FUNC199_IN_SEL_S  0
+
+#define GPIO_FUNC200_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x474)
+/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG200_IN_SEL    (BIT(7))
+#define GPIO_SIG200_IN_SEL_M  (BIT(7))
+#define GPIO_SIG200_IN_SEL_V  0x1
+#define GPIO_SIG200_IN_SEL_S  7
+/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC200_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_V  0x1
+#define GPIO_FUNC200_IN_INV_SEL_S  6
+/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC200_IN_SEL    0x0000003F
+#define GPIO_FUNC200_IN_SEL_M  ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S))
+#define GPIO_FUNC200_IN_SEL_V  0x3F
+#define GPIO_FUNC200_IN_SEL_S  0
+
+#define GPIO_FUNC201_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x478)
+/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG201_IN_SEL    (BIT(7))
+#define GPIO_SIG201_IN_SEL_M  (BIT(7))
+#define GPIO_SIG201_IN_SEL_V  0x1
+#define GPIO_SIG201_IN_SEL_S  7
+/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC201_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_V  0x1
+#define GPIO_FUNC201_IN_INV_SEL_S  6
+/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC201_IN_SEL    0x0000003F
+#define GPIO_FUNC201_IN_SEL_M  ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S))
+#define GPIO_FUNC201_IN_SEL_V  0x3F
+#define GPIO_FUNC201_IN_SEL_S  0
+
+#define GPIO_FUNC202_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x47C)
+/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG202_IN_SEL    (BIT(7))
+#define GPIO_SIG202_IN_SEL_M  (BIT(7))
+#define GPIO_SIG202_IN_SEL_V  0x1
+#define GPIO_SIG202_IN_SEL_S  7
+/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC202_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_V  0x1
+#define GPIO_FUNC202_IN_INV_SEL_S  6
+/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC202_IN_SEL    0x0000003F
+#define GPIO_FUNC202_IN_SEL_M  ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S))
+#define GPIO_FUNC202_IN_SEL_V  0x3F
+#define GPIO_FUNC202_IN_SEL_S  0
+
+#define GPIO_FUNC203_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x480)
+/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG203_IN_SEL    (BIT(7))
+#define GPIO_SIG203_IN_SEL_M  (BIT(7))
+#define GPIO_SIG203_IN_SEL_V  0x1
+#define GPIO_SIG203_IN_SEL_S  7
+/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC203_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_V  0x1
+#define GPIO_FUNC203_IN_INV_SEL_S  6
+/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC203_IN_SEL    0x0000003F
+#define GPIO_FUNC203_IN_SEL_M  ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S))
+#define GPIO_FUNC203_IN_SEL_V  0x3F
+#define GPIO_FUNC203_IN_SEL_S  0
+
+#define GPIO_FUNC204_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x484)
+/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG204_IN_SEL    (BIT(7))
+#define GPIO_SIG204_IN_SEL_M  (BIT(7))
+#define GPIO_SIG204_IN_SEL_V  0x1
+#define GPIO_SIG204_IN_SEL_S  7
+/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC204_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC204_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC204_IN_INV_SEL_V  0x1
+#define GPIO_FUNC204_IN_INV_SEL_S  6
+/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC204_IN_SEL    0x0000003F
+#define GPIO_FUNC204_IN_SEL_M  ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S))
+#define GPIO_FUNC204_IN_SEL_V  0x3F
+#define GPIO_FUNC204_IN_SEL_S  0
+
+#define GPIO_FUNC205_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x488)
+/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG205_IN_SEL    (BIT(7))
+#define GPIO_SIG205_IN_SEL_M  (BIT(7))
+#define GPIO_SIG205_IN_SEL_V  0x1
+#define GPIO_SIG205_IN_SEL_S  7
+/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC205_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC205_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC205_IN_INV_SEL_V  0x1
+#define GPIO_FUNC205_IN_INV_SEL_S  6
+/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC205_IN_SEL    0x0000003F
+#define GPIO_FUNC205_IN_SEL_M  ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S))
+#define GPIO_FUNC205_IN_SEL_V  0x3F
+#define GPIO_FUNC205_IN_SEL_S  0
+
+#define GPIO_FUNC206_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x48C)
+/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG206_IN_SEL    (BIT(7))
+#define GPIO_SIG206_IN_SEL_M  (BIT(7))
+#define GPIO_SIG206_IN_SEL_V  0x1
+#define GPIO_SIG206_IN_SEL_S  7
+/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC206_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC206_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC206_IN_INV_SEL_V  0x1
+#define GPIO_FUNC206_IN_INV_SEL_S  6
+/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC206_IN_SEL    0x0000003F
+#define GPIO_FUNC206_IN_SEL_M  ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S))
+#define GPIO_FUNC206_IN_SEL_V  0x3F
+#define GPIO_FUNC206_IN_SEL_S  0
+
+#define GPIO_FUNC207_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x490)
+/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG207_IN_SEL    (BIT(7))
+#define GPIO_SIG207_IN_SEL_M  (BIT(7))
+#define GPIO_SIG207_IN_SEL_V  0x1
+#define GPIO_SIG207_IN_SEL_S  7
+/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC207_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC207_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC207_IN_INV_SEL_V  0x1
+#define GPIO_FUNC207_IN_INV_SEL_S  6
+/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC207_IN_SEL    0x0000003F
+#define GPIO_FUNC207_IN_SEL_M  ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S))
+#define GPIO_FUNC207_IN_SEL_V  0x3F
+#define GPIO_FUNC207_IN_SEL_S  0
+
+#define GPIO_FUNC208_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x494)
+/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG208_IN_SEL    (BIT(7))
+#define GPIO_SIG208_IN_SEL_M  (BIT(7))
+#define GPIO_SIG208_IN_SEL_V  0x1
+#define GPIO_SIG208_IN_SEL_S  7
+/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC208_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC208_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC208_IN_INV_SEL_V  0x1
+#define GPIO_FUNC208_IN_INV_SEL_S  6
+/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC208_IN_SEL    0x0000003F
+#define GPIO_FUNC208_IN_SEL_M  ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S))
+#define GPIO_FUNC208_IN_SEL_V  0x3F
+#define GPIO_FUNC208_IN_SEL_S  0
+
+#define GPIO_FUNC209_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x498)
+/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG209_IN_SEL    (BIT(7))
+#define GPIO_SIG209_IN_SEL_M  (BIT(7))
+#define GPIO_SIG209_IN_SEL_V  0x1
+#define GPIO_SIG209_IN_SEL_S  7
+/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC209_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC209_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC209_IN_INV_SEL_V  0x1
+#define GPIO_FUNC209_IN_INV_SEL_S  6
+/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC209_IN_SEL    0x0000003F
+#define GPIO_FUNC209_IN_SEL_M  ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S))
+#define GPIO_FUNC209_IN_SEL_V  0x3F
+#define GPIO_FUNC209_IN_SEL_S  0
+
+#define GPIO_FUNC210_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x49C)
+/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG210_IN_SEL    (BIT(7))
+#define GPIO_SIG210_IN_SEL_M  (BIT(7))
+#define GPIO_SIG210_IN_SEL_V  0x1
+#define GPIO_SIG210_IN_SEL_S  7
+/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC210_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC210_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC210_IN_INV_SEL_V  0x1
+#define GPIO_FUNC210_IN_INV_SEL_S  6
+/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC210_IN_SEL    0x0000003F
+#define GPIO_FUNC210_IN_SEL_M  ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S))
+#define GPIO_FUNC210_IN_SEL_V  0x3F
+#define GPIO_FUNC210_IN_SEL_S  0
+
+#define GPIO_FUNC211_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A0)
+/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG211_IN_SEL    (BIT(7))
+#define GPIO_SIG211_IN_SEL_M  (BIT(7))
+#define GPIO_SIG211_IN_SEL_V  0x1
+#define GPIO_SIG211_IN_SEL_S  7
+/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC211_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC211_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC211_IN_INV_SEL_V  0x1
+#define GPIO_FUNC211_IN_INV_SEL_S  6
+/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC211_IN_SEL    0x0000003F
+#define GPIO_FUNC211_IN_SEL_M  ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S))
+#define GPIO_FUNC211_IN_SEL_V  0x3F
+#define GPIO_FUNC211_IN_SEL_S  0
+
+#define GPIO_FUNC212_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A4)
+/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG212_IN_SEL    (BIT(7))
+#define GPIO_SIG212_IN_SEL_M  (BIT(7))
+#define GPIO_SIG212_IN_SEL_V  0x1
+#define GPIO_SIG212_IN_SEL_S  7
+/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC212_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC212_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC212_IN_INV_SEL_V  0x1
+#define GPIO_FUNC212_IN_INV_SEL_S  6
+/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC212_IN_SEL    0x0000003F
+#define GPIO_FUNC212_IN_SEL_M  ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S))
+#define GPIO_FUNC212_IN_SEL_V  0x3F
+#define GPIO_FUNC212_IN_SEL_S  0
+
+#define GPIO_FUNC213_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A8)
+/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG213_IN_SEL    (BIT(7))
+#define GPIO_SIG213_IN_SEL_M  (BIT(7))
+#define GPIO_SIG213_IN_SEL_V  0x1
+#define GPIO_SIG213_IN_SEL_S  7
+/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC213_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC213_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC213_IN_INV_SEL_V  0x1
+#define GPIO_FUNC213_IN_INV_SEL_S  6
+/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC213_IN_SEL    0x0000003F
+#define GPIO_FUNC213_IN_SEL_M  ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S))
+#define GPIO_FUNC213_IN_SEL_V  0x3F
+#define GPIO_FUNC213_IN_SEL_S  0
+
+#define GPIO_FUNC214_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4AC)
+/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG214_IN_SEL    (BIT(7))
+#define GPIO_SIG214_IN_SEL_M  (BIT(7))
+#define GPIO_SIG214_IN_SEL_V  0x1
+#define GPIO_SIG214_IN_SEL_S  7
+/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC214_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_V  0x1
+#define GPIO_FUNC214_IN_INV_SEL_S  6
+/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC214_IN_SEL    0x0000003F
+#define GPIO_FUNC214_IN_SEL_M  ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S))
+#define GPIO_FUNC214_IN_SEL_V  0x3F
+#define GPIO_FUNC214_IN_SEL_S  0
+
+#define GPIO_FUNC215_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B0)
+/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG215_IN_SEL    (BIT(7))
+#define GPIO_SIG215_IN_SEL_M  (BIT(7))
+#define GPIO_SIG215_IN_SEL_V  0x1
+#define GPIO_SIG215_IN_SEL_S  7
+/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC215_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_V  0x1
+#define GPIO_FUNC215_IN_INV_SEL_S  6
+/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC215_IN_SEL    0x0000003F
+#define GPIO_FUNC215_IN_SEL_M  ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S))
+#define GPIO_FUNC215_IN_SEL_V  0x3F
+#define GPIO_FUNC215_IN_SEL_S  0
+
+#define GPIO_FUNC216_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B4)
+/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG216_IN_SEL    (BIT(7))
+#define GPIO_SIG216_IN_SEL_M  (BIT(7))
+#define GPIO_SIG216_IN_SEL_V  0x1
+#define GPIO_SIG216_IN_SEL_S  7
+/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC216_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_V  0x1
+#define GPIO_FUNC216_IN_INV_SEL_S  6
+/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC216_IN_SEL    0x0000003F
+#define GPIO_FUNC216_IN_SEL_M  ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S))
+#define GPIO_FUNC216_IN_SEL_V  0x3F
+#define GPIO_FUNC216_IN_SEL_S  0
+
+#define GPIO_FUNC217_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B8)
+/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG217_IN_SEL    (BIT(7))
+#define GPIO_SIG217_IN_SEL_M  (BIT(7))
+#define GPIO_SIG217_IN_SEL_V  0x1
+#define GPIO_SIG217_IN_SEL_S  7
+/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC217_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_V  0x1
+#define GPIO_FUNC217_IN_INV_SEL_S  6
+/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC217_IN_SEL    0x0000003F
+#define GPIO_FUNC217_IN_SEL_M  ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S))
+#define GPIO_FUNC217_IN_SEL_V  0x3F
+#define GPIO_FUNC217_IN_SEL_S  0
+
+#define GPIO_FUNC218_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4BC)
+/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG218_IN_SEL    (BIT(7))
+#define GPIO_SIG218_IN_SEL_M  (BIT(7))
+#define GPIO_SIG218_IN_SEL_V  0x1
+#define GPIO_SIG218_IN_SEL_S  7
+/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC218_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_V  0x1
+#define GPIO_FUNC218_IN_INV_SEL_S  6
+/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC218_IN_SEL    0x0000003F
+#define GPIO_FUNC218_IN_SEL_M  ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S))
+#define GPIO_FUNC218_IN_SEL_V  0x3F
+#define GPIO_FUNC218_IN_SEL_S  0
+
+#define GPIO_FUNC219_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C0)
+/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG219_IN_SEL    (BIT(7))
+#define GPIO_SIG219_IN_SEL_M  (BIT(7))
+#define GPIO_SIG219_IN_SEL_V  0x1
+#define GPIO_SIG219_IN_SEL_S  7
+/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC219_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_V  0x1
+#define GPIO_FUNC219_IN_INV_SEL_S  6
+/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC219_IN_SEL    0x0000003F
+#define GPIO_FUNC219_IN_SEL_M  ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S))
+#define GPIO_FUNC219_IN_SEL_V  0x3F
+#define GPIO_FUNC219_IN_SEL_S  0
+
+#define GPIO_FUNC220_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C4)
+/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG220_IN_SEL    (BIT(7))
+#define GPIO_SIG220_IN_SEL_M  (BIT(7))
+#define GPIO_SIG220_IN_SEL_V  0x1
+#define GPIO_SIG220_IN_SEL_S  7
+/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC220_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_V  0x1
+#define GPIO_FUNC220_IN_INV_SEL_S  6
+/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC220_IN_SEL    0x0000003F
+#define GPIO_FUNC220_IN_SEL_M  ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S))
+#define GPIO_FUNC220_IN_SEL_V  0x3F
+#define GPIO_FUNC220_IN_SEL_S  0
+
+#define GPIO_FUNC221_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C8)
+/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG221_IN_SEL    (BIT(7))
+#define GPIO_SIG221_IN_SEL_M  (BIT(7))
+#define GPIO_SIG221_IN_SEL_V  0x1
+#define GPIO_SIG221_IN_SEL_S  7
+/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC221_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_V  0x1
+#define GPIO_FUNC221_IN_INV_SEL_S  6
+/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC221_IN_SEL    0x0000003F
+#define GPIO_FUNC221_IN_SEL_M  ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S))
+#define GPIO_FUNC221_IN_SEL_V  0x3F
+#define GPIO_FUNC221_IN_SEL_S  0
+
+#define GPIO_FUNC222_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4CC)
+/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG222_IN_SEL    (BIT(7))
+#define GPIO_SIG222_IN_SEL_M  (BIT(7))
+#define GPIO_SIG222_IN_SEL_V  0x1
+#define GPIO_SIG222_IN_SEL_S  7
+/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC222_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_V  0x1
+#define GPIO_FUNC222_IN_INV_SEL_S  6
+/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC222_IN_SEL    0x0000003F
+#define GPIO_FUNC222_IN_SEL_M  ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S))
+#define GPIO_FUNC222_IN_SEL_V  0x3F
+#define GPIO_FUNC222_IN_SEL_S  0
+
+#define GPIO_FUNC223_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D0)
+/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG223_IN_SEL    (BIT(7))
+#define GPIO_SIG223_IN_SEL_M  (BIT(7))
+#define GPIO_SIG223_IN_SEL_V  0x1
+#define GPIO_SIG223_IN_SEL_S  7
+/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC223_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_V  0x1
+#define GPIO_FUNC223_IN_INV_SEL_S  6
+/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC223_IN_SEL    0x0000003F
+#define GPIO_FUNC223_IN_SEL_M  ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S))
+#define GPIO_FUNC223_IN_SEL_V  0x3F
+#define GPIO_FUNC223_IN_SEL_S  0
+
+#define GPIO_FUNC224_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D4)
+/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG224_IN_SEL    (BIT(7))
+#define GPIO_SIG224_IN_SEL_M  (BIT(7))
+#define GPIO_SIG224_IN_SEL_V  0x1
+#define GPIO_SIG224_IN_SEL_S  7
+/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC224_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_V  0x1
+#define GPIO_FUNC224_IN_INV_SEL_S  6
+/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC224_IN_SEL    0x0000003F
+#define GPIO_FUNC224_IN_SEL_M  ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S))
+#define GPIO_FUNC224_IN_SEL_V  0x3F
+#define GPIO_FUNC224_IN_SEL_S  0
+
+#define GPIO_FUNC225_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D8)
+/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG225_IN_SEL    (BIT(7))
+#define GPIO_SIG225_IN_SEL_M  (BIT(7))
+#define GPIO_SIG225_IN_SEL_V  0x1
+#define GPIO_SIG225_IN_SEL_S  7
+/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC225_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_V  0x1
+#define GPIO_FUNC225_IN_INV_SEL_S  6
+/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC225_IN_SEL    0x0000003F
+#define GPIO_FUNC225_IN_SEL_M  ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S))
+#define GPIO_FUNC225_IN_SEL_V  0x3F
+#define GPIO_FUNC225_IN_SEL_S  0
+
+#define GPIO_FUNC226_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4DC)
+/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG226_IN_SEL    (BIT(7))
+#define GPIO_SIG226_IN_SEL_M  (BIT(7))
+#define GPIO_SIG226_IN_SEL_V  0x1
+#define GPIO_SIG226_IN_SEL_S  7
+/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC226_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_V  0x1
+#define GPIO_FUNC226_IN_INV_SEL_S  6
+/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC226_IN_SEL    0x0000003F
+#define GPIO_FUNC226_IN_SEL_M  ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S))
+#define GPIO_FUNC226_IN_SEL_V  0x3F
+#define GPIO_FUNC226_IN_SEL_S  0
+
+#define GPIO_FUNC227_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E0)
+/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG227_IN_SEL    (BIT(7))
+#define GPIO_SIG227_IN_SEL_M  (BIT(7))
+#define GPIO_SIG227_IN_SEL_V  0x1
+#define GPIO_SIG227_IN_SEL_S  7
+/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC227_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_V  0x1
+#define GPIO_FUNC227_IN_INV_SEL_S  6
+/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC227_IN_SEL    0x0000003F
+#define GPIO_FUNC227_IN_SEL_M  ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S))
+#define GPIO_FUNC227_IN_SEL_V  0x3F
+#define GPIO_FUNC227_IN_SEL_S  0
+
+#define GPIO_FUNC228_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E4)
+/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG228_IN_SEL    (BIT(7))
+#define GPIO_SIG228_IN_SEL_M  (BIT(7))
+#define GPIO_SIG228_IN_SEL_V  0x1
+#define GPIO_SIG228_IN_SEL_S  7
+/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC228_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_V  0x1
+#define GPIO_FUNC228_IN_INV_SEL_S  6
+/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC228_IN_SEL    0x0000003F
+#define GPIO_FUNC228_IN_SEL_M  ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S))
+#define GPIO_FUNC228_IN_SEL_V  0x3F
+#define GPIO_FUNC228_IN_SEL_S  0
+
+#define GPIO_FUNC229_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E8)
+/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG229_IN_SEL    (BIT(7))
+#define GPIO_SIG229_IN_SEL_M  (BIT(7))
+#define GPIO_SIG229_IN_SEL_V  0x1
+#define GPIO_SIG229_IN_SEL_S  7
+/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC229_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_V  0x1
+#define GPIO_FUNC229_IN_INV_SEL_S  6
+/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC229_IN_SEL    0x0000003F
+#define GPIO_FUNC229_IN_SEL_M  ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S))
+#define GPIO_FUNC229_IN_SEL_V  0x3F
+#define GPIO_FUNC229_IN_SEL_S  0
+
+#define GPIO_FUNC230_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4EC)
+/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG230_IN_SEL    (BIT(7))
+#define GPIO_SIG230_IN_SEL_M  (BIT(7))
+#define GPIO_SIG230_IN_SEL_V  0x1
+#define GPIO_SIG230_IN_SEL_S  7
+/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC230_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_V  0x1
+#define GPIO_FUNC230_IN_INV_SEL_S  6
+/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC230_IN_SEL    0x0000003F
+#define GPIO_FUNC230_IN_SEL_M  ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S))
+#define GPIO_FUNC230_IN_SEL_V  0x3F
+#define GPIO_FUNC230_IN_SEL_S  0
+
+#define GPIO_FUNC231_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F0)
+/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG231_IN_SEL    (BIT(7))
+#define GPIO_SIG231_IN_SEL_M  (BIT(7))
+#define GPIO_SIG231_IN_SEL_V  0x1
+#define GPIO_SIG231_IN_SEL_S  7
+/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC231_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_V  0x1
+#define GPIO_FUNC231_IN_INV_SEL_S  6
+/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC231_IN_SEL    0x0000003F
+#define GPIO_FUNC231_IN_SEL_M  ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S))
+#define GPIO_FUNC231_IN_SEL_V  0x3F
+#define GPIO_FUNC231_IN_SEL_S  0
+
+#define GPIO_FUNC232_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F4)
+/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG232_IN_SEL    (BIT(7))
+#define GPIO_SIG232_IN_SEL_M  (BIT(7))
+#define GPIO_SIG232_IN_SEL_V  0x1
+#define GPIO_SIG232_IN_SEL_S  7
+/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC232_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_V  0x1
+#define GPIO_FUNC232_IN_INV_SEL_S  6
+/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC232_IN_SEL    0x0000003F
+#define GPIO_FUNC232_IN_SEL_M  ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S))
+#define GPIO_FUNC232_IN_SEL_V  0x3F
+#define GPIO_FUNC232_IN_SEL_S  0
+
+#define GPIO_FUNC233_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F8)
+/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG233_IN_SEL    (BIT(7))
+#define GPIO_SIG233_IN_SEL_M  (BIT(7))
+#define GPIO_SIG233_IN_SEL_V  0x1
+#define GPIO_SIG233_IN_SEL_S  7
+/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC233_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_V  0x1
+#define GPIO_FUNC233_IN_INV_SEL_S  6
+/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC233_IN_SEL    0x0000003F
+#define GPIO_FUNC233_IN_SEL_M  ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S))
+#define GPIO_FUNC233_IN_SEL_V  0x3F
+#define GPIO_FUNC233_IN_SEL_S  0
+
+#define GPIO_FUNC234_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4FC)
+/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG234_IN_SEL    (BIT(7))
+#define GPIO_SIG234_IN_SEL_M  (BIT(7))
+#define GPIO_SIG234_IN_SEL_V  0x1
+#define GPIO_SIG234_IN_SEL_S  7
+/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC234_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_V  0x1
+#define GPIO_FUNC234_IN_INV_SEL_S  6
+/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC234_IN_SEL    0x0000003F
+#define GPIO_FUNC234_IN_SEL_M  ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S))
+#define GPIO_FUNC234_IN_SEL_V  0x3F
+#define GPIO_FUNC234_IN_SEL_S  0
+
+#define GPIO_FUNC235_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x500)
+/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG235_IN_SEL    (BIT(7))
+#define GPIO_SIG235_IN_SEL_M  (BIT(7))
+#define GPIO_SIG235_IN_SEL_V  0x1
+#define GPIO_SIG235_IN_SEL_S  7
+/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC235_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_V  0x1
+#define GPIO_FUNC235_IN_INV_SEL_S  6
+/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC235_IN_SEL    0x0000003F
+#define GPIO_FUNC235_IN_SEL_M  ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S))
+#define GPIO_FUNC235_IN_SEL_V  0x3F
+#define GPIO_FUNC235_IN_SEL_S  0
+
+#define GPIO_FUNC236_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x504)
+/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG236_IN_SEL    (BIT(7))
+#define GPIO_SIG236_IN_SEL_M  (BIT(7))
+#define GPIO_SIG236_IN_SEL_V  0x1
+#define GPIO_SIG236_IN_SEL_S  7
+/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC236_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_V  0x1
+#define GPIO_FUNC236_IN_INV_SEL_S  6
+/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC236_IN_SEL    0x0000003F
+#define GPIO_FUNC236_IN_SEL_M  ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S))
+#define GPIO_FUNC236_IN_SEL_V  0x3F
+#define GPIO_FUNC236_IN_SEL_S  0
+
+#define GPIO_FUNC237_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x508)
+/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG237_IN_SEL    (BIT(7))
+#define GPIO_SIG237_IN_SEL_M  (BIT(7))
+#define GPIO_SIG237_IN_SEL_V  0x1
+#define GPIO_SIG237_IN_SEL_S  7
+/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC237_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_V  0x1
+#define GPIO_FUNC237_IN_INV_SEL_S  6
+/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC237_IN_SEL    0x0000003F
+#define GPIO_FUNC237_IN_SEL_M  ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S))
+#define GPIO_FUNC237_IN_SEL_V  0x3F
+#define GPIO_FUNC237_IN_SEL_S  0
+
+#define GPIO_FUNC238_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x50C)
+/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG238_IN_SEL    (BIT(7))
+#define GPIO_SIG238_IN_SEL_M  (BIT(7))
+#define GPIO_SIG238_IN_SEL_V  0x1
+#define GPIO_SIG238_IN_SEL_S  7
+/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC238_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_V  0x1
+#define GPIO_FUNC238_IN_INV_SEL_S  6
+/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC238_IN_SEL    0x0000003F
+#define GPIO_FUNC238_IN_SEL_M  ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S))
+#define GPIO_FUNC238_IN_SEL_V  0x3F
+#define GPIO_FUNC238_IN_SEL_S  0
+
+#define GPIO_FUNC239_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x510)
+/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG239_IN_SEL    (BIT(7))
+#define GPIO_SIG239_IN_SEL_M  (BIT(7))
+#define GPIO_SIG239_IN_SEL_V  0x1
+#define GPIO_SIG239_IN_SEL_S  7
+/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC239_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_V  0x1
+#define GPIO_FUNC239_IN_INV_SEL_S  6
+/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC239_IN_SEL    0x0000003F
+#define GPIO_FUNC239_IN_SEL_M  ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S))
+#define GPIO_FUNC239_IN_SEL_V  0x3F
+#define GPIO_FUNC239_IN_SEL_S  0
+
+#define GPIO_FUNC240_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x514)
+/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG240_IN_SEL    (BIT(7))
+#define GPIO_SIG240_IN_SEL_M  (BIT(7))
+#define GPIO_SIG240_IN_SEL_V  0x1
+#define GPIO_SIG240_IN_SEL_S  7
+/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC240_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_V  0x1
+#define GPIO_FUNC240_IN_INV_SEL_S  6
+/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC240_IN_SEL    0x0000003F
+#define GPIO_FUNC240_IN_SEL_M  ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S))
+#define GPIO_FUNC240_IN_SEL_V  0x3F
+#define GPIO_FUNC240_IN_SEL_S  0
+
+#define GPIO_FUNC241_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x518)
+/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG241_IN_SEL    (BIT(7))
+#define GPIO_SIG241_IN_SEL_M  (BIT(7))
+#define GPIO_SIG241_IN_SEL_V  0x1
+#define GPIO_SIG241_IN_SEL_S  7
+/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC241_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_V  0x1
+#define GPIO_FUNC241_IN_INV_SEL_S  6
+/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC241_IN_SEL    0x0000003F
+#define GPIO_FUNC241_IN_SEL_M  ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S))
+#define GPIO_FUNC241_IN_SEL_V  0x3F
+#define GPIO_FUNC241_IN_SEL_S  0
+
+#define GPIO_FUNC242_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x51C)
+/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG242_IN_SEL    (BIT(7))
+#define GPIO_SIG242_IN_SEL_M  (BIT(7))
+#define GPIO_SIG242_IN_SEL_V  0x1
+#define GPIO_SIG242_IN_SEL_S  7
+/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC242_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_V  0x1
+#define GPIO_FUNC242_IN_INV_SEL_S  6
+/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC242_IN_SEL    0x0000003F
+#define GPIO_FUNC242_IN_SEL_M  ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S))
+#define GPIO_FUNC242_IN_SEL_V  0x3F
+#define GPIO_FUNC242_IN_SEL_S  0
+
+#define GPIO_FUNC243_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x520)
+/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG243_IN_SEL    (BIT(7))
+#define GPIO_SIG243_IN_SEL_M  (BIT(7))
+#define GPIO_SIG243_IN_SEL_V  0x1
+#define GPIO_SIG243_IN_SEL_S  7
+/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC243_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_V  0x1
+#define GPIO_FUNC243_IN_INV_SEL_S  6
+/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC243_IN_SEL    0x0000003F
+#define GPIO_FUNC243_IN_SEL_M  ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S))
+#define GPIO_FUNC243_IN_SEL_V  0x3F
+#define GPIO_FUNC243_IN_SEL_S  0
+
+#define GPIO_FUNC244_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x524)
+/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG244_IN_SEL    (BIT(7))
+#define GPIO_SIG244_IN_SEL_M  (BIT(7))
+#define GPIO_SIG244_IN_SEL_V  0x1
+#define GPIO_SIG244_IN_SEL_S  7
+/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC244_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_V  0x1
+#define GPIO_FUNC244_IN_INV_SEL_S  6
+/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC244_IN_SEL    0x0000003F
+#define GPIO_FUNC244_IN_SEL_M  ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S))
+#define GPIO_FUNC244_IN_SEL_V  0x3F
+#define GPIO_FUNC244_IN_SEL_S  0
+
+#define GPIO_FUNC245_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x528)
+/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG245_IN_SEL    (BIT(7))
+#define GPIO_SIG245_IN_SEL_M  (BIT(7))
+#define GPIO_SIG245_IN_SEL_V  0x1
+#define GPIO_SIG245_IN_SEL_S  7
+/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC245_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_V  0x1
+#define GPIO_FUNC245_IN_INV_SEL_S  6
+/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC245_IN_SEL    0x0000003F
+#define GPIO_FUNC245_IN_SEL_M  ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S))
+#define GPIO_FUNC245_IN_SEL_V  0x3F
+#define GPIO_FUNC245_IN_SEL_S  0
+
+#define GPIO_FUNC246_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x52C)
+/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG246_IN_SEL    (BIT(7))
+#define GPIO_SIG246_IN_SEL_M  (BIT(7))
+#define GPIO_SIG246_IN_SEL_V  0x1
+#define GPIO_SIG246_IN_SEL_S  7
+/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC246_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_V  0x1
+#define GPIO_FUNC246_IN_INV_SEL_S  6
+/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC246_IN_SEL    0x0000003F
+#define GPIO_FUNC246_IN_SEL_M  ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S))
+#define GPIO_FUNC246_IN_SEL_V  0x3F
+#define GPIO_FUNC246_IN_SEL_S  0
+
+#define GPIO_FUNC247_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x530)
+/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG247_IN_SEL    (BIT(7))
+#define GPIO_SIG247_IN_SEL_M  (BIT(7))
+#define GPIO_SIG247_IN_SEL_V  0x1
+#define GPIO_SIG247_IN_SEL_S  7
+/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC247_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_V  0x1
+#define GPIO_FUNC247_IN_INV_SEL_S  6
+/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC247_IN_SEL    0x0000003F
+#define GPIO_FUNC247_IN_SEL_M  ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S))
+#define GPIO_FUNC247_IN_SEL_V  0x3F
+#define GPIO_FUNC247_IN_SEL_S  0
+
+#define GPIO_FUNC248_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x534)
+/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG248_IN_SEL    (BIT(7))
+#define GPIO_SIG248_IN_SEL_M  (BIT(7))
+#define GPIO_SIG248_IN_SEL_V  0x1
+#define GPIO_SIG248_IN_SEL_S  7
+/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC248_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_V  0x1
+#define GPIO_FUNC248_IN_INV_SEL_S  6
+/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC248_IN_SEL    0x0000003F
+#define GPIO_FUNC248_IN_SEL_M  ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S))
+#define GPIO_FUNC248_IN_SEL_V  0x3F
+#define GPIO_FUNC248_IN_SEL_S  0
+
+#define GPIO_FUNC249_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x538)
+/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG249_IN_SEL    (BIT(7))
+#define GPIO_SIG249_IN_SEL_M  (BIT(7))
+#define GPIO_SIG249_IN_SEL_V  0x1
+#define GPIO_SIG249_IN_SEL_S  7
+/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC249_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_V  0x1
+#define GPIO_FUNC249_IN_INV_SEL_S  6
+/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC249_IN_SEL    0x0000003F
+#define GPIO_FUNC249_IN_SEL_M  ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S))
+#define GPIO_FUNC249_IN_SEL_V  0x3F
+#define GPIO_FUNC249_IN_SEL_S  0
+
+#define GPIO_FUNC250_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x53C)
+/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG250_IN_SEL    (BIT(7))
+#define GPIO_SIG250_IN_SEL_M  (BIT(7))
+#define GPIO_SIG250_IN_SEL_V  0x1
+#define GPIO_SIG250_IN_SEL_S  7
+/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC250_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_V  0x1
+#define GPIO_FUNC250_IN_INV_SEL_S  6
+/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC250_IN_SEL    0x0000003F
+#define GPIO_FUNC250_IN_SEL_M  ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S))
+#define GPIO_FUNC250_IN_SEL_V  0x3F
+#define GPIO_FUNC250_IN_SEL_S  0
+
+#define GPIO_FUNC251_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x540)
+/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG251_IN_SEL    (BIT(7))
+#define GPIO_SIG251_IN_SEL_M  (BIT(7))
+#define GPIO_SIG251_IN_SEL_V  0x1
+#define GPIO_SIG251_IN_SEL_S  7
+/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC251_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_V  0x1
+#define GPIO_FUNC251_IN_INV_SEL_S  6
+/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC251_IN_SEL    0x0000003F
+#define GPIO_FUNC251_IN_SEL_M  ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S))
+#define GPIO_FUNC251_IN_SEL_V  0x3F
+#define GPIO_FUNC251_IN_SEL_S  0
+
+#define GPIO_FUNC252_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x544)
+/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG252_IN_SEL    (BIT(7))
+#define GPIO_SIG252_IN_SEL_M  (BIT(7))
+#define GPIO_SIG252_IN_SEL_V  0x1
+#define GPIO_SIG252_IN_SEL_S  7
+/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC252_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_V  0x1
+#define GPIO_FUNC252_IN_INV_SEL_S  6
+/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC252_IN_SEL    0x0000003F
+#define GPIO_FUNC252_IN_SEL_M  ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S))
+#define GPIO_FUNC252_IN_SEL_V  0x3F
+#define GPIO_FUNC252_IN_SEL_S  0
+
+#define GPIO_FUNC253_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x548)
+/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG253_IN_SEL    (BIT(7))
+#define GPIO_SIG253_IN_SEL_M  (BIT(7))
+#define GPIO_SIG253_IN_SEL_V  0x1
+#define GPIO_SIG253_IN_SEL_S  7
+/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC253_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_V  0x1
+#define GPIO_FUNC253_IN_INV_SEL_S  6
+/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC253_IN_SEL    0x0000003F
+#define GPIO_FUNC253_IN_SEL_M  ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S))
+#define GPIO_FUNC253_IN_SEL_V  0x3F
+#define GPIO_FUNC253_IN_SEL_S  0
+
+#define GPIO_FUNC254_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x54C)
+/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG254_IN_SEL    (BIT(7))
+#define GPIO_SIG254_IN_SEL_M  (BIT(7))
+#define GPIO_SIG254_IN_SEL_V  0x1
+#define GPIO_SIG254_IN_SEL_S  7
+/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC254_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_V  0x1
+#define GPIO_FUNC254_IN_INV_SEL_S  6
+/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC254_IN_SEL    0x0000003F
+#define GPIO_FUNC254_IN_SEL_M  ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S))
+#define GPIO_FUNC254_IN_SEL_V  0x3F
+#define GPIO_FUNC254_IN_SEL_S  0
+
+#define GPIO_FUNC255_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x550)
+/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SIG255_IN_SEL    (BIT(7))
+#define GPIO_SIG255_IN_SEL_M  (BIT(7))
+#define GPIO_SIG255_IN_SEL_V  0x1
+#define GPIO_SIG255_IN_SEL_S  7
+/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC255_IN_INV_SEL    (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_V  0x1
+#define GPIO_FUNC255_IN_INV_SEL_S  6
+/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: .*/
+#define GPIO_FUNC255_IN_SEL    0x0000003F
+#define GPIO_FUNC255_IN_SEL_M  ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S))
+#define GPIO_FUNC255_IN_SEL_V  0x3F
+#define GPIO_FUNC255_IN_SEL_S  0
+
+#define GPIO_FUNC0_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x554)
+/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC0_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC0_OEN_INV_SEL_S  11
+/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC0_OEN_SEL    (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_V  0x1
+#define GPIO_FUNC0_OEN_SEL_S  10
+/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC0_OUT_INV_SEL_S  9
+/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC0_OUT_SEL    0x000001FF
+#define GPIO_FUNC0_OUT_SEL_M  ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
+#define GPIO_FUNC0_OUT_SEL_V  0x1FF
+#define GPIO_FUNC0_OUT_SEL_S  0
+
+#define GPIO_FUNC1_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x558)
+/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC1_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC1_OEN_INV_SEL_S  11
+/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC1_OEN_SEL    (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_V  0x1
+#define GPIO_FUNC1_OEN_SEL_S  10
+/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC1_OUT_INV_SEL_S  9
+/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC1_OUT_SEL    0x000001FF
+#define GPIO_FUNC1_OUT_SEL_M  ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
+#define GPIO_FUNC1_OUT_SEL_V  0x1FF
+#define GPIO_FUNC1_OUT_SEL_S  0
+
+#define GPIO_FUNC2_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x55C)
+/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC2_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC2_OEN_INV_SEL_S  11
+/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC2_OEN_SEL    (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_V  0x1
+#define GPIO_FUNC2_OEN_SEL_S  10
+/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC2_OUT_INV_SEL_S  9
+/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC2_OUT_SEL    0x000001FF
+#define GPIO_FUNC2_OUT_SEL_M  ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
+#define GPIO_FUNC2_OUT_SEL_V  0x1FF
+#define GPIO_FUNC2_OUT_SEL_S  0
+
+#define GPIO_FUNC3_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x560)
+/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC3_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC3_OEN_INV_SEL_S  11
+/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC3_OEN_SEL    (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_V  0x1
+#define GPIO_FUNC3_OEN_SEL_S  10
+/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC3_OUT_INV_SEL_S  9
+/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC3_OUT_SEL    0x000001FF
+#define GPIO_FUNC3_OUT_SEL_M  ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
+#define GPIO_FUNC3_OUT_SEL_V  0x1FF
+#define GPIO_FUNC3_OUT_SEL_S  0
+
+#define GPIO_FUNC4_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x564)
+/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC4_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC4_OEN_INV_SEL_S  11
+/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC4_OEN_SEL    (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_V  0x1
+#define GPIO_FUNC4_OEN_SEL_S  10
+/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC4_OUT_INV_SEL_S  9
+/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC4_OUT_SEL    0x000001FF
+#define GPIO_FUNC4_OUT_SEL_M  ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
+#define GPIO_FUNC4_OUT_SEL_V  0x1FF
+#define GPIO_FUNC4_OUT_SEL_S  0
+
+#define GPIO_FUNC5_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x568)
+/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC5_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC5_OEN_INV_SEL_S  11
+/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC5_OEN_SEL    (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_V  0x1
+#define GPIO_FUNC5_OEN_SEL_S  10
+/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC5_OUT_INV_SEL_S  9
+/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC5_OUT_SEL    0x000001FF
+#define GPIO_FUNC5_OUT_SEL_M  ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
+#define GPIO_FUNC5_OUT_SEL_V  0x1FF
+#define GPIO_FUNC5_OUT_SEL_S  0
+
+#define GPIO_FUNC6_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x56C)
+/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC6_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC6_OEN_INV_SEL_S  11
+/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC6_OEN_SEL    (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_V  0x1
+#define GPIO_FUNC6_OEN_SEL_S  10
+/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC6_OUT_INV_SEL_S  9
+/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC6_OUT_SEL    0x000001FF
+#define GPIO_FUNC6_OUT_SEL_M  ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
+#define GPIO_FUNC6_OUT_SEL_V  0x1FF
+#define GPIO_FUNC6_OUT_SEL_S  0
+
+#define GPIO_FUNC7_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x570)
+/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC7_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC7_OEN_INV_SEL_S  11
+/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC7_OEN_SEL    (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_V  0x1
+#define GPIO_FUNC7_OEN_SEL_S  10
+/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC7_OUT_INV_SEL_S  9
+/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC7_OUT_SEL    0x000001FF
+#define GPIO_FUNC7_OUT_SEL_M  ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
+#define GPIO_FUNC7_OUT_SEL_V  0x1FF
+#define GPIO_FUNC7_OUT_SEL_S  0
+
+#define GPIO_FUNC8_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x574)
+/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC8_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC8_OEN_INV_SEL_S  11
+/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC8_OEN_SEL    (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_V  0x1
+#define GPIO_FUNC8_OEN_SEL_S  10
+/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC8_OUT_INV_SEL_S  9
+/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC8_OUT_SEL    0x000001FF
+#define GPIO_FUNC8_OUT_SEL_M  ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
+#define GPIO_FUNC8_OUT_SEL_V  0x1FF
+#define GPIO_FUNC8_OUT_SEL_S  0
+
+#define GPIO_FUNC9_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x578)
+/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC9_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC9_OEN_INV_SEL_S  11
+/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC9_OEN_SEL    (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_V  0x1
+#define GPIO_FUNC9_OEN_SEL_S  10
+/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC9_OUT_INV_SEL_S  9
+/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC9_OUT_SEL    0x000001FF
+#define GPIO_FUNC9_OUT_SEL_M  ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
+#define GPIO_FUNC9_OUT_SEL_V  0x1FF
+#define GPIO_FUNC9_OUT_SEL_S  0
+
+#define GPIO_FUNC10_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x57C)
+/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC10_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC10_OEN_INV_SEL_S  11
+/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC10_OEN_SEL    (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_V  0x1
+#define GPIO_FUNC10_OEN_SEL_S  10
+/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC10_OUT_INV_SEL_S  9
+/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC10_OUT_SEL    0x000001FF
+#define GPIO_FUNC10_OUT_SEL_M  ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
+#define GPIO_FUNC10_OUT_SEL_V  0x1FF
+#define GPIO_FUNC10_OUT_SEL_S  0
+
+#define GPIO_FUNC11_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x580)
+/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC11_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC11_OEN_INV_SEL_S  11
+/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC11_OEN_SEL    (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_V  0x1
+#define GPIO_FUNC11_OEN_SEL_S  10
+/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC11_OUT_INV_SEL_S  9
+/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC11_OUT_SEL    0x000001FF
+#define GPIO_FUNC11_OUT_SEL_M  ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
+#define GPIO_FUNC11_OUT_SEL_V  0x1FF
+#define GPIO_FUNC11_OUT_SEL_S  0
+
+#define GPIO_FUNC12_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x584)
+/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC12_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC12_OEN_INV_SEL_S  11
+/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC12_OEN_SEL    (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_V  0x1
+#define GPIO_FUNC12_OEN_SEL_S  10
+/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC12_OUT_INV_SEL_S  9
+/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC12_OUT_SEL    0x000001FF
+#define GPIO_FUNC12_OUT_SEL_M  ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
+#define GPIO_FUNC12_OUT_SEL_V  0x1FF
+#define GPIO_FUNC12_OUT_SEL_S  0
+
+#define GPIO_FUNC13_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x588)
+/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC13_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC13_OEN_INV_SEL_S  11
+/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC13_OEN_SEL    (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_V  0x1
+#define GPIO_FUNC13_OEN_SEL_S  10
+/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC13_OUT_INV_SEL_S  9
+/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC13_OUT_SEL    0x000001FF
+#define GPIO_FUNC13_OUT_SEL_M  ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
+#define GPIO_FUNC13_OUT_SEL_V  0x1FF
+#define GPIO_FUNC13_OUT_SEL_S  0
+
+#define GPIO_FUNC14_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x58C)
+/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC14_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC14_OEN_INV_SEL_S  11
+/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC14_OEN_SEL    (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_V  0x1
+#define GPIO_FUNC14_OEN_SEL_S  10
+/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC14_OUT_INV_SEL_S  9
+/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC14_OUT_SEL    0x000001FF
+#define GPIO_FUNC14_OUT_SEL_M  ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
+#define GPIO_FUNC14_OUT_SEL_V  0x1FF
+#define GPIO_FUNC14_OUT_SEL_S  0
+
+#define GPIO_FUNC15_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x590)
+/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC15_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC15_OEN_INV_SEL_S  11
+/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC15_OEN_SEL    (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_V  0x1
+#define GPIO_FUNC15_OEN_SEL_S  10
+/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC15_OUT_INV_SEL_S  9
+/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC15_OUT_SEL    0x000001FF
+#define GPIO_FUNC15_OUT_SEL_M  ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
+#define GPIO_FUNC15_OUT_SEL_V  0x1FF
+#define GPIO_FUNC15_OUT_SEL_S  0
+
+#define GPIO_FUNC16_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x594)
+/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC16_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC16_OEN_INV_SEL_S  11
+/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC16_OEN_SEL    (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_V  0x1
+#define GPIO_FUNC16_OEN_SEL_S  10
+/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC16_OUT_INV_SEL_S  9
+/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC16_OUT_SEL    0x000001FF
+#define GPIO_FUNC16_OUT_SEL_M  ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
+#define GPIO_FUNC16_OUT_SEL_V  0x1FF
+#define GPIO_FUNC16_OUT_SEL_S  0
+
+#define GPIO_FUNC17_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x598)
+/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC17_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC17_OEN_INV_SEL_S  11
+/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC17_OEN_SEL    (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_V  0x1
+#define GPIO_FUNC17_OEN_SEL_S  10
+/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC17_OUT_INV_SEL_S  9
+/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC17_OUT_SEL    0x000001FF
+#define GPIO_FUNC17_OUT_SEL_M  ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
+#define GPIO_FUNC17_OUT_SEL_V  0x1FF
+#define GPIO_FUNC17_OUT_SEL_S  0
+
+#define GPIO_FUNC18_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x59C)
+/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC18_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC18_OEN_INV_SEL_S  11
+/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC18_OEN_SEL    (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_V  0x1
+#define GPIO_FUNC18_OEN_SEL_S  10
+/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC18_OUT_INV_SEL_S  9
+/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC18_OUT_SEL    0x000001FF
+#define GPIO_FUNC18_OUT_SEL_M  ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
+#define GPIO_FUNC18_OUT_SEL_V  0x1FF
+#define GPIO_FUNC18_OUT_SEL_S  0
+
+#define GPIO_FUNC19_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A0)
+/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC19_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC19_OEN_INV_SEL_S  11
+/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC19_OEN_SEL    (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_V  0x1
+#define GPIO_FUNC19_OEN_SEL_S  10
+/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC19_OUT_INV_SEL_S  9
+/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC19_OUT_SEL    0x000001FF
+#define GPIO_FUNC19_OUT_SEL_M  ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
+#define GPIO_FUNC19_OUT_SEL_V  0x1FF
+#define GPIO_FUNC19_OUT_SEL_S  0
+
+#define GPIO_FUNC20_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A4)
+/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC20_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC20_OEN_INV_SEL_S  11
+/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC20_OEN_SEL    (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_V  0x1
+#define GPIO_FUNC20_OEN_SEL_S  10
+/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC20_OUT_INV_SEL_S  9
+/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC20_OUT_SEL    0x000001FF
+#define GPIO_FUNC20_OUT_SEL_M  ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
+#define GPIO_FUNC20_OUT_SEL_V  0x1FF
+#define GPIO_FUNC20_OUT_SEL_S  0
+
+#define GPIO_FUNC21_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A8)
+/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC21_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC21_OEN_INV_SEL_S  11
+/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC21_OEN_SEL    (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_V  0x1
+#define GPIO_FUNC21_OEN_SEL_S  10
+/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC21_OUT_INV_SEL_S  9
+/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC21_OUT_SEL    0x000001FF
+#define GPIO_FUNC21_OUT_SEL_M  ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
+#define GPIO_FUNC21_OUT_SEL_V  0x1FF
+#define GPIO_FUNC21_OUT_SEL_S  0
+
+#define GPIO_FUNC22_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5AC)
+/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC22_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC22_OEN_INV_SEL_S  11
+/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC22_OEN_SEL    (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_V  0x1
+#define GPIO_FUNC22_OEN_SEL_S  10
+/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC22_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC22_OUT_INV_SEL_S  9
+/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC22_OUT_SEL    0x000001FF
+#define GPIO_FUNC22_OUT_SEL_M  ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
+#define GPIO_FUNC22_OUT_SEL_V  0x1FF
+#define GPIO_FUNC22_OUT_SEL_S  0
+
+#define GPIO_FUNC23_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B0)
+/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC23_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC23_OEN_INV_SEL_S  11
+/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC23_OEN_SEL    (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_V  0x1
+#define GPIO_FUNC23_OEN_SEL_S  10
+/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC23_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC23_OUT_INV_SEL_S  9
+/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC23_OUT_SEL    0x000001FF
+#define GPIO_FUNC23_OUT_SEL_M  ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
+#define GPIO_FUNC23_OUT_SEL_V  0x1FF
+#define GPIO_FUNC23_OUT_SEL_S  0
+
+#define GPIO_FUNC24_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B4)
+/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC24_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC24_OEN_INV_SEL_S  11
+/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC24_OEN_SEL    (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_V  0x1
+#define GPIO_FUNC24_OEN_SEL_S  10
+/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC24_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC24_OUT_INV_SEL_S  9
+/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC24_OUT_SEL    0x000001FF
+#define GPIO_FUNC24_OUT_SEL_M  ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
+#define GPIO_FUNC24_OUT_SEL_V  0x1FF
+#define GPIO_FUNC24_OUT_SEL_S  0
+
+#define GPIO_FUNC25_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B8)
+/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC25_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC25_OEN_INV_SEL_S  11
+/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC25_OEN_SEL    (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_V  0x1
+#define GPIO_FUNC25_OEN_SEL_S  10
+/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC25_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC25_OUT_INV_SEL_S  9
+/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC25_OUT_SEL    0x000001FF
+#define GPIO_FUNC25_OUT_SEL_M  ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
+#define GPIO_FUNC25_OUT_SEL_V  0x1FF
+#define GPIO_FUNC25_OUT_SEL_S  0
+
+#define GPIO_FUNC26_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5BC)
+/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC26_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC26_OEN_INV_SEL_S  11
+/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC26_OEN_SEL    (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_V  0x1
+#define GPIO_FUNC26_OEN_SEL_S  10
+/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC26_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC26_OUT_INV_SEL_S  9
+/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC26_OUT_SEL    0x000001FF
+#define GPIO_FUNC26_OUT_SEL_M  ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S))
+#define GPIO_FUNC26_OUT_SEL_V  0x1FF
+#define GPIO_FUNC26_OUT_SEL_S  0
+
+#define GPIO_FUNC27_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C0)
+/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC27_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC27_OEN_INV_SEL_S  11
+/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC27_OEN_SEL    (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_V  0x1
+#define GPIO_FUNC27_OEN_SEL_S  10
+/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC27_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC27_OUT_INV_SEL_S  9
+/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC27_OUT_SEL    0x000001FF
+#define GPIO_FUNC27_OUT_SEL_M  ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S))
+#define GPIO_FUNC27_OUT_SEL_V  0x1FF
+#define GPIO_FUNC27_OUT_SEL_S  0
+
+#define GPIO_FUNC28_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C4)
+/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC28_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC28_OEN_INV_SEL_S  11
+/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC28_OEN_SEL    (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_V  0x1
+#define GPIO_FUNC28_OEN_SEL_S  10
+/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC28_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC28_OUT_INV_SEL_S  9
+/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC28_OUT_SEL    0x000001FF
+#define GPIO_FUNC28_OUT_SEL_M  ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S))
+#define GPIO_FUNC28_OUT_SEL_V  0x1FF
+#define GPIO_FUNC28_OUT_SEL_S  0
+
+#define GPIO_FUNC29_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C8)
+/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC29_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC29_OEN_INV_SEL_S  11
+/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC29_OEN_SEL    (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_V  0x1
+#define GPIO_FUNC29_OEN_SEL_S  10
+/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC29_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC29_OUT_INV_SEL_S  9
+/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC29_OUT_SEL    0x000001FF
+#define GPIO_FUNC29_OUT_SEL_M  ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S))
+#define GPIO_FUNC29_OUT_SEL_V  0x1FF
+#define GPIO_FUNC29_OUT_SEL_S  0
+
+#define GPIO_FUNC30_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5CC)
+/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC30_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC30_OEN_INV_SEL_S  11
+/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC30_OEN_SEL    (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_V  0x1
+#define GPIO_FUNC30_OEN_SEL_S  10
+/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC30_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC30_OUT_INV_SEL_S  9
+/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC30_OUT_SEL    0x000001FF
+#define GPIO_FUNC30_OUT_SEL_M  ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S))
+#define GPIO_FUNC30_OUT_SEL_V  0x1FF
+#define GPIO_FUNC30_OUT_SEL_S  0
+
+#define GPIO_FUNC31_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D0)
+/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC31_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC31_OEN_INV_SEL_S  11
+/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC31_OEN_SEL    (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_V  0x1
+#define GPIO_FUNC31_OEN_SEL_S  10
+/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC31_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC31_OUT_INV_SEL_S  9
+/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC31_OUT_SEL    0x000001FF
+#define GPIO_FUNC31_OUT_SEL_M  ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S))
+#define GPIO_FUNC31_OUT_SEL_V  0x1FF
+#define GPIO_FUNC31_OUT_SEL_S  0
+
+#define GPIO_FUNC32_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D4)
+/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC32_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC32_OEN_INV_SEL_S  11
+/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC32_OEN_SEL    (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_V  0x1
+#define GPIO_FUNC32_OEN_SEL_S  10
+/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC32_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC32_OUT_INV_SEL_S  9
+/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC32_OUT_SEL    0x000001FF
+#define GPIO_FUNC32_OUT_SEL_M  ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S))
+#define GPIO_FUNC32_OUT_SEL_V  0x1FF
+#define GPIO_FUNC32_OUT_SEL_S  0
+
+#define GPIO_FUNC33_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D8)
+/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC33_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC33_OEN_INV_SEL_S  11
+/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC33_OEN_SEL    (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_V  0x1
+#define GPIO_FUNC33_OEN_SEL_S  10
+/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC33_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC33_OUT_INV_SEL_S  9
+/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC33_OUT_SEL    0x000001FF
+#define GPIO_FUNC33_OUT_SEL_M  ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S))
+#define GPIO_FUNC33_OUT_SEL_V  0x1FF
+#define GPIO_FUNC33_OUT_SEL_S  0
+
+#define GPIO_FUNC34_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5DC)
+/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC34_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC34_OEN_INV_SEL_S  11
+/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC34_OEN_SEL    (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_V  0x1
+#define GPIO_FUNC34_OEN_SEL_S  10
+/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC34_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC34_OUT_INV_SEL_S  9
+/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC34_OUT_SEL    0x000001FF
+#define GPIO_FUNC34_OUT_SEL_M  ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S))
+#define GPIO_FUNC34_OUT_SEL_V  0x1FF
+#define GPIO_FUNC34_OUT_SEL_S  0
+
+#define GPIO_FUNC35_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E0)
+/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC35_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC35_OEN_INV_SEL_S  11
+/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC35_OEN_SEL    (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_V  0x1
+#define GPIO_FUNC35_OEN_SEL_S  10
+/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC35_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC35_OUT_INV_SEL_S  9
+/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC35_OUT_SEL    0x000001FF
+#define GPIO_FUNC35_OUT_SEL_M  ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S))
+#define GPIO_FUNC35_OUT_SEL_V  0x1FF
+#define GPIO_FUNC35_OUT_SEL_S  0
+
+#define GPIO_FUNC36_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E4)
+/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC36_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC36_OEN_INV_SEL_S  11
+/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC36_OEN_SEL    (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_V  0x1
+#define GPIO_FUNC36_OEN_SEL_S  10
+/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC36_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC36_OUT_INV_SEL_S  9
+/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC36_OUT_SEL    0x000001FF
+#define GPIO_FUNC36_OUT_SEL_M  ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S))
+#define GPIO_FUNC36_OUT_SEL_V  0x1FF
+#define GPIO_FUNC36_OUT_SEL_S  0
+
+#define GPIO_FUNC37_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E8)
+/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC37_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC37_OEN_INV_SEL_S  11
+/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC37_OEN_SEL    (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_V  0x1
+#define GPIO_FUNC37_OEN_SEL_S  10
+/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC37_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC37_OUT_INV_SEL_S  9
+/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC37_OUT_SEL    0x000001FF
+#define GPIO_FUNC37_OUT_SEL_M  ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S))
+#define GPIO_FUNC37_OUT_SEL_V  0x1FF
+#define GPIO_FUNC37_OUT_SEL_S  0
+
+#define GPIO_FUNC38_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5EC)
+/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC38_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC38_OEN_INV_SEL_S  11
+/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC38_OEN_SEL    (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_V  0x1
+#define GPIO_FUNC38_OEN_SEL_S  10
+/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC38_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC38_OUT_INV_SEL_S  9
+/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC38_OUT_SEL    0x000001FF
+#define GPIO_FUNC38_OUT_SEL_M  ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S))
+#define GPIO_FUNC38_OUT_SEL_V  0x1FF
+#define GPIO_FUNC38_OUT_SEL_S  0
+
+#define GPIO_FUNC39_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F0)
+/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC39_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC39_OEN_INV_SEL_S  11
+/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC39_OEN_SEL    (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_V  0x1
+#define GPIO_FUNC39_OEN_SEL_S  10
+/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC39_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC39_OUT_INV_SEL_S  9
+/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC39_OUT_SEL    0x000001FF
+#define GPIO_FUNC39_OUT_SEL_M  ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S))
+#define GPIO_FUNC39_OUT_SEL_V  0x1FF
+#define GPIO_FUNC39_OUT_SEL_S  0
+
+#define GPIO_FUNC40_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F4)
+/* GPIO_FUNC40_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC40_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC40_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC40_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC40_OEN_INV_SEL_S  11
+/* GPIO_FUNC40_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC40_OEN_SEL    (BIT(10))
+#define GPIO_FUNC40_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC40_OEN_SEL_V  0x1
+#define GPIO_FUNC40_OEN_SEL_S  10
+/* GPIO_FUNC40_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC40_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC40_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC40_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC40_OUT_INV_SEL_S  9
+/* GPIO_FUNC40_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC40_OUT_SEL    0x000001FF
+#define GPIO_FUNC40_OUT_SEL_M  ((GPIO_FUNC40_OUT_SEL_V)<<(GPIO_FUNC40_OUT_SEL_S))
+#define GPIO_FUNC40_OUT_SEL_V  0x1FF
+#define GPIO_FUNC40_OUT_SEL_S  0
+
+#define GPIO_FUNC41_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F8)
+/* GPIO_FUNC41_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC41_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC41_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC41_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC41_OEN_INV_SEL_S  11
+/* GPIO_FUNC41_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC41_OEN_SEL    (BIT(10))
+#define GPIO_FUNC41_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC41_OEN_SEL_V  0x1
+#define GPIO_FUNC41_OEN_SEL_S  10
+/* GPIO_FUNC41_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC41_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC41_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC41_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC41_OUT_INV_SEL_S  9
+/* GPIO_FUNC41_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC41_OUT_SEL    0x000001FF
+#define GPIO_FUNC41_OUT_SEL_M  ((GPIO_FUNC41_OUT_SEL_V)<<(GPIO_FUNC41_OUT_SEL_S))
+#define GPIO_FUNC41_OUT_SEL_V  0x1FF
+#define GPIO_FUNC41_OUT_SEL_S  0
+
+#define GPIO_FUNC42_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5FC)
+/* GPIO_FUNC42_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC42_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC42_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC42_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC42_OEN_INV_SEL_S  11
+/* GPIO_FUNC42_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC42_OEN_SEL    (BIT(10))
+#define GPIO_FUNC42_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC42_OEN_SEL_V  0x1
+#define GPIO_FUNC42_OEN_SEL_S  10
+/* GPIO_FUNC42_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC42_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC42_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC42_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC42_OUT_INV_SEL_S  9
+/* GPIO_FUNC42_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC42_OUT_SEL    0x000001FF
+#define GPIO_FUNC42_OUT_SEL_M  ((GPIO_FUNC42_OUT_SEL_V)<<(GPIO_FUNC42_OUT_SEL_S))
+#define GPIO_FUNC42_OUT_SEL_V  0x1FF
+#define GPIO_FUNC42_OUT_SEL_S  0
+
+#define GPIO_FUNC43_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x600)
+/* GPIO_FUNC43_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC43_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC43_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC43_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC43_OEN_INV_SEL_S  11
+/* GPIO_FUNC43_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC43_OEN_SEL    (BIT(10))
+#define GPIO_FUNC43_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC43_OEN_SEL_V  0x1
+#define GPIO_FUNC43_OEN_SEL_S  10
+/* GPIO_FUNC43_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC43_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC43_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC43_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC43_OUT_INV_SEL_S  9
+/* GPIO_FUNC43_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC43_OUT_SEL    0x000001FF
+#define GPIO_FUNC43_OUT_SEL_M  ((GPIO_FUNC43_OUT_SEL_V)<<(GPIO_FUNC43_OUT_SEL_S))
+#define GPIO_FUNC43_OUT_SEL_V  0x1FF
+#define GPIO_FUNC43_OUT_SEL_S  0
+
+#define GPIO_FUNC44_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x604)
+/* GPIO_FUNC44_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC44_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC44_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC44_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC44_OEN_INV_SEL_S  11
+/* GPIO_FUNC44_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC44_OEN_SEL    (BIT(10))
+#define GPIO_FUNC44_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC44_OEN_SEL_V  0x1
+#define GPIO_FUNC44_OEN_SEL_S  10
+/* GPIO_FUNC44_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC44_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC44_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC44_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC44_OUT_INV_SEL_S  9
+/* GPIO_FUNC44_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC44_OUT_SEL    0x000001FF
+#define GPIO_FUNC44_OUT_SEL_M  ((GPIO_FUNC44_OUT_SEL_V)<<(GPIO_FUNC44_OUT_SEL_S))
+#define GPIO_FUNC44_OUT_SEL_V  0x1FF
+#define GPIO_FUNC44_OUT_SEL_S  0
+
+#define GPIO_FUNC45_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x608)
+/* GPIO_FUNC45_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC45_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC45_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC45_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC45_OEN_INV_SEL_S  11
+/* GPIO_FUNC45_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC45_OEN_SEL    (BIT(10))
+#define GPIO_FUNC45_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC45_OEN_SEL_V  0x1
+#define GPIO_FUNC45_OEN_SEL_S  10
+/* GPIO_FUNC45_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC45_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC45_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC45_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC45_OUT_INV_SEL_S  9
+/* GPIO_FUNC45_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC45_OUT_SEL    0x000001FF
+#define GPIO_FUNC45_OUT_SEL_M  ((GPIO_FUNC45_OUT_SEL_V)<<(GPIO_FUNC45_OUT_SEL_S))
+#define GPIO_FUNC45_OUT_SEL_V  0x1FF
+#define GPIO_FUNC45_OUT_SEL_S  0
+
+#define GPIO_FUNC46_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x60C)
+/* GPIO_FUNC46_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC46_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC46_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC46_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC46_OEN_INV_SEL_S  11
+/* GPIO_FUNC46_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC46_OEN_SEL    (BIT(10))
+#define GPIO_FUNC46_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC46_OEN_SEL_V  0x1
+#define GPIO_FUNC46_OEN_SEL_S  10
+/* GPIO_FUNC46_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC46_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC46_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC46_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC46_OUT_INV_SEL_S  9
+/* GPIO_FUNC46_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC46_OUT_SEL    0x000001FF
+#define GPIO_FUNC46_OUT_SEL_M  ((GPIO_FUNC46_OUT_SEL_V)<<(GPIO_FUNC46_OUT_SEL_S))
+#define GPIO_FUNC46_OUT_SEL_V  0x1FF
+#define GPIO_FUNC46_OUT_SEL_S  0
+
+#define GPIO_FUNC47_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x610)
+/* GPIO_FUNC47_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC47_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC47_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC47_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC47_OEN_INV_SEL_S  11
+/* GPIO_FUNC47_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC47_OEN_SEL    (BIT(10))
+#define GPIO_FUNC47_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC47_OEN_SEL_V  0x1
+#define GPIO_FUNC47_OEN_SEL_S  10
+/* GPIO_FUNC47_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC47_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC47_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC47_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC47_OUT_INV_SEL_S  9
+/* GPIO_FUNC47_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC47_OUT_SEL    0x000001FF
+#define GPIO_FUNC47_OUT_SEL_M  ((GPIO_FUNC47_OUT_SEL_V)<<(GPIO_FUNC47_OUT_SEL_S))
+#define GPIO_FUNC47_OUT_SEL_V  0x1FF
+#define GPIO_FUNC47_OUT_SEL_S  0
+
+#define GPIO_FUNC48_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x614)
+/* GPIO_FUNC48_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC48_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC48_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC48_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC48_OEN_INV_SEL_S  11
+/* GPIO_FUNC48_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC48_OEN_SEL    (BIT(10))
+#define GPIO_FUNC48_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC48_OEN_SEL_V  0x1
+#define GPIO_FUNC48_OEN_SEL_S  10
+/* GPIO_FUNC48_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC48_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC48_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC48_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC48_OUT_INV_SEL_S  9
+/* GPIO_FUNC48_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC48_OUT_SEL    0x000001FF
+#define GPIO_FUNC48_OUT_SEL_M  ((GPIO_FUNC48_OUT_SEL_V)<<(GPIO_FUNC48_OUT_SEL_S))
+#define GPIO_FUNC48_OUT_SEL_V  0x1FF
+#define GPIO_FUNC48_OUT_SEL_S  0
+
+#define GPIO_FUNC49_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x618)
+/* GPIO_FUNC49_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC49_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC49_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC49_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC49_OEN_INV_SEL_S  11
+/* GPIO_FUNC49_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC49_OEN_SEL    (BIT(10))
+#define GPIO_FUNC49_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC49_OEN_SEL_V  0x1
+#define GPIO_FUNC49_OEN_SEL_S  10
+/* GPIO_FUNC49_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC49_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC49_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC49_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC49_OUT_INV_SEL_S  9
+/* GPIO_FUNC49_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC49_OUT_SEL    0x000001FF
+#define GPIO_FUNC49_OUT_SEL_M  ((GPIO_FUNC49_OUT_SEL_V)<<(GPIO_FUNC49_OUT_SEL_S))
+#define GPIO_FUNC49_OUT_SEL_V  0x1FF
+#define GPIO_FUNC49_OUT_SEL_S  0
+
+#define GPIO_FUNC50_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x61C)
+/* GPIO_FUNC50_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC50_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC50_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC50_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC50_OEN_INV_SEL_S  11
+/* GPIO_FUNC50_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC50_OEN_SEL    (BIT(10))
+#define GPIO_FUNC50_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC50_OEN_SEL_V  0x1
+#define GPIO_FUNC50_OEN_SEL_S  10
+/* GPIO_FUNC50_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC50_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC50_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC50_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC50_OUT_INV_SEL_S  9
+/* GPIO_FUNC50_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC50_OUT_SEL    0x000001FF
+#define GPIO_FUNC50_OUT_SEL_M  ((GPIO_FUNC50_OUT_SEL_V)<<(GPIO_FUNC50_OUT_SEL_S))
+#define GPIO_FUNC50_OUT_SEL_V  0x1FF
+#define GPIO_FUNC50_OUT_SEL_S  0
+
+#define GPIO_FUNC51_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x620)
+/* GPIO_FUNC51_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC51_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC51_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC51_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC51_OEN_INV_SEL_S  11
+/* GPIO_FUNC51_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC51_OEN_SEL    (BIT(10))
+#define GPIO_FUNC51_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC51_OEN_SEL_V  0x1
+#define GPIO_FUNC51_OEN_SEL_S  10
+/* GPIO_FUNC51_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC51_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC51_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC51_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC51_OUT_INV_SEL_S  9
+/* GPIO_FUNC51_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC51_OUT_SEL    0x000001FF
+#define GPIO_FUNC51_OUT_SEL_M  ((GPIO_FUNC51_OUT_SEL_V)<<(GPIO_FUNC51_OUT_SEL_S))
+#define GPIO_FUNC51_OUT_SEL_V  0x1FF
+#define GPIO_FUNC51_OUT_SEL_S  0
+
+#define GPIO_FUNC52_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x624)
+/* GPIO_FUNC52_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC52_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC52_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC52_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC52_OEN_INV_SEL_S  11
+/* GPIO_FUNC52_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC52_OEN_SEL    (BIT(10))
+#define GPIO_FUNC52_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC52_OEN_SEL_V  0x1
+#define GPIO_FUNC52_OEN_SEL_S  10
+/* GPIO_FUNC52_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC52_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC52_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC52_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC52_OUT_INV_SEL_S  9
+/* GPIO_FUNC52_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC52_OUT_SEL    0x000001FF
+#define GPIO_FUNC52_OUT_SEL_M  ((GPIO_FUNC52_OUT_SEL_V)<<(GPIO_FUNC52_OUT_SEL_S))
+#define GPIO_FUNC52_OUT_SEL_V  0x1FF
+#define GPIO_FUNC52_OUT_SEL_S  0
+
+#define GPIO_FUNC53_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x628)
+/* GPIO_FUNC53_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC53_OEN_INV_SEL    (BIT(11))
+#define GPIO_FUNC53_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC53_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC53_OEN_INV_SEL_S  11
+/* GPIO_FUNC53_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC53_OEN_SEL    (BIT(10))
+#define GPIO_FUNC53_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC53_OEN_SEL_V  0x1
+#define GPIO_FUNC53_OEN_SEL_S  10
+/* GPIO_FUNC53_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_FUNC53_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC53_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC53_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC53_OUT_INV_SEL_S  9
+/* GPIO_FUNC53_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: .*/
+#define GPIO_FUNC53_OUT_SEL    0x000001FF
+#define GPIO_FUNC53_OUT_SEL_M  ((GPIO_FUNC53_OUT_SEL_V)<<(GPIO_FUNC53_OUT_SEL_S))
+#define GPIO_FUNC53_OUT_SEL_V  0x1FF
+#define GPIO_FUNC53_OUT_SEL_S  0
+
+#define GPIO_CLOCK_GATE_REG          (DR_REG_GPIO_BASE + 0x62C)
+/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define GPIO_CLK_EN    (BIT(0))
+#define GPIO_CLK_EN_M  (BIT(0))
+#define GPIO_CLK_EN_V  0x1
+#define GPIO_CLK_EN_S  0
+
+#define GPIO_DATE_REG          (DR_REG_GPIO_BASE + 0x6FC)
+/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1907040 ; */
+/*description: .*/
+#define GPIO_DATE    0x0FFFFFFF
+#define GPIO_DATE_M  ((GPIO_DATE_V)<<(GPIO_DATE_S))
+#define GPIO_DATE_V  0xFFFFFFF
+#define GPIO_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_GPIO_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/gpio_sd_reg.h b/components/soc/esp32s3/register/soc/gpio_sd_reg.h
new file mode 100644
index 00000000000..f171b12dae5
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/gpio_sd_reg.h
@@ -0,0 +1,159 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0)
+/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: .*/
+#define GPIO_SD0_PRESCALE    0x000000FF
+#define GPIO_SD0_PRESCALE_M  ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
+#define GPIO_SD0_PRESCALE_V  0xFF
+#define GPIO_SD0_PRESCALE_S  8
+/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SD0_IN    0x000000FF
+#define GPIO_SD0_IN_M  ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
+#define GPIO_SD0_IN_V  0xFF
+#define GPIO_SD0_IN_S  0
+
+#define GPIO_SIGMADELTA1_REG          (DR_REG_GPIO_SD_BASE + 0x4)
+/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: .*/
+#define GPIO_SD1_PRESCALE    0x000000FF
+#define GPIO_SD1_PRESCALE_M  ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
+#define GPIO_SD1_PRESCALE_V  0xFF
+#define GPIO_SD1_PRESCALE_S  8
+/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SD1_IN    0x000000FF
+#define GPIO_SD1_IN_M  ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
+#define GPIO_SD1_IN_V  0xFF
+#define GPIO_SD1_IN_S  0
+
+#define GPIO_SIGMADELTA2_REG          (DR_REG_GPIO_SD_BASE + 0x8)
+/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: .*/
+#define GPIO_SD2_PRESCALE    0x000000FF
+#define GPIO_SD2_PRESCALE_M  ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
+#define GPIO_SD2_PRESCALE_V  0xFF
+#define GPIO_SD2_PRESCALE_S  8
+/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SD2_IN    0x000000FF
+#define GPIO_SD2_IN_M  ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
+#define GPIO_SD2_IN_V  0xFF
+#define GPIO_SD2_IN_S  0
+
+#define GPIO_SIGMADELTA3_REG          (DR_REG_GPIO_SD_BASE + 0xC)
+/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: .*/
+#define GPIO_SD3_PRESCALE    0x000000FF
+#define GPIO_SD3_PRESCALE_M  ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
+#define GPIO_SD3_PRESCALE_V  0xFF
+#define GPIO_SD3_PRESCALE_S  8
+/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SD3_IN    0x000000FF
+#define GPIO_SD3_IN_M  ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
+#define GPIO_SD3_IN_V  0xFF
+#define GPIO_SD3_IN_S  0
+
+#define GPIO_SIGMADELTA4_REG          (DR_REG_GPIO_SD_BASE + 0x10)
+/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: .*/
+#define GPIO_SD4_PRESCALE    0x000000FF
+#define GPIO_SD4_PRESCALE_M  ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
+#define GPIO_SD4_PRESCALE_V  0xFF
+#define GPIO_SD4_PRESCALE_S  8
+/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SD4_IN    0x000000FF
+#define GPIO_SD4_IN_M  ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
+#define GPIO_SD4_IN_V  0xFF
+#define GPIO_SD4_IN_S  0
+
+#define GPIO_SIGMADELTA5_REG          (DR_REG_GPIO_SD_BASE + 0x14)
+/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: .*/
+#define GPIO_SD5_PRESCALE    0x000000FF
+#define GPIO_SD5_PRESCALE_M  ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
+#define GPIO_SD5_PRESCALE_V  0xFF
+#define GPIO_SD5_PRESCALE_S  8
+/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SD5_IN    0x000000FF
+#define GPIO_SD5_IN_M  ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
+#define GPIO_SD5_IN_V  0xFF
+#define GPIO_SD5_IN_S  0
+
+#define GPIO_SIGMADELTA6_REG          (DR_REG_GPIO_SD_BASE + 0x18)
+/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: .*/
+#define GPIO_SD6_PRESCALE    0x000000FF
+#define GPIO_SD6_PRESCALE_M  ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
+#define GPIO_SD6_PRESCALE_V  0xFF
+#define GPIO_SD6_PRESCALE_S  8
+/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SD6_IN    0x000000FF
+#define GPIO_SD6_IN_M  ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
+#define GPIO_SD6_IN_V  0xFF
+#define GPIO_SD6_IN_S  0
+
+#define GPIO_SIGMADELTA7_REG          (DR_REG_GPIO_SD_BASE + 0x1C)
+/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: .*/
+#define GPIO_SD7_PRESCALE    0x000000FF
+#define GPIO_SD7_PRESCALE_M  ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
+#define GPIO_SD7_PRESCALE_V  0xFF
+#define GPIO_SD7_PRESCALE_S  8
+/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define GPIO_SD7_IN    0x000000FF
+#define GPIO_SD7_IN_M  ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
+#define GPIO_SD7_IN_V  0xFF
+#define GPIO_SD7_IN_S  0
+
+#define GPIO_SIGMADELTA_CG_REG          (DR_REG_GPIO_SD_BASE + 0x20)
+/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SD_CLK_EN    (BIT(31))
+#define GPIO_SD_CLK_EN_M  (BIT(31))
+#define GPIO_SD_CLK_EN_V  0x1
+#define GPIO_SD_CLK_EN_S  31
+
+#define GPIO_SIGMADELTA_MISC_REG          (DR_REG_GPIO_SD_BASE + 0x24)
+/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define GPIO_SPI_SWAP    (BIT(31))
+#define GPIO_SPI_SWAP_M  (BIT(31))
+#define GPIO_SPI_SWAP_V  0x1
+#define GPIO_SPI_SWAP_S  31
+/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: .*/
+#define GPIO_FUNCTION_CLK_EN    (BIT(30))
+#define GPIO_FUNCTION_CLK_EN_M  (BIT(30))
+#define GPIO_FUNCTION_CLK_EN_V  0x1
+#define GPIO_FUNCTION_CLK_EN_S  30
+
+#define GPIO_SIGMADELTA_VERSION_REG          (DR_REG_GPIO_SD_BASE + 0x28)
+/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
+/*description: .*/
+#define GPIO_SD_DATE    0x0FFFFFFF
+#define GPIO_SD_DATE_M  ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
+#define GPIO_SD_DATE_V  0xFFFFFFF
+#define GPIO_SD_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/include/soc/gpio_sd_struct.h b/components/soc/esp32s3/register/soc/gpio_sd_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/gpio_sd_struct.h
rename to components/soc/esp32s3/register/soc/gpio_sd_struct.h
diff --git a/components/soc/esp32s3/include/soc/gpio_struct.h b/components/soc/esp32s3/register/soc/gpio_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/gpio_struct.h
rename to components/soc/esp32s3/register/soc/gpio_struct.h
diff --git a/components/soc/esp32s3/include/soc/hinf_reg.h b/components/soc/esp32s3/register/soc/hinf_reg.h
similarity index 93%
rename from components/soc/esp32s3/include/soc/hinf_reg.h
rename to components/soc/esp32s3/register/soc/hinf_reg.h
index 212fe817ca2..d419cf129e0 100644
--- a/components/soc/esp32s3/include/soc/hinf_reg.h
+++ b/components/soc/esp32s3/register/soc/hinf_reg.h
@@ -1,19 +1,11 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once
 
-#include "soc.h"
+#include "soc/soc.h"
 
 #define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
 /* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
diff --git a/components/soc/esp32s3/include/soc/hinf_struct.h b/components/soc/esp32s3/register/soc/hinf_struct.h
similarity index 84%
rename from components/soc/esp32s3/include/soc/hinf_struct.h
rename to components/soc/esp32s3/register/soc/hinf_struct.h
index 965f8bd43c1..cf0713461bf 100644
--- a/components/soc/esp32s3/include/soc/hinf_struct.h
+++ b/components/soc/esp32s3/register/soc/hinf_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once
 
 #include <stdint.h>
diff --git a/components/soc/esp32s3/include/soc/host_reg.h b/components/soc/esp32s3/register/soc/host_reg.h
similarity index 99%
rename from components/soc/esp32s3/include/soc/host_reg.h
rename to components/soc/esp32s3/register/soc/host_reg.h
index afcd67d85f2..4dc04161fca 100644
--- a/components/soc/esp32s3/include/soc/host_reg.h
+++ b/components/soc/esp32s3/register/soc/host_reg.h
@@ -1,21 +1,13 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_HOST_REG_H_
 #define _SOC_HOST_REG_H_
 
 
-#include "soc.h"
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32s3/include/soc/host_struct.h b/components/soc/esp32s3/register/soc/host_struct.h
similarity index 97%
rename from components/soc/esp32s3/include/soc/host_struct.h
rename to components/soc/esp32s3/register/soc/host_struct.h
index 1a6b89e2817..79a830ef145 100644
--- a/components/soc/esp32s3/include/soc/host_struct.h
+++ b/components/soc/esp32s3/register/soc/host_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_HOST_STRUCT_H_
 #define _SOC_HOST_STRUCT_H_
 
@@ -459,7 +451,7 @@ typedef volatile struct host_dev_s {
     uint32_t reserved_f0;
     union {
         struct {
-            uint32_t infor                         :    20;
+            uint32_t infor                         :    20;  // codespell:ignore infor
             uint32_t reserved20                    :    12;
         };
         uint32_t val;
diff --git a/components/soc/esp32s3/register/soc/i2c_reg.h b/components/soc/esp32s3/register/soc/i2c_reg.h
new file mode 100644
index 00000000000..0585f139b32
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/i2c_reg.h
@@ -0,0 +1,1422 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_SCL_LOW_PERIOD_REG register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
+/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SCL remains low in master mode, in
+ *  I2C module clock cycles.
+ */
+#define I2C_SCL_LOW_PERIOD    0x000001FFU
+#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
+#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
+#define I2C_SCL_LOW_PERIOD_S  0
+
+/** I2C_CTR_REG register
+ *  Transmission setting
+ */
+#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
+/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 1;
+ *  0: direct output; 1: open drain output.
+ */
+#define I2C_SDA_FORCE_OUT    (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
+#define I2C_SDA_FORCE_OUT_V  0x00000001U
+#define I2C_SDA_FORCE_OUT_S  0
+/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 1;
+ *  0: direct output; 1: open drain output.
+ */
+#define I2C_SCL_FORCE_OUT    (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
+#define I2C_SCL_FORCE_OUT_V  0x00000001U
+#define I2C_SCL_FORCE_OUT_S  1
+/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
+ *  This register is used to select the sample mode.
+ *  1: sample SDA data on the SCL low level.
+ *  0: sample SDA data on the SCL high level.
+ */
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
+#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
+ *  This register is used to configure the ACK value that need to sent by master when
+ *  the rx_fifo_cnt has reached the threshold.
+ */
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
+#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to configure the module as an I2C Master. Clear this bit to configure
+ *  the
+ *  module as an I2C Slave.
+ */
+#define I2C_MS_MODE    (BIT(4))
+#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
+#define I2C_MS_MODE_V  0x00000001U
+#define I2C_MS_MODE_S  4
+/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
+ *  Set this bit to start sending the data in txfifo.
+ */
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
+#define I2C_TRANS_START_V  0x00000001U
+#define I2C_TRANS_START_S  5
+/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
+ *  This bit is used to control the sending mode for data needing to be sent.
+ *  1: send data from the least significant bit;
+ *  0: send data from the most significant bit.
+ */
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
+#define I2C_TX_LSB_FIRST_V  0x00000001U
+#define I2C_TX_LSB_FIRST_S  6
+/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
+ *  This bit is used to control the storage mode for received data.
+ *  1: receive data from the least significant bit;
+ *  0: receive data from the most significant bit.
+ */
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
+#define I2C_RX_LSB_FIRST_V  0x00000001U
+#define I2C_RX_LSB_FIRST_S  7
+/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
+#define I2C_CLK_EN_V  0x00000001U
+#define I2C_CLK_EN_S  8
+/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
+ *  This is the enable bit for arbitration_lost.
+ */
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
+#define I2C_ARBITRATION_EN_V  0x00000001U
+#define I2C_ARBITRATION_EN_S  9
+/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
+ *  This register is used to reset the scl FMS.
+ */
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
+#define I2C_FSM_RST_V  0x00000001U
+#define I2C_FSM_RST_S  10
+/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
+ *  synchronization bit
+ */
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
+#define I2C_CONF_UPGATE_V  0x00000001U
+#define I2C_CONF_UPGATE_S  11
+/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for slave to send data automatically
+ */
+#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
+#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001U
+#define I2C_SLV_TX_AUTO_START_EN_S  12
+/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit to check if the r/w bit of 10bit addressing consists with
+ *  I2C protocol
+ */
+#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S)
+#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
+/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit to support the 7bit general call function.
+ */
+#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_M  (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
+#define I2C_ADDR_BROADCASTING_EN_V  0x00000001U
+#define I2C_ADDR_BROADCASTING_EN_S  14
+
+/** I2C_SR_REG register
+ *  Describe I2C work status.
+ */
+#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
+/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
+ *  The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
+ */
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
+#define I2C_RESP_REC_V  0x00000001U
+#define I2C_RESP_REC_S  0
+/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
+ *  When in slave mode, 1: master reads from slave; 0: master writes to slave.
+ */
+#define I2C_SLAVE_RW    (BIT(1))
+#define I2C_SLAVE_RW_M  (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S)
+#define I2C_SLAVE_RW_V  0x00000001U
+#define I2C_SLAVE_RW_S  1
+/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
+ *  When the I2C controller loses control of SCL line, this register changes to 1.
+ */
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
+#define I2C_ARB_LOST_V  0x00000001U
+#define I2C_ARB_LOST_S  3
+/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
+ *  1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state.
+ */
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
+#define I2C_BUS_BUSY_V  0x00000001U
+#define I2C_BUS_BUSY_S  4
+/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
+ *  When configured as an I2C Slave, and the address sent by the master is
+ *  equal to the address of the slave, then this bit will be of high level.
+ */
+#define I2C_SLAVE_ADDRESSED    (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
+#define I2C_SLAVE_ADDRESSED_V  0x00000001U
+#define I2C_SLAVE_ADDRESSED_S  5
+/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0;
+ *  This field represents the amount of data needed to be sent.
+ */
+#define I2C_RXFIFO_CNT    0x0000003FU
+#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
+#define I2C_RXFIFO_CNT_V  0x0000003FU
+#define I2C_RXFIFO_CNT_S  8
+/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
+ *  The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the
+ *  beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty
+ *  in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.
+ */
+#define I2C_STRETCH_CAUSE    0x00000003U
+#define I2C_STRETCH_CAUSE_M  (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S)
+#define I2C_STRETCH_CAUSE_V  0x00000003U
+#define I2C_STRETCH_CAUSE_S  14
+/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0;
+ *  This field stores the amount of received data in RAM.
+ */
+#define I2C_TXFIFO_CNT    0x0000003FU
+#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
+#define I2C_TXFIFO_CNT_V  0x0000003FU
+#define I2C_TXFIFO_CNT_S  18
+/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
+ *  This field indicates the states of the I2C module state machine.
+ *  0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6:
+ *  Wait ACK
+ */
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
+#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
+ *  This field indicates the states of the state machine used to produce SCL.
+ *  0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop
+ */
+#define I2C_SCL_STATE_LAST    0x00000007U
+#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
+#define I2C_SCL_STATE_LAST_V  0x00000007U
+#define I2C_SCL_STATE_LAST_S  28
+
+/** I2C_TO_REG register
+ *  Setting time out control for receiving data.
+ */
+#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
+/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  This register is used to configure the timeout for receiving a data bit in APB
+ *  clock cycles.
+ */
+#define I2C_TIME_OUT_VALUE    0x0000001FU
+#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
+#define I2C_TIME_OUT_VALUE_V  0x0000001FU
+#define I2C_TIME_OUT_VALUE_S  0
+/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for time out control.
+ */
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
+#define I2C_TIME_OUT_EN_V  0x00000001U
+#define I2C_TIME_OUT_EN_S  5
+
+/** I2C_SLAVE_ADDR_REG register
+ *  Local slave address setting
+ */
+#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
+/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
+ *  When configured as an I2C Slave, this field is used to configure the slave address.
+ */
+#define I2C_SLAVE_ADDR    0x00007FFFU
+#define I2C_SLAVE_ADDR_M  (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
+#define I2C_SLAVE_ADDR_V  0x00007FFFU
+#define I2C_SLAVE_ADDR_S  0
+/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
+ *  This field is used to enable the slave 10-bit addressing mode in master mode.
+ */
+#define I2C_ADDR_10BIT_EN    (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
+#define I2C_ADDR_10BIT_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_EN_S  31
+
+/** I2C_FIFO_ST_REG register
+ *  FIFO status register.
+ */
+#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
+/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
+ *  This is the offset address of the APB reading from rxfifo
+ */
+#define I2C_RXFIFO_RADDR    0x0000001FU
+#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
+#define I2C_RXFIFO_RADDR_V  0x0000001FU
+#define I2C_RXFIFO_RADDR_S  0
+/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0;
+ *  This is the offset address of i2c module receiving data and writing to rxfifo.
+ */
+#define I2C_RXFIFO_WADDR    0x0000001FU
+#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
+#define I2C_RXFIFO_WADDR_V  0x0000001FU
+#define I2C_RXFIFO_WADDR_S  5
+/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0;
+ *  This is the offset address of i2c module reading from txfifo.
+ */
+#define I2C_TXFIFO_RADDR    0x0000001FU
+#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
+#define I2C_TXFIFO_RADDR_V  0x0000001FU
+#define I2C_TXFIFO_RADDR_S  10
+/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0;
+ *  This is the offset address of APB bus writing to txfifo.
+ */
+#define I2C_TXFIFO_WADDR    0x0000001FU
+#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
+#define I2C_TXFIFO_WADDR_V  0x0000001FU
+#define I2C_TXFIFO_WADDR_S  15
+/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0;
+ *  The received data in I2C slave mode.
+ */
+#define I2C_SLAVE_RW_POINT    0x000000FFU
+#define I2C_SLAVE_RW_POINT_M  (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S)
+#define I2C_SLAVE_RW_POINT_V  0x000000FFU
+#define I2C_SLAVE_RW_POINT_S  22
+
+/** I2C_FIFO_CONF_REG register
+ *  FIFO configuration register.
+ */
+#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
+/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
+ *  The water mark threshold of rx FIFO in nonfifo access mode. When
+ *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+ *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
+ */
+#define I2C_RXFIFO_WM_THRHD    0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
+#define I2C_RXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_S  0
+/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4;
+ *  The water mark threshold of tx FIFO in nonfifo access mode. When
+ *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+ *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
+ */
+#define I2C_TXFIFO_WM_THRHD    0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
+#define I2C_TXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_S  5
+/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to enable APB nonfifo access.
+ */
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
+#define I2C_NONFIFO_EN_V  0x00000001U
+#define I2C_NONFIFO_EN_S  10
+/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
+ *  When this bit is set to 1, the byte received after the I2C address byte represents
+ *  the offset address in the I2C Slave RAM.
+ */
+#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
+#define I2C_FIFO_ADDR_CFG_EN_V  0x00000001U
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to reset rx-fifo.
+ */
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
+#define I2C_RX_FIFO_RST_V  0x00000001U
+#define I2C_RX_FIFO_RST_S  12
+/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to reset tx-fifo.
+ */
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
+#define I2C_TX_FIFO_RST_V  0x00000001U
+#define I2C_TX_FIFO_RST_S  13
+/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
+ *  The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
+ *  the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
+ */
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
+#define I2C_FIFO_PRT_EN_V  0x00000001U
+#define I2C_FIFO_PRT_EN_S  14
+
+/** I2C_DATA_REG register
+ *  Rx FIFO read data.
+ */
+#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
+/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0;
+ *  The value of rx FIFO read data.
+ */
+#define I2C_FIFO_RDATA    0x000000FFU
+#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
+#define I2C_FIFO_RDATA_V  0x000000FFU
+#define I2C_FIFO_RDATA_S  0
+
+/** I2C_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
+/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
+#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
+ *  The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
+#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
+#define I2C_END_DETECT_INT_RAW_V  0x00000001U
+#define I2C_END_DETECT_INT_RAW_S  3
+/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
+ *  The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
+ *  The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
+#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
+#define I2C_TIME_OUT_INT_RAW_S  8
+/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
+ *  The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
+#define I2C_TRANS_START_INT_RAW_V  0x00000001U
+#define I2C_TRANS_START_INT_RAW_S  9
+/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
+ *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
+#define I2C_NACK_INT_RAW_V  0x00000001U
+#define I2C_NACK_INT_RAW_S  10
+/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
+ *  The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
+ *  The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
+ *  The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
+#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
+ *  The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
+ *  The raw interrupt bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
+#define I2C_DET_START_INT_RAW_V  0x00000001U
+#define I2C_DET_START_INT_RAW_S  15
+/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
+ *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_M  (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S)
+#define I2C_SLAVE_STRETCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_RAW_S  16
+/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
+ *  The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_M  (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S)
+#define I2C_GENERAL_CALL_INT_RAW_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_RAW_S  17
+
+/** I2C_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
+/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
+#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
+#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
+#define I2C_END_DETECT_INT_CLR_V  0x00000001U
+#define I2C_END_DETECT_INT_CLR_S  3
+/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
+#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
+#define I2C_TIME_OUT_INT_CLR_S  8
+/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
+#define I2C_TRANS_START_INT_CLR_V  0x00000001U
+#define I2C_TRANS_START_INT_CLR_S  9
+/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
+#define I2C_NACK_INT_CLR_V  0x00000001U
+#define I2C_NACK_INT_CLR_S  10
+/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
+#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
+#define I2C_DET_START_INT_CLR_V  0x00000001U
+#define I2C_DET_START_INT_CLR_S  15
+/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_M  (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S)
+#define I2C_SLAVE_STRETCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_CLR_S  16
+/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit for I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_M  (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S)
+#define I2C_GENERAL_CALL_INT_CLR_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_CLR_S  17
+
+/** I2C_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
+/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
+#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
+#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
+#define I2C_END_DETECT_INT_ENA_V  0x00000001U
+#define I2C_END_DETECT_INT_ENA_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
+#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
+#define I2C_TIME_OUT_INT_ENA_S  8
+/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
+#define I2C_TRANS_START_INT_ENA_V  0x00000001U
+#define I2C_TRANS_START_INT_ENA_S  9
+/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
+#define I2C_NACK_INT_ENA_V  0x00000001U
+#define I2C_NACK_INT_ENA_S  10
+/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
+#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The interrupt enable bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
+#define I2C_DET_START_INT_ENA_V  0x00000001U
+#define I2C_DET_START_INT_ENA_S  15
+/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_M  (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S)
+#define I2C_SLAVE_STRETCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ENA_S  16
+/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_M  (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S)
+#define I2C_GENERAL_CALL_INT_ENA_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ENA_S  17
+
+/** I2C_INT_STATUS_REG register
+ *  Status of captured I2C communication events
+ */
+#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
+/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
+ */
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
+#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ST_S  0
+/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
+ */
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
+#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
+ */
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
+#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
+#define I2C_END_DETECT_INT_ST_V  0x00000001U
+#define I2C_END_DETECT_INT_ST_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
+ */
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
+ */
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
+ */
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
+#define I2C_TIME_OUT_INT_ST_V  0x00000001U
+#define I2C_TIME_OUT_INT_ST_S  8
+/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
+ */
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
+#define I2C_TRANS_START_INT_ST_V  0x00000001U
+#define I2C_TRANS_START_INT_ST_S  9
+/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
+#define I2C_NACK_INT_ST_V  0x00000001U
+#define I2C_NACK_INT_ST_S  10
+/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
+ */
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
+#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.
+ */
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
+#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
+#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked interrupt status bit for I2C_DET_START_INT interrupt.
+ */
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
+#define I2C_DET_START_INT_ST_V  0x00000001U
+#define I2C_DET_START_INT_ST_S  15
+/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
+ */
+#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_M  (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S)
+#define I2C_SLAVE_STRETCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ST_S  16
+/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.
+ */
+#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_M  (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S)
+#define I2C_GENERAL_CALL_INT_ST_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ST_S  17
+
+/** I2C_SDA_HOLD_REG register
+ *  Configures the hold time after a negative SCL edge.
+ */
+#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
+/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure the time to hold the data after the negative
+ *  edge of SCL, in I2C module clock cycles.
+ */
+#define I2C_SDA_HOLD_TIME    0x000001FFU
+#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
+#define I2C_SDA_HOLD_TIME_V  0x000001FFU
+#define I2C_SDA_HOLD_TIME_S  0
+
+/** I2C_SDA_SAMPLE_REG register
+ *  Configures the sample time after a positive SCL edge.
+ */
+#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
+/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SDA is sampled, in I2C module clock
+ *  cycles.
+ */
+#define I2C_SDA_SAMPLE_TIME    0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
+#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+/** I2C_SCL_HIGH_PERIOD_REG register
+ *  Configures the high level width of SCL
+ */
+#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
+/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  This register is used to configure for how long SCL remains high in master mode, in
+ *  I2C module clock cycles.
+ */
+#define I2C_SCL_HIGH_PERIOD    0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
+#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_S  0
+/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
+ *  This register is used to configure for the SCL_FSM's waiting period for SCL high
+ *  level in master mode, in I2C module clock cycles.
+ */
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+
+/** I2C_SCL_START_HOLD_REG register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
+/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the negative edge
+ *  of SDA and the negative edge of SCL for a START condition, in I2C module clock
+ *  cycles.
+ */
+#define I2C_SCL_START_HOLD_TIME    0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
+#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+/** I2C_SCL_RSTART_SETUP_REG register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
+/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the positive
+ *  edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
+ *  clock cycles.
+ */
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+/** I2C_SCL_STOP_HOLD_REG register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
+/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the delay after the STOP condition,
+ *  in I2C module clock cycles.
+ */
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
+#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+/** I2C_SCL_STOP_SETUP_REG register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
+/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  This register is used to configure the time between the positive edge
+ *  of SCL and the positive edge of SDA, in I2C module clock cycles.
+ */
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
+#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+/** I2C_FILTER_CFG_REG register
+ *  SCL and SDA filter configuration register
+ */
+#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
+/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
+ *  When a pulse on the SCL input has smaller width than this register value
+ *  in I2C module clock cycles, the I2C controller will ignore that pulse.
+ */
+#define I2C_SCL_FILTER_THRES    0x0000000FU
+#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
+#define I2C_SCL_FILTER_THRES_V  0x0000000FU
+#define I2C_SCL_FILTER_THRES_S  0
+/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
+ *  When a pulse on the SDA input has smaller width than this register value
+ *  in I2C module clock cycles, the I2C controller will ignore that pulse.
+ */
+#define I2C_SDA_FILTER_THRES    0x0000000FU
+#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
+#define I2C_SDA_FILTER_THRES_V  0x0000000FU
+#define I2C_SDA_FILTER_THRES_S  4
+/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
+ *  This is the filter enable bit for SCL.
+ */
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
+#define I2C_SCL_FILTER_EN_V  0x00000001U
+#define I2C_SCL_FILTER_EN_S  8
+/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
+ *  This is the filter enable bit for SDA.
+ */
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
+#define I2C_SDA_FILTER_EN_V  0x00000001U
+#define I2C_SDA_FILTER_EN_S  9
+
+/** I2C_CLK_CONF_REG register
+ *  I2C CLK configuration register
+ */
+#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54)
+/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  the integral part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_NUM    0x000000FFU
+#define I2C_SCLK_DIV_NUM_M  (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S)
+#define I2C_SCLK_DIV_NUM_V  0x000000FFU
+#define I2C_SCLK_DIV_NUM_S  0
+/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0;
+ *  the numerator of the fractional part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_A    0x0000003FU
+#define I2C_SCLK_DIV_A_M  (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S)
+#define I2C_SCLK_DIV_A_V  0x0000003FU
+#define I2C_SCLK_DIV_A_S  8
+/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0;
+ *  the denominator of the fractional part of the fractional divisor for i2c module
+ */
+#define I2C_SCLK_DIV_B    0x0000003FU
+#define I2C_SCLK_DIV_B_M  (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S)
+#define I2C_SCLK_DIV_B_V  0x0000003FU
+#define I2C_SCLK_DIV_B_S  14
+/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0;
+ *  The clock selection for i2c module:0-XTAL;1-CLK_8MHz.
+ */
+#define I2C_SCLK_SEL    (BIT(20))
+#define I2C_SCLK_SEL_M  (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S)
+#define I2C_SCLK_SEL_V  0x00000001U
+#define I2C_SCLK_SEL_S  20
+/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1;
+ *  The clock switch for i2c module
+ */
+#define I2C_SCLK_ACTIVE    (BIT(21))
+#define I2C_SCLK_ACTIVE_M  (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S)
+#define I2C_SCLK_ACTIVE_V  0x00000001U
+#define I2C_SCLK_ACTIVE_S  21
+
+/** I2C_COMD0_REG register
+ *  I2C command register 0
+ */
+#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
+/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 0. It consists of three parts:
+ *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND0    0x00003FFFU
+#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
+#define I2C_COMMAND0_V  0x00003FFFU
+#define I2C_COMMAND0_S  0
+/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 0 is done in I2C Master mode, this bit changes to high
+ *  level.
+ */
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
+#define I2C_COMMAND0_DONE_V  0x00000001U
+#define I2C_COMMAND0_DONE_S  31
+
+/** I2C_COMD1_REG register
+ *  I2C command register 1
+ */
+#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
+/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 1. It consists of three parts:
+ *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND1    0x00003FFFU
+#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
+#define I2C_COMMAND1_V  0x00003FFFU
+#define I2C_COMMAND1_S  0
+/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 1 is done in I2C Master mode, this bit changes to high
+ *  level.
+ */
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
+#define I2C_COMMAND1_DONE_V  0x00000001U
+#define I2C_COMMAND1_DONE_S  31
+
+/** I2C_COMD2_REG register
+ *  I2C command register 2
+ */
+#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
+/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 2. It consists of three parts:
+ *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND2    0x00003FFFU
+#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
+#define I2C_COMMAND2_V  0x00003FFFU
+#define I2C_COMMAND2_S  0
+/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 2 is done in I2C Master mode, this bit changes to high
+ *  Level.
+ */
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
+#define I2C_COMMAND2_DONE_V  0x00000001U
+#define I2C_COMMAND2_DONE_S  31
+
+/** I2C_COMD3_REG register
+ *  I2C command register 3
+ */
+#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
+/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 3. It consists of three parts:
+ *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND3    0x00003FFFU
+#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
+#define I2C_COMMAND3_V  0x00003FFFU
+#define I2C_COMMAND3_S  0
+/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 3 is done in I2C Master mode, this bit changes to high
+ *  level.
+ */
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
+#define I2C_COMMAND3_DONE_V  0x00000001U
+#define I2C_COMMAND3_DONE_S  31
+
+/** I2C_COMD4_REG register
+ *  I2C command register 4
+ */
+#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
+/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 4. It consists of three parts:
+ *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND4    0x00003FFFU
+#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
+#define I2C_COMMAND4_V  0x00003FFFU
+#define I2C_COMMAND4_S  0
+/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 4 is done in I2C Master mode, this bit changes to high
+ *  level.
+ */
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
+#define I2C_COMMAND4_DONE_V  0x00000001U
+#define I2C_COMMAND4_DONE_S  31
+
+/** I2C_COMD5_REG register
+ *  I2C command register 5
+ */
+#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
+/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 5. It consists of three parts:
+ *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND5    0x00003FFFU
+#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
+#define I2C_COMMAND5_V  0x00003FFFU
+#define I2C_COMMAND5_S  0
+/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 5 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
+#define I2C_COMMAND5_DONE_V  0x00000001U
+#define I2C_COMMAND5_DONE_S  31
+
+/** I2C_COMD6_REG register
+ *  I2C command register 6
+ */
+#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
+/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 6. It consists of three parts:
+ *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND6    0x00003FFFU
+#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
+#define I2C_COMMAND6_V  0x00003FFFU
+#define I2C_COMMAND6_S  0
+/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 6 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
+#define I2C_COMMAND6_DONE_V  0x00000001U
+#define I2C_COMMAND6_DONE_S  31
+
+/** I2C_COMD7_REG register
+ *  I2C command register 7
+ */
+#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
+/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
+ *  This is the content of command 7. It consists of three parts:
+ *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+ *  structure for more
+ *  Information.
+ */
+#define I2C_COMMAND7    0x00003FFFU
+#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
+#define I2C_COMMAND7_V  0x00003FFFU
+#define I2C_COMMAND7_S  0
+/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  When command 7 is done in I2C Master mode, this bit changes to high level.
+ */
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
+#define I2C_COMMAND7_DONE_V  0x00000001U
+#define I2C_COMMAND7_DONE_S  31
+
+/** I2C_SCL_ST_TIME_OUT_REG register
+ *  SCL status time out register
+ */
+#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
+/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  The threshold value of SCL_FSM state unchanged period. It should be o more than 23
+ */
+#define I2C_SCL_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
+#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_ST_TO_I2C_S  0
+
+/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
+ *  SCL main status time out register
+ */
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
+/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
+ *  than 23
+ */
+#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
+#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_S  0
+
+/** I2C_SCL_SP_CONF_REG register
+ *  Power configuration register
+ */
+#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
+/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
+ *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
+ *  equals to reg_scl_rst_slv_num[4:0].
+ */
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
+#define I2C_SCL_RST_SLV_EN_V  0x00000001U
+#define I2C_SCL_RST_SLV_EN_S  0
+/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
+ *  Configure the pulses of SCL generated in I2C master mode. Valid when
+ *  reg_scl_rst_slv_en is 1.
+ */
+#define I2C_SCL_RST_SLV_NUM    0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
+#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_S  1
+/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
+ *  The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
+ *  down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
+ */
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
+#define I2C_SCL_PD_EN_V  0x00000001U
+#define I2C_SCL_PD_EN_S  6
+/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
+ *  The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
+ *  down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
+ */
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
+#define I2C_SDA_PD_EN_V  0x00000001U
+#define I2C_SDA_PD_EN_S  7
+
+/** I2C_SCL_STRETCH_CONF_REG register
+ *  Set SCL stretch of I2C slave
+ */
+#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
+/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
+ *  Configure the period of I2C slave stretching SCL line.
+ */
+#define I2C_STRETCH_PROTECT_NUM    0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_M  (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
+#define I2C_STRETCH_PROTECT_NUM_V  0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_S  0
+/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL
+ *  output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch
+ *  event happens. The stretch cause can be seen in reg_stretch_cause.
+ */
+#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_M  (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
+#define I2C_SLAVE_SCL_STRETCH_EN_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_EN_S  10
+/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the I2C slave SCL stretch function.
+ */
+#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_M  (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
+#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
+/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for slave to control ACK level function.
+ */
+#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
+/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
+ *  Set the ACK level when slave controlling ACK level function enables.
+ */
+#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_M  (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
+#define I2C_SLAVE_BYTE_ACK_LVL_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_LVL_S  13
+
+/** I2C_DATE_REG register
+ *  Version register
+ */
+#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
+/** I2C_DATE : R/W; bitpos: [31:0]; default: 537330177;
+ *  This is the the version register.
+ */
+#define I2C_DATE    0xFFFFFFFFU
+#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
+#define I2C_DATE_V  0xFFFFFFFFU
+#define I2C_DATE_S  0
+
+/** I2C_TXFIFO_START_ADDR_REG register
+ *  I2C TXFIFO base address register
+ */
+#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
+/** I2C_TXFIFO_START_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  This is the I2C txfifo first address.
+ */
+#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
+#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_S  0
+
+/** I2C_RXFIFO_START_ADDR_REG register
+ *  I2C RXFIFO base address register
+ */
+#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
+/** I2C_RXFIFO_START_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  This is the I2C rxfifo first address.
+ */
+#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
+#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/i2c_struct.h b/components/soc/esp32s3/register/soc/i2c_struct.h
new file mode 100644
index 00000000000..fe3695f44fd
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/i2c_struct.h
@@ -0,0 +1,979 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL
+ *  Clock
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SCL remains low in master mode, in
+         *  I2C module clock cycles.
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure the time to hold the data after the negative
+         *  edge of SCL, in I2C module clock cycles.
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge.
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SDA is sampled, in I2C module clock
+         *  cycles.
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  This register is used to configure for how long SCL remains high in master mode, in
+         *  I2C module clock cycles.
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  This register is used to configure for the SCL_FSM's waiting period for SCL high
+         *  level in master mode, in I2C module clock cycles.
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the negative edge
+         *  of SDA and the negative edge of SCL for a START condition, in I2C module clock
+         *  cycles.
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive
+ *  edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the positive
+         *  edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
+         *  clock cycles.
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock
+ *  edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the delay after the STOP condition,
+         *  in I2C module clock cycles.
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and
+ *  SCL positive edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  This register is used to configure the time between the positive edge
+         *  of SCL and the positive edge of SDA, in I2C module clock cycles.
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status time out register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  The threshold value of SCL_FSM state unchanged period. It should be o more than 23
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status time out register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
+         *  than 23
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting
+ */
+typedef union {
+    struct {
+        /** sda_force_out : R/W; bitpos: [0]; default: 1;
+         *  0: direct output; 1: open drain output.
+         */
+        uint32_t sda_force_out:1;
+        /** scl_force_out : R/W; bitpos: [1]; default: 1;
+         *  0: direct output; 1: open drain output.
+         */
+        uint32_t scl_force_out:1;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  This register is used to select the sample mode.
+         *  1: sample SDA data on the SCL low level.
+         *  0: sample SDA data on the SCL high level.
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  This register is used to configure the ACK value that need to sent by master when
+         *  the rx_fifo_cnt has reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        /** ms_mode : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to configure the module as an I2C Master. Clear this bit to configure
+         *  the
+         *  module as an I2C Slave.
+         */
+        uint32_t ms_mode:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Set this bit to start sending the data in txfifo.
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  This bit is used to control the sending mode for data needing to be sent.
+         *  1: send data from the least significant bit;
+         *  0: send data from the most significant bit.
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  This bit is used to control the storage mode for received data.
+         *  1: receive data from the least significant bit;
+         *  0: receive data from the most significant bit.
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  This is the enable bit for arbitration_lost.
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  This register is used to reset the scl FMS.
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  synchronization bit
+         */
+        uint32_t conf_upgate:1;
+        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for slave to send data automatically
+         */
+        uint32_t slv_tx_auto_start_en:1;
+        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit to check if the r/w bit of 10bit addressing consists with
+         *  I2C protocol
+         */
+        uint32_t addr_10bit_rw_check_en:1;
+        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit to support the 7bit general call function.
+         */
+        uint32_t addr_broadcasting_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Setting time out control for receiving data.
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  This register is used to configure the timeout for receiving a data bit in APB
+         *  clock cycles.
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for time out control.
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of slave_addr register
+ *  Local slave address setting
+ */
+typedef union {
+    struct {
+        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
+         *  When configured as an I2C Slave, this field is used to configure the slave address.
+         */
+        uint32_t slave_addr:15;
+        uint32_t reserved_15:16;
+        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
+         *  This field is used to enable the slave 10-bit addressing mode in master mode.
+         */
+        uint32_t addr_10bit_en:1;
+    };
+    uint32_t val;
+} i2c_slave_addr_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
+         *  The water mark threshold of rx FIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
+         *  reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t rxfifo_wm_thrhd:5;
+        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
+         *  The water mark threshold of tx FIFO in nonfifo access mode. When
+         *  reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
+         *  reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:5;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to enable APB nonfifo access.
+         */
+        uint32_t nonfifo_en:1;
+        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
+         *  When this bit is set to 1, the byte received after the I2C address byte represents
+         *  the offset address in the I2C Slave RAM.
+         */
+        uint32_t fifo_addr_cfg_en:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to reset rx-fifo.
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to reset tx-fifo.
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
+         *  the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  When a pulse on the SCL input has smaller width than this register value
+         *  in I2C module clock cycles, the I2C controller will ignore that pulse.
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  When a pulse on the SDA input has smaller width than this register value
+         *  in I2C module clock cycles, the I2C controller will ignore that pulse.
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  This is the filter enable bit for SCL.
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  This is the filter enable bit for SDA.
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of clk_conf register
+ *  I2C CLK configuration register
+ */
+typedef union {
+    struct {
+        /** sclk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  the integral part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_num:8;
+        /** sclk_div_a : R/W; bitpos: [13:8]; default: 0;
+         *  the numerator of the fractional part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_b : R/W; bitpos: [19:14]; default: 0;
+         *  the denominator of the fractional part of the fractional divisor for i2c module
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_sel : R/W; bitpos: [20]; default: 0;
+         *  The clock selection for i2c module:0-XTAL;1-CLK_8MHz.
+         */
+        uint32_t sclk_sel:1;
+        /** sclk_active : R/W; bitpos: [21]; default: 1;
+         *  The clock switch for i2c module
+         */
+        uint32_t sclk_active:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} i2c_clk_conf_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
+         *  equals to reg_scl_rst_slv_num[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C master mode. Valid when
+         *  reg_scl_rst_slv_en is 1.
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
+         *  down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
+         *  down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+/** Type of scl_stretch_conf register
+ *  Set SCL stretch of I2C slave
+ */
+typedef union {
+    struct {
+        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
+         *  Configure the period of I2C slave stretching SCL line.
+         */
+        uint32_t stretch_protect_num:10;
+        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL
+         *  output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch
+         *  event happens. The stretch cause can be seen in reg_stretch_cause.
+         */
+        uint32_t slave_scl_stretch_en:1;
+        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the I2C slave SCL stretch function.
+         */
+        uint32_t slave_scl_stretch_clr:1;
+        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
+         *  The enable bit for slave to control ACK level function.
+         */
+        uint32_t slave_byte_ack_ctl_en:1;
+        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
+         *  Set the ACK level when slave controlling ACK level function enables.
+         */
+        uint32_t slave_byte_ack_lvl:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i2c_scl_stretch_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  Describe I2C work status.
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
+         */
+        uint32_t resp_rec:1;
+        /** slave_rw : RO; bitpos: [1]; default: 0;
+         *  When in slave mode, 1: master reads from slave; 0: master writes to slave.
+         */
+        uint32_t slave_rw:1;
+        uint32_t reserved_2:1;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  When the I2C controller loses control of SCL line, this register changes to 1.
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state.
+         */
+        uint32_t bus_busy:1;
+        /** slave_addressed : RO; bitpos: [5]; default: 0;
+         *  When configured as an I2C Slave, and the address sent by the master is
+         *  equal to the address of the slave, then this bit will be of high level.
+         */
+        uint32_t slave_addressed:1;
+        uint32_t reserved_6:2;
+        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
+         *  This field represents the amount of data needed to be sent.
+         */
+        uint32_t rxfifo_cnt:6;
+        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
+         *  The cause of stretching SCL low in slave mode. 0:  stretching SCL low at the
+         *  beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty
+         *  in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.
+         */
+        uint32_t stretch_cause:2;
+        uint32_t reserved_16:2;
+        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
+         *  This field stores the amount of received data in RAM.
+         */
+        uint32_t txfifo_cnt:6;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  This field indicates the states of the I2C module state machine.
+         *  0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6:
+         *  Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  This field indicates the states of the state machine used to produce SCL.
+         *  0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register.
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
+         *  This is the offset address of the APB reading from rxfifo
+         */
+        uint32_t rxfifo_raddr:5;
+        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
+         *  This is the offset address of i2c module receiving data and writing to rxfifo.
+         */
+        uint32_t rxfifo_waddr:5;
+        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
+         *  This is the offset address of i2c module reading from txfifo.
+         */
+        uint32_t txfifo_raddr:5;
+        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
+         *  This is the offset address of APB bus writing to txfifo.
+         */
+        uint32_t txfifo_waddr:5;
+        uint32_t reserved_20:2;
+        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
+         *  The received data in I2C slave mode.
+         */
+        uint32_t slave_rw_point:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data.
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : RO; bitpos: [7:0]; default: 0;
+         *  The value of rx FIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_raw:1;
+        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_raw:1;
+        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_raw:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_clr:1;
+        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_clr:1;
+        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit for I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The interrupt enable bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_ena:1;
+        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_ena:1;
+        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_ena:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status bit for I2C_RXFIFO_UDF_INT  interrupt.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status bit for I2C_DET_START_INT interrupt.
+         */
+        uint32_t det_start_int_st:1;
+        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
+         */
+        uint32_t slave_stretch_int_st:1;
+        /** general_call_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.
+         */
+        uint32_t general_call_int_st:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of command register
+ *  I2C command register
+ */
+typedef union {
+    struct {
+        /** command0 : R/W; bitpos: [13:0]; default: 0;
+         *  This is the content of command 0. It consists of three parts:
+         *  op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
+         *  structure for more
+         *  Information.
+         */
+        uint32_t command:14;
+        uint32_t reserved_14:17;
+        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
+         *  When command 0 is done in I2C Master mode, this bit changes to high
+         *  level.
+         */
+        uint32_t command_done:1;
+    };
+    uint32_t val;
+} i2c_comd_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 537330177;
+         *  This is the the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    volatile i2c_slave_addr_reg_t slave_addr;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    volatile i2c_clk_conf_reg_t clk_conf;
+    volatile i2c_comd_reg_t comd[8];
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
+    uint32_t reserved_088[28];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile uint32_t txfifo_mem[32];
+    volatile uint32_t rxfifo_mem[32];
+} i2c_dev_t;
+
+extern i2c_dev_t I2C0;
+extern i2c_dev_t I2C1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/i2s_reg.h b/components/soc/esp32s3/register/soc/i2s_reg.h
new file mode 100644
index 00000000000..16293844343
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/i2s_reg.h
@@ -0,0 +1,1098 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_I2S_REG_H_
+#define _SOC_I2S_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0xC)
+/* I2S_TX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt.*/
+#define I2S_TX_HUNG_INT_RAW    (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_V  0x1
+#define I2S_TX_HUNG_INT_RAW_S  3
+/* I2S_RX_HUNG_INT_RAW : RO/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_hung_int interrupt.*/
+#define I2S_RX_HUNG_INT_RAW    (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_V  0x1
+#define I2S_RX_HUNG_INT_RAW_S  2
+/* I2S_TX_DONE_INT_RAW : RO/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_done_int interrupt.*/
+#define I2S_TX_DONE_INT_RAW    (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (BIT(1))
+#define I2S_TX_DONE_INT_RAW_V  0x1
+#define I2S_TX_DONE_INT_RAW_S  1
+/* I2S_RX_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_done_int interrupt.*/
+#define I2S_RX_DONE_INT_RAW    (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (BIT(0))
+#define I2S_RX_DONE_INT_RAW_V  0x1
+#define I2S_RX_DONE_INT_RAW_S  0
+
+#define I2S_INT_ST_REG(i)          (REG_I2S_BASE(i) + 0x10)
+/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_hung_int interrupt.*/
+#define I2S_TX_HUNG_INT_ST    (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (BIT(3))
+#define I2S_TX_HUNG_INT_ST_V  0x1
+#define I2S_TX_HUNG_INT_ST_S  3
+/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_hung_int interrupt.*/
+#define I2S_RX_HUNG_INT_ST    (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (BIT(2))
+#define I2S_RX_HUNG_INT_ST_V  0x1
+#define I2S_RX_HUNG_INT_ST_S  2
+/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_done_int interrupt.*/
+#define I2S_TX_DONE_INT_ST    (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (BIT(1))
+#define I2S_TX_DONE_INT_ST_V  0x1
+#define I2S_TX_DONE_INT_ST_S  1
+/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_done_int interrupt.*/
+#define I2S_RX_DONE_INT_ST    (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (BIT(0))
+#define I2S_RX_DONE_INT_ST_V  0x1
+#define I2S_RX_DONE_INT_ST_S  0
+
+#define I2S_INT_ENA_REG(i)          (REG_I2S_BASE(i) + 0x14)
+/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_hung_int interrupt.*/
+#define I2S_TX_HUNG_INT_ENA    (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_V  0x1
+#define I2S_TX_HUNG_INT_ENA_S  3
+/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_hung_int interrupt.*/
+#define I2S_RX_HUNG_INT_ENA    (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_V  0x1
+#define I2S_RX_HUNG_INT_ENA_S  2
+/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_done_int interrupt.*/
+#define I2S_TX_DONE_INT_ENA    (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (BIT(1))
+#define I2S_TX_DONE_INT_ENA_V  0x1
+#define I2S_TX_DONE_INT_ENA_S  1
+/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_done_int interrupt.*/
+#define I2S_RX_DONE_INT_ENA    (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (BIT(0))
+#define I2S_RX_DONE_INT_ENA_V  0x1
+#define I2S_RX_DONE_INT_ENA_S  0
+
+#define I2S_INT_CLR_REG(i)          (REG_I2S_BASE(i) + 0x18)
+/* I2S_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_hung_int interrupt.*/
+#define I2S_TX_HUNG_INT_CLR    (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_V  0x1
+#define I2S_TX_HUNG_INT_CLR_S  3
+/* I2S_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_hung_int interrupt.*/
+#define I2S_RX_HUNG_INT_CLR    (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_V  0x1
+#define I2S_RX_HUNG_INT_CLR_S  2
+/* I2S_TX_DONE_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_done_int interrupt.*/
+#define I2S_TX_DONE_INT_CLR    (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (BIT(1))
+#define I2S_TX_DONE_INT_CLR_V  0x1
+#define I2S_TX_DONE_INT_CLR_S  1
+/* I2S_RX_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_done_int interrupt.*/
+#define I2S_RX_DONE_INT_CLR    (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (BIT(0))
+#define I2S_RX_DONE_INT_CLR_V  0x1
+#define I2S_RX_DONE_INT_CLR_S  0
+
+#define I2S_RX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x20)
+/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: Configure the down sampling rate of PDM RX filter group1 module. 1: The  down sa
+mpling rate is 128. 0: down sampling rate is 64..*/
+#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(22))
+#define I2S_RX_PDM_SINC_DSR_16_EN_M  (BIT(22))
+#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x1
+#define I2S_RX_PDM_SINC_DSR_16_EN_S  22
+/* I2S_RX_PDM2PCM_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: 1: Enable PDM2PCM RX mode. 0: DIsable..*/
+#define I2S_RX_PDM2PCM_EN    (BIT(21))
+#define I2S_RX_PDM2PCM_EN_M  (BIT(21))
+#define I2S_RX_PDM2PCM_EN_V  0x1
+#define I2S_RX_PDM2PCM_EN_S  21
+/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: 1: Enable I2S PDM Rx mode . 0: Disable..*/
+#define I2S_RX_PDM_EN    (BIT(20))
+#define I2S_RX_PDM_EN_M  (BIT(20))
+#define I2S_RX_PDM_EN_V  0x1
+#define I2S_RX_PDM_EN_S  20
+/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: 1: Enable I2S TDM Rx mode . 0: Disable..*/
+#define I2S_RX_TDM_EN    (BIT(19))
+#define I2S_RX_TDM_EN_M  (BIT(19))
+#define I2S_RX_TDM_EN_V  0x1
+#define I2S_RX_TDM_EN_S  19
+/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the
+MSB is received first..*/
+#define I2S_RX_BIT_ORDER    (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (BIT(18))
+#define I2S_RX_BIT_ORDER_V  0x1
+#define I2S_RX_BIT_ORDER_S  18
+/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: 0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+  1: WS should be 1 when receiving left channel data, and WS is 0in right channel
+l. .*/
+#define I2S_RX_WS_IDLE_POL    (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (BIT(17))
+#define I2S_RX_WS_IDLE_POL_V  0x1
+#define I2S_RX_WS_IDLE_POL_S  17
+/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits..*/
+#define I2S_RX_24_FILL_EN    (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (BIT(16))
+#define I2S_RX_24_FILL_EN_V  0x1
+#define I2S_RX_24_FILL_EN_S  16
+/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode..*/
+#define I2S_RX_LEFT_ALIGN    (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (BIT(15))
+#define I2S_RX_LEFT_ALIGN_V  0x1
+#define I2S_RX_LEFT_ALIGN_S  15
+/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */
+/*description: 0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start
+is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is
+full..*/
+#define I2S_RX_STOP_MODE    0x00000003
+#define I2S_RX_STOP_MODE_M  ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S))
+#define I2S_RX_STOP_MODE_V  0x3
+#define I2S_RX_STOP_MODE_S  13
+/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to bypass Compress/Decompress module for received data..*/
+#define I2S_RX_PCM_BYPASS    (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (BIT(12))
+#define I2S_RX_PCM_BYPASS_V  0x1
+#define I2S_RX_PCM_BYPASS_S  12
+/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */
+/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (l
+toa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &.*/
+#define I2S_RX_PCM_CONF    0x00000003
+#define I2S_RX_PCM_CONF_M  ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
+#define I2S_RX_PCM_CONF_V  0x3
+#define I2S_RX_PCM_CONF_S  10
+/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: 1: The first channel data value is valid in I2S RX mono mode.   0: The second ch
+annel data value is valid in I2S RX mono mode..*/
+#define I2S_RX_MONO_FST_VLD    (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (BIT(9))
+#define I2S_RX_MONO_FST_VLD_V  0x1
+#define I2S_RX_MONO_FST_VLD_S  9
+/* I2S_RX_UPDATE : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. T
+his bit will be cleared by hardware after update register done..*/
+#define I2S_RX_UPDATE    (BIT(8))
+#define I2S_RX_UPDATE_M  (BIT(8))
+#define I2S_RX_UPDATE_V  0x1
+#define I2S_RX_UPDATE_S  8
+/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr va
+lue..*/
+#define I2S_RX_BIG_ENDIAN    (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (BIT(7))
+#define I2S_RX_BIG_ENDIAN_V  0x1
+#define I2S_RX_BIG_ENDIAN_S  7
+/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver  in mono mode.*/
+#define I2S_RX_MONO    (BIT(5))
+#define I2S_RX_MONO_M  (BIT(5))
+#define I2S_RX_MONO_V  0x1
+#define I2S_RX_MONO_S  5
+/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave receiver mode.*/
+#define I2S_RX_SLAVE_MOD    (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (BIT(3))
+#define I2S_RX_SLAVE_MOD_V  0x1
+#define I2S_RX_SLAVE_MOD_S  3
+/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to start receiving data.*/
+#define I2S_RX_START    (BIT(2))
+#define I2S_RX_START_M  (BIT(2))
+#define I2S_RX_START_V  0x1
+#define I2S_RX_START_S  2
+/* I2S_RX_FIFO_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset Rx AFIFO.*/
+#define I2S_RX_FIFO_RESET    (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (BIT(1))
+#define I2S_RX_FIFO_RESET_V  0x1
+#define I2S_RX_FIFO_RESET_S  1
+/* I2S_RX_RESET : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to reset receiver.*/
+#define I2S_RX_RESET    (BIT(0))
+#define I2S_RX_RESET_M  (BIT(0))
+#define I2S_RX_RESET_V  0x1
+#define I2S_RX_RESET_S  0
+
+#define I2S_TX_CONF_REG(i)          (REG_I2S_BASE(i) + 0x24)
+/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable signal loop back mode with transmitter module and receiver module sharing
+ the same WS and BCK signals..*/
+#define I2S_SIG_LOOPBACK    (BIT(27))
+#define I2S_SIG_LOOPBACK_M  (BIT(27))
+#define I2S_SIG_LOOPBACK_V  0x1
+#define I2S_SIG_LOOPBACK_S  27
+/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: I2S transmitter channel mode configuration bits..*/
+#define I2S_TX_CHAN_MOD    0x00000007
+#define I2S_TX_CHAN_MOD_M  ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S))
+#define I2S_TX_CHAN_MOD_V  0x7
+#define I2S_TX_CHAN_MOD_S  24
+/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: 1: Enable I2S PDM Tx mode . 0: Disable..*/
+#define I2S_TX_PDM_EN    (BIT(20))
+#define I2S_TX_PDM_EN_M  (BIT(20))
+#define I2S_TX_PDM_EN_V  0x1
+#define I2S_TX_PDM_EN_S  20
+/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: 1: Enable I2S TDM Tx mode . 0: Disable..*/
+#define I2S_TX_TDM_EN    (BIT(19))
+#define I2S_TX_TDM_EN_M  (BIT(19))
+#define I2S_TX_TDM_EN_V  0x1
+#define I2S_TX_TDM_EN_S  19
+/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB
+is sent first..*/
+#define I2S_TX_BIT_ORDER    (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (BIT(18))
+#define I2S_TX_BIT_ORDER_V  0x1
+#define I2S_TX_BIT_ORDER_S  18
+/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: 0: WS should be 0 when sending left channel data, and WS is 1in right channel.
+1: WS should be 1 when sending left channel data, and WS is 0in right channel. .*/
+#define I2S_TX_WS_IDLE_POL    (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (BIT(17))
+#define I2S_TX_WS_IDLE_POL_V  0x1
+#define I2S_TX_WS_IDLE_POL_S  17
+/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode.*/
+#define I2S_TX_24_FILL_EN    (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (BIT(16))
+#define I2S_TX_24_FILL_EN_V  0x1
+#define I2S_TX_24_FILL_EN_S  16
+/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode..*/
+#define I2S_TX_LEFT_ALIGN    (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (BIT(15))
+#define I2S_TX_LEFT_ALIGN_V  0x1
+#define I2S_TX_LEFT_ALIGN_S  15
+/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emt
+py.*/
+#define I2S_TX_STOP_EN    (BIT(13))
+#define I2S_TX_STOP_EN_M  (BIT(13))
+#define I2S_TX_STOP_EN_V  0x1
+#define I2S_TX_STOP_EN_S  13
+/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to bypass  Compress/Decompress module for transmitted data..*/
+#define I2S_TX_PCM_BYPASS    (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (BIT(12))
+#define I2S_TX_PCM_BYPASS_V  0x1
+#define I2S_TX_PCM_BYPASS_S  12
+/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (l
+toa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &.*/
+#define I2S_TX_PCM_CONF    0x00000003
+#define I2S_TX_PCM_CONF_M  ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
+#define I2S_TX_PCM_CONF_V  0x3
+#define I2S_TX_PCM_CONF_S  10
+/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: 1: The first channel data value is valid in I2S TX mono mode.   0: The second ch
+annel data value is valid in I2S TX mono mode..*/
+#define I2S_TX_MONO_FST_VLD    (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (BIT(9))
+#define I2S_TX_MONO_FST_VLD_V  0x1
+#define I2S_TX_MONO_FST_VLD_S  9
+/* I2S_TX_UPDATE : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. T
+his bit will be cleared by hardware after update register done..*/
+#define I2S_TX_UPDATE    (BIT(8))
+#define I2S_TX_UPDATE_M  (BIT(8))
+#define I2S_TX_UPDATE_V  0x1
+#define I2S_TX_UPDATE_S  8
+/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr v
+value..*/
+#define I2S_TX_BIG_ENDIAN    (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (BIT(7))
+#define I2S_TX_BIG_ENDIAN_V  0x1
+#define I2S_TX_BIG_ENDIAN_S  7
+/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: The value of Left channel data is equal to the value of right channel data in
+ I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg
+_i2s_single_data in I2S TX mono mode or TDM channel select mode..*/
+#define I2S_TX_CHAN_EQUAL    (BIT(6))
+#define I2S_TX_CHAN_EQUAL_M  (BIT(6))
+#define I2S_TX_CHAN_EQUAL_V  0x1
+#define I2S_TX_CHAN_EQUAL_S  6
+/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter in mono mode  .*/
+#define I2S_TX_MONO    (BIT(5))
+#define I2S_TX_MONO_M  (BIT(5))
+#define I2S_TX_MONO_V  0x1
+#define I2S_TX_MONO_S  5
+/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave transmitter mode  .*/
+#define I2S_TX_SLAVE_MOD    (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (BIT(3))
+#define I2S_TX_SLAVE_MOD_V  0x1
+#define I2S_TX_SLAVE_MOD_S  3
+/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to start transmitting data .*/
+#define I2S_TX_START    (BIT(2))
+#define I2S_TX_START_M  (BIT(2))
+#define I2S_TX_START_V  0x1
+#define I2S_TX_START_S  2
+/* I2S_TX_FIFO_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset Tx AFIFO.*/
+#define I2S_TX_FIFO_RESET    (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (BIT(1))
+#define I2S_TX_FIFO_RESET_V  0x1
+#define I2S_TX_FIFO_RESET_S  1
+/* I2S_TX_RESET : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to reset transmitter.*/
+#define I2S_TX_RESET    (BIT(0))
+#define I2S_TX_RESET_M  (BIT(0))
+#define I2S_TX_RESET_V  0x1
+#define I2S_TX_RESET_S  0
+
+#define I2S_RX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x28)
+/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to enable receiver in Phillips standard mode.*/
+#define I2S_RX_MSB_SHIFT    (BIT(29))
+#define I2S_RX_MSB_SHIFT_M  (BIT(29))
+#define I2S_RX_MSB_SHIFT_V  0x1
+#define I2S_RX_MSB_SHIFT_S  29
+/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hf ; */
+/*description: The Rx bit number for each channel minus 1in TDM mode..*/
+#define I2S_RX_TDM_CHAN_BITS    0x0000001F
+#define I2S_RX_TDM_CHAN_BITS_M  ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S))
+#define I2S_RX_TDM_CHAN_BITS_V  0x1F
+#define I2S_RX_TDM_CHAN_BITS_S  24
+/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hf ; */
+/*description: I2S Rx half sample bits -1..*/
+#define I2S_RX_HALF_SAMPLE_BITS    0x0000003F
+#define I2S_RX_HALF_SAMPLE_BITS_M  ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S))
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x3F
+#define I2S_RX_HALF_SAMPLE_BITS_S  18
+/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hf ; */
+/*description: Set the bits to configure the valid data bit length of I2S receiver channel. 7:
+all the valid channel data is in 8-bit-mode. 15: all the valid channel data is i
+n 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the vali
+d channel data is in 32-bit-mode..*/
+#define I2S_RX_BITS_MOD    0x0000001F
+#define I2S_RX_BITS_MOD_M  ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
+#define I2S_RX_BITS_MOD_V  0x1F
+#define I2S_RX_BITS_MOD_S  13
+/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
+/*description: Bit clock configuration bits in receiver mode. .*/
+#define I2S_RX_BCK_DIV_NUM    0x0000003F
+#define I2S_RX_BCK_DIV_NUM_M  ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S))
+#define I2S_RX_BCK_DIV_NUM_V  0x3F
+#define I2S_RX_BCK_DIV_NUM_S  7
+/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description:  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck.*/
+#define I2S_RX_TDM_WS_WIDTH    0x0000007F
+#define I2S_RX_TDM_WS_WIDTH_M  ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S))
+#define I2S_RX_TDM_WS_WIDTH_V  0x7F
+#define I2S_RX_TDM_WS_WIDTH_S  0
+
+#define I2S_TX_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x2C)
+/* I2S_TX_BCK_NO_DLY : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed
+ to generate pos/neg edge in master mode..*/
+#define I2S_TX_BCK_NO_DLY    (BIT(30))
+#define I2S_TX_BCK_NO_DLY_M  (BIT(30))
+#define I2S_TX_BCK_NO_DLY_V  0x1
+#define I2S_TX_BCK_NO_DLY_S  30
+/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: Set this bit to enable transmitter in Phillips standard mode.*/
+#define I2S_TX_MSB_SHIFT    (BIT(29))
+#define I2S_TX_MSB_SHIFT_M  (BIT(29))
+#define I2S_TX_MSB_SHIFT_V  0x1
+#define I2S_TX_MSB_SHIFT_S  29
+/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hf ; */
+/*description: The Tx bit number for each channel minus 1in TDM mode..*/
+#define I2S_TX_TDM_CHAN_BITS    0x0000001F
+#define I2S_TX_TDM_CHAN_BITS_M  ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S))
+#define I2S_TX_TDM_CHAN_BITS_V  0x1F
+#define I2S_TX_TDM_CHAN_BITS_S  24
+/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hf ; */
+/*description:  I2S Tx half sample bits -1..*/
+#define I2S_TX_HALF_SAMPLE_BITS    0x0000003F
+#define I2S_TX_HALF_SAMPLE_BITS_M  ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S))
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x3F
+#define I2S_TX_HALF_SAMPLE_BITS_S  18
+/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hf ; */
+/*description: Set the bits to configure the valid data bit length of I2S transmitter channel.
+7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data i
+s in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the v
+alid channel data is in 32-bit-mode..*/
+#define I2S_TX_BITS_MOD    0x0000001F
+#define I2S_TX_BITS_MOD_M  ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S))
+#define I2S_TX_BITS_MOD_V  0x1F
+#define I2S_TX_BITS_MOD_S  13
+/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
+/*description: Bit clock configuration bits in transmitter mode. .*/
+#define I2S_TX_BCK_DIV_NUM    0x0000003F
+#define I2S_TX_BCK_DIV_NUM_M  ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S))
+#define I2S_TX_BCK_DIV_NUM_V  0x3F
+#define I2S_TX_BCK_DIV_NUM_S  7
+/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description:  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck.*/
+#define I2S_TX_TDM_WS_WIDTH    0x0000007F
+#define I2S_TX_TDM_WS_WIDTH_M  ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S))
+#define I2S_TX_TDM_WS_WIDTH_V  0x7F
+#define I2S_TX_TDM_WS_WIDTH_S  0
+
+#define I2S_RX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x30)
+/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description:  0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MC
+LK_OUT. .*/
+#define I2S_MCLK_SEL    (BIT(29))
+#define I2S_MCLK_SEL_M  (BIT(29))
+#define I2S_MCLK_SEL_V  0x1
+#define I2S_MCLK_SEL_S  29
+/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_
+in..*/
+#define I2S_RX_CLK_SEL    0x00000003
+#define I2S_RX_CLK_SEL_M  ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S))
+#define I2S_RX_CLK_SEL_V  0x3
+#define I2S_RX_CLK_SEL_S  27
+/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: I2S Rx module clock enable signal..*/
+#define I2S_RX_CLK_ACTIVE    (BIT(26))
+#define I2S_RX_CLK_ACTIVE_M  (BIT(26))
+#define I2S_RX_CLK_ACTIVE_V  0x1
+#define I2S_RX_CLK_ACTIVE_S  26
+/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: Integral I2S clock divider value.*/
+#define I2S_RX_CLKM_DIV_NUM    0x000000FF
+#define I2S_RX_CLKM_DIV_NUM_M  ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S))
+#define I2S_RX_CLKM_DIV_NUM_V  0xFF
+#define I2S_RX_CLKM_DIV_NUM_S  0
+
+#define I2S_TX_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x34)
+/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate.*/
+#define I2S_CLK_EN    (BIT(29))
+#define I2S_CLK_EN_M  (BIT(29))
+#define I2S_CLK_EN_V  0x1
+#define I2S_CLK_EN_S  29
+/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCL
+K_in..*/
+#define I2S_TX_CLK_SEL    0x00000003
+#define I2S_TX_CLK_SEL_M  ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S))
+#define I2S_TX_CLK_SEL_V  0x3
+#define I2S_TX_CLK_SEL_S  27
+/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: I2S Tx module clock enable signal..*/
+#define I2S_TX_CLK_ACTIVE    (BIT(26))
+#define I2S_TX_CLK_ACTIVE_M  (BIT(26))
+#define I2S_TX_CLK_ACTIVE_V  0x1
+#define I2S_TX_CLK_ACTIVE_S  26
+/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will
+ be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b
+ <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+(n+1)-div] + y * (n+1)-div. .*/
+#define I2S_TX_CLKM_DIV_NUM    0x000000FF
+#define I2S_TX_CLKM_DIV_NUM_M  ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S))
+#define I2S_TX_CLKM_DIV_NUM_V  0xFF
+#define I2S_TX_CLKM_DIV_NUM_S  0
+
+#define I2S_RX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x38)
+/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+I2S_RX_CLKM_DIV_YN1 is 1. .*/
+#define I2S_RX_CLKM_DIV_YN1    (BIT(27))
+#define I2S_RX_CLKM_DIV_YN1_M  (BIT(27))
+#define I2S_RX_CLKM_DIV_YN1_V  0x1
+#define I2S_RX_CLKM_DIV_YN1_S  27
+/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
+/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+e of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. .*/
+#define I2S_RX_CLKM_DIV_X    0x000001FF
+#define I2S_RX_CLKM_DIV_X_M  ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S))
+#define I2S_RX_CLKM_DIV_X_V  0x1FF
+#define I2S_RX_CLKM_DIV_X_S  18
+/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
+/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value o
+f I2S_RX_CLKM_DIV_Y is (a%(a-b)). .*/
+#define I2S_RX_CLKM_DIV_Y    0x000001FF
+#define I2S_RX_CLKM_DIV_Y_M  ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S))
+#define I2S_RX_CLKM_DIV_Y_V  0x1FF
+#define I2S_RX_CLKM_DIV_Y_S  9
+/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S
+_RX_CLKM_DIV_Z is (a-b). .*/
+#define I2S_RX_CLKM_DIV_Z    0x000001FF
+#define I2S_RX_CLKM_DIV_Z_M  ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S))
+#define I2S_RX_CLKM_DIV_Z_V  0x1FF
+#define I2S_RX_CLKM_DIV_Z_S  0
+
+#define I2S_TX_CLKM_DIV_CONF_REG(i)          (REG_I2S_BASE(i) + 0x3C)
+/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+I2S_TX_CLKM_DIV_YN1 is 1. .*/
+#define I2S_TX_CLKM_DIV_YN1    (BIT(27))
+#define I2S_TX_CLKM_DIV_YN1_M  (BIT(27))
+#define I2S_TX_CLKM_DIV_YN1_V  0x1
+#define I2S_TX_CLKM_DIV_YN1_S  27
+/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
+/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value
+e of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. .*/
+#define I2S_TX_CLKM_DIV_X    0x000001FF
+#define I2S_TX_CLKM_DIV_X_M  ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S))
+#define I2S_TX_CLKM_DIV_X_V  0x1FF
+#define I2S_TX_CLKM_DIV_X_S  18
+/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
+/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value o
+f I2S_TX_CLKM_DIV_Y is (a%(a-b)). .*/
+#define I2S_TX_CLKM_DIV_Y    0x000001FF
+#define I2S_TX_CLKM_DIV_Y_M  ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S))
+#define I2S_TX_CLKM_DIV_Y_V  0x1FF
+#define I2S_TX_CLKM_DIV_Y_S  9
+/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S
+_TX_CLKM_DIV_Z is (a-b). .*/
+#define I2S_TX_CLKM_DIV_Z    0x000001FF
+#define I2S_TX_CLKM_DIV_Z_M  ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S))
+#define I2S_TX_CLKM_DIV_Z_V  0x1FF
+#define I2S_TX_CLKM_DIV_Z_S  0
+
+#define I2S_TX_PCM2PDM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x40)
+/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: I2S TX PDM Converter enable.*/
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_V  0x1
+#define I2S_PCM2PDM_CONV_EN_S  25
+/* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: I2S TX PDM dac 2channel enable.*/
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x1
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: I2S TX PDM dac mode enable.*/
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x1
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: I2S TX PDM sigmadelta dither value.*/
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x1
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: I2S TX PDM sigmadelta dither2 value.*/
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x1
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_LP_IN_SHIFT_M  ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
+/*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003
+#define I2S_TX_PDM_HP_IN_SHIFT_M  ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */
+/*description: I2S TX PDM prescale for sigmadelta.*/
+#define I2S_TX_PDM_PRESCALE    0x000000FF
+#define I2S_TX_PDM_PRESCALE_M  ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
+#define I2S_TX_PDM_PRESCALE_V  0xFF
+#define I2S_TX_PDM_PRESCALE_S  5
+/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */
+/*description: I2S TX PDM OSR2 value.*/
+#define I2S_TX_PDM_SINC_OSR2    0x0000000F
+#define I2S_TX_PDM_SINC_OSR2_M  ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
+#define I2S_TX_PDM_SINC_OSR2_V  0xF
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/
+#define I2S_TX_PDM_HP_BYPASS    (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_M  (BIT(0))
+#define I2S_TX_PDM_HP_BYPASS_V  0x1
+#define I2S_TX_PDM_HP_BYPASS_S  0
+
+#define I2S_TX_PCM2PDM_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x44)
+/* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */
+/*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL
+T12_0[2:0]).*/
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007
+#define I2S_TX_IIR_HP_MULT12_0_M  ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S))
+#define I2S_TX_IIR_HP_MULT12_0_V  0x7
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+/* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */
+/*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL
+T12_5[2:0]).*/
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007
+#define I2S_TX_IIR_HP_MULT12_5_M  ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S))
+#define I2S_TX_IIR_HP_MULT12_5_V  0x7
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */
+/*description: I2S TX PDM Fs.*/
+#define I2S_TX_PDM_FS    0x000003FF
+#define I2S_TX_PDM_FS_M  ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
+#define I2S_TX_PDM_FS_V  0x3FF
+#define I2S_TX_PDM_FS_S  10
+/* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */
+/*description: I2S TX PDM Fp.*/
+#define I2S_TX_PDM_FP    0x000003FF
+#define I2S_TX_PDM_FP_M  ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
+#define I2S_TX_PDM_FP_V  0x3FF
+#define I2S_TX_PDM_FP_S  0
+
+#define I2S_RX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x50)
+/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: The total channel number of I2S TX TDM mode..*/
+#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000F
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S))
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0xF
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
+ 0 in this channel..*/
+#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_V  0x1
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
+ 0 in this channel..*/
+#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_V  0x1
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
+ 0 in this channel..*/
+#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_V  0x1
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
+ 0 in this channel..*/
+#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_V  0x1
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
+ 0 in this channel..*/
+#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_V  0x1
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
+ 0 in this channel..*/
+#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_V  0x1
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
+ 0 in this channel..*/
+#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_V  0x1
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input
+ 0 in this channel..*/
+#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_V  0x1
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+t input 0 in this channel..*/
+#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+t input 0 in this channel..*/
+#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+t input 0 in this channel..*/
+#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+t input 0 in this channel..*/
+#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+t input 0 in this channel..*/
+#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+t input 0 in this channel..*/
+#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+t input 0 in this channel..*/
+#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+t input 0 in this channel..*/
+#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x1
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+
+#define I2S_TX_TDM_CTRL_REG(i)          (REG_I2S_BASE(i) + 0x54)
+/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels,
+and only the data of the enabled channels is sent, then this bit should be set. C
+lear it when all the data stored in DMA TX buffer is for enabled channels..*/
+#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x1
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
+/*description: The total channel number of I2S TX TDM mode..*/
+#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000F
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S))
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0xF
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_V  0x1
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_V  0x1
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_V  0x1
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_V  0x1
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_V  0x1
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_V  0x1
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_V  0x1
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_V  0x1
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_V  0x1
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_V  0x1
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_V  0x1
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_V  0x1
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_V  0x1
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_V  0x1
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_V  0x1
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
+/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just outp
+ut 0 in this channel..*/
+#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_V  0x1
+#define I2S_TX_TDM_CHAN0_EN_S  0
+
+#define I2S_RX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x58)
+/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+delay by neg edge. 3: not used..*/
+#define I2S_RX_BCK_IN_DM    0x00000003
+#define I2S_RX_BCK_IN_DM_M  ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S))
+#define I2S_RX_BCK_IN_DM_V  0x3
+#define I2S_RX_BCK_IN_DM_S  28
+/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: d
+elay by neg edge. 3: not used..*/
+#define I2S_RX_WS_IN_DM    0x00000003
+#define I2S_RX_WS_IN_DM_M  ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S))
+#define I2S_RX_WS_IN_DM_V  0x3
+#define I2S_RX_WS_IN_DM_S  24
+/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ delay by neg edge. 3: not used..*/
+#define I2S_RX_BCK_OUT_DM    0x00000003
+#define I2S_RX_BCK_OUT_DM_M  ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S))
+#define I2S_RX_BCK_OUT_DM_V  0x3
+#define I2S_RX_BCK_OUT_DM_S  20
+/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+delay by neg edge. 3: not used..*/
+#define I2S_RX_WS_OUT_DM    0x00000003
+#define I2S_RX_WS_OUT_DM_M  ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S))
+#define I2S_RX_WS_OUT_DM_V  0x3
+#define I2S_RX_WS_OUT_DM_S  16
+/* I2S_RX_SD3_IN_DM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+delay by neg edge. 3: not used..*/
+#define I2S_RX_SD3_IN_DM    0x00000003
+#define I2S_RX_SD3_IN_DM_M  ((I2S_RX_SD3_IN_DM_V)<<(I2S_RX_SD3_IN_DM_S))
+#define I2S_RX_SD3_IN_DM_V  0x3
+#define I2S_RX_SD3_IN_DM_S  12
+/* I2S_RX_SD2_IN_DM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+delay by neg edge. 3: not used..*/
+#define I2S_RX_SD2_IN_DM    0x00000003
+#define I2S_RX_SD2_IN_DM_M  ((I2S_RX_SD2_IN_DM_V)<<(I2S_RX_SD2_IN_DM_S))
+#define I2S_RX_SD2_IN_DM_V  0x3
+#define I2S_RX_SD2_IN_DM_S  8
+/* I2S_RX_SD1_IN_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+delay by neg edge. 3: not used..*/
+#define I2S_RX_SD1_IN_DM    0x00000003
+#define I2S_RX_SD1_IN_DM_M  ((I2S_RX_SD1_IN_DM_V)<<(I2S_RX_SD1_IN_DM_S))
+#define I2S_RX_SD1_IN_DM_V  0x3
+#define I2S_RX_SD1_IN_DM_S  4
+/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: d
+elay by neg edge. 3: not used..*/
+#define I2S_RX_SD_IN_DM    0x00000003
+#define I2S_RX_SD_IN_DM_M  ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S))
+#define I2S_RX_SD_IN_DM_V  0x3
+#define I2S_RX_SD_IN_DM_S  0
+
+#define I2S_TX_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x5C)
+/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
+/*description: The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+delay by neg edge. 3: not used..*/
+#define I2S_TX_BCK_IN_DM    0x00000003
+#define I2S_TX_BCK_IN_DM_M  ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S))
+#define I2S_TX_BCK_IN_DM_V  0x3
+#define I2S_TX_BCK_IN_DM_S  28
+/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
+/*description: The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: d
+elay by neg edge. 3: not used..*/
+#define I2S_TX_WS_IN_DM    0x00000003
+#define I2S_TX_WS_IN_DM_M  ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S))
+#define I2S_TX_WS_IN_DM_V  0x3
+#define I2S_TX_WS_IN_DM_S  24
+/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
+/*description: The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ delay by neg edge. 3: not used..*/
+#define I2S_TX_BCK_OUT_DM    0x00000003
+#define I2S_TX_BCK_OUT_DM_M  ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S))
+#define I2S_TX_BCK_OUT_DM_V  0x3
+#define I2S_TX_BCK_OUT_DM_S  20
+/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+delay by neg edge. 3: not used..*/
+#define I2S_TX_WS_OUT_DM    0x00000003
+#define I2S_TX_WS_OUT_DM_M  ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S))
+#define I2S_TX_WS_OUT_DM_V  0x3
+#define I2S_TX_WS_OUT_DM_S  16
+/* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ delay by neg edge. 3: not used..*/
+#define I2S_TX_SD1_OUT_DM    0x00000003
+#define I2S_TX_SD1_OUT_DM_M  ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S))
+#define I2S_TX_SD1_OUT_DM_V  0x3
+#define I2S_TX_SD1_OUT_DM_S  4
+/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+delay by neg edge. 3: not used..*/
+#define I2S_TX_SD_OUT_DM    0x00000003
+#define I2S_TX_SD_OUT_DM_M  ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S))
+#define I2S_TX_SD_OUT_DM_V  0x3
+#define I2S_TX_SD_OUT_DM_S  0
+
+#define I2S_LC_HUNG_CONF_REG(i)          (REG_I2S_BASE(i) + 0x60)
+/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: The enable bit for FIFO timeout.*/
+#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x1
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: The bits are used to scale tick counter threshold. The tick counter is reset
+when counter value >= 88000/2^i2s_lc_fifo_timeout_shift.*/
+#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x7
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ when fifo hung counter is equal to this value  .*/
+#define I2S_LC_FIFO_TIMEOUT    0x000000FF
+#define I2S_LC_FIFO_TIMEOUT_M  ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S))
+#define I2S_LC_FIFO_TIMEOUT_V  0xFF
+#define I2S_LC_FIFO_TIMEOUT_S  0
+
+#define I2S_RXEOF_NUM_REG(i)          (REG_I2S_BASE(i) + 0x64)
+/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */
+/*description: The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0
+] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel..*/
+#define I2S_RX_EOF_NUM    0x00000FFF
+#define I2S_RX_EOF_NUM_M  ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
+#define I2S_RX_EOF_NUM_V  0xFFF
+#define I2S_RX_EOF_NUM_S  0
+
+#define I2S_CONF_SIGLE_DATA_REG(i)          (REG_I2S_BASE(i) + 0x68)
+/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: The configured constant channel data to be sent out..*/
+#define I2S_SINGLE_DATA    0xFFFFFFFF
+#define I2S_SINGLE_DATA_M  ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S))
+#define I2S_SINGLE_DATA_V  0xFFFFFFFF
+#define I2S_SINGLE_DATA_S  0
+
+#define I2S_STATE_REG(i)          (REG_I2S_BASE(i) + 0x6C)
+/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: i2s_tx is idle state. 0: i2s_tx is working..*/
+#define I2S_TX_IDLE    (BIT(0))
+#define I2S_TX_IDLE_M  (BIT(0))
+#define I2S_TX_IDLE_V  0x1
+#define I2S_TX_IDLE_S  0
+
+#define I2S_DATE_REG(i)          (REG_I2S_BASE(i) + 0x80)
+/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2009070 ; */
+/*description: I2S version control register.*/
+#define I2S_DATE    0x0FFFFFFF
+#define I2S_DATE_M  ((I2S_DATE_V)<<(I2S_DATE_S))
+#define I2S_DATE_V  0xFFFFFFF
+#define I2S_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2S_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/i2s_struct.h b/components/soc/esp32s3/register/soc/i2s_struct.h
new file mode 100644
index 00000000000..c7500479b10
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/i2s_struct.h
@@ -0,0 +1,337 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct i2s_dev_s {
+    uint32_t reserved_0;
+    uint32_t reserved_4;
+    uint32_t reserved_8;
+    union {
+        struct {
+            uint32_t rx_done                       :    1;  /*The raw interrupt status bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done                       :    1;  /*The raw interrupt status bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung                       :    1;  /*The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung                       :    1;  /*The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4                     :    28;  /*Reserve*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_done                       :    1;  /*The masked interrupt status bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done                       :    1;  /*The masked interrupt status bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung                       :    1;  /*The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung                       :    1;  /*The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4                     :    28;  /*Reserve*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rx_done                       :    1;  /*The interrupt enable bit  for the i2s_rx_done_int interrupt*/
+            uint32_t tx_done                       :    1;  /*The interrupt enable bit  for the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung                       :    1;  /*The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung                       :    1;  /*The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4                     :    28;  /*Reserve*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rx_done                       :    1;  /*Set this bit to clear the i2s_rx_done_int interrupt*/
+            uint32_t tx_done                       :    1;  /*Set this bit to clear the i2s_tx_done_int interrupt*/
+            uint32_t rx_hung                       :    1;  /*Set this bit to clear the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung                       :    1;  /*Set this bit to clear the i2s_tx_hung_int interrupt*/
+            uint32_t reserved4                     :    28;  /*Reserve*/
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t reserved_1c;
+    union {
+        struct {
+            uint32_t rx_reset                      :    1;  /*Set this bit to reset receiver*/
+            uint32_t rx_fifo_reset                 :    1;  /*Set this bit to reset Rx AFIFO*/
+            uint32_t rx_start                      :    1;  /*Set this bit to start receiving data*/
+            uint32_t rx_slave_mod                  :    1;  /*Set this bit to enable slave receiver mode*/
+            uint32_t reserved4                     :    1;  /* Reserved*/
+            uint32_t rx_mono                       :    1;  /*Set this bit to enable receiver  in mono mode*/
+            uint32_t reserved6                     :    1;  /*Reserve*/
+            uint32_t rx_big_endian                 :    1;  /*I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
+            uint32_t rx_update                     :    1;  /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
+            uint32_t rx_mono_fst_vld               :    1;  /*1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.*/
+            uint32_t rx_pcm_conf                   :    2;  /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
+            uint32_t rx_pcm_bypass                 :    1;  /*Set this bit to bypass Compress/Decompress module for received data.*/
+            uint32_t rx_stop_mode                  :    2;  /*0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
+            uint32_t rx_left_align                 :    1;  /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
+            uint32_t rx_24_fill_en                 :    1;  /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
+            uint32_t rx_ws_idle_pol                :    1;  /*0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel. */
+            uint32_t rx_bit_order                  :    1;  /*I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.*/
+            uint32_t rx_tdm_en                     :    1;  /*1: Enable I2S TDM Rx mode . 0: Disable.*/
+            uint32_t rx_pdm_en                     :    1;  /*1: Enable I2S PDM Rx mode . 0: Disable.*/
+            uint32_t rx_pdm2pcm_en                 :    1;  /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
+            uint32_t rx_pdm_sinc_dsr_16_en         :    1;  /*Configure the down sampling rate of PDM RX filter group1 module. 1: The  down sampling rate is 128. 0: down sampling rate is 64.*/
+            uint32_t reserved23                    :    9;  /*Reserve*/
+        };
+        uint32_t val;
+    } rx_conf;
+    union {
+        struct {
+            uint32_t tx_reset                      :    1;  /*Set this bit to reset transmitter*/
+            uint32_t tx_fifo_reset                 :    1;  /*Set this bit to reset Tx AFIFO*/
+            uint32_t tx_start                      :    1;  /*Set this bit to start transmitting data */
+            uint32_t tx_slave_mod                  :    1;  /*Set this bit to enable slave transmitter mode  */
+            uint32_t reserved4                     :    1;  /* Reserved*/
+            uint32_t tx_mono                       :    1;  /*Set this bit to enable transmitter in mono mode  */
+            uint32_t tx_chan_equal                 :    1;  /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
+            uint32_t tx_big_endian                 :    1;  /*I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.*/
+            uint32_t tx_update                     :    1;  /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
+            uint32_t tx_mono_fst_vld               :    1;  /*1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.*/
+            uint32_t tx_pcm_conf                   :    2;  /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
+            uint32_t tx_pcm_bypass                 :    1;  /*Set this bit to bypass  Compress/Decompress module for transmitted data.*/
+            uint32_t tx_stop_en                    :    1;  /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty*/
+            uint32_t reserved14                    :    1;  /* Reserved*/
+            uint32_t tx_left_align                 :    1;  /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
+            uint32_t tx_24_fill_en                 :    1;  /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
+            uint32_t tx_ws_idle_pol                :    1;  /*0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel. */
+            uint32_t tx_bit_order                  :    1;  /*I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.*/
+            uint32_t tx_tdm_en                     :    1;  /*1: Enable I2S TDM Tx mode . 0: Disable.*/
+            uint32_t tx_pdm_en                     :    1;  /*1: Enable I2S PDM Tx mode . 0: Disable.*/
+            uint32_t reserved21                    :    3;  /*Reserved*/
+            uint32_t tx_chan_mod                   :    3;  /*I2S transmitter channel mode configuration bits.*/
+            uint32_t sig_loopback                  :    1;  /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
+            uint32_t reserved28                    :    4;  /*Reserve*/
+        };
+        uint32_t val;
+    } tx_conf;
+    union {
+        struct {
+            uint32_t rx_tdm_ws_width               :    7;  /* The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
+            uint32_t rx_bck_div_num                :    6;  /*Bit clock configuration bits in receiver mode. */
+            uint32_t rx_bits_mod                   :    5;  /*Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
+            uint32_t rx_half_sample_bits           :    6;  /*I2S Rx half sample bits -1.*/
+            uint32_t rx_tdm_chan_bits              :    5;  /*The Rx bit number for each channel minus 1in TDM mode.*/
+            uint32_t rx_msb_shift                  :    1;  /*Set this bit to enable receiver in Phillips standard mode*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
+        };
+        uint32_t val;
+    } rx_conf1;
+    union {
+        struct {
+            uint32_t tx_tdm_ws_width               :    7;  /* The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
+            uint32_t tx_bck_div_num                :    6;  /*Bit clock configuration bits in transmitter mode. */
+            uint32_t tx_bits_mod                   :    5;  /*Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
+            uint32_t tx_half_sample_bits           :    6;  /* I2S Tx half sample bits -1.*/
+            uint32_t tx_tdm_chan_bits              :    5;  /*The Tx bit number for each channel minus 1in TDM mode.*/
+            uint32_t tx_msb_shift                  :    1;  /*Set this bit to enable transmitter in Phillips standard mode*/
+            uint32_t tx_bck_no_dly                 :    1;  /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
+            uint32_t reserved31                    :    1;  /* Reserved*/
+        };
+        uint32_t val;
+    } tx_conf1;
+    union {
+        struct {
+            uint32_t rx_clkm_div_num               :    8;  /*Integral I2S clock divider value*/
+            uint32_t reserved8                     :    18;  /* Reserved*/
+            uint32_t rx_clk_active                 :    1;  /*I2S Rx module clock enable signal.*/
+            uint32_t rx_clk_sel                    :    2;  /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
+            uint32_t mclk_sel                      :    1;  /* 0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT. */
+            uint32_t reserved30                    :    2;  /* Reserved*/
+        };
+        uint32_t val;
+    } rx_clkm_conf;
+    union {
+        struct {
+            uint32_t tx_clkm_div_num               :    8;  /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. */
+            uint32_t reserved8                     :    18;  /* Reserved*/
+            uint32_t tx_clk_active                 :    1;  /*I2S Tx module clock enable signal.*/
+            uint32_t tx_clk_sel                    :    2;  /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
+        };
+        uint32_t val;
+    } tx_clkm_conf;
+    union {
+        struct {
+            uint32_t rx_clkm_div_z                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). */
+            uint32_t rx_clkm_div_y                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). */
+            uint32_t rx_clkm_div_x                 :    9;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. */
+            uint32_t rx_clkm_div_yn1               :    1;  /*For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. */
+            uint32_t reserved28                    :    4;  /* Reserved*/
+        };
+        uint32_t val;
+    } rx_clkm_div_conf;
+    union {
+        struct {
+            uint32_t tx_clkm_div_z                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). */
+            uint32_t tx_clkm_div_y                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). */
+            uint32_t tx_clkm_div_x                 :    9;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. */
+            uint32_t tx_clkm_div_yn1               :    1;  /*For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. */
+            uint32_t reserved28                    :    4;  /* Reserved*/
+        };
+        uint32_t val;
+    } tx_clkm_div_conf;
+    union {
+        struct {
+            uint32_t tx_hp_bypass                  :    1;  /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
+            uint32_t tx_sinc_osr2                  :    4;  /*I2S TX PDM OSR2 value*/
+            uint32_t tx_prescale                   :    8;  /*I2S TX PDM prescale for sigmadelta*/
+            uint32_t tx_hp_in_shift                :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_lp_in_shift                :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_sinc_in_shift              :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_sigmadelta_in_shift        :    2;  /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
+            uint32_t tx_sigmadelta_dither2         :    1;  /*I2S TX PDM sigmadelta dither2 value*/
+            uint32_t tx_sigmadelta_dither          :    1;  /*I2S TX PDM sigmadelta dither value*/
+            uint32_t tx_dac_2out_en                :    1;  /*I2S TX PDM dac mode enable*/
+            uint32_t tx_dac_mode_en                :    1;  /*I2S TX PDM dac 2channel enable*/
+            uint32_t pcm2pdm_conv_en               :    1;  /*I2S TX PDM Converter enable*/
+            uint32_t reserved26                    :    6;  /*Reserved*/
+        };
+        uint32_t val;
+    } tx_pcm2pdm_conf; // Only available on I2S0
+    union {
+        struct {
+            uint32_t tx_pdm_fp                     :    10;  /*I2S TX PDM Fp*/
+            uint32_t tx_pdm_fs                     :    10;  /*I2S TX PDM Fs*/
+            uint32_t tx_iir_hp_mult12_5            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
+            uint32_t tx_iir_hp_mult12_0            :    3;  /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
+            uint32_t reserved26                    :    6;  /*Reserved*/
+        };
+        uint32_t val;
+    } tx_pcm2pdm_conf1; // Only available on I2S0
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    union {
+        struct {
+            uint32_t rx_tdm_chan0_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan1_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan2_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan3_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan4_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan5_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan6_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan7_en               :    1;  /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan8_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan9_en               :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan10_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan11_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan12_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan13_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan14_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_chan15_en              :    1;  /*1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0 in this channel.*/
+            uint32_t rx_tdm_tot_chan_num           :    4;  /*The total channel number of I2S TX TDM mode.*/
+            uint32_t reserved20                    :    12;  /* Reserved*/
+        };
+        uint32_t val;
+    } rx_tdm_ctrl;
+    union {
+        struct {
+            uint32_t tx_tdm_chan0_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan1_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan2_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan3_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan4_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan5_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan6_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan7_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan8_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan9_en               :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan10_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan11_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan12_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan13_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan14_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_chan15_en              :    1;  /*1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output 0 in this channel.*/
+            uint32_t tx_tdm_tot_chan_num           :    4;  /*The total channel number of I2S TX TDM mode.*/
+            uint32_t tx_tdm_skip_msk_en            :    1;  /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
+            uint32_t reserved21                    :    11;  /* Reserved*/
+        };
+        uint32_t val;
+    } tx_tdm_ctrl;
+    union {
+        struct {
+            uint32_t rx_sd_in_dm                   :    2;  /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved2                     :    2;
+            uint32_t rx_sd1_in_dm                  :    2;  /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved6                     :    2;
+            uint32_t rx_sd2_in_dm                  :    2;  /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved10                    :    2;
+            uint32_t rx_sd3_in_dm                  :    2;  /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved14                    :    2;
+            uint32_t rx_ws_out_dm                  :    2;  /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved18                    :    2;  /* Reserved*/
+            uint32_t rx_bck_out_dm                 :    2;  /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved22                    :    2;  /* Reserved*/
+            uint32_t rx_ws_in_dm                   :    2;  /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved26                    :    2;  /* Reserved*/
+            uint32_t rx_bck_in_dm                  :    2;  /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
+        };
+        uint32_t val;
+    } rx_timing;
+    union {
+        struct {
+            uint32_t tx_sd_out_dm                  :    2;  /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved2                     :    2;  /* Reserved*/
+            uint32_t tx_sd1_out_dm                 :    2;  /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved6                     :    10;  /* Reserved*/
+            uint32_t tx_ws_out_dm                  :    2;  /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved18                    :    2;  /* Reserved*/
+            uint32_t tx_bck_out_dm                 :    2;  /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved22                    :    2;  /* Reserved*/
+            uint32_t tx_ws_in_dm                   :    2;  /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved26                    :    2;  /* Reserved*/
+            uint32_t tx_bck_in_dm                  :    2;  /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.*/
+            uint32_t reserved30                    :    2;  /* Reserved*/
+        };
+        uint32_t val;
+    } tx_timing;
+    union {
+        struct {
+            uint32_t fifo_timeout                  :    8;  /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value  */
+            uint32_t fifo_timeout_shift            :    3;  /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
+            uint32_t fifo_timeout_ena              :    1;  /*The enable bit for FIFO timeout*/
+            uint32_t reserved12                    :    20;  /* Reserved*/
+        };
+        uint32_t val;
+    } lc_hung_conf;
+    union {
+        struct {
+            uint32_t rx_eof_num                    :    12;  /*The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/
+            uint32_t reserved12                    :    20;  /* Reserved*/
+        };
+        uint32_t val;
+    } rx_eof_num;
+    uint32_t conf_single_data;                               /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
+    union {
+        struct {
+            uint32_t tx_idle                       :    1;  /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
+            uint32_t reserved1                     :    31;  /* Reserved*/
+        };
+        uint32_t val;
+    } state;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*I2S version control register*/
+            uint32_t reserved28                    :    4;  /* Reserved*/
+        };
+        uint32_t val;
+    } date;
+} i2s_dev_t;
+extern i2s_dev_t I2S0;
+extern i2s_dev_t I2S1;
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/interrupt_core0_reg.h b/components/soc/esp32s3/register/soc/interrupt_core0_reg.h
new file mode 100644
index 00000000000..132bb9f98ed
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/interrupt_core0_reg.h
@@ -0,0 +1,863 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_INTERRUPT_CORE0_REG_H_
+#define _SOC_INTERRUPT_CORE0_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DR_REG_INTERRUPT_CORE0_BASE                 DR_REG_INTERRUPT_BASE
+
+#define INTERRUPT_CORE0_MAC_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
+/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_MAC_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_MAC_INTR_MAP_M  ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
+#define INTERRUPT_CORE0_MAC_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_MAC_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_MAC_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
+/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_MAC_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_MAC_NMI_MAP_M  ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
+#define INTERRUPT_CORE0_MAC_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_MAC_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_PWR_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
+/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_PWR_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_PWR_INTR_MAP_M  ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
+#define INTERRUPT_CORE0_PWR_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_PWR_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
+/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_BB_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BB_INT_MAP_M  ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
+#define INTERRUPT_CORE0_BB_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BB_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
+/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M  ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
+/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_BB_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_M  ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
+/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
+/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
+/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x024)
+/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBT_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_M  ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x028)
+/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M  ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x02C)
+/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x030)
+/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SLC0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_M  ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x034)
+/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SLC1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_M  ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x038)
+/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UHCI1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x03C)
+/* INTERRUPT_CORE0_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_UHCI1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UHCI1_INTR_MAP_M  ((INTERRUPT_CORE0_UHCI1_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI1_INTR_MAP_S))
+#define INTERRUPT_CORE0_UHCI1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UHCI1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x040)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP  0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x044)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x048)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP  0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S  0
+
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x04C)
+/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP  0x0000001F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S))
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V  0x1F
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
+/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
+/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x058)
+/* INTERRUPT_CORE0_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_INTR_3_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_3_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_3_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_3_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_3_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_3_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_INTR_4_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x05C)
+/* INTERRUPT_CORE0_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_INTR_4_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_INTR_4_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_4_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_4_MAP_S))
+#define INTERRUPT_CORE0_SPI_INTR_4_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_INTR_4_MAP_S  0
+
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x060)
+/* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M  ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE0_LCD_CAM_INT_MAP_S))
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I2S0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
+/* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2S0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2S0_INT_MAP_M  ((INTERRUPT_CORE0_I2S0_INT_MAP_V)<<(INTERRUPT_CORE0_I2S0_INT_MAP_S))
+#define INTERRUPT_CORE0_I2S0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2S0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
+/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2S1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2S1_INT_MAP_M  ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
+#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2S1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x06C)
+/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_UART_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UART_INTR_MAP_M  ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UART1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x070)
+/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_UART1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UART1_INTR_MAP_M  ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_UART2_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x074)
+/* INTERRUPT_CORE0_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_UART2_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_UART2_INTR_MAP_M  ((INTERRUPT_CORE0_UART2_INTR_MAP_V)<<(INTERRUPT_CORE0_UART2_INTR_MAP_S))
+#define INTERRUPT_CORE0_UART2_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_UART2_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x078)
+/* INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_M  ((INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V)<<(INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S))
+#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S  0
+
+#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x07C)
+/* INTERRUPT_CORE0_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_PWM0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_PWM0_INTR_MAP_M  ((INTERRUPT_CORE0_PWM0_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM0_INTR_MAP_S))
+#define INTERRUPT_CORE0_PWM0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_PWM0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x080)
+/* INTERRUPT_CORE0_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_PWM1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_PWM1_INTR_MAP_M  ((INTERRUPT_CORE0_PWM1_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM1_INTR_MAP_S))
+#define INTERRUPT_CORE0_PWM1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_PWM1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x084)
+/* INTERRUPT_CORE0_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_PWM2_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_PWM2_INTR_MAP_M  ((INTERRUPT_CORE0_PWM2_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM2_INTR_MAP_S))
+#define INTERRUPT_CORE0_PWM2_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_PWM2_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x088)
+/* INTERRUPT_CORE0_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_PWM3_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_PWM3_INTR_MAP_M  ((INTERRUPT_CORE0_PWM3_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM3_INTR_MAP_S))
+#define INTERRUPT_CORE0_PWM3_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_PWM3_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x08C)
+/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_LEDC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
+#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x090)
+/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_EFUSE_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CAN_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
+/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CAN_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CAN_INT_MAP_M  ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
+#define INTERRUPT_CORE0_CAN_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CAN_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_USB_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
+/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_USB_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_USB_INTR_MAP_M  ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
+#define INTERRUPT_CORE0_USB_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_USB_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x09C)
+/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M  ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_RMT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0)
+/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_RMT_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_RMT_INTR_MAP_M  ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
+#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4)
+/* INTERRUPT_CORE0_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_PCNT_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_PCNT_INTR_MAP_M  ((INTERRUPT_CORE0_PCNT_INTR_MAP_V)<<(INTERRUPT_CORE0_PCNT_INTR_MAP_S))
+#define INTERRUPT_CORE0_PCNT_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_PCNT_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8)
+/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC)
+/* INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S))
+#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0)
+/* INTERRUPT_CORE0_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_M  ((INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S))
+#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4)
+/* INTERRUPT_CORE0_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_M  ((INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S))
+#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8)
+/* INTERRUPT_CORE0_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_M  ((INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S))
+#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_WDG_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC)
+/* INTERRUPT_CORE0_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_WDG_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_WDG_INT_MAP_M  ((INTERRUPT_CORE0_WDG_INT_MAP_V)<<(INTERRUPT_CORE0_WDG_INT_MAP_S))
+#define INTERRUPT_CORE0_WDG_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_WDG_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0)
+/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_TIMER_INT1_MAP  0x0000001F
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_M  ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_V  0x1F
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_S  0
+
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4)
+/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_TIMER_INT2_MAP  0x0000001F
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_M  ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_V  0x1F
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8)
+/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG_T0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC)
+/* INTERRUPT_CORE0_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG_T1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG_T1_INT_MAP_M  ((INTERRUPT_CORE0_TG_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T1_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_T1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_T1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0)
+/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4)
+/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG1_T1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8)
+/* INTERRUPT_CORE0_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG1_T1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG1_T1_INT_MAP_M  ((INTERRUPT_CORE0_TG1_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T1_INT_MAP_S))
+#define INTERRUPT_CORE0_TG1_T1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG1_T1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC)
+/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0)
+/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC)
+/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0)
+/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M  ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4)
+/* INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S))
+#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
+/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
+/* INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S))
+#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M  ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/* INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
+/* INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/* INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/* INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/* INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_M  ((INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
+/* INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/* INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/* INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/* INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
+/* INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_M  ((INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_RSA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_RSA_INT_MAP_M  ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
+#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_RSA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_AES_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_AES_INT_MAP_M  ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
+#define INTERRUPT_CORE0_AES_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_AES_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_SHA_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
+#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_SHA_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
+
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
+
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
+/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
+/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
+/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
+/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
+/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
+/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
+/* INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
+/* INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
+/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
+/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
+/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP  0x0000001F
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V  0x1F
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
+/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
+/* INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S))
+#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
+/* INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M  ((INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S))
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
+/* INTERRUPT_CORE0_PERI_BACKUP_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_M  ((INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V)<<(INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S))
+#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
+/* INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_M  ((INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S))
+#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
+/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTR_STATUS_0  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
+#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_0_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
+/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTR_STATUS_1  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
+#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_1_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
+/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTR_STATUS_2  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_2_M  ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S))
+#define INTERRUPT_CORE0_INTR_STATUS_2_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_2_S  0
+
+#define INTERRUPT_CORE0_INTR_STATUS_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
+/* INTERRUPT_CORE0_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTR_STATUS_3  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_3_M  ((INTERRUPT_CORE0_INTR_STATUS_3_V)<<(INTERRUPT_CORE0_INTR_STATUS_3_S))
+#define INTERRUPT_CORE0_INTR_STATUS_3_V  0xFFFFFFFF
+#define INTERRUPT_CORE0_INTR_STATUS_3_S  0
+
+#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
+/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define INTERRUPT_CORE0_CLK_EN  (BIT(0))
+#define INTERRUPT_CORE0_CLK_EN_M  (BIT(0))
+#define INTERRUPT_CORE0_CLK_EN_V  0x1
+#define INTERRUPT_CORE0_CLK_EN_S  0
+
+#define INTERRUPT_CORE0_INTERRUPT_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
+/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
+/*description: */
+#define INTERRUPT_CORE0_INTERRUPT_DATE  0x0FFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
+#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0xFFFFFFF
+#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/interrupt_core0_struct.h b/components/soc/esp32s3/register/soc/interrupt_core0_struct.h
similarity index 98%
rename from components/soc/esp32s3/include/soc/interrupt_core0_struct.h
rename to components/soc/esp32s3/register/soc/interrupt_core0_struct.h
index aa27462fb00..4a909495068 100644
--- a/components/soc/esp32s3/include/soc/interrupt_core0_struct.h
+++ b/components/soc/esp32s3/register/soc/interrupt_core0_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_INTERRUPT_CORE0_STRUCT_H_
 #define _SOC_INTERRUPT_CORE0_STRUCT_H_
 #include <stdint.h>
diff --git a/components/soc/esp32s3/include/soc/interrupt_core1_reg.h b/components/soc/esp32s3/register/soc/interrupt_core1_reg.h
similarity index 98%
rename from components/soc/esp32s3/include/soc/interrupt_core1_reg.h
rename to components/soc/esp32s3/register/soc/interrupt_core1_reg.h
index 82d77e2f0d1..854106dbf52 100644
--- a/components/soc/esp32s3/include/soc/interrupt_core1_reg.h
+++ b/components/soc/esp32s3/register/soc/interrupt_core1_reg.h
@@ -1,21 +1,13 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_INTERRUPT_CORE1_REG_H_
 #define _SOC_INTERRUPT_CORE1_REG_H_
 
 
-#include "soc.h"
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32s3/include/soc/interrupt_core1_struct.h b/components/soc/esp32s3/register/soc/interrupt_core1_struct.h
similarity index 98%
rename from components/soc/esp32s3/include/soc/interrupt_core1_struct.h
rename to components/soc/esp32s3/register/soc/interrupt_core1_struct.h
index d4dee29ae50..850cc4dc777 100644
--- a/components/soc/esp32s3/include/soc/interrupt_core1_struct.h
+++ b/components/soc/esp32s3/register/soc/interrupt_core1_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_INTERRUPT_CORE1_STRUCT_H_
 #define _SOC_INTERRUPT_CORE1_STRUCT_H_
 #include <stdint.h>
diff --git a/components/soc/esp32s3/register/soc/io_mux_reg.h b/components/soc/esp32s3/register/soc/io_mux_reg.h
new file mode 100644
index 00000000000..fa72d363064
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/io_mux_reg.h
@@ -0,0 +1,436 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15
+
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)
+
+#define IO_MUX_GPIO0_REG        PERIPHS_IO_MUX_GPIO0_U
+#define IO_MUX_GPIO1_REG        PERIPHS_IO_MUX_GPIO1_U
+#define IO_MUX_GPIO2_REG        PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG        PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG        PERIPHS_IO_MUX_GPIO4_U
+#define IO_MUX_GPIO5_REG        PERIPHS_IO_MUX_GPIO5_U
+#define IO_MUX_GPIO6_REG        PERIPHS_IO_MUX_GPIO6_U
+#define IO_MUX_GPIO7_REG        PERIPHS_IO_MUX_GPIO7_U
+#define IO_MUX_GPIO8_REG        PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG        PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG       PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG       PERIPHS_IO_MUX_GPIO11_U
+#define IO_MUX_GPIO12_REG       PERIPHS_IO_MUX_GPIO12_U
+#define IO_MUX_GPIO13_REG       PERIPHS_IO_MUX_GPIO13_U
+#define IO_MUX_GPIO14_REG       PERIPHS_IO_MUX_GPIO14_U
+#define IO_MUX_GPIO15_REG       PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO16_REG       PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO17_REG       PERIPHS_IO_MUX_DAC_1_U
+#define IO_MUX_GPIO18_REG       PERIPHS_IO_MUX_DAC_2_U
+#define IO_MUX_GPIO19_REG       PERIPHS_IO_MUX_GPIO19_U
+#define IO_MUX_GPIO20_REG       PERIPHS_IO_MUX_GPIO20_U
+#define IO_MUX_GPIO21_REG       PERIPHS_IO_MUX_GPIO21_U
+#define IO_MUX_GPIO26_REG       PERIPHS_IO_MUX_SPICS1_U
+#define IO_MUX_GPIO27_REG       PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO28_REG       PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO29_REG       PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO30_REG       PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO31_REG       PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO32_REG       PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO33_REG       PERIPHS_IO_MUX_GPIO33_U
+#define IO_MUX_GPIO34_REG       PERIPHS_IO_MUX_GPIO34_U
+#define IO_MUX_GPIO35_REG       PERIPHS_IO_MUX_GPIO35_U
+#define IO_MUX_GPIO36_REG       PERIPHS_IO_MUX_GPIO36_U
+#define IO_MUX_GPIO37_REG       PERIPHS_IO_MUX_GPIO37_U
+#define IO_MUX_GPIO38_REG       PERIPHS_IO_MUX_GPIO38_U
+#define IO_MUX_GPIO39_REG       PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO40_REG       PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO41_REG       PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO42_REG       PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO43_REG       PERIPHS_IO_MUX_U0TXD_U
+#define IO_MUX_GPIO44_REG       PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO45_REG       PERIPHS_IO_MUX_GPIO45_U
+#define IO_MUX_GPIO46_REG       PERIPHS_IO_MUX_GPIO46_U
+#define IO_MUX_GPIO47_REG       PERIPHS_IO_MUX_SPICLK_P_U
+#define IO_MUX_GPIO48_REG       PERIPHS_IO_MUX_SPICLK_N_U
+
+#define PIN_FUNC_GPIO                               1
+
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define SPI_CS1_GPIO_NUM 26
+#define SPI_HD_GPIO_NUM  27
+#define SPI_WP_GPIO_NUM  28
+#define SPI_CS0_GPIO_NUM 29
+#define SPI_CLK_GPIO_NUM 30
+#define SPI_Q_GPIO_NUM   31
+#define SPI_D_GPIO_NUM   32
+#define SPI_D4_GPIO_NUM  33
+#define SPI_D5_GPIO_NUM  34
+#define SPI_D6_GPIO_NUM  35
+#define SPI_D7_GPIO_NUM  36
+#define SPI_DQS_GPIO_NUM 37
+#define SD_CLK_GPIO_NUM 12
+#define SD_CMD_GPIO_NUM 11
+#define SD_DATA0_GPIO_NUM 13
+#define SD_DATA1_GPIO_NUM 14
+#define SD_DATA2_GPIO_NUM 9
+#define SD_DATA3_GPIO_NUM 10
+#define USB_INT_PHY0_DM_GPIO_NUM   19
+#define USB_INT_PHY0_DP_GPIO_NUM   20
+#define XTAL32K_P_GPIO_NUM 15
+#define XTAL32K_N_GPIO_NUM 16
+
+#define MAX_RTC_GPIO_NUM 21
+#define MAX_PAD_GPIO_NUM 48
+#define MAX_GPIO_NUM    53
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
+#define PAD_POWER_SEL                               BIT(15)
+#define PAD_POWER_SEL_V                             0x1
+#define PAD_POWER_SEL_M                             BIT(15)
+#define PAD_POWER_SEL_S                             15
+
+
+#define PAD_POWER_SWITCH_DELAY                      0x7
+#define PAD_POWER_SWITCH_DELAY_V                    0x7
+#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
+#define PAD_POWER_SWITCH_DELAY_S                    12
+
+
+#define CLK_OUT3                                    0xf
+#define CLK_OUT3_V                                  CLK_OUT3
+#define CLK_OUT3_S                                  8
+#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2                                    0xf
+#define CLK_OUT2_V                                  CLK_OUT2
+#define CLK_OUT2_S                                  4
+#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1                                    0xf
+#define CLK_OUT1_V                                  CLK_OUT1
+#define CLK_OUT1_S                                  0
+#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
+
+#define PERIPHS_IO_MUX_GPIO0_U            (REG_IO_MUX_BASE +0x04)
+#define FUNC_GPIO0_GPIO0                            1
+#define FUNC_GPIO0_GPIO0_0                          0
+
+#define PERIPHS_IO_MUX_GPIO1_U            (REG_IO_MUX_BASE +0x08)
+#define FUNC_GPIO1_GPIO1                            1
+#define FUNC_GPIO1_GPIO1_0                          0
+
+#define PERIPHS_IO_MUX_GPIO2_U            (REG_IO_MUX_BASE +0x0c)
+#define FUNC_GPIO2_GPIO2                            1
+#define FUNC_GPIO2_GPIO2_0                          0
+
+#define PERIPHS_IO_MUX_GPIO3_U            (REG_IO_MUX_BASE +0x10)
+#define FUNC_GPIO3_GPIO3                            1
+#define FUNC_GPIO3_GPIO3_0                          0
+
+#define PERIPHS_IO_MUX_GPIO4_U            (REG_IO_MUX_BASE +0x14)
+#define FUNC_GPIO4_GPIO4                            1
+#define FUNC_GPIO4_GPIO4_0                          0
+
+#define PERIPHS_IO_MUX_GPIO5_U            (REG_IO_MUX_BASE +0x18)
+#define FUNC_GPIO5_GPIO5                            1
+#define FUNC_GPIO5_GPIO5_0                          0
+
+#define PERIPHS_IO_MUX_GPIO6_U            (REG_IO_MUX_BASE +0x1c)
+#define FUNC_GPIO6_GPIO6                            1
+#define FUNC_GPIO6_GPIO6_0                          0
+
+#define PERIPHS_IO_MUX_GPIO7_U            (REG_IO_MUX_BASE +0x20)
+#define FUNC_GPIO7_GPIO7                            1
+#define FUNC_GPIO7_GPIO7_0                          0
+
+#define PERIPHS_IO_MUX_GPIO8_U            (REG_IO_MUX_BASE +0x24)
+#define FUNC_GPIO8_SUBSPICS1                        3
+#define FUNC_GPIO8_GPIO8                            1
+#define FUNC_GPIO8_GPIO8_0                          0
+
+#define PERIPHS_IO_MUX_GPIO9_U            (REG_IO_MUX_BASE +0x28)
+#define FUNC_GPIO9_FSPIHD                           4
+#define FUNC_GPIO9_SUBSPIHD                         3
+#define FUNC_GPIO9_GPIO9                            1
+#define FUNC_GPIO9_GPIO9_0                          0
+
+#define PERIPHS_IO_MUX_GPIO10_U           (REG_IO_MUX_BASE +0x2c)
+#define FUNC_GPIO10_FSPICS0                         4
+#define FUNC_GPIO10_SUBSPICS0                       3
+#define FUNC_GPIO10_FSPIIO4                         2
+#define FUNC_GPIO10_GPIO10                          1
+#define FUNC_GPIO10_GPIO10_0                        0
+
+#define PERIPHS_IO_MUX_GPIO11_U           (REG_IO_MUX_BASE +0x30)
+#define FUNC_GPIO11_FSPID                           4
+#define FUNC_GPIO11_SUBSPID                         3
+#define FUNC_GPIO11_FSPIIO5                         2
+#define FUNC_GPIO11_GPIO11                          1
+#define FUNC_GPIO11_GPIO11_0                        0
+
+#define PERIPHS_IO_MUX_GPIO12_U           (REG_IO_MUX_BASE +0x34)
+#define FUNC_GPIO12_FSPICLK                         4
+#define FUNC_GPIO12_SUBSPICLK                       3
+#define FUNC_GPIO12_FSPIIO6                         2
+#define FUNC_GPIO12_GPIO12                          1
+#define FUNC_GPIO12_GPIO12_0                        0
+
+#define PERIPHS_IO_MUX_GPIO13_U           (REG_IO_MUX_BASE +0x38)
+#define FUNC_GPIO13_FSPIQ                           4
+#define FUNC_GPIO13_SUBSPIQ                         3
+#define FUNC_GPIO13_FSPIIO7                         2
+#define FUNC_GPIO13_GPIO13                          1
+#define FUNC_GPIO13_GPIO13_0                        0
+
+#define PERIPHS_IO_MUX_GPIO14_U           (REG_IO_MUX_BASE +0x3c)
+#define FUNC_GPIO14_FSPIWP                          4
+#define FUNC_GPIO14_SUBSPIWP                        3
+#define FUNC_GPIO14_FSPIDQS                         2
+#define FUNC_GPIO14_GPIO14                          1
+#define FUNC_GPIO14_GPIO14_0                        0
+
+#define PERIPHS_IO_MUX_XTAL_32K_P_U       (REG_IO_MUX_BASE +0x40)
+#define FUNC_XTAL_32K_P_U0RTS                       2
+#define FUNC_XTAL_32K_P_GPIO15                      1
+#define FUNC_XTAL_32K_P_GPIO15_0                    0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U       (REG_IO_MUX_BASE +0x44)
+#define FUNC_XTAL_32K_N_U0CTS                       2
+#define FUNC_XTAL_32K_N_GPIO16                      1
+#define FUNC_XTAL_32K_N_GPIO16_0                    0
+
+#define PERIPHS_IO_MUX_DAC_1_U            (REG_IO_MUX_BASE +0x48)
+#define FUNC_DAC_1_U1TXD                            2
+#define FUNC_DAC_1_GPIO17                           1
+#define FUNC_DAC_1_GPIO17_0                         0
+
+#define PERIPHS_IO_MUX_DAC_2_U            (REG_IO_MUX_BASE +0x4c)
+#define FUNC_DAC_2_CLK_OUT3                         3
+#define FUNC_DAC_2_U1RXD                            2
+#define FUNC_DAC_2_GPIO18                           1
+#define FUNC_DAC_2_GPIO18_0                         0
+
+#define PERIPHS_IO_MUX_GPIO19_U           (REG_IO_MUX_BASE +0x50)
+#define FUNC_GPIO19_CLK_OUT2                        3
+#define FUNC_GPIO19_U1RTS                           2
+#define FUNC_GPIO19_GPIO19                          1
+#define FUNC_GPIO19_GPIO19_0                        0
+
+#define PERIPHS_IO_MUX_GPIO20_U           (REG_IO_MUX_BASE +0x54)
+#define FUNC_GPIO20_CLK_OUT1                        3
+#define FUNC_GPIO20_U1CTS                           2
+#define FUNC_GPIO20_GPIO20                          1
+#define FUNC_GPIO20_GPIO20_0                        0
+
+#define PERIPHS_IO_MUX_GPIO21_U           (REG_IO_MUX_BASE +0x58)
+#define FUNC_GPIO21_GPIO21                          1
+#define FUNC_GPIO21_GPIO21_0                        0
+
+#define PERIPHS_IO_MUX_SPICS1_U           (REG_IO_MUX_BASE +0x6c)
+#define FUNC_SPICS1_GPIO26                          1
+#define FUNC_SPICS1_SPICS1                          0
+
+#define PERIPHS_IO_MUX_SPIHD_U            (REG_IO_MUX_BASE +0x70)
+#define FUNC_SPIHD_GPIO27                           1
+#define FUNC_SPIHD_SPIHD                            0
+
+#define PERIPHS_IO_MUX_SPIWP_U            (REG_IO_MUX_BASE +0x74)
+#define FUNC_SPIWP_GPIO28                           1
+#define FUNC_SPIWP_SPIWP                            0
+
+#define PERIPHS_IO_MUX_SPICS0_U           (REG_IO_MUX_BASE +0x78)
+#define FUNC_SPICS0_GPIO29                          1
+#define FUNC_SPICS0_SPICS0                          0
+
+#define PERIPHS_IO_MUX_SPICLK_U           (REG_IO_MUX_BASE +0x7c)
+#define FUNC_SPICLK_GPIO30                          1
+#define FUNC_SPICLK_SPICLK                          0
+
+#define PERIPHS_IO_MUX_SPIQ_U             (REG_IO_MUX_BASE +0x80)
+#define FUNC_SPIQ_GPIO31                            1
+#define FUNC_SPIQ_SPIQ                              0
+
+#define PERIPHS_IO_MUX_SPID_U             (REG_IO_MUX_BASE +0x84)
+#define FUNC_SPID_GPIO32                            1
+#define FUNC_SPID_SPID                              0
+
+#define PERIPHS_IO_MUX_GPIO33_U           (REG_IO_MUX_BASE +0x88)
+#define FUNC_GPIO33_SPIIO4                          4
+#define FUNC_GPIO33_SUBSPIHD                        3
+#define FUNC_GPIO33_FSPIHD                          2
+#define FUNC_GPIO33_GPIO33                          1
+#define FUNC_GPIO33_GPIO33_0                        0
+
+#define PERIPHS_IO_MUX_GPIO34_U           (REG_IO_MUX_BASE +0x8c)
+#define FUNC_GPIO34_SPIIO5                          4
+#define FUNC_GPIO34_SUBSPICS0                       3
+#define FUNC_GPIO34_FSPICS0                         2
+#define FUNC_GPIO34_GPIO34                          1
+#define FUNC_GPIO34_GPIO34_0                        0
+
+#define PERIPHS_IO_MUX_GPIO35_U           (REG_IO_MUX_BASE +0x90)
+#define FUNC_GPIO35_SPIIO6                          4
+#define FUNC_GPIO35_SUBSPID                         3
+#define FUNC_GPIO35_FSPID                           2
+#define FUNC_GPIO35_GPIO35                          1
+#define FUNC_GPIO35_GPIO35_0                        0
+
+#define PERIPHS_IO_MUX_GPIO36_U           (REG_IO_MUX_BASE +0x94)
+#define FUNC_GPIO36_SPIIO7                          4
+#define FUNC_GPIO36_SUBSPICLK                       3
+#define FUNC_GPIO36_FSPICLK                         2
+#define FUNC_GPIO36_GPIO36                          1
+#define FUNC_GPIO36_GPIO36_0                        0
+
+#define PERIPHS_IO_MUX_GPIO37_U           (REG_IO_MUX_BASE +0x98)
+#define FUNC_GPIO37_SPIDQS                          4
+#define FUNC_GPIO37_SUBSPIQ                         3
+#define FUNC_GPIO37_FSPIQ                           2
+#define FUNC_GPIO37_GPIO37                          1
+#define FUNC_GPIO37_GPIO37_0                        0
+
+#define PERIPHS_IO_MUX_GPIO38_U           (REG_IO_MUX_BASE +0x9c)
+#define FUNC_GPIO38_SUBSPIWP                        3
+#define FUNC_GPIO38_FSPIWP                          2
+#define FUNC_GPIO38_GPIO38                          1
+#define FUNC_GPIO38_GPIO38_0                        0
+
+#define PERIPHS_IO_MUX_MTCK_U             (REG_IO_MUX_BASE +0xa0)
+#define FUNC_MTCK_SUBSPICS1                         3
+#define FUNC_MTCK_CLK_OUT3                          2
+#define FUNC_MTCK_GPIO39                            1
+#define FUNC_MTCK_MTCK                              0
+
+#define PERIPHS_IO_MUX_MTDO_U             (REG_IO_MUX_BASE +0xa4)
+#define FUNC_MTDO_CLK_OUT2                          2
+#define FUNC_MTDO_GPIO40                            1
+#define FUNC_MTDO_MTDO                              0
+
+#define PERIPHS_IO_MUX_MTDI_U             (REG_IO_MUX_BASE +0xa8)
+#define FUNC_MTDI_CLK_OUT1                          2
+#define FUNC_MTDI_GPIO41                            1
+#define FUNC_MTDI_MTDI                              0
+
+#define PERIPHS_IO_MUX_MTMS_U             (REG_IO_MUX_BASE +0xac)
+#define FUNC_MTMS_GPIO42                            1
+#define FUNC_MTMS_MTMS                              0
+
+#define PERIPHS_IO_MUX_U0TXD_U            (REG_IO_MUX_BASE +0xb0)
+#define FUNC_U0TXD_CLK_OUT1                         2
+#define FUNC_U0TXD_GPIO43                           1
+#define FUNC_U0TXD_U0TXD                            0
+
+#define PERIPHS_IO_MUX_U0RXD_U            (REG_IO_MUX_BASE +0xb4)
+#define FUNC_U0RXD_CLK_OUT2                         2
+#define FUNC_U0RXD_GPIO44                           1
+#define FUNC_U0RXD_U0RXD                            0
+
+#define PERIPHS_IO_MUX_GPIO45_U           (REG_IO_MUX_BASE +0xb8)
+#define FUNC_GPIO45_GPIO45                          1
+#define FUNC_GPIO45_GPIO45_0                        0
+
+#define PERIPHS_IO_MUX_GPIO46_U           (REG_IO_MUX_BASE +0xbc)
+#define FUNC_GPIO46_GPIO46                          1
+#define FUNC_GPIO46_GPIO46_0                        0
+
+#define PERIPHS_IO_MUX_SPICLK_P_U         (REG_IO_MUX_BASE +0xc0)
+#define FUNC_SPICLK_P_SUBSPICLK_DIFF                2
+#define FUNC_SPICLK_P_GPIO47                        1
+#define FUNC_SPICLK_P_SPICLK_DIFF                   0
+
+#define PERIPHS_IO_MUX_SPICLK_N_U         (REG_IO_MUX_BASE +0xc4)
+#define FUNC_SPICLK_N_SUBSPICLK_DIFF                2
+#define FUNC_SPICLK_N_GPIO48                        1
+#define FUNC_SPICLK_N_SPICLK_DIFF                   0
+
+
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+#define IO_MUX_DATE 0xFFFFFFFF
+#define IO_MUX_DATE_S 0
+#define IO_MUX_DATE_VERSION 0x1907160
diff --git a/components/soc/esp32s3/include/soc/lcd_cam_reg.h b/components/soc/esp32s3/register/soc/lcd_cam_reg.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/lcd_cam_reg.h
rename to components/soc/esp32s3/register/soc/lcd_cam_reg.h
diff --git a/components/soc/esp32s3/include/soc/lcd_cam_struct.h b/components/soc/esp32s3/register/soc/lcd_cam_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/lcd_cam_struct.h
rename to components/soc/esp32s3/register/soc/lcd_cam_struct.h
diff --git a/components/soc/esp32s3/register/soc/ledc_reg.h b/components/soc/esp32s3/register/soc/ledc_reg.h
new file mode 100644
index 00000000000..1a4d70e2635
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/ledc_reg.h
@@ -0,0 +1,1559 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "soc/soc.h"
+
+#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000)
+/* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_ST_LSCH0 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH0_M (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH0_V 0x1
+#define LEDC_OVF_CNT_RESET_ST_LSCH0_S 17
+/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH0 (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH0_M (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH0_V 0x1
+#define LEDC_OVF_CNT_RESET_LSCH0_S 16
+/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH0 (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_M (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_V 0x1
+#define LEDC_OVF_CNT_EN_LSCH0_S 15
+/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH0 0x000003FF
+#define LEDC_OVF_NUM_LSCH0_M ((LEDC_OVF_NUM_LSCH0_V) << (LEDC_OVF_NUM_LSCH0_S))
+#define LEDC_OVF_NUM_LSCH0_V 0x3FF
+#define LEDC_OVF_NUM_LSCH0_S 5
+/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH0 (BIT(4))
+#define LEDC_PARA_UP_LSCH0_M (BIT(4))
+#define LEDC_PARA_UP_LSCH0_V 0x1
+#define LEDC_PARA_UP_LSCH0_S 4
+/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH0 (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_V 0x1
+#define LEDC_IDLE_LV_LSCH0_S 3
+/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH0_S 2
+/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH0 0x00000003
+#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V) << (LEDC_TIMER_SEL_LSCH0_S))
+#define LEDC_TIMER_SEL_LSCH0_V 0x3
+#define LEDC_TIMER_SEL_LSCH0_S 0
+
+#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004)
+/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH0 0x00003FFF
+#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V) << (LEDC_HPOINT_LSCH0_S))
+#define LEDC_HPOINT_LSCH0_V 0x3FFF
+#define LEDC_HPOINT_LSCH0_S 0
+
+#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008)
+/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH0 0x0007FFFF
+#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V) << (LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V 0x7FFFF
+#define LEDC_DUTY_LSCH0_S 0
+
+#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C)
+/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH0 (BIT(31))
+#define LEDC_DUTY_START_LSCH0_M (BIT(31))
+#define LEDC_DUTY_START_LSCH0_V 0x1
+#define LEDC_DUTY_START_LSCH0_S 31
+/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH0 (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_V 0x1
+#define LEDC_DUTY_INC_LSCH0_S 30
+/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH0 0x000003FF
+#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V) << (LEDC_DUTY_NUM_LSCH0_S))
+#define LEDC_DUTY_NUM_LSCH0_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH0_S 20
+/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V) << (LEDC_DUTY_CYCLE_LSCH0_S))
+#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH0_S 10
+/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH0 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V) << (LEDC_DUTY_SCALE_LSCH0_S))
+#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH0_S 0
+
+#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010)
+/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH0 0x0007FFFF
+#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V) << (LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V 0x7FFFF
+#define LEDC_DUTY_LSCH0_S 0
+
+#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014)
+/* LEDC_OVF_CNT_RESET_ST_LSCH1 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_ST_LSCH1 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH1_M (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH1_V 0x1
+#define LEDC_OVF_CNT_RESET_ST_LSCH1_S 17
+/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH1 (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH1_M (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH1_V 0x1
+#define LEDC_OVF_CNT_RESET_LSCH1_S 16
+/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH1 (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_M (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_V 0x1
+#define LEDC_OVF_CNT_EN_LSCH1_S 15
+/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH1 0x000003FF
+#define LEDC_OVF_NUM_LSCH1_M ((LEDC_OVF_NUM_LSCH1_V) << (LEDC_OVF_NUM_LSCH1_S))
+#define LEDC_OVF_NUM_LSCH1_V 0x3FF
+#define LEDC_OVF_NUM_LSCH1_S 5
+/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH1 (BIT(4))
+#define LEDC_PARA_UP_LSCH1_M (BIT(4))
+#define LEDC_PARA_UP_LSCH1_V 0x1
+#define LEDC_PARA_UP_LSCH1_S 4
+/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH1 (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_V 0x1
+#define LEDC_IDLE_LV_LSCH1_S 3
+/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH1_S 2
+/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH1 0x00000003
+#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V) << (LEDC_TIMER_SEL_LSCH1_S))
+#define LEDC_TIMER_SEL_LSCH1_V 0x3
+#define LEDC_TIMER_SEL_LSCH1_S 0
+
+#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018)
+/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH1 0x00003FFF
+#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V) << (LEDC_HPOINT_LSCH1_S))
+#define LEDC_HPOINT_LSCH1_V 0x3FFF
+#define LEDC_HPOINT_LSCH1_S 0
+
+#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C)
+/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH1 0x0007FFFF
+#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V) << (LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V 0x7FFFF
+#define LEDC_DUTY_LSCH1_S 0
+
+#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020)
+/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH1 (BIT(31))
+#define LEDC_DUTY_START_LSCH1_M (BIT(31))
+#define LEDC_DUTY_START_LSCH1_V 0x1
+#define LEDC_DUTY_START_LSCH1_S 31
+/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH1 (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_V 0x1
+#define LEDC_DUTY_INC_LSCH1_S 30
+/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH1 0x000003FF
+#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V) << (LEDC_DUTY_NUM_LSCH1_S))
+#define LEDC_DUTY_NUM_LSCH1_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH1_S 20
+/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V) << (LEDC_DUTY_CYCLE_LSCH1_S))
+#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH1_S 10
+/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH1 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V) << (LEDC_DUTY_SCALE_LSCH1_S))
+#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH1_S 0
+
+#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024)
+/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH1 0x0007FFFF
+#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V) << (LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V 0x7FFFF
+#define LEDC_DUTY_LSCH1_S 0
+
+#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028)
+/* LEDC_OVF_CNT_RESET_ST_LSCH2 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_ST_LSCH2 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH2_M (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH2_V 0x1
+#define LEDC_OVF_CNT_RESET_ST_LSCH2_S 17
+/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH2 (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH2_M (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH2_V 0x1
+#define LEDC_OVF_CNT_RESET_LSCH2_S 16
+/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH2 (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_M (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_V 0x1
+#define LEDC_OVF_CNT_EN_LSCH2_S 15
+/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH2 0x000003FF
+#define LEDC_OVF_NUM_LSCH2_M ((LEDC_OVF_NUM_LSCH2_V) << (LEDC_OVF_NUM_LSCH2_S))
+#define LEDC_OVF_NUM_LSCH2_V 0x3FF
+#define LEDC_OVF_NUM_LSCH2_S 5
+/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH2 (BIT(4))
+#define LEDC_PARA_UP_LSCH2_M (BIT(4))
+#define LEDC_PARA_UP_LSCH2_V 0x1
+#define LEDC_PARA_UP_LSCH2_S 4
+/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH2 (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_V 0x1
+#define LEDC_IDLE_LV_LSCH2_S 3
+/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH2_S 2
+/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH2 0x00000003
+#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V) << (LEDC_TIMER_SEL_LSCH2_S))
+#define LEDC_TIMER_SEL_LSCH2_V 0x3
+#define LEDC_TIMER_SEL_LSCH2_S 0
+
+#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C)
+/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH2 0x00003FFF
+#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V) << (LEDC_HPOINT_LSCH2_S))
+#define LEDC_HPOINT_LSCH2_V 0x3FFF
+#define LEDC_HPOINT_LSCH2_S 0
+
+#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030)
+/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH2 0x0007FFFF
+#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V) << (LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V 0x7FFFF
+#define LEDC_DUTY_LSCH2_S 0
+
+#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034)
+/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH2 (BIT(31))
+#define LEDC_DUTY_START_LSCH2_M (BIT(31))
+#define LEDC_DUTY_START_LSCH2_V 0x1
+#define LEDC_DUTY_START_LSCH2_S 31
+/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH2 (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_V 0x1
+#define LEDC_DUTY_INC_LSCH2_S 30
+/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH2 0x000003FF
+#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V) << (LEDC_DUTY_NUM_LSCH2_S))
+#define LEDC_DUTY_NUM_LSCH2_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH2_S 20
+/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V) << (LEDC_DUTY_CYCLE_LSCH2_S))
+#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH2_S 10
+/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH2 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V) << (LEDC_DUTY_SCALE_LSCH2_S))
+#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH2_S 0
+
+#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038)
+/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH2 0x0007FFFF
+#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V) << (LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V 0x7FFFF
+#define LEDC_DUTY_LSCH2_S 0
+
+#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C)
+/* LEDC_OVF_CNT_RESET_ST_LSCH3 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_ST_LSCH3 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH3_M (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH3_V 0x1
+#define LEDC_OVF_CNT_RESET_ST_LSCH3_S 17
+/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH3 (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH3_M (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH3_V 0x1
+#define LEDC_OVF_CNT_RESET_LSCH3_S 16
+/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH3 (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_M (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_V 0x1
+#define LEDC_OVF_CNT_EN_LSCH3_S 15
+/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH3 0x000003FF
+#define LEDC_OVF_NUM_LSCH3_M ((LEDC_OVF_NUM_LSCH3_V) << (LEDC_OVF_NUM_LSCH3_S))
+#define LEDC_OVF_NUM_LSCH3_V 0x3FF
+#define LEDC_OVF_NUM_LSCH3_S 5
+/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH3 (BIT(4))
+#define LEDC_PARA_UP_LSCH3_M (BIT(4))
+#define LEDC_PARA_UP_LSCH3_V 0x1
+#define LEDC_PARA_UP_LSCH3_S 4
+/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH3 (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_V 0x1
+#define LEDC_IDLE_LV_LSCH3_S 3
+/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH3_S 2
+/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH3 0x00000003
+#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V) << (LEDC_TIMER_SEL_LSCH3_S))
+#define LEDC_TIMER_SEL_LSCH3_V 0x3
+#define LEDC_TIMER_SEL_LSCH3_S 0
+
+#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040)
+/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH3 0x00003FFF
+#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V) << (LEDC_HPOINT_LSCH3_S))
+#define LEDC_HPOINT_LSCH3_V 0x3FFF
+#define LEDC_HPOINT_LSCH3_S 0
+
+#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044)
+/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH3 0x0007FFFF
+#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V) << (LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V 0x7FFFF
+#define LEDC_DUTY_LSCH3_S 0
+
+#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048)
+/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH3 (BIT(31))
+#define LEDC_DUTY_START_LSCH3_M (BIT(31))
+#define LEDC_DUTY_START_LSCH3_V 0x1
+#define LEDC_DUTY_START_LSCH3_S 31
+/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH3 (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_V 0x1
+#define LEDC_DUTY_INC_LSCH3_S 30
+/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH3 0x000003FF
+#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V) << (LEDC_DUTY_NUM_LSCH3_S))
+#define LEDC_DUTY_NUM_LSCH3_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH3_S 20
+/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V) << (LEDC_DUTY_CYCLE_LSCH3_S))
+#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH3_S 10
+/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH3 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V) << (LEDC_DUTY_SCALE_LSCH3_S))
+#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH3_S 0
+
+#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C)
+/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH3 0x0007FFFF
+#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V) << (LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V 0x7FFFF
+#define LEDC_DUTY_LSCH3_S 0
+
+#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050)
+/* LEDC_OVF_CNT_RESET_ST_LSCH4 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_ST_LSCH4 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH4_M (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH4_V 0x1
+#define LEDC_OVF_CNT_RESET_ST_LSCH4_S 17
+/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH4 (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH4_M (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH4_V 0x1
+#define LEDC_OVF_CNT_RESET_LSCH4_S 16
+/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH4 (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_M (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_V 0x1
+#define LEDC_OVF_CNT_EN_LSCH4_S 15
+/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH4 0x000003FF
+#define LEDC_OVF_NUM_LSCH4_M ((LEDC_OVF_NUM_LSCH4_V) << (LEDC_OVF_NUM_LSCH4_S))
+#define LEDC_OVF_NUM_LSCH4_V 0x3FF
+#define LEDC_OVF_NUM_LSCH4_S 5
+/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH4 (BIT(4))
+#define LEDC_PARA_UP_LSCH4_M (BIT(4))
+#define LEDC_PARA_UP_LSCH4_V 0x1
+#define LEDC_PARA_UP_LSCH4_S 4
+/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH4 (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_V 0x1
+#define LEDC_IDLE_LV_LSCH4_S 3
+/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH4_S 2
+/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH4 0x00000003
+#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V) << (LEDC_TIMER_SEL_LSCH4_S))
+#define LEDC_TIMER_SEL_LSCH4_V 0x3
+#define LEDC_TIMER_SEL_LSCH4_S 0
+
+#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054)
+/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH4 0x00003FFF
+#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V) << (LEDC_HPOINT_LSCH4_S))
+#define LEDC_HPOINT_LSCH4_V 0x3FFF
+#define LEDC_HPOINT_LSCH4_S 0
+
+#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058)
+/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH4 0x0007FFFF
+#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V) << (LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V 0x7FFFF
+#define LEDC_DUTY_LSCH4_S 0
+
+#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C)
+/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH4 (BIT(31))
+#define LEDC_DUTY_START_LSCH4_M (BIT(31))
+#define LEDC_DUTY_START_LSCH4_V 0x1
+#define LEDC_DUTY_START_LSCH4_S 31
+/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH4 (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_V 0x1
+#define LEDC_DUTY_INC_LSCH4_S 30
+/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH4 0x000003FF
+#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V) << (LEDC_DUTY_NUM_LSCH4_S))
+#define LEDC_DUTY_NUM_LSCH4_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH4_S 20
+/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V) << (LEDC_DUTY_CYCLE_LSCH4_S))
+#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH4_S 10
+/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH4 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V) << (LEDC_DUTY_SCALE_LSCH4_S))
+#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH4_S 0
+
+#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060)
+/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH4 0x0007FFFF
+#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V) << (LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V 0x7FFFF
+#define LEDC_DUTY_LSCH4_S 0
+
+#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064)
+/* LEDC_OVF_CNT_RESET_ST_LSCH5 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_ST_LSCH5 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH5_M (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH5_V 0x1
+#define LEDC_OVF_CNT_RESET_ST_LSCH5_S 17
+/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH5 (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH5_M (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH5_V 0x1
+#define LEDC_OVF_CNT_RESET_LSCH5_S 16
+/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH5 (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_M (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_V 0x1
+#define LEDC_OVF_CNT_EN_LSCH5_S 15
+/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH5 0x000003FF
+#define LEDC_OVF_NUM_LSCH5_M ((LEDC_OVF_NUM_LSCH5_V) << (LEDC_OVF_NUM_LSCH5_S))
+#define LEDC_OVF_NUM_LSCH5_V 0x3FF
+#define LEDC_OVF_NUM_LSCH5_S 5
+/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH5 (BIT(4))
+#define LEDC_PARA_UP_LSCH5_M (BIT(4))
+#define LEDC_PARA_UP_LSCH5_V 0x1
+#define LEDC_PARA_UP_LSCH5_S 4
+/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH5 (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_V 0x1
+#define LEDC_IDLE_LV_LSCH5_S 3
+/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH5_S 2
+/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH5 0x00000003
+#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V) << (LEDC_TIMER_SEL_LSCH5_S))
+#define LEDC_TIMER_SEL_LSCH5_V 0x3
+#define LEDC_TIMER_SEL_LSCH5_S 0
+
+#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068)
+/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH5 0x00003FFF
+#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V) << (LEDC_HPOINT_LSCH5_S))
+#define LEDC_HPOINT_LSCH5_V 0x3FFF
+#define LEDC_HPOINT_LSCH5_S 0
+
+#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C)
+/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH5 0x0007FFFF
+#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V) << (LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V 0x7FFFF
+#define LEDC_DUTY_LSCH5_S 0
+
+#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070)
+/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH5 (BIT(31))
+#define LEDC_DUTY_START_LSCH5_M (BIT(31))
+#define LEDC_DUTY_START_LSCH5_V 0x1
+#define LEDC_DUTY_START_LSCH5_S 31
+/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH5 (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_V 0x1
+#define LEDC_DUTY_INC_LSCH5_S 30
+/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH5 0x000003FF
+#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V) << (LEDC_DUTY_NUM_LSCH5_S))
+#define LEDC_DUTY_NUM_LSCH5_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH5_S 20
+/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V) << (LEDC_DUTY_CYCLE_LSCH5_S))
+#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH5_S 10
+/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH5 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V) << (LEDC_DUTY_SCALE_LSCH5_S))
+#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH5_S 0
+
+#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074)
+/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH5 0x0007FFFF
+#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V) << (LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V 0x7FFFF
+#define LEDC_DUTY_LSCH5_S 0
+
+#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078)
+/* LEDC_OVF_CNT_RESET_ST_LSCH6 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_ST_LSCH6 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH6_M (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH6_V 0x1
+#define LEDC_OVF_CNT_RESET_ST_LSCH6_S 17
+/* LEDC_OVF_CNT_RESET_LSCH6 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH6 (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH6_M (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH6_V 0x1
+#define LEDC_OVF_CNT_RESET_LSCH6_S 16
+/* LEDC_OVF_CNT_EN_LSCH6 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH6 (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH6_M (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH6_V 0x1
+#define LEDC_OVF_CNT_EN_LSCH6_S 15
+/* LEDC_OVF_NUM_LSCH6 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH6 0x000003FF
+#define LEDC_OVF_NUM_LSCH6_M ((LEDC_OVF_NUM_LSCH6_V) << (LEDC_OVF_NUM_LSCH6_S))
+#define LEDC_OVF_NUM_LSCH6_V 0x3FF
+#define LEDC_OVF_NUM_LSCH6_S 5
+/* LEDC_PARA_UP_LSCH6 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH6 (BIT(4))
+#define LEDC_PARA_UP_LSCH6_M (BIT(4))
+#define LEDC_PARA_UP_LSCH6_V 0x1
+#define LEDC_PARA_UP_LSCH6_S 4
+/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH6 (BIT(3))
+#define LEDC_IDLE_LV_LSCH6_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH6_V 0x1
+#define LEDC_IDLE_LV_LSCH6_S 3
+/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH6_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH6_S 2
+/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH6 0x00000003
+#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V) << (LEDC_TIMER_SEL_LSCH6_S))
+#define LEDC_TIMER_SEL_LSCH6_V 0x3
+#define LEDC_TIMER_SEL_LSCH6_S 0
+
+#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C)
+/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH6 0x00003FFF
+#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V) << (LEDC_HPOINT_LSCH6_S))
+#define LEDC_HPOINT_LSCH6_V 0x3FFF
+#define LEDC_HPOINT_LSCH6_S 0
+
+#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080)
+/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH6 0x0007FFFF
+#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V) << (LEDC_DUTY_LSCH6_S))
+#define LEDC_DUTY_LSCH6_V 0x7FFFF
+#define LEDC_DUTY_LSCH6_S 0
+
+#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084)
+/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH6 (BIT(31))
+#define LEDC_DUTY_START_LSCH6_M (BIT(31))
+#define LEDC_DUTY_START_LSCH6_V 0x1
+#define LEDC_DUTY_START_LSCH6_S 31
+/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH6 (BIT(30))
+#define LEDC_DUTY_INC_LSCH6_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH6_V 0x1
+#define LEDC_DUTY_INC_LSCH6_S 30
+/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH6 0x000003FF
+#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V) << (LEDC_DUTY_NUM_LSCH6_S))
+#define LEDC_DUTY_NUM_LSCH6_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH6_S 20
+/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V) << (LEDC_DUTY_CYCLE_LSCH6_S))
+#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH6_S 10
+/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH6 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V) << (LEDC_DUTY_SCALE_LSCH6_S))
+#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH6_S 0
+
+#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088)
+/* LEDC_DUTY_LSCH6 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH6 0x0007FFFF
+#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V) << (LEDC_DUTY_LSCH6_S))
+#define LEDC_DUTY_LSCH6_V 0x7FFFF
+#define LEDC_DUTY_LSCH6_S 0
+
+#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C)
+/* LEDC_OVF_CNT_RESET_ST_LSCH7 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_ST_LSCH7 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH7_M (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_LSCH7_V 0x1
+#define LEDC_OVF_CNT_RESET_ST_LSCH7_S 17
+/* LEDC_OVF_CNT_RESET_LSCH7 : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_RESET_LSCH7 (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH7_M (BIT(16))
+#define LEDC_OVF_CNT_RESET_LSCH7_V 0x1
+#define LEDC_OVF_CNT_RESET_LSCH7_S 16
+/* LEDC_OVF_CNT_EN_LSCH7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH7 (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH7_M (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH7_V 0x1
+#define LEDC_OVF_CNT_EN_LSCH7_S 15
+/* LEDC_OVF_NUM_LSCH7 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH7 0x000003FF
+#define LEDC_OVF_NUM_LSCH7_M ((LEDC_OVF_NUM_LSCH7_V) << (LEDC_OVF_NUM_LSCH7_S))
+#define LEDC_OVF_NUM_LSCH7_V 0x3FF
+#define LEDC_OVF_NUM_LSCH7_S 5
+/* LEDC_PARA_UP_LSCH7 : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_PARA_UP_LSCH7 (BIT(4))
+#define LEDC_PARA_UP_LSCH7_M (BIT(4))
+#define LEDC_PARA_UP_LSCH7_V 0x1
+#define LEDC_PARA_UP_LSCH7_S 4
+/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_IDLE_LV_LSCH7 (BIT(3))
+#define LEDC_IDLE_LV_LSCH7_M (BIT(3))
+#define LEDC_IDLE_LV_LSCH7_V 0x1
+#define LEDC_IDLE_LV_LSCH7_S 3
+/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH7_V 0x1
+#define LEDC_SIG_OUT_EN_LSCH7_S 2
+/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define LEDC_TIMER_SEL_LSCH7 0x00000003
+#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V) << (LEDC_TIMER_SEL_LSCH7_S))
+#define LEDC_TIMER_SEL_LSCH7_V 0x3
+#define LEDC_TIMER_SEL_LSCH7_S 0
+
+#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090)
+/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: */
+#define LEDC_HPOINT_LSCH7 0x00003FFF
+#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V) << (LEDC_HPOINT_LSCH7_S))
+#define LEDC_HPOINT_LSCH7_V 0x3FFF
+#define LEDC_HPOINT_LSCH7_S 0
+
+#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094)
+/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH7 0x0007FFFF
+#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V) << (LEDC_DUTY_LSCH7_S))
+#define LEDC_DUTY_LSCH7_V 0x7FFFF
+#define LEDC_DUTY_LSCH7_S 0
+
+#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098)
+/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_START_LSCH7 (BIT(31))
+#define LEDC_DUTY_START_LSCH7_M (BIT(31))
+#define LEDC_DUTY_START_LSCH7_V 0x1
+#define LEDC_DUTY_START_LSCH7_S 31
+/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_DUTY_INC_LSCH7 (BIT(30))
+#define LEDC_DUTY_INC_LSCH7_M (BIT(30))
+#define LEDC_DUTY_INC_LSCH7_V 0x1
+#define LEDC_DUTY_INC_LSCH7_S 30
+/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_NUM_LSCH7 0x000003FF
+#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V) << (LEDC_DUTY_NUM_LSCH7_S))
+#define LEDC_DUTY_NUM_LSCH7_V 0x3FF
+#define LEDC_DUTY_NUM_LSCH7_S 20
+/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V) << (LEDC_DUTY_CYCLE_LSCH7_S))
+#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF
+#define LEDC_DUTY_CYCLE_LSCH7_S 10
+/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define LEDC_DUTY_SCALE_LSCH7 0x000003FF
+#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V) << (LEDC_DUTY_SCALE_LSCH7_S))
+#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF
+#define LEDC_DUTY_SCALE_LSCH7_S 0
+
+#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C)
+/* LEDC_DUTY_LSCH7 : RO ;bitpos:[18:0] ;default: 19'h0 ; */
+/*description: */
+#define LEDC_DUTY_LSCH7 0x0007FFFF
+#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V) << (LEDC_DUTY_LSCH7_S))
+#define LEDC_DUTY_LSCH7_V 0x7FFFF
+#define LEDC_DUTY_LSCH7_S 0
+
+#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x00a0)
+/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_PARA_UP (BIT(25))
+#define LEDC_LSTIMER0_PARA_UP_M (BIT(25))
+#define LEDC_LSTIMER0_PARA_UP_V 0x1
+#define LEDC_LSTIMER0_PARA_UP_S 25
+/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER0 (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER0_M (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER0_V 0x1
+#define LEDC_TICK_SEL_LSTIMER0_S 24
+/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER0_RST (BIT(23))
+#define LEDC_LSTIMER0_RST_M (BIT(23))
+#define LEDC_LSTIMER0_RST_V 0x1
+#define LEDC_LSTIMER0_RST_S 23
+/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_PAUSE (BIT(22))
+#define LEDC_LSTIMER0_PAUSE_M (BIT(22))
+#define LEDC_LSTIMER0_PAUSE_V 0x1
+#define LEDC_LSTIMER0_PAUSE_S 22
+/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER0 0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER0_M ((LEDC_CLK_DIV_LSTIMER0_V) << (LEDC_CLK_DIV_LSTIMER0_S))
+#define LEDC_CLK_DIV_LSTIMER0_V 0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER0_S 4
+/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_DUTY_RES 0x0000000F
+#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V) << (LEDC_LSTIMER0_DUTY_RES_S))
+#define LEDC_LSTIMER0_DUTY_RES_V 0xF
+#define LEDC_LSTIMER0_DUTY_RES_S 0
+
+#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x00a4)
+/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_CNT 0x00003FFF
+#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V) << (LEDC_LSTIMER0_CNT_S))
+#define LEDC_LSTIMER0_CNT_V 0x3FFF
+#define LEDC_LSTIMER0_CNT_S 0
+
+#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x00a8)
+/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_PARA_UP (BIT(25))
+#define LEDC_LSTIMER1_PARA_UP_M (BIT(25))
+#define LEDC_LSTIMER1_PARA_UP_V 0x1
+#define LEDC_LSTIMER1_PARA_UP_S 25
+/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER1 (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER1_M (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER1_V 0x1
+#define LEDC_TICK_SEL_LSTIMER1_S 24
+/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER1_RST (BIT(23))
+#define LEDC_LSTIMER1_RST_M (BIT(23))
+#define LEDC_LSTIMER1_RST_V 0x1
+#define LEDC_LSTIMER1_RST_S 23
+/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_PAUSE (BIT(22))
+#define LEDC_LSTIMER1_PAUSE_M (BIT(22))
+#define LEDC_LSTIMER1_PAUSE_V 0x1
+#define LEDC_LSTIMER1_PAUSE_S 22
+/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER1 0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER1_M ((LEDC_CLK_DIV_LSTIMER1_V) << (LEDC_CLK_DIV_LSTIMER1_S))
+#define LEDC_CLK_DIV_LSTIMER1_V 0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER1_S 4
+/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_DUTY_RES 0x0000000F
+#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V) << (LEDC_LSTIMER1_DUTY_RES_S))
+#define LEDC_LSTIMER1_DUTY_RES_V 0xF
+#define LEDC_LSTIMER1_DUTY_RES_S 0
+
+#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x00aC)
+/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_CNT 0x00003FFF
+#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V) << (LEDC_LSTIMER1_CNT_S))
+#define LEDC_LSTIMER1_CNT_V 0x3FFF
+#define LEDC_LSTIMER1_CNT_S 0
+
+#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x00b0)
+/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_PARA_UP (BIT(25))
+#define LEDC_LSTIMER2_PARA_UP_M (BIT(25))
+#define LEDC_LSTIMER2_PARA_UP_V 0x1
+#define LEDC_LSTIMER2_PARA_UP_S 25
+/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER2 (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER2_M (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER2_V 0x1
+#define LEDC_TICK_SEL_LSTIMER2_S 24
+/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER2_RST (BIT(23))
+#define LEDC_LSTIMER2_RST_M (BIT(23))
+#define LEDC_LSTIMER2_RST_V 0x1
+#define LEDC_LSTIMER2_RST_S 23
+/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_PAUSE (BIT(22))
+#define LEDC_LSTIMER2_PAUSE_M (BIT(22))
+#define LEDC_LSTIMER2_PAUSE_V 0x1
+#define LEDC_LSTIMER2_PAUSE_S 22
+/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER2 0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER2_M ((LEDC_CLK_DIV_LSTIMER2_V) << (LEDC_CLK_DIV_LSTIMER2_S))
+#define LEDC_CLK_DIV_LSTIMER2_V 0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER2_S 4
+/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_DUTY_RES 0x0000000F
+#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V) << (LEDC_LSTIMER2_DUTY_RES_S))
+#define LEDC_LSTIMER2_DUTY_RES_V 0xF
+#define LEDC_LSTIMER2_DUTY_RES_S 0
+
+#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x00b4)
+/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_CNT 0x00003FFF
+#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V) << (LEDC_LSTIMER2_CNT_S))
+#define LEDC_LSTIMER2_CNT_V 0x3FFF
+#define LEDC_LSTIMER2_CNT_S 0
+
+#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x00b8)
+/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_PARA_UP (BIT(25))
+#define LEDC_LSTIMER3_PARA_UP_M (BIT(25))
+#define LEDC_LSTIMER3_PARA_UP_V 0x1
+#define LEDC_LSTIMER3_PARA_UP_S 25
+/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_TICK_SEL_LSTIMER3 (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER3_M (BIT(24))
+#define LEDC_TICK_SEL_LSTIMER3_V 0x1
+#define LEDC_TICK_SEL_LSTIMER3_S 24
+/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define LEDC_LSTIMER3_RST (BIT(23))
+#define LEDC_LSTIMER3_RST_M (BIT(23))
+#define LEDC_LSTIMER3_RST_V 0x1
+#define LEDC_LSTIMER3_RST_S 23
+/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_PAUSE (BIT(22))
+#define LEDC_LSTIMER3_PAUSE_M (BIT(22))
+#define LEDC_LSTIMER3_PAUSE_V 0x1
+#define LEDC_LSTIMER3_PAUSE_S 22
+/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER3 0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER3_M ((LEDC_CLK_DIV_LSTIMER3_V) << (LEDC_CLK_DIV_LSTIMER3_S))
+#define LEDC_CLK_DIV_LSTIMER3_V 0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER3_S 4
+/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_DUTY_RES 0x0000000F
+#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V) << (LEDC_LSTIMER3_DUTY_RES_S))
+#define LEDC_LSTIMER3_DUTY_RES_V 0xF
+#define LEDC_LSTIMER3_DUTY_RES_S 0
+
+#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x00bC)
+/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_CNT 0x00003FFF
+#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V) << (LEDC_LSTIMER3_CNT_S))
+#define LEDC_LSTIMER3_CNT_V 0x3FFF
+#define LEDC_LSTIMER3_CNT_S 0
+
+#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x00c0)
+/* LEDC_OVF_CNT_LSCH7_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH7_INT_RAW (BIT(19))
+#define LEDC_OVF_CNT_LSCH7_INT_RAW_M (BIT(19))
+#define LEDC_OVF_CNT_LSCH7_INT_RAW_V 0x1
+#define LEDC_OVF_CNT_LSCH7_INT_RAW_S 19
+/* LEDC_OVF_CNT_LSCH6_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH6_INT_RAW (BIT(18))
+#define LEDC_OVF_CNT_LSCH6_INT_RAW_M (BIT(18))
+#define LEDC_OVF_CNT_LSCH6_INT_RAW_V 0x1
+#define LEDC_OVF_CNT_LSCH6_INT_RAW_S 18
+/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_RAW (BIT(17))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_M (BIT(17))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_V 0x1
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_S 17
+/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_RAW (BIT(16))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_M (BIT(16))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_V 0x1
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_S 16
+/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_RAW (BIT(15))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_M (BIT(15))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_V 0x1
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_S 15
+/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_RAW (BIT(14))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_M (BIT(14))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_V 0x1
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_S 14
+/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_RAW (BIT(13))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_M (BIT(13))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_V 0x1
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_S 13
+/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_RAW (BIT(12))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_M (BIT(12))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_V 0x1
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_S 12
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(11))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 11
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(10))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 4
+/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_RAW_S 3
+/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_RAW_S 2
+/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_RAW_S 1
+/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_RAW_S 0
+
+#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x00c4)
+/* LEDC_OVF_CNT_LSCH7_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH7_INT_ST (BIT(19))
+#define LEDC_OVF_CNT_LSCH7_INT_ST_M (BIT(19))
+#define LEDC_OVF_CNT_LSCH7_INT_ST_V 0x1
+#define LEDC_OVF_CNT_LSCH7_INT_ST_S 19
+/* LEDC_OVF_CNT_LSCH6_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH6_INT_ST (BIT(18))
+#define LEDC_OVF_CNT_LSCH6_INT_ST_M (BIT(18))
+#define LEDC_OVF_CNT_LSCH6_INT_ST_V 0x1
+#define LEDC_OVF_CNT_LSCH6_INT_ST_S 18
+/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ST (BIT(17))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_M (BIT(17))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_V 0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ST_S 17
+/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ST (BIT(16))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_M (BIT(16))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_V 0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ST_S 16
+/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ST (BIT(15))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_M (BIT(15))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_V 0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ST_S 15
+/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ST (BIT(14))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_M (BIT(14))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_V 0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ST_S 14
+/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ST (BIT(13))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_M (BIT(13))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_V 0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ST_S 13
+/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ST (BIT(12))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_M (BIT(12))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_V 0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ST_S 12
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(11))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 11
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(10))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 4
+/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_ST (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_ST_S 3
+/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_ST (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_ST_S 2
+/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_ST (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_ST_S 1
+/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_ST (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_ST_S 0
+
+#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x00c8)
+/* LEDC_OVF_CNT_LSCH7_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH7_INT_ENA (BIT(19))
+#define LEDC_OVF_CNT_LSCH7_INT_ENA_M (BIT(19))
+#define LEDC_OVF_CNT_LSCH7_INT_ENA_V 0x1
+#define LEDC_OVF_CNT_LSCH7_INT_ENA_S 19
+/* LEDC_OVF_CNT_LSCH6_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH6_INT_ENA (BIT(18))
+#define LEDC_OVF_CNT_LSCH6_INT_ENA_M (BIT(18))
+#define LEDC_OVF_CNT_LSCH6_INT_ENA_V 0x1
+#define LEDC_OVF_CNT_LSCH6_INT_ENA_S 18
+/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ENA (BIT(17))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_M (BIT(17))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_V 0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_S 17
+/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ENA (BIT(16))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_M (BIT(16))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_V 0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_S 16
+/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ENA (BIT(15))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_M (BIT(15))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_V 0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_S 15
+/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ENA (BIT(14))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_M (BIT(14))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_V 0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_S 14
+/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ENA (BIT(13))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_M (BIT(13))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_V 0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_S 13
+/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ENA (BIT(12))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_M (BIT(12))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_V 0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_S 12
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(11))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 11
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(10))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 4
+/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_ENA_S 3
+/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_ENA_S 2
+/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_ENA_S 1
+/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_ENA_S 0
+
+#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x00cC)
+/* LEDC_OVF_CNT_LSCH7_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH7_INT_CLR (BIT(19))
+#define LEDC_OVF_CNT_LSCH7_INT_CLR_M (BIT(19))
+#define LEDC_OVF_CNT_LSCH7_INT_CLR_V 0x1
+#define LEDC_OVF_CNT_LSCH7_INT_CLR_S 19
+/* LEDC_OVF_CNT_LSCH6_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH6_INT_CLR (BIT(18))
+#define LEDC_OVF_CNT_LSCH6_INT_CLR_M (BIT(18))
+#define LEDC_OVF_CNT_LSCH6_INT_CLR_V 0x1
+#define LEDC_OVF_CNT_LSCH6_INT_CLR_S 18
+/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_CLR (BIT(17))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_M (BIT(17))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_V 0x1
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_S 17
+/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_CLR (BIT(16))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_M (BIT(16))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_V 0x1
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_S 16
+/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_CLR (BIT(15))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_M (BIT(15))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_V 0x1
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_S 15
+/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_CLR (BIT(14))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_M (BIT(14))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_V 0x1
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_S 14
+/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_CLR (BIT(13))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_M (BIT(13))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_V 0x1
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_S 13
+/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_CLR (BIT(12))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_M (BIT(12))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_V 0x1
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_S 12
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(11))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(11))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 11
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(10))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(10))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 10
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(9))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 9
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(8))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 8
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(7))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 7
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(6))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 6
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(5))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 5
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(4))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 4
+/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(3))
+#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER3_OVF_INT_CLR_S 3
+/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(2))
+#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER2_OVF_INT_CLR_S 2
+/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(1))
+#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER1_OVF_INT_CLR_S 1
+/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(0))
+#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1
+#define LEDC_LSTIMER0_OVF_INT_CLR_S 0
+
+#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x00d0)
+/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_CLK_EN (BIT(31))
+#define LEDC_CLK_EN_M (BIT(31))
+#define LEDC_CLK_EN_V 0x1
+#define LEDC_CLK_EN_S 31
+/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define LEDC_APB_CLK_SEL 0x00000003
+#define LEDC_APB_CLK_SEL_M ((LEDC_APB_CLK_SEL_V) << (LEDC_APB_CLK_SEL_S))
+#define LEDC_APB_CLK_SEL_V 0x3
+#define LEDC_APB_CLK_SEL_S 0
+
+#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x00FC)
+/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19040200 ; */
+/*description: */
+#define LEDC_DATE 0xFFFFFFFF
+#define LEDC_DATE_M ((LEDC_DATE_V) << (LEDC_DATE_S))
+#define LEDC_DATE_V 0xFFFFFFFF
+#define LEDC_DATE_S 0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/include/soc/ledc_struct.h b/components/soc/esp32s3/register/soc/ledc_struct.h
similarity index 92%
rename from components/soc/esp32s3/include/soc/ledc_struct.h
rename to components/soc/esp32s3/register/soc/ledc_struct.h
index 85cea78e582..c3e0765a400 100644
--- a/components/soc/esp32s3/include/soc/ledc_struct.h
+++ b/components/soc/esp32s3/register/soc/ledc_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once
 
 #include <stdint.h>
diff --git a/components/soc/esp32s3/register/soc/mcpwm_reg.h b/components/soc/esp32s3/register/soc/mcpwm_reg.h
new file mode 100644
index 00000000000..c8e749dac0c
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/mcpwm_reg.h
@@ -0,0 +1,3829 @@
+/**
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DR_REG_MCPWM_BASE(i) (DR_REG_PWM0_BASE + i * (0xE000))
+
+/** MCPWM_CLK_CFG_REG register
+ *  PWM clock prescaler register.
+ */
+#define MCPWM_CLK_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x0)
+/** MCPWM_CLK_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
+ */
+#define MCPWM_CLK_PRESCALE    0x000000FFU
+#define MCPWM_CLK_PRESCALE_M  (MCPWM_CLK_PRESCALE_V << MCPWM_CLK_PRESCALE_S)
+#define MCPWM_CLK_PRESCALE_V  0x000000FFU
+#define MCPWM_CLK_PRESCALE_S  0
+
+/** MCPWM_TIMER0_CFG0_REG register
+ *  PWM timer0 period and update method configuration register.
+ */
+#define MCPWM_TIMER0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4)
+/** MCPWM_TIMER0_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configure the divisor of PT0_clk, takes effect when PWM timer0 stops and starts
+ *  agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)
+ */
+#define MCPWM_TIMER0_PRESCALE    0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_M  (MCPWM_TIMER0_PRESCALE_V << MCPWM_TIMER0_PRESCALE_S)
+#define MCPWM_TIMER0_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER0_PRESCALE_S  0
+/** MCPWM_TIMER0_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer0
+ */
+#define MCPWM_TIMER0_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_M  (MCPWM_TIMER0_PERIOD_V << MCPWM_TIMER0_PERIOD_S)
+#define MCPWM_TIMER0_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER0_PERIOD_S  8
+/** MCPWM_TIMER0_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ or sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER0_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  (MCPWM_TIMER0_PERIOD_UPMETHOD_V << MCPWM_TIMER0_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER0_CFG1_REG register
+ *  PWM timer0 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8)
+/** MCPWM_TIMER0_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1:
+ *  if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0
+ *  starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER0_START    0x00000007U
+#define MCPWM_TIMER0_START_M  (MCPWM_TIMER0_START_V << MCPWM_TIMER0_START_S)
+#define MCPWM_TIMER0_START_V  0x00000007U
+#define MCPWM_TIMER0_START_S  0
+/** MCPWM_TIMER0_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER0_MOD    0x00000003U
+#define MCPWM_TIMER0_MOD_M  (MCPWM_TIMER0_MOD_V << MCPWM_TIMER0_MOD_S)
+#define MCPWM_TIMER0_MOD_V  0x00000003U
+#define MCPWM_TIMER0_MOD_S  3
+
+/** MCPWM_TIMER0_SYNC_REG register
+ *  PWM timer0 sync function configuration register.
+ */
+#define MCPWM_TIMER0_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc)
+/** MCPWM_TIMER0_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER0_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (MCPWM_TIMER0_SYNCI_EN_V << MCPWM_TIMER0_SYNCI_EN_S)
+#define MCPWM_TIMER0_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+/** MCPWM_TIMER0_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER0_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (MCPWM_TIMER0_SYNC_SW_V << MCPWM_TIMER0_SYNC_SW_S)
+#define MCPWM_TIMER0_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/** MCPWM_TIMER0_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer0_sync_sw bit
+ */
+#define MCPWM_TIMER0_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_M  (MCPWM_TIMER0_SYNCO_SEL_V << MCPWM_TIMER0_SYNCO_SEL_S)
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/** MCPWM_TIMER0_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER0_PHASE    0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_M  (MCPWM_TIMER0_PHASE_V << MCPWM_TIMER0_PHASE_S)
+#define MCPWM_TIMER0_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER0_PHASE_S  4
+/** MCPWM_TIMER0_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer0's direction at the time sync event occurs when timer0 mode
+ *  is up-down mode: 0-increase,1-decrease
+ */
+#define MCPWM_TIMER0_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER0_PHASE_DIRECTION_M  (MCPWM_TIMER0_PHASE_DIRECTION_V << MCPWM_TIMER0_PHASE_DIRECTION_S)
+#define MCPWM_TIMER0_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER0_STATUS_REG register
+ *  PWM timer0 status register.
+ */
+#define MCPWM_TIMER0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10)
+/** MCPWM_TIMER0_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer0 counter value
+ */
+#define MCPWM_TIMER0_VALUE    0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_M  (MCPWM_TIMER0_VALUE_V << MCPWM_TIMER0_VALUE_S)
+#define MCPWM_TIMER0_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER0_VALUE_S  0
+/** MCPWM_TIMER0_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer0 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER0_DIRECTION    (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (MCPWM_TIMER0_DIRECTION_V << MCPWM_TIMER0_DIRECTION_S)
+#define MCPWM_TIMER0_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER0_DIRECTION_S  16
+
+/** MCPWM_TIMER1_CFG0_REG register
+ *  PWM timer1 period and update method configuration register.
+ */
+#define MCPWM_TIMER1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x14)
+/** MCPWM_TIMER1_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configure the divisor of PT1_clk, takes effect when PWM timer1 stops and starts
+ *  agsin. period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)
+ */
+#define MCPWM_TIMER1_PRESCALE    0x000000FFU
+#define MCPWM_TIMER1_PRESCALE_M  (MCPWM_TIMER1_PRESCALE_V << MCPWM_TIMER1_PRESCALE_S)
+#define MCPWM_TIMER1_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER1_PRESCALE_S  0
+/** MCPWM_TIMER1_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer1
+ */
+#define MCPWM_TIMER1_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER1_PERIOD_M  (MCPWM_TIMER1_PERIOD_V << MCPWM_TIMER1_PERIOD_S)
+#define MCPWM_TIMER1_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER1_PERIOD_S  8
+/** MCPWM_TIMER1_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER1_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  (MCPWM_TIMER1_PERIOD_UPMETHOD_V << MCPWM_TIMER1_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER1_CFG1_REG register
+ *  PWM timer1 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x18)
+/** MCPWM_TIMER1_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1:
+ *  if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1
+ *  starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER1_START    0x00000007U
+#define MCPWM_TIMER1_START_M  (MCPWM_TIMER1_START_V << MCPWM_TIMER1_START_S)
+#define MCPWM_TIMER1_START_V  0x00000007U
+#define MCPWM_TIMER1_START_S  0
+/** MCPWM_TIMER1_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER1_MOD    0x00000003U
+#define MCPWM_TIMER1_MOD_M  (MCPWM_TIMER1_MOD_V << MCPWM_TIMER1_MOD_S)
+#define MCPWM_TIMER1_MOD_V  0x00000003U
+#define MCPWM_TIMER1_MOD_S  3
+
+/** MCPWM_TIMER1_SYNC_REG register
+ *  PWM timer1 sync function configuration register.
+ */
+#define MCPWM_TIMER1_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x1c)
+/** MCPWM_TIMER1_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER1_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (MCPWM_TIMER1_SYNCI_EN_V << MCPWM_TIMER1_SYNCI_EN_S)
+#define MCPWM_TIMER1_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+/** MCPWM_TIMER1_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER1_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (MCPWM_TIMER1_SYNC_SW_V << MCPWM_TIMER1_SYNC_SW_S)
+#define MCPWM_TIMER1_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/** MCPWM_TIMER1_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer1_sync_sw bit
+ */
+#define MCPWM_TIMER1_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_M  (MCPWM_TIMER1_SYNCO_SEL_V << MCPWM_TIMER1_SYNCO_SEL_S)
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/** MCPWM_TIMER1_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER1_PHASE    0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_M  (MCPWM_TIMER1_PHASE_V << MCPWM_TIMER1_PHASE_S)
+#define MCPWM_TIMER1_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER1_PHASE_S  4
+/** MCPWM_TIMER1_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer1's direction at the time sync event occurs when timer1 mode
+ *  is up-down mode: 0-increase,1-decrease
+ */
+#define MCPWM_TIMER1_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER1_PHASE_DIRECTION_M  (MCPWM_TIMER1_PHASE_DIRECTION_V << MCPWM_TIMER1_PHASE_DIRECTION_S)
+#define MCPWM_TIMER1_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER1_STATUS_REG register
+ *  PWM timer1 status register.
+ */
+#define MCPWM_TIMER1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x20)
+/** MCPWM_TIMER1_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer1 counter value
+ */
+#define MCPWM_TIMER1_VALUE    0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_M  (MCPWM_TIMER1_VALUE_V << MCPWM_TIMER1_VALUE_S)
+#define MCPWM_TIMER1_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER1_VALUE_S  0
+/** MCPWM_TIMER1_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer1 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER1_DIRECTION    (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (MCPWM_TIMER1_DIRECTION_V << MCPWM_TIMER1_DIRECTION_S)
+#define MCPWM_TIMER1_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER1_DIRECTION_S  16
+
+/** MCPWM_TIMER2_CFG0_REG register
+ *  PWM timer2 period and update method configuration register.
+ */
+#define MCPWM_TIMER2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x24)
+/** MCPWM_TIMER2_PRESCALE : R/W; bitpos: [7:0]; default: 0;
+ *  Configure the divisor of PT2_clk, takes effect when PWM timer2 stops and starts
+ *  agsin. period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)
+ */
+#define MCPWM_TIMER2_PRESCALE    0x000000FFU
+#define MCPWM_TIMER2_PRESCALE_M  (MCPWM_TIMER2_PRESCALE_V << MCPWM_TIMER2_PRESCALE_S)
+#define MCPWM_TIMER2_PRESCALE_V  0x000000FFU
+#define MCPWM_TIMER2_PRESCALE_S  0
+/** MCPWM_TIMER2_PERIOD : R/W; bitpos: [23:8]; default: 255;
+ *  period shadow register of PWM timer2
+ */
+#define MCPWM_TIMER2_PERIOD    0x0000FFFFU
+#define MCPWM_TIMER2_PERIOD_M  (MCPWM_TIMER2_PERIOD_V << MCPWM_TIMER2_PERIOD_S)
+#define MCPWM_TIMER2_PERIOD_V  0x0000FFFFU
+#define MCPWM_TIMER2_PERIOD_S  8
+/** MCPWM_TIMER2_PERIOD_UPMETHOD : R/W; bitpos: [25:24]; default: 0;
+ *  Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2:
+ *  sync, 3: TEZ | sync. TEZ here and below means timer equal zero event
+ */
+#define MCPWM_TIMER2_PERIOD_UPMETHOD    0x00000003U
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  (MCPWM_TIMER2_PERIOD_UPMETHOD_V << MCPWM_TIMER2_PERIOD_UPMETHOD_S)
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x00000003U
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
+
+/** MCPWM_TIMER2_CFG1_REG register
+ *  PWM timer2 working mode and start/stop control configuration register.
+ */
+#define MCPWM_TIMER2_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x28)
+/** MCPWM_TIMER2_START : R/W/SC; bitpos: [2:0]; default: 0;
+ *  PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1:
+ *  if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2
+ *  starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP
+ *  here and below means the event that happens when the timer equals to period
+ */
+#define MCPWM_TIMER2_START    0x00000007U
+#define MCPWM_TIMER2_START_M  (MCPWM_TIMER2_START_V << MCPWM_TIMER2_START_S)
+#define MCPWM_TIMER2_START_V  0x00000007U
+#define MCPWM_TIMER2_START_S  0
+/** MCPWM_TIMER2_MOD : R/W; bitpos: [4:3]; default: 0;
+ *  PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+ *  mode
+ */
+#define MCPWM_TIMER2_MOD    0x00000003U
+#define MCPWM_TIMER2_MOD_M  (MCPWM_TIMER2_MOD_V << MCPWM_TIMER2_MOD_S)
+#define MCPWM_TIMER2_MOD_V  0x00000003U
+#define MCPWM_TIMER2_MOD_S  3
+
+/** MCPWM_TIMER2_SYNC_REG register
+ *  PWM timer2 sync function configuration register.
+ */
+#define MCPWM_TIMER2_SYNC_REG(i) (DR_REG_MCPWM_BASE(i) + 0x2c)
+/** MCPWM_TIMER2_SYNCI_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, timer reloading with phase on sync input event is enabled.
+ */
+#define MCPWM_TIMER2_SYNCI_EN    (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (MCPWM_TIMER2_SYNCI_EN_V << MCPWM_TIMER2_SYNCI_EN_S)
+#define MCPWM_TIMER2_SYNCI_EN_V  0x00000001U
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+/** MCPWM_TIMER2_SYNC_SW : R/W; bitpos: [1]; default: 0;
+ *  Toggling this bit will trigger a software sync.
+ */
+#define MCPWM_TIMER2_SYNC_SW    (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (MCPWM_TIMER2_SYNC_SW_V << MCPWM_TIMER2_SYNC_SW_S)
+#define MCPWM_TIMER2_SYNC_SW_V  0x00000001U
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/** MCPWM_TIMER2_SYNCO_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+ *  generate when toggling the reg_timer0_sync_sw bit
+ */
+#define MCPWM_TIMER2_SYNCO_SEL    0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_M  (MCPWM_TIMER2_SYNCO_SEL_V << MCPWM_TIMER2_SYNCO_SEL_S)
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x00000003U
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/** MCPWM_TIMER2_PHASE : R/W; bitpos: [19:4]; default: 0;
+ *  phase for timer reload on sync event
+ */
+#define MCPWM_TIMER2_PHASE    0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_M  (MCPWM_TIMER2_PHASE_V << MCPWM_TIMER2_PHASE_S)
+#define MCPWM_TIMER2_PHASE_V  0x0000FFFFU
+#define MCPWM_TIMER2_PHASE_S  4
+/** MCPWM_TIMER2_PHASE_DIRECTION : R/W; bitpos: [20]; default: 0;
+ *  Configure the PWM timer2's direction at the time sync event occurs when timer2 mode
+ *  is up-down mode: 0-increase,1-decrease
+ */
+#define MCPWM_TIMER2_PHASE_DIRECTION    (BIT(20))
+#define MCPWM_TIMER2_PHASE_DIRECTION_M  (MCPWM_TIMER2_PHASE_DIRECTION_V << MCPWM_TIMER2_PHASE_DIRECTION_S)
+#define MCPWM_TIMER2_PHASE_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_PHASE_DIRECTION_S  20
+
+/** MCPWM_TIMER2_STATUS_REG register
+ *  PWM timer2 status register.
+ */
+#define MCPWM_TIMER2_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x30)
+/** MCPWM_TIMER2_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  current PWM timer2 counter value
+ */
+#define MCPWM_TIMER2_VALUE    0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_M  (MCPWM_TIMER2_VALUE_V << MCPWM_TIMER2_VALUE_S)
+#define MCPWM_TIMER2_VALUE_V  0x0000FFFFU
+#define MCPWM_TIMER2_VALUE_S  0
+/** MCPWM_TIMER2_DIRECTION : RO; bitpos: [16]; default: 0;
+ *  current PWM timer2 counter direction, 0: increment 1: decrement
+ */
+#define MCPWM_TIMER2_DIRECTION    (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (MCPWM_TIMER2_DIRECTION_V << MCPWM_TIMER2_DIRECTION_S)
+#define MCPWM_TIMER2_DIRECTION_V  0x00000001U
+#define MCPWM_TIMER2_DIRECTION_S  16
+
+/** MCPWM_TIMER_SYNCI_CFG_REG register
+ *  Synchronization input selection for three PWM timers.
+ */
+#define MCPWM_TIMER_SYNCI_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x34)
+/** MCPWM_TIMER0_SYNCISEL : R/W; bitpos: [2:0]; default: 0;
+ *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER0_SYNCISEL    0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_M  (MCPWM_TIMER0_SYNCISEL_V << MCPWM_TIMER0_SYNCISEL_S)
+#define MCPWM_TIMER0_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER0_SYNCISEL_S  0
+/** MCPWM_TIMER1_SYNCISEL : R/W; bitpos: [5:3]; default: 0;
+ *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER1_SYNCISEL    0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_M  (MCPWM_TIMER1_SYNCISEL_V << MCPWM_TIMER1_SYNCISEL_S)
+#define MCPWM_TIMER1_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/** MCPWM_TIMER2_SYNCISEL : R/W; bitpos: [8:6]; default: 0;
+ *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+ *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+ *  SYNC2 from GPIO matrix, other values: no sync input selected
+ */
+#define MCPWM_TIMER2_SYNCISEL    0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_M  (MCPWM_TIMER2_SYNCISEL_V << MCPWM_TIMER2_SYNCISEL_S)
+#define MCPWM_TIMER2_SYNCISEL_V  0x00000007U
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/** MCPWM_EXTERNAL_SYNCI0_INVERT : R/W; bitpos: [9]; default: 0;
+ *  invert SYNC0 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI0_INVERT    (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (MCPWM_EXTERNAL_SYNCI0_INVERT_V << MCPWM_EXTERNAL_SYNCI0_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/** MCPWM_EXTERNAL_SYNCI1_INVERT : R/W; bitpos: [10]; default: 0;
+ *  invert SYNC1 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI1_INVERT    (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (MCPWM_EXTERNAL_SYNCI1_INVERT_V << MCPWM_EXTERNAL_SYNCI1_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/** MCPWM_EXTERNAL_SYNCI2_INVERT : R/W; bitpos: [11]; default: 0;
+ *  invert SYNC2 from GPIO matrix
+ */
+#define MCPWM_EXTERNAL_SYNCI2_INVERT    (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (MCPWM_EXTERNAL_SYNCI2_INVERT_V << MCPWM_EXTERNAL_SYNCI2_INVERT_S)
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x00000001U
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+
+/** MCPWM_OPERATOR_TIMERSEL_REG register
+ *  Select specific timer for PWM operators.
+ */
+#define MCPWM_OPERATOR_TIMERSEL_REG(i) (DR_REG_MCPWM_BASE(i) + 0x38)
+/** MCPWM_OPERATOR0_TIMERSEL : R/W; bitpos: [1:0]; default: 0;
+ *  Select which PWM timer is the timing reference for PWM operator0, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR0_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_M  (MCPWM_OPERATOR0_TIMERSEL_V << MCPWM_OPERATOR0_TIMERSEL_S)
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+/** MCPWM_OPERATOR1_TIMERSEL : R/W; bitpos: [3:2]; default: 0;
+ *  Select which PWM timer is the timing reference for PWM operator1, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR1_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_M  (MCPWM_OPERATOR1_TIMERSEL_V << MCPWM_OPERATOR1_TIMERSEL_S)
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/** MCPWM_OPERATOR2_TIMERSEL : R/W; bitpos: [5:4]; default: 0;
+ *  Select which PWM timer is the timing reference for PWM operator2, 0: timer0, 1:
+ *  timer1, 2: timer2
+ */
+#define MCPWM_OPERATOR2_TIMERSEL    0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_M  (MCPWM_OPERATOR2_TIMERSEL_V << MCPWM_OPERATOR2_TIMERSEL_S)
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x00000003U
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+
+/** MCPWM_GEN0_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN0_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x3c)
+/** MCPWM_GEN0_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 0 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_GEN0_A_UPMETHOD    0x0000000FU
+#define MCPWM_GEN0_A_UPMETHOD_M  (MCPWM_GEN0_A_UPMETHOD_V << MCPWM_GEN0_A_UPMETHOD_S)
+#define MCPWM_GEN0_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN0_A_UPMETHOD_S  0
+/** MCPWM_GEN0_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 0 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_GEN0_B_UPMETHOD    0x0000000FU
+#define MCPWM_GEN0_B_UPMETHOD_M  (MCPWM_GEN0_B_UPMETHOD_V << MCPWM_GEN0_B_UPMETHOD_S)
+#define MCPWM_GEN0_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN0_B_UPMETHOD_S  4
+/** MCPWM_GEN0_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_GEN0_A_SHDW_FULL    (BIT(8))
+#define MCPWM_GEN0_A_SHDW_FULL_M  (MCPWM_GEN0_A_SHDW_FULL_V << MCPWM_GEN0_A_SHDW_FULL_S)
+#define MCPWM_GEN0_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_GEN0_A_SHDW_FULL_S  8
+/** MCPWM_GEN0_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_GEN0_B_SHDW_FULL    (BIT(9))
+#define MCPWM_GEN0_B_SHDW_FULL_M  (MCPWM_GEN0_B_SHDW_FULL_V << MCPWM_GEN0_B_SHDW_FULL_S)
+#define MCPWM_GEN0_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_GEN0_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN0_TSTMP_A_REG register
+ *  PWM generator 0 shadow register for timer stamp A.
+ */
+#define MCPWM_GEN0_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x40)
+/** MCPWM_GEN0_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 0 time stamp A's shadow register
+ */
+#define MCPWM_GEN0_A    0x0000FFFFU
+#define MCPWM_GEN0_A_M  (MCPWM_GEN0_A_V << MCPWM_GEN0_A_S)
+#define MCPWM_GEN0_A_V  0x0000FFFFU
+#define MCPWM_GEN0_A_S  0
+
+/** MCPWM_GEN0_TSTMP_B_REG register
+ *  PWM generator 0 shadow register for timer stamp B.
+ */
+#define MCPWM_GEN0_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x44)
+/** MCPWM_GEN0_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 0 time stamp B's shadow register
+ */
+#define MCPWM_GEN0_B    0x0000FFFFU
+#define MCPWM_GEN0_B_M  (MCPWM_GEN0_B_V << MCPWM_GEN0_B_S)
+#define MCPWM_GEN0_B_V  0x0000FFFFU
+#define MCPWM_GEN0_B_S  0
+
+/** MCPWM_GEN0_CFG0_REG register
+ *  PWM generator 0  event T0 and T1 handling
+ */
+#define MCPWM_GEN0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x48)
+/** MCPWM_GEN0_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 0's active register of configuration. When all bits
+ *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+ *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
+ */
+#define MCPWM_GEN0_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_M  (MCPWM_GEN0_CFG_UPMETHOD_V << MCPWM_GEN0_CFG_UPMETHOD_S)
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+/** MCPWM_GEN0_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 0 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN0_T0_SEL    0x00000007U
+#define MCPWM_GEN0_T0_SEL_M  (MCPWM_GEN0_T0_SEL_V << MCPWM_GEN0_T0_SEL_S)
+#define MCPWM_GEN0_T0_SEL_V  0x00000007U
+#define MCPWM_GEN0_T0_SEL_S  4
+/** MCPWM_GEN0_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 0 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN0_T1_SEL    0x00000007U
+#define MCPWM_GEN0_T1_SEL_M  (MCPWM_GEN0_T1_SEL_V << MCPWM_GEN0_T1_SEL_S)
+#define MCPWM_GEN0_T1_SEL_V  0x00000007U
+#define MCPWM_GEN0_T1_SEL_S  7
+
+/** MCPWM_GEN0_FORCE_REG register
+ *  Permissives to force PWM0A and PWM0B outputs by software
+ */
+#define MCPWM_GEN0_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0x4c)
+/** MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator0. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN0_CNTUFORCE_UPMETHOD_V << MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN0_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN0_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  (MCPWM_GEN0_A_CNTUFORCE_MODE_V << MCPWM_GEN0_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN0_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN0_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  (MCPWM_GEN0_B_CNTUFORCE_MODE_V << MCPWM_GEN0_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN0_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM0A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN0_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (MCPWM_GEN0_A_NCIFORCE_V << MCPWM_GEN0_A_NCIFORCE_S)
+#define MCPWM_GEN0_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/** MCPWM_GEN0_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN0_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  (MCPWM_GEN0_A_NCIFORCE_MODE_V << MCPWM_GEN0_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN0_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM0B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN0_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (MCPWM_GEN0_B_NCIFORCE_V << MCPWM_GEN0_B_NCIFORCE_S)
+#define MCPWM_GEN0_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/** MCPWM_GEN0_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN0_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  (MCPWM_GEN0_B_NCIFORCE_MODE_V << MCPWM_GEN0_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN0_A_REG register
+ *  Actions triggered by events on PWM0A
+ */
+#define MCPWM_GEN0_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x50)
+/** MCPWM_GEN0_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM0A triggered by event TEZ when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_UTEZ    0x00000003U
+#define MCPWM_GEN0_A_UTEZ_M  (MCPWM_GEN0_A_UTEZ_V << MCPWM_GEN0_A_UTEZ_S)
+#define MCPWM_GEN0_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_UTEZ_S  0
+/** MCPWM_GEN0_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM0A triggered by event TEP when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_UTEP    0x00000003U
+#define MCPWM_GEN0_A_UTEP_M  (MCPWM_GEN0_A_UTEP_V << MCPWM_GEN0_A_UTEP_S)
+#define MCPWM_GEN0_A_UTEP_V  0x00000003U
+#define MCPWM_GEN0_A_UTEP_S  2
+/** MCPWM_GEN0_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM0A triggered by event TEA when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_UTEA    0x00000003U
+#define MCPWM_GEN0_A_UTEA_M  (MCPWM_GEN0_A_UTEA_V << MCPWM_GEN0_A_UTEA_S)
+#define MCPWM_GEN0_A_UTEA_V  0x00000003U
+#define MCPWM_GEN0_A_UTEA_S  4
+/** MCPWM_GEN0_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM0A triggered by event TEB when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_UTEB    0x00000003U
+#define MCPWM_GEN0_A_UTEB_M  (MCPWM_GEN0_A_UTEB_V << MCPWM_GEN0_A_UTEB_S)
+#define MCPWM_GEN0_A_UTEB_V  0x00000003U
+#define MCPWM_GEN0_A_UTEB_S  6
+/** MCPWM_GEN0_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM0A triggered by event_t0 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_UT0    0x00000003U
+#define MCPWM_GEN0_A_UT0_M  (MCPWM_GEN0_A_UT0_V << MCPWM_GEN0_A_UT0_S)
+#define MCPWM_GEN0_A_UT0_V  0x00000003U
+#define MCPWM_GEN0_A_UT0_S  8
+/** MCPWM_GEN0_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM0A triggered by event_t1 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_UT1    0x00000003U
+#define MCPWM_GEN0_A_UT1_M  (MCPWM_GEN0_A_UT1_V << MCPWM_GEN0_A_UT1_S)
+#define MCPWM_GEN0_A_UT1_V  0x00000003U
+#define MCPWM_GEN0_A_UT1_S  10
+/** MCPWM_GEN0_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM0A triggered by event TEZ when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_DTEZ    0x00000003U
+#define MCPWM_GEN0_A_DTEZ_M  (MCPWM_GEN0_A_DTEZ_V << MCPWM_GEN0_A_DTEZ_S)
+#define MCPWM_GEN0_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_A_DTEZ_S  12
+/** MCPWM_GEN0_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM0A triggered by event TEP when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_DTEP    0x00000003U
+#define MCPWM_GEN0_A_DTEP_M  (MCPWM_GEN0_A_DTEP_V << MCPWM_GEN0_A_DTEP_S)
+#define MCPWM_GEN0_A_DTEP_V  0x00000003U
+#define MCPWM_GEN0_A_DTEP_S  14
+/** MCPWM_GEN0_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM0A triggered by event TEA when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_DTEA    0x00000003U
+#define MCPWM_GEN0_A_DTEA_M  (MCPWM_GEN0_A_DTEA_V << MCPWM_GEN0_A_DTEA_S)
+#define MCPWM_GEN0_A_DTEA_V  0x00000003U
+#define MCPWM_GEN0_A_DTEA_S  16
+/** MCPWM_GEN0_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM0A triggered by event TEB when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_DTEB    0x00000003U
+#define MCPWM_GEN0_A_DTEB_M  (MCPWM_GEN0_A_DTEB_V << MCPWM_GEN0_A_DTEB_S)
+#define MCPWM_GEN0_A_DTEB_V  0x00000003U
+#define MCPWM_GEN0_A_DTEB_S  18
+/** MCPWM_GEN0_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM0A triggered by event_t0 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_DT0    0x00000003U
+#define MCPWM_GEN0_A_DT0_M  (MCPWM_GEN0_A_DT0_V << MCPWM_GEN0_A_DT0_S)
+#define MCPWM_GEN0_A_DT0_V  0x00000003U
+#define MCPWM_GEN0_A_DT0_S  20
+/** MCPWM_GEN0_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_A_DT1    0x00000003U
+#define MCPWM_GEN0_A_DT1_M  (MCPWM_GEN0_A_DT1_V << MCPWM_GEN0_A_DT1_S)
+#define MCPWM_GEN0_A_DT1_V  0x00000003U
+#define MCPWM_GEN0_A_DT1_S  22
+
+/** MCPWM_GEN0_B_REG register
+ *  Actions triggered by events on PWM0B
+ */
+#define MCPWM_GEN0_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x54)
+/** MCPWM_GEN0_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM0B triggered by event TEZ when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_UTEZ    0x00000003U
+#define MCPWM_GEN0_B_UTEZ_M  (MCPWM_GEN0_B_UTEZ_V << MCPWM_GEN0_B_UTEZ_S)
+#define MCPWM_GEN0_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_UTEZ_S  0
+/** MCPWM_GEN0_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM0B triggered by event TEP when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_UTEP    0x00000003U
+#define MCPWM_GEN0_B_UTEP_M  (MCPWM_GEN0_B_UTEP_V << MCPWM_GEN0_B_UTEP_S)
+#define MCPWM_GEN0_B_UTEP_V  0x00000003U
+#define MCPWM_GEN0_B_UTEP_S  2
+/** MCPWM_GEN0_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM0B triggered by event TEA when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_UTEA    0x00000003U
+#define MCPWM_GEN0_B_UTEA_M  (MCPWM_GEN0_B_UTEA_V << MCPWM_GEN0_B_UTEA_S)
+#define MCPWM_GEN0_B_UTEA_V  0x00000003U
+#define MCPWM_GEN0_B_UTEA_S  4
+/** MCPWM_GEN0_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM0B triggered by event TEB when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_UTEB    0x00000003U
+#define MCPWM_GEN0_B_UTEB_M  (MCPWM_GEN0_B_UTEB_V << MCPWM_GEN0_B_UTEB_S)
+#define MCPWM_GEN0_B_UTEB_V  0x00000003U
+#define MCPWM_GEN0_B_UTEB_S  6
+/** MCPWM_GEN0_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM0B triggered by event_t0 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_UT0    0x00000003U
+#define MCPWM_GEN0_B_UT0_M  (MCPWM_GEN0_B_UT0_V << MCPWM_GEN0_B_UT0_S)
+#define MCPWM_GEN0_B_UT0_V  0x00000003U
+#define MCPWM_GEN0_B_UT0_S  8
+/** MCPWM_GEN0_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM0B triggered by event_t1 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_UT1    0x00000003U
+#define MCPWM_GEN0_B_UT1_M  (MCPWM_GEN0_B_UT1_V << MCPWM_GEN0_B_UT1_S)
+#define MCPWM_GEN0_B_UT1_V  0x00000003U
+#define MCPWM_GEN0_B_UT1_S  10
+/** MCPWM_GEN0_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM0B triggered by event TEZ when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_DTEZ    0x00000003U
+#define MCPWM_GEN0_B_DTEZ_M  (MCPWM_GEN0_B_DTEZ_V << MCPWM_GEN0_B_DTEZ_S)
+#define MCPWM_GEN0_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN0_B_DTEZ_S  12
+/** MCPWM_GEN0_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM0B triggered by event TEP when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_DTEP    0x00000003U
+#define MCPWM_GEN0_B_DTEP_M  (MCPWM_GEN0_B_DTEP_V << MCPWM_GEN0_B_DTEP_S)
+#define MCPWM_GEN0_B_DTEP_V  0x00000003U
+#define MCPWM_GEN0_B_DTEP_S  14
+/** MCPWM_GEN0_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM0B triggered by event TEA when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_DTEA    0x00000003U
+#define MCPWM_GEN0_B_DTEA_M  (MCPWM_GEN0_B_DTEA_V << MCPWM_GEN0_B_DTEA_S)
+#define MCPWM_GEN0_B_DTEA_V  0x00000003U
+#define MCPWM_GEN0_B_DTEA_S  16
+/** MCPWM_GEN0_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM0B triggered by event TEB when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_DTEB    0x00000003U
+#define MCPWM_GEN0_B_DTEB_M  (MCPWM_GEN0_B_DTEB_V << MCPWM_GEN0_B_DTEB_S)
+#define MCPWM_GEN0_B_DTEB_V  0x00000003U
+#define MCPWM_GEN0_B_DTEB_S  18
+/** MCPWM_GEN0_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM0B triggered by event_t0 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_DT0    0x00000003U
+#define MCPWM_GEN0_B_DT0_M  (MCPWM_GEN0_B_DT0_V << MCPWM_GEN0_B_DT0_S)
+#define MCPWM_GEN0_B_DT0_V  0x00000003U
+#define MCPWM_GEN0_B_DT0_S  20
+/** MCPWM_GEN0_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN0_B_DT1    0x00000003U
+#define MCPWM_GEN0_B_DT1_M  (MCPWM_GEN0_B_DT1_V << MCPWM_GEN0_B_DT1_S)
+#define MCPWM_GEN0_B_DT1_V  0x00000003U
+#define MCPWM_GEN0_B_DT1_S  22
+
+/** MCPWM_DT0_CFG_REG register
+ *  PWM generator 0 dead time type selection and configuration
+ */
+#define MCPWM_DT0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x58)
+/** MCPWM_DT0_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DT0_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DT0_FED_UPMETHOD_M  (MCPWM_DT0_FED_UPMETHOD_V << MCPWM_DT0_FED_UPMETHOD_S)
+#define MCPWM_DT0_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DT0_FED_UPMETHOD_S  0
+/** MCPWM_DT0_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DT0_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DT0_RED_UPMETHOD_M  (MCPWM_DT0_RED_UPMETHOD_V << MCPWM_DT0_RED_UPMETHOD_S)
+#define MCPWM_DT0_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DT0_RED_UPMETHOD_S  4
+/** MCPWM_DT0_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DT0_DEB_MODE    (BIT(8))
+#define MCPWM_DT0_DEB_MODE_M  (MCPWM_DT0_DEB_MODE_V << MCPWM_DT0_DEB_MODE_S)
+#define MCPWM_DT0_DEB_MODE_V  0x00000001U
+#define MCPWM_DT0_DEB_MODE_S  8
+/** MCPWM_DT0_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DT0_A_OUTSWAP    (BIT(9))
+#define MCPWM_DT0_A_OUTSWAP_M  (MCPWM_DT0_A_OUTSWAP_V << MCPWM_DT0_A_OUTSWAP_S)
+#define MCPWM_DT0_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DT0_A_OUTSWAP_S  9
+/** MCPWM_DT0_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DT0_B_OUTSWAP    (BIT(10))
+#define MCPWM_DT0_B_OUTSWAP_M  (MCPWM_DT0_B_OUTSWAP_V << MCPWM_DT0_B_OUTSWAP_S)
+#define MCPWM_DT0_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DT0_B_OUTSWAP_S  10
+/** MCPWM_DT0_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DT0_RED_INSEL    (BIT(11))
+#define MCPWM_DT0_RED_INSEL_M  (MCPWM_DT0_RED_INSEL_V << MCPWM_DT0_RED_INSEL_S)
+#define MCPWM_DT0_RED_INSEL_V  0x00000001U
+#define MCPWM_DT0_RED_INSEL_S  11
+/** MCPWM_DT0_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DT0_FED_INSEL    (BIT(12))
+#define MCPWM_DT0_FED_INSEL_M  (MCPWM_DT0_FED_INSEL_V << MCPWM_DT0_FED_INSEL_S)
+#define MCPWM_DT0_FED_INSEL_V  0x00000001U
+#define MCPWM_DT0_FED_INSEL_S  12
+/** MCPWM_DT0_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DT0_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DT0_RED_OUTINVERT_M  (MCPWM_DT0_RED_OUTINVERT_V << MCPWM_DT0_RED_OUTINVERT_S)
+#define MCPWM_DT0_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DT0_RED_OUTINVERT_S  13
+/** MCPWM_DT0_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DT0_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DT0_FED_OUTINVERT_M  (MCPWM_DT0_FED_OUTINVERT_V << MCPWM_DT0_FED_OUTINVERT_S)
+#define MCPWM_DT0_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DT0_FED_OUTINVERT_S  14
+/** MCPWM_DT0_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DT0_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DT0_A_OUTBYPASS_M  (MCPWM_DT0_A_OUTBYPASS_V << MCPWM_DT0_A_OUTBYPASS_S)
+#define MCPWM_DT0_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DT0_A_OUTBYPASS_S  15
+/** MCPWM_DT0_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DT0_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DT0_B_OUTBYPASS_M  (MCPWM_DT0_B_OUTBYPASS_V << MCPWM_DT0_B_OUTBYPASS_S)
+#define MCPWM_DT0_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DT0_B_OUTBYPASS_S  16
+/** MCPWM_DT0_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DT0_CLK_SEL    (BIT(17))
+#define MCPWM_DT0_CLK_SEL_M  (MCPWM_DT0_CLK_SEL_V << MCPWM_DT0_CLK_SEL_S)
+#define MCPWM_DT0_CLK_SEL_V  0x00000001U
+#define MCPWM_DT0_CLK_SEL_S  17
+
+/** MCPWM_DT0_FED_CFG_REG register
+ *  PWM generator 0 shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT0_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x5c)
+/** MCPWM_DT0_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DT0_FED    0x0000FFFFU
+#define MCPWM_DT0_FED_M  (MCPWM_DT0_FED_V << MCPWM_DT0_FED_S)
+#define MCPWM_DT0_FED_V  0x0000FFFFU
+#define MCPWM_DT0_FED_S  0
+
+/** MCPWM_DT0_RED_CFG_REG register
+ *  PWM generator 0 shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT0_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x60)
+/** MCPWM_DT0_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DT0_RED    0x0000FFFFU
+#define MCPWM_DT0_RED_M  (MCPWM_DT0_RED_V << MCPWM_DT0_RED_S)
+#define MCPWM_DT0_RED_V  0x0000FFFFU
+#define MCPWM_DT0_RED_S  0
+
+/** MCPWM_CARRIER0_CFG_REG register
+ *  PWM generator 0 carrier enable and configuration
+ */
+#define MCPWM_CARRIER0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x64)
+/** MCPWM_CARRIER0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier0 function is enabled. When cleared, carrier0 is bypassed
+ */
+#define MCPWM_CARRIER0_EN    (BIT(0))
+#define MCPWM_CARRIER0_EN_M  (MCPWM_CARRIER0_EN_V << MCPWM_CARRIER0_EN_S)
+#define MCPWM_CARRIER0_EN_V  0x00000001U
+#define MCPWM_CARRIER0_EN_S  0
+/** MCPWM_CARRIER0_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CARRIER0_PRESCALE    0x0000000FU
+#define MCPWM_CARRIER0_PRESCALE_M  (MCPWM_CARRIER0_PRESCALE_V << MCPWM_CARRIER0_PRESCALE_S)
+#define MCPWM_CARRIER0_PRESCALE_V  0x0000000FU
+#define MCPWM_CARRIER0_PRESCALE_S  1
+/** MCPWM_CARRIER0_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CARRIER0_DUTY    0x00000007U
+#define MCPWM_CARRIER0_DUTY_M  (MCPWM_CARRIER0_DUTY_V << MCPWM_CARRIER0_DUTY_S)
+#define MCPWM_CARRIER0_DUTY_V  0x00000007U
+#define MCPWM_CARRIER0_DUTY_S  5
+/** MCPWM_CARRIER0_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CARRIER0_OSHTWTH    0x0000000FU
+#define MCPWM_CARRIER0_OSHTWTH_M  (MCPWM_CARRIER0_OSHTWTH_V << MCPWM_CARRIER0_OSHTWTH_S)
+#define MCPWM_CARRIER0_OSHTWTH_V  0x0000000FU
+#define MCPWM_CARRIER0_OSHTWTH_S  8
+/** MCPWM_CARRIER0_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM0A and PWM0B for this submodule
+ */
+#define MCPWM_CARRIER0_OUT_INVERT    (BIT(12))
+#define MCPWM_CARRIER0_OUT_INVERT_M  (MCPWM_CARRIER0_OUT_INVERT_V << MCPWM_CARRIER0_OUT_INVERT_S)
+#define MCPWM_CARRIER0_OUT_INVERT_V  0x00000001U
+#define MCPWM_CARRIER0_OUT_INVERT_S  12
+/** MCPWM_CARRIER0_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM0A and PWM0B for this submodule
+ */
+#define MCPWM_CARRIER0_IN_INVERT    (BIT(13))
+#define MCPWM_CARRIER0_IN_INVERT_M  (MCPWM_CARRIER0_IN_INVERT_V << MCPWM_CARRIER0_IN_INVERT_S)
+#define MCPWM_CARRIER0_IN_INVERT_V  0x00000001U
+#define MCPWM_CARRIER0_IN_INVERT_S  13
+
+/** MCPWM_FH0_CFG0_REG register
+ *  Actions on PWM0A and PWM0B trip events
+ */
+#define MCPWM_FH0_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x68)
+/** MCPWM_FH0_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH0_SW_CBC    (BIT(0))
+#define MCPWM_FH0_SW_CBC_M  (MCPWM_FH0_SW_CBC_V << MCPWM_FH0_SW_CBC_S)
+#define MCPWM_FH0_SW_CBC_V  0x00000001U
+#define MCPWM_FH0_SW_CBC_S  0
+/** MCPWM_FH0_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH0_F2_CBC    (BIT(1))
+#define MCPWM_FH0_F2_CBC_M  (MCPWM_FH0_F2_CBC_V << MCPWM_FH0_F2_CBC_S)
+#define MCPWM_FH0_F2_CBC_V  0x00000001U
+#define MCPWM_FH0_F2_CBC_S  1
+/** MCPWM_FH0_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH0_F1_CBC    (BIT(2))
+#define MCPWM_FH0_F1_CBC_M  (MCPWM_FH0_F1_CBC_V << MCPWM_FH0_F1_CBC_S)
+#define MCPWM_FH0_F1_CBC_V  0x00000001U
+#define MCPWM_FH0_F1_CBC_S  2
+/** MCPWM_FH0_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH0_F0_CBC    (BIT(3))
+#define MCPWM_FH0_F0_CBC_M  (MCPWM_FH0_F0_CBC_V << MCPWM_FH0_F0_CBC_S)
+#define MCPWM_FH0_F0_CBC_V  0x00000001U
+#define MCPWM_FH0_F0_CBC_S  3
+/** MCPWM_FH0_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH0_SW_OST    (BIT(4))
+#define MCPWM_FH0_SW_OST_M  (MCPWM_FH0_SW_OST_V << MCPWM_FH0_SW_OST_S)
+#define MCPWM_FH0_SW_OST_V  0x00000001U
+#define MCPWM_FH0_SW_OST_S  4
+/** MCPWM_FH0_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  fault_event2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH0_F2_OST    (BIT(5))
+#define MCPWM_FH0_F2_OST_M  (MCPWM_FH0_F2_OST_V << MCPWM_FH0_F2_OST_S)
+#define MCPWM_FH0_F2_OST_V  0x00000001U
+#define MCPWM_FH0_F2_OST_S  5
+/** MCPWM_FH0_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  fault_event1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH0_F1_OST    (BIT(6))
+#define MCPWM_FH0_F1_OST_M  (MCPWM_FH0_F1_OST_V << MCPWM_FH0_F1_OST_S)
+#define MCPWM_FH0_F1_OST_V  0x00000001U
+#define MCPWM_FH0_F1_OST_S  6
+/** MCPWM_FH0_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  fault_event0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH0_F0_OST    (BIT(7))
+#define MCPWM_FH0_F0_OST_M  (MCPWM_FH0_F0_OST_V << MCPWM_FH0_F0_OST_S)
+#define MCPWM_FH0_F0_OST_V  0x00000001U
+#define MCPWM_FH0_F0_OST_S  7
+/** MCPWM_FH0_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH0_A_CBC_D    0x00000003U
+#define MCPWM_FH0_A_CBC_D_M  (MCPWM_FH0_A_CBC_D_V << MCPWM_FH0_A_CBC_D_S)
+#define MCPWM_FH0_A_CBC_D_V  0x00000003U
+#define MCPWM_FH0_A_CBC_D_S  8
+/** MCPWM_FH0_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH0_A_CBC_U    0x00000003U
+#define MCPWM_FH0_A_CBC_U_M  (MCPWM_FH0_A_CBC_U_V << MCPWM_FH0_A_CBC_U_S)
+#define MCPWM_FH0_A_CBC_U_V  0x00000003U
+#define MCPWM_FH0_A_CBC_U_S  10
+/** MCPWM_FH0_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH0_A_OST_D    0x00000003U
+#define MCPWM_FH0_A_OST_D_M  (MCPWM_FH0_A_OST_D_V << MCPWM_FH0_A_OST_D_S)
+#define MCPWM_FH0_A_OST_D_V  0x00000003U
+#define MCPWM_FH0_A_OST_D_S  12
+/** MCPWM_FH0_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH0_A_OST_U    0x00000003U
+#define MCPWM_FH0_A_OST_U_M  (MCPWM_FH0_A_OST_U_V << MCPWM_FH0_A_OST_U_S)
+#define MCPWM_FH0_A_OST_U_V  0x00000003U
+#define MCPWM_FH0_A_OST_U_S  14
+/** MCPWM_FH0_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH0_B_CBC_D    0x00000003U
+#define MCPWM_FH0_B_CBC_D_M  (MCPWM_FH0_B_CBC_D_V << MCPWM_FH0_B_CBC_D_S)
+#define MCPWM_FH0_B_CBC_D_V  0x00000003U
+#define MCPWM_FH0_B_CBC_D_S  16
+/** MCPWM_FH0_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+ *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH0_B_CBC_U    0x00000003U
+#define MCPWM_FH0_B_CBC_U_M  (MCPWM_FH0_B_CBC_U_V << MCPWM_FH0_B_CBC_U_S)
+#define MCPWM_FH0_B_CBC_U_V  0x00000003U
+#define MCPWM_FH0_B_CBC_U_S  18
+/** MCPWM_FH0_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH0_B_OST_D    0x00000003U
+#define MCPWM_FH0_B_OST_D_M  (MCPWM_FH0_B_OST_D_V << MCPWM_FH0_B_OST_D_S)
+#define MCPWM_FH0_B_OST_D_V  0x00000003U
+#define MCPWM_FH0_B_OST_D_S  20
+/** MCPWM_FH0_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH0_B_OST_U    0x00000003U
+#define MCPWM_FH0_B_OST_U_M  (MCPWM_FH0_B_OST_U_V << MCPWM_FH0_B_OST_U_S)
+#define MCPWM_FH0_B_OST_U_V  0x00000003U
+#define MCPWM_FH0_B_OST_U_S  22
+
+/** MCPWM_FH0_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH0_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x6c)
+/** MCPWM_FH0_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_FH0_CLR_OST    (BIT(0))
+#define MCPWM_FH0_CLR_OST_M  (MCPWM_FH0_CLR_OST_V << MCPWM_FH0_CLR_OST_S)
+#define MCPWM_FH0_CLR_OST_V  0x00000001U
+#define MCPWM_FH0_CLR_OST_S  0
+/** MCPWM_FH0_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when
+ *  bit0 and bit1 both set to 1: refresh at TEP/TEZ
+ */
+#define MCPWM_FH0_CBCPULSE    0x00000003U
+#define MCPWM_FH0_CBCPULSE_M  (MCPWM_FH0_CBCPULSE_V << MCPWM_FH0_CBCPULSE_S)
+#define MCPWM_FH0_CBCPULSE_V  0x00000003U
+#define MCPWM_FH0_CBCPULSE_S  1
+/** MCPWM_FH0_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_FH0_FORCE_CBC    (BIT(3))
+#define MCPWM_FH0_FORCE_CBC_M  (MCPWM_FH0_FORCE_CBC_V << MCPWM_FH0_FORCE_CBC_S)
+#define MCPWM_FH0_FORCE_CBC_V  0x00000001U
+#define MCPWM_FH0_FORCE_CBC_S  3
+/** MCPWM_FH0_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_FH0_FORCE_OST    (BIT(4))
+#define MCPWM_FH0_FORCE_OST_M  (MCPWM_FH0_FORCE_OST_V << MCPWM_FH0_FORCE_OST_S)
+#define MCPWM_FH0_FORCE_OST_V  0x00000001U
+#define MCPWM_FH0_FORCE_OST_S  4
+
+/** MCPWM_FH0_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH0_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x70)
+/** MCPWM_FH0_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_FH0_CBC_ON    (BIT(0))
+#define MCPWM_FH0_CBC_ON_M  (MCPWM_FH0_CBC_ON_V << MCPWM_FH0_CBC_ON_S)
+#define MCPWM_FH0_CBC_ON_V  0x00000001U
+#define MCPWM_FH0_CBC_ON_S  0
+/** MCPWM_FH0_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_FH0_OST_ON    (BIT(1))
+#define MCPWM_FH0_OST_ON_M  (MCPWM_FH0_OST_ON_V << MCPWM_FH0_OST_ON_S)
+#define MCPWM_FH0_OST_ON_V  0x00000001U
+#define MCPWM_FH0_OST_ON_S  1
+
+/** MCPWM_GEN1_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN1_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x74)
+/** MCPWM_GEN1_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 1 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_GEN1_A_UPMETHOD    0x0000000FU
+#define MCPWM_GEN1_A_UPMETHOD_M  (MCPWM_GEN1_A_UPMETHOD_V << MCPWM_GEN1_A_UPMETHOD_S)
+#define MCPWM_GEN1_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN1_A_UPMETHOD_S  0
+/** MCPWM_GEN1_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 1 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_GEN1_B_UPMETHOD    0x0000000FU
+#define MCPWM_GEN1_B_UPMETHOD_M  (MCPWM_GEN1_B_UPMETHOD_V << MCPWM_GEN1_B_UPMETHOD_S)
+#define MCPWM_GEN1_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN1_B_UPMETHOD_S  4
+/** MCPWM_GEN1_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_GEN1_A_SHDW_FULL    (BIT(8))
+#define MCPWM_GEN1_A_SHDW_FULL_M  (MCPWM_GEN1_A_SHDW_FULL_V << MCPWM_GEN1_A_SHDW_FULL_S)
+#define MCPWM_GEN1_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_GEN1_A_SHDW_FULL_S  8
+/** MCPWM_GEN1_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_GEN1_B_SHDW_FULL    (BIT(9))
+#define MCPWM_GEN1_B_SHDW_FULL_M  (MCPWM_GEN1_B_SHDW_FULL_V << MCPWM_GEN1_B_SHDW_FULL_S)
+#define MCPWM_GEN1_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_GEN1_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN1_TSTMP_A_REG register
+ *  PWM generator 1 shadow register for timer stamp A.
+ */
+#define MCPWM_GEN1_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x78)
+/** MCPWM_GEN1_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 1 time stamp A's shadow register
+ */
+#define MCPWM_GEN1_A    0x0000FFFFU
+#define MCPWM_GEN1_A_M  (MCPWM_GEN1_A_V << MCPWM_GEN1_A_S)
+#define MCPWM_GEN1_A_V  0x0000FFFFU
+#define MCPWM_GEN1_A_S  0
+
+/** MCPWM_GEN1_TSTMP_B_REG register
+ *  PWM generator 1 shadow register for timer stamp B.
+ */
+#define MCPWM_GEN1_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x7c)
+/** MCPWM_GEN1_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 1 time stamp B's shadow register
+ */
+#define MCPWM_GEN1_B    0x0000FFFFU
+#define MCPWM_GEN1_B_M  (MCPWM_GEN1_B_V << MCPWM_GEN1_B_S)
+#define MCPWM_GEN1_B_V  0x0000FFFFU
+#define MCPWM_GEN1_B_S  0
+
+/** MCPWM_GEN1_CFG0_REG register
+ *  PWM generator 1 event T0 and T1 handling
+ */
+#define MCPWM_GEN1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0x80)
+/** MCPWM_GEN1_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 1's active register of configuration. When all bits
+ *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+ *  1:sync;when bit3 is set to 1:disable the update.
+ */
+#define MCPWM_GEN1_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_M  (MCPWM_GEN1_CFG_UPMETHOD_V << MCPWM_GEN1_CFG_UPMETHOD_S)
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+/** MCPWM_GEN1_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 1 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN1_T0_SEL    0x00000007U
+#define MCPWM_GEN1_T0_SEL_M  (MCPWM_GEN1_T0_SEL_V << MCPWM_GEN1_T0_SEL_S)
+#define MCPWM_GEN1_T0_SEL_V  0x00000007U
+#define MCPWM_GEN1_T0_SEL_S  4
+/** MCPWM_GEN1_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 1 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN1_T1_SEL    0x00000007U
+#define MCPWM_GEN1_T1_SEL_M  (MCPWM_GEN1_T1_SEL_V << MCPWM_GEN1_T1_SEL_S)
+#define MCPWM_GEN1_T1_SEL_V  0x00000007U
+#define MCPWM_GEN1_T1_SEL_S  7
+
+/** MCPWM_GEN1_FORCE_REG register
+ *  Permissives to force PWM1A and PWM1B outputs by software
+ */
+#define MCPWM_GEN1_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0x84)
+/** MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator 1. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN1_CNTUFORCE_UPMETHOD_V << MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN1_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN1_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  (MCPWM_GEN1_A_CNTUFORCE_MODE_V << MCPWM_GEN1_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN1_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN1_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  (MCPWM_GEN1_B_CNTUFORCE_MODE_V << MCPWM_GEN1_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN1_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM1A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN1_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (MCPWM_GEN1_A_NCIFORCE_V << MCPWM_GEN1_A_NCIFORCE_S)
+#define MCPWM_GEN1_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/** MCPWM_GEN1_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN1_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  (MCPWM_GEN1_A_NCIFORCE_MODE_V << MCPWM_GEN1_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN1_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM1B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN1_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (MCPWM_GEN1_B_NCIFORCE_V << MCPWM_GEN1_B_NCIFORCE_S)
+#define MCPWM_GEN1_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/** MCPWM_GEN1_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN1_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  (MCPWM_GEN1_B_NCIFORCE_MODE_V << MCPWM_GEN1_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN1_A_REG register
+ *  Actions triggered by events on PWM1A
+ */
+#define MCPWM_GEN1_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0x88)
+/** MCPWM_GEN1_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM1A triggered by event TEZ when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_UTEZ    0x00000003U
+#define MCPWM_GEN1_A_UTEZ_M  (MCPWM_GEN1_A_UTEZ_V << MCPWM_GEN1_A_UTEZ_S)
+#define MCPWM_GEN1_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_UTEZ_S  0
+/** MCPWM_GEN1_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM1A triggered by event TEP when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_UTEP    0x00000003U
+#define MCPWM_GEN1_A_UTEP_M  (MCPWM_GEN1_A_UTEP_V << MCPWM_GEN1_A_UTEP_S)
+#define MCPWM_GEN1_A_UTEP_V  0x00000003U
+#define MCPWM_GEN1_A_UTEP_S  2
+/** MCPWM_GEN1_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM1A triggered by event TEA when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_UTEA    0x00000003U
+#define MCPWM_GEN1_A_UTEA_M  (MCPWM_GEN1_A_UTEA_V << MCPWM_GEN1_A_UTEA_S)
+#define MCPWM_GEN1_A_UTEA_V  0x00000003U
+#define MCPWM_GEN1_A_UTEA_S  4
+/** MCPWM_GEN1_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM1A triggered by event TEB when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_UTEB    0x00000003U
+#define MCPWM_GEN1_A_UTEB_M  (MCPWM_GEN1_A_UTEB_V << MCPWM_GEN1_A_UTEB_S)
+#define MCPWM_GEN1_A_UTEB_V  0x00000003U
+#define MCPWM_GEN1_A_UTEB_S  6
+/** MCPWM_GEN1_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM1A triggered by event_t0 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_UT0    0x00000003U
+#define MCPWM_GEN1_A_UT0_M  (MCPWM_GEN1_A_UT0_V << MCPWM_GEN1_A_UT0_S)
+#define MCPWM_GEN1_A_UT0_V  0x00000003U
+#define MCPWM_GEN1_A_UT0_S  8
+/** MCPWM_GEN1_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM1A triggered by event_t1 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_UT1    0x00000003U
+#define MCPWM_GEN1_A_UT1_M  (MCPWM_GEN1_A_UT1_V << MCPWM_GEN1_A_UT1_S)
+#define MCPWM_GEN1_A_UT1_V  0x00000003U
+#define MCPWM_GEN1_A_UT1_S  10
+/** MCPWM_GEN1_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM1A triggered by event TEZ when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_DTEZ    0x00000003U
+#define MCPWM_GEN1_A_DTEZ_M  (MCPWM_GEN1_A_DTEZ_V << MCPWM_GEN1_A_DTEZ_S)
+#define MCPWM_GEN1_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_A_DTEZ_S  12
+/** MCPWM_GEN1_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM1A triggered by event TEP when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_DTEP    0x00000003U
+#define MCPWM_GEN1_A_DTEP_M  (MCPWM_GEN1_A_DTEP_V << MCPWM_GEN1_A_DTEP_S)
+#define MCPWM_GEN1_A_DTEP_V  0x00000003U
+#define MCPWM_GEN1_A_DTEP_S  14
+/** MCPWM_GEN1_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM1A triggered by event TEA when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_DTEA    0x00000003U
+#define MCPWM_GEN1_A_DTEA_M  (MCPWM_GEN1_A_DTEA_V << MCPWM_GEN1_A_DTEA_S)
+#define MCPWM_GEN1_A_DTEA_V  0x00000003U
+#define MCPWM_GEN1_A_DTEA_S  16
+/** MCPWM_GEN1_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM1A triggered by event TEB when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_DTEB    0x00000003U
+#define MCPWM_GEN1_A_DTEB_M  (MCPWM_GEN1_A_DTEB_V << MCPWM_GEN1_A_DTEB_S)
+#define MCPWM_GEN1_A_DTEB_V  0x00000003U
+#define MCPWM_GEN1_A_DTEB_S  18
+/** MCPWM_GEN1_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM1A triggered by event_t0 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_DT0    0x00000003U
+#define MCPWM_GEN1_A_DT0_M  (MCPWM_GEN1_A_DT0_V << MCPWM_GEN1_A_DT0_S)
+#define MCPWM_GEN1_A_DT0_V  0x00000003U
+#define MCPWM_GEN1_A_DT0_S  20
+/** MCPWM_GEN1_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_A_DT1    0x00000003U
+#define MCPWM_GEN1_A_DT1_M  (MCPWM_GEN1_A_DT1_V << MCPWM_GEN1_A_DT1_S)
+#define MCPWM_GEN1_A_DT1_V  0x00000003U
+#define MCPWM_GEN1_A_DT1_S  22
+
+/** MCPWM_GEN1_B_REG register
+ *  Actions triggered by events on PWM1B
+ */
+#define MCPWM_GEN1_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0x8c)
+/** MCPWM_GEN1_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM1B triggered by event TEZ when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_UTEZ    0x00000003U
+#define MCPWM_GEN1_B_UTEZ_M  (MCPWM_GEN1_B_UTEZ_V << MCPWM_GEN1_B_UTEZ_S)
+#define MCPWM_GEN1_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_UTEZ_S  0
+/** MCPWM_GEN1_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM1B triggered by event TEP when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_UTEP    0x00000003U
+#define MCPWM_GEN1_B_UTEP_M  (MCPWM_GEN1_B_UTEP_V << MCPWM_GEN1_B_UTEP_S)
+#define MCPWM_GEN1_B_UTEP_V  0x00000003U
+#define MCPWM_GEN1_B_UTEP_S  2
+/** MCPWM_GEN1_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM1B triggered by event TEA when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_UTEA    0x00000003U
+#define MCPWM_GEN1_B_UTEA_M  (MCPWM_GEN1_B_UTEA_V << MCPWM_GEN1_B_UTEA_S)
+#define MCPWM_GEN1_B_UTEA_V  0x00000003U
+#define MCPWM_GEN1_B_UTEA_S  4
+/** MCPWM_GEN1_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM1B triggered by event TEB when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_UTEB    0x00000003U
+#define MCPWM_GEN1_B_UTEB_M  (MCPWM_GEN1_B_UTEB_V << MCPWM_GEN1_B_UTEB_S)
+#define MCPWM_GEN1_B_UTEB_V  0x00000003U
+#define MCPWM_GEN1_B_UTEB_S  6
+/** MCPWM_GEN1_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM1B triggered by event_t0 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_UT0    0x00000003U
+#define MCPWM_GEN1_B_UT0_M  (MCPWM_GEN1_B_UT0_V << MCPWM_GEN1_B_UT0_S)
+#define MCPWM_GEN1_B_UT0_V  0x00000003U
+#define MCPWM_GEN1_B_UT0_S  8
+/** MCPWM_GEN1_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM1B triggered by event_t1 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_UT1    0x00000003U
+#define MCPWM_GEN1_B_UT1_M  (MCPWM_GEN1_B_UT1_V << MCPWM_GEN1_B_UT1_S)
+#define MCPWM_GEN1_B_UT1_V  0x00000003U
+#define MCPWM_GEN1_B_UT1_S  10
+/** MCPWM_GEN1_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM1B triggered by event TEZ when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_DTEZ    0x00000003U
+#define MCPWM_GEN1_B_DTEZ_M  (MCPWM_GEN1_B_DTEZ_V << MCPWM_GEN1_B_DTEZ_S)
+#define MCPWM_GEN1_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN1_B_DTEZ_S  12
+/** MCPWM_GEN1_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM1B triggered by event TEP when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_DTEP    0x00000003U
+#define MCPWM_GEN1_B_DTEP_M  (MCPWM_GEN1_B_DTEP_V << MCPWM_GEN1_B_DTEP_S)
+#define MCPWM_GEN1_B_DTEP_V  0x00000003U
+#define MCPWM_GEN1_B_DTEP_S  14
+/** MCPWM_GEN1_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM1B triggered by event TEA when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_DTEA    0x00000003U
+#define MCPWM_GEN1_B_DTEA_M  (MCPWM_GEN1_B_DTEA_V << MCPWM_GEN1_B_DTEA_S)
+#define MCPWM_GEN1_B_DTEA_V  0x00000003U
+#define MCPWM_GEN1_B_DTEA_S  16
+/** MCPWM_GEN1_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM1B triggered by event TEB when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_DTEB    0x00000003U
+#define MCPWM_GEN1_B_DTEB_M  (MCPWM_GEN1_B_DTEB_V << MCPWM_GEN1_B_DTEB_S)
+#define MCPWM_GEN1_B_DTEB_V  0x00000003U
+#define MCPWM_GEN1_B_DTEB_S  18
+/** MCPWM_GEN1_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM1B triggered by event_t0 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_DT0    0x00000003U
+#define MCPWM_GEN1_B_DT0_M  (MCPWM_GEN1_B_DT0_V << MCPWM_GEN1_B_DT0_S)
+#define MCPWM_GEN1_B_DT0_V  0x00000003U
+#define MCPWM_GEN1_B_DT0_S  20
+/** MCPWM_GEN1_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN1_B_DT1    0x00000003U
+#define MCPWM_GEN1_B_DT1_M  (MCPWM_GEN1_B_DT1_V << MCPWM_GEN1_B_DT1_S)
+#define MCPWM_GEN1_B_DT1_V  0x00000003U
+#define MCPWM_GEN1_B_DT1_S  22
+
+/** MCPWM_DT1_CFG_REG register
+ *  PWM generator 1 dead time type selection and configuration
+ */
+#define MCPWM_DT1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x90)
+/** MCPWM_DT1_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (falling edge delay) active register. 0: immediate, when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DT1_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DT1_FED_UPMETHOD_M  (MCPWM_DT1_FED_UPMETHOD_V << MCPWM_DT1_FED_UPMETHOD_S)
+#define MCPWM_DT1_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DT1_FED_UPMETHOD_S  0
+/** MCPWM_DT1_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register. 0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DT1_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DT1_RED_UPMETHOD_M  (MCPWM_DT1_RED_UPMETHOD_V << MCPWM_DT1_RED_UPMETHOD_S)
+#define MCPWM_DT1_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DT1_RED_UPMETHOD_S  4
+/** MCPWM_DT1_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DT1_DEB_MODE    (BIT(8))
+#define MCPWM_DT1_DEB_MODE_M  (MCPWM_DT1_DEB_MODE_V << MCPWM_DT1_DEB_MODE_S)
+#define MCPWM_DT1_DEB_MODE_V  0x00000001U
+#define MCPWM_DT1_DEB_MODE_S  8
+/** MCPWM_DT1_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DT1_A_OUTSWAP    (BIT(9))
+#define MCPWM_DT1_A_OUTSWAP_M  (MCPWM_DT1_A_OUTSWAP_V << MCPWM_DT1_A_OUTSWAP_S)
+#define MCPWM_DT1_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DT1_A_OUTSWAP_S  9
+/** MCPWM_DT1_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DT1_B_OUTSWAP    (BIT(10))
+#define MCPWM_DT1_B_OUTSWAP_M  (MCPWM_DT1_B_OUTSWAP_V << MCPWM_DT1_B_OUTSWAP_S)
+#define MCPWM_DT1_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DT1_B_OUTSWAP_S  10
+/** MCPWM_DT1_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DT1_RED_INSEL    (BIT(11))
+#define MCPWM_DT1_RED_INSEL_M  (MCPWM_DT1_RED_INSEL_V << MCPWM_DT1_RED_INSEL_S)
+#define MCPWM_DT1_RED_INSEL_V  0x00000001U
+#define MCPWM_DT1_RED_INSEL_S  11
+/** MCPWM_DT1_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DT1_FED_INSEL    (BIT(12))
+#define MCPWM_DT1_FED_INSEL_M  (MCPWM_DT1_FED_INSEL_V << MCPWM_DT1_FED_INSEL_S)
+#define MCPWM_DT1_FED_INSEL_V  0x00000001U
+#define MCPWM_DT1_FED_INSEL_S  12
+/** MCPWM_DT1_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DT1_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DT1_RED_OUTINVERT_M  (MCPWM_DT1_RED_OUTINVERT_V << MCPWM_DT1_RED_OUTINVERT_S)
+#define MCPWM_DT1_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DT1_RED_OUTINVERT_S  13
+/** MCPWM_DT1_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DT1_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DT1_FED_OUTINVERT_M  (MCPWM_DT1_FED_OUTINVERT_V << MCPWM_DT1_FED_OUTINVERT_S)
+#define MCPWM_DT1_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DT1_FED_OUTINVERT_S  14
+/** MCPWM_DT1_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DT1_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DT1_A_OUTBYPASS_M  (MCPWM_DT1_A_OUTBYPASS_V << MCPWM_DT1_A_OUTBYPASS_S)
+#define MCPWM_DT1_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DT1_A_OUTBYPASS_S  15
+/** MCPWM_DT1_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DT1_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DT1_B_OUTBYPASS_M  (MCPWM_DT1_B_OUTBYPASS_V << MCPWM_DT1_B_OUTBYPASS_S)
+#define MCPWM_DT1_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DT1_B_OUTBYPASS_S  16
+/** MCPWM_DT1_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DT1_CLK_SEL    (BIT(17))
+#define MCPWM_DT1_CLK_SEL_M  (MCPWM_DT1_CLK_SEL_V << MCPWM_DT1_CLK_SEL_S)
+#define MCPWM_DT1_CLK_SEL_V  0x00000001U
+#define MCPWM_DT1_CLK_SEL_S  17
+
+/** MCPWM_DT1_FED_CFG_REG register
+ *  PWM generator 1 shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT1_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x94)
+/** MCPWM_DT1_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DT1_FED    0x0000FFFFU
+#define MCPWM_DT1_FED_M  (MCPWM_DT1_FED_V << MCPWM_DT1_FED_S)
+#define MCPWM_DT1_FED_V  0x0000FFFFU
+#define MCPWM_DT1_FED_S  0
+
+/** MCPWM_DT1_RED_CFG_REG register
+ *  PWM generator 1 shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT1_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x98)
+/** MCPWM_DT1_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DT1_RED    0x0000FFFFU
+#define MCPWM_DT1_RED_M  (MCPWM_DT1_RED_V << MCPWM_DT1_RED_S)
+#define MCPWM_DT1_RED_V  0x0000FFFFU
+#define MCPWM_DT1_RED_S  0
+
+/** MCPWM_CARRIER1_CFG_REG register
+ *  PWM generator 1 carrier enable and configuration
+ */
+#define MCPWM_CARRIER1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x9c)
+/** MCPWM_CARRIER1_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier1 function is enabled. When cleared, carrier1 is bypassed
+ */
+#define MCPWM_CARRIER1_EN    (BIT(0))
+#define MCPWM_CARRIER1_EN_M  (MCPWM_CARRIER1_EN_V << MCPWM_CARRIER1_EN_S)
+#define MCPWM_CARRIER1_EN_V  0x00000001U
+#define MCPWM_CARRIER1_EN_S  0
+/** MCPWM_CARRIER1_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CARRIER1_PRESCALE    0x0000000FU
+#define MCPWM_CARRIER1_PRESCALE_M  (MCPWM_CARRIER1_PRESCALE_V << MCPWM_CARRIER1_PRESCALE_S)
+#define MCPWM_CARRIER1_PRESCALE_V  0x0000000FU
+#define MCPWM_CARRIER1_PRESCALE_S  1
+/** MCPWM_CARRIER1_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CARRIER1_DUTY    0x00000007U
+#define MCPWM_CARRIER1_DUTY_M  (MCPWM_CARRIER1_DUTY_V << MCPWM_CARRIER1_DUTY_S)
+#define MCPWM_CARRIER1_DUTY_V  0x00000007U
+#define MCPWM_CARRIER1_DUTY_S  5
+/** MCPWM_CARRIER1_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CARRIER1_OSHTWTH    0x0000000FU
+#define MCPWM_CARRIER1_OSHTWTH_M  (MCPWM_CARRIER1_OSHTWTH_V << MCPWM_CARRIER1_OSHTWTH_S)
+#define MCPWM_CARRIER1_OSHTWTH_V  0x0000000FU
+#define MCPWM_CARRIER1_OSHTWTH_S  8
+/** MCPWM_CARRIER1_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM1A and PWM1B for this submodule
+ */
+#define MCPWM_CARRIER1_OUT_INVERT    (BIT(12))
+#define MCPWM_CARRIER1_OUT_INVERT_M  (MCPWM_CARRIER1_OUT_INVERT_V << MCPWM_CARRIER1_OUT_INVERT_S)
+#define MCPWM_CARRIER1_OUT_INVERT_V  0x00000001U
+#define MCPWM_CARRIER1_OUT_INVERT_S  12
+/** MCPWM_CARRIER1_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM1A and PWM1B for this submodule
+ */
+#define MCPWM_CARRIER1_IN_INVERT    (BIT(13))
+#define MCPWM_CARRIER1_IN_INVERT_M  (MCPWM_CARRIER1_IN_INVERT_V << MCPWM_CARRIER1_IN_INVERT_S)
+#define MCPWM_CARRIER1_IN_INVERT_V  0x00000001U
+#define MCPWM_CARRIER1_IN_INVERT_S  13
+
+/** MCPWM_FH1_CFG0_REG register
+ *  Actions on PWM1A and PWM1B trip events
+ */
+#define MCPWM_FH1_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa0)
+/** MCPWM_FH1_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH1_SW_CBC    (BIT(0))
+#define MCPWM_FH1_SW_CBC_M  (MCPWM_FH1_SW_CBC_V << MCPWM_FH1_SW_CBC_S)
+#define MCPWM_FH1_SW_CBC_V  0x00000001U
+#define MCPWM_FH1_SW_CBC_S  0
+/** MCPWM_FH1_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH1_F2_CBC    (BIT(1))
+#define MCPWM_FH1_F2_CBC_M  (MCPWM_FH1_F2_CBC_V << MCPWM_FH1_F2_CBC_S)
+#define MCPWM_FH1_F2_CBC_V  0x00000001U
+#define MCPWM_FH1_F2_CBC_S  1
+/** MCPWM_FH1_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH1_F1_CBC    (BIT(2))
+#define MCPWM_FH1_F1_CBC_M  (MCPWM_FH1_F1_CBC_V << MCPWM_FH1_F1_CBC_S)
+#define MCPWM_FH1_F1_CBC_V  0x00000001U
+#define MCPWM_FH1_F1_CBC_S  2
+/** MCPWM_FH1_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH1_F0_CBC    (BIT(3))
+#define MCPWM_FH1_F0_CBC_M  (MCPWM_FH1_F0_CBC_V << MCPWM_FH1_F0_CBC_S)
+#define MCPWM_FH1_F0_CBC_V  0x00000001U
+#define MCPWM_FH1_F0_CBC_S  3
+/** MCPWM_FH1_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH1_SW_OST    (BIT(4))
+#define MCPWM_FH1_SW_OST_M  (MCPWM_FH1_SW_OST_V << MCPWM_FH1_SW_OST_S)
+#define MCPWM_FH1_SW_OST_V  0x00000001U
+#define MCPWM_FH1_SW_OST_S  4
+/** MCPWM_FH1_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  fault_event2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH1_F2_OST    (BIT(5))
+#define MCPWM_FH1_F2_OST_M  (MCPWM_FH1_F2_OST_V << MCPWM_FH1_F2_OST_S)
+#define MCPWM_FH1_F2_OST_V  0x00000001U
+#define MCPWM_FH1_F2_OST_S  5
+/** MCPWM_FH1_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  fault_event1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH1_F1_OST    (BIT(6))
+#define MCPWM_FH1_F1_OST_M  (MCPWM_FH1_F1_OST_V << MCPWM_FH1_F1_OST_S)
+#define MCPWM_FH1_F1_OST_V  0x00000001U
+#define MCPWM_FH1_F1_OST_S  6
+/** MCPWM_FH1_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  fault_event0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH1_F0_OST    (BIT(7))
+#define MCPWM_FH1_F0_OST_M  (MCPWM_FH1_F0_OST_V << MCPWM_FH1_F0_OST_S)
+#define MCPWM_FH1_F0_OST_V  0x00000001U
+#define MCPWM_FH1_F0_OST_S  7
+/** MCPWM_FH1_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH1_A_CBC_D    0x00000003U
+#define MCPWM_FH1_A_CBC_D_M  (MCPWM_FH1_A_CBC_D_V << MCPWM_FH1_A_CBC_D_S)
+#define MCPWM_FH1_A_CBC_D_V  0x00000003U
+#define MCPWM_FH1_A_CBC_D_S  8
+/** MCPWM_FH1_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH1_A_CBC_U    0x00000003U
+#define MCPWM_FH1_A_CBC_U_M  (MCPWM_FH1_A_CBC_U_V << MCPWM_FH1_A_CBC_U_S)
+#define MCPWM_FH1_A_CBC_U_V  0x00000003U
+#define MCPWM_FH1_A_CBC_U_S  10
+/** MCPWM_FH1_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0:
+ *  do nothing,1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH1_A_OST_D    0x00000003U
+#define MCPWM_FH1_A_OST_D_M  (MCPWM_FH1_A_OST_D_V << MCPWM_FH1_A_OST_D_S)
+#define MCPWM_FH1_A_OST_D_V  0x00000003U
+#define MCPWM_FH1_A_OST_D_S  12
+/** MCPWM_FH1_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH1_A_OST_U    0x00000003U
+#define MCPWM_FH1_A_OST_U_M  (MCPWM_FH1_A_OST_U_V << MCPWM_FH1_A_OST_U_S)
+#define MCPWM_FH1_A_OST_U_V  0x00000003U
+#define MCPWM_FH1_A_OST_U_S  14
+/** MCPWM_FH1_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH1_B_CBC_D    0x00000003U
+#define MCPWM_FH1_B_CBC_D_M  (MCPWM_FH1_B_CBC_D_V << MCPWM_FH1_B_CBC_D_S)
+#define MCPWM_FH1_B_CBC_D_V  0x00000003U
+#define MCPWM_FH1_B_CBC_D_S  16
+/** MCPWM_FH1_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH1_B_CBC_U    0x00000003U
+#define MCPWM_FH1_B_CBC_U_M  (MCPWM_FH1_B_CBC_U_V << MCPWM_FH1_B_CBC_U_S)
+#define MCPWM_FH1_B_CBC_U_V  0x00000003U
+#define MCPWM_FH1_B_CBC_U_S  18
+/** MCPWM_FH1_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH1_B_OST_D    0x00000003U
+#define MCPWM_FH1_B_OST_D_M  (MCPWM_FH1_B_OST_D_V << MCPWM_FH1_B_OST_D_S)
+#define MCPWM_FH1_B_OST_D_V  0x00000003U
+#define MCPWM_FH1_B_OST_D_S  20
+/** MCPWM_FH1_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH1_B_OST_U    0x00000003U
+#define MCPWM_FH1_B_OST_U_M  (MCPWM_FH1_B_OST_U_V << MCPWM_FH1_B_OST_U_S)
+#define MCPWM_FH1_B_OST_U_V  0x00000003U
+#define MCPWM_FH1_B_OST_U_S  22
+
+/** MCPWM_FH1_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH1_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa4)
+/** MCPWM_FH1_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_FH1_CLR_OST    (BIT(0))
+#define MCPWM_FH1_CLR_OST_M  (MCPWM_FH1_CLR_OST_V << MCPWM_FH1_CLR_OST_S)
+#define MCPWM_FH1_CLR_OST_V  0x00000001U
+#define MCPWM_FH1_CLR_OST_S  0
+/** MCPWM_FH1_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP
+ */
+#define MCPWM_FH1_CBCPULSE    0x00000003U
+#define MCPWM_FH1_CBCPULSE_M  (MCPWM_FH1_CBCPULSE_V << MCPWM_FH1_CBCPULSE_S)
+#define MCPWM_FH1_CBCPULSE_V  0x00000003U
+#define MCPWM_FH1_CBCPULSE_S  1
+/** MCPWM_FH1_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_FH1_FORCE_CBC    (BIT(3))
+#define MCPWM_FH1_FORCE_CBC_M  (MCPWM_FH1_FORCE_CBC_V << MCPWM_FH1_FORCE_CBC_S)
+#define MCPWM_FH1_FORCE_CBC_V  0x00000001U
+#define MCPWM_FH1_FORCE_CBC_S  3
+/** MCPWM_FH1_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_FH1_FORCE_OST    (BIT(4))
+#define MCPWM_FH1_FORCE_OST_M  (MCPWM_FH1_FORCE_OST_V << MCPWM_FH1_FORCE_OST_S)
+#define MCPWM_FH1_FORCE_OST_V  0x00000001U
+#define MCPWM_FH1_FORCE_OST_S  4
+
+/** MCPWM_FH1_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH1_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0xa8)
+/** MCPWM_FH1_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_FH1_CBC_ON    (BIT(0))
+#define MCPWM_FH1_CBC_ON_M  (MCPWM_FH1_CBC_ON_V << MCPWM_FH1_CBC_ON_S)
+#define MCPWM_FH1_CBC_ON_V  0x00000001U
+#define MCPWM_FH1_CBC_ON_S  0
+/** MCPWM_FH1_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_FH1_OST_ON    (BIT(1))
+#define MCPWM_FH1_OST_ON_M  (MCPWM_FH1_OST_ON_V << MCPWM_FH1_OST_ON_S)
+#define MCPWM_FH1_OST_ON_V  0x00000001U
+#define MCPWM_FH1_OST_ON_S  1
+
+/** MCPWM_GEN2_STMP_CFG_REG register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+#define MCPWM_GEN2_STMP_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xac)
+/** MCPWM_GEN2_A_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 2 time stamp A's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_GEN2_A_UPMETHOD    0x0000000FU
+#define MCPWM_GEN2_A_UPMETHOD_M  (MCPWM_GEN2_A_UPMETHOD_V << MCPWM_GEN2_A_UPMETHOD_S)
+#define MCPWM_GEN2_A_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN2_A_UPMETHOD_S  0
+/** MCPWM_GEN2_B_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for PWM generator 2 time stamp B's active register. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+ *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+ */
+#define MCPWM_GEN2_B_UPMETHOD    0x0000000FU
+#define MCPWM_GEN2_B_UPMETHOD_M  (MCPWM_GEN2_B_UPMETHOD_V << MCPWM_GEN2_B_UPMETHOD_S)
+#define MCPWM_GEN2_B_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN2_B_UPMETHOD_S  4
+/** MCPWM_GEN2_A_SHDW_FULL : R/W/WTC/SC; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is
+ *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_GEN2_A_SHDW_FULL    (BIT(8))
+#define MCPWM_GEN2_A_SHDW_FULL_M  (MCPWM_GEN2_A_SHDW_FULL_V << MCPWM_GEN2_A_SHDW_FULL_S)
+#define MCPWM_GEN2_A_SHDW_FULL_V  0x00000001U
+#define MCPWM_GEN2_A_SHDW_FULL_S  8
+/** MCPWM_GEN2_B_SHDW_FULL : R/W/WTC/SC; bitpos: [9]; default: 0;
+ *  Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is
+ *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+ *  has been updated with shadow register latest value
+ */
+#define MCPWM_GEN2_B_SHDW_FULL    (BIT(9))
+#define MCPWM_GEN2_B_SHDW_FULL_M  (MCPWM_GEN2_B_SHDW_FULL_V << MCPWM_GEN2_B_SHDW_FULL_S)
+#define MCPWM_GEN2_B_SHDW_FULL_V  0x00000001U
+#define MCPWM_GEN2_B_SHDW_FULL_S  9
+
+/** MCPWM_GEN2_TSTMP_A_REG register
+ *  PWM generator 2 shadow register for timer stamp A.
+ */
+#define MCPWM_GEN2_TSTMP_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb0)
+/** MCPWM_GEN2_A : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 2 time stamp A's shadow register
+ */
+#define MCPWM_GEN2_A    0x0000FFFFU
+#define MCPWM_GEN2_A_M  (MCPWM_GEN2_A_V << MCPWM_GEN2_A_S)
+#define MCPWM_GEN2_A_V  0x0000FFFFU
+#define MCPWM_GEN2_A_S  0
+
+/** MCPWM_GEN2_TSTMP_B_REG register
+ *  PWM generator 2 shadow register for timer stamp A.
+ */
+#define MCPWM_GEN2_TSTMP_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb4)
+/** MCPWM_GEN2_B : R/W; bitpos: [15:0]; default: 0;
+ *  PWM generator 2 time stamp B's shadow register
+ */
+#define MCPWM_GEN2_B    0x0000FFFFU
+#define MCPWM_GEN2_B_M  (MCPWM_GEN2_B_V << MCPWM_GEN2_B_S)
+#define MCPWM_GEN2_B_V  0x0000FFFFU
+#define MCPWM_GEN2_B_S  0
+
+/** MCPWM_GEN2_CFG0_REG register
+ *  PWM generator 2 event T0 and T1 handling
+ */
+#define MCPWM_GEN2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xb8)
+/** MCPWM_GEN2_CFG_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for PWM generator 2's active register of configuration. 0:
+ *  immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is
+ *  set to 1:disable the update.
+ */
+#define MCPWM_GEN2_CFG_UPMETHOD    0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_M  (MCPWM_GEN2_CFG_UPMETHOD_V << MCPWM_GEN2_CFG_UPMETHOD_S)
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0x0000000FU
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+/** MCPWM_GEN2_T0_SEL : R/W; bitpos: [6:4]; default: 0;
+ *  Source selection for PWM generator 2 event_t0, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN2_T0_SEL    0x00000007U
+#define MCPWM_GEN2_T0_SEL_M  (MCPWM_GEN2_T0_SEL_V << MCPWM_GEN2_T0_SEL_S)
+#define MCPWM_GEN2_T0_SEL_V  0x00000007U
+#define MCPWM_GEN2_T0_SEL_S  4
+/** MCPWM_GEN2_T1_SEL : R/W; bitpos: [9:7]; default: 0;
+ *  Source selection for PWM generator 2 event_t1, take effect immediately, 0:
+ *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+ */
+#define MCPWM_GEN2_T1_SEL    0x00000007U
+#define MCPWM_GEN2_T1_SEL_M  (MCPWM_GEN2_T1_SEL_V << MCPWM_GEN2_T1_SEL_S)
+#define MCPWM_GEN2_T1_SEL_V  0x00000007U
+#define MCPWM_GEN2_T1_SEL_S  7
+
+/** MCPWM_GEN2_FORCE_REG register
+ *  Permissives to force PWM2A and PWM2B outputs by software
+ */
+#define MCPWM_GEN2_FORCE_REG(i) (DR_REG_MCPWM_BASE(i) + 0xbc)
+/** MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W; bitpos: [5:0]; default: 32;
+ *  Updating method for continuous software force of PWM generator 2. When all bits are
+ *  set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when
+ *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+ *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+ *  generated when the timer's value equals to that of register A/B.)
+ */
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD    0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  (MCPWM_GEN2_CNTUFORCE_UPMETHOD_V << MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x0000003FU
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+/** MCPWM_GEN2_A_CNTUFORCE_MODE : R/W; bitpos: [7:6]; default: 0;
+ *  Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN2_A_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  (MCPWM_GEN2_A_CNTUFORCE_MODE_V << MCPWM_GEN2_A_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/** MCPWM_GEN2_B_CNTUFORCE_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled
+ */
+#define MCPWM_GEN2_B_CNTUFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  (MCPWM_GEN2_B_CNTUFORCE_MODE_V << MCPWM_GEN2_B_CNTUFORCE_MODE_S)
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/** MCPWM_GEN2_A_NCIFORCE : R/W; bitpos: [10]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM2A, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN2_A_NCIFORCE    (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (MCPWM_GEN2_A_NCIFORCE_V << MCPWM_GEN2_A_NCIFORCE_S)
+#define MCPWM_GEN2_A_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/** MCPWM_GEN2_A_NCIFORCE_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN2_A_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  (MCPWM_GEN2_A_NCIFORCE_MODE_V << MCPWM_GEN2_A_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/** MCPWM_GEN2_B_NCIFORCE : R/W; bitpos: [13]; default: 0;
+ *  Trigger of non-continuous immediate software-force event for PWM2B, a toggle will
+ *  trigger a force event.
+ */
+#define MCPWM_GEN2_B_NCIFORCE    (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (MCPWM_GEN2_B_NCIFORCE_V << MCPWM_GEN2_B_NCIFORCE_S)
+#define MCPWM_GEN2_B_NCIFORCE_V  0x00000001U
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/** MCPWM_GEN2_B_NCIFORCE_MODE : R/W; bitpos: [15:14]; default: 0;
+ *  non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2:
+ *  high, 3: disabled
+ */
+#define MCPWM_GEN2_B_NCIFORCE_MODE    0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  (MCPWM_GEN2_B_NCIFORCE_MODE_V << MCPWM_GEN2_B_NCIFORCE_MODE_S)
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x00000003U
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+
+/** MCPWM_GEN2_A_REG register
+ *  Actions triggered by events on PWM2A
+ */
+#define MCPWM_GEN2_A_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc0)
+/** MCPWM_GEN2_A_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM2A triggered by event TEZ when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_UTEZ    0x00000003U
+#define MCPWM_GEN2_A_UTEZ_M  (MCPWM_GEN2_A_UTEZ_V << MCPWM_GEN2_A_UTEZ_S)
+#define MCPWM_GEN2_A_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_UTEZ_S  0
+/** MCPWM_GEN2_A_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM2A triggered by event TEP when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_UTEP    0x00000003U
+#define MCPWM_GEN2_A_UTEP_M  (MCPWM_GEN2_A_UTEP_V << MCPWM_GEN2_A_UTEP_S)
+#define MCPWM_GEN2_A_UTEP_V  0x00000003U
+#define MCPWM_GEN2_A_UTEP_S  2
+/** MCPWM_GEN2_A_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM2A triggered by event TEA when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_UTEA    0x00000003U
+#define MCPWM_GEN2_A_UTEA_M  (MCPWM_GEN2_A_UTEA_V << MCPWM_GEN2_A_UTEA_S)
+#define MCPWM_GEN2_A_UTEA_V  0x00000003U
+#define MCPWM_GEN2_A_UTEA_S  4
+/** MCPWM_GEN2_A_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM2A triggered by event TEB when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_UTEB    0x00000003U
+#define MCPWM_GEN2_A_UTEB_M  (MCPWM_GEN2_A_UTEB_V << MCPWM_GEN2_A_UTEB_S)
+#define MCPWM_GEN2_A_UTEB_V  0x00000003U
+#define MCPWM_GEN2_A_UTEB_S  6
+/** MCPWM_GEN2_A_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM2A triggered by event_t0 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_UT0    0x00000003U
+#define MCPWM_GEN2_A_UT0_M  (MCPWM_GEN2_A_UT0_V << MCPWM_GEN2_A_UT0_S)
+#define MCPWM_GEN2_A_UT0_V  0x00000003U
+#define MCPWM_GEN2_A_UT0_S  8
+/** MCPWM_GEN2_A_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM2A triggered by event_t1 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_UT1    0x00000003U
+#define MCPWM_GEN2_A_UT1_M  (MCPWM_GEN2_A_UT1_V << MCPWM_GEN2_A_UT1_S)
+#define MCPWM_GEN2_A_UT1_V  0x00000003U
+#define MCPWM_GEN2_A_UT1_S  10
+/** MCPWM_GEN2_A_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM2A triggered by event TEZ when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_DTEZ    0x00000003U
+#define MCPWM_GEN2_A_DTEZ_M  (MCPWM_GEN2_A_DTEZ_V << MCPWM_GEN2_A_DTEZ_S)
+#define MCPWM_GEN2_A_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_A_DTEZ_S  12
+/** MCPWM_GEN2_A_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM2A triggered by event TEP when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_DTEP    0x00000003U
+#define MCPWM_GEN2_A_DTEP_M  (MCPWM_GEN2_A_DTEP_V << MCPWM_GEN2_A_DTEP_S)
+#define MCPWM_GEN2_A_DTEP_V  0x00000003U
+#define MCPWM_GEN2_A_DTEP_S  14
+/** MCPWM_GEN2_A_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM2A triggered by event TEA when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_DTEA    0x00000003U
+#define MCPWM_GEN2_A_DTEA_M  (MCPWM_GEN2_A_DTEA_V << MCPWM_GEN2_A_DTEA_S)
+#define MCPWM_GEN2_A_DTEA_V  0x00000003U
+#define MCPWM_GEN2_A_DTEA_S  16
+/** MCPWM_GEN2_A_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM2A triggered by event TEB when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_DTEB    0x00000003U
+#define MCPWM_GEN2_A_DTEB_M  (MCPWM_GEN2_A_DTEB_V << MCPWM_GEN2_A_DTEB_S)
+#define MCPWM_GEN2_A_DTEB_V  0x00000003U
+#define MCPWM_GEN2_A_DTEB_S  18
+/** MCPWM_GEN2_A_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM2A triggered by event_t0 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_DT0    0x00000003U
+#define MCPWM_GEN2_A_DT0_M  (MCPWM_GEN2_A_DT0_V << MCPWM_GEN2_A_DT0_S)
+#define MCPWM_GEN2_A_DT0_V  0x00000003U
+#define MCPWM_GEN2_A_DT0_S  20
+/** MCPWM_GEN2_A_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_A_DT1    0x00000003U
+#define MCPWM_GEN2_A_DT1_M  (MCPWM_GEN2_A_DT1_V << MCPWM_GEN2_A_DT1_S)
+#define MCPWM_GEN2_A_DT1_V  0x00000003U
+#define MCPWM_GEN2_A_DT1_S  22
+
+/** MCPWM_GEN2_B_REG register
+ *  Actions triggered by events on PWM2B
+ */
+#define MCPWM_GEN2_B_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc4)
+/** MCPWM_GEN2_B_UTEZ : R/W; bitpos: [1:0]; default: 0;
+ *  Action on PWM2B triggered by event TEZ when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_UTEZ    0x00000003U
+#define MCPWM_GEN2_B_UTEZ_M  (MCPWM_GEN2_B_UTEZ_V << MCPWM_GEN2_B_UTEZ_S)
+#define MCPWM_GEN2_B_UTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_UTEZ_S  0
+/** MCPWM_GEN2_B_UTEP : R/W; bitpos: [3:2]; default: 0;
+ *  Action on PWM2B triggered by event TEP when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_UTEP    0x00000003U
+#define MCPWM_GEN2_B_UTEP_M  (MCPWM_GEN2_B_UTEP_V << MCPWM_GEN2_B_UTEP_S)
+#define MCPWM_GEN2_B_UTEP_V  0x00000003U
+#define MCPWM_GEN2_B_UTEP_S  2
+/** MCPWM_GEN2_B_UTEA : R/W; bitpos: [5:4]; default: 0;
+ *  Action on PWM2B triggered by event TEA when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_UTEA    0x00000003U
+#define MCPWM_GEN2_B_UTEA_M  (MCPWM_GEN2_B_UTEA_V << MCPWM_GEN2_B_UTEA_S)
+#define MCPWM_GEN2_B_UTEA_V  0x00000003U
+#define MCPWM_GEN2_B_UTEA_S  4
+/** MCPWM_GEN2_B_UTEB : R/W; bitpos: [7:6]; default: 0;
+ *  Action on PWM2B triggered by event TEB when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_UTEB    0x00000003U
+#define MCPWM_GEN2_B_UTEB_M  (MCPWM_GEN2_B_UTEB_V << MCPWM_GEN2_B_UTEB_S)
+#define MCPWM_GEN2_B_UTEB_V  0x00000003U
+#define MCPWM_GEN2_B_UTEB_S  6
+/** MCPWM_GEN2_B_UT0 : R/W; bitpos: [9:8]; default: 0;
+ *  Action on PWM2B triggered by event_t0 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_UT0    0x00000003U
+#define MCPWM_GEN2_B_UT0_M  (MCPWM_GEN2_B_UT0_V << MCPWM_GEN2_B_UT0_S)
+#define MCPWM_GEN2_B_UT0_V  0x00000003U
+#define MCPWM_GEN2_B_UT0_S  8
+/** MCPWM_GEN2_B_UT1 : R/W; bitpos: [11:10]; default: 0;
+ *  Action on PWM2B triggered by event_t1 when timer increasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_UT1    0x00000003U
+#define MCPWM_GEN2_B_UT1_M  (MCPWM_GEN2_B_UT1_V << MCPWM_GEN2_B_UT1_S)
+#define MCPWM_GEN2_B_UT1_V  0x00000003U
+#define MCPWM_GEN2_B_UT1_S  10
+/** MCPWM_GEN2_B_DTEZ : R/W; bitpos: [13:12]; default: 0;
+ *  Action on PWM2B triggered by event TEZ when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_DTEZ    0x00000003U
+#define MCPWM_GEN2_B_DTEZ_M  (MCPWM_GEN2_B_DTEZ_V << MCPWM_GEN2_B_DTEZ_S)
+#define MCPWM_GEN2_B_DTEZ_V  0x00000003U
+#define MCPWM_GEN2_B_DTEZ_S  12
+/** MCPWM_GEN2_B_DTEP : R/W; bitpos: [15:14]; default: 0;
+ *  Action on PWM2B triggered by event TEP when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_DTEP    0x00000003U
+#define MCPWM_GEN2_B_DTEP_M  (MCPWM_GEN2_B_DTEP_V << MCPWM_GEN2_B_DTEP_S)
+#define MCPWM_GEN2_B_DTEP_V  0x00000003U
+#define MCPWM_GEN2_B_DTEP_S  14
+/** MCPWM_GEN2_B_DTEA : R/W; bitpos: [17:16]; default: 0;
+ *  Action on PWM2B triggered by event TEA when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_DTEA    0x00000003U
+#define MCPWM_GEN2_B_DTEA_M  (MCPWM_GEN2_B_DTEA_V << MCPWM_GEN2_B_DTEA_S)
+#define MCPWM_GEN2_B_DTEA_V  0x00000003U
+#define MCPWM_GEN2_B_DTEA_S  16
+/** MCPWM_GEN2_B_DTEB : R/W; bitpos: [19:18]; default: 0;
+ *  Action on PWM2B triggered by event TEB when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_DTEB    0x00000003U
+#define MCPWM_GEN2_B_DTEB_M  (MCPWM_GEN2_B_DTEB_V << MCPWM_GEN2_B_DTEB_S)
+#define MCPWM_GEN2_B_DTEB_V  0x00000003U
+#define MCPWM_GEN2_B_DTEB_S  18
+/** MCPWM_GEN2_B_DT0 : R/W; bitpos: [21:20]; default: 0;
+ *  Action on PWM2B triggered by event_t0 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_DT0    0x00000003U
+#define MCPWM_GEN2_B_DT0_M  (MCPWM_GEN2_B_DT0_V << MCPWM_GEN2_B_DT0_S)
+#define MCPWM_GEN2_B_DT0_V  0x00000003U
+#define MCPWM_GEN2_B_DT0_S  20
+/** MCPWM_GEN2_B_DT1 : R/W; bitpos: [23:22]; default: 0;
+ *  Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+ *  2: high, 3: toggle
+ */
+#define MCPWM_GEN2_B_DT1    0x00000003U
+#define MCPWM_GEN2_B_DT1_M  (MCPWM_GEN2_B_DT1_V << MCPWM_GEN2_B_DT1_S)
+#define MCPWM_GEN2_B_DT1_V  0x00000003U
+#define MCPWM_GEN2_B_DT1_S  22
+
+/** MCPWM_DT2_CFG_REG register
+ *  PWM generator 2 dead time type selection and configuration
+ */
+#define MCPWM_DT2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xc8)
+/** MCPWM_DT2_FED_UPMETHOD : R/W; bitpos: [3:0]; default: 0;
+ *  Update method for FED (falling edge delay) active register.  0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DT2_FED_UPMETHOD    0x0000000FU
+#define MCPWM_DT2_FED_UPMETHOD_M  (MCPWM_DT2_FED_UPMETHOD_V << MCPWM_DT2_FED_UPMETHOD_S)
+#define MCPWM_DT2_FED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DT2_FED_UPMETHOD_S  0
+/** MCPWM_DT2_RED_UPMETHOD : R/W; bitpos: [7:4]; default: 0;
+ *  Update method for RED (rising edge delay) active register.  0: immediate,when bit0
+ *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+ *  bit3 is set to 1: disable the update
+ */
+#define MCPWM_DT2_RED_UPMETHOD    0x0000000FU
+#define MCPWM_DT2_RED_UPMETHOD_M  (MCPWM_DT2_RED_UPMETHOD_V << MCPWM_DT2_RED_UPMETHOD_S)
+#define MCPWM_DT2_RED_UPMETHOD_V  0x0000000FU
+#define MCPWM_DT2_RED_UPMETHOD_S  4
+/** MCPWM_DT2_DEB_MODE : R/W; bitpos: [8]; default: 0;
+ *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+ *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+ */
+#define MCPWM_DT2_DEB_MODE    (BIT(8))
+#define MCPWM_DT2_DEB_MODE_M  (MCPWM_DT2_DEB_MODE_V << MCPWM_DT2_DEB_MODE_S)
+#define MCPWM_DT2_DEB_MODE_V  0x00000001U
+#define MCPWM_DT2_DEB_MODE_S  8
+/** MCPWM_DT2_A_OUTSWAP : R/W; bitpos: [9]; default: 0;
+ *  S6 in table
+ */
+#define MCPWM_DT2_A_OUTSWAP    (BIT(9))
+#define MCPWM_DT2_A_OUTSWAP_M  (MCPWM_DT2_A_OUTSWAP_V << MCPWM_DT2_A_OUTSWAP_S)
+#define MCPWM_DT2_A_OUTSWAP_V  0x00000001U
+#define MCPWM_DT2_A_OUTSWAP_S  9
+/** MCPWM_DT2_B_OUTSWAP : R/W; bitpos: [10]; default: 0;
+ *  S7 in table
+ */
+#define MCPWM_DT2_B_OUTSWAP    (BIT(10))
+#define MCPWM_DT2_B_OUTSWAP_M  (MCPWM_DT2_B_OUTSWAP_V << MCPWM_DT2_B_OUTSWAP_S)
+#define MCPWM_DT2_B_OUTSWAP_V  0x00000001U
+#define MCPWM_DT2_B_OUTSWAP_S  10
+/** MCPWM_DT2_RED_INSEL : R/W; bitpos: [11]; default: 0;
+ *  S4 in table
+ */
+#define MCPWM_DT2_RED_INSEL    (BIT(11))
+#define MCPWM_DT2_RED_INSEL_M  (MCPWM_DT2_RED_INSEL_V << MCPWM_DT2_RED_INSEL_S)
+#define MCPWM_DT2_RED_INSEL_V  0x00000001U
+#define MCPWM_DT2_RED_INSEL_S  11
+/** MCPWM_DT2_FED_INSEL : R/W; bitpos: [12]; default: 0;
+ *  S5 in table
+ */
+#define MCPWM_DT2_FED_INSEL    (BIT(12))
+#define MCPWM_DT2_FED_INSEL_M  (MCPWM_DT2_FED_INSEL_V << MCPWM_DT2_FED_INSEL_S)
+#define MCPWM_DT2_FED_INSEL_V  0x00000001U
+#define MCPWM_DT2_FED_INSEL_S  12
+/** MCPWM_DT2_RED_OUTINVERT : R/W; bitpos: [13]; default: 0;
+ *  S2 in table
+ */
+#define MCPWM_DT2_RED_OUTINVERT    (BIT(13))
+#define MCPWM_DT2_RED_OUTINVERT_M  (MCPWM_DT2_RED_OUTINVERT_V << MCPWM_DT2_RED_OUTINVERT_S)
+#define MCPWM_DT2_RED_OUTINVERT_V  0x00000001U
+#define MCPWM_DT2_RED_OUTINVERT_S  13
+/** MCPWM_DT2_FED_OUTINVERT : R/W; bitpos: [14]; default: 0;
+ *  S3 in table
+ */
+#define MCPWM_DT2_FED_OUTINVERT    (BIT(14))
+#define MCPWM_DT2_FED_OUTINVERT_M  (MCPWM_DT2_FED_OUTINVERT_V << MCPWM_DT2_FED_OUTINVERT_S)
+#define MCPWM_DT2_FED_OUTINVERT_V  0x00000001U
+#define MCPWM_DT2_FED_OUTINVERT_S  14
+/** MCPWM_DT2_A_OUTBYPASS : R/W; bitpos: [15]; default: 1;
+ *  S1 in table
+ */
+#define MCPWM_DT2_A_OUTBYPASS    (BIT(15))
+#define MCPWM_DT2_A_OUTBYPASS_M  (MCPWM_DT2_A_OUTBYPASS_V << MCPWM_DT2_A_OUTBYPASS_S)
+#define MCPWM_DT2_A_OUTBYPASS_V  0x00000001U
+#define MCPWM_DT2_A_OUTBYPASS_S  15
+/** MCPWM_DT2_B_OUTBYPASS : R/W; bitpos: [16]; default: 1;
+ *  S0 in table
+ */
+#define MCPWM_DT2_B_OUTBYPASS    (BIT(16))
+#define MCPWM_DT2_B_OUTBYPASS_M  (MCPWM_DT2_B_OUTBYPASS_V << MCPWM_DT2_B_OUTBYPASS_S)
+#define MCPWM_DT2_B_OUTBYPASS_V  0x00000001U
+#define MCPWM_DT2_B_OUTBYPASS_S  16
+/** MCPWM_DT2_CLK_SEL : R/W; bitpos: [17]; default: 0;
+ *  Dead time clock selection. 0: PWM_clk, 1: PT_clk
+ */
+#define MCPWM_DT2_CLK_SEL    (BIT(17))
+#define MCPWM_DT2_CLK_SEL_M  (MCPWM_DT2_CLK_SEL_V << MCPWM_DT2_CLK_SEL_S)
+#define MCPWM_DT2_CLK_SEL_V  0x00000001U
+#define MCPWM_DT2_CLK_SEL_S  17
+
+/** MCPWM_DT2_FED_CFG_REG register
+ *  PWM generator 2 shadow register for falling edge delay (FED).
+ */
+#define MCPWM_DT2_FED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xcc)
+/** MCPWM_DT2_FED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for FED
+ */
+#define MCPWM_DT2_FED    0x0000FFFFU
+#define MCPWM_DT2_FED_M  (MCPWM_DT2_FED_V << MCPWM_DT2_FED_S)
+#define MCPWM_DT2_FED_V  0x0000FFFFU
+#define MCPWM_DT2_FED_S  0
+
+/** MCPWM_DT2_RED_CFG_REG register
+ *  PWM generator 2 shadow register for rising edge delay (RED).
+ */
+#define MCPWM_DT2_RED_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd0)
+/** MCPWM_DT2_RED : R/W; bitpos: [15:0]; default: 0;
+ *  Shadow register for RED
+ */
+#define MCPWM_DT2_RED    0x0000FFFFU
+#define MCPWM_DT2_RED_M  (MCPWM_DT2_RED_V << MCPWM_DT2_RED_S)
+#define MCPWM_DT2_RED_V  0x0000FFFFU
+#define MCPWM_DT2_RED_S  0
+
+/** MCPWM_CARRIER2_CFG_REG register
+ *  PWM generator 2 carrier enable and configuration
+ */
+#define MCPWM_CARRIER2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd4)
+/** MCPWM_CARRIER2_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, carrier2 function is enabled. When cleared, carrier2 is bypassed
+ */
+#define MCPWM_CARRIER2_EN    (BIT(0))
+#define MCPWM_CARRIER2_EN_M  (MCPWM_CARRIER2_EN_V << MCPWM_CARRIER2_EN_S)
+#define MCPWM_CARRIER2_EN_V  0x00000001U
+#define MCPWM_CARRIER2_EN_S  0
+/** MCPWM_CARRIER2_PRESCALE : R/W; bitpos: [4:1]; default: 0;
+ *  PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+ *  (PWM_CARRIER0_PRESCALE + 1)
+ */
+#define MCPWM_CARRIER2_PRESCALE    0x0000000FU
+#define MCPWM_CARRIER2_PRESCALE_M  (MCPWM_CARRIER2_PRESCALE_V << MCPWM_CARRIER2_PRESCALE_S)
+#define MCPWM_CARRIER2_PRESCALE_V  0x0000000FU
+#define MCPWM_CARRIER2_PRESCALE_S  1
+/** MCPWM_CARRIER2_DUTY : R/W; bitpos: [7:5]; default: 0;
+ *  carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8
+ */
+#define MCPWM_CARRIER2_DUTY    0x00000007U
+#define MCPWM_CARRIER2_DUTY_M  (MCPWM_CARRIER2_DUTY_V << MCPWM_CARRIER2_DUTY_S)
+#define MCPWM_CARRIER2_DUTY_V  0x00000007U
+#define MCPWM_CARRIER2_DUTY_S  5
+/** MCPWM_CARRIER2_OSHTWTH : R/W; bitpos: [11:8]; default: 0;
+ *  width of the first pulse in number of periods of the carrier
+ */
+#define MCPWM_CARRIER2_OSHTWTH    0x0000000FU
+#define MCPWM_CARRIER2_OSHTWTH_M  (MCPWM_CARRIER2_OSHTWTH_V << MCPWM_CARRIER2_OSHTWTH_S)
+#define MCPWM_CARRIER2_OSHTWTH_V  0x0000000FU
+#define MCPWM_CARRIER2_OSHTWTH_S  8
+/** MCPWM_CARRIER2_OUT_INVERT : R/W; bitpos: [12]; default: 0;
+ *  when set, invert the output of PWM2A and PWM2B for this submodule
+ */
+#define MCPWM_CARRIER2_OUT_INVERT    (BIT(12))
+#define MCPWM_CARRIER2_OUT_INVERT_M  (MCPWM_CARRIER2_OUT_INVERT_V << MCPWM_CARRIER2_OUT_INVERT_S)
+#define MCPWM_CARRIER2_OUT_INVERT_V  0x00000001U
+#define MCPWM_CARRIER2_OUT_INVERT_S  12
+/** MCPWM_CARRIER2_IN_INVERT : R/W; bitpos: [13]; default: 0;
+ *  when set, invert the input of PWM2A and PWM2B for this submodule
+ */
+#define MCPWM_CARRIER2_IN_INVERT    (BIT(13))
+#define MCPWM_CARRIER2_IN_INVERT_M  (MCPWM_CARRIER2_IN_INVERT_V << MCPWM_CARRIER2_IN_INVERT_S)
+#define MCPWM_CARRIER2_IN_INVERT_V  0x00000001U
+#define MCPWM_CARRIER2_IN_INVERT_S  13
+
+/** MCPWM_FH2_CFG0_REG register
+ *  Actions on PWM2A and PWM2B trip events
+ */
+#define MCPWM_FH2_CFG0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xd8)
+/** MCPWM_FH2_SW_CBC : R/W; bitpos: [0]; default: 0;
+ *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH2_SW_CBC    (BIT(0))
+#define MCPWM_FH2_SW_CBC_M  (MCPWM_FH2_SW_CBC_V << MCPWM_FH2_SW_CBC_S)
+#define MCPWM_FH2_SW_CBC_V  0x00000001U
+#define MCPWM_FH2_SW_CBC_S  0
+/** MCPWM_FH2_F2_CBC : R/W; bitpos: [1]; default: 0;
+ *  fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH2_F2_CBC    (BIT(1))
+#define MCPWM_FH2_F2_CBC_M  (MCPWM_FH2_F2_CBC_V << MCPWM_FH2_F2_CBC_S)
+#define MCPWM_FH2_F2_CBC_V  0x00000001U
+#define MCPWM_FH2_F2_CBC_S  1
+/** MCPWM_FH2_F1_CBC : R/W; bitpos: [2]; default: 0;
+ *  fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH2_F1_CBC    (BIT(2))
+#define MCPWM_FH2_F1_CBC_M  (MCPWM_FH2_F1_CBC_V << MCPWM_FH2_F1_CBC_S)
+#define MCPWM_FH2_F1_CBC_V  0x00000001U
+#define MCPWM_FH2_F1_CBC_S  2
+/** MCPWM_FH2_F0_CBC : R/W; bitpos: [3]; default: 0;
+ *  fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH2_F0_CBC    (BIT(3))
+#define MCPWM_FH2_F0_CBC_M  (MCPWM_FH2_F0_CBC_V << MCPWM_FH2_F0_CBC_S)
+#define MCPWM_FH2_F0_CBC_V  0x00000001U
+#define MCPWM_FH2_F0_CBC_S  3
+/** MCPWM_FH2_SW_OST : R/W; bitpos: [4]; default: 0;
+ *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH2_SW_OST    (BIT(4))
+#define MCPWM_FH2_SW_OST_M  (MCPWM_FH2_SW_OST_V << MCPWM_FH2_SW_OST_S)
+#define MCPWM_FH2_SW_OST_V  0x00000001U
+#define MCPWM_FH2_SW_OST_S  4
+/** MCPWM_FH2_F2_OST : R/W; bitpos: [5]; default: 0;
+ *  fault_event2 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH2_F2_OST    (BIT(5))
+#define MCPWM_FH2_F2_OST_M  (MCPWM_FH2_F2_OST_V << MCPWM_FH2_F2_OST_S)
+#define MCPWM_FH2_F2_OST_V  0x00000001U
+#define MCPWM_FH2_F2_OST_S  5
+/** MCPWM_FH2_F1_OST : R/W; bitpos: [6]; default: 0;
+ *  fault_event1 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH2_F1_OST    (BIT(6))
+#define MCPWM_FH2_F1_OST_M  (MCPWM_FH2_F1_OST_V << MCPWM_FH2_F1_OST_S)
+#define MCPWM_FH2_F1_OST_V  0x00000001U
+#define MCPWM_FH2_F1_OST_S  6
+/** MCPWM_FH2_F0_OST : R/W; bitpos: [7]; default: 0;
+ *  fault_event0 will trigger one-shot mode action. 0: disable, 1: enable
+ */
+#define MCPWM_FH2_F0_OST    (BIT(7))
+#define MCPWM_FH2_F0_OST_M  (MCPWM_FH2_F0_OST_V << MCPWM_FH2_F0_OST_S)
+#define MCPWM_FH2_F0_OST_V  0x00000001U
+#define MCPWM_FH2_F0_OST_S  7
+/** MCPWM_FH2_A_CBC_D : R/W; bitpos: [9:8]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH2_A_CBC_D    0x00000003U
+#define MCPWM_FH2_A_CBC_D_M  (MCPWM_FH2_A_CBC_D_V << MCPWM_FH2_A_CBC_D_S)
+#define MCPWM_FH2_A_CBC_D_V  0x00000003U
+#define MCPWM_FH2_A_CBC_D_S  8
+/** MCPWM_FH2_A_CBC_U : R/W; bitpos: [11:10]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH2_A_CBC_U    0x00000003U
+#define MCPWM_FH2_A_CBC_U_M  (MCPWM_FH2_A_CBC_U_V << MCPWM_FH2_A_CBC_U_S)
+#define MCPWM_FH2_A_CBC_U_V  0x00000003U
+#define MCPWM_FH2_A_CBC_U_S  10
+/** MCPWM_FH2_A_OST_D : R/W; bitpos: [13:12]; default: 0;
+ *  One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH2_A_OST_D    0x00000003U
+#define MCPWM_FH2_A_OST_D_M  (MCPWM_FH2_A_OST_D_V << MCPWM_FH2_A_OST_D_S)
+#define MCPWM_FH2_A_OST_D_V  0x00000003U
+#define MCPWM_FH2_A_OST_D_S  12
+/** MCPWM_FH2_A_OST_U : R/W; bitpos: [15:14]; default: 0;
+ *  One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH2_A_OST_U    0x00000003U
+#define MCPWM_FH2_A_OST_U_M  (MCPWM_FH2_A_OST_U_V << MCPWM_FH2_A_OST_U_S)
+#define MCPWM_FH2_A_OST_U_V  0x00000003U
+#define MCPWM_FH2_A_OST_U_S  14
+/** MCPWM_FH2_B_CBC_D : R/W; bitpos: [17:16]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
+ *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH2_B_CBC_D    0x00000003U
+#define MCPWM_FH2_B_CBC_D_M  (MCPWM_FH2_B_CBC_D_V << MCPWM_FH2_B_CBC_D_S)
+#define MCPWM_FH2_B_CBC_D_V  0x00000003U
+#define MCPWM_FH2_B_CBC_D_S  16
+/** MCPWM_FH2_B_CBC_U : R/W; bitpos: [19:18]; default: 0;
+ *  Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is
+ *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH2_B_CBC_U    0x00000003U
+#define MCPWM_FH2_B_CBC_U_M  (MCPWM_FH2_B_CBC_U_V << MCPWM_FH2_B_CBC_U_S)
+#define MCPWM_FH2_B_CBC_U_V  0x00000003U
+#define MCPWM_FH2_B_CBC_U_S  18
+/** MCPWM_FH2_B_OST_D : R/W; bitpos: [21:20]; default: 0;
+ *  One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH2_B_OST_D    0x00000003U
+#define MCPWM_FH2_B_OST_D_M  (MCPWM_FH2_B_OST_D_V << MCPWM_FH2_B_OST_D_S)
+#define MCPWM_FH2_B_OST_D_V  0x00000003U
+#define MCPWM_FH2_B_OST_D_S  20
+/** MCPWM_FH2_B_OST_U : R/W; bitpos: [23:22]; default: 0;
+ *  One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0:
+ *  do nothing, 1: force low, 2: force high, 3: toggle
+ */
+#define MCPWM_FH2_B_OST_U    0x00000003U
+#define MCPWM_FH2_B_OST_U_M  (MCPWM_FH2_B_OST_U_V << MCPWM_FH2_B_OST_U_S)
+#define MCPWM_FH2_B_OST_U_V  0x00000003U
+#define MCPWM_FH2_B_OST_U_S  22
+
+/** MCPWM_FH2_CFG1_REG register
+ *  Software triggers for fault handler actions
+ */
+#define MCPWM_FH2_CFG1_REG(i) (DR_REG_MCPWM_BASE(i) + 0xdc)
+/** MCPWM_FH2_CLR_OST : R/W; bitpos: [0]; default: 0;
+ *  a rising edge will clear on going one-shot mode action
+ */
+#define MCPWM_FH2_CLR_OST    (BIT(0))
+#define MCPWM_FH2_CLR_OST_M  (MCPWM_FH2_CLR_OST_V << MCPWM_FH2_CLR_OST_S)
+#define MCPWM_FH2_CLR_OST_V  0x00000001U
+#define MCPWM_FH2_CLR_OST_S  0
+/** MCPWM_FH2_CBCPULSE : R/W; bitpos: [2:1]; default: 0;
+ *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+ *  when bit1 is set to 1:TEP
+ */
+#define MCPWM_FH2_CBCPULSE    0x00000003U
+#define MCPWM_FH2_CBCPULSE_M  (MCPWM_FH2_CBCPULSE_V << MCPWM_FH2_CBCPULSE_S)
+#define MCPWM_FH2_CBCPULSE_V  0x00000003U
+#define MCPWM_FH2_CBCPULSE_S  1
+/** MCPWM_FH2_FORCE_CBC : R/W; bitpos: [3]; default: 0;
+ *  a toggle trigger a cycle-by-cycle mode action
+ */
+#define MCPWM_FH2_FORCE_CBC    (BIT(3))
+#define MCPWM_FH2_FORCE_CBC_M  (MCPWM_FH2_FORCE_CBC_V << MCPWM_FH2_FORCE_CBC_S)
+#define MCPWM_FH2_FORCE_CBC_V  0x00000001U
+#define MCPWM_FH2_FORCE_CBC_S  3
+/** MCPWM_FH2_FORCE_OST : R/W; bitpos: [4]; default: 0;
+ *  a toggle (software negate its value) triggers a one-shot mode action
+ */
+#define MCPWM_FH2_FORCE_OST    (BIT(4))
+#define MCPWM_FH2_FORCE_OST_M  (MCPWM_FH2_FORCE_OST_V << MCPWM_FH2_FORCE_OST_S)
+#define MCPWM_FH2_FORCE_OST_V  0x00000001U
+#define MCPWM_FH2_FORCE_OST_S  4
+
+/** MCPWM_FH2_STATUS_REG register
+ *  Status of fault events.
+ */
+#define MCPWM_FH2_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe0)
+/** MCPWM_FH2_CBC_ON : RO; bitpos: [0]; default: 0;
+ *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+ */
+#define MCPWM_FH2_CBC_ON    (BIT(0))
+#define MCPWM_FH2_CBC_ON_M  (MCPWM_FH2_CBC_ON_V << MCPWM_FH2_CBC_ON_S)
+#define MCPWM_FH2_CBC_ON_V  0x00000001U
+#define MCPWM_FH2_CBC_ON_S  0
+/** MCPWM_FH2_OST_ON : RO; bitpos: [1]; default: 0;
+ *  Set and reset by hardware. If set, an one-shot mode action is on going
+ */
+#define MCPWM_FH2_OST_ON    (BIT(1))
+#define MCPWM_FH2_OST_ON_M  (MCPWM_FH2_OST_ON_V << MCPWM_FH2_OST_ON_S)
+#define MCPWM_FH2_OST_ON_V  0x00000001U
+#define MCPWM_FH2_OST_ON_S  1
+
+/** MCPWM_FAULT_DETECT_REG register
+ *  Fault detection configuration and status
+ */
+#define MCPWM_FAULT_DETECT_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe4)
+/** MCPWM_F0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, fault_event0 generation is enabled
+ */
+#define MCPWM_F0_EN    (BIT(0))
+#define MCPWM_F0_EN_M  (MCPWM_F0_EN_V << MCPWM_F0_EN_S)
+#define MCPWM_F0_EN_V  0x00000001U
+#define MCPWM_F0_EN_S  0
+/** MCPWM_F1_EN : R/W; bitpos: [1]; default: 0;
+ *  When set, fault_event1 generation is enabled
+ */
+#define MCPWM_F1_EN    (BIT(1))
+#define MCPWM_F1_EN_M  (MCPWM_F1_EN_V << MCPWM_F1_EN_S)
+#define MCPWM_F1_EN_V  0x00000001U
+#define MCPWM_F1_EN_S  1
+/** MCPWM_F2_EN : R/W; bitpos: [2]; default: 0;
+ *  When set, fault_event2 generation is enabled
+ */
+#define MCPWM_F2_EN    (BIT(2))
+#define MCPWM_F2_EN_M  (MCPWM_F2_EN_V << MCPWM_F2_EN_S)
+#define MCPWM_F2_EN_V  0x00000001U
+#define MCPWM_F2_EN_S  2
+/** MCPWM_F0_POLE : R/W; bitpos: [3]; default: 0;
+ *  Set fault_event0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
+ *  1: level high
+ */
+#define MCPWM_F0_POLE    (BIT(3))
+#define MCPWM_F0_POLE_M  (MCPWM_F0_POLE_V << MCPWM_F0_POLE_S)
+#define MCPWM_F0_POLE_V  0x00000001U
+#define MCPWM_F0_POLE_S  3
+/** MCPWM_F1_POLE : R/W; bitpos: [4]; default: 0;
+ *  Set fault_event1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
+ *  1: level high
+ */
+#define MCPWM_F1_POLE    (BIT(4))
+#define MCPWM_F1_POLE_M  (MCPWM_F1_POLE_V << MCPWM_F1_POLE_S)
+#define MCPWM_F1_POLE_V  0x00000001U
+#define MCPWM_F1_POLE_S  4
+/** MCPWM_F2_POLE : R/W; bitpos: [5]; default: 0;
+ *  Set fault_event2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
+ *  1: level high
+ */
+#define MCPWM_F2_POLE    (BIT(5))
+#define MCPWM_F2_POLE_M  (MCPWM_F2_POLE_V << MCPWM_F2_POLE_S)
+#define MCPWM_F2_POLE_V  0x00000001U
+#define MCPWM_F2_POLE_S  5
+/** MCPWM_EVENT_F0 : RO; bitpos: [6]; default: 0;
+ *  Set and reset by hardware. If set, fault_event0 is on going
+ */
+#define MCPWM_EVENT_F0    (BIT(6))
+#define MCPWM_EVENT_F0_M  (MCPWM_EVENT_F0_V << MCPWM_EVENT_F0_S)
+#define MCPWM_EVENT_F0_V  0x00000001U
+#define MCPWM_EVENT_F0_S  6
+/** MCPWM_EVENT_F1 : RO; bitpos: [7]; default: 0;
+ *  Set and reset by hardware. If set, fault_event1 is on going
+ */
+#define MCPWM_EVENT_F1    (BIT(7))
+#define MCPWM_EVENT_F1_M  (MCPWM_EVENT_F1_V << MCPWM_EVENT_F1_S)
+#define MCPWM_EVENT_F1_V  0x00000001U
+#define MCPWM_EVENT_F1_S  7
+/** MCPWM_EVENT_F2 : RO; bitpos: [8]; default: 0;
+ *  Set and reset by hardware. If set, fault_event2 is on going
+ */
+#define MCPWM_EVENT_F2    (BIT(8))
+#define MCPWM_EVENT_F2_M  (MCPWM_EVENT_F2_V << MCPWM_EVENT_F2_S)
+#define MCPWM_EVENT_F2_V  0x00000001U
+#define MCPWM_EVENT_F2_S  8
+
+/** MCPWM_CAP_TIMER_CFG_REG register
+ *  Configure capture timer
+ */
+#define MCPWM_CAP_TIMER_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xe8)
+/** MCPWM_CAP_TIMER_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture timer incrementing under APB_clk is enabled.
+ */
+#define MCPWM_CAP_TIMER_EN    (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (MCPWM_CAP_TIMER_EN_V << MCPWM_CAP_TIMER_EN_S)
+#define MCPWM_CAP_TIMER_EN_V  0x00000001U
+#define MCPWM_CAP_TIMER_EN_S  0
+/** MCPWM_CAP_SYNCI_EN : R/W; bitpos: [1]; default: 0;
+ *  When set, capture timer sync is enabled.
+ */
+#define MCPWM_CAP_SYNCI_EN    (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (MCPWM_CAP_SYNCI_EN_V << MCPWM_CAP_SYNCI_EN_S)
+#define MCPWM_CAP_SYNCI_EN_V  0x00000001U
+#define MCPWM_CAP_SYNCI_EN_S  1
+/** MCPWM_CAP_SYNCI_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
+ *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
+ *  6: SYNC2 from GPIO matrix
+ */
+#define MCPWM_CAP_SYNCI_SEL    0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_M  (MCPWM_CAP_SYNCI_SEL_V << MCPWM_CAP_SYNCI_SEL_S)
+#define MCPWM_CAP_SYNCI_SEL_V  0x00000007U
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/** MCPWM_CAP_SYNC_SW : WT; bitpos: [5]; default: 0;
+ *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
+ *  timer is loaded with value in phase register.
+ */
+#define MCPWM_CAP_SYNC_SW    (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (MCPWM_CAP_SYNC_SW_V << MCPWM_CAP_SYNC_SW_S)
+#define MCPWM_CAP_SYNC_SW_V  0x00000001U
+#define MCPWM_CAP_SYNC_SW_S  5
+
+/** MCPWM_CAP_TIMER_PHASE_REG register
+ *  Phase for capture timer sync
+ */
+#define MCPWM_CAP_TIMER_PHASE_REG(i) (DR_REG_MCPWM_BASE(i) + 0xec)
+/** MCPWM_CAP_TIMER_PHASE : R/W; bitpos: [31:0]; default: 0;
+ *  Phase value for capture timer sync operation.
+ */
+#define MCPWM_CAP_TIMER_PHASE    0xFFFFFFFFU
+#define MCPWM_CAP_TIMER_PHASE_M  (MCPWM_CAP_TIMER_PHASE_V << MCPWM_CAP_TIMER_PHASE_S)
+#define MCPWM_CAP_TIMER_PHASE_V  0xFFFFFFFFU
+#define MCPWM_CAP_TIMER_PHASE_S  0
+
+/** MCPWM_CAP_CH0_CFG_REG register
+ *  Capture channel 0 configuration and enable
+ */
+#define MCPWM_CAP_CH0_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf0)
+/** MCPWM_CAP0_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 0 is enabled
+ */
+#define MCPWM_CAP0_EN    (BIT(0))
+#define MCPWM_CAP0_EN_M  (MCPWM_CAP0_EN_V << MCPWM_CAP0_EN_S)
+#define MCPWM_CAP0_EN_V  0x00000001U
+#define MCPWM_CAP0_EN_S  0
+/** MCPWM_CAP0_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP0_MODE    0x00000003U
+#define MCPWM_CAP0_MODE_M  (MCPWM_CAP0_MODE_V << MCPWM_CAP0_MODE_S)
+#define MCPWM_CAP0_MODE_V  0x00000003U
+#define MCPWM_CAP0_MODE_S  1
+/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP0_PRESCALE    0x000000FFU
+#define MCPWM_CAP0_PRESCALE_M  (MCPWM_CAP0_PRESCALE_V << MCPWM_CAP0_PRESCALE_S)
+#define MCPWM_CAP0_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP0_PRESCALE_S  3
+/** MCPWM_CAP0_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP0 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP0_IN_INVERT    (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (MCPWM_CAP0_IN_INVERT_V << MCPWM_CAP0_IN_INVERT_S)
+#define MCPWM_CAP0_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP0_IN_INVERT_S  11
+/** MCPWM_CAP0_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 0
+ */
+#define MCPWM_CAP0_SW    (BIT(12))
+#define MCPWM_CAP0_SW_M  (MCPWM_CAP0_SW_V << MCPWM_CAP0_SW_S)
+#define MCPWM_CAP0_SW_V  0x00000001U
+#define MCPWM_CAP0_SW_S  12
+
+/** MCPWM_CAP_CH1_CFG_REG register
+ *  Capture channel 1 configuration and enable
+ */
+#define MCPWM_CAP_CH1_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf4)
+/** MCPWM_CAP1_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 2 is enabled
+ */
+#define MCPWM_CAP1_EN    (BIT(0))
+#define MCPWM_CAP1_EN_M  (MCPWM_CAP1_EN_V << MCPWM_CAP1_EN_S)
+#define MCPWM_CAP1_EN_V  0x00000001U
+#define MCPWM_CAP1_EN_S  0
+/** MCPWM_CAP1_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP1_MODE    0x00000003U
+#define MCPWM_CAP1_MODE_M  (MCPWM_CAP1_MODE_V << MCPWM_CAP1_MODE_S)
+#define MCPWM_CAP1_MODE_V  0x00000003U
+#define MCPWM_CAP1_MODE_S  1
+/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP1_PRESCALE    0x000000FFU
+#define MCPWM_CAP1_PRESCALE_M  (MCPWM_CAP1_PRESCALE_V << MCPWM_CAP1_PRESCALE_S)
+#define MCPWM_CAP1_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP1_PRESCALE_S  3
+/** MCPWM_CAP1_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP1 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP1_IN_INVERT    (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_M  (MCPWM_CAP1_IN_INVERT_V << MCPWM_CAP1_IN_INVERT_S)
+#define MCPWM_CAP1_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP1_IN_INVERT_S  11
+/** MCPWM_CAP1_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 1
+ */
+#define MCPWM_CAP1_SW    (BIT(12))
+#define MCPWM_CAP1_SW_M  (MCPWM_CAP1_SW_V << MCPWM_CAP1_SW_S)
+#define MCPWM_CAP1_SW_V  0x00000001U
+#define MCPWM_CAP1_SW_S  12
+
+/** MCPWM_CAP_CH2_CFG_REG register
+ *  Capture channel 2 configuration and enable
+ */
+#define MCPWM_CAP_CH2_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0xf8)
+/** MCPWM_CAP2_EN : R/W; bitpos: [0]; default: 0;
+ *  When set, capture on channel 2 is enabled
+ */
+#define MCPWM_CAP2_EN    (BIT(0))
+#define MCPWM_CAP2_EN_M  (MCPWM_CAP2_EN_V << MCPWM_CAP2_EN_S)
+#define MCPWM_CAP2_EN_V  0x00000001U
+#define MCPWM_CAP2_EN_S  0
+/** MCPWM_CAP2_MODE : R/W; bitpos: [2:1]; default: 0;
+ *  Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable
+ *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+ *  edge.
+ */
+#define MCPWM_CAP2_MODE    0x00000003U
+#define MCPWM_CAP2_MODE_M  (MCPWM_CAP2_MODE_V << MCPWM_CAP2_MODE_S)
+#define MCPWM_CAP2_MODE_V  0x00000003U
+#define MCPWM_CAP2_MODE_S  1
+/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
+ *  Value of prescaling on positive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE +
+ *  1
+ */
+#define MCPWM_CAP2_PRESCALE    0x000000FFU
+#define MCPWM_CAP2_PRESCALE_M  (MCPWM_CAP2_PRESCALE_V << MCPWM_CAP2_PRESCALE_S)
+#define MCPWM_CAP2_PRESCALE_V  0x000000FFU
+#define MCPWM_CAP2_PRESCALE_S  3
+/** MCPWM_CAP2_IN_INVERT : R/W; bitpos: [11]; default: 0;
+ *  when set, CAP2 form GPIO matrix is inverted before prescale
+ */
+#define MCPWM_CAP2_IN_INVERT    (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_M  (MCPWM_CAP2_IN_INVERT_V << MCPWM_CAP2_IN_INVERT_S)
+#define MCPWM_CAP2_IN_INVERT_V  0x00000001U
+#define MCPWM_CAP2_IN_INVERT_S  11
+/** MCPWM_CAP2_SW : WT; bitpos: [12]; default: 0;
+ *  Write 1 will trigger a software forced capture on channel 2
+ */
+#define MCPWM_CAP2_SW    (BIT(12))
+#define MCPWM_CAP2_SW_M  (MCPWM_CAP2_SW_V << MCPWM_CAP2_SW_S)
+#define MCPWM_CAP2_SW_V  0x00000001U
+#define MCPWM_CAP2_SW_S  12
+
+/** MCPWM_CAP_CH0_REG register
+ *  ch0 capture value status register
+ */
+#define MCPWM_CAP_CH0_REG(i) (DR_REG_MCPWM_BASE(i) + 0xfc)
+/** MCPWM_CAP0_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 0
+ */
+#define MCPWM_CAP0_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_M  (MCPWM_CAP0_VALUE_V << MCPWM_CAP0_VALUE_S)
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP0_VALUE_S  0
+
+/** MCPWM_CAP_CH1_REG register
+ *  ch1 capture value status register
+ */
+#define MCPWM_CAP_CH1_REG(i) (DR_REG_MCPWM_BASE(i) + 0x100)
+/** MCPWM_CAP1_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 1
+ */
+#define MCPWM_CAP1_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP1_VALUE_M  (MCPWM_CAP1_VALUE_V << MCPWM_CAP1_VALUE_S)
+#define MCPWM_CAP1_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP1_VALUE_S  0
+
+/** MCPWM_CAP_CH2_REG register
+ *  ch2 capture value status register
+ */
+#define MCPWM_CAP_CH2_REG(i) (DR_REG_MCPWM_BASE(i) + 0x104)
+/** MCPWM_CAP2_VALUE : RO; bitpos: [31:0]; default: 0;
+ *  Value of last capture on channel 2
+ */
+#define MCPWM_CAP2_VALUE    0xFFFFFFFFU
+#define MCPWM_CAP2_VALUE_M  (MCPWM_CAP2_VALUE_V << MCPWM_CAP2_VALUE_S)
+#define MCPWM_CAP2_VALUE_V  0xFFFFFFFFU
+#define MCPWM_CAP2_VALUE_S  0
+
+/** MCPWM_CAP_STATUS_REG register
+ *  Edge of last capture trigger
+ */
+#define MCPWM_CAP_STATUS_REG(i) (DR_REG_MCPWM_BASE(i) + 0x108)
+/** MCPWM_CAP0_EDGE : RO; bitpos: [0]; default: 0;
+ *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP0_EDGE    (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (MCPWM_CAP0_EDGE_V << MCPWM_CAP0_EDGE_S)
+#define MCPWM_CAP0_EDGE_V  0x00000001U
+#define MCPWM_CAP0_EDGE_S  0
+/** MCPWM_CAP1_EDGE : RO; bitpos: [1]; default: 0;
+ *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP1_EDGE    (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (MCPWM_CAP1_EDGE_V << MCPWM_CAP1_EDGE_S)
+#define MCPWM_CAP1_EDGE_V  0x00000001U
+#define MCPWM_CAP1_EDGE_S  1
+/** MCPWM_CAP2_EDGE : RO; bitpos: [2]; default: 0;
+ *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
+ */
+#define MCPWM_CAP2_EDGE    (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (MCPWM_CAP2_EDGE_V << MCPWM_CAP2_EDGE_S)
+#define MCPWM_CAP2_EDGE_V  0x00000001U
+#define MCPWM_CAP2_EDGE_S  2
+
+/** MCPWM_UPDATE_CFG_REG register
+ *  Enable update.
+ */
+#define MCPWM_UPDATE_CFG_REG(i) (DR_REG_MCPWM_BASE(i) + 0x10c)
+/** MCPWM_GLOBAL_UP_EN : R/W; bitpos: [0]; default: 1;
+ *  The global enable of update of all active registers in MCPWM module
+ */
+#define MCPWM_GLOBAL_UP_EN    (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (MCPWM_GLOBAL_UP_EN_V << MCPWM_GLOBAL_UP_EN_S)
+#define MCPWM_GLOBAL_UP_EN_V  0x00000001U
+#define MCPWM_GLOBAL_UP_EN_S  0
+/** MCPWM_GLOBAL_FORCE_UP : R/W; bitpos: [1]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of all active
+ *  registers in MCPWM module
+ */
+#define MCPWM_GLOBAL_FORCE_UP    (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (MCPWM_GLOBAL_FORCE_UP_V << MCPWM_GLOBAL_FORCE_UP_S)
+#define MCPWM_GLOBAL_FORCE_UP_V  0x00000001U
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/** MCPWM_OP0_UP_EN : R/W; bitpos: [2]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
+ *  are enabled
+ */
+#define MCPWM_OP0_UP_EN    (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (MCPWM_OP0_UP_EN_V << MCPWM_OP0_UP_EN_S)
+#define MCPWM_OP0_UP_EN_V  0x00000001U
+#define MCPWM_OP0_UP_EN_S  2
+/** MCPWM_OP0_FORCE_UP : R/W; bitpos: [3]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 0
+ */
+#define MCPWM_OP0_FORCE_UP    (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (MCPWM_OP0_FORCE_UP_V << MCPWM_OP0_FORCE_UP_S)
+#define MCPWM_OP0_FORCE_UP_V  0x00000001U
+#define MCPWM_OP0_FORCE_UP_S  3
+/** MCPWM_OP1_UP_EN : R/W; bitpos: [4]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
+ *  are enabled
+ */
+#define MCPWM_OP1_UP_EN    (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (MCPWM_OP1_UP_EN_V << MCPWM_OP1_UP_EN_S)
+#define MCPWM_OP1_UP_EN_V  0x00000001U
+#define MCPWM_OP1_UP_EN_S  4
+/** MCPWM_OP1_FORCE_UP : R/W; bitpos: [5]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 1
+ */
+#define MCPWM_OP1_FORCE_UP    (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (MCPWM_OP1_FORCE_UP_V << MCPWM_OP1_FORCE_UP_S)
+#define MCPWM_OP1_FORCE_UP_V  0x00000001U
+#define MCPWM_OP1_FORCE_UP_S  5
+/** MCPWM_OP2_UP_EN : R/W; bitpos: [6]; default: 1;
+ *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
+ *  are enabled
+ */
+#define MCPWM_OP2_UP_EN    (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (MCPWM_OP2_UP_EN_V << MCPWM_OP2_UP_EN_S)
+#define MCPWM_OP2_UP_EN_V  0x00000001U
+#define MCPWM_OP2_UP_EN_S  6
+/** MCPWM_OP2_FORCE_UP : R/W; bitpos: [7]; default: 0;
+ *  a toggle (software invert its value) will trigger a forced update of active
+ *  registers in PWM operator 2
+ */
+#define MCPWM_OP2_FORCE_UP    (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (MCPWM_OP2_FORCE_UP_V << MCPWM_OP2_FORCE_UP_S)
+#define MCPWM_OP2_FORCE_UP_V  0x00000001U
+#define MCPWM_OP2_FORCE_UP_S  7
+
+/** MCPWM_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define MCPWM_INT_ENA_REG(i) (DR_REG_MCPWM_BASE(i) + 0x110)
+/** MCPWM_TIMER0_STOP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ENA    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (MCPWM_TIMER0_STOP_INT_ENA_V << MCPWM_TIMER0_STOP_INT_ENA_S)
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+/** MCPWM_TIMER1_STOP_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ENA    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (MCPWM_TIMER1_STOP_INT_ENA_V << MCPWM_TIMER1_STOP_INT_ENA_S)
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/** MCPWM_TIMER2_STOP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The enable bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ENA    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (MCPWM_TIMER2_STOP_INT_ENA_V << MCPWM_TIMER2_STOP_INT_ENA_S)
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/** MCPWM_TIMER0_TEZ_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ENA    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (MCPWM_TIMER0_TEZ_INT_ENA_V << MCPWM_TIMER0_TEZ_INT_ENA_S)
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/** MCPWM_TIMER1_TEZ_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ENA    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (MCPWM_TIMER1_TEZ_INT_ENA_V << MCPWM_TIMER1_TEZ_INT_ENA_S)
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/** MCPWM_TIMER2_TEZ_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ENA    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (MCPWM_TIMER2_TEZ_INT_ENA_V << MCPWM_TIMER2_TEZ_INT_ENA_S)
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/** MCPWM_TIMER0_TEP_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ENA    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (MCPWM_TIMER0_TEP_INT_ENA_V << MCPWM_TIMER0_TEP_INT_ENA_S)
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/** MCPWM_TIMER1_TEP_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ENA    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (MCPWM_TIMER1_TEP_INT_ENA_V << MCPWM_TIMER1_TEP_INT_ENA_S)
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/** MCPWM_TIMER2_TEP_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ENA    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (MCPWM_TIMER2_TEP_INT_ENA_V << MCPWM_TIMER2_TEP_INT_ENA_S)
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/** MCPWM_FAULT0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The enable bit for the interrupt triggered when fault_event0 starts.
+ */
+#define MCPWM_FAULT0_INT_ENA    (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (MCPWM_FAULT0_INT_ENA_V << MCPWM_FAULT0_INT_ENA_S)
+#define MCPWM_FAULT0_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_INT_ENA_S  9
+/** MCPWM_FAULT1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The enable bit for the interrupt triggered when fault_event1 starts.
+ */
+#define MCPWM_FAULT1_INT_ENA    (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (MCPWM_FAULT1_INT_ENA_V << MCPWM_FAULT1_INT_ENA_S)
+#define MCPWM_FAULT1_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_INT_ENA_S  10
+/** MCPWM_FAULT2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The enable bit for the interrupt triggered when fault_event2 starts.
+ */
+#define MCPWM_FAULT2_INT_ENA    (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (MCPWM_FAULT2_INT_ENA_V << MCPWM_FAULT2_INT_ENA_S)
+#define MCPWM_FAULT2_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_INT_ENA_S  11
+/** MCPWM_FAULT0_CLR_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The enable bit for the interrupt triggered when fault_event0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_ENA    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (MCPWM_FAULT0_CLR_INT_ENA_V << MCPWM_FAULT0_CLR_INT_ENA_S)
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/** MCPWM_FAULT1_CLR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The enable bit for the interrupt triggered when fault_event1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_ENA    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (MCPWM_FAULT1_CLR_INT_ENA_V << MCPWM_FAULT1_CLR_INT_ENA_S)
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/** MCPWM_FAULT2_CLR_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  The enable bit for the interrupt triggered when fault_event2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_ENA    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (MCPWM_FAULT2_CLR_INT_ENA_V << MCPWM_FAULT2_CLR_INT_ENA_S)
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/** MCPWM_OP0_TEA_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_OP0_TEA_INT_ENA    (BIT(15))
+#define MCPWM_OP0_TEA_INT_ENA_M  (MCPWM_OP0_TEA_INT_ENA_V << MCPWM_OP0_TEA_INT_ENA_S)
+#define MCPWM_OP0_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_OP0_TEA_INT_ENA_S  15
+/** MCPWM_OP1_TEA_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_OP1_TEA_INT_ENA    (BIT(16))
+#define MCPWM_OP1_TEA_INT_ENA_M  (MCPWM_OP1_TEA_INT_ENA_V << MCPWM_OP1_TEA_INT_ENA_S)
+#define MCPWM_OP1_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_OP1_TEA_INT_ENA_S  16
+/** MCPWM_OP2_TEA_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_OP2_TEA_INT_ENA    (BIT(17))
+#define MCPWM_OP2_TEA_INT_ENA_M  (MCPWM_OP2_TEA_INT_ENA_V << MCPWM_OP2_TEA_INT_ENA_S)
+#define MCPWM_OP2_TEA_INT_ENA_V  0x00000001U
+#define MCPWM_OP2_TEA_INT_ENA_S  17
+/** MCPWM_OP0_TEB_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_OP0_TEB_INT_ENA    (BIT(18))
+#define MCPWM_OP0_TEB_INT_ENA_M  (MCPWM_OP0_TEB_INT_ENA_V << MCPWM_OP0_TEB_INT_ENA_S)
+#define MCPWM_OP0_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_OP0_TEB_INT_ENA_S  18
+/** MCPWM_OP1_TEB_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_OP1_TEB_INT_ENA    (BIT(19))
+#define MCPWM_OP1_TEB_INT_ENA_M  (MCPWM_OP1_TEB_INT_ENA_V << MCPWM_OP1_TEB_INT_ENA_S)
+#define MCPWM_OP1_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_OP1_TEB_INT_ENA_S  19
+/** MCPWM_OP2_TEB_INT_ENA : R/W; bitpos: [20]; default: 0;
+ *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_OP2_TEB_INT_ENA    (BIT(20))
+#define MCPWM_OP2_TEB_INT_ENA_M  (MCPWM_OP2_TEB_INT_ENA_V << MCPWM_OP2_TEB_INT_ENA_S)
+#define MCPWM_OP2_TEB_INT_ENA_V  0x00000001U
+#define MCPWM_OP2_TEB_INT_ENA_S  20
+/** MCPWM_FH0_CBC_INT_ENA : R/W; bitpos: [21]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
+ */
+#define MCPWM_FH0_CBC_INT_ENA    (BIT(21))
+#define MCPWM_FH0_CBC_INT_ENA_M  (MCPWM_FH0_CBC_INT_ENA_V << MCPWM_FH0_CBC_INT_ENA_S)
+#define MCPWM_FH0_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_FH0_CBC_INT_ENA_S  21
+/** MCPWM_FH1_CBC_INT_ENA : R/W; bitpos: [22]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
+ */
+#define MCPWM_FH1_CBC_INT_ENA    (BIT(22))
+#define MCPWM_FH1_CBC_INT_ENA_M  (MCPWM_FH1_CBC_INT_ENA_V << MCPWM_FH1_CBC_INT_ENA_S)
+#define MCPWM_FH1_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_FH1_CBC_INT_ENA_S  22
+/** MCPWM_FH2_CBC_INT_ENA : R/W; bitpos: [23]; default: 0;
+ *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
+ */
+#define MCPWM_FH2_CBC_INT_ENA    (BIT(23))
+#define MCPWM_FH2_CBC_INT_ENA_M  (MCPWM_FH2_CBC_INT_ENA_V << MCPWM_FH2_CBC_INT_ENA_S)
+#define MCPWM_FH2_CBC_INT_ENA_V  0x00000001U
+#define MCPWM_FH2_CBC_INT_ENA_S  23
+/** MCPWM_FH0_OST_INT_ENA : R/W; bitpos: [24]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_FH0_OST_INT_ENA    (BIT(24))
+#define MCPWM_FH0_OST_INT_ENA_M  (MCPWM_FH0_OST_INT_ENA_V << MCPWM_FH0_OST_INT_ENA_S)
+#define MCPWM_FH0_OST_INT_ENA_V  0x00000001U
+#define MCPWM_FH0_OST_INT_ENA_S  24
+/** MCPWM_FH1_OST_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_FH1_OST_INT_ENA    (BIT(25))
+#define MCPWM_FH1_OST_INT_ENA_M  (MCPWM_FH1_OST_INT_ENA_V << MCPWM_FH1_OST_INT_ENA_S)
+#define MCPWM_FH1_OST_INT_ENA_V  0x00000001U
+#define MCPWM_FH1_OST_INT_ENA_S  25
+/** MCPWM_FH2_OST_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_FH2_OST_INT_ENA    (BIT(26))
+#define MCPWM_FH2_OST_INT_ENA_M  (MCPWM_FH2_OST_INT_ENA_V << MCPWM_FH2_OST_INT_ENA_S)
+#define MCPWM_FH2_OST_INT_ENA_V  0x00000001U
+#define MCPWM_FH2_OST_INT_ENA_S  26
+/** MCPWM_CAP0_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_ENA    (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (MCPWM_CAP0_INT_ENA_V << MCPWM_CAP0_INT_ENA_S)
+#define MCPWM_CAP0_INT_ENA_V  0x00000001U
+#define MCPWM_CAP0_INT_ENA_S  27
+/** MCPWM_CAP1_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_ENA    (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (MCPWM_CAP1_INT_ENA_V << MCPWM_CAP1_INT_ENA_S)
+#define MCPWM_CAP1_INT_ENA_V  0x00000001U
+#define MCPWM_CAP1_INT_ENA_S  28
+/** MCPWM_CAP2_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  The enable bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_ENA    (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (MCPWM_CAP2_INT_ENA_V << MCPWM_CAP2_INT_ENA_S)
+#define MCPWM_CAP2_INT_ENA_V  0x00000001U
+#define MCPWM_CAP2_INT_ENA_S  29
+
+/** MCPWM_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define MCPWM_INT_RAW_REG(i) (DR_REG_MCPWM_BASE(i) + 0x114)
+/** MCPWM_TIMER0_STOP_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_RAW    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (MCPWM_TIMER0_STOP_INT_RAW_V << MCPWM_TIMER0_STOP_INT_RAW_S)
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+/** MCPWM_TIMER1_STOP_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_RAW    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (MCPWM_TIMER1_STOP_INT_RAW_V << MCPWM_TIMER1_STOP_INT_RAW_S)
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/** MCPWM_TIMER2_STOP_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw status bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_RAW    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (MCPWM_TIMER2_STOP_INT_RAW_V << MCPWM_TIMER2_STOP_INT_RAW_S)
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/** MCPWM_TIMER0_TEZ_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_RAW    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (MCPWM_TIMER0_TEZ_INT_RAW_V << MCPWM_TIMER0_TEZ_INT_RAW_S)
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/** MCPWM_TIMER1_TEZ_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_RAW    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (MCPWM_TIMER1_TEZ_INT_RAW_V << MCPWM_TIMER1_TEZ_INT_RAW_S)
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/** MCPWM_TIMER2_TEZ_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_RAW    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (MCPWM_TIMER2_TEZ_INT_RAW_V << MCPWM_TIMER2_TEZ_INT_RAW_S)
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/** MCPWM_TIMER0_TEP_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_RAW    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (MCPWM_TIMER0_TEP_INT_RAW_V << MCPWM_TIMER0_TEP_INT_RAW_S)
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/** MCPWM_TIMER1_TEP_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_RAW    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (MCPWM_TIMER1_TEP_INT_RAW_V << MCPWM_TIMER1_TEP_INT_RAW_S)
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/** MCPWM_TIMER2_TEP_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_RAW    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (MCPWM_TIMER2_TEP_INT_RAW_V << MCPWM_TIMER2_TEP_INT_RAW_S)
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/** MCPWM_FAULT0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw status bit for the interrupt triggered when fault_event0 starts.
+ */
+#define MCPWM_FAULT0_INT_RAW    (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (MCPWM_FAULT0_INT_RAW_V << MCPWM_FAULT0_INT_RAW_S)
+#define MCPWM_FAULT0_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_INT_RAW_S  9
+/** MCPWM_FAULT1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw status bit for the interrupt triggered when fault_event1 starts.
+ */
+#define MCPWM_FAULT1_INT_RAW    (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (MCPWM_FAULT1_INT_RAW_V << MCPWM_FAULT1_INT_RAW_S)
+#define MCPWM_FAULT1_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_INT_RAW_S  10
+/** MCPWM_FAULT2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw status bit for the interrupt triggered when fault_event2 starts.
+ */
+#define MCPWM_FAULT2_INT_RAW    (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (MCPWM_FAULT2_INT_RAW_V << MCPWM_FAULT2_INT_RAW_S)
+#define MCPWM_FAULT2_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_INT_RAW_S  11
+/** MCPWM_FAULT0_CLR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw status bit for the interrupt triggered when fault_event0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_RAW    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (MCPWM_FAULT0_CLR_INT_RAW_V << MCPWM_FAULT0_CLR_INT_RAW_S)
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/** MCPWM_FAULT1_CLR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw status bit for the interrupt triggered when fault_event1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_RAW    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (MCPWM_FAULT1_CLR_INT_RAW_V << MCPWM_FAULT1_CLR_INT_RAW_S)
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/** MCPWM_FAULT2_CLR_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw status bit for the interrupt triggered when fault_event2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_RAW    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (MCPWM_FAULT2_CLR_INT_RAW_V << MCPWM_FAULT2_CLR_INT_RAW_S)
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/** MCPWM_OP0_TEA_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_OP0_TEA_INT_RAW    (BIT(15))
+#define MCPWM_OP0_TEA_INT_RAW_M  (MCPWM_OP0_TEA_INT_RAW_V << MCPWM_OP0_TEA_INT_RAW_S)
+#define MCPWM_OP0_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_OP0_TEA_INT_RAW_S  15
+/** MCPWM_OP1_TEA_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_OP1_TEA_INT_RAW    (BIT(16))
+#define MCPWM_OP1_TEA_INT_RAW_M  (MCPWM_OP1_TEA_INT_RAW_V << MCPWM_OP1_TEA_INT_RAW_S)
+#define MCPWM_OP1_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_OP1_TEA_INT_RAW_S  16
+/** MCPWM_OP2_TEA_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_OP2_TEA_INT_RAW    (BIT(17))
+#define MCPWM_OP2_TEA_INT_RAW_M  (MCPWM_OP2_TEA_INT_RAW_V << MCPWM_OP2_TEA_INT_RAW_S)
+#define MCPWM_OP2_TEA_INT_RAW_V  0x00000001U
+#define MCPWM_OP2_TEA_INT_RAW_S  17
+/** MCPWM_OP0_TEB_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_OP0_TEB_INT_RAW    (BIT(18))
+#define MCPWM_OP0_TEB_INT_RAW_M  (MCPWM_OP0_TEB_INT_RAW_V << MCPWM_OP0_TEB_INT_RAW_S)
+#define MCPWM_OP0_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_OP0_TEB_INT_RAW_S  18
+/** MCPWM_OP1_TEB_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_OP1_TEB_INT_RAW    (BIT(19))
+#define MCPWM_OP1_TEB_INT_RAW_M  (MCPWM_OP1_TEB_INT_RAW_V << MCPWM_OP1_TEB_INT_RAW_S)
+#define MCPWM_OP1_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_OP1_TEB_INT_RAW_S  19
+/** MCPWM_OP2_TEB_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0;
+ *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_OP2_TEB_INT_RAW    (BIT(20))
+#define MCPWM_OP2_TEB_INT_RAW_M  (MCPWM_OP2_TEB_INT_RAW_V << MCPWM_OP2_TEB_INT_RAW_S)
+#define MCPWM_OP2_TEB_INT_RAW_V  0x00000001U
+#define MCPWM_OP2_TEB_INT_RAW_S  20
+/** MCPWM_FH0_CBC_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM0.
+ */
+#define MCPWM_FH0_CBC_INT_RAW    (BIT(21))
+#define MCPWM_FH0_CBC_INT_RAW_M  (MCPWM_FH0_CBC_INT_RAW_V << MCPWM_FH0_CBC_INT_RAW_S)
+#define MCPWM_FH0_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_FH0_CBC_INT_RAW_S  21
+/** MCPWM_FH1_CBC_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM1.
+ */
+#define MCPWM_FH1_CBC_INT_RAW    (BIT(22))
+#define MCPWM_FH1_CBC_INT_RAW_M  (MCPWM_FH1_CBC_INT_RAW_V << MCPWM_FH1_CBC_INT_RAW_S)
+#define MCPWM_FH1_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_FH1_CBC_INT_RAW_S  22
+/** MCPWM_FH2_CBC_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0;
+ *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM2.
+ */
+#define MCPWM_FH2_CBC_INT_RAW    (BIT(23))
+#define MCPWM_FH2_CBC_INT_RAW_M  (MCPWM_FH2_CBC_INT_RAW_V << MCPWM_FH2_CBC_INT_RAW_S)
+#define MCPWM_FH2_CBC_INT_RAW_V  0x00000001U
+#define MCPWM_FH2_CBC_INT_RAW_S  23
+/** MCPWM_FH0_OST_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_FH0_OST_INT_RAW    (BIT(24))
+#define MCPWM_FH0_OST_INT_RAW_M  (MCPWM_FH0_OST_INT_RAW_V << MCPWM_FH0_OST_INT_RAW_S)
+#define MCPWM_FH0_OST_INT_RAW_V  0x00000001U
+#define MCPWM_FH0_OST_INT_RAW_S  24
+/** MCPWM_FH1_OST_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_FH1_OST_INT_RAW    (BIT(25))
+#define MCPWM_FH1_OST_INT_RAW_M  (MCPWM_FH1_OST_INT_RAW_V << MCPWM_FH1_OST_INT_RAW_S)
+#define MCPWM_FH1_OST_INT_RAW_V  0x00000001U
+#define MCPWM_FH1_OST_INT_RAW_S  25
+/** MCPWM_FH2_OST_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_FH2_OST_INT_RAW    (BIT(26))
+#define MCPWM_FH2_OST_INT_RAW_M  (MCPWM_FH2_OST_INT_RAW_V << MCPWM_FH2_OST_INT_RAW_S)
+#define MCPWM_FH2_OST_INT_RAW_V  0x00000001U
+#define MCPWM_FH2_OST_INT_RAW_S  26
+/** MCPWM_CAP0_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_RAW    (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (MCPWM_CAP0_INT_RAW_V << MCPWM_CAP0_INT_RAW_S)
+#define MCPWM_CAP0_INT_RAW_V  0x00000001U
+#define MCPWM_CAP0_INT_RAW_S  27
+/** MCPWM_CAP1_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_RAW    (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (MCPWM_CAP1_INT_RAW_V << MCPWM_CAP1_INT_RAW_S)
+#define MCPWM_CAP1_INT_RAW_V  0x00000001U
+#define MCPWM_CAP1_INT_RAW_S  28
+/** MCPWM_CAP2_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  The raw status bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_RAW    (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (MCPWM_CAP2_INT_RAW_V << MCPWM_CAP2_INT_RAW_S)
+#define MCPWM_CAP2_INT_RAW_V  0x00000001U
+#define MCPWM_CAP2_INT_RAW_S  29
+
+/** MCPWM_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define MCPWM_INT_ST_REG(i) (DR_REG_MCPWM_BASE(i) + 0x118)
+/** MCPWM_TIMER0_STOP_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_ST    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (MCPWM_TIMER0_STOP_INT_ST_V << MCPWM_TIMER0_STOP_INT_ST_S)
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+/** MCPWM_TIMER1_STOP_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_ST    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (MCPWM_TIMER1_STOP_INT_ST_V << MCPWM_TIMER1_STOP_INT_ST_S)
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/** MCPWM_TIMER2_STOP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked status bit for the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_ST    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (MCPWM_TIMER2_STOP_INT_ST_V << MCPWM_TIMER2_STOP_INT_ST_S)
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/** MCPWM_TIMER0_TEZ_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_ST    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (MCPWM_TIMER0_TEZ_INT_ST_V << MCPWM_TIMER0_TEZ_INT_ST_S)
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/** MCPWM_TIMER1_TEZ_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_ST    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (MCPWM_TIMER1_TEZ_INT_ST_V << MCPWM_TIMER1_TEZ_INT_ST_S)
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/** MCPWM_TIMER2_TEZ_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_ST    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (MCPWM_TIMER2_TEZ_INT_ST_V << MCPWM_TIMER2_TEZ_INT_ST_S)
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/** MCPWM_TIMER0_TEP_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_ST    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (MCPWM_TIMER0_TEP_INT_ST_V << MCPWM_TIMER0_TEP_INT_ST_S)
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/** MCPWM_TIMER1_TEP_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_ST    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (MCPWM_TIMER1_TEP_INT_ST_V << MCPWM_TIMER1_TEP_INT_ST_S)
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/** MCPWM_TIMER2_TEP_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_ST    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (MCPWM_TIMER2_TEP_INT_ST_V << MCPWM_TIMER2_TEP_INT_ST_S)
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/** MCPWM_FAULT0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked status bit for the interrupt triggered when fault_event0 starts.
+ */
+#define MCPWM_FAULT0_INT_ST    (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (MCPWM_FAULT0_INT_ST_V << MCPWM_FAULT0_INT_ST_S)
+#define MCPWM_FAULT0_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_INT_ST_S  9
+/** MCPWM_FAULT1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked status bit for the interrupt triggered when fault_event1 starts.
+ */
+#define MCPWM_FAULT1_INT_ST    (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (MCPWM_FAULT1_INT_ST_V << MCPWM_FAULT1_INT_ST_S)
+#define MCPWM_FAULT1_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_INT_ST_S  10
+/** MCPWM_FAULT2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked status bit for the interrupt triggered when fault_event2 starts.
+ */
+#define MCPWM_FAULT2_INT_ST    (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (MCPWM_FAULT2_INT_ST_V << MCPWM_FAULT2_INT_ST_S)
+#define MCPWM_FAULT2_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_INT_ST_S  11
+/** MCPWM_FAULT0_CLR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked status bit for the interrupt triggered when fault_event0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_ST    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (MCPWM_FAULT0_CLR_INT_ST_V << MCPWM_FAULT0_CLR_INT_ST_S)
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/** MCPWM_FAULT1_CLR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked status bit for the interrupt triggered when fault_event1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_ST    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (MCPWM_FAULT1_CLR_INT_ST_V << MCPWM_FAULT1_CLR_INT_ST_S)
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/** MCPWM_FAULT2_CLR_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked status bit for the interrupt triggered when fault_event2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_ST    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (MCPWM_FAULT2_CLR_INT_ST_V << MCPWM_FAULT2_CLR_INT_ST_S)
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/** MCPWM_OP0_TEA_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_OP0_TEA_INT_ST    (BIT(15))
+#define MCPWM_OP0_TEA_INT_ST_M  (MCPWM_OP0_TEA_INT_ST_V << MCPWM_OP0_TEA_INT_ST_S)
+#define MCPWM_OP0_TEA_INT_ST_V  0x00000001U
+#define MCPWM_OP0_TEA_INT_ST_S  15
+/** MCPWM_OP1_TEA_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_OP1_TEA_INT_ST    (BIT(16))
+#define MCPWM_OP1_TEA_INT_ST_M  (MCPWM_OP1_TEA_INT_ST_V << MCPWM_OP1_TEA_INT_ST_S)
+#define MCPWM_OP1_TEA_INT_ST_V  0x00000001U
+#define MCPWM_OP1_TEA_INT_ST_S  16
+/** MCPWM_OP2_TEA_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_OP2_TEA_INT_ST    (BIT(17))
+#define MCPWM_OP2_TEA_INT_ST_M  (MCPWM_OP2_TEA_INT_ST_V << MCPWM_OP2_TEA_INT_ST_S)
+#define MCPWM_OP2_TEA_INT_ST_V  0x00000001U
+#define MCPWM_OP2_TEA_INT_ST_S  17
+/** MCPWM_OP0_TEB_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_OP0_TEB_INT_ST    (BIT(18))
+#define MCPWM_OP0_TEB_INT_ST_M  (MCPWM_OP0_TEB_INT_ST_V << MCPWM_OP0_TEB_INT_ST_S)
+#define MCPWM_OP0_TEB_INT_ST_V  0x00000001U
+#define MCPWM_OP0_TEB_INT_ST_S  18
+/** MCPWM_OP1_TEB_INT_ST : RO; bitpos: [19]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_OP1_TEB_INT_ST    (BIT(19))
+#define MCPWM_OP1_TEB_INT_ST_M  (MCPWM_OP1_TEB_INT_ST_V << MCPWM_OP1_TEB_INT_ST_S)
+#define MCPWM_OP1_TEB_INT_ST_V  0x00000001U
+#define MCPWM_OP1_TEB_INT_ST_S  19
+/** MCPWM_OP2_TEB_INT_ST : RO; bitpos: [20]; default: 0;
+ *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_OP2_TEB_INT_ST    (BIT(20))
+#define MCPWM_OP2_TEB_INT_ST_M  (MCPWM_OP2_TEB_INT_ST_V << MCPWM_OP2_TEB_INT_ST_S)
+#define MCPWM_OP2_TEB_INT_ST_V  0x00000001U
+#define MCPWM_OP2_TEB_INT_ST_S  20
+/** MCPWM_FH0_CBC_INT_ST : RO; bitpos: [21]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM0.
+ */
+#define MCPWM_FH0_CBC_INT_ST    (BIT(21))
+#define MCPWM_FH0_CBC_INT_ST_M  (MCPWM_FH0_CBC_INT_ST_V << MCPWM_FH0_CBC_INT_ST_S)
+#define MCPWM_FH0_CBC_INT_ST_V  0x00000001U
+#define MCPWM_FH0_CBC_INT_ST_S  21
+/** MCPWM_FH1_CBC_INT_ST : RO; bitpos: [22]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM1.
+ */
+#define MCPWM_FH1_CBC_INT_ST    (BIT(22))
+#define MCPWM_FH1_CBC_INT_ST_M  (MCPWM_FH1_CBC_INT_ST_V << MCPWM_FH1_CBC_INT_ST_S)
+#define MCPWM_FH1_CBC_INT_ST_V  0x00000001U
+#define MCPWM_FH1_CBC_INT_ST_S  22
+/** MCPWM_FH2_CBC_INT_ST : RO; bitpos: [23]; default: 0;
+ *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+ *  on PWM2.
+ */
+#define MCPWM_FH2_CBC_INT_ST    (BIT(23))
+#define MCPWM_FH2_CBC_INT_ST_M  (MCPWM_FH2_CBC_INT_ST_V << MCPWM_FH2_CBC_INT_ST_S)
+#define MCPWM_FH2_CBC_INT_ST_V  0x00000001U
+#define MCPWM_FH2_CBC_INT_ST_S  23
+/** MCPWM_FH0_OST_INT_ST : RO; bitpos: [24]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_FH0_OST_INT_ST    (BIT(24))
+#define MCPWM_FH0_OST_INT_ST_M  (MCPWM_FH0_OST_INT_ST_V << MCPWM_FH0_OST_INT_ST_S)
+#define MCPWM_FH0_OST_INT_ST_V  0x00000001U
+#define MCPWM_FH0_OST_INT_ST_S  24
+/** MCPWM_FH1_OST_INT_ST : RO; bitpos: [25]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_FH1_OST_INT_ST    (BIT(25))
+#define MCPWM_FH1_OST_INT_ST_M  (MCPWM_FH1_OST_INT_ST_V << MCPWM_FH1_OST_INT_ST_S)
+#define MCPWM_FH1_OST_INT_ST_V  0x00000001U
+#define MCPWM_FH1_OST_INT_ST_S  25
+/** MCPWM_FH2_OST_INT_ST : RO; bitpos: [26]; default: 0;
+ *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_FH2_OST_INT_ST    (BIT(26))
+#define MCPWM_FH2_OST_INT_ST_M  (MCPWM_FH2_OST_INT_ST_V << MCPWM_FH2_OST_INT_ST_S)
+#define MCPWM_FH2_OST_INT_ST_V  0x00000001U
+#define MCPWM_FH2_OST_INT_ST_S  26
+/** MCPWM_CAP0_INT_ST : RO; bitpos: [27]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_ST    (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (MCPWM_CAP0_INT_ST_V << MCPWM_CAP0_INT_ST_S)
+#define MCPWM_CAP0_INT_ST_V  0x00000001U
+#define MCPWM_CAP0_INT_ST_S  27
+/** MCPWM_CAP1_INT_ST : RO; bitpos: [28]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_ST    (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (MCPWM_CAP1_INT_ST_V << MCPWM_CAP1_INT_ST_S)
+#define MCPWM_CAP1_INT_ST_V  0x00000001U
+#define MCPWM_CAP1_INT_ST_S  28
+/** MCPWM_CAP2_INT_ST : RO; bitpos: [29]; default: 0;
+ *  The masked status bit for the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_ST    (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (MCPWM_CAP2_INT_ST_V << MCPWM_CAP2_INT_ST_S)
+#define MCPWM_CAP2_INT_ST_V  0x00000001U
+#define MCPWM_CAP2_INT_ST_S  29
+
+/** MCPWM_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define MCPWM_INT_CLR_REG(i) (DR_REG_MCPWM_BASE(i) + 0x11c)
+/** MCPWM_TIMER0_STOP_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 0 stops.
+ */
+#define MCPWM_TIMER0_STOP_INT_CLR    (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (MCPWM_TIMER0_STOP_INT_CLR_V << MCPWM_TIMER0_STOP_INT_CLR_S)
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+/** MCPWM_TIMER1_STOP_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 1 stops.
+ */
+#define MCPWM_TIMER1_STOP_INT_CLR    (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (MCPWM_TIMER1_STOP_INT_CLR_V << MCPWM_TIMER1_STOP_INT_CLR_S)
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/** MCPWM_TIMER2_STOP_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the interrupt triggered when the timer 2 stops.
+ */
+#define MCPWM_TIMER2_STOP_INT_CLR    (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (MCPWM_TIMER2_STOP_INT_CLR_V << MCPWM_TIMER2_STOP_INT_CLR_S)
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/** MCPWM_TIMER0_TEZ_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
+ */
+#define MCPWM_TIMER0_TEZ_INT_CLR    (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (MCPWM_TIMER0_TEZ_INT_CLR_V << MCPWM_TIMER0_TEZ_INT_CLR_S)
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/** MCPWM_TIMER1_TEZ_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
+ */
+#define MCPWM_TIMER1_TEZ_INT_CLR    (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (MCPWM_TIMER1_TEZ_INT_CLR_V << MCPWM_TIMER1_TEZ_INT_CLR_S)
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/** MCPWM_TIMER2_TEZ_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
+ */
+#define MCPWM_TIMER2_TEZ_INT_CLR    (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (MCPWM_TIMER2_TEZ_INT_CLR_V << MCPWM_TIMER2_TEZ_INT_CLR_S)
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/** MCPWM_TIMER0_TEP_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
+ */
+#define MCPWM_TIMER0_TEP_INT_CLR    (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (MCPWM_TIMER0_TEP_INT_CLR_V << MCPWM_TIMER0_TEP_INT_CLR_S)
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/** MCPWM_TIMER1_TEP_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
+ */
+#define MCPWM_TIMER1_TEP_INT_CLR    (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (MCPWM_TIMER1_TEP_INT_CLR_V << MCPWM_TIMER1_TEP_INT_CLR_S)
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/** MCPWM_TIMER2_TEP_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
+ */
+#define MCPWM_TIMER2_TEP_INT_CLR    (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (MCPWM_TIMER2_TEP_INT_CLR_V << MCPWM_TIMER2_TEP_INT_CLR_S)
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x00000001U
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/** MCPWM_FAULT0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the interrupt triggered when fault_event0 starts.
+ */
+#define MCPWM_FAULT0_INT_CLR    (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (MCPWM_FAULT0_INT_CLR_V << MCPWM_FAULT0_INT_CLR_S)
+#define MCPWM_FAULT0_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_INT_CLR_S  9
+/** MCPWM_FAULT1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the interrupt triggered when fault_event1 starts.
+ */
+#define MCPWM_FAULT1_INT_CLR    (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (MCPWM_FAULT1_INT_CLR_V << MCPWM_FAULT1_INT_CLR_S)
+#define MCPWM_FAULT1_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_INT_CLR_S  10
+/** MCPWM_FAULT2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the interrupt triggered when fault_event2 starts.
+ */
+#define MCPWM_FAULT2_INT_CLR    (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (MCPWM_FAULT2_INT_CLR_V << MCPWM_FAULT2_INT_CLR_S)
+#define MCPWM_FAULT2_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_INT_CLR_S  11
+/** MCPWM_FAULT0_CLR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the interrupt triggered when fault_event0 ends.
+ */
+#define MCPWM_FAULT0_CLR_INT_CLR    (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (MCPWM_FAULT0_CLR_INT_CLR_V << MCPWM_FAULT0_CLR_INT_CLR_S)
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/** MCPWM_FAULT1_CLR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the interrupt triggered when fault_event1 ends.
+ */
+#define MCPWM_FAULT1_CLR_INT_CLR    (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (MCPWM_FAULT1_CLR_INT_CLR_V << MCPWM_FAULT1_CLR_INT_CLR_S)
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/** MCPWM_FAULT2_CLR_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the interrupt triggered when fault_event2 ends.
+ */
+#define MCPWM_FAULT2_CLR_INT_CLR    (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (MCPWM_FAULT2_CLR_INT_CLR_V << MCPWM_FAULT2_CLR_INT_CLR_S)
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x00000001U
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/** MCPWM_OP0_TEA_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
+ */
+#define MCPWM_OP0_TEA_INT_CLR    (BIT(15))
+#define MCPWM_OP0_TEA_INT_CLR_M  (MCPWM_OP0_TEA_INT_CLR_V << MCPWM_OP0_TEA_INT_CLR_S)
+#define MCPWM_OP0_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_OP0_TEA_INT_CLR_S  15
+/** MCPWM_OP1_TEA_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
+ */
+#define MCPWM_OP1_TEA_INT_CLR    (BIT(16))
+#define MCPWM_OP1_TEA_INT_CLR_M  (MCPWM_OP1_TEA_INT_CLR_V << MCPWM_OP1_TEA_INT_CLR_S)
+#define MCPWM_OP1_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_OP1_TEA_INT_CLR_S  16
+/** MCPWM_OP2_TEA_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
+ */
+#define MCPWM_OP2_TEA_INT_CLR    (BIT(17))
+#define MCPWM_OP2_TEA_INT_CLR_M  (MCPWM_OP2_TEA_INT_CLR_V << MCPWM_OP2_TEA_INT_CLR_S)
+#define MCPWM_OP2_TEA_INT_CLR_V  0x00000001U
+#define MCPWM_OP2_TEA_INT_CLR_S  17
+/** MCPWM_OP0_TEB_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
+ */
+#define MCPWM_OP0_TEB_INT_CLR    (BIT(18))
+#define MCPWM_OP0_TEB_INT_CLR_M  (MCPWM_OP0_TEB_INT_CLR_V << MCPWM_OP0_TEB_INT_CLR_S)
+#define MCPWM_OP0_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_OP0_TEB_INT_CLR_S  18
+/** MCPWM_OP1_TEB_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
+ */
+#define MCPWM_OP1_TEB_INT_CLR    (BIT(19))
+#define MCPWM_OP1_TEB_INT_CLR_M  (MCPWM_OP1_TEB_INT_CLR_V << MCPWM_OP1_TEB_INT_CLR_S)
+#define MCPWM_OP1_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_OP1_TEB_INT_CLR_S  19
+/** MCPWM_OP2_TEB_INT_CLR : WT; bitpos: [20]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
+ */
+#define MCPWM_OP2_TEB_INT_CLR    (BIT(20))
+#define MCPWM_OP2_TEB_INT_CLR_M  (MCPWM_OP2_TEB_INT_CLR_V << MCPWM_OP2_TEB_INT_CLR_S)
+#define MCPWM_OP2_TEB_INT_CLR_V  0x00000001U
+#define MCPWM_OP2_TEB_INT_CLR_S  20
+/** MCPWM_FH0_CBC_INT_CLR : WT; bitpos: [21]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM0.
+ */
+#define MCPWM_FH0_CBC_INT_CLR    (BIT(21))
+#define MCPWM_FH0_CBC_INT_CLR_M  (MCPWM_FH0_CBC_INT_CLR_V << MCPWM_FH0_CBC_INT_CLR_S)
+#define MCPWM_FH0_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_FH0_CBC_INT_CLR_S  21
+/** MCPWM_FH1_CBC_INT_CLR : WT; bitpos: [22]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM1.
+ */
+#define MCPWM_FH1_CBC_INT_CLR    (BIT(22))
+#define MCPWM_FH1_CBC_INT_CLR_M  (MCPWM_FH1_CBC_INT_CLR_V << MCPWM_FH1_CBC_INT_CLR_S)
+#define MCPWM_FH1_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_FH1_CBC_INT_CLR_S  22
+/** MCPWM_FH2_CBC_INT_CLR : WT; bitpos: [23]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+ *  PWM2.
+ */
+#define MCPWM_FH2_CBC_INT_CLR    (BIT(23))
+#define MCPWM_FH2_CBC_INT_CLR_M  (MCPWM_FH2_CBC_INT_CLR_V << MCPWM_FH2_CBC_INT_CLR_S)
+#define MCPWM_FH2_CBC_INT_CLR_V  0x00000001U
+#define MCPWM_FH2_CBC_INT_CLR_S  23
+/** MCPWM_FH0_OST_INT_CLR : WT; bitpos: [24]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
+ */
+#define MCPWM_FH0_OST_INT_CLR    (BIT(24))
+#define MCPWM_FH0_OST_INT_CLR_M  (MCPWM_FH0_OST_INT_CLR_V << MCPWM_FH0_OST_INT_CLR_S)
+#define MCPWM_FH0_OST_INT_CLR_V  0x00000001U
+#define MCPWM_FH0_OST_INT_CLR_S  24
+/** MCPWM_FH1_OST_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
+ */
+#define MCPWM_FH1_OST_INT_CLR    (BIT(25))
+#define MCPWM_FH1_OST_INT_CLR_M  (MCPWM_FH1_OST_INT_CLR_V << MCPWM_FH1_OST_INT_CLR_S)
+#define MCPWM_FH1_OST_INT_CLR_V  0x00000001U
+#define MCPWM_FH1_OST_INT_CLR_S  25
+/** MCPWM_FH2_OST_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
+ */
+#define MCPWM_FH2_OST_INT_CLR    (BIT(26))
+#define MCPWM_FH2_OST_INT_CLR_M  (MCPWM_FH2_OST_INT_CLR_V << MCPWM_FH2_OST_INT_CLR_S)
+#define MCPWM_FH2_OST_INT_CLR_V  0x00000001U
+#define MCPWM_FH2_OST_INT_CLR_S  26
+/** MCPWM_CAP0_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 0.
+ */
+#define MCPWM_CAP0_INT_CLR    (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (MCPWM_CAP0_INT_CLR_V << MCPWM_CAP0_INT_CLR_S)
+#define MCPWM_CAP0_INT_CLR_V  0x00000001U
+#define MCPWM_CAP0_INT_CLR_S  27
+/** MCPWM_CAP1_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 1.
+ */
+#define MCPWM_CAP1_INT_CLR    (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (MCPWM_CAP1_INT_CLR_V << MCPWM_CAP1_INT_CLR_S)
+#define MCPWM_CAP1_INT_CLR_V  0x00000001U
+#define MCPWM_CAP1_INT_CLR_S  28
+/** MCPWM_CAP2_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  Set this bit to clear the interrupt triggered by capture on channel 2.
+ */
+#define MCPWM_CAP2_INT_CLR    (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (MCPWM_CAP2_INT_CLR_V << MCPWM_CAP2_INT_CLR_S)
+#define MCPWM_CAP2_INT_CLR_V  0x00000001U
+#define MCPWM_CAP2_INT_CLR_S  29
+
+/** MCPWM_CLK_REG register
+ *  MCPWM APB configuration register
+ */
+#define MCPWM_CLK_REG(i) (DR_REG_MCPWM_BASE(i) + 0x120)
+/** MCPWM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Force clock on for this register file
+ */
+#define MCPWM_CLK_EN    (BIT(0))
+#define MCPWM_CLK_EN_M  (MCPWM_CLK_EN_V << MCPWM_CLK_EN_S)
+#define MCPWM_CLK_EN_V  0x00000001U
+#define MCPWM_CLK_EN_S  0
+
+/** MCPWM_VERSION_REG register
+ *  Version register.
+ */
+#define MCPWM_VERSION_REG(i) (DR_REG_MCPWM_BASE(i) + 0x124)
+/** MCPWM_DATE : R/W; bitpos: [27:0]; default: 34632240;
+ *  Version of this register file
+ */
+#define MCPWM_DATE    0x0FFFFFFFU
+#define MCPWM_DATE_M  (MCPWM_DATE_V << MCPWM_DATE_S)
+#define MCPWM_DATE_V  0x0FFFFFFFU
+#define MCPWM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/mcpwm_struct.h b/components/soc/esp32s3/register/soc/mcpwm_struct.h
new file mode 100644
index 00000000000..9040142e67e
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/mcpwm_struct.h
@@ -0,0 +1,1468 @@
+/**
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Prescaler configuration */
+/** Type of clk_cfg register
+ *  PWM clock prescaler register.
+ */
+typedef union {
+    struct {
+        /** clk_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)
+         */
+        uint32_t clk_prescale: 8;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} mcpwm_clk_cfg_reg_t;
+
+
+/** Group: MCPWM Timer Configuration and status */
+/** Type of timer_cfg0 register
+ *  PWM timer period and update method configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_prescale : R/W; bitpos: [7:0]; default: 0;
+         *  Configure the divisor of PT0_clk, takes effect when PWM timer stops and starts
+         *  agsin. period of PT0_clk = Period of PWM_clk * (PWM_TIMER_PRESCALE + 1)
+         */
+        uint32_t timer_prescale: 8;
+        /** timer_period : R/W; bitpos: [23:8]; default: 255;
+         *  period shadow register of PWM timer
+         */
+        uint32_t timer_period: 16;
+        /** timer_period_upmethod : R/W; bitpos: [25:24]; default: 0;
+         *  Update method for active register of PWM timer period, 0: immediate, 1: TEZ, 2:
+         *  sync, 3: TEZ or sync. TEZ here and below means timer equal zero event
+         */
+        uint32_t timer_period_upmethod: 2;
+        uint32_t reserved_26: 6;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg0_reg_t;
+
+/** Type of timer_cfg1 register
+ *  PWM timer working mode and start/stop control configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_start : R/W/SC; bitpos: [2:0]; default: 0;
+         *  PWM timer start and stop control. 0: if PWM timer starts, then stops at TEZ, 1:
+         *  if timer starts, then stops at TEP, 2: PWM timer starts and runs on, 3: timer
+         *  starts and stops at the next TEZ, 4: timer starts and stops at the next TEP. TEP
+         *  here and below means the event that happens when the timer equals to period
+         */
+        uint32_t timer_start: 3;
+        /** timer_mod : R/W; bitpos: [4:3]; default: 0;
+         *  PWM timer working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down
+         *  mode
+         */
+        uint32_t timer_mod: 2;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} mcpwm_timer_cfg1_reg_t;
+
+/** Type of timer_sync register
+ *  PWM timer sync function configuration register.
+ */
+typedef union {
+    struct {
+        /** timer_synci_en : R/W; bitpos: [0]; default: 0;
+         *  When set, timer reloading with phase on sync input event is enabled.
+         */
+        uint32_t timer_synci_en: 1;
+        /** timer_sync_sw : R/W; bitpos: [1]; default: 0;
+         *  Toggling this bit will trigger a software sync.
+         */
+        uint32_t timer_sync_sw: 1;
+        /** timer_synco_sel : R/W; bitpos: [3:2]; default: 0;
+         *  PWM timer sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always
+         *  generate when toggling the reg_timer_sync_sw bit
+         */
+        uint32_t timer_synco_sel: 2;
+        /** timer_phase : R/W; bitpos: [19:4]; default: 0;
+         *  phase for timer reload on sync event
+         */
+        uint32_t timer_phase: 16;
+        /** timer_phase_direction : R/W; bitpos: [20]; default: 0;
+         *  Configure the PWM timer's direction at the time sync event occurs when timer mode
+         *  is up-down mode: 0-increase,1-decrease
+         */
+        uint32_t timer_phase_direction: 1;
+        uint32_t reserved_21: 11;
+    };
+    uint32_t val;
+} mcpwm_timer_sync_reg_t;
+
+/** Type of timer_status register
+ *  PWM timer status register.
+ */
+typedef union {
+    struct {
+        /** timer_value : RO; bitpos: [15:0]; default: 0;
+         *  current PWM timer counter value
+         */
+        uint32_t timer_value: 16;
+        /** timer_direction : RO; bitpos: [16]; default: 0;
+         *  current PWM timer counter direction, 0: increment 1: decrement
+         */
+        uint32_t timer_direction: 1;
+        uint32_t reserved_17: 15;
+    };
+    uint32_t val;
+} mcpwm_timer_status_reg_t;
+
+
+/** Group: Common configuration for MCPWM timers */
+/** Type of timer_synci_cfg register
+ *  Synchronization input selection for three PWM timers.
+ */
+typedef union {
+    struct {
+        /** timer0_syncisel : R/W; bitpos: [2:0]; default: 0;
+         *  select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer0_syncisel: 3;
+        /** timer1_syncisel : R/W; bitpos: [5:3]; default: 0;
+         *  select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer1_syncisel: 3;
+        /** timer2_syncisel : R/W; bitpos: [8:6]; default: 0;
+         *  select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out,
+         *  3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6:
+         *  SYNC2 from GPIO matrix, other values: no sync input selected
+         */
+        uint32_t timer2_syncisel: 3;
+        /** external_synci0_invert : R/W; bitpos: [9]; default: 0;
+         *  invert SYNC0 from GPIO matrix
+         */
+        uint32_t external_synci0_invert: 1;
+        /** external_synci1_invert : R/W; bitpos: [10]; default: 0;
+         *  invert SYNC1 from GPIO matrix
+         */
+        uint32_t external_synci1_invert: 1;
+        /** external_synci2_invert : R/W; bitpos: [11]; default: 0;
+         *  invert SYNC2 from GPIO matrix
+         */
+        uint32_t external_synci2_invert: 1;
+        uint32_t reserved_12: 20;
+    };
+    uint32_t val;
+} mcpwm_timer_synci_cfg_reg_t;
+
+/** Type of operator_timersel register
+ *  Select specific timer for PWM operators.
+ */
+typedef union {
+    struct {
+        /** operator0_timersel : R/W; bitpos: [1:0]; default: 0;
+         *  Select which PWM timer is the timing reference for PWM operator0, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator0_timersel: 2;
+        /** operator1_timersel : R/W; bitpos: [3:2]; default: 0;
+         *  Select which PWM timer is the timing reference for PWM operator1, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator1_timersel: 2;
+        /** operator2_timersel : R/W; bitpos: [5:4]; default: 0;
+         *  Select which PWM timer is the timing reference for PWM operator2, 0: timer0, 1:
+         *  timer1, 2: timer2
+         */
+        uint32_t operator2_timersel: 2;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} mcpwm_operator_timersel_reg_t;
+
+
+/** Group: MCPWM Operator Configuration and Status */
+/** Type of gen_stmp_cfg register
+ *  Transfer status and update method for time stamp registers A and B
+ */
+typedef union {
+    struct {
+        /** gen_a_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for PWM generator time stamp A's active register. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+         */
+        uint32_t gen_a_upmethod: 4;
+        /** gen_b_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Update method for PWM generator time stamp B's active register. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when
+         *  bit2 is set to 1: sync, when bit3 is set to 1: disable the update.
+         */
+        uint32_t gen_b_upmethod: 4;
+        /** gen_a_shdw_full : R/W/WTC/SC; bitpos: [8]; default: 0;
+         *  Set and reset by hardware. If set, PWM generator time stamp A's shadow reg is
+         *  filled and waiting to be transferred to A's active reg. If cleared, A's active reg
+         *  has been updated with shadow register latest value
+         */
+        uint32_t gen_a_shdw_full: 1;
+        /** gen_b_shdw_full : R/W/WTC/SC; bitpos: [9]; default: 0;
+         *  Set and reset by hardware. If set, PWM generator time stamp B's shadow reg is
+         *  filled and waiting to be transferred to B's active reg. If cleared, B's active reg
+         *  has been updated with shadow register latest value
+         */
+        uint32_t gen_b_shdw_full: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} mcpwm_gen_stmp_cfg_reg_t;
+
+/** Type of gen_tstmp register
+ *  PWM generator shadow register for timer stamp
+ */
+typedef union {
+    struct {
+        /** gen : R/W; bitpos: [15:0]; default: 0;
+         *  PWM generator time stamp's shadow register
+         */
+        uint32_t gen: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} mcpwm_gen_tstmp_reg_t;
+
+/** Type of gen_cfg0 register
+ *  PWM generator event T0 and T1 handling
+ */
+typedef union {
+    struct {
+        /** gen_cfg_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for PWM generator's active register of configuration. When all bits
+         *  are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to
+         *  1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update
+         */
+        uint32_t gen_cfg_upmethod: 4;
+        /** gen_t0_sel : R/W; bitpos: [6:4]; default: 0;
+         *  Source selection for PWM generator event_t0, take effect immediately, 0:
+         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+         */
+        uint32_t gen_t0_sel: 3;
+        /** gen_t1_sel : R/W; bitpos: [9:7]; default: 0;
+         *  Source selection for PWM generator event_t1, take effect immediately, 0:
+         *  fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none
+         */
+        uint32_t gen_t1_sel: 3;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} mcpwm_gen_cfg0_reg_t;
+
+/** Type of gen_force register
+ *  Permissives to force PWM0A and PWM0B outputs by software
+ */
+typedef union {
+    struct {
+        /** gen_cntuforce_upmethod : R/W; bitpos: [5:0]; default: 32;
+         *  Updating method for continuous software force of PWM generator0. When all bits are
+         *  set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when
+         *  bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync,
+         *  when bit5 is set to 1: disable update. (TEA/B here and below means an event
+         *  generated when the timer's value equals to that of register A/B.)
+         */
+        uint32_t gen_cntuforce_upmethod: 6;
+        /** gen_a_cntuforce_mode : R/W; bitpos: [7:6]; default: 0;
+         *  Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled
+         */
+        uint32_t gen_a_cntuforce_mode: 2;
+        /** gen_b_cntuforce_mode : R/W; bitpos: [9:8]; default: 0;
+         *  Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled
+         */
+        uint32_t gen_b_cntuforce_mode: 2;
+        /** gen_a_nciforce : R/W; bitpos: [10]; default: 0;
+         *  Trigger of non-continuous immediate software-force event for PWM0A, a toggle will
+         *  trigger a force event.
+         */
+        uint32_t gen_a_nciforce: 1;
+        /** gen_a_nciforce_mode : R/W; bitpos: [12:11]; default: 0;
+         *  non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2:
+         *  high, 3: disabled
+         */
+        uint32_t gen_a_nciforce_mode: 2;
+        /** gen_b_nciforce : R/W; bitpos: [13]; default: 0;
+         *  Trigger of non-continuous immediate software-force event for PWM0B, a toggle will
+         *  trigger a force event.
+         */
+        uint32_t gen_b_nciforce: 1;
+        /** gen_b_nciforce_mode : R/W; bitpos: [15:14]; default: 0;
+         *  non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2:
+         *  high, 3: disabled
+         */
+        uint32_t gen_b_nciforce_mode: 2;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} mcpwm_gen_force_reg_t;
+
+/** Type of generator register
+ *  Actions triggered by events on PWM0A
+ */
+typedef union {
+    struct {
+        /** gen_utez : R/W; bitpos: [1:0]; default: 0;
+         *  Action on PWM0A triggered by event TEZ when timer increasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_utez: 2;
+        /** gen_utep : R/W; bitpos: [3:2]; default: 0;
+         *  Action on PWM0A triggered by event TEP when timer increasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_utep: 2;
+        /** gen_utea : R/W; bitpos: [5:4]; default: 0;
+         *  Action on PWM0A triggered by event TEA when timer increasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_utea: 2;
+        /** gen_uteb : R/W; bitpos: [7:6]; default: 0;
+         *  Action on PWM0A triggered by event TEB when timer increasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_uteb: 2;
+        /** gen_ut0 : R/W; bitpos: [9:8]; default: 0;
+         *  Action on PWM0A triggered by event_t0 when timer increasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_ut0: 2;
+        /** gen_ut1 : R/W; bitpos: [11:10]; default: 0;
+         *  Action on PWM0A triggered by event_t1 when timer increasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_ut1: 2;
+        /** gen_dtez : R/W; bitpos: [13:12]; default: 0;
+         *  Action on PWM0A triggered by event TEZ when timer decreasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_dtez: 2;
+        /** gen_dtep : R/W; bitpos: [15:14]; default: 0;
+         *  Action on PWM0A triggered by event TEP when timer decreasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_dtep: 2;
+        /** gen_dtea : R/W; bitpos: [17:16]; default: 0;
+         *  Action on PWM0A triggered by event TEA when timer decreasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_dtea: 2;
+        /** gen_dteb : R/W; bitpos: [19:18]; default: 0;
+         *  Action on PWM0A triggered by event TEB when timer decreasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_dteb: 2;
+        /** gen_dt0 : R/W; bitpos: [21:20]; default: 0;
+         *  Action on PWM0A triggered by event_t0 when timer decreasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_dt0: 2;
+        /** gen_dt1 : R/W; bitpos: [23:22]; default: 0;
+         *  Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low,
+         *  2: high, 3: toggle
+         */
+        uint32_t gen_dt1: 2;
+        uint32_t reserved_24: 8;
+    };
+    uint32_t val;
+} mcpwm_gen_reg_t;
+
+/** Type of dt_cfg register
+ *  PWM generator dead time type selection and configuration
+ */
+typedef union {
+    struct {
+        /** dt_fed_upmethod : R/W; bitpos: [3:0]; default: 0;
+         *  Update method for FED (rising edge delay) active register. 0: immediate, when bit0
+         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+         *  bit3 is set to 1: disable the update
+         */
+        uint32_t dt_fed_upmethod: 4;
+        /** dt_red_upmethod : R/W; bitpos: [7:4]; default: 0;
+         *  Update method for RED (rising edge delay) active register. 0: immediate, when bit0
+         *  is set to 1: tez, when bit1 is set to 1:tep,  when bit2 is set to 1: sync, when
+         *  bit3 is set to 1: disable the update
+         */
+        uint32_t dt_red_upmethod: 4;
+        /** dt_deb_mode : R/W; bitpos: [8]; default: 0;
+         *  S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately,
+         *  1: fed/red take effect on B path, A out is in bypass or dulpB mode
+         */
+        uint32_t dt_deb_mode: 1;
+        /** dt_a_outswap : R/W; bitpos: [9]; default: 0;
+         *  S6 in table
+         */
+        uint32_t dt_a_outswap: 1;
+        /** dt_b_outswap : R/W; bitpos: [10]; default: 0;
+         *  S7 in table
+         */
+        uint32_t dt_b_outswap: 1;
+        /** dt_red_insel : R/W; bitpos: [11]; default: 0;
+         *  S4 in table
+         */
+        uint32_t dt_red_insel: 1;
+        /** dt_fed_insel : R/W; bitpos: [12]; default: 0;
+         *  S5 in table
+         */
+        uint32_t dt_fed_insel: 1;
+        /** dt_red_outinvert : R/W; bitpos: [13]; default: 0;
+         *  S2 in table
+         */
+        uint32_t dt_red_outinvert: 1;
+        /** dt_fed_outinvert : R/W; bitpos: [14]; default: 0;
+         *  S3 in table
+         */
+        uint32_t dt_fed_outinvert: 1;
+        /** dt_a_outbypass : R/W; bitpos: [15]; default: 1;
+         *  S1 in table
+         */
+        uint32_t dt_a_outbypass: 1;
+        /** dt_b_outbypass : R/W; bitpos: [16]; default: 1;
+         *  S0 in table
+         */
+        uint32_t dt_b_outbypass: 1;
+        /** dt_clk_sel : R/W; bitpos: [17]; default: 0;
+         *  Dead time clock selection. 0: PWM_clk, 1: PT_clk
+         */
+        uint32_t dt_clk_sel: 1;
+        uint32_t reserved_18: 14;
+    };
+    uint32_t val;
+} mcpwm_dt_cfg_reg_t;
+
+/** Type of dt_fed_cfg register
+ *  PWM generator shadow register for falling edge delay (FED).
+ */
+typedef union {
+    struct {
+        /** dt_fed : R/W; bitpos: [15:0]; default: 0;
+         *  Shadow register for FED
+         */
+        uint32_t dt_fed: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} mcpwm_dt_fed_cfg_reg_t;
+
+/** Type of dt_red_cfg register
+ *  PWM generator shadow register for rising edge delay (RED).
+ */
+typedef union {
+    struct {
+        /** dt_red : R/W; bitpos: [15:0]; default: 0;
+         *  Shadow register for RED
+         */
+        uint32_t dt_red: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} mcpwm_dt_red_cfg_reg_t;
+
+/** Type of carrier_cfg register
+ *  PWM generator carrier enable and configuration
+ */
+typedef union {
+    struct {
+        /** carrier_en : R/W; bitpos: [0]; default: 0;
+         *  When set, carrier function is enabled. When cleared, carrier is bypassed
+         */
+        uint32_t carrier_en: 1;
+        /** carrier_prescale : R/W; bitpos: [4:1]; default: 0;
+         *  PWM carrier clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk *
+         *  (PWM_CARRIER_PRESCALE + 1)
+         */
+        uint32_t carrier_prescale: 4;
+        /** carrier_duty : R/W; bitpos: [7:5]; default: 0;
+         *  carrier duty selection. Duty = PWM_CARRIER_DUTY / 8
+         */
+        uint32_t carrier_duty: 3;
+        /** carrier_oshtwth : R/W; bitpos: [11:8]; default: 0;
+         *  width of the first pulse in number of periods of the carrier
+         */
+        uint32_t carrier_oshtwth: 4;
+        /** carrier_out_invert : R/W; bitpos: [12]; default: 0;
+         *  when set, invert the output of PWM0A and PWM0B for this submodule
+         */
+        uint32_t carrier_out_invert: 1;
+        /** carrier_in_invert : R/W; bitpos: [13]; default: 0;
+         *  when set, invert the input of PWM0A and PWM0B for this submodule
+         */
+        uint32_t carrier_in_invert: 1;
+        uint32_t reserved_14: 18;
+    };
+    uint32_t val;
+} mcpwm_carrier_cfg_reg_t;
+
+/** Type of fh_cfg0 register
+ *  Actions on PWM0A and PWM0B trip events
+ */
+typedef union {
+    struct {
+        /** fh_sw_cbc : R/W; bitpos: [0]; default: 0;
+         *  Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t fh_sw_cbc: 1;
+        /** fh_f2_cbc : R/W; bitpos: [1]; default: 0;
+         *  fault_event2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t fh_f2_cbc: 1;
+        /** fh_f1_cbc : R/W; bitpos: [2]; default: 0;
+         *  fault_event1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t fh_f1_cbc: 1;
+        /** fh_f0_cbc : R/W; bitpos: [3]; default: 0;
+         *  fault_event0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable
+         */
+        uint32_t fh_f0_cbc: 1;
+        /** fh_sw_ost : R/W; bitpos: [4]; default: 0;
+         *  Enable register for software force one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t fh_sw_ost: 1;
+        /** fh_f2_ost : R/W; bitpos: [5]; default: 0;
+         *  fault_event2 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t fh_f2_ost: 1;
+        /** fh_f1_ost : R/W; bitpos: [6]; default: 0;
+         *  fault_event1 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t fh_f1_ost: 1;
+        /** fh_f0_ost : R/W; bitpos: [7]; default: 0;
+         *  fault_event0 will trigger one-shot mode action. 0: disable, 1: enable
+         */
+        uint32_t fh_f0_ost: 1;
+        /** fh_a_cbc_d : R/W; bitpos: [9:8]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t fh_a_cbc_d: 2;
+        /** fh_a_cbc_u : R/W; bitpos: [11:10]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is
+         *  increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t fh_a_cbc_u: 2;
+        /** fh_a_ost_d : R/W; bitpos: [13:12]; default: 0;
+         *  One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t fh_a_ost_d: 2;
+        /** fh_a_ost_u : R/W; bitpos: [15:14]; default: 0;
+         *  One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t fh_a_ost_u: 2;
+        /** fh_b_cbc_d : R/W; bitpos: [17:16]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+         *  decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t fh_b_cbc_d: 2;
+        /** fh_b_cbc_u : R/W; bitpos: [19:18]; default: 0;
+         *  Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is
+         *  increasing. 0: do nothing,1: force low, 2: force high, 3: toggle
+         */
+        uint32_t fh_b_cbc_u: 2;
+        /** fh_b_ost_d : R/W; bitpos: [21:20]; default: 0;
+         *  One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t fh_b_ost_d: 2;
+        /** fh_b_ost_u : R/W; bitpos: [23:22]; default: 0;
+         *  One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0:
+         *  do nothing, 1: force low, 2: force high, 3: toggle
+         */
+        uint32_t fh_b_ost_u: 2;
+        uint32_t reserved_24: 8;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg0_reg_t;
+
+/** Type of fh_cfg1 register
+ *  Software triggers for fault handler actions
+ */
+typedef union {
+    struct {
+        /** fh_clr_ost : R/W; bitpos: [0]; default: 0;
+         *  a rising edge will clear on going one-shot mode action
+         */
+        uint32_t fh_clr_ost: 1;
+        /** fh_cbcpulse : R/W; bitpos: [2:1]; default: 0;
+         *  cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ,
+         *  when bit1 is set to 1:TEP, when bit0 and bit1 both set to 0: stop refresh, when
+         *  bit0 and bit1 both set to 1: refresh at TEP/TEZ
+         */
+        uint32_t fh_cbcpulse: 2;
+        /** fh_force_cbc : R/W; bitpos: [3]; default: 0;
+         *  a toggle trigger a cycle-by-cycle mode action
+         */
+        uint32_t fh_force_cbc: 1;
+        /** fh_force_ost : R/W; bitpos: [4]; default: 0;
+         *  a toggle (software negate its value) triggers a one-shot mode action
+         */
+        uint32_t fh_force_ost: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} mcpwm_fh_cfg1_reg_t;
+
+/** Type of fh_status register
+ *  Status of fault events.
+ */
+typedef union {
+    struct {
+        /** fh_cbc_on : RO; bitpos: [0]; default: 0;
+         *  Set and reset by hardware. If set, a cycle-by-cycle mode action is on going
+         */
+        uint32_t fh_cbc_on: 1;
+        /** fh_ost_on : RO; bitpos: [1]; default: 0;
+         *  Set and reset by hardware. If set, an one-shot mode action is on going
+         */
+        uint32_t fh_ost_on: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} mcpwm_fh_status_reg_t;
+
+/** Group: Fault Detection Configuration and Status */
+/** Type of fault_detect register
+ *  Fault detection configuration and status
+ */
+typedef union {
+    struct {
+        /** f0_en : R/W; bitpos: [0]; default: 0;
+         *  When set, fault_event0 generation is enabled
+         */
+        uint32_t f0_en: 1;
+        /** f1_en : R/W; bitpos: [1]; default: 0;
+         *  When set, fault_event1 generation is enabled
+         */
+        uint32_t f1_en: 1;
+        /** f2_en : R/W; bitpos: [2]; default: 0;
+         *  When set, fault_event2 generation is enabled
+         */
+        uint32_t f2_en: 1;
+        /** f0_pole : R/W; bitpos: [3]; default: 0;
+         *  Set fault_event0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
+         *  1: level high
+         */
+        uint32_t f0_pole: 1;
+        /** f1_pole : R/W; bitpos: [4]; default: 0;
+         *  Set fault_event1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
+         *  1: level high
+         */
+        uint32_t f1_pole: 1;
+        /** f2_pole : R/W; bitpos: [5]; default: 0;
+         *  Set fault_event2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low,
+         *  1: level high
+         */
+        uint32_t f2_pole: 1;
+        /** event_f0 : RO; bitpos: [6]; default: 0;
+         *  Set and reset by hardware. If set, fault_event0 is on going
+         */
+        uint32_t event_f0: 1;
+        /** event_f1 : RO; bitpos: [7]; default: 0;
+         *  Set and reset by hardware. If set, fault_event1 is on going
+         */
+        uint32_t event_f1: 1;
+        /** event_f2 : RO; bitpos: [8]; default: 0;
+         *  Set and reset by hardware. If set, fault_event2 is on going
+         */
+        uint32_t event_f2: 1;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} mcpwm_fault_detect_reg_t;
+
+
+/** Group: Capture Configuration and Status */
+/** Type of cap_timer_cfg register
+ *  Configure capture timer
+ */
+typedef union {
+    struct {
+        /** cap_timer_en : R/W; bitpos: [0]; default: 0;
+         *  When set, capture timer incrementing under APB_clk is enabled.
+         */
+        uint32_t cap_timer_en: 1;
+        /** cap_synci_en : R/W; bitpos: [1]; default: 0;
+         *  When set, capture timer sync is enabled.
+         */
+        uint32_t cap_synci_en: 1;
+        /** cap_synci_sel : R/W; bitpos: [4:2]; default: 0;
+         *  capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1
+         *  sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix,
+         *  6: SYNC2 from GPIO matrix
+         */
+        uint32_t cap_synci_sel: 3;
+        /** cap_sync_sw : WT; bitpos: [5]; default: 0;
+         *  When reg_cap_synci_en is 1,  write 1 will trigger a capture timer sync, capture
+         *  timer is loaded with value in phase register.
+         */
+        uint32_t cap_sync_sw: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_cfg_reg_t;
+
+/** Type of cap_timer_phase register
+ *  Phase for capture timer sync
+ */
+typedef union {
+    struct {
+        /** cap_timer_phase : R/W; bitpos: [31:0]; default: 0;
+         *  Phase value for capture timer sync operation.
+         */
+        uint32_t cap_timer_phase: 32;
+    };
+    uint32_t val;
+} mcpwm_cap_timer_phase_reg_t;
+
+/** Type of cap_chn_cfg register
+ *  Capture channel 0 configuration and enable
+ */
+typedef union {
+    struct {
+        /** capn_en : R/W; bitpos: [0]; default: 0;
+         *  When set, capture on channel 0 is enabled
+         */
+        uint32_t capn_en: 1;
+        /** capn_mode : R/W; bitpos: [2:1]; default: 0;
+         *  Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
+         *  capture on the negative edge, When bit1 is set to 1: enable capture on the positive
+         *  edge.
+         */
+        uint32_t capn_mode: 2;
+        /** capn_prescale : R/W; bitpos: [10:3]; default: 0;
+         *  Value of prescaling on positive edge of CAPn. Prescale value = PWM_CAPn_PRESCALE +
+         *  1
+         */
+        uint32_t capn_prescale: 8;
+        /** capn_in_invert : R/W; bitpos: [11]; default: 0;
+         *  when set, CAPn form GPIO matrix is inverted before prescale
+         */
+        uint32_t capn_in_invert: 1;
+        /** capn_sw : WT; bitpos: [12]; default: 0;
+         *  Write 1 will trigger a software forced capture on channel 0
+         */
+        uint32_t capn_sw: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_cfg_reg_t;
+
+/** Type of cap_chn register
+ *  chn capture value status register
+ */
+typedef union {
+    struct {
+        /** capn_value : RO; bitpos: [31:0]; default: 0;
+         *  Value of last capture on channel n
+         */
+        uint32_t capn_value: 32;
+    };
+    uint32_t val;
+} mcpwm_cap_chn_reg_t;
+
+/** Type of cap_status register
+ *  Edge of last capture trigger
+ */
+typedef union {
+    struct {
+        /** cap0_edge : RO; bitpos: [0]; default: 0;
+         *  Edge of last capture trigger on channel 0, 0: posedge, 1: negedge
+         */
+        uint32_t cap0_edge: 1;
+        /** cap1_edge : RO; bitpos: [1]; default: 0;
+         *  Edge of last capture trigger on channel 1, 0: posedge, 1: negedge
+         */
+        uint32_t cap1_edge: 1;
+        /** cap2_edge : RO; bitpos: [2]; default: 0;
+         *  Edge of last capture trigger on channel 2, 0: posedge, 1: negedge
+         */
+        uint32_t cap2_edge: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} mcpwm_cap_status_reg_t;
+
+
+/** Group: Enable update of active registers */
+/** Type of update_cfg register
+ *  Enable update.
+ */
+typedef union {
+    struct {
+        /** global_up_en : R/W; bitpos: [0]; default: 1;
+         *  The global enable of update of all active registers in MCPWM module
+         */
+        uint32_t global_up_en: 1;
+        /** global_force_up : R/W; bitpos: [1]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of all active
+         *  registers in MCPWM module
+         */
+        uint32_t global_force_up: 1;
+        /** op0_up_en : R/W; bitpos: [2]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0
+         *  are enabled
+         */
+        uint32_t op0_up_en: 1;
+        /** op0_force_up : R/W; bitpos: [3]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 0
+         */
+        uint32_t op0_force_up: 1;
+        /** op1_up_en : R/W; bitpos: [4]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1
+         *  are enabled
+         */
+        uint32_t op1_up_en: 1;
+        /** op1_force_up : R/W; bitpos: [5]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 1
+         */
+        uint32_t op1_force_up: 1;
+        /** op2_up_en : R/W; bitpos: [6]; default: 1;
+         *  When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2
+         *  are enabled
+         */
+        uint32_t op2_up_en: 1;
+        /** op2_force_up : R/W; bitpos: [7]; default: 0;
+         *  a toggle (software invert its value) will trigger a forced update of active
+         *  registers in PWM operator 2
+         */
+        uint32_t op2_force_up: 1;
+        uint32_t reserved_8: 24;
+    };
+    uint32_t val;
+} mcpwm_update_cfg_reg_t;
+
+
+/** Group: Manage Interrupts */
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_ena: 1;
+        /** timer1_stop_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_ena: 1;
+        /** timer2_stop_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The enable bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_ena: 1;
+        /** timer0_tez_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_ena: 1;
+        /** timer1_tez_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_ena: 1;
+        /** timer2_tez_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_ena: 1;
+        /** timer0_tep_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_ena: 1;
+        /** timer1_tep_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_ena: 1;
+        /** timer2_tep_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_ena: 1;
+        /** fault0_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The enable bit for the interrupt triggered when fault_event0 starts.
+         */
+        uint32_t fault0_int_ena: 1;
+        /** fault1_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The enable bit for the interrupt triggered when fault_event1 starts.
+         */
+        uint32_t fault1_int_ena: 1;
+        /** fault2_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The enable bit for the interrupt triggered when fault_event2 starts.
+         */
+        uint32_t fault2_int_ena: 1;
+        /** fault0_clr_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The enable bit for the interrupt triggered when fault_event0 ends.
+         */
+        uint32_t fault0_clr_int_ena: 1;
+        /** fault1_clr_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The enable bit for the interrupt triggered when fault_event1 ends.
+         */
+        uint32_t fault1_clr_int_ena: 1;
+        /** fault2_clr_int_ena : R/W; bitpos: [14]; default: 0;
+         *  The enable bit for the interrupt triggered when fault_event2 ends.
+         */
+        uint32_t fault2_clr_int_ena: 1;
+        /** op0_tea_int_ena : R/W; bitpos: [15]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t op0_tea_int_ena: 1;
+        /** op1_tea_int_ena : R/W; bitpos: [16]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t op1_tea_int_ena: 1;
+        /** op2_tea_int_ena : R/W; bitpos: [17]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t op2_tea_int_ena: 1;
+        /** op0_teb_int_ena : R/W; bitpos: [18]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t op0_teb_int_ena: 1;
+        /** op1_teb_int_ena : R/W; bitpos: [19]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t op1_teb_int_ena: 1;
+        /** op2_teb_int_ena : R/W; bitpos: [20]; default: 0;
+         *  The enable bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t op2_teb_int_ena: 1;
+        /** fh0_cbc_int_ena : R/W; bitpos: [21]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.
+         */
+        uint32_t fh0_cbc_int_ena: 1;
+        /** fh1_cbc_int_ena : R/W; bitpos: [22]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.
+         */
+        uint32_t fh1_cbc_int_ena: 1;
+        /** fh2_cbc_int_ena : R/W; bitpos: [23]; default: 0;
+         *  The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.
+         */
+        uint32_t fh2_cbc_int_ena: 1;
+        /** fh0_ost_int_ena : R/W; bitpos: [24]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t fh0_ost_int_ena: 1;
+        /** fh1_ost_int_ena : R/W; bitpos: [25]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t fh1_ost_int_ena: 1;
+        /** fh2_ost_int_ena : R/W; bitpos: [26]; default: 0;
+         *  The enable bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t fh2_ost_int_ena: 1;
+        /** cap0_int_ena : R/W; bitpos: [27]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_ena: 1;
+        /** cap1_int_ena : R/W; bitpos: [28]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_ena: 1;
+        /** cap2_int_ena : R/W; bitpos: [29]; default: 0;
+         *  The enable bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_ena: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} mcpwm_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_raw: 1;
+        /** timer1_stop_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_raw: 1;
+        /** timer2_stop_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw status bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_raw: 1;
+        /** timer0_tez_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_raw: 1;
+        /** timer1_tez_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_raw: 1;
+        /** timer2_tez_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_raw: 1;
+        /** timer0_tep_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_raw: 1;
+        /** timer1_tep_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_raw: 1;
+        /** timer2_tep_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_raw: 1;
+        /** fault0_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw status bit for the interrupt triggered when fault_event0 starts.
+         */
+        uint32_t fault0_int_raw: 1;
+        /** fault1_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw status bit for the interrupt triggered when fault_event1 starts.
+         */
+        uint32_t fault1_int_raw: 1;
+        /** fault2_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw status bit for the interrupt triggered when fault_event2 starts.
+         */
+        uint32_t fault2_int_raw: 1;
+        /** fault0_clr_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw status bit for the interrupt triggered when fault_event0 ends.
+         */
+        uint32_t fault0_clr_int_raw: 1;
+        /** fault1_clr_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw status bit for the interrupt triggered when fault_event1 ends.
+         */
+        uint32_t fault1_clr_int_raw: 1;
+        /** fault2_clr_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw status bit for the interrupt triggered when fault_event2 ends.
+         */
+        uint32_t fault2_clr_int_raw: 1;
+        /** op0_tea_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t op0_tea_int_raw: 1;
+        /** op1_tea_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t op1_tea_int_raw: 1;
+        /** op2_tea_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t op2_tea_int_raw: 1;
+        /** op0_teb_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t op0_teb_int_raw: 1;
+        /** op1_teb_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t op1_teb_int_raw: 1;
+        /** op2_teb_int_raw : R/WTC/SS; bitpos: [20]; default: 0;
+         *  The raw status bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t op2_teb_int_raw: 1;
+        /** fh0_cbc_int_raw : R/WTC/SS; bitpos: [21]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM0.
+         */
+        uint32_t fh0_cbc_int_raw: 1;
+        /** fh1_cbc_int_raw : R/WTC/SS; bitpos: [22]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM1.
+         */
+        uint32_t fh1_cbc_int_raw: 1;
+        /** fh2_cbc_int_raw : R/WTC/SS; bitpos: [23]; default: 0;
+         *  The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM2.
+         */
+        uint32_t fh2_cbc_int_raw: 1;
+        /** fh0_ost_int_raw : R/WTC/SS; bitpos: [24]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t fh0_ost_int_raw: 1;
+        /** fh1_ost_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t fh1_ost_int_raw: 1;
+        /** fh2_ost_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  The raw status bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t fh2_ost_int_raw: 1;
+        /** cap0_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_raw: 1;
+        /** cap1_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_raw: 1;
+        /** cap2_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  The raw status bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_raw: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} mcpwm_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_st: 1;
+        /** timer1_stop_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_st: 1;
+        /** timer2_stop_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked status bit for the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_st: 1;
+        /** timer0_tez_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_st: 1;
+        /** timer1_tez_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_st: 1;
+        /** timer2_tez_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_st: 1;
+        /** timer0_tep_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_st: 1;
+        /** timer1_tep_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_st: 1;
+        /** timer2_tep_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_st: 1;
+        /** fault0_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked status bit for the interrupt triggered when fault_event0 starts.
+         */
+        uint32_t fault0_int_st: 1;
+        /** fault1_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked status bit for the interrupt triggered when fault_event1 starts.
+         */
+        uint32_t fault1_int_st: 1;
+        /** fault2_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked status bit for the interrupt triggered when fault_event2 starts.
+         */
+        uint32_t fault2_int_st: 1;
+        /** fault0_clr_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked status bit for the interrupt triggered when fault_event0 ends.
+         */
+        uint32_t fault0_clr_int_st: 1;
+        /** fault1_clr_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked status bit for the interrupt triggered when fault_event1 ends.
+         */
+        uint32_t fault1_clr_int_st: 1;
+        /** fault2_clr_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked status bit for the interrupt triggered when fault_event2 ends.
+         */
+        uint32_t fault2_clr_int_st: 1;
+        /** op0_tea_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t op0_tea_int_st: 1;
+        /** op1_tea_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t op1_tea_int_st: 1;
+        /** op2_tea_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t op2_tea_int_st: 1;
+        /** op0_teb_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t op0_teb_int_st: 1;
+        /** op1_teb_int_st : RO; bitpos: [19]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t op1_teb_int_st: 1;
+        /** op2_teb_int_st : RO; bitpos: [20]; default: 0;
+         *  The masked status bit for the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t op2_teb_int_st: 1;
+        /** fh0_cbc_int_st : RO; bitpos: [21]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM0.
+         */
+        uint32_t fh0_cbc_int_st: 1;
+        /** fh1_cbc_int_st : RO; bitpos: [22]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM1.
+         */
+        uint32_t fh1_cbc_int_st: 1;
+        /** fh2_cbc_int_st : RO; bitpos: [23]; default: 0;
+         *  The masked status bit for the interrupt triggered by a cycle-by-cycle mode action
+         *  on PWM2.
+         */
+        uint32_t fh2_cbc_int_st: 1;
+        /** fh0_ost_int_st : RO; bitpos: [24]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t fh0_ost_int_st: 1;
+        /** fh1_ost_int_st : RO; bitpos: [25]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t fh1_ost_int_st: 1;
+        /** fh2_ost_int_st : RO; bitpos: [26]; default: 0;
+         *  The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t fh2_ost_int_st: 1;
+        /** cap0_int_st : RO; bitpos: [27]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_st: 1;
+        /** cap1_int_st : RO; bitpos: [28]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_st: 1;
+        /** cap2_int_st : RO; bitpos: [29]; default: 0;
+         *  The masked status bit for the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_st: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} mcpwm_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** timer0_stop_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 0 stops.
+         */
+        uint32_t timer0_stop_int_clr: 1;
+        /** timer1_stop_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 1 stops.
+         */
+        uint32_t timer1_stop_int_clr: 1;
+        /** timer2_stop_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the interrupt triggered when the timer 2 stops.
+         */
+        uint32_t timer2_stop_int_clr: 1;
+        /** timer0_tez_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.
+         */
+        uint32_t timer0_tez_int_clr: 1;
+        /** timer1_tez_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.
+         */
+        uint32_t timer1_tez_int_clr: 1;
+        /** timer2_tez_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.
+         */
+        uint32_t timer2_tez_int_clr: 1;
+        /** timer0_tep_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.
+         */
+        uint32_t timer0_tep_int_clr: 1;
+        /** timer1_tep_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.
+         */
+        uint32_t timer1_tep_int_clr: 1;
+        /** timer2_tep_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.
+         */
+        uint32_t timer2_tep_int_clr: 1;
+        /** fault0_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the interrupt triggered when fault_event0 starts.
+         */
+        uint32_t fault0_int_clr: 1;
+        /** fault1_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the interrupt triggered when fault_event1 starts.
+         */
+        uint32_t fault1_int_clr: 1;
+        /** fault2_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the interrupt triggered when fault_event2 starts.
+         */
+        uint32_t fault2_int_clr: 1;
+        /** fault0_clr_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the interrupt triggered when fault_event0 ends.
+         */
+        uint32_t fault0_clr_int_clr: 1;
+        /** fault1_clr_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the interrupt triggered when fault_event1 ends.
+         */
+        uint32_t fault1_clr_int_clr: 1;
+        /** fault2_clr_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the interrupt triggered when fault_event2 ends.
+         */
+        uint32_t fault2_clr_int_clr: 1;
+        /** op0_tea_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event
+         */
+        uint32_t op0_tea_int_clr: 1;
+        /** op1_tea_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event
+         */
+        uint32_t op1_tea_int_clr: 1;
+        /** op2_tea_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event
+         */
+        uint32_t op2_tea_int_clr: 1;
+        /** op0_teb_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event
+         */
+        uint32_t op0_teb_int_clr: 1;
+        /** op1_teb_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event
+         */
+        uint32_t op1_teb_int_clr: 1;
+        /** op2_teb_int_clr : WT; bitpos: [20]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event
+         */
+        uint32_t op2_teb_int_clr: 1;
+        /** fh0_cbc_int_clr : WT; bitpos: [21]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM0.
+         */
+        uint32_t fh0_cbc_int_clr: 1;
+        /** fh1_cbc_int_clr : WT; bitpos: [22]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM1.
+         */
+        uint32_t fh1_cbc_int_clr: 1;
+        /** fh2_cbc_int_clr : WT; bitpos: [23]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on
+         *  PWM2.
+         */
+        uint32_t fh2_cbc_int_clr: 1;
+        /** fh0_ost_int_clr : WT; bitpos: [24]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.
+         */
+        uint32_t fh0_ost_int_clr: 1;
+        /** fh1_ost_int_clr : WT; bitpos: [25]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.
+         */
+        uint32_t fh1_ost_int_clr: 1;
+        /** fh2_ost_int_clr : WT; bitpos: [26]; default: 0;
+         *  Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.
+         */
+        uint32_t fh2_ost_int_clr: 1;
+        /** cap0_int_clr : WT; bitpos: [27]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 0.
+         */
+        uint32_t cap0_int_clr: 1;
+        /** cap1_int_clr : WT; bitpos: [28]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 1.
+         */
+        uint32_t cap1_int_clr: 1;
+        /** cap2_int_clr : WT; bitpos: [29]; default: 0;
+         *  Set this bit to clear the interrupt triggered by capture on channel 2.
+         */
+        uint32_t cap2_int_clr: 1;
+        uint32_t reserved_30: 2;
+    };
+    uint32_t val;
+} mcpwm_int_clr_reg_t;
+
+
+/** Group: MCMCPWM APB configuration register */
+/** Type of clk register
+ *  MCPWM APB configuration register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} mcpwm_clk_reg_t;
+
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 34632240;
+         *  Version of this register file
+         */
+        uint32_t date: 28;
+        uint32_t reserved_28: 4;
+    };
+    uint32_t val;
+} mcpwm_version_reg_t;
+
+
+typedef struct {
+    mcpwm_timer_cfg0_reg_t timer_cfg0;
+    mcpwm_timer_cfg1_reg_t timer_cfg1;
+    mcpwm_timer_sync_reg_t timer_sync;
+    mcpwm_timer_status_reg_t timer_status;
+} mcpwm_timer_regs_t;
+
+typedef struct {
+    mcpwm_gen_stmp_cfg_reg_t gen_stmp_cfg;
+    mcpwm_gen_tstmp_reg_t timestamp[2];
+    mcpwm_gen_cfg0_reg_t gen_cfg0;
+    mcpwm_gen_force_reg_t gen_force;
+    mcpwm_gen_reg_t generator[2];
+    mcpwm_dt_cfg_reg_t dt_cfg;
+    mcpwm_dt_fed_cfg_reg_t dt_fed_cfg;
+    mcpwm_dt_red_cfg_reg_t dt_red_cfg;
+    mcpwm_carrier_cfg_reg_t carrier_cfg;
+    mcpwm_fh_cfg0_reg_t fh_cfg0;
+    mcpwm_fh_cfg1_reg_t fh_cfg1;
+    mcpwm_fh_status_reg_t fh_status;
+} mcpwm_operator_reg_t;
+
+typedef struct mcpwm_dev_t {
+    volatile mcpwm_clk_cfg_reg_t clk_cfg;
+    volatile mcpwm_timer_regs_t timer[3];
+    volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
+    volatile mcpwm_operator_timersel_reg_t operator_timersel;
+    volatile mcpwm_operator_reg_t operators[3];
+    volatile mcpwm_fault_detect_reg_t fault_detect;
+    volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
+    volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
+    volatile mcpwm_cap_chn_cfg_reg_t cap_chn_cfg[3];
+    volatile mcpwm_cap_chn_reg_t cap_chn[3];
+    volatile mcpwm_cap_status_reg_t cap_status;
+    volatile mcpwm_update_cfg_reg_t update_cfg;
+    volatile mcpwm_int_ena_reg_t int_ena;
+    volatile mcpwm_int_raw_reg_t int_raw;
+    volatile mcpwm_int_st_reg_t int_st;
+    volatile mcpwm_int_clr_reg_t int_clr;
+    volatile mcpwm_clk_reg_t clk;
+    volatile mcpwm_version_reg_t version;
+} mcpwm_dev_t;
+
+extern mcpwm_dev_t MCPWM0;
+extern mcpwm_dev_t MCPWM1;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(mcpwm_dev_t) == 0x128, "Invalid size of mcpwm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/include/soc/pcnt_reg.h b/components/soc/esp32s3/register/soc/pcnt_reg.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/pcnt_reg.h
rename to components/soc/esp32s3/register/soc/pcnt_reg.h
diff --git a/components/soc/esp32s3/include/soc/pcnt_struct.h b/components/soc/esp32s3/register/soc/pcnt_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/pcnt_struct.h
rename to components/soc/esp32s3/register/soc/pcnt_struct.h
diff --git a/components/soc/esp32s3/include/soc/peri_backup_reg.h b/components/soc/esp32s3/register/soc/peri_backup_reg.h
similarity index 92%
rename from components/soc/esp32s3/include/soc/peri_backup_reg.h
rename to components/soc/esp32s3/register/soc/peri_backup_reg.h
index 71907355b0c..b627104fc3b 100644
--- a/components/soc/esp32s3/include/soc/peri_backup_reg.h
+++ b/components/soc/esp32s3/register/soc/peri_backup_reg.h
@@ -1,21 +1,13 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_PERI_BACKUP_REG_H_
 #define _SOC_PERI_BACKUP_REG_H_
 
 
-#include "soc.h"
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32s3/include/soc/peri_backup_struct.h b/components/soc/esp32s3/register/soc/peri_backup_struct.h
similarity index 85%
rename from components/soc/esp32s3/include/soc/peri_backup_struct.h
rename to components/soc/esp32s3/register/soc/peri_backup_struct.h
index 20d6673f2ec..bc0563f7156 100644
--- a/components/soc/esp32s3/include/soc/peri_backup_struct.h
+++ b/components/soc/esp32s3/register/soc/peri_backup_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_PERI_BACKUP_STRUCT_H_
 #define _SOC_PERI_BACKUP_STRUCT_H_
 
diff --git a/components/soc/esp32s3/include/soc/reg_base.h b/components/soc/esp32s3/register/soc/reg_base.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/reg_base.h
rename to components/soc/esp32s3/register/soc/reg_base.h
diff --git a/components/soc/esp32s3/include/soc/rmt_reg.h b/components/soc/esp32s3/register/soc/rmt_reg.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/rmt_reg.h
rename to components/soc/esp32s3/register/soc/rmt_reg.h
diff --git a/components/soc/esp32s3/include/soc/rmt_struct.h b/components/soc/esp32s3/register/soc/rmt_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/rmt_struct.h
rename to components/soc/esp32s3/register/soc/rmt_struct.h
diff --git a/components/soc/esp32s3/register/soc/rtc_cntl_reg.h b/components/soc/esp32s3/register/soc/rtc_cntl_reg.h
new file mode 100644
index 00000000000..5a1fa823249
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/rtc_cntl_reg.h
@@ -0,0 +1,3702 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_RTC_CNTL_REG_H_
+#define _SOC_RTC_CNTL_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG to write-enable the wdt registers */
+#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
+
+#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
+#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
+
+#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0)
+/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: SW system reset.*/
+#define RTC_CNTL_SW_SYS_RST    (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_V  0x1
+#define RTC_CNTL_SW_SYS_RST_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force no reset in deep sleep.*/
+#define RTC_CNTL_DG_WRAP_FORCE_NORST    (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
+/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: digital wrap force reset in deep sleep.*/
+#define RTC_CNTL_DG_WRAP_FORCE_RST    (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
+/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: .*/
+#define RTC_CNTL_ANALOG_FORCE_NOISO    (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
+/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: .*/
+#define RTC_CNTL_PLL_FORCE_NOISO    (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_M  (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_PLL_FORCE_NOISO_S  27
+/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
+/*description: .*/
+#define RTC_CNTL_XTL_FORCE_NOISO    (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_M  (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_XTL_FORCE_NOISO_S  26
+/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_ANALOG_FORCE_ISO    (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
+/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_PLL_FORCE_ISO    (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_M  (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_V  0x1
+#define RTC_CNTL_PLL_FORCE_ISO_S  24
+/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_XTL_FORCE_ISO    (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_M  (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_V  0x1
+#define RTC_CNTL_XTL_FORCE_ISO_S  23
+/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */
+/*description: wait bias_sleep and current source wakeup.*/
+#define RTC_CNTL_XTL_EN_WAIT    0x0000000F
+#define RTC_CNTL_XTL_EN_WAIT_M  ((RTC_CNTL_XTL_EN_WAIT_V)<<(RTC_CNTL_XTL_EN_WAIT_S))
+#define RTC_CNTL_XTL_EN_WAIT_V  0xF
+#define RTC_CNTL_XTL_EN_WAIT_S  14
+/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
+/*description: crystall force power up.*/
+#define RTC_CNTL_XTL_FORCE_PU    (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_V  0x1
+#define RTC_CNTL_XTL_FORCE_PU_S  13
+/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: crystall force power down.*/
+#define RTC_CNTL_XTL_FORCE_PD    (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_V  0x1
+#define RTC_CNTL_XTL_FORCE_PD_S  12
+/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: BB_PLL force power up.*/
+#define RTC_CNTL_BBPLL_FORCE_PU    (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PU_S  11
+/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: BB_PLL force power down.*/
+#define RTC_CNTL_BBPLL_FORCE_PD    (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PD_S  10
+/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: BB_PLL_I2C force power up.*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU    (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
+/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: BB_PLL _I2C force power down.*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD    (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
+/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: BB_I2C force power up.*/
+#define RTC_CNTL_BB_I2C_FORCE_PU    (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
+/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: BB_I2C force power down.*/
+#define RTC_CNTL_BB_I2C_FORCE_PD    (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
+/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: PRO CPU SW reset.*/
+#define RTC_CNTL_SW_PROCPU_RST    (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_V  0x1
+#define RTC_CNTL_SW_PROCPU_RST_S  5
+/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: APP CPU SW reset.*/
+#define RTC_CNTL_SW_APPCPU_RST    (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_M  (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_V  0x1
+#define RTC_CNTL_SW_APPCPU_RST_S  4
+/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall P
+RO CPU.*/
+#define RTC_CNTL_SW_STALL_PROCPU_C0    0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
+/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall A
+PP CPU.*/
+#define RTC_CNTL_SW_STALL_APPCPU_C0    0x00000003
+#define RTC_CNTL_SW_STALL_APPCPU_C0_M  ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_APPCPU_C0_S  0
+
+#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x4)
+/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define RTC_CNTL_SLP_VAL_LO    0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
+#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_S  0
+
+#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x8)
+/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */
+/*description: timer alarm enable bit.*/
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN    (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
+/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC sleep timer high 16 bits.*/
+#define RTC_CNTL_SLP_VAL_HI    0x0000FFFF
+#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
+#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
+#define RTC_CNTL_SLP_VAL_HI_S  0
+
+#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0xC)
+/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Set 1: to update register with RTC timer.*/
+#define RTC_CNTL_TIME_UPDATE    (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_V  0x1
+#define RTC_CNTL_TIME_UPDATE_S  31
+/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: enable to record system reset time.*/
+#define RTC_CNTL_TIMER_SYS_RST    (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_V  0x1
+#define RTC_CNTL_TIMER_SYS_RST_S  29
+/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Enable to record 40M XTAL OFF time.*/
+#define RTC_CNTL_TIMER_XTL_OFF    (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
+#define RTC_CNTL_TIMER_XTL_OFF_S  28
+/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable to record system stall time.*/
+#define RTC_CNTL_TIMER_SYS_STALL    (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
+#define RTC_CNTL_TIMER_SYS_STALL_S  27
+
+#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x10)
+/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits.*/
+#define RTC_CNTL_TIMER_VALUE0_LOW    0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
+#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x14)
+/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits.*/
+#define RTC_CNTL_TIMER_VALUE0_HIGH    0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
+
+#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x18)
+/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: sleep enable bit.*/
+#define RTC_CNTL_SLEEP_EN    (BIT(31))
+#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_V  0x1
+#define RTC_CNTL_SLEEP_EN_S  31
+/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: leep reject bit.*/
+#define RTC_CNTL_SLP_REJECT    (BIT(30))
+#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_V  0x1
+#define RTC_CNTL_SLP_REJECT_S  30
+/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: leep wakeup bit.*/
+#define RTC_CNTL_SLP_WAKEUP    (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_S  29
+/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: SDIO active indication.*/
+#define RTC_CNTL_SDIO_ACTIVE_IND    (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
+#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
+/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: APB to RTC using bridge.*/
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL    (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
+/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear rtc sleep reject cause.*/
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
+/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rtc software interrupt to main cpu.*/
+#define RTC_CNTL_SW_CPU_INT    (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_V  0x1
+#define RTC_CNTL_SW_CPU_INT_S  0
+
+#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x1C)
+/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
+/*description: PLL wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_PLL_BUF_WAIT    0x000000FF
+#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
+#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
+#define RTC_CNTL_PLL_BUF_WAIT_S  24
+/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
+/*description: XTAL wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_XTL_BUF_WAIT    0x000003FF
+#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
+#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
+#define RTC_CNTL_XTL_BUF_WAIT_S  14
+/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
+/*description: CK8M wait cycles in slow_clk_rtc.*/
+#define RTC_CNTL_CK8M_WAIT    0x000000FF
+#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
+#define RTC_CNTL_CK8M_WAIT_V  0xFF
+#define RTC_CNTL_CK8M_WAIT_S  6
+/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
+/*description: CPU stall wait cycles in fast_clk_rtc.*/
+#define RTC_CNTL_CPU_STALL_WAIT    0x0000001F
+#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
+#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
+#define RTC_CNTL_CPU_STALL_WAIT_S  1
+/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: CPU stall enable bit.*/
+#define RTC_CNTL_CPU_STALL_EN    (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_V  0x1
+#define RTC_CNTL_CPU_STALL_EN_S  0
+
+#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x20)
+/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
+/*description: minimal cycles in slow_clk_rtc for CK8M in power down state.*/
+#define RTC_CNTL_MIN_TIME_CK8M_OFF    0x000000FF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
+/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */
+/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to w
+ork.*/
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT    0x000001FF
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M  ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S))
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V  0x1FF
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S  15
+
+#define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x24)
+/* RTC_CNTL_BT_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */
+/*description: .*/
+#define RTC_CNTL_BT_POWERUP_TIMER    0x0000007F
+#define RTC_CNTL_BT_POWERUP_TIMER_M  ((RTC_CNTL_BT_POWERUP_TIMER_V)<<(RTC_CNTL_BT_POWERUP_TIMER_S))
+#define RTC_CNTL_BT_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_BT_POWERUP_TIMER_S  25
+/* RTC_CNTL_BT_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */
+/*description: .*/
+#define RTC_CNTL_BT_WAIT_TIMER    0x000001FF
+#define RTC_CNTL_BT_WAIT_TIMER_M  ((RTC_CNTL_BT_WAIT_TIMER_V)<<(RTC_CNTL_BT_WAIT_TIMER_S))
+#define RTC_CNTL_BT_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_BT_WAIT_TIMER_S  16
+/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: .*/
+#define RTC_CNTL_WIFI_POWERUP_TIMER    0x0000007F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_M  ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
+#define RTC_CNTL_WIFI_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_S  9
+/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: .*/
+#define RTC_CNTL_WIFI_WAIT_TIMER    0x000001FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_M  ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
+#define RTC_CNTL_WIFI_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_S  0
+
+#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x28)
+/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: .*/
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER    0x0000007F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: .*/
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER    0x000001FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
+/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: .*/
+#define RTC_CNTL_POWERUP_TIMER    0x0000007F
+#define RTC_CNTL_POWERUP_TIMER_M  ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S))
+#define RTC_CNTL_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_POWERUP_TIMER_S  9
+/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: .*/
+#define RTC_CNTL_WAIT_TIMER    0x000001FF
+#define RTC_CNTL_WAIT_TIMER_M  ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S))
+#define RTC_CNTL_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_WAIT_TIMER_S  0
+
+#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x2C)
+/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
+/*description: minimal sleep cycles in slow_clk_rtc.*/
+#define RTC_CNTL_MIN_SLP_VAL    0x000000FF
+#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
+#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
+#define RTC_CNTL_MIN_SLP_VAL_S  8
+
+#define RTC_CNTL_TIMER6_REG          (DR_REG_RTCCNTL_BASE + 0x30)
+/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: .*/
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER    0x0000007F
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M  ((RTC_CNTL_DG_PERI_POWERUP_TIMER_V)<<(RTC_CNTL_DG_PERI_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: .*/
+#define RTC_CNTL_DG_PERI_WAIT_TIMER    0x000001FF
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_M  ((RTC_CNTL_DG_PERI_WAIT_TIMER_V)<<(RTC_CNTL_DG_PERI_WAIT_TIMER_S))
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_PERI_WAIT_TIMER_S  16
+/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: .*/
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER    0x0000007F
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M  ((RTC_CNTL_CPU_TOP_POWERUP_TIMER_V)<<(RTC_CNTL_CPU_TOP_POWERUP_TIMER_S))
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S  9
+/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: .*/
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER    0x000001FF
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M  ((RTC_CNTL_CPU_TOP_WAIT_TIMER_V)<<(RTC_CNTL_CPU_TOP_WAIT_TIMER_S))
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S  0
+
+#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x34)
+/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_PLL_I2C_PU    (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_V  0x1
+#define RTC_CNTL_PLL_I2C_PU_S  31
+/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: CKGEN_I2C power up.*/
+#define RTC_CNTL_CKGEN_I2C_PU    (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
+#define RTC_CNTL_CKGEN_I2C_PU_S  30
+/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: 1: RFRX_PBUS power up.*/
+#define RTC_CNTL_RFRX_PBUS_PU    (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
+#define RTC_CNTL_RFRX_PBUS_PU_S  28
+/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: TXRF_I2C power up.*/
+#define RTC_CNTL_TXRF_I2C_PU    (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_V  0x1
+#define RTC_CNTL_TXRF_I2C_PU_S  27
+/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: PVTMON power up.*/
+#define RTC_CNTL_PVTMON_PU    (BIT(26))
+#define RTC_CNTL_PVTMON_PU_M  (BIT(26))
+#define RTC_CNTL_PVTMON_PU_V  0x1
+#define RTC_CNTL_PVTMON_PU_S  26
+/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: start BBPLL calibration during sleep.*/
+#define RTC_CNTL_BBPLL_CAL_SLP_START    (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
+/* RTC_CNTL_ANALOG_TOP_ISO_MONITOR : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: PLLA force power up.*/
+#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR    (BIT(24))
+#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_M  (BIT(24))
+#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V  0x1
+#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S  24
+/* RTC_CNTL_ANALOG_TOP_ISO_SLEEP : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: PLLA force power down.*/
+#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP    (BIT(23))
+#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_M  (BIT(23))
+#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V  0x1
+#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S  23
+/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: PLLA force power up.*/
+#define RTC_CNTL_SAR_I2C_PU    (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_M  (BIT(22))
+#define RTC_CNTL_SAR_I2C_PU_V  0x1
+#define RTC_CNTL_SAR_I2C_PU_S  22
+/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_GLITCH_RST_EN    (BIT(20))
+#define RTC_CNTL_GLITCH_RST_EN_M  (BIT(20))
+#define RTC_CNTL_GLITCH_RST_EN_V  0x1
+#define RTC_CNTL_GLITCH_RST_EN_S  20
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU    (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M  (BIT(19))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S  19
+/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: .*/
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD    (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M  (BIT(18))
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V  0x1
+#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S  18
+
+#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x38)
+/* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_PRO_DRESET_MASK    (BIT(25))
+#define RTC_CNTL_PRO_DRESET_MASK_M  (BIT(25))
+#define RTC_CNTL_PRO_DRESET_MASK_V  0x1
+#define RTC_CNTL_PRO_DRESET_MASK_S  25
+/* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_APP_DRESET_MASK    (BIT(24))
+#define RTC_CNTL_APP_DRESET_MASK_M  (BIT(24))
+#define RTC_CNTL_APP_DRESET_MASK_V  0x1
+#define RTC_CNTL_APP_DRESET_MASK_S  24
+/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR    (BIT(23))
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M  (BIT(23))
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V  0x1
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S  23
+/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR    (BIT(22))
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M  (BIT(22))
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V  0x1
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S  22
+/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU    (BIT(21))
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M  (BIT(21))
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V  0x1
+#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S  21
+/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU    (BIT(20))
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M  (BIT(20))
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V  0x1
+#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S  20
+/* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: PROCPU OcdHaltOnReset.*/
+#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET    (BIT(19))
+#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M  (BIT(19))
+#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V  0x1
+#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S  19
+/* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: APPCPU OcdHaltOnReset.*/
+#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET    (BIT(18))
+#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M  (BIT(18))
+#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V  0x1
+#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S  18
+/* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: clear APP CPU reset flag.*/
+#define RTC_CNTL_RESET_FLAG_APPCPU_CLR    (BIT(17))
+#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M  (BIT(17))
+#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V  0x1
+#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S  17
+/* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: clear PRO CPU reset_flag.*/
+#define RTC_CNTL_RESET_FLAG_PROCPU_CLR    (BIT(16))
+#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M  (BIT(16))
+#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V  0x1
+#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S  16
+/* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: APP CPU reset flag.*/
+#define RTC_CNTL_RESET_FLAG_APPCPU    (BIT(15))
+#define RTC_CNTL_RESET_FLAG_APPCPU_M  (BIT(15))
+#define RTC_CNTL_RESET_FLAG_APPCPU_V  0x1
+#define RTC_CNTL_RESET_FLAG_APPCPU_S  15
+/* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: PRO CPU reset_flag.*/
+#define RTC_CNTL_RESET_FLAG_PROCPU    (BIT(14))
+#define RTC_CNTL_RESET_FLAG_PROCPU_M  (BIT(14))
+#define RTC_CNTL_RESET_FLAG_PROCPU_V  0x1
+#define RTC_CNTL_RESET_FLAG_PROCPU_S  14
+/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: PRO CPU state vector sel.*/
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL    (BIT(13))
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M  (BIT(13))
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V  0x1
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S  13
+/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: APP CPU state vector sel.*/
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL    (BIT(12))
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M  (BIT(12))
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V  0x1
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S  12
+/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
+/*description: reset cause of APP CPU.*/
+#define RTC_CNTL_RESET_CAUSE_APPCPU    0x0000003F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_M  ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
+#define RTC_CNTL_RESET_CAUSE_APPCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_S  6
+/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
+/*description: reset cause of PRO CPU.*/
+#define RTC_CNTL_RESET_CAUSE_PROCPU    0x0000003F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
+#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
+
+#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x3C)
+/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */
+/*description: wakeup enable bitmap.*/
+#define RTC_CNTL_WAKEUP_ENA    0x0001FFFF
+#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
+#define RTC_CNTL_WAKEUP_ENA_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_ENA_S  15
+
+#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x40)
+/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA    (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M  (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enable gitch det interrupt.*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA    (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_S  19
+/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: enable touch timeout interrupt.*/
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA    (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M  (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S  18
+/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: enable cocpu trap interrupt.*/
+#define RTC_CNTL_COCPU_TRAP_INT_ENA    (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt.*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA    (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S  16
+/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_S  15
+/* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable saradc2 interrupt.*/
+#define RTC_CNTL_SARADC2_INT_ENA    (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ENA_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ENA_V  0x1
+#define RTC_CNTL_SARADC2_INT_ENA_S  14
+/* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: enable riscV cocpu interrupt.*/
+#define RTC_CNTL_COCPU_INT_ENA    (BIT(13))
+#define RTC_CNTL_COCPU_INT_ENA_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_ENA_V  0x1
+#define RTC_CNTL_COCPU_INT_ENA_S  13
+/* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: enable tsens interrupt.*/
+#define RTC_CNTL_TSENS_INT_ENA    (BIT(12))
+#define RTC_CNTL_TSENS_INT_ENA_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_ENA_V  0x1
+#define RTC_CNTL_TSENS_INT_ENA_S  12
+/* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: enable saradc1 interrupt.*/
+#define RTC_CNTL_SARADC1_INT_ENA    (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ENA_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ENA_V  0x1
+#define RTC_CNTL_SARADC1_INT_ENA_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable touch inactive interrupt.*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA    (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable touch active interrupt.*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA    (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable touch done interrupt.*/
+#define RTC_CNTL_TOUCH_DONE_INT_ENA    (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_S  6
+/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable ULP-coprocessor interrupt.*/
+#define RTC_CNTL_ULP_CP_INT_ENA    (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_V  0x1
+#define RTC_CNTL_ULP_CP_INT_ENA_S  5
+/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable touch scan done interrupt.*/
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA    (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M  (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S  4
+/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable SDIO idle interrupt.*/
+#define RTC_CNTL_SDIO_IDLE_INT_ENA    (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_S  2
+/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
+
+#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x44)
+/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW    (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M  (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S  20
+/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: glitch_det_interrupt_raw.*/
+#define RTC_CNTL_GLITCH_DET_INT_RAW    (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_RAW_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_RAW_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_RAW_S  19
+/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: touch timeout interrupt raw.*/
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW    (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M  (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S  18
+/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: cocpu trap interrupt raw.*/
+#define RTC_CNTL_COCPU_TRAP_INT_RAW    (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_RAW_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_RAW_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_RAW_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt raw.*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW    (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S  16
+/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt raw.*/
+#define RTC_CNTL_SWD_INT_RAW    (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_V  0x1
+#define RTC_CNTL_SWD_INT_RAW_S  15
+/* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: saradc2 interrupt raw.*/
+#define RTC_CNTL_SARADC2_INT_RAW    (BIT(14))
+#define RTC_CNTL_SARADC2_INT_RAW_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_RAW_V  0x1
+#define RTC_CNTL_SARADC2_INT_RAW_S  14
+/* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: riscV cocpu interrupt raw.*/
+#define RTC_CNTL_COCPU_INT_RAW    (BIT(13))
+#define RTC_CNTL_COCPU_INT_RAW_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_RAW_V  0x1
+#define RTC_CNTL_COCPU_INT_RAW_S  13
+/* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: tsens interrupt raw.*/
+#define RTC_CNTL_TSENS_INT_RAW    (BIT(12))
+#define RTC_CNTL_TSENS_INT_RAW_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_RAW_V  0x1
+#define RTC_CNTL_TSENS_INT_RAW_S  12
+/* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: saradc1 interrupt raw.*/
+#define RTC_CNTL_SARADC1_INT_RAW    (BIT(11))
+#define RTC_CNTL_SARADC1_INT_RAW_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_RAW_V  0x1
+#define RTC_CNTL_SARADC1_INT_RAW_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt raw.*/
+#define RTC_CNTL_MAIN_TIMER_INT_RAW    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
+/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt raw.*/
+#define RTC_CNTL_BROWN_OUT_INT_RAW    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: touch inactive interrupt raw.*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW    (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: touch active interrupt raw.*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW    (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: touch interrupt raw.*/
+#define RTC_CNTL_TOUCH_DONE_INT_RAW    (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_RAW_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_RAW_S  6
+/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ULP-coprocessor interrupt raw.*/
+#define RTC_CNTL_ULP_CP_INT_RAW    (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_RAW_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_RAW_V  0x1
+#define RTC_CNTL_ULP_CP_INT_RAW_S  5
+/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW    (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M  (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S  4
+/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt raw.*/
+#define RTC_CNTL_WDT_INT_RAW    (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_V  0x1
+#define RTC_CNTL_WDT_INT_RAW_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SDIO idle interrupt raw.*/
+#define RTC_CNTL_SDIO_IDLE_INT_RAW    (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_S  2
+/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt raw.*/
+#define RTC_CNTL_SLP_REJECT_INT_RAW    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt raw.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
+
+#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x48)
+/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST    (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M  (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: glitch_det_interrupt state.*/
+#define RTC_CNTL_GLITCH_DET_INT_ST    (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ST_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ST_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ST_S  19
+/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Touch timeout interrupt state.*/
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST    (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M  (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S  18
+/* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: cocpu trap interrupt state.*/
+#define RTC_CNTL_COCPU_TRAP_INT_ST    (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ST_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ST_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_ST_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt state.*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST    (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S  16
+/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt state.*/
+#define RTC_CNTL_SWD_INT_ST    (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_V  0x1
+#define RTC_CNTL_SWD_INT_ST_S  15
+/* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: saradc2 interrupt state.*/
+#define RTC_CNTL_SARADC2_INT_ST    (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ST_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ST_V  0x1
+#define RTC_CNTL_SARADC2_INT_ST_S  14
+/* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: riscV cocpu interrupt state.*/
+#define RTC_CNTL_COCPU_INT_ST    (BIT(13))
+#define RTC_CNTL_COCPU_INT_ST_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_ST_V  0x1
+#define RTC_CNTL_COCPU_INT_ST_S  13
+/* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: tsens interrupt state.*/
+#define RTC_CNTL_TSENS_INT_ST    (BIT(12))
+#define RTC_CNTL_TSENS_INT_ST_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_ST_V  0x1
+#define RTC_CNTL_TSENS_INT_ST_S  12
+/* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: saradc1 interrupt state.*/
+#define RTC_CNTL_SARADC1_INT_ST    (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ST_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ST_V  0x1
+#define RTC_CNTL_SARADC1_INT_ST_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt state.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ST    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt state.*/
+#define RTC_CNTL_BROWN_OUT_INT_ST    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: touch inactive interrupt state.*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ST    (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: touch active interrupt state.*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ST    (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: touch done interrupt state.*/
+#define RTC_CNTL_TOUCH_DONE_INT_ST    (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ST_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_ST_S  6
+/* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ULP-coprocessor interrupt state.*/
+#define RTC_CNTL_ULP_CP_INT_ST    (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ST_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ST_V  0x1
+#define RTC_CNTL_ULP_CP_INT_ST_S  5
+/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST    (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M  (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S  4
+/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt state.*/
+#define RTC_CNTL_WDT_INT_ST    (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_V  0x1
+#define RTC_CNTL_WDT_INT_ST_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SDIO idle interrupt state.*/
+#define RTC_CNTL_SDIO_IDLE_INT_ST    (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ST_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ST_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_ST_S  2
+/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt state.*/
+#define RTC_CNTL_SLP_REJECT_INT_ST    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt state.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ST    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
+
+#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x4C)
+/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR    (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M  (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S  20
+/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Clear glitch det interrupt state.*/
+#define RTC_CNTL_GLITCH_DET_INT_CLR    (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_CLR_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_CLR_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_CLR_S  19
+/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Clear touch timeout interrupt state.*/
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR    (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M  (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S  18
+/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Clear cocpu trap interrupt state.*/
+#define RTC_CNTL_COCPU_TRAP_INT_CLR    (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_CLR_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_CLR_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_CLR_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state.*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR    (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S  16
+/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Clear super watch dog interrupt state.*/
+#define RTC_CNTL_SWD_INT_CLR    (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_V  0x1
+#define RTC_CNTL_SWD_INT_CLR_S  15
+/* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Clear saradc2 interrupt state.*/
+#define RTC_CNTL_SARADC2_INT_CLR    (BIT(14))
+#define RTC_CNTL_SARADC2_INT_CLR_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_CLR_V  0x1
+#define RTC_CNTL_SARADC2_INT_CLR_S  14
+/* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Clear riscV cocpu interrupt state.*/
+#define RTC_CNTL_COCPU_INT_CLR    (BIT(13))
+#define RTC_CNTL_COCPU_INT_CLR_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_CLR_V  0x1
+#define RTC_CNTL_COCPU_INT_CLR_S  13
+/* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Clear tsens interrupt state.*/
+#define RTC_CNTL_TSENS_INT_CLR    (BIT(12))
+#define RTC_CNTL_TSENS_INT_CLR_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_CLR_V  0x1
+#define RTC_CNTL_TSENS_INT_CLR_S  12
+/* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Clear saradc1 interrupt state.*/
+#define RTC_CNTL_SARADC1_INT_CLR    (BIT(11))
+#define RTC_CNTL_SARADC1_INT_CLR_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_CLR_V  0x1
+#define RTC_CNTL_SARADC1_INT_CLR_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Clear RTC main timer interrupt state.*/
+#define RTC_CNTL_MAIN_TIMER_INT_CLR    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
+/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Clear brown out interrupt state.*/
+#define RTC_CNTL_BROWN_OUT_INT_CLR    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Clear touch inactive interrupt state.*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR    (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Clear touch active interrupt state.*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR    (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Clear touch done interrupt state.*/
+#define RTC_CNTL_TOUCH_DONE_INT_CLR    (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_CLR_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_CLR_S  6
+/* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Clear ULP-coprocessor interrupt state.*/
+#define RTC_CNTL_ULP_CP_INT_CLR    (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_CLR_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_CLR_V  0x1
+#define RTC_CNTL_ULP_CP_INT_CLR_S  5
+/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR    (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M  (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S  4
+/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state.*/
+#define RTC_CNTL_WDT_INT_CLR    (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_V  0x1
+#define RTC_CNTL_WDT_INT_CLR_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Clear SDIO idle interrupt state.*/
+#define RTC_CNTL_SDIO_IDLE_INT_CLR    (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_S  2
+/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Clear sleep reject interrupt state.*/
+#define RTC_CNTL_SLP_REJECT_INT_CLR    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Clear sleep wakeup interrupt state.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
+
+#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x50)
+/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_SCRATCH0    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
+#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_S  0
+
+#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x54)
+/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_SCRATCH1    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
+#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_S  0
+
+#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x58)
+/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_SCRATCH2    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
+#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_S  0
+
+#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x5C)
+/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_SCRATCH3    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
+#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_S  0
+
+#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x60)
+/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_XTL_EXT_CTR_EN    (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
+/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: power down XTAL at high level.*/
+#define RTC_CNTL_XTL_EXT_CTR_LV    (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
+/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: XTAL_32K sel. 0: external XTAL_32K.*/
+#define RTC_CNTL_XTAL32K_GPIO_SEL    (BIT(23))
+#define RTC_CNTL_XTAL32K_GPIO_SEL_M  (BIT(23))
+#define RTC_CNTL_XTAL32K_GPIO_SEL_V  0x1
+#define RTC_CNTL_XTAL32K_GPIO_SEL_S  23
+/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
+/*description: state of 32k_wdt.*/
+#define RTC_CNTL_WDT_STATE    0x00000007
+#define RTC_CNTL_WDT_STATE_M  ((RTC_CNTL_WDT_STATE_V)<<(RTC_CNTL_WDT_STATE_S))
+#define RTC_CNTL_WDT_STATE_V  0x7
+#define RTC_CNTL_WDT_STATE_S  20
+/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */
+/*description: DAC_XTAL_32K.*/
+#define RTC_CNTL_DAC_XTAL_32K    0x00000007
+#define RTC_CNTL_DAC_XTAL_32K_M  ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S))
+#define RTC_CNTL_DAC_XTAL_32K_V  0x7
+#define RTC_CNTL_DAC_XTAL_32K_S  17
+/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: XPD_XTAL_32K.*/
+#define RTC_CNTL_XPD_XTAL_32K    (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_M  (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_V  0x1
+#define RTC_CNTL_XPD_XTAL_32K_S  16
+/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
+/*description: DRES_XTAL_32K.*/
+#define RTC_CNTL_DRES_XTAL_32K    0x00000007
+#define RTC_CNTL_DRES_XTAL_32K_M  ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S))
+#define RTC_CNTL_DRES_XTAL_32K_V  0x7
+#define RTC_CNTL_DRES_XTAL_32K_S  13
+/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: xtal_32k gm control.*/
+#define RTC_CNTL_DGM_XTAL_32K    0x00000007
+#define RTC_CNTL_DGM_XTAL_32K_M  ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S))
+#define RTC_CNTL_DGM_XTAL_32K_V  0x7
+#define RTC_CNTL_DGM_XTAL_32K_S  10
+/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 0: single-end buffer 1: differential buffer.*/
+#define RTC_CNTL_DBUF_XTAL_32K    (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_M  (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_V  0x1
+#define RTC_CNTL_DBUF_XTAL_32K_S  9
+/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: apply an internal clock to help xtal 32k to start.*/
+#define RTC_CNTL_ENCKINIT_XTAL_32K    (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_M  (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_V  0x1
+#define RTC_CNTL_ENCKINIT_XTAL_32K_S  8
+/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: Xtal 32k xpd control by sw or fsm.*/
+#define RTC_CNTL_XTAL32K_XPD_FORCE    (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_M  (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_V  0x1
+#define RTC_CNTL_XTAL32K_XPD_FORCE_S  7
+/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: xtal 32k switch back xtal when xtal is restarted.*/
+#define RTC_CNTL_XTAL32K_AUTO_RETURN    (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_M  (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_S  6
+/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: xtal 32k restart xtal when xtal is dead.*/
+#define RTC_CNTL_XTAL32K_AUTO_RESTART    (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_M  (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_S  5
+/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: xtal 32k switch to back up clock when xtal is dead.*/
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP    (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M  (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S  4
+/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: xtal 32k external xtal clock force on.*/
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO    (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M  (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V  0x1
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S  3
+/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog sw reset.*/
+#define RTC_CNTL_XTAL32K_WDT_RESET    (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_M  (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_RESET_S  2
+/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog clock force on.*/
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO    (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M  (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S  1
+/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog enable.*/
+#define RTC_CNTL_XTAL32K_WDT_EN    (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_M  (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_EN_S  0
+
+#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x64)
+/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_EXT_WAKEUP1_LV    (BIT(31))
+#define RTC_CNTL_EXT_WAKEUP1_LV_M  (BIT(31))
+#define RTC_CNTL_EXT_WAKEUP1_LV_V  0x1
+#define RTC_CNTL_EXT_WAKEUP1_LV_S  31
+/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: external wakeup at low level.*/
+#define RTC_CNTL_EXT_WAKEUP0_LV    (BIT(30))
+#define RTC_CNTL_EXT_WAKEUP0_LV_M  (BIT(30))
+#define RTC_CNTL_EXT_WAKEUP0_LV_V  0x1
+#define RTC_CNTL_EXT_WAKEUP0_LV_S  30
+/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: enable filter for gpio wakeup event.*/
+#define RTC_CNTL_GPIO_WAKEUP_FILTER    (BIT(29))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(29))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  29
+
+#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x68)
+/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable reject for deep sleep.*/
+#define RTC_CNTL_DEEP_SLP_REJECT_EN    (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
+/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable reject for light sleep.*/
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN    (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
+/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */
+/*description: sleep reject enable.*/
+#define RTC_CNTL_SLEEP_REJECT_ENA    0x0003FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
+#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x3FFFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_S  12
+
+#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x6C)
+/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
+/*description: .*/
+#define RTC_CNTL_CPUPERIOD_SEL    0x00000003
+#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
+#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
+#define RTC_CNTL_CPUPERIOD_SEL_S  30
+/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: CPU sel option.*/
+#define RTC_CNTL_CPUSEL_CONF    (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_V  0x1
+#define RTC_CNTL_CPUSEL_CONF_S  29
+
+#define RTC_CNTL_SDIO_ACT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x70)
+/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */
+/*description: .*/
+#define RTC_CNTL_SDIO_ACT_DNUM    0x000003FF
+#define RTC_CNTL_SDIO_ACT_DNUM_M  ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S))
+#define RTC_CNTL_SDIO_ACT_DNUM_V  0x3FF
+#define RTC_CNTL_SDIO_ACT_DNUM_S  22
+
+#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x74)
+/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: .*/
+#define RTC_CNTL_ANA_CLK_RTC_SEL    0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
+#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
+/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: fast_clk_rtc sel. 0: XTAL div 2.*/
+#define RTC_CNTL_FAST_CLK_RTC_SEL    (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: .*/
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING    (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M  (BIT(28))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S  28
+/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING    (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M  (BIT(27))
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V  0x1
+#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S  27
+/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: CK8M force power up.*/
+#define RTC_CNTL_CK8M_FORCE_PU    (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PU_S  26
+/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: CK8M force power down.*/
+#define RTC_CNTL_CK8M_FORCE_PD    (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PD_S  25
+/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */
+/*description: CK8M_DFREQ.*/
+#define RTC_CNTL_CK8M_DFREQ    0x000000FF
+#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
+#define RTC_CNTL_CK8M_DFREQ_V  0xFF
+#define RTC_CNTL_CK8M_DFREQ_S  17
+/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: CK8M force no gating during sleep.*/
+#define RTC_CNTL_CK8M_FORCE_NOGATING    (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
+/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: XTAL force no gating during sleep.*/
+#define RTC_CNTL_XTAL_FORCE_NOGATING    (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
+/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: divider = reg_ck8m_div_sel + 1.*/
+#define RTC_CNTL_CK8M_DIV_SEL    0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
+#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
+#define RTC_CNTL_CK8M_DIV_SEL_S  12
+/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable CK8M for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_CLK8M_EN    (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_EN_S  10
+/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_CLK8M_D256_EN    (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
+/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core).*/
+#define RTC_CNTL_DIG_XTAL32K_EN    (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
+#define RTC_CNTL_DIG_XTAL32K_EN_S  8
+/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: 1: CK8M_D256_OUT is actually CK8M.*/
+#define RTC_CNTL_ENB_CK8M_DIV    (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
+#define RTC_CNTL_ENB_CK8M_DIV_S  7
+/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: disable CK8M and CK8M_D256_OUT.*/
+#define RTC_CNTL_ENB_CK8M    (BIT(6))
+#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_V  0x1
+#define RTC_CNTL_ENB_CK8M_S  6
+/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
+/*description: CK8M_D256_OUT divider. 00: div128.*/
+#define RTC_CNTL_CK8M_DIV    0x00000003
+#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
+#define RTC_CNTL_CK8M_DIV_V  0x3
+#define RTC_CNTL_CK8M_DIV_S  4
+/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel.*/
+#define RTC_CNTL_CK8M_DIV_SEL_VLD    (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
+/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING    (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M  (BIT(2))
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S  2
+/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING    (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M  (BIT(1))
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V  0x1
+#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S  1
+
+#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x78)
+/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE    (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
+/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */
+/*description: .*/
+#define RTC_CNTL_ANA_CLK_DIV    0x000000FF
+#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
+#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
+#define RTC_CNTL_ANA_CLK_DIV_S  23
+/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div.*/
+#define RTC_CNTL_ANA_CLK_DIV_VLD    (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
+#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
+
+#define RTC_CNTL_SDIO_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x7C)
+/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_XPD_SDIO_REG    (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_M  (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_V  0x1
+#define RTC_CNTL_XPD_SDIO_REG_S  31
+/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
+/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1.*/
+#define RTC_CNTL_DREFH_SDIO    0x00000003
+#define RTC_CNTL_DREFH_SDIO_M  ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
+#define RTC_CNTL_DREFH_SDIO_V  0x3
+#define RTC_CNTL_DREFH_SDIO_S  29
+/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */
+/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1.*/
+#define RTC_CNTL_DREFM_SDIO    0x00000003
+#define RTC_CNTL_DREFM_SDIO_M  ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
+#define RTC_CNTL_DREFM_SDIO_V  0x3
+#define RTC_CNTL_DREFM_SDIO_S  27
+/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
+/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1.*/
+#define RTC_CNTL_DREFL_SDIO    0x00000003
+#define RTC_CNTL_DREFL_SDIO_M  ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
+#define RTC_CNTL_DREFL_SDIO_V  0x3
+#define RTC_CNTL_DREFL_SDIO_S  25
+/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: read only register for REG1P8_READY.*/
+#define RTC_CNTL_REG1P8_READY    (BIT(24))
+#define RTC_CNTL_REG1P8_READY_M  (BIT(24))
+#define RTC_CNTL_REG1P8_READY_V  0x1
+#define RTC_CNTL_REG1P8_READY_S  24
+/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1.*/
+#define RTC_CNTL_SDIO_TIEH    (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_M  (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_V  0x1
+#define RTC_CNTL_SDIO_TIEH_S  23
+/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: use SW option to control SDIO_REG.*/
+#define RTC_CNTL_SDIO_FORCE    (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_M  (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_V  0x1
+#define RTC_CNTL_SDIO_FORCE_S  22
+/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
+/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0.*/
+#define RTC_CNTL_SDIO_PD_EN    (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_M  (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_V  0x1
+#define RTC_CNTL_SDIO_PD_EN_S  21
+/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: enable current limit.*/
+#define RTC_CNTL_SDIO_ENCURLIM    (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_M  (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_V  0x1
+#define RTC_CNTL_SDIO_ENCURLIM_S  20
+/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: select current limit mode.*/
+#define RTC_CNTL_SDIO_MODECURLIM    (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_M  (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_V  0x1
+#define RTC_CNTL_SDIO_MODECURLIM_S  19
+/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */
+/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d).*/
+#define RTC_CNTL_SDIO_DCURLIM    0x00000007
+#define RTC_CNTL_SDIO_DCURLIM_M  ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S))
+#define RTC_CNTL_SDIO_DCURLIM_V  0x7
+#define RTC_CNTL_SDIO_DCURLIM_S  16
+/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: 0 to set init[1:0]=0.*/
+#define RTC_CNTL_SDIO_EN_INITI    (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_M  (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_V  0x1
+#define RTC_CNTL_SDIO_EN_INITI_S  15
+/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */
+/*description: add resistor from ldo output to ground. 0: no res.*/
+#define RTC_CNTL_SDIO_INITI    0x00000003
+#define RTC_CNTL_SDIO_INITI_M  ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
+#define RTC_CNTL_SDIO_INITI_V  0x3
+#define RTC_CNTL_SDIO_INITI_S  13
+/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
+/*description: ability to prevent LDO from overshoot.*/
+#define RTC_CNTL_SDIO_DCAP    0x00000003
+#define RTC_CNTL_SDIO_DCAP_M  ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S))
+#define RTC_CNTL_SDIO_DCAP_V  0x3
+#define RTC_CNTL_SDIO_DCAP_S  11
+/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */
+/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current.*/
+#define RTC_CNTL_SDIO_DTHDRV    0x00000003
+#define RTC_CNTL_SDIO_DTHDRV_M  ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S))
+#define RTC_CNTL_SDIO_DTHDRV_V  0x3
+#define RTC_CNTL_SDIO_DTHDRV_S  9
+/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
+/*description: timer count to apply reg_sdio_dcap after sdio power on.*/
+#define RTC_CNTL_SDIO_TIMER_TARGET    0x000000FF
+#define RTC_CNTL_SDIO_TIMER_TARGET_M  ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S))
+#define RTC_CNTL_SDIO_TIMER_TARGET_V  0xFF
+#define RTC_CNTL_SDIO_TIMER_TARGET_S  0
+
+#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x80)
+/* RTC_CNTL_DBG_ATTEN_WAKEUP : R/W ;bitpos:[29:26] ;default: 4'd0 ; */
+/*description: .*/
+#define RTC_CNTL_DBG_ATTEN_WAKEUP    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_WAKEUP_M  ((RTC_CNTL_DBG_ATTEN_WAKEUP_V)<<(RTC_CNTL_DBG_ATTEN_WAKEUP_S))
+#define RTC_CNTL_DBG_ATTEN_WAKEUP_V  0xF
+#define RTC_CNTL_DBG_ATTEN_WAKEUP_S  26
+/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in monitor state.*/
+#define RTC_CNTL_DBG_ATTEN_MONITOR    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_MONITOR_M  ((RTC_CNTL_DBG_ATTEN_MONITOR_V)<<(RTC_CNTL_DBG_ATTEN_MONITOR_S))
+#define RTC_CNTL_DBG_ATTEN_MONITOR_V  0xF
+#define RTC_CNTL_DBG_ATTEN_MONITOR_S  22
+/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */
+/*description: DBG_ATTEN when rtc in sleep state.*/
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP    0x0000000F
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M  ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V)<<(RTC_CNTL_DBG_ATTEN_DEEP_SLP_S))
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V  0xF
+#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S  18
+/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: bias_sleep when rtc in monitor state.*/
+#define RTC_CNTL_BIAS_SLEEP_MONITOR    (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_M  (BIT(17))
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_MONITOR_S  17
+/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: bias_sleep when rtc in sleep_state.*/
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP    (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M  (BIT(16))
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S  16
+/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in monitor state.*/
+#define RTC_CNTL_PD_CUR_MONITOR    (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_M  (BIT(15))
+#define RTC_CNTL_PD_CUR_MONITOR_V  0x1
+#define RTC_CNTL_PD_CUR_MONITOR_S  15
+/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: xpd cur when rtc in sleep_state.*/
+#define RTC_CNTL_PD_CUR_DEEP_SLP    (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_M  (BIT(14))
+#define RTC_CNTL_PD_CUR_DEEP_SLP_V  0x1
+#define RTC_CNTL_PD_CUR_DEEP_SLP_S  14
+/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_BIAS_BUF_MONITOR    (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_M  (BIT(13))
+#define RTC_CNTL_BIAS_BUF_MONITOR_V  0x1
+#define RTC_CNTL_BIAS_BUF_MONITOR_S  13
+/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP    (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M  (BIT(12))
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V  0x1
+#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S  12
+/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: .*/
+#define RTC_CNTL_BIAS_BUF_WAKE    (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_M  (BIT(11))
+#define RTC_CNTL_BIAS_BUF_WAKE_V  0x1
+#define RTC_CNTL_BIAS_BUF_WAKE_S  11
+/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_BIAS_BUF_IDLE    (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_M  (BIT(10))
+#define RTC_CNTL_BIAS_BUF_IDLE_V  0x1
+#define RTC_CNTL_BIAS_BUF_IDLE_S  10
+
+#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x84)
+/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: .*/
+#define RTC_CNTL_REGULATOR_FORCE_PU    (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
+/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0
+.8v or lower ).*/
+#define RTC_CNTL_REGULATOR_FORCE_PD    (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
+/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: RTC_DBOOST force power up.*/
+#define RTC_CNTL_DBOOST_FORCE_PU    (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_M  (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_V  0x1
+#define RTC_CNTL_DBOOST_FORCE_PU_S  29
+/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RTC_DBOOST force power down.*/
+#define RTC_CNTL_DBOOST_FORCE_PD    (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_M  (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_V  0x1
+#define RTC_CNTL_DBOOST_FORCE_PD_S  28
+/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
+ * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
+ * Valid if RTC_CNTL_DBG_ATTEN is 0.
+ */
+#define RTC_CNTL_DIG_DBIAS_0V85  0
+#define RTC_CNTL_DIG_DBIAS_0V90  1
+#define RTC_CNTL_DIG_DBIAS_0V95  2
+#define RTC_CNTL_DIG_DBIAS_1V00  3
+#define RTC_CNTL_DIG_DBIAS_1V05  4
+#define RTC_CNTL_DIG_DBIAS_1V10  5
+#define RTC_CNTL_DIG_DBIAS_1V15  6
+#define RTC_CNTL_DIG_DBIAS_1V20  7
+
+
+/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
+/*description: SCK_DCAP.*/
+#define RTC_CNTL_SCK_DCAP    0x000000FF
+#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
+#define RTC_CNTL_SCK_DCAP_V  0xFF
+#define RTC_CNTL_SCK_DCAP_S  14
+/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_DIG_CAL_EN    (BIT(7))
+#define RTC_CNTL_DIG_CAL_EN_M  (BIT(7))
+#define RTC_CNTL_DIG_CAL_EN_V  0x1
+#define RTC_CNTL_DIG_CAL_EN_S  7
+
+#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x88)
+/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: rtc pad force hold.*/
+#define RTC_CNTL_PAD_FORCE_HOLD    (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_PAD_FORCE_HOLD_S  21
+/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: enable power down rtc_peri in sleep .*/
+#define RTC_CNTL_PD_EN    (BIT(20))
+#define RTC_CNTL_PD_EN_M  (BIT(20))
+#define RTC_CNTL_PD_EN_V  0x1
+#define RTC_CNTL_PD_EN_S  20
+/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: rtc_peri force power up.*/
+#define RTC_CNTL_FORCE_PU    (BIT(19))
+#define RTC_CNTL_FORCE_PU_M  (BIT(19))
+#define RTC_CNTL_FORCE_PU_V  0x1
+#define RTC_CNTL_FORCE_PU_S  19
+/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc_peri force power down.*/
+#define RTC_CNTL_FORCE_PD    (BIT(18))
+#define RTC_CNTL_FORCE_PD_M  (BIT(18))
+#define RTC_CNTL_FORCE_PD_V  0x1
+#define RTC_CNTL_FORCE_PD_S  18
+/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: RTC memory force no PD.*/
+#define RTC_CNTL_SLOWMEM_FORCE_LPU    (BIT(11))
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_M  (BIT(11))
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_S  11
+/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC memory force PD.*/
+#define RTC_CNTL_SLOWMEM_FORCE_LPD    (BIT(10))
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_M  (BIT(10))
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_S  10
+/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: RTC memory  PD following CPU.*/
+#define RTC_CNTL_SLOWMEM_FOLW_CPU    (BIT(9))
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_M  (BIT(9))
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_V  0x1
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_S  9
+/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: Fast RTC memory force no PD.*/
+#define RTC_CNTL_FASTMEM_FORCE_LPU    (BIT(8))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_M  (BIT(8))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPU_S  8
+/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Fast RTC memory force PD.*/
+#define RTC_CNTL_FASTMEM_FORCE_LPD    (BIT(7))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_M  (BIT(7))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPD_S  7
+/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: Fast RTC memory PD following CPU.*/
+#define RTC_CNTL_FASTMEM_FOLW_CPU    (BIT(6))
+#define RTC_CNTL_FASTMEM_FOLW_CPU_M  (BIT(6))
+#define RTC_CNTL_FASTMEM_FOLW_CPU_V  0x1
+#define RTC_CNTL_FASTMEM_FOLW_CPU_S  6
+/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */
+/*description: rtc_peri force no ISO.*/
+#define RTC_CNTL_FORCE_NOISO    (BIT(5))
+#define RTC_CNTL_FORCE_NOISO_M  (BIT(5))
+#define RTC_CNTL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_FORCE_NOISO_S  5
+/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: rtc_peri force ISO.*/
+#define RTC_CNTL_FORCE_ISO    (BIT(4))
+#define RTC_CNTL_FORCE_ISO_M  (BIT(4))
+#define RTC_CNTL_FORCE_ISO_V  0x1
+#define RTC_CNTL_FORCE_ISO_S  4
+/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC memory force ISO.*/
+#define RTC_CNTL_SLOWMEM_FORCE_ISO    (BIT(3))
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_M  (BIT(3))
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_S  3
+/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: RTC memory force no ISO.*/
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO    (BIT(2))
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M  (BIT(2))
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S  2
+/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Fast RTC memory force ISO.*/
+#define RTC_CNTL_FASTMEM_FORCE_ISO    (BIT(1))
+#define RTC_CNTL_FASTMEM_FORCE_ISO_M  (BIT(1))
+#define RTC_CNTL_FASTMEM_FORCE_ISO_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_ISO_S  1
+/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Fast RTC memory force no ISO.*/
+#define RTC_CNTL_FASTMEM_FORCE_NOISO    (BIT(0))
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_M  (BIT(0))
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_S  0
+
+#define RTC_CNTL_REGULATOR_DRV_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x8C)
+/* RTC_CNTL_DG_VDD_DRV_B_MONITOR : R/W ;bitpos:[27:20] ;default: 8'h0 ; */
+/*description: .*/
+#define RTC_CNTL_DG_VDD_DRV_B_MONITOR    0x000000FF
+#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_M  ((RTC_CNTL_DG_VDD_DRV_B_MONITOR_V)<<(RTC_CNTL_DG_VDD_DRV_B_MONITOR_S))
+#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_V  0xFF
+#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_S  20
+/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W ;bitpos:[19:12] ;default: 8'h0 ; */
+/*description: .*/
+#define RTC_CNTL_DG_VDD_DRV_B_SLP    0x000000FF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_M  ((RTC_CNTL_DG_VDD_DRV_B_SLP_V)<<(RTC_CNTL_DG_VDD_DRV_B_SLP_S))
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_V  0xFF
+#define RTC_CNTL_DG_VDD_DRV_B_SLP_S  12
+/* RTC_CNTL_REGULATOR_DRV_B_SLP : R/W ;bitpos:[11:6] ;default: 6'b0 ; */
+/*description: .*/
+#define RTC_CNTL_REGULATOR_DRV_B_SLP    0x0000003F
+#define RTC_CNTL_REGULATOR_DRV_B_SLP_M  ((RTC_CNTL_REGULATOR_DRV_B_SLP_V)<<(RTC_CNTL_REGULATOR_DRV_B_SLP_S))
+#define RTC_CNTL_REGULATOR_DRV_B_SLP_V  0x3F
+#define RTC_CNTL_REGULATOR_DRV_B_SLP_S  6
+/* RTC_CNTL_REGULATOR_DRV_B_MONITOR : R/W ;bitpos:[5:0] ;default: 6'b0 ; */
+/*description: .*/
+#define RTC_CNTL_REGULATOR_DRV_B_MONITOR    0x0000003F
+#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_M  ((RTC_CNTL_REGULATOR_DRV_B_MONITOR_V)<<(RTC_CNTL_REGULATOR_DRV_B_MONITOR_S))
+#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_V  0x3F
+#define RTC_CNTL_REGULATOR_DRV_B_MONITOR_S  0
+
+#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x90)
+/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_DG_WRAP_PD_EN    (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
+#define RTC_CNTL_DG_WRAP_PD_EN_S  31
+/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */
+/*description: enable power down wifi in sleep.*/
+#define RTC_CNTL_WIFI_PD_EN    (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_M  (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_V  0x1
+#define RTC_CNTL_WIFI_PD_EN_S  30
+/* RTC_CNTL_CPU_TOP_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */
+/*description: enable power down internal SRAM 4 in sleep.*/
+#define RTC_CNTL_CPU_TOP_PD_EN    (BIT(29))
+#define RTC_CNTL_CPU_TOP_PD_EN_M  (BIT(29))
+#define RTC_CNTL_CPU_TOP_PD_EN_V  0x1
+#define RTC_CNTL_CPU_TOP_PD_EN_S  29
+/* RTC_CNTL_DG_PERI_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */
+/*description: enable power down internal SRAM 3 in sleep.*/
+#define RTC_CNTL_DG_PERI_PD_EN    (BIT(28))
+#define RTC_CNTL_DG_PERI_PD_EN_M  (BIT(28))
+#define RTC_CNTL_DG_PERI_PD_EN_V  0x1
+#define RTC_CNTL_DG_PERI_PD_EN_S  28
+/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */
+/*description: digital dcdc force power up.*/
+#define RTC_CNTL_CPU_TOP_FORCE_PU    (BIT(22))
+#define RTC_CNTL_CPU_TOP_FORCE_PU_M  (BIT(22))
+#define RTC_CNTL_CPU_TOP_FORCE_PU_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_PU_S  22
+/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: digital dcdc force power down.*/
+#define RTC_CNTL_CPU_TOP_FORCE_PD    (BIT(21))
+#define RTC_CNTL_CPU_TOP_FORCE_PD_M  (BIT(21))
+#define RTC_CNTL_CPU_TOP_FORCE_PD_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_PD_S  21
+/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: digital core force power up.*/
+#define RTC_CNTL_DG_WRAP_FORCE_PU    (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
+/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: digital core force power down.*/
+#define RTC_CNTL_DG_WRAP_FORCE_PD    (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
+/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
+/*description: wifi force power up.*/
+#define RTC_CNTL_WIFI_FORCE_PU    (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_M  (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_V  0x1
+#define RTC_CNTL_WIFI_FORCE_PU_S  18
+/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: wifi force power down.*/
+#define RTC_CNTL_WIFI_FORCE_PD    (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_M  (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_V  0x1
+#define RTC_CNTL_WIFI_FORCE_PD_S  17
+/* RTC_CNTL_DG_PERI_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */
+/*description: internal SRAM 3 force power up.*/
+#define RTC_CNTL_DG_PERI_FORCE_PU    (BIT(14))
+#define RTC_CNTL_DG_PERI_FORCE_PU_M  (BIT(14))
+#define RTC_CNTL_DG_PERI_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_PU_S  14
+/* RTC_CNTL_DG_PERI_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: internal SRAM 3 force power down.*/
+#define RTC_CNTL_DG_PERI_FORCE_PD    (BIT(13))
+#define RTC_CNTL_DG_PERI_FORCE_PD_M  (BIT(13))
+#define RTC_CNTL_DG_PERI_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_PD_S  13
+/* RTC_CNTL_BT_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: internal SRAM 2 force power up.*/
+#define RTC_CNTL_BT_FORCE_PU    (BIT(12))
+#define RTC_CNTL_BT_FORCE_PU_M  (BIT(12))
+#define RTC_CNTL_BT_FORCE_PU_V  0x1
+#define RTC_CNTL_BT_FORCE_PU_S  12
+/* RTC_CNTL_BT_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: internal SRAM 2 force power down.*/
+#define RTC_CNTL_BT_FORCE_PD    (BIT(11))
+#define RTC_CNTL_BT_FORCE_PD_M  (BIT(11))
+#define RTC_CNTL_BT_FORCE_PD_V  0x1
+#define RTC_CNTL_BT_FORCE_PD_S  11
+/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: memories in digital core force no PD in sleep.*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PU    (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  4
+/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: memories in digital core force PD in sleep.*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PD    (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
+
+#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x94)
+/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: .*/
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO    (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force ISO.*/
+#define RTC_CNTL_DG_WRAP_FORCE_ISO    (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
+/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: wifi force no ISO.*/
+#define RTC_CNTL_WIFI_FORCE_NOISO    (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_M  (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_V  0x1
+#define RTC_CNTL_WIFI_FORCE_NOISO_S  29
+/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: wifi force ISO.*/
+#define RTC_CNTL_WIFI_FORCE_ISO    (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_M  (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_V  0x1
+#define RTC_CNTL_WIFI_FORCE_ISO_S  28
+/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: internal SRAM 4 force no ISO.*/
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO    (BIT(27))
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M  (BIT(27))
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S  27
+/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: internal SRAM 4 force ISO.*/
+#define RTC_CNTL_CPU_TOP_FORCE_ISO    (BIT(26))
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_M  (BIT(26))
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_V  0x1
+#define RTC_CNTL_CPU_TOP_FORCE_ISO_S  26
+/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
+/*description: internal SRAM 3 force no ISO.*/
+#define RTC_CNTL_DG_PERI_FORCE_NOISO    (BIT(25))
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_M  (BIT(25))
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_NOISO_S  25
+/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: internal SRAM 3 force ISO.*/
+#define RTC_CNTL_DG_PERI_FORCE_ISO    (BIT(24))
+#define RTC_CNTL_DG_PERI_FORCE_ISO_M  (BIT(24))
+#define RTC_CNTL_DG_PERI_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PERI_FORCE_ISO_S  24
+/* RTC_CNTL_BT_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: internal SRAM 2 force no ISO.*/
+#define RTC_CNTL_BT_FORCE_NOISO    (BIT(23))
+#define RTC_CNTL_BT_FORCE_NOISO_M  (BIT(23))
+#define RTC_CNTL_BT_FORCE_NOISO_V  0x1
+#define RTC_CNTL_BT_FORCE_NOISO_S  23
+/* RTC_CNTL_BT_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: internal SRAM 2 force ISO.*/
+#define RTC_CNTL_BT_FORCE_ISO    (BIT(22))
+#define RTC_CNTL_BT_FORCE_ISO_M  (BIT(22))
+#define RTC_CNTL_BT_FORCE_ISO_V  0x1
+#define RTC_CNTL_BT_FORCE_ISO_S  22
+/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: digital pad force hold.*/
+#define RTC_CNTL_DG_PAD_FORCE_HOLD    (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
+/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
+/*description: digital pad force un-hold.*/
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD    (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
+/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: digital pad force ISO.*/
+#define RTC_CNTL_DG_PAD_FORCE_ISO    (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
+/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: digital pad force no ISO.*/
+#define RTC_CNTL_DG_PAD_FORCE_NOISO    (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
+/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: digital pad enable auto-hold.*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN    (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
+/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: wtite only register to clear digital pad auto-hold.*/
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD    (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
+/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: read only register to indicate digital pad auto-hold status.*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD    (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
+/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_DIG_ISO_FORCE_ON    (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
+/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */
+/*description: .*/
+#define RTC_CNTL_DIG_ISO_FORCE_OFF    (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
+
+#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x98)
+/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define RTC_CNTL_WDT_EN    (BIT(31))
+#define RTC_CNTL_WDT_EN_M  (BIT(31))
+#define RTC_CNTL_WDT_EN_V  0x1
+#define RTC_CNTL_WDT_EN_S  31
+/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG0    0x00000007
+#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
+#define RTC_CNTL_WDT_STG0_V  0x7
+#define RTC_CNTL_WDT_STG0_S  28
+/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG1    0x00000007
+#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
+#define RTC_CNTL_WDT_STG1_V  0x7
+#define RTC_CNTL_WDT_STG1_S  25
+/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG2    0x00000007
+#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
+#define RTC_CNTL_WDT_STG2_V  0x7
+#define RTC_CNTL_WDT_STG2_S  22
+/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en.*/
+#define RTC_CNTL_WDT_STG3    0x00000007
+#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
+#define RTC_CNTL_WDT_STG3_V  0x7
+#define RTC_CNTL_WDT_STG3_S  19
+
+/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: CPU reset counter length.*/
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH    0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
+/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
+/*description: system reset counter length.*/
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH    0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
+/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: enable WDT in flash boot.*/
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN    (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
+/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: enable WDT reset PRO CPU.*/
+#define RTC_CNTL_WDT_PROCPU_RESET_EN    (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
+/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable WDT reset APP CPU.*/
+#define RTC_CNTL_WDT_APPCPU_RESET_EN    (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_M  (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_S  10
+/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: pause WDT in sleep.*/
+#define RTC_CNTL_WDT_PAUSE_IN_SLP    (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
+/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: wdt reset whole chip enable.*/
+#define RTC_CNTL_WDT_CHIP_RESET_EN    (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
+/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */
+/*description: chip reset siginal pulse width.*/
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH    0x000000FF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
+
+#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x9C)
+/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
+/*description: .*/
+#define RTC_CNTL_WDT_STG0_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
+#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0xA0)
+/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
+/*description: .*/
+#define RTC_CNTL_WDT_STG1_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
+#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0xA4)
+/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: .*/
+#define RTC_CNTL_WDT_STG2_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
+#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0xA8)
+/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: .*/
+#define RTC_CNTL_WDT_STG3_HOLD    0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
+#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_S  0
+
+#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0xAC)
+/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_WDT_FEED    (BIT(31))
+#define RTC_CNTL_WDT_FEED_M  (BIT(31))
+#define RTC_CNTL_WDT_FEED_V  0x1
+#define RTC_CNTL_WDT_FEED_S  31
+
+#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xB0)
+/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: .*/
+#define RTC_CNTL_WDT_WKEY    0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
+#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_S  0
+
+#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xB4)
+/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: automatically feed swd when int comes.*/
+#define RTC_CNTL_SWD_AUTO_FEED_EN    (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
+#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
+/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: disable SWD.*/
+#define RTC_CNTL_SWD_DISABLE    (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_V  0x1
+#define RTC_CNTL_SWD_DISABLE_S  30
+/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Sw feed swd.*/
+#define RTC_CNTL_SWD_FEED    (BIT(29))
+#define RTC_CNTL_SWD_FEED_M  (BIT(29))
+#define RTC_CNTL_SWD_FEED_V  0x1
+#define RTC_CNTL_SWD_FEED_S  29
+/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: reset swd reset flag.*/
+#define RTC_CNTL_SWD_RST_FLAG_CLR    (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
+#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
+/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
+/*description: adjust signal width send to swd.*/
+#define RTC_CNTL_SWD_SIGNAL_WIDTH    0x000003FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
+/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_SWD_BYPASS_RST    (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_M  (BIT(17))
+#define RTC_CNTL_SWD_BYPASS_RST_V  0x1
+#define RTC_CNTL_SWD_BYPASS_RST_S  17
+/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: swd interrupt for feeding.*/
+#define RTC_CNTL_SWD_FEED_INT    (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_V  0x1
+#define RTC_CNTL_SWD_FEED_INT_S  1
+/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: swd reset flag.*/
+#define RTC_CNTL_SWD_RESET_FLAG    (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
+#define RTC_CNTL_SWD_RESET_FLAG_S  0
+
+#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0xB8)
+/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
+/*description: .*/
+#define RTC_CNTL_SWD_WKEY    0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
+#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_S  0
+
+#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0xBC)
+/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
+/*description: .*/
+#define RTC_CNTL_SW_STALL_PROCPU_C1    0x0000003F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
+/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0].*/
+#define RTC_CNTL_SW_STALL_APPCPU_C1    0x0000003F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_M  ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_S  20
+
+#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0xC0)
+/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_SCRATCH4    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
+#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_S  0
+
+#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0xC4)
+/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_SCRATCH5    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
+#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_S  0
+
+#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0xC8)
+/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_SCRATCH6    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
+#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_S  0
+
+#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0xCC)
+/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_SCRATCH7    0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
+#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_S  0
+
+#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0xD0)
+/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: rtc main state machine status.*/
+#define RTC_CNTL_MAIN_STATE    0x0000000F
+#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
+#define RTC_CNTL_MAIN_STATE_V  0xF
+#define RTC_CNTL_MAIN_STATE_S  28
+/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: rtc main state machine is in idle state.*/
+#define RTC_CNTL_MAIN_STATE_IN_IDLE    (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
+/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: rtc main state machine is in sleep state.*/
+#define RTC_CNTL_MAIN_STATE_IN_SLP    (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait xtal state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL    (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait pll state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL    (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait 8m state.*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M    (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
+/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of low power.*/
+#define RTC_CNTL_IN_LOW_POWER_STATE    (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
+#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
+/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of wakeup process.*/
+#define RTC_CNTL_IN_WAKEUP_STATE    (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
+#define RTC_CNTL_IN_WAKEUP_STATE_S  21
+/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: rtc main state machine has been waited for some cycles.*/
+#define RTC_CNTL_MAIN_STATE_WAIT_END    (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
+#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
+/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: rtc is ready to receive wake up trigger from wake up source.*/
+#define RTC_CNTL_RDY_FOR_WAKEUP    (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
+#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
+/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc main state machine is in states that pll should be running.*/
+#define RTC_CNTL_MAIN_STATE_PLL_ON    (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
+#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
+/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: no use any more.*/
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO    (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
+/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: ulp/cocpu is done.*/
+#define RTC_CNTL_COCPU_STATE_DONE    (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
+#define RTC_CNTL_COCPU_STATE_DONE_S  16
+/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: ulp/cocpu is in sleep state.*/
+#define RTC_CNTL_COCPU_STATE_SLP    (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
+#define RTC_CNTL_COCPU_STATE_SLP_S  15
+/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: ulp/cocpu is about to working. Switch rtc main state.*/
+#define RTC_CNTL_COCPU_STATE_SWITCH    (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
+#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
+/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: ulp/cocpu should start to work.*/
+#define RTC_CNTL_COCPU_STATE_START    (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_V  0x1
+#define RTC_CNTL_COCPU_STATE_START_S  13
+/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: touch is done.*/
+#define RTC_CNTL_TOUCH_STATE_DONE    (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
+#define RTC_CNTL_TOUCH_STATE_DONE_S  12
+/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: touch is in sleep state.*/
+#define RTC_CNTL_TOUCH_STATE_SLP    (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SLP_S  11
+/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: touch is about to working. Switch rtc main state.*/
+#define RTC_CNTL_TOUCH_STATE_SWITCH    (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
+/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: touch should start to work.*/
+#define RTC_CNTL_TOUCH_STATE_START    (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_V  0x1
+#define RTC_CNTL_TOUCH_STATE_START_S  9
+/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: digital wrap power down.*/
+#define RTC_CNTL_XPD_DIG    (BIT(8))
+#define RTC_CNTL_XPD_DIG_M  (BIT(8))
+#define RTC_CNTL_XPD_DIG_V  0x1
+#define RTC_CNTL_XPD_DIG_S  8
+/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: digital wrap iso.*/
+#define RTC_CNTL_DIG_ISO    (BIT(7))
+#define RTC_CNTL_DIG_ISO_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_V  0x1
+#define RTC_CNTL_DIG_ISO_S  7
+/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: wifi wrap power down.*/
+#define RTC_CNTL_XPD_WIFI    (BIT(6))
+#define RTC_CNTL_XPD_WIFI_M  (BIT(6))
+#define RTC_CNTL_XPD_WIFI_V  0x1
+#define RTC_CNTL_XPD_WIFI_S  6
+/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: wifi iso.*/
+#define RTC_CNTL_WIFI_ISO    (BIT(5))
+#define RTC_CNTL_WIFI_ISO_M  (BIT(5))
+#define RTC_CNTL_WIFI_ISO_V  0x1
+#define RTC_CNTL_WIFI_ISO_S  5
+/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: rtc peripheral power down .*/
+#define RTC_CNTL_XPD_RTC_PERI    (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_M  (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_V  0x1
+#define RTC_CNTL_XPD_RTC_PERI_S  4
+/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: rtc peripheral iso.*/
+#define RTC_CNTL_PERI_ISO    (BIT(3))
+#define RTC_CNTL_PERI_ISO_M  (BIT(3))
+#define RTC_CNTL_PERI_ISO_V  0x1
+#define RTC_CNTL_PERI_ISO_S  3
+/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: External DCDC power down.*/
+#define RTC_CNTL_XPD_DIG_DCDC    (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_M  (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_V  0x1
+#define RTC_CNTL_XPD_DIG_DCDC_S  2
+/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rom0 power down.*/
+#define RTC_CNTL_XPD_ROM0    (BIT(0))
+#define RTC_CNTL_XPD_ROM0_M  (BIT(0))
+#define RTC_CNTL_XPD_ROM0_V  0x1
+#define RTC_CNTL_XPD_ROM0_S  0
+
+#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0xD4)
+/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
+/*description: .*/
+#define RTC_CNTL_LOW_POWER_DIAG1    0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
+#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_S  0
+
+#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xD8)
+/* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_PAD21_HOLD    (BIT(21))
+#define RTC_CNTL_PAD21_HOLD_M  (BIT(21))
+#define RTC_CNTL_PAD21_HOLD_V  0x1
+#define RTC_CNTL_PAD21_HOLD_S  21
+/* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_PAD20_HOLD    (BIT(20))
+#define RTC_CNTL_PAD20_HOLD_M  (BIT(20))
+#define RTC_CNTL_PAD20_HOLD_V  0x1
+#define RTC_CNTL_PAD20_HOLD_S  20
+/* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_PAD19_HOLD    (BIT(19))
+#define RTC_CNTL_PAD19_HOLD_M  (BIT(19))
+#define RTC_CNTL_PAD19_HOLD_V  0x1
+#define RTC_CNTL_PAD19_HOLD_S  19
+/* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_PDAC2_HOLD    (BIT(18))
+#define RTC_CNTL_PDAC2_HOLD_M  (BIT(18))
+#define RTC_CNTL_PDAC2_HOLD_V  0x1
+#define RTC_CNTL_PDAC2_HOLD_S  18
+/* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_PDAC1_HOLD    (BIT(17))
+#define RTC_CNTL_PDAC1_HOLD_M  (BIT(17))
+#define RTC_CNTL_PDAC1_HOLD_V  0x1
+#define RTC_CNTL_PDAC1_HOLD_S  17
+/* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_X32N_HOLD    (BIT(16))
+#define RTC_CNTL_X32N_HOLD_M  (BIT(16))
+#define RTC_CNTL_X32N_HOLD_V  0x1
+#define RTC_CNTL_X32N_HOLD_S  16
+/* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_X32P_HOLD    (BIT(15))
+#define RTC_CNTL_X32P_HOLD_M  (BIT(15))
+#define RTC_CNTL_X32P_HOLD_V  0x1
+#define RTC_CNTL_X32P_HOLD_S  15
+/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD14_HOLD    (BIT(14))
+#define RTC_CNTL_TOUCH_PAD14_HOLD_M  (BIT(14))
+#define RTC_CNTL_TOUCH_PAD14_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD14_HOLD_S  14
+/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD13_HOLD    (BIT(13))
+#define RTC_CNTL_TOUCH_PAD13_HOLD_M  (BIT(13))
+#define RTC_CNTL_TOUCH_PAD13_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD13_HOLD_S  13
+/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD12_HOLD    (BIT(12))
+#define RTC_CNTL_TOUCH_PAD12_HOLD_M  (BIT(12))
+#define RTC_CNTL_TOUCH_PAD12_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD12_HOLD_S  12
+/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD11_HOLD    (BIT(11))
+#define RTC_CNTL_TOUCH_PAD11_HOLD_M  (BIT(11))
+#define RTC_CNTL_TOUCH_PAD11_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD11_HOLD_S  11
+/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD10_HOLD    (BIT(10))
+#define RTC_CNTL_TOUCH_PAD10_HOLD_M  (BIT(10))
+#define RTC_CNTL_TOUCH_PAD10_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD10_HOLD_S  10
+/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD9_HOLD    (BIT(9))
+#define RTC_CNTL_TOUCH_PAD9_HOLD_M  (BIT(9))
+#define RTC_CNTL_TOUCH_PAD9_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD9_HOLD_S  9
+/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD8_HOLD    (BIT(8))
+#define RTC_CNTL_TOUCH_PAD8_HOLD_M  (BIT(8))
+#define RTC_CNTL_TOUCH_PAD8_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD8_HOLD_S  8
+/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD7_HOLD    (BIT(7))
+#define RTC_CNTL_TOUCH_PAD7_HOLD_M  (BIT(7))
+#define RTC_CNTL_TOUCH_PAD7_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD7_HOLD_S  7
+/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD6_HOLD    (BIT(6))
+#define RTC_CNTL_TOUCH_PAD6_HOLD_M  (BIT(6))
+#define RTC_CNTL_TOUCH_PAD6_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD6_HOLD_S  6
+/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD5_HOLD    (BIT(5))
+#define RTC_CNTL_TOUCH_PAD5_HOLD_M  (BIT(5))
+#define RTC_CNTL_TOUCH_PAD5_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD5_HOLD_S  5
+/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD4_HOLD    (BIT(4))
+#define RTC_CNTL_TOUCH_PAD4_HOLD_M  (BIT(4))
+#define RTC_CNTL_TOUCH_PAD4_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD4_HOLD_S  4
+/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD3_HOLD    (BIT(3))
+#define RTC_CNTL_TOUCH_PAD3_HOLD_M  (BIT(3))
+#define RTC_CNTL_TOUCH_PAD3_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD3_HOLD_S  3
+/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD2_HOLD    (BIT(2))
+#define RTC_CNTL_TOUCH_PAD2_HOLD_M  (BIT(2))
+#define RTC_CNTL_TOUCH_PAD2_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD2_HOLD_S  2
+/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD1_HOLD    (BIT(1))
+#define RTC_CNTL_TOUCH_PAD1_HOLD_M  (BIT(1))
+#define RTC_CNTL_TOUCH_PAD1_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD1_HOLD_S  1
+/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD0_HOLD    (BIT(0))
+#define RTC_CNTL_TOUCH_PAD0_HOLD_M  (BIT(0))
+#define RTC_CNTL_TOUCH_PAD0_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD0_HOLD_S  0
+
+#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0xDC)
+/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define RTC_CNTL_DIG_PAD_HOLD    0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
+#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_S  0
+
+#define RTC_CNTL_EXT_WAKEUP1_REG          (DR_REG_RTCCNTL_BASE + 0xE0)
+/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: clear ext wakeup1 status.*/
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR    (BIT(22))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M  (BIT(22))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V  0x1
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S  22
+/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */
+/*description: Bitmap to select RTC pads for ext wakeup1.*/
+#define RTC_CNTL_EXT_WAKEUP1_SEL    0x003FFFFF
+#define RTC_CNTL_EXT_WAKEUP1_SEL_M  ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S))
+#define RTC_CNTL_EXT_WAKEUP1_SEL_V  0x3FFFFF
+#define RTC_CNTL_EXT_WAKEUP1_SEL_S  0
+
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG          (DR_REG_RTCCNTL_BASE + 0xE4)
+/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */
+/*description: ext wakeup1 status.*/
+#define RTC_CNTL_EXT_WAKEUP1_STATUS    0x003FFFFF
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_M  ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_V  0x3FFFFF
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_S  0
+
+#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0xE8)
+/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_BROWN_OUT_DET    (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_V  0x1
+#define RTC_CNTL_BROWN_OUT_DET_S  31
+/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: enable brown out.*/
+#define RTC_CNTL_BROWN_OUT_ENA    (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_ENA_S  30
+/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: clear brown out counter.*/
+#define RTC_CNTL_BROWN_OUT_CNT_CLR    (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
+/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN    (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M  (BIT(28))
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V  0x1
+#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S  28
+/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 1:  4-pos reset.*/
+#define RTC_CNTL_BROWN_OUT_RST_SEL    (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_M  (BIT(27))
+#define RTC_CNTL_BROWN_OUT_RST_SEL_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_SEL_S  27
+/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: enable brown out reset.*/
+#define RTC_CNTL_BROWN_OUT_RST_ENA    (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
+/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
+/*description: brown out reset wait cycles.*/
+#define RTC_CNTL_BROWN_OUT_RST_WAIT    0x000003FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
+/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable power down RF when brown out happens.*/
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA    (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
+/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable close flash when brown out happens.*/
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA    (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
+/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */
+/*description: brown out interrupt wait cycles.*/
+#define RTC_CNTL_BROWN_OUT_INT_WAIT    0x000003FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
+
+#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0xEC)
+/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits.*/
+#define RTC_CNTL_TIMER_VALUE1_LOW    0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
+#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0xF0)
+/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits.*/
+#define RTC_CNTL_TIMER_VALUE1_HIGH    0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
+
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG          (DR_REG_RTCCNTL_BASE + 0xF4)
+/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: xtal 32k watch dog backup clock factor.*/
+#define RTC_CNTL_XTAL32K_CLK_FACTOR    0xFFFFFFFF
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_M  ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S))
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_V  0xFFFFFFFF
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_S  0
+
+#define RTC_CNTL_XTAL32K_CONF_REG          (DR_REG_RTCCNTL_BASE + 0xF8)
+/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: if restarted xtal32k period is smaller than this.*/
+#define RTC_CNTL_XTAL32K_STABLE_THRES    0x0000000F
+#define RTC_CNTL_XTAL32K_STABLE_THRES_M  ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S))
+#define RTC_CNTL_XTAL32K_STABLE_THRES_V  0xF
+#define RTC_CNTL_XTAL32K_STABLE_THRES_S  28
+/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
+/*description: If no clock detected for this amount of time.*/
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT    0x000000FF
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M  ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S))
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V  0xFF
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S  20
+/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
+/*description: cycles to wait to repower on xtal 32k.*/
+#define RTC_CNTL_XTAL32K_RESTART_WAIT    0x0000FFFF
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_M  ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S))
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_V  0xFFFF
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_S  4
+/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: cycles to wait to return normal xtal 32k.*/
+#define RTC_CNTL_XTAL32K_RETURN_WAIT    0x0000000F
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_M  ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S))
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_V  0xF
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_S  0
+
+#define RTC_CNTL_ULP_CP_TIMER_REG          (DR_REG_RTCCNTL_BASE + 0xFC)
+/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: ULP-coprocessor timer enable bit.*/
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN    (BIT(31))
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M  (BIT(31))
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V  0x1
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S  31
+/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */
+/*description: ULP-coprocessor wakeup by GPIO state clear.*/
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR    (BIT(30))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M  (BIT(30))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V  0x1
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S  30
+/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: ULP-coprocessor wakeup by GPIO enable.*/
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA    (BIT(29))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M  (BIT(29))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V  0x1
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S  29
+/* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */
+/*description: ULP-coprocessor PC initial address.*/
+#define RTC_CNTL_ULP_CP_PC_INIT    0x000007FF
+#define RTC_CNTL_ULP_CP_PC_INIT_M  ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S))
+#define RTC_CNTL_ULP_CP_PC_INIT_V  0x7FF
+#define RTC_CNTL_ULP_CP_PC_INIT_S  0
+
+#define RTC_CNTL_ULP_CP_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x100)
+/* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: Write 1 to start ULP-coprocessor.*/
+#define RTC_CNTL_ULP_CP_START_TOP    (BIT(31))
+#define RTC_CNTL_ULP_CP_START_TOP_M  (BIT(31))
+#define RTC_CNTL_ULP_CP_START_TOP_V  0x1
+#define RTC_CNTL_ULP_CP_START_TOP_S  31
+/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: ULP-coprocessor is started by SW.*/
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP    (BIT(30))
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M  (BIT(30))
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V  0x1
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S  30
+/* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: ulp coprocessor clk software reset.*/
+#define RTC_CNTL_ULP_CP_RESET    (BIT(29))
+#define RTC_CNTL_ULP_CP_RESET_M  (BIT(29))
+#define RTC_CNTL_ULP_CP_RESET_V  0x1
+#define RTC_CNTL_ULP_CP_RESET_S  29
+/* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: ulp coprocessor clk force on.*/
+#define RTC_CNTL_ULP_CP_CLK_FO    (BIT(28))
+#define RTC_CNTL_ULP_CP_CLK_FO_M  (BIT(28))
+#define RTC_CNTL_ULP_CP_CLK_FO_V  0x1
+#define RTC_CNTL_ULP_CP_CLK_FO_S  28
+/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR    (BIT(22))
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M  (BIT(22))
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V  0x1
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S  22
+/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */
+/*description: .*/
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE    0x000007FF
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M  ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S))
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V  0x7FF
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S  11
+/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */
+/*description: .*/
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT    0x000007FF
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M  ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S))
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V  0x7FF
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S  0
+
+#define RTC_CNTL_COCPU_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x104)
+/* RTC_CNTL_COCPU_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_COCPU_CLKGATE_EN    (BIT(27))
+#define RTC_CNTL_COCPU_CLKGATE_EN_M  (BIT(27))
+#define RTC_CNTL_COCPU_CLKGATE_EN_V  0x1
+#define RTC_CNTL_COCPU_CLKGATE_EN_S  27
+/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: trigger cocpu register interrupt.*/
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER    (BIT(26))
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M  (BIT(26))
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V  0x1
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S  26
+/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: done signal used by riscv to control timer. .*/
+#define RTC_CNTL_COCPU_DONE    (BIT(25))
+#define RTC_CNTL_COCPU_DONE_M  (BIT(25))
+#define RTC_CNTL_COCPU_DONE_V  0x1
+#define RTC_CNTL_COCPU_DONE_S  25
+/* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: select riscv done 0: select ulp done.*/
+#define RTC_CNTL_COCPU_DONE_FORCE    (BIT(24))
+#define RTC_CNTL_COCPU_DONE_FORCE_M  (BIT(24))
+#define RTC_CNTL_COCPU_DONE_FORCE_V  0x1
+#define RTC_CNTL_COCPU_DONE_FORCE_S  24
+/* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: 1: old ULP 0: new riscV.*/
+#define RTC_CNTL_COCPU_SEL    (BIT(23))
+#define RTC_CNTL_COCPU_SEL_M  (BIT(23))
+#define RTC_CNTL_COCPU_SEL_V  0x1
+#define RTC_CNTL_COCPU_SEL_S  23
+/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: to reset cocpu.*/
+#define RTC_CNTL_COCPU_SHUT_RESET_EN    (BIT(22))
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_M  (BIT(22))
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_V  0x1
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_S  22
+/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */
+/*description: time from shut cocpu to disable clk.*/
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS    0x000000FF
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M  ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S))
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V  0xFF
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S  14
+/* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: to shut cocpu.*/
+#define RTC_CNTL_COCPU_SHUT    (BIT(13))
+#define RTC_CNTL_COCPU_SHUT_M  (BIT(13))
+#define RTC_CNTL_COCPU_SHUT_V  0x1
+#define RTC_CNTL_COCPU_SHUT_S  13
+/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */
+/*description: time from start cocpu to give start interrupt.*/
+#define RTC_CNTL_COCPU_START_2_INTR_EN    0x0000003F
+#define RTC_CNTL_COCPU_START_2_INTR_EN_M  ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S))
+#define RTC_CNTL_COCPU_START_2_INTR_EN_V  0x3F
+#define RTC_CNTL_COCPU_START_2_INTR_EN_S  7
+/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */
+/*description: time from start cocpu to pull down reset.*/
+#define RTC_CNTL_COCPU_START_2_RESET_DIS    0x0000003F
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_M  ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S))
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_V  0x3F
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_S  1
+/* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: cocpu clk force on.*/
+#define RTC_CNTL_COCPU_CLK_FO    (BIT(0))
+#define RTC_CNTL_COCPU_CLK_FO_M  (BIT(0))
+#define RTC_CNTL_COCPU_CLK_FO_V  0x1
+#define RTC_CNTL_COCPU_CLK_FO_S  0
+
+#define RTC_CNTL_TOUCH_CTRL1_REG          (DR_REG_RTCCNTL_BASE + 0x108)
+/* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */
+/*description: the meas length (in 8MHz).*/
+#define RTC_CNTL_TOUCH_MEAS_NUM    0x0000FFFF
+#define RTC_CNTL_TOUCH_MEAS_NUM_M  ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S))
+#define RTC_CNTL_TOUCH_MEAS_NUM_V  0xFFFF
+#define RTC_CNTL_TOUCH_MEAS_NUM_S  16
+/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */
+/*description: sleep cycles for timer.*/
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES    0x0000FFFF
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M  ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S))
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V  0xFFFF
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S  0
+
+#define RTC_CNTL_TOUCH_CTRL2_REG          (DR_REG_RTCCNTL_BASE + 0x10C)
+/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: touch clock enable.*/
+#define RTC_CNTL_TOUCH_CLKGATE_EN    (BIT(31))
+#define RTC_CNTL_TOUCH_CLKGATE_EN_M  (BIT(31))
+#define RTC_CNTL_TOUCH_CLKGATE_EN_V  0x1
+#define RTC_CNTL_TOUCH_CLKGATE_EN_S  31
+/* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: touch clock force on.*/
+#define RTC_CNTL_TOUCH_CLK_FO    (BIT(30))
+#define RTC_CNTL_TOUCH_CLK_FO_M  (BIT(30))
+#define RTC_CNTL_TOUCH_CLK_FO_V  0x1
+#define RTC_CNTL_TOUCH_CLK_FO_S  30
+/* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: reset upgrade touch.*/
+#define RTC_CNTL_TOUCH_RESET    (BIT(29))
+#define RTC_CNTL_TOUCH_RESET_M  (BIT(29))
+#define RTC_CNTL_TOUCH_RESET_V  0x1
+#define RTC_CNTL_TOUCH_RESET_S  29
+/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: force touch timer done.*/
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE    0x00000003
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M  ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V)<<(RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S))
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V  0x3
+#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S  27
+/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */
+/*description: when a touch pad is active.*/
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV    0x00000003
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M  ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S))
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V  0x3
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S  25
+/* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */
+/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD.*/
+#define RTC_CNTL_TOUCH_XPD_WAIT    0x000000FF
+#define RTC_CNTL_TOUCH_XPD_WAIT_M  ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S))
+#define RTC_CNTL_TOUCH_XPD_WAIT_V  0xFF
+#define RTC_CNTL_TOUCH_XPD_WAIT_S  17
+/* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1: to start touch fsm by SW.*/
+#define RTC_CNTL_TOUCH_START_FORCE    (BIT(16))
+#define RTC_CNTL_TOUCH_START_FORCE_M  (BIT(16))
+#define RTC_CNTL_TOUCH_START_FORCE_V  0x1
+#define RTC_CNTL_TOUCH_START_FORCE_S  16
+/* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: start touch fsm.*/
+#define RTC_CNTL_TOUCH_START_EN    (BIT(15))
+#define RTC_CNTL_TOUCH_START_EN_M  (BIT(15))
+#define RTC_CNTL_TOUCH_START_EN_V  0x1
+#define RTC_CNTL_TOUCH_START_EN_S  15
+/* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm.*/
+#define RTC_CNTL_TOUCH_START_FSM_EN    (BIT(14))
+#define RTC_CNTL_TOUCH_START_FSM_EN_M  (BIT(14))
+#define RTC_CNTL_TOUCH_START_FSM_EN_V  0x1
+#define RTC_CNTL_TOUCH_START_FSM_EN_S  14
+/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: touch timer enable bit.*/
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN    (BIT(13))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M  (BIT(13))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V  0x1
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S  13
+/* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: 1:use self bias 0:use bandgap bias.*/
+#define RTC_CNTL_TOUCH_DBIAS    (BIT(12))
+#define RTC_CNTL_TOUCH_DBIAS_M  (BIT(12))
+#define RTC_CNTL_TOUCH_DBIAS_V  0x1
+#define RTC_CNTL_TOUCH_DBIAS_S  12
+/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: TOUCH pad0 reference cap.*/
+#define RTC_CNTL_TOUCH_REFC    0x00000007
+#define RTC_CNTL_TOUCH_REFC_M  ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S))
+#define RTC_CNTL_TOUCH_REFC_V  0x7
+#define RTC_CNTL_TOUCH_REFC_S  9
+/* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: TOUCH_XPD_BIAS.*/
+#define RTC_CNTL_TOUCH_XPD_BIAS    (BIT(8))
+#define RTC_CNTL_TOUCH_XPD_BIAS_M  (BIT(8))
+#define RTC_CNTL_TOUCH_XPD_BIAS_V  0x1
+#define RTC_CNTL_TOUCH_XPD_BIAS_S  8
+/* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
+/*description: TOUCH_DREFH.*/
+#define RTC_CNTL_TOUCH_DREFH    0x00000003
+#define RTC_CNTL_TOUCH_DREFH_M  ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S))
+#define RTC_CNTL_TOUCH_DREFH_V  0x3
+#define RTC_CNTL_TOUCH_DREFH_S  6
+/* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */
+/*description: TOUCH_DREFL.*/
+#define RTC_CNTL_TOUCH_DREFL    0x00000003
+#define RTC_CNTL_TOUCH_DREFL_M  ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S))
+#define RTC_CNTL_TOUCH_DREFL_V  0x3
+#define RTC_CNTL_TOUCH_DREFL_S  4
+/* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: TOUCH_DRANGE.*/
+#define RTC_CNTL_TOUCH_DRANGE    0x00000003
+#define RTC_CNTL_TOUCH_DRANGE_M  ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S))
+#define RTC_CNTL_TOUCH_DRANGE_V  0x3
+#define RTC_CNTL_TOUCH_DRANGE_S  2
+
+#define RTC_CNTL_TOUCH_SCAN_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x110)
+/* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */
+/*description: select out ring pad.*/
+#define RTC_CNTL_TOUCH_OUT_RING    0x0000000F
+#define RTC_CNTL_TOUCH_OUT_RING_M  ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S))
+#define RTC_CNTL_TOUCH_OUT_RING_V  0xF
+#define RTC_CNTL_TOUCH_OUT_RING_S  28
+/* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: touch7 buffer driver strength.*/
+#define RTC_CNTL_TOUCH_BUFDRV    0x00000007
+#define RTC_CNTL_TOUCH_BUFDRV_M  ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S))
+#define RTC_CNTL_TOUCH_BUFDRV_V  0x7
+#define RTC_CNTL_TOUCH_BUFDRV_S  25
+/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */
+/*description: touch scan mode pad enable map.*/
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP    0x00007FFF
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M  ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S))
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V  0x7FFF
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S  10
+/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: touch pad14 will be used as shield.*/
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN    (BIT(9))
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M  (BIT(9))
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V  0x1
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: inactive touch pads connect to 1: gnd 0: HighZ.*/
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION    (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S  8
+/* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: touch pad0 will be used to de-noise.*/
+#define RTC_CNTL_TOUCH_DENOISE_EN    (BIT(2))
+#define RTC_CNTL_TOUCH_DENOISE_EN_M  (BIT(2))
+#define RTC_CNTL_TOUCH_DENOISE_EN_V  0x1
+#define RTC_CNTL_TOUCH_DENOISE_EN_S  2
+/* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */
+/*description: De-noise resolution: 12/10/8/4 bit.*/
+#define RTC_CNTL_TOUCH_DENOISE_RES    0x00000003
+#define RTC_CNTL_TOUCH_DENOISE_RES_M  ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S))
+#define RTC_CNTL_TOUCH_DENOISE_RES_V  0x3
+#define RTC_CNTL_TOUCH_DENOISE_RES_S  0
+
+#define RTC_CNTL_TOUCH_SLP_THRES_REG          (DR_REG_RTCCNTL_BASE + 0x114)
+/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hf ; */
+/*description:  .*/
+#define RTC_CNTL_TOUCH_SLP_PAD    0x0000001F
+#define RTC_CNTL_TOUCH_SLP_PAD_M  ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S))
+#define RTC_CNTL_TOUCH_SLP_PAD_V  0x1F
+#define RTC_CNTL_TOUCH_SLP_PAD_S  27
+/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: sleep pad approach function enable.*/
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN    (BIT(26))
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M  (BIT(26))
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V  0x1
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S  26
+/* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: the threshold for sleep touch pad.*/
+#define RTC_CNTL_TOUCH_SLP_TH    0x003FFFFF
+#define RTC_CNTL_TOUCH_SLP_TH_M  ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S))
+#define RTC_CNTL_TOUCH_SLP_TH_V  0x3FFFFF
+#define RTC_CNTL_TOUCH_SLP_TH_S  0
+
+#define RTC_CNTL_TOUCH_APPROACH_REG          (DR_REG_RTCCNTL_BASE + 0x118)
+/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */
+/*description: approach pads total meas times.*/
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME    0x000000FF
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M  ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S))
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V  0xFF
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S  24
+/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear touch slp channel.*/
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR    (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M  (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V  0x1
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S  23
+
+#define RTC_CNTL_TOUCH_FILTER_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x11C)
+/* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: touch filter enable.*/
+#define RTC_CNTL_TOUCH_FILTER_EN    (BIT(31))
+#define RTC_CNTL_TOUCH_FILTER_EN_M  (BIT(31))
+#define RTC_CNTL_TOUCH_FILTER_EN_V  0x1
+#define RTC_CNTL_TOUCH_FILTER_EN_S  31
+/* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */
+/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter.*/
+#define RTC_CNTL_TOUCH_FILTER_MODE    0x00000007
+#define RTC_CNTL_TOUCH_FILTER_MODE_M  ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S))
+#define RTC_CNTL_TOUCH_FILTER_MODE_V  0x7
+#define RTC_CNTL_TOUCH_FILTER_MODE_S  28
+/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */
+/*description: debounce counter.*/
+#define RTC_CNTL_TOUCH_DEBOUNCE    0x00000007
+#define RTC_CNTL_TOUCH_DEBOUNCE_M  ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S))
+#define RTC_CNTL_TOUCH_DEBOUNCE_V  0x7
+#define RTC_CNTL_TOUCH_DEBOUNCE_S  25
+/* RTC_CNTL_TOUCH_CONFIG3 : R/W ;bitpos:[24:23] ;default: 2'd1 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_CONFIG3 0x00000003
+#define RTC_CNTL_TOUCH_CONFIG3_M ((RTC_CNTL_TOUCH_CONFIG3_V) << (RTC_CNTL_TOUCH_CONFIG3_S))
+#define RTC_CNTL_TOUCH_CONFIG3_V 0x3
+#define RTC_CNTL_TOUCH_CONFIG3_S 23
+/* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_NOISE_THRES    0x00000003
+#define RTC_CNTL_TOUCH_NOISE_THRES_M  ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S))
+#define RTC_CNTL_TOUCH_NOISE_THRES_V  0x3
+#define RTC_CNTL_TOUCH_NOISE_THRES_S  21
+/* RTC_CNTL_TOUCH_CONFIG2 : R/W ;bitpos:[20:19] ;default: 2'd1 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_CONFIG2 0x00000003
+#define RTC_CNTL_TOUCH_CONFIG2_M ((RTC_CNTL_TOUCH_CONFIG2_V) << (RTC_CNTL_TOUCH_CONFIG2_S))
+#define RTC_CNTL_TOUCH_CONFIG2_V 0x3
+#define RTC_CNTL_TOUCH_CONFIG2_S 19
+/* RTC_CNTL_TOUCH_CONFIG1 : R/W ;bitpos:[18:15] ;default: 4'd5 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_CONFIG1 0x0000000F
+#define RTC_CNTL_TOUCH_CONFIG1_M ((RTC_CNTL_TOUCH_CONFIG1_V) << (RTC_CNTL_TOUCH_CONFIG1_S))
+#define RTC_CNTL_TOUCH_CONFIG1_V 0xF
+#define RTC_CNTL_TOUCH_CONFIG1_S 15
+/* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */
+/*description: touch jitter step.*/
+#define RTC_CNTL_TOUCH_JITTER_STEP    0x0000000F
+#define RTC_CNTL_TOUCH_JITTER_STEP_M  ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S))
+#define RTC_CNTL_TOUCH_JITTER_STEP_V  0xF
+#define RTC_CNTL_TOUCH_JITTER_STEP_S  11
+/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_SMOOTH_LVL    0x00000003
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_M  ((RTC_CNTL_TOUCH_SMOOTH_LVL_V)<<(RTC_CNTL_TOUCH_SMOOTH_LVL_S))
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_V  0x3
+#define RTC_CNTL_TOUCH_SMOOTH_LVL_S  9
+/* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES    (BIT(8))
+#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M  (BIT(8))
+#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V  0x1
+#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S  8
+/* RTC_CNTL_TOUCH_BYPASS_NN_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_BYPASS_NN_THRES (BIT(7))
+#define RTC_CNTL_TOUCH_BYPASS_NN_THRES_M (BIT(7))
+#define RTC_CNTL_TOUCH_BYPASS_NN_THRES_V 0x1
+#define RTC_CNTL_TOUCH_BYPASS_NN_THRES_S 7
+
+#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x120)
+/* RTC_CNTL_SW_HW_USB_PHY_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_SW_HW_USB_PHY_SEL    (BIT(20))
+#define RTC_CNTL_SW_HW_USB_PHY_SEL_M  (BIT(20))
+#define RTC_CNTL_SW_HW_USB_PHY_SEL_V  0x1
+#define RTC_CNTL_SW_HW_USB_PHY_SEL_S  20
+/* RTC_CNTL_SW_USB_PHY_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_SW_USB_PHY_SEL    (BIT(19))
+#define RTC_CNTL_SW_USB_PHY_SEL_M  (BIT(19))
+#define RTC_CNTL_SW_USB_PHY_SEL_V  0x1
+#define RTC_CNTL_SW_USB_PHY_SEL_S  19
+/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_IO_MUX_RESET_DISABLE    (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_M  (BIT(18))
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_V  0x1
+#define RTC_CNTL_IO_MUX_RESET_DISABLE_S  18
+/* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_RESET_DISABLE    (BIT(17))
+#define RTC_CNTL_USB_RESET_DISABLE_M  (BIT(17))
+#define RTC_CNTL_USB_RESET_DISABLE_V  0x1
+#define RTC_CNTL_USB_RESET_DISABLE_S  17
+/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_TX_EN_OVERRIDE    (BIT(16))
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_M  (BIT(16))
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_V  0x1
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_S  16
+/* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_TX_EN    (BIT(15))
+#define RTC_CNTL_USB_TX_EN_M  (BIT(15))
+#define RTC_CNTL_USB_TX_EN_V  0x1
+#define RTC_CNTL_USB_TX_EN_S  15
+/* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_TXP    (BIT(14))
+#define RTC_CNTL_USB_TXP_M  (BIT(14))
+#define RTC_CNTL_USB_TXP_V  0x1
+#define RTC_CNTL_USB_TXP_S  14
+/* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_TXM    (BIT(13))
+#define RTC_CNTL_USB_TXM_M  (BIT(13))
+#define RTC_CNTL_USB_TXM_V  0x1
+#define RTC_CNTL_USB_TXM_S  13
+/* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_PAD_ENABLE    (BIT(12))
+#define RTC_CNTL_USB_PAD_ENABLE_M  (BIT(12))
+#define RTC_CNTL_USB_PAD_ENABLE_V  0x1
+#define RTC_CNTL_USB_PAD_ENABLE_S  12
+/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE    (BIT(11))
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M  (BIT(11))
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V  0x1
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S  11
+/* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_PULLUP_VALUE    (BIT(10))
+#define RTC_CNTL_USB_PULLUP_VALUE_M  (BIT(10))
+#define RTC_CNTL_USB_PULLUP_VALUE_V  0x1
+#define RTC_CNTL_USB_PULLUP_VALUE_S  10
+/* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_DM_PULLDOWN    (BIT(9))
+#define RTC_CNTL_USB_DM_PULLDOWN_M  (BIT(9))
+#define RTC_CNTL_USB_DM_PULLDOWN_V  0x1
+#define RTC_CNTL_USB_DM_PULLDOWN_S  9
+/* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_DM_PULLUP    (BIT(8))
+#define RTC_CNTL_USB_DM_PULLUP_M  (BIT(8))
+#define RTC_CNTL_USB_DM_PULLUP_V  0x1
+#define RTC_CNTL_USB_DM_PULLUP_S  8
+/* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_DP_PULLDOWN    (BIT(7))
+#define RTC_CNTL_USB_DP_PULLDOWN_M  (BIT(7))
+#define RTC_CNTL_USB_DP_PULLDOWN_V  0x1
+#define RTC_CNTL_USB_DP_PULLDOWN_S  7
+/* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_DP_PULLUP    (BIT(6))
+#define RTC_CNTL_USB_DP_PULLUP_M  (BIT(6))
+#define RTC_CNTL_USB_DP_PULLUP_V  0x1
+#define RTC_CNTL_USB_DP_PULLUP_S  6
+/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE    (BIT(5))
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M  (BIT(5))
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V  0x1
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S  5
+/* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_VREF_OVERRIDE    (BIT(4))
+#define RTC_CNTL_USB_VREF_OVERRIDE_M  (BIT(4))
+#define RTC_CNTL_USB_VREF_OVERRIDE_V  0x1
+#define RTC_CNTL_USB_VREF_OVERRIDE_S  4
+/* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_VREFL    0x00000003
+#define RTC_CNTL_USB_VREFL_M  ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S))
+#define RTC_CNTL_USB_VREFL_V  0x3
+#define RTC_CNTL_USB_VREFL_S  2
+/* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: .*/
+#define RTC_CNTL_USB_VREFH    0x00000003
+#define RTC_CNTL_USB_VREFH_M  ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S))
+#define RTC_CNTL_USB_VREFH_V  0x3
+#define RTC_CNTL_USB_VREFH_S  0
+
+#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x124)
+/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_TIMEOUT_EN    (BIT(22))
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_M  (BIT(22))
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_V  0x1
+#define RTC_CNTL_TOUCH_TIMEOUT_EN_S  22
+/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM    0x003FFFFF
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M  ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V)<<(RTC_CNTL_TOUCH_TIMEOUT_NUM_S))
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V  0x3FFFFF
+#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S  0
+
+#define RTC_CNTL_SLP_REJECT_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x128)
+/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: sleep reject cause.*/
+#define RTC_CNTL_REJECT_CAUSE    0x0003FFFF
+#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
+#define RTC_CNTL_REJECT_CAUSE_V  0x3FFFF
+#define RTC_CNTL_REJECT_CAUSE_S  0
+
+#define RTC_CNTL_OPTION1_REG          (DR_REG_RTCCNTL_BASE + 0x12C)
+/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT    (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M  (BIT(0))
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V  0x1
+#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S  0
+
+#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG          (DR_REG_RTCCNTL_BASE + 0x130)
+/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */
+/*description: sleep wakeup cause.*/
+#define RTC_CNTL_WAKEUP_CAUSE    0x0001FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
+#define RTC_CNTL_WAKEUP_CAUSE_V  0x1FFFF
+#define RTC_CNTL_WAKEUP_CAUSE_S  0
+
+#define RTC_CNTL_ULP_CP_TIMER_1_REG          (DR_REG_RTCCNTL_BASE + 0x134)
+/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */
+/*description: sleep cycles for ULP-coprocessor timer.*/
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE    0x00FFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  8
+
+#define RTC_CNTL_INT_ENA_W1TS_REG          (DR_REG_RTCCNTL_BASE + 0x138)
+/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS    (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M  (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enable gitch det interrupt.*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS    (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S  19
+/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: enable touch timeout interrupt.*/
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS    (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M  (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S  18
+/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: enable cocpu trap interrupt.*/
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS    (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt.*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS    (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S  16
+/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA_W1TS    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TS_S  15
+/* RTC_CNTL_SARADC2_INT_ENA_W1TS : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable saradc2 interrupt.*/
+#define RTC_CNTL_SARADC2_INT_ENA_W1TS    (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ENA_W1TS_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SARADC2_INT_ENA_W1TS_S  14
+/* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: enable riscV cocpu interrupt.*/
+#define RTC_CNTL_COCPU_INT_ENA_W1TS    (BIT(13))
+#define RTC_CNTL_COCPU_INT_ENA_W1TS_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_COCPU_INT_ENA_W1TS_S  13
+/* RTC_CNTL_TSENS_INT_ENA_W1TS : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: enable tsens interrupt.*/
+#define RTC_CNTL_TSENS_INT_ENA_W1TS    (BIT(12))
+#define RTC_CNTL_TSENS_INT_ENA_W1TS_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_TSENS_INT_ENA_W1TS_S  12
+/* RTC_CNTL_SARADC1_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: enable saradc1 interrupt.*/
+#define RTC_CNTL_SARADC1_INT_ENA_W1TS    (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ENA_W1TS_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SARADC1_INT_ENA_W1TS_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable touch inactive interrupt.*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS    (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable touch active interrupt.*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS    (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable touch done interrupt.*/
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS    (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S  6
+/* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable ULP-coprocessor interrupt.*/
+#define RTC_CNTL_ULP_CP_INT_ENA_W1TS    (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S  5
+/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable touch scan done interrupt.*/
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS    (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M  (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S  4
+/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA_W1TS    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TS_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable SDIO idle interrupt.*/
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS    (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S  2
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S  0
+
+#define RTC_CNTL_INT_ENA_W1TC_REG          (DR_REG_RTCCNTL_BASE + 0x13C)
+/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC    (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M  (BIT(20))
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S  20
+/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: enable gitch det interrupt.*/
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC    (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M  (BIT(19))
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S  19
+/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: enable touch timeout interrupt.*/
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC    (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M  (BIT(18))
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S  18
+/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: enable cocpu trap interrupt.*/
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC    (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable xtal32k_dead  interrupt.*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC    (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S  16
+/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt.*/
+#define RTC_CNTL_SWD_INT_ENA_W1TC    (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_W1TC_S  15
+/* RTC_CNTL_SARADC2_INT_ENA_W1TC : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable saradc2 interrupt.*/
+#define RTC_CNTL_SARADC2_INT_ENA_W1TC    (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ENA_W1TC_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SARADC2_INT_ENA_W1TC_S  14
+/* RTC_CNTL_COCPU_INT_ENA_W1TC : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: enable riscV cocpu interrupt.*/
+#define RTC_CNTL_COCPU_INT_ENA_W1TC    (BIT(13))
+#define RTC_CNTL_COCPU_INT_ENA_W1TC_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_COCPU_INT_ENA_W1TC_S  13
+/* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: enable tsens interrupt.*/
+#define RTC_CNTL_TSENS_INT_ENA_W1TC    (BIT(12))
+#define RTC_CNTL_TSENS_INT_ENA_W1TC_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_TSENS_INT_ENA_W1TC_S  12
+/* RTC_CNTL_SARADC1_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: enable saradc1 interrupt.*/
+#define RTC_CNTL_SARADC1_INT_ENA_W1TC    (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ENA_W1TC_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SARADC1_INT_ENA_W1TC_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt.*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC    (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt.*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC    (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable touch inactive interrupt.*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC    (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable touch active interrupt.*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC    (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable touch done interrupt.*/
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC    (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S  6
+/* RTC_CNTL_ULP_CP_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable ULP-coprocessor interrupt.*/
+#define RTC_CNTL_ULP_CP_INT_ENA_W1TC    (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S  5
+/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable touch scan done interrupt.*/
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC    (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M  (BIT(4))
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S  4
+/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt.*/
+#define RTC_CNTL_WDT_INT_ENA_W1TC    (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_W1TC_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable SDIO idle interrupt.*/
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC    (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S  2
+/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt.*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC    (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt.*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC    (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S  0
+
+#define RTC_CNTL_RETENTION_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x140)
+/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:25] ;default: 7'd20 ; */
+/*description: wait cycles for rention operation.*/
+#define RTC_CNTL_RETENTION_WAIT    0x0000007F
+#define RTC_CNTL_RETENTION_WAIT_M  ((RTC_CNTL_RETENTION_WAIT_V)<<(RTC_CNTL_RETENTION_WAIT_S))
+#define RTC_CNTL_RETENTION_WAIT_V  0x7F
+#define RTC_CNTL_RETENTION_WAIT_S  25
+/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: .*/
+#define RTC_CNTL_RETENTION_EN    (BIT(24))
+#define RTC_CNTL_RETENTION_EN_M  (BIT(24))
+#define RTC_CNTL_RETENTION_EN_V  0x1
+#define RTC_CNTL_RETENTION_EN_S  24
+/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W ;bitpos:[23:20] ;default: 4'd3 ; */
+/*description: .*/
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT    0x0000000F
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M  ((RTC_CNTL_RETENTION_CLKOFF_WAIT_V)<<(RTC_CNTL_RETENTION_CLKOFF_WAIT_S))
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V  0xF
+#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S  20
+/* RTC_CNTL_RETENTION_DONE_WAIT : R/W ;bitpos:[19:17] ;default: 3'd2 ; */
+/*description: .*/
+#define RTC_CNTL_RETENTION_DONE_WAIT    0x00000007
+#define RTC_CNTL_RETENTION_DONE_WAIT_M  ((RTC_CNTL_RETENTION_DONE_WAIT_V)<<(RTC_CNTL_RETENTION_DONE_WAIT_S))
+#define RTC_CNTL_RETENTION_DONE_WAIT_V  0x7
+#define RTC_CNTL_RETENTION_DONE_WAIT_S  17
+/* RTC_CNTL_RETENTION_CLK_SEL : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_RETENTION_CLK_SEL    (BIT(16))
+#define RTC_CNTL_RETENTION_CLK_SEL_M  (BIT(16))
+#define RTC_CNTL_RETENTION_CLK_SEL_V  0x1
+#define RTC_CNTL_RETENTION_CLK_SEL_S  16
+/* RTC_CNTL_RETENTION_TARGET : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: .*/
+#define RTC_CNTL_RETENTION_TARGET    0x00000003
+#define RTC_CNTL_RETENTION_TARGET_M  ((RTC_CNTL_RETENTION_TARGET_V)<<(RTC_CNTL_RETENTION_TARGET_S))
+#define RTC_CNTL_RETENTION_TARGET_V  0x3
+#define RTC_CNTL_RETENTION_TARGET_S  14
+/* RTC_CNTL_RETENTION_TAG_MODE : R/W ;bitpos:[13:10] ;default: 4'd0 ; */
+/*description: .*/
+#define RTC_CNTL_RETENTION_TAG_MODE    0x0000000F
+#define RTC_CNTL_RETENTION_TAG_MODE_M  ((RTC_CNTL_RETENTION_TAG_MODE_V)<<(RTC_CNTL_RETENTION_TAG_MODE_S))
+#define RTC_CNTL_RETENTION_TAG_MODE_V  0xF
+#define RTC_CNTL_RETENTION_TAG_MODE_S  10
+
+#define RTC_CNTL_PG_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x144)
+/* RTC_CNTL_POWER_GLITCH_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_POWER_GLITCH_EN    (BIT(31))
+#define RTC_CNTL_POWER_GLITCH_EN_M  (BIT(31))
+#define RTC_CNTL_POWER_GLITCH_EN_V  0x1
+#define RTC_CNTL_POWER_GLITCH_EN_S  31
+/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: select use analog fib signal.*/
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL    (BIT(30))
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M  (BIT(30))
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V  0x1
+#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S  30
+/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU    (BIT(29))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M  (BIT(29))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V  0x1
+#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S  29
+/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD    (BIT(28))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M  (BIT(28))
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V  0x1
+#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S  28
+/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */
+/*description: .*/
+#define RTC_CNTL_POWER_GLITCH_DSENSE    0x00000003
+#define RTC_CNTL_POWER_GLITCH_DSENSE_M  ((RTC_CNTL_POWER_GLITCH_DSENSE_V)<<(RTC_CNTL_POWER_GLITCH_DSENSE_S))
+#define RTC_CNTL_POWER_GLITCH_DSENSE_V  0x3
+#define RTC_CNTL_POWER_GLITCH_DSENSE_S  26
+
+#define RTC_CNTL_FIB_SEL_REG          (DR_REG_RTCCNTL_BASE + 0x148)
+/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
+/*description: .*/
+#define RTC_CNTL_FIB_SEL    0x00000007
+#define RTC_CNTL_FIB_SEL_M  ((RTC_CNTL_FIB_SEL_V)<<(RTC_CNTL_FIB_SEL_S))
+#define RTC_CNTL_FIB_SEL_V  0x7
+#define RTC_CNTL_FIB_SEL_S  0
+
+#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
+#define RTC_CNTL_FIB_BOD_RST BIT(1)
+#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
+
+#define RTC_CNTL_TOUCH_DAC_REG          (DR_REG_RTCCNTL_BASE + 0x14C)
+/* RTC_CNTL_TOUCH_PAD0_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD0_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD0_DAC_M  ((RTC_CNTL_TOUCH_PAD0_DAC_V)<<(RTC_CNTL_TOUCH_PAD0_DAC_S))
+#define RTC_CNTL_TOUCH_PAD0_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD0_DAC_S  29
+/* RTC_CNTL_TOUCH_PAD1_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD1_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD1_DAC_M  ((RTC_CNTL_TOUCH_PAD1_DAC_V)<<(RTC_CNTL_TOUCH_PAD1_DAC_S))
+#define RTC_CNTL_TOUCH_PAD1_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD1_DAC_S  26
+/* RTC_CNTL_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD2_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD2_DAC_M  ((RTC_CNTL_TOUCH_PAD2_DAC_V)<<(RTC_CNTL_TOUCH_PAD2_DAC_S))
+#define RTC_CNTL_TOUCH_PAD2_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD2_DAC_S  23
+/* RTC_CNTL_TOUCH_PAD3_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD3_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD3_DAC_M  ((RTC_CNTL_TOUCH_PAD3_DAC_V)<<(RTC_CNTL_TOUCH_PAD3_DAC_S))
+#define RTC_CNTL_TOUCH_PAD3_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD3_DAC_S  20
+/* RTC_CNTL_TOUCH_PAD4_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD4_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD4_DAC_M  ((RTC_CNTL_TOUCH_PAD4_DAC_V)<<(RTC_CNTL_TOUCH_PAD4_DAC_S))
+#define RTC_CNTL_TOUCH_PAD4_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD4_DAC_S  17
+/* RTC_CNTL_TOUCH_PAD5_DAC : R/W ;bitpos:[16:14] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD5_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD5_DAC_M  ((RTC_CNTL_TOUCH_PAD5_DAC_V)<<(RTC_CNTL_TOUCH_PAD5_DAC_S))
+#define RTC_CNTL_TOUCH_PAD5_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD5_DAC_S  14
+/* RTC_CNTL_TOUCH_PAD6_DAC : R/W ;bitpos:[13:11] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD6_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD6_DAC_M  ((RTC_CNTL_TOUCH_PAD6_DAC_V)<<(RTC_CNTL_TOUCH_PAD6_DAC_S))
+#define RTC_CNTL_TOUCH_PAD6_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD6_DAC_S  11
+/* RTC_CNTL_TOUCH_PAD7_DAC : R/W ;bitpos:[10:8] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD7_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD7_DAC_M  ((RTC_CNTL_TOUCH_PAD7_DAC_V)<<(RTC_CNTL_TOUCH_PAD7_DAC_S))
+#define RTC_CNTL_TOUCH_PAD7_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD7_DAC_S  8
+/* RTC_CNTL_TOUCH_PAD8_DAC : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD8_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD8_DAC_M  ((RTC_CNTL_TOUCH_PAD8_DAC_V)<<(RTC_CNTL_TOUCH_PAD8_DAC_S))
+#define RTC_CNTL_TOUCH_PAD8_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD8_DAC_S  5
+/* RTC_CNTL_TOUCH_PAD9_DAC : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD9_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD9_DAC_M  ((RTC_CNTL_TOUCH_PAD9_DAC_V)<<(RTC_CNTL_TOUCH_PAD9_DAC_S))
+#define RTC_CNTL_TOUCH_PAD9_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD9_DAC_S  2
+
+#define RTC_CNTL_TOUCH_DAC1_REG          (DR_REG_RTCCNTL_BASE + 0x150)
+/* RTC_CNTL_TOUCH_PAD10_DAC : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD10_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD10_DAC_M  ((RTC_CNTL_TOUCH_PAD10_DAC_V)<<(RTC_CNTL_TOUCH_PAD10_DAC_S))
+#define RTC_CNTL_TOUCH_PAD10_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD10_DAC_S  29
+/* RTC_CNTL_TOUCH_PAD11_DAC : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD11_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD11_DAC_M  ((RTC_CNTL_TOUCH_PAD11_DAC_V)<<(RTC_CNTL_TOUCH_PAD11_DAC_S))
+#define RTC_CNTL_TOUCH_PAD11_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD11_DAC_S  26
+/* RTC_CNTL_TOUCH_PAD12_DAC : R/W ;bitpos:[25:23] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD12_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD12_DAC_M  ((RTC_CNTL_TOUCH_PAD12_DAC_V)<<(RTC_CNTL_TOUCH_PAD12_DAC_S))
+#define RTC_CNTL_TOUCH_PAD12_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD12_DAC_S  23
+/* RTC_CNTL_TOUCH_PAD13_DAC : R/W ;bitpos:[22:20] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD13_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD13_DAC_M  ((RTC_CNTL_TOUCH_PAD13_DAC_V)<<(RTC_CNTL_TOUCH_PAD13_DAC_S))
+#define RTC_CNTL_TOUCH_PAD13_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD13_DAC_S  20
+/* RTC_CNTL_TOUCH_PAD14_DAC : R/W ;bitpos:[19:17] ;default: 3'd0 ; */
+/*description: .*/
+#define RTC_CNTL_TOUCH_PAD14_DAC    0x00000007
+#define RTC_CNTL_TOUCH_PAD14_DAC_M  ((RTC_CNTL_TOUCH_PAD14_DAC_V)<<(RTC_CNTL_TOUCH_PAD14_DAC_S))
+#define RTC_CNTL_TOUCH_PAD14_DAC_V  0x7
+#define RTC_CNTL_TOUCH_PAD14_DAC_S  17
+
+#define RTC_CNTL_COCPU_DISABLE_REG          (DR_REG_RTCCNTL_BASE + 0x154)
+/* RTC_CNTL_DISABLE_RTC_CPU : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define RTC_CNTL_DISABLE_RTC_CPU    (BIT(31))
+#define RTC_CNTL_DISABLE_RTC_CPU_M  (BIT(31))
+#define RTC_CNTL_DISABLE_RTC_CPU_V  0x1
+#define RTC_CNTL_DISABLE_RTC_CPU_S  31
+
+/*
+Due to the LDO slaves, RTC_CNTL_DATE_REG[18:13] can only be used for LDO adjustment.
+*/
+#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x1FC)
+/* RTC_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101271 ; */
+/*description: .*/
+#define RTC_CNTL_DATE    0x0FFFFFFF
+#define RTC_CNTL_DATE_M  ((RTC_CNTL_DATE_V)<<(RTC_CNTL_DATE_S))
+#define RTC_CNTL_DATE_V  0xFFFFFFF
+#define RTC_CNTL_DATE_S  0
+/*LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ;*/
+/*description: .*/
+#define RTC_CNTL_SLAVE_PD    0x0000003F
+#define RTC_CNTL_SLAVE_PD_M  ((RTC_CNTL_SLAVE_PD_V)<<(RTC_CNTL_SLAVE_PD_S))
+#define RTC_CNTL_SLAVE_PD_V  0x3F
+#define RTC_CNTL_SLAVE_PD_S  13
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_CNTL_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/rtc_cntl_struct.h b/components/soc/esp32s3/register/soc/rtc_cntl_struct.h
new file mode 100644
index 00000000000..a92633ec86b
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/rtc_cntl_struct.h
@@ -0,0 +1,1051 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_RTC_CNTL_STRUCT_H_
+#define _SOC_RTC_CNTL_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct rtc_cntl_dev_s {
+    union {
+        struct {
+            uint32_t sw_stall_appcpu_c0            :    2;  /*{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
+            uint32_t sw_stall_procpu_c0            :    2;  /*{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
+            uint32_t sw_appcpu_rst                 :    1;  /*APP CPU SW reset*/
+            uint32_t sw_procpu_rst                 :    1;  /*PRO CPU SW reset*/
+            uint32_t bb_i2c_force_pd               :    1;  /*BB_I2C force power down*/
+            uint32_t bb_i2c_force_pu               :    1;  /*BB_I2C force power up*/
+            uint32_t bbpll_i2c_force_pd            :    1;  /*BB_PLL _I2C force power down*/
+            uint32_t bbpll_i2c_force_pu            :    1;  /*BB_PLL_I2C force power up*/
+            uint32_t bbpll_force_pd                :    1;  /*BB_PLL force power down*/
+            uint32_t bbpll_force_pu                :    1;  /*BB_PLL force power up*/
+            uint32_t xtl_force_pd                  :    1;  /*crystall force power down*/
+            uint32_t xtl_force_pu                  :    1;  /*crystall force power up*/
+            uint32_t xtl_en_wait                   :    4;  /*wait bias_sleep and current source wakeup*/
+            uint32_t reserved18                    :    5;
+            uint32_t xtl_force_iso                 :    1;
+            uint32_t pll_force_iso                 :    1;
+            uint32_t analog_force_iso              :    1;
+            uint32_t xtl_force_noiso               :    1;
+            uint32_t pll_force_noiso               :    1;
+            uint32_t analog_force_noiso            :    1;
+            uint32_t dg_wrap_force_rst             :    1;  /*digital wrap force reset in deep sleep*/
+            uint32_t dg_wrap_force_norst           :    1;  /*digital core force no reset in deep sleep*/
+            uint32_t sw_sys_rst                    :    1;  /*SW system reset*/
+        };
+        uint32_t val;
+    } options0;
+    uint32_t slp_timer0;
+    union {
+        struct {
+            uint32_t slp_val_hi                    :    16;  /*RTC sleep timer high 16 bits*/
+            uint32_t main_timer_alarm_en           :    1;  /*timer alarm enable bit*/
+            uint32_t reserved17                    :    15;
+        };
+        uint32_t val;
+    } slp_timer1;
+    union {
+        struct {
+            uint32_t reserved0                     :    27;
+            uint32_t timer_sys_stall               :    1;  /*Enable to record system stall time*/
+            uint32_t timer_xtl_off                 :    1;  /*Enable to record 40M XTAL OFF time*/
+            uint32_t timer_sys_rst                 :    1;  /*enable to record system reset time*/
+            uint32_t reserved30                    :    1;
+            uint32_t update                        :    1;  /*Set 1: to update register with RTC timer*/
+        };
+        uint32_t val;
+    } time_update;
+    uint32_t time_low0;
+    union {
+        struct {
+            uint32_t rtc_timer_value0_high         :    16;  /*RTC timer high 16 bits*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } time_high0;
+    union {
+        struct {
+            uint32_t rtc_sw_cpu_int                :    1;  /*rtc software interrupt to main cpu*/
+            uint32_t rtc_slp_reject_cause_clr      :    1;  /*clear rtc sleep reject cause*/
+            uint32_t reserved2                     :    20;
+            uint32_t apb2rtc_bridge_sel            :    1;  /*1: APB to RTC using bridge*/
+            uint32_t reserved23                    :    5;
+            uint32_t sdio_active_ind               :    1;  /*SDIO active indication*/
+            uint32_t slp_wakeup                    :    1;  /*leep wakeup bit*/
+            uint32_t slp_reject                    :    1;  /*leep reject bit*/
+            uint32_t sleep_en                      :    1;  /*sleep enable bit*/
+        };
+        uint32_t val;
+    } state0;
+    union {
+        struct {
+            uint32_t cpu_stall_en                  :    1;  /*CPU stall enable bit*/
+            uint32_t cpu_stall_wait                :    5;  /*CPU stall wait cycles in fast_clk_rtc*/
+            uint32_t ck8m_wait                     :    8;  /*CK8M wait cycles in slow_clk_rtc*/
+            uint32_t xtl_buf_wait                  :    10;  /*XTAL wait cycles in slow_clk_rtc*/
+            uint32_t pll_buf_wait                  :    8;  /*PLL wait cycles in slow_clk_rtc*/
+        };
+        uint32_t val;
+    } timer1;
+    union {
+        struct {
+            uint32_t reserved0                     :    15;
+            uint32_t ulpcp_touch_start_wait        :    9;  /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/
+            uint32_t min_time_ck8m_off             :    8;  /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
+        };
+        uint32_t val;
+    } timer2;
+    union {
+        struct {
+            uint32_t wifi_wait_timer               :    9;
+            uint32_t wifi_powerup_timer            :    7;
+            uint32_t bt_wait_timer                 :    9;
+            uint32_t bt_powerup_timer              :    7;
+        };
+        uint32_t val;
+    } timer3;
+    union {
+        struct {
+            uint32_t rtc_wait_timer                :    9;
+            uint32_t rtc_powerup_timer             :    7;
+            uint32_t dg_wrap_wait_timer            :    9;
+            uint32_t dg_wrap_powerup_timer         :    7;
+        };
+        uint32_t val;
+    } timer4;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;
+            uint32_t min_slp_val                   :    8;  /*minimal sleep cycles in slow_clk_rtc*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } timer5;
+    union {
+        struct {
+            uint32_t cpu_top_wait_timer            :    9;
+            uint32_t cpu_top_powerup_timer         :    7;
+            uint32_t dg_peri_wait_timer            :    9;
+            uint32_t dg_peri_powerup_timer         :    7;
+        };
+        uint32_t val;
+    } timer6;
+    union {
+        struct {
+            uint32_t reserved0                     :    18;
+            uint32_t i2c_reset_por_force_pd        :    1;
+            uint32_t i2c_reset_por_force_pu        :    1;
+            uint32_t glitch_rst_en                 :    1;
+            uint32_t reserved21                    :    1;  /*PLLA force power down*/
+            uint32_t sar_i2c_pu                    :    1;  /*PLLA force power up*/
+            uint32_t analog_top_iso_sleep          :    1;  /*PLLA force power down*/
+            uint32_t analog_top_iso_monitor        :    1;  /*PLLA force power up*/
+            uint32_t bbpll_cal_slp_start           :    1;  /*start BBPLL calibration during sleep*/
+            uint32_t pvtmon_pu                     :    1;  /*1: PVTMON power up*/
+            uint32_t txrf_i2c_pu                   :    1;  /*1: TXRF_I2C power up*/
+            uint32_t rfrx_pbus_pu                  :    1;  /*1: RFRX_PBUS power up*/
+            uint32_t reserved29                    :    1;
+            uint32_t ckgen_i2c_pu                  :    1;  /*1: CKGEN_I2C power up*/
+            uint32_t pll_i2c_pu                    :    1;
+        };
+        uint32_t val;
+    } ana_conf;
+    union {
+        struct {
+            uint32_t reset_cause_procpu            :    6;  /*reset cause of PRO CPU*/
+            uint32_t reset_cause_appcpu            :    6;  /*reset cause of APP CPU*/
+            uint32_t appcpu_stat_vector_sel        :    1;  /*APP CPU state vector sel*/
+            uint32_t procpu_stat_vector_sel        :    1;  /*PRO CPU state vector sel*/
+            uint32_t reset_flag_procpu             :    1;  /*PRO CPU reset_flag*/
+            uint32_t reset_flag_appcpu             :    1;  /*APP CPU reset flag*/
+            uint32_t reset_flag_procpu_clr         :    1;  /*clear PRO CPU reset_flag*/
+            uint32_t reset_flag_appcpu_clr         :    1;  /*clear APP CPU reset flag*/
+            uint32_t appcpu_ocd_halt_on_reset      :    1;  /*APPCPU OcdHaltOnReset*/
+            uint32_t procpu_ocd_halt_on_reset      :    1;  /*PROCPU OcdHaltOnReset*/
+            uint32_t reset_flag_jtag_procpu        :    1;
+            uint32_t reset_flag_jtag_appcpu        :    1;
+            uint32_t reset_flag_jtag_procpu_clr    :    1;
+            uint32_t reset_flag_jtag_appcpu_clr    :    1;
+            uint32_t rtc_app_dreset_mask           :    1;
+            uint32_t rtc_pro_dreset_mask           :    1;
+            uint32_t reserved26                    :    6;
+        };
+        uint32_t val;
+    } reset_state;
+    union {
+        struct {
+            uint32_t reserved0                     :    15;
+            uint32_t rtc_wakeup_ena                :    17;  /*wakeup enable bitmap*/
+        };
+        uint32_t val;
+    } wakeup_state;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject                    :    1;  /*enable sleep reject interrupt*/
+            uint32_t sdio_idle                     :    1;  /*enable SDIO idle interrupt*/
+            uint32_t rtc_wdt                       :    1;  /*enable RTC WDT interrupt*/
+            uint32_t rtc_touch_scan_done           :    1;  /*enable touch scan done interrupt*/
+            uint32_t rtc_ulp_cp                    :    1;  /*enable ULP-coprocessor interrupt*/
+            uint32_t rtc_touch_done                :    1;  /*enable touch done interrupt*/
+            uint32_t rtc_touch_active              :    1;  /*enable touch active interrupt*/
+            uint32_t rtc_touch_inactive            :    1;  /*enable touch inactive interrupt*/
+            uint32_t rtc_brown_out                 :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer                :    1;  /*enable RTC main timer interrupt*/
+            uint32_t rtc_saradc1                   :    1;  /*enable saradc1 interrupt*/
+            uint32_t rtc_tsens                     :    1;  /*enable tsens interrupt*/
+            uint32_t rtc_cocpu                     :    1;  /*enable riscV cocpu interrupt*/
+            uint32_t rtc_saradc2                   :    1;  /*enable saradc2 interrupt*/
+            uint32_t rtc_swd                       :    1;  /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead              :    1;  /*enable xtal32k_dead  interrupt*/
+            uint32_t rtc_cocpu_trap                :    1;  /*enable cocpu trap interrupt*/
+            uint32_t rtc_touch_timeout             :    1;  /*enable touch timeout interrupt*/
+            uint32_t rtc_glitch_det                :    1;  /*enable gitch det interrupt*/
+            uint32_t rtc_touch_approach_loop_done  :    1;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt raw*/
+            uint32_t slp_reject                    :    1;  /*sleep reject interrupt raw*/
+            uint32_t sdio_idle                     :    1;  /*SDIO idle interrupt raw*/
+            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt raw*/
+            uint32_t rtc_touch_scan_done           :    1;
+            uint32_t rtc_ulp_cp                    :    1;  /*ULP-coprocessor interrupt raw*/
+            uint32_t rtc_touch_done                :    1;  /*touch interrupt raw*/
+            uint32_t rtc_touch_active              :    1;  /*touch active interrupt raw*/
+            uint32_t rtc_touch_inactive            :    1;  /*touch inactive interrupt raw*/
+            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt raw*/
+            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt raw*/
+            uint32_t rtc_saradc1                   :    1;  /*saradc1 interrupt raw*/
+            uint32_t rtc_tsens                     :    1;  /*tsens interrupt raw*/
+            uint32_t rtc_cocpu                     :    1;  /*riscV cocpu interrupt raw*/
+            uint32_t rtc_saradc2                   :    1;  /*saradc2 interrupt raw*/
+            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt raw*/
+            uint32_t rtc_xtal32k_dead              :    1;  /*xtal32k dead detection interrupt raw*/
+            uint32_t rtc_cocpu_trap                :    1;  /*cocpu trap interrupt raw*/
+            uint32_t rtc_touch_timeout             :    1;  /*touch timeout interrupt raw*/
+            uint32_t rtc_glitch_det                :    1;  /*glitch_det_interrupt_raw*/
+            uint32_t rtc_touch_approach_loop_done  :    1;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt state*/
+            uint32_t slp_reject                    :    1;  /*sleep reject interrupt state*/
+            uint32_t sdio_idle                     :    1;  /*SDIO idle interrupt state*/
+            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt state*/
+            uint32_t rtc_touch_scan_done           :    1;
+            uint32_t rtc_ulp_cp                    :    1;  /*ULP-coprocessor interrupt state*/
+            uint32_t rtc_touch_done                :    1;  /*touch done interrupt state*/
+            uint32_t rtc_touch_active              :    1;  /*touch active interrupt state*/
+            uint32_t rtc_touch_inactive            :    1;  /*touch inactive interrupt state*/
+            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt state*/
+            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt state*/
+            uint32_t rtc_saradc1                   :    1;  /*saradc1 interrupt state*/
+            uint32_t rtc_tsens                     :    1;  /*tsens interrupt state*/
+            uint32_t rtc_cocpu                     :    1;  /*riscV cocpu interrupt state*/
+            uint32_t rtc_saradc2                   :    1;  /*saradc2 interrupt state*/
+            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt state*/
+            uint32_t rtc_xtal32k_dead              :    1;  /*xtal32k dead detection interrupt state*/
+            uint32_t rtc_cocpu_trap                :    1;  /*cocpu trap interrupt state*/
+            uint32_t rtc_touch_timeout             :    1;  /*Touch timeout interrupt state*/
+            uint32_t rtc_glitch_det                :    1;  /*glitch_det_interrupt state*/
+            uint32_t rtc_touch_approach_loop_done  :    1;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slp_wakeup                    :    1;  /*Clear sleep wakeup interrupt state*/
+            uint32_t slp_reject                    :    1;  /*Clear sleep reject interrupt state*/
+            uint32_t sdio_idle                     :    1;  /*Clear SDIO idle interrupt state*/
+            uint32_t rtc_wdt                       :    1;  /*Clear RTC WDT interrupt state*/
+            uint32_t rtc_touch_scan_done           :    1;
+            uint32_t rtc_ulp_cp                    :    1;  /*Clear ULP-coprocessor interrupt state*/
+            uint32_t rtc_touch_done                :    1;  /*Clear touch done interrupt state*/
+            uint32_t rtc_touch_active              :    1;  /*Clear touch active interrupt state*/
+            uint32_t rtc_touch_inactive            :    1;  /*Clear touch inactive interrupt state*/
+            uint32_t rtc_brown_out                 :    1;  /*Clear brown out interrupt state*/
+            uint32_t rtc_main_timer                :    1;  /*Clear RTC main timer interrupt state*/
+            uint32_t rtc_saradc1                   :    1;  /*Clear saradc1 interrupt state*/
+            uint32_t rtc_tsens                     :    1;  /*Clear tsens interrupt state*/
+            uint32_t rtc_cocpu                     :    1;  /*Clear riscV cocpu interrupt state*/
+            uint32_t rtc_saradc2                   :    1;  /*Clear saradc2 interrupt state*/
+            uint32_t rtc_swd                       :    1;  /*Clear super watch dog interrupt state*/
+            uint32_t rtc_xtal32k_dead              :    1;  /*Clear RTC WDT interrupt state*/
+            uint32_t rtc_cocpu_trap                :    1;  /*Clear cocpu trap interrupt state*/
+            uint32_t rtc_touch_timeout             :    1;  /*Clear touch timeout interrupt state*/
+            uint32_t rtc_glitch_det                :    1;  /*Clear glitch det interrupt state*/
+            uint32_t rtc_touch_approach_loop_done  :    1;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t store[4];
+    union {
+        struct {
+            uint32_t xtal32k_wdt_en                :    1;  /*xtal 32k watch dog enable*/
+            uint32_t xtal32k_wdt_clk_fo            :    1;  /*xtal 32k watch dog clock force on*/
+            uint32_t xtal32k_wdt_reset             :    1;  /*xtal 32k watch dog sw reset*/
+            uint32_t xtal32k_ext_clk_fo            :    1;  /*xtal 32k external xtal clock force on*/
+            uint32_t xtal32k_auto_backup           :    1;  /*xtal 32k switch to back up clock when xtal is dead*/
+            uint32_t xtal32k_auto_restart          :    1;  /*xtal 32k restart xtal when xtal is dead*/
+            uint32_t xtal32k_auto_return           :    1;  /*xtal 32k switch back xtal when xtal is restarted*/
+            uint32_t xtal32k_xpd_force             :    1;  /*Xtal 32k xpd control by sw or fsm*/
+            uint32_t enckinit_xtal_32k             :    1;  /*apply an internal clock to help xtal 32k to start*/
+            uint32_t dbuf_xtal_32k                 :    1;  /*0: single-end buffer 1: differential buffer*/
+            uint32_t dgm_xtal_32k                  :    3;  /*xtal_32k gm control*/
+            uint32_t dres_xtal_32k                 :    3;  /*DRES_XTAL_32K*/
+            uint32_t xpd_xtal_32k                  :    1;  /*XPD_XTAL_32K*/
+            uint32_t dac_xtal_32k                  :    3;  /*DAC_XTAL_32K*/
+            uint32_t rtc_wdt_state                 :    3;  /*state of 32k_wdt*/
+            uint32_t rtc_xtal32k_gpio_sel          :    1;  /*XTAL_32K sel. 0: external XTAL_32K*/
+            uint32_t reserved24                    :    6;
+            uint32_t ctr_lv                        :    1;  /*0: power down XTAL at high level*/
+            uint32_t ctr_en                        :    1;
+        };
+        uint32_t val;
+    } ext_xtl_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    29;
+            uint32_t gpio_wakeup_filter            :    1;  /*enable filter for gpio wakeup event*/
+            uint32_t ext_wakeup0_lv                :    1;  /*0: external wakeup at low level*/
+            uint32_t ext_wakeup1_lv                :    1;
+        };
+        uint32_t val;
+    } ext_wakeup_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    12;
+            uint32_t rtc_sleep_reject_ena          :    18;  /*sleep reject enable*/
+            uint32_t light_slp_reject_en           :    1;  /*enable reject for light sleep*/
+            uint32_t deep_slp_reject_en            :    1;  /*enable reject for deep sleep*/
+        };
+        uint32_t val;
+    } slp_reject_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    29;
+            uint32_t cpusel_conf                   :    1;  /*CPU sel option*/
+            uint32_t cpuperiod_sel                 :    2;
+        };
+        uint32_t val;
+    } cpu_period_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    22;
+            uint32_t sdio_act_dnum                 :    10;
+        };
+        uint32_t val;
+    } sdio_act_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    1;
+            uint32_t efuse_clk_force_gating        :    1;
+            uint32_t efuse_clk_force_nogating      :    1;
+            uint32_t ck8m_div_sel_vld              :    1;  /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
+            uint32_t ck8m_div                      :    2;  /*CK8M_D256_OUT divider. 00: div128*/
+            uint32_t enb_ck8m                      :    1;  /*disable CK8M and CK8M_D256_OUT*/
+            uint32_t enb_ck8m_div                  :    1;  /*1: CK8M_D256_OUT is actually CK8M*/
+            uint32_t dig_xtal32k_en                :    1;  /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_d256_en             :    1;  /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_en                  :    1;  /*enable CK8M for digital core (no relationship with RTC core)*/
+            uint32_t reserved11                    :    1;
+            uint32_t ck8m_div_sel                  :    3;  /*divider = reg_ck8m_div_sel + 1*/
+            uint32_t xtal_force_nogating           :    1;  /*XTAL force no gating during sleep*/
+            uint32_t ck8m_force_nogating           :    1;  /*CK8M force no gating during sleep*/
+            uint32_t ck8m_dfreq                    :    8;  /*CK8M_DFREQ*/
+            uint32_t ck8m_force_pd                 :    1;  /*CK8M force power down*/
+            uint32_t ck8m_force_pu                 :    1;  /*CK8M force power up*/
+            uint32_t xtal_global_force_gating      :    1;
+            uint32_t xtal_global_force_nogating    :    1;
+            uint32_t fast_clk_rtc_sel              :    1;  /*fast_clk_rtc sel. 0: XTAL div 2*/
+            uint32_t ana_clk_rtc_sel               :    2;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    22;
+            uint32_t rtc_ana_clk_div_vld           :    1;  /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
+            uint32_t rtc_ana_clk_div               :    8;
+            uint32_t slow_clk_next_edge            :    1;
+        };
+        uint32_t val;
+    } slow_clk_conf;
+    union {
+        struct {
+            uint32_t sdio_timer_target             :    8;  /*timer count to apply reg_sdio_dcap after sdio power on*/
+            uint32_t reserved8                     :    1;
+            uint32_t sdio_dthdrv                   :    2;  /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
+            uint32_t sdio_dcap                     :    2;  /*ability to prevent LDO from overshoot*/
+            uint32_t sdio_initi                    :    2;  /*add resistor from ldo output to ground. 0: no res*/
+            uint32_t sdio_en_initi                 :    1;  /*0 to set init[1:0]=0*/
+            uint32_t sdio_dcurlim                  :    3;  /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
+            uint32_t sdio_modecurlim               :    1;  /*select current limit mode*/
+            uint32_t sdio_encurlim                 :    1;  /*enable current limit*/
+            uint32_t sdio_pd_en                    :    1;  /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
+            uint32_t sdio_force                    :    1;  /*1: use SW option to control SDIO_REG*/
+            uint32_t sdio_tieh                     :    1;  /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
+            uint32_t reg1p8_ready                  :    1;  /*read only register for REG1P8_READY*/
+            uint32_t drefl_sdio                    :    2;  /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t drefm_sdio                    :    2;  /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t drefh_sdio                    :    2;  /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t xpd_sdio                      :    1;
+        };
+        uint32_t val;
+    } sdio_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    10;
+            uint32_t bias_buf_idle                 :    1;
+            uint32_t bias_buf_wake                 :    1;
+            uint32_t bias_buf_deep_slp             :    1;
+            uint32_t bias_buf_monitor              :    1;
+            uint32_t pd_cur_deep_slp               :    1;  /*xpd cur when rtc in sleep_state*/
+            uint32_t pd_cur_monitor                :    1;  /*xpd cur when rtc in monitor state*/
+            uint32_t bias_sleep_deep_slp           :    1;  /*bias_sleep when rtc in sleep_state*/
+            uint32_t bias_sleep_monitor            :    1;  /*bias_sleep when rtc in monitor state*/
+            uint32_t dbg_atten_deep_slp            :    4;  /*DBG_ATTEN when rtc in sleep state*/
+            uint32_t dbg_atten_monitor             :    4;  /*DBG_ATTEN when rtc in monitor state*/
+            uint32_t dbg_atten_wakeup              :    4;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } bias_conf;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;
+            uint32_t dig_cal_en                    :    1;
+            uint32_t reserved8                     :    6;
+            uint32_t sck_dcap                      :    8;  /*SCK_DCAP*/
+            uint32_t reserved22                    :    6;
+            uint32_t rtc_dboost_force_pd           :    1;  /*RTC_DBOOST force power down*/
+            uint32_t rtc_dboost_force_pu           :    1;  /*RTC_DBOOST force power up*/
+            uint32_t rtculator_force_pd            :    1;  /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
+            uint32_t rtculator_force_pu            :    1;
+        };
+        uint32_t val;
+    } rtc;
+    union {
+        struct {
+            uint32_t rtc_fastmem_force_noiso       :    1;  /*Fast RTC memory force no ISO*/
+            uint32_t rtc_fastmem_force_iso         :    1;  /*Fast RTC memory force ISO*/
+            uint32_t rtc_slowmem_force_noiso       :    1;  /*RTC memory force no ISO*/
+            uint32_t rtc_slowmem_force_iso         :    1;  /*RTC memory force ISO*/
+            uint32_t rtc_force_iso                 :    1;  /*rtc_peri force ISO*/
+            uint32_t rtc_force_noiso               :    1;  /*rtc_peri force no ISO*/
+            uint32_t rtc_fastmem_folw_cpu          :    1;  /*1: Fast RTC memory PD following CPU*/
+            uint32_t fastmem_force_lpd             :    1;  /*Fast RTC memory force PD*/
+            uint32_t fastmem_force_lpu             :    1;  /*Fast RTC memory force no PD*/
+            uint32_t rtc_slowmem_folw_cpu          :    1;  /*1: RTC memory  PD following CPU*/
+            uint32_t rtc_slowmem_force_lpd         :    1;  /*RTC memory force PD*/
+            uint32_t rtc_slowmem_force_lpu         :    1;  /*RTC memory force no PD*/
+            uint32_t reserved12                    :    6;  /*enable power down RTC memory in sleep*/
+            uint32_t rtc_force_pd                  :    1;  /*rtc_peri force power down*/
+            uint32_t rtc_force_pu                  :    1;  /*rtc_peri force power up*/
+            uint32_t rtc_pd_en                     :    1;  /*enable power down rtc_peri in sleep */
+            uint32_t rtc_pad_force_hold            :    1;  /*rtc pad force hold*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } pwc;
+    union {
+        struct {
+            uint32_t rtculator_drv_b_monitor       :    6;
+            uint32_t rtculator_drv_b_slp           :    6;
+            uint32_t dg_vdd_drv_b_slp              :    8;
+            uint32_t dg_vdd_drv_b_monitor          :    8;
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } regulator_drv_ctrl;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;
+            uint32_t lslp_mem_force_pd             :    1;  /*memories in digital core force PD in sleep*/
+            uint32_t lslp_mem_force_pu             :    1;  /*memories in digital core force no PD in sleep*/
+            uint32_t reserved5                     :    6;  /*internal SRAM 1 force power up*/
+            uint32_t bt_force_pd                   :    1;  /*internal SRAM 2 force power down*/
+            uint32_t bt_force_pu                   :    1;  /*internal SRAM 2 force power up*/
+            uint32_t dg_peri_force_pd              :    1;  /*internal SRAM 3 force power down*/
+            uint32_t dg_peri_force_pu              :    1;  /*internal SRAM 3 force power up*/
+            uint32_t reserved15                    :    2;  /*internal SRAM 4 force power up*/
+            uint32_t wifi_force_pd                 :    1;  /*wifi force power down*/
+            uint32_t wifi_force_pu                 :    1;  /*wifi force power up*/
+            uint32_t dg_wrap_force_pd              :    1;  /*digital core force power down*/
+            uint32_t dg_wrap_force_pu              :    1;  /*digital core force power up*/
+            uint32_t cpu_top_force_pd              :    1;  /*digital dcdc force power down*/
+            uint32_t cpu_top_force_pu              :    1;  /*digital dcdc force power up*/
+            uint32_t reserved23                    :    4;  /*enable power down internal SRAM 1 in sleep*/
+            uint32_t bt_pd_en                      :    1;  /*enable power down internal SRAM 2 in sleep*/
+            uint32_t dg_peri_pd_en                 :    1;  /*enable power down internal SRAM 3 in sleep*/
+            uint32_t cpu_top_pd_en                 :    1;  /*enable power down internal SRAM 4 in sleep*/
+            uint32_t wifi_pd_en                    :    1;  /*enable power down wifi in sleep*/
+            uint32_t dg_wrap_pd_en                 :    1;
+        };
+        uint32_t val;
+    } dig_pwc;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;
+            uint32_t dig_iso_force_off             :    1;
+            uint32_t dig_iso_force_on              :    1;
+            uint32_t dg_pad_autohold               :    1;  /*read only register to indicate digital pad auto-hold status*/
+            uint32_t clr_dg_pad_autohold           :    1;  /*wtite only register to clear digital pad auto-hold*/
+            uint32_t dg_pad_autohold_en            :    1;  /*digital pad enable auto-hold*/
+            uint32_t dg_pad_force_noiso            :    1;  /*digital pad force no ISO*/
+            uint32_t dg_pad_force_iso              :    1;  /*digital pad force ISO*/
+            uint32_t dg_pad_force_unhold           :    1;  /*digital pad force un-hold*/
+            uint32_t dg_pad_force_hold             :    1;  /*digital pad force hold*/
+            uint32_t reserved16                    :    6;  /*internal SRAM 1 force no ISO*/
+            uint32_t bt_force_iso                  :    1;  /*internal SRAM 2 force ISO*/
+            uint32_t bt_force_noiso                :    1;  /*internal SRAM 2 force no ISO*/
+            uint32_t dg_peri_force_iso             :    1;  /*internal SRAM 3 force ISO*/
+            uint32_t dg_peri_force_noiso           :    1;  /*internal SRAM 3 force no ISO*/
+            uint32_t cpu_top_force_iso             :    1;  /*internal SRAM 4 force ISO*/
+            uint32_t cpu_top_force_noiso           :    1;  /*internal SRAM 4 force no ISO*/
+            uint32_t wifi_force_iso                :    1;  /*wifi force ISO*/
+            uint32_t wifi_force_noiso              :    1;  /*wifi force no ISO*/
+            uint32_t dg_wrap_force_iso             :    1;  /*digital core force ISO*/
+            uint32_t dg_wrap_force_noiso           :    1;
+        };
+        uint32_t val;
+    } dig_iso;
+    union {
+        struct {
+            uint32_t chip_reset_width              :    8;  /*chip reset siginal pulse width*/
+            uint32_t chip_reset_en                 :    1;  /*wdt reset whole chip enable*/
+            uint32_t pause_in_slp                  :    1;  /*pause WDT in sleep*/
+            uint32_t appcpu_reset_en               :    1;  /*enable WDT reset APP CPU*/
+            uint32_t procpu_reset_en               :    1;  /*enable WDT reset PRO CPU*/
+            uint32_t flashboot_mod_en              :    1;  /*enable WDT in flash boot*/
+            uint32_t sys_reset_length              :    3;  /*system reset counter length*/
+            uint32_t cpu_reset_length              :    3;  /*CPU reset counter length*/
+            uint32_t stg3                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg2                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg1                          :    3;  /*1: interrupt stage en*/
+            uint32_t stg0                          :    3;  /*1: interrupt stage en*/
+            uint32_t en                            :    1;
+        };
+        uint32_t val;
+    } wdt_config0;
+    uint32_t wdt_config1;
+    uint32_t wdt_config2;
+    uint32_t wdt_config3;
+    uint32_t wdt_config4;
+    union {
+        struct {
+            uint32_t reserved0                     :    31;
+            uint32_t feed                          :    1;
+        };
+        uint32_t val;
+    } wdt_feed;
+    uint32_t wdt_wprotect;
+    union {
+        struct {
+            uint32_t swd_reset_flag                :    1;  /*swd reset flag*/
+            uint32_t swd_feed_int                  :    1;  /*swd interrupt for feeding*/
+            uint32_t reserved2                     :    15;
+            uint32_t swd_bypass_rst                :    1;
+            uint32_t swd_signal_width              :    10;  /*adjust signal width send to swd*/
+            uint32_t swd_rst_flag_clr              :    1;  /*reset swd reset flag*/
+            uint32_t swd_feed                      :    1;  /*Sw feed swd*/
+            uint32_t swd_disable                   :    1;  /*disable SWD*/
+            uint32_t swd_auto_feed_en              :    1;  /*automatically feed swd when int comes*/
+        };
+        uint32_t val;
+    } swd_conf;
+    uint32_t swd_wprotect;
+    union {
+        struct {
+            uint32_t reserved0                     :    20;
+            uint32_t appcpu_c1                     :    6;  /*{reg_sw_stall_appcpu_c1[5:0]*/
+            uint32_t procpu_c1                     :    6;
+        };
+        uint32_t val;
+    } sw_cpu_stall;
+    uint32_t store4;
+    uint32_t store5;
+    uint32_t store6;
+    uint32_t store7;
+    union {
+        struct {
+            uint32_t xpd_rom0                      :    1;  /*rom0 power down*/
+            uint32_t reserved1                     :    1;
+            uint32_t xpd_dig_dcdc                  :    1;  /*External DCDC power down*/
+            uint32_t rtc_peri_iso                  :    1;  /*rtc peripheral iso*/
+            uint32_t xpd_rtc_peri                  :    1;  /*rtc peripheral power down */
+            uint32_t wifi_iso                      :    1;  /*wifi iso*/
+            uint32_t xpd_wifi                      :    1;  /*wifi wrap power down*/
+            uint32_t dig_iso                       :    1;  /*digital wrap iso*/
+            uint32_t xpd_dig                       :    1;  /*digital wrap power down*/
+            uint32_t rtc_touch_state_start         :    1;  /*touch should start to work*/
+            uint32_t rtc_touch_state_switch        :    1;  /*touch is about to working. Switch rtc main state*/
+            uint32_t rtc_touch_state_slp           :    1;  /*touch is in sleep state*/
+            uint32_t rtc_touch_state_done          :    1;  /*touch is done*/
+            uint32_t rtc_cocpu_state_start         :    1;  /*ulp/cocpu should start to work*/
+            uint32_t rtc_cocpu_state_switch        :    1;  /*ulp/cocpu is about to working. Switch rtc main state*/
+            uint32_t rtc_cocpu_state_slp           :    1;  /*ulp/cocpu is in sleep state*/
+            uint32_t rtc_cocpu_state_done          :    1;  /*ulp/cocpu is done*/
+            uint32_t rtc_main_state_xtal_iso       :    1;  /*no use any more*/
+            uint32_t rtc_main_state_pll_on         :    1;  /*rtc main state machine is in states that pll should be running*/
+            uint32_t rtc_rdy_for_wakeup            :    1;  /*rtc is ready to receive wake up trigger from wake up source*/
+            uint32_t rtc_main_state_wait_end       :    1;  /*rtc main state machine has been waited for some cycles*/
+            uint32_t rtc_in_wakeup_state           :    1;  /*rtc main state machine is in the states of wakeup process*/
+            uint32_t rtc_in_low_power_state        :    1;  /*rtc main state machine is in the states of low power*/
+            uint32_t rtc_main_state_in_wait_8m     :    1;  /*rtc main state machine is in wait 8m state*/
+            uint32_t rtc_main_state_in_wait_pll    :    1;  /*rtc main state machine is in wait pll state*/
+            uint32_t rtc_main_state_in_wait_xtl    :    1;  /*rtc main state machine is in wait xtal state*/
+            uint32_t rtc_main_state_in_slp         :    1;  /*rtc main state machine is in sleep state*/
+            uint32_t rtc_main_state_in_idle        :    1;  /*rtc main state machine is in idle state*/
+            uint32_t rtc_main_state                :    4;  /*rtc main state machine status*/
+        };
+        uint32_t val;
+    } low_power_st;
+    uint32_t diag0;
+    union {
+        struct {
+            uint32_t touch_pad0_hold               :    1;
+            uint32_t touch_pad1_hold               :    1;
+            uint32_t touch_pad2_hold               :    1;
+            uint32_t touch_pad3_hold               :    1;
+            uint32_t touch_pad4_hold               :    1;
+            uint32_t touch_pad5_hold               :    1;
+            uint32_t touch_pad6_hold               :    1;
+            uint32_t touch_pad7_hold               :    1;
+            uint32_t touch_pad8_hold               :    1;
+            uint32_t touch_pad9_hold               :    1;
+            uint32_t touch_pad10_hold              :    1;
+            uint32_t touch_pad11_hold              :    1;
+            uint32_t touch_pad12_hold              :    1;
+            uint32_t touch_pad13_hold              :    1;
+            uint32_t touch_pad14_hold              :    1;
+            uint32_t x32p_hold                     :    1;
+            uint32_t x32n_hold                     :    1;
+            uint32_t pdac1_hold                    :    1;
+            uint32_t pdac2_hold                    :    1;
+            uint32_t rtc_pad19_hold                :    1;
+            uint32_t rtc_pad20_hold                :    1;
+            uint32_t rtc_pad21_hold                :    1;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } pad_hold;
+    uint32_t dig_pad_hold;
+    union {
+        struct {
+            uint32_t ext_wakeup1_sel               :    22;  /*Bitmap to select RTC pads for ext wakeup1*/
+            uint32_t ext_wakeup1_status_clr        :    1;  /*clear ext wakeup1 status*/
+            uint32_t reserved23                    :    9;
+        };
+        uint32_t val;
+    } ext_wakeup1;
+    union {
+        struct {
+            uint32_t ext_wakeup1_status            :    22;  /*ext wakeup1 status*/
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } ext_wakeup1_status;
+    union {
+        struct {
+            uint32_t reserved0                     :    4;
+            uint32_t int_wait                      :    10;  /*brown out interrupt wait cycles*/
+            uint32_t close_flash_ena               :    1;  /*enable close flash when brown out happens*/
+            uint32_t pd_rf_ena                     :    1;  /*enable power down RF when brown out happens*/
+            uint32_t rst_wait                      :    10;  /*brown out reset wait cycles*/
+            uint32_t rst_ena                       :    1;  /*enable brown out reset*/
+            uint32_t rst_sel                       :    1;  /*1:  4-pos reset*/
+            uint32_t ana_rst_en                    :    1;
+            uint32_t cnt_clr                       :    1;  /*clear brown out counter*/
+            uint32_t ena                           :    1;  /*enable brown out*/
+            uint32_t det                           :    1;
+        };
+        uint32_t val;
+    } brown_out;
+    uint32_t time_low1;
+    union {
+        struct {
+            uint32_t rtc_timer_value1_high         :    16;  /*RTC timer high 16 bits*/
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } time_high1;
+    uint32_t xtal32k_clk_factor;
+    union {
+        struct {
+            uint32_t xtal32k_return_wait           :    4;  /*cycles to wait to return normal xtal 32k*/
+            uint32_t xtal32k_restart_wait          :    16;  /*cycles to wait to repower on xtal 32k*/
+            uint32_t xtal32k_wdt_timeout           :    8;  /*If no clock detected for this amount of time*/
+            uint32_t xtal32k_stable_thres          :    4;  /*if restarted xtal32k period is smaller than this*/
+        };
+        uint32_t val;
+    } xtal32k_conf;
+    union {
+        struct {
+            uint32_t ulp_cp_pc_init                :    11;  /*ULP-coprocessor PC initial address*/
+            uint32_t reserved11                    :    18;
+            uint32_t ulp_cp_gpio_wakeup_ena        :    1;  /*ULP-coprocessor wakeup by GPIO enable*/
+            uint32_t ulp_cp_gpio_wakeup_clr        :    1;  /*ULP-coprocessor wakeup by GPIO state clear*/
+            uint32_t ulp_cp_slp_timer_en           :    1;  /*ULP-coprocessor timer enable bit*/
+        };
+        uint32_t val;
+    } ulp_cp_timer;
+    union {
+        struct {
+            uint32_t ulp_cp_mem_addr_init          :    11;
+            uint32_t ulp_cp_mem_addr_size          :    11;
+            uint32_t ulp_cp_mem_offst_clr          :    1;
+            uint32_t reserved23                    :    5;
+            uint32_t ulp_cp_clk_fo                 :    1;  /*ulp coprocessor clk force on*/
+            uint32_t ulp_cp_reset                  :    1;  /*ulp coprocessor clk software reset*/
+            uint32_t ulp_cp_force_start_top        :    1;  /*1: ULP-coprocessor is started by SW*/
+            uint32_t ulp_cp_start_top              :    1;  /*Write 1 to start ULP-coprocessor*/
+        };
+        uint32_t val;
+    } ulp_cp_ctrl;
+    union {
+        struct {
+            uint32_t cocpu_clk_fo                  :    1;  /*cocpu clk force on*/
+            uint32_t cocpu_start_2_reset_dis       :    6;  /*time from start cocpu to pull down reset*/
+            uint32_t cocpu_start_2_intr_en         :    6;  /*time from start cocpu to give start interrupt*/
+            uint32_t cocpu_shut                    :    1;  /*to shut cocpu*/
+            uint32_t cocpu_shut_2_clk_dis          :    8;  /*time from shut cocpu to disable clk*/
+            uint32_t cocpu_shut_reset_en           :    1;  /*to reset cocpu*/
+            uint32_t cocpu_sel                     :    1;  /*1: old ULP 0: new riscV*/
+            uint32_t cocpu_done_force              :    1;  /*1: select riscv done 0: select ulp done*/
+            uint32_t cocpu_done                    :    1;  /*done signal used by riscv to control timer. */
+            uint32_t cocpu_sw_int_trigger          :    1;  /*trigger cocpu register interrupt*/
+            uint32_t cocpu_clkgate_en              :    1;
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } cocpu_ctrl;
+    union {
+        struct {
+            uint32_t touch_sleep_cycles            :    16;  /*sleep cycles for timer*/
+            uint32_t touch_meas_num                :    16;  /*the meas length (in 8MHz)*/
+        };
+        uint32_t val;
+    } touch_ctrl1;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t touch_drange                  :    2;  /*TOUCH_DRANGE*/
+            uint32_t touch_drefl                   :    2;  /*TOUCH_DREFL*/
+            uint32_t touch_drefh                   :    2;  /*TOUCH_DREFH*/
+            uint32_t touch_xpd_bias                :    1;  /*TOUCH_XPD_BIAS*/
+            uint32_t touch_refc                    :    3;  /*TOUCH pad0 reference cap*/
+            uint32_t touch_dbias                   :    1;  /*1:use self bias 0:use bandgap bias*/
+            uint32_t touch_slp_timer_en            :    1;  /*touch timer enable bit*/
+            uint32_t touch_start_fsm_en            :    1;  /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/
+            uint32_t touch_start_en                :    1;  /*1: start touch fsm*/
+            uint32_t touch_start_force             :    1;  /*1: to start touch fsm by SW*/
+            uint32_t touch_xpd_wait                :    8;  /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
+            uint32_t touch_slp_cyc_div             :    2;  /*when a touch pad is active*/
+            uint32_t touch_timer_force_done        :    2;  /*force touch timer done*/
+            uint32_t touch_reset                   :    1;  /*reset upgrade touch*/
+            uint32_t touch_clk_fo                  :    1;  /*touch clock force on*/
+            uint32_t touch_clkgate_en              :    1;  /*touch clock enable*/
+        };
+        uint32_t val;
+    } touch_ctrl2;
+    union {
+        struct {
+            uint32_t touch_denoise_res             :    2;  /*De-noise resolution: 12/10/8/4 bit*/
+            uint32_t touch_denoise_en              :    1;  /*touch pad0 will be used to de-noise*/
+            uint32_t reserved3                     :    5;
+            uint32_t touch_inactive_connection     :    1;  /*inactive touch pads connect to 1: gnd 0: HighZ*/
+            uint32_t touch_shield_pad_en           :    1;  /*touch pad14 will be used as shield*/
+            uint32_t touch_scan_pad_map            :    15;  /*touch scan mode pad enable map*/
+            uint32_t touch_bufdrv                  :    3;  /*touch7 buffer driver strength*/
+            uint32_t touch_out_ring                :    4;  /*select out ring pad*/
+        };
+        uint32_t val;
+    } touch_scan_ctrl;
+    union {
+        struct {
+            uint32_t touch_slp_th                  :    22;  /*the threshold for sleep touch pad*/
+            uint32_t reserved22                    :    4;
+            uint32_t touch_slp_approach_en         :    1;  /*sleep pad approach function enable*/
+            uint32_t touch_slp_pad                 :    5;  /* */
+        };
+        uint32_t val;
+    } touch_slp_thres;
+    union {
+        struct {
+            uint32_t reserved0                     :    23;
+            uint32_t touch_slp_channel_clr         :    1;  /*clear touch slp channel*/
+            uint32_t touch_approach_meas_time      :    8;  /*approach pads total meas times*/
+        };
+        uint32_t val;
+    } touch_approach;
+    union {
+        struct {
+            uint32_t reserved0                     :    7;
+            uint32_t touch_bypass_nn_thres         :    1;
+            uint32_t touch_bypass_noise_thres      :    1;
+            uint32_t touch_smooth_lvl              :    2;
+            uint32_t touch_jitter_step             :    4;  /*touch jitter step*/
+            uint32_t config1                       :    4;
+            uint32_t config2                       :    2;
+            uint32_t touch_noise_thres             :    2;
+            uint32_t config3                       :    2;
+            uint32_t touch_debounce                :    3;  /*debounce counter*/
+            uint32_t touch_filter_mode             :    3;  /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/
+            uint32_t touch_filter_en               :    1;  /*touch filter enable*/
+        };
+        uint32_t val;
+    } touch_filter_ctrl;
+    union {
+        struct {
+            uint32_t usb_vrefh                     :    2;
+            uint32_t usb_vrefl                     :    2;
+            uint32_t usb_vref_override             :    1;
+            uint32_t usb_pad_pull_override         :    1;
+            uint32_t usb_dp_pullup                 :    1;
+            uint32_t usb_dp_pulldown               :    1;
+            uint32_t usb_dm_pullup                 :    1;
+            uint32_t usb_dm_pulldown               :    1;
+            uint32_t usb_pullup_value              :    1;
+            uint32_t usb_pad_enable_override       :    1;
+            uint32_t usb_pad_enable                :    1;
+            uint32_t usb_txm                       :    1;
+            uint32_t usb_txp                       :    1;
+            uint32_t usb_tx_en                     :    1;
+            uint32_t usb_tx_en_override            :    1;
+            uint32_t usb_reset_disable             :    1;
+            uint32_t io_mux_reset_disable          :    1;
+            uint32_t sw_usb_phy_sel                :    1;
+            uint32_t sw_hw_usb_phy_sel             :    1;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } usb_conf;
+    union {
+        struct {
+            uint32_t touch_timeout_num             :    22;
+            uint32_t touch_timeout_en              :    1;
+            uint32_t reserved23                    :    9;
+        };
+        uint32_t val;
+    } touch_timeout_ctrl;
+    union {
+        struct {
+            uint32_t reject_cause                  :    18;  /*sleep reject cause*/
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } slp_reject_cause;
+    union {
+        struct {
+            uint32_t force_download_boot           :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } option1;
+    union {
+        struct {
+            uint32_t wakeup_cause                  :    17;  /*sleep wakeup cause*/
+            uint32_t reserved17                    :    15;
+        };
+        uint32_t val;
+    } slp_wakeup_cause;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;
+            uint32_t ulp_cp_timer_slp_cycle        :    24;  /*sleep cycles for ULP-coprocessor timer*/
+        };
+        uint32_t val;
+    } ulp_cp_timer_1;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1ts               :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1ts               :    1;  /*enable sleep reject interrupt*/
+            uint32_t sdio_idle_w1ts                :    1;  /*enable SDIO idle interrupt*/
+            uint32_t rtc_wdt_w1ts                  :    1;  /*enable RTC WDT interrupt*/
+            uint32_t rtc_touch_scan_done_w1ts      :    1;  /*enable touch scan done interrupt*/
+            uint32_t rtc_ulp_cp_w1ts               :    1;  /*enable ULP-coprocessor interrupt*/
+            uint32_t rtc_touch_done_w1ts           :    1;  /*enable touch done interrupt*/
+            uint32_t rtc_touch_active_w1ts         :    1;  /*enable touch active interrupt*/
+            uint32_t rtc_touch_inactive_w1ts       :    1;  /*enable touch inactive interrupt*/
+            uint32_t w1ts                          :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1ts           :    1;  /*enable RTC main timer interrupt*/
+            uint32_t rtc_saradc1_w1ts              :    1;  /*enable saradc1 interrupt*/
+            uint32_t rtc_tsens_w1ts                :    1;  /*enable tsens interrupt*/
+            uint32_t rtc_cocpu_w1ts                :    1;  /*enable riscV cocpu interrupt*/
+            uint32_t rtc_saradc2_w1ts              :    1;  /*enable saradc2 interrupt*/
+            uint32_t rtc_swd_w1ts                  :    1;  /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead_w1ts         :    1;  /*enable xtal32k_dead  interrupt*/
+            uint32_t rtc_cocpu_trap_w1ts           :    1;  /*enable cocpu trap interrupt*/
+            uint32_t rtc_touch_timeout_w1ts        :    1;  /*enable touch timeout interrupt*/
+            uint32_t rtc_glitch_det_w1ts           :    1;  /*enable gitch det interrupt*/
+            uint32_t rtc_touch_approach_loop_done_w1ts:    1;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } int_ena_w1ts;
+    union {
+        struct {
+            uint32_t slp_wakeup_w1tc               :    1;  /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject_w1tc               :    1;  /*enable sleep reject interrupt*/
+            uint32_t sdio_idle_w1tc                :    1;  /*enable SDIO idle interrupt*/
+            uint32_t rtc_wdt_w1tc                  :    1;  /*enable RTC WDT interrupt*/
+            uint32_t rtc_touch_scan_done_w1tc      :    1;  /*enable touch scan done interrupt*/
+            uint32_t rtc_ulp_cp_w1tc               :    1;  /*enable ULP-coprocessor interrupt*/
+            uint32_t rtc_touch_done_w1tc           :    1;  /*enable touch done interrupt*/
+            uint32_t rtc_touch_active_w1tc         :    1;  /*enable touch active interrupt*/
+            uint32_t rtc_touch_inactive_w1tc       :    1;  /*enable touch inactive interrupt*/
+            uint32_t w1tc                          :    1;  /*enable brown out interrupt*/
+            uint32_t rtc_main_timer_w1tc           :    1;  /*enable RTC main timer interrupt*/
+            uint32_t rtc_saradc1_w1tc              :    1;  /*enable saradc1 interrupt*/
+            uint32_t rtc_tsens_w1tc                :    1;  /*enable tsens interrupt*/
+            uint32_t rtc_cocpu_w1tc                :    1;  /*enable riscV cocpu interrupt*/
+            uint32_t rtc_saradc2_w1tc              :    1;  /*enable saradc2 interrupt*/
+            uint32_t rtc_swd_w1tc                  :    1;  /*enable super watch dog interrupt*/
+            uint32_t rtc_xtal32k_dead_w1tc         :    1;  /*enable xtal32k_dead  interrupt*/
+            uint32_t rtc_cocpu_trap_w1tc           :    1;  /*enable cocpu trap interrupt*/
+            uint32_t rtc_touch_timeout_w1tc        :    1;  /*enable touch timeout interrupt*/
+            uint32_t rtc_glitch_det_w1tc           :    1;  /*enable gitch det interrupt*/
+            uint32_t rtc_touch_approach_loop_done_w1tc:    1;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } int_ena_w1tc;
+    union {
+        struct {
+            uint32_t reserved0                     :    10;
+            uint32_t retention_tag_mode            :    4;
+            uint32_t retention_target              :    2;
+            uint32_t retention_clk_sel             :    1;
+            uint32_t retention_done_wait           :    3;
+            uint32_t retention_clkoff_wait         :    4;
+            uint32_t retention_en                  :    1;
+            uint32_t retention_wait                :    7;  /*wait cycles for rention operation*/
+        };
+        uint32_t val;
+    } retention_ctrl;
+    union {
+        struct {
+            uint32_t reserved0                     :    26;
+            uint32_t power_glitch_dsense           :    2;
+            uint32_t power_glitch_force_pd         :    1;
+            uint32_t power_glitch_force_pu         :    1;
+            uint32_t power_glitch_efuse_sel        :    1;  /*select use analog fib signal*/
+            uint32_t power_glitch_en               :    1;
+        };
+        uint32_t val;
+    } pg_ctrl;
+    union {
+        struct {
+            uint32_t rtc_fib_sel                   :    3;
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } fib_sel;
+    union {
+        struct {
+            uint32_t reserved0                     :    2;
+            uint32_t touch_pad9_dac                :    3;
+            uint32_t touch_pad8_dac                :    3;
+            uint32_t touch_pad7_dac                :    3;
+            uint32_t touch_pad6_dac                :    3;
+            uint32_t touch_pad5_dac                :    3;
+            uint32_t touch_pad4_dac                :    3;
+            uint32_t touch_pad3_dac                :    3;
+            uint32_t touch_pad2_dac                :    3;
+            uint32_t touch_pad1_dac                :    3;
+            uint32_t touch_pad0_dac                :    3;
+        };
+        uint32_t val;
+    } touch_dac;
+    union {
+        struct {
+            uint32_t reserved0                     :    17;
+            uint32_t touch_pad14_dac               :    3;
+            uint32_t touch_pad13_dac               :    3;
+            uint32_t touch_pad12_dac               :    3;
+            uint32_t touch_pad11_dac               :    3;
+            uint32_t touch_pad10_dac               :    3;
+        };
+        uint32_t val;
+    } touch_dac1;
+    union {
+        struct {
+            uint32_t reserved0                     :    31;
+            uint32_t disable_rtc_cpu               :    1;
+        };
+        uint32_t val;
+    } cocpu_disable;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t date                          :    28;
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } date;
+} rtc_cntl_dev_t;
+extern rtc_cntl_dev_t RTCCNTL;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_CNTL_STRUCT_H_ */
diff --git a/components/soc/esp32s3/register/soc/rtc_i2c_reg.h b/components/soc/esp32s3/register/soc/rtc_i2c_reg.h
new file mode 100644
index 00000000000..ba10ed02330
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/rtc_i2c_reg.h
@@ -0,0 +1,864 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** RTC_I2C_SCL_LOW_REG register
+ *  configure low scl period
+ */
+#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_I2C_BASE + 0x0)
+/** RTC_I2C_SCL_LOW_PERIOD_REG : R/W; bitpos: [19:0]; default: 256;
+ *  time period that scl =0
+ */
+#define RTC_I2C_SCL_LOW_PERIOD_REG    0x000FFFFFU
+#define RTC_I2C_SCL_LOW_PERIOD_REG_M  (RTC_I2C_SCL_LOW_PERIOD_REG_V << RTC_I2C_SCL_LOW_PERIOD_REG_S)
+#define RTC_I2C_SCL_LOW_PERIOD_REG_V  0x000FFFFFU
+#define RTC_I2C_SCL_LOW_PERIOD_REG_S  0
+
+/** RTC_I2C_CTRL_REG register
+ *  configure i2c ctrl
+ */
+#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x4)
+/** RTC_I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
+ *  1=push pull,0=open drain
+ */
+#define RTC_I2C_SDA_FORCE_OUT    (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_M  (RTC_I2C_SDA_FORCE_OUT_V << RTC_I2C_SDA_FORCE_OUT_S)
+#define RTC_I2C_SDA_FORCE_OUT_V  0x00000001U
+#define RTC_I2C_SDA_FORCE_OUT_S  0
+/** RTC_I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
+ *  1=push pull,0=open drain
+ */
+#define RTC_I2C_SCL_FORCE_OUT    (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_M  (RTC_I2C_SCL_FORCE_OUT_V << RTC_I2C_SCL_FORCE_OUT_S)
+#define RTC_I2C_SCL_FORCE_OUT_V  0x00000001U
+#define RTC_I2C_SCL_FORCE_OUT_S  1
+/** RTC_I2C_MS_MODE : R/W; bitpos: [2]; default: 0;
+ *  1=master,0=slave
+ */
+#define RTC_I2C_MS_MODE    (BIT(2))
+#define RTC_I2C_MS_MODE_M  (RTC_I2C_MS_MODE_V << RTC_I2C_MS_MODE_S)
+#define RTC_I2C_MS_MODE_V  0x00000001U
+#define RTC_I2C_MS_MODE_S  2
+/** RTC_I2C_TRANS_START : R/W; bitpos: [3]; default: 0;
+ *  force start
+ */
+#define RTC_I2C_TRANS_START    (BIT(3))
+#define RTC_I2C_TRANS_START_M  (RTC_I2C_TRANS_START_V << RTC_I2C_TRANS_START_S)
+#define RTC_I2C_TRANS_START_V  0x00000001U
+#define RTC_I2C_TRANS_START_S  3
+/** RTC_I2C_TX_LSB_FIRST : R/W; bitpos: [4]; default: 0;
+ *  transit lsb first
+ */
+#define RTC_I2C_TX_LSB_FIRST    (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_M  (RTC_I2C_TX_LSB_FIRST_V << RTC_I2C_TX_LSB_FIRST_S)
+#define RTC_I2C_TX_LSB_FIRST_V  0x00000001U
+#define RTC_I2C_TX_LSB_FIRST_S  4
+/** RTC_I2C_RX_LSB_FIRST : R/W; bitpos: [5]; default: 0;
+ *  receive lsb first
+ */
+#define RTC_I2C_RX_LSB_FIRST    (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_M  (RTC_I2C_RX_LSB_FIRST_V << RTC_I2C_RX_LSB_FIRST_S)
+#define RTC_I2C_RX_LSB_FIRST_V  0x00000001U
+#define RTC_I2C_RX_LSB_FIRST_S  5
+/** RTC_I2C_I2C_CTRL_CLK_GATE_EN : R/W; bitpos: [29]; default: 0;
+ *  configure i2c ctrl clk enable
+ */
+#define RTC_I2C_I2C_CTRL_CLK_GATE_EN    (BIT(29))
+#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_M  (RTC_I2C_I2C_CTRL_CLK_GATE_EN_V << RTC_I2C_I2C_CTRL_CLK_GATE_EN_S)
+#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_V  0x00000001U
+#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_S  29
+/** RTC_I2C_I2C_RESET : R/W; bitpos: [30]; default: 0;
+ *  rtc i2c sw reset
+ */
+#define RTC_I2C_I2C_RESET    (BIT(30))
+#define RTC_I2C_I2C_RESET_M  (RTC_I2C_I2C_RESET_V << RTC_I2C_I2C_RESET_S)
+#define RTC_I2C_I2C_RESET_V  0x00000001U
+#define RTC_I2C_I2C_RESET_S  30
+/** RTC_I2C_I2CCLK_EN : R/W; bitpos: [31]; default: 0;
+ *  rtc i2c reg clk gating
+ */
+#define RTC_I2C_I2CCLK_EN    (BIT(31))
+#define RTC_I2C_I2CCLK_EN_M  (RTC_I2C_I2CCLK_EN_V << RTC_I2C_I2CCLK_EN_S)
+#define RTC_I2C_I2CCLK_EN_V  0x00000001U
+#define RTC_I2C_I2CCLK_EN_S  31
+
+/** RTC_I2C_STATUS_REG register
+ *  get i2c status
+ */
+#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x8)
+/** RTC_I2C_ACK_REC : RO; bitpos: [0]; default: 0;
+ *  ack response
+ */
+#define RTC_I2C_ACK_REC    (BIT(0))
+#define RTC_I2C_ACK_REC_M  (RTC_I2C_ACK_REC_V << RTC_I2C_ACK_REC_S)
+#define RTC_I2C_ACK_REC_V  0x00000001U
+#define RTC_I2C_ACK_REC_S  0
+/** RTC_I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
+ *  slave read or write
+ */
+#define RTC_I2C_SLAVE_RW    (BIT(1))
+#define RTC_I2C_SLAVE_RW_M  (RTC_I2C_SLAVE_RW_V << RTC_I2C_SLAVE_RW_S)
+#define RTC_I2C_SLAVE_RW_V  0x00000001U
+#define RTC_I2C_SLAVE_RW_S  1
+/** RTC_I2C_ARB_LOST : RO; bitpos: [2]; default: 0;
+ *  arbitration is lost
+ */
+#define RTC_I2C_ARB_LOST    (BIT(2))
+#define RTC_I2C_ARB_LOST_M  (RTC_I2C_ARB_LOST_V << RTC_I2C_ARB_LOST_S)
+#define RTC_I2C_ARB_LOST_V  0x00000001U
+#define RTC_I2C_ARB_LOST_S  2
+/** RTC_I2C_BUS_BUSY : RO; bitpos: [3]; default: 0;
+ *  bus is busy
+ */
+#define RTC_I2C_BUS_BUSY    (BIT(3))
+#define RTC_I2C_BUS_BUSY_M  (RTC_I2C_BUS_BUSY_V << RTC_I2C_BUS_BUSY_S)
+#define RTC_I2C_BUS_BUSY_V  0x00000001U
+#define RTC_I2C_BUS_BUSY_S  3
+/** RTC_I2C_SLAVE_ADDRESSED : RO; bitpos: [4]; default: 0;
+ *  slave reg sub address
+ */
+#define RTC_I2C_SLAVE_ADDRESSED    (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_M  (RTC_I2C_SLAVE_ADDRESSED_V << RTC_I2C_SLAVE_ADDRESSED_S)
+#define RTC_I2C_SLAVE_ADDRESSED_V  0x00000001U
+#define RTC_I2C_SLAVE_ADDRESSED_S  4
+/** RTC_I2C_BYTE_TRANS : RO; bitpos: [5]; default: 0;
+ *  One byte transit done
+ */
+#define RTC_I2C_BYTE_TRANS    (BIT(5))
+#define RTC_I2C_BYTE_TRANS_M  (RTC_I2C_BYTE_TRANS_V << RTC_I2C_BYTE_TRANS_S)
+#define RTC_I2C_BYTE_TRANS_V  0x00000001U
+#define RTC_I2C_BYTE_TRANS_S  5
+/** RTC_I2C_OP_CNT : RO; bitpos: [7:6]; default: 0;
+ *  which operation is working
+ */
+#define RTC_I2C_OP_CNT    0x00000003U
+#define RTC_I2C_OP_CNT_M  (RTC_I2C_OP_CNT_V << RTC_I2C_OP_CNT_S)
+#define RTC_I2C_OP_CNT_V  0x00000003U
+#define RTC_I2C_OP_CNT_S  6
+/** RTC_I2C_SHIFT_REG : RO; bitpos: [23:16]; default: 0;
+ *  shifter content
+ */
+#define RTC_I2C_SHIFT_REG    0x000000FFU
+#define RTC_I2C_SHIFT_REG_M  (RTC_I2C_SHIFT_REG_V << RTC_I2C_SHIFT_REG_S)
+#define RTC_I2C_SHIFT_REG_V  0x000000FFU
+#define RTC_I2C_SHIFT_REG_S  16
+/** RTC_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
+ *  i2c last main status
+ */
+#define RTC_I2C_SCL_MAIN_STATE_LAST    0x00000007U
+#define RTC_I2C_SCL_MAIN_STATE_LAST_M  (RTC_I2C_SCL_MAIN_STATE_LAST_V << RTC_I2C_SCL_MAIN_STATE_LAST_S)
+#define RTC_I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
+#define RTC_I2C_SCL_MAIN_STATE_LAST_S  24
+/** RTC_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
+ *  scl last status
+ */
+#define RTC_I2C_SCL_STATE_LAST    0x00000007U
+#define RTC_I2C_SCL_STATE_LAST_M  (RTC_I2C_SCL_STATE_LAST_V << RTC_I2C_SCL_STATE_LAST_S)
+#define RTC_I2C_SCL_STATE_LAST_V  0x00000007U
+#define RTC_I2C_SCL_STATE_LAST_S  28
+
+/** RTC_I2C_TO_REG register
+ *  configure time out
+ */
+#define RTC_I2C_TO_REG (DR_REG_RTC_I2C_BASE + 0xc)
+/** RTC_I2C_TIME_OUT_REG : R/W; bitpos: [19:0]; default: 65536;
+ *  time out threshold
+ */
+#define RTC_I2C_TIME_OUT_REG    0x000FFFFFU
+#define RTC_I2C_TIME_OUT_REG_M  (RTC_I2C_TIME_OUT_REG_V << RTC_I2C_TIME_OUT_REG_S)
+#define RTC_I2C_TIME_OUT_REG_V  0x000FFFFFU
+#define RTC_I2C_TIME_OUT_REG_S  0
+
+/** RTC_I2C_SLAVE_ADDR_REG register
+ *  configure slave id
+ */
+#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x10)
+/** RTC_I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
+ *  slave address
+ */
+#define RTC_I2C_SLAVE_ADDR    0x00007FFFU
+#define RTC_I2C_SLAVE_ADDR_M  (RTC_I2C_SLAVE_ADDR_V << RTC_I2C_SLAVE_ADDR_S)
+#define RTC_I2C_SLAVE_ADDR_V  0x00007FFFU
+#define RTC_I2C_SLAVE_ADDR_S  0
+/** RTC_I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
+ *  i2c 10bit mode enable
+ */
+#define RTC_I2C_ADDR_10BIT_EN    (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_M  (RTC_I2C_ADDR_10BIT_EN_V << RTC_I2C_ADDR_10BIT_EN_S)
+#define RTC_I2C_ADDR_10BIT_EN_V  0x00000001U
+#define RTC_I2C_ADDR_10BIT_EN_S  31
+
+/** RTC_I2C_SCL_HIGH_REG register
+ *  configure high scl period
+ */
+#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x14)
+/** RTC_I2C_SCL_HIGH_PERIOD_REG : R/W; bitpos: [19:0]; default: 256;
+ *  time period that scl = 1
+ */
+#define RTC_I2C_SCL_HIGH_PERIOD_REG    0x000FFFFFU
+#define RTC_I2C_SCL_HIGH_PERIOD_REG_M  (RTC_I2C_SCL_HIGH_PERIOD_REG_V << RTC_I2C_SCL_HIGH_PERIOD_REG_S)
+#define RTC_I2C_SCL_HIGH_PERIOD_REG_V  0x000FFFFFU
+#define RTC_I2C_SCL_HIGH_PERIOD_REG_S  0
+
+/** RTC_I2C_SDA_DUTY_REG register
+ *  configure sda duty
+ */
+#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x18)
+/** RTC_I2C_SDA_DUTY_NUM : R/W; bitpos: [19:0]; default: 16;
+ *  time period for SDA to toggle after SCL goes low
+ */
+#define RTC_I2C_SDA_DUTY_NUM    0x000FFFFFU
+#define RTC_I2C_SDA_DUTY_NUM_M  (RTC_I2C_SDA_DUTY_NUM_V << RTC_I2C_SDA_DUTY_NUM_S)
+#define RTC_I2C_SDA_DUTY_NUM_V  0x000FFFFFU
+#define RTC_I2C_SDA_DUTY_NUM_S  0
+
+/** RTC_I2C_SCL_START_PERIOD_REG register
+ *  configure scl start period
+ */
+#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x1c)
+/** RTC_I2C_SCL_START_PERIOD : R/W; bitpos: [19:0]; default: 8;
+ *  time period for SCL to toggle after I2C start is triggered
+ */
+#define RTC_I2C_SCL_START_PERIOD    0x000FFFFFU
+#define RTC_I2C_SCL_START_PERIOD_M  (RTC_I2C_SCL_START_PERIOD_V << RTC_I2C_SCL_START_PERIOD_S)
+#define RTC_I2C_SCL_START_PERIOD_V  0x000FFFFFU
+#define RTC_I2C_SCL_START_PERIOD_S  0
+
+/** RTC_I2C_SCL_STOP_PERIOD_REG register
+ *  configure scl stop period
+ */
+#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x20)
+/** RTC_I2C_SCL_STOP_PERIOD : R/W; bitpos: [19:0]; default: 8;
+ *  time period for SCL to stop after I2C end is triggered
+ */
+#define RTC_I2C_SCL_STOP_PERIOD    0x000FFFFFU
+#define RTC_I2C_SCL_STOP_PERIOD_M  (RTC_I2C_SCL_STOP_PERIOD_V << RTC_I2C_SCL_STOP_PERIOD_S)
+#define RTC_I2C_SCL_STOP_PERIOD_V  0x000FFFFFU
+#define RTC_I2C_SCL_STOP_PERIOD_S  0
+
+/** RTC_I2C_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x24)
+/** RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  clear slave transit complete interrupt
+ */
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR    (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M  (RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V << RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S)
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x00000001U
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S  0
+/** RTC_I2C_ARBITRATION_LOST_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  clear arbitration lost interrupt
+ */
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR    (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M  (RTC_I2C_ARBITRATION_LOST_INT_CLR_V << RTC_I2C_ARBITRATION_LOST_INT_CLR_S)
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S  1
+/** RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO; bitpos: [2]; default: 0;
+ *  clear master transit complete interrupt
+ */
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR    (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M  (RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V << RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S)
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V  0x00000001U
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S  2
+/** RTC_I2C_TRANS_COMPLETE_INT_CLR : WO; bitpos: [3]; default: 0;
+ *  clear transit complete interrupt
+ */
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR    (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M  (RTC_I2C_TRANS_COMPLETE_INT_CLR_V << RTC_I2C_TRANS_COMPLETE_INT_CLR_S)
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S  3
+/** RTC_I2C_TIME_OUT_INT_CLR : WO; bitpos: [4]; default: 0;
+ *  clear time out interrupt
+ */
+#define RTC_I2C_TIME_OUT_INT_CLR    (BIT(4))
+#define RTC_I2C_TIME_OUT_INT_CLR_M  (RTC_I2C_TIME_OUT_INT_CLR_V << RTC_I2C_TIME_OUT_INT_CLR_S)
+#define RTC_I2C_TIME_OUT_INT_CLR_V  0x00000001U
+#define RTC_I2C_TIME_OUT_INT_CLR_S  4
+/** RTC_I2C_ACK_ERR_INT_CLR : WO; bitpos: [5]; default: 0;
+ *  clear ack error interrupt
+ */
+#define RTC_I2C_ACK_ERR_INT_CLR    (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_M  (RTC_I2C_ACK_ERR_INT_CLR_V << RTC_I2C_ACK_ERR_INT_CLR_S)
+#define RTC_I2C_ACK_ERR_INT_CLR_V  0x00000001U
+#define RTC_I2C_ACK_ERR_INT_CLR_S  5
+/** RTC_I2C_RX_DATA_INT_CLR : WO; bitpos: [6]; default: 0;
+ *  clear receive data interrupt
+ */
+#define RTC_I2C_RX_DATA_INT_CLR    (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_M  (RTC_I2C_RX_DATA_INT_CLR_V << RTC_I2C_RX_DATA_INT_CLR_S)
+#define RTC_I2C_RX_DATA_INT_CLR_V  0x00000001U
+#define RTC_I2C_RX_DATA_INT_CLR_S  6
+/** RTC_I2C_TX_DATA_INT_CLR : WO; bitpos: [7]; default: 0;
+ *  clear transit load data complete interrupt
+ */
+#define RTC_I2C_TX_DATA_INT_CLR    (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_M  (RTC_I2C_TX_DATA_INT_CLR_V << RTC_I2C_TX_DATA_INT_CLR_S)
+#define RTC_I2C_TX_DATA_INT_CLR_V  0x00000001U
+#define RTC_I2C_TX_DATA_INT_CLR_S  7
+/** RTC_I2C_DETECT_START_INT_CLR : WO; bitpos: [8]; default: 0;
+ *  clear detect start interrupt
+ */
+#define RTC_I2C_DETECT_START_INT_CLR    (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_M  (RTC_I2C_DETECT_START_INT_CLR_V << RTC_I2C_DETECT_START_INT_CLR_S)
+#define RTC_I2C_DETECT_START_INT_CLR_V  0x00000001U
+#define RTC_I2C_DETECT_START_INT_CLR_S  8
+
+/** RTC_I2C_INT_RAW_REG register
+ *  interrupt raw register
+ */
+#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x28)
+/** RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO; bitpos: [0]; default: 0;
+ *  slave transit complete interrupt raw
+ */
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW    (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M  (RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V << RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S)
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x00000001U
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S  0
+/** RTC_I2C_ARBITRATION_LOST_INT_RAW : RO; bitpos: [1]; default: 0;
+ *  arbitration lost interrupt raw
+ */
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW    (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M  (RTC_I2C_ARBITRATION_LOST_INT_RAW_V << RTC_I2C_ARBITRATION_LOST_INT_RAW_S)
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S  1
+/** RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO; bitpos: [2]; default: 0;
+ *  master transit complete interrupt raw
+ */
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW    (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M  (RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V << RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S)
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V  0x00000001U
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S  2
+/** RTC_I2C_TRANS_COMPLETE_INT_RAW : RO; bitpos: [3]; default: 0;
+ *  transit complete interrupt raw
+ */
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW    (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M  (RTC_I2C_TRANS_COMPLETE_INT_RAW_V << RTC_I2C_TRANS_COMPLETE_INT_RAW_S)
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S  3
+/** RTC_I2C_TIME_OUT_INT_RAW : RO; bitpos: [4]; default: 0;
+ *  time out interrupt raw
+ */
+#define RTC_I2C_TIME_OUT_INT_RAW    (BIT(4))
+#define RTC_I2C_TIME_OUT_INT_RAW_M  (RTC_I2C_TIME_OUT_INT_RAW_V << RTC_I2C_TIME_OUT_INT_RAW_S)
+#define RTC_I2C_TIME_OUT_INT_RAW_V  0x00000001U
+#define RTC_I2C_TIME_OUT_INT_RAW_S  4
+/** RTC_I2C_ACK_ERR_INT_RAW : RO; bitpos: [5]; default: 0;
+ *  ack error interrupt raw
+ */
+#define RTC_I2C_ACK_ERR_INT_RAW    (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_M  (RTC_I2C_ACK_ERR_INT_RAW_V << RTC_I2C_ACK_ERR_INT_RAW_S)
+#define RTC_I2C_ACK_ERR_INT_RAW_V  0x00000001U
+#define RTC_I2C_ACK_ERR_INT_RAW_S  5
+/** RTC_I2C_RX_DATA_INT_RAW : RO; bitpos: [6]; default: 0;
+ *  receive data interrupt raw
+ */
+#define RTC_I2C_RX_DATA_INT_RAW    (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_M  (RTC_I2C_RX_DATA_INT_RAW_V << RTC_I2C_RX_DATA_INT_RAW_S)
+#define RTC_I2C_RX_DATA_INT_RAW_V  0x00000001U
+#define RTC_I2C_RX_DATA_INT_RAW_S  6
+/** RTC_I2C_TX_DATA_INT_RAW : RO; bitpos: [7]; default: 0;
+ *  transit data interrupt raw
+ */
+#define RTC_I2C_TX_DATA_INT_RAW    (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_M  (RTC_I2C_TX_DATA_INT_RAW_V << RTC_I2C_TX_DATA_INT_RAW_S)
+#define RTC_I2C_TX_DATA_INT_RAW_V  0x00000001U
+#define RTC_I2C_TX_DATA_INT_RAW_S  7
+/** RTC_I2C_DETECT_START_INT_RAW : RO; bitpos: [8]; default: 0;
+ *  detect start interrupt raw
+ */
+#define RTC_I2C_DETECT_START_INT_RAW    (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_M  (RTC_I2C_DETECT_START_INT_RAW_V << RTC_I2C_DETECT_START_INT_RAW_S)
+#define RTC_I2C_DETECT_START_INT_RAW_V  0x00000001U
+#define RTC_I2C_DETECT_START_INT_RAW_S  8
+
+/** RTC_I2C_INT_ST_REG register
+ *  interrupt state register
+ */
+#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x2c)
+/** RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO; bitpos: [0]; default: 0;
+ *  slave transit complete interrupt state
+ */
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST    (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M  (RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V << RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S)
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V  0x00000001U
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S  0
+/** RTC_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [1]; default: 0;
+ *  arbitration lost interrupt state
+ */
+#define RTC_I2C_ARBITRATION_LOST_INT_ST    (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_M  (RTC_I2C_ARBITRATION_LOST_INT_ST_V << RTC_I2C_ARBITRATION_LOST_INT_ST_S)
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_S  1
+/** RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO; bitpos: [2]; default: 0;
+ *  master transit complete interrupt state
+ */
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST    (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M  (RTC_I2C_MASTER_TRAN_COMP_INT_ST_V << RTC_I2C_MASTER_TRAN_COMP_INT_ST_S)
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V  0x00000001U
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S  2
+/** RTC_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  transit complete interrupt state
+ */
+#define RTC_I2C_TRANS_COMPLETE_INT_ST    (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_M  (RTC_I2C_TRANS_COMPLETE_INT_ST_V << RTC_I2C_TRANS_COMPLETE_INT_ST_S)
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_S  3
+/** RTC_I2C_TIME_OUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  time out interrupt state
+ */
+#define RTC_I2C_TIME_OUT_INT_ST    (BIT(4))
+#define RTC_I2C_TIME_OUT_INT_ST_M  (RTC_I2C_TIME_OUT_INT_ST_V << RTC_I2C_TIME_OUT_INT_ST_S)
+#define RTC_I2C_TIME_OUT_INT_ST_V  0x00000001U
+#define RTC_I2C_TIME_OUT_INT_ST_S  4
+/** RTC_I2C_ACK_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  ack error interrupt state
+ */
+#define RTC_I2C_ACK_ERR_INT_ST    (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_M  (RTC_I2C_ACK_ERR_INT_ST_V << RTC_I2C_ACK_ERR_INT_ST_S)
+#define RTC_I2C_ACK_ERR_INT_ST_V  0x00000001U
+#define RTC_I2C_ACK_ERR_INT_ST_S  5
+/** RTC_I2C_RX_DATA_INT_ST : RO; bitpos: [6]; default: 0;
+ *  receive data interrupt state
+ */
+#define RTC_I2C_RX_DATA_INT_ST    (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_M  (RTC_I2C_RX_DATA_INT_ST_V << RTC_I2C_RX_DATA_INT_ST_S)
+#define RTC_I2C_RX_DATA_INT_ST_V  0x00000001U
+#define RTC_I2C_RX_DATA_INT_ST_S  6
+/** RTC_I2C_TX_DATA_INT_ST : RO; bitpos: [7]; default: 0;
+ *  transit data interrupt state
+ */
+#define RTC_I2C_TX_DATA_INT_ST    (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_M  (RTC_I2C_TX_DATA_INT_ST_V << RTC_I2C_TX_DATA_INT_ST_S)
+#define RTC_I2C_TX_DATA_INT_ST_V  0x00000001U
+#define RTC_I2C_TX_DATA_INT_ST_S  7
+/** RTC_I2C_DETECT_START_INT_ST : RO; bitpos: [8]; default: 0;
+ *  detect start interrupt state
+ */
+#define RTC_I2C_DETECT_START_INT_ST    (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_M  (RTC_I2C_DETECT_START_INT_ST_V << RTC_I2C_DETECT_START_INT_ST_S)
+#define RTC_I2C_DETECT_START_INT_ST_V  0x00000001U
+#define RTC_I2C_DETECT_START_INT_ST_S  8
+
+/** RTC_I2C_INT_ENA_REG register
+ *  interrupt enable register
+ */
+#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x30)
+/** RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  enable slave transit complete interrupt
+ */
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA    (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M  (RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V << RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S)
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x00000001U
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S  0
+/** RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  enable arbitration lost interrupt
+ */
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA    (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M  (RTC_I2C_ARBITRATION_LOST_INT_ENA_V << RTC_I2C_ARBITRATION_LOST_INT_ENA_S)
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S  1
+/** RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  enable master transit complete interrupt
+ */
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA    (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M  (RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V << RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S)
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V  0x00000001U
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S  2
+/** RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  enable transit complete interrupt
+ */
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA    (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M  (RTC_I2C_TRANS_COMPLETE_INT_ENA_V << RTC_I2C_TRANS_COMPLETE_INT_ENA_S)
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S  3
+/** RTC_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  enable time out interrupt
+ */
+#define RTC_I2C_TIME_OUT_INT_ENA    (BIT(4))
+#define RTC_I2C_TIME_OUT_INT_ENA_M  (RTC_I2C_TIME_OUT_INT_ENA_V << RTC_I2C_TIME_OUT_INT_ENA_S)
+#define RTC_I2C_TIME_OUT_INT_ENA_V  0x00000001U
+#define RTC_I2C_TIME_OUT_INT_ENA_S  4
+/** RTC_I2C_ACK_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  enable eack error interrupt
+ */
+#define RTC_I2C_ACK_ERR_INT_ENA    (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_M  (RTC_I2C_ACK_ERR_INT_ENA_V << RTC_I2C_ACK_ERR_INT_ENA_S)
+#define RTC_I2C_ACK_ERR_INT_ENA_V  0x00000001U
+#define RTC_I2C_ACK_ERR_INT_ENA_S  5
+/** RTC_I2C_RX_DATA_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  enable receive data interrupt
+ */
+#define RTC_I2C_RX_DATA_INT_ENA    (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_M  (RTC_I2C_RX_DATA_INT_ENA_V << RTC_I2C_RX_DATA_INT_ENA_S)
+#define RTC_I2C_RX_DATA_INT_ENA_V  0x00000001U
+#define RTC_I2C_RX_DATA_INT_ENA_S  6
+/** RTC_I2C_TX_DATA_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  enable transit data interrupt
+ */
+#define RTC_I2C_TX_DATA_INT_ENA    (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_M  (RTC_I2C_TX_DATA_INT_ENA_V << RTC_I2C_TX_DATA_INT_ENA_S)
+#define RTC_I2C_TX_DATA_INT_ENA_V  0x00000001U
+#define RTC_I2C_TX_DATA_INT_ENA_S  7
+/** RTC_I2C_DETECT_START_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  enable detect start interrupt
+ */
+#define RTC_I2C_DETECT_START_INT_ENA    (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_M  (RTC_I2C_DETECT_START_INT_ENA_V << RTC_I2C_DETECT_START_INT_ENA_S)
+#define RTC_I2C_DETECT_START_INT_ENA_V  0x00000001U
+#define RTC_I2C_DETECT_START_INT_ENA_S  8
+
+/** RTC_I2C_DATA_REG register
+ *  get i2c data status
+ */
+#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x34)
+/** RTC_I2C_I2C_RDATA : RO; bitpos: [7:0]; default: 0;
+ *  data received
+ */
+#define RTC_I2C_I2C_RDATA    0x000000FFU
+#define RTC_I2C_I2C_RDATA_M  (RTC_I2C_I2C_RDATA_V << RTC_I2C_I2C_RDATA_S)
+#define RTC_I2C_I2C_RDATA_V  0x000000FFU
+#define RTC_I2C_I2C_RDATA_S  0
+/** RTC_I2C_SLAVE_TX_DATA : R/W; bitpos: [15:8]; default: 0;
+ *  data sent by slave
+ */
+#define RTC_I2C_SLAVE_TX_DATA    0x000000FFU
+#define RTC_I2C_SLAVE_TX_DATA_M  (RTC_I2C_SLAVE_TX_DATA_V << RTC_I2C_SLAVE_TX_DATA_S)
+#define RTC_I2C_SLAVE_TX_DATA_V  0x000000FFU
+#define RTC_I2C_SLAVE_TX_DATA_S  8
+/** RTC_I2C_I2C_DONE : RO; bitpos: [31]; default: 0;
+ *  i2c done
+ */
+#define RTC_I2C_I2C_DONE    (BIT(31))
+#define RTC_I2C_I2C_DONE_M  (RTC_I2C_I2C_DONE_V << RTC_I2C_I2C_DONE_S)
+#define RTC_I2C_I2C_DONE_V  0x00000001U
+#define RTC_I2C_I2C_DONE_S  31
+
+/** RTC_I2C_CMD0_REG register
+ *  i2c commond0 register
+ */
+#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x38)
+/** RTC_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 2307;
+ *  command0
+ */
+#define RTC_I2C_COMMAND0    0x00003FFFU
+#define RTC_I2C_COMMAND0_M  (RTC_I2C_COMMAND0_V << RTC_I2C_COMMAND0_S)
+#define RTC_I2C_COMMAND0_V  0x00003FFFU
+#define RTC_I2C_COMMAND0_S  0
+/** RTC_I2C_COMMAND0_DONE : RO; bitpos: [31]; default: 0;
+ *  command0_done
+ */
+#define RTC_I2C_COMMAND0_DONE    (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_M  (RTC_I2C_COMMAND0_DONE_V << RTC_I2C_COMMAND0_DONE_S)
+#define RTC_I2C_COMMAND0_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND0_DONE_S  31
+
+/** RTC_I2C_CMD1_REG register
+ *  i2c commond1 register
+ */
+#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x3c)
+/** RTC_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 6401;
+ *  command1
+ */
+#define RTC_I2C_COMMAND1    0x00003FFFU
+#define RTC_I2C_COMMAND1_M  (RTC_I2C_COMMAND1_V << RTC_I2C_COMMAND1_S)
+#define RTC_I2C_COMMAND1_V  0x00003FFFU
+#define RTC_I2C_COMMAND1_S  0
+/** RTC_I2C_COMMAND1_DONE : RO; bitpos: [31]; default: 0;
+ *  command1_done
+ */
+#define RTC_I2C_COMMAND1_DONE    (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_M  (RTC_I2C_COMMAND1_DONE_V << RTC_I2C_COMMAND1_DONE_S)
+#define RTC_I2C_COMMAND1_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND1_DONE_S  31
+
+/** RTC_I2C_CMD2_REG register
+ *  i2c commond2 register
+ */
+#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x40)
+/** RTC_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 2306;
+ *  command2
+ */
+#define RTC_I2C_COMMAND2    0x00003FFFU
+#define RTC_I2C_COMMAND2_M  (RTC_I2C_COMMAND2_V << RTC_I2C_COMMAND2_S)
+#define RTC_I2C_COMMAND2_V  0x00003FFFU
+#define RTC_I2C_COMMAND2_S  0
+/** RTC_I2C_COMMAND2_DONE : RO; bitpos: [31]; default: 0;
+ *  command2_done
+ */
+#define RTC_I2C_COMMAND2_DONE    (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_M  (RTC_I2C_COMMAND2_DONE_V << RTC_I2C_COMMAND2_DONE_S)
+#define RTC_I2C_COMMAND2_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND2_DONE_S  31
+
+/** RTC_I2C_CMD3_REG register
+ *  i2c commond3 register
+ */
+#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x44)
+/** RTC_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 257;
+ *  command3
+ */
+#define RTC_I2C_COMMAND3    0x00003FFFU
+#define RTC_I2C_COMMAND3_M  (RTC_I2C_COMMAND3_V << RTC_I2C_COMMAND3_S)
+#define RTC_I2C_COMMAND3_V  0x00003FFFU
+#define RTC_I2C_COMMAND3_S  0
+/** RTC_I2C_COMMAND3_DONE : RO; bitpos: [31]; default: 0;
+ *  command3_done
+ */
+#define RTC_I2C_COMMAND3_DONE    (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_M  (RTC_I2C_COMMAND3_DONE_V << RTC_I2C_COMMAND3_DONE_S)
+#define RTC_I2C_COMMAND3_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND3_DONE_S  31
+
+/** RTC_I2C_CMD4_REG register
+ *  i2c commond4 register
+ */
+#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x48)
+/** RTC_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 2305;
+ *  command4
+ */
+#define RTC_I2C_COMMAND4    0x00003FFFU
+#define RTC_I2C_COMMAND4_M  (RTC_I2C_COMMAND4_V << RTC_I2C_COMMAND4_S)
+#define RTC_I2C_COMMAND4_V  0x00003FFFU
+#define RTC_I2C_COMMAND4_S  0
+/** RTC_I2C_COMMAND4_DONE : RO; bitpos: [31]; default: 0;
+ *  command4_done
+ */
+#define RTC_I2C_COMMAND4_DONE    (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_M  (RTC_I2C_COMMAND4_DONE_V << RTC_I2C_COMMAND4_DONE_S)
+#define RTC_I2C_COMMAND4_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND4_DONE_S  31
+
+/** RTC_I2C_CMD5_REG register
+ *  i2c commond5_register
+ */
+#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x4c)
+/** RTC_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 5889;
+ *  command5
+ */
+#define RTC_I2C_COMMAND5    0x00003FFFU
+#define RTC_I2C_COMMAND5_M  (RTC_I2C_COMMAND5_V << RTC_I2C_COMMAND5_S)
+#define RTC_I2C_COMMAND5_V  0x00003FFFU
+#define RTC_I2C_COMMAND5_S  0
+/** RTC_I2C_COMMAND5_DONE : RO; bitpos: [31]; default: 0;
+ *  command5_done
+ */
+#define RTC_I2C_COMMAND5_DONE    (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_M  (RTC_I2C_COMMAND5_DONE_V << RTC_I2C_COMMAND5_DONE_S)
+#define RTC_I2C_COMMAND5_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND5_DONE_S  31
+
+/** RTC_I2C_CMD6_REG register
+ *  i2c commond6 register
+ */
+#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x50)
+/** RTC_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 6401;
+ *  command6
+ */
+#define RTC_I2C_COMMAND6    0x00003FFFU
+#define RTC_I2C_COMMAND6_M  (RTC_I2C_COMMAND6_V << RTC_I2C_COMMAND6_S)
+#define RTC_I2C_COMMAND6_V  0x00003FFFU
+#define RTC_I2C_COMMAND6_S  0
+/** RTC_I2C_COMMAND6_DONE : RO; bitpos: [31]; default: 0;
+ *  command6_done
+ */
+#define RTC_I2C_COMMAND6_DONE    (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_M  (RTC_I2C_COMMAND6_DONE_V << RTC_I2C_COMMAND6_DONE_S)
+#define RTC_I2C_COMMAND6_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND6_DONE_S  31
+
+/** RTC_I2C_CMD7_REG register
+ *  i2c commond7 register
+ */
+#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x54)
+/** RTC_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 2308;
+ *  command7
+ */
+#define RTC_I2C_COMMAND7    0x00003FFFU
+#define RTC_I2C_COMMAND7_M  (RTC_I2C_COMMAND7_V << RTC_I2C_COMMAND7_S)
+#define RTC_I2C_COMMAND7_V  0x00003FFFU
+#define RTC_I2C_COMMAND7_S  0
+/** RTC_I2C_COMMAND7_DONE : RO; bitpos: [31]; default: 0;
+ *  command7_done
+ */
+#define RTC_I2C_COMMAND7_DONE    (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_M  (RTC_I2C_COMMAND7_DONE_V << RTC_I2C_COMMAND7_DONE_S)
+#define RTC_I2C_COMMAND7_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND7_DONE_S  31
+
+/** RTC_I2C_CMD8_REG register
+ *  i2c commond8 register
+ */
+#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x58)
+/** RTC_I2C_COMMAND8 : R/W; bitpos: [13:0]; default: 6401;
+ *  command8
+ */
+#define RTC_I2C_COMMAND8    0x00003FFFU
+#define RTC_I2C_COMMAND8_M  (RTC_I2C_COMMAND8_V << RTC_I2C_COMMAND8_S)
+#define RTC_I2C_COMMAND8_V  0x00003FFFU
+#define RTC_I2C_COMMAND8_S  0
+/** RTC_I2C_COMMAND8_DONE : RO; bitpos: [31]; default: 0;
+ *  command8_done
+ */
+#define RTC_I2C_COMMAND8_DONE    (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_M  (RTC_I2C_COMMAND8_DONE_V << RTC_I2C_COMMAND8_DONE_S)
+#define RTC_I2C_COMMAND8_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND8_DONE_S  31
+
+/** RTC_I2C_CMD9_REG register
+ *  i2c commond9 register
+ */
+#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x5c)
+/** RTC_I2C_COMMAND9 : R/W; bitpos: [13:0]; default: 2307;
+ *  command9
+ */
+#define RTC_I2C_COMMAND9    0x00003FFFU
+#define RTC_I2C_COMMAND9_M  (RTC_I2C_COMMAND9_V << RTC_I2C_COMMAND9_S)
+#define RTC_I2C_COMMAND9_V  0x00003FFFU
+#define RTC_I2C_COMMAND9_S  0
+/** RTC_I2C_COMMAND9_DONE : RO; bitpos: [31]; default: 0;
+ *  command9_done
+ */
+#define RTC_I2C_COMMAND9_DONE    (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_M  (RTC_I2C_COMMAND9_DONE_V << RTC_I2C_COMMAND9_DONE_S)
+#define RTC_I2C_COMMAND9_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND9_DONE_S  31
+
+/** RTC_I2C_CMD10_REG register
+ *  i2c commond10 register
+ */
+#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x60)
+/** RTC_I2C_COMMAND10 : R/W; bitpos: [13:0]; default: 257;
+ *  command10
+ */
+#define RTC_I2C_COMMAND10    0x00003FFFU
+#define RTC_I2C_COMMAND10_M  (RTC_I2C_COMMAND10_V << RTC_I2C_COMMAND10_S)
+#define RTC_I2C_COMMAND10_V  0x00003FFFU
+#define RTC_I2C_COMMAND10_S  0
+/** RTC_I2C_COMMAND10_DONE : RO; bitpos: [31]; default: 0;
+ *  command10_done
+ */
+#define RTC_I2C_COMMAND10_DONE    (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_M  (RTC_I2C_COMMAND10_DONE_V << RTC_I2C_COMMAND10_DONE_S)
+#define RTC_I2C_COMMAND10_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND10_DONE_S  31
+
+/** RTC_I2C_CMD11_REG register
+ *  i2c commond11 register
+ */
+#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x64)
+/** RTC_I2C_COMMAND11 : R/W; bitpos: [13:0]; default: 2305;
+ *  command11
+ */
+#define RTC_I2C_COMMAND11    0x00003FFFU
+#define RTC_I2C_COMMAND11_M  (RTC_I2C_COMMAND11_V << RTC_I2C_COMMAND11_S)
+#define RTC_I2C_COMMAND11_V  0x00003FFFU
+#define RTC_I2C_COMMAND11_S  0
+/** RTC_I2C_COMMAND11_DONE : RO; bitpos: [31]; default: 0;
+ *  command11_done
+ */
+#define RTC_I2C_COMMAND11_DONE    (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_M  (RTC_I2C_COMMAND11_DONE_V << RTC_I2C_COMMAND11_DONE_S)
+#define RTC_I2C_COMMAND11_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND11_DONE_S  31
+
+/** RTC_I2C_CMD12_REG register
+ *  i2c commond12 register
+ */
+#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x68)
+/** RTC_I2C_COMMAND12 : R/W; bitpos: [13:0]; default: 5889;
+ *  command12
+ */
+#define RTC_I2C_COMMAND12    0x00003FFFU
+#define RTC_I2C_COMMAND12_M  (RTC_I2C_COMMAND12_V << RTC_I2C_COMMAND12_S)
+#define RTC_I2C_COMMAND12_V  0x00003FFFU
+#define RTC_I2C_COMMAND12_S  0
+/** RTC_I2C_COMMAND12_DONE : RO; bitpos: [31]; default: 0;
+ *  command12_done
+ */
+#define RTC_I2C_COMMAND12_DONE    (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_M  (RTC_I2C_COMMAND12_DONE_V << RTC_I2C_COMMAND12_DONE_S)
+#define RTC_I2C_COMMAND12_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND12_DONE_S  31
+
+/** RTC_I2C_CMD13_REG register
+ *  i2c commond13 register
+ */
+#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x6c)
+/** RTC_I2C_COMMAND13 : R/W; bitpos: [13:0]; default: 6401;
+ *  command13
+ */
+#define RTC_I2C_COMMAND13    0x00003FFFU
+#define RTC_I2C_COMMAND13_M  (RTC_I2C_COMMAND13_V << RTC_I2C_COMMAND13_S)
+#define RTC_I2C_COMMAND13_V  0x00003FFFU
+#define RTC_I2C_COMMAND13_S  0
+/** RTC_I2C_COMMAND13_DONE : RO; bitpos: [31]; default: 0;
+ *  command13_done
+ */
+#define RTC_I2C_COMMAND13_DONE    (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_M  (RTC_I2C_COMMAND13_DONE_V << RTC_I2C_COMMAND13_DONE_S)
+#define RTC_I2C_COMMAND13_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND13_DONE_S  31
+
+/** RTC_I2C_CMD14_REG register
+ *  i2c commond14 register
+ */
+#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x70)
+/** RTC_I2C_COMMAND14 : R/W; bitpos: [13:0]; default: 0;
+ *  command14
+ */
+#define RTC_I2C_COMMAND14    0x00003FFFU
+#define RTC_I2C_COMMAND14_M  (RTC_I2C_COMMAND14_V << RTC_I2C_COMMAND14_S)
+#define RTC_I2C_COMMAND14_V  0x00003FFFU
+#define RTC_I2C_COMMAND14_S  0
+/** RTC_I2C_COMMAND14_DONE : RO; bitpos: [31]; default: 0;
+ *  command14_done
+ */
+#define RTC_I2C_COMMAND14_DONE    (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_M  (RTC_I2C_COMMAND14_DONE_V << RTC_I2C_COMMAND14_DONE_S)
+#define RTC_I2C_COMMAND14_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND14_DONE_S  31
+
+/** RTC_I2C_CMD15_REG register
+ *  i2c commond15 register
+ */
+#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x74)
+/** RTC_I2C_COMMAND15 : R/W; bitpos: [13:0]; default: 0;
+ *  command15
+ */
+#define RTC_I2C_COMMAND15    0x00003FFFU
+#define RTC_I2C_COMMAND15_M  (RTC_I2C_COMMAND15_V << RTC_I2C_COMMAND15_S)
+#define RTC_I2C_COMMAND15_V  0x00003FFFU
+#define RTC_I2C_COMMAND15_S  0
+/** RTC_I2C_COMMAND15_DONE : RO; bitpos: [31]; default: 0;
+ *  command15_done
+ */
+#define RTC_I2C_COMMAND15_DONE    (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_M  (RTC_I2C_COMMAND15_DONE_V << RTC_I2C_COMMAND15_DONE_S)
+#define RTC_I2C_COMMAND15_DONE_V  0x00000001U
+#define RTC_I2C_COMMAND15_DONE_S  31
+
+/** RTC_I2C_DATE_REG register
+ *  version register
+ */
+#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0xfc)
+/** RTC_I2C_I2C_DATE : R/W; bitpos: [27:0]; default: 26235664;
+ *  version
+ */
+#define RTC_I2C_I2C_DATE    0x0FFFFFFFU
+#define RTC_I2C_I2C_DATE_M  (RTC_I2C_I2C_DATE_V << RTC_I2C_I2C_DATE_S)
+#define RTC_I2C_I2C_DATE_V  0x0FFFFFFFU
+#define RTC_I2C_I2C_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h b/components/soc/esp32s3/register/soc/rtc_i2c_struct.h
similarity index 96%
rename from components/soc/esp32s3/include/soc/rtc_i2c_struct.h
rename to components/soc/esp32s3/register/soc/rtc_i2c_struct.h
index 2bac2fa5804..0d42c68906d 100644
--- a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h
+++ b/components/soc/esp32s3/register/soc/rtc_i2c_struct.h
@@ -1,16 +1,7 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
diff --git a/components/soc/esp32s3/include/soc/rtc_io_reg.h b/components/soc/esp32s3/register/soc/rtc_io_reg.h
similarity index 98%
rename from components/soc/esp32s3/include/soc/rtc_io_reg.h
rename to components/soc/esp32s3/register/soc/rtc_io_reg.h
index a324329117a..0ce66dde613 100644
--- a/components/soc/esp32s3/include/soc/rtc_io_reg.h
+++ b/components/soc/esp32s3/register/soc/rtc_io_reg.h
@@ -1,21 +1,13 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RTC_IO_REG_H_
 #define _SOC_RTC_IO_REG_H_
 
 
-#include "soc.h"
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -109,8 +101,8 @@ extern "C" {
 #define RTC_GPIO_PIN0_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN0_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN0_INT_TYPE_M  ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))
 #define RTC_GPIO_PIN0_INT_TYPE_V  0x7
@@ -131,8 +123,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN1_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN1_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN1_INT_TYPE_M  ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))
 #define RTC_GPIO_PIN1_INT_TYPE_V  0x7
@@ -153,8 +145,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN2_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN2_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN2_INT_TYPE_M  ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))
 #define RTC_GPIO_PIN2_INT_TYPE_V  0x7
@@ -175,8 +167,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN3_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN3_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN3_INT_TYPE_M  ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))
 #define RTC_GPIO_PIN3_INT_TYPE_V  0x7
@@ -197,8 +189,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN4_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN4_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN4_INT_TYPE_M  ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))
 #define RTC_GPIO_PIN4_INT_TYPE_V  0x7
@@ -219,8 +211,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN5_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN5_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN5_INT_TYPE_M  ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))
 #define RTC_GPIO_PIN5_INT_TYPE_V  0x7
@@ -241,8 +233,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN6_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN6_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN6_INT_TYPE_M  ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))
 #define RTC_GPIO_PIN6_INT_TYPE_V  0x7
@@ -263,8 +255,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN7_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN7_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN7_INT_TYPE_M  ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))
 #define RTC_GPIO_PIN7_INT_TYPE_V  0x7
@@ -285,8 +277,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN8_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN8_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN8_INT_TYPE_M  ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))
 #define RTC_GPIO_PIN8_INT_TYPE_V  0x7
@@ -307,8 +299,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN9_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN9_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN9_INT_TYPE_M  ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))
 #define RTC_GPIO_PIN9_INT_TYPE_V  0x7
@@ -329,8 +321,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN10_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN10_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN10_INT_TYPE_M  ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))
 #define RTC_GPIO_PIN10_INT_TYPE_V  0x7
@@ -351,8 +343,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN11_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN11_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN11_INT_TYPE_M  ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))
 #define RTC_GPIO_PIN11_INT_TYPE_V  0x7
@@ -373,8 +365,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN12_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN12_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN12_INT_TYPE_M  ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))
 #define RTC_GPIO_PIN12_INT_TYPE_V  0x7
@@ -395,8 +387,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN13_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN13_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN13_INT_TYPE_M  ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))
 #define RTC_GPIO_PIN13_INT_TYPE_V  0x7
@@ -417,8 +409,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN14_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN14_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN14_INT_TYPE_M  ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))
 #define RTC_GPIO_PIN14_INT_TYPE_V  0x7
@@ -439,8 +431,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN15_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN15_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN15_INT_TYPE_M  ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))
 #define RTC_GPIO_PIN15_INT_TYPE_V  0x7
@@ -461,8 +453,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN16_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN16_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN16_INT_TYPE_M  ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))
 #define RTC_GPIO_PIN16_INT_TYPE_V  0x7
@@ -483,8 +475,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN17_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN17_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN17_INT_TYPE_M  ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))
 #define RTC_GPIO_PIN17_INT_TYPE_V  0x7
@@ -505,8 +497,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN18_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN18_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN18_INT_TYPE_M  ((RTC_GPIO_PIN18_INT_TYPE_V)<<(RTC_GPIO_PIN18_INT_TYPE_S))
 #define RTC_GPIO_PIN18_INT_TYPE_V  0x7
@@ -527,8 +519,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN19_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN19_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN19_INT_TYPE_M  ((RTC_GPIO_PIN19_INT_TYPE_V)<<(RTC_GPIO_PIN19_INT_TYPE_S))
 #define RTC_GPIO_PIN19_INT_TYPE_V  0x7
@@ -549,8 +541,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN20_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN20_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN20_INT_TYPE_M  ((RTC_GPIO_PIN20_INT_TYPE_V)<<(RTC_GPIO_PIN20_INT_TYPE_S))
 #define RTC_GPIO_PIN20_INT_TYPE_V  0x7
@@ -571,8 +563,8 @@ l trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN21_WAKEUP_ENABLE_S  10
 /* RTC_GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
 /*description: if set to 0: GPIO interrupt disable,  if set to 1: rising edge trigger,  if set
-to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low leve
-l trigger,  if set to 5: high level trigger.*/
+to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low
+level trigger,  if set to 5: high level trigger.*/
 #define RTC_GPIO_PIN21_INT_TYPE    0x00000007
 #define RTC_GPIO_PIN21_INT_TYPE_M  ((RTC_GPIO_PIN21_INT_TYPE_V)<<(RTC_GPIO_PIN21_INT_TYPE_S))
 #define RTC_GPIO_PIN21_INT_TYPE_V  0x7
diff --git a/components/soc/esp32s3/include/soc/rtc_io_struct.h b/components/soc/esp32s3/register/soc/rtc_io_struct.h
similarity index 95%
rename from components/soc/esp32s3/include/soc/rtc_io_struct.h
rename to components/soc/esp32s3/register/soc/rtc_io_struct.h
index 1154be038b3..d91204e18da 100644
--- a/components/soc/esp32s3/include/soc/rtc_io_struct.h
+++ b/components/soc/esp32s3/register/soc/rtc_io_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RTC_IO_STRUCT_H_
 #define _SOC_RTC_IO_STRUCT_H_
 
diff --git a/components/soc/esp32s3/register/soc/sdmmc_reg.h b/components/soc/esp32s3/register/soc/sdmmc_reg.h
new file mode 100644
index 00000000000..84b5dd5b095
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/sdmmc_reg.h
@@ -0,0 +1,87 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+
+#define SDMMC_CTRL_REG          (DR_REG_SDMMC_BASE + 0x00)
+#define SDMMC_PWREN_REG         (DR_REG_SDMMC_BASE + 0x04)
+#define SDMMC_CLKDIV_REG        (DR_REG_SDMMC_BASE + 0x08)
+#define SDMMC_CLKSRC_REG        (DR_REG_SDMMC_BASE + 0x0c)
+#define SDMMC_CLKENA_REG        (DR_REG_SDMMC_BASE + 0x10)
+#define SDMMC_TMOUT_REG         (DR_REG_SDMMC_BASE + 0x14)
+#define SDMMC_CTYPE_REG         (DR_REG_SDMMC_BASE + 0x18)
+#define SDMMC_BLKSIZ_REG        (DR_REG_SDMMC_BASE + 0x1c)
+#define SDMMC_BYTCNT_REG        (DR_REG_SDMMC_BASE + 0x20)
+#define SDMMC_INTMASK_REG       (DR_REG_SDMMC_BASE + 0x24)
+#define SDMMC_CMDARG_REG        (DR_REG_SDMMC_BASE + 0x28)
+#define SDMMC_CMD_REG           (DR_REG_SDMMC_BASE + 0x2c)
+#define SDMMC_RESP0_REG         (DR_REG_SDMMC_BASE + 0x30)
+#define SDMMC_RESP1_REG         (DR_REG_SDMMC_BASE + 0x34)
+#define SDMMC_RESP2_REG         (DR_REG_SDMMC_BASE + 0x38)
+#define SDMMC_RESP3_REG         (DR_REG_SDMMC_BASE + 0x3c)
+
+#define SDMMC_MINTSTS_REG       (DR_REG_SDMMC_BASE + 0x40)
+#define SDMMC_RINTSTS_REG       (DR_REG_SDMMC_BASE + 0x44)
+#define SDMMC_STATUS_REG        (DR_REG_SDMMC_BASE + 0x48)
+#define SDMMC_FIFOTH_REG        (DR_REG_SDMMC_BASE + 0x4c)
+#define SDMMC_CDETECT_REG       (DR_REG_SDMMC_BASE + 0x50)
+#define SDMMC_WRTPRT_REG        (DR_REG_SDMMC_BASE + 0x54)
+#define SDMMC_GPIO_REG          (DR_REG_SDMMC_BASE + 0x58)
+#define SDMMC_TCBCNT_REG        (DR_REG_SDMMC_BASE + 0x5c)
+#define SDMMC_TBBCNT_REG        (DR_REG_SDMMC_BASE + 0x60)
+#define SDMMC_DEBNCE_REG        (DR_REG_SDMMC_BASE + 0x64)
+#define SDMMC_USRID_REG         (DR_REG_SDMMC_BASE + 0x68)
+#define SDMMC_VERID_REG         (DR_REG_SDMMC_BASE + 0x6c)
+#define SDMMC_HCON_REG          (DR_REG_SDMMC_BASE + 0x70)
+#define SDMMC_UHS_REG_REG       (DR_REG_SDMMC_BASE + 0x74)
+#define SDMMC_RST_N_REG         (DR_REG_SDMMC_BASE + 0x78)
+#define SDMMC_BMOD_REG          (DR_REG_SDMMC_BASE + 0x80)
+#define SDMMC_PLDMND_REG        (DR_REG_SDMMC_BASE + 0x84)
+#define SDMMC_DBADDR_REG        (DR_REG_SDMMC_BASE + 0x88)
+#define SDMMC_DBADDRU_REG       (DR_REG_SDMMC_BASE + 0x8c)
+#define SDMMC_IDSTS_REG         (DR_REG_SDMMC_BASE + 0x8c)
+#define SDMMC_IDINTEN_REG       (DR_REG_SDMMC_BASE + 0x90)
+#define SDMMC_DSCADDR_REG       (DR_REG_SDMMC_BASE + 0x94)
+#define SDMMC_DSCADDRL_REG      (DR_REG_SDMMC_BASE + 0x98)
+#define SDMMC_DSCADDRU_REG      (DR_REG_SDMMC_BASE + 0x9c)
+#define SDMMC_BUFADDRL_REG      (DR_REG_SDMMC_BASE + 0xa0)
+#define SDMMC_BUFADDRU_REG      (DR_REG_SDMMC_BASE + 0xa4)
+#define SDMMC_CARDTHRCTL_REG    (DR_REG_SDMMC_BASE + 0x100)
+#define SDMMC_BACK_END_POWER_REG    (DR_REG_SDMMC_BASE + 0x104)
+#define SDMMC_UHS_REG_EXT_REG   (DR_REG_SDMMC_BASE + 0x108)
+#define SDMMC_EMMC_DDR_REG_REG  (DR_REG_SDMMC_BASE + 0x10c)
+#define SDMMC_ENABLE_SHIFT_REG  (DR_REG_SDMMC_BASE + 0x110)
+
+#define SDMMC_CLOCK_REG         (DR_REG_SDMMC_BASE + 0x800)
+
+#define SDMMC_INTMASK_IO_SLOT1  BIT(17)
+#define SDMMC_INTMASK_IO_SLOT0  BIT(16)
+#define SDMMC_INTMASK_EBE       BIT(15)
+#define SDMMC_INTMASK_ACD       BIT(14)
+#define SDMMC_INTMASK_SBE       BIT(13)
+#define SDMMC_INTMASK_HLE       BIT(12)
+#define SDMMC_INTMASK_FRUN      BIT(11)
+#define SDMMC_INTMASK_HTO       BIT(10)
+#define SDMMC_INTMASK_VOLT_SW   SDMMC_INTMASK_HTO
+#define SDMMC_INTMASK_DTO       BIT(9)
+#define SDMMC_INTMASK_RTO       BIT(8)
+#define SDMMC_INTMASK_DCRC      BIT(7)
+#define SDMMC_INTMASK_RCRC      BIT(6)
+#define SDMMC_INTMASK_RXDR      BIT(5)
+#define SDMMC_INTMASK_TXDR      BIT(4)
+#define SDMMC_INTMASK_DATA_OVER BIT(3)
+#define SDMMC_INTMASK_CMD_DONE  BIT(2)
+#define SDMMC_INTMASK_RESP_ERR  BIT(1)
+#define SDMMC_INTMASK_CD        BIT(0)
+
+#define SDMMC_IDMAC_INTMASK_AI  BIT(9)
+#define SDMMC_IDMAC_INTMASK_NI  BIT(8)
+#define SDMMC_IDMAC_INTMASK_CES BIT(5)
+#define SDMMC_IDMAC_INTMASK_DU  BIT(4)
+#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
+#define SDMMC_IDMAC_INTMASK_RI  BIT(1)
+#define SDMMC_IDMAC_INTMASK_TI  BIT(0)
diff --git a/components/soc/esp32s3/include/soc/sdmmc_struct.h b/components/soc/esp32s3/register/soc/sdmmc_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/sdmmc_struct.h
rename to components/soc/esp32s3/register/soc/sdmmc_struct.h
diff --git a/components/soc/esp32s3/include/soc/sens_reg.h b/components/soc/esp32s3/register/soc/sens_reg.h
similarity index 99%
rename from components/soc/esp32s3/include/soc/sens_reg.h
rename to components/soc/esp32s3/register/soc/sens_reg.h
index ca14d862dc9..350804cf20e 100644
--- a/components/soc/esp32s3/include/soc/sens_reg.h
+++ b/components/soc/esp32s3/register/soc/sens_reg.h
@@ -7,7 +7,7 @@
 #define _SOC_SENS_REG_H_
 
 
-#include "soc.h"
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32s3/include/soc/sens_struct.h b/components/soc/esp32s3/register/soc/sens_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/sens_struct.h
rename to components/soc/esp32s3/register/soc/sens_struct.h
diff --git a/components/soc/esp32s3/register/soc/sensitive_reg.h b/components/soc/esp32s3/register/soc/sensitive_reg.h
new file mode 100644
index 00000000000..3c17e73cce0
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/sensitive_reg.h
@@ -0,0 +1,4718 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SENSITIVE_REG_H_
+#define _SOC_SENSITIVE_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG          (DR_REG_SENSITIVE_BASE + 0x0)
+/* SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK    (BIT(0))
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V  0x1
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S  0
+
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG          (DR_REG_SENSITIVE_BASE + 0x4)
+/* SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN : R/W ;bitpos:[7:0] ;default: ~8'b0 ; */
+/*description: .*/
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN    0x000000FF
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_M  ((SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V)<<(SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S))
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V  0xFF
+#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S  0
+
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x8)
+/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK    (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S  0
+
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0xC)
+/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST    (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (BIT(0))
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG          (DR_REG_SENSITIVE_BASE + 0x10)
+/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK    (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (BIT(0))
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG          (DR_REG_SENSITIVE_BASE + 0x14)
+/* SENSITIVE_INTERNAL_SRAM_CPU_USAGE : R/W ;bitpos:[10:4] ;default: ~7'h0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE    0x0000007F
+#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S))
+#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V  0x7F
+#define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S  4
+/* SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE : R/W ;bitpos:[3:2] ;default: ~2'h0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE    0x00000003
+#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S))
+#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V  0x3
+#define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S  2
+/* SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE : R/W ;bitpos:[1:0] ;default: ~2'h0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE    0x00000003
+#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S))
+#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V  0x3
+#define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG          (DR_REG_SENSITIVE_BASE + 0x18)
+/* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC    0x00000003
+#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_M  ((SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V)<<(SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S))
+#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V  0x3
+#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S  16
+/* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC    0x00000003
+#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_M  ((SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V)<<(SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S))
+#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V  0x3
+#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S  14
+/* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE : R/W ;bitpos:[13:7] ;default: 7'b0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE    0x0000007F
+#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S))
+#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V  0x7F
+#define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S  7
+/* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE    0x0000007F
+#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S))
+#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V  0x7F
+#define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG          (DR_REG_SENSITIVE_BASE + 0x1C)
+/* SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE    0x0000000F
+#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S))
+#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V  0xF
+#define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S  0
+
+#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG          (DR_REG_SENSITIVE_BASE + 0x20)
+/* SENSITIVE_INTERNAL_SRAM_LOG_USAGE : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
+/*description: .*/
+#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE    0x0000007F
+#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S))
+#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V  0x7F
+#define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S  0
+
+#define SENSITIVE_RETENTION_DISABLE_REG          (DR_REG_SENSITIVE_BASE + 0x24)
+/* SENSITIVE_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_RETENTION_DISABLE    (BIT(0))
+#define SENSITIVE_RETENTION_DISABLE_M  (BIT(0))
+#define SENSITIVE_RETENTION_DISABLE_V  0x1
+#define SENSITIVE_RETENTION_DISABLE_S  0
+
+#define SENSITIVE_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x28)
+/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK    (BIT(0))
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S  0
+
+#define SENSITIVE_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x2C)
+/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_PRO_D_TAG_WR_ACS    (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_M  (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x1
+#define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
+/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_PRO_D_TAG_RD_ACS    (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_M  (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
+/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_PRO_I_TAG_WR_ACS    (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_M  (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
+/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_PRO_I_TAG_RD_ACS    (BIT(0))
+#define SENSITIVE_PRO_I_TAG_RD_ACS_M  (BIT(0))
+#define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_RD_ACS_S  0
+
+#define SENSITIVE_CACHE_MMU_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x30)
+/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK    (BIT(0))
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (BIT(0))
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S  0
+
+#define SENSITIVE_CACHE_MMU_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x34)
+/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SENSITIVE_PRO_MMU_WR_ACS    (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_M  (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_WR_ACS_S  1
+/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SENSITIVE_PRO_MMU_RD_ACS    (BIT(0))
+#define SENSITIVE_PRO_MMU_RD_ACS_M  (BIT(0))
+#define SENSITIVE_PRO_MMU_RD_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_RD_ACS_S  0
+
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x38)
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x3C)
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x40)
+/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x44)
+/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x48)
+/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x4C)
+/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x50)
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x54)
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x58)
+/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x5C)
+/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x60)
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x64)
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x68)
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x6C)
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x70)
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x74)
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x78)
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x7C)
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x80)
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x84)
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x88)
+/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x8C)
+/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x90)
+/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x94)
+/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x98)
+/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x9C)
+/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xA0)
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xA4)
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xA8)
+/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xAC)
+/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S))
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S  6
+/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S))
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S  4
+/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S))
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S  2
+/* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S))
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
+#define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xB0)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xB4)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xB8)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[24:3] ;default: 22'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  3
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0xBC)
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
+/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xC0)
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xC4)
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR    0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S  12
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S  10
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S  8
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S  6
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xC8)
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR    0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S  12
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S  10
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S  8
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S  6
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0xCC)
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR    0x000000FF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S  12
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S  10
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S  8
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S  6
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0    0x00000003
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0xD0)
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR    0x000000FF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S  12
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S  10
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S  8
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S  6
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0xD4)
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR    0x000000FF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V  0xFF
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S  14
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S  12
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S  10
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S  8
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S  6
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S))
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xD8)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xDC)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  18
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S  15
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  12
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  9
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  6
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  3
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  0
+
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xE0)
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  18
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S  15
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  12
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  9
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  6
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  3
+/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000007
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x7
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xE4)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xE8)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xEC)
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE    (BIT(2))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
+/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xF0)
+/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xF4)
+/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xF8)
+/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
+/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
+/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE    (BIT(2))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
+/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(1))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
+/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xFC)
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x100)
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  26
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  24
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S  22
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  20
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S  10
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  8
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x104)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x108)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x10C)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK    (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x110)
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
+/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x114)
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x118)
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x11C)
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK    (BIT(1))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x120)
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
+/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x124)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x128)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S  20
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x12C)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x130)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x134)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x138)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S  20
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x13C)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x140)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x144)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S  14
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S  10
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x148)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1    0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0    0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x14C)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x150)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1    0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S  11
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0    0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x154)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S  9
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S  3
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x158)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1    0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S  11
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0    0x000007FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V  0x7FF
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x15C)
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S  9
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S  3
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x160)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x164)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S  20
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S  18
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S  16
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S  14
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x168)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S  20
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S  18
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S  16
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S  14
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0    0x00000003
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x16C)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x170)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x174)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x178)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x17C)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x180)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x184)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x188)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x18C)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x190)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x194)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S  0
+
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x198)
+/* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11    0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S))
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V  0x3FFFFFFF
+#define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x19C)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x1A0)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x1A4)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(5))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0    (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x1A8)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR    0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x1AC)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x1B0)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x1B4)
+/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x1B8)
+/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK    (BIT(0))
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V  0x1
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S  0
+
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x1BC)
+/* SENSITIVE_CORE_0_VECBASE_WORLD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK    (BIT(0))
+#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_M  (BIT(0))
+#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_V  0x1
+#define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_S  0
+
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x1C0)
+/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL    0x00000003
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S))
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V  0x3
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S  22
+/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE    0x003FFFFF
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S))
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V  0x3FFFFF
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S  0
+
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_REG          (DR_REG_SENSITIVE_BASE + 0x1C4)
+/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE    0x003FFFFF
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S))
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V  0x3FFFFF
+#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S  0
+
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x1C8)
+/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK    (BIT(0))
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V  0x1
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S  0
+
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x1CC)
+/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE    (BIT(0))
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_M  (BIT(0))
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V  0x1
+#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x1D0)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x1D4)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S  28
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S  20
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x1D8)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S  24
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S  18
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S  14
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S  12
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S  8
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x1DC)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S  16
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S  12
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S  8
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S  2
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x1E0)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S  14
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S  10
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x1E4)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S  28
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S  20
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x1E8)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S  24
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S  18
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S  14
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S  12
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S  8
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x1EC)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S  16
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S  12
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S  8
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S  2
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x1F0)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S  14
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S  10
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x1F4)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1    0x000007FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0    0x000007FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x1F8)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x1FC)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1    0x000007FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V  0x7FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S  11
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0    0x000007FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V  0x7FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x200)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S  9
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S  3
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x204)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1    0x000007FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V  0x7FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S  11
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0    0x000007FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V  0x7FF
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x208)
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S  9
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S  3
+/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S))
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x20C)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x210)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S  20
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S  18
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S  16
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S  14
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x214)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S  20
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S  18
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S  16
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S  14
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0    0x00000003
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x218)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x21C)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x220)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x224)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x228)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x22C)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x230)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x234)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x238)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x23C)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x240)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S  0
+
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x244)
+/* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11    0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S))
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V  0x3FFFFFFF
+#define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x248)
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x24C)
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x250)
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(5))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0    (BIT(1))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x254)
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR    0xFFFFFFFF
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x258)
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x25C)
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
+
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x260)
+/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFF
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
+
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x264)
+/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK    (BIT(0))
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V  0x1
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S  0
+
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x268)
+/* SENSITIVE_CORE_1_VECBASE_WORLD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK    (BIT(0))
+#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_M  (BIT(0))
+#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_V  0x1
+#define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_S  0
+
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x26C)
+/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL    0x00000003
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S))
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V  0x3
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S  22
+/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE    0x003FFFFF
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S))
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V  0x3FFFFF
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S  0
+
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_2_REG          (DR_REG_SENSITIVE_BASE + 0x270)
+/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE    0x003FFFFF
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S))
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V  0x3FFFFF
+#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S  0
+
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x274)
+/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK    (BIT(0))
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M  (BIT(0))
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V  0x1
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S  0
+
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x278)
+/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE    (BIT(0))
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_M  (BIT(0))
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V  0x1
+#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x27C)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x280)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S  30
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S  28
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S  24
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S  20
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S  16
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S  8
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S  2
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x284)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S  30
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S  28
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S  24
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S  22
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S  18
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S  16
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S  12
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S  8
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x288)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S  28
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S  22
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S  16
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S  12
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S  8
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S  2
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x28C)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S  30
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S  28
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S  26
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S  24
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S  22
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S  20
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S  18
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S  16
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S  14
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S  12
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S  10
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S  8
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S  4
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S  2
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x290)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR    0x000007FF
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V  0x7FF
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x294)
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H    0x00000007
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V  0x7
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S  3
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L    0x00000007
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V  0x7
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x298)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK    (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x29C)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S  1
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x2A0)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(6))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(6))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  6
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  3
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS    0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S  1
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S  0
+
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x2A4)
+/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR    0xFFFFFFFF
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V  0xFFFFFFFF
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S  0
+
+#define SENSITIVE_EDMA_BOUNDARY_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2A8)
+/* SENSITIVE_EDMA_BOUNDARY_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_BOUNDARY_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_BOUNDARY_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_BOUNDARY_LOCK_V  0x1
+#define SENSITIVE_EDMA_BOUNDARY_LOCK_S  0
+
+#define SENSITIVE_EDMA_BOUNDARY_0_REG          (DR_REG_SENSITIVE_BASE + 0x2AC)
+/* SENSITIVE_EDMA_BOUNDARY_0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_BOUNDARY_0    0x00003FFF
+#define SENSITIVE_EDMA_BOUNDARY_0_M  ((SENSITIVE_EDMA_BOUNDARY_0_V)<<(SENSITIVE_EDMA_BOUNDARY_0_S))
+#define SENSITIVE_EDMA_BOUNDARY_0_V  0x3FFF
+#define SENSITIVE_EDMA_BOUNDARY_0_S  0
+
+#define SENSITIVE_EDMA_BOUNDARY_1_REG          (DR_REG_SENSITIVE_BASE + 0x2B0)
+/* SENSITIVE_EDMA_BOUNDARY_1 : R/W ;bitpos:[13:0] ;default: 14'h2000 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_BOUNDARY_1    0x00003FFF
+#define SENSITIVE_EDMA_BOUNDARY_1_M  ((SENSITIVE_EDMA_BOUNDARY_1_V)<<(SENSITIVE_EDMA_BOUNDARY_1_S))
+#define SENSITIVE_EDMA_BOUNDARY_1_V  0x3FFF
+#define SENSITIVE_EDMA_BOUNDARY_1_S  0
+
+#define SENSITIVE_EDMA_BOUNDARY_2_REG          (DR_REG_SENSITIVE_BASE + 0x2B4)
+/* SENSITIVE_EDMA_BOUNDARY_2 : R/W ;bitpos:[13:0] ;default: 14'h2000 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_BOUNDARY_2    0x00003FFF
+#define SENSITIVE_EDMA_BOUNDARY_2_M  ((SENSITIVE_EDMA_BOUNDARY_2_V)<<(SENSITIVE_EDMA_BOUNDARY_2_S))
+#define SENSITIVE_EDMA_BOUNDARY_2_V  0x3FFF
+#define SENSITIVE_EDMA_BOUNDARY_2_S  0
+
+#define SENSITIVE_EDMA_PMS_SPI2_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2B8)
+/* SENSITIVE_EDMA_PMS_SPI2_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SPI2_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_SPI2_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_SPI2_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_SPI2_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_SPI2_REG          (DR_REG_SENSITIVE_BASE + 0x2BC)
+/* SENSITIVE_EDMA_PMS_SPI2_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SPI2_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_M  ((SENSITIVE_EDMA_PMS_SPI2_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_SPI2_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_SPI2_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SPI2_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_M  ((SENSITIVE_EDMA_PMS_SPI2_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_SPI2_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_SPI3_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2C0)
+/* SENSITIVE_EDMA_PMS_SPI3_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SPI3_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_SPI3_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_SPI3_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_SPI3_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_SPI3_REG          (DR_REG_SENSITIVE_BASE + 0x2C4)
+/* SENSITIVE_EDMA_PMS_SPI3_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SPI3_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_M  ((SENSITIVE_EDMA_PMS_SPI3_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_SPI3_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_SPI3_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SPI3_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_M  ((SENSITIVE_EDMA_PMS_SPI3_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_SPI3_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2C8)
+/* SENSITIVE_EDMA_PMS_UHCI0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_UHCI0_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_UHCI0_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_UHCI0_REG          (DR_REG_SENSITIVE_BASE + 0x2CC)
+/* SENSITIVE_EDMA_PMS_UHCI0_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_M  ((SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_UHCI0_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_M  ((SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_I2S0_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2D0)
+/* SENSITIVE_EDMA_PMS_I2S0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_I2S0_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_I2S0_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_I2S0_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_I2S0_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_I2S0_REG          (DR_REG_SENSITIVE_BASE + 0x2D4)
+/* SENSITIVE_EDMA_PMS_I2S0_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_I2S0_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_M  ((SENSITIVE_EDMA_PMS_I2S0_ATTR2_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_I2S0_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_I2S0_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_I2S0_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_M  ((SENSITIVE_EDMA_PMS_I2S0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_I2S0_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_I2S1_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2D8)
+/* SENSITIVE_EDMA_PMS_I2S1_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_I2S1_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_I2S1_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_I2S1_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_I2S1_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_I2S1_REG          (DR_REG_SENSITIVE_BASE + 0x2DC)
+/* SENSITIVE_EDMA_PMS_I2S1_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_I2S1_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_M  ((SENSITIVE_EDMA_PMS_I2S1_ATTR2_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_I2S1_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_I2S1_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_I2S1_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_M  ((SENSITIVE_EDMA_PMS_I2S1_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_I2S1_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2E0)
+/* SENSITIVE_EDMA_PMS_LCD_CAM_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_LCD_CAM_REG          (DR_REG_SENSITIVE_BASE + 0x2E4)
+/* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_M  ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_M  ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_AES_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2E8)
+/* SENSITIVE_EDMA_PMS_AES_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_AES_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_AES_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_AES_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_AES_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_AES_REG          (DR_REG_SENSITIVE_BASE + 0x2EC)
+/* SENSITIVE_EDMA_PMS_AES_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_AES_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_AES_ATTR2_M  ((SENSITIVE_EDMA_PMS_AES_ATTR2_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_AES_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_AES_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_AES_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_AES_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_AES_ATTR1_M  ((SENSITIVE_EDMA_PMS_AES_ATTR1_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_AES_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_AES_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_SHA_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2F0)
+/* SENSITIVE_EDMA_PMS_SHA_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SHA_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_SHA_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_SHA_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_SHA_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_SHA_REG          (DR_REG_SENSITIVE_BASE + 0x2F4)
+/* SENSITIVE_EDMA_PMS_SHA_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SHA_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_SHA_ATTR2_M  ((SENSITIVE_EDMA_PMS_SHA_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_SHA_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_SHA_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_SHA_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_SHA_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_SHA_ATTR1_M  ((SENSITIVE_EDMA_PMS_SHA_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_SHA_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_SHA_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2F8)
+/* SENSITIVE_EDMA_PMS_ADC_DAC_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_ADC_DAC_REG          (DR_REG_SENSITIVE_BASE + 0x2FC)
+/* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_M  ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_M  ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S  0
+
+#define SENSITIVE_EDMA_PMS_RMT_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x300)
+/* SENSITIVE_EDMA_PMS_RMT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_RMT_LOCK    (BIT(0))
+#define SENSITIVE_EDMA_PMS_RMT_LOCK_M  (BIT(0))
+#define SENSITIVE_EDMA_PMS_RMT_LOCK_V  0x1
+#define SENSITIVE_EDMA_PMS_RMT_LOCK_S  0
+
+#define SENSITIVE_EDMA_PMS_RMT_REG          (DR_REG_SENSITIVE_BASE + 0x304)
+/* SENSITIVE_EDMA_PMS_RMT_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_RMT_ATTR2    0x00000003
+#define SENSITIVE_EDMA_PMS_RMT_ATTR2_M  ((SENSITIVE_EDMA_PMS_RMT_ATTR2_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR2_S))
+#define SENSITIVE_EDMA_PMS_RMT_ATTR2_V  0x3
+#define SENSITIVE_EDMA_PMS_RMT_ATTR2_S  2
+/* SENSITIVE_EDMA_PMS_RMT_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: .*/
+#define SENSITIVE_EDMA_PMS_RMT_ATTR1    0x00000003
+#define SENSITIVE_EDMA_PMS_RMT_ATTR1_M  ((SENSITIVE_EDMA_PMS_RMT_ATTR1_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR1_S))
+#define SENSITIVE_EDMA_PMS_RMT_ATTR1_V  0x3
+#define SENSITIVE_EDMA_PMS_RMT_ATTR1_S  0
+
+#define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x308)
+/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SENSITIVE_CLK_EN    (BIT(0))
+#define SENSITIVE_CLK_EN_M  (BIT(0))
+#define SENSITIVE_CLK_EN_V  0x1
+#define SENSITIVE_CLK_EN_S  0
+
+#define SENSITIVE_RTC_PMS_REG          (DR_REG_SENSITIVE_BASE + 0x30C)
+/* SENSITIVE_DIS_RTC_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SENSITIVE_DIS_RTC_CPU    (BIT(0))
+#define SENSITIVE_DIS_RTC_CPU_M  (BIT(0))
+#define SENSITIVE_DIS_RTC_CPU_V  0x1
+#define SENSITIVE_DIS_RTC_CPU_S  0
+
+#define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
+/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101280 ; */
+/*description: .*/
+#define SENSITIVE_DATE    0x0FFFFFFF
+#define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
+#define SENSITIVE_DATE_V  0xFFFFFFF
+#define SENSITIVE_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/sensitive_struct.h b/components/soc/esp32s3/register/soc/sensitive_struct.h
new file mode 100644
index 00000000000..c6102c055b5
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/sensitive_struct.h
@@ -0,0 +1,2745 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SENSITIVE_STRUCT_H_
+#define _SOC_SENSITIVE_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct sensitive_dev_s {
+    union {
+        struct {
+            uint32_t cache_dataarray_connect_lock  :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_dataarray_connect_0;
+    union {
+        struct {
+            uint32_t cache_dataarray_connect_flatten:    8;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } cache_dataarray_connect_1;
+    union {
+        struct {
+            uint32_t apb_peripheral_access_lock    :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } apb_peripheral_access_0;
+    union {
+        struct {
+            uint32_t apb_peripheral_access_split_burst:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } apb_peripheral_access_1;
+    union {
+        struct {
+            uint32_t internal_sram_usage_lock      :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } internal_sram_usage_0;
+    union {
+        struct {
+            uint32_t internal_sram_icache_usage    :    2;
+            uint32_t internal_sram_dcache_usage    :    2;
+            uint32_t internal_sram_cpu_usage       :    7;
+            uint32_t reserved11                    :    21;
+        };
+        uint32_t val;
+    } internal_sram_usage_1;
+    union {
+        struct {
+            uint32_t internal_sram_core0_trace_usage:    7;
+            uint32_t internal_sram_core1_trace_usage:    7;
+            uint32_t internal_sram_core0_trace_alloc:    2;
+            uint32_t internal_sram_core1_trace_alloc:    2;
+            uint32_t reserved18                    :    14;
+        };
+        uint32_t val;
+    } internal_sram_usage_2;
+    union {
+        struct {
+            uint32_t internal_sram_mac_dump_usage  :    4;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } internal_sram_usage_3;
+    union {
+        struct {
+            uint32_t internal_sram_log_usage       :    7;
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } internal_sram_usage_4;
+    union {
+        struct {
+            uint32_t retention_disable             :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } retention_disable;
+    union {
+        struct {
+            uint32_t cache_tag_access_lock         :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_tag_access_0;
+    union {
+        struct {
+            uint32_t pro_i_tag_rd_acs              :    1;
+            uint32_t pro_i_tag_wr_acs              :    1;
+            uint32_t pro_d_tag_rd_acs              :    1;
+            uint32_t pro_d_tag_wr_acs              :    1;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } cache_tag_access_1;
+    union {
+        struct {
+            uint32_t cache_mmu_access_lock         :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cache_mmu_access_0;
+    union {
+        struct {
+            uint32_t pro_mmu_rd_acs                :    1;
+            uint32_t pro_mmu_wr_acs                :    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } cache_mmu_access_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_spi2_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_spi2_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_spi2_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_spi2_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_spi2_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_spi3_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_spi3_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_spi3_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_spi3_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_spi3_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_uhci0_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_uhci0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_uhci0_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_uhci0_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_uhci0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_i2s0_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_i2s0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_i2s0_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_i2s0_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_i2s0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_i2s1_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_i2s1_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_i2s1_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_i2s1_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_i2s1_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_mac_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_mac_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_mac_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_mac_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_mac_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_mac_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_mac_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_mac_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_backup_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_backup_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_backup_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_backup_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_backup_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_backup_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_backup_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_backup_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_aes_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_aes_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_aes_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_aes_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_aes_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_aes_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_aes_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_aes_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_sha_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_sha_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_sha_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_sha_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_sha_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_sha_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_sha_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_sha_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_adc_dac_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_adc_dac_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_adc_dac_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_adc_dac_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_rmt_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_rmt_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_rmt_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_rmt_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_rmt_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_lcd_cam_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_lcd_cam_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_lcd_cam_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_usb_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_usb_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_usb_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_usb_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_usb_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_usb_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_usb_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_usb_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_lc_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_lc_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_lc_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_lc_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_lc_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_lc_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_lc_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_lc_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_sdio_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_sdio_pms_constrain_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_0:    2;
+            uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_1:    2;
+            uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_2:    2;
+            uint32_t dma_apbperi_sdio_pms_constrain_sram_pms_3:    2;
+            uint32_t dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_0:    2;
+            uint32_t dma_apbperi_sdio_pms_constrain_sram_cachedataarray_pms_1:    2;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } dma_apbperi_sdio_pms_constrain_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_pms_monitor_lock  :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_0;
+    union {
+        struct {
+            uint32_t dma_apbperi_pms_monitor_violate_clr:    1;
+            uint32_t dma_apbperi_pms_monitor_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_1;
+    union {
+        struct {
+            uint32_t dma_apbperi_pms_monitor_violate_intr:    1;
+            uint32_t dma_apbperi_pms_monitor_violate_status_world:    2;
+            uint32_t dma_apbperi_pms_monitor_violate_status_addr:    22;
+            uint32_t reserved25                    :    7;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_2;
+    union {
+        struct {
+            uint32_t dma_apbperi_pms_monitor_violate_status_wr:    1;
+            uint32_t dma_apbperi_pms_monitor_violate_status_byteen:    16;
+            uint32_t reserved17                    :    15;
+        };
+        uint32_t val;
+    } dma_apbperi_pms_monitor_3;
+    union {
+        struct {
+            uint32_t core_x_iram0_dram0_dma_split_line_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_0;
+    union {
+        struct {
+            uint32_t core_x_iram0_dram0_dma_sram_category_0:    2;
+            uint32_t core_x_iram0_dram0_dma_sram_category_1:    2;
+            uint32_t core_x_iram0_dram0_dma_sram_category_2:    2;
+            uint32_t core_x_iram0_dram0_dma_sram_category_3:    2;
+            uint32_t core_x_iram0_dram0_dma_sram_category_4:    2;
+            uint32_t core_x_iram0_dram0_dma_sram_category_5:    2;
+            uint32_t core_x_iram0_dram0_dma_sram_category_6:    2;
+            uint32_t core_x_iram0_dram0_dma_sram_splitaddr:    8;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_1;
+    union {
+        struct {
+            uint32_t core_x_iram0_sram_line_0_category_0:    2;
+            uint32_t core_x_iram0_sram_line_0_category_1:    2;
+            uint32_t core_x_iram0_sram_line_0_category_2:    2;
+            uint32_t core_x_iram0_sram_line_0_category_3:    2;
+            uint32_t core_x_iram0_sram_line_0_category_4:    2;
+            uint32_t core_x_iram0_sram_line_0_category_5:    2;
+            uint32_t core_x_iram0_sram_line_0_category_6:    2;
+            uint32_t core_x_iram0_sram_line_0_splitaddr:    8;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_2;
+    union {
+        struct {
+            uint32_t core_x_iram0_sram_line_1_category_0:    2;
+            uint32_t core_x_iram0_sram_line_1_category_1:    2;
+            uint32_t core_x_iram0_sram_line_1_category_2:    2;
+            uint32_t core_x_iram0_sram_line_1_category_3:    2;
+            uint32_t core_x_iram0_sram_line_1_category_4:    2;
+            uint32_t core_x_iram0_sram_line_1_category_5:    2;
+            uint32_t core_x_iram0_sram_line_1_category_6:    2;
+            uint32_t core_x_iram0_sram_line_1_splitaddr:    8;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_3;
+    union {
+        struct {
+            uint32_t core_x_dram0_dma_sram_line_0_category_0:    2;
+            uint32_t core_x_dram0_dma_sram_line_0_category_1:    2;
+            uint32_t core_x_dram0_dma_sram_line_0_category_2:    2;
+            uint32_t core_x_dram0_dma_sram_line_0_category_3:    2;
+            uint32_t core_x_dram0_dma_sram_line_0_category_4:    2;
+            uint32_t core_x_dram0_dma_sram_line_0_category_5:    2;
+            uint32_t core_x_dram0_dma_sram_line_0_category_6:    2;
+            uint32_t core_x_dram0_dma_sram_line_0_splitaddr:    8;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_4;
+    union {
+        struct {
+            uint32_t core_x_dram0_dma_sram_line_1_category_0:    2;
+            uint32_t core_x_dram0_dma_sram_line_1_category_1:    2;
+            uint32_t core_x_dram0_dma_sram_line_1_category_2:    2;
+            uint32_t core_x_dram0_dma_sram_line_1_category_3:    2;
+            uint32_t core_x_dram0_dma_sram_line_1_category_4:    2;
+            uint32_t core_x_dram0_dma_sram_line_1_category_5:    2;
+            uint32_t core_x_dram0_dma_sram_line_1_category_6:    2;
+            uint32_t core_x_dram0_dma_sram_line_1_splitaddr:    8;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_x_iram0_dram0_dma_split_line_constrain_5;
+    union {
+        struct {
+            uint32_t core_x_iram0_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_0:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_1:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_2:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_3:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1:    3;
+            uint32_t core_x_iram0_pms_constrain_rom_world_1_pms:    3;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_0:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_1:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_2:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_3:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0:    3;
+            uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1:    3;
+            uint32_t core_x_iram0_pms_constrain_rom_world_0_pms:    3;
+            uint32_t reserved21                    :    11;
+        };
+        uint32_t val;
+    } core_x_iram0_pms_constrain_2;
+    union {
+        struct {
+            uint32_t core_0_iram0_pms_monitor_lock :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_0;
+    union {
+        struct {
+            uint32_t core_0_iram0_pms_monitor_violate_clr:    1;
+            uint32_t core_0_iram0_pms_monitor_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_1;
+    union {
+        struct {
+            uint32_t core_0_iram0_pms_monitor_violate_intr:    1;
+            uint32_t core_0_iram0_pms_monitor_violate_status_wr:    1;
+            uint32_t core_0_iram0_pms_monitor_violate_status_loadstore:    1;
+            uint32_t core_0_iram0_pms_monitor_violate_status_world:    2;
+            uint32_t core_0_iram0_pms_monitor_violate_status_addr:    24;
+            uint32_t reserved29                    :    3;
+        };
+        uint32_t val;
+    } core_0_iram0_pms_monitor_2;
+    union {
+        struct {
+            uint32_t core_1_iram0_pms_monitor_lock :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_iram0_pms_monitor_0;
+    union {
+        struct {
+            uint32_t core_1_iram0_pms_monitor_violate_clr:    1;
+            uint32_t core_1_iram0_pms_monitor_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_1_iram0_pms_monitor_1;
+    union {
+        struct {
+            uint32_t core_1_iram0_pms_monitor_violate_intr:    1;
+            uint32_t core_1_iram0_pms_monitor_violate_status_wr:    1;
+            uint32_t core_1_iram0_pms_monitor_violate_status_loadstore:    1;
+            uint32_t core_1_iram0_pms_monitor_violate_status_world:    2;
+            uint32_t core_1_iram0_pms_monitor_violate_status_addr:    24;
+            uint32_t reserved29                    :    3;
+        };
+        uint32_t val;
+    } core_1_iram0_pms_monitor_2;
+    union {
+        struct {
+            uint32_t core_x_dram0_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_x_dram0_pms_constrain_0;
+    union {
+        struct {
+            uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_0:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_1:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_2:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_3:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_0:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_1:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_2:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_3:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0:    2;
+            uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1:    2;
+            uint32_t core_x_dram0_pms_constrain_rom_world_0_pms:    2;
+            uint32_t core_x_dram0_pms_constrain_rom_world_1_pms:    2;
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } core_x_dram0_pms_constrain_1;
+    union {
+        struct {
+            uint32_t core_0_dram0_pms_monitor_lock :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_0;
+    union {
+        struct {
+            uint32_t core_0_dram0_pms_monitor_violate_clr:    1;
+            uint32_t core_0_dram0_pms_monitor_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_1;
+    union {
+        struct {
+            uint32_t core_0_dram0_pms_monitor_violate_intr:    1;
+            uint32_t core_0_dram0_pms_monitor_violate_status_lock:    1;
+            uint32_t core_0_dram0_pms_monitor_violate_status_world:    2;
+            uint32_t core_0_dram0_pms_monitor_violate_status_addr:    22;
+            uint32_t reserved26                    :    6;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_2;
+    union {
+        struct {
+            uint32_t core_0_dram0_pms_monitor_violate_status_wr:    1;
+            uint32_t core_0_dram0_pms_monitor_violate_status_byteen:    16;
+            uint32_t reserved17                    :    15;
+        };
+        uint32_t val;
+    } core_0_dram0_pms_monitor_3;
+    union {
+        struct {
+            uint32_t core_1_dram0_pms_monitor_lock :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_dram0_pms_monitor_0;
+    union {
+        struct {
+            uint32_t core_1_dram0_pms_monitor_violate_clr:    1;
+            uint32_t core_1_dram0_pms_monitor_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_1_dram0_pms_monitor_1;
+    union {
+        struct {
+            uint32_t core_1_dram0_pms_monitor_violate_intr:    1;
+            uint32_t core_1_dram0_pms_monitor_violate_status_lock:    1;
+            uint32_t core_1_dram0_pms_monitor_violate_status_world:    2;
+            uint32_t core_1_dram0_pms_monitor_violate_status_addr:    22;
+            uint32_t reserved26                    :    6;
+        };
+        uint32_t val;
+    } core_1_dram0_pms_monitor_2;
+    union {
+        struct {
+            uint32_t core_1_dram0_pms_monitor_violate_status_wr:    1;
+            uint32_t core_1_dram0_pms_monitor_violate_status_byteen:    16;
+            uint32_t reserved17                    :    15;
+        };
+        uint32_t val;
+    } core_1_dram0_pms_monitor_3;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_lock :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_0;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_world_0_uart:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_g0spi_1:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_g0spi_0:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_gpio:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_fe2:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_fe:    2;
+            uint32_t reserved12                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_0_rtc:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_io_mux:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_0_hinf:    2;
+            uint32_t reserved22                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_0_misc:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_i2c:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_i2s0:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_uart1:    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_1;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_world_0_bt:    2;
+            uint32_t reserved2                     :    2;
+            uint32_t core_0_pif_pms_constrain_world_0_i2c_ext0:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_uhci0:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_slchost:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_rmt:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_pcnt:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_slc:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_ledc:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_backup:    2;
+            uint32_t reserved20                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_0_bb:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_pwm0:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_timergroup:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_timergroup1:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_systimer:    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_2;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_world_0_spi_2:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_spi_3:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_apb_ctrl:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_i2c_ext1:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_sdio_host:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_can:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_pwm1:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_i2s1:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_uart2:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t reserved20                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_0_rwbt:    2;
+            uint32_t reserved24                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_0_wifimac:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_pwr:    2;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_3;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_world_0_usb_device:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_usb_wrap:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_crypto_peri:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_crypto_dma:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_apb_adc:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_lcd_cam:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_bt_pwr:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_usb:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_system:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_sensitive:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_interrupt:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_dma_copy:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_cache_config:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_ad:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_dio:    2;
+            uint32_t core_0_pif_pms_constrain_world_0_world_controller:    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_4;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_world_1_uart:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_g0spi_1:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_g0spi_0:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_gpio:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_fe2:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_fe:    2;
+            uint32_t reserved12                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_1_rtc:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_io_mux:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_1_hinf:    2;
+            uint32_t reserved22                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_1_misc:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_i2c:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_i2s0:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_uart1:    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_5;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_world_1_bt:    2;
+            uint32_t reserved2                     :    2;
+            uint32_t core_0_pif_pms_constrain_world_1_i2c_ext0:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_uhci0:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_slchost:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_rmt:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_pcnt:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_slc:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_ledc:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_backup:    2;
+            uint32_t reserved20                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_1_bb:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_pwm0:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_timergroup:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_timergroup1:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_systimer:    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_6;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_world_1_spi_2:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_spi_3:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_apb_ctrl:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_i2c_ext1:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_sdio_host:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_can:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_pwm1:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_i2s1:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_uart2:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t reserved20                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_1_rwbt:    2;
+            uint32_t reserved24                    :    2;
+            uint32_t core_0_pif_pms_constrain_world_1_wifimac:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_pwr:    2;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_7;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_world_1_usb_device:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_usb_wrap:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_crypto_peri:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_crypto_dma:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_apb_adc:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_lcd_cam:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_bt_pwr:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_usb:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_system:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_sensitive:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_interrupt:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_dma_copy:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_cache_config:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_ad:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_dio:    2;
+            uint32_t core_0_pif_pms_constrain_world_1_world_controller:    2;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_8;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:    11;
+            uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_1:    11;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_9;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_rtcfast_world_0_l:    3;
+            uint32_t core_0_pif_pms_constrain_rtcfast_world_0_h:    3;
+            uint32_t core_0_pif_pms_constrain_rtcfast_world_1_l:    3;
+            uint32_t core_0_pif_pms_constrain_rtcfast_world_1_h:    3;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_10;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0:    11;
+            uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1:    11;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_11;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_l:    3;
+            uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_h:    3;
+            uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_l:    3;
+            uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_h:    3;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_12;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0:    11;
+            uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1:    11;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_13;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_l:    3;
+            uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_h:    3;
+            uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_l:    3;
+            uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_h:    3;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_0_pif_pms_constrain_14;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_0;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_world_0_area_0:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_1:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_2:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_3:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_4:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_5:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_6:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_7:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_8:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_9:    2;
+            uint32_t core_0_region_pms_constrain_world_0_area_10:    2;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_1;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_world_1_area_0:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_1:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_2:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_3:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_4:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_5:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_6:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_7:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_8:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_9:    2;
+            uint32_t core_0_region_pms_constrain_world_1_area_10:    2;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_2;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_0:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_3;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_1:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_4;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_2:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_5;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_3:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_6;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_4:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_7;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_5:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_8;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_6:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_9;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_7:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_10;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_8:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_11;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_9:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_12;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_10:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_13;
+    union {
+        struct {
+            uint32_t core_0_region_pms_constrain_addr_11:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_0_region_pms_constrain_14;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_monitor_lock   :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_0;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_monitor_violate_clr:    1;
+            uint32_t core_0_pif_pms_monitor_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_1;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_monitor_violate_intr:    1;
+            uint32_t core_0_pif_pms_monitor_violate_status_hport_0:    1;
+            uint32_t core_0_pif_pms_monitor_violate_status_hsize:    3;
+            uint32_t core_0_pif_pms_monitor_violate_status_hwrite:    1;
+            uint32_t core_0_pif_pms_monitor_violate_status_hworld:    2;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_2;
+    uint32_t core_0_pif_pms_monitor_3;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_monitor_nonword_violate_clr:    1;
+            uint32_t core_0_pif_pms_monitor_nonword_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_4;
+    union {
+        struct {
+            uint32_t core_0_pif_pms_monitor_nonword_violate_intr:    1;
+            uint32_t core_0_pif_pms_monitor_nonword_violate_status_hsize:    2;
+            uint32_t core_0_pif_pms_monitor_nonword_violate_status_hworld:    2;
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core_0_pif_pms_monitor_5;
+    uint32_t core_0_pif_pms_monitor_6;
+    union {
+        struct {
+            uint32_t core_0_vecbase_override_lock  :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_vecbase_override_lock;
+    union {
+        struct {
+            uint32_t core_0_vecbase_world_mask     :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_vecbase_override_0;
+    union {
+        struct {
+            uint32_t core_0_vecbase_override_world0_value:    22;
+            uint32_t core_0_vecbase_override_sel   :    2;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } core_0_vecbase_override_1;
+    union {
+        struct {
+            uint32_t core_0_vecbase_override_world1_value:    22;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_0_vecbase_override_2;
+    union {
+        struct {
+            uint32_t core_0_toomanyexceptions_m_override_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_toomanyexceptions_m_override_0;
+    union {
+        struct {
+            uint32_t core_0_toomanyexceptions_m_override:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_0_toomanyexceptions_m_override_1;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_lock :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_0;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_world_0_uart:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_g0spi_1:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_g0spi_0:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_gpio:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_fe2:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_fe:    2;
+            uint32_t reserved12                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_0_rtc:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_io_mux:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_0_hinf:    2;
+            uint32_t reserved22                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_0_misc:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_i2c:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_i2s0:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_uart1:    2;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_1;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_world_0_bt:    2;
+            uint32_t reserved2                     :    2;
+            uint32_t core_1_pif_pms_constrain_world_0_i2c_ext0:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_uhci0:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_slchost:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_rmt:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_pcnt:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_slc:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_ledc:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_backup:    2;
+            uint32_t reserved20                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_0_bb:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_pwm0:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_timergroup:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_timergroup1:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_systimer:    2;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_2;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_world_0_spi_2:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_spi_3:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_apb_ctrl:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_i2c_ext1:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_sdio_host:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_can:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_pwm1:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_i2s1:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_uart2:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t reserved20                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_0_rwbt:    2;
+            uint32_t reserved24                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_0_wifimac:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_pwr:    2;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_3;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_world_0_usb_device:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_usb_wrap:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_crypto_peri:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_crypto_dma:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_apb_adc:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_lcd_cam:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_bt_pwr:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_usb:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_system:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_sensitive:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_interrupt:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_dma_copy:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_cache_config:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_ad:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_dio:    2;
+            uint32_t core_1_pif_pms_constrain_world_0_world_controller:    2;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_4;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_world_1_uart:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_g0spi_1:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_g0spi_0:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_gpio:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_fe2:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_fe:    2;
+            uint32_t reserved12                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_1_rtc:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_io_mux:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_1_hinf:    2;
+            uint32_t reserved22                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_1_misc:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_i2c:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_i2s0:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_uart1:    2;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_5;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_world_1_bt:    2;
+            uint32_t reserved2                     :    2;
+            uint32_t core_1_pif_pms_constrain_world_1_i2c_ext0:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_uhci0:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_slchost:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_rmt:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_pcnt:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_slc:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_ledc:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_backup:    2;
+            uint32_t reserved20                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_1_bb:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_pwm0:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_timergroup:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_timergroup1:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_systimer:    2;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_6;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_world_1_spi_2:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_spi_3:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_apb_ctrl:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_i2c_ext1:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_sdio_host:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_can:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_pwm1:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_i2s1:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_uart2:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t reserved20                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_1_rwbt:    2;
+            uint32_t reserved24                    :    2;
+            uint32_t core_1_pif_pms_constrain_world_1_wifimac:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_pwr:    2;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_7;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_world_1_usb_device:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_usb_wrap:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_crypto_peri:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_crypto_dma:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_apb_adc:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_lcd_cam:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_bt_pwr:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_usb:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_system:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_sensitive:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_interrupt:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_dma_copy:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_cache_config:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_ad:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_dio:    2;
+            uint32_t core_1_pif_pms_constrain_world_1_world_controller:    2;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_8;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_0:    11;
+            uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_1:    11;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_9;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_rtcfast_world_0_l:    3;
+            uint32_t core_1_pif_pms_constrain_rtcfast_world_0_h:    3;
+            uint32_t core_1_pif_pms_constrain_rtcfast_world_1_l:    3;
+            uint32_t core_1_pif_pms_constrain_rtcfast_world_1_h:    3;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_10;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0:    11;
+            uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1:    11;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_11;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_rtcslow_0_world_0_l:    3;
+            uint32_t core_1_pif_pms_constrain_rtcslow_0_world_0_h:    3;
+            uint32_t core_1_pif_pms_constrain_rtcslow_0_world_1_l:    3;
+            uint32_t core_1_pif_pms_constrain_rtcslow_0_world_1_h:    3;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_12;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0:    11;
+            uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1:    11;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_13;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_constrain_rtcslow_1_world_0_l:    3;
+            uint32_t core_1_pif_pms_constrain_rtcslow_1_world_0_h:    3;
+            uint32_t core_1_pif_pms_constrain_rtcslow_1_world_1_l:    3;
+            uint32_t core_1_pif_pms_constrain_rtcslow_1_world_1_h:    3;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } core_1_pif_pms_constrain_14;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_0;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_world_0_area_0:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_1:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_2:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_3:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_4:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_5:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_6:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_7:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_8:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_9:    2;
+            uint32_t core_1_region_pms_constrain_world_0_area_10:    2;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_1;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_world_1_area_0:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_1:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_2:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_3:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_4:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_5:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_6:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_7:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_8:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_9:    2;
+            uint32_t core_1_region_pms_constrain_world_1_area_10:    2;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_2;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_0:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_3;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_1:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_4;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_2:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_5;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_3:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_6;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_4:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_7;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_5:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_8;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_6:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_9;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_7:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_10;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_8:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_11;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_9:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_12;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_10:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_13;
+    union {
+        struct {
+            uint32_t core_1_region_pms_constrain_addr_11:    30;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } core_1_region_pms_constrain_14;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_monitor_lock   :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_pif_pms_monitor_0;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_monitor_violate_clr:    1;
+            uint32_t core_1_pif_pms_monitor_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_1_pif_pms_monitor_1;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_monitor_violate_intr:    1;
+            uint32_t core_1_pif_pms_monitor_violate_status_hport_0:    1;
+            uint32_t core_1_pif_pms_monitor_violate_status_hsize:    3;
+            uint32_t core_1_pif_pms_monitor_violate_status_hwrite:    1;
+            uint32_t core_1_pif_pms_monitor_violate_status_hworld:    2;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } core_1_pif_pms_monitor_2;
+    uint32_t core_1_pif_pms_monitor_3;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_monitor_nonword_violate_clr:    1;
+            uint32_t core_1_pif_pms_monitor_nonword_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } core_1_pif_pms_monitor_4;
+    union {
+        struct {
+            uint32_t core_1_pif_pms_monitor_nonword_violate_intr:    1;
+            uint32_t core_1_pif_pms_monitor_nonword_violate_status_hsize:    2;
+            uint32_t core_1_pif_pms_monitor_nonword_violate_status_hworld:    2;
+            uint32_t reserved5                     :    27;
+        };
+        uint32_t val;
+    } core_1_pif_pms_monitor_5;
+    uint32_t core_1_pif_pms_monitor_6;
+    union {
+        struct {
+            uint32_t core_1_vecbase_override_lock  :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_vecbase_override_lock;
+    union {
+        struct {
+            uint32_t core_1_vecbase_world_mask     :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_vecbase_override_0;
+    union {
+        struct {
+            uint32_t core_1_vecbase_override_world0_value:    22;
+            uint32_t core_1_vecbase_override_sel   :    2;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } core_1_vecbase_override_1;
+    union {
+        struct {
+            uint32_t core_1_vecbase_override_world1_value:    22;
+            uint32_t reserved22                    :    10;
+        };
+        uint32_t val;
+    } core_1_vecbase_override_2;
+    union {
+        struct {
+            uint32_t core_1_toomanyexceptions_m_override_lock:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_toomanyexceptions_m_override_0;
+    union {
+        struct {
+            uint32_t core_1_toomanyexceptions_m_override:    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } core_1_toomanyexceptions_m_override_1;
+    union {
+        struct {
+            uint32_t backup_bus_pms_constrain_lock :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_0;
+    union {
+        struct {
+            uint32_t backup_bus_pms_constrain_uart :    2;
+            uint32_t backup_bus_pms_constrain_g0spi_1:    2;
+            uint32_t backup_bus_pms_constrain_g0spi_0:    2;
+            uint32_t backup_bus_pms_constrain_gpio :    2;
+            uint32_t backup_bus_pms_constrain_fe2  :    2;
+            uint32_t backup_bus_pms_constrain_fe   :    2;
+            uint32_t reserved12                    :    2;
+            uint32_t backup_bus_pms_constrain_rtc  :    2;
+            uint32_t backup_bus_pms_constrain_io_mux:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t backup_bus_pms_constrain_hinf :    2;
+            uint32_t reserved22                    :    2;
+            uint32_t backup_bus_pms_constrain_misc :    2;
+            uint32_t backup_bus_pms_constrain_i2c  :    2;
+            uint32_t backup_bus_pms_constrain_i2s0 :    2;
+            uint32_t backup_bus_pms_constrain_uart1:    2;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_1;
+    union {
+        struct {
+            uint32_t backup_bus_pms_constrain_bt   :    2;
+            uint32_t reserved2                     :    2;
+            uint32_t backup_bus_pms_constrain_i2c_ext0:    2;
+            uint32_t backup_bus_pms_constrain_uhci0:    2;
+            uint32_t backup_bus_pms_constrain_slchost:    2;
+            uint32_t backup_bus_pms_constrain_rmt  :    2;
+            uint32_t backup_bus_pms_constrain_pcnt :    2;
+            uint32_t backup_bus_pms_constrain_slc  :    2;
+            uint32_t backup_bus_pms_constrain_ledc :    2;
+            uint32_t backup_bus_pms_constrain_backup:    2;
+            uint32_t reserved20                    :    2;
+            uint32_t backup_bus_pms_constrain_bb   :    2;
+            uint32_t backup_bus_pms_constrain_pwm0 :    2;
+            uint32_t backup_bus_pms_constrain_timergroup:    2;
+            uint32_t backup_bus_pms_constrain_timergroup1:    2;
+            uint32_t backup_bus_pms_constrain_systimer:    2;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_2;
+    union {
+        struct {
+            uint32_t backup_bus_pms_constrain_spi_2:    2;
+            uint32_t backup_bus_pms_constrain_spi_3:    2;
+            uint32_t backup_bus_pms_constrain_apb_ctrl:    2;
+            uint32_t backup_bus_pms_constrain_i2c_ext1:    2;
+            uint32_t backup_bus_pms_constrain_sdio_host:    2;
+            uint32_t backup_bus_pms_constrain_can  :    2;
+            uint32_t backup_bus_pms_constrain_pwm1 :    2;
+            uint32_t backup_bus_pms_constrain_i2s1 :    2;
+            uint32_t backup_bus_pms_constrain_uart2:    2;
+            uint32_t reserved18                    :    2;
+            uint32_t reserved20                    :    2;
+            uint32_t backup_bus_pms_constrain_rwbt :    2;
+            uint32_t reserved24                    :    2;
+            uint32_t backup_bus_pms_constrain_wifimac:    2;
+            uint32_t backup_bus_pms_constrain_pwr  :    2;
+            uint32_t reserved30                    :    2;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_3;
+    union {
+        struct {
+            uint32_t backup_bus_pms_constrain_usb_device:    2;
+            uint32_t backup_bus_pms_constrain_usb_wrap:    2;
+            uint32_t backup_bus_pms_constrain_crypto_peri:    2;
+            uint32_t backup_bus_pms_constrain_crypto_dma:    2;
+            uint32_t backup_bus_pms_constrain_apb_adc:    2;
+            uint32_t backup_bus_pms_constrain_lcd_cam:    2;
+            uint32_t backup_bus_pms_constrain_bt_pwr:    2;
+            uint32_t backup_bus_pms_constrain_usb  :    2;
+            uint32_t backup_bus_pms_constrain_system:    2;
+            uint32_t backup_bus_pms_constrain_sensitive:    2;
+            uint32_t backup_bus_pms_constrain_interrupt:    2;
+            uint32_t backup_bus_pms_constrain_dma_copy:    2;
+            uint32_t backup_bus_pms_constrain_cache_config:    2;
+            uint32_t backup_bus_pms_constrain_ad   :    2;
+            uint32_t backup_bus_pms_constrain_dio  :    2;
+            uint32_t backup_bus_pms_constrain_world_controller:    2;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_4;
+    union {
+        struct {
+            uint32_t backup_bus_pms_constrain_rtcfast_spltaddr:    11;
+            uint32_t reserved11                    :    21;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_5;
+    union {
+        struct {
+            uint32_t backup_bus_pms_constrain_rtcfast_l:    3;
+            uint32_t backup_bus_pms_constrain_rtcfast_h:    3;
+            uint32_t reserved6                     :    26;
+        };
+        uint32_t val;
+    } backup_bus_pms_constrain_6;
+    union {
+        struct {
+            uint32_t backup_bus_pms_monitor_lock   :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_0;
+    union {
+        struct {
+            uint32_t backup_bus_pms_monitor_violate_clr:    1;
+            uint32_t backup_bus_pms_monitor_violate_en:    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_1;
+    union {
+        struct {
+            uint32_t backup_bus_pms_monitor_violate_intr:    1;
+            uint32_t backup_bus_pms_monitor_violate_status_htrans:    2;
+            uint32_t backup_bus_pms_monitor_violate_status_hsize:    3;
+            uint32_t backup_bus_pms_monitor_violate_status_hwrite:    1;
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } backup_bus_pms_monitor_2;
+    uint32_t backup_bus_pms_monitor_3;
+    union {
+        struct {
+            uint32_t edma_boundary_lock            :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_boundary_lock;
+    union {
+        struct {
+            uint32_t edma_boundary_0               :    14;
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } edma_boundary_0;
+    union {
+        struct {
+            uint32_t edma_boundary_1               :    14;
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } edma_boundary_1;
+    union {
+        struct {
+            uint32_t edma_boundary_2               :    14;
+            uint32_t reserved14                    :    18;
+        };
+        uint32_t val;
+    } edma_boundary_2;
+    union {
+        struct {
+            uint32_t edma_pms_spi2_lock            :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_spi2_lock;
+    union {
+        struct {
+            uint32_t edma_pms_spi2_attr1           :    2;
+            uint32_t edma_pms_spi2_attr2           :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_spi2;
+    union {
+        struct {
+            uint32_t edma_pms_spi3_lock            :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_spi3_lock;
+    union {
+        struct {
+            uint32_t edma_pms_spi3_attr1           :    2;
+            uint32_t edma_pms_spi3_attr2           :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_spi3;
+    union {
+        struct {
+            uint32_t edma_pms_uhci0_lock           :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_uhci0_lock;
+    union {
+        struct {
+            uint32_t edma_pms_uhci0_attr1          :    2;
+            uint32_t edma_pms_uhci0_attr2          :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_uhci0;
+    union {
+        struct {
+            uint32_t edma_pms_i2s0_lock            :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_i2s0_lock;
+    union {
+        struct {
+            uint32_t edma_pms_i2s0_attr1           :    2;
+            uint32_t edma_pms_i2s0_attr2           :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_i2s0;
+    union {
+        struct {
+            uint32_t edma_pms_i2s1_lock            :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_i2s1_lock;
+    union {
+        struct {
+            uint32_t edma_pms_i2s1_attr1           :    2;
+            uint32_t edma_pms_i2s1_attr2           :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_i2s1;
+    union {
+        struct {
+            uint32_t edma_pms_lcd_cam_lock         :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_lcd_cam_lock;
+    union {
+        struct {
+            uint32_t edma_pms_lcd_cam_attr1        :    2;
+            uint32_t edma_pms_lcd_cam_attr2        :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_lcd_cam;
+    union {
+        struct {
+            uint32_t edma_pms_aes_lock             :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_aes_lock;
+    union {
+        struct {
+            uint32_t edma_pms_aes_attr1            :    2;
+            uint32_t edma_pms_aes_attr2            :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_aes;
+    union {
+        struct {
+            uint32_t edma_pms_sha_lock             :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_sha_lock;
+    union {
+        struct {
+            uint32_t edma_pms_sha_attr1            :    2;
+            uint32_t edma_pms_sha_attr2            :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_sha;
+    union {
+        struct {
+            uint32_t edma_pms_adc_dac_lock         :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_adc_dac_lock;
+    union {
+        struct {
+            uint32_t edma_pms_adc_dac_attr1        :    2;
+            uint32_t edma_pms_adc_dac_attr2        :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_adc_dac;
+    union {
+        struct {
+            uint32_t edma_pms_rmt_lock             :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } edma_pms_rmt_lock;
+    union {
+        struct {
+            uint32_t edma_pms_rmt_attr1            :    2;
+            uint32_t edma_pms_rmt_attr2            :    2;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } edma_pms_rmt;
+    union {
+        struct {
+            uint32_t reg_clk_en                    :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t dis_rtc_cpu                   :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } rtc_pms;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t reserved_800;
+    uint32_t reserved_804;
+    uint32_t reserved_808;
+    uint32_t reserved_80c;
+    uint32_t reserved_810;
+    uint32_t reserved_814;
+    uint32_t reserved_818;
+    uint32_t reserved_81c;
+    uint32_t reserved_820;
+    uint32_t reserved_824;
+    uint32_t reserved_828;
+    uint32_t reserved_82c;
+    uint32_t reserved_830;
+    uint32_t reserved_834;
+    uint32_t reserved_838;
+    uint32_t reserved_83c;
+    uint32_t reserved_840;
+    uint32_t reserved_844;
+    uint32_t reserved_848;
+    uint32_t reserved_84c;
+    uint32_t reserved_850;
+    uint32_t reserved_854;
+    uint32_t reserved_858;
+    uint32_t reserved_85c;
+    uint32_t reserved_860;
+    uint32_t reserved_864;
+    uint32_t reserved_868;
+    uint32_t reserved_86c;
+    uint32_t reserved_870;
+    uint32_t reserved_874;
+    uint32_t reserved_878;
+    uint32_t reserved_87c;
+    uint32_t reserved_880;
+    uint32_t reserved_884;
+    uint32_t reserved_888;
+    uint32_t reserved_88c;
+    uint32_t reserved_890;
+    uint32_t reserved_894;
+    uint32_t reserved_898;
+    uint32_t reserved_89c;
+    uint32_t reserved_8a0;
+    uint32_t reserved_8a4;
+    uint32_t reserved_8a8;
+    uint32_t reserved_8ac;
+    uint32_t reserved_8b0;
+    uint32_t reserved_8b4;
+    uint32_t reserved_8b8;
+    uint32_t reserved_8bc;
+    uint32_t reserved_8c0;
+    uint32_t reserved_8c4;
+    uint32_t reserved_8c8;
+    uint32_t reserved_8cc;
+    uint32_t reserved_8d0;
+    uint32_t reserved_8d4;
+    uint32_t reserved_8d8;
+    uint32_t reserved_8dc;
+    uint32_t reserved_8e0;
+    uint32_t reserved_8e4;
+    uint32_t reserved_8e8;
+    uint32_t reserved_8ec;
+    uint32_t reserved_8f0;
+    uint32_t reserved_8f4;
+    uint32_t reserved_8f8;
+    uint32_t reserved_8fc;
+    uint32_t reserved_900;
+    uint32_t reserved_904;
+    uint32_t reserved_908;
+    uint32_t reserved_90c;
+    uint32_t reserved_910;
+    uint32_t reserved_914;
+    uint32_t reserved_918;
+    uint32_t reserved_91c;
+    uint32_t reserved_920;
+    uint32_t reserved_924;
+    uint32_t reserved_928;
+    uint32_t reserved_92c;
+    uint32_t reserved_930;
+    uint32_t reserved_934;
+    uint32_t reserved_938;
+    uint32_t reserved_93c;
+    uint32_t reserved_940;
+    uint32_t reserved_944;
+    uint32_t reserved_948;
+    uint32_t reserved_94c;
+    uint32_t reserved_950;
+    uint32_t reserved_954;
+    uint32_t reserved_958;
+    uint32_t reserved_95c;
+    uint32_t reserved_960;
+    uint32_t reserved_964;
+    uint32_t reserved_968;
+    uint32_t reserved_96c;
+    uint32_t reserved_970;
+    uint32_t reserved_974;
+    uint32_t reserved_978;
+    uint32_t reserved_97c;
+    uint32_t reserved_980;
+    uint32_t reserved_984;
+    uint32_t reserved_988;
+    uint32_t reserved_98c;
+    uint32_t reserved_990;
+    uint32_t reserved_994;
+    uint32_t reserved_998;
+    uint32_t reserved_99c;
+    uint32_t reserved_9a0;
+    uint32_t reserved_9a4;
+    uint32_t reserved_9a8;
+    uint32_t reserved_9ac;
+    uint32_t reserved_9b0;
+    uint32_t reserved_9b4;
+    uint32_t reserved_9b8;
+    uint32_t reserved_9bc;
+    uint32_t reserved_9c0;
+    uint32_t reserved_9c4;
+    uint32_t reserved_9c8;
+    uint32_t reserved_9cc;
+    uint32_t reserved_9d0;
+    uint32_t reserved_9d4;
+    uint32_t reserved_9d8;
+    uint32_t reserved_9dc;
+    uint32_t reserved_9e0;
+    uint32_t reserved_9e4;
+    uint32_t reserved_9e8;
+    uint32_t reserved_9ec;
+    uint32_t reserved_9f0;
+    uint32_t reserved_9f4;
+    uint32_t reserved_9f8;
+    uint32_t reserved_9fc;
+    uint32_t reserved_a00;
+    uint32_t reserved_a04;
+    uint32_t reserved_a08;
+    uint32_t reserved_a0c;
+    uint32_t reserved_a10;
+    uint32_t reserved_a14;
+    uint32_t reserved_a18;
+    uint32_t reserved_a1c;
+    uint32_t reserved_a20;
+    uint32_t reserved_a24;
+    uint32_t reserved_a28;
+    uint32_t reserved_a2c;
+    uint32_t reserved_a30;
+    uint32_t reserved_a34;
+    uint32_t reserved_a38;
+    uint32_t reserved_a3c;
+    uint32_t reserved_a40;
+    uint32_t reserved_a44;
+    uint32_t reserved_a48;
+    uint32_t reserved_a4c;
+    uint32_t reserved_a50;
+    uint32_t reserved_a54;
+    uint32_t reserved_a58;
+    uint32_t reserved_a5c;
+    uint32_t reserved_a60;
+    uint32_t reserved_a64;
+    uint32_t reserved_a68;
+    uint32_t reserved_a6c;
+    uint32_t reserved_a70;
+    uint32_t reserved_a74;
+    uint32_t reserved_a78;
+    uint32_t reserved_a7c;
+    uint32_t reserved_a80;
+    uint32_t reserved_a84;
+    uint32_t reserved_a88;
+    uint32_t reserved_a8c;
+    uint32_t reserved_a90;
+    uint32_t reserved_a94;
+    uint32_t reserved_a98;
+    uint32_t reserved_a9c;
+    uint32_t reserved_aa0;
+    uint32_t reserved_aa4;
+    uint32_t reserved_aa8;
+    uint32_t reserved_aac;
+    uint32_t reserved_ab0;
+    uint32_t reserved_ab4;
+    uint32_t reserved_ab8;
+    uint32_t reserved_abc;
+    uint32_t reserved_ac0;
+    uint32_t reserved_ac4;
+    uint32_t reserved_ac8;
+    uint32_t reserved_acc;
+    uint32_t reserved_ad0;
+    uint32_t reserved_ad4;
+    uint32_t reserved_ad8;
+    uint32_t reserved_adc;
+    uint32_t reserved_ae0;
+    uint32_t reserved_ae4;
+    uint32_t reserved_ae8;
+    uint32_t reserved_aec;
+    uint32_t reserved_af0;
+    uint32_t reserved_af4;
+    uint32_t reserved_af8;
+    uint32_t reserved_afc;
+    uint32_t reserved_b00;
+    uint32_t reserved_b04;
+    uint32_t reserved_b08;
+    uint32_t reserved_b0c;
+    uint32_t reserved_b10;
+    uint32_t reserved_b14;
+    uint32_t reserved_b18;
+    uint32_t reserved_b1c;
+    uint32_t reserved_b20;
+    uint32_t reserved_b24;
+    uint32_t reserved_b28;
+    uint32_t reserved_b2c;
+    uint32_t reserved_b30;
+    uint32_t reserved_b34;
+    uint32_t reserved_b38;
+    uint32_t reserved_b3c;
+    uint32_t reserved_b40;
+    uint32_t reserved_b44;
+    uint32_t reserved_b48;
+    uint32_t reserved_b4c;
+    uint32_t reserved_b50;
+    uint32_t reserved_b54;
+    uint32_t reserved_b58;
+    uint32_t reserved_b5c;
+    uint32_t reserved_b60;
+    uint32_t reserved_b64;
+    uint32_t reserved_b68;
+    uint32_t reserved_b6c;
+    uint32_t reserved_b70;
+    uint32_t reserved_b74;
+    uint32_t reserved_b78;
+    uint32_t reserved_b7c;
+    uint32_t reserved_b80;
+    uint32_t reserved_b84;
+    uint32_t reserved_b88;
+    uint32_t reserved_b8c;
+    uint32_t reserved_b90;
+    uint32_t reserved_b94;
+    uint32_t reserved_b98;
+    uint32_t reserved_b9c;
+    uint32_t reserved_ba0;
+    uint32_t reserved_ba4;
+    uint32_t reserved_ba8;
+    uint32_t reserved_bac;
+    uint32_t reserved_bb0;
+    uint32_t reserved_bb4;
+    uint32_t reserved_bb8;
+    uint32_t reserved_bbc;
+    uint32_t reserved_bc0;
+    uint32_t reserved_bc4;
+    uint32_t reserved_bc8;
+    uint32_t reserved_bcc;
+    uint32_t reserved_bd0;
+    uint32_t reserved_bd4;
+    uint32_t reserved_bd8;
+    uint32_t reserved_bdc;
+    uint32_t reserved_be0;
+    uint32_t reserved_be4;
+    uint32_t reserved_be8;
+    uint32_t reserved_bec;
+    uint32_t reserved_bf0;
+    uint32_t reserved_bf4;
+    uint32_t reserved_bf8;
+    uint32_t reserved_bfc;
+    uint32_t reserved_c00;
+    uint32_t reserved_c04;
+    uint32_t reserved_c08;
+    uint32_t reserved_c0c;
+    uint32_t reserved_c10;
+    uint32_t reserved_c14;
+    uint32_t reserved_c18;
+    uint32_t reserved_c1c;
+    uint32_t reserved_c20;
+    uint32_t reserved_c24;
+    uint32_t reserved_c28;
+    uint32_t reserved_c2c;
+    uint32_t reserved_c30;
+    uint32_t reserved_c34;
+    uint32_t reserved_c38;
+    uint32_t reserved_c3c;
+    uint32_t reserved_c40;
+    uint32_t reserved_c44;
+    uint32_t reserved_c48;
+    uint32_t reserved_c4c;
+    uint32_t reserved_c50;
+    uint32_t reserved_c54;
+    uint32_t reserved_c58;
+    uint32_t reserved_c5c;
+    uint32_t reserved_c60;
+    uint32_t reserved_c64;
+    uint32_t reserved_c68;
+    uint32_t reserved_c6c;
+    uint32_t reserved_c70;
+    uint32_t reserved_c74;
+    uint32_t reserved_c78;
+    uint32_t reserved_c7c;
+    uint32_t reserved_c80;
+    uint32_t reserved_c84;
+    uint32_t reserved_c88;
+    uint32_t reserved_c8c;
+    uint32_t reserved_c90;
+    uint32_t reserved_c94;
+    uint32_t reserved_c98;
+    uint32_t reserved_c9c;
+    uint32_t reserved_ca0;
+    uint32_t reserved_ca4;
+    uint32_t reserved_ca8;
+    uint32_t reserved_cac;
+    uint32_t reserved_cb0;
+    uint32_t reserved_cb4;
+    uint32_t reserved_cb8;
+    uint32_t reserved_cbc;
+    uint32_t reserved_cc0;
+    uint32_t reserved_cc4;
+    uint32_t reserved_cc8;
+    uint32_t reserved_ccc;
+    uint32_t reserved_cd0;
+    uint32_t reserved_cd4;
+    uint32_t reserved_cd8;
+    uint32_t reserved_cdc;
+    uint32_t reserved_ce0;
+    uint32_t reserved_ce4;
+    uint32_t reserved_ce8;
+    uint32_t reserved_cec;
+    uint32_t reserved_cf0;
+    uint32_t reserved_cf4;
+    uint32_t reserved_cf8;
+    uint32_t reserved_cfc;
+    uint32_t reserved_d00;
+    uint32_t reserved_d04;
+    uint32_t reserved_d08;
+    uint32_t reserved_d0c;
+    uint32_t reserved_d10;
+    uint32_t reserved_d14;
+    uint32_t reserved_d18;
+    uint32_t reserved_d1c;
+    uint32_t reserved_d20;
+    uint32_t reserved_d24;
+    uint32_t reserved_d28;
+    uint32_t reserved_d2c;
+    uint32_t reserved_d30;
+    uint32_t reserved_d34;
+    uint32_t reserved_d38;
+    uint32_t reserved_d3c;
+    uint32_t reserved_d40;
+    uint32_t reserved_d44;
+    uint32_t reserved_d48;
+    uint32_t reserved_d4c;
+    uint32_t reserved_d50;
+    uint32_t reserved_d54;
+    uint32_t reserved_d58;
+    uint32_t reserved_d5c;
+    uint32_t reserved_d60;
+    uint32_t reserved_d64;
+    uint32_t reserved_d68;
+    uint32_t reserved_d6c;
+    uint32_t reserved_d70;
+    uint32_t reserved_d74;
+    uint32_t reserved_d78;
+    uint32_t reserved_d7c;
+    uint32_t reserved_d80;
+    uint32_t reserved_d84;
+    uint32_t reserved_d88;
+    uint32_t reserved_d8c;
+    uint32_t reserved_d90;
+    uint32_t reserved_d94;
+    uint32_t reserved_d98;
+    uint32_t reserved_d9c;
+    uint32_t reserved_da0;
+    uint32_t reserved_da4;
+    uint32_t reserved_da8;
+    uint32_t reserved_dac;
+    uint32_t reserved_db0;
+    uint32_t reserved_db4;
+    uint32_t reserved_db8;
+    uint32_t reserved_dbc;
+    uint32_t reserved_dc0;
+    uint32_t reserved_dc4;
+    uint32_t reserved_dc8;
+    uint32_t reserved_dcc;
+    uint32_t reserved_dd0;
+    uint32_t reserved_dd4;
+    uint32_t reserved_dd8;
+    uint32_t reserved_ddc;
+    uint32_t reserved_de0;
+    uint32_t reserved_de4;
+    uint32_t reserved_de8;
+    uint32_t reserved_dec;
+    uint32_t reserved_df0;
+    uint32_t reserved_df4;
+    uint32_t reserved_df8;
+    uint32_t reserved_dfc;
+    uint32_t reserved_e00;
+    uint32_t reserved_e04;
+    uint32_t reserved_e08;
+    uint32_t reserved_e0c;
+    uint32_t reserved_e10;
+    uint32_t reserved_e14;
+    uint32_t reserved_e18;
+    uint32_t reserved_e1c;
+    uint32_t reserved_e20;
+    uint32_t reserved_e24;
+    uint32_t reserved_e28;
+    uint32_t reserved_e2c;
+    uint32_t reserved_e30;
+    uint32_t reserved_e34;
+    uint32_t reserved_e38;
+    uint32_t reserved_e3c;
+    uint32_t reserved_e40;
+    uint32_t reserved_e44;
+    uint32_t reserved_e48;
+    uint32_t reserved_e4c;
+    uint32_t reserved_e50;
+    uint32_t reserved_e54;
+    uint32_t reserved_e58;
+    uint32_t reserved_e5c;
+    uint32_t reserved_e60;
+    uint32_t reserved_e64;
+    uint32_t reserved_e68;
+    uint32_t reserved_e6c;
+    uint32_t reserved_e70;
+    uint32_t reserved_e74;
+    uint32_t reserved_e78;
+    uint32_t reserved_e7c;
+    uint32_t reserved_e80;
+    uint32_t reserved_e84;
+    uint32_t reserved_e88;
+    uint32_t reserved_e8c;
+    uint32_t reserved_e90;
+    uint32_t reserved_e94;
+    uint32_t reserved_e98;
+    uint32_t reserved_e9c;
+    uint32_t reserved_ea0;
+    uint32_t reserved_ea4;
+    uint32_t reserved_ea8;
+    uint32_t reserved_eac;
+    uint32_t reserved_eb0;
+    uint32_t reserved_eb4;
+    uint32_t reserved_eb8;
+    uint32_t reserved_ebc;
+    uint32_t reserved_ec0;
+    uint32_t reserved_ec4;
+    uint32_t reserved_ec8;
+    uint32_t reserved_ecc;
+    uint32_t reserved_ed0;
+    uint32_t reserved_ed4;
+    uint32_t reserved_ed8;
+    uint32_t reserved_edc;
+    uint32_t reserved_ee0;
+    uint32_t reserved_ee4;
+    uint32_t reserved_ee8;
+    uint32_t reserved_eec;
+    uint32_t reserved_ef0;
+    uint32_t reserved_ef4;
+    uint32_t reserved_ef8;
+    uint32_t reserved_efc;
+    uint32_t reserved_f00;
+    uint32_t reserved_f04;
+    uint32_t reserved_f08;
+    uint32_t reserved_f0c;
+    uint32_t reserved_f10;
+    uint32_t reserved_f14;
+    uint32_t reserved_f18;
+    uint32_t reserved_f1c;
+    uint32_t reserved_f20;
+    uint32_t reserved_f24;
+    uint32_t reserved_f28;
+    uint32_t reserved_f2c;
+    uint32_t reserved_f30;
+    uint32_t reserved_f34;
+    uint32_t reserved_f38;
+    uint32_t reserved_f3c;
+    uint32_t reserved_f40;
+    uint32_t reserved_f44;
+    uint32_t reserved_f48;
+    uint32_t reserved_f4c;
+    uint32_t reserved_f50;
+    uint32_t reserved_f54;
+    uint32_t reserved_f58;
+    uint32_t reserved_f5c;
+    uint32_t reserved_f60;
+    uint32_t reserved_f64;
+    uint32_t reserved_f68;
+    uint32_t reserved_f6c;
+    uint32_t reserved_f70;
+    uint32_t reserved_f74;
+    uint32_t reserved_f78;
+    uint32_t reserved_f7c;
+    uint32_t reserved_f80;
+    uint32_t reserved_f84;
+    uint32_t reserved_f88;
+    uint32_t reserved_f8c;
+    uint32_t reserved_f90;
+    uint32_t reserved_f94;
+    uint32_t reserved_f98;
+    uint32_t reserved_f9c;
+    uint32_t reserved_fa0;
+    uint32_t reserved_fa4;
+    uint32_t reserved_fa8;
+    uint32_t reserved_fac;
+    uint32_t reserved_fb0;
+    uint32_t reserved_fb4;
+    uint32_t reserved_fb8;
+    uint32_t reserved_fbc;
+    uint32_t reserved_fc0;
+    uint32_t reserved_fc4;
+    uint32_t reserved_fc8;
+    uint32_t reserved_fcc;
+    uint32_t reserved_fd0;
+    uint32_t reserved_fd4;
+    uint32_t reserved_fd8;
+    uint32_t reserved_fdc;
+    uint32_t reserved_fe0;
+    uint32_t reserved_fe4;
+    uint32_t reserved_fe8;
+    uint32_t reserved_fec;
+    uint32_t reserved_ff0;
+    uint32_t reserved_ff4;
+    uint32_t reserved_ff8;
+    union {
+        struct {
+            uint32_t sensitive_reg_date            :    28;
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } reg_date;
+} sensitive_dev_t;
+extern sensitive_dev_t SENSITIVE;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_STRUCT_H_ */
diff --git a/components/soc/esp32s3/register/soc/spi_mem_reg.h b/components/soc/esp32s3/register/soc/spi_mem_reg.h
new file mode 100644
index 00000000000..16a8ec5f9c5
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/spi_mem_reg.h
@@ -0,0 +1,2233 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_MEM_REG_H_
+#define _SOC_SPI_MEM_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0)
+/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done. 1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_READ    (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the bit is set. The
+bit will be cleared once the operation done. 1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_WREN    (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when the bit is set. The
+ bit will be cleared once the operation done. 1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_WRDI    (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will b
+e cleared once the operation done. 1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_RDID    (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered when the bit is
+ set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_RDSR    (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will be triggered when t
+he bit is set. The bit will be cleared once the operation done.1: enable 0: disa
+ble. .*/
+#define SPI_MEM_FLASH_WRSR    (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~64 bytes data to be programmed). Page program operat
+ion  will be triggered when the bit is set. The bit will be cleared once the ope
+ration done .1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_PP    (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered when the bit
+is set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_SE    (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered when the bit
+ is set. The bit will be cleared once the operation done.1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_BE    (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when the bit is set. T
+he bit will be cleared once the operation done.1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_CE    (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered when the bit is set
+. The bit will be cleared once the operation done.1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_DP    (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down
+state or high performance mode and obtains the devices ID. The bit will be clear
+ed once the operation done.1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_RES    (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared once the operat
+ion done.1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_HPM    (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when the bit is set.
+ The bit will be cleared once the operation done.1: enable 0: disable. .*/
+#define SPI_MEM_USR    (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode, it is set to indicate that program/erase operation will be trigger
+ed. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the o
+peration done.1: enable 0: disable. .*/
+#define SPI_MEM_FLASH_PE    (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode, it is the memory address. other then the bit0-bit23 is the memory
+address, the bit24-bit31 are the byte length of a transfer..*/
+#define SPI_MEM_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8)
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-
+mode). 1: enable 0: disable. .*/
+#define SPI_MEM_FREAD_QIO    (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-
+mode). 1: enable 0: disable. .*/
+#define SPI_MEM_FREAD_DIO    (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Two bytes data will be written to status register when it is set. 1: enable 0: d
+isable. .*/
+#define SPI_MEM_WRSR_2B    (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low. .*/
+#define SPI_MEM_WP_REG    (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enabl
+e 0: disable. .*/
+#define SPI_MEM_FREAD_QUAD    (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low.*/
+#define SPI_MEM_D_POL    (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low.*/
+#define SPI_MEM_Q_POL    (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with
+spi_mem_flash_res bit. 1: enable 0: disable. .*/
+#define SPI_MEM_RESANDRES    (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable
+. .*/
+#define SPI_MEM_FREAD_DUAL    (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_
+QUAD or SPI_MEM_FREAD_DUAL is set..*/
+#define SPI_MEM_FASTRD_MODE    (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+e.*/
+#define SPI_MEM_TX_CRC_EN    (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1,  initialize crc32 module before writing encrypted data to flash. Active
+e low..*/
+#define SPI_MEM_FCS_CRC_EN    (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase..*/
+#define SPI_MEM_FCMD_OCT    (BIT(9))
+#define SPI_MEM_FCMD_OCT_M  (BIT(9))
+#define SPI_MEM_FCMD_OCT_V  0x1
+#define SPI_MEM_FCMD_OCT_S  9
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase..*/
+#define SPI_MEM_FCMD_QUAD    (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase..*/
+#define SPI_MEM_FCMD_DUAL    (BIT(7))
+#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_V  0x1
+#define SPI_MEM_FCMD_DUAL_S  7
+/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase..*/
+#define SPI_MEM_FADDR_OCT    (BIT(6))
+#define SPI_MEM_FADDR_OCT_M  (BIT(6))
+#define SPI_MEM_FADDR_OCT_V  0x1
+#define SPI_MEM_FADDR_OCT_S  6
+/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase..*/
+#define SPI_MEM_FDIN_OCT    (BIT(5))
+#define SPI_MEM_FDIN_OCT_M  (BIT(5))
+#define SPI_MEM_FDIN_OCT_V  0x1
+#define SPI_MEM_FDIN_OCT_S  5
+/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase..*/
+#define SPI_MEM_FDOUT_OCT    (BIT(4))
+#define SPI_MEM_FDOUT_OCT_M  (BIT(4))
+#define SPI_MEM_FDOUT_OCT_V  0x1
+#define SPI_MEM_FDOUT_OCT_S  4
+/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller..*/
+#define SPI_MEM_FDUMMY_OUT    (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_M  (BIT(3))
+#define SPI_MEM_FDUMMY_OUT_V  0x1
+#define SPI_MEM_FDUMMY_OUT_S  3
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC)
+/* SPI_MEM_RXFIFO_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts
+..*/
+#define SPI_MEM_RXFIFO_RST    (BIT(30))
+#define SPI_MEM_RXFIFO_RST_M  (BIT(30))
+#define SPI_MEM_RXFIFO_RST_V  0x1
+#define SPI_MEM_RXFIFO_RST_S  30
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */
+/*description: After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 4 or * 256) SPI_CLK cycles..*/
+#define SPI_MEM_CS_HOLD_DLY_RES    0x000003FF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0x3FF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS ina
+ctive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delaye
+d two cycles after SPI_CS inactive 3: SPI_CLK is always on..*/
+#define SPI_MEM_CLK_MODE    0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10)
+/* SPI_MEM_SYNC_RESET : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The FSM will be reset..*/
+#define SPI_MEM_SYNC_RESET    (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core
+ clock cycles..*/
+#define SPI_MEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_CS_HOLD_DELAY_M  ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse
+s flash..*/
+#define SPI_MEM_ECC_16TO18_BYTE_EN    (BIT(14))
+#define SPI_MEM_ECC_16TO18_BYTE_EN_M  (BIT(14))
+#define SPI_MEM_ECC_16TO18_BYTE_EN_V  0x1
+#define SPI_MEM_ECC_16TO18_BYTE_EN_S  14
+/* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when acce
+sses flash..*/
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER    (BIT(13))
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M  (BIT(13))
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S  13
+/* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC
+mode when accessed flash..*/
+#define SPI_MEM_ECC_CS_HOLD_TIME    0x00000007
+#define SPI_MEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S))
+#define SPI_MEM_ECC_CS_HOLD_TIME_V  0x7
+#define SPI_MEM_ECC_CS_HOLD_TIME_S  10
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */
+/*description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), wh
+ich is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_ME
+M_CS_HOLD bit..*/
+#define SPI_MEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_CS_HOLD_TIME_S  5
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */
+/*description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits
+are combined with SPI_MEM_CS_SETUP bit..*/
+#define SPI_MEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x14)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK
+ = f_MSPI_CORE_CLK..*/
+#define SPI_MEM_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLK
+CNT_N+1).*/
+#define SPI_MEM_CLKCNT_N    0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1)..*/
+#define SPI_MEM_CLKCNT_H    0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: It must equal to the value of SPI_MEM_CLKCNT_N. .*/
+#define SPI_MEM_CLKCNT_L    0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x18)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: Set this bit to enable enable the CMD phase of an operation..*/
+#define SPI_MEM_USR_COMMAND    (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable enable the ADDR phase of an operation..*/
+#define SPI_MEM_USR_ADDR    (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable enable the DUMMY phase of an operation..*/
+#define SPI_MEM_USR_DUMMY    (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable enable the DIN phase of a read-data operation..*/
+#define SPI_MEM_USR_MISO    (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the DOUT phase of an write-data operation..*/
+#define SPI_MEM_USR_MOSI    (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable..*/
+#define SPI_MEM_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG
+. 1: enable 0: disable. .*/
+#define SPI_MEM_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG.
+ 1: enable 0: disable. .*/
+#define SPI_MEM_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write ope
+ration..*/
+#define SPI_MEM_FWRITE_QIO    (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation..*/
+#define SPI_MEM_FWRITE_DIO    (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to enable 4-bm in DOUT phase in SPI1 write operation..*/
+#define SPI_MEM_FWRITE_QUAD    (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable 2-bm in DOUT phase in SPI1 write operation..*/
+#define SPI_MEM_FWRITE_DUAL    (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mo
+de 0~3 of SPI_CLK. .*/
+#define SPI_MEM_CK_OUT_EDGE    (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/
+#define SPI_MEM_CS_SETUP    (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/
+#define SPI_MEM_CS_HOLD    (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x1C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of ADDR phase. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */
+/*description: The SPI_CLK cycle length minus 1 of DUMMY phase..*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x20)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of CMD phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of user defined(USR) command..*/
+#define SPI_MEM_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x24)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of DOUT phase. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MOSI_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x28)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: The length in bits of DIN phase. The register value shall be (bit_num-1)..*/
+#define SPI_MEM_USR_MISO_DBITLEN    0x000003FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x3FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x2C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with SPI_MEM_FASTRD_MODE b
+it..*/
+#define SPI_MEM_WB_MODE    0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit..*/
+#define SPI_MEM_STATUS    0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_EXT_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x30)
+/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The register are the higher 32bits in the 64 bits address mode..*/
+#define SPI_MEM_EXT_ADDR    0xFFFFFFFF
+#define SPI_MEM_EXT_ADDR_M  ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S))
+#define SPI_MEM_EXT_ADDR_V  0xFFFFFFFF
+#define SPI_MEM_EXT_ADDR_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x34)
+/* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to enable auto PER function. Hardware will sent out PER command if
+PES command is sent..*/
+#define SPI_MEM_AUTO_PER    (BIT(11))
+#define SPI_MEM_AUTO_PER_M  (BIT(11))
+#define SPI_MEM_AUTO_PER_V  0x1
+#define SPI_MEM_AUTO_PER_S  11
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: SPI_CS line keep low when the bit is set..*/
+#define SPI_MEM_CS_KEEP_ACTIVE    (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is i
+dle..*/
+#define SPI_MEM_CK_IDLE_EDGE    (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Ext_RAM is connected to SPI SUBPIN bus..*/
+#define SPI_MEM_SSUB_PIN    (BIT(8))
+#define SPI_MEM_SSUB_PIN_M  (BIT(8))
+#define SPI_MEM_SSUB_PIN_V  0x1
+#define SPI_MEM_SSUB_PIN_S  8
+/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Flash is connected to SPI SUBPIN bus..*/
+#define SPI_MEM_FSUB_PIN    (BIT(7))
+#define SPI_MEM_FSUB_PIN_M  (BIT(7))
+#define SPI_MEM_FSUB_PIN_V  0x1
+#define SPI_MEM_FSUB_PIN_S  7
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM)
+ connected to SPI_CS1 is in low level when SPI1 transfer starts..*/
+#define SPI_MEM_CS1_DIS    (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) co
+nnected to SPI_CS is in low level when SPI1 transfer starts..*/
+#define SPI_MEM_CS0_DIS    (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x38)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: For SPI1, the value of crc32..*/
+#define SPI_MEM_TX_CRC_DATA    0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3C)
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phas
+e..*/
+#define SPI_MEM_FADDR_QUAD    (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phas
+e..*/
+#define SPI_MEM_FDOUT_QUAD    (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase
+..*/
+#define SPI_MEM_FDIN_QUAD    (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phas
+e..*/
+#define SPI_MEM_FADDR_DUAL    (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phas
+e..*/
+#define SPI_MEM_FDOUT_DUAL    (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase
+..*/
+#define SPI_MEM_FDIN_DUAL    (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardwa
+re read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_M
+EM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits..*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD    (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_
+USR_ADDR_BITLEN should be 31..*/
+#define SPI_MEM_CACHE_USR_CMD_4BYTE    (BIT(1))
+#define SPI_MEM_CACHE_USR_CMD_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_CMD_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_CMD_4BYTE_S  1
+/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable Cache's access and SPI0's transfer..*/
+#define SPI_MEM_CACHE_REQ_EN    (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_V  0x1
+#define SPI_MEM_CACHE_REQ_EN_S  0
+
+#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x40)
+/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */
+/*description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase i
+n write data transfer..*/
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
+/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer..*/
+#define SPI_MEM_SRAM_OCT    (BIT(21))
+#define SPI_MEM_SRAM_OCT_M  (BIT(21))
+#define SPI_MEM_SRAM_OCT_V  0x1
+#define SPI_MEM_SRAM_OCT_S  21
+/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALU
+E. 0: The value is 0x3..*/
+#define SPI_MEM_CACHE_SRAM_USR_WCMD    (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
+/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */
+/*description: When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The regis
+ter value shall be (bit_num-1)..*/
+#define SPI_MEM_SRAM_ADDR_BITLEN    0x0000003F
+#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
+#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
+/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */
+/*description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase i
+n read data transfer..*/
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
+/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE
+. 0: The value is 0x2..*/
+#define SPI_MEM_CACHE_SRAM_USR_RCMD    (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
+/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operat
+ions..*/
+#define SPI_MEM_USR_RD_SRAM_DUMMY    (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
+/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write opera
+tions..*/
+#define SPI_MEM_USR_WR_SRAM_DUMMY    (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
+/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer..*/
+#define SPI_MEM_USR_SRAM_QIO    (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_V  0x1
+#define SPI_MEM_USR_SRAM_QIO_S  2
+/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer..*/
+#define SPI_MEM_USR_SRAM_DIO    (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_V  0x1
+#define SPI_MEM_USR_SRAM_DIO_S  1
+/* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_
+MEM_SRAM_ADDR_BITLEN should be 31..*/
+#define SPI_MEM_CACHE_USR_SCMD_4BYTE    (BIT(0))
+#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M  (BIT(0))
+#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S  0
+
+#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x44)
+/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is
+ output by the SPI0 controller..*/
+#define SPI_MEM_SDUMMY_OUT    (BIT(22))
+#define SPI_MEM_SDUMMY_OUT_M  (BIT(22))
+#define SPI_MEM_SDUMMY_OUT_V  0x1
+#define SPI_MEM_SDUMMY_OUT_S  22
+/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase..*/
+#define SPI_MEM_SCMD_OCT    (BIT(21))
+#define SPI_MEM_SCMD_OCT_M  (BIT(21))
+#define SPI_MEM_SCMD_OCT_V  0x1
+#define SPI_MEM_SCMD_OCT_S  21
+/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase..*/
+#define SPI_MEM_SADDR_OCT    (BIT(20))
+#define SPI_MEM_SADDR_OCT_M  (BIT(20))
+#define SPI_MEM_SADDR_OCT_V  0x1
+#define SPI_MEM_SADDR_OCT_S  20
+/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase..*/
+#define SPI_MEM_SDOUT_OCT    (BIT(19))
+#define SPI_MEM_SDOUT_OCT_M  (BIT(19))
+#define SPI_MEM_SDOUT_OCT_V  0x1
+#define SPI_MEM_SDOUT_OCT_S  19
+/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase..*/
+#define SPI_MEM_SDIN_OCT    (BIT(18))
+#define SPI_MEM_SDIN_OCT_M  (BIT(18))
+#define SPI_MEM_SDIN_OCT_V  0x1
+#define SPI_MEM_SDIN_OCT_S  18
+/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase..*/
+#define SPI_MEM_SCMD_QUAD    (BIT(17))
+#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
+#define SPI_MEM_SCMD_QUAD_V  0x1
+#define SPI_MEM_SCMD_QUAD_S  17
+/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase..*/
+#define SPI_MEM_SADDR_QUAD    (BIT(16))
+#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
+#define SPI_MEM_SADDR_QUAD_V  0x1
+#define SPI_MEM_SADDR_QUAD_S  16
+/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase..*/
+#define SPI_MEM_SDOUT_QUAD    (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_V  0x1
+#define SPI_MEM_SDOUT_QUAD_S  15
+/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase..*/
+#define SPI_MEM_SDIN_QUAD    (BIT(14))
+#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
+#define SPI_MEM_SDIN_QUAD_V  0x1
+#define SPI_MEM_SDIN_QUAD_S  14
+/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase..*/
+#define SPI_MEM_SCMD_DUAL    (BIT(13))
+#define SPI_MEM_SCMD_DUAL_M  (BIT(13))
+#define SPI_MEM_SCMD_DUAL_V  0x1
+#define SPI_MEM_SCMD_DUAL_S  13
+/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase..*/
+#define SPI_MEM_SADDR_DUAL    (BIT(12))
+#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
+#define SPI_MEM_SADDR_DUAL_V  0x1
+#define SPI_MEM_SADDR_DUAL_S  12
+/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase..*/
+#define SPI_MEM_SDOUT_DUAL    (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_V  0x1
+#define SPI_MEM_SDOUT_DUAL_S  11
+/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase..*/
+#define SPI_MEM_SDIN_DUAL    (BIT(10))
+#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
+#define SPI_MEM_SDIN_DUAL_V  0x1
+#define SPI_MEM_SDIN_DUAL_S  10
+/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
+/*description: Mode bits when SPI0 accesses to Ext_RAM..*/
+#define SPI_MEM_SWB_MODE    0x000000FF
+#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
+#define SPI_MEM_SWB_MODE_V  0xFF
+#define SPI_MEM_SWB_MODE_S  2
+/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: SPI_CLK mode bits  when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inac
+tive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two
+ cycles after CS inactive 3: SPI_CLK is always on..*/
+#define SPI_MEM_SCLK_MODE    0x00000003
+#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
+#define SPI_MEM_SCLK_MODE_V  0x3
+#define SPI_MEM_SCLK_MODE_S  0
+
+#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x48)
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register
+value shall be (bit_num-1)..*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN    0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: When SPI0 reads Ext_RAM, it is the command value of CMD phase..*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE    0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x4C)
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register va
+lue shall be (bit_num-1)..*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN    0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: When SPI0 writes Ext_RAM, it is the command value of CMD phase..*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE    0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x50)
+/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MS
+PI_CORE_CLK..*/
+#define SPI_MEM_SCLK_EQU_SYSCLK    (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
+/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1).*/
+#define SPI_MEM_SCLKCNT_N    0x000000FF
+#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
+#define SPI_MEM_SCLKCNT_N_V  0xFF
+#define SPI_MEM_SCLKCNT_N_S  16
+/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1)..*/
+#define SPI_MEM_SCLKCNT_H    0x000000FF
+#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
+#define SPI_MEM_SCLKCNT_H_V  0xFF
+#define SPI_MEM_SCLKCNT_H_S  8
+/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: It must equal to the value of SPI_MEM_SCLKCNT_N. .*/
+#define SPI_MEM_SCLKCNT_L    0x000000FF
+#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
+#define SPI_MEM_SCLKCNT_L_V  0xFF
+#define SPI_MEM_SCLKCNT_L_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x54)
+/* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP
+), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DI
+N), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE)..*/
+#define SPI_MEM_ST    0x00000007
+#define SPI_MEM_ST_M  ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S))
+#define SPI_MEM_ST_V  0x7
+#define SPI_MEM_ST_S  0
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x58)
+/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF0    0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x5C)
+/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF1    0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x60)
+/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF2    0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x64)
+/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF3    0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x68)
+/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF4    0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x6C)
+/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF5    0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x70)
+/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF6    0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x74)
+/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF7    0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x78)
+/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF8    0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x7C)
+/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF9    0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x80)
+/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF10    0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x84)
+/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF11    0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x88)
+/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF12    0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x8C)
+/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF13    0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x90)
+/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF14    0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x94)
+/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer.*/
+#define SPI_MEM_BUF15    0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x98)
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */
+/*description: The dummy cycle length when wait flash idle(RDSR)..*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN    0x0000003F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0x3F
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
+/*description: The command value of auto wait flash idle transfer(RDSR)..*/
+#define SPI_MEM_WAITI_CMD    0x000000FF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFF
+#define SPI_MEM_WAITI_CMD_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR)..*/
+#define SPI_MEM_WAITI_DUMMY    (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/P
+ES command is sent..*/
+#define SPI_MEM_WAITI_EN    (BIT(0))
+#define SPI_MEM_WAITI_EN_M  (BIT(0))
+#define SPI_MEM_WAITI_EN_V  0x1
+#define SPI_MEM_WAITI_EN_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x9C)
+/* SPI_MEM_PESR_IDLE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: 1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate..*/
+#define SPI_MEM_PESR_IDLE_EN    (BIT(5))
+#define SPI_MEM_PESR_IDLE_EN_M  (BIT(5))
+#define SPI_MEM_PESR_IDLE_EN_V  0x1
+#define SPI_MEM_PESR_IDLE_EN_S  5
+/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable PES transfer trigger PES transfer option..*/
+#define SPI_MEM_PES_PER_EN    (BIT(4))
+#define SPI_MEM_PES_PER_EN_M  (BIT(4))
+#define SPI_MEM_PES_PER_EN_V  0x1
+#define SPI_MEM_PES_PER_EN_S  4
+/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to add delay time after program erase suspend(PES) command is sent..*/
+#define SPI_MEM_FLASH_PES_WAIT_EN    (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_M  (BIT(3))
+#define SPI_MEM_FLASH_PES_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PES_WAIT_EN_S  3
+/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to add delay time after program erase resume(PER) is sent..*/
+#define SPI_MEM_FLASH_PER_WAIT_EN    (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_M  (BIT(2))
+#define SPI_MEM_FLASH_PER_WAIT_EN_V  0x1
+#define SPI_MEM_FLASH_PER_WAIT_EN_S  2
+/* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit, program erase suspend operation will be triggered
+when the bit is set. The bit will be cleared once the operation done.1: enable 0: d
+isable. .*/
+#define SPI_MEM_FLASH_PES    (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit, program erase suspend operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: di
+sable. .*/
+#define SPI_MEM_FLASH_PER    (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA0)
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */
+/*description: Program/Erase suspend command value..*/
+#define SPI_MEM_FLASH_PES_COMMAND    0x000000FF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  9
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */
+/*description: Program/Erase resume command value..*/
+#define SPI_MEM_FLASH_PER_COMMAND    0x000000FF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  1
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable auto-suspend function..*/
+#define SPI_MEM_FLASH_PES_EN    (BIT(0))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(0))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA4)
+/* SPI_MEM_FLASH_PES_DLY_256 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent..*/
+#define SPI_MEM_FLASH_PES_DLY_256    (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_256_M  (BIT(6))
+#define SPI_MEM_FLASH_PES_DLY_256_V  0x1
+#define SPI_MEM_FLASH_PES_DLY_256_S  6
+/* SPI_MEM_FLASH_PER_DLY_256 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_
+RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM
+_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent..*/
+#define SPI_MEM_FLASH_PER_DLY_256    (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_256_M  (BIT(5))
+#define SPI_MEM_FLASH_PER_DLY_256_V  0x1
+#define SPI_MEM_FLASH_PER_DLY_256_S  5
+/* SPI_MEM_FLASH_DP_DLY_256 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP com
+mand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+after DP command is sent..*/
+#define SPI_MEM_FLASH_DP_DLY_256    (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_256_M  (BIT(4))
+#define SPI_MEM_FLASH_DP_DLY_256_V  0x1
+#define SPI_MEM_FLASH_DP_DLY_256_S  4
+/* SPI_MEM_FLASH_RES_DLY_256 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after RES command is sent..*/
+#define SPI_MEM_FLASH_RES_DLY_256    (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_256_M  (BIT(3))
+#define SPI_MEM_FLASH_RES_DLY_256_V  0x1
+#define SPI_MEM_FLASH_RES_DLY_256_S  3
+/* SPI_MEM_FLASH_HPM_DLY_256 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM co
+mmand is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles
+ after HPM command is sent..*/
+#define SPI_MEM_FLASH_HPM_DLY_256    (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_256_M  (BIT(2))
+#define SPI_MEM_FLASH_HPM_DLY_256_V  0x1
+#define SPI_MEM_FLASH_HPM_DLY_256_S  2
+/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend. This bit is set when PES command is sent, and clear
+ed when PER is sent. Only used in SPI1..*/
+#define SPI_MEM_FLASH_SUS    (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xA8)
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when S
+PI_MEM_TIMING_CALI bit is set..*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operation
+ns..*/
+#define SPI_MEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
+also to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
+#define SPI_MEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xAC)
+/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles
+at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK
+ positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
+EM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negat
+ive edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one
+ cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles
+at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DINS_MODE    0x00000007
+#define SPI_MEM_DINS_MODE_M  ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S))
+#define SPI_MEM_DINS_MODE_V  0x7
+#define SPI_MEM_DINS_MODE_S  24
+/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
+ at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
+LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
+_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
+gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
+ one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
+cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DIN7_MODE    0x00000007
+#define SPI_MEM_DIN7_MODE_M  ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S))
+#define SPI_MEM_DIN7_MODE_V  0x7
+#define SPI_MEM_DIN7_MODE_S  21
+/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
+ at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
+LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
+_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
+gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
+ one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
+cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DIN6_MODE    0x00000007
+#define SPI_MEM_DIN6_MODE_M  ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S))
+#define SPI_MEM_DIN6_MODE_V  0x7
+#define SPI_MEM_DIN6_MODE_S  18
+/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
+ at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
+LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
+_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
+gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
+ one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
+cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DIN5_MODE    0x00000007
+#define SPI_MEM_DIN5_MODE_M  ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S))
+#define SPI_MEM_DIN5_MODE_V  0x7
+#define SPI_MEM_DIN5_MODE_S  15
+/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
+ at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HC
+LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
+_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
+gative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
+ one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cy
+cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DIN4_MODE    0x00000007
+#define SPI_MEM_DIN4_MODE_M  ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S))
+#define SPI_MEM_DIN4_MODE_V  0x7
+#define SPI_MEM_DIN4_MODE_S  12
+/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
+at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL
+K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_
+MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
+nagetive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
+one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
+les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DIN3_MODE    0x00000007
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x7
+#define SPI_MEM_DIN3_MODE_S  9
+/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles
+at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCL
+K positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_
+MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
+nagetive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and
+one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cyc
+les at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DIN2_MODE    0x00000007
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x7
+#define SPI_MEM_DIN2_MODE_S  6
+/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a
+t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK
+ positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
+EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega
+tive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o
+ne cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycl
+es at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DIN1_MODE    0x00000007
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x7
+#define SPI_MEM_DIN1_MODE_S  3
+/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles a
+t MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK
+ positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_M
+EM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK nega
+tive edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o
+ne cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycl
+es at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_DIN0_MODE    0x00000007
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x7
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB0)
+/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: SPI_DQS input delay number..*/
+#define SPI_MEM_DINS_NUM    0x00000003
+#define SPI_MEM_DINS_NUM_M  ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S))
+#define SPI_MEM_DINS_NUM_V  0x3
+#define SPI_MEM_DINS_NUM_S  16
+/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: SPI_IO7 input delay number..*/
+#define SPI_MEM_DIN7_NUM    0x00000003
+#define SPI_MEM_DIN7_NUM_M  ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S))
+#define SPI_MEM_DIN7_NUM_V  0x3
+#define SPI_MEM_DIN7_NUM_S  14
+/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: SPI_IO6 input delay number..*/
+#define SPI_MEM_DIN6_NUM    0x00000003
+#define SPI_MEM_DIN6_NUM_M  ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S))
+#define SPI_MEM_DIN6_NUM_V  0x3
+#define SPI_MEM_DIN6_NUM_S  12
+/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: SPI_IO5 input delay number..*/
+#define SPI_MEM_DIN5_NUM    0x00000003
+#define SPI_MEM_DIN5_NUM_M  ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S))
+#define SPI_MEM_DIN5_NUM_V  0x3
+#define SPI_MEM_DIN5_NUM_S  10
+/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: SPI_IO4 input delay number..*/
+#define SPI_MEM_DIN4_NUM    0x00000003
+#define SPI_MEM_DIN4_NUM_M  ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S))
+#define SPI_MEM_DIN4_NUM_V  0x3
+#define SPI_MEM_DIN4_NUM_S  8
+/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: SPI_HD input delay number..*/
+#define SPI_MEM_DIN3_NUM    0x00000003
+#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
+#define SPI_MEM_DIN3_NUM_V  0x3
+#define SPI_MEM_DIN3_NUM_S  6
+/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: SPI_WP input delay number..*/
+#define SPI_MEM_DIN2_NUM    0x00000003
+#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
+#define SPI_MEM_DIN2_NUM_V  0x3
+#define SPI_MEM_DIN2_NUM_S  4
+/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: SPI_Q input delay number..*/
+#define SPI_MEM_DIN1_NUM    0x00000003
+#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
+#define SPI_MEM_DIN1_NUM_V  0x3
+#define SPI_MEM_DIN1_NUM_S  2
+/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI_D input delay number..*/
+#define SPI_MEM_DIN0_NUM    0x00000003
+#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
+#define SPI_MEM_DIN0_NUM_V  0x3
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xB4)
+/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_DOUTS_MODE_M  (BIT(8))
+#define SPI_MEM_DOUTS_MODE_V  0x1
+#define SPI_MEM_DOUTS_MODE_S  8
+/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_DOUT7_MODE_M  (BIT(7))
+#define SPI_MEM_DOUT7_MODE_V  0x1
+#define SPI_MEM_DOUT7_MODE_S  7
+/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_DOUT6_MODE_M  (BIT(6))
+#define SPI_MEM_DOUT6_MODE_V  0x1
+#define SPI_MEM_DOUT6_MODE_S  6
+/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_DOUT5_MODE_M  (BIT(5))
+#define SPI_MEM_DOUT5_MODE_V  0x1
+#define SPI_MEM_DOUT5_MODE_S  5
+/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_DOUT4_MODE_M  (BIT(4))
+#define SPI_MEM_DOUT4_MODE_V  0x1
+#define SPI_MEM_DOUT4_MODE_S  4
+/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
+ive edge..*/
+#define SPI_MEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_DOUT3_MODE_S  3
+/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
+ive edge..*/
+#define SPI_MEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_DOUT2_MODE_S  2
+/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
+ve edge..*/
+#define SPI_MEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_DOUT1_MODE_S  1
+/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
+ve edge..*/
+#define SPI_MEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0xBC)
+/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 acc
+esses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set..*/
+#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN    0x00000007
+#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x7
+#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operation
+ns..*/
+#define SPI_MEM_SPI_SMEM_TIMING_CALI    (BIT(1))
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_V  0x1
+#define SPI_MEM_SPI_SMEM_TIMING_CALI_S  1
+/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equ
+also to that of PLL. Otherwise, the frequency equals to that of XTAL..*/
+#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA    (BIT(0))
+#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC0)
+/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */
+/*description: SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles
+ at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HC
+LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
+_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK ne
+gative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and
+ one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cy
+cles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DINS_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DINS_MODE_M  ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S))
+#define SPI_MEM_SPI_SMEM_DINS_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DINS_MODE_S  24
+/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */
+/*description: SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
+s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
+HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
+PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
+ negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
+ and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DIN7_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN7_MODE_M  ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN7_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN7_MODE_S  21
+/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */
+/*description: SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
+s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
+HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
+PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
+ negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
+ and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DIN6_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN6_MODE_M  ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN6_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN6_MODE_S  18
+/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */
+/*description: SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
+s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
+HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
+PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
+ negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
+ and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DIN5_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN5_MODE_M  ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN5_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN5_MODE_S  15
+/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */
+/*description: SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycle
+s at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at
+HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (S
+PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
+ negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
+ and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+
+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DIN4_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN4_MODE_M  ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN4_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN4_MODE_S  12
+/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
+ at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at H
+CLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SP
+I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
+negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
+and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1
+) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DIN3_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN3_MODE_M  ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN3_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN3_MODE_S  9
+/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
+ at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at H
+CLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SP
+I_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK
+negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
+and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1
+) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DIN2_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN2_MODE_M  ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN2_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN2_MODE_S  6
+/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
+at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
+LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
+_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
+egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
+and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
+ cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DIN1_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN1_MODE_M  ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN1_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN1_MODE_S  3
+/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles
+at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HC
+LK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI
+_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK n
+egative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge
+and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1)
+ cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge..*/
+#define SPI_MEM_SPI_SMEM_DIN0_MODE    0x00000007
+#define SPI_MEM_SPI_SMEM_DIN0_MODE_M  ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S))
+#define SPI_MEM_SPI_SMEM_DIN0_MODE_V  0x7
+#define SPI_MEM_SPI_SMEM_DIN0_MODE_S  0
+
+#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC4)
+/* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
+/*description: SPI_DQS input delay number..*/
+#define SPI_MEM_SPI_SMEM_DINS_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DINS_NUM_M  ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S))
+#define SPI_MEM_SPI_SMEM_DINS_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DINS_NUM_S  16
+/* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
+/*description: SPI_IO7 input delay number..*/
+#define SPI_MEM_SPI_SMEM_DIN7_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN7_NUM_M  ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN7_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN7_NUM_S  14
+/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
+/*description: SPI_IO6 input delay number..*/
+#define SPI_MEM_SPI_SMEM_DIN6_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN6_NUM_M  ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN6_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN6_NUM_S  12
+/* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
+/*description: SPI_IO5 input delay number..*/
+#define SPI_MEM_SPI_SMEM_DIN5_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN5_NUM_M  ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN5_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN5_NUM_S  10
+/* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: SPI_IO4 input delay number..*/
+#define SPI_MEM_SPI_SMEM_DIN4_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN4_NUM_M  ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN4_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN4_NUM_S  8
+/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: SPI_HD input delay number..*/
+#define SPI_MEM_SPI_SMEM_DIN3_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN3_NUM_M  ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN3_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN3_NUM_S  6
+/* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: SPI_WP input delay number..*/
+#define SPI_MEM_SPI_SMEM_DIN2_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN2_NUM_M  ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN2_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN2_NUM_S  4
+/* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: SPI_Q input delay number..*/
+#define SPI_MEM_SPI_SMEM_DIN1_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN1_NUM_M  ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN1_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN1_NUM_S  2
+/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI_D input delay number..*/
+#define SPI_MEM_SPI_SMEM_DIN0_NUM    0x00000003
+#define SPI_MEM_SPI_SMEM_DIN0_NUM_M  ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S))
+#define SPI_MEM_SPI_SMEM_DIN0_NUM_V  0x3
+#define SPI_MEM_SPI_SMEM_DIN0_NUM_S  0
+
+#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xC8)
+/* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_SPI_SMEM_DOUTS_MODE    (BIT(8))
+#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M  (BIT(8))
+#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S  8
+/* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_SPI_SMEM_DOUT7_MODE    (BIT(7))
+#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M  (BIT(7))
+#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S  7
+/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_SPI_SMEM_DOUT6_MODE    (BIT(6))
+#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M  (BIT(6))
+#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S  6
+/* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_SPI_SMEM_DOUT5_MODE    (BIT(5))
+#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M  (BIT(5))
+#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S  5
+/* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK nega
+tive edge..*/
+#define SPI_MEM_SPI_SMEM_DOUT4_MODE    (BIT(4))
+#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M  (BIT(4))
+#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S  4
+/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
+ive edge..*/
+#define SPI_MEM_SPI_SMEM_DOUT3_MODE    (BIT(3))
+#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M  (BIT(3))
+#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S  3
+/* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negat
+ive edge..*/
+#define SPI_MEM_SPI_SMEM_DOUT2_MODE    (BIT(2))
+#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S  2
+/* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
+ve edge..*/
+#define SPI_MEM_SPI_SMEM_DOUT1_MODE    (BIT(1))
+#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S  1
+/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negati
+ve edge..*/
+#define SPI_MEM_SPI_SMEM_DOUT0_MODE    (BIT(0))
+#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_ECC_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xCC)
+/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to flas
+h..*/
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN    (BIT(8))
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M  (BIT(8))
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S  8
+/* SPI_MEM_ECC_ERR_INT_NUM : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
+/*description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interr
+upt..*/
+#define SPI_MEM_ECC_ERR_INT_NUM    0x000000FF
+#define SPI_MEM_ECC_ERR_INT_NUM_M  ((SPI_MEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_ECC_ERR_INT_NUM_S))
+#define SPI_MEM_ECC_ERR_INT_NUM_V  0xFF
+#define SPI_MEM_ECC_ERR_INT_NUM_S  0
+
+#define SPI_MEM_ECC_ERR_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD0)
+/* SPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SP
+I_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte e
+rror and data error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/
+#define SPI_MEM_ECC_ERR_ADDR    0xFFFFFFFF
+#define SPI_MEM_ECC_ERR_ADDR_M  ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S))
+#define SPI_MEM_ECC_ERR_ADDR_V  0xFFFFFFFF
+#define SPI_MEM_ECC_ERR_ADDR_S  0
+
+#define SPI_MEM_ECC_ERR_BIT_REG(i)          (REG_SPI_MEM_BASE(i) + 0xD4)
+/* SPI_MEM_ECC_ERR_CNT : RO ;bitpos:[24:17] ;default: 8'd0 ; */
+/*description: This bits show the error times of MSPI ECC read, including ECC byte error and da
+ta byte error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. .*/
+#define SPI_MEM_ECC_ERR_CNT    0x000000FF
+#define SPI_MEM_ECC_ERR_CNT_M  ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S))
+#define SPI_MEM_ECC_ERR_CNT_V  0xFF
+#define SPI_MEM_ECC_ERR_CNT_S  17
+/* SPI_MEM_ECC_BYTE_ERR : R/SS/WTC ;bitpos:[16] ;default: 1'd0 ; */
+/*description: It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ER
+R_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_
+INT_CLR bit..*/
+#define SPI_MEM_ECC_BYTE_ERR    (BIT(16))
+#define SPI_MEM_ECC_BYTE_ERR_M  (BIT(16))
+#define SPI_MEM_ECC_BYTE_ERR_V  0x1
+#define SPI_MEM_ECC_BYTE_ERR_S  16
+/* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */
+/*description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC
+byte..*/
+#define SPI_MEM_ECC_CHK_ERR_BIT    0x00000007
+#define SPI_MEM_ECC_CHK_ERR_BIT_M  ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S))
+#define SPI_MEM_ECC_CHK_ERR_BIT_V  0x7
+#define SPI_MEM_ECC_CHK_ERR_BIT_S  13
+/* SPI_MEM_ECC_DATA_ERR_BIT : R/SS/WTC ;bitpos:[12:6] ;default: 7'd0 ; */
+/*description: It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_
+SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from
+0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_ME
+M_ECC_ERR_INT_CLR bit..*/
+#define SPI_MEM_ECC_DATA_ERR_BIT    0x0000007F
+#define SPI_MEM_ECC_DATA_ERR_BIT_M  ((SPI_MEM_ECC_DATA_ERR_BIT_V)<<(SPI_MEM_ECC_DATA_ERR_BIT_S))
+#define SPI_MEM_ECC_DATA_ERR_BIT_V  0x7F
+#define SPI_MEM_ECC_DATA_ERR_BIT_S  6
+
+#define SPI_MEM_SPI_SMEM_AC_REG(i)          (REG_SPI_MEM_BASE(i) + 0xDC)
+/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */
+/*description: These bits are used to set the minimum CS high time tSHSL between SPI burst tran
+sfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) M
+SPI core clock cycles..*/
+#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY    0x0000003F
+#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S))
+#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V  0x3F
+#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S  25
+/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to calculate the error times of MSPI ECC read when accesses to exte
+rnal RAM..*/
+#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN    (BIT(24))
+#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M  (BIT(24))
+#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S  24
+/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesse
+s to external RAM..*/
+#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN    (BIT(16))
+#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M  (BIT(16))
+#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S  16
+/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: 1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner
+ when accesses to external RAM..*/
+#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER    (BIT(15))
+#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M  (BIT(15))
+#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V  0x1
+#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S  15
+/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in
+ECC mode when accesses to external RAM..*/
+#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME    0x00000007
+#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S))
+#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V  0x7
+#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S  12
+/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */
+/*description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), wh
+ich is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_ME
+M_CS_HOLD bit..*/
+#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME    0x0000001F
+#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M  ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S))
+#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V  0x1F
+#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S  7
+/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */
+/*description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits
+are combined with SPI_MEM_CS_SETUP bit..*/
+#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME    0x0000001F
+#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M  ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S))
+#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V  0x1F
+#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S  2
+/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to keep SPI_CS low when MSPI is in DONE state..*/
+#define SPI_MEM_SPI_SMEM_CS_HOLD    (BIT(1))
+#define SPI_MEM_SPI_SMEM_CS_HOLD_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_CS_HOLD_V  0x1
+#define SPI_MEM_SPI_SMEM_CS_HOLD_S  1
+/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to keep SPI_CS low when MSPI is in PREP state..*/
+#define SPI_MEM_SPI_SMEM_CS_SETUP    (BIT(0))
+#define SPI_MEM_SPI_SMEM_CS_SETUP_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_CS_SETUP_V  0x1
+#define SPI_MEM_SPI_SMEM_CS_SETUP_S  0
+
+#define SPI_MEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE0)
+/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}..*/
+#define SPI_MEM_SPI_FMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M  (BIT(30))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V  0x1
+#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S  30
+/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to flash, which means
+ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}
+..*/
+#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V  0x1
+#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S  29
+/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to flash. ..*/
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M  (BIT(28))
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V  0x1
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S  28
+/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses flash or SPI1 accesses flash or sram..*/
+#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S  27
+/* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define SPI_MEM_SPI_FMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M  (BIT(26))
+#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V  0x1
+#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S  26
+/* SPI_MEM_SPI_FMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to enable the SPI HyperBus mode..*/
+#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE    (BIT(25))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M  (BIT(25))
+#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V  0x1
+#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S  25
+/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M  (BIT(24))
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S  24
+/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK
+ as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is
+ not active..*/
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE    (BIT(22))
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M  (BIT(22))
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S  22
+/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Use internal signal  as data strobe, the strobe can not be delayed by input t
+iming module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe ca
+n be delayed by input timing module.*/
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S  21
+/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI_CLK..*/
+#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD    0x0000007F
+#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S))
+#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V  0x7F
+#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S  14
+/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when
+accesses to flash..*/
+#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S  13
+/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when
+ accesses to flash..*/
+#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S  12
+/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the panda device..*/
+#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN    0x0000007F
+#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S))
+#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V  0x7F
+#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S  5
+/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in command phase when DDR mode..*/
+#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M  (BIT(4))
+#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S  4
+/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder TX data of the word in DDR mode..*/
+#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S  3
+/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder RX data of the word in DDR mode..*/
+#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S  2
+/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in DDRmode..*/
+#define SPI_MEM_SPI_FMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M  (BIT(1))
+#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V  0x1
+#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S  1
+/* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in DDR mode,  0: in SDR mode..*/
+#define SPI_MEM_SPI_FMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_SPI_FMEM_DDR_EN_M  (BIT(0))
+#define SPI_MEM_SPI_FMEM_DDR_EN_V  0x1
+#define SPI_MEM_SPI_FMEM_DDR_EN_S  0
+
+#define SPI_MEM_SPI_SMEM_DDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE4)
+/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable HyperRAM address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1
+]}..*/
+#define SPI_MEM_SPI_SMEM_HYPERBUS_CA    (BIT(30))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M  (BIT(30))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V  0x1
+#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S  30
+/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable octa_ram address out when accesses to external RAM, which
+ means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1]
+, 1'b0}..*/
+#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR    (BIT(29))
+#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M  (BIT(29))
+#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V  0x1
+#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S  29
+/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. ..*/
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV    (BIT(28))
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M  (BIT(28))
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V  0x1
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S  28
+/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 a
+ccesses to flash or SPI1 accesses flash or sram..*/
+#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X    (BIT(27))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M  (BIT(27))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V  0x1
+#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S  27
+/* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR
+..*/
+#define SPI_MEM_SPI_SMEM_DQS_CA_IN    (BIT(26))
+#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M  (BIT(26))
+#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V  0x1
+#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S  26
+/* SPI_MEM_SPI_SMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to enable the SPI HyperBus mode..*/
+#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE    (BIT(25))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M  (BIT(25))
+#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S  25
+/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable the differential SPI_CLK#..*/
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN    (BIT(24))
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M  (BIT(24))
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S  24
+/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK
+ as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is
+ not active..*/
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE    (BIT(22))
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M  (BIT(22))
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S  22
+/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: Use internal signal  as data strobe, the strobe can not be delayed by input t
+iming module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe ca
+n be delayed by input timing module.*/
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP    (BIT(21))
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M  (BIT(21))
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S  21
+/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */
+/*description: The delay number of data strobe which from memory based on SPI_CLK..*/
+#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD    0x0000007F
+#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M  ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S))
+#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V  0x7F
+#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S  14
+/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when
+accesses to external RAM..*/
+#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN    (BIT(13))
+#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M  (BIT(13))
+#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S  13
+/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when
+ accesses to external RAM..*/
+#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN    (BIT(12))
+#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M  (BIT(12))
+#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S  12
+/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */
+/*description: It is the minimum output data length in the ddr psram..*/
+#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN    0x0000007F
+#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M  ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S))
+#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V  0x7F
+#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S  5
+/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: the bit is used to disable dual edge in CMD phase when ddr mode..*/
+#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS    (BIT(4))
+#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M  (BIT(4))
+#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S  4
+/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set the bit to reorder tx data of the word in spi ddr mode..*/
+#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP    (BIT(3))
+#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M  (BIT(3))
+#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S  3
+/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to reorder rx data of the word in spi ddr mode..*/
+#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP    (BIT(2))
+#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M  (BIT(2))
+#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S  2
+/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set the bit to enable variable dummy cycle in spi ddr mode..*/
+#define SPI_MEM_SPI_SMEM_VAR_DUMMY    (BIT(1))
+#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M  (BIT(1))
+#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V  0x1
+#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S  1
+/* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: in ddr mode,  0 in sdr mode.*/
+#define SPI_MEM_SPI_SMEM_DDR_EN    (BIT(0))
+#define SPI_MEM_SPI_SMEM_DDR_EN_M  (BIT(0))
+#define SPI_MEM_SPI_SMEM_DDR_EN_V  0x1
+#define SPI_MEM_SPI_SMEM_DDR_EN_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0xE8)
+/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Register clock gate enable signal. 1: Enable. 0: Disable..*/
+#define SPI_MEM_CLK_EN    (BIT(0))
+#define SPI_MEM_CLK_EN_M  (BIT(0))
+#define SPI_MEM_CLK_EN_V  0x1
+#define SPI_MEM_CLK_EN_S  0
+
+#define SPI_MEM_CORE_CLK_SEL_REG(i)          (REG_SPI_MEM_BASE(i) + 0xEC)
+/* SPI_MEM_CORE_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: When the digital system clock selects PLL clock and the frequency of PLL clock i
+s 480MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: SPI0/1 module clock (MSPI_CORE_
+CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz.  2: MSPI_CORE_CLK is 160MHz. 3: MSPI_
+CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the freq
+uency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: MSPI_CORE_C
+LK is 80MHz. 1: MSPI_CORE_CLK is 80MHz.  2: MSPI_CORE_CLK 160MHz. 3: Not used. .*/
+#define SPI_MEM_CORE_CLK_SEL    0x00000003
+#define SPI_MEM_CORE_CLK_SEL_M  ((SPI_MEM_CORE_CLK_SEL_V)<<(SPI_MEM_CORE_CLK_SEL_S))
+#define SPI_MEM_CORE_CLK_SEL_V  0x3
+#define SPI_MEM_CORE_CLK_SEL_S  0
+
+#define SPI_MEM_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF0)
+/* SPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_ENA    (BIT(4))
+#define SPI_MEM_ECC_ERR_INT_ENA_M  (BIT(4))
+#define SPI_MEM_ECC_ERR_INT_ENA_V  0x1
+#define SPI_MEM_ECC_ERR_INT_ENA_S  4
+/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ENA    (BIT(3))
+#define SPI_MEM_BROWN_OUT_INT_ENA_M  (BIT(3))
+#define SPI_MEM_BROWN_OUT_INT_ENA_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ENA_S  3
+/* SPI_MEM_TOTAL_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
+#define SPI_MEM_TOTAL_TRANS_END_INT_ENA    (BIT(2))
+#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_M  (BIT(2))
+#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_S  2
+/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ENA    (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ENA_V  0x1
+#define SPI_MEM_PES_END_INT_ENA_S  1
+/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ENA    (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ENA_V  0x1
+#define SPI_MEM_PER_END_INT_ENA_S  0
+
+#define SPI_MEM_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF4)
+/* SPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_ME
+M_ECC_ERR_CNT will be cleared by the pulse of this bit..*/
+#define SPI_MEM_ECC_ERR_INT_CLR    (BIT(4))
+#define SPI_MEM_ECC_ERR_INT_CLR_M  (BIT(4))
+#define SPI_MEM_ECC_ERR_INT_CLR_V  0x1
+#define SPI_MEM_ECC_ERR_INT_CLR_S  4
+/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_CLR    (BIT(3))
+#define SPI_MEM_BROWN_OUT_INT_CLR_M  (BIT(3))
+#define SPI_MEM_BROWN_OUT_INT_CLR_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_CLR_S  3
+/* SPI_MEM_TOTAL_TRANS_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
+#define SPI_MEM_TOTAL_TRANS_END_INT_CLR    (BIT(2))
+#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_M  (BIT(2))
+#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_V  0x1
+#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_S  2
+/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_CLR    (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_CLR_V  0x1
+#define SPI_MEM_PES_END_INT_CLR_S  1
+/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_CLR    (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_CLR_V  0x1
+#define SPI_MEM_PER_END_INT_CLR_S  0
+
+#define SPI_MEM_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0xF8)
+/* SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is
+set and  APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the err
+or times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_
+NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and  APB_CTRL_SECC_ERR_INT_EN is s
+et, this bit is triggered when the error times of SPI0/1 ECC read external RAM a
+re equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN
+and  APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error
+r times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_C
+TRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN
+ are cleared, this bit will not be triggered..*/
+#define SPI_MEM_ECC_ERR_INT_RAW    (BIT(4))
+#define SPI_MEM_ECC_ERR_INT_RAW_M  (BIT(4))
+#define SPI_MEM_ECC_ERR_INT_RAW_V  0x1
+#define SPI_MEM_ECC_ERR_INT_RAW_S  4
+/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
+chip is losing power and RTC module sends out brown out close flash request to
+SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
+ and MSPI returns to idle state. 0: Others..*/
+#define SPI_MEM_BROWN_OUT_INT_RAW    (BIT(3))
+#define SPI_MEM_BROWN_OUT_INT_RAW_M  (BIT(3))
+#define SPI_MEM_BROWN_OUT_INT_RAW_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_RAW_S  3
+/* SPI_MEM_TOTAL_TRANS_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 tr
+ansfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/
+PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success.  0: Other
+s..*/
+#define SPI_MEM_TOTAL_TRANS_END_INT_RAW    (BIT(2))
+#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_M  (BIT(2))
+#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_V  0x1
+#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_S  2
+/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend com
+mand (0x75) is sent and flash is suspended successfully. 0: Others..*/
+#define SPI_MEM_PES_END_INT_RAW    (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_RAW_V  0x1
+#define SPI_MEM_PES_END_INT_RAW_S  1
+/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume com
+mand (0x7A) is sent and flash is resumed successfully. 0: Others..*/
+#define SPI_MEM_PER_END_INT_RAW    (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_RAW_V  0x1
+#define SPI_MEM_PER_END_INT_RAW_S  0
+
+#define SPI_MEM_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0xFC)
+/* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_ECC_ERR_INT interrupt..*/
+#define SPI_MEM_ECC_ERR_INT_ST    (BIT(4))
+#define SPI_MEM_ECC_ERR_INT_ST_M  (BIT(4))
+#define SPI_MEM_ECC_ERR_INT_ST_V  0x1
+#define SPI_MEM_ECC_ERR_INT_ST_S  4
+/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt..*/
+#define SPI_MEM_BROWN_OUT_INT_ST    (BIT(3))
+#define SPI_MEM_BROWN_OUT_INT_ST_M  (BIT(3))
+#define SPI_MEM_BROWN_OUT_INT_ST_V  0x1
+#define SPI_MEM_BROWN_OUT_INT_ST_S  3
+/* SPI_MEM_TOTAL_TRANS_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt..*/
+#define SPI_MEM_TOTAL_TRANS_END_INT_ST    (BIT(2))
+#define SPI_MEM_TOTAL_TRANS_END_INT_ST_M  (BIT(2))
+#define SPI_MEM_TOTAL_TRANS_END_INT_ST_V  0x1
+#define SPI_MEM_TOTAL_TRANS_END_INT_ST_S  2
+/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PES_END_INT interrupt..*/
+#define SPI_MEM_PES_END_INT_ST    (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_M  (BIT(1))
+#define SPI_MEM_PES_END_INT_ST_V  0x1
+#define SPI_MEM_PES_END_INT_ST_S  1
+/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MEM_PER_END_INT interrupt..*/
+#define SPI_MEM_PER_END_INT_ST    (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_M  (BIT(0))
+#define SPI_MEM_PER_END_INT_ST_V  0x1
+#define SPI_MEM_PER_END_INT_ST_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W ;bitpos:[27:5] ;default: 23'h108082 ; */
+/*description: SPI register version..*/
+#define SPI_MEM_DATE    0x007FFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0x7FFFFF
+#define SPI_MEM_DATE_S  5
+/* SPI_MEM_SPICLK_PAD_DRV_CTL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD  is controlled b
+y the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The
+ driver of SPI_CLK PAD  is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK
+ PAD..*/
+#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN    (BIT(4))
+#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_M  (BIT(4))
+#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V  0x1
+#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S  4
+/* SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0
+] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash..*/
+#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV    0x00000003
+#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_M  ((SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S))
+#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V  0x3
+#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S  2
+/* SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: The driver of SPI_CLK PAD  is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0
+] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RA
+M..*/
+#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV    0x00000003
+#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_M  ((SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S))
+#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V  0x3
+#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/spi_mem_struct.h b/components/soc/esp32s3/register/soc/spi_mem_struct.h
new file mode 100644
index 00000000000..07d352bb184
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/spi_mem_struct.h
@@ -0,0 +1,773 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_MEM_STRUCT_H_
+#define _SOC_SPI_MEM_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct spi_mem_dev_s {
+    union {
+        struct {
+            uint32_t reserved0                     :    17;  /*reserved*/
+            uint32_t flash_pe                      :    1;  /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_hpm                     :    1;  /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_res                     :    1;  /*This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_dp                      :    1;  /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_ce                      :    1;  /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_be                      :    1;  /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_se                      :    1;  /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pp                      :    1;  /*Page program enable(1 byte ~64 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
+            uint32_t flash_wrsr                    :    1;  /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdsr                    :    1;  /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_rdid                    :    1;  /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wrdi                    :    1;  /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_wren                    :    1;  /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+            uint32_t flash_read                    :    1;  /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;  /*reserved*/
+            uint32_t fdummy_out                    :    1;  /*In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
+            uint32_t fdout_oct                     :    1;  /*Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.*/
+            uint32_t fdin_oct                      :    1;  /*Set this bit to enable 8-bit-mode(8-bm) in DIN phase.*/
+            uint32_t faddr_oct                     :    1;  /*Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.*/
+            uint32_t fcmd_dual                     :    1;  /*Set this bit to enable 2-bit-mode(2-bm) in CMD phase.*/
+            uint32_t fcmd_quad                     :    1;  /*Set this bit to enable 4-bit-mode(4-bm) in CMD phase.*/
+            uint32_t fcmd_oct                      :    1;  /*Set this bit to enable 8-bit-mode(8-bm) in CMD phase.*/
+            uint32_t fcs_crc_en                    :    1;  /*For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en                     :    1;  /*For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12                    :    1;  /*reserved*/
+            uint32_t fastrd_mode                   :    1;  /*This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.*/
+            uint32_t fread_dual                    :    1;  /*In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. */
+            uint32_t resandres                     :    1;  /*The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
+            uint32_t reserved16                    :    2;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low*/
+            uint32_t fread_quad                    :    1;  /*In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
+            uint32_t wp                            :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low. */
+            uint32_t wrsr_2b                       :    1;  /*Two bytes data will be written to status register when it is set. 1: enable 0: disable. */
+            uint32_t fread_dio                     :    1;  /*In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. */
+            uint32_t fread_qio                     :    1;  /*In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.*/
+            uint32_t cs_hold_dly_res               :    10;  /*After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.*/
+            uint32_t reserved2                     :    18;  /*reserved*/
+            uint32_t rxfifo_rst                    :    1;  /*SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time                 :    5;  /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
+            uint32_t cs_hold_time                  :    5;  /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
+            uint32_t ecc_cs_hold_time              :    3;  /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.*/
+            uint32_t ecc_skip_page_corner          :    1;  /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
+            uint32_t ecc_16to18_byte_en            :    1;  /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
+            uint32_t reserved15                    :    10;  /*reserved*/
+            uint32_t cs_hold_delay                 :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t sync_reset                    :    1;  /*The FSM will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    8;  /*It must equal to the value of SPI_MEM_CLKCNT_N. */
+            uint32_t clkcnt_h                      :    8;  /*It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).*/
+            uint32_t clkcnt_n                      :    8;  /*When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/
+            uint32_t reserved24                    :    7;  /*reserved*/
+            uint32_t clk_equ_sysclk                :    1;  /*When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t cs_hold                       :    1;  /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
+            uint32_t cs_setup                      :    1;  /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
+            uint32_t reserved8                     :    1;  /*reserved*/
+            uint32_t ck_out_edge                   :    1;  /*This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. */
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.*/
+            uint32_t fwrite_quad                   :    1;  /*Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.*/
+            uint32_t fwrite_dio                    :    1;  /*Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.*/
+            uint32_t fwrite_qio                    :    1;  /*Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.*/
+            uint32_t reserved16                    :    8;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
+            uint32_t usr_mosi_highpart             :    1;  /*DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
+            uint32_t usr_dummy_idle                :    1;  /*SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.*/
+            uint32_t usr_mosi                      :    1;  /*Set this bit to enable the DOUT phase of an write-data operation.*/
+            uint32_t usr_miso                      :    1;  /*Set this bit to enable enable the DIN phase of a read-data operation.*/
+            uint32_t usr_dummy                     :    1;  /*Set this bit to enable enable the DUMMY phase of an operation.*/
+            uint32_t usr_addr                      :    1;  /*Set this bit to enable enable the ADDR phase of an operation.*/
+            uint32_t usr_command                   :    1;  /*Set this bit to enable enable the CMD phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    6;  /*The SPI_CLK cycle length minus 1 of DUMMY phase.*/
+            uint32_t reserved6                     :    20;  /*reserved*/
+            uint32_t usr_addr_bitlen               :    6;  /*The length in bits of ADDR phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of user defined(USR) command.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of CMD phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len              :    10;  /*The length in bits of DOUT phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len              :    10;  /*The length in bits of DIN phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved10                    :    22;  /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status                        :    16;  /*The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit.*/
+            uint32_t wb_mode                       :    8;  /*Mode bits in the flash fast read mode  it is combined with SPI_MEM_FASTRD_MODE bit.*/
+            uint32_t reserved24                    :    8;  /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t ext_addr;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts.*/
+            uint32_t cs1_dis                       :    1;  /*Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts.*/
+            uint32_t reserved0                     :    5;  /*reserved*/
+            uint32_t fsub_pin                      :    1;  /*Flash is connected to SPI SUBPIN bus.*/
+            uint32_t ssub_pin                      :    1;  /*Ext_RAM is connected to SPI SUBPIN bus.*/
+            uint32_t ck_idle_edge                  :    1;  /*1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle */
+            uint32_t cs_keep_active                :    1;  /*SPI_CS line keep low when the bit is set.*/
+            uint32_t auto_per                      :    1;  /*Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;
+    union {
+        struct {
+            uint32_t req_en                        :    1;  /*Set this bit to enable Cache's access and SPI0's transfer.*/
+            uint32_t usr_cmd_4byte                 :    1;  /*Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.*/
+            uint32_t flash_usr_cmd                 :    1;  /*1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.*/
+            uint32_t fdin_dual                     :    1;  /*When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.*/
+            uint32_t fdout_dual                    :    1;  /*When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.*/
+            uint32_t faddr_dual                    :    1;  /*When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.*/
+            uint32_t fdin_quad                     :    1;  /*When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.*/
+            uint32_t fdout_quad                    :    1;  /*When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.*/
+            uint32_t faddr_quad                    :    1;  /*When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    union {
+        struct {
+            uint32_t usr_scmd_4byte                :    1;  /*Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.*/
+            uint32_t usr_sram_dio                  :    1;  /*Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.*/
+            uint32_t usr_sram_qio                  :    1;  /*Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.*/
+            uint32_t usr_wr_sram_dummy             :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.*/
+            uint32_t usr_rd_sram_dummy             :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.*/
+            uint32_t usr_rcmd                      :    1;  /*1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.*/
+            uint32_t sram_rdummy_cyclelen          :    6;  /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.*/
+            uint32_t reserved12                    :    2;  /*reserved*/
+            uint32_t sram_addr_bitlen              :    6;  /*When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).*/
+            uint32_t usr_wcmd                      :    1;  /*1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.*/
+            uint32_t sram_oct                      :    1;  /*Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.*/
+            uint32_t sram_wdummy_cyclelen          :    6;  /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } cache_sctrl;
+    union {
+        struct {
+            uint32_t sclk_mode                     :    2;  /*SPI_CLK mode bits  when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.*/
+            uint32_t swb_mode                      :    8;  /*Mode bits when SPI0 accesses to Ext_RAM.*/
+            uint32_t sdin_dual                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.*/
+            uint32_t sdout_dual                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.*/
+            uint32_t saddr_dual                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.*/
+            uint32_t scmd_dual                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.*/
+            uint32_t sdin_quad                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.*/
+            uint32_t sdout_quad                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.*/
+            uint32_t saddr_quad                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.*/
+            uint32_t scmd_quad                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.*/
+            uint32_t sdin_oct                      :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.*/
+            uint32_t sdout_oct                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.*/
+            uint32_t saddr_oct                     :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.*/
+            uint32_t scmd_oct                      :    1;  /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.*/
+            uint32_t sdummy_out                    :    1;  /*When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
+            uint32_t reserved23                    :    9;  /*reserved*/
+        };
+        uint32_t val;
+    } sram_cmd;
+    union {
+        struct {
+            uint32_t usr_rd_cmd_value              :    16;  /*When SPI0 reads Ext_RAM, it is the command value of CMD phase.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_rd_cmd_bitlen             :    4;  /*When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_drd_cmd;
+    union {
+        struct {
+            uint32_t usr_wr_cmd_value              :    16;  /*When SPI0 writes Ext_RAM, it is the command value of CMD phase.*/
+            uint32_t reserved16                    :    12;  /*reserved*/
+            uint32_t usr_wr_cmd_bitlen             :    4;  /*When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_dwr_cmd;
+    union {
+        struct {
+            uint32_t cnt_l                         :    8;  /*It must equal to the value of SPI_MEM_SCLKCNT_N. */
+            uint32_t cnt_h                         :    8;  /*It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1).*/
+            uint32_t cnt_n                         :    8;  /*When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)*/
+            uint32_t reserved24                    :    7;  /*reserved*/
+            uint32_t equ_sysclk                    :    1;  /*When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
+        };
+        uint32_t val;
+    } sram_clk;
+    union {
+        struct {
+            uint32_t st                            :    3;  /*The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    uint32_t data_buf[16];                                                /*data buffer*/
+    union {
+        struct {
+            uint32_t waiti_en                      :    1;  /*Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.*/
+            uint32_t waiti_dummy                   :    1;  /*Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR).*/
+            uint32_t waiti_cmd                     :    8;  /*The command value of auto wait flash idle transfer(RDSR).*/
+            uint32_t waiti_dummy_cyclelen          :    6;  /*The dummy cycle length when wait flash idle(RDSR).*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per                     :    1;  /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_pes                     :    1;  /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
+            uint32_t flash_per_wait_en             :    1;  /*Set this bit to add delay time after program erase resume(PER) is sent.*/
+            uint32_t flash_pes_wait_en             :    1;  /*Set this bit to add delay time after program erase suspend(PES) command is sent.*/
+            uint32_t pes_per_en                    :    1;  /*Set this bit to enable PES transfer trigger PES transfer option.*/
+            uint32_t pesr_idle_en                  :    1;  /*1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.*/
+            uint32_t reserved6                     :    26;  /*reserved*/
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_pes_en                  :    1;  /*Set this bit to enable auto-suspend function.*/
+            uint32_t flash_per_command             :    8;  /*Program/Erase resume command value.*/
+            uint32_t flash_pes_command             :    8;  /*Program/Erase suspend command value.*/
+            uint32_t reserved17                    :    15;  /*reserved*/
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t flash_sus                     :    1;  /*The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1.*/
+            uint32_t reserved1                     :    1;  /*reserved*/
+            uint32_t flash_hpm_dly_256             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
+            uint32_t flash_res_dly_256             :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
+            uint32_t flash_dp_dly_256              :    1;  /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
+            uint32_t flash_per_dly_256             :    1;  /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
+            uint32_t flash_pes_dly_256             :    1;  /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
+            uint32_t reserved7                     :    25;  /*reserved*/
+        };
+        uint32_t val;
+    } sus_status;
+    union {
+        struct {
+            uint32_t timing_clk_ena                :    1;  /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
+            uint32_t timing_cali                   :    1;  /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
+            uint32_t extra_dummy_cyclelen          :    3;  /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } timing_cali;
+    union {
+        struct {
+            uint32_t din0_mode                     :    3;  /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t din1_mode                     :    3;  /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t din2_mode                     :    3;  /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t din3_mode                     :    3;  /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t din4_mode                     :    3;  /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t din5_mode                     :    3;  /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t din6_mode                     :    3;  /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t din7_mode                     :    3;  /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t dins_mode                     :    3;  /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*SPI_D input delay number.*/
+            uint32_t din1_num                      :    2;  /*SPI_Q input delay number.*/
+            uint32_t din2_num                      :    2;  /*SPI_WP input delay number.*/
+            uint32_t din3_num                      :    2;  /*SPI_HD input delay number.*/
+            uint32_t din4_num                      :    2;  /*SPI_IO4 input delay number.*/
+            uint32_t din5_num                      :    2;  /*SPI_IO5 input delay number.*/
+            uint32_t din6_num                      :    2;  /*SPI_IO6 input delay number.*/
+            uint32_t din7_num                      :    2;  /*SPI_IO7 input delay number.*/
+            uint32_t dins_num                      :    2;  /*SPI_DQS input delay number.*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t dout1_mode                    :    1;  /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t dout2_mode                    :    1;  /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t dout3_mode                    :    1;  /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t dout4_mode                    :    1;  /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t dout5_mode                    :    1;  /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t dout6_mode                    :    1;  /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t dout7_mode                    :    1;  /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t douts_mode                    :    1;  /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    uint32_t reserved_b8;
+    union {
+        struct {
+            uint32_t smem_timing_clk_ena           :    1;  /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
+            uint32_t smem_timing_cali              :    1;  /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
+            uint32_t smem_extra_dummy_cyclelen     :    3;  /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_timing_cali;
+    union {
+        struct {
+            uint32_t smem_din0_mode                :    3;  /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_din1_mode                :    3;  /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_din2_mode                :    3;  /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_din3_mode                :    3;  /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_din4_mode                :    3;  /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_din5_mode                :    3;  /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_din6_mode                :    3;  /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_din7_mode                :    3;  /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_dins_mode                :    3;  /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_mode;
+    union {
+        struct {
+            uint32_t smem_din0_num                 :    2;  /*SPI_D input delay number.*/
+            uint32_t smem_din1_num                 :    2;  /*SPI_Q input delay number.*/
+            uint32_t smem_din2_num                 :    2;  /*SPI_WP input delay number.*/
+            uint32_t smem_din3_num                 :    2;  /*SPI_HD input delay number.*/
+            uint32_t smem_din4_num                 :    2;  /*SPI_IO4 input delay number.*/
+            uint32_t smem_din5_num                 :    2;  /*SPI_IO5 input delay number.*/
+            uint32_t smem_din6_num                 :    2;  /*SPI_IO6 input delay number.*/
+            uint32_t smem_din7_num                 :    2;  /*SPI_IO7 input delay number.*/
+            uint32_t smem_dins_num                 :    2;  /*SPI_DQS input delay number.*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_din_num;
+    union {
+        struct {
+            uint32_t smem_dout0_mode               :    1;  /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_dout1_mode               :    1;  /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_dout2_mode               :    1;  /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_dout3_mode               :    1;  /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_dout4_mode               :    1;  /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_dout5_mode               :    1;  /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_dout6_mode               :    1;  /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_dout7_mode               :    1;  /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t smem_douts_mode               :    1;  /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_dout_mode;
+    union {
+        struct {
+            uint32_t ecc_err_int_num               :    8;  /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t fmem_ecc_err_int_en           :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } ecc_ctrl;
+    uint32_t ecc_err_addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;  /*reserved*/
+            uint32_t ecc_data_err_bit              :    7;  /*It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
+            uint32_t ecc_chk_err_bit               :    3;  /*When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte.*/
+            uint32_t ecc_byte_err                  :    1;  /*It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
+            uint32_t ecc_err_cnt                   :    8;  /*This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when  SPI_MEM_ECC_ERR_INT_CLR bit is set. */
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } ecc_err_bit;
+    uint32_t reserved_d8;
+    union {
+        struct {
+            uint32_t smem_cs_setup                 :    1;  /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
+            uint32_t smem_cs_hold                  :    1;  /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
+            uint32_t smem_cs_setup_time            :    5;  /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
+            uint32_t smem_cs_hold_time             :    5;  /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
+            uint32_t smem_ecc_cs_hold_time         :    3;  /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM.*/
+            uint32_t smem_ecc_skip_page_corner     :    1;  /*1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM.*/
+            uint32_t smem_ecc_16to18_byte_en       :    1;  /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM.*/
+            uint32_t reserved17                    :    7;  /*reserved*/
+            uint32_t smem_ecc_err_int_en           :    1;  /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
+            uint32_t smem_cs_hold_delay            :    6;  /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_ac;
+    union {
+        struct {
+            uint32_t fmem_ddr_en                   :    1;  /*1: in ddr mode,  0 in sdr mode*/
+            uint32_t fmem_var_dummy                :    1;  /*Set the bit to enable variable dummy cycle in DDR mode.*/
+            uint32_t fmem_ddr_rdat_swp             :    1;  /*Set the bit to reorder RX data of the word in DDR mode.*/
+            uint32_t fmem_ddr_wdat_swp             :    1;  /*Set the bit to swap TX data of a word in DDR mode.*/
+            uint32_t fmem_ddr_cmd_dis              :    1;  /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
+            uint32_t fmem_outminbytelen            :    7;  /*It is the minimum output data length in the panda device.*/
+            uint32_t fmem_tx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.*/
+            uint32_t fmem_rx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.*/
+            uint32_t fmem_usr_ddr_dqs_thd          :    7;  /*The delay number of data strobe which from memory based on SPI_CLK.*/
+            uint32_t fmem_ddr_dqs_loop             :    1;  /*1: Use internal signal  as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
+            uint32_t fmem_ddr_dqs_loop_mode        :    1;  /*When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is not active.*/
+            uint32_t reserved23                    :    1;  /*reserved*/
+            uint32_t fmem_clk_diff_en              :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
+            uint32_t fmem_hyperbus_mode            :    1;  /*Set this bit to enable the SPI HyperBus mode.*/
+            uint32_t fmem_dqs_ca_in                :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
+            uint32_t fmem_hyperbus_dummy_2x        :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
+            uint32_t fmem_clk_diff_inv             :    1;  /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
+            uint32_t fmem_octa_ram_addr            :    1;  /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
+            uint32_t fmem_hyperbus_ca              :    1;  /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } ddr;
+    union {
+        struct {
+            uint32_t smem_ddr_en                   :    1;  /*1: in ddr mode,  0 in sdr mode*/
+            uint32_t smem_var_dummy                :    1;  /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
+            uint32_t smem_ddr_rdat_swp             :    1;  /*Set the bit to reorder rx data of the word in spi ddr mode.*/
+            uint32_t smem_ddr_wdat_swp             :    1;  /*Set the bit to reorder tx data of the word in spi ddr mode.*/
+            uint32_t smem_ddr_cmd_dis              :    1;  /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
+            uint32_t smem_outminbytelen            :    7;  /*It is the minimum output data length in the ddr psram.*/
+            uint32_t smem_tx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM.*/
+            uint32_t smem_rx_ddr_msk_en            :    1;  /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM.*/
+            uint32_t smem_usr_ddr_dqs_thd          :    7;  /*The delay number of data strobe which from memory based on SPI_CLK.*/
+            uint32_t smem_ddr_dqs_loop             :    1;  /*1: Use internal signal  as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
+            uint32_t smem_ddr_dqs_loop_mode        :    1;  /*When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK  as data strobe. 0: Use internal ~SPI_CLK  as data strobe. Otherwise this bit is not active.*/
+            uint32_t reserved23                    :    1;  /*reserved*/
+            uint32_t smem_clk_diff_en              :    1;  /*Set this bit to enable the differential SPI_CLK#.*/
+            uint32_t smem_hyperbus_mode            :    1;  /*Set this bit to enable the SPI HyperBus mode.*/
+            uint32_t smem_dqs_ca_in                :    1;  /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
+            uint32_t smem_hyperbus_dummy_2x        :    1;  /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
+            uint32_t smem_clk_diff_inv             :    1;  /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
+            uint32_t smem_octa_ram_addr            :    1;  /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
+            uint32_t smem_hyperbus_ca              :    1;  /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
+            uint32_t reserved31                    :    1;  /*reserved*/
+        };
+        uint32_t val;
+    } spi_smem_ddr;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
+            uint32_t reserved1                     :    31;  /*reserved*/
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t core_clk_sel                  :    2;  /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz.  2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL:  0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz.  2: MSPI_CORE_CLK 160MHz. 3: Not used. */
+            uint32_t reserved2                     :    30;  /*reserved*/
+        };
+        uint32_t val;
+    } core_clk_sel;
+    union {
+        struct {
+            uint32_t per_end_en                    :    1;  /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_en                    :    1;  /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t total_trans_end_en            :    1;  /*The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
+            uint32_t brown_out_en                  :    1;  /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t ecc_err_en                    :    1;  /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t per_end_int_clr               :    1;  /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_int_clr               :    1;  /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t total_trans_end_int_clr       :    1;  /*The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
+            uint32_t brown_out_int_clr             :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t ecc_err_int_clr               :    1;  /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t per_end_int_raw               :    1;  /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
+            uint32_t pes_end_int_raw               :    1;  /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
+            uint32_t total_trans_end_int_raw       :    1;  /*The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success.  0: Others.*/
+            uint32_t brown_out_int_raw             :    1;  /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
+            uint32_t ecc_err_int_raw               :    1;  /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and  APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and  APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and  APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t per_end_int_st                :    1;  /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
+            uint32_t pes_end_int_st                :    1;  /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
+            uint32_t total_trans_end_int_st        :    1;  /*The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
+            uint32_t brown_out_int_st              :    1;  /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
+            uint32_t ecc_err_int_st                :    1;  /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
+            uint32_t reserved5                     :    27;  /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t reg_smem_spiclk_fun_drv       :    2;  /*The driver of SPI_CLK PAD  is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM.*/
+            uint32_t fmem_spiclk_fun_drv           :    2;  /*The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash.*/
+            uint32_t reg_spiclk_pad_drv_ctl_en     :    1;  /*SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD  is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD  is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD.*/
+            uint32_t date                          :    23;  /*SPI register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_STRUCT_H_ */
diff --git a/components/soc/esp32s3/register/soc/spi_reg.h b/components/soc/esp32s3/register/soc/spi_reg.h
new file mode 100644
index 00000000000..a5870547124
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/spi_reg.h
@@ -0,0 +1,1749 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_REG_H_
+#define _SOC_SPI_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x0)
+/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when the bit is set.
+ The bit will be cleared once the operation done.1: enable 0: disable. Can not b
+e changed by CONF_buf..*/
+#define SPI_USR    (BIT(24))
+#define SPI_USR_M  (BIT(24))
+#define SPI_USR_V  0x1
+#define SPI_USR_S  24
+/* SPI_UPDATE : WT ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to synchronize SPI registers from APB clock domain into SPI module
+clock domain, which is only used in SPI master mode..*/
+#define SPI_UPDATE    (BIT(23))
+#define SPI_UPDATE_M  (BIT(23))
+#define SPI_UPDATE_V  0x1
+#define SPI_UPDATE_S  23
+/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: Define the APB cycles of  SPI_CONF state. Can be configured in CONF state..*/
+#define SPI_CONF_BITLEN    0x0003FFFF
+#define SPI_CONF_BITLEN_M  ((SPI_CONF_BITLEN_V)<<(SPI_CONF_BITLEN_S))
+#define SPI_CONF_BITLEN_V  0x3FFFF
+#define SPI_CONF_BITLEN_S  0
+
+#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x4)
+/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: Address to slave. Can be configured in CONF state..*/
+#define SPI_USR_ADDR_VALUE    0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_S  0
+
+#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x8)
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26:25] ;default: 2'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be con
+figured in CONF state..*/
+#define SPI_WR_BIT_ORDER    0x00000003
+#define SPI_WR_BIT_ORDER_M  ((SPI_WR_BIT_ORDER_V)<<(SPI_WR_BIT_ORDER_S))
+#define SPI_WR_BIT_ORDER_V  0x3
+#define SPI_WR_BIT_ORDER_S  25
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[24:23] ;default: 2'b0 ; */
+/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF s
+tate..*/
+#define SPI_RD_BIT_ORDER    0x00000003
+#define SPI_RD_BIT_ORDER_M  ((SPI_RD_BIT_ORDER_V)<<(SPI_RD_BIT_ORDER_S))
+#define SPI_RD_BIT_ORDER_V  0x3
+#define SPI_RD_BIT_ORDER_S  23
+/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high, 0: output low.  C
+an be configured in CONF state..*/
+#define SPI_WP_POL    (BIT(21))
+#define SPI_WP_POL_M  (BIT(21))
+#define SPI_WP_POL_V  0x1
+#define SPI_WP_POL_S  21
+/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be co
+nfigured in CONF state..*/
+#define SPI_HOLD_POL    (BIT(20))
+#define SPI_HOLD_POL_M  (BIT(20))
+#define SPI_HOLD_POL_V  0x1
+#define SPI_HOLD_POL_S  20
+/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_D_POL    (BIT(19))
+#define SPI_D_POL_M  (BIT(19))
+#define SPI_D_POL_V  0x1
+#define SPI_D_POL_S  19
+/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+CONF state..*/
+#define SPI_Q_POL    (BIT(18))
+#define SPI_Q_POL_M  (BIT(18))
+#define SPI_Q_POL_V  0x1
+#define SPI_Q_POL_S  18
+/* SPI_FREAD_OCT : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  C
+an be configured in CONF state..*/
+#define SPI_FREAD_OCT    (BIT(16))
+#define SPI_FREAD_OCT_M  (BIT(16))
+#define SPI_FREAD_OCT_V  0x1
+#define SPI_FREAD_OCT_S  16
+/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  C
+an be configured in CONF state..*/
+#define SPI_FREAD_QUAD    (BIT(15))
+#define SPI_FREAD_QUAD_M  (BIT(15))
+#define SPI_FREAD_QUAD_V  0x1
+#define SPI_FREAD_QUAD_S  15
+/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. C
+an be configured in CONF state..*/
+#define SPI_FREAD_DUAL    (BIT(14))
+#define SPI_FREAD_DUAL_M  (BIT(14))
+#define SPI_FREAD_DUAL_V  0x1
+#define SPI_FREAD_DUAL_S  14
+/* SPI_FCMD_OCT : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Apply 8 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_OCT    (BIT(10))
+#define SPI_FCMD_OCT_M  (BIT(10))
+#define SPI_FCMD_OCT_V  0x1
+#define SPI_FCMD_OCT_S  10
+/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_QUAD    (BIT(9))
+#define SPI_FCMD_QUAD_M  (BIT(9))
+#define SPI_FCMD_QUAD_V  0x1
+#define SPI_FCMD_QUAD_S  9
+/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable. Can be configured in C
+ONF state..*/
+#define SPI_FCMD_DUAL    (BIT(8))
+#define SPI_FCMD_DUAL_M  (BIT(8))
+#define SPI_FCMD_DUAL_V  0x1
+#define SPI_FCMD_DUAL_S  8
+/* SPI_FADDR_OCT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_OCT    (BIT(7))
+#define SPI_FADDR_OCT_M  (BIT(7))
+#define SPI_FADDR_OCT_V  0x1
+#define SPI_FADDR_OCT_S  7
+/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_QUAD    (BIT(6))
+#define SPI_FADDR_QUAD_M  (BIT(6))
+#define SPI_FADDR_QUAD_V  0x1
+#define SPI_FADDR_QUAD_S  6
+/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+ state..*/
+#define SPI_FADDR_DUAL    (BIT(5))
+#define SPI_FADDR_DUAL_M  (BIT(5))
+#define SPI_FADDR_DUAL_V  0x1
+#define SPI_FADDR_DUAL_S  5
+/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phas
+e, the FSPI bus signals are output. Can be configured in CONF state..*/
+#define SPI_DUMMY_OUT    (BIT(3))
+#define SPI_DUMMY_OUT_M  (BIT(3))
+#define SPI_DUMMY_OUT_V  0x1
+#define SPI_DUMMY_OUT_S  3
+
+#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0xC)
+/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst
+em clock. Can be configured in CONF state..*/
+#define SPI_CLK_EQU_SYSCLK    (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_V  0x1
+#define SPI_CLK_EQU_SYSCLK_S  31
+/* SPI_CLKDIV_PRE : R/W ;bitpos:[21:18] ;default: 4'b0 ; */
+/*description: In the master mode it is pre-divider of spi_clk.  Can be configured in CONF stat
+e..*/
+#define SPI_CLKDIV_PRE    0x0000000F
+#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
+#define SPI_CLKDIV_PRE_V  0xF
+#define SPI_CLKDIV_PRE_S  18
+/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
+/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/
+(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state..*/
+#define SPI_CLKCNT_N    0x0000003F
+#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
+#define SPI_CLKCNT_N_V  0x3F
+#define SPI_CLKCNT_N_S  12
+/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
+/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+must be 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_H    0x0000003F
+#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
+#define SPI_CLKCNT_H_V  0x3F
+#define SPI_CLKCNT_H_S  6
+/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must b
+e 0. Can be configured in CONF state..*/
+#define SPI_CLKCNT_L    0x0000003F
+#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
+#define SPI_CLKCNT_L_V  0x3F
+#define SPI_CLKCNT_L_S  0
+
+#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x10)
+/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_COMMAND    (BIT(31))
+#define SPI_USR_COMMAND_M  (BIT(31))
+#define SPI_USR_COMMAND_V  0x1
+#define SPI_USR_COMMAND_S  31
+/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_ADDR    (BIT(30))
+#define SPI_USR_ADDR_M  (BIT(30))
+#define SPI_USR_ADDR_V  0x1
+#define SPI_USR_ADDR_S  30
+/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation. Can be configured in CONF state
+..*/
+#define SPI_USR_DUMMY    (BIT(29))
+#define SPI_USR_DUMMY_M  (BIT(29))
+#define SPI_USR_DUMMY_V  0x1
+#define SPI_USR_DUMMY_S  29
+/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation. Can be configured in CONF s
+tate..*/
+#define SPI_USR_MISO    (BIT(28))
+#define SPI_USR_MISO_M  (BIT(28))
+#define SPI_USR_MISO_V  0x1
+#define SPI_USR_MISO_S  28
+/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation. Can be configured in CONF
+state..*/
+#define SPI_USR_MOSI    (BIT(27))
+#define SPI_USR_MOSI_M  (BIT(27))
+#define SPI_USR_MOSI_V  0x1
+#define SPI_USR_MOSI_S  27
+/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable. Can be configured in
+ CONF state..*/
+#define SPI_USR_DUMMY_IDLE    (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_USR_DUMMY_IDLE_V  0x1
+#define SPI_USR_DUMMY_IDLE_S  26
+/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enabl
+e 0: disable.  Can be configured in CONF state..*/
+#define SPI_USR_MOSI_HIGHPART    (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_V  0x1
+#define SPI_USR_MOSI_HIGHPART_S  25
+/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+ 0: disable. Can be configured in CONF state..*/
+#define SPI_USR_MISO_HIGHPART    (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_USR_MISO_HIGHPART_V  0x1
+#define SPI_USR_MISO_HIGHPART_S  24
+/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set the bit to enable 3-line half duplex communication mosi and miso signals sha
+re the same pin. 1: enable 0: disable. Can be configured in CONF state..*/
+#define SPI_SIO    (BIT(17))
+#define SPI_SIO_M  (BIT(17))
+#define SPI_SIO_V  0x1
+#define SPI_SIO_S  17
+/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+will continue. 0: The seg-trans will end after the current SPI seg-trans or this
+ is not seg-trans mode. Can be configured in CONF state..*/
+#define SPI_USR_CONF_NXT    (BIT(15))
+#define SPI_USR_CONF_NXT_M  (BIT(15))
+#define SPI_USR_CONF_NXT_V  0x1
+#define SPI_USR_CONF_NXT_S  15
+/* SPI_FWRITE_OCT : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 8 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_OCT    (BIT(14))
+#define SPI_FWRITE_OCT_M  (BIT(14))
+#define SPI_FWRITE_OCT_V  0x1
+#define SPI_FWRITE_OCT_S  14
+/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_QUAD    (BIT(13))
+#define SPI_FWRITE_QUAD_M  (BIT(13))
+#define SPI_FWRITE_QUAD_V  0x1
+#define SPI_FWRITE_QUAD_S  13
+/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals. Can be configured in CO
+NF state..*/
+#define SPI_FWRITE_DUAL    (BIT(12))
+#define SPI_FWRITE_DUAL_M  (BIT(12))
+#define SPI_FWRITE_DUAL_V  0x1
+#define SPI_FWRITE_DUAL_S  12
+/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Ca
+n be configured in CONF state..*/
+#define SPI_CK_OUT_EDGE    (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_CK_OUT_EDGE_V  0x1
+#define SPI_CK_OUT_EDGE_S  9
+/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
+= !spi_ck_i. 1:rsck = spi_ck_i..*/
+#define SPI_RSCK_I_EDGE    (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (BIT(8))
+#define SPI_RSCK_I_EDGE_V  0x1
+#define SPI_RSCK_I_EDGE_S  8
+/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_CS_SETUP    (BIT(7))
+#define SPI_CS_SETUP_M  (BIT(7))
+#define SPI_CS_SETUP_V  0x1
+#define SPI_CS_SETUP_S  7
+/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be config
+ured in CONF state..*/
+#define SPI_CS_HOLD    (BIT(6))
+#define SPI_CS_HOLD_M  (BIT(6))
+#define SPI_CS_HOLD_V  0x1
+#define SPI_CS_HOLD_S  6
+/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
+= spi_ck_i. 1:tsck = !spi_ck_i..*/
+#define SPI_TSCK_I_EDGE    (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (BIT(5))
+#define SPI_TSCK_I_EDGE_V  0x1
+#define SPI_TSCK_I_EDGE_S  5
+/* SPI_OPI_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others
+. Can be configured in CONF state..*/
+#define SPI_OPI_MODE    (BIT(4))
+#define SPI_OPI_MODE_M  (BIT(4))
+#define SPI_OPI_MODE_V  0x1
+#define SPI_OPI_MODE_S  4
+/* SPI_QPI_MODE : R/W/SS/SC ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others
+. Can be configured in CONF state..*/
+#define SPI_QPI_MODE    (BIT(3))
+#define SPI_QPI_MODE_M  (BIT(3))
+#define SPI_QPI_MODE_V  0x1
+#define SPI_QPI_MODE_S  3
+/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set the bit to enable full duplex communication. 1: enable 0: disable. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUTDIN    (BIT(0))
+#define SPI_DOUTDIN_M  (BIT(0))
+#define SPI_DOUTDIN_V  0x1
+#define SPI_DOUTDIN_S  0
+
+#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x14)
+/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_ADDR_BITLEN    0x0000001F
+#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
+#define SPI_USR_ADDR_BITLEN_V  0x1F
+#define SPI_USR_ADDR_BITLEN_S  27
+/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */
+/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+ Can be configured in CONF state..*/
+#define SPI_CS_HOLD_TIME    0x0000001F
+#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
+#define SPI_CS_HOLD_TIME_V  0x1F
+#define SPI_CS_HOLD_TIME_S  22
+/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
+/*description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setu
+p bit. Can be configured in CONF state..*/
+#define SPI_CS_SETUP_TIME    0x0000001F
+#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
+#define SPI_CS_SETUP_TIME_V  0x1F
+#define SPI_CS_SETUP_TIME_S  17
+/* SPI_MST_WFULL_ERR_END_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+ FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
+ in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_WFULL_ERR_END_EN    (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_M  (BIT(16))
+#define SPI_MST_WFULL_ERR_END_EN_V  0x1
+#define SPI_MST_WFULL_ERR_END_EN_S  16
+/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
+/*description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_
+num-1). Can be configured in CONF state..*/
+#define SPI_USR_DUMMY_CYCLELEN    0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
+#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x18)
+/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1). Ca
+n be configured in CONF state..*/
+#define SPI_USR_COMMAND_BITLEN    0x0000000F
+#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
+#define SPI_USR_COMMAND_BITLEN_V  0xF
+#define SPI_USR_COMMAND_BITLEN_S  28
+/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
+aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
+r is valid in GP-SPI master FD/HD-mode..*/
+#define SPI_MST_REMPTY_ERR_END_EN    (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_M  (BIT(27))
+#define SPI_MST_REMPTY_ERR_END_EN_V  0x1
+#define SPI_MST_REMPTY_ERR_END_EN_S  27
+/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command. Can be configured in CONF state..*/
+#define SPI_USR_COMMAND_VALUE    0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
+#define SPI_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_USR_COMMAND_VALUE_S  0
+
+#define SPI_MS_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x1C)
+/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: The value of these bits is the configured SPI transmission data bit length in ma
+ster mode DMA controlled transfer or CPU controlled transfer. The value is also
+the configured bit length in slave mode DMA RX controlled transfer. The register
+ value shall be (bit_num-1). Can be configured in CONF state..*/
+#define SPI_MS_DATA_BITLEN    0x0003FFFF
+#define SPI_MS_DATA_BITLEN_M  ((SPI_MS_DATA_BITLEN_V)<<(SPI_MS_DATA_BITLEN_S))
+#define SPI_MS_DATA_BITLEN_V  0x3FFFF
+#define SPI_MS_DATA_BITLEN_S  0
+
+#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x20)
+/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0
+:  spi quad input swap disable. Can be configured in CONF state..*/
+#define SPI_QUAD_DIN_PIN_SWAP    (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set. Can be configured in CONF state..*/
+#define SPI_CS_KEEP_ACTIVE    (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_V  0x1
+#define SPI_CS_KEEP_ACTIVE_S  30
+/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle. Can be c
+onfigured in CONF state..*/
+#define SPI_CK_IDLE_EDGE    (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (BIT(29))
+#define SPI_CK_IDLE_EDGE_V  0x1
+#define SPI_CK_IDLE_EDGE_S  29
+/* SPI_DQS_IDLE_EDGE : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The default value of spi_dqs. Can be configured in CONF state..*/
+#define SPI_DQS_IDLE_EDGE    (BIT(24))
+#define SPI_DQS_IDLE_EDGE_M  (BIT(24))
+#define SPI_DQS_IDLE_EDGE_V  0x1
+#define SPI_DQS_IDLE_EDGE_S  24
+/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: spi slave input cs polarity select. 1: inv  0: not change. Can be configured in
+CONF state..*/
+#define SPI_SLAVE_CS_POL    (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (BIT(23))
+#define SPI_SLAVE_CS_POL_V  0x1
+#define SPI_SLAVE_CS_POL_S  23
+/* SPI_CMD_DTR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/
+4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be confi
+gured in CONF state..*/
+#define SPI_CMD_DTR_EN    (BIT(19))
+#define SPI_CMD_DTR_EN_M  (BIT(19))
+#define SPI_CMD_DTR_EN_V  0x1
+#define SPI_CMD_DTR_EN_S  19
+/* SPI_ADDR_DTR_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2
+/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be co
+nfigured in CONF state..*/
+#define SPI_ADDR_DTR_EN    (BIT(18))
+#define SPI_ADDR_DTR_EN_M  (BIT(18))
+#define SPI_ADDR_DTR_EN_V  0x1
+#define SPI_ADDR_DTR_EN_S  18
+/* SPI_DATA_DTR_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including mas
+ter 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR m
+ode. Can be configured in CONF state..*/
+#define SPI_DATA_DTR_EN    (BIT(17))
+#define SPI_DATA_DTR_EN_M  (BIT(17))
+#define SPI_DATA_DTR_EN_V  0x1
+#define SPI_DATA_DTR_EN_S  17
+/* SPI_CLK_DATA_DTR_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master D
+TR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19. .*/
+#define SPI_CLK_DATA_DTR_EN    (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_M  (BIT(16))
+#define SPI_CLK_DATA_DTR_EN_V  0x1
+#define SPI_CLK_DATA_DTR_EN_S  16
+/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */
+/*description: In the master mode the bits are the polarity of spi cs line, the value is equiva
+lent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state..*/
+#define SPI_MASTER_CS_POL    0x0000003F
+#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
+#define SPI_MASTER_CS_POL_V  0x3F
+#define SPI_MASTER_CS_POL_S  7
+/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state..*/
+#define SPI_CK_DIS    (BIT(6))
+#define SPI_CK_DIS_M  (BIT(6))
+#define SPI_CK_DIS_V  0x1
+#define SPI_CK_DIS_S  6
+/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS5_DIS    (BIT(5))
+#define SPI_CS5_DIS_M  (BIT(5))
+#define SPI_CS5_DIS_V  0x1
+#define SPI_CS5_DIS_S  5
+/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS4_DIS    (BIT(4))
+#define SPI_CS4_DIS_M  (BIT(4))
+#define SPI_CS4_DIS_V  0x1
+#define SPI_CS4_DIS_S  4
+/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS3_DIS    (BIT(3))
+#define SPI_CS3_DIS_M  (BIT(3))
+#define SPI_CS3_DIS_V  0x1
+#define SPI_CS3_DIS_S  3
+/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS2_DIS    (BIT(2))
+#define SPI_CS2_DIS_M  (BIT(2))
+#define SPI_CS2_DIS_V  0x1
+#define SPI_CS2_DIS_S  2
+/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS1_DIS    (BIT(1))
+#define SPI_CS1_DIS_M  (BIT(1))
+#define SPI_CS1_DIS_V  0x1
+#define SPI_CS1_DIS_S  1
+/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca
+n be configured in CONF state..*/
+#define SPI_CS0_DIS    (BIT(0))
+#define SPI_CS0_DIS_M  (BIT(0))
+#define SPI_CS0_DIS_V  0x1
+#define SPI_CS0_DIS_S  0
+
+#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x24)
+/* SPI_TIMING_HCLK_ACTIVE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1:enable hclk in SPI input timing module.  0: disable it. Can be configured in C
+ONF state..*/
+#define SPI_TIMING_HCLK_ACTIVE    (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_M  (BIT(16))
+#define SPI_TIMING_HCLK_ACTIVE_V  0x1
+#define SPI_TIMING_HCLK_ACTIVE_S  16
+/* SPI_DIN7_MODE : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN7_MODE    0x00000003
+#define SPI_DIN7_MODE_M  ((SPI_DIN7_MODE_V)<<(SPI_DIN7_MODE_S))
+#define SPI_DIN7_MODE_V  0x3
+#define SPI_DIN7_MODE_S  14
+/* SPI_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN6_MODE    0x00000003
+#define SPI_DIN6_MODE_M  ((SPI_DIN6_MODE_V)<<(SPI_DIN6_MODE_S))
+#define SPI_DIN6_MODE_V  0x3
+#define SPI_DIN6_MODE_S  12
+/* SPI_DIN5_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN5_MODE    0x00000003
+#define SPI_DIN5_MODE_M  ((SPI_DIN5_MODE_V)<<(SPI_DIN5_MODE_S))
+#define SPI_DIN5_MODE_V  0x3
+#define SPI_DIN5_MODE_S  10
+/* SPI_DIN4_MODE : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN4_MODE    0x00000003
+#define SPI_DIN4_MODE_M  ((SPI_DIN4_MODE_V)<<(SPI_DIN4_MODE_S))
+#define SPI_DIN4_MODE_V  0x3
+#define SPI_DIN4_MODE_S  8
+/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN3_MODE    0x00000003
+#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
+#define SPI_DIN3_MODE_V  0x3
+#define SPI_DIN3_MODE_S  6
+/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN2_MODE    0x00000003
+#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
+#define SPI_DIN2_MODE_V  0x3
+#define SPI_DIN2_MODE_S  4
+/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN1_MODE    0x00000003
+#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
+#define SPI_DIN1_MODE_V  0x3
+#define SPI_DIN1_MODE_S  2
+/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: input without delay
+ed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+ input with the spi_clk. Can be configured in CONF state..*/
+#define SPI_DIN0_MODE    0x00000003
+#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
+#define SPI_DIN0_MODE_V  0x3
+#define SPI_DIN0_MODE_S  0
+
+#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x28)
+/* SPI_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN7_NUM    0x00000003
+#define SPI_DIN7_NUM_M  ((SPI_DIN7_NUM_V)<<(SPI_DIN7_NUM_S))
+#define SPI_DIN7_NUM_V  0x3
+#define SPI_DIN7_NUM_S  14
+/* SPI_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN6_NUM    0x00000003
+#define SPI_DIN6_NUM_M  ((SPI_DIN6_NUM_V)<<(SPI_DIN6_NUM_S))
+#define SPI_DIN6_NUM_V  0x3
+#define SPI_DIN6_NUM_S  12
+/* SPI_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN5_NUM    0x00000003
+#define SPI_DIN5_NUM_M  ((SPI_DIN5_NUM_V)<<(SPI_DIN5_NUM_S))
+#define SPI_DIN5_NUM_V  0x3
+#define SPI_DIN5_NUM_S  10
+/* SPI_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN4_NUM    0x00000003
+#define SPI_DIN4_NUM_M  ((SPI_DIN4_NUM_V)<<(SPI_DIN4_NUM_S))
+#define SPI_DIN4_NUM_V  0x3
+#define SPI_DIN4_NUM_S  8
+/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN3_NUM    0x00000003
+#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
+#define SPI_DIN3_NUM_V  0x3
+#define SPI_DIN3_NUM_S  6
+/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN2_NUM    0x00000003
+#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
+#define SPI_DIN2_NUM_V  0x3
+#define SPI_DIN2_NUM_S  4
+/* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN1_NUM    0x00000003
+#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
+#define SPI_DIN1_NUM_V  0x3
+#define SPI_DIN1_NUM_S  2
+/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+ 1: delayed by 2 cycles,...  Can be configured in CONF state..*/
+#define SPI_DIN0_NUM    0x00000003
+#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
+#define SPI_DIN0_NUM_V  0x3
+#define SPI_DIN0_NUM_S  0
+
+#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x2C)
+/* SPI_D_DQS_MODE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The output signal SPI_DQS is delayed by the SPI module clock, 0: output without
+delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+be configured in CONF state..*/
+#define SPI_D_DQS_MODE    (BIT(8))
+#define SPI_D_DQS_MODE_M  (BIT(8))
+#define SPI_D_DQS_MODE_V  0x1
+#define SPI_D_DQS_MODE_S  8
+/* SPI_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT7_MODE    (BIT(7))
+#define SPI_DOUT7_MODE_M  (BIT(7))
+#define SPI_DOUT7_MODE_V  0x1
+#define SPI_DOUT7_MODE_S  7
+/* SPI_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT6_MODE    (BIT(6))
+#define SPI_DOUT6_MODE_M  (BIT(6))
+#define SPI_DOUT6_MODE_V  0x1
+#define SPI_DOUT6_MODE_S  6
+/* SPI_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT5_MODE    (BIT(5))
+#define SPI_DOUT5_MODE_M  (BIT(5))
+#define SPI_DOUT5_MODE_V  0x1
+#define SPI_DOUT5_MODE_S  5
+/* SPI_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT4_MODE    (BIT(4))
+#define SPI_DOUT4_MODE_M  (BIT(4))
+#define SPI_DOUT4_MODE_V  0x1
+#define SPI_DOUT4_MODE_S  4
+/* SPI_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT3_MODE    (BIT(3))
+#define SPI_DOUT3_MODE_M  (BIT(3))
+#define SPI_DOUT3_MODE_V  0x1
+#define SPI_DOUT3_MODE_S  3
+/* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT2_MODE    (BIT(2))
+#define SPI_DOUT2_MODE_M  (BIT(2))
+#define SPI_DOUT2_MODE_V  0x1
+#define SPI_DOUT2_MODE_S  2
+/* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT1_MODE    (BIT(1))
+#define SPI_DOUT1_MODE_M  (BIT(1))
+#define SPI_DOUT1_MODE_V  0x1
+#define SPI_DOUT1_MODE_S  1
+/* SPI_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The output signal $n is delayed by the SPI module clock, 0: output without delay
+ed, 1: output delay for a SPI module clock cycle at its negative edge. Can be co
+nfigured in CONF state..*/
+#define SPI_DOUT0_MODE    (BIT(0))
+#define SPI_DOUT0_MODE_M  (BIT(0))
+#define SPI_DOUT0_MODE_V  0x1
+#define SPI_DOUT0_MODE_S  0
+
+#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x30)
+/* SPI_DMA_AFIFO_RST : WT ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
+DMA controlled mode transfer..*/
+#define SPI_DMA_AFIFO_RST    (BIT(31))
+#define SPI_DMA_AFIFO_RST_M  (BIT(31))
+#define SPI_DMA_AFIFO_RST_V  0x1
+#define SPI_DMA_AFIFO_RST_S  31
+/* SPI_BUF_AFIFO_RST : WT ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+ controlled mode transfer and master mode transfer..*/
+#define SPI_BUF_AFIFO_RST    (BIT(30))
+#define SPI_BUF_AFIFO_RST_M  (BIT(30))
+#define SPI_BUF_AFIFO_RST_V  0x1
+#define SPI_BUF_AFIFO_RST_S  30
+/* SPI_RX_AFIFO_RST : WT ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+slave mode transfer..*/
+#define SPI_RX_AFIFO_RST    (BIT(29))
+#define SPI_RX_AFIFO_RST_M  (BIT(29))
+#define SPI_RX_AFIFO_RST_V  0x1
+#define SPI_RX_AFIFO_RST_S  29
+/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable SPI DMA controlled send data mode..*/
+#define SPI_DMA_TX_ENA    (BIT(28))
+#define SPI_DMA_TX_ENA_M  (BIT(28))
+#define SPI_DMA_TX_ENA_V  0x1
+#define SPI_DMA_TX_ENA_S  28
+/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Set this bit to enable SPI DMA controlled receive data mode..*/
+#define SPI_DMA_RX_ENA    (BIT(27))
+#define SPI_DMA_RX_ENA_M  (BIT(27))
+#define SPI_DMA_RX_ENA_V  0x1
+#define SPI_DMA_RX_ENA_S  27
+/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal t
+o the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_d
+ma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_don
+e in seg-trans..*/
+#define SPI_RX_EOF_EN    (BIT(21))
+#define SPI_RX_EOF_EN_M  (BIT(21))
+#define SPI_RX_EOF_EN_V  0x1
+#define SPI_RX_EOF_EN_S  21
+/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_e
+mpty_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN    (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M  (BIT(20))
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S  20
+/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full
+_vld is cleared by spi_trans_done..*/
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN    (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M  (BIT(19))
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V  0x1
+#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S  19
+/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable..*/
+#define SPI_DMA_SLV_SEG_TRANS_EN    (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_M  (BIT(18))
+#define SPI_DMA_SLV_SEG_TRANS_EN_V  0x1
+#define SPI_DMA_SLV_SEG_TRANS_EN_S  18
+/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving dat
+a. 0: DMA RX FIFO is ready for receiving data..*/
+#define SPI_DMA_INFIFO_FULL    (BIT(1))
+#define SPI_DMA_INFIFO_FULL_M  (BIT(1))
+#define SPI_DMA_INFIFO_FULL_V  0x1
+#define SPI_DMA_INFIFO_FULL_S  1
+/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data.
+ 0: DMA TX FIFO is ready for sending data..*/
+#define SPI_DMA_OUTFIFO_EMPTY    (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (BIT(0))
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_S  0
+
+#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x34)
+/* SPI_APP1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ENA    (BIT(20))
+#define SPI_APP1_INT_ENA_M  (BIT(20))
+#define SPI_APP1_INT_ENA_V  0x1
+#define SPI_APP1_INT_ENA_S  20
+/* SPI_APP2_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ENA    (BIT(19))
+#define SPI_APP2_INT_ENA_M  (BIT(19))
+#define SPI_APP2_INT_ENA_V  0x1
+#define SPI_APP2_INT_ENA_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S  17
+/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ENA    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ENA_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ENA_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ENA    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ENA_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ENA_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S  13
+/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ENA    (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ENA_V  0x1
+#define SPI_TRANS_DONE_INT_ENA_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ENA    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ENA_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ENA    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ENA_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ENA    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ENA_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ENA    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ENA_S  8
+/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ENA    (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ENA_V  0x1
+#define SPI_SLV_CMDA_INT_ENA_S  7
+/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ENA    (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ENA_V  0x1
+#define SPI_SLV_CMD9_INT_ENA_S  6
+/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ENA    (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ENA_V  0x1
+#define SPI_SLV_CMD8_INT_ENA_S  5
+/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ENA    (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ENA_V  0x1
+#define SPI_SLV_CMD7_INT_ENA_S  4
+/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ENA    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EN_QPI_INT_ENA_S  3
+/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ENA    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ENA_V  0x1
+#define SPI_SLV_EX_QPI_INT_ENA_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S  0
+
+#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x38)
+/* SPI_APP1_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_CLR    (BIT(20))
+#define SPI_APP1_INT_CLR_M  (BIT(20))
+#define SPI_APP1_INT_CLR_V  0x1
+#define SPI_APP1_INT_CLR_S  20
+/* SPI_APP2_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_CLR    (BIT(19))
+#define SPI_APP2_INT_CLR_M  (BIT(19))
+#define SPI_APP2_INT_CLR_V  0x1
+#define SPI_APP2_INT_CLR_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S  17
+/* SPI_SLV_CMD_ERR_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_CLR    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_CLR_V  0x1
+#define SPI_SLV_CMD_ERR_INT_CLR_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S  15
+/* SPI_SEG_MAGIC_ERR_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_CLR    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_CLR_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_CLR_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S  13
+/* SPI_TRANS_DONE_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_CLR    (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_CLR_V  0x1
+#define SPI_TRANS_DONE_INT_CLR_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_CLR    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_CLR_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_CLR    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_CLR_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_CLR    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_CLR_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_CLR    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_CLR_S  8
+/* SPI_SLV_CMDA_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_CLR    (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_CLR_V  0x1
+#define SPI_SLV_CMDA_INT_CLR_S  7
+/* SPI_SLV_CMD9_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_CLR    (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_CLR_V  0x1
+#define SPI_SLV_CMD9_INT_CLR_S  6
+/* SPI_SLV_CMD8_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_CLR    (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_CLR_V  0x1
+#define SPI_SLV_CMD8_INT_CLR_S  5
+/* SPI_SLV_CMD7_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_CLR    (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_CLR_V  0x1
+#define SPI_SLV_CMD7_INT_CLR_S  4
+/* SPI_SLV_EN_QPI_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_CLR    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EN_QPI_INT_CLR_S  3
+/* SPI_SLV_EX_QPI_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_CLR    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_CLR_V  0x1
+#define SPI_SLV_EX_QPI_INT_CLR_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S  0
+
+#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x3C)
+/* SPI_APP1_INT_RAW : R/WTC/SS ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software
+..*/
+#define SPI_APP1_INT_RAW    (BIT(20))
+#define SPI_APP1_INT_RAW_M  (BIT(20))
+#define SPI_APP1_INT_RAW_V  0x1
+#define SPI_APP1_INT_RAW_S  20
+/* SPI_APP2_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software
+..*/
+#define SPI_APP2_INT_RAW    (BIT(19))
+#define SPI_APP2_INT_RAW_M  (BIT(19))
+#define SPI_APP2_INT_RAW_V  0x1
+#define SPI_APP2_INT_RAW_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+ write-full error when SPI inputs data in master mode. 0: Others..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S  17
+/* SPI_SLV_CMD_ERR_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+ current SPI slave HD mode transmission is not supported. 0: Others..*/
+#define SPI_SLV_CMD_ERR_INT_RAW    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_RAW_V  0x1
+#define SPI_SLV_CMD_ERR_INT_RAW_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
+s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
+ is bigger than 63. 0: Others..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S  15
+/* SPI_SEG_MAGIC_ERR_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buff
+er is error in the DMA seg-conf-trans. 0: others..*/
+#define SPI_SEG_MAGIC_ERR_INT_RAW    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_RAW_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_RAW_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-du
+plex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And da
+ta has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is
+not ended or not occurred. .*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S  13
+/* SPI_TRANS_DONE_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+ ended. 0: others..*/
+#define SPI_TRANS_DONE_INT_RAW    (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_RAW_V  0x1
+#define SPI_TRANS_DONE_INT_RAW_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_BUF_DONE_INT_RAW    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_RAW_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_BUF_DONE_INT_RAW    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_RAW_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_WR_DMA_DONE_INT_RAW    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_RAW_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA tran
+smission is ended. 0: Others..*/
+#define SPI_SLV_RD_DMA_DONE_INT_RAW    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_RAW_S  8
+/* SPI_SLV_CMDA_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMDA_INT_RAW    (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_RAW_V  0x1
+#define SPI_SLV_CMDA_INT_RAW_S  7
+/* SPI_SLV_CMD9_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD9_INT_RAW    (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_RAW_V  0x1
+#define SPI_SLV_CMD9_INT_RAW_S  6
+/* SPI_SLV_CMD8_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD8_INT_RAW    (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_RAW_V  0x1
+#define SPI_SLV_CMD8_INT_RAW_S  5
+/* SPI_SLV_CMD7_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+ ended. 0: Others..*/
+#define SPI_SLV_CMD7_INT_RAW    (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_RAW_V  0x1
+#define SPI_SLV_CMD7_INT_RAW_S  4
+/* SPI_SLV_EN_QPI_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EN_QPI_INT_RAW    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EN_QPI_INT_RAW_S  3
+/* SPI_SLV_EX_QPI_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmissio
+n is ended. 0: Others..*/
+#define SPI_SLV_EX_QPI_INT_RAW    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_RAW_V  0x1
+#define SPI_SLV_EX_QPI_INT_RAW_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+ master mode and send out all 0 in slave mode.  0: Others.  .*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
+the receive data.  0: Others.  .*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S  0
+
+#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x40)
+/* SPI_APP1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_ST    (BIT(20))
+#define SPI_APP1_INT_ST_M  (BIT(20))
+#define SPI_APP1_INT_ST_V  0x1
+#define SPI_APP1_INT_ST_S  20
+/* SPI_APP2_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The status bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_ST    (BIT(19))
+#define SPI_APP2_INT_ST_M  (BIT(19))
+#define SPI_APP2_INT_ST_V  0x1
+#define SPI_APP2_INT_ST_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S  17
+/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_ST    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_ST_V  0x1
+#define SPI_SLV_CMD_ERR_INT_ST_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S  15
+/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_ST    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_ST_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_ST_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S  13
+/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The status bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_ST    (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_ST_V  0x1
+#define SPI_TRANS_DONE_INT_ST_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_ST    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_ST_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_ST    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_ST_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_ST    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_ST_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_ST    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_ST_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_ST_S  8
+/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_ST    (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_ST_V  0x1
+#define SPI_SLV_CMDA_INT_ST_S  7
+/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_ST    (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_ST_V  0x1
+#define SPI_SLV_CMD9_INT_ST_S  6
+/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_ST    (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_ST_V  0x1
+#define SPI_SLV_CMD8_INT_ST_S  5
+/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_ST    (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_ST_V  0x1
+#define SPI_SLV_CMD7_INT_ST_S  4
+/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_ST    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_ST_V  0x1
+#define SPI_SLV_EN_QPI_INT_ST_S  3
+/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_ST    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_ST_V  0x1
+#define SPI_SLV_EX_QPI_INT_ST_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S  0
+
+#define SPI_DMA_INT_SET_REG(i)          (REG_SPI_BASE(i) + 0x44)
+/* SPI_APP1_INT_SET : WT ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_APP1_INT interrupt..*/
+#define SPI_APP1_INT_SET    (BIT(20))
+#define SPI_APP1_INT_SET_M  (BIT(20))
+#define SPI_APP1_INT_SET_V  0x1
+#define SPI_APP1_INT_SET_S  20
+/* SPI_APP2_INT_SET : WT ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_APP2_INT interrupt..*/
+#define SPI_APP2_INT_SET    (BIT(19))
+#define SPI_APP2_INT_SET_M  (BIT(19))
+#define SPI_APP2_INT_SET_V  0x1
+#define SPI_APP2_INT_SET_S  19
+/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET : WT ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt..*/
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET    (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_M  (BIT(18))
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_V  0x1
+#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET_S  18
+/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET : WT ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt..*/
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET    (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_M  (BIT(17))
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_V  0x1
+#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET_S  17
+/* SPI_SLV_CMD_ERR_INT_SET : WT ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt..*/
+#define SPI_SLV_CMD_ERR_INT_SET    (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_M  (BIT(16))
+#define SPI_SLV_CMD_ERR_INT_SET_V  0x1
+#define SPI_SLV_CMD_ERR_INT_SET_S  16
+/* SPI_SLV_BUF_ADDR_ERR_INT_SET : WT ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt..*/
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET    (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_M  (BIT(15))
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_V  0x1
+#define SPI_SLV_BUF_ADDR_ERR_INT_SET_S  15
+/* SPI_SEG_MAGIC_ERR_INT_SET : WT ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt..*/
+#define SPI_SEG_MAGIC_ERR_INT_SET    (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_M  (BIT(14))
+#define SPI_SEG_MAGIC_ERR_INT_SET_V  0x1
+#define SPI_SEG_MAGIC_ERR_INT_SET_S  14
+/* SPI_DMA_SEG_TRANS_DONE_INT_SET : WT ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt..*/
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET    (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_M  (BIT(13))
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_V  0x1
+#define SPI_DMA_SEG_TRANS_DONE_INT_SET_S  13
+/* SPI_TRANS_DONE_INT_SET : WT ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_TRANS_DONE_INT interrupt..*/
+#define SPI_TRANS_DONE_INT_SET    (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_M  (BIT(12))
+#define SPI_TRANS_DONE_INT_SET_V  0x1
+#define SPI_TRANS_DONE_INT_SET_S  12
+/* SPI_SLV_WR_BUF_DONE_INT_SET : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_WR_BUF_DONE_INT_SET    (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_M  (BIT(11))
+#define SPI_SLV_WR_BUF_DONE_INT_SET_V  0x1
+#define SPI_SLV_WR_BUF_DONE_INT_SET_S  11
+/* SPI_SLV_RD_BUF_DONE_INT_SET : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt..*/
+#define SPI_SLV_RD_BUF_DONE_INT_SET    (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_M  (BIT(10))
+#define SPI_SLV_RD_BUF_DONE_INT_SET_V  0x1
+#define SPI_SLV_RD_BUF_DONE_INT_SET_S  10
+/* SPI_SLV_WR_DMA_DONE_INT_SET : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_WR_DMA_DONE_INT_SET    (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_M  (BIT(9))
+#define SPI_SLV_WR_DMA_DONE_INT_SET_V  0x1
+#define SPI_SLV_WR_DMA_DONE_INT_SET_S  9
+/* SPI_SLV_RD_DMA_DONE_INT_SET : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt..*/
+#define SPI_SLV_RD_DMA_DONE_INT_SET    (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_INT_SET_V  0x1
+#define SPI_SLV_RD_DMA_DONE_INT_SET_S  8
+/* SPI_SLV_CMDA_INT_SET : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMDA interrupt..*/
+#define SPI_SLV_CMDA_INT_SET    (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_M  (BIT(7))
+#define SPI_SLV_CMDA_INT_SET_V  0x1
+#define SPI_SLV_CMDA_INT_SET_S  7
+/* SPI_SLV_CMD9_INT_SET : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD9 interrupt..*/
+#define SPI_SLV_CMD9_INT_SET    (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_M  (BIT(6))
+#define SPI_SLV_CMD9_INT_SET_V  0x1
+#define SPI_SLV_CMD9_INT_SET_S  6
+/* SPI_SLV_CMD8_INT_SET : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD8 interrupt..*/
+#define SPI_SLV_CMD8_INT_SET    (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_M  (BIT(5))
+#define SPI_SLV_CMD8_INT_SET_V  0x1
+#define SPI_SLV_CMD8_INT_SET_S  5
+/* SPI_SLV_CMD7_INT_SET : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave CMD7 interrupt..*/
+#define SPI_SLV_CMD7_INT_SET    (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_M  (BIT(4))
+#define SPI_SLV_CMD7_INT_SET_V  0x1
+#define SPI_SLV_CMD7_INT_SET_S  4
+/* SPI_SLV_EN_QPI_INT_SET : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave En_QPI interrupt..*/
+#define SPI_SLV_EN_QPI_INT_SET    (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_M  (BIT(3))
+#define SPI_SLV_EN_QPI_INT_SET_V  0x1
+#define SPI_SLV_EN_QPI_INT_SET_S  3
+/* SPI_SLV_EX_QPI_INT_SET : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The software set bit for SPI slave Ex_QPI interrupt..*/
+#define SPI_SLV_EX_QPI_INT_SET    (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_M  (BIT(2))
+#define SPI_SLV_EX_QPI_INT_SET_V  0x1
+#define SPI_SLV_EX_QPI_INT_SET_S  2
+/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt..*/
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET    (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_M  (BIT(1))
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET_S  1
+/* SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt..*/
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET    (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_M  (BIT(0))
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_V  0x1
+#define SPI_DMA_INFIFO_FULL_ERR_INT_SET_S  0
+
+#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x98)
+/* SPI_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF0    0xFFFFFFFF
+#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
+#define SPI_BUF0_V  0xFFFFFFFF
+#define SPI_BUF0_S  0
+
+#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x9C)
+/* SPI_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF1    0xFFFFFFFF
+#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
+#define SPI_BUF1_V  0xFFFFFFFF
+#define SPI_BUF1_S  0
+
+#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0xA0)
+/* SPI_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF2    0xFFFFFFFF
+#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
+#define SPI_BUF2_V  0xFFFFFFFF
+#define SPI_BUF2_S  0
+
+#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0xA4)
+/* SPI_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF3    0xFFFFFFFF
+#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
+#define SPI_BUF3_V  0xFFFFFFFF
+#define SPI_BUF3_S  0
+
+#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0xA8)
+/* SPI_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF4    0xFFFFFFFF
+#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
+#define SPI_BUF4_V  0xFFFFFFFF
+#define SPI_BUF4_S  0
+
+#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0xAC)
+/* SPI_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF5    0xFFFFFFFF
+#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
+#define SPI_BUF5_V  0xFFFFFFFF
+#define SPI_BUF5_S  0
+
+#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0xB0)
+/* SPI_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF6    0xFFFFFFFF
+#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
+#define SPI_BUF6_V  0xFFFFFFFF
+#define SPI_BUF6_S  0
+
+#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0xB4)
+/* SPI_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF7    0xFFFFFFFF
+#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
+#define SPI_BUF7_V  0xFFFFFFFF
+#define SPI_BUF7_S  0
+
+#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0xB8)
+/* SPI_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF8    0xFFFFFFFF
+#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
+#define SPI_BUF8_V  0xFFFFFFFF
+#define SPI_BUF8_S  0
+
+#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0xBC)
+/* SPI_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF9    0xFFFFFFFF
+#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
+#define SPI_BUF9_V  0xFFFFFFFF
+#define SPI_BUF9_S  0
+
+#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0xC0)
+/* SPI_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF10    0xFFFFFFFF
+#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
+#define SPI_BUF10_V  0xFFFFFFFF
+#define SPI_BUF10_S  0
+
+#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0xC4)
+/* SPI_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF11    0xFFFFFFFF
+#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
+#define SPI_BUF11_V  0xFFFFFFFF
+#define SPI_BUF11_S  0
+
+#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0xC8)
+/* SPI_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF12    0xFFFFFFFF
+#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
+#define SPI_BUF12_V  0xFFFFFFFF
+#define SPI_BUF12_S  0
+
+#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0xCC)
+/* SPI_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF13    0xFFFFFFFF
+#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
+#define SPI_BUF13_V  0xFFFFFFFF
+#define SPI_BUF13_S  0
+
+#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0xD0)
+/* SPI_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF14    0xFFFFFFFF
+#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
+#define SPI_BUF14_V  0xFFFFFFFF
+#define SPI_BUF14_S  0
+
+#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0xD4)
+/* SPI_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: data buffer.*/
+#define SPI_BUF15    0xFFFFFFFF
+#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
+#define SPI_BUF15_V  0xFFFFFFFF
+#define SPI_BUF15_S  0
+
+#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0xE0)
+/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-tra
+ns will start. 0: This is not seg-trans mode..*/
+#define SPI_USR_CONF    (BIT(28))
+#define SPI_USR_CONF_M  (BIT(28))
+#define SPI_USR_CONF_V  0x1
+#define SPI_USR_CONF_S  28
+/* SPI_SOFT_RESET : WT ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Software reset enable, reset the spi clock line cs line and data lines. Can be c
+onfigured in CONF state..*/
+#define SPI_SOFT_RESET    (BIT(27))
+#define SPI_SOFT_RESET_M  (BIT(27))
+#define SPI_SOFT_RESET_V  0x1
+#define SPI_SOFT_RESET_S  27
+/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set SPI work mode. 1: slave mode 0: master mode..*/
+#define SPI_SLAVE_MODE    (BIT(26))
+#define SPI_SLAVE_MODE_M  (BIT(26))
+#define SPI_SLAVE_MODE_V  0x1
+#define SPI_SLAVE_MODE_S  26
+/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */
+/*description: The magic value of BM table in master DMA seg-trans..*/
+#define SPI_DMA_SEG_MAGIC_VALUE    0x0000000F
+#define SPI_DMA_SEG_MAGIC_VALUE_M  ((SPI_DMA_SEG_MAGIC_VALUE_V)<<(SPI_DMA_SEG_MAGIC_VALUE_S))
+#define SPI_DMA_SEG_MAGIC_VALUE_V  0xF
+#define SPI_DMA_SEG_MAGIC_VALUE_S  22
+/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in CPU controlled mode(Wr_BUF). 0: others.*/
+#define SPI_SLV_WRBUF_BITLEN_EN    (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_M  (BIT(11))
+#define SPI_SLV_WRBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_WRBUF_BITLEN_EN_S  11
+/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n CPU controlled mode(Rd_BUF). 0: others.*/
+#define SPI_SLV_RDBUF_BITLEN_EN    (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_M  (BIT(10))
+#define SPI_SLV_RDBUF_BITLEN_EN_V  0x1
+#define SPI_SLV_RDBUF_BITLEN_EN_S  10
+/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data leng
+th in DMA controlled mode(Wr_DMA). 0: others.*/
+#define SPI_SLV_WRDMA_BITLEN_EN    (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_M  (BIT(9))
+#define SPI_SLV_WRDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_WRDMA_BITLEN_EN_S  9
+/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length i
+n DMA controlled mode(Rd_DMA). 0: others.*/
+#define SPI_SLV_RDDMA_BITLEN_EN    (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_M  (BIT(8))
+#define SPI_SLV_RDDMA_BITLEN_EN_V  0x1
+#define SPI_SLV_RDDMA_BITLEN_EN_S  8
+/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: It saves half a cycle when tsck is the same as rsck. 1: output data at rsck pose
+dge   0: output data at tsck posedge .*/
+#define SPI_RSCK_DATA_OUT    (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (BIT(3))
+#define SPI_RSCK_DATA_OUT_V  0x1
+#define SPI_RSCK_DATA_OUT_S  3
+/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
+ 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]..*/
+#define SPI_CLK_MODE_13    (BIT(2))
+#define SPI_CLK_MODE_13_M  (BIT(2))
+#define SPI_CLK_MODE_13_V  0x1
+#define SPI_CLK_MODE_13_S  2
+/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
+d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
+ve 3: SPI clock is always on. Can be configured in CONF state..*/
+#define SPI_CLK_MODE    0x00000003
+#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
+#define SPI_CLK_MODE_V  0x3
+#define SPI_CLK_MODE_S  0
+
+#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0xE4)
+/* SPI_SLV_LAST_ADDR : R/W/SS ;bitpos:[31:26] ;default: 6'd0 ; */
+/*description: In the slave mode it is the value of address..*/
+#define SPI_SLV_LAST_ADDR    0x0000003F
+#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
+#define SPI_SLV_LAST_ADDR_V  0x3F
+#define SPI_SLV_LAST_ADDR_S  26
+/* SPI_SLV_LAST_COMMAND : R/W/SS ;bitpos:[25:18] ;default: 8'b0 ; */
+/*description: In the slave mode it is the value of command..*/
+#define SPI_SLV_LAST_COMMAND    0x000000FF
+#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
+#define SPI_SLV_LAST_COMMAND_V  0xFF
+#define SPI_SLV_LAST_COMMAND_S  18
+/* SPI_SLV_DATA_BITLEN : R/W/SS ;bitpos:[17:0] ;default: 18'd0 ; */
+/*description: The transferred data bit length in SPI slave FD and HD mode. .*/
+#define SPI_SLV_DATA_BITLEN    0x0003FFFF
+#define SPI_SLV_DATA_BITLEN_M  ((SPI_SLV_DATA_BITLEN_V)<<(SPI_SLV_DATA_BITLEN_S))
+#define SPI_SLV_DATA_BITLEN_V  0x3FFFF
+#define SPI_SLV_DATA_BITLEN_S  0
+
+#define SPI_CLK_GATE_REG(i)          (REG_SPI_BASE(i) + 0xE8)
+/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80
+M. 0: XTAL CLK..*/
+#define SPI_MST_CLK_SEL    (BIT(2))
+#define SPI_MST_CLK_SEL_M  (BIT(2))
+#define SPI_MST_CLK_SEL_V  0x1
+#define SPI_MST_CLK_SEL_S  2
+/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to power on the SPI module clock..*/
+#define SPI_MST_CLK_ACTIVE    (BIT(1))
+#define SPI_MST_CLK_ACTIVE_M  (BIT(1))
+#define SPI_MST_CLK_ACTIVE_V  0x1
+#define SPI_MST_CLK_ACTIVE_S  1
+/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate.*/
+#define SPI_CLK_EN    (BIT(0))
+#define SPI_CLK_EN_M  (BIT(0))
+#define SPI_CLK_EN_V  0x1
+#define SPI_CLK_EN_S  0
+
+#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0xF0)
+/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101190 ; */
+/*description: SPI register version..*/
+#define SPI_DATE    0x0FFFFFFF
+#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
+#define SPI_DATE_V  0xFFFFFFF
+#define SPI_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/spi_struct.h b/components/soc/esp32s3/register/soc/spi_struct.h
new file mode 100644
index 00000000000..e9d62932e2b
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/spi_struct.h
@@ -0,0 +1,420 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SPI_STRUCT_H_
+#define _SOC_SPI_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct spi_dev_s {
+    union {
+        struct {
+            uint32_t conf_bitlen                   :    18;  /*Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    5;  /*reserved*/
+            uint32_t update                        :    1;  /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
+            uint32_t usr                           :    1;  /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
+            uint32_t reserved25                    :    7;  /*reserved*/
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;
+    union {
+        struct {
+            uint32_t reserved0                     :    3;  /*reserved*/
+            uint32_t dummy_out                     :    1;  /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
+            uint32_t reserved4                     :    1;  /*reserved*/
+            uint32_t faddr_dual                    :    1;  /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t faddr_quad                    :    1;  /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t faddr_oct                     :    1;  /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_dual                     :    1;  /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_quad                     :    1;  /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fcmd_oct                      :    1;  /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved11                    :    3;  /*reserved*/
+            uint32_t fread_dual                    :    1;  /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t fread_quad                    :    1;  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t fread_oct                     :    1;  /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t reserved17                    :    1;  /*reserved*/
+            uint32_t q_pol                         :    1;  /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t d_pol                         :    1;  /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
+            uint32_t hold_pol                      :    1;  /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
+            uint32_t wp_pol                        :    1;  /*Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    1;  /*reserved*/
+            uint32_t rd_bit_order                  :    2;  /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
+            uint32_t wr_bit_order                  :    2;  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
+            uint32_t reserved27                    :    5;  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clkcnt_l                      :    6;  /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_h                      :    6;  /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
+            uint32_t clkcnt_n                      :    6;  /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
+            uint32_t clkdiv_pre                    :    4;  /*In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.*/
+            uint32_t reserved22                    :    9;  /*reserved*/
+            uint32_t clk_equ_sysclk                :    1;  /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t doutdin                       :    1;  /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved1                     :    2;  /*reserved*/
+            uint32_t qpi_mode                      :    1;  /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
+            uint32_t opi_mode                      :    1;  /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
+            uint32_t tsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
+            uint32_t cs_hold                       :    1;  /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t cs_setup                      :    1;  /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t rsck_i_edge                   :    1;  /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
+            uint32_t ck_out_edge                   :    1;  /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
+            uint32_t reserved10                    :    2;  /*reserved*/
+            uint32_t fwrite_dual                   :    1;  /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
+            uint32_t fwrite_quad                   :    1;  /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
+            uint32_t fwrite_oct                    :    1;  /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
+            uint32_t usr_conf_nxt                  :    1;  /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    1;  /*reserved*/
+            uint32_t sio                           :    1;  /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t reserved18                    :    6;  /*reserved*/
+            uint32_t usr_miso_highpart             :    1;  /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
+            uint32_t usr_mosi_highpart             :    1;  /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.*/
+            uint32_t usr_dummy_idle                :    1;  /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
+            uint32_t usr_mosi                      :    1;  /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_miso                      :    1;  /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_dummy                     :    1;  /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_addr                      :    1;  /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
+            uint32_t usr_command                   :    1;  /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen            :    8;  /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
+            uint32_t reserved8                     :    8;  /*reserved*/
+            uint32_t mst_wfull_err_end_en          :    1;  /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t cs_setup_time                 :    5;  /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
+            uint32_t cs_hold_time                  :    5;  /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
+            uint32_t usr_addr_bitlen               :    5;  /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value             :    16;  /*The value of  command. Can be configured in CONF state.*/
+            uint32_t reserved16                    :    11;  /*reserved*/
+            uint32_t mst_rempty_err_end_en         :    1;  /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
+            uint32_t usr_command_bitlen            :    4;  /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t ms_data_bitlen                :    18;  /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
+            uint32_t reserved18                    :    14;  /*reserved*/
+        };
+        uint32_t val;
+    } ms_dlen;
+    union {
+        struct {
+            uint32_t cs0_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs1_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs2_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs3_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs4_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t cs5_dis                       :    1;  /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
+            uint32_t ck_dis                        :    1;  /*1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.*/
+            uint32_t master_cs_pol                 :    6;  /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
+            uint32_t reserved13                    :    3;  /*reserved*/
+            uint32_t clk_data_dtr_en               :    1;  /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs.  0: SPI master DTR mode is  only applied to spi_dqs. This bit should be used with bit 17/18/19. */
+            uint32_t data_dtr_en                   :    1;  /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
+            uint32_t addr_dtr_en                   :    1;  /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm.  0:  SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
+            uint32_t cmd_dtr_en                    :    1;  /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0:  SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
+            uint32_t reserved20                    :    3;  /*reserved*/
+            uint32_t slave_cs_pol                  :    1;  /*spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.*/
+            uint32_t dqs_idle_edge                 :    1;  /*The default value of spi_dqs. Can be configured in CONF state.*/
+            uint32_t reserved25                    :    4;  /*reserved*/
+            uint32_t ck_idle_edge                  :    1;  /*1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.*/
+            uint32_t cs_keep_active                :    1;  /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
+            uint32_t quad_din_pin_swap             :    1;  /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0:  spi quad input swap disable. Can be configured in CONF state.*/
+        };
+        uint32_t val;
+    } misc;
+    union {
+        struct {
+            uint32_t din0_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din1_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din2_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din3_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din4_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din5_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din6_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t din7_mode                     :    2;  /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
+            uint32_t timing_hclk_active            :    1;  /*1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.*/
+            uint32_t reserved17                    :    15;  /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din1_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din2_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din3_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din4_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din5_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din6_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t din7_num                      :    2;  /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout1_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout2_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout3_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout4_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout5_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout6_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t dout7_mode                    :    1;  /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t d_dqs_mode                    :    1;  /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
+            uint32_t reserved9                     :    23;  /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t outfifo_empty                 :    1;  /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
+            uint32_t infifo_full                   :    1;  /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
+            uint32_t reserved2                     :    16;  /*reserved*/
+            uint32_t dma_seg_trans_en              :    1;  /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
+            uint32_t rx_seg_trans_clr_en           :    1;  /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
+            uint32_t tx_seg_trans_clr_en           :    1;  /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
+            uint32_t rx_eof_en                     :    1;  /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
+            uint32_t reserved22                    :    5;  /*reserved*/
+            uint32_t dma_rx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled receive data mode.*/
+            uint32_t dma_tx_ena                    :    1;  /*Set this bit to enable SPI DMA controlled send data mode.*/
+            uint32_t rx_afifo_rst                  :    1;  /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
+            uint32_t buf_afifo_rst                 :    1;  /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
+            uint32_t dma_afifo_rst                 :    1;  /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The enable bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The enable bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The enable bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The enable bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The enable bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The enable bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The enable bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The enable bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_ena;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The clear bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The clear bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The clear bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The clear bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The clear bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The clear bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The clear bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The clear bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_clr;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.  */
+            uint32_t outfifo_empty_err             :    1;  /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.  */
+            uint32_t ex_qpi                        :    1;  /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
+            uint32_t en_qpi                        :    1;  /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
+            uint32_t cmd7                          :    1;  /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
+            uint32_t cmd8                          :    1;  /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
+            uint32_t cmd9                          :    1;  /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
+            uint32_t cmda                          :    1;  /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
+            uint32_t rd_dma_done                   :    1;  /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
+            uint32_t wr_dma_done                   :    1;  /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
+            uint32_t rd_buf_done                   :    1;  /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
+            uint32_t wr_buf_done                   :    1;  /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
+            uint32_t trans_done                    :    1;  /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred. */
+            uint32_t seg_magic_err                 :    1;  /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
+            uint32_t buf_addr_err                  :    1;  /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
+            uint32_t cmd_err                       :    1;  /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
+            uint32_t app2                          :    1;  /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
+            uint32_t app1                          :    1;  /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_raw;
+    union {
+        struct {
+            uint32_t infifo_full_err               :    1;  /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err             :    1;  /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi                        :    1;  /*The status bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi                        :    1;  /*The status bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7                          :    1;  /*The status bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8                          :    1;  /*The status bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9                          :    1;  /*The status bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda                          :    1;  /*The status bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done                   :    1;  /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done                   :    1;  /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done                   :    1;  /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done                   :    1;  /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done                    :    1;  /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done            :    1;  /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err                 :    1;  /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err                  :    1;  /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err                       :    1;  /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err        :    1;  /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err       :    1;  /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2                          :    1;  /*The status bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1                          :    1;  /*The status bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_st;
+    union {
+        struct {
+            uint32_t infifo_full_err_int_set       :    1;  /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
+            uint32_t outfifo_empty_err_int_set     :    1;  /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
+            uint32_t ex_qpi_int_set                :    1;  /*The software set bit for SPI slave Ex_QPI interrupt.*/
+            uint32_t en_qpi_int_set                :    1;  /*The software set bit for SPI slave En_QPI interrupt.*/
+            uint32_t cmd7_int_set                  :    1;  /*The software set bit for SPI slave CMD7 interrupt.*/
+            uint32_t cmd8_int_set                  :    1;  /*The software set bit for SPI slave CMD8 interrupt.*/
+            uint32_t cmd9_int_set                  :    1;  /*The software set bit for SPI slave CMD9 interrupt.*/
+            uint32_t cmda_int_set                  :    1;  /*The software set bit for SPI slave CMDA interrupt.*/
+            uint32_t rd_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
+            uint32_t wr_dma_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
+            uint32_t rd_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
+            uint32_t wr_buf_done_int_set           :    1;  /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
+            uint32_t trans_done_int_set            :    1;  /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
+            uint32_t dma_seg_trans_done_int_set    :    1;  /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
+            uint32_t seg_magic_err_int_set         :    1;  /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
+            uint32_t buf_addr_err_int_set          :    1;  /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
+            uint32_t cmd_err_int_set               :    1;  /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
+            uint32_t mst_rx_afifo_wfull_err_int_set:    1;  /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
+            uint32_t mst_tx_afifo_rempty_err_int_set:    1;  /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
+            uint32_t app2_int_set                  :    1;  /*The software set bit for SPI_APP2_INT interrupt.*/
+            uint32_t app1_int_set                  :    1;  /*The software set bit for SPI_APP1_INT interrupt.*/
+            uint32_t reserved21                    :    11;  /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_set;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t data_buf[16];                                               /*SPI CPU-controlled buffer0*/
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    union {
+        struct {
+            uint32_t clk_mode                      :    2;  /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/
+            uint32_t clk_mode_13                   :    1;  /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
+            uint32_t rsck_data_out                 :    1;  /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge */
+            uint32_t reserved4                     :    4;  /*reserved*/
+            uint32_t rddma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
+            uint32_t wrdma_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
+            uint32_t rdbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
+            uint32_t wrbuf_bitlen_en               :    1;  /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
+            uint32_t reserved12                    :    10;  /*reserved*/
+            uint32_t dma_seg_magic_value           :    4;  /*The magic value of BM table in master DMA seg-trans.*/
+            uint32_t slave_mode                    :    1;  /*Set SPI work mode. 1: slave mode 0: master mode.*/
+            uint32_t soft_reset                    :    1;  /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
+            uint32_t usr_conf                      :    1;  /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
+            uint32_t reserved29                    :    3;  /*reserved*/
+        };
+        uint32_t val;
+    } slave;
+    union {
+        struct {
+            uint32_t data_bitlen                   :    18;  /*The transferred data bit length in SPI slave FD and HD mode. */
+            uint32_t last_command                  :    8;  /*In the slave mode it is the value of command.*/
+            uint32_t last_addr                     :    6;  /*In the slave mode it is the value of address.*/
+        };
+        uint32_t val;
+    } slave1;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;  /*Set this bit to enable clk gate*/
+            uint32_t mst_clk_active                :    1;  /*Set this bit to power on the SPI module clock.*/
+            uint32_t mst_clk_sel                   :    1;  /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } clk_gate;
+    uint32_t reserved_ec;
+    union {
+        struct {
+            uint32_t date                          :    28;  /*SPI register version.*/
+            uint32_t reserved28                    :    4;  /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_dev_t;
+extern spi_dev_t GPSPI2;
+extern spi_dev_t GPSPI3;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_STRUCT_H_ */
diff --git a/components/soc/esp32s3/register/soc/syscon_reg.h b/components/soc/esp32s3/register/soc/syscon_reg.h
new file mode 100644
index 00000000000..75a58fcdb52
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/syscon_reg.h
@@ -0,0 +1,720 @@
+/**
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSCON_REG_H_
+#define _SOC_SYSCON_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x0)
+/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_RST_TICK_CNT    (BIT(12))
+#define SYSCON_RST_TICK_CNT_M  (BIT(12))
+#define SYSCON_RST_TICK_CNT_V  0x1
+#define SYSCON_RST_TICK_CNT_S  12
+/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_CLK_EN    (BIT(11))
+#define SYSCON_CLK_EN_M  (BIT(11))
+#define SYSCON_CLK_EN_V  0x1
+#define SYSCON_CLK_EN_S  11
+/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_CLK_320M_EN    (BIT(10))
+#define SYSCON_CLK_320M_EN_M  (BIT(10))
+#define SYSCON_CLK_320M_EN_V  0x1
+#define SYSCON_CLK_320M_EN_S  10
+/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: .*/
+#define SYSCON_PRE_DIV_CNT    0x000003FF
+#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
+#define SYSCON_PRE_DIV_CNT_V  0x3FF
+#define SYSCON_PRE_DIV_CNT_S  0
+
+#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x4)
+/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: .*/
+#define SYSCON_TICK_ENABLE    (BIT(16))
+#define SYSCON_TICK_ENABLE_M  (BIT(16))
+#define SYSCON_TICK_ENABLE_V  0x1
+#define SYSCON_TICK_ENABLE_S  16
+/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: .*/
+#define SYSCON_CK8M_TICK_NUM    0x000000FF
+#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
+#define SYSCON_CK8M_TICK_NUM_V  0xFF
+#define SYSCON_CK8M_TICK_NUM_S  8
+/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: .*/
+#define SYSCON_XTAL_TICK_NUM    0x000000FF
+#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
+#define SYSCON_XTAL_TICK_NUM_V  0xFF
+#define SYSCON_XTAL_TICK_NUM_S  0
+
+#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x8)
+/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK_XTAL_OEN    (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_V  0x1
+#define SYSCON_CLK_XTAL_OEN_S  10
+/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK40X_BB_OEN    (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_V  0x1
+#define SYSCON_CLK40X_BB_OEN_S  9
+/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK_DAC_CPU_OEN    (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
+#define SYSCON_CLK_DAC_CPU_OEN_S  8
+/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK_ADC_INF_OEN    (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_V  0x1
+#define SYSCON_CLK_ADC_INF_OEN_S  7
+/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK_320M_OEN    (BIT(6))
+#define SYSCON_CLK_320M_OEN_M  (BIT(6))
+#define SYSCON_CLK_320M_OEN_V  0x1
+#define SYSCON_CLK_320M_OEN_S  6
+/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK160_OEN    (BIT(5))
+#define SYSCON_CLK160_OEN_M  (BIT(5))
+#define SYSCON_CLK160_OEN_V  0x1
+#define SYSCON_CLK160_OEN_S  5
+/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK80_OEN    (BIT(4))
+#define SYSCON_CLK80_OEN_M  (BIT(4))
+#define SYSCON_CLK80_OEN_V  0x1
+#define SYSCON_CLK80_OEN_S  4
+/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK_BB_OEN    (BIT(3))
+#define SYSCON_CLK_BB_OEN_M  (BIT(3))
+#define SYSCON_CLK_BB_OEN_V  0x1
+#define SYSCON_CLK_BB_OEN_S  3
+/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK44_OEN    (BIT(2))
+#define SYSCON_CLK44_OEN_M  (BIT(2))
+#define SYSCON_CLK44_OEN_V  0x1
+#define SYSCON_CLK44_OEN_S  2
+/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK22_OEN    (BIT(1))
+#define SYSCON_CLK22_OEN_M  (BIT(1))
+#define SYSCON_CLK22_OEN_V  0x1
+#define SYSCON_CLK22_OEN_S  1
+/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_CLK20_OEN    (BIT(0))
+#define SYSCON_CLK20_OEN_M  (BIT(0))
+#define SYSCON_CLK20_OEN_V  0x1
+#define SYSCON_CLK20_OEN_S  0
+
+#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0xC)
+/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define SYSCON_WIFI_BB_CFG    0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
+#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_S  0
+
+#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x10)
+/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define SYSCON_WIFI_BB_CFG_2    0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
+#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_S  0
+
+#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x14)
+/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: .*/
+#define SYSCON_WIFI_CLK_EN    0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
+#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_S  0
+
+#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x18)
+/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define SYSCON_WIFI_RST    0xFFFFFFFF
+#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
+#define SYSCON_WIFI_RST_V  0xFFFFFFFF
+#define SYSCON_WIFI_RST_S  0
+
+#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
+/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
+#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S))
+#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
+#define SYSTEM_WIFI_CLK_EN_S 0
+
+/* Mask for all Wifi clock bits, 6 */
+#define SYSTEM_WIFI_CLK_WIFI_EN  0x0
+#define SYSTEM_WIFI_CLK_WIFI_EN_M  ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
+#define SYSTEM_WIFI_CLK_WIFI_EN_V  0x0
+#define SYSTEM_WIFI_CLK_WIFI_EN_S  0
+/* Mask for all Bluetooth clock bits, 11, 16, 17 */
+#define SYSTEM_WIFI_CLK_BT_EN  0x0
+#define SYSTEM_WIFI_CLK_BT_EN_M  ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
+#define SYSTEM_WIFI_CLK_BT_EN_V  0x0
+#define SYSTEM_WIFI_CLK_BT_EN_S  0
+/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
+#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
+
+//bluetooth baseband bit11
+#define SYSTEM_BT_BASEBAND_EN BIT(11)
+//bluetooth LC bit16 and bit17
+#define SYSTEM_BT_LC_EN (BIT(16) | BIT(17))
+
+/* Remaining single bit clock masks */
+#define SYSTEM_WIFI_CLK_I2C_CLK_EN BIT(5)
+#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12)
+#define SYSTEM_WIFI_CLK_SDIO_HOST_EN BIT(13)
+#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14)
+#define SYSTEM_WIFI_CLK_RNG_EN BIT(15)
+
+#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
+#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
+/* SYSTEM_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSTEM_WIFI_RST 0xFFFFFFFF
+#define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S))
+#define SYSTEM_WIFI_RST_V 0xFFFFFFFF
+#define SYSTEM_WIFI_RST_S 0
+
+#define SYSTEM_WIFIBB_RST           BIT(0)
+#define SYSTEM_FE_RST               BIT(1)
+#define SYSTEM_WIFIMAC_RST          BIT(2)
+#define SYSTEM_BTBB_RST             BIT(3)    /* Bluetooth Baseband */
+#define SYSTEM_BTMAC_RST            BIT(4)    /* deprecated */
+#define SYSTEM_SDIO_RST             BIT(5)
+#define SYSTEM_EMAC_RST             BIT(7)
+#define SYSTEM_MACPWR_RST           BIT(8)
+#define SYSTEM_RW_BTMAC_RST         BIT(9)    /* Bluetooth MAC */
+#define SYSTEM_RW_BTLP_RST          BIT(10)   /* Bluetooth Low Power Module */
+#define SYSTEM_RW_BTMAC_REG_RST     BIT(11)   /* Bluetooth MAC Registers */
+#define SYSTEM_RW_BTLP_REG_RST      BIT(12)   /* Bluetooth Low Power Registers */
+#define SYSTEM_BTBB_REG_RST         BIT(13)   /* Bluetooth Baseband Registers */
+
+#define MODEM_RESET_FIELD_WHEN_PU   (SYSTEM_WIFIBB_RST       | \
+                                     SYSTEM_FE_RST           | \
+                                     SYSTEM_WIFIMAC_RST      | \
+                                     SYSTEM_BTBB_RST         | \
+                                     SYSTEM_BTMAC_RST        | \
+                                     SYSTEM_RW_BTMAC_RST     | \
+                                     SYSTEM_RW_BTMAC_REG_RST | \
+                                     SYSTEM_BTBB_REG_RST)
+
+#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x1C)
+/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: .*/
+#define SYSCON_PERI_IO_SWAP    0x000000FF
+#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
+#define SYSCON_PERI_IO_SWAP_V  0xFF
+#define SYSCON_PERI_IO_SWAP_S  0
+
+#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x20)
+/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_EXT_MEM_PMS_LOCK    (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
+#define SYSCON_EXT_MEM_PMS_LOCK_S  0
+
+#define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG          (DR_REG_SYSCON_BASE + 0x24)
+/* SYSCON_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set 1 to bypass cache writeback request to external memory so that spi will not
+check its attribute..*/
+#define SYSCON_WRITEBACK_BYPASS    (BIT(0))
+#define SYSCON_WRITEBACK_BYPASS_M  (BIT(0))
+#define SYSCON_WRITEBACK_BYPASS_V  0x1
+#define SYSCON_WRITEBACK_BYPASS_S  0
+
+#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x28)
+/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE0_ATTR    0x000001FF
+#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
+#define SYSCON_FLASH_ACE0_ATTR_V  0x1FF
+#define SYSCON_FLASH_ACE0_ATTR_S  0
+
+#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x2C)
+/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE1_ATTR    0x000001FF
+#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
+#define SYSCON_FLASH_ACE1_ATTR_V  0x1FF
+#define SYSCON_FLASH_ACE1_ATTR_S  0
+
+#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x30)
+/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE2_ATTR    0x000001FF
+#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
+#define SYSCON_FLASH_ACE2_ATTR_V  0x1FF
+#define SYSCON_FLASH_ACE2_ATTR_S  0
+
+#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x34)
+/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE3_ATTR    0x000001FF
+#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
+#define SYSCON_FLASH_ACE3_ATTR_V  0x1FF
+#define SYSCON_FLASH_ACE3_ATTR_S  0
+
+#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x38)
+/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE0_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
+#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x3C)
+/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE1_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
+#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x40)
+/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE2_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
+#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x44)
+/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE3_ADDR_S    0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
+#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x48)
+/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE0_SIZE    0x0000FFFF
+#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
+#define SYSCON_FLASH_ACE0_SIZE_V  0xFFFF
+#define SYSCON_FLASH_ACE0_SIZE_S  0
+
+#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x4C)
+/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE1_SIZE    0x0000FFFF
+#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
+#define SYSCON_FLASH_ACE1_SIZE_V  0xFFFF
+#define SYSCON_FLASH_ACE1_SIZE_S  0
+
+#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x50)
+/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE2_SIZE    0x0000FFFF
+#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
+#define SYSCON_FLASH_ACE2_SIZE_V  0xFFFF
+#define SYSCON_FLASH_ACE2_SIZE_S  0
+
+#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x54)
+/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define SYSCON_FLASH_ACE3_SIZE    0x0000FFFF
+#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
+#define SYSCON_FLASH_ACE3_SIZE_V  0xFFFF
+#define SYSCON_FLASH_ACE3_SIZE_S  0
+
+#define SYSCON_SRAM_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x58)
+/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE0_ATTR    0x000001FF
+#define SYSCON_SRAM_ACE0_ATTR_M  ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S))
+#define SYSCON_SRAM_ACE0_ATTR_V  0x1FF
+#define SYSCON_SRAM_ACE0_ATTR_S  0
+
+#define SYSCON_SRAM_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x5C)
+/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE1_ATTR    0x000001FF
+#define SYSCON_SRAM_ACE1_ATTR_M  ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S))
+#define SYSCON_SRAM_ACE1_ATTR_V  0x1FF
+#define SYSCON_SRAM_ACE1_ATTR_S  0
+
+#define SYSCON_SRAM_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x60)
+/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE2_ATTR    0x000001FF
+#define SYSCON_SRAM_ACE2_ATTR_M  ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S))
+#define SYSCON_SRAM_ACE2_ATTR_V  0x1FF
+#define SYSCON_SRAM_ACE2_ATTR_S  0
+
+#define SYSCON_SRAM_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x64)
+/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE3_ATTR    0x000001FF
+#define SYSCON_SRAM_ACE3_ATTR_M  ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S))
+#define SYSCON_SRAM_ACE3_ATTR_V  0x1FF
+#define SYSCON_SRAM_ACE3_ATTR_S  0
+
+#define SYSCON_SRAM_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x68)
+/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE0_ADDR_S    0xFFFFFFFF
+#define SYSCON_SRAM_ACE0_ADDR_S_M  ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S))
+#define SYSCON_SRAM_ACE0_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_SRAM_ACE0_ADDR_S_S  0
+
+#define SYSCON_SRAM_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x6C)
+/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE1_ADDR_S    0xFFFFFFFF
+#define SYSCON_SRAM_ACE1_ADDR_S_M  ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S))
+#define SYSCON_SRAM_ACE1_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_SRAM_ACE1_ADDR_S_S  0
+
+#define SYSCON_SRAM_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x70)
+/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE2_ADDR_S    0xFFFFFFFF
+#define SYSCON_SRAM_ACE2_ADDR_S_M  ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S))
+#define SYSCON_SRAM_ACE2_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_SRAM_ACE2_ADDR_S_S  0
+
+#define SYSCON_SRAM_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x74)
+/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE3_ADDR_S    0xFFFFFFFF
+#define SYSCON_SRAM_ACE3_ADDR_S_M  ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S))
+#define SYSCON_SRAM_ACE3_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_SRAM_ACE3_ADDR_S_S  0
+
+#define SYSCON_SRAM_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x78)
+/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE0_SIZE    0x0000FFFF
+#define SYSCON_SRAM_ACE0_SIZE_M  ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S))
+#define SYSCON_SRAM_ACE0_SIZE_V  0xFFFF
+#define SYSCON_SRAM_ACE0_SIZE_S  0
+
+#define SYSCON_SRAM_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x7C)
+/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE1_SIZE    0x0000FFFF
+#define SYSCON_SRAM_ACE1_SIZE_M  ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S))
+#define SYSCON_SRAM_ACE1_SIZE_V  0xFFFF
+#define SYSCON_SRAM_ACE1_SIZE_S  0
+
+#define SYSCON_SRAM_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x80)
+/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE2_SIZE    0x0000FFFF
+#define SYSCON_SRAM_ACE2_SIZE_M  ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S))
+#define SYSCON_SRAM_ACE2_SIZE_V  0xFFFF
+#define SYSCON_SRAM_ACE2_SIZE_S  0
+
+#define SYSCON_SRAM_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x84)
+/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: .*/
+#define SYSCON_SRAM_ACE3_SIZE    0x0000FFFF
+#define SYSCON_SRAM_ACE3_SIZE_M  ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S))
+#define SYSCON_SRAM_ACE3_SIZE_V  0xFFFF
+#define SYSCON_SRAM_ACE3_SIZE_S  0
+
+#define SYSCON_SPI_MEM_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x88)
+/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: .*/
+#define SYSCON_SPI_MEM_REJECT_CDE    0x0000001F
+#define SYSCON_SPI_MEM_REJECT_CDE_M  ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
+#define SYSCON_SPI_MEM_REJECT_CDE_V  0x1F
+#define SYSCON_SPI_MEM_REJECT_CDE_S  2
+/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_SPI_MEM_REJECT_CLR    (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_M  (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_V  0x1
+#define SYSCON_SPI_MEM_REJECT_CLR_S  1
+/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_SPI_MEM_REJECT_INT    (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_M  (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_V  0x1
+#define SYSCON_SPI_MEM_REJECT_INT_S  0
+
+#define SYSCON_SPI_MEM_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x8C)
+/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define SYSCON_SPI_MEM_REJECT_ADDR    0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_M  ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
+#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFF
+#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
+
+#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x90)
+/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: .*/
+#define SYSCON_SDIO_WIN_ACCESS_EN    (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
+#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
+
+#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x94)
+/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define SYSCON_REDCY_ANDOR    (BIT(31))
+#define SYSCON_REDCY_ANDOR_M  (BIT(31))
+#define SYSCON_REDCY_ANDOR_V  0x1
+#define SYSCON_REDCY_ANDOR_S  31
+/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: .*/
+#define SYSCON_REDCY_SIG0    0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
+#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_S  0
+
+#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x98)
+/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define SYSCON_REDCY_NANDOR    (BIT(31))
+#define SYSCON_REDCY_NANDOR_M  (BIT(31))
+#define SYSCON_REDCY_NANDOR_V  0x1
+#define SYSCON_REDCY_NANDOR_S  31
+/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: .*/
+#define SYSCON_REDCY_SIG1    0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
+#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_S  0
+
+#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x9C)
+/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_FREQ_MEM_FORCE_PD    (BIT(7))
+#define SYSCON_FREQ_MEM_FORCE_PD_M  (BIT(7))
+#define SYSCON_FREQ_MEM_FORCE_PD_V  0x1
+#define SYSCON_FREQ_MEM_FORCE_PD_S  7
+/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_FREQ_MEM_FORCE_PU    (BIT(6))
+#define SYSCON_FREQ_MEM_FORCE_PU_M  (BIT(6))
+#define SYSCON_FREQ_MEM_FORCE_PU_V  0x1
+#define SYSCON_FREQ_MEM_FORCE_PU_S  6
+/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_DC_MEM_FORCE_PD    (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_V  0x1
+#define SYSCON_DC_MEM_FORCE_PD_S  5
+/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_DC_MEM_FORCE_PU    (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_V  0x1
+#define SYSCON_DC_MEM_FORCE_PU_S  4
+/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_PBUS_MEM_FORCE_PD    (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PD_S  3
+/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_PBUS_MEM_FORCE_PU    (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PU_S  2
+/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_AGC_MEM_FORCE_PD    (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PD_S  1
+/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSCON_AGC_MEM_FORCE_PU    (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PU_S  0
+
+#define SYSCON_SPI_MEM_ECC_CTRL_REG          (DR_REG_SYSCON_BASE + 0xA0)
+/* SYSCON_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
+/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2:
+1024 bytes. 3: 2048 bytes..*/
+#define SYSCON_SRAM_PAGE_SIZE    0x00000003
+#define SYSCON_SRAM_PAGE_SIZE_M  ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S))
+#define SYSCON_SRAM_PAGE_SIZE_V  0x3
+#define SYSCON_SRAM_PAGE_SIZE_S  20
+/* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by
+tes. 3: 2048 bytes..*/
+#define SYSCON_FLASH_PAGE_SIZE    0x00000003
+#define SYSCON_FLASH_PAGE_SIZE_M  ((SYSCON_FLASH_PAGE_SIZE_V)<<(SYSCON_FLASH_PAGE_SIZE_S))
+#define SYSCON_FLASH_PAGE_SIZE_V  0x3
+#define SYSCON_FLASH_PAGE_SIZE_S  18
+
+#define SYSCON_CLKGATE_FORCE_ON_REG          (DR_REG_SYSCON_BASE + 0xA8)
+/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
+/*description: .*/
+#define SYSCON_SRAM_CLKGATE_FORCE_ON    0x000007FF
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0x7FF
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  3
+/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SYSCON_ROM_CLKGATE_FORCE_ON    0x00000007
+#define SYSCON_ROM_CLKGATE_FORCE_ON_M  ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
+#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x7
+#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
+
+#define SYSCON_MEM_POWER_DOWN_REG          (DR_REG_SYSCON_BASE + 0xAC)
+/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
+/*description: .*/
+#define SYSCON_SRAM_POWER_DOWN    0x000007FF
+#define SYSCON_SRAM_POWER_DOWN_M  ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
+#define SYSCON_SRAM_POWER_DOWN_V  0x7FF
+#define SYSCON_SRAM_POWER_DOWN_S  3
+/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: .*/
+#define SYSCON_ROM_POWER_DOWN    0x00000007
+#define SYSCON_ROM_POWER_DOWN_M  ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
+#define SYSCON_ROM_POWER_DOWN_V  0x7
+#define SYSCON_ROM_POWER_DOWN_S  0
+
+#define SYSCON_MEM_POWER_UP_REG          (DR_REG_SYSCON_BASE + 0xB0)
+/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
+/*description: .*/
+#define SYSCON_SRAM_POWER_UP    0x000007FF
+#define SYSCON_SRAM_POWER_UP_M  ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
+#define SYSCON_SRAM_POWER_UP_V  0x7FF
+#define SYSCON_SRAM_POWER_UP_S  3
+/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
+/*description: .*/
+#define SYSCON_ROM_POWER_UP    0x00000007
+#define SYSCON_ROM_POWER_UP_M  ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
+#define SYSCON_ROM_POWER_UP_V  0x7
+#define SYSCON_ROM_POWER_UP_S  0
+
+#define SYSCON_RETENTION_CTRL_REG          (DR_REG_SYSCON_BASE + 0xB4)
+/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_NOBYPASS_CPU_ISO_RST    (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x1
+#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
+/* SYSCON_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: .*/
+#define SYSCON_RETENTION_CPU_LINK_ADDR    0x07FFFFFF
+#define SYSCON_RETENTION_CPU_LINK_ADDR_M  ((SYSCON_RETENTION_CPU_LINK_ADDR_V)<<(SYSCON_RETENTION_CPU_LINK_ADDR_S))
+#define SYSCON_RETENTION_CPU_LINK_ADDR_V  0x7FFFFFF
+#define SYSCON_RETENTION_CPU_LINK_ADDR_S  0
+
+#define SYSCON_RETENTION_CTRL1_REG          (DR_REG_SYSCON_BASE + 0xB8)
+/* SYSCON_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
+/*description: .*/
+#define SYSCON_RETENTION_TAG_LINK_ADDR    0x07FFFFFF
+#define SYSCON_RETENTION_TAG_LINK_ADDR_M  ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S))
+#define SYSCON_RETENTION_TAG_LINK_ADDR_V  0x7FFFFFF
+#define SYSCON_RETENTION_TAG_LINK_ADDR_S  0
+
+#define SYSCON_RETENTION_CTRL2_REG          (DR_REG_SYSCON_BASE + 0xBC)
+/* SYSCON_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_RET_ICACHE_ENABLE    (BIT(31))
+#define SYSCON_RET_ICACHE_ENABLE_M  (BIT(31))
+#define SYSCON_RET_ICACHE_ENABLE_V  0x1
+#define SYSCON_RET_ICACHE_ENABLE_S  31
+/* SYSCON_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
+/*description: .*/
+#define SYSCON_RET_ICACHE_START_POINT    0x000000FF
+#define SYSCON_RET_ICACHE_START_POINT_M  ((SYSCON_RET_ICACHE_START_POINT_V)<<(SYSCON_RET_ICACHE_START_POINT_S))
+#define SYSCON_RET_ICACHE_START_POINT_V  0xFF
+#define SYSCON_RET_ICACHE_START_POINT_S  22
+/* SYSCON_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
+/*description: .*/
+#define SYSCON_RET_ICACHE_VLD_SIZE    0x000000FF
+#define SYSCON_RET_ICACHE_VLD_SIZE_M  ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S))
+#define SYSCON_RET_ICACHE_VLD_SIZE_V  0xFF
+#define SYSCON_RET_ICACHE_VLD_SIZE_S  13
+/* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
+/*description: .*/
+#define SYSCON_RET_ICACHE_SIZE    0x000000FF
+#define SYSCON_RET_ICACHE_SIZE_M  ((SYSCON_RET_ICACHE_SIZE_V)<<(SYSCON_RET_ICACHE_SIZE_S))
+#define SYSCON_RET_ICACHE_SIZE_V  0xFF
+#define SYSCON_RET_ICACHE_SIZE_S  4
+
+#define SYSCON_RETENTION_CTRL3_REG          (DR_REG_SYSCON_BASE + 0xC0)
+/* SYSCON_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_RET_DCACHE_ENABLE    (BIT(31))
+#define SYSCON_RET_DCACHE_ENABLE_M  (BIT(31))
+#define SYSCON_RET_DCACHE_ENABLE_V  0x1
+#define SYSCON_RET_DCACHE_ENABLE_S  31
+/* SYSCON_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
+/*description: .*/
+#define SYSCON_RET_DCACHE_START_POINT    0x000001FF
+#define SYSCON_RET_DCACHE_START_POINT_M  ((SYSCON_RET_DCACHE_START_POINT_V)<<(SYSCON_RET_DCACHE_START_POINT_S))
+#define SYSCON_RET_DCACHE_START_POINT_V  0x1FF
+#define SYSCON_RET_DCACHE_START_POINT_S  22
+/* SYSCON_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
+/*description: .*/
+#define SYSCON_RET_DCACHE_VLD_SIZE    0x000001FF
+#define SYSCON_RET_DCACHE_VLD_SIZE_M  ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S))
+#define SYSCON_RET_DCACHE_VLD_SIZE_V  0x1FF
+#define SYSCON_RET_DCACHE_VLD_SIZE_S  13
+/* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
+/*description: .*/
+#define SYSCON_RET_DCACHE_SIZE    0x000001FF
+#define SYSCON_RET_DCACHE_SIZE_M  ((SYSCON_RET_DCACHE_SIZE_V)<<(SYSCON_RET_DCACHE_SIZE_S))
+#define SYSCON_RET_DCACHE_SIZE_V  0x1FF
+#define SYSCON_RET_DCACHE_SIZE_S  4
+
+#define SYSCON_RETENTION_CTRL4_REG          (DR_REG_SYSCON_BASE + 0xC4)
+/* SYSCON_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */
+/*description: .*/
+#define SYSCON_RETENTION_INV_CFG    0xFFFFFFFF
+#define SYSCON_RETENTION_INV_CFG_M  ((SYSCON_RETENTION_INV_CFG_V)<<(SYSCON_RETENTION_INV_CFG_S))
+#define SYSCON_RETENTION_INV_CFG_V  0xFFFFFFFF
+#define SYSCON_RETENTION_INV_CFG_S  0
+
+#define SYSCON_RETENTION_CTRL5_REG          (DR_REG_SYSCON_BASE + 0xC8)
+/* SYSCON_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSCON_RETENTION_DISABLE    (BIT(0))
+#define SYSCON_RETENTION_DISABLE_M  (BIT(0))
+#define SYSCON_RETENTION_DISABLE_V  0x1
+#define SYSCON_RETENTION_DISABLE_S  0
+
+#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
+/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
+/*description: Version control.*/
+#define SYSCON_DATE    0xFFFFFFFF
+#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
+#define SYSCON_DATE_V  0xFFFFFFFF
+#define SYSCON_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSCON_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/syscon_struct.h b/components/soc/esp32s3/register/soc/syscon_struct.h
similarity index 96%
rename from components/soc/esp32s3/include/soc/syscon_struct.h
rename to components/soc/esp32s3/register/soc/syscon_struct.h
index a392939e422..e01c7153497 100644
--- a/components/soc/esp32s3/include/soc/syscon_struct.h
+++ b/components/soc/esp32s3/register/soc/syscon_struct.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SYSCON_STRUCT_H_
 #define _SOC_SYSCON_STRUCT_H_
 
diff --git a/components/soc/esp32s3/register/soc/system_reg.h b/components/soc/esp32s3/register/soc/system_reg.h
new file mode 100644
index 00000000000..736e90a84a4
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/system_reg.h
@@ -0,0 +1,1084 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSTEM_REG_H_
+#define _SOC_SYSTEM_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SYSTEM_CORE_1_CONTROL_0_REG          (DR_REG_SYSTEM_BASE + 0x0)
+/* SYSTEM_CONTROL_CORE_1_RESETING : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_CONTROL_CORE_1_RESETING    (BIT(2))
+#define SYSTEM_CONTROL_CORE_1_RESETING_M  (BIT(2))
+#define SYSTEM_CONTROL_CORE_1_RESETING_V  0x1
+#define SYSTEM_CONTROL_CORE_1_RESETING_S  2
+/* SYSTEM_CONTROL_CORE_1_CLKGATE_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN    (BIT(1))
+#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M  (BIT(1))
+#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V  0x1
+#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S  1
+/* SYSTEM_CONTROL_CORE_1_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CONTROL_CORE_1_RUNSTALL    (BIT(0))
+#define SYSTEM_CONTROL_CORE_1_RUNSTALL_M  (BIT(0))
+#define SYSTEM_CONTROL_CORE_1_RUNSTALL_V  0x1
+#define SYSTEM_CONTROL_CORE_1_RUNSTALL_S  0
+
+#define SYSTEM_CORE_1_CONTROL_1_REG          (DR_REG_SYSTEM_BASE + 0x4)
+/* SYSTEM_CONTROL_CORE_1_MESSAGE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define SYSTEM_CONTROL_CORE_1_MESSAGE    0xFFFFFFFF
+#define SYSTEM_CONTROL_CORE_1_MESSAGE_M  ((SYSTEM_CONTROL_CORE_1_MESSAGE_V)<<(SYSTEM_CONTROL_CORE_1_MESSAGE_S))
+#define SYSTEM_CONTROL_CORE_1_MESSAGE_V  0xFFFFFFFF
+#define SYSTEM_CONTROL_CORE_1_MESSAGE_S  0
+
+#define SYSTEM_CPU_PERI_CLK_EN_REG          (DR_REG_SYSTEM_BASE + 0x8)
+/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CLK_EN_DEDICATED_GPIO    (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_M  (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_V  0x1
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_S  7
+/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CLK_EN_ASSIST_DEBUG    (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_M  (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_V  0x1
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_S  6
+
+#define SYSTEM_CPU_PERI_RST_EN_REG          (DR_REG_SYSTEM_BASE + 0xC)
+/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_RST_EN_DEDICATED_GPIO    (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_M  (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_V  0x1
+#define SYSTEM_RST_EN_DEDICATED_GPIO_S  7
+/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_RST_EN_ASSIST_DEBUG    (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_M  (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_V  0x1
+#define SYSTEM_RST_EN_ASSIST_DEBUG_S  6
+
+#define SYSTEM_CPU_PER_CONF_REG          (DR_REG_SYSTEM_BASE + 0x10)
+/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: .*/
+#define SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000F
+#define SYSTEM_CPU_WAITI_DELAY_NUM_M  ((SYSTEM_CPU_WAITI_DELAY_NUM_V)<<(SYSTEM_CPU_WAITI_DELAY_NUM_S))
+#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0xF
+#define SYSTEM_CPU_WAITI_DELAY_NUM_S  4
+/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x1
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  3
+/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_PLL_FREQ_SEL    (BIT(2))
+#define SYSTEM_PLL_FREQ_SEL_M  (BIT(2))
+#define SYSTEM_PLL_FREQ_SEL_V  0x1
+#define SYSTEM_PLL_FREQ_SEL_S  2
+/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: .*/
+#define SYSTEM_CPUPERIOD_SEL    0x00000003
+#define SYSTEM_CPUPERIOD_SEL_M  ((SYSTEM_CPUPERIOD_SEL_V)<<(SYSTEM_CPUPERIOD_SEL_S))
+#define SYSTEM_CPUPERIOD_SEL_V  0x3
+#define SYSTEM_CPUPERIOD_SEL_S  0
+
+#define SYSTEM_MEM_PD_MASK_REG          (DR_REG_SYSTEM_BASE + 0x14)
+/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_LSLP_MEM_PD_MASK    (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_M  (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_V  0x1
+#define SYSTEM_LSLP_MEM_PD_MASK_S  0
+
+#define SYSTEM_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x18)
+/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
+/*description: .*/
+#define SYSTEM_SPI4_CLK_EN    (BIT(31))
+#define SYSTEM_SPI4_CLK_EN_M  (BIT(31))
+#define SYSTEM_SPI4_CLK_EN_V  0x1
+#define SYSTEM_SPI4_CLK_EN_S  31
+/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_ADC2_ARB_CLK_EN    (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_M  (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_V  0x1
+#define SYSTEM_ADC2_ARB_CLK_EN_S  30
+/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_SYSTIMER_CLK_EN    (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_M  (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_V  0x1
+#define SYSTEM_SYSTIMER_CLK_EN_S  29
+/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_APB_SARADC_CLK_EN    (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_M  (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_V  0x1
+#define SYSTEM_APB_SARADC_CLK_EN_S  28
+/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_SPI3_DMA_CLK_EN    (BIT(27))
+#define SYSTEM_SPI3_DMA_CLK_EN_M  (BIT(27))
+#define SYSTEM_SPI3_DMA_CLK_EN_V  0x1
+#define SYSTEM_SPI3_DMA_CLK_EN_S  27
+/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PWM3_CLK_EN    (BIT(26))
+#define SYSTEM_PWM3_CLK_EN_M  (BIT(26))
+#define SYSTEM_PWM3_CLK_EN_V  0x1
+#define SYSTEM_PWM3_CLK_EN_S  26
+/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PWM2_CLK_EN    (BIT(25))
+#define SYSTEM_PWM2_CLK_EN_M  (BIT(25))
+#define SYSTEM_PWM2_CLK_EN_V  0x1
+#define SYSTEM_PWM2_CLK_EN_S  25
+/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_UART_MEM_CLK_EN    (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_M  (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_V  0x1
+#define SYSTEM_UART_MEM_CLK_EN_S  24
+/* SYSTEM_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_USB_CLK_EN    (BIT(23))
+#define SYSTEM_USB_CLK_EN_M  (BIT(23))
+#define SYSTEM_USB_CLK_EN_V  0x1
+#define SYSTEM_USB_CLK_EN_S  23
+/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_SPI2_DMA_CLK_EN    (BIT(22))
+#define SYSTEM_SPI2_DMA_CLK_EN_M  (BIT(22))
+#define SYSTEM_SPI2_DMA_CLK_EN_V  0x1
+#define SYSTEM_SPI2_DMA_CLK_EN_S  22
+/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_I2S1_CLK_EN    (BIT(21))
+#define SYSTEM_I2S1_CLK_EN_M  (BIT(21))
+#define SYSTEM_I2S1_CLK_EN_V  0x1
+#define SYSTEM_I2S1_CLK_EN_S  21
+/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PWM1_CLK_EN    (BIT(20))
+#define SYSTEM_PWM1_CLK_EN_M  (BIT(20))
+#define SYSTEM_PWM1_CLK_EN_V  0x1
+#define SYSTEM_PWM1_CLK_EN_S  20
+/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_TWAI_CLK_EN    (BIT(19))
+#define SYSTEM_TWAI_CLK_EN_M  (BIT(19))
+#define SYSTEM_TWAI_CLK_EN_V  0x1
+#define SYSTEM_TWAI_CLK_EN_S  19
+/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_I2C_EXT1_CLK_EN    (BIT(18))
+#define SYSTEM_I2C_EXT1_CLK_EN_M  (BIT(18))
+#define SYSTEM_I2C_EXT1_CLK_EN_V  0x1
+#define SYSTEM_I2C_EXT1_CLK_EN_S  18
+/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PWM0_CLK_EN    (BIT(17))
+#define SYSTEM_PWM0_CLK_EN_M  (BIT(17))
+#define SYSTEM_PWM0_CLK_EN_V  0x1
+#define SYSTEM_PWM0_CLK_EN_S  17
+/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_SPI3_CLK_EN    (BIT(16))
+#define SYSTEM_SPI3_CLK_EN_M  (BIT(16))
+#define SYSTEM_SPI3_CLK_EN_V  0x1
+#define SYSTEM_SPI3_CLK_EN_S  16
+/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_TIMERGROUP1_CLK_EN    (BIT(15))
+#define SYSTEM_TIMERGROUP1_CLK_EN_M  (BIT(15))
+#define SYSTEM_TIMERGROUP1_CLK_EN_V  0x1
+#define SYSTEM_TIMERGROUP1_CLK_EN_S  15
+/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_EFUSE_CLK_EN    (BIT(14))
+#define SYSTEM_EFUSE_CLK_EN_M  (BIT(14))
+#define SYSTEM_EFUSE_CLK_EN_V  0x1
+#define SYSTEM_EFUSE_CLK_EN_S  14
+/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_TIMERGROUP_CLK_EN    (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_M  (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_V  0x1
+#define SYSTEM_TIMERGROUP_CLK_EN_S  13
+/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_UHCI1_CLK_EN    (BIT(12))
+#define SYSTEM_UHCI1_CLK_EN_M  (BIT(12))
+#define SYSTEM_UHCI1_CLK_EN_V  0x1
+#define SYSTEM_UHCI1_CLK_EN_S  12
+/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_LEDC_CLK_EN    (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_M  (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_V  0x1
+#define SYSTEM_LEDC_CLK_EN_S  11
+/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PCNT_CLK_EN    (BIT(10))
+#define SYSTEM_PCNT_CLK_EN_M  (BIT(10))
+#define SYSTEM_PCNT_CLK_EN_V  0x1
+#define SYSTEM_PCNT_CLK_EN_S  10
+/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_RMT_CLK_EN    (BIT(9))
+#define SYSTEM_RMT_CLK_EN_M  (BIT(9))
+#define SYSTEM_RMT_CLK_EN_V  0x1
+#define SYSTEM_RMT_CLK_EN_S  9
+/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_UHCI0_CLK_EN    (BIT(8))
+#define SYSTEM_UHCI0_CLK_EN_M  (BIT(8))
+#define SYSTEM_UHCI0_CLK_EN_V  0x1
+#define SYSTEM_UHCI0_CLK_EN_S  8
+/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_I2C_EXT0_CLK_EN    (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_M  (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_V  0x1
+#define SYSTEM_I2C_EXT0_CLK_EN_S  7
+/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_SPI2_CLK_EN    (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_M  (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_V  0x1
+#define SYSTEM_SPI2_CLK_EN_S  6
+/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_UART1_CLK_EN    (BIT(5))
+#define SYSTEM_UART1_CLK_EN_M  (BIT(5))
+#define SYSTEM_UART1_CLK_EN_V  0x1
+#define SYSTEM_UART1_CLK_EN_S  5
+/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_I2S0_CLK_EN    (BIT(4))
+#define SYSTEM_I2S0_CLK_EN_M  (BIT(4))
+#define SYSTEM_I2S0_CLK_EN_V  0x1
+#define SYSTEM_I2S0_CLK_EN_S  4
+/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_WDG_CLK_EN    (BIT(3))
+#define SYSTEM_WDG_CLK_EN_M  (BIT(3))
+#define SYSTEM_WDG_CLK_EN_V  0x1
+#define SYSTEM_WDG_CLK_EN_S  3
+/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_UART_CLK_EN    (BIT(2))
+#define SYSTEM_UART_CLK_EN_M  (BIT(2))
+#define SYSTEM_UART_CLK_EN_V  0x1
+#define SYSTEM_UART_CLK_EN_S  2
+/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_SPI01_CLK_EN    (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_M  (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_V  0x1
+#define SYSTEM_SPI01_CLK_EN_S  1
+/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_TIMERS_CLK_EN    (BIT(0))
+#define SYSTEM_TIMERS_CLK_EN_M  (BIT(0))
+#define SYSTEM_TIMERS_CLK_EN_V  0x1
+#define SYSTEM_TIMERS_CLK_EN_S  0
+
+#define SYSTEM_PERIP_CLK_EN1_REG          (DR_REG_SYSTEM_BASE + 0x1C)
+/* SYSTEM_USB_DEVICE_CLK_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_USB_DEVICE_CLK_EN    (BIT(10))
+#define SYSTEM_USB_DEVICE_CLK_EN_M  (BIT(10))
+#define SYSTEM_USB_DEVICE_CLK_EN_V  0x1
+#define SYSTEM_USB_DEVICE_CLK_EN_S  10
+/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_UART2_CLK_EN    (BIT(9))
+#define SYSTEM_UART2_CLK_EN_M  (BIT(9))
+#define SYSTEM_UART2_CLK_EN_V  0x1
+#define SYSTEM_UART2_CLK_EN_S  9
+/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_LCD_CAM_CLK_EN    (BIT(8))
+#define SYSTEM_LCD_CAM_CLK_EN_M  (BIT(8))
+#define SYSTEM_LCD_CAM_CLK_EN_V  0x1
+#define SYSTEM_LCD_CAM_CLK_EN_S  8
+/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_SDIO_HOST_CLK_EN    (BIT(7))
+#define SYSTEM_SDIO_HOST_CLK_EN_M  (BIT(7))
+#define SYSTEM_SDIO_HOST_CLK_EN_V  0x1
+#define SYSTEM_SDIO_HOST_CLK_EN_S  7
+/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_DMA_CLK_EN    (BIT(6))
+#define SYSTEM_DMA_CLK_EN_M  (BIT(6))
+#define SYSTEM_DMA_CLK_EN_V  0x1
+#define SYSTEM_DMA_CLK_EN_S  6
+/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_HMAC_CLK_EN    (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_M  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_S  5
+/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_DS_CLK_EN    (BIT(4))
+#define SYSTEM_CRYPTO_DS_CLK_EN_M  (BIT(4))
+#define SYSTEM_CRYPTO_DS_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_DS_CLK_EN_S  4
+/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_RSA_CLK_EN    (BIT(3))
+#define SYSTEM_CRYPTO_RSA_CLK_EN_M  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_RSA_CLK_EN_S  3
+/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_SHA_CLK_EN    (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_M  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_SHA_CLK_EN_S  2
+/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_AES_CLK_EN    (BIT(1))
+#define SYSTEM_CRYPTO_AES_CLK_EN_M  (BIT(1))
+#define SYSTEM_CRYPTO_AES_CLK_EN_V  0x1
+#define SYSTEM_CRYPTO_AES_CLK_EN_S  1
+/* SYSTEM_PERI_BACKUP_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PERI_BACKUP_CLK_EN    (BIT(0))
+#define SYSTEM_PERI_BACKUP_CLK_EN_M  (BIT(0))
+#define SYSTEM_PERI_BACKUP_CLK_EN_V  0x1
+#define SYSTEM_PERI_BACKUP_CLK_EN_S  0
+
+#define SYSTEM_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x20)
+/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: .*/
+#define SYSTEM_SPI4_RST    (BIT(31))
+#define SYSTEM_SPI4_RST_M  (BIT(31))
+#define SYSTEM_SPI4_RST_V  0x1
+#define SYSTEM_SPI4_RST_S  31
+/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_ADC2_ARB_RST    (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_M  (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_V  0x1
+#define SYSTEM_ADC2_ARB_RST_S  30
+/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_SYSTIMER_RST    (BIT(29))
+#define SYSTEM_SYSTIMER_RST_M  (BIT(29))
+#define SYSTEM_SYSTIMER_RST_V  0x1
+#define SYSTEM_SYSTIMER_RST_S  29
+/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_APB_SARADC_RST    (BIT(28))
+#define SYSTEM_APB_SARADC_RST_M  (BIT(28))
+#define SYSTEM_APB_SARADC_RST_V  0x1
+#define SYSTEM_APB_SARADC_RST_S  28
+/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_SPI3_DMA_RST    (BIT(27))
+#define SYSTEM_SPI3_DMA_RST_M  (BIT(27))
+#define SYSTEM_SPI3_DMA_RST_V  0x1
+#define SYSTEM_SPI3_DMA_RST_S  27
+/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PWM3_RST    (BIT(26))
+#define SYSTEM_PWM3_RST_M  (BIT(26))
+#define SYSTEM_PWM3_RST_V  0x1
+#define SYSTEM_PWM3_RST_S  26
+/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PWM2_RST    (BIT(25))
+#define SYSTEM_PWM2_RST_M  (BIT(25))
+#define SYSTEM_PWM2_RST_V  0x1
+#define SYSTEM_PWM2_RST_S  25
+/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_UART_MEM_RST    (BIT(24))
+#define SYSTEM_UART_MEM_RST_M  (BIT(24))
+#define SYSTEM_UART_MEM_RST_V  0x1
+#define SYSTEM_UART_MEM_RST_S  24
+/* SYSTEM_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_USB_RST    (BIT(23))
+#define SYSTEM_USB_RST_M  (BIT(23))
+#define SYSTEM_USB_RST_V  0x1
+#define SYSTEM_USB_RST_S  23
+/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_SPI2_DMA_RST    (BIT(22))
+#define SYSTEM_SPI2_DMA_RST_M  (BIT(22))
+#define SYSTEM_SPI2_DMA_RST_V  0x1
+#define SYSTEM_SPI2_DMA_RST_S  22
+/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_I2S1_RST    (BIT(21))
+#define SYSTEM_I2S1_RST_M  (BIT(21))
+#define SYSTEM_I2S1_RST_V  0x1
+#define SYSTEM_I2S1_RST_S  21
+/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PWM1_RST    (BIT(20))
+#define SYSTEM_PWM1_RST_M  (BIT(20))
+#define SYSTEM_PWM1_RST_V  0x1
+#define SYSTEM_PWM1_RST_S  20
+/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_TWAI_RST    (BIT(19))
+#define SYSTEM_TWAI_RST_M  (BIT(19))
+#define SYSTEM_TWAI_RST_V  0x1
+#define SYSTEM_TWAI_RST_S  19
+/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_I2C_EXT1_RST    (BIT(18))
+#define SYSTEM_I2C_EXT1_RST_M  (BIT(18))
+#define SYSTEM_I2C_EXT1_RST_V  0x1
+#define SYSTEM_I2C_EXT1_RST_S  18
+/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PWM0_RST    (BIT(17))
+#define SYSTEM_PWM0_RST_M  (BIT(17))
+#define SYSTEM_PWM0_RST_V  0x1
+#define SYSTEM_PWM0_RST_S  17
+/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_SPI3_RST    (BIT(16))
+#define SYSTEM_SPI3_RST_M  (BIT(16))
+#define SYSTEM_SPI3_RST_V  0x1
+#define SYSTEM_SPI3_RST_S  16
+/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_TIMERGROUP1_RST    (BIT(15))
+#define SYSTEM_TIMERGROUP1_RST_M  (BIT(15))
+#define SYSTEM_TIMERGROUP1_RST_V  0x1
+#define SYSTEM_TIMERGROUP1_RST_S  15
+/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_EFUSE_RST    (BIT(14))
+#define SYSTEM_EFUSE_RST_M  (BIT(14))
+#define SYSTEM_EFUSE_RST_V  0x1
+#define SYSTEM_EFUSE_RST_S  14
+/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_TIMERGROUP_RST    (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_M  (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_V  0x1
+#define SYSTEM_TIMERGROUP_RST_S  13
+/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_UHCI1_RST    (BIT(12))
+#define SYSTEM_UHCI1_RST_M  (BIT(12))
+#define SYSTEM_UHCI1_RST_V  0x1
+#define SYSTEM_UHCI1_RST_S  12
+/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_LEDC_RST    (BIT(11))
+#define SYSTEM_LEDC_RST_M  (BIT(11))
+#define SYSTEM_LEDC_RST_V  0x1
+#define SYSTEM_LEDC_RST_S  11
+/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PCNT_RST    (BIT(10))
+#define SYSTEM_PCNT_RST_M  (BIT(10))
+#define SYSTEM_PCNT_RST_V  0x1
+#define SYSTEM_PCNT_RST_S  10
+/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_RMT_RST    (BIT(9))
+#define SYSTEM_RMT_RST_M  (BIT(9))
+#define SYSTEM_RMT_RST_V  0x1
+#define SYSTEM_RMT_RST_S  9
+/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_UHCI0_RST    (BIT(8))
+#define SYSTEM_UHCI0_RST_M  (BIT(8))
+#define SYSTEM_UHCI0_RST_V  0x1
+#define SYSTEM_UHCI0_RST_S  8
+/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_I2C_EXT0_RST    (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_M  (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_V  0x1
+#define SYSTEM_I2C_EXT0_RST_S  7
+/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_SPI2_RST    (BIT(6))
+#define SYSTEM_SPI2_RST_M  (BIT(6))
+#define SYSTEM_SPI2_RST_V  0x1
+#define SYSTEM_SPI2_RST_S  6
+/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_UART1_RST    (BIT(5))
+#define SYSTEM_UART1_RST_M  (BIT(5))
+#define SYSTEM_UART1_RST_V  0x1
+#define SYSTEM_UART1_RST_S  5
+/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_I2S0_RST    (BIT(4))
+#define SYSTEM_I2S0_RST_M  (BIT(4))
+#define SYSTEM_I2S0_RST_V  0x1
+#define SYSTEM_I2S0_RST_S  4
+/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_WDG_RST    (BIT(3))
+#define SYSTEM_WDG_RST_M  (BIT(3))
+#define SYSTEM_WDG_RST_V  0x1
+#define SYSTEM_WDG_RST_S  3
+/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_UART_RST    (BIT(2))
+#define SYSTEM_UART_RST_M  (BIT(2))
+#define SYSTEM_UART_RST_V  0x1
+#define SYSTEM_UART_RST_S  2
+/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_SPI01_RST    (BIT(1))
+#define SYSTEM_SPI01_RST_M  (BIT(1))
+#define SYSTEM_SPI01_RST_V  0x1
+#define SYSTEM_SPI01_RST_S  1
+/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_TIMERS_RST    (BIT(0))
+#define SYSTEM_TIMERS_RST_M  (BIT(0))
+#define SYSTEM_TIMERS_RST_V  0x1
+#define SYSTEM_TIMERS_RST_S  0
+
+#define SYSTEM_PERIP_RST_EN1_REG          (DR_REG_SYSTEM_BASE + 0x24)
+/* SYSTEM_USB_DEVICE_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_USB_DEVICE_RST    (BIT(10))
+#define SYSTEM_USB_DEVICE_RST_M  (BIT(10))
+#define SYSTEM_USB_DEVICE_RST_V  0x1
+#define SYSTEM_USB_DEVICE_RST_S  10
+/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_UART2_RST    (BIT(9))
+#define SYSTEM_UART2_RST_M  (BIT(9))
+#define SYSTEM_UART2_RST_V  0x1
+#define SYSTEM_UART2_RST_S  9
+/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_LCD_CAM_RST    (BIT(8))
+#define SYSTEM_LCD_CAM_RST_M  (BIT(8))
+#define SYSTEM_LCD_CAM_RST_V  0x1
+#define SYSTEM_LCD_CAM_RST_S  8
+/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_SDIO_HOST_RST    (BIT(7))
+#define SYSTEM_SDIO_HOST_RST_M  (BIT(7))
+#define SYSTEM_SDIO_HOST_RST_V  0x1
+#define SYSTEM_SDIO_HOST_RST_S  7
+/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_DMA_RST    (BIT(6))
+#define SYSTEM_DMA_RST_M  (BIT(6))
+#define SYSTEM_DMA_RST_V  0x1
+#define SYSTEM_DMA_RST_S  6
+/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_HMAC_RST    (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_RST_M  (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_RST_V  0x1
+#define SYSTEM_CRYPTO_HMAC_RST_S  5
+/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_DS_RST    (BIT(4))
+#define SYSTEM_CRYPTO_DS_RST_M  (BIT(4))
+#define SYSTEM_CRYPTO_DS_RST_V  0x1
+#define SYSTEM_CRYPTO_DS_RST_S  4
+/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_RSA_RST    (BIT(3))
+#define SYSTEM_CRYPTO_RSA_RST_M  (BIT(3))
+#define SYSTEM_CRYPTO_RSA_RST_V  0x1
+#define SYSTEM_CRYPTO_RSA_RST_S  3
+/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_SHA_RST    (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_M  (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_V  0x1
+#define SYSTEM_CRYPTO_SHA_RST_S  2
+/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_CRYPTO_AES_RST    (BIT(1))
+#define SYSTEM_CRYPTO_AES_RST_M  (BIT(1))
+#define SYSTEM_CRYPTO_AES_RST_V  0x1
+#define SYSTEM_CRYPTO_AES_RST_S  1
+/* SYSTEM_PERI_BACKUP_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_PERI_BACKUP_RST    (BIT(0))
+#define SYSTEM_PERI_BACKUP_RST_M  (BIT(0))
+#define SYSTEM_PERI_BACKUP_RST_V  0x1
+#define SYSTEM_PERI_BACKUP_RST_S  0
+
+#define SYSTEM_BT_LPCK_DIV_INT_REG          (DR_REG_SYSTEM_BASE + 0x28)
+/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
+/*description: .*/
+#define SYSTEM_BT_LPCK_DIV_NUM    0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_NUM_M  ((SYSTEM_BT_LPCK_DIV_NUM_V)<<(SYSTEM_BT_LPCK_DIV_NUM_S))
+#define SYSTEM_BT_LPCK_DIV_NUM_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_NUM_S  0
+
+#define SYSTEM_BT_LPCK_DIV_FRAC_REG          (DR_REG_SYSTEM_BASE + 0x2C)
+/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_LPCLK_RTC_EN    (BIT(28))
+#define SYSTEM_LPCLK_RTC_EN_M  (BIT(28))
+#define SYSTEM_LPCLK_RTC_EN_V  0x1
+#define SYSTEM_LPCLK_RTC_EN_S  28
+/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_LPCLK_SEL_XTAL32K    (BIT(27))
+#define SYSTEM_LPCLK_SEL_XTAL32K_M  (BIT(27))
+#define SYSTEM_LPCLK_SEL_XTAL32K_V  0x1
+#define SYSTEM_LPCLK_SEL_XTAL32K_S  27
+/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_LPCLK_SEL_XTAL    (BIT(26))
+#define SYSTEM_LPCLK_SEL_XTAL_M  (BIT(26))
+#define SYSTEM_LPCLK_SEL_XTAL_V  0x1
+#define SYSTEM_LPCLK_SEL_XTAL_S  26
+/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_LPCLK_SEL_8M    (BIT(25))
+#define SYSTEM_LPCLK_SEL_8M_M  (BIT(25))
+#define SYSTEM_LPCLK_SEL_8M_V  0x1
+#define SYSTEM_LPCLK_SEL_8M_S  25
+/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_LPCLK_SEL_RTC_SLOW    (BIT(24))
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_V  0x1
+#define SYSTEM_LPCLK_SEL_RTC_SLOW_S  24
+/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
+/*description: .*/
+#define SYSTEM_BT_LPCK_DIV_A    0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_A_M  ((SYSTEM_BT_LPCK_DIV_A_V)<<(SYSTEM_BT_LPCK_DIV_A_S))
+#define SYSTEM_BT_LPCK_DIV_A_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_A_S  12
+/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
+/*description: .*/
+#define SYSTEM_BT_LPCK_DIV_B    0x00000FFF
+#define SYSTEM_BT_LPCK_DIV_B_M  ((SYSTEM_BT_LPCK_DIV_B_V)<<(SYSTEM_BT_LPCK_DIV_B_S))
+#define SYSTEM_BT_LPCK_DIV_B_V  0xFFF
+#define SYSTEM_BT_LPCK_DIV_B_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_0_REG          (DR_REG_SYSTEM_BASE + 0x30)
+/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CPU_INTR_FROM_CPU_0    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_0_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_1_REG          (DR_REG_SYSTEM_BASE + 0x34)
+/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CPU_INTR_FROM_CPU_1    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_1_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_2_REG          (DR_REG_SYSTEM_BASE + 0x38)
+/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CPU_INTR_FROM_CPU_2    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_2_S  0
+
+#define SYSTEM_CPU_INTR_FROM_CPU_3_REG          (DR_REG_SYSTEM_BASE + 0x3C)
+/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_CPU_INTR_FROM_CPU_3    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_M  (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_V  0x1
+#define SYSTEM_CPU_INTR_FROM_CPU_3_S  0
+
+#define SYSTEM_RSA_PD_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x40)
+/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_RSA_MEM_FORCE_PD    (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_M  (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_V  0x1
+#define SYSTEM_RSA_MEM_FORCE_PD_S  2
+/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_RSA_MEM_FORCE_PU    (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_M  (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_V  0x1
+#define SYSTEM_RSA_MEM_FORCE_PU_S  1
+/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_RSA_MEM_PD    (BIT(0))
+#define SYSTEM_RSA_MEM_PD_M  (BIT(0))
+#define SYSTEM_RSA_MEM_PD_V  0x1
+#define SYSTEM_RSA_MEM_PD_S  0
+
+#define SYSTEM_EDMA_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x44)
+/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_EDMA_RESET    (BIT(1))
+#define SYSTEM_EDMA_RESET_M  (BIT(1))
+#define SYSTEM_EDMA_RESET_V  0x1
+#define SYSTEM_EDMA_RESET_S  1
+/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_EDMA_CLK_ON    (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_M  (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_V  0x1
+#define SYSTEM_EDMA_CLK_ON_S  0
+
+#define SYSTEM_CACHE_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x48)
+/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_DCACHE_RESET    (BIT(3))
+#define SYSTEM_DCACHE_RESET_M  (BIT(3))
+#define SYSTEM_DCACHE_RESET_V  0x1
+#define SYSTEM_DCACHE_RESET_S  3
+/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_DCACHE_CLK_ON    (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_M  (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_V  0x1
+#define SYSTEM_DCACHE_CLK_ON_S  2
+/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_ICACHE_RESET    (BIT(1))
+#define SYSTEM_ICACHE_RESET_M  (BIT(1))
+#define SYSTEM_ICACHE_RESET_V  0x1
+#define SYSTEM_ICACHE_RESET_S  1
+/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_ICACHE_CLK_ON    (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_M  (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_V  0x1
+#define SYSTEM_ICACHE_CLK_ON_S  0
+
+#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x4C)
+/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x1
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+
+#define SYSTEM_RTC_FASTMEM_CONFIG_REG          (DR_REG_SYSTEM_BASE + 0x50)
+/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_RTC_MEM_CRC_FINISH    (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_M  (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_V  0x1
+#define SYSTEM_RTC_MEM_CRC_FINISH_S  31
+/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
+/*description: .*/
+#define SYSTEM_RTC_MEM_CRC_LEN    0x000007FF
+#define SYSTEM_RTC_MEM_CRC_LEN_M  ((SYSTEM_RTC_MEM_CRC_LEN_V)<<(SYSTEM_RTC_MEM_CRC_LEN_S))
+#define SYSTEM_RTC_MEM_CRC_LEN_V  0x7FF
+#define SYSTEM_RTC_MEM_CRC_LEN_S  20
+/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
+/*description: .*/
+#define SYSTEM_RTC_MEM_CRC_ADDR    0x000007FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_M  ((SYSTEM_RTC_MEM_CRC_ADDR_V)<<(SYSTEM_RTC_MEM_CRC_ADDR_S))
+#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x7FF
+#define SYSTEM_RTC_MEM_CRC_ADDR_S  9
+/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_RTC_MEM_CRC_START    (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_M  (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_V  0x1
+#define SYSTEM_RTC_MEM_CRC_START_S  8
+
+#define SYSTEM_RTC_FASTMEM_CRC_REG          (DR_REG_SYSTEM_BASE + 0x54)
+/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: .*/
+#define SYSTEM_RTC_MEM_CRC_RES    0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_M  ((SYSTEM_RTC_MEM_CRC_RES_V)<<(SYSTEM_RTC_MEM_CRC_RES_S))
+#define SYSTEM_RTC_MEM_CRC_RES_V  0xFFFFFFFF
+#define SYSTEM_RTC_MEM_CRC_RES_S  0
+
+#define SYSTEM_REDUNDANT_ECO_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x58)
+/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_REDUNDANT_ECO_RESULT    (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_M  (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_V  0x1
+#define SYSTEM_REDUNDANT_ECO_RESULT_S  1
+/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_REDUNDANT_ECO_DRIVE    (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_M  (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_V  0x1
+#define SYSTEM_REDUNDANT_ECO_DRIVE_S  0
+
+#define SYSTEM_CLOCK_GATE_REG          (DR_REG_SYSTEM_BASE + 0x5C)
+/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define SYSTEM_CLK_EN    (BIT(0))
+#define SYSTEM_CLK_EN_M  (BIT(0))
+#define SYSTEM_CLK_EN_V  0x1
+#define SYSTEM_CLK_EN_S  0
+
+#define SYSTEM_SYSCLK_CONF_REG          (DR_REG_SYSTEM_BASE + 0x60)
+/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: .*/
+#define SYSTEM_CLK_DIV_EN    (BIT(19))
+#define SYSTEM_CLK_DIV_EN_M  (BIT(19))
+#define SYSTEM_CLK_DIV_EN_V  0x1
+#define SYSTEM_CLK_DIV_EN_S  19
+/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */
+/*description: .*/
+#define SYSTEM_CLK_XTAL_FREQ    0x0000007F
+#define SYSTEM_CLK_XTAL_FREQ_M  ((SYSTEM_CLK_XTAL_FREQ_V)<<(SYSTEM_CLK_XTAL_FREQ_S))
+#define SYSTEM_CLK_XTAL_FREQ_V  0x7F
+#define SYSTEM_CLK_XTAL_FREQ_S  12
+/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: .*/
+#define SYSTEM_SOC_CLK_SEL    0x00000003
+#define SYSTEM_SOC_CLK_SEL_M  ((SYSTEM_SOC_CLK_SEL_V)<<(SYSTEM_SOC_CLK_SEL_S))
+#define SYSTEM_SOC_CLK_SEL_V  0x3
+#define SYSTEM_SOC_CLK_SEL_S  10
+/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
+/*description: .*/
+#define SYSTEM_PRE_DIV_CNT    0x000003FF
+#define SYSTEM_PRE_DIV_CNT_M  ((SYSTEM_PRE_DIV_CNT_V)<<(SYSTEM_PRE_DIV_CNT_S))
+#define SYSTEM_PRE_DIV_CNT_V  0x3FF
+#define SYSTEM_PRE_DIV_CNT_S  0
+
+#define SYSTEM_MEM_PVT_REG          (DR_REG_SYSTEM_BASE + 0x64)
+/* SYSTEM_MEM_VT_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: .*/
+#define SYSTEM_MEM_VT_SEL    0x00000003
+#define SYSTEM_MEM_VT_SEL_M  ((SYSTEM_MEM_VT_SEL_V)<<(SYSTEM_MEM_VT_SEL_S))
+#define SYSTEM_MEM_VT_SEL_V  0x3
+#define SYSTEM_MEM_VT_SEL_S  22
+/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_MEM_TIMING_ERR_CNT    0x0000FFFF
+#define SYSTEM_MEM_TIMING_ERR_CNT_M  ((SYSTEM_MEM_TIMING_ERR_CNT_V)<<(SYSTEM_MEM_TIMING_ERR_CNT_S))
+#define SYSTEM_MEM_TIMING_ERR_CNT_V  0xFFFF
+#define SYSTEM_MEM_TIMING_ERR_CNT_S  6
+/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_MEM_PVT_MONITOR_EN    (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_M  (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_V  0x1
+#define SYSTEM_MEM_PVT_MONITOR_EN_S  5
+/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_MEM_ERR_CNT_CLR    (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_M  (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_V  0x1
+#define SYSTEM_MEM_ERR_CNT_CLR_S  4
+/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */
+/*description: .*/
+#define SYSTEM_MEM_PATH_LEN    0x0000000F
+#define SYSTEM_MEM_PATH_LEN_M  ((SYSTEM_MEM_PATH_LEN_V)<<(SYSTEM_MEM_PATH_LEN_S))
+#define SYSTEM_MEM_PATH_LEN_V  0xF
+#define SYSTEM_MEM_PATH_LEN_S  0
+
+#define SYSTEM_COMB_PVT_LVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x68)
+/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT    (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT    (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S  5
+/* SYSTEM_COMB_PATH_LEN_LVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: .*/
+#define SYSTEM_COMB_PATH_LEN_LVT    0x0000001F
+#define SYSTEM_COMB_PATH_LEN_LVT_M  ((SYSTEM_COMB_PATH_LEN_LVT_V)<<(SYSTEM_COMB_PATH_LEN_LVT_S))
+#define SYSTEM_COMB_PATH_LEN_LVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_LVT_S  0
+
+#define SYSTEM_COMB_PVT_NVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x6C)
+/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT    (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT    (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S  5
+/* SYSTEM_COMB_PATH_LEN_NVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: .*/
+#define SYSTEM_COMB_PATH_LEN_NVT    0x0000001F
+#define SYSTEM_COMB_PATH_LEN_NVT_M  ((SYSTEM_COMB_PATH_LEN_NVT_V)<<(SYSTEM_COMB_PATH_LEN_NVT_S))
+#define SYSTEM_COMB_PATH_LEN_NVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_NVT_S  0
+
+#define SYSTEM_COMB_PVT_HVT_CONF_REG          (DR_REG_SYSTEM_BASE + 0x70)
+/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT    (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M  (BIT(6))
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V  0x1
+#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S  6
+/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT    (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M  (BIT(5))
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V  0x1
+#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S  5
+/* SYSTEM_COMB_PATH_LEN_HVT : R/W ;bitpos:[4:0] ;default: 5'h3 ; */
+/*description: .*/
+#define SYSTEM_COMB_PATH_LEN_HVT    0x0000001F
+#define SYSTEM_COMB_PATH_LEN_HVT_M  ((SYSTEM_COMB_PATH_LEN_HVT_V)<<(SYSTEM_COMB_PATH_LEN_HVT_S))
+#define SYSTEM_COMB_PATH_LEN_HVT_V  0x1F
+#define SYSTEM_COMB_PATH_LEN_HVT_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x74)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x78)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG          (DR_REG_SYSTEM_BASE + 0x7C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x80)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x84)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG          (DR_REG_SYSTEM_BASE + 0x88)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x8C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x90)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG          (DR_REG_SYSTEM_BASE + 0x94)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S  0
+
+#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x98)
+/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S  0
+
+#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0x9C)
+/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S  0
+
+#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG          (DR_REG_SYSTEM_BASE + 0xA0)
+/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3    0x0000FFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M  ((SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V)<<(SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S))
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V  0xFFFF
+#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S  0
+
+#define SYSTEM_DATE_REG          (DR_REG_SYSTEM_BASE + 0xFFC)
+/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101220 ; */
+/*description: .*/
+#define SYSTEM_DATE    0x0FFFFFFF
+#define SYSTEM_DATE_M  ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
+#define SYSTEM_DATE_V  0xFFFFFFF
+#define SYSTEM_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_REG_H_ */
diff --git a/components/soc/esp32s3/register/soc/system_struct.h b/components/soc/esp32s3/register/soc/system_struct.h
new file mode 100644
index 00000000000..b0e5f2a712e
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/system_struct.h
@@ -0,0 +1,1412 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_SYSTEM_STRUCT_H_
+#define _SOC_SYSTEM_STRUCT_H_
+
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct system_dev_s {
+    union {
+        struct {
+            uint32_t control_core_1_runstall       :    1;
+            uint32_t control_core_1_clkgate_en     :    1;
+            uint32_t control_core_1_reseting       :    1;
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } core_1_control_0;
+    uint32_t core_1_control_1;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;
+            uint32_t clk_en_assist_debug           :    1;
+            uint32_t clk_en_dedicated_gpio         :    1;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } cpu_peri_clk_en;
+    union {
+        struct {
+            uint32_t reserved0                     :    6;
+            uint32_t rst_en_assist_debug           :    1;
+            uint32_t rst_en_dedicated_gpio         :    1;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } cpu_peri_rst_en;
+    union {
+        struct {
+            uint32_t cpuperiod_sel                 :    2;
+            uint32_t pll_freq_sel                  :    1;
+            uint32_t cpu_wait_mode_force_on        :    1;
+            uint32_t cpu_waiti_delay_num           :    4;
+            uint32_t reserved8                     :    24;
+        };
+        uint32_t val;
+    } cpu_per_conf;
+    union {
+        struct {
+            uint32_t lslp_mem_pd_mask              :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } mem_pd_mask;
+    union {
+        struct {
+            uint32_t timers_clk_en                 :    1;
+            uint32_t spi01_clk_en                  :    1;
+            uint32_t uart_clk_en                   :    1;
+            uint32_t wdg_clk_en                    :    1;
+            uint32_t i2s0_clk_en                   :    1;
+            uint32_t uart1_clk_en                  :    1;
+            uint32_t spi2_clk_en                   :    1;
+            uint32_t i2c_ext0_clk_en               :    1;
+            uint32_t uhci0_clk_en                  :    1;
+            uint32_t rmt_clk_en                    :    1;
+            uint32_t pcnt_clk_en                   :    1;
+            uint32_t ledc_clk_en                   :    1;
+            uint32_t uhci1_clk_en                  :    1;
+            uint32_t timergroup_clk_en             :    1;
+            uint32_t efuse_clk_en                  :    1;
+            uint32_t timergroup1_clk_en            :    1;
+            uint32_t spi3_clk_en                   :    1;
+            uint32_t pwm0_clk_en                   :    1;
+            uint32_t i2c_ext1_clk_en               :    1;
+            uint32_t can_clk_en                    :    1;
+            uint32_t pwm1_clk_en                   :    1;
+            uint32_t i2s1_clk_en                   :    1;
+            uint32_t spi2_dma_clk_en               :    1;
+            uint32_t usb_clk_en                    :    1;
+            uint32_t uart_mem_clk_en               :    1;
+            uint32_t pwm2_clk_en                   :    1;
+            uint32_t pwm3_clk_en                   :    1;
+            uint32_t spi3_dma_clk_en               :    1;
+            uint32_t apb_saradc_clk_en             :    1;
+            uint32_t systimer_clk_en               :    1;
+            uint32_t adc2_arb_clk_en               :    1;
+            uint32_t spi4_clk_en                   :    1;
+        };
+        uint32_t val;
+    } perip_clk_en0;
+    union {
+        struct {
+            uint32_t peri_backup_clk_en            :    1;
+            uint32_t crypto_aes_clk_en             :    1;
+            uint32_t crypto_sha_clk_en             :    1;
+            uint32_t crypto_rsa_clk_en             :    1;
+            uint32_t crypto_ds_clk_en              :    1;
+            uint32_t crypto_hmac_clk_en            :    1;
+            uint32_t dma_clk_en                    :    1;
+            uint32_t sdio_host_clk_en              :    1;
+            uint32_t lcd_cam_clk_en                :    1;
+            uint32_t uart2_clk_en                  :    1;
+            uint32_t usb_device_clk_en             :    1;
+            uint32_t reserved11                    :    21;
+        };
+        uint32_t val;
+    } perip_clk_en1;
+    union {
+        struct {
+            uint32_t timers_rst                    :    1;
+            uint32_t spi01_rst                     :    1;
+            uint32_t uart_rst                      :    1;
+            uint32_t wdg_rst                       :    1;
+            uint32_t i2s0_rst                      :    1;
+            uint32_t uart1_rst                     :    1;
+            uint32_t spi2_rst                      :    1;
+            uint32_t i2c_ext0_rst                  :    1;
+            uint32_t uhci0_rst                     :    1;
+            uint32_t rmt_rst                       :    1;
+            uint32_t pcnt_rst                      :    1;
+            uint32_t ledc_rst                      :    1;
+            uint32_t uhci1_rst                     :    1;
+            uint32_t timergroup_rst                :    1;
+            uint32_t efuse_rst                     :    1;
+            uint32_t timergroup1_rst               :    1;
+            uint32_t spi3_rst                      :    1;
+            uint32_t pwm0_rst                      :    1;
+            uint32_t i2c_ext1_rst                  :    1;
+            uint32_t can_rst                       :    1;
+            uint32_t pwm1_rst                      :    1;
+            uint32_t i2s1_rst                      :    1;
+            uint32_t spi2_dma_rst                  :    1;
+            uint32_t usb_rst                       :    1;
+            uint32_t uart_mem_rst                  :    1;
+            uint32_t pwm2_rst                      :    1;
+            uint32_t pwm3_rst                      :    1;
+            uint32_t spi3_dma_rst                  :    1;
+            uint32_t apb_saradc_rst                :    1;
+            uint32_t systimer_rst                  :    1;
+            uint32_t adc2_arb_rst                  :    1;
+            uint32_t spi4_rst                      :    1;
+        };
+        uint32_t val;
+    } perip_rst_en0;
+    union {
+        struct {
+            uint32_t peri_backup_rst               :    1;
+            uint32_t crypto_aes_rst                :    1;
+            uint32_t crypto_sha_rst                :    1;
+            uint32_t crypto_rsa_rst                :    1;
+            uint32_t crypto_ds_rst                 :    1;
+            uint32_t crypto_hmac_rst               :    1;
+            uint32_t dma_rst                       :    1;
+            uint32_t sdio_host_rst                 :    1;
+            uint32_t lcd_cam_rst                   :    1;
+            uint32_t uart2_rst                     :    1;
+            uint32_t usb_device_rst                :    1;
+            uint32_t reserved11                    :    21;
+        };
+        uint32_t val;
+    } perip_rst_en1;
+    union {
+        struct {
+            uint32_t bt_lpck_div_num               :    12;
+            uint32_t reserved12                    :    20;
+        };
+        uint32_t val;
+    } bt_lpck_div_int;
+    union {
+        struct {
+            uint32_t bt_lpck_div_b                 :    12;
+            uint32_t bt_lpck_div_a                 :    12;
+            uint32_t lpclk_sel_rtc_slow            :    1;
+            uint32_t lpclk_sel_8m                  :    1;
+            uint32_t lpclk_sel_xtal                :    1;
+            uint32_t lpclk_sel_xtal32k             :    1;
+            uint32_t lpclk_rtc_en                  :    1;
+            uint32_t reserved29                    :    3;
+        };
+        uint32_t val;
+    } bt_lpck_div_frac;
+    union {
+        struct {
+            uint32_t cpu_intr_from_cpu_0           :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_0;
+    union {
+        struct {
+            uint32_t cpu_intr_from_cpu_1           :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_1;
+    union {
+        struct {
+            uint32_t cpu_intr_from_cpu_2           :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_2;
+    union {
+        struct {
+            uint32_t cpu_intr_from_cpu_3           :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } cpu_intr_from_cpu_3;
+    union {
+        struct {
+            uint32_t rsa_mem_pd                    :    1;
+            uint32_t rsa_mem_force_pu              :    1;
+            uint32_t rsa_mem_force_pd              :    1;
+            uint32_t reserved3                     :    29;
+        };
+        uint32_t val;
+    } rsa_pd_ctrl;
+    union {
+        struct {
+            uint32_t edma_clk_on                   :    1;
+            uint32_t edma_reset                    :    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } edma_ctrl;
+    union {
+        struct {
+            uint32_t icache_clk_on                 :    1;
+            uint32_t icache_reset                  :    1;
+            uint32_t dcache_clk_on                 :    1;
+            uint32_t dcache_reset                  :    1;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } cache_control;
+    union {
+        struct {
+            uint32_t enable_spi_manual_encrypt     :    1;
+            uint32_t enable_download_db_encrypt    :    1;
+            uint32_t enable_download_g0cb_decrypt  :    1;
+            uint32_t enable_download_manual_encrypt:    1;
+            uint32_t reserved4                     :    28;
+        };
+        uint32_t val;
+    } external_device_encrypt_decrypt_control;
+    union {
+        struct {
+            uint32_t reserved0                     :    8;
+            uint32_t rtc_mem_crc_start             :    1;
+            uint32_t rtc_mem_crc_addr              :    11;
+            uint32_t rtc_mem_crc_len               :    11;
+            uint32_t rtc_mem_crc_finish            :    1;
+        };
+        uint32_t val;
+    } rtc_fastmem_config;
+    uint32_t rtc_fastmem_crc;
+    union {
+        struct {
+            uint32_t redundant_eco_drive           :    1;
+            uint32_t redundant_eco_result          :    1;
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } redundant_eco_ctrl;
+    union {
+        struct {
+            uint32_t clk_en                        :    1;
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } clock_gate;
+    union {
+        struct {
+            uint32_t pre_div_cnt                   :    10;
+            uint32_t soc_clk_sel                   :    2;
+            uint32_t clk_xtal_freq                 :    7;
+            uint32_t clk_div_en                    :    1;
+            uint32_t reserved20                    :    12;
+        };
+        uint32_t val;
+    } sysclk_conf;
+    union {
+        struct {
+            uint32_t mem_path_len                  :    4;
+            uint32_t mem_err_cnt_clr               :    1;
+            uint32_t mem_pvt_monitor_en            :    1;
+            uint32_t mem_timing_err_cnt            :    16;
+            uint32_t mem_vt_sel                    :    2;
+            uint32_t reserved24                    :    8;
+        };
+        uint32_t val;
+    } mem_pvt;
+    union {
+        struct {
+            uint32_t comb_path_len_lvt             :    5;
+            uint32_t comb_err_cnt_clr_lvt          :    1;
+            uint32_t comb_pvt_monitor_en_lvt       :    1;
+            uint32_t reserved7                     :    18;
+            uint32_t reserved25                    :    7;
+        };
+        uint32_t val;
+    } comb_pvt_lvt_conf;
+    union {
+        struct {
+            uint32_t comb_path_len_nvt             :    5;
+            uint32_t comb_err_cnt_clr_nvt          :    1;
+            uint32_t comb_pvt_monitor_en_nvt       :    1;
+            uint32_t reserved7                     :    18;
+            uint32_t reserved25                    :    7;
+        };
+        uint32_t val;
+    } comb_pvt_nvt_conf;
+    union {
+        struct {
+            uint32_t comb_path_len_hvt             :    5;
+            uint32_t comb_err_cnt_clr_hvt          :    1;
+            uint32_t comb_pvt_monitor_en_hvt       :    1;
+            uint32_t reserved7                     :    18;
+            uint32_t reserved25                    :    7;
+        };
+        uint32_t val;
+    } comb_pvt_hvt_conf;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_lvt_site0 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site0;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_nvt_site0 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site0;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_hvt_site0 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site0;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_lvt_site1 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site1;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_nvt_site1 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site1;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_hvt_site1 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site1;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_lvt_site2 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site2;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_nvt_site2 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site2;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_hvt_site2 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site2;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_lvt_site3 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_lvt_site3;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_nvt_site3 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_nvt_site3;
+    union {
+        struct {
+            uint32_t comb_timing_err_cnt_hvt_site3 :    16;
+            uint32_t reserved16                    :    16;
+        };
+        uint32_t val;
+    } comb_pvt_err_hvt_site3;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t reserved_3fc;
+    uint32_t reserved_400;
+    uint32_t reserved_404;
+    uint32_t reserved_408;
+    uint32_t reserved_40c;
+    uint32_t reserved_410;
+    uint32_t reserved_414;
+    uint32_t reserved_418;
+    uint32_t reserved_41c;
+    uint32_t reserved_420;
+    uint32_t reserved_424;
+    uint32_t reserved_428;
+    uint32_t reserved_42c;
+    uint32_t reserved_430;
+    uint32_t reserved_434;
+    uint32_t reserved_438;
+    uint32_t reserved_43c;
+    uint32_t reserved_440;
+    uint32_t reserved_444;
+    uint32_t reserved_448;
+    uint32_t reserved_44c;
+    uint32_t reserved_450;
+    uint32_t reserved_454;
+    uint32_t reserved_458;
+    uint32_t reserved_45c;
+    uint32_t reserved_460;
+    uint32_t reserved_464;
+    uint32_t reserved_468;
+    uint32_t reserved_46c;
+    uint32_t reserved_470;
+    uint32_t reserved_474;
+    uint32_t reserved_478;
+    uint32_t reserved_47c;
+    uint32_t reserved_480;
+    uint32_t reserved_484;
+    uint32_t reserved_488;
+    uint32_t reserved_48c;
+    uint32_t reserved_490;
+    uint32_t reserved_494;
+    uint32_t reserved_498;
+    uint32_t reserved_49c;
+    uint32_t reserved_4a0;
+    uint32_t reserved_4a4;
+    uint32_t reserved_4a8;
+    uint32_t reserved_4ac;
+    uint32_t reserved_4b0;
+    uint32_t reserved_4b4;
+    uint32_t reserved_4b8;
+    uint32_t reserved_4bc;
+    uint32_t reserved_4c0;
+    uint32_t reserved_4c4;
+    uint32_t reserved_4c8;
+    uint32_t reserved_4cc;
+    uint32_t reserved_4d0;
+    uint32_t reserved_4d4;
+    uint32_t reserved_4d8;
+    uint32_t reserved_4dc;
+    uint32_t reserved_4e0;
+    uint32_t reserved_4e4;
+    uint32_t reserved_4e8;
+    uint32_t reserved_4ec;
+    uint32_t reserved_4f0;
+    uint32_t reserved_4f4;
+    uint32_t reserved_4f8;
+    uint32_t reserved_4fc;
+    uint32_t reserved_500;
+    uint32_t reserved_504;
+    uint32_t reserved_508;
+    uint32_t reserved_50c;
+    uint32_t reserved_510;
+    uint32_t reserved_514;
+    uint32_t reserved_518;
+    uint32_t reserved_51c;
+    uint32_t reserved_520;
+    uint32_t reserved_524;
+    uint32_t reserved_528;
+    uint32_t reserved_52c;
+    uint32_t reserved_530;
+    uint32_t reserved_534;
+    uint32_t reserved_538;
+    uint32_t reserved_53c;
+    uint32_t reserved_540;
+    uint32_t reserved_544;
+    uint32_t reserved_548;
+    uint32_t reserved_54c;
+    uint32_t reserved_550;
+    uint32_t reserved_554;
+    uint32_t reserved_558;
+    uint32_t reserved_55c;
+    uint32_t reserved_560;
+    uint32_t reserved_564;
+    uint32_t reserved_568;
+    uint32_t reserved_56c;
+    uint32_t reserved_570;
+    uint32_t reserved_574;
+    uint32_t reserved_578;
+    uint32_t reserved_57c;
+    uint32_t reserved_580;
+    uint32_t reserved_584;
+    uint32_t reserved_588;
+    uint32_t reserved_58c;
+    uint32_t reserved_590;
+    uint32_t reserved_594;
+    uint32_t reserved_598;
+    uint32_t reserved_59c;
+    uint32_t reserved_5a0;
+    uint32_t reserved_5a4;
+    uint32_t reserved_5a8;
+    uint32_t reserved_5ac;
+    uint32_t reserved_5b0;
+    uint32_t reserved_5b4;
+    uint32_t reserved_5b8;
+    uint32_t reserved_5bc;
+    uint32_t reserved_5c0;
+    uint32_t reserved_5c4;
+    uint32_t reserved_5c8;
+    uint32_t reserved_5cc;
+    uint32_t reserved_5d0;
+    uint32_t reserved_5d4;
+    uint32_t reserved_5d8;
+    uint32_t reserved_5dc;
+    uint32_t reserved_5e0;
+    uint32_t reserved_5e4;
+    uint32_t reserved_5e8;
+    uint32_t reserved_5ec;
+    uint32_t reserved_5f0;
+    uint32_t reserved_5f4;
+    uint32_t reserved_5f8;
+    uint32_t reserved_5fc;
+    uint32_t reserved_600;
+    uint32_t reserved_604;
+    uint32_t reserved_608;
+    uint32_t reserved_60c;
+    uint32_t reserved_610;
+    uint32_t reserved_614;
+    uint32_t reserved_618;
+    uint32_t reserved_61c;
+    uint32_t reserved_620;
+    uint32_t reserved_624;
+    uint32_t reserved_628;
+    uint32_t reserved_62c;
+    uint32_t reserved_630;
+    uint32_t reserved_634;
+    uint32_t reserved_638;
+    uint32_t reserved_63c;
+    uint32_t reserved_640;
+    uint32_t reserved_644;
+    uint32_t reserved_648;
+    uint32_t reserved_64c;
+    uint32_t reserved_650;
+    uint32_t reserved_654;
+    uint32_t reserved_658;
+    uint32_t reserved_65c;
+    uint32_t reserved_660;
+    uint32_t reserved_664;
+    uint32_t reserved_668;
+    uint32_t reserved_66c;
+    uint32_t reserved_670;
+    uint32_t reserved_674;
+    uint32_t reserved_678;
+    uint32_t reserved_67c;
+    uint32_t reserved_680;
+    uint32_t reserved_684;
+    uint32_t reserved_688;
+    uint32_t reserved_68c;
+    uint32_t reserved_690;
+    uint32_t reserved_694;
+    uint32_t reserved_698;
+    uint32_t reserved_69c;
+    uint32_t reserved_6a0;
+    uint32_t reserved_6a4;
+    uint32_t reserved_6a8;
+    uint32_t reserved_6ac;
+    uint32_t reserved_6b0;
+    uint32_t reserved_6b4;
+    uint32_t reserved_6b8;
+    uint32_t reserved_6bc;
+    uint32_t reserved_6c0;
+    uint32_t reserved_6c4;
+    uint32_t reserved_6c8;
+    uint32_t reserved_6cc;
+    uint32_t reserved_6d0;
+    uint32_t reserved_6d4;
+    uint32_t reserved_6d8;
+    uint32_t reserved_6dc;
+    uint32_t reserved_6e0;
+    uint32_t reserved_6e4;
+    uint32_t reserved_6e8;
+    uint32_t reserved_6ec;
+    uint32_t reserved_6f0;
+    uint32_t reserved_6f4;
+    uint32_t reserved_6f8;
+    uint32_t reserved_6fc;
+    uint32_t reserved_700;
+    uint32_t reserved_704;
+    uint32_t reserved_708;
+    uint32_t reserved_70c;
+    uint32_t reserved_710;
+    uint32_t reserved_714;
+    uint32_t reserved_718;
+    uint32_t reserved_71c;
+    uint32_t reserved_720;
+    uint32_t reserved_724;
+    uint32_t reserved_728;
+    uint32_t reserved_72c;
+    uint32_t reserved_730;
+    uint32_t reserved_734;
+    uint32_t reserved_738;
+    uint32_t reserved_73c;
+    uint32_t reserved_740;
+    uint32_t reserved_744;
+    uint32_t reserved_748;
+    uint32_t reserved_74c;
+    uint32_t reserved_750;
+    uint32_t reserved_754;
+    uint32_t reserved_758;
+    uint32_t reserved_75c;
+    uint32_t reserved_760;
+    uint32_t reserved_764;
+    uint32_t reserved_768;
+    uint32_t reserved_76c;
+    uint32_t reserved_770;
+    uint32_t reserved_774;
+    uint32_t reserved_778;
+    uint32_t reserved_77c;
+    uint32_t reserved_780;
+    uint32_t reserved_784;
+    uint32_t reserved_788;
+    uint32_t reserved_78c;
+    uint32_t reserved_790;
+    uint32_t reserved_794;
+    uint32_t reserved_798;
+    uint32_t reserved_79c;
+    uint32_t reserved_7a0;
+    uint32_t reserved_7a4;
+    uint32_t reserved_7a8;
+    uint32_t reserved_7ac;
+    uint32_t reserved_7b0;
+    uint32_t reserved_7b4;
+    uint32_t reserved_7b8;
+    uint32_t reserved_7bc;
+    uint32_t reserved_7c0;
+    uint32_t reserved_7c4;
+    uint32_t reserved_7c8;
+    uint32_t reserved_7cc;
+    uint32_t reserved_7d0;
+    uint32_t reserved_7d4;
+    uint32_t reserved_7d8;
+    uint32_t reserved_7dc;
+    uint32_t reserved_7e0;
+    uint32_t reserved_7e4;
+    uint32_t reserved_7e8;
+    uint32_t reserved_7ec;
+    uint32_t reserved_7f0;
+    uint32_t reserved_7f4;
+    uint32_t reserved_7f8;
+    uint32_t reserved_7fc;
+    uint32_t reserved_800;
+    uint32_t reserved_804;
+    uint32_t reserved_808;
+    uint32_t reserved_80c;
+    uint32_t reserved_810;
+    uint32_t reserved_814;
+    uint32_t reserved_818;
+    uint32_t reserved_81c;
+    uint32_t reserved_820;
+    uint32_t reserved_824;
+    uint32_t reserved_828;
+    uint32_t reserved_82c;
+    uint32_t reserved_830;
+    uint32_t reserved_834;
+    uint32_t reserved_838;
+    uint32_t reserved_83c;
+    uint32_t reserved_840;
+    uint32_t reserved_844;
+    uint32_t reserved_848;
+    uint32_t reserved_84c;
+    uint32_t reserved_850;
+    uint32_t reserved_854;
+    uint32_t reserved_858;
+    uint32_t reserved_85c;
+    uint32_t reserved_860;
+    uint32_t reserved_864;
+    uint32_t reserved_868;
+    uint32_t reserved_86c;
+    uint32_t reserved_870;
+    uint32_t reserved_874;
+    uint32_t reserved_878;
+    uint32_t reserved_87c;
+    uint32_t reserved_880;
+    uint32_t reserved_884;
+    uint32_t reserved_888;
+    uint32_t reserved_88c;
+    uint32_t reserved_890;
+    uint32_t reserved_894;
+    uint32_t reserved_898;
+    uint32_t reserved_89c;
+    uint32_t reserved_8a0;
+    uint32_t reserved_8a4;
+    uint32_t reserved_8a8;
+    uint32_t reserved_8ac;
+    uint32_t reserved_8b0;
+    uint32_t reserved_8b4;
+    uint32_t reserved_8b8;
+    uint32_t reserved_8bc;
+    uint32_t reserved_8c0;
+    uint32_t reserved_8c4;
+    uint32_t reserved_8c8;
+    uint32_t reserved_8cc;
+    uint32_t reserved_8d0;
+    uint32_t reserved_8d4;
+    uint32_t reserved_8d8;
+    uint32_t reserved_8dc;
+    uint32_t reserved_8e0;
+    uint32_t reserved_8e4;
+    uint32_t reserved_8e8;
+    uint32_t reserved_8ec;
+    uint32_t reserved_8f0;
+    uint32_t reserved_8f4;
+    uint32_t reserved_8f8;
+    uint32_t reserved_8fc;
+    uint32_t reserved_900;
+    uint32_t reserved_904;
+    uint32_t reserved_908;
+    uint32_t reserved_90c;
+    uint32_t reserved_910;
+    uint32_t reserved_914;
+    uint32_t reserved_918;
+    uint32_t reserved_91c;
+    uint32_t reserved_920;
+    uint32_t reserved_924;
+    uint32_t reserved_928;
+    uint32_t reserved_92c;
+    uint32_t reserved_930;
+    uint32_t reserved_934;
+    uint32_t reserved_938;
+    uint32_t reserved_93c;
+    uint32_t reserved_940;
+    uint32_t reserved_944;
+    uint32_t reserved_948;
+    uint32_t reserved_94c;
+    uint32_t reserved_950;
+    uint32_t reserved_954;
+    uint32_t reserved_958;
+    uint32_t reserved_95c;
+    uint32_t reserved_960;
+    uint32_t reserved_964;
+    uint32_t reserved_968;
+    uint32_t reserved_96c;
+    uint32_t reserved_970;
+    uint32_t reserved_974;
+    uint32_t reserved_978;
+    uint32_t reserved_97c;
+    uint32_t reserved_980;
+    uint32_t reserved_984;
+    uint32_t reserved_988;
+    uint32_t reserved_98c;
+    uint32_t reserved_990;
+    uint32_t reserved_994;
+    uint32_t reserved_998;
+    uint32_t reserved_99c;
+    uint32_t reserved_9a0;
+    uint32_t reserved_9a4;
+    uint32_t reserved_9a8;
+    uint32_t reserved_9ac;
+    uint32_t reserved_9b0;
+    uint32_t reserved_9b4;
+    uint32_t reserved_9b8;
+    uint32_t reserved_9bc;
+    uint32_t reserved_9c0;
+    uint32_t reserved_9c4;
+    uint32_t reserved_9c8;
+    uint32_t reserved_9cc;
+    uint32_t reserved_9d0;
+    uint32_t reserved_9d4;
+    uint32_t reserved_9d8;
+    uint32_t reserved_9dc;
+    uint32_t reserved_9e0;
+    uint32_t reserved_9e4;
+    uint32_t reserved_9e8;
+    uint32_t reserved_9ec;
+    uint32_t reserved_9f0;
+    uint32_t reserved_9f4;
+    uint32_t reserved_9f8;
+    uint32_t reserved_9fc;
+    uint32_t reserved_a00;
+    uint32_t reserved_a04;
+    uint32_t reserved_a08;
+    uint32_t reserved_a0c;
+    uint32_t reserved_a10;
+    uint32_t reserved_a14;
+    uint32_t reserved_a18;
+    uint32_t reserved_a1c;
+    uint32_t reserved_a20;
+    uint32_t reserved_a24;
+    uint32_t reserved_a28;
+    uint32_t reserved_a2c;
+    uint32_t reserved_a30;
+    uint32_t reserved_a34;
+    uint32_t reserved_a38;
+    uint32_t reserved_a3c;
+    uint32_t reserved_a40;
+    uint32_t reserved_a44;
+    uint32_t reserved_a48;
+    uint32_t reserved_a4c;
+    uint32_t reserved_a50;
+    uint32_t reserved_a54;
+    uint32_t reserved_a58;
+    uint32_t reserved_a5c;
+    uint32_t reserved_a60;
+    uint32_t reserved_a64;
+    uint32_t reserved_a68;
+    uint32_t reserved_a6c;
+    uint32_t reserved_a70;
+    uint32_t reserved_a74;
+    uint32_t reserved_a78;
+    uint32_t reserved_a7c;
+    uint32_t reserved_a80;
+    uint32_t reserved_a84;
+    uint32_t reserved_a88;
+    uint32_t reserved_a8c;
+    uint32_t reserved_a90;
+    uint32_t reserved_a94;
+    uint32_t reserved_a98;
+    uint32_t reserved_a9c;
+    uint32_t reserved_aa0;
+    uint32_t reserved_aa4;
+    uint32_t reserved_aa8;
+    uint32_t reserved_aac;
+    uint32_t reserved_ab0;
+    uint32_t reserved_ab4;
+    uint32_t reserved_ab8;
+    uint32_t reserved_abc;
+    uint32_t reserved_ac0;
+    uint32_t reserved_ac4;
+    uint32_t reserved_ac8;
+    uint32_t reserved_acc;
+    uint32_t reserved_ad0;
+    uint32_t reserved_ad4;
+    uint32_t reserved_ad8;
+    uint32_t reserved_adc;
+    uint32_t reserved_ae0;
+    uint32_t reserved_ae4;
+    uint32_t reserved_ae8;
+    uint32_t reserved_aec;
+    uint32_t reserved_af0;
+    uint32_t reserved_af4;
+    uint32_t reserved_af8;
+    uint32_t reserved_afc;
+    uint32_t reserved_b00;
+    uint32_t reserved_b04;
+    uint32_t reserved_b08;
+    uint32_t reserved_b0c;
+    uint32_t reserved_b10;
+    uint32_t reserved_b14;
+    uint32_t reserved_b18;
+    uint32_t reserved_b1c;
+    uint32_t reserved_b20;
+    uint32_t reserved_b24;
+    uint32_t reserved_b28;
+    uint32_t reserved_b2c;
+    uint32_t reserved_b30;
+    uint32_t reserved_b34;
+    uint32_t reserved_b38;
+    uint32_t reserved_b3c;
+    uint32_t reserved_b40;
+    uint32_t reserved_b44;
+    uint32_t reserved_b48;
+    uint32_t reserved_b4c;
+    uint32_t reserved_b50;
+    uint32_t reserved_b54;
+    uint32_t reserved_b58;
+    uint32_t reserved_b5c;
+    uint32_t reserved_b60;
+    uint32_t reserved_b64;
+    uint32_t reserved_b68;
+    uint32_t reserved_b6c;
+    uint32_t reserved_b70;
+    uint32_t reserved_b74;
+    uint32_t reserved_b78;
+    uint32_t reserved_b7c;
+    uint32_t reserved_b80;
+    uint32_t reserved_b84;
+    uint32_t reserved_b88;
+    uint32_t reserved_b8c;
+    uint32_t reserved_b90;
+    uint32_t reserved_b94;
+    uint32_t reserved_b98;
+    uint32_t reserved_b9c;
+    uint32_t reserved_ba0;
+    uint32_t reserved_ba4;
+    uint32_t reserved_ba8;
+    uint32_t reserved_bac;
+    uint32_t reserved_bb0;
+    uint32_t reserved_bb4;
+    uint32_t reserved_bb8;
+    uint32_t reserved_bbc;
+    uint32_t reserved_bc0;
+    uint32_t reserved_bc4;
+    uint32_t reserved_bc8;
+    uint32_t reserved_bcc;
+    uint32_t reserved_bd0;
+    uint32_t reserved_bd4;
+    uint32_t reserved_bd8;
+    uint32_t reserved_bdc;
+    uint32_t reserved_be0;
+    uint32_t reserved_be4;
+    uint32_t reserved_be8;
+    uint32_t reserved_bec;
+    uint32_t reserved_bf0;
+    uint32_t reserved_bf4;
+    uint32_t reserved_bf8;
+    uint32_t reserved_bfc;
+    uint32_t reserved_c00;
+    uint32_t reserved_c04;
+    uint32_t reserved_c08;
+    uint32_t reserved_c0c;
+    uint32_t reserved_c10;
+    uint32_t reserved_c14;
+    uint32_t reserved_c18;
+    uint32_t reserved_c1c;
+    uint32_t reserved_c20;
+    uint32_t reserved_c24;
+    uint32_t reserved_c28;
+    uint32_t reserved_c2c;
+    uint32_t reserved_c30;
+    uint32_t reserved_c34;
+    uint32_t reserved_c38;
+    uint32_t reserved_c3c;
+    uint32_t reserved_c40;
+    uint32_t reserved_c44;
+    uint32_t reserved_c48;
+    uint32_t reserved_c4c;
+    uint32_t reserved_c50;
+    uint32_t reserved_c54;
+    uint32_t reserved_c58;
+    uint32_t reserved_c5c;
+    uint32_t reserved_c60;
+    uint32_t reserved_c64;
+    uint32_t reserved_c68;
+    uint32_t reserved_c6c;
+    uint32_t reserved_c70;
+    uint32_t reserved_c74;
+    uint32_t reserved_c78;
+    uint32_t reserved_c7c;
+    uint32_t reserved_c80;
+    uint32_t reserved_c84;
+    uint32_t reserved_c88;
+    uint32_t reserved_c8c;
+    uint32_t reserved_c90;
+    uint32_t reserved_c94;
+    uint32_t reserved_c98;
+    uint32_t reserved_c9c;
+    uint32_t reserved_ca0;
+    uint32_t reserved_ca4;
+    uint32_t reserved_ca8;
+    uint32_t reserved_cac;
+    uint32_t reserved_cb0;
+    uint32_t reserved_cb4;
+    uint32_t reserved_cb8;
+    uint32_t reserved_cbc;
+    uint32_t reserved_cc0;
+    uint32_t reserved_cc4;
+    uint32_t reserved_cc8;
+    uint32_t reserved_ccc;
+    uint32_t reserved_cd0;
+    uint32_t reserved_cd4;
+    uint32_t reserved_cd8;
+    uint32_t reserved_cdc;
+    uint32_t reserved_ce0;
+    uint32_t reserved_ce4;
+    uint32_t reserved_ce8;
+    uint32_t reserved_cec;
+    uint32_t reserved_cf0;
+    uint32_t reserved_cf4;
+    uint32_t reserved_cf8;
+    uint32_t reserved_cfc;
+    uint32_t reserved_d00;
+    uint32_t reserved_d04;
+    uint32_t reserved_d08;
+    uint32_t reserved_d0c;
+    uint32_t reserved_d10;
+    uint32_t reserved_d14;
+    uint32_t reserved_d18;
+    uint32_t reserved_d1c;
+    uint32_t reserved_d20;
+    uint32_t reserved_d24;
+    uint32_t reserved_d28;
+    uint32_t reserved_d2c;
+    uint32_t reserved_d30;
+    uint32_t reserved_d34;
+    uint32_t reserved_d38;
+    uint32_t reserved_d3c;
+    uint32_t reserved_d40;
+    uint32_t reserved_d44;
+    uint32_t reserved_d48;
+    uint32_t reserved_d4c;
+    uint32_t reserved_d50;
+    uint32_t reserved_d54;
+    uint32_t reserved_d58;
+    uint32_t reserved_d5c;
+    uint32_t reserved_d60;
+    uint32_t reserved_d64;
+    uint32_t reserved_d68;
+    uint32_t reserved_d6c;
+    uint32_t reserved_d70;
+    uint32_t reserved_d74;
+    uint32_t reserved_d78;
+    uint32_t reserved_d7c;
+    uint32_t reserved_d80;
+    uint32_t reserved_d84;
+    uint32_t reserved_d88;
+    uint32_t reserved_d8c;
+    uint32_t reserved_d90;
+    uint32_t reserved_d94;
+    uint32_t reserved_d98;
+    uint32_t reserved_d9c;
+    uint32_t reserved_da0;
+    uint32_t reserved_da4;
+    uint32_t reserved_da8;
+    uint32_t reserved_dac;
+    uint32_t reserved_db0;
+    uint32_t reserved_db4;
+    uint32_t reserved_db8;
+    uint32_t reserved_dbc;
+    uint32_t reserved_dc0;
+    uint32_t reserved_dc4;
+    uint32_t reserved_dc8;
+    uint32_t reserved_dcc;
+    uint32_t reserved_dd0;
+    uint32_t reserved_dd4;
+    uint32_t reserved_dd8;
+    uint32_t reserved_ddc;
+    uint32_t reserved_de0;
+    uint32_t reserved_de4;
+    uint32_t reserved_de8;
+    uint32_t reserved_dec;
+    uint32_t reserved_df0;
+    uint32_t reserved_df4;
+    uint32_t reserved_df8;
+    uint32_t reserved_dfc;
+    uint32_t reserved_e00;
+    uint32_t reserved_e04;
+    uint32_t reserved_e08;
+    uint32_t reserved_e0c;
+    uint32_t reserved_e10;
+    uint32_t reserved_e14;
+    uint32_t reserved_e18;
+    uint32_t reserved_e1c;
+    uint32_t reserved_e20;
+    uint32_t reserved_e24;
+    uint32_t reserved_e28;
+    uint32_t reserved_e2c;
+    uint32_t reserved_e30;
+    uint32_t reserved_e34;
+    uint32_t reserved_e38;
+    uint32_t reserved_e3c;
+    uint32_t reserved_e40;
+    uint32_t reserved_e44;
+    uint32_t reserved_e48;
+    uint32_t reserved_e4c;
+    uint32_t reserved_e50;
+    uint32_t reserved_e54;
+    uint32_t reserved_e58;
+    uint32_t reserved_e5c;
+    uint32_t reserved_e60;
+    uint32_t reserved_e64;
+    uint32_t reserved_e68;
+    uint32_t reserved_e6c;
+    uint32_t reserved_e70;
+    uint32_t reserved_e74;
+    uint32_t reserved_e78;
+    uint32_t reserved_e7c;
+    uint32_t reserved_e80;
+    uint32_t reserved_e84;
+    uint32_t reserved_e88;
+    uint32_t reserved_e8c;
+    uint32_t reserved_e90;
+    uint32_t reserved_e94;
+    uint32_t reserved_e98;
+    uint32_t reserved_e9c;
+    uint32_t reserved_ea0;
+    uint32_t reserved_ea4;
+    uint32_t reserved_ea8;
+    uint32_t reserved_eac;
+    uint32_t reserved_eb0;
+    uint32_t reserved_eb4;
+    uint32_t reserved_eb8;
+    uint32_t reserved_ebc;
+    uint32_t reserved_ec0;
+    uint32_t reserved_ec4;
+    uint32_t reserved_ec8;
+    uint32_t reserved_ecc;
+    uint32_t reserved_ed0;
+    uint32_t reserved_ed4;
+    uint32_t reserved_ed8;
+    uint32_t reserved_edc;
+    uint32_t reserved_ee0;
+    uint32_t reserved_ee4;
+    uint32_t reserved_ee8;
+    uint32_t reserved_eec;
+    uint32_t reserved_ef0;
+    uint32_t reserved_ef4;
+    uint32_t reserved_ef8;
+    uint32_t reserved_efc;
+    uint32_t reserved_f00;
+    uint32_t reserved_f04;
+    uint32_t reserved_f08;
+    uint32_t reserved_f0c;
+    uint32_t reserved_f10;
+    uint32_t reserved_f14;
+    uint32_t reserved_f18;
+    uint32_t reserved_f1c;
+    uint32_t reserved_f20;
+    uint32_t reserved_f24;
+    uint32_t reserved_f28;
+    uint32_t reserved_f2c;
+    uint32_t reserved_f30;
+    uint32_t reserved_f34;
+    uint32_t reserved_f38;
+    uint32_t reserved_f3c;
+    uint32_t reserved_f40;
+    uint32_t reserved_f44;
+    uint32_t reserved_f48;
+    uint32_t reserved_f4c;
+    uint32_t reserved_f50;
+    uint32_t reserved_f54;
+    uint32_t reserved_f58;
+    uint32_t reserved_f5c;
+    uint32_t reserved_f60;
+    uint32_t reserved_f64;
+    uint32_t reserved_f68;
+    uint32_t reserved_f6c;
+    uint32_t reserved_f70;
+    uint32_t reserved_f74;
+    uint32_t reserved_f78;
+    uint32_t reserved_f7c;
+    uint32_t reserved_f80;
+    uint32_t reserved_f84;
+    uint32_t reserved_f88;
+    uint32_t reserved_f8c;
+    uint32_t reserved_f90;
+    uint32_t reserved_f94;
+    uint32_t reserved_f98;
+    uint32_t reserved_f9c;
+    uint32_t reserved_fa0;
+    uint32_t reserved_fa4;
+    uint32_t reserved_fa8;
+    uint32_t reserved_fac;
+    uint32_t reserved_fb0;
+    uint32_t reserved_fb4;
+    uint32_t reserved_fb8;
+    uint32_t reserved_fbc;
+    uint32_t reserved_fc0;
+    uint32_t reserved_fc4;
+    uint32_t reserved_fc8;
+    uint32_t reserved_fcc;
+    uint32_t reserved_fd0;
+    uint32_t reserved_fd4;
+    uint32_t reserved_fd8;
+    uint32_t reserved_fdc;
+    uint32_t reserved_fe0;
+    uint32_t reserved_fe4;
+    uint32_t reserved_fe8;
+    uint32_t reserved_fec;
+    uint32_t reserved_ff0;
+    uint32_t reserved_ff4;
+    uint32_t reserved_ff8;
+    union {
+        struct {
+            uint32_t date                          :    28;
+            uint32_t reserved28                    :    4;
+        };
+        uint32_t val;
+    } date;
+} system_dev_t;
+extern system_dev_t SYSTEM;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_STRUCT_H_ */
diff --git a/components/soc/esp32s3/register/soc/systimer_reg.h b/components/soc/esp32s3/register/soc/systimer_reg.h
new file mode 100644
index 00000000000..45873735b42
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/systimer_reg.h
@@ -0,0 +1,630 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSTIMER_CONF_REG register
+ *  Configure system timer clock
+ */
+#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
+/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
+ *  systimer clock force on
+ */
+#define SYSTIMER_SYSTIMER_CLK_FO    (BIT(0))
+#define SYSTIMER_SYSTIMER_CLK_FO_M  (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
+#define SYSTIMER_SYSTIMER_CLK_FO_V  0x00000001
+#define SYSTIMER_SYSTIMER_CLK_FO_S  0
+/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
+ *  target2 work enable
+ */
+#define SYSTIMER_TARGET2_WORK_EN    (BIT(22))
+#define SYSTIMER_TARGET2_WORK_EN_M  (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
+#define SYSTIMER_TARGET2_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET2_WORK_EN_S  22
+/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
+ *  target1 work enable
+ */
+#define SYSTIMER_TARGET1_WORK_EN    (BIT(23))
+#define SYSTIMER_TARGET1_WORK_EN_M  (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
+#define SYSTIMER_TARGET1_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET1_WORK_EN_S  23
+/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
+ *  target0 work enable
+ */
+#define SYSTIMER_TARGET0_WORK_EN    (BIT(24))
+#define SYSTIMER_TARGET0_WORK_EN_M  (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
+#define SYSTIMER_TARGET0_WORK_EN_V  0x00000001
+#define SYSTIMER_TARGET0_WORK_EN_S  24
+/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
+ *  If timer unit1 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN    (BIT(25))
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S  25
+/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
+ *  If timer unit1 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN    (BIT(26))
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S  26
+/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
+ *  If timer unit0 is stalled when core1 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN    (BIT(27))
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S  27
+/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
+ *  If timer unit0 is stalled when core0 stalled
+ */
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN    (BIT(28))
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M  (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S  28
+/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
+ *  timer unit1 work enable
+ */
+#define SYSTIMER_TIMER_UNIT1_WORK_EN    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_M  (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_WORK_EN_S  29
+/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
+ *  timer unit0 work enable
+ */
+#define SYSTIMER_TIMER_UNIT0_WORK_EN    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_M  (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_WORK_EN_S  30
+/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  register file clk gating
+ */
+#define SYSTIMER_CLK_EN    (BIT(31))
+#define SYSTIMER_CLK_EN_M  (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
+#define SYSTIMER_CLK_EN_V  0x00000001
+#define SYSTIMER_CLK_EN_S  31
+
+/** SYSTIMER_UNIT0_OP_REG register
+ *  system timer unit0 value update register
+ */
+#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
+/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  timer value is sync and valid
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer_unit0
+ */
+#define SYSTIMER_TIMER_UNIT0_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT0_UPDATE_M  (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT0_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_UPDATE_S  30
+
+/** SYSTIMER_UNIT1_OP_REG register
+ *  system timer unit1 value update register
+ */
+#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
+/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
+ *  timer value is sync and valid
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID    (BIT(29))
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M  (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S  29
+/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
+ *  update timer unit1
+ */
+#define SYSTIMER_TIMER_UNIT1_UPDATE    (BIT(30))
+#define SYSTIMER_TIMER_UNIT1_UPDATE_M  (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
+#define SYSTIMER_TIMER_UNIT1_UPDATE_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_UPDATE_S  30
+
+/** SYSTIMER_UNIT0_LOAD_HI_REG register
+ *  system timer unit0 value high load register
+ */
+#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
+/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit0 load high 20 bits
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M  (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT0_LOAD_LO_REG register
+ *  system timer unit0 value low load register
+ */
+#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
+/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit0 load low 32 bits
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M  (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S  0
+
+/** SYSTIMER_UNIT1_LOAD_HI_REG register
+ *  system timer unit1 value high load register
+ */
+#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
+/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer unit1 load high 20 bits
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M  (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S  0
+
+/** SYSTIMER_UNIT1_LOAD_LO_REG register
+ *  system timer unit1 value low load register
+ */
+#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
+/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer unit1 load low 32 bits
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M  (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S  0
+
+/** SYSTIMER_TARGET0_HI_REG register
+ *  system timer comp0 value high register
+ */
+#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
+/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget0 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET0_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET0_HI_M  (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
+#define SYSTIMER_TIMER_TARGET0_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET0_HI_S  0
+
+/** SYSTIMER_TARGET0_LO_REG register
+ *  system timer comp0 value low register
+ */
+#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
+/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget0 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET0_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET0_LO_M  (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
+#define SYSTIMER_TIMER_TARGET0_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET0_LO_S  0
+
+/** SYSTIMER_TARGET1_HI_REG register
+ *  system timer comp1 value high register
+ */
+#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
+/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget1 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET1_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET1_HI_M  (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
+#define SYSTIMER_TIMER_TARGET1_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET1_HI_S  0
+
+/** SYSTIMER_TARGET1_LO_REG register
+ *  system timer comp1 value low register
+ */
+#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
+/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget1 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET1_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET1_LO_M  (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
+#define SYSTIMER_TIMER_TARGET1_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET1_LO_S  0
+
+/** SYSTIMER_TARGET2_HI_REG register
+ *  system timer comp2 value high register
+ */
+#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
+/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
+ *  timer taget2 high 20 bits
+ */
+#define SYSTIMER_TIMER_TARGET2_HI    0x000FFFFF
+#define SYSTIMER_TIMER_TARGET2_HI_M  (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
+#define SYSTIMER_TIMER_TARGET2_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_TARGET2_HI_S  0
+
+/** SYSTIMER_TARGET2_LO_REG register
+ *  system timer comp2 value low register
+ */
+#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
+/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
+ *  timer taget2 low 32 bits
+ */
+#define SYSTIMER_TIMER_TARGET2_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET2_LO_M  (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
+#define SYSTIMER_TIMER_TARGET2_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_TARGET2_LO_S  0
+
+/** SYSTIMER_TARGET0_CONF_REG register
+ *  system timer comp0 target mode register
+ */
+#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
+/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target0 period
+ */
+#define SYSTIMER_TARGET0_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_M  (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
+#define SYSTIMER_TARGET0_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET0_PERIOD_S  0
+/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target0 to period mode
+ */
+#define SYSTIMER_TARGET0_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET0_PERIOD_MODE_M  (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
+#define SYSTIMER_TARGET0_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET0_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET1_CONF_REG register
+ *  system timer comp1 target mode register
+ */
+#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
+/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target1 period
+ */
+#define SYSTIMER_TARGET1_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_M  (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
+#define SYSTIMER_TARGET1_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET1_PERIOD_S  0
+/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target1 to period mode
+ */
+#define SYSTIMER_TARGET1_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET1_PERIOD_MODE_M  (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
+#define SYSTIMER_TARGET1_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET1_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_TARGET2_CONF_REG register
+ *  system timer comp2 target mode register
+ */
+#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
+/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
+ *  target2 period
+ */
+#define SYSTIMER_TARGET2_PERIOD    0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_M  (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
+#define SYSTIMER_TARGET2_PERIOD_V  0x03FFFFFF
+#define SYSTIMER_TARGET2_PERIOD_S  0
+/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
+ *  Set target2 to period mode
+ */
+#define SYSTIMER_TARGET2_PERIOD_MODE    (BIT(30))
+#define SYSTIMER_TARGET2_PERIOD_MODE_M  (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
+#define SYSTIMER_TARGET2_PERIOD_MODE_V  0x00000001
+#define SYSTIMER_TARGET2_PERIOD_MODE_S  30
+/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
+ *  select which unit to compare
+ */
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL    (BIT(31))
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M  (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V  0x00000001
+#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S  31
+
+/** SYSTIMER_UNIT0_VALUE_HI_REG register
+ *  system timer unit0 value high register
+ */
+#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
+/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 20bits
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M  (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT0_VALUE_LO_REG register
+ *  system timer unit0 value low register
+ */
+#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
+/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bits
+ */
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M  (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S  0
+
+/** SYSTIMER_UNIT1_VALUE_HI_REG register
+ *  system timer unit1 value high register
+ */
+#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
+/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
+ *  timer read value high 20bits
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI    0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M  (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V  0x000FFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S  0
+
+/** SYSTIMER_UNIT1_VALUE_LO_REG register
+ *  system timer unit1 value low register
+ */
+#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
+/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
+ *  timer read value low 32bits
+ */
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO    0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M  (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V  0xFFFFFFFF
+#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S  0
+
+/** SYSTIMER_COMP0_LOAD_REG register
+ *  system timer comp0 conf sync register
+ */
+#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
+/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp0 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP0_LOAD_M  (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
+#define SYSTIMER_TIMER_COMP0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP0_LOAD_S  0
+
+/** SYSTIMER_COMP1_LOAD_REG register
+ *  system timer comp1 conf sync register
+ */
+#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
+/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp1 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP1_LOAD_M  (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
+#define SYSTIMER_TIMER_COMP1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP1_LOAD_S  0
+
+/** SYSTIMER_COMP2_LOAD_REG register
+ *  system timer comp2 conf sync register
+ */
+#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
+/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer comp2 sync enable signal
+ */
+#define SYSTIMER_TIMER_COMP2_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_COMP2_LOAD_M  (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
+#define SYSTIMER_TIMER_COMP2_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_COMP2_LOAD_S  0
+
+/** SYSTIMER_UNIT0_LOAD_REG register
+ *  system timer unit0 conf sync register
+ */
+#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
+/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit0 sync enable signal
+ */
+#define SYSTIMER_TIMER_UNIT0_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT0_LOAD_M  (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
+#define SYSTIMER_TIMER_UNIT0_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT0_LOAD_S  0
+
+/** SYSTIMER_UNIT1_LOAD_REG register
+ *  system timer unit1 conf sync register
+ */
+#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
+/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
+ *  timer unit1 sync enable signal
+ */
+#define SYSTIMER_TIMER_UNIT1_LOAD    (BIT(0))
+#define SYSTIMER_TIMER_UNIT1_LOAD_M  (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
+#define SYSTIMER_TIMER_UNIT1_LOAD_V  0x00000001
+#define SYSTIMER_TIMER_UNIT1_LOAD_S  0
+
+/** SYSTIMER_INT_ENA_REG register
+ *  systimer interrupt enable register
+ */
+#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
+/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  interupt0 enable
+ */
+#define SYSTIMER_TARGET0_INT_ENA    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ENA_M  (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
+#define SYSTIMER_TARGET0_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ENA_S  0
+/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  interupt1 enable
+ */
+#define SYSTIMER_TARGET1_INT_ENA    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ENA_M  (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
+#define SYSTIMER_TARGET1_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ENA_S  1
+/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  interupt2 enable
+ */
+#define SYSTIMER_TARGET2_INT_ENA    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ENA_M  (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
+#define SYSTIMER_TARGET2_INT_ENA_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ENA_S  2
+
+/** SYSTIMER_INT_RAW_REG register
+ *  systimer interrupt raw register
+ */
+#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
+/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  interupt0 raw
+ */
+#define SYSTIMER_TARGET0_INT_RAW    (BIT(0))
+#define SYSTIMER_TARGET0_INT_RAW_M  (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
+#define SYSTIMER_TARGET0_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET0_INT_RAW_S  0
+/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  interupt1 raw
+ */
+#define SYSTIMER_TARGET1_INT_RAW    (BIT(1))
+#define SYSTIMER_TARGET1_INT_RAW_M  (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
+#define SYSTIMER_TARGET1_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET1_INT_RAW_S  1
+/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  interupt2 raw
+ */
+#define SYSTIMER_TARGET2_INT_RAW    (BIT(2))
+#define SYSTIMER_TARGET2_INT_RAW_M  (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
+#define SYSTIMER_TARGET2_INT_RAW_V  0x00000001
+#define SYSTIMER_TARGET2_INT_RAW_S  2
+
+/** SYSTIMER_INT_CLR_REG register
+ *  systimer interrupt clear register
+ */
+#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
+/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  interupt0 clear
+ */
+#define SYSTIMER_TARGET0_INT_CLR    (BIT(0))
+#define SYSTIMER_TARGET0_INT_CLR_M  (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
+#define SYSTIMER_TARGET0_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET0_INT_CLR_S  0
+/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  interupt1 clear
+ */
+#define SYSTIMER_TARGET1_INT_CLR    (BIT(1))
+#define SYSTIMER_TARGET1_INT_CLR_M  (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
+#define SYSTIMER_TARGET1_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET1_INT_CLR_S  1
+/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  interupt2 clear
+ */
+#define SYSTIMER_TARGET2_INT_CLR    (BIT(2))
+#define SYSTIMER_TARGET2_INT_CLR_M  (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
+#define SYSTIMER_TARGET2_INT_CLR_V  0x00000001
+#define SYSTIMER_TARGET2_INT_CLR_S  2
+
+/** SYSTIMER_INT_ST_REG register
+ *  systimer interrupt status register
+ */
+#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
+/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  interupt0 status
+ */
+#define SYSTIMER_TARGET0_INT_ST    (BIT(0))
+#define SYSTIMER_TARGET0_INT_ST_M  (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
+#define SYSTIMER_TARGET0_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET0_INT_ST_S  0
+/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  interupt1 status
+ */
+#define SYSTIMER_TARGET1_INT_ST    (BIT(1))
+#define SYSTIMER_TARGET1_INT_ST_M  (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
+#define SYSTIMER_TARGET1_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET1_INT_ST_S  1
+/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  interupt2 status
+ */
+#define SYSTIMER_TARGET2_INT_ST    (BIT(2))
+#define SYSTIMER_TARGET2_INT_ST_M  (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
+#define SYSTIMER_TARGET2_INT_ST_V  0x00000001
+#define SYSTIMER_TARGET2_INT_ST_S  2
+
+/** SYSTIMER_REAL_TARGET0_LO_REG register
+ *  system timer comp0 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
+/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET0_LO_RO    0xFFFFFFFF
+#define SYSTIMER_TARGET0_LO_RO_M  (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
+#define SYSTIMER_TARGET0_LO_RO_V  0xFFFFFFFF
+#define SYSTIMER_TARGET0_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET0_HI_REG register
+ *  system timer comp0 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
+/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET0_HI_RO    0x000FFFFF
+#define SYSTIMER_TARGET0_HI_RO_M  (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
+#define SYSTIMER_TARGET0_HI_RO_V  0x000FFFFF
+#define SYSTIMER_TARGET0_HI_RO_S  0
+
+/** SYSTIMER_REAL_TARGET1_LO_REG register
+ *  system timer comp1 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
+/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET1_LO_RO    0xFFFFFFFF
+#define SYSTIMER_TARGET1_LO_RO_M  (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
+#define SYSTIMER_TARGET1_LO_RO_V  0xFFFFFFFF
+#define SYSTIMER_TARGET1_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET1_HI_REG register
+ *  system timer comp1 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
+/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET1_HI_RO    0x000FFFFF
+#define SYSTIMER_TARGET1_HI_RO_M  (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
+#define SYSTIMER_TARGET1_HI_RO_V  0x000FFFFF
+#define SYSTIMER_TARGET1_HI_RO_S  0
+
+/** SYSTIMER_REAL_TARGET2_LO_REG register
+ *  system timer comp2 actual target value low register
+ */
+#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
+/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
+ *  actual target value value low 32bits
+ */
+#define SYSTIMER_TARGET2_LO_RO    0xFFFFFFFF
+#define SYSTIMER_TARGET2_LO_RO_M  (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
+#define SYSTIMER_TARGET2_LO_RO_V  0xFFFFFFFF
+#define SYSTIMER_TARGET2_LO_RO_S  0
+
+/** SYSTIMER_REAL_TARGET2_HI_REG register
+ *  system timer comp2 actual target value high register
+ */
+#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
+/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
+ *  actual target value value high 20bits
+ */
+#define SYSTIMER_TARGET2_HI_RO    0x000FFFFF
+#define SYSTIMER_TARGET2_HI_RO_M  (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
+#define SYSTIMER_TARGET2_HI_RO_V  0x000FFFFF
+#define SYSTIMER_TARGET2_HI_RO_S  0
+
+/** SYSTIMER_DATE_REG register
+ *  system timer version control register
+ */
+#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
+/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33628753;
+ *  systimer register version
+ */
+#define SYSTIMER_DATE    0xFFFFFFFF
+#define SYSTIMER_DATE_M  (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
+#define SYSTIMER_DATE_V  0xFFFFFFFF
+#define SYSTIMER_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/systimer_struct.h b/components/soc/esp32s3/register/soc/systimer_struct.h
new file mode 100644
index 00000000000..4216561c3c2
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/systimer_struct.h
@@ -0,0 +1,400 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSTEM TIMER CLK CONTROL REGISTER */
+/** Type of conf register
+ *  Configure system timer clock
+ */
+typedef union {
+    struct {
+        /** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
+         *  systimer clock force on
+         */
+        uint32_t systimer_clk_fo: 1;
+        uint32_t reserved_1: 21;
+        /** target2_work_en : R/W; bitpos: [22]; default: 0;
+         *  target2 work enable
+         */
+        uint32_t target2_work_en: 1;
+        /** target1_work_en : R/W; bitpos: [23]; default: 0;
+         *  target1 work enable
+         */
+        uint32_t target1_work_en: 1;
+        /** target0_work_en : R/W; bitpos: [24]; default: 0;
+         *  target0 work enable
+         */
+        uint32_t target0_work_en: 1;
+        /** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
+         *  If timer unit1 is stalled when core1 stalled
+         */
+        uint32_t timer_unit1_core1_stall_en: 1;
+        /** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
+         *  If timer unit1 is stalled when core0 stalled
+         */
+        uint32_t timer_unit1_core0_stall_en: 1;
+        /** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
+         *  If timer unit0 is stalled when core1 stalled
+         */
+        uint32_t timer_unit0_core1_stall_en: 1;
+        /** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
+         *  If timer unit0 is stalled when core0 stalled
+         */
+        uint32_t timer_unit0_core0_stall_en: 1;
+        /** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
+         *  timer unit1 work enable
+         */
+        uint32_t timer_unit1_work_en: 1;
+        /** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
+         *  timer unit0 work enable
+         */
+        uint32_t timer_unit0_work_en: 1;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  register file clk gating
+         */
+        uint32_t clk_en: 1;
+    };
+    uint32_t val;
+} systimer_conf_reg_t;
+
+
+/** Type of unit_op register
+ *  SYSTIMER_UNIT_OP.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 29;
+        /** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
+         *  reg_timer_unit0_value_valid
+         */
+        uint32_t timer_unit_value_valid: 1;
+        /** timer_unit_update : WT; bitpos: [30]; default: 0;
+         *  update timer_unit0
+         */
+        uint32_t timer_unit_update: 1;
+        uint32_t reserved_32: 1;
+    };
+    uint32_t val;
+} systimer_unit_op_reg_t;
+
+/** Type of unit_load register
+ *  SYSTIMER_UNIT_LOAD
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer unit load high 32 bit
+             */
+            uint32_t timer_unit_load_hi: 20;
+            uint32_t reserved_20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer unit load low 32 bit
+             */
+            uint32_t timer_unit_load_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_load_val_reg_t;
+
+
+/** Type of target register
+ *  SYSTIMER_TARGET.
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
+             *  timer target high 32 bit
+             */
+            uint32_t timer_target_hi: 20;
+            uint32_t reserved_20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
+             *  timer target low 32 bit
+             */
+            uint32_t timer_target_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_target_val_reg_t;
+
+
+/** Type of target_conf register
+ *  SYSTIMER_TARGET_CONF.
+ */
+typedef union {
+    struct {
+        /** target_period : R/W; bitpos: [25:0]; default: 0;
+         *  target period
+         */
+        uint32_t target_period: 26;
+        uint32_t reserved_26: 4;
+        /** target_period_mode : R/W; bitpos: [30]; default: 0;
+         *  Set target to period mode
+         */
+        uint32_t target_period_mode: 1;
+        /** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
+         *  select which unit to compare
+         */
+        uint32_t target_timer_unit_sel: 1;
+    };
+    uint32_t val;
+} systimer_target_conf_reg_t;
+
+
+/** Type of unit_value_hi register
+ *  SYSTIMER_UNIT_VALUE_HI.
+ */
+typedef struct {
+    union {
+        struct {
+            /** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
+             *  timer read value high 20bit
+             */
+            uint32_t timer_unit_value_hi: 20;
+            uint32_t reserved_20: 12;
+        };
+        uint32_t val;
+    } hi;
+    union {
+        struct {
+            /** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
+             *  timer read value low 32bit
+             */
+            uint32_t timer_unit_value_lo: 32;
+        };
+        uint32_t val;
+    } lo;
+} systimer_unit_value_reg_t;
+
+
+/** Type of comp_load register
+ *  SYSTIMER_COMP_LOAD.
+ */
+typedef union {
+    struct {
+        /** timer_comp_load : WT; bitpos: [0]; default: 0;
+         *  timer comp load value
+         */
+        uint32_t timer_comp_load: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} systimer_comp_load_reg_t;
+
+
+/** Type of unit_load register
+ *  SYSTIMER_UNIT_LOAD.
+ */
+typedef union {
+    struct {
+        /** timer_unit_load : WT; bitpos: [0]; default: 0;
+         *  timer unit load value
+         */
+        uint32_t timer_unit_load: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} systimer_unit_load_reg_t;
+
+
+/** SYSTEM TIMER INTERRUPT REGISTER */
+/** Type of int_ena register
+ *  systimer interrupt enable register
+ */
+typedef union {
+    struct {
+        /** target0_int_ena : R/W; bitpos: [0]; default: 0;
+         *  interupt0 enable
+         */
+        uint32_t target0_int_ena: 1;
+        /** target1_int_ena : R/W; bitpos: [1]; default: 0;
+         *  interupt1 enable
+         */
+        uint32_t target1_int_ena: 1;
+        /** target2_int_ena : R/W; bitpos: [2]; default: 0;
+         *  interupt2 enable
+         */
+        uint32_t target2_int_ena: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} systimer_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  systimer interrupt raw register
+ */
+typedef union {
+    struct {
+        /** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  interupt0 raw
+         */
+        uint32_t target0_int_raw: 1;
+        /** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  interupt1 raw
+         */
+        uint32_t target1_int_raw: 1;
+        /** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  interupt2 raw
+         */
+        uint32_t target2_int_raw: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} systimer_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  systimer interrupt clear register
+ */
+typedef union {
+    struct {
+        /** target0_int_clr : WT; bitpos: [0]; default: 0;
+         *  interupt0 clear
+         */
+        uint32_t target0_int_clr: 1;
+        /** target1_int_clr : WT; bitpos: [1]; default: 0;
+         *  interupt1 clear
+         */
+        uint32_t target1_int_clr: 1;
+        /** target2_int_clr : WT; bitpos: [2]; default: 0;
+         *  interupt2 clear
+         */
+        uint32_t target2_int_clr: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} systimer_int_clr_reg_t;
+
+/** Type of int_st register
+ *  systimer interrupt status register
+ */
+typedef union {
+    struct {
+        /** target0_int_st : RO; bitpos: [0]; default: 0;
+         *  interupt0 status
+         */
+        uint32_t target0_int_st: 1;
+        /** target1_int_st : RO; bitpos: [1]; default: 0;
+         *  interupt1 status
+         */
+        uint32_t target1_int_st: 1;
+        /** target2_int_st : RO; bitpos: [2]; default: 0;
+         *  interupt2 status
+         */
+        uint32_t target2_int_st: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} systimer_int_st_reg_t;
+
+
+/** SYSTEM TIMER COMP STATUS REGISTER
+ *  systimer comp actual target value low register
+ */
+typedef struct {
+    union {
+        struct {
+            /** target_lo_ro : RO; bitpos: [31:0]; default: 0;
+             *  actual target value value low 32bits
+             */
+            uint32_t target_lo_ro: 32;
+        };
+        uint32_t val;
+    } lo;
+    union {
+        struct {
+            /** target_hi_ro : RO; bitpos: [19:0]; default: 0;
+             *  actual target value value high 20bits
+             */
+            uint32_t target_hi_ro: 20;
+            uint32_t reserved_20: 12;
+        };
+        uint32_t val;
+    } hi;
+} systimer_real_target_val_reg_t;
+
+
+/** VERSION REGISTER */
+/** Type of date register
+ *  system timer version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 33628753;
+         *  systimer register version
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} systimer_date_reg_t;
+
+
+typedef struct systimer_dev_t {
+    volatile systimer_conf_reg_t conf;
+    volatile systimer_unit_op_reg_t unit_op[2];
+    volatile systimer_unit_load_val_reg_t unit_load_val[2];
+    volatile systimer_target_val_reg_t target_val[3];
+    volatile systimer_target_conf_reg_t target_conf[3];
+    volatile systimer_unit_value_reg_t unit_val[2];
+    volatile systimer_comp_load_reg_t comp_load[3];
+    volatile systimer_unit_load_reg_t unit_load[2];
+    volatile systimer_int_ena_reg_t int_ena;
+    volatile systimer_int_raw_reg_t int_raw;
+    volatile systimer_int_clr_reg_t int_clr;
+    volatile systimer_int_st_reg_t int_st;
+    volatile systimer_real_target_val_reg_t real_target_val[3];
+    uint32_t reserved_08c;
+    uint32_t reserved_090;
+    uint32_t reserved_094;
+    uint32_t reserved_098;
+    uint32_t reserved_09c;
+    uint32_t reserved_0a0;
+    uint32_t reserved_0a4;
+    uint32_t reserved_0a8;
+    uint32_t reserved_0ac;
+    uint32_t reserved_0b0;
+    uint32_t reserved_0b4;
+    uint32_t reserved_0b8;
+    uint32_t reserved_0bc;
+    uint32_t reserved_0c0;
+    uint32_t reserved_0c4;
+    uint32_t reserved_0c8;
+    uint32_t reserved_0cc;
+    uint32_t reserved_0d0;
+    uint32_t reserved_0d4;
+    uint32_t reserved_0d8;
+    uint32_t reserved_0dc;
+    uint32_t reserved_0e0;
+    uint32_t reserved_0e4;
+    uint32_t reserved_0e8;
+    uint32_t reserved_0ec;
+    uint32_t reserved_0f0;
+    uint32_t reserved_0f4;
+    uint32_t reserved_0f8;
+    volatile systimer_date_reg_t date;
+} systimer_dev_t;
+
+extern systimer_dev_t SYSTIMER;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/include/soc/timer_group_reg.h b/components/soc/esp32s3/register/soc/timer_group_reg.h
similarity index 97%
rename from components/soc/esp32s3/include/soc/timer_group_reg.h
rename to components/soc/esp32s3/register/soc/timer_group_reg.h
index 7252d250673..e712afc168f 100644
--- a/components/soc/esp32s3/include/soc/timer_group_reg.h
+++ b/components/soc/esp32s3/register/soc/timer_group_reg.h
@@ -1,16 +1,7 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
diff --git a/components/soc/esp32s3/include/soc/timer_group_struct.h b/components/soc/esp32s3/register/soc/timer_group_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/timer_group_struct.h
rename to components/soc/esp32s3/register/soc/timer_group_struct.h
diff --git a/components/soc/esp32s3/include/soc/twai_struct.h b/components/soc/esp32s3/register/soc/twai_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/twai_struct.h
rename to components/soc/esp32s3/register/soc/twai_struct.h
diff --git a/components/soc/esp32s3/register/soc/uart_reg.h b/components/soc/esp32s3/register/soc/uart_reg.h
new file mode 100644
index 00000000000..ecae7cb6462
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/uart_reg.h
@@ -0,0 +1,1523 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UART_FIFO_REG register
+ *  FIFO data register
+ */
+#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
+/** UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0;
+ *  UART(i) accesses FIFO via this register.
+ */
+#define UART_RXFIFO_RD_BYTE    0x000000FFU
+#define UART_RXFIFO_RD_BYTE_M  (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S)
+#define UART_RXFIFO_RD_BYTE_V  0x000000FFU
+#define UART_RXFIFO_RD_BYTE_S  0
+
+/** UART_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4)
+/** UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  what rxfifo_full_thrhd specifies.
+ */
+#define UART_RXFIFO_FULL_INT_RAW    (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S)
+#define UART_RXFIFO_FULL_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+/** UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1;
+ *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+ *  less than what txfifo_empty_thrhd specifies .
+ */
+#define UART_TXFIFO_EMPTY_INT_RAW    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S)
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/** UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error in
+ *  the data.
+ */
+#define UART_PARITY_ERR_INT_RAW    (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S)
+#define UART_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_PARITY_ERR_INT_RAW_S  2
+/** UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  .
+ */
+#define UART_FRM_ERR_INT_RAW    (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S)
+#define UART_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_FRM_ERR_INT_RAW_S  3
+/** UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives more data than
+ *  the FIFO can store.
+ */
+#define UART_RXFIFO_OVF_INT_RAW    (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S)
+#define UART_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/** UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  DSRn signal.
+ */
+#define UART_DSR_CHG_INT_RAW    (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S)
+#define UART_DSR_CHG_INT_RAW_V  0x00000001U
+#define UART_DSR_CHG_INT_RAW_S  5
+/** UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the edge change of
+ *  CTSn signal.
+ */
+#define UART_CTS_CHG_INT_RAW    (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S)
+#define UART_CTS_CHG_INT_RAW_V  0x00000001U
+#define UART_CTS_CHG_INT_RAW_S  6
+/** UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+ *  bit.
+ */
+#define UART_BRK_DET_INT_RAW    (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S)
+#define UART_BRK_DET_INT_RAW_V  0x00000001U
+#define UART_BRK_DET_INT_RAW_S  7
+/** UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver takes more time than
+ *  rx_tout_thrhd to receive a byte.
+ */
+#define UART_RXFIFO_TOUT_INT_RAW    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S)
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xon char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XON_INT_RAW    (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S)
+#define UART_SW_XON_INT_RAW_V  0x00000001U
+#define UART_SW_XON_INT_RAW_S  9
+/** UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+ *  uart_sw_flow_con_en is set to 1.
+ */
+#define UART_SW_XOFF_INT_RAW    (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S)
+#define UART_SW_XOFF_INT_RAW_V  0x00000001U
+#define UART_SW_XOFF_INT_RAW_S  10
+/** UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+ *  middle of a start bit.
+ */
+#define UART_GLITCH_DET_INT_RAW    (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S)
+#define UART_GLITCH_DET_INT_RAW_V  0x00000001U
+#define UART_GLITCH_DET_INT_RAW_S  11
+/** UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter completes  sending
+ *  NULL characters, after all data in Tx-FIFO are sent.
+ */
+#define UART_TX_BRK_DONE_INT_RAW    (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S)
+#define UART_TX_BRK_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+ *  duration after sending the  last data.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S)
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/** UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  This interrupt raw bit turns to high level when transmitter has send out all data
+ *  in FIFO.
+ */
+#define UART_TX_DONE_INT_RAW    (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S)
+#define UART_TX_DONE_INT_RAW_V  0x00000001U
+#define UART_TX_DONE_INT_RAW_S  14
+/** UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a parity error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_PARITY_ERR_INT_RAW    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S)
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/** UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects a data frame error
+ *  from the echo of transmitter in rs485 mode.
+ */
+#define UART_RS485_FRM_ERR_INT_RAW    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S)
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/** UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0;
+ *  This interrupt raw bit turns to high level when detects a clash between transmitter
+ *  and receiver in rs485 mode.
+ */
+#define UART_RS485_CLASH_INT_RAW    (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S)
+#define UART_RS485_CLASH_INT_RAW_V  0x00000001U
+#define UART_RS485_CLASH_INT_RAW_S  17
+/** UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0;
+ *  This interrupt raw bit turns to high level when receiver detects the configured
+ *  at_cmd char.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_RAW    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S)
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/** UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0;
+ *  This interrupt raw bit turns to high level when input rxd edge changes more times
+ *  than what reg_active_threshold specifies in light sleeping mode.
+ */
+#define UART_WAKEUP_INT_RAW    (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S)
+#define UART_WAKEUP_INT_RAW_V  0x00000001U
+#define UART_WAKEUP_INT_RAW_S  19
+
+/** UART_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8)
+/** UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+ */
+#define UART_RXFIFO_FULL_INT_ST    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S)
+#define UART_RXFIFO_FULL_INT_ST_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ST_S  0
+/** UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0;
+ *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+ *  to 1.
+ */
+#define UART_TXFIFO_EMPTY_INT_ST    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S)
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/** UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0;
+ *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+ */
+#define UART_PARITY_ERR_INT_ST    (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S)
+#define UART_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_PARITY_ERR_INT_ST_S  2
+/** UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0;
+ *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+ */
+#define UART_FRM_ERR_INT_ST    (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S)
+#define UART_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_FRM_ERR_INT_ST_S  3
+/** UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+ */
+#define UART_RXFIFO_OVF_INT_ST    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S)
+#define UART_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/** UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0;
+ *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+ */
+#define UART_DSR_CHG_INT_ST    (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S)
+#define UART_DSR_CHG_INT_ST_V  0x00000001U
+#define UART_DSR_CHG_INT_ST_S  5
+/** UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0;
+ *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+ */
+#define UART_CTS_CHG_INT_ST    (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S)
+#define UART_CTS_CHG_INT_ST_V  0x00000001U
+#define UART_CTS_CHG_INT_ST_S  6
+/** UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0;
+ *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+ */
+#define UART_BRK_DET_INT_ST    (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S)
+#define UART_BRK_DET_INT_ST_V  0x00000001U
+#define UART_BRK_DET_INT_ST_S  7
+/** UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+ */
+#define UART_RXFIFO_TOUT_INT_ST    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S)
+#define UART_RXFIFO_TOUT_INT_ST_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/** UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0;
+ *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+ */
+#define UART_SW_XON_INT_ST    (BIT(9))
+#define UART_SW_XON_INT_ST_M  (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S)
+#define UART_SW_XON_INT_ST_V  0x00000001U
+#define UART_SW_XON_INT_ST_S  9
+/** UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0;
+ *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+ */
+#define UART_SW_XOFF_INT_ST    (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S)
+#define UART_SW_XOFF_INT_ST_V  0x00000001U
+#define UART_SW_XOFF_INT_ST_S  10
+/** UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0;
+ *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+ */
+#define UART_GLITCH_DET_INT_ST    (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S)
+#define UART_GLITCH_DET_INT_ST_V  0x00000001U
+#define UART_GLITCH_DET_INT_ST_S  11
+/** UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0;
+ *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+ */
+#define UART_TX_BRK_DONE_INT_ST    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S)
+#define UART_TX_BRK_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0;
+ *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+ *  is set to 1.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ST    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/** UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0;
+ *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+ */
+#define UART_TX_DONE_INT_ST    (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S)
+#define UART_TX_DONE_INT_ST_V  0x00000001U
+#define UART_TX_DONE_INT_ST_S  14
+/** UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0;
+ *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+ *  set to 1.
+ */
+#define UART_RS485_PARITY_ERR_INT_ST    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S)
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/** UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0;
+ *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+ *  to 1.
+ */
+#define UART_RS485_FRM_ERR_INT_ST    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S)
+#define UART_RS485_FRM_ERR_INT_ST_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/** UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0;
+ *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+ */
+#define UART_RS485_CLASH_INT_ST    (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S)
+#define UART_RS485_CLASH_INT_ST_V  0x00000001U
+#define UART_RS485_CLASH_INT_ST_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0;
+ *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+ *  to 1.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ST    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S)
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/** UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0;
+ *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+ */
+#define UART_WAKEUP_INT_ST    (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S)
+#define UART_WAKEUP_INT_ST_V  0x00000001U
+#define UART_WAKEUP_INT_ST_S  19
+
+/** UART_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc)
+/** UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for rxfifo_full_int_st register.
+ */
+#define UART_RXFIFO_FULL_INT_ENA    (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S)
+#define UART_RXFIFO_FULL_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+/** UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  This is the enable bit for txfifo_empty_int_st register.
+ */
+#define UART_TXFIFO_EMPTY_INT_ENA    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S)
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/** UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  This is the enable bit for parity_err_int_st register.
+ */
+#define UART_PARITY_ERR_INT_ENA    (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S)
+#define UART_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_PARITY_ERR_INT_ENA_S  2
+/** UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  This is the enable bit for frm_err_int_st register.
+ */
+#define UART_FRM_ERR_INT_ENA    (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S)
+#define UART_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_FRM_ERR_INT_ENA_S  3
+/** UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  This is the enable bit for rxfifo_ovf_int_st register.
+ */
+#define UART_RXFIFO_OVF_INT_ENA    (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S)
+#define UART_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/** UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  This is the enable bit for dsr_chg_int_st register.
+ */
+#define UART_DSR_CHG_INT_ENA    (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S)
+#define UART_DSR_CHG_INT_ENA_V  0x00000001U
+#define UART_DSR_CHG_INT_ENA_S  5
+/** UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  This is the enable bit for cts_chg_int_st register.
+ */
+#define UART_CTS_CHG_INT_ENA    (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S)
+#define UART_CTS_CHG_INT_ENA_V  0x00000001U
+#define UART_CTS_CHG_INT_ENA_S  6
+/** UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  This is the enable bit for brk_det_int_st register.
+ */
+#define UART_BRK_DET_INT_ENA    (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S)
+#define UART_BRK_DET_INT_ENA_V  0x00000001U
+#define UART_BRK_DET_INT_ENA_S  7
+/** UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  This is the enable bit for rxfifo_tout_int_st register.
+ */
+#define UART_RXFIFO_TOUT_INT_ENA    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S)
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/** UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  This is the enable bit for sw_xon_int_st register.
+ */
+#define UART_SW_XON_INT_ENA    (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S)
+#define UART_SW_XON_INT_ENA_V  0x00000001U
+#define UART_SW_XON_INT_ENA_S  9
+/** UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  This is the enable bit for sw_xoff_int_st register.
+ */
+#define UART_SW_XOFF_INT_ENA    (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S)
+#define UART_SW_XOFF_INT_ENA_V  0x00000001U
+#define UART_SW_XOFF_INT_ENA_S  10
+/** UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  This is the enable bit for glitch_det_int_st register.
+ */
+#define UART_GLITCH_DET_INT_ENA    (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S)
+#define UART_GLITCH_DET_INT_ENA_V  0x00000001U
+#define UART_GLITCH_DET_INT_ENA_S  11
+/** UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  This is the enable bit for tx_brk_done_int_st register.
+ */
+#define UART_TX_BRK_DONE_INT_ENA    (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S)
+#define UART_TX_BRK_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  This is the enable bit for tx_brk_idle_done_int_st register.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S)
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/** UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  This is the enable bit for tx_done_int_st register.
+ */
+#define UART_TX_DONE_INT_ENA    (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S)
+#define UART_TX_DONE_INT_ENA_V  0x00000001U
+#define UART_TX_DONE_INT_ENA_S  14
+/** UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_PARITY_ERR_INT_ENA    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S)
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/** UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  This is the enable bit for rs485_parity_err_int_st register.
+ */
+#define UART_RS485_FRM_ERR_INT_ENA    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S)
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/** UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  This is the enable bit for rs485_clash_int_st register.
+ */
+#define UART_RS485_CLASH_INT_ENA    (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S)
+#define UART_RS485_CLASH_INT_ENA_V  0x00000001U
+#define UART_RS485_CLASH_INT_ENA_S  17
+/** UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  This is the enable bit for at_cmd_char_det_int_st register.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_ENA    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S)
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/** UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0;
+ *  This is the enable bit for uart_wakeup_int_st register.
+ */
+#define UART_WAKEUP_INT_ENA    (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S)
+#define UART_WAKEUP_INT_ENA_V  0x00000001U
+#define UART_WAKEUP_INT_ENA_S  19
+
+/** UART_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10)
+/** UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+ */
+#define UART_RXFIFO_FULL_INT_CLR    (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S)
+#define UART_RXFIFO_FULL_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+/** UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear txfifo_empty_int_raw interrupt.
+ */
+#define UART_TXFIFO_EMPTY_INT_CLR    (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S)
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x00000001U
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/** UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear parity_err_int_raw interrupt.
+ */
+#define UART_PARITY_ERR_INT_CLR    (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S)
+#define UART_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_PARITY_ERR_INT_CLR_S  2
+/** UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear frm_err_int_raw interrupt.
+ */
+#define UART_FRM_ERR_INT_CLR    (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S)
+#define UART_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_FRM_ERR_INT_CLR_S  3
+/** UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+ */
+#define UART_RXFIFO_OVF_INT_CLR    (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S)
+#define UART_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/** UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the dsr_chg_int_raw interrupt.
+ */
+#define UART_DSR_CHG_INT_CLR    (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S)
+#define UART_DSR_CHG_INT_CLR_V  0x00000001U
+#define UART_DSR_CHG_INT_CLR_S  5
+/** UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the cts_chg_int_raw interrupt.
+ */
+#define UART_CTS_CHG_INT_CLR    (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S)
+#define UART_CTS_CHG_INT_CLR_V  0x00000001U
+#define UART_CTS_CHG_INT_CLR_S  6
+/** UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the brk_det_int_raw interrupt.
+ */
+#define UART_BRK_DET_INT_CLR    (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S)
+#define UART_BRK_DET_INT_CLR_V  0x00000001U
+#define UART_BRK_DET_INT_CLR_S  7
+/** UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+ */
+#define UART_RXFIFO_TOUT_INT_CLR    (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S)
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x00000001U
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/** UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the sw_xon_int_raw interrupt.
+ */
+#define UART_SW_XON_INT_CLR    (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S)
+#define UART_SW_XON_INT_CLR_V  0x00000001U
+#define UART_SW_XON_INT_CLR_S  9
+/** UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the sw_xoff_int_raw interrupt.
+ */
+#define UART_SW_XOFF_INT_CLR    (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S)
+#define UART_SW_XOFF_INT_CLR_V  0x00000001U
+#define UART_SW_XOFF_INT_CLR_S  10
+/** UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the glitch_det_int_raw interrupt.
+ */
+#define UART_GLITCH_DET_INT_CLR    (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S)
+#define UART_GLITCH_DET_INT_CLR_V  0x00000001U
+#define UART_GLITCH_DET_INT_CLR_S  11
+/** UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+ */
+#define UART_TX_BRK_DONE_INT_CLR    (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S)
+#define UART_TX_BRK_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/** UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+ */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR    (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S)
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/** UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Set this bit to clear the tx_done_int_raw interrupt.
+ */
+#define UART_TX_DONE_INT_CLR    (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S)
+#define UART_TX_DONE_INT_CLR_V  0x00000001U
+#define UART_TX_DONE_INT_CLR_S  14
+/** UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+ */
+#define UART_RS485_PARITY_ERR_INT_CLR    (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S)
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/** UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+ */
+#define UART_RS485_FRM_ERR_INT_CLR    (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S)
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x00000001U
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/** UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Set this bit to clear the rs485_clash_int_raw interrupt.
+ */
+#define UART_RS485_CLASH_INT_CLR    (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S)
+#define UART_RS485_CLASH_INT_CLR_V  0x00000001U
+#define UART_RS485_CLASH_INT_CLR_S  17
+/** UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+ */
+#define UART_AT_CMD_CHAR_DET_INT_CLR    (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S)
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x00000001U
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/** UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0;
+ *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+ */
+#define UART_WAKEUP_INT_CLR    (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S)
+#define UART_WAKEUP_INT_CLR_V  0x00000001U
+#define UART_WAKEUP_INT_CLR_S  19
+
+/** UART_CLKDIV_REG register
+ *  Clock divider configuration
+ */
+#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14)
+/** UART_CLKDIV : R/W; bitpos: [11:0]; default: 694;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_CLKDIV    0x00000FFFU
+#define UART_CLKDIV_M  (UART_CLKDIV_V << UART_CLKDIV_S)
+#define UART_CLKDIV_V  0x00000FFFU
+#define UART_CLKDIV_S  0
+/** UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0;
+ *  The decimal part of the frequency divider factor.
+ */
+#define UART_CLKDIV_FRAG    0x0000000FU
+#define UART_CLKDIV_FRAG_M  (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S)
+#define UART_CLKDIV_FRAG_V  0x0000000FU
+#define UART_CLKDIV_FRAG_S  20
+
+/** UART_RX_FILT_REG register
+ *  Rx Filter configuration
+ */
+#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18)
+/** UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8;
+ *  when input pulse width is lower than this value, the pulse is ignored.
+ */
+#define UART_GLITCH_FILT    0x000000FFU
+#define UART_GLITCH_FILT_M  (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S)
+#define UART_GLITCH_FILT_V  0x000000FFU
+#define UART_GLITCH_FILT_S  0
+/** UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable Rx signal filter.
+ */
+#define UART_GLITCH_FILT_EN    (BIT(8))
+#define UART_GLITCH_FILT_EN_M  (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S)
+#define UART_GLITCH_FILT_EN_V  0x00000001U
+#define UART_GLITCH_FILT_EN_S  8
+
+/** UART_STATUS_REG register
+ *  UART status register
+ */
+#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c)
+/** UART_RXFIFO_CNT : RO; bitpos: [9:0]; default: 0;
+ *  Stores the byte number of valid data in Rx-FIFO.
+ */
+#define UART_RXFIFO_CNT    0x000003FFU
+#define UART_RXFIFO_CNT_M  (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S)
+#define UART_RXFIFO_CNT_V  0x000003FFU
+#define UART_RXFIFO_CNT_S  0
+/** UART_DSRN : RO; bitpos: [13]; default: 0;
+ *  The register represent the level value of the internal uart dsr signal.
+ */
+#define UART_DSRN    (BIT(13))
+#define UART_DSRN_M  (UART_DSRN_V << UART_DSRN_S)
+#define UART_DSRN_V  0x00000001U
+#define UART_DSRN_S  13
+/** UART_CTSN : RO; bitpos: [14]; default: 1;
+ *  This register represent the level value of the internal uart cts signal.
+ */
+#define UART_CTSN    (BIT(14))
+#define UART_CTSN_M  (UART_CTSN_V << UART_CTSN_S)
+#define UART_CTSN_V  0x00000001U
+#define UART_CTSN_S  14
+/** UART_RXD : RO; bitpos: [15]; default: 1;
+ *  This register represent the  level value of the internal uart rxd signal.
+ */
+#define UART_RXD    (BIT(15))
+#define UART_RXD_M  (UART_RXD_V << UART_RXD_S)
+#define UART_RXD_V  0x00000001U
+#define UART_RXD_S  15
+/** UART_TXFIFO_CNT : RO; bitpos: [25:16]; default: 0;
+ *  Stores the byte number of data in Tx-FIFO.
+ */
+#define UART_TXFIFO_CNT    0x000003FFU
+#define UART_TXFIFO_CNT_M  (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S)
+#define UART_TXFIFO_CNT_V  0x000003FFU
+#define UART_TXFIFO_CNT_S  16
+/** UART_DTRN : RO; bitpos: [29]; default: 1;
+ *  This bit represents the level of the internal uart dtr signal.
+ */
+#define UART_DTRN    (BIT(29))
+#define UART_DTRN_M  (UART_DTRN_V << UART_DTRN_S)
+#define UART_DTRN_V  0x00000001U
+#define UART_DTRN_S  29
+/** UART_RTSN : RO; bitpos: [30]; default: 1;
+ *  This bit represents the level of the internal uart rts signal.
+ */
+#define UART_RTSN    (BIT(30))
+#define UART_RTSN_M  (UART_RTSN_V << UART_RTSN_S)
+#define UART_RTSN_V  0x00000001U
+#define UART_RTSN_S  30
+/** UART_TXD : RO; bitpos: [31]; default: 1;
+ *  This bit represents the  level of the internal uart txd signal.
+ */
+#define UART_TXD    (BIT(31))
+#define UART_TXD_M  (UART_TXD_V << UART_TXD_S)
+#define UART_TXD_V  0x00000001U
+#define UART_TXD_S  31
+
+/** UART_CONF0_REG register
+ *  a
+ */
+#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20)
+/** UART_PARITY : R/W; bitpos: [0]; default: 0;
+ *  This register is used to configure the parity check mode.
+ */
+#define UART_PARITY    (BIT(0))
+#define UART_PARITY_M  (UART_PARITY_V << UART_PARITY_S)
+#define UART_PARITY_V  0x00000001U
+#define UART_PARITY_S  0
+/** UART_PARITY_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to enable uart parity check.
+ */
+#define UART_PARITY_EN    (BIT(1))
+#define UART_PARITY_EN_M  (UART_PARITY_EN_V << UART_PARITY_EN_S)
+#define UART_PARITY_EN_V  0x00000001U
+#define UART_PARITY_EN_S  1
+/** UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3;
+ *  This register is used to set the length of data.
+ */
+#define UART_BIT_NUM    0x00000003U
+#define UART_BIT_NUM_M  (UART_BIT_NUM_V << UART_BIT_NUM_S)
+#define UART_BIT_NUM_V  0x00000003U
+#define UART_BIT_NUM_S  2
+/** UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1;
+ *  This register is used to set the length of  stop bit.
+ */
+#define UART_STOP_BIT_NUM    0x00000003U
+#define UART_STOP_BIT_NUM_M  (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S)
+#define UART_STOP_BIT_NUM_V  0x00000003U
+#define UART_STOP_BIT_NUM_S  4
+/** UART_SW_RTS : R/W; bitpos: [6]; default: 0;
+ *  This register is used to configure the software rts signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_RTS    (BIT(6))
+#define UART_SW_RTS_M  (UART_SW_RTS_V << UART_SW_RTS_S)
+#define UART_SW_RTS_V  0x00000001U
+#define UART_SW_RTS_S  6
+/** UART_SW_DTR : R/W; bitpos: [7]; default: 0;
+ *  This register is used to configure the software dtr signal which is used in
+ *  software flow control.
+ */
+#define UART_SW_DTR    (BIT(7))
+#define UART_SW_DTR_M  (UART_SW_DTR_V << UART_SW_DTR_S)
+#define UART_SW_DTR_V  0x00000001U
+#define UART_SW_DTR_S  7
+/** UART_TXD_BRK : R/W; bitpos: [8]; default: 0;
+ *  Set this bit to enable transmitter to  send NULL when the process of sending data
+ *  is done.
+ */
+#define UART_TXD_BRK    (BIT(8))
+#define UART_TXD_BRK_M  (UART_TXD_BRK_V << UART_TXD_BRK_S)
+#define UART_TXD_BRK_V  0x00000001U
+#define UART_TXD_BRK_S  8
+/** UART_IRDA_DPLX : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to enable IrDA loopback mode.
+ */
+#define UART_IRDA_DPLX    (BIT(9))
+#define UART_IRDA_DPLX_M  (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S)
+#define UART_IRDA_DPLX_V  0x00000001U
+#define UART_IRDA_DPLX_S  9
+/** UART_IRDA_TX_EN : R/W; bitpos: [10]; default: 0;
+ *  This is the start enable bit for IrDA transmitter.
+ */
+#define UART_IRDA_TX_EN    (BIT(10))
+#define UART_IRDA_TX_EN_M  (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S)
+#define UART_IRDA_TX_EN_V  0x00000001U
+#define UART_IRDA_TX_EN_S  10
+/** UART_IRDA_WCTL : R/W; bitpos: [11]; default: 0;
+ *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+ *  transmitter's 11th bit to 0.
+ */
+#define UART_IRDA_WCTL    (BIT(11))
+#define UART_IRDA_WCTL_M  (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S)
+#define UART_IRDA_WCTL_V  0x00000001U
+#define UART_IRDA_WCTL_S  11
+/** UART_IRDA_TX_INV : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to invert the level of  IrDA transmitter.
+ */
+#define UART_IRDA_TX_INV    (BIT(12))
+#define UART_IRDA_TX_INV_M  (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S)
+#define UART_IRDA_TX_INV_V  0x00000001U
+#define UART_IRDA_TX_INV_S  12
+/** UART_IRDA_RX_INV : R/W; bitpos: [13]; default: 0;
+ *  Set this bit to invert the level of IrDA receiver.
+ */
+#define UART_IRDA_RX_INV    (BIT(13))
+#define UART_IRDA_RX_INV_M  (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S)
+#define UART_IRDA_RX_INV_V  0x00000001U
+#define UART_IRDA_RX_INV_S  13
+/** UART_LOOPBACK : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to enable uart loopback test mode.
+ */
+#define UART_LOOPBACK    (BIT(14))
+#define UART_LOOPBACK_M  (UART_LOOPBACK_V << UART_LOOPBACK_S)
+#define UART_LOOPBACK_V  0x00000001U
+#define UART_LOOPBACK_S  14
+/** UART_TX_FLOW_EN : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to enable flow control function for transmitter.
+ */
+#define UART_TX_FLOW_EN    (BIT(15))
+#define UART_TX_FLOW_EN_M  (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S)
+#define UART_TX_FLOW_EN_V  0x00000001U
+#define UART_TX_FLOW_EN_S  15
+/** UART_IRDA_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit to enable IrDA protocol.
+ */
+#define UART_IRDA_EN    (BIT(16))
+#define UART_IRDA_EN_M  (UART_IRDA_EN_V << UART_IRDA_EN_S)
+#define UART_IRDA_EN_V  0x00000001U
+#define UART_IRDA_EN_S  16
+/** UART_RXFIFO_RST : R/W; bitpos: [17]; default: 0;
+ *  Set this bit to reset the uart receive-FIFO.
+ */
+#define UART_RXFIFO_RST    (BIT(17))
+#define UART_RXFIFO_RST_M  (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S)
+#define UART_RXFIFO_RST_V  0x00000001U
+#define UART_RXFIFO_RST_S  17
+/** UART_TXFIFO_RST : R/W; bitpos: [18]; default: 0;
+ *  Set this bit to reset the uart transmit-FIFO.
+ */
+#define UART_TXFIFO_RST    (BIT(18))
+#define UART_TXFIFO_RST_M  (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S)
+#define UART_TXFIFO_RST_V  0x00000001U
+#define UART_TXFIFO_RST_S  18
+/** UART_RXD_INV : R/W; bitpos: [19]; default: 0;
+ *  Set this bit to inverse the level value of uart rxd signal.
+ */
+#define UART_RXD_INV    (BIT(19))
+#define UART_RXD_INV_M  (UART_RXD_INV_V << UART_RXD_INV_S)
+#define UART_RXD_INV_V  0x00000001U
+#define UART_RXD_INV_S  19
+/** UART_CTS_INV : R/W; bitpos: [20]; default: 0;
+ *  Set this bit to inverse the level value of uart cts signal.
+ */
+#define UART_CTS_INV    (BIT(20))
+#define UART_CTS_INV_M  (UART_CTS_INV_V << UART_CTS_INV_S)
+#define UART_CTS_INV_V  0x00000001U
+#define UART_CTS_INV_S  20
+/** UART_DSR_INV : R/W; bitpos: [21]; default: 0;
+ *  Set this bit to inverse the level value of uart dsr signal.
+ */
+#define UART_DSR_INV    (BIT(21))
+#define UART_DSR_INV_M  (UART_DSR_INV_V << UART_DSR_INV_S)
+#define UART_DSR_INV_V  0x00000001U
+#define UART_DSR_INV_S  21
+/** UART_TXD_INV : R/W; bitpos: [22]; default: 0;
+ *  Set this bit to inverse the level value of uart txd signal.
+ */
+#define UART_TXD_INV    (BIT(22))
+#define UART_TXD_INV_M  (UART_TXD_INV_V << UART_TXD_INV_S)
+#define UART_TXD_INV_V  0x00000001U
+#define UART_TXD_INV_S  22
+/** UART_RTS_INV : R/W; bitpos: [23]; default: 0;
+ *  Set this bit to inverse the level value of uart rts signal.
+ */
+#define UART_RTS_INV    (BIT(23))
+#define UART_RTS_INV_M  (UART_RTS_INV_V << UART_RTS_INV_S)
+#define UART_RTS_INV_V  0x00000001U
+#define UART_RTS_INV_S  23
+/** UART_DTR_INV : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to inverse the level value of uart dtr signal.
+ */
+#define UART_DTR_INV    (BIT(24))
+#define UART_DTR_INV_M  (UART_DTR_INV_V << UART_DTR_INV_S)
+#define UART_DTR_INV_V  0x00000001U
+#define UART_DTR_INV_S  24
+/** UART_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define UART_CLK_EN    (BIT(25))
+#define UART_CLK_EN_M  (UART_CLK_EN_V << UART_CLK_EN_S)
+#define UART_CLK_EN_V  0x00000001U
+#define UART_CLK_EN_S  25
+/** UART_ERR_WR_MASK : R/W; bitpos: [26]; default: 0;
+ *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+ *  stores the data even if the  received data is wrong.
+ */
+#define UART_ERR_WR_MASK    (BIT(26))
+#define UART_ERR_WR_MASK_M  (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S)
+#define UART_ERR_WR_MASK_V  0x00000001U
+#define UART_ERR_WR_MASK_S  26
+/** UART_AUTOBAUD_EN : R/W; bitpos: [27]; default: 0;
+ *  This is the enable bit for detecting baudrate.
+ */
+#define UART_AUTOBAUD_EN    (BIT(27))
+#define UART_AUTOBAUD_EN_M  (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S)
+#define UART_AUTOBAUD_EN_V  0x00000001U
+#define UART_AUTOBAUD_EN_S  27
+/** UART_MEM_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  UART memory clock gate enable signal.
+ */
+#define UART_MEM_CLK_EN    (BIT(28))
+#define UART_MEM_CLK_EN_M  (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S)
+#define UART_MEM_CLK_EN_V  0x00000001U
+#define UART_MEM_CLK_EN_S  28
+
+/** UART_CONF1_REG register
+ *  Configuration register 1
+ */
+#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
+/** UART_RXFIFO_FULL_THRHD : R/W; bitpos: [9:0]; default: 96;
+ *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+ *  this register value.
+ */
+#define UART_RXFIFO_FULL_THRHD    0x000003FFU
+#define UART_RXFIFO_FULL_THRHD_M  (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S)
+#define UART_RXFIFO_FULL_THRHD_V  0x000003FFU
+#define UART_RXFIFO_FULL_THRHD_S  0
+/** UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [19:10]; default: 96;
+ *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+ *  than this register value.
+ */
+#define UART_TXFIFO_EMPTY_THRHD    0x000003FFU
+#define UART_TXFIFO_EMPTY_THRHD_M  (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S)
+#define UART_TXFIFO_EMPTY_THRHD_V  0x000003FFU
+#define UART_TXFIFO_EMPTY_THRHD_S  10
+/** UART_DIS_RX_DAT_OVF : R/W; bitpos: [20]; default: 0;
+ *  Disable UART Rx data overflow detect.
+ */
+#define UART_DIS_RX_DAT_OVF    (BIT(20))
+#define UART_DIS_RX_DAT_OVF_M  (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S)
+#define UART_DIS_RX_DAT_OVF_V  0x00000001U
+#define UART_DIS_RX_DAT_OVF_S  20
+/** UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [21]; default: 0;
+ *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+ */
+#define UART_RX_TOUT_FLOW_DIS    (BIT(21))
+#define UART_RX_TOUT_FLOW_DIS_M  (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S)
+#define UART_RX_TOUT_FLOW_DIS_V  0x00000001U
+#define UART_RX_TOUT_FLOW_DIS_S  21
+/** UART_RX_FLOW_EN : R/W; bitpos: [22]; default: 0;
+ *  This is the flow enable bit for UART receiver.
+ */
+#define UART_RX_FLOW_EN    (BIT(22))
+#define UART_RX_FLOW_EN_M  (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S)
+#define UART_RX_FLOW_EN_V  0x00000001U
+#define UART_RX_FLOW_EN_S  22
+/** UART_RX_TOUT_EN : R/W; bitpos: [23]; default: 0;
+ *  This is the enable bit for uart receiver's timeout function.
+ */
+#define UART_RX_TOUT_EN    (BIT(23))
+#define UART_RX_TOUT_EN_M  (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
+#define UART_RX_TOUT_EN_V  0x00000001U
+#define UART_RX_TOUT_EN_S  23
+
+/** UART_LOWPULSE_REG register
+ *  Autobaud minimum low pulse duration register
+ */
+#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28)
+/** UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the value of the minimum duration time of the low level pulse.
+ *  It is used in baud rate-detect process.
+ */
+#define UART_LOWPULSE_MIN_CNT    0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_M  (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S)
+#define UART_LOWPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+/** UART_HIGHPULSE_REG register
+ *  Autobaud minimum high pulse duration register
+ */
+#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c)
+/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores  the value of the maximum duration time for the high level
+ *  pulse. It is used in baud rate-detect process.
+ */
+#define UART_HIGHPULSE_MIN_CNT    0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_M  (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S)
+#define UART_HIGHPULSE_MIN_CNT_V  0x00000FFFU
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+/** UART_RXD_CNT_REG register
+ *  Autobaud edge change count register
+ */
+#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30)
+/** UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the count of rxd edge change. It is used in baud rate-detect
+ *  process.
+ */
+#define UART_RXD_EDGE_CNT    0x000003FFU
+#define UART_RXD_EDGE_CNT_M  (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S)
+#define UART_RXD_EDGE_CNT_V  0x000003FFU
+#define UART_RXD_EDGE_CNT_S  0
+
+/** UART_FLOW_CONF_REG register
+ *  Software flow-control configuration
+ */
+#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34)
+/** UART_SW_FLOW_CON_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable software flow control. It is used with register sw_xon or
+ *  sw_xoff.
+ */
+#define UART_SW_FLOW_CON_EN    (BIT(0))
+#define UART_SW_FLOW_CON_EN_M  (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S)
+#define UART_SW_FLOW_CON_EN_V  0x00000001U
+#define UART_SW_FLOW_CON_EN_S  0
+/** UART_XONOFF_DEL : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to remove flow control char from the received data.
+ */
+#define UART_XONOFF_DEL    (BIT(1))
+#define UART_XONOFF_DEL_M  (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S)
+#define UART_XONOFF_DEL_V  0x00000001U
+#define UART_XONOFF_DEL_S  1
+/** UART_FORCE_XON : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable the transmitter to go on sending data.
+ */
+#define UART_FORCE_XON    (BIT(2))
+#define UART_FORCE_XON_M  (UART_FORCE_XON_V << UART_FORCE_XON_S)
+#define UART_FORCE_XON_V  0x00000001U
+#define UART_FORCE_XON_S  2
+/** UART_FORCE_XOFF : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to stop the  transmitter from sending data.
+ */
+#define UART_FORCE_XOFF    (BIT(3))
+#define UART_FORCE_XOFF_M  (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S)
+#define UART_FORCE_XOFF_V  0x00000001U
+#define UART_FORCE_XOFF_S  3
+/** UART_SEND_XON : R/W/SS/SC; bitpos: [4]; default: 0;
+ *  Set this bit to send Xon char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XON    (BIT(4))
+#define UART_SEND_XON_M  (UART_SEND_XON_V << UART_SEND_XON_S)
+#define UART_SEND_XON_V  0x00000001U
+#define UART_SEND_XON_S  4
+/** UART_SEND_XOFF : R/W/SS/SC; bitpos: [5]; default: 0;
+ *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+ */
+#define UART_SEND_XOFF    (BIT(5))
+#define UART_SEND_XOFF_M  (UART_SEND_XOFF_V << UART_SEND_XOFF_S)
+#define UART_SEND_XOFF_V  0x00000001U
+#define UART_SEND_XOFF_S  5
+
+/** UART_SLEEP_CONF_REG register
+ *  Sleep-mode configuration
+ */
+#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
+/** UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240;
+ *  The uart is activated from light sleeping mode when the input rxd edge changes more
+ *  times than this register value.
+ */
+#define UART_ACTIVE_THRESHOLD    0x000003FFU
+#define UART_ACTIVE_THRESHOLD_M  (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S)
+#define UART_ACTIVE_THRESHOLD_V  0x000003FFU
+#define UART_ACTIVE_THRESHOLD_S  0
+
+/** UART_SWFC_CONF0_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3c)
+/** UART_XOFF_THRESHOLD : R/W; bitpos: [9:0]; default: 224;
+ *  When the data amount in Rx-FIFO is more than this register value with
+ *  uart_sw_flow_con_en set to 1, it will send a Xoff char.
+ */
+#define UART_XOFF_THRESHOLD    0x000003FFU
+#define UART_XOFF_THRESHOLD_M  (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S)
+#define UART_XOFF_THRESHOLD_V  0x000003FFU
+#define UART_XOFF_THRESHOLD_S  0
+/** UART_XOFF_CHAR : R/W; bitpos: [17:10]; default: 19;
+ *  This register stores the Xoff flow control char.
+ */
+#define UART_XOFF_CHAR    0x000000FFU
+#define UART_XOFF_CHAR_M  (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S)
+#define UART_XOFF_CHAR_V  0x000000FFU
+#define UART_XOFF_CHAR_S  10
+
+/** UART_SWFC_CONF1_REG register
+ *  Software flow-control character configuration
+ */
+#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40)
+/** UART_XON_THRESHOLD : R/W; bitpos: [9:0]; default: 0;
+ *  When the data amount in Rx-FIFO is less than this register value with
+ *  uart_sw_flow_con_en set to 1, it will send a Xon char.
+ */
+#define UART_XON_THRESHOLD    0x000003FFU
+#define UART_XON_THRESHOLD_M  (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S)
+#define UART_XON_THRESHOLD_V  0x000003FFU
+#define UART_XON_THRESHOLD_S  0
+/** UART_XON_CHAR : R/W; bitpos: [17:10]; default: 17;
+ *  This register stores the Xon flow control char.
+ */
+#define UART_XON_CHAR    0x000000FFU
+#define UART_XON_CHAR_M  (UART_XON_CHAR_V << UART_XON_CHAR_S)
+#define UART_XON_CHAR_V  0x000000FFU
+#define UART_XON_CHAR_S  10
+
+/** UART_TXBRK_CONF_REG register
+ *  Tx Break character configuration
+ */
+#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44)
+/** UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10;
+ *  This register is used to configure the number of 0 to be sent after the process of
+ *  sending data is done. It is active when txd_brk is set to 1.
+ */
+#define UART_TX_BRK_NUM    0x000000FFU
+#define UART_TX_BRK_NUM_M  (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S)
+#define UART_TX_BRK_NUM_V  0x000000FFU
+#define UART_TX_BRK_NUM_S  0
+
+/** UART_IDLE_CONF_REG register
+ *  Frame-end idle configuration
+ */
+#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48)
+/** UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256;
+ *  It will produce frame end signal when receiver takes more time to receive one byte
+ *  data than this register value.
+ */
+#define UART_RX_IDLE_THRHD    0x000003FFU
+#define UART_RX_IDLE_THRHD_M  (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S)
+#define UART_RX_IDLE_THRHD_V  0x000003FFU
+#define UART_RX_IDLE_THRHD_S  0
+/** UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256;
+ *  This register is used to configure the duration time between transfers.
+ */
+#define UART_TX_IDLE_NUM    0x000003FFU
+#define UART_TX_IDLE_NUM_M  (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S)
+#define UART_TX_IDLE_NUM_V  0x000003FFU
+#define UART_TX_IDLE_NUM_S  10
+
+/** UART_RS485_CONF_REG register
+ *  RS485 mode configuration
+ */
+#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4c)
+/** UART_RS485_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to choose the rs485 mode.
+ */
+#define UART_RS485_EN    (BIT(0))
+#define UART_RS485_EN_M  (UART_RS485_EN_V << UART_RS485_EN_S)
+#define UART_RS485_EN_V  0x00000001U
+#define UART_RS485_EN_S  0
+/** UART_DL0_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL0_EN    (BIT(1))
+#define UART_DL0_EN_M  (UART_DL0_EN_V << UART_DL0_EN_S)
+#define UART_DL0_EN_V  0x00000001U
+#define UART_DL0_EN_S  1
+/** UART_DL1_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to delay the stop bit by 1 bit.
+ */
+#define UART_DL1_EN    (BIT(2))
+#define UART_DL1_EN_M  (UART_DL1_EN_V << UART_DL1_EN_S)
+#define UART_DL1_EN_V  0x00000001U
+#define UART_DL1_EN_S  2
+/** UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable receiver could receive data when the transmitter is
+ *  transmitting data in rs485 mode.
+ */
+#define UART_RS485TX_RX_EN    (BIT(3))
+#define UART_RS485TX_RX_EN_M  (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S)
+#define UART_RS485TX_RX_EN_V  0x00000001U
+#define UART_RS485TX_RX_EN_S  3
+/** UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+ */
+#define UART_RS485RXBY_TX_EN    (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S)
+#define UART_RS485RXBY_TX_EN_V  0x00000001U
+#define UART_RS485RXBY_TX_EN_S  4
+/** UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0;
+ *  This register is used to delay the receiver's internal data signal.
+ */
+#define UART_RS485_RX_DLY_NUM    (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S)
+#define UART_RS485_RX_DLY_NUM_V  0x00000001U
+#define UART_RS485_RX_DLY_NUM_S  5
+/** UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0;
+ *  This register is used to delay the transmitter's internal data signal.
+ */
+#define UART_RS485_TX_DLY_NUM    0x0000000FU
+#define UART_RS485_TX_DLY_NUM_M  (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S)
+#define UART_RS485_TX_DLY_NUM_V  0x0000000FU
+#define UART_RS485_TX_DLY_NUM_S  6
+
+/** UART_AT_CMD_PRECNT_REG register
+ *  Pre-sequence timing configuration
+ */
+#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50)
+/** UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the idle duration time before the first at_cmd
+ *  is received by receiver.
+ */
+#define UART_PRE_IDLE_NUM    0x0000FFFFU
+#define UART_PRE_IDLE_NUM_M  (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S)
+#define UART_PRE_IDLE_NUM_V  0x0000FFFFU
+#define UART_PRE_IDLE_NUM_S  0
+
+/** UART_AT_CMD_POSTCNT_REG register
+ *  Post-sequence timing configuration
+ */
+#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54)
+/** UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305;
+ *  This register is used to configure the duration time between the last at_cmd and
+ *  the next data.
+ */
+#define UART_POST_IDLE_NUM    0x0000FFFFU
+#define UART_POST_IDLE_NUM_M  (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S)
+#define UART_POST_IDLE_NUM_V  0x0000FFFFU
+#define UART_POST_IDLE_NUM_S  0
+
+/** UART_AT_CMD_GAPTOUT_REG register
+ *  Timeout configuration
+ */
+#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58)
+/** UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11;
+ *  This register is used to configure the duration time between the at_cmd chars.
+ */
+#define UART_RX_GAP_TOUT    0x0000FFFFU
+#define UART_RX_GAP_TOUT_M  (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S)
+#define UART_RX_GAP_TOUT_V  0x0000FFFFU
+#define UART_RX_GAP_TOUT_S  0
+
+/** UART_AT_CMD_CHAR_REG register
+ *  AT escape sequence detection configuration
+ */
+#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c)
+/** UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43;
+ *  This register is used to configure the content of at_cmd char.
+ */
+#define UART_AT_CMD_CHAR    0x000000FFU
+#define UART_AT_CMD_CHAR_M  (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S)
+#define UART_AT_CMD_CHAR_V  0x000000FFU
+#define UART_AT_CMD_CHAR_S  0
+/** UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  This register is used to configure the num of continuous at_cmd chars received by
+ *  receiver.
+ */
+#define UART_CHAR_NUM    0x000000FFU
+#define UART_CHAR_NUM_M  (UART_CHAR_NUM_V << UART_CHAR_NUM_S)
+#define UART_CHAR_NUM_V  0x000000FFU
+#define UART_CHAR_NUM_S  8
+
+/** UART_MEM_CONF_REG register
+ *  UART threshold and allocation configuration
+ */
+#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60)
+/** UART_RX_SIZE : R/W; bitpos: [3:1]; default: 1;
+ *  This register is used to configure the amount of mem allocated for receive-FIFO.
+ *  The default number is 128 bytes.
+ */
+#define UART_RX_SIZE    0x00000007U
+#define UART_RX_SIZE_M  (UART_RX_SIZE_V << UART_RX_SIZE_S)
+#define UART_RX_SIZE_V  0x00000007U
+#define UART_RX_SIZE_S  1
+/** UART_TX_SIZE : R/W; bitpos: [6:4]; default: 1;
+ *  This register is used to configure the amount of mem allocated for transmit-FIFO.
+ *  The default number is 128 bytes.
+ */
+#define UART_TX_SIZE    0x00000007U
+#define UART_TX_SIZE_M  (UART_TX_SIZE_V << UART_TX_SIZE_S)
+#define UART_TX_SIZE_V  0x00000007U
+#define UART_TX_SIZE_S  4
+/** UART_RX_FLOW_THRHD : R/W; bitpos: [16:7]; default: 0;
+ *  This register is used to configure the maximum amount of data that can be received
+ *  when hardware flow control works.
+ */
+#define UART_RX_FLOW_THRHD    0x000003FFU
+#define UART_RX_FLOW_THRHD_M  (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S)
+#define UART_RX_FLOW_THRHD_V  0x000003FFU
+#define UART_RX_FLOW_THRHD_S  7
+/** UART_RX_TOUT_THRHD : R/W; bitpos: [26:17]; default: 10;
+ *  This register is used to configure the threshold time that receiver takes to
+ *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+ *  takes more time to receive one byte with rx_tout_en set to 1.
+ */
+#define UART_RX_TOUT_THRHD    0x000003FFU
+#define UART_RX_TOUT_THRHD_M  (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S)
+#define UART_RX_TOUT_THRHD_V  0x000003FFU
+#define UART_RX_TOUT_THRHD_S  17
+/** UART_MEM_FORCE_PD : R/W; bitpos: [27]; default: 0;
+ *  Set this bit to force power down UART memory.
+ */
+#define UART_MEM_FORCE_PD    (BIT(27))
+#define UART_MEM_FORCE_PD_M  (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S)
+#define UART_MEM_FORCE_PD_V  0x00000001U
+#define UART_MEM_FORCE_PD_S  27
+/** UART_MEM_FORCE_PU : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to force power up UART memory.
+ */
+#define UART_MEM_FORCE_PU    (BIT(28))
+#define UART_MEM_FORCE_PU_M  (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S)
+#define UART_MEM_FORCE_PU_V  0x00000001U
+#define UART_MEM_FORCE_PU_S  28
+
+/** UART_MEM_TX_STATUS_REG register
+ *  Tx-FIFO write and read offset address.
+ */
+#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64)
+/** UART_APB_TX_WADDR : RO; bitpos: [9:0]; default: 0;
+ *  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via
+ *  APB.
+ */
+#define UART_APB_TX_WADDR    0x000003FFU
+#define UART_APB_TX_WADDR_M  (UART_APB_TX_WADDR_V << UART_APB_TX_WADDR_S)
+#define UART_APB_TX_WADDR_V  0x000003FFU
+#define UART_APB_TX_WADDR_S  0
+/** UART_TX_RADDR : RO; bitpos: [20:11]; default: 0;
+ *  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
+ *  Tx-FIFO_Ctrl.
+ */
+#define UART_TX_RADDR    0x000003FFU
+#define UART_TX_RADDR_M  (UART_TX_RADDR_V << UART_TX_RADDR_S)
+#define UART_TX_RADDR_V  0x000003FFU
+#define UART_TX_RADDR_S  11
+
+/** UART_MEM_RX_STATUS_REG register
+ *  Rx-FIFO write and read offset address.
+ */
+#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68)
+/** UART_APB_RX_RADDR : RO; bitpos: [9:0]; default: 512;
+ *  This register stores the offset address in RX-FIFO when software reads data from
+ *  Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
+ */
+#define UART_APB_RX_RADDR    0x000003FFU
+#define UART_APB_RX_RADDR_M  (UART_APB_RX_RADDR_V << UART_APB_RX_RADDR_S)
+#define UART_APB_RX_RADDR_V  0x000003FFU
+#define UART_APB_RX_RADDR_S  0
+/** UART_RX_WADDR : RO; bitpos: [20:11]; default: 512;
+ *  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
+ *  Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
+ */
+#define UART_RX_WADDR    0x000003FFU
+#define UART_RX_WADDR_M  (UART_RX_WADDR_V << UART_RX_WADDR_S)
+#define UART_RX_WADDR_V  0x000003FFU
+#define UART_RX_WADDR_S  11
+
+/** UART_FSM_STATUS_REG register
+ *  UART transmit and receive status.
+ */
+#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c)
+/** UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0;
+ *  This is the status register of receiver.
+ */
+#define UART_ST_URX_OUT    0x0000000FU
+#define UART_ST_URX_OUT_M  (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S)
+#define UART_ST_URX_OUT_V  0x0000000FU
+#define UART_ST_URX_OUT_S  0
+/** UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0;
+ *  This is the status register of transmitter.
+ */
+#define UART_ST_UTX_OUT    0x0000000FU
+#define UART_ST_UTX_OUT_M  (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S)
+#define UART_ST_UTX_OUT_V  0x0000000FU
+#define UART_ST_UTX_OUT_S  4
+
+/** UART_POSPULSE_REG register
+ *  Autobaud high pulse register
+ */
+#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70)
+/** UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two positive edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_POSEDGE_MIN_CNT    0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_M  (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S)
+#define UART_POSEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_POSEDGE_MIN_CNT_S  0
+
+/** UART_NEGPULSE_REG register
+ *  Autobaud low pulse register
+ */
+#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74)
+/** UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
+ *  This register stores the minimal input clock count between two negative edges. It
+ *  is used in boudrate-detect process.
+ */
+#define UART_NEGEDGE_MIN_CNT    0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_M  (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S)
+#define UART_NEGEDGE_MIN_CNT_V  0x00000FFFU
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+/** UART_CLK_CONF_REG register
+ *  UART core clock configuration
+ */
+#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78)
+/** UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
+ *  The  denominator of the frequency divider factor.
+ */
+#define UART_SCLK_DIV_B    0x0000003FU
+#define UART_SCLK_DIV_B_M  (UART_SCLK_DIV_B_V << UART_SCLK_DIV_B_S)
+#define UART_SCLK_DIV_B_V  0x0000003FU
+#define UART_SCLK_DIV_B_S  0
+/** UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
+ *  The numerator of the frequency divider factor.
+ */
+#define UART_SCLK_DIV_A    0x0000003FU
+#define UART_SCLK_DIV_A_M  (UART_SCLK_DIV_A_V << UART_SCLK_DIV_A_S)
+#define UART_SCLK_DIV_A_V  0x0000003FU
+#define UART_SCLK_DIV_A_S  6
+/** UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
+ *  The integral part of the frequency divider factor.
+ */
+#define UART_SCLK_DIV_NUM    0x000000FFU
+#define UART_SCLK_DIV_NUM_M  (UART_SCLK_DIV_NUM_V << UART_SCLK_DIV_NUM_S)
+#define UART_SCLK_DIV_NUM_V  0x000000FFU
+#define UART_SCLK_DIV_NUM_S  12
+/** UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
+ *  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+ */
+#define UART_SCLK_SEL    0x00000003U
+#define UART_SCLK_SEL_M  (UART_SCLK_SEL_V << UART_SCLK_SEL_S)
+#define UART_SCLK_SEL_V  0x00000003U
+#define UART_SCLK_SEL_S  20
+/** UART_SCLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Set this bit to enable UART Tx/Rx clock.
+ */
+#define UART_SCLK_EN    (BIT(22))
+#define UART_SCLK_EN_M  (UART_SCLK_EN_V << UART_SCLK_EN_S)
+#define UART_SCLK_EN_V  0x00000001U
+#define UART_SCLK_EN_S  22
+/** UART_RST_CORE : R/W; bitpos: [23]; default: 0;
+ *  Write 1 then write 0 to this bit, reset UART Tx/Rx.
+ */
+#define UART_RST_CORE    (BIT(23))
+#define UART_RST_CORE_M  (UART_RST_CORE_V << UART_RST_CORE_S)
+#define UART_RST_CORE_V  0x00000001U
+#define UART_RST_CORE_S  23
+/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Set this bit to enable UART Tx clock.
+ */
+#define UART_TX_SCLK_EN    (BIT(24))
+#define UART_TX_SCLK_EN_M  (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
+#define UART_TX_SCLK_EN_V  0x00000001U
+#define UART_TX_SCLK_EN_S  24
+/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
+ *  Set this bit to enable UART Rx clock.
+ */
+#define UART_RX_SCLK_EN    (BIT(25))
+#define UART_RX_SCLK_EN_M  (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
+#define UART_RX_SCLK_EN_V  0x00000001U
+#define UART_RX_SCLK_EN_S  25
+/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
+ *  Write 1 then write 0 to this bit, reset UART Tx.
+ */
+#define UART_TX_RST_CORE    (BIT(26))
+#define UART_TX_RST_CORE_M  (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
+#define UART_TX_RST_CORE_V  0x00000001U
+#define UART_TX_RST_CORE_S  26
+/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
+ *  Write 1 then write 0 to this bit, reset UART Rx.
+ */
+#define UART_RX_RST_CORE    (BIT(27))
+#define UART_RX_RST_CORE_M  (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
+#define UART_RX_RST_CORE_V  0x00000001U
+#define UART_RX_RST_CORE_S  27
+
+/** UART_DATE_REG register
+ *  UART Version register
+ */
+#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c)
+/** UART_DATE : R/W; bitpos: [31:0]; default: 33587824;
+ *  This is the version register.
+ */
+#define UART_DATE    0xFFFFFFFFU
+#define UART_DATE_M  (UART_DATE_V << UART_DATE_S)
+#define UART_DATE_V  0xFFFFFFFFU
+#define UART_DATE_S  0
+
+/** UART_ID_REG register
+ *  UART ID register
+ */
+#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80)
+/** UART_ID : R/W; bitpos: [29:0]; default: 1280;
+ *  This register is used to configure the uart_id.
+ */
+#define UART_ID    0x3FFFFFFFU
+#define UART_ID_M  (UART_ID_V << UART_ID_S)
+#define UART_ID_V  0x3FFFFFFFU
+#define UART_ID_S  0
+/** UART_HIGH_SPEED : R/W; bitpos: [30]; default: 1;
+ *  This bit used to select synchronize mode. 1: Registers are auto synchronized into
+ *  UART Core clock and UART core should be keep the same with APB clock. 0: After
+ *  configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize
+ *  registers.
+ */
+#define UART_HIGH_SPEED    (BIT(30))
+#define UART_HIGH_SPEED_M  (UART_HIGH_SPEED_V << UART_HIGH_SPEED_S)
+#define UART_HIGH_SPEED_V  0x00000001U
+#define UART_HIGH_SPEED_S  30
+/** UART_REG_UPDATE : R/W/SC; bitpos: [31]; default: 0;
+ *  Software write 1 would synchronize registers into UART Core clock domain and would
+ *  be cleared by hardware after synchronization is done.
+ */
+#define UART_REG_UPDATE    (BIT(31))
+#define UART_REG_UPDATE_M  (UART_REG_UPDATE_V << UART_REG_UPDATE_S)
+#define UART_REG_UPDATE_V  0x00000001U
+#define UART_REG_UPDATE_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/uart_struct.h b/components/soc/esp32s3/register/soc/uart_struct.h
new file mode 100644
index 00000000000..a79a95dde57
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/uart_struct.h
@@ -0,0 +1,1204 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: FIFO Configuration */
+/** Type of fifo register
+ *  FIFO data register
+ */
+typedef union {
+    struct {
+        /** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
+         *  UART $n accesses FIFO via this register.
+         *  Must be a unit32_t not a bitfield as to avoid
+         *  a read->write operation during writing. Reading
+         *  during writing would impact RX fifo
+         */
+        uint32_t rxfifo_rd_byte;
+    };
+    uint32_t val;
+} uart_fifo_reg_t;
+
+/** Type of mem_conf register
+ *  UART threshold and allocation configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** rx_size : R/W; bitpos: [3:1]; default: 1;
+         *  This register is used to configure the amount of mem allocated for receive-FIFO.
+         *  The default number is 128 bytes.
+         */
+        uint32_t rx_size:3;
+        /** tx_size : R/W; bitpos: [6:4]; default: 1;
+         *  This register is used to configure the amount of mem allocated for transmit-FIFO.
+         *  The default number is 128 bytes.
+         */
+        uint32_t tx_size:3;
+        /** rx_flow_thrhd : R/W; bitpos: [16:7]; default: 0;
+         *  This register is used to configure the maximum amount of data that can be received
+         *  when hardware flow control works.
+         */
+        uint32_t rx_flow_thrhd:10;
+        /** rx_tout_thrhd : R/W; bitpos: [26:17]; default: 10;
+         *  This register is used to configure the threshold time that receiver takes to
+         *  receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver
+         *  takes more time to receive one byte with rx_tout_en set to 1.
+         */
+        uint32_t rx_tout_thrhd:10;
+        /** mem_force_pd : R/W; bitpos: [27]; default: 0;
+         *  Set this bit to force power down UART memory.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_force_pu : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to force power up UART memory.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} uart_mem_conf_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  what rxfifo_full_thrhd specifies.
+         */
+        uint32_t rxfifo_full_int_raw:1;
+        /** txfifo_empty_int_raw : R/WTC/SS; bitpos: [1]; default: 1;
+         *  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+         *  less than what txfifo_empty_thrhd specifies .
+         */
+        uint32_t txfifo_empty_int_raw:1;
+        /** parity_err_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error in
+         *  the data.
+         */
+        uint32_t parity_err_int_raw:1;
+        /** frm_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  .
+         */
+        uint32_t frm_err_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives more data than
+         *  the FIFO can store.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** dsr_chg_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  DSRn signal.
+         */
+        uint32_t dsr_chg_int_raw:1;
+        /** cts_chg_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the edge change of
+         *  CTSn signal.
+         */
+        uint32_t cts_chg_int_raw:1;
+        /** brk_det_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a 0 after the stop
+         *  bit.
+         */
+        uint32_t brk_det_int_raw:1;
+        /** rxfifo_tout_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver takes more time than
+         *  rx_tout_thrhd to receive a byte.
+         */
+        uint32_t rxfifo_tout_int_raw:1;
+        /** sw_xon_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xon char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xon_int_raw:1;
+        /** sw_xoff_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver receives Xoff char when
+         *  uart_sw_flow_con_en is set to 1.
+         */
+        uint32_t sw_xoff_int_raw:1;
+        /** glitch_det_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a glitch in the
+         *  middle of a start bit.
+         */
+        uint32_t glitch_det_int_raw:1;
+        /** tx_brk_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter completes  sending
+         *  NULL characters, after all data in Tx-FIFO are sent.
+         */
+        uint32_t tx_brk_done_int_raw:1;
+        /** tx_brk_idle_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has kept the shortest
+         *  duration after sending the  last data.
+         */
+        uint32_t tx_brk_idle_done_int_raw:1;
+        /** tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  This interrupt raw bit turns to high level when transmitter has send out all data
+         *  in FIFO.
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rs485_parity_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a parity error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_parity_err_int_raw:1;
+        /** rs485_frm_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects a data frame error
+         *  from the echo of transmitter in rs485 mode.
+         */
+        uint32_t rs485_frm_err_int_raw:1;
+        /** rs485_clash_int_raw : R/WTC/SS; bitpos: [17]; default: 0;
+         *  This interrupt raw bit turns to high level when detects a clash between transmitter
+         *  and receiver in rs485 mode.
+         */
+        uint32_t rs485_clash_int_raw:1;
+        /** at_cmd_char_det_int_raw : R/WTC/SS; bitpos: [18]; default: 0;
+         *  This interrupt raw bit turns to high level when receiver detects the configured
+         *  at_cmd char.
+         */
+        uint32_t at_cmd_char_det_int_raw:1;
+        /** wakeup_int_raw : R/WTC/SS; bitpos: [19]; default: 0;
+         *  This interrupt raw bit turns to high level when input rxd edge changes more times
+         *  than what reg_active_threshold specifies in light sleeping mode.
+         */
+        uint32_t wakeup_int_raw:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+         */
+        uint32_t rxfifo_full_int_st:1;
+        /** txfifo_empty_int_st : RO; bitpos: [1]; default: 0;
+         *  This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set
+         *  to 1.
+         */
+        uint32_t txfifo_empty_int_st:1;
+        /** parity_err_int_st : RO; bitpos: [2]; default: 0;
+         *  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+         */
+        uint32_t parity_err_int_st:1;
+        /** frm_err_int_st : RO; bitpos: [3]; default: 0;
+         *  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+         */
+        uint32_t frm_err_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** dsr_chg_int_st : RO; bitpos: [5]; default: 0;
+         *  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+         */
+        uint32_t dsr_chg_int_st:1;
+        /** cts_chg_int_st : RO; bitpos: [6]; default: 0;
+         *  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+         */
+        uint32_t cts_chg_int_st:1;
+        /** brk_det_int_st : RO; bitpos: [7]; default: 0;
+         *  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+         */
+        uint32_t brk_det_int_st:1;
+        /** rxfifo_tout_int_st : RO; bitpos: [8]; default: 0;
+         *  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+         */
+        uint32_t rxfifo_tout_int_st:1;
+        /** sw_xon_int_st : RO; bitpos: [9]; default: 0;
+         *  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+         */
+        uint32_t sw_xon_int_st:1;
+        /** sw_xoff_int_st : RO; bitpos: [10]; default: 0;
+         *  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+         */
+        uint32_t sw_xoff_int_st:1;
+        /** glitch_det_int_st : RO; bitpos: [11]; default: 0;
+         *  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+         */
+        uint32_t glitch_det_int_st:1;
+        /** tx_brk_done_int_st : RO; bitpos: [12]; default: 0;
+         *  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+         */
+        uint32_t tx_brk_done_int_st:1;
+        /** tx_brk_idle_done_int_st : RO; bitpos: [13]; default: 0;
+         *  This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena
+         *  is set to 1.
+         */
+        uint32_t tx_brk_idle_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [14]; default: 0;
+         *  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+         */
+        uint32_t tx_done_int_st:1;
+        /** rs485_parity_err_int_st : RO; bitpos: [15]; default: 0;
+         *  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+         *  set to 1.
+         */
+        uint32_t rs485_parity_err_int_st:1;
+        /** rs485_frm_err_int_st : RO; bitpos: [16]; default: 0;
+         *  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set
+         *  to 1.
+         */
+        uint32_t rs485_frm_err_int_st:1;
+        /** rs485_clash_int_st : RO; bitpos: [17]; default: 0;
+         *  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+         */
+        uint32_t rs485_clash_int_st:1;
+        /** at_cmd_char_det_int_st : RO; bitpos: [18]; default: 0;
+         *  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set
+         *  to 1.
+         */
+        uint32_t at_cmd_char_det_int_st:1;
+        /** wakeup_int_st : RO; bitpos: [19]; default: 0;
+         *  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+         */
+        uint32_t wakeup_int_st:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for rxfifo_full_int_st register.
+         */
+        uint32_t rxfifo_full_int_ena:1;
+        /** txfifo_empty_int_ena : R/W; bitpos: [1]; default: 0;
+         *  This is the enable bit for txfifo_empty_int_st register.
+         */
+        uint32_t txfifo_empty_int_ena:1;
+        /** parity_err_int_ena : R/W; bitpos: [2]; default: 0;
+         *  This is the enable bit for parity_err_int_st register.
+         */
+        uint32_t parity_err_int_ena:1;
+        /** frm_err_int_ena : R/W; bitpos: [3]; default: 0;
+         *  This is the enable bit for frm_err_int_st register.
+         */
+        uint32_t frm_err_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  This is the enable bit for rxfifo_ovf_int_st register.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** dsr_chg_int_ena : R/W; bitpos: [5]; default: 0;
+         *  This is the enable bit for dsr_chg_int_st register.
+         */
+        uint32_t dsr_chg_int_ena:1;
+        /** cts_chg_int_ena : R/W; bitpos: [6]; default: 0;
+         *  This is the enable bit for cts_chg_int_st register.
+         */
+        uint32_t cts_chg_int_ena:1;
+        /** brk_det_int_ena : R/W; bitpos: [7]; default: 0;
+         *  This is the enable bit for brk_det_int_st register.
+         */
+        uint32_t brk_det_int_ena:1;
+        /** rxfifo_tout_int_ena : R/W; bitpos: [8]; default: 0;
+         *  This is the enable bit for rxfifo_tout_int_st register.
+         */
+        uint32_t rxfifo_tout_int_ena:1;
+        /** sw_xon_int_ena : R/W; bitpos: [9]; default: 0;
+         *  This is the enable bit for sw_xon_int_st register.
+         */
+        uint32_t sw_xon_int_ena:1;
+        /** sw_xoff_int_ena : R/W; bitpos: [10]; default: 0;
+         *  This is the enable bit for sw_xoff_int_st register.
+         */
+        uint32_t sw_xoff_int_ena:1;
+        /** glitch_det_int_ena : R/W; bitpos: [11]; default: 0;
+         *  This is the enable bit for glitch_det_int_st register.
+         */
+        uint32_t glitch_det_int_ena:1;
+        /** tx_brk_done_int_ena : R/W; bitpos: [12]; default: 0;
+         *  This is the enable bit for tx_brk_done_int_st register.
+         */
+        uint32_t tx_brk_done_int_ena:1;
+        /** tx_brk_idle_done_int_ena : R/W; bitpos: [13]; default: 0;
+         *  This is the enable bit for tx_brk_idle_done_int_st register.
+         */
+        uint32_t tx_brk_idle_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [14]; default: 0;
+         *  This is the enable bit for tx_done_int_st register.
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rs485_parity_err_int_ena : R/W; bitpos: [15]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_parity_err_int_ena:1;
+        /** rs485_frm_err_int_ena : R/W; bitpos: [16]; default: 0;
+         *  This is the enable bit for rs485_parity_err_int_st register.
+         */
+        uint32_t rs485_frm_err_int_ena:1;
+        /** rs485_clash_int_ena : R/W; bitpos: [17]; default: 0;
+         *  This is the enable bit for rs485_clash_int_st register.
+         */
+        uint32_t rs485_clash_int_ena:1;
+        /** at_cmd_char_det_int_ena : R/W; bitpos: [18]; default: 0;
+         *  This is the enable bit for at_cmd_char_det_int_st register.
+         */
+        uint32_t at_cmd_char_det_int_ena:1;
+        /** wakeup_int_ena : R/W; bitpos: [19]; default: 0;
+         *  This is the enable bit for uart_wakeup_int_st register.
+         */
+        uint32_t wakeup_int_ena:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the rxfifo_full_int_raw interrupt.
+         */
+        uint32_t rxfifo_full_int_clr:1;
+        /** txfifo_empty_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear txfifo_empty_int_raw interrupt.
+         */
+        uint32_t txfifo_empty_int_clr:1;
+        /** parity_err_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear parity_err_int_raw interrupt.
+         */
+        uint32_t parity_err_int_clr:1;
+        /** frm_err_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear frm_err_int_raw interrupt.
+         */
+        uint32_t frm_err_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** dsr_chg_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the dsr_chg_int_raw interrupt.
+         */
+        uint32_t dsr_chg_int_clr:1;
+        /** cts_chg_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the cts_chg_int_raw interrupt.
+         */
+        uint32_t cts_chg_int_clr:1;
+        /** brk_det_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the brk_det_int_raw interrupt.
+         */
+        uint32_t brk_det_int_clr:1;
+        /** rxfifo_tout_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+         */
+        uint32_t rxfifo_tout_int_clr:1;
+        /** sw_xon_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the sw_xon_int_raw interrupt.
+         */
+        uint32_t sw_xon_int_clr:1;
+        /** sw_xoff_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the sw_xoff_int_raw interrupt.
+         */
+        uint32_t sw_xoff_int_clr:1;
+        /** glitch_det_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the glitch_det_int_raw interrupt.
+         */
+        uint32_t glitch_det_int_clr:1;
+        /** tx_brk_done_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the tx_brk_done_int_raw interrupt..
+         */
+        uint32_t tx_brk_done_int_clr:1;
+        /** tx_brk_idle_done_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+         */
+        uint32_t tx_brk_idle_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [14]; default: 0;
+         *  Set this bit to clear the tx_done_int_raw interrupt.
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rs485_parity_err_int_clr : WT; bitpos: [15]; default: 0;
+         *  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+         */
+        uint32_t rs485_parity_err_int_clr:1;
+        /** rs485_frm_err_int_clr : WT; bitpos: [16]; default: 0;
+         *  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+         */
+        uint32_t rs485_frm_err_int_clr:1;
+        /** rs485_clash_int_clr : WT; bitpos: [17]; default: 0;
+         *  Set this bit to clear the rs485_clash_int_raw interrupt.
+         */
+        uint32_t rs485_clash_int_clr:1;
+        /** at_cmd_char_det_int_clr : WT; bitpos: [18]; default: 0;
+         *  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+         */
+        uint32_t at_cmd_char_det_int_clr:1;
+        /** wakeup_int_clr : WT; bitpos: [19]; default: 0;
+         *  Set this bit to clear the uart_wakeup_int_raw interrupt.
+         */
+        uint32_t wakeup_int_clr:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_int_clr_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of clkdiv register
+ *  Clock divider configuration
+ */
+typedef union {
+    struct {
+        /** clkdiv : R/W; bitpos: [11:0]; default: 694;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t clkdiv:12;
+        uint32_t reserved_12:8;
+        /** clkdiv_frag : R/W; bitpos: [23:20]; default: 0;
+         *  The decimal part of the frequency divider factor.
+         */
+        uint32_t clkdiv_frag:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_clkdiv_reg_t;
+
+/** Type of rx_filt register
+ *  Rx Filter configuration
+ */
+typedef union {
+    struct {
+        /** glitch_filt : R/W; bitpos: [7:0]; default: 8;
+         *  when input pulse width is lower than this value, the pulse is ignored.
+         */
+        uint32_t glitch_filt:8;
+        /** glitch_filt_en : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable Rx signal filter.
+         */
+        uint32_t glitch_filt_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} uart_rx_filt_reg_t;
+
+/** Type of conf0 register
+ *  a
+ */
+typedef union {
+    struct {
+        /** parity : R/W; bitpos: [0]; default: 0;
+         *  This register is used to configure the parity check mode.
+         */
+        uint32_t parity:1;
+        /** parity_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to enable uart parity check.
+         */
+        uint32_t parity_en:1;
+        /** bit_num : R/W; bitpos: [3:2]; default: 3;
+         *  This register is used to set the length of data.
+         */
+        uint32_t bit_num:2;
+        /** stop_bit_num : R/W; bitpos: [5:4]; default: 1;
+         *  This register is used to set the length of  stop bit.
+         */
+        uint32_t stop_bit_num:2;
+        /** sw_rts : R/W; bitpos: [6]; default: 0;
+         *  This register is used to configure the software rts signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_rts:1;
+        /** sw_dtr : R/W; bitpos: [7]; default: 0;
+         *  This register is used to configure the software dtr signal which is used in
+         *  software flow control.
+         */
+        uint32_t sw_dtr:1;
+        /** txd_brk : R/W; bitpos: [8]; default: 0;
+         *  Set this bit to enable transmitter to  send NULL when the process of sending data
+         *  is done.
+         */
+        uint32_t txd_brk:1;
+        /** irda_dplx : R/W; bitpos: [9]; default: 0;
+         *  Set this bit to enable IrDA loopback mode.
+         */
+        uint32_t irda_dplx:1;
+        /** irda_tx_en : R/W; bitpos: [10]; default: 0;
+         *  This is the start enable bit for IrDA transmitter.
+         */
+        uint32_t irda_tx_en:1;
+        /** irda_wctl : R/W; bitpos: [11]; default: 0;
+         *  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+         *  transmitter's 11th bit to 0.
+         */
+        uint32_t irda_wctl:1;
+        /** irda_tx_inv : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to invert the level of  IrDA transmitter.
+         */
+        uint32_t irda_tx_inv:1;
+        /** irda_rx_inv : R/W; bitpos: [13]; default: 0;
+         *  Set this bit to invert the level of IrDA receiver.
+         */
+        uint32_t irda_rx_inv:1;
+        /** loopback : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to enable uart loopback test mode.
+         */
+        uint32_t loopback:1;
+        /** tx_flow_en : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to enable flow control function for transmitter.
+         */
+        uint32_t tx_flow_en:1;
+        /** irda_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit to enable IrDA protocol.
+         */
+        uint32_t irda_en:1;
+        /** rxfifo_rst : R/W; bitpos: [17]; default: 0;
+         *  Set this bit to reset the uart receive-FIFO.
+         */
+        uint32_t rxfifo_rst:1;
+        /** txfifo_rst : R/W; bitpos: [18]; default: 0;
+         *  Set this bit to reset the uart transmit-FIFO.
+         */
+        uint32_t txfifo_rst:1;
+        /** rxd_inv : R/W; bitpos: [19]; default: 0;
+         *  Set this bit to inverse the level value of uart rxd signal.
+         */
+        uint32_t rxd_inv:1;
+        /** cts_inv : R/W; bitpos: [20]; default: 0;
+         *  Set this bit to inverse the level value of uart cts signal.
+         */
+        uint32_t cts_inv:1;
+        /** dsr_inv : R/W; bitpos: [21]; default: 0;
+         *  Set this bit to inverse the level value of uart dsr signal.
+         */
+        uint32_t dsr_inv:1;
+        /** txd_inv : R/W; bitpos: [22]; default: 0;
+         *  Set this bit to inverse the level value of uart txd signal.
+         */
+        uint32_t txd_inv:1;
+        /** rts_inv : R/W; bitpos: [23]; default: 0;
+         *  Set this bit to inverse the level value of uart rts signal.
+         */
+        uint32_t rts_inv:1;
+        /** dtr_inv : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to inverse the level value of uart dtr signal.
+         */
+        uint32_t dtr_inv:1;
+        /** clk_en : R/W; bitpos: [25]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        /** err_wr_mask : R/W; bitpos: [26]; default: 0;
+         *  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+         *  stores the data even if the  received data is wrong.
+         */
+        uint32_t err_wr_mask:1;
+        /** autobaud_en : R/W; bitpos: [27]; default: 0;
+         *  This is the enable bit for detecting baudrate.
+         */
+        uint32_t autobaud_en:1;
+        /** mem_clk_en : R/W; bitpos: [28]; default: 1;
+         *  UART memory clock gate enable signal.
+         */
+        uint32_t mem_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} uart_conf0_reg_t;
+
+/** Type of conf1 register
+ *  Configuration register 1
+ */
+typedef union {
+    struct {
+        /** rxfifo_full_thrhd : R/W; bitpos: [9:0]; default: 96;
+         *  It will produce rxfifo_full_int interrupt when receiver receives more data than
+         *  this register value.
+         */
+        uint32_t rxfifo_full_thrhd:10;
+        /** txfifo_empty_thrhd : R/W; bitpos: [19:10]; default: 96;
+         *  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less
+         *  than this register value.
+         */
+        uint32_t txfifo_empty_thrhd:10;
+        /** dis_rx_dat_ovf : R/W; bitpos: [20]; default: 0;
+         *  Disable UART Rx data overflow detect.
+         */
+        uint32_t dis_rx_dat_ovf:1;
+        /** rx_tout_flow_dis : R/W; bitpos: [21]; default: 0;
+         *  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+         */
+        uint32_t rx_tout_flow_dis:1;
+        /** rx_flow_en : R/W; bitpos: [22]; default: 0;
+         *  This is the flow enable bit for UART receiver.
+         */
+        uint32_t rx_flow_en:1;
+        /** rx_tout_en : R/W; bitpos: [23]; default: 0;
+         *  This is the enable bit for uart receiver's timeout function.
+         */
+        uint32_t rx_tout_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} uart_conf1_reg_t;
+
+/** Type of flow_conf register
+ *  Software flow-control configuration
+ */
+typedef union {
+    struct {
+        /** sw_flow_con_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable software flow control. It is used with register sw_xon or
+         *  sw_xoff.
+         */
+        uint32_t sw_flow_con_en:1;
+        /** xonoff_del : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to remove flow control char from the received data.
+         */
+        uint32_t xonoff_del:1;
+        /** force_xon : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable the transmitter to go on sending data.
+         */
+        uint32_t force_xon:1;
+        /** force_xoff : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to stop the  transmitter from sending data.
+         */
+        uint32_t force_xoff:1;
+        /** send_xon : R/W/SS/SC; bitpos: [4]; default: 0;
+         *  Set this bit to send Xon char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xon:1;
+        /** send_xoff : R/W/SS/SC; bitpos: [5]; default: 0;
+         *  Set this bit to send Xoff char. It is cleared by hardware automatically.
+         */
+        uint32_t send_xoff:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} uart_flow_conf_reg_t;
+
+/** Type of sleep_conf register
+ *  Sleep-mode configuration
+ */
+typedef union {
+    struct {
+        /** active_threshold : R/W; bitpos: [9:0]; default: 240;
+         *  The uart is activated from light sleeping mode when the input rxd edge changes more
+         *  times than this register value.
+         */
+        uint32_t active_threshold:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_sleep_conf_reg_t;
+
+/** Type of swfc_conf0 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xoff_threshold : R/W; bitpos: [9:0]; default: 224;
+         *  When the data amount in Rx-FIFO is more than this register value with
+         *  uart_sw_flow_con_en set to 1, it will send a Xoff char.
+         */
+        uint32_t xoff_threshold:10;
+        /** xoff_character : R/W; bitpos: [17:10]; default: 19;
+         *  This register stores the Xoff flow control char.
+         */
+        uint32_t xoff_character:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} uart_swfc_conf0_reg_t;
+
+/** Type of swfc_conf1 register
+ *  Software flow-control character configuration
+ */
+typedef union {
+    struct {
+        /** xon_threshold : R/W; bitpos: [9:0]; default: 0;
+         *  When the data amount in Rx-FIFO is less than this register value with
+         *  uart_sw_flow_con_en set to 1, it will send a Xon char.
+         */
+        uint32_t xon_threshold:10;
+        /** xon_character : R/W; bitpos: [17:10]; default: 17;
+         *  This register stores the Xon flow control char.
+         */
+        uint32_t xon_character:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} uart_swfc_conf1_reg_t;
+
+/** Type of txbrk_conf register
+ *  Tx Break character configuration
+ */
+typedef union {
+    struct {
+        /** tx_brk_num : R/W; bitpos: [7:0]; default: 10;
+         *  This register is used to configure the number of 0 to be sent after the process of
+         *  sending data is done. It is active when txd_brk is set to 1.
+         */
+        uint32_t tx_brk_num:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_txbrk_conf_reg_t;
+
+/** Type of idle_conf register
+ *  Frame-end idle configuration
+ */
+typedef union {
+    struct {
+        /** rx_idle_thrhd : R/W; bitpos: [9:0]; default: 256;
+         *  It will produce frame end signal when receiver takes more time to receive one byte
+         *  data than this register value.
+         */
+        uint32_t rx_idle_thrhd:10;
+        /** tx_idle_num : R/W; bitpos: [19:10]; default: 256;
+         *  This register is used to configure the duration time between transfers.
+         */
+        uint32_t tx_idle_num:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} uart_idle_conf_reg_t;
+
+/** Type of rs485_conf register
+ *  RS485 mode configuration
+ */
+typedef union {
+    struct {
+        /** rs485_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to choose the rs485 mode.
+         */
+        uint32_t rs485_en:1;
+        /** dl0_en : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl0_en:1;
+        /** dl1_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to delay the stop bit by 1 bit.
+         */
+        uint32_t dl1_en:1;
+        /** rs485tx_rx_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable receiver could receive data when the transmitter is
+         *  transmitting data in rs485 mode.
+         */
+        uint32_t rs485tx_rx_en:1;
+        /** rs485rxby_tx_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+         */
+        uint32_t rs485rxby_tx_en:1;
+        /** rs485_rx_dly_num : R/W; bitpos: [5]; default: 0;
+         *  This register is used to delay the receiver's internal data signal.
+         */
+        uint32_t rs485_rx_dly_num:1;
+        /** rs485_tx_dly_num : R/W; bitpos: [9:6]; default: 0;
+         *  This register is used to delay the transmitter's internal data signal.
+         */
+        uint32_t rs485_tx_dly_num:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rs485_conf_reg_t;
+
+/** Type of clk_conf register
+ *  UART core clock configuration
+ */
+typedef union {
+    struct {
+        /** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
+         *  The  denominator of the frequency divider factor.
+         */
+        uint32_t sclk_div_b:6;
+        /** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
+         *  The numerator of the frequency divider factor.
+         */
+        uint32_t sclk_div_a:6;
+        /** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
+         *  The integral part of the frequency divider factor.
+         */
+        uint32_t sclk_div_num:8;
+        /** sclk_sel : R/W; bitpos: [21:20]; default: 3;
+         *  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+         */
+        uint32_t sclk_sel:2;
+        /** sclk_en : R/W; bitpos: [22]; default: 1;
+         *  Set this bit to enable UART Tx/Rx clock.
+         */
+        uint32_t sclk_en:1;
+        /** rst_core : R/W; bitpos: [23]; default: 0;
+         *  Write 1 then write 0 to this bit, reset UART Tx/Rx.
+         */
+        uint32_t rst_core:1;
+        /** tx_sclk_en : R/W; bitpos: [24]; default: 1;
+         *  Set this bit to enable UART Tx clock.
+         */
+        uint32_t tx_sclk_en:1;
+        /** rx_sclk_en : R/W; bitpos: [25]; default: 1;
+         *  Set this bit to enable UART Rx clock.
+         */
+        uint32_t rx_sclk_en:1;
+        /** tx_rst_core : R/W; bitpos: [26]; default: 0;
+         *  Write 1 then write 0 to this bit, reset UART Tx.
+         */
+        uint32_t tx_rst_core:1;
+        /** rx_rst_core : R/W; bitpos: [27]; default: 0;
+         *  Write 1 then write 0 to this bit, reset UART Rx.
+         */
+        uint32_t rx_rst_core:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} uart_clk_conf_reg_t;
+
+
+/** Group: Status Register */
+/** Type of status register
+ *  UART status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_cnt : RO; bitpos: [9:0]; default: 0;
+         *  Stores the byte number of valid data in Rx-FIFO.
+         */
+        uint32_t rxfifo_cnt:10;
+        uint32_t reserved_10:3;
+        /** dsrn : RO; bitpos: [13]; default: 0;
+         *  The register represent the level value of the internal uart dsr signal.
+         */
+        uint32_t dsrn:1;
+        /** ctsn : RO; bitpos: [14]; default: 1;
+         *  This register represent the level value of the internal uart cts signal.
+         */
+        uint32_t ctsn:1;
+        /** rxd : RO; bitpos: [15]; default: 1;
+         *  This register represent the  level value of the internal uart rxd signal.
+         */
+        uint32_t rxd:1;
+        /** txfifo_cnt : RO; bitpos: [25:16]; default: 0;
+         *  Stores the byte number of data in Tx-FIFO.
+         */
+        uint32_t txfifo_cnt:10;
+        uint32_t reserved_26:3;
+        /** dtrn : RO; bitpos: [29]; default: 1;
+         *  This bit represents the level of the internal uart dtr signal.
+         */
+        uint32_t dtrn:1;
+        /** rtsn : RO; bitpos: [30]; default: 1;
+         *  This bit represents the level of the internal uart rts signal.
+         */
+        uint32_t rtsn:1;
+        /** txd : RO; bitpos: [31]; default: 1;
+         *  This bit represents the  level of the internal uart txd signal.
+         */
+        uint32_t txd:1;
+    };
+    uint32_t val;
+} uart_status_reg_t;
+
+/** Type of mem_tx_status register
+ *  Tx-FIFO write and read offset address.
+ */
+typedef union {
+    struct {
+        /** apb_tx_waddr : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via
+         *  APB.
+         */
+        uint32_t apb_tx_waddr:10;
+        uint32_t reserved_10:1;
+        /** tx_raddr : RO; bitpos: [20:11]; default: 0;
+         *  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
+         *  Tx-FIFO_Ctrl.
+         */
+        uint32_t tx_raddr:10;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} uart_mem_tx_status_reg_t;
+
+/** Type of mem_rx_status register
+ *  Rx-FIFO write and read offset address.
+ */
+typedef union {
+    struct {
+        /** apb_rx_raddr : RO; bitpos: [9:0]; default: 512;
+         *  This register stores the offset address in RX-FIFO when software reads data from
+         *  Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
+         */
+        uint32_t apb_rx_raddr:10;
+        uint32_t reserved_10:1;
+        /** rx_waddr : RO; bitpos: [20:11]; default: 512;
+         *  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
+         *  Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300.
+         */
+        uint32_t rx_waddr:10;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} uart_mem_rx_status_reg_t;
+
+/** Type of fsm_status register
+ *  UART transmit and receive status.
+ */
+typedef union {
+    struct {
+        /** st_urx_out : RO; bitpos: [3:0]; default: 0;
+         *  This is the status register of receiver.
+         */
+        uint32_t st_urx_out:4;
+        /** st_utx_out : RO; bitpos: [7:4]; default: 0;
+         *  This is the status register of transmitter.
+         */
+        uint32_t st_utx_out:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} uart_fsm_status_reg_t;
+
+
+/** Group: Autobaud Register */
+/** Type of lowpulse register
+ *  Autobaud minimum low pulse duration register
+ */
+typedef union {
+    struct {
+        /** lowpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the value of the minimum duration time of the low level pulse.
+         *  It is used in baud rate-detect process.
+         */
+        uint32_t lowpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_lowpulse_reg_t;
+
+/** Type of highpulse register
+ *  Autobaud minimum high pulse duration register
+ */
+typedef union {
+    struct {
+        /** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores  the value of the maximum duration time for the high level
+         *  pulse. It is used in baud rate-detect process.
+         */
+        uint32_t highpulse_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_highpulse_reg_t;
+
+/** Type of rxd_cnt register
+ *  Autobaud edge change count register
+ */
+typedef union {
+    struct {
+        /** rxd_edge_cnt : RO; bitpos: [9:0]; default: 0;
+         *  This register stores the count of rxd edge change. It is used in baud rate-detect
+         *  process.
+         */
+        uint32_t rxd_edge_cnt:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} uart_rxd_cnt_reg_t;
+
+/** Type of pospulse register
+ *  Autobaud high pulse register
+ */
+typedef union {
+    struct {
+        /** posedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two positive edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t posedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_pospulse_reg_t;
+
+/** Type of negpulse register
+ *  Autobaud low pulse register
+ */
+typedef union {
+    struct {
+        /** negedge_min_cnt : RO; bitpos: [11:0]; default: 4095;
+         *  This register stores the minimal input clock count between two negative edges. It
+         *  is used in boudrate-detect process.
+         */
+        uint32_t negedge_min_cnt:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} uart_negpulse_reg_t;
+
+
+/** Group: AT Escape Sequence Selection Configuration */
+/** Type of at_cmd_precnt register
+ *  Pre-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** pre_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the idle duration time before the first at_cmd
+         *  is received by receiver.
+         */
+        uint32_t pre_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_precnt_reg_t;
+
+/** Type of at_cmd_postcnt register
+ *  Post-sequence timing configuration
+ */
+typedef union {
+    struct {
+        /** post_idle_num : R/W; bitpos: [15:0]; default: 2305;
+         *  This register is used to configure the duration time between the last at_cmd and
+         *  the next data.
+         */
+        uint32_t post_idle_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_postcnt_reg_t;
+
+/** Type of at_cmd_gaptout register
+ *  Timeout configuration
+ */
+typedef union {
+    struct {
+        /** rx_gap_tout : R/W; bitpos: [15:0]; default: 11;
+         *  This register is used to configure the duration time between the at_cmd chars.
+         */
+        uint32_t rx_gap_tout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_gaptout_reg_t;
+
+/** Type of at_cmd_char register
+ *  AT escape sequence detection configuration
+ */
+typedef union {
+    struct {
+        /** data : R/W; bitpos: [7:0]; default: 43;
+         *  This register is used to configure the content of at_cmd char.
+         */
+        uint32_t data:8;
+        /** at_char_num : R/W; bitpos: [15:8]; default: 3;
+         *  This register is used to configure the num of continuous at_cmd chars received by
+         *  receiver.
+         */
+        uint32_t at_char_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} uart_at_cmd_char_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  UART Version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 33587824;
+         *  This is the version register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} uart_date_reg_t;
+
+/** Type of id register
+ *  UART ID register
+ */
+typedef union {
+    struct {
+        /** id : R/W; bitpos: [29:0]; default: 1280;
+         *  This register is used to configure the uart_id.
+         */
+        uint32_t id:30;
+        /** high_speed : R/W; bitpos: [30]; default: 1;
+         *  This bit used to select synchronize mode. 1: Registers are auto synchronized into
+         *  UART Core clock and UART core should be keep the same with APB clock. 0: After
+         *  configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize
+         *  registers.
+         */
+        uint32_t high_speed:1;
+        /** reg_update : R/W/SC; bitpos: [31]; default: 0;
+         *  Software write 1 would synchronize registers into UART Core clock domain and would
+         *  be cleared by hardware after synchronization is done.
+         */
+        uint32_t reg_update:1;
+    };
+    uint32_t val;
+} uart_id_reg_t;
+
+
+typedef struct {
+    volatile uart_fifo_reg_t fifo;
+    volatile uart_int_raw_reg_t int_raw;
+    volatile uart_int_st_reg_t int_st;
+    volatile uart_int_ena_reg_t int_ena;
+    volatile uart_int_clr_reg_t int_clr;
+    volatile uart_clkdiv_reg_t clkdiv;
+    volatile uart_rx_filt_reg_t rx_filt;
+    volatile uart_status_reg_t status;
+    volatile uart_conf0_reg_t conf0;
+    volatile uart_conf1_reg_t conf1;
+    volatile uart_lowpulse_reg_t lowpulse;
+    volatile uart_highpulse_reg_t highpulse;
+    volatile uart_rxd_cnt_reg_t rxd_cnt;
+    volatile uart_flow_conf_reg_t flow_conf;
+    volatile uart_sleep_conf_reg_t sleep_conf;
+    volatile uart_swfc_conf0_reg_t swfc_conf0;
+    volatile uart_swfc_conf1_reg_t swfc_conf1;
+    volatile uart_txbrk_conf_reg_t txbrk_conf;
+    volatile uart_idle_conf_reg_t idle_conf;
+    volatile uart_rs485_conf_reg_t rs485_conf;
+    volatile uart_at_cmd_precnt_reg_t at_cmd_precnt;
+    volatile uart_at_cmd_postcnt_reg_t at_cmd_postcnt;
+    volatile uart_at_cmd_gaptout_reg_t at_cmd_gaptout;
+    volatile uart_at_cmd_char_reg_t at_cmd_char;
+    volatile uart_mem_conf_reg_t mem_conf;
+    volatile uart_mem_tx_status_reg_t mem_tx_status;
+    volatile uart_mem_rx_status_reg_t mem_rx_status;
+    volatile uart_fsm_status_reg_t fsm_status;
+    volatile uart_pospulse_reg_t pospulse;
+    volatile uart_negpulse_reg_t negpulse;
+    volatile uart_clk_conf_reg_t clk_conf;
+    volatile uart_date_reg_t date;
+    volatile uart_id_reg_t id;
+} uart_dev_t;
+
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+extern uart_dev_t UART2;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(uart_dev_t) == 0x84, "Invalid size of uart_dev_t structure");
+_Static_assert(sizeof(UART0.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
+_Static_assert(sizeof(UART1.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
+_Static_assert(sizeof(UART2.fifo.rxfifo_rd_byte) == 4, "FIFO, must be a uint32_t, not bitfield!");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/uhci_reg.h b/components/soc/esp32s3/register/soc/uhci_reg.h
new file mode 100644
index 00000000000..19fefc9f35e
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/uhci_reg.h
@@ -0,0 +1,756 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_UHCI_REG_H_
+#define _SOC_UHCI_REG_H_
+
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
+/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_UART_RX_BRK_EOF_EN    (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_M  (BIT(12))
+#define UHCI_UART_RX_BRK_EOF_EN_V  0x1
+#define UHCI_UART_RX_BRK_EOF_EN_S  12
+/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_CLK_EN    (BIT(11))
+#define UHCI_CLK_EN_M  (BIT(11))
+#define UHCI_CLK_EN_V  0x1
+#define UHCI_CLK_EN_S  11
+/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_ENCODE_CRC_EN    (BIT(10))
+#define UHCI_ENCODE_CRC_EN_M  (BIT(10))
+#define UHCI_ENCODE_CRC_EN_V  0x1
+#define UHCI_ENCODE_CRC_EN_S  10
+/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_LEN_EOF_EN    (BIT(9))
+#define UHCI_LEN_EOF_EN_M  (BIT(9))
+#define UHCI_LEN_EOF_EN_V  0x1
+#define UHCI_LEN_EOF_EN_S  9
+/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_UART_IDLE_EOF_EN    (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_M  (BIT(8))
+#define UHCI_UART_IDLE_EOF_EN_V  0x1
+#define UHCI_UART_IDLE_EOF_EN_S  8
+/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_CRC_REC_EN    (BIT(7))
+#define UHCI_CRC_REC_EN_M  (BIT(7))
+#define UHCI_CRC_REC_EN_V  0x1
+#define UHCI_CRC_REC_EN_S  7
+/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_HEAD_EN    (BIT(6))
+#define UHCI_HEAD_EN_M  (BIT(6))
+#define UHCI_HEAD_EN_V  0x1
+#define UHCI_HEAD_EN_S  6
+/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_SEPER_EN    (BIT(5))
+#define UHCI_SEPER_EN_M  (BIT(5))
+#define UHCI_SEPER_EN_V  0x1
+#define UHCI_SEPER_EN_S  5
+/* UHCI_UART2_CE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_UART2_CE    (BIT(4))
+#define UHCI_UART2_CE_M  (BIT(4))
+#define UHCI_UART2_CE_V  0x1
+#define UHCI_UART2_CE_S  4
+/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_UART1_CE    (BIT(3))
+#define UHCI_UART1_CE_M  (BIT(3))
+#define UHCI_UART1_CE_V  0x1
+#define UHCI_UART1_CE_S  3
+/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: .*/
+#define UHCI_UART0_CE    (BIT(2))
+#define UHCI_UART0_CE_M  (BIT(2))
+#define UHCI_UART0_CE_V  0x1
+#define UHCI_UART0_CE_S  2
+/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_RST    (BIT(1))
+#define UHCI_RX_RST_M  (BIT(1))
+#define UHCI_RX_RST_V  0x1
+#define UHCI_RX_RST_S  1
+/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: .*/
+#define UHCI_TX_RST    (BIT(0))
+#define UHCI_TX_RST_M  (BIT(0))
+#define UHCI_TX_RST_V  0x1
+#define UHCI_TX_RST_S  0
+
+#define UHCI_INT_RAW_REG(i)          (REG_UHCI_BASE(i) + 0x4)
+/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL1_INT_RAW    (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_RAW_V  0x1
+#define UHCI_APP_CTRL1_INT_RAW_S  8
+/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL0_INT_RAW    (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_RAW_V  0x1
+#define UHCI_APP_CTRL0_INT_RAW_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S  6
+/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SEND_A_Q_INT_RAW    (BIT(5))
+#define UHCI_SEND_A_Q_INT_RAW_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_RAW_V  0x1
+#define UHCI_SEND_A_Q_INT_RAW_S  5
+/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SEND_S_Q_INT_RAW    (BIT(4))
+#define UHCI_SEND_S_Q_INT_RAW_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_RAW_V  0x1
+#define UHCI_SEND_S_Q_INT_RAW_S  4
+/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_HUNG_INT_RAW    (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_V  0x1
+#define UHCI_TX_HUNG_INT_RAW_S  3
+/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_HUNG_INT_RAW    (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_V  0x1
+#define UHCI_RX_HUNG_INT_RAW_S  2
+/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_START_INT_RAW    (BIT(1))
+#define UHCI_TX_START_INT_RAW_M  (BIT(1))
+#define UHCI_TX_START_INT_RAW_V  0x1
+#define UHCI_TX_START_INT_RAW_S  1
+/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_START_INT_RAW    (BIT(0))
+#define UHCI_RX_START_INT_RAW_M  (BIT(0))
+#define UHCI_RX_START_INT_RAW_V  0x1
+#define UHCI_RX_START_INT_RAW_S  0
+
+#define UHCI_INT_ST_REG(i)          (REG_UHCI_BASE(i) + 0x8)
+/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL1_INT_ST    (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ST_V  0x1
+#define UHCI_APP_CTRL1_INT_ST_S  8
+/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL0_INT_ST    (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ST_V  0x1
+#define UHCI_APP_CTRL0_INT_ST_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_OUTLINK_EOF_ERR_INT_ST    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  6
+/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SEND_A_Q_INT_ST    (BIT(5))
+#define UHCI_SEND_A_Q_INT_ST_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ST_V  0x1
+#define UHCI_SEND_A_Q_INT_ST_S  5
+/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SEND_S_Q_INT_ST    (BIT(4))
+#define UHCI_SEND_S_Q_INT_ST_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ST_V  0x1
+#define UHCI_SEND_S_Q_INT_ST_S  4
+/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_HUNG_INT_ST    (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_V  0x1
+#define UHCI_TX_HUNG_INT_ST_S  3
+/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_HUNG_INT_ST    (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_V  0x1
+#define UHCI_RX_HUNG_INT_ST_S  2
+/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_START_INT_ST    (BIT(1))
+#define UHCI_TX_START_INT_ST_M  (BIT(1))
+#define UHCI_TX_START_INT_ST_V  0x1
+#define UHCI_TX_START_INT_ST_S  1
+/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_START_INT_ST    (BIT(0))
+#define UHCI_RX_START_INT_ST_M  (BIT(0))
+#define UHCI_RX_START_INT_ST_V  0x1
+#define UHCI_RX_START_INT_ST_S  0
+
+#define UHCI_INT_ENA_REG(i)          (REG_UHCI_BASE(i) + 0xC)
+/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL1_INT_ENA    (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_ENA_V  0x1
+#define UHCI_APP_CTRL1_INT_ENA_S  8
+/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL0_INT_ENA    (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_ENA_V  0x1
+#define UHCI_APP_CTRL0_INT_ENA_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  6
+/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SEND_A_Q_INT_ENA    (BIT(5))
+#define UHCI_SEND_A_Q_INT_ENA_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_ENA_V  0x1
+#define UHCI_SEND_A_Q_INT_ENA_S  5
+/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SEND_S_Q_INT_ENA    (BIT(4))
+#define UHCI_SEND_S_Q_INT_ENA_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_ENA_V  0x1
+#define UHCI_SEND_S_Q_INT_ENA_S  4
+/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_HUNG_INT_ENA    (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_V  0x1
+#define UHCI_TX_HUNG_INT_ENA_S  3
+/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_HUNG_INT_ENA    (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_V  0x1
+#define UHCI_RX_HUNG_INT_ENA_S  2
+/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_START_INT_ENA    (BIT(1))
+#define UHCI_TX_START_INT_ENA_M  (BIT(1))
+#define UHCI_TX_START_INT_ENA_V  0x1
+#define UHCI_TX_START_INT_ENA_S  1
+/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_START_INT_ENA    (BIT(0))
+#define UHCI_RX_START_INT_ENA_M  (BIT(0))
+#define UHCI_RX_START_INT_ENA_V  0x1
+#define UHCI_RX_START_INT_ENA_S  0
+
+#define UHCI_INT_CLR_REG(i)          (REG_UHCI_BASE(i) + 0x10)
+/* UHCI_APP_CTRL1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL1_INT_CLR    (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_M  (BIT(8))
+#define UHCI_APP_CTRL1_INT_CLR_V  0x1
+#define UHCI_APP_CTRL1_INT_CLR_S  8
+/* UHCI_APP_CTRL0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL0_INT_CLR    (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_M  (BIT(7))
+#define UHCI_APP_CTRL0_INT_CLR_V  0x1
+#define UHCI_APP_CTRL0_INT_CLR_S  7
+/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR    (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (BIT(6))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  6
+/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SEND_A_Q_INT_CLR    (BIT(5))
+#define UHCI_SEND_A_Q_INT_CLR_M  (BIT(5))
+#define UHCI_SEND_A_Q_INT_CLR_V  0x1
+#define UHCI_SEND_A_Q_INT_CLR_S  5
+/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SEND_S_Q_INT_CLR    (BIT(4))
+#define UHCI_SEND_S_Q_INT_CLR_M  (BIT(4))
+#define UHCI_SEND_S_Q_INT_CLR_V  0x1
+#define UHCI_SEND_S_Q_INT_CLR_S  4
+/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_HUNG_INT_CLR    (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_V  0x1
+#define UHCI_TX_HUNG_INT_CLR_S  3
+/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_HUNG_INT_CLR    (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_V  0x1
+#define UHCI_RX_HUNG_INT_CLR_S  2
+/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_START_INT_CLR    (BIT(1))
+#define UHCI_TX_START_INT_CLR_M  (BIT(1))
+#define UHCI_TX_START_INT_CLR_V  0x1
+#define UHCI_TX_START_INT_CLR_S  1
+/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_START_INT_CLR    (BIT(0))
+#define UHCI_RX_START_INT_CLR_M  (BIT(0))
+#define UHCI_RX_START_INT_CLR_V  0x1
+#define UHCI_RX_START_INT_CLR_S  0
+
+#define UHCI_APP_INT_SET_REG(i)          (REG_UHCI_BASE(i) + 0x14)
+/* UHCI_APP_CTRL1_INT_SET : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL1_INT_SET    (BIT(1))
+#define UHCI_APP_CTRL1_INT_SET_M  (BIT(1))
+#define UHCI_APP_CTRL1_INT_SET_V  0x1
+#define UHCI_APP_CTRL1_INT_SET_S  1
+/* UHCI_APP_CTRL0_INT_SET : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_APP_CTRL0_INT_SET    (BIT(0))
+#define UHCI_APP_CTRL0_INT_SET_M  (BIT(0))
+#define UHCI_APP_CTRL0_INT_SET_V  0x1
+#define UHCI_APP_CTRL0_INT_SET_S  0
+
+#define UHCI_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x18)
+/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SW_START    (BIT(8))
+#define UHCI_SW_START_M  (BIT(8))
+#define UHCI_SW_START_V  0x1
+#define UHCI_SW_START_S  8
+/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_WAIT_SW_START    (BIT(7))
+#define UHCI_WAIT_SW_START_M  (BIT(7))
+#define UHCI_WAIT_SW_START_V  0x1
+#define UHCI_WAIT_SW_START_S  7
+/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_TX_ACK_NUM_RE    (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_M  (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_V  0x1
+#define UHCI_TX_ACK_NUM_RE_S  5
+/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_TX_CHECK_SUM_RE    (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_M  (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_V  0x1
+#define UHCI_TX_CHECK_SUM_RE_S  4
+/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SAVE_HEAD    (BIT(3))
+#define UHCI_SAVE_HEAD_M  (BIT(3))
+#define UHCI_SAVE_HEAD_V  0x1
+#define UHCI_SAVE_HEAD_S  3
+/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_CRC_DISABLE    (BIT(2))
+#define UHCI_CRC_DISABLE_M  (BIT(2))
+#define UHCI_CRC_DISABLE_V  0x1
+#define UHCI_CRC_DISABLE_S  2
+/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_CHECK_SEQ_EN    (BIT(1))
+#define UHCI_CHECK_SEQ_EN_M  (BIT(1))
+#define UHCI_CHECK_SEQ_EN_V  0x1
+#define UHCI_CHECK_SEQ_EN_S  1
+/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_CHECK_SUM_EN    (BIT(0))
+#define UHCI_CHECK_SUM_EN_M  (BIT(0))
+#define UHCI_CHECK_SUM_EN_V  0x1
+#define UHCI_CHECK_SUM_EN_S  0
+
+#define UHCI_STATE0_REG(i)          (REG_UHCI_BASE(i) + 0x1C)
+/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: .*/
+#define UHCI_DECODE_STATE    0x00000007
+#define UHCI_DECODE_STATE_M  ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
+#define UHCI_DECODE_STATE_V  0x7
+#define UHCI_DECODE_STATE_S  3
+/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: .*/
+#define UHCI_RX_ERR_CAUSE    0x00000007
+#define UHCI_RX_ERR_CAUSE_M  ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
+#define UHCI_RX_ERR_CAUSE_V  0x7
+#define UHCI_RX_ERR_CAUSE_S  0
+
+#define UHCI_STATE1_REG(i)          (REG_UHCI_BASE(i) + 0x20)
+/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: .*/
+#define UHCI_ENCODE_STATE    0x00000007
+#define UHCI_ENCODE_STATE_M  ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
+#define UHCI_ENCODE_STATE_V  0x7
+#define UHCI_ENCODE_STATE_S  0
+
+#define UHCI_ESCAPE_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x24)
+/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_13_ESC_EN    (BIT(7))
+#define UHCI_RX_13_ESC_EN_M  (BIT(7))
+#define UHCI_RX_13_ESC_EN_V  0x1
+#define UHCI_RX_13_ESC_EN_S  7
+/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_RX_11_ESC_EN    (BIT(6))
+#define UHCI_RX_11_ESC_EN_M  (BIT(6))
+#define UHCI_RX_11_ESC_EN_V  0x1
+#define UHCI_RX_11_ESC_EN_S  6
+/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_RX_DB_ESC_EN    (BIT(5))
+#define UHCI_RX_DB_ESC_EN_M  (BIT(5))
+#define UHCI_RX_DB_ESC_EN_V  0x1
+#define UHCI_RX_DB_ESC_EN_S  5
+/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_RX_C0_ESC_EN    (BIT(4))
+#define UHCI_RX_C0_ESC_EN_M  (BIT(4))
+#define UHCI_RX_C0_ESC_EN_V  0x1
+#define UHCI_RX_C0_ESC_EN_S  4
+/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_13_ESC_EN    (BIT(3))
+#define UHCI_TX_13_ESC_EN_M  (BIT(3))
+#define UHCI_TX_13_ESC_EN_V  0x1
+#define UHCI_TX_13_ESC_EN_S  3
+/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_TX_11_ESC_EN    (BIT(2))
+#define UHCI_TX_11_ESC_EN_M  (BIT(2))
+#define UHCI_TX_11_ESC_EN_V  0x1
+#define UHCI_TX_11_ESC_EN_S  2
+/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_TX_DB_ESC_EN    (BIT(1))
+#define UHCI_TX_DB_ESC_EN_M  (BIT(1))
+#define UHCI_TX_DB_ESC_EN_V  0x1
+#define UHCI_TX_DB_ESC_EN_S  1
+/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_TX_C0_ESC_EN    (BIT(0))
+#define UHCI_TX_C0_ESC_EN_M  (BIT(0))
+#define UHCI_TX_C0_ESC_EN_V  0x1
+#define UHCI_TX_C0_ESC_EN_S  0
+
+#define UHCI_HUNG_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x28)
+/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_RXFIFO_TIMEOUT_ENA    (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_M  (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x1
+#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
+/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: .*/
+#define UHCI_RXFIFO_TIMEOUT_SHIFT    0x00000007
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x7
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
+/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
+/*description: .*/
+#define UHCI_RXFIFO_TIMEOUT    0x000000FF
+#define UHCI_RXFIFO_TIMEOUT_M  ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
+#define UHCI_RXFIFO_TIMEOUT_V  0xFF
+#define UHCI_RXFIFO_TIMEOUT_S  12
+/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_TXFIFO_TIMEOUT_ENA    (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_M  (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x1
+#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
+/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: .*/
+#define UHCI_TXFIFO_TIMEOUT_SHIFT    0x00000007
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x7
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
+/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: .*/
+#define UHCI_TXFIFO_TIMEOUT    0x000000FF
+#define UHCI_TXFIFO_TIMEOUT_M  ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
+#define UHCI_TXFIFO_TIMEOUT_V  0xFF
+#define UHCI_TXFIFO_TIMEOUT_S  0
+
+#define UHCI_ACK_NUM_REG(i)          (REG_UHCI_BASE(i) + 0x2C)
+/* UHCI_ACK_NUM_LOAD : WO ;bitpos:[3] ;default: 1'b1 ; */
+/*description: .*/
+#define UHCI_ACK_NUM_LOAD    (BIT(3))
+#define UHCI_ACK_NUM_LOAD_M  (BIT(3))
+#define UHCI_ACK_NUM_LOAD_V  0x1
+#define UHCI_ACK_NUM_LOAD_S  3
+/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: .*/
+#define UHCI_ACK_NUM    0x00000007
+#define UHCI_ACK_NUM_M  ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S))
+#define UHCI_ACK_NUM_V  0x7
+#define UHCI_ACK_NUM_S  0
+
+#define UHCI_RX_HEAD_REG(i)          (REG_UHCI_BASE(i) + 0x30)
+/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_RX_HEAD    0xFFFFFFFF
+#define UHCI_RX_HEAD_M  ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
+#define UHCI_RX_HEAD_V  0xFFFFFFFF
+#define UHCI_RX_HEAD_S  0
+
+#define UHCI_QUICK_SENT_REG(i)          (REG_UHCI_BASE(i) + 0x34)
+/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_ALWAYS_SEND_EN    (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_M  (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_V  0x1
+#define UHCI_ALWAYS_SEND_EN_S  7
+/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: .*/
+#define UHCI_ALWAYS_SEND_NUM    0x00000007
+#define UHCI_ALWAYS_SEND_NUM_M  ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
+#define UHCI_ALWAYS_SEND_NUM_V  0x7
+#define UHCI_ALWAYS_SEND_NUM_S  4
+/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: .*/
+#define UHCI_SINGLE_SEND_EN    (BIT(3))
+#define UHCI_SINGLE_SEND_EN_M  (BIT(3))
+#define UHCI_SINGLE_SEND_EN_V  0x1
+#define UHCI_SINGLE_SEND_EN_S  3
+/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: .*/
+#define UHCI_SINGLE_SEND_NUM    0x00000007
+#define UHCI_SINGLE_SEND_NUM_M  ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
+#define UHCI_SINGLE_SEND_NUM_V  0x7
+#define UHCI_SINGLE_SEND_NUM_S  0
+
+#define UHCI_Q0_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x38)
+/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q0_WORD0    0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_M  ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
+#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_S  0
+
+#define UHCI_Q0_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x3C)
+/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q0_WORD1    0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_M  ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
+#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_S  0
+
+#define UHCI_Q1_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x40)
+/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q1_WORD0    0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_M  ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
+#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_S  0
+
+#define UHCI_Q1_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x44)
+/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q1_WORD1    0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_M  ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
+#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_S  0
+
+#define UHCI_Q2_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x48)
+/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q2_WORD0    0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_M  ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
+#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_S  0
+
+#define UHCI_Q2_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x4C)
+/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q2_WORD1    0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_M  ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
+#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_S  0
+
+#define UHCI_Q3_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x50)
+/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q3_WORD0    0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_M  ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
+#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_S  0
+
+#define UHCI_Q3_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x54)
+/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q3_WORD1    0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_M  ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
+#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_S  0
+
+#define UHCI_Q4_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x58)
+/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q4_WORD0    0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_M  ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
+#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_S  0
+
+#define UHCI_Q4_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x5C)
+/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q4_WORD1    0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_M  ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
+#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_S  0
+
+#define UHCI_Q5_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x60)
+/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q5_WORD0    0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_M  ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
+#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_S  0
+
+#define UHCI_Q5_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x64)
+/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q5_WORD1    0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_M  ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
+#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_S  0
+
+#define UHCI_Q6_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x68)
+/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q6_WORD0    0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_M  ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
+#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_S  0
+
+#define UHCI_Q6_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x6C)
+/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: .*/
+#define UHCI_SEND_Q6_WORD1    0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_M  ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
+#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_S  0
+
+#define UHCI_ESC_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x70)
+/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
+/*description: .*/
+#define UHCI_SEPER_ESC_CHAR1    0x000000FF
+#define UHCI_SEPER_ESC_CHAR1_M  ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
+#define UHCI_SEPER_ESC_CHAR1_V  0xFF
+#define UHCI_SEPER_ESC_CHAR1_S  16
+/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: .*/
+#define UHCI_SEPER_ESC_CHAR0    0x000000FF
+#define UHCI_SEPER_ESC_CHAR0_M  ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
+#define UHCI_SEPER_ESC_CHAR0_V  0xFF
+#define UHCI_SEPER_ESC_CHAR0_S  8
+/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
+/*description: .*/
+#define UHCI_SEPER_CHAR    0x000000FF
+#define UHCI_SEPER_CHAR_M  ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
+#define UHCI_SEPER_CHAR_V  0xFF
+#define UHCI_SEPER_CHAR_S  0
+
+#define UHCI_ESC_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x74)
+/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
+/*description: .*/
+#define UHCI_ESC_SEQ0_CHAR1    0x000000FF
+#define UHCI_ESC_SEQ0_CHAR1_M  ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
+#define UHCI_ESC_SEQ0_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ0_CHAR1_S  16
+/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: .*/
+#define UHCI_ESC_SEQ0_CHAR0    0x000000FF
+#define UHCI_ESC_SEQ0_CHAR0_M  ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
+#define UHCI_ESC_SEQ0_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ0_CHAR0_S  8
+/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
+/*description: .*/
+#define UHCI_ESC_SEQ0    0x000000FF
+#define UHCI_ESC_SEQ0_M  ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
+#define UHCI_ESC_SEQ0_V  0xFF
+#define UHCI_ESC_SEQ0_S  0
+
+#define UHCI_ESC_CONF2_REG(i)          (REG_UHCI_BASE(i) + 0x78)
+/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
+/*description: .*/
+#define UHCI_ESC_SEQ1_CHAR1    0x000000FF
+#define UHCI_ESC_SEQ1_CHAR1_M  ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
+#define UHCI_ESC_SEQ1_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ1_CHAR1_S  16
+/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: .*/
+#define UHCI_ESC_SEQ1_CHAR0    0x000000FF
+#define UHCI_ESC_SEQ1_CHAR0_M  ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
+#define UHCI_ESC_SEQ1_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ1_CHAR0_S  8
+/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
+/*description: .*/
+#define UHCI_ESC_SEQ1    0x000000FF
+#define UHCI_ESC_SEQ1_M  ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
+#define UHCI_ESC_SEQ1_V  0xFF
+#define UHCI_ESC_SEQ1_S  0
+
+#define UHCI_ESC_CONF3_REG(i)          (REG_UHCI_BASE(i) + 0x7C)
+/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
+/*description: .*/
+#define UHCI_ESC_SEQ2_CHAR1    0x000000FF
+#define UHCI_ESC_SEQ2_CHAR1_M  ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
+#define UHCI_ESC_SEQ2_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ2_CHAR1_S  16
+/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: .*/
+#define UHCI_ESC_SEQ2_CHAR0    0x000000FF
+#define UHCI_ESC_SEQ2_CHAR0_M  ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
+#define UHCI_ESC_SEQ2_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ2_CHAR0_S  8
+/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
+/*description: .*/
+#define UHCI_ESC_SEQ2    0x000000FF
+#define UHCI_ESC_SEQ2_M  ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
+#define UHCI_ESC_SEQ2_V  0xFF
+#define UHCI_ESC_SEQ2_S  0
+
+#define UHCI_PKT_THRES_REG(i)          (REG_UHCI_BASE(i) + 0x80)
+/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
+/*description: .*/
+#define UHCI_PKT_THRS    0x00001FFF
+#define UHCI_PKT_THRS_M  ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
+#define UHCI_PKT_THRS_V  0x1FFF
+#define UHCI_PKT_THRS_S  0
+
+#define UHCI_DATE_REG(i)          (REG_UHCI_BASE(i) + 0x84)
+/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2010090 ; */
+/*description: .*/
+#define UHCI_DATE    0xFFFFFFFF
+#define UHCI_DATE_M  ((UHCI_DATE_V)<<(UHCI_DATE_S))
+#define UHCI_DATE_V  0xFFFFFFFF
+#define UHCI_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UHCI_REG_H_ */
diff --git a/components/soc/esp32s3/include/soc/uhci_struct.h b/components/soc/esp32s3/register/soc/uhci_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/uhci_struct.h
rename to components/soc/esp32s3/register/soc/uhci_struct.h
diff --git a/components/soc/esp32s3/include/soc/usb_reg.h b/components/soc/esp32s3/register/soc/usb_reg.h
similarity index 99%
rename from components/soc/esp32s3/include/soc/usb_reg.h
rename to components/soc/esp32s3/register/soc/usb_reg.h
index 90bc61d71ac..d98ebf419b6 100644
--- a/components/soc/esp32s3/include/soc/usb_reg.h
+++ b/components/soc/esp32s3/register/soc/usb_reg.h
@@ -8,7 +8,7 @@
 
 #include <stdint.h>
 #include "soc/soc.h"
-#include "soc.h"
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -608,7 +608,7 @@ extern "C" {
 #define USB_H_LSPDDEV0_V  0x00000001
 #define USB_H_LSPDDEV0_S  17
 /** USB_H_EPTYPE0 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -647,7 +647,7 @@ extern "C" {
 #define USB_H_ODDFRM0_S  29
 /** USB_H_CHDIS0 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS0    (BIT(30))
@@ -720,7 +720,7 @@ extern "C" {
 #define USB_H_LSPDDEV1_V  0x00000001
 #define USB_H_LSPDDEV1_S  17
 /** USB_H_EPTYPE1 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -759,7 +759,7 @@ extern "C" {
 #define USB_H_ODDFRM1_S  29
 /** USB_H_CHDIS1 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS1    (BIT(30))
@@ -832,7 +832,7 @@ extern "C" {
 #define USB_H_LSPDDEV2_V  0x00000001
 #define USB_H_LSPDDEV2_S  17
 /** USB_H_EPTYPE2 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -871,7 +871,7 @@ extern "C" {
 #define USB_H_ODDFRM2_S  29
 /** USB_H_CHDIS2 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS2    (BIT(30))
@@ -944,7 +944,7 @@ extern "C" {
 #define USB_H_LSPDDEV3_V  0x00000001
 #define USB_H_LSPDDEV3_S  17
 /** USB_H_EPTYPE3 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -983,7 +983,7 @@ extern "C" {
 #define USB_H_ODDFRM3_S  29
 /** USB_H_CHDIS3 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS3    (BIT(30))
@@ -1056,7 +1056,7 @@ extern "C" {
 #define USB_H_LSPDDEV4_V  0x00000001
 #define USB_H_LSPDDEV4_S  17
 /** USB_H_EPTYPE4 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -1095,7 +1095,7 @@ extern "C" {
 #define USB_H_ODDFRM4_S  29
 /** USB_H_CHDIS4 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS4    (BIT(30))
@@ -1168,7 +1168,7 @@ extern "C" {
 #define USB_H_LSPDDEV5_V  0x00000001
 #define USB_H_LSPDDEV5_S  17
 /** USB_H_EPTYPE5 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -1207,7 +1207,7 @@ extern "C" {
 #define USB_H_ODDFRM5_S  29
 /** USB_H_CHDIS5 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS5    (BIT(30))
@@ -1280,7 +1280,7 @@ extern "C" {
 #define USB_H_LSPDDEV6_V  0x00000001
 #define USB_H_LSPDDEV6_S  17
 /** USB_H_EPTYPE6 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -1319,7 +1319,7 @@ extern "C" {
 #define USB_H_ODDFRM6_S  29
 /** USB_H_CHDIS6 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS6    (BIT(30))
@@ -1392,7 +1392,7 @@ extern "C" {
 #define USB_H_LSPDDEV7_V  0x00000001
 #define USB_H_LSPDDEV7_S  17
 /** USB_H_EPTYPE7 : R/W; bitpos: [20:18]; default: 0;
- *  0x0 (CTRL): Contro
+ *  0x0 (CTRL): Control
  *  0x1 (ISOC): Isochronous
  *  0x2 (BULK): Bulk
  *  0x3 (INTERR): Interrupt
@@ -1431,7 +1431,7 @@ extern "C" {
 #define USB_H_ODDFRM7_S  29
 /** USB_H_CHDIS7 : R/W; bitpos: [30]; default: 0;
  *  Channel Disable
- *  0x0 : Transmit/Recieve norma
+ *  0x0 : Transmit/Receive norma
  *  0x1 : Stop transmitting/receiving data on channel
  */
 #define USB_H_CHDIS7    (BIT(30))
@@ -1476,7 +1476,7 @@ extern "C" {
 /** USB_NZSTSOUTHSHK : R/W; bitpos: [2]; default: 0;
  *  1'b0: Send the received OUT packet to the application (zero-length or non-zero
  *  length) and send a handshake based on NAK and STALL bits for the endpoint in the
- *  Devce Endpoint Control Register
+ *  Device Endpoint Control Register
  *  1'b1: Send a STALL handshake on a nonzero-length status OUT transaction and do not
  *  send the received OUT packet to the application
  */
@@ -1488,7 +1488,7 @@ extern "C" {
  *  This bit can be set only if FS PHY interface is selected.
  *  Otherwise, this bit needs to be set to zero.
  *  1'b0: USB 1.1 Full-Speed Serial transiver not selected
- *  1'b1: If FS PHY interface is choosen and this bit is set, the PHY clock during Suspend
+ *  1'b1: If FS PHY interface is chosen and this bit is set, the PHY clock during Suspend
  *  must be switched from 48 MHz to 32 KHz
  */
 #define USB_ENA32KHZSUSP    (BIT(3))
@@ -1580,7 +1580,7 @@ extern "C" {
 #define USB_DCTL_REG (SOC_DPORT_USB_BASE + 0x804)
 /** USB_RMTWKUPSIG : R/W; bitpos: [0]; default: 0;
  *  0x0 : Core does not send Remote Wakeup Signaling
- *  0x1 : Core sends Remote Wakeup Signalin
+ *  0x1 : Core sends Remote Wakeup Signaling
  */
 #define USB_RMTWKUPSIG    (BIT(0))
 #define USB_RMTWKUPSIG_M  (USB_RMTWKUPSIG_V << USB_RMTWKUPSIG_S)
@@ -4729,7 +4729,7 @@ extern "C" {
 #define USB_H_NACK0_S  4
 /** USB_H_ACK0 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK0    (BIT(5))
 #define USB_H_ACK0_M  (USB_H_ACK0_V << USB_H_ACK0_S)
@@ -4965,7 +4965,7 @@ extern "C" {
 #define USB_H_NACK1_S  4
 /** USB_H_ACK1 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK1    (BIT(5))
 #define USB_H_ACK1_M  (USB_H_ACK1_V << USB_H_ACK1_S)
@@ -5201,7 +5201,7 @@ extern "C" {
 #define USB_H_NACK2_S  4
 /** USB_H_ACK2 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK2    (BIT(5))
 #define USB_H_ACK2_M  (USB_H_ACK2_V << USB_H_ACK2_S)
@@ -5437,7 +5437,7 @@ extern "C" {
 #define USB_H_NACK3_S  4
 /** USB_H_ACK3 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK3    (BIT(5))
 #define USB_H_ACK3_M  (USB_H_ACK3_V << USB_H_ACK3_S)
@@ -5673,7 +5673,7 @@ extern "C" {
 #define USB_H_NACK4_S  4
 /** USB_H_ACK4 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK4    (BIT(5))
 #define USB_H_ACK4_M  (USB_H_ACK4_V << USB_H_ACK4_S)
@@ -5909,7 +5909,7 @@ extern "C" {
 #define USB_H_NACK5_S  4
 /** USB_H_ACK5 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK5    (BIT(5))
 #define USB_H_ACK5_M  (USB_H_ACK5_V << USB_H_ACK5_S)
@@ -6145,7 +6145,7 @@ extern "C" {
 #define USB_H_NACK6_S  4
 /** USB_H_ACK6 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK6    (BIT(5))
 #define USB_H_ACK6_M  (USB_H_ACK6_V << USB_H_ACK6_S)
@@ -6381,7 +6381,7 @@ extern "C" {
 #define USB_H_NACK7_S  4
 /** USB_H_ACK7 : R/W1C; bitpos: [5]; default: 0;
  *  1'b0: No ACK Response Received or Transmitted Interrupt
- *  1'b1: ACK Response Received or Transmitted Interrup
+ *  1'b1: ACK Response Received or Transmitted Interrupt
  */
 #define USB_H_ACK7    (BIT(5))
 #define USB_H_ACK7_M  (USB_H_ACK7_V << USB_H_ACK7_S)
@@ -8915,9 +8915,9 @@ extern "C" {
 #define USB_AHBSINGLE_V  0x00000001
 #define USB_AHBSINGLE_S  23
 /** USB_INVDESCENDIANESS : R/W; bitpos: [24]; default: 0;
- *  Invert Descriptor Endianess
+ *  Invert Descriptor Endianness
  *  1'b0: Descriptor Endianness is same as AHB Master Endianness
- *  1'b1:Invert Descriptor Endianess according to AHB Master endianness
+ *  1'b1:Invert Descriptor Endianness according to AHB Master endianness
  */
 #define USB_INVDESCENDIANESS    (BIT(24))
 #define USB_INVDESCENDIANESS_M  (USB_INVDESCENDIANESS_V << USB_INVDESCENDIANESS_S)
@@ -9678,7 +9678,7 @@ extern "C" {
 
 
 /** USB_GSNPSID_REG register
- *  Synopsys ID Register
+ *  ID Register
  */
 #define USB_GSNPSID_REG (SOC_DPORT_USB_BASE + 0x40)
 /** USB_SYNOPSYSID : RO; bitpos: [32:0]; default: 1330921482;
diff --git a/components/soc/esp32s3/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32s3/register/soc/usb_serial_jtag_reg.h
new file mode 100644
index 00000000000..2338bc6a4de
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/usb_serial_jtag_reg.h
@@ -0,0 +1,732 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+#define USB_SERIAL_JTAG_EP1_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+/* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE
+VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into
+UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB
+_DEVICE_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is rece
+ived, then read data from UART Rx FIFO..*/
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FF
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S))
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0xFF
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+#define USB_SERIAL_JTAG_EP1_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1'b1: Indicate there is data in UART Rx FIFO..*/
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After
+writing USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
+USB Host..*/
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/* USB_SERIAL_JTAG_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done..*/
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_V  0x1
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+
+#define USB_SERIAL_JTAG_INT_RAW_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi
+th zero palyload..*/
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet wi
+th zero palyload..*/
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when usb bus reset is detected..*/
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is rec
+eived..*/
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when stuff error is detected..*/
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when CRC16 error is detected..*/
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when CRC5 error is detected..*/
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when pid error is detected..*/
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */
+/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty..*/
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ one packet..*/
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when SOF frame is received..*/
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt bit turns to high level when flush cmd is received for IN
+endpoint 2 of JTAG..*/
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x1
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+
+#define USB_SERIAL_JTAG_INT_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0xC)
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interru
+pt..*/
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interru
+pt..*/
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt
+t..*/
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt
+t..*/
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/* USB_SERIAL_JTAG_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt..*/
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x1
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+
+#define USB_SERIAL_JTAG_INT_ENA_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt..*/
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt..*/
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt..*/
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x1
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+
+#define USB_SERIAL_JTAG_INT_CLR_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt..*/
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt..*/
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/* USB_SERIAL_JTAG_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt..*/
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x1
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+
+#define USB_SERIAL_JTAG_CONF0_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+/* USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disc
+onnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input thr
+ough GPIO Matrix..*/
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN    (BIT(16))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M  (BIT(16))
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V  0x1
+#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S  16
+/* USB_SERIAL_JTAG_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 0: TX output at clock negedge. 1: Tx output at clock posedge..*/
+#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL    (BIT(15))
+#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_M  (BIT(15))
+#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V  0x1
+#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S  15
+/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: Enable USB pad function..*/
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x1
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Control pull up value..*/
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x1
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Control USB D- pull down..*/
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x1
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/* USB_SERIAL_JTAG_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Control USB D- pull up..*/
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x1
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Control USB D+ pull down..*/
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x1
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/* USB_SERIAL_JTAG_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: Control USB D+ pull up..*/
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x1
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Enable software control USB D+ D- pullup pulldown.*/
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x1
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Enable software control input  threshold.*/
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x1
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/* USB_SERIAL_JTAG_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
+/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/
+#define USB_SERIAL_JTAG_VREFL    0x00000003
+#define USB_SERIAL_JTAG_VREFL_M  ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S))
+#define USB_SERIAL_JTAG_VREFL_V  0x3
+#define USB_SERIAL_JTAG_VREFL_S  5
+/* USB_SERIAL_JTAG_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/
+#define USB_SERIAL_JTAG_VREFH    0x00000003
+#define USB_SERIAL_JTAG_VREFH_M  ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S))
+#define USB_SERIAL_JTAG_VREFH_V  0x3
+#define USB_SERIAL_JTAG_VREFH_S  3
+/* USB_SERIAL_JTAG_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: USB D+ D- exchange.*/
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x1
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Enable software control USB D+ D- exchange.*/
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x1
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/* USB_SERIAL_JTAG_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Select internal/external PHY.*/
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x1
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+
+#define USB_SERIAL_JTAG_TEST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x1C)
+/* USB_SERIAL_JTAG_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: USB D- rx value in test.*/
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x1
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+/* USB_SERIAL_JTAG_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: USB D+ rx value in test.*/
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x1
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/* USB_SERIAL_JTAG_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: USB differential rx value in test.*/
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x1
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/* USB_SERIAL_JTAG_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: USB D- tx value in test.*/
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x1
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/* USB_SERIAL_JTAG_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: USB D+ tx value in test.*/
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x1
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/* USB_SERIAL_JTAG_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: USB pad oen in test.*/
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x1
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/* USB_SERIAL_JTAG_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Enable test of the USB pad.*/
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x1
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+
+#define USB_SERIAL_JTAG_JFIFO_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Write 1 to reset JTAG out fifo..*/
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x1
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Write 1 to reset JTAG in fifo..*/
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x1
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: 1: JTAG out fifo is full..*/
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x1
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */
+/*description: 1: JTAG out fifo is empty..*/
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x1
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: JTAT out fifo counter..*/
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S))
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x3
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: 1: JTAG in fifo is full..*/
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x1
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */
+/*description: 1: JTAG in fifo is empty..*/
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x1
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: JTAT in fifo counter..*/
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S))
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x3
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+
+#define USB_SERIAL_JTAG_FRAM_NUM_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */
+/*description: Frame index of received SOF frame..*/
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FF
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S))
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x7FF
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
+/*description: Read data address of IN endpoint 0..*/
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S))
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
+/*description: Write data address of IN endpoint 0..*/
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S))
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: State of IN Endpoint 0..*/
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S))
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x3
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x2C)
+/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
+/*description: Read data address of IN endpoint 1..*/
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S))
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
+/*description: Write data address of IN endpoint 1..*/
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S))
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: State of IN Endpoint 1..*/
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S))
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x3
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
+/*description: Read data address of IN endpoint 2..*/
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S))
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
+/*description: Write data address of IN endpoint 2..*/
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S))
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: State of IN Endpoint 2..*/
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S))
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x3
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
+/*description: Read data address of IN endpoint 3..*/
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S))
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
+/*description: Write data address of IN endpoint 3..*/
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S))
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
+/*description: State of IN Endpoint 3..*/
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S))
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x3
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
+/*description: Read data address of OUT endpoint 0..*/
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S))
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
+/*description: Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
+ detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0..*/
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S))
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: State of OUT Endpoint 0..*/
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S))
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x3
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x3C)
+/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */
+/*description: Data count in OUT endpoint 1 when one packet is received..*/
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S))
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x7F
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
+/*description: Read data address of OUT endpoint 1..*/
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S))
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
+/*description: Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
+ detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S))
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: State of OUT Endpoint 1..*/
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S))
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x3
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
+/*description: Read data address of OUT endpoint 2..*/
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S))
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
+/*description: Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
+ detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007F
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S))
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x7F
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: State of OUT Endpoint 2..*/
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S))
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x3
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+
+#define USB_SERIAL_JTAG_MISC_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+/* USB_SERIAL_JTAG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
+tes registers..*/
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_V  0x1
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+#define USB_SERIAL_JTAG_MEM_CONF_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: 1: Force clock on for usb memory..*/
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x1
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+/* USB_SERIAL_JTAG_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1: power down usb memory..*/
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x1
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+
+#define USB_SERIAL_JTAG_DATE_REG          (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+/* USB_SERIAL_JTAG_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101200 ; */
+/*description: register version..*/
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFF
+#define USB_SERIAL_JTAG_DATE_M  ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S))
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFF
+#define USB_SERIAL_JTAG_DATE_S  0
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/register/soc/usb_serial_jtag_struct.h b/components/soc/esp32s3/register/soc/usb_serial_jtag_struct.h
new file mode 100644
index 00000000000..aeb3bb47caa
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/usb_serial_jtag_struct.h
@@ -0,0 +1,259 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
+#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc/soc.h"
+
+typedef volatile struct usb_serial_jtag_dev_s {
+    union {
+        struct {
+            uint32_t rdwr_byte                 :    32;  /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.*/
+        };
+        uint32_t val;
+    } ep1;
+    union {
+        struct {
+            uint32_t wr_done                   :    1;  /*Set this bit to indicate writing byte data to UART Tx FIFO is done.*/
+            uint32_t serial_in_ep_data_free    :    1;  /*1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.*/
+            uint32_t serial_out_ep_data_avail  :    1;  /*1'b1: Indicate there is data in UART Rx FIFO.*/
+            uint32_t reserved3                     :    29;  /*reserved*/
+        };
+        uint32_t val;
+    } ep1_conf;
+    union {
+        struct {
+            uint32_t jtag_in_flush_int_raw     :    1;  /*The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.*/
+            uint32_t sof_int_raw               :    1;  /*The raw interrupt bit turns to high level when SOF frame is received.*/
+            uint32_t serial_out_recv_pkt_int_raw:    1;  /*The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.*/
+            uint32_t serial_in_empty_int_raw   :    1;  /*The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.*/
+            uint32_t pid_err_int_raw           :    1;  /*The raw interrupt bit turns to high level when pid error is detected.*/
+            uint32_t crc5_err_int_raw          :    1;  /*The raw interrupt bit turns to high level when CRC5 error is detected.*/
+            uint32_t crc16_err_int_raw         :    1;  /*The raw interrupt bit turns to high level when CRC16 error is detected.*/
+            uint32_t stuff_err_int_raw         :    1;  /*The raw interrupt bit turns to high level when stuff error is detected.*/
+            uint32_t in_token_rec_in_ep1_int_raw:    1;  /*The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.*/
+            uint32_t usb_bus_reset_int_raw     :    1;  /*The raw interrupt bit turns to high level when usb bus reset is detected.*/
+            uint32_t out_ep1_zero_payload_int_raw:    1;  /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.*/
+            uint32_t out_ep2_zero_payload_int_raw:    1;  /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t jtag_in_flush_int_st      :    1;  /*The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
+            uint32_t sof_int_st                :    1;  /*The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.*/
+            uint32_t serial_out_recv_pkt_int_st:    1;  /*The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
+            uint32_t serial_in_empty_int_st    :    1;  /*The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
+            uint32_t pid_err_int_st            :    1;  /*The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
+            uint32_t crc5_err_int_st           :    1;  /*The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/
+            uint32_t crc16_err_int_st          :    1;  /*The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
+            uint32_t stuff_err_int_st          :    1;  /*The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
+            uint32_t in_token_rec_in_ep1_int_st:    1;  /*The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
+            uint32_t usb_bus_reset_int_st      :    1;  /*The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
+            uint32_t out_ep1_zero_payload_int_st:    1;  /*The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t out_ep2_zero_payload_int_st:    1;  /*The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t jtag_in_flush_int_ena     :    1;  /*The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
+            uint32_t sof_int_ena               :    1;  /*The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.*/
+            uint32_t serial_out_recv_pkt_int_ena:    1;  /*The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
+            uint32_t serial_in_empty_int_ena   :    1;  /*The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
+            uint32_t pid_err_int_ena           :    1;  /*The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
+            uint32_t crc5_err_int_ena          :    1;  /*The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/
+            uint32_t crc16_err_int_ena         :    1;  /*The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
+            uint32_t stuff_err_int_ena         :    1;  /*The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
+            uint32_t in_token_rec_in_ep1_int_ena:    1;  /*The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
+            uint32_t usb_bus_reset_int_ena     :    1;  /*The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
+            uint32_t out_ep1_zero_payload_int_ena:    1;  /*The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t out_ep2_zero_payload_int_ena:    1;  /*The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t jtag_in_flush_int_clr     :    1;  /*Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
+            uint32_t sof_int_clr               :    1;  /*Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.*/
+            uint32_t serial_out_recv_pkt_int_clr:    1;  /*Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
+            uint32_t serial_in_empty_int_clr   :    1;  /*Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
+            uint32_t pid_err_int_clr           :    1;  /*Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.*/
+            uint32_t crc5_err_int_clr          :    1;  /*Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.*/
+            uint32_t crc16_err_int_clr         :    1;  /*Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.*/
+            uint32_t stuff_err_int_clr         :    1;  /*Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.*/
+            uint32_t in_token_rec_in_ep1_int_clr:    1;  /*Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.*/
+            uint32_t usb_bus_reset_int_clr     :    1;  /*Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
+            uint32_t out_ep1_zero_payload_int_clr:    1;  /*Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t out_ep2_zero_payload_int_clr:    1;  /*Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
+            uint32_t reserved12                    :    20;  /*reserved*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t phy_sel                   :    1;  /*Select internal/external PHY*/
+            uint32_t exchg_pins_override       :    1;  /*Enable software control USB D+ D- exchange*/
+            uint32_t exchg_pins                :    1;  /*USB D+ D- exchange*/
+            uint32_t vrefh                     :    2;  /*Control single-end input high threshold,1.76V to 2V, step 80mV*/
+            uint32_t vrefl                     :    2;  /*Control single-end input low threshold,0.8V to 1.04V, step 80mV*/
+            uint32_t vref_override             :    1;  /*Enable software control input  threshold*/
+            uint32_t pad_pull_override         :    1;  /*Enable software control USB D+ D- pullup pulldown*/
+            uint32_t dp_pullup                 :    1;  /*Control USB D+ pull up.*/
+            uint32_t dp_pulldown               :    1;  /*Control USB D+ pull down.*/
+            uint32_t dm_pullup                 :    1;  /*Control USB D- pull up.*/
+            uint32_t dm_pulldown               :    1;  /*Control USB D- pull down.*/
+            uint32_t pullup_value              :    1;  /*Control pull up value.*/
+            uint32_t usb_pad_enable            :    1;  /*Enable USB pad function.*/
+            uint32_t phy_tx_edge_sel           :    1;  /*0: TX output at clock negedge. 1: Tx output at clock posedge.*/
+            uint32_t usb_jtag_bridge_en        :    1;  /*Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix.*/
+            uint32_t reserved17                    :    15;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t test_enable               :    1;  /*Enable test of the USB pad*/
+            uint32_t test_usb_oe               :    1;  /*USB pad oen in test*/
+            uint32_t test_tx_dp                :    1;  /*USB D+ tx value in test*/
+            uint32_t test_tx_dm                :    1;  /*USB D- tx value in test*/
+            uint32_t test_rx_rcv               :    1;  /*USB differential rx value in test*/
+            uint32_t test_rx_dp                :    1;  /*USB D+ rx value in test*/
+            uint32_t test_rx_dm                :    1;  /*USB D- rx value in test*/
+            uint32_t reserved7                     :    25;
+        };
+        uint32_t val;
+    } test;
+    union {
+        struct {
+            uint32_t in_fifo_cnt               :    2;  /*JTAT in fifo counter.*/
+            uint32_t in_fifo_empty             :    1;  /*1: JTAG in fifo is empty.*/
+            uint32_t in_fifo_full              :    1;  /*1: JTAG in fifo is full.*/
+            uint32_t out_fifo_cnt              :    2;  /*JTAT out fifo counter.*/
+            uint32_t out_fifo_empty            :    1;  /*1: JTAG out fifo is empty.*/
+            uint32_t out_fifo_full             :    1;  /*1: JTAG out fifo is full.*/
+            uint32_t in_fifo_reset             :    1;  /*Write 1 to reset JTAG in fifo.*/
+            uint32_t out_fifo_reset            :    1;  /*Write 1 to reset JTAG out fifo.*/
+            uint32_t reserved10                    :    22;
+        };
+        uint32_t val;
+    } jfifo_st;
+    union {
+        struct {
+            uint32_t sof_frame_index           :    11;  /*Frame index of received SOF frame.*/
+            uint32_t reserved11                    :    21;
+        };
+        uint32_t val;
+    } fram_num;
+    union {
+        struct {
+            uint32_t in_ep0_state              :    2;  /*State of IN Endpoint 0.*/
+            uint32_t in_ep0_wr_addr            :    7;  /*Write data address of IN endpoint 0.*/
+            uint32_t in_ep0_rd_addr            :    7;  /*Read data address of IN endpoint 0.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } in_ep0_st;
+    union {
+        struct {
+            uint32_t in_ep1_state              :    2;  /*State of IN Endpoint 1.*/
+            uint32_t in_ep1_wr_addr            :    7;  /*Write data address of IN endpoint 1.*/
+            uint32_t in_ep1_rd_addr            :    7;  /*Read data address of IN endpoint 1.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } in_ep1_st;
+    union {
+        struct {
+            uint32_t in_ep2_state              :    2;  /*State of IN Endpoint 2.*/
+            uint32_t in_ep2_wr_addr            :    7;  /*Write data address of IN endpoint 2.*/
+            uint32_t in_ep2_rd_addr            :    7;  /*Read data address of IN endpoint 2.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } in_ep2_st;
+    union {
+        struct {
+            uint32_t in_ep3_state              :    2;  /*State of IN Endpoint 3.*/
+            uint32_t in_ep3_wr_addr            :    7;  /*Write data address of IN endpoint 3.*/
+            uint32_t in_ep3_rd_addr            :    7;  /*Read data address of IN endpoint 3.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } in_ep3_st;
+    union {
+        struct {
+            uint32_t out_ep0_state             :    2;  /*State of OUT Endpoint 0.*/
+            uint32_t out_ep0_wr_addr           :    7;  /*Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.*/
+            uint32_t out_ep0_rd_addr           :    7;  /*Read data address of OUT endpoint 0.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } out_ep0_st;
+    union {
+        struct {
+            uint32_t out_ep1_state             :    2;  /*State of OUT Endpoint 1.*/
+            uint32_t out_ep1_wr_addr           :    7;  /*Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
+            uint32_t out_ep1_rd_addr           :    7;  /*Read data address of OUT endpoint 1.*/
+            uint32_t out_ep1_rec_data_cnt      :    7;  /*Data count in OUT endpoint 1 when one packet is received.*/
+            uint32_t reserved23                    :    9;  /*reserved*/
+        };
+        uint32_t val;
+    } out_ep1_st;
+    union {
+        struct {
+            uint32_t out_ep2_state             :    2;  /*State of OUT Endpoint 2.*/
+            uint32_t out_ep2_wr_addr           :    7;  /*Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
+            uint32_t out_ep2_rd_addr           :    7;  /*Read data address of OUT endpoint 2.*/
+            uint32_t reserved16                    :    16;  /*reserved*/
+        };
+        uint32_t val;
+    } out_ep2_st;
+    union {
+        struct {
+            uint32_t clk_en                    :    1;  /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
+            uint32_t reserved1                     :    31;
+        };
+        uint32_t val;
+    } misc_conf;
+    union {
+        struct {
+            uint32_t usb_mem_pd                :    1;  /*1: power down usb memory.*/
+            uint32_t usb_mem_clk_en            :    1;  /*1: Force clock on for usb memory.*/
+            uint32_t reserved2                     :    30;
+        };
+        uint32_t val;
+    } mem_conf;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t date;
+} usb_serial_jtag_dev_t;
+extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */
diff --git a/components/soc/esp32s3/include/soc/usb_struct.h b/components/soc/esp32s3/register/soc/usb_struct.h
similarity index 98%
rename from components/soc/esp32s3/include/soc/usb_struct.h
rename to components/soc/esp32s3/register/soc/usb_struct.h
index 697c79e416f..a07aa34f533 100644
--- a/components/soc/esp32s3/include/soc/usb_struct.h
+++ b/components/soc/esp32s3/register/soc/usb_struct.h
@@ -50,7 +50,7 @@ typedef struct usb_reg {
     volatile uint32_t gnptxfsiz;            // 0x0028 Non-periodic Transmit FIFO Size Register
     volatile uint32_t gnptxsts;             // 0x002c Non-periodic Transmit FIFO/Queue Status Register
     uint32_t reserved_0x0030_0x0040[4];     // 0x0030 to 0x0040
-    volatile uint32_t gsnpsid;              // 0x0040 Synopsys ID Register
+    volatile uint32_t gsnpsid;              // 0x0040 ID Register
     volatile uint32_t ghwcfg1;              // 0x0044 User Hardware Configuration 1 Register
     volatile uint32_t ghwcfg2;              // 0x0048 User Hardware Configuration 2 Register
     volatile uint32_t ghwcfg3;              // 0x004c User Hardware Configuration 3 Register
diff --git a/components/soc/esp32s3/include/soc/usb_wrap_reg.h b/components/soc/esp32s3/register/soc/usb_wrap_reg.h
similarity index 93%
rename from components/soc/esp32s3/include/soc/usb_wrap_reg.h
rename to components/soc/esp32s3/register/soc/usb_wrap_reg.h
index 45502289cdf..9b8ea950a24 100644
--- a/components/soc/esp32s3/include/soc/usb_wrap_reg.h
+++ b/components/soc/esp32s3/register/soc/usb_wrap_reg.h
@@ -1,21 +1,13 @@
-// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_USB_WRAP_REG_H_
 #define _SOC_USB_WRAP_REG_H_
 
 
-#include "soc.h"
+#include "soc/soc.h"
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/soc/esp32s3/register/soc/usb_wrap_struct.h b/components/soc/esp32s3/register/soc/usb_wrap_struct.h
new file mode 100644
index 00000000000..9f440d17e9a
--- /dev/null
+++ b/components/soc/esp32s3/register/soc/usb_wrap_struct.h
@@ -0,0 +1,436 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Control/Status registers */
+/** Type of otg_conf register
+ *  PAD/DFIFO/PHY configuration register.
+ */
+typedef union {
+    struct {
+        /** srp_sessend_override : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to enable the software override of srp session end signal.1'b0:
+         *  the signal is controlled by the chip input.1'b1: the signal is controlled by the
+         *  software.
+         */
+        uint32_t srp_sessend_override:1;
+        /** srp_sessend_value : R/W; bitpos: [1]; default: 0;
+         *  Software override value of srp session end signal.
+         */
+        uint32_t srp_sessend_value:1;
+        /** phy_sel : R/W; bitpos: [2]; default: 0;
+         *  Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY
+         */
+        uint32_t phy_sel:1;
+        /** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
+         *  Force the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pd:1;
+        /** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
+         *  Bypass Debounce filters for avalid.
+         */
+        uint32_t dbnce_fltr_bypass:1;
+        /** exchg_pins_override : R/W; bitpos: [5]; default: 0;
+         *  Enable software to control USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [6]; default: 0;
+         *  USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-.
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [8:7]; default: 0;
+         *  Control single-end input high threshold.
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [10:9]; default: 0;
+         *  Control single-end input low threshold.
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [11]; default: 0;
+         *  Enable software to control input  threshold.
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [12]; default: 0;
+         *  Enable software to control USB pad in pullup or pulldown mode.
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [13]; default: 0;
+         *  Control USB D+ pullup.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [14]; default: 0;
+         *  Control USB D+ pulldown.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [15]; default: 0;
+         *  Control USB D+ pullup.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [16]; default: 0;
+         *  Control USB D+ pulldown.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [17]; default: 0;
+         *  Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K.
+         */
+        uint32_t pullup_value:1;
+        /** pad_enable : R/W; bitpos: [18]; default: 0;
+         *  Enable USB pad function.
+         */
+        uint32_t pad_enable:1;
+        /** ahb_clk_force_on : R/W; bitpos: [19]; default: 1;
+         *  Force AHB clock always on.
+         */
+        uint32_t ahb_clk_force_on:1;
+        /** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
+         *  Force PHY clock always on.
+         */
+        uint32_t phy_clk_force_on:1;
+        /** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
+         *  Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
+         */
+        uint32_t phy_tx_edge_sel:1;
+        /** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
+         *  Disable the dfifo to go into low power mode. The data in dfifo will not lost.
+         */
+        uint32_t dfifo_force_pu:1;
+        uint32_t reserved_23:8;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Disable auto clock gating of CSR registers.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} usb_wrap_otg_conf_reg_t;
+
+/** Type of test_conf register
+ *  TEST relative configuration registers.
+ */
+typedef union {
+    struct {
+        /** test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable to test the USB pad.
+         */
+        uint32_t test_enable:1;
+        /** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test.
+         */
+        uint32_t test_usb_wrap_oe:1;
+        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test.
+         */
+        uint32_t test_tx_dp:1;
+        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test.
+         */
+        uint32_t test_tx_dm:1;
+        /** test_rx_rcv : RO; bitpos: [4]; default: 0;
+         *  USB differential rx value in test.
+         */
+        uint32_t test_rx_rcv:1;
+        /** test_rx_dp : RO; bitpos: [5]; default: 0;
+         *  USB D+ rx value in test.
+         */
+        uint32_t test_rx_dp:1;
+        /** test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test.
+         */
+        uint32_t test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_wrap_test_conf_reg_t;
+
+
+/** Status registers */
+/** Type of date register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 419631616;
+         *  data register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} usb_wrap_date_reg_t;
+
+
+typedef struct {
+    volatile usb_wrap_otg_conf_reg_t otg_conf;
+    volatile usb_wrap_test_conf_reg_t test_conf;
+    uint32_t reserved_008;
+    uint32_t reserved_00c;
+    uint32_t reserved_010;
+    uint32_t reserved_014;
+    uint32_t reserved_018;
+    uint32_t reserved_01c;
+    uint32_t reserved_020;
+    uint32_t reserved_024;
+    uint32_t reserved_028;
+    uint32_t reserved_02c;
+    uint32_t reserved_030;
+    uint32_t reserved_034;
+    uint32_t reserved_038;
+    uint32_t reserved_03c;
+    uint32_t reserved_040;
+    uint32_t reserved_044;
+    uint32_t reserved_048;
+    uint32_t reserved_04c;
+    uint32_t reserved_050;
+    uint32_t reserved_054;
+    uint32_t reserved_058;
+    uint32_t reserved_05c;
+    uint32_t reserved_060;
+    uint32_t reserved_064;
+    uint32_t reserved_068;
+    uint32_t reserved_06c;
+    uint32_t reserved_070;
+    uint32_t reserved_074;
+    uint32_t reserved_078;
+    uint32_t reserved_07c;
+    uint32_t reserved_080;
+    uint32_t reserved_084;
+    uint32_t reserved_088;
+    uint32_t reserved_08c;
+    uint32_t reserved_090;
+    uint32_t reserved_094;
+    uint32_t reserved_098;
+    uint32_t reserved_09c;
+    uint32_t reserved_0a0;
+    uint32_t reserved_0a4;
+    uint32_t reserved_0a8;
+    uint32_t reserved_0ac;
+    uint32_t reserved_0b0;
+    uint32_t reserved_0b4;
+    uint32_t reserved_0b8;
+    uint32_t reserved_0bc;
+    uint32_t reserved_0c0;
+    uint32_t reserved_0c4;
+    uint32_t reserved_0c8;
+    uint32_t reserved_0cc;
+    uint32_t reserved_0d0;
+    uint32_t reserved_0d4;
+    uint32_t reserved_0d8;
+    uint32_t reserved_0dc;
+    uint32_t reserved_0e0;
+    uint32_t reserved_0e4;
+    uint32_t reserved_0e8;
+    uint32_t reserved_0ec;
+    uint32_t reserved_0f0;
+    uint32_t reserved_0f4;
+    uint32_t reserved_0f8;
+    uint32_t reserved_0fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    volatile usb_wrap_date_reg_t date;
+} usb_wrap_dev_t;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_wrap_dev_t)==0x400, "Invalid USB_WRAP size");
+#endif
+
+extern usb_wrap_dev_t USB_WRAP;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s3/include/soc/world_controller_reg.h b/components/soc/esp32s3/register/soc/world_controller_reg.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/world_controller_reg.h
rename to components/soc/esp32s3/register/soc/world_controller_reg.h
diff --git a/components/soc/esp32s3/include/soc/world_controller_struct.h b/components/soc/esp32s3/register/soc/world_controller_struct.h
similarity index 100%
rename from components/soc/esp32s3/include/soc/world_controller_struct.h
rename to components/soc/esp32s3/register/soc/world_controller_struct.h
diff --git a/components/soc/esp32s3/spi_periph.c b/components/soc/esp32s3/spi_periph.c
index 91fdc873551..3675131a9b9 100644
--- a/components/soc/esp32s3/spi_periph.c
+++ b/components/soc/esp32s3/spi_periph.c
@@ -33,7 +33,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = -1,
         .irq = -1,
         .irq_dma = -1,
-        .module = -1,
         .hw = NULL,
         .func = -1,
     }, {
@@ -65,7 +64,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
         .irq = ETS_SPI2_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_SPI2_MODULE,
         .hw = &GPSPI2,
         .func = SPI2_FUNC_NUM,
     }, {
@@ -91,7 +89,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
         .spics0_iomux_pin = -1,
         .irq = ETS_SPI3_INTR_SOURCE,
         .irq_dma = -1,
-        .module = PERIPH_SPI3_MODULE,
         .hw = &GPSPI3,
         .func = -1,
     }
diff --git a/components/soc/esp32s3/usb_dwc_periph.c b/components/soc/esp32s3/usb_dwc_periph.c
index eba3eaaf60b..51386dde8b8 100644
--- a/components/soc/esp32s3/usb_dwc_periph.c
+++ b/components/soc/esp32s3/usb_dwc_periph.c
@@ -4,8 +4,79 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "soc/usb_dwc_periph.h"
+#include <stddef.h>
 #include "soc/gpio_sig_map.h"
+#include "soc/usb_periph.h"
+#include "soc/interrupts.h"
+#include "soc/usb_dwc_periph.h"
+
+/* -------------------------------- Private --------------------------------- */
+
+static const usb_fsls_serial_signal_conn_t fsls_signals = {
+    // Inputs
+    .rx_dp          = USB_EXTPHY_VP_IDX,
+    .rx_dm          = USB_EXTPHY_VM_IDX,
+    .rx_rcv         = USB_EXTPHY_RCV_IDX,
+    // Outputs
+    .suspend_n      = USB_EXTPHY_SUSPND_IDX,
+    .tx_enable_n    = USB_EXTPHY_OEN_IDX,
+    .tx_dp          = USB_EXTPHY_VPO_IDX,
+    .tx_dm          = USB_EXTPHY_VMO_IDX,
+    .fs_edge_sel    = USB_EXTPHY_SPEED_IDX,
+};
+
+static const usb_utmi_otg_signal_conn_t otg_signals = {
+    // Inputs
+    .iddig          = USB_OTG_IDDIG_IN_IDX,
+    .avalid         = USB_OTG_AVALID_IN_IDX,
+    .bvalid         = USB_SRP_BVALID_IN_IDX,
+    .vbusvalid      = USB_OTG_VBUSVALID_IN_IDX,
+    .sessend        = USB_SRP_SESSEND_IN_IDX,
+    // Outputs
+    .idpullup       = USB_OTG_IDPULLUP_IDX,
+    .dppulldown     = USB_OTG_DPPULLDOWN_IDX,
+    .dmpulldown     = USB_OTG_DMPULLDOWN_IDX,
+    .drvvbus        = USB_OTG_DRVVBUS_IDX,
+    .chrgvbus       = USB_SRP_CHRGVBUS_IDX,
+    .dischrgvbus    = USB_SRP_DISCHRGVBUS_IDX,
+};
+
+/* --------------------------------- Public --------------------------------- */
+
+const usb_dwc_info_t usb_dwc_info = {
+    .controllers = {
+        [0] = {
+            .fsls_signals = &fsls_signals,
+            .otg_signals = &otg_signals,
+            .irq = ETS_USB_INTR_SOURCE,
+            .irq_2nd_cpu = -1,
+        },
+    },
+};
+
+/* ------------------------------- Deprecated ------------------------------- */
+
+/*
+Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
+PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
+matrix. Thus, this mapping of signals to IO pins is meaningless.
+
+Todo: Remove in IDF v6.0 (IDF-9029)
+*/
+const usb_iopin_dsc_t usb_periph_iopins[] = {
+    {USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
+    {USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
+    {USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
+    {USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
+    {USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
+    {USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
+    {GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0},     //connected connector is mini-B
+    //connected connector is mini-B
+    {GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0},    //HIGH to force USB device mode
+    {GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
+    {GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
+    {-1, -1, 0, 0}
+};
 
 /*
  Bunch of constants for USB peripheral: GPIO signals
diff --git a/components/soc/esp32s3/usb_periph.c b/components/soc/esp32s3/usb_periph.c
deleted file mode 100644
index a3fda7193e3..00000000000
--- a/components/soc/esp32s3/usb_periph.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "soc/soc_caps.h"
-#include "soc/usb_periph.h"
-
-/*
-Note: These IO pins are deprecated. When connecting USB OTG to an external FSLS
-PHY, the FSLS Serial Interface signals can be routed to any GPIO via the GPIO
-matrix. Thus, this mapping of signals to IO pins is meaningless.
-
-Todo: Remove in IDF v6.0 (IDF-9029)
-*/
-const usb_iopin_dsc_t usb_periph_iopins[] = {
-    {USBPHY_VP_NUM, USB_EXTPHY_VP_IDX, 0, 1},
-    {USBPHY_VM_NUM, USB_EXTPHY_VM_IDX, 0, 1},
-    {USBPHY_RCV_NUM, USB_EXTPHY_RCV_IDX, 0, 1},
-    {USBPHY_OEN_NUM, USB_EXTPHY_OEN_IDX, 1, 1},
-    {USBPHY_VPO_NUM, USB_EXTPHY_VPO_IDX, 1, 1},
-    {USBPHY_VMO_NUM, USB_EXTPHY_VMO_IDX, 1, 1},
-    {GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, 0, 0},     //connected connector is mini-B
-    //connected connector is mini-B
-    {GPIO_MATRIX_CONST_ONE_INPUT, USB_SRP_BVALID_IN_IDX, 0, 0},    //HIGH to force USB device mode
-    {GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, 0, 0}, //receiving a valid Vbus from host
-    {GPIO_MATRIX_CONST_ZERO_INPUT, USB_OTG_AVALID_IN_IDX, 0, 0},
-    {-1, -1, 0, 0}
-};
diff --git a/components/soc/include/soc/etm_periph.h b/components/soc/include/soc/etm_periph.h
new file mode 100644
index 00000000000..f7168ff7173
--- /dev/null
+++ b/components/soc/include/soc/etm_periph.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "soc/soc_caps.h"
+#include "soc/regdma.h"
+
+#if SOC_ETM_SUPPORT_SLEEP_RETENTION
+#include "soc/retention_periph_defs.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if SOC_ETM_SUPPORT_SLEEP_RETENTION
+typedef struct {
+    periph_retention_module_t module;
+    const regdma_entries_config_t *regdma_entry_array;
+    uint32_t array_size;
+} etm_reg_retention_info_t;
+
+extern const etm_reg_retention_info_t etm_reg_retention_info[SOC_ETM_GROUPS];
+#endif // SOC_ETM_SUPPORT_SLEEP_RETENTION
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/include/soc/gdma_periph.h b/components/soc/include/soc/gdma_periph.h
index 4da8b042b2e..478aab39a90 100644
--- a/components/soc/include/soc/gdma_periph.h
+++ b/components/soc/include/soc/gdma_periph.h
@@ -44,7 +44,7 @@ extern const gdma_signal_conn_t gdma_periph_signals;
 typedef struct {
     const regdma_entries_config_t *link_list;
     uint32_t link_num;
-    periph_retention_module_t module_id;
+    const periph_retention_module_t module_id;
 } gdma_chx_reg_ctx_link_t;
 
 extern const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX];
diff --git a/components/soc/include/soc/i2c_periph.h b/components/soc/include/soc/i2c_periph.h
index 408da3afc49..c1fbb0fbc8d 100644
--- a/components/soc/include/soc/i2c_periph.h
+++ b/components/soc/include/soc/i2c_periph.h
@@ -11,6 +11,9 @@
 #if SOC_I2C_SUPPORTED
 #include "soc/regdma.h"
 #include "soc/interrupts.h"
+#if SOC_I2C_SUPPORT_SLEEP_RETENTION
+#include "soc/retention_periph_defs.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -31,6 +34,7 @@ extern const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM];
 typedef struct {
     const regdma_entries_config_t *link_list;
     uint32_t link_num;
+    periph_retention_module_t module_id;
 } i2c_reg_ctx_link_t;
 
 extern const i2c_reg_ctx_link_t i2c_regs_retention[SOC_HP_I2C_NUM];
diff --git a/components/soc/include/soc/ledc_periph.h b/components/soc/include/soc/ledc_periph.h
index d90f22e7931..8ed332010ba 100644
--- a/components/soc/include/soc/ledc_periph.h
+++ b/components/soc/include/soc/ledc_periph.h
@@ -1,21 +1,18 @@
-// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
+
 #include "soc/soc_caps.h"
 #include "soc/ledc_reg.h"
 #include "soc/ledc_struct.h"
+#if SOC_PAU_SUPPORTED
+#include "soc/regdma.h"
+#include "soc/retention_periph_defs.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -34,6 +31,33 @@ extern const ledc_signal_conn_t ledc_periph_signal[2];
 extern const ledc_signal_conn_t ledc_periph_signal[1];
 #endif
 
+#if SOC_PAU_SUPPORTED
+
+#if SOC_LIGHT_SLEEP_SUPPORTED
+#if SOC_PHY_SUPPORTED
+#define LEDC_RETENTION_ENTRY        (ENTRY(0) | ENTRY(2))
+#else
+#define LEDC_RETENTION_ENTRY        (ENTRY(0))
+#endif
+#else // !SOC_LIGHT_SLEEP_SUPPORTED
+#define LEDC_RETENTION_ENTRY        REGDMA_SW_TRIGGER_ENTRY
+#endif
+
+typedef struct {
+    const regdma_entries_config_t *regdma_entry_array;
+    uint32_t array_size;
+} ledc_sub_reg_retention_info_t;
+
+typedef struct {
+    ledc_sub_reg_retention_info_t common;
+    ledc_sub_reg_retention_info_t timer[SOC_LEDC_TIMER_NUM];
+    ledc_sub_reg_retention_info_t channel[SOC_LEDC_CHANNEL_NUM];
+    const periph_retention_module_t module_id;
+} ledc_reg_retention_info_t;
+
+extern const ledc_reg_retention_info_t ledc_reg_retention_info;
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/include/soc/mcpwm_periph.h b/components/soc/include/soc/mcpwm_periph.h
index 9ce4e065922..12309f208fc 100644
--- a/components/soc/include/soc/mcpwm_periph.h
+++ b/components/soc/include/soc/mcpwm_periph.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,10 @@
 #include <stdint.h>
 #include "soc/soc_caps.h"
 #include "soc/periph_defs.h"
+#include "soc/regdma.h"
+#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+#include "soc/retention_periph_defs.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -37,6 +41,17 @@ typedef struct {
 } mcpwm_signal_conn_t;
 
 extern const mcpwm_signal_conn_t mcpwm_periph_signals;
+
+#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+typedef struct {
+    const regdma_entries_config_t *regdma_entry_array;
+    uint32_t array_size;
+    const periph_retention_module_t retention_module;
+} mcpwm_reg_retention_info_t;
+
+extern const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[SOC_MCPWM_GROUPS];
+#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+
 #endif // SOC_MCPWM_SUPPORTED
 
 #ifdef __cplusplus
diff --git a/components/soc/include/soc/parlio_periph.h b/components/soc/include/soc/parlio_periph.h
index c9781a048f5..3bb4de72b02 100644
--- a/components/soc/include/soc/parlio_periph.h
+++ b/components/soc/include/soc/parlio_periph.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +13,10 @@
 #include "soc/parl_io_reg.h"
 #include "soc/parl_io_struct.h"
 #endif
+#include "soc/regdma.h"
+#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+#include "soc/retention_periph_defs.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -39,6 +43,16 @@ typedef struct {
 
 extern const parlio_signal_conn_t parlio_periph_signals;
 
+#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+typedef struct {
+    const periph_retention_module_t retention_module;
+    const regdma_entries_config_t *regdma_entry_array;
+    uint32_t array_size;
+} parlio_reg_retention_info_t;
+
+extern const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS];
+#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION
+
 #endif
 
 #ifdef __cplusplus
diff --git a/components/soc/include/soc/pcnt_periph.h b/components/soc/include/soc/pcnt_periph.h
index e7d8818b090..a060af597fe 100644
--- a/components/soc/include/soc/pcnt_periph.h
+++ b/components/soc/include/soc/pcnt_periph.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,10 @@
 #include <stdint.h>
 #include "soc/soc_caps.h"
 #include "soc/periph_defs.h"
+#include "soc/regdma.h"
+#if SOC_PCNT_SUPPORT_SLEEP_RETENTION
+#include "soc/retention_periph_defs.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -31,6 +35,16 @@ typedef struct {
 
 extern const pcnt_signal_conn_t pcnt_periph_signals;
 
+#if SOC_PCNT_SUPPORT_SLEEP_RETENTION
+typedef struct {
+    const periph_retention_module_t retention_module;
+    const regdma_entries_config_t *regdma_entry_array;
+    uint32_t array_size;
+} pcnt_reg_retention_info_t;
+
+extern const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS];
+#endif // SOC_PCNT_SUPPORT_SLEEP_RETENTION
+
 #endif // SOC_PCNT_SUPPORTED
 
 #ifdef __cplusplus
diff --git a/components/soc/include/soc/regdma.h b/components/soc/include/soc/regdma.h
index c3c62081f00..80b7cf301ff 100644
--- a/components/soc/include/soc/regdma.h
+++ b/components/soc/include/soc/regdma.h
@@ -54,6 +54,14 @@ extern "C" {
 #define REGDMA_TG0_TIMER_LINK(_pri)         ((0x1C << 8) | _pri)
 #define REGDMA_TG1_TIMER_LINK(_pri)         ((0x1D << 8) | _pri)
 #define REGDMA_I2S_LINK(_pri)               ((0x1E << 8) | _pri)
+#define REGDMA_ETM_LINK(_pri)               ((0x1F << 8) | _pri)
+#define REGDMA_TSENS_LINK(_pri)             ((0x20 << 8) | _pri)
+#define REGDMA_TWAI_LINK(_pri)              ((0x21 << 8) | _pri)
+#define REGDMA_PARLIO_LINK(_pri)            ((0x22 << 8) | _pri)
+#define REGDMA_GPSPI_LINK(_pri)             ((0x23 << 8) | _pri)
+#define REGDMA_LEDC_LINK(_pri)              ((0x24 << 8) | _pri)
+#define REGDMA_PCNT_LINK(_pri)              ((0x25 << 8) | _pri)
+#define REGDMA_MCPWM_LINK(_pri)             ((0x26 << 8) | _pri)
 #define REGDMA_MODEM_FE_LINK(_pri)          ((0xFF << 8) | _pri)
 
 #define REGDMA_LINK_PRI_SYS_CLK                 REGDMA_LINK_PRI_0
@@ -68,10 +76,18 @@ extern "C" {
 #define REGDMA_LINK_PRI_IEEE802154              REGDMA_LINK_PRI_GENERAL_PERIPH
 #define REGDMA_LINK_PRI_GDMA                    REGDMA_LINK_PRI_GENERAL_PERIPH
 #define REGDMA_LINK_PRI_RMT                     REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_ETM                     REGDMA_LINK_PRI_GENERAL_PERIPH
 #define REGDMA_LINK_PRI_GPTIMER                 REGDMA_LINK_PRI_GENERAL_PERIPH
 #define REGDMA_LINK_PRI_I2C                     REGDMA_LINK_PRI_GENERAL_PERIPH
 #define REGDMA_LINK_PRI_I2S                     REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_PARLIO                  REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_PCNT                    REGDMA_LINK_PRI_GENERAL_PERIPH
 #define REGDMA_LINK_PRI_UART                    REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_TEMPERATURE_SENSOR      REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_TWAI                    REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_GPSPI                   REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_LEDC                    REGDMA_LINK_PRI_GENERAL_PERIPH
+#define REGDMA_LINK_PRI_MCPWM                   REGDMA_LINK_PRI_GENERAL_PERIPH
 
 typedef enum {
     REGDMA_LINK_PRI_0 = 0,
diff --git a/components/soc/include/soc/rmt_periph.h b/components/soc/include/soc/rmt_periph.h
index a85b5930a22..bb35a67b863 100644
--- a/components/soc/include/soc/rmt_periph.h
+++ b/components/soc/include/soc/rmt_periph.h
@@ -10,6 +10,10 @@
 #include "soc/periph_defs.h"
 #include "soc/regdma.h"
 
+#if SOC_RMT_SUPPORT_SLEEP_RETENTION
+#include "soc/retention_periph_defs.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -32,6 +36,7 @@ extern const rmt_signal_conn_t rmt_periph_signals;
 
 #if SOC_RMT_SUPPORT_SLEEP_RETENTION
 typedef struct {
+    periph_retention_module_t module;
     const regdma_entries_config_t *regdma_entry_array;
     uint32_t array_size;
 } rmt_reg_retention_info_t;
diff --git a/components/soc/include/soc/spi_periph.h b/components/soc/include/soc/spi_periph.h
index 7a85aafa650..8e653edf0c3 100644
--- a/components/soc/include/soc/spi_periph.h
+++ b/components/soc/include/soc/spi_periph.h
@@ -9,13 +9,17 @@
 #include <stdint.h>
 #include "sdkconfig.h"
 #include "soc/soc.h"
-#include "soc/periph_defs.h"
+#include "soc/soc_caps.h"
+#include "soc/spi_pins.h"
+#if SOC_PAU_SUPPORTED
+#include "soc/regdma.h"
+#include "soc/retention_periph_defs.h"
+#endif
 
 //include soc related (generated) definitions
-#include "soc/soc_caps.h"
+#include "soc/interrupts.h"
 #include "soc/spi_reg.h"
 #include "soc/spi_struct.h"
-#include "soc/spi_pins.h"
 #include "soc/gpio_sig_map.h"
 #if SOC_MEMSPI_IS_INDEPENDENT
 #include "soc/spi_mem_struct.h"
@@ -71,13 +75,22 @@ typedef struct {
     const uint8_t spics0_iomux_pin;
     const uint8_t irq;              //irq source for interrupt mux
     const uint8_t irq_dma;          //dma irq source for interrupt mux
-    const periph_module_t module;   //peripheral module, for enabling clock etc
-    const int func;             //function number for IOMUX
-    spi_dev_t *hw;              //Pointer to the hardware registers
+    const int func;                 //function number for IOMUX
+    spi_dev_t *hw;                  //Pointer to the hardware registers
 } spi_signal_conn_t;
 
 extern const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM];
 
+#if SOC_PAU_SUPPORTED
+typedef struct {
+    const periph_retention_module_t module_id;
+    const regdma_entries_config_t *entry_array;
+    uint32_t array_size;
+} spi_reg_retention_info_t;
+
+extern const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1];   // -1 to except mspi
+#endif  // SOC_PAU_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/include/soc/temperature_sensor_periph.h b/components/soc/include/soc/temperature_sensor_periph.h
index 73742819350..d5273925541 100644
--- a/components/soc/include/soc/temperature_sensor_periph.h
+++ b/components/soc/include/soc/temperature_sensor_periph.h
@@ -1,11 +1,16 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+#include "soc/regdma.h"
+#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+#include "soc/retention_periph_defs.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -22,6 +27,16 @@ typedef struct {
 
 extern const temperature_sensor_attribute_t temperature_sensor_attributes[TEMPERATURE_SENSOR_ATTR_RANGE_NUM];
 
+#if SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+typedef struct {
+    const regdma_entries_config_t *link_list;
+    uint32_t link_num;
+    periph_retention_module_t module_id;
+} temperature_sensor_reg_ctx_link_t;
+
+extern const temperature_sensor_reg_ctx_link_t temperature_sensor_regs_retention;
+#endif // SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/include/soc/twai_periph.h b/components/soc/include/soc/twai_periph.h
index 72a37210a2b..89ca029f02c 100644
--- a/components/soc/include/soc/twai_periph.h
+++ b/components/soc/include/soc/twai_periph.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,10 @@
 #include <stdint.h>
 #include "soc/soc_caps.h"
 #include "soc/periph_defs.h"
+#if SOC_PAU_SUPPORTED
+#include "soc/regdma.h"
+#include "soc/retention_periph_defs.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -30,6 +34,16 @@ typedef struct {
 
 extern const twai_controller_signal_conn_t twai_controller_periph_signals;
 
+#if SOC_PAU_SUPPORTED
+typedef struct {
+    const periph_retention_module_t module_id;
+    const regdma_entries_config_t *entry_array;
+    uint32_t array_size;
+} twai_reg_retention_info_t;
+
+extern const twai_reg_retention_info_t twai_reg_retention_info[SOC_TWAI_CONTROLLER_NUM];
+#endif  // SOC_PAU_SUPPORTED
+
 #endif // SOC_TWAI_SUPPORTED
 
 #ifdef __cplusplus
diff --git a/components/soc/include/soc/uart_periph.h b/components/soc/include/soc/uart_periph.h
index 2c0681e8dad..ba73db13095 100644
--- a/components/soc/include/soc/uart_periph.h
+++ b/components/soc/include/soc/uart_periph.h
@@ -12,7 +12,10 @@
 #include "soc/uart_pins.h"
 #include "soc/uart_struct.h"
 #include "soc/uart_reg.h"
+#if SOC_PAU_SUPPORTED
 #include "soc/regdma.h"
+#include "soc/retention_periph_defs.h"
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -50,8 +53,9 @@ typedef struct {
 
 extern const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM];
 
-#if SOC_UART_SUPPORT_SLEEP_RETENTION
+#if SOC_UART_SUPPORT_SLEEP_RETENTION && SOC_PAU_SUPPORTED
 typedef struct {
+    const periph_retention_module_t module;
     const regdma_entries_config_t *regdma_entry_array;
     uint32_t array_size;
 } uart_reg_retention_info_t;
diff --git a/components/soc/include/soc/usb_dwc_periph.h b/components/soc/include/soc/usb_dwc_periph.h
index d13286aa1dc..8e1832c2ced 100644
--- a/components/soc/include/soc/usb_dwc_periph.h
+++ b/components/soc/include/soc/usb_dwc_periph.h
@@ -1,18 +1,93 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
+
 #include <stdint.h>
+#include <stdbool.h>
+#include "soc/soc_pins.h"
 #include "soc/soc_caps.h"
 #include "soc/periph_defs.h"
+#include "soc/gpio_sig_map.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#if SOC_USB_OTG_SUPPORTED
+
+/* ---------------------------------- Types --------------------------------- */
+
+/**
+ * @brief USB PHY FSLS Serial Interface Signals
+ *
+ * Structure to store the GPIO matrix signal indexes for a USB PHY FSLS Serial
+ * interface's signals.
+ *
+ * @note Refer to section "2.2.1.13 FsLsSerialMode" of the UTMI+ for more
+ *       details regarding the FSLS Serial Interface.
+ */
+typedef struct {
+    // Inputs
+    int rx_dp;
+    int rx_dm;
+    int rx_rcv;
+    // Outputs
+    int suspend_n;
+    int tx_enable_n;
+    int tx_dp;
+    int tx_dm;
+    int fs_edge_sel;
+} usb_fsls_serial_signal_conn_t;
+
+/**
+ * @brief USB PHY UTMI OTG Interface Signal Index Type
+ *
+ * Structure to store the GPIO matrix signal indexes for a UTMI PHY interface's
+ * OTG signals.
+ */
+typedef struct {
+    // Inputs
+    int iddig;
+    int avalid;
+    int bvalid;
+    int vbusvalid;
+    int sessend;
+    // Outputs
+    int idpullup;
+    int dppulldown;
+    int dmpulldown;
+    int drvvbus;
+    int chrgvbus;
+    int dischrgvbus;
+} usb_utmi_otg_signal_conn_t;
+
+/**
+ * @brief USB Controller Information
+ *
+ * Structure to store information for all USB-DWC instances
+ */
+typedef struct {
+    struct {
+        const usb_fsls_serial_signal_conn_t * const fsls_signals;   // Must be set if external PHY is supported by controller
+        const usb_utmi_otg_signal_conn_t * const otg_signals;
+        const int irq;
+        const int irq_2nd_cpu;  // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported
+    } controllers [SOC_USB_OTG_PERIPH_NUM];
+} usb_dwc_info_t;
+
+extern const usb_dwc_info_t usb_dwc_info;
+
+#endif // SOC_USB_OTG_SUPPORTED
+
+/* ------------------------------- Deprecated ------------------------------- */
+/* Todo: Remove in ESP-IDF v6.0 (IDF-9052) */
+
+#if SOC_USB_OTG_SUPPORTED
+
 /*
  Stores a bunch of USB-peripheral data.
 */
@@ -41,6 +116,8 @@ typedef struct {
 
 extern const usb_phy_signal_conn_t usb_otg_periph_signal;
 
+#endif // SOC_USB_OTG_SUPPORTED
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt
index b71f6e71cfd..5e85a5c94f2 100644
--- a/components/spi_flash/CMakeLists.txt
+++ b/components/spi_flash/CMakeLists.txt
@@ -1,4 +1,6 @@
 idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(non_os_build NON_OS_BUILD)
+
 if(${target} STREQUAL "linux")
     idf_component_register(SRCS "linux/spi_flash_linux.c"
                           "linux/cache_utils.c"
@@ -8,7 +10,7 @@ if(${target} STREQUAL "linux")
     return()
 endif()
 
-if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
+if(non_os_build OR CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
     set(srcs "spi_flash_wrap.c")
     set(priv_requires bootloader_support soc)
 else()
@@ -70,7 +72,7 @@ if(CMAKE_C_COMPILER_ID MATCHES "GNU")
         " -fno-inline-small-functions -fno-inline-functions-called-once")
 endif()
 
-if(NOT BOOTLOADER_BUILD AND NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
+if(NOT non_os_build AND NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
     if(CONFIG_SPIRAM)
         # [refactor-todo]: requires "esp_psram" for few MMU usages in `flash_mmap.c`
         # will be replaced with MMU requirements
diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig
index 367b1376571..80a48a1b7e4 100644
--- a/components/spi_flash/Kconfig
+++ b/components/spi_flash/Kconfig
@@ -109,6 +109,17 @@ menu "Main Flash configuration"
                 This config is used for setting Tsus parameter. Tsus means CS# high to next command after
                 suspend. You can refer to the chapter of AC CHARACTERISTICS of flash datasheet.
 
+        config SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND
+            bool "Enable XMC-C series flash chip suspend feature anyway"
+            default n
+            help
+                XMC-C series is regarded as not qualified for the Suspend feature, since its specification
+                has a tRS >= 1ms restriction. We strongly do not suggest using it for the Suspend feature.
+                However, if your product in field has enabled this feature, you may still enable this
+                config option to keep the legacy behavior.
+
+                For new users, DO NOT enable this config.
+
     endmenu
 endmenu
 
diff --git a/components/spi_flash/flash_brownout_hook.c b/components/spi_flash/flash_brownout_hook.c
index 762b54028df..7d070c0b19b 100644
--- a/components/spi_flash/flash_brownout_hook.c
+++ b/components/spi_flash/flash_brownout_hook.c
@@ -20,7 +20,7 @@ void spi_flash_needs_reset_check(void)
 {
     // Currently only XMC is suggested to reset when brownout
 #if CONFIG_SPI_FLASH_BROWNOUT_RESET_XMC
-    if ((g_rom_flashchip.device_id >> 16) == 0x20 || (g_rom_flashchip.device_id >> 16) == 0x46) {
+    if ((g_rom_flashchip.device_id >> 16) == 0x20) {
         flash_brownout_needs_reset = true;
     }
 #endif
diff --git a/components/spi_flash/include/spi_flash/spi_flash_defs.h b/components/spi_flash/include/spi_flash/spi_flash_defs.h
index 08247c619be..7a8bf432f78 100644
--- a/components/spi_flash/include/spi_flash/spi_flash_defs.h
+++ b/components/spi_flash/include/spi_flash/spi_flash_defs.h
@@ -53,6 +53,8 @@
 #define CMD_RST_EN      0x66
 #define CMD_RST_DEV     0x99
 
+#define CMD_RDSFDP     0x5A /* Read the SFDP of the flash */
+
 #define SPI_FLASH_DIO_ADDR_BITLEN       24
 #define SPI_FLASH_DIO_DUMMY_BITLEN      4
 #define SPI_FLASH_QIO_ADDR_BITLEN       24
diff --git a/components/spi_flash/spi_flash_chip_generic.c b/components/spi_flash/spi_flash_chip_generic.c
index 33bd1c30291..8233eaf174b 100644
--- a/components/spi_flash/spi_flash_chip_generic.c
+++ b/components/spi_flash/spi_flash_chip_generic.c
@@ -599,11 +599,37 @@ spi_flash_caps_t spi_flash_chip_generic_get_caps(esp_flash_t *chip)
     // 32M-bits address support
 
     // flash suspend support
-    // XMC support suspend
-    if (chip->chip_id >> 16 == 0x20 || chip->chip_id >> 16 == 0x46) {
+    // XMC-D support suspend
+    if (chip->chip_id >> 16 == 0x46) {
         caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND;
     }
 
+    // XMC-D support suspend (some D series flash chip begin with 0x20, difference checked by SFDP)
+    if (chip->chip_id >> 16 == 0x20) {
+        uint8_t data = 0;
+        spi_flash_trans_t t = {
+            .command = CMD_RDSFDP,
+            .address_bitlen = 24,
+            .address = 0x32,
+            .mosi_len = 0,
+            .mosi_data = 0,
+            .miso_len = 1,
+            .miso_data = &data,
+            .dummy_bitlen = 8,
+        };
+        chip->host->driver->common_command(chip->host, &t);
+        if((data & 0x8) == 0x8) {
+            caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND;
+        }
+    }
+
+#if CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND
+    // XMC-C suspend has big risk. But can enable this anyway.
+    if (chip->chip_id >> 16 == 0x20) {
+        caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND;
+    }
+#endif
+
     // FM support suspend
     if (chip->chip_id >> 16 == 0xa1) {
         caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND;
diff --git a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
index 032c053adda..b75e3b7eafa 100644
--- a/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
+++ b/components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
@@ -595,7 +595,11 @@ TEST_CASE_MULTI_FLASH_IGNORE("Test esp_flash_write can toggle QE bit", test_togg
 #endif //CONFIG_ESPTOOLPY_OCT_FLASH
 
 // This table could be chip specific in the future.
+#if CONFIG_IDF_TARGET_ESP32C2
+uint8_t flash_frequency_table[5] = {5, 10, 20, 40};
+#else
 uint8_t flash_frequency_table[6] = {5, 10, 20, 26, 40, 80};
+#endif
 #define TEST_FLASH_SPEED_MIN 5
 void test_permutations_part(const flashtest_config_t* config, esp_partition_t* part, void* source_buf, size_t length)
 {
diff --git a/components/spi_flash/test_apps/esp_flash_stress/pytest_esp_flash_stress.py b/components/spi_flash/test_apps/esp_flash_stress/pytest_esp_flash_stress.py
index 1e855dbcb97..686f4de6955 100644
--- a/components/spi_flash/test_apps/esp_flash_stress/pytest_esp_flash_stress.py
+++ b/components/spi_flash/test_apps/esp_flash_stress/pytest_esp_flash_stress.py
@@ -52,5 +52,5 @@ def test_esp_flash_stress_rom_xip_psram(dut: Dut) -> None:
     ],
     indirect=True,
 )
-def test_flash_auto_suspend(dut: Dut) -> None:
+def test_flash_auto_suspend_stress(dut: Dut) -> None:
     dut.run_all_single_board_cases()
diff --git a/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c b/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c
index 6ebfa46b523..0277dd5ebcd 100644
--- a/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c
+++ b/components/spi_flash/test_apps/flash_encryption/main/test_flash_encryption.c
@@ -273,6 +273,33 @@ TEST_CASE("test read & write encrypted data(32 bytes alianed address)", "[flash_
 
     free(cmp_normal_buf);
     free(cmp_encrypt_buf);
+
+    uint32_t size;
+    esp_flash_get_physical_size(NULL, &size);
+
+    if (size > 0x1000000) {
+        start = 0x1030000;
+        TEST_ESP_OK(esp_flash_erase_region(NULL, start, SPI_FLASH_SEC_SIZE));
+        start = (start + 31) & (~31); // round up to 32 byte boundary
+        printf("Test data partition @ 0x%" PRIx32 "\n", (uint32_t) start);
+        ESP_LOG_BUFFER_HEXDUMP(TAG, plainttext_data, sizeof(plainttext_data), ESP_LOG_INFO);
+        printf("Encrypted writing......\n");
+        TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, plainttext_data, sizeof(plainttext_data)));
+
+        cmp_encrypt_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+        printf("Encrypted reading......\n");
+        TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, cmp_encrypt_buf, SPI_FLASH_SEC_SIZE));
+        ESP_LOG_BUFFER_HEXDUMP(TAG, cmp_encrypt_buf, sizeof(plainttext_data), ESP_LOG_INFO);
+        TEST_ASSERT_EQUAL_HEX8_ARRAY(plainttext_data, cmp_encrypt_buf, sizeof(plainttext_data));
+
+        cmp_normal_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+        TEST_ESP_OK(esp_flash_read(NULL, cmp_normal_buf, start, SPI_FLASH_SEC_SIZE));
+        printf("Normal read(esp_flash_read)......\n");
+        ESP_LOG_BUFFER_HEXDUMP(TAG, cmp_normal_buf, sizeof(plainttext_data), ESP_LOG_INFO);
+
+        free(cmp_normal_buf);
+        free(cmp_encrypt_buf);
+    }
 }
 
 TEST_CASE("test read & write encrypted data(16 bytes alianed but 32 bytes unaligned)", "[flash_encryption]")
@@ -305,6 +332,38 @@ TEST_CASE("test read & write encrypted data(16 bytes alianed but 32 bytes unalig
 
     free(cmp_normal_buf);
     free(cmp_encrypt_buf);
+
+    uint32_t size;
+    esp_flash_get_physical_size(NULL, &size);
+    if (size > 0x1000000) {
+        start = 0x1030000;
+        TEST_ESP_OK(esp_flash_erase_region(NULL, start, SPI_FLASH_SEC_SIZE));
+        do {
+            start++;
+        } while ((start % 16) != 0);
+
+        if (start % 32 == 0) {
+            start += 16;
+        }
+        printf("Test data partition @ 0x%" PRIx32 "\n", (uint32_t) start);
+        ESP_LOG_BUFFER_HEXDUMP(TAG, plainttext_data, sizeof(plainttext_data), ESP_LOG_INFO);
+        printf("Encrypted writing......\n");
+        TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, plainttext_data, sizeof(plainttext_data)));
+
+        cmp_encrypt_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+        printf("Encrypted reading......\n");
+        TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, cmp_encrypt_buf, SPI_FLASH_SEC_SIZE));
+        ESP_LOG_BUFFER_HEXDUMP(TAG, cmp_encrypt_buf, sizeof(plainttext_data), ESP_LOG_INFO);
+        TEST_ASSERT_EQUAL_HEX8_ARRAY(plainttext_data, cmp_encrypt_buf, sizeof(plainttext_data));
+
+        cmp_normal_buf = heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_32BIT | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+        TEST_ESP_OK(esp_flash_read(NULL, cmp_normal_buf, start, SPI_FLASH_SEC_SIZE));
+        printf("Normal read(esp_flash_read)......\n");
+        ESP_LOG_BUFFER_HEXDUMP(TAG, cmp_normal_buf, sizeof(plainttext_data), ESP_LOG_INFO);
+
+        free(cmp_normal_buf);
+        free(cmp_encrypt_buf);
+    }
 }
 
 static const uint8_t large_const_buffer[16432] = {
@@ -338,6 +397,27 @@ TEST_CASE("test read & write encrypted data with large buffer(n*64+32+16)", "[fl
     TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, buf, sizeof(large_const_buffer)));
     TEST_ASSERT_EQUAL_HEX8_ARRAY(buf, large_const_buffer, sizeof(large_const_buffer));
     free(buf);
+
+    uint32_t size;
+    esp_flash_get_physical_size(NULL, &size);
+
+    if (size > 0x1000000) {
+        start = 0x1030000;
+        printf("Test data partition @ 0x%" PRIx32 "\n", (uint32_t) start);
+        TEST_ESP_OK(esp_flash_erase_region(NULL, start, 5 * 4096));
+        printf("Encrypted writing......\n");
+
+        TEST_ESP_OK(ccomp_timer_start());
+        TEST_ESP_OK(esp_flash_write_encrypted(NULL, start, large_const_buffer, sizeof(large_const_buffer)));
+        write_time = ccomp_timer_stop();
+        IDF_LOG_PERFORMANCE(TAG, "Writing speed: %.2f us/KB", (double)(write_time/sizeof(large_const_buffer))*1024);
+
+        buf = (uint8_t*)heap_caps_malloc(sizeof(large_const_buffer), MALLOC_CAP_8BIT);
+
+        TEST_ESP_OK(esp_flash_read_encrypted(NULL, start, buf, sizeof(large_const_buffer)));
+        TEST_ASSERT_EQUAL_HEX8_ARRAY(buf, large_const_buffer, sizeof(large_const_buffer));
+        free(buf);
+    }
 }
 
 static DRAM_ATTR const uint8_t large_const_buffer_dram[16432] = {
diff --git a/components/spi_flash/test_apps/flash_encryption/sdkconfig.ci.release_f8r8 b/components/spi_flash/test_apps/flash_encryption/sdkconfig.ci.release_f8r8
index b31f5907ca3..6fab53cf3ad 100644
--- a/components/spi_flash/test_apps/flash_encryption/sdkconfig.ci.release_f8r8
+++ b/components/spi_flash/test_apps/flash_encryption/sdkconfig.ci.release_f8r8
@@ -18,3 +18,4 @@ CONFIG_SPIRAM_MODE_OCT=y
 CONFIG_SPIRAM_TYPE_AUTO=y
 CONFIG_ESPTOOLPY_OCT_FLASH=y
 CONFIG_ESPTOOLPY_FLASHMODE_OPI=y
+CONFIG_ESPTOOLPY_FLASHSIZE_32MB=y
diff --git a/components/spiffs/host_test/main/host_test_spiffs.c b/components/spiffs/host_test/main/host_test_spiffs.c
index 4fcfce13c1f..8a63c1316ac 100644
--- a/components/spiffs/host_test/main/host_test_spiffs.c
+++ b/components/spiffs/host_test/main/host_test_spiffs.c
@@ -281,29 +281,27 @@ TEST(spiffs, erase_check)
     init_spiffs(&fs, 5);
 
 
-    for (int boot_iter = 0; boot_iter <= 10000; ++boot_iter) {
-        for (int write_iter = 0; write_iter < 1000; ++write_iter) {
-            spiffs_file f = SPIFFS_open(&fs, "/test", SPIFFS_CREAT | SPIFFS_TRUNC | SPIFFS_RDWR, 0);
-            if (f < 0) {
-                fprintf(stderr, "Failed to open file\n");
+    for (int write_iter = 0; write_iter < 100; ++write_iter) {
+        spiffs_file f = SPIFFS_open(&fs, "/test", SPIFFS_CREAT | SPIFFS_TRUNC | SPIFFS_RDWR, 0);
+        if (f < 0) {
+            fprintf(stderr, "Failed to open file\n");
 #if !CONFIG_ESP_PARTITION_ERASE_CHECK
-                TEST_FAIL();
+            TEST_FAIL();
 #endif
-                return;
-            }
-            const int data_sz = 7 * 1024;
-            char data[data_sz];
-            memset(data, 0x55, data_sz);
-            int cb = SPIFFS_write(&fs, f, data, data_sz);
-            if (cb != data_sz) {
-                fprintf(stderr, "Failed to write file\n");
-                TEST_FAIL();
-            }
-            int rc = SPIFFS_close(&fs, f);
-            if (rc < 0) {
-                fprintf(stderr, "Failed to close file\n");
-                TEST_FAIL();
-            }
+            return;
+        }
+        const int data_sz = 7 * 1024;
+        char data[data_sz];
+        memset(data, 0x55, data_sz);
+        int cb = SPIFFS_write(&fs, f, data, data_sz);
+        if (cb != data_sz) {
+            fprintf(stderr, "Failed to write file\n");
+            TEST_FAIL();
+        }
+        int rc = SPIFFS_close(&fs, f);
+        if (rc < 0) {
+            fprintf(stderr, "Failed to close file\n");
+            TEST_FAIL();
         }
     }
 
diff --git a/components/tcp_transport/host_test/main/test_websocket_transport.cpp b/components/tcp_transport/host_test/main/test_websocket_transport.cpp
index 2d00bb143f4..8ea89cf9c02 100644
--- a/components/tcp_transport/host_test/main/test_websocket_transport.cpp
+++ b/components/tcp_transport/host_test/main/test_websocket_transport.cpp
@@ -102,17 +102,52 @@ int mock_write_callback(esp_transport_handle_t transport, const char *request_se
     return len;
 }
 
-// Callback function for mock_read
+// Callbacks for mocked poll_reed and read functions
+int mock_poll_read_callback(esp_transport_handle_t t, int timeout_ms, int num_call)
+{
+    if (num_call) {
+        return 0;
+    }
+    return 1;
+}
+
 int mock_valid_read_callback(esp_transport_handle_t transport, char *buffer, int len, int timeout_ms, int num_call)
 {
+    if (num_call) {
+        return 0;
+    }
     std::string websocket_response = make_response();
     std::memcpy(buffer, websocket_response.data(), websocket_response.size());
     return websocket_response.size();
 }
 
+// Callback function for mock_read
+int mock_valid_read_fragmented_callback(esp_transport_handle_t t, char *buffer, int len, int timeout_ms, int num_call)
+{
+    static int offset = 0;
+    std::string websocket_response = make_response();
+    if (buffer == nullptr) {
+        return offset == websocket_response.size() ? 0 : 1;
+    }
+    int read_size = 1;
+    if (offset == websocket_response.size()) {
+        return 0;
+    }
+    std::memcpy(buffer, websocket_response.data() + offset, read_size);
+    offset += read_size;
+    return read_size;
+}
+
+int mock_valid_poll_read_fragmented_callback(esp_transport_handle_t t, int timeout_ms, int num_call)
+{
+    return mock_valid_read_fragmented_callback(t, nullptr, 0, 0, 0);
+}
+
 }
 
-void test_ws_connect(bool expect_valid_connection, CMOCK_mock_read_CALLBACK read_callback) {
+void test_ws_connect(bool expect_valid_connection,
+                     CMOCK_mock_read_CALLBACK read_callback,
+                     CMOCK_mock_poll_read_CALLBACK poll_read_callback=mock_poll_read_callback) {
     constexpr static auto timeout = 50;
     constexpr static auto port = 8080;
     constexpr static auto host = "localhost";
@@ -128,7 +163,7 @@ void test_ws_connect(bool expect_valid_connection, CMOCK_mock_read_CALLBACK read
 
     SECTION("Successful connection and read data") {
         fmt::print("Attempting to connect to WebSocket\n");
-	esp_crypto_sha1_ExpectAnyArgsAndReturn(0);
+	    esp_crypto_sha1_ExpectAnyArgsAndReturn(0);
         esp_crypto_base64_encode_ExpectAnyArgsAndReturn(0);
 
         // Set the callback function for mock_write
@@ -136,7 +171,7 @@ void test_ws_connect(bool expect_valid_connection, CMOCK_mock_read_CALLBACK read
         mock_connect_ExpectAndReturn(parent_handle.get(), host, port, timeout, ESP_OK);
         // Set the callback function for mock_read
         mock_read_Stub(read_callback);
-        mock_poll_read_ExpectAnyArgsAndReturn(1);
+        mock_poll_read_Stub(poll_read_callback);
         esp_crypto_base64_encode_ExpectAnyArgsAndReturn(0);
         mock_destroy_ExpectAnyArgsAndReturn(ESP_OK);
 
@@ -150,7 +185,11 @@ void test_ws_connect(bool expect_valid_connection, CMOCK_mock_read_CALLBACK read
         REQUIRE(esp_transport_connect(websocket_transport.get(), host, port, timeout) == 0);
 
         char buffer[WS_BUFFER_SIZE];
-        int read_len = esp_transport_read(websocket_transport.get(), buffer, WS_BUFFER_SIZE, timeout);
+        int read_len = 0;
+        int partial_read;
+        while ((partial_read = esp_transport_read(websocket_transport.get(), &buffer[read_len], WS_BUFFER_SIZE - read_len, timeout)) > 0 ) {
+            read_len+= partial_read;
+        }
         fmt::print("Read result: {}\n", read_len);
         REQUIRE(read_len > 0);  // Ensure data is read
 
@@ -166,6 +205,12 @@ TEST_CASE("WebSocket Transport Connection", "[websocket_transport]")
     test_ws_connect(true, mock_valid_read_callback);
 }
 
+// Happy flow with fragmented reads byte by byte
+TEST_CASE("ws connect and reads by fragments", "[websocket_transport]")
+{
+    test_ws_connect(true, mock_valid_read_fragmented_callback, mock_valid_poll_read_fragmented_callback);
+}
+
 // Some corner cases where we expect the ws connection to fail
 
 TEST_CASE("ws connect fails (0 len response)", "[websocket_transport]")
diff --git a/components/tcp_transport/transport_ws.c b/components/tcp_transport/transport_ws.c
index 6ccfe369f9c..7e4ca86cfe6 100644
--- a/components/tcp_transport/transport_ws.c
+++ b/components/tcp_transport/transport_ws.c
@@ -495,6 +495,34 @@ static int ws_read_payload(esp_transport_handle_t t, char *buffer, int len, int
     return rlen;
 }
 
+static int esp_transport_read_exact_size(transport_ws_t *ws, char *buffer, int requested_len, int timeout_ms)
+{
+    int total_read = 0;
+    int len = requested_len;
+
+    while (len > 0) {
+        int bytes_read = esp_transport_read_internal(ws, buffer, len, timeout_ms);
+
+        if (bytes_read < 0) {
+            return bytes_read; // Return error from the underlying read
+        }
+
+        if (bytes_read == 0) {
+            // If we read 0 bytes, we return an error, since reading exact number of bytes resulted in a timeout operation
+            ESP_LOGW(TAG, "Requested to read %d, actually read %d bytes", requested_len, total_read);
+            return -1;
+        }
+
+        // Update buffer and remaining length
+        buffer += bytes_read;
+        len -= bytes_read;
+        total_read += bytes_read;
+
+        ESP_LOGV(TAG, "Read fragment of %d bytes", bytes_read);
+    }
+    return total_read;
+}
+
 
 /* Read and parse the WS header, determine length of payload */
 static int ws_read_header(esp_transport_handle_t t, char *buffer, int len, int timeout_ms)
diff --git a/components/touch_element/include/touch_element/touch_element.h b/components/touch_element/include/touch_element/touch_element.h
index 902c23e94b2..fa32d8f42c1 100644
--- a/components/touch_element/include/touch_element/touch_element.h
+++ b/components/touch_element/include/touch_element/touch_element.h
@@ -1,12 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
-#include "driver/touch_sensor.h"
+#include "driver/touch_sensor_legacy.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -274,9 +274,9 @@ esp_err_t touch_element_waterproof_remove(touch_elem_handle_t element_handle);
  * @return
  *      - ESP_OK: Successfully initialized touch sleep
  *      - ESP_ERR_INVALID_STATE: Touch element is not installed or touch sleep has been installed
- *      - ESP_ERR_INVALID_ARG: inputed argument is NULL
+ *      - ESP_ERR_INVALID_ARG: inputted argument is NULL
  *      - ESP_ERR_NO_MEM: no memory for touch sleep struct
- *      - ESP_ERR_NOT_SUPPORTED: inputed wakeup_elem_handle is not touch_button_handle_t type, currently only touch_button_handle_t supported
+ *      - ESP_ERR_NOT_SUPPORTED: inputted wakeup_elem_handle is not touch_button_handle_t type, currently only touch_button_handle_t supported
  */
 esp_err_t touch_element_enable_light_sleep(const touch_elem_sleep_config_t *sleep_config);
 
@@ -305,9 +305,9 @@ esp_err_t touch_element_disable_light_sleep(void);
  * @return
  *      - ESP_OK: Successfully initialized touch sleep
  *      - ESP_ERR_INVALID_STATE: Touch element is not installed or touch sleep has been installed
- *      - ESP_ERR_INVALID_ARG: inputed argument is NULL
+ *      - ESP_ERR_INVALID_ARG: inputted argument is NULL
  *      - ESP_ERR_NO_MEM: no memory for touch sleep struct
- *      - ESP_ERR_NOT_SUPPORTED: inputed wakeup_elem_handle is not touch_button_handle_t type, currently only touch_button_handle_t supported
+ *      - ESP_ERR_NOT_SUPPORTED: inputted wakeup_elem_handle is not touch_button_handle_t type, currently only touch_button_handle_t supported
  */
 esp_err_t touch_element_enable_deep_sleep(touch_elem_handle_t wakeup_elem_handle, const touch_elem_sleep_config_t *sleep_config);
 
diff --git a/components/ulp/CMakeLists.txt b/components/ulp/CMakeLists.txt
index 058d05922b3..dbe990e652e 100644
--- a/components/ulp/CMakeLists.txt
+++ b/components/ulp/CMakeLists.txt
@@ -78,6 +78,10 @@ if(CONFIG_ULP_COPROC_TYPE_LP_CORE)
     if(CONFIG_SOC_LP_ADC_SUPPORTED)
         list(APPEND srcs "lp_core/shared/ulp_lp_core_lp_adc_shared.c")
     endif()
+
+    if(CONFIG_SOC_LP_VAD_SUPPORTED)
+        list(APPEND srcs "lp_core/shared/ulp_lp_core_lp_vad_shared.c")
+    endif()
 endif()
 
 idf_component_register(SRCS ${srcs}
diff --git a/components/ulp/cmake/IDFULPProject.cmake b/components/ulp/cmake/IDFULPProject.cmake
index 04da71b00c2..fd90cfd87ff 100644
--- a/components/ulp/cmake/IDFULPProject.cmake
+++ b/components/ulp/cmake/IDFULPProject.cmake
@@ -126,6 +126,7 @@ function(ulp_apply_default_sources ulp_app_name)
         "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_spi.c"
         "${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_ubsan.c"
         "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_lp_adc_shared.c"
+        "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c"
         "${IDF_PATH}/components/ulp/lp_core/shared/ulp_lp_core_critical_section_shared.c")
 
         set(target_folder ${IDF_TARGET})
diff --git a/components/ulp/lp_core/include/ulp_lp_core.h b/components/ulp/lp_core/include/ulp_lp_core.h
index d737d638aca..6a0373aefa2 100644
--- a/components/ulp/lp_core/include/ulp_lp_core.h
+++ b/components/ulp/lp_core/include/ulp_lp_core.h
@@ -22,6 +22,7 @@ extern "C" {
 #define ULP_LP_CORE_WAKEUP_SOURCE_LP_IO     BIT(2) // Enable wake-up by LP IO interrupt
 #define ULP_LP_CORE_WAKEUP_SOURCE_ETM       BIT(3) // Enable wake-up by ETM event
 #define ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER  BIT(4) // Enable wake-up by LP timer
+#define ULP_LP_CORE_WAKEUP_SOURCE_LP_VAD    BIT(5) // Enable wake-up by LP VAD
 
 /**
  * @brief ULP LP core init parameters
diff --git a/components/ulp/lp_core/lp_core.c b/components/ulp/lp_core/lp_core.c
index aedcf0e78e2..0efa300ac0f 100644
--- a/components/ulp/lp_core/lp_core.c
+++ b/components/ulp/lp_core/lp_core.c
@@ -35,7 +35,7 @@ extern uint32_t _rtc_ulp_memory_start;
 
 const static char* TAG = "ulp-lp-core";
 
-#define WAKEUP_SOURCE_MAX_NUMBER 5
+#define WAKEUP_SOURCE_MAX_NUMBER 6
 
 #define RESET_HANDLER_ADDR (intptr_t)(&_rtc_ulp_memory_start + 0x80 / 4) // Placed after the 0x80 byte long vector table
 
@@ -46,6 +46,9 @@ static uint32_t wakeup_src_sw_to_hw_flag_lookup[WAKEUP_SOURCE_MAX_NUMBER] = {
     LP_CORE_LL_WAKEUP_SOURCE_LP_IO,
     LP_CORE_LL_WAKEUP_SOURCE_ETM,
     LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER,
+#if SOC_LP_VAD_SUPPORTED
+    LP_CORE_LL_WAKEUP_SOURCE_LP_VAD,
+#endif
 };
 
 /* Convert the wake-up sources defined in ulp_lp_core.h to the actual HW wake-up source values */
@@ -130,7 +133,7 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg)
     }
 #endif
 
-    if (cfg->wakeup_source & (ULP_LP_CORE_WAKEUP_SOURCE_LP_UART | ULP_LP_CORE_WAKEUP_SOURCE_LP_IO)) {
+    if (cfg->wakeup_source & (ULP_LP_CORE_WAKEUP_SOURCE_LP_UART)) {
         ESP_LOGE(TAG, "Wake-up source not yet supported");
         return ESP_ERR_INVALID_ARG;
     }
diff --git a/components/ulp/lp_core/lp_core/lp_core_utils.c b/components/ulp/lp_core/lp_core/lp_core_utils.c
index 8b358741fbb..d3e8664907b 100644
--- a/components/ulp/lp_core/lp_core/lp_core_utils.c
+++ b/components/ulp/lp_core/lp_core/lp_core_utils.c
@@ -14,6 +14,10 @@
 #include "hal/pmu_ll.h"
 #include "hal/uart_ll.h"
 #include "hal/rtc_io_ll.h"
+#if SOC_LP_I2S_SUPPORT_VAD
+//For VAD
+#include "hal/lp_i2s_ll.h"
+#endif
 
 #if SOC_LP_TIMER_SUPPORTED
 #include "hal/lp_timer_ll.h"
@@ -56,6 +60,13 @@ void ulp_lp_core_update_wakeup_cause(void)
         rtcio_ll_clear_interrupt_status();
     }
 
+#if SOC_LP_VAD_SUPPORTED
+    if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_VAD)) {
+        lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_VAD;
+        lp_i2s_ll_rx_clear_interrupt_status(&LP_I2S, LP_I2S_LL_EVENT_VAD_DONE_INT);
+    }
+#endif
+
 #if SOC_ETM_SUPPORTED
     if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_ETM) \
             && lp_core_ll_get_etm_wakeup_flag()) {
diff --git a/components/ulp/lp_core/shared/include/ulp_lp_core_lp_vad_shared.h b/components/ulp/lp_core/shared/include/ulp_lp_core_lp_vad_shared.h
new file mode 100644
index 00000000000..8a37dee54db
--- /dev/null
+++ b/components/ulp/lp_core/shared/include/ulp_lp_core_lp_vad_shared.h
@@ -0,0 +1,121 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/lp_i2s_vad.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief LP VAD configurations
+ */
+typedef lp_vad_init_config_t lp_core_lp_vad_cfg_t;
+
+/**
+ * @brief State Machine
+                                           ┌──────────────────────────────────┐
+                                           │                                  │
+                             ┌─────────────┤  speak-activity-listening-state  │ ◄───────────────┐
+                             │             │                                  │                 │
+                             │             └──────────────────────────────────┘                 │
+                             │                          ▲                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+detected speak activity      │                          │  detected speak activity              │   detected speak activity
+        >=                   │                          │          >=                           │           >=
+'speak_activity_thresh'      │                          │  'min_speak_activity_thresh'          │   'max_speak_activity_thresh'
+                             │                          │                                       │
+                             │                          │          &&                           │
+                             │                          │                                       │
+                             │                          │  detected non-speak activity          │
+                             │                          │           <                           │
+                             │                          │  'non_speak_activity_thresh'          │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │                          │                                       │
+                             │              ┌───────────┴─────────────────────┐                 │
+                             │              │                                 │                 │
+                             └───────────►  │ speak-activity-detected-state   ├─────────────────┘
+                                            │                                 │
+                                            └─┬───────────────────────────────┘
+                                              │
+                                              │                     ▲
+                                              │                     │
+                                              │                     │
+                                              │                     │  detected speak activity
+                                              │                     │          >=
+                                              │                     │  'min_speak_activity_thresh'
+                                              │                     │
+                                              │                     │          &&
+                                              │                     │
+                                              │                     │  detected non-speak activity
+                                              │                     │           <
+                                              └─────────────────────┘  'non_speak_activity_thresh'
+*/
+
+/**
+ * @brief LP VAD init
+ *
+ * @param[in] vad_id        VAD ID
+ * @param[in] init_config   Initial configurations
+ *
+ * @return
+ *        - ESP_OK:                 On success
+ *        - ESP_ERR_INVALID_ARG:    Invalid argument
+ *        - ESP_ERR_INVALID_STATE:  Driver state is invalid, you shouldn't call this API at this moment
+ */
+esp_err_t lp_core_lp_vad_init(lp_vad_t vad_id, const lp_core_lp_vad_cfg_t *init_config);
+
+/**
+ * @brief Enable LP VAD
+ *
+ * @param[in] vad_id        VAD ID
+ * @param[in] init_config   Initial configurations
+ *
+ * @return
+ *        - ESP_OK:                 On success
+ *        - ESP_ERR_INVALID_ARG:    Invalid argument
+ *        - ESP_ERR_INVALID_STATE:  Driver state is invalid, you shouldn't call this API at this moment
+ */
+esp_err_t lp_core_lp_vad_enable(lp_vad_t vad_id);
+
+/**
+ * @brief Disable LP VAD
+ *
+ * @param[in] vad_id        VAD ID
+ * @param[in] init_config   Initial configurations
+ *
+ * @return
+ *        - ESP_OK:                 On success
+ *        - ESP_ERR_INVALID_ARG:    Invalid argument
+ *        - ESP_ERR_INVALID_STATE:  Driver state is invalid, you shouldn't call this API at this moment
+ */
+esp_err_t lp_core_lp_vad_disable(lp_vad_t vad_id);
+
+/**
+ * @brief Deinit LP VAD
+ *
+ * @param[in] vad_id        VAD ID
+ *
+ * @return
+ *        - ESP_OK:                 On success
+ *        - ESP_ERR_INVALID_ARG:    Invalid argument
+ *        - ESP_ERR_INVALID_STATE:  Driver state is invalid, you shouldn't call this API at this moment
+ */
+esp_err_t lp_core_lp_vad_deinit(lp_vad_t vad_id);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c b/components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c
new file mode 100644
index 00000000000..db78e746335
--- /dev/null
+++ b/components/ulp/lp_core/shared/ulp_lp_core_lp_vad_shared.c
@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/soc_caps.h"
+#if SOC_LP_VAD_SUPPORTED
+#include "esp_check.h"
+#include "esp_err.h"
+#include "ulp_lp_core_lp_vad_shared.h"
+#if SOC_LP_I2S_SUPPORT_VAD
+//For VAD
+#include "hal/lp_i2s_ll.h"
+#include "hal/lp_i2s_hal.h"
+#include "esp_private/lp_i2s_private.h"
+#endif  //SOC_LP_I2S_SUPPORT_VAD
+
+//make this available for multi vad id in future
+vad_unit_handle_t s_vad_handle;
+
+esp_err_t lp_core_lp_vad_init(lp_vad_t vad_id, const lp_core_lp_vad_cfg_t *init_config)
+{
+#if IS_ULP_COCPU
+    // Not supported
+    return ESP_ERR_NOT_SUPPORTED;
+#else
+    esp_err_t ret = lp_i2s_vad_new_unit(vad_id, init_config, &s_vad_handle);
+    return ret;
+#endif
+}
+
+esp_err_t lp_core_lp_vad_enable(lp_vad_t vad_id)
+{
+#if IS_ULP_COCPU
+    // Not supported
+    return ESP_ERR_NOT_SUPPORTED;
+#else
+    esp_err_t ret = lp_i2s_vad_enable(s_vad_handle);
+    return ret;
+#endif
+}
+
+esp_err_t lp_core_lp_vad_disable(lp_vad_t vad_id)
+{
+#if IS_ULP_COCPU
+    // Not supported
+    return ESP_ERR_NOT_SUPPORTED;
+#else
+    esp_err_t ret = lp_i2s_vad_disable(s_vad_handle);
+    return ret;
+#endif
+}
+
+esp_err_t lp_core_lp_vad_deinit(lp_vad_t vad_id)
+{
+#if IS_ULP_COCPU
+    // Not supported
+    return ESP_ERR_NOT_SUPPORTED;
+#else
+    esp_err_t ret = lp_i2s_vad_del_unit(s_vad_handle);
+    return ret;
+#endif
+}
+#endif /* SOC_LP_VAD_SUPPORTED */
diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt
index 63d8f905d7c..239b78cf330 100644
--- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt
+++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt
@@ -20,6 +20,10 @@ if(CONFIG_SOC_LP_ADC_SUPPORTED)
     list(APPEND app_sources "test_lp_core_adc.c")
 endif()
 
+if(CONFIG_SOC_LP_VAD_SUPPORTED)
+    list(APPEND app_sources "test_lp_core_vad.c")
+endif()
+
 set(lp_core_sources         "lp_core/test_main.c")
 set(lp_core_sources_counter "lp_core/test_main_counter.c")
 
@@ -46,10 +50,15 @@ if(CONFIG_SOC_LP_ADC_SUPPORTED)
     set(lp_core_sources_adc "lp_core/test_main_adc.c")
 endif()
 
+if(CONFIG_SOC_LP_VAD_SUPPORTED)
+    set(lp_core_sources_vad "lp_core/test_main_vad.c")
+endif()
+
 idf_component_register(SRCS ${app_sources}
                        INCLUDE_DIRS "lp_core"
                        REQUIRES ulp unity esp_timer test_utils
-                       WHOLE_ARCHIVE)
+                       WHOLE_ARCHIVE
+                       EMBED_FILES "test_vad_8k.pcm")
 
 set(lp_core_exp_dep_srcs ${app_sources})
 
@@ -79,3 +88,7 @@ endif()
 if(CONFIG_SOC_LP_ADC_SUPPORTED)
     ulp_embed_binary(lp_core_test_app_adc "${lp_core_sources_adc}" "${lp_core_exp_dep_srcs}")
 endif()
+
+if(CONFIG_SOC_LP_VAD_SUPPORTED)
+    ulp_embed_binary(lp_core_test_app_vad "${lp_core_sources_vad}" "${lp_core_exp_dep_srcs}")
+endif()
diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/Kconfig.projbuild b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/Kconfig.projbuild
new file mode 100644
index 00000000000..5783fc5daf0
--- /dev/null
+++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/Kconfig.projbuild
@@ -0,0 +1,9 @@
+menu "Test Configurations"
+
+    config TEST_LP_CORE_VAD_ENABLE
+        bool "Enable LP VAD test"
+        default n
+        help
+            Enable this to trigger LP VAD test
+
+endmenu
diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_vad.c b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_vad.c
new file mode 100644
index 00000000000..5f6198fe370
--- /dev/null
+++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/lp_core/test_main_vad.c
@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+volatile bool vad_wakup;
+
+int main(void)
+{
+    vad_wakup = true;
+
+    return 0;
+}
diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_vad.c b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_vad.c
new file mode 100644
index 00000000000..16a3c059dd8
--- /dev/null
+++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_vad.c
@@ -0,0 +1,154 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+#include <string.h>
+#include "unity.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_log.h"
+#include "driver/lp_i2s.h"
+#include "driver/lp_i2s_std.h"
+#include "driver/i2s_std.h"
+#include "ulp_lp_core.h"
+#include "ulp_lp_core_lp_vad_shared.h"
+#include "lp_core_test_app_vad.h"
+
+#if CONFIG_TEST_LP_CORE_VAD_ENABLE
+
+#define TEST_I2S_FRAME_SIZE            (128)       // Frame numbers in every writing / reading
+#define TEST_I2S_TRANS_SIZE            (4096)      // Trans size
+
+extern const uint8_t test_vad_pcm_start[]            asm("_binary_test_vad_8k_pcm_start");
+extern const uint8_t test_vad_pcm_end[]              asm("_binary_test_vad_8k_pcm_end");
+extern const uint8_t lp_core_main_vad_bin_start[]    asm("_binary_lp_core_test_app_vad_bin_start");
+extern const uint8_t lp_core_main_vad_bin_end[]      asm("_binary_lp_core_test_app_vad_bin_end");
+static const char *TAG = "TEST_VAD";
+
+static void load_and_start_lp_core_firmware(ulp_lp_core_cfg_t* cfg, const uint8_t* firmware_start, const uint8_t* firmware_end)
+{
+    TEST_ASSERT(ulp_lp_core_load_binary(firmware_start,
+                                        (firmware_end - firmware_start)) == ESP_OK);
+
+    TEST_ASSERT(ulp_lp_core_run(cfg) == ESP_OK);
+}
+
+void test_lp_vad(lp_vad_t vad_id)
+{
+    esp_err_t ret = ESP_FAIL;
+    int pcm_size = test_vad_pcm_end - test_vad_pcm_start;
+    printf("pcm_size: %d\n", pcm_size);
+
+    lp_i2s_chan_handle_t rx_handle = NULL;
+    lp_i2s_chan_config_t config = {
+        .id = 0,
+        .role = I2S_ROLE_SLAVE,
+        .threshold = 512,
+    };
+    TEST_ESP_OK(lp_i2s_new_channel(&config, NULL, &rx_handle));
+
+    i2s_chan_handle_t tx_handle = NULL;
+    i2s_chan_config_t i2s_channel_config = {
+        .id = I2S_NUM_0,
+        .role = I2S_ROLE_MASTER,
+        .dma_desc_num = 4,
+        .dma_frame_num = TEST_I2S_FRAME_SIZE,
+        .auto_clear = false,
+    };
+    TEST_ESP_OK(i2s_new_channel(&i2s_channel_config, &tx_handle, NULL));
+
+    lp_i2s_std_config_t lp_std_cfg = {
+        .pin_cfg = {
+            .bck = 4,
+            .ws = 5,
+            .din = 6,
+        },
+    };
+    lp_std_cfg.slot_cfg = (lp_i2s_std_slot_config_t)LP_I2S_STD_PCM_SHORT_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO);
+    TEST_ESP_OK(lp_i2s_channel_init_std_mode(rx_handle, &lp_std_cfg));
+
+    i2s_std_config_t i2s_std_config = {
+        .gpio_cfg = {
+            .mclk = I2S_GPIO_UNUSED,
+            .bclk = GPIO_NUM_7,
+            .ws   = GPIO_NUM_8,
+            .dout = GPIO_NUM_21,
+            .din  = -1,
+            .invert_flags = {
+                .mclk_inv = false,
+                .bclk_inv = false,
+                .ws_inv   = false,
+            },
+        },
+    };
+    i2s_std_config.clk_cfg = (i2s_std_clk_config_t)I2S_STD_CLK_DEFAULT_CONFIG(16000);
+    i2s_std_config.slot_cfg = (i2s_std_slot_config_t)I2S_STD_PCM_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO);
+    TEST_ESP_OK(i2s_channel_init_std_mode(tx_handle, &i2s_std_config));
+
+    // LP VAD Init
+    lp_vad_init_config_t init_config = {
+        .lp_i2s_chan = rx_handle,
+        .vad_config = {
+            .init_frame_num = 100,
+            .min_energy_thresh = 100,
+            .speak_activity_thresh = 10,
+            .non_speak_activity_thresh = 30,
+            .min_speak_activity_thresh = 3,
+            .max_speak_activity_thresh = 100,
+        },
+    };
+    TEST_ESP_OK(lp_core_lp_vad_init(0, &init_config));
+
+    /* Load ULP firmware and start the coprocessor */
+    ulp_lp_core_cfg_t cfg = {
+        .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_LP_VAD,
+    };
+    load_and_start_lp_core_firmware(&cfg, lp_core_main_vad_bin_start, lp_core_main_vad_bin_end);
+
+    uint8_t *txbuf = (uint8_t *)heap_caps_calloc(1, TEST_I2S_TRANS_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+    TEST_ASSERT(txbuf);
+
+    uint8_t *prebuf = (uint8_t *)heap_caps_calloc(1, TEST_I2S_TRANS_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL);
+    TEST_ASSERT(prebuf);
+
+    memcpy(prebuf, test_vad_pcm_start, TEST_I2S_TRANS_SIZE);
+    memcpy(txbuf, test_vad_pcm_start, TEST_I2S_TRANS_SIZE);
+
+    for (int i = 0; i < TEST_I2S_TRANS_SIZE; i++) {
+        ESP_LOGD(TAG, "prebuf[%d]: %d", i, prebuf[i]);
+        ESP_LOGD(TAG, "txbuf[%d]: %d", i, txbuf[i]);
+    }
+
+    size_t bytes_written = 0;
+    TEST_ESP_OK(i2s_channel_preload_data(tx_handle, prebuf, TEST_I2S_TRANS_SIZE, &bytes_written));
+    TEST_ESP_OK(lp_i2s_channel_enable(rx_handle));
+    TEST_ESP_OK(lp_core_lp_vad_enable(0));
+    TEST_ESP_OK(i2s_channel_enable(tx_handle));
+
+    ret = i2s_channel_write(tx_handle, txbuf, TEST_I2S_TRANS_SIZE, &bytes_written, 0);
+    if (ret != ESP_OK && ret != ESP_ERR_TIMEOUT) {
+        TEST_ESP_OK(ret);
+    }
+    ESP_LOGD(TAG, "bytes_written: %d", bytes_written);
+
+    while (!ulp_vad_wakup) {
+        ;
+    }
+
+    ESP_LOGI(TAG, "wakeup");
+
+    TEST_ESP_OK(lp_i2s_channel_disable(rx_handle));
+    TEST_ESP_OK(lp_i2s_del_channel(rx_handle));
+    TEST_ESP_OK(i2s_channel_disable(tx_handle));
+    TEST_ESP_OK(i2s_del_channel(tx_handle));
+    free(txbuf);
+    free(prebuf);
+}
+
+TEST_CASE("LP VAD wakeup test", "[lp_core][lp_vad]")
+{
+    test_lp_vad(0);
+}
+#endif  //CONFIG_TEST_LP_CORE_VAD_ENABLE
diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_vad_8k.pcm b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_vad_8k.pcm
new file mode 100644
index 00000000000..5b6c32a0373
Binary files /dev/null and b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_vad_8k.pcm differ
diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py b/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py
index 53178dca4e8..33e7b3c9507 100644
--- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py
+++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py
@@ -33,6 +33,19 @@ def test_lp_core_xtal(dut: Dut) -> None:
     dut.run_all_single_board_cases()
 
 
+@pytest.mark.esp32p4
+@pytest.mark.lp_i2s
+@pytest.mark.parametrize(
+    'config',
+    [
+        'lp_vad',
+    ],
+    indirect=True,
+)
+def test_lp_vad(dut: Dut) -> None:
+    dut.run_all_single_board_cases(group='lp_vad')
+
+
 @pytest.mark.esp32c6
 # TODO: Enable LP I2C test for esp32p4 (IDF-9407)
 @pytest.mark.generic_multi_device
diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.default b/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.default
deleted file mode 100644
index e69de29bb2d..00000000000
diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad b/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad
new file mode 100644
index 00000000000..766d6c83cde
--- /dev/null
+++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.lp_vad
@@ -0,0 +1 @@
+CONFIG_TEST_LP_CORE_VAD_ENABLE=y
diff --git a/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/CMakeLists.txt b/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/CMakeLists.txt
index 9e6a9d16bbb..a1ca21afaf9 100644
--- a/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/CMakeLists.txt
+++ b/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/CMakeLists.txt
@@ -1,7 +1,8 @@
 set(app_sources "test_app_main.c" "test_lp_core.c")
 set(lp_core_sources             "lp_core/test_hello_main.c")
 set(lp_core_sources_panic       "lp_core/test_panic_main.c")
-set(lp_core_sources_shared_mem   "lp_core/test_shared_mem_main.c")
+set(lp_core_sources_shared_mem  "lp_core/test_shared_mem_main.c")
+set(lp_core_sources_lp_rom              "lp_core/test_lp_rom_main.c")
 
 idf_component_register(SRCS ${app_sources}
                        INCLUDE_DIRS "lp_core"
@@ -13,3 +14,7 @@ set(lp_core_exp_dep_srcs ${app_sources})
 ulp_embed_binary(lp_core_test_app "${lp_core_sources}" "${lp_core_exp_dep_srcs}")
 ulp_embed_binary(lp_core_test_app_panic "${lp_core_sources_panic}" "${lp_core_exp_dep_srcs}")
 ulp_embed_binary(lp_core_test_app_shared_mem "${lp_core_sources_shared_mem}" "${lp_core_exp_dep_srcs}")
+
+if(CONFIG_ESP_ROM_HAS_LP_ROM)
+    ulp_embed_binary(lp_core_test_app_lp_rom "${lp_core_sources_lp_rom}" "${lp_core_exp_dep_srcs}")
+endif()
diff --git a/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/lp_core/test_lp_rom_main.c b/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/lp_core/test_lp_rom_main.c
new file mode 100644
index 00000000000..6a99e116f74
--- /dev/null
+++ b/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/lp_core/test_lp_rom_main.c
@@ -0,0 +1,85 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include "soc/soc.h"
+#include "ulp_lp_core_print.h"
+#include <ctype.h>
+
+void assert_function_in_rom(void *func)
+{
+    if ((intptr_t)func < SOC_LP_ROM_LOW || (intptr_t)func > SOC_LP_ROM_HIGH) {
+        abort();
+    }
+}
+
+static void test_memset(void)
+{
+#define TEST_MEMSET_VAL 0xAB
+    assert_function_in_rom(memset);
+
+    lp_core_printf("Testing memset\n");
+    uint8_t test_buf[100];
+
+    memset(test_buf, TEST_MEMSET_VAL, sizeof(test_buf));
+
+    for (int i = 0; i < sizeof(test_buf); i++) {
+        if (test_buf[i] != TEST_MEMSET_VAL) {
+            lp_core_printf("test_buf[%d]: 0x%X != 0x%X\n", i, test_buf[i], TEST_MEMSET_VAL);
+            abort();
+        }
+    }
+}
+
+static void test_memcpy(void)
+{
+#define TEST_MEMCPY_VAL 0xAC
+#define TEST_SIZE 100
+
+    assert_function_in_rom(memcpy);
+    lp_core_printf("Testing memcpy\n");
+    uint8_t test_buf_a[TEST_SIZE];
+    memset(test_buf_a, TEST_MEMCPY_VAL, TEST_SIZE);
+
+    uint8_t test_buf_b[TEST_SIZE];
+
+    memcpy(test_buf_b, test_buf_a, TEST_SIZE);
+
+    for (int i = 0; i < TEST_SIZE; i++) {
+        if (test_buf_b[i] != TEST_MEMCPY_VAL) {
+            lp_core_printf("test_buf_b[%d]: 0x%X != 0x%X\n", i, test_buf_b[i], TEST_MEMCPY_VAL);
+            abort();
+        }
+    }
+}
+
+static void test_abs(void)
+{
+    assert_function_in_rom(abs);
+    lp_core_printf("Testing abs\n");
+    if (abs(-123) != 123) {
+        lp_core_printf("Failed abs() test\n");
+        abort();
+    }
+}
+
+volatile bool lp_rom_test_finished;
+
+int main(void)
+{
+    // Test a misc of ROM functions to catch any regression with LD file updates
+    test_memset();
+    test_memcpy();
+    test_abs();
+
+    lp_core_printf("ULP: all tests passed\n");
+    lp_rom_test_finished = true;
+
+    return 0;
+}
diff --git a/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/test_lp_core.c b/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/test_lp_core.c
index e21d52afbda..3567f4a65f7 100644
--- a/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/test_lp_core.c
+++ b/components/ulp/test_apps/lp_core/lp_core_hp_uart/main/test_lp_core.c
@@ -19,6 +19,10 @@
 #include "ulp_lp_core_memory_shared.h"
 #include "test_shared.h"
 
+#if ESP_ROM_HAS_LP_ROM
+#include "lp_core_test_app_lp_rom.h"
+#endif
+
 extern const uint8_t lp_core_main_bin_start[] asm("_binary_lp_core_test_app_bin_start");
 extern const uint8_t lp_core_main_bin_end[]   asm("_binary_lp_core_test_app_bin_end");
 
@@ -28,6 +32,11 @@ extern const uint8_t lp_core_panic_bin_end[]   asm("_binary_lp_core_test_app_pan
 extern const uint8_t lp_core_shared_mem_bin_start[] asm("_binary_lp_core_test_app_shared_mem_bin_start");
 extern const uint8_t lp_core_shared_mem_bin_end[]   asm("_binary_lp_core_test_app_shared_mem_bin_end");
 
+#if ESP_ROM_HAS_LP_ROM
+extern const uint8_t lp_core_lp_rom_bin_start[] asm("_binary_lp_core_test_app_lp_rom_bin_start");
+extern const uint8_t lp_core_lp_rom_bin_end[]   asm("_binary_lp_core_test_app_lp_rom_bin_end");
+#endif
+
 static void load_and_start_lp_core_firmware(ulp_lp_core_cfg_t* cfg, const uint8_t* firmware_start, const uint8_t* firmware_end)
 {
     TEST_ASSERT(ulp_lp_core_load_binary(firmware_start,
@@ -93,3 +102,24 @@ TEST_CASE("LP-Core Shared-mem", "[lp_core]")
 
     printf("HP shared memory test passed\n");
 }
+
+#if ESP_ROM_HAS_LP_ROM
+TEST_CASE("LP-Core LP-ROM", "[lp_core]")
+{
+    /* Load ULP firmware and start the coprocessor */
+    ulp_lp_core_cfg_t cfg = {
+        .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU,
+    };
+
+    TEST_ASSERT(ulp_lp_core_load_binary(lp_core_lp_rom_bin_start, (lp_core_lp_rom_bin_end - lp_core_lp_rom_bin_start)) == ESP_OK);
+
+    TEST_ASSERT(ulp_lp_core_run(&cfg) == ESP_OK);
+    // Actual test output on UART is checked by pytest, not unity test-case
+    // We simply wait to allow the lp-core to run once
+    while (!ulp_lp_rom_test_finished) {
+        vTaskDelay(100 / portTICK_PERIOD_MS);
+    }
+
+    printf("LP ROM test passed\n");
+}
+#endif
diff --git a/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py b/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py
index b21e6e3e358..1da72851654 100644
--- a/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py
+++ b/components/ulp/test_apps/lp_core/lp_core_hp_uart/pytest_lp_core_hp_uart.py
@@ -47,3 +47,12 @@ def test_lp_core_shared_mem(dut: Dut) -> None:
 
     dut.expect_exact('ULP shared memory test passed')
     dut.expect_exact('HP shared memory test passed')
+
+
+@pytest.mark.esp32p4
+@pytest.mark.generic
+def test_lp_core_lp_rom(dut: Dut) -> None:
+    dut.expect_exact('Press ENTER to see the list of tests')
+    dut.write('"LP-Core LP-ROM"')
+    dut.expect_exact('ULP: all tests passed')
+    dut.expect_exact('LP ROM test passed')
diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h
index 2556e766350..043c7d50728 100644
--- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h
+++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h
@@ -8,7 +8,7 @@
 
 #include "esp_err.h"
 #include "ulp_riscv_register_ops.h"
-#include "hal/touch_sensor_types.h"
+#include "hal/touch_sensor_legacy_types.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/components/usb/Kconfig b/components/usb/Kconfig
index a527613c7f5..376b7fc58c1 100644
--- a/components/usb/Kconfig
+++ b/components/usb/Kconfig
@@ -133,7 +133,19 @@ menu "USB-OTG"
 
                     The default value is 1.
 
-            config USB_HOST_EXT_PORT_CUSTOM_RESET_ENABLE
+            config USB_HOST_EXT_PORT_RESET_RECOVERY_DELAY_MS
+                int "Reset recovery delay in ms"
+                default 30
+                help
+                    After a port stops driving the reset signal, the USB 2.0 specification requires that
+                    the "USB System Software guarantees a minimum of 10 ms for reset recovery" before the
+                    attached device is expected to respond to data transfers (see USB 2.0 chapter 7.1.7.3 for
+                    more details).
+                    The device may ignore any data transfers during the recovery interval.
+
+                    The default value is set to 30 ms to be safe.
+
+            config USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_ENABLE
                 bool "Custom bPwrOn2PwrGood value"
                 default n
                 help
@@ -143,8 +155,8 @@ menu "USB-OTG"
                     When enabled, applies the custom PwrOn2PwrGood delay.
                     When disabled, applies the PwrOn2PwrGood value from the Hub Descriptor.
 
-            config USB_HOST_EXT_PORT_CUSTOM_RESET_MS
-                depends on USB_HOST_EXT_PORT_CUSTOM_RESET_ENABLE
+            config USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_MS
+                depends on USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_ENABLE
                 int "PwrOn2PwrGood delay in ms"
                 default 100
                 range 0 5000
diff --git a/components/usb/enum.c b/components/usb/enum.c
index ec18294c514..2024c09ee51 100644
--- a/components/usb/enum.c
+++ b/components/usb/enum.c
@@ -765,9 +765,15 @@ static esp_err_t control_response_handling(enum_stage_t stage)
     usb_transfer_t *ctrl_xfer = &p_enum_driver->constant.urb->transfer;
 
     if (ctrl_xfer->status != USB_TRANSFER_STATUS_COMPLETED) {
-        ESP_LOGE(ENUM_TAG, "Bad transfer status %d: %s",
-                 ctrl_xfer->status,
-                 enum_stage_strings[stage]);
+        if (ctrl_xfer->status == USB_TRANSFER_STATUS_STALL &&
+                stage >= ENUM_STAGE_CHECK_SHORT_LANGID_TABLE &&
+                stage <= ENUM_STAGE_CHECK_FULL_SER_STR_DESC) {
+            // String Descriptor request could be STALLed, if the device doesn't have them
+        } else {
+            ESP_LOGE(ENUM_TAG, "Bad transfer status %d: %s",
+                     ctrl_xfer->status,
+                     enum_stage_strings[stage]);
+        }
         return ret;
     }
 
@@ -1015,10 +1021,6 @@ static bool set_next_stage(bool last_stage_pass)
                 next_stage = last_stage + 1;
             }
         } else {
-            ESP_LOGE(ENUM_TAG, "[%d:%d] %s FAILED",
-                     p_enum_driver->single_thread.parent_dev_addr,
-                     p_enum_driver->single_thread.parent_port_num,
-                     enum_stage_strings[last_stage]);
             // These stages cannot fail
             assert(last_stage != ENUM_STAGE_SET_ADDR_RECOVERY &&
                    last_stage != ENUM_STAGE_SELECT_CONFIG &&
@@ -1055,6 +1057,10 @@ static bool set_next_stage(bool last_stage_pass)
                 break;
             default:
                 // Stage is not allowed to failed. Cancel enumeration.
+                ESP_LOGE(ENUM_TAG, "[%d:%d] %s FAILED",
+                         p_enum_driver->single_thread.parent_dev_addr,
+                         p_enum_driver->single_thread.parent_port_num,
+                         enum_stage_strings[last_stage]);
                 next_stage = ENUM_STAGE_CANCEL;
                 break;
             }
diff --git a/components/usb/ext_hub.c b/components/usb/ext_hub.c
index 149993070c0..8b02f4191f1 100644
--- a/components/usb/ext_hub.c
+++ b/components/usb/ext_hub.c
@@ -9,8 +9,7 @@
 #include "esp_err.h"
 #include "esp_log.h"
 #include "esp_heap_caps.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
+#include "esp_private/critical_section.h"
 #include "usb_private.h"
 #include "ext_hub.h"
 #include "ext_port.h"
@@ -152,7 +151,6 @@ typedef struct {
 } ext_hub_driver_t;
 
 static ext_hub_driver_t *p_ext_hub_driver = NULL;
-static portMUX_TYPE ext_hub_driver_lock = portMUX_INITIALIZER_UNLOCKED;
 
 const char *EXT_HUB_TAG = "EXT_HUB";
 
@@ -160,10 +158,11 @@ const char *EXT_HUB_TAG = "EXT_HUB";
 // ------------------------------- Helpers -------------------------------------
 // -----------------------------------------------------------------------------
 
-#define EXT_HUB_ENTER_CRITICAL()          portENTER_CRITICAL(&ext_hub_driver_lock)
-#define EXT_HUB_EXIT_CRITICAL()           portEXIT_CRITICAL(&ext_hub_driver_lock)
-#define EXT_HUB_ENTER_CRITICAL_SAFE()     portENTER_CRITICAL_SAFE(&ext_hub_driver_lock)
-#define EXT_HUB_EXIT_CRITICAL_SAFE()      portEXIT_CRITICAL_SAFE(&ext_hub_driver_lock)
+DEFINE_CRIT_SECTION_LOCK_STATIC(ext_hub_driver_lock);
+#define EXT_HUB_ENTER_CRITICAL()           esp_os_enter_critical(&ext_hub_driver_lock)
+#define EXT_HUB_EXIT_CRITICAL()            esp_os_exit_critical(&ext_hub_driver_lock)
+#define EXT_HUB_ENTER_CRITICAL_SAFE()      esp_os_enter_critical_safe(&ext_hub_driver_lock)
+#define EXT_HUB_EXIT_CRITICAL_SAFE()       esp_os_exit_critical_safe(&ext_hub_driver_lock)
 
 #define EXT_HUB_CHECK(cond, ret_val) ({              \
             if (!(cond)) {                                  \
@@ -529,7 +528,7 @@ static esp_err_t device_alloc(device_config_t *config, ext_hub_dev_t **ext_hub_d
     usb_device_info_t dev_info;
     ESP_ERROR_CHECK(usbh_dev_get_info(config->dev_hdl, &dev_info));
     if (dev_info.parent.dev_hdl) {
-        ESP_LOGW(EXT_HUB_TAG, "Multiple Hubs not supported, use menuconfig to enable feature");
+        ESP_LOGW(EXT_HUB_TAG, "Multiple Hubs support disabled, Hub device was not initialized");
         ret = ESP_ERR_NOT_SUPPORTED;
         goto fail;
     }
diff --git a/components/usb/ext_port.c b/components/usb/ext_port.c
index 541eb60a50a..efce9ed7de3 100644
--- a/components/usb/ext_port.c
+++ b/components/usb/ext_port.c
@@ -25,9 +25,9 @@
 #define EXT_PORT_RESET_ATTEMPTS     1
 #endif
 // Delay in ms after sending the SetFeature() class specific request
-#define EXT_PORT_RESET_CUSTOM_DELAY         CONFIG_USB_HOST_EXT_PORT_CUSTOM_RESET_ENABLE
-#define EXT_PORT_RESET_CUSTOM_DELAY_MS      CONFIG_USB_HOST_EXT_PORT_CUSTOM_RESET_MS
-#define EXT_PORT_RESET_DEFAULT_DELAY_MS     100
+#define EXT_PORT_RESET_RECOVERY_DELAY_MS       CONFIG_USB_HOST_EXT_PORT_RESET_RECOVERY_DELAY_MS
+#define EXT_PORT_POWER_ON_CUSTOM_DELAY         CONFIG_USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_ENABLE
+#define EXT_PORT_POWER_ON_CUSTOM_DELAY_MS      CONFIG_USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_MS
 
 /**
  * @brief External Port driver action flags
@@ -80,7 +80,7 @@ struct ext_port_s {
         // Port related constant members
         ext_hub_handle_t ext_hub_hdl;           /**< Ports' parent External Hub handle */
         uint8_t port_num;                       /**< Ports' parent External Hub Port number */
-        int reset_delay_ms;                     /**< Ports' Power on time to Power Good, ms */
+        int power_on_delay_ms;                  /**< Ports' Power on time to Power Good, ms */
     } constant;                                 /**< Constant members. Do not change after installation thus do not require a critical section or mutex */
 };
 
@@ -262,9 +262,17 @@ static esp_err_t port_set_feature(ext_port_t *ext_port, const usb_hub_port_featu
     }
     // Every set feature requires status update
     ext_port->flags.status_outdated = 1;
-    // PowerOn to PowerGood delay for port
-    if (feature == USB_FEATURE_PORT_RESET) {
-        vTaskDelay(pdMS_TO_TICKS(ext_port->constant.reset_delay_ms));
+    switch (feature) {
+    case USB_FEATURE_PORT_POWER:
+        // PowerOn to PowerGood delay for port
+        vTaskDelay(pdMS_TO_TICKS(ext_port->constant.power_on_delay_ms));
+        break;
+    case USB_FEATURE_PORT_RESET:
+        // Port has reset, give the port some time to recover
+        vTaskDelay(pdMS_TO_TICKS(EXT_PORT_RESET_RECOVERY_DELAY_MS));
+        break;
+    default:
+        break;
     }
     return ret;
 }
@@ -451,13 +459,13 @@ static esp_err_t port_alloc(ext_hub_handle_t ext_hub_hdl, usb_device_handle_t pa
     ext_port->constant.parent_dev_addr = parent_dev_addr;
     ext_port->constant.ext_hub_hdl = ext_hub_hdl;
     ext_port->constant.port_num = parent_port_num;
-#if (EXT_PORT_RESET_CUSTOM_DELAY)
-    ext_port->constant.reset_delay_ms = EXT_PORT_RESET_CUSTOM_DELAY_MS;
+#if (EXT_PORT_POWER_ON_CUSTOM_DELAY)
+    ext_port->constant.power_on_delay_ms = EXT_PORT_POWER_ON_CUSTOM_DELAY_MS;
 #else
-    ext_port->constant.reset_delay_ms = (port_delay_ms == 0)
-                                        ? EXT_PORT_RESET_DEFAULT_DELAY_MS
-                                        : port_delay_ms;
-#endif // EXT_PORT_POWER_ON_CUSTOM
+    // We don't need any additional delay in case port_delay_ms == 0, because this usually means
+    // that parent Hub device has no power switches
+    ext_port->constant.power_on_delay_ms = port_delay_ms;
+#endif // EXT_PORT_POWER_ON_CUSTOM_DELAY
 
     ext_port->state = USB_PORT_STATE_NOT_CONFIGURED;
     ext_port->dev_state = PORT_DEV_NOT_PRESENT;
@@ -465,7 +473,7 @@ static esp_err_t port_alloc(ext_hub_handle_t ext_hub_hdl, usb_device_handle_t pa
     ESP_LOGD(EXT_PORT_TAG, "[%d:%d] Port has been added (PwrOn2PwrGood=%d ms)",
              ext_port->constant.parent_dev_addr,
              ext_port->constant.port_num,
-             ext_port->constant.reset_delay_ms);
+             ext_port->constant.power_on_delay_ms);
 
     *port_obj = ext_port;
     return ESP_OK;
@@ -555,8 +563,6 @@ static bool handle_port_status(ext_port_t *ext_port)
         ESP_LOGD(EXT_PORT_TAG, "[%d:%d] Port still in reset, wait and repeat get status...",
                  ext_port->constant.parent_dev_addr,
                  ext_port->constant.port_num);
-        // PowerOn to PowerGood delay for port
-        vTaskDelay(pdMS_TO_TICKS(ext_port->constant.reset_delay_ms));
         port_request_status(ext_port);
         need_processing = true;
     }
diff --git a/components/usb/hcd_dwc.c b/components/usb/hcd_dwc.c
index a5ea7d736ff..21e13db3015 100644
--- a/components/usb/hcd_dwc.c
+++ b/components/usb/hcd_dwc.c
@@ -10,13 +10,14 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "freertos/semphr.h"
+#include "esp_private/critical_section.h"
 #include "esp_heap_caps.h"
 #include "esp_intr_alloc.h"
-#include "soc/interrupts.h" // For interrupt index
 #include "esp_err.h"
 #include "esp_log.h"
+
+#include "soc/usb_dwc_periph.h"
 #include "hal/usb_dwc_hal.h"
-#include "hal/usb_dwc_types.h"
 #include "hcd.h"
 #include "usb_private.h"
 #include "usb/usb_types_ch9.h"
@@ -28,15 +29,6 @@
 
 // ----------------------------------------------------- Macros --------------------------------------------------------
 
-// ------------------ Target specific ----------------------
-// TODO: Remove target specific section after support for multiple USB peripherals is implemented
-#include "sdkconfig.h"
-#if (CONFIG_IDF_TARGET_ESP32P4)
-#define USB_INTR ETS_USB_OTG_INTR_SOURCE
-#else
-#define USB_INTR ETS_USB_INTR_SOURCE
-#endif
-
 // --------------------- Constants -------------------------
 
 #define INIT_DELAY_MS                           30  // A delay of at least 25ms to enter Host mode. Make it 30ms to be safe
@@ -64,30 +56,28 @@
 #define XFER_LIST_LEN_ISOC                      64  // Implement longer ISOC transfer list to give us enough space for additional timing margin
 #define XFER_LIST_ISOC_MARGIN                   3   // The 1st ISOC transfer is scheduled 3 (micro)frames later so we have enough timing margin
 
-// ------------------------ Flags --------------------------
+// ------------------------ Internal --------------------------
 
 /**
- * @brief Bit masks for the HCD to use in the URBs reserved_flags field
+ * @brief Values for the HCD to use in the URBs hcd_var field
  *
- * The URB object has a reserved_flags member for host stack's internal use. The following flags will be set in
- * reserved_flags in order to keep track of state of an URB within the HCD.
+ * The URB object has a hcd_var member for host stack's internal use. The following values will be set in
+ * hcd_var in order to keep track of state of an URB within the HCD.
  */
 #define URB_HCD_STATE_IDLE                      0   // The URB is not enqueued in an HCD pipe
 #define URB_HCD_STATE_PENDING                   1   // The URB is enqueued and pending execution
 #define URB_HCD_STATE_INFLIGHT                  2   // The URB is currently in flight
 #define URB_HCD_STATE_DONE                      3   // The URB has completed execution or is retired, and is waiting to be dequeued
 
-#define URB_HCD_STATE_SET(reserved_flags, state)    (reserved_flags = (reserved_flags & ~URB_HCD_STATE_MASK) | state)
-#define URB_HCD_STATE_GET(reserved_flags)           (reserved_flags & URB_HCD_STATE_MASK)
-
 // -------------------- Convenience ------------------------
 
 const char *HCD_DWC_TAG = "HCD DWC";
 
-#define HCD_ENTER_CRITICAL_ISR()                portENTER_CRITICAL_ISR(&hcd_lock)
-#define HCD_EXIT_CRITICAL_ISR()                 portEXIT_CRITICAL_ISR(&hcd_lock)
-#define HCD_ENTER_CRITICAL()                    portENTER_CRITICAL(&hcd_lock)
-#define HCD_EXIT_CRITICAL()                     portEXIT_CRITICAL(&hcd_lock)
+DEFINE_CRIT_SECTION_LOCK_STATIC(hcd_lock);
+#define HCD_ENTER_CRITICAL_ISR()       esp_os_enter_critical_isr(&hcd_lock)
+#define HCD_EXIT_CRITICAL_ISR()        esp_os_exit_critical_isr(&hcd_lock)
+#define HCD_ENTER_CRITICAL()           esp_os_enter_critical(&hcd_lock)
+#define HCD_EXIT_CRITICAL()            esp_os_exit_critical(&hcd_lock)
 
 #define HCD_CHECK(cond, ret_val) ({                                         \
             if (!(cond)) {                                                  \
@@ -270,7 +260,6 @@ typedef struct {
     intr_handle_t isr_hdl;
 } hcd_obj_t;
 
-static portMUX_TYPE hcd_lock = portMUX_INITIALIZER_UNLOCKED;
 static hcd_obj_t *s_hcd_obj = NULL;     // Note: "s_" is for the static pointer
 
 // ------------------------------------------------- Forward Declare ---------------------------------------------------
@@ -1005,7 +994,7 @@ esp_err_t hcd_install(const hcd_config_t *config)
         goto port_alloc_err;
     }
     // Allocate interrupt
-    err_ret = esp_intr_alloc(USB_INTR,
+    err_ret = esp_intr_alloc(usb_dwc_info.controllers[0].irq,
                              config->intr_flags | ESP_INTR_FLAG_INTRDISABLED,  // The interrupt must be disabled until the port is initialized
                              intr_hdlr_main,
                              (void *)p_hcd_obj_dmy->port_obj,
@@ -1287,7 +1276,9 @@ esp_err_t hcd_port_init(int port_number, const hcd_port_config_t *port_config, h
     port_obj->callback = port_config->callback;
     port_obj->callback_arg = port_config->callback_arg;
     port_obj->context = port_config->context;
-    usb_dwc_hal_init(port_obj->hal);
+    usb_dwc_hal_init(port_obj->hal, 0);
+    port_obj->hal->channels.hdls = calloc(port_obj->hal->constant_config.chan_num_total, sizeof(usb_dwc_hal_chan_t*));
+    HCD_CHECK_FROM_CRIT(port_obj->hal->channels.hdls != NULL, ESP_ERR_NO_MEM);
     port_obj->initialized = true;
     // Clear the frame list. We set the frame list register and enable periodic scheduling after a successful reset
     memset(port_obj->frame_list, 0, FRAME_LIST_LEN * sizeof(uint32_t));
@@ -1311,6 +1302,7 @@ esp_err_t hcd_port_deinit(hcd_port_handle_t port_hdl)
                         ESP_ERR_INVALID_STATE);
     port->initialized = false;
     esp_intr_disable(s_hcd_obj->isr_hdl);
+    free(port->hal->channels.hdls);
     usb_dwc_hal_deinit(port->hal);
     HCD_EXIT_CRITICAL();
 
@@ -1423,14 +1415,14 @@ esp_err_t hcd_port_recover(hcd_port_handle_t port_hdl)
                         && port->num_pipes_idle == 0 && port->num_pipes_queued == 0
                         && port->flags.val == 0 && port->task_waiting_port_notif == NULL,
                         ESP_ERR_INVALID_STATE);
+
     // We are about to do a soft reset on the peripheral. Disable the peripheral throughout
     esp_intr_disable(s_hcd_obj->isr_hdl);
     usb_dwc_hal_core_soft_reset(port->hal);
     port->state = HCD_PORT_STATE_NOT_POWERED;
     port->last_event = HCD_PORT_EVENT_NONE;
     port->flags.val = 0;
-    // Soft reset wipes all registers so we need to reinitialize the HAL
-    usb_dwc_hal_init(port->hal);
+
     // Clear the frame list. We set the frame list register and enable periodic scheduling after a successful reset
     memset(port->frame_list, 0, FRAME_LIST_LEN * sizeof(uint32_t));
     esp_intr_enable(s_hcd_obj->isr_hdl);
@@ -1825,6 +1817,8 @@ esp_err_t hcd_pipe_alloc(hcd_port_handle_t port_hdl, const hcd_pipe_config_t *pi
     bool chan_allocated = usb_dwc_hal_chan_alloc(port->hal, pipe->chan_obj, (void *) pipe);
     if (!chan_allocated) {
         HCD_EXIT_CRITICAL();
+        // The only reason why alloc channel could return false is no more free channels
+        ESP_LOGE(HCD_DWC_TAG, "No more HCD channels available");
         ret = ESP_ERR_NOT_SUPPORTED;
         goto err;
     }
diff --git a/components/usb/hub.c b/components/usb/hub.c
index 079a18f351a..e39e741d694 100644
--- a/components/usb/hub.c
+++ b/components/usb/hub.c
@@ -9,10 +9,9 @@
 #include <stdbool.h>
 #include <string.h>
 #include <sys/queue.h>
-#include "freertos/FreeRTOS.h"
-#include "freertos/portmacro.h"
 #include "esp_err.h"
 #include "esp_heap_caps.h"
+#include "esp_private/critical_section.h"
 #include "esp_log.h"
 #include "usb_private.h"
 #include "hcd.h"
@@ -107,16 +106,16 @@ typedef struct {
 } hub_driver_t;
 
 static hub_driver_t *p_hub_driver_obj = NULL;
-static portMUX_TYPE hub_driver_lock = portMUX_INITIALIZER_UNLOCKED;
 
 const char *HUB_DRIVER_TAG = "HUB";
 
-#define HUB_DRIVER_ENTER_CRITICAL_ISR()                 portENTER_CRITICAL_ISR(&hub_driver_lock)
-#define HUB_DRIVER_EXIT_CRITICAL_ISR()                  portEXIT_CRITICAL_ISR(&hub_driver_lock)
-#define HUB_DRIVER_ENTER_CRITICAL()                     portENTER_CRITICAL(&hub_driver_lock)
-#define HUB_DRIVER_EXIT_CRITICAL()                      portEXIT_CRITICAL(&hub_driver_lock)
-#define HUB_DRIVER_ENTER_CRITICAL_SAFE()                portENTER_CRITICAL_SAFE(&hub_driver_lock)
-#define HUB_DRIVER_EXIT_CRITICAL_SAFE()                 portEXIT_CRITICAL_SAFE(&hub_driver_lock)
+DEFINE_CRIT_SECTION_LOCK_STATIC(hub_driver_lock);
+#define HUB_DRIVER_ENTER_CRITICAL_ISR()       esp_os_enter_critical_isr(&hub_driver_lock)
+#define HUB_DRIVER_EXIT_CRITICAL_ISR()        esp_os_exit_critical_isr(&hub_driver_lock)
+#define HUB_DRIVER_ENTER_CRITICAL()           esp_os_enter_critical(&hub_driver_lock)
+#define HUB_DRIVER_EXIT_CRITICAL()            esp_os_exit_critical(&hub_driver_lock)
+#define HUB_DRIVER_ENTER_CRITICAL_SAFE()      esp_os_enter_critical_safe(&hub_driver_lock)
+#define HUB_DRIVER_EXIT_CRITICAL_SAFE()       esp_os_exit_critical_safe(&hub_driver_lock)
 
 #define HUB_DRIVER_CHECK(cond, ret_val) ({              \
             if (!(cond)) {                              \
@@ -779,14 +778,35 @@ esp_err_t hub_port_disable(usb_device_handle_t parent_dev_hdl, uint8_t parent_po
     return ret;
 }
 
-#if ENABLE_USB_HUBS
 esp_err_t hub_notify_new_dev(uint8_t dev_addr)
 {
     HUB_DRIVER_ENTER_CRITICAL();
     HUB_DRIVER_CHECK_FROM_CRIT(p_hub_driver_obj != NULL, ESP_ERR_INVALID_STATE);
     HUB_DRIVER_EXIT_CRITICAL();
 
-    return ext_hub_new_dev(dev_addr);
+    esp_err_t ret;
+#if ENABLE_USB_HUBS
+    ret = ext_hub_new_dev(dev_addr);
+#else
+    // Verify the device descriptor and if the bDeviceClass is a Hub class,
+    // show the warning message, that Hub support feature is not enabled
+    usb_device_handle_t dev_hdl = NULL;
+    const usb_device_desc_t *device_desc = NULL;
+    // Open device
+    if (usbh_devs_open(dev_addr, &dev_hdl) == ESP_OK) {
+        // Get Device Descriptor
+        if (usbh_dev_get_desc(dev_hdl, &device_desc) == ESP_OK) {
+            if (device_desc->bDeviceClass == USB_CLASS_HUB) {
+                ESP_LOGW(HUB_DRIVER_TAG, "External Hubs support disabled, Hub device was not initialized");
+            }
+        }
+        // Close device
+        usbh_dev_close(dev_hdl);
+    }
+    // Logic should not stop the flow, so no error to return
+    ret = ESP_OK;
+#endif // ENABLE_USB_HUBS
+    return ret;
 }
 
 esp_err_t hub_notify_dev_gone(uint8_t dev_addr)
@@ -795,9 +815,17 @@ esp_err_t hub_notify_dev_gone(uint8_t dev_addr)
     HUB_DRIVER_CHECK_FROM_CRIT(p_hub_driver_obj != NULL, ESP_ERR_INVALID_STATE);
     HUB_DRIVER_EXIT_CRITICAL();
 
-    return ext_hub_dev_gone(dev_addr);
+    esp_err_t ret;
+#if ENABLE_USB_HUBS
+    ret = ext_hub_dev_gone(dev_addr);
+#else
+    // Nothing to do, while Hubs support is not enabled
+    ret = ESP_OK;
+#endif // ENABLE_USB_HUBS
+    return ret;
 }
 
+#if (ENABLE_USB_HUBS)
 esp_err_t hub_notify_all_free(void)
 {
     HUB_DRIVER_ENTER_CRITICAL();
diff --git a/components/usb/private_include/hub.h b/components/usb/private_include/hub.h
index e3efaac9bf8..f563a56f283 100644
--- a/components/usb/private_include/hub.h
+++ b/components/usb/private_include/hub.h
@@ -191,13 +191,13 @@ esp_err_t hub_port_active(usb_device_handle_t parent_dev_hdl, uint8_t parent_por
  */
 esp_err_t hub_port_disable(usb_device_handle_t parent_dev_hdl, uint8_t parent_port_num);
 
-#if ENABLE_USB_HUBS
 /**
  * @brief Notify Hub driver that new device has been attached
  *
  * If device is has a HUB class, then it will be added as External Hub to Hub Driver.
  *
  * @note This function should only be called from the Host Library task
+ * @note If the Hub support feature is disabled and device has a Hub class, only the warning message will be shown.
  *
  * @param[in] dev_addr  Device bus address
  *
@@ -213,6 +213,7 @@ esp_err_t hub_notify_new_dev(uint8_t dev_addr);
  * If the device was an External Hub, then it will be removed from the Hub Driver.
  *
  * @note This function should only be called from the Host Library task
+ * @note If the Hub support feature is disabled, no additional logic requires here.
  *
  * @param[in] dev_addr  Device bus address
  *
@@ -222,6 +223,7 @@ esp_err_t hub_notify_new_dev(uint8_t dev_addr);
  */
 esp_err_t hub_notify_dev_gone(uint8_t dev_addr);
 
+#if ENABLE_USB_HUBS
 /**
  * @brief Notify Hub driver that all devices should be freed
  *
diff --git a/components/usb/test_apps/hcd/main/test_hcd_isoc.c b/components/usb/test_apps/hcd/main/test_hcd_isoc.c
index 1f6420bf81c..2f5f837af42 100644
--- a/components/usb/test_apps/hcd/main/test_hcd_isoc.c
+++ b/components/usb/test_apps/hcd/main/test_hcd_isoc.c
@@ -6,7 +6,7 @@
 
 #include <stdio.h>
 #include <string.h>
-#include "soc/usb_dwc_cfg.h"
+#include "hal/usb_dwc_ll.h" // For USB-DWC configuration
 #include "freertos/FreeRTOS.h"
 #include "freertos/semphr.h"
 #include "unity.h"
@@ -17,7 +17,7 @@
 #define NUM_URBS                3
 #define NUM_PACKETS_PER_URB     3
 #define POST_ENQUEUE_DELAY_US   20
-#define ENQUEUE_DELAY (OTG_HSPHY_INTERFACE ? 100 : 500) // With this delay we want to enqueue the URBs at different times
+#define ENQUEUE_DELAY (usb_dwc_ll_ghwcfg_get_hsphy_type(USB_DWC_LL_GET_HW(0)) ? 100 : 500) // With this delay we want to enqueue the URBs at different times
 
 /*
 Test HCD ISOC pipe URBs
@@ -126,12 +126,12 @@ TEST_CASE("Test HCD isochronous pipe URBs all", "[isoc][full_speed][high_speed]"
     uint8_t dev_addr = test_hcd_enum_device(default_pipe);
 
     urb_t *urb_list[NUM_URBS];
-    hcd_pipe_handle_t unused_pipes[OTG_NUM_HOST_CHAN];
+    hcd_pipe_handle_t unused_pipes[16];
     const usb_ep_desc_t *out_ep_desc = dev_isoc_get_out_ep_desc(port_speed);
     const int isoc_packet_size = USB_EP_DESC_GET_MPS(out_ep_desc);
 
-    // For all channels
-    for (int channel = 0; channel < OTG_NUM_HOST_CHAN - 1; channel++) {
+    // For all channels (except channel allocated for EP0)
+    for (int channel = 0; channel < usb_dwc_ll_ghwcfg_get_channel_num(USB_DWC_LL_GET_HW(0)) - 1; channel++) {
         // Allocate unused pipes, so the active isoc_out_pipe uses different channel index
         for (int ch = 0; ch < channel; ch++) {
             unused_pipes[ch] = test_hcd_pipe_alloc(port_hdl, out_ep_desc, dev_addr + 1, port_speed);
diff --git a/components/usb/test_apps/hcd/sdkconfig.defaults b/components/usb/test_apps/hcd/sdkconfig.defaults
index 0632edf7579..d433503fbfd 100644
--- a/components/usb/test_apps/hcd/sdkconfig.defaults
+++ b/components/usb/test_apps/hcd/sdkconfig.defaults
@@ -6,3 +6,4 @@ CONFIG_HEAP_POISONING_COMPREHENSIVE=y
 # CONFIG_UNITY_ENABLE_FLOAT is not set
 # CONFIG_UNITY_ENABLE_DOUBLE is not set
 CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y
+CONFIG_USB_HOST_HUBS_SUPPORTED=y
diff --git a/components/usb/test_apps/usb_host/sdkconfig.defaults b/components/usb/test_apps/usb_host/sdkconfig.defaults
index 0632edf7579..d433503fbfd 100644
--- a/components/usb/test_apps/usb_host/sdkconfig.defaults
+++ b/components/usb/test_apps/usb_host/sdkconfig.defaults
@@ -6,3 +6,4 @@ CONFIG_HEAP_POISONING_COMPREHENSIVE=y
 # CONFIG_UNITY_ENABLE_FLOAT is not set
 # CONFIG_UNITY_ENABLE_DOUBLE is not set
 CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL=y
+CONFIG_USB_HOST_HUBS_SUPPORTED=y
diff --git a/components/usb/usb_host.c b/components/usb/usb_host.c
index 644a5e777e5..50a3722cd67 100644
--- a/components/usb/usb_host.c
+++ b/components/usb/usb_host.c
@@ -16,6 +16,7 @@ Warning: The USB Host Library API is still a beta version and may be subject to
 #include "freertos/task.h"
 #include "freertos/queue.h"
 #include "freertos/semphr.h"
+#include "esp_private/critical_section.h"
 #include "esp_err.h"
 #include "esp_log.h"
 #include "esp_heap_caps.h"
@@ -26,14 +27,13 @@ Warning: The USB Host Library API is still a beta version and may be subject to
 #include "esp_private/usb_phy.h"
 #include "usb/usb_host.h"
 
-static portMUX_TYPE host_lock = portMUX_INITIALIZER_UNLOCKED;
-
-#define HOST_ENTER_CRITICAL_ISR()       portENTER_CRITICAL_ISR(&host_lock)
-#define HOST_EXIT_CRITICAL_ISR()        portEXIT_CRITICAL_ISR(&host_lock)
-#define HOST_ENTER_CRITICAL()           portENTER_CRITICAL(&host_lock)
-#define HOST_EXIT_CRITICAL()            portEXIT_CRITICAL(&host_lock)
-#define HOST_ENTER_CRITICAL_SAFE()      portENTER_CRITICAL_SAFE(&host_lock)
-#define HOST_EXIT_CRITICAL_SAFE()       portEXIT_CRITICAL_SAFE(&host_lock)
+DEFINE_CRIT_SECTION_LOCK_STATIC(host_lock);
+#define HOST_ENTER_CRITICAL_ISR()       esp_os_enter_critical_isr(&host_lock)
+#define HOST_EXIT_CRITICAL_ISR()        esp_os_exit_critical_isr(&host_lock)
+#define HOST_ENTER_CRITICAL()           esp_os_enter_critical(&host_lock)
+#define HOST_EXIT_CRITICAL()            esp_os_exit_critical(&host_lock)
+#define HOST_ENTER_CRITICAL_SAFE()      esp_os_enter_critical_safe(&host_lock)
+#define HOST_EXIT_CRITICAL_SAFE()       esp_os_exit_critical_safe(&host_lock)
 
 #define HOST_CHECK(cond, ret_val) ({                                        \
             if (!(cond)) {                                                  \
@@ -309,21 +309,21 @@ static void usbh_event_callback(usbh_event_data_t *event_data, void *arg)
         break;
     }
     case USBH_EVENT_NEW_DEV: {
+        // Internal client
+        hub_notify_new_dev(event_data->new_dev_data.dev_addr);
+        // External clients
         // Prepare a NEW_DEV client event message, the send it to all clients
         usb_host_client_event_msg_t event_msg = {
             .event = USB_HOST_CLIENT_EVENT_NEW_DEV,
             .new_dev.address = event_data->new_dev_data.dev_addr,
         };
         send_event_msg_to_clients(&event_msg, true, 0);
-#if ENABLE_USB_HUBS
-        hub_notify_new_dev(event_data->new_dev_data.dev_addr);
-#endif // ENABLE_USB_HUBS
         break;
     }
     case USBH_EVENT_DEV_GONE: {
-#if ENABLE_USB_HUBS
+        // Internal client
         hub_notify_dev_gone(event_data->new_dev_data.dev_addr);
-#endif // ENABLE_USB_HUBS
+        // External clients
         // Prepare event msg, send only to clients that have opened the device
         usb_host_client_event_msg_t event_msg = {
             .event = USB_HOST_CLIENT_EVENT_DEV_GONE,
@@ -818,7 +818,7 @@ esp_err_t usb_host_client_register(const usb_host_client_config_t *client_config
         vSemaphoreDelete(event_sem);
     }
     heap_caps_free(client_obj);
-    return ESP_OK;
+    return ret;
 }
 
 esp_err_t usb_host_client_deregister(usb_host_client_handle_t client_hdl)
diff --git a/components/usb/usb_phy.c b/components/usb/usb_phy.c
index 7ae5e5f3826..220e6317321 100644
--- a/components/usb/usb_phy.c
+++ b/components/usb/usb_phy.c
@@ -6,11 +6,11 @@
 
 #include <esp_types.h>
 #include <string.h>
-#include "freertos/FreeRTOS.h"
 #include "esp_log.h"
 #include "esp_check.h"
 #include "esp_private/periph_ctrl.h"
 #include "esp_private/usb_phy.h"
+#include "esp_private/critical_section.h"
 #include "soc/usb_dwc_periph.h"
 #include "hal/usb_wrap_hal.h"
 #include "hal/usb_serial_jtag_hal.h"
@@ -61,7 +61,10 @@ typedef struct {
 } usb_iopin_dsc_t;
 
 static phy_ctrl_obj_t *p_phy_ctrl_obj = NULL;
-static portMUX_TYPE phy_spinlock = portMUX_INITIALIZER_UNLOCKED;
+
+DEFINE_CRIT_SECTION_LOCK_STATIC(phy_spinlock);
+#define PHY_ENTER_CRITICAL()           esp_os_enter_critical(&phy_spinlock)
+#define PHY_EXIT_CRITICAL()            esp_os_exit_critical(&phy_spinlock)
 
 static esp_err_t phy_iopins_configure(const usb_iopin_dsc_t *usb_periph_iopins, int iopins_num)
 {
@@ -235,29 +238,29 @@ esp_err_t usb_phy_action(usb_phy_handle_t handle, usb_phy_action_t action)
 
 static esp_err_t usb_phy_install(void)
 {
-    portENTER_CRITICAL(&phy_spinlock);
+    PHY_ENTER_CRITICAL();
     if (p_phy_ctrl_obj) {
         // p_phy_ctrl_obj already installed, return immediately
-        portEXIT_CRITICAL(&phy_spinlock);
+        PHY_EXIT_CRITICAL();
         return ESP_OK;
     }
-    portEXIT_CRITICAL(&phy_spinlock);
+    PHY_EXIT_CRITICAL();
 
     esp_err_t ret = ESP_OK;
     phy_ctrl_obj_t *phy_ctrl_obj = (phy_ctrl_obj_t *) calloc(1, sizeof(phy_ctrl_obj_t));
     ESP_GOTO_ON_FALSE(phy_ctrl_obj, ESP_ERR_NO_MEM, cleanup, USBPHY_TAG, "no mem for USB_PHY driver");
 
-    portENTER_CRITICAL(&phy_spinlock);
+    PHY_ENTER_CRITICAL();
     if (!p_phy_ctrl_obj) {
         p_phy_ctrl_obj = phy_ctrl_obj;
         p_phy_ctrl_obj->ref_count = 0;
     } else {
         // p_phy_ctrl_obj already installed, need to free resource
-        portEXIT_CRITICAL(&phy_spinlock);
+        PHY_EXIT_CRITICAL();
         goto cleanup;
     }
     // Enable USB peripheral and reset the register
-    portEXIT_CRITICAL(&phy_spinlock);
+    PHY_EXIT_CRITICAL();
     USB_WRAP_RCC_ATOMIC() {
         usb_wrap_ll_enable_bus_clock(true);
         usb_wrap_ll_reset_register();
@@ -281,7 +284,7 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
     phy_context_t *phy_context = (phy_context_t *) calloc(1, sizeof(phy_context_t));
     ESP_GOTO_ON_FALSE(phy_context, ESP_ERR_NO_MEM, cleanup, USBPHY_TAG, "no mem for phy context");
 
-    portENTER_CRITICAL(&phy_spinlock);
+    PHY_ENTER_CRITICAL();
     usb_phy_get_phy_status(config->target, &phy_context->status);
     if (phy_context->status == USB_PHY_STATUS_FREE) {
         new_phy = true;
@@ -292,7 +295,7 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
             p_phy_ctrl_obj->internal_phy = phy_context;
         }
     }
-    portEXIT_CRITICAL(&phy_spinlock);
+    PHY_EXIT_CRITICAL();
     ESP_GOTO_ON_FALSE(new_phy, ESP_ERR_INVALID_STATE, cleanup, USBPHY_TAG, "selected PHY is in use");
 
     phy_context->target = config->target;
@@ -354,7 +357,7 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
 static void phy_uninstall(void)
 {
     phy_ctrl_obj_t *p_phy_ctrl_obj_free = NULL;
-    portENTER_CRITICAL(&phy_spinlock);
+    PHY_ENTER_CRITICAL();
     if (p_phy_ctrl_obj->ref_count == 0) {
         p_phy_ctrl_obj_free = p_phy_ctrl_obj;
         p_phy_ctrl_obj = NULL;
@@ -363,7 +366,7 @@ static void phy_uninstall(void)
             usb_wrap_ll_enable_bus_clock(false);
         }
     }
-    portEXIT_CRITICAL(&phy_spinlock);
+    PHY_EXIT_CRITICAL();
     free(p_phy_ctrl_obj_free);
 }
 
@@ -371,7 +374,7 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle)
 {
     ESP_RETURN_ON_FALSE(handle, ESP_ERR_INVALID_ARG, USBPHY_TAG, "handle argument is invalid");
 
-    portENTER_CRITICAL(&phy_spinlock);
+    PHY_ENTER_CRITICAL();
     p_phy_ctrl_obj->ref_count--;
     if (handle->target == USB_PHY_TARGET_EXT) {
         p_phy_ctrl_obj->external_phy = NULL;
@@ -380,7 +383,7 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle)
         usb_wrap_hal_phy_disable_pull_override(&handle->wrap_hal);
         p_phy_ctrl_obj->internal_phy = NULL;
     }
-    portEXIT_CRITICAL(&phy_spinlock);
+    PHY_EXIT_CRITICAL();
     free(handle->iopins);
     free(handle);
     phy_uninstall();
diff --git a/components/usb/usb_phy_p4.c b/components/usb/usb_phy_p4.c
index b81e9be5483..43611c393c4 100644
--- a/components/usb/usb_phy_p4.c
+++ b/components/usb/usb_phy_p4.c
@@ -4,47 +4,33 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// TODO: Refactor during the IDF-9198
-#include "sdkconfig.h"
-#include "soc/soc_caps.h"
-#include "soc/usb_dwc_cfg.h"
-#include "hal/usb_utmi_ll.h" // We don't have usb_utmi_hal yet
-#include "esp_private/periph_ctrl.h"
-// TODO: Remove this file when proper support of P4 PHYs is implemented IDF-7323
+// TODO: Remove this file when proper support of P4 PHYs is implemented IDF-11144
+#include "hal/usb_utmi_hal.h"
 #include "esp_private/usb_phy.h"
-#include "esp_private/periph_ctrl.h"
 
+#include "soc/soc_caps.h"
 #if SOC_RCC_IS_INDEPENDENT
 #define USB_UTMI_BUS_CLK_ATOMIC()
 #else
+#include "esp_private/periph_ctrl.h"
 #define USB_UTMI_BUS_CLK_ATOMIC()       PERIPH_RCC_ATOMIC()
 #endif
 
+static usb_utmi_hal_context_t s_utmi_hal_context;
+
 esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_ret)
 {
-#if (OTG_HSPHY_INTERFACE != 0)
-#if CONFIG_IDF_TARGET_ESP32P4
     USB_UTMI_BUS_CLK_ATOMIC() {
-        usb_utmi_ll_enable_bus_clock(true);
-        usb_utmi_ll_reset_register();
+        usb_utmi_hal_init(&s_utmi_hal_context);
     }
-    /*
-    Additional setting to solve missing DCONN event on ESP32P4 (IDF-9953).
-
-    Note: On ESP32P4, the HP_SYSTEM_OTG_SUSPENDM is not connected to 1 by hardware.
-    For correct detection of the device detaching, internal signal should be set to 1 by the software.
-    */
-    usb_utmi_ll_enable_precise_detection(true);
-    usb_utmi_ll_configure_ls(&USB_UTMI, true);
-#endif // CONFIG_IDF_TARGET_ESP32P4
-#endif // (OTG_HSPHY_INTERFACE != 0)
     return ESP_OK;
 }
 
 esp_err_t usb_del_phy(usb_phy_handle_t handle)
 {
+    // Note: handle argument is not checked, because we don't have phy_handle for P4 yet
     USB_UTMI_BUS_CLK_ATOMIC() {
-        usb_utmi_ll_enable_bus_clock(false);
+        usb_utmi_hal_disable();
     }
     return ESP_OK;
 }
diff --git a/components/usb/usbh.c b/components/usb/usbh.c
index c515fc01ca5..54355ace682 100644
--- a/components/usb/usbh.c
+++ b/components/usb/usbh.c
@@ -10,9 +10,8 @@
 #include <assert.h>
 #include <sys/queue.h>
 #include "freertos/FreeRTOS.h"
-#include "freertos/portmacro.h"
-#include "freertos/task.h"
 #include "freertos/semphr.h"
+#include "esp_private/critical_section.h"
 #include "esp_err.h"
 #include "esp_log.h"
 #include "esp_heap_caps.h"
@@ -117,16 +116,15 @@ typedef struct {
 
 static usbh_t *p_usbh_obj = NULL;
 
-static portMUX_TYPE usbh_lock = portMUX_INITIALIZER_UNLOCKED;
-
 const char *USBH_TAG = "USBH";
 
-#define USBH_ENTER_CRITICAL_ISR()       portENTER_CRITICAL_ISR(&usbh_lock)
-#define USBH_EXIT_CRITICAL_ISR()        portEXIT_CRITICAL_ISR(&usbh_lock)
-#define USBH_ENTER_CRITICAL()           portENTER_CRITICAL(&usbh_lock)
-#define USBH_EXIT_CRITICAL()            portEXIT_CRITICAL(&usbh_lock)
-#define USBH_ENTER_CRITICAL_SAFE()      portENTER_CRITICAL_SAFE(&usbh_lock)
-#define USBH_EXIT_CRITICAL_SAFE()       portEXIT_CRITICAL_SAFE(&usbh_lock)
+DEFINE_CRIT_SECTION_LOCK_STATIC(usbh_lock);
+#define USBH_ENTER_CRITICAL_ISR()       esp_os_enter_critical_isr(&usbh_lock)
+#define USBH_EXIT_CRITICAL_ISR()        esp_os_exit_critical_isr(&usbh_lock)
+#define USBH_ENTER_CRITICAL()           esp_os_enter_critical(&usbh_lock)
+#define USBH_EXIT_CRITICAL()            esp_os_exit_critical(&usbh_lock)
+#define USBH_ENTER_CRITICAL_SAFE()      esp_os_enter_critical_safe(&usbh_lock)
+#define USBH_EXIT_CRITICAL_SAFE()       esp_os_exit_critical_safe(&usbh_lock)
 
 #define USBH_CHECK(cond, ret_val) ({                                        \
             if (!(cond)) {                                                  \
diff --git a/components/vfs/include/esp_vfs.h b/components/vfs/include/esp_vfs.h
index 655bbf5790f..8e71115a435 100644
--- a/components/vfs/include/esp_vfs.h
+++ b/components/vfs/include/esp_vfs.h
@@ -29,6 +29,8 @@
 #include <string.h>
 #include "sdkconfig.h"
 
+#include "esp_vfs_ops.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -62,20 +64,11 @@ extern "C" {
  */
 #define ESP_VFS_FLAG_READONLY_FS (1 << 2)
 
-/*
- * @brief VFS identificator used for esp_vfs_register_with_id()
- */
-typedef int esp_vfs_id_t;
-
 /**
- * @brief VFS semaphore type for select()
- *
+ * Flag which indicates that VFS structure should be freed upon unregistering.
+ * @note Free if false, do not free if true
  */
-typedef struct
-{
-    bool is_sem_local;      /*!< type of "sem" is SemaphoreHandle_t when true, defined by socket driver otherwise */
-    void *sem;              /*!< semaphore instance */
-} esp_vfs_select_sem_t;
+#define ESP_VFS_FLAG_STATIC (1 << 3)
 
 /**
  * @brief VFS definition structure
@@ -259,6 +252,8 @@ typedef struct
 #endif // CONFIG_VFS_SUPPORT_SELECT || defined __DOXYGEN__
 } esp_vfs_t;
 
+
+
 /**
  * Register a virtual filesystem for given path prefix.
  *
@@ -284,7 +279,6 @@ typedef struct
  */
 esp_err_t esp_vfs_register(const char* base_path, const esp_vfs_t* vfs, void* ctx);
 
-
 /**
  * Special case function for registering a VFS that uses a method other than
  * open() to open new file descriptors from the interval <min_fd; max_fd).
@@ -492,6 +486,23 @@ ssize_t esp_vfs_pwrite(int fd, const void *src, size_t size, off_t offset);
  */
 void esp_vfs_dump_fds(FILE *fp);
 
+/**
+ * @brief Dump all registered FSs to the provided FILE*
+ *
+ * Dump the FSs in the format:
+ @verbatim
+        <index>:<VFS Path Prefix> -> <VFS entry ptr>
+
+    where:
+        index           : internal index in the table of registered FSs (the same as returned when registering fd with id)
+        VFS Path Prefix : file prefix used in the esp_vfs_register call or "NULL"
+        VFS entry ptr   : pointer to the esp_vfs_fs_ops_t struct used internally when resolving the calls
+ @endverbatim
+ *
+ * @param fp File descriptor where data will be dumped
+ */
+void esp_vfs_dump_registered_paths(FILE *fp);
+
 #ifdef __cplusplus
 } // extern "C"
 #endif
diff --git a/components/vfs/include/esp_vfs_ops.h b/components/vfs/include/esp_vfs_ops.h
new file mode 100644
index 00000000000..bd5d635235c
--- /dev/null
+++ b/components/vfs/include/esp_vfs_ops.h
@@ -0,0 +1,308 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdarg.h>
+#include <unistd.h>
+#include <utime.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "esp_err.h"
+#include <sys/types.h>
+#include <sys/reent.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/termios.h>
+#include <sys/poll.h>
+#ifdef __clang__ // TODO LLVM-330
+#include <sys/dirent.h>
+#else
+#include <dirent.h>
+#endif
+#include <string.h>
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _SYS_TYPES_FD_SET
+#error "VFS should be used with FD_SETSIZE and FD_SET from sys/types.h"
+#endif
+
+/*
+ * @brief VFS identificator used for esp_vfs_register_with_id()
+ */
+typedef int esp_vfs_id_t;
+
+/**
+ * @brief VFS semaphore type for select()
+ *
+ */
+typedef struct
+{
+    bool is_sem_local;      /*!< type of "sem" is SemaphoreHandle_t when true, defined by socket driver otherwise */
+    void *sem;              /*!< semaphore instance */
+} esp_vfs_select_sem_t;
+
+#ifdef CONFIG_VFS_SUPPORT_DIR
+
+/**
+ * @brief Struct containing function pointers to directory related functionality.
+ *
+ */
+typedef struct {
+    union {
+        int (*stat_p)(void* ctx, const char * path, struct stat * st);                               /*!< stat with context pointer */
+        int (*stat)(const char * path, struct stat * st);                                            /*!< stat without context pointer */
+    };
+    union {
+        int (*link_p)(void* ctx, const char* n1, const char* n2);                                    /*!< link with context pointer */
+        int (*link)(const char* n1, const char* n2);                                                 /*!< link without context pointer */
+    };
+    union {
+        int (*unlink_p)(void* ctx, const char *path);                                                /*!< unlink with context pointer */
+        int (*unlink)(const char *path);                                                             /*!< unlink without context pointer */
+    };
+    union {
+        int (*rename_p)(void* ctx, const char *src, const char *dst);                               /*!< rename with context pointer */
+        int (*rename)(const char *src, const char *dst);                                            /*!< rename without context pointer */
+    };
+    union {
+        DIR* (*opendir_p)(void* ctx, const char* name);                                             /*!< opendir with context pointer */
+        DIR* (*opendir)(const char* name);                                                          /*!< opendir without context pointer */
+    };
+    union {
+        struct dirent* (*readdir_p)(void* ctx, DIR* pdir);                                          /*!< readdir with context pointer */
+        struct dirent* (*readdir)(DIR* pdir);                                                       /*!< readdir without context pointer */
+    };
+    union {
+        int (*readdir_r_p)(void* ctx, DIR* pdir, struct dirent* entry, struct dirent** out_dirent); /*!< readdir_r with context pointer */
+        int (*readdir_r)(DIR* pdir, struct dirent* entry, struct dirent** out_dirent);              /*!< readdir_r without context pointer */
+    };
+    union {
+        long (*telldir_p)(void* ctx, DIR* pdir);                                                    /*!< telldir with context pointer */
+        long (*telldir)(DIR* pdir);                                                                 /*!< telldir without context pointer */
+    };
+    union {
+        void (*seekdir_p)(void* ctx, DIR* pdir, long offset);                                       /*!< seekdir with context pointer */
+        void (*seekdir)(DIR* pdir, long offset);                                                    /*!< seekdir without context pointer */
+    };
+    union {
+        int (*closedir_p)(void* ctx, DIR* pdir);                                                    /*!< closedir with context pointer */
+        int (*closedir)(DIR* pdir);                                                                 /*!< closedir without context pointer */
+    };
+    union {
+        int (*mkdir_p)(void* ctx, const char* name, mode_t mode);                                   /*!< mkdir with context pointer */
+        int (*mkdir)(const char* name, mode_t mode);                                                /*!< mkdir without context pointer */
+    };
+    union {
+        int (*rmdir_p)(void* ctx, const char* name);                                                /*!< rmdir with context pointer */
+        int (*rmdir)(const char* name);                                                             /*!< rmdir without context pointer */
+    };
+    union {
+        int (*access_p)(void* ctx, const char *path, int amode);                                    /*!< access with context pointer */
+        int (*access)(const char *path, int amode);                                                 /*!< access without context pointer */
+    };
+    union {
+        int (*truncate_p)(void* ctx, const char *path, off_t length);                               /*!< truncate with context pointer */
+        int (*truncate)(const char *path, off_t length);                                            /*!< truncate without context pointer */
+    };
+    union {
+        int (*ftruncate_p)(void* ctx, int fd, off_t length);                                        /*!< ftruncate with context pointer */
+        int (*ftruncate)(int fd, off_t length);                                                     /*!< ftruncate without context pointer */
+    };
+    union {
+        int (*utime_p)(void* ctx, const char *path, const struct utimbuf *times);                   /*!< utime with context pointer */
+        int (*utime)(const char *path, const struct utimbuf *times);                                /*!< utime without context pointer */
+    };
+} esp_vfs_dir_ops_t;
+
+#endif // CONFIG_VFS_SUPPORT_DIR
+
+#ifdef CONFIG_VFS_SUPPORT_TERMIOS
+
+/**
+ * @brief Struct containing function pointers to termios related functionality.
+ *
+ */
+typedef struct {
+    union {
+        int (*tcsetattr_p)(void *ctx, int fd, int optional_actions, const struct termios *p);       /*!< tcsetattr with context pointer */
+        int (*tcsetattr)(int fd, int optional_actions, const struct termios *p);                    /*!< tcsetattr without context pointer */
+    };
+    union {
+        int (*tcgetattr_p)(void *ctx, int fd, struct termios *p);                                   /*!< tcgetattr with context pointer */
+        int (*tcgetattr)(int fd, struct termios *p);                                                /*!< tcgetattr without context pointer */
+    };
+    union {
+        int (*tcdrain_p)(void *ctx, int fd);                                                        /*!< tcdrain with context pointer */
+        int (*tcdrain)(int fd);                                                                     /*!< tcdrain without context pointer */
+    };
+    union {
+        int (*tcflush_p)(void *ctx, int fd, int select);                                            /*!< tcflush with context pointer */
+        int (*tcflush)(int fd, int select);                                                         /*!< tcflush without context pointer */
+    };
+    union {
+        int (*tcflow_p)(void *ctx, int fd, int action);                                             /*!< tcflow with context pointer */
+        int (*tcflow)(int fd, int action);                                                          /*!< tcflow without context pointer */
+    };
+    union {
+        pid_t (*tcgetsid_p)(void *ctx, int fd);                                                     /*!< tcgetsid with context pointer */
+        pid_t (*tcgetsid)(int fd);                                                                  /*!< tcgetsid without context pointer */
+    };
+    union {
+        int (*tcsendbreak_p)(void *ctx, int fd, int duration);                                      /*!< tcsendbreak with context pointer */
+        int (*tcsendbreak)(int fd, int duration);                                                   /*!< tcsendbreak without context pointer */
+    };
+} esp_vfs_termios_ops_t;
+
+#endif // CONFIG_VFS_SUPPORT_TERMIOS
+
+#ifdef CONFIG_VFS_SUPPORT_SELECT
+
+/**
+ * @brief Struct containing function pointers to select related functionality.
+ *
+ */
+typedef struct {
+    /** start_select is called for setting up synchronous I/O multiplexing of the desired file descriptors in the given VFS */
+    esp_err_t (*start_select)(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, esp_vfs_select_sem_t sem, void **end_select_args);
+
+    /** socket select function for socket FDs with the functionality of POSIX select(); this should be set only for the socket VFS */
+    int (*socket_select)(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds, struct timeval *timeout);
+
+    /** called by VFS to interrupt the socket_select call when select is activated from a non-socket VFS driver; set only for the socket driver */
+    void (*stop_socket_select)(void *sem);
+
+    /** stop_socket_select which can be called from ISR; set only for the socket driver */
+    void (*stop_socket_select_isr)(void *sem, BaseType_t *woken);
+
+    /** end_select is called to stop the I/O multiplexing and deinitialize the environment created by start_select for the given VFS */
+    void* (*get_socket_select_semaphore)(void);
+
+    /** get_socket_select_semaphore returns semaphore allocated in the socket driver; set only for the socket driver */
+    esp_err_t (*end_select)(void *end_select_args);
+} esp_vfs_select_ops_t;
+
+#endif // CONFIG_VFS_SUPPORT_SELECT
+
+/**
+ * @brief Main struct of the minified vfs API, containing basic function pointers as well as pointers to the other subcomponents.
+ *
+ */
+typedef struct {
+    union {
+        ssize_t (*write_p)(void* p, int fd, const void * data, size_t size);                         /*!< Write with context pointer */
+        ssize_t (*write)(int fd, const void * data, size_t size);                                    /*!< Write without context pointer */
+    };
+    union {
+        off_t (*lseek_p)(void* p, int fd, off_t size, int mode);                                     /*!< Seek with context pointer */
+        off_t (*lseek)(int fd, off_t size, int mode);                                                /*!< Seek without context pointer */
+    };
+    union {
+        ssize_t (*read_p)(void* ctx, int fd, void * dst, size_t size);                               /*!< Read with context pointer */
+        ssize_t (*read)(int fd, void * dst, size_t size);                                            /*!< Read without context pointer */
+    };
+    union {
+        ssize_t (*pread_p)(void *ctx, int fd, void * dst, size_t size, off_t offset);                /*!< pread with context pointer */
+        ssize_t (*pread)(int fd, void * dst, size_t size, off_t offset);                             /*!< pread without context pointer */
+    };
+    union {
+        ssize_t (*pwrite_p)(void *ctx, int fd, const void *src, size_t size, off_t offset);          /*!< pwrite with context pointer */
+        ssize_t (*pwrite)(int fd, const void *src, size_t size, off_t offset);                       /*!< pwrite without context pointer */
+    };
+    union {
+        int (*open_p)(void* ctx, const char * path, int flags, int mode);                            /*!< open with context pointer */
+        int (*open)(const char * path, int flags, int mode);                                         /*!< open without context pointer */
+    };
+    union {
+        int (*close_p)(void* ctx, int fd);                                                           /*!< close with context pointer */
+        int (*close)(int fd);                                                                        /*!< close without context pointer */
+    };
+    union {
+        int (*fstat_p)(void* ctx, int fd, struct stat * st);                                         /*!< fstat with context pointer */
+        int (*fstat)(int fd, struct stat * st);                                                      /*!< fstat without context pointer */
+    };
+    union {
+        int (*fcntl_p)(void* ctx, int fd, int cmd, int arg);                                        /*!< fcntl with context pointer */
+        int (*fcntl)(int fd, int cmd, int arg);                                                     /*!< fcntl without context pointer */
+    };
+    union {
+        int (*ioctl_p)(void* ctx, int fd, int cmd, va_list args);                                   /*!< ioctl with context pointer */
+        int (*ioctl)(int fd, int cmd, va_list args);                                                /*!< ioctl without context pointer */
+    };
+    union {
+        int (*fsync_p)(void* ctx, int fd);                                                          /*!< fsync with context pointer */
+        int (*fsync)(int fd);                                                                       /*!< fsync without context pointer */
+    };
+
+#ifdef CONFIG_VFS_SUPPORT_DIR
+    esp_vfs_dir_ops_t *dir;                                                                             /*!< pointer to the dir subcomponent */
+#endif
+
+#ifdef CONFIG_VFS_SUPPORT_TERMIOS
+    esp_vfs_termios_ops_t *termios;                                                                     /*!< pointer to the termios subcomponent */
+#endif
+
+#if CONFIG_VFS_SUPPORT_SELECT || defined __DOXYGEN__
+    esp_vfs_select_ops_t *select;                                                                       /*!< pointer to the select subcomponent */
+#endif
+
+} esp_vfs_fs_ops_t;
+
+/**
+ * Register a virtual filesystem for given path prefix.
+ *
+ * @param base_path  file path prefix associated with the filesystem.
+ *                   Must be a zero-terminated C string, may be empty.
+ *                   If not empty, must be up to ESP_VFS_PATH_MAX
+ *                   characters long, and at least 2 characters long.
+ *                   Name must start with a "/" and must not end with "/".
+ *                   For example, "/data" or "/dev/spi" are valid.
+ *                   These VFSes would then be called to handle file paths such as
+ *                   "/data/myfile.txt" or "/dev/spi/0".
+ *                   In the special case of an empty base_path, a "fallback"
+ *                   VFS is registered. Such VFS will handle paths which are not
+ *                   matched by any other registered VFS.
+ * @param vfs  Pointer to esp_vfs_fs_ops_t, a structure which maps syscalls to
+ *             the filesystem driver functions. VFS component does not assume ownership of this struct, but see flags for more info
+ *
+ * @param flags Set of binary flags controlling how the registered FS should be treated
+ *             - ESP_VFS_FLAG_STATIC - if this flag is specified VFS assumes the provided esp_vfs_fs_ops_t and all its subcomponents are statically allocated,
+ *                                     if it is not enabled a deep copy of the provided struct will be created, which will be managed by the VFS component
+ *             - ESP_VFS_FLAG_CONTEXT_PTR - If set, the VFS will use the context-aware versions of the filesystem operation functions (suffixed with `_p`) in `esp_vfs_fs_ops_t` and its subcomponents.
+ *                                          The `ctx` parameter will be passed as the context argument when these functions are invoked.
+ *
+ * @param ctx  Context pointer for fs operation functions, see the ESP_VFS_FLAG_CONTEXT_PTR.
+ *             Should be `NULL` if not used.
+ *
+ * @return  ESP_OK if successful, ESP_ERR_NO_MEM if too many FSes are
+ *          registered.
+ */
+esp_err_t esp_vfs_register_fs(const char* base_path, const esp_vfs_fs_ops_t* vfs, int flags, void* ctx);
+
+/**
+ * Analog of esp_vfs_register_with_id which accepts esp_vfs_fs_ops_t instead.
+ *
+ */
+esp_err_t esp_vfs_register_fs_with_id(const esp_vfs_fs_ops_t* vfs, int flags, void* ctx, esp_vfs_id_t* id);
+
+/**
+ * Alias for esp_vfs_unregister for naming consistency
+ */
+esp_err_t esp_vfs_unregister_fs(const char* base_path);
+
+/**
+ * Alias for esp_vfs_unregister_with_id for naming consistency
+ */
+esp_err_t esp_vfs_unregister_fs_with_id(esp_vfs_id_t id);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/vfs/private_include/esp_vfs_private.h b/components/vfs/private_include/esp_vfs_private.h
index fda3e9712ba..5dcca69b55f 100644
--- a/components/vfs/private_include/esp_vfs_private.h
+++ b/components/vfs/private_include/esp_vfs_private.h
@@ -19,7 +19,8 @@ extern "C" {
 #endif
 
 typedef struct vfs_entry_ {
-    esp_vfs_t vfs;          // contains pointers to VFS functions
+    int flags;      /*!< ESP_VFS_FLAG_CONTEXT_PTR and/or ESP_VFS_FLAG_READONLY_FS or ESP_VFS_FLAG_DEFAULT */
+    const esp_vfs_fs_ops_t *vfs;          // contains pointers to VFS functions
     char path_prefix[ESP_VFS_PATH_MAX]; // path prefix mapped to this VFS
     size_t path_prefix_len; // micro-optimization to avoid doing extra strlen
     void* ctx;              // optional pointer which can be passed to VFS
diff --git a/components/vfs/test_apps/.build-test-rules.yml b/components/vfs/test_apps/.build-test-rules.yml
index 5a050d00c46..6f8e89a2a64 100644
--- a/components/vfs/test_apps/.build-test-rules.yml
+++ b/components/vfs/test_apps/.build-test-rules.yml
@@ -1,8 +1,4 @@
 components/vfs/test_apps:
-  disable:
-    - if: IDF_TARGET in ["esp32c5", "esp32c61"]
-      temporary: true
-      reason: not support yet # TODO: [ESP32C5] IDF-8704, [esp32c61] IDF-9305
   disable_test:
     - if: IDF_TARGET not in ["esp32", "esp32c2", "esp32c3", "esp32c6", "esp32h2", "esp32s3"]
       temporary: true
diff --git a/components/vfs/test_apps/README.md b/components/vfs/test_apps/README.md
index bf47d80ec64..7b96141437e 100644
--- a/components/vfs/test_apps/README.md
+++ b/components/vfs/test_apps/README.md
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
diff --git a/components/vfs/test_apps/main/CMakeLists.txt b/components/vfs/test_apps/main/CMakeLists.txt
index 7ab4968a9e0..e7cfc100f53 100644
--- a/components/vfs/test_apps/main/CMakeLists.txt
+++ b/components/vfs/test_apps/main/CMakeLists.txt
@@ -3,6 +3,7 @@ set(src "test_app_main.c" "test_vfs_access.c"
         "test_vfs_fd.c" "test_vfs_lwip.c"
         "test_vfs_open.c" "test_vfs_paths.c"
         "test_vfs_select.c" "test_vfs_nullfs.c"
+        "test_vfs_minified.c"
         )
 
 idf_component_register(SRCS ${src}
diff --git a/components/vfs/test_apps/main/test_vfs_lwip.c b/components/vfs/test_apps/main/test_vfs_lwip.c
index 3bed7d5ec8b..e9cf3870ab5 100644
--- a/components/vfs/test_apps/main/test_vfs_lwip.c
+++ b/components/vfs/test_apps/main/test_vfs_lwip.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,8 +15,9 @@ TEST_CASE("fstat() sets st_mode to socket type", "[vfs][lwip]")
 {
     test_case_uses_tcpip();
     int socket_fd = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP);
+    TEST_ASSERT(socket_fd >= 0);
     struct stat stat = { 0 };
-    fstat(socket_fd, &stat);
+    TEST_ASSERT_EQUAL(0, fstat(socket_fd, &stat));
 
     TEST_ASSERT_TRUE(S_ISSOCK(stat.st_mode));
     TEST_ASSERT_FALSE(S_ISBLK(stat.st_mode));
@@ -25,5 +26,5 @@ TEST_CASE("fstat() sets st_mode to socket type", "[vfs][lwip]")
     TEST_ASSERT_FALSE(S_ISREG(stat.st_mode));
     TEST_ASSERT_FALSE(S_ISLNK(stat.st_mode));
 
-    close(socket_fd);
+    TEST_ASSERT_EQUAL(0, close(socket_fd));
 }
diff --git a/components/vfs/test_apps/main/test_vfs_minified.c b/components/vfs/test_apps/main/test_vfs_minified.c
new file mode 100644
index 00000000000..bef2e507fba
--- /dev/null
+++ b/components/vfs/test_apps/main/test_vfs_minified.c
@@ -0,0 +1,166 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include <stdint.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "esp_err.h"
+#include "esp_vfs_ops.h"
+#include "unity.h"
+#include "esp_vfs.h"
+
+#include "unity_test_runner.h"
+
+#define BUF_CAP 1024
+
+typedef struct {
+    uint8_t data[BUF_CAP];
+    size_t head;
+    size_t tail;
+} cb_t;
+
+void cb_reset(cb_t* buf) {
+    buf->head = 0;
+    buf->tail = 0;
+}
+
+size_t cb_count(const cb_t *buf) {
+    return buf->head - buf->tail;
+}
+
+int cb_write(cb_t *buf, const uint8_t *data, size_t size) {
+    size_t count = cb_count(buf);
+    size_t space = BUF_CAP - count;
+
+    size_t to_write = (size > space) ? space : size;
+
+    size_t idx = buf->head % BUF_CAP;
+    size_t first_chunk = BUF_CAP - idx;
+    if (first_chunk > to_write)
+        first_chunk = to_write;
+
+    memcpy(&buf->data[idx], data, first_chunk);
+    buf->head += first_chunk;
+
+    if (first_chunk < to_write) {
+        size_t second_chunk = to_write - first_chunk;
+        memcpy(&buf->data[0], data + first_chunk, second_chunk);
+        buf->head += second_chunk;
+    }
+
+    return (int)to_write;
+}
+
+int cb_read(cb_t *buf, uint8_t *dest, size_t count) {
+    size_t available = cb_count(buf);
+    size_t to_read = (count > available) ? available : count;
+
+    size_t idx = buf->tail % BUF_CAP;
+    size_t first_chunk = BUF_CAP - idx;
+    if (first_chunk > to_read)
+        first_chunk = to_read;
+
+    memcpy(dest, &buf->data[idx], first_chunk);
+    buf->tail += first_chunk;
+
+    if (first_chunk < to_read) {
+        size_t second_chunk = to_read - first_chunk;
+        memcpy(dest + first_chunk, &buf->data[0], second_chunk);
+        buf->tail += second_chunk;
+    }
+
+    return (int)to_read;
+}
+
+
+int buffer_open(void *ctx, const char *path, int flags, int mode) {
+    return 0;
+}
+
+int buffer_write(void *ctx, int fd, const void *data, size_t size) {
+    cb_t* buf = (cb_t*) ctx;
+    return cb_write(buf, data, size);
+}
+
+int buffer_read(void *ctx, int fd, void *data, size_t size) {
+    cb_t* buf = (cb_t*) ctx;
+    return cb_read(buf, data, size);
+}
+
+int buffer_close(void *ctx, int fd) {
+    cb_reset((cb_t*) ctx);
+    return 0;
+}
+
+static esp_vfs_fs_ops_t s_buffer_fs = {
+    .write_p = buffer_write,
+    .read_p = buffer_read,
+    .open_p = buffer_open,
+    .close_p = buffer_close,
+};
+
+TEST_CASE("VFS won't create a copy when ESP_FLAG_VFS_STATIC is specified", "[esp_vfs_fs_ops_t]")
+{
+    TEST_MESSAGE("test");
+    static esp_vfs_dir_ops_t dir = {};
+    static esp_vfs_fs_ops_t vfs = {
+        .dir = &dir,
+    };
+
+    cb_t *buffer = calloc(1, sizeof(cb_t));
+
+    esp_err_t err = ESP_OK;
+    err = esp_vfs_register_fs("/buffer", &s_buffer_fs, ESP_VFS_FLAG_CONTEXT_PTR | ESP_VFS_FLAG_STATIC, buffer);
+    TEST_ASSERT_EQUAL(ESP_OK, err);
+
+    err = esp_vfs_register_fs("/static", &vfs, ESP_VFS_FLAG_STATIC, NULL);
+    TEST_ASSERT_EQUAL(ESP_OK, err);
+
+    err = esp_vfs_register_fs("/dynamic", &vfs, ESP_VFS_FLAG_DEFAULT, NULL);
+    TEST_ASSERT_EQUAL(ESP_OK, err);
+
+    FILE *buf_f = fopen("/buffer/a", "r+");
+
+    esp_vfs_dump_registered_paths(buf_f);
+
+    char read_buffer[512];
+    size_t bytes_read = fread(read_buffer, 1, sizeof(read_buffer) - 1, buf_f);
+    read_buffer[bytes_read] = '\0'; // Null-terminate the string
+
+    // Parse the buffer to extract VFS pointers
+    char *line = strtok(read_buffer, "\n");
+    void *static_vfs_ptr = NULL;
+    void *dynamic_vfs_ptr = NULL;
+
+    while (line != NULL) {
+        int index;
+        char path_prefix[64];
+        char ptr_str[32];
+        TEST_MESSAGE(line);
+        if (sscanf(line, "%d:%63s -> %31s", &index, path_prefix, ptr_str) == 3) {
+            void *vfs_ptr = (void *)strtoul(ptr_str, NULL, 0);
+            if (strcmp(path_prefix, "/static") == 0) {
+                static_vfs_ptr = vfs_ptr;
+            } else if (strcmp(path_prefix, "/dynamic") == 0) {
+                dynamic_vfs_ptr = vfs_ptr;
+            }
+        }
+        line = strtok(NULL, "\n");
+    }
+
+    // Check that the pointer for "/static" is the same as 'vfs' and "/dynamic" is different
+    TEST_ASSERT_EQUAL_PTR(&vfs, static_vfs_ptr);
+    TEST_ASSERT_NOT_EQUAL(&vfs, dynamic_vfs_ptr);
+
+    free(buffer);
+    fclose(buf_f);
+
+    esp_vfs_unregister("/buffer");
+    esp_vfs_unregister("/static");
+    esp_vfs_unregister("/dynamic");
+}
diff --git a/components/vfs/vfs.c b/components/vfs/vfs.c
index 906e8684d9d..1f02e0f5509 100644
--- a/components/vfs/vfs.c
+++ b/components/vfs/vfs.c
@@ -19,6 +19,7 @@
 #include "freertos/semphr.h"
 #include "esp_vfs.h"
 #include "esp_vfs_private.h"
+#include "include/esp_vfs.h"
 #include "sdkconfig.h"
 
 // Warn about using deprecated option
@@ -75,8 +76,283 @@ static size_t s_vfs_count = 0;
 static fd_table_t s_fd_table[MAX_FDS] = { [0 ... MAX_FDS-1] = FD_TABLE_ENTRY_UNUSED };
 static _lock_t s_fd_table_lock;
 
-esp_err_t esp_vfs_register_common(const char* base_path, size_t len, const esp_vfs_t* vfs, void* ctx, int *vfs_index)
+static ssize_t esp_get_free_index(void) {
+    for (ssize_t i = 0; i < VFS_MAX_COUNT; i++) {
+        if (s_vfs[i] == NULL) {
+            return i;
+        }
+    }
+    return -1;
+}
+
+static void esp_vfs_free_fs_ops(esp_vfs_fs_ops_t *vfs) {
+#ifdef CONFIG_VFS_SUPPORT_TERMIOS
+    free(vfs->termios);
+#endif
+
+#ifdef CONFIG_VFS_SUPPORT_DIR
+    free(vfs->dir);
+#endif
+
+#ifdef CONFIG_VFS_SUPPORT_SELECT
+    free(vfs->select);
+#endif
+
+    free(vfs);
+}
+
+static void esp_vfs_free_entry(vfs_entry_t *entry) {
+    if (entry == NULL) { // Necessary because of the following flags check
+        return;
+    }
+
+    if (!(entry->flags & ESP_VFS_FLAG_STATIC)) {
+        esp_vfs_free_fs_ops((esp_vfs_fs_ops_t*)entry->vfs); // const cast, but we know it's not static from the flag
+    }
+
+    free(entry);
+}
+
+static void esp_minify_vfs(const esp_vfs_t * const vfs, esp_vfs_fs_ops_t *min) {
+    assert(vfs != NULL);
+    assert(min != NULL);
+    *min = (esp_vfs_fs_ops_t) {
+        .write = vfs->write,
+        .lseek = vfs->lseek,
+        .read = vfs->read,
+        .pread = vfs->pread,
+        .pwrite = vfs->pwrite,
+        .open = vfs->open,
+        .close = vfs->close,
+        .fstat = vfs->fstat,
+        .fcntl = vfs->fcntl,
+        .ioctl = vfs->ioctl,
+        .fsync = vfs->fsync,
+#ifdef CONFIG_VFS_SUPPORT_DIR
+        .dir = min->dir,
+#endif
+#ifdef CONFIG_VFS_SUPPORT_TERMIOS
+        .termios = min->termios,
+#endif
+#ifdef CONFIG_VFS_SUPPORT_SELECT
+        .select = min->select,
+#endif
+    };
+
+#ifdef CONFIG_VFS_SUPPORT_DIR
+    // If the dir functions are not implemented, we don't need to convert them
+    if (min->dir != NULL) {
+        *(min->dir) = (esp_vfs_dir_ops_t) {
+            .stat = vfs->stat,
+            .link = vfs->link,
+            .unlink = vfs->unlink,
+            .rename = vfs->rename,
+            .opendir = vfs->opendir,
+            .readdir = vfs->readdir,
+            .readdir_r = vfs->readdir_r,
+            .telldir = vfs->telldir,
+            .seekdir = vfs->seekdir,
+            .closedir = vfs->closedir,
+            .mkdir = vfs->mkdir,
+            .rmdir = vfs->rmdir,
+            .access = vfs->access,
+            .truncate = vfs->truncate,
+            .ftruncate = vfs->ftruncate,
+            .utime = vfs->utime,
+        };
+    }
+#endif // CONFIG_VFS_SUPPORT_DIR
+
+#ifdef CONFIG_VFS_SUPPORT_TERMIOS
+    // If the termios functions are not implemented, we don't need to convert them
+    if (min->termios != NULL) {
+        *(min->termios) = (esp_vfs_termios_ops_t) {
+            .tcsetattr = vfs->tcsetattr,
+            .tcgetattr = vfs->tcgetattr,
+            .tcdrain = vfs->tcdrain,
+            .tcflush = vfs->tcflush,
+            .tcflow = vfs->tcflow,
+            .tcgetsid = vfs->tcgetsid,
+            .tcsendbreak = vfs->tcsendbreak,
+        };
+    }
+#endif // CONFIG_VFS_SUPPORT_TERMIOS
+
+#ifdef CONFIG_VFS_SUPPORT_SELECT
+    // If the select functions are not implemented, we don't need to convert them
+    if (min->select != NULL) {
+        *(min->select) = (esp_vfs_select_ops_t) {
+            .start_select = vfs->start_select,
+            .socket_select = vfs->socket_select,
+            .stop_socket_select = vfs->stop_socket_select,
+            .stop_socket_select_isr = vfs->stop_socket_select_isr,
+            .get_socket_select_semaphore = vfs->get_socket_select_semaphore,
+            .end_select = vfs->end_select,
+        };
+    }
+#endif // CONFIG_VFS_SUPPORT_SELECT
+
+}
+
+static esp_vfs_fs_ops_t* esp_vfs_duplicate_fs_ops(const esp_vfs_fs_ops_t *vfs) {
+    esp_vfs_fs_ops_t *min = (esp_vfs_fs_ops_t*) heap_caps_malloc(sizeof(esp_vfs_fs_ops_t), VFS_MALLOC_FLAGS);
+    if (min == NULL) {
+        return NULL;
+    }
+
+    memcpy(min, vfs, sizeof(esp_vfs_fs_ops_t));
+
+    // remove references to the original components
+#ifdef CONFIG_VFS_SUPPORT_DIR
+    min->dir = NULL;
+#endif
+#ifdef CONFIG_VFS_SUPPORT_TERMIOS
+    min->termios = NULL;
+#endif
+#ifdef CONFIG_VFS_SUPPORT_SELECT
+    min->select = NULL;
+#endif
+
+#ifdef CONFIG_VFS_SUPPORT_DIR
+    if (vfs->dir != NULL) {
+        min->dir = (esp_vfs_dir_ops_t*) heap_caps_malloc(sizeof(esp_vfs_dir_ops_t), VFS_MALLOC_FLAGS);
+        if (min->dir == NULL) {
+            goto fail;
+        }
+        memcpy(min->dir, vfs->dir, sizeof(esp_vfs_dir_ops_t));
+    }
+#endif
+
+#ifdef CONFIG_VFS_SUPPORT_TERMIOS
+    if (vfs->termios != NULL) {
+        min->termios = (esp_vfs_termios_ops_t*) heap_caps_malloc(sizeof(esp_vfs_termios_ops_t), VFS_MALLOC_FLAGS);
+        if (min->termios == NULL) {
+            goto fail;
+        }
+        memcpy(min->termios, vfs->termios, sizeof(esp_vfs_termios_ops_t));
+    }
+#endif
+
+#ifdef CONFIG_VFS_SUPPORT_SELECT
+    if (vfs->select != NULL) {
+        min->select = (esp_vfs_select_ops_t*) heap_caps_malloc(sizeof(esp_vfs_select_ops_t), VFS_MALLOC_FLAGS);
+        if (min->select == NULL) {
+            goto fail;
+        }
+        memcpy(min->select, vfs->select, sizeof(esp_vfs_select_ops_t));
+    }
+#endif
+
+    return min;
+
+#if defined(CONFIG_VFS_SUPPORT_SELECT) || defined(CONFIG_VFS_SUPPORT_TERMIOS) || defined(CONFIG_VFS_SUPPORT_DIR)
+fail:
+#endif
+    esp_vfs_free_fs_ops(min);
+    return NULL;
+}
+
+static esp_err_t esp_vfs_make_fs_ops(const esp_vfs_t *vfs, esp_vfs_fs_ops_t **min) {
+    if (vfs == NULL) {
+        ESP_LOGE(TAG, "Cannot minify NULL VFS");
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    if (min == NULL) {
+        ESP_LOGE(TAG, "Cannot minify VFS to NULL");
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    esp_vfs_fs_ops_t *main = (esp_vfs_fs_ops_t*) heap_caps_malloc(sizeof(esp_vfs_fs_ops_t), VFS_MALLOC_FLAGS);
+    if (main == NULL) {
+        return ESP_ERR_NO_MEM;
+    }
+
+    // Initialize all fields to NULL
+    memset(main, 0, sizeof(esp_vfs_fs_ops_t));
+
+#ifdef CONFIG_VFS_SUPPORT_DIR
+    bool skip_dir =
+        vfs->stat == NULL &&
+        vfs->link == NULL &&
+        vfs->unlink == NULL &&
+        vfs->rename == NULL &&
+        vfs->opendir == NULL &&
+        vfs->readdir == NULL &&
+        vfs->readdir_r == NULL &&
+        vfs->telldir == NULL &&
+        vfs->seekdir == NULL &&
+        vfs->closedir == NULL &&
+        vfs->mkdir == NULL &&
+        vfs->rmdir == NULL &&
+        vfs->access == NULL &&
+        vfs->truncate == NULL &&
+        vfs->ftruncate == NULL &&
+        vfs->utime == NULL;
+
+    if (!skip_dir) {
+        main->dir = (esp_vfs_dir_ops_t*) heap_caps_malloc(sizeof(esp_vfs_dir_ops_t), VFS_MALLOC_FLAGS);
+        if (main->dir == NULL) {
+            goto fail;
+        }
+    }
+#endif
+
+#ifdef CONFIG_VFS_SUPPORT_TERMIOS
+    bool skip_termios =
+        vfs->tcsetattr == NULL &&
+        vfs->tcgetattr == NULL &&
+        vfs->tcdrain == NULL &&
+        vfs->tcflush == NULL &&
+        vfs->tcflow == NULL &&
+        vfs->tcgetsid == NULL &&
+        vfs->tcsendbreak == NULL;
+
+    if (!skip_termios) {
+        main->termios = (esp_vfs_termios_ops_t*) heap_caps_malloc(sizeof(esp_vfs_termios_ops_t), VFS_MALLOC_FLAGS);
+        if (main->termios == NULL) {
+            goto fail;
+        }
+    }
+#endif
+
+#ifdef CONFIG_VFS_SUPPORT_SELECT
+    bool skip_select =
+        vfs->start_select == NULL &&
+        vfs->socket_select == NULL &&
+        vfs->stop_socket_select == NULL &&
+        vfs->stop_socket_select_isr == NULL &&
+        vfs->get_socket_select_semaphore == NULL &&
+        vfs->end_select == NULL;
+
+    if (!skip_select) {
+        main->select = (esp_vfs_select_ops_t*) heap_caps_malloc(sizeof(esp_vfs_select_ops_t), VFS_MALLOC_FLAGS);
+        if (main->select == NULL) {
+            goto fail;
+        }
+    }
+#endif
+
+    esp_minify_vfs(vfs, main);
+
+    *min = main;
+    return ESP_OK;
+
+#if defined(CONFIG_VFS_SUPPORT_SELECT) || defined(CONFIG_VFS_SUPPORT_TERMIOS) || defined(CONFIG_VFS_SUPPORT_DIR)
+fail:
+
+    esp_vfs_free_fs_ops(main);
+    return ESP_ERR_NO_MEM;
+#endif
+}
+
+static esp_err_t esp_vfs_register_fs_common(const char* base_path, size_t len, const esp_vfs_fs_ops_t* vfs, int flags, void* ctx, int *vfs_index)
 {
+    if (vfs == NULL) {
+        ESP_LOGE(TAG, "VFS is NULL");
+        return ESP_ERR_INVALID_ARG;
+    }
+
     if (len != LEN_PATH_PREFIX_IGNORED) {
         /* empty prefix is allowed, "/" is not allowed */
         if ((len == 1) || (len > ESP_VFS_PATH_MAX)) {
@@ -87,33 +363,36 @@ esp_err_t esp_vfs_register_common(const char* base_path, size_t len, const esp_v
             return ESP_ERR_INVALID_ARG;
         }
     }
-    vfs_entry_t *entry = (vfs_entry_t*) heap_caps_malloc(sizeof(vfs_entry_t), VFS_MALLOC_FLAGS);
-    if (entry == NULL) {
+
+    ssize_t index = esp_get_free_index();
+    if (index < 0) {
         return ESP_ERR_NO_MEM;
     }
-    size_t index;
-    for (index = 0; index < s_vfs_count; ++index) {
-        if (s_vfs[index] == NULL) {
-            break;
-        }
+
+    if (s_vfs[index] != NULL) {
+        return ESP_ERR_INVALID_STATE;
     }
+
     if (index == s_vfs_count) {
-        if (s_vfs_count >= VFS_MAX_COUNT) {
-            free(entry);
-            return ESP_ERR_NO_MEM;
-        }
-        ++s_vfs_count;
+        s_vfs_count++;
     }
+
+    vfs_entry_t *entry = (vfs_entry_t*) heap_caps_malloc(sizeof(vfs_entry_t), VFS_MALLOC_FLAGS);
+    if (entry == NULL) {
+        return ESP_ERR_NO_MEM;
+    }
+
     s_vfs[index] = entry;
     if (len != LEN_PATH_PREFIX_IGNORED) {
         strcpy(entry->path_prefix, base_path); // we have already verified argument length
     } else {
         bzero(entry->path_prefix, sizeof(entry->path_prefix));
     }
-    memcpy(&entry->vfs, vfs, sizeof(esp_vfs_t));
     entry->path_prefix_len = len;
+    entry->vfs = vfs;
     entry->ctx = ctx;
     entry->offset = index;
+    entry->flags = flags;
 
     if (vfs_index) {
         *vfs_index = index;
@@ -122,6 +401,58 @@ esp_err_t esp_vfs_register_common(const char* base_path, size_t len, const esp_v
     return ESP_OK;
 }
 
+esp_err_t esp_vfs_register_fs(const char* base_path, const esp_vfs_fs_ops_t* vfs, int flags, void* ctx)
+{
+    if (vfs == NULL) {
+        ESP_LOGE(TAG, "VFS is NULL");
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    if ((flags & ESP_VFS_FLAG_STATIC)) {
+        return esp_vfs_register_fs_common(base_path, strlen(base_path), vfs, flags, ctx, NULL);
+    }
+
+    esp_vfs_fs_ops_t *_vfs = esp_vfs_duplicate_fs_ops(vfs);
+    if (_vfs == NULL) {
+        return ESP_ERR_NO_MEM;
+    }
+
+    esp_err_t ret = esp_vfs_register_fs_common(base_path, strlen(base_path), _vfs, flags, ctx, NULL);
+    if (ret != ESP_OK) {
+        esp_vfs_free_fs_ops(_vfs);
+        return ret;
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t esp_vfs_register_common(const char* base_path, size_t len, const esp_vfs_t* vfs, void* ctx, int *vfs_index)
+{
+    if (vfs == NULL) {
+        ESP_LOGE(TAG, "VFS is NULL");
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    if (vfs->flags & ESP_VFS_FLAG_STATIC) {
+        ESP_LOGE(TAG, "ESP_VFS_FLAG_STATIC is not supported for esp_vfs_t, use esp_vfs_register_fs instead");
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    esp_vfs_fs_ops_t *_vfs = NULL;
+    esp_err_t ret = esp_vfs_make_fs_ops(vfs, &_vfs);
+    if (ret != ESP_OK) {
+        return ret;
+    }
+
+    ret = esp_vfs_register_fs_common(base_path, len, _vfs, vfs->flags, ctx, vfs_index);
+    if (ret != ESP_OK) {
+        esp_vfs_free_fs_ops(_vfs);
+        return ret;
+    }
+
+    return ESP_OK;
+}
+
 esp_err_t esp_vfs_register(const char* base_path, const esp_vfs_t* vfs, void* ctx)
 {
     return esp_vfs_register_common(base_path, strlen(base_path), vfs, ctx, NULL);
@@ -134,7 +465,7 @@ esp_err_t esp_vfs_register_fd_range(const esp_vfs_t *vfs, void *ctx, int min_fd,
         return ESP_ERR_INVALID_ARG;
     }
 
-    int index = -1;
+    int index = 0;
     esp_err_t ret = esp_vfs_register_common("", LEN_PATH_PREFIX_IGNORED, vfs, ctx, &index);
 
     if (ret == ESP_OK) {
@@ -164,6 +495,16 @@ esp_err_t esp_vfs_register_fd_range(const esp_vfs_t *vfs, void *ctx, int min_fd,
     return ret;
 }
 
+esp_err_t esp_vfs_register_fs_with_id(const esp_vfs_fs_ops_t *vfs, int flags, void *ctx, esp_vfs_id_t *vfs_id)
+{
+    if (vfs_id == NULL) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    *vfs_id = -1;
+    return esp_vfs_register_fs_common("", LEN_PATH_PREFIX_IGNORED, vfs, flags, ctx, vfs_id);
+}
+
 esp_err_t esp_vfs_register_with_id(const esp_vfs_t *vfs, void *ctx, esp_vfs_id_t *vfs_id)
 {
     if (vfs_id == NULL) {
@@ -180,7 +521,7 @@ esp_err_t esp_vfs_unregister_with_id(esp_vfs_id_t vfs_id)
         return ESP_ERR_INVALID_ARG;
     }
     vfs_entry_t* vfs = s_vfs[vfs_id];
-    free(vfs);
+    esp_vfs_free_entry(vfs);
     s_vfs[vfs_id] = NULL;
 
     _lock_acquire(&s_fd_table_lock);
@@ -193,8 +534,11 @@ esp_err_t esp_vfs_unregister_with_id(esp_vfs_id_t vfs_id)
     _lock_release(&s_fd_table_lock);
 
     return ESP_OK;
+
 }
 
+esp_err_t esp_vfs_unregister_fs_with_id(esp_vfs_id_t vfs_id) __attribute__((alias("esp_vfs_unregister_with_id")));
+
 esp_err_t esp_vfs_unregister(const char* base_path)
 {
     const size_t base_path_len = strlen(base_path);
@@ -211,6 +555,8 @@ esp_err_t esp_vfs_unregister(const char* base_path)
     return ESP_ERR_INVALID_STATE;
 }
 
+esp_err_t esp_vfs_unregister_fs(const char* base_path) __attribute__((alias("esp_vfs_unregister")));
+
 esp_err_t esp_vfs_register_fd(esp_vfs_id_t vfs_id, int *fd)
 {
     return esp_vfs_register_fd_with_local_fd(vfs_id, -1, true, fd);
@@ -290,6 +636,22 @@ void esp_vfs_dump_fds(FILE *fp)
     _lock_release(&s_fd_table_lock);
 }
 
+void esp_vfs_dump_registered_paths(FILE *fp)
+{
+    fprintf(fp, "------------------------------------------------------\n");
+    fprintf(fp, "<index>:<VFS Path Prefix> -> <VFS entry ptr>\n");
+    fprintf(fp, "------------------------------------------------------\n");
+    for (size_t i = 0; i < VFS_MAX_COUNT; ++i) {
+        fprintf(
+            fp,
+            "%d:%s -> %p\n",
+            i,
+            s_vfs[i] ? s_vfs[i]->path_prefix : "NULL",
+            s_vfs[i] ? s_vfs[i]->vfs : NULL
+        );
+    }
+}
+
 /*
  * Set ESP_VFS_FLAG_READONLY_FS read-only flag for a registered virtual filesystem
  * for given path prefix. Should be only called from the esp_vfs_*filesystem* register
@@ -306,7 +668,7 @@ esp_err_t esp_vfs_set_readonly_flag(const char* base_path)
         }
         if (base_path_len == vfs->path_prefix_len &&
                 memcmp(base_path, vfs->path_prefix, vfs->path_prefix_len) == 0) {
-            vfs->vfs.flags |= ESP_VFS_FLAG_READONLY_FS;
+            vfs->flags |= ESP_VFS_FLAG_READONLY_FS;
             return ESP_OK;
         }
     }
@@ -365,7 +727,7 @@ const vfs_entry_t* get_vfs_for_path(const char* path)
     size_t len = strlen(path);
     for (size_t i = 0; i < s_vfs_count; ++i) {
         const vfs_entry_t* vfs = s_vfs[i];
-        if (!vfs || vfs->path_prefix_len == LEN_PATH_PREFIX_IGNORED) {
+        if (vfs == NULL || vfs->path_prefix_len == LEN_PATH_PREFIX_IGNORED) {
             continue;
         }
         // match path prefix
@@ -411,37 +773,69 @@ const vfs_entry_t* get_vfs_for_path(const char* path)
  * It is enough to check just one of them for NULL, as both variants are part of a union.
  */
 #define CHECK_AND_CALL(ret, r, pvfs, func, ...) \
-    if (pvfs->vfs.func == NULL) { \
+    if (pvfs->vfs->func == NULL) { \
         __errno_r(r) = ENOSYS; \
         return -1; \
     } \
-    if (pvfs->vfs.flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
-        ret = (*pvfs->vfs.func ## _p)(pvfs->ctx, __VA_ARGS__); \
+    if (pvfs->flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
+        ret = (*pvfs->vfs->func ## _p)(pvfs->ctx, __VA_ARGS__); \
     } else { \
-        ret = (*pvfs->vfs.func)(__VA_ARGS__);\
+        ret = (*pvfs->vfs->func)(__VA_ARGS__);\
     }
 
+#define CHECK_AND_CALL_SUBCOMPONENT(ret, r, pvfs, component, func, ...) \
+    if (pvfs->vfs->component == NULL || pvfs->vfs->component->func == NULL) { \
+        __errno_r(r) = ENOSYS; \
+        return -1; \
+    } \
+    if (pvfs->flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
+        ret = (*pvfs->vfs->component->func ## _p)(pvfs->ctx, __VA_ARGS__); \
+    } else { \
+        ret = (*pvfs->vfs->component->func)(__VA_ARGS__);\
+    }
 
 #define CHECK_AND_CALLV(r, pvfs, func, ...) \
-    if (pvfs->vfs.func == NULL) { \
+    if (pvfs->vfs->func == NULL) { \
         __errno_r(r) = ENOSYS; \
         return; \
     } \
-    if (pvfs->vfs.flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
-        (*pvfs->vfs.func ## _p)(pvfs->ctx, __VA_ARGS__); \
+    if (pvfs->flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
+        (*pvfs->vfs->func ## _p)(pvfs->ctx, __VA_ARGS__); \
     } else { \
-        (*pvfs->vfs.func)(__VA_ARGS__);\
+        (*pvfs->vfs->func)(__VA_ARGS__);\
+    }
+
+#define CHECK_AND_CALL_SUBCOMPONENTV(r, pvfs, component, func, ...) \
+    if (pvfs->vfs->component == NULL || pvfs->vfs->component->func == NULL) { \
+        __errno_r(r) = ENOSYS; \
+        return; \
+    } \
+    if (pvfs->flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
+        (*pvfs->vfs->component->func ## _p)(pvfs->ctx, __VA_ARGS__); \
+    } else { \
+        (*pvfs->vfs->component->func)(__VA_ARGS__);\
     }
 
 #define CHECK_AND_CALLP(ret, r, pvfs, func, ...) \
-    if (pvfs->vfs.func == NULL) { \
+    if (pvfs->vfs->func == NULL) { \
+        __errno_r(r) = ENOSYS; \
+        return NULL; \
+    } \
+    if (pvfs->flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
+        ret = (*pvfs->vfs->func ## _p)(pvfs->ctx, __VA_ARGS__); \
+    } else { \
+        ret = (*pvfs->vfs->func)(__VA_ARGS__);\
+    }
+
+#define CHECK_AND_CALL_SUBCOMPONENTP(ret, r, pvfs, component, func, ...) \
+    if (pvfs->vfs->component == NULL || pvfs->vfs->component->func == NULL) { \
         __errno_r(r) = ENOSYS; \
         return NULL; \
     } \
-    if (pvfs->vfs.flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
-        ret = (*pvfs->vfs.func ## _p)(pvfs->ctx, __VA_ARGS__); \
+    if (pvfs->flags & ESP_VFS_FLAG_CONTEXT_PTR) { \
+        ret = (*pvfs->vfs->component->func ## _p)(pvfs->ctx, __VA_ARGS__); \
     } else { \
-        ret = (*pvfs->vfs.func)(__VA_ARGS__);\
+        ret = (*pvfs->vfs->component->func)(__VA_ARGS__);\
     }
 
 #define CHECK_VFS_READONLY_FLAG(flags) \
@@ -459,7 +853,7 @@ int esp_vfs_open(struct _reent *r, const char * path, int flags, int mode)
     }
 
     int acc_mode = flags & O_ACCMODE;
-    int ro_filesystem = vfs->vfs.flags & ESP_VFS_FLAG_READONLY_FS;
+    int ro_filesystem = vfs->flags & ESP_VFS_FLAG_READONLY_FS;
     if (acc_mode != O_RDONLY && ro_filesystem) {
         __errno_r(r) = EROFS;
         return -1;
@@ -648,7 +1042,7 @@ int esp_vfs_stat(struct _reent *r, const char * path, struct stat * st)
     }
     const char* path_within_vfs = translate_path(vfs, path);
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, stat, path_within_vfs, st);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, stat, path_within_vfs, st);
     return ret;
 }
 
@@ -662,7 +1056,7 @@ int esp_vfs_utime(const char *path, const struct utimbuf *times)
         return -1;
     }
     const char* path_within_vfs = translate_path(vfs, path);
-    CHECK_AND_CALL(ret, r, vfs, utime, path_within_vfs, times);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, utime, path_within_vfs, times);
     return ret;
 }
 
@@ -679,12 +1073,12 @@ int esp_vfs_link(struct _reent *r, const char* n1, const char* n2)
         return -1;
     }
 
-    CHECK_VFS_READONLY_FLAG(vfs2->vfs.flags);
+    CHECK_VFS_READONLY_FLAG(vfs2->flags);
 
     const char* path1_within_vfs = translate_path(vfs, n1);
     const char* path2_within_vfs = translate_path(vfs, n2);
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, link, path1_within_vfs, path2_within_vfs);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, link, path1_within_vfs, path2_within_vfs);
     return ret;
 }
 
@@ -696,11 +1090,11 @@ int esp_vfs_unlink(struct _reent *r, const char *path)
         return -1;
     }
 
-    CHECK_VFS_READONLY_FLAG(vfs->vfs.flags);
+    CHECK_VFS_READONLY_FLAG(vfs->flags);
 
     const char* path_within_vfs = translate_path(vfs, path);
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, unlink, path_within_vfs);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, unlink, path_within_vfs);
     return ret;
 }
 
@@ -712,7 +1106,7 @@ int esp_vfs_rename(struct _reent *r, const char *src, const char *dst)
         return -1;
     }
 
-    CHECK_VFS_READONLY_FLAG(vfs->vfs.flags);
+    CHECK_VFS_READONLY_FLAG(vfs->flags);
 
     const vfs_entry_t* vfs_dst = get_vfs_for_path(dst);
     if (vfs != vfs_dst) {
@@ -720,12 +1114,12 @@ int esp_vfs_rename(struct _reent *r, const char *src, const char *dst)
         return -1;
     }
 
-    CHECK_VFS_READONLY_FLAG(vfs_dst->vfs.flags);
+    CHECK_VFS_READONLY_FLAG(vfs_dst->flags);
 
     const char* src_within_vfs = translate_path(vfs, src);
     const char* dst_within_vfs = translate_path(vfs, dst);
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, rename, src_within_vfs, dst_within_vfs);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, rename, src_within_vfs, dst_within_vfs);
     return ret;
 }
 
@@ -739,7 +1133,7 @@ DIR* esp_vfs_opendir(const char* name)
     }
     const char* path_within_vfs = translate_path(vfs, name);
     DIR* ret;
-    CHECK_AND_CALLP(ret, r, vfs, opendir, path_within_vfs);
+    CHECK_AND_CALL_SUBCOMPONENTP(ret, r, vfs, dir, opendir, path_within_vfs);
     if (ret != NULL) {
         ret->dd_vfs_idx = vfs->offset;
     }
@@ -755,7 +1149,7 @@ struct dirent* esp_vfs_readdir(DIR* pdir)
         return NULL;
     }
     struct dirent* ret;
-    CHECK_AND_CALLP(ret, r, vfs, readdir, pdir);
+    CHECK_AND_CALL_SUBCOMPONENTP(ret, r, vfs, dir, readdir, pdir);
     return ret;
 }
 
@@ -768,7 +1162,7 @@ int esp_vfs_readdir_r(DIR* pdir, struct dirent* entry, struct dirent** out_diren
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, readdir_r, pdir, entry, out_dirent);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, readdir_r, pdir, entry, out_dirent);
     return ret;
 }
 
@@ -781,7 +1175,7 @@ long esp_vfs_telldir(DIR* pdir)
         return -1;
     }
     long ret;
-    CHECK_AND_CALL(ret, r, vfs, telldir, pdir);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, telldir, pdir);
     return ret;
 }
 
@@ -793,7 +1187,7 @@ void esp_vfs_seekdir(DIR* pdir, long loc)
         errno = EBADF;
         return;
     }
-    CHECK_AND_CALLV(r, vfs, seekdir, pdir, loc);
+    CHECK_AND_CALL_SUBCOMPONENTV(r, vfs, dir, seekdir, pdir, loc);
 }
 
 void esp_vfs_rewinddir(DIR* pdir)
@@ -810,7 +1204,7 @@ int esp_vfs_closedir(DIR* pdir)
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, closedir, pdir);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, closedir, pdir);
     return ret;
 }
 
@@ -823,11 +1217,11 @@ int esp_vfs_mkdir(const char* name, mode_t mode)
         return -1;
     }
 
-    CHECK_VFS_READONLY_FLAG(vfs->vfs.flags);
+    CHECK_VFS_READONLY_FLAG(vfs->flags);
 
     const char* path_within_vfs = translate_path(vfs, name);
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, mkdir, path_within_vfs, mode);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, mkdir, path_within_vfs, mode);
     return ret;
 }
 
@@ -840,11 +1234,11 @@ int esp_vfs_rmdir(const char* name)
         return -1;
     }
 
-    CHECK_VFS_READONLY_FLAG(vfs->vfs.flags);
+    CHECK_VFS_READONLY_FLAG(vfs->flags);
 
     const char* path_within_vfs = translate_path(vfs, name);
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, rmdir, path_within_vfs);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, rmdir, path_within_vfs);
     return ret;
 }
 
@@ -858,7 +1252,7 @@ int esp_vfs_access(const char *path, int amode)
         return -1;
     }
     const char* path_within_vfs = translate_path(vfs, path);
-    CHECK_AND_CALL(ret, r, vfs, access, path_within_vfs, amode);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, access, path_within_vfs, amode);
     return ret;
 }
 
@@ -872,10 +1266,10 @@ int esp_vfs_truncate(const char *path, off_t length)
         return -1;
     }
 
-    CHECK_VFS_READONLY_FLAG(vfs->vfs.flags);
+    CHECK_VFS_READONLY_FLAG(vfs->flags);
 
     const char* path_within_vfs = translate_path(vfs, path);
-    CHECK_AND_CALL(ret, r, vfs, truncate, path_within_vfs, length);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, truncate, path_within_vfs, length);
     return ret;
 }
 
@@ -889,10 +1283,10 @@ int esp_vfs_ftruncate(int fd, off_t length)
         return -1;
     }
 
-    CHECK_VFS_READONLY_FLAG(vfs->vfs.flags);
+    CHECK_VFS_READONLY_FLAG(vfs->flags);
 
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, ftruncate, local_fd, length);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, dir, ftruncate, local_fd, length);
     return ret;
 }
 
@@ -905,8 +1299,12 @@ static void call_end_selects(int end_index, const fds_triple_t *vfs_fds_triple,
     for (int i = 0; i < end_index; ++i) {
         const vfs_entry_t *vfs = get_vfs_for_index(i);
         const fds_triple_t *item = &vfs_fds_triple[i];
-        if (vfs && vfs->vfs.end_select && item->isset) {
-            esp_err_t err = vfs->vfs.end_select(driver_args[i]);
+        if (vfs != NULL
+            && vfs->vfs->select != NULL
+            && vfs->vfs->select->end_select != NULL
+            && item->isset
+        ) {
+            esp_err_t err = vfs->vfs->select->end_select(driver_args[i]);
             if (err != ESP_OK) {
                 ESP_LOGD(TAG, "end_select failed: %s", esp_err_to_name(err));
             }
@@ -1023,8 +1421,8 @@ int esp_vfs_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds
                         esp_vfs_safe_fd_isset(fd, writefds) ||
                         esp_vfs_safe_fd_isset(fd, errorfds)) {
                     const vfs_entry_t *vfs = s_vfs[vfs_index];
-                    socket_select = vfs->vfs.socket_select;
-                    sel_sem.sem = vfs->vfs.get_socket_select_semaphore();
+                    socket_select = vfs->vfs->select->socket_select;
+                    sel_sem.sem = vfs->vfs->select->get_socket_select_semaphore();
                 }
             }
             continue;
@@ -1080,33 +1478,38 @@ int esp_vfs_select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds
         const vfs_entry_t *vfs = get_vfs_for_index(i);
         fds_triple_t *item = &vfs_fds_triple[i];
 
-        if (vfs && !vfs->vfs.start_select) {
+        if (vfs == NULL || vfs->vfs->select == NULL || vfs->vfs->select->start_select == NULL) {
             ESP_LOGD(TAG, "start_select function callback for this vfs (s_vfs[%d]) is not defined", vfs->offset);
-        } else if (vfs && vfs->vfs.start_select && item->isset) {
-            // call start_select for all non-socket VFSs with has at least one FD set in readfds, writefds, or errorfds
-            // note: it can point to socket VFS but item->isset will be false for that
-            ESP_LOGD(TAG, "calling start_select for VFS ID %d with the following local FDs", i);
-            esp_vfs_log_fd_set("readfds", &item->readfds);
-            esp_vfs_log_fd_set("writefds", &item->writefds);
-            esp_vfs_log_fd_set("errorfds", &item->errorfds);
-            esp_err_t err = vfs->vfs.start_select(nfds, &item->readfds, &item->writefds, &item->errorfds, sel_sem,
-                    driver_args + i);
+            continue;
+        }
 
-            if (err != ESP_OK) {
-                if (err != ESP_ERR_NOT_SUPPORTED) {
-                    call_end_selects(i, vfs_fds_triple, driver_args);
-                }
-                (void) set_global_fd_sets(vfs_fds_triple, vfs_count, readfds, writefds, errorfds);
-                if (sel_sem.is_sem_local && sel_sem.sem) {
-                    vSemaphoreDelete(sel_sem.sem);
-                    sel_sem.sem = NULL;
-                }
-                free(vfs_fds_triple);
-                free(driver_args);
-                __errno_r(r) = EINTR;
-                ESP_LOGD(TAG, "start_select failed: %s", esp_err_to_name(err));
-                return -1;
+        if (!item->isset) {
+            continue;
+        }
+
+        // call start_select for all non-socket VFSs with has at least one FD set in readfds, writefds, or errorfds
+        // note: it can point to socket VFS but item->isset will be false for that
+        ESP_LOGD(TAG, "calling start_select for VFS ID %d with the following local FDs", i);
+        esp_vfs_log_fd_set("readfds", &item->readfds);
+        esp_vfs_log_fd_set("writefds", &item->writefds);
+        esp_vfs_log_fd_set("errorfds", &item->errorfds);
+        esp_err_t err = vfs->vfs->select->start_select(nfds, &item->readfds, &item->writefds, &item->errorfds, sel_sem,
+                driver_args + i);
+
+        if (err != ESP_OK) {
+            if (err != ESP_ERR_NOT_SUPPORTED) {
+                call_end_selects(i, vfs_fds_triple, driver_args);
             }
+            (void) set_global_fd_sets(vfs_fds_triple, vfs_count, readfds, writefds, errorfds);
+            if (sel_sem.is_sem_local && sel_sem.sem) {
+                vSemaphoreDelete(sel_sem.sem);
+                sel_sem.sem = NULL;
+            }
+            free(vfs_fds_triple);
+            free(driver_args);
+            __errno_r(r) = EINTR;
+            ESP_LOGD(TAG, "start_select failed: %s", esp_err_to_name(err));
+            return -1;
         }
     }
 
@@ -1193,8 +1596,11 @@ void esp_vfs_select_triggered(esp_vfs_select_sem_t sem)
             // Note: s_vfs_count could have changed since the start of vfs_select() call. However, that change doesn't
             // matter here stop_socket_select() will be called for only valid VFS drivers.
             const vfs_entry_t *vfs = s_vfs[i];
-            if (vfs != NULL && vfs->vfs.stop_socket_select != NULL) {
-                vfs->vfs.stop_socket_select(sem.sem);
+            if (vfs != NULL
+                && vfs->vfs->select != NULL
+                && vfs->vfs->select->stop_socket_select != NULL
+            ) {
+                vfs->vfs->select->stop_socket_select(sem.sem);
                 break;
             }
         }
@@ -1213,9 +1619,12 @@ void esp_vfs_select_triggered_isr(esp_vfs_select_sem_t sem, BaseType_t *woken)
             // Note: s_vfs_count could have changed since the start of vfs_select() call. However, that change doesn't
             // matter here stop_socket_select() will be called for only valid VFS drivers.
             const vfs_entry_t *vfs = s_vfs[i];
-            if (vfs != NULL && vfs->vfs.stop_socket_select_isr != NULL) {
+            if (vfs != NULL
+                && vfs->vfs->select != NULL
+                && vfs->vfs->select->stop_socket_select_isr != NULL
+            ) {
                 // Note: If the UART ISR resides in IRAM, the function referenced by stop_socket_select_isr should also be placed in IRAM.
-                vfs->vfs.stop_socket_select_isr(sem.sem, woken);
+                vfs->vfs->select->stop_socket_select_isr(sem.sem, woken);
                 break;
             }
         }
@@ -1236,7 +1645,7 @@ int tcgetattr(int fd, struct termios *p)
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, tcgetattr, local_fd, p);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, termios, tcgetattr, local_fd, p);
     return ret;
 }
 
@@ -1250,7 +1659,7 @@ int tcsetattr(int fd, int optional_actions, const struct termios *p)
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, tcsetattr, local_fd, optional_actions, p);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, termios, tcsetattr, local_fd, optional_actions, p);
     return ret;
 }
 
@@ -1264,7 +1673,7 @@ int tcdrain(int fd)
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, tcdrain, local_fd);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, termios, tcdrain, local_fd);
     return ret;
 }
 
@@ -1278,7 +1687,7 @@ int tcflush(int fd, int select)
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, tcflush, local_fd, select);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, termios, tcflush, local_fd, select);
     return ret;
 }
 
@@ -1292,7 +1701,7 @@ int tcflow(int fd, int action)
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, tcflow, local_fd, action);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, termios, tcflow, local_fd, action);
     return ret;
 }
 
@@ -1306,7 +1715,7 @@ pid_t tcgetsid(int fd)
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, tcgetsid, local_fd);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, termios, tcgetsid, local_fd);
     return ret;
 }
 
@@ -1320,7 +1729,7 @@ int tcsendbreak(int fd, int duration)
         return -1;
     }
     int ret;
-    CHECK_AND_CALL(ret, r, vfs, tcsendbreak, local_fd, duration);
+    CHECK_AND_CALL_SUBCOMPONENT(ret, r, vfs, termios, tcsendbreak, local_fd, duration);
     return ret;
 }
 #endif // CONFIG_VFS_SUPPORT_TERMIOS
diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_hostap.c b/components/wpa_supplicant/esp_supplicant/src/esp_hostap.c
index 45c256bf93a..0716ad5952b 100644
--- a/components/wpa_supplicant/esp_supplicant/src/esp_hostap.c
+++ b/components/wpa_supplicant/esp_supplicant/src/esp_hostap.c
@@ -7,6 +7,7 @@
 #include "utils/includes.h"
 
 #include "utils/common.h"
+#include "utils/eloop.h"
 #include "crypto/sha1.h"
 #include "common/ieee802_11_defs.h"
 #include "common/eapol_common.h"
@@ -21,6 +22,9 @@
 #include "esp_wps.h"
 #include "esp_wps_i.h"
 
+#include "ap/sta_info.h"
+#include "common/sae.h"
+#include "ap/ieee802_11.h"
 #define WIFI_PASSWORD_LEN_MAX 65
 
 struct hostapd_data *global_hapd;
@@ -320,3 +324,143 @@ u16 esp_send_assoc_resp(struct hostapd_data *hapd, const u8 *addr,
     os_free(reply);
     return res;
 }
+
+uint8_t wpa_status_to_reason_code(int status)
+{
+    switch (status) {
+    case WLAN_STATUS_INVALID_IE:
+        return WLAN_REASON_INVALID_IE;
+    case WLAN_STATUS_GROUP_CIPHER_NOT_VALID:
+        return WLAN_REASON_GROUP_CIPHER_NOT_VALID;
+    case WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID:
+        return WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID;
+    case WLAN_STATUS_AKMP_NOT_VALID:
+        return WLAN_REASON_AKMP_NOT_VALID;
+    case WLAN_STATUS_CIPHER_REJECTED_PER_POLICY:
+        return WLAN_REASON_CIPHER_SUITE_REJECTED;
+    case WLAN_STATUS_INVALID_PMKID:
+        return WLAN_REASON_INVALID_PMKID;
+    case WLAN_STATUS_INVALID_MDIE:
+        return WLAN_REASON_INVALID_MDE;
+    default:
+        return WLAN_REASON_UNSPECIFIED;
+    }
+}
+
+bool hostap_new_assoc_sta(struct sta_info *sta, uint8_t *bssid, uint8_t *wpa_ie,
+                          uint8_t wpa_ie_len, uint8_t *rsnxe, uint8_t rsnxe_len,
+                          bool *pmf_enable, int subtype, uint8_t *pairwise_cipher, uint8_t *reason)
+{
+    struct hostapd_data *hapd = (struct hostapd_data*)esp_wifi_get_hostap_private_internal();
+    enum wpa_validate_result res = WPA_IE_OK;
+    int status = WLAN_STATUS_SUCCESS;
+    bool omit_rsnxe = false;
+
+    if (!sta || !bssid || !wpa_ie) {
+        return false;
+    }
+
+    if (hapd) {
+        if (hapd->wpa_auth->conf.wpa) {
+            if (sta->wpa_sm) {
+                wpa_auth_sta_deinit(sta->wpa_sm);
+            }
+
+            sta->wpa_sm = wpa_auth_sta_init(hapd->wpa_auth, bssid);
+            wpa_printf(MSG_DEBUG, "init wpa sm=%p", sta->wpa_sm);
+
+            if (sta->wpa_sm == NULL) {
+                status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
+                goto send_resp;
+            }
+
+            res = wpa_validate_wpa_ie(hapd->wpa_auth, sta->wpa_sm, wpa_ie, wpa_ie_len, rsnxe, rsnxe_len);
+
+#ifdef CONFIG_SAE
+            if (wpa_auth_uses_sae(sta->wpa_sm) && sta->sae &&
+                    sta->sae->state == SAE_ACCEPTED) {
+                wpa_auth_add_sae_pmkid(sta->wpa_sm, sta->sae->pmkid);
+            }
+#endif /* CONFIG_SAE */
+
+            status = wpa_res_to_status_code(res);
+
+send_resp:
+            if (!rsnxe) {
+                omit_rsnxe = true;
+            }
+
+            if (esp_send_assoc_resp(hapd, bssid, status, omit_rsnxe, subtype) != WLAN_STATUS_SUCCESS) {
+                status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
+            }
+
+            if (status != WLAN_STATUS_SUCCESS) {
+                *reason = wpa_status_to_reason_code(status);
+                return false;
+            }
+
+            //Check whether AP uses Management Frame Protection for this connection
+            *pmf_enable = wpa_auth_uses_mfp(sta->wpa_sm);
+            *pairwise_cipher = GET_BIT_POSITION(sta->wpa_sm->pairwise);
+        }
+
+        wpa_auth_sta_associated(hapd->wpa_auth, sta->wpa_sm);
+    }
+
+    return true;
+}
+
+#ifdef CONFIG_WPS_REGISTRAR
+static void ap_free_sta_timeout(void *ctx, void *data)
+{
+    struct hostapd_data *hapd = (struct hostapd_data *) ctx;
+    u8 *addr = (u8 *) data;
+    struct sta_info *sta = ap_get_sta(hapd, addr);
+
+    if (sta) {
+        ap_free_sta(hapd, sta);
+    }
+
+    os_free(addr);
+}
+#endif
+
+bool wpa_ap_remove(u8* bssid)
+{
+    struct hostapd_data *hapd = hostapd_get_hapd_data();
+
+    if (!hapd) {
+        return false;
+    }
+    struct sta_info *sta = ap_get_sta(hapd, bssid);
+    if (!sta) {
+        return false;
+    }
+
+#ifdef CONFIG_SAE
+    if (sta->lock) {
+        if (os_semphr_take(sta->lock, 0)) {
+            ap_free_sta(hapd, sta);
+        } else {
+            sta->remove_pending = true;
+        }
+        return true;
+    }
+#endif /* CONFIG_SAE */
+
+#ifdef CONFIG_WPS_REGISTRAR
+    wpa_printf(MSG_DEBUG, "wps_status=%d", wps_get_status());
+    if (wps_get_status() == WPS_STATUS_PENDING) {
+        u8 *addr = os_malloc(ETH_ALEN);
+
+        if (!addr) {
+            return false;
+        }
+        os_memcpy(addr, sta->addr, ETH_ALEN);
+        eloop_register_timeout(0, 10000, ap_free_sta_timeout, hapd, addr);
+    } else
+#endif
+        ap_free_sta(hapd, sta);
+
+    return true;
+}
diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wifi_driver.h b/components/wpa_supplicant/esp_supplicant/src/esp_wifi_driver.h
index d5ca7fd7163..a07650603d8 100644
--- a/components/wpa_supplicant/esp_supplicant/src/esp_wifi_driver.h
+++ b/components/wpa_supplicant/esp_supplicant/src/esp_wifi_driver.h
@@ -144,6 +144,7 @@ struct wpa_funcs {
     void (*wpa_config_done)(void);
     uint8_t *(*owe_build_dhie)(uint16_t group);
     int (*owe_process_assoc_resp)(const u8 *rsn_ie, size_t rsn_len, const uint8_t *dh_ie, size_t dh_len);
+    void (*wpa_sta_clear_curr_pmksa)(void);
 };
 
 struct wpa2_funcs {
diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c b/components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c
index 76fa0f5f32e..e66b2a745d8 100644
--- a/components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c
+++ b/components/wpa_supplicant/esp_supplicant/src/esp_wpa3.c
@@ -647,6 +647,9 @@ bool wpa3_hostap_auth_deinit(void)
 static int wpa3_hostap_handle_auth(u8 *buf, size_t len, u32 auth_transaction, u16 status, u8 *bssid)
 {
     struct hostapd_data *hapd = (struct hostapd_data *)esp_wifi_get_hostap_private_internal();
+    if (!hapd) {
+        return ESP_FAIL;
+    }
     struct sta_info *sta = ap_get_sta(hapd, bssid);
     if (auth_transaction == SAE_MSG_COMMIT) {
         if (sta && sta->sae_commit_processing) {
diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c b/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c
index 6de23146428..09532deb126 100644
--- a/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c
+++ b/components/wpa_supplicant/esp_supplicant/src/esp_wpa_main.c
@@ -287,8 +287,8 @@ static void wpa_sta_disconnected_cb(uint8_t reason_code)
 {
     switch (reason_code) {
     case WIFI_REASON_AUTH_EXPIRE:
-    case WIFI_REASON_NOT_AUTHED:
-    case WIFI_REASON_NOT_ASSOCED:
+    case WIFI_REASON_CLASS2_FRAME_FROM_NONAUTH_STA:
+    case WIFI_REASON_CLASS3_FRAME_FROM_NONASSOC_STA:
     case WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT:
     case WIFI_REASON_INVALID_PMKID:
     case WIFI_REASON_AUTH_FAIL:
@@ -356,6 +356,7 @@ static bool hostap_sta_join(void **sta, u8 *bssid, u8 *wpa_ie, u8 wpa_ie_len, u8
 {
     struct sta_info *sta_info = NULL;
     struct hostapd_data *hapd = hostapd_get_hapd_data();
+    uint8_t reason = WLAN_REASON_PREV_AUTH_NOT_VALID;
 
     if (!hapd) {
         goto fail;
@@ -413,7 +414,7 @@ static bool hostap_sta_join(void **sta, u8 *bssid, u8 *wpa_ie, u8 wpa_ie_len, u8
         goto fail;
     }
 #endif
-    if (wpa_ap_join(sta_info, bssid, wpa_ie, wpa_ie_len, rsnxe, rsnxe_len, pmf_enable, subtype, pairwise_cipher)) {
+    if (hostap_new_assoc_sta(sta_info, bssid, wpa_ie, wpa_ie_len, rsnxe, rsnxe_len, pmf_enable, subtype, pairwise_cipher, &reason)) {
         goto done;
     } else {
         goto fail;
@@ -434,7 +435,7 @@ static bool hostap_sta_join(void **sta, u8 *bssid, u8 *wpa_ie, u8 wpa_ie_len, u8
         os_semphr_give(sta_info->lock);
     }
 #endif /* CONFIG_SAE */
-    esp_wifi_ap_deauth_internal(bssid, WLAN_REASON_PREV_AUTH_NOT_VALID);
+    esp_wifi_ap_deauth_internal(bssid, reason);
     return false;
 }
 #endif
@@ -475,6 +476,7 @@ int esp_supplicant_init(void)
     wpa_cb->wpa_config_bss = NULL;//wpa_config_bss;
     wpa_cb->wpa_michael_mic_failure = wpa_michael_mic_failure;
     wpa_cb->wpa_config_done = wpa_config_done;
+    wpa_cb->wpa_sta_clear_curr_pmksa = wpa_sta_clear_curr_pmksa;
 
     esp_wifi_register_wpa3_ap_cb(wpa_cb);
     esp_wifi_register_wpa3_cb(wpa_cb);
diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c
index ae84728bf8a..c67413b1271 100644
--- a/components/wpa_supplicant/esp_supplicant/src/esp_wps.c
+++ b/components/wpa_supplicant/esp_supplicant/src/esp_wps.c
@@ -930,7 +930,7 @@ int wps_start_msg_timer(void)
         ret = 0;
     } else if (sm->wps->state == RECV_M2) {
         msg_timeout = 5;
-        wpa_printf(MSG_DEBUG, "start msg timer RECV_M2 %" PRId32 " ms", msg_timeout);
+        wpa_printf(MSG_DEBUG, "start msg timer RECV_M2 %" PRId32 " s", msg_timeout);
 	eloop_cancel_timeout(wifi_station_wps_msg_timeout, NULL, NULL);
 	eloop_register_timeout(msg_timeout, 0, wifi_station_wps_msg_timeout, NULL, NULL);
         ret = 0;
diff --git a/components/wpa_supplicant/sbom.yml b/components/wpa_supplicant/sbom.yml
new file mode 100644
index 00000000000..c283feb6320
--- /dev/null
+++ b/components/wpa_supplicant/sbom.yml
@@ -0,0 +1,6 @@
+name: 'wpa_supplicant'
+version: '2.10'
+cpe: cpe:2.3:a:w1.fi:wpa_supplicant:{}:*:*:*:*:*:*:*
+supplier: 'Organization: Espressif Systems (Shanghai) CO LTD'
+originator: 'Person: Jouni Malinen'
+description: Espressif fork of wpa_supplicant - an open-source WPA/WPA2/WPA3/IEEE 802.1X Supplicant.
diff --git a/components/wpa_supplicant/src/ap/ap_config.h b/components/wpa_supplicant/src/ap/ap_config.h
index 486d802a119..1d11dd4816b 100644
--- a/components/wpa_supplicant/src/ap/ap_config.h
+++ b/components/wpa_supplicant/src/ap/ap_config.h
@@ -382,9 +382,9 @@ const u8 * hostapd_get_psk(const struct hostapd_bss_config *conf,
 			   const u8 *addr, const u8 *prev_psk);
 int hostapd_setup_wpa_psk(struct hostapd_bss_config *conf);
 struct sta_info;
-bool wpa_ap_join(struct sta_info *sta, uint8_t *bssid, uint8_t *wpa_ie,
+bool hostap_new_assoc_sta(struct sta_info *sta, uint8_t *bssid, uint8_t *wpa_ie,
 		 uint8_t wpa_ie_len,uint8_t *rsnxe, uint8_t rsnxe_len,
-		 bool *pmf_enable, int subtype, uint8_t *pairwise_cipher);
+		 bool *pmf_enable, int subtype, uint8_t *pairwise_cipher, uint8_t *reason);
 bool wpa_ap_remove(u8* bssid);
 
 #endif /* HOSTAPD_CONFIG_H */
diff --git a/components/wpa_supplicant/src/ap/wpa_auth.c b/components/wpa_supplicant/src/ap/wpa_auth.c
index 513ec9fa822..58748a85ff3 100644
--- a/components/wpa_supplicant/src/ap/wpa_auth.c
+++ b/components/wpa_supplicant/src/ap/wpa_auth.c
@@ -13,7 +13,6 @@
 #include "common/ieee802_11_defs.h"
 #include "common/sae.h"
 #include "ap/sta_info.h"
-#include "ap/ieee802_11.h"
 #include "ap/wpa_auth.h"
 #include "ap/wpa_auth_i.h"
 #include "ap/wpa_auth_ie.h"
@@ -36,7 +35,6 @@
 #include "esp_wifi.h"
 #include "esp_private/wifi.h"
 #include "esp_wpas_glue.h"
-#include "esp_wps_i.h"
 #include "esp_hostap.h"
 
 #define STATE_MACHINE_DATA struct wpa_state_machine
@@ -2557,97 +2555,6 @@ void wpa_deinit(struct wpa_authenticator *wpa_auth)
 
 }
 
-#ifdef CONFIG_ESP_WIFI_SOFTAP_SUPPORT
-bool wpa_ap_join(struct sta_info *sta, uint8_t *bssid, uint8_t *wpa_ie,
-                uint8_t wpa_ie_len, uint8_t *rsnxe, uint8_t rsnxe_len,
-                bool *pmf_enable, int subtype, uint8_t *pairwise_cipher)
-{
-    struct hostapd_data *hapd = (struct hostapd_data*)esp_wifi_get_hostap_private_internal();
-    enum wpa_validate_result status_code = WPA_IE_OK;
-    int resp = WLAN_STATUS_SUCCESS;
-    bool omit_rsnxe = false;
-
-    if (!sta || !bssid || !wpa_ie) {
-        return false;
-    }
-
-    if (hapd) {
-        if (hapd->wpa_auth->conf.wpa) {
-            if (sta->wpa_sm){
-                wpa_auth_sta_deinit(sta->wpa_sm);
-            }
-
-            sta->wpa_sm = wpa_auth_sta_init(hapd->wpa_auth, bssid);
-            wpa_printf( MSG_DEBUG, "init wpa sm=%p", sta->wpa_sm);
-
-            if (sta->wpa_sm == NULL) {
-                resp = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
-                goto send_resp;
-            }
-
-            status_code = wpa_validate_wpa_ie(hapd->wpa_auth, sta->wpa_sm, wpa_ie, wpa_ie_len, rsnxe, rsnxe_len);
-
-#ifdef CONFIG_SAE
-            if (wpa_auth_uses_sae(sta->wpa_sm) && sta->sae &&
-                sta->sae->state == SAE_ACCEPTED) {
-                wpa_auth_add_sae_pmkid(sta->wpa_sm, sta->sae->pmkid);
-            }
-#endif /* CONFIG_SAE */
-
-            resp = wpa_res_to_status_code(status_code);
-
-send_resp:
-            if (!rsnxe) {
-                omit_rsnxe = true;
-            }
-
-            if (esp_send_assoc_resp(hapd, bssid, resp, omit_rsnxe, subtype) != WLAN_STATUS_SUCCESS) {
-                resp = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA;
-            }
-
-            if (resp != WLAN_STATUS_SUCCESS) {
-                return false;
-            }
-
-            //Check whether AP uses Management Frame Protection for this connection
-            *pmf_enable = wpa_auth_uses_mfp(sta->wpa_sm);
-            *pairwise_cipher = GET_BIT_POSITION(sta->wpa_sm->pairwise);
-        }
-
-        wpa_auth_sta_associated(hapd->wpa_auth, sta->wpa_sm);
-    }
-
-    return true;
-}
-
-bool wpa_ap_remove(u8* bssid)
-{
-    struct hostapd_data *hapd = hostapd_get_hapd_data();
-
-    if (!hapd) {
-        return false;
-    }
-    struct sta_info *sta = ap_get_sta(hapd, bssid);
-    if (!sta) {
-        return false;
-    }
-
-#ifdef CONFIG_SAE
-    if (sta->lock) {
-        if (os_semphr_take(sta->lock, 0)) {
-            ap_free_sta(hapd, sta);
-        } else {
-            sta->remove_pending = true;
-        }
-        return true;
-    }
-#endif /* CONFIG_SAE */
-    ap_free_sta(hapd, sta);
-
-    return true;
-}
-#endif /* CONFIG_ESP_WIFI_SOFTAP_SUPPORT */
-
 void wpa_auth_pmksa_remove(struct wpa_authenticator *wpa_auth,
                const u8 *sta_addr)
 {
diff --git a/components/wpa_supplicant/src/common/ieee802_11_defs.h b/components/wpa_supplicant/src/common/ieee802_11_defs.h
index b496690ab78..958bf5feeb1 100644
--- a/components/wpa_supplicant/src/common/ieee802_11_defs.h
+++ b/components/wpa_supplicant/src/common/ieee802_11_defs.h
@@ -186,6 +186,8 @@
 #define WLAN_REASON_INVALID_RSN_IE_CAPAB 22
 #define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23
 #define WLAN_REASON_CIPHER_SUITE_REJECTED 24
+#define WLAN_REASON_INVALID_PMKID 49
+#define WLAN_REASON_INVALID_MDE 50
 
 /* Information Element IDs (IEEE Std 802.11-2016, 9.4.2.1, Table 9-77) */
 #define WLAN_EID_SSID 0
diff --git a/docs/_static/ESP32-S3-DevKitC-1_v1-SystemBlock.png b/docs/_static/ESP32-S3-DevKitC-1_v1-SystemBlock.png
deleted file mode 100644
index feb598763f3..00000000000
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diff --git a/docs/_static/ESP32-S3-DevKitC-1_v1-annotated-photo.png b/docs/_static/ESP32-S3-DevKitC-1_v1-annotated-photo.png
deleted file mode 100644
index 8a0ae98b395..00000000000
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diff --git a/docs/_static/ESP32-S3-DevKitC-1_v1.1-annotated-photo.png b/docs/_static/ESP32-S3-DevKitC-1_v1.1-annotated-photo.png
deleted file mode 100644
index 753c3c189d7..00000000000
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diff --git a/docs/_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png b/docs/_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png
deleted file mode 100644
index 58ab4f25a83..00000000000
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deleted file mode 100644
index ce2b1ff6153..00000000000
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deleted file mode 100644
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deleted file mode 100644
index da4ab97645b..00000000000
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deleted file mode 100644
index f24fd6762f3..00000000000
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diff --git a/docs/_static/ESP32-S3_DevKitC-1_pinlayout_v1.1.jpg b/docs/_static/ESP32-S3_DevKitC-1_pinlayout_v1.1.jpg
deleted file mode 100644
index 703145ebed7..00000000000
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diff --git a/docs/_static/ESP32-S3_DevKitM-1_pinlayout.jpg b/docs/_static/ESP32-S3_DevKitM-1_pinlayout.jpg
deleted file mode 100644
index ca39d7d2bbc..00000000000
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deleted file mode 100644
index 359251737f6..00000000000
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diff --git a/docs/_static/esp32-DevKitM-1-front.png b/docs/_static/esp32-DevKitM-1-front.png
deleted file mode 100644
index 5685040471e..00000000000
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deleted file mode 100644
index af9aa306cb8..00000000000
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diff --git a/docs/_static/esp32-DevKitM-1_v1_SystemBlock.png b/docs/_static/esp32-DevKitM-1_v1_SystemBlock.png
deleted file mode 100644
index 35eac16c8d9..00000000000
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deleted file mode 100644
index ffcaa4ac48f..00000000000
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diff --git a/docs/_static/esp32-s2-saola-1-v1.2-annotated-photo.png b/docs/_static/esp32-s2-saola-1-v1.2-annotated-photo.png
deleted file mode 100644
index 0178b161297..00000000000
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diff --git a/docs/_static/esp32-s2-saola-1-v1.2-block-diags.png b/docs/_static/esp32-s2-saola-1-v1.2-block-diags.png
deleted file mode 100644
index 7cb5f2ddf23..00000000000
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deleted file mode 100644
index 8c1b4ce596d..00000000000
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diff --git a/docs/_static/esp32-s2_saola1-pinout.jpg b/docs/_static/esp32-s2_saola1-pinout.jpg
deleted file mode 100644
index 3f42688751c..00000000000
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diff --git a/docs/_static/esp32-s3-devkitc-1-v1-isometric.png b/docs/_static/esp32-s3-devkitc-1-v1-isometric.png
deleted file mode 100644
index 628672a1c3c..00000000000
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diff --git a/docs/_static/esp32-s3-devkitc-1-v1.1-isometric.png b/docs/_static/esp32-s3-devkitc-1-v1.1-isometric.png
deleted file mode 100644
index 3eb0a731a15..00000000000
Binary files a/docs/_static/esp32-s3-devkitc-1-v1.1-isometric.png and /dev/null differ
diff --git a/docs/_static/esp32-s3-devkitm-1-v1-isometric.png b/docs/_static/esp32-s3-devkitm-1-v1-isometric.png
deleted file mode 100644
index 67b4607b967..00000000000
Binary files a/docs/_static/esp32-s3-devkitm-1-v1-isometric.png and /dev/null differ
diff --git a/docs/_static/menuconfig-screen.png b/docs/_static/menuconfig-screen.png
new file mode 100644
index 00000000000..451647074a6
Binary files /dev/null and b/docs/_static/menuconfig-screen.png differ
diff --git a/docs/_static/usb_host/poweron-timings.png b/docs/_static/usb_host/poweron-timings.png
index 867253da18d..59973ec9cef 100644
Binary files a/docs/_static/usb_host/poweron-timings.png and b/docs/_static/usb_host/poweron-timings.png differ
diff --git a/docs/conf_common.py b/docs/conf_common.py
index 2a9a6fee84b..e8d75279a7c 100644
--- a/docs/conf_common.py
+++ b/docs/conf_common.py
@@ -129,7 +129,8 @@
             'api-reference/peripherals/usb_host/usb_host_notes_index.rst',
             'api-reference/peripherals/usb_host/usb_host_notes_usbh.rst',
             'api-reference/peripherals/usb_host/usb_host_notes_enum.rst',
-            'api-reference/peripherals/usb_host/usb_host_notes_ext_hub.rst']
+            'api-reference/peripherals/usb_host/usb_host_notes_ext_hub.rst',
+            'api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst']
 
 I80_LCD_DOCS = ['api-reference/peripherals/lcd/i80_lcd.rst']
 RGB_LCD_DOCS = ['api-reference/peripherals/lcd/rgb_lcd.rst']
@@ -207,7 +208,7 @@
                 'api-reference/peripherals/ds.rst',
                 'api-reference/peripherals/temp_sensor.rst',
                 'api-reference/system/async_memcpy.rst',
-                'api-reference/peripherals/touch_pad.rst',
+                'api-reference/peripherals/cap_touch_sens.rst',
                 'api-reference/peripherals/touch_element.rst',
                 'api-guides/RF_calibration.rst',
                 'api-guides/phy.rst'] + FTDI_JTAG_DOCS + USB_OTG_DFU_DOCS + USB_OTG_CONSOLE_DOCS
@@ -215,10 +216,10 @@
 ESP32S3_DOCS = ['hw-reference/esp32s3/**',
                 'api-reference/system/ipc.rst',
                 'api-guides/flash_psram_config.rst',
-                'api-reference/peripherals/touch_pad.rst',
+                'api-reference/peripherals/cap_touch_sens.rst',
                 'api-reference/peripherals/sd_pullup_requirements.rst',
                 'api-guides/RF_calibration.rst',
-                'api-guides/phy.rst'] + USB_OTG_DFU_DOCS + USB_OTG_CONSOLE_DOCS
+                'api-guides/phy.rst'] + USB_OTG_DFU_DOCS + USB_OTG_CONSOLE_DOCS + QEMU_DOCS
 
 # No JTAG docs for this one as it gets gated on SOC_USB_SERIAL_JTAG_SUPPORTED down below.
 ESP32C3_DOCS = ['hw-reference/esp32c3/**',
@@ -379,6 +380,9 @@
 
 idf_build_system = {'doxygen_component_info': True, 'component_info_ignore_file': Path(os.environ['IDF_PATH']) / 'docs' / 'component_info_ignore_file.txt'}
 
+# Please update following list to enable Qemu doc guide (and cross references) for a new target
+QEMU_TARGETS = ['esp32', 'esp32c3', 'esp32s3']
+
 
 # Callback function for user setup that needs be done after `config-init`-event
 # config.idf_target is not available at the initial config stage
@@ -386,6 +390,10 @@ def conf_setup(app, config):
     config.add_warnings_content = 'This document is not updated for {} yet, so some of the content may not be correct.'.format(config.idf_target.upper())
 
     add_warnings_file = '{}/../docs_not_updated/{}.txt'.format(app.confdir, config.idf_target)
+
+    if config.idf_target in QEMU_TARGETS:
+        app.tags.add('TARGET_SUPPORT_QEMU')
+
     try:
         with open(add_warnings_file) as warning_file:
             config.add_warnings_pages = warning_file.read().splitlines()
diff --git a/docs/docs_not_updated/esp32c5.txt b/docs/docs_not_updated/esp32c5.txt
index 78e9f9ee899..7a8cf3a65db 100644
--- a/docs/docs_not_updated/esp32c5.txt
+++ b/docs/docs_not_updated/esp32c5.txt
@@ -1,19 +1,12 @@
 api-guides/low-power-mode.rst
 api-guides/RF_calibration.rst
 api-guides/deep-sleep-stub.rst
-api-guides/blufi.rst
 api-guides/coexist.rst
 api-guides/wifi.rst
-api-guides/bluetooth.rst
 api-guides/wireshark-user-guide.rst
 api-guides/esp-wifi-mesh.rst
 api-guides/inc/external-ram-esp32-notes.rst
 api-guides/current-consumption-measurement-modules.rst
-api-guides/esp-ble-mesh/ble-mesh-index.rst
-api-guides/esp-ble-mesh/ble-mesh-feature-list.rst
-api-guides/esp-ble-mesh/ble-mesh-terminology.rst
-api-guides/esp-ble-mesh/ble-mesh-architecture.rst
-api-guides/esp-ble-mesh/ble-mesh-faq.rst
 api-guides/wifi-security.rst
 api-guides/openthread.rst
 api-reference/template.rst
@@ -57,32 +50,6 @@ api-reference/system/async_memcpy.rst
 api-reference/system/power_management.rst
 api-reference/system/inc/power_management_esp32c5.rst
 api-reference/system/mm.rst
-api-reference/bluetooth/esp_spp.rst
-api-reference/bluetooth/esp_l2cap_bt.rst
-api-reference/bluetooth/esp_hidd.rst
-api-reference/bluetooth/esp_avrc.rst
-api-reference/bluetooth/controller_vhci.rst
-api-reference/bluetooth/esp_bt_defs.rst
-api-reference/bluetooth/esp_hf_ag.rst
-api-reference/bluetooth/esp_bt_main.rst
-api-reference/bluetooth/esp_bt_device.rst
-api-reference/bluetooth/esp_hidh.rst
-api-reference/bluetooth/esp_gatts.rst
-api-reference/bluetooth/esp_gattc.rst
-api-reference/bluetooth/esp_sdp.rst
-api-reference/bluetooth/bt_common.rst
-api-reference/bluetooth/nimble/index.rst
-api-reference/bluetooth/esp_hf_client.rst
-api-reference/bluetooth/esp_a2dp.rst
-api-reference/bluetooth/esp_blufi.rst
-api-reference/bluetooth/bt_le.rst
-api-reference/bluetooth/esp_hf_defs.rst
-api-reference/bluetooth/esp_gap_bt.rst
-api-reference/bluetooth/esp_gatt_defs.rst
-api-reference/bluetooth/esp-ble-mesh.rst
-api-reference/bluetooth/index.rst
-api-reference/bluetooth/esp_gap_ble.rst
-api-reference/bluetooth/classic_bt.rst
 api-reference/index.rst
 api-reference/protocols/esp_serial_slave_link.rst
 api-reference/protocols/esp_crt_bundle.rst
diff --git a/docs/docs_not_updated/esp32c61.txt b/docs/docs_not_updated/esp32c61.txt
index 444a1b4d36c..7458f86219a 100644
--- a/docs/docs_not_updated/esp32c61.txt
+++ b/docs/docs_not_updated/esp32c61.txt
@@ -1,4 +1,3 @@
-api-guides/core_dump_internals.rst
 api-guides/performance/speed.rst
 api-guides/performance/size.rst
 api-guides/performance/ram-usage.rst
@@ -8,23 +7,16 @@ api-guides/app_trace.rst
 api-guides/low-power-mode.rst
 api-guides/RF_calibration.rst
 api-guides/deep-sleep-stub.rst
-api-guides/blufi.rst
 api-guides/lwip.rst
 api-guides/coexist.rst
 api-guides/wifi.rst
 api-guides/usb-otg-console.rst
-api-guides/bluetooth.rst
 api-guides/wireshark-user-guide.rst
 api-guides/esp-wifi-mesh.rst
 api-guides/core_dump.rst
 api-guides/inc/external-ram-esp32-notes.rst
 api-guides/dfu.rst
 api-guides/current-consumption-measurement-modules.rst
-api-guides/esp-ble-mesh/ble-mesh-index.rst
-api-guides/esp-ble-mesh/ble-mesh-feature-list.rst
-api-guides/esp-ble-mesh/ble-mesh-terminology.rst
-api-guides/esp-ble-mesh/ble-mesh-architecture.rst
-api-guides/esp-ble-mesh/ble-mesh-faq.rst
 api-guides/wifi-security.rst
 api-guides/index.rst
 api-guides/openthread.rst
@@ -42,10 +34,7 @@ api-reference/storage/mass_mfg.rst
 api-reference/storage/fatfsgen.rst
 api-reference/storage/index.rst
 api-reference/storage/nvs_partition_parse.rst
-api-reference/peripherals/sdspi_share.rst
 api-reference/peripherals/isp.rst
-api-reference/peripherals/adc_continuous.rst
-api-reference/peripherals/adc_oneshot.rst
 api-reference/peripherals/usb_host.rst
 api-reference/peripherals/usb_host/usb_host_notes_arch.rst
 api-reference/peripherals/usb_host/usb_host_notes_index.rst
@@ -53,10 +42,7 @@ api-reference/peripherals/usb_host/usb_host_notes_dwc_otg.rst
 api-reference/peripherals/usb_host/usb_host_notes_usbh.rst
 api-reference/peripherals/usb_host/usb_host_notes_design.rst
 api-reference/peripherals/usb_device.rst
-api-reference/peripherals/sdspi_host.rst
 api-reference/peripherals/dac.rst
-api-reference/peripherals/etm.rst
-api-reference/peripherals/i2s.rst
 api-reference/peripherals/touch_element.rst
 api-reference/peripherals/ppa.rst
 api-reference/peripherals/ana_cmpr.rst
@@ -132,32 +118,6 @@ api-reference/system/inc/power_management_esp32c2.rst
 api-reference/system/inc/show-efuse-table_ESP32-S2.rst
 api-reference/system/mm.rst
 api-reference/system/index.rst
-api-reference/bluetooth/esp_spp.rst
-api-reference/bluetooth/esp_l2cap_bt.rst
-api-reference/bluetooth/esp_hidd.rst
-api-reference/bluetooth/esp_avrc.rst
-api-reference/bluetooth/controller_vhci.rst
-api-reference/bluetooth/esp_bt_defs.rst
-api-reference/bluetooth/esp_hf_ag.rst
-api-reference/bluetooth/esp_bt_main.rst
-api-reference/bluetooth/esp_bt_device.rst
-api-reference/bluetooth/esp_hidh.rst
-api-reference/bluetooth/esp_gatts.rst
-api-reference/bluetooth/esp_gattc.rst
-api-reference/bluetooth/esp_sdp.rst
-api-reference/bluetooth/bt_common.rst
-api-reference/bluetooth/nimble/index.rst
-api-reference/bluetooth/esp_hf_client.rst
-api-reference/bluetooth/esp_a2dp.rst
-api-reference/bluetooth/esp_blufi.rst
-api-reference/bluetooth/bt_le.rst
-api-reference/bluetooth/esp_hf_defs.rst
-api-reference/bluetooth/esp_gap_bt.rst
-api-reference/bluetooth/esp_gatt_defs.rst
-api-reference/bluetooth/esp-ble-mesh.rst
-api-reference/bluetooth/index.rst
-api-reference/bluetooth/esp_gap_ble.rst
-api-reference/bluetooth/classic_bt.rst
 api-reference/error-codes.rst
 api-reference/index.rst
 api-reference/protocols/icmp_echo.rst
diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt
index e11054ce4e5..fff012c1189 100644
--- a/docs/docs_not_updated/esp32p4.txt
+++ b/docs/docs_not_updated/esp32p4.txt
@@ -6,10 +6,6 @@ api-guides/usb-otg-console.rst
 api-guides/esp-wifi-mesh.rst
 api-guides/dfu.rst
 api-guides/wifi-security.rst
-api-reference/peripherals/adc_continuous.rst
-api-reference/peripherals/adc_oneshot.rst
-api-reference/peripherals/touch_element.rst
-api-reference/peripherals/touch_pad.rst
 api-reference/peripherals/adc_calibration.rst
 api-reference/peripherals/parlio.rst
 api-reference/peripherals/sd_pullup_requirements.rst
diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile
index 8a131eddecc..1916b68d9fc 100644
--- a/docs/doxygen/Doxyfile
+++ b/docs/doxygen/Doxyfile
@@ -29,6 +29,7 @@ INPUT = \
     $(PROJECT_PATH)/components/bootloader_support/include/esp_flash_encrypt.h \
     $(PROJECT_PATH)/components/esp_coex/include/esp_coexist.h \
     $(PROJECT_PATH)/components/bt/common/api/include/api/esp_blufi_api.h \
+    $(PROJECT_PATH)/components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_ble_api.h \
     $(PROJECT_PATH)/components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_common_api.h \
     $(PROJECT_PATH)/components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_local_data_operation_api.h \
     $(PROJECT_PATH)/components/bt/esp_ble_mesh/api/core/include/esp_ble_mesh_low_power_api.h \
@@ -212,10 +213,12 @@ INPUT = \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_mesh.h \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_now.h \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_smartconfig.h \
+    $(PROJECT_PATH)/components/esp_wifi/include/local/esp_wifi_types_native.h \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_ap_get_sta_list.h \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_crypto_types.h \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_default.h \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_netif.h \
+    $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_types_generic.h \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi_types.h \
     $(PROJECT_PATH)/components/esp_wifi/include/esp_wifi.h \
     $(PROJECT_PATH)/components/wpa_supplicant/esp_supplicant/include/esp_mbo.h  \
@@ -259,7 +262,6 @@ INPUT = \
     $(PROJECT_PATH)/components/hal/include/hal/spi_types.h \
     $(PROJECT_PATH)/components/hal/include/hal/temperature_sensor_types.h \
     $(PROJECT_PATH)/components/hal/include/hal/timer_types.h \
-    $(PROJECT_PATH)/components/hal/include/hal/touch_sensor_types.h \
     $(PROJECT_PATH)/components/hal/include/hal/twai_types.h \
     $(PROJECT_PATH)/components/hal/include/hal/uart_types.h \
     $(PROJECT_PATH)/components/hal/include/hal/efuse_hal.h \
@@ -314,6 +316,7 @@ INPUT = \
     $(PROJECT_PATH)/components/vfs/include/esp_vfs_eventfd.h \
     $(PROJECT_PATH)/components/vfs/include/esp_vfs_semihost.h \
     $(PROJECT_PATH)/components/vfs/include/esp_vfs_null.h \
+    $(PROJECT_PATH)/components/vfs/include/esp_vfs_ops.h \
     $(PROJECT_PATH)/components/vfs/include/esp_vfs.h \
     $(PROJECT_PATH)/components/wear_levelling/include/wear_levelling.h \
     $(PROJECT_PATH)/components/wifi_provisioning/include/wifi_provisioning/manager.h \
diff --git a/docs/doxygen/Doxyfile_esp32 b/docs/doxygen/Doxyfile_esp32
index 1b098c71ccd..cc46952c97c 100644
--- a/docs/doxygen/Doxyfile_esp32
+++ b/docs/doxygen/Doxyfile_esp32
@@ -1,5 +1,6 @@
 INPUT += \
          $(PROJECT_PATH)/components/driver/touch_sensor/$(IDF_TARGET)/include/driver/touch_sensor.h \
+		 $(PROJECT_PATH)/components/hal/include/hal/touch_sensor_legacy_types.h \
          $(PROJECT_PATH)/components/esp_psram/include/esp32/himem.h \
          $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/dac_channel.h \
          $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/rtc_io_channel.h \
diff --git a/docs/doxygen/Doxyfile_esp32p4 b/docs/doxygen/Doxyfile_esp32p4
index 4f53c338f09..3bea406c983 100644
--- a/docs/doxygen/Doxyfile_esp32p4
+++ b/docs/doxygen/Doxyfile_esp32p4
@@ -44,5 +44,6 @@ INPUT += \
     $(PROJECT_PATH)/components/esp_driver_jpeg/include/driver/jpeg_encode.h \
     $(PROJECT_PATH)/components/esp_driver_ppa/include/driver/ppa.h \
     $(PROJECT_PATH)/components/esp_lcd/dsi/include/esp_lcd_mipi_dsi.h \
+    $(PROJECT_PATH)/components/esp_lcd/rgb/include/esp_lcd_panel_rgb.h \
     $(PROJECT_PATH)/components/sdmmc/include/sd_pwr_ctrl.h \
     $(PROJECT_PATH)/components/sdmmc/include/sd_pwr_ctrl_by_on_chip_ldo.h \
diff --git a/docs/doxygen/Doxyfile_esp32s2 b/docs/doxygen/Doxyfile_esp32s2
index 1601d5562d1..c212f7d4dba 100644
--- a/docs/doxygen/Doxyfile_esp32s2
+++ b/docs/doxygen/Doxyfile_esp32s2
@@ -1,8 +1,9 @@
 INPUT += \
-         $(PROJECT_PATH)/components/driver/touch_sensor/$(IDF_TARGET)/include/driver/touch_sensor.h \
+         $(PROJECT_PATH)/components/esp_driver_touch_sens/include/driver/touch_sens.h \
+		 $(PROJECT_PATH)/components/esp_driver_touch_sens/include/driver/touch_sens_types.h \
+		 $(PROJECT_PATH)/components/esp_driver_touch_sens/hw_ver2/include/driver/touch_version_types.h \
          $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/dac_channel.h \
          $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/rtc_io_channel.h \
-         $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/touch_sensor_channel.h \
          $(PROJECT_PATH)/components/ulp/ulp_fsm/include/$(IDF_TARGET)/ulp.h \
          $(PROJECT_PATH)/components/touch_element/include/touch_element/touch_button.h \
          $(PROJECT_PATH)/components/touch_element/include/touch_element/touch_element.h \
diff --git a/docs/doxygen/Doxyfile_esp32s3 b/docs/doxygen/Doxyfile_esp32s3
index f16dad3a422..20235266c32 100644
--- a/docs/doxygen/Doxyfile_esp32s3
+++ b/docs/doxygen/Doxyfile_esp32s3
@@ -1,7 +1,8 @@
 INPUT += \
-         $(PROJECT_PATH)/components/driver/touch_sensor/$(IDF_TARGET)/include/driver/touch_sensor.h \
+         $(PROJECT_PATH)/components/esp_driver_touch_sens/include/driver/touch_sens.h \
+		 $(PROJECT_PATH)/components/esp_driver_touch_sens/include/driver/touch_sens_types.h \
+		 $(PROJECT_PATH)/components/esp_driver_touch_sens/hw_ver2/include/driver/touch_version_types.h \
          $(PROJECT_PATH)/components/esp_lcd/rgb/include/esp_lcd_panel_rgb.h \
-         $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/touch_sensor_channel.h \
          $(PROJECT_PATH)/components/ulp/ulp_fsm/include/$(IDF_TARGET)/ulp.h \
          $(PROJECT_PATH)/components/touch_element/include/touch_element/touch_button.h \
          $(PROJECT_PATH)/components/touch_element/include/touch_element/touch_element.h \
diff --git a/docs/en/api-guides/ble/ble-feature-support-status.rst b/docs/en/api-guides/ble/ble-feature-support-status.rst
index 01a7aa5b3cc..a750483ad3f 100644
--- a/docs/en/api-guides/ble/ble-feature-support-status.rst
+++ b/docs/en/api-guides/ble/ble-feature-support-status.rst
@@ -162,7 +162,7 @@ If none of our chip series meet your needs, please contact `customer support tea
       - |experimental|
       - |experimental|
     * -
-      - Advertising Channel Index
+      - Randomized Advertising Channel Indexing
       - |unsupported|
       - |NA|
       - |NA|
@@ -171,19 +171,19 @@ If none of our chip series meet your needs, please contact `customer support tea
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61
 
             |experimental|
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61
 
             |experimental|
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61
 
             |experimental|
     * - .. centered:: |5.2|
@@ -201,14 +201,14 @@ If none of our chip series meet your needs, please contact `customer support tea
       - .. only:: esp32 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 or esp32c61
 
             |experimental|
       - |unsupported|
       - .. only:: esp32 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 or esp31c61
 
             |experimental|
     * - .. centered:: |5.3|
@@ -216,31 +216,31 @@ If none of our chip series meet your needs, please contact `customer support tea
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |supported|
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
            |supported|
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |supported|
     * -
       - LE Enhanced Connection Update (Connection Subrating)
-      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5
+      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |unsupported|
         .. only:: esp32c3 or esp32s3
 
             |experimental|
       - |unsupported|
-      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5
+      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |unsupported|
         .. only:: esp32c3 or esp32s3
@@ -251,31 +251,31 @@ If none of our chip series meet your needs, please contact `customer support tea
       - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61
 
             |experimental|
       - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61
 
             |experimental|
       - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61
 
             |experimental|
     * - .. centered:: |5.4|
       - Advertising Coding Selection
-      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5
+      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |unsupported|
         .. only:: esp32c3 or esp32s3
 
             |experimental|
       - |unsupported|
-      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5
+      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp31c61
 
             |unsupported|
         .. only:: esp32c3 or esp32s3
diff --git a/docs/en/api-guides/ble/get-started/ble-connection.rst b/docs/en/api-guides/ble/get-started/ble-connection.rst
index baeb7eedbed..54a7ad64c7b 100644
--- a/docs/en/api-guides/ble/get-started/ble-connection.rst
+++ b/docs/en/api-guides/ble/get-started/ble-connection.rst
@@ -1 +1,477 @@
-.. include:: ../../../../zh_CN/api-guides/ble/get-started/ble-connection.rst
+Connection
+===================
+
+:link_to_translation:`zh_CN:[中文]`
+
+This document is the third tutorial in the Getting Started series on Bluetooth Low Energy (Bluetooth LE), aiming to provide a brief overview of the connection process. Subsequently, the tutorial introduces the code implementation of peripheral devices using the :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` example based on the NimBLE host layer stack.
+
+
+Learning Objectives
+----------------------------------
+
+- Understand the basic concepts of connection
+- Learn about connection-related parameters
+- Explore the code structure of the :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` example
+
+
+Basic Concepts
+---------------------------------
+
+
+Initiating a Connection
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+*With the introduction of extended advertising features in Bluetooth LE 5.0, there are slight differences in the connection establishment process between Legacy ADV and Extended ADV. Below, we take the Legacy ADV connection establishment process as an example.*
+
+When a scanner receives an advertising packet on a specific advertising channel, if the advertiser is connectable, the scanner can send a connection request on the same advertising channel. The advertiser can set a *Filter Accept List* to filter out untrusted devices or accept connection requests from any scanner. Afterward, the advertiser becomes the peripheral device, and the scanner becomes the central device, allowing for bidirectional communication over the data channel.
+
+As described in the section :ref:`Scan Requests and Scan Responses <scan_request_and_scan_response>`, after each advertising period on a channel, the advertiser briefly enters RX mode to receive possible scan requests. In fact, this RX phase can also accept connection requests. Thus, for the scanner, the time window for sending a connection request is similar to that for sending a scan request.
+
+.. figure:: ../../../../_static/ble/ble-advertiser-rx-connection-request.png
+    :align: center
+    :scale: 30%
+    :alt: Initiating a Connection
+
+    Initiating a Connection
+
+
+Connection Interval and Connection Event
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+During a connection, the central and peripheral devices periodically exchange data, with this data exchange cycle referred to as the Connection Interval. The connection interval is one of the connection parameters determined during the initial connection request and can be modified afterward. The step size for the connection interval is 1.25 ms, with a range from 7.5 ms (6 steps) to 4.0 s (3200 steps).
+
+A single data exchange process is termed Connection Event. During a connection event, there can be one or more data packet exchanges (when the data volume is large, it may need to be fragmented). In a data packet exchange, the central device first sends a packet to the peripheral device, followed by a packet from the peripheral device back to the central device. Even if either party does not need to send data at the start of a connection interval, it must send an empty packet to maintain the connection.
+
+The timing relationship between the connection interval and connection event can be referenced in the diagram below.
+
+.. figure:: ../../../../_static/ble/ble-connection-event-and-connection-interval.png
+    :align: center
+    :scale: 30%
+    :alt: Connection Interval and Connection Event
+
+    Connection Interval and Connection Event
+
+It's worth noting that if a connection event requires sending a large amount of data, causing the duration of the connection event to exceed the connection interval, the connection event must be split into multiple events. This means that if there isn't enough remaining time in the connection interval to complete the next packet exchange, the next packet exchange must wait until the next connection interval begins.
+
+When the required data exchange frequency is low, a longer connection interval can be set; during the connection interval, the device can sleep outside of connection events to reduce power consumption.
+
+
+Connection Parameters
+------------------------------
+
+As mentioned earlier, the connection interval is a connection parameter whose initial value is given by the central device in the connection request and can be modified in subsequent connections. In addition to the connection interval, there are many other important connection parameters. Below, we will explain some of these key parameters.
+
+
+Supervision Timeout
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Supervision Timeout defines the maximum time allowed between two successful connection events. If a successful connection event is followed by a period longer than the supervision timeout without another successful connection event, the connection is considered to be disconnected. This parameter is critical for maintaining connection status; for example, if one party unexpectedly loses power or moves out of range, the other party can determine whether to disconnect to conserve communication resources by checking for a timeout.
+
+
+Peripheral Latency
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Peripheral Latency specifies the maximum number of connection events that the peripheral device can skip when there is no data to send.
+
+To understand the purpose of this parameter, consider a Bluetooth mouse as an example. When a user is typing on a keyboard, the mouse may not have any data to send, so it’s preferable to reduce the frequency of data packet transmissions to save power. Conversely, during mouse usage, we want the mouse to send data as quickly as possible to minimize latency. This means that the data transmission from the Bluetooth mouse is intermittently high-frequency. If we rely solely on the connection interval for adjustments, a lower connection interval would lead to high energy consumption, while a higher connection interval would result in high latency.
+
+In this scenario, the peripheral latency mechanism is a perfect solution. To reduce the latency of a Bluetooth mouse, we can set a smaller connection interval, such as 10 ms, which allows a data exchange frequency of up to 100 Hz during intensive use. We can then set the peripheral latency to 100, allowing the mouse to effectively reduce the data exchange frequency to 1 Hz when idle. This design achieves variable data exchange frequency without adjusting connection parameters, maximizing user experience.
+
+
+Maximum Transmission Unit
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The Maximum Transmission Unit (MTU) refers to the maximum byte size of a single ATT data packet. Before discussing the MTU parameter, it's essential to describe the structure of the Data Channel Packet.
+
+The structure of the Data Channel Packet is similar to that of the :ref:`Advertising Packet <adv_packet_structure>`, with differences in the PDU structure. The data PDU can be divided into three parts:
+
+.. list-table::
+    :align: center
+    :widths: 10 30 20 40
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+        -   Byte Size
+        -   Notes
+    *   -   1
+        -   Header
+        -   2
+        -
+    *   -   2
+        -   Payload
+        -   0-27 / 0-251
+        -   Before Bluetooth LE 4.2, the maximum payload was 27 bytes; Bluetooth LE 4.2 introduced Data Length Extension (DLE), allowing a maximum payload of 251 bytes.
+    *   -   3
+        -   Message Integrity Check, MIC
+        -   4
+        -   Optional
+
+The payload of the data PDU can be further divided into:
+
+.. list-table::
+    :align: center
+    :widths: 10 70 20
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+        -   Byte Size
+    *   -   1
+        -   L2CAP Header
+        -   4
+    *   -   2
+        -   ATT Header + ATT Data
+        -   0-23 / 0-247
+
+The default MTU value is 23 bytes, which matches the maximum ATT data byte size that can be carried in a single data PDU before Bluetooth LE 4.2.
+
+MTU can be set to larger values, such as 140 bytes. Before Bluetooth LE 4.2, with a maximum of 23 bytes carrying ATT data in the payload, a complete ATT data packet would need to be split across multiple data PDUs. After Bluetooth LE 4.2, a single data PDU can carry up to 247 bytes of ATT data, so an MTU of 140 bytes can still be accommodated in a single data PDU.
+
+
+Hands-On Practice
+--------------------------
+
+Having understood the concepts related to connections, let’s move on to the :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` example code to learn how to build a simple peripheral device using the NimBLE stack.
+
+
+Prerequisites
+^^^^^^^^^^^^^^^^^^^^
+
+1. An {IDF_TARGET_NAME} development board
+2. ESP-IDF development environment
+3. The **nRF Connect for Mobile** app installed on your phone
+
+If you have not yet completed the ESP-IDF development environment setup, please refer to :doc:`IDF Get Started <../../../get-started/index>`.
+
+
+Try It Out
+^^^^^^^^^^^^^^^^^^^^^^
+
+
+Building and Flashing
+##########################
+
+
+The reference example for this tutorial is :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>`.
+
+You can navigate to the example directory using the following command:
+
+.. code-block:: shell
+
+    $ cd <ESP-IDF Path>/examples/bluetooth/ble_get_started/nimble/NimBLE_Connection
+
+Please replace `<ESP-IDF Path>` with your local ESP-IDF folder path. Then, you can open the NimBLE_Connection project using VSCode or another IDE you prefer. For example, after navigating to the example directory via the command line, you can open the project in VSCode using the following command:
+
+.. code-block:: shell
+
+    $ code .
+
+Next, enter the ESP-IDF environment in the command line and set the target chip:
+
+.. code-block:: shell
+
+    $ idf.py set-target <chip-name>
+
+You should see messages like:
+
+.. code-block:: shell
+
+    ...
+    -- Configuring done
+    -- Generating done
+    -- Build files have been written to ...
+
+These messages indicate that the chip has been successfully configured. Then, connect the development board to your computer and run the following command to build the firmware, flash it to the board, and monitor the serial output from the {IDF_TARGET_NAME} development board:
+
+.. code-block:: shell
+
+    $ idf.py flash monitor
+
+You should see messages like:
+
+.. code-block:: shell
+
+    ...
+    main_task: Returned from app_main()
+
+Wait until the notification ends.
+
+
+Connect and Disconnect
+############################
+
+Open the **nRF Connect for Mobile** app on your phone, pull down to refresh in the **SCANNER** tab, and locate the NimBLE_CONN device as shown in the image below.
+
+.. figure:: ../../../../_static/ble/ble-connection-device-list.jpg
+    :align: center
+    :scale: 30%
+
+    Locate NimBLE_CONN Device
+
+If the device list is long, it's recommended to filter by the keyword "NimBLE" to quickly find the NimBLE_CONN device.
+
+Compared to :ref:`NimBLE_Beacon <nimble_beacon_details>`, you can observe that most of the advertising data is consistent, but there is an additional Advertising Interval data with a value of 500 ms. Below the **CONNECT** button, you should also see that the advertising interval is around 510 ms.
+
+Click the **CONNECT** button to connect to the device, and you should be able to see the GAP service on your phone as shown below.
+
+.. figure:: ../../../../_static/ble/ble-connection-connected.jpg
+    :align: center
+    :scale: 30%
+
+    Connected to NimBLE_CONN Device
+
+At this point, you should also see the LED on the development board light up. Click **DISCONNECT** to disconnect from the device, and the LED on the development board should turn off.
+
+If your development board does not have any other LEDs except the one for the power indicator, you should be able to observe the corresponding status indicators in the log output.
+
+
+Viewing Log Output
+##########################
+
+When connected to the device, you should see logs similar to the following:
+
+.. code-block::
+
+    I (36367) NimBLE_Connection: connection established; status=0
+    I (36367) NimBLE_Connection: connection handle: 0
+    I (36367) NimBLE_Connection: device id address: type=0, value=CE:4E:F7:F9:55:60
+    I (36377) NimBLE_Connection: peer id address: type=1, value=7F:BE:AD:66:6F:45
+    I (36377) NimBLE_Connection: conn_itvl=36, conn_latency=0, supervision_timeout=500, encrypted=0, authenticated=0, bonded=0
+
+    I (36397) NimBLE: GAP procedure initiated:
+    I (36397) NimBLE: connection parameter update; conn_handle=0 itvl_min=36 itvl_max=36 latency=3 supervision_timeout=500 min_ce_len=0 max_ce_len=0
+    I (36407) NimBLE:
+
+    I (37007) NimBLE_Connection: connection updated; status=0
+    I (37007) NimBLE_Connection: connection handle: 0
+    I (37007) NimBLE_Connection: device id address: type=0, value=CE:4E:F7:F9:55:60
+    I (37007) NimBLE_Connection: peer id address: type=1, value=7F:BE:AD:66:6F:45
+    I (37017) NimBLE_Connection: conn_itvl=36, conn_latency=3, supervision_timeout=500, encrypted=0, authenticated=0, bonded=0
+
+The first part of the log shows the connection information output by the device when the connection is established, including the connection handle, the Bluetooth addresses of both the device and the mobile phone, as well as the connection parameters. Here, `conn_itvl` refers to the connection interval, `conn_latency` indicates the peripheral latency, and `supervision_timeout` is the connection timeout parameter. Other parameters can be temporarily ignored.
+
+The second part indicates that the device initiated an update to the connection parameters, requesting to set the peripheral latency to 3.
+
+The third part of the log displays the connection information after the update, showing that the peripheral latency has been successfully updated to 3, while other connection parameters remain unchanged.
+
+When the device disconnects, you should see logs similar to the following:
+
+.. code-block::
+
+    I (63647) NimBLE_Connection: disconnected from peer; reason=531
+    I (63647) NimBLE: GAP procedure initiated: advertise;
+    I (63647) NimBLE: disc_mode=2
+    I (63647) NimBLE:  adv_channel_map=0 own_addr_type=0 adv_filter_policy=0 adv_itvl_min=800 adv_itvl_max=801
+    I (63657) NimBLE:
+
+    I (63657) NimBLE_Connection: advertising started!
+
+You can observe that the device outputs the reason for disconnection when the connection is terminated, and then it initiates advertising again.
+
+
+Code Details
+------------------------------
+
+
+Project Structure Overview
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _nimble_connection_project_structure:
+
+The root directory structure of :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` is identical to that of :ref:`NimBLE_Beacon <nimble_beacon_project_structure>`. However, after building the firmware, you may notice an additional `managed_components` directory in the root, which contains dependencies automatically included during firmware construction; in this case, it's the `led_strip` component used to control the development board's LED. This dependency is referenced in the `main/idf_component.yml` file.
+
+Additionally, LED control-related source code has been introduced in the `main` folder.
+
+
+Program Behavior Overview
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _nimble_connection_program_behavior:
+
+The behavior of this example is mostly consistent with that of :ref:`NimBLE_Beacon <nimble_beacon_program_behavior>`, with the key difference being that this example can accept scan requests from scanners and enter a connected state after entering advertising mode. Furthermore, it utilizes a callback function, `gap_event_handler`, to handle connection events and respond accordingly, such as turning on the LED when a connection is established and turning it off when the connection is terminated.
+
+Entry Function
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+
+.. _nimble_connection_entry_point:
+
+The entry function of this example is nearly the same as that of :ref:`NimBLE_Beacon <nimble_beacon_entry_point>`, except that before initializing NVS Flash, we call the `led_init` function to initialize the LED.
+
+
+Starting Advertising
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The process for initiating advertising is largely similar to that of :ref:`NimBLE_Beacon <nimble_beacon_start_advertising>`, but there are some details to note.
+
+First, we've added the advertising interval parameter in the scan response. We want to set the advertising interval to 500 ms, and since the unit for the advertising interval is 0.625 ms, we need to set it to `0x320`. However, NimBLE provides a unit conversion macro `BLE_GAP_ADV_ITVL_MS`, which allows us to avoid manual calculations, as shown below:
+
+.. code-block:: C
+
+    static void start_advertising(void) {
+        ...
+
+        /* Set advertising interval */
+        rsp_fields.adv_itvl = BLE_GAP_ADV_ITVL_MS(500);
+        rsp_fields.adv_itvl_is_present = 1;
+
+        ...
+    }
+
+Next, we want the device to be connectable, so we need to modify the advertising mode from non-connectable to connectable. Additionally, the advertising interval parameter set in the scan response serves only to inform other devices and does not affect the actual advertising interval. This parameter must be set in the advertising parameter structure to take effect. Here, we set the minimum and maximum values of the advertising interval to 500 ms and 510 ms, respectively. Finally, we want to handle GAP events using the callback function `gap_event_handler`, so we pass this callback to the API `ble_gap_adv_start` that starts advertising. The relevant code is as follows:
+
+.. code-block:: C
+
+    static void start_advertising(void) {
+        ...
+
+        /* Set non-connetable and general discoverable mode to be a beacon */
+        adv_params.conn_mode = BLE_GAP_CONN_MODE_UND;
+        adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
+
+        /* Set advertising interval */
+        adv_params.itvl_min = BLE_GAP_ADV_ITVL_MS(500);
+        adv_params.itvl_max = BLE_GAP_ADV_ITVL_MS(510);
+
+        /* Start advertising */
+        rc = ble_gap_adv_start(own_addr_type, NULL, BLE_HS_FOREVER, &adv_params,
+                            gap_event_handler, NULL);
+        if (rc != 0) {
+            ESP_LOGE(TAG, "failed to start advertising, error code: %d", rc);
+            return;
+        }
+        ESP_LOGI(TAG, "advertising started!");
+
+        ...
+    }
+
+When the return value of `ble_gap_adv_start` is 0, it indicates that the device has successfully initiated advertising. Subsequently, the NimBLE protocol stack will call the `gap_event_handler` callback function whenever a GAP event is triggered, passing the corresponding GAP event.
+
+GAP Event Handling
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+In this example, we handle three different types of GAP events:
+
+- Connection Event `BLE_GAP_EVENT_CONNECT`
+- Disconnection Event `BLE_GAP_EVENT_DISCONNECT`
+- Connection Update Event `BLE_GAP_EVENT_CONN_UPDATE`
+
+
+The connection event is triggered when a connection is successfully established or when a connection attempt fails. If the connection fails, we will restart advertising. If the connection is successful, we will log the connection information, turn on the LED, and initiate a connection parameter update to set the peripheral latency parameter to 3. Here’s how the code looks:
+
+.. code-block:: C
+
+    static int gap_event_handler(struct ble_gap_event *event, void *arg) {
+        /* Local variables */
+        int rc = 0;
+        struct ble_gap_conn_desc desc;
+
+        /* Handle different GAP event */
+        switch (event->type) {
+
+        /* Connect event */
+        case BLE_GAP_EVENT_CONNECT:
+            /* A new connection was established or a connection attempt failed. */
+            ESP_LOGI(TAG, "connection %s; status=%d",
+                    event->connect.status == 0 ? "established" : "failed",
+                    event->connect.status);
+
+            /* Connection succeeded */
+            if (event->connect.status == 0) {
+                /* Check connection handle */
+                rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
+                if (rc != 0) {
+                    ESP_LOGE(TAG,
+                            "failed to find connection by handle, error code: %d",
+                            rc);
+                    return rc;
+                }
+
+                /* Print connection descriptor and turn on the LED */
+                print_conn_desc(&desc);
+                led_on();
+
+                /* Try to update connection parameters */
+                struct ble_gap_upd_params params = {.itvl_min = desc.conn_itvl,
+                                                    .itvl_max = desc.conn_itvl,
+                                                    .latency = 3,
+                                                    .supervision_timeout =
+                                                        desc.supervision_timeout};
+                rc = ble_gap_update_params(event->connect.conn_handle, &params);
+                if (rc != 0) {
+                    ESP_LOGE(
+                        TAG,
+                        "failed to update connection parameters, error code: %d",
+                        rc);
+                    return rc;
+                }
+            }
+            /* Connection failed, restart advertising */
+            else {
+                start_advertising();
+            }
+            return rc;
+
+        ...
+        }
+
+        return rc;
+    }
+
+The disconnection event is triggered when either party disconnects from the connection. At this point, we log the reason for the disconnection, turn off the LED, and restart advertising. Here’s the code:
+
+.. code-block:: C
+
+    static int gap_event_handler(struct ble_gap_event *event, void *arg) {
+        ...
+
+        /* Disconnect event */
+        case BLE_GAP_EVENT_DISCONNECT:
+            /* A connection was terminated, print connection descriptor */
+            ESP_LOGI(TAG, "disconnected from peer; reason=%d",
+                    event->disconnect.reason);
+
+            /* Turn off the LED */
+            led_off();
+
+            /* Restart advertising */
+            start_advertising();
+            return rc;
+
+        ...
+    }
+
+The connection update event is triggered when the connection parameters are updated. At this point, we log the updated connection information. Here’s the code:
+
+.. code-block:: C
+
+    static int gap_event_handler(struct ble_gap_event *event, void *arg) {
+        ...
+
+        /* Connection parameters update event */
+        case BLE_GAP_EVENT_CONN_UPDATE:
+            /* The central has updated the connection parameters. */
+            ESP_LOGI(TAG, "connection updated; status=%d",
+                    event->conn_update.status);
+
+            /* Print connection descriptor */
+            rc = ble_gap_conn_find(event->conn_update.conn_handle, &desc);
+            if (rc != 0) {
+                ESP_LOGE(TAG, "failed to find connection by handle, error code: %d",
+                        rc);
+                return rc;
+            }
+            print_conn_desc(&desc);
+            return rc;
+
+        ...
+    }
+
+
+Summary
+----------------------
+
+Through this tutorial, you have learned the basic concepts of connections and how to use the NimBLE host stack to build a Bluetooth LE peripheral device using the :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` example.
+
+You can try to modify parameters in the example and observe the results in the log output. For instance, you can change the peripheral latency or connection timeout parameters to see if the modifications trigger connection update events.
diff --git a/docs/en/api-guides/ble/get-started/ble-data-exchange.rst b/docs/en/api-guides/ble/get-started/ble-data-exchange.rst
index 4b455a4bc14..e8a00f57ef1 100644
--- a/docs/en/api-guides/ble/get-started/ble-data-exchange.rst
+++ b/docs/en/api-guides/ble/get-started/ble-data-exchange.rst
@@ -1 +1,660 @@
-.. include:: ../../../../zh_CN/api-guides/ble/get-started/ble-data-exchange.rst
+Data Exchange
+========================
+
+:link_to_translation:`zh_CN:[中文]`
+
+This document is the fourth tutorial in the Getting Started series on Bluetooth Low Energy (Bluetooth LE), aiming to provide a brief overview of the data exchange process within Bluetooth LE connections. Subsequently, this tutorial introduces the code implementation of a GATT server, using the :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` example based on the NimBLE host layer stack.
+
+
+Learning Objectives
+----------------------------
+
+- Understand the data structure details of characteristic data and services
+- Learn about different data access operations in GATT
+- Learn about the code structure of the :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` example
+
+
+GATT Data Characteristics and Services
+--------------------------------------------------
+
+GATT services are the infrastructure for data exchange between two devices in a Bluetooth LE connection, with the minimum data unit being an attribute. In the section on :ref:`Data Representation and Exchange <gatt_att_introduction>`, we briefly introduced the attributes at the ATT layer and the characteristic data, services, and specifications at the GATT layer. Below are details regarding the attribute-based data structure.
+
+
+Attributes
+^^^^^^^^^^^^^^^^^^^^^^
+
+An attribute consists of the following four parts:
+
+.. list-table::
+    :align: center
+    :widths: 10 30 60
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+        -   Description
+    *   -   1
+        -   Handle
+        -   A 16-bit unsigned integer representing the index of the attribute in the :ref:`attribute table <attribute_table>`
+    *   -   2
+        -   Type
+        -   ATT attributes use UUID (Universally Unique Identifier) to differentiate types
+    *   -   3
+        -   Access Permission
+        -   Indicates whether encryption/authorization is needed; whether it is readable or writable
+    *   -   4
+        -   Value
+        -   Actual user data or metadata of another attribute
+
+There are two types of UUIDs in Bluetooth LE:
+
+1. 16-bit UUIDs defined by SIG
+2. 128-bit UUIDs customized by manufacturers
+
+Common characteristic and service UUIDs are provided in SIG's `Assigned Numbers <https://www.bluetooth.com/specifications/assigned-numbers/>`_ standard document, such as:
+
+.. list-table::
+    :align: center
+    :widths: 20 60 20
+    :header-rows: 1
+
+    *   -   Category
+        -   Type Name
+        -   UUID
+    *   -   Service
+        -   Blood Pressure Service
+        -   `0x1810`
+    *   -   Service
+        -   Common Audio Service
+        -   `0x1853`
+    *   -   Characteristic Data
+        -   Age
+        -   `0x2A80`
+    *   -   Characteristic Data
+        -   Appearance
+        -   `0x2A01`
+
+In fact, the definitions of these services and characteristic data are also provided by the SIG. For example, the value of the Heart Rate Measurement must include a flag field and a heart rate measurement field, and may include fields such as energy expended, RR-interval, and transmission interval, among others. Therefore, these definitions from SIG allow Bluetooth LE devices from different manufacturers to recognize each other's services or characteristic data, enabling cross-manufacturer communication.
+
+Manufacturers' customized 128-bit UUIDs are used for proprietary services or data characteristics, such as the UUID for the LED characteristic in this example: `0x00001525-1212-EFDE-1523-785FEABCD123`.
+
+
+Characteristic Data
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _characteristic_attributes:
+
+A characteristic data item typically consists of the following attributes:
+
+.. list-table::
+    :align: center
+    :widths: 10 30 30 30
+    :header-rows: 1
+
+    *   -   No.
+        -   Type
+        -   Function
+        -   Notes
+    *   -   1
+        -   Characteristic Declaration
+        -   Contains properties, handle, and UUID info for the characteristic value
+        -   UUID is 0x2803, read-only
+    *   -   2
+        -   Characteristic Value
+        -   user data
+        -   UUID identifies the characteristic type
+    *   -   3
+        -   Characteristic Descriptor
+        -   Additional description for the characteristic data
+        -   Optional attribute
+
+
+Relationship between Characteristic Declaration and Characteristic Value
+################################################################################
+
+
+Using the Heart Rate Measurement as an example, the relationship between the characteristic declaration and characteristic value is illustrated as follows:
+
+The table below is an attribute table, containing two attributes of the Heart Rate Measurement characteristic. Let's first look at the attribute with handle 0. Its UUID is `0x2803`, and the access permission is read-only, indicating that this is a characteristic declaration attribute. The attribute value shows that the read/write property is read-only, and the handle points to 1, indicating that the attribute with handle 1 is the value attribute for this characteristic. The UUID is `0x2A37`, meaning that this characteristic type is Heart Rate Measurement.
+
+Now, let's examine the attribute with handle 1. Its UUID is `0x2A37`, and the access permission is also read-only, corresponding directly with the characteristic declaration attribute. The value of this attribute consists of flag bits and measurement values, which complies with the SIG specification for Heart Rate Measurement characteristic data.
+
++-------------+--------------+-----------------+-------------------------+----------------------------+
+| Handle      | UUID         | Permissions     | Value                   | Attribute Type             |
++=============+==============+=================+=========================+============================+
+| 0           | `0x2803`     | Read-only       | Properties = Read-only  | Characteristic Declaration |
+|             |              |                 +-------------------------+                            |
+|             |              |                 | Handle = 1              |                            |
+|             |              |                 +-------------------------+                            |
+|             |              |                 | UUID = `0x2A37`         |                            |
++-------------+--------------+-----------------+-------------------------+----------------------------+
+| 1           | `0x2A37`     | Read-only       | Flags                   | Characteristic Value       |
+|             |              |                 +-------------------------+                            |
+|             |              |                 | Measurement value       |                            |
++-------------+--------------+-----------------+-------------------------+----------------------------+
+
+
+Characteristic Descriptors
+#########################################
+
+Characteristic descriptors provide supplementary information about characteristic data. The most common is the Client Characteristic Configuration Descriptor (CCCD). When a characteristic supports server-initiated :ref:`data operations <gatt_data_operation>` (notifications or indications), CCCD must be used to describe the relevant information. This is a read-write attribute that allows the GATT client to inform the server whether notifications or indications should be enabled. Writing to this value is also referred to as subscribing or unsubscribing.
+
+The UUID for CCCD is `0x2902`, and its attribute value contains only 2 bits of information. The first bit indicates whether notifications are enabled, and the second bit indicates whether indications are enabled. By adding the CCCD to the attribute table and providing indication access permissions for the Heart Rate Measurement characteristic data, we obtain the complete form of the Heart Rate Measurement characteristic data in the attribute table as follows:
+
++-------------+--------------+-----------------+-----------------------------+----------------------------+
+| Handle      | UUID         | Permissions     | Value                       | Attribute Type             |
++=============+==============+=================+=============================+============================+
+| 0           | `0x2803`     | Read-only       | Properties = Read/Indicate  | Characteristic Declaration |
+|             |              |                 +-----------------------------+                            |
+|             |              |                 | Handle = 1                  |                            |
+|             |              |                 +-----------------------------+                            |
+|             |              |                 | UUID = `0x2A37`             |                            |
++-------------+--------------+-----------------+-----------------------------+----------------------------+
+| 1           | `0x2A37`     | Read/Indicate   | Flags                       | Characteristic Value       |
+|             |              |                 +-----------------------------+                            |
+|             |              |                 | Measurement value           |                            |
++-------------+--------------+-----------------+-----------------------------+----------------------------+
+| 2           | `0x2902`     | Read/Write      | Notification status         | Characteristic Descriptor  |
+|             |              |                 +-----------------------------+                            |
+|             |              |                 | Indication status           |                            |
++-------------+--------------+-----------------+-----------------------------+----------------------------+
+
+
+Services
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The data structure of a service can be broadly divided into two parts:
+
+.. list-table::
+    :align: center
+    :widths: 20 80
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+    *   -   1
+        -   Service Declaration Attribute
+    *   -   2
+        -   Characteristic Definition Attributes
+
+The three characteristic data attributes mentioned in the :ref:`Characteristic Data <characteristic_attributes>` belong to characteristic definition attributes. In essence, the data structure of a service consists of several characteristic data attributes along with a service declaration attribute.
+
+The UUID for the service declaration attribute is 0x2800, which is read-only and holds the UUID identifying the service type. For example, the UUID for the Heart Rate Service is `0x180D`, so its service declaration attribute can be represented as follows:
+
+.. list-table::
+    :align: center
+    :widths: 10 20 20 20 30
+    :header-rows: 1
+
+    *   -   Handle
+        -   UUID
+        -   Permissions
+        -   Value
+        -   Attribute Type
+    *   -   0
+        -   `0x2800`
+        -   Read-only
+        -   `0x180D`
+        -   Service Declaration
+
+
+Attribute Example
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _attribute_table:
+
+The following is an example of a possible attribute table for a GATT server, using the :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` as an illustration. The example includes two services: the Heart Rate Service and the Automation IO Service. The former contains a Heart Rate Measurement characteristic, while the latter includes an LED characteristic. The complete attribute table for the GATT server is as follows:
+
++-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
+| Handle      | UUID                                     | Permissions     | Value                                           | Attribute Type             |
++=============+==========================================+=================+=================================================+============================+
+| 0           | `0x2800`                                 | Read-only       | UUID = `0x180D`                                 | Service Declaration        |
++-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
+| 1           | `0x2803`                                 | Read-only       | Properties = Read/Indicate                      | Characteristic Declaration |
+|             |                                          |                 +-------------------------------------------------+                            |
+|             |                                          |                 | Handle = 2                                      |                            |
+|             |                                          |                 +-------------------------------------------------+                            |
+|             |                                          |                 | UUID = `0x2A37`                                 |                            |
++-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
+| 2           | `0x2A37`                                 | Read/Indicate   | Flags                                           | Characteristic Value       |
+|             |                                          |                 +-------------------------------------------------+                            |
+|             |                                          |                 | Measurement value                               |                            |
++-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
+| 3           | `0x2902`                                 | Read/Write      | Notification status                             | Characteristic Descriptor  |
+|             |                                          |                 +-------------------------------------------------+                            |
+|             |                                          |                 | Indication status                               |                            |
++-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
+| 4           | `0x2800`                                 | Read-only       | UUID = `0x1815`                                 | Service Declaration        |
++-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
+| 5           | `0x2803`                                 | Read-only       | Properties = Write-only                         | Characteristic Declaration |
+|             |                                          |                 +-------------------------------------------------+                            |
+|             |                                          |                 | Handle = 6                                      |                            |
+|             |                                          |                 +-------------------------------------------------+                            |
+|             |                                          |                 | UUID = `0x00001525-1212-EFDE-1523-785FEABCD123` |                            |
++-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
+| 6           | `0x00001525-1212-EFDE-`                  |Write-only       | LED status                                      |Characteristic Value        |
+|             | `1523-785FE`                             |                 |                                                 |                            |
+|             | `ABCD123`                                |                 |                                                 |                            |
++-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
+
+When a GATT client first establishes communication with a GATT server, it pulls metadata from the server's attribute table to discover the available services and characteristics. This process is known as *Service Discovery*.
+
+
+GATT Data Operations
+------------------------------
+
+.. _gatt_data_operation:
+
+Data operations refer to accessing characteristic data on a GATT server, which can be mainly categorized into two types:
+
+1. Client-initiated operations
+2. Server-initiated operations
+
+
+Client-initiated Operations
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Client-initiated operations include the following three types:
+
+- **Read**
+    - A straightforward operation to pull the current value of a specific characteristic from the GATT server.
+- **Write**
+    - Standard write operations require confirmation from the GATT server upon receiving the client's write request and data.
+- **Write without response**
+    - This is another form of write operation that does not require server acknowledgment.
+
+
+Server-Initiated Operations
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Server-initiated operations are divided into two types:
+
+- **Notify**
+    - A GATT server actively pushes data to the client without requiring a confirmation response.
+- **Indicate**
+    - Similar to notifications, but this requires confirmation from the client, which makes indication slower than notification.
+
+Although both notifications and indications are initiated by the server, the prerequisite for these operations is that the client has enabled notifications or indications. Therefore, the data exchange process in GATT essentially begins with a client request for data.
+
+
+Hands-On Practice
+----------------------------
+
+Having grasped the relevant knowledge of GATT data exchange, let’s combine the :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` example code to learn how to build a simple GATT server using the NimBLE protocol stack and put our knowledge into practice.
+
+
+Prerequisites
+^^^^^^^^^^^^^^^^^^
+
+1. An {IDF_TARGET_NAME} development board
+2. ESP-IDF development environment
+3. The nRF Connect for Mobile application installed on your phone
+
+If you have not completed the ESP-IDF development environment setup, please refer to :doc:`IDF Get Started <../../../get-started/index>`.
+
+
+Try It Out
+^^^^^^^^^^^^^^^^^^
+
+Please refer to :ref:`BLE Introduction Try It Out <nimble_gatt_server_practice>` 。
+
+
+Code Explanation
+-------------------------------
+
+
+Project Structure Overview
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The root directory structure of :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` is identical to that of :ref:`NimBLE_Connection <nimble_connection_project_structure>`. Additionally, the `main` folder includes source code related to the GATT service and simulated heart rate generation.
+
+
+Program Behavior Overview
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The program behavior of this example is largely consistent with that of :ref:`NimBLE_Connection <nimble_connection_project_structure>`, with the difference being that this example adds GATT services and handles access to GATT characteristic data through corresponding callback functions.
+
+
+Entry Function
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _nimble_gatt_server_entry_point:
+
+Based on :ref:`NimBLE_Connection <nimble_connection_entry_point>`, a process to initialize the GATT service by calling the `gatt_svc_init` function has been added. Moreover, in addition to the NimBLE thread, a new `heart_rate_task` thread has been introduced, responsible for the random generation of simulated heart rate measurement data and indication handling. Relevant code is as follows:
+
+.. code-block:: C
+
+    static void heart_rate_task(void *param) {
+        /* Task entry log */
+        ESP_LOGI(TAG, "heart rate task has been started!");
+
+        /* Loop forever */
+        while (1) {
+            /* Update heart rate value every 1 second */
+            update_heart_rate();
+            ESP_LOGI(TAG, "heart rate updated to %d", get_heart_rate());
+
+            /* Send heart rate indication if enabled */
+            send_heart_rate_indication();
+
+            /* Sleep */
+            vTaskDelay(HEART_RATE_TASK_PERIOD);
+        }
+
+        /* Clean up at exit */
+        vTaskDelete(NULL);
+    }
+
+    void app_main(void) {
+        ...
+
+        xTaskCreate(heart_rate_task, "Heart Rate", 4*1024, NULL, 5, NULL);
+        return;
+    }
+
+The `heart_rate_task` thread runs at a frequency of 1 Hz, as `HEART_RATE_TASK_PERIOD` is defined as 1000 ms. Each time it executes, the thread calls the `update_heart_rate` function to randomly generate a new heart rate measurement and then calls `send_heart_rate_indication` to handle the indication operation.
+
+
+GATT Service Initialization
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+In the `gatt_svc.c` file, there is a GATT service initialization function as follows:
+
+.. code-block:: C
+
+    int gatt_svc_init(void) {
+        /* Local variables */
+        int rc;
+
+        /* 1. GATT service initialization */
+        ble_svc_gatt_init();
+
+        /* 2. Update GATT services counter */
+        rc = ble_gatts_count_cfg(gatt_svr_svcs);
+        if (rc != 0) {
+            return rc;
+        }
+
+        /* 3. Add GATT services */
+        rc = ble_gatts_add_svcs(gatt_svr_svcs);
+        if (rc != 0) {
+            return rc;
+        }
+
+        return 0;
+    }
+
+This function first calls the `ble_svc_gatt_init` API to initialize the GATT Service. It's important to note that this GATT Service is a special service with the UUID `0x1801`, which is used by the GATT server to notify clients when services change (i.e., when GATT services are added or removed). In such cases, the client will re-execute the service discovery process to update its service information.
+
+Next, the function calls `ble_gatts_count_cfg` and `ble_gatts_add_svcs` APIs to add the services and characteristic data defined in the `gatt_svr_svcs` service table to the GATT server.
+
+
+GATT Service Table
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The `gatt_svr_svcs service` table is a crucial data structure in this example, defining all services and characteristic data used. The relevant code is as follows:
+
+.. code-block:: C
+
+    /* Heart rate service */
+    static const ble_uuid16_t heart_rate_svc_uuid = BLE_UUID16_INIT(0x180D);
+
+    ...
+
+    static uint16_t heart_rate_chr_val_handle;
+    static const ble_uuid16_t heart_rate_chr_uuid = BLE_UUID16_INIT(0x2A37);
+
+    static uint16_t heart_rate_chr_conn_handle = 0;
+
+    ...
+
+    /* Automation IO service */
+    static const ble_uuid16_t auto_io_svc_uuid = BLE_UUID16_INIT(0x1815);
+    static uint16_t led_chr_val_handle;
+    static const ble_uuid128_t led_chr_uuid =
+        BLE_UUID128_INIT(0x23, 0xd1, 0xbc, 0xea, 0x5f, 0x78, 0x23, 0x15, 0xde, 0xef,
+                        0x12, 0x12, 0x25, 0x15, 0x00, 0x00);
+
+    /* GATT services table */
+    static const struct ble_gatt_svc_def gatt_svr_svcs[] = {
+        /* Heart rate service */
+        {.type = BLE_GATT_SVC_TYPE_PRIMARY,
+        .uuid = &heart_rate_svc_uuid.u,
+        .characteristics =
+            (struct ble_gatt_chr_def[]){
+                {/* Heart rate characteristic */
+                .uuid = &heart_rate_chr_uuid.u,
+                .access_cb = heart_rate_chr_access,
+                .flags = BLE_GATT_CHR_F_READ | BLE_GATT_CHR_F_INDICATE,
+                .val_handle = &heart_rate_chr_val_handle},
+                {
+                    0, /* No more characteristics in this service. */
+                }}},
+
+        /* Automation IO service */
+        {
+            .type = BLE_GATT_SVC_TYPE_PRIMARY,
+            .uuid = &auto_io_svc_uuid.u,
+            .characteristics =
+                (struct ble_gatt_chr_def[]){/* LED characteristic */
+                                            {.uuid = &led_chr_uuid.u,
+                                            .access_cb = led_chr_access,
+                                            .flags = BLE_GATT_CHR_F_WRITE,
+                                            .val_handle = &led_chr_val_handle},
+                                            {0}},
+        },
+
+        {
+            0, /* No more services. */
+        },
+    };
+
+The macros `BLE_UUID16_INIT` and `BLE_UUID128_INIT` provided by the NimBLE protocol stack allow for convenient conversion of 16-bit and 128-bit UUIDs from raw data into `ble_uuid16_t` and `ble_uuid128_t` type variables.
+
+The `gatt_svr_svcs` is an array of structures of type `ble_gatt_svc_def`. The `ble_gatt_svc_def` structure defines a service, with key fields being `type`, `uuid`, and `characteristics`. The `type` field indicates whether the service is primary or secondary, with all services in this example being primary. The `uuid` field represents the UUID of the service. The `characteristics` field is an array of `ble_gatt_chr_def` structures that stores the characteristics associated with the service.
+
+The `ble_gatt_chr_def` structure defines the characteristics, with key fields being `uuid`, `access_cb`, `flags`, and `val_handle`. The `uuid` field is the UUID of the characteristic. The `access_cb` field points to the access callback function for that characteristic. The `flags` field indicates the access permissions for the characteristic data. The `val_handle` field points to the variable handle address for the characteristic value.
+
+It's important to note that when the `BLE_GATT_CHR_F_INDICATE` flag is set for a characteristic, the NimBLE protocol stack automatically adds the CCCD, so there's no need to manually add the descriptor.
+
+Based on variable naming, it's clear that `gatt_svr_svcs` implements all property definitions in the :ref:`attribute table <attribute_table>`. Additionally, access to the Heart Rate Measurement characteristic is managed through the `heart_rate_chr_access` callback function, while access to the LED characteristic is managed through the `led_chr_access` callback function.
+
+
+Characteristic Data Access Management
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+
+LED Access Management
+#####################################
+
+Access to the LED characteristic data is managed through the `led_chr_access` callback function, with the relevant code as follows:
+
+.. code-block:: C
+
+    static int led_chr_access(uint16_t conn_handle, uint16_t attr_handle,
+                            struct ble_gatt_access_ctxt *ctxt, void *arg) {
+        /* Local variables */
+        int rc;
+
+        /* Handle access events */
+        /* Note: LED characteristic is write only */
+        switch (ctxt->op) {
+
+        /* Write characteristic event */
+        case BLE_GATT_ACCESS_OP_WRITE_CHR:
+            /* Verify connection handle */
+            if (conn_handle != BLE_HS_CONN_HANDLE_NONE) {
+                ESP_LOGI(TAG, "characteristic write; conn_handle=%d attr_handle=%d",
+                        conn_handle, attr_handle);
+            } else {
+                ESP_LOGI(TAG,
+                        "characteristic write by nimble stack; attr_handle=%d",
+                        attr_handle);
+            }
+
+            /* Verify attribute handle */
+            if (attr_handle == led_chr_val_handle) {
+                /* Verify access buffer length */
+                if (ctxt->om->om_len == 1) {
+                    /* Turn the LED on or off according to the operation bit */
+                    if (ctxt->om->om_data[0]) {
+                        led_on();
+                        ESP_LOGI(TAG, "led turned on!");
+                    } else {
+                        led_off();
+                        ESP_LOGI(TAG, "led turned off!");
+                    }
+                } else {
+                    goto error;
+                }
+                return rc;
+            }
+            goto error;
+
+        /* Unknown event */
+        default:
+            goto error;
+        }
+
+    error:
+        ESP_LOGE(TAG,
+                "unexpected access operation to led characteristic, opcode: %d",
+                ctxt->op);
+        return BLE_ATT_ERR_UNLIKELY;
+    }
+
+When the GATT client initiates access to the LED characteristic data, the NimBLE protocol stack will call the `led_chr_access` callback function, passing in the handle information and access context. The `op` field of `ble_gatt_access_ctxt` is used to identify different access events. Since the LED is a write-only characteristic, we only handle the `BLE_GATT_ACCESS_OP_WRITE_CHR` event.
+
+In this processing branch, we first validate the attribute handle to ensure that the client is accessing the LED characteristic. Then, based on the `om` field of `ble_gatt_access_ctxt`, we verify the length of the access data. Finally, we check if the data in `om_data` is equal to 1 to either turn the LED on or off.
+
+If any other access events occur, they are considered unexpected, and we proceed to the error branch to return.
+
+
+Heart Rate Measurement Read Access Management
+######################################################
+
+The heart rate measurement is a readable and indicative characteristic. The read access initiated by the client for heart rate measurement values is managed by the `heart_rate_chr_access` callback function, with the relevant code as follows:
+
+.. code-block:: C
+
+    static int heart_rate_chr_access(uint16_t conn_handle, uint16_t attr_handle,
+                                    struct ble_gatt_access_ctxt *ctxt, void *arg) {
+        /* Local variables */
+        int rc;
+
+        /* Handle access events */
+        /* Note: Heart rate characteristic is read only */
+        switch (ctxt->op) {
+
+        /* Read characteristic event */
+        case BLE_GATT_ACCESS_OP_READ_CHR:
+            /* Verify connection handle */
+            if (conn_handle != BLE_HS_CONN_HANDLE_NONE) {
+                ESP_LOGI(TAG, "characteristic read; conn_handle=%d attr_handle=%d",
+                        conn_handle, attr_handle);
+            } else {
+                ESP_LOGI(TAG, "characteristic read by nimble stack; attr_handle=%d",
+                        attr_handle);
+            }
+
+            /* Verify attribute handle */
+            if (attr_handle == heart_rate_chr_val_handle) {
+                /* Update access buffer value */
+                heart_rate_chr_val[1] = get_heart_rate();
+                rc = os_mbuf_append(ctxt->om, &heart_rate_chr_val,
+                                    sizeof(heart_rate_chr_val));
+                return rc == 0 ? 0 : BLE_ATT_ERR_INSUFFICIENT_RES;
+            }
+            goto error;
+
+        /* Unknown event */
+        default:
+            goto error;
+        }
+
+    error:
+        ESP_LOGE(
+            TAG,
+            "unexpected access operation to heart rate characteristic, opcode: %d",
+            ctxt->op);
+        return BLE_ATT_ERR_UNLIKELY;
+    }
+
+Similar to the LED access management, we use the `op` field of the `ble_gatt_access_ctxt` access context to determine the access event, handling the `BLE_GATT_ACCESS_OP_READ_CHR` event.
+
+In the handling branch, we first validate the attribute handle to confirm that the client is accessing the heart rate measurement attribute. Then, we call the `get_heart_rate` function to retrieve the latest heart rate measurement, storing it in the measurement area of the `heart_rate_chr_val` array. Finally, we copy the data from `heart_rate_chr_val` into the `om` field of the `ble_gatt_access_ctxt` access context. The NimBLE protocol stack will send the data in this field to the client after the current callback function ends, thus achieving read access to the Heart Rate Measurement characteristic value.
+
+
+Heart Rate Measurement Indication
+#############################################
+
+When the client enables indications for heart rate measurements, the processing flow is a bit more complicated. First, enabling or disabling the heart rate measurement indications is a subscription or unsubscription event at the GAP layer, so we need to add a handling branch for subscription events in the `gap_event_handler` callback function, as follows:
+
+.. code-block:: C
+
+    static int gap_event_handler(struct ble_gap_event *event, void *arg) {
+        ...
+
+        /* Subscribe event */
+        case BLE_GAP_EVENT_SUBSCRIBE:
+            /* Print subscription info to log */
+            ESP_LOGI(TAG,
+                    "subscribe event; conn_handle=%d attr_handle=%d "
+                    "reason=%d prevn=%d curn=%d previ=%d curi=%d",
+                    event->subscribe.conn_handle, event->subscribe.attr_handle,
+                    event->subscribe.reason, event->subscribe.prev_notify,
+                    event->subscribe.cur_notify, event->subscribe.prev_indicate,
+                    event->subscribe.cur_indicate);
+
+            /* GATT subscribe event callback */
+            gatt_svr_subscribe_cb(event);
+            return rc;
+    }
+
+The subscription event is represented by `BLE_GAP_EVENT_SUBSCRIBE`. In this handling branch, we do not process the subscription event directly; instead, we call the `gatt_svr_subscribe_cb` callback function to handle the subscription event. This reflects the layered design philosophy of software, as the subscription event affects the GATT server's behavior in sending characteristic data and is not directly related to the GAP layer. Thus, it should be passed to the GATT layer for processing.
+
+Next, let's take a look at the operations performed in the `gatt_svr_subscribe_cb` callback function.
+
+.. code-block:: C
+
+    void gatt_svr_subscribe_cb(struct ble_gap_event *event) {
+        /* Check connection handle */
+        if (event->subscribe.conn_handle != BLE_HS_CONN_HANDLE_NONE) {
+            ESP_LOGI(TAG, "subscribe event; conn_handle=%d attr_handle=%d",
+                    event->subscribe.conn_handle, event->subscribe.attr_handle);
+        } else {
+            ESP_LOGI(TAG, "subscribe by nimble stack; attr_handle=%d",
+                    event->subscribe.attr_handle);
+        }
+
+        /* Check attribute handle */
+        if (event->subscribe.attr_handle == heart_rate_chr_val_handle) {
+            /* Update heart rate subscription status */
+            heart_rate_chr_conn_handle = event->subscribe.conn_handle;
+            heart_rate_chr_conn_handle_inited = true;
+            heart_rate_ind_status = event->subscribe.cur_indicate;
+        }
+    }
+
+In this example, the callback handling is quite simple: it checks whether the attribute handle in the subscription event corresponds to the heart rate measurement attribute handle. If it does, it saves the corresponding connection handle and updates the indication status requested by the client.
+
+As mentioned in :ref:`Entry Function <nimble_gatt_server_entry_point>`, the `send_heart_rate_indication` function is called by the `heart_rate_task` thread at a frequency of 1 Hz. The implementation of this function is as follows:
+
+.. code-block:: C
+
+    void send_heart_rate_indication(void) {
+        if (heart_rate_ind_status && heart_rate_chr_conn_handle_inited) {
+            ble_gatts_indicate(heart_rate_chr_conn_handle,
+                            heart_rate_chr_val_handle);
+            ESP_LOGI(TAG, "heart rate indication sent!");
+        }
+    }
+
+The `ble_gatts_indicate` function is an API provided by the NimBLE protocol stack for sending indications. This means that when the indication status for the heart rate measurement is true and the corresponding connection handle is available, calling the `send_heart_rate_indication` function will send the heart rate measurement to the GATT client.
+
+To summarize, when a GATT client subscribes to heart rate measurements, the `gap_event_handler` receives the subscription event and passes it to the `gatt_svr_subscribe_cb` callback function, which updates the subscription status for heart rate measurements. In the `heart_rate_task` thread, it checks the subscription status every second; if the status is true, it sends the heart rate measurement to the client.
+
+Summary
+--------------------------------
+
+Through this tutorial, you have learned how to create GATT services and their corresponding characteristic data using a service table, and you mastered the management of access to GATT characteristic data, including read, write, and subscription operations. You can now build more complex GATT service applications based on the :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` example.
diff --git a/docs/en/api-guides/ble/get-started/ble-device-discovery.rst b/docs/en/api-guides/ble/get-started/ble-device-discovery.rst
index f6986844999..10895c586b2 100644
--- a/docs/en/api-guides/ble/get-started/ble-device-discovery.rst
+++ b/docs/en/api-guides/ble/get-started/ble-device-discovery.rst
@@ -1 +1,885 @@
-.. include:: ../../../../zh_CN/api-guides/ble/get-started/ble-device-discovery.rst
+Device Discovery
+=======================
+
+:link_to_translation:`zh_CN:[中文]`
+
+This document is the second tutorial in the Getting Started series on Bluetooth Low Energy (Bluetooth LE), aiming to provide a brief overview of the Bluetooth LE device discovery process, including basic concepts related to advertising and scanning. Following this, the tutorial introduces the code implementation of Bluetooth LE advertising, using the :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` example based on the NimBLE host layer stack.
+
+
+Learning Objectives
+-----------------------
+
+- Understand the basic concepts of Advertising
+- Understand the basic concepts of Scanning
+- Learn about the code structure of the :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` example
+
+
+Advertising and Scanning are the states of Bluetooth LE devices during the device discovery phase before establishing a connection. First, let’s understand the basic concepts related to advertising.
+
+
+Basic Concepts of Advertising
+---------------------------------
+
+Advertising is the process where a device sends out advertising packets via its Bluetooth antenna. Since the advertiser does not know whether there is a receiver in the environment or when the receiver will activate its antenna, it needs to send advertising packets periodically until a device responds. During this process, there are several questions for the advertiser to consider:
+
+1. Where should the advertising packets be sent? (Where?)
+2. How long should the interval between advertising packets be? (When?)
+3. What information should be included in the advertising packets? (What?)
+
+
+Where to Send Advertising Packets?
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Bluetooth Radio Frequency Band
+########################################
+
+The first question pertains to which radio frequency band the advertising packets should be sent on. The answer is provided by the Bluetooth Core Specification: the 2.4 GHz ISM band. This band is a globally available, license-free radio frequency band that is not controlled by any country for military or other purposes, and does not require payment to any organization. Thus, it has high availability and no usage costs. However, this also means the 2.4 GHz ISM band is very crowded and may interfere with other wireless communication protocols such as 2.4 GHz WiFi.
+
+
+Bluetooth Channels
+############################
+
+Similar to Bluetooth Classic, the Bluetooth SIG has adopted Adaptive Frequency Hopping (AFH) in Bluetooth LE to address data collision issues. This technology can assess the congestion of RF channels and avoid crowded channels through frequency hopping to improve communication quality. However, unlike Bluetooth Classic, Bluetooth LE uses the 2.4 GHz ISM band divided into 40 RF channels, each with a 2 MHz bandwidth, ranging from 2402 MHz to 2480 MHz, while Bluetooth Classic uses 79 RF channels, each with a 1 MHz bandwidth.
+
+In the Bluetooth LE 4.2 standard, RF channels are categorized into two types, as follows:
+
+.. list-table::
+    :align: center
+    :widths: 30 20 20 30
+    :header-rows: 1
+
+    *   -   Type
+        -   Quantity
+        -   Index
+        -   Purpose
+    *   -   Advertising Channel
+        -   3
+        -   37-39
+        -   Used for sending advertising packets and scan response packets
+    *   -   Data Channel
+        -   37
+        -   0-36
+        -   Used for sending data channel packets
+
+During advertising, the advertiser will send advertising packets on the three advertising channels (37-39). Once the advertising packets have been sent on all three channels, the advertising process is considered complete, and the advertiser will repeat the process at the next advertising interval.
+
+
+Extended Advertising Features
+##################################
+
+In the Bluetooth LE 4.2 standard, advertising packets are limited to a maximum of 31 bytes, which restricts the functionality of advertising. To enhance the capability of advertising, Bluetooth 5.0 introduced the Extended Advertising feature. This feature divides advertising packets into:
+
+.. list-table::
+    :align: center
+    :widths: 40 20 20 20
+    :header-rows: 1
+
+    *   -   Type
+        -   Abbreviation
+        -   Max Payload Size per Packet (Bytes）
+        -   Max Total Payload Size (Bytes)
+    *   -   Primary Advertising Packet
+        -   Legacy ADV
+        -   31
+        -   31
+    *   -   Extended Advertising Packet
+        -   Extended ADV
+        -   254
+        -   1650
+
+Extended advertising packets are composed of `ADV_EXT_IND` and `AUX_ADV_IND`, transmitted on the primary and secondary advertising channels, respectively. The primary advertising channels correspond to channels 37-39, while the secondary advertising channels correspond to channels 0-36. Since the receiver always receives advertising data on the primary advertising channels, the advertiser must send `ADV_EXT_IND` on the primary advertising channels and `AUX_ADV_IND` on the secondary advertising channels. `ADV_EXT_IND` will indicate the secondary advertising channels where `AUX_ADV_IND` is transmitted. This mechanism allows the receiver to obtain the complete extended advertising packet by first receiving `ADV_EXT_IND` on the primary advertising channels and then going to the specified secondary advertising channels to receive `AUX_ADV_IND`.
+
+.. list-table::
+    :align: center
+    :widths: 30 40 30
+    :header-rows: 1
+
+    *   -   Type
+        -   Channels
+        -   Purpose
+    *   -   Primary Advertising Channel
+        -   37-39
+        -   Used to transmit `ADV_EXT_IND` of the extended advertising packet
+    *   -   Secondary Advertising Channel
+        -   0-36
+        -   Used to transmit `AUX_ADV_IND` of the extended advertising packet
+
+
+How long should the advertising interval be?
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Advertising Interval
+#########################
+
+For the second question, regarding the period for sending advertising packets, the Bluetooth standard provides a clear parameter definition: Advertising Interval. The advertising interval can range from 20 ms to 10.24 s, with a step size of 0.625 ms.
+
+The choice of advertising interval affects both the discoverability of the advertiser and the device’s power consumption. If the advertising interval is too long, the probability of the advertising packets being received by a receiver becomes very low, which decreases the advertiser’s discoverability. Conversely, if the advertising interval is too short, frequent advertising consumes more power. Therefore, the advertiser needs to balance between discoverability and power consumption and choose the most appropriate advertising interval based on the application's needs.
+
+It is worth noting that if there are two advertisers with the same advertising interval in the same space, packet collision may occur, meaning both advertisers are sending advertising data to the same channel at the same time. Since advertising is a one-way process with no reception, the advertiser cannot know if a packet collision has occurred. To reduce the likelihood of such collisions, advertisers should add a random delay of 0-10 ms after each advertising event.
+
+
+What information is included in the advertising packet?
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Advertising Packet Structure
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+For the third question, regarding the information contained in the advertising packet, the Bluetooth LE 4.2 standard defines the format of the advertising packet, as shown in the diagram below:
+
+
+.. _adv_packet_structure:
+
+.. figure:: ../../../../_static/ble/ble-4.2-adv-packet-structure.png
+    :align: center
+    :scale: 35%
+    :alt: Advertising Packet Structure
+
+    Bluetooth LE 4.2 Advertising Packet Structure
+
+
+Let’s break it down step by step. The outer layer of an advertising packet contains four parts, which are:
+
+.. list-table::
+    :align: center
+    :widths: 10 40 10 40
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+        -   Byte Size
+        -   Function
+    *   -   1
+        -   Preamble
+        -   1
+        -   A special bit sequence used for device clock synchronization
+    *   -   2
+        -   Access Address
+        -   4
+        -   Marks the address of the advertising packet
+    *   -   3
+        -   Protocol Data Unit, PDU
+        -   2-39
+        -   The area where the actual data is stored
+    *   -   4
+        -   Cyclic Redundancy Check, CRC
+        -   3
+        -   Used for cyclic redundancy checking
+
+The advertising packet is a type of Bluetooth packet, and its nature is determined by the type of PDU. Now, let's take a detailed look at the PDU.
+
+
+PDU
+##########################
+
+The PDU segment is where the actual data is stored. Its structure is as follows:
+
+.. list-table::
+    :align: center
+    :widths: 10 50 40
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+        -   Byte Size
+    *   -   1
+        -   Header
+        -   2
+    *   -   2
+        -   Payload
+        -   0-37
+
+
+PDU Header
+##############
+
+The PDU header contains various pieces of information, which can be broken down into six parts:
+
+.. list-table::
+    :align: center
+    :widths: 10 40 10 40
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+        -   Bit Size
+        -   Notes
+    *   -   1
+        -   PDU Type
+        -   4
+        -
+    *   -   2
+        -   Reserved for Future Use, **RFU**
+        -   1
+        -
+    *   -   3
+        -   Channel Selection Bit, **ChSel**
+        -   1
+        -   Indicates whether the advertiser supports the *LE Channel Selection Algorithm #2*
+    *   -   4
+        -   TX Address, **TxAdd**
+        -   1
+        -   0/1 indicates Public Address/Random Address
+    *   -   5
+        -   Rx Address, **RxAdd**
+        -   1
+        -   0/1 indicates Public Address/Random Address
+    *   -   6
+        -   Payload Length
+        -   8
+        -
+
+The PDU Type bit reflects the advertising behavior of the device. In the Bluetooth protocol, there are three pairs of advertising behaviors:
+
+- *Connectable* vs. *Non-connectable*:
+    - Whether the device accepts connection requests from others.
+- *Scannable* vs. *Non-scannable*:
+    - Whether the device accepts scan requests from others.
+- *Undirected* vs. *Directed*:
+    - Whether the advertising packet is sent to a specific device.
+
+These advertising behaviors can be combined into four common types of advertising, corresponding to four different PDU types:
+
+.. list-table::
+    :align: center
+    :widths: 10 10 10 30 40
+    :header-rows: 1
+
+    *   -   Connectable？
+        -   Scannable？
+        -   Undirected？
+        -   PDU Type
+        -   Purpose
+    *   -   Y
+        -   Y
+        -   Y
+        -   `ADV_IND`
+        -   The most common advertising type
+    *   -   Y
+        -   N
+        -   N
+        -   `ADV_DIRECT_IND`
+        -   Commonly used for reconnecting with known devices
+    *   -   N
+        -   N
+        -   Y
+        -   `ADV_NONCONN_IND`
+        -   Used by beacon devices to advertising data without connection
+    *   -   N
+        -   Y
+        -   Y
+        -   `ADV_SCAN_IND`
+        -   Used by beacons to advertise additional data via a scan response when packet length is insufficient
+
+
+PDU Payload
+#####################
+
+The PDU Payload is divided into two parts:
+
+.. list-table::
+    :align: center
+    :widths: 10 50 10 30
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+        -   Byte Size
+        -   Notes
+    *   -   1
+        -   Advertisement Address, **AdvA**
+        -   6
+        -   The 48-bit Bluetooth address of the advertiser
+    *   -   2
+        -   Advertisement Data, **AdvData**
+        -   0-31
+        -   Consists of multiple Advertisement Data Structures
+
+The Advertisement Address can be either a:
+
+.. list-table::
+    :align: center
+    :widths: 40 60
+    :header-rows: 1
+
+    *   -   Type
+        -   Description
+    *   -   Public Address
+        -   A globally unique fixed device address that manufacturers must register and pay fees to IEEE for
+    *   -   Random Address
+        -   A randomly generated address
+
+Random addresses are further divided into two categories:
+
+.. list-table::
+    :align: center
+    :widths: 40 60
+    :header-rows: 1
+
+    *   -   Type
+        -   Description
+    *   -   Random Static Address
+        -   Can be either fixed in firmware or randomly generated at startup but must not change during operation. Often used as an alternative to a Public Address.
+    *   -   Random Private Address
+        -   Periodically changes to prevent device tracking.
+
+For devices using random private addresses to communicate with trusted devices, an Identity Resolving Key (IRK) should be used to generate the random address. Devices with the same IRK can resolve and obtain the true address. There are two types of random private addresses:
+
+.. list-table::
+    :align: center
+    :widths: 40 60
+    :header-rows: 1
+
+    *   -   Type
+        -   Description
+    *   -   Resolvable Random Private Address
+        -   Can be resolved with an IRK to obtain the device’s true address
+    *   -   Non-resolvable Random Private Address
+        -   Completely random and rarely used, as it cannot be resolved and is only meant to prevent tracking
+
+Let's look at the **advertising data**. The format of an advertising data structure is defined as follows:
+
+.. list-table::
+    :align: center
+    :widths: 10 40 20 30
+    :header-rows: 1
+
+    *   -   No.
+        -   Name
+        -   Byte Size
+        -   Notes
+    *   -   1
+        -   AD Length
+        -   1
+        -
+    *   -   2
+        -   AD Type
+        -   n
+        -   Most types take 1 byte
+    *   -   3
+        -   AD Data
+        -   (AD Length - n)
+        -
+
+
+Basic Concepts of Scanning
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Similar to the advertising process, scanning also raises three questions:
+
+1. Where to scan? (Where?)
+2. When to scan and for how long? (When?)
+3. What to do during scanning? (What?)
+
+For Bluetooth LE 4.2 devices, the advertiser only sends data on the advertising channels, which are channels 37-39. For Bluetooth LE 5.0 devices, if the advertiser has enabled extended advertising, it sends `ADV_EXT_IND` on the primary advertising channels and `AUX_ADV_IND` on the secondary advertising channels.
+Thus, for Bluetooth LE 4.2 devices, scanners only need to receive advertising data on advertising channels. For Bluetooth LE 5.0 devices, scanners must first receive the `ADV_EXT_IND` on the primary advertising channels and, if it indicates a secondary channel, move to the corresponding secondary channel to receive the `AUX_ADV_IND`.
+
+
+Scan Window and Scan Interval
+#####################################
+
+The second question refers to the concepts of the Scan Window and the Scan Interval.
+
+- **Scan Window**: the duration for which the scanner continuously receives packets on a single RF channel. For example, if the scan window is set to 50 ms, the scanner continuously scans for 50 ms on each RF channel.
+
+- **Scan Interval**: the time between the start of two consecutive scan windows, which means the scan interval is always greater than or equal to the scan window.
+
+The diagram below illustrates the process of a scanner receiving advertising packets on a timeline. The scanner's scan interval is 100 ms, and the scan window is 50 ms; the advertiser's advertising interval is 50 ms, and the duration of the advertising packet transmission is for illustrative purposes only. As shown, the first scan window corresponds to channel 37, where the scanner successfully receives the advertiser's first broadcasting packet sent on channel 37, and this pattern continues.
+
+.. figure:: ../../../../_static/ble/ble-advertise-and-scan-sequence.png
+    :align: center
+    :scale: 30%
+    :alt: Advertising and Scanning Timing Diagram
+
+    Advertising and Scanning Timing Diagram
+
+
+.. _scan_request_and_scan_response:
+
+Scan Request and Scan Response
+#####################################
+
+From the current introduction, it might seem that the advertiser only transmits and the scanner only receives during the advertising process. However, scanning behavior is divided into two types:
+
+- **Passive Scanning**:
+    - The scanner only receives advertising packets.
+- **Active Scanning**:
+    - After receiving an advertising packet, the scanner sends a scan request to a scannable advertiser.
+
+When a scannable advertiser receives a scan request, it sends a scan response packet, providing more advertising information to the interested scanner. The structure of the scan response packet is identical to the advertising packet, with the difference being the PDU type in the PDU header.
+
+In scenarios where the advertiser operates in scannable advertising mode and the scanner in active scanning mode, the data transmission timing between the advertiser and the scanner becomes more complex. For the scanner, after a scan window ends, it briefly switches to TX mode to send a scan request, then quickly switches back to RX mode to receive a possible scan response. For the advertiser, after each advertising, it briefly switches to RX mode to receive any scan requests, and upon receiving one, it switches to TX mode to send the scan response.
+
+.. figure:: ../../../../_static/ble/ble-advertiser-rx-scan-request.png
+    :align: center
+    :scale: 30%
+    :alt: Scan Request Reception and Scan Response Transmission
+
+    Scan Request Reception and Scan Response Transmission
+
+
+Hands-On Practice
+--------------------------
+
+After learning the relevant concepts of advertising and scanning, let's apply this knowledge in practice using the :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` example to create a simple beacon device.
+
+
+Prerequisites
+^^^^^^^^^^^^^^^^^^^^^^^
+
+1. An {IDF_TARGET_NAME} development board
+2. ESP-IDF development environment
+3. The **nRF Connect for Mobile** app installed on your phone
+
+If you haven't set up the ESP-IDF development environment yet, please refer to :doc:`IDF Get Started <../../../get-started/index>`.
+
+
+Try It Out
+^^^^^^^^^^^^^^^^^^^^^^
+
+
+Building and Flashing
+##########################
+
+
+The reference example for this tutorial is :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>`.
+
+You can navigate to the example directory using the following command:
+
+.. code-block:: shell
+
+    $ cd <ESP-IDF Path>/examples/bluetooth/ble_get_started/nimble/NimBLE_Beacon
+
+Please replace `<ESP-IDF Path>` with your local ESP-IDF folder path. Then, you can open the NimBLE_Beacon project using VSCode or another IDE you prefer. For example, after navigating to the example directory via the command line, you can open the project in VSCode using the following command:
+
+.. code-block:: shell
+
+    $ code .
+
+Next, enter the ESP-IDF environment in the command line and set the target chip:
+
+.. code-block:: shell
+
+    $ idf.py set-target <chip-name>
+
+You should see messages like:
+
+.. code-block:: shell
+
+    ...
+    -- Configuring done
+    -- Generating done
+    -- Build files have been written to ...
+
+These messages indicate that the chip has been successfully configured. Then, connect the development board to your computer and run the following command to build the firmware, flash it to the board, and monitor the serial output from the {IDF_TARGET_NAME} development board:
+
+.. code-block:: shell
+
+    $ idf.py flash monitor
+
+You should see messages like:
+
+.. code-block:: shell
+
+    ...
+    main_task: Returned from app_main()
+
+Wait until the notification ends.
+
+
+Viewing Beacon Device Information
+#########################################
+
+.. _nimble_beacon_details:
+
+Open the **nRF Connect for Mobile** app on your phone, go to the **SCANNER** tab, and pull down to refresh. Locate the NimBLE_Beacon device, as shown in the figure below.
+
+.. figure:: ../../../../_static/ble/ble-scan-list-nimble-beacon.jpg
+    :align: center
+    :scale: 30%
+    :alt: NimBLE Beacon
+
+    Locate NimBLE Beacon Device
+
+If the device list is long, it is recommended to filter by the keyword NimBLE in the device name to quickly find the NimBLE_Beacon device.
+
+You will notice that the NimBLE Beacon device contains rich information, including the Espressif website (this demonstrates the beacon advertising feature). Click the **RAW** button in the lower-right corner to view the raw advertising packet data, as shown below.
+
+.. figure:: ../../../../_static/ble/ble-adv-packet-raw-data.jpg
+    :align: center
+    :scale: 30%
+    :alt: ADV Packet Raw Data
+
+    Advertising Packet Raw Data
+
+**Details** table summarizes all advertising data structures in the advertising data packet and the scan response data packet:
+
+.. list-table::
+    :align: center
+    :widths: 30 10 10 30 20
+    :header-rows: 1
+
+    *   -   Name
+        -   Length
+        -   Type
+        -   Raw Data
+        -   Resolved Information
+    *   -   Flags
+        -   2 Bytes
+        -   `0x01`
+        -   `0x06`
+        -   General Discoverable, BR/EDR Not Supported
+    *   -   Complete Local Device Name
+        -   14 Bytes
+        -   `0x09`
+        -   `0x4E696D424C455F426561636F6E`
+        -   NimBLE_Beacon
+    *   -   TX Power Level
+        -   2 Bytes
+        -   `0x0A`
+        -   `0x09`
+        -   9 dBm
+    *   -   Appearance
+        -   3 Bytes
+        -   `0x19`
+        -   `0x0002`
+        -   Generic Tag (Generic category)
+    *   -   LE Role
+        -   2 Bytes
+        -   `0x1C`
+        -   `0x00`
+        -   Only Peripheral Role supported
+    *   -   LE Bluetooth Device Address
+        -   8 Bytes
+        -   `0x1B`
+        -   `0x46F506BDF5F000`
+        -   `F0:F5:BD:06:F5:46`
+    *   -   URI
+        -   17 Bytes
+        -   `0x24`
+        -   `0x172F2F6573707265737369662E636F6D`
+        -   `https://espressif.com`
+
+It is worth mentioning that the total length of the first five advertising data structures is 28 bytes, leaving only 3 bytes of space in the advertising data packet, which is not enough to accommodate the last two data structures. Therefore, the last two advertising data structures must be placed in the scan response data packet.
+
+You may also notice that the Raw Data for the Device Appearance is `0x0002`, while in the code, the definition for Generic Tag is `0x0200`. Additionally, the Raw Data for the Device Address appears to be completely reversed, except for the last byte (`0x00`). This is because Bluetooth LE air packets follow a little-endian transmission order, meaning the lower bytes are placed at the front.
+
+Also, note that the **nRF Connect for Mobile** app does not provide a **CONNECT** button to connect to this device, which aligns with our expectations since a Beacon device is inherently non-connectable. Now, let's dive into the code details to see how such a Beacon device is implemented.
+
+
+Code Explanation
+---------------------------
+
+
+Project Structure Overview
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _nimble_beacon_project_structure:
+
+The root directory of :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` is roughly divided into the following parts:
+
+- `README*.md`
+    - Documentation for the project
+- `sdkconfig.defaults*`
+    - Default configurations for different chip development boards
+- `CMakeLists.txt`
+    - Used to include the ESP-IDF build environment
+- `main`
+    - The main project folder containing the source code, header files, and build configurations
+
+
+Program Behavior Overview
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _nimble_beacon_program_behavior:
+
+Before diving into the code details, let's first get a macro understanding of the program behavior.
+
+First, we initialize the various modules used in the program, mainly including NVS Flash, the NimBLE Host Stack, and the GAP service.
+
+After the NimBLE Host Stack synchronizes with the Bluetooth controller, we confirm the Bluetooth address is available, then initiate an undirected, non-connectable, and scannable advertisement.
+
+The device remains in advertising mode continuously until a reboot occurs.
+
+
+Entry Function
+^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _nimble_beacon_entry_point:
+
+As with other projects, the entry function of the application is the `app_main` function in the `main/main.c` file, where we typically initialize the modules. In this example, we mainly do the following:
+
+1. Initialize NVS Flash and the NimBLE Host Stack
+2. Initialize the GAP service
+3. Start the FreeRTOS task for the NimBLE Host Stack
+
+The {IDF_TARGET_NAME} Bluetooth stack uses NVS Flash to store related configurations, so before initializing the Bluetooth stack, we must call the `nvs_flash_init` API to initialize NVS Flash. In some cases, we may need to call the `nvs_flash_erase` API to erase NVS Flash before initialization.
+
+.. code-block:: C
+
+    void app_main(void) {
+        ...
+
+        /* NVS flash initialization */
+        ret = nvs_flash_init();
+        if (ret == ESP_ERR_NVS_NO_FREE_PAGES ||
+            ret == ESP_ERR_NVS_NEW_VERSION_FOUND) {
+            ESP_ERROR_CHECK(nvs_flash_erase());
+            ret = nvs_flash_init();
+        }
+        if (ret != ESP_OK) {
+            ESP_LOGE(TAG, "failed to initialize nvs flash, error code: %d ", ret);
+            return;
+        }
+
+        ...
+    }
+
+Next, you can call `nimble_port_init` API to initialize NimBLE host stack.
+
+.. code-block:: C
+
+    void app_main(void) {
+        ...
+
+        /* NimBLE host stack initialization */
+        ret = nimble_port_init();
+        if (ret != ESP_OK) {
+            ESP_LOGE(TAG, "failed to initialize nimble stack, error code: %d ",
+                    ret);
+            return;
+        }
+
+        ...
+    }
+
+Then, we call the `gap_init` function defined in the `gap.c` file to initialize the GAP service and set the device name and appearance.
+
+.. code-block:: C
+
+    void app_main(void) {
+        ...
+
+        /* GAP service initialization */
+        rc = gap_init();
+        if (rc != 0) {
+            ESP_LOGE(TAG, "failed to initialize GAP service, error code: %d", rc);
+            return;
+        }
+
+        ...
+    }
+
+Next, we configure the NimBLE host stack, which mainly involves setting some callback functions, including callbacks for when the stack is reset and when synchronization is complete, and then saving the configuration.
+
+.. code-block:: C
+
+    static void nimble_host_config_init(void) {
+        /* Set host callbacks */
+        ble_hs_cfg.reset_cb = on_stack_reset;
+        ble_hs_cfg.sync_cb = on_stack_sync;
+        ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
+
+        /* Store host configuration */
+        ble_store_config_init();
+    }
+
+    void app_main(void) {
+        ...
+
+        /* NimBLE host configuration initialization */
+        nimble_host_config_init();
+
+        ...
+    }
+
+Finally, start the FreeRTOS thread for the NimBLE host stack.
+
+.. code-block:: C
+
+    static void nimble_host_task(void *param) {
+        /* Task entry log */
+        ESP_LOGI(TAG, "nimble host task has been started!");
+
+        /* This function won't return until nimble_port_stop() is executed */
+        nimble_port_run();
+
+        /* Clean up at exit */
+        vTaskDelete(NULL);
+    }
+
+    void app_main(void) {
+        ...
+
+        /* Start NimBLE host task thread and return */
+        xTaskCreate(nimble_host_task, "NimBLE Host", 4*1024, NULL, 5, NULL);
+
+        ...
+    }
+
+
+Start Advertising
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _nimble_beacon_start_advertising:
+
+When developing applications using the NimBLE host stack, the programming model is event-driven.
+
+For example, after the NimBLE host stack synchronizes with the Bluetooth controller, a synchronization completion event will be triggered, invoking the `ble_hs_cfg.sync_cb` function. When setting up the callback function, we point the function pointer to the `on_stack_sync` function, which is the actual function called upon synchronization completion.
+
+In the `on_stack_sync` function, we call the `adv_init` function to initialize advertising operations. In `adv_init`, we first call the `ble_hs_util_ensure_addr` API to confirm that a usable Bluetooth address is available. Then, we call the `ble_hs_id_infer_auto` API to obtain the optimal Bluetooth address type.
+
+.. code-block:: C
+
+    static void on_stack_sync(void) {
+        /* On stack sync, do advertising initialization */
+        adv_init();
+    }
+
+    void adv_init(void) {
+        ...
+
+        /* Make sure we have proper BT identity address set */
+        rc = ble_hs_util_ensure_addr(0);
+        if (rc != 0) {
+            ESP_LOGE(TAG, "device does not have any available bt address!");
+            return;
+        }
+
+        /* Figure out BT address to use while advertising */
+        rc = ble_hs_id_infer_auto(0, &own_addr_type);
+        if (rc != 0) {
+            ESP_LOGE(TAG, "failed to infer address type, error code: %d", rc);
+            return;
+        }
+
+        ...
+    }
+
+Next, we copy the Bluetooth address data from the NimBLE stack's memory space into the local `addr_val` array, preparing it for subsequent use.
+
+.. code-block:: C
+
+    void adv_init(void) {
+        ...
+
+        /* Copy device address to addr_val */
+        rc = ble_hs_id_copy_addr(own_addr_type, addr_val, NULL);
+        if (rc != 0) {
+            ESP_LOGE(TAG, "failed to copy device address, error code: %d", rc);
+            return;
+        }
+        format_addr(addr_str, addr_val);
+        ESP_LOGI(TAG, "device address: %s", addr_str);
+
+        ...
+    }
+
+Finally, we call the `start_advertising` function to initiate advertising. Within the `start_advertising` function, we first populate the advertising data structures, including the advertising flags, complete device name, transmission power level, device appearance, and LE role, into the advertising packet as follows:
+
+.. code-block:: C
+
+    static void start_advertising(void) {
+        /* Local variables */
+        int rc = 0;
+        const char *name;
+        struct ble_hs_adv_fields adv_fields = {0};
+
+        ...
+
+        /* Set advertising flags */
+        adv_fields.flags = BLE_HS_ADV_F_DISC_GEN | BLE_HS_ADV_F_BREDR_UNSUP;
+
+        /* Set device name */
+        name = ble_svc_gap_device_name();
+        adv_fields.name = (uint8_t *)name;
+        adv_fields.name_len = strlen(name);
+        adv_fields.name_is_complete = 1;
+
+        /* Set device tx power */
+        adv_fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO;
+        adv_fields.tx_pwr_lvl_is_present = 1;
+
+        /* Set device appearance */
+        adv_fields.appearance = BLE_GAP_APPEARANCE_GENERIC_TAG;
+        adv_fields.appearance_is_present = 1;
+
+        /* Set device LE role */
+        adv_fields.le_role = BLE_GAP_LE_ROLE_PERIPHERAL;
+        adv_fields.le_role_is_present = 1;
+
+        /* Set advertiement fields */
+        rc = ble_gap_adv_set_fields(&adv_fields);
+        if (rc != 0) {
+            ESP_LOGE(TAG, "failed to set advertising data, error code: %d", rc);
+            return;
+        }
+
+        ...
+    }
+
+The `ble_hs_adv_fields` structure predefines some commonly used advertising data types. After completing the data setup, we can enable the corresponding advertising data structures by setting the relevant is_present field to 1 or by assigning a non-zero value to the corresponding length field (len). For example, in the code above, we configure the device's transmission power with `adv_fields.tx_pwr_lvl = BLE_HS_ADV_TX_PWR_LVL_AUTO;`, and then enable that advertising data structure by setting `adv_fields.tx_pwr_lvl_is_present = 1;`. If we only configure the transmission power without setting the corresponding is_present field, the advertising data structure becomes invalid. Similarly, we configure the device name with `adv_fields.name = (uint8_t *)name;` and set the name's length with `adv_fields.name_len = strlen(name);` to add the device name as an advertising data structure to the advertising packet. If we only configure the device name without specifying its length, the advertising data structure will also be invalid.
+
+Finally, we call the `ble_gap_adv_set_fields` API to finalize the setup of the advertising data structures in the advertising packet.
+
+In the same way, we can fill in the device address and URI into the scan response packet as follows:
+
+.. code-block:: C
+
+    static void start_advertising(void) {
+        ...
+
+        struct ble_hs_adv_fields rsp_fields = {0};
+
+        ...
+
+        /* Set device address */
+        rsp_fields.device_addr = addr_val;
+        rsp_fields.device_addr_type = own_addr_type;
+        rsp_fields.device_addr_is_present = 1;
+
+        /* Set URI */
+        rsp_fields.uri = esp_uri;
+        rsp_fields.uri_len = sizeof(esp_uri);
+
+        /* Set scan response fields */
+        rc = ble_gap_adv_rsp_set_fields(&rsp_fields);
+        if (rc != 0) {
+            ESP_LOGE(TAG, "failed to set scan response data, error code: %d", rc);
+            return;
+        }
+
+        ...
+    }
+
+Finally, we set the advertising parameters and initiate the advertising by calling the `ble_gap_adv_start` API.
+
+.. code-block:: C
+
+    static void start_advertising(void) {
+        ...
+
+        struct ble_gap_adv_params adv_params = {0};
+
+        ...
+
+        /* Set non-connetable and general discoverable mode to be a beacon */
+        adv_params.conn_mode = BLE_GAP_CONN_MODE_NON;
+        adv_params.disc_mode = BLE_GAP_DISC_MODE_GEN;
+
+        /* Start advertising */
+        rc = ble_gap_adv_start(own_addr_type, NULL, BLE_HS_FOREVER, &adv_params,
+                            NULL, NULL);
+        if (rc != 0) {
+            ESP_LOGE(TAG, "failed to start advertising, error code: %d", rc);
+            return;
+        }
+        ESP_LOGI(TAG, "advertising started!");
+    }
+
+
+Summary
+---------------------
+
+Through this tutorial, you have learned the basic concepts of advertising and scanning, and you mastered the method of building a Bluetooth LE Beacon device using the NimBLE host stack through the :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` example.
+
+You can try to modify the data in the example and observe the changes in the **nRF Connect for Mobile** app. For instance, you might modify the `adv_fields` or `rsp_fields` structures to change the populated advertising data structures, or swap the advertising data structures between the advertising packet and the scan response packet. However, keep in mind that the maximum size for the advertising data in both the advertising packet and the scan response packet is 31 bytes; if the size of the advertising data structure exceeds this limit, calling the `ble_gap_adv_start` API will fail.
diff --git a/docs/en/api-guides/ble/get-started/ble-introduction.rst b/docs/en/api-guides/ble/get-started/ble-introduction.rst
index 2630c641569..adc839ff059 100644
--- a/docs/en/api-guides/ble/get-started/ble-introduction.rst
+++ b/docs/en/api-guides/ble/get-started/ble-introduction.rst
@@ -1 +1,342 @@
-.. include:: ../../../../zh_CN/api-guides/ble/get-started/ble-introduction.rst
+Introduction
+===================
+
+:link_to_translation:`zh_CN:[中文]`
+
+This document is the first tutorial in the Getting Started series on Bluetooth Low Energy (Bluetooth LE). It introduces the basic concepts of Bluetooth LE and guides users through flashing a Bluetooth LE example onto an {IDF_TARGET_NAME} development board. The tutorial also instructs users on how to use the **nRF Connect for Mobile** app to control an LED and read heart rate data from the board. The tutorial offers a hands-on approach to understanding Bluetooth LE and working with the ESP-IDF framework for Bluetooth LE applications.
+
+
+Learning Objectives
+-----------------------
+
+- Understand the layered architecture of Bluetooth LE
+- Learn the basic functions of each layer in Bluetooth LE
+- Understand the functions of GAP and GATT/ATT layers
+- Master the method of flashing Bluetooth LE examples on {IDF_TARGET_NAME} development board and interacting with it via a mobile phone
+
+
+Preface
+-----------------
+
+Most people have experienced Bluetooth technology in their daily lives—perhaps you are even wearing Bluetooth headphones right now, listening to audio from your phone or computer. However, audio transmission is a typical use case of Bluetooth Classic, while Bluetooth LE is a Bluetooth protocol that is not compatible with Bluetooth Classic and was introduced in Bluetooth 4.0. As the name suggests, Bluetooth LE is a low-power Bluetooth protocol with a lower data transfer rate compared to Bluetooth Classic. It is typically used in data communication for the Internet of Things (IoT), such as smart switches or sensors, as shown in the example in this tutorial. However, before diving into the example project, let's first understand the basic concepts of Bluetooth LE to help you get started.
+
+
+Layered Architecture of Bluetooth LE
+------------------------------------
+
+The Bluetooth LE protocol defines a three-layer software architecture, listed from top to bottom:
+
+- Application Layer
+- Host Layer
+- Controller Layer
+
+The Application Layer is where applications are built using Bluetooth LE as the underlying communication technology, relying on the API interfaces provided by the Host Layer.
+
+The Host Layer implements low-level Bluetooth protocols such as L2CAP, GATT/ATT, SMP, and GAP, providing API interfaces to the Application Layer above and communicating with the Controller Layer below via the Host Controller Interface (HCI).
+
+The Controller Layer consists of the Physical Layer (PHY) and the Link Layer (LL), which directly interacts with the hardware below and communicates with the Host Layer above through the HCI.
+
+It’s worth mentioning that the Bluetooth Core Specification allows the Host Layer and Controller Layer to be physically separated, in which case the HCI is realized as a physical interface, including SDIO, USB, and UART, among others. However, the Host and Controller Layers can also coexist on the same chip for higher integration, in which case the HCI is referred to as the Virtual Host Controller Interface (VHCI). Generally, the Host Layer and Controller Layer together make up the Bluetooth LE Stack.
+
+The diagram below shows the layered structure of Bluetooth LE.
+
+.. figure:: ../../../../_static/ble/ble-architecture.png
+    :align: center
+    :scale: 50%
+    :alt: Bluetooth LE Layered Architecture
+
+    Layered Architecture of Bluetooth LE
+
+As an application developer, during the development process, we primarily interact with the APIs provided by the Host Layer, which requires a certain understanding of the Bluetooth protocols within the Host Layer. Next, we will introduce the basic concepts of the GAP and GATT/ATT layers from two perspectives: connection and data exchange.
+
+
+GAP Layer - Defining Device Connections
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The GAP (Generic Access Profile) layer defines the connection behaviors between Bluetooth LE devices and the roles they play in the connection.
+
+
+GAP States and Roles
+#######################
+
+The GAP layer defines three connection states and five different device roles, as follows:
+
+- Idle
+    - In this state, the device is in a standby state without any role.
+- Device Discovery
+    - Advertiser
+    - Scanner
+    - Initiator
+- Connection
+    - Peripheral
+    - Central
+
+The advertising data contains information such as the device address, indicating the advertiser's presence to external devices and informing them whether they are connectable. A scanner continuously receives advertising packets in the environment. If a scanner detects a connectable advertiser and wishes to establish a connection, it can switch its role to initiator. When the initiator receives another advertising data from the same advertiser, it immediately sends a Connection Request. If the advertiser has not enabled a Filter Accept List (also known as White List), or if the initiator is included in the advertiser's Filter Accept List, the connection will be successfully established.
+
+Once connected, the original advertiser becomes the peripheral device (formerly known as the slave device), and the original scanner or connection initiator becomes the central device (formerly known as the master device).
+
+The diagram below shows the relationship between the GAP roles.
+
+.. figure:: ../../../../_static/ble/ble-gap-state-diagram.png
+    :align: center
+    :scale: 50%
+    :alt: GAP roles relationship
+
+    GAP Roles Relationship
+
+
+Bluetooth LE Network Topology
+################################
+
+Bluetooth LE devices can connect to multiple Bluetooth LE devices simultaneously, playing multiple peripheral or central device roles, or acting as both a peripheral and a central device at the same time. For example, a Bluetooth LE gateway can act as a central device to connect with peripheral devices such as smart switches, while also functioning as a peripheral device to connect with central devices like smartphones, serving as a data intermediary.
+
+In a Bluetooth LE network, if all devices are connected to at least one other device and each plays only one type of role, this is referred to as a Connected Topology. If at least one device plays both peripheral and central roles simultaneously, the network is called a Multi-role Topology.
+
+Bluetooth LE also supports a connectionless network topology known as Broadcast Topology. In such a network, there are two roles: the device sending the data is called the Broadcaster, and the device receiving the data is called the Observer. The broadcaster only sends data and does not accept connections, while the observer only receives advertising data and does not initiate connections. For example, in a network where a sensor's data is shared by multiple devices, maintaining multiple connections can be costly, so advertising sensor data to all devices in the network is a more suitable approach.
+
+
+Learn More
+##################
+
+If you want to learn more about device discovery and connection, please refer to :doc:`Device Discovery <./ble-device-discovery>` and :doc:`Connection <./ble-connection>`.
+
+
+GATT/ATT Layer - Data Representation and Exchange
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. _gatt_att_introduction:
+
+The GATT/ATT layer defines the methods for data exchange between devices once they are connected, including how data is represented and the process of exchanging it.
+
+
+ATT Layer
+#############
+
+ATT stands for Attribute Protocol (ATT), which defines a basic data structure called **Attribute** and data access methods based on a server/client architecture.
+
+In simple terms, data is stored on a server as attributes, awaiting access by the client. For example, in a smart switch, the switch state is stored in the Bluetooth chip (server) of the smart switch as data in the form of an attribute. The user can then access the switch state attribute stored in the smart switch's Bluetooth chip (server) via their smartphone (client), to either read the current state (read access) or open and close the switch (write access).
+
+The attribute data structure typically consists of the following three parts:
+
+- Handle
+- Type
+- Value
+- Permissions
+
+In the protocol stack implementation, attributes are generally managed in an array-like structure called an **Attribute Table**. The index of an attribute in this table is its handle, usually an unsigned integer.
+
+The type of an attribute is represented by a UUID and can be divided into three categories: 16-bit, 32-bit, and 128-bit UUIDs. The 16-bit UUIDs are universally defined by the Bluetooth Special Interest Group (Bluetooth SIG) and can be found in their publicly available `Assigned Numbers <https://www.bluetooth.com/specifications/assigned-numbers/>`__ document. The other two lengths of UUIDs are used for vendor-defined attribute types, with the 128-bit UUID being the most commonly used.
+
+
+GATT Layer
+###############
+
+GATT stands for Generic Attribute Profile (GATT), and it builds on ATT by defining the following three concepts:
+
+- Characteristic
+- Service
+- Profile
+
+The hierarchical relationship between these three concepts is shown in the diagram below.
+
+.. figure:: ../../../../_static/ble/ble-gatt-architecture.png
+    :align: center
+    :scale: 30%
+    :alt: GATT Hierarchical Architecture
+
+    GATT Hierarchical Architecture
+
+.. _characteristic_structure:
+
+Both characteristics and services are composite data structures based on attributes. A characteristic is often described by two or more attributes, including:
+
+- Characteristic Declaration Attribute
+- Characteristic Value Attribute
+
+In addition, a characteristic may also include several optional Characteristic Descriptor Attributes.
+
+A service itself is also described by an attribute, called the Service Declaration Attribute. A service can contain one or more characteristics, with a dependency relationship between them. Additionally, a service can reference another service using the `Include` mechanism, reusing its characteristic definitions to avoid redundant definitions for common characteristics, such as device names or manufacturer information.
+
+A profile is a predefined set of services. A device that implements all the services defined in a profile is said to comply with that profile. For example, the Heart Rate Profile includes the Heart Rate Service and the Device Information Service. Thus, a device that implements both the Heart Rate Service and Device Information Service is considered compliant with the Heart Rate Profile.
+
+Broadly speaking, any device that stores and manages characteristics is called a GATT Server, while any device that accesses the GATT Server to retrieve characteristics is called a GATT Client.
+
+
+Learn More
+####################
+
+If you'd like to learn more about data representation and exchange, please refer to :doc:`Data Exchange <./ble-data-exchange>`.
+
+
+Hands-On Practice
+--------------------------
+
+
+After learning the basic concepts of Bluetooth LE, let's load a simple Bluetooth LE example onto the {IDF_TARGET_NAME} development board to experience the functionalities of LED control and heart rate data reading, and gain an intuitive understanding of Bluetooth LE technology.
+
+
+Prerequisites
+^^^^^^^^^^^^^^^^
+
+1. An {IDF_TARGET_NAME} development board
+2. ESP-IDF development environment
+3. The **nRF Connect for Mobile** app installed on your phone
+
+If you haven't set up the ESP-IDF development environment yet, please refer to :doc:`IDF Get Started <../../../get-started/index>`.
+
+
+Try It Out
+^^^^^^^^^^^^^^^^^^
+
+.. _nimble_gatt_server_practice:
+
+Building and Flashing
+##########################
+
+
+The reference example for this tutorial is :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>`.
+
+You can navigate to the example directory using the following command:
+
+.. code-block:: shell
+
+    $ cd <ESP-IDF Path>/examples/bluetooth/ble_get_started/nimble/NimBLE_GATT_Server
+
+Please replace `<ESP-IDF Path>` with your local ESP-IDF folder path. Then, you can open the NimBLE_GATT_Server project using VSCode or another IDE you prefer. For example, after navigating to the example directory via the command line, you can open the project in VSCode using the following command:
+
+.. code-block:: shell
+
+    $ code .
+
+Next, enter the ESP-IDF environment in the command line and set the target chip:
+
+.. code-block:: shell
+
+    $ idf.py set-target <chip-name>
+
+You should see messages like:
+
+.. code-block:: shell
+
+    ...
+    -- Configuring done
+    -- Generating done
+    -- Build files have been written to ...
+
+These messages indicate that the chip has been successfully configured. Then, connect the development board to your computer and run the following command to build the firmware, flash it to the board, and monitor the serial output from the {IDF_TARGET_NAME} development board:
+
+.. code-block:: shell
+
+    $ idf.py flash monitor
+
+You should see messages like:
+
+.. code-block:: shell
+
+    ...
+    main_task: Returned from app_main()
+    NimBLE_GATT_Server: Heart rate updated to 70
+
+The heart rate data will update at a frequency of about 1 Hz, fluctuating between 60 and 80.
+
+
+Connecting to the Development Board
+#######################################
+
+Now the development board is ready. Next, open the **nRF Connect for Mobile** app on your phone, refresh the **SCANNER** tab, and find the NimBLE_GATT device, as shown in the image below.
+
+.. figure:: ../../../../_static/ble/ble-get-started-connect-brief.jpg
+    :align: center
+    :scale: 20%
+    :alt: Device Scan
+
+    Device Scan
+
+If the device list is long, it is recommended to filter the device names using NimBLE as a keyword to quickly find the NimBLE_GATT device.
+
+Click on the **NimBLE_GATT** device entry to expand and view the detailed advertising data.
+
+.. figure:: ../../../../_static/ble/ble-get-started-connect-details.jpg
+    :align: center
+    :scale: 20%
+    :alt: Advertising Data Details
+
+    Advertising Data Details
+
+Click the **CONNECT** button on the right. While the phone is connecting, you can observe many connection-related log messages in the serial output of the development board. Then, the NimBLE_GATT tab will appear on the phone, and there should be a **CONNECTED** status in the upper left corner, indicating that the phone has successfully connected to the development board via the Bluetooth LE protocol. On the CLIENT subpage, you should be able to see four GATT services, as shown in the figure.
+
+.. figure:: ../../../../_static/ble/ble-get-started-gatt-services-list.jpg
+    :align: center
+    :scale: 20%
+    :alt: GATT Services List
+
+    GATT Services List
+
+The first two services are the GAP service and GATT service, which are foundational services in Bluetooth LE applications. The other two services are the Heart Rate Service and Automation IO Service, both defined by the Bluetooth SIG. They provide heart rate data reading and LED control functionality, respectively.
+
+Below the service names, you can see the corresponding UUIDs and the primary/secondary service designation. For example, the UUID for the Heart Rate Service is `0x180D`, which is a primary service. It’s important to note that the service names are derived from the UUIDs. In **nRF Connect for Mobile**, when implementing a GATT client, the developer preloads the database with services defined by the Bluetooth SIG or other customized services. Based on the GATT service UUID, service information is parsed. Therefore, if a service's UUID is not in the database, its information cannot be parsed, and the service name will be displayed as Unknown Service.
+
+
+Let’s Light Up the LED!
+###############################
+
+Now, let's try out the functionality of this example. First, click on the **Automation IO Service**, and you will see an LED characteristic under this service.
+
+.. figure:: ../../../../_static/ble/ble-get-started-automation-io-service-details.jpg
+    :align: center
+    :scale: 20%
+    :alt: Automation IO Service
+
+    Automation IO Service
+
+As shown in the figure, the UUID of this LED characteristic is a 128-bit vendor-specific UUID. Click the **UPLOAD** button on the right to perform a write operation on this characteristic, as shown in the figure.
+
+.. figure:: ../../../../_static/ble/ble-get-started-led-write.jpg
+    :align: center
+    :scale: 20%
+    :alt: Write to LED Characteristic Data
+
+    Write to LED Characteristic Data
+
+Select the **ON** option and send it. You should see the LED on the development board light up. Select the **OFF** option and send it, and you should observe the LED on the development board turning off again.
+
+If your development board does not have other LED except the one for the power indicator, you should be able to observe the corresponding status indication in the log output.
+
+
+Receiving Heart Rate Data
+#############################
+
+Next, click on the **Heart Rate Service**. You will see a Heart Rate Measurement characteristic under this service.
+
+.. figure:: ../../../../_static/ble/ble-get-started-heart-rate-service-details.jpg
+    :align: center
+    :scale: 20%
+    :alt: Heart Rate Service
+
+    Heart Rate Service
+
+The UUID of the Heart Rate Measurement characteristic is `0x2A37`, which is a Bluetooth SIG-defined characteristic. Click the download button on the right to perform a read operation on the heart rate characteristic. You should see the latest heart rate measurement data appear in the `Value` field of the characteristic data section, as shown in the figure.
+
+.. figure:: ../../../../_static/ble/ble-get-started-heart-rate-read.jpg
+    :align: center
+    :scale: 20%
+    :alt: Read Heart Rate Characteristic Data
+
+    Read Heart Rate Characteristic Data
+
+In the application, it is best for heart rate data to be synchronized to the GATT client immediately when the measurement is updated. To achieve this, we can click the **SUBSCRIPTION** button on the far right to request the heart rate characteristic to perform an indication operation. At this point, you should be able to see the heart rate measurement data continuously updating, as shown in the figure.
+
+.. figure:: ../../../../_static/ble/ble-get-started-heart-rate-indicate.jpg
+    :align: center
+    :scale: 20%
+    :alt: Subscribe to the heart rate characteristic data
+
+    Subscribe to Heart Rate Characteristic Data
+
+You might have noticed that under the heart rate characteristic, there is a descriptor named *Client Characteristic Configuration* (often abbreviated as CCCD), with a UUID of `0x2902`. When you click the subscribe button, the value of this descriptor changes, which indicates that the characteristic's indications are enabled. Indeed, this descriptor is used to indicate the status of notifications or indications for the characteristic data. When you unsubscribe, the descriptor's value changes to indicate that notifications and indications are disabled.
+
+
+Summary
+-----------
+
+Through this tutorial, you have learned about the layered architecture of Bluetooth LE, the basic functions of the host and controller layers in the Bluetooth LE protocol stack, and the roles of the GAP and GATT/ATT layers. Additionally, using the :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` example, you have mastered how to build and flash Bluetooth LE applications with the ESP-IDF framework, debug the application on your phone using **nRF Connect for Mobile**, remotely control the LED on the development board, and receive randomly generated heart rate data. You've taken the first step towards becoming a Bluetooth LE developer—congratulations!
diff --git a/docs/en/api-guides/ble/host-feature-support-status.rst b/docs/en/api-guides/ble/host-feature-support-status.rst
index 1900dca3a6f..75c5c4425ec 100644
--- a/docs/en/api-guides/ble/host-feature-support-status.rst
+++ b/docs/en/api-guides/ble/host-feature-support-status.rst
@@ -79,7 +79,7 @@ If none of our chip series meet your needs, please contact `customer support tea
       - |experimental|
       - |experimental|
     * -
-      - Advertising Channel Index
+      - Randomized Advertising Channel Indexing
       - |NA|
       - |NA|
     * -
diff --git a/docs/en/api-guides/ble/overview.rst b/docs/en/api-guides/ble/overview.rst
index e360d210cd4..9058f82c8a6 100644
--- a/docs/en/api-guides/ble/overview.rst
+++ b/docs/en/api-guides/ble/overview.rst
@@ -13,13 +13,13 @@ This document provides an architecture overview of the Bluetooth Low Energy (Blu
 
     {IDF_TARGET_NAME} supports Bluetooth 5.0 (LE) and is certified for Bluetooth LE 5.4.
 
-.. only:: esp32c2 or esp32c6 or esp32h2
+.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61
 
     {IDF_TARGET_NAME} supports Bluetooth 5.0 (LE) and is certified for Bluetooth LE 5.3.
 
 The Bluetooth LE stack in ESP-IDF is a layered architecture that enables Bluetooth functionality on {IDF_TARGET_NAME} chip series. The table below shows its architecture.
 
-.. only:: esp32 or esp32s3 or esp32c3 or esp32c6
+.. only:: esp32 or esp32s3 or esp32c3 or esp32c6 or esp32c5 or esp32c61
 
     .. figure:: ../../../_static/bluetooth-architecture.png
         :align: center
diff --git a/docs/en/api-guides/bootloader.rst b/docs/en/api-guides/bootloader.rst
index 58b7d9ee702..8c19b5535c1 100644
--- a/docs/en/api-guides/bootloader.rst
+++ b/docs/en/api-guides/bootloader.rst
@@ -3,16 +3,16 @@ Bootloader
 
 :link_to_translation:`zh_CN:[中文]`
 
-The ESP-IDF Software Bootloader performs the following functions:
+The ESP-IDF second stage bootloader performs the following functions:
 
 1. Minimal initial configuration of internal modules;
-2. Initialize :doc:`/security/flash-encryption` and/or :doc:`Secure </security/secure-boot-v2>` features, if configured;
+2. Initialize :doc:`/security/flash-encryption` and/or :doc:`Secure Boot </security/secure-boot-v2>` features, if configured;
 3. Select the application partition to boot, based on the partition table and ota_data (if any);
 4. Load this image to RAM (IRAM & DRAM) and transfer management to the image that was just loaded.
 
-Bootloader is located at the address {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} in the flash.
+ESP-IDF second stage bootloader is located at the address {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} in the flash.
 
-For a full description of the startup process including the ESP-IDF bootloader, see :doc:`startup`.
+For a full description of the startup process including the ESP-IDF second stage bootloader, see :doc:`startup`.
 
 .. _bootloader-compatibility:
 
@@ -50,7 +50,7 @@ SPI Flash Configuration
 
 Each ESP-IDF application or bootloader .bin file contains a header with :ref:`CONFIG_ESPTOOLPY_FLASHMODE`, :ref:`CONFIG_ESPTOOLPY_FLASHFREQ`, :ref:`CONFIG_ESPTOOLPY_FLASHSIZE` embedded in it. These are used to configure the SPI flash during boot.
 
-The :ref:`first-stage-bootloader` in ROM reads the :ref:`second-stage-bootloader` header information from flash and uses this information to load the rest of the :ref:`second-stage-bootloader` from flash. However, at this time the system clock speed is lower than configured and not all flash modes are supported. When the :ref:`second-stage-bootloader` then runs, it will reconfigure the flash using values read from the currently selected app binary's header (and NOT from the :ref:`second-stage-bootloader` header). This allows an OTA update to change the SPI flash settings in use.
+The :ref:`first-stage-bootloader` reads the :ref:`second-stage-bootloader` header information from flash and uses this information to load the rest of the :ref:`second-stage-bootloader` from flash. However, at this time the system clock speed is lower than configured and not all flash modes are supported. When the :ref:`second-stage-bootloader` then runs, it will reconfigure the flash using values read from the currently selected app binary's header (and NOT from the :ref:`second-stage-bootloader` header). This allows an OTA update to change the SPI flash settings in use.
 
 .. only:: esp32
 
diff --git a/docs/en/api-guides/build-system.rst b/docs/en/api-guides/build-system.rst
index af6de647347..0532114108f 100644
--- a/docs/en/api-guides/build-system.rst
+++ b/docs/en/api-guides/build-system.rst
@@ -131,7 +131,7 @@ For more detailed information about integrating ESP-IDF with CMake into an IDE,
 Setting up the Python Interpreter
 ---------------------------------
 
-ESP-IDF works well with Python version 3.8+.
+ESP-IDF works well with Python version 3.9+.
 
 ``idf.py`` and other Python scripts will run with the default Python interpreter, i.e., ``python``. You can switch to a different one like ``python3 $IDF_PATH/tools/idf.py ...``, or you can set up a shell alias or another script to simplify the command.
 
@@ -181,7 +181,7 @@ This example "myProject" contains the following elements:
 
 - A top-level project CMakeLists.txt file. This is the primary file which CMake uses to learn how to build the project; and may set project-wide CMake variables. It includes the file :idf_file:`/tools/cmake/project.cmake` which implements the rest of the build system. Finally, it sets the project name and defines the project.
 
-- "sdkconfig" project configuration file. This file is created/updated when ``idf.py menuconfig`` runs, and holds the configuration for all of the components in the project (including ESP-IDF itself). The ``sdkconfig`` file may or may not be added to the source control system of the project.
+- "sdkconfig" project configuration file. This file is created/updated when ``idf.py menuconfig`` runs, and holds the configuration for all of the components in the project (including ESP-IDF itself). The ``sdkconfig`` file may or may not be added to the source control system of the project. More information about this file can be found in the :ref:`sdkconfig file <sdkconfig-file>` section in the Configuration Guide.
 
 - "dependencies.lock" file contains the list of all managed components, and their versions, that are currently in used in the project. The ``dependencies.lock`` file is generated or updated automatically when IDF Component Manager is used to add or update project components. So this file should never be edited manually! If the project does not have ``idf_component.yml`` files in any of its components, ``dependencies.lock`` will not be created.
 
@@ -245,7 +245,9 @@ These variables all have default values that can be overridden for custom behavi
 
 - ``COMPONENTS``: A list of component names to build into the project. Defaults to all components found in the ``COMPONENT_DIRS`` directories. Use this variable to "trim down" the project for faster build times. Note that any component which "requires" another component via the REQUIRES or PRIV_REQUIRES arguments on component registration will automatically have it added to this list, so the ``COMPONENTS`` list can be very short.
 
-- ``BOOTLOADER_IGNORE_EXTRA_COMPONENT``: A list of components, placed in ``bootloader_components/``, that should be ignored by the bootloader compilation. Use this variable if a bootloader component needs to be included conditionally inside the project.
+- ``BOOTLOADER_IGNORE_EXTRA_COMPONENT``: Optional list of components, placed in ``bootloader_components/``, that should be ignored by the bootloader compilation. Use this variable if a bootloader component needs to be included conditionally inside the project.
+
+- ``BOOTLOADER_EXTRA_COMPONENT_DIRS``: Optional list of additional directories to search for components to be compiled as part of the bootloader. Please note that this is a build property.
 
 Any paths in these variables can be absolute paths, or set relative to the project directory.
 
@@ -362,7 +364,7 @@ The following component-specific variables are available for use inside componen
 
 The following variables are set at the project level, but available for use in component CMakeLists:
 
-- ``CONFIG_*``: Each value in the project configuration has a corresponding variable available in cmake. All names begin with ``CONFIG_``. :doc:`More information here </api-reference/kconfig>`.
+- ``CONFIG_*``: Each value in the project configuration has a corresponding variable available in cmake. All names begin with ``CONFIG_``. More information on how the project configuration works, please visit :ref:`Project Configuration Guide <project-configuration-guide>`.
 - ``ESP_PLATFORM``: Set to 1 when the CMake file is processed within the ESP-IDF build system.
 
 
@@ -428,7 +430,7 @@ These settings are found under the "Component Settings" menu when menuconfig is
 
 To create a component Kconfig file, it is easiest to start with one of the Kconfig files distributed with ESP-IDF.
 
-For an example, see `Adding conditional configuration`_.
+For an example, see `Adding conditional configuration`_. For a more detailed guide, see :ref:`Component Configuration Guide <component-configuration-guide>`.
 
 
 Preprocessor Definitions
@@ -461,7 +463,7 @@ When Writing a Component
 
 - ``PRIV_REQUIRES`` should be set to all components whose header files are #included from *any source files* in this component, unless already listed in ``REQUIRES``. Also, any component which is required to be linked in order for this component to function correctly.
 
-- The values of ``REQUIRES`` and ``PRIV_REQUIRES`` should not depend on any configuration choices (``CONFIG_xxx`` macros). This is because requirements are expanded before the configuration is loaded. Other component variables (like include paths or source files) can depend on configuration choices.
+- The values of ``REQUIRES`` and ``PRIV_REQUIRES`` should not depend on any configuration options (``CONFIG_xxx`` macros). This is because requirements are expanded before the configuration is loaded. Other component variables (like include paths or source files) can depend on configuration options.
 
 - Not setting either or both ``REQUIRES`` variables is fine. If the component has no requirements except for the `Common component requirements`_ needed for RTOS, libc, etc.
 
@@ -724,13 +726,14 @@ Note that ``project_include.cmake`` isn't necessary for the most common componen
 Take great care when setting variables or targets in a ``project_include.cmake`` file. As the values are included in the top-level project CMake pass, they can influence or break functionality across all components!
 
 
-KConfig.projbuild
+Kconfig.projbuild
 -----------------
 
-This is an equivalent to ``project_include.cmake`` for :ref:`component-configuration` KConfig files. If you want to include configuration options at the top level of menuconfig, rather than inside the "Component Configuration" sub-menu, then these can be defined in the KConfig.projbuild file alongside the ``CMakeLists.txt`` file.
+This is an equivalent to ``project_include.cmake`` for :ref:`component-configuration` Kconfig files. If you want to include configuration options at the top level of menuconfig, rather than inside the "Component Configuration" sub-menu, then these can be defined in the Kconfig.projbuild file alongside the ``CMakeLists.txt`` file.
 
-Take care when adding configuration values in this file, as they will be included across the entire project configuration. Where possible, it's generally better to create a KConfig file for :ref:`component-configuration`.
+Take care when adding configuration values in this file, as they will be included across the entire project configuration. Where possible, it's generally better to create a Kconfig file for :ref:`component-configuration`.
 
+For more information, see :ref:`Kconfig Files <kconfig-files>` section in the Configuration Guide.
 
 Wrappers to Redefine or Extend Existing Functions
 -------------------------------------------------
@@ -751,7 +754,7 @@ This mechanism is shown in the example :example:`build_system/wrappers`. Check :
 Override the Default Bootloader
 -------------------------------
 
-Thanks to the optional ``bootloader_components`` directory present in your ESP-IDf project, it is possible to override the default ESP-IDF bootloader. To do so, a new ``bootloader_components/main`` component should be defined, which will make the project directory tree look like the following:
+Thanks to the optional ``bootloader_components`` directory present in your ESP-IDF project, it is possible to override the default ESP-IDF bootloader. To do so, a new ``bootloader_components/main`` component should be defined, which will make the project directory tree look like the following:
 
     - myProject/
                  - CMakeLists.txt
@@ -765,7 +768,7 @@ Thanks to the optional ``bootloader_components`` directory present in your ESP-I
                  - build/
 
 
-Here the ``my_bootloader.c`` file becomes source code for the new bootloader, which means that it will need to perform all the required operations to set up and load the ``main`` application from flash.
+Here, the ``my_bootloader.c`` file becomes source code for the new bootloader, which means that it will need to perform all the required operations to set up and load the ``main`` application from flash.
 
 It is also possible to conditionally replace the bootloader depending on a certain condition, such as the target for example. This can be achieved thanks to the ``BOOTLOADER_IGNORE_EXTRA_COMPONENT`` CMake variable. This list can be used to tell the ESP-IDF bootloader project to ignore and not compile the given components present in ``bootloader_components``. For example, if one wants to use the default bootloader for ESP32 target, then ``myProject/CMakeLists.txt`` should look like the following::
 
@@ -781,13 +784,22 @@ It is important to note that this can also be used for any other bootloader comp
 
 See :example:`custom_bootloader/bootloader_override` for an example of overriding the default bootloader.
 
+Similarly to regular applications, it is possible to include external components, not placed in `bootloader_component`, as part of the bootloader build thanks to the build property ``BOOTLOADER_EXTRA_COMPONENT_DIRS``. It can either refer to a directory that contains several components, or refer to a single component. For example:
+
+    include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+    idf_build_set_property(BOOTLOADER_EXTRA_COMPONENT_DIRS "/path/to/extra/component/" APPEND)
+
+    project(main)
+
+See :example:`custom_bootloader/bootloader_extra_dir` for an example of adding extra components to the bootloader build.
 
 .. _config_only_component:
 
 Configuration-Only Components
 =============================
 
-Special components which contain no source files, only ``Kconfig.projbuild`` and ``KConfig``, can have a one-line ``CMakeLists.txt`` file which calls the function ``idf_component_register()`` with no arguments specified. This function will include the component in the project build, but no library will be built *and* no header files will be added to any included paths.
+Special components which contain no source files, only ``Kconfig.projbuild`` and ``Kconfig``, can have a one-line ``CMakeLists.txt`` file which calls the function ``idf_component_register()`` with no arguments specified. This function will include the component in the project build, but no library will be built *and* no header files will be added to any included paths.
 
 
 Debugging CMake
@@ -1065,6 +1077,10 @@ The best of these approaches for building an external project will depend on the
 Custom Sdkconfig Defaults
 =========================
 
+.. note::
+
+  For more detailed information about ``sdkconfig.defaults`` file, please visit :ref:`sdkconfig.defaults file <sdkconfig-defaults-file>` in Project Configuration section.
+
 For example projects or other projects where you don't want to specify a full sdkconfig configuration, but you do want to override some key values from the ESP-IDF defaults, it is possible to create a file ``sdkconfig.defaults`` in the project directory. This file will be used when creating a new config from scratch, or when any new config value hasn't yet been set in the ``sdkconfig`` file.
 
 To override the name of this file or to specify multiple files, set the ``SDKCONFIG_DEFAULTS`` environment variable or set ``SDKCONFIG_DEFAULTS`` in top-level ``CMakeLists.txt``. File names that are not specified as full paths are resolved relative to current project's directory.
@@ -1083,6 +1099,7 @@ If ``SDKCONFIG_DEFAULTS`` is used to override the name of defaults file/files, t
 
 For example, if ``SDKCONFIG_DEFAULTS="sdkconfig.defaults;sdkconfig_devkit1"``, and there is a file ``sdkconfig.defaults.esp32`` in the same folder, then the files will be applied in the following order: (1) sdkconfig.defaults (2) sdkconfig.defaults.esp32 (3) sdkconfig_devkit1.
 
+You can find more detailed information on how the project configuration works in the :ref:`Project Configuration Guide <project-configuration-guide>`. In the :ref:`Configuration Files Structure and Relationships <configuration-structure>`, you can find lower-level information about the configuration files.
 
 .. _flash_parameters:
 
@@ -1670,7 +1687,7 @@ Application Examples
 
 - :example:`build_system/wrappers` demonstrates how to use a linker feature to redefine or override any public function in both ESP-IDF and the bootloader, allowing modification or extension of a function's default behavior.
 
-- :example:`custom_bootloader/bootloader_override` demonstrates how to override the second-stage bootloader from a regular project, providing a custom bootloader that prints an extra message on startup, with the ability to conditionally override the bootloader based on certain conditions like target-dependency or KConfig options.
+- :example:`custom_bootloader/bootloader_override` demonstrates how to override the second stage bootloader from a regular project, providing a custom bootloader that prints an extra message on startup, with the ability to conditionally override the bootloader based on certain conditions like target-dependency or Kconfig options.
 
 - :example:`build_system/cmake/import_lib` demonstrates how to import and use third-party libraries using ExternalProject CMake module.
 
diff --git a/docs/en/api-guides/external-ram.rst b/docs/en/api-guides/external-ram.rst
index f8cebef14d4..44a8d3bd7f1 100644
--- a/docs/en/api-guides/external-ram.rst
+++ b/docs/en/api-guides/external-ram.rst
@@ -167,7 +167,7 @@ By applying the macro ``EXT_RAM_NOINIT_ATTR``, data could be moved from the inte
 
         The benefits of XiP from PSRAM is:
 
-        - PSRAM access speed may be faster than Flash access, so the overall application performance may be better. For example, if the PSRAM is an Octal mode (8-line-PSRAM) and is configured to 80 MHz, then it is faster than a Quad flash (4-line-flash) which is configured to 80 MHz.
+        - PSRAM access speed may be faster than flash access, so the overall application performance may be better. For example, if the PSRAM is an Octal mode (8-line PSRAM) and is configured to 80 MHz, then it is faster than a Quad flash (4-line flash) which is configured to 80 MHz.
 
         - The cache will not be disabled during an SPI1 flash operation, thus optimizing the code execution performance during SPI1 flash operations. For ISRs, ISR callbacks and data which might be accessed during this period, you do not need to place them in internal RAM, thus internal RAM usage can be optimized. This feature is useful for high throughput peripheral involved applications to improve the performance during SPI1 flash operations.
 
@@ -186,11 +186,11 @@ By applying the macro ``EXT_RAM_NOINIT_ATTR``, data could be moved from the inte
 
         .. only:: SOC_MMU_PER_EXT_MEM_TARGET
 
-            Because {IDF_TARGET_NAME} flash and PSRAM are using two separate SPI buses, moving flash content to PSRAM will actually increase the load of the PSRAM MSPI bus, so the exact impact on performance will be dependent on your app usage of PSRAM.
+            Since the flash and PSRAM in {IDF_TARGET_NAME} use two separate SPI buses, moving flash content to PSRAM will actually increase the load on the PSRAM MSPI bus. Therefore, the exact impact on performance will be dependent on your app usage of PSRAM.
 
-            For example, as the PSRAM bus speed could be faster than flash bus speed (e.g., if the PSRAM is a HEX (16-line-PSRAM on ESP32P4) and is configured to 200 Mhz, then it is much faster than a Quad flash (4-line-flash) which is configured to 80 MHz.).
+            The PSRAM bus can operate at a higher speed than the flash bus. For example, if the PSRAM is a HEX (16-line PSRAM on ESP32P4) running at 200 MHz, it is significantly faster than a Quad flash (4-line flash) running at 80 MHz.
 
-            If the instructions and data that are used to be in flash are not accessed very frequently, you should get better performance with this option enabled. We suggest doing performance profiling to determine how enabling this option will impact your system.
+            If the instructions and data previously stored in flash are not accessed frequently, then enabling this option could improve performance. It is recommended to conduct performance profiling to evaluate how this option will affect your system.
 
 Restrictions
 ============
@@ -213,7 +213,7 @@ External RAM use has the following restrictions:
 
     - In general, external RAM will not be used as task stack memory. :cpp:func:`xTaskCreate` and similar functions will always allocate internal memory for stack and task TCBs.
 
-The option :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` can be used to allow placing task stacks into external memory. In these cases :cpp:func:`xTaskCreateStatic` must be used to specify a task stack buffer allocated from external memory, otherwise task stacks will still be allocated from internal memory.
+The option :ref:`CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM` can be used to allow placing task stacks into external memory. In these cases :cpp:func:`xTaskCreateStatic` must be used to specify a task stack buffer allocated from external memory, otherwise task stacks will still be allocated from internal memory.
 
 
 Failure to Initialize
diff --git a/docs/en/api-guides/fatal-errors.rst b/docs/en/api-guides/fatal-errors.rst
index 31917081075..49228163a86 100644
--- a/docs/en/api-guides/fatal-errors.rst
+++ b/docs/en/api-guides/fatal-errors.rst
@@ -13,17 +13,17 @@ In certain situations, the execution of the program can not be continued in a we
 - CPU Exceptions: |CPU_EXCEPTIONS_LIST|
 - System level checks and safeguards:
 
-  .. list::
-
-     - :doc:`Interrupt watchdog <../api-reference/system/wdts>` timeout
-     - :doc:`Task watchdog <../api-reference/system/wdts>` timeout (only fatal if :ref:`CONFIG_ESP_TASK_WDT_PANIC` is set)
-     - Cache access error
-     :SOC_MEMPROT_SUPPORTED: - Memory protection fault
-     - Brownout detection event
-     - Stack overflow
-     - Stack smashing protection check
-     - Heap integrity check
-     - Undefined behavior sanitizer (UBSAN) checks
+    .. list::
+
+        - :doc:`Interrupt watchdog <../api-reference/system/wdts>` timeout
+        - :doc:`Task watchdog <../api-reference/system/wdts>` timeout (only fatal if :ref:`CONFIG_ESP_TASK_WDT_PANIC` is set)
+        - Cache access error
+        :SOC_MEMPROT_SUPPORTED: - Memory protection fault
+        - Brownout detection event
+        - Stack overflow
+        - Stack smashing protection check
+        - Heap integrity check
+        - Undefined behavior sanitizer (UBSAN) checks
 
 - Failed assertions, via ``assert``, ``configASSERT`` and similar macros.
 
@@ -32,7 +32,7 @@ This guide explains the procedure used in ESP-IDF for handling these errors, and
 Panic Handler
 -------------
 
-Every error cause listed in the `Overview`_ will be handled by the *panic handler*.
+Every error cause listed in the :ref:`Overview` will be handled by the *panic handler*.
 
 The panic handler will start by printing the cause of the error to the console. For CPU exceptions, the message will be similar to
 
@@ -46,29 +46,29 @@ For some of the system level checks (interrupt watchdog, cache access error), th
 
     Guru Meditation Error: Core 0 panic'ed (|CACHE_ERR_MSG|). Exception was unhandled.
 
-In all cases, the error cause will be printed in parentheses. See `Guru Meditation Errors`_ for a list of possible error causes.
+In all cases, the error cause will be printed in parentheses. See :ref:`Guru-Meditation-Errors` for a list of possible error causes.
 
 Subsequent behavior of the panic handler can be set using :ref:`CONFIG_ESP_SYSTEM_PANIC` configuration choice. The available options are:
 
 - Print registers and reboot (``CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT``) — default option.
 
-  This will print register values at the point of the exception, print the backtrace, and restart the chip.
+    This will print register values at the point of the exception, print the backtrace, and restart the chip.
 
 - Print registers and halt (``CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT``)
 
-  Similar to the above option, but halt instead of rebooting. External reset is required to restart the program.
+    Similar to the above option, but halt instead of rebooting. External reset is required to restart the program.
 
 - Silent reboot (``CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT``)
 
-  Do not print registers or backtrace, restart the chip immediately.
+    Do not print registers or backtrace, restart the chip immediately.
 
 - Invoke GDB Stub (``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB``)
 
-  Start GDB server which can communicate with GDB over console UART port. This option will only provide read-only debugging or post-mortem debugging. See `GDB Stub`_ for more details.
+    Start GDB server which can communicate with GDB over console UART port. This option will only provide read-only debugging or post-mortem debugging. See `GDB Stub`_ for more details.
 
 .. note::
 
-  The ``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB`` choice in the configuration option :ref:`CONFIG_ESP_SYSTEM_PANIC` is only available when the component ``esp_gdbstub`` is included in the build.
+    The ``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB`` choice in the configuration option :ref:`CONFIG_ESP_SYSTEM_PANIC` is only available when the component ``esp_gdbstub`` is included in the build.
 
 The behavior of the panic handler is affected by three other configuration options.
 
@@ -78,7 +78,7 @@ The behavior of the panic handler is affected by three other configuration optio
 
 - If :ref:`CONFIG_ESP_PANIC_HANDLER_IRAM` is disabled (disabled by default), the panic handler code is placed in flash memory, not IRAM. This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor risk, if the flash cache status is also corrupted during the crash.
 
-  If this option is enabled, the panic handler code (including required UART functions) is placed in IRAM, and hence will decrease the usable memory space in SRAM. But this may be necessary to debug some complex issues with crashes while flash cache is disabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception is triggered.
+    If this option is enabled, the panic handler code (including required UART functions) is placed in IRAM, and hence will decrease the usable memory space in SRAM. But this may be necessary to debug some complex issues with crashes while flash cache is disabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception is triggered.
 
 - If :ref:`CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS` is enabled (disabled by default) and set to a number higher than 0, the panic handler will delay the reboot for that amount of time in seconds. This can help if the tool used to monitor serial output does not provide a possibility to stop and examine the serial output. In that case, delaying the reboot will allow users to examine and debug the panic handler output (backtrace, etc.) for the duration of the delay. After the delay, the device will reboot. The reset reason is preserved.
 
@@ -134,7 +134,7 @@ Unless the ``CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT`` option is enabled, the pani
 
 .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA
 
-    ::
+    .. code-block:: none
 
         Core 0 register dump:
         PC      : 0x400e14ed  PS      : 0x00060030  A0      : 0x800d0805  A1      : 0x3ffb5030
@@ -148,7 +148,7 @@ Unless the ``CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT`` option is enabled, the pani
 
 .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
-    ::
+    .. code-block:: none
 
         Core  0 register dump:
         MEPC    : 0x420048b4  RA      : 0x420048b4  SP      : 0x3fc8f2f0  GP      : 0x3fc8a600
@@ -176,7 +176,7 @@ If :doc:`IDF Monitor <tools/idf-monitor>` is used, Program Counter values will b
 
 .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA
 
-    ::
+    .. code-block:: none
 
         Core 0 register dump:
         PC      : 0x400e14ed  PS      : 0x00060030  A0      : 0x800d0805  A1      : 0x3ffb5030
@@ -197,7 +197,7 @@ If :doc:`IDF Monitor <tools/idf-monitor>` is used, Program Counter values will b
 
 .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
-    ::
+    .. code-block:: none
 
         Core  0 register dump:
         MEPC    : 0x420048b4  RA      : 0x420048b4  SP      : 0x3fc8f2f0  GP      : 0x3fc8a600
@@ -220,7 +220,7 @@ If :doc:`IDF Monitor <tools/idf-monitor>` is used, Program Counter values will b
     Moreover, :doc:`IDF Monitor <tools/idf-monitor>` is also capable of generating and printing a backtrace thanks to the stack dump provided by the board in the panic handler.
     The output looks like this:
 
-    ::
+    .. code-block:: none
 
         Backtrace:
 
@@ -238,7 +238,7 @@ If :doc:`IDF Monitor <tools/idf-monitor>` is used, Program Counter values will b
 
     This option will let the compiler generate DWARF information for each function of the project. Then, when a CPU exception occurs, the panic handler will parse these data and determine the backtrace of the task that failed. The output looks like this:
 
-    ::
+    .. code-block:: none
 
         Backtrace: 0x42009e9a:0x3fc92120 0x42009ea6:0x3fc92120 0x42009ec2:0x3fc92130 0x42024620:0x3fc92150 0x40387d7c:0x3fc92160 0xfffffffe:0x3fc92170
 
@@ -256,7 +256,9 @@ GDB Stub
 
 If the ``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB`` option is enabled, the panic handler will not reset the chip when a fatal error happens. Instead, it will start a GDB remote protocol server, commonly referred to as GDB Stub. When this happens, a GDB instance running on the host computer can be instructed to connect to the {IDF_TARGET_NAME} UART port.
 
-If :doc:`IDF Monitor <tools/idf-monitor>` is used, GDB is started automatically when a GDB Stub prompt is detected on the UART. The output looks like this::
+If :doc:`IDF Monitor <tools/idf-monitor>` is used, GDB is started automatically when a GDB Stub prompt is detected on the UART. The output looks like this:
+
+.. code-block:: none
 
     Entering gdb stub now.
     $T0b#e6GNU gdb (crosstool-NG crosstool-ng-1.22.0-80-gff1f415) 7.10
@@ -286,16 +288,17 @@ The GDB prompt can be used to inspect CPU registers, local and static variables,
 
 RTC Watchdog Timeout
 --------------------
+
 {IDF_TARGET_RTCWDT_RTC_RESET:default="Not updated", esp32="RTCWDT_RTC_RESET", esp32s2="RTCWDT_RTC_RST", esp32s3="RTCWDT_RTC_RST", esp32c3="RTCWDT_RTC_RST", esp32c2="RTCWDT_RTC_RST", esp32c6="LP_WDT_SYS", esp32h2="LP_WDT_SYS", esp32p4="LP_WDT_SYS"}
 
-The RTC watchdog is used in the startup code to keep track of execution time and it also helps to prevent a lock-up caused by an unstable power source. It is enabled by default (see :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`). If the execution time is exceeded, the RTC watchdog will restart the system. In this case, the ROM bootloader will print a message with the ``RTC Watchdog Timeout`` reason for the reboot.
+The RTC watchdog is used in the startup code to keep track of execution time and it also helps to prevent a lock-up caused by an unstable power source. It is enabled by default (see :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`). If the execution time is exceeded, the RTC watchdog will restart the system. In this case, the first stage (ROM) bootloader will print a message with the ``RTC Watchdog Timeout`` reason for the reboot.
 
-::
+.. code-block:: none
 
     rst:0x10 ({IDF_TARGET_RTCWDT_RTC_RESET})
 
 
-The RTC watchdog covers the execution time from the first stage bootloader (ROM bootloader) to application startup. It is initially set in the ROM bootloader, then configured in the bootloader with the :ref:`CONFIG_BOOTLOADER_WDT_TIME_MS` option (9000 ms by default). During the application initialization stage, it is reconfigured because the source of the slow clock may have changed, and finally disabled right before the ``app_main()`` call. There is an option :ref:`CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE` which prevents the RTC watchdog from being disabled before ``app_main``. Instead, the RTC watchdog remains active and must be fed periodically in your application's code.
+The RTC watchdog covers the execution time from the first stage (ROM) bootloader to application startup. It is initially set in the first stage (ROM) bootloader, then configured in the bootloader with the :ref:`CONFIG_BOOTLOADER_WDT_TIME_MS` option (9000 ms by default). During the application initialization stage, it is reconfigured because the source of the slow clock may have changed, and finally disabled right before the ``app_main()`` call. There is an option :ref:`CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE` which prevents the RTC watchdog from being disabled before ``app_main``. Instead, the RTC watchdog remains active and must be fed periodically in your application's code.
 
 .. _Guru-Meditation-Errors:
 
@@ -310,7 +313,7 @@ This section explains the meaning of different error causes, printed in parens a
 
 .. note::
 
-  See the `Guru Meditation Wikipedia article <https://en.wikipedia.org/wiki/Guru_Meditation>`_ for historical origins of "Guru Meditation".
+    See the `Guru Meditation Wikipedia article <https://en.wikipedia.org/wiki/Guru_Meditation>`_ for historical origins of "Guru Meditation".
 
 
 |ILLEGAL_INSTR_MSG|
@@ -322,9 +325,9 @@ This CPU exception indicates that the instruction which was executed was not a v
 
 - Failure to read next instruction from SPI flash. This usually happens if:
 
-  - Application has reconfigured the SPI flash pins as some other function (GPIO, UART, etc.). Consult the Hardware Design Guidelines and the datasheet for the chip or module for details about the SPI flash pins.
+    - Application has reconfigured the SPI flash pins as some other function (GPIO, UART, etc.). Consult the Hardware Design Guidelines and the datasheet for the chip or module for details about the SPI flash pins.
 
-  - Some external device has accidentally been connected to the SPI flash pins, and has interfered with communication between {IDF_TARGET_NAME} and SPI flash.
+    - Some external device has accidentally been connected to the SPI flash pins, and has interfered with communication between {IDF_TARGET_NAME} and SPI flash.
 
 - In C++ code, exiting from a non-void function without returning a value is considered to be an undefined behavior. When optimizations are enabled, the compiler will often omit the epilogue in such functions. This most often results in an |ILLEGAL_INSTR_MSG| exception. By default, ESP-IDF build system enables ``-Werror=return-type`` which means that missing return statements are treated as compile time errors. However if the application project disables compiler warnings, this issue might go undetected and the |ILLEGAL_INSTR_MSG| exception will occur at run time.
 
@@ -424,7 +427,9 @@ Other Fatal Errors
 
     {IDF_TARGET_NAME} has a built-in brownout detector, which is enabled by default. The brownout detector can trigger a system reset if the supply voltage goes below a safe level. The brownout detector can be configured using :ref:`CONFIG_ESP_BROWNOUT_DET` and :ref:`CONFIG_ESP_BROWNOUT_DET_LVL_SEL` options.
 
-    When the brownout detector triggers, the following message is printed::
+    When the brownout detector triggers, the following message is printed:
+
+    .. code-block:: none
 
         Brownout detector was triggered
 
@@ -436,7 +441,9 @@ Other Fatal Errors
 Corrupt Heap
 ^^^^^^^^^^^^
 
-ESP-IDF's heap implementation contains a number of run-time checks of the heap structure. Additional checks ("Heap Poisoning") can be enabled in menuconfig. If one of the checks fails, a message similar to the following will be printed::
+ESP-IDF's heap implementation contains a number of run-time checks of the heap structure. Additional checks ("Heap Poisoning") can be enabled in menuconfig. If one of the checks fails, a message similar to the following will be printed:
+
+.. code-block:: none
 
     CORRUPT HEAP: Bad tail at 0x3ffe270a. Expected 0xbaad5678 got 0xbaac5678
     assertion "head != NULL" failed: file "/Users/user/esp/esp-idf/components/heap/multi_heap_poisoning.c", line 201, function: multi_heap_free
@@ -480,19 +487,20 @@ ESP-IDF provides a custom FreeRTOS stack overflow detecting mechanism based on w
 Generally, this may cause the watchpoint to be triggered up to 28 bytes earlier than expected. The value 32 is chosen because it is larger than the stack canary size in FreeRTOS (20 bytes). Adopting this approach ensures that the watchpoint triggers before the stack canary is corrupted, not after.
 
 .. note::
+
     Not every stack overflow is guaranteed to trigger the watchpoint. It is possible that the task writes to memory beyond the stack canary location, in which case the watchpoint will not be triggered.
 
 If watchpoint triggers, the message will be similar to:
 
 .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA
 
-    ::
+    .. code-block:: none
 
         Debug exception reason: Stack canary watchpoint triggered (task_name)
 
 .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
-    ::
+    .. code-block:: none
 
         Guru Meditation Error: Core  0 panic'ed (Breakpoint). Exception was unhandled.
 
@@ -507,7 +515,9 @@ See :ref:`CONFIG_FREERTOS_CHECK_STACKOVERFLOW`
 Stack Smashing
 ^^^^^^^^^^^^^^
 
-Stack smashing protection (based on GCC ``-fstack-protector*`` flags) can be enabled in ESP-IDF using :ref:`CONFIG_COMPILER_STACK_CHECK_MODE` option. If stack smashing is detected, message similar to the following will be printed::
+Stack smashing protection (based on GCC ``-fstack-protector*`` flags) can be enabled in ESP-IDF using :ref:`CONFIG_COMPILER_STACK_CHECK_MODE` option. If stack smashing is detected, message similar to the following will be printed:
+
+.. code-block:: none
 
     Stack smashing protect failure!
 
@@ -522,7 +532,7 @@ The backtrace should point to the function where stack smashing has occurred. Ch
 
     .. |CPU_EXCEPTIONS_LIST| replace:: Illegal Instruction, Load/Store Alignment Error, Load/Store Prohibited error, Double Exception.
     .. |ILLEGAL_INSTR_MSG| replace:: IllegalInstruction
-    .. |CACHE_ERR_MSG| replace:: Cache disabled but cached memory region accessed
+    .. |CACHE_ERR_MSG| replace:: Cache error
     .. |STACK_OVERFLOW| replace:: Stack overflow
 
 .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
@@ -537,9 +547,10 @@ The backtrace should point to the function where stack smashing has occurred. Ch
 
     CPU Lockup
     ^^^^^^^^^^
-    A CPU lockup reset happens when there is a double exception, i.e. when an exception occurs while the CPU is already in an exception handler. The most common cause for this is when the cache is in such a state that accessing external memory not possible. If this is the case then the panic handler will crash as well due to being unable to fetch instructions or read data.
 
-    If this is the case you can try placing the panic handler code in IRAM, which can be accessed when cache is disabled, to get more information about the cause of the lockup. This can be done with :ref:`CONFIG_ESP_PANIC_HANDLER_IRAM`.
+    A CPU lockup reset happens when there is a double exception, i.e. when an exception occurs while the CPU is already in an exception handler. The most common cause for this is when the cache is in a state where accessing external memory becomes impossible. In such cases, the panic handler will crash as well due to being unable to fetch instructions or read data.
+
+    To gather more information about the cause of the lockup, you can try placing the panic handler code in IRAM, which remains accessible even when the cache is disabled. This can be done with :ref:`CONFIG_ESP_PANIC_HANDLER_IRAM`.
 
 
 Undefined Behavior Sanitizer (UBSAN) Checks
@@ -560,7 +571,9 @@ UBSAN is disabled by default. It can be enabled at file, component, or project l
 
 When enabling UBSAN for code which uses the SOC hardware register header files (``soc/xxx_reg.h``), it is recommended to disable shift-base sanitizer using ``-fno-sanitize=shift-base`` option. This is due to the fact that ESP-IDF register header files currently contain patterns which cause false positives for this specific sanitizer option.
 
-To enable UBSAN at project level, add the following code at the end of the project's ``CMakeLists.txt`` file::
+To enable UBSAN at project level, add the following code at the end of the project's ``CMakeLists.txt`` file:
+
+.. code-block:: none
 
     idf_build_set_property(COMPILE_OPTIONS "-fsanitize=undefined" "-fno-sanitize=shift-base" APPEND)
 
@@ -568,29 +581,37 @@ Alternatively, pass these options through the ``EXTRA_CFLAGS`` and ``EXTRA_CXXFL
 
 Enabling UBSAN results in significant increase of code and data size. Most applications, except for the trivial ones, will not fit into the available RAM of the microcontroller when UBSAN is enabled for the whole application. Therefore it is recommended that UBSAN is instead enabled for specific components under test.
 
-To enable UBSAN for a specific component (``component_name``) from the project's ``CMakeLists.txt`` file, add the following code at the end of the file::
+To enable UBSAN for a specific component (``component_name``) from the project's ``CMakeLists.txt`` file, add the following code at the end of the file:
+
+.. code-block:: none
 
     idf_component_get_property(lib component_name COMPONENT_LIB)
     target_compile_options(${lib} PRIVATE "-fsanitize=undefined" "-fno-sanitize=shift-base")
 
 .. note::
 
-  See the build system documentation for more information about :ref:`build properties <cmake-build-properties>` and :ref:`component properties <cmake-component-properties>`.
+    See the build system documentation for more information about :ref:`build properties <cmake-build-properties>` and :ref:`component properties <cmake-component-properties>`.
 
-To enable UBSAN for a specific component (``component_name``) from ``CMakeLists.txt`` of the same component, add the following at the end of the file::
+To enable UBSAN for a specific component (``component_name``) from ``CMakeLists.txt`` of the same component, add the following at the end of the file:
+
+.. code-block:: none
 
     target_compile_options(${COMPONENT_LIB} PRIVATE "-fsanitize=undefined" "-fno-sanitize=shift-base")
 
 UBSAN Output
 """"""""""""
 
-When UBSAN detects an error, a message and the backtrace are printed, for example::
+When UBSAN detects an error, a message and the backtrace are printed, for example:
+
+.. code-block:: none
 
     Undefined behavior of type out_of_bounds
 
     Backtrace:0x4008b383:0x3ffcd8b0 0x4008c791:0x3ffcd8d0 0x4008c587:0x3ffcd8f0 0x4008c6be:0x3ffcd950 0x400db74f:0x3ffcd970 0x400db99c:0x3ffcd9a0
 
-When using :doc:`IDF Monitor <tools/idf-monitor>`, the backtrace will be decoded to function names and source code locations, pointing to the location where the issue has happened (here it is ``main.c:128``)::
+When using :doc:`IDF Monitor <tools/idf-monitor>`, the backtrace will be decoded to function names and source code locations, pointing to the location where the issue has happened (here it is ``main.c:128``):
+
+.. code-block:: none
 
     0x4008b383: panic_abort at /path/to/esp-idf/components/esp_system/panic.c:367
 
@@ -608,34 +629,34 @@ The types of errors reported by UBSAN can be as follows:
 
 
 .. list-table::
-  :widths: 40 60
-  :header-rows: 1
-
-  * - Name
-    - Meaning
-  * - ``type_mismatch``, ``type_mismatch_v1``
-    - Incorrect pointer value: null, unaligned, not compatible with the given type.
-  * - ``add_overflow``, ``sub_overflow``, ``mul_overflow``, ``negate_overflow``
-    - Integer overflow during addition, subtraction, multiplication, negation.
-  * - ``divrem_overflow``
-    - Integer division by 0 or ``INT_MIN``.
-  * - ``shift_out_of_bounds``
-    - Overflow in left or right shift operators.
-  * - ``out_of_bounds``
-    - Access outside of bounds of an array.
-  * - ``unreachable``
-    - Unreachable code executed.
-  * - ``missing_return``
-    - Non-void function has reached its end without returning a value (C++ only).
-  * - ``vla_bound_not_positive``
-    - Size of variable length array is not positive.
-  * - ``load_invalid_value``
-    - Value of ``bool`` or ``enum`` (C++ only) variable is invalid (out of bounds).
-  * - ``nonnull_arg``
-    - Null argument passed to a function which is declared with a ``nonnull`` attribute.
-  * - ``nonnull_return``
-    - Null value returned from a function which is declared with ``returns_nonnull`` attribute.
-  * - ``builtin_unreachable``
-    - ``__builtin_unreachable`` function called.
-  * - ``pointer_overflow``
-    - Overflow in pointer arithmetic.
+    :widths: 40 60
+    :header-rows: 1
+
+    * - Name
+      - Meaning
+    * - ``type_mismatch``, ``type_mismatch_v1``
+      - Incorrect pointer value: null, unaligned, not compatible with the given type.
+    * - ``add_overflow``, ``sub_overflow``, ``mul_overflow``, ``negate_overflow``
+      - Integer overflow during addition, subtraction, multiplication, negation.
+    * - ``divrem_overflow``
+      - Integer division by 0 or ``INT_MIN``.
+    * - ``shift_out_of_bounds``
+      - Overflow in left or right shift operators.
+    * - ``out_of_bounds``
+      - Access outside of bounds of an array.
+    * - ``unreachable``
+      - Unreachable code executed.
+    * - ``missing_return``
+      - Non-void function has reached its end without returning a value (C++ only).
+    * - ``vla_bound_not_positive``
+      - Size of variable length array is not positive.
+    * - ``load_invalid_value``
+      - Value of ``bool`` or ``enum`` (C++ only) variable is invalid (out of bounds).
+    * - ``nonnull_arg``
+      - Null argument passed to a function which is declared with a ``nonnull`` attribute.
+    * - ``nonnull_return``
+      - Null value returned from a function which is declared with ``returns_nonnull`` attribute.
+    * - ``builtin_unreachable``
+      - ``__builtin_unreachable`` function called.
+    * - ``pointer_overflow``
+      - Overflow in pointer arithmetic.
diff --git a/docs/en/api-guides/file-system-considerations.rst b/docs/en/api-guides/file-system-considerations.rst
index a57ab01c878..9b6c05253ef 100644
--- a/docs/en/api-guides/file-system-considerations.rst
+++ b/docs/en/api-guides/file-system-considerations.rst
@@ -50,7 +50,7 @@ The most significant properties and features of above-mentioned file systems are
       - Integrated
       - Integrated
     * - Minimum partition size
-      - * 128 sectors With wear levelling on (WL sector=4096B):
+      - * 8 sectors with wear levelling on (4 FATFS sectors + 4 WL sectors with WL sector size = 4096B)
         * plus 4 sectors at least
         * real number given by WL configuration (Safe, Perf)
       - * 6 logical blocks
@@ -105,7 +105,7 @@ The most supported file system, recommended for common applications - file/direc
 **Examples:**
 
 * :example:`storage/sd_card`: access the SD card which uses the FAT file system
-* :example:`storage/ext_flash_fatfs`: access the external flash chip which uses the FAT file system
+* :example:`storage/fatfs/ext_flash`: access the external flash chip which uses the FAT file system
 
 
 .. _spiffs-fs-section:
@@ -113,7 +113,7 @@ The most supported file system, recommended for common applications - file/direc
 SPIFFS
 ----------------------
 
-SPIFFS is a file system providing certain level of power-off safety (see repair-after-restart function :cpp:func:`esp_spiffs_check`) and built-in wear levelling. It tend to become slow down when exceeding around 70% of dedicated partition size due to its garbage collector implementation, and it also doesn't support directories. It is useful for applications depending only on few files (possibly large) and requiring high level of consistency. Generally, the SPIFFS needs less RAM resources than FatFS and supports flash chips up to 128MB in size. Please keep in mind the SPIFFS is not being developed and maintained anymore, so consider precisely whether its advantages for your project really prevail over the other file systems.
+SPIFFS is a file system providing certain level of power-off safety (see repair-after-restart function :cpp:func:`esp_spiffs_check`) and built-in wear levelling. It tends to slow down when exceeding around 70% of the dedicated partition size due to its garbage collector implementation, and also doesn't support directories. It is useful for applications depending only on few files (possibly large) and requiring high level of consistency. Generally, the SPIFFS needs less RAM resources than FatFS and supports flash chips up to 128 MB in size. Please keep in mind the SPIFFS is not being developed and maintained anymore, so consider precisely whether its advantages for your project really prevail over the other file systems.
 
 **Related documents:**
 
@@ -122,7 +122,7 @@ SPIFFS is a file system providing certain level of power-off safety (see repair-
 
 **Examples:**
 
-* :example:`storage/spiffs`: SPIFFS examples
+* :example:`storage/spiffs` demonstrates how to use SPIFFS.
 
 
 .. _littlefs-fs-section:
@@ -143,7 +143,7 @@ LittleFS is available as external component in the ESP Registry, see `LittleFS c
 
 **Examples:**
 
-* :example:`storage/littlefs`: ESP-IDF LittleFS example
+* :example:`storage/littlefs` demonstrates how to use LittleFS.
 
 .. _nvs-fs-section:
 
@@ -177,10 +177,10 @@ Points to keep in mind when developing NVS related code:
 
 **Examples:**
 
-- Write a single integer value: :example:`storage/nvs_rw_value`
-- Write a blob: :example:`storage/nvs_rw_blob`
-- Encryption keys generation: :example:`security/nvs_encryption_hmac`
-- Flash encryption workflow including NVS partition: :example:`security/flash_encryption`
+- :example:`storage/nvs_rw_value` demonstrates how to use NVS to write and read a single integer value.
+- :example:`storage/nvs_rw_blob` demonstrates how to use NVS to write and read a blob.
+- :example:`security/nvs_encryption_hmac` demonstrates NVS encryption using the HMAC peripheral, where the encryption keys are derived from the HMAC key burnt in eFuse.
+- :example:`security/flash_encryption` demonstrates the flash encryption workflow including NVS partition creation and usage.
 
 
 File handling design considerations
@@ -205,5 +205,5 @@ Encrypting partitions
 Given storage security scheme and the {IDF_TARGET_NAME} chips design result into a few implications which may not be fully obvious in the main documents:
 
 * The Flash encryption applies only to the main SPI Flash memory, due to its cache module design (all the "transparent" encryption APIs run over this cache). This implies that external flash partitions cannot be encrypted using the native Flash Encryption means.
-* External partition encryption can be deployed by implementing custom encrypt/decrypt code in appropriate driver APIs - either by implementing own SPI flash driver (see :example:`storage/custom_flash_driver`) or by customising higher levels in the driver stack, for instance by providing own :ref:`FatFS disk IO layer <fatfs-diskio-layer>`.
+* External partition encryption can be deployed by implementing custom encrypt/decrypt code in appropriate driver APIs - either by implementing own SPI flash driver (see :example:`storage/custom_flash_driver`) or by customizing higher levels in the driver stack, for instance by providing own :ref:`FatFS disk IO layer <fatfs-diskio-layer>`.
 
diff --git a/docs/en/api-guides/flash_psram_config.rst b/docs/en/api-guides/flash_psram_config.rst
index bc4103cd938..883c020cba1 100644
--- a/docs/en/api-guides/flash_psram_config.rst
+++ b/docs/en/api-guides/flash_psram_config.rst
@@ -73,7 +73,7 @@ To enable PSRAM, please enable the :ref:`CONFIG_SPIRAM` under ``Component config
 
 .. note::
 
-    If a board with Octal flash resets before the second-stage bootloader, please refer to :ref:`Error Handling Chapter <flash-psram-error>`.
+    If a board with Octal flash resets before the second stage bootloader, please refer to :ref:`Error Handling Chapter <flash-psram-error>`.
 
 
 .. _flash-psram-combination:
@@ -228,7 +228,7 @@ F4R4 Hardware
 Error Handling
 --------------
 
-1. If a board with Octal flash resets before the second-stage bootloader:
+1. If a board with Octal flash resets before the second stage bootloader:
 
     .. code-block:: c
 
@@ -243,7 +243,7 @@ Error Handling
 
    this may mean that the necessary eFuses are not correctly burnt. Please check the eFuse bits of the chip using ``idf.py efuse-summary``.
 
-   The ROM bootloader relies on an eFuse bit ``FLASH_TYPE`` to reset the flash into the default mode (SPI mode). If this bit is not burnt and the flash is working in OPI mode, ROM bootloader may not be able to read from the flash and load the following images.
+   The first stage (ROM) bootloader relies on an eFuse bit ``FLASH_TYPE`` to reset the flash into the default mode (SPI mode). If this bit is not burnt and the flash is working in OPI mode, the first stage (ROM) bootloader may not be able to read from the flash and load the following images.
 
 2. If you enabled :ref:`CONFIG_ESPTOOLPY_OCT_FLASH`, and there's an error log saying:
 
diff --git a/docs/en/api-guides/hlinterrupts.rst b/docs/en/api-guides/hlinterrupts.rst
index 6655a13ae43..4b0dd29295d 100644
--- a/docs/en/api-guides/hlinterrupts.rst
+++ b/docs/en/api-guides/hlinterrupts.rst
@@ -114,7 +114,7 @@ Then, in the component ``CMakeLists.txt``, add this name as an unresolved symbol
 
 This will ensure the linker to always includes the file defining ``ld_include_my_isr_file``, so that the ISR is always linked.
 
-- High-priority interrupts can be routed and handled using :cpp:func:`esp_intr_alloc` and associated functions. The handler and handler arguments to :cpp:func:`esp_intr_alloc` must be NULL, however.
+- High-priority interrupts can be routed and handled using :cpp:func:`esp_intr_alloc` and associated functions. However, the handler and handler arguments to :cpp:func:`esp_intr_alloc` must be NULL.
 
 - In theory, medium priority interrupts could also be handled in this way. ESP-IDF does not support this yet.
 
diff --git a/docs/en/api-guides/inc/external-ram-esp32-notes.rst b/docs/en/api-guides/inc/external-ram-esp32-notes.rst
index ac8f8d4764c..b914ebd8165 100644
--- a/docs/en/api-guides/inc/external-ram-esp32-notes.rst
+++ b/docs/en/api-guides/inc/external-ram-esp32-notes.rst
@@ -1,4 +1,4 @@
-* Regarding stacks in PSRAM: For tasks that do not call ROM code in any way (directly or indirectly), the :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` option will eliminate the check in :cpp:func:`xTaskCreateStatic`, allowing a task's stack to be in external RAM. However, using this is **not advised**.
+* Regarding stacks in PSRAM: For tasks that do not call ROM code in any way (directly or indirectly), the :ref:`CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM` option will eliminate the check in :cpp:func:`xTaskCreateStatic`, allowing a task's stack to be in external RAM. However, using this is **not advised**.
 * When used at 80 MHz clock speed, external RAM must also occupy either the HSPI or VSPI bus. Select which SPI host will be used by :ref:`CONFIG_SPIRAM_OCCUPY_SPI_HOST`.
 
 
diff --git a/docs/en/api-guides/index.rst b/docs/en/api-guides/index.rst
index 26a46a389ec..e9ad8c6941e 100644
--- a/docs/en/api-guides/index.rst
+++ b/docs/en/api-guides/index.rst
@@ -29,6 +29,7 @@ API Guides
    hardware-abstraction
    :CONFIG_IDF_TARGET_ARCH_XTENSA: hlinterrupts
    jtag-debugging/index
+   kconfig/index
    linker-script-generation
    low-power-mode/index
    lwip
diff --git a/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst b/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst
index 8037f47cbf9..68ead8622c4 100644
--- a/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst
+++ b/docs/en/api-guides/jtag-debugging/tips-and-quirks.rst
@@ -103,8 +103,20 @@ In order to achieve higher data rates and minimize number of dropped packets it
 3.  In particular reduce frequency, if you get DSR/DIR errors (and they do not relate to OpenOCD trying to read from a memory range without physical memory being present there).
 4.  ESP-WROVER-KIT operates stable at 20 MHz or 26 MHz.
 
+.. only:: SOC_DEBUG_HAVE_OCD_STUB_BINS
 
-.. _jtag-debugging-tip-debugger-startup-commands:
+    .. _jtag-debugging-tip-improve-debugging-speed:
+
+    Improve Debugging Speed
+    ^^^^^^^^^^^^^^^^^^^^^^^
+
+    Enabling :ref:`CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS` allocates 8 KB of RAM and embeds pre-built stub binaries into RAM. This improves the overall debugging speed by eliminating the need to load the stub binaries at runtime. It is particularly beneficial when using flash breakpoints, as it reduces the latency of add/remove breakpoints. However, keep in mind that the increased RAM usage may reduce memory availability for other tasks.
+
+    .. _jtag-debugging-tip-debugger-startup-commands:
+
+.. only:: not SOC_DEBUG_HAVE_OCD_STUB_BINS
+
+    .. _jtag-debugging-tip-debugger-startup-commands:
 
 What Is the Meaning of Debugger's Startup Commands?
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/docs/en/api-guides/kconfig/component-configuration-guide.rst b/docs/en/api-guides/kconfig/component-configuration-guide.rst
new file mode 100644
index 00000000000..39fcba59bb6
--- /dev/null
+++ b/docs/en/api-guides/kconfig/component-configuration-guide.rst
@@ -0,0 +1,99 @@
+.. _component-configuration-guide:
+
+Component Configuration Guide
+=============================
+
+This guide is intended to describe how to define configuration options for components in ESP-IDF. Following topics will be covered:
+
+- How to define new configuration options for components.
+- Basic syntax of Kconfig language.
+- How to ensure backward compatibility.
+
+How Configuration Works in ESP-IDF
+----------------------------------
+
+.. note::
+
+    More detailed information about the configuration system in ESP-IDF can be found in the :ref:`configuration-overview`.
+
+
+ESP-IDF uses unified way to configure the project, build system, ESP-IDF framework itself and external components. This configuration tool is called `Kconfig <https://docs.espressif.com/projects/esp-idf-kconfig/en/latest/kconfiglib/index.html>`_.
+
+Configuration options are **defined** in ``Kconfig`` files. ESP-IDF contains the top-level ``Kconfig`` file in the root of the framework. Each component can have its own ``Kconfig`` file defining configuration options specific to that component, as well as relations between the options. Relations between config options can spread across multiple Kconfig files from different sources. In other words, configuration option from ``Component_A`` can depend on a configuration option from ``Component_B``, even if ``Component_B`` is e.g. maintained by another developer.
+
+When the configuration is saved (for more information about configuration editing, see e.g. :ref:`project-configuration-guide`), the  **values** in the ``sdkconfig`` file are updated, as well as those in ``sdkconfig.h``, ``sdkconfig.cmake`` and ``sdkconfig.json``.
+
+How to Define New Configuration Options for Your Component
+----------------------------------------------------------
+.. note::
+
+    If you plan to write ``Kconfig`` configuration files for your component, but you are not familiar with ``Kconfig language`` it is recommended to refer to the `esp-idf-kconfig Documentation <https://docs.espressif.com/projects/esp-idf-kconfig/en/latest/index.html>`_, where an in-depth guide is provided.
+
+To define new configuration options for components, you need to:
+
+1. Create the ``Kconfig`` and/or ``Kconfig.projbuild`` in the root folder of the component.
+2. Define the configuration options in the ``Kconfig`` and/or ``Kconfig.projbuild`` file. It is generally a good practice to wrap them in the ``menu-endmenu`` block. You can see a minimal example below. Complete documentation of the Kconfig language can be found in the `Kconfig Documentation <https://docs.espressif.com/projects/esp-idf-kconfig/en/latest/kconfiglib/language.html>`_.
+
+When your component is used in a project, the ``Kconfig`` and/or ``Kconfig.projbuild`` will be automatically discovered and shown in the ``menuconfig`` tool.
+
+.. note::
+
+    **Difference between Kconfig and Kconfig.projbuild files**:
+
+    - ``Kconfig``: configuration options in this file will be shown under ``Component configuration`` in the ``menuconfig`` tool.
+    - ``Kconfig.projbuild``: configuration options in this file will be shown in the top menu of the ``menuconfig`` tool.
+
+Example:
+
+.. code-block:: kconfig
+
+    menu "Motors configuration"
+
+        config SUBLIGHT_DRIVE_ENABLED
+            bool "Enable sublight drive"
+            default n
+            depends on SPACE_SHIP
+            help
+                This option enables sublight on our spaceship.
+
+    endmenu
+
+.. note::
+
+    **Visibility and dependencies**:
+
+    In the example above, the ``SUBLIGHT_DRIVE_ENABLED`` configuration option has a dependency on the ``SPACE_SHIP`` configuration option. This option can origin from a different component. If the ``SPACE_SHIP`` option is not set or is not defined in the current configuration (e.g. the component containing this option was  not included in the project), the dependency will not be satisfied and the ``SUBLIGHT_DRIVE_ENABLED`` option will not be shown in the ``menuconfig`` tool.
+
+    For more information about the visibility and dependencies, please refer to the `Kconfig Documentation <https://docs.espressif.com/projects/esp-idf-kconfig/en/latest/kconfiglib/language.html>`_.
+
+
+.. _configuration-options-compatibility:
+
+How to Ensure Backward Compatibility
+------------------------------------
+
+In general, renaming a Kconfig option of a component is a breaking API change, just like renaming a function is. ESP-IDF contains a mechanism which makes it possible to maintain backward compatibility when renaming configuration options. This mechanism is based on ``sdkconfig.rename`` files which include pairs of configuration option names. File structure is described below.
+
+When renaming configuration options of a component, create the ``sdkconfig.rename`` file in the root folder of the component. Every line in this file should contain one of the following pairs:
+
+* ``CONFIG_OLD_NAME CONFIG_NEW_NAME`` if the new option is a direct replacement of the old option.
+* ``CONFIG_OLD_NAME !CONFIG_NEW_NAME`` if the new option is a Boolean inversion of the old option.
+
+The project configuration tool (invoked by ``idf.py menuconfig``) will automatically find it and generate the compatibility statements in ``sdkconfig`` for the user.
+
+For more information about the ``sdkconfig.rename`` file, please refer to the :ref:`sdkconfig.rename <sdkconfig-rename-file>` section of Configuration Structure.
+
+Detailed explanation of the backward compatibility mechanism:
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. note::
+
+    This part of the guide is intended to explain the behavior of the backward compatibility mechanism in ESP-IDF in greater detail. It is not necessary to understand this mechanism as it it done automatically, but it is described here for the sake of completeness.
+
+If the user has set any value for the old config option (e.g. old config name is used in ``sdkconfig`` or ``sdkconfig.defaults``) without ``sdkconfig.rename`` file provided, this value would be **silently ignored**. This behavior is the default of the Kconfig system and is not a bug. In the original project (configuration of the linux kernel) this behavior was desired and is still desired in many projects.
+
+This behavior is suppressed in ESP-IDF by the the configuration tool (invoked by ``idf.py menuconfig``). This tool generates compatibility statements for all the renamed options in the ``sdkconfig`` file. In more detail, the following approach is used to prevent the above mentioned situation:
+
+1. Configuration tool searches the whole ESP-IDF folder for ``sdkconfig.rename`` files. If the project target (``<chip>``) matches the last suffix of any ``sdkconfig.rename.<chip>`` file, the file will be used in the next step as well.
+
+2. After collecting all the relevant files, the ``sdkconfig`` file (and ``sdkconfig.h/json/cmake`` files if any) is post-processed. A block of compatibility statements for all the renamed options is added during the post-process to the end of the file(s). The block starts with ``# Deprecated options for backward compatibility`` and ends with ``# End of deprecated options``.
diff --git a/docs/en/api-guides/kconfig/configuration_structure.rst b/docs/en/api-guides/kconfig/configuration_structure.rst
new file mode 100644
index 00000000000..3a9bd8f33d9
--- /dev/null
+++ b/docs/en/api-guides/kconfig/configuration_structure.rst
@@ -0,0 +1,151 @@
+.. _configuration-structure:
+
+Configuration Files Structure and Relationships
+===============================================
+
+.. note::
+
+    This article primarily focuses on the structure of the files. For more information about project configuration, please refer to the :ref:`Project Configuration Guide <project-configuration-guide>`. For the component configuration, please refer to the :ref:`Component Configuration Guide <component-configuration-guide>`.
+
+ESP-IDF uses `Kconfig language <https://docs.espressif.com/projects/esp-idf-kconfig/en/latest/kconfiglib/language.html>`_ for configuration of the project. Configuration consists of config options (e.g. ``CONFIG_IDF_TARGET``) and their values (e.g. ``esp32``). Every config option has a prefix ``CONFIG_`` to distinguish it from e.g. environment variables.
+
+In context of ESP-IDF, configuration consists of several files, most importantly:
+
+- ``Kconfig`` files, defining the configuration options and their relationships, together with their default values (if any).
+- ``sdkconfig`` file, containing the currently used values of configuration options.
+- ``sdkconfig.defaults`` file, containing user-defined default values for the configuration options.
+- ``sdkconfig.rename`` file, containing ``OLD_NAME NEW_NAME`` pairs of configuration names to ensure backward compatibility. This file is used primarily by component or ESP-IDF developers.
+
+Configuration files can be divided into two groups: those primarily **defining** the configuration options and those containing the **values** of these options. First group includes ``Kconfig``, ``Kcofnig.projbuild`` and ``sdkconfig.rename`` files, second group includes ``sdkconfig``, ``sdkconfig.defaults``, ``sdkconfig.h`` and ``sdkconfig.cmake`` files. All the files will be described in the following sections.
+
+For more information about the configuration system in ESP-IDF, please refer to the :ref:`Configuration Overview <configuration-overview>`.
+
+.. _kconfig-files:
+
+Kconfig and Kconfig.projbuild Files
+-----------------------------------
+
+The ``Kconfig.*`` files store the configuration options, together with their properties and relationships. They also may contain default values for the configuration options. Every component has its own ``Kconfig`` file, which is used to define the configuration options for that component.
+
+The only difference between ``Kconfig`` and ``Kconfig.projbuild`` files is where the their content will appear in the configuration interface (menuconfig):
+
+- ``Kconfig``: The content of this file will appear in the ``Component config`` window of the configuration interface.
+- ``Kconfig.projbuild``: The content of this file will appear in the root window of the configuration interface.
+
+Example of ``Kconfig`` file:
+
+.. code-block:: kconfig
+
+    mainmenu "Motors configuration"
+
+        config SUBLIGHT_DRIVE_ENABLED
+            bool "Enable sublight drive"
+            default y
+            help
+                This option enables sublight on our spaceship.
+
+For more information about the Kconfig language, please refer to the `Kconfig Documentation <https://docs.espressif.com/projects/esp-idf-kconfig/en/latest/kconfiglib/language.html>`_.
+
+.. _sdkconfig-file:
+
+sdkconfig and sdkconfig.old
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+In the ``sdkconfig`` file, **values currently assigned** to the configuration options are stored. It is generated automatically and is not to be edited, because configuration options can have relationships between one another (dependencies and reverse dependencies), that can be broken by manual editing.
+
+Every line follows one of the following patterns:
+
+- ``CONFIG_NAME=<value>``: Config name and its value.
+- ``# CONFIG_NAME is not set``: Boolean config ``CONFIG_NAME`` is visible, but it is set to n. For non-Boolean configs, ``CONFIG_NAME=""`` will be present instead.
+- Other #-style comments and empty lines.
+
+The ``sdkconfig.old`` file is a backup of the previous configuration. It is generated every time the ``sdkconfig`` file is generated.
+
+.. note::
+
+    There are other sdkconfig.* files in the project, namely ``sdkconfig.h``, ``sdkconfig.cmake``, ``sdkconfig.json``. These files are the same as the ``sdkconfig`` file mentioned above, but in different formats. These files are used with their respective tools (C/C++ code, CMake). You can check :ref:`configs-in-C-Cmake` for more information.
+
+.. _sdkconfig-rename-file:
+
+sdkconfig.rename and sdkconfig.rename.<chip>
+----------------------------------------------------
+
+The ``sdkconfig.rename`` files are used by the build system to ensure backward compatibility. These files are created and maintained by component or ESP-IDF developers and application developer should have no need to edit them.
+
+The structure of the ``sdkconfig.rename`` file is as follows:
+
+* Lines starting with ``#`` and empty lines will be ignored.
+* All other lines should follow one of these formats:
+    * ``CONFIG_DEPRECATED_NAME CONFIG_NEW_NAME``, where ``CONFIG_DEPRECATED_NAME`` is the old config name which was renamed in a newer ESP-IDF version to ``CONFIG_NEW_NAME``.
+    * ``CONFIG_DEPRECATED_NAME !CONFIG_NEW_INVERTED_NAME`` where ``CONFIG_NEW_INVERTED_NAME`` was introduced in a newer ESP-IDF version by Boolean inversion of the logic value of ``CONFIG_DEPRECATED_NAME``.
+
+Primary use case of this file is to ensure backward compatibility when the config name is changed in the newer ESP-IDF version.
+
+Example:
+
+``sdkconfig.rename``:
+
+.. code-block:: kconfig
+
+    # new name            old name
+    CONFIG_HYPEDRIVE      CONFIG_WARP_DRIVE
+    CONFIG_DISABLE_WAPRT_ !CONFIG_ENABLE_WARP_DRIVE
+
+``sdkconfig``:
+
+.. code-block:: kconfig
+
+    (...)
+    CONFIG_HYPEDRIVE=y
+    CONFIG_DISABLE_HYPEDRIVE=n
+    (...)
+    # Deprecated options for backward compatibility
+    CONFIG_WARP_DRIVE=y
+    CONFIG_ENABLE_WARP_DRIVE=y
+    # End of deprecated options
+
+.. _sdkconfig-defaults-file:
+
+sdkconfig.defaults and sdkconfig.defaults.<chip>
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Kconfig language provides a way to set default values for configs: ``default`` option. However, input Kconfig file may be in a different project, under version control or there is another reason why it would be inconvenient to directly edit it. In this case, ``sdkconfig.defaults`` file can be used. The file structure is the same as ``sdkconfig`` file; on every line, there is a full config name (including the ``CONFIG_`` prefix) and its value. This value has precedence over the default value in the Kconfig file by ``default`` option.
+
+It is also possible to override the default values only for specific target. In this case, you can create ``sdkconfig.defaults.<chip>`` file, where ``<chip>`` is the target name (e.g. ``esp32s2``). In this case, it is mandatory to create the ``sdkconfig.defaults`` file as well, otherwise the ``sdkconfig.defaults.<chip>`` file will be ignored. However, the ``sdkconfig.defaults`` file can be empty.
+
+.. note::
+
+    Values in ``sdkconfig.defaults`` are additional default values, not overrides! This means that those values will be ignored if ``sdkconfig`` file is present.
+
+It is also possible to override the name of this file by setting an environment variable. For information on how to set the custom file name and in which order the files are processed if multiple files with default values are present, please visit :ref:`Custom Sdkconfig Defaults <custom-sdkconfig-defaults>` section of Build System documentation.
+
+Example:
+
+``Kconfig``:
+
+.. code-block:: kconfig
+
+    (...)
+    config SUBLIGHT_SPEED
+        int "Sublight speed"
+        default 10
+    (...)
+
+``sdkconifg.defaults``:
+
+.. code-block:: text
+
+    CONFIG_SUBLIGHT_SPEED=42
+
+When running e.g. ``idf.py menuconfig``, the ``SUBLIGHT_SPEED`` will be set to 42. If the value will be changed in the GUI, the value from the GUI will be used and saved into ``sdkconfig`` file.
+
+How to generate ``sdkconfig.defaults`` file:
+
+1. ``cd`` into your project folder.
+2. Configure everything you need in ``idf.py menuconfig``.
+3. Run ``idf.py save-defconfig``. This will generate ``sdkconfig.defaults`` file with all the values different from the default ones.
+
+sdkconfig.ci
+^^^^^^^^^^^^
+
+Some of the IDF examples include a ``sdkconfig.ci`` file. This is part of the continuous integration (CI) test framework and is ignored by the normal build process.
diff --git a/docs/en/api-guides/kconfig/index.rst b/docs/en/api-guides/kconfig/index.rst
new file mode 100644
index 00000000000..2779bc6d44b
--- /dev/null
+++ b/docs/en/api-guides/kconfig/index.rst
@@ -0,0 +1,29 @@
+.. _configuration-overview:
+
+Project Configuration
+=====================
+
+In smaller projects (e.g. command line utility like ``grep`` command), it is often enough to configure it e.g. via command line parameters. When the projects gets larger, dedicated configuration files (C/C++ header files, YAML, JSON etc.) are often used with parameters altering the code behavior. However, as the number of configuration options grows, it becomes more and more difficult to manage them. Furthermore, different parts of the project (think of e.g. IDE plugins) can have different ways of configuring.
+
+ESP-IDF project unified the way to configure the project, build system, ESP-IDF framework itself and external components. This configuration tool is called Kconfig.
+
+Kconfig tool uses distributed structure of configuration files of the same name (``Kconfig``). These files contain the **definition** of configuration options (e.g. name, type) and may contain their **default values**. Every component has its own ``Kconfig`` file. Their discovery is done automatically by the configuration tool.
+
+**Values currently assigned** to the configuration options are then stored in one :ref:`sdkconfig file <sdkconfig-file>` in the project's root folder. This file is specific for the given project and is changed every time user makes a change in any of the configuration option's value. For the purpose of editing the configuration, the :ref:`menuconfig tool <project-configuration-menu>` is used. The values of the configuration options are also propagated to the CMake scripts and C code via ``sdkconfig.h`` and ``sdkconfig.cmake`` files.
+
+For the purpose of setting **user-defined default values** for configuration options, the :ref:`sdkconfig.defaults file <sdkconfig-defaults-file>` can be used. This approach is also preferred in the situation when the project is under version control. This file is used to replace default values set by ``Kconfig`` files when the project is configured the first time and no ``sdkconfig`` is present, but those values can still be changed by the user via configuration tools (e.g. ``idf.py menuconfig``).
+
+.. toctree::
+    :maxdepth: 2
+
+    ESP-IDF Project Configuration Guide <project-configuration-guide>
+    Configuration Files and Structure <configuration_structure>
+    Defining configuration options of components <component-configuration-guide>
+
+
+.. note::
+
+    For the detailed information about Kconfig language or ``esp-idf-kconfig``, which is the package of tools for the ESP-IDF configuration, please refer to the to the lower-level and more implementation-focused `esp-idf-kconfig documentation <https://docs.espressif.com/projects/esp-idf-kconfig/en/latest/>`_.
+
+.. note::
+    For the complete list of configuration options, please refer to the :ref:`Configuration Options Reference <configuration-options-reference>` and in the top left corner, choose your combination of a chip and ESP-IDF version.
diff --git a/docs/en/api-guides/kconfig/project-configuration-guide.rst b/docs/en/api-guides/kconfig/project-configuration-guide.rst
new file mode 100644
index 00000000000..b772122983b
--- /dev/null
+++ b/docs/en/api-guides/kconfig/project-configuration-guide.rst
@@ -0,0 +1,107 @@
+.. _project-configuration-guide:
+
+Project Configuration Guide
+===========================
+
+This guide is intended to describe three aspects of project configuration in ESP-IDF:
+
+- How the configuration can be edited (``idf.py menuconfig`` and configuration via plugins)
+- How to use configuration values in C code and CMake
+- How to define new configuration options for the project
+
+.. _project-configuration-menu:
+
+Editing the Configuration
+-------------------------
+
+As mentioned in the :ref:`configuration-overview`, **values currently assigned** to the configuration options are stored in the ``sdkconfig`` file. This file should not be edited manually, because there can be relationships between the configuration options that could be broken by manual editing. Instead, the ``idf.py menuconfig`` command  (or its alternatives depending on the specific IDE used) should be used.
+
+If the user wants to redefine the default values of the configuration options set in ``Kconfig`` files, the ``sdkconfig.defaults`` file can be used. The values set there overwrite those from ``Kconfig`` files, but user can still change those via ``idf.py menuconfig``. Those user-set values for the configuration options will be stored in the ``sdkconfig`` file, ``sdkconfig.defaults`` will remain unchanged.
+
+There are several ways how to configure the project, depending on the IDE used. The most common way is to use the ``idf.py menuconfig`` command. This command opens a TUI (Text-based User Interface) where user can set the configuration options. The configuration is saved into the ``sdkconfig`` file. Alternatively, IDE plugins can be used as well.
+
+Independently on the tool used, configuration values are loaded in the following order, values from later steps **may override** those from previous ones. These steps are done automatically and are described here only in order to explain the behavior:
+
+1. Default configuration option values from  ``Kconfig`` files are loaded, together with the relationships between them.
+2. If ``sdkconfig.defaults`` file is found, default values from this file are loaded.
+3. If present, ``sdkconfig`` file is loaded.
+
+When the configuration is saved, the values in the ``sdkconfig`` file are updated, as well as those in ``sdkconfig.h``, ``sdkconfig.cmake`` and ``sdkconfig.json``.
+
+Configuration with ``idf.py menuconfig``
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Using the ``idf.py menuconfig`` command in terminal or command line is the most system and IDE agnostic way of configuration. This command opens a TUI (Text-based User Interface) where user can set the configuration options. Navigation is realized by arrow keys, other hotkeys are described in the lower part of the window.
+
+.. image:: /../_static/menuconfig-screen.png
+
+Configuration with ESP-IDF Plugin for Visual Studio Code
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+After successful `installation <https://github.com/espressif/vscode-esp-idf-extension/blob/master/docs/tutorial/install.md>`_ of the ESP-IDF plugin for Visual Studio Code, follow their `Basic Use document <https://github.com/espressif/vscode-esp-idf-extension/blob/master/docs/tutorial/basic_use.md>`_ and search for the **Configuration Editor** option.
+
+Configuration with ESP-IDE
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+We also provide `plugin for Eclipse IDE <https://github.com/espressif/idf-eclipse-plugin/blob/master/README.md#Installation>`_. To edit the project configuration, follow `our documentation about SDK configuration <https://github.com/espressif/idf-eclipse-plugin/blob/master/README.md#sdk-configuration-editor>`_
+
+.. note::
+
+    If you are using another IDE/plugin, please refer to the documentation of the IDE/plugin or use command line command ``idf.py menuconfig``.
+
+.. _configs-in-C-Cmake:
+
+How to Use Configuration Variables in C Code and CMake
+------------------------------------------------------
+
+When the configuration is being saved to ``sdkconfig`` file, it is also saved in several different formats, including ``sdkconfig.h`` and ``sdkconfig.cmake``. The values in these files can be used in C code and CMake scripts.
+
+Example of using configuration options in C code:
+
+.. code-block:: c
+
+    // Contents of sdkconfig.h file (generated automatically, it should NOT be changed manually)
+    //(...)
+    #define CONFIG_USE_WARP 1
+    #define CONFIG_WARP_SPEED 42
+    //(...)
+
+.. code-block:: c
+
+    // Contents of C code file
+    #include "sdkconfig.h"
+    (...)
+    #if CONFIG_USE_WARP
+        set_warp_speed(CONFIG_WARP_SPEED);
+    #else
+        set_warp_speed(0);
+    #endif
+
+Example of using configuration options in CMake script:
+
+.. code-block:: cmake
+
+    # Contents of sdkconfig.cmake file (generated automatically, it should NOT be changed manually)
+    #(...)
+    set(CONFIG_USE_WARP 1)
+    set(CONFIG_WARP_SPEED 42)
+    #(...)
+
+.. code-block:: cmake
+
+        # Contents of CMakeLists.txt file
+        #(...)
+        if(CONFIG_USE_WARP)
+            set(WARP_SPEED ${CONFIG_WARP_SPEED})
+        else()
+            set(WARP_SPEED 0)
+        endif()
+        #(...)
+
+.. _project-wide-config-options:
+
+Defining New Configuration Options for the Project
+--------------------------------------------------
+
+Some applications can get very complex and require a lot of configuration options. In such cases, it is useful to define new configuration options for the project. Similar to components, the application can have its own configuration options. These options are defined in the  ``Kconfig`` or ``Kconfig.projbuild`` file in the ``main`` folder of the project. The process is the same as :ref:`defining new configuration options for components <component-configuration-guide>`, only with **different location** location of the ``Kconfig`` or ``Kconfig.projbuild`` file (``main`` instead of the root folder).
+
diff --git a/docs/en/api-guides/lwip.rst b/docs/en/api-guides/lwip.rst
index 462ded4e9eb..77a6c281c1c 100644
--- a/docs/en/api-guides/lwip.rst
+++ b/docs/en/api-guides/lwip.rst
@@ -31,9 +31,9 @@ Some common lwIP app APIs are supported indirectly by ESP-IDF:
 
     DNS server configuration in lwIP is global, not interface-specific. If you are using multiple network interfaces with distinct DNS servers, exercise caution to prevent inadvertent overwrites of one interface's DNS settings when acquiring a DHCP lease from another interface.
 
-- Simple Network Time Protocol (SNTP) is also supported via the :doc:`/api-reference/network/esp_netif`, or directly via the :component_file:`lwip/include/apps/esp_sntp.h` functions, which also provide thread-safe API to :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` functions, see also :ref:`system-time-sntp-sync`.
+- Simple Network Time Protocol (SNTP) is also supported via the :doc:`/api-reference/network/esp_netif`, or directly via the :component_file:`lwip/include/apps/esp_sntp.h` functions, which also provide thread-safe API to :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` functions, see also :ref:`system-time-sntp-sync`. For implementation details, see :example:`protocols/sntp`. This example demonstrates how to use the LwIP SNTP module to obtain time from internet servers, configure the synchronization method and interval, and retrieve time using the SNTP-over-DHCP module.
 - ICMP Ping is supported using a variation on the lwIP ping API, see :doc:`/api-reference/protocols/icmp_echo`.
-- ICMPv6 Ping, supported by lwIP's ICMPv6 Echo API, is used to test IPv6 network connectivity. For more information, see :example:`protocols/sockets/icmpv6_ping`.
+- ICMPv6 Ping, supported by lwIP's ICMPv6 Echo API, is used to test IPv6 network connectivity. For more information, see :example:`protocols/sockets/icmpv6_ping`. This example demonstrates how to use the network interface to discover an IPv6 address, create a raw ICMPv6 socket, send an ICMPv6 Echo Request to a destination IPv6 address, and wait for an Echo Reply from the target.
 - NetBIOS lookup is available using the standard lwIP API. :example:`protocols/http_server/restful_server` has the option to demonstrate using NetBIOS to look up a host on the LAN.
 - mDNS uses a different implementation to the lwIP default mDNS, see :doc:`/api-reference/protocols/mdns`. But lwIP can look up mDNS hosts using standard APIs such as ``gethostbyname()`` and the convention ``hostname.local``, provided the :ref:`CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES` setting is enabled.
 - The PPP implementation in lwIP can be used to create PPPoS (PPP over serial) interface in ESP-IDF. Please refer to the documentation of the :doc:`/api-reference/network/esp_netif` component to create and configure a PPP network interface, by means of the ``ESP_NETIF_DEFAULT_PPP()`` macro defined in :component_file:`esp_netif/include/esp_netif_defaults.h`. Additional runtime settings are provided via :component_file:`esp_netif/include/esp_netif_ppp.h`. PPPoS interfaces are typically used to interact with NBIoT/GSM/LTE modems. More application-level friendly API is supported by the `esp_modem <https://components.espressif.com/component/espressif/esp_modem>`_ library, which uses this PPP lwIP module behind the scenes.
@@ -43,7 +43,7 @@ BSD Sockets API
 
 The BSD Sockets API is a common cross-platform TCP/IP sockets API that originated in the Berkeley Standard Distribution of UNIX but is now standardized in a section of the POSIX specification. BSD Sockets are sometimes called POSIX Sockets or Berkeley Sockets.
 
-As implemented in ESP-IDF, lwIP supports all of the common usages of the BSD Sockets API.
+As implemented in ESP-IDF, lwIP supports all of the common usages of the BSD Sockets API. However, not all operations are fully thread-safe, and simultaneous reads and writes from multiple threads may require additional synchronization mechanisms, see :ref:`lwip-limitations` for more details.
 
 References
 ^^^^^^^^^^
@@ -53,17 +53,24 @@ A wide range of BSD Sockets reference materials are available, including:
 - `Single UNIX Specification - BSD Sockets page <https://pubs.opengroup.org/onlinepubs/007908799/xnsix.html>`_
 - `Berkeley Sockets - Wikipedia page <https://en.wikipedia.org/wiki/Berkeley_sockets>`_
 
-Examples
-^^^^^^^^
+Application Examples
+^^^^^^^^^^^^^^^^^^^^
 
 A number of ESP-IDF examples show how to use the BSD Sockets APIs:
 
-- :example:`protocols/sockets/tcp_server`
-- :example:`protocols/sockets/tcp_client`
-- :example:`protocols/sockets/udp_server`
-- :example:`protocols/sockets/udp_client`
-- :example:`protocols/sockets/udp_multicast`
-- :example:`protocols/http_request`: this simplified example uses a TCP socket to send an HTTP request, but :doc:`/api-reference/protocols/esp_http_client` is a much better option for sending HTTP requests
+- :example:`protocols/sockets/non_blocking` demonstrates how to configure and run a non-blocking TCP client and server, supporting both IPv4 and IPv6 protocols.
+
+- :example:`protocols/sockets/tcp_server` demonstrates how to create a TCP server that accepts client connection requests and receives data.
+
+- :example:`protocols/sockets/tcp_client` demonstrates how to create a TCP client that connects to a server using a predefined IP address and port.
+
+- :example:`protocols/sockets/tcp_client_multi_net` demonstrates how to use Ethernet and Wi-Fi interfaces together, connect to both simultaneously, create a TCP client for each interface, and send a basic HTTP request and response.
+
+- :example:`protocols/sockets/udp_server` demonstrates how to create a UDP server that receives client connection requests and data.
+
+- :example:`protocols/sockets/udp_client` demonstrates how to create a UDP client that connects to a server using a predefined IP address and port.
+
+- :example:`protocols/sockets/udp_multicast` demonstrates how to use the IPV4 and IPV6 UDP multicast features via the BSD-style sockets interface.
 
 Supported Functions
 ^^^^^^^^^^^^^^^^^^^
@@ -454,9 +461,13 @@ This approach may not work for function-like macros, as there is no guarantee th
 
 Alternatively, you can define your function-like macro in a header file which will be pre-included as an lwIP hook file, see :ref:`lwip-custom-hooks`.
 
+.. _lwip-limitations:
+
 Limitations
 ^^^^^^^^^^^
 
+lwIP in ESP-IDF supports thread safety in certain scenarios, but with limitations. It is possible to perform read, write, and close operations from different threads on the same socket simultaneously. However, performing multiple reads or multiple writes from more than one thread on the same socket at the same time is not supported. Applications that require simultaneous reads or writes from multiple threads on the same socket must implement additional synchronization mechanisms, such as locking around socket operations.
+
 ESP-IDF additions to lwIP still suffer from the global DNS limitation, described in :ref:`lwip-dns-limitation`. To address this limitation from application code, the ``FALLBACK_DNS_SERVER_ADDRESS()`` macro can be utilized to define a global DNS fallback server accessible from all interfaces. Alternatively, you have the option to maintain per-interface DNS servers and reconfigure them whenever the default interface changes.
 
 The number of IP addresses returned by network database APIs such as ``getaddrinfo()`` and ``gethostbyname()`` is restricted by the macro ``DNS_MAX_HOST_IP``. By default, the value of this macro is set to 1.
diff --git a/docs/en/api-guides/partition-tables.rst b/docs/en/api-guides/partition-tables.rst
index 9da55858a1a..b279cdaa65b 100644
--- a/docs/en/api-guides/partition-tables.rst
+++ b/docs/en/api-guides/partition-tables.rst
@@ -17,55 +17,76 @@ The simplest way to use the partition table is to open the project configuration
 * "Single factory app, no OTA"
 * "Factory app, two OTA definitions"
 
-In both cases the factory app is flashed at offset 0x10000. If you execute `idf.py partition-table` then it will print a summary of the partition table.
+In both cases the factory app is flashed at offset 0x10000. If you execute ``idf.py partition-table`` then it will print a summary of the partition table.
 
 Built-in Partition Tables
 -------------------------
 
-Here is the summary printed for the "Single factory app, no OTA" configuration::
+Here is the summary printed for the "Single factory app, no OTA" configuration:
 
-  # ESP-IDF Partition Table
-  # Name,   Type, SubType, Offset,  Size, Flags
-  nvs,      data, nvs,     0x9000,  0x6000,
-  phy_init, data, phy,     0xf000,  0x1000,
-  factory,  app,  factory, 0x10000, 1M,
+.. code-block:: none
 
-* At a 0x10000 (64 KB) offset in the flash is the app labelled "factory". The bootloader will run this app by default.
+    # ESP-IDF Partition Table
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     0x9000,  0x6000,
+    phy_init, data, phy,     0xf000,  0x1000,
+    factory,  app,  factory, 0x10000, 1M,
+
+* At a 0x10000 (64 KB) offset in the flash is the app labelled "factory". The bootloader runs this app by default.
 * There are also two data regions defined in the partition table for storing NVS library partition and PHY init data.
 
-Here is the summary printed for the "Factory app, two OTA definitions" configuration::
+Here is the summary printed for the "Factory app, two OTA definitions" configuration:
+
+.. code-block:: none
 
-  # ESP-IDF Partition Table
-  # Name,   Type, SubType, Offset,  Size, Flags
-  nvs,      data, nvs,     0x9000,  0x4000,
-  otadata,  data, ota,     0xd000,  0x2000,
-  phy_init, data, phy,     0xf000,  0x1000,
-  factory,  app,  factory, 0x10000,  1M,
-  ota_0,    app,  ota_0,   0x110000, 1M,
-  ota_1,    app,  ota_1,   0x210000, 1M,
+    # ESP-IDF Partition Table
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     0x9000,  0x4000,
+    otadata,  data, ota,     0xd000,  0x2000,
+    phy_init, data, phy,     0xf000,  0x1000,
+    factory,  app,  factory, 0x10000,  1M,
+    ota_0,    app,  ota_0,   0x110000, 1M,
+    ota_1,    app,  ota_1,   0x210000, 1M,
 
 * There are now three app partition definitions. The type of the factory app (at 0x10000) and the next two "OTA" apps are all set to "app", but their subtypes are different.
 * There is also a new "otadata" slot, which holds the data for OTA updates. The bootloader consults this data in order to know which app to execute. If "ota data" is empty, it will execute the factory app.
 
 Creating Custom Tables
--------------------------
+----------------------
 
 If you choose "Custom partition table CSV" in menuconfig then you can also enter the name of a CSV file (in the project directory) to use for your partition table. The CSV file can describe any number of definitions for the table you need.
 
-The CSV format is the same format as printed in the summaries shown above. However, not all fields are required in the CSV. For example, here is the "input" CSV for the OTA partition table::
+The CSV format is the same format as printed in the summaries shown above. However, not all fields are required in the CSV. For example, here is the "input" CSV for the OTA partition table:
+
+.. code-block:: none
 
-  # Name,   Type, SubType,  Offset,   Size,  Flags
-  nvs,      data, nvs,      0x9000,  0x4000
-  otadata,  data, ota,      0xd000,  0x2000
-  phy_init, data, phy,      0xf000,  0x1000
-  factory,  app,  factory,  0x10000,  1M
-  ota_0,    app,  ota_0,    ,         1M
-  ota_1,    app,  ota_1,    ,         1M
-  nvs_key,  data, nvs_keys, ,        0x1000
+    # Name,   Type, SubType,  Offset,   Size,  Flags
+    nvs,      data, nvs,      0x9000,  0x4000
+    otadata,  data, ota,      0xd000,  0x2000
+    phy_init, data, phy,      0xf000,  0x1000
+    factory,  app,  factory,  0x10000,  1M
+    ota_0,    app,  ota_0,    ,         1M
+    ota_1,    app,  ota_1,    ,         1M
+    nvs_key,  data, nvs_keys, ,        0x1000
 
 * Whitespace between fields is ignored, and so is any line starting with # (comments).
 * Each non-comment line in the CSV file is a partition definition.
-* The "Offset" field for each partition is empty. The gen_esp32part.py tool fills in each blank offset, starting after the partition table and making sure each partition is aligned correctly.
+* The ``Offset`` field for each partition is empty. The ``gen_esp32part.py`` tool fills in each blank offset, starting after the partition table and making sure each partition is aligned correctly.
+
+Here is an example of a CSV partition table that includes bootloader and partition table partitions:
+
+.. code-block:: none
+
+    # ESP-IDF Partition Table
+    # Name,           Type,            SubType,  Offset,  Size,     Flags
+    bootloader,       bootloader,      primary,  N/A,     N/A,
+    partition_table,  partition_table, primary,  N/A,     N/A,
+    nvs,              data,            nvs,      ,        0x6000,
+    phy_init,         data,            phy,      ,        0x1000,
+    factory,          app,             factory,  ,        1M,
+    recoveryBloader,  bootloader,      recovery, N/A,     N/A,
+
+The ``gen_esp32part.py`` tool will replace each ``N/A`` with appropriate values based on the selected Kconfig options: {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} for the bootloader offset and :ref:`CONFIG_PARTITION_TABLE_OFFSET` for the partition table offset.
 
 Name Field
 ~~~~~~~~~~
@@ -75,20 +96,27 @@ Name field can be any meaningful name. It is not significant to the {IDF_TARGET_
 Type Field
 ~~~~~~~~~~
 
-Partition type field can be specified as ``app`` (0x00) or ``data`` (0x01). Or it can be a number 0-254 (or as hex 0x00-0xFE). Types 0x00-0x3F are reserved for ESP-IDF core functions.
+Partition type field can be specified as a name or a number 0-254 (or as hex 0x00-0xFE). Types 0x00-0x3F are reserved for ESP-IDF core functions.
 
-If your app needs to store data in a format not already supported by ESP-IDF, then please add a custom partition type value in the range 0x40-0xFE.
+- ``app`` (0x00),
+- ``data`` (0x01),
+- ``bootloader`` (0x02). By default, this partition is not included in any CSV partition table files in ESP-IDF because it is not required and does not impact the system's functionality. It is only useful for the bootloader OTA updates and flash partitioning. Even if this partition is not present in the CSV file, it is still possible to perform the OTA.
+- ``partition_table`` (0x03). By default, this partition also is not included in any CSV partition table files in ESP-IDF.
+- 0x40-0xFE are reserved for **custom partition types**. If your app needs to store data in a format not already supported by ESP-IDF, then use a value from this range.
 
 See :cpp:type:`esp_partition_type_t` for the enum definitions for ``app`` and ``data`` partitions.
 
-If writing in C++ then specifying a application-defined partition type requires casting an integer to :cpp:type:`esp_partition_type_t` in order to use it with the :ref:`partition API<api-reference-partition-table>`. For example::
+If writing in C++ then specifying a application-defined partition type requires casting an integer to :cpp:type:`esp_partition_type_t` in order to use it with the :ref:`partition API<api-reference-partition-table>`. For example:
+
+.. code-block:: none
 
     static const esp_partition_type_t APP_PARTITION_TYPE_A = (esp_partition_type_t)0x40;
 
-The ESP-IDF bootloader ignores any partition types other than ``app`` (0x00) and ``data`` (0x01).
+The bootloader ignores any partition types other than ``app`` (0x00) and ``data`` (0x01).
 
 SubType
 ~~~~~~~
+
 {IDF_TARGET_ESP_PHY_REF:default = ":ref:`CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION`", esp32p4, esp32c5, esp32c61="NOT UPDATED YET"}
 
 The 8-bit SubType field is specific to a given partition type. ESP-IDF currently only specifies the meaning of the subtype field for ``app`` and ``data`` partition types.
@@ -97,53 +125,68 @@ See enum :cpp:type:`esp_partition_subtype_t` for the full list of subtypes defin
 
 * When type is ``app``, the SubType field can be specified as ``factory`` (0x00), ``ota_0`` (0x10) ... ``ota_15`` (0x1F) or ``test`` (0x20).
 
-  - ``factory`` (0x00) is the default app partition. The bootloader will execute the factory app unless there it sees a partition of type data/ota, in which case it reads this partition to determine which OTA image to boot.
+    - ``factory`` (0x00) is the default app partition. The bootloader will execute the factory app unless there it sees a partition of type data/ota, in which case it reads this partition to determine which OTA image to boot.
+
+        - OTA never updates the factory partition.
+        - If you want to conserve flash usage in an OTA project, you can remove the factory partition and use ``ota_0`` instead.
+
+    - ``ota_0`` (0x10) ... ``ota_15`` (0x1F) are the OTA app slots. When :doc:`OTA <../api-reference/system/ota>` is in use, the OTA data partition configures which app slot the bootloader should boot. When using OTA, an application should have at least two OTA application slots (``ota_0`` & ``ota_1``). Refer to the :doc:`OTA documentation <../api-reference/system/ota>` for more details.
+    - ``test`` (0x20) is a reserved subtype for factory test procedures. It will be used as the fallback boot partition if no other valid app partition is found. It is also possible to configure the bootloader to read a GPIO input during each boot, and boot this partition if the GPIO is held low, see :ref:`bootloader_boot_from_test_firmware`.
+
+* When type is ``bootloader``, the SubType field can be specified as:
+
+  - ``primary`` (0x00). This is the 2nd stage bootloader, located at the {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} address in flash memory. The tool automatically determines the appropriate size and offset for this subtype, so any size or offset specified for this subtype will be ignored. You can either leave these fields blank or use ``N/A`` as a placeholder.
+  - ``ota`` (0x01). This is a temporary bootloader partition used by the bootloader OTA update functionality to download a new image. The tool ignores the size for this subtype, allowing you to leave it blank or use ``N/A``. You can only specify an offset, or leave it blank to have the tool calculate it based on the offsets of previously used partitions.
+  - ``recovery`` (0x02). This is the recovery bootloader partition used for safely performing OTA updates to the bootloader. The ``gen_esp32part.py`` tool automatically determines the address and size for this partition, so you can leave these fields blank or use ``N/A`` as a placeholder. The address must match an eFuse field, which is defined through a Kconfig option. If the normal bootloader loading path fails, the ROM bootloader will attempt to load the recovery partition at the address specified by the eFuse field.
 
-    - OTA never updates the factory partition.
-    - If you want to conserve flash usage in an OTA project, you can remove the factory partition and use ``ota_0`` instead.
+  The size of the bootloader type is calculated by the ``gen_esp32part.py`` tool  based on the specified ``--offset`` (the partition table offset) and ``--primary-partition-offset`` arguments. Specifically, the bootloader size is defined as (:ref:`CONFIG_PARTITION_TABLE_OFFSET` - {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}). This calculated size applies to all subtypes of the bootloader.
 
-  - ``ota_0`` (0x10) ... ``ota_15`` (0x1F) are the OTA app slots. When :doc:`OTA <../api-reference/system/ota>` is in use, the OTA data partition configures which app slot the bootloader should boot. When using OTA, an application should have at least two OTA application slots (``ota_0`` & ``ota_1``). Refer to the :doc:`OTA documentation <../api-reference/system/ota>` for more details.
-  - ``test`` (0x20) is a reserved subtype for factory test procedures. It will be used as the fallback boot partition if no other valid app partition is found. It is also possible to configure the bootloader to read a GPIO input during each boot, and boot this partition if the GPIO is held low, see :ref:`bootloader_boot_from_test_firmware`.
+* When type is ``partition_table``, the SubType field can be specified as:
+
+  - ``primary`` (0x00). This is the primary partition table, located at the :ref:`CONFIG_PARTITION_TABLE_OFFSET` address in flash memory. The tool automatically determines the appropriate size and offset for this subtype, so any size or offset specified for this subtype will be ignored. You can either leave these fields blank or use ``N/A`` as a placeholder.
+  - ``ota`` (0x01). It is a temporary partition table partition used by the partition table OTA update functionality for downloading a new image. The tool ignores the size for this subtype, allowing you to leave it blank or use ``N/A``. You can specify an offset, or leave it blank, in which case the tool will calculate it based on the offsets of previously allocated partitions.
+
+  The size for the ``partition_table`` type is fixed at ``0x1000`` and applies uniformly across all subtypes of ``partition_table``.
 
 * When type is ``data``, the subtype field can be specified as ``ota`` (0x00), ``phy`` (0x01), ``nvs`` (0x02), nvs_keys (0x04), or a range of other component-specific subtypes (see :cpp:type:`subtype enum <esp_partition_subtype_t>`).
 
-  - ``ota`` (0) is the :ref:`OTA data partition <ota_data_partition>` which stores information about the currently selected OTA app slot. This partition should be 0x2000 bytes in size. Refer to the :ref:`OTA documentation <ota_data_partition>` for more details.
-  - ``phy`` (1) is for storing PHY initialisation data. This allows PHY to be configured per-device, instead of in firmware.
+    - ``ota`` (0) is the :ref:`OTA data partition <ota_data_partition>` which stores information about the currently selected OTA app slot. This partition should be 0x2000 bytes in size. Refer to the :ref:`OTA documentation <ota_data_partition>` for more details.
+    - ``phy`` (1) is for storing PHY initialisation data. This allows PHY to be configured per-device, instead of in firmware.
 
-    - In the default configuration, the phy partition is not used and PHY initialisation data is compiled into the app itself. As such, this partition can be removed from the partition table to save space.
-    - To load PHY data from this partition, open the project configuration menu (``idf.py menuconfig``) and enable {IDF_TARGET_ESP_PHY_REF} option. You will also need to flash your devices with phy init data as the esp-idf build system does not do this automatically.
-  - ``nvs`` (2) is for the :doc:`Non-Volatile Storage (NVS) API <../api-reference/storage/nvs_flash>`.
+        - In the default configuration, the phy partition is not used and PHY initialisation data is compiled into the app itself. As such, this partition can be removed from the partition table to save space.
+        - To load PHY data from this partition, open the project configuration menu (``idf.py menuconfig``) and enable {IDF_TARGET_ESP_PHY_REF} option. You will also need to flash your devices with phy init data as the esp-idf build system does not do this automatically.
+    - ``nvs`` (2) is for the :doc:`Non-Volatile Storage (NVS) API <../api-reference/storage/nvs_flash>`.
 
-    - NVS is used to store per-device PHY calibration data (different to initialisation data).
+        - NVS is used to store per-device PHY calibration data (different to initialisation data).
 
-    .. only:: SOC_WIFI_SUPPORTED
+        .. only:: SOC_WIFI_SUPPORTED
 
-        - NVS is used to store Wi-Fi data if the :doc:`esp_wifi_set_storage(WIFI_STORAGE_FLASH) <../api-reference/network/esp_wifi>` initialization function is used.
+            - NVS is used to store Wi-Fi data if the :doc:`esp_wifi_set_storage(WIFI_STORAGE_FLASH) <../api-reference/network/esp_wifi>` initialization function is used.
 
-    - The NVS API can also be used for other application data.
-    - It is strongly recommended that you include an NVS partition of at least 0x3000 bytes in your project.
-    - If using NVS API to store a lot of data, increase the NVS partition size from the default 0x6000 bytes.
-  - ``nvs_keys`` (4) is for the NVS key partition. See :doc:`Non-Volatile Storage (NVS) API <../api-reference/storage/nvs_flash>` for more details.
+        - The NVS API can also be used for other application data.
+        - It is strongly recommended that you include an NVS partition of at least 0x3000 bytes in your project.
+        - If using NVS API to store a lot of data, increase the NVS partition size from the default 0x6000 bytes.
+    - ``nvs_keys`` (4) is for the NVS key partition. See :doc:`Non-Volatile Storage (NVS) API <../api-reference/storage/nvs_flash>` for more details.
 
-    - It is used to store NVS encryption keys when `NVS Encryption` feature is enabled.
-    - The size of this partition should be 4096 bytes (minimum partition size).
+        - It is used to store NVS encryption keys when `NVS Encryption` feature is enabled.
+        - The size of this partition should be 4096 bytes (minimum partition size).
 
-  - There are other predefined data subtypes for data storage supported by ESP-IDF. These include:
+    - There are other predefined data subtypes for data storage supported by ESP-IDF. These include:
 
-    - ``coredump`` (0x03) is for storing core dumps while using a custom partition table CSV file. See :doc:`/api-guides/core_dump` for more details.
-    - ``efuse`` (0x05) is for emulating eFuse bits using :ref:`virtual-efuses`.
-    - ``undefined`` (0x06) is implicitly used for data partitions with unspecified (empty) subtype, but it is possible to explicitly mark them as undefined as well.
-    - ``fat`` (0x81) is for :doc:`/api-reference/storage/fatfs`.
-    - ``spiffs`` (0x82) is for :doc:`/api-reference/storage/spiffs`.
-    - ``littlefs`` (0x83) is for `LittleFS filesystem <https://github.com/littlefs-project/littlefs>`_. See :example:`storage/littlefs` example for more details.
+        - ``coredump`` (0x03) is for storing core dumps while using a custom partition table CSV file. See :doc:`/api-guides/core_dump` for more details.
+        - ``efuse`` (0x05) is for emulating eFuse bits using :ref:`virtual-efuses`.
+        - ``undefined`` (0x06) is implicitly used for data partitions with unspecified (empty) subtype, but it is possible to explicitly mark them as undefined as well.
+        - ``fat`` (0x81) is for :doc:`/api-reference/storage/fatfs`.
+        - ``spiffs`` (0x82) is for :doc:`/api-reference/storage/spiffs`.
+        - ``littlefs`` (0x83) is for `LittleFS filesystem <https://github.com/littlefs-project/littlefs>`_. See :example:`storage/littlefs` example for more details.
 
 .. Comment: ``esphttpd`` (0x80) was not added to the list because there is no docs section for it and it is not clear whether user should use it explicitly.
 
-  Other subtypes of ``data`` type are reserved for future ESP-IDF uses.
+    Other subtypes of ``data`` type are reserved for future ESP-IDF uses.
 
 * If the partition type is any application-defined value (range 0x40-0xFE), then ``subtype`` field can be any value chosen by the application (range 0x00-0xFE).
 
-  Note that when writing in C++, an application-defined subtype value requires casting to type :cpp:type:`esp_partition_subtype_t` in order to use it with the :ref:`partition API <api-reference-partition-table>`.
+    Note that when writing in C++, an application-defined subtype value requires casting to type :cpp:type:`esp_partition_subtype_t` in order to use it with the :ref:`partition API <api-reference-partition-table>`.
 
 Extra Partition SubTypes
 ~~~~~~~~~~~~~~~~~~~~~~~~
@@ -162,7 +205,9 @@ Offset & Size
     - Partitions of type ``app`` have to be placed at offsets aligned to 0x10000 (64 KB). If you leave the offset field blank, ``gen_esp32part.py`` will automatically align the partition. If you specify an unaligned offset for an ``app`` partition, the tool will return an error.
     - Partitions of type ``app`` should have the size aligned to the flash sector size (4 KB). If you specify an unaligned size for an ``app`` partition, the tool will return an error.
     :SOC_SECURE_BOOT_V1: - If Secure Boot V1 is enabled, then the partition of type ``app`` needs to have size aligned to 0x10000 (64 KB) boundary.
+    :SOC_SECURE_BOOT_V1: - The ``bootloader`` offset and size are not affected by the Secure Boot V1 option. Whether Secure Boot V1 is enabled or not, the bootloader remains the same size and does not include the secure digest, which is flashed at offset 0x0 in the flash and occupies one sector (4096 bytes).
     - Sizes and offsets can be specified as decimal numbers, hex numbers with the prefix 0x, or size multipliers K or M (1024 and 1024*1024 bytes).
+    - For ``bootloader`` and ``partition_table`` types, specifying ``N/A`` for size and offset in the CSV file means that these values are automatically determined by the tool and cannot be manually defined. This requires setting the ``--offset`` and ``--primary-partition-offset`` arguments of ``gen_esp32part.py``.
 
 If you want the partitions in the partition table to work relative to any placement (:ref:`CONFIG_PARTITION_TABLE_OFFSET`) of the table itself, leave the offset field (in CSV file) for all partitions blank. Similarly, if changing the partition table offset then be aware that all blank partition offsets may change to match, and that any fixed offsets may now collide with the partition table (causing an error).
 
@@ -171,17 +216,25 @@ Flags
 
 Two flags are currently supported, ``encrypted`` and ``readonly``:
 
-  - If ``encrypted`` flag is set, the partition will be encrypted if :doc:`/security/flash-encryption` is enabled.
+    - If ``encrypted`` flag is set, the partition will be encrypted if :doc:`/security/flash-encryption` is enabled.
+
+    .. note::
+
+      The following type partitions will always be encrypted, regardless of whether this flag is set or not:
 
-  .. note::
+      .. list::
 
-      ``app`` type partitions will always be encrypted, regardless of whether this flag is set or not.
+          - ``app``,
+          - ``bootloader``,
+          - ``partition_table``,
+          - type ``data`` and subtype ``ota``,
+          - type ``data`` and subtype ``nvs_keys``.
 
-  - If ``readonly`` flag is set, the partition will be read-only. This flag is only supported for ``data`` type partitions except ``ota``` and ``coredump``` subtypes. This flag can help to protect against accidental writes to a partition that contains critical device-specific configuration data, e.g., factory data partition.
+    - If ``readonly`` flag is set, the partition will be read-only. This flag is only supported for ``data`` type partitions except ``ota`` and ``coredump`` subtypes. This flag can help to protect against accidental writes to a partition that contains critical device-specific configuration data, e.g., factory data partition.
 
-  .. note::
+    .. note::
 
-      Using C file I/O API to open a file (``fopen```) in any write mode (``w``, ``w+``, ``a``, ``a+``, ``r+``) will fail and return ``NULL``. Using ``open`` with any other flag than ``O_RDONLY`` will fail and return ``-1`` while ``errno`` global variable will be set to ``EROFS``. This is also true for any other POSIX syscall function performing write or erase operations. Opening a handle in read-write mode for NVS on a read-only partition will fail and return :c:macro:`ESP_ERR_NOT_ALLOWED` error code. Using a lower level API like ``esp_partition``, ``spi_flash``, etc. to write to a read-only partition will result in :c:macro:`ESP_ERR_NOT_ALLOWED` error code.
+        Using C file I/O API to open a file (``fopen``) in any write mode (``w``, ``w+``, ``a``, ``a+``, ``r+``) will fail and return ``NULL``. Using ``open`` with any other flag than ``O_RDONLY`` will fail and return ``-1`` while ``errno`` global variable will be set to ``EROFS``. This is also true for any other POSIX syscall function performing write or erase operations. Opening a handle in read-write mode for NVS on a read-only partition will fail and return :c:macro:`ESP_ERR_NOT_ALLOWED` error code. Using a lower level API like ``esp_partition``, ``spi_flash``, etc. to write to a read-only partition will result in :c:macro:`ESP_ERR_NOT_ALLOWED` error code.
 
 You can specify multiple flags by separating them with a colon. For example, ``encrypted:readonly``.
 
@@ -192,17 +245,23 @@ The partition table which is flashed to the {IDF_TARGET_NAME} is in a binary for
 
 If you configure the partition table CSV name in the project configuration (``idf.py menuconfig``) and then build the project or run ``idf.py partition-table``, this conversion is done as part of the build process.
 
-To convert CSV to Binary manually::
+To convert CSV to Binary manually:
+
+.. code-block:: none
+
+    python gen_esp32part.py input_partitions.csv binary_partitions.bin
+
+To convert binary format back to CSV manually:
 
-  python gen_esp32part.py input_partitions.csv binary_partitions.bin
+.. code-block:: none
 
-To convert binary format back to CSV manually::
+    python gen_esp32part.py binary_partitions.bin input_partitions.csv
 
-  python gen_esp32part.py binary_partitions.bin input_partitions.csv
+To display the contents of a binary partition table on stdout (this is how the summaries displayed when running ``idf.py partition-table`` are generated:
 
-To display the contents of a binary partition table on stdout (this is how the summaries displayed when running ``idf.py partition-table`` are generated::
+.. code-block:: none
 
-  python gen_esp32part.py binary_partitions.bin
+    python gen_esp32part.py binary_partitions.bin
 
 Partition Size Checks
 ---------------------
@@ -216,7 +275,7 @@ Currently these checks are performed for the following binaries:
 
 .. note::
 
-   Although the build process will fail if the size check returns an error, the binary files are still generated and can be flashed (although they may not work if they are too large for the available space.)
+    Although the build process will fail if the size check returns an error, the binary files are still generated and can be flashed (although they may not work if they are too large for the available space.)
 
 MD5 Checksum
 ~~~~~~~~~~~~
@@ -242,7 +301,7 @@ A manual flashing command is also printed as part of ``idf.py partition-table``
 
 .. note::
 
-  Note that updating the partition table does not erase data that may have been stored according to the old partition table. You can use ``idf.py erase-flash`` (or ``esptool.py erase_flash``) to erase the entire flash contents.
+    Note that updating the partition table does not erase data that may have been stored according to the old partition table. You can use ``idf.py erase-flash`` (or ``esptool.py erase_flash``) to erase the entire flash contents.
 
 
 Partition Tool (``parttool.py``)
@@ -250,10 +309,10 @@ Partition Tool (``parttool.py``)
 
 The component `partition_table` provides a tool :component_file:`parttool.py <partition_table/parttool.py>` for performing partition-related operations on a target device. The following operations can be performed using the tool:
 
-  - reading a partition and saving the contents to a file (read_partition)
-  - writing the contents of a file to a partition (write_partition)
-  - erasing a partition (erase_partition)
-  - retrieving info such as name, offset, size and flag ("encrypted") of a given partition (get_partition_info)
+    - reading a partition and saving the contents to a file (read_partition)
+    - writing the contents of a file to a partition (write_partition)
+    - erasing a partition (erase_partition)
+    - retrieving info such as name, offset, size and flag ("encrypted") of a given partition (get_partition_info)
 
 The tool can either be imported and used from another Python script or invoked from shell script for users wanting to perform operation programmatically. This is facilitated by the tool's Python API and command-line interface, respectively.
 
@@ -264,38 +323,38 @@ Before anything else, make sure that the `parttool` module is imported.
 
 .. code-block:: python
 
-  import sys
-  import os
+    import sys
+    import os
 
-  idf_path = os.environ["IDF_PATH"]  # get value of IDF_PATH from environment
-  parttool_dir = os.path.join(idf_path, "components", "partition_table")  # parttool.py lives in $IDF_PATH/components/partition_table
+    idf_path = os.environ["IDF_PATH"]  # get value of IDF_PATH from environment
+    parttool_dir = os.path.join(idf_path, "components", "partition_table")  # parttool.py lives in $IDF_PATH/components/partition_table
 
-  sys.path.append(parttool_dir)  # this enables Python to find parttool module
-  from parttool import *  # import all names inside parttool module
+    sys.path.append(parttool_dir)  # this enables Python to find parttool module
+    from parttool import *  # import all names inside parttool module
 
 The starting point for using the tool's Python API to do is create a `ParttoolTarget` object:
 
 .. code-block:: python
 
-  # Create a parttool.py target device connected on serial port /dev/ttyUSB1
-  target = ParttoolTarget("/dev/ttyUSB1")
+    # Create a parttool.py target device connected on serial port /dev/ttyUSB1
+    target = ParttoolTarget("/dev/ttyUSB1")
 
 The created object can now be used to perform operations on the target device:
 
 .. code-block:: python
 
-  # Erase partition with name 'storage'
+    # Erase partition with name 'storage'
   target.erase_partition(PartitionName("storage"))
 
-  # Read partition with type 'data' and subtype 'spiffs' and save to file 'spiffs.bin'
-  target.read_partition(PartitionType("data", "spiffs"), "spiffs.bin")
+    # Read partition with type 'data' and subtype 'spiffs' and save to file 'spiffs.bin'
+    target.read_partition(PartitionType("data", "spiffs"), "spiffs.bin")
 
-  # Write to partition 'factory' the contents of a file named 'factory.bin'
-  target.write_partition(PartitionName("factory"), "factory.bin")
+    # Write to partition 'factory' the contents of a file named 'factory.bin'
+    target.write_partition(PartitionName("factory"), "factory.bin")
 
-  # Print the size of default boot partition
-  storage = target.get_partition_info(PARTITION_BOOT_DEFAULT)
-  print(storage.size)
+    # Print the size of default boot partition
+    storage = target.get_partition_info(PARTITION_BOOT_DEFAULT)
+    print(storage.size)
 
 The partition to operate on is specified using `PartitionName` or `PartitionType` or PARTITION_BOOT_DEFAULT. As the name implies, these can be used to refer to partitions of a particular name, type-subtype combination, or the default boot partition.
 
@@ -308,53 +367,54 @@ The command-line interface of `parttool.py` has the following structure:
 
 .. code-block:: bash
 
-  parttool.py [command-args] [subcommand] [subcommand-args]
+    parttool.py [command-args] [subcommand] [subcommand-args]
 
-  - command-args - These are arguments that are needed for executing the main command (parttool.py), mostly pertaining to the target device
-  - subcommand - This is the operation to be performed
-  - subcommand-args - These are arguments that are specific to the chosen operation
+    - command-args - These are arguments that are needed for executing the main command (parttool.py), mostly pertaining to the target device
+    - subcommand - This is the operation to be performed
+    - subcommand-args - These are arguments that are specific to the chosen operation
 
 .. code-block:: bash
 
-  # Erase partition with name 'storage'
-  parttool.py --port "/dev/ttyUSB1" erase_partition --partition-name=storage
+    # Erase partition with name 'storage'
+    parttool.py --port "/dev/ttyUSB1" erase_partition --partition-name=storage
 
-  # Read partition with type 'data' and subtype 'spiffs' and save to file 'spiffs.bin'
-  parttool.py --port "/dev/ttyUSB1" read_partition --partition-type=data --partition-subtype=spiffs --output "spiffs.bin"
+    # Read partition with type 'data' and subtype 'spiffs' and save to file 'spiffs.bin'
+    parttool.py --port "/dev/ttyUSB1" read_partition --partition-type=data --partition-subtype=spiffs --output "spiffs.bin"
 
-  # Write to partition 'factory' the contents of a file named 'factory.bin'
-  parttool.py --port "/dev/ttyUSB1" write_partition --partition-name=factory --input "factory.bin"
+    # Write to partition 'factory' the contents of a file named 'factory.bin'
+    parttool.py --port "/dev/ttyUSB1" write_partition --partition-name=factory --input "factory.bin"
 
-  # Print the size of default boot partition
-  parttool.py --port "/dev/ttyUSB1" get_partition_info --partition-boot-default --info size
+    # Print the size of default boot partition
+    parttool.py --port "/dev/ttyUSB1" get_partition_info --partition-boot-default --info size
 
 .. note::
-  If the device has already enabled ``Flash Encryption`` or ``Secure Boot``, attempting to use commands that modify the flash content, such as ``erase_partition`` or ``write_partition``, will result in an error. This error is generated by the erase command of ``esptool.py``, which is called first before writing. This error is done as a safety measure to prevent bricking your device.
 
-  ::
+    If the device has already enabled ``Flash Encryption`` or ``Secure Boot``, attempting to use commands that modify the flash content, such as ``erase_partition`` or ``write_partition``, will result in an error. This error is generated by the erase command of ``esptool.py``, which is called first before writing. This error is done as a safety measure to prevent bricking your device.
 
-    A fatal error occurred: Active security features detected, erasing flash is disabled as a safety measure. Use --force to override, please use with caution, otherwise it may brick your device!
+    .. code-block:: none
 
-  To work around this, you need use the ``--force`` flag with ``esptool.py``. Specifically, the ``parttool.py`` provides the ``--esptool-erase-args`` argument that help to pass this flag to ``esptool.py``.
+        A fatal error occurred: Active security features detected, erasing flash is disabled as a safety measure. Use --force to override, please use with caution, otherwise it may brick your device!
 
-  .. code-block:: bash
+    To work around this, you need use the ``--force`` flag with ``esptool.py``. Specifically, the ``parttool.py`` provides the ``--esptool-erase-args`` argument that help to pass this flag to ``esptool.py``.
 
-    # Erase partition with name 'storage'
-    # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force"
-    parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force erase_partition --partition-name=storage
+    .. code-block:: bash
 
-    # Write to partition 'factory' the contents of a file named 'factory.bin'
-    # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force"
-    parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force write_partition --partition-name=factory --input "factory.bin"
+        # Erase partition with name 'storage'
+        # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force"
+        parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force erase_partition --partition-name=storage
+
+        # Write to partition 'factory' the contents of a file named 'factory.bin'
+        # If Flash Encryption or Secure Boot are enabled then add "--esptool-erase-args=force"
+        parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force write_partition --partition-name=factory --input "factory.bin"
 
 More information can be obtained by specifying `--help` as argument:
 
 .. code-block:: bash
 
-  # Display possible subcommands and show main command argument descriptions
-  parttool.py --help
+    # Display possible subcommands and show main command argument descriptions
+    parttool.py --help
 
-  # Show descriptions for specific subcommand arguments
-  parttool.py [subcommand] --help
+    # Show descriptions for specific subcommand arguments
+    parttool.py [subcommand] --help
 
 .. _secure boot: security/secure-boot-v1.rst
diff --git a/docs/en/api-guides/performance/ram-usage.rst b/docs/en/api-guides/performance/ram-usage.rst
index b3a0d142cf7..61d3da46548 100644
--- a/docs/en/api-guides/performance/ram-usage.rst
+++ b/docs/en/api-guides/performance/ram-usage.rst
@@ -198,11 +198,11 @@ The following options will reduce IRAM usage of some ESP-IDF features:
    Using SRAM1 for IRAM
    ^^^^^^^^^^^^^^^^^^^^
 
-   The SRAM1 memory area is normally used for DRAM, but it is possible to use parts of it for IRAM with :ref:`CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM`. This memory would previously be reserved for DRAM data usage (e.g., ``.bss``) by the software bootloader and later added to the heap. After this option was introduced, the bootloader DRAM size was reduced to a value closer to what it normally actually needs.
+   The SRAM1 memory area is normally used for DRAM, but it is possible to use parts of it for IRAM with :ref:`CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM`. This memory would previously be reserved for DRAM data usage (e.g., ``.bss``) by the ESP-IDF second stage bootloader and later added to the heap. After this option was introduced, the bootloader DRAM size was reduced to a value closer to what it normally actually needs.
 
-   To use this option, ESP-IDF should be able to recognize that the new SRAM1 area is also a valid load address for an image segment. If the software bootloader was compiled before this option existed, then the bootloader will not be able to load the app that has code placed in this new extended IRAM area. This would typically happen if you are doing an OTA update, where only the app would be updated.
+   To use this option, ESP-IDF should be able to recognize that the new SRAM1 area is also a valid load address for an image segment. If the second stage bootloader was compiled before this option existed, then the bootloader will not be able to load the app that has code placed in this new extended IRAM area. This would typically happen if you are doing an OTA update, where only the app would be updated.
 
-   If the IRAM section were to be placed in an invalid area, then this would be detected during the boot-up process, and result in a failed boot:
+   If the IRAM section were to be placed in an invalid area, then this would be detected during the boot up process, and result in a failed boot:
 
    .. code-block:: text
 
@@ -210,7 +210,7 @@ The following options will reduce IRAM usage of some ESP-IDF features:
 
    .. warning::
 
-      Apps compiled with :ref:`CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM` may fail to boot, if used together with a software bootloader that was compiled before this config option was introduced. If you are using an older bootloader and updating over OTA, please test carefully before pushing any updates.
+      Apps compiled with :ref:`CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM` may fail to boot, if used together with a second stage bootloader that was compiled before this config option was introduced. If you are using an older bootloader and updating over OTA, please test carefully before pushing any updates.
 
    Any memory that ends up unused for static IRAM will be added to the heap.
 
diff --git a/docs/en/api-guides/performance/size.rst b/docs/en/api-guides/performance/size.rst
index f88f8a38bc9..7cfc916b400 100644
--- a/docs/en/api-guides/performance/size.rst
+++ b/docs/en/api-guides/performance/size.rst
@@ -194,6 +194,7 @@ These include:
 - :ref:`CONFIG_MBEDTLS_HAVE_TIME`
 - :ref:`CONFIG_MBEDTLS_ECDSA_DETERMINISTIC`
 - :ref:`CONFIG_MBEDTLS_SHA512_C`
+- :ref:`CONFIG_MBEDTLS_SHA3_C`
 - :ref:`CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS`
 - :ref:`CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS`
 - :ref:`CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION`
@@ -255,6 +256,23 @@ VFS
         * Enabling :ref:`CONFIG_HEAP_PLACE_FUNCTION_INTO_FLASH` can reduce the IRAM usage and binary size by placing the entirety of the heap functionalities in flash memory.
         :CONFIG_ESP_ROM_HAS_HEAP_TLSF: * Enabling :ref:`CONFIG_HEAP_TLSF_USE_ROM_IMPL` can reduce the IRAM usage and binary size by linking in the TLSF library of ROM implementation.
 
+
+.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED
+
+    Console
+    @@@@@@@@
+
+    For targets that support USB-Serial-JTAG, both the USB-Serial-JTAG and UART console output are enabled by default. If you only need one console, you can reduce the binary size and RAM usage by doing the following:
+
+    1. Disable the secondary console by setting :ref:`CONFIG_ESP_CONSOLE_SECONDARY` to ``CONFIG_ESP_CONSOLE_SECONDARY_NONE``.
+    2. Set :ref:`CONFIG_ESP_CONSOLE_UART` to use one of the following:
+
+      * ``UART`` reduces the binary size by around 2.5 KB.
+      * ``USB-Serial-JTAG`` reduces the binary size by around 10 KB and DRAM usage by around 1.5 KB.
+
+    Please note that these size reductions assume the UART/USB-Serial-JTAG driver code is not pulled into the app, if you already use these drivers for other purposes then the savings will be smaller.
+
+
 Bootloader Size
 ---------------
 
diff --git a/docs/en/api-guides/performance/speed.rst b/docs/en/api-guides/performance/speed.rst
index 0cce05a5717..c374a327462 100644
--- a/docs/en/api-guides/performance/speed.rst
+++ b/docs/en/api-guides/performance/speed.rst
@@ -301,9 +301,9 @@ Improving I/O Performance
 
 Using standard C library functions like ``fread`` and ``fwrite`` instead of platform-specific unbuffered syscalls such as ``read`` and ``write``, may result in slower performance.
 
-The ``fread`` and ``fwrite`` functions are designed for portability rather than speed, introducing some overhead due to their buffered nature. Check the example :example:`storage/fatfsgen` to see how to use these two functions.
+The ``fread`` and ``fwrite`` functions are designed for portability rather than speed, introducing some overhead due to their buffered nature. Check the example :example:`storage/fatfs/getting_started` to see how to use these two functions.
 
-In contrast, the ``read`` and ``write`` functions are standard POSIX APIs that can be used directly when working with FatFs through VFS, with ESP-IDF handling the underlying implementation. Check the example :example:`storage/perf_benchmark` to see how to use the two functions.
+In contrast, the ``read`` and ``write`` functions are standard POSIX APIs that can be used directly when working with FatFs through VFS, with ESP-IDF handling the underlying implementation. Check the example :example:`storage/fatfs/fs_operations` to see how to use the two functions.
 
 Additional tips are provided below, and further details can be found in :doc:`/api-reference/storage/fatfs`.
 
diff --git a/docs/en/api-guides/startup.rst b/docs/en/api-guides/startup.rst
index 91e1c425c0e..47555130a9f 100644
--- a/docs/en/api-guides/startup.rst
+++ b/docs/en/api-guides/startup.rst
@@ -9,7 +9,7 @@ The high level view of startup process is as follows:
 
 .. list::
 
-    1. :ref:`first-stage-bootloader` in ROM loads second-stage bootloader image to RAM (IRAM & DRAM) from flash offset {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}.
+    1. :ref:`first-stage-bootloader` loads the second stage bootloader image to RAM (IRAM & DRAM) from flash offset {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}.
 
     2. :ref:`second-stage-bootloader` loads partition table and main app image from flash. Main app incorporates both RAM segments and read-only segments mapped via flash cache.
 
@@ -21,8 +21,8 @@ This process is explained in detail in the following sections.
 
 .. _first-stage-bootloader:
 
-First Stage Bootloader
-^^^^^^^^^^^^^^^^^^^^^^
+First stage (ROM) bootloader
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 .. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES
 
@@ -71,7 +71,7 @@ Second Stage Bootloader
 
 In ESP-IDF, the binary image which resides at offset {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} in flash is the second stage bootloader. Second stage bootloader source code is available in :idf:`components/bootloader` directory of ESP-IDF. Second stage bootloader is used in ESP-IDF to add flexibility to flash layout (using partition tables), and allow for various flows associated with flash encryption, secure boot, and over-the-air updates (OTA) to take place.
 
-When the first stage bootloader is finished checking and loading the second stage bootloader, it jumps to the second stage bootloader entry point found in the binary image header.
+When the first stage (ROM) bootloader is finished checking and loading the second stage bootloader, it jumps to the second stage bootloader entry point found in the binary image header.
 
 Second stage bootloader reads the partition table found by default at offset {IDF_TARGET_CONFIG_PARTITION_TABLE_OFFSET} (:ref:`configurable value <CONFIG_PARTITION_TABLE_OFFSET>`). See :doc:`partition tables <partition-tables>` documentation for more information. The bootloader finds factory and OTA app partitions. If OTA app partitions are found in the partition table, the bootloader consults the ``otadata`` partition to determine which one should be booted. See :doc:`/api-reference/system/ota` for more information.
 
diff --git a/docs/en/api-guides/tools/idf-docker-image.rst b/docs/en/api-guides/tools/idf-docker-image.rst
index 9d1ca753da6..2633a041957 100644
--- a/docs/en/api-guides/tools/idf-docker-image.rst
+++ b/docs/en/api-guides/tools/idf-docker-image.rst
@@ -14,7 +14,7 @@ IDF Docker image (``espressif/idf``) is intended for building applications and l
 The image contains:
 
 - Common utilities such as ``git``, ``wget``, ``curl``, and ``zip``.
-- Python 3.8 or newer.
+- Python 3.9 or newer.
 - A copy of a specific version of ESP-IDF. See below for information about versions. ``IDF_PATH`` environment variable is set and points to the ESP-IDF location in the container.
 - All the build tools required for the specific version of ESP-IDF: CMake, Ninja, cross-compiler toolchains, etc.
 - All Python packages required by ESP-IDF are installed in a virtual environment.
diff --git a/docs/en/api-guides/tools/idf-monitor.rst b/docs/en/api-guides/tools/idf-monitor.rst
index 5c4408209de..9505a76210d 100644
--- a/docs/en/api-guides/tools/idf-monitor.rst
+++ b/docs/en/api-guides/tools/idf-monitor.rst
@@ -252,63 +252,7 @@ Custom Reset Sequence
 
 For more advanced users or specific use cases, IDF Monitor supports the configuration of a custom reset sequence using :ref:`configuration-file`. This is particularly useful in extreme edge cases where the default sequence may not suffice.
 
-The sequence is defined with a string in the following format:
-
-- Consists of individual commands divided by ``|`` (e.g. ``R0|D1|W0.5``).
-- Commands (e.g. ``R0``) are defined by a code (``R``) and an argument (``0``).
-
-.. list-table::
-    :header-rows: 1
-    :widths: 15 50 35
-    :align: center
-
-    * - Code
-      - Action
-      - Argument
-    * - D
-      - Set DTR control line
-      - ``1``/``0``
-    * - R
-      - Set RTS control line
-      - ``1``/``0``
-    * - U
-      - Set DTR and RTS control lines at the same time (Unix-like systems only)
-      - ``0,0``/``0,1``/``1,0``/``1,1``
-    * - W
-      - Wait for ``N`` seconds (where ``N`` is a float)
-      - N
-
-Example:
-
-.. code-block:: ini
-
-    [esp-idf-monitor]
-    custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0
-
-Refer to `custom reset sequence`_ from Esptool documentation for further details. Please note that ``custom_reset_sequence`` is the only used value from the Esptool configuration, and others will be ignored in IDF Monitor.
-
-Share Configuration Across Tools
---------------------------------
-
-The configuration for the custom reset sequence can be specified in a shared configuration file between IDF Monitor and Esptool. In this case, your configuration file name should be either ``setup.cfg`` or ``tox.ini`` so it would be recognized by both tools.
-
-Example of a shared configuration file:
-
-.. code-block:: ini
-
-    [esp-idf-monitor]
-    menu_key = T
-    skip_menu_key = True
-
-    [esptool]
-    custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0
-
-.. note::
-
-    When using the ``custom_reset_sequence`` parameter in both the ``[esp-idf-monitor]`` section and the ``[esptool]`` section, the configuration from the ``[esp-idf-monitor]`` section will take precedence in IDF Monitor. Any conflicting configuration in the ``[esptool]`` section will be ignored.
-
-    This precedence rule also applies when the configuration is spread across multiple files. The global esp-idf-monitor configuration will take precedence over the local esptool configuration.
-
+If you would like to use a custom reset sequence, take a look at the `IDF Monitor documentation`_ for more details.
 
 Launching GDB with GDBStub
 ~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -397,107 +341,9 @@ The options ``--print_filter="light_driver:D esp_image:N boot:N cpu_start:N vfs:
 Configuration File
 ==================
 
-``esp-idf-monitor`` is using `C0 control codes`_ to interact with the console. Characters from the config file are converted to their C0 control codes. Available characters include the English alphabet (A-Z) and special symbols: ``[``, ``]``, ``\``, ``^``, ``_``.
-
-.. warning::
+``esp-idf-monitor`` offers option to change its default behavior with configuration file. This file can be used for example to set custom key bindings, or set a custom reset sequence for resetting the chip into bootloader mode.
 
-    Please note that some characters may not work on all platforms or can be already reserved as a shortcut for something else. Use this feature with caution!
-
-
-File Location
-~~~~~~~~~~~~~
-
-The default name for a configuration file is ``esp-idf-monitor.cfg``. First, the same directory ``esp-idf-monitor`` is being run if is inspected.
-
-If a configuration file is not found here, the current user's OS configuration directory is inspected next:
-
- - Linux: ``/home/<user>/.config/esp-idf-monitor/``
- - MacOS ``/Users/<user>/.config/esp-idf-monitor/``
- - Windows: ``c:\Users\<user>\AppData\Local\esp-idf-monitor\``
-
-If a configuration file is still not found, the last inspected location is the home directory:
-
- - Linux: ``/home/<user>/``
- - MacOS ``/Users/<user>/``
- - Windows: ``c:\Users\<user>\``
-
-On Windows, the home directory can be set with the ``HOME`` or ``USERPROFILE`` environment variables. Therefore, the Windows configuration directory location also depends on these.
-
-A different location for the configuration file can be specified with the ``ESP_IDF_MONITOR_CFGFILE`` environment variable, e.g., ``ESP_IDF_MONITOR_CFGFILE = ~/custom_config.cfg``. This overrides the search priorities described above.
-
-``esp-idf-monitor`` will read settings from other usual configuration files if no other configuration file is used. It automatically reads from ``setup.cfg`` or ``tox.ini`` if they exist.
-
-Configuration Options
-~~~~~~~~~~~~~~~~~~~~~
-
-Below is a table listing the available configuration options:
-
-.. list-table::
-    :header-rows: 1
-    :widths: 30 50 20
-    :align: center
-
-    * - Option Name
-      - Description
-      - Default Value
-    * - menu_key
-      - Key to access the main menu.
-      - ``T``
-    * - exit_key
-      - Key to exit the monitor.
-      - ``]``
-    * - chip_reset_key
-      - Key to initiate a chip reset.
-      - ``R``
-    * - recompile_upload_key
-      - Key to recompile and upload.
-      - ``F``
-    * - recompile_upload_app_key
-      - Key to recompile and upload just the application.
-      - ``A``
-    * - toggle_output_key
-      - Key to toggle the output display.
-      - ``Y``
-    * - toggle_log_key
-      - Key to toggle the logging feature.
-      - ``L``
-    * - toggle_timestamp_key
-      - Key to toggle timestamp display.
-      - ``I``
-    * - chip_reset_bootloader_key
-      - Key to reset the chip to bootloader mode.
-      - ``P``
-    * - exit_menu_key
-      - Key to exit the monitor from the menu.
-      - ``X``
-    * - skip_menu_key
-      - Pressing the menu key can be skipped for menu commands.
-      - ``False``
-    * - custom_reset_sequence
-      - Custom reset sequence for resetting into the bootloader.
-      - N/A
-
-
-Syntax
-~~~~~~
-
-The configuration file is in .ini file format: it must be introduced by an ``[esp-idf-monitor]`` header to be recognized as valid. This section then contains name = value entries. Lines beginning with ``#`` or ``;`` are ignored as comments.
-
-.. code-block:: ini
-
-    # esp-idf-monitor.cfg file to configure internal settings of esp-idf-monitor
-    [esp-idf-monitor]
-    menu_key = T
-    exit_key = ]
-    chip_reset_key = R
-    recompile_upload_key = F
-    recompile_upload_app_key = A
-    toggle_output_key = Y
-    toggle_log_key = L
-    toggle_timestamp_key = I
-    chip_reset_bootloader_key = P
-    exit_menu_key = X
-    skip_menu_key = False
+For more details on the configuration file, see the `IDF Monitor documentation`_.
 
 
 Known Issues with IDF Monitor
@@ -505,10 +351,6 @@ Known Issues with IDF Monitor
 
 If you encounter any issues while using IDF Monitor, check our `GitHub repository <https://github.com/espressif/esp-idf-monitor/issues>`_ for a list of known issues and their current status. If you come across a problem that hasn't been documented yet, we encourage you to create a new issue report.
 
-.. _addr2line: https://sourceware.org/binutils/docs/binutils/addr2line.html
 .. _esp-idf-monitor: https://github.com/espressif/esp-idf-monitor
+.. _IDF Monitor documentation: https://github.com/espressif/esp-idf-monitor/blob/v1.5.0/README.md#documentation
 .. _gdb: https://sourceware.org/gdb/download/onlinedocs/
-.. _pySerial: https://github.com/pyserial/pyserial
-.. _miniterm: https://pyserial.readthedocs.org/en/latest/tools.html#module-serial.tools.miniterm
-.. _C0 control codes: https://en.wikipedia.org/wiki/C0_and_C1_control_codes#C0_controls
-.. _custom reset sequence: https://docs.espressif.com/projects/esptool/en/latest/{IDF_TARGET_PATH_NAME}/esptool/configuration-file.html#custom-reset-sequence
diff --git a/docs/en/api-guides/tools/index.rst b/docs/en/api-guides/tools/index.rst
index 1b25030209f..f5d1801ab77 100644
--- a/docs/en/api-guides/tools/index.rst
+++ b/docs/en/api-guides/tools/index.rst
@@ -12,4 +12,4 @@ Tools
    idf-clang-tidy
    idf-tools
    idf-size
-   :esp32 or esp32c3: qemu
+   :TARGET_SUPPORT_QEMU: qemu
diff --git a/docs/en/api-guides/tools/qemu.rst b/docs/en/api-guides/tools/qemu.rst
index 697f45ca7cd..f88766a4a3c 100644
--- a/docs/en/api-guides/tools/qemu.rst
+++ b/docs/en/api-guides/tools/qemu.rst
@@ -1,6 +1,8 @@
 QEMU Emulator
 =============
 
+{IDF_TARGET_CRYPT_CNT:default="SPI_BOOT_CRYPT_CNT",esp32="FLASH_CRYPT_CNT"}
+
 :link_to_translation:`zh_CN:[中文]`
 
 Espressif maintains a `fork <https://github.com/espressif/qemu>`_ of the QEMU emulator with support for {IDF_TARGET_NAME}. This fork implements emulation of the CPU, memory, and several peripherals of {IDF_TARGET_NAME}. For more information about QEMU for {IDF_TARGET_NAME}, see the `QEMU README documentation <https://github.com/espressif/esp-toolchain-docs/blob/main/qemu/README.md>`_.
@@ -119,13 +121,52 @@ QEMU supports emulation of eFuses. This can be a convenient way to test security
 
 You can use :doc:`idf.py<idf-py>` eFuse-related commands to program eFuses. When you run any of these commands together with ``qemu`` command, the eFuses are programmed in QEMU, and the ``qemu_efuse.bin`` file is updated. For example,
 
+.. only:: not SOC_FLASH_ENCRYPTION_XTS_AES
+
+    .. code-block:: console
+
+        idf.py qemu efuse-burn {IDF_TARGET_CRYPT_CNT} 1
+        idf.py qemu efuse-burn-key flash_encryption my_flash_encryption_key.bin
+
+.. only:: SOC_FLASH_ENCRYPTION_XTS_AES
+
+    .. code-block:: console
+
+        idf.py qemu efuse-burn {IDF_TARGET_CRYPT_CNT} 1
+        idf.py qemu efuse-burn-key BLOCK my_flash_encryption_key.bin KEYPURPOSE
+
+    For details regarding the ``BLOCK`` and ``KEYPURPOSE``, please refer to the :doc:`../../security/flash-encryption` guide.
+
+To dump the eFuse summary, please use the following command:
+
 .. code-block:: console
 
-    idf.py qemu efuse-burn FLASH_CRYPT_CNT 1
+    idf.py qemu efuse-summary
 
 By default, the values of eFuses are read from and written to the ``qemu_efuse.bin`` file in the build directory. You can specify a different file using the ``--efuse-file`` option. For example,
 
 .. code-block:: console
 
-    idf.py qemu --efuse-file my_efuse.bin efuse-burn FLASH_CRYPT_CNT 1
+    idf.py qemu --efuse-file my_efuse.bin efuse-burn {IDF_TARGET_CRYPT_CNT} 1
     idf.py qemu --efuse-file my_efuse.bin monitor
+
+Specifying Flash Image
+~~~~~~~~~~~~~~~~~~~~~~
+
+By default, QEMU uses the ``qemu_flash.bin`` file in the build directory as the flash image. This file is generated based on the information available about the project from the ``flash_args`` file present in the build directory. If you want to use a different flash image file, you can specify it using the ``--flash-file`` option. For example,
+
+.. code-block:: console
+
+    idf.py qemu --flash-file my_flash.bin monitor
+
+
+The provided flash image must meet the following requirements for proper emulation:
+
+- The flash file size matches the value specified by :ref:`CONFIG_ESPTOOLPY_FLASHSIZE` in the project configuration.
+- The flash file includes all required binaries, such as the bootloader, partition table, and application firmware, placed at their respective memory offsets.
+
+
+Emulating Secure Boot
+~~~~~~~~~~~~~~~~~~~~~
+
+QEMU supports emulation of secure boot v2 scheme. Please keep :ref:`CONFIG_SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT` enabled to include signed bootloader image into the QEMU image artifact.
diff --git a/docs/en/api-guides/wifi.rst b/docs/en/api-guides/wifi.rst
index 6c87032e0e9..f2a0deb5e91 100644
--- a/docs/en/api-guides/wifi.rst
+++ b/docs/en/api-guides/wifi.rst
@@ -839,7 +839,7 @@ Association Phase
 +++++++++++++++++++++
 
  - s3.1: The association request is sent and the association timer is enabled.
- - s3.2: If the association response is not received before the association timer times out, `WIFI_EVENT_STA_DISCONNECTED`_ will arise and the reason code will be ``WIFI_REASON_ASSOC_EXPIRE``. Refer to `Wi-Fi Reason Code`_.
+ - s3.2: If the association response is not received before the association timer times out, `WIFI_EVENT_STA_DISCONNECTED`_ will arise and the reason code will be ``WIFI_REASON_DISASSOC_DUE_TO_INACTIVITY``. Refer to `Wi-Fi Reason Code`_.
  - s3.3: The association response is received and the association timer is stopped.
  - s3.4: The AP rejects the association in the response and `WIFI_EVENT_STA_DISCONNECTED`_ arises, while the reason code is the one specified in the association response. Refer to `Wi-Fi Reason Code`_.
 
@@ -904,19 +904,15 @@ Following reason codes are renamed to their shorter form to wrap the table in pa
        For the ESP station, this reason is reported when:
 
        - it is received from the AP.
-   * - ASSOC_EXPIRE
+   * - DISASSOC_DUE_TO_INACTIVITY
      - 4
      - Disassociated due to inactivity.
 
        For the ESP station, this reason is reported when:
 
+       - assoc is timed out.
        - it is received from the AP.
 
-       For the ESP AP, this reason is reported when:
-
-       - the AP has not received any packets from the station in the past five minutes.
-       - the AP is stopped by calling :cpp:func:`esp_wifi_stop()`.
-       - the station is de-authed by calling :cpp:func:`esp_wifi_deauth_sta()`.
    * - ASSOC_TOOMANY
      - 5
      - Disassociated, because the AP is unable to handle all currently associated STAs at the same time.
@@ -928,7 +924,7 @@ Following reason codes are renamed to their shorter form to wrap the table in pa
        For the ESP AP, this reason is reported when:
 
        - the stations associated with the AP reach the maximum number that the AP can support.
-   * - NOT_AUTHED
+   * - CLASS2_FRAME_FROM_NONAUTH_STA
      - 6
      - Class-2 frame received from a non-authenticated STA.
 
@@ -939,7 +935,7 @@ Following reason codes are renamed to their shorter form to wrap the table in pa
        For the ESP AP, this reason is reported when:
 
        - the AP receives a packet with data from a non-authenticated station.
-   * - NOT_ASSOCED
+   * - CLASS3_FRAME_FROM_NONASSOC_STA
      - 7
      - Class-3 frame received from a non-associated STA.
 
@@ -1166,7 +1162,7 @@ Following reason codes are renamed to their shorter form to wrap the table in pa
      - Espressif-specific Wi-Fi reason code: the authentication fails, but not because of a timeout.
    * - ASSOC_FAIL
      - 203
-     - Espressif-specific Wi-Fi reason code: the association fails, but not because of ASSOC_EXPIRE or ASSOC_TOOMANY.
+     - Espressif-specific Wi-Fi reason code: the association fails, but not because of DISASSOC_DUE_TO_INACTIVITY or ASSOC_TOOMANY.
    * - HANDSHAKE_TIMEOUT
      - 204
      - Espressif-specific Wi-Fi reason code: the handshake fails for the same reason as that in WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT.
diff --git a/docs/en/api-reference/api-conventions.rst b/docs/en/api-reference/api-conventions.rst
index d541547e54a..7c4b45bd000 100644
--- a/docs/en/api-reference/api-conventions.rst
+++ b/docs/en/api-reference/api-conventions.rst
@@ -10,7 +10,7 @@ ESP-IDF provides several kinds of programming interfaces:
 
 * C functions, structures, enums, type definitions, and preprocessor macros declared in public header files of ESP-IDF components. Various pages in the API Reference section of the programming guide contain descriptions of these functions, structures, and types.
 * Build system functions, predefined variables, and options. These are documented in the :ref:`ESP-IDF CMake Build System API <cmake_buildsystem_api>`.
-* :doc:`Kconfig <kconfig>` options can be used in code and in the build system (``CMakeLists.txt``) files.
+* :ref:`Kconfig options <configs-in-C-Cmake>` can be used in code and in the build system (``CMakeLists.txt``) files.
 * :doc:`Host tools <../api-guides/tools/index>` and their command line parameters are also part of the ESP-IDF interfaces.
 
 ESP-IDF is made up of multiple components where these components either contain code specifically written for ESP chips, or contain a third-party library (i.e., a third-party component). In some cases, third-party components contain an "ESP-IDF specific" wrapper in order to provide an interface that is either simpler or better integrated with the rest of ESP-IDF's features. In other cases, third-party components present the original API of the underlying library directly.
@@ -145,7 +145,7 @@ While we try to make upgrading to a new ESP-IDF version easy, there are parts of
 * Changes made to mitigate security issues or to replace insecure default behaviors with secure ones.
 * Features that were never functional. For example, if it was never possible to use a certain function or an enumeration value, it may get renamed (as part of fixing it) or removed. This includes software features that depend on non-functional chip hardware features.
 * Unexpected or undefined behavior that is not documented explicitly may be fixed/changed, such as due to missing validation of argument ranges.
-* Location of :doc:`Kconfig <kconfig>` options in menuconfig.
+* Location of :ref:`Kconfig <project-configuration-guide>` options in menuconfig.
 * Location and names of example projects.
 
 .. _designated initializers: https://en.cppreference.com/w/c/language/struct_initialization
diff --git a/docs/en/api-reference/bluetooth/esp-ble-mesh.rst b/docs/en/api-reference/bluetooth/esp-ble-mesh.rst
index bf03a8fe796..35de1143e51 100644
--- a/docs/en/api-reference/bluetooth/esp-ble-mesh.rst
+++ b/docs/en/api-reference/bluetooth/esp-ble-mesh.rst
@@ -71,6 +71,9 @@ Reading of Local Data Information
 
 .. include-build-file:: inc/esp_ble_mesh_local_data_operation_api.inc
 
+Coexist with BLE
+
+..  include-build-file:: inc/esp_ble_mesh_ble_api.inc
 
 Low Power Operation (Updating)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/docs/en/api-reference/index.rst b/docs/en/api-reference/index.rst
index 21558e56cf3..9bd5e5bd3cf 100644
--- a/docs/en/api-reference/index.rst
+++ b/docs/en/api-reference/index.rst
@@ -13,7 +13,7 @@ API Reference
    error-codes
    network/index
    peripherals/index
-   kconfig
    provisioning/index
    storage/index
    system/index
+   kconfig-reference
diff --git a/docs/en/api-reference/kconfig-reference.rst b/docs/en/api-reference/kconfig-reference.rst
new file mode 100644
index 00000000000..1acbeec5523
--- /dev/null
+++ b/docs/en/api-reference/kconfig-reference.rst
@@ -0,0 +1,11 @@
+Configuration Options Reference
+===============================
+
+.. _configuration-options-reference:
+
+Subsequent sections contain the list of available ESP-IDF options automatically generated from Kconfig files. Note that due to dependencies between options, some options listed here may not be visible by default in ``menuconfig``.
+
+By convention, all option names are upper-case letters with underscores. When Kconfig generates ``sdkconfig`` and ``sdkconfig.h`` files, option names are prefixed with ``CONFIG_``. So if an option ``ENABLE_FOO`` is defined in a Kconfig file and selected in ``menuconfig``, then the ``sdkconfig`` and ``sdkconfig.h`` files will have ``CONFIG_ENABLE_FOO`` defined. In the following sections, option names are also prefixed with ``CONFIG_``, same as in the source code.
+
+
+.. include-build-file:: inc/kconfig.inc
diff --git a/docs/en/api-reference/kconfig.rst b/docs/en/api-reference/kconfig.rst
deleted file mode 100644
index 19ca3e0f97e..00000000000
--- a/docs/en/api-reference/kconfig.rst
+++ /dev/null
@@ -1,86 +0,0 @@
-Project Configuration
-*********************
-:link_to_translation:`zh_CN:[中文]`
-
-Introduction
-============
-
-The esp-idf-kconfig_ package that ESP-IDF uses is based on kconfiglib_, which is a Python extension to the Kconfig_ system. Kconfig provides a compile-time project configuration mechanism and offers configuration options of several types (e.g., integers, strings, and Booleans). Kconfig files specify dependencies between options, default values of options, the way options are grouped together, etc.
-
-For the full list of available features, please see Kconfig_ and `kconfiglib extensions`_.
-
-.. _project-configuration-menu:
-
-Project Configuration Menu
-==========================
-
-Application developers can open a terminal-based project configuration menu with the ``idf.py menuconfig`` build target.
-
-After being updated, this configuration is saved in the ``sdkconfig`` file under the project root directory. Based on ``sdkconfig``, application build targets will generate the ``sdkconfig.h`` file under the build directory, and will make the ``sdkconfig`` options available to the project build system and source files.
-
-Using ``sdkconfig.defaults``
-============================
-
-In some cases, for example, when the ``sdkconfig`` file is under revision control, it may be inconvenient for the build system to change the ``sdkconfig`` file. The build system offers a solution to prevent it from happening, which is to create the ``sdkconfig.defaults`` file. This file is never touched by the build system, and can be created manually or automatically. It contains all the options which matter to the given application and are different from the default ones. The format is the same as that of the ``sdkconfig`` file. ``sdkconfig.defaults`` can be created manually when one remembers all the changed configuration, or it can be generated automatically by running the ``idf.py save-defconfig`` command.
-
-Once ``sdkconfig.defaults`` is created, ``sdkconfig`` can be deleted or added to the ignore list of the revision control system (e.g., the ``.gitignore`` file for ``git``). Project build targets will automatically create the ``sdkconfig`` file, populate it with the settings from the ``sdkconfig.defaults`` file, and configure the rest of the settings to their default values. Note that during the build process, settings from ``sdkconfig.defaults`` will not override those already in ``sdkconfig``. For more information, see :ref:`custom-sdkconfig-defaults`.
-
-Kconfig Format Rules
-====================
-
-Format rules for Kconfig files are as follows:
-
-- Option names in any menus should have consistent prefixes. The prefix currently should have at least 3 characters.
-- The unit of indentation should be 4 spaces. All sub-items belonging to a parent item are indented by one level deeper. For example, ``menu`` is indented by 0 spaces, ``config``  ``menu`` by 4 spaces, ``help`` in ``config`` by 8 spaces, and the text under ``help`` by 12 spaces.
-- No trailing spaces are allowed at the end of the lines.
-- The maximum length of options is 50 characters.
-- The maximum length of lines is 120 characters.
-
-.. note::
-
-    The ``help`` section of each config in the menu is treated as reStructuredText to generate the reference documentation for each option.
-
-Format Checker
---------------
-
-``kconfcheck`` tool in esp-idf-kconfig_ package is provided for checking Kconfig files against the above format rules. The checker checks all Kconfig and ``Kconfig.projbuild`` files given as arguments, and generates a new file with suffix ``.new`` with some suggestions about how to fix issues (if there are any). Please note that the checker cannot correct all format issues and the responsibility of the developer is to final check and make corrections in order to pass the tests. For example, indentations will be corrected if there is not any misleading formatting, but it cannot come up with a common prefix for options inside a menu.
-
-The ``esp-idf-kconfig`` package is available in ESP-IDF environments, where the checker tool can be invoked by running command ``python -m kconfcheck <path_to_kconfig_file>``.
-
-For more information, please refer to `esp-idf-kconfig package documentation <https://github.com/espressif/esp-idf-kconfig/blob/master/docs/DOCUMENTATION.md>`__.
-
-.. _configuration-options-compatibility:
-
-Backward Compatibility of Kconfig Options
-=========================================
-
-The standard Kconfig_ tools ignore unknown options in ``sdkconfig``. So if a developer has custom settings for options which are renamed in newer ESP-IDF releases, then the given setting for the option would be silently ignored. Therefore, several features have been adopted to avoid this:
-
-1. ``kconfgen`` is used by the tool chain to pre-process ``sdkconfig`` files before anything else. For example, ``menuconfig`` would read them, so the settings for old options is kept and not ignored.
-2. ``kconfgen`` recursively finds all ``sdkconfig.rename`` files in ESP-IDF directory which contain old and new ``Kconfig`` option names. Old options are replaced by new ones in the ``sdkconfig`` file. Renames that should only appear for a single target can be placed in a target-specific rename file ``sdkconfig.rename.TARGET``, where ``TARGET`` is the target name, e.g., ``sdkconfig.rename.esp32s2``.
-3. ``kconfgen`` post-processes ``sdkconfig`` files and generates all build outputs (``sdkconfig.h``, ``sdkconfig.cmake``, and ``auto.conf``) by adding a list of compatibility statements, i.e., the values of old options are set for new options after modification. If users still use old options in their code, this will prevent it from breaking.
-4. :ref:`configuration-deprecated-options` are automatically generated by ``kconfgen``.
-
-The structure of the ``sdkconfig.rename`` file is as follows:
-
-* Lines starting with ``#`` and empty lines will be ignored.
-* All other lines should follow one of these formats:
-    * ``CONFIG_DEPRECATED_NAME CONFIG_NEW_NAME``, where ``CONFIG_DEPRECATED_NAME`` is the old config name which was renamed in a newer ESP-IDF version to ``CONFIG_NEW_NAME``.
-    * ``CONFIG_DEPRECATED_NAME !CONFIG_NEW_INVERTED_NAME`` where ``CONFIG_NEW_INVERTED_NAME`` was introduced in a newer ESP-IDF version by Boolean inversion of the logic value of ``CONFIG_DEPRECATED_NAME``.
-
-.. _configuration-options-reference:
-
-Configuration Options Reference
-===============================
-
-Subsequent sections contain the list of available ESP-IDF options automatically generated from Kconfig files. Note that due to dependencies between options, some options listed here may not be visible by default in ``menuconfig``.
-
-By convention, all option names are upper-case letters with underscores. When Kconfig generates ``sdkconfig`` and ``sdkconfig.h`` files, option names are prefixed with ``CONFIG_``. So if an option ``ENABLE_FOO`` is defined in a Kconfig file and selected in ``menuconfig``, then the ``sdkconfig`` and ``sdkconfig.h`` files will have ``CONFIG_ENABLE_FOO`` defined. In the following sections, option names are also prefixed with ``CONFIG_``, same as in the source code.
-
-
-.. include-build-file:: inc/kconfig.inc
-
-.. _Kconfig: https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt
-.. _esp-idf-kconfig: https://pypi.org/project/esp-idf-kconfig/
-.. _kconfiglib: https://github.com/ulfalizer/Kconfiglib
-.. _kconfiglib extensions: https://pypi.org/project/kconfiglib/#kconfig-extensions
diff --git a/docs/en/api-reference/network/esp_eth.rst b/docs/en/api-reference/network/esp_eth.rst
index bf22ff5b8c3..6f039d86d11 100644
--- a/docs/en/api-reference/network/esp_eth.rst
+++ b/docs/en/api-reference/network/esp_eth.rst
@@ -269,6 +269,10 @@ Configuration for PHY is described in :cpp:class:`eth_phy_config_t`, including:
 
     * :cpp:member:`eth_phy_config_t::reset_gpio_num`: if your board also connects the PHY reset pin to one of the GPIO, then set it here. Otherwise, set this field to ``-1``.
 
+    * :cpp:member:`eth_phy_config_t::hw_reset_assert_time_us`: Time the PHY reset pin is asserted in usec. Set this field to ``0`` to use chip specific default timing.
+
+    * :cpp:member:`eth_phy_config_t::post_hw_reset_delay_ms`: Time to wait after the PHY hardware reset is done in msec. Set this field to ``0`` to use chip specific default timing. Set this field to ``-1`` to not wait after the PHY hardware reset.
+
 ESP-IDF provides a default configuration for MAC and PHY in macro :c:macro:`ETH_MAC_DEFAULT_CONFIG` and :c:macro:`ETH_PHY_DEFAULT_CONFIG`.
 
 
@@ -288,19 +292,23 @@ The Ethernet driver is implemented in an Object-Oriented style. Any operation on
 
         eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG();                      // apply default common MAC configuration
         eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); // apply default vendor-specific MAC configuration
-        esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO;            // alter the GPIO used for MDC signal
-        esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO;          // alter the GPIO used for MDIO signal
+        esp32_emac_config.smi_gpio.mdc_num = CONFIG_EXAMPLE_ETH_MDC_GPIO;            // alter the GPIO used for MDC signal
+        esp32_emac_config.smi_gpio.mdio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO;          // alter the GPIO used for MDIO signal
         esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); // create MAC instance
 
         eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG();      // apply default PHY configuration
         phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR;           // alter the PHY address according to your board design
         phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; // alter the GPIO used for PHY reset
-        esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config);     // create PHY instance
-        // ESP-IDF officially supports several different Ethernet PHY chip driver
+        esp_eth_phy_t *phy = esp_eth_phy_new_generic(&phy_config);   // create generic PHY instance
+        // ESP-IDF officially supports several different specific Ethernet PHY chip driver
+        // esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config);
         // esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config);
         // esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config);
         // esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config);
 
+    .. note::
+        Any Ethernet PHY chip compliant with IEEE 802.3 can be used when creating new PHY instance with :cpp:func:`esp_eth_phy_new_generic`. However, while basic functionality should always work, some specific features might be limited, even if the PHY meets IEEE 802.3 standard. A typical example is loopback functionality, where certain PHYs may require setting a specific speed mode to operate correctly. If this is the concern and you need PHY driver specifically tailored to your chip needs, use drivers for PHY chips the ESP-IDF already officially supports or consult with :ref:`Custom PHY Driver <custom-phy-driver>` section to create a new custom driver.
+
     Optional Runtime MAC Clock Configuration
     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -374,7 +382,7 @@ To install the Ethernet driver, we need to combine the instance of MAC and PHY a
 
 * :cpp:member:`esp_eth_config_t::check_link_period_ms`: Ethernet driver starts an OS timer to check the link status periodically, this field is used to set the interval, in milliseconds.
 
-* :cpp:member:`esp_eth_config_t::stack_input`: In most Ethernet IoT applications, any Ethernet frame received by a driver should be passed to the upper layer (e.g., TCP/IP stack). This field is set to a function that is responsible to deal with the incoming frames. You can even update this field at runtime via function :cpp:func:`esp_eth_update_input_path` after driver installation.
+* :cpp:member:`esp_eth_config_t::stack_input` or :cpp:member:`esp_eth_config_t::stack_input_info`: In most Ethernet IoT applications, any Ethernet frame received by a driver should be passed to the upper layer (e.g., TCP/IP stack). This field is set to a function that is responsible to deal with the incoming frames. You can even update this field at runtime via function :cpp:func:`esp_eth_update_input_path` after driver installation.
 
 * :cpp:member:`esp_eth_config_t::on_lowlevel_init_done` and :cpp:member:`esp_eth_config_t::on_lowlevel_deinit_done`: These two fields are used to specify the hooks which get invoked when low-level hardware has been initialized or de-initialized.
 
@@ -509,6 +517,57 @@ The following functions should only be invoked after the Ethernet driver has bee
     esp_eth_ioctl(eth_handle, ETH_CMD_G_PHY_ADDR, &phy_addr);
     ESP_LOGI(TAG, "Ethernet PHY Address: %d", phy_addr);
 
+.. _time-stamping:
+
+.. only:: SOC_EMAC_IEEE1588V2_SUPPORTED
+
+    EMAC Hardware Time Stamping
+    ---------------------------
+
+    Time stamping in EMAC allows precise tracking of when Ethernet frames are transmitted or received. Hardware time stamping is crucial for applications like Precision Time Protocol (PTP) because it minimizes jitter and inaccuracies that can occur when relying on software-based time stamps. By embedding time stamps directly in hardware, delays introduced by software layers or processing overhead are avoided, ensuring nanosecond-level precision.
+
+    .. warning::
+        Time stamp associated API is currently in **"Experimental Feature"** state so be aware it may change with future releases.
+
+    The basic way how to enable time stamping, get and set time in the EMAC is demonstrated below.
+
+    .. highlight:: c
+
+    ::
+
+        // Enable hardware time stamping
+        bool ptp_enable = true;
+        esp_eth_ioctl(eth_hndl, ETH_MAC_ESP_CMD_PTP_ENABLE, &ptp_enable);
+
+        // Get current EMAC time
+        eth_mac_time_t ptp_time;
+        esp_eth_ioctl(eth_hndl, ETH_MAC_ESP_CMD_G_PTP_TIME, &ptp_time);
+
+        // Set EMAC time
+        ptp_time = {
+            .seconds = 42,
+            .nanoseconds = 0
+        };
+        esp_eth_ioctl(eth_hndl, ETH_MAC_ESP_CMD_S_PTP_TIME, &ptp_time);
+
+    You have an option to schedule event at precise point in time by registering callback function and configuring a target time when the event is supposed to be fired. Note that the callback function is then called from ISR context so it should be as brief as possible.
+
+    .. highlight:: c
+
+    ::
+
+        // Register the callback function
+        esp_eth_ioctl(eth_hndl, ETH_MAC_ESP_CMD_S_TARGET_CB, ts_callback);
+
+        // Set time when event is triggered
+        eth_mac_time_t mac_target_time = {
+            .seconds = 42,
+            .nanoseconds = 0
+        };
+        esp_eth_ioctl(s_eth_hndl, ETH_MAC_ESP_CMD_S_TARGET_TIME, &mac_target_time);
+
+    Time stamps for transmitted and received frames can be accessed via the last argument of the registered :cpp:member:`esp_eth_config_t::stack_input_info` function for the receive path, and via the ``ctrl`` argument of the :cpp:func:`esp_eth_transmit_ctrl_vargs` function for the transmit path. However, a more user-friendly approach to retrieve time stamp information in user space is by utilizing the L2 TAP :ref:`Extended Buffer <esp_netif_l2tap_ext_buff>` mechanism.
+
 .. _flow-control:
 
 Flow Control
@@ -538,6 +597,8 @@ Application Examples
 
   * :example:`ethernet/iperf` demonstrates how to use the Ethernet capabilities to measure the throughput/bandwidth using iPerf.
 
+  * :example:`ethernet/ptp` demonstrates the use of Precision Time Protocol (PTP) for time synchronization over Ethernet.
+
   * :example:`network/vlan_support` demonstrates how to create virtual network interfaces over Ethernet, including VLAN and non-VLAN interfaces.
 
   * :example:`network/sta2eth` demonstrates how to create a 1-to-1 bridge using a Wi-Fi station and a wired interface such as Ethernet or USB.
@@ -557,10 +618,12 @@ Application Examples
 Advanced Topics
 ---------------
 
+.. _custom-phy-driver:
+
 Custom PHY Driver
 ^^^^^^^^^^^^^^^^^
 
-There are multiple PHY manufacturers with wide portfolios of chips available. The ESP-IDF already supports several PHY chips however one can easily get to a point where none of them satisfies the user's actual needs due to price, features, stock availability, etc.
+There are multiple PHY manufacturers with wide portfolios of chips available. The ESP-IDF supports ``Generic PHY`` and also several specific PHY chips however one can easily get to a point where none of them satisfies the user's actual needs due to price, features, stock availability, etc.
 
 Luckily, a management interface between EMAC and PHY is standardized by IEEE 802.3 in Section 22.2.4 Management Functions. It defines provisions of the so-called "MII Management Interface" to control the PHY and gather status from the PHY. A set of management registers is defined to control chip behavior, link properties, auto-negotiation configuration, etc. This basic management functionality is addressed by :component_file:`esp_eth/src/phy/esp_eth_phy_802_3.c` in ESP-IDF and so it makes the creation of a new custom PHY chip driver quite a simple task.
 
diff --git a/docs/en/api-reference/network/esp_netif.rst b/docs/en/api-reference/network/esp_netif.rst
index 70faff41a15..8e20c5df2c5 100644
--- a/docs/en/api-reference/network/esp_netif.rst
+++ b/docs/en/api-reference/network/esp_netif.rst
@@ -82,20 +82,19 @@ Common Network Interfaces
 
 As the initialization of network interfaces could be quite complex, ESP-NETIF provides some convenient methods of creating the most common ones, such as Wi-Fi and Ethernet.
 
-Please refer to the following example to understand the initialization process of the default interface:
+Please refer to the following examples to understand the initialization process of the default interface:
 
+.. list::
 
-.. only:: SOC_WIFI_SUPPORTED
-
-    - Wi-Fi Station: :example_file:`wifi/getting_started/station/main/station_example_main.c`
+    :SOC_WIFI_SUPPORTED: - :example:`wifi/getting_started/station` demonstrates how to use the station functionality to connect {IDF_TARGET_NAME} to an AP.
 
-- Ethernet: :example_file:`ethernet/basic/main/ethernet_example_main.c`
+    :CONFIG_ESP_WIFI_SOFTAP_SUPPORT: - :example:`wifi/getting_started/softAP` demonstrates how to use the SoftAP functionality to configure {IDF_TARGET_NAME} as an AP.
 
-- L2 TAP: :example_file:`protocols/l2tap/main/l2tap_main.c`
+    - :example:`ethernet/basic` demonstrates how to use the Ethernet driver, attach it to `esp_netif`, and obtain an IP address that can be pinged.
 
-.. only:: CONFIG_ESP_WIFI_SOFTAP_SUPPORT
+    - :example:`protocols/l2tap` demonstrates how to use the ESP-NETIF L2 TAP interface to access the Data Link Layer for receiving and transmitting frames, implement non-IP protocols, and echo Ethernet frames with specific EthTypes.
 
-    - Wi-Fi Access Point: :example_file:`wifi/getting_started/softAP/main/softap_example_main.c`
+    - :example:`protocols/static_ip` demonstrates how to configure Wi-Fi as a station, including setting up a static IP, netmask, gateway and DNS server.
 
 .. only:: SOC_WIFI_SUPPORTED
 
@@ -149,42 +148,42 @@ ESP-NETIF Architecture
 
 
                          |          (A) USER CODE                 |
-                         |                 Apps                   |
-        .................| init          settings      events     |
+                         |                   Apps                 |
+        .................| init            settings        events |
         .                +----------------------------------------+
-        .                   .                |           *
-        .                   .                |           *
-    --------+            +===========================+   *     +-----------------------+
-            |            | new/config   get/set/apps |   *     | init                  |
-            |            |                           |...*.....| Apps (DHCP, SNTP)     |
-            |            |---------------------------|   *     |                       |
-      init  |            |                           |****     |                       |
-      start |************|  event handler            |*********|  DHCP                 |
-      stop  |            |                           |         |                       |
-            |            |---------------------------|         |                       |
-            |            |                           |         |    NETIF              |
-      +-----|            |                           |         +-----------------+     |
-      | glue|---<----|---|  esp_netif_transmit       |--<------| netif_output    |     |
-      |     |        |   |                           |         |                 |     |
-      |     |--->----|---|  esp_netif_receive        |-->------| netif_input     |     |
-      |     |        |   |                           |         + ----------------+     |
-      |     |...<....|...|  esp_netif_free_rx_buffer |...<.....| packet buffer         |
-      +-----|     |  |   |                           |         |                       |
-            |     |  |   |                           |         |         (D)           |
-      (B)   |     |  |   |          (C)              |         +-----------------------+
-    --------+     |  |   +===========================+               NETWORK STACK
+        .                   .                  |              *
+        .                   .                  |              *
+    --------+            +================================+   *     +-----------------------+
+            |            | new/config      get/set/apps   |   *     | init                  |
+            |            |                                |...*.....| Apps (DHCP, SNTP)     |
+            |            |--------------------------------|   *     |                       |
+      init  |            |                                |****     |                       |
+      start |************|  event handler                 |*********|  DHCP                 |
+      stop  |            |                                |         |                       |
+            |            |--------------------------------|         |                       |
+            |            |                                |         |    NETIF              |
+      +-----|            |                                |         +-----------------+     |
+      | glue|---<----|---|  esp_netif_transmit            |--<------| netif_output    |     |
+      |     |        |   |                                |         |                 |     |
+      |     |--->----|---|  esp_netif_receive             |-->------| netif_input     |     |
+      |     |        |   |                                |         + ----------------+     |
+      |     |...<....|...|  esp_netif_free_rx_buffer      |...<.....| packet buffer         |
+      +-----|     |  |   |                                |         |                       |
+            |     |  |   |                                |         |         (D)           |
+      (B)   |     |  |   |              (C)               |         +-----------------------+
+    --------+     |  |   +================================+               NETWORK STACK
   NETWORK         |  |           ESP-NETIF
   INTERFACE       |  |
-  DRIVER          |  |   +---------------------------+         +------------------+
-                  |  |   |                           |.........| open/close       |
-                  |  |   |                           |         |                  |
-                  |  -<--|  l2tap_write              |-----<---|  write           |
-                  |      |                           |         |                  |
-                  ---->--|  esp_vfs_l2tap_eth_filter |----->---|  read            |
-                         |                           |         |        (A)       |
-                         |            (E)            |         +------------------+
-                         +---------------------------+              USER CODE
-                               ESP-NETIF L2 TAP
+  DRIVER          |  |   +--------------------------------+         +------------------+
+                  |  |   |                                |.........| open/close       |
+                  |  |   |                                |         |                  |
+                  |  -<--| l2tap_write                    |-----<---|  write           |
+                  |      |                                |         |                  |
+                  ---->--| esp_vfs_l2tap_eth_filter_frame |----->---|  read            |
+                         |                                |         |        (A)       |
+                         |              (E)               |         +------------------+
+                         +--------------------------------+              USER CODE
+                                 ESP-NETIF L2 TAP
 
 
 Data and Event Flow in the Diagram
diff --git a/docs/en/api-reference/network/esp_netif_programming.rst b/docs/en/api-reference/network/esp_netif_programming.rst
index e07f2cdf2b0..e2685e96bca 100644
--- a/docs/en/api-reference/network/esp_netif_programming.rst
+++ b/docs/en/api-reference/network/esp_netif_programming.rst
@@ -132,8 +132,9 @@ The newly opened ESP-NETIF L2 TAP file descriptor needs to be configured prior t
   * ``L2TAP_S_INTF_DEVICE`` - bounds the file descriptor to a specific Network Interface that is identified by its ``if_key``. ESP-NETIF Network Interface ``if_key`` is passed to ``ioctl()`` as the third parameter. Note that default Network Interfaces ``if_key``'s used in ESP-IDF can be found in :component_file:`esp_netif/include/esp_netif_defaults.h`.
   * ``L2TAP_S_DEVICE_DRV_HNDL`` - is another way to bound the file descriptor to a specific Network Interface. In this case, the Network interface is identified directly by IO Driver handle (e.g., :cpp:type:`esp_eth_handle_t` in case of Ethernet). The IO Driver handle is passed to ``ioctl()`` as the third parameter.
   * ``L2TAP_S_RCV_FILTER`` - sets the filter to frames with the type to be passed to the file descriptor. In the case of Ethernet frames, the frames are to be filtered based on the Length and Ethernet type field. In case the filter value is set less than or equal to 0x05DC, the Ethernet type field is considered to represent IEEE802.3 Length Field, and all frames with values in interval <0, 0x05DC> at that field are passed to the file descriptor. The IEEE802.2 logical link control (LLC) resolution is then expected to be performed by the user's application. In case the filter value is set greater than 0x05DC, the Ethernet type field is considered to represent protocol identification and only frames that are equal to the set value are to be passed to the file descriptor.
+  * ``L2TAP_S_TIMESTAMP_EN`` - enables the hardware Time Stamping processing inside the file descriptor. The Time Stamps are retrieved to user space by using :ref:`Extended Buffer <esp_netif_l2tap_ext_buff>` mechanism when accessing the file descriptor by ``read()`` and ``write()`` functions. Hardware time stamping needs to be supported by target and needs to be enabled in IO Driver to this option work as expected.
 
-All above-set configuration options have a getter counterpart option to read the current settings.
+All above-set configuration options have a getter counterpart option to read the current settings except for ``L2TAP_S_TIMESTAMP_EN``.
 
 .. warning::
     The file descriptor needs to be firstly bounded to a specific Network Interface by ``L2TAP_S_INTF_DEVICE`` or ``L2TAP_S_DEVICE_DRV_HNDL`` to make ``L2TAP_S_RCV_FILTER`` option available.
@@ -153,14 +154,14 @@ All above-set configuration options have a getter counterpart option to read the
 
 ``fcntl()``
 ^^^^^^^^^^^
-``fcntl()`` is used to manipulate with properties of opened ESP-NETIF L2 TAP file descriptor.
+The ``fcntl()`` is used to manipulate with properties of opened ESP-NETIF L2 TAP file descriptor.
 
 The following commands manipulate the status flags associated with the file descriptor:
 
   * ``F_GETFD`` - the function returns the file descriptor flags, and the third argument is ignored.
   * ``F_SETFD`` - sets the file descriptor flags to the value specified by the third argument. Zero is returned.
 
-| On success, ``ioctl()`` returns 0. On error, -1 is returned, and ``errno`` is set to indicate the error.
+| On success, ``fcntl()`` returns 0. On error, -1 is returned, and ``errno`` is set to indicate the error.
 | * EBADF - not a valid file descriptor.
 | * ENOSYS - unsupported command.
 
@@ -172,23 +173,24 @@ Opened and configured ESP-NETIF L2 TAP file descriptor can be accessed by ``read
 | * EBADF - not a valid file descriptor.
 | * EAGAIN - the file descriptor has been marked non-blocking (``O_NONBLOCK``), and the read would block.
 
+.. note::
+    ESP-NETIF L2 TAP ``read()`` implementation extends the standard and offers Extended Buffer mechanism to retrieve additional information about received frame. See :ref:`Extended Buffer <esp_netif_l2tap_ext_buff>` section for more information.
+
 ``write()``
 ^^^^^^^^^^^
 A raw Data Link Layer frame can be sent to Network Interface via opened and configured ESP-NETIF L2 TAP file descriptor. The user's application is responsible to construct the whole frame except for fields which are added automatically by the physical interface device. The following fields need to be constructed by the user's application in case of an Ethernet link: source/destination MAC addresses, Ethernet type, actual protocol header, and user data. The length of these fields is as follows:
 
-.. list-table::
-    :header-rows: 1
-    :widths: 20 20 20 30
-    :align: center
+.. packetdiag::
 
-    * - Destination MAC
-      - Source MAC
-      - Type/Length
-      - Payload (protocol header/data)
-    * - 6 B
-      - 6 B
-      - 2 B
-      - 0-1486 B
+   packetdiag {
+     colwidth = 16;
+     node_width = 38;
+     0-5: Destination MAC (6B) [color = "#ffcccc"];
+     6-11: Source MAC Port (6B) [color = "#ffcccc"];
+     12-13: Type/Length (2B) [color = "#ccccff"];
+     14-15: [color = "#ffffcc"];
+     16-31: Payload (protocol header/data - 1486B) [color = "#ffffcc", colheight = 3];
+   }
 
 In other words, there is no additional frame processing performed by the ESP-NETIF L2 TAP interface. It only checks the Ethernet type of the frame is the same as the filter configured in the file descriptor. If the Ethernet type is different, an error is returned and the frame is not sent. Note that the ``write()`` may block in the current implementation when accessing a Network interface since it is a shared resource among multiple ESP-NETIF L2 TAP file descriptors and IP stack, and there is currently no queuing mechanism deployed.
 
@@ -197,9 +199,12 @@ In other words, there is no additional frame processing performed by the ESP-NET
 | * EBADMSG - The Ethernet type of the frame is different from the file descriptor configured filter.
 | * EIO - Network interface not available or busy.
 
+.. note::
+    ESP-NETIF L2 TAP ``write()`` implementation extends the standard and offers Extended Buffer mechanism to retrieve additional information about transmitted frame. See :ref:`Extended Buffer <esp_netif_l2tap_ext_buff>` section for more information.
+
 ``close()``
 ^^^^^^^^^^^
-Opened ESP-NETIF L2 TAP file descriptor can be closed by the ``close()`` to free its allocated resources. The ESP-NETIF L2 TAP implementation of ``close()`` may block. On the other hand, it is thread-safe and can be called from a different task than the file descriptor is actually used. If such a situation occurs and one task is blocked in the I/O operation and another task tries to close the file descriptor, the first task is unblocked. The first's task read operation then ends with an error.
+Opened ESP-NETIF L2 TAP file descriptor can be closed by the ``close()`` to free its allocated resources. The ESP-NETIF L2 TAP implementation of ``close()`` may block. On the other hand, it is thread-safe and can be called from a different task than the file descriptor is actually used. If such a situation occurs and one task is blocked in the I/O operation and another task tries to close the file descriptor, the first task is unblocked. The first's task ``read`` operation then ends with returning `0` bytes was read.
 
 | On success, ``close()`` returns zero. On error, -1 is returned, and ``errno`` is set to indicate the error.
 | * EBADF - not a valid file descriptor.
@@ -208,6 +213,77 @@ Opened ESP-NETIF L2 TAP file descriptor can be closed by the ``close()`` to free
 ^^^^^^^^^^^^
 Select is used in a standard way, just :ref:`CONFIG_VFS_SUPPORT_SELECT` needs to be enabled to make the ``select()`` function available.
 
+.. _esp_netif_l2tap_ext_buff:
+
+Extended Buffer
+^^^^^^^^^^^^^^^
+
+The Extended Buffer is ESP-NETIF L2 TAP's mechanism of how to retrieve additional information about transmitted or received IO frame via ``write()`` or ``read()`` functions. The Extended Buffer must be only used when specific functionality is enabled in the file descriptor (such as ``L2TAP_S_TIMESTAMP_EN``) and you want to access the additional data (such as Time Stamp) or control the frame processing.
+
+The **Extended Buffer** is a structure with fields which serve as arguments to drive underlying functionality in the ESP-NETIF L2 TAP file descriptor. The structure is defined as follows:
+
+.. code-block:: c
+
+    typedef struct {
+        size_t info_recs_len;       /*!< Length of Information Records buffer */
+        void *info_recs_buff;       /*!< Buffer holding extended information (IRECs) related to IO frames */
+        size_t buff_len;            /*!< Length of the actual IO Frame buffer */
+        void *buff;                 /*!< Pointer to the IO Frame buffer */
+    } l2tap_extended_buff_t;
+
+One Extended buffer may hold multiple **Information Records** (IRECs). These are variable data typed (and sized) records which may hold any datatype of additional information associated with the IO frame. The IREC structure is defined as follows:
+
+.. code-block:: c
+
+    typedef struct
+    {
+        size_t len;                         /*!< Length of the record including header and data*/
+        l2tap_irec_type_t type;             /*!< Type of the record */
+        alignas(long long) uint8_t data[];  /*!< Records Data aligned to double word */
+    } l2tap_irec_hdr_t;
+
+Currently implement and used IREC data types are defined in :cpp:type:`l2tap_irec_type_t`.
+
+Since the flexible array to hold data is used, proper memory alignment of multiple IRECs in the records buffer is required to correctly access memory. Improper alignment can result in slower memory access due to misaligned read/write operations, or in the worst case, cause undefined behavior on certain architectures. Therefore it is strictly recommended to use the below macros when manipulating with IRECs:
+
+* ``L2TAP_IREC_SPACE()`` - determines the space required for an IREC, ensuring that it is properly aligned.
+* ``L2TAP_IREC_LEN()`` - calculates the total length of one IREC, including the header and the data section of the record.
+* ``L2TAP_IREC_FIRST()`` - retrieves the first IREC from the :cpp:member:`l2tap_extended_buff_t::info_recs_buff` pool of Extended Buffer. If the :cpp:member:`l2tap_extended_buff_t::info_recs_len` is smaller than the size of a record header, it returns NULL.
+* ``L2TAP_IREC_NEXT()`` - retrieves the next IREC in the Extended Buffer after the current record. If the current record is NULL, it returns the first record.
+
+Extended Buffer Usage
+"""""""""""""""""""""
+
+Prior any Extended Buffer IO operation (either ``write()`` or ``read()``), you first need to fully populate the Extended Buffer and its IREC fields. For example, when you want to retrieve Time Stamp, you need to set type of the IREC to :cpp:enumerator:`L2TAP_IREC_TIME_STAMP` and configure appropriate length. If you don't set the type correctly, the frame is still received or transmitted but information to be retrieved is lost. Similarly, when the IREC length is less than expected length, the frame is still received or transmitted but the type of affected IREC is marked to :cpp:enumerator:`L2TAP_IREC_INVALID` by the ESP-NETIF L2 TAP and information to be retrieved is lost.
+
+When accessing the file descriptor using Extended Buffer, ``size`` parameter of ``write()`` or ``read()`` function must be set equal to ``0``. Failing to do so (i.e. accessing such file descriptor in a standard way with ``size`` parameter set to data length) will result in an -1 error and ``errno`` set to EINVAL.
+
+.. code-block:: c
+
+    // wrap "Info Records Buffer" into union to ensure proper alignment of data (this is typically needed when
+    // accessing double word variables or structs containing double word variables)
+    union {
+        uint8_t info_recs_buff[L2TAP_IREC_SPACE(sizeof(struct timespec))];
+        l2tap_irec_hdr_t align;
+    } u;
+
+    l2tap_extended_buff_t ptp_msg_ext_buff;
+
+    ptp_msg_ext_buff.info_recs_len = sizeof(u.info_recs_buff);
+    ptp_msg_ext_buff.info_recs_buff = u.info_recs_buff;
+    ptp_msg_ext_buff.buff = eth_frame;
+    ptp_msg_ext_buff.buff_len = sizeof(eth_frame);
+
+    l2tap_irec_hdr_t *ts_info = L2TAP_IREC_FIRST(&ptp_msg_ext_buff);
+    ts_info->len = L2TAP_IREC_LEN(sizeof(struct timespec));
+    ts_info->type = L2TAP_IREC_TIME_STAMP;
+
+    int ret = write(state->ptp_socket, &ptp_msg_ext_buff, 0);
+
+    // check if write was successful and ts_info is valid
+    if (ret > 0 && ts_info->type == L2TAP_IREC_TIME_STAMP) {
+        *ts = *(struct timespec *)ts_info->data;
+    }
 
 .. _esp_netif_other_events:
 
diff --git a/docs/en/api-reference/network/esp_now.rst b/docs/en/api-reference/network/esp_now.rst
index 2906264133c..4e5ea51c02f 100644
--- a/docs/en/api-reference/network/esp_now.rst
+++ b/docs/en/api-reference/network/esp_now.rst
@@ -15,10 +15,12 @@ Frame Format
 
 ESP-NOW uses a vendor-specific action frame to transmit ESP-NOW data. The default ESP-NOW bit rate is 1 Mbps.
 
-Currently, ESP-NOW supports two versions: v1.0 and v2.0. The maximum packet length supported by v2.0 devices is ESP_NOW_MAX_DATA_LEN_V2 bytes, while the maximum packet length supported by v1.0 devices is ESP_NOW_MAX_DATA_LEN bytes.
+Currently, ESP-NOW supports two versions: v1.0 and v2.0. The maximum packet length supported by v2.0 devices is 1490 (``ESP_NOW_MAX_DATA_LEN_V2``) bytes, while the maximum packet length supported by v1.0 devices is 250 (``ESP_NOW_MAX_DATA_LEN``)  bytes.
+
 The v2.0 devices are capable of receiving packets from both v2.0 and v1.0 devices. In contrast, v1.0 devices can only receive packets from other v1.0 devices.
-However, v1.0 devices can receive v2.0 packets if the packet length is less than or equal to ESP_NOW_MAX_IE_DATA_LEN.
-For packets exceeding this length, the v1.0 devices will either truncate the data to the first ESP_NOW_MAX_IE_DATA_LEN bytes or discard the packet entirely.
+
+However, v1.0 devices can receive v2.0 packets if the packet length is less than or equal to 250 (``ESP_NOW_MAX_IE_DATA_LEN``).For packets exceeding this length, the v1.0 devices will either truncate the data to the first 250 (``ESP_NOW_MAX_IE_DATA_LEN``) bytes or discard the packet entirely.
+
 For detailed behavior, please refer to the documentation corresponding to the specific IDF version.
 
 The format of the vendor-specific action frame is as follows:
diff --git a/docs/en/api-reference/network/esp_smartconfig.rst b/docs/en/api-reference/network/esp_smartconfig.rst
index d94091e8190..f7159fc6410 100644
--- a/docs/en/api-reference/network/esp_smartconfig.rst
+++ b/docs/en/api-reference/network/esp_smartconfig.rst
@@ -3,10 +3,17 @@ SmartConfig
 
 :link_to_translation:`zh_CN:[中文]`
 
+Introduction
+------------
+
 The SmartConfig\ :sup:`TM` is a provisioning technology developed by TI to connect a new Wi-Fi device to a Wi-Fi network. It uses a mobile application to broadcast the network credentials from a smartphone, or a tablet, to an un-provisioned Wi-Fi device.
 
 The advantage of this technology is that the device does not need to directly know SSID or password of an Access Point (AP). This information is provided using the smartphone. This is particularly important to headless device and systems, due to their lack of a user interface.
 
+Currently, {IDF_TARGET_NAME} support three types of SmartConfig: Airkiss, ESPTouch, and ESPTouch v2. ESPTouch v2 has been supported since SmartConfig v3.0 (the version of SmartConfig can be get from :cpp:func:`esp_smartconfig_get_version()`), and it employs a completely different algorithm compared to ESPTouch, resulting in faster setup times. Additionally, ESPTouch v2 introduces AES encryption and custom data fields.
+
+Starting from SmartConfig v3.0.2, ESPTouch v2 introduces support for random IV in AES encryption. On the application side, when the option for random IV is disabled, the default IV is set to 0, maintaining consistency with previous versions. When the random IV option is enabled, the IV will be a random value. It is important to note that when AES encryption is enabled with a random IV, the provision time will be extended due to the need of transmitting the IV to the provisioning device. On the provisioning device side, the device will identify whether the random IV for AES is enabled based on the flag in the provisioning packet.
+
 If you are looking for other options to provision your {IDF_TARGET_NAME} devices, check :doc:`../provisioning/index`.
 
 
diff --git a/docs/en/api-reference/network/esp_wifi.rst b/docs/en/api-reference/network/esp_wifi.rst
index 2fc5e14890b..5b119e3c8de 100644
--- a/docs/en/api-reference/network/esp_wifi.rst
+++ b/docs/en/api-reference/network/esp_wifi.rst
@@ -28,6 +28,7 @@ API Reference
 
 .. include-build-file:: inc/esp_wifi.inc
 .. include-build-file:: inc/esp_wifi_types.inc
+.. include-build-file:: inc/esp_wifi_types_generic.inc
 .. include-build-file:: inc/esp_eap_client.inc
 .. include-build-file:: inc/esp_wps.inc
 .. include-build-file:: inc/esp_rrm.inc
diff --git a/docs/en/api-reference/peripherals/adc_continuous.rst b/docs/en/api-reference/peripherals/adc_continuous.rst
index 32dc9b5c7bf..5498a252818 100644
--- a/docs/en/api-reference/peripherals/adc_continuous.rst
+++ b/docs/en/api-reference/peripherals/adc_continuous.rst
@@ -3,7 +3,7 @@ Analog to Digital Converter (ADC) Continuous Mode Driver
 
 :link_to_translation:`zh_CN:[中文]`
 
-{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one", esp32c5="one"}
+{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one", esp32c5="one", esp32c61="one"}
 
 Introduction
 ------------
@@ -117,7 +117,7 @@ If the ADC continuous mode driver is no longer used, you should deinitialize the
 
     - :cpp:func:`adc_continuous_monitor_enable`: Enable a monitor.
     - :cpp:func:`adc_continuous_monitor_disable`: Disable a monitor.
-    - :cpp:func:`adc_monitor_register_callbacks`: register user callbacks to take action when the ADC value exceeds of the threshold.
+    - :cpp:func:`adc_continuous_monitor_register_event_callbacks`: register user callbacks to take action when the ADC value exceeds of the thresholds.
     - :cpp:func:`adc_del_continuous_monitor`: Delete a created monitor and free resources.
 
     .. only:: esp32s2
@@ -129,6 +129,41 @@ If the ADC continuous mode driver is no longer used, you should deinitialize the
             2. Only one monitor is supported for one ADC unit.
             3. All enabled channel(s) of a certain ADC unit in ADC continuous mode driver will be monitored. The :cpp:member:`adc_monitor_config_t::channel` parameter will not be used.
 
+    Specifically, the monitor function can be used to implement zero-crossing detection. As ADC cannot directly process negative input signals, an extra **DC bias** should be applied to the original signal before measurement.
+
+    First, add a DC bias to the input signal through a circuit to "shift" the negative signal into the ADC's measurement range. For the measurement range, please refer to the On-Chip Sensor and Analog Signal Processing chapter in `TRM <{IDF_TARGET_TRM_EN_URL}>`__. For example, adding a 1 V bias would transform a signal from -1 V to +1 V into 0 V to 2 V range. Then by setting the appropriate high and low thresholds, the ADC can detect if the input signal approaches zero, allowing for the identification of phase changes in the signal. Refer to the example code below for details.
+
+    .. code:: c
+
+        // Initialize the ADC monitor handle
+        adc_monitor_handle_t adc_monitor_handle = NULL;
+
+        // Configure the ADC monitor
+        adc_monitor_config_t zero_crossing_config = {
+            .adc_unit = EXAMPLE_ADC_UNIT_1,      // Specify the ADC unit to monitor
+            .channel = EXAMPLE_ADC_CHANNEL_0,    // Specify the ADC channel to monitor
+            .h_threshold = 1100,                 // Set the high threshold close to the DC bias and adjust it as needed
+            .l_threshold = 900,                 // Set the low threshold close to the DC bias and adjust it as needed
+        };
+
+        // Create the ADC monitor
+        ESP_ERROR_CHECK(adc_new_continuous_monitor(&zero_crossing_config, &adc_monitor_handle));
+
+        // Register the callback function
+        adc_monitor_evt_cbs_t zero_crossing_cbs = {
+            .on_over_high_thresh = example_on_exceed_high_thresh,
+            .on_below_low_thresh = example_on_below_low_thresh,
+        };
+
+        ESP_ERROR_CHECK(adc_continuous_monitor_register_event_callbacks(adc_monitor_handle, &zero_crossing_cbs, NULL));
+
+        // Enable the ADC monitor
+        ESP_ERROR_CHECK(adc_continuous_monitor_enable(adc_monitor_handle));
+
+        // Disable and delete the ADC monitor
+        ESP_ERROR_CHECK(adc_continuous_monitor_disable(adc_monitor_handle));
+        ESP_ERROR_CHECK(adc_del_continuous_monitor(adc_monitor_handle));
+
 Initialize the ADC Continuous Mode Driver
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -254,7 +289,7 @@ After calling :cpp:func:`adc_continuous_start`, the ADC continuous conversion st
 Function :cpp:func:`adc_continuous_read` tries to read the expected length of conversion results each time.
 
 - When calling :cpp:func:`adc_continuous_read`, you can request to read a conversion result of the specified length. Sometimes, however, the actual available conversion results may be less than the requested length, in which case the function still moves the data from the internal pool into the buffer you provided. Therefore, to learn the number of conversion results actually moved into the buffer, please check the value of ``out_length``.
-- If there is no conversion result generated in the internal pool, the function will block for ``timeout_ms`` until the conversion results are generated. If there are still no generated results, the function will return :c:macro:`ESP_ERR_TIMEOUT`.
+- If there is no conversion result generated in the internal pool, the function will block for ``timeout_ms`` until at least one conversion result is generated. If there are still no generated results, the function will return :c:macro:`ESP_ERR_TIMEOUT`.
 - If the generated results fill up the internal pool, newly generated results will be lost. Next time when :cpp:func:`adc_continuous_read` is called, this function will return :c:macro:`ESP_ERR_INVALID_STATE` to indicate this situation.
 
 This API aims to give you a chance to read all the ADC continuous conversion results.
@@ -277,7 +312,7 @@ where:
     * - Dout
       - ADC raw digital reading result.
     * - Vmax
-      - Maximum measurable input analog voltage, this is related to the ADC attenuation, please refer to the On-Chip Sensor and Analog Signal Processing chapter in `Datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
+      - Maximum measurable input analog voltage, this is related to the ADC attenuation, please refer to the On-Chip Sensor and Analog Signal Processing chapter in `TRM <{IDF_TARGET_TRM_EN_URL}#sensor>`__.
     * - Dmax
       - Maximum of the output ADC raw digital reading result, which is 2^bitwidth, where the bitwidth is the :cpp:member:`adc_digi_pattern_config_t::bit_width` configured before.
 
@@ -290,39 +325,19 @@ To do further calibration to convert the ADC raw result to voltage in mV, please
 Hardware Limitations
 ^^^^^^^^^^^^^^^^^^^^
 
-- A specific ADC unit can only work under one operating mode at any one time, either continuous mode or one-shot mode. :cpp:func:`adc_continuous_start` has provided the protection.
-
-- Random Number Generator (RNG) uses ADC as an input source. When ADC continuous mode driver works, the random number generated from RNG will be less random.
-
-.. only:: esp32 or esp32s2
-
-    - ADC2 is also used by Wi-Fi. :cpp:func:`adc_continuous_start` has provided the protection between Wi-Fi driver and ADC continuous mode driver.
-
-.. only:: esp32
-
-    - ADC continuous mode driver uses I2S0 peripheral as hardware DMA FIFO. Therefore, if I2S0 is in use already, the :cpp:func:`adc_continuous_new_handle` will return :c:macro:`ESP_ERR_NOT_FOUND`.
-
-    - ESP32 DevKitC: GPIO 0 cannot be used due to external auto program circuits.
-
-    - ESP-WROVER-KIT: GPIO 0, 2, 4, and 15 cannot be used due to external connections for different purposes.
-
-.. only:: esp32s2
-
-    - ADC continuous mode driver uses SPI3 peripheral as hardware DMA FIFO. Therefore, if SPI3 is in use already, the :cpp:func:`adc_continuous_new_handle` will return :c:macro:`ESP_ERR_NOT_FOUND`.
-
-.. only:: esp32c3
-
-    - ADC2 DMA functionality is no longer supported to retrieve ADC conversion results due to hardware limitations, as unstable results have been observed. This issue can be found in `ESP32C3 Errata <https://www.espressif.com/sites/default/files/documentation/esp32-c3_errata_en.pdf>`_. For compatibility, you can enable :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` to force use ADC2.
-
-.. only:: esp32s3
-
-    - ADC2 DMA functionality is no longer supported to retrieve ADC conversion results due to hardware limitations, as unstable results have been observed. This issue can be found in `ESP32S3 Errata <https://www.espressif.com/sites/default/files/documentation/esp32-s3_errata_en.pdf>`_. For compatibility, you can enable :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` to force use ADC2.
-
-    .. _adc-continuous-power-management:
+.. list::
 
-.. only:: not esp32s3
+    - A specific ADC unit can only work under one operating mode at any one time, either continuous mode or one-shot mode. :cpp:func:`adc_continuous_start` has provided the protection.
+    - Random Number Generator (RNG) uses ADC as an input source. When ADC continuous mode driver works, the random number generated from RNG will be less random.
+    :esp32 or esp32s2: - ADC2 is also used by Wi-Fi. :cpp:func:`adc_continuous_start` has provided the protection between Wi-Fi driver and ADC continuous mode driver.
+    :esp32: - ADC continuous mode driver uses I2S0 peripheral as hardware DMA FIFO. Therefore, if I2S0 is in use already, the :cpp:func:`adc_continuous_new_handle` will return :c:macro:`ESP_ERR_NOT_FOUND`.
+    :esp32: - ESP32 DevKitC: GPIO 0 cannot be used due to external auto program circuits.
+    :esp32: - ESP-WROVER-KIT: GPIO 0, 2, 4, and 15 cannot be used due to external connections for different purposes.
+    :esp32s2: - ADC continuous mode driver uses SPI3 peripheral as hardware DMA FIFO. Therefore, if SPI3 is in use already, the :cpp:func:`adc_continuous_new_handle` will return :c:macro:`ESP_ERR_NOT_FOUND`.
+    :esp32c3: - ADC2 DMA functionality is no longer supported to retrieve ADC conversion results due to hardware limitations, as unstable results have been observed. This issue can be found in `ESP32C3 Errata <https://www.espressif.com/sites/default/files/documentation/esp32-c3_errata_en.pdf>`_. For compatibility, you can enable :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` to force use ADC2.
+    :esp32s3: - ADC2 DMA functionality is no longer supported to retrieve ADC conversion results due to hardware limitations, as unstable results have been observed. This issue can be found in `ESP32S3 Errata <https://www.espressif.com/sites/default/files/documentation/esp32-s3_errata_en.pdf>`_. For compatibility, you can enable :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3` to force use ADC2.
 
-    .. _adc-continuous-power-management:
+.. _adc-continuous-power-management:
 
 Power Management
 ^^^^^^^^^^^^^^^^
diff --git a/docs/en/api-reference/peripherals/adc_oneshot.rst b/docs/en/api-reference/peripherals/adc_oneshot.rst
index c7dfec41d00..24fee32be51 100644
--- a/docs/en/api-reference/peripherals/adc_oneshot.rst
+++ b/docs/en/api-reference/peripherals/adc_oneshot.rst
@@ -3,20 +3,17 @@ Analog to Digital Converter (ADC) Oneshot Mode Driver
 
 :link_to_translation:`zh_CN:[中文]`
 
-{IDF_TARGET_ADC_NUM:default="two", esp32c2="one", esp32c6="one", esp32h2="one", esp32c5="one"}
-
 Introduction
 ------------
 
 The Analog to Digital Converter is integrated on the chip and is capable of measuring analog signals from specific analog IO pins.
 
-{IDF_TARGET_NAME} has {IDF_TARGET_ADC_NUM} ADC unit(s), which can be used in scenario(s) like:
-
-- Generate one-shot ADC conversion result
+{IDF_TARGET_NAME} has {SOC_ADC_PERIPH_NUM} ADC unit(s), which can be used in scenario(s) like:
 
-.. only:: SOC_ADC_DMA_SUPPORTED
+.. list::
 
-    - Generate continuous ADC conversion results
+    - Generate one-shot ADC conversion result
+    :SOC_ADC_DMA_SUPPORTED: - Generate continuous ADC conversion results
 
 This guide introduces ADC oneshot mode conversion.
 
@@ -164,31 +161,16 @@ Read Raw Result
 Hardware Limitations
 ^^^^^^^^^^^^^^^^^^^^
 
-- Random Number Generator (RNG) uses ADC as an input source. When ADC :cpp:func:`adc_oneshot_read` works, the random number generated from RNG will be less random.
-
-.. only:: SOC_ADC_DMA_SUPPORTED
-
-    - A specific ADC unit can only work under one operating mode at any one time, either continuous mode or oneshot mode. :cpp:func:`adc_oneshot_read` has provided the protection.
-
-.. only:: esp32 or esp32s2 or esp32s3
-
-    - ADC2 is also used by Wi-Fi. :cpp:func:`adc_oneshot_read` has provided protection between the Wi-Fi driver and ADC oneshot mode driver.
-
-.. only:: esp32c3
-
-    - ADC2 oneshot mode is no longer supported, due to hardware limitations. The results are not stable. This issue can be found in `ESP32-C3 Series SoC Errata <https://www.espressif.com/sites/default/files/documentation/esp32-c3_errata_en.pdf>`_. For compatibility, you can enable :ref:`CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3` to force use ADC2.
-
-.. only:: esp32
-
-    - ESP32-DevKitC: GPIO0 cannot be used in oneshot mode, because the DevKit has used it for auto-flash.
-
-    - ESP-WROVER-KIT: GPIO 0, 2, 4, and 15 cannot be used due to external connections for different purposes.
-
-    .. _adc-oneshot-power-management:
+.. list::
 
-.. only:: not esp32
+    - Random Number Generator (RNG) uses ADC as an input source. When ADC :cpp:func:`adc_oneshot_read` works, the random number generated from RNG will be less random.
+    :SOC_ADC_DMA_SUPPORTED: - A specific ADC unit can only work under one operating mode at any one time, either continuous mode or oneshot mode. :cpp:func:`adc_oneshot_read` has provided the protection.
+    :esp32 or esp32s2 or esp32s3: - ADC2 is also used by Wi-Fi. :cpp:func:`adc_oneshot_read` has provided protection between the Wi-Fi driver and ADC oneshot mode driver.
+    :esp32c3: - ADC2 oneshot mode is no longer supported, due to hardware limitations. The results are not stable. This issue can be found in `ESP32-C3 Series SoC Errata <https://www.espressif.com/sites/default/files/documentation/esp32-c3_errata_en.pdf>`_. For compatibility, you can enable :ref:`CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3` to force use ADC2.
+    :esp32: - ESP32-DevKitC: GPIO0 cannot be used in oneshot mode, because the DevKit has used it for auto-flash.
+    :esp32: - ESP-WROVER-KIT: GPIO 0, 2, 4, and 15 cannot be used due to external connections for different purposes.
 
-    .. _adc-oneshot-power-management:
+.. _adc-oneshot-power-management:
 
 Power Management
 ^^^^^^^^^^^^^^^^
diff --git a/docs/en/api-reference/peripherals/camera_driver.rst b/docs/en/api-reference/peripherals/camera_driver.rst
index f1ac880171e..9023d0a9570 100644
--- a/docs/en/api-reference/peripherals/camera_driver.rst
+++ b/docs/en/api-reference/peripherals/camera_driver.rst
@@ -221,4 +221,3 @@ API Reference
 .. include-build-file:: inc/esp_cam_ctlr_types.inc
 .. include-build-file:: inc/esp_cam_ctlr_csi.inc
 .. include-build-file:: inc/esp_cam_ctlr_isp_dvp.inc
-.. include-build-file:: inc/isp_core.inc
diff --git a/docs/en/api-reference/peripherals/cap_touch_sens.rst b/docs/en/api-reference/peripherals/cap_touch_sens.rst
index 0b08103dbd8..7e4ba8c6eef 100644
--- a/docs/en/api-reference/peripherals/cap_touch_sens.rst
+++ b/docs/en/api-reference/peripherals/cap_touch_sens.rst
@@ -3,7 +3,7 @@ Capacitive Touch Sensor
 
 :link_to_translation:`zh_CN:[中文]`
 
-{IDF_TARGET_TOUCH_SENSOR_VERSION:default="NOT_UPDATED", esp32p4="v3"}
+{IDF_TARGET_TOUCH_SENSOR_VERSION:default="NOT_UPDATED", esp32s2="v2", esp32s3="v2", esp32p4="v3"}
 
 Introduction
 ---------------
@@ -35,59 +35,9 @@ Overview of Capacitive Touch Sensor Versions
 Overview of Touch Sensor Channels
 ------------------------------------
 
-.. only:: esp32p4
-
-    .. list-table::
-      :header-rows: 1
-      :widths: 20  20
-
-      * - Channel
-        - GPIO
-
-      * - CH0
-        - IO2
-
-      * - CH1
-        - IO3
-
-      * - CH2
-        - IO4
-
-      * - CH3
-        - IO5
-
-      * - CH4
-        - IO6
-
-      * - CH5
-        - IO7
-
-      * - CH6
-        - IO8
-
-      * - CH7
-        - IO9
-
-      * - CH8
-        - IO10
-
-      * - CH9
-        - IO11
-
-      * - CH10
-        - IO12
-
-      * - CH11
-        - IO13
-
-      * - CH12
-        - IO14
-
-      * - CH13
-        - IO15
-
-      * - CH14
-        - Internal
+.. include:: cap_touch_sens/{IDF_TARGET_PATH_NAME}.inc
+    :start-after: touch-chan-mapping
+    :end-before: ---
 
 Terminology in the Driver
 ----------------------------
@@ -148,6 +98,7 @@ Categorized by functionality, the APIs of Capacitive Touch Sensor mainly include
   :SOC_TOUCH_SUPPORT_WATERPROOF: - `Waterproof Configuration <#touch-waterproof>`__
   :SOC_TOUCH_SUPPORT_PROX_SENSING: - `Proximity Sensing Configuration <#touch-prox-sensing>`__
   :SOC_TOUCH_SUPPORT_SLEEP_WAKEUP: - `Sleep Wake-up Configuration <#touch-sleep-wakeup>`__
+  :SOC_TOUCH_SUPPORT_DENOISE_CHAN: - `Denoise Channel Configuration <#touch-denoise-chan>`__
 
 .. _touch-ctrl:
 
@@ -385,7 +336,13 @@ Call :cpp:func:`touch_channel_read_data` to read the data with different types.
 
     The {IDF_TARGET_NAME} supports proximity sensing. Proximity sensing can be registered by calling :cpp:func:`touch_sensor_config_proximity_sensing` and specify the configurations :cpp:type:`touch_proximity_config_t`.
 
-    Since the capacitance change caused by proximity sensing is far less than that caused by physical touch, large area of copper foil is often used on PCB to increase the sensing area. In addition, multiple rounds of scans are needed and the result of each scan will be accumulated in the driver to improve the measurement sensitivity. The scan times (rounds) can be determined by :cpp:member:`touch_proximity_config_t::scan_times` and the charging times of the proximity channel in one scan can be determined by :cpp:member:`touch_proximity_config_t::charge_times`. Generally, the larger the scan times and charging times is, the higher the sensitivity will be, however, the read data will be unstable if the sensitivity is too high. Proper parameters should be determined regarding the application.
+    .. only:: esp32p4
+
+        Since the capacitance change caused by proximity sensing is far less than that caused by physical touch, large area of copper foil is often used on PCB to increase the sensing area. In addition, multiple rounds of scans are needed and the result of each scan will be accumulated in the driver to improve the measurement sensitivity. The scan times (rounds) can be determined by :cpp:member:`touch_proximity_config_t::scan_times` and the charging times of the proximity channel in one scan can be determined by :cpp:member:`touch_proximity_config_t::charge_times`. Generally, the larger the scan times and charging times is, the higher the sensitivity will be, however, the read data will be unstable if the sensitivity is too high. Proper parameters should be determined regarding the application.
+
+    .. only:: not esp32p4
+
+        Since the capacitance change caused by proximity sensing is far less than that caused by physical touch, large area of copper foil is often used on PCB to increase the sensing area. In addition, multiple rounds of scans are needed and the result of each scan will be accumulated in the driver to improve the measurement sensitivity. The scan times (rounds) can be determined by :cpp:member:`touch_proximity_config_t::scan_times`. Generally, the larger the scan times and charging times is, the higher the sensitivity will be, however, the read data will be unstable if the sensitivity is too high. Proper parameters should be determined regarding the application.
 
     The accumulated proximity data can be read by :cpp:func:`touch_channel_read_data` with the data type :cpp:enumerator:`TOUCH_CHAN_DATA_TYPE_PROXIMITY`
 
@@ -421,7 +378,7 @@ Call :cpp:func:`touch_channel_read_data` to read the data with different types.
         If you want to read or configure the touch sensor during the sleep, you can turn to the driver ``components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h`` which based on the :doc:`Ultra Low Power (ULP) Coprocessor <../system/ulp>`.
 
     - Light sleep wake-up: you need to set :cpp:member:`slp_wakeup_lvl` to :cpp:enumerator:`TOUCH_LIGHT_SLEEP_WAKEUP` to enable the light sleep wake-up by touch sensor. Note that any registered touch channel can wake-up the chip from light sleep.
-    - Deep sleep wake-up: beside setting :cpp:member:`slp_wakeup_lvl` to :cpp:enumerator:`TOUCH_DEEP_SLEEP_WAKEUP`, you need to specify :cpp:member:`deep_slp_chan` additionally. Only the specified channel can wake-up the chip from the deep sleep, in order to reduce the power consumption. And also, the driver supports to store another set of configurations for the deep sleep via :cpp:member:`deep_slp_sens_cfg`, this set of configurations only takes effect during the deep sleep, you can customize the configurations to save more power. The configurations will be reset to the previous set after waking-up from the deep sleep. Please be aware that, not only deep sleep wake-up, but also light sleep wake-up will be enabled when the :cpp:member:`slp_wakeup_lvl` is :cpp:enumerator:`TOUCH_DEEP_SLEEP_WAKEUP`.
+    - Deep sleep wake-up: beside setting :cpp:member:`slp_wakeup_lvl` to :cpp:enumerator:`TOUCH_DEEP_SLEEP_WAKEUP`, you need to specify :cpp:member:`deep_slp_chan` additionally. In order to reduce the power consumption, only the specified channel can wake-up the chip from the deep sleep when RTC_PREI power domain off. And also, the driver supports to store another set of configurations for the deep sleep via :cpp:member:`deep_slp_sens_cfg`, this set of configurations only takes effect during the deep sleep, you can customize the configurations to save more power. The configurations will be reset to the previous set after waking-up from the deep sleep. Please be aware that, not only deep sleep wake-up, but also light sleep wake-up will be enabled when the :cpp:member:`slp_wakeup_lvl` is :cpp:enumerator:`TOUCH_DEEP_SLEEP_WAKEUP`.
 
     To deregister the sleep wake-up function, you can call :cpp:func:`touch_sensor_config_sleep_wakeup` again, and set the second parameter (i.e. :cpp:type:`touch_sleep_config_t` pointer) to ``NULL``.
 
@@ -444,15 +401,44 @@ Call :cpp:func:`touch_channel_read_data` to read the data with different types.
         // Register the deep sleep wake-up
         ESP_ERROR_CHECK(touch_sensor_config_sleep_wakeup(sens_handle, &deep_slp_cfg));
 
+.. _touch-denoise-chan:
+
+.. only:: SOC_TOUCH_SUPPORT_DENOISE_CHAN
+
+    Denoise Channel Configuration
+    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    The {IDF_TARGET_NAME} supports the internal background noise suppression by the denoise channel. Denoise channel can be registered by calling :cpp:func:`touch_sensor_config_denoise_channel` and specify the configurations :cpp:type:`touch_denoise_chan_config_t`.
+
+    Denoise channel is an internal channel that not fanned out. After the denoise channel is enabled, the sampled data of the other touch channels will minus the data of the denoise channel automatically, so the final measurement result of the touch channels will be attenuated compare to the original data.
+
+    Aside of the common touch channel configuration, the reference capacitance that attached to the denoise channel can be set by :cpp:member:`touch_denoise_chan_config_t::ref_cap`. And the noise suppression resolution can be set by :cpp:member:`touch_denoise_chan_config_t::resolution`. The higher the resolution, the greater and more accuracy the denoise channel sample data will be, and the better  suppression effect it takes. But at the same time, the attenuation of other touch channel sampling values also increases.
+
+    For example, the denoise channel resolution is :cpp:enumerator:`touch_denoise_chan_resolution_t::TOUCH_DENOISE_CHAN_RESOLUTION_BIT8`, i.e., maximum sample data is ``255``. Assuming the actual sample data of a normal touch channel is ``10000``, and the denoise channel sample data is ``100``, then the final measurement result of the touch channel will be ``10000 - 100 = 9900``; If we increase the resolution to :cpp:enumerator:`touch_denoise_chan_resolution_t::TOUCH_DENOISE_CHAN_RESOLUTION_BIT12`, i.e., maximum sample data is ``4095``, the resolution is ``16`` times greater. So the denoise channel sample data will be about ``100 * 16 = 1600``, then the final measurement result of this touch channel will be ``10000 - 1600 = 8400.``
+
+    To deregister the denoise channel, you can call :cpp:func:`touch_sensor_config_denoise_channel` again, and set the second parameter (i.e. :cpp:type:`touch_denoise_chan_config_t` pointer) to ``NULL``.
+
+    .. code-block:: c
+
+        touch_denoise_chan_config_t denoise_cfg = {
+            // Denoise channel configurations
+            // ...
+        }
+        // Register the denoise channel
+        ESP_ERROR_CHECK(touch_sensor_config_denoise_channel(sens_handle, &denoise_cfg));
+        // ...
+        // Deregister the denoise channel
+        ESP_ERROR_CHECK(touch_sensor_config_denoise_channel(sens_handle, NULL));
+
 Application Examples
 ------------------------
 
-    - :example:`peripherals/touch_sensor/touch_sensor_v3` demonstrates how to register touch channels and read the data, including hardware requirements and project configuration instructions.
+    - :example:`peripherals/touch_sensor/touch_sens_basic` demonstrates how to register touch channels and read the data, including hardware requirements and project configuration instructions.
 
 API Reference
 -------------
 
-.. only:: esp32p4
+.. only:: esp32p4 or esp32s2 or esp32s3
 
     .. include-build-file:: inc/touch_sens.inc
     .. include-build-file:: inc/touch_sens_types.inc
diff --git a/docs/en/api-reference/peripherals/cap_touch_sens/esp32p4.inc b/docs/en/api-reference/peripherals/cap_touch_sens/esp32p4.inc
new file mode 100644
index 00000000000..e02da617bbb
--- /dev/null
+++ b/docs/en/api-reference/peripherals/cap_touch_sens/esp32p4.inc
@@ -0,0 +1,64 @@
+.. This file gets included from other .rst files in this folder.
+.. It contains target-specific snippets.
+.. Comments and '---' lines act as delimiters.
+..
+.. This is necessary mainly because RST doesn't support substitutions
+.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
+.. These code blocks can be moved back to the main .rst files, with target-specific
+.. file names being replaced by substitutions.
+
+.. touch-chan-mapping
+
+.. list-table::
+    :header-rows: 1
+    :widths: 20  20
+
+    * - Channel
+      - GPIO
+
+    * - CH0
+      - IO2
+
+    * - CH1
+      - IO3
+
+    * - CH2
+      - IO4
+
+    * - CH3
+      - IO5
+
+    * - CH4
+      - IO6
+
+    * - CH5
+      - IO7
+
+    * - CH6
+      - IO8
+
+    * - CH7
+      - IO9
+
+    * - CH8
+      - IO10
+
+    * - CH9
+      - IO11
+
+    * - CH10
+      - IO12
+
+    * - CH11
+      - IO13
+
+    * - CH12
+      - IO14
+
+    * - CH13
+      - IO15
+
+    * - CH14
+      - Internal
+
+---
diff --git a/docs/en/api-reference/peripherals/cap_touch_sens/esp32s2.inc b/docs/en/api-reference/peripherals/cap_touch_sens/esp32s2.inc
new file mode 100644
index 00000000000..c4af1781b1e
--- /dev/null
+++ b/docs/en/api-reference/peripherals/cap_touch_sens/esp32s2.inc
@@ -0,0 +1,64 @@
+.. This file gets included from other .rst files in this folder.
+.. It contains target-specific snippets.
+.. Comments and '---' lines act as delimiters.
+..
+.. This is necessary mainly because RST doesn't support substitutions
+.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
+.. These code blocks can be moved back to the main .rst files, with target-specific
+.. file names being replaced by substitutions.
+
+.. touch-chan-mapping
+
+.. list-table::
+    :header-rows: 1
+    :widths: 20  20
+
+    * - Channel
+      - GPIO
+
+    * - CH0
+      - Internal
+
+    * - CH1
+      - IO1
+
+    * - CH2
+      - IO2
+
+    * - CH3
+      - IO3
+
+    * - CH4
+      - IO4
+
+    * - CH5
+      - IO5
+
+    * - CH6
+      - IO6
+
+    * - CH7
+      - IO7
+
+    * - CH8
+      - IO8
+
+    * - CH9
+      - IO9
+
+    * - CH10
+      - IO10
+
+    * - CH11
+      - IO11
+
+    * - CH12
+      - IO12
+
+    * - CH13
+      - IO13
+
+    * - CH14
+      - IO14
+
+---
diff --git a/docs/en/api-reference/peripherals/cap_touch_sens/esp32s3.inc b/docs/en/api-reference/peripherals/cap_touch_sens/esp32s3.inc
new file mode 100644
index 00000000000..c4af1781b1e
--- /dev/null
+++ b/docs/en/api-reference/peripherals/cap_touch_sens/esp32s3.inc
@@ -0,0 +1,64 @@
+.. This file gets included from other .rst files in this folder.
+.. It contains target-specific snippets.
+.. Comments and '---' lines act as delimiters.
+..
+.. This is necessary mainly because RST doesn't support substitutions
+.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
+.. These code blocks can be moved back to the main .rst files, with target-specific
+.. file names being replaced by substitutions.
+
+.. touch-chan-mapping
+
+.. list-table::
+    :header-rows: 1
+    :widths: 20  20
+
+    * - Channel
+      - GPIO
+
+    * - CH0
+      - Internal
+
+    * - CH1
+      - IO1
+
+    * - CH2
+      - IO2
+
+    * - CH3
+      - IO3
+
+    * - CH4
+      - IO4
+
+    * - CH5
+      - IO5
+
+    * - CH6
+      - IO6
+
+    * - CH7
+      - IO7
+
+    * - CH8
+      - IO8
+
+    * - CH9
+      - IO9
+
+    * - CH10
+      - IO10
+
+    * - CH11
+      - IO11
+
+    * - CH12
+      - IO12
+
+    * - CH13
+      - IO13
+
+    * - CH14
+      - IO14
+
+---
diff --git a/docs/en/api-reference/peripherals/dac.rst b/docs/en/api-reference/peripherals/dac.rst
index 4cb3eb12b3d..06b5cc55f0e 100644
--- a/docs/en/api-reference/peripherals/dac.rst
+++ b/docs/en/api-reference/peripherals/dac.rst
@@ -96,7 +96,7 @@ Power Management
 
 When the power management is enabled (i.e., :ref:`CONFIG_PM_ENABLE` is on), the system will adjust or stop the clock source of DAC before entering Light-sleep mode, thus potential influence to the DAC signals may lead to false data conversion.
 
-When using DAC driver in continuous mode, it can prevent the system from changing or stopping the clock source in DMA or cosine mode by acquiring a power management lock. When the clock source is generated from APB, the lock type will be set to :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_APB_FREQ_MAX`. When the clock source is APLL (only in DMA mode), it will be set to :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_NO_LIGHT_SLEEP`. Whenever the DAC is converting (i.e., DMA or cosine wave generator is working), the driver guarantees that the power management lock is acquired after calling :cpp:func:`dac_continuous_enable`. Likewise, the driver will release the lock when :cpp:func:`dac_continuous_disable` is called.
+When using DAC driver in continuous mode, it can prevent the system from changing or stopping the clock source in DMA or cosine mode by acquiring a power management lock. The power lock type will be set to :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_APB_FREQ_MAX`. Whenever the DAC is converting (i.e., DMA or cosine wave generator is working), the driver guarantees that the power management lock is acquired after calling :cpp:func:`dac_continuous_enable`. Likewise, the driver will release the lock when :cpp:func:`dac_continuous_disable` is called.
 
 IRAM Safe
 ^^^^^^^^^
diff --git a/docs/en/api-reference/peripherals/dedic_gpio.rst b/docs/en/api-reference/peripherals/dedic_gpio.rst
index 319586f4f66..108abd73e18 100644
--- a/docs/en/api-reference/peripherals/dedic_gpio.rst
+++ b/docs/en/api-reference/peripherals/dedic_gpio.rst
@@ -16,32 +16,21 @@ A GPIO bundle is a group of GPIOs, which can be manipulated at the same time in
 
 .. note::
 
-    Dedicated GPIO is more of a CPU peripheral, so it has a strong relationship with CPU core. It's highly recommended to install and operate GPIO bundle in a pin-to-core task. For example, if GPIOA is connected to CPU0, and the dedicated GPIO instruction is issued from CPU1, then it's impossible to control GPIOA.
+    Dedicated GPIO is more like a CPU peripheral, it has a strong relationship with CPU core. It's highly recommended to install and operate GPIO bundle in the same task, and the task should be pined to a CPU core. For example, if GPIO_A is connected to CPU_0, but the dedicated GPIO instruction is issued from CPU_1, then it's impossible to control GPIO_A.
 
 To install a GPIO bundle, one needs to call :cpp:func:`dedic_gpio_new_bundle` to allocate the software resources and connect the dedicated channels to user selected GPIOs. Configurations for a GPIO bundle are covered in :cpp:type:`dedic_gpio_bundle_config_t` structure:
 
-- :cpp:member:`gpio_array`: An array that contains GPIO number.
-- :cpp:member:`array_size`: Element number of :cpp:member:`gpio_array`.
-- :cpp:member:`flags`: Extra flags to control the behavior of GPIO Bundle.
+- :cpp:member:`dedic_gpio_bundle_config_t::gpio_array`: An array that contains GPIO number.
+- :cpp:member:`dedic_gpio_bundle_config_t::array_size`: Element number of :cpp:member:`dedic_gpio_bundle_config_t::gpio_array`.
+- :cpp:member:`dedic_gpio_bundle_config_t::in_en` and :cpp:member:`dedic_gpio_bundle_config_t::out_en` are used to configure whether to enable the input and output ability of the GPIO(s).
+- :cpp:member:`dedic_gpio_bundle_config_t::in_invert` and :cpp:member:`dedic_gpio_bundle_config_t::out_invert` are used to configure whether to invert the GPIO signal.
 
-  - :cpp:member:`in_en` and :cpp:member:`out_en` are used to select whether to enable the input and output function (note, they can be enabled together).
-  - :cpp:member:`in_invert` and :cpp:member:`out_invert` are used to select whether to invert the GPIO signal.
-
-The following code shows how to install a output only GPIO bundle:
+The following code shows how to install an output only GPIO bundle:
 
 .. highlight:: c
 
 ::
 
-    // configure GPIO
-    const int bundleA_gpios[] = {0, 1};
-    gpio_config_t io_conf = {
-        .mode = GPIO_MODE_OUTPUT,
-    };
-    for (int i = 0; i < sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]); i++) {
-        io_conf.pin_bit_mask = 1ULL << bundleA_gpios[i];
-        gpio_config(&io_conf);
-    }
     // Create bundleA, output only
     dedic_gpio_bundle_handle_t bundleA = NULL;
     dedic_gpio_bundle_config_t bundleA_config = {
@@ -53,11 +42,7 @@ The following code shows how to install a output only GPIO bundle:
     };
     ESP_ERROR_CHECK(dedic_gpio_new_bundle(&bundleA_config, &bundleA));
 
-To uninstall the GPIO bundle, one needs to call :cpp:func:`dedic_gpio_del_bundle`.
-
-.. note::
-
-    :cpp:func:`dedic_gpio_new_bundle` doesn't cover any GPIO pad configuration (e.g., pull up/down, drive ability, output/input enable), so before installing a dedicated GPIO bundle, you have to configure the GPIO separately using GPIO driver API (e.g., :cpp:func:`gpio_config`). For more information about GPIO driver, please refer to :doc:`GPIO API Reference <gpio>`.
+To uninstall the GPIO bundle, you should call :cpp:func:`dedic_gpio_del_bundle`.
 
 
 GPIO Bundle Operations
@@ -92,13 +77,13 @@ For advanced users, they can always manipulate the GPIOs by writing assembly cod
 3. Call CPU LL apis (e.g., `dedic_gpio_cpu_ll_write_mask`) or write assembly code with that mask
 4. The fastest way of toggling IO is to use the dedicated "set/clear" instructions:
 
-    .. only:: esp32s2 or esp32s3
+    .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA
 
         - Set bits of GPIO: ``set_bit_gpio_out imm[7:0]``
         - Clear bits of GPIO: ``clr_bit_gpio_out imm[7:0]``
         - Note: Immediate value width depends on the number of dedicated GPIO channels
 
-    .. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2
+    .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
         - Set bits of GPIO: ``csrrsi rd, csr, imm[4:0]``
         - Clear bits of GPIO: ``csrrci rd, csr, imm[4:0]``
diff --git a/docs/en/api-reference/peripherals/etm.rst b/docs/en/api-reference/peripherals/etm.rst
index b5a6a963ddd..a462082e83c 100644
--- a/docs/en/api-reference/peripherals/etm.rst
+++ b/docs/en/api-reference/peripherals/etm.rst
@@ -32,6 +32,7 @@ The following sections of this document cover the typical steps to configure and
 - :ref:`etm-event` - describes how to allocate a new ETM event handle or fetch an existing handle from various peripherals.
 - :ref:`etm-task` - describes how to allocate a new ETM task handle or fetch an existing handle from various peripherals.
 - :ref:`etm-channel-control` - describes common ETM channel control functions.
+- :ref:`etm-power-management` - describes the options and strategies provided by the driver in order to save power.
 - :ref:`etm-thread-safety` - lists which APIs are guaranteed to be thread-safe by the driver.
 - :ref:`etm-kconfig-options` - lists the supported Kconfig options that can be used to make a different effect on driver behavior.
 
@@ -131,6 +132,17 @@ To check if the ETM channels are set with proper events and tasks, you can call
 
 The digital ID printed in the dump information is defined in the ``soc/soc_etm_source.h`` file.
 
+.. _etm-power-management:
+
+Power Management
+^^^^^^^^^^^^^^^^
+
+When power management is enabled, i.e., :ref:`CONFIG_PM_ENABLE` is on, the system may adjust or disable the clock source, and power off the ETM peripheral before going to sleep. As a result, the existing connection between events and tasks will be lost, and the ETM channels can't work correctly after wake up. So by default, the driver will acquire a power management lock internally to forbid the system from powering off the ETM peripheral.
+
+.. only:: SOC_ETM_SUPPORT_SLEEP_RETENTION
+
+    If you want to save more power, you can set :cpp:member:`esp_etm_channel_config_t::etm_chan_flags::allow_pd` to ``true``. Then ETM registers will be backed up before sleep and restored after wake up. Please note, enabling this option will increase the memory consumption for saving the register context.
+
 .. _etm-thread-safety:
 
 Thread Safety
diff --git a/docs/en/api-reference/peripherals/gpio/esp32c61.inc b/docs/en/api-reference/peripherals/gpio/esp32c61.inc
index 6e312fb9132..dde339064a0 100644
--- a/docs/en/api-reference/peripherals/gpio/esp32c61.inc
+++ b/docs/en/api-reference/peripherals/gpio/esp32c61.inc
@@ -9,7 +9,7 @@
 
 .. gpio-summary
 
-The {IDF_TARGET_NAME} chip features 22 physical GPIO pins (GPIO0 ~ GPIO21). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
+The {IDF_TARGET_NAME} chip features 25 physical GPIO pins (GPIO0 ~ GPIO24). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
 
 The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
 
@@ -23,7 +23,7 @@ The table below provides more information on pin usage, and please note the comm
       - Comments
 
     * - GPIO0
-      - ADC2_CH0
+      -
       - LP_GPIO0
       -
 
@@ -53,7 +53,7 @@ The table below provides more information on pin usage, and please note the comm
       -
 
     * - GPIO6
-      - ADC1_CH5
+      -
       - LP_GPIO6
       -
 
@@ -132,6 +132,21 @@ The table below provides more information on pin usage, and please note the comm
       -
       - SPI0/1
 
+    * - GPIO22
+      -
+      -
+      -
+
+    * - GPIO23
+      -
+      -
+      -
+
+    * - GPIO24
+      -
+      -
+      -
+
 .. note::
 
   - Some pins are used as strapping pins, which can be used to select in which boot mode to load the chip, etc.. The details can be found in `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`_ > ``Strapping Pins``.
diff --git a/docs/en/api-reference/peripherals/i2c.rst b/docs/en/api-reference/peripherals/i2c.rst
index a592b250864..f5e906402b2 100644
--- a/docs/en/api-reference/peripherals/i2c.rst
+++ b/docs/en/api-reference/peripherals/i2c.rst
@@ -44,7 +44,7 @@ I2C Clock Configuration
 
     - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_DEFAULT`: Default I2C source clock.
     :SOC_I2C_SUPPORT_XTAL: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_XTAL`: External crystal for I2C clock source.
-    :SOC_I2C_SUPPORT_RTC: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_RC_FAST`: Internal 20 MHz RC oscillator for I2C clock source.
+    :SOC_I2C_SUPPORT_RTC: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_RC_FAST`: Internal 20 MHz RC oscillator for I2C clock source.
     :SOC_I2C_SUPPORT_APB: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_APB`: APB clock as I2C clock source.
     :SOC_I2C_SUPPORT_REF_TICK: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_REF_TICK`: 1 MHZ clock.
 
@@ -88,7 +88,7 @@ The I2C driver offers following services:
 Resource Allocation
 ^^^^^^^^^^^^^^^^^^^
 
-Both I2C master bus and I2C slave bus, when supported, are represented by :cpp:type:`i2c_bus_handle_t` in the driver. The available ports are managed in a resource pool that allocates a free port on request.
+The I2C master bus is represented by :cpp:type:`i2c_master_bus_handle_t` in the driver. The available ports are managed in a resource pool that allocates a free port on request.
 
 Install I2C master bus and device
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -111,7 +111,7 @@ I2C master bus requires the configuration that specified by :cpp:type:`i2c_maste
 - :cpp:member:`i2c_master_bus_config_t::intr_priority` sets the priority of the interrupt. If set to ``0`` , then the driver will use a interrupt with low or medium priority (priority level may be one of 1, 2 or 3), otherwise use the priority indicated by :cpp:member:`i2c_master_bus_config_t::intr_priority`. Please use the number form (1, 2, 3) , not the bitmask form ((1<<1), (1<<2), (1<<3)).
 - :cpp:member:`i2c_master_bus_config_t::trans_queue_depth` sets the depth of internal transfer queue. Only valid in asynchronous transaction.
 - :cpp:member:`i2c_master_bus_config_t::enable_internal_pullup` enables internal pullups. Note: This is not strong enough to pullup buses under high-speed frequency. A suitable external pullup is recommended.
-
+- :cpp:member:`i2c_master_bus_config_t::allow_pd` configures if the driver allows the system to power down the peripheral in light sleep mode. Before entering sleep, the system will backup the I2C register context, which will be restored later when the system exit the sleep mode. Powering down the peripheral can save more power, but at the cost of more memory consumed to save the register context. It's a tradeoff between power consumption and memory consumption. This configuration option relies on specific hardware feature, if you enable it on an unsupported chip, you will see error message like ``not able to power down in light sleep``.
 
 If the configurations in :cpp:type:`i2c_master_bus_config_t` is specified, then :cpp:func:`i2c_new_master_bus` can be called to allocate and initialize an I2C master bus. This function will return an I2C bus handle if it runs correctly. Specifically, when there are no more I2C port available, this function will return :c:macro:`ESP_ERR_NOT_FOUND` error.
 
@@ -166,7 +166,6 @@ When the I2C master handle has been initialized in one module (e.g. the audio mo
     ESP_ERROR_CHECK(i2c_new_master_bus(&i2c_mst_config, &bus_handle));
 
     // Source File 2
-    #include "esp_private/i2c_platform.h"
     #include "driver/i2c_master.h"
     i2c_master_bus_handle_t handle;
     ESP_ERROR_CHECK(i2c_master_get_bus_handle(0, &handle));
@@ -394,7 +393,7 @@ Please note that no STOP condition bit is inserted between the write and read op
     };
 
     i2c_master_dev_handle_t dev_handle;
-    ESP_ERROR_CHECK(i2c_master_bus_add_device(I2C_PORT_NUM_0, &dev_cfg, &dev_handle));
+    ESP_ERROR_CHECK(i2c_master_bus_add_device(bus_handle, &dev_cfg, &dev_handle));
     uint8_t buf[20] = {0x20};
     uint8_t buffer[2];
     ESP_ERROR_CHECK(i2c_master_transmit_receive(dev_handle, buf, sizeof(buf), buffer, 2, -1));
@@ -452,20 +451,20 @@ Simple example for writing data to FIFO:
     i2c_slave_config_t i2c_slv_config = {
         .addr_bit_len = I2C_ADDR_BIT_LEN_7,   // 7-bit address
         .clk_source = I2C_CLK_SRC_DEFAULT,    // set the clock source
-        .i2c_port = 0,                        // set I2C port number
+        .i2c_port = TEST_I2C_PORT,            // set I2C port number
         .send_buf_depth = 256,                // set TX buffer length
-        .scl_io_num = 2,                      // SCL GPIO number
-        .sda_io_num = 1,                      // SDA GPIO number
+        .scl_io_num = I2C_SLAVE_SCL_IO,       // SCL GPIO number
+        .sda_io_num = I2C_SLAVE_SDA_IO,       // SDA GPIO number
         .slave_addr = 0x58,                   // slave address
     };
 
-    i2c_bus_handle_t i2c_bus_handle;
-    ESP_ERROR_CHECK(i2c_new_slave_device(&i2c_slv_config, &i2c_bus_handle));
+    i2c_slave_dev_handle_t slave_handle;
+    ESP_ERROR_CHECK(i2c_new_slave_device(&i2c_slv_config, &slave_handle));
     for (int i = 0; i < DATA_LENGTH; i++) {
         data_wr[i] = i;
     }
 
-    ESP_ERROR_CHECK(i2c_slave_transmit(i2c_bus_handle, data_wr, DATA_LENGTH, 10000));
+    ESP_ERROR_CHECK(i2c_slave_transmit(slave_handle, data_wr, DATA_LENGTH, 10000));
 
 I2C Slave Read
 ~~~~~~~~~~~~~~
diff --git a/docs/en/api-reference/peripherals/i2s.rst b/docs/en/api-reference/peripherals/i2s.rst
index 9d0ad91bb1b..ea3dd9467bd 100644
--- a/docs/en/api-reference/peripherals/i2s.rst
+++ b/docs/en/api-reference/peripherals/i2s.rst
@@ -78,6 +78,10 @@ Clock Source
 
     - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`: 160 MHz PLL clock.
 
+.. only:: SOC_I2S_SUPPORTS_PLL_F120M
+
+    - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_120M`: 120 MHz PLL clock.
+
 .. only:: SOC_I2S_SUPPORTS_PLL_F96M
 
     - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`: 96 MHz PLL clock.
@@ -232,7 +236,7 @@ Power Management
 
 When the power management is enabled (i.e., :ref:`CONFIG_PM_ENABLE` is on), the system will adjust or stop the source clock of I2S before entering Light-sleep, thus potentially changing the I2S signals and leading to transmitting or receiving invalid data.
 
-The I2S driver can prevent the system from changing or stopping the source clock by acquiring a power management lock. When the source clock is generated from APB, the lock type will be set to :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_APB_FREQ_MAX` and when the source clock is APLL (if supported), it will be set to :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_NO_LIGHT_SLEEP`. Whenever the user is reading or writing via I2S (i.e., calling :cpp:func:`i2s_channel_read` or :cpp:func:`i2s_channel_write`), the driver guarantees that the power management lock is acquired. Likewise, the driver releases the lock after the reading or writing finishes.
+The I2S driver can prevent the system from changing or stopping the source clock by acquiring a power management lock. The power lock type will be set to :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_APB_FREQ_MAX`. Whenever the user is reading or writing via I2S (i.e., calling :cpp:func:`i2s_channel_read` or :cpp:func:`i2s_channel_write`), the driver guarantees that the power management lock is acquired. Likewise, the driver releases the lock after the reading or writing finishes.
 
 .. only:: SOC_I2S_SUPPORT_SLEEP_RETENTION
 
diff --git a/docs/en/api-reference/peripherals/index.rst b/docs/en/api-reference/peripherals/index.rst
index 3a959b72490..0e0fd30b16a 100644
--- a/docs/en/api-reference/peripherals/index.rst
+++ b/docs/en/api-reference/peripherals/index.rst
@@ -42,8 +42,8 @@ Peripherals API
     :SOC_GPSPI_SUPPORTED: spi_slave
     :SOC_SPI_SUPPORT_SLAVE_HD_VER2: spi_slave_hd
     :SOC_TEMP_SENSOR_SUPPORTED: temp_sensor
-    :SOC_TOUCH_SENSOR_SUPPORTED and not esp32p4: touch_pad
-    :esp32p4: cap_touch_sens
+    :esp32: touch_pad
+    :SOC_TOUCH_SENSOR_SUPPORTED and not esp32: cap_touch_sens
     :esp32s2: touch_element
     :SOC_TWAI_SUPPORTED: twai
     uart
diff --git a/docs/en/api-reference/peripherals/isp.rst b/docs/en/api-reference/peripherals/isp.rst
index 13e7ff499a0..865e0d5d5d2 100644
--- a/docs/en/api-reference/peripherals/isp.rst
+++ b/docs/en/api-reference/peripherals/isp.rst
@@ -1,24 +1,29 @@
-Image Signal Processor
-======================
+Image Signal Processor (ISP)
+============================
+
+:link_to_translation:`zh_CN:[中文]`
 
 Introduction
 ------------
 
-{IDF_TARGET_NAME} includes an Image Signal Processor (ISP), which is a feature pipeline that consists of many image processing algorithms. ISP receives image data from the DVP camera or MIPI-CSI camera, or system memory, and writes the processed image data to the system memory through DMA. The ISP is designed to work with other camera controller modules and cannot operate independently.
+{IDF_TARGET_NAME} includes an Image Signal Processor (ISP), which is a feature pipeline that consists of many image processing algorithms. ISP receives image data from the DVP camera or MIPI-CSI camera, or system memory, and writes the processed image data to the system memory through DMA. The ISP is designed to work with other camera controller modules and can not operate independently.
 
 Terminology
 -----------
 
 .. list::
-  - MIPI-CSI: Camera serial interface, a high-speed serial interface for cameras compliant with MIPI specifications
-  - DVP: Digital video parallel interface, generally composed of vsync, hsync, de, and data signals
-  - RAW: Unprocessed data directly output from an image sensor, typically divided into R, Gr, Gb, and B four channels classified into RAW8, RAW10, RAW12, etc., based on bit width
-  - RGB: Colored image format composed of red, green, and blue colors classified into RGB888, RGB565, etc., based on the bit width of each color
-  - YUV: Colored image format composed of luminance and chrominance classified into YUV444, YUV422, YUV420, etc., based on the data arrangement
-  - AF:  Auto-focus
-  - AWB: Auto-white balance
-  - BF:  Bayer noise filter
-  - CCM: Color correction matrix
+
+    - MIPI-CSI: Camera serial interface, a high-speed serial interface for cameras compliant with MIPI specifications
+    - DVP: Digital video parallel interface, generally composed of vsync, hsync, de, and data signals
+    - RAW: Unprocessed data directly output from an image sensor, typically divided into R, Gr, Gb, and B four channels classified into RAW8, RAW10, RAW12, etc., based on bit width
+    - RGB: Colored image format composed of red, green, and blue colors classified into RGB888, RGB565, etc., based on the bit width of each color
+    - YUV: Colored image format composed of luminance and chrominance classified into YUV444, YUV422, YUV420, etc., based on the data arrangement
+    - AF: Auto focus
+    - AWB: Auto white balance
+    - AE: Auto exposure
+    - HIST: Histogram
+    - BF: Bayer noise filter
+    - CCM: Color correction matrix
 
 ISP Pipeline
 ------------
@@ -38,7 +43,7 @@ ISP Pipeline
         isp_header [label = "ISP Header"];
         isp_tail [label = "ISP Tail"];
         isp_chs [label = "Contrast &\n Hue & Saturation", width = 150, height = 70];
-        isp_yuv [label = "YUV Limit\nYUB2RGB", width = 120, height = 70];
+        isp_yuv [label = "YUV Limit\n YUB2RGB", width = 120, height = 70];
 
         isp_header -> BF -> Demosaic -> CCM -> Gamma -> RGB2YUV -> SHARP -> isp_chs -> isp_yuv -> isp_tail;
 
@@ -49,7 +54,7 @@ ISP Pipeline
         CCM -> AWB
         Gamma -> AE
         RGB2YUV -> HIST
-        SHARP -> AF
+        RGB2YUV -> AF
     }
 
 Functional Overview
@@ -57,21 +62,21 @@ Functional Overview
 
 The ISP driver offers following services:
 
--  `Resource Allocation <#isp-resource-allocation>`__ - covers how to allocate ISP resources with properly set of configurations. It also covers how to recycle the resources when they finished working.
--  `Enable and disable ISP processor <#isp-enable-disable>`__ - covers how to enable and disable an ISP processor.
--  `Get AF statistics in one shot or continuous way <#isp-af-statistics>`__ - covers how to get AF statistics one-shot or continuously.
--  `Get AE statistics in one shot or continuous way <#isp-ae-statistics>`__ - covers how to get AE statistics one-shot or continuously.
--  `Get AWB statistics in one shot or continuous way <#isp-awb-statistics>`__ - covers how to get AWB white patches statistics one-shot or continuously.
--  `Get histogram statistics in one shot or continuous way <#isp-hist-statistics>`__ - covers how to get histogram statistics one-shot or continuously.
--  `Enable BF function <#isp_bf>`__ - covers how to enable and configure BF function.
--  `Configure CCM <#isp-ccm-config>`__ - covers how to configure the Color Correction Matrix.
--  `Configure Demosaic <#isp-demosaic>`__ - covers how to config the Demosaic function.
--  `Enable Gamma Correction <#isp-gamma-correction>`__ - covers how to enable and configure gamma correction.
--  `Configure Sharpen <#isp-sharpen>`__ - covers how to config the Sharpen function.
--  `Register callback <#isp-callback>`__ - covers how to hook user specific code to ISP driver event callback function.
--  `Thread Safety <#isp-thread-safety>`__ - lists which APIs are guaranteed to be thread safe by the driver.
--  `Kconfig Options <#isp-kconfig-options>`__ - lists the supported Kconfig options that can bring different effects to the driver.
--  `IRAM SAFE <#isp-iram-safe>`__ - describes tips on how to make the ISP interrupt and control functions work better along with a disabled cache.
+- :ref:`isp-resource-allocation` - covers how to allocate ISP resources with properly set of configurations. It also covers how to recycle the resources when they finished working.
+- :ref:`isp-enable-disable` - covers how to enable and disable an ISP processor.
+- :ref:`isp-af-statistics` - covers how to get AF statistics one-shot or continuously.
+- :ref:`isp-awb-statistics` - covers how to get AWB white patches statistics one-shot or continuously.
+- :ref:`isp-ae-statistics` - covers how to get AE statistics one-shot or continuously.
+- :ref:`isp-hist-statistics` - covers how to get histogram statistics one-shot or continuously.
+- :ref:`isp-bf` - covers how to enable and configure BF function.
+- :ref:`isp-ccm-config` - covers how to configure the CCM.
+- :ref:`isp-demosaic` - covers how to configure the Demosaic function.
+- :ref:`isp-gamma-correction` - covers how to enable and configure gamma correction.
+- :ref:`isp-sharpen` - covers how to configure the sharpening function.
+- :ref:`isp-callback` - covers how to hook user specific code to ISP driver event callback function.
+- :ref:`isp-thread-safety` - lists which APIs are guaranteed to be thread safe by the driver.
+- :ref:`isp-kconfig-options` - lists the supported Kconfig options that can bring different effects to the driver.
+- :ref:`isp-iram-safe` - describes tips on how to make the ISP interrupt and control functions work better along with a disabled cache.
 
 .. _isp-resource-allocation:
 
@@ -83,9 +88,9 @@ Install ISP Driver
 
 ISP driver requires the configuration that specified by :cpp:type:`esp_isp_processor_cfg_t`.
 
-If the configurations in :cpp:type:`esp_isp_processor_cfg_t` is specified, users can call :cpp:func:`esp_isp_new_processor` to allocate and initialize an ISP processor. This function will return an ISP processor handle if it runs correctly. You can take following code as reference.
+If the configurations in :cpp:type:`esp_isp_processor_cfg_t` is specified, users can call :cpp:func:`esp_isp_new_processor` to allocate and initialize an ISP processor. This function will return an ISP processor handle if it runs correctly. You can take following code as reference:
 
-.. code:: c
+.. code-block:: c
 
     esp_isp_processor_cfg_t isp_config = {
         .clk_src = ISP_CLK_SRC_DEFAULT,
@@ -95,17 +100,17 @@ If the configurations in :cpp:type:`esp_isp_processor_cfg_t` is specified, users
     isp_proc_handle_t isp_proc = NULL;
     ESP_ERROR_CHECK(esp_isp_new_processor(&isp_config, &isp_proc));
 
-You can use the created handle to do driver enable / disable the ISP driver and do other ISP module installation.
+You can use the created handle to enable/disable the ISP driver and do other ISP module installation.
 
 
-Install ISP Auto-Focus (AF) Driver
+Install ISP Auto Focus (AF) Driver
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-ISP auto-focus (AF) driver requires the configuration that specified by :cpp:type:`esp_isp_af_config_t`.
+ISP auto focus (AF) driver requires the configuration that specified by :cpp:type:`esp_isp_af_config_t`.
 
-If the configurations in :cpp:type:`esp_isp_af_config_t` is specified, users can call :cpp:func:`esp_isp_new_af_controller` to allocate and initialize an ISP AF processor. This function will return an ISP AF processor handle if it runs correctly. You can take following code as reference.
+If the configurations in :cpp:type:`esp_isp_af_config_t` is specified, users can call :cpp:func:`esp_isp_new_af_controller` to allocate and initialize an ISP AF controller. This function will return an ISP AF controller handle if it runs correctly. You can take following code as reference:
 
-.. code:: c
+.. code-block:: c
 
     esp_isp_af_config_t af_config = {
         .edge_thresh = 128,
@@ -113,16 +118,16 @@ If the configurations in :cpp:type:`esp_isp_af_config_t` is specified, users can
     isp_af_ctlr_t af_ctrlr = NULL;
     ESP_ERROR_CHECK(esp_isp_new_af_controller(isp_proc, &af_config, &af_ctrlr));
 
-You can use the created handle to do driver enable / disable the ISP AF driver and ISP AF Env module installation.
+You can use the created handle to enable/disable the ISP AF driver and install ISP AF environment detector module.
 
-Install ISP Auto-White-Balance (AWB) Driver
+Install ISP Auto White Balance (AWB) Driver
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-ISP auto-white-balance (AWB) driver requires the configuration specified by :cpp:type:`esp_isp_awb_config_t`.
+ISP auto white balance (AWB) driver requires the configuration specified by :cpp:type:`esp_isp_awb_config_t`.
 
-If an :cpp:type:`esp_isp_awb_config_t` configuration is specified, you can call :cpp:func:`esp_isp_new_awb_controller` to allocate and initialize an ISP AWB processor. This function will return an ISP AWB processor handle on success. You can take following code as reference.
+If an :cpp:type:`esp_isp_awb_config_t` configuration is specified, you can call :cpp:func:`esp_isp_new_awb_controller` to allocate and initialize an ISP AWB controller. This function will return an ISP AWB controller handle on success. You can take following code as reference:
 
-.. code:: c
+.. code-block:: c
 
     isp_awb_ctlr_t awb_ctlr = NULL;
     uint32_t image_width = 800;
@@ -136,14 +141,14 @@ If an :cpp:type:`esp_isp_awb_config_t` configuration is specified, you can call
 
 The AWB handle created in this step is required by other AWB APIs and AWB scheme.
 
-Install ISP Auto-Exposure (AE) Driver
+Install ISP Auto Exposure (AE) Driver
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-ISP auto-exposure (AE) driver requires the configuration that specified by :cpp:type:`esp_isp_ae_config_t`.
+ISP auto exposure (AE) driver requires the configuration that specified by :cpp:type:`esp_isp_ae_config_t`.
 
-If the configurations in :cpp:type:`esp_isp_ae_config_t` is specified, users can call :cpp:func:`esp_isp_new_ae_controller` to allocate and initialize an ISP AE processor. This function will return an ISP AE processor handle if it runs correctly. You can take following code as reference.
+If the configurations in :cpp:type:`esp_isp_ae_config_t` is specified, call :cpp:func:`esp_isp_new_ae_controller` to allocate and initialize an ISP AE controller. This function will return an ISP AE controller handle if it runs correctly. You can take following code as reference.
 
-.. code:: c
+.. code-block:: c
 
     esp_isp_ae_config_t ae_config = {
         .sample_point = ISP_AE_SAMPLE_POINT_AFTER_DEMOSAIC,
@@ -152,20 +157,20 @@ If the configurations in :cpp:type:`esp_isp_ae_config_t` is specified, users can
     isp_ae_ctlr_t ae_ctlr = NULL;
     ESP_ERROR_CHECK(esp_isp_new_ae_controller(isp_proc, &ae_config, &ae_ctlr));
 
-You can use the created handle to do driver enable / disable the ISP AE driver and ISP AE environment detector setup.
+You can use the created handle to enable/disable the ISP AE driver and do ISP AE environment detector setup.
 
-Install ISP histogram (HIST) Driver
+Install ISP Histogram (HIST) Driver
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 ISP histogram (HIST) driver requires the configuration that specified by :cpp:type:`esp_isp_hist_config_t`.
 
-If the configurations in :cpp:type:`esp_isp_hist_config_t` is specified, users can call :cpp:func:`esp_isp_new_hist_controller` to allocate and initialize an ISP Histogram processor. This function will return an ISP HIST processor handle if it runs correctly. You can take following code as reference.
+If the configurations in :cpp:type:`esp_isp_hist_config_t` is specified, users can call :cpp:func:`esp_isp_new_hist_controller` to allocate and initialize an ISP Histogram controller. This function will return an ISP HIST controller handle if it runs correctly. You can take following code as reference.
 
 .. list::
 
-    - The sum of all subwindows weight's decimal value should be 256 or the statistics will be small, and integer value should be 0.
-    - The sum of all RGB coefficients' decimal value should be 256 or the statistics will be small, and integer value should be 0.
-    - The segment_threshold must be 0 ~ 255 and in order
+    - The sum of all subwindow weights' decimal values should be 256; otherwise, the statistics will be small. The integer value should be 0.
+    - The sum of all RGB coefficients' decimal values should be 256; otherwise, the statistics will be small. The integer value should be 0.
+    - The segment_threshold must be 0–255 and in order.
 
 .. code:: c
 
@@ -195,20 +200,20 @@ If the configurations in :cpp:type:`esp_isp_hist_config_t` is specified, users c
     isp_hist_ctlr_t hist_ctlr_ctlr = NULL;
     ESP_ERROR_CHECK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr));
 
-You can use the created handle to do driver enable / disable the ISP HIST driver setup.
+You can use the created handle to enable/disable the ISP HIST driver setup.
 
-Uninstall ISP Driver(s)
+Uninstall ISP Drivers
 ~~~~~~~~~~~~~~~~~~~~~~~
 
-If a previously installed ISP driver(s) are not needed, it's recommended to recycle the resource by following APIs to release the underlying hardware:
+If previously installed ISP drivers are no longer needed, it's recommended to recycle the resource by following APIs to release the underlying hardware:
 
 .. list::
 
     - :cpp:func:`esp_isp_del_processor`, for ISP processor.
-    - :cpp:func:`esp_isp_del_af_controller`, for ISP AF processor.
-    - :cpp:func:`esp_isp_del_awb_controller`, for ISP AWB processor.
-    - :cpp:func:`esp_isp_del_ae_controller`, for ISP AE processor.
-    - :cpp:func:`esp_isp_del_hist_controller`, for ISP Histogram processor.
+    - :cpp:func:`esp_isp_del_af_controller`, for ISP AF controller.
+    - :cpp:func:`esp_isp_del_awb_controller`, for ISP AWB controller.
+    - :cpp:func:`esp_isp_del_ae_controller`, for ISP AE controller.
+    - :cpp:func:`esp_isp_del_hist_controller`, for ISP Histogram controller.
 
 .. _isp-enable-disable:
 
@@ -224,10 +229,10 @@ Before doing ISP pipeline, you need to enable the ISP processor first, by callin
 
 Calling :cpp:func:`esp_isp_disable` does the opposite, that is, put the driver back to the **init** state.
 
-ISP AF Processor
-~~~~~~~~~~~~~~~~
+ISP AF Controller
+~~~~~~~~~~~~~~~~~
 
-Before doing ISP AF, you need to enable the ISP AF processor first, by calling :cpp:func:`esp_isp_af_controller_enable`. This function:
+Before doing ISP AF, you need to enable the ISP AF controller first, by calling :cpp:func:`esp_isp_af_controller_enable`. This function:
 
 * Switches the driver state from **init** to **enable**.
 
@@ -238,13 +243,14 @@ Calling :cpp:func:`esp_isp_af_controller_disable` does the opposite, that is, pu
 AF One-shot and Continuous Statistics
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-Calling :cpp:func:`esp_isp_af_controller_get_oneshot_statistics` to get oneshot AF statistics result. You can take following code as reference.
+Calling :cpp:func:`esp_isp_af_controller_get_oneshot_statistics` to get one-shot AF statistics result. You can take following code as reference.
 
-Aside from the above oneshot API, the ISP AF driver also provides a way to start AF statistics continuously. Calling :cpp:func:`esp_isp_af_controller_start_continuous_statistics` to start the continuous statistics and :cpp:func:`esp_isp_af_controller_stop_continuous_statistics` to stop it.
+Aside from the above one-shot API, the ISP AF driver also provides a way to start AF statistics continuously. Calling :cpp:func:`esp_isp_af_controller_start_continuous_statistics` to start the continuous statistics and :cpp:func:`esp_isp_af_controller_stop_continuous_statistics` to stop it.
 
-Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_statistics_done` or :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_change` callback to get the statistics result. See how to register in `Register Event Callbacks <#isp-callback>`__
+Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_statistics_done` or :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_change` callbacks to get the statistics result. See how to register in :ref:`isp-callback`.
 
 .. note::
+
     When you use the continuous statistics, AF Environment Detector will be invalid.
 
 .. code:: c
@@ -256,7 +262,7 @@ Note that if you want to use the continuous statistics, you need to register the
     ESP_ERROR_CHECK(esp_isp_new_af_controller(isp_proc, &af_config, &af_ctrlr));
     ESP_ERROR_CHECK(esp_isp_af_controller_enable(af_ctrlr));
     isp_af_result_t result = {};
-    /* Trigger the AF statistics and get its result for one time with timeout value 2000ms. */
+    /* Trigger the AF statistics and get its result for one time with timeout value 2000 ms */
     ESP_ERROR_CHECK(esp_isp_af_controller_get_oneshot_statistics(af_ctrlr, 2000, &result));
 
     /* Start continuous AF statistics */
@@ -267,17 +273,17 @@ Note that if you want to use the continuous statistics, you need to register the
     /* Stop continuous AF statistics */
     ESP_ERROR_CHECK(esp_isp_af_controller_stop_continuous_statistics(af_ctrlr));
 
-    /* Disable the af controller */
+    /* Disable the AF controller */
     ESP_ERROR_CHECK(esp_isp_af_controller_disable(af_ctrlr));
-    /* Delete the af controller and free the resources */
+    /* Delete the AF controller and free the resources */
     ESP_ERROR_CHECK(esp_isp_del_af_controller(af_ctrlr));
 
 Set AF Environment Detector
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-Calling :cpp:func:`esp_isp_af_controller_set_env_detector` to set an ISP AF environment detector. You can take following code as reference.
+Calling :cpp:func:`esp_isp_af_controller_set_env_detector` to set an ISP AF environment detector. You can take following code as reference:
 
-.. code:: c
+.. code-block:: c
 
     esp_isp_af_env_config_t env_config = {
         .interval = 10,
@@ -289,18 +295,77 @@ Calling :cpp:func:`esp_isp_af_controller_set_env_detector` to set an ISP AF envi
 Set AF Environment Detector Threshold
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-Calling :cpp:func:`esp_isp_af_env_detector_set_threshold` to set the threshold of an ISP AF environment detector.
+Calling :cpp:func:`esp_isp_af_controller_set_env_detector_threshold` to set the threshold of an ISP AF environment detector.
 
-.. code:: c
+.. code-block:: c
 
     int definition_thresh = 0;
     int luminance_thresh = 0;
     ESP_ERROR_CHECK(esp_isp_af_env_detector_set_threshold(env_detector, definition_thresh, luminance_thresh));
 
-ISP AE Processor
-----------------
+ISP AWB Controller
+~~~~~~~~~~~~~~~~~~
 
-Before doing ISP AE, you need to enable the ISP AE processor first, by calling :cpp:func:`esp_isp_ae_controller_enable`. This function:
+Before doing ISP AWB, you need to enable the ISP AWB controller first, by calling :cpp:func:`esp_isp_awb_controller_enable`. This function:
+
+* Switches the driver state from **init** to **enable**.
+
+Calling :cpp:func:`esp_isp_awb_controller_disable` does the opposite, that is, put the driver back to the **init** state.
+
+.. _isp-awb-statistics:
+
+AWB One-shot and Continuous Statistics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Calling :cpp:func:`esp_isp_awb_controller_get_oneshot_statistics` to get oneshot AWB statistics result of white patches. You can take following code as reference.
+
+Aside from the above one-shot API, the ISP AWB driver also provides a way to start AWB statistics continuously. Calling :cpp:func:`esp_isp_awb_controller_start_continuous_statistics` starts the continuous statistics and :cpp:func:`esp_isp_awb_controller_stop_continuous_statistics` stops it.
+
+Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_awb_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in :ref:`isp-callback`.
+
+.. code-block:: c
+
+    bool example_isp_awb_on_statistics_done_cb(isp_awb_ctlr_t awb_ctlr, const esp_isp_awb_evt_data_t *edata, void *user_data);
+    // ...
+    isp_awb_ctlr_t awb_ctlr = NULL;
+    uint32_t image_width = 800;
+    uint32_t image_height = 600;
+    /* The AWB configuration, please refer to the API comment for how to tune these parameters */
+    esp_isp_awb_config_t awb_config = {
+        .sample_point = ISP_AWB_SAMPLE_POINT_AFTER_CCM,
+        ...
+    };
+    isp_awb_stat_result_t stat_res = {};
+    /* Create the AWB controller */
+    ESP_ERROR_CHECK(esp_isp_new_awb_controller(isp_proc, &awb_config, &awb_ctlr));
+    /* Register the AWB callback */
+    esp_isp_awb_cbs_t awb_cb = {
+        .on_statistics_done = example_isp_awb_on_statistics_done_cb,
+    };
+    ESP_ERROR_CHECK(esp_isp_awb_register_event_callbacks(awb_ctlr, &awb_cb, NULL));
+    /* Enable the AWB controller */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_enable(awb_ctlr));
+
+    /* Get one-shot AWB statistics result */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_get_oneshot_statistics(awb_ctlr, -1, &stat_res));
+
+    /* Start continuous AWB statistics, note that continuous statistics requires `on_statistics_done` callback */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_start_continuous_statistics(awb_ctlr));
+    // You can do other stuffs here, the statistics result can be obtained in the callback
+    // ......
+    // vTaskDelay(pdMS_TO_TICKS(1000));
+    /* Stop continuous AWB statistics */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_stop_continuous_statistics(awb_ctlr));
+
+    /* Disable the AWB controller */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_disable(awb_ctlr));
+    /* Delete the AWB controller and free the resources */
+    ESP_ERROR_CHECK(esp_isp_del_awb_controller(awb_ctlr));
+
+ISP AE Controller
+~~~~~~~~~~~~~~~~~
+
+Before doing ISP AE, you need to enable the ISP AE controller first, by calling :cpp:func:`esp_isp_ae_controller_enable`. This function:
 
 * Switches the driver state from **init** to **enable**.
 
@@ -313,16 +378,17 @@ AE One-shot and Continuous Statistics
 
 Calling :cpp:func:`esp_isp_ae_controller_get_oneshot_statistics` to get oneshot AE statistics result. You can take following code as reference.
 
-When you use AE oneshot statistics, the AE continuous mode need to be disabled otherwise the result may be overwritten by the environment detector. After oneshot operation finishes, you need to restart continuous mode again.
+When using AE oneshot statistics, the AE continuous mode need to be disabled otherwise the result may be overwritten by the environment detector. After oneshot operation finishes, you need to restart continuous mode again.
 
 Aside from the above oneshot API, the ISP AE driver also provides a way to start AE statistics continuously. Calling :cpp:func:`esp_isp_ae_controller_start_continuous_statistics` to start the continuous statistics and :cpp:func:`esp_isp_ae_controller_stop_continuous_statistics` to stop it.
 
-Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_statistics_done` or :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_change` callback to get the statistics result. See how to register in `Register Event Callbacks <#isp-callback>`__
+Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` or :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` callback to get the statistics result. See how to register in :ref:`isp-callback`.
 
 .. note::
-    When using oneshot statistics, the AE Environment Detector will be temporarily disabled and will automatically recover once the oneshot is complete.
 
-.. code:: c
+    When using oneshot statistics, the AE environment detector will be temporarily disabled and will automatically recover once the oneshot is completed.
+
+.. code-block:: c
 
     esp_isp_ae_config_t ae_config = {
         .sample_point = ISP_AE_SAMPLE_POINT_AFTER_DEMOSAIC,
@@ -331,7 +397,7 @@ Note that if you want to use the continuous statistics, you need to register the
     ESP_ERROR_CHECK(esp_isp_new_ae_controller(isp_proc, &ae_config, &ae_ctlr));
     ESP_ERROR_CHECK(esp_isp_ae_controller_enable(ae_ctlr));
     isp_ae_result_t result = {};
-    /* Trigger the AE statistics and get its result for one time with timeout value 2000ms. */
+    /* Trigger the AE statistics and get its result for one time with timeout value 2000 ms. */
     ESP_ERROR_CHECK(esp_isp_ae_controller_get_oneshot_statistics(ae_ctlr, 2000, &result));
 
     /* Start continuous AE statistics */
@@ -342,9 +408,9 @@ Note that if you want to use the continuous statistics, you need to register the
     /* Stop continuous AE statistics */
     ESP_ERROR_CHECK(esp_isp_ae_controller_stop_continuous_statistics(ae_ctlr));
 
-    /* Disable the ae controller */
+    /* Disable the AE controller */
     ESP_ERROR_CHECK(esp_isp_ae_controller_disable(ae_ctlr));
-    /* Delete the ae controller and free the resources */
+    /* Delete the AE controller and free the resources */
     ESP_ERROR_CHECK(esp_isp_del_ae_controller(ae_ctlr));
 
 Set AE Environment Detector
@@ -362,7 +428,7 @@ Calling :cpp:func:`esp_isp_ae_controller_set_env_detector` to set an ISP AE envi
 Set AE Environment Detector Threshold
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-Calling :cpp:func:`esp_isp_ae_controller_set_env_detector_threshold` to set the thresholds(1-255) of an ISP AE environment detector.
+Calling :cpp:func:`esp_isp_ae_controller_set_env_detector_threshold` to set the thresholds (1-255) of an ISP AE environment detector.
 
 .. code:: c
 
@@ -372,71 +438,12 @@ Calling :cpp:func:`esp_isp_ae_controller_set_env_detector_threshold` to set the
     };
     ESP_ERROR_CHECK(esp_isp_ae_controller_set_env_detector_threshold(ae_ctlr, env_thresh));
 
-ISP AWB Processor
-~~~~~~~~~~~~~~~~~
-
-Before doing ISP AWB, you need to enable the ISP AWB processor first, by calling :cpp:func:`esp_isp_awb_controller_enable`. This function:
-
-* Switches the driver state from **init** to **enable**.
-
-Calling :cpp:func:`esp_isp_awb_controller_disable` does the opposite, that is, put the driver back to the **init** state.
-
-.. _isp-awb-statistics:
-
-AWB One-shot and Continuous Statistics
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Calling :cpp:func:`esp_isp_awb_controller_get_oneshot_statistics` to get oneshot AWB statistics result of white patches. You can take following code as reference.
-
-Aside from the above oneshot API, the ISP AWB driver also provides a way to start AWB statistics continuously. Calling :cpp:func:`esp_isp_awb_controller_start_continuous_statistics` starts the continuous statistics and :cpp:func:`esp_isp_awb_controller_stop_continuous_statistics` stops it.
-
-Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_awb_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in `Register Event Callbacks <#isp-callback>`__
-
-.. code:: c
-
-    bool example_isp_awb_on_statistics_done_cb(isp_awb_ctlr_t awb_ctlr, const esp_isp_awb_evt_data_t *edata, void *user_data);
-    // ...
-    isp_awb_ctlr_t awb_ctlr = NULL;
-    uint32_t image_width = 800;
-    uint32_t image_height = 600;
-    /* The AWB configuration, please refer to the API comment for how to tune these parameters */
-    esp_isp_awb_config_t awb_config = {
-        .sample_point = ISP_AWB_SAMPLE_POINT_AFTER_CCM,
-        ...
-    };
-    isp_awb_stat_result_t stat_res = {};
-    /* Create the awb controller */
-    ESP_ERROR_CHECK(esp_isp_new_awb_controller(isp_proc, &awb_config, &awb_ctlr));
-    /* Register AWB callback */
-    esp_isp_awb_cbs_t awb_cb = {
-        .on_statistics_done = example_isp_awb_on_statistics_done_cb,
-    };
-    ESP_ERROR_CHECK(esp_isp_awb_register_event_callbacks(awb_ctlr, &awb_cb, NULL));
-    /* Enabled the awb controller */
-    ESP_ERROR_CHECK(esp_isp_awb_controller_enable(awb_ctlr));
-
-    /* Get oneshot AWB statistics result */
-    ESP_ERROR_CHECK(esp_isp_awb_controller_get_oneshot_statistics(awb_ctlr, -1, &stat_res));
-
-    /* Start continuous AWB statistics, note that continuous statistics requires `on_statistics_done` callback */
-    ESP_ERROR_CHECK(esp_isp_awb_controller_start_continuous_statistics(awb_ctlr));
-    // You can do other stuffs here, the statistics result can be obtained in the callback
-    // ......
-    // vTaskDelay(pdMS_TO_TICKS(1000));
-    /* Stop continuous AWB statistics */
-    ESP_ERROR_CHECK(esp_isp_awb_controller_stop_continuous_statistics(awb_ctlr));
-
-    /* Disable the awb controller */
-    ESP_ERROR_CHECK(esp_isp_awb_controller_disable(awb_ctlr));
-    /* Delete the awb controller and free the resources */
-    ESP_ERROR_CHECK(esp_isp_del_awb_controller(awb_ctlr));
-
 .. _isp-hist:
 
-ISP histogram Processor
------------------------
+ISP Histogram Controller
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-Before doing ISP histogram statistics, you need to enable the ISP histogram processor first, by calling :cpp:func:`esp_isp_hist_controller_enable`. This function:
+Before doing ISP histogram statistics, you need to enable the ISP histogram controller first, by calling :cpp:func:`esp_isp_hist_controller_enable`. This function:
 
 * Switches the driver state from **init** to **enable**.
 
@@ -451,7 +458,7 @@ Calling :cpp:func:`esp_isp_hist_controller_get_oneshot_statistics` to get onesho
 
 Aside from the above oneshot API, the ISP histogram driver also provides a way to start histogram statistics continuously. Calling :cpp:func:`esp_isp_hist_controller_start_continuous_statistics` starts the continuous statistics and :cpp:func:`esp_isp_hist_controller_stop_continuous_statistics` stops it.
 
-Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in `Register Event Callbacks <#isp-callback>`__
+Note that if you want to use the continuous statistics, you need to register the :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` callback to get the statistics result. See how to register it in :ref:`isp-callback`.
 
 .. code:: c
 
@@ -471,16 +478,16 @@ Note that if you want to use the continuous statistics, you need to register the
     esp_isp_hist_controller_enable(hist_ctlr);
 
 
-.. _isp_bf:
+.. _isp-bf:
 
-ISP BF Processor
-~~~~~~~~~~~~~~~~
+ISP BF Controller
+~~~~~~~~~~~~~~~~~
 
 This pipeline is used for doing image input denoising under bayer mode.
 
 Calling :cpp:func:`esp_isp_bf_configure` to configure BF function, you can take following code as reference.
 
-.. code:: c
+.. code-block:: c
 
     esp_isp_bf_config_t bf_config = {
         .denoising_level = 5,
@@ -496,7 +503,7 @@ Calling :cpp:func:`esp_isp_bf_configure` to configure BF function, you can take
 
 :cpp:member:`esp_isp_bf_config_t::bf_template` is used for bayer denoise. You can set the :cpp:member:`esp_isp_bf_config_t::bf_template` with a Gaussian filter template or an average filter template.
 
-After calling :cpp:func:`esp_isp_bf_configure`, you need to enable the ISP BF processor, by calling :cpp:func:`esp_isp_bf_enable`. This function:
+After calling :cpp:func:`esp_isp_bf_configure`, you need to enable the ISP BF controller, by calling :cpp:func:`esp_isp_bf_enable`. This function:
 
 * Switches the driver state from **init** to **enable**.
 
@@ -504,8 +511,8 @@ Calling :cpp:func:`esp_isp_bf_disable` does the opposite, that is, put the drive
 
 .. _isp-color:
 
-ISP Color Processor
-~~~~~~~~~~~~~~~~~~~
+ISP Color Controller
+~~~~~~~~~~~~~~~~~~~~
 
 This pipeline is used to adjust the image contrast, saturation, hue and brightness.
 
@@ -529,7 +536,7 @@ Calling :cpp:func:`esp_isp_color_configure` to configure color function, you can
     - Contrast value should be 0 ~ {IDF_TARGET_SOC_ISP_COLOR_CONTRAST_MAX}, default {IDF_TARGET_SOC_ISP_COLOR_CONTRAST_DEFAULT}
     - Saturation value should be 0 ~ {IDF_TARGET_SOC_ISP_COLOR_SATURATION_MAX}, default {IDF_TARGET_SOC_ISP_COLOR_SATURATION_DEFAULT}
     - Hue value should be 0 ~ {IDF_TARGET_SOC_ISP_COLOR_HUE_MAX}, default {IDF_TARGET_SOC_ISP_COLOR_HUE_DEFAULT}
-    - Brightness value should be -{IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_MIN} ~ {IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_MAX}, default {IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_DEFAULT}
+    - Brightness value should be {IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_MIN} ~ {IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_MAX}, default {IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_DEFAULT}
 
 .. code:: c
 
@@ -548,7 +555,7 @@ Calling :cpp:func:`esp_isp_color_configure` to configure color function, you can
     ESP_ERROR_CHECK(esp_isp_color_configure(isp_proc, &color_config));
     ESP_ERROR_CHECK(esp_isp_color_enable(isp_proc));
 
-After calling :cpp:func:`esp_isp_color_configure`, you need to enable the ISP color processor, by calling :cpp:func:`esp_isp_color_enable`. This function:
+After calling :cpp:func:`esp_isp_color_configure`, you need to enable the ISP color controller, by calling :cpp:func:`esp_isp_color_enable`. This function:
 
 * Switches the driver state from **init** to **enable**.
 
@@ -559,13 +566,11 @@ Calling :cpp:func:`esp_isp_color_disable` does the opposite, that is, put the dr
 Configure CCM
 ^^^^^^^^^^^^^
 
-Color Correction Matrix can scale the color ratio of RGB888 pixels. It can be used for adjusting the image color via some algorithms, for example, used for white balance by inputting the AWB computed result, or used as a Filter with some filter algorithms.
+Color correction matrix can scale the color ratio of RGB888 pixels. It can be used for adjusting the image color via some algorithms, for example, used for white balance by inputting the AWB computed result, or used as a filter with some filter algorithms.
 
 To adjust the color correction matrix, here is the formula:
 
-
-
-::
+.. code-block:: none
 
     [ R' ]     [ RR  RG  RB  ]   [ R ]
     [ G' ] =   [ GR  GG  GB  ] * [ G ]
@@ -597,8 +602,8 @@ To adjust the color correction matrix, here is the formula:
 
 .. _isp-demosaic:
 
-ISP Demosaic Processor
-~~~~~~~~~~~~~~~~~~~~~~
+ISP Demosaic Controller
+~~~~~~~~~~~~~~~~~~~~~~~
 
 This pipeline is used for doing image demosaic algorithm to convert RAW image to RGB mode.
 
@@ -617,7 +622,7 @@ Calling :cpp:func:`esp_isp_demosaic_configure` to configure Demosaic function, y
     ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &sharpen_config));
     ESP_ERROR_CHECK(esp_isp_demosaic_enable(isp_proc));
 
-After calling :cpp:func:`esp_isp_demosaic_configure`, you need to enable the ISP Sharpen processor, by calling :cpp:func:`esp_isp_demosaic_enable`. This function:
+After calling :cpp:func:`esp_isp_demosaic_configure`, you need to enable the ISP Demosaic controller, by calling :cpp:func:`esp_isp_demosaic_enable`. This function:
 
 * Switches the driver state from **init** to **enable**.
 
@@ -630,9 +635,9 @@ Calling :cpp:func:`esp_isp_demosaic_disable` does the opposite, that is, put the
 Enable Gamma Correction
 ^^^^^^^^^^^^^^^^^^^^^^^
 
-The human visual system is non-linearly sensitive to the physical luminance. Adding gamma correction to the ISP pipeline to transforms RGB coordinates into a space in which coordinates are proportional to subjective brightness.
+The human visual system is non-linearly sensitive to the physical luminance. Adding gamma correction to the ISP pipeline to transform RGB coordinates into a space in which coordinates are proportional to subjective brightness.
 
-The driver provides a helper API :cpp:func:`esp_isp_gamma_fill_curve_points` to fill :cpp:type:`isp_gamma_curve_points_t`, which is a group of points used to describe the gamma correction curve. Or you can manually declare the points as your desired 'gamma' correction curve. Each R / G / B component can have its own gamma correction curve, you can set the configuration by calling :cpp:func:`esp_isp_gamma_configure`.
+The driver provides a helper API :cpp:func:`esp_isp_gamma_fill_curve_points` to fill :cpp:type:`isp_gamma_curve_points_t`, which is a group of points used to describe the gamma correction curve. Or you can manually declare the points as your desired gamma correction curve. Each R/G/B component can have its own gamma correction curve, you can set the configuration by calling :cpp:func:`esp_isp_gamma_configure`.
 
 A typical code example is:
 
@@ -660,8 +665,8 @@ A typical code example is:
 
 .. _isp-sharpen:
 
-ISP Sharpen Processor
-~~~~~~~~~~~~~~~~~~~~~
+ISP Sharpen Controller
+~~~~~~~~~~~~~~~~~~~~~~
 
 This pipeline is used for doing image input sharpening under YUV mode.
 
@@ -683,7 +688,7 @@ Calling :cpp:func:`esp_isp_sharpen_configure` to configure Sharpen function, you
 
 :cpp:member:`esp_isp_sharpen_config_t::sharpen_template` is used for sharpening. You can set the :cpp:member:`esp_isp_sharpen_config_t::sharpen_template` with a Gaussian filter template or an average filter template.
 
-After calling :cpp:func:`esp_isp_sharpen_configure`, you need to enable the ISP Sharpen processor, by calling :cpp:func:`esp_isp_sharpen_enable`. This function:
+After calling :cpp:func:`esp_isp_sharpen_configure`, you need to enable the ISP Sharpen controller, by calling :cpp:func:`esp_isp_sharpen_enable`. This function:
 
 * Switches the driver state from **init** to **enable**.
 
@@ -696,19 +701,21 @@ Calling :cpp:func:`esp_isp_sharpen_disable` does the opposite, that is, put the
 
 Register Event Callbacks
 ^^^^^^^^^^^^^^^^^^^^^^^^
+
 After an ISP module starts up, it can generate a specific event dynamically.
+
 You can save your own context to callback function as well, via the parameter ``user_data``. The user data will be directly passed to the callback function.
 
 .. note::
 
-    The below mentioned callback functions are called within an ISR context, you must ensure that the functions do not attempt to block (e.g., by making sure that only FreeRTOS APIs with ``ISR`` suffix are called from within the function).
+    The below-mentioned callback functions are called within an ISR context. You must ensure that the functions do not attempt to block (e.g., by making sure that only FreeRTOS APIs with ``ISR`` suffix are called from within the function).
 
 Register ISP Processor Event Callbacks
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 After the ISP processor is enabled, it can generate multiple events of multiple ISP submodules dynamically. You can hook your functions to the interrupt service routine by calling :cpp:func:`esp_isp_register_event_callbacks`. All supported event callbacks are listed in :cpp:type:`esp_isp_evt_cbs_t`:
 
-- :cpp:member:`esp_isp_evt_cbs_t::on_sharpen_frame_done`. sets a callback function for sharpen frame done. It will be called after the ISP sharpen submodule finishes its operation for one frame. The function prototype is declared in :cpp:type:`esp_isp_sharpen_callback_t`.
+- :cpp:member:`esp_isp_evt_cbs_t::on_sharpen_frame_done` sets a callback function for sharpen frame done. It will be called after the ISP sharpen submodule finishes its operation for one frame. The function prototype is declared in :cpp:type:`esp_isp_sharpen_callback_t`.
 
 Register ISP AF Environment Detector Event Callbacks
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -723,7 +730,7 @@ Register ISP AWB Statistics Done Event Callbacks
 
 After the ISP AWB controller finished statistics of white patches, it can generate a specific event dynamically. If you want to be informed when the statistics done event takes place, please hook your function to the interrupt service routine by calling :cpp:func:`esp_isp_awb_register_event_callbacks`. All supported event callbacks are listed in :cpp:type:`esp_isp_awb_cbs_t`:
 
--  :cpp:member:`esp_isp_awb_cbs_t::on_statistics_done` sets a callback function when finished statistics of the white patches. The function prototype is declared in :cpp:type:`esp_isp_awb_callback_t`.
+-  :cpp:member:`esp_isp_awb_cbs_t::on_statistics_done` sets a callback function when finishing statistics of the white patches. The function prototype is declared in :cpp:type:`esp_isp_awb_callback_t`.
 
 
 Register ISP AE Environment Detector Event Callbacks
@@ -731,8 +738,8 @@ Register ISP AE Environment Detector Event Callbacks
 
 After the ISP AE environment detector starts up, it can generate a specific event dynamically. If you have some functions that should be called when the event happens, please hook your function to the interrupt service routine by calling :cpp:func:`esp_isp_ae_env_detector_register_event_callbacks`. All supported event callbacks are listed in :cpp:type:`esp_isp_ae_env_detector_evt_cbs_t`:
 
--  :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` sets a callback function for environment statistics done. . The function prototype is declared in :cpp:type:`esp_isp_ae_env_detector_callback_t`.
--  :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` sets a callback function for environment change. . The function prototype is declared in :cpp:type:`esp_isp_ae_env_detector_callback_t`.
+- :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` sets a callback function for environment statistics done. The function prototype is declared in :cpp:type:`esp_isp_ae_env_detector_callback_t`.
+- :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` sets a callback function for environment change. The function prototype is declared in :cpp:type:`esp_isp_ae_env_detector_callback_t`.
 
 
 Register ISP HIST Statistics Done Event Callbacks
@@ -740,14 +747,14 @@ Register ISP HIST Statistics Done Event Callbacks
 
 After the ISP HIST controller finished statistics of brightness, it can generate a specific event dynamically. If you want to be informed when the statistics done event takes place, please hook your function to the interrupt service routine by calling :cpp:func:`esp_isp_hist_register_event_callbacks`. All supported event callbacks are listed in :cpp:type:`esp_isp_hist_cbs_t`:
 
--  :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` sets a callback function when finished statistics of the brightness. . The function prototype is declared in :cpp:type:`esp_isp_hist_callback_t`.
+- :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` sets a callback function when finishing statistics of the brightness. The function prototype is declared in :cpp:type:`esp_isp_hist_callback_t`.
 
 .. _isp-thread-safety:
 
 Thread Safety
 ^^^^^^^^^^^^^
 
-The factory function
+The following factory function are guaranteed to be thread safe by the driver:
 
 .. list::
 
@@ -762,14 +769,14 @@ The factory function
     - :cpp:func:`esp_isp_new_hist_controller`
     - :cpp:func:`esp_isp_del_hist_controller`
 
-are guaranteed to be thread safe by the driver, which means, user can call them from different RTOS tasks without protection by extra locks. Other APIs are not guaranteed to be thread-safe.
+These functions can be called from different RTOS tasks without protection by extra locks. Other APIs are not guaranteed to be thread-safe.
 
 .. _isp-kconfig-options:
 
 Kconfig Options
 ^^^^^^^^^^^^^^^
 
-- :ref:`CONFIG_ISP_ISR_IRAM_SAFE` controls whether the default ISR handler should be masked when the cache is disabled
+- :ref:`CONFIG_ISP_ISR_IRAM_SAFE` controls whether the default ISR handler should be masked when the cache is disabled.
 
 .. _isp-iram-safe:
 
@@ -788,12 +795,12 @@ This allows the interrupt to run while the cache is disabled, but comes at the c
 
 Kconfig option :ref:`CONFIG_ISP_CTRL_FUNC_IN_IRAM` will:
 
-- Place some of ISP control functions into IRAM, function list:
+- Place some of the ISP control functions into IRAM, including:
 
-.. list::
+    .. list::
 
-  - :cpp:func:`esp_isp_sharpen_configure`
-  - :cpp:func:`esp_isp_demosaic_configure`
+        - :cpp:func:`esp_isp_sharpen_configure`
+        - :cpp:func:`esp_isp_demosaic_configure`
 
 Application Examples
 --------------------
@@ -804,8 +811,6 @@ API Reference
 -------------
 
 .. include-build-file:: inc/isp.inc
-.. include-build-file:: inc/components/hal/include/hal/isp_types.inc
-.. include-build-file:: inc/components/esp_driver_isp/include/driver/isp_types.inc
 .. include-build-file:: inc/isp_af.inc
 .. include-build-file:: inc/isp_ae.inc
 .. include-build-file:: inc/isp_awb.inc
@@ -816,3 +821,6 @@ API Reference
 .. include-build-file:: inc/isp_gamma.inc
 .. include-build-file:: inc/isp_hist.inc
 .. include-build-file:: inc/isp_color.inc
+.. include-build-file:: inc/isp_core.inc
+.. include-build-file:: inc/components/esp_driver_isp/include/driver/isp_types.inc
+.. include-build-file:: inc/components/hal/include/hal/isp_types.inc
diff --git a/docs/en/api-reference/peripherals/lcd/dsi_lcd.rst b/docs/en/api-reference/peripherals/lcd/dsi_lcd.rst
index 0666f2c774b..c44c288bfa0 100644
--- a/docs/en/api-reference/peripherals/lcd/dsi_lcd.rst
+++ b/docs/en/api-reference/peripherals/lcd/dsi_lcd.rst
@@ -60,7 +60,7 @@ MIPI DSI Interfaced LCD
     - :cpp:member:`esp_lcd_dpi_panel_config_t::virtual_channel` sets the virtual channel number to use. Like the DBI interface, we also need to set the virtual channel for the DPI interface. If you only have one LCD connected, you can set this to ``0``.
     - :cpp:member:`esp_lcd_dpi_panel_config_t::dpi_clk_src` sets the clock source for the DPI interface. The available clock sources are listed in :cpp:type:`mipi_dsi_dpi_clock_source_t`.
     - :cpp:member:`esp_lcd_dpi_panel_config_t::dpi_clock_freq_mhz` sets the DPI clock frequency in MHz. Higher pixel clock frequency results in higher refresh rate, but may cause flickering if the DMA bandwidth is not sufficient or the LCD controller chip does not support high pixel clock frequency.
-    - :cpp:member:`esp_lcd_dpi_panel_config_t::pixel_format` sets the pixel format of the pixel data. The available pixel formats are listed in :cpp:type:`lcd_color_rgb_pixel_format_t`. We usually use **RGB888** for MIPI LCD to get the best color depth.
+    - :cpp:member:`esp_lcd_dpi_panel_config_t::in_color_format` sets the pixel format of the input pixel data. The available pixel formats are listed in :cpp:type:`lcd_color_format_t`. We usually use **RGB888** for MIPI LCD to get the best color depth.
     - :cpp:member:`esp_lcd_dpi_panel_config_t::video_timing` sets the LCD panel specific timing parameters. All required parameters are listed in the :cpp:type:`esp_lcd_video_timing_t`, including the LCD resolution and blanking porches. Please fill them according to the datasheet of your LCD.
     - :cpp:member:`esp_lcd_dpi_panel_config_t::extra_dpi_panel_flags::use_dma2d` sets whether to use the 2D DMA peripheral to copy the user data to the frame buffer, asynchronously.
 
@@ -71,7 +71,7 @@ MIPI DSI Interfaced LCD
             .virtual_channel = 0,
             .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
             .dpi_clock_freq_mhz = 1 * 1000,
-            .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB888,
+            .in_color_format = LCD_COLOR_FMT_RGB888,
             .video_timing = {
                 .h_size = EXAMPLE_MIPI_DSI_LCD_H_RES,
                 .v_size = EXAMPLE_MIPI_DSI_LCD_V_RES,
diff --git a/docs/en/api-reference/peripherals/lcd/rgb_lcd.rst b/docs/en/api-reference/peripherals/lcd/rgb_lcd.rst
index 4d4d9ece486..b099a090b97 100644
--- a/docs/en/api-reference/peripherals/lcd/rgb_lcd.rst
+++ b/docs/en/api-reference/peripherals/lcd/rgb_lcd.rst
@@ -3,17 +3,17 @@ RGB Interfaced LCD
 
 :link_to_translation:`zh_CN:[中文]`
 
-RGB LCD panel is allocated in one step: :cpp:func:`esp_lcd_new_rgb_panel`, with various configurations specified by :cpp:type:`esp_lcd_rgb_panel_config_t`.
-
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::clk_src` selects the clock source for the RGB LCD controller. The available clock sources are listed in :cpp:type:`lcd_clock_source_t`.
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::data_width` sets number of data lines used by the RGB interface. Currently, the supported value can be 8 or 16.
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::bits_per_pixel` sets the number of bits per pixel. This is different from :cpp:member:`esp_lcd_rgb_panel_config_t::data_width`. By default, if you set this field to 0, the driver will automatically adjust the bpp to the value set in :cpp:member:`esp_lcd_rgb_panel_config_t::data_width`. But in some cases, these two values must be different. For example, a serial RGB interfaced LCD only needs ``8`` data lines, but the color width can reach to ``RGB888``, i.e., the :cpp:member:`esp_lcd_rgb_panel_config_t::bits_per_pixel` should be set to ``24``.
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::hsync_gpio_num`, :cpp:member:`esp_lcd_rgb_panel_config_t::vsync_gpio_num`, :cpp:member:`esp_lcd_rgb_panel_config_t::de_gpio_num`, :cpp:member:`esp_lcd_rgb_panel_config_t::pclk_gpio_num`, :cpp:member:`esp_lcd_rgb_panel_config_t::disp_gpio_num` and :cpp:member:`esp_lcd_rgb_panel_config_t::data_gpio_nums` are GPIO pins used by the RGB LCD controller. If any of them are not used, please set them to `-1`.
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::dma_burst_size` sets the DMA transfer burst size. The value must be a power of 2.
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::bounce_buffer_size_px` sets the size of bounce buffer. This is only necessary for a so-called "bounce buffer" mode. Please refer to :ref:`bounce_buffer_with_single_psram_frame_buffer` for more information.
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::timings` sets the LCD panel specific timing parameters. All required parameters are listed in the :cpp:type:`esp_lcd_rgb_timing_t`, including the LCD resolution and blanking porches. Please fill them according to the datasheet of your LCD.
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::fb_in_psram` sets whether to allocate the frame buffer from PSRAM or not. Please refer to :ref:`single_frame_buffer_in_psram` for more information.
-    - :cpp:member:`esp_lcd_rgb_panel_config_t::num_fbs` sets the number of frame buffers allocated by the driver. For backward compatibility, ``0`` means to allocate ``one`` frame buffer. Please use :cpp:member:`esp_lcd_rgb_panel_config_t::no_fb` if you do not want to allocate any frame buffer.
+RGB LCD panel is created by :cpp:func:`esp_lcd_new_rgb_panel`, with various configurations specified in :cpp:type:`esp_lcd_rgb_panel_config_t`.
+
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::clk_src` selects the clock source of the RGB LCD controller. The available clock sources are listed in :cpp:type:`lcd_clock_source_t`.
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::data_width` sets number of data lines consumed by the RGB interface. It can be 8/16/24.
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::bits_per_pixel` specifies the number of bits per pixel. This differs from :cpp:member:`esp_lcd_rgb_panel_config_t::data_width`. By default, if this field is set to 0, the driver will automatically match the bpp to the value set in :cpp:member:`esp_lcd_rgb_panel_config_t::data_width`. However, in some scenarios, these values need to be different. For instance, a serial RGB interfaced LCD might only require ``8`` data lines, but the color depth could be ``RGB888``, meaning :cpp:member:`esp_lcd_rgb_panel_config_t::bits_per_pixel` should be set to ``24``.
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::hsync_gpio_num`, :cpp:member:`esp_lcd_rgb_panel_config_t::vsync_gpio_num`, :cpp:member:`esp_lcd_rgb_panel_config_t::de_gpio_num`, :cpp:member:`esp_lcd_rgb_panel_config_t::pclk_gpio_num`, :cpp:member:`esp_lcd_rgb_panel_config_t::disp_gpio_num` and :cpp:member:`esp_lcd_rgb_panel_config_t::data_gpio_nums` are GPIO pins consumed by the RGB LCD controller. If any of them are not used, please set them to ``-1``.
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::dma_burst_size` specifies the size of the DMA transfer burst. Ensure this value is a power of 2.
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::bounce_buffer_size_px` specifies the size of the bounce buffer. This is required only for the "bounce buffer" mode. For more details, see :ref:`bounce_buffer_with_single_psram_frame_buffer`.
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::timings` specifies the timing parameters unique to the LCD panel. These parameters, detailed in :cpp:type:`esp_lcd_rgb_timing_t`, include the LCD resolution and blanking porches. Ensure they are set according to your LCD's datasheet.
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::fb_in_psram` determines if the frame buffer should be allocated from PSRAM. For further details, see :ref:`single_frame_buffer_in_psram`.
+    - :cpp:member:`esp_lcd_rgb_panel_config_t::num_fbs` specifies how many frame buffers the driver should allocate. For backward compatibility, setting this to ``0`` will allocate a single frame buffer. If you don't want to allocate any frame buffer, use :cpp:member:`esp_lcd_rgb_panel_config_t::no_fb` instead.
     - :cpp:member:`esp_lcd_rgb_panel_config_t::no_fb` determines whether frame buffer will be allocated. When it is set, no frame buffer will be allocated. This is also called the :ref:`bounce_buffer_only` mode.
 
 RGB LCD Frame Buffer Operation Modes
@@ -65,7 +65,7 @@ This is the default and simplest and you do not have to specify flags or bounce
 Single Frame Buffer in PSRAM
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-If you have PSRAM and want to store the frame buffer there rather than in the limited internal memory, the LCD peripheral will use EDMA to fetch frame data directly from the PSRAM, bypassing the internal cache. You can enable this feature by setting the :cpp:member:`esp_lcd_rgb_panel_config_t::fb_in_psram` to ``true``. The downside of this is that when both the CPU as well as EDMA need access to the PSRAM, the bandwidth will be **shared** between them, that is, EDMA gets half and the CPU gets the other half. If there are other peripherals using EDMA as well, with a high enough pixel clock, they may cause starvation of the LCD peripheral, resulting in display corruption. However, if the pixel clock is low enough to avoid this issue, it provides a solution with minimal CPU intervention.
+If you have PSRAM and prefer to store the frame buffer there instead of using the limited internal memory, the LCD peripheral can utilize EDMA to fetch frame data directly from PSRAM, bypassing the internal cache. This can be enabled by setting :cpp:member:`esp_lcd_rgb_panel_config_t::fb_in_psram` to ``true``. The trade-off is that when both the CPU and EDMA need access to PSRAM, the bandwidth is **shared** between them, meaning EDMA and the CPU each get half. If other peripherals are also using EDMA, a high pixel clock might cause LCD peripheral starvation, leading to display corruption. However, with a sufficiently low pixel clock, this approach minimizes CPU intervention.
 
 .. only:: esp32s3
 
@@ -112,7 +112,7 @@ If you have PSRAM and want to store the frame buffer there rather than in the li
 Double Frame Buffer in PSRAM
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-To avoid tearing effect, using two screen sized frame buffers is the easiest approach. In this mode, the frame buffer can only be allocated from PSRAM, because of the limited internal memory. The frame buffer that the CPU write to and the frame buffer that the EDMA read from are guaranteed to be different and independent. The EDMA will only switch between the two frame buffers when the previous write operation is finished and the current frame has been sent to the LCD. The downside of this mode is that, you have to maintain the synchronization between the two frame buffers.
+To prevent tearing effects, the simplest method is to use two screen-sized frame buffers. Given the limited internal memory, these buffers must be allocated from PSRAM. This ensures that the frame buffer being written to by the CPU and the one being read by the EDMA are always distinct and independent. The EDMA will only switch between the two buffers once the current write operation is complete and the frame has been fully transmitted to the LCD. The main drawback of this approach is the need to maintain synchronization between the two frame buffers.
 
 .. code:: c
 
@@ -155,15 +155,15 @@ To avoid tearing effect, using two screen sized frame buffers is the easiest app
 Bounce Buffer with Single PSRAM Frame Buffer
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-This mode allocates two so-called ``bounce buffers`` from the internal memory, and a main frame buffer that is still in PSRAM. This mode is selected by setting the :cpp:member:`esp_lcd_rgb_panel_config_t::fb_in_psram` flag and additionally specifying a non-zero :cpp:member:`esp_lcd_rgb_panel_config_t::bounce_buffer_size_px` value. The bounce buffers only need to be large enough to hold a few lines of display data, which is significantly less than the main frame buffer. The LCD peripheral uses DMA to read data from one of the bounce buffers, and meanwhile an interrupt routine uses the CPU DCache to copy data from the main PSRAM frame buffer into the other bounce buffer. Once the LCD peripheral has finished reading the bounce buffer, the two buffers change place and the CPU can fill the others. The advantage of this mode is that, you can achieve higher pixel clock frequency. As the bounce buffers are larger than the FIFOs in the EDMA path, this method is also more robust against short bandwidth spikes. The downside is a major increase in CPU use and that the LCD **CAN NOT** work if we disable the cache of the external memory, via e.g., OTA or NVS write to the main flash.
+This mode allocates two "bounce buffers" from internal memory and a main frame buffer in PSRAM. To enable this mode, set the :cpp:member:`esp_lcd_rgb_panel_config_t::fb_in_psram` flag and specify a non-zero value for :cpp:member:`esp_lcd_rgb_panel_config_t::bounce_buffer_size_px`. The bounce buffers only need to hold a few lines of display data, which is much smaller than the main frame buffer. The LCD peripheral uses DMA to read data from one bounce buffer while an interrupt routine uses the CPU DCache to copy data from the main PSRAM frame buffer into the other bounce buffer. Once the LCD peripheral finishes reading from the bounce buffer, the buffers swap roles, allowing the CPU to fill the other one. The advantage of this mode is achieving a higher pixel clock frequency. Since the bounce buffers are larger than the FIFOs in the EDMA path, this method is also more robust against short bandwidth spikes. The downside is a significant increase in CPU usage, and the LCD **CANNOT** function if the external memory cache is disabled, such as during OTA or NVS writes to the main flash.
 
 .. note::
 
-    It is highly recommended to turn on the "PSRAM XIP (Execute In Place)" feature in this mode by enabling the Kconfig options: :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` and :ref:`CONFIG_SPIRAM_RODATA`, which allows the CPU to fetch instructions and readonly data from the PSRAM instead of the main flash. What is more, the external memory cache will not be disabled even if you attempt to write to the main flash through SPI 1. This makes it possible to display an OTA progress bar for your application.
+    For optimal performance in this mode, it is highly recommended to enable the "PSRAM XIP (Execute In Place)" feature by turning on the Kconfig option: :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM`. This allows the CPU to fetch instructions and read-only data directly from PSRAM instead of the main flash. Additionally, the external memory cache remains active even when writing to the main flash via SPI 1, making it feasible to display an OTA progress bar during your application updates.
 
 .. note::
 
-    This mode still has another problem which is also caused by insufficient PSRAM bandwidth. For example, when your draw buffers are allocated from PSRAM, and their contents are copied into the internal frame buffer on CPU Core 1, on CPU Core 0, there is another memory copy happening in the DMA EOF ISR. In this situation, both CPUs are accessing the PSRAM by cache and sharing the bandwidth of the PSRAM. This increases the memory copy time that spent in the DMA EOF ISR significantly. The driver can not switch the bounce buffer in time, thus leading to a shift on the LCD screen. Although the driver can detect such a condition and perform a restart in the LCD's VSYNC interrupt handler, you still can see a flickering on the screen.
+    This mode also faces issues due to limited PSRAM bandwidth. For instance, if your draw buffers are in PSRAM and their contents are copied to the internal frame buffer by CPU Core 1, while CPU Core 0 is performing another memory copy in the DMA EOF ISR, both CPUs will be accessing PSRAM via cache, sharing its bandwidth. This significantly increases the memory copy time in the DMA EOF ISR, causing the driver to fail in switching the bounce buffer promptly, resulting in a screen shift. Although the driver can detect this condition and restart in the LCD's VSYNC interrupt handler, you may still notice flickering on the screen.
 
 .. code:: c
 
@@ -201,8 +201,6 @@ This mode allocates two so-called ``bounce buffers`` from the internal memory, a
     };
     ESP_ERROR_CHECK(esp_lcd_new_rgb_panel(&panel_config, &panel_handle));
 
-Note that this mode also allows for a :cpp:member:`esp_lcd_rgb_panel_config_t::bb_invalidate_cache` flag to be set. Enabling this frees up the cache lines after they are used to read out the frame buffer data from PSRAM, but it may lead to slight corruption if the other core writes data to the frame buffer at the exact time the cache lines are freed up. (Technically, a write to the frame buffer can be ignored if it falls between the cache writeback and the cache invalidate calls.)
-
 .. _bounce_buffer_only:
 
 Bounce Buffer Only
@@ -212,8 +210,8 @@ This mode is similar to :ref:`bounce_buffer_with_single_psram_frame_buffer`, but
 
 .. note::
 
-    In a well-designed embedded application, situations where the DMA can not deliver data as fast as the LCD consumes it should be avoided. However, such scenarios can happen in theory. In the {IDF_TARGET_NAME} hardware, this leads to the LCD simply outputting dummy bytes while DMA waits for data. If we were to run DMA in a stream fashion, a desynchronization between the LCD address for which the DMA reads the data and the LCD address for which the LCD peripheral outputs data would occur, leading to a **permanently** shifted image.
-    In order to stop this from happening, you can either enable the :ref:`CONFIG_LCD_RGB_RESTART_IN_VSYNC` option, so the driver can restart the DMA in the VBlank interrupt automatically, or call :cpp:func:`esp_lcd_rgb_panel_restart` to restart the DMA manually. Note that :cpp:func:`esp_lcd_rgb_panel_restart` does not restart the DMA immediately; instead, the DMA will be restarted in the next VSYNC event.
+    In a well-designed embedded application, situations where the DMA cannot deliver data as fast as the LCD consumes it should be avoided. However, such scenarios can theoretically occur. In the {IDF_TARGET_NAME} hardware, this results in the LCD outputting dummy bytes while the DMA waits for data. If the DMA were to run in a continuous stream, it could cause a desynchronization between the LCD address from which the DMA reads data and the address from which the LCD peripheral outputs data, leading to a **permanently** shifted image.
+    To prevent this, you can either enable the :ref:`CONFIG_LCD_RGB_RESTART_IN_VSYNC` option, allowing the driver to automatically restart the DMA during the VBlank interrupt, or call :cpp:func:`esp_lcd_rgb_panel_restart` to manually restart the DMA. Note that :cpp:func:`esp_lcd_rgb_panel_restart` does not restart the DMA immediately; instead, the DMA will be restarted at the next VSYNC event.
 
 API Reference
 -------------
diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst
index cc50f2c0d7a..8005b6b5582 100644
--- a/docs/en/api-reference/peripherals/ledc.rst
+++ b/docs/en/api-reference/peripherals/ledc.rst
@@ -88,7 +88,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
        * - RC_FAST_CLK
          - ~ 8 MHz
          - Low
-         - Dynamic Frequency Scaling compatible, Light sleep compatible
+         - Dynamic Frequency Scaling compatible, Light-sleep compatible
 
 .. only:: esp32s2
 
@@ -107,7 +107,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
          - Dynamic Frequency Scaling compatible
        * - RC_FAST_CLK
          - ~ 8 MHz
-         - Dynamic Frequency Scaling compatible, Light sleep compatible
+         - Dynamic Frequency Scaling compatible, Light-sleep compatible
        * - XTAL_CLK
          - 40 MHz
          - Dynamic Frequency Scaling compatible
@@ -126,7 +126,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
          - /
        * - RC_FAST_CLK
          - ~ 20 MHz
-         - Dynamic Frequency Scaling compatible, Light sleep compatible
+         - Dynamic Frequency Scaling compatible, Light-sleep compatible
        * - XTAL_CLK
          - 40 MHz
          - Dynamic Frequency Scaling compatible
@@ -145,7 +145,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
          - /
        * - RC_FAST_CLK
          - ~ 20 MHz
-         - Dynamic Frequency Scaling compatible, Light sleep compatible
+         - Dynamic Frequency Scaling compatible, Light-sleep compatible
        * - XTAL_CLK
          - 40/26 MHz
          - Dynamic Frequency Scaling compatible
@@ -164,7 +164,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
          - /
        * - RC_FAST_CLK
          - ~ 17.5 MHz
-         - Dynamic Frequency Scaling compatible, Light sleep compatible
+         - Dynamic Frequency Scaling compatible, Light-sleep compatible
        * - XTAL_CLK
          - 48 MHz
          - Dynamic Frequency Scaling compatible
@@ -183,7 +183,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
          - /
        * - RC_FAST_CLK
          - ~ 17.5 MHz
-         - Dynamic Frequency Scaling compatible, Light sleep compatible
+         - Dynamic Frequency Scaling compatible, Light-sleep compatible
        * - XTAL_CLK
          - 40 MHz
          - Dynamic Frequency Scaling compatible
@@ -202,7 +202,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
          - /
        * - RC_FAST_CLK
          - ~ 8 MHz
-         - Dynamic Frequency Scaling compatible, Light sleep compatible
+         - Dynamic Frequency Scaling compatible, Light-sleep compatible
        * - XTAL_CLK
          - 32 MHz
          - Dynamic Frequency Scaling compatible
@@ -337,6 +337,18 @@ When configuring an LEDC channel, one of the parameters selected within :cpp:typ
 For registration of a handler to address this interrupt, call :cpp:func:`ledc_isr_register`.
 
 
+Power Management
+----------------
+
+LEDC driver does not utilize power management lock to prevent the system from going into Light-sleep. Instead, the LEDC peripheral power domain state and the PWM signal output behavior during sleep can be chosen by configuring :cpp:member:`ledc_channel_config_t::sleep_mode`. The default mode is :cpp:enumerator:`LEDC_SLEEP_MODE_NO_ALIVE_NO_PD`, which stands for no signal output and LEDC power domain will not be powered down during sleep.
+
+If signal output needs to be maintained in Light-sleep, then select :cpp:enumerator:`LEDC_SLEEP_MODE_KEEP_ALIVE`. As long as the binded LEDC timer clock source is Light-sleep compatible, the PWM signal can continue its output even the system enters Light-sleep. The cost is a higher power consumption in sleep, since the clock source and the power domain where LEDC belongs to cannot be powered down. Note that, if there is an unfinished fade before entering sleep, the fade can also continue during sleep, but the target duty might not be reached exactly. It will adjust to the target duty after wake-up.
+
+.. only:: SOC_LEDC_SUPPORT_SLEEP_RETENTION
+
+    There is another sleep mode, :cpp:enumerator:`LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD`, can save some power consumption in sleep, but at the expense of more memory being consumed. The system retains LEDC register context before entering Light-sleep and restores them after waking up, so that the LEDC power domain can be powered down during sleep. Any unfinished fade will not resume upon waking up from sleep, instead, it will output a PWM signal with a fixed duty cycle that matches the duty cycle just before entering sleep.
+
+
 .. only:: esp32
 
     .. _ledc-api-high_low_speed_mode:
diff --git a/docs/en/api-reference/peripherals/mcpwm.rst b/docs/en/api-reference/peripherals/mcpwm.rst
index 3a6de1476e0..d6fd611d53b 100644
--- a/docs/en/api-reference/peripherals/mcpwm.rst
+++ b/docs/en/api-reference/peripherals/mcpwm.rst
@@ -122,8 +122,6 @@ You can allocate a MCPWM generator object by calling the :cpp:func:`mcpwm_new_ge
 
 - :cpp:member:`mcpwm_generator_config_t::gen_gpio_num` sets the GPIO number used by the generator.
 - :cpp:member:`mcpwm_generator_config_t::invert_pwm` sets whether to invert the PWM signal.
-- :cpp:member:`mcpwm_generator_config_t::io_loop_back` sets whether to enable the Loop-back mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral.
-- :cpp:member:`mcpwm_generator_config_t::io_od_mode` configures the PWM GPIO as open-drain output.
 - :cpp:member:`mcpwm_generator_config_t::pull_up` and :cpp:member:`mcpwm_generator_config_t::pull_down` controls whether to enable the internal pull-up and pull-down resistors accordingly.
 
 The :cpp:func:`mcpwm_new_generator` will return a pointer to the allocated generator object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there are no more free generators in the MCPWM operator, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error. [1]_
@@ -142,7 +140,6 @@ To allocate a GPIO fault object, you can call the :cpp:func:`mcpwm_new_gpio_faul
 - :cpp:member:`mcpwm_gpio_fault_config_t::gpio_num` sets the GPIO number used by the fault.
 - :cpp:member:`mcpwm_gpio_fault_config_t::active_level` sets the active level of the fault signal.
 - :cpp:member:`mcpwm_gpio_fault_config_t::pull_up` and :cpp:member:`mcpwm_gpio_fault_config_t::pull_down` set whether to pull up and/or pull down the GPIO internally.
-- :cpp:member:`mcpwm_gpio_fault_config_t::io_loop_back` sets whether to enable the loopback mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral.
 
 The :cpp:func:`mcpwm_new_gpio_fault` will return a pointer to the allocated fault object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there are no more free GPIO faults in the MCPWM group, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error. [1]_
 
@@ -163,7 +160,6 @@ To allocate a GPIO sync source, you can call the :cpp:func:`mcpwm_new_gpio_sync_
 - :cpp:member:`mcpwm_gpio_sync_src_config_t::gpio_num` sets the GPIO number used by the sync source.
 - :cpp:member:`mcpwm_gpio_sync_src_config_t::active_neg` sets whether the sync signal is active on falling edges.
 - :cpp:member:`mcpwm_gpio_sync_src_config_t::pull_up` and :cpp:member:`mcpwm_gpio_sync_src_config_t::pull_down` set whether to pull up and/or pull down the GPIO internally.
-- :cpp:member:`mcpwm_gpio_sync_src_config_t::io_loop_back` sets whether to enable the Loop-back mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral.
 
 The :cpp:func:`mcpwm_new_gpio_sync_src` will return a pointer to the allocated sync source object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there are no more free GPIO sync sources in the MCPWM group, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error. [1]_
 
@@ -207,8 +203,6 @@ Next, to allocate a capture channel, you can call the :cpp:func:`mcpwm_new_captu
 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pos_edge` and :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::neg_edge` set whether to capture on the positive and/or falling edge of the input signal.
 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pull_up` and :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pull_down` set whether to pull up and/or pull down the GPIO internally.
 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::invert_cap_signal` sets whether to invert the capture signal.
-- :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::io_loop_back` sets whether to enable the Loop-back mode. It is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral.
-- :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::keep_io_conf_at_exit` sets whether to keep the GPIO configuration when the capture channel is deleted.
 
 The :cpp:func:`mcpwm_new_capture_channel` will return a pointer to the allocated capture channel object if the allocation succeeds. Otherwise, it will return an error code. Specifically, when there is no free capture channel left in the capture timer, this function will return the :c:macro:`ESP_ERR_NOT_FOUND` error.
 
@@ -529,7 +523,7 @@ Dead time specific configuration is listed in the :cpp:type:`mcpwm_dead_time_con
         // NOTE: This is invalid, you can not apply the posedge delay to another generator
         mcpwm_generator_set_dead_time(mcpwm_gen_b, mcpwm_gen_b, &dt_config);
 
-    However, you can apply ``posedge delay`` to generator A and ``negedge delay`` to generator B. You can also set both ``posedge delay`` and ``negedge delay`` for generator A, while letting generator B bypass the dead time module.
+    However, you can apply ``posedge delay`` to generator A and ``negedge delay`` to generator B. You can also set both ``posedge delay`` and ``negedge delay`` for generator B, while letting generator A bypass the dead time module. Note that if ``negedge delay`` and ``posedge delay`` are both set for generator A, generator B will not be available. Where generator A is the first generator requested through the operator handle and generator B is the second generator requested through an operator handle.
 
 .. note::
 
@@ -982,6 +976,11 @@ However, the driver can prevent the system from going into Light-sleep by acquir
 
 Likewise, whenever the driver creates an MCPWM capture timer instance, the driver guarantees that the power management lock is acquired when enabling the timer by :cpp:func:`mcpwm_capture_timer_enable`. And releases the lock in  :cpp:func:`mcpwm_capture_timer_disable`.
 
+.. only:: SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+
+    {IDF_TARGET_NAME} supports to retain the MCPWM register context before entering **Light-sleep** and restore them after woke up. Which means you don't have to re-init the MCPWM driver after the **Light-sleep**.
+
+    This feature can be enabled by setting the flag :cpp:member:`mcpwm_timer_config_t::allow_pd` or :cpp:member:`mcpwm_capture_timer_config_t::allow_pd`. It will allow the system to power down the MCPWM in Light-sleep, meanwhile save the MCPWM register context. It can help to save more power consumption with some extra cost of the memory.
 
 .. _mcpwm-iram-safe:
 
diff --git a/docs/en/api-reference/peripherals/pcnt.rst b/docs/en/api-reference/peripherals/pcnt.rst
index 15478424fe1..3f7d9a12c08 100644
--- a/docs/en/api-reference/peripherals/pcnt.rst
+++ b/docs/en/api-reference/peripherals/pcnt.rst
@@ -226,7 +226,7 @@ This function should be called when the unit is in the init state. Otherwise, it
 
 .. note::
 
-    The glitch filter is clocked from APB. For the counter not to miss any pulses, the maximum glitch width should be longer than one APB_CLK cycle (usually 12.5 ns if APB equals 80 MHz). As the APB frequency would be changed after DFS (Dynamic Frequency Scaling) enabled, which means the filter does not work as expect in that case. So the driver installs a PM lock for PCNT unit during the first time you enable the glitch filter. For more information related to power management strategy used in PCNT driver, please see :ref:`pcnt-power-management`.
+    The glitch filter operates using the APB clock. To ensure the counter does not miss any pulses, the maximum glitch width should be longer than one APB_CLK cycle (typically 12.5 ns if APB is 80 MHz). Since the APB frequency can change with Dynamic Frequency Scaling (DFS), the filter may not function as expected in such cases. Therefore, the driver installs a power management lock for each PCNT unit. For more details on the power management strategy used in the PCNT driver, please refer to :ref:`pcnt-power-management`.
 
 .. code:: c
 
@@ -269,7 +269,7 @@ Before doing IO control to the PCNT unit, you need to enable it first, by callin
 
 * switches the PCNT driver state from **init** to **enable**.
 * enables the interrupt service if it has been lazy installed in :cpp:func:`pcnt_unit_register_event_callbacks`.
-* acquires a proper power management lock if it has been lazy installed in :cpp:func:`pcnt_unit_set_glitch_filter`. See also :ref:`pcnt-power-management` for more information.
+* acquires a proper power management lock if it has been installed. See also :ref:`pcnt-power-management` for more information.
 
 On the contrary, calling :cpp:func:`pcnt_unit_disable` will do the opposite, that is, put the PCNT driver back to the **init** state, disable the interrupts service and release the power management lock.
 
@@ -327,9 +327,9 @@ The internal hardware counter will be cleared to zero automatically when it reac
 Power Management
 ^^^^^^^^^^^^^^^^
 
-When power management is enabled (i.e., :ref:`CONFIG_PM_ENABLE` is on), the system will adjust the APB frequency before going into light sleep, thus potentially changing the behavior of PCNT glitch filter and leading to valid signal being treated as noise.
+When power management is enabled (i.e., :ref:`CONFIG_PM_ENABLE` is on), the system adjusts the APB frequency before entering light sleep, which can cause the PCNT glitch filter to misinterpret valid signals as noise.
 
-However, the driver can prevent the system from changing APB frequency by acquiring a power management lock of type :cpp:enumerator:`ESP_PM_APB_FREQ_MAX`. Whenever you enable the glitch filter by :cpp:func:`pcnt_unit_set_glitch_filter`, the driver guarantees that the power management lock is acquired after the PCNT unit is enabled by :cpp:func:`pcnt_unit_enable`. Likewise, the driver releases the lock after :cpp:func:`pcnt_unit_disable` is called.
+To prevent this, the driver can acquire a power management lock of type :cpp:enumerator:`ESP_PM_APB_FREQ_MAX`, ensuring the APB frequency remains constant. This lock is acquired when the PCNT unit is enabled via :cpp:func:`pcnt_unit_enable` and released when the unit is disabled via :cpp:func:`pcnt_unit_disable`.
 
 .. _pcnt-iram-safe:
 
diff --git a/docs/en/api-reference/peripherals/sd_pullup_requirements.rst b/docs/en/api-reference/peripherals/sd_pullup_requirements.rst
index 399d5f424ac..21e8e1e5ed9 100644
--- a/docs/en/api-reference/peripherals/sd_pullup_requirements.rst
+++ b/docs/en/api-reference/peripherals/sd_pullup_requirements.rst
@@ -1,9 +1,11 @@
 SD Pull-up Requirements
 =======================
 
+:link_to_translation:`zh_CN:[中文]`
+
 Espressif hardware products are designed for multiple use cases which may require different pull states on pins. For this reason, the pull state of particular pins on certain products needs to be adjusted to provide the pull-ups required in the SD bus.
 
-SD pull-up requirements apply to cases where {IDF_TARGET_NAME} uses the SPI or SDMMC controller to communicate with SD cards. When an SD card is operating in SPI mode or 1-bit SD mode, the CMD and DATA (DAT0 - DAT3) lines of the SD bus must be pulled up by 10 kOhm resistors. SD cards and SDIO devices should also have pull-ups on all above-mentioned lines (regardless of whether these lines are connected to the host) in order to prevent them from entering a wrong state.
+SD pull-up requirements apply to cases where {IDF_TARGET_NAME} uses the SPI or SDMMC controller to communicate with SD cards. When an SD card is operating in SPI mode or 1-bit SD mode, the CMD and DATA (DAT0 - DAT3) lines of the SD bus must be pulled up by 10 kΩ resistors. SD cards and SDIO devices should also have pull-ups on all above-mentioned lines (regardless of whether these lines are connected to the host) in order to prevent them from entering a wrong state.
 
 .. only:: esp32
 
@@ -11,13 +13,13 @@ SD pull-up requirements apply to cases where {IDF_TARGET_NAME} uses the SPI or S
 
 .. todo::
 
-   Add a diagram of the Bus lines and pullups
+   Add a diagram of the bus lines and pullups
 
 This document has the following structure:
 
-- `Overview of compatibility`_ between the default pull states on pins of Espressif's products and the states required by the SD bus
-- `Solutions`_ - ideas on how to resolve compatibility issues
-- `Related information`_ - other relevant information
+- :ref:`compatibility_overview_espressif_hw_sdio` between the default pull states on pins of Espressif's products and the states required by the SD bus
+- :ref:`sdio_solutions` - ideas on how to resolve compatibility issues
+- :ref:`related_info_sdio` - other relevant information
 
 
 .. _compatibility_overview_espressif_hw_sdio:
@@ -28,11 +30,11 @@ Overview of Compatibility
 This section provides an overview of compatibility issues that might occur when using SDIO (secure digital input output). Since the SD bus needs to be connected to pull-ups, these issues should be resolved regardless of whether they are related to master (host) or slave (device). Each issue has links to its respective solution. A solution for a host and device may differ.
 
 
-Systems on a Chip (SoCs)
-^^^^^^^^^^^^^^^^^^^^^^^^
-
 .. only:: esp32
 
+    Systems on a Chip (SoCs)
+    ^^^^^^^^^^^^^^^^^^^^^^^^
+
     - ESP32 (except for D2WD versions, see `ESP32 datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_):
 
         - :ref:`sd_pull-up_no_pull-ups`
@@ -45,33 +47,34 @@ Systems on a Chip (SoCs)
 
 .. only:: SOC_SDMMC_USE_GPIO_MATRIX
 
-    {IDF_TARGET_NAME} SDMMC host controller allows using any of GPIOs for any of SD interface signals. However, it is recommended to avoid using strapping GPIOs, GPIOs with internal weak pull-downs and GPIOs commonly used for other purposes to prevent conflicts:
+    Systems on a Chip (SoCs)
+    ^^^^^^^^^^^^^^^^^^^^^^^^
 
-.. only:: esp32s3
+    {IDF_TARGET_NAME} SDMMC host controller allows using any of GPIOs for any of SD interface signals. However, it is recommended to avoid using strapping GPIOs, GPIOs with internal weak pull-downs and GPIOs commonly used for other purposes to prevent conflicts.
 
-    - GPIO0 (strapping pin)
-    - GPIO45, GPIO46 (strapping pins, internal weak pulldown)
-    - GPIO26 - GPIO32 (commonly used for SPI Flash and PSRAM)
-    - GPIO33 - GPIO37 (when using chips and modules with Octal SPI Flash or Octal PSRAM)
-    - GPIO43, GPIO44 (GPIOs used for UART0 by default)
-    - GPIO19, GPIO20 (GPIOs used for USB by default)
+    .. only:: esp32s3
 
+        - GPIO0 (strapping pin)
+        - GPIO45, GPIO46 (strapping pins, internal weak pulldown)
+        - GPIO26 - GPIO32 (commonly used for SPI flash and PSRAM)
+        - GPIO33 - GPIO37 (when using chips and modules with octal SPI flash or octal PSRAM)
+        - GPIO43, GPIO44 (GPIOs used for UART0 by default)
+        - GPIO19, GPIO20 (GPIOs used for USB by default)
 
-Systems in Packages (SIP)
-^^^^^^^^^^^^^^^^^^^^^^^^^
 
 .. only:: esp32
 
+    Systems in Packages (SIP)
+    ^^^^^^^^^^^^^^^^^^^^^^^^^
+
     - ESP32-PICO-D4:
 
         - :ref:`sd_pull-up_no_pull-ups`
         - :ref:`strapping_conflicts_dat2`
 
 
-Modules
-^^^^^^^
-
-.. only:: esp32
+    Modules
+    ^^^^^^^
 
     - ESP32-WROOM-32 Series, including ESP32-WROOM-32, ESP32-WROOM-32D, ESP32-WROOM-32U, and ESP32-SOLO-1
 
@@ -88,12 +91,12 @@ Modules
         - :ref:`strapping_conflicts_dat2`
 
 
-.. _sdio_dev_kits:
+.. only:: esp32
 
-Development Boards
-^^^^^^^^^^^^^^^^^^
+    .. _sdio_dev_kits:
 
-.. only:: esp32
+    Development Boards
+    ^^^^^^^^^^^^^^^^^^
 
     - ESP32-PICO-KIT, including PICO-KIT v4.1, v4.0, and v3
 
@@ -132,6 +135,11 @@ Development Boards
 
 .. only:: esp32s3
 
+    .. _sdio_dev_kits:
+
+    Development Boards
+    ^^^^^^^^^^^^^^^^^^
+
     - ESP32-S3-DevKitC-1
 
         - :ref:`sd_pull-up_no_pull-ups`
@@ -154,6 +162,8 @@ Development Boards
     Please make sure that your SDIO host provides necessary pull-ups for all SD bus signals.
 
 
+.. _sdio_solutions:
+
 Solutions
 ---------
 
@@ -162,10 +172,19 @@ Solutions
 No Pull-ups
 ^^^^^^^^^^^
 
-If you use a development board without pull-ups, you can do the following:
+.. only:: esp32 or esp32s3
 
-- If your host and slave device are on separate boards, replace one of them with a board that has pull-ups. For the list of Espressif's development boards with pull-ups, go to :ref:`sdio_dev_kits`.
-- Attach external pull-ups by connecting each pin which requires a pull-up to VDD via a 10 kOhm resistor.
+    When using a development board without pull-ups:
+
+    - If your host and slave device are on separate boards, replace one of them with a board that has pull-ups. For the list of Espressif's development boards with pull-ups, go to :ref:`sdio_dev_kits`.
+    - Attach external pull-ups by connecting each pin which requires a pull-up to VDD via a 10 kΩ resistor.
+
+.. only:: not esp32 and not esp32s3
+
+    When using a development board without pull-ups:
+
+    - If your host and slave device are on separate boards, replace one of them with a board that has pull-ups.
+    - Attach external pull-ups by connecting each pin which requires a pull-up to VDD via a 10 kΩ resistor.
 
 .. only:: esp32
 
@@ -180,7 +199,7 @@ If you use a development board without pull-ups, you can do the following:
     - Use SPI mode
     - Perform one of the following actions on the GPIO13 pin:
         - Remove the pull-down resistors
-        - Attach a pull-up resistor of less than 5 kOhm (2 kOhm suggested)
+        - Attach a pull-up resistor of less than 5 kΩ (2 kΩ suggested)
         - Pull it up or drive it high either by using the host or with 3.3 V on VDD in 1-bit SD mode
 
 
@@ -219,20 +238,20 @@ If you use a development board without pull-ups, you can do the following:
         BURN
         VDD_SDIO setting complete.
 
-    To check the status of the eFuses, run::
+    To check the status of the eFuses, run:
 
-    .. code-block::
+    .. code-block:: none
 
         idf.py efuse-summary
 
-    If running from an automated flashing script, it is better to use standalone eFuse tool, ``espefuse.py``. This tool also has an option ``--do-not-confirm`` to burn eFuses without confirmation.
+    If running from an automated flashing script, it is better to use standalone eFuse tool ``espefuse.py``. This tool also has an option ``--do-not-confirm`` to burn eFuses without confirmation.
 
     For more details, see **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
 
-    2. **If using 1-bit SD mode or SPI mode**, disconnect the DAT2 pin and make sure it is pulled high. For this, do one the following:
+    2. **If using 1-bit SD mode or SPI mode**, disconnect the DAT2 pin and make sure it is pulled high. For this, you have the following options:
 
-        - Leave the host's DAT2 floating and directly connect the slave's DAT2 to VDD.
-        - For a slave device, build a firmware with the option ``SDIO_SLAVE_FLAG_DAT2_DISABLED`` and re-flash your device. This option helps avoid slave detecting on the DAT2 line. Note that 4-bit SD mode is no longer supported by the standard Card Common Control Register (CCCR); however, the host is not aware of that. The use of 4-bit SD mode has to be disabled on the host's side.
+    - Leave the host's DAT2 floating and directly connect the slave's DAT2 to VDD.
+    - For a slave device, build a firmware with the option ``SDIO_SLAVE_FLAG_DAT2_DISABLED`` and re-flash your device. This option helps avoid slave detecting on the DAT2 line. Note that 4-bit SD mode is no longer supported by the standard Card Common Control Register (CCCR); however, the host is not aware of that. The use of 4-bit SD mode has to be disabled on the host's side.
 
 
     .. _no_pull-up_on_gpio12:
@@ -240,7 +259,7 @@ If you use a development board without pull-ups, you can do the following:
     No Pull-up on GPIO12
     ^^^^^^^^^^^^^^^^^^^^
 
-    Your module is compatible with the SDIO protocol. Just connect GPIO12 to VDD via a 10 kOhm resistor.
+    Your module is compatible with the SDIO protocol. Just connect GPIO12 to VDD via a 10 kΩ resistor.
 
 
     .. _gpio2_strapping_pin:
@@ -248,25 +267,25 @@ If you use a development board without pull-ups, you can do the following:
     Download Mode Not Working (minor issue)
     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-    When the GPIO2 pin is pulled high in accordance with the SD pull-up requirements, you cannot enter Download mode because GPIO2 is a bootstrapping pin which in this case must be pulled low.
+    When the GPIO2 pin is pulled high in accordance with the SD pull-up requirements, you can not enter download mode because GPIO2 is a bootstrapping pin which in this case must be pulled low.
 
-    There are the following solutions:
+    There are following solutions:
 
-    - For boards that require shorting the GPIO0 and GPIO2 pins with a jumper, put the jumper in place, and the auto-reset circuit pulls GPIO2 low along with GPIO0 before entering Download mode.
+    - For boards that require shorting the GPIO0 and GPIO2 pins with a jumper, put the jumper in place, and the auto-reset circuit pulls GPIO2 low along with GPIO0 before entering download mode.
     - For boards with components attached to their GPIO2 pin (such as pull-down resistors and/or LEDs), check the schematic of your development board for anything connected to GPIO2.
 
         - **LEDs** would not affect operation in most cases.
         - **Pull-down resistors** can interfere with DAT0 signals and must be removed.
 
-    If the above solutions do not work for you, please determine if it is the host or slave device that has pull-ups affecting their GPIO2, then locate these pull-ups and remove them.
+    If above solutions do not work for you, please determine if it is the host or slave device that has pull-ups affecting their GPIO2, then locate these pull-ups and remove them.
 
 
-.. _related_info_sdio:
+.. only:: esp32
 
-Related Information
--------------------
+    .. _related_info_sdio:
 
-.. only:: esp32
+    Related Information
+    -------------------
 
     .. _mtdi_strapping_pin:
 
@@ -287,9 +306,9 @@ Related Information
     Internal Pull-ups and Strapping Requirements
     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-    Using external resistors is always preferable. However, Espressif's products have internal weak pull-up and pull-down resistors which can be enabled and used instead of external ones. Please keep in mind that this solution cannot guarantee reliable SDIO communication.
+    Using external resistors is always preferable. However, Espressif's products have internal weak pull-up and pull-down resistors which can be enabled and used instead of external ones. Please keep in mind that this solution can not guarantee reliable SDIO communication.
 
-    With that said, the information about these internal pull-ups and strapping requirements can still be useful. Espressif hardware products have different weak internal pull-ups/pull-downs connected to CMD and DATA pins. The table below shows the default pull-up and pull-down states of the CMD and DATA pins.
+    With that said, the information about these internal pull-ups and strapping requirements can still be useful. Espressif hardware products have different weak internal pull-ups and pull-downs connected to CMD and DATA pins. The table below shows the default pull-up and pull-down states of the CMD and DATA pins.
 
     The following abbreviations are used in the table:
 
@@ -325,3 +344,17 @@ Related Information
          - DAT3
          - WPU
          -
+
+.. only:: not esp32
+
+    .. _related_info_sdio:
+
+    Related Information
+    -------------------
+
+    Internal Pull-ups and Strapping Requirements
+    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    Using external resistors is always preferable. However, Espressif's products have internal weak pull-up and pull-down resistors which can be enabled and used instead of external ones. Please keep in mind that this solution can not guarantee reliable SDIO communication.
+
+    Generally it's not recommended to reuse strapping pins for SDIO purposes. The pullup and pulldown requirements of SD and strapping may conflict with each other. See datasheet for the strapping pins of {IDF_TARGET}.
diff --git a/docs/en/api-reference/peripherals/sdm.rst b/docs/en/api-reference/peripherals/sdm.rst
index 85edb53f73a..32dc851fe64 100644
--- a/docs/en/api-reference/peripherals/sdm.rst
+++ b/docs/en/api-reference/peripherals/sdm.rst
@@ -42,7 +42,6 @@ To install an SDM channel, you should call :cpp:func:`sdm_new_channel` to get a
 - :cpp:member:`sdm_config_t::clk_src` selects the source clock for the SDM module. Note that, all channels should select the same clock source.
 - :cpp:member:`sdm_config_t::sample_rate_hz` sets the sample rate of the SDM module. A higher sample rate can help to output signals with higher SNR (Signal to Noise Ratio), and easier to restore the original signal after the filter.
 - :cpp:member:`sdm_config_t::invert_out` sets whether to invert the output signal.
-- :cpp:member:`sdm_config_t::io_loop_back` is for debugging purposes only. It enables both the GPIO's input and output ability through the GPIO matrix peripheral.
 
 The function :cpp:func:`sdm_new_channel` can fail due to various errors such as insufficient memory, invalid arguments, etc. Specifically, when there are no more free channels (i.e., all hardware SDM channels have been used up), :c:macro:`ESP_ERR_NOT_FOUND` will be returned.
 
diff --git a/docs/en/api-reference/peripherals/sdmmc_host.rst b/docs/en/api-reference/peripherals/sdmmc_host.rst
index c7bcb9f0ae1..c37f1800524 100644
--- a/docs/en/api-reference/peripherals/sdmmc_host.rst
+++ b/docs/en/api-reference/peripherals/sdmmc_host.rst
@@ -83,14 +83,17 @@ Supported Speed Modes
 
 SDMMC Host driver supports the following speed modes:
 
-- Default Speed (20 MHz): 1-line or 4-line with SD cards, and 1-line, 4-line, or 8-line with 3.3 V eMMC
-- High Speed (40 MHz): 1-line or 4-line with SD cards, and 1-line, 4-line, or 8-line with 3.3 V eMMC
-- High Speed DDR (40 MHz): 4-line with 3.3 V eMMC
+.. list::
+
+  - Default Speed (20 MHz): 1-line or 4-line with SD cards, and 1-line, 4-line, or 8-line with 3.3 V eMMC
+  - High Speed (40 MHz): 1-line or 4-line with SD cards, and 1-line, 4-line, or 8-line with 3.3 V eMMC
+  :SOC_SDMMC_UHS_I_SUPPORTED: - UHS-I 1.8 V, SDR50 (100 MHz): 4-line with SD cards
+  :SOC_SDMMC_UHS_I_SUPPORTED: - UHS-I 1.8 V, DDR50 (50 MHz): 4-line with SD cards
+  - High Speed DDR (40 MHz): 4-line with 3.3 V eMMC
 
 Speed modes not supported at present:
 
 - High Speed DDR mode: 8-line eMMC
-- UHS-I 1.8 V modes: 4-line SD cards
 
 
 Using the SDMMC Host Driver
diff --git a/docs/en/api-reference/peripherals/spi_flash/index.rst b/docs/en/api-reference/peripherals/spi_flash/index.rst
index 9b1c4053a68..631a5a80462 100644
--- a/docs/en/api-reference/peripherals/spi_flash/index.rst
+++ b/docs/en/api-reference/peripherals/spi_flash/index.rst
@@ -116,7 +116,7 @@ Generally, try to avoid using the raw SPI flash functions to the "main" SPI flas
 SPI Flash Size
 --------------
 
-The SPI flash size is configured by writing a field in the software bootloader image header, flashed at offset 0x1000.
+The SPI flash size is configured by writing a field in the ESP-IDF second stage bootloader image header, flashed at offset 0x1000.
 
 By default, the SPI flash size is detected by ``esptool.py`` when this bootloader is written to flash, and the header is updated with the correct size. Alternatively, it is possible to generate a fixed flash size by setting :ref:`CONFIG_ESPTOOLPY_FLASHSIZE` in the project configuration.
 
diff --git a/docs/en/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst b/docs/en/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
index 7af6fb199d2..1d461737074 100644
--- a/docs/en/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
+++ b/docs/en/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
@@ -64,7 +64,7 @@ Steps For Creating Custom Chip Drivers and Overriding the ESP-IDF Default Driver
             .get_chip_caps = spi_flash_chip_eon_get_caps,
          };
 
-   - You also can see how to implement this in the example :example:`storage/custom_flash_driver`.
+   - You also can see how to implement this in the example :example:`storage/custom_flash_driver`. This example demonstrates how to override the default chip driver list.
 
 4. Write a new ``CMakeLists.txt`` file for the ``custom_chip_driver`` component, including an additional line to add a linker dependency from ``spi_flash`` to ``custom_chip_driver``::
 
@@ -80,8 +80,3 @@ Steps For Creating Custom Chip Drivers and Overriding the ESP-IDF Default Driver
 5. The ``linker.lf`` is used to put every chip driver that you are going to use whilst cache is disabled into internal RAM. See :doc:`/api-guides/linker-script-generation` for more details. Make sure this file covers all the source files that you add.
 
 6. Build your project, and you will see the new flash driver is used.
-
-Example
--------
-
-See also :example:`storage/custom_flash_driver`.
diff --git a/docs/en/api-reference/peripherals/spi_master.rst b/docs/en/api-reference/peripherals/spi_master.rst
index 71ef262c433..7932212719e 100644
--- a/docs/en/api-reference/peripherals/spi_master.rst
+++ b/docs/en/api-reference/peripherals/spi_master.rst
@@ -305,6 +305,14 @@ Bus Acquiring
 
 Sometimes you might want to send SPI transactions exclusively and continuously so that it takes as little time as possible. For this, you can use bus acquiring, which helps to suspend transactions (both polling or interrupt) to other Devices until the bus is released. To acquire and release a bus, use the functions :cpp:func:`spi_device_acquire_bus` and :cpp:func:`spi_device_release_bus`.
 
+.. only:: SOC_SPI_SUPPORT_SLEEP_RETENTION
+
+    Sleep Retention
+    ^^^^^^^^^^^^^^^
+
+    {IDF_TARGET_NAME} supports to retain the SPI register context before entering **light sleep** and restore them after waking up. This means you don't have to re-init the SPI driver after the light sleep.
+
+    This feature can be enabled by setting the flag :c:macro:`SPICOMMON_BUSFLAG_SLP_ALLOW_PD`. It will allow the system to power down the SPI in light sleep, meanwhile save the register context. It can help to save more power consumption with some extra cost of the memory.
 
 Driver Usage
 ------------
diff --git a/docs/en/api-reference/peripherals/temp_sensor.rst b/docs/en/api-reference/peripherals/temp_sensor.rst
index 22b7e1a6ce3..ca7231e6e1e 100644
--- a/docs/en/api-reference/peripherals/temp_sensor.rst
+++ b/docs/en/api-reference/peripherals/temp_sensor.rst
@@ -59,6 +59,7 @@ In order to install a built-in temperature sensor instance, the first thing is t
 
 - :cpp:member:`range_min`: The minimum value of the testing range you have evaluated.
 - :cpp:member:`range_max`: The maximum value of the testing range you have evaluated.
+- :cpp:member:`allow_pd` configures if the driver allows the system to power down the peripheral in light sleep mode. Before entering sleep, the system will backup the temperature sensor register context, which will be restored later when the system exit the sleep mode. Powering down the peripheral can save more power, but at the cost of more memory consumed to save the register context. It's a tradeoff between power consumption and memory consumption. This configuration option relies on specific hardware feature, if you enable it on an unsupported chip, you will see error message like ``not able to power down in light sleep``.
 
 After the ranges are set, the structure could be passed to :cpp:func:`temperature_sensor_install`, which will instantiate the temperature sensor instance and return a handle.
 
diff --git a/docs/en/api-reference/peripherals/touch_element.rst b/docs/en/api-reference/peripherals/touch_element.rst
index 22d1761d831..5ddae43a3b9 100644
--- a/docs/en/api-reference/peripherals/touch_element.rst
+++ b/docs/en/api-reference/peripherals/touch_element.rst
@@ -6,7 +6,11 @@ Touch Element
 Overview
 --------
 
-The Touch Element Library is a highly abstracted element library designed on the basis of the touch sensor driver. The library provides a unified and user-friendly software interface to quickly build capacitive touch sensor applications. For more information about the touch sensor driver API, see :doc:`../peripherals/touch_pad`.
+The Touch Element Library is a highly abstracted element library designed on the basis of the touch sensor driver. The library provides a unified and user-friendly software interface to quickly build capacitive touch sensor applications.
+
+.. warning::
+
+    The Touch Element Library currently is still based on the legacy touch driver. Please refer to the :doc:`new driver of Capacitive Touch Sensor </api-reference/peripherals/cap_touch_sens>` if you don't need the Touch Element Library.
 
 Architecture
 ^^^^^^^^^^^^
diff --git a/docs/en/api-reference/peripherals/touch_pad.rst b/docs/en/api-reference/peripherals/touch_pad.rst
index 1725375aa67..0cbab8545c8 100644
--- a/docs/en/api-reference/peripherals/touch_pad.rst
+++ b/docs/en/api-reference/peripherals/touch_pad.rst
@@ -5,6 +5,12 @@ Touch Sensor
 
 {IDF_TARGET_TOUCH_SENSOR_VERSION:default="v2", esp32="v1"}
 
+.. only:: esp32s2 or esp32s3
+
+    .. warning::
+
+        The touch driver in this document has been deprecated, please move to the new document for the latest touch driver: :doc:`Capacitive Touch Sensor </api-reference/peripherals/cap_touch_sens>`.
+
 Introduction
 ------------
 
@@ -146,8 +152,6 @@ Touch State Measurements
 
     It can also be used, for example, to evaluate a particular touch pad design by checking the range of sensor readings when a pad is touched or released. This information can be then used to establish a touch threshold.
 
-For the demonstration of how to read the touch pad data, check the application example :example:`peripherals/touch_sensor/touch_sensor_{IDF_TARGET_TOUCH_SENSOR_VERSION}/touch_pad_read`.
-
 Method of Measurements
 ^^^^^^^^^^^^^^^^^^^^^^
 
@@ -250,7 +254,7 @@ Touch detection is implemented in ESP32's hardware based on the user-configured
 
 Hardware touch detection can also be wired to interrupts. This is described in the next section.
 
-If measurements are noisy and capacity changes are small, hardware touch detection might be unreliable. To resolve this issue, instead of using hardware detection/provided interrupts, implement measurement filtering and perform touch detection in your own application. For sample implementation of both methods of touch detection, see :example:`peripherals/touch_sensor/touch_sensor_{IDF_TARGET_TOUCH_SENSOR_VERSION}/touch_pad_interrupt`.
+If measurements are noisy and capacity changes are small, hardware touch detection might be unreliable. To resolve this issue, instead of using hardware detection/provided interrupts, implement measurement filtering and perform touch detection in your own application.
 
 Touch Triggered Interrupts
 ^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -300,9 +304,9 @@ Application Examples
 
 .. only:: esp32s2 or esp32s3
 
-    - :example:`peripherals/touch_sensor/touch_sensor_v2/touch_pad_read` demonstrates how to read and display raw values from capacitive touch pad sensors on {IDF_TARGET_NAME}, including how to calibrate the sensors and detect touch actions.
-    - :example:`peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt` demonstrates how to set up {IDF_TARGET_NAME}'s capacitive touch pad peripheral to trigger an interrupt when a pad is touched, and how to detect the touch event by the software for sensor designs when greater touch detection sensitivity is required.
+    .. warning::
 
+        The example that uses legacy driver is removed, please see :example:`peripherals/touch_sensor/touch_sens_basic` for the usage of the new driver.
 
 .. _touch_pad-api-reference:
 
@@ -321,4 +325,4 @@ Some useful macros can be used to specified the GPIO number of a touch pad chann
 2. ``TOUCH_PAD_GPIO4_CHANNEL`` is the channel number of GPIO 4 (channel 0).
 
 .. include-build-file:: inc/touch_sensor_channel.inc
-.. include-build-file:: inc/touch_sensor_types.inc
+.. include-build-file:: inc/touch_sensor_legacy_types.inc
diff --git a/docs/en/api-reference/peripherals/twai.rst b/docs/en/api-reference/peripherals/twai.rst
index 00c90529cf4..310f9126c52 100644
--- a/docs/en/api-reference/peripherals/twai.rst
+++ b/docs/en/api-reference/peripherals/twai.rst
@@ -599,6 +599,14 @@ Application Examples
 
 **Self-Test Example:** :example:`peripherals/twai/twai_self_test` demonstrates how a node can transmit TWAI messages to itself using the TWAI driver's "No Acknowledgement" mode and Self Reception Requests, testing the proper connection of a target to a working external transceiver.
 
+.. only:: SOC_TWAI_SUPPORT_SLEEP_RETENTION
+
+    Sleep Retention
+    ^^^^^^^^^^^^^^^
+
+    {IDF_TARGET_NAME} supports to retain the TWAI register context before entering **light sleep** and restore them after waking up. This means you don't have to re-init the TWAI driver after the light sleep.
+
+    This feature can be enabled by setting the flag :cpp:member:`twai_general_config_t::sleep_allow_pd`. It will allow the system to power down the TWAI in light sleep, meanwhile saving the register context. It can help save more power consumption with some extra cost of the memory.
 
 .. ---------------------------- API Reference ----------------------------------
 
diff --git a/docs/en/api-reference/peripherals/usb_host.rst b/docs/en/api-reference/peripherals/usb_host.rst
index 27376a13f5b..1012748d859 100644
--- a/docs/en/api-reference/peripherals/usb_host.rst
+++ b/docs/en/api-reference/peripherals/usb_host.rst
@@ -34,17 +34,23 @@ The Host Library has the following features:
     - Allows multiple class drivers to run simultaneously, i.e., multiple clients of the Host Library.
     - A single device can be used by multiple clients simultaneously, e.g., composite devices.
     - The Host Library itself and the underlying Host Stack does not internally instantiate any OS tasks. The number of tasks is entirely controlled by how the Host Library interface is used. However, a general rule of thumb regarding the number of tasks is ``(the number of host class drivers running + 1)``.
+    - Allows single Hub support (If option :ref:`CONFIG_USB_HOST_HUBS_SUPPORTED` is enabled).
+    - Allows multiple Hubs support (If option :ref:`CONFIG_USB_HOST_HUB_MULTI_LEVEL` is enabled).
 
 Currently, the Host Library and the underlying Host Stack has the following limitations:
 
 .. list::
 
-    - Only supports a single device, but the Host Library's API is designed for multiple device support.
     - Only supports Asynchronous transfers.
     - Only supports using one configuration. Changing to other configurations after enumeration is not supported yet.
     - Transfer timeouts are not supported yet.
     :esp32p4: - {IDF_TARGET_NAME} contains two USB-OTG peripherals USB 2.0 OTG High-Speed and USB 2.0 OTG Full-Speed. Only the High-Speed instance is supported now.
-    :esp32p4: - {IDF_TARGET_NAME} cannot enumerate Low-Speed devices yet.
+    - The External Hub Driver: Supports only devices with the same speed as upstream port speed (e.g., Low-speed device won't work through Full-speed external Hub).
+    - The External Hub Driver: Remote Wakeup feature is not supported (External Hubs are active, even if there are no devices inserted).
+    - The External Hub Driver: Doesn't handle error cases (overcurrent handling, errors during initialization etc. are not implemented yet).
+    - The External Hub Driver: No Interface selection. The Driver uses the first available Interface with Hub Class code (09h).
+    - The External Port Driver: No downstream port debounce mechanism (not implemented yet)
+    :esp32p4: - The External Hub Driver: No Transaction Translator layer (No FS/LS Devices support when a Hub is attached to HS Host).
 
 
 .. -------------------------------------------------- Architecture -----------------------------------------------------
@@ -97,7 +103,7 @@ Therefore, in addition to the client tasks, the Host Library also requires a tas
 Devices
 ^^^^^^^
 
-The Host Library shields clients from the details of device handling, encompassing details such as connection, memory allocation, and enumeration. The clients are provided only with a list of already connected and enumerated devices to choose from. By default during enumeration, each device is automatically configured to use the first configuration found, namely, the first configuration descriptor returned on a Get Configuration Descriptor request. For most standard devices, the first configuration will have a ``bConfigurationValue`` of ``1``. If option  :ref:`CONFIG_USB_HOST_ENABLE_ENUM_FILTER_CALLBACK` is enabled, a different ``bConfigurationValue`` can be selected, see `Multiple configuration Support`_ for more details.
+The Host Library shields clients from the details of device handling, encompassing details such as connection, memory allocation, and enumeration. The clients are provided only with a list of already connected and enumerated devices to choose from. By default during enumeration, each device is automatically configured to use the first configuration found, namely, the first configuration descriptor returned on a Get Configuration Descriptor request. For most standard devices, the first configuration will have a ``bConfigurationValue`` of ``1``. If option  :ref:`CONFIG_USB_HOST_ENABLE_ENUM_FILTER_CALLBACK` is enabled, a different ``bConfigurationValue`` can be selected, see `Multiple Configuration Support`_ for more details.
 
 It is possible for two or more clients to simultaneously communicate with the same device as long as they are not communicating to the same interface. However, multiple clients can simultaneously communicate with the same device's default endpoint (i.e., EP0), which will result in their control transfers being serialized.
 
@@ -166,8 +172,8 @@ Lifecycle
 
 The graph above illustrates the typical lifecycle of the Host Library with multiple clients and devices. Specifically, the example involves:
 
-- two registered clients (Client 1 and Client 2).
-- two connected devices (Device 1 and Device 2), where Client 1 communicates with Device 1 and Client 2 communicates with Device 2.
+- Two registered clients (Client 1 and Client 2).
+- Two connected devices (Device 1 and Device 2), where Client 1 communicates with Device 1 and Client 2 communicates with Device 2.
 
 With reference to the graph above, the typical lifecycle involves the following key stages.
 
@@ -438,6 +444,44 @@ Configurable parameters of the USB host stack can be configured with multiple op
 * For reset recovery interval, refer to :ref:`CONFIG_USB_HOST_RESET_RECOVERY_MS`.
 * For ``SetAddress()`` recovery interval, refer to :ref:`CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS`.
 
+Downstream Port Configuration
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+When external Hubs feature is supported, there are several parameters which could be configured for the external Hubs port.
+
+Each external Hub has a Hub Descriptor which describes the device characteristics.
+
+.. note::
+
+    For detailed information about Hub Descriptor, please refer to `USB 2.0 Specification <https://www.usb.org/document-library/usb-20-specification>`_ > Chapter 11.23.2.1 *Hub Descriptor*.
+
+Configurable parameters of the downstream port can be configured with multiple options via Menuconfig.
+
+* For custom value to stabilize the power after powering on the port (PwrOn2PwrGood value), refer to :ref:`CONFIG_USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_MS`.
+* For reset recovery interval, refer to :ref:`CONFIG_USB_HOST_EXT_PORT_RESET_RECOVERY_DELAY_MS`.
+
+.. note::
+
+    The specification claims, that for a hub with no power switches, PwrOn2PwrGood must be set to zero. Meanwhile, for some devices, this value could be increased to give extra time for device to power-up. To enable this feature, refer to :ref:`CONFIG_USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_ENABLE`.
+
+Host Channels
+"""""""""""""
+
+When external Hubs support feature is enabled (:ref:`CONFIG_USB_HOST_HUBS_SUPPORTED`), the amount of Host channels plays important role, as each downstream device requires vacant channel.
+
+To handle each attached device, different amount of channels are required. This amount does depend on the device class (EPs number).
+
+Supported amount of channels for {IDF_TARGET_NAME} is {OTG_NUM_HOST_CHAN}.
+
+.. note::
+
+    - One free channel is required to enumerate the device.
+
+    - From 1 to N (when N - number of EPs) free channels are required to claim the interface.
+
+    - When there are no more free Host channels available, the device could not be enumerated and its interface cannot be claimed.
+
+
 Multiple Configuration Support
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/docs/en/api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst b/docs/en/api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst
new file mode 100644
index 00000000000..1dc74d90e22
--- /dev/null
+++ b/docs/en/api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst
@@ -0,0 +1,85 @@
+USB Host External Port Driver (Ext Port)
+========================================
+
+Introduction
+------------
+
+The External Port Driver (henceforth referred to as Ext Port Driver) isolates the handling process for downstream facing ports, which are provided by the Ext Hub Driver.
+
+.. note::
+
+    For more detailed information, please refer to `USB 2.0 Specification <https://www.usb.org/document-library/usb-20-specification>`_ > Chapter 11.5 **Downstream Facing Ports**.
+
+Requirements
+------------
+
+Host Stack Requirements
+^^^^^^^^^^^^^^^^^^^^^^^
+
+The Ext Port Driver takes into consideration the requirements set for the overall Host Stack (see :doc:`./usb_host_notes_design`):
+
+- The Ext Port Driver must not instantiate any tasks/threads
+- The Ext Port Driver must be event driven, providing event callbacks and an event processing function
+- The Ext Port Driver must use only API from underlying layer (The Ext Hub Driver)
+
+Implementation & Usage
+----------------------
+
+Host Stack Interaction
+^^^^^^^^^^^^^^^^^^^^^^
+
+The Ext Port Driver is a part of The Ext Hub Driver, so the interaction and hierarchical place in USB Host Stack is the same as for the Ext Hub Driver. The Ext Hub and the Ext Port Drivers were split into two Drivers to achieve the goal of logic distinguishing between external Hubs and Downstream Facing Ports handling.
+
+Ports handling
+^^^^^^^^^^^^^^^
+
+The Ext Port Driver can be installed via ``ext_port_install()`` call and uninstalled via ``ext_port_uninstall()`` call.
+
+After installation, the Ext Port Driver API could be requested via ``ext_port_get_driver()`` call.
+
+The Ext Port Driver API
+-----------------------
+
+The Ext Port Driver provides an API, which could be split into three groups: object control, device control and general.
+
+The Ext Port Driver: Object Control
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    - Create object
+    - Delete object
+
+The Ext Port Driver: Port Control
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    - Reset
+    - Disable
+    - Recycle
+    - Activate
+    - Get Speed
+    - Get status
+    - Set status
+    - Gone
+
+The Ext Port Driver: General Purpose
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    - Request processing
+
+Events & Processing
+-------------------
+
+The Ext Port Driver is completely event driven and all event handling is done via the ``ext_port_process()`` function. The ``ext_port_driver_config_t.proc_req_cb`` callback provided on the Ext Port Driver installation will be called when processing is required. Typically, ``ext_port_process()`` will be called from the Hub Driver ``hub_process()`` processing function.
+
+The Ext Port Driver exposes the following events via ``ext_port_driver_config_t.event_cb``:
+
+- ``EXT_PORT_CONNECTED`` Downstream facing port has a device connection event
+- ``EXT_PORT_RESET_COMPLETED`` Downstream facing port has a device and completed the port reset
+- ``EXT_PORT_DISCONNECTED`` Downstream facing port has a device disconnection event
+
+The Ext Port Driver ports processing is based on the Hub class-specific request ``Get Port Status``.
+
+After successful completion of the class-specific request ``Get Port Status`` and setting the new port status, the Ext Port Driver continues the port handling while it is required by ports' state and status.
+
+.. note::
+
+    For more detailed information, please refer to `USB 2.0 Specification <https://www.usb.org/document-library/usb-20-specification>`_ > Chapter 11.24.2.7 **Get Port Status**
diff --git a/docs/en/api-reference/peripherals/usb_host/usb_host_notes_index.rst b/docs/en/api-reference/peripherals/usb_host/usb_host_notes_index.rst
index 738ac7a2701..cac7338ece8 100644
--- a/docs/en/api-reference/peripherals/usb_host/usb_host_notes_index.rst
+++ b/docs/en/api-reference/peripherals/usb_host/usb_host_notes_index.rst
@@ -24,6 +24,7 @@ This document is split into the following sections:
     usb_host_notes_usbh
     usb_host_notes_enum
     usb_host_notes_ext_hub
+    usb_host_notes_ext_port
 
 Todo:
 
@@ -40,21 +41,3 @@ Introduction
 The ESP-IDF USB Host Stack allows the {IDF_TARGET_NAME} to operate as a USB Host. Operating as a USB Host allows the {IDF_TARGET_NAME} to communicate with a wide range of USB devices. However, most USB Host Stack implementations do not run on embedded hardware (i.e., runs on PCs and smartphones), thus have comparatively more resources (i.e., memory and CPU speed).
 
 The implementation of the ESP-IDF USB Host Stack (henceforth referred to as the Host Stack) takes into account the embedded nature of the {IDF_TARGET_NAME} which is reflected in various aspects of the Host Stack's design.
-
-Features & Limitations
-^^^^^^^^^^^^^^^^^^^^^^
-
-**The Host Stack currently supports the following notable features:**
-
-.. only:: esp32p4
-
-    - Supports HS (High Speed)
-
-- Supports FS (Full Speed) and LS (Low Speed) devices
-- Supports all transfer types (Control, Bulk, Isochronous, and Interrupt)
-- Automatically enumerates connected devices
-- Allows multiple class drivers (i.e., Clients of the USB Host Library) to run simultaneously and share the same device (i.e., composite devices)
-
-**The Host Stack currently has the following notable limitations:**
-
-- No Hub support (currently only supports a single device)
diff --git a/docs/en/api-reference/protocols/esp_http_server.rst b/docs/en/api-reference/protocols/esp_http_server.rst
index 0e79769feeb..7324cd3a1d4 100644
--- a/docs/en/api-reference/protocols/esp_http_server.rst
+++ b/docs/en/api-reference/protocols/esp_http_server.rst
@@ -10,109 +10,14 @@ The HTTP Server component provides an ability for running a lightweight web serv
 
     * :cpp:func:`httpd_start`: Creates an instance of HTTP server, allocate memory/resources for it depending upon the specified configuration and outputs a handle to the server instance. The server has both, a listening socket (TCP) for HTTP traffic, and a control socket (UDP) for control signals, which are selected in a round robin fashion in the server task loop. The task priority and stack size are configurable during server instance creation by passing ``httpd_config_t`` structure to ``httpd_start()``. TCP traffic is parsed as HTTP requests and, depending on the requested URI, user registered handlers are invoked which are supposed to send back HTTP response packets.
     * :cpp:func:`httpd_stop`: This stops the server with the provided handle and frees up any associated memory/resources. This is a blocking function that first signals a halt to the server task and then waits for the task to terminate. While stopping, the task closes all open connections, removes registered URI handlers and resets all session context data to empty.
-    * :cpp:func:`httpd_register_uri_handler`: A URI handler is registered by passing object of type ``httpd_uri_t`` structure which has members including ``uri`` name, ``method`` type (eg. ``HTTPD_GET/HTTPD_POST/HTTPD_PUT`` etc.), function pointer of type ``esp_err_t *handler (httpd_req_t *req)`` and ``user_ctx`` pointer to user context data.
+    * :cpp:func:`httpd_register_uri_handler`: A URI handler is registered by passing object of type ``httpd_uri_t`` structure which has members including ``uri`` name, ``method`` type (eg. ``HTTP_GET/HTTP_POST/HTTP_PUT`` etc.), function pointer of type ``esp_err_t *handler (httpd_req_t *req)`` and ``user_ctx`` pointer to user context data.
 
 Application Examples
 --------------------
 
-    .. code-block:: c
-
-        /* Our URI handler function to be called during GET /uri request */
-        esp_err_t get_handler(httpd_req_t *req)
-        {
-            /* Send a simple response */
-            const char resp[] = "URI GET Response";
-            httpd_resp_send(req, resp, HTTPD_RESP_USE_STRLEN);
-            return ESP_OK;
-        }
-
-        /* Our URI handler function to be called during POST /uri request */
-        esp_err_t post_handler(httpd_req_t *req)
-        {
-            /* Destination buffer for content of HTTP POST request.
-             * httpd_req_recv() accepts char* only, but content could
-             * as well be any binary data (needs type casting).
-             * In case of string data, null termination will be absent, and
-             * content length would give length of string */
-            char content[100];
-
-            /* Truncate if content length larger than the buffer */
-            size_t recv_size = MIN(req->content_len, sizeof(content));
-
-            int ret = httpd_req_recv(req, content, recv_size);
-            if (ret <= 0) {  /* 0 return value indicates connection closed */
-                /* Check if timeout occurred */
-                if (ret == HTTPD_SOCK_ERR_TIMEOUT) {
-                    /* In case of timeout one can choose to retry calling
-                     * httpd_req_recv(), but to keep it simple, here we
-                     * respond with an HTTP 408 (Request Timeout) error */
-                    httpd_resp_send_408(req);
-                }
-                /* In case of error, returning ESP_FAIL will
-                 * ensure that the underlying socket is closed */
-                return ESP_FAIL;
-            }
-
-            /* Send a simple response */
-            const char resp[] = "URI POST Response";
-            httpd_resp_send(req, resp, HTTPD_RESP_USE_STRLEN);
-            return ESP_OK;
-        }
-
-        /* URI handler structure for GET /uri */
-        httpd_uri_t uri_get = {
-            .uri      = "/uri",
-            .method   = HTTP_GET,
-            .handler  = get_handler,
-            .user_ctx = NULL
-        };
-
-        /* URI handler structure for POST /uri */
-        httpd_uri_t uri_post = {
-            .uri      = "/uri",
-            .method   = HTTP_POST,
-            .handler  = post_handler,
-            .user_ctx = NULL
-        };
-
-        /* Function for starting the webserver */
-        httpd_handle_t start_webserver(void)
-        {
-            /* Generate default configuration */
-            httpd_config_t config = HTTPD_DEFAULT_CONFIG();
-
-            /* Empty handle to esp_http_server */
-            httpd_handle_t server = NULL;
-
-            /* Start the httpd server */
-            if (httpd_start(&server, &config) == ESP_OK) {
-                /* Register URI handlers */
-                httpd_register_uri_handler(server, &uri_get);
-                httpd_register_uri_handler(server, &uri_post);
-            }
-            /* If server failed to start, handle will be NULL */
-            return server;
-        }
-
-        /* Function for stopping the webserver */
-        void stop_webserver(httpd_handle_t server)
-        {
-            if (server) {
-                /* Stop the httpd server */
-                httpd_stop(server);
-            }
-        }
-
-Simple HTTP Server Example
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-:example:`protocols/http_server/simple` demonstrates how to handle arbitrary content lengths, read request headers and URL query parameters, and set response headers.
-
-Advanced Testing Example
-^^^^^^^^^^^^^^^^^^^^^^^^
-
-:example:`protocols/http_server/advanced_tests` demonstrates how to use the HTTP server for advanced testing.
+- :example:`protocols/http_server/simple` demonstrates how to handle arbitrary content lengths, read request headers and URL query parameters, and set response headers.
 
+- :example:`protocols/http_server/advanced_tests` demonstrates how to use the HTTP server for advanced testing.
 
 Persistent Connections
 ----------------------
diff --git a/docs/en/api-reference/protocols/esp_serial_slave_link.rst b/docs/en/api-reference/protocols/esp_serial_slave_link.rst
index af35ba5ed08..b3ab831180a 100644
--- a/docs/en/api-reference/protocols/esp_serial_slave_link.rst
+++ b/docs/en/api-reference/protocols/esp_serial_slave_link.rst
@@ -91,7 +91,7 @@ ESP SDIO Slave
 
 The ESP SDIO slave link (ESSL SDIO) devices relies on the SDMMC component. It includes the usage of communicating with ESP SDIO Slave device via the SDMMC Host or SDSPI Host feature. The ESSL device should be initialized as below:
 
-1. Initialize a SDMMC card (see :doc:` Document of SDMMC driver </api-reference/storage/sdmmc>`) structure.
+1. Initialize a SDMMC card (see :doc:`Document of SDMMC driver </api-reference/storage/sdmmc>`) structure.
 
 2. Call :cpp:func:`sdmmc_card_init` to initialize the card.
 
diff --git a/docs/en/api-reference/protocols/icmp_echo.rst b/docs/en/api-reference/protocols/icmp_echo.rst
index 929211088b4..5aa1451133a 100644
--- a/docs/en/api-reference/protocols/icmp_echo.rst
+++ b/docs/en/api-reference/protocols/icmp_echo.rst
@@ -109,10 +109,10 @@ Get Runtime Statistics
 As the example code above, you can call ``esp_ping_get_profile`` to get different runtime statistics of ping session in the callback function.
 
 
-Application Example
--------------------
+Application Examples
+--------------------
 
-ICMP echo example: :example:`protocols/icmp_echo`
+- :example:`protocols/icmp_echo` demonstrates how to implement a simple ping command line utility to test if a remote host is reachable on the IP network, using ICMP echo request packets.
 
 API Reference
 -------------
diff --git a/docs/en/api-reference/protocols/mbedtls.rst b/docs/en/api-reference/protocols/mbedtls.rst
index cc636fd033c..b02fd595d7c 100644
--- a/docs/en/api-reference/protocols/mbedtls.rst
+++ b/docs/en/api-reference/protocols/mbedtls.rst
@@ -118,5 +118,5 @@ Reducing Binary Size
 Under ``Component Config -> mbedTLS``, there are multiple Mbed TLS features which are enabled by default but can be disabled if not needed to save code size. More information can be about this can be found in :ref:`Minimizing Binary Size <minimizing_binary_mbedtls>` docs.
 
 
-.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.1/
+.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.2/
 .. _`Knowledge Base`: https://mbed-tls.readthedocs.io/en/latest/kb/
diff --git a/docs/en/api-reference/protocols/modbus.rst b/docs/en/api-reference/protocols/modbus.rst
index c74978e2f24..434ce786750 100644
--- a/docs/en/api-reference/protocols/modbus.rst
+++ b/docs/en/api-reference/protocols/modbus.rst
@@ -1,5 +1,6 @@
 ESP-Modbus
 ==========
+
 :link_to_translation:`zh_CN:[中文]`
 
 The Espressif ESP-Modbus Library (esp-modbus) supports Modbus communication in the networks based on RS485, Wi-Fi, and Ethernet interfaces.
@@ -14,15 +15,18 @@ The documentation can be found through the link below:
 
 * `ESP-Modbus documentation (English) <https://docs.espressif.com/projects/esp-modbus>`__
 
-Application Example
--------------------
+Application Examples
+--------------------
 
 The examples below demonstrate the ESP-Modbus library of serial and TCP ports for both slave and master implementations respectively.
 
-- :example:`protocols/modbus/serial/mb_slave`
-- :example:`protocols/modbus/serial/mb_master`
-- :example:`protocols/modbus/tcp/mb_tcp_slave`
-- :example:`protocols/modbus/tcp/mb_tcp_master`
+- :example:`protocols/modbus/serial/mb_slave` demonstrates how to use {IDF_TARGET_NAME} as a Modbus serial slave device with the esp-modbus stack, enabling an external Modbus host to read and write device parameters using the Modbus protocol.
+
+- :example:`protocols/modbus/serial/mb_master` demonstrates how to use the esp-modbus stack port on {IDF_TARGET_NAME} as a Modbus serial master device, capable of reading and writing values from slave devices in a Modbus segment.
+
+- :example:`protocols/modbus/tcp/mb_tcp_slave` demonstrates the esp-modbus TCP slave stack port, allowing an external Modbus host to read and write device parameters via the Modbus protocol.
+
+- :example:`protocols/modbus/tcp/mb_tcp_master` demonstrates how to use the esp-modbus stack port on {IDF_TARGET_NAME} as a Modbus TCP master device, capable of reading and writing values from slave devices in a Modbus network.
 
 Please refer to the ``README.md`` documents of each specific example for details.
 
@@ -30,5 +34,3 @@ Protocol References
 -------------------
 
     - For the detailed protocol specifications, see `The Modbus Organization <https://modbus.org/specs.php>`_.
-
-
diff --git a/docs/en/api-reference/protocols/mqtt.rst b/docs/en/api-reference/protocols/mqtt.rst
index 7c5899de56c..b408c3bc2d8 100644
--- a/docs/en/api-reference/protocols/mqtt.rst
+++ b/docs/en/api-reference/protocols/mqtt.rst
@@ -19,16 +19,25 @@ Features
 
 
 Application Examples
----------------------
-
-   * :example:`protocols/mqtt/tcp`: MQTT over TCP, default port 1883
-   * :example:`protocols/mqtt/ssl`: MQTT over TLS, default port 8883
-   * :example:`protocols/mqtt/ssl_ds`: MQTT over TLS using digital signature peripheral for authentication, default port 8883
-   * :example:`protocols/mqtt/ssl_mutual_auth`: MQTT over TLS using certificates for authentication, default port 8883
-   * :example:`protocols/mqtt/ssl_psk`: MQTT over TLS using pre-shared keys for authentication, default port 8883
-   * :example:`protocols/mqtt/ws`: MQTT over WebSocket, default port 80
-   * :example:`protocols/mqtt/wss`: MQTT over WebSocket Secure, default port 443
-   * :example:`protocols/mqtt5`: Uses ESP-MQTT library to connect to broker with MQTT v5.0
+--------------------
+
+   - :example:`protocols/mqtt/tcp` demonstrates how to implement MQTT communication over TCP (default port 1883).
+
+   - :example:`protocols/mqtt/ssl` demonstrates how to use SSL transport to implement MQTT communication over TLS (default port 8883).
+
+   - :example:`protocols/mqtt/ssl_ds` demonstrates how to use digital signature peripheral for authentication to implement MQTT communication over TLS (default port 8883).
+
+   - :example:`protocols/mqtt/ssl_mutual_auth` demonstrates how to use certificates for authentication to implement MQTT communication (default port 8883).
+
+   - :example:`protocols/mqtt/ssl_psk` demonstrates how to use pre-shared keys for authentication to implement MQTT communication over TLS (default port 8883).
+
+   - :example:`protocols/mqtt/ws` demonstrates how to implement MQTT communication over WebSocket (default port 80).
+
+   - :example:`protocols/mqtt/wss` demonstrates how to implement MQTT communication over WebSocket Secure (default port 443).
+
+   - :example:`protocols/mqtt5` demonstrates how to use ESP-MQTT library to connect to broker with MQTT v5.0.
+
+   - :example:`protocols/mqtt/custom_outbox` demonstrates how to customize the outbox in the ESP-MQTT library.
 
 MQTT Message Retransmission
 ---------------------------
diff --git a/docs/en/api-reference/storage/fatfs.rst b/docs/en/api-reference/storage/fatfs.rst
index f45007607ce..8a3f2b3d0c5 100644
--- a/docs/en/api-reference/storage/fatfs.rst
+++ b/docs/en/api-reference/storage/fatfs.rst
@@ -123,7 +123,7 @@ If you decide for any reason to use ``fatfs_create_rawflash_image`` (without wea
 
 The arguments of the function are as follows:
 
-#. partition - the name of the partition as defined in the partition table (e.g., :example_file:`storage/fatfsgen/partitions_example.csv`).
+#. partition - the name of the partition as defined in the partition table (e.g., :example_file:`storage/fatfs/fatfsgen/partitions_example.csv`).
 
 #. base_dir - the directory that will be encoded to FatFs partition and optionally flashed into the device. Beware that you have to specify the suitable size of the partition in the partition table.
 
@@ -139,7 +139,7 @@ For example::
 
 If FLASH_IN_PROJECT is not specified, the image will still be generated, but you will have to flash it manually using ``esptool.py`` or a custom build system target.
 
-For an example, see :example:`storage/fatfsgen`.
+For an example, see :example:`storage/fatfs/fatfsgen`.
 
 
 .. _fatfs-partition-analyzer:
@@ -157,6 +157,40 @@ Usage::
 
 Parameter --verbose prints detailed information from boot sector of the FatFs image to the terminal before folder structure is generated.
 
+FATFS Minimum Partition Size and Limits
+---------------------------------------
+
+The FATFS component supports FAT12, FAT16, and FAT32 file system types. The file system type is determined by the number of clusters (calculated as data sectors divided by sectors per cluster) on the volume. The minimum partition size is defined by the number of sectors allocated to FAT tables, root directories and data clusters.
+
+* The minimum supported size for a FAT partition with wear leveling enabled is 32 KB for a sector size of 4096 bytes. For a sector size of 512 bytes, the minimum partition size varies based on the WL configuration: 20 KB for Performance mode and 28 KB for Safety mode (requiring 2 extra sectors).
+* For a partition with wear leveling enabled, 4 sectors will be reserved for wear-leveling operations, and 4 sectors will be used by the FATFS (1 reserved sector, 1 FAT sector, 1 root directory sector and 1 data sector).
+* Increasing the partition size will allocate additional data sectors, allowing for more storage space.
+* For partition sizes less than 528 KB, 1 root directory sector will be allocated; for larger partitions, 4 root directory sectors will be used.
+* By default, two FAT sectors are created, increasing the partition size by one sector to accommodate the extra FAT sector. To enable a single FAT sector, configure the `use_one_fat` option in `struct esp_vfs_fat_mount_config_t` (see :component_file:`fatfs/vfs/esp_vfs_fat.h`). Enabling this option allows the minimum partition size to be reduced to 32 KB.
+* The general formula for calculating the partition size for a wear-leveled partition is::
+
+    partition_size = Wear-levelling sectors * FLASH_SEC_SIZE + FATFS partition sectors * FAT_SEC_SIZE
+
+  Where:
+
+  - Wear-leveling sectors are fixed at 4
+  - FLASH_SEC_SIZE is 4096 bytes
+  - FATFS partition sectors include: 1 reserved sector + FAT sectors + root directory sectors + data sectors
+  - FAT_SEC_SIZE can be either 512 bytes or 4096 bytes, depending on the configuration
+
+* For read-only partitions without wear leveling enabled and a sector size of 512 bytes, the minimum partition size can be reduced to as low as 2 KB.
+
+Please refer :doc:`File System Considerations <../../api-guides/file-system-considerations>` for further details.
+
+Application Examples
+--------------------
+
+- :example:`storage/fatfs/getting_started` demonstrates the minimal setup required to store persistent data on SPI flash using the FatFS, including mounting the file system, opening a file, performing basic read and write operations, and unmounting the file system.
+
+- :example:`storage/fatfs/fs_operations` demonstrates more advanced FatFS operations, including reading and writing files, creating, moving, and deleting files and directories, and inspecting file details.
+
+- :example:`storage/fatfs/ext_flash` demonstrates how to operate an external SPI flash formatted with FatFS, including initializing the SPI bus, configuring the flash chip, registering it as a partition, and performing read and write operations.
+
 High-level API Reference
 ------------------------
 
diff --git a/docs/en/api-reference/storage/fatfsgen.rst b/docs/en/api-reference/storage/fatfsgen.rst
index 0d6218e9607..4bbbd1e2ebc 100644
--- a/docs/en/api-reference/storage/fatfsgen.rst
+++ b/docs/en/api-reference/storage/fatfsgen.rst
@@ -219,3 +219,8 @@ Date and Time in FAT File System
 The FAT file system protocol used by ESP-IDF does not preserve the date or time on the chips' media, so all the images extracted from the device have the same default timestamp for all the FAT-specified date-time fields (creation and the last modification timestamp as well as creation, last modification and last access dates).
 
 There are a couple of fields in the SFN entry describing time, such as **DIR_CrtTime** and **DIR_WrtTime**. Some fields are ignored by the FAT implementation used by ESP-IDF (see the file ``entry.py``). However, changes in the fields **DIR_WrtTime** and **DIR_WrtDate** are preserved in the chip. Both time and data entry are 16-bit, where the granularity of the time is 2 seconds.
+
+Application Examples
+--------------------
+
+- :example:`storage/fatfs/fatfsgen` demonstrates how to use the FatFS partition generation tool to automatically create a FatFS image from a host folder during the building process.
diff --git a/docs/en/api-reference/storage/index.rst b/docs/en/api-reference/storage/index.rst
index 19bf5b6b929..f3f184270f2 100644
--- a/docs/en/api-reference/storage/index.rst
+++ b/docs/en/api-reference/storage/index.rst
@@ -37,22 +37,15 @@ For information about storage security, please refer to :doc:`Storage Security <
     wear-levelling
     storage-security.rst
 
-.. list-table:: Code Examples for Storage API
+Examples
+--------
+
+.. list-table:: NVS API examples
     :widths: 25 75
     :header-rows: 0
 
     * - **Code Example**
       - **Description**
-    * - :doc:`fatfs`
-      -
-    * - :example:`wear_leveling <storage/wear_levelling>`
-      - Demonstrates using FATFS over wear leveling on internal flash.
-    * - :example:`ext_flash_fatfs <storage/ext_flash_fatfs>`
-      - Demonstrates using FATFS over wear leveling on external flash.
-    * - :example:`fatfsgen <storage/fatfsgen>`
-      - Demonstrates the capabilities of Python-based tooling for FATFS images available on host computers.
-    * - :doc:`nvs_flash`
-      -
     * - :example:`nvs_rw_blob <storage/nvs_rw_blob>`
       - Shows the use of the C-style API to read and write blob data types in NVS flash.
     * - :example:`nvs_rw_value <storage/nvs_rw_value>`
@@ -61,20 +54,59 @@ For information about storage security, please refer to :doc:`Storage Security <
       - Shows the use of the C++-style API to read and write integer data types in NVS flash.
     * - :example:`nvsgen <storage/nvsgen>`
       - Demonstrates how to use the Python-based NVS image generation tool to create an NVS partition image from the contents of a CSV file.
-    * - :doc:`spiffs`
-      -
+
+.. list-table:: Common Filesystem API
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **Code Example**
+      - **Description**
+    * - :example:`fatfs/getting_started <storage/fatfs/getting_started>`
+      - Demonstrates basic common file API (stdio.h) usage over internal flash using FATFS.
+    * - :example:`fatfs/fs_operations <storage/fatfs/fs_operations>`
+      - Demonstrates POSIX API for filesystem manipulation, such as moving, removing and renaming files.
+
+.. list-table:: FATFS API examples
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **Code Example**
+      - **Description**
+    * - :example:`fatfsgen <storage/fatfs/fatfsgen>`
+      - Demonstrates the capabilities of Python-based tooling for FATFS images available on host computers.
+    * - :example:`ext_flash_fatfs <storage/fatfs/ext_flash>`
+      - Demonstrates using FATFS over wear leveling on external flash.
+    * - :example:`wear_leveling <storage/wear_levelling>`
+      - Demonstrates using FATFS over wear leveling on internal flash.
+
+.. list-table:: SPIFFS API examples
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **Code Example**
+      - **Description**
     * - :example:`spiffs <storage/spiffs>`
       - Shows the use of the SPIFFS API to initialize the filesystem and work with files using POSIX functions.
     * - :example:`spiffsgen <storage/spiffsgen>`
       - Demonstrates the capabilities of Python-based tooling for SPIFFS images available on host computers.
-    * - :doc:`partition`
-      -
+
+.. list-table:: Partition API examples
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **Code Example**
+      - **Description**
     * - :example:`partition_api <storage/partition_api>`
       - Provides an overview of API functions to look up particular partitions, perform basic I/O operations, and use partitions via CPU memory mapping.
     * - :example:`parttool <storage/parttool>`
       - Demonstrates the capabilities of Python-based tooling for partition images available on host computers.
-    * - :doc:`vfs`
-      -
+
+.. list-table:: VFS related examples
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **Code Example**
+      - **Description**
     * - :example:`littlefs <storage/littlefs>`
       - Shows the use of the LittleFS component to initialize the filesystem and work with a file using POSIX functions.
     * - :example:`semihost_vfs <storage/semihost_vfs>`
diff --git a/docs/en/api-reference/storage/partition.rst b/docs/en/api-reference/storage/partition.rst
index 173f5e08b65..9a38235e865 100644
--- a/docs/en/api-reference/storage/partition.rst
+++ b/docs/en/api-reference/storage/partition.rst
@@ -24,6 +24,16 @@ This component provides API functions to enumerate partitions found in the parti
 - :cpp:func:`esp_partition_find_first` is a convenience function which returns the structure describing the first partition found by :cpp:func:`esp_partition_find`.
 - :cpp:func:`esp_partition_read`, :cpp:func:`esp_partition_write`, :cpp:func:`esp_partition_erase_range` are equivalent to :cpp:func:`esp_flash_read`, :cpp:func:`esp_flash_write`, :cpp:func:`esp_flash_erase_region`, but operate within partition boundaries.
 
+Application Examples
+--------------------
+
+- :example:`storage/partition_api/partition_ops` demonstrates how to perform read, write, and erase operations on a partition table.
+
+- :example:`storage/parttool` demonstrates how to use the partitions tool to perform operations such as reading, writing, erasing partitions, retrieving partition information, and dumping the entire partition table.
+
+- :example:`storage/partition_api/partition_find` demonstrates how to search the partition table and return matching partitions based on set constraints such as partition type, subtype, and label/name.
+
+- :example:`storage/partition_api/partition_mmap` demonstrates how to configure the MMU, map a partition into memory address space for read operations, and verify the data written and read.
 
 See Also
 --------
diff --git a/docs/en/api-reference/storage/sdmmc.rst b/docs/en/api-reference/storage/sdmmc.rst
index ec00684ecaf..f90ba43625f 100644
--- a/docs/en/api-reference/storage/sdmmc.rst
+++ b/docs/en/api-reference/storage/sdmmc.rst
@@ -29,10 +29,16 @@ Host layer driver(s) implement the protocol layer driver by supporting these fun
     :align: center
 
 
-Application Example
--------------------
+Application Examples
+--------------------
 
-An example which combines the SDMMC driver with the FATFS library is provided in the :example:`storage/sd_card` directory of ESP-IDF examples. This example initializes the card, then writes and reads data from it using POSIX and C library APIs. See README.md file in the example directory for more information.
+.. list::
+
+    :SOC_SDMMC_HOST_SUPPORTED: - :example:`storage/sd_card/sdmmc` demonstrates how to operate an SD card formatted with the FatFS file system via the SDMMC interface.
+
+    :SOC_SDMMC_HOST_SUPPORTED: - :example:`storage/emmc` demonstrates how to operate an eMMC chip formatted with the FatFS file system via the SDMMC interface.
+
+    :SOC_GPSPI_SUPPORTED: - :example:`storage/sd_card/sdspi` demonstrates how to operate an SD card formatted with the FatFS file system via the SPI interface.
 
 Protocol Layer API
 ------------------
diff --git a/docs/en/api-reference/storage/spiffs.rst b/docs/en/api-reference/storage/spiffs.rst
index 2104ce9dc04..28ab0704556 100644
--- a/docs/en/api-reference/storage/spiffs.rst
+++ b/docs/en/api-reference/storage/spiffs.rst
@@ -65,7 +65,7 @@ There are cases where the contents of the base directory itself is generated at
 
     spiffs_create_partition_image(my_spiffs_partition my_folder DEPENDS dep)
 
-For an example, see :example:`storage/spiffsgen`.
+For an example, see :example:`storage/spiffsgen`. This example demonstrates how to use the SPIFFS image generation tool to automatically create an SPIFFS image from a host folder during building.
 
 ``mkspiffs``
 ^^^^^^^^^^^^
diff --git a/docs/en/api-reference/storage/vfs.rst b/docs/en/api-reference/storage/vfs.rst
index 44b13075463..b8e4bd3c753 100644
--- a/docs/en/api-reference/storage/vfs.rst
+++ b/docs/en/api-reference/storage/vfs.rst
@@ -44,7 +44,7 @@ Case 1: API functions are declared without an extra context pointer (the FS driv
         .write = &myfs_write,
     // ... other members initialized
 
-    // When registering FS, context pointer (third argument) is NULL:
+    // When registering FS, context pointer (the third argument) is NULL:
     ESP_ERROR_CHECK(esp_vfs_register("/data", &myfs, NULL));
 
 Case 2: API functions are declared with an extra context pointer (the FS driver supports multiple instances)::
@@ -141,7 +141,9 @@ A socket VFS driver needs to be registered with the following functions defined:
 Please see :component_file:`lwip/port/esp32xx/vfs_lwip.c` for a reference socket driver implementation using LWIP.
 
 .. note::
+
     If you use :cpp:func:`select` for socket file descriptors only then you can disable the :ref:`CONFIG_VFS_SUPPORT_SELECT` option to reduce the code size and improve performance.
+
     You should not change the socket driver during an active :cpp:func:`select` call or you might experience some undefined behavior.
 
 Paths
@@ -192,6 +194,17 @@ Standard I/O streams (``stdin``, ``stdout``, ``stderr``) are mapped to file desc
 
 Note that creating an eventfd with ``EFD_SUPPORT_ISR`` will cause interrupts to be temporarily disabled when reading, writing the file and during the beginning and the ending of the ``select()`` when this file is set.
 
+
+Minified VFS
+------------
+
+To minimize RAM usage, an alternative version of :cpp:func:`esp_vfs_register` function, :cpp:func:`esp_vfs_register_fs` is provided. This version accepts :cpp:class:`esp_vfs_fs_ops_t` instead of :cpp:class:`esp_vfs_t` alongside separate argument for OR-ed flags. Unlike :cpp:func:`esp_vfs_register`, it can handle statically allocated struct, as long as the ``ESP_VFS_FLAG_STATIC`` is provided.
+
+The :cpp:class:`esp_vfs_fs_ops_t` is split into separate structs based on features (directory operations, select support, termios support, ...). The main struct contains the basic functions (``read``, ``write``, ...), alongside pointers to the feature-specific structs. These pointers can be ``NULL`` indicating lack of support for all the functions provided by that struct, which decreases the required memory.
+
+Internally the VFS component uses this version of API, with additional steps to convert the :cpp:class:`esp_vfs_t` to :cpp:class:`esp_vfs_fs_ops_t` upon registration.
+
+
 Well Known VFS Devices
 ----------------------
 
@@ -208,11 +221,15 @@ Application Examples
 
 - :example:`system/select` demonstrates how to use synchronous I/O multiplexing with the ``select()`` function, using UART and socket file descriptors, and configuring both to act as loopbacks to receive messages sent from other tasks.
 
+- :example:`storage/semihost_vfs` demonstrates how to use the semihosting VFS driver, including registering a host directory, redirecting stdout from UART to a file on the host, and reading and printing the content of a text file.
+
 API Reference
 -------------
 
 .. include-build-file:: inc/esp_vfs.inc
 
+.. include-build-file:: inc/esp_vfs_ops.inc
+
 .. include-build-file:: inc/esp_vfs_dev.inc
 
 .. include-build-file:: inc/uart_vfs.inc
diff --git a/docs/en/api-reference/storage/wear-levelling.rst b/docs/en/api-reference/storage/wear-levelling.rst
index b1f46f3f122..67d01488c9a 100644
--- a/docs/en/api-reference/storage/wear-levelling.rst
+++ b/docs/en/api-reference/storage/wear-levelling.rst
@@ -6,10 +6,10 @@ See Also
 - :doc:`./fatfs`
 - :doc:`../../api-guides/partition-tables`
 
-Application Example
--------------------
+Application Examples
+--------------------
 
-An example that combines the wear levelling driver with the FATFS library is provided in the :example:`storage/wear_levelling` directory. This example initializes the wear levelling driver, mounts FatFs partition, as well as writes and reads data from it using POSIX and C library APIs. See :example_file:`storage/wear_levelling/README.md` for more information.
+- :example:`storage/wear_levelling` demonstrates how to use the wear levelling library and FatFS library to store files in a partition, as well as write and read data from these files using POSIX and C library APIs.
 
 High-level API Reference
 ------------------------
diff --git a/docs/en/api-reference/system/bootloader_image_format.rst b/docs/en/api-reference/system/bootloader_image_format.rst
index 1937c81839b..98710de96fe 100644
--- a/docs/en/api-reference/system/bootloader_image_format.rst
+++ b/docs/en/api-reference/system/bootloader_image_format.rst
@@ -64,6 +64,7 @@ The ``DRAM0`` segment of the bootloader binary starts with the :cpp:type:`esp_bo
 
  * ``magic_byte``: the magic byte for the esp_bootloader_desc structure
  * ``reserved``: reserved for the future IDF use
+ * ``secure_version``: the secure version used by the bootloader anti-rollback feature, see :ref:`CONFIG_BOOTLOADER_ANTI_ROLLBACK_ENABLE`.
  * ``version``: bootloader version, see :ref:`CONFIG_BOOTLOADER_PROJECT_VER`
  * ``idf_ver``: ESP-IDF version. [#f1]_
  * ``date`` and ``time``: compile date and time
diff --git a/docs/en/api-reference/system/chip_revision.rst b/docs/en/api-reference/system/chip_revision.rst
index 1af4903cc3f..e3e48955584 100644
--- a/docs/en/api-reference/system/chip_revision.rst
+++ b/docs/en/api-reference/system/chip_revision.rst
@@ -110,7 +110,7 @@ Below is the information about troubleshooting when the chip revision fails the
 Troubleshooting
 ^^^^^^^^^^^^^^^
 
-1. If the 2nd stage bootloader is run on a chip revision smaller than minimum revision specified in the image (i.e., the application), a reboot occurs. The following message will be printed:
+1. If the second stage bootloader is run on a chip revision smaller than minimum revision specified in the image (i.e., the application), a reboot occurs. The following message will be printed:
 
 .. code-block:: none
 
@@ -132,7 +132,7 @@ To resolve this issue, update ESP-IDF to a newer version that supports the chip'
 Representing Revision Requirements of a Binary Image
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-For the chip revision, the 2nd stage bootloader and the application binary images contain the :cpp:type:`esp_image_header_t` header, which stores information specifying the chip revisions that the image is permitted to run on. This header has 3 fields related to the chip revisions:
+For the chip revision, the second stage bootloader and the application binary images contain the :cpp:type:`esp_image_header_t` header, which stores information specifying the chip revisions that the image is permitted to run on. This header has 3 fields related to the chip revisions:
 
 - ``min_chip_rev`` - Minimum chip MAJOR revision required by image (but for ESP32-C3 it is MINOR revision). Its value is determined by :ref:`CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MIN`.
 - ``min_chip_rev_full`` - Minimum chip MINOR revision required by image in format: ``major * 100 + minor``. Its value is determined by :ref:`CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MIN`.
@@ -148,11 +148,11 @@ Maximum And Minimum Revision Restrictions
 
 The order for checking the minimum and maximum revisions during application boot up is as follows:
 
-1. The 1st stage bootloader (ROM bootloader) does not check minimum and maximum revision fields from :cpp:type:`esp_image_header_t` before running the 2nd stage bootloader.
+1. The first stage (ROM) bootloader does not check minimum and maximum revision fields from :cpp:type:`esp_image_header_t` before running the 2nd stage bootloader.
 
-2. The initialization phase of the  2nd stage bootloader checks that the 2nd stage bootloader itself can be launched on the chip of this revision. It extracts the minimum revision from the header of the bootloader image and checks against the chip revision from eFuses. If the chip revision is less than the minimum revision, the bootloader refuses to boot up and aborts. The maximum revision is not checked at this phase.
+2. The initialization phase of the second stage bootloader checks that the second stage bootloader itself can be launched on the chip of this revision. It extracts the minimum revision from the header of the bootloader image and checks against the chip revision from eFuses. If the chip revision is less than the minimum revision, the bootloader refuses to boot up and aborts. The maximum revision is not checked at this phase.
 
-3. Then the 2nd stage bootloader checks the revision requirements of the application. It extracts the minimum and maximum revisions of the chip from the application image header, and the eFuse block from the segment header. Then the bootloader checks these versions against the chip and eFuse block revision from eFuses. If the these revisions are less than their minimum revision or higher than the maximum revision, the bootloader refuses to boot up and aborts. However, if the ignore maximum revision bit is set, the maximum revision constraint can be ignored. The ignore bits are set by the customer themselves when there is confirmation that the software is able to work with this chip revision or eFuse block revision.
+3. Then the second stage bootloader checks the revision requirements of the application. It extracts the minimum and maximum revisions of the chip from the application image header, and the eFuse block from the segment header. Then the bootloader checks these versions against the chip and eFuse block revision from eFuses. If the these revisions are less than their minimum revision or higher than the maximum revision, the bootloader refuses to boot up and aborts. However, if the ignore maximum revision bit is set, the maximum revision constraint can be ignored. The ignore bits are set by the customer themselves when there is confirmation that the software is able to work with this chip revision or eFuse block revision.
 
 4. Furthermore, at the OTA update stage, the running application checks if the new software matches the chip revision and eFuse block revision. It extracts the minimum and maximum chip revisions from the header of the new application image and the eFuse block constraints from the application description to check against the these revisions from eFuses. It checks for revisions matching in the same way that the bootloader does, so that the chip and eFuse block revisions are between their min and max revisions (logic of ignoring max revision also applies).
 
diff --git a/docs/en/api-reference/system/esp_https_ota.rst b/docs/en/api-reference/system/esp_https_ota.rst
index 623959968dd..7b84e4d0cee 100644
--- a/docs/en/api-reference/system/esp_https_ota.rst
+++ b/docs/en/api-reference/system/esp_https_ota.rst
@@ -150,6 +150,8 @@ Application Examples
 
 - :example:`system/ota/advanced_https_ota` demonstrates how to use the Advanced HTTPS OTA update functionality on {IDF_TARGET_NAME} using the `esp_https_ota` component's APIs. For the applicable SoCs, please refer to :example_file:`system/ota/advanced_https_ota/README.md`.
 
+- :example:`system/ota/partitions_ota` demonstrates how to perform OTA updates for various partitions (app, bootloader, partition table, storage) using the `esp_https_ota` component's APIs.
+
 - :example:`system/ota/simple_ota_example` demonstrates how to use the `esp_https_ota` component's APIs to support firmware upgrades through specific networking interfaces such as Ethernet or Wi-Fi Station on {IDF_TARGET_NAME}. For the applicable SoCs, please refer to :example_file:`system/ota/simple_ota_example/README.md`.
 
 API Reference
diff --git a/docs/en/api-reference/system/freertos.rst b/docs/en/api-reference/system/freertos.rst
index 0633d8641df..121c14348b4 100644
--- a/docs/en/api-reference/system/freertos.rst
+++ b/docs/en/api-reference/system/freertos.rst
@@ -47,7 +47,7 @@ Vanilla FreeRTOS requires that ports and applications configure the kernel by ad
 
 **However, for all FreeRTOS ports in ESP-IDF, the FreeRTOSConfig.h header file is considered private and must not be modified by users**. A large number of kernel configuration options in ``FreeRTOSConfig.h`` are hard-coded as they are either required/not supported by ESP-IDF. All kernel configuration options that are configurable by the user are exposed via menuconfig under ``Component Config/FreeRTOS/Kernel``.
 
-For the full list of user configurable kernel options, see :doc:`/api-reference/kconfig`. The list below highlights some commonly used kernel configuration options:
+For the full list of user configurable kernel options, see :ref:`Kconfig Options Reference <configuration-options-reference>`. The list below highlights some commonly used kernel configuration options:
 
 - :ref:`CONFIG_FREERTOS_UNICORE` runs FreeRTOS only on Core 0. Note that this is **not equivalent to running Vanilla FreeRTOS**. Furthermore, this option may affect behavior of components other than :component:`freertos`. For more details regarding the effects of running FreeRTOS on a single core, refer to :ref:`freertos-idf-single-core` (if using ESP-IDF FreeRTOS) or the official Amazon SMP FreeRTOS documentation. Alternatively, users can also search for occurrences of ``CONFIG_FREERTOS_UNICORE`` in the ESP-IDF components.
 
diff --git a/docs/en/api-reference/system/mem_alloc.rst b/docs/en/api-reference/system/mem_alloc.rst
index 5641ef8254b..dbe30659a0b 100644
--- a/docs/en/api-reference/system/mem_alloc.rst
+++ b/docs/en/api-reference/system/mem_alloc.rst
@@ -105,7 +105,7 @@ DMA-Capable Memory
 
 Use the ``MALLOC_CAP_DMA`` flag to allocate memory which is suitable for use with hardware DMA engines (for example SPI and I2S). This capability flag excludes any external PSRAM.
 
-.. only SOC_SPIRAM_SUPPORTED and not esp32::
+.. only:: SOC_SPIRAM_SUPPORTED and not esp32
 
     The EDMA hardware feature allows DMA buffers to be placed in external PSRAM, but there may be additional alignment constraints. Consult the {IDF_TARGET_NAME} Technical Reference Manual for details. To allocate a DMA-capable external memory buffer, use the ``MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA`` capabilities flags; the heap allocator will take care of alignment requirements imposed by the cache and DMA subsystems. If a peripheral has additional alignment requirements, you can use :cpp:func:`heap_caps_aligned_alloc` with the necessary alignment specified.
 
diff --git a/docs/en/api-reference/system/ota.rst b/docs/en/api-reference/system/ota.rst
index e446a5ce88d..edb8c69645c 100644
--- a/docs/en/api-reference/system/ota.rst
+++ b/docs/en/api-reference/system/ota.rst
@@ -8,9 +8,17 @@ OTA Process Overview
 
 The OTA update mechanism allows a device to update itself based on data received while the normal firmware is running (for example, over Wi-Fi, Bluetooth or Ethernet).
 
-OTA requires configuring the :doc:`../../api-guides/partition-tables` of the device with at least two OTA app slot partitions (i.e., ``ota_0`` and ``ota_1``) and an OTA Data Partition.
+The following modes support OTA updates for certain partitions:
 
-The OTA operation functions write a new app firmware image to whichever OTA app slot that is currently not selected for booting. Once the image is verified, the OTA Data partition is updated to specify that this image should be used for the next boot.
+- **Safe update mode**. The update process for certain partitions is designed to be resilient, ensuring that even if the power is cut off during the update, the chip will remain operational and capable of booting the current application. The following partitions support this mode:
+
+  - Application. OTA requires configuring the :doc:`../../api-guides/partition-tables` of the device with at least two OTA app slot partitions (i.e., ``ota_0`` and ``ota_1``) and an OTA Data Partition. The OTA operation functions write a new app firmware image to whichever OTA app slot that is currently not selected for booting. Once the image is verified, the OTA Data partition is updated to specify that this image should be used for the next boot.
+
+- **Unsafe update mode**. The update process is vulnerable, meaning that a power interruption during the update can cause issues that prevent the current application from loading, potentially leading to an unrecoverable state. The temporary partition receives the new image, and once it is fully downloaded, the image is copied to the final destination partition. If an interruption occurs during this final copying process, it can lead to issues. The following partitions support this mode:
+
+  - Bootloader.
+  - Partition table.
+  - other data partitions like nvs, fat, etc.
 
 .. _ota_data_partition:
 
@@ -19,7 +27,7 @@ OTA Data Partition
 
 An OTA data partition (type ``data``, subtype ``ota``) must be included in the :doc:`../../api-guides/partition-tables` of any project which uses the OTA functions.
 
-For factory boot settings, the OTA data partition should contain no data (all bytes erased to 0xFF). In this case, the ESP-IDF software bootloader will boot the factory app if it is present in the partition table. If no factory app is included in the partition table, the first available OTA slot (usually ``ota_0``) is booted.
+For factory boot settings, the OTA data partition should contain no data (all bytes erased to 0xFF). In this case, the ESP-IDF second stage bootloader boots the factory app if it is present in the partition table. If no factory app is included in the partition table, the first available OTA slot (usually ``ota_0``) is booted.
 
 After the first OTA update, the OTA data partition is updated to specify which OTA app slot partition should be booted next.
 
@@ -344,7 +352,7 @@ See Also
 Application Examples
 --------------------
 
-- :example:`system/ota/native_ota_example` demonstrates how to use the `app_update` component's APIs for native Over-the-Air (OTA) updates on {IDF_TARGET_NAME}. For the applicable SoCs, please refer to :example_file:`system/ota/native_ota_example/README.md`.
+- :example:`system/ota/native_ota_example` demonstrates how to use the `app_update` component's APIs for native over-the-air (OTA) updates on {IDF_TARGET_NAME}. For applicable SoCs, please refer to :example_file:`system/ota/native_ota_example/README.md`.
 
 - :example:`system/ota/otatool` demonstrates how to use the OTA tool to perform operations such as reading, writing, and erasing OTA partitions, switching boot partitions, and switching to factory partition. For more information, please refer to :example_file:`system/ota/otatool/README.md`.
 
diff --git a/docs/en/api-reference/system/power_management.rst b/docs/en/api-reference/system/power_management.rst
index 8a7b9c37ba8..98434d8c6c8 100644
--- a/docs/en/api-reference/system/power_management.rst
+++ b/docs/en/api-reference/system/power_management.rst
@@ -141,40 +141,44 @@ The following peripheral drivers are not aware of DFS yet. Applications need to
 
         If :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP` is enabled, when the driver initializes the peripheral, the driver will register the working register context of the peripheral to the sleep retention link. Before entering sleep, the ``REG_DMA`` peripheral reads the configuration in the sleep retention link, and back up the register context to memory according to the configuration. ``REG_DMA`` also restores context from memory to peripheral registers on wakeup.
 
-        Currently ESP-IDF supports Light-sleep context retention for the following peripherals:
+        Currently ESP-IDF supports Light-sleep context retention for the following peripherals. Their context is automatically restored, or they provide some option for the user to enable this feature and goes into peripheral power down mode.
 
         .. list::
 
             - INT_MTX
             - TEE/APM
             - IO_MUX / GPIO
-            - Timer Group 0 & Timer Group 1
-            - SPI0/1
+            - MSPI (SPI0/1)
             - SYSTIMER
+            :SOC_TIMER_SUPPORT_SLEEP_RETENTION: - GPTimer
             :SOC_RMT_SUPPORT_SLEEP_RETENTION: - RMT
+            :SOC_ETM_SUPPORT_SLEEP_RETENTION: - ETM
+            :SOC_LEDC_SUPPORT_SLEEP_RETENTION: - LEDC
             :SOC_I2C_SUPPORT_SLEEP_RETENTION: - I2C
             :SOC_I2S_SUPPORT_SLEEP_RETENTION: - I2S
+            :SOC_MCPWM_SUPPORT_SLEEP_RETENTION: - MCPWM
             :SOC_UART_SUPPORT_SLEEP_RETENTION: - All UARTs
+            :SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION: - Temperature Sensor
+            :SOC_TWAI_SUPPORT_SLEEP_RETENTION: - All TWAIs
+            :SOC_PARLIO_SUPPORT_SLEEP_RETENTION: - PARL_IO
+            :SOC_SPI_SUPPORT_SLEEP_RETENTION: - All GPSPIs
 
-        The following peripherals are not yet supported:
+        Some peripherals haven't support Light-sleep context retention, or it cannot survive from the register lose. They will prevent the power-down of peripherals even when the feature is enabled.
+
+        .. list::
+
+            :SOC_SDIO_SLAVE_SUPPORTED: - SDIO Slave
+
+        The following peripherals (and those not listed in any group of this section) are not yet supported. If your application uses these peripherals, they may not work well after waking up from sleep.
 
         .. list::
 
-            - ETM
             - ASSIST_DEBUG
             - Trace
             - Crypto: AES/ECC/HMAC/RSA/SHA/DS/XTA_AES/ECDSA
-            - SPI2
             - PCNT
             - USB-Serial-JTAG
-            - TWAI
-            - LEDC
-            - MCPWM
             - SARADC
-            - SDIO
-            - PARL_IO
-
-        For peripherals that do not support Light-sleep context retention, if the Power management is enabled, the ``ESP_PM_NO_LIGHT_SLEEP`` lock should be held when the peripheral is working to avoid losing the working context of the peripheral when entering sleep.
 
         .. note::
 
diff --git a/docs/en/api-reference/system/pthread.rst b/docs/en/api-reference/system/pthread.rst
index f78a8fbe6e7..894e1a659ef 100644
--- a/docs/en/api-reference/system/pthread.rst
+++ b/docs/en/api-reference/system/pthread.rst
@@ -183,6 +183,7 @@ Message Queues
 ^^^^^^^^^^^^^^
 
 The message queue implementation is based on the `FreeRTOS-Plus-POSIX <https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_POSIX/index.html>`_ project. Message queues are not made available in any filesystem on ESP-IDF. Message priorities are not supported.
+
 The following API functions of the POSIX message queue specification are implemented:
 
 * `mq_open() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_open.html>`_
@@ -191,7 +192,7 @@ The following API functions of the POSIX message queue specification are impleme
         - It has to begin with a leading slash.
         - It has to be no more than 255 + 2 characters long (including the leading slash, excluding the terminating null byte). However, memory for ``name`` is dynamically allocated internally, so the shorter it is, the fewer memory it will consume.
     - The ``mode`` argument is not implemented and is ignored.
-    - Supported ``oflags``: ``O_RDWR``, ``O_CREAT``, ``O_EXCL``, and ``O_NONBLOCK``
+    - Supported ``oflags``: ``O_RDWR``, ``O_CREAT``, ``O_EXCL``, and ``O_NONBLOCK``.
 
 * `mq_close() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_close.html>`_
 * `mq_unlink() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_unlink.html>`_
@@ -218,7 +219,7 @@ The following API functions of the POSIX message queue specification are impleme
 Building
 ........
 
-To use the POSIX message queue API, please add ``rt`` as a requirement in your component's ``CMakeLists.txt``
+To use the POSIX message queue API, please add ``rt`` as a requirement in your component's ``CMakeLists.txt``.
 
 .. note::
 
diff --git a/docs/en/api-reference/system/ulp-lp-core.rst b/docs/en/api-reference/system/ulp-lp-core.rst
index 1e91c49c69d..0e8a7ca2fec 100644
--- a/docs/en/api-reference/system/ulp-lp-core.rst
+++ b/docs/en/api-reference/system/ulp-lp-core.rst
@@ -1,11 +1,11 @@
-ULP LP-Core Coprocessor Programming
+ULP LP Core Coprocessor Programming
 ===================================
 
 :link_to_translation:`zh_CN:[中文]`
 
-The ULP LP-Core (Low-power core) coprocessor is a variant of the ULP present in {IDF_TARGET_NAME}. It features ultra-low power consumption while also being able to stay powered on while the main CPU stays in low-power modes. This enables the LP-Core coprocessor to handle tasks like GPIO or sensor readings while the main CPU is in sleep mode, resulting in significant overall power savings for the entire system.
+The ULP LP core (Low-power core) coprocessor is a variant of the ULP present in {IDF_TARGET_NAME}. It features ultra-low power consumption while also being able to stay powered on while the main CPU stays in low-power modes. This enables the LP core coprocessor to handle tasks like GPIO or sensor readings while the main CPU is in sleep mode, resulting in significant overall power savings for the entire system.
 
-The ULP LP-Core coprocessor has the following features:
+The ULP LP core coprocessor has the following features:
 
 * A RV32I (32-bit RISC-V ISA) processor, with the multiplication/division (M), atomic (A), and compressed (C) extensions.
 * Interrupt controller.
@@ -13,15 +13,15 @@ The ULP LP-Core coprocessor has the following features:
 * Can access all of the High-power (HP) SRAM and peripherals when the entire system is active.
 * Can access the Low-power (LP) SRAM and peripherals when the HP system is in sleep mode.
 
-Compiling Code for the ULP LP-Core
+Compiling Code for the ULP LP Core
 ----------------------------------
 
-The ULP LP-Core code is compiled together with your ESP-IDF project as a separate binary and automatically embedded into the main project binary. There are two ways to achieve this:
+The ULP LP core code is compiled together with your ESP-IDF project as a separate binary and automatically embedded into the main project binary. There are two ways to achieve this:
 
 Using ``ulp_embed_binary``
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-1. Place the ULP LP-Core code, written in C or assembly (with the ``.S`` extension), in a dedicated directory within the component directory, such as ``ulp/``.
+1. Place the ULP LP core code, written in C or assembly (with the ``.S`` extension), in a dedicated directory within the component directory, such as ``ulp/``.
 
 2. After registering the component in the ``CMakeLists.txt`` file, call the ``ulp_embed_binary`` function. Here is an example:
 
@@ -41,7 +41,7 @@ The first argument to ``ulp_embed_binary`` specifies the ULP binary name. The na
 Using a Custom CMake Project
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-It is also possible to create a custom CMake project for the LP-Core. This gives more control over the build process and allows you to set compile options, link external libraries and all other things that are possible with a regular CMake project.
+It is also possible to create a custom CMake project for the LP core. This gives more control over the build process and allows you to set compile options, link external libraries and all other things that are possible with a regular CMake project.
 
 To do this, add the ULP project as an external project in your component ``CMakeLists.txt`` file:
 
@@ -90,7 +90,7 @@ Building Your Project
 
 To compile and build your project:
 
-1. Enable both :ref:`CONFIG_ULP_COPROC_ENABLED` and :ref:`CONFIG_ULP_COPROC_TYPE` in menuconfig, and set :ref:`CONFIG_ULP_COPROC_TYPE` to ``CONFIG_ULP_COPROC_TYPE_LP_CORE``. The :ref:`CONFIG_ULP_COPROC_RESERVE_MEM` option reserves RTC memory for the ULP, and must be set to a value big enough to store both the ULP LP-Core code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one.
+1. Enable both :ref:`CONFIG_ULP_COPROC_ENABLED` and :ref:`CONFIG_ULP_COPROC_TYPE` in menuconfig, and set :ref:`CONFIG_ULP_COPROC_TYPE` to ``CONFIG_ULP_COPROC_TYPE_LP_CORE``. The :ref:`CONFIG_ULP_COPROC_RESERVE_MEM` option reserves RTC memory for the ULP, and must be set to a value big enough to store both the ULP LP core code and data. If the application components contain multiple ULP programs, then the size of the RTC memory must be sufficient to hold the largest one.
 
 2. Build the application as usual (e.g., ``idf.py app``).
 
@@ -113,12 +113,12 @@ During the build process, the following steps are taken to build ULP program:
 
 .. _ulp-lp-core-access-variables:
 
-Accessing the ULP LP-Core Program Variables
+Accessing the ULP LP Core Program Variables
 -------------------------------------------
 
-Global symbols defined in the ULP LP-Core program may be used inside the main program.
+Global symbols defined in the ULP LP core program may be used inside the main program.
 
-For example, the ULP LP-Core program may define a variable ``measurement_count`` which defines the number of GPIO measurements the program needs to make before waking up the chip from Deep-sleep.
+For example, the ULP LP core program may define a variable ``measurement_count`` which defines the number of GPIO measurements the program needs to make before waking up the chip from Deep-sleep.
 
 .. code-block:: c
 
@@ -132,7 +132,7 @@ For example, the ULP LP-Core program may define a variable ``measurement_count``
         ...do something.
     }
 
-The main program can access the global ULP LP-Core program variables as the build system makes this possible by generating the ``${ULP_APP_NAME}.h`` and ``${ULP_APP_NAME}.ld`` files which define the global symbols present in the ULP LP-Core program. Each global symbol defined in the ULP LP-Core program is included in these files and are prefixed with ``ulp_``.
+The main program can access the global ULP LP core program variables as the build system makes this possible by generating the ``${ULP_APP_NAME}.h`` and ``${ULP_APP_NAME}.ld`` files which define the global symbols present in the ULP LP core program. Each global symbol defined in the ULP LP core program is included in these files and are prefixed with ``ulp_``.
 
 The header file contains the declaration of the symbol:
 
@@ -148,7 +148,7 @@ The generated linker script file defines the locations of symbols in LP_MEM:
 
     PROVIDE ( ulp_measurement_count = 0x50000060 );
 
-To access the ULP LP-Core program variables from the main program, the generated header file should be included using an ``include`` statement. This allows the ULP LP-Core program variables to be accessed as regular variables.
+To access the ULP LP core program variables from the main program, the generated header file should be included using an ``include`` statement. This allows the ULP LP core program variables to be accessed as regular variables.
 
 .. code-block:: c
 
@@ -160,15 +160,15 @@ To access the ULP LP-Core program variables from the main program, the generated
 
 .. note::
 
-    Variables declared in the global scope of the LP-Core program reside in either the ``.bss`` or ``.data`` section of the binary. These sections are initialized when the LP-Core binary is loaded and executed. Accessing these variables from the main program on the HP-Core before the first LP-Core run may result in undefined behavior.
+    Variables declared in the global scope of the LP core program reside in either the ``.bss`` or ``.data`` section of the binary. These sections are initialized when the LP core binary is loaded and executed. Accessing these variables from the main program on the HP-Core before the first LP core run may result in undefined behavior.
 
 
-Starting the ULP LP-Core Program
+Starting the ULP LP Core Program
 --------------------------------
 
-To run a ULP LP-Core program, the main application needs to load the ULP program into RTC memory using the :cpp:func:`ulp_lp_core_load_binary` function, and then start it using the :cpp:func:`ulp_lp_core_run` function.
+To run a ULP LP core program, the main application needs to load the ULP program into RTC memory using the :cpp:func:`ulp_lp_core_load_binary` function, and then start it using the :cpp:func:`ulp_lp_core_run` function.
 
-Each ULP LP-Core program is embedded into the ESP-IDF application as a binary blob. The application can reference this blob and load it in the following way (supposed ULP_APP_NAME was defined to ``ulp_app_name``):
+Each ULP LP core program is embedded into the ESP-IDF application as a binary blob. The application can reference this blob and load it in the following way (supposed ULP_APP_NAME was defined to ``ulp_app_name``):
 
 .. code-block:: c
 
@@ -191,17 +191,17 @@ Once the program is loaded into LP memory, the application can be configured and
 
     ESP_ERROR_CHECK( ulp_lp_core_run(&cfg) );
 
-ULP LP-Core Program Flow
+ULP LP Core Program Flow
 ------------------------
 
-How the ULP LP-Core coprocessor is started depends on the wake-up source selected in :cpp:type:`ulp_lp_core_cfg_t`. The most common use-case is for the ULP to periodically wake up, do some measurements before either waking up the main CPU or going back to sleep again.
+How the ULP LP core coprocessor is started depends on the wake-up source selected in :cpp:type:`ulp_lp_core_cfg_t`. The most common use-case is for the ULP to periodically wake up, do some measurements before either waking up the main CPU or going back to sleep again.
 
 The ULP has the following wake-up sources:
-    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU` - LP Core can be woken up by the HP CPU.
-    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER` - LP Core can be woken up by the LP timer.
-    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_ETM` - LP Core can be woken up by a ETM event. (Not yet supported)
-    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_IO` - LP Core can be woken up when LP IO level changes. (Not yet supported)
-    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_UART` - LP Core can be woken up after receiving a certain number of UART RX pulses. (Not yet supported)
+    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU` - LP core can be woken up by the HP CPU.
+    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER` - LP core can be woken up by the LP timer.
+    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_ETM` - LP core can be woken up by a ETM event. (Not yet supported)
+    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_IO` - LP core can be woken up when LP IO level changes. (Not yet supported)
+    * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_LP_UART` - LP core can be woken up after receiving a certain number of UART RX pulses. (Not yet supported)
 
 When the ULP is woken up, it will go through the following steps:
 
@@ -215,10 +215,10 @@ When the ULP is woken up, it will go through the following steps:
     #. Call :cpp:func:`ulp_lp_core_halt`
 
 
-ULP LP-Core Peripheral Support
+ULP LP Core Peripheral Support
 ------------------------------
 
-To enhance the capabilities of the ULP LP-Core coprocessor, it has access to peripherals that operate in the low-power domain. The ULP LP-Core coprocessor can interact with these peripherals when the main CPU is in sleep mode, and can wake up the main CPU once a wake-up condition is reached. The following peripherals are supported:
+To enhance the capabilities of the ULP LP core coprocessor, it has access to peripherals that operate in the low-power domain. The ULP LP core coprocessor can interact with these peripherals when the main CPU is in sleep mode, and can wake up the main CPU once a wake-up condition is reached. The following peripherals are supported:
 
 .. list::
 
@@ -229,10 +229,10 @@ To enhance the capabilities of the ULP LP-Core coprocessor, it has access to per
 
 .. only:: CONFIG_ESP_ROM_HAS_LP_ROM
 
-    ULP LP-Core ROM
+    ULP LP Core ROM
     ---------------
 
-    The ULP LP-Core ROM is a small pre-built piece of code located in LP-ROM, which can't be modified. Similar to the bootloader ROM code ran by the main CPU, this code is executed when the ULP LP-Core coprocessor is started. The ROM code initializes the ULP LP-Core coprocessor and then jumps to the user program. The ROM code also prints boot messages if the LP UART has been initialized.
+    The ULP LP core ROM is a small pre-built piece of code located in LP-ROM, which can't be modified. Similar to the bootloader ROM code ran by the main CPU, this code is executed when the ULP LP core coprocessor is started. The ROM code initializes the ULP LP core coprocessor and then jumps to the user program. The ROM code also prints boot messages if the LP UART has been initialized.
 
     The ROM code is not executed if :cpp:member:`ulp_lp_core_cfg_t::skip_lp_rom_boot` is set to true. This is useful when you need the ULP to wake-up as quickly as possible and the extra overhead of initializing and printing is unwanted.
 
@@ -244,12 +244,12 @@ To enhance the capabilities of the ULP LP-Core coprocessor, it has access to per
     Since these functions are already present in LP-ROM no matter what, using these in your program allows you to reduce the RAM footprint of your ULP application.
 
 
-ULP LP-Core Interrupts
+ULP LP Core Interrupts
 ----------------------
 
-The LP-Core coprocessor can be configured to handle interrupts from various sources. Examples of such interrupts could be LP IO low/high or LP timer interrupts. To register a handler for an interrupt, simply override any of the weak handlers provided by IDF. A complete list of handlers can be found in :component_file:`ulp_lp_core_interrupts.h <ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h>`. For details on which interrupts are available on a specific target, please consult **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#ulp>`__].
+The LP core coprocessor can be configured to handle interrupts from various sources. Examples of such interrupts could be LP IO low/high or LP timer interrupts. To register a handler for an interrupt, simply override any of the weak handlers provided by IDF. A complete list of handlers can be found in :component_file:`ulp_lp_core_interrupts.h <ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h>`. For details on which interrupts are available on a specific target, please consult **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#ulp>`__].
 
-For example, to override the handler for the LP IO interrupt, you can define the following function in your ULP LP-Core code:
+For example, to override the handler for the LP IO interrupt, you can define the following function in your ULP LP core code:
 
 .. code-block:: c
 
@@ -260,39 +260,40 @@ For example, to override the handler for the LP IO interrupt, you can define the
 
 :c:macro:`LP_CORE_ISR_ATTR` is a macro that is used to define the interrupt handler function. This macro ensures that registers are saved and restored correctly when the interrupt handler is called.
 
-In addition to configuring the interrupt related registers for the interrupt source you want to handle, you also need to enable the interrupts globally in the LP-Core interrupt controller. This can be done using the :cpp:func:`ulp_lp_core_intr_enable` function.
+In addition to configuring the interrupt related registers for the interrupt source you want to handle, you also need to enable the interrupts globally in the LP core interrupt controller. This can be done using the :cpp:func:`ulp_lp_core_intr_enable` function.
 
-ULP LP-Core Clock Configuration
+ULP LP Core Clock Configuration
 -------------------------------
+
 {IDF_TARGET_XTAL_FREQ:default="Not updated", esp32c5="48 MHz", esp32p4="40 MHz"}
 
-The ULP LP-Core clock source is based on the system clock ``LP_FAST_CLK``, see `TRM <{IDF_TARGET_TRM_EN_URL}>`__ > ``Reset and Clock`` for more details.
+The ULP LP Core clock source is based on the system clock ``LP_FAST_CLK``, see `TRM <{IDF_TARGET_TRM_EN_URL}>`__ > ``Reset and Clock`` for more details.
 
 .. only:: SOC_CLK_LP_FAST_SUPPORT_XTAL
 
-    On {IDF_TARGET_NAME} ``LP_FAST_CLK`` supports using the external {IDF_TARGET_XTAL_FREQ} crystal (XTAL) as the source for ``LP_FAST_CLK``, which allows the ULP LP-Core to run at a higher frequency than with the default ``RTC_FAST_CLOCK`` which runs at around 20 MHz. The drawback is that this clock is normally powered down during sleep to reduce power consumption, with it selected XTAL will also stay powered on during sleep, increasing power consumption. If you only plan to use the LP-Core as a co-processor while the HP-Core is active, then this option can be used to increase both the performance and the frequency stability of the LP-Core.
+    On {IDF_TARGET_NAME}, ``LP_FAST_CLK`` supports using the external {IDF_TARGET_XTAL_FREQ} crystal (XTAL) as its clock source. This allows the ULP LP Core to run at a higher frequency than with the default ``RTC_FAST_CLOCK``, which runs at around 20 MHz. However, there is a trade-off: this clock is normally powered down during sleep to reduce power consumption, but if XTAL is selected as the source, it will remain powered up during sleep, which increases power consumption. If you only plan to use the LP Core as a coprocessor while the HP Core is active, then selecting XTAL can enhance both the performance and frequency stability of the LP Core.
 
-    To enable this feature set :ref:`CONFIG_RTC_FAST_CLK_SRC` to ``CONFIG_RTC_FAST_CLK_SRC_XTAL``.
+    To enable this feature, set :ref:`CONFIG_RTC_FAST_CLK_SRC` to ``CONFIG_RTC_FAST_CLK_SRC_XTAL``.
 
 
 Debugging ULP LP-Core Applications
 ----------------------------------
 
-When programming the LP-Core, it can sometimes be challenging to figure out why the program is not behaving as expected. Here are some strategies to help you debug your LP-Core program:
+When programming the LP core, it can sometimes be challenging to figure out why the program is not behaving as expected. Here are some strategies to help you debug your LP core program:
 
-* Use the LP-UART to print: the LP-Core has access to the LP-UART peripheral, which can be used for printing information independently of the main CPU sleep state. See :example:`system/ulp/lp_core/lp_uart/lp_uart_print` for an example of how to use this driver.
+* Use the LP-UART to print: the LP core has access to the LP-UART peripheral, which can be used for printing information independently of the main CPU sleep state. See :example:`system/ulp/lp_core/lp_uart/lp_uart_print` for an example of how to use this driver.
 
-* Routing :cpp:func:`lp_core_printf` to the HP-Core console UART with :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`. This allows you to easily print LP-Core information to the already connected HP-Core console UART. The drawback of this approach is that it requires the main CPU to be awake and since there is no synchronization between the LP and HP cores, the output may be interleaved.
+* Routing :cpp:func:`lp_core_printf` to the HP-Core console UART with :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`. This allows you to easily print LP core information to the already connected HP-Core console UART. The drawback of this approach is that it requires the main CPU to be awake and since there is no synchronization between the LP and HP cores, the output may be interleaved.
 
 * Share program state through shared variables: as described in :ref:`ulp-lp-core-access-variables`, both the main CPU and the ULP core can easily access global variables in RTC memory. Writing state information to such a variable from the ULP and reading it from the main CPU can help you discern what is happening on the ULP core. The downside of this approach is that it requires the main CPU to be awake, which will not always be the case. Keeping the main CPU awake might even, in some cases, mask problems, as some issues may only occur when certain power domains are powered down.
 
-* Panic handler: the LP-Core has a panic handler that can dump the state of the LP-Core registers by the LP-UART when an exception is detected. To enable the panic handler, set the :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` option to ``y``. This option can be kept disabled to reduce LP-RAM usage by the LP-Core application. To recover a backtrace from the panic dump, it is possible to use  esp-idf-monitor_., e.g.:
+* Panic handler: the LP core has a panic handler that can dump the state of the LP core registers by the LP-UART when an exception is detected. To enable the panic handler, set the :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` option to ``y``. This option can be kept disabled to reduce LP-RAM usage by the LP core application. To recover a backtrace from the panic dump, it is possible to use  esp-idf-monitor_., e.g.:
 
     .. code-block:: bash
 
         python -m esp_idf_monitor --toolchain-prefix riscv32-esp-elf- --target {IDF_TARGET_NAME} --decode-panic backtrace PATH_TO_ULP_ELF_FILE
 
-Debugging ULP LP-Core Applications with GDB and OpenOCD
+Debugging ULP LP Core Applications with GDB and OpenOCD
 -------------------------------------------------------
 
 It is also possible to debug code running on LP core using GDB and OpenOCD as you usually do for HP cores, but it has some specifics and limitations.
@@ -307,7 +308,7 @@ Run OpenOCD with special config file for LP core debugging support. And then run
     openocd -f board/{IDF_TARGET_PATH_NAME}-lpcore-builtin.cfg
     riscv32-esp-elf-gdb -x gdbinit <path to main program ELF>
 
-``gdbinit`` file contents with inline comments is below. For more details see the next section.
+Below is the ``gdbinit`` file content with inline comments. For more details, see the next section.
 
 .. code-block:: bash
 
@@ -339,17 +340,17 @@ LP Core Debugging Specifics
 
 .. list::
 
-    #. For convenient debugging you may need to add `-O0` compile option for ULP app in its CMakeLists.txt. See :example:`system/ulp/lp_core/debugging/` how to do this.
-    :not esp32p4: #. LP core supports limited set of HW exceptions, so, for example, writing at address `0x0` will not cause a panic as it would be for the code running on HP core. This can be overcome to some extent by enabling undefined behavior sanitizer for LP core application, so `ubsan` can help to catch some errors. But note that it will increase code size significantly and it can happen that application won't fit into RTC RAM. To enable `ubsan` for ULP app add `-fsanitize=undefined -fno-sanitize=shift-base` compile option to its CMakeLists.txt. See :example:`system/ulp/lp_core/debugging/` how to do this.
-    #. To be able to debug program running on LP core debug info and symbols need to be loaded to GDB. It can be done via GDB command line or in ``gdbinit`` file. See section above.
-    #. Upon startup LP core application is loaded into RAM, so all SW breakpoints set before that moment will get overwritten. The best moment to set breakpoints for LP core application is to do this when LP core program reaches `main` function.
-    #. When using IDEs it can be that it does not support breakpoint actions/commands configuration shown in ``gdbinit`` above, so in this case you have to preset all breakpoints before debug session start and disable all of them except for ``main``. When program is stopped at ``main`` manually enable remaining breakpoints and resume execution.
+    #. For convenient debugging, you may need to add ``-O0`` compile option for ULP app in its ``CMakeLists.txt``. See :example:`system/ulp/lp_core/debugging/` on how to do this.
+    :not esp32p4: #. LP core supports limited set of HW exceptions, so, for example, writing at address `0x0` will not cause a panic as it would be for the code running on HP core. This can be overcome to some extent by enabling undefined behavior sanitizer for LP core application, so `ubsan` can help to catch some errors. But note that it will increase code size significantly and it can happen that application won't fit into RTC RAM. To enable `ubsan` for ULP app, add ``-fsanitize=undefined -fno-sanitize=shift-base`` compile option to its ``CMakeLists.txt``. See :example:`system/ulp/lp_core/debugging/` on how to do this.
+    #. To be able to debug program running on LP core, debugging information and symbols need to be loaded to GDB. It can be done via GDB command line or in ``gdbinit`` file. See section above.
+    #. Upon startup, LP core application is loaded into RAM, so all SW breakpoints set before that moment will get overwritten. The best moment to set breakpoints for LP core application is to do this when LP core program reaches `main` function.
+    #. When using IDEs, it may lack support for configuring breakpoint actions or commands shown in ``gdbinit`` above. Consequently, you have to preset all breakpoints before debug session start and disable all of them except for ``main``. When program stops at ``main``, enable the remaining breakpoints and resume execution manually.
 
 Limitations
 ~~~~~~~~~~~
 
-#. Currently debugging is not supported when either HP or LP core enters any sleep mode. So it limits available debugging scenarios.
-#. FreeRTOS support in OpenOCD is disabled when debugging LP core, so you won't be able to see tasks running in the system. Instead there will be several threads representing HP and LP cores:
+#. Currently, debugging is not supported when either HP or LP core enters any sleep mode. So it limits available debugging scenarios.
+#. FreeRTOS support in OpenOCD is disabled when debugging LP core, so you won't be able to see tasks running in the system. Instead, there will be several threads representing HP and LP cores:
 
 .. code-block:: bash
 
@@ -360,28 +361,23 @@ Limitations
       * 2    Thread 2 "{IDF_TARGET_PATH_NAME}.cpu1" (Name: {IDF_TARGET_PATH_NAME}.cpu1, state: breakpoint)    do_things (max=1000000000)
             at /home/user/projects/esp/esp-idf/examples/system/ulp/lp_core/debugging/main/lp_core/main.c:21
 
-#. When setting HW breakpoint in GDB it is set on both cores, so the number of available HW breakpoints is limited to the number of them supported by LP core ({IDF_TARGET_SOC_CPU_BREAKPOINTS_NUM} for {IDF_TARGET_NAME}).
-#. OpenOCD flash support is disabled. It does not matter for LP core application because it is run completely from RAM and GDB can use SW breakpoints for it. But if you want to set a breakpoint on function from flash used by the code running on HP core (e.g. `app_main`) you should request to set HW breakpoint explicitly via ``hb`` / ``thb`` GDB commands.
-#. Since main and ULP programs are linked as separate binaries it is possible for them to have global symbols (functions, variables) with the same name. When you set breakpoint for such a functions using its name GDB will set breakpoints for all of them. It could lead to the problems when one of the function is located in the flash because currently flash support is disabled in OpenOCD when debugging LP core. In that case you can use source line or address based breakpoints.
+#. When setting HW breakpoint in GDB, it is set on both cores, so the number of available HW breakpoints is limited to the number of them supported by LP core ({IDF_TARGET_SOC_CPU_BREAKPOINTS_NUM} for {IDF_TARGET_NAME}).
+#. OpenOCD flash support is disabled. It does not matter for LP core application because it is run completely from RAM and GDB can use SW breakpoints for it. But if you want to set a breakpoint on function from flash used by the code running on HP core (e.g., `app_main`), you should request to set HW breakpoint explicitly via ``hb`` and ``thb`` GDB commands.
+#. Since the main and ULP programs are linked as separate binaries, it is possible for them to have global symbols (such as functions or variables) with the same name. If you set a breakpoint using the function name, GDB will apply it to all instances of that function. This can cause issues if one of the functions is located in the flash, as OpenOCD currently doesn't support flash when debugging the LP core. In such cases, you can set breakpoints using the source line or the function's memory address instead.
 
 Application Examples
 --------------------
 
-* :example:`system/ulp/lp_core/gpio` polls GPIO while main CPU is in Deep-sleep.
-
-.. only:: esp32c6
-
-    * :example:`system/ulp/lp_core/lp_i2c` reads external I2C ambient light sensor (BH1750) while the main CPU is in Deep-sleep and wakes up the main CPU once a threshold is met.
-
-* :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver running on the LP core.
-
-* :example:`system/ulp/lp_core/lp_uart/lp_uart_print` shows how to print various statements from a program running on the LP core.
-
-* :example:`system/ulp/lp_core/interrupt` shows how to register an interrupt handler on the LP core to receive an interrupt triggered by the main CPU.
-* :example:`system/ulp/lp_core/gpio_intr_pulse_counter` shows how to use GPIO interrupts to count pulses while the main CPU is in Deep-sleep mode.
+.. list::
 
-* :example:`system/ulp/lp_core/build_system/` demonstrates how to include custom ``CMakeLists.txt`` file for the ULP app.
-* :example:`system/ulp/lp_core/debugging` shows how to debug code running on LP core using GDB and OpenOCD.
+    - :example:`system/ulp/lp_core/gpio` polls GPIO while main CPU is in Deep-sleep.
+    :esp32c6: - :example:`system/ulp/lp_core/lp_i2c` reads external I2C ambient light sensor (BH1750) while the main CPU is in Deep-sleep and wakes up the main CPU once a threshold is met.
+    - :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` reads data written to a serial console and echoes it back. This example demonstrates the usage of the LP UART driver running on the LP core.
+    - :example:`system/ulp/lp_core/lp_uart/lp_uart_print` shows how to print various statements from a program running on the LP core.
+    - :example:`system/ulp/lp_core/interrupt` shows how to register an interrupt handler on the LP core to receive an interrupt triggered by the main CPU.
+    - :example:`system/ulp/lp_core/gpio_intr_pulse_counter` shows how to use GPIO interrupts to count pulses while the main CPU is in Deep-sleep mode.
+    - :example:`system/ulp/lp_core/build_system/` demonstrates how to include custom ``CMakeLists.txt`` file for the ULP app.
+    - :example:`system/ulp/lp_core/debugging` shows how to debug code running on LP core using GDB and OpenOCD.
 
 API Reference
 -------------
diff --git a/docs/en/get-started/flashing-troubleshooting.rst b/docs/en/get-started/flashing-troubleshooting.rst
index 8664fe1ede6..3c8ad87575c 100644
--- a/docs/en/get-started/flashing-troubleshooting.rst
+++ b/docs/en/get-started/flashing-troubleshooting.rst
@@ -8,7 +8,7 @@ Failed to Connect
 
 {IDF_TARGET_STRAP_GPIO:default="[NEEDS TO BE UPDATED]", esp32="GPIO0", esp32s2="GPIO0", esp32s3="GPIO0", esp32c2="GPIO9", esp32c3="GPIO9", esp32c6="GPIO9", esp32h2="GPIO9", esp32p4="GPIO35"}
 
-If you run the given command and see errors such as "Failed to connect", there might be several reasons for this. One of the reasons might be issues encountered by ``esptool.py``, the utility that is called by the build system to reset the chip, interact with the ROM bootloader, and flash firmware. One simple solution to try is to manually reset as described below. If it does not help, you can find more details about possible issues in the `esptool troubleshooting <https://docs.espressif.com/projects/esptool/en/latest/esp32/troubleshooting.html>`_ page.
+If you run the given command and see errors such as "Failed to connect", there might be several reasons for this. One of the reasons might be issues encountered by ``esptool.py``, the utility that is called by the build system to reset the chip, interact with the first stage (ROM) bootloader, and flash firmware. One simple solution to try is to manually reset as described below. If it does not help, you can find more details about possible issues in the `esptool troubleshooting <https://docs.espressif.com/projects/esptool/en/latest/esp32/troubleshooting.html>`_ page.
 
 ``esptool.py`` resets {IDF_TARGET_NAME} automatically by asserting DTR and RTS control lines of the USB-to-UART bridge, i.e., FTDI or CP210x (for more information, see :doc:`establish-serial-connection`). The DTR and RTS control lines are in turn connected to ``{IDF_TARGET_STRAP_GPIO}`` and ``CHIP_PU`` (EN) pins of {IDF_TARGET_NAME}, thus changes in the voltage levels of DTR and RTS will boot {IDF_TARGET_NAME} into Firmware Download mode. As an example, check the `schematic <https://dl.espressif.com/dl/schematics/esp32_devkitc_v4-sch-20180607a.pdf>`_ for the ESP32 DevKitC development board.
 
diff --git a/docs/en/get-started/index.rst b/docs/en/get-started/index.rst
index 31051267b3c..935370c4b95 100644
--- a/docs/en/get-started/index.rst
+++ b/docs/en/get-started/index.rst
@@ -108,19 +108,19 @@ If you have one of {IDF_TARGET_NAME} official development boards listed below, y
         :maxdepth: 1
 
         ESP32-DevKitC <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-devkitc/index.html>
+        ESP32-DevKitM-1 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-devkitm-1/index.html>
         ESP-WROVER-KIT <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp-wrover-kit/index.html>
         ESP32-PICO-KIT <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-pico-kit/index.html>
         ESP32-Ethernet-Kit <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-ethernet-kit/index.html>
         ESP32-PICO-KIT-1 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-pico-kit-1/index.html>
         ESP32-PICO-DevKitM-2 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-pico-devkitm-2/index.html>
-        ESP32-DevKitM-1 <../hw-reference/esp32/user-guide-devkitm-1>
 
 .. only:: esp32s2
 
     .. toctree::
         :maxdepth: 1
 
-        ESP32-S2-Saola-1 <../hw-reference/esp32s2/user-guide-saola-1-v1.2>
+        ESP32-S2-Saola-1 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-saola-1/index.html>
         ESP32-S2-DevKitM-1 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-devkitm-1/index.html>
         ESP32-S2-DevKitC-1 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-devkitc-1/index.html>
         ESP32-S2-Kaluga-Kit <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-kaluga-1/index.html>
@@ -139,8 +139,8 @@ If you have one of {IDF_TARGET_NAME} official development boards listed below, y
     .. toctree::
         :maxdepth: 1
 
-        ESP32-S3-DevKitC-1 <../hw-reference/esp32s3/user-guide-devkitc-1>
-        ESP32-S3-DevKitM-1 <../hw-reference/esp32s3/user-guide-devkitm-1>
+        ESP32-S3-DevKitC-1 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitc-1/index.html>
+        ESP32-S3-DevKitM-1 <https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitm-1/index.html>
 
 .. only:: esp32c2
 
diff --git a/docs/en/get-started/start-project.rst b/docs/en/get-started/start-project.rst
index 3ec97059def..7b5148ea6a1 100644
--- a/docs/en/get-started/start-project.rst
+++ b/docs/en/get-started/start-project.rst
@@ -160,7 +160,7 @@ With some Linux distributions, you may get the error message similar to ``Could
 Python Compatibility
 ~~~~~~~~~~~~~~~~~~~~
 
-ESP-IDF supports Python 3.8 or newer. It is recommended to upgrade your operating system to a recent version satisfying this requirement. Other options include the installation of Python from `sources <https://www.python.org/downloads/>`_ or the use of a Python version management system such as `pyenv <https://github.com/pyenv/pyenv>`_.
+ESP-IDF supports Python 3.9 or newer. It is recommended to upgrade your operating system to a recent version satisfying this requirement. Other options include the installation of Python from `sources <https://www.python.org/downloads/>`_ or the use of a Python version management system such as `pyenv <https://github.com/pyenv/pyenv>`_.
 
 .. only:: esp32 or esp32s2 or esp32s3
 
diff --git a/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst b/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst
deleted file mode 100644
index e0500316264..00000000000
--- a/docs/en/hw-reference/esp32/user-guide-devkitm-1.rst
+++ /dev/null
@@ -1,335 +0,0 @@
-===============
-ESP32-DevKitM-1
-===============
-
-:link_to_translation:`zh_CN:[中文]`
-
-This user guide will help you get started with ESP32-DevKitM-1 and will also provide more in-depth information.
-
-ESP32-DevKitM-1 is an ESP32-MINI-1/1U-based development board produced by Espressif. Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. Users can either connect peripherals with jumper wires or mount ESP32-DevKitM-1 on a breadboard.
-
-
-+---------------------------+-------------------------------+
-| |ESP32-DevKitM-1 - front| | |ESP32-DevKitM-1 - isometric| |
-+---------------------------+-------------------------------+
-|  ESP32-DevKitM-1 - front  |  ESP32-DevKitM-1 - isometric  |
-+---------------------------+-------------------------------+
-
-.. |ESP32-DevKitM-1 - front| image:: ../../../_static/esp32-DevKitM-1-front.png
-
-.. |ESP32-DevKitM-1 - isometric| image:: ../../../_static/esp32-DevKitM-1-isometric.png
-
-
-The document consists of the following major sections:
-
-- `Getting started`_: Provides an overview of the ESP32-DevKitM-1 and hardware/software setup instructions to get started.
-- `Hardware reference`_: Provides more detailed information about the ESP32-DevKitM-1's hardware.
-- `Related Documents`_: Gives links to related documentation.
-
-
-Getting Started
-===============
-
-This section describes how to get started with ESP32-DevKitM-1. It begins with a few introductory sections about the ESP32-DevKitM-1, then Section `Start Application Development`_ provides instructions on how to do the initial hardware setup and then how to flash firmware onto the ESP32-DevKitM-1.
-
-
-Overview
---------
-
-This is a small and convenient development board that features:
-
-- `ESP32-MINI-1, or ESP32-MINI-1U module <https://www.espressif.com/sites/default/files/documentation/esp32-mini-1_datasheet_en.pdf>`_
-- USB-to-serial programming interface that also provides power supply for the board
-- pin headers
-- pushbuttons for reset and activation of Firmware Download mode
-- a few other components
-
-
-Contents and Packaging
-----------------------
-
-Retail Orders
-^^^^^^^^^^^^^
-
-If you order a few samples, each ESP32-DevKitM-1 comes in an individual package in either antistatic bag or any packaging depending on your retailer.
-
-For retail orders, please go to https://www.espressif.com/en/contact-us/get-samples.
-
-
-Wholesale Orders
-^^^^^^^^^^^^^^^^
-
-If you order in bulk, the boards come in large cardboard boxes.
-
-For wholesale orders, please go to https://www.espressif.com/en/contact-us/sales-questions.
-
-
-Description of Components
--------------------------
-
-The following figure and the table below describe the key components, interfaces and controls of the ESP32-DevKitM-1 board. We take the board with a ESP32-MINI-1 module as an example in the following sections.
-
-
-.. figure:: ../../../_static/esp32-devkitm-1-v1-annotated-photo.png
-    :align: center
-    :alt: ESP32-DevKitM-1 - front
-    :figclass: align-center
-
-    ESP32-DevKitM-1 - front
-
-
-.. list-table::
-    :widths: 25 75
-    :header-rows: 1
-
-    * - Key Component
-      - Description
-    * - On-board module
-      - ESP32-MINI-1 module or ESP32-MINI-1U module. ESP32-MINI-1 comes with an on-board PCB antenna. ESP32-MINI-1U comes with an external antenna connector. The two modules both have a 4 MB flash in chip package. For details, please see `ESP32-MINI-1 & ESP32-MINI-1U Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-mini-1_datasheet_en.pdf>`_.
-    * - 5 V to 3.3 V LDO
-      - Power regulator converts 5 V to 3.3 V.
-    * - Boot Button
-      - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port.
-    * - Reset Button
-      - Reset Button
-    * - Micro-USB Port
-      - USB interface. Power supply for the board as well as the communication interface between a computer and the ESP32 chip.
-    * - USB-to-UART Bridge
-      - Single USB-UART bridge chip provides transfer rates up to 3 Mbps.
-    * - 3.3 V Power On LED
-      - Turns on when the USB is connected to the board. For details, please see the schematics in `Related Documents`_.
-    * - I/O Connector
-      - All available GPIO pins (except for the SPI bus for flash) are broken out to the pin headers on the board. Users can program ESP32 chip to enable multiple functions.
-
-
-Start Application Development
------------------------------
-
-Before powering up your ESP32-DevKitM-1, please make sure that it is in good condition with no obvious signs of damage.
-
-
-Required Hardware
-^^^^^^^^^^^^^^^^^
-
-- ESP32-DevKitM-1
-- USB 2.0 cable (Standard-A to Micro-B)
-- Computer running Windows, Linux, or macOS
-
-
-Software Setup
-^^^^^^^^^^^^^^
-
-Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example onto your ESP32-DevKitM-1.
-
-.. attention::
-
-    ESP32-DevKitM-1 boards manufactured before December 2, 2021 have a single core module installed. To verify what module you have, please check module marking information in `PCN-2021-021 <https://www.espressif.com/sites/default/files/pcn_downloads/PCN-2021-021%20ESP32-U4WDH%20%E5%8D%87%E7%BA%A7%E4%B8%BA%E5%8F%8C%E6%A0%B8%E5%A4%84%E7%90%86%E5%99%A8%E4%BA%A7%E5%93%81.pdf>`_ . If your board has a single core module installed, please enable single core mode (:ref:`CONFIG_FREERTOS_UNICORE`) in :ref:`menuconfig <get-started-configure>` before flashing your applications.
-
-
-Hardware Reference
-==================
-
-Block Diagram
--------------
-
-A block diagram below shows the components of ESP32-DevKitM-1 and their interconnections.
-
-.. figure:: ../../../_static/esp32-DevKitM-1_v1_SystemBlock.png
-    :align: center
-    :alt: ESP32-DevKitM-1
-    :figclass: align-center
-
-    ESP32-DevKitM-1
-
-
-Power Source Select
--------------------
-
-There are three mutually exclusive ways to provide power to the board:
-
-* Micro USB port, default power supply
-* 5V and GND header pins
-* 3V3 and GND header pins
-
-.. warning::
-
-    - The power supply must be provided using **one and only one of the options above**, otherwise the board and/or the power supply source can be damaged.
-    - Power supply by micro USB port is recommended.
-
-
-Pin Descriptions
-----------------
-
-The table below provides the Name and Function of pins on both sides of the board. For peripheral pin configurations, please refer to `ESP32 Datasheet`_.
-
-.. list-table::
-   :header-rows: 1
-   :widths: 10 12 12 66
-
-
-   * - No.
-     - Name
-     - Type [1]_
-     - Function
-   * - 1
-     - GND
-     - P
-     - Ground
-   * - 2
-     - 3V3
-     - P
-     - 3.3 V power supply
-   * - 3
-     - I36
-     - I
-     - GPIO36, ADC1_CH0, RTC_GPIO0
-   * - 4
-     - I37
-     - I
-     - GPIO37, ADC1_CH1, RTC_GPIO1
-   * - 5
-     - I38
-     - I
-     - GPIO38, ADC1_CH2, RTC_GPIO2
-   * - 6
-     - I39
-     - I
-     - GPIO39, ADC1_CH3, RTC_GPIO3
-   * - 7
-     - RST
-     - I
-     - Reset; High: enable; Low: powers off
-   * - 8
-     - I34
-     - I
-     - GPIO34, ADC1_CH6, RTC_GPIO4
-   * - 9
-     - I35
-     - I
-     - GPIO35, ADC1_CH7, RTC_GPIO5
-   * - 10
-     - IO32
-     - I/O
-     - GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4, TOUCH9, RTC_GPIO9
-   * - 11
-     - IO33
-     - I/O
-     - GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output), ADC1_CH5, TOUCH8, RTC_GPIO8
-   * - 12
-     - IO25
-     - I/O
-     - GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0
-   * - 13
-     - IO26
-     - I/O
-     - GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1
-   * - 14
-     - IO27
-     - I/O
-     - GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV
-   * - 15
-     - IO14
-     - I/O
-     - GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK, HS2_CLK, SD_CLK, EMAC_TXD2
-   * - 16
-     - 5V
-     - P
-     - 5 V power supply
-   * - 17
-     - IO12
-     - I/O
-     - GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI [2]_, HSPIQ, HS2_DATA2, SD_DATA2, EMAC_TXD3
-   * - 18
-     - IO13
-     - I/O
-     - GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3, SD_DATA3, EMAC_RX_ER
-   * - 19
-     - IO15
-     - I/O
-     - GPIO15, ADC2_CH3, TOUCH3, RTC_GPIO13, MTDO [2]_, HSPICS0, HS2_CMD, SD_CMD, EMAC_RXD3
-   * - 20
-     - IO2
-     - I/O
-     - GPIO2 [2]_, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0, SD_DATA0
-   * - 21
-     - IO0
-     - I/O
-     - GPIO0 [2]_, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK
-   * - 22
-     - IO4
-     - I/O
-     - GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1, SD_DATA1, EMAC_TX_ER
-   * - 23
-     - IO9
-     - I/O
-     - GPIO9, HS1_DATA2, U1RXD, SD_DATA2
-   * - 24
-     - IO10
-     - I/O
-     - GPIO10, HS1_DATA3, U1TXD, SD_DATA3
-   * - 25
-     - IO5
-     - I/O
-     - GPIO5 [2]_, HS1_DATA6, VSPICS0, EMAC_RX_CLK
-   * - 26
-     - IO18
-     - I/O
-     - GPIO18, HS1_DATA7, VSPICLK
-   * - 27
-     - IO23
-     - I/O
-     - GPIO23, HS1_STROBE, VSPID
-   * - 28
-     - IO19
-     - I/O
-     - GPIO19, VSPIQ, U0CTS, EMAC_TXD0
-   * - 29
-     - IO22
-     - I/O
-     - GPIO22, VSPIWP, U0RTS, EMAC_TXD1
-   * - 30
-     - IO21
-     - I/O
-     - GPIO21, VSPIHD, EMAC_TX_EN
-   * - 31
-     - TXD0
-     - I/O
-     - GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2
-   * - 32
-     - RXD0
-     - I/O
-     - GPIO3, U0RXD, CLK_OUT2
-
-.. [1] P: Power supply; I: Input; O: Output.
-.. [2] MTDI, GPIO0, GPIO2, MTDO, and GPIO5 are strapping pins. These pins are used to control several chip functions depending on binary voltage values applied to the pins during chip power-up or system reset. For description and application of the strapping pins, please refer to `ESP32 Datasheet`_ > Section *Strapping Pins*.
-
-
-Pin Layout
-^^^^^^^^^^
-
-.. figure:: ../../../_static/ESP32_DevKitM-1_pinlayout.png
-    :align: center
-    :scale: 43%
-    :alt: ESP32-DevKitM-1 (click to enlarge)
-    :figclass: align-center
-
-    ESP32-DevKitM-1 (click to enlarge)
-
-
-Hardware Revision Details
-=========================
-
-No previous versions available.
-
-
-Related Documents
-=================
-
-* `ESP32-MINI-1 & ESP32-MINI-1U Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-mini-1_datasheet_en.pdf>`_ (PDF)
-* `ESP32-DevKitM-1 Schematics <https://dl.espressif.com/dl/schematics/SCH_ESP32-DEVKITM-1_V1_20200910A.pdf>`_ (PDF)
-* `ESP32-DevKitM-1 PCB layout <https://dl.espressif.com/dl/schematics/PCB_ESP32-DevKitM-1_V1_20200910AE.pdf>`_ (PDF)
-* `ESP32-DevKitM-1 layout <https://dl.espressif.com/dl/schematics/ESP32-DevKitM-1_V1.dxf>`_ (DXF) - You can view it with `Autodesk Viewer <https://viewer.autodesk.com/>`_ online
-* `ESP32 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ (PDF)
-* `ESP Product Selector <https://products.espressif.com/#/product-selector?names=>`_
-
-For other design documentation for the board, please contact us at sales@espressif.com.
diff --git a/docs/en/hw-reference/esp32s2/user-guide-saola-1-v1.2.rst b/docs/en/hw-reference/esp32s2/user-guide-saola-1-v1.2.rst
deleted file mode 100644
index 7e24b7fcba7..00000000000
--- a/docs/en/hw-reference/esp32s2/user-guide-saola-1-v1.2.rst
+++ /dev/null
@@ -1,262 +0,0 @@
-================
-ESP32-S2-Saola-1
-================
-
-:link_to_translation:`zh_CN:[中文]`
-
-This user guide provides information on ESP32-S2-Saola-1, a small-sized `ESP32-S2 Datasheet`_ based development board produced by Espressif.
-
-.. figure:: ../../../_static/esp32-s2-saola-1-v1.2-isometric.png
-    :align: center
-    :alt: ESP32-S2-Saola-1
-    :figclass: align-center
-
-    ESP32-S2-Saola-1
-
-The document consists of the following major sections:
-
-- `Getting started`_: Provides an overview of the ESP32-S2-Saola-1 and hardware/software setup instructions to get started.
-- `Hardware reference`_: Provides more detailed information about the ESP32-S2-Saola-1's hardware.
-- `Hardware Revision Details`_: Revision history, known issues, and links to user guides for previous versions (if any) of ESP32-S2-Saola-1.
-- `Related Documents`_: Gives links to related documentation.
-
-
-Getting Started
-===============
-
-This section describes how to get started with ESP32-S2-Saola-1. It begins with a few introductory sections about the ESP32-S2-Saola-1, then Section `Start Application Development`_ provides instructions on how to get the ESP32-S2-Saola-1 ready and flash firmware into it.
-
-
-Overview
---------
-
-ESP32-S2-Saola-1 is a small-sized ESP32-S2 based development board produced by Espressif. Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S2-Saola-1 on a breadboard.
-
-To cover a wide range of users' needs, ESP32-S2-Saola-1 supports:
-
-- `ESP32-S2-WROVER <https://www.espressif.com/sites/default/files/documentation/esp32-s2-wrover_esp32-s2-wrover-i_datasheet_en.pdf>`_
-- `ESP32-S2-WROVER-I <https://www.espressif.com/sites/default/files/documentation/esp32-s2-wrover_esp32-s2-wrover-i_datasheet_en.pdf>`_
-- `ESP32-S2-WROOM <https://www.espressif.com/sites/default/files/documentation/esp32-s2-wroom_esp32-s2-wroom-i_datasheet_en.pdf>`_
-- `ESP32-S2-WROOM-I <https://www.espressif.com/sites/default/files/documentation/esp32-s2-wroom_esp32-s2-wroom-i_datasheet_en.pdf>`_
-
-In this guide, we take ESP32-S2-Saola-1 equipped with ESP32-S2-WROVER as an example.
-
-
-Contents and Packaging
-----------------------
-
-Retail Orders
-^^^^^^^^^^^^^
-
-If you order a few samples, each ESP32-S2-Saola-1 comes in an individual package in either antistatic bag or any packaging depending on your retailer.
-
-For retail orders, please go to https://www.espressif.com/en/contact-us/get-samples.
-
-
-Wholesale Orders
-^^^^^^^^^^^^^^^^
-
-If you order in bulk, the boards come in large cardboard boxes.
-
-For wholesale orders, please go to https://www.espressif.com/en/contact-us/sales-questions.
-
-
-Description of Components
--------------------------
-
-.. _user-guide-saola-1-v1.2-board-front:
-
-.. figure:: ../../../_static/esp32-s2-saola-1-v1.2-annotated-photo.png
-    :align: center
-    :alt: ESP32-S2-Saola-1 - front/back
-    :figclass: align-center
-
-    ESP32-S2-Saola-1 - front
-
-The key components of the board are described in a clockwise direction.
-
-.. list-table::
-   :widths: 30 70
-   :header-rows: 1
-
-   * - Key Component
-     - Description
-   * - ESP32-S2-WROVER
-     - ESP32-S2-WROVER is a powerful, generic Wi-Fi MCU module that integrates ESP32-S2. It has a PCB antenna, a 4 MB external SPI flash and an additional 2 MB PSRAM.
-   * - Pin Headers
-     - All available GPIO pins (except for the SPI bus for flash and PSRAM) are broken out to the pin headers on the board. Users can program ESP32-S2 chip to enable multiple functions such as SPI, I2S, UART, I2C, touch sensors, PWM etc.
-   * - 3.3 V Power On LED
-     - Turns on when the USB power is connected to the board.
-   * - USB-to-UART Bridge
-     - Single USB-UART bridge chip provides transfer rates up to 3 Mbps.
-   * - Reset Button
-     - Reset button.
-   * - Micro-USB Port
-     - USB interface. Power supply for the board as well as the communication interface between a computer and the ESP32-S2 chip.
-   * - Boot Button
-     - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port.
-   * - RGB LED
-     - Addressable RGB LED (WS2812), driven by GPIO18.
-
-
-Start Application Development
------------------------------
-
-Before powering up your ESP32-S2-Saola-1, please make sure that it is in good condition with no obvious signs of damage.
-
-
-Required Hardware
-^^^^^^^^^^^^^^^^^
-
-- ESP32-S2-Saola-1
-- USB 2.0 cable (Standard-A to Micro-B)
-- Computer running Windows, Linux, or macOS
-
-.. note::
-
-  Be sure to use an appropriate USB cable. Some cables are for charging only and do not provide the needed data lines nor work for programming the boards.
-
-
-Software Setup
-^^^^^^^^^^^^^^
-
-Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example into your ESP32-S2-Saola-1.
-
-.. note::
-
-    ESP32-S2 series of chips only supports ESP-IDF master or version v4.2 and higher.
-
-
-Hardware Reference
-==================
-
-Block Diagram
--------------
-
-A block diagram below shows the components of ESP32-S2-Saola-1 and their interconnections.
-
-.. figure:: ../../../_static/esp32-s2-saola-1-v1.2-block-diags.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S2-Saola-1 (click to enlarge)
-    :figclass: align-center
-
-    ESP32-S2-Saola-1 (click to enlarge)
-
-
-Power Supply Options
-^^^^^^^^^^^^^^^^^^^^
-
-There are three mutually exclusive ways to provide power to the board:
-
-- Micro-USB port, default power supply
-- 5V and GND pin headers
-- 3V3 and GND pin headers
-
-It is recommended to use the first option: Micro-USB Port.
-
-
-Header Block
-------------
-
-The two tables below provide the **Name** and **Function** of the pin headers on both sides of the board (J2 and J3). The pin header names are shown in :ref:`user-guide-saola-1-v1.2-board-front`. The numbering is the same as in the `ESP32-S2-Saola-1 Schematics`_ (PDF).
-
-
-J2
-^^^
-
-===  ====  ==========  ======================================
-No.  Name  Type [#]_    Function
-===  ====  ==========  ======================================
-1    3V3    P           3.3 V power supply
-2    IO0    I/O         GPIO0, Boot
-3    IO1    I/O         GPIO1, ADC1_CH0, TOUCH_CH1
-4    IO2    I/O         GPIO2, ADC1_CH1, TOUCH_CH2
-5    IO3    I/O         GPIO3, ADC1_CH2, TOUCH_CH3
-6    IO4    I/O         GPIO4, ADC1_CH3, TOUCH_CH4
-7    IO5    I/O         GPIO5, ADC1_CH4, TOUCH_CH5
-8    IO6    I/O         GPIO6, ADC1_CH5, TOUCH_CH6
-9    IO7    I/O         GPIO7, ADC1_CH6, TOUCH_CH7
-10   IO8    I/O         GPIO8, ADC1_CH7, TOUCH_CH8
-11   IO9    I/O         GPIO9, ADC1_CH8, TOUCH_CH9
-12   IO10   I/O         GPIO10, ADC1_CH9, TOUCH_CH10
-13   IO11   I/O         GPIO11, ADC2_CH0, TOUCH_CH11
-14   IO12   I/O         GPIO12, ADC2_CH1, TOUCH_CH12
-15   IO13   I/O         GPIO13, ADC2_CH2, TOUCH_CH13
-16   IO14   I/O         GPIO14, ADC2_CH3, TOUCH_CH14
-17   IO15   I/O         GPIO15, ADC2_CH4, XTAL_32K_P
-18   IO16   I/O         GPIO16, ADC2_CH5, XTAL_32K_N
-19   IO17   I/O         GPIO17, ADC2_CH6, DAC_1
-20   5V0    P           5 V power supply
-21   GND    G           Ground
-===  ====  ==========  ======================================
-
-
-J3
-^^^
-
-===  ====  =====  ====================================
-No.  Name  Type   Function
-===  ====  =====  ====================================
-1    GND   G      Ground
-2    RST   I      CHIP_PU, Reset
-3    IO46  I      GPIO46
-4    IO45  I/O    GPIO45
-5    IO44  I/O    GPIO44, U0RXD
-6    IO43  I/O    GPIO43, U0TXD
-7    IO42  I/O    GPIO42, MTMS
-8    IO41  I/O    GPIO41, MTDI
-9    IO40  I/O    GPIO40, MTDO
-10   IO39  I/O    GPIO39, MTCK
-11   IO38  I/O    GPIO38
-12   IO37  I/O    GPIO37
-13   IO36  I/O    GPIO36
-14   IO35  I/O    GPIO35
-16   IO34  I/O    GPIO34
-17   IO33  I/O    GPIO33
-17   IO26  I/O    GPIO26
-18   IO21  I/O    GPIO21
-19   IO20  I/O    GPIO20, ADC2_CH9, USB_D+
-20   IO19  I/O    GPIO19, ADC2_CH8, USB_D-
-21   IO18  I/O    GPIO18, ADC2_CH7, DAC_2, RGB LED
-===  ====  =====  ====================================
-
-.. [#] P: Power supply; I: Input; O: Output; T: High impedance.
-
-
-Pin Layout
-^^^^^^^^^^^
-
-.. figure:: ../../../_static/esp32-s2_saola1-pinout.jpg
-    :align: center
-    :scale: 45%
-    :alt: ESP32-S2-Saola-1 (click to enlarge)
-    :figclass: align-center
-
-    ESP32-S2 Saola-1 Pin Layout (click to enlarge)
-
-
-Hardware Revision Details
-=========================
-
-This is the first revision of this board released.
-
-
-Related Documents
-=================
-
-* `ESP32-S2-Saola-1 Schematics`_ (PDF)
-* `ESP32-S2-Saola-1 Dimensions`_ (PDF)
-* `ESP32-S2 Datasheet`_ (PDF)
-* `ESP32-S2-WROVER and ESP32-S2-WROVER-I Datasheet`_ (PDF)
-* `ESP32-S2-WROOM and ESP32-S2-WROOM-I Datasheet`_ (PDF)
-* `ESP Product Selector`_
-
-For other design documentation for the board, please contact us at `sales@espressif.com <sales@espressif.com>`_.
-
-.. _ESP32-S2-Saola-1 Schematics: https://dl.espressif.com/dl/schematics/ESP32-S2-SAOLA-1_V1.1_schematics.pdf
-.. _ESP32-S2-Saola-1 Dimensions: https://dl.espressif.com/dl/schematics/ESP32-S2-Saola-1_V1.2_Dimensions.pdf
-.. _ESP32-S2 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf
-.. _ESP32-S2-WROVER and ESP32-S2-WROVER-I Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2-wrover_esp32-s2-wrover-i_datasheet_en.pdf
-.. _ESP32-S2-WROOM and ESP32-S2-WROOM-I Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2-wroom_esp32-s2-wroom-i_datasheet_en.pdf
-.. _ESP Product Selector: https://products.espressif.com/#/product-selector?names=
diff --git a/docs/en/hw-reference/esp32s3/user-guide-devkitc-1-v1.0.rst b/docs/en/hw-reference/esp32s3/user-guide-devkitc-1-v1.0.rst
deleted file mode 100644
index ca62c3f1c1c..00000000000
--- a/docs/en/hw-reference/esp32s3/user-guide-devkitc-1-v1.0.rst
+++ /dev/null
@@ -1,320 +0,0 @@
-==================
-ESP32-S3-DevKitC-1
-==================
-
-:link_to_translation:`zh_CN:[中文]`
-
-The latest version: :doc:`user-guide-devkitc-1`
-
-This user guide will help you get started with ESP32-S3-DevKitC-1 and will also provide more in-depth information.
-
-The ESP32-S3-DevKitC-1 is an entry-level development board equipped with ESP32-S3-WROOM-1, ESP32-S3-WROOM-1U, or ESP32-S3-WROOM-2, a general-purpose Wi-Fi + Bluetooth® Low Energy MCU module that integrates complete Wi-Fi and Bluetooth Low Energy functions.
-
-Most of the I/O pins on the module are broken out to the pin headers on both sides of this board for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S3-DevKitC-1 on a breadboard.
-
-.. figure:: ../../../_static/esp32-s3-devkitc-1-v1-isometric.png
-    :align: center
-    :alt: ESP32-S3-DevKitC-1 with ESP32-S3-WROOM-1 Module
-
-    ESP32-S3-DevKitC-1 with ESP32-S3-WROOM-1 Module
-
-
-The document consists of the following major sections:
-
-- `Getting started`_: Overview of the board and hardware/software setup instructions to get started.
-- `Hardware Reference`_: More detailed information about the board's hardware.
-- `Hardware Revision Details`_: Revision history, known issues, and links to user guides for previous versions (if any) of the board.
-- `Related Documents`_: Links to related documentation.
-
-
-Getting Started
-===============
-
-This section provides a brief introduction of ESP32-S3-DevKitC-1, instructions on how to do the initial hardware setup and how to flash firmware onto it.
-
-
-Description of Components
--------------------------
-
-.. _user-guide-s3-devkitc-1-v1-board-front:
-
-.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png
-    :align: center
-    :alt: ESP32-S3-DevKitC-1 - front
-
-    ESP32-S3-DevKitC-1 - front
-
-The key components of the board are described in a counter-clockwise direction.
-
-.. list-table::
-   :widths: 30 70
-   :header-rows: 1
-
-   * - Key Component
-     - Description
-   * - ESP32-S3-WROOM-1/1U/2
-     - ESP32-S3-WROOM-1, ESP32-S3-WROOM-1U, and ESP32-S3-WROOM-2 are powerful, generic Wi-Fi + Bluetooth Low Energy MCU modules that have a rich set of peripherals. They provide acceleration for neural network computing and signal processing workloads. ESP32-S3-WROOM-1 and ESP32-S3-WROOM-2 comes with a PCB antenna. ESP32-S3-WROOM-1U comes with an external antenna connector.
-   * - 5 V to 3.3 V LDO
-     - Power regulator that converts a 5 V supply into a 3.3 V output.
-   * - Pin Headers
-     - All available GPIO pins (except for the SPI bus for flash) are broken out to the pin headers on the board for easy interfacing and programming. For details, please see :ref:`user-guide-s3-devkitc-1-v1-header-blocks`.
-   * - USB-to-UART Port
-     - A Micro-USB port used for power supply to the board, for flashing applications to the chip, as well as for communication with the chip via the on-board USB-to-UART bridge.
-   * - Boot Button
-     - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port.
-   * - Reset Button
-     - Press this button to restart the system.
-   * - ESP32-S3 USB Port
-     - ESP32-S3 full-speed USB OTG interface, compliant with the USB 1.1 specification. The interface is used for power supply to the board, for flashing applications to the chip, for communication with the chip using USB 1.1 protocols, as well as for JTAG debugging.
-   * - USB-to-UART Bridge
-     - Single USB-to-UART bridge chip provides transfer rates up to 3 Mbps.
-   * - RGB LED
-     - Addressable RGB LED, driven by GPIO48.
-   * - 3.3 V Power On LED
-     - Turns on when the USB power is connected to the board.
-
-.. note::
-
-    For boards with Octal SPI flash/PSRAM memory embedded ESP32-S3-WROOM-1/1U modules, and boards with ESP32-S3-WROOM-2 modules, the pins GPIO35, GPIO36 and GPIO37 are used for the internal communication between ESP32-S3 and SPI flash/PSRAM memory, thus not available for external use.
-
-
-Start Application Development
------------------------------
-
-Before powering up your board, please make sure that it is in good condition with no obvious signs of damage.
-
-
-Required Hardware
-^^^^^^^^^^^^^^^^^
-
-- ESP32-S3-DevKitC-1
-- USB 2.0 cable (Standard-A to Micro-B)
-- Computer running Windows, Linux, or macOS
-
-.. note::
-
-  Be sure to use an appropriate USB cable. Some cables are for charging only and do not provide the needed data lines nor work for programming the boards.
-
-
-Hardware Setup
-^^^^^^^^^^^^^^
-
-Connect the board with the computer using **USB-to-UART Port**. Connection using **ESP32-S3 USB Port** is not fully implemented in software. In subsequent steps, **USB-to-UART Port** will be used by default.
-
-
-Software Setup
-^^^^^^^^^^^^^^
-
-Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example onto your board.
-
-
-Contents and Packaging
-----------------------
-
-Ordering Information
-^^^^^^^^^^^^^^^^^^^^
-
-The development board has a variety of variants to choose from, as shown in the table below.
-
-.. list-table::
-   :widths: 28 29 19 17 15
-   :header-rows: 1
-
-   * - Ordering Code
-     - Module Integrated
-     - Flash
-     - PSRAM
-     - SPI Voltage
-   * - ESP32-S3-DevKitC-1-N8
-     - ESP32-S3-WROOM-1-N8
-     - 8 MB QD
-     - —
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N8R2
-     - ESP32-S3-WROOM-1-N8R2
-     - 8 MB QD
-     - 2 MB QD
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N8R8
-     - ESP32-S3-WROOM-1-N8R8
-     - 8 MB QD
-     - 8 MB OT
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N16R8V
-     - ESP32-S3-WROOM-2-N16R8V
-     - 16 MB OT
-     - 8 MB OT
-     - 1.8 V
-   * - ESP32-S3-DevKitC-1-N32R8V
-     - ESP32-S3-WROOM-2-N32R8V
-     - 32 MB OT
-     - 8 MB OT
-     - 1.8 V
-   * - ESP32-S3-DevKitC-1U-N8
-     - ESP32-S3-WROOM-1U-N8
-     - 8 MB QD
-     - —
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1U-N8R2
-     - ESP32-S3-WROOM-1U-N8R2
-     - 8 MB QD
-     - 2 MB QD
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1U-N8R8
-     - ESP32-S3-WROOM-1U-N8R8
-     - 8 MB QD
-     - 8 MB OT
-     - 3.3 V
-
-.. note::
-
-  In the table above, QD stands for Quad SPI and OT stands for Octal SPI.
-
-
-Retail Orders
-^^^^^^^^^^^^^
-
-If you order a few samples, each board comes in an individual package in either antistatic bag or any packaging depending on your retailer.
-
-For retail orders, please go to https://www.espressif.com/en/company/contact/buy-a-sample.
-
-
-Wholesale Orders
-^^^^^^^^^^^^^^^^
-
-If you order in bulk, the boards come in large cardboard boxes.
-
-For wholesale orders, please go to https://www.espressif.com/en/contact-us/sales-questions.
-
-
-Hardware Reference
-==================
-
-Block Diagram
--------------
-
-The block diagram below shows the components of ESP32-S3-DevKitC-1 and their interconnections.
-
-.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S3-DevKitC-1 (click to enlarge)
-
-    ESP32-S3-DevKitC-1 (click to enlarge)
-
-
-Power Supply Options
-^^^^^^^^^^^^^^^^^^^^
-
-There are three mutually exclusive ways to provide power to the board:
-
-- USB-to-UART Port and ESP32-S3 USB Port (either one or both), default power supply (recommended)
-- 5V and G (GND) pins
-- 3V3 and G (GND) pins
-
-
-.. _user-guide-s3-devkitc-1-v1-header-blocks:
-
-Header Block
-------------
-
-The two tables below provide the **Name** and **Function** of the pins on both sides of the board (J1 and J3). The pin names are shown in :ref:`user-guide-s3-devkitc-1-v1-board-front`. The numbering is the same as in the `Board Schematic <https://dl.espressif.com/dl/SCH_ESP32-S3-DEVKITC-1_V1_20210312C.pdf>`_ (PDF).
-
-
-J1
-^^^
-
-===  ====  ==========  ===================================
-No.  Name  Type [#]_    Function
-===  ====  ==========  ===================================
-1    3V3   P           3.3 V power supply
-2    3V3   P           3.3 V power supply
-3    RST   I           EN
-4    4     I/O/T       RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
-5    5     I/O/T       RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
-6    6     I/O/T       RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
-7    7     I/O/T       RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
-8    15    I/O/T       RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
-9    16    I/O/T       RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
-10   17    I/O/T       RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
-11   18    I/O/T       RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3
-12   8     I/O/T       RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
-13   3     I/O/T       RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
-14   46    I/O/T       GPIO46
-15   9     I/O/T       RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD
-16   10    I/O/T       RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS0
-17   11    I/O/T       RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID
-18   12    I/O/T       RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK
-19   13    I/O/T       RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ
-20   14    I/O/T       RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP
-21   5V    P           5 V power supply
-22   G     G           Ground
-===  ====  ==========  ===================================
-
-
-J3
-^^^
-
-===  ====  =====  ====================================
-No.  Name  Type   Function
-===  ====  =====  ====================================
-1    G     G      Ground
-2    TX    I/O/T  U0TXD, GPIO43, CLK_OUT1
-3    RX    I/O/T  U0RXD, GPIO44, CLK_OUT2
-4    1     I/O/T  RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
-5    2     I/O/T  RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
-6    42    I/O/T  MTMS, GPIO42
-7    41    I/O/T  MTDI, GPIO41, CLK_OUT1
-8    40    I/O/T  MTDO, GPIO40, CLK_OUT2
-9    39    I/O/T  MTCK, GPIO39, CLK_OUT3, SUBSPICS1
-10   38    I/O/T  GPIO38, FSPIWP, SUBSPIWP
-11   37    I/O/T  SPIDQS, GPIO37, FSPIQ, SUBSPIQ
-12   36    I/O/T  SPIIO7, GPIO36, FSPICLK, SUBSPICLK
-13   35    I/O/T  SPIIO6, GPIO35, FSPID, SUBSPID
-14   0     I/O/T  RTC_GPIO0, GPIO0
-15   45    I/O/T  GPIO45
-16   48    I/O/T  GPIO48, SPICLK_N, SUBSPICLK_N_DIFF, RGB LED
-17   47    I/O/T  GPIO47, SPICLK_P, SUBSPICLK_P_DIFF
-18   21    I/O/T  RTC_GPIO21, GPIO21
-19   20    I/O/T  RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
-20   19    I/O/T  RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
-21   G     G      Ground
-22   G     G      Ground
-===  ====  =====  ====================================
-
-
-.. [#] P: Power supply; I: Input; O: Output; T: High impedance.
-
-
-For description of function names, please refer to `Chip Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf>`_ (PDF).
-
-
-Pin Layout
-^^^^^^^^^^
-
-.. figure:: ../../../_static/ESP32-S3_DevKitC-1_pinlayout.jpg
-    :align: center
-    :scale: 50%
-    :alt: ESP32-S3-DevKitC-1 (click to enlarge)
-
-    ESP32-S3-DevKitC-1 Pin Layout (click to enlarge)
-
-
-Hardware Revision Details
-=========================
-
-This is the first revision of this board released.
-
-
-Related Documents
-=================
-
-- `ESP32-S3 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf>`_ (PDF)
-- `ESP32-S3-WROOM-1 & ESP32-S3-WROOM-1U Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf>`_ (PDF)
-- `ESP32-S3-WROOM-2 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-2_datasheet_en.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 Schematic <https://dl.espressif.com/dl/SCH_ESP32-S3-DEVKITC-1_V1_20210312C.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 PCB layout <https://dl.espressif.com/dl/PCB_ESP32-S3-DevKitC-1_V1_20210312CB.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 Dimensions <https://dl.espressif.com/dl/DXF_ESP32-S3-DevKitC-1_V1_20210312CB.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 Dimensions source file <https://dl.espressif.com/dl/DXF_ESP32-S3-DevKitC-1_V1_20210312CB.dxf>`_ (DXF) - You can view it with `Autodesk Viewer <https://viewer.autodesk.com/>`_ online
-
-For further design documentation for the board, please contact us at `sales@espressif.com <sales@espressif.com>`_.
diff --git a/docs/en/hw-reference/esp32s3/user-guide-devkitc-1.rst b/docs/en/hw-reference/esp32s3/user-guide-devkitc-1.rst
deleted file mode 100644
index 2b7923086eb..00000000000
--- a/docs/en/hw-reference/esp32s3/user-guide-devkitc-1.rst
+++ /dev/null
@@ -1,329 +0,0 @@
-=======================
-ESP32-S3-DevKitC-1 v1.1
-=======================
-
-:link_to_translation:`zh_CN:[中文]`
-
-The older version: :doc:`user-guide-devkitc-1-v1.0`
-
-This user guide will help you get started with ESP32-S3-DevKitC-1 and will also provide more in-depth information.
-
-The ESP32-S3-DevKitC-1 is an entry-level development board equipped with ESP32-S3-WROOM-1, ESP32-S3-WROOM-1U, or ESP32-S3-WROOM-2, a general-purpose Wi-Fi + Bluetooth® Low Energy MCU module that integrates complete Wi-Fi and Bluetooth Low Energy functions.
-
-Most of the I/O pins on the module are broken out to the pin headers on both sides of this board for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S3-DevKitC-1 on a breadboard.
-
-.. figure:: ../../../_static/esp32-s3-devkitc-1-v1.1-isometric.png
-    :align: center
-    :alt: ESP32-S3-DevKitC-1 with ESP32-S3-WROOM-1 Module
-
-    ESP32-S3-DevKitC-1 with ESP32-S3-WROOM-1 Module
-
-
-The document consists of the following major sections:
-
-- `Getting started`_: Overview of the board and hardware/software setup instructions to get started.
-- `Hardware Reference`_: More detailed information about the board's hardware.
-- `Hardware Revision Details`_: Revision history, known issues, and links to user guides for previous versions (if any) of the board.
-- `Related Documents`_: Links to related documentation.
-
-
-Getting Started
-===============
-
-This section provides a brief introduction of ESP32-S3-DevKitC-1, instructions on how to do the initial hardware setup and how to flash firmware onto it.
-
-
-Description of Components
--------------------------
-
-.. _user-guide-s3-devkitc-1-v1.1-board-front:
-
-.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png
-    :align: center
-    :alt: ESP32-S3-DevKitC-1 - front
-
-    ESP32-S3-DevKitC-1 - front
-
-The key components of the board are described in a counter-clockwise direction.
-
-.. list-table::
-   :widths: 30 70
-   :header-rows: 1
-
-   * - Key Component
-     - Description
-   * - ESP32-S3-WROOM-1/1U/2
-     - ESP32-S3-WROOM-1, ESP32-S3-WROOM-1U, and ESP32-S3-WROOM-2 are powerful, generic Wi-Fi + Bluetooth Low Energy MCU modules that have a rich set of peripherals. They provide acceleration for neural network computing and signal processing workloads. ESP32-S3-WROOM-1 and ESP32-S3-WROOM-2 comes with a PCB antenna. ESP32-S3-WROOM-1U comes with an external antenna connector.
-   * - 5 V to 3.3 V LDO
-     - Power regulator that converts a 5 V supply into a 3.3 V output.
-   * - Pin Headers
-     - All available GPIO pins (except for the SPI bus for flash) are broken out to the pin headers on the board for easy interfacing and programming. For details, please see :ref:`user-guide-s3-devkitc-1-v1.1-header-blocks`.
-   * - USB-to-UART Port
-     - A Micro-USB port used for power supply to the board, for flashing applications to the chip, as well as for communication with the chip via the on-board USB-to-UART bridge.
-   * - Boot Button
-     - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port.
-   * - Reset Button
-     - Press this button to restart the system.
-   * - USB Port
-     - ESP32-S3 full-speed USB OTG interface, compliant with the USB 1.1 specification. The interface is used for power supply to the board, for flashing applications to the chip, for communication with the chip using USB 1.1 protocols, as well as for JTAG debugging.
-   * - USB-to-UART Bridge
-     - Single USB-to-UART bridge chip provides transfer rates up to 3 Mbps.
-   * - RGB LED
-     - Addressable RGB LED, driven by GPIO38.
-   * - 3.3 V Power On LED
-     - Turns on when the USB power is connected to the board.
-
-.. note::
-
-    For boards with Octal SPI flash/PSRAM memory embedded ESP32-S3-WROOM-1/1U modules, and boards with ESP32-S3-WROOM-2 modules, the pins GPIO35, GPIO36 and GPIO37 are used for the internal communication between ESP32-S3 and SPI flash/PSRAM memory, thus not available for external use.
-
-
-Start Application Development
------------------------------
-
-Before powering up your board, please make sure that it is in good condition with no obvious signs of damage.
-
-
-Required Hardware
-^^^^^^^^^^^^^^^^^
-
-- ESP32-S3-DevKitC-1
-- USB 2.0 cable (Standard-A to Micro-B)
-- Computer running Windows, Linux, or macOS
-
-.. note::
-
-  Be sure to use an appropriate USB cable. Some cables are for charging only and do not provide the needed data lines nor work for programming the boards.
-
-
-Hardware Setup
-^^^^^^^^^^^^^^
-
-Connect the board with the computer using **USB-to-UART Port** or **ESP32-S3 USB Port**. In subsequent steps, **USB-to-UART Port** will be used by default.
-
-
-Software Setup
-^^^^^^^^^^^^^^
-
-Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example onto your board.
-
-
-Contents and Packaging
-----------------------
-
-Ordering Information
-^^^^^^^^^^^^^^^^^^^^
-
-The development board has a variety of variants to choose from, as shown in the table below.
-
-.. list-table::
-   :widths: 28 29 19 17 15
-   :header-rows: 1
-
-   * - Ordering Code
-     - Module Integrated
-     - Flash
-     - PSRAM
-     - SPI Voltage
-   * - ESP32-S3-DevKitC-1-N8
-     - ESP32-S3-WROOM-1-N8
-     - 8 MB QD
-     - —
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N8R2
-     - ESP32-S3-WROOM-1-N8R2
-     - 8 MB QD
-     - 2 MB QD
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N8R8
-     - ESP32-S3-WROOM-1-N8R8
-     - 8 MB QD
-     - 8 MB OT
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N16R8V
-     - ESP32-S3-WROOM-2-N16R8V
-     - 16 MB OT
-     - 8 MB OT
-     - 1.8 V
-   * - ESP32-S3-DevKitC-1-N32R8V
-     - ESP32-S3-WROOM-2-N32R8V
-     - 32 MB OT
-     - 8 MB OT
-     - 1.8 V
-   * - ESP32-S3-DevKitC-1U-N8
-     - ESP32-S3-WROOM-1U-N8
-     - 8 MB QD
-     - —
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1U-N8R2
-     - ESP32-S3-WROOM-1U-N8R2
-     - 8 MB QD
-     - 2 MB QD
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1U-N8R8
-     - ESP32-S3-WROOM-1U-N8R8
-     - 8 MB QD
-     - 8 MB OT
-     - 3.3 V
-
-.. note::
-
-  In the table above, QD stands for Quad SPI and OT stands for Octal SPI.
-
-
-Retail Orders
-^^^^^^^^^^^^^
-
-If you order a few samples, each board comes in an individual package in either antistatic bag or any packaging depending on your retailer.
-
-For retail orders, please go to https://www.espressif.com/en/contact-us/get-samples.
-
-
-Wholesale Orders
-^^^^^^^^^^^^^^^^
-
-If you order in bulk, the boards come in large cardboard boxes.
-
-For wholesale orders, please go to https://www.espressif.com/en/contact-us/sales-questions.
-
-
-Hardware Reference
-==================
-
-Block Diagram
--------------
-
-The block diagram below shows the components of ESP32-S3-DevKitC-1 and their interconnections.
-
-.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S3-DevKitC-1 (click to enlarge)
-
-    ESP32-S3-DevKitC-1 (click to enlarge)
-
-
-Power Supply Options
-^^^^^^^^^^^^^^^^^^^^
-
-There are three mutually exclusive ways to provide power to the board:
-
-- USB-to-UART Port and ESP32-S3 USB Port (either one or both), default power supply (recommended)
-- 5V and G (GND) pins
-- 3V3 and G (GND) pins
-
-
-.. _user-guide-s3-devkitc-1-v1.1-header-blocks:
-
-Header Block
-------------
-
-The two tables below provide the **Name** and **Function** of the pins on both sides of the board (J1 and J3). The pin names are shown in :ref:`user-guide-s3-devkitc-1-v1.1-board-front`. The numbering is the same as in the `Board Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-S3-DevKitC-1_V1.1_20220413.pdf>`_ (PDF).
-
-
-J1
-^^^
-
-===  ====  ==========  ===================================
-No.  Name  Type [#]_    Function
-===  ====  ==========  ===================================
-1    3V3   P           3.3 V power supply
-2    3V3   P           3.3 V power supply
-3    RST   I           EN
-4    4     I/O/T       RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
-5    5     I/O/T       RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
-6    6     I/O/T       RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
-7    7     I/O/T       RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
-8    15    I/O/T       RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
-9    16    I/O/T       RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
-10   17    I/O/T       RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
-11   18    I/O/T       RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3
-12   8     I/O/T       RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
-13   3     I/O/T       RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
-14   46    I/O/T       GPIO46
-15   9     I/O/T       RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD
-16   10    I/O/T       RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS0
-17   11    I/O/T       RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID
-18   12    I/O/T       RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK
-19   13    I/O/T       RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ
-20   14    I/O/T       RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP
-21   5V    P           5 V power supply
-22   G     G           Ground
-===  ====  ==========  ===================================
-
-
-J3
-^^^
-
-===  ====  =====  ====================================
-No.  Name  Type   Function
-===  ====  =====  ====================================
-1    G     G      Ground
-2    TX    I/O/T  U0TXD, GPIO43, CLK_OUT1
-3    RX    I/O/T  U0RXD, GPIO44, CLK_OUT2
-4    1     I/O/T  RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
-5    2     I/O/T  RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
-6    42    I/O/T  MTMS, GPIO42
-7    41    I/O/T  MTDI, GPIO41, CLK_OUT1
-8    40    I/O/T  MTDO, GPIO40, CLK_OUT2
-9    39    I/O/T  MTCK, GPIO39, CLK_OUT3, SUBSPICS1
-10   38    I/O/T  GPIO38, FSPIWP, SUBSPIWP, RGB LED
-11   37    I/O/T  SPIDQS, GPIO37, FSPIQ, SUBSPIQ
-12   36    I/O/T  SPIIO7, GPIO36, FSPICLK, SUBSPICLK
-13   35    I/O/T  SPIIO6, GPIO35, FSPID, SUBSPID
-14   0     I/O/T  RTC_GPIO0, GPIO0
-15   45    I/O/T  GPIO45
-16   48    I/O/T  GPIO48, SPICLK_N, SUBSPICLK_N_DIFF
-17   47    I/O/T  GPIO47, SPICLK_P, SUBSPICLK_P_DIFF
-18   21    I/O/T  RTC_GPIO21, GPIO21
-19   20    I/O/T  RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
-20   19    I/O/T  RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
-21   G     G      Ground
-22   G     G      Ground
-===  ====  =====  ====================================
-
-
-.. [#] P: Power supply; I: Input; O: Output; T: High impedance.
-
-
-For description of function names, please refer to `ESP32-S3 Series Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf>`_ (PDF).
-
-
-Pin Layout
-^^^^^^^^^^
-
-.. figure:: ../../../_static/ESP32-S3_DevKitC-1_pinlayout_v1.1.jpg
-    :align: center
-    :scale: 50%
-    :alt: ESP32-S3-DevKitC-1 (click to enlarge)
-
-    ESP32-S3-DevKitC-1 Pin Layout (click to enlarge)
-
-
-Hardware Revision Details
-=========================
-
-:doc:`Initial release <user-guide-devkitc-1-v1.0>`
-
-.. note::
-
-    Both the initial and v1.1 versions of ESP32-S3-DevKitC-1 are available on the market. The main difference lies in the GPIO assignment for the RGB LED: the initial version uses GPIO48, whereas v1.1 uses GPIO38.
-
-
-Related Documents
-=================
-
-- `ESP32-S3 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf>`_ (PDF)
-- `ESP32-S3-WROOM-1 & ESP32-S3-WROOM-1U Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf>`_ (PDF)
-- `ESP32-S3-WROOM-2 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-2_datasheet_en.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-S3-DevKitC-1_V1.1_20221130.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 PCB layout <https://dl.espressif.com/dl/schematics/PCB_ESP32-S3-DevKitC-1_V1.1_20220429.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 Dimensions <https://dl.espressif.com/dl/schematics/esp_idf/DXF_ESP32-S3-DevKitC-1_V1.1_20220429.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 Dimensions source file <https://dl.espressif.com/dl/schematics/esp_idf/DXF_ESP32-S3-DevKitC-1_V1.1_20220429.dxf>`_ (DXF) - You can view it with `Autodesk Viewer <https://viewer.autodesk.com/>`_ online
-
-For further design documentation for the board, please contact us at `sales@espressif.com <sales@espressif.com>`_.
-
-.. toctree::
-    :hidden:
-
-    user-guide-devkitc-1-v1.0
diff --git a/docs/en/hw-reference/esp32s3/user-guide-devkitm-1.rst b/docs/en/hw-reference/esp32s3/user-guide-devkitm-1.rst
deleted file mode 100644
index 850cc939d70..00000000000
--- a/docs/en/hw-reference/esp32s3/user-guide-devkitm-1.rst
+++ /dev/null
@@ -1,258 +0,0 @@
-==================
-ESP32-S3-DevKitM-1
-==================
-
-:link_to_translation:`zh_CN:[中文]`
-
-This user guide will help you get started with ESP32-S3-DevKitM-1 and will also provide more in-depth information.
-
-The ESP32-S3-DevKitM-1 is an entry-level development board equipped with either ESP32-S3-MINI-1 or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi and Bluetooth® Low Energy functions.
-
-Most of the I/O pins on the module are broken out to the pin headers on both sides of this board for easy interfacing. Developers can either connect peripherals with jumper wires or mount ESP32-S3-DevKitM-1 on a breadboard.
-
-.. figure:: ../../../_static/esp32-s3-devkitm-1-v1-isometric.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S3-DevKitM-1 with ESP32-S3-MINI-1 Module
-    :figclass: align-center
-
-    ESP32-S3-DevKitM-1 with ESP32-S3-MINI-1 Module
-
-
-The document consists of the following major sections:
-
-- `Getting Started`_: Overview of the board and hardware/software setup instructions to get started.
-- `Hardware Reference`_: More detailed information about the board's hardware.
-- `Related Documents`_: Links to related documentation.
-
-
-Getting Started
-===============
-
-This section provides a brief introduction of ESP32-S3-DevKitM-1, instructions on how to do the initial hardware setup and how to flash firmware onto it.
-
-
-Description of Components
--------------------------
-
-.. _user-guide-s3-devkitm-1-v1-board-front:
-
-.. figure:: ../../../_static/ESP32-S3-DevKitM-1_v1-annotated-photo.png
-    :align: center
-    :alt: ESP32-S3-DevKitM-1 - front
-    :figclass: align-center
-
-    ESP32-S3-DevKitM-1 - front
-
-The key components of the board are described in a counter-clockwise direction, starting from the ESP32-S3-MINI-1/1U module.
-
-.. list-table::
-   :widths: 30 70
-   :header-rows: 1
-
-   * - Key Component
-     - Description
-   * - ESP32-S3-MINI-1/1U
-     - ESP32-S3-MINI-1 and ESP32-S3-MINI-1U are two general-purpose Wi-Fi and Bluetooth Low Energy combo modules that have a rich set of peripherals. ESP32-S3-MINI-1 comes with a PCB antenna. ESP32-S3-MINI-1U comes with an external antenna connector. At the core of the modules is ESP32-S3FN8, a chip equipped with an 8 MB flash. Since flash is packaged in the chip, rather than integrated into the module, ESP32-S3-MINI-1/1U has a smaller package size.
-   * - 5 V to 3.3 V LDO
-     - Power regulator that converts a 5 V supply into a 3.3 V output.
-   * - Pin Headers
-     - All available GPIO pins (except for the SPI bus for flash) are broken out to the pin headers on the board for easy interfacing and programming. For details, please see :ref:`user-guide-s3-devkitm-1-v1-header-blocks`.
-   * - USB-to-UART Port
-     - A Micro-USB port used for power supply to the board, for flashing applications to the chip, as well as for communication with the chip via the on-board USB-to-UART bridge.
-   * - Boot Button
-     - Download button. Holding down **Boot** and then pressing **Reset** initiates Firmware Download mode for downloading firmware through the serial port.
-   * - Reset Button
-     - Press this button to restart ESP32-S3.
-   * - ESP32-S3 USB Port
-     - ESP32-S3 full-speed USB OTG interface, compliant with the USB 1.1 specification. The interface is used for power supply to the board, for flashing applications to the chip, for communication with the chip using USB 1.1 protocols, as well as for JTAG debugging.
-   * - USB-to-UART Bridge
-     - Single USB-to-UART bridge chip provides transfer rates up to 3 Mbps.
-   * - RGB LED
-     - Addressable RGB LED, driven by GPIO48.
-   * - 3.3 V Power On LED
-     - Turns on when the USB power is connected to the board.
-
-
-Start Application Development
------------------------------
-
-Before powering up your board, please make sure that it is in good condition with no obvious signs of damage.
-
-
-Required Hardware
-^^^^^^^^^^^^^^^^^
-
-- ESP32-S3-DevKitM-1
-- USB 2.0 cable (Standard-A to Micro-B)
-- Computer running Windows, Linux, or macOS
-
-.. note::
-
-  Be sure to use an appropriate USB cable. Some cables are for charging only and do not provide the needed data lines nor work for programming the boards.
-
-
-Hardware Setup
-^^^^^^^^^^^^^^
-
-Connect the board with the computer using **USB-to-UART Port** or **ESP32-S3 USB Port**. In subsequent steps, **USB-to-UART Port** will be used by default.
-
-
-Software Setup
-^^^^^^^^^^^^^^
-
-Please proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an application example onto your board.
-
-
-Contents and Packaging
-----------------------
-
-Retail Orders
-^^^^^^^^^^^^^
-
-If you order a few samples, each board comes in an individual package in either antistatic bag or any packaging depending on your retailer.
-
-For retail orders, please go to https://www.espressif.com/en/contact-us/get-samples.
-
-
-Wholesale Orders
-^^^^^^^^^^^^^^^^
-
-If you order in bulk, the boards come in large cardboard boxes.
-
-For wholesale orders, please go to https://www.espressif.com/en/contact-us/sales-questions.
-
-
-Hardware Reference
-==================
-
-Block Diagram
--------------
-
-The block diagram below shows the components of ESP32-S3-DevKitM-1 and their interconnections.
-
-.. figure:: ../../../_static/ESP32-S3-DevKitM-1_v1_SystemBlock.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S3-DevKitM-1 (click to enlarge)
-    :figclass: align-center
-
-    ESP32-S3-DevKitM-1 (click to enlarge)
-
-
-Power Supply Options
-^^^^^^^^^^^^^^^^^^^^
-
-There are three mutually exclusive ways to provide power to the board:
-
-- USB-to-UART Port and ESP32-S3 USB Port (either one or both), default power supply (recommended)
-- 5V and G (GND) pins
-- 3V3 and G (GND) pins
-
-
-.. _user-guide-s3-devkitm-1-v1-header-blocks:
-
-Header Block
-------------
-
-The two tables below provide the **Name** and **Function** of the pins on both sides of the board (J1 and J3). The pin names are shown in :ref:`user-guide-s3-devkitm-1-v1-board-front`. The numbering is the same as in the `Board Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-S3-DEVKITM-1_V1_20210310A.pdf>`_ (PDF).
-
-
-J1
-^^^
-
-===  ====  ==========  ===================================
-No.  Name  Type [#]_    Function
-===  ====  ==========  ===================================
-1    3V3   P           3.3 V power supply
-2    0     I/O/T       RTC_GPIO0, GPIO0
-3    1     I/O/T       RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
-4    2     I/O/T       RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
-5    3     I/O/T       RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
-6    4     I/O/T       RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
-7    5     I/O/T       RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
-8    6     I/O/T       RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
-9    7     I/O/T       RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
-10   8     I/O/T       RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
-11   9     I/O/T       RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD
-12   10    I/O/T       RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS0
-13   11    I/O/T       RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID
-14   12    I/O/T       RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK
-15   13    I/O/T       RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ
-16   14    I/O/T       RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP
-17   15    I/O/T       RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
-18   16    I/O/T       RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
-19   17    I/O/T       RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
-20   18    I/O/T       RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3
-21   5V    P           5 V power supply
-22   G     G           Ground
-===  ====  ==========  ===================================
-
-
-J3
-^^^
-
-===  ====  =====  ====================================
-No.  Name  Type   Function
-===  ====  =====  ====================================
-1    G     G      Ground
-2    RST   I      EN
-3    46    I/O/T  GPIO46
-4    45    I/O/T  GPIO45
-5    RX    I/O/T  U0RXD, GPIO44, CLK_OUT2
-6    TX    I/O/T  U0TXD, GPIO43, CLK_OUT1
-7    42    I/O/T  MTMS, GPIO42
-8    41    I/O/T  MTDI, GPIO41, CLK_OUT1
-9    40    I/O/T  MTDO, GPIO40, CLK_OUT2
-10   39    I/O/T  MTCK, GPIO39, CLK_OUT3, SUBSPICS1
-11   38    I/O/T  GPIO38, FSPIWP, SUBSPIWP
-12   37    I/O/T  SPIDQS, GPIO37, FSPIQ, SUBSPIQ
-13   36    I/O/T  SPIIO7, GPIO36, FSPICLK, SUBSPICLK
-14   35    I/O/T  SPIIO6, GPIO35, FSPID, SUBSPID
-15   34    I/O/T  SPIIO5, GPIO34, FSPICS0, SUBSPICS0
-16   33    I/O/T  SPIIO4, GPIO33, FSPIHD, SUBSPIHD
-17   26    I/O/T  SPICS1, GPIO26
-18   21    I/O/T  RTC_GPIO21, GPIO21
-19   20    I/O/T  RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
-20   19    I/O/T  RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
-21   48    I/O/T  SPICLK_N, GPIO48, SUBSPICLK_N_DIFF, RGB LED
-22   47    I/O/T  SPICLK_P, GPIO47, SUBSPICLK_P_DIFF
-===  ====  =====  ====================================
-
-
-.. [#] P: Power supply; I: Input; O: Output; T: High impedance.
-
-
-
-For description of function names, please refer to `ESP32-S3 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf>`_ (PDF).
-
-
-Pin Layout
-^^^^^^^^^^
-
-.. figure:: ../../../_static/ESP32-S3_DevKitM-1_pinlayout.jpg
-    :align: center
-    :scale: 50%
-    :alt: ESP32-S3-DevKitM-1 (click to enlarge)
-    :figclass: align-center
-
-    ESP32-S3-DevKitM-1 Pin Layout (click to enlarge)
-
-
-Hardware Revision Details
-=========================
-
-This is the first revision of this board released.
-
-
-Related Documents
-=================
-
-- `ESP32-S3 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf>`_ (PDF)
-- `ESP32-S3-MINI-1 & ESP32-S3-MINI-1U Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf>`_ (PDF)
-- `ESP32-S3-DevKitM-1 Schematic <https://dl.espressif.com/dl/schematics/SCH_ESP32-S3-DEVKITM-1_V1_20210310A.pdf>`_ (PDF)
-- `ESP32-S3-DevKitM-1 PCB layout <https://dl.espressif.com/dl/schematics/PCB_ESP32-S3-DevKitM-1_V1_20210310AC.pdf>`_ (PDF)
-- `ESP32-S3-DevKitM-1 Dimensions <https://dl.espressif.com/dl/schematics/DXF_ESP32-S3-DevKitM-1_V1_20210310AC.pdf>`_ (PDF)
-- `ESP32-S3-DevKitM-1 Dimensions source file <https://dl.espressif.com/dl/schematics/DXF_ESP32-S3-DevKitM-1_V1_20210310AC.dxf>`_ (DXF) - You can view it with `Autodesk Viewer <https://viewer.autodesk.com/>`_ online
-
-For further design documentation for the board, please contact us at `sales@espressif.com <sales@espressif.com>`_.
diff --git a/docs/en/libraries-and-frameworks/libs-frameworks.rst b/docs/en/libraries-and-frameworks/libs-frameworks.rst
index 0793fd7726f..5c18c5b1364 100644
--- a/docs/en/libraries-and-frameworks/libs-frameworks.rst
+++ b/docs/en/libraries-and-frameworks/libs-frameworks.rst
@@ -107,4 +107,3 @@ ESP-IDF-CXX
 -----------
 
 `ESP-IDF-CXX <https://github.com/espressif/esp-idf-cxx>`_ contains C++ wrappers for part of ESP-IDF. The focuses are on ease of use, safety, automatic resource management. They also move error checking from runtime to compile time to prevent running failure. There are C++ classes for ESP-Timer, I2C, SPI, GPIO and other peripherals or features of ESP-IDF. ESP-IDF-CXX is available as a component from `ESP Component Registry <https://components.espressif.com/components/espressif/esp-idf-cxx>`__. Please check the project's `README.md <https://github.com/espressif/esp-idf-cxx/blob/main/README.md>`_ for more information.
-
diff --git a/docs/en/migration-guides/release-5.x/5.4/index.rst b/docs/en/migration-guides/release-5.x/5.4/index.rst
index cab9e7ac4ee..f6b85cb5e7e 100644
--- a/docs/en/migration-guides/release-5.x/5.4/index.rst
+++ b/docs/en/migration-guides/release-5.x/5.4/index.rst
@@ -9,3 +9,5 @@ Migration from 5.3 to 5.4
     gcc
     system
     bluetooth-classic
+    storage
+    wifi
diff --git a/docs/en/migration-guides/release-5.x/5.4/storage.rst b/docs/en/migration-guides/release-5.x/5.4/storage.rst
new file mode 100644
index 00000000000..41360c019e6
--- /dev/null
+++ b/docs/en/migration-guides/release-5.x/5.4/storage.rst
@@ -0,0 +1,7 @@
+Storage
+=======
+
+SPI Flash Driver
+^^^^^^^^^^^^^^^^
+
+XMC-C series flash suspend support has been removed. According to feedback from the flash manufacturer, in some situations the XMC-C flash would require a 1ms interval between resume and next command. This is too long for a software request. Based on the above reason, in order to use suspend safely, we decide to remove flash suspend support from XMC-C series. But you can still force enable it via `CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND`. If you have any questions, please contact espressif business support.
diff --git a/docs/en/migration-guides/release-5.x/5.4/system.rst b/docs/en/migration-guides/release-5.x/5.4/system.rst
index e6e0ede0156..f845786e6e4 100644
--- a/docs/en/migration-guides/release-5.x/5.4/system.rst
+++ b/docs/en/migration-guides/release-5.x/5.4/system.rst
@@ -3,11 +3,17 @@ System
 
 :link_to_translation:`zh_CN:[中文]`
 
+ESP-Common
+----------
+
+``__VA_NARG__`` and its related macros have been re-named to avoid naming collisions, use the new name with ``ESP`` pre-fix, e.g. ``ESP_VA_NARG`` instead.
+
 Log
 ---
 
 - `esp_log_buffer_hex` is deprecated, use `ESP_LOG_BUFFER_HEX` instead.
 - `esp_log_buffer_char` is deprecated, use `ESP_LOG_BUFFER_CHAR` instead.
+- The default value for ``CONFIG_LOG_COLORS`` is now set to false. Colors are added on the host side by default in IDF Monitor. If you want to enable colors in the log output for other console monitors, set ``CONFIG_LOG_COLORS`` to true in your project configuration. To disable automatic coloring in IDF Monitor, run the following command: ``idf.py monitor --disable-auto-color``.
 
 ESP ROM
 ---------
diff --git a/docs/en/migration-guides/release-5.x/5.4/wifi.rst b/docs/en/migration-guides/release-5.x/5.4/wifi.rst
new file mode 100644
index 00000000000..ddcc2c49f17
--- /dev/null
+++ b/docs/en/migration-guides/release-5.x/5.4/wifi.rst
@@ -0,0 +1,22 @@
+Wi-Fi
+======
+
+:link_to_translation:`zh_CN:[中文]`
+
+
+Wi-Fi Scan and Connect
+------------------------
+
+    The following types have been modified:
+
+    - :component_file:`esp_wifi/include/esp_wifi_he_types.h`
+
+        - :cpp:struct:`esp_wifi_htc_omc_t`:
+
+            - ``uph_id``, ``ul_pw_headroom``, ``min_tx_pw_flag`` are deprecated.
+
+    - :component_file:`esp_wifi/include/esp_wifi_types_generic.h`
+
+        - :cpp:struct:`wifi_ap_record_t`:
+
+            - The type of ``bandwidth`` has been changed from ``uint8_t`` to ``wifi_bandwidth_t``
diff --git a/docs/en/security/flash-encryption.rst b/docs/en/security/flash-encryption.rst
index 6600c7eba2e..b5c07b2b76b 100644
--- a/docs/en/security/flash-encryption.rst
+++ b/docs/en/security/flash-encryption.rst
@@ -39,7 +39,7 @@ Encrypted Partitions
 
 With flash encryption enabled, the following types of data are encrypted by default:
 
-- :ref:`second-stage-bootloader` (Firmware Bootloader)
+- :ref:`second-stage-bootloader`
 - Partition Table
 - :ref:`nvs_encr_key_partition`
 - Otadata
@@ -175,39 +175,39 @@ Read and write access to eFuse bits is controlled by appropriate fields in the r
 Flash Encryption Process
 ------------------------
 
-Assuming that the eFuse values are in their default states and the firmware bootloader is compiled to support flash encryption, the flash encryption process executes as shown below:
+Assuming that the eFuse values are in their default states and the second stage bootloader is compiled to support flash encryption, the flash encryption process executes as shown below:
 
 .. only:: not SOC_FLASH_ENCRYPTION_XTS_AES
 
-  1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The ROM bootloader loads the firmware bootloader.
+  1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The first stage (ROM) bootloader loads the second stage bootloader.
 
-  2. Firmware bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b0000000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. It also sets the ``FLASH_CRYPT_CONFIG`` eFuse to 0xF. For more information on the flash encryption block, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* > *Flash Encryption Block* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
+  2. Second stage bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b0000000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. It also sets the ``FLASH_CRYPT_CONFIG`` eFuse to 0xF. For more information on the flash encryption block, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* > *Flash Encryption Block* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
 
-  3. Firmware bootloader first checks if a valid key is already present in the eFuse (e.g., burned using espefuse tool), then the process of key generation is skipped and the same key is used for flash encryption process. Otherwise, Firmware bootloader uses RNG (random) module to generate an AES-256 bit key and then writes it into the ``flash_encryption`` eFuse. The key cannot be accessed via software as the write and read protection bits for the ``flash_encryption`` eFuse are set. The flash encryption operations happen entirely by hardware, and the key cannot be accessed via software.
+  3. Second stage bootloader first checks if a valid key is already present in the eFuse (e.g., burned using espefuse tool), then the process of key generation is skipped and the same key is used for flash encryption process. Otherwise, Second stage bootloader uses RNG (random) module to generate an AES-256 bit key and then writes it into the ``flash_encryption`` eFuse. The key cannot be accessed via software as the write and read protection bits for the ``flash_encryption`` eFuse are set. The flash encryption operations happen entirely by hardware, and the key cannot be accessed via software.
 
-  4. Flash encryption block encrypts the flash contents - the firmware bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
+  4. Flash encryption block encrypts the flash contents - the second stage bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
 
-  5. Firmware bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b0000001) to mark the flash contents as encrypted. Odd number of bits is set.
+  5. Second stage bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b0000001) to mark the flash contents as encrypted. Odd number of bits is set.
 
-  6. For :ref:`flash-enc-development-mode`, the firmware bootloader sets only the eFuse bits ``DISABLE_DL_DECRYPT`` and ``DISABLE_DL_CACHE`` to allow the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected.
+  6. For :ref:`flash-enc-development-mode`, the second stage bootloader sets only the eFuse bits ``DISABLE_DL_DECRYPT`` and ``DISABLE_DL_CACHE`` to allow the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected.
 
-  7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets the eFuse bits ``DISABLE_DL_ENCRYPT``, ``DISABLE_DL_DECRYPT``, and ``DISABLE_DL_CACHE`` to 1 to prevent the UART bootloader from decrypting the flash contents. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
+  7. For :ref:`flash-enc-release-mode`, the second stage bootloader sets the eFuse bits ``DISABLE_DL_ENCRYPT``, ``DISABLE_DL_DECRYPT``, and ``DISABLE_DL_CACHE`` to 1 to prevent the UART bootloader from decrypting the flash contents. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
 
-  8. The device is then rebooted to start executing the encrypted image. The firmware bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
+  8. The device is then rebooted to start executing the encrypted image. The second stage bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
 
 .. only:: SOC_FLASH_ENCRYPTION_XTS_AES_256
 
-  1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The ROM bootloader loads the firmware bootloader.
+  1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The first stage (ROM) bootloader loads the second stage bootloader.
 
-  2. Firmware bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. For more information on the flash encryption block, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* > *Auto Encryption Block* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
+  2. Second stage bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. For more information on the flash encryption block, see *{IDF_TARGET_NAME} Technical Reference Manual* > *eFuse Controller (eFuse)* > *Auto Encryption Block* [`PDF <{IDF_TARGET_TRM_EN_URL}#efuse>`__].
 
-  3. Firmware bootloader first checks if a valid key is already present in the eFuse (e.g., burned using espefuse tool) then the process of key generation is skipped and the same key is used for flash encryption process. Otherwise, Firmware bootloader uses RNG (random) module to generate an 256 bit or 512 bit key, depending on the value of :ref:`Size of generated XTS-AES key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`, and then writes it into respectively one or two `BLOCK_KEYN` eFuses. The software also updates the ``KEY_PURPOSE_N`` for the blocks where the keys were stored. The key cannot be accessed via software as the write and read protection bits for one or two `BLOCK_KEYN` eFuses are set. ``KEY_PURPOSE_N`` field is write-protected as well. The flash encryption operations happen entirely by hardware, and the key cannot be accessed via software.
+  3. Second stage bootloader first checks if a valid key is already present in the eFuse (e.g., burned using espefuse tool) then the process of key generation is skipped and the same key is used for flash encryption process. Otherwise, second stage bootloader uses RNG (random) module to generate an 256 bit or 512 bit key, depending on the value of :ref:`Size of generated XTS-AES key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`, and then writes it into respectively one or two `BLOCK_KEYN` eFuses. The software also updates the ``KEY_PURPOSE_N`` for the blocks where the keys were stored. The key cannot be accessed via software as the write and read protection bits for one or two `BLOCK_KEYN` eFuses are set. ``KEY_PURPOSE_N`` field is write-protected as well. The flash encryption operations happen entirely by hardware, and the key cannot be accessed via software.
 
-  4. Flash encryption block encrypts the flash contents - the firmware bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
+  4. Flash encryption block encrypts the flash contents - the second stage bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
 
-  5. Firmware bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b001) to mark the flash contents as encrypted. Odd number of bits is set.
+  5. Second stage bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b001) to mark the flash contents as encrypted. Odd number of bits is set.
 
-  6. For :ref:`flash-enc-development-mode`, the firmware bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the firmware bootloader by default sets the following eFuse bits:
+  6. For :ref:`flash-enc-development-mode`, the second stage bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the second stage bootloader by default sets the following eFuse bits:
 
     .. list::
 
@@ -217,45 +217,45 @@ Assuming that the eFuse values are in their default states and the firmware boot
       - ``HARD_DIS_JTAG``
       - ``DIS_LEGACY_SPI_BOOT``
 
-  7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets all the eFuse bits set under development mode as well as ``DIS_DOWNLOAD_MANUAL_ENCRYPT``. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
+  7. For :ref:`flash-enc-release-mode`, the second stage bootloader sets all the eFuse bits set under development mode as well as ``DIS_DOWNLOAD_MANUAL_ENCRYPT``. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
 
-  8. The device is then rebooted to start executing the encrypted image. The firmware bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
+  8. The device is then rebooted to start executing the encrypted image. The second stage bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
 
 .. only:: SOC_FLASH_ENCRYPTION_XTS_AES_128 and not SOC_FLASH_ENCRYPTION_XTS_AES_256 and not SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
 
-  1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The ROM bootloader loads the firmware bootloader.
+  1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The first stage (ROM) bootloader loads the second stage bootloader.
 
-  2. Firmware bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. For more information on the flash encryption block, see `{IDF_TARGET_NAME} Technical Reference Manual <{IDF_TARGET_TRM_EN_URL}>`_.
+  2. Second stage bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. For more information on the flash encryption block, see `{IDF_TARGET_NAME} Technical Reference Manual <{IDF_TARGET_TRM_EN_URL}>`_.
 
-  3. Firmware bootloader uses RNG (random) module to generate an 256 bit key and then writes it into `BLOCK_KEYN` eFuse. The software also updates the ``KEY_PURPOSE_N`` for the block where the key is stored. The key cannot be accessed via software as the write and read protection bits for `BLOCK_KEYN` eFuse are set. ``KEY_PURPOSE_N`` field is write-protected as well. The flash encryption is completely conducted by hardware, and the key cannot be accessed via software. If a valid key is already present in the eFuse (e.g., burned using espefuse tool) then the process of key generation is skipped and the same key is used for flash encryption process.
+  3. Second stage bootloader uses RNG (random) module to generate an 256 bit key and then writes it into `BLOCK_KEYN` eFuse. The software also updates the ``KEY_PURPOSE_N`` for the block where the key is stored. The key cannot be accessed via software as the write and read protection bits for `BLOCK_KEYN` eFuse are set. ``KEY_PURPOSE_N`` field is write-protected as well. The flash encryption is completely conducted by hardware, and the key cannot be accessed via software. If a valid key is already present in the eFuse (e.g., burned using espefuse tool) then the process of key generation is skipped and the same key is used for flash encryption process.
 
-  4. Flash encryption block encrypts the flash contents - the firmware bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
+  4. Flash encryption block encrypts the flash contents - the second stage bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
 
-  5. Firmware bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b001) to mark the flash contents as encrypted. Odd number of bits is set.
+  5. Second stage bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b001) to mark the flash contents as encrypted. Odd number of bits is set.
 
-  6. For :ref:`flash-enc-development-mode`, the firmware bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the firmware bootloader by default sets the eFuse bits ``DIS_DOWNLOAD_ICACHE``, ``DIS_PAD_JTAG``, ``DIS_USB_JTAG`` and ``DIS_LEGACY_SPI_BOOT``.
+  6. For :ref:`flash-enc-development-mode`, the second stage bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the second stage bootloader by default sets the eFuse bits ``DIS_DOWNLOAD_ICACHE``, ``DIS_PAD_JTAG``, ``DIS_USB_JTAG`` and ``DIS_LEGACY_SPI_BOOT``.
 
-  7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets all the eFuse bits set under development mode as well as ``DIS_DOWNLOAD_MANUAL_ENCRYPT``. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
+  7. For :ref:`flash-enc-release-mode`, the second stage bootloader sets all the eFuse bits set under development mode as well as ``DIS_DOWNLOAD_MANUAL_ENCRYPT``. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
 
-  8. The device is then rebooted to start executing the encrypted image. The firmware bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
+  8. The device is then rebooted to start executing the encrypted image. The second stage bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
 
 .. only:: SOC_FLASH_ENCRYPTION_XTS_AES_128 and SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
 
-  1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The ROM bootloader loads the firmware bootloader.
+  1. On the first power-on reset, all data in flash is un-encrypted (plaintext). The first stage (ROM) bootloaders loads the second stage bootloader.
 
-  2. Firmware bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. For more information on the flash encryption block, see `{IDF_TARGET_NAME} Technical Reference Manual <{IDF_TARGET_TRM_EN_URL}>`_.
+  2. The second stage bootloader reads the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value (``0b000``). Since the value is ``0`` (even number of bits set), it configures and enables the flash encryption block. For more information on the flash encryption block, see `{IDF_TARGET_NAME} Technical Reference Manual <{IDF_TARGET_TRM_EN_URL}>`_.
 
-  3. Firmware bootloader uses RNG (random) module to generate an 256 or 128 bit key (depends on :ref:`Size of generated XTS-AES key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`) and then writes it into `BLOCK_KEY0` eFuse. The software also updates the ``XTS_KEY_LENGTH_256`` according to the chosen option. The key cannot be accessed via software as the write and read protection bits for ``BLOCK_KEY0`` eFuse are set. The flash encryption operations happen entirely by hardware, and the key cannot be accessed via software. If 128-bit flash encryption key is used, then only the lower 128 bits of the eFuse key block are read-protected, the remaining 128 bits are readable, which is required for secure boot. The entire eFuse block is write-protected. If the FE key is 256 bits long, then ``XTS_KEY_LENGTH_256`` is 1, otherwise it is 0. To prevent this eFuse from being accidentally changed in the future (from 0 to 1), we set a write-protect bit for the RELEASE mode. If a valid key is already present in the eFuse (e.g., burned using espefuse tool) then the process of key generation is skipped and the same key is used for flash encryption process.
+  3. The second stage bootloader uses RNG (random) module to generate an 256 or 128 bit key (depends on :ref:`Size of generated XTS-AES key <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`) and then writes it into `BLOCK_KEY0` eFuse. The software also updates the ``XTS_KEY_LENGTH_256`` according to the chosen option. The key cannot be accessed via software as the write and read protection bits for ``BLOCK_KEY0`` eFuse are set. The flash encryption operations happen entirely by hardware, and the key cannot be accessed via software. If 128-bit flash encryption key is used, then only the lower 128 bits of the eFuse key block are read-protected, the remaining 128 bits are readable, which is required for secure boot. The entire eFuse block is write-protected. If the FE key is 256 bits long, then ``XTS_KEY_LENGTH_256`` is 1, otherwise it is 0. To prevent this eFuse from being accidentally changed in the future (from 0 to 1), we set a write-protect bit for the RELEASE mode. If a valid key is already present in the eFuse (e.g., burned using espefuse tool) then the process of key generation is skipped and the same key is used for flash encryption process.
 
-  4. Flash encryption block encrypts the flash contents - the firmware bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
+  4. Flash encryption block encrypts the flash contents - the second stage bootloader, applications and partitions marked as ``encrypted``. Encrypting in-place can take time, up to a minute for large partitions.
 
-  5. Firmware bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b001) to mark the flash contents as encrypted. Odd number of bits is set.
+  5. The second stage bootloader sets the first available bit in ``{IDF_TARGET_CRYPT_CNT}`` (0b001) to mark the flash contents as encrypted. Odd number of bits is set.
 
-  6. For :ref:`flash-enc-development-mode`, the firmware bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the firmware bootloader by default sets the eFuse bits ``DIS_DOWNLOAD_ICACHE``, ``DIS_PAD_JTAG``, and ``DIS_DIRECT_BOOT``.
+  6. For :ref:`flash-enc-development-mode`, the second stage bootloader allows the UART bootloader to re-flash encrypted binaries. Also, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits are NOT write-protected. In addition, the second stage bootloader by default sets the eFuse bits ``DIS_DOWNLOAD_ICACHE``, ``DIS_PAD_JTAG``, and ``DIS_DIRECT_BOOT``.
 
-  7. For :ref:`flash-enc-release-mode`, the firmware bootloader sets all the eFuse bits set under development mode as well as ``DIS_DOWNLOAD_MANUAL_ENCRYPT``. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
+  7. For :ref:`flash-enc-release-mode`, the second stage bootloader sets all the eFuse bits set under development mode as well as ``DIS_DOWNLOAD_MANUAL_ENCRYPT``. It also write-protects the ``{IDF_TARGET_CRYPT_CNT}`` eFuse bits. To modify this behavior, see :ref:`uart-bootloader-encryption`.
 
-  8. The device is then rebooted to start executing the encrypted image. The firmware bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
+  8. The device is then rebooted to start executing the encrypted image. The second stage bootloader calls the flash decryption block to decrypt the flash contents and then loads the decrypted contents into IRAM.
 
 During the development stage, there is a frequent need to program different plaintext flash images and test the flash encryption process. This requires that Firmware Download mode is able to load new plaintext images as many times as it might be needed. However, during manufacturing or production stages, Firmware Download mode should not be allowed to access flash contents for security reasons.
 
@@ -316,7 +316,7 @@ Enabling flash encryption will increase the size of bootloader, which might requ
 
       This command does not include any user files which should be written to the partitions on the flash memory. Please write them manually before running this command otherwise the files should be encrypted separately before writing.
 
-  This command will write to flash memory unencrypted images: the firmware bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the firmware bootloader encrypts: the firmware bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
+  This command will write to flash memory unencrypted images: the second stage bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the second stage bootloader encrypts: the second stage bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
 
 A sample output of the first {IDF_TARGET_NAME} boot after enabling flash encryption is given below:
 
@@ -486,7 +486,7 @@ Enabling flash encryption will increase the size of bootloader, which might requ
 
       This command does not include any user files which should be written to the partitions on the flash memory. Please write them manually before running this command otherwise the files should be encrypted separately before writing.
 
-  This command will write to flash memory unencrypted images: the firmware bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the firmware bootloader encrypts: the firmware bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
+  This command will write to flash memory unencrypted images: the second stage bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the second stage bootloader encrypts: the second stage bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
 
 If using Development Mode, then the easiest way to update and re-flash binaries is :ref:`encrypt-partitions`.
 
@@ -549,7 +549,7 @@ Enabling flash encryption will increase the size of bootloader, which might requ
 
       This command does not include any user files which should be written to the partitions on the flash memory. Please write them manually before running this command otherwise the files should be encrypted separately before writing.
 
-  This command will write to flash memory unencrypted images: the firmware bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the firmware bootloader encrypts: the firmware bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
+  This command will write to flash memory unencrypted images: the second stage bootloader, the partition table and applications. Once the flashing is complete, {IDF_TARGET_NAME} will reset. On the next boot, the second stage bootloader encrypts: the second stage bootloader, application partitions and partitions marked as ``encrypted`` then resets. Encrypting in-place can take time, up to a minute for large partitions. After that, the application is decrypted at runtime and executed.
 
 Once the flash encryption is enabled in Release mode, the bootloader will write-protect the ``{IDF_TARGET_CRYPT_CNT}`` eFuse.
 
@@ -576,14 +576,14 @@ When using Flash Encryption in production:
 Enable Flash Encryption Externally
 ----------------------------------
 
-In the process mentioned above, flash encryption related eFuses which ultimately enable flash encryption are programmed through the firmware bootloader. Alternatively, all the eFuses can be programmed with the help of ``espefuse`` tool. Please refer :ref:`enable-flash-encryption-externally` for more details.
+In the process mentioned above, flash encryption related eFuses which ultimately enable flash encryption are programmed through the second stage bootloader. Alternatively, all the eFuses can be programmed with the help of ``espefuse`` tool. Please refer :ref:`enable-flash-encryption-externally` for more details.
 
 Possible Failures
 -----------------
 
 Once flash encryption is enabled, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value will have an odd number of bits set. It means that all the partitions marked with the encryption flag are expected to contain encrypted ciphertext. Below are the three typical failure cases if the {IDF_TARGET_NAME} is erroneously loaded with plaintext data:
 
-1. If the bootloader partition is re-flashed with a **plaintext firmware bootloader image**, the ROM bootloader will fail to load the firmware bootloader resulting in the following failure:
+1. If the bootloader partition is re-flashed with a **plaintext second stage bootloader image**, the first stage (ROM) bootloader will fail to load the second stage bootloader resulting in the following failure:
 
 .. only:: esp32
 
@@ -635,7 +635,7 @@ Once flash encryption is enabled, the ``{IDF_TARGET_CRYPT_CNT}`` eFuse value wil
 
     This error also appears if the flash contents are erased or corrupted.
 
-2. If the firmware bootloader is encrypted, but the partition table is re-flashed with a **plaintext partition table image**, the bootloader will fail to read the partition table resulting in the following failure:
+2. If the second stage bootloader is encrypted, but the partition table is re-flashed with a **plaintext partition table image**, the bootloader will fail to read the partition table resulting in the following failure:
 
   .. code-block:: bash
 
@@ -727,7 +727,7 @@ Whenever the ``{IDF_TARGET_CRYPT_CNT}`` eFuse is set to a value with an odd numb
 - Executable application code in flash (IROM).
 - All read-only data stored in flash (DROM).
 - Any data accessed via :cpp:func:`spi_flash_mmap`.
-- The firmware bootloader image when it is read by the ROM bootloader.
+- The second stage bootloader image when it is read by the first stage (ROM) bootloader.
 
 .. important::
 
@@ -776,7 +776,7 @@ OTA updates to encrypted partitions will automatically write encrypted data if t
 
 Before building the application image for OTA updating of an already encrypted device, enable the option :ref:`Enable flash encryption on boot <CONFIG_SECURE_FLASH_ENC_ENABLED>` in project configuration menu.
 
-For general information about ESP-IDF OTA updates, please refer to :doc:`OTA <../api-reference/system/ota>`
+For general information about ESP-IDF OTA updates, please refer to :doc:`OTA <../api-reference/system/ota>`.
 
 
 .. _updating-encrypted-flash-serial:
@@ -976,7 +976,7 @@ However, before the first boot you can choose to keep any of these features enab
 
   The eFuse ``FLASH_CRYPT_CONFIG`` determines the number of bits in the flash encryption key which are "tweaked" with the block offset. For details, see :ref:`flash-encryption-algorithm`.
 
-  On the first boot of the firmware bootloader, this value is set to the maximum ``0xF``.
+  On the first boot of the second stage bootloader, this value is set to the maximum ``0xF``.
 
   It is possible to burn this eFuse manually and write protect it before the first boot in order to select different tweak values. However, this is not recommended.
 
diff --git a/docs/en/security/secure-boot-v1.rst b/docs/en/security/secure-boot-v1.rst
index 4d618af1fa7..d67b75999a8 100644
--- a/docs/en/security/secure-boot-v1.rst
+++ b/docs/en/security/secure-boot-v1.rst
@@ -30,7 +30,7 @@ Background
 
 - To understand the secure boot process, please familiarize yourself with the standard :doc:`../api-guides/startup`.
 
-- Both stages of the boot process, including initial software bootloader load and subsequent partition & app loading, are verified by the secure boot process, in a chain of trust relationship.
+- Both stages of the boot process, including initial second stage bootloader load and subsequent partition & app loading, are verified by the secure boot process, in a chain of trust relationship.
 
 
 Secure Boot Process Overview
@@ -42,18 +42,18 @@ This is a high-level overview of the secure boot process. Step-by-step instructi
 
 2. Secure boot defaults to signing images and partition table data during the build process. The ``Secure boot private signing key`` config item is a file path to an ECDSA public/private key pair in a PEM format file.
 
-3. The software bootloader image is built by ESP-IDF with secure boot support enabled, and the public key for signature verification is integrated into the bootloader image. This software bootloader image is flashed at offset 0x1000.
+3. The second stage bootloader image is built by ESP-IDF with secure boot support enabled, and the public key for signature verification is integrated into the bootloader image. This second stage bootloader image is flashed at offset 0x1000.
 
-4. On the first boot, the software bootloader follows the following process to enable a secure boot:
+4. On the first boot, the second stage bootloader follows the following process to enable a secure boot:
 
    - Hardware secure boot support generates a device-secure bootloader key and a secure digest. The secure bootloader key is generated with the help of the hardware RNG, and then stored in eFuse with read and write protection enabled. The digest is derived from the key, an initialization vector (IV), and the bootloader image contents.
    - The secure digest is flashed at offset 0x0 in the flash.
    - Depending on Secure Boot Configuration, eFuses are burned to disable JTAG and the ROM BASIC interpreter. It is **strongly recommended** that these options are turned on.
-   - Bootloader permanently enables secure boot by burning the ABS_DONE_0 eFuse. The software bootloader then becomes protected. After this point, the chip will only boot a bootloader image if the digest matches.
+   - Bootloader permanently enables secure boot by burning the ABS_DONE_0 eFuse. The second stage bootloader then becomes protected. After this point, the chip will only boot a bootloader image if the digest matches.
 
-5. On subsequent boots, the ROM bootloader sees that the secure boot eFuse is burned, reads the saved digest at 0x0, and uses hardware secure boot support to compare it with a newly calculated digest. If the digest does not match then booting will not continue. The digest and comparison are performed entirely by hardware, and the calculated digest is not readable by software. For technical details see :ref:`secure-boot-hardware-support`.
+5. On subsequent boots, the first stage (ROM) bootloader sees that the secure boot eFuse is burned, reads the saved digest at 0x0, and uses hardware secure boot support to compare it with a newly calculated digest. If the digest does not match then booting will not continue. The digest and comparison are performed entirely by hardware, and the calculated digest is not readable by software. For technical details see :ref:`secure-boot-hardware-support`.
 
-6. When running in secure boot mode, the software bootloader uses the secure boot signing key, the public key of which is embedded in the bootloader itself and therefore validated as part of the bootloader, to verify the signature appended to all subsequent partition tables and app images before they are booted.
+6. When running in secure boot mode, the second stage bootloader uses the secure boot signing key, the public key of which is embedded in the bootloader itself and therefore validated as part of the bootloader, to verify the signature appended to all subsequent partition tables and app images before they are booted.
 
 
 Keys
@@ -73,7 +73,7 @@ The following keys are used by the secure boot process:
 
 - ``secure boot signing key`` is a standard ECDSA public/private key pair in PEM format, see :ref:`secure-boot-image-signing-algorithm`.
 
-  - The public key from this key pair is compiled into the software bootloader. It is only used for signature verification purposes and not signature creation. This public key is used to verify the second stage of booting, including the partition table and app image, before booting continues. The public key can be freely distributed; it does not need to be kept secret.
+  - The public key from this key pair is compiled into the second stage bootloader. It is only used for signature verification purposes and not signature creation. This public key is used to verify the second stage of booting, including the partition table and app image, before booting continues. The public key can be freely distributed; it does not need to be kept secret.
 
   - The private key from this key pair **must be securely kept private**, as anyone who has this key can authenticate to any bootloader that is configured with a secure boot and the matching public key.
 
@@ -117,7 +117,7 @@ How to Enable Secure Boot
 
   ``idf.py flash`` does not flash the bootloader if secure boot is enabled.
 
-8. Reset the {IDF_TARGET_NAME} and it will boot the software bootloader you flashed. The software bootloader will enable secure boot on the chip, and then it verifies the app image signature and boots the app. You should watch the serial console output from the {IDF_TARGET_NAME} to verify that secure boot is enabled and no errors have occurred due to the build configuration.
+8. Reset the {IDF_TARGET_NAME} and it will boot the second stage bootloader you flashed. The second stage bootloader will enable secure boot on the chip, and then it verifies the app image signature and boots the app. You should watch the serial console output from the {IDF_TARGET_NAME} to verify that secure boot is enabled and no errors have occurred due to the build configuration.
 
 .. note::
 
@@ -127,13 +127,13 @@ How to Enable Secure Boot
 
   If {IDF_TARGET_NAME} is reset or powered down during the first boot, it will start the process again on the next boot.
 
-9. On subsequent boots, the secure boot hardware will verify the software bootloader has not changed using the secure bootloader key, and then the software bootloader will verify the signed partition table and app image using the public key portion of the secure boot signing key.
+9. On subsequent boots, the secure boot hardware will verify the second stage bootloader has not changed using the secure bootloader key, and then the second stage bootloader will verify the signed partition table and app image using the public key portion of the secure boot signing key.
 
 
 .. _secure-boot-reflashable:
 
-Reflashable Software Bootloader
--------------------------------
+Reflashable Second Stage Bootloader
+-----------------------------------
 
 Configuration ``Secure Boot: One-Time Flash`` is the recommended configuration for production devices. In this mode, each device gets a unique key that is never stored outside the device.
 
@@ -229,7 +229,7 @@ The following sections contain low-level reference descriptions of various secur
 Secure Boot Hardware Support
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-The first stage of secure boot verification, i.e., checking the software bootloader, is done via hardware. The {IDF_TARGET_NAME}'s secure boot support hardware can perform three basic operations:
+The first stage of secure boot verification, i.e., checking the second stage bootloader, is done via hardware. The {IDF_TARGET_NAME}'s secure boot support hardware can perform three basic operations:
 
 1. Generate a random sequence of bytes from a hardware random number generator.
 
diff --git a/docs/en/security/secure-boot-v2.rst b/docs/en/security/secure-boot-v2.rst
index e69b3ce049c..d2404cf3c62 100644
--- a/docs/en/security/secure-boot-v2.rst
+++ b/docs/en/security/secure-boot-v2.rst
@@ -31,7 +31,7 @@ Secure Boot v2
 
         For ESP32 before chip revision v3.0, refer to :doc:`secure-boot-v1`. It is recommended to use Secure Boot v2 if you have a chip revision that supports it. Secure Boot v2 is safer and more flexible than Secure Boot V1.
 
-    Secure Boot v2 uses {IDF_TARGET_SBV2_SCHEME} based app and bootloader :ref:`second-stage-bootloader` verification. This document can also be used as a reference for signing apps using the {IDF_TARGET_SBV2_SCHEME} scheme without signing the bootloader.
+    Secure Boot v2 uses {IDF_TARGET_SBV2_SCHEME} based app and :ref:`second-stage-bootloader` verification. This document can also be used as a reference for signing apps using the {IDF_TARGET_SBV2_SCHEME} scheme without signing the bootloader.
 
 .. only:: esp32
 
@@ -49,7 +49,7 @@ Secure Boot v2
 Background
 ----------
 
-Secure Boot protects a device from running any unauthorized (i.e., unsigned) code by checking that each piece of software that is being booted is signed. On an {IDF_TARGET_NAME}, these pieces of software include the second stage bootloader and each application binary. Note that the first stage bootloader does not require signing as it is ROM code and thus cannot be changed.
+Secure Boot protects a device from running any unauthorized (i.e., unsigned) code by checking that each piece of software that is being booted is signed. On an {IDF_TARGET_NAME}, these pieces of software include the second stage bootloader and each application binary. Note that the first stage (ROM) bootloader does not require signing as it is ROM code and thus cannot be changed.
 
 .. only:: esp32 or (SOC_SECURE_BOOT_V2_RSA and not SOC_SECURE_BOOT_V2_ECC)
 
@@ -65,7 +65,7 @@ Secure Boot protects a device from running any unauthorized (i.e., unsigned) cod
 
 The Secure Boot process on {IDF_TARGET_NAME} involves the following steps:
 
-1. The first stage bootloader (i.e. ROM boot), which is residing in ROM, loads the second stage bootloader, and the second stage bootloader's {IDF_TARGET_SBV2_SCHEME} signature is verified. Only if the verification is successful, the second stage bootloader is executed.
+1. The first stage (ROM) bootloader loads the second stage bootloader, and the second stage bootloader's {IDF_TARGET_SBV2_SCHEME} signature is verified. Only if the verification is successful, the second stage bootloader is executed.
 
 2. When the second stage bootloader loads a particular application image, the application's {IDF_TARGET_SBV2_SCHEME} signature is verified. If the verification is successful, the application image is executed.
 
@@ -85,10 +85,10 @@ Advantages
 
     - {IDF_TARGET_NAME} provides the facility to permanently revoke individual public keys. This can be configured conservatively or aggressively.
 
-      - Conservatively: The old key is revoked after the bootloader and application have successfully migrated to a new key.
-      - Aggressively: The key is revoked as soon as verification with this key fails.
+        - Conservatively: The old key is revoked after the bootloader and application have successfully migrated to a new key.
+        - Aggressively: The key is revoked as soon as verification with this key fails.
 
-- The same image format and signature verification method is applied for applications and the software bootloader.
+- The same image format and signature verification method is applied for applications and the second stage bootloader.
 
 - No secrets are stored on the device. Therefore, it is immune to passive side-channel attacks, e.g., timing or power analysis.
 
@@ -166,7 +166,7 @@ The signature block starts on a 4 KB aligned boundary and has a flash sector of
                   - {IDF_TARGET_ECDSA_TIME}
                   - {IDF_TARGET_CPU_FREQ}
 
-          The above table compares the time taken to verify a signature in a particular scheme. It does not indicate the boot-up time.
+            The above table compares the time taken to verify a signature in a particular scheme. It does not indicate the boot-up time.
 
 The content of each signature block is shown in the following table:
 
@@ -216,7 +216,7 @@ The content of each signature block is shown in the following table:
 
     .. note::
 
-      R and M' are used for hardware-assisted Montgomery Multiplication.
+        R and M' are used for hardware-assisted Montgomery Multiplication.
 
 .. only:: SOC_SECURE_BOOT_V2_ECC
 
@@ -399,11 +399,11 @@ How To Enable Secure Boot v2
 
 .. important::
 
-   A signing key generated this way will use the best random number source available to the OS and its Python installation, which is `/dev/urandom` on OSX/Linux and `CryptGenRandom()` on Windows. If this random number source is weak, then the private key will be weak.
+    A signing key generated this way will use the best random number source available to the OS and its Python installation, which is `/dev/urandom` on OSX/Linux and `CryptGenRandom()` on Windows. If this random number source is weak, then the private key will be weak.
 
 .. important::
 
-   For production environments, we recommend generating the key pair using OpenSSL or another industry-standard encryption program. See :ref:`secure-boot-v2-generate-key` for more details.
+    For production environments, we recommend generating the key pair using OpenSSL or another industry-standard encryption program. See :ref:`secure-boot-v2-generate-key` for more details.
 
 7. Run ``idf.py bootloader`` to build a Secure Boot-enabled bootloader. The build output will include a prompt for a flashing command, using ``esptool.py write_flash``.
 
@@ -415,17 +415,17 @@ How To Enable Secure Boot v2
 
   ``idf.py flash`` does not flash the bootloader if Secure Boot is enabled.
 
-10. Reset the {IDF_TARGET_NAME} and it will boot the software bootloader you flashed. The software bootloader will enable Secure Boot on the chip, and then it verifies the app image signature and boots the app. You should watch the serial console output from the {IDF_TARGET_NAME} to verify that Secure Boot is enabled and no errors have occurred due to the build configuration.
+10. Reset the {IDF_TARGET_NAME} and it will boot the second stage bootloader you flashed. The second stage bootloader will enable Secure Boot on the chip, and then it verifies the app image signature and boots the app. You should watch the serial console output from the {IDF_TARGET_NAME} to verify that Secure Boot is enabled and no errors have occurred due to the build configuration.
 
 .. note::
 
-  Secure Boot will not be enabled until after a valid partition table and app image have been flashed. This is to prevent accidents before the system is fully configured.
+    Secure Boot will not be enabled until after a valid partition table and app image have been flashed. This is to prevent accidents before the system is fully configured.
 
 .. note::
 
-  If the {IDF_TARGET_NAME} is reset or powered down during the first boot, it will start the process again on the next boot.
+    If the {IDF_TARGET_NAME} is reset or powered down during the first boot, it will start the process again on the next boot.
 
-11. On subsequent boots, the Secure Boot hardware will verify the software bootloader has not changed and the software bootloader will verify the signed app image using the validated public key portion of its appended signature block.
+11. On subsequent boots, the Secure Boot hardware will verify that the second stage bootloader has not changed, and the second stage bootloader will verify the signed app image using the validated public key portion of its appended signature block.
 
 
 Restrictions After Secure Boot Is Enabled
@@ -445,21 +445,21 @@ The following keys must be read-protected on the device, the respective hardware
 
 .. list::
 
-  :SOC_FLASH_ENC_SUPPORTED:* Flash encryption key
+    :SOC_FLASH_ENC_SUPPORTED:* Flash encryption key
 
-  :SOC_HMAC_SUPPORTED:* HMAC keys
+    :SOC_HMAC_SUPPORTED:* HMAC keys
 
-  :SOC_ECDSA_SUPPORTED:* ECDSA keys
+    :SOC_ECDSA_SUPPORTED:* ECDSA keys
 
-  :SOC_KEY_MANAGER_SUPPORTED:* Key Manager keys
+    :SOC_KEY_MANAGER_SUPPORTED:* Key Manager keys
 
 **Non-read protected keys**:
 The following keys must not be read-protected on the device as the software needs to access them (readable by software):
 
 .. list::
 
-  :SOC_SECURE_BOOT_SUPPORTED:* Secure boot public key digest
-  * User data
+    :SOC_SECURE_BOOT_SUPPORTED:* Secure boot public key digest
+    * User data
 
 When Secure Boot is enabled, it shall disable the ability to read-protect further eFuses by default. If you want keep the ability to read-protect an eFuse later in the application (e.g, a key mentioned in the above list of read-protected keys) then you need to enable the config :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS` at the same time when you enable Secure Boot.
 
@@ -467,7 +467,7 @@ Ideally, it is strongly recommended that all such keys must been burned before e
 
 .. note::
 
-   If :doc:`/security/flash-encryption` is enabled by the 2nd stage bootloader at the time of enabling Secure Boot, it ensures that the flash encryption key generated on the first boot shall already be read-protected.
+    If :doc:`/security/flash-encryption` is enabled by the second stage bootloader at the time of enabling Secure Boot, it ensures that the flash encryption key generated on the first boot shall already be read-protected.
 
 .. _secure-boot-v2-generate-key:
 
@@ -478,11 +478,11 @@ The build system will prompt you with a command to generate a new signing key vi
 
 .. only:: esp32 or SOC_SECURE_BOOT_V2_RSA
 
-   The ``--version 2`` parameter will generate the RSA 3072 private key for Secure Boot v2. Additionally ``--scheme rsa3072`` can be passed as well to generate RSA 3072 private key.
+    The ``--version 2`` parameter will generate the RSA 3072 private key for Secure Boot v2. Additionally ``--scheme rsa3072`` can be passed as well to generate RSA 3072 private key.
 
 .. only:: SOC_SECURE_BOOT_V2_ECC
 
-   Select the ECDSA scheme by passing ``--version 2 --scheme ecdsa256`` or ``--version 2 --scheme ecdsa192`` to generate corresponding ECDSA private key.
+    Select the ECDSA scheme by passing ``--version 2 --scheme ecdsa256`` or ``--version 2 --scheme ecdsa192`` to generate corresponding ECDSA private key.
 
 The strength of the signing key is proportional to (a) the random number source of the system, and (b) the correctness of the algorithm used. For production devices, we recommend generating signing keys from a system with a quality entropy source and using the best available {IDF_TARGET_SBV2_SCHEME} key generation utilities.
 
@@ -502,13 +502,13 @@ For example, to generate a signing key using the OpenSSL command line:
 
     .. code-block::
 
-      openssl ecparam -name prime192v1 -genkey -noout -out my_secure_boot_signing_key.pem
+        openssl ecparam -name prime192v1 -genkey -noout -out my_secure_boot_signing_key.pem
 
     For the ECC NIST256p curve
 
     .. code-block::
 
-      openssl ecparam -name prime256v1 -genkey -noout -out my_secure_boot_signing_key.pem
+        openssl ecparam -name prime256v1 -genkey -noout -out my_secure_boot_signing_key.pem
 
 Remember that the strength of the Secure Boot system depends on keeping the signing key private.
 
@@ -529,13 +529,13 @@ After the app image and partition table are built, the build system will print s
 
 .. code-block::
 
-  idf.py secure-sign-data BINARY_FILE --keyfile PRIVATE_SIGNING_KEY
+    idf.py secure-sign-data BINARY_FILE --keyfile PRIVATE_SIGNING_KEY
 
 The above command appends the image signature to the existing binary. You can use the `--output` argument to write the signed binary to a separate file:
 
 .. code-block::
 
-  idf.py secure-sign-data --keyfile PRIVATE_SIGNING_KEY --output SIGNED_BINARY_FILE BINARY_FILE
+    idf.py secure-sign-data --keyfile PRIVATE_SIGNING_KEY --output SIGNED_BINARY_FILE BINARY_FILE
 
 
 Signing Using Pre-calculated Signatures
@@ -547,7 +547,7 @@ In such cases, the firmware image should be built by disabling the option :ref:`
 
 .. code-block::
 
-  idf.py secure-sign-data --pub-key PUBLIC_SIGNING_KEY --signature SIGNATURE_FILE --output SIGNED_BINARY_FILE BINARY_FILE
+    idf.py secure-sign-data --pub-key PUBLIC_SIGNING_KEY --signature SIGNATURE_FILE --output SIGNED_BINARY_FILE BINARY_FILE
 
 The above command verifies the signature, generates a signature block (refer to :ref:`signature-block-format`), and appends it to the binary file.
 
@@ -563,13 +563,13 @@ In such cases, disable the option :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES
 
     .. note::
 
-      For all the above three remote signing workflows, the signed binary is written to the filename provided to the ``--output`` argument, and the option ``--append_signatures`` allows us to append multiple signatures (up to 3) to the image.
+        For all the above three remote signing workflows, the signed binary is written to the filename provided to the ``--output`` argument, and the option ``--append_signatures`` allows us to append multiple signatures (up to 3) to the image.
 
 .. only:: not SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
 
     .. note::
 
-      For all the above three remote signing workflows, the signed binary is written to the filename provided to the ``--output`` argument.
+        For all the above three remote signing workflows, the signed binary is written to the filename provided to the ``--output`` argument.
 
 
 Secure Boot Best Practices
@@ -589,9 +589,9 @@ Secure Boot Best Practices
     * Between 1 and 3 {IDF_TARGET_SBV2_KEY} public key pairs (Keys #0, #1, #2) should be computed independently and stored separately.
     * The KEY_DIGEST eFuses should be write-protected after being programmed.
     * The unused KEY_DIGEST slots must have their corresponding KEY_REVOKE eFuse burned to permanently disable them. This must happen before the device leaves the factory.
-    * The eFuses can either be written by the software bootloader during first boot after enabling ``Secure Boot v2`` from menuconfig or can be done using ``espefuse.py`` which communicates with the serial bootloader program in ROM.
+    * The eFuses can either be written by the second stage bootloader during first boot after enabling ``Secure Boot v2`` from menuconfig or can be done using ``espefuse.py`` which communicates with the serial bootloader program in ROM.
     * The KEY_DIGESTs should be numbered sequentially beginning at key digest #0. If key digest #1 is used, key digest #0 should be used. If key digest #2 is used, key digest #0 & #1 must be used.
-    * The software bootloader is non-OTA upgradeable, and is signed using at least one, possibly all three, private keys and flashed in the factory.
+    * The second stage bootloader is non-OTA upgradeable, and is signed using at least one, possibly all three, private keys and flashed in the factory.
     * Apps should only be signed with a single private key, with the others being stored securely elsewhere. However, they may be signed with multiple private keys if some are being revoked, see :ref:`secure-boot-v2-key-revocation` below.
 
 
@@ -600,7 +600,7 @@ Secure Boot Best Practices
 
     * The bootloader should be signed with all the private key(s) that are needed for the life of the device, before it is flashed.
     * The build system can sign with at most one private key, user has to run manual commands to append more signatures if necessary.
-    * You can use the append functionality of ``idf.py secure-sign-data``, this command would also printed at the end of the Secure Boot V2 enabled bootloader compilation.
+    * You can use the append functionality of ``idf.py secure-sign-data``, this command would also printed at the end of the Secure Boot v2 enabled bootloader compilation.
 
     .. code-block::
 
@@ -646,8 +646,7 @@ Secure Boot Best Practices
 
     .. note::
 
-        It may be necessary to revoke a key that isn't currently being used.
-        For example, if the active application is signed with key #0, but key #1 becomes compromised, you should revoke key #1 by using the above approach. The new OTA update should continue to be signed with key #0, and the API `esp_ota_revoke_secure_boot_public_key(SECURE_BOOT_PUBLIC_KEY_INDEX_[N])` can be used to revoke the key #N (N would be 1 in this case). After revoking, all remaining unrevoked keys can still be used to sign future applications.
+        It may be necessary to revoke a key that isn't currently being used. For example, if the active application is signed with key #0, but key #1 becomes compromised, you should revoke key #1 by using the above approach. The new OTA update should continue to be signed with key #0, and the API `esp_ota_revoke_secure_boot_public_key (SECURE_BOOT_PUBLIC_KEY_INDEX_[N])` can be used to revoke the key #N (N would be 1 in this case). After revoking, all remaining unrevoked keys can still be used to sign future applications.
 
 
     .. _secure-boot-v2-aggressive-key-revocation:
@@ -673,15 +672,14 @@ The following sections contain low-level reference descriptions of various Secur
 
 Secure Boot is integrated into the ESP-IDF build system, so ``idf.py build`` will sign an app image, and ``idf.py bootloader`` will produce a signed bootloader if :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` is enabled.
 
-However, it is possible to use the ``idf.py`` or the ``openssl`` tool to generate standalone signatures and verify them. Using ``idf.py`` is recommended, but in case you need to generate or verify signatures in non-ESP-IDF environments,
-you could also use the ``openssl`` commands as the Secure Boot V2 signature generation is compliant with the standard signing algorithms.
+However, it is possible to use the ``idf.py`` or the ``openssl`` tool to generate standalone signatures and verify them. Using ``idf.py`` is recommended, but in case you need to generate or verify signatures in non-ESP-IDF environments, you could also use the ``openssl`` commands as the Secure Boot v2 signature generation is compliant with the standard signing algorithms.
 
-Generating and Verifying signatures using ``idf.py``
+Generating and Verifying Signatures Using ``idf.py``
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 1. To sign a binary image:
 
-  .. code-block::
+.. code-block::
 
     idf.py secure-sign-data --keyfile ./my_signing_key.pem --output ./image_signed.bin image-unsigned.bin
 
@@ -689,11 +687,11 @@ Keyfile is the PEM file containing an {IDF_TARGET_SBV2_KEY} private signing key.
 
 2. To verify a signed binary image:
 
-  .. code-block::
+.. code-block::
 
     idf.py secure-verify-signature --keyfile ./my_signing_key.pem image_signed.bin
 
-Keyfile is the PEM file containing an {IDF_TARGET_SBV2_KEY} public/\private signing key.
+Keyfile is the PEM file containing an {IDF_TARGET_SBV2_KEY} public/private signing key.
 
 Generating and Verifying signatures using OpenSSL
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -772,7 +770,7 @@ If Secure Boot is used without :doc:`flash-encryption`, it is possible to launch
 
     .. important::
 
-       {IDF_TARGET_NAME} has only one eFuse key block, which is used for both keys: Secure Boot and Flash Encryption. The eFuse key block can only be burned once. Therefore these keys should be burned together at the same time. Please note that ``Secure Boot`` and ``Flash Encryption`` can not be enabled separately as subsequent writes to the eFuse key block shall return an error.
+        {IDF_TARGET_NAME} has only one eFuse key block, which is used for both keys: Secure Boot and Flash Encryption. The eFuse key block can only be burned once. Therefore these keys should be burned together at the same time. Please note that ``Secure Boot`` and ``Flash Encryption`` can not be enabled separately as subsequent writes to the eFuse key block shall return an error.
 
 
 .. _signed-app-verify-v2:
diff --git a/docs/en/security/security-features-enablement-workflows.rst b/docs/en/security/security-features-enablement-workflows.rst
index 35e36344b83..973c7305b17 100644
--- a/docs/en/security/security-features-enablement-workflows.rst
+++ b/docs/en/security/security-features-enablement-workflows.rst
@@ -18,6 +18,11 @@ When enabling security features on ESP32 SoCs, it is recommended that power supp
 
 This guide describes a set of workflows to enable security features on the device with the assistance of an external host machine. These workflows are broken down into various stages, with each stage generating signing/encryption keys on the host machine. This allows for greater chances of recovery in case of power or other failures. Furthermore, these workflows expedites the overall provisioning process via the use of the host machine (e.g., encrypting firmware on the host is quicker than on the device).
 
+.. only:: TARGET_SUPPORT_QEMU
+
+   .. important::
+
+      It is possible to try out the security features for {IDF_TARGET_NAME} target SoC under :doc:`../api-guides/tools/qemu` virtually. Once the security workflow is established, you can then proceed to the real hardware.
 
 Goals
 -----
@@ -25,7 +30,7 @@ Goals
 #. Simplify the traditional workflow for enabling security features with stepwise instructions.
 #. Design a more flexible workflow when compared to the traditional firmware-based workflow.
 #. Improve reliability by dividing the workflow into small operations.
-#. Eliminate dependency on :ref:`second-stage-bootloader` (firmware bootloader).
+#. Eliminate dependency on :ref:`second-stage-bootloader`.
 
 Prerequisites
 -------------
@@ -324,7 +329,7 @@ In this case all the eFuses related to Flash Encryption are written with help of
 
         .. only:: esp32
 
-            If your ESP32 uses non-default :ref:`FLASH_CRYPT_CONFIG value in eFuse <setting-flash-crypt-config>` then you will need to pass the ``--flash_crypt_conf`` argument to ``espsecure.py`` to set the matching value. This will not happen when the Flash Encryption is enabled by the firmware bootloader but may happen when burning eFuses manually to enable Flash Encryption.
+            If your ESP32 uses non-default :ref:`FLASH_CRYPT_CONFIG value in eFuse <setting-flash-crypt-config>` then you will need to pass the ``--flash_crypt_conf`` argument to ``espsecure.py`` to set the matching value. This will not happen when the Flash Encryption is enabled by the second stage bootloader but may happen when burning eFuses manually to enable Flash Encryption.
 
     The command ``espsecure.py decrypt_flash_data`` can be used with the same options (and different input or output files), to decrypt ciphertext flash contents or a previously encrypted file.
 
@@ -518,7 +523,7 @@ In this workflow we shall use ``espsecure`` tool to generate signing keys and us
 
 6. Configure the project
 
-    By default, the ROM bootloader would only verify the :ref:`second-stage-bootloader` (firmware bootloader). The firmware bootloader would verify the app partition only when the :ref:`CONFIG_SECURE_BOOT` option is enabled (and :ref:`CONFIG_SECURE_BOOT_VERSION` is set to ``SECURE_BOOT_V2_ENABLED``) while building the bootloader.
+    By default, the first stage (ROM) bootloader would only verify the :ref:`second-stage-bootloader`. The second stage bootloader would verify the app partition only when the :ref:`CONFIG_SECURE_BOOT` option is enabled (and :ref:`CONFIG_SECURE_BOOT_VERSION` is set to ``SECURE_BOOT_V2_ENABLED``) while building the bootloader.
 
     A) Open the :ref:`project-configuration-menu`, in ``Security features`` set ``Enable hardware Secure Boot in bootloader`` to enable Secure Boot.
 
diff --git a/docs/en/security/security.rst b/docs/en/security/security.rst
index 07e3ef2b262..d834e7c9d4b 100644
--- a/docs/en/security/security.rst
+++ b/docs/en/security/security.rst
@@ -13,6 +13,12 @@ This guide provides an overview of the overall security features available in va
 
     In this guide, most used commands are in the form of ``idf.py secure-<command>``, which is a wrapper around corresponding ``espsecure.py <command>``. The ``idf.py`` based commands provides more user-friendly experience, although may lack some of the advanced functionality of their ``espsecure.py`` based counterparts.
 
+.. only:: TARGET_SUPPORT_QEMU
+
+   .. important::
+
+      It is possible to try out the security features for {IDF_TARGET_NAME} target SoC under :doc:`../api-guides/tools/qemu` virtually. Once the security workflow is established, you can then proceed to the real hardware.
+
 Goals
 -----
 
diff --git a/docs/en/versions.rst b/docs/en/versions.rst
index b18ed5dd266..b6eec4d8be2 100644
--- a/docs/en/versions.rst
+++ b/docs/en/versions.rst
@@ -125,7 +125,7 @@ The local ESP-IDF version can be checked by using idf.py::
 
   idf.py --version
 
-The ESP-IDF version is also compiled into the firmware and can be accessed (as a string) via the macro ``IDF_VER``. The default ESP-IDF bootloader will print the version on boot (the version information is not always updated if the code in the GitHub repo is updated, it only changes if there is a clean build or if that particular source file is recompiled).
+The ESP-IDF version is also compiled into the firmware and can be accessed (as a string) via the macro ``IDF_VER``. The default ESP-IDF bootloader prints the version on boot (The version information is not always updated if the code in the GitHub repo is updated, it only changes if there is a clean build or if that particular source file is recompiled).
 
 If writing code that needs to support multiple ESP-IDF versions, the version can be checked at compile time using :ref:`compile-time macros <idf-version-h>`.
 
diff --git a/docs/page_redirects.txt b/docs/page_redirects.txt
index 68afde9d3f3..f566d253542 100644
--- a/docs/page_redirects.txt
+++ b/docs/page_redirects.txt
@@ -105,3 +105,6 @@ get-started/macos-setup-scratch                 get-started/linux-macos-setup
 get-started/toolchain-setup-scratch             get-started/index
 get-started/eclipse-setup                       get-started/index
 get-started/vscode-setup                        get-started/index
+
+# Kconfig documentation got pretty serious file structure changes
+api-reference/kconfig                          api-reference/kconfig-reference
diff --git a/docs/zh_CN/api-guides/ble/ble-feature-support-status.rst b/docs/zh_CN/api-guides/ble/ble-feature-support-status.rst
index 60d3919ebb2..288f0edfe73 100644
--- a/docs/zh_CN/api-guides/ble/ble-feature-support-status.rst
+++ b/docs/zh_CN/api-guides/ble/ble-feature-support-status.rst
@@ -162,7 +162,7 @@
       - |experimental|
       - |experimental|
     * -
-      - Advertising Channel Index
+      - Randomized Advertising Channel Indexing
       - |unsupported|
       - |NA|
       - |NA|
@@ -171,19 +171,19 @@
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61
 
             |experimental|
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61
 
             |experimental|
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c2 or esp32c5 or esp32c61
 
             |experimental|
     * - .. centered:: |5.2|
@@ -201,14 +201,14 @@
       - .. only:: esp32 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 or esp32c61
 
             |experimental|
       - |unsupported|
       - .. only:: esp32 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c3 or esp32s3 or esp32c5 or esp32c61
 
             |experimental|
     * - .. centered:: |5.3|
@@ -216,31 +216,31 @@
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |supported|
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
            |supported|
       - .. only:: esp32 or esp32c3 or esp32s3
 
             |unsupported|
-        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |supported|
     * -
       - LE Enhanced Connection Update (Connection Subrating)
-      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5
+      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |unsupported|
         .. only:: esp32c3 or esp32s3
 
             |experimental|
       - |unsupported|
-      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5
+      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |unsupported|
         .. only:: esp32c3 or esp32s3
@@ -251,31 +251,31 @@
       - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61
 
             |experimental|
       - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61
 
             |experimental|
       - .. only:: esp32 or esp32c3 or esp32s3 or esp32c2
 
             |unsupported|
-        .. only:: esp32c6 or esp32h2 or esp32c5
+        .. only:: esp32c6 or esp32h2 or esp32c5 or esp32c61
 
             |experimental|
     * - .. centered:: |5.4|
       - Advertising Coding Selection
-      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5
+      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |unsupported|
         .. only:: esp32c3 or esp32s3
 
             |experimental|
       - |unsupported|
-      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5
+      - .. only:: esp32 or esp32c6 or esp32c2 or esp32h2 or esp32c5 or esp32c61
 
             |unsupported|
         .. only:: esp32c3 or esp32s3
diff --git a/docs/zh_CN/api-guides/ble/get-started/ble-connection.rst b/docs/zh_CN/api-guides/ble/get-started/ble-connection.rst
index b34bb9fdeb9..83ae7b84c30 100644
--- a/docs/zh_CN/api-guides/ble/get-started/ble-connection.rst
+++ b/docs/zh_CN/api-guides/ble/get-started/ble-connection.rst
@@ -11,7 +11,7 @@
 
 - 学习连接的基本概念
 - 学习连接相关的参数
-- 学习 NimBLE_Connection 例程的代码结构
+- 学习 :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` 例程的代码结构
 
 
 连接的基本概念
@@ -23,7 +23,7 @@
 
 *在 Bluetooth LE 5.0 引入扩展广播特性以后， Legacy ADV 和 Extended ADV 对应的连接建立过程略有差异，下以 Legacy ADV 对应的连接建立过程为例。*
 
-当扫描者在某一个广播信道接收到一个广播数据包时，若该广播者是可连接的，那么扫描者可以在同一广播信道发送连接请求 (Connection Request)。对于广播者来说，它可以设置 *接受列表 (Accept List)* 以过滤不受信任的设备，或接受任一扫描者的连接请求。随后，广播者转变为外围设备，扫描者转变为中央设备，两者之间可以在数据信道进行双向通信。
+当扫描者在某一个广播信道接收到一个广播数据包时，若该广播者是可连接的，那么扫描者可以在同一广播信道发送连接请求 (Connection Request)。对于广播者来说，它可以设置 *接受列表 (Filter Accept List)* 以过滤不受信任的设备，或接受任一扫描者的连接请求。随后，广播者转变为外围设备，扫描者转变为中央设备，两者之间可以在数据信道进行双向通信。
 
 如 :ref:`扫描请求与扫描响应 <scan_request_and_scan_response>` 所述，广播者在每一个信道的广播结束以后，都会短暂进入 RX 模式，以接收可能的扫描请求。实际上，这个 RX 过程中还可以接受连接请求。所以对于扫描者来说，发送连接请求的时间窗口和发送扫描请求的时间窗口是类似的。
 
@@ -73,7 +73,7 @@
 
 外围设备延迟 (Peripheral Latency) 规定了外围设备在无需发送数据的前提下，最多可忽略的连接事件数量。
 
-为了理解这个连接参数的作用，让我们以蓝牙鼠标为例，分析其应用场景。用户在使用键盘的过程中，鼠标并没有需要发送的有效数据，此时最好降低数据包发送的频率以节省电量；在使用鼠标的过程中，我们希望鼠标能够尽可能快地发送数据，以降低使用延迟。也就是说，蓝牙鼠标的数据发送是间歇性高频率的。此时，如果仅靠连接间隔参数进行连接调节，则那么较低的连接间隔会导致高能耗，较高的连接间隔会导致高延迟。
+为了理解这个连接参数的作用，让我们以蓝牙鼠标为例。用户在使用键盘的过程中，鼠标并没有需要发送的有效数据，此时最好降低数据包发送的频率以节省电量；在使用鼠标的过程中，我们希望鼠标能够尽可能快地发送数据，以降低使用延迟。也就是说，蓝牙鼠标的数据发送是间歇性高频率的。此时，如果仅靠连接间隔参数进行连接调节，则那么较低的连接间隔会导致高能耗，较高的连接间隔会导致高延迟。
 
 在这种场景下，外围设备延迟机制将是一个完美的解决方案。为了降低蓝牙鼠标的延迟，我们可以将连接间隔设为一个较小的值，例如 10 ms ，那么在密集使用时数据交换频率可达 100 Hz ；随后，我们将外围设备延迟设定为 100 ，那么蓝牙鼠标在不使用的状态下，实际的数据交换频率可降低至 1 Hz 。通过这种设计，我们在不调整连接参数的前提下，实现了可变的数据交换频率，在最大程度上提升了用户体验。
 
@@ -132,17 +132,17 @@ MTU 可以设定为更大的值，例如 140 字节。在 Bluetooth LE 4.2 以
 例程实践
 -------------------------------------------
 
-在掌握了连接的相关知识以后，接下来让我们结合 NimBLE_Connection 例程代码，学习如何使用 NimBLE 协议栈构建一个简单的外围设备，对学到的知识进行实践。
+在掌握了连接的相关知识以后，接下来让我们结合 :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` 例程代码，学习如何使用 NimBLE 协议栈构建一个简单的外围设备，对学到的知识进行实践。
 
 
 前提条件
 ^^^^^^^^^^^^^^^
 
-1. 一块支持 Bluetooth LE 的 {IDF_TARGET_NAME} 开发板
+1. 一块 {IDF_TARGET_NAME} 开发板
 2. ESP-IDF 开发环境
-3. 在手机上安装 nRF Connect for Mobile 应用程序
+3. 在手机上安装 **nRF Connect for Mobile** 应用程序
 
-若你尚未完成 ESP-IDF 开发环境的配置，请参考 :doc:`API 参考 <../../../get-started/index>`。
+若你尚未完成 ESP-IDF 开发环境的配置，请参考 :doc:`IDF 快速入门 <../../../get-started/index>`。
 
 
 动手试试
@@ -173,7 +173,7 @@ MTU 可以设定为更大的值，例如 140 字节。在 Bluetooth LE 4.2 以
 
     $ idf.py set-target <chip-name>
 
-你应该能看到命令行以
+你应该能看到以下命令行
 
 .. code-block:: shell
 
@@ -188,7 +188,7 @@ MTU 可以设定为更大的值，例如 140 字节。在 Bluetooth LE 4.2 以
 
     $ idf.py flash monitor
 
-你应该能看到命令行以
+你应该能看到以下命令行以
 
 .. code-block:: shell
 
@@ -201,7 +201,7 @@ MTU 可以设定为更大的值，例如 140 字节。在 Bluetooth LE 4.2 以
 连接，然后断开
 ##############################
 
-打开手机上的 nRF Connect for Mobile 程序，在 SCANNER 标签页中下拉刷新，找到 NimBLE_CONN 设备，如下图所示
+打开手机上的 **nRF Connect for Mobile** 程序，在 **SCANNER** 标签页中下拉刷新，找到 NimBLE_CONN 设备，如下图所示
 
 .. figure:: ../../../../_static/ble/ble-connection-device-list.jpg
     :align: center
@@ -211,9 +211,9 @@ MTU 可以设定为更大的值，例如 140 字节。在 Bluetooth LE 4.2 以
 
 若设备列表较长，建议以 NimBLE 为关键字进行设备名过滤，快速找到 NimBLE_CONN 设备。
 
-与 :ref:`NimBLE_Beacon <nimble_beacon_details>` 相比，可以观察到大部分广播数据是一致的，但多了一项 `Advertising Interval` 数据，其值为 500 ms ；在 `CONNECT` 按钮下方，确实也可以观察到广播间隔为 510 ms 左右。
+与 :ref:`NimBLE_Beacon <nimble_beacon_details>` 相比，可以观察到大部分广播数据是一致的，但多了一项 `Advertising Interval` 数据，其值为 500 ms ；在 **CONNECT** 按钮下方，确实也可以观察到广播间隔为 510 ms 左右。
 
-点击 `CONNECT` 按钮连接到设备，在手机上应能够看到 GAP 服务，如下
+点击 **CONNECT** 按钮连接到设备，在手机上应能够看到 GAP 服务，如下
 
 .. figure:: ../../../../_static/ble/ble-connection-connected.jpg
     :align: center
@@ -221,7 +221,7 @@ MTU 可以设定为更大的值，例如 140 字节。在 Bluetooth LE 4.2 以
 
     连接到 NimBLE_CONN 设备
 
-此时应该还能观察到开发板上的 LED 亮起。点击 `DISCONNECT`，断开与设备的连接，此时应能观察到开发板上的 LED 熄灭。
+此时应该还能观察到开发板上的 LED 亮起。点击 **DISCONNECT**，断开与设备的连接，此时应能观察到开发板上的 LED 熄灭。
 
 若你的开发板上没有电源指示灯以外的 LED ，你应该能在日志输出中观察到对应的状态指示。
 
@@ -279,7 +279,7 @@ MTU 可以设定为更大的值，例如 140 字节。在 Bluetooth LE 4.2 以
 
 .. _nimble_connection_project_structure:
 
-NimBLE_Connection 的根目录结构与 :ref:`NimBLE_Beacon <nimble_beacon_project_structure>` 完全一致，不过在完成了固件的构建以后，你可能会观察到根目录下多了一个 `managed_components` 目录，里面含有固件构建时自动引入的依赖；本例中为 `led_strip` 组件，用于控制开发板的 LED。该依赖项在 `main/idf_component.yml` 文件中被引入。
+:example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` 的根目录结构与 :ref:`NimBLE_Beacon <nimble_beacon_project_structure>` 完全一致，不过在完成了固件的构建以后，你可能会观察到根目录下多了一个 `managed_components` 目录，里面含有固件构建时自动引入的依赖；本例中为 `led_strip` 组件，用于控制开发板的 LED。该依赖项在 `main/idf_component.yml` 文件中被引入。
 
 另外，在 `main` 文件夹中引入了 LED 控制相关的源代码。
 
@@ -472,6 +472,6 @@ GAP 事件处理
 总结
 ----------------
 
-通过本教程，你了解了连接的基本概念，并通过 NimBLE_Connection 例程掌握了使用 NimBLE 主机层协议栈构建 Bluetooth LE 外围设备的方法。
+通过本教程，你了解了连接的基本概念，并通过 :example:`NimBLE_Connection <bluetooth/ble_get_started/nimble/NimBLE_Connection>` 例程掌握了使用 NimBLE 主机层协议栈构建 Bluetooth LE 外围设备的方法。
 
 你可以尝试对例程中的参数进行修改，并在日志输出中观察修改结果。例如，你可以修改外围设备延迟或连接超时参数，观察连接参数的修改是否能够触发连接更新事件。
diff --git a/docs/zh_CN/api-guides/ble/get-started/ble-data-exchange.rst b/docs/zh_CN/api-guides/ble/get-started/ble-data-exchange.rst
index 91a4a96cbe1..dc0450ccb6f 100644
--- a/docs/zh_CN/api-guides/ble/get-started/ble-data-exchange.rst
+++ b/docs/zh_CN/api-guides/ble/get-started/ble-data-exchange.rst
@@ -3,7 +3,7 @@
 
 :link_to_translation:`en:[English]`
 
-本文档为低功耗蓝牙 (Bluetooth Low Energy, Bluetooth LE) 入门教程其四，旨在对 Bluetooth LE 连接中的数据交换过程进行简要介绍。随后，本教程会结合 NimBLE_GATT_Server 例程，基于 NimBLE 主机层协议栈，对 GATT 服务器的代码实现进行介绍。
+本文档为低功耗蓝牙 (Bluetooth Low Energy, Bluetooth LE) 入门教程其四，旨在对 Bluetooth LE 连接中的数据交换过程进行简要介绍。随后，本教程会结合 :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` 例程，基于 NimBLE 主机层协议栈，对 GATT 服务器的代码实现进行介绍。
 
 
 学习目标
@@ -11,7 +11,7 @@
 
 - 学习特征数据和服务的数据结构细节
 - 学习 GATT 的不同数据访问操作
-- 学习 NimBLE_GATT_Server 例程的代码结构
+- 学习 :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` 例程的代码结构
 
 
 GATT 数据特征与服务
@@ -203,7 +203,7 @@ CCCD 的 UUID 是 `0x2902`，属性值中仅含 2 比特信息。第一个比特
 
 .. _attribute_table:
 
-下面以 NimBLE_GATT_Server 为例，展示一个 GATT 服务器可能的属性表形态。例程中含有两个服务，分别是 Heart Rate Service 和 Automation IO Service ；前者含有一个 Heart Rate Measurement 特征数据，后者含有一个 LED 特征数据。整个 GATT 服务器有属性表如下
+下面以 :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` 为例，展示一个 GATT 服务器可能的属性表形态。例程中含有两个服务，分别是 Heart Rate Service 和 Automation IO Service ；前者含有一个 Heart Rate Measurement 特征数据，后者含有一个 LED 特征数据。整个 GATT 服务器有属性表如下
 
 +-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
 | Handle      | UUID                                     | Permissions     | Value                                           | Attribute Type             |
@@ -232,7 +232,9 @@ CCCD 的 UUID 是 `0x2902`，属性值中仅含 2 比特信息。第一个比特
 |             |                                          |                 +-------------------------------------------------+                            |
 |             |                                          |                 | UUID = `0x00001525-1212-EFDE-1523-785FEABCD123` |                            |
 +-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
-| 6           | `0x00001525-1212-EFDE-1523-785FEABCD123` | Write-only      | LED status                                      | Characteristic Value       |
+| 6           | `0x00001525-1212-EFDE-`                  |Write-only       | LED status                                      |Characteristic Value        |
+|             | `1523-785FE`                             |                 |                                                 |                            |
+|             | `ABCD123`                                |                 |                                                 |                            |
 +-------------+------------------------------------------+-----------------+-------------------------------------------------+----------------------------+
 
 GATT 客户端在与 GATT 服务器初次建立通信时，会从 GATT 服务器拉取属性表中的元信息，从而获取 GATT 服务器上可用的服务以及数据特征。这一过程被称为 *服务发现 (Service Discovery)*。
@@ -243,26 +245,23 @@ GATT 数据操作
 
 .. _gatt_data_operation:
 
-数据操作指的是对 GATT 服务器上的特征数据进行访问的操作，主要可以分为
+数据操作指的是对 GATT 服务器上的特征数据进行访问的操作，主要可以分为以下两类：
 
 1. 由客户端发起的操作
 2. 由服务器发起的操作
 
-两类。
-
 
 由客户端发起的操作
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 由客户端发起的操作有以下三种
 
-1. 读 (Read)
-2. 写 (Write)
-3. 写（无需响应） (Write without response)
-
-读操作比较简单，单纯是从 GATT 服务器上拉取某一特征数据的当前值。
-
-写操作分两种。普通的写操作要求 GATT 服务器在收到客户端的写请求以及对应数据以后，进行确认响应；快速写操作则不需要服务器进行确认响应。
+- **读 (Read)**
+    - 从 GATT 服务器上拉取某一特征数据的当前值。
+- **写 (Write)**
+    - 普通的写操作要求 GATT 服务器在收到客户端的写请求以及对应数据以后，进行确认响应。
+- **写（无需响应） (Write without response)**
+    - 快速写操作则不需要服务器进行确认响应。
 
 
 由服务器发起的操作
@@ -270,10 +269,10 @@ GATT 数据操作
 
 由服务器发起的操作分两种
 
-1. 通知 (Notify)
-2. 指示 (Indicate)
-
-通知和指示都是 GATT 服务器主动向客户端推送数据的操作，区别在于通知无需客户端回复确认响应，而指示需要。所以，指示的数据推送速度比通知慢。
+- **通知 (Notify)**
+    - 通知是 GATT 服务器主动向客户端推送数据的操作，不需要客户端回复确认响应。
+- **指示 (Indicate)**
+    - 与通知相似，区别在于指示需要客户端回复确认，因此数据推送速度比通知慢。
 
 虽然通知和指示都是由服务器发起的操作，但是服务器发起操作的前提是，客户端启用了通知或指示。所以，本质上 GATT 的数据交换过程总是以客户端请求数据开始。
 
@@ -281,23 +280,23 @@ GATT 数据操作
 例程实践
 -------------------------------------------
 
-在掌握了 GATT 数据交换的相关知识以后，接下来让我们结合 NimBLE_GATT_Server 例程代码，学习如何使用 NimBLE 协议栈构建一个简单的 GATT 服务器，对学到的知识进行实践。
+在掌握了 GATT 数据交换的相关知识以后，接下来让我们结合 :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` 例程代码，学习如何使用 NimBLE 协议栈构建一个简单的 GATT 服务器，对学到的知识进行实践。
 
 
 前提条件
 ^^^^^^^^^^^^^^^
 
-1. 一块支持 Bluetooth LE 的 {IDF_TARGET_NAME} 开发板
+1. 一块 {IDF_TARGET_NAME} 开发板
 2. ESP-IDF 开发环境
 3. 在手机上安装 nRF Connect for Mobile 应用程序
 
-若你尚未完成 ESP-IDF 开发环境的配置，请参考 :doc:`API 参考 <../../../get-started/index>`。
+若你尚未完成 ESP-IDF 开发环境的配置，请参考 :doc:`IDF 快速入门 <../../../get-started/index>`。
 
 
 动手试试
 ^^^^^^^^^^^^^^^^^^
 
-请参考 :ref:`动手试试 <nimble_gatt_server_practice>` 。
+请参考 :ref:`BLE 介绍 动手试试 <nimble_gatt_server_practice>` 。
 
 
 代码详解
@@ -307,7 +306,7 @@ GATT 数据操作
 工程结构综述
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-NimBLE_GATT_Server 的根目录结构与 :ref:`NimBLE_Connection <nimble_connection_project_structure>` 完全一致。另外，在 `main` 文件夹中引入了与 GATT 服务以及模拟心率生成相关的源代码。
+:example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` 的根目录结构与 :ref:`NimBLE_Connection <nimble_connection_project_structure>` 完全一致。另外，在 `main` 文件夹中引入了与 GATT 服务以及模拟心率生成相关的源代码。
 
 
 程序行为综述
@@ -659,6 +658,4 @@ LED 特征数据的访问通过 `led_chr_access` 回调函数管理，相关代
 总结
 ----------------------------
 
-通过本教程，你了解了如何通过服务表创建 GATT 服务以及相应的特征数据，并掌握了 GATT 特征数据的访问管理方式，包括读、写和订阅操作的实现。你可以在 NimBLE_GATT_Server 例程的基础上，开发更加复杂的 GATT 服务应用。
-
-
+通过本教程，你了解了如何通过服务表创建 GATT 服务以及相应的特征数据，并掌握了 GATT 特征数据的访问管理方式，包括读、写和订阅操作的实现。你可以在 :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` 例程的基础上，开发更加复杂的 GATT 服务应用。
diff --git a/docs/zh_CN/api-guides/ble/get-started/ble-device-discovery.rst b/docs/zh_CN/api-guides/ble/get-started/ble-device-discovery.rst
index 245eee9a6d0..19ca21b428f 100644
--- a/docs/zh_CN/api-guides/ble/get-started/ble-device-discovery.rst
+++ b/docs/zh_CN/api-guides/ble/get-started/ble-device-discovery.rst
@@ -3,7 +3,7 @@
 
 :link_to_translation:`en:[English]`
 
-本文档为低功耗蓝牙 (Bluetooth Low Energy, Bluetooth LE) 入门教程其二，旨在对 Bluetooth LE 设备发现过程进行简要介绍，包括广播与扫描相关的基本概念。随后，本教程会结合 NimBLE_Beacon 例程，基于 NimBLE 主机层协议栈，对 Bluetooth LE 广播的代码实现进行介绍。
+本文档为低功耗蓝牙 (Bluetooth Low Energy, Bluetooth LE) 入门教程其二，旨在对 Bluetooth LE 设备发现过程进行简要介绍，包括广播与扫描相关的基本概念。随后，本教程会结合 :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` 例程，基于 NimBLE 主机层协议栈，对 Bluetooth LE 广播的代码实现进行介绍。
 
 
 学习目标
@@ -11,7 +11,7 @@
 
 - 学习广播的基本概念
 - 学习扫描的基本概念
-- 学习 NimBLE_Beacon 例程的代码结构
+- 学习 :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` 例程的代码结构
 
 
 广播 (Advertising) 与扫描 (Scanning) 是 Bluetooth LE 设备在进入连接前在设备发现 (Device Discovery) 阶段的工作状态。下面，我们先了解与广播有关的基本概念。
@@ -33,7 +33,7 @@
 蓝牙的无线电频段
 ################################
 
-第一个问题指向的是，广播数据包应发送到哪一无线电频段。这个回答由蓝牙核心规范给出，答案是 2.4 GHz ISM 频段。选择该频段的理由是， 2.4 GHz ISM 频段是一个全球可用的免费无线电频段，不被任何国家以军事用途等理由管控，也无需向任何组织支付许可费用，因此该频段的可用性极高，且没有任何使用成本。不过，这也意味着 2.4 GHz ISM 频段非常拥挤，可能会与其他无线通信协议发生数据冲突，如 2.4 GHz WiFi。
+第一个问题指向的是，广播数据包应发送到哪一无线电频段。这个回答由蓝牙核心规范给出，答案是 2.4 GHz ISM 频段。2.4 GHz ISM 频段是一个全球可用的免费无线电频段，不被任何国家以军事用途等理由管控，也无需向任何组织支付许可费用，因此该频段的可用性极高，且没有任何使用成本。不过，这也意味着 2.4 GHz ISM 频段非常拥挤，可能会与其他无线通信协议发生数据冲突，如 2.4 GHz WiFi。
 
 
 蓝牙信道
@@ -87,7 +87,7 @@ Bluetooth LE 4.2 标准中，广播数据包允许搭载最多 31 字节广播
         -   254
         -   1650
 
-扩展广播数据包由 ADV_EXT_IND 和 AUX_ADV_IND 组成，分别在主广播信道 (Primary Advertising Channel) 和次广播信道 (Secondary Advertising Channel) 上传输。其中，主广播信道对应于信道 37-39 ，次广播信道对应于信道 0-36 。由于接收方总是在主广播信道中接收广播数据，因此发送方在发送扩展广播数据包时，应在主广播信道中发送 ADV_EXT_IND ，在次广播信道中发送 AUX_ADV_IND ，并在 ADV_EXT_IND 中指示 AUX_ADV_IND 所在的次广播信道；通过这种机制，接收方能够在接收到主广播信道的 ADV_EXT_IND 以后，根据指示到指定的次广播信道去接收 AUX_ADV_IND ，从而得到完整的扩展广播数据包。
+扩展广播数据包由 `ADV_EXT_IND` 和 `AUX_ADV_IND` 组成，分别在主广播信道 (Primary Advertising Channel) 和次广播信道 (Secondary Advertising Channel) 上传输。其中，主广播信道对应于信道 37-39 ，次广播信道对应于信道 0-36 。由于接收方总是在主广播信道中接收广播数据，因此发送方在发送扩展广播数据包时，应在主广播信道中发送 `ADV_EXT_IND` ，在次广播信道中发送 `AUX_ADV_IND` ，并在 `ADV_EXT_IND` 中指示 `AUX_ADV_IND` 所在的次广播信道；通过这种机制，接收方能够在接收到主广播信道的 `ADV_EXT_IND` 以后，根据指示到指定的次广播信道去接收 `AUX_ADV_IND` ，从而得到完整的扩展广播数据包。
 
 .. list-table::
     :align: center
@@ -99,10 +99,10 @@ Bluetooth LE 4.2 标准中，广播数据包允许搭载最多 31 字节广播
         -   作用
     *   -   主广播信道 (Primary Advertising Channel)
         -   37-39
-        -   用于传输扩展广播数据包的 ADV_EXT_IND
+        -   用于传输扩展广播数据包的 `ADV_EXT_IND`
     *   -   次广播信道 (Secondary Advertising Channel)
         -   0-36
-        -   用于传输扩展广播数据包的 AUX_ADV_IND
+        -   用于传输扩展广播数据包的 `AUX_ADV_IND`
 
 
 发送广播数据包的周期取多久？
@@ -111,11 +111,11 @@ Bluetooth LE 4.2 标准中，广播数据包允许搭载最多 31 字节广播
 广播间隔
 ##################
 
-对于第二个问题，即发送广播数据包的周期怎么取，蓝牙标准中也给出了一个明确的参数定义，即广播间隔 (Advertising Interval)。广播间隔可取的范围为 20 ms 到 10.24 s ，取值步长为 0.625 ms。
+对于第二个问题，即发送广播数据包的周期怎么取，蓝牙标准中也给出了一个明确的参数定义，即广播间隔 （Advertising Interval）。广播间隔可取的范围为 20 ms 到 10.24 s ，取值步长为 0.625 ms。
 
-广播间隔的取值决定了广播者的可发现性 (Discoverability)以及设备功耗。当广播间隔取得太长时，广播数据包被接收方接收到的概率就会变得很低，此时广播者的可发现性就会变差。同时，广播间隔也不宜取得太短，因此频繁发送广播数据需要消耗更多的电量。所以，广播者需要在可发现性和能耗之间进行取舍，根据应用场景的需求选择最合适的广播间隔。
+广播间隔的取值决定了广播者的可发现性 （Discoverability） 以及设备功耗。当广播间隔取得太长时，广播数据包被接收方接收到的概率就会变得很低，此时广播者的可发现性就会变差。同时，广播间隔也不宜取得太短，因此频繁发送广播数据需要消耗更多的电量。所以，广播者需要在可发现性和能耗之间进行取舍，根据应用场景的需求选择最合适的广播间隔。
 
-值得一提的是，如果在同一空间中存在两个广播间隔相同的广播者，那么有概率出现重复性的撞包 (Packet Collision) 现象，即两个广播者总是在同一时刻向同一信道发送广播数据。由于广播是一个只发不收的过程，广播者无法得知是否发生了广播撞包。为了降低上述问题的发生概率，广播者应在每一次广播事件后添加 0-10 ms 的随机时延。
+值得一提的是，如果在同一空间中存在两个广播间隔相同的广播者，那么有概率出现重复性的撞包 （Packet Collision） 现象，即两个广播者总是在同一时刻向同一信道发送广播数据。由于广播是一个只发不收的过程，广播者无法得知是否发生了广播撞包。为了降低上述问题的发生概率，广播者应在每一次广播事件后添加 0-10 ms 的随机时延。
 
 
 广播数据包里包含哪些信息？
@@ -201,7 +201,7 @@ PDU 头中含有较多信息，可以分为以下六个部分
 
     *   -   序号
         -   名称
-        -   位数
+        -   比特位数
         -   备注
     *   -   1
         -   PDU 类型 (PDU Type)
@@ -222,7 +222,7 @@ PDU 头中含有较多信息，可以分为以下六个部分
     *   -   5
         -   接收地址类型 (Rx Address, **RxAdd**)
         -   1
-        -   同上
+        -   0/1 分别表示公共地址/随机地址
     *   -   6
         -   有效负载长度 (Payload Length)
         -   8
@@ -336,7 +336,7 @@ PDU 有效负载也分为两部分
     *   -   不可解析随机私有地址 (Non-resolvable Random Private Address)
         -   完全随机的地址，仅用于防止设备被追踪，非常少用
 
-然后看广播数据。一个广播数据结构的格式定义如下
+然后看**广播数据**。一个广播数据结构的格式定义如下
 
 .. list-table::
     :align: center
@@ -370,7 +370,8 @@ PDU 有效负载也分为两部分
 2. 多久扫描一次？一次扫描多久？ (When?)
 3. 扫描的过程中需要做什么？ (What?)
 
-第一个问题已经在广播的介绍中说明了。对于 Bluetooth LE 4.2 设备来说，广播者只会在广播信道，即编号为 37-39 的三个信道发送广播数据；对于 Bluetooth LE 5.0 设备来说，如果广播者启用了扩展广播特性，则会在主广播信道发送 ADV_EXT_IND ，在次广播信道发送 AUX_ADV_IND ，并在 ADV_EXT_IND 指示 AUX_ADV_IND 所在的次广播信道。所以相应的，对于 Bluetooth LE 4.2 设备来说，扫描者只需在广播信道接收广播数据包即可。对于 Bluetooth LE 5.0 设备来说，扫描者应在主广播信道接收主广播数据包和扩展广播数据包的 ADV_EXT_IND ； 若扫描者接收到了 ADV_EXT_IND ，且 ADV_EXT_IND 指示了一个次广播信道，那么还需要到对应的次广播信道去接收 AUX_ADV_IND ，以获取完整的扩展广播数据包。
+第一个问题已经在广播的介绍中说明了。对于 Bluetooth LE 4.2 设备来说，广播者只会在广播信道，即编号为 37-39 的三个信道发送广播数据；对于 Bluetooth LE 5.0 设备来说，如果广播者启用了扩展广播特性，则会在主广播信道发送 `ADV_EXT_IND` ，在次广播信道发送 `AUX_ADV_IND` ，并在 `ADV_EXT_IND` 指示 `AUX_ADV_IND` 所在的次广播信道。
+所以相应的，对于 Bluetooth LE 4.2 设备来说，扫描者只需在广播信道接收广播数据包即可。对于 Bluetooth LE 5.0 设备来说，扫描者应在主广播信道接收主广播数据包和扩展广播数据包的 `ADV_EXT_IND` ； 若扫描者接收到了 `ADV_EXT_IND` ，且 `ADV_EXT_IND` 指示了一个次广播信道，那么还需要到对应的次广播信道去接收 `AUX_ADV_IND` ，以获取完整的扩展广播数据包。
 
 
 扫描窗口与扫描间隔
@@ -378,9 +379,9 @@ PDU 有效负载也分为两部分
 
 第二个问题分别指向扫描窗口 (Scan Window) 和 扫描间隔 (Scan Interval) 概念。
 
-首先对扫描窗口进行说明。扫描窗口指的是扫描者在同一个 RF 信道持续接收蓝牙数据包的持续时间，例如扫描窗口参数设定为 50 ms 时，扫描者在每个 RF 信道都会不间断地扫描 50 ms。
+- **扫描窗口**：扫描者在同一个 RF 信道持续接收蓝牙数据包的持续时间，例如扫描窗口参数设定为 50 ms 时，扫描者在每个 RF 信道都会不间断地扫描 50 ms。
 
-扫描间隔则指的是相邻两个扫描窗口开始时刻之间的时间间隔，所以扫描间隔必然大于等于扫描窗口。
+- **扫描间隔**：相邻两个扫描窗口开始时刻之间的时间间隔，所以扫描间隔必然大于等于扫描窗口。
 
 下图在时间轴上展示了扫描者的广播数据包接收过程，其中扫描者的扫描间隔为 100 ms ，扫描窗口为 50 ms ；广播者的广播间隔为 50 ms ，广播数据包的发送时长仅起到示意作用。可以看到，第一个扫描窗口对应 37 信道，此时扫描者恰好接收到了广播者第一次在 37 信道发送的广播数据包，以此类推。
 
@@ -419,17 +420,17 @@ PDU 有效负载也分为两部分
 例程实践
 -------------------------------------------
 
-在掌握了广播与扫描的相关知识以后，接下来让我们结合 NimBLE_Beacon 例程代码，学习如何使用 NimBLE 协议栈构建一个简单的 Beacon 设备，对学到的知识进行实践。
+在掌握了广播与扫描的相关知识以后，接下来让我们结合 :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` 例程代码，学习如何使用 NimBLE 协议栈构建一个简单的 Beacon 设备，对学到的知识进行实践。
 
 
 前提条件
 ^^^^^^^^^^^^^^^
 
-1. 一块支持 Bluetooth LE 的 {IDF_TARGET_NAME} 开发板
+1. 一块 {IDF_TARGET_NAME} 开发板
 2. ESP-IDF 开发环境
-3. 在手机上安装 nRF Connect for Mobile 应用程序
+3. 在手机上安装 **nRF Connect for Mobile** 应用程序
 
-若你尚未完成 ESP-IDF 开发环境的配置，请参考 :doc:`API 参考 <../../../get-started/index>`。
+若你尚未完成 ESP-IDF 开发环境的配置，请参考 :doc:`IDF 快速入门 <../../../get-started/index>`。
 
 
 动手试试
@@ -460,7 +461,7 @@ PDU 有效负载也分为两部分
 
     $ idf.py set-target <chip-name>
 
-你应该能看到命令行以
+你应该能看到以下命令行
 
 .. code-block:: shell
 
@@ -475,7 +476,7 @@ PDU 有效负载也分为两部分
 
     $ idf.py flash monitor
 
-你应该能看到命令行以
+你应该能看到以下命令行
 
 .. code-block:: shell
 
@@ -490,7 +491,7 @@ PDU 有效负载也分为两部分
 
 .. _nimble_beacon_details:
 
-打开手机上的 nRF Connect for Mobile 程序，在 SCANNER 标签页中下拉刷新，找到 NimBLE_Beacon 设备，如下图所示
+打开手机上的 **nRF Connect for Mobile** 程序，在 SCANNER 标签页中下拉刷新，找到 NimBLE_Beacon 设备，如下图所示
 
 .. figure:: ../../../../_static/ble/ble-scan-list-nimble-beacon.jpg
     :align: center
@@ -501,7 +502,7 @@ PDU 有效负载也分为两部分
 
 若设备列表较长，建议以 NimBLE 为关键字进行设备名过滤，快速找到 NimBLE_Beacon 设备。
 
-观察到 NimBLE Beacon 设备下带有丰富的设备信息，甚至还带有乐鑫的网址（这就是信标广告功能的体现）。点击右下角的 `RAW` 按钮，可以看到广播数据包的原始信息，如下
+观察到 NimBLE Beacon 设备下带有丰富的设备信息，甚至还带有乐鑫的网址（这就是信标广告功能的体现）。点击右下角的 **RAW** 按钮，可以看到广播数据包的原始信息，如下
 
 .. figure:: ../../../../_static/ble/ble-adv-packet-raw-data.jpg
     :align: center
@@ -510,7 +511,7 @@ PDU 有效负载也分为两部分
 
     广播数据包原始信息
 
-Details 表格即广播数据包和扫描响应数据包中的所有广播数据结构，可以整理如下
+**Details** 表格即广播数据包和扫描响应数据包中的所有广播数据结构，可以整理如下
 
 .. list-table::
     :align: center
@@ -523,37 +524,37 @@ Details 表格即广播数据包和扫描响应数据包中的所有广播数据
         -   原始数据
         -   解析值
     *   -   标志位
-        -   2
+        -   2 Bytes
         -   `0x01`
         -   `0x06`
         -   General Discoverable, BR/EDR Not Supported
     *   -   完整设备名称
-        -   14
+        -   14 Bytes
         -   `0x09`
         -   `0x4E696D424C455F426561636F6E`
         -   NimBLE_Beacon
     *   -   发送功率等级
-        -   2
+        -   2 Bytes
         -   `0x0A`
         -   `0x09`
         -   9 dBm
     *   -   设备外观
-        -   3
+        -   3 Bytes
         -   `0x19`
         -   `0x0002`
         -   通用标签
     *   -   LE 角色
-        -   2
+        -   2 Bytes
         -   `0x1C`
         -   `0x00`
         -   仅支持外设设备
     *   -   设备地址
-        -   8
+        -   8 Bytes
         -   `0x1B`
         -   `0x46F506BDF5F000`
         -   `F0:F5:BD:06:F5:46`
     *   -   URI
-        -   17
+        -   17 Bytes
         -   `0x24`
         -   `0x172F2F6573707265737369662E636F6D`
         -   `https://espressif.com`
@@ -562,7 +563,7 @@ Details 表格即广播数据包和扫描响应数据包中的所有广播数据
 
 你可能还注意到，对应于设备外观的 Raw Data 为 `0x0002`，而代码中对 Generic Tag 的定义是 `0x0200`；还有，设备地址的 Raw Data 除了最后一个字节 `0x00` 以外，似乎与实际地址完全颠倒。这是因为， Bluetooth LE 的空中数据包遵循小端 (Little Endian) 传输的顺序，所以低字节的数据反而会在靠前的位置。
 
-另外，注意到 nRF Connect for Mobile 程序并没有为我们提供 `CONNECT` 按钮以连接至此设备。这符合我们的预期，因为 Beacon 设备本来就应该是不可连接的。下面，让我们深入代码细节，看看这样的一个 Beacon 设备是怎样实现的。
+另外，注意到 **nRF Connect for Mobile** 程序并没有为我们提供 **CONNECT** 按钮以连接至此设备。这符合我们的预期，因为 Beacon 设备本来就应该是不可连接的。下面，让我们深入代码细节，看看这样的一个 Beacon 设备是怎样实现的。
 
 
 代码详解
@@ -574,7 +575,7 @@ Details 表格即广播数据包和扫描响应数据包中的所有广播数据
 
 .. _nimble_beacon_project_structure:
 
-NimBLE_Beacon 的根目录大致分为以下几部分
+:example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` 的根目录大致分为以下几部分
 
 - `README*.md`
     - 工程的说明文档
@@ -611,7 +612,7 @@ NimBLE_Beacon 的根目录大致分为以下几部分
 2. 初始化 GAP 服务
 3. 启动 NimBLE 主机层的 FreeRTOS 线程
 
-ESP32 的蓝牙协议栈使用 NVS Flash 存储相关配置，所以在初始化蓝牙协议栈之前，必须调用 `nvs_flash_init` API 以初始化 NVS Flash ，某些情况下需要调用 `nvs_flash_erase` API 对 NVS Flash 进行擦除后再初始化。
+{IDF_TARGET_NAME} 的蓝牙协议栈使用 NVS Flash 存储相关配置，所以在初始化蓝牙协议栈之前，必须调用 `nvs_flash_init` API 以初始化 NVS Flash ，某些情况下需要调用 `nvs_flash_erase` API 对 NVS Flash 进行擦除后再初始化。
 
 .. code-block:: C
 
@@ -879,6 +880,6 @@ ESP32 的蓝牙协议栈使用 NVS Flash 存储相关配置，所以在初始化
 总结
 ---------
 
-通过本教程，你了解了广播和扫描的基本概念，并通过 NimBLE_Beacon 例程掌握了使用 NimBLE 主机层协议栈构建 Bluetooth LE Beacon 设备的方法。
+通过本教程，你了解了广播和扫描的基本概念，并通过 :example:`NimBLE_Beacon <bluetooth/ble_get_started/nimble/NimBLE_Beacon>` 例程掌握了使用 NimBLE 主机层协议栈构建 Bluetooth LE Beacon 设备的方法。
 
 你可以尝试对例程中的数据进行修改，并在 nRF Connect for Mobile 调试工具中查看修改结果。例如，你可以尝试修改 `adv_fields` 或 `rsp_fields` 结构体，以修改被填充的广播数据结构，或者交换广播数据包和扫描响应数据包中的广播数据结构。但需要注意的一点是，广播数据包和扫描响应数据包的广播数据上限为 31 字节，若设定的广播数据结构大小超过该限值，调用 `ble_gap_adv_start` API 将会失败。
diff --git a/docs/zh_CN/api-guides/ble/get-started/ble-introduction.rst b/docs/zh_CN/api-guides/ble/get-started/ble-introduction.rst
index 430e41f5995..d37d28ce31e 100644
--- a/docs/zh_CN/api-guides/ble/get-started/ble-introduction.rst
+++ b/docs/zh_CN/api-guides/ble/get-started/ble-introduction.rst
@@ -47,7 +47,7 @@ Bluetooth LE 协议定义了三层软件结构，自上而下分别是
 
     Bluetooth LE 分层结构
 
-作为应用开发者，在开发过程中我们主要与主机层提供的 API 接口打交道，这要求我们对主机层中的蓝牙协议有一定的了解。接下来，我们会从连接和数据交互两个角度，对 GAP 和 GATT/ATT 层的基本概念进行介绍。
+作为应用开发者，在开发过程中我们主要与主机层提供的 API 接口打交道，这要求我们对主机层中的蓝牙协议有一定的了解。接下来，我们会从连接和数据交换两个角度，对 GAP 和 GATT/ATT 层的基本概念进行介绍。
 
 
 GAP 层 - 定义设备的连接
@@ -71,7 +71,7 @@ GAP 中共定义了三种设备的连接状态以及五种不同的设备角色
     - 外围设备 (Peripheral)
     - 中央设备 (Central)
 
-广播者向外广播的数据中包含设备地址等信息，用于向外界设备表明广播者的存在，并告知其他设备是否可以连接。扫描者则持续接收环境中的广播数据包。若某一个扫描者发现了一个可连接的广播者，并希望与之建立连接，可以将角色切换为连接发起者。当连接发起者再次收到该广播者的广播数据，会立即发起连接请求 (Connection Request)；在广播者未开启白名单 (White List, 又称 Accept List) 或连接发起者在广播者的白名单之中时，连接将被成功建立。
+广播者向外广播的数据中包含设备地址等信息，用于向外界设备表明广播者的存在，并告知其他设备是否可以连接。扫描者则持续接收环境中的广播数据包。若某一个扫描者发现了一个可连接的广播者，并希望与之建立连接，可以将角色切换为连接发起者。当连接发起者再次收到该广播者的广播数据，会立即发起连接请求 (Connection Request)；在广播者未开启白名单 (Filter Accept List, 又称 White List) 或连接发起者在广播者的白名单之中时，连接将被成功建立。
 
 进入连接以后，原广播者转变为外围设备（旧称从设备 Slave ），原扫描者或连接初始化者转变为中央设备（旧称主设备 Master ）。
 
@@ -112,7 +112,7 @@ GATT/ATT 层定义了进入连接状态后，设备之间的数据交换方式
 ATT 层
 #############
 
-ATT 的全称是属性协议 (Attribute Protocol, ATT)，定义了一种称为属性 (Attribute) 的基本数据结构，以及基于服务器/客户端架构的数据访问方式。
+ATT 的全称是属性协议 (Attribute Protocol, ATT)，定义了一种称为**属性 (Attribute)** 的基本数据结构，以及基于服务器/客户端架构的数据访问方式。
 
 简单来说，数据以属性的形式存储在服务器上，等待客户端的访问。以智能开关为例，开关量作为数据，以属性的形式存储在智能开关内的蓝牙芯片（服务器）中，此时用户可以通过手机（客户端）访问智能开关蓝牙芯片（服务器）上存放的开关量属性，获取当前的开关状态（读访问），或控制开关的闭合与断开（写访问）。
 
@@ -123,7 +123,7 @@ ATT 的全称是属性协议 (Attribute Protocol, ATT)，定义了一种称为
 - 值 (Value)
 - 访问权限 (Permissions)
 
-在协议栈实现中，属性一般被放在称为属性表 (Attribute Table) 的结构体数组中管理。一个属性在这张表中的索引，就是属性的句柄，常为一无符号整型。
+在协议栈实现中，属性一般被放在称为**属性表 (Attribute Table)** 的结构体数组中管理。一个属性在这张表中的索引，就是属性的句柄，常为一无符号整型。
 
 属性的类型由 UUID 表示，可以分为 16 位、32 位与 128 位 UUID 三类。 16 位 UUID 由蓝牙技术联盟 (Bluetooth Special Interest Group, Bluetooth SIG) 统一定义，可以在其公开发布的 `Assigned Numbers <https://www.bluetooth.com/specifications/assigned-numbers/>`__ 文件中查询；其他两种长度的 UUID 用于表示厂商自定义的属性类型，其中 128 位 UUID 较为常用。
 
@@ -155,7 +155,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 
 除此以外，特征数据中还可能包含若干可选的描述符属性 (Characteristic Descriptor Attribute)。
 
-一个服务本身也由一个属性进行描述，称为服务声明属性 (Service Declaration Attribute)。一个服务中可以存在一个或多个特征数据，它们之间体现为从属关系。另外，一个服务可以通过 Include 机制引用另一个服务，复用其特性定义，避免如设备名称、制造商信息等相同特性的重复定义。
+一个服务本身也由一个属性进行描述，称为服务声明属性 (Service Declaration Attribute)。一个服务中可以存在一个或多个特征数据，它们之间体现为从属关系。另外，一个服务可以通过 `Include` 机制引用另一个服务，复用其特性定义，避免如设备名称、制造商信息等相同特性的重复定义。
 
 规范是一个预定义的服务集合，实现了某规范中所定义的所有服务的设备即满足该规范。例如 Heart Rate Profile 规范由 Heart Rate Service 和 Device Information Service 两个服务组成，那么可以称实现了 Heart Rate Service 和 Device Information Service 服务的设备符合 Heart Rate Profile 规范。
 
@@ -178,11 +178,11 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 前提条件
 ^^^^^^^^^^^^^^^
 
-1. 一块支持 Bluetooth LE 的 {IDF_TARGET_NAME} 开发板
+1. 一块 {IDF_TARGET_NAME} 开发板
 2. ESP-IDF 开发环境
-3. 在手机上安装 nRF Connect for Mobile 应用程序
+3. 在手机上安装 **nRF Connect for Mobile** 应用程序
 
-若你尚未完成 ESP-IDF 开发环境的配置，请参考 :doc:`API 参考 <../../../get-started/index>`。
+若你尚未完成 ESP-IDF 开发环境的配置，请参考 :doc:`IDF 快速入门 <../../../get-started/index>`。
 
 
 动手试试
@@ -214,7 +214,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 
     $ idf.py set-target <chip-name>
 
-你应该能看到命令行以
+你应该能看到以下命令行
 
 .. code-block:: shell
 
@@ -229,7 +229,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 
     $ idf.py flash monitor
 
-你应该能看到命令行以
+你应该能看到以下命令行
 
 .. code-block:: shell
 
@@ -243,7 +243,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 连接到开发板
 #######################
 
-现在开发板已准备就绪。接下来，打开手机上的 nRF Connect for Mobile 程序，在 SCANNER 标签页中下拉刷新，找到 NimBLE_GATT 设备，如下图所示
+现在开发板已准备就绪。接下来，打开手机上的 **nRF Connect for Mobile** 程序，在 **SCANNER** 标签页中下拉刷新，找到 NimBLE_GATT 设备，如下图所示
 
 .. figure:: ../../../../_static/ble/ble-get-started-connect-brief.jpg
     :align: center
@@ -254,7 +254,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 
 若设备列表较长，建议以 NimBLE 为关键字进行设备名过滤，快速找到 NimBLE_GATT 设备。
 
-点击 NimBLE_GATT 设备条目，可以展开看到广播数据的详细信息。
+点击 **NimBLE_GATT** 设备条目，可以展开看到广播数据的详细信息。
 
 .. figure:: ../../../../_static/ble/ble-get-started-connect-details.jpg
     :align: center
@@ -263,7 +263,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 
     广播数据详情
 
-点击右侧的 CONNECT 按钮，在手机连接的同时，可以在开发板的串口输出中观察到许多与连接相关的日志信息。随后，手机上会显示 NimBLE_GATT 标签页，左上角应有 CONNECTED 状态，说明手机已成功通过 Bluetooth LE 协议连接至开发板。在 CLIENT 子页中，你应该能够看到四个 GATT 服务，如图所示
+点击右侧的 **CONNECT** 按钮，在手机连接的同时，可以在开发板的串口输出中观察到许多与连接相关的日志信息。随后，手机上会显示 NimBLE_GATT 标签页，左上角应有 **CONNECTED** 状态，说明手机已成功通过 Bluetooth LE 协议连接至开发板。在 CLIENT 子页中，你应该能够看到四个 GATT 服务，如图所示
 
 .. figure:: ../../../../_static/ble/ble-get-started-gatt-services-list.jpg
     :align: center
@@ -274,13 +274,13 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 
 前两个服务是 GAP 服务和 GATT 服务，这两个服务是 Bluetooth LE 应用中的基础服务。后两个服务是 Bluetooth SIG 定义的 Heart Rate Service 服务和 Automation IO Service 服务，分别提供心率数据读取和 LED 控制功能。
 
-在服务名的下方，对应有各个服务的 UUID 以及服务主次标识。如 Heart Rate Service 服务的 UUID 为 `0x180D`，是一个主服务 (Primary Service)。需要注意的是，服务的名称是通过 UUID 解析得到的。以 nRF Connect for Mobile 为例，在实现 GATT 客户端时，开发者会将 Bluetooth SIG 定义的服务，以及开发商 Nordic Semiconductor 自定义的服务预先写入数据库中，然后根据 GATT 服务的 UUID 进行服务信息解析。所以，假如某一服务的 UUID 不在数据库中，那么该服务的服务信息就无法被解析，服务名称将会显示为未知服务 (Unknown Service)。
+在服务名的下方，对应有各个服务的 UUID 以及服务主次标识。如 Heart Rate Service 服务的 UUID 为 `0x180D`，是一个主服务 (Primary Service)。需要注意的是，服务的名称是通过 UUID 解析得到的。以 nRF Connect for Mobile 为例，在实现 GATT 客户端时，开发者会将 Bluetooth SIG 定义的服务，以及例程自定义的服务预先写入数据库中，然后根据 GATT 服务的 UUID 进行服务信息解析。所以，假如某一服务的 UUID 不在数据库中，那么该服务的服务信息就无法被解析，服务名称将会显示为未知服务 (Unknown Service)。
 
 
 把灯点亮！
 ##################
 
-下面体验一下本例程的功能。首先，点击 Automation IO Service 服务，可以看到该服务下有一个 LED 特征数据。
+下面体验一下本例程的功能。首先，点击 **Automation IO Service** 服务，可以看到该服务下有一个 LED 特征数据。
 
 .. figure:: ../../../../_static/ble/ble-get-started-automation-io-service-details.jpg
     :align: center
@@ -289,7 +289,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 
     Automation IO Service
 
-如图，该 LED 特征数据的 UUID 为 128 位的厂商自定义 UUID 。实际上，这是 Nordic Semiconductor 自定义的 LED 特征数据，在 nRF Connect for Mobile 上有专门的控制页面适配。点击右侧的上传按钮，可以对该特征数据进行写访问，如下图所示。
+如图，该 LED 特征数据的 UUID 为 128 位的厂商自定义 UUID 。 点击右侧的**UPLOAD**按钮，可以对该特征数据进行写访问，如下图所示。
 
 .. figure:: ../../../../_static/ble/ble-get-started-led-write.jpg
     :align: center
@@ -298,7 +298,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 
     对 LED 特征数据进行写访问
 
-选择 ON 选项，然后发送，你应该能看到开发板上的 LED 被点亮了。选择 OFF 选项，然后发送，你应该能观察到开发板上的 LED 又熄灭了。
+选择 **ON** 选项，然后发送，你应该能看到开发板上的 LED 被点亮了。选择 **OFF** 选项，然后发送，你应该能观察到开发板上的 LED 又熄灭了。
 
 若你的开发板上没有电源指示灯以外的 LED ，你应该能在日志输出中观察到对应的状态指示。
 
@@ -306,7 +306,7 @@ GATT 的全称是通用属性规范 (Generic Attribute Profile)，在 ATT 的基
 接收心率数据
 #######################
 
-接下来，点击 Heart Rate Service 服务，可以看到该服务下有一个 Heart Rate Measurement 特征数据。
+接下来，点击 **Heart Rate Service** 服务，可以看到该服务下有一个 Heart Rate Measurement 特征数据。
 
 .. figure:: ../../../../_static/ble/ble-get-started-heart-rate-service-details.jpg
     :align: center
@@ -339,4 +339,4 @@ Heart Rate Measurement 特征数据的 UUID 是 `0x2A37`，这是一个 Bluetoot
 总结
 ---------
 
-通过本教程，你了解了 Bluetooth LE 的分层架构、Bluetooth LE 协议栈中主机层和控制器层的基本功能以及 GAP 层与 GATT/ATT 层的作用。随后，通过 NimBLE_GATT_Server 例程，你掌握了如何使用 ESP-IDF 开发框架进行 Bluetooth LE 应用的构建与烧录，能够在手机上使用 nRF Connect for Mobile 调试程序，远程控制开发板上 LED 的点亮与熄灭，以及接收随机生成的心率数据。你已经迈出了走向 Bluetooth LE 开发者的第一步，恭喜！
+通过本教程，你了解了 Bluetooth LE 的分层架构、Bluetooth LE 协议栈中主机层和控制器层的基本功能以及 GAP 层与 GATT/ATT 层的作用。随后，通过 :example:`NimBLE_GATT_Server <bluetooth/ble_get_started/nimble/NimBLE_GATT_Server>` 例程，你掌握了如何使用 ESP-IDF 开发框架进行 Bluetooth LE 应用的构建与烧录，能够在手机上使用 **nRF Connect for Mobile** 调试程序，远程控制开发板上 LED 的点亮与熄灭，以及接收随机生成的心率数据。你已经迈出了走向 Bluetooth LE 开发者的第一步，恭喜！
diff --git a/docs/zh_CN/api-guides/ble/host-feature-support-status.rst b/docs/zh_CN/api-guides/ble/host-feature-support-status.rst
index 2acb0855b37..d1134e17e5b 100644
--- a/docs/zh_CN/api-guides/ble/host-feature-support-status.rst
+++ b/docs/zh_CN/api-guides/ble/host-feature-support-status.rst
@@ -79,7 +79,7 @@ ESP 主机主要功能支持状态
       - |experimental|
       - |experimental|
     * -
-      - Advertising Channel Index
+      - Randomized Advertising Channel Indexing
       - |NA|
       - |NA|
     * -
diff --git a/docs/zh_CN/api-guides/ble/overview.rst b/docs/zh_CN/api-guides/ble/overview.rst
index 62dbc36db09..d9997eef481 100644
--- a/docs/zh_CN/api-guides/ble/overview.rst
+++ b/docs/zh_CN/api-guides/ble/overview.rst
@@ -13,13 +13,13 @@
 
     {IDF_TARGET_NAME} 支持蓝牙 5.0 (LE)，并且已经获得蓝牙 LE 5.4 认证。
 
-.. only:: esp32c2 or esp32c6 or esp32h2
+.. only:: esp32c2 or esp32c6 or esp32h2 or esp32c5 or esp32c61
 
     {IDF_TARGET_NAME} 支持蓝牙 5.0 (LE)，并且已经获得蓝牙 LE 5.3 认证。
 
 ESP-IDF 中的低功耗蓝牙协议栈是一个分层架构，可在 {IDF_TARGET_NAME} 系列芯片上实现低功耗蓝牙功能，详见下。
 
-.. only:: esp32 or esp32s3 or esp32c3 or esp32c6
+.. only:: esp32 or esp32s3 or esp32c3 or esp32c6 or esp32c5 or esp32c61
 
     .. figure:: ../../../_static/bluetooth-architecture.png
         :align: center
diff --git a/docs/zh_CN/api-guides/bootloader.rst b/docs/zh_CN/api-guides/bootloader.rst
index 29277188a71..a8537c1b9f4 100644
--- a/docs/zh_CN/api-guides/bootloader.rst
+++ b/docs/zh_CN/api-guides/bootloader.rst
@@ -3,16 +3,16 @@
 
 :link_to_translation:`en:[English]`
 
-ESP-IDF 软件引导加载程序 (Bootloader) 主要执行以下任务：
+ESP-IDF 二级引导加载程序 (second stage bootloader) 主要执行以下任务：
 
 1. 内部模块的最小化初始配置；
-2. 如果配置了 :doc:`/security/flash-encryption` 和/或 :doc:`Secure </security/secure-boot-v2>`，则对其进行初始化。
+2. 如果配置了 :doc:`/security/flash-encryption` 和/或 :doc:`Secure Boot </security/secure-boot-v2>`，则对其进行初始化。
 3. 根据分区表和 ota_data（如果存在）选择需要引导的应用程序 (app) 分区；
 4. 将此应用程序镜像加载到 RAM（IRAM 和 DRAM）中，最后把控制权转交给此应用程序。
 
-引导加载程序位于 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处。
+ESP-IDF 二级引导加载程序位于 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处。
 
-关于启动过程以及 ESP-IDF 引导加载程序的更多信息，请参考 :doc:`startup`。
+如需了解包括 ESP-IDF 二级引导加载程序在内的完整启动过程，请参考 :doc:`startup`。
 
 .. _bootloader-compatibility:
 
@@ -21,11 +21,11 @@ ESP-IDF 软件引导加载程序 (Bootloader) 主要执行以下任务：
 
 建议使用最新发布的 :doc:`ESP-IDF 版本 </versions>`。OTA（空中升级）更新可以在现场烧录新的应用程序，但不能烧录一个新的引导加载程序。因此，引导加载程序支持引导从 ESP-IDF 新版本中构建的应用程序。
 
-但不支持引导从 ESP-IDF 旧版本中构建的程序。如果现有产品可能需要将应用程序降级到旧版本，那么在手动更新 ESP-IDF 时，请继续使用旧版本 ESP-IDF 引导加载程序的二进制文件。
+但不支持引导从 ESP-IDF 旧版本中构建的程序。如果现有产品可能需要将应用程序降级到旧版本，那么在手动更新 ESP-IDF 时，请继续使用旧版本引导加载程序的二进制文件。
 
 .. note::
 
-    如果在生产中测试现有产品的 OTA 更新，请确保测试中使用的 ESP-IDF 引导加载程序二进制文件与生产中部署的相同。
+    如果在生产中测试现有产品的 OTA 更新，请确保测试中使用的引导加载程序二进制文件与生产中部署的相同。
 
 .. only:: esp32
 
@@ -50,11 +50,11 @@ ESP-IDF 软件引导加载程序 (Bootloader) 主要执行以下任务：
 
 每个 ESP-IDF 应用程序或引导加载程序的二进制文件中都包含一个文件头，其中内置了 :ref:`CONFIG_ESPTOOLPY_FLASHMODE`、:ref:`CONFIG_ESPTOOLPY_FLASHFREQ`、和 :ref:`CONFIG_ESPTOOLPY_FLASHSIZE`。这些是用于在启动时配置 SPI flash。
 
-ROM 中的 :ref:`first-stage-bootloader` 从 flash 中读取 :ref:`second-stage-bootloader` 文件头中的配置信息，并使用这些信息来加载剩余的 :ref:`second-stage-bootloader`。然而，此时系统的时钟速度低于其被配置的速度，并且在这个阶段，只支持部分 flash 模式。因此，当 :ref:`second-stage-bootloader` 运行时，它会从当前应用程序的二进制文件头中读取数据（而不是从引导加载程序的文件头中读取数据），并使用这些数据重新配置 flash。这样的配置流程可让 OTA 更新去更改当前使用的 SPI flash 的配置。
+:ref:`first-stage-bootloader` 从 flash 中读取 :ref:`second-stage-bootloader` 文件头中的配置信息，并使用这些信息来加载剩余的 :ref:`second-stage-bootloader`。然而，此时系统的时钟速度低于其被配置的速度，并且在这个阶段，只支持部分 flash 模式。因此，当 :ref:`second-stage-bootloader` 运行时，它会从当前应用程序的二进制文件头中读取数据（而不是从 :ref:`second-stage-bootloader` 的文件头中读取数据），并使用这些数据重新配置 flash。这样的配置流程可让 OTA 更新去更改当前使用的 SPI flash 的配置。
 
 .. only:: esp32
 
-    ESP-IDF V4.0 版本之前的引导加载程序使用其自身的文件头来配置 SPI flash，这意味着无法在 OTA 更新时更改 SPI flash 配置。为了与旧引导加载程序兼容，应用程序在其启动期间使用应用程序文件头中的配置信息重新初始化 flash 配置。
+    ESP-IDF V4.0 版本之前的引导加载程序使用其自身的文件头来配置 SPI flash，这意味着无法在 OTA 更新时更改 SPI flash 配置。为了与旧版本的引导加载程序兼容，应用程序在其启动期间使用应用程序文件头中的配置信息重新初始化 flash 配置。
 
 日志级别
 ---------
@@ -125,7 +125,7 @@ ROM 中的 :ref:`first-stage-bootloader` 从 flash 中读取 :ref:`second-stage-
 回滚
 --------
 
-回滚和反回滚功能也必须在引导程序中配置。
+回滚和反回滚功能也必须在引导加载程序中配置。
 
 请参考 :doc:`OTA API 参考文档 </api-reference/system/ota>` 中的 :ref:`app_rollback` 和 :ref:`anti-rollback` 章节。
 
@@ -157,7 +157,7 @@ ROM 中的 :ref:`first-stage-bootloader` 从 flash 中读取 :ref:`second-stage-
 
 可以使用如下方法解决此问题：
 
-- 将 :ref:`bootloader 编译器优化 <CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION>` 重新设置回默认值“Size”。
+- 将 :ref:`引导加载程序编译器优化 <CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION>` 重新设置回默认值“Size”。
 - 降低 :ref:`引导加载程序日志级别 <CONFIG_BOOTLOADER_LOG_LEVEL>`。将日志级别设置为 Warning, Error 或 None 都会显著减少最终二进制文件的大小（但也可能会让调试变得更加困难）。
 - 将 :ref:`CONFIG_PARTITION_TABLE_OFFSET` 设置为高于 0x8000 的值，以便稍后将分区表放置在 flash 中，这样可以增加引导加载程序的可用空间。如果 :doc:`分区表 </api-guides/partition-tables>` 的 CSV 文件包含明确的分区偏移量，则需要修改这些偏移量，从而保证没有分区的偏移量低于 ``CONFIG_PARTITION_TABLE_OFFSET + 0x1000``。（这包括随 ESP-IDF 提供的默认分区 CSV 文件）
 
@@ -186,4 +186,4 @@ ROM 中的 :ref:`first-stage-bootloader` 从 flash 中读取 :ref:`second-stage-
 
 在引导加载程序的代码中，用户不能使用其他组件提供的驱动和函数，如果确实需要，请将该功能的实现部分放在项目的 `bootloader_components` 目录中（注意，这会增加引导加载程序的大小）。
 
-如果引导加载程序过大，则可能与内存中的分区表重叠，分区表默认烧录在偏移量 0x8000 处。增加 :ref:`分区表偏移量 <CONFIG_PARTITION_TABLE_OFFSET>` ，将分区表放在 flash 中靠后的区域，这样可以增加引导程序的可用空间。
+如果引导加载程序过大，则可能与内存中的分区表重叠，分区表默认烧录在偏移量 0x8000 处。增加 :ref:`分区表偏移量 <CONFIG_PARTITION_TABLE_OFFSET>` ，将分区表放在 flash 中靠后的区域，这样可以增加引导加载程序的可用空间。
diff --git a/docs/zh_CN/api-guides/build-system.rst b/docs/zh_CN/api-guides/build-system.rst
index 66da3ed88a2..88adf5e5a88 100644
--- a/docs/zh_CN/api-guides/build-system.rst
+++ b/docs/zh_CN/api-guides/build-system.rst
@@ -25,11 +25,11 @@ ESP-IDF 可以显式地指定和配置每个组件。在构建项目的时候，
 概念
 ----
 
-- ``项目`` 特指一个目录，其中包含了构建可执行应用程序所需的全部文件和配置，以及其他支持型文件，例如分区表、数据/文件系统分区和引导程序。
+- ``项目`` 特指一个目录，其中包含了构建可执行应用程序所需的全部文件和配置，以及其他支持型文件，例如分区表、数据/文件系统分区和引导加载程序。
 
 - ``项目配置`` 保存在项目根目录下名为 ``sdkconfig`` 的文件中，可以通过 ``idf.py menuconfig`` 进行修改，且一个项目只能包含一个项目配置。
 
-- ``应用程序`` 是由 ESP-IDF 构建得到的可执行文件。一个项目通常会构建两个应用程序：项目应用程序（可执行的主文件，即用户自定义的固件）和引导程序（启动并初始化项目应用程序）。
+- ``应用程序`` 是由 ESP-IDF 构建得到的可执行文件。一个项目通常会构建两个应用程序：项目应用程序（可执行的主文件，即用户自定义的固件）和引导加载程序（启动并初始化项目应用程序）。
 
 - ``组件`` 是模块化且独立的代码，会被编译成静态库（.a 文件）并链接到应用程序。部分组件由 ESP-IDF 官方提供，其他组件则来源于其它开源项目。
 
@@ -97,7 +97,7 @@ idf.py
 
     make app-flash
 
-可用的目标还包括：``flash``、``app-flash`` （仅用于 app）、``bootloader-flash`` （仅用于 bootloader）。
+可用的目标还包括：``flash``、``app-flash`` （仅用于 app）、``bootloader-flash`` （仅用于引导加载程序）。
 
 以这种方式烧录时，可以通过设置 ``ESPPORT`` 和 ``ESPBAUD`` 环境变量来指定串口设备和波特率。可以在操作系统或 IDE 项目中设置该环境变量，或者直接在命令行中进行设置::
 
@@ -131,7 +131,7 @@ idf.py
 设置 Python 解释器
 ------------------
 
-ESP-IDF 适用于 Python 3.8 以上版本。
+ESP-IDF 适用于 Python 3.9 以上版本。
 
 ``idf.py`` 和其他的 Python 脚本会使用默认的 Python 解释器运行，如 ``python``。你可以通过 ``python3 $IDF_PATH/tools/idf.py ...`` 命令切换到别的 Python 解释器，或者通过设置 shell 别名或其他脚本来简化该命令。
 
@@ -181,7 +181,7 @@ ESP-IDF 适用于 Python 3.8 以上版本。
 
 - 顶层项目 CMakeLists.txt 文件，这是 CMake 用于学习如何构建项目的主要文件，可以在这个文件中设置项目全局的 CMake 变量。顶层项目 CMakeLists.txt 文件会导入 :idf_file:`/tools/cmake/project.cmake` 文件，由它负责实现构建系统的其余部分。该文件最后会设置项目的名称，并定义该项目。
 
-- "sdkconfig" 项目配置文件，执行 ``idf.py menuconfig`` 时会创建或更新此文件，文件中保存了项目中所有组件（包括 ESP-IDF 本身）的配置信息。 ``sdkconfig`` 文件可能会也可能不会被添加到项目的源码管理系统中。
+- "sdkconfig" 项目配置文件，执行 ``idf.py menuconfig`` 时会创建或更新此文件，文件中保存了项目中所有组件（包括 ESP-IDF 本身）的配置信息。 ``sdkconfig`` 文件可能会也可能不会被添加到项目的源码管理系统中。更多有关本配置文件的信息，请参阅配置指南中的 :ref:`sdkconfig file <sdkconfig-file>` 章节。
 
 - "dependencies.lock" 文件包含项目中当前使用的所有托管的组件及其版本。使用 IDF 组件管理器添加或更新项目组件时，会自动生成或更新 ``dependencies.lock`` 文件。因此，请勿手动编辑此文件！如果项目中没有组件包含 ``idf_component.yml`` 文件，则不会创建 ``dependencies.lock`` 文件。
 
@@ -245,7 +245,9 @@ ESP-IDF 适用于 Python 3.8 以上版本。
 
 - ``COMPONENTS``：要构建进项目中的组件名称列表，默认为 ``COMPONENT_DIRS`` 目录下检索到的所有组件。使用此变量可以“精简”项目以缩短构建时间。请注意，如果一个组件通过 ``COMPONENT_REQUIRES`` 指定了它依赖的另一个组件，则会自动将其添加到 ``COMPONENTS`` 中，所以 ``COMPONENTS`` 列表可能会非常短。
 
-- ``BOOTLOADER_IGNORE_EXTRA_COMPONENT``：引导加载程序编译时应忽略的组件列表，位于 ``bootloader_components/`` 目录中。使用这一变量可以将一个组件有条件地包含在项目中。
+- ``BOOTLOADER_IGNORE_EXTRA_COMPONENT``：可选组件列表，位于 ``bootloader_components/`` 目录中，引导加载程序编译时会忽略该列表中的组件。使用这一变量可以将一个组件有条件地包含在项目中。
+
+- ``BOOTLOADER_EXTRA_COMPONENT_DIRS``：可选的附加路径列表，引导加载程序编译时将从这些路径中搜索要编译的组件。注意，这是一个构建属性。
 
 以上变量中的路径可以是绝对路径，或者是相对于项目目录的相对路径。
 
@@ -362,7 +364,7 @@ ESP-IDF 在搜索所有待构建的组件时，会按照以下优先级搜索组
 
 以下变量在项目级别中被设置，但可在组件 CMakeLists 中使用：
 
-- ``CONFIG_*``：项目配置中的每个值在 cmake 中都对应一个以 ``CONFIG_`` 开头的变量。更多详细信息请参阅 :doc:`Kconfig </api-reference/kconfig>`。
+- ``CONFIG_*``：项目配置中的每个值在 cmake 中都对应一个以 ``CONFIG_`` 开头的变量。更多有关项目配置的信息，请参阅 :ref:`项目配置指南 <project-configuration-guide>`。
 - ``ESP_PLATFORM``：ESP-IDF 构建系统处理 CMake 文件时，其值设为 1。
 
 
@@ -428,7 +430,7 @@ ESP-IDF 在搜索所有待构建的组件时，会按照以下优先级搜索组
 
 创建一个组件的 Kconfig 文件，最简单的方法就是使用 ESP-IDF 中现有的 Kconfig 文件作为模板，在这基础上进行修改。
 
-有关示例请参阅 :ref:`add_conditional_config`。
+有关示例请参阅 :ref:`add_conditional_config`。详细信息请参阅 :ref:`组件配置指南 <component-configuration-guide>`。
 
 
 预处理器定义
@@ -461,7 +463,7 @@ ESP-IDF 构建系统会在命令行中添加以下 C 预处理器定义：
 
 - ``PRIV_REQUIRES`` 需要包含被当前组件的源文件 `#include` 的头文件所在的组件（除非已经被设置在了 ``REQUIRES`` 中）。以及是当前组件正常工作必须要链接的组件。
 
-- ``REQUIRES`` 和 ``PRIV_REQUIRES`` 的值不能依赖于任何配置选项（``CONFIG_xxx`` 宏）。这是因为在配置加载之前，依赖关系就已经被展开。其它组件变量（比如包含路径或源文件）可以依赖配置选择。
+- ``REQUIRES`` 和 ``PRIV_REQUIRES`` 的值不能依赖于任何配置选项（``CONFIG_xxx`` 宏）。这是因为在配置加载之前，依赖关系就已经被展开。其它组件变量（比如包含路径或源文件）可以依赖配置选项。
 
 - 如果当前组件除了 `通用组件依赖项`_ 中设置的通用组件（比如 RTOS、libc 等）外，并不依赖其它组件，那么对于上述两个 ``REQUIRES`` 变量，可以选择其中一个或是两个都不设置。
 
@@ -724,13 +726,14 @@ project_include.cmake
 在 ``project_include.cmake`` 文件中设置变量或目标时要格外小心，这些值被包含在项目的顶层 CMake 文件中，因此他们会影响或破坏所有组件的功能。
 
 
-KConfig.projbuild
+Kconfig.projbuild
 -----------------
 
-与 ``project_include.cmake`` 类似，也可以为组件定义一个 KConfig 文件以实现全局的 :ref:`component-configuration`。如果要在 menuconfig 的顶层添加配置选项，而不是在 “Component Configuration” 子菜单中，则可以在 ``CMakeLists.txt`` 文件所在目录的 KConfig.projbuild 文件中定义这些选项。
+与 ``project_include.cmake`` 类似，也可以为组件定义一个 Kconfig 文件以实现全局的 :ref:`component-configuration`。如果要在 menuconfig 的顶层添加配置选项，而不是在 “Component Configuration” 子菜单中，则可以在 ``CMakeLists.txt`` 文件所在目录的 Kconfig.projbuild 文件中定义这些选项。
 
-在此文件中添加配置时要小心，因为这些配置会包含在整个项目配置中。在可能的情况下，请为 :ref:`component-configuration` 创建 KConfig 文件。
+在此文件中添加配置时要小心，因为这些配置会包含在整个项目配置中。在可能的情况下，请为 :ref:`component-configuration` 创建 Kconfig 文件。
 
+详情请参阅配置指南中的 :ref:`Kconfig 文件 <kconfig-files>` 章节。
 
 通过封装对现有函数进行重新定义或扩展
 -------------------------------------
@@ -781,13 +784,22 @@ KConfig.projbuild
 
 请参考 :example:`custom_bootloader/bootloader_override` 查看覆盖默认引导加载程序的示例。
 
+与常规应用程序类似，通过构建属性 ``BOOTLOADER_EXTRA_COMPONENT_DIRS`` 可以将不在 `bootloader_component` 中的外部组件作为引导加载程序的一部分进行构建。可以只引用一个组件，也可以引用包含多个组件的路径。例如：
+
+    include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+    idf_build_set_property(BOOTLOADER_EXTRA_COMPONENT_DIRS "/path/to/extra/component/" APPEND)
+
+    project(main)
+
+请参考示例 :example:`custom_bootloader/bootloader_extra_dir`，查看如何向引导加载程序构建过程添加额外的组件。
 
 .. _config_only_component:
 
 仅配置组件
 ===========
 
-仅配置组件是一类不包含源文件的特殊组件，仅包含 ``Kconfig.projbuild``、``KConfig`` 和 ``CMakeLists.txt`` 文件，该 ``CMakeLists.txt`` 文件仅有一行代码，调用了 ``idf_component_register()`` 函数。此函数会将组件导入到项目构建中，但不会构建任何库，也不会将头文件添加到任何 include 搜索路径中。
+仅配置组件是一类不包含源文件的特殊组件，仅包含 ``Kconfig.projbuild``、``Kconfig`` 和 ``CMakeLists.txt`` 文件，该 ``CMakeLists.txt`` 文件仅有一行代码，调用了 ``idf_component_register()`` 函数。此函数会将组件导入到项目构建中，但不会构建任何库，也不会将头文件添加到任何 include 搜索路径中。
 
 
 CMake 调试
@@ -1065,6 +1077,10 @@ ExternalProject 的依赖与构建清理
 自定义 sdkconfig 的默认值
 =========================
 
+.. note::
+
+  有关 ``sdkconfig.defaults`` 文件的详细信息，请参阅项目配置章节的 :ref:`sdkconfig.defaults 文件 <sdkconfig-defaults-file>`。
+
 对于示例工程或者其他你不想指定完整 sdkconfig 配置的项目，但是你确实希望覆盖 ESP-IDF 默认值中的某些键值，则可以在项目中创建 ``sdkconfig.defaults`` 文件。重新创建新配置时将会用到此文件，另外在 ``sdkconfig`` 没有设置新配置值时，上述文件也会被用到。
 
 如若需要覆盖此文件的名称或指定多个文件，请设置 ``SDKCONFIG_DEFAULTS`` 环境变量或在顶层 CMakeLists.txt 文件中设置 ``SDKCONFIG_DEFAULTS``。非绝对路径的文件名将以当前项目的相对路径来解析。
@@ -1083,6 +1099,7 @@ ExternalProject 的依赖与构建清理
 
 例如，如果 ``SDKCONFIG_DEFAULTS="sdkconfig.defaults;sdkconfig_devkit1"``，并且在同一文件夹中有一个 ``sdkconfig.defaults.esp32`` 文件，那么这些文件将按以下顺序应用：（1) sdkconfig.defaults (2) sdkconfig.defaults.esp32 (3) sdkconfig_devkit1。
 
+关于项目配置的详细信息，请参阅 :ref:`项目配置指南 <project-configuration-guide>`。关于配置文件的详细信息，请参阅 :ref:`配置文件的结构和关系 <configuration-structure>`。
 
 .. _flash_parameters:
 
@@ -1093,9 +1110,9 @@ flash 参数
 
 运行项目构建之后，构建目录将包含项目二进制输出文件（``.bin`` 文件），同时也包含以下烧录数据文件：
 
-- ``flash_project_args`` 包含烧录整个项目的参数，包括应用程序 (app)、引导程序 (bootloader)、分区表，如果设置了 PHY 数据，也会包含此数据。
+- ``flash_project_args`` 包含烧录整个项目的参数，包括应用程序 (app)、引导加载程序 (bootloader)、分区表，如果设置了 PHY 数据，也会包含此数据。
 - ``flash_app_args`` 只包含烧录应用程序的参数。
-- ``flash_bootloader_args`` 只包含烧录引导程序的参数。
+- ``flash_bootloader_args`` 只包含烧录引导加载程序的参数。
 
 .. highlight:: bash
 
@@ -1108,12 +1125,12 @@ flash 参数
 构建目录中还包含生成的 ``flasher_args.json`` 文件，此文件包含 JSON 格式的项目烧录信息，可用于 ``idf.py`` 和其它需要项目构建信息的工具。
 
 
-构建 Bootloader
-===============
+构建引导加载程序
+================
 
-引导程序是 :idf:`/components/bootloader/subproject` 内部独特的“子项目”，它有自己的项目 CMakeLists.txt 文件，能够构建独立于主项目的 ``.ELF`` 和 ``.BIN`` 文件，同时它又与主项目共享配置和构建目录。
+引导加载程序是 :idf:`/components/bootloader/subproject` 内部独特的“子项目”，它有自己的项目 CMakeLists.txt 文件，能够构建独立于主项目的 ``.ELF`` 和 ``.BIN`` 文件，同时它又与主项目共享配置和构建目录。
 
-子项目通过 :idf_file:`/components/bootloader/project_include.cmake` 文件作为外部项目插入到项目的顶层，主构建进程会运行子项目的 CMake，包括查找组件（主项目使用的组件的子集），生成引导程序专用的配置文件（从主 ``sdkconfig`` 文件中派生）。
+子项目通过 :idf_file:`/components/bootloader/project_include.cmake` 文件作为外部项目插入到项目的顶层，主构建进程会运行子项目的 CMake，包括查找组件（主项目使用的组件的子集），生成引导加载程序专用的配置文件（从主 ``sdkconfig`` 文件中派生）。
 
 
 .. _write-pure-component:
@@ -1668,9 +1685,9 @@ CMake 中不可用的功能
 应用示例
 --------------------
 
-- :example:`build_system/wrappers` 演示了如何使用链接器功能在 ESP-IDF 和引导程序中重新定义或覆盖任何公共函数，以修改或扩展函数的默认行为。
+- :example:`build_system/wrappers` 演示了如何使用链接器功能在 ESP-IDF 和引导加载程序中重新定义或覆盖任何公共函数，以修改或扩展函数的默认行为。
 
-- :example:`custom_bootloader/bootloader_override` 演示了如何从常规项目中覆盖二级引导程序，提供一个自定义引导程序，在启动时打印额外的消息，并能够基于某些条件（如目标依赖性或 KConfig 选项）有条件地覆盖引导程序。
+- :example:`custom_bootloader/bootloader_override` 演示了如何从常规项目中覆盖二级引导加载程序，提供一个自定义引导加载程序，在启动时打印额外的消息，并能够基于某些条件（如目标依赖性或 Kconfig 选项）有条件地覆盖引导加载程序。
 
 - :example:`build_system/cmake/import_lib` 演示了如何使用 ExternalProject CMake 模块导入和使用第三方库。
 
diff --git a/docs/zh_CN/api-guides/cplusplus.rst b/docs/zh_CN/api-guides/cplusplus.rst
index 5968ef27228..ba0c833e907 100644
--- a/docs/zh_CN/api-guides/cplusplus.rst
+++ b/docs/zh_CN/api-guides/cplusplus.rst
@@ -193,12 +193,3 @@ ESP-IDF 支持 ``iostream`` 功能，但应注意：
 -------------
 
 请勿在 C++ 中使用 ``setjmp``/``longjmp``。``longjmp`` 会在不调用任何析构函数的情况下盲目跳出堆栈，容易引起未定义的行为和内存泄漏。请改用 C++ 异常处理，这类程序可以确保正确调用析构函数。如果无法使用 C++ 异常处理，请使用其他替代方案（ ``setjmp``/``longjmp`` 除外），如简单的返回码。
-
-应用示例
---------------------
-
-- :example:`cxx/pthread`
-
-- :example:`cxx/exceptions` 演示了如何在 {IDF_TARGET_NAME} 中启用和使用 C++ 异常。该示例声明了一个类，当提供的参数等于 0 时，这个类会在构造函数中抛出异常。
-
-- :example:`cxx/rtti`
diff --git a/docs/zh_CN/api-guides/external-ram.rst b/docs/zh_CN/api-guides/external-ram.rst
index 92bfa9eafcd..51a8af1b9d3 100644
--- a/docs/zh_CN/api-guides/external-ram.rst
+++ b/docs/zh_CN/api-guides/external-ram.rst
@@ -167,7 +167,7 @@ ESP-IDF 启动过程中，片外 RAM 被映射到数据虚拟地址空间，该
 
         在 PSRAM 中直接执行代码的好处包括：
 
-        - PSRAM 访问速度可能快于 flash，因此性能更好。例如，如果使用的 PSRAM 是八线的，且被配置为 80 MHz，而 flash 是4线的，且被配置为 80 Mhz，那么 PSRAM 的访问速度是快于 flash 的。
+        - PSRAM 的访问速度可能快于 flash，因此性能更好。例如，如果使用的 PSRAM 是八线的，且被配置为 80 MHz，而 flash 是四线的，且被配置为 80 Mhz，那么 PSRAM 的访问速度将快于 flash。
 
         - 在进行 SPI1 flash 操作期间，cache 仍然保持启用状态，这样可以优化代码执行性能。由于无需把中断服务程序 (ISR)、ISR 回调和在此期间可能被访问的数据放置在片上 RAM 中，片上 RAM 可用于其他用途，从而提高了使用效率。这个特性适用于需要处理大量数据的高吞吐量外设应用，能显著提高 SPI1 flash 操作期间的性能。
 
@@ -188,7 +188,9 @@ ESP-IDF 启动过程中，片外 RAM 被映射到数据虚拟地址空间，该
 
             由于 {IDF_TARGET_NAME} flash 和 PSRAM 使用两个独立的 SPI 总线，将 flash 内容移动到 PSRAM 实际上增加了 PSRAM MSPI 总线的负载，
 
-            例如，PSRAM 的访问速度可能快于 flash (比如在 ESP32-P4 上，选择的 PSRAM 是十六线的并将其配置为 200 MHz， 此时 PSRAM 的访问速度是远快于一颗被配置为 80 MHz 的四线 flash 芯片)，如果这些之前在 flash 中被就地执行的指令和数据不是十分频繁地被访问，则使能这个选项会增加系统的性能。建议先进行性能分析以确定启用此选项是否会显著影响应用程序性能。
+            PSRAM 的访问速度可能快于 flash。比如在 ESP32-P4 上，选择十六线 PSRAM 并将其配置为 200 MHz，此时 PSRAM 的访问速度远快于被配置为 80 MHz 的四线 flash 芯片。
+
+            如果这些之前在 flash 中被就地执行的指令和数据不会被频繁访问，则使能该选项可能会提高系统的性能。建议先进行性能分析，评估启用此选项是否会显著影响应用程序的性能。
 
 片外 RAM 使用限制
 ===================
@@ -211,7 +213,7 @@ ESP-IDF 启动过程中，片外 RAM 被映射到数据虚拟地址空间，该
 
     - 一般来说，片外 RAM 不会用作任务堆栈存储器。:cpp:func:`xTaskCreate` 及类似函数始终会为堆栈和任务 TCB 分配片上储存器。
 
-可以使用 :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` 选项将任务堆栈放入片外存储器。这时，必须使用 :cpp:func:`xTaskCreateStatic` 指定从片外存储器分配的任务堆栈缓冲区，否则任务堆栈将仍从片上存储器分配。
+可以使用 :ref:`CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM` 选项将任务堆栈放入片外存储器。这时，必须使用 :cpp:func:`xTaskCreateStatic` 指定从片外存储器分配的任务堆栈缓冲区，否则任务堆栈将仍从片上存储器分配。
 
 
 初始化失败
diff --git a/docs/zh_CN/api-guides/fatal-errors.rst b/docs/zh_CN/api-guides/fatal-errors.rst
index 6426732ae49..7cab6e65dfb 100644
--- a/docs/zh_CN/api-guides/fatal-errors.rst
+++ b/docs/zh_CN/api-guides/fatal-errors.rst
@@ -13,17 +13,17 @@
 - CPU 异常：|CPU_EXCEPTIONS_LIST|
 - 系统级检查错误：
 
-  .. list::
-
-      - :doc:`中断看门狗 <../api-reference/system/wdts>` 超时
-      - :doc:`任务看门狗 <../api-reference/system/wdts>` 超时（只有开启 :ref:`CONFIG_ESP_TASK_WDT_PANIC` 后才会触发严重错误）
-      - 高速缓存访问错误
-      :SOC_MEMPROT_SUPPORTED: - 内存保护故障
-      - 掉电检测事件
-      - 堆栈溢出
-      - 堆栈粉碎保护检查
-      - 堆完整性检查
-      - 未定义行为清理器 (UBSAN) 检查
+    .. list::
+
+        - :doc:`中断看门狗 <../api-reference/system/wdts>` 超时
+        - :doc:`任务看门狗 <../api-reference/system/wdts>` 超时（只有开启 :ref:`CONFIG_ESP_TASK_WDT_PANIC` 后才会触发严重错误）
+        - 高速缓存访问错误
+        :SOC_MEMPROT_SUPPORTED: - 内存保护故障
+        - 掉电检测事件
+        - 堆栈溢出
+        - 堆栈粉碎保护检查
+        - 堆完整性检查
+        - 未定义行为清理器 (UBSAN) 检查
 
 - 使用 ``assert``、``configASSERT`` 等类似的宏断言失败。
 
@@ -50,25 +50,25 @@
 
 紧急处理程序接下来的行为将取决于 :ref:`CONFIG_ESP_SYSTEM_PANIC` 的设置，支持的选项包括：
 
-- 打印 CPU 寄存器，然后重启（``CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT``）- 默认选项
+- 打印 CPU 寄存器，然后重启 (``CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT``) - 默认选项
 
-  打印系统发生异常时 CPU 寄存器的值，打印回溯，最后重启芯片。
+    打印系统发生异常时 CPU 寄存器的值，打印回溯，最后重启芯片。
 
-- 打印 CPU 寄存器，然后暂停（``CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT``）
+- 打印 CPU 寄存器，然后暂停 (``CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT``)
 
-  与上一个选项类似，但不会重启，而是选择暂停程序的运行。重启程序需要外部执行复位操作。
+    与上一个选项类似，但不会重启，而是选择暂停程序的运行。重启程序需要外部执行复位操作。
 
-- 静默重启（``CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT``）
+- 静默重启 (``CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT``)
 
-  不打印 CPU 寄存器的值，也不打印回溯，立即重启芯片。
+    不打印 CPU 寄存器的值，也不打印回溯，立即重启芯片。
 
-- 调用 GDB Stub（``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB``）
+- 调用 GDB Stub (``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB``)
 
-  启动 GDB 服务器，通过控制台 UART 接口与 GDB 进行通信。该选项只提供只读调试或者事后调试，详细信息请参阅 `GDB Stub`_。
+    启动 GDB 服务器，通过控制台 UART 接口与 GDB 进行通信。该选项只提供只读调试或者事后调试，详细信息请参阅 `GDB Stub`_。
 
 .. note::
 
-  仅当构建中包含组件 ``esp_gdbstub`` 时，配置选项 :ref:`CONFIG_ESP_SYSTEM_PANIC` 中的 ``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB`` 选项可用。
+    仅当构建中包含组件 ``esp_gdbstub`` 时，配置选项 :ref:`CONFIG_ESP_SYSTEM_PANIC` 中的 ``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB`` 选项可用。
 
 紧急处理程序的行为还受到另外两个配置项的影响：
 
@@ -78,7 +78,7 @@
 
 - 如果 :ref:`CONFIG_ESP_PANIC_HANDLER_IRAM` 被禁用（默认情况下禁用），紧急处理程序的代码会放置在 flash 而不是 IRAM 中。这意味着，如果 ESP-IDF 在 flash 高速缓存禁用时崩溃，在运行 GDB Stub 和内核转储之前紧急处理程序会自动重新使能 flash 高速缓存。如果 flash 高速缓存也崩溃了，这样做会增加一些小风险。
 
-  如果使能了该选项，紧急处理程序的代码（包括所需的 UART 函数）会放置在 IRAM 中，导致 SRAM 中的可用内存空间变小。当禁用 flash 高速缓存（如写入 SPI flash）时或触发异常导致 flash 高速缓存崩溃时，可用此选项调试一些复杂的崩溃问题。
+    如果使能了该选项，紧急处理程序的代码（包括所需的 UART 函数）会放置在 IRAM 中，导致 SRAM 中的可用内存空间变小。当禁用 flash 高速缓存（如写入 SPI flash）时或触发异常导致 flash 高速缓存崩溃时，可用此选项调试一些复杂的崩溃问题。
 
 - 如果启用 :ref:`CONFIG_ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS` （默认为禁用）并将其配置为大于 0 的数字，紧急处理程序将基于该数字延迟重启的时间，单位为秒。如果用于监测串行输出的工具不支持停止和检查串行输出，可启用该选项。在这种情况下，借助延迟重启，用户可以在延迟期间检查和调试紧急处理程序的输出（例如回溯）。延迟结束后，设备将重新启动，并记录重置原因。
 
@@ -134,7 +134,7 @@
 
 .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA
 
-    ::
+    .. code-block:: none
 
         Core 0 register dump:
         PC      : 0x400e14ed  PS      : 0x00060030  A0      : 0x800d0805  A1      : 0x3ffb5030
@@ -148,7 +148,7 @@
 
 .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
-    ::
+    .. code-block:: none
 
         Core  0 register dump:
         MEPC    : 0x420048b4  RA      : 0x420048b4  SP      : 0x3fc8f2f0  GP      : 0x3fc8a600
@@ -176,7 +176,7 @@
 
 .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA
 
-    ::
+    .. code-block:: none
 
         Core 0 register dump:
         PC      : 0x400e14ed  PS      : 0x00060030  A0      : 0x800d0805  A1      : 0x3ffb5030
@@ -197,7 +197,7 @@
 
 .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
-    ::
+    .. code-block:: none
 
         Core  0 register dump:
         MEPC    : 0x420048b4  RA      : 0x420048b4  SP      : 0x3fc8f2f0  GP      : 0x3fc8a600
@@ -220,7 +220,7 @@
     此外，由于紧急处理程序中提供了堆栈转储，因此 :doc:`IDF 监视器 <tools/idf-monitor>` 也可以生成并打印回溯。
     输出结果如下：
 
-    ::
+    .. code-block:: none
 
         Backtrace:
 
@@ -238,7 +238,7 @@
 
     该选项会让编译器为项目的每个函数生成 DWARF 信息。然后，当 CPU 异常发生时，紧急处理程序将解析这些数据并生成出错任务的堆栈回溯信息。输出结果如下：
 
-    ::
+    .. code-block:: none
 
         Backtrace: 0x42009e9a:0x3fc92120 0x42009ea6:0x3fc92120 0x42009ec2:0x3fc92130 0x42024620:0x3fc92150 0x40387d7c:0x3fc92160 0xfffffffe:0x3fc92170
 
@@ -256,7 +256,9 @@ GDB Stub
 
 如果启用了 ``CONFIG_ESP_SYSTEM_PANIC_GDBSTUB`` 选项，在发生严重错误时，紧急处理程序不会复位芯片，相反，它将启动 GDB 远程协议服务器，通常称为 GDB Stub。发生这种情况时，可以让主机上运行的 GDB 实例通过 UART 端口连接到 ESP32。
 
-如果使用了 :doc:`IDF 监视器 <tools/idf-monitor>`，该工具会在 UART 端口检测到 GDB Stub 提示符后自动启动 GDB，输出会类似于::
+如果使用了 :doc:`IDF 监视器 <tools/idf-monitor>`，该工具会在 UART 端口检测到 GDB Stub 提示符后自动启动 GDB，输出会类似于：
+
+.. code-block:: none
 
     Entering gdb stub now.
     $T0b#e6GNU gdb (crosstool-NG crosstool-ng-1.22.0-80-gff1f415) 7.10
@@ -286,16 +288,17 @@ GDB Stub
 
 RTC 看门狗超时
 ----------------
-{IDF_TARGET_RTCWDT_RTC_RESET:default="Not updated", esp32="RTCWDT_RTC_RESET", esp32s2="RTCWDT_RTC_RST", esp32s3="RTCWDT_RTC_RST", esp32c3="RTCWDT_RTC_RST", esp32c2="RTCWDT_RTC_RST", esp32c6="LP_WDT_SYS", esp32h2="LP_WDT_SYS", esp32p4="LP_WDT_SYS"}
 
-RTC 看门狗在启动代码中用于跟踪执行时间，也有助于防止由于电源不稳定引起的锁定。RTC 看门狗默认启用，参见 :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`。如果执行时间超时，RTC 看门狗将自动重启系统。此时，ROM 引导加载程序将打印消息 ``RTC Watchdog Timeout`` 说明重启原因。
+{IDF_TARGET_RTCWDT_RTC_RESET:default="未更新", esp32="RTCWDT_RTC_RESET", esp32s2="RTCWDT_RTC_RST", esp32s3="RTCWDT_RTC_RST", esp32c3="RTCWDT_RTC_RST", esp32c2="RTCWDT_RTC_RST", esp32c6="LP_WDT_SYS", esp32h2="LP_WDT_SYS", esp32p4="LP_WDT_SYS"}
+
+RTC 看门狗在启动代码中用于跟踪执行时间，也有助于防止由于电源不稳定引起的锁定。RTC 看门狗默认启用，参见 :ref:`CONFIG_BOOTLOADER_WDT_ENABLE`。如果执行时间超时，RTC 看门狗将自动重启系统。此时，一级 (ROM) 引导加载程序将打印消息 ``RTC Watchdog Timeout`` 说明重启原因。
 
-::
+.. code-block:: none
 
     rst:0x10 ({IDF_TARGET_RTCWDT_RTC_RESET})
 
 
-RTC 看门狗涵盖了从一级引导程序（ROM 引导程序）到应用程序启动的执行时间，最初在 ROM 引导程序中设置，而后在引导程序中使用 :ref:`CONFIG_BOOTLOADER_WDT_TIME_MS` 选项进行配置（默认 9000 ms）。在应用初始化阶段，由于慢速时钟源可能已更改，RTC 看门狗将被重新配置，最后在调用 ``app_main()`` 之前被禁用。可以使用选项 :ref:`CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE` 以保证 RTC 看门狗在调用 ``app_main`` 之前不被禁用，而是保持运行状态，用户需要在应用代码中定期“喂狗”。
+RTC 看门狗涵盖了从一级 (ROM) 引导加载程序到应用程序启动的执行时间，最初在一级 (ROM) 引导加载程序中设置，而后在引导加载程序中使用 :ref:`CONFIG_BOOTLOADER_WDT_TIME_MS` 选项进行配置（默认 9000 ms）。在应用初始化阶段，由于慢速时钟源可能已更改，RTC 看门狗将被重新配置，最后在调用 ``app_main()`` 之前被禁用。可以使用选项 :ref:`CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE` 以保证 RTC 看门狗在调用 ``app_main`` 之前不被禁用，而是保持运行状态，用户需要在应用代码中定期“喂狗”。
 
 .. _Guru-Meditation-Errors:
 
@@ -310,7 +313,7 @@ Guru Meditation 错误
 
 .. note::
 
-  想要了解 "Guru Meditation" 的历史渊源，请参阅 `维基百科 <https://en.wikipedia.org/wiki/Guru_Meditation>`_ 。
+    想要了解 "Guru Meditation" 的历史渊源，请参阅 `维基百科 <https://en.wikipedia.org/wiki/Guru_Meditation>`_ 。
 
 
 |ILLEGAL_INSTR_MSG|
@@ -322,9 +325,9 @@ Guru Meditation 错误
 
 - 无法从 SPI flash 中读取下一条指令，这通常发生在：
 
-  - 应用程序将 SPI flash 的管脚重新配置为其它功能（如 GPIO、UART 等）。有关 SPI flash 管脚的详细信息，请参阅硬件设计指南和芯片/模组的数据手册。
+    - 应用程序将 SPI flash 的管脚重新配置为其它功能（如 GPIO、UART 等）。有关 SPI flash 管脚的详细信息，请参阅硬件设计指南和芯片/模组的数据手册。
 
-  - 某些外部设备意外连接到 SPI flash 的管脚上，干扰了 {IDF_TARGET_NAME} 和 SPI flash 之间的通信。
+    - 某些外部设备意外连接到 SPI flash 的管脚上，干扰了 {IDF_TARGET_NAME} 和 SPI flash 之间的通信。
 
 - 在 C++ 代码中，退出 non-void 函数而无返回值被认为是未定义的行为。启用优化后，编译器通常会忽略此类函数的结尾，导致 |ILLEGAL_INSTR_MSG| 异常。默认情况下，ESP-IDF 构建系统启用 ``-Werror=return-type``，这意味着缺少返回语句会被视为编译时错误。但是，如果应用程序项目禁用了编译器警告，可能就无法检测到该问题，在运行时就会出现 |ILLEGAL_INSTR_MSG| 异常。
 
@@ -402,8 +405,8 @@ Interrupt wdt timeout on CPU0 / CPU1
 
 .. only:: SOC_MEMPROT_SUPPORTED
 
-    内存保护错误
-    ^^^^^^^^^^^^
+    Memory Protection Fault
+    ^^^^^^^^^^^^^^^^^^^^^^^
 
     ESP-IDF 中使用 {IDF_TARGET_NAME} 的权限控制功能来防止以下类型的内存访问：
 
@@ -424,7 +427,9 @@ Interrupt wdt timeout on CPU0 / CPU1
 
     {IDF_TARGET_NAME} 内部集成掉电检测电路，并且会默认启用。如果电源电压低于安全值，掉电检测器可以触发系统复位。掉电检测器可以使用 :ref:`CONFIG_ESP_BROWNOUT_DET` 和 :ref:`CONFIG_ESP_BROWNOUT_DET_LVL_SEL` 这两个选项进行设置。
 
-    当掉电检测器被触发时，会打印如下信息::
+    当掉电检测器被触发时，会打印如下信息：
+
+    .. code-block:: none
 
         Brownout detector was triggered
 
@@ -434,9 +439,11 @@ Interrupt wdt timeout on CPU0 / CPU1
 
 
 堆不完整
-^^^^^^^^^^^
+^^^^^^^^
 
-ESP-IDF 堆的实现包含许多运行时的堆结构检查，可以在 menuconfig 中开启额外的检查（“Heap Poisoning”）。如果其中的某项检查失败，则会打印类似如下信息::
+ESP-IDF 堆的实现包含许多运行时的堆结构检查，可以在 menuconfig 中开启额外的检查（“Heap Poisoning”）。如果其中的某项检查失败，则会打印类似如下信息：
+
+.. code-block:: none
 
     CORRUPT HEAP: Bad tail at 0x3ffe270a. Expected 0xbaad5678 got 0xbaac5678
     assertion "head != NULL" failed: file "/Users/user/esp/esp-idf/components/heap/multi_heap_poisoning.c", line 201, function: multi_heap_free
@@ -452,7 +459,7 @@ ESP-IDF 堆的实现包含许多运行时的堆结构检查，可以在 menuconf
     .. _Hardware-Stack-Guard:
 
     硬件堆栈保护
-    """"""""""""""""""""
+    """"""""""""
 
     {IDF_TARGET_NAME} 集成了辅助调试模块，支持监测堆栈指针 (SP) 寄存器，确保其值位于已分配给堆栈的内存范围内。发生中断处理或 FreeRTOS 切换上下文时，辅助调试模块都会设置新的堆栈监测范围。注意，该操作会对性能产生一定影响。
 
@@ -473,26 +480,27 @@ ESP-IDF 堆的实现包含许多运行时的堆结构检查，可以在 menuconf
 .. _FreeRTOS-End-Of-Stack-Watchpoint:
 
 FreeRTOS 任务堆栈末尾监视点
-""""""""""""""""""""""""""""""""
+"""""""""""""""""""""""""""
 
 ESP-IDF 支持基于监视点的 FreeRTOS 堆栈溢出检测机制。每次 FreeRTOS 切换任务上下文时，都会设置一个监视点，用于监视堆栈的最后 32 字节。
 
 通常，该设置会提前触发监视点，触发点可能会比预期提前多达 28 字节。基于 FreeRTOS 中堆栈金丝雀的大小为 20 字节，故将观察范围设置为 32 字节，确保可以在堆栈金丝雀遭到破坏前及时触发监测点。
 
 .. note::
+
     并非每次堆栈溢出都能触发监视点。如果任务绕过堆栈金丝雀的位置访问堆栈，则无法触发监视点。
 
 监视点触发后，将打印类似如下信息：
 
 .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA
 
-    ::
+    .. code-block:: none
 
         Debug exception reason: Stack canary watchpoint triggered (task_name)
 
 .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
-    ::
+    .. code-block:: none
 
         Guru Meditation Error: Core  0 panic'ed (Breakpoint). Exception was unhandled.
 
@@ -500,14 +508,16 @@ ESP-IDF 支持基于监视点的 FreeRTOS 堆栈溢出检测机制。每次 Free
 
 
 FreeRTOS 堆栈检查
-"""""""""""""""""""""
+"""""""""""""""""
 
 请参见 :ref:`CONFIG_FREERTOS_CHECK_STACKOVERFLOW`。
 
 堆栈粉碎
-^^^^^^^^^^
+^^^^^^^^
 
-堆栈粉碎保护（基于 GCC ``-fstack-protector*`` 标志）可以通过 ESP-IDF 中的 :ref:`CONFIG_COMPILER_STACK_CHECK_MODE` 选项来开启。如果检测到堆栈粉碎，则会打印类似如下的信息::
+堆栈粉碎保护（基于 GCC ``-fstack-protector*`` 标志）可以通过 ESP-IDF 中的 :ref:`CONFIG_COMPILER_STACK_CHECK_MODE` 选项来开启。如果检测到堆栈粉碎，则会打印类似如下的信息：
+
+.. code-block:: none
 
     Stack smashing protect failure!
 
@@ -522,7 +532,7 @@ FreeRTOS 堆栈检查
 
     .. |CPU_EXCEPTIONS_LIST| replace:: 非法指令，加载/存储时的内存对齐错误，加载/存储时的访问权限错误，双重异常。
     .. |ILLEGAL_INSTR_MSG| replace:: IllegalInstruction
-    .. |CACHE_ERR_MSG| replace:: Cache disabled but cached memory region accessed
+    .. |CACHE_ERR_MSG| replace:: Cache error
     .. |STACK_OVERFLOW| replace:: 堆栈溢出
 
 .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
@@ -532,8 +542,19 @@ FreeRTOS 堆栈检查
     .. |CACHE_ERR_MSG| replace:: Cache error
     .. |STACK_OVERFLOW| replace:: 堆栈溢出
 
+
+.. only:: SOC_CPU_HAS_LOCKUP_RESET
+
+    CPU 锁死
+    ^^^^^^^^
+
+    若出现双重异常，即当 CPU 已经在异常处理程序中时，又出现了其他异常，则 CPU 会锁死，并触发系统复位。当 cache 出现问题，导致 CPU 无法访问外部存储时，CPU 就会进入锁死状态。此时，紧急处理程序也会因为无法获取指令或读取数据而崩溃。
+
+    通过配置选项 :ref:`CONFIG_ESP_PANIC_HANDLER_IRAM`，可以将紧急处理程序的代码放在 IRAM 中，这样即使 cache 被禁用也可以访问 IRAM，从而获取更多关于锁死原因的信息。
+
+
 未定义行为清理器 (UBSAN) 检查
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 未定义行为清理器 (UBSAN) 是一种编译器功能，它会为可能不正确的操作添加运行时检查，例如：
 
@@ -544,13 +565,15 @@ FreeRTOS 堆栈检查
 请参考 `GCC 文档 <https://gcc.gnu.org/onlinedocs/gcc/Instrumentation-Options.html>`_ 中的 ``-fsanitize=undefined`` 选项，查看支持检查的完整列表。
 
 使能 UBSAN
-""""""""""""""
+""""""""""
 
 默认情况下未启用 UBSAN。可以通过在构建系统中添加编译器选项 ``-fsanitize=undefined`` 在文件、组件或项目级别上使能 UBSAN。
 
 在对使用 SoC 硬件寄存器头文件（``soc/xxx_reg.h``）的代码使能 UBSAN 时，建议使用 ``-fno-sanitize=shift-base`` 选项禁用移位基数清理器。这是由于 ESP-IDF 寄存器头文件目前包含的模式会对这个特定的清理器选项造成误报。
 
-要在项目级使能 UBSAN，请在项目 CMakeLists.txt 文件的末尾添加以下内容::
+要在项目级使能 UBSAN，请在项目 CMakeLists.txt 文件的末尾添加以下内容：
+
+.. code-block:: none
 
     idf_build_set_property(COMPILE_OPTIONS "-fsanitize=undefined" "-fno-sanitize=shift-base" APPEND)
 
@@ -558,29 +581,37 @@ FreeRTOS 堆栈检查
 
 使能 UBSAN 会明显增加代码量和数据大小。当为整个应用程序使能 UBSAN 时，微控制器的可用 RAM 无法容纳大多数应用程序（除了一些微小程序）。因此，建议为特定的待测组件使能 UBSAN。
 
-要为项目 CMakeLists.txt 文件中的特定组件（``component_name``）启用 UBSAN，请在文件末尾添加以下内容::
+要为项目 CMakeLists.txt 文件中的特定组件（``component_name``）启用 UBSAN，请在文件末尾添加以下内容：
+
+.. code-block:: none
 
     idf_component_get_property(lib component_name COMPONENT_LIB)
     target_compile_options(${lib} PRIVATE "-fsanitize=undefined" "-fno-sanitize=shift-base")
 
-.. 注意::
+.. note::
+
+    关于 :ref:`构建属性 <cmake-build-properties>` 和 :ref:`组件属性 <cmake-component-properties>` 的更多信息，请查看构建系统文档。
 
-  关于 :ref:`构建属性 <cmake-build-properties>` 和 :ref:`组件属性 <cmake-component-properties>` 的更多信息，请查看构建系统文档。
+要为同一组件的 CMakeLists.txt 中的特定组件（``component_name``）使能 UBSAN，在文件末尾添加以下内容：
 
-要为同一组件的 CMakeLists.txt 中的特定组件（``component_name``）使能 UBSAN，在文件末尾添加以下内容::
+.. code-block:: none
 
     target_compile_options(${COMPONENT_LIB} PRIVATE "-fsanitize=undefined" "-fno-sanitize=shift-base")
 
 UBSAN 输出
-""""""""""""""""
+""""""""""
 
-当 UBSAN 检测到一个错误时，会打印一个信息和回溯，例如::
+当 UBSAN 检测到一个错误时，会打印一个信息和回溯，例如：
+
+.. code-block:: none
 
     Undefined behavior of type out_of_bounds
 
     Backtrace:0x4008b383:0x3ffcd8b0 0x4008c791:0x3ffcd8d0 0x4008c587:0x3ffcd8f0 0x4008c6be:0x3ffcd950 0x400db74f:0x3ffcd970 0x400db99c:0x3ffcd9a0
 
-当使用 :doc:`IDF 监视器 <tools/idf-monitor>` 时，回溯会被解码为函数名以及源代码位置，并指向问题发生的位置（这里是 ``main.c:128``）::
+当使用 :doc:`IDF 监视器 <tools/idf-monitor>` 时，回溯会被解码为函数名以及源代码位置，并指向问题发生的位置（这里是 ``main.c:128``）：
+
+.. code-block:: none
 
     0x4008b383: panic_abort at /path/to/esp-idf/components/esp_system/panic.c:367
 
@@ -598,34 +629,34 @@ UBSAN 报告的错误类型为以下几种：
 
 
 .. list-table::
-  :widths: 40 60
-  :header-rows: 1
-
-  * - 名称
-    - 含义
-  * - ``type_mismatch``、``type_mismatch_v1``
-    - 指针值不正确：空、未对齐、或与给定类型不兼容
-  * - ``add_overflow``、``sub_overflow``、``mul_overflow``、``negate_overflow``
-    - 加法、减法、乘法、求反过程中的整数溢出
-  * - ``divrem_overflow``
-    - 整数除以 0 或 ``INT_MIN``
-  * - ``shift_out_of_bounds``
-    - 左移或右移运算符导致的溢出
-  * - ``out_of_bounds``
-    - 访问超出数组范围
-  * - ``unreachable``
-    - 执行无法访问的代码
-  * - ``missing_return``
-    - Non-void 函数已结束而没有返回值（仅限 C++）
-  * - ``vla_bound_not_positive``
-    - 可变长度数组的大小不是正数
-  * - ``load_invalid_value``
-    - bool 或 enum（仅 C++）变量的值无效（超出范围）
-  * - ``nonnull_arg``
-    - 对于 ``nonnull`` 属性的函数，传递给函数的参数为空
-  * - ``nonnull_return``
-    - 对于 ``returns_nonnull`` 属性的函数，函数返回值为空
-  * - ``builtin_unreachable``
-    - 调用 ``__builtin_unreachable`` 函数
-  * - ``pointer_overflow``
-    - 指针运算过程中的溢出
+    :widths: 40 60
+    :header-rows: 1
+
+    * - 名称
+      - 含义
+    * - ``type_mismatch``、``type_mismatch_v1``
+      - 指针值不正确：空、未对齐、或与给定类型不兼容
+    * - ``add_overflow``、``sub_overflow``、``mul_overflow``、``negate_overflow``
+      - 加法、减法、乘法、求反过程中的整数溢出
+    * - ``divrem_overflow``
+      - 整数除以 0 或 ``INT_MIN``
+    * - ``shift_out_of_bounds``
+      - 左移或右移运算符导致的溢出
+    * - ``out_of_bounds``
+      - 访问超出数组范围
+    * - ``unreachable``
+      - 执行无法访问的代码
+    * - ``missing_return``
+      - Non-void 函数已结束而没有返回值（仅限 C++）
+    * - ``vla_bound_not_positive``
+      - 可变长度数组的大小不是正数
+    * - ``load_invalid_value``
+      - bool 或 enum（仅 C++）变量的值无效（超出范围）
+    * - ``nonnull_arg``
+      - 对于 ``nonnull`` 属性的函数，传递给函数的参数为空
+    * - ``nonnull_return``
+      - 对于 ``returns_nonnull`` 属性的函数，函数返回值为空
+    * - ``builtin_unreachable``
+      - 调用 ``__builtin_unreachable`` 函数
+    * - ``pointer_overflow``
+      - 指针运算过程中的溢出
diff --git a/docs/zh_CN/api-guides/flash_psram_config.rst b/docs/zh_CN/api-guides/flash_psram_config.rst
index d121056091b..0dafd6a52f9 100644
--- a/docs/zh_CN/api-guides/flash_psram_config.rst
+++ b/docs/zh_CN/api-guides/flash_psram_config.rst
@@ -73,7 +73,7 @@ SPI Flash 和片外 SPI RAM 配置
 
 .. note::
 
-    如果配有八线 flash 的开发板在第二阶段引导加载程序之前复位，请参考 :ref:`错误处理章节 <flash-psram-error>`。
+    如果配有八线 flash 的开发板在二级引导加载程序之前复位，请参考 :ref:`错误处理章节 <flash-psram-error>`。
 
 
 .. _flash-psram-combination:
@@ -228,7 +228,7 @@ F4R4 硬件
 错误处理
 --------
 
-1. 如果配有八线 flash 的开发板在第二阶段引导加载程序之前复位:
+1. 如果配有八线 flash 的开发板在二级引导加载程序之前复位:
 
     .. code-block:: c
 
@@ -243,7 +243,7 @@ F4R4 硬件
 
    这可能意味着必要的 efuse 未得到正确烧录。请使用命令 ``espefuse.py summary``，检查芯片的 eFuse 位。
 
-   ROM 引导加载程序可通过 eFuse 位 ``FLASH_TYPE`` 将 flash 复位为默认模式（SPI 模式）。如果未烧录此位，且 flash 处于 OPI 模式，则 ROM 引导加载程序可能无法从 flash 中读取并加载以下图像。
+   一级 (ROM) 引导加载程序可通过 eFuse 位 ``FLASH_TYPE`` 将 flash 复位为默认模式（SPI 模式）。如果未烧录此位，且 flash 处于 OPI 模式，则一级 (ROM) 引导加载程序可能无法从 flash 中读取并加载以下图像。
 
 2. 如果启用 :ref:`CONFIG_ESPTOOLPY_OCT_FLASH` 后出现如下错误日志：
 
diff --git a/docs/zh_CN/api-guides/hlinterrupts.rst b/docs/zh_CN/api-guides/hlinterrupts.rst
index 7f78e1a3d9c..07fec7119e7 100644
--- a/docs/zh_CN/api-guides/hlinterrupts.rst
+++ b/docs/zh_CN/api-guides/hlinterrupts.rst
@@ -119,3 +119,5 @@ Xtensa 架构支持 32 个中断处理程序，这些中断分为从 1 到 7 的
 - 中等优先级的中断理论上也可以通过上述方式处理，但 ESP-IDF 尚不支持此功能。
 
 - 要检查 Xtensa 指令集架构 (ISA)，请参阅 `Xtensa ISA 摘要 <https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/tensilica-ip/isa-summary.pdf>`_。
+
+:example:`system/nmi_isr` 提供了一个示例，可以在基于 Xtensa 架构的目标平台上实现自定义 NMI 处理程序。
diff --git a/docs/zh_CN/api-guides/inc/external-ram-esp32-notes.rst b/docs/zh_CN/api-guides/inc/external-ram-esp32-notes.rst
index 6d93693c8de..6c7186a3281 100644
--- a/docs/zh_CN/api-guides/inc/external-ram-esp32-notes.rst
+++ b/docs/zh_CN/api-guides/inc/external-ram-esp32-notes.rst
@@ -1,4 +1,4 @@
-* PSRAM 中的栈：对于不以任何直接或间接方式调用 ROM 中代码的任务，选项 :ref:`CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY` 会取消 :cpp:func:`xTaskCreateStatic` 中的检查，允许任务栈存放在外部 RAM 中。但 **不建议** 使用此选项。
+* PSRAM 中的栈：对于不以任何直接或间接方式调用 ROM 中代码的任务，选项 :ref:`CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM` 会取消 :cpp:func:`xTaskCreateStatic` 中的检查，允许任务栈存放在外部 RAM 中。但 **不建议** 使用此选项。
 * 在以 80 MHz 时钟速度运行时，外部 RAM 还必须占用 HSPI 或 VSPI 总线。设置 :ref:`CONFIG_SPIRAM_OCCUPY_SPI_HOST` 选项可以选择使用的 SPI 主机。
 
 
diff --git a/docs/zh_CN/api-guides/index.rst b/docs/zh_CN/api-guides/index.rst
index 7dbe29957f2..c8eccdc5e25 100644
--- a/docs/zh_CN/api-guides/index.rst
+++ b/docs/zh_CN/api-guides/index.rst
@@ -29,6 +29,7 @@ API 指南
    hardware-abstraction
    :CONFIG_IDF_TARGET_ARCH_XTENSA: hlinterrupts
    jtag-debugging/index
+   kconfig/index
    linker-script-generation
    low-power-mode/index
    lwip
diff --git a/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst b/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst
index ccc150b35cd..3c4ccf32892 100644
--- a/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst
+++ b/docs/zh_CN/api-guides/jtag-debugging/tips-and-quirks.rst
@@ -103,8 +103,20 @@ GDB 具有 FreeRTOS 支持的 Python 扩展模块。在系统要求满足的情
 3.  在某些特殊情况下，如果你看到 DSR/DIR 错误（并且它并不是由 OpenOCD 试图从一个没有物理存储器映射的地址空间读取数据而导致的），请降低 JTAG 的工作频率。
 4.  ESP-WROVER-KIT 能够稳定运行在 20 MHz 或 26 MHz 频率下。
 
+.. only:: SOC_DEBUG_HAVE_OCD_STUB_BINS
 
-.. _jtag-debugging-tip-debugger-startup-commands:
+    .. _jtag-debugging-tip-improve-debugging-speed:
+
+    提高调试速度
+    ^^^^^^^^^^^^^^^^^^^^^^^
+
+    启用 :ref:`CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS` 将预先分配 8 KB 的 RAM, 且预编译的存根二进制文件将嵌入到 RAM 中，因此运行时将无需加载存根二进制文件，从而提高整体调试速度。在使用 flash 断点时，上述优化可以有效降低添加和删除断点的延迟。但要注意，RAM 使用量的增加可能会占用其他任务所需的内存。
+
+    .. _jtag-debugging-tip-debugger-startup-commands:
+
+.. only:: not SOC_DEBUG_HAVE_OCD_STUB_BINS
+
+    .. _jtag-debugging-tip-debugger-startup-commands:
 
 调试器的启动命令的含义
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -232,7 +244,7 @@ JTAG 管脚是否能用于其他功能
 JTAG 与 flash 加密和安全引导
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-默认情况下，开启了 flash 加密和（或者）安全引导后，系统在首次启动时，引导程序会烧写 eFuse 的某个比特，从而将 JTAG 永久关闭。
+默认情况下，开启了 flash 加密和（或者）安全引导后，系统在首次启动时，引导加载程序会烧写 eFuse 的某个比特，从而将 JTAG 永久关闭。
 
 .. only:: SOC_HMAC_SUPPORTED
 
@@ -249,7 +261,7 @@ Kconfig 配置项 :ref:`CONFIG_SECURE_BOOT_ALLOW_JTAG` 可以改变这个默认
 
 .. note::
 
-   同样地，当启用该选项，并且在调试过程中设置了软件断点，引导程序将无法校验通过应用程序的签名。
+   同样地，当启用该选项，并且在调试过程中设置了软件断点，引导加载程序将无法校验通过应用程序的签名。
 
 .. only:: esp32
 
diff --git a/docs/zh_CN/api-guides/kconfig/component-configuration-guide.rst b/docs/zh_CN/api-guides/kconfig/component-configuration-guide.rst
new file mode 100644
index 00000000000..cd27fdcdf04
--- /dev/null
+++ b/docs/zh_CN/api-guides/kconfig/component-configuration-guide.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-guides/kconfig/component-configuration-guide.rst
diff --git a/docs/zh_CN/api-guides/kconfig/configuration_structure.rst b/docs/zh_CN/api-guides/kconfig/configuration_structure.rst
new file mode 100644
index 00000000000..a74801603fe
--- /dev/null
+++ b/docs/zh_CN/api-guides/kconfig/configuration_structure.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-guides/kconfig/configuration_structure.rst
diff --git a/docs/zh_CN/api-guides/kconfig/index.rst b/docs/zh_CN/api-guides/kconfig/index.rst
new file mode 100644
index 00000000000..b1a10e3140e
--- /dev/null
+++ b/docs/zh_CN/api-guides/kconfig/index.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-guides/kconfig/index.rst
diff --git a/docs/zh_CN/api-guides/kconfig/project-configuration-guide.rst b/docs/zh_CN/api-guides/kconfig/project-configuration-guide.rst
new file mode 100644
index 00000000000..62237745100
--- /dev/null
+++ b/docs/zh_CN/api-guides/kconfig/project-configuration-guide.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-guides/kconfig/project-configuration-guide.rst
diff --git a/docs/zh_CN/api-guides/low-power-mode/low-power-mode-wifi.rst b/docs/zh_CN/api-guides/low-power-mode/low-power-mode-wifi.rst
index 3ed8b54f180..2ffe3331e91 100644
--- a/docs/zh_CN/api-guides/low-power-mode/low-power-mode-wifi.rst
+++ b/docs/zh_CN/api-guides/low-power-mode/low-power-mode-wifi.rst
@@ -14,14 +14,13 @@ Wi-Fi 场景下低功耗模式介绍
 
   在介绍具体内容前先给出 Wi-Fi 场景下低功耗模式总结表，以方便用户根据需求快速选择想要了解的内容，选择合适的低功耗模式。
 
-
   .. include:: ../sleep-current/{IDF_TARGET_PATH_NAME}_summary.inc
 
   .. note::
 
       上表中所有电流均为平均电流，所测数据均在屏蔽箱中测试得出。表中术语在下文均有介绍，用户可根据需求进行查看。
 
-.. _Wi-Fi 省电的基本原理:
+.. _Basic Principles of Wi-Fi Power Saving:
 
 Wi-Fi 省电的基本原理
 ---------------------
@@ -90,9 +89,9 @@ Wi-Fi 省电的基本原理
 
 可以看出影响功耗表现的主要有三点：interval、period 和 base current。
 
-  - **interval** 是 station Wi-Fi 相关模块工作的间隔，既可以由低功耗模式自定义，也可根据 Wi-Fi 协议省电机制（详细内容请见 :ref:`Wi-Fi 省电的基本原理`），由 DTIM 周期决定。可以看出在同等情下，interval 越大，功耗表现会更好，但是响应会更慢，影响通信的及时性。
+  - **interval** 是 station Wi-Fi 相关模块工作的间隔，既可以由低功耗模式自定义，也可根据 Wi-Fi 协议省电机制（详细内容请见 :ref:`Basic Principles of Wi-Fi Power Saving`），由 DTIM 周期决定。可以看出在同等情下，interval 越大，功耗表现会更好，但是响应会更慢，影响通信的及时性。
 
-  - **period** 可以看作每次 station Wi-Fi 工作的时间，这段时间的长度也会影响功耗的表现。period 不是一个固定的时长（详细内容请见 :ref:`Wi-Fi 省电的基本原理`），在保证 Wi-Fi 通信正常的情况下，period 持续时间越短，功耗表现越好。但是减少 period 时间，必然会影响通信的可靠性。
+  - **period** 可以看作每次 station Wi-Fi 工作的时间，这段时间的长度也会影响功耗的表现。period 不是一个固定的时长（详细内容请见 :ref:`Basic Principles of Wi-Fi Power Saving`），在保证 Wi-Fi 通信正常的情况下，period 持续时间越短，功耗表现越好。但是减少 period 时间，必然会影响通信的可靠性。
 
   - **base current** 是 Wi-Fi 相关模块不工作时芯片的电流，影响其大小的因素很多，不同的功耗模式下休眠策略不同。所以，在满足功能的情况下，优化配置降低该电流大小可以提高功耗表现，但同时关闭其余模块会影响相关功能和芯片的唤醒时间。
 
@@ -106,7 +105,7 @@ Modem-sleep 模式主要工作原理基于 DTIM 机制，周期性的醒来处
 
 Modem-sleep 模式会在 Wi-Fi 任务结束后自动进入休眠无需调用 API，休眠时仅会关闭 Wi-Fi 相关模块 (PHY)，其余模块均处在正常上电状态。
 
-Modem-sleep 模式默认会根据 DTIM 周期或 listen interval（于 :ref:`Modem-sleep 模式配置` 中介绍）醒来，相当于系统自动设置了一个 Wi-Fi 唤醒源，因此用户无需再配置唤醒源，同时系统主动发包时也可以唤醒。
+Modem-sleep 模式默认会根据 DTIM 周期或 listen interval（于 :ref:`Modem-sleep Mode Configuration` 中介绍）醒来，相当于系统自动设置了一个 Wi-Fi 唤醒源，因此用户无需再配置唤醒源，同时系统主动发包时也可以唤醒。
 
 Modem-sleep 模式是一个开关型的模式，调用 API 开启后一直自动运行，其工作流程十分简单，具体如下图。
 
@@ -121,7 +120,7 @@ Modem-sleep 模式是一个开关型的模式，调用 API 开启后一直自动
 
                           Modem-sleep 模式工作流程图
 
-根据上文的基本电流图，结合 Modem-sleep 模式的工作原理，以 Min Modem 模式（于 :ref:`Modem-sleep 模式配置` 中介绍）为例可得理想情况下电流变化图。
+根据上文的基本电流图，结合 Modem-sleep 模式的工作原理，以 Min Modem 模式（于 :ref:`Modem-sleep Mode Configuration` 中介绍）为例可得理想情况下电流变化图。
 
 .. code-block:: text
 
@@ -294,7 +293,7 @@ Deep-sleep 模式在 Wi-Fi 场景下与纯系统下基本相同，详情可以
   - 丢失 beacon 时睡眠优化 (:ref:`CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT`)
 
 
-.. _Modem-sleep 模式配置:
+.. _Modem-sleep Mode Configuration:
 
 Modem-sleep 模式配置
 +++++++++++++++++++++++
diff --git a/docs/zh_CN/api-guides/lwip.rst b/docs/zh_CN/api-guides/lwip.rst
index 34e8b485fe2..1a659dcd246 100644
--- a/docs/zh_CN/api-guides/lwip.rst
+++ b/docs/zh_CN/api-guides/lwip.rst
@@ -31,9 +31,9 @@ ESP-IDF 间接支持以下常见的 lwIP 应用程序 API：
 
     lwIP 中的 DNS 服务器配置为全局配置，而非针对特定接口的配置。如需同时使用不同 DNS 服务器的多个网络接口，在从一个接口获取 DHCP 租约时，请注意避免意外覆盖另一个接口的 DNS 设置。
 
-- 简单网络时间协议 (SNTP)，由 :doc:`/api-reference/network/esp_netif` 功能间接支持，或通过 :component_file:`lwip/include/apps/esp_sntp.h` 中的函数直接支持。该函数还为 :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` 函数提供了线程安全的 API，请参阅 :ref:`system-time-sntp-sync`。
+- 简单网络时间协议 (SNTP)，由 :doc:`/api-reference/network/esp_netif` 功能间接支持，或通过 :component_file:`lwip/include/apps/esp_sntp.h` 中的函数直接支持。该函数还为 :component_file:`lwip/lwip/src/include/lwip/apps/sntp.h` 函数提供了线程安全的 API，请参阅 :ref:`system-time-sntp-sync`。有关详细信息，请见 :example:`protocols/sntp`。该示例演示了如何使用 LwIP SNTP 模块从互联网服务器获取时间、配置同步方法与时间间隔，并使用 SNTP-over-DHCP 模块检索时间。
 - ICMP Ping，由 lwIP ping API 的变体支持，请参阅 :doc:`/api-reference/protocols/icmp_echo`。
-- ICMPv6 Ping，由 lwIP 的 ICMPv6 Echo API 支持，用于测试 IPv6 网络连接情况。有关详细信息，请参阅 :example:`protocols/sockets/icmpv6_ping`。
+- ICMPv6 Ping，由 lwIP 的 ICMPv6 Echo API 支持，用于测试 IPv6 网络连接情况。有关详细信息，请参阅 :example:`protocols/sockets/icmpv6_ping`。该示例演示了如何使用网络接口发现 IPv6 地址，创建原始 ICMPv6 套接字，向目标 IPv6 地址发送 ICMPv6 Echo 请求，并等待目标返回 Echo 回复。
 - NetBIOS 查找，由标准的 lwIP API 支持，:example:`protocols/http_server/restful_server` 示例中提供了使用 NetBIOS 在局域网中查找主机的选项。
 - mDNS 与 lwIP 的默认 mDNS 使用不同实现方式，请参阅 :doc:`/api-reference/protocols/mdns`。但启用 :ref:`CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES` 设置项后，lwIP 可以使用 ``gethostbyname()`` 等标准 API 和 ``hostname.local`` 约定查找 mDNS 主机。
 - lwIP 中的 PPP 实现可用于在 ESP-IDF 中创建 PPPoS（串行 PPP）接口。请参阅 :doc:`/api-reference/network/esp_netif` 组件文档，使用 :component_file:`esp_netif/include/esp_netif_defaults.h` 中定义的 ``ESP_NETIF_DEFAULT_PPP()`` 宏创建并配置 PPP 网络接口。:component_file:`esp_netif/include/esp_netif_ppp.h` 中提供了其他的运行时设置。PPPoS 接口通常用于与 NBIoT/GSM/LTE 调制解调器交互。`esp_modem <https://components.espressif.com/component/espressif/esp_modem>`_ 仓库还支持更多应用层友好的 API，该仓库内部使用了上述 PPP lwIP 模块。
@@ -43,7 +43,7 @@ BSD 套接字 API
 
 BSD 套接字 API 是一种常见的跨平台 TCP/IP 套接字 API，最初源于 UNIX 操作系统的伯克利标准发行版，现已标准化为 POSIX 规范的一部分。BSD 套接字有时也称 POSIX 套接字，或伯克利套接字。
 
-在 ESP-IDF 中，lwIP 支持 BSD 套接字 API 的所有常见用法。
+在 ESP-IDF 中，lwIP 支持 BSD 套接字 API 的所有常见用法。然而，并非所有操作都完全线程安全，因此多个线程同时进行读写可能需要额外的同步机制。详情请参见 :ref:`lwip-limitations`。
 
 参考
 ^^^^^^^^^^
@@ -58,12 +58,19 @@ BSD 套接字的相关参考资料十分丰富，包括但不限于：
 
 以下为 ESP-IDF 中使用 BSD 套接字 API 的部分示例：
 
-- :example:`protocols/sockets/tcp_server`
-- :example:`protocols/sockets/tcp_client`
-- :example:`protocols/sockets/udp_server`
-- :example:`protocols/sockets/udp_client`
-- :example:`protocols/sockets/udp_multicast`
-- :example:`protocols/http_request`：此简化示例使用 TCP 套接字发送 HTTP 请求，但更推荐使用 :doc:`/api-reference/protocols/esp_http_client` 发送 HTTP 请求
+- :example:`protocols/sockets/non_blocking` 演示了如何配置和运行一个支持 IPv4 和 IPv6 协议的非阻塞 TCP 客户端和服务器。
+
+- :example:`protocols/sockets/tcp_server` 演示了如何创建一个 TCP 服务器，该服务器可以接受客户端的连接请求并接收数据。
+
+- :example:`protocols/sockets/tcp_client` 演示了如何创建一个 TCP 客户端，该客户端使用预定义的 IP 地址和端口连接到服务器。
+
+- :example:`protocols/sockets/tcp_client_multi_net` 演示了如何同时使用以太网和 Wi-Fi 接口连接，在每个接口上创建一个 TCP 客户端，并发送一个简单的 HTTP 请求和响应。
+
+- :example:`protocols/sockets/udp_server` 演示了如何创建一个 UDP 服务器，该服务器可以接收客户端的连接请求和数据。
+
+- :example:`protocols/sockets/udp_client` 演示了如何创建一个 UDP 客户端，该客户端使用预定义的 IP 地址和端口连接到服务器。
+
+- :example:`protocols/sockets/udp_multicast` 演示了如何通过 BSD 风格的套接字接口使用 IPV4 和 IPV6 的 UDP 组播功能。
 
 支持的函数
 ^^^^^^^^^^^^^^^^^^^
@@ -454,9 +461,13 @@ NAPT 和端口转发
 
 另一种方法是在头文件中定义函数式宏，该头文件将预先包含在 lwIP 钩子文件中，请参考 :ref:`lwip-custom-hooks`。
 
+.. _lwip-limitations:
+
 限制
 ^^^^^^^^^^^
 
+在 ESP-IDF 中，lwIP 在某些场景下线程安全，但存在一定的限制。在 lwIP 中，可以在同一套接字上由多个线程同时分别执行读、写和关闭操作，但不支持在同一套接字上由多个线程同时执行多个读操作或多个写操作。如果应用程序需要在多个线程中同时对同一套接字进行读、写操作，就需要额外的同步机制来确保线程安全。例如，在套接字操作周围加锁。
+
 如 :ref:`lwip-dns-limitation` 所述，ESP-IDF 中的 lwIP 扩展功能仍然受到全局 DNS 限制的影响。为了在应用程序代码中解决这一限制，可以使用 ``FALLBACK_DNS_SERVER_ADDRESS()`` 宏定义所有接口能够访问的全局 DNS 备用服务器，或者单独维护每个接口的 DNS 服务器，并在默认接口更改时重新配置。
 
 通过网络数据库 API 返回的 IP 地址数量受限：``getaddrinfo()`` 和 ``gethostbyname()`` 受到宏 ``DNS_MAX_HOST_IP`` 的限制，宏的默认值为 1。
diff --git a/docs/zh_CN/api-guides/partition-tables.rst b/docs/zh_CN/api-guides/partition-tables.rst
index 7297ccf5284..f6f95aec2c5 100644
--- a/docs/zh_CN/api-guides/partition-tables.rst
+++ b/docs/zh_CN/api-guides/partition-tables.rst
@@ -8,64 +8,84 @@
 
 每片 {IDF_TARGET_NAME} 的 flash 可以包含多个应用程序，以及多种不同类型的数据（例如校准数据、文件系统数据、参数存储数据等）。因此，我们在 flash 的 :ref:`默认偏移地址 <CONFIG_PARTITION_TABLE_OFFSET>` 0x8000 处烧写一张分区表。
 
-分区表的长度为 0xC00 字节，最多可以保存 95 条分区表条目。MD5 校验和附加在分区表之后，用于在运行时验证分区表的完整性。分区表占据了整个 flash 扇区，大小为 0x1000 (4 KB)。因此，它后面的任何分区至少需要位于 (:ref:`默认偏移地址 <CONFIG_PARTITION_TABLE_OFFSET>`) + 0x1000 处。
+分区表的长度为 0xC00 字节，最多可以保存 95 条分区表条目。MD5 校验和附加在分区表之后，用于在运行时验证分区表的完整性。分区表占据了整个 flash 扇区，大小为 0x1000 (4 KB)。因此，它后面的任何分区至少需要位于（:ref:`默认偏移地址 <CONFIG_PARTITION_TABLE_OFFSET>`） + 0x1000 处。
 
 分区表中的每个条目都包括以下几个部分：Name（标签）、Type（app、data 等）、SubType 以及在 flash 中的偏移量（分区的加载地址）。
 
-在使用分区表时，最简单的方法就是打开项目配置菜单（``idf.py menuconfig``），并在 :ref:`CONFIG_PARTITION_TABLE_TYPE` 下选择一个预定义的分区表：
+在使用分区表时，最简单的方法就是打开项目配置菜单 (``idf.py menuconfig``)，并在 :ref:`CONFIG_PARTITION_TABLE_TYPE` 下选择一个预定义的分区表：
 
--  "Single factory app, no OTA"
--  "Factory app, two OTA definitions"
+* "Single factory app, no OTA"
+* "Factory app, two OTA definitions"
 
 在以上两种选项中，出厂应用程序均将被烧录至 flash 的 0x10000 偏移地址处。这时，运行 ``idf.py partition-table``，即可以打印当前使用分区表的信息摘要。
 
 内置分区表
-------------
+----------
 
-以下是 "Single factory app, no OTA" 选项的分区表信息摘要::
+以下是 "Single factory app, no OTA" 选项的分区表信息摘要：
 
-   # ESP-IDF Partition Table
-   # Name,   Type, SubType, Offset,  Size,   Flags
-   nvs,      data, nvs,     0x9000,  0x6000,
-   phy_init, data, phy,     0xf000,  0x1000,
-   factory,  app,  factory, 0x10000, 1M,
+.. code-block:: none
 
--  flash 的 0x10000 (64 KB) 偏移地址处存放一个标记为 "factory" 的二进制应用程序，且启动加载器将默认加载这个应用程序。
+    # ESP-IDF Partition Table
+    # Name,   Type, SubType, Offset,  Size,   Flags
+    nvs,      data, nvs,     0x9000,  0x6000,
+    phy_init, data, phy,     0xf000,  0x1000,
+    factory,  app,  factory, 0x10000, 1M,
+
+-  flash 的 0x10000 (64 KB) 偏移地址处存放一个标记为 "factory" 的二进制应用程序，引导加载程序默认加载这个应用程序。
 -  分区表中还定义了两个数据区域，分别用于存储 NVS 库专用分区和 PHY 初始化数据。
 
-以下是 "Factory app, two OTA definitions" 选项的分区表信息摘要::
+以下是 "Factory app, two OTA definitions" 选项的分区表信息摘要：
+
+.. code-block:: none
 
-  # ESP-IDF Partition Table
-  # Name,   Type, SubType, Offset,  Size, Flags
-  nvs,      data, nvs,     0x9000,  0x4000,
-  otadata,  data, ota,     0xd000,  0x2000,
-  phy_init, data, phy,     0xf000,  0x1000,
-  factory,  app,  factory, 0x10000,  1M,
-  ota_0,    app,  ota_0,   0x110000, 1M,
-  ota_1,    app,  ota_1,   0x210000, 1M,
+    # ESP-IDF Partition Table
+    # Name,   Type, SubType, Offset,  Size, Flags
+    nvs,      data, nvs,     0x9000,  0x4000,
+    otadata,  data, ota,     0xd000,  0x2000,
+    phy_init, data, phy,     0xf000,  0x1000,
+    factory,  app,  factory, 0x10000,  1M,
+    ota_0,    app,  ota_0,   0x110000, 1M,
+    ota_1,    app,  ota_1,   0x210000, 1M,
 
--  分区表中定义了三个应用程序分区，这三个分区的类型都被设置为 “app”，但具体 app 类型不同。其中，位于 0x10000 偏移地址处的为出厂应用程序 (factory)，其余两个为 OTA 应用程序（ota_0，ota_1）。
--  新增了一个名为 “otadata” 的数据分区，用于保存 OTA 升级时需要的数据。启动加载器会查询该分区的数据，以判断该从哪个 OTA 应用程序分区加载程序。如果 “otadata” 分区为空，则会执行出厂程序。
+*  分区表中定义了三个应用程序分区，这三个分区的类型都被设置为 “app”，但具体 app 类型不同。其中，位于 0x10000 偏移地址处的为出厂应用程序 (factory)，其余两个为 OTA 应用程序 (ota_0, ota_1)。
+*  新增了一个名为 "otadata" 的数据分区，用于保存 OTA 升级时需要的数据。引导加载程序会查询该分区的数据，以判断该从哪个 OTA 应用程序分区加载程序。如果 "otadata" 分区为空，则会执行出厂程序。
 
 创建自定义分区表
 ----------------
 
-如果在 ``menuconfig`` 中选择了 “Custom partition table CSV”，则还需要输入该分区表的 CSV 文件在项目中的路径。CSV 文件可以根据需要，描述任意数量的分区信息。
+如果在 ``menuconfig`` 中选择了 "Custom partition table CSV"，则还需要输入该分区表的 CSV 文件在项目中的路径。CSV 文件可以根据需要，描述任意数量的分区信息。
+
+CSV 文件的格式与上面摘要中打印的格式相同，但是在 CSV 文件中并非所有字段都是必需的。例如下面是一个自定义的 OTA 分区表的 CSV 文件：
+
+.. code-block:: none
+
+    # Name,   Type, SubType,  Offset,   Size,  Flags
+    nvs,      data, nvs,      0x9000,  0x4000
+    otadata,  data, ota,      0xd000,  0x2000
+    phy_init, data, phy,      0xf000,  0x1000
+    factory,  app,  factory,  0x10000,  1M
+    ota_0,    app,  ota_0,    ,         1M
+    ota_1,    app,  ota_1,    ,         1M
+    nvs_key,  data, nvs_keys, ,        0x1000
 
-CSV 文件的格式与上面摘要中打印的格式相同，但是在 CSV 文件中并非所有字段都是必需的。例如下面是一个自定义的 OTA 分区表的 CSV 文件::
+*  字段之间的空格会被忽略，任何以 ``#`` 开头的行（注释）也会被忽略。
+*  CSV 文件中的每个非注释行均为一个分区定义。
+*  每个分区的 ``Offset`` 字段可以为空，``gen_esp32part.py`` 工具会从分区表位置的后面开始自动计算并填充该分区的偏移地址，同时确保每个分区的偏移地址正确对齐。
 
-   # Name,   Type, SubType,  Offset,   Size,  Flags
-   nvs,      data, nvs,      0x9000,  0x4000
-   otadata,  data, ota,      0xd000,  0x2000
-   phy_init, data, phy,      0xf000,  0x1000
-   factory,  app,  factory,  0x10000,  1M
-   ota_0,    app,  ota_0,    ,         1M
-   ota_1,    app,  ota_1,    ,         1M
-   nvs_key,  data, nvs_keys, ,        0x1000
+下面是一个包含引导加载程序和分区表分区的 CSV 分区表示例：
 
--  字段之间的空格会被忽略，任何以 ``#`` 开头的行（注释）也会被忽略。
--  CSV 文件中的每个非注释行均为一个分区定义。
--  每个分区的 ``Offset`` 字段可以为空，``gen_esp32part.py`` 工具会从分区表位置的后面开始自动计算并填充该分区的偏移地址，同时确保每个分区的偏移地址正确对齐。
+.. code-block:: none
+
+    # ESP-IDF Partition Table
+    # Name,           Type,            SubType,  Offset,  Size,     Flags
+    bootloader,       bootloader,      primary,  N/A,     N/A,
+    partition_table,  partition_table, primary,  N/A,     N/A,
+    nvs,              data,            nvs,      ,        0x6000,
+    phy_init,         data,            phy,      ,        0x1000,
+    factory,          app,             factory,  ,        1M,
+
+``gen_esp32part.py`` 工具将根据所选的 Kconfig 选项将每个 ``N/A`` 替换为适当的值：引导加载程序的偏移地址为 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH}，分区表的偏移地址见 :ref:`CONFIG_PARTITION_TABLE_OFFSET`。
 
 Name 字段
 ~~~~~~~~~
@@ -75,75 +95,96 @@ Name 字段可以是任何有意义的名称，但不能超过 16 个字节，
 Type 字段
 ~~~~~~~~~
 
-Type 字段可以指定为 app (0x00) 或者 data (0x01)，也可以直接使用数字 0-254（或者十六进制 0x00-0xFE）。注意，0x00-0x3F 不得使用（预留给 esp-idf 的核心功能）。
+Type 字段可以指定为名称或数字 0～254（或者十六进制 0x00-0xFE）。注意，不得使用预留给 ESP-IDF 核心功能的 0x00-0x3F。
 
-如果你的应用程序需要以 ESP-IDF 尚未支持的格式存储数据，请在 0x40-0xFE 内添加一个自定义分区类型。
+- ``app`` (0x00)，
+- ``data`` (0x01)，
+- ``bootloader`` (0x02)。该分区为可选项且不会影响系统功能，因此默认情况下，该分区不会出现在 ESP-IDF 的任何 CSV 分区表文件中，仅在引导加载程序 OTA 更新和 flash 分区时有用。即使 CSV 文件中没有该分区，仍然可以执行 OTA。
+- ``partition_table`` (0x03)。默认情况下，该分区也不会出现在 ESP-IDF 的任何 CSV 分区表文件中。
+- 0x40-0xFE 预留给 **自定义分区类型**。如果你的应用程序需要以 ESP-IDF 尚未支持的格式存储数据，请在 0x40-0xFE 内添加一个自定义分区类型。
 
-参考 :cpp:type:`esp_partition_type_t` 关于 ``app`` 和 ``data`` 分区的枚举定义。
+关于 ``app`` 和 ``data`` 分区的枚举定义，请参考 :cpp:type:`esp_partition_type_t`。
 
-如果用 C++ 编写，那么指定一个应用程序定义的分区类型，需要在 :cpp:type:`esp_partition_type_t` 中使用整数，从而与 :ref:`分区 API<api-reference-partition-table>` 一起使用。例如::
+如果用 C++ 编写，那么指定一个应用程序定义的分区类型，需要在 :cpp:type:`esp_partition_type_t` 中使用整数，从而与 :ref:`分区 API<api-reference-partition-table>` 一起使用。例如：
+
+.. code-block:: none
 
     static const esp_partition_type_t APP_PARTITION_TYPE_A = (esp_partition_type_t)0x40;
 
-注意，启动加载器将忽略 ``app`` (0x00) 和 ``data`` (0x01) 以外的其他分区类型。
+注意，引导加载程序会忽略 ``app`` (0x00) 和 ``data`` (0x01) 以外的其他分区类型。
 
 SubType 字段
 ~~~~~~~~~~~~
-{IDF_TARGET_ESP_PHY_REF:default = ":ref:`CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION`", esp32p4, esp32c5, esp32c61 = "NOT UPDATED YET"}
 
-SubType 字段长度为 8 bit，内容与具体分区 Type 有关。目前，esp-idf 仅仅规定了 “app” 和 “data” 两种分区类型的子类型含义。
+{IDF_TARGET_ESP_PHY_REF:default = ":ref:`CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION`", esp32p4, esp32c5, esp32c61 = "尚未更新"}
+
+SubType 字段长度为 8 bit，内容与具体分区 Type 有关。目前，ESP-IDF 仅仅规定了 ``app`` 和 ``data`` 两种分区类型的子类型含义。
 
 参考 :cpp:type:`esp_partition_subtype_t`，以了解 ESP-IDF 定义的全部子类型列表，包括：
 
 * 当 Type 定义为 ``app`` 时，SubType 字段可以指定为 ``factory`` (0x00)、 ``ota_0`` (0x10) … ``ota_15`` (0x1F) 或者 ``test`` (0x20)。
 
-   -  ``factory`` (0x00) 是默认的 app 分区。启动加载器将默认加载该应用程序。但如果存在类型为 data/ota 分区，则启动加载器将加载 data/ota 分区中的数据，进而判断启动哪个 OTA 镜像文件。
+    -  ``factory`` (0x00) 是默认的 app 分区。引导加载程序将默认加载该应用程序。但如果存在类型为 data/ota 的分区，则引导加载程序将加载 data/ota 分区中的数据，进而判断启动哪个 OTA 镜像文件。
+
+        -  OTA 升级永远都不会更新 factory 分区中的内容。
+        -  如果你希望在 OTA 项目中预留更多 flash，可以删除 factory 分区，转而使用 ota_0 分区。
+
+    -  ``ota_0`` (0x10) … ``ota_15`` (0x1F) 为 OTA 应用程序分区，引导加载程序将根据 OTA 数据分区中的数据来决定加载哪个 OTA 应用程序分区中的程序。在使用 OTA 功能时，应用程序应至少拥有 2 个 OTA 应用程序分区（``ota_0`` 和 ``ota_1``）。更多详细信息，请参考 :doc:`OTA 文档 </api-reference/system/ota>`。
+    -  ``test`` (0x20) 为预留的子类型，用于工厂测试流程。如果没有其他有效 app 分区，test 将作为备选启动分区使用。也可以配置引导加载程序在每次启动时读取 GPIO，如果 GPIO 被拉低则启动该分区。详细信息请查阅 :ref:`bootloader_boot_from_test_firmware`。
+
+* 当 Type 定义为 ``bootloader`` 时，可以将 SubType 字段指定为：
 
-      -  OTA 升级永远都不会更新 factory 分区中的内容。
-      -  如果你希望在 OTA 项目中预留更多 flash，可以删除 factory 分区，转而使用 ota_0 分区。
+    - ``primary`` (0x00)，即二级引导加载程序，位于 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 地址处。工具会自动确定此子类型的适当大小和偏移量，因此为此子类型指定的任何大小或偏移量将被忽略。你可以将这些字段留空或使用 ``N/A`` 作为占位符。
+    - ``ota`` (0x01)，是一个临时的引导加载程序分区，在 OTA 更新期间可用于下载新的引导加载程序镜像。工具会忽略此子类型的大小，你可以将其留空或使用 ``N/A``。你只能指定一个偏移量，或者将其留空，工具将根据先前使用的分区的偏移量进行计算。
 
-   -  ota_0 (0x10) … ota_15 (0x1F) 为 OTA 应用程序分区，启动加载器将根据 OTA 数据分区中的数据来决定加载哪个 OTA 应用程序分区中的程序。在使用 OTA 功能时，应用程序应至少拥有 2 个 OTA 应用程序分区（``ota_0`` 和 ``ota_1``）。更多详细信息，请参考 :doc:`OTA 文档 </api-reference/system/ota>` 。
-   -  ``test`` (0x20) 为预留的子类型，用于工厂测试流程。如果没有其他有效 app 分区，test 将作为备选启动分区使用。也可以配置启动加载器在每次启动时读取 GPIO，如果 GPIO 被拉低则启动该分区。详细信息请查阅 :ref:`bootloader_boot_from_test_firmware`。
+    引导加载程序的大小由 ``gen_esp32part.py`` 工具根据指定的 ``--offset`` (分区表偏移量) 和 ``--primary-partition-offset`` 参数计算。具体而言，引导加载程序的大小定义为 (:ref:`CONFIG_PARTITION_TABLE_OFFSET` - {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH})。此计算的大小适用于引导加载程序的所有子类型。
 
-* 当 Type 定义为 ``data`` 时，SubType 字段可以指定为 ``ota`` (0x00)、``phy`` (0x01)、``nvs`` (0x02)、``nvs_keys`` (0x04) 或者其他组件特定的子类型（请参考 :cpp:type:`子类型枚举 <esp_partition_subtype_t>`).
+* 当 Type 定义为 ``partition_table`` 时，可以将 SubType 字段指定为：
 
-   -  ``ota`` (0) 即 :ref:`OTA 数据分区 <ota_data_partition>` ，用于存储当前所选的 OTA 应用程序的信息。这个分区的大小需要设定为 0x2000。更多详细信息，请参考 :doc:`OTA 文档 <../api-reference/system/ota>` 。
-   -  ``phy`` (1) 分区用于存放 PHY 初始化数据，从而保证可以为每个设备单独配置 PHY，而非必须采用固件中的统一 PHY 初始化数据。
+    - ``primary`` (0x00)，是主分区表，位于 flash 的 :ref:`CONFIG_PARTITION_TABLE_OFFSET` 地址处。工具会自动确定此子类型的适当大小和偏移量，因此为此子类型指定的任何大小或偏移量将被忽略。你可以将这些字段留空或使用 ``N/A`` 作为占位符。
+    - ``ota`` (0x01)，是一个临时的分区表分区，在 OTA 更新期间可用于下载新的分区表镜像。工具会忽略此子类型的大小，你可以将其留空或使用 ``N/A``。你可以指定一个偏移量，或者将其留空，工具将根据先前分配的分区的偏移量进行计算。
 
-      -  默认配置下，phy 分区并不启用，而是直接将 phy 初始化数据编译至应用程序中，从而节省分区表空间（直接将此分区删掉）。
-      -  如果需要从此分区加载 phy 初始化数据，请打开项目配置菜单（``idf.py menuconfig``），并且使能 {IDF_TARGET_ESP_PHY_REF} 选项。此时，还需要手动将 phy 初始化数据烧至设备 flash（esp-idf 编译系统并不会自动完成该操作）。
-   -  ``nvs`` (2) 是专门给 :doc:`非易失性存储 (NVS) API <../api-reference/storage/nvs_flash>` 使用的分区。
+    ``partition_table`` 的大小固定为 ``0x1000``，适用于 ``partition_table`` 的所有子类型。
 
-      -  用于存储每台设备的 PHY 校准数据（注意，并不是 PHY 初始化数据）。
+* 当 Type 定义为 ``data`` 时，SubType 字段可以指定为 ``ota`` (0x00)、``phy`` (0x01)、``nvs`` (0x02)、``nvs_keys`` (0x04) 或者其他组件特定的子类型（请参考 :cpp:type:`子类型枚举 <esp_partition_subtype_t>`）。
 
-      .. only:: SOC_WIFI_SUPPORTED
+    -  ``ota`` (0) 即 :ref:`OTA 数据分区 <ota_data_partition>` ，用于存储当前所选的 OTA 应用程序的信息。这个分区的大小需要设定为 0x2000。更多详细信息，请参考 :doc:`OTA 文档 <../api-reference/system/ota>` 。
+    -  ``phy`` (1) 分区用于存放 PHY 初始化数据，从而保证可以为每个设备单独配置 PHY，而非必须采用固件中的统一 PHY 初始化数据。
 
-          -  用于存储 Wi-Fi 数据（如果使用了 :doc:`esp_wifi_set_storage(WIFI_STORAGE_FLASH) <../api-reference/network/esp_wifi>` 初始化函数）。
+        -  默认配置下，phy 分区并不启用，而是直接将 phy 初始化数据编译至应用程序中，从而节省分区表空间（直接将此分区删掉）。
+        -  如果需要从此分区加载 phy 初始化数据，请打开项目配置菜单（``idf.py menuconfig``），并且使能 {IDF_TARGET_ESP_PHY_REF} 选项。此时，还需要手动将 phy 初始化数据烧至设备 flash（esp-idf 编译系统并不会自动完成该操作）。
+    -  ``nvs`` (2) 是专门给 :doc:`非易失性存储 (NVS) API <../api-reference/storage/nvs_flash>` 使用的分区。
 
-      -  NVS API 还可以用于其他应用程序数据。
-      -  强烈建议为 NVS 分区分配至少 0x3000 字节空间。
-      -  如果使用 NVS API 存储大量数据，请增加 NVS 分区的大小（默认是 0x6000 字节）。
-   -  ``nvs_keys`` (4) 是 NVS 秘钥分区。详细信息，请参考 :doc:`非易失性存储 (NVS) API <../api-reference/storage/nvs_flash>` 文档。
+        -  用于存储每台设备的 PHY 校准数据（注意，并不是 PHY 初始化数据）。
 
-      -  用于存储加密密钥（如果启用了 `NVS 加密` 功能）。
-      -  此分区应至少设定为 4096 字节。
+        .. only:: SOC_WIFI_SUPPORTED
 
-  - ESP-IDF 还支持其他用于数据存储的预定义子类型，包括：
+            -  用于存储 Wi-Fi 数据（如果使用了 :doc:`esp_wifi_set_storage(WIFI_STORAGE_FLASH) <../api-reference/network/esp_wifi>` 初始化函数）。
 
-    - ``coredump`` (0x03) 用于在使用自定义分区表 CSV 文件时存储核心转储，详情请参阅 :doc:`/api-guides/core_dump`。
-    - ``efuse`` (0x05) 使用 :ref:`虚拟 eFuse <virtual-efuses>` 模拟 eFuse 位。
-    - ``undefined`` (0x06) 隐式用于未指定子类型（即子类型为空）的数据分区，但也可显式将其标记为未定义。
-    - ``fat`` (0x81) 用于 :doc:`/api-reference/storage/fatfs`。
-    - ``spiffs`` (0x82) 用于 :doc:`/api-reference/storage/spiffs`。
-    - ``littlefs`` (0x83) 用于 `LittleFS 文件系统 <https://github.com/littlefs-project/littlefs>`_，详情可参阅 :example:`storage/littlefs` 示例。
+        -  NVS API 还可以用于其他应用程序数据。
+        -  强烈建议为 NVS 分区分配至少 0x3000 字节空间。
+        -  如果使用 NVS API 存储大量数据，请增加 NVS 分区的大小（默认是 0x6000 字节）。
+    - ``nvs_keys`` (4) 是 NVS 秘钥分区。详细信息，请参考 :doc:`非易失性存储 (NVS) API <../api-reference/storage/nvs_flash>` 文档。
+
+        -  用于存储加密密钥（如果启用了 `NVS 加密` 功能）。
+        -  此分区应至少设定为 4096 字节。
+
+    - ESP-IDF 还支持其他用于数据存储的预定义子类型，包括：
+
+        - ``coredump`` (0x03) 用于在使用自定义分区表 CSV 文件时存储核心转储，详情请参阅 :doc:`/api-guides/core_dump`。
+        - ``efuse`` (0x05) 使用 :ref:`虚拟 eFuse <virtual-efuses>` 模拟 eFuse 位。
+        - ``undefined`` (0x06) 隐式用于未指定子类型（即子类型为空）的数据分区，但也可显式将其标记为未定义。
+        - ``fat`` (0x81) 用于 :doc:`/api-reference/storage/fatfs`。
+        - ``spiffs`` (0x82) 用于 :doc:`/api-reference/storage/spiffs`。
+        - ``littlefs`` (0x83) 用于 `LittleFS 文件系统 <https://github.com/littlefs-project/littlefs>`_，详情可参阅 :example:`storage/littlefs` 示例。
 
 .. Comment: ``esphttpd`` (0x80) was not added to the list because there is no docs section for it and it is not clear whether user should use it explicitly.
 
-  其它数据子类型已预留给 ESP-IDF 未来使用。
+    其它数据子类型已预留给 ESP-IDF 未来使用。
 
 * 如果分区类型是由应用程序定义的任意值 (0x40-0xFE)，那么 ``subtype`` 字段可以是由应用程序选择的任何值 (0x00-0xFE)。
 
-  请注意，如果用 C++ 编写，应用程序定义的子类型值需要转换为 :cpp:type:`esp_partition_type_t`，从而与 :ref:`分区 API <api-reference-partition-table>` 一起使用。
+    请注意，如果用 C++ 编写，应用程序定义的子类型值需要转换为 :cpp:type:`esp_partition_type_t`，从而与 :ref:`分区 API <api-reference-partition-table>` 一起使用。
 
 额外分区 SubType 字段
 ~~~~~~~~~~~~~~~~~~~~~~~~
@@ -152,17 +193,19 @@ SubType 字段长度为 8 bit，内容与具体分区 Type 有关。目前，esp
 
 .. _partition-offset-and-size:
 
-偏移地址 (Offset) 和 大小 (Size) 字段
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+偏移地址 (Offset) 和大小 (Size) 字段
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 .. list::
 
-   - 偏移地址表示 SPI flash 中的分区地址，扇区大小为 0x1000 (4 KB)。因此，偏移地址必须是 4 KB 的倍数。
-   - 若 CSV 文件中的分区偏移地址为空，则该分区会接在前一个分区之后；若为首个分区，则将接在分区表之后。
-   - ``app`` 分区的偏移地址必须与 0x10000 (64 KB) 对齐。如果偏移字段留空，则 ``gen_esp32part.py`` 工具会自动计算得到一个满足对齐要求的偏移地址。如果 ``app`` 分区的偏移地址没有与 0x10000 (64 KB) 对齐，则该工具会报错。
-   - ``app`` 分区的大小必须与 flash 扇区大小对齐。为 ``app`` 分区指定未对齐的大小将返回错误。
-   :SOC_SECURE_BOOT_V1: - 若启用了安全启动 V1，则 ``app`` 分区的大小需与 0x10000 (64 KB) 对齐。
-   - ``app`` 分区的大小和偏移地址可以采用十进制数或是以 0x 为前缀的十六进制数，且支持 K 或 M 的倍数单位（K 和 M 分别代表 1024 和 1024*1024 字节）。
+    - 偏移地址表示 SPI flash 中的分区地址，扇区大小为 0x1000 (4 KB)。因此，偏移地址必须是 4 KB 的倍数。
+    - 若 CSV 文件中的分区偏移地址为空，则该分区会接在前一个分区之后；若为首个分区，则将接在分区表之后。
+    - ``app`` 分区的偏移地址必须与 0x10000 (64 KB) 对齐。如果偏移字段留空，则 ``gen_esp32part.py`` 工具会自动计算得到一个满足对齐要求的偏移地址。如果 ``app`` 分区的偏移地址没有与 0x10000 (64 KB) 对齐，则该工具会报错。
+    - ``app`` 分区的大小必须与 flash 扇区大小对齐。为 ``app`` 分区指定未对齐的大小将返回错误。
+    :SOC_SECURE_BOOT_V1: - 若启用了 Secure Boot V1，则 ``app`` 分区的大小需与 0x10000 (64 KB) 对齐。
+    :SOC_SECURE_BOOT_V1: - ``bootloader`` 的偏移量和大小不受 Secure Boot V1 选项的影响。无论是否启用 Secure Boot V1，引导加载程序的大小保持不变，并且不包括安全摘要，安全摘要位于 flash 的 0x0 偏移地址处，占用一个扇区（4096 字节）。
+    - ``app`` 分区的大小和偏移地址可以采用十进制数或是以 0x 为前缀的十六进制数，且支持 K 或 M 的倍数单位（K 和 M 分别代表 1024 和 1024*1024 字节）。
+    - 对于 ``bootloader`` 和 ``partition_table``，在 CSV 文件中将大小和偏移量指定为 ``N/A`` 意味着这些值将由工具自动确定，无法手动定义。这需要设置 ``gen_esp32part.py`` 工具的 ``--offset`` 和 ``--primary-partition-offset`` 参数。
 
 如果你希望允许分区表中的分区采用任意起始偏移量 (:ref:`CONFIG_PARTITION_TABLE_OFFSET`)，请将分区表（CSV 文件）中所有分区的偏移字段都留空。注意，此时，如果你更改了分区表中任意分区的偏移地址，则其他分区的偏移地址也会跟着改变。这种情况下，如果你之前还曾设定某个分区采用固定偏移地址，则可能造成分区表冲突，从而导致报错。
 
@@ -171,17 +214,25 @@ Flags 字段
 
 目前支持 ``encrypted`` 和 ``readonly`` 标记：
 
-  - 如果 Flags 字段设置为 ``encrypted``，且已启用 :doc:`/security/flash-encryption` 功能，则该分区将会被加密。
+    - 如果 Flags 字段设置为 ``encrypted``，且已启用 :doc:`/security/flash-encryption` 功能，则该分区将会被加密。
+
+    .. note::
 
-  .. note::
+        无论是否设置 Flags 字段，当启用了 :doc:`/security/flash-encryption` 功能时，以下类型的分区将始终保持加密状态。
 
-      无论是否设置 Flags 字段，``app`` 分区都将保持加密。
+        .. list::
 
-  - 如果 Flags 字段设置为 ``readonly``，则该分区为只读分区。``readonly`` 标记仅支持除 ``ota`` 和 ``coredump`` 子类型外的 ``data`` 分区。使用该标记，防止意外写入如出厂数据分区等包含关键设备特定配置数据的分区。
+            - ``app``，
+            - ``bootloader``，
+            - ``partition_table``，
+            - type ``data`` 和 subtype ``ota``，
+            - type ``data`` 和 subtype ``nvs_keys``。
 
-  .. note::
+    - 如果 Flags 字段设置为 ``readonly``，则该分区为只读分区。``readonly`` 标记仅支持除 ``ota`` 和 ``coredump`` 子类型外的 ``data`` 分区。使用该标记，防止意外写入如出厂数据分区等包含关键设备特定配置数据的分区。
 
-      在任何写入模式下 (``w``、``w+``、``a``、``a+``、``r+``)，尝试通过 C 文件 I/O API 打开文件 (``fopen```) 的操作都将失败并返回 ``NULL``。除 ``O_RDONLY`` 外，``open`` 与任何标志一同使用都将失败并返回 ``-1``，全局变量 ``errno`` 也将设置为 ``EROFS``。上述情况同样适用于通过其他 POSIX 系统调用函数执行写入或擦除的操作。在只读分区上，以读写模式打开 NVS 的句柄将失败并返回 :c:macro:`ESP_ERR_NOT_ALLOWED` 错误代码，使用 ``esp_partition`` 或 ``spi_flash`` 等较低级别的 API 进行写入操作也将返回 :c:macro:`ESP_ERR_NOT_ALLOWED` 错误代码。
+    .. note::
+
+        在任何写入模式下 (``w``、``w+``、``a``、``a+``、``r+``)，尝试通过 C 文件 I/O API 打开文件 (``fopen``) 的操作都将失败并返回 ``NULL``。除 ``O_RDONLY`` 外，``open`` 与任何标志一同使用都将失败并返回 ``-1``，全局变量 ``errno`` 也将设置为 ``EROFS``。上述情况同样适用于通过其他 POSIX 系统调用函数执行写入或擦除的操作。在只读分区上，以读写模式打开 NVS 的句柄将失败并返回 :c:macro:`ESP_ERR_NOT_ALLOWED` 错误代码，使用 ``esp_partition`` 或 ``spi_flash`` 等较低级别的 API 进行写入操作也将返回 :c:macro:`ESP_ERR_NOT_ALLOWED` 错误代码。
 
 可以使用冒号连接不同的标记，来同时指定多个标记，如 ``encrypted:readonly``。
 
@@ -192,20 +243,26 @@ Flags 字段
 
 如果你在项目配置菜单（``idf.py menuconfig``）中设置了分区表 CSV 文件的名称，然后构建项目或执行 ``idf.py partition-table``。这时，转换将在编译过程中自动完成。
 
-手动将 CSV 文件转换为二进制文件::
+手动将 CSV 文件转换为二进制文件：
+
+.. code-block:: none
+
+    python gen_esp32part.py input_partitions.csv binary_partitions.bin
 
-   python gen_esp32part.py input_partitions.csv binary_partitions.bin
+手动将二进制文件转换为 CSV 文件：
 
-手动将二进制文件转换为 CSV 文件::
+.. code-block:: none
 
-   python gen_esp32part.py binary_partitions.bin input_partitions.csv
+    python gen_esp32part.py binary_partitions.bin input_partitions.csv
 
-在标准输出 (stdout) 上，打印二进制分区表的内容（运行  ``idf.py partition-table`` 时展示的信息摘要也是这样生成的）::
+在标准输出 (stdout) 上，打印二进制分区表的内容（运行  ``idf.py partition-table`` 时展示的信息摘要也是这样生成的）：
 
-   python gen_esp32part.py binary_partitions.bin
+.. code-block:: none
+
+    python gen_esp32part.py binary_partitions.bin
 
 分区大小检查
----------------------
+------------
 
 ESP-IDF 构建系统将自动检查生成的二进制文件大小与可用的分区大小是否匹配，如果二进制文件太大，则会构建失败并报错。
 
@@ -216,7 +273,7 @@ ESP-IDF 构建系统将自动检查生成的二进制文件大小与可用的分
 
 .. note::
 
-   即使分区大小检查返回错误并导致构建失败，仍然会生成可以烧录的二进制文件（它们对于可用空间来说过大，因此无法正常工作）。
+    即使分区大小检查返回错误并导致构建失败，仍然会生成可以烧录的二进制文件（它们对于可用空间来说过大，因此无法正常工作）。
 
 MD5 校验和
 ~~~~~~~~~~
@@ -225,7 +282,7 @@ MD5 校验和
 
 .. only:: esp32
 
-   用户可通过 ``gen_esp32part.py`` 的 ``--disable-md5sum`` 选项或者 :ref:`CONFIG_PARTITION_TABLE_MD5` 选项关闭 MD5 校验。对于 :ref:`ESP-IDF v3.1 版本前的引导加载程序 <CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS>`，因为它不支持 MD5 校验，所以无法正常启动并报错 ``invalid magic number 0xebeb``，此时用户可以使用此选项关闭 MD5 校验。
+    用户可通过 ``gen_esp32part.py`` 的 ``--disable-md5sum`` 选项或者 :ref:`CONFIG_PARTITION_TABLE_MD5` 选项关闭 MD5 校验。对于 :ref:`ESP-IDF v3.1 版本前的引导加载程序 <CONFIG_APP_COMPATIBLE_PRE_V3_1_BOOTLOADERS>`，因为它不支持 MD5 校验，所以无法正常启动并报错 ``invalid magic number 0xebeb``，此时用户可以使用此选项关闭 MD5 校验。
 
 .. only:: not esp32
 
@@ -235,67 +292,67 @@ MD5 校验和
 烧写分区表
 ----------
 
--  ``idf.py partition-table-flash`` ：使用 esptool.py 工具烧写分区表。
--  ``idf.py flash`` ：会烧写所有内容，包括分区表。
+* ``idf.py partition-table-flash`` ：使用 esptool.py 工具烧写分区表。
+* ``idf.py flash`` ：会烧写所有内容，包括分区表。
 
 在执行 ``idf.py partition-table`` 命令时，手动烧写分区表的命令也将打印在终端上。
 
 .. note::
 
-   分区表的更新并不会擦除根据旧分区表存储的数据。此时，可以使用 ``idf.py erase-flash`` 命令或者 ``esptool.py erase_flash`` 命令来擦除 flash 中的所有内容。
+    分区表的更新并不会擦除根据旧分区表存储的数据。此时，可以使用 ``idf.py erase-flash`` 命令或者 ``esptool.py erase_flash`` 命令来擦除 flash 中的所有内容。
 
 
 分区工具 (``parttool.py``)
----------------------------
+--------------------------
 
 `partition_table` 组件中有分区工具 :component_file:`parttool.py<partition_table/parttool.py>`，可以在目标设备上完成分区相关操作。该工具有如下用途：
 
-  - 读取分区，将内容存储到文件中 (read_partition)
-  - 将文件中的内容写至分区 (write_partition)
-  - 擦除分区 (erase_partition)
-  - 检索特定分区的名称、偏移、大小和 flag（“加密”）标志等信息 (get_partition_info)
+    - 读取分区，将内容存储到文件中 (read_partition)
+    - 将文件中的内容写至分区 (write_partition)
+    - 擦除分区 (erase_partition)
+    - 检索特定分区的名称、偏移、大小和 flag（“加密”）标志等信息 (get_partition_info)
 
 用户若想通过编程方式完成相关操作，可从另一个 Python 脚本导入并使用分区工具，或者从 Shell 脚本调用分区工具。前者可使用工具的 Python API，后者可使用命令行界面。
 
 Python API
-~~~~~~~~~~~
+~~~~~~~~~~
 
 首先请确保已导入 `parttool` 模块。
 
 .. code-block:: python
 
-  import sys
-  import os
+    import sys
+    import os
 
-  idf_path = os.environ["IDF_PATH"]  # 从环境中获取 IDF_PATH 的值
-  parttool_dir = os.path.join(idf_path, "components", "partition_table")  # parttool.py 位于 $IDF_PATH/components/partition_table 下
+    idf_path = os.environ["IDF_PATH"]  # 从环境中获取 IDF_PATH 的值
+    parttool_dir = os.path.join(idf_path, "components", "partition_table")  # parttool.py 位于 $IDF_PATH/components/partition_table 下
 
-  sys.path.append(parttool_dir)  # 使能 Python 寻找 parttool 模块
-  from parttool import *  # 导入 parttool 模块内的所有名称
+    sys.path.append(parttool_dir)  # 使能 Python 寻找 parttool 模块
+    from parttool import *  # 导入 parttool 模块内的所有名称
 
 要使用分区工具的 Python API，第一步是创建 `ParttoolTarget`：
 
 .. code-block:: python
 
-  # 创建 parttool.py 的目标设备，并将目标设备连接到串行端口 /dev/ttyUSB1
-  target = ParttoolTarget("/dev/ttyUSB1")
+    # 创建 parttool.py 的目标设备，并将目标设备连接到串行端口 /dev/ttyUSB1
+    target = ParttoolTarget("/dev/ttyUSB1")
 
 现在，可使用创建的 `ParttoolTarget` 在目标设备上完成操作：
 
 .. code-block:: python
 
-  # 擦除名为 'storage' 的分区
-  target.erase_partition(PartitionName("storage"))
+    # 擦除名为 'storage' 的分区
+    target.erase_partition(PartitionName("storage"))
 
-  # 读取类型为 'data'、子类型为 'spiffs' 的分区，保存至文件 'spiffs.bin'
-  target.read_partition(PartitionType("data", "spiffs"), "spiffs.bin")
+    # 读取类型为 'data'、子类型为 'spiffs' 的分区，保存至文件 'spiffs.bin'
+    target.read_partition(PartitionType("data", "spiffs"), "spiffs.bin")
 
-  # 将 'factory.bin' 文件的内容写至 'factory' 分区
-  target.write_partition(PartitionName("factory"), "factory.bin")
+    # 将 'factory.bin' 文件的内容写至 'factory' 分区
+    target.write_partition(PartitionName("factory"), "factory.bin")
 
-  # 打印默认启动分区的大小
-  storage = target.get_partition_info(PARTITION_BOOT_DEFAULT)
-  print(storage.size)
+    # 打印默认启动分区的大小
+    storage = target.get_partition_info(PARTITION_BOOT_DEFAULT)
+    print(storage.size)
 
 使用 `PartitionName`、`PartitionType` 或 PARTITION_BOOT_DEFAULT 指定要操作的分区。顾名思义，这三个参数可以指向拥有特定名称的分区、特定类型和子类型的分区或默认启动分区。
 
@@ -308,44 +365,45 @@ Python API
 
 .. code-block:: bash
 
-  parttool.py [command-args] [subcommand] [subcommand-args]
+    parttool.py [command-args] [subcommand] [subcommand-args]
 
-  - command-args - 执行主命令 (parttool.py) 所需的实际参数，多与目标设备有关
-  - subcommand - 要执行的操作
-  - subcommand-args - 所选操作的实际参数
+    - command-args - 执行主命令 (parttool.py) 所需的实际参数，多与目标设备有关
+    - subcommand - 要执行的操作
+    - subcommand-args - 所选操作的实际参数
 
 .. code-block:: bash
 
-  # 擦除名为 'storage' 的分区
-  parttool.py --port "/dev/ttyUSB1" erase_partition --partition-name=storage
+    # 擦除名为 'storage' 的分区
+    parttool.py --port "/dev/ttyUSB1" erase_partition --partition-name=storage
 
-  # 读取类型为 'data'、子类型为 'spiffs' 的分区，保存到 'spiffs.bin' 文件
-  parttool.py --port "/dev/ttyUSB1" read_partition --partition-type=data --partition-subtype=spiffs --output "spiffs.bin"
+    # 读取类型为 'data'、子类型为 'spiffs' 的分区，保存到 'spiffs.bin' 文件
+    parttool.py --port "/dev/ttyUSB1" read_partition --partition-type=data --partition-subtype=spiffs --output "spiffs.bin"
 
-  # 将 'factory.bin' 文件中的内容写入到 'factory' 分区
-  parttool.py --port "/dev/ttyUSB1" write_partition --partition-name=factory --input "factory.bin"
+    # 将 'factory.bin' 文件中的内容写入到 'factory' 分区
+    parttool.py --port "/dev/ttyUSB1" write_partition --partition-name=factory --input "factory.bin"
 
-  # 打印默认启动分区的大小
-  parttool.py --port "/dev/ttyUSB1" get_partition_info --partition-boot-default --info size
+    # 打印默认启动分区的大小
+    parttool.py --port "/dev/ttyUSB1" get_partition_info --partition-boot-default --info size
 
 .. note::
-  如果设备启用了 ``Flash Encryption`` 或 ``Secure Boot``，尝试使用修改 flash 内容的命令（如 ``erase_partition`` 或 ``write_partition``）会导致错误。这是因为 ``esptool.py`` 的擦除命令会在写入之前先被调用。这个“错误”实际上是一个用来防止设备变砖的安全措施。
 
-  ::
+    如果设备启用了 ``Flash Encryption`` 或 ``Secure Boot``，尝试使用修改 flash 内容的命令（如 ``erase_partition`` 或 ``write_partition``）会导致错误。这是因为 ``esptool.py`` 的擦除命令会在写入之前先被调用。这个“错误”实际上是一个用来防止设备变砖的安全措施。
 
-    A fatal error occurred: Active security features detected, erasing flash is disabled as a safety measure. Use --force to override, please use with caution, otherwise it may brick your device!
+    .. code-block:: none
 
-  要解决此问题，需在运行 ``esptool.py`` 时使用 ``--force`` 参数。具体而言，``parttool.py`` 提供了 ``--esptool-erase-args`` 参数，用来将 ``--force`` 参数传递给 ``esptool.py``。
+        A fatal error occurred: Active security features detected, erasing flash is disabled as a safety measure. Use --force to override, please use with caution, otherwise it may brick your device!
 
-  .. code-block:: bash
+    要解决此问题，需在运行 ``esptool.py`` 时使用 ``--force`` 参数。具体而言，``parttool.py`` 提供了 ``--esptool-erase-args`` 参数，用来将 ``--force`` 参数传递给 ``esptool.py``。
 
-    # 擦除名为 'storage' 的分区
-    # 如果启用了 Flash Encryption 或 Secure Boot，则添加 "--esptool-erase-args=force"
-    parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force erase_partition --partition-name=storage
+    .. code-block:: bash
+
+        # 擦除名为 'storage' 的分区
+        # 如果启用了 Flash Encryption 或 Secure Boot，则添加 "--esptool-erase-args=force"
+        parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force erase_partition --partition-name=storage
 
-    # 将名为 'factory.bin' 的文件内容写入 'factory' 分区
-    # 如果启用了 Flash Encryption 或 Secure Boot，则添加 "--esptool-erase-args=force"
-    parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force write_partition --partition-name=factory --input "factory.bin"
+        # 将名为 'factory.bin' 的文件内容写入 'factory' 分区
+        # 如果启用了 Flash Encryption 或 Secure Boot，则添加 "--esptool-erase-args=force"
+        parttool.py --port "/dev/ttyUSB1" --esptool-erase-args=force write_partition --partition-name=factory --input "factory.bin"
 
 更多信息可用 `--help` 指令查看：
 
diff --git a/docs/zh_CN/api-guides/performance/ram-usage.rst b/docs/zh_CN/api-guides/performance/ram-usage.rst
index 44839f698ee..2e8295c49c0 100644
--- a/docs/zh_CN/api-guides/performance/ram-usage.rst
+++ b/docs/zh_CN/api-guides/performance/ram-usage.rst
@@ -198,9 +198,9 @@ IRAM 优化
    将 SRAM1 用于 IRAM
    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-   SRAM1 内存区域通常用于 DRAM 存储，但可以设置 :ref:`CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM` 选项，将其中一部分用作 IRAM 存储。引入该选项前，这个内存区域通常预留给 DRAM 数据使用（如 ``.bss`` ），随后由软件引导加载程序加入到堆中。引入该选项后，引导加载程序的 DRAM 大小会减少到更接近实际需要的值。
+   SRAM1 内存区域通常用于 DRAM 存储，但可以设置 :ref:`CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM` 选项，将其中一部分用作 IRAM 存储。引入该选项前，这个内存区域通常预留给 DRAM 数据使用（如 ``.bss``），随后由二级引导加载程序加入到堆中。引入该选项后，二级引导加载程序的 DRAM 大小会减少到更接近实际需要的值。
 
-   要使用以上选项，ESP-IDF 应能够将新的 SRAM1 区域识别为有效镜像段的加载地址。部分应用程序的代码置于新扩展的 IRAM 区域，如果软件引导加载程序在引入该选项前编译，将无法加载这类应用程序。这类情况通常在进行 OTA 更新时发生，此时仅会更新应用程序。
+   要使用以上选项，ESP-IDF 应能够将新的 SRAM1 区域识别为有效镜像段的加载地址。部分应用程序的代码置于新扩展的 IRAM 区域，如果二级引导加载程序在引入该选项前编译，将无法加载这类应用程序。这类情况通常在进行 OTA 更新时发生，此时仅会更新应用程序。
 
    如果 IRAM 段放置在无效区域，在启动过程中将检测到以下问题，并导致启动失败：
 
@@ -210,7 +210,7 @@ IRAM 优化
 
    .. warning::
 
-      若与在引入以上配置选项前编译的软件引导加载程序一同使用，使用 :ref:`CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM` 选项编译的应用程序很可能无法启动。若使用旧版本的引导加载程序，并进行 OTA 更新，请在提交任何更新前仔细测试。
+      若与在引入以上配置选项前编译的二级引导加载程序一同使用，使用 :ref:`CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM` 选项编译的应用程序很可能无法启动。若使用旧版本的引导加载程序，并进行 OTA 更新，请在提交任何更新前仔细测试。
 
    任何最终未用于静态 IRAM 的内存都将添加到堆内存中。
 
diff --git a/docs/zh_CN/api-guides/performance/size.rst b/docs/zh_CN/api-guides/performance/size.rst
index 1a9545e7dcf..3d52af653e5 100644
--- a/docs/zh_CN/api-guides/performance/size.rst
+++ b/docs/zh_CN/api-guides/performance/size.rst
@@ -194,6 +194,7 @@ MbedTLS 功能
 - :ref:`CONFIG_MBEDTLS_HAVE_TIME`
 - :ref:`CONFIG_MBEDTLS_ECDSA_DETERMINISTIC`
 - :ref:`CONFIG_MBEDTLS_SHA512_C`
+- :ref:`CONFIG_MBEDTLS_SHA3_C`
 - :ref:`CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS`
 - :ref:`CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS`
 - :ref:`CONFIG_MBEDTLS_SSL_CONTEXT_SERIALIZATION`
@@ -260,7 +261,7 @@ MbedTLS 功能
 
 本文档仅涉及 ESP-IDF 应用程序的二进制文件大小，而不涉及 ESP-IDF :ref:`second-stage-bootloader`。
 
-关于 ESP-IDF 引导加载程序二进制文件大小的讨论，参阅 :ref:`bootloader-size`。
+关于 ESP-IDF 引导加载程序二进制文件大小的讨论，请参阅 :ref:`bootloader-size`。
 
 IRAM 二进制文件大小
 ------------------------------------
diff --git a/docs/zh_CN/api-guides/performance/speed.rst b/docs/zh_CN/api-guides/performance/speed.rst
index 25601b4dadf..54dc7465d6f 100644
--- a/docs/zh_CN/api-guides/performance/speed.rst
+++ b/docs/zh_CN/api-guides/performance/speed.rst
@@ -301,9 +301,9 @@ ESP-IDF 支持动态 :doc:`/api-reference/system/intr_alloc` 和中断抢占。
 
 使用标准 C 库函数，如 ``fread`` 和 ``fwrite``，相较于使用平台特定的不带缓冲系统调用，如 ``read`` 和 ``write``，可能会导致 I/O 性能下降。
 
-``fread`` 与 ``fwrite`` 函数是为可移植性而设计的，而非速度，其缓冲性质会引入一些额外的开销。关于如何使用这两个函数，请参考示例 :example:`storage/fatfsgen`。
+``fread`` 与 ``fwrite`` 函数是为可移植性而设计的，而非速度，其缓冲性质会引入一些额外的开销。关于如何使用这两个函数，请参考示例 :example:`storage/fatfs/getting_started`。
 
-与之相比，``read`` 与 ``write`` 函数是标准的 POSIX API，可直接通过 VFS 处理 FatFs，由 ESP-IDF 负责底层实现。关于如何使用这两个函数，请参考示例 :example:`storage/perf_benchmark`。
+与之相比，``read`` 与 ``write`` 函数是标准的 POSIX API，可直接通过 VFS 处理 FatFs，由 ESP-IDF 负责底层实现。关于如何使用这两个函数，请参考示例 :example:`storage/fatfs/fs_operations`。
 
 下面提供了一些提示，更多信息请见 :doc:`/api-reference/storage/fatfs`。
 
@@ -314,4 +314,5 @@ ESP-IDF 支持动态 :doc:`/api-reference/system/intr_alloc` 和中断抢占。
     - 要提高诸如 ``fread`` 和 ``fgets`` 等缓冲读取函数的执行速度，可以增加文件缓冲区的大小。Newlib 的默认值为 128 字节，但可将其增加到 4096、8192 或 16384 字节。为此，可以使用 ``setvbuf`` 函数对特定文件指针进行局部设置，或者通过修改 :ref:`CONFIG_FATFS_VFS_FSTAT_BLKSIZE` 设置来进行全局修改。
 
         .. note::
+
             增加缓冲区的大小会增加堆内存的使用量。
diff --git a/docs/zh_CN/api-guides/startup.rst b/docs/zh_CN/api-guides/startup.rst
index b51c2d2a4f4..2f7dcc06031 100644
--- a/docs/zh_CN/api-guides/startup.rst
+++ b/docs/zh_CN/api-guides/startup.rst
@@ -9,7 +9,7 @@
 
 .. list::
 
-   1. :ref:`first-stage-bootloader` 被固化在了 {IDF_TARGET_NAME} 内部的 ROM 中，它会从 flash 的  {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载二级引导程序至 RAM (IRAM & DRAM) 中。
+   1. :ref:`first-stage-bootloader` 被固化在了 {IDF_TARGET_NAME} 内部的 ROM 中，它会从 flash 的  {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载二级引导加载程序至 RAM (IRAM & DRAM) 中。
 
    2. :ref:`second-stage-bootloader` 从 flash 中加载分区表和主程序镜像至内存中，主程序中包含了 RAM 段和通过 flash 高速缓存映射的只读段。
 
@@ -21,8 +21,8 @@
 
 .. _first-stage-bootloader:
 
-一级引导程序
-~~~~~~~~~~~~
+一级 (ROM) 引导加载程序
+~~~~~~~~~~~~~~~~~~~~~~~
 
 .. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES
 
@@ -48,45 +48,45 @@
 
 .. only:: esp32
 
-    二级引导程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。如果正在使用 :doc:`/security/secure-boot-v1`，则 flash 的第一个 4 kB 扇区用于存储安全启动 IV 以及引导程序镜像的摘要，否则不使用该扇区。
+    二级引导加载程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。如果正在使用 :doc:`/security/secure-boot-v1`，则 flash 的第一个 4 kB 扇区用于存储安全启动 IV 以及引导加载程序镜像的摘要，否则不使用该扇区。
 
 .. only:: esp32s2
 
-    二级引导程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。该地址前面的 flash 4 kB 扇区未使用。
+    二级引导加载程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。该地址前面的 flash 4 kB 扇区未使用。
 
 .. only:: SOC_KEY_MANAGER_SUPPORTED
 
-    二级引导程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。该地址前面的 flash 8 kB 扇区将为密钥管理器保留，用于与 flash 加密 (AES-XTS) 相关的操作。
+    二级引导加载程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。该地址前面的 flash 8 kB 扇区将为密钥管理器保留，用于与 flash 加密 (AES-XTS) 相关的操作。
 
  .. only:: not (esp32 or esp32s2 or SOC_KEY_MANAGER_SUPPORTED)
 
-    二级引导程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。
+    二级引导加载程序二进制镜像会从 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处加载。
 
 .. TODO: describe application binary image format, describe optional flash configuration commands.
 
 .. _second-stage-bootloader:
 
-二级引导程序
-~~~~~~~~~~~~
+二级引导加载程序
+~~~~~~~~~~~~~~~~
 
-在 ESP-IDF 中，存放在 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处的二进制镜像就是二级引导程序。二级引导程序的源码可以在 ESP-IDF 的 :idf:`components/bootloader` 目录下找到。ESP-IDF 使用二级引导程序可以增加 flash 分区的灵活性（使用分区表），并且方便实现 flash 加密，安全引导和空中升级 (OTA) 等功能。
+在 ESP-IDF 中，存放在 flash 的 {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} 偏移地址处的二进制镜像就是二级引导加载程序。二级引导加载程序的源码可以在 ESP-IDF 的 :idf:`components/bootloader` 目录下找到。ESP-IDF 使用二级引导加载程序可以增加 flash 分区的灵活性（使用分区表），并且方便实现 flash 加密，安全引导和空中升级 (OTA) 等功能。
 
-当一级引导程序校验并加载完二级引导程序后，它会从二进制镜像的头部找到二级引导程序的入口点，并跳转过去运行。
+当一级 (ROM) 引导加载程序校验并加载完二级引导加载程序后，它会从二进制镜像的头部找到二级引导加载程序的入口点，并跳转过去运行。
 
-二级引导程序默认从 flash 的 {IDF_TARGET_CONFIG_PARTITION_TABLE_OFFSET} 偏移地址处（:ref:`可配置的值 <CONFIG_PARTITION_TABLE_OFFSET>`）读取分区表。请参考 :doc:`分区表 <partition-tables>` 获取详细信息。引导程序会寻找工厂分区和 OTA 应用程序分区。如果在分区表中找到了 OTA 应用程序分区，引导程序将查询 ``otadata`` 分区以确定应引导哪个分区。更多信息请参考 :doc:`/api-reference/system/ota`。
+二级引导加载程序默认从 flash 的 {IDF_TARGET_CONFIG_PARTITION_TABLE_OFFSET} 偏移地址处（:ref:`可配置的值 <CONFIG_PARTITION_TABLE_OFFSET>`）读取分区表。请参考 :doc:`分区表 <partition-tables>` 获取详细信息。引导加载程序会寻找工厂分区和 OTA 应用程序分区。如果在分区表中找到了 OTA 应用程序分区，引导加载程序将查询 ``otadata`` 分区以确定应引导哪个分区。更多信息请参考 :doc:`/api-reference/system/ota`。
 
-关于 ESP-IDF 引导程序可用的配置选项，请参考 :doc:`bootloader`。
+关于 ESP-IDF 引导加载程序可用的配置选项，请参考 :doc:`bootloader`。
 
-对于选定的分区，二级引导程序将从 flash 逐段读取二进制镜像：
+对于选定的分区，二级引导加载程序将从 flash 逐段读取二进制镜像：
 
 - 对于在内部 :ref:`iram` 或 :ref:`dram` 中具有加载地址的段，将把数据从 flash 复制到它们的加载地址处。
 - 对于一些加载地址位于 :ref:`drom` 或 :ref:`irom` 区域的段，通过配置 flash MMU，可为从 flash 到加载地址提供正确的映射。
 
 .. only:: esp32
 
-    请注意，二级引导程序同时为 PRO CPU 和 APP CPU 配置 flash MMU，但仅使能 PRO CPU 的 flash MMU。原因是二级引导程序代码已加载到 APP CPU 的高速缓存使用的内存区域中。因此使能 APP CPU 高速缓存的任务就交给了应用程序。
+    请注意，二级引导加载程序同时为 PRO CPU 和 APP CPU 配置 flash MMU，但仅使能 PRO CPU 的 flash MMU。原因是二级引导加载程序代码已加载到 APP CPU 的高速缓存使用的内存区域中。因此使能 APP CPU 高速缓存的任务就交给了应用程序。
 
-一旦处理完所有段（即加载了代码并设置了 flash MMU），二级引导程序将验证应用程序的完整性，并从二进制镜像文件的头部寻找入口地址，然后跳转到该地址处运行。
+一旦处理完所有段（即加载了代码并设置了 flash MMU），二级引导加载程序将验证应用程序的完整性，并从二进制镜像文件的头部寻找入口地址，然后跳转到该地址处运行。
 
 .. _application-startup:
 
@@ -108,7 +108,7 @@
 
 ESP-IDF 应用程序的入口是 :idf_file:`components/esp_system/port/cpu_start.c` 文件中的 ``call_start_cpu0`` 函数。这个函数由二级引导加载程序执行，并且从不返回。
 
-该端口层的初始化功能会初始化基本的 C 运行环境 ("CRT"），并对 SoC 的内部硬件进行了初始配置。
+该端口层的初始化功能会初始化基本的 C 运行环境 ("CRT")，并对 SoC 的内部硬件进行了初始配置。
 
 .. list::
 
@@ -119,7 +119,7 @@ ESP-IDF 应用程序的入口是 :idf_file:`components/esp_system/port/cpu_start
    :SOC_SPIRAM_SUPPORTED: - 如果配置了 PSRAM，则使能 PSRAM。
    - 将 CPU 时钟设置为项目配置的频率。
    :SOC_MEMPROT_SUPPORTED: - 如果配置了内存保护，则初始化内存保护。
-   :esp32: - 根据应用程序头部设置重新配置主 SPI flash，这是为了与 ESP-IDF V4.0 之前的引导程序版本兼容，请参考 :ref:`bootloader-compatibility`。
+   :esp32: - 根据应用程序头部设置重新配置主 SPI flash，这是为了与 ESP-IDF V4.0 之前的引导加载程序版本兼容，请参考 :ref:`bootloader-compatibility`。
    :SOC_HP_CPU_HAS_MULTIPLE_CORES: - 如果应用程序被配置为在多个内核上运行，则启动另一个内核并等待其初始化（在类似的“端口层”初始化函数 ``call_start_cpu1`` 内）。
 
 .. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES
diff --git a/docs/zh_CN/api-guides/tools/idf-docker-image.rst b/docs/zh_CN/api-guides/tools/idf-docker-image.rst
index d771d0253f0..36412976215 100644
--- a/docs/zh_CN/api-guides/tools/idf-docker-image.rst
+++ b/docs/zh_CN/api-guides/tools/idf-docker-image.rst
@@ -14,7 +14,7 @@ IDF Docker 镜像 (``espressif/idf``) 为使用特定版本的 ESP-IDF 自动化
 该镜像包含以下内容：
 
 - 常见的实用工具，如 ``git``、``wget``、``curl`` 和 ``zip``。
-- Python 3.8 或更高版本。
+- Python 3.9 或更高版本。
 - 特定版本 ESP-IDF 的副本。有关版本信息，请参阅下文。该副本中设置了 ``IDF_PATH`` 环境变量，并指向容器中 ESP-IDF 的位置。
 - 构建特定版本 ESP-IDF 所需工具：CMake、Ninja、交叉编译器工具链等。
 - ESP-IDF 需要的所有 Python 软件包。这些软件包均已安装在虚拟环境中。
diff --git a/docs/zh_CN/api-guides/tools/idf-monitor.rst b/docs/zh_CN/api-guides/tools/idf-monitor.rst
index 7e38c5a187c..8c186f6539f 100644
--- a/docs/zh_CN/api-guides/tools/idf-monitor.rst
+++ b/docs/zh_CN/api-guides/tools/idf-monitor.rst
@@ -252,63 +252,7 @@ IDF 监视器的默认复位序列可在大多数环境中使用。使用默认
 
 对于高级用户或特定用例，IDF 监视器支持使用 :ref:`configuration-file` 配置自定义复位序列。这在默认序列可能不足的极端情况下特别有用。
 
-复位序列可通过以下格式的字符串定义：
-
-- 各个命令由 ``|`` 分隔（例如 ``R0|D1|W0.5``）。
-- 命令（例如 ``R0``）由代码（``R``）和参数（``0``）定义。
-
-.. list-table::
-    :header-rows: 1
-    :widths: 15 50 35
-    :align: center
-
-    * - 代码
-      - 操作
-      - 参数
-    * - D
-      - 设置 DTR 控制线
-      - ``1``/``0``
-    * - R
-      - 设置 RTS 控制线
-      - ``1``/``0``
-    * - U
-      - 同时设置 DTR 和 RTS 控制线（仅适用于类 Unix 系统）
-      - ``0,0``/``0,1``/``1,0``/``1,1``
-    * - W
-      - 等待 ``N`` 秒（其中 ``N`` 为浮点数）
-      - N
-
-示例：
-
-.. code-block:: ini
-
-    [esp-idf-monitor]
-    custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0
-
-有关更多详细信息，请参阅 Esptool 文档中 `custom reset sequence`_ 章节。请注意，IDF 监视器只使用了 Esptool 配置中的 ``custom_reset_sequence`` 值，其他值会被 IDF 监视器忽略。
-
-IDF 监视器和 Esptool 之间共享配置
-----------------------------------------------
-
-自定义复位序列的配置可以在 IDF 监视器和 Esptool 之间的共享配置文件中指定。在这种情况下，为了使两个工具都能识别配置文件，其名称应为 ``setup.cfg`` 或 ``tox.ini``。
-
-共享配置文件的示例：
-
-.. code-block:: ini
-
-    [esp-idf-monitor]
-    menu_key = T
-    skip_menu_key = True
-
-    [esptool]
-    custom_reset_sequence = U0,1|W0.1|D1|R0|W0.5|D0
-
-.. note::
-
-    当在 ``[esp-idf-monitor]`` 部分和 ``[esptool]`` 部分都使用 ``custom_reset_sequence`` 参数时，IDF 监视器会优先使用 ``[esp-idf-monitor]`` 部分的配置。``[esptool]`` 部分中任何与之冲突的配置都将被忽略。
-
-    当配置分散在多个文件中时，此优先规则也适用。全局 esp-idf-monitor 配置将优先于本地 esptool 配置。
-
+如需使用自定义复位序列，请参阅 `IDF 监视器文档`_ 获取更多详细信息。
 
 配置 GDBStub 以启用 GDB
 ~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -397,118 +341,16 @@ GDBStub 支持在运行时进行调试。GDBStub 在目标上运行，并通过
 配置文件
 ========
 
-``esp-idf-monitor`` 使用 `C0 控制字符`_ 与控制台进行交互。配置文件中的字符会被转换为对应的 C0 控制代码。可用字符包括英文字母 (A-Z) 和特殊符号：``[``、``]``、``\``、``^``、和 ``_``.
-
-.. warning::
-
-    注意，一些字符可能无法在所有平台通用，或被保留作为其他用途的快捷键。请谨慎使用此功能。
-
-
-文件位置
-~~~~~~~~~~
-
-配置文件的默认名称为 ``esp-idf-monitor.cfg``。首先，在 ``esp-idf-monitor`` 路径中检测配置文件并运行。
-
-如果此目录中没有检测到配置文件，则检查当前用户操作系统的配置目录：
-
-  - Linux: ``/home/<user>/.config/esp-idf-monitor/``
-  - MacOS ``/Users/<user>/.config/esp-idf-monitor/``
-  - Windows: ``c:\Users\<user>\AppData\Local\esp-idf-monitor\``
+``esp-idf-monitor`` 支持通过配置文件更改其默认行为。该配置文件可用于设置自定义快捷键，或设置自定义复位序列以重置芯片进入引导加载程序。
 
-如仍未检测到配置文件，会最后再检查主目录：
-
-  - Linux: ``/home/<user>/``
-  - MacOS ``/Users/<user>/``
-  - Windows: ``c:\Users\<user>\``
-
-在 Windows 中，可以使用 ``HOME`` 或 ``USERPROFILE`` 环境变量设置主目录，因此，Windows 配置目录的位置也取决于这些变量。
-
-还可以使用 ``ESP_IDF_MONITOR_CFGFILE`` 环境变量为配置文件指定一个不同的位置，例如 ``ESP_IDF_MONITOR_CFGFILE = ~/custom_config.cfg``。这一设置的检测优先级高于上述所有位置检测的优先级。
-
-如果没有使用其他配置文件，``esp-idf-monitor`` 会从其他常用的配置文件中读取设置。如果存在 ``setup.cfg`` 或 ``tox.ini`` 文件，``esp-idf-monitor`` 会自动从这些文件中读取设置。
-
-配置选项
-~~~~~~~~~~
-
-下表列出了可用的配置选项：
-
-.. list-table::
-    :header-rows: 1
-    :widths: 30 50 20
-    :align: center
-
-    * - 选项名称
-      - 描述
-      - 默认值
-    * - menu_key
-      - 访问主菜单
-      - ``T``
-    * - exit_key
-      - 退出监视器
-      - ``]``
-    * - chip_reset_key
-      - 初始化芯片重置
-      - ``R``
-    * - recompile_upload_key
-      - 重新编译并上传
-      - ``F``
-    * - recompile_upload_app_key
-      - 仅重新编译并上传应用程序
-      - ``A``
-    * - toggle_output_key
-      - 切换输出显示
-      - ``Y``
-    * - toggle_log_key
-      - 切换日志功能
-      - ``L``
-    * - toggle_timestamp_key
-      - 切换时间戳显示
-      - ``I``
-    * - chip_reset_bootloader_key
-      - 将芯片重置为引导加载模式
-      - ``P``
-    * - exit_menu_key
-      - 从菜单中退出监视器
-      - ``X``
-    * - skip_menu_key
-      - 设置使用菜单命令时无需按下主菜单键
-      - ``False``
-    * - custom_reset_sequence
-      - 复位目标到引导加载程序的自定义复位序列
-      - 无默认值
-
-
-语法
-~~~~
-
-配置文件为 .ini 文件格式，必须以 ``[esp-idf-monitor]`` 标头引入才能被识别为有效文件。以下语法以“配置名称 = 配置值”形式列出。以 ``#`` 或 ``;`` 开头的行是注释，将被忽略。
-
-.. code-block:: ini
-
-    # esp-idf-monitor.cfg file to configure internal settings of esp-idf-monitor
-    [esp-idf-monitor]
-    menu_key = T
-    exit_key = ]
-    chip_reset_key = R
-    recompile_upload_key = F
-    recompile_upload_app_key = A
-    toggle_output_key = Y
-    toggle_log_key = L
-    toggle_timestamp_key = I
-    chip_reset_bootloader_key = P
-    exit_menu_key = X
-    skip_menu_key = False
+有关配置文件的更多详细信息，请参阅 `IDF 监视器文档`_。
 
 
 IDF 监视器已知问题
 =================================
 
-如果在使用 IDF 监视器过程中遇到任何问题，请查看我们的 `GitHub 仓库 <https://github.com/espressif/esp-idf-monitor/issues>`_ 以获取已知问题列表及其当前状态。如果遇到的问题没有相关记录，请创建一个新的问题报告。
+如果在使用 IDF 监视器过程中遇到任何问题，请查看 `GitHub 仓库 <https://github.com/espressif/esp-idf-monitor/issues>`_ 以获取已知问题列表及其当前状态。如果遇到的问题没有相关记录，请创建一个新的问题报告。
 
-.. _addr2line: https://sourceware.org/binutils/docs/binutils/addr2line.html
 .. _esp-idf-monitor: https://github.com/espressif/esp-idf-monitor
+.. _IDF 监视器文档: https://github.com/espressif/esp-idf-monitor/blob/v1.5.0/README.md#documentation
 .. _gdb: https://sourceware.org/gdb/download/onlinedocs/
-.. _pySerial: https://github.com/pyserial/pyserial
-.. _miniterm: https://pyserial.readthedocs.org/en/latest/tools.html#module-serial.tools.miniterm
-.. _C0 控制字符: https://zh.wikipedia.org/wiki/C0%E4%B8%8EC1%E6%8E%A7%E5%88%B6%E5%AD%97%E7%AC%A6#C0_(ASCII%E5%8F%8A%E5%85%B6%E6%B4%BE%E7%94%9F)
-.. _custom reset sequence: https://docs.espressif.com/projects/esptool/en/latest/{IDF_TARGET_PATH_NAME}/esptool/configuration-file.html#custom-reset-sequence
diff --git a/docs/zh_CN/api-guides/tools/idf-py.rst b/docs/zh_CN/api-guides/tools/idf-py.rst
index b281e3531f1..deab7632059 100644
--- a/docs/zh_CN/api-guides/tools/idf-py.rst
+++ b/docs/zh_CN/api-guides/tools/idf-py.rst
@@ -250,7 +250,7 @@ uf2 二进制文件也可以通过 :ref:`idf.py uf2 <generate-uf2-binary>` 生
 
 在 ESP 芯片上运行 `ESP USB Bridge <https://github.com/espressif/esp-usb-bridge>`_ 项目将创建一个 USB 大容量存储设备，用户可以将生成的 UF2 文件复制到该 USB 设备中，桥接 MCU 将使用该文件来烧录目标 MCU。这一操作十分简单，只需将文件复制（或“拖放”）到文件资源管理器访问的公开磁盘中即可。
 
-如需仅为应用程序生成 UF2 二进制文件，即不包含加载引导程序和分区表，请使用 ``uf2-app`` 命令。
+如需仅为应用程序生成 UF2 二进制文件，即不包含引导加载程序和分区表，请使用 ``uf2-app`` 命令。
 
 ``idf.py uf2`` 命令在功能上与 :ref:`上述 <merging-binaries>` ``idf.py merge-bin -f uf2`` 命令等效。而将二进制文件合并为除 uf2 以外的各种格式时，``idf.py merge-bin`` 命令更具灵活性和可选性。
 
diff --git a/docs/zh_CN/api-guides/tools/index.rst b/docs/zh_CN/api-guides/tools/index.rst
index 44916de2606..e6b4d2158fc 100644
--- a/docs/zh_CN/api-guides/tools/index.rst
+++ b/docs/zh_CN/api-guides/tools/index.rst
@@ -12,4 +12,4 @@
    idf-clang-tidy
    idf-tools
    idf-size
-   :esp32 or esp32c3: qemu
+   :TARGET_SUPPORT_QEMU: qemu
diff --git a/docs/zh_CN/api-guides/tools/qemu.rst b/docs/zh_CN/api-guides/tools/qemu.rst
index 14f962dbcfe..3d4465f7005 100644
--- a/docs/zh_CN/api-guides/tools/qemu.rst
+++ b/docs/zh_CN/api-guides/tools/qemu.rst
@@ -1,6 +1,8 @@
 QEMU 模拟器
 ===========
 
+{IDF_TARGET_CRYPT_CNT:default="SPI_BOOT_CRYPT_CNT",esp32="FLASH_CRYPT_CNT"}
+
 :link_to_translation:`en:[English]`
 
 乐鑫维护了一个 QEMU 模拟器的 `分支 <https://github.com/espressif/qemu>`_，支持 {IDF_TARGET_NAME}。这个分支实现了对 {IDF_TARGET_NAME} 的 CPU、内存和多个外设的模拟。更多有关 {IDF_TARGET_NAME} 的 QEMU 的信息，请参阅 `QEMU README 文档 <https://github.com/espressif/esp-toolchain-docs/blob/main/qemu/README.md>`_。
@@ -119,13 +121,52 @@ QEMU 支持 eFuse 的仿真，可用来测试安全启动和 flash 加密等与
 
 使用 :doc:`idf.py<idf-py>` eFuse 相关命令来编程 eFuse。当这些命令与 ``qemu`` 命令一起运行时，eFuse 会在 QEMU 中编程，并且 ``qemu_efuse.bin`` 文件会更新。例如，
 
+.. only:: not SOC_FLASH_ENCRYPTION_XTS_AES
+
+    .. code-block:: console
+
+        idf.py qemu efuse-burn {IDF_TARGET_CRYPT_CNT} 1
+        idf.py qemu efuse-burn-key flash_encryption my_flash_encryption_key.bin
+
+.. only:: SOC_FLASH_ENCRYPTION_XTS_AES
+
+    .. code-block:: console
+
+        idf.py qemu efuse-burn {IDF_TARGET_CRYPT_CNT} 1
+        idf.py qemu efuse-burn-key BLOCK my_flash_encryption_key.bin KEYPURPOSE
+
+    有关 ``BLOCK`` 和 ``KEYPURPOSE`` 的详细信息，请参阅 :doc:`../../security/flash-encryption` 指南。
+
+如需导出 eFuse 概要，使用以下命令：
+
 .. code-block:: console
 
-    idf.py qemu efuse-burn FLASH_CRYPT_CNT 1
+    idf.py qemu efuse-summary
 
 默认情况下，eFuse 的值从编译文件夹里的 ``qemu_efuse.bin`` 文件中读取和写入。也可以使用 ``--efuse-file`` 选项指定不同的文件。例如，
 
 .. code-block:: console
 
-    idf.py qemu --efuse-file my_efuse.bin efuse-burn FLASH_CRYPT_CNT 1
+    idf.py qemu --efuse-file my_efuse.bin efuse-burn {IDF_TARGET_CRYPT_CNT} 1
     idf.py qemu --efuse-file my_efuse.bin monitor
+
+指定 flash 映像
+~~~~~~~~~~~~~~~
+
+默认情况下，QEMU 使用构建目录中的 ``qemu_flash.bin`` 文件作为 flash 映像。该文件是根据构建目录中 ``flash_args`` 文件提供的项目信息生成的。如果想使用其他 flash 映像，可通过 ``--flash-file`` 选项进行指定。例如:
+
+.. code-block:: console
+
+    idf.py qemu --flash-file my_flash.bin monitor
+
+
+所提供的 flash 映像必须满足以下要求，以确保正确模拟：
+
+- flash 文件大小与项目配置中 :ref:`CONFIG_ESPTOOLPY_FLASHSIZE` 的指定值相同。
+- flash 文件包括所有必需的二进制文件，如引导加载程序、分区表和应用程序固件，这些文件位于各自的内存偏移量处。
+
+
+模拟安全启动
+~~~~~~~~~~~~~
+
+QEMU 支持模拟安全启动 v2 机制。请保持 :ref:`CONFIG_SECURE_BOOT_FLASH_BOOTLOADER_DEFAULT` 处于启用状态，将签名的引导加载程序镜像嵌入到 QEMU 的镜像文件中。
diff --git a/docs/zh_CN/api-guides/wifi.rst b/docs/zh_CN/api-guides/wifi.rst
index e64e4e65ec4..93cce80a0fd 100644
--- a/docs/zh_CN/api-guides/wifi.rst
+++ b/docs/zh_CN/api-guides/wifi.rst
@@ -839,7 +839,7 @@ Wi-Fi 驱动程序内部扫描阶段
 +++++++++++++++++++++
 
  - s3.1：发送关联请求并使能关联计时器。
- - s3.2：如果在关联计时器超时之前未接收到关联响应，将产生 `WIFI_EVENT_STA_DISCONNECTED`_ 事件，且原因代码为 ``WIFI_REASON_ASSOC_EXPIRE``。请参阅 `Wi-Fi 原因代码`_。
+ - s3.2：如果在关联计时器超时之前未接收到关联响应，将产生 `WIFI_EVENT_STA_DISCONNECTED`_ 事件，且原因代码为 ``WIFI_REASON_DISASSOC_DUE_TO_INACTIVITY``。请参阅 `Wi-Fi 原因代码`_。
  - s3.3：接收到关联响应，且关联计时器终止。
  - s3.4：AP 在响应中拒绝关联且产生 `WIFI_EVENT_STA_DISCONNECTED`_ 事件，原因代码将在关联响应中指定。请参阅 `Wi-Fi 原因代码`_。
 
@@ -896,7 +896,7 @@ Wi-Fi 原因代码
        对于 ESP station，出现以下情况时报告该代码：
 
        - 从 AP 接收到该代码。
-   * - ASSOC_EXPIRE
+   * - DISASSOC_DUE_TO_INACTIVITY
      - 4
      - 4
      - 因为 AP 不活跃，association 取消。
@@ -922,7 +922,7 @@ Wi-Fi 原因代码
        对于 ESP AP，出现以下情况时将报告该代码：
 
        - 与 AP 相关联的 station 数量已到达 AP 可支持的最大值。
-   * - NOT_AUTHED
+   * - CLASS2_FRAME_FROM_NONAUTH_STA
      - 6
      - 6
      - 从一个未认证 station 接收到 class-2 frame。
@@ -934,7 +934,7 @@ Wi-Fi 原因代码
        对于 ESP AP，出现以下情况时将报告该代码：
 
        - AP 从一个未认证 station 接收到数据包。
-   * - NOT_ASSOCED
+   * - CLASS3_FRAME_FROM_NONASSOC_STA
      - 7
      - 7
      - 从一个未关联 station 接收到的 class-3 frame。
@@ -1199,7 +1199,7 @@ Wi-Fi 原因代码
    * - ASSOC_FAIL
      - 203
      - 保留
-     - 乐鑫特有的 Wi-Fi 原因代码： association 失败，但并非由 ASSOC_EXPIRE 或 ASSOC_TOOMANY 引发。
+     - 乐鑫特有的 Wi-Fi 原因代码： association 失败，但并非由 DISASSOC_DUE_TO_INACTIVITY 或 ASSOC_TOOMANY 引发。
    * - HANDSHAKE_TIMEOUT
      - 204
      - 保留
diff --git a/docs/zh_CN/api-reference/api-conventions.rst b/docs/zh_CN/api-reference/api-conventions.rst
index 592ae5ae033..e9bb4c37e9c 100644
--- a/docs/zh_CN/api-reference/api-conventions.rst
+++ b/docs/zh_CN/api-reference/api-conventions.rst
@@ -10,7 +10,7 @@ ESP-IDF 提供了几种编程接口：
 
 * 在 ESP-IDF 组件的公共头文件中声明的 C 函数、结构体、枚举、类型定义和预处理器宏。编程指南的 API 参考部分描述了这些函数、结构体和类型。
 * 编译系统函数、预定义变量和选项，详情请参阅 :ref:`ESP-IDF CMake 构建系统 API <cmake_buildsystem_api>`。
-* :doc:`Kconfig <kconfig>` 选项，可用于代码及编译系统文件 (``CMakeLists.txt``)。
+* :ref:`Kconfig <configs-in-C-Cmake>` 选项，可用于代码及编译系统文件 (``CMakeLists.txt``)。
 * :doc:`主机工具 <../api-guides/tools/index>` 及其命令行参数。
 
 ESP-IDF 由多个组件组成，组件中包含专门为 ESP 芯片编写的代码或第三方库（即第三方组件）。对于某些第三方库，ESP-IDF 提供专用的包装器和接口，以简化对第三方库的使用，或提高其与 ESP-IDF 其他功能的兼容性。某些情况下，第三方组件将直接呈现底层库的原始 API。
@@ -145,7 +145,7 @@ ESP-IDF 无法确保版本间的二进制兼容性。这意味着，如果使用
 * 为缓解安全问题做出的更改，或以更安全的行为取代不安全的默认行为的更改。
 * 从未运行成功的功能。例如，如果某个函数或枚举值从未成功使用，则可能会以修复的形式将其重命名或删除。这包括依赖于非功能芯片硬件功能的软件功能。
 * 未明确记录的意外或未定义行为可能会被修复或更改，如缺少参数范围验证。
-* 在菜单配置中 :doc:`Kconfig <kconfig>` 选项的位置。
+* 在菜单配置中 :ref:`Kconfig <project-configuration-guide>` 选项的位置。
 * 示例项目的位置和名称。
 
 .. _指定初始化器: https://en.cppreference.com/w/c/language/struct_initialization
diff --git a/docs/zh_CN/api-reference/index.rst b/docs/zh_CN/api-reference/index.rst
index ae9abca64db..f29e4a9e295 100644
--- a/docs/zh_CN/api-reference/index.rst
+++ b/docs/zh_CN/api-reference/index.rst
@@ -13,7 +13,7 @@ API 参考
    error-codes
    network/index
    peripherals/index
-   kconfig
    provisioning/index
    storage/index
    system/index
+   kconfig-reference
diff --git a/docs/zh_CN/api-reference/kconfig-reference.rst b/docs/zh_CN/api-reference/kconfig-reference.rst
new file mode 100644
index 00000000000..f29a08b39a8
--- /dev/null
+++ b/docs/zh_CN/api-reference/kconfig-reference.rst
@@ -0,0 +1 @@
+.. include:: ../../en/api-reference/kconfig-reference.rst
diff --git a/docs/zh_CN/api-reference/kconfig.rst b/docs/zh_CN/api-reference/kconfig.rst
deleted file mode 100644
index 1da2defaf6e..00000000000
--- a/docs/zh_CN/api-reference/kconfig.rst
+++ /dev/null
@@ -1,86 +0,0 @@
-项目配置
-********
-:link_to_translation:`en:[English]`
-
-简介
-=====
-
-ESP-IDF 使用基于 kconfiglib_ 的 esp-idf-kconfig_ 包，而 kconfiglib_ 是 Kconfig_ 系统的 Python 扩展。Kconfig 提供了编译时的项目配置机制，以及多种类型的配置选项（如整数、字符串和布尔值等）。Kconfig 文件指定了选项之间的依赖关系、默认值、组合方式等。
-
-了解所有可用功能，请查看 Kconfig_ 和 `kconfiglib 扩展`_。
-
-.. _project-configuration-menu:
-
-项目配置菜单
-============
-
-应用程序开发人员可以通过 ``idf.py menuconfig`` 构建目标，在终端中打开项目配置菜单。
-
-更新后，此配置将保存在项目根目录的 ``sdkconfig`` 文件中。借助 ``sdkconfig``，应用程序构建目标将在构建目录中生成 ``sdkconfig.h`` 文件，并使得 ``sdkconfig`` 选项可用于项目构建系统和源文件。
-
-使用 sdkconfig.defaults
-==============================
-
-在某些情况下，例如 ``sdkconfig`` 文件处于版本控制状态时，构建系统可能会不便于更改 ``sdkconfig`` 文件。要避免上述情况，可以在构建系统中创建 ``sdkconfig.defaults`` 文件。该文件可以手动或自动创建，且构建系统永远不会对其进行更改。该文件包含所有不同于默认选项的重要选项，其格式与 ``sdkconfig`` 文件格式相同。如果用户记得所有已更改的配置，则可以手动创建 ``sdkconfig.defaults``，或运行 ``idf.py save-defconfig`` 命令来自动生成此文件。
-
-``sdkconfig.defaults`` 创建后，用户可以删除 ``sdkconfig`` 或将其添加到版本控制系统的忽略列表中（例如 ``git`` 的 ``.gitignore`` 文件）。项目构建目标将自动创建 ``sdkconfig`` 文件，填充 ``sdkconfig.defaults`` 文件中的设置，并将其他设置配置为默认值。请注意，构建时 ``sdkconfig.defaults`` 中的设置不会覆盖 ``sdkconfig`` 的已有设置。了解更多信息，请查看 :ref:`custom-sdkconfig-defaults`。
-
-Kconfig 格式规定
-====================
-
-Kconfig 文件的格式规定如下：
-
-- 在所有菜单中，选项名称的前缀需保持一致。目前，前缀长度应为至少 3 个字符。
-- 每级采用 4 个空格的缩进方式，子项需比父项多缩进一级。例如， ``menu`` 缩进 0 个空格，``menu`` 中的 ``config`` 则缩进 4 个空格， ``config`` 中的 ``help`` 缩进 8 个空格， ``help`` 下的文本缩进 12 个空格。
-- 行末不得出现尾随空格。
-- 选项最长为 50 个字符。
-- 每行最长为 120 个字符。
-
-.. note::
-
-    菜单中不同配置的 ``help`` 小节默认视为 reStructuredText 格式，以便生成相应选项的参考文档。
-
-格式检查器
---------------
-
-esp-idf-kconfig_ 软件包中的 ``kconfcheck`` 工具可以检查 Kconfig 文件是否符合上述格式规定。检查器会检查作为参数给出的所有 Kconfig 和 ``Kconfig.projbuild`` 文件，并生成一个后缀为 ``.new`` 的新文件，如有格式错误，便会在此文件中提供修改建议。注意，检查器不能解决所有格式问题，开发人员仍需终审并修改文件，使其通过测试。例如，在没有其他误导性格式的情况下，检查器能够更正缩进，但无法为菜单内选项提供常用的前缀。
-
-``esp-idf-kconfig`` 软件包可以在 ESP-IDF 环境中使用。运行命令 ``python -m kconfcheck <path_to_kconfig_file>`` 即可调用检查工具。
-
-如需了解更多内容，请参考 `esp-idf-kconfig 相关文档 <https://github.com/espressif/esp-idf-kconfig/blob/master/docs/DOCUMENTATION.md>`__。
-
-.. _configuration-options-compatibility:
-
-Kconfig 选项的向后兼容性
-================================
-
-标准 Kconfig_ 工具会忽略 ``sdkconfig`` 中的未知选项。因此，如果开发人员对某些选项进行了自定义设置，但这些选项在 ESP-IDF 新版本中重新命名，标准 Kconfig_ 工具将忽略原有设置。以下功能可以避免上述情况：
-
-1. 工具链使用 ``kconfgen`` 预处理 ``sdkconfig`` 文件。例如， ``menuconfig`` 会读取这些文件，从而保留旧选项设置。
-2. ``kconfgen`` 递归查找 ESP-IDF 目录中所有包含新旧 Kconfig 选项名称的 ``sdkconfig.rename`` 文件。在 ``sdkconfig`` 文件中，新选项将替换旧选项。针对单个目标的重命名可以放在特定目标的重命名文件 ``sdkconfig.rename.TARGET`` 中，其中 ``TARGET`` 是目标名称，例如 ``sdkconfig.rename.esp32s2``。
-3. ``kconfgen`` 通过添加兼容性语句列表（即经过修改后，将旧选项的值设置为新选项的值），后处理 ``sdkconfig`` 文件，并生成所有构建结果（ ``sdkconfig.h``、 ``sdkconfig.cmake`` 以及 ``auto.conf``）。如果用户在其代码中仍然使用旧选项，此举可以防止用户代码出现问题。
-4. ``kconfgen`` 会自动生成 :ref:`configuration-deprecated-options`。
-
-``sdkconfig.rename`` 文件的结构如下：
-
-* 以 ``#`` 开头的行和空行将被忽略。
-* 其他所有行应遵循以下格式之一：
-    * ``CONFIG_DEPRECATED_NAME CONFIG_NEW_NAME``，其中 ``CONFIG_DEPRECATED_NAME`` 是旧配置名称，在较新的 ESP-IDF 版本中已更名为 ``CONFIG_NEW_NAME``。
-    * ``CONFIG_DEPRECATED_NAME !CONFIG_NEW_INVERTED_NAME``，其中 ``CONFIG_NEW_INVERTED_NAME`` 是在较新的 ESP-IDF 版本中通过布尔反转 ``CONFIG_DEPRECATED_NAME`` 的逻辑值而引入的新配置名称。
-
-.. _configuration-options-reference:
-
-配置选项参考
-==================
-
-以下小节包含由 Kconfig 文件自动生成的 ESP-IDF 可用选项列表。请注意，由于所选选项不同，下列某些选项可能在 ``menuconfig`` 界面中默认不可见。
-
-按照惯例，所有选项名称均为大写字母加下划线。当 Kconfig 生成 ``sdkconfig`` 和 ``sdkconfig.h`` 文件时，选项名称会以 ``CONFIG_`` 为前缀。因此，如果 Kconfig 文件定义了 ``ENABLE_FOO`` 选项且 ``menuconfig`` 中选择了该选项，则 ``sdkconfig`` 和 ``sdkconfig.h`` 文件也将定义 ``CONFIG_ENABLE_FOO``。在以下小节中，选项名称也以 ``CONFIG_`` 为前缀，与源代码相同。
-
-
-.. include-build-file:: inc/kconfig.inc
-
-.. _Kconfig: https://www.kernel.org/doc/Documentation/kbuild/kconfig-language.txt
-.. _esp-idf-kconfig: https://pypi.org/project/esp-idf-kconfig/
-.. _kconfiglib: https://github.com/ulfalizer/Kconfiglib
-.. _kconfiglib 扩展: https://pypi.org/project/kconfiglib/#kconfig-extensions
diff --git a/docs/zh_CN/api-reference/network/esp_eth.rst b/docs/zh_CN/api-reference/network/esp_eth.rst
index d4acdfb6d13..96ffa63b23c 100644
--- a/docs/zh_CN/api-reference/network/esp_eth.rst
+++ b/docs/zh_CN/api-reference/network/esp_eth.rst
@@ -269,6 +269,10 @@ PHY 的相关配置可以在 :cpp:class:`eth_phy_config_t` 中找到，具体包
 
     * :cpp:member:`eth_phy_config_t::reset_gpio_num`：如果开发板同时将 PHY 复位管脚连接至了任意 GPIO 管脚，请使用该字段进行配置。否则，配置为 ``-1``。
 
+    * :cpp:member:`eth_phy_config_t::hw_reset_assert_time_us`：PHY 复位引脚被置为有效状态的时间（以微秒为单位）。将该值配置为 ``0``，即可使用芯片默认的复位时长。
+
+    * :cpp:member:`eth_phy_config_t::post_hw_reset_delay_ms`：PHY 硬件复位完成后的等待时间（以毫秒为单位）。将该值配置为 ``0``，即可使用芯片默认的等待时长，配置为 ``-1``，表示执行 PHY 硬件复位后不等待。
+
 ESP-IDF 在宏 :c:macro:`ETH_MAC_DEFAULT_CONFIG` 和 :c:macro:`ETH_PHY_DEFAULT_CONFIG` 中为 MAC 和 PHY 提供了默认配置。
 
 
@@ -288,19 +292,23 @@ ESP-IDF 在宏 :c:macro:`ETH_MAC_DEFAULT_CONFIG` 和 :c:macro:`ETH_PHY_DEFAULT_C
 
         eth_mac_config_t mac_config = ETH_MAC_DEFAULT_CONFIG();                      // 应用默认的通用 MAC 配置
         eth_esp32_emac_config_t esp32_emac_config = ETH_ESP32_EMAC_DEFAULT_CONFIG(); // 应用默认的供应商特定 MAC 配置
-        esp32_emac_config.smi_mdc_gpio_num = CONFIG_EXAMPLE_ETH_MDC_GPIO;            // 更改用于 MDC 信号的 GPIO
-        esp32_emac_config.smi_mdio_gpio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO;          // 更改用于 MDIO 信号的 GPIO
+        esp32_emac_config.smi_gpio.mdc_num = CONFIG_EXAMPLE_ETH_MDC_GPIO;            // 更改用于 MDC 信号的 GPIO
+        esp32_emac_config.smi_gpio.mdio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO;          // 更改用于 MDIO 信号的 GPIO
         esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config); // 创建 MAC 实例
 
         eth_phy_config_t phy_config = ETH_PHY_DEFAULT_CONFIG();      // 应用默认的 PHY 配置
         phy_config.phy_addr = CONFIG_EXAMPLE_ETH_PHY_ADDR;           // 根据开发板设计更改 PHY 地址
         phy_config.reset_gpio_num = CONFIG_EXAMPLE_ETH_PHY_RST_GPIO; // 更改用于 PHY 复位的 GPIO
-        esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config);     // 创建 PHY 实例
-        // ESP-IDF 为数种以太网 PHY 芯片驱动提供官方支持
+        esp_eth_phy_t *phy = esp_eth_phy_new_generic(&phy_config);     // 创建通用 PHY 实例
+        // ESP-IDF 为数种特定以太网 PHY 芯片驱动提供官方支持
+        // esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config);
         // esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config);
         // esp_eth_phy_t *phy = esp_eth_phy_new_lan8720(&phy_config);
         // esp_eth_phy_t *phy = esp_eth_phy_new_dp83848(&phy_config);
 
+    .. note::
+        使用 :cpp:func:`esp_eth_phy_new_generic` 创建新的 PHY 实例时，可以使用任何符合 IEEE 802.3 标准的以太网 PHY 芯片。然而，尽管 PHY 芯片符合 IEEE 802.3 标准，能提供基本功能，但某些特定的功能可能无法完全实现。例如，某些以太网 PHY 芯片可能需要配置特定的速度模式才能启用环回功能。遇到这种情况，需要配置 PHY 驱动程序以满足特定芯片需求，请使用 ESP-IDF 官方支持的 PHY 芯片驱动程序，或参阅 :ref:`Custom PHY Driver <custom-phy-driver>` 小节以创建新的自定义驱动程序。
+
     可选的运行时 MAC 时钟配置
     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -557,10 +565,12 @@ ESP-IDF 在宏 :c:macro:`ETH_DEFAULT_CONFIG` 中为安装驱动程序提供了
 进阶操作
 ---------------
 
+.. _custom-phy-driver:
+
 自定义 PHY 驱动程序
 ^^^^^^^^^^^^^^^^^^^^^^^^^
 
-市面上有多家 PHY 芯片制造商提供各种类型的芯片。ESP-IDF 现已支持数种 PHY 芯片，但是由于价格、功能、库存等原因，有时用户还是无法找到一款能满足其实际需求的芯片。
+市面上有多家 PHY 芯片制造商提供各种类型的芯片。ESP-IDF 现已支持 ``通用 PHY`` 和数种特定的 PHY 芯片，但是由于价格、功能、库存等原因，有时用户还是无法找到一款能满足其实际需求的芯片。
 
 好在 IEEE 802.3 在其 22.2.4 管理功能部分对 EMAC 和 PHY 之间的管理接口进行了标准化。该部分定义了所谓的 ”MII 管理接口”规范，用于控制 PHY 和收集 PHY 的状态，还定义了一组管理寄存器来控制芯片行为、链接属性、自动协商配置等。在 ESP-IDF 中，这项基本的管理功能是由 :component_file:`esp_eth/src/phy/esp_eth_phy_802_3.c` 实现的，这也大大降低了创建新的自定义 PHY 芯片驱动的难度。
 
diff --git a/docs/zh_CN/api-reference/network/esp_netif.rst b/docs/zh_CN/api-reference/network/esp_netif.rst
index 00c0d6fe750..6d87042d18f 100644
--- a/docs/zh_CN/api-reference/network/esp_netif.rst
+++ b/docs/zh_CN/api-reference/network/esp_netif.rst
@@ -82,20 +82,19 @@ ESP-NETIF 组件使用了系统事件，典型的网络启动代码如下所示
 
 初始化网络接口可能有些复杂，ESP-NETIF 提供了一些创建常见接口（例如 Wi-Fi 和以太网）的快捷方式。
 
-以下示例展示了默认接口的初始化过程：
+请参考以下示例来了解如何初始化默认接口：
 
+.. list::
 
-.. only:: SOC_WIFI_SUPPORTED
-
-    - Wi-Fi 站点：:example_file:`wifi/getting_started/station/main/station_example_main.c`
+    :SOC_WIFI_SUPPORTED: - :example:`wifi/getting_started/station` 演示了如何使用 station 功能将 {IDF_TARGET_NAME} 连接到 AP。
 
-- 以太网：:example_file:`ethernet/basic/main/ethernet_example_main.c`
+    :CONFIG_ESP_WIFI_SOFTAP_SUPPORT: - :example:`wifi/getting_started/softAP` 演示了如何使用 SoftAP 功能将 {IDF_TARGET_NAME} 配置为 AP。
 
-- L2 TAP: :example_file:`protocols/l2tap/main/l2tap_main.c`
+    - :example:`ethernet/basic` 演示了如何使用以太网驱动程序，将其添加到 `esp_netif`，并获取一个可 ping 的 IP 地址。
 
-.. only:: CONFIG_ESP_WIFI_SOFTAP_SUPPORT
+    - :example:`protocols/l2tap` 演示了如何使用 ESP-NETIF L2 TAP 接口访问数据链路层，以接收和传输帧，实现非 IP 协议，并使用特定的 EthTypes 回显以太网帧。
 
-    - Wi-Fi 接入点：:example_file:`wifi/getting_started/softAP/main/softap_example_main.c`
+    - :example:`protocols/static_ip` 演示了如何将 Wi-Fi 配置为 station，包括设置静态 IP、子网掩码、网关和 DNS 服务器。
 
 .. only:: SOC_WIFI_SUPPORTED
 
diff --git a/docs/zh_CN/api-reference/network/esp_now.rst b/docs/zh_CN/api-reference/network/esp_now.rst
index 65e793ca59a..c3986cf30c9 100644
--- a/docs/zh_CN/api-reference/network/esp_now.rst
+++ b/docs/zh_CN/api-reference/network/esp_now.rst
@@ -13,10 +13,15 @@ CTR 与 CBC-MAC 协议 (CCMP) 可用来保护动作帧的安全。ESP-NOW 广泛
 帧格式
 ------------
 
-ESP-NOW 使用供应商的动作帧传输数据，默认比特率为 1 Mbps。目前 ESP-NOW 支持两个版本： v1.0 和 v2.0。
+ESP-NOW 使用供应商的动作帧传输数据，默认比特率为 1 Mbps。
 
-v2.0 的设备支持的最大数据包长度为 ESP_NOW_MAX_DATA_LEN_V2 bytes； v1.0 的设备支持的最大数据包长度为 ESP_NOW_MAX_DATA_LEN bytes。
-v2.0 设备可以接收来自 v2.0 和 v1.0 设备的数据包。v1.0 设备能接收来自 v1.0 的数据包。v1.0 设备可以接收长度不超过 ESP_NOW_MAX_IE_DATA_LEN 的 v2.0 数据包，而对于长度超过 ESP_NOW_MAX_IE_DATA_LEN 的数据包，它要么只接收前 ESP_NOW_MAX_IE_DATA_LEN 字节，要么丢弃数据包。具体行为请参考对应 IDF 版本中的文档。
+目前 ESP-NOW 支持两个版本：v1.0 和 v2.0。v2.0 的设备支持的最大数据包长度为 1490 (``ESP_NOW_MAX_DATA_LEN_V2``) 字节；v1.0 的设备支持的最大数据包长度为 250 (``ESP_NOW_MAX_DATA_LEN``) 字节。
+
+v2.0 设备可以接收来自 v2.0 和 v1.0 设备的数据包。v1.0 设备只能接收来自 v1.0 设备的数据包。
+
+当然，v1.0 设备也可以接收长度不超过 250 (``ESP_NOW_MAX_IE_DATA_LEN``) 的 v2.0 数据包，只是如果长度超过此值，就只接收前 250 (``ESP_NOW_MAX_IE_DATA_LEN``) 字节，或是直接丢弃数据包。
+
+具体行为请参考对应 IDF 版本中的文档。
 
 供应商的动作帧格式为：
 
diff --git a/docs/zh_CN/api-reference/network/esp_smartconfig.rst b/docs/zh_CN/api-reference/network/esp_smartconfig.rst
index 70f77b0d698..56185702cba 100644
--- a/docs/zh_CN/api-reference/network/esp_smartconfig.rst
+++ b/docs/zh_CN/api-reference/network/esp_smartconfig.rst
@@ -3,10 +3,17 @@ SmartConfig
 
 :link_to_translation:`en:[English]`
 
+概述
+-----
+
 SmartConfig\ :sup:`TM` 是由 TI 开发的配网技术，用于将新的 Wi-Fi 设备连接到 Wi-Fi 网络。它使用移动应用程序将无线网凭据从智能手机或平板电脑端广播给未配网的 Wi-Fi 设备。
 
 这项技术的优势在于，设备无需直接获知 AP 的 SSID 或密码，而是通过智能手机获取。这对于没有用户界面的无头设备和系统而言十分重要。
 
+目前， {IDF_TARGET_NAME} 支持三种类型的 SmartConfig 配网： Airkiss、ESPTouch 和 ESPTouch v2。ESPTouch v2 自 SmartConfig v3.0 （SmartConfig 的版本可以从 :cpp:func:`esp_smartconfig_get_version()` 获取）起开始支持，ESPTouch v2 和 vESPTouch 采用完全不同的配网算法，因此配网速度更快。此外，ESPTouch v2 还增加了 AES 加密功能和自定义数据字段。
+
+从 SmartConfig v3.0.2 开始，ESPTouch v2 的 AES 加密支持随机 IV。在应用程序端，当随机 IV 的选项关闭的时候，默认的 IV 为 0，与旧版本保持一致，当随机 IV 的选项打开的时候，IV 为随机值。需要注意的是，当启用 AES 加密且 IV 为随机值时，配网时间会延长，因为需要将 IV 传输到配网设备。在配网设备端，设备会根据配网包中的 flag 来识别 AES 的随机 IV 是否开启。
+
 如需通过其他方式为 {IDF_TARGET_NAME} 设备配网，请参阅 :doc:`../provisioning/index`。
 
 
diff --git a/docs/zh_CN/api-reference/network/esp_wifi.rst b/docs/zh_CN/api-reference/network/esp_wifi.rst
index f54c6424112..f2c0509d121 100644
--- a/docs/zh_CN/api-reference/network/esp_wifi.rst
+++ b/docs/zh_CN/api-reference/network/esp_wifi.rst
@@ -28,6 +28,7 @@ API 参考
 
 .. include-build-file:: inc/esp_wifi.inc
 .. include-build-file:: inc/esp_wifi_types.inc
+.. include-build-file:: inc/esp_wifi_types_generic.inc
 .. include-build-file:: inc/esp_eap_client.inc
 .. include-build-file:: inc/esp_wps.inc
 .. include-build-file:: inc/esp_rrm.inc
diff --git a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
index e1f33caf556..2232c31b3ec 100644
--- a/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
+++ b/docs/zh_CN/api-reference/peripherals/adc_continuous.rst
@@ -3,7 +3,7 @@
 
 :link_to_translation:`en:[English]`
 
-{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一", esp32c5="一"}
+{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一", esp32c5="一", esp32c61="一"}
 
 简介
 ------------
@@ -117,7 +117,7 @@ ADC 连续转换模式驱动基于 {IDF_TARGET_NAME} SAR ADC 模块实现，不
 
     - :cpp:func:`adc_continuous_monitor_enable`：启用监视器。
     - :cpp:func:`adc_continuous_monitor_disable`：禁用监视器.
-    - :cpp:func:`adc_monitor_register_callbacks`：注册用户回调函数，在 ADC 转换结果超出阈值时，执行相应操作。
+    - :cpp:func:`adc_continuous_monitor_register_event_callbacks`：注册用户回调函数，在 ADC 转换结果超出阈值时，执行相应操作。
     - :cpp:func:`adc_del_continuous_monitor`：删除监视器，释放资源。
 
     .. only:: esp32s2
@@ -129,6 +129,41 @@ ADC 连续转换模式驱动基于 {IDF_TARGET_NAME} SAR ADC 模块实现，不
             2. 每个 ADC 单元仅支持一个监视器。
             3. ADC 连续转换模式驱动中，如果启用了监视器，无需使用参数 :cpp:member:`adc_monitor_config_t::channel` 指定，某个 ADC 单元中所有已启用的通道都会受监视。
 
+    特别地，监视器功能可用于实现过零检测。由于 ADC 无法直接处理负输入信号，可以通过 **直流偏置（DC bias）** 来实现过零检测。
+
+    首先，通过电路将直流偏置添加到输入信号中，以将负信号“移位”到 ADC 的测量范围内。关于 ADC 的测量范围，请参考 `技术参考手册 <{IDF_TARGET_TRM_CN_URL}#sensor>`__ 中的片上传感器与模拟信号处理章节。例如，添加一个 1 V 的偏置可以将 -1 V 至 +1 V 的信号变换到 0 V 至 2 V 的范围。然后，通过设置合适的高阈值与低阈值，ADC 可以检测输入信号是否接近零，从而识别信号的相位变化。详情请参考下面的示例代码。
+
+    .. code:: c
+
+        // 初始化 ADC 监视器句柄
+        adc_monitor_handle_t adc_monitor_handle = NULL;
+
+        // 配置 ADC 监视器
+        adc_monitor_config_t zero_crossing_config = {
+            .adc_unit = EXAMPLE_ADC_UNIT_1,      // 指定要监视的 ADC 单元
+            .channel = EXAMPLE_ADC_CHANNEL_0,    // 指定要监视的 ADC 通道
+            .h_threshold = 1100,                 // 设置监视的高阈值为接近偏置值，请根据实际情况进行调整
+            .l_threshold = 900,                 // 设置监视的低阈值为接近偏置值，请根据实际情况进行调整
+        };
+
+        // 创建 ADC 监视器
+        ESP_ERROR_CHECK(adc_new_continuous_monitor(&zero_crossing_config, &adc_monitor_handle));
+
+        // 注册回调函数
+        adc_monitor_evt_cbs_t zero_crossing_cbs = {
+            .on_over_high_thresh = example_on_exceed_high_thresh,
+            .on_below_low_thresh = example_on_below_low_thresh,
+        };
+
+        ESP_ERROR_CHECK(adc_continuous_monitor_register_event_callbacks(adc_monitor_handle, &zero_crossing_cbs, NULL));
+
+        // 启用 ADC 监视器
+        ESP_ERROR_CHECK(adc_continuous_monitor_enable(adc_monitor_handle));
+
+        // 禁用并删除 ADC 监视器
+        ESP_ERROR_CHECK(adc_continuous_monitor_disable(adc_monitor_handle));
+        ESP_ERROR_CHECK(adc_del_continuous_monitor(adc_monitor_handle));
+
 初始化 ADC 连续转换模式驱动
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
@@ -165,7 +200,7 @@ ADC 连续转换模式驱动基于 {IDF_TARGET_NAME} SAR ADC 模块实现，不
 
 按照以下步骤设置 :cpp:type:`adc_digi_pattern_config_t`：
 
-- :cpp:member:`adc_digi_pattern_config_t::atten`：ADC 衰减。请参阅 `技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}#sensor>`__ 中的 ``ADC 特性`` 章节。
+- :cpp:member:`adc_digi_pattern_config_t::atten`：ADC 衰减。请参阅 `技术参考手册 <{IDF_TARGET_TRM_CN_URL}#sensor>`__ 中的 ``ADC 特性`` 章节。
 - :cpp:member:`adc_digi_pattern_config_t::channel`：IO 对应的 ADC 通道号，请参阅下文注意事项。
 - :cpp:member:`adc_digi_pattern_config_t::unit`：IO 所属的 ADC 单元。
 - :cpp:member:`adc_digi_pattern_config_t::bit_width`：原始转换结果的位宽。
@@ -290,39 +325,19 @@ ADC 连续转换模式驱动使用内部缓冲池保存转换结果，缓冲池
 硬件限制
 ^^^^^^^^^^^^^^^^^^^^
 
-- 一个 ADC 单元一次只能运行一种操作模式，即连续模式或单次模式。:cpp:func:`adc_continuous_start` 提供了保护措施。
-
-- 随机数生成器 (RNG) 以 ADC 为输入源。使用 ADC 连续转换模式驱动从 RNG 生成随机数时，随机性会减弱。
-
-.. only:: esp32 or esp32s2
-
-    - Wi-Fi 也使用 ADC2，:cpp:func:`adc_continuous_start` 提供了 Wi-Fi 驱动和 ADC 连续转换模式驱动之间的保护。
-
-.. only:: esp32
-
-    - ADC 连续转换模式驱动使用 I2S0 外设作为硬件 DMA FIFO。因此，如果 I2S0 已在使用中，:cpp:func:`adc_continuous_new_handle` 将返回 :c:macro:`ESP_ERR_NOT_FOUND`。
-
-    - ESP32 DevKitC：由于存在外部自动烧录电路，GPIO 0 不能用于 ADC 连续转换模式。
-
-    - ESP-WROVER-KIT：由于部分 GPIO 管脚可能已经用于其他目的，GPIO 0、2、4 和 15 不能用于 ADC 连续转换模式。
-
-.. only:: esp32s2
-
-    - ADC 连续转换模式驱动使用 SPI3 外设作为硬件 DMA FIFO。因此，如果 SPI3 已在使用中，:cpp:func:`adc_continuous_new_handle` 将返回 :c:macro:`ESP_ERR_NOT_FOUND`。
-
-.. only:: esp32c3
-
-    - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 连续转换的结果可能不稳定，具体可参考 `ESP32-C3 系列芯片勘误表 <https://www.espressif.com/sites/default/files/documentation/esp32-c3_errata_cn.pdf>`__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3`，强制使用 ADC2。
-
-.. only:: esp32s3
-
-    - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 连续转换的结果可能不稳定，具体可参考 `ESP32-S3 系列芯片勘误表 <https://www.espressif.com/sites/default/files/documentation/esp32-s3_errata_cn.pdf>`__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3`，强制使用 ADC2。
-
-    .. _adc-continuous-power-management:
+.. list::
 
-.. only:: not esp32s3
+    - 一个 ADC 单元一次只能运行一种操作模式，即连续模式或单次模式。:cpp:func:`adc_continuous_start` 提供了保护措施。
+    - 随机数生成器 (RNG) 以 ADC 为输入源。使用 ADC 连续转换模式驱动从 RNG 生成随机数时，随机性会减弱。
+    :esp32 or esp32s2: - Wi-Fi 也使用 ADC2，:cpp:func:`adc_continuous_start` 提供了 Wi-Fi 驱动和 ADC 连续转换模式驱动之间的保护。
+    :esp32: - ADC 连续转换模式驱动使用 I2S0 外设作为硬件 DMA FIFO。因此，如果 I2S0 已在使用中，:cpp:func:`adc_continuous_new_handle` 将返回 :c:macro:`ESP_ERR_NOT_FOUND`。
+    :esp32: - ESP32 DevKitC：由于存在外部自动烧录电路，GPIO 0 不能用于 ADC 连续转换模式。
+    :esp32: - ESP-WROVER-KIT：由于部分 GPIO 管脚可能已经用于其他目的，GPIO 0、2、4 和 15 不能用于 ADC 连续转换模式。
+    :esp32s2: - ADC 连续转换模式驱动使用 SPI3 外设作为硬件 DMA FIFO。因此，如果 SPI3 已在使用中，:cpp:func:`adc_continuous_new_handle` 将返回 :c:macro:`ESP_ERR_NOT_FOUND`。
+    :esp32c3: - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 连续转换的结果可能不稳定，具体可参考 `ESP32-C3 系列芯片勘误表 <https://www.espressif.com/sites/default/files/documentation/esp32-c3_errata_cn.pdf>`__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3`，强制使用 ADC2。
+    :esp32s3: - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 连续转换的结果可能不稳定，具体可参考 `ESP32-S3 系列芯片勘误表 <https://www.espressif.com/sites/default/files/documentation/esp32-s3_errata_cn.pdf>`__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_CONTINUOUS_FORCE_USE_ADC2_ON_C3_S3`，强制使用 ADC2。
 
-    .. _adc-continuous-power-management:
+.. _adc-continuous-power-management:
 
 电源管理
 ^^^^^^^^^^^^^^^^
diff --git a/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst b/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst
index 0f7a2bfbb03..8365bb49e99 100644
--- a/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst
+++ b/docs/zh_CN/api-reference/peripherals/adc_oneshot.rst
@@ -3,20 +3,17 @@
 
 :link_to_translation:`en:[English]`
 
-{IDF_TARGET_ADC_NUM:default="两", esp32c2="一", esp32c6="一", esp32h2="一", esp32c5="一"}
-
 简介
 ----
 
 模数转换器集成于芯片，支持测量特定模拟 IO 管脚的模拟信号。
 
-{IDF_TARGET_NAME} 有 {IDF_TARGET_ADC_NUM} 个 ADC 单元，可以在以下场景使用：
-
-- 生成 ADC 单次转换结果
+{IDF_TARGET_NAME} 有 {SOC_ADC_PERIPH_NUM} 个 ADC 单元，可以在以下场景使用：
 
-.. only:: SOC_ADC_DMA_SUPPORTED
+.. list::
 
-    - 生成连续 ADC 转换结果
+    - 生成 ADC 单次转换结果
+    :SOC_ADC_DMA_SUPPORTED: - 生成连续 ADC 转换结果
 
 本指南介绍了 ADC 单次转换模式。
 
@@ -164,31 +161,16 @@ ADC 单次转换模式驱动基于 {IDF_TARGET_NAME} SAR ADC 模块实现，不
 硬件限制
 ^^^^^^^^^^^^^^^^^^^^
 
-- 随机数生成器 (RNG) 以 ADC 为输入源。使用 ADC 单次转换模式驱动从 RNG 生成随机数时，随机性会减弱。
-
-.. only:: SOC_ADC_DMA_SUPPORTED
-
-    - 一个 ADC 单元每次只能在一种操作模式下运行，可以是连续模式或单次模式。:cpp:func:`adc_oneshot_start` 提供了保护措施。
-
-.. only:: esp32 or esp32s2 or esp32s3
-
-    - Wi-Fi 也使用 ADC2，:cpp:func:`adc_oneshot_read` 提供了 Wi-Fi 驱动与 ADC 单次转换模式驱动间的保护。
-
-.. only:: esp32c3
-
-    - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 单次转换的结果可能不稳定，具体可参考 `ESP32-C3 系列芯片勘误表 <https://www.espressif.com/sites/default/files/documentation/esp32-c3_errata_cn.pdf>`__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3`，强制使用 ADC2。
-
-.. only:: esp32
-
-    - ESP32-DevKitC：GPIO0 已用于自动烧录功能，不能用于 ADC 单次转换模式。
-
-    - ESP-WROVER-KIT：GPIO0、GPIO2、GPIO4 和 GPIO15 已有其他用途，不能用于 ADC 单次转换模式。
-
-    .. _adc-oneshot-power-management:
+.. list::
 
-.. only:: not esp32
+    - 随机数生成器 (RNG) 以 ADC 为输入源。使用 ADC 单次转换模式驱动从 RNG 生成随机数时，随机性会减弱。
+    :SOC_ADC_DMA_SUPPORTED: - 一个 ADC 单元每次只能在一种操作模式下运行，可以是连续模式或单次模式。:cpp:func:`adc_oneshot_start` 提供了保护措施。
+    :esp32 or esp32s2 or esp32s3: - Wi-Fi 也使用 ADC2，:cpp:func:`adc_oneshot_read` 提供了 Wi-Fi 驱动与 ADC 单次转换模式驱动间的保护。
+    :esp32c3: - 由于硬件限制，现已不再支持使用 ADC2 DMA 功能获取 ADC 转换结果。使用 ADC2 单次转换的结果可能不稳定，具体可参考 `ESP32-C3 系列芯片勘误表 <https://www.espressif.com/sites/default/files/documentation/esp32-c3_errata_cn.pdf>`__。出于兼容性考虑，可以启用 :ref:`CONFIG_ADC_ONESHOT_FORCE_USE_ADC2_ON_C3`，强制使用 ADC2。
+    :esp32: - ESP32-DevKitC：GPIO0 已用于自动烧录功能，不能用于 ADC 单次转换模式。
+    :esp32: - ESP-WROVER-KIT：GPIO0、GPIO2、GPIO4 和 GPIO15 已有其他用途，不能用于 ADC 单次转换模式。
 
-    .. _adc-oneshot-power-management:
+.. _adc-oneshot-power-management:
 
 电源管理
 ^^^^^^^^
diff --git a/docs/zh_CN/api-reference/peripherals/camera_driver.rst b/docs/zh_CN/api-reference/peripherals/camera_driver.rst
index d5dda32ca7c..80c473f7930 100644
--- a/docs/zh_CN/api-reference/peripherals/camera_driver.rst
+++ b/docs/zh_CN/api-reference/peripherals/camera_driver.rst
@@ -221,4 +221,3 @@ API 参考
 .. include-build-file:: inc/esp_cam_ctlr_types.inc
 .. include-build-file:: inc/esp_cam_ctlr_csi.inc
 .. include-build-file:: inc/esp_cam_ctlr_isp_dvp.inc
-.. include-build-file:: inc/isp_core.inc
diff --git a/docs/zh_CN/api-reference/peripherals/cap_touch_sens.rst b/docs/zh_CN/api-reference/peripherals/cap_touch_sens.rst
index 794c4e67c6b..6070b6a3013 100644
--- a/docs/zh_CN/api-reference/peripherals/cap_touch_sens.rst
+++ b/docs/zh_CN/api-reference/peripherals/cap_touch_sens.rst
@@ -3,7 +3,7 @@
 
 :link_to_translation:`en:[English]`
 
-{IDF_TARGET_TOUCH_SENSOR_VERSION:default="NOT_UPDATED", esp32p4="v3"}
+{IDF_TARGET_TOUCH_SENSOR_VERSION:default="NOT_UPDATED", esp32s2="v2", esp32s3="v2", esp32p4="v3"}
 
 概述
 ------
@@ -35,59 +35,9 @@
 触摸通道概览
 ----------------------
 
-.. only:: esp32p4
-
-    .. list-table::
-      :header-rows: 1
-      :widths: 20  20
-
-      * - 通道
-        - GPIO
-
-      * - CH0
-        - IO2
-
-      * - CH1
-        - IO3
-
-      * - CH2
-        - IO4
-
-      * - CH3
-        - IO5
-
-      * - CH4
-        - IO6
-
-      * - CH5
-        - IO7
-
-      * - CH6
-        - IO8
-
-      * - CH7
-        - IO9
-
-      * - CH8
-        - IO10
-
-      * - CH9
-        - IO11
-
-      * - CH10
-        - IO12
-
-      * - CH11
-        - IO13
-
-      * - CH12
-        - IO14
-
-      * - CH13
-        - IO15
-
-      * - CH14
-        - 未引出
+.. include:: cap_touch_sens/{IDF_TARGET_PATH_NAME}.inc
+    :start-after: touch-chan-mapping
+    :end-before: ---
 
 驱动中的术语介绍
 -------------------------
@@ -148,6 +98,7 @@
   :SOC_TOUCH_SUPPORT_WATERPROOF: - `防水防潮配置 <#touch-waterproof>`__
   :SOC_TOUCH_SUPPORT_PROX_SENSING: - `接近感应配置 <#touch-prox-sensing>`__
   :SOC_TOUCH_SUPPORT_SLEEP_WAKEUP: - `睡眠唤醒配置 <#touch-sleep-wakeup>`__
+  :SOC_TOUCH_SUPPORT_DENOISE_CHAN: - `去噪通道配置 <#touch-denoise-chan>`__
 
 .. _touch-ctrl:
 
@@ -385,7 +336,13 @@
 
     {IDF_TARGET_NAME} 支持接近感应功能。可通过调用 :cpp:func:`touch_sensor_config_proximity_sensing` 并配置 :cpp:type:`touch_proximity_config_t` 来注册接近感应功能。
 
-    由于接近感应引起的电容变化远小于物理触摸，PCB 上常用较大面积的铺铜来增大触摸通道的感应面积，另外需要在硬件上对接近感应通道进行多轮扫描并在驱动中进行累加来提高测量灵敏度。接近感应的灵敏度由测量轮数 :cpp:member:`touch_proximity_config_t::scan_times` 以及单次测量的充放电次数 :cpp:member:`touch_proximity_config_t::charge_times` 决定。测量轮数以及充放电次数越高，灵敏度越高，但是过高的灵敏度容易导致误触发，请选择适当的灵敏度来保证触发的稳定性。
+    .. only:: esp32p4
+
+        由于接近感应引起的电容变化远小于物理触摸，PCB 上常用较大面积的铺铜来增大触摸通道的感应面积，另外需要在硬件上对接近感应通道进行多轮扫描并在驱动中进行累加来提高测量灵敏度。接近感应的灵敏度由测量轮数 :cpp:member:`touch_proximity_config_t::scan_times` 以及单次测量的充放电次数 :cpp:member:`touch_proximity_config_t::charge_times` 决定。测量轮数以及充放电次数越高，灵敏度越高，但是过高的灵敏度容易导致误触发，请选择适当的灵敏度来保证触发的稳定性。
+
+    .. only:: not esp32p4
+
+        由于接近感应引起的电容变化远小于物理触摸，PCB 上常用较大面积的铺铜来增大触摸通道的感应面积，另外需要在硬件上对接近感应通道进行多轮扫描并在驱动中进行累加来提高测量灵敏度。接近感应的灵敏度由测量轮数 :cpp:member:`touch_proximity_config_t::scan_times` 决定。测量轮数以及充放电次数越高，灵敏度越高，但是过高的灵敏度容易导致误触发，请选择适当的灵敏度来保证触发的稳定性。
 
     接近感应通道多次测量的累加值也可通过 :cpp:func:`touch_channel_read_data` 获取，数据类型 :cpp:type:`touch_chan_data_type_t` 为 :cpp:enumerator:`TOUCH_CHAN_DATA_TYPE_PROXIMITY`。
 
@@ -410,7 +367,7 @@
     睡眠唤醒配置
     ^^^^^^^^^^^^^^
 
-    {IDF_TARGET_NAME} 支持触摸传感器将芯片从浅睡眠或深睡眠状态中唤醒。可通过调用 :cpp:func:`touch_sensor_config_sleep_wakeup` 并配置 :cpp:type:`touch_sleep_config_t` 来注册接近感应功能。
+    {IDF_TARGET_NAME} 支持触摸传感器将芯片从 Light-sleep 或 Deep-sleep 状态中唤醒。可通过调用 :cpp:func:`touch_sensor_config_sleep_wakeup` 并配置 :cpp:type:`touch_sleep_config_t` 来注册接近感应功能。
 
     注册触摸传感器的睡眠唤醒功能后，处于睡眠状态下的芯片仍将继续保持对触摸传感器的采样，这将会导致芯片睡眠后的功耗增加，可通过减少充放电次数、增加采样间隔等方式来降低功耗。
 
@@ -420,8 +377,8 @@
 
         若需要在睡眠过程中进行读数、配置等操作，可通过运行在 :doc:`超低功耗协处理器 ULP <../system/ulp>` 上的触摸传感器驱动 ``components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h`` 实现。
 
-    - 浅睡眠状态唤醒：通过指定 :cpp:member:`slp_wakeup_lvl` 为 :cpp:enumerator:`TOUCH_LIGHT_SLEEP_WAKEUP` 即可启用触摸传感器浅睡眠唤醒功能。注意任何已注册的触摸传感器通道都会在浅睡眠状态下保持采样并支持唤醒浅睡眠。
-    - 深睡眠状态唤醒：启用触摸传感器深睡眠唤醒功能除了指定 :cpp:member:`slp_wakeup_lvl` 为 :cpp:enumerator:`TOUCH_DEEP_SLEEP_WAKEUP` 外，还需要指定深睡眠唤醒通道 :cpp:member:`deep_slp_chan`，注意只有该指定的通道才会在深睡眠状态下保持采样以及唤醒，以此降低在深睡眠状态下的功耗。此外，若需要在深度睡眠下使用另一套低功耗的配置来进一步降低功耗，可以通过 :cpp:member:`deep_slp_sens_cfg` 额外指定一套低功耗配置，在进入深睡眠前，驱动会应用这套配置，从深睡眠状态唤醒后，则会重新配置到之前的配置。请注意当 :cpp:member:`slp_wakeup_lvl` 配置为 :cpp:enumerator:`TOUCH_DEEP_SLEEP_WAKEUP` 后，触摸传感器不仅能唤醒深睡眠状态，还能唤醒浅睡眠状态。
+    - Light-sleep 状态唤醒：通过指定 :cpp:member:`slp_wakeup_lvl` 为 :cpp:enumerator:`TOUCH_LIGHT_SLEEP_WAKEUP` 即可启用触摸传感器 Light-sleep 唤醒功能。注意任何已注册的触摸传感器通道都会在 Light-sleep 状态下保持采样并支持唤醒 Light-sleep。
+    - Deep-sleep 状态唤醒：启用触摸传感器 Deep-sleep 唤醒功能除了指定 :cpp:member:`slp_wakeup_lvl` 为 :cpp:enumerator:`TOUCH_DEEP_SLEEP_WAKEUP` 外，还需要指定 Deep-sleep 唤醒通道 :cpp:member:`deep_slp_chan`，注意只有该指定的通道才会在 Deep-sleep 状态下保持采样以及唤醒，以此降低在 Deep-sleep 状态下的功耗。此外，若需要在深度睡眠下使用另一套低功耗的配置来进一步降低功耗，可以通过 :cpp:member:`deep_slp_sens_cfg` 额外指定一套低功耗配置，在进入 Deep-sleep 前，驱动会应用这套配置，从 Deep-sleep 状态唤醒后，则会重新配置到之前的配置。请注意当 :cpp:member:`slp_wakeup_lvl` 配置为 :cpp:enumerator:`TOUCH_DEEP_SLEEP_WAKEUP` 后，触摸传感器不仅能唤醒 Deep-sleep 状态，还能唤醒 Light-sleep 状态。
 
     若需要注销睡眠唤醒功能，可再次调用 :cpp:func:`touch_sensor_config_sleep_wakeup` 并将第二个参数（即 :cpp:type:`touch_sleep_config_t` 的配置结构体指针）设为 ``NULL`` 来注销睡眠唤醒功能。
 
@@ -430,7 +387,7 @@
         touch_sleep_config_t light_slp_cfg = {
             .slp_wakeup_lvl = TOUCH_LIGHT_SLEEP_WAKEUP,
         };
-        // 注册浅睡眠唤醒功能
+        // 注册 Light-sleep 唤醒功能
         ESP_ERROR_CHECK(touch_sensor_config_sleep_wakeup(sens_handle, &light_slp_cfg));
         // ...
         // 注销睡眠唤醒功能
@@ -438,21 +395,50 @@
         touch_sleep_config_t deep_slp_cfg = {
             .slp_wakeup_lvl = TOUCH_DEEP_SLEEP_WAKEUP,
             .deep_slp_chan = dslp_chan_handle,
-            // 其他深睡眠唤醒配置
+            // 其他 Deep-sleep 唤醒配置
             // ...
         };
-        // 注册深睡眠唤醒功能
+        // 注册 Deep-sleep 唤醒功能
         ESP_ERROR_CHECK(touch_sensor_config_sleep_wakeup(sens_handle, &deep_slp_cfg));
 
+.. _touch-denoise-chan:
+
+.. only:: SOC_TOUCH_SUPPORT_DENOISE_CHAN
+
+    去噪通道配置
+    ^^^^^^^^^^^^
+
+    {IDF_TARGET_NAME} 支持通过去噪通道抑制内部背景噪声。可通过调用 :cpp:func:`touch_sensor_config_denoise_channel` 并配置 :cpp:type:`touch_denoise_chan_config_t` 来注册去噪通道。
+
+    去噪通道是一个没有引出的内部触摸通道。去噪通道使能之后，其他触摸通道的采样值会自动减去去噪通道的采样值，从而实现去噪。因此最终测量结果相比去噪前会有一定衰减。
+
+    除了常规的触摸通道配置，去噪通道还可以配置 :cpp:member:`touch_denoise_chan_config_t::ref_cap` 来指定连接到该通道上的参考电容大小，以及 :cpp:member:`touch_denoise_chan_config_t::resolution` 来指定噪声抑制的分辨率。分辨率越高，去噪通道采样值越大越精确，抑制效果越好，但同时其他触摸通道在自动扣除去噪通道采样值后的测量值衰减也越大。
+
+    例如，去噪通道分辨率为 :cpp:enumerator:`touch_denoise_chan_resolution_t::TOUCH_DENOISE_CHAN_RESOLUTION_BIT8`，即去噪通道采样值最大为 ``255``。假设此时一个常规通道实际采样值为 ``10000``，去噪通道采样值假设为 ``100``，则该常规通道扣除去噪通道采样值后的读数为 ``10000 - 100 = 9900``；若分辨率改为 :cpp:enumerator:`touch_denoise_chan_resolution_t::TOUCH_DENOISE_CHAN_RESOLUTION_BIT12`，即去噪通道采样值最大为 ``4095``，去噪通道分辨率提升 ``16`` 倍，去噪通道采样值大概为 ``100 * 16 = 1600``。此时该常规通道扣除去噪通道采样值后的读数为 ``10000 - 1600 = 8400``。
+
+    若需要注销去噪通道功能，可再次调用 :cpp:func:`touch_sensor_config_denoise_channel` 并将第二个参数（即 :cpp:type:`touch_denoise_chan_config_t` 的配置结构体指针）设为 ``NULL`` 来注销去噪通道功能。
+
+    .. code-block:: c
+
+        touch_denoise_chan_config_t denoise_cfg = {
+            // 去噪通道配置
+            // ...
+        }
+        // 注册去噪通道
+        ESP_ERROR_CHECK(touch_sensor_config_denoise_channel(sens_handle, &denoise_cfg));
+        // ...
+        // 注销去噪通道
+        ESP_ERROR_CHECK(touch_sensor_config_denoise_channel(sens_handle, NULL));
+
 应用示例
 --------
 
-    - :example:`peripherals/touch_sensor/touch_sensor_v3` 演示了如何注册触摸通道并读取数据，并说明了硬件要求及项目配置。
+    - :example:`peripherals/touch_sensor/touch_sens_basic` 演示了如何注册触摸通道并读取数据，并说明了硬件要求及项目配置。
 
 API 参考
 ----------
 
-.. only:: esp32p4
+.. only:: esp32p4 or esp32s2 or esp32s3
 
     .. include-build-file:: inc/touch_sens.inc
     .. include-build-file:: inc/touch_sens_types.inc
diff --git a/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32p4.inc b/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32p4.inc
new file mode 100644
index 00000000000..dcaf2a6ba77
--- /dev/null
+++ b/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32p4.inc
@@ -0,0 +1,64 @@
+.. This file gets included from other .rst files in this folder.
+.. It contains target-specific snippets.
+.. Comments and '---' lines act as delimiters.
+..
+.. This is necessary mainly because RST doesn't support substitutions
+.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
+.. These code blocks can be moved back to the main .rst files, with target-specific
+.. file names being replaced by substitutions.
+
+.. touch-chan-mapping
+
+.. list-table::
+    :header-rows: 1
+    :widths: 20  20
+
+    * - 通道
+      - GPIO
+
+    * - CH0
+      - IO2
+
+    * - CH1
+      - IO3
+
+    * - CH2
+      - IO4
+
+    * - CH3
+      - IO5
+
+    * - CH4
+      - IO6
+
+    * - CH5
+      - IO7
+
+    * - CH6
+      - IO8
+
+    * - CH7
+      - IO9
+
+    * - CH8
+      - IO10
+
+    * - CH9
+      - IO11
+
+    * - CH10
+      - IO12
+
+    * - CH11
+      - IO13
+
+    * - CH12
+      - IO14
+
+    * - CH13
+      - IO15
+
+    * - CH14
+      - 未引出
+
+---
diff --git a/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32s2.inc b/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32s2.inc
new file mode 100644
index 00000000000..736efa5ed8a
--- /dev/null
+++ b/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32s2.inc
@@ -0,0 +1,64 @@
+.. This file gets included from other .rst files in this folder.
+.. It contains target-specific snippets.
+.. Comments and '---' lines act as delimiters.
+..
+.. This is necessary mainly because RST doesn't support substitutions
+.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
+.. These code blocks can be moved back to the main .rst files, with target-specific
+.. file names being replaced by substitutions.
+
+.. touch-chan-mapping
+
+.. list-table::
+    :header-rows: 1
+    :widths: 20  20
+
+    * - 通道
+      - GPIO
+
+    * - CH0
+      - 未引出
+
+    * - CH1
+      - IO1
+
+    * - CH2
+      - IO2
+
+    * - CH3
+      - IO3
+
+    * - CH4
+      - IO4
+
+    * - CH5
+      - IO5
+
+    * - CH6
+      - IO6
+
+    * - CH7
+      - IO7
+
+    * - CH8
+      - IO8
+
+    * - CH9
+      - IO9
+
+    * - CH10
+      - IO10
+
+    * - CH11
+      - IO11
+
+    * - CH12
+      - IO12
+
+    * - CH13
+      - IO13
+
+    * - CH14
+      - IO14
+
+---
diff --git a/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32s3.inc b/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32s3.inc
new file mode 100644
index 00000000000..736efa5ed8a
--- /dev/null
+++ b/docs/zh_CN/api-reference/peripherals/cap_touch_sens/esp32s3.inc
@@ -0,0 +1,64 @@
+.. This file gets included from other .rst files in this folder.
+.. It contains target-specific snippets.
+.. Comments and '---' lines act as delimiters.
+..
+.. This is necessary mainly because RST doesn't support substitutions
+.. (defined in RST, not in Python) inside code blocks. If that is ever implemented,
+.. These code blocks can be moved back to the main .rst files, with target-specific
+.. file names being replaced by substitutions.
+
+.. touch-chan-mapping
+
+.. list-table::
+    :header-rows: 1
+    :widths: 20  20
+
+    * - 通道
+      - GPIO
+
+    * - CH0
+      - 未引出
+
+    * - CH1
+      - IO1
+
+    * - CH2
+      - IO2
+
+    * - CH3
+      - IO3
+
+    * - CH4
+      - IO4
+
+    * - CH5
+      - IO5
+
+    * - CH6
+      - IO6
+
+    * - CH7
+      - IO7
+
+    * - CH8
+      - IO8
+
+    * - CH9
+      - IO9
+
+    * - CH10
+      - IO10
+
+    * - CH11
+      - IO11
+
+    * - CH12
+      - IO12
+
+    * - CH13
+      - IO13
+
+    * - CH14
+      - IO14
+
+---
diff --git a/docs/zh_CN/api-reference/peripherals/dac.rst b/docs/zh_CN/api-reference/peripherals/dac.rst
index 1c45cbf8c5d..d96ce61213d 100644
--- a/docs/zh_CN/api-reference/peripherals/dac.rst
+++ b/docs/zh_CN/api-reference/peripherals/dac.rst
@@ -96,7 +96,7 @@ DAC 外设中包含一个余弦波发生器，可以在通道上产生余弦波
 
 启用电源管理时（即开启 :ref:`CONFIG_PM_ENABLE`），系统会在进入 Light-sleep 模式前调整或停止 DAC 时钟源，这可能会影响 DAC 信号，从而导致数据无法正确转换。
 
-在连续模式下使用 DAC 驱动时，可以通过获取电源管理锁来防止系统在 DMA 或余弦波模式下改变或停止时钟源。时钟源为 APB 时，锁的类型将被设置为 :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_APB_FREQ_MAX`。时钟源为 APLL 时（仅在 DMA 模式下），锁的类型将被设置为 :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_NO_LIGHT_SLEEP`。在进行 DAC 转换时（即 DMA 或余弦波发生器运行时），驱动程序会保证在调用 :cpp:func:`dac_continuous_enable` 后获取电源管理锁。同样地，在调用 :cpp:func:`dac_continuous_disable` 时，驱动程序会释放锁。
+在连续模式下使用 DAC 驱动时，可以通过获取电源管理锁来防止系统在 DMA 或余弦波模式下改变或停止时钟源。电源锁的类型将被设置为 :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_APB_FREQ_MAX`。在进行 DAC 转换时（即 DMA 或余弦波发生器运行时），驱动程序会保证在调用 :cpp:func:`dac_continuous_enable` 后获取电源管理锁。同样地，在调用 :cpp:func:`dac_continuous_disable` 时，驱动程序会释放锁。
 
 IRAM 安全
 ^^^^^^^^^
diff --git a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst
index 68d58211dbb..37f4979bf97 100644
--- a/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst
+++ b/docs/zh_CN/api-reference/peripherals/dedic_gpio.rst
@@ -16,16 +16,14 @@ GPIO 捆绑包是一组 GPIO，该组 GPIO 可以在一个 CPU 周期内同时
 
 .. note::
 
-    专用 GPIO 更像是 CPU 外设，因此与 CPU 内核关系密切。强烈建议在 pin-to-core 任务中安装和操作 GPIO 捆绑包。例如，如果 GPIOA 连接到了 CPU0，而专用的 GPIO 指令却是从 CPU1 发出的，那么就无法控制 GPIOA。
+    专用 GPIO 更像是 CPU 外设，因此与 CPU 内核关系密切。强烈建议在 pin-to-core 任务中安装和操作 GPIO 捆绑包。例如，如果 GPIO_A 连接到了 CPU_0，而专用的 GPIO 指令却是从 CPU_1 发出的，那么就无法控制 GPIO_A。
 
 安装 GPIO 捆绑包需要调用 :cpp:func:`dedic_gpio_new_bundle` 来分配软件资源并将专用通道连接到用户选择的 GPIO。GPIO 捆绑包的配置在 :cpp:type:`dedic_gpio_bundle_config_t` 结构体中：
 
-- :cpp:member:`gpio_array`：包含 GPIO 编号的数组。
-- :cpp:member:`array_size`：:cpp:member:`gpio_array` 的元素个数。
-- :cpp:member:`flags`：用于控制 GPIO 捆绑包行为的标志。
-
-  - :cpp:member:`in_en` 和 :cpp:member:`out_en` 用于选择是否开启输入输出功能（这两个功能可以同时开启）。
-  - :cpp:member:`in_invert` 和 :cpp:member:`out_invert` 用于选择是否反转 GPIO 信号。
+- :cpp:member:`dedic_gpio_bundle_config_t::gpio_array`：包含 GPIO 编号的数组。
+- :cpp:member:`dedic_gpio_bundle_config_t::array_size`: :cpp:member:`dedic_gpio_bundle_config_t::gpio_array` 的元素个数。
+- :cpp:member:`dedic_gpio_bundle_config_t::in_en` 和 :cpp:member:`dedic_gpio_bundle_config_t::out_en` 用于选择是否开启输入输出功能（这两个功能可以同时开启）。
+- :cpp:member:`dedic_gpio_bundle_config_t::in_invert` 和 :cpp:member:`dedic_gpio_bundle_config_t::out_invert` 用于选择是否反转 GPIO 信号。
 
 以下代码展示了如何安装只有输出功能的 GPIO 捆绑包：
 
@@ -33,15 +31,6 @@ GPIO 捆绑包是一组 GPIO，该组 GPIO 可以在一个 CPU 周期内同时
 
 ::
 
-    // 配置 GPIO
-    const int bundleA_gpios[] = {0, 1};
-    gpio_config_t io_conf = {
-        .mode = GPIO_MODE_OUTPUT,
-    };
-    for (int i = 0; i < sizeof(bundleA_gpios) / sizeof(bundleA_gpios[0]); i++) {
-        io_conf.pin_bit_mask = 1ULL << bundleA_gpios[i];
-        gpio_config(&io_conf);
-    }
     // 创建 bundleA，仅输出
     dedic_gpio_bundle_handle_t bundleA = NULL;
     dedic_gpio_bundle_config_t bundleA_config = {
@@ -55,10 +44,6 @@ GPIO 捆绑包是一组 GPIO，该组 GPIO 可以在一个 CPU 周期内同时
 
 如需卸载 GPIO 捆绑包，可调用 :cpp:func:`dedic_gpio_del_bundle`。
 
-.. note::
-
-    :cpp:func:`dedic_gpio_new_bundle` 不包含任何 GPIO pad 配置（例如上拉/下拉、驱动能力、输出/输入使能）。因此，在安装专用 GPIO 捆绑包之前，必须使用 GPIO 驱动程序 API（如 :cpp:func:`gpio_config`）单独配置 GPIO。更多关于 GPIO 驱动的信息，请参考 :doc:`GPIO API 参考 <gpio>`。
-
 
 GPIO 捆绑包操作
 ----------------------
@@ -92,13 +77,13 @@ GPIO 捆绑包操作
 3. 调用 CPU LL apis（如 `cpu_ll_write_dedic_gpio_mask`）或使用该掩码编写汇编代码
 4. 切换 IO 的最快捷方式是使用专用的“设置/清除”指令：
 
-    .. only:: esp32s2 or esp32s3
+    .. only:: CONFIG_IDF_TARGET_ARCH_XTENSA
 
         - 设置 GPIO 位：``set_bit_gpio_out imm[7:0]``
         - 清除 GPIO 位：``clr_bit_gpio_out imm[7:0]``
         - 注意：立即数宽度取决于专用 GPIO 通道的数量
 
-    .. only:: esp32c2 or esp32c3 or esp32c6 or esp32h2
+    .. only:: CONFIG_IDF_TARGET_ARCH_RISCV
 
         - 设置 GPIO 位：``csrrsi rd, csr, imm[4:0]``
         - 清除 GPIO 位：``csrrci rd, csr, imm[4:0]``
diff --git a/docs/zh_CN/api-reference/peripherals/etm.rst b/docs/zh_CN/api-reference/peripherals/etm.rst
index 9c1967dcadd..448b1be6c69 100644
--- a/docs/zh_CN/api-reference/peripherals/etm.rst
+++ b/docs/zh_CN/api-reference/peripherals/etm.rst
@@ -32,6 +32,7 @@ ETM 模块具有多个通道，这些通道支持用户根据需要进行配置
 - :ref:`etm-event` - 介绍如何分配新的 ETM 事件句柄，以及如何从不同外设获取现有句柄。
 - :ref:`etm-task` - 介绍如何分配新的 ETM 任务句柄，以及如何从不同外设获取现有句柄。
 - :ref:`etm-channel-control` - 介绍常见的 ETM 通道控制函数。
+- :ref:`etm-power-management` - 介绍了驱动针对功耗管理提供的选项和策略。
 - :ref:`etm-thread-safety` - 列出了驱动程序中始终线程安全的 API。
 - :ref:`etm-kconfig-options` - 列出了 ETM 支持的 Kconfig 选项，这些选项对驱动程序的行为会产生不同影响。
 
@@ -131,6 +132,17 @@ ETM 通道分析
 
 以上输出信息打印的数字 ID 在 ``soc/soc_etm_source.h`` 文件中定义。
 
+.. _etm-power-management:
+
+电源管理
+^^^^^^^^
+
+当启用电源管理时，即 :ref:`CONFIG_PM_ENABLE` 打开的时候，系统可能会调整或禁用时钟源，并在进入睡眠前关闭 ETM 外设依赖的电源。这会导致事件和任务之间的连接信息被丢失，ETM 通道在唤醒后无法正常工作。因此，默认情况下，驱动程序会获取电源管理锁，以禁止系统关闭 ETM 外设。
+
+.. only:: SOC_ETM_SUPPORT_SLEEP_RETENTION
+
+    如果你想节省更多电量，可以将 :cpp:member:`esp_etm_channel_config_t::etm_chan_flags::allow_pd` 设置为 ``true``。ETM 寄存器将在睡眠前备份，并在唤醒后恢复。请注意，启用此选项会增加内存消耗，用于保存寄存器上下文。
+
 .. _etm-thread-safety:
 
 线程安全
diff --git a/docs/zh_CN/api-reference/peripherals/gpio.rst b/docs/zh_CN/api-reference/peripherals/gpio.rst
index 761fdcd7c88..4fc0489c3d7 100644
--- a/docs/zh_CN/api-reference/peripherals/gpio.rst
+++ b/docs/zh_CN/api-reference/peripherals/gpio.rst
@@ -85,7 +85,7 @@ GPIO 驱动提供了一个函数 :cpp:func:`gpio_dump_io_configuration` 用来
 
 如果 IO 管脚通过 GPIO 交换矩阵连接到内部外设信号，输出信息打印中的外设信号 ID 定义可以在 :component_file:`soc/{IDF_TARGET_PATH_NAME}/include/soc/gpio_sig_map.h` 头文件中查看。``**RESERVED**`` 字样则表示此 IO 用于连接 SPI flash 或 PSRAM，强烈建议不要重新配置这些管脚用于其他功能。
 
-请不要依赖技术参考手册中记录的 GPIO 默认配置状态，因为特殊用途的 GPIO 可能会在 app_main 之前被引导程序或应用程序启动阶段的代码更改。
+请不要依赖技术参考手册中记录的 GPIO 默认配置状态，因为特殊用途的 GPIO 可能会在 app_main 之前被引导加载程序或应用程序启动阶段的代码更改。
 
 .. only:: esp32c3 or esp32c6 or esp32h2 or esp32p4 or esp32s2 or esp32s3 or esp32c5 or esp32c61
 
diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc
index 0535e65bfa8..aa7cc6fc8f9 100644
--- a/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc
+++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc
@@ -9,7 +9,7 @@
 
 .. gpio-summary
 
-{IDF_TARGET_NAME} 芯片具有 22 个物理 GPIO 管脚（GPIO0 ~ GPIO21）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
+{IDF_TARGET_NAME} 芯片具有 25 个物理 GPIO 管脚（GPIO0 ~ GPIO24）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
 
 下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。
 
@@ -23,7 +23,7 @@
       - 注释
 
     * - GPIO0
-      - ADC2_CH0
+      -
       - LP_GPIO0
       -
 
@@ -132,6 +132,21 @@
       -
       - SPI0/1
 
+    * - GPIO22
+      -
+      -
+      -
+
+    * - GPIO23
+      -
+      -
+      -
+
+    * - GPIO24
+      -
+      -
+      -
+
 .. note::
 
     - 其中一些管脚被用作 Strapping 管脚，可用于选择加载芯片的启动模式等。详细信息请见 `ESP32-C61 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_ > ``Strapping 管脚``。
diff --git a/docs/zh_CN/api-reference/peripherals/i2c.rst b/docs/zh_CN/api-reference/peripherals/i2c.rst
index 0b545cf773e..8898870fe97 100644
--- a/docs/zh_CN/api-reference/peripherals/i2c.rst
+++ b/docs/zh_CN/api-reference/peripherals/i2c.rst
@@ -1,4 +1,4 @@
-集成电路总线 (I2C)
+I2C 接口
 ==================
 
 :link_to_translation:`en:[English]`
@@ -44,7 +44,7 @@ I2C 时钟配置
 
     - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_DEFAULT`：默认的 I2C 时钟源。
     :SOC_I2C_SUPPORT_XTAL: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_XTAL`：以外部晶振作为 I2C 时钟源。
-    :SOC_I2C_SUPPORT_RTC: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_RC_FAST`：以内部 20 MHz RC 振荡器作为 I2C 时钟源。
+    :SOC_I2C_SUPPORT_RTC: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_RC_FAST`：以内部 20 MHz RC 振荡器作为 I2C 时钟源。
     :SOC_I2C_SUPPORT_APB: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_APB`：以 APB 时钟作为 I2C 时钟源。
     :SOC_I2C_SUPPORT_REF_TICK: - :cpp:enumerator:`i2c_clock_source_t::I2C_CLK_SRC_REF_TICK`：1 MHZ 时钟。
 
@@ -88,7 +88,7 @@ I2C 驱动程序提供以下服务：
 资源分配
 ^^^^^^^^^
 
-若系统支持 I2C 主机总线和 I2C 从机总线，则由驱动程序中的 :cpp:type:`i2c_bus_handle_t` 来表示。资源池管理可用的端口，并在有请求时分配空闲端口。
+若系统支持 I2C 主机总线，由驱动程序中的 :cpp:type:`i2c_master_bus_handle_t` 来表示。资源池管理可用的端口，并在有请求时分配空闲端口。
 
 安装 I2C 主机总线和设备
 ~~~~~~~~~~~~~~~~~~~~~~~
@@ -111,7 +111,7 @@ I2C 主机总线需要 :cpp:type:`i2c_master_bus_config_t` 指定的配置：
 - :cpp:member:`i2c_master_bus_config_t::intr_priority` 设置中断的优先级。如果设置为 ``0``，则驱动程序将使用低或中优先级的中断（优先级可设为 1、2 或 3 中的一个），若未设置，则将使用 :cpp:member:`i2c_master_bus_config_t::intr_priority` 指示的优先级。请使用数字形式（1、2、3），不要用位掩码形式（(1<<1)、(1<<2)、(1<<3)）。
 - :cpp:member:`i2c_master_bus_config_t::trans_queue_depth` 设置内部传输队列的深度，但仅在异步传输中有效。
 - :cpp:member:`i2c_master_bus_config_t::enable_internal_pullup` 启用内部上拉电阻。注意：该设置无法在高速频率下拉高总线，此时建议使用合适的外部上拉电阻。
-
+- :cpp:member:`i2c_master_bus_config_t::allow_pd` 配置驱动程序是否允许系统在睡眠模式下关闭外设电源。在进入睡眠之前，系统将备份 I2C 寄存器上下文，当系统退出睡眠模式时，这些上下文将被恢复。关闭外设可以节省更多功耗，但代价是消耗更多内存来保存寄存器上下文。你需要在功耗和内存消耗之间做权衡。此配置选项依赖于特定的硬件功能，如果在不支持的芯片上启用它，你将看到类似 ``not able to power down in light sleep`` 的错误消息。
 
 如果在 :cpp:type:`i2c_master_bus_config_t` 中指定了配置，则可调用 :cpp:func:`i2c_new_master_bus` 来分配和初始化 I2C 主机总线。如果函数运行正确，则将返回一个 I2C 总线句柄。若没有可用的 I2C 端口，此函数将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。
 
@@ -166,7 +166,6 @@ I2C 主机设备需要 :cpp:type:`i2c_device_config_t` 指定的配置：
     ESP_ERROR_CHECK(i2c_new_master_bus(&i2c_mst_config, &bus_handle));
 
     // 源文件 2
-    #include "esp_private/i2c_platform.h"
     #include "driver/i2c_master.h"
     i2c_master_bus_handle_t handle;
     ESP_ERROR_CHECK(i2c_master_get_bus_handle(0, &handle));
@@ -394,7 +393,7 @@ I2C 主机写入后读取
     };
 
     i2c_master_dev_handle_t dev_handle;
-    ESP_ERROR_CHECK(i2c_master_bus_add_device(I2C_PORT_NUM_0, &dev_cfg, &dev_handle));
+    ESP_ERROR_CHECK(i2c_master_bus_add_device(bus_handle, &dev_cfg, &dev_handle));
     uint8_t buf[20] = {0x20};
     uint8_t buffer[2];
     ESP_ERROR_CHECK(i2c_master_transmit_receive(dev_handle, buf, sizeof(buf), buffer, 2, -1));
@@ -452,20 +451,20 @@ I2C 从机的发送 buffer 可作为 FIFO 来存储要发送的数据。在主
     i2c_slave_config_t i2c_slv_config = {
         .addr_bit_len = I2C_ADDR_BIT_LEN_7,   // 7 位地址
         .clk_source = I2C_CLK_SRC_DEFAULT,    // 设置时钟源
-        .i2c_port = 0,                        // 设置 I2C 端口编号
+        .i2c_port = TEST_I2C_PORT,            // 设置 I2C 端口编号
         .send_buf_depth = 256,                // 设置 TX buffer 长度
-        .scl_io_num = 2,                      // SCL 管脚编号
-        .sda_io_num = 1,                      // SDA 管脚编号
+        .scl_io_num = I2C_SLAVE_SCL_IO,       // SCL 管脚编号
+        .sda_io_num = I2C_SLAVE_SDA_IO,       // SDA 管脚编号
         .slave_addr = 0x58,                   // 从机地址
     };
 
-    i2c_bus_handle_t i2c_bus_handle;
-    ESP_ERROR_CHECK(i2c_new_slave_device(&i2c_slv_config, &i2c_bus_handle));
+    i2c_slave_dev_handle_t slave_handle;
+    ESP_ERROR_CHECK(i2c_new_slave_device(&i2c_slv_config, &slave_handle));
     for (int i = 0; i < DATA_LENGTH; i++) {
         data_wr[i] = i;
     }
 
-    ESP_ERROR_CHECK(i2c_slave_transmit(i2c_bus_handle, data_wr, DATA_LENGTH, 10000));
+    ESP_ERROR_CHECK(i2c_slave_transmit(slave_handle, data_wr, DATA_LENGTH, 10000));
 
 I2C 从机读取
 ~~~~~~~~~~~~~
diff --git a/docs/zh_CN/api-reference/peripherals/i2s.rst b/docs/zh_CN/api-reference/peripherals/i2s.rst
index 0620798defb..ae166b6fa27 100644
--- a/docs/zh_CN/api-reference/peripherals/i2s.rst
+++ b/docs/zh_CN/api-reference/peripherals/i2s.rst
@@ -78,6 +78,10 @@ I2S 时钟
 
     - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_160M`：160 MHz PLL 时钟。
 
+.. only:: SOC_I2S_SUPPORTS_PLL_F120M
+
+    - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_120M`：120 MHz PLL 时钟。
+
 .. only:: SOC_I2S_SUPPORTS_PLL_F96M
 
     - :cpp:enumerator:`i2s_clock_src_t::I2S_CLK_SRC_PLL_96M`：96 MHz PLL 时钟。
@@ -232,7 +236,7 @@ I2S 驱动中的资源可分为三个级别：
 
 电源管理启用（即开启 :ref:`CONFIG_PM_ENABLE`）时，系统将在进入 Light-sleep 前调整或停止 I2S 时钟源，这可能会影响 I2S 信号，从而导致传输或接收的数据无效。
 
-I2S 驱动可以获取电源管理锁，从而防止系统设置更改或时钟源被禁用。时钟源为 APB 时，锁的类型将被设置为 :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_APB_FREQ_MAX`。时钟源为 APLL（若支持）时，锁的类型将被设置为 :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_NO_LIGHT_SLEEP`。用户通过 I2S 读写时（即调用 :cpp:func:`i2s_channel_read` 或 :cpp:func:`i2s_channel_write`），驱动程序将获取电源管理锁，并在读写完成后释放锁。
+I2S 驱动可以获取电源管理锁，从而防止系统设置更改或时钟源被禁用。电源锁的类型将被设置为 :cpp:enumerator:`esp_pm_lock_type_t::ESP_PM_APB_FREQ_MAX`。用户通过 I2S 读写时（即调用 :cpp:func:`i2s_channel_read` 或 :cpp:func:`i2s_channel_write`），驱动程序将获取电源管理锁，并在读写完成后释放锁。
 
 .. only:: SOC_I2S_SUPPORT_SLEEP_RETENTION
 
diff --git a/docs/zh_CN/api-reference/peripherals/index.rst b/docs/zh_CN/api-reference/peripherals/index.rst
index ea2198b57a3..bc60f6a4894 100644
--- a/docs/zh_CN/api-reference/peripherals/index.rst
+++ b/docs/zh_CN/api-reference/peripherals/index.rst
@@ -42,8 +42,8 @@
     :SOC_SPI_SUPPORT_SLAVE_HD_VER2: spi_slave_hd
     :SOC_JPEG_CODEC_SUPPORTED: jpeg
     :SOC_TEMP_SENSOR_SUPPORTED: temp_sensor
-    :SOC_TOUCH_SENSOR_SUPPORTED and not esp32p4: touch_pad
-    :esp32p4: cap_touch_sens
+    :esp32: touch_pad
+    :SOC_TOUCH_SENSOR_SUPPORTED and not esp32: cap_touch_sens
     :esp32s2: touch_element
     :SOC_TWAI_SUPPORTED: twai
     uart
diff --git a/docs/zh_CN/api-reference/peripherals/isp.rst b/docs/zh_CN/api-reference/peripherals/isp.rst
index 3770b5e0b23..466c4a18d61 100644
--- a/docs/zh_CN/api-reference/peripherals/isp.rst
+++ b/docs/zh_CN/api-reference/peripherals/isp.rst
@@ -1 +1,826 @@
-.. include:: ../../../en/api-reference/peripherals/isp.rst
+图像信号处理器 (ISP)
+====================
+
+:link_to_translation:`en:[English]`
+
+简介
+----
+
+{IDF_TARGET_NAME} 内含图像信号处理器 (ISP)，是由众多图像处理算法组成的流水线。ISP 从 DVP 摄像头、MIPI-CSI 摄像头或系统存储处接收图像数据，并通过 DMA 将处理后的图像数据写入系统存储。ISP 需要与其他摄像头控制器模块协同工作，无法独立工作。
+
+术语表
+------
+
+.. list::
+
+    - MIPI-CSI：符合 MIPI 规范的高速串行摄像头接口
+    - DVP：数字视频并行接口，通常由 vsync、hsync、de 和 data 信号组成
+    - RAW：直接从图像传感器输出的未处理数据，通常分为 R、Gr、Gb 和 B 四个通道，按位宽分为 RAW8、RAW10、RAW12 等不同格式
+    - RGB：由红、绿、蓝三种颜色组成的彩色图像格式，按每种颜色的位宽分为 RGB888、RGB565 等格式
+    - YUV：由亮度和色度组成的彩色图像格式，按数据排列方式分为 YUV444、YUV422、YUV420 等格式
+    - AF：自动对焦
+    - AWB：自动白平衡
+    - AE：自动曝光
+    - HIST：直方图
+    - BF：拜耳域降噪
+    - CCM：色彩校正矩阵
+
+ISP 流水线
+----------
+
+.. blockdiag::
+    :scale: 100%
+    :caption: ISP 流水线
+    :align: center
+
+    blockdiag isp_pipeline {
+        orientation = portrait;
+        node_height = 30;
+        node_width = 120;
+        span_width = 100;
+        default_fontsize = 16;
+
+        isp_header [label = "ISP Header"];
+        isp_tail [label = "ISP Tail"];
+        isp_chs [label = "对比度 &\n 色调 & 饱和度", width = 150, height = 70];
+        isp_yuv [label = "YUV 限制\n YUB2RGB", width = 120, height = 70];
+
+        isp_header -> BF -> 去马赛克 -> CCM -> gamma 校正 -> RGB 转 YUV -> 锐化 -> isp_chs -> isp_yuv -> isp_tail;
+
+        BF -> HIST
+        去马赛克 -> AWB
+        去马赛克 -> AE
+        去马赛克 -> HIST
+        CCM -> AWB
+        gamma 校正 -> AE
+        RGB 转 YUV -> HIST
+        RGB 转 YUV -> AF
+    }
+
+功能概述
+--------
+
+ISP 驱动程序提供以下服务：
+
+- :ref:`isp-resource-allocation` - 涵盖如何通过正确的配置来分配 ISP 资源，以及完成工作后如何回收资源。
+- :ref:`isp-enable-disable` - 涵盖如何启用和禁用 ISP 处理器。
+- :ref:`isp-af-statistics` - 涵盖如何单次或连续获取 AF 统计信息。
+- :ref:`isp-awb-statistics` - 涵盖如何单次或连续获取 AWB 白块统计信息。
+- :ref:`isp-ae-statistics` - 涵盖如何单次或连续获取 AE 统计信息。
+- :ref:`isp-hist-statistics` - 涵盖如何单次或连续获取直方图统计信息。
+- :ref:`isp-bf` - 涵盖如何启用和配置 BF 功能。
+- :ref:`isp-ccm-config` - 涵盖如何配置 CCM。
+- :ref:`isp-demosaic` - 涵盖如何配置去马赛克功能。
+- :ref:`isp-gamma-correction` - 涵盖如何启用和配置 gamma 校正。
+- :ref:`isp-sharpen` - 涵盖如何配置锐化功能。
+- :ref:`isp-callback` - 涵盖如何将用户特定代码挂接到 ISP 驱动事件回调。
+- :ref:`isp-thread-safety` - 列出了驱动程序中线程安全的 API。
+- :ref:`isp-kconfig-options` - 列出了支持的 Kconfig 选项，这些选项可以对驱动程序产生不同影响。
+- :ref:`isp-iram-safe` - 描述了当 cache 被禁用时，如何使 ISP 中断和控制功能正常工作。
+
+.. _isp-resource-allocation:
+
+资源分配
+^^^^^^^^
+
+安装 ISP 驱动程序
+~~~~~~~~~~~~~~~~~
+
+ISP 驱动程序需要由 :cpp:type:`esp_isp_processor_cfg_t` 指定配置。
+
+指定 :cpp:type:`esp_isp_processor_cfg_t` 中的配置后，可以调用 :cpp:func:`esp_isp_new_processor` 来分配和初始化 ISP 处理器。如果函数运行正常，将返回一个 ISP 处理器句柄。请参考以下代码：
+
+.. code-block:: c
+
+    esp_isp_processor_cfg_t isp_config = {
+        .clk_src = ISP_CLK_SRC_DEFAULT,
+        ...
+    };
+
+    isp_proc_handle_t isp_proc = NULL;
+    ESP_ERROR_CHECK(esp_isp_new_processor(&isp_config, &isp_proc));
+
+使用上述句柄，可以启用/禁用 ISP 驱动程序，也可以安装其他 ISP 模块。
+
+
+安装 ISP 自动对焦 (AF) 驱动程序
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ISP 自动对焦 (AF) 驱动程序需要由 :cpp:type:`esp_isp_af_config_t` 指定配置。
+
+指定 :cpp:type:`esp_isp_af_config_t` 中的配置后，可以调用 :cpp:func:`esp_isp_new_af_controller` 来分配和初始化 ISP AF 控制器。如果函数运行正常，将返回一个 ISP AF 控制器句柄。请参考以下代码：
+
+.. code-block:: c
+
+    esp_isp_af_config_t af_config = {
+        .edge_thresh = 128,
+    };
+    isp_af_ctlr_t af_ctrlr = NULL;
+    ESP_ERROR_CHECK(esp_isp_new_af_controller(isp_proc, &af_config, &af_ctrlr));
+
+使用上述句柄，可以启用/禁用 ISP AF 驱动程序，也可以安装 ISP AF 环境检测模块。
+
+安装 ISP 自动白平衡 (AWB) 驱动程序
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ISP 自动白平衡 (AWB) 驱动程序需要由 :cpp:type:`esp_isp_awb_config_t` 指定配置。
+
+指定 :cpp:type:`esp_isp_awb_config_t` 中的配置后，可以调用 :cpp:func:`esp_isp_new_awb_controller` 来分配和初始化 ISP AWB 控制器。如果函数运行正常，将返回一个 ISP AWB 控制器句柄。请参考以下代码：
+
+.. code-block:: c
+
+    isp_awb_ctlr_t awb_ctlr = NULL;
+    uint32_t image_width = 800;
+    uint32_t image_height = 600;
+    /* AWB 配置，请参考 API 注释来调整参数 */
+    esp_isp_awb_config_t awb_config = {
+        .sample_point = ISP_AWB_SAMPLE_POINT_AFTER_CCM,
+        ...
+    };
+    ESP_ERROR_CHECK(esp_isp_new_awb_controller(isp_proc, &awb_config, &awb_ctlr));
+
+其他 AWB API 和 AWB 方案也需要此步骤中创建的 AWB 句柄。
+
+安装 ISP 自动曝光 (AE) 驱动程序
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ISP 自动曝光 (AE) 驱动程序需要由 :cpp:type:`esp_isp_ae_config_t` 指定配置。
+
+指定 :cpp:type:`esp_isp_ae_config_t` 中的配置后，可以调用 :cpp:func:`esp_isp_new_ae_controller` 来分配和初始化 ISP AE 控制器。如果函数运行正常，将返回一个 ISP AE 控制器句柄。请参考以下代码：
+
+.. code-block:: c
+
+    esp_isp_ae_config_t ae_config = {
+        .sample_point = ISP_AE_SAMPLE_POINT_AFTER_DEMOSAIC,
+        ...
+    };
+    isp_ae_ctlr_t ae_ctlr = NULL;
+    ESP_ERROR_CHECK(esp_isp_new_ae_controller(isp_proc, &ae_config, &ae_ctlr));
+
+使用上述句柄，可以启用/禁用 ISP AE 驱动程序，也可以设置 ISP AE 环境检测器。
+
+安装 ISP 直方图 (HIST) 驱动程序
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ISP 直方图 (HIST) 驱动程序需要由 :cpp:type:`esp_isp_hist_config_t` 指定配置。
+
+指定 :cpp:type:`esp_isp_hist_config_t` 中的配置后，可以调用 :cpp:func:`esp_isp_new_hist_controller` 来分配和初始化 ISP 直方图控制器。如果此函数运行正常，将返回一个 ISP HIST 控制器句柄。请参考以下代码。
+
+.. list::
+
+    - 所有子窗口权重的十进制值之和应为 256，否则统计数据将较小，并且整数值应为 0。
+    - 所有 RGB 系数的十进制值之和应为 256，否则统计数据将较小，并且整数值应为 0。
+    - segment_threshold 必须在 0~255 之间且按顺序排列。
+
+.. code:: c
+
+    esp_isp_hist_config_t hist_cfg = {
+        .segment_threshold = {16, 32, 48, 64, 80, 96, 112, 128, 144, 160, 176, 192, 208, 224, 240},
+        .hist_mode = ISP_HIST_SAMPLING_RGB,
+        .rgb_coefficient.coeff_r = {
+            .integer = 0,
+            .decimal = 86,
+        },
+        .rgb_coefficient.coeff_g = {
+            .integer = 0,
+            .decimal = 85,
+        },
+        .rgb_coefficient.coeff_b = {
+            .integer = 0,
+            .decimal = 85,
+        },
+        .window_weight = {
+            {{16, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
+            {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
+            {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
+            {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
+            {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}}, {{10, 0}},
+        },
+    };
+    isp_hist_ctlr_t hist_ctlr_ctlr = NULL;
+    ESP_ERROR_CHECK(esp_isp_new_hist_controller(isp_proc, &hist_config, &hist_ctlr));
+
+使用上述句柄，可以启用/禁用 ISP HIST 驱动程序的设置。
+
+卸载 ISP 驱动程序
+~~~~~~~~~~~~~~~~~
+
+如果不再需要先前安装的 ISP 驱动程序，建议通过调用 API 来回收资源，并释放底层硬件：
+
+.. list::
+
+    - :cpp:func:`esp_isp_del_processor`，用于 ISP 核心处理器。
+    - :cpp:func:`esp_isp_del_af_controller`，用于 ISP AF 控制器。
+    - :cpp:func:`esp_isp_del_awb_controller`，用于 ISP AWB 控制器。
+    - :cpp:func:`esp_isp_del_ae_controller`，用于 ISP AE 控制器。
+    - :cpp:func:`esp_isp_del_hist_controller`，用于 ISP 直方图控制器。
+
+.. _isp-enable-disable:
+
+启用和禁用 ISP
+^^^^^^^^^^^^^^
+
+ISP
+~~~
+
+在进行 ISP 流水线操作之前，需要先调用 :cpp:func:`esp_isp_enable` 函数来启用 ISP 处理器。此函数：
+
+* 将驱动程序状态从 **init** 切换到 **enable**。
+
+调用 :cpp:func:`esp_isp_disable` 函数会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+ISP AF 控制器
+~~~~~~~~~~~~~
+
+在进行 ISP AF 操作之前，需要先调用 :cpp:func:`esp_isp_af_controller_enable` 函数来启用 ISP AF 控制器。此函数：
+
+* 将驱动程序状态从 **init** 切换到 **enable**。
+
+调用 :cpp:func:`esp_isp_af_controller_disable` 函数会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+.. _isp-af-statistics:
+
+单次与连续 AF 数据统计
+^^^^^^^^^^^^^^^^^^^^^^
+
+调用 :cpp:func:`esp_isp_af_controller_get_oneshot_statistics` 可获取单次 AF 统计结果，请参考以下代码。
+
+除此之外，ISP AF 驱动程序还可以连续获取 AF 统计信息。调用 :cpp:func:`esp_isp_af_controller_start_continuous_statistics` 可启动连续统计，调用 :cpp:func:`esp_isp_af_controller_stop_continuous_statistics` 可停止统计。
+
+若想启用连续统计，需要先注册回调函数 :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_statistics_done` 或 :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_change` 以获取统计数据。有关如何注册回调函数，请参见 :ref:`isp-callback`。
+
+.. note::
+
+    使用连续统计时，AF 环境检测器将失效。
+
+.. code-block:: c
+
+    esp_isp_af_config_t af_config = {
+        .edge_thresh = 128,
+    };
+    isp_af_ctlr_t af_ctrlr = NULL;
+    ESP_ERROR_CHECK(esp_isp_new_af_controller(isp_proc, &af_config, &af_ctrlr));
+    ESP_ERROR_CHECK(esp_isp_af_controller_enable(af_ctrlr));
+    isp_af_result_t result = {};
+    /* 触发单次 AF 统计并获取结果，超时时长为 2000 ms */
+    ESP_ERROR_CHECK(esp_isp_af_controller_get_oneshot_statistics(af_ctrlr, 2000, &result));
+
+    /* 启动连续 AF 数据统计 */
+    ESP_ERROR_CHECK(esp_isp_af_controller_start_continuous_statistics(af_ctrlr));
+    // 可在此进行其他操作，统计结果可从回调函数中获取
+    // ......
+    // vTaskDelay(pdMS_TO_TICKS(1000));
+    /* 停止连续 AF 数据统计  */
+    ESP_ERROR_CHECK(esp_isp_af_controller_stop_continuous_statistics(af_ctrlr));
+
+    /* 禁用 AF 控制器 */
+    ESP_ERROR_CHECK(esp_isp_af_controller_disable(af_ctrlr));
+    /* 删除 AF 控制器并释放资源 */
+    ESP_ERROR_CHECK(esp_isp_del_af_controller(af_ctrlr));
+
+设置 AF 环境检测器
+^^^^^^^^^^^^^^^^^^
+
+调用 :cpp:func:`esp_isp_af_controller_set_env_detector` 来设置 ISP AF 环境检测器，请参考以下代码：
+
+.. code-block:: c
+
+    esp_isp_af_env_config_t env_config = {
+        .interval = 10,
+    };
+    isp_af_ctlr_t af_ctrlr = NULL;
+    ESP_ERROR_CHECK(esp_isp_new_af_controller(isp_proc, &af_config, &af_ctrlr));
+    ESP_ERROR_CHECK(esp_isp_af_controller_set_env_detector(af_ctrlr, &env_config));
+
+设置 AF 环境检测器阈值
+^^^^^^^^^^^^^^^^^^^^^^
+
+调用 :cpp:func:`esp_isp_af_controller_set_env_detector_threshold` 来设置 ISP AF 环境检测器的阈值。
+
+.. code-block:: c
+
+    int definition_thresh = 0;
+    int luminance_thresh = 0;
+    ESP_ERROR_CHECK(esp_isp_af_env_detector_set_threshold(env_detector, definition_thresh, luminance_thresh));
+
+ISP AWB 控制器
+~~~~~~~~~~~~~~
+
+在进行 ISP AWB 操作之前，需要先调用 :cpp:func:`esp_isp_awb_controller_enable` 以启用 ISP AWB 控制器。此函数：
+
+* 将驱动程序状态从 **init** 切换到 **enable**。
+
+调用 :cpp:func:`esp_isp_awb_controller_disable` 函数会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+.. _isp-awb-statistics:
+
+单次与连续 AWB 数据统计
+^^^^^^^^^^^^^^^^^^^^^^^
+
+调用 :cpp:func:`esp_isp_awb_controller_get_oneshot_statistics` 可获取单次 AWB 白块统计结果，请参考以下代码。
+
+除此之外，ISP AWB 驱动程序还可以连续获取 AWB 统计信息。调用 :cpp:func:`esp_isp_awb_controller_start_continuous_statistics` 可启动连续统计，调用 :cpp:func:`esp_isp_awb_controller_stop_continuous_statistics` 可停止统计。
+
+若想启用连续统计，需要先注册回调函数 :cpp:member:`esp_isp_awb_cbs_t::on_statistics_done` 以获取统计结果。有关如何注册回调函数，请参见 :ref:`isp-callback`。
+
+.. code-block:: c
+
+    bool example_isp_awb_on_statistics_done_cb(isp_awb_ctlr_t awb_ctlr, const esp_isp_awb_evt_data_t *edata, void *user_data);
+    // ...
+    isp_awb_ctlr_t awb_ctlr = NULL;
+    uint32_t image_width = 800;
+    uint32_t image_height = 600;
+    /* AWB 配置，请参考 API 注释来调整参数 */
+    esp_isp_awb_config_t awb_config = {
+        .sample_point = ISP_AWB_SAMPLE_POINT_AFTER_CCM,
+        ...
+    };
+    isp_awb_stat_result_t stat_res = {};
+    /* 创建 AWB 控制器 */
+    ESP_ERROR_CHECK(esp_isp_new_awb_controller(isp_proc, &awb_config, &awb_ctlr));
+    /* 注册 AWB 回调函数 */
+    esp_isp_awb_cbs_t awb_cb = {
+        .on_statistics_done = example_isp_awb_on_statistics_done_cb,
+    };
+    ESP_ERROR_CHECK(esp_isp_awb_register_event_callbacks(awb_ctlr, &awb_cb, NULL));
+    /* 启用 AWB 控制器 */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_enable(awb_ctlr));
+
+    /* 获取单次 AWB 统计结果 */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_get_oneshot_statistics(awb_ctlr, -1, &stat_res));
+
+    /* 启动连续 AWB 数据统计，注意在此之前需要先注册 `on_statistics_done` 回调函数 */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_start_continuous_statistics(awb_ctlr));
+    // 可在此进行其他操作，统计结果可从回调函数中获取
+    // ......
+    // vTaskDelay(pdMS_TO_TICKS(1000));
+    /* 停止连续 AWB 数据统计 */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_stop_continuous_statistics(awb_ctlr));
+
+    /* 禁用 AWB 控制器 */
+    ESP_ERROR_CHECK(esp_isp_awb_controller_disable(awb_ctlr));
+    /* 删除 AWB 控制器并释放资源 */
+    ESP_ERROR_CHECK(esp_isp_del_awb_controller(awb_ctlr));
+
+ISP AE 控制器
+~~~~~~~~~~~~~
+
+在进行 ISP AE 操作之前，需要先调用 :cpp:func:`esp_isp_ae_controller_enable` 来启用 ISP AE 控制器。此函数：
+
+* 将驱动程序状态从 **init** 切换到 **enable**。
+
+调用 :cpp:func:`esp_isp_ae_controller_disable` 函数会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+.. _isp-ae-statistics:
+
+单次与连续 AE 数据统计
+^^^^^^^^^^^^^^^^^^^^^^
+
+调用 :cpp:func:`esp_isp_ae_controller_get_oneshot_statistics` 可获取单次 AE 统计结果，请参考以下代码。
+
+使用单次 AE 数据统计时，需要禁用连续 AE 模式，否则结果可能会被环境检测器覆盖。完成单次操作后，请重新启动连续模式。
+
+除了上述单次统计 API 外，ISP AE 驱动程序还可以连续获取 AE 统计信息。调用 :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` 可启动连续统计，调用 :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` 可停止统计。
+
+若想启用连续统计，需要先注册回调函数 :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` 或 :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` 以获取统计数据。有关如何注册回调函数，请参见 :ref:`isp-callback`。
+
+.. note::
+
+    使用单次统计时，AE 环境检测器将暂时失效，并在完成单次操作后自动恢复。
+
+.. code-block:: c
+
+     esp_isp_ae_config_t ae_config = {
+        .sample_point = ISP_AE_SAMPLE_POINT_AFTER_DEMOSAIC,
+    };
+    isp_ae_ctlr_t ae_ctlr = NULL;
+    ESP_ERROR_CHECK(esp_isp_new_ae_controller(isp_proc, &ae_config, &ae_ctlr));
+    ESP_ERROR_CHECK(esp_isp_ae_controller_enable(ae_ctlr));
+    isp_ae_result_t result = {};
+    /* 触发单次 AE 统计并获取结果，超时时长为 2000 ms */
+    ESP_ERROR_CHECK(esp_isp_ae_controller_get_oneshot_statistics(ae_ctlr, 2000, &result));
+
+    /* 启动连续 AE 数据统计 */
+    ESP_ERROR_CHECK(esp_isp_ae_controller_start_continuous_statistics(ae_ctlr));
+    // 可在此进行其他操作，统计结果可从回调函数中获取
+    // ......
+    // vTaskDelay(pdMS_TO_TICKS(1000));
+    /* 停止连续 AE 数据统计 */
+    ESP_ERROR_CHECK(esp_isp_ae_controller_stop_continuous_statistics(ae_ctlr));
+
+    /* 禁用 AE 控制器 */
+    ESP_ERROR_CHECK(esp_isp_ae_controller_disable(ae_ctlr));
+    /* 删除 AE 控制器并释放资源 */
+    ESP_ERROR_CHECK(esp_isp_del_ae_controller(ae_ctlr));
+
+设置 AE 环境检测器
+^^^^^^^^^^^^^^^^^^
+
+调用 :cpp:func:`esp_isp_ae_controller_set_env_detector` 来设置 ISP AE 环境检测器，请参考以下代码：
+
+.. code:: c
+
+    esp_isp_ae_env_config_t env_config = {
+        .interval = 10,
+    };
+    ESP_ERROR_CHECK(esp_isp_ae_controller_set_env_detector(ae_ctlr, &env_config));
+
+设置 AE 环境检测器阈值
+^^^^^^^^^^^^^^^^^^^^^^
+
+调用 :cpp:func:`esp_isp_ae_controller_set_env_detector_threshold` 来设置 ISP AE 环境检测器的阈值 (1-255)。
+
+.. code:: c
+
+    esp_isp_ae_env_thresh_t env_thresh = {
+        .low_thresh = 110,
+        .high_thresh = 130,
+    };
+    ESP_ERROR_CHECK(esp_isp_ae_controller_set_env_detector_threshold(ae_ctlr, env_thresh));
+
+.. _isp-hist:
+
+ISP 直方图控制器
+~~~~~~~~~~~~~~~~
+
+在进行 ISP 直方图统计之前，需要先调用 :cpp:func:`esp_isp_hist_controller_enable` 以启用 ISP 直方图控制器。此函数：
+
+* 将驱动程序状态从 **init** 切换到 **enable**。
+
+调用 :cpp:func:`esp_isp_hist_controller_disable` 函数会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+.. _isp-hist-statistics:
+
+单次与连续直方图数据统计
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+调用 :cpp:func:`esp_isp_hist_controller_get_oneshot_statistics` 可获取单次直方图统计结果，请参考以下代码。
+
+除此之外，ISP 直方图驱动程序还可以连续获取直方图统计信息。调用 :cpp:func:`esp_isp_hist_controller_start_continuous_statistics` 可启动连续统计，调用 :cpp:func:`esp_isp_hist_controller_stop_continuous_statistics` 可停止连续统计。
+
+若想启用连续统计，需要先注册回调函数 :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` 以获取统计结果。有关如何注册回调函数，请参见 :ref:`isp-callback`。
+
+.. code:: c
+
+    static bool s_hist_scheme_on_statistics_done_callback(isp_hist_ctlr_t awb_ctrlr, const esp_isp_hist_evt_data_t *edata, void *user_data)
+    {
+        for(int i = 0; i < 16; i++) {
+            esp_rom_printf(DRAM_STR("val %d is %x\n"), i, edata->hist_result.hist_value[i]); // 获取直方图统计值
+        }
+        return true;
+    }
+
+    esp_isp_hist_cbs_t hist_cbs = {
+        .on_statistics_done = s_hist_scheme_on_statistics_done_callback,
+    };
+
+    esp_isp_hist_register_event_callbacks(hist_ctlr, &hist_cbs, hist_ctlr);
+    esp_isp_hist_controller_enable(hist_ctlr);
+
+
+.. _isp-bf:
+
+ISP BF 控制器
+~~~~~~~~~~~~~
+
+此流水线用于在拜耳模式下进行图像输入降噪。
+
+可调用 :cpp:func:`esp_isp_bf_configure` 函数配置 BF 功能，请参考以下代码：
+
+.. code-block:: c
+
+    esp_isp_bf_config_t bf_config = {
+        .denoising_level = 5,
+        .bf_template = {
+            {1, 2, 1},
+            {2, 4, 2},
+            {1, 2, 1},
+        },
+        ...
+    };
+    ESP_ERROR_CHECK(esp_isp_bf_configure(isp_proc, &bf_config));
+    ESP_ERROR_CHECK(esp_isp_bf_enable(isp_proc));
+
+:cpp:member:`esp_isp_bf_config_t::bf_template` 用于拜耳域降噪。可以通过高斯滤波器模板或均值滤波器模板来设置 :cpp:member:`esp_isp_bf_config_t::bf_template`。
+
+调用 :cpp:func:`esp_isp_bf_configure` 后，需要通过调用 :cpp:func:`esp_isp_bf_enable` 来启用 ISP BF 控制器。此函数：
+
+* 将驱动程序状态从 **init** 切换到 **enable**。
+
+调用 :cpp:func:`esp_isp_bf_disable` 函数会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+.. _isp-color:
+
+ISP 色彩控制器
+~~~~~~~~~~~~~~
+
+该流水线用于调整图像的对比度、饱和度、色调和亮度。
+
+可调用 :cpp:func:`esp_isp_color_configure` 函数配置色彩功能，请参考以下代码。
+
+{IDF_TARGET_SOC_ISP_COLOR_CONTRAST_MAX:default="1.0", esp32p4="1.0"}
+{IDF_TARGET_SOC_ISP_COLOR_CONTRAST_DEFAULT:default="1.0", esp32p4="1.0"}
+
+{IDF_TARGET_SOC_ISP_COLOR_SATURATION_MAX:default="1.0", esp32p4="1.0"}
+{IDF_TARGET_SOC_ISP_COLOR_SATURATION_DEFAULT:default="1.0", esp32p4="1.0"}
+
+{IDF_TARGET_SOC_ISP_COLOR_HUE_MAX:default="360", esp32p4="360"}
+{IDF_TARGET_SOC_ISP_COLOR_HUE_DEFAULT:default="0", esp32p4="0"}
+
+{IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_MIN:default="-127", esp32p4="-127"}
+{IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_MAX:default="128", esp32p4="128"}
+{IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_DEFAULT:default="0", esp32p4="0"}
+
+.. list::
+
+    - 对比度应为 0 ~ {IDF_TARGET_SOC_ISP_COLOR_CONTRAST_MAX}，默认值为 {IDF_TARGET_SOC_ISP_COLOR_CONTRAST_DEFAULT}
+    - 饱和度应为 0 ~ {IDF_TARGET_SOC_ISP_COLOR_SATURATION_MAX}，默认值为 {IDF_TARGET_SOC_ISP_COLOR_SATURATION_DEFAULT}
+    - 色调应为 0 ~ {IDF_TARGET_SOC_ISP_COLOR_HUE_MAX}，默认值为 {IDF_TARGET_SOC_ISP_COLOR_HUE_DEFAULT}
+    - 亮度应为 {IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_MIN} ~ {IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_MAX}，默认值为 {IDF_TARGET_SOC_ISP_COLOR_BRIGHTNESS_DEFAULT}
+
+.. code:: c
+
+    esp_isp_color_config_t color_config = {
+        .color_contrast = {
+            .integer = 1,
+            .decimal = 0,
+        },
+        .color_saturation = {
+            .integer = 1,
+            .decimal = 0,
+        },
+        .color_hue = 0,
+        .color_brightness = 0,
+    };
+    ESP_ERROR_CHECK(esp_isp_color_configure(isp_proc, &color_config));
+    ESP_ERROR_CHECK(esp_isp_color_enable(isp_proc));
+
+调用 :cpp:func:`esp_isp_color_configure` 后，需要通过调用 :cpp:func:`esp_isp_color_enable` 来启用 ISP 色彩控制器。此函数：
+
+* 将驱动程序状态从 **init** 切换为 **enable**。
+
+调用 :cpp:func:`esp_isp_color_disable` 函数会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+.. _isp-ccm-config:
+
+配置 CCM
+^^^^^^^^
+
+色彩校正矩阵可以调整 RGB888 像素格式的颜色比例，可用于通过算法调整图像颜色（例如，使用 AWB 计算结果进行白平衡），或者通过滤波算法用作过滤器。
+
+调整色彩校正矩阵的公式如下：
+
+.. code-block:: none
+
+    [ R' ]     [ RR  RG  RB  ]   [ R ]
+    [ G' ] =   [ GR  GG  GB  ] * [ G ]
+    [ B' ]     [ BR  BG  BB  ]   [ B ]
+
+可以参考以下代码进行配置：
+
+.. code-block:: c
+
+    // ...
+    // 配置 CCM
+    esp_isp_ccm_config_t ccm_cfg = {
+        .matrix = {
+            1.0, 0.0, 0.0,
+            0.0, 1.0, 0.0,
+            0.0, 0.0, 1.0
+        },
+        .saturation = false,
+        ...
+    };
+    ESP_ERROR_CHECK(esp_isp_ccm_configure(isp_proc, &ccm_cfg));
+    // 启用 CCM 模块后，配置好的 CCM 将应用到图像上
+    ESP_ERROR_CHECK(esp_isp_ccm_enable(isp_proc));
+    // CCM 也可以在启用后进行配置
+    ccm_cfg.matrix[0][0] = 2.0;
+    ESP_ERROR_CHECK(esp_isp_ccm_configure(isp_proc, &ccm_cfg));
+    // 如果不再需要 CCM，则禁用它
+    ESP_ERROR_CHECK(esp_isp_ccm_disable(isp_proc));
+
+.. _isp-demosaic:
+
+ISP 去马赛克控制器
+~~~~~~~~~~~~~~~~~~~~~~
+
+此流水线用于执行图像去马赛克算法，将 RAW 图像转换为 RGB 模式。
+
+可调用 :cpp:func:`esp_isp_demosaic_configure` 来配置去马赛克功能，请参考以下代码：
+
+.. code:: c
+
+    esp_isp_demosaic_config_t demosaic_config = {
+        .grad_ratio = {
+            .integer = 2,
+            .decimal = 5,
+        },
+        ...
+    };
+
+    ESP_ERROR_CHECK(esp_isp_demosaic_configure(isp_proc, &sharpen_config));
+    ESP_ERROR_CHECK(esp_isp_demosaic_enable(isp_proc));
+
+调用 :cpp:func:`esp_isp_demosaic_configure` 后，需要通过调用 :cpp:func:`esp_isp_demosaic_enable` 来启用 ISP 去马赛克控制器。此函数：
+
+* 将驱动程序状态从 **init** 切换到 **enable**。
+
+调用 :cpp:func:`esp_isp_demosaic_disable` 会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+即使驱动程序处于 **init** 状态，也可以调用 :cpp:func:`esp_isp_demosaic_configure`，但去马赛克配置只有在 **enable** 状态下才会生效。
+
+.. _isp-gamma-correction:
+
+启用 gamma 校正
+^^^^^^^^^^^^^^^
+
+人眼的视觉系统对物理亮度的感知是非线性的。将 gamma 校正添加到 ISP 流水线中，可以将 RGB 坐标转换为坐标与主观亮度成正比的空间。
+
+驱动程序提供了帮助函数 :cpp:func:`esp_isp_gamma_fill_curve_points`，用于填充 :cpp:type:`isp_gamma_curve_points_t`，这是描述 gamma 校正曲线的点集合。也可以通过手动声明点来获得期望的 gamma 校正曲线。每个 R/G/B 分量有自己的 gamma 校正曲线，可以通过调用 :cpp:func:`esp_isp_gamma_configure` 来配置。
+
+以下是一个典型的代码示例：
+
+.. code:: c
+
+    #include <math.h>
+
+    // 设置相机 gamma 为 0.7，gamma 校正曲线为 y = 256 * (x / 256) ^ 0.7
+    static uint32_t s_gamma_curve(uint32_t x)
+    {
+        return pow((double)x / 256, 0.7) * 256;
+    }
+
+    isp_gamma_curve_points_t pts = {};
+    ESP_ERROR_CHECK(esp_isp_gamma_fill_curve_points(s_gamma_curve, &pts));
+    ESP_ERROR_CHECK(esp_isp_gamma_configure(isp_proc, COLOR_COMPONENT_R, &pts));
+    ESP_ERROR_CHECK(esp_isp_gamma_configure(isp_proc, COLOR_COMPONENT_G, &pts));
+    ESP_ERROR_CHECK(esp_isp_gamma_configure(isp_proc, COLOR_COMPONENT_B, &pts));
+
+    // 配置完曲线参数后启用 gamma 模块
+    ESP_ERROR_CHECK(esp_isp_gamma_enable(isp_proc));
+
+    // 如果不再需要，则禁用 gamma
+    ESP_ERROR_CHECK(esp_isp_gamma_disable(isp_proc));
+
+.. _isp-sharpen:
+
+ISP 锐化控制器
+~~~~~~~~~~~~~~
+
+此流水线用于在 YUV 模式下锐化输入图像。
+
+调用 :cpp:func:`esp_isp_sharpen_configure` 来配置锐化功能，请参考以下代码。
+
+.. code:: c
+
+    esp_isp_sharpen_config_t sharpen_config = {
+        .h_thresh = 255,
+        .sharpen_template = {
+            {1, 2, 1},
+            {2, 4, 2},
+            {1, 2, 1},
+        },
+        ...
+    };
+    ESP_ERROR_CHECK(esp_isp_sharpen_configure(isp_proc, &sharpen_config));
+    ESP_ERROR_CHECK(esp_isp_sharpen_enable(isp_proc));
+
+调用 :cpp:member:`esp_isp_sharpen_config_t::sharpen_template` 进行锐化。可以通过高斯滤波器模板或均值滤波器模板来设置  :cpp:member:`esp_isp_sharpen_config_t::sharpen_template`。
+
+调用 :cpp:func:`esp_isp_sharpen_configure` 后，需要通过调用 :cpp:func:`esp_isp_sharpen_enable` 以启用 ISP 锐化控制器。此函数：
+
+* 将驱动程序状态从 **init** 切换到 **enable**。
+
+调用 :cpp:func:`esp_isp_sharpen_disable` 函数会执行相反的操作，即将驱动程序恢复到 **init** 状态。
+
+即使驱动程序处于 **init** 状态，也可以调用 :cpp:func:`esp_isp_sharpen_configure`，但锐化配置只有在 **enable** 状态下才会生效。
+
+
+.. _isp-callback:
+
+注册事件回调函数
+^^^^^^^^^^^^^^^^
+
+ISP 模块启动后，会动态生成特定事件。
+
+你也可以通过参数 ``user_data`` 将自己的上下文保存到回调函数中，用户数据将直接传递给回调函数。
+
+.. note::
+
+    下文中提到的回调函数在 ISR 上下文中被调用，必须确保这些函数不会尝试阻塞（例如，确保只从函数中调用带有 ``ISR`` 后缀的 FreeRTOS API）。
+
+注册 ISP 处理器事件回调函数
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+启用 ISP 处理器后，会动态生成多个 ISP 子模块的事件。可以通过调用 :cpp:func:`esp_isp_register_event_callbacks` 将函数挂接到中断服务例程。所有支持的事件回调函数可参见 :cpp:type:`esp_isp_evt_cbs_t`：
+
+- :cpp:member:`esp_isp_evt_cbs_t::on_sharpen_frame_done` 在完成锐化帧后设置回调函数。ISP 锐化子模块完成一帧的操作后会调用此函数。函数原型在 :cpp:type:`esp_isp_sharpen_callback_t` 中声明。
+
+注册 ISP AF 环境检测器事件回调函数
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ISP AF 环境检测器启动后，将动态生成特定事件。若想在事件发生时调用某些函数，请通过调用 :cpp:func:`esp_isp_af_env_detector_register_event_callbacks` 将目标函数挂接到中断服务程序中。所有支持的事件回调函数可参见 :cpp:type:`esp_isp_af_env_detector_evt_cbs_t`：
+
+- :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_statistics_done` 为环境统计完成事件设置回调函数。该函数原型在 :cpp:type:`esp_isp_af_env_detector_callback_t` 中声明。
+- :cpp:member:`esp_isp_af_env_detector_evt_cbs_t::on_env_change` 为环境变化事件设置回调函数。该函数原型在 :cpp:type:`esp_isp_af_env_detector_callback_t` 中声明。
+
+注册 ISP AWB 统计完成事件回调函数
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ISP AWB 控制器完成白块数据统计后，将动态生成特定事件。若想在统计完成时收到通知，请通过调用 :cpp:func:`esp_isp_awb_register_event_callbacks` 将目标函数挂接到中断服务程序中。所有支持的事件回调函数可参见 :cpp:type:`esp_isp_awb_cbs_t`：
+
+- :cpp:member:`esp_isp_awb_cbs_t::on_statistics_done` 在白块数据统计完成后设置回调函数。该函数原型在 :cpp:type:`esp_isp_awb_callback_t` 中声明。
+
+
+注册 ISP AE 环境检测器事件回调函数
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ISP AE 环境检测器启动后，将动态生成特定事件。若想在事件发生时调用某些函数，请通过调用 :cpp:func:`esp_isp_ae_env_detector_register_event_callbacks` 将目标函数挂接到中断服务程序中。所有支持的事件回调函数可参见 :cpp:type:`esp_isp_ae_env_detector_evt_cbs_t`：
+
+- :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_statistics_done` 为环境统计完成事件设置回调函数。该函数原型在 :cpp:type:`esp_isp_ae_env_detector_callback_t` 中声明。
+- :cpp:member:`esp_isp_ae_env_detector_evt_cbs_t::on_env_change` 为环境变化事件设置回调函数。该函数原型在 :cpp:type:`esp_isp_ae_env_detector_callback_t` 中声明。
+
+
+注册 ISP HIST 统计完成事件回调函数
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+ISP HIST 控制器完成亮度统计后，将动态生成特定事件。若想在统计完成时收到通知，请通过调用 :cpp:func:`esp_isp_hist_register_event_callbacks` 将目标函数挂挂接到中断服务程序。所有支持的事件回调函数可参见 :cpp:type:`esp_isp_hist_cbs_t`：
+
+- :cpp:member:`esp_isp_hist_cbs_t::on_statistics_done` 在完成亮度统计时设置回调函数。该函数原型在 :cpp:type:`esp_isp_hist_callback_t` 中声明。
+
+.. _isp-thread-safety:
+
+线程安全
+^^^^^^^^
+
+驱动程序会确保以下工厂函数的线程安全：
+
+.. list::
+
+    - :cpp:func:`esp_isp_new_processor`
+    - :cpp:func:`esp_isp_del_processor`
+    - :cpp:func:`esp_isp_new_af_controller`
+    - :cpp:func:`esp_isp_del_af_controller`
+    - :cpp:func:`esp_isp_new_awb_controller`
+    - :cpp:func:`esp_isp_del_awb_controller`
+    - :cpp:func:`esp_isp_new_ae_controller`
+    - :cpp:func:`esp_isp_del_ae_controller`
+    - :cpp:func:`esp_isp_new_hist_controller`
+    - :cpp:func:`esp_isp_del_hist_controller`
+
+使用时，可以直接从不同的 RTOS 任务中调用此类函数，无需额外锁保护。其他 API 无法确保线程安全。
+
+.. _isp-kconfig-options:
+
+Kconfig 选项
+^^^^^^^^^^^^
+
+- :ref:`CONFIG_ISP_ISR_IRAM_SAFE` 控制默认的 ISR 句柄在 cache 被禁用时是否可以正常工作。
+
+.. _isp-iram-safe:
+
+IRAM 安全
+^^^^^^^^^
+
+默认情况下，当 cache 因写入或擦除 flash 等原因而被禁用时，ISP 的中断将会延迟。
+
+Kconfig 选项 :ref:`CONFIG_ISP_ISR_IRAM_SAFE` 支持：
+
+- 即使 cache 被禁用也能启用中断
+- 将 ISR 使用的所有函数放入 IRAM
+- 将驱动程序对象放入 DRAM（以防意外映射到 PSRAM）
+
+启用上述 Kconfig 选项，保证 cache 被禁用时中断可以正常运行，但这会增加 IRAM 使用量。启用此选项后，当 cache 被禁用时，ISR 回调函数将继续运行。因此，必须确保回调函数及其上下文也是 IRAM 安全的。
+
+Kconfig 选项 :ref:`CONFIG_ISP_CTRL_FUNC_IN_IRAM` 支持：
+
+- 将一些 ISP 控制函数放入 IRAM，函数列表请参见：
+
+    .. list::
+
+        - :cpp:func:`esp_isp_sharpen_configure`
+        - :cpp:func:`esp_isp_demosaic_configure`
+
+应用示例
+--------
+
+* :example:`peripherals/isp/multi_pipelines` 演示了如何使用 ISP 流水线处理来自摄像头传感器的图像信号，并通过 DSI 外设在 LCD 屏幕上显示视频。
+
+API 参考
+--------
+
+.. include-build-file:: inc/isp.inc
+.. include-build-file:: inc/isp_af.inc
+.. include-build-file:: inc/isp_ae.inc
+.. include-build-file:: inc/isp_awb.inc
+.. include-build-file:: inc/isp_bf.inc
+.. include-build-file:: inc/isp_ccm.inc
+.. include-build-file:: inc/isp_demosaic.inc
+.. include-build-file:: inc/isp_sharpen.inc
+.. include-build-file:: inc/isp_gamma.inc
+.. include-build-file:: inc/isp_hist.inc
+.. include-build-file:: inc/isp_color.inc
+.. include-build-file:: inc/isp_core.inc
+.. include-build-file:: inc/components/esp_driver_isp/include/driver/isp_types.inc
+.. include-build-file:: inc/components/hal/include/hal/isp_types.inc
diff --git a/docs/zh_CN/api-reference/peripherals/lcd/dsi_lcd.rst b/docs/zh_CN/api-reference/peripherals/lcd/dsi_lcd.rst
index 874c8b051a3..ace7b536cab 100644
--- a/docs/zh_CN/api-reference/peripherals/lcd/dsi_lcd.rst
+++ b/docs/zh_CN/api-reference/peripherals/lcd/dsi_lcd.rst
@@ -60,7 +60,7 @@ MIPI DSI 接口的 LCD
     - :cpp:member:`esp_lcd_dpi_panel_config_t::virtual_channel` 设置虚拟通道号。与 DBI 接口类似，DPI 接口也需要设置虚拟通道。如果只连接了一个 LCD，则将此值设置为 ``0``。
     - :cpp:member:`esp_lcd_dpi_panel_config_t::dpi_clk_src` 设置 DPI 接口的时钟源。可用的时钟源列表见 :cpp:type:`mipi_dsi_dpi_clock_source_t`。
     - :cpp:member:`esp_lcd_dpi_panel_config_t::dpi_clock_freq_mhz` 设置 DPI 时钟频率 (MHz)。像素时钟频率越高，刷新率越高，但如果 DMA 带宽不足或 LCD 控制器芯片不支持高像素时钟频率，则可能会导致闪烁。
-    - :cpp:member:`esp_lcd_dpi_panel_config_t::pixel_format` 设置像素数据的像素格式。可用的像素格式见 :cpp:type:`lcd_color_rgb_pixel_format_t`。MIPI LCD 通常使用 **RGB888** 来获得最佳色彩深度。
+    - :cpp:member:`esp_lcd_dpi_panel_config_t::in_color_format` 设置输入的像素数据的格式。可用的像素格式见 :cpp:type:`lcd_color_format_t`。MIPI LCD 通常使用 **RGB888** 来获得最佳色彩深度。
     - :cpp:member:`esp_lcd_dpi_panel_config_t::video_timing` 设置 LCD 面板的特定时序参数。包括 LCD 分辨率和消隐间隔在内的必要参数列表见 :cpp:type:`esp_lcd_video_timing_t`，请依据 LCD 技术规格书填写参数。
     - :cpp:member:`esp_lcd_dpi_panel_config_t::extra_dpi_panel_flags::use_dma2d` 设置是否用 2D DMA 将用户数据异步复制到帧 buffer 中。
 
@@ -71,7 +71,7 @@ MIPI DSI 接口的 LCD
             .virtual_channel = 0,
             .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
             .dpi_clock_freq_mhz = 1 * 1000,
-            .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB888,
+            .in_color_format = LCD_COLOR_FMT_RGB888,
             .video_timing = {
                 .h_size = EXAMPLE_MIPI_DSI_LCD_H_RES,
                 .v_size = EXAMPLE_MIPI_DSI_LCD_V_RES,
diff --git a/docs/zh_CN/api-reference/peripherals/lcd/rgb_lcd.rst b/docs/zh_CN/api-reference/peripherals/lcd/rgb_lcd.rst
index 6890194ee67..f73e2a6cbb5 100644
--- a/docs/zh_CN/api-reference/peripherals/lcd/rgb_lcd.rst
+++ b/docs/zh_CN/api-reference/peripherals/lcd/rgb_lcd.rst
@@ -159,7 +159,7 @@ bounce buffer 与 PSRAM frame buffer
 
 .. note::
 
-    强烈建议在此模式下启用 Kconfig 选项：:ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` 和 :ref:`CONFIG_SPIRAM_RODATA`，开启“PSRAM XIP（就地执行）”功能，使 CPU 能从 PSRAM 里而不是主 flash 中提取指令和只读数据。此外，即使想通过 SPI 1 写入主 flash，外部存储器 cache 也不会被禁用，应用程序便能正常显示 OTA 进度条。
+    强烈建议在此模式下启用 Kconfig 选项：:ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM`，开启“PSRAM XIP（就地执行）”功能，使 CPU 能从 PSRAM 里而不是主 flash 中提取指令和只读数据。此外，即使想通过 SPI 1 写入主 flash，外部存储器 cache 也不会被禁用，应用程序便能正常显示 OTA 进度条。
 
 .. note::
 
@@ -201,8 +201,6 @@ bounce buffer 与 PSRAM frame buffer
     };
     ESP_ERROR_CHECK(esp_lcd_new_rgb_panel(&panel_config, &panel_handle));
 
-请注意，此模式下还可以设置 :cpp:member:`esp_lcd_rgb_panel_config_t::bb_invalidate_cache` 标志。启用此功能，从 PSRAM 中读取 frame buffer 数据后可以释放 cache 行。但如果在 cache 行被释放时，另一个内核恰好将数据写入 frame buffer 中，则可能导致轻微的损坏（从技术上讲，在 cache 写回和调用失效之间的时间窗口内，对 frame buffer 的写入操作会被忽略）。
-
 .. _bounce_buffer_only:
 
 只应用 bounce buffer
diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst
index e068936f540..51ce5785ecc 100644
--- a/docs/zh_CN/api-reference/peripherals/ledc.rst
+++ b/docs/zh_CN/api-reference/peripherals/ledc.rst
@@ -337,6 +337,18 @@ LED PWM 控制器 API 有多种方式即时改变 PWM 频率：
 要注册处理程序来处理中断，可调用函数 :cpp:func:`ledc_isr_register`。
 
 
+电源管理
+--------
+
+LEDC 驱动不使用电源管理锁来防止系统进入 Light-sleep 。相反，可以通过配置 :cpp:member:`ledc_channel_config_t::sleep_mode` 来选择 LEDC 外设电源域状态和 PWM 信号在睡眠期间的输出行为。默认模式是 :cpp:enumerator:`LEDC_SLEEP_MODE_NO_ALIVE_NO_PD`，它表示没有信号输出，并且 LEDC 电源域在睡眠期间不会下电。
+
+如果需要在 Light-sleep 中保持信号输出，则可以选择 :cpp:enumerator:`LEDC_SLEEP_MODE_KEEP_ALIVE` 模式。只要绑定的 LEDC 定时器时钟源兼容 Light-sleep ， PWM 信号就可以在系统进入 Light-sleep 期间继续输出。其代价是睡眠期间的功耗会更高，这是由于时钟源和 LEDC 所属的电源域无法被下电。值得注意的是，在入睡前未完成的渐变也可以在睡眠期间继续，只是有可能没法准确停在目标占空比上。系统被唤醒后，驱动会调整 PWM 占空比到原来设定的目标占空比上。
+
+.. only:: SOC_LEDC_SUPPORT_SLEEP_RETENTION
+
+    此外还有另一种睡眠模式，:cpp:enumerator:`LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD` 。选择此模式可以在睡眠中节省一些功耗，但会消耗更多内存。在进入 Light-sleep 之前，系统会保存 LEDC 寄存器上下文，并在唤醒后恢复它们，从而使 LEDC 电源域可以在睡眠期间被下电。任何未完成的渐变在从睡眠状态唤醒后都不会继续进行，而是输出一个固定占空比的 PWM 信号，该占空比与进入睡眠前的当下占空比相匹配。
+
+
 .. only:: esp32
 
     .. _ledc-api-high_low_speed_mode:
diff --git a/docs/zh_CN/api-reference/peripherals/mcpwm.rst b/docs/zh_CN/api-reference/peripherals/mcpwm.rst
index f90ba9cd429..e91e9062057 100644
--- a/docs/zh_CN/api-reference/peripherals/mcpwm.rst
+++ b/docs/zh_CN/api-reference/peripherals/mcpwm.rst
@@ -122,8 +122,6 @@ MCPWM 生成器
 
 - :cpp:member:`mcpwm_generator_config_t::gen_gpio_num` 设置生成器使用的 GPIO 编号。
 - :cpp:member:`mcpwm_generator_config_t::invert_pwm` 设置是否反相 PWM 信号。
-- :cpp:member:`mcpwm_generator_config_t::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。
-- :cpp:member:`mcpwm_generator_config_t::io_od_mode` 设置是否启用漏极开路输出。
 - :cpp:member:`mcpwm_generator_config_t::pull_up` 和 :cpp:member:`mcpwm_generator_config_t::pull_down` 用来设置是否启用内部上下拉电阻。
 
 分配成功后，:cpp:func:`mcpwm_new_generator` 将返回一个指向已分配生成器的指针。否则，函数将返回错误代码。具体来说，当 MCPWM 操作器中没有空闲生成器时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。[1]_
@@ -142,7 +140,6 @@ MCPWM 故障分为两种类型：来自 GPIO 的故障信号和软件故障。
 - :cpp:member:`mcpwm_gpio_fault_config_t::gpio_num` 设置故障所使用的 GPIO 编号。
 - :cpp:member:`mcpwm_gpio_fault_config_t::active_level` 设置故障信号的有效电平。
 - :cpp:member:`mcpwm_gpio_fault_config_t::pull_up` 和 :cpp:member:`mcpwm_gpio_fault_config_t::pull_down` 设置是否在内部拉高和/或拉低 GPIO。
-- :cpp:member:`mcpwm_gpio_fault_config_t::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。
 
 分配成功后，:cpp:func:`mcpwm_new_gpio_fault` 将返回一个指向已分配故障的指针。否则，函数将返回错误代码。具体来说，当指定 MCPWM 组中没有空闲 GPIO 故障时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。[1]_
 
@@ -163,7 +160,6 @@ MCPWM 同步源
 - :cpp:member:`mcpwm_gpio_sync_src_config_t::gpio_num` 设置同步源使用的 GPIO 编号。
 - :cpp:member:`mcpwm_gpio_sync_src_config_t::active_neg` 设置同步信号在下降沿是否有效。
 - :cpp:member:`mcpwm_gpio_sync_src_config_t::pull_up` 和 :cpp:member:`mcpwm_gpio_sync_src_config_t::pull_down` 设置是否在内部拉高和/或拉低 GPIO。
-- :cpp:member:`mcpwm_gpio_sync_src_config_t::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。
 
 分配成功后，:cpp:func:`mcpwm_new_gpio_sync_src` 将返回一个指向已分配同步源的指针。否则，函数将返回错误代码。具体来说，当 MCPWM 组中没有空闲 GPIO 时钟源时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。[1]_
 
@@ -207,8 +203,6 @@ MCPWM 组有一个专用定时器，用于捕获特定事件发生时的时间
 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pos_edge` 和 :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::neg_edge` 设置是否在输入信号的上升沿和/或下降沿捕获时间戳。
 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pull_up` 和 :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::pull_down` 设置是否在内部拉高和/或拉低 GPIO。
 - :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::invert_cap_signal` 设置是否取反捕获信号。
-- :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::io_loop_back` 设置是否启用回环模式。该模式仅用于调试，使用 GPIO 交换矩阵外设同时启用 GPIO 输入和输出。
-- :cpp:member:`mcpwm_capture_channel_config_t::extra_capture_channel_flags::keep_io_conf_at_exit` 设置是否在删除通道时保留 GPIO 的相关配置。
 
 分配成功后，:cpp:func:`mcpwm_new_capture_channel` 将返回一个指向已分配捕获通道的指针。否则，函数将返回错误代码。具体来说，当捕获定时器中没有空闲捕获通道时，将返回 :c:macro:`ESP_ERR_NOT_FOUND` 错误。
 
@@ -529,7 +523,7 @@ MCPWM 比较器可以在定时器计数器等于比较值时发送通知。若
         // NOTE: 下面的操作是无效的，不能将同一种 delay 应用于不同的 generator 上
         mcpwm_generator_set_dead_time(mcpwm_gen_b, mcpwm_gen_b, &dt_config);
 
-    然而，你可以为生成器 A 设置 ``posedge delay``，为生成器 B 设置 ``negedge delay``。另外，也可以为生成器 A 同时设置 ``posedge delay`` 和 ``negedge delay``，而让生成器 B 绕过死区模块。
+    然而，你可以为生成器 A 设置 ``posedge delay``，为生成器 B 设置 ``negedge delay``。另外，也可以为生成器 B 同时设置 ``posedge delay`` 和 ``negedge delay``，而让生成器 A 绕过死区模块。注意，如果对生成器 A 同时设置 ``negedge delay`` 和 ``posedge delay``，生成器 B 将无法正常工作。其中，生成器 A 为通过操作器句柄申请的第一个生成器，生成器 B 为通过操作器句柄申请的第二个生成器。
 
 .. note::
 
@@ -982,6 +976,11 @@ MCPWM 捕获通道支持在信号上检测到有效边沿时发送通知。须
 
 同理，每当驱动创建 MCPWM 捕获定时器实例时，都会在通过 :cpp:func:`mcpwm_capture_timer_enable` 启用定时器时获取电源管理锁，并在调用 :cpp:func:`mcpwm_capture_timer_disable` 时释放锁。
 
+.. only:: SOC_MCPWM_SUPPORT_SLEEP_RETENTION
+
+    {IDF_TARGET_NAME} 支持在进入 **Light-sleep** 之前保留 MCPWM 寄存器中的内容，并在唤醒后恢复。也就是说程序不需要在 **Light-sleep** 唤醒后重新配置 MCPWM。
+
+    该特性可以通过置位配置中的 :cpp:member:`mcpwm_timer_config_t::allow_pd` 或 :cpp:member:`mcpwm_capture_timer_config_t::allow_pd` 标志位启用。启用后驱动允许系统在 Light-sleep 时对 MCPWM 掉电，同时保存 MCPWM 的寄存器内容。它可以帮助降低 Light-sleep 时的功耗，但需要花费一些额外的存储来保存寄存器的配置。
 
 .. _mcpwm-iram-safe:
 
diff --git a/docs/zh_CN/api-reference/peripherals/pcnt.rst b/docs/zh_CN/api-reference/peripherals/pcnt.rst
index 4f4cc2b0858..acd8ed55054 100644
--- a/docs/zh_CN/api-reference/peripherals/pcnt.rst
+++ b/docs/zh_CN/api-reference/peripherals/pcnt.rst
@@ -226,7 +226,7 @@ PCNT 单元的滤波器可滤除信号中的短时毛刺，:cpp:type:`pcnt_glitc
 
 .. note::
 
-    毛刺滤波器的时钟信息来自 APB。为确保 PCNT 单元不会滤除脉冲信号，最大毛刺宽度应大于一个 APB_CLK 周期（如果 APB 的频率为 80 MHz，则最大毛刺宽度为 12.5 ns）。使能动态频率缩放 (DFS) 后，APB 的频率会发生变化，从而最大毛刺宽度也会发生变化，这会导致计数器无法正常工作。因此，第一次使能毛刺滤波器时，驱动会为 PCNT 单元安装 PM 锁。关于 PCNT 驱动的电源管理的更多信息，请参考 :ref:`pcnt-power-management`。
+    毛刺滤波器的时钟信息来自 APB。为确保 PCNT 单元不会滤除脉冲信号，最大毛刺宽度应大于一个 APB_CLK 周期（如果 APB 的频率为 80 MHz，则最大毛刺宽度为 12.5 ns）。使能动态频率缩放 (DFS) 后，APB 的频率会发生变化，从而最大毛刺宽度也会发生变化，这会导致计数器无法正常工作。因此，驱动会为每个 PCNT 单元安装电源锁。关于 PCNT 驱动的电源管理的更多信息，请参考 :ref:`pcnt-power-management`。
 
 .. code:: c
 
@@ -269,7 +269,7 @@ PCNT 单元的滤波器可滤除信号中的短时毛刺，:cpp:type:`pcnt_glitc
 
 * 将 PCNT 单元的驱动状态从 **初始** 切换到 **使能** 。
 * 如果中断服务已经在 :cpp:func:`pcnt_unit_register_event_callbacks` 延迟安装，使能中断服务。
-* 如果电源管理锁已经在 :cpp:func:`pcnt_unit_set_glitch_filter` 延迟安装，获取该电源管理锁。请参考 :ref:`pcnt-power-management` 获取更多信息。
+* 如果电源管理锁已经安装，获取该电源管理锁。请参考 :ref:`pcnt-power-management` 获取更多信息。
 
 调用函数 :cpp:func:`pcnt_unit_disable` 会进行相反的操作，即将 PCNT 单元的驱动状态切换回 **初始** 状态，禁用中断服务并释放电源管理锁。
 
@@ -327,9 +327,9 @@ PCNT 内部的硬件计数器会在计数达到高/低门限的时候自动清
 电源管理
 ^^^^^^^^^^
 
-使能电源管理（即 :ref:`CONFIG_PM_ENABLE` 开启）后，在进入 Light-sleep 模式之前，系统会调整 APB 的频率。这会改变 PCNT 毛刺滤波器的参数，从而可能导致有效信号被滤除。
+当电源管理使能（即 :ref:`CONFIG_PM_ENABLE` 开启）时，系统会在进入 Light-sleep 模式之前调整 APB 的频率，这可能导致 PCNT 毛刺滤波器将有效信号误认为噪声。
 
-驱动通过获取 :cpp:enumerator:`ESP_PM_APB_FREQ_MAX` 类型的电源管理锁来防止系统修改 APB 频率。每当通过 :cpp:func:`pcnt_unit_set_glitch_filter` 使能毛刺滤波器时，驱动可以保证系统在 :cpp:func:`pcnt_unit_enable` 使能 PCNT 单元后获取电源管理锁。而系统调用 :cpp:func:`pcnt_unit_disable` 之后，驱动会释放电源管理锁。
+为了防止这种情况发生，驱动程序可以获取类型为 :cpp:enumerator:`ESP_PM_APB_FREQ_MAX` 的电源管理锁，以确保 APB 频率保持不变。该锁在通过 :cpp:func:`pcnt_unit_enable` 使能 PCNT 单元时获取，并在通过 :cpp:func:`pcnt_unit_disable` 禁用单元时释放。
 
 .. _pcnt-iram-safe:
 
diff --git a/docs/zh_CN/api-reference/peripherals/sd_pullup_requirements.rst b/docs/zh_CN/api-reference/peripherals/sd_pullup_requirements.rst
index 4b57be13f5d..16f88d6884e 100644
--- a/docs/zh_CN/api-reference/peripherals/sd_pullup_requirements.rst
+++ b/docs/zh_CN/api-reference/peripherals/sd_pullup_requirements.rst
@@ -1 +1,360 @@
-.. include:: ../../../en/api-reference/peripherals/sd_pullup_requirements.rst
+SD 上拉需求
+===========
+
+:link_to_translation:`en:[English]`
+
+乐鑫硬件产品适用于多种场景，这些场景可能需要不同的管脚上拉状态。因此，要调整某些产品的特定管脚上拉状态，为 SD 总线提供所需的上拉电阻。
+
+{IDF_TARGET_NAME} 使用 SPI 或 SDMMC 控制器与 SD 卡通信时，需要满足 SD 卡的上拉需求。当 SD 卡在 SPI 模式或 1 位 SD 模式下运行时，SD 总线的 CMD 和 DATA (DAT0 - DAT3) 线必须通过 10 kΩ 电阻上拉。SD 卡和 SDIO 设备也应在上述所有管脚（无论是否连接到主机）上有上拉电阻，以防设备进入错误状态。
+
+.. only:: esp32
+
+    默认情况下，如果 flash 电压为 3.3 V，则 MTDI strapping 管脚与 DAT2 线的上拉电阻不兼容。详情请参阅 :ref:`mtdi_strapping_pin`。
+
+.. todo::
+
+   Add a diagram of the bus lines and pullups
+
+本文档涵盖以下章节内容：
+
+- :ref:`compatibility_overview_espressif_hw_sdio` - 简要介绍乐鑫产品管脚的默认上拉状态与 SD 总线所需状态之间的兼容性
+- :ref:`sdio_solutions`  - 解决兼容性问题的方案
+- :ref:`related_info_sdio` - 其他相关信息
+
+
+.. _compatibility_overview_espressif_hw_sdio:
+
+兼容性概述
+----------
+
+本节概述了在使用安全数字输入输出 (SDIO) 时可能出现的兼容性问题。SD 总线需要连接上拉电阻，因此要妥善解决与主机设备及从机设备有关的兼容性问题。下面每个问题都有相应解决方案的链接，主机设备和从机设备的解决方案可能有所不同。
+
+
+.. only:: esp32
+
+    片上系统 (SoCs)
+    ^^^^^^^^^^^^^^^
+
+    - ESP32（除 D2WD 版本外，请参阅 `ESP32 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_）：
+
+        - :ref:`sd_pull-up_no_pull-ups`
+        - 带有 3.3 V flash 芯片的模组，请参阅 :ref:`strapping_conflicts_dat2`
+
+    - ESP32-D2WD：
+
+        - :ref:`sd_pull-up_no_pull-ups`
+        - :ref:`no_pull-up_on_gpio12`
+
+.. only:: SOC_SDMMC_USE_GPIO_MATRIX
+
+    片上系统 (SoCs)
+    ^^^^^^^^^^^^^^^
+
+    {IDF_TARGET_NAME} SDMMC 主机控制器允许 SD 接口信号使用所有 GPIO。但建议避免使用 strapping GPIO、带内部弱下拉的 GPIO 以及通常用于其他用途的 GPIO，以防出现冲突。
+
+    .. only:: esp32s3
+
+        - GPIO0（strapping 管脚）
+        - GPIO45、GPIO46（strapping 管脚，内部弱下拉）
+        - GPIO26 - GPIO32（通常用于 SPI flash 和 PSRAM）
+        - GPIO33 - GPIO37（用于带有八线 SPI flash 或八线 PSRAM 的芯片和模组）
+        - GPIO43、GPIO44（默认用于 UART0 的 GPIO）
+        - GPIO19、GPIO20（默认用于 USB 的 GPIO）
+
+
+.. only:: esp32
+
+    系统级封装 (SIP)
+    ^^^^^^^^^^^^^^^^
+
+    - ESP32-PICO-D4：
+
+        - :ref:`sd_pull-up_no_pull-ups`
+        - :ref:`strapping_conflicts_dat2`
+
+
+    模组
+    ^^^^
+
+    - ESP32-WROOM-32 系列模组，包括 ESP32-WROOM-32、ESP32-WROOM-32D、ESP32-WROOM-32U 和 ESP32-SOLO-1
+
+        - :ref:`sd_pull-up_no_pull-ups`
+        - :ref:`strapping_conflicts_dat2`
+
+    - ESP32-WROVER 系列模组，包括 ESP32-WROVER 和 ESP32-WROVER-I
+
+        - :ref:`sd_pull-up_no_pull-ups`
+
+    - ESP32-WROVER-B 系列模组，包括 ESP32-WROVER-B 和 ESP32-WROVER-IB
+
+        - :ref:`sd_pull-up_no_pull-ups`
+        - :ref:`strapping_conflicts_dat2`
+
+
+.. only:: esp32
+
+    .. _sdio_dev_kits:
+
+    开发板
+    ^^^^^^
+
+    - ESP32-PICO-KIT，包括 PICO-KIT v4.1、v4.0 和 v3
+
+        - :ref:`sd_pull-up_no_pull-ups`
+        - :ref:`strapping_conflicts_dat2`
+        - :ref:`gpio2_strapping_pin`
+
+    - ESP32-DevKitC，包括 ESP32-DevKitC v4 和 v2
+
+        - :ref:`sd_pull-up_no_pull-ups`
+        - :ref:`strapping_conflicts_dat2`
+        - :ref:`gpio2_strapping_pin`
+
+    - ESP-WROVER-KIT
+
+        - 提供所需的上拉电阻
+        - :ref:`pull-up_conflicts_on_gpio13` （v4.1、v3、v2 和 v1）
+        - :ref:`strapping_conflicts_dat2` （v4.1、v2 和 v1）
+        - :ref:`gpio2_strapping_pin` （v2 和 v1）
+
+        通过查看安装在开发板上的模组，可以确定所使用的 ESP32-WROVER-KIT 的版本：
+
+        - ESP32-WROVER-B 对应 v4.1 版本
+        - ESP32-WROVER 对应 v3 版本
+        - ESP32-WROOM-32 对应 v1 和 v2 版本
+
+    - ESP32-LyraTD-MSC
+
+        - 提供所需的上拉电阻
+        - :ref:`strapping_conflicts_dat2`
+
+    - ESP32-LyraT
+
+        - 提供所需的上拉电阻
+        - :ref:`pull-up_conflicts_on_gpio13`
+
+.. only:: esp32s3
+
+    .. _sdio_dev_kits:
+
+    开发板
+    ^^^^^^
+
+    - ESP32-S3-DevKitC-1
+
+        - :ref:`sd_pull-up_no_pull-ups`
+
+    - ESP32-S3-USB-OTG
+
+        - 该开发板可在单线和四线 SD 模式或 SPI 模式下使用。
+        - 在 GPIO 33-38 上提供所需的上拉电阻。
+
+    - ESP32-S3-EYE
+
+        - 该开发板仅限于单线 SD 模式下使用。
+        - 在 GPIO 38-40 上提供所需的上拉电阻。
+
+.. only:: SOC_SDIO_SLAVE_SUPPORTED
+
+    非乐鑫主机
+    ^^^^^^^^^^
+
+    请确保 SDIO 主机为所有 SD 总线信号提供必要的上拉电阻。
+
+
+.. _sdio_solutions:
+
+解决方案
+--------
+
+.. _sd_pull-up_no_pull-ups:
+
+无上拉电阻
+^^^^^^^^^^
+
+.. only:: esp32 or esp32s3
+
+    如果所使用的开发板没有上拉电阻，可以执行以下操作：
+
+    - 如果主机设备和从机设备在不同的开发板上，将其中一块开发板换为带有上拉电阻的开发板。如需了解哪些乐鑫开发板带有上拉电阻，请参阅 :ref:`sdio_dev_kits`。
+    - 用一个 10 kΩ 的电阻将每个需要上拉的管脚连接到 VDD，从而附加外部上拉电阻。
+
+.. only:: not esp32 and not esp32s3
+
+    如果所使用的开发板没有上拉电阻，可以执行以下操作：
+
+    - 如果主机设备和从机设备在不同的开发板上，将其中一块开发板换为带有上拉电阻的开发板。
+    - 用一个 10 kΩ 的电阻将每个需要上拉的管脚连接到 VDD，从而附加外部上拉电阻。
+
+.. only:: esp32
+
+    .. _pull-up_conflicts_on_gpio13:
+
+    GPIO13 上拉冲突
+    ^^^^^^^^^^^^^^^
+
+    如果所用设备的 DAT3 没有正确上拉，可以参考下列操作：
+
+    - 使用 1 位 SD 模式并将设备的 DAT3 连接到 VDD
+    - 使用 SPI 模式
+    - 对 GPIO13 管脚执行以下操作之一：
+        - 移除下拉电阻
+        - 附加小于 5 kΩ 的上拉电阻（建议使用 2 kΩ 的电阻）
+        - 在 1 位 SD 模式下，通过主机、或是通过 VDD 上的 3.3 V 电压，将管脚拉高或驱动到高电平。
+
+
+    .. _strapping_conflicts_dat2:
+
+    Bootstrap 与 SDIO 在 DAT2 上的冲突
+    ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    ESP32 的启动 strapping 需求与 SDIO 协议之间存在冲突。详情请参阅 :ref:`mtdi_strapping_pin`。
+
+    要解决此冲突，可参考以下选项：
+
+    1.（推荐）烧录选择 flash 电压的 eFuse。该操作会将内部调节器的输出电压永久配置为 3.3 V，并且 GPIO12 将不再用作 strapping 管脚。烧录完成后，将上拉电阻连接到 GPIO12。
+
+    .. warning::
+
+        烧录 eFuse 是不可逆的！上述问题清单可能已经过时，因此请确保要烧录的模组内嵌 3.3 V flash 芯片，可前往 https://www.espressif.com/ 进行确认。如果在带有 1.8 V flash 芯片的模组上烧录 3.3 V eFuse，模组将停止工作。
+
+    如果确定要烧录 eFuse，请转到 ESP-IDF 目录下，通过 ``espefuse.py`` 工具运行以下命令：
+
+    .. code-block:: bash
+
+        components/esptool_py/esptool/espefuse.py set_flash_voltage 3.3V
+
+    此命令将烧录 ``XPD_SDIO_TIEH``、``XPD_SDIO_FORCE`` 和 ``XPD_SDIO_REG`` eFuse。当以上三个 eFuse 被烧录为 1 时，内部 VDD_SDIO flash 电压调节器将被永久设置为 3.3 V。如果烧录成功，将看到以下日志：
+
+    .. code-block:: bash
+
+        espefuse.py v2.6
+        Connecting....
+
+        Enable internal flash voltage regulator (VDD_SDIO) to 3.3 V.
+        The following eFuses are burned: XPD_SDIO_FORCE, XPD_SDIO_REG, XPD_SDIO_TIEH.
+        This is an irreversible operation.
+        Type 'BURN' (all capitals) to continue.
+        BURN
+        VDD_SDIO setting complete.
+
+    要检查 eFuse 的状态，请运行：
+
+    .. code-block:: none
+
+        idf.py efuse-summary
+
+    如果运行自动烧录脚本，最好使用独立的 eFuse 工具 ``espefuse.py``。此工具还具有 ``--do-not-confirm`` 选项，可在无需确认的情况下烧录 eFuse。
+
+    有关烧录 eFuse 的更多信息，请参阅 **{IDF_TARGET_NAME} 技术参考手册** [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]。
+
+    2. **如果使用 1 位 SD 模式或 SPI 模式**，请断开 DAT2 管脚并确保其被拉高。可以采取下列两个选项之一：
+
+    - 使主机的 DAT2 管脚悬空，并将从机设备的 DAT2 直接连接到 VDD。
+    - 对于从机设备，构建具有 ``SDIO_SLAVE_FLAG_DAT2_DISABLED`` 选项的固件并重新烧录设备，此选项可避免从机设备检测 DAT2 线。请注意，CCCR 寄存器将不再支持 4 位 SD 模式，但主机并不知晓这一点，因此必须在主机端禁用 4 位 SD 模式。
+
+
+    .. _no_pull-up_on_gpio12:
+
+    GPIO12 无上拉电阻
+    ^^^^^^^^^^^^^^^^^
+
+    所用模组与 SDIO 协议兼容，只需通过 10 kΩ 电阻将 GPIO12 连接到 VDD 即可。
+
+
+    .. _gpio2_strapping_pin:
+
+    下载模式不起效（次要问题）
+    ^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    当 GPIO2 管脚根据 SD 上拉需求被拉高时，将无法进入下载模式，因为 GPIO2 是一个 strapping 管脚，下载模式下必须被拉低。
+
+    可参考以下解决方案：
+
+    - 对于需要用跳线短接 GPIO0 和 GPIO2 管脚的开发板，跳线连接完成后，自动复位电路会在进入下载模式前将 GPIO2 与 GPIO0 一起拉低。
+    - 对于 GPIO2 管脚上连有组件（例如下拉电阻和/或 LED）的开发板，请查看开发板的原理图，确认连接到 GPIO2 上组件的具体情况。
+
+        - **LED** 大多数情况下不会影响操作。
+        - **下拉电阻** 可能会干扰 DAT0 信号，必须移除。
+
+    如果上述解决方案无效，请检查主机或从机设备是否带有会影响 GPIO2 的上拉电阻，如有，将其移除。
+
+
+.. only:: esp32
+
+    .. _related_info_sdio:
+
+    相关信息
+    --------
+
+    .. _mtdi_strapping_pin:
+
+    MTDI strapping 管脚
+    ^^^^^^^^^^^^^^^^^^^
+
+    MTDI (GPIO12) 为 strapping 管脚，用于选择内部调节器 (VDD_SDIO) 的输出电压，为 flash 芯片供电。该管脚带有内部下拉电阻，因此若处于未连接状态，MTDI 管脚将在启动时读取低电平，选择默认的 3.3 V 操作。
+
+    除 ESP32-WROVER-B 外的所有 ESP32-WROVER 模组都使用 1.8 V flash，并在 GPIO12 上有内部上拉电阻。使用 3.3 V flash 的其他模组在 GPIO12 管脚上没有上拉电阻，并在芯片内部 GPIO12 管脚默认使能弱下拉。
+
+    为 GPIO12 添加上拉电阻以进行 SD 卡操作时，请考虑以下事项：
+
+    - 在不使用内部调节器 (VDD_SDIO) 为 flash 供电的开发板上，GPIO12 可以被拉高。
+    - 在使用 1.8 V flash 芯片的开发板上，复位时 GPIO12 需要被拉高，这与 SD 卡操作完全兼容。
+    - 在使用内部调节器和 3.3 V flash 芯片的开发板上，复位时 GPIO12 必须被拉低，这与 SD 卡操作不兼容。有关乐鑫开发板与 SD 卡操作之间的兼容性问题，详情请参阅 :ref:`compatibility_overview_espressif_hw_sdio`。
+
+
+    内部上拉和 strapping 需求
+    ^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    使用外部电阻始终是更优选择。乐鑫产品中的内部弱上拉和下拉电阻启用后可以代替外部电阻，但此解决方案并不能保证可靠的 SDIO 通信。
+
+    话虽如此，有关内部上拉和 strapping 需求的信息仍有一些参考价值。乐鑫硬件产品不同管脚（CMD 和 DATA 等）的内部弱上拉和弱下拉电阻的默认连接情况不同。下表展示了 CMD 和 DATA 管脚的默认上拉和下拉状态。
+
+    表中使用了以下缩写：
+
+    - **WPU**：SoC 内部的弱上拉电阻
+    - **WPD**：SoC 内部的弱下拉电阻
+    - **PU**：位于乐鑫模组内部、SoC 外部的上拉电阻
+
+    .. list-table:: CMD 和 DATA 管脚的默认上拉和下拉状态
+       :widths: 25 25 25 25
+       :header-rows: 1
+
+       * - GPIO 编号
+         - 管脚名
+         - 启动状态
+         - strapping 需求
+       * - **15**
+         - CMD
+         - WPU
+         -
+       * - **2**
+         - DAT0
+         - WPD
+         - 下载模式要求低电平
+       * - **4**
+         - DAT1
+         - WPD
+         -
+       * - **12**
+         - DAT2
+         - 使用 1.8 V flash 时为 PU；3.3 V flash 时为 WPD
+         - 使用 1.8 V flash 时要求高电平；3.3 V flash 时要求低电平
+       * - **13**
+         - DAT3
+         - WPU
+         -
+
+.. only:: not esp32
+
+    .. _related_info_sdio:
+
+    相关信息
+    --------
+
+    内部上拉和 strapping 需求
+    ^^^^^^^^^^^^^^^^^^^^^^^^^
+
+    使用外部电阻始终是更优选择。乐鑫产品中的内部弱上拉和下拉电阻启用后可以代替外部电阻，但此解决方案并不能保证可靠的 SDIO 通信。
+
+    通常不建议将 strapping 管脚重复用于 SDIO 功能。SD 和 strapping 管脚的上拉、下拉需求可能会相互冲突。有关 {IDF_TARGET} strapping 管脚的详细信息，请参阅技术规格书。
diff --git a/docs/zh_CN/api-reference/peripherals/sdm.rst b/docs/zh_CN/api-reference/peripherals/sdm.rst
index 0547cd99c79..5230e67e1a4 100644
--- a/docs/zh_CN/api-reference/peripherals/sdm.rst
+++ b/docs/zh_CN/api-reference/peripherals/sdm.rst
@@ -42,7 +42,6 @@ Sigma-Delta 调制通道通常应用于以下场景：
 - :cpp:member:`sdm_config_t::clk_src` 选择 SDM 模块的时钟源。注意，所有通道选择的时钟源应保持一致。
 - :cpp:member:`sdm_config_t::sample_rate_hz` 设置 SDM 模块的采样率。提高采样率可以提高输出信号的信噪比，更容易在后级通过滤波获取高精度的原始信号。
 - :cpp:member:`sdm_config_t::invert_out` 设置是否反转输出信号。
-- :cpp:member:`sdm_config_t::io_loop_back` 通过 GPIO 矩阵外设，启用 GPIO 的输入和输出功能。注意，该字段仅供调试使用。
 
 函数 :cpp:func:`sdm_new_channel` 可能因为各种原因失败，如内存不足、参数无效等。当缺少空闲通道（即所有的硬件 SDM 通道均在使用中）时，将返回 :c:macro:`ESP_ERR_NOT_FOUND`。
 
diff --git a/docs/zh_CN/api-reference/peripherals/sdmmc_host.rst b/docs/zh_CN/api-reference/peripherals/sdmmc_host.rst
index d41e9490a50..2f8061065ec 100644
--- a/docs/zh_CN/api-reference/peripherals/sdmmc_host.rst
+++ b/docs/zh_CN/api-reference/peripherals/sdmmc_host.rst
@@ -83,14 +83,17 @@ SDMMC 主机驱动
 
 SDMMC 主机驱动支持以下速率模式：
 
-- 默认速率 (20 MHz)：对于 SD 卡，支持 1 线或 4 线传输；对于 3.3 V eMMC，支持 1 线、4 线或 8 线传输。
-- 高速模式 (40 MHz)：对于 SD 卡，支持 1 线或 4 线传输；对于 3.3 V eMMC，支持 1 线、4 线或 8 线传输。
-- 高速 DDR 模式 (40 MHz)：对于 3.3 V eMMC，支持 4 线传输。
+.. list::
+
+  - 默认速率 (20 MHz)：对于 SD 卡，支持 1 线或 4 线传输；对于 3.3 V eMMC，支持 1 线、4 线或 8 线传输。
+  - 高速模式 (40 MHz)：对于 SD 卡，支持 1 线或 4 线传输；对于 3.3 V eMMC，支持 1 线、4 线或 8 线传输。
+  :SOC_SDMMC_UHS_I_SUPPORTED: - UHS-I 1.8 V SDR50 模式 (100 MHz)：支持 4 线 SD 卡传输。
+  :SOC_SDMMC_UHS_I_SUPPORTED: - UHS-I 1.8 V DDR50 模式 (50 MHz)：支持 4 线 SD 卡传输。
+  - 高速 DDR 模式 (40 MHz)：对于 3.3 V eMMC，支持 4 线传输。
 
 当前尚不支持的速率模式：
 
 - 高速 DDR 模式：不支持 8 线 eMMC 传输
-- UHS-I 1.8 V 模式：不支持 4 线 SD 卡传输
 
 
 使用 SDMMC 主机驱动
diff --git a/docs/zh_CN/api-reference/peripherals/spi_flash/index.rst b/docs/zh_CN/api-reference/peripherals/spi_flash/index.rst
index 89e899569eb..56632c71a08 100644
--- a/docs/zh_CN/api-reference/peripherals/spi_flash/index.rst
+++ b/docs/zh_CN/api-reference/peripherals/spi_flash/index.rst
@@ -118,7 +118,7 @@ SPI flash 容量
 
 SPI flash 容量由引导加载程序镜像头部（烧录偏移量为 0x1000）的一个字段进行配置。
 
-默认情况下，引导程序被写入 flash 时，``esptool.py`` 会自动检测 SPI flash 容量，同时使用正确容量更新引导程序的头部。也可以在工程配置中设置 :ref:`CONFIG_ESPTOOLPY_FLASHSIZE`，生成固定的 flash 容量。
+默认情况下，引导加载程序被写入 flash 时，``esptool.py`` 会自动检测 SPI flash 容量，同时使用正确容量更新引导加载程序的头部。也可以在工程配置中设置 :ref:`CONFIG_ESPTOOLPY_FLASHSIZE`，生成固定的 flash 容量。
 
 如需在运行时覆盖已配置的 flash 容量，请配置 ``g_rom_flashchip`` 结构中的 ``chip_size``。``esp_flash_*`` 函数使用此容量（于软件和 ROM 中）进行边界检查。
 
diff --git a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
index 24b3f5843b9..691d4c75129 100644
--- a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
+++ b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
@@ -64,7 +64,7 @@
             .get_chip_caps = spi_flash_chip_eon_get_caps,
          };
 
-   - 也可以在示例 :example:`storage/custom_flash_driver` 中查看如何实现此功能。
+   - 也可以在示例 :example:`storage/custom_flash_driver` 中查看如何实现此功能。该示例演示了如何覆盖默认芯片驱动列表。
 
 4. 为 ``custom_chip_driver`` 组件编写一个新的 ``CMakeLists.txt`` 文件，其中包含额外的一行，添加了从 ``spi_flash`` 到 ``custom_chip_driver`` 的链接依赖项::
 
@@ -80,8 +80,3 @@
 5. ``linker.lf`` 用于在禁用缓存时，把要使用的每个芯片驱动程序都放入内部 RAM 中。详情请参阅 :doc:`/api-guides/linker-script-generation`。请确保此文件包含所有添加的源文件。
 
 6. 构建你的项目，将会看到新的 flash 驱动程序已投入使用。
-
-示例
-----
-
-参考 :example:`storage/custom_flash_driver`。
diff --git a/docs/zh_CN/api-reference/peripherals/spi_master.rst b/docs/zh_CN/api-reference/peripherals/spi_master.rst
index 9868ee66bae..764f7bc82a1 100644
--- a/docs/zh_CN/api-reference/peripherals/spi_master.rst
+++ b/docs/zh_CN/api-reference/peripherals/spi_master.rst
@@ -305,6 +305,14 @@ SPI 总线传输事务由五个阶段构成，详见下表（任意阶段均可
 
 若需连续发送专门的 SPI 传输事务以提高效率，可采用获取总线的方式。获取总线后，与其他设备间的传输事务（包括轮询传输事务或中断传输事务）将处于待处理状态，直到总线被释放。要获取和释放总线，请调用函数 :cpp:func:`spi_device_acquire_bus` 和 :cpp:func:`spi_device_release_bus`。
 
+.. only:: SOC_SPI_SUPPORT_SLEEP_RETENTION
+
+    睡眠保留
+    ^^^^^^^^
+
+    {IDF_TARGET_NAME} 支持在进入 **Light Sleep** 之前保留 SPI 寄存器中的内容，并在唤醒后恢复。即程序不需要在 **Light Sleep** 唤醒后重新配置 SPI。
+
+    该特性可以通过置位配置中的 :c:macro:`SPICOMMON_BUSFLAG_SLP_ALLOW_PD` 标志位启用。启用后驱动允许系统在 Light Sleep 时对 SPI 掉电，同时保存寄存器配置。它可以帮助降低轻度睡眠时的功耗，但需要花费一些额外的存储来保存寄存器的配置。
 
 使用驱动程序
 -----------------
diff --git a/docs/zh_CN/api-reference/peripherals/temp_sensor.rst b/docs/zh_CN/api-reference/peripherals/temp_sensor.rst
index bffe7b66943..a53aace2fbd 100644
--- a/docs/zh_CN/api-reference/peripherals/temp_sensor.rst
+++ b/docs/zh_CN/api-reference/peripherals/temp_sensor.rst
@@ -59,6 +59,7 @@
 
 - :cpp:member:`range_min`：所测量温度范围的最小值。
 - :cpp:member:`range_max`：所测量温度范围的最大值。
+- :cpp:member:`allow_pd` 配置驱动程序是否允许系统在睡眠模式下关闭外设电源。在进入睡眠之前，系统将备份温度传感器寄存器上下文，当系统退出睡眠模式时，这些上下文将被恢复。关闭外设可以节省更多功耗，但代价是消耗更多内存来保存寄存器上下文。你需要在功耗和内存消耗之间做权衡。此配置选项依赖于特定的硬件功能，如果在不支持的芯片上启用它，你将看到类似 ``not able to power down in light sleep`` 的错误消息。
 
 设置好温度范围后，将配置结构体传递给 :cpp:func:`temperature_sensor_install`，该函数将创建温度传感器模块并返回句柄。
 
diff --git a/docs/zh_CN/api-reference/peripherals/touch_element.rst b/docs/zh_CN/api-reference/peripherals/touch_element.rst
index 22c22ad58b7..277471e08ce 100644
--- a/docs/zh_CN/api-reference/peripherals/touch_element.rst
+++ b/docs/zh_CN/api-reference/peripherals/touch_element.rst
@@ -6,7 +6,11 @@
 概述
 --------
 
-触摸元件库是基于触摸传感器驱动设计的高度抽象的元件库，该库提供了统一且友好的软件接口，可以快速构建电容式触摸传感器的应用。有关触摸传感器驱动 API 的更多信息，请参阅 :doc:`../peripherals/touch_pad`。
+触摸元件库是基于触摸传感器驱动设计的高度抽象的元件库，该库提供了统一且友好的软件接口，可以快速构建电容式触摸传感器的应用。
+
+.. warning::
+
+    目前的触摸元件库仍然基于旧的触摸传感器驱动。如您不需要使用触摸元件库，请参考新的 :doc:`电容式触摸传感器 </api-reference/peripherals/cap_touch_sens>` 驱动。
 
 架构
 ^^^^^^^^^^^^
diff --git a/docs/zh_CN/api-reference/peripherals/touch_pad.rst b/docs/zh_CN/api-reference/peripherals/touch_pad.rst
index 4879ece09e6..b5a38a87396 100644
--- a/docs/zh_CN/api-reference/peripherals/touch_pad.rst
+++ b/docs/zh_CN/api-reference/peripherals/touch_pad.rst
@@ -5,6 +5,12 @@
 
 {IDF_TARGET_TOUCH_SENSOR_VERSION:default="v2", esp32="v1"}
 
+.. only:: esp32s2 or esp32s3
+
+    .. warning::
+
+        该文档所演示的 Touch 驱动已弃用, 请移步新文档查看最新的 Touch 驱动: :doc:`Capacitive Touch Sensor </api-reference/peripherals/cap_touch_sens>`.
+
 概述
 ------------
 
@@ -146,8 +152,6 @@
 
     该函数也可以用于检查触碰和释放触摸传感器时传感器读数变化范围，然后根据这些信息设定触摸传感器的触摸阈值。
 
-请参考应用示例 :example:`peripherals/touch_sensor/touch_sensor_{IDF_TARGET_TOUCH_SENSOR_VERSION}/touch_pad_read`，查看如何使用读取触摸传感器数据。
-
 测量方式
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
@@ -250,7 +254,7 @@
 
 也可以将硬件触摸监测连接至中断，详细介绍见下一章节。
 
-如果测量中存在噪声，且电容变化幅度较小，硬件触摸监测结果可能就不太理想。如需解决这一问题，不建议使用硬件监测或中断信号，建议在自己的应用程序中进行采样滤波，并执行触摸监测。请参考 :example:`peripherals/touch_sensor/touch_sensor_{IDF_TARGET_TOUCH_SENSOR_VERSION}/touch_pad_interrupt`，查看以上两种触摸监测的实现方式。
+如果测量中存在噪声，且电容变化幅度较小，硬件触摸监测结果可能就不太理想。如需解决这一问题，不建议使用硬件监测或中断信号，建议在自己的应用程序中进行采样滤波，并执行触摸监测。
 
 中断触发
 ^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -300,9 +304,9 @@
 
 .. only:: esp32s2 or esp32s3
 
-    - :example:`peripherals/touch_sensor/touch_sensor_v2/touch_pad_read` 演示了如何在 {IDF_TARGET_NAME} 上读取并显示电容触摸传感器的原始值，包括如何校准传感器以及监测触摸动作。
-    - :example:`peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt` 演示了如何设置 {IDF_TARGET_NAME} 的电容触摸板外设，使其在被触摸时触发中断，以及在需要更高触摸监测灵敏度的传感器设计中，如何通过软件来监测触摸事件。
+    .. warning::
 
+        使用老驱动的例程已移除，新驱动用法请参考 :example:`peripherals/touch_sensor/touch_sens_basic`。
 
 .. _touch_pad-api-reference:
 
@@ -321,4 +325,4 @@ GPIO 宏查找表
 2. ``TOUCH_PAD_GPIO4_CHANNEL`` 定义了 GPIO 4 的通道（即通道 0）。
 
 .. include-build-file:: inc/touch_sensor_channel.inc
-.. include-build-file:: inc/touch_sensor_types.inc
+.. include-build-file:: inc/touch_sensor_legacy_types.inc
diff --git a/docs/zh_CN/api-reference/peripherals/twai.rst b/docs/zh_CN/api-reference/peripherals/twai.rst
index b8c1af990a1..4bd78d2fe12 100644
--- a/docs/zh_CN/api-reference/peripherals/twai.rst
+++ b/docs/zh_CN/api-reference/peripherals/twai.rst
@@ -599,6 +599,14 @@ TWAI 驱动程序通过 :cpp:type:`twai_message_t` 结构体的不同位字段
 
 **自测示例：** :example:`peripherals/twai/twai_self_test` 演示了节点如何使用 TWAI 驱动程序的无应答模式和自接收请求，向自身传输 TWAI 消息。此示例可用于测试目标芯片与外部收发器之间的连接是否正常。
 
+.. only:: SOC_TWAI_SUPPORT_SLEEP_RETENTION
+
+    睡眠保留
+    ^^^^^^^^
+
+    {IDF_TARGET_NAME} 支持在进入 **Light Sleep** 之前保留 TWAI 寄存器中的内容，并在唤醒后恢复。即程序不需要在 **Light Sleep** 唤醒后重新配置 TWAI
+
+    该特性可以通过置位配置中的 :cpp:member:`twai_general_config_t::sleep_allow_pd` 标志位启用。启用后驱动允许系统在 Light Sleep 时对 TWAI 掉电，同时保存寄存器配置。它可以帮助降低轻度睡眠时的功耗，但需要花费一些额外的存储来保存寄存器的配置。
 
 .. ---------------------------- API Reference ----------------------------------
 
diff --git a/docs/zh_CN/api-reference/peripherals/usb_host.rst b/docs/zh_CN/api-reference/peripherals/usb_host.rst
index 7fb9a74b441..5a36b9bb089 100644
--- a/docs/zh_CN/api-reference/peripherals/usb_host.rst
+++ b/docs/zh_CN/api-reference/peripherals/usb_host.rst
@@ -18,7 +18,7 @@ USB 主机库（以下简称主机库）是 USB 主机栈的最底层，提供
 然而，由于以下的某些原因（但不仅限于此），有时你可能需要直接使用主机库：
 
 - 需要实现自定义主机 Class 驱动程序
-- 需要更低级别的抽象
+- 需要更低级别的 USB 主机 API
 
 特性和限制
 ^^^^^^^^^^^^^^^^^^^^^^
@@ -34,17 +34,23 @@ USB 主机库（以下简称主机库）是 USB 主机栈的最底层，提供
     - 支持多个 Class 驱动程序同时运行，即主机的多个客户端同时运行。
     - 单个设备可以由多个客户端同时使用，如复合设备。
     - 主机库及其底层主机栈不会在内部自动创建操作系统任务，任务数量完全由主机库接口的使用方式决定。一般来说，任务数量为 ``（运行中的主机 Class 驱动程序数量 + 1）``。
+    - 支持单个 Hub（启用选项 :ref:`CONFIG_USB_HOST_HUBS_SUPPORTED`）。
+    - 支持多个 Hub（启用选项 :ref:`CONFIG_USB_HOST_HUB_MULTI_LEVEL`）。
 
 目前，主机库及其底层主机栈存在以下限制：
 
 .. list::
 
-    - 仅支持单个设备，而主机库的 API 支持多设备。
     - 仅支持异步传输。
     - 仅支持使用发现的首个配置，尚不支持变更为其他配置。
     - 尚不支持传输超时。
     :esp32p4: - {IDF_TARGET_NAME} 包含两个 USB-OTG 外设：USB 2.0 OTG 高速和 USB 2.0 OTG 全速。目前仅支持高速实例。
-    :esp32p4: - {IDF_TARGET_NAME} 目前无法枚举低速设备。
+    - 外部 Hub 驱动：仅支持与上游端口速率相同的设备。（例如，低速设备无法通过全速外部 Hub 工作。）
+    - 外部 Hub 驱动：不支持远程唤醒功能（即使没有设备插入，外部 Hub 也处于工作状态）。
+    - 外部 Hub 驱动：不处理错误用例（尚未实现过流处理、初始化错误等功能）。
+    - 外部 Hub 驱动：不支持接口选择。驱动程序使用具有 Hub 类代码 (09h) 的第一个可用接口。
+    - 外部端口驱动：无下游端口去抖动机制（尚未实现）。
+    :esp32p4: - 外部 Hub 驱动：无事务转换层（当 Hub 连接到高速主机时，不支持全速/低速设备）。
 
 
 .. -------------------------------------------------- Architecture -----------------------------------------------------
@@ -97,7 +103,7 @@ USB 主机库（以下简称主机库）是 USB 主机栈的最底层，提供
 设备
 ^^^^^^^
 
-主机库隔离了客户端与设备处理的细节，包括连接、内存分配和枚举等，客户端只需提供已连接且已枚举的设备列表供选择。默认情况下，在枚举过程中，每个设备都会自动配置为使用找到的第一个配置，即通过获取配置描述符请求返回的第一个配置描述符。对于大多数标准设备，通常将第一个配置的 ``bConfigurationValue`` 设置为 ``1``。启用选项 :ref:`CONFIG_USB_HOST_ENABLE_ENUM_FILTER_CALLBACK` 后，可以选择不同的 ``bConfigurationValue``。获取更多详细信息，请参阅 `Multiple configuration Support_`。
+主机库隔离了客户端与设备处理的细节，包括连接、内存分配和枚举等，客户端只需提供已连接且已枚举的设备列表供选择。默认情况下，在枚举过程中，每个设备都会自动配置为使用找到的第一个配置，即通过获取配置描述符请求返回的第一个配置描述符。对于大多数标准设备，通常将第一个配置的 ``bConfigurationValue`` 设置为 ``1``。启用选项 :ref:`CONFIG_USB_HOST_ENABLE_ENUM_FILTER_CALLBACK` 后，可以选择不同的 ``bConfigurationValue``。获取更多详细信息，请参阅 `多项配置支持`_。
 
 只要不与相同接口通信，两个及以上的客户端可以同时与同一设备通信。然而，多个客户端同时与相同设备的默认端点（即 EP0）通信，将导致它们的控制传输序列化。
 
@@ -438,6 +444,44 @@ USB 设备可能是热插拔的，因此必须配置电源开关和设备连接
 * :ref:`CONFIG_USB_HOST_RESET_RECOVERY_MS` 用于配置重置恢复时间。
 * :ref:`CONFIG_USB_HOST_SET_ADDR_RECOVERY_MS` 用于配置 ``SetAddress()`` 恢复时间。
 
+下游端口配置
+^^^^^^^^^^^^
+
+当支持外部 Hub 功能时，可以为外部 Hub 端口配置多个参数。
+
+每个外部 Hub 都有一个 Hub 描述符，用于描述设备特性。
+
+.. note::
+
+    有关 Hub 描述符的详细信息，请参考 `USB 2.0 规范 <https://www.usb.org/document-library/usb-20-specification>`_ > 章节 11.23.2.1 *Hub Descriptor*。
+
+可以通过 Menuconfig 配置下游端口的可配置参数。
+
+* 对于在端口上电后稳定电源的自定义值（PwrOn2PwrGood 值），请参阅 :ref:`CONFIG_USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_MS`。
+* 对于复位恢复间隔，请参阅 :ref:`CONFIG_USB_HOST_EXT_PORT_RESET_RECOVERY_DELAY_MS`。
+
+.. note::
+
+    规范规定，对于没有电源开关的 Hub，PwrOn2PwrGood 必须设置为零。同时，对于某些设备，可以增加此值以提供额外的上电时间。如需启用此功能，请参考 :ref:`CONFIG_USB_HOST_EXT_PORT_CUSTOM_POWER_ON_DELAY_ENABLE`。
+
+主机通道
+"""""""""""""
+
+当启用外部 Hub 支持功能（:ref:`CONFIG_USB_HOST_HUBS_SUPPORTED`）时，主机通道的数量非常重要，因为每个下游设备都需要空闲通道。
+
+每个连接的设备需要不同数量的通道，而所需通道数则取决于设备类别（EP 数量）。
+
+对于 {IDF_TARGET_NAME}，支持的通道数量为 {OTG_NUM_HOST_CHAN}。
+
+.. note::
+
+    - 需要一个空闲通道来枚举设备。
+
+    - 需要 1 到 N（N 为 EP 数量）个空闲通道来占用接口。
+
+    - 如果所有的主机通道都已经被占用，则设备无法进行枚举，也无法获取接口。
+
+
 多项配置支持
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/docs/zh_CN/api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst b/docs/zh_CN/api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst
new file mode 100644
index 00000000000..6833910aa4b
--- /dev/null
+++ b/docs/zh_CN/api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst
@@ -0,0 +1 @@
+.. include:: ../../../../en/api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst
diff --git a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst
index a08e012377e..2fdb0d4c4ad 100644
--- a/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst
+++ b/docs/zh_CN/api-reference/protocols/esp_crt_bundle.rst
@@ -16,7 +16,7 @@ ESP x509 证书包 API 提供了一种简便的方法，帮助你安装自定义
 
 生成证书包时，你需选择：
 
-* 来自 Mozilla 的完整根证书包，包含超过 130 份证书。目前提供的证书包更新于 2024 年 3 月 11 日，星期一，15:25:27 (GMT)。
+* 来自 Mozilla 的完整根证书包，包含超过 130 份证书。目前提供的证书包更新于 2024 年 9 月 24 日，星期二，03:12:04 (GMT)。
 * 一组预先筛选的常用根证书。其中仅包含约 41 份证书，但根据 SSL 证书颁发机构统计数据，其绝对使用率约达到 90%，市场覆盖率约达 99%。
 
 此外，还可指定证书文件的路径或包含证书的目录，将其他证书添加到生成的证书包中。
diff --git a/docs/zh_CN/api-reference/protocols/esp_http_server.rst b/docs/zh_CN/api-reference/protocols/esp_http_server.rst
index baf90115a4f..4d899409181 100644
--- a/docs/zh_CN/api-reference/protocols/esp_http_server.rst
+++ b/docs/zh_CN/api-reference/protocols/esp_http_server.rst
@@ -10,109 +10,14 @@ HTTP Server 组件提供了在 ESP32 上运行轻量级 Web 服务器的功能
 
     * :cpp:func:`httpd_start`： 创建 HTTP 服务器的实例，根据具体的配置为其分配内存和资源，并返回该服务器实例的句柄。服务器使用了两个套接字，一个用来监听 HTTP 流量（TCP 类型），另一个用来处理控制信号（UDP 类型），它们在服务器的任务循环中轮流使用。通过向 ``httpd_start()`` 传递 ``httpd_config_t`` 结构体，可以在创建服务器实例时配置任务的优先级和堆栈的大小。TCP 流量被解析为 HTTP 请求，根据请求的 URI 来调用用户注册的处理程序，在处理程序中需要发送回 HTTP 响应数据包。
     * :cpp:func:`httpd_stop`： 根据传入的句柄停止服务器，并释放相关联的内存和资源。这是一个阻塞函数，首先给服务器任务发送停止信号，然后等待其终止。期间服务器任务会关闭所有已打开的连接，删除已注册的 URI 处理程序，并将所有会话的上下文数据重置为空。
-    * :cpp:func:`httpd_register_uri_handler`： 通过传入 ``httpd_uri_t`` 结构体类型的对象来注册 URI 处理程序。该结构体包含如下成员：``uri`` 名字，``method`` 类型（比如 ``HTTPD_GET/HTTPD_POST/HTTPD_PUT`` 等等）， ``esp_err_t *handler (httpd_req_t *req)`` 类型的函数指针，指向用户上下文数据的 ``user_ctx`` 指针。
+    * :cpp:func:`httpd_register_uri_handler`： 通过传入 ``httpd_uri_t`` 结构体类型的对象来注册 URI 处理程序。该结构体包含如下成员：``uri`` 名字，``method`` 类型（比如 ``HTTP_GET/HTTP_POST/HTTP_PUT`` 等等）， ``esp_err_t *handler (httpd_req_t *req)`` 类型的函数指针，指向用户上下文数据的 ``user_ctx`` 指针。
 
 应用示例
 --------
 
-    .. code-block:: c
-
-        /* URI 处理函数，在客户端发起 GET /uri 请求时被调用 */
-        esp_err_t get_handler(httpd_req_t *req)
-        {
-            /* 发送回简单的响应数据包 */
-            const char resp[] = "URI GET Response";
-            httpd_resp_send(req, resp, HTTPD_RESP_USE_STRLEN);
-            return ESP_OK;
-        }
-
-        /* URI 处理函数，在客户端发起 POST/uri 请求时被调用 */
-        esp_err_t post_handler(httpd_req_t *req)
-        {
-            /* 定义 HTTP POST 请求数据的目标缓存区
-             * httpd_req_recv() 只接收 char* 数据，但也可以是
-             * 任意二进制数据（需要类型转换）
-             * 对于字符串数据，null 终止符会被省略，
-             * content_len 会给出字符串的长度 */
-            char content[100];
-
-            /* 如果内容长度大于缓冲区则截断 */
-            size_t recv_size = MIN(req->content_len, sizeof(content));
-
-            int ret = httpd_req_recv(req, content, recv_size);
-            if (ret <= 0) {  /* 返回 0 表示连接已关闭 */
-                /* 检查是否超时 */
-                if (ret == HTTPD_SOCK_ERR_TIMEOUT) {
-                    /* 如果是超时，可以调用 httpd_req_recv() 重试
-                     * 简单起见，这里我们直接
-                     * 响应 HTTP 408（请求超时）错误给客户端 */
-                    httpd_resp_send_408(req);
-                }
-                /* 如果发生了错误，返回 ESP_FAIL 可以确保
-                 * 底层套接字被关闭 */
-                return ESP_FAIL;
-            }
-
-            /* 发送简单的响应数据包 */
-            const char resp[] = "URI POST Response";
-            httpd_resp_send(req, resp, HTTPD_RESP_USE_STRLEN);
-            return ESP_OK;
-        }
-
-        /* GET /uri 的 URI 处理结构 */
-        httpd_uri_t uri_get = {
-            .uri      = "/uri",
-            .method   = HTTP_GET,
-            .handler  = get_handler,
-            .user_ctx = NULL
-        };
-
-        /* POST/uri 的 URI 处理结构 */
-        httpd_uri_t uri_post = {
-            .uri      = "/uri",
-            .method   = HTTP_POST,
-            .handler  = post_handler,
-            .user_ctx = NULL
-        };
-
-        /* 启动 Web 服务器的函数 */
-        httpd_handle_t start_webserver(void)
-        {
-            /* 生成默认的配置参数 */
-            httpd_config_t config = HTTPD_DEFAULT_CONFIG();
-
-            /* 置空 esp_http_server 的实例句柄 */
-            httpd_handle_t server = NULL;
-
-            /* 启动 httpd server */
-            if (httpd_start(&server, &config) == ESP_OK) {
-                /* 注册 URI 处理程序 */
-                httpd_register_uri_handler(server, &uri_get);
-                httpd_register_uri_handler(server, &uri_post);
-            }
-            /* 如果服务器启动失败，返回的句柄是 NULL */
-            return server;
-        }
-
-        /* 停止 Web 服务器的函数 */
-        void stop_webserver(httpd_handle_t server)
-        {
-            if (server) {
-                /* 停止 httpd server */
-                httpd_stop(server);
-            }
-        }
-
-简单 HTTP 服务器示例
-^^^^^^^^^^^^^^^^^^^^
-
-:example:`protocols/http_server/simple` 演示了如何处理任意内容长度的数据，读取请求头和 URL 查询参数，并设置响应头。
-
-高级测试示例
-^^^^^^^^^^^^
-
-:example:`protocols/http_server/advanced_tests` 演示了如何使用 HTTP 服务器进行高级测试。
+- :example:`protocols/http_server/simple` 演示了如何处理任意内容长度的数据，读取请求头和 URL 查询参数，并设置响应头。
 
+- :example:`protocols/http_server/advanced_tests` 演示了如何使用 HTTP 服务器进行高级测试。
 
 HTTP 长连接
 -----------
diff --git a/docs/zh_CN/api-reference/protocols/icmp_echo.rst b/docs/zh_CN/api-reference/protocols/icmp_echo.rst
index 87dea76943a..38bb987ac05 100644
--- a/docs/zh_CN/api-reference/protocols/icmp_echo.rst
+++ b/docs/zh_CN/api-reference/protocols/icmp_echo.rst
@@ -112,7 +112,7 @@ IoT 设备通常需要检查远程服务器是否可用。如果服务器离线
 应用示例
 ----------
 
-ICMP echo 示例： :example:`protocols/icmp_echo`
+- :example:`protocols/icmp_echo` 演示了如何实现一个简单的 ping 命令行工具，使用 ICMP 回显请求数据包测试远程主机在 IP 网络上的可达性。
 
 API 参考
 --------------
diff --git a/docs/zh_CN/api-reference/protocols/mbedtls.rst b/docs/zh_CN/api-reference/protocols/mbedtls.rst
index 2ed68754969..f109476f868 100644
--- a/docs/zh_CN/api-reference/protocols/mbedtls.rst
+++ b/docs/zh_CN/api-reference/protocols/mbedtls.rst
@@ -118,5 +118,5 @@ ESP-IDF 中的示例使用 :doc:`/api-reference/protocols/esp_tls`，为访问
 在 ``Component Config -> mbedTLS`` 中，有多个 Mbed TLS 功能默认为启用状态。如果不需要这些功能，可将其禁用以减小固件大小。要了解更多信息，请参考 :ref:`Minimizing Binary Size <minimizing_binary_mbedtls>` 文档。
 
 
-.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.1/
+.. _`API Reference`: https://mbed-tls.readthedocs.io/projects/api/en/v3.6.2/
 .. _`Knowledge Base`: https://mbed-tls.readthedocs.io/en/latest/kb/
diff --git a/docs/zh_CN/api-reference/protocols/modbus.rst b/docs/zh_CN/api-reference/protocols/modbus.rst
index 3d88cbcfba8..d63d673dded 100644
--- a/docs/zh_CN/api-reference/protocols/modbus.rst
+++ b/docs/zh_CN/api-reference/protocols/modbus.rst
@@ -1,5 +1,6 @@
 ESP-Modbus
 ==========
+
 :link_to_translation:`en:[English]`
 
 乐鑫的 ESP-Modbus 库 (esp-modbus) 支持基于 RS485、Wi-Fi 和以太网接口的 Modbus 通信。
@@ -8,27 +9,28 @@ ESP-Modbus
 * `GitHub 上的 ESP-Modbus 组件 <https://github.com/espressif/esp-modbus>`__
 
 托管文档
---------------------
+--------
 
 相应文档请参阅：
 
 * `ESP-Modbus 文档 <https://docs.espressif.com/projects/esp-modbus>`__
 
 应用示例
--------------------
+--------
 
 以下示例分别介绍了 ESP-Modbus 库的串行端口、TCP 端口的从机和主机实现。
 
-- :example:`protocols/modbus/serial/mb_slave`
-- :example:`protocols/modbus/serial/mb_master`
-- :example:`protocols/modbus/tcp/mb_tcp_slave`
-- :example:`protocols/modbus/tcp/mb_tcp_master`
+- :example:`protocols/modbus/serial/mb_slave` 演示了如何使用 {IDF_TARGET_NAME} 作为 Modbus 串行从设备，通过 esp-modbus 栈，使外部 Modbus 主机能够使用 Modbus 协议读取和写入设备参数。
+
+- :example:`protocols/modbus/serial/mb_master` 演示了如何在 {IDF_TARGET_NAME} 上使用 esp-modbus 栈端口作为 Modbus 串行主设备，读取和写入 Modbus 网络中从设备的值。
+
+- :example:`protocols/modbus/tcp/mb_tcp_slave` 演示了 esp-modbus TCP 从设备栈端口，允许外部 Modbus 主机通过 Modbus 协议读取和写入设备参数。
+
+- :example:`protocols/modbus/tcp/mb_tcp_master` 演示了如何在 {IDF_TARGET_NAME} 上使用 esp-modbus 栈端口作为 Modbus TCP 主设备，读取和写入 Modbus 网络中从设备的值。
 
 详情请参阅具体示例的 ``README.md`` 。
 
 协议参考
--------------------
+--------
 
     -  Modbus 组织与规范协议请参阅 `The Modbus Organization <https://modbus.org/specs.php>`_。
-
-
diff --git a/docs/zh_CN/api-reference/protocols/mqtt.rst b/docs/zh_CN/api-reference/protocols/mqtt.rst
index 9365dfe850a..7ad56ec21e2 100644
--- a/docs/zh_CN/api-reference/protocols/mqtt.rst
+++ b/docs/zh_CN/api-reference/protocols/mqtt.rst
@@ -21,14 +21,23 @@ ESP-MQTT 是 `MQTT <https://mqtt.org/>`__ 协议客户端的实现，MQTT 是一
 应用示例
 -------------------
 
-   * :example:`protocols/mqtt/tcp`：基于 TCP 的 MQTT，默认端口 1883
-   * :example:`protocols/mqtt/ssl`：基于 TLS 的 MQTT，默认端口 8883
-   * :example:`protocols/mqtt/ssl_ds`：基于 TLS 的 MQTT，使用数字签名外设进行身份验证，默认端口 8883
-   * :example:`protocols/mqtt/ssl_mutual_auth`：基于 TLS 的 MQTT，使用证书进行身份验证，默认端口 8883
-   * :example:`protocols/mqtt/ssl_psk`：基于 TLS 的 MQTT，使用预共享密钥进行身份验证，默认端口 8883
-   * :example:`protocols/mqtt/ws`：基于 WebSocket 的 MQTT，默认端口 80
-   * :example:`protocols/mqtt/wss`：基于 WebSocket Secure 的 MQTT，默认端口 443
-   * :example:`protocols/mqtt5`: 使用 ESP-MQTT 库连接 MQTT v5.0 的服务器
+   - :example:`protocols/mqtt/tcp` 演示了如何通过 TCP 实现 MQTT 通信（默认端口 1883）。
+
+   - :example:`protocols/mqtt/ssl` 演示了如何使用 SSL 传输来实现基于 TLS 的 MQTT 通信（默认端口 8883）。
+
+   - :example:`protocols/mqtt/ssl_ds` 演示了如何使用数字签名外设进行身份验证，以实现基于 TLS 的 MQTT 通信（默认端口 8883）。
+
+   - :example:`protocols/mqtt/ssl_mutual_auth` 演示了如何使用证书进行身份验证实现 MQTT 通信（默认端口 8883）。
+
+   - :example:`protocols/mqtt/ssl_psk` 演示了如何使用预共享密钥进行身份验证，以实现基于 TLS 的 MQTT 通信（默认端口 8883）。
+
+   - :example:`protocols/mqtt/ws` 演示了如何通过 WebSocket 实现 MQTT 通信（默认端口 80）。
+
+   - :example:`protocols/mqtt/wss` 演示了如何通过 WebSocket Secure 实现 MQTT 通信（默认端口 443）。
+
+   - :example:`protocols/mqtt5` 演示了如何使用 ESP-MQTT 库通过 MQTT v5.0 连接到代理。
+
+   - :example:`protocols/mqtt/custom_outbox` 演示了如何自定义 ESP-MQTT 库中的 outbox。
 
 MQTT 消息重传
 --------------------------
diff --git a/docs/zh_CN/api-reference/storage/fatfs.rst b/docs/zh_CN/api-reference/storage/fatfs.rst
index 65f281bd790..a5d7e6e8b2b 100644
--- a/docs/zh_CN/api-reference/storage/fatfs.rst
+++ b/docs/zh_CN/api-reference/storage/fatfs.rst
@@ -99,7 +99,7 @@ FatFs 分区生成器
 
 该生成器可以在主机上创建文件系统镜像，并用指定的主机文件夹内容对其进行填充。
 
-该脚本是建立在分区生成器的基础上 (:component_file:`fatfsgen.py<fatfs/fatfsgen.py>`)，目前除了可以生成分区外，也可以初始化磨损均衡。
+该脚本是建立在分区生成器的基础上 (:component_file:`fatfsgen.py<fatfs/fatfsgen.py>`)，目前除了可以生成分区外，也可以初始化损耗均衡。
 
 目前的最新版本支持短文件名、长文件名、FAT12 和 FAT16。长文件名的上限是 255 个字符，文件名中可以包含多个 ``.`` 字符以及其他字符，如 ``+``、``,``、``;``、``=``、``[`` and ``]`` 等。
 
@@ -112,18 +112,18 @@ FatFs 分区生成器
 
     fatfs_create_spiflash_image(<partition> <base_dir> [FLASH_IN_PROJECT])
 
-如果不希望在生成分区时使用磨损均衡，可以使用 ``fatfs_create_rawflash_image``::
+如果不希望在生成分区时使用损耗均衡，可以使用 ``fatfs_create_rawflash_image``::
 
     fatfs_create_rawflash_image(<partition> <base_dir> [FLASH_IN_PROJECT])
 
 ``fatfs_create_spiflash_image`` 以及 ``fatfs_create_rawflash_image`` 必须从项目的 CMakeLists.txt 中调用。
 
-如果决定使用 ``fatfs_create_rawflash_image`` （不支持磨损均衡），请注意它仅支持在设备中以只读模式安装。
+如果决定使用 ``fatfs_create_rawflash_image`` （不支持损耗均衡），请注意它仅支持在设备中以只读模式安装。
 
 
 该函数的参数如下：
 
-#. partition - 分区的名称，需要在分区表中定义（如 :example_file:`storage/fatfsgen/partitions_example.csv`）。
+#. partition - 分区的名称，需要在分区表中定义（如 :example_file:`storage/fatfs/fatfsgen/partitions_example.csv`）。
 
 #. base_dir - 目录名称，该目录会被编码为 FatFs 分区，也可以选择将其被烧录进设备。但注意必须在分区表中指定合适的分区大小。
 
@@ -139,7 +139,8 @@ FatFs 分区生成器
 
 没有指定 FLASH_IN_PROJECT 时也可以生成分区镜像，但是用户需要使用 ``esptool.py`` 或自定义的构建系统目标对其手动烧录。
 
-相关示例请查看 :example:`storage/fatfsgen`。
+相关示例请查看 :example:`storage/fatfs/fatfsgen`。
+
 
 .. _fatfs-partition-analyzer:
 
@@ -156,6 +157,40 @@ FatFs 分区分析器
 
 生成文件夹结构之前，参数 --verbose 将根据 FatFs 镜像的引导扇区在终端打印详细信息。
 
+FATFS 最小分区大小及限制
+------------------------
+
+FATFS 组件支持 FAT12、FAT16 和 FAT32 文件系统类型。文件系统类型取决于卷上簇的数量（簇数通过数据扇区数量除以每簇包含的扇区数计算得出）。最小分区大小由分配给 FAT 表、根目录和数据簇的扇区数量决定。
+
+* 对于 4096 字节的扇区，启用损耗均衡的 FAT 分区大小最小支持 32 KB。对于 512 字节的扇区，最小分区大小取决于损耗均衡的配置：性能模式下，最小支持 20 KB，安全模式下最小支持 28 KB（需要额外的 2 个扇区）。
+* 启用了损耗均衡的分区会预留 4 个扇区用于损耗均衡操作。此外，FATFS 本身也会使用 4 个扇区，分别为 1 个保留扇区、1 个 FAT 扇区、1 个根目录扇区和 1 个数据扇区。
+* 增加分区大小将分配更多的数据扇区，提供更大的存储空间。
+* 对小于 528 KB 的分区，将分配 1 个根目录扇区；对于更大的分区，将分配 4 个根目录扇区。
+* 默认会创建两个 FAT 扇区，因此分区大小会增加一个扇区来容纳这个额外的 FAT 扇区。如要启用单个 FAT 扇区，可以在 `struct esp_vfs_fat_mount_config_t` 中（参见 :component_file:`fatfs/vfs/esp_vfs_fat.h`）设置 `use_one_fat` 选项。启用此选项后，最小分区大小可减少至 32 KB。
+* 计算损耗均衡分区大小的一般公式为::
+
+    partition_size = 损耗均衡扇区数 * FLASH_SEC_SIZE + FATFS 分区扇区数量 * FAT_SEC_SIZE
+
+  其中：
+
+  - 损耗均衡扇区数固定为 4 个
+  - FLASH_SEC_SIZE 为 4096 字节
+  - FATFS 分区扇区包括：1 个保留扇区 + FAT 扇区 + 根目录扇区 + 数据扇区
+  - FAT_SEC_SIZE 根据不同的配置，可以是 512 字节或 4096 字节
+
+* 对于未启用损耗均衡、扇区大小为 512 字节的只读分区，最小分区大小可减少至 2 KB。
+
+更多详情请参考 :doc:`文件系统注意事项 <../../api-guides/file-system-considerations>`。
+
+应用示例
+-----------------
+
+- :example:`storage/fatfs/getting_started` 演示了如何使用 FatFS 在 SPI flash 上存储永久数据的基本设置，包括挂载文件系统、打开文件、执行基本的读写操作以及卸载文件系统。
+
+- :example:`storage/fatfs/fs_operations` 演示了更全面的 FatFS 操作，包括读取和写入文件、创建、移动和删除文件及目录，以及检查文件详细信息。
+
+- :example:`storage/fatfs/ext_flash` 演示了如何操作使用 FatFS 格式化的外部 SPI flash，包括初始化 SPI 总线、配置 flash、将其注册为分区以及执行读写操作。
+
 高级 API 参考
 ------------------------
 
diff --git a/docs/zh_CN/api-reference/storage/fatfsgen.rst b/docs/zh_CN/api-reference/storage/fatfsgen.rst
index af83bcba295..e45b21c765a 100644
--- a/docs/zh_CN/api-reference/storage/fatfsgen.rst
+++ b/docs/zh_CN/api-reference/storage/fatfsgen.rst
@@ -219,3 +219,8 @@ FAT 文件系统中的日期和时间
 ESP-IDF 使用的 FAT 文件系统协议不保留芯片介质上的日期或时间，因此，从设备中提取的所有映像都具有相同的默认时间戳，这个时间戳会应用到所有 FAT 相关的日期和时间字段上，包括创建、最后修改时间戳，以及创建、最后修改和最后访问日期。
 
 SFN 条目中有几个描述时间的字段，如 **DIR_CrtTime** 和 **DIR_WrtTime**。ESP-IDF 的 FAT 实现过程会忽略一些字段（参见文件 ``entry.py``），然而 **DIR_WrtTime** 和 **DIR_WrtDate** 字段的更改会保留在芯片中。时间和数据条目都是 16 位的，其中时间粒度为 2 秒。
+
+应用示例
+---------------
+
+- :example:`storage/fatfs/fatfsgen` 演示了如何在构建过程中使用 FatFS 分区生成工具从主机文件夹自动创建 FatFS 镜像。
diff --git a/docs/zh_CN/api-reference/storage/index.rst b/docs/zh_CN/api-reference/storage/index.rst
index 0687d98c054..3b71db1be00 100644
--- a/docs/zh_CN/api-reference/storage/index.rst
+++ b/docs/zh_CN/api-reference/storage/index.rst
@@ -37,44 +37,76 @@
    wear-levelling
    storage-security.rst
 
+示例
+----
+
 .. list-table:: 存储 API 相关例程
     :widths: 25 75
     :header-rows: 0
 
     * - **例程**
       - **描述**
-    * - :doc:`fatfs`
-      -
-    * - :example:`wear_leveling <storage/wear_levelling>`
-      - 演示了如何在内部 flash 上使用 FATFS 磨损均衡。
-    * - :example:`ext_flash_fatfs <storage/ext_flash_fatfs>`
-      - 演示了如何在外部 flash 上使用 FATFS 磨损均衡。
-    * - :example:`fatfsgen <storage/fatfsgen>`
-      - 演示了在主机计算机上使用 Python 工具生成 FATFS 镜像的功能。
-    * - :doc:`nvs_flash`
-      -
     * - :example:`nvs_rw_blob <storage/nvs_rw_blob>`
       - 演示了如何在 NVS flash 中使用 C 语言 API 读写 blob 数据类型。
     * - :example:`nvs_rw_value <storage/nvs_rw_value>`
       - 演示了如何在 NVS flash 中使用 C 语言 API 读写整数数据类型。
-    * - :example:`nvs_rw_value_cxx <storage/nvs_rw_value_cxx>`
+    * - :example:`nvs_rw_value <storage/nvs_rw_value>`
       - 演示了如何在 NVS flash 中使用 C++ 语言 API 读写整数数据类型。
     * - :example:`nvsgen <storage/nvsgen>`
       - 演示了如何使用基于 Python 的 NVS 镜像生成工具，根据 CSV 文件内容创建 NVS 分区镜像。
-    * - :doc:`spiffs`
-      -
+
+.. list-table:: 常用文件系统 API
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **代码示例**
+      - **描述**
+    * - :example:`fatfs/getting_started <storage/fatfs/getting_started>`
+      - 演示了如何使用 FATFS 库在内部 flash 上应用标准文件 API (stdio.h)。
+    * - :example:`fatfs/fs_operations <storage/fatfs/fs_operations>`
+      - 演示了如何使用 POSIX API 进行文件系统操作，如移动、删除和重命名文件等。
+
+.. list-table:: FATFS API 示例
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **代码示例**
+      - **描述**
+    * - :example:`fatfsgen <storage/fatfs/fatfsgen>`
+      - 演示了在主机上使用 Python 工具生成 FATFS 镜像的相关功能。
+    * - :example:`ext_flash_fatfs <storage/fatfs/ext_flash>`
+      - 演示了在外部 flash 上使用带有磨损均衡功能的 FATFS。
+    * - :example:`wear_leveling <storage/wear_levelling>`
+      - 演示了在内部 flash 上使用带有磨损均衡功能的 FATFS。
+
+.. list-table:: SPIFFS API 示例
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **代码示例**
+      - **描述**
     * - :example:`spiffs <storage/spiffs>`
       - 演示了如何使用 SPIFFS API 初始化文件系统，并使用 POSIX 函数处理文件。
     * - :example:`spiffsgen <storage/spiffsgen>`
       - 演示了在主机计算机上使用 Python 工具生成 SPIFFS 镜像的功能。
-    * - :doc:`partition`
-      -
+
+.. list-table:: 分区 API 示例
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **代码示例**
+      - **描述**
     * - :example:`partition_api <storage/partition_api>`
       - 介绍了用于查找特定分区、执行基本 I/O 操作以及通过 CPU 内存映射使用分区的 API 函数。
     * - :example:`parttool <storage/parttool>`
       - 演示了在主机计算机上使用 Python 工具生成分区镜像的功能。
-    * - :doc:`vfs`
-      -
+
+.. list-table:: VFS 相关示例
+    :widths: 25 75
+    :header-rows: 0
+
+    * - **代码示例**
+      - **描述**
     * - :example:`littlefs <storage/littlefs>`
       - 演示了如何使用 LittleFS 组件初始化文件系统，并使用 POSIX 函数处理文件。
     * - :example:`semihost_vfs <storage/semihost_vfs>`
diff --git a/docs/zh_CN/api-reference/storage/nvs_encryption.rst b/docs/zh_CN/api-reference/storage/nvs_encryption.rst
index f0565d02de4..13c3bb59d30 100644
--- a/docs/zh_CN/api-reference/storage/nvs_encryption.rst
+++ b/docs/zh_CN/api-reference/storage/nvs_encryption.rst
@@ -98,7 +98,7 @@ NVS 密钥分区
             # "Active security features detected, erasing flash is disabled as a safety measure.  Use --force to override ..."
             parttool.py --esptool-erase-args=force --esptool-write-args encrypt --port PORT --partition-table-file=PARTITION_TABLE_FILE --partition-table-offset PARTITION_TABLE_OFFSET write_partition --partition-name="name of nvs_key partition" --input NVS_KEY_PARTITION_FILE
 
-由于密钥分区被标记为 ``encrypted``，且 :doc:`../../security/flash-encryption` 已启用，引导程序会在首次启动时使用 flash 加密密钥对此分区进行加密。
+由于密钥分区被标记为 ``encrypted``，且 :doc:`../../security/flash-encryption` 已启用，引导加载程序会在首次启动时使用 flash 加密密钥对此分区进行加密。
 
 一个应用程序可以使用不同的密钥对不同的 NVS 分区进行加密，从而拥有多个密钥分区。应用程序应为加密或解密操作提供正确的密钥分区和密钥信息。
 
diff --git a/docs/zh_CN/api-reference/storage/partition.rst b/docs/zh_CN/api-reference/storage/partition.rst
index 4a1a4a6269d..eafe918215e 100644
--- a/docs/zh_CN/api-reference/storage/partition.rst
+++ b/docs/zh_CN/api-reference/storage/partition.rst
@@ -13,7 +13,7 @@
 分区表 API
 -------------------
 
-ESP-IDF 工程使用分区表保存 SPI flash 各区信息，包括引导程序、各种应用程序二进制文件、数据及文件系统等。请参阅 :doc:`/api-guides/partition-tables`，查看详细信息。
+ESP-IDF 工程使用分区表保存 SPI flash 各区信息，包括引导加载程序、各种应用程序二进制文件、数据及文件系统等。请参阅 :doc:`/api-guides/partition-tables`，查看详细信息。
 
 该组件在 ``esp_partition.h`` 中声明了一些 API 函数，用以枚举在分区表中找到的分区，并对这些分区执行操作：
 
@@ -24,9 +24,19 @@ ESP-IDF 工程使用分区表保存 SPI flash 各区信息，包括引导程序
 - :cpp:func:`esp_partition_find_first`：返回描述 :cpp:func:`esp_partition_find` 中找到的第一个分区的结构；
 - :cpp:func:`esp_partition_read`、:cpp:func:`esp_partition_write` 和 :cpp:func:`esp_partition_erase_range` 等同于 :cpp:func:`esp_flash_read`、:cpp:func:`esp_flash_write` 和 :cpp:func:`esp_flash_erase_region`，但在分区边界内执行。
 
+应用示例
+-------------
 
-另请参考
-------------
+- :example:`storage/partition_api/partition_ops` 演示了如何对分区表执行读、写和擦除操作。
+
+- :example:`storage/parttool` 演示了如何使用分区工具执行读、写、擦除分区、检索分区信息和转储整个分区表等操作。
+
+- :example:`storage/partition_api/partition_find` 演示了如何搜索分区表，并根据分区类型、子类型和标签/名称等约束条件返回匹配的分区。
+
+- :example:`storage/partition_api/partition_mmap` 演示了如何配置 MMU，将分区映射到内存地址空间以进行读操作，并验证写入和读取的数据。
+
+其他资源
+-------------
 
 - :doc:`../../api-guides/partition-tables`
 - :doc:`../system/ota` 提供了高层 API 用于更新存储在 flash 中的 app 固件。
diff --git a/docs/zh_CN/api-reference/storage/sdmmc.rst b/docs/zh_CN/api-reference/storage/sdmmc.rst
index e870f7e9530..fa23ff479ae 100644
--- a/docs/zh_CN/api-reference/storage/sdmmc.rst
+++ b/docs/zh_CN/api-reference/storage/sdmmc.rst
@@ -32,7 +32,13 @@ SD/SDIO/MMC 驱动支持 SD 存储器、SDIO 卡和 eMMC 芯片。这是一个
 应用示例
 -------------------
 
-ESP-IDF :example:`storage/sd_card` 目录下提供了 SDMMC 驱动与 FatFs 库组合使用的示例，演示了先初始化卡，然后使用 POSIX 和 C 库 API 向卡读写数据。请参考示例目录下 README.md 文件，查看更多详细信息。
+.. list::
+
+    :SOC_SDMMC_HOST_SUPPORTED: - :example:`storage/sd_card/sdmmc` 演示了如何通过 SDMMC 接口操作使用 FatFS 文件系统格式化的 SD 卡。
+
+    :SOC_SDMMC_HOST_SUPPORTED: - :example:`storage/emmc` 演示了如何通过 SDMMC 接口操作使用 FatFS 文件系统格式化的 eMMC 芯片。
+
+    :SOC_GPSPI_SUPPORTED: - :example:`storage/sd_card/sdspi` 演示了如何通过 SPI 接口操作使用 FatFS 文件系统格式化的 SD 卡。
 
 协议层 API
 ------------------
diff --git a/docs/zh_CN/api-reference/storage/spiffs.rst b/docs/zh_CN/api-reference/storage/spiffs.rst
index 76a61ef9dea..da68b7a6703 100644
--- a/docs/zh_CN/api-reference/storage/spiffs.rst
+++ b/docs/zh_CN/api-reference/storage/spiffs.rst
@@ -65,7 +65,7 @@ SPIFFS 是一个用于 SPI NOR flash 设备的嵌入式文件系统，支持磨
 
     spiffs_create_partition_image(my_spiffs_partition my_folder DEPENDS dep)
 
-请参考 :example:`storage/spiffsgen`，查看示例。
+请参考 :example:`storage/spiffsgen`，查看示例。该示例演示了如何使用 SPIFFS 镜像生成工具在构建过程中自动从主机文件夹创建 SPIFFS 镜像。
 
 ``mkspiffs``
 ^^^^^^^^^^^^
diff --git a/docs/zh_CN/api-reference/storage/vfs.rst b/docs/zh_CN/api-reference/storage/vfs.rst
index ff633c189c1..cdd0a7a0a7e 100644
--- a/docs/zh_CN/api-reference/storage/vfs.rst
+++ b/docs/zh_CN/api-reference/storage/vfs.rst
@@ -39,34 +39,34 @@ VFS 组件支持 C 库函数（如 fopen 和 fprintf 等）与文件系统 (FS)
 
     ssize_t myfs_write(int fd, const void * data, size_t size);
 
-    // In definition of esp_vfs_t:
+    // 在 esp_vfs_t 的定义中：
         .flags = ESP_VFS_FLAG_DEFAULT,
         .write = &myfs_write,
-    // ... other members initialized
+    // ... 其他成员已初始化
 
-    // When registering FS, context pointer (third argument) is NULL:
+    // 注册文件系统时，上下文指针（第三个参数）为 NULL：
     ESP_ERROR_CHECK(esp_vfs_register("/data", &myfs, NULL));
 
 示例 2：声明 API 函数时需要一个额外的上下文指针作为参数，即可支持多个 FS 驱动程序实例，此时使用 ``write_p`` ::
 
     ssize_t myfs_write(myfs_t* fs, int fd, const void * data, size_t size);
 
-    // In definition of esp_vfs_t:
+    // 在 esp_vfs_t 的定义中：
         .flags = ESP_VFS_FLAG_CONTEXT_PTR,
         .write_p = &myfs_write,
-    // ... other members initialized
+    // ... 其他成员已初始化
 
-    // When registering FS, pass the FS context pointer into the third argument
-    // (hypothetical myfs_mount function is used for illustrative purposes)
+    // 注册文件系统时，将文件系统上下文指针传递给第三个参数
+    // （使用假设的 myfs_mount 函数进行示例说明）
     myfs_t* myfs_inst1 = myfs_mount(partition1->offset, partition1->size);
     ESP_ERROR_CHECK(esp_vfs_register("/data1", &myfs, myfs_inst1));
 
-    // Can register another instance:
+    // 可以注册另一个实例：
     myfs_t* myfs_inst2 = myfs_mount(partition2->offset, partition2->size);
     ESP_ERROR_CHECK(esp_vfs_register("/data2", &myfs, myfs_inst2));
 
 同步输入/输出多路复用
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^
 
 VFS 组件支持通过 :cpp:func:`select` 进行同步输入/输出多路复用，其实现方式如下：
 
@@ -91,16 +91,17 @@ VFS 组件支持通过 :cpp:func:`select` 进行同步输入/输出多路复用
 
 ::
 
-    // In definition of esp_vfs_t:
+    // 在 esp_vfs_t 的定义中：
         .start_select = &uart_start_select,
         .end_select = &uart_end_select,
-    // ... other members initialized
+    // ... 其他成员已初始化
 
 调用 :cpp:func:`start_select` 函数可以设置环境，检测指定 VFS 驱动的文件描述符读取/写入/错误条件。
 
 调用 :cpp:func:`end_select` 函数可以终止/取消初始化/释放由 :cpp:func:`start_select` 设置的环境。
 
 .. note::
+
     在少数情况下，在调用 :cpp:func:`end_select` 之前可能并没有调用过 :cpp:func:`start_select`。因此 :cpp:func:`end_select` 的实现必须在该情况下返回错误而不能崩溃。
 
 如需获取更多信息，请参考 :component_file:`esp_driver_uart/src/uart_vfs.c` 中 UART 外设的 VFS 驱动，尤其是函数 :cpp:func:`uart_vfs_dev_register`、:cpp:func:`uart_start_select` 和 :cpp:func:`uart_end_select`。
@@ -122,12 +123,12 @@ VFS 组件支持通过 :cpp:func:`select` 进行同步输入/输出多路复用
 
 ::
 
-    // In definition of esp_vfs_t:
+    // 在 esp_vfs_t 的定义中：
         .socket_select = &lwip_select,
         .get_socket_select_semaphore = &lwip_get_socket_select_semaphore,
         .stop_socket_select = &lwip_stop_socket_select,
         .stop_socket_select_isr = &lwip_stop_socket_select_isr,
-    // ... other members initialized
+    // ... 其他成员已初始化
 
 函数 :cpp:func:`socket_select` 是套接字驱动对 :cpp:func:`select` 的内部实现。该函数只对套接字 VFS 驱动的文件描述符起作用。
 
@@ -142,6 +143,7 @@ VFS 组件支持通过 :cpp:func:`select` 进行同步输入/输出多路复用
 .. note::
 
     如果 :cpp:func:`select` 用于套接字文件描述符，可以禁用 :ref:`CONFIG_VFS_SUPPORT_SELECT` 选项来减少代码量，提高性能。
+
     不要在 :cpp:func:`select` 调用过程中更改套接字驱动，否则会出现一些未定义行为。
 
 路径
@@ -192,6 +194,17 @@ VFS 对文件路径长度没有限制，但文件系统路径前缀受 ``ESP_VFS
 
 注意，用 ``EFD_SUPPORT_ISR`` 创建 eventfd 将导致在读取、写入文件时，以及在设置这个文件的 ``select()`` 开始和结束时，暂时禁用中断。
 
+
+精简版 VFS
+------------
+
+为尽量减少 RAM 使用，提供了另一版本的 :cpp:func:`esp_vfs_register` 函数，即 :cpp:func:`esp_vfs_register_fs`。这个版本的函数接受 :cpp:class:`esp_vfs_fs_ops_t` 而不是 :cpp:class:`esp_vfs_t`，并且还接受按位或 (OR-ed) 的标志参数。与 :cpp:func:`esp_vfs_register` 函数不同，只要在调用时提供 ``ESP_VFS_FLAG_STATIC`` 标志，该函数就可以处理静态分配的结构体。
+
+:cpp:class:`esp_vfs_fs_ops_t` 根据功能（如，目录操作、选择支持、termios 支持等）被拆分为不同的结构体。主结构体包含基本功能，如 ``read``、``write`` 等，并包含指向特定功能结构体的指针。这些指针可以设置为 ``NULL``，表示不支持该结构体中提供的所有功能，从而减少所需内存。
+
+在内部，VFS 组件使用的是该版本的 API，并在注册时通过额外步骤将 :cpp:class:`esp_vfs_t` 转换为 :cpp:class:`esp_vfs_fs_ops_t`。
+
+
 常用 VFS 设备
 -------------
 
@@ -208,11 +221,15 @@ IDF 定义了多个可供应用程序使用的 VFS 设备。这些设备包括
 
 - :example:`system/select` 演示了如何使用 ``select()`` 函数进行同步 I/O 多路复用，使用 UART 和套接字文件描述符，并将二者配置为回环模式，以接收来自其他任务发送的消息。
 
+- :example:`storage/semihost_vfs` 演示了如何使用半托管 VFS 驱动程序，包括注册主机目录、将 UART 的 stdout 重定向到主机上的文件，并读取和打印文本文件的内容。
+
 API 参考
 -------------
 
 .. include-build-file:: inc/esp_vfs.inc
 
+.. include-build-file:: inc/esp_vfs_ops.inc
+
 .. include-build-file:: inc/esp_vfs_dev.inc
 
 .. include-build-file:: inc/uart_vfs.inc
diff --git a/docs/zh_CN/api-reference/storage/wear-levelling.rst b/docs/zh_CN/api-reference/storage/wear-levelling.rst
index 830bcc077ec..68a22aa6fbf 100644
--- a/docs/zh_CN/api-reference/storage/wear-levelling.rst
+++ b/docs/zh_CN/api-reference/storage/wear-levelling.rst
@@ -9,7 +9,7 @@
 应用示例
 -------------------
 
-:example:`storage/wear_levelling` 中提供了一款磨损均衡驱动与 FatFs 库结合使用的示例。该示例初始化磨损均衡驱动，挂载 FAT 文件系统分区，并使用 POSIX（可移植操作系统接口）和 C 库 API 从中写入和读取数据。如需了解更多信息，请参考 :example_file:`storage/wear_levelling/README.md`。
+:example:`storage/wear_levelling` 演示了如何使用磨损均衡库和 FatFS 库在分区中存储文件，并使用 POSIX 和 C 库 API 从中写入和读取数据。
 
 高级 API 参考
 ------------------------
diff --git a/docs/zh_CN/api-reference/system/chip_revision.rst b/docs/zh_CN/api-reference/system/chip_revision.rst
index 0c584539e34..c700d56946b 100644
--- a/docs/zh_CN/api-reference/system/chip_revision.rst
+++ b/docs/zh_CN/api-reference/system/chip_revision.rst
@@ -110,7 +110,7 @@ EFuse 块版本号与芯片版本号类似，但是它主要影响在 eFuse 中
 故障排除
 ^^^^^^^^^^^^^^^
 
-1. 如果第二阶段引导加载程序所运行的芯片版本低于镜像（如软件镜像）中指定的最小版本，会发生重启并显示以下消息：
+1. 如果二级引导加载程序所运行的芯片版本低于镜像（如软件镜像）中指定的最小版本，会发生重启并显示以下消息：
 
 .. code-block:: none
 
@@ -132,13 +132,13 @@ EFuse 块版本号与芯片版本号类似，但是它主要影响在 eFuse 中
 二进制镜像的常见版本需求
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-芯片版本号检查主要根据二级引导程序和应用程序二进制镜像中包含的 :cpp:type:`esp_image_header_t` 标头，其中记录了可以运行该软件的芯片版本号。这一标头有 3 个与版本相关的字段：
+芯片版本号检查主要根据二级引导加载程序和应用程序二进制镜像中包含的 :cpp:type:`esp_image_header_t` 标头，其中记录了可以运行该软件的芯片版本号。这一标头有 3 个与版本相关的字段：
 
 - ``min_chip_rev`` - 镜像所需芯片的最小主版本号（但对于 ESP32-C3，该字段指次版本号）。其值由 :ref:`CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MIN` 确定。
 - ``min_chip_rev_full`` - 镜像所需芯片的最小版本号，格式为 ``major * 100 + minor``。其值由 :ref:`CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MIN` 确定。
 - ``max_chip_rev_full`` - 镜像所需芯片的最大版本号，格式为 ``major * 100 + minor``。其值由 ``CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MAX_FULL`` 确定。用户无法对其进行修改，仅当 ESP-IDF 支持新版本时由乐鑫官方进行更改。
 
-而 eFuse 块版本的要求则存储在 :cpp:type:`esp_app_desc_t` 结构体中。该结构体对象位于应用程序的二进制进项文件中。由于 eFuse 块版本信息主要影响 ADC 校准，而二级引导程序的镜像不涉及 ADC，因此我们只需要检查应用程序镜像的 eFuse 块版本信息。有 2 个与 eFuse 块版本相关的字段：
+而 eFuse 块版本的要求则存储在 :cpp:type:`esp_app_desc_t` 结构体中。该结构体对象位于应用程序的二进制进项文件中。由于 eFuse 块版本信息主要影响 ADC 校准，而二级引导加载程序的镜像不涉及 ADC，因此我们只需要检查应用程序镜像的 eFuse 块版本信息。有 2 个与 eFuse 块版本相关的字段：
 
 - ``min_efuse_blk_rev_full`` - 镜像所需 eFuse 块的最小版本号，格式为 ``major * 100 + minor``。其值由 ``CONFIG_ESP_EFUSE_BLOCK_REV_MIN_FULL`` 确定。
 - ``max_efuse_blk_rev_full`` - 镜像所需 eFuse 块的最大版本号，格式为 ``major * 100 + minor``。其值由 ``CONFIG_ESP_EFUSE_BLOCK_REV_MAX_FULL`` 确定。它反映了当前 ESP-IDF 版本能支持的最大 eFuse 块版本号，不应由用户修改。
@@ -148,36 +148,36 @@ EFuse 块版本号与芯片版本号类似，但是它主要影响在 eFuse 中
 
 应用启动过程中，检查最小和最大版本的顺序如下：
 
-1. 在运行第 2 阶段引导启动程序前，第 1 阶段引导启动程序（ROM 引导启动程序）不会在 :cpp:type:`esp_image_header_t` 中检查最小和最大版本字段。
+1. 在运行二级引导加载程序前，一级 (ROM) 引导加载程序不会在 :cpp:type:`esp_image_header_t` 中检查最小和最大版本字段。
 
-2. 在第 2 阶段引导启动程序的初始化阶段，会检查引导程序自身是否可以在此版本的芯片上启动。它从引导启动程序镜像的标头中读取最小版本，并与 eFuse 中的芯片版本进行比较。如果芯片版本低于最小版本，引导启动程序会拒绝启动并中止运行。此阶段不检查最大版本。
+2. 在二级引导加载程序的初始化阶段，会检查引导加载程序自身是否可以在此版本的芯片上启动。它从引导加载程序镜像的标头中读取最小版本，并与 eFuse 中的芯片版本进行比较。如果芯片版本低于最小版本，引导加载程序会拒绝启动并中止运行。此阶段不检查最大版本。
 
-3. 然后，第 2 阶段引导启动程序会检查应用程序的版本要求。它从应用程序镜像的标头中读取支持的芯片最小和最大版本，以及从段的标头中读取 eFuse 块版本信息，并与 eFuse 中的芯片版本进行比较。如果该芯片版本或 eFuse 块版本低于各自的最小版本或高于最大版本，引导程序会拒绝启动并中止。然而，如果设置了忽略最大版本位，则可以忽略最大版本限制。软件确定可以使用此芯片版本时，用户可以自行设置忽略位。
+3. 然后，二级引导加载程序会检查应用程序的版本要求。它从应用程序镜像的标头中读取支持的芯片最小和最大版本，以及从段的标头中读取 eFuse 块版本信息，并与 eFuse 中的芯片版本进行比较。如果该芯片版本或 eFuse 块版本低于各自的最小版本或高于最大版本，引导加载程序会拒绝启动并中止。然而，如果设置了忽略最大版本位，则可以忽略最大版本限制。软件确定可以使用此芯片版本时，用户可以自行设置忽略位。
 
-4. 在空中升级 (OTA) 阶段，运行中的应用程序会检查新软件是否与芯片版本及 eFuse 块版本相匹配。它会从新应用程序镜像的标头中提取最小和最大芯片版本，以及应用程序描述中提取最大和最小 eFuse 块版本，并与 eFuse 中的芯片版本和块版本进行比较。应用程序检查版本匹配的方式与引导启动程序相同，即芯片版本和 eFuse 块版本须处在最小和最大版本之间（忽略最大版本的逻辑也相同）。
+4. 在空中升级 (OTA) 阶段，运行中的应用程序会检查新软件是否与芯片版本及 eFuse 块版本相匹配。它会从新应用程序镜像的标头中提取最小和最大芯片版本，以及应用程序描述中提取最大和最小 eFuse 块版本，并与 eFuse 中的芯片版本和块版本进行比较。应用程序检查版本匹配的方式与引导加载程序相同，即芯片版本和 eFuse 块版本须处在最小和最大版本之间（忽略最大版本的逻辑也相同）。
 
-向后兼容旧版 ESP-IDF 构建的引导启动程序
+向后兼容旧版 ESP-IDF 构建的引导加载程序
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 .. only:: esp32 or esp32c3 or esp32s2 or esp32s3
 
-    主要版本号和次版本号的 eFuse 位对于旧版引导启动程序（由早于 v5.0 版本的 ESP-IDF 进行构建）而言是未知的。旧版启动引导程序只使用一个 eFuse 位来表示芯片版本。
+    主要版本号和次版本号的 eFuse 位对于旧版引导加载程序（由早于 v5.0 版本的 ESP-IDF 进行构建）而言是未知的。旧版引导加载程序只使用一个 eFuse 位来表示芯片版本。
 
 .. only:: esp32
 
-    旧版引导启动程序不读取次版本号的 eFuse 位，且主版本号只能低于或等于 v3。这表明，旧版引导启动程序只能正确检测范围在 ``v0.0`` 至 ``v3.0`` 的芯片版本，其中，次版本号总是设置为 ``0``。
+    旧版引导加载程序不读取次版本号的 eFuse 位，且主版本号只能低于或等于 v3。这表明，旧版引导加载程序只能正确检测范围在 ``v0.0`` 至 ``v3.0`` 的芯片版本，其中，次版本号总是设置为 ``0``。
 
 .. only:: esp32c2
 
-    ESP-IDF v5.0 中添加了对 {IDF_TARGET_NAME} 芯片的支持。引导启动程序能够检测范围在 ``v0.0`` 至 ``v3.15`` 内的所有芯片版本。
+    ESP-IDF v5.0 中添加了对 {IDF_TARGET_NAME} 芯片的支持。引导加载程序能够检测范围在 ``v0.0`` 至 ``v3.15`` 内的所有芯片版本。
 
 .. only:: esp32c3
 
-    在 ESP-IDF v4.3 中添加了对 {IDF_TARGET_NAME} 芯片的支持。旧版引导启动程序无法读取晶圆版本 eFuse 的所有位，只能读取前 3 个最低有效位。因此，旧版引导启动程序无法正确检测芯片版本。具体而言，只能正确检测 ``v0.0`` 至 ``v0.8`` 范围内的芯片版本，其他芯片版本则会被错误识别为该范围内的某个版本。
+    在 ESP-IDF v4.3 中添加了对 {IDF_TARGET_NAME} 芯片的支持。旧版引导加载程序无法读取晶圆版本 eFuse 的所有位，只能读取前 3 个最低有效位。因此，旧版引导加载程序无法正确检测芯片版本。具体而言，只能正确检测 ``v0.0`` 至 ``v0.8`` 范围内的芯片版本，其他芯片版本则会被错误识别为该范围内的某个版本。
 
 .. only:: esp32s2 or esp32s3
 
-    在 ESP-IDF v4.2 中添加了对 {IDF_TARGET_NAME} 芯片的支持。 由于 ``Minimum Supported ESP32-S2 Revision`` Kconfig 选项未引入，{IDF_TARGET_NAME} 芯片在 :cpp:type:`esp_image_header_t` 头文件中将 ``rev_min`` 设置为 0。这表明旧版引导启动程序不会检查芯片版本。在 v0.0 至 v3.15 范围内，任何应用程序都可以通过此类引导加载程序加载。
+    在 ESP-IDF v4.2 中添加了对 {IDF_TARGET_NAME} 芯片的支持。 由于 ``Minimum Supported ESP32-S2 Revision`` Kconfig 选项未引入，{IDF_TARGET_NAME} 芯片在 :cpp:type:`esp_image_header_t` 头文件中将 ``rev_min`` 设置为 0。这表明旧版引导加载程序不会检查芯片版本。在 v0.0 至 v3.15 范围内，任何应用程序都可以通过此类引导加载程序加载。
 
 请使用 ``esptool chip_id`` 命令查看芯片版本。
 
diff --git a/docs/zh_CN/api-reference/system/efuse.rst b/docs/zh_CN/api-reference/system/efuse.rst
index 941e3472c26..c3b4bd624f4 100644
--- a/docs/zh_CN/api-reference/system/efuse.rst
+++ b/docs/zh_CN/api-reference/system/efuse.rst
@@ -555,7 +555,7 @@ flash 加密测试
 
 flash 加密是一项硬件功能，需要物理烧录 eFuse ``key`` 和 ``FLASH_CRYPT_CNT``。如果 flash 加密实际未启用，那么启用 :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` 选项只是提供了测试的可能性，而不会加密 flash 中的任何内容，即使日志中显示了加密操作。
 
-为此，可使用 :cpp:func:`bootloader_flash_write` 函数。但是，如果运行应用程序时芯片已启用 flash 加密，或者以 :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` 选项创建了启动加载程序，则 flash 加密/解密操作会正常进行。这意味着数据写入加密 flash 分区时被加密，从加密分区读取时被解密。
+为此，可使用 :cpp:func:`bootloader_flash_write` 函数。但是，如果运行应用程序时芯片已启用 flash 加密，或者以 :ref:`CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH` 选项创建了引导加载程序，则 flash 加密/解密操作会正常进行。这意味着数据写入加密 flash 分区时被加密，从加密分区读取时被解密。
 
 ``espefuse.py``
 ^^^^^^^^^^^^^^^
diff --git a/docs/zh_CN/api-reference/system/freertos.rst b/docs/zh_CN/api-reference/system/freertos.rst
index bccfb14da3a..73ddc5c1c6f 100644
--- a/docs/zh_CN/api-reference/system/freertos.rst
+++ b/docs/zh_CN/api-reference/system/freertos.rst
@@ -47,7 +47,7 @@ ESP-IDF FreeRTOS
 
 **然而，对于 ESP-IDF 中的所有 FreeRTOS 移植，FreeRTOSConfig.h 头文件被视为私有文件，用户不得修改。** 由于该选项在 ESP-IDF 中是必选项或不被支持，``FreeRTOSConfig.h`` 中的大量内核配置选项均为硬编码。所有用户可配置的内核配置选项都在 ``Component Config/FreeRTOS/Kernel`` 下的 menuconfig 中。
 
-关于用户可配置内核选项的完整列表，参见 :doc:`/api-reference/kconfig`。下列为常用的内核配置选项：
+关于用户可配置内核选项的完整列表，请参见 :ref:`Kconfig 选项参考 <configuration-options-reference>`。下列为常用的内核配置选项：
 
 - :ref:`CONFIG_FREERTOS_UNICORE`：仅在核 0 上运行 FreeRTOS。注意，这 **不等同于运行原生 FreeRTOS。** 另外，此选项还可能影响除 :component:`freertos` 外其他组件的行为。关于在单核上运行 FreeRTOS 的更多内容，请参考 :ref:`freertos-idf-single-core` （使用 ESP-IDF FreeRTOS 时）或参考 Amazon SMP FreeRTOS 的官方文档，还可以在 ESP-IDF 组件中搜索 ``CONFIG_FREERTOS_UNICORE``。
 
diff --git a/docs/zh_CN/api-reference/system/mem_alloc.rst b/docs/zh_CN/api-reference/system/mem_alloc.rst
index 12fef6b8f11..ed203af3abd 100644
--- a/docs/zh_CN/api-reference/system/mem_alloc.rst
+++ b/docs/zh_CN/api-reference/system/mem_alloc.rst
@@ -105,7 +105,7 @@ DMA 存储器
 
 使用 ``MALLOC_CAP_DMA`` 标志分配适合与硬件 DMA 引擎（如 SPI 和 I2S）配合使用的内存，此属性标志不包括外部 PSRAM。
 
-.. only SOC_SPIRAM_SUPPORTED and not esp32::
+.. only:: SOC_SPIRAM_SUPPORTED and not esp32
 
     EDMA 硬件功能可以将 DMA buffer 放置在外部 PSRAM，但可能存在一定的对齐限制，详情请参阅 {IDF_TARGET_NAME} 技术参考手册。若要分配一个可用 DMA 的外部 buffer，请使用 ``MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA`` 属性标志，堆分配器将处理 cache 及 DMA 子系统的对齐要求。如果某个外设有额外的对齐要求，可以调用 :cpp:func:heap_caps_aligned_alloc 并指定必要的对齐方式。
 
diff --git a/docs/zh_CN/api-reference/system/misc_system_api.rst b/docs/zh_CN/api-reference/system/misc_system_api.rst
index 21e3a22973e..455c0594f3d 100644
--- a/docs/zh_CN/api-reference/system/misc_system_api.rst
+++ b/docs/zh_CN/api-reference/system/misc_system_api.rst
@@ -9,7 +9,7 @@
 软件复位
 ------------
 
-函数 :cpp:func:`esp_restart` 用于执行芯片的软件复位。调用此函数时，程序停止执行，{IDF_TARGET_CPU_RESET_DES}，应用程序由 bootloader 加载并重启。
+函数 :cpp:func:`esp_restart` 用于执行芯片的软件复位。调用此函数时，程序停止执行，{IDF_TARGET_CPU_RESET_DES}，应用程序由引导加载程序加载并重启。
 
 函数 :cpp:func:`esp_register_shutdown_handler` 用于注册复位前会自动调用的例程（复位过程由 :cpp:func:`esp_restart` 函数触发），这与 ``atexit`` POSIX 函数的功能类似。
 
diff --git a/docs/zh_CN/api-reference/system/ota.rst b/docs/zh_CN/api-reference/system/ota.rst
index 53d0d1b6723..0ba597fcb83 100644
--- a/docs/zh_CN/api-reference/system/ota.rst
+++ b/docs/zh_CN/api-reference/system/ota.rst
@@ -19,7 +19,7 @@ OTA 数据分区
 
 所有使用 OTA 功能项目，其 :doc:`../../api-guides/partition-tables` 必须包含一个 OTA 数据分区（类型为 ``data``，子类型为 ``ota``）。
 
-工厂启动设置下，OTA 数据分区中应没有数据（所有字节擦写成 0xFF）。如果分区表中有工厂应用程序，ESP-IDF 软件引导加载程序会启动工厂应用程序。如果分区表中没有工厂应用程序，则启动第一个可用的 OTA 分区（通常是 ``ota_0``）。
+工厂启动设置下，OTA 数据分区中应没有数据（所有字节擦写成 0xFF）。如果分区表中有工厂应用程序，ESP-IDF 二级引导加载程序会启动工厂应用程序。如果分区表中没有工厂应用程序，则启动第一个可用的 OTA 分区（通常是 ``ota_0``）。
 
 第一次 OTA 升级后，OTA 数据分区更新，指定下一次启动哪个 OTA 应用程序分区。
 
@@ -344,7 +344,9 @@ Python API
 应用示例
 ------------
 
-- :example:`system/ota/otatool` 演示了如何使用 OTA 工具执行读取、写入和擦除 OTA 分区、切换启动分区以及切换到出厂分区等操作。有关更多信息，请参考 :example_file:`system/ota/otatool/README.md`。
+- :example:`system/ota/native_ota_example` 演示了如何在 {IDF_TARGET_NAME} 上使用 `app_update` 组件的 API 进行原生空中升级 (OTA)。适用的 SoC 请参阅 :example_file:`system/ota/native_ota_example/README.md`。
+
+- :example:`system/ota/otatool` 演示了如何使用 OTA 工具执行读取、写入和擦除 OTA 分区、切换启动分区以及切换到工厂分区等操作。详情请参阅 :example_file:`system/ota/otatool/README.md`。
 
 API 参考
 --------
diff --git a/docs/zh_CN/api-reference/system/power_management.rst b/docs/zh_CN/api-reference/system/power_management.rst
index 6d1e464abc0..e6d2b211de2 100644
--- a/docs/zh_CN/api-reference/system/power_management.rst
+++ b/docs/zh_CN/api-reference/system/power_management.rst
@@ -141,40 +141,44 @@ ESP-IDF 中集成的电源管理算法可以根据应用程序组件的需求，
 
         如果在 menuconfig 中启用了 :ref:`CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP`，在初始化外设时，驱动会将外设工作的寄存器上下文注册到休眠备份链表中，在进入休眠前，``REG_DMA`` 外设会读取休眠备份链表中的配置，根据链表中的配置将外设的寄存器上下文备份至内存，``REG_DMA`` 也会在唤醒时将上下文从内存恢复到外设寄存中。
 
-        目前 IDF 支持以下外设的 Light-sleep 上下文备份：
+        目前 IDF 支持以下外设的 Light-sleep 上下文备份，它们的上下文会自动恢复，或者提供了相关的选项允许用户进入外设下电模式：
 
         .. list::
 
             - INT_MTX
             - TEE/APM
             - IO_MUX / GPIO
-            - Timer Group 0 & Timer Group 1
-            - SPI0/1
+            - MSPI (SPI0/1)
             - SYSTIMER
+            :SOC_TIMER_SUPPORT_SLEEP_RETENTION: - GPTimer
             :SOC_RMT_SUPPORT_SLEEP_RETENTION: - RMT
+            :SOC_LEDC_SUPPORT_SLEEP_RETENTION: - LEDC
             :SOC_I2C_SUPPORT_SLEEP_RETENTION: - I2C
             :SOC_I2S_SUPPORT_SLEEP_RETENTION: - I2S
+            :SOC_ETM_SUPPORT_SLEEP_RETENTION: - ETM
+            :SOC_MCPWM_SUPPORT_SLEEP_RETENTION: - MCPWM
             :SOC_UART_SUPPORT_SLEEP_RETENTION: - All UARTs
+            :SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION: - Temperature Sensor
+            :SOC_TWAI_SUPPORT_SLEEP_RETENTION: - All TWAIs
+            :SOC_PARLIO_SUPPORT_SLEEP_RETENTION: - PARL_IO
+            :SOC_SPI_SUPPORT_SLEEP_RETENTION: - All GPSPIs
 
-        以下外设尚未支持：
+        一些外设尚未支持睡眠上下文恢复，或者寄存器丢失后根本无法恢复。即使外设下电功能被启用，它们也会阻止外设下电的发生：
+
+        .. list::
+
+            :SOC_SDIO_SLAVE_SUPPORTED: - SDIO Slave
+
+        以下外设（以及一些未在本章节任意一组中列出的外设）尚未支持外设下电功能。如果您的应用使用了这些外设，它们可能无法在从睡眠中醒来后仍然正常工作：
 
         .. list::
 
-            - ETM
             - ASSIST_DEBUG
             - Trace
             - Crypto: AES/ECC/HMAC/RSA/SHA/DS/XTA_AES/ECDSA
-            - SPI2
             - PCNT
             - USB-Serial-JTAG
-            - TWAI
-            - LEDC
-            - MCPWM
             - SARADC
-            - SDIO
-            - PARL_IO
-
-        对于未支持 Light-sleep 上下文备份的外设，若启用了电源管理功能，应在外设工作时持有 ``ESP_PM_NO_LIGHT_SLEEP`` 锁以避免进入休眠导致外设工作上下文丢失。
 
         .. note::
 
diff --git a/docs/zh_CN/api-reference/system/pthread.rst b/docs/zh_CN/api-reference/system/pthread.rst
index 218c647ec21..48af7bf9b89 100644
--- a/docs/zh_CN/api-reference/system/pthread.rst
+++ b/docs/zh_CN/api-reference/system/pthread.rst
@@ -1,5 +1,5 @@
-POSIX Thread
-============
+POSIX 支持（包括 POSIX 线程支持）
+=================================
 
 :link_to_translation:`en:[English]`
 
@@ -12,7 +12,11 @@ ESP-IDF 基于 FreeRTOS，但提供了一系列与 POSIX 兼容的 API，以便
 
 添加标准 ``pthread.h`` 头文件后可以在 ESP-IDF 中使用 pthread，该头文件已包含在工具链 libc 中。还有另一个专用于 ESP-IDF 的头文件 ``esp_pthread.h``，其中提供了一些额外的非 POSIX API，以便通过 pthread 使用一些 ESP-IDF 功能。
 
-C++ 标准库中的 ``std::thread``、``std::mutex``、``std::condition_variable`` 等功能也是通过 pthread（利用 GCC libstdc++）实现的。因此，本文档提到的限制条件也同样适用于 C++ 标准库中等效功能。
+除了 POSIX 线程，ESP-IDF 还支持 :ref:`POSIX 消息队列 <posix_message_queues>`。
+
+C++ 标准库中的 ``std::thread``、``std::mutex``、``std::condition_variable`` 等功能也是通过 pthread 和其他 POSIX API（利用 GCC libstdc++）实现的。因此，本文档提到的限制条件也同样适用于 C++ 标准库中的等效功能。
+
+如果希望 ESP-IDF 支持某个尚未实现的 API，请 `在 GitHub 上发起功能请求 <https://github.com/espressif/esp-idf/issues>`_ 并提供详细信息。
 
 RTOS 集成
 ----------------
@@ -23,6 +27,10 @@ RTOS 集成
 
     如果调用 C 标准库或 C++ sleep 函数，例如在 ``unistd.h`` 中定义的 ``usleep``，那么只有当睡眠时间超过 :ref:`一个 FreeRTOS 滴答周期 <CONFIG_FREERTOS_HZ>` 时，任务才会阻塞并让出内核。如果时间较短，线程将处于忙等待状态，不会让步给另一个 RTOS 任务。
 
+.. note::
+
+    POSIX 的 ``errno`` 由 ESP-IDF 中的 newlib 提供。因此，配置项 ``configUSE_POSIX_ERRNO`` 并未被使用，应该保持禁用状态。
+
 默认情况下，所有 pthread 具有相同的 RTOS 优先级，但可以通过调用 :ref:`ESP-IDF 提供的扩展 API <esp-pthread>` 对此优先级进行更改。
 
 标准功能
@@ -169,15 +177,65 @@ ESP-IDF 中实现了 POSIX 读写锁规范的以下 API 函数：
 
     ESP-IDF 中还有其他的线程本地存储选项，包括性能更高的选项。参见 :doc:`/api-guides/thread-local-storage`。
 
+.. _posix_message_queues:
+
+消息队列
+^^^^^^^^
+
+消息队列的实现基于 `FreeRTOS-Plus-POSIX <https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_POSIX/index.html>`_ 项目，ESP-IDF 的文件系统不提供消息队列，不支持消息优先级。
+
+以下 POSIX 消息队列规范中的 API 函数已被实现：
+
+* `mq_open() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_open.html>`_
+
+    - 除了要符合 POSIX 规范，``name`` 参数还有以下额外限制：
+        - 必须以斜杠开头。
+        - 长度不得超过 255 + 2 个字符（包括开头的斜杠，除去终止的空字符）。但 ``name`` 的内存是在内部动态分配的，所以名称越短，消耗的内存越少。
+    - ``mode`` 参数未实现且被忽略。
+    - 支持的 ``oflags``：``O_RDWR``、``O_CREAT``、``O_EXCL`` 和 ``O_NONBLOCK``。
+
+* `mq_close() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_close.html>`_
+* `mq_unlink() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_unlink.html>`_
+* `mq_receive() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_receive.html>`_
+
+    - 不支持消息优先级，因此 ``msg_prio`` 未被使用。
+
+* `mq_timedreceive() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_receive.html>`_
+
+    - 不支持消息优先级，因此 ``msg_prio`` 未被使用。
+
+* `mq_send() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_send.html>`_
+
+    - 不支持消息优先级，因此 ``msg_prio`` 无效。
+
+* `mq_timedsend() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_send.html>`_
+
+    - 不支持消息优先级，因此 ``msg_prio`` 无效。
+
+* `mq_getattr() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_getattr.html>`_
+
+尚未实现 `mq_notify() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_notify.html>`_ 和 `mq_setattr() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_setattr.html>`_。
+
+构建
+....
+
+要使用 POSIX 消息队列 API，请在组件的 ``CMakeLists.txt`` 文件中添加 ``rt`` 作为依赖项。
+
+.. note::
+
+    请注意，如果曾在其他 FreeRTOS 项目中使用过 `FreeRTOS-Plus-POSIX <https://www.freertos.org/FreeRTOS-Plus/FreeRTOS_Plus_POSIX/index.html>`_，则 IDF 中的包含路径是 POSIX 风格的。因此，应用程序应直接包含 ``mqueue.h``，而不是使用子目录来包含 ``FreeRTOS_POSIX/mqueue.h``。
+
 未实现 API
 ---------------
 
 ``pthread.h`` 头文件是一个标准头文件，包含了在 ESP-IDF 中未实现的额外 API 和功能，包括：
 
-* 如果调用 ``pthread_cancel()``，返回 ``ENOSYS``。
-* ``pthread_condattr_init()`` 如果被调用，返回 ``ENOSYS``。
+* 若调用 ``pthread_cancel()``，则返回 ``ENOSYS``。
+* 若调用 ``pthread_condattr_init()``，则返回 ``ENOSYS``。
+* 若调用 `mq_notify() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_notify.html>`_，则返回 ``ENOSYS``。
+* 若调用 `mq_setattr() <https://pubs.opengroup.org/onlinepubs/9699919799/functions/mq_setattr.html>`_，则返回 ``ENOSYS``。
 
-其他未列出的 pthread 函数未在 ESP-IDF 中实现，如果从 ESP-IDF 应用程序中直接引用，将产生编译器错误或链接器错误。如果希望 ESP-IDF 支持某个尚未实现的 API，请 `在 GitHub 上发起功能请求 <https://github.com/espressif/esp-idf/issues>`_ 并提供详细信息。
+其他未列出的 pthread 函数未在 ESP-IDF 中实现，如果从 ESP-IDF 应用程序中直接引用，将产生编译器错误或链接器错误。
 
 .. _esp-pthread:
 
diff --git a/docs/zh_CN/api-reference/system/random.rst b/docs/zh_CN/api-reference/system/random.rst
index d10a9433b85..dc1117b698b 100644
--- a/docs/zh_CN/api-reference/system/random.rst
+++ b/docs/zh_CN/api-reference/system/random.rst
@@ -46,7 +46,7 @@
 
 .. note::
 
-    ESP-IDF 第二阶段引导加载程序在启动过程中启用的熵源会用熵来初始化内部 RNG 状态。但是，内部硬件 RNG 状态的大小并不足以提供连续的真随机数流。因此，在需要真随机数时必须启用连续的熵源。
+    ESP-IDF 二级引导加载程序在启动过程中启用的熵源会用熵来初始化内部 RNG 状态。但是，内部硬件 RNG 状态的大小并不足以提供连续的真随机数流。因此，在需要真随机数时必须启用连续的熵源。
 
 .. note::
 
diff --git a/docs/zh_CN/api-reference/system/ulp-lp-core.rst b/docs/zh_CN/api-reference/system/ulp-lp-core.rst
index 70cd7ec870b..4ffeca4ad74 100644
--- a/docs/zh_CN/api-reference/system/ulp-lp-core.rst
+++ b/docs/zh_CN/api-reference/system/ulp-lp-core.rst
@@ -1,11 +1,11 @@
-ULP LP-Core 协处理器编程
-===================================
+ULP LP 内核协处理器编程
+=======================
 
 :link_to_translation:`en:[English]`
 
-ULP LP-Core（低功耗内核）协处理器是 {IDF_TARGET_NAME} 中 ULP 的一个变型。它具有超低功耗，同时还能在主 CPU 处于低功耗模式时保持运行。因此，LP-Core 协处理器能够在主 CPU 处于睡眠模式时处理 GPIO 或传感器读取等任务，从而显著降低整个系统的整体功耗。
+ULP LP 内核 (Low-power core) 协处理器是 {IDF_TARGET_NAME} 中 ULP 的一个变型。它具有超低功耗，同时还能在主 CPU 处于低功耗模式时保持运行。因此，LP 内核协处理器能够在主 CPU 处于睡眠模式时处理 GPIO 或传感器读取等任务，从而显著降低整个系统的整体功耗。
 
-ULP LP-Core 协处理器具有以下功能：
+ULP LP 内核协处理器具有以下功能：
 
 * RV32I 处理器（32 位 RISC-V ISA），支持乘法/除法 (M)、原子 (A) 和压缩 (C) 扩展。
 * 中断控制器。
@@ -13,17 +13,17 @@ ULP LP-Core 协处理器具有以下功能：
 * 当整个系统处于 active 模式时，可以访问所有的高功耗 (HP) SRAM 和外设。
 * 当 HP 系统处于睡眠模式时，可以访问低功耗 (LP) SRAM 和外设。
 
-编译 ULP LP-Core 代码
-----------------------------------
+编译 ULP LP 内核代码
+--------------------
 
-ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二进制文件，并自动嵌入到主项目的二进制文件中。编译可通过以下两种方式实现：
+ULP LP 内核代码会与 ESP-IDF 项目共同编译，生成一个单独的二进制文件，并自动嵌入到主项目的二进制文件中。编译可通过以下两种方式实现：
 
 使用 ``ulp_embed_binary``
 ~~~~~~~~~~~~~~~~~~~~~~~~~
 
-1. 将用 C 语言或汇编语言编写的 ULP LP-Core 代码（带有 ``.S`` 扩展名）放在组件目录下的专用目录中，例如 ``ulp/``。
+1. 将用 C 语言或汇编语言编写的 ULP LP 内核代码（带有 ``.S`` 扩展名）放在组件目录下的专用目录中，例如 ``ulp/``。
 
-2. 在 CMakeLists.txt 文件中注册组件后，调用 ``ulp_embed_binary`` 函数。例如：
+2. 在 ``CMakeLists.txt`` 文件中注册组件后，调用 ``ulp_embed_binary`` 函数。例如：
 
 .. code-block:: cmake
 
@@ -41,7 +41,7 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二
 使用自定义的 CMake 项目
 ~~~~~~~~~~~~~~~~~~~~~~~
 
-也可以为 LP-Core 创建自定义的 CMake 项目，从而更好地控制构建过程，并实现常规 CMake 项目的操作，例如设置编译选项、链接外部库等。
+也可以为 LP 内核创建自定义的 CMake 项目，从而更好地控制构建过程，并实现常规 CMake 项目的操作，例如设置编译选项、链接外部库等。
 
 请在组件的 ``CMakeLists.txt`` 文件中将 ULP 项目添加为外部项目：
 
@@ -90,7 +90,7 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二
 
 若想编译和构建项目，请执行以下操作：
 
-1. 在 menuconfig 中启用 :ref:`CONFIG_ULP_COPROC_ENABLED` 和 :ref:`CONFIG_ULP_COPROC_TYPE` 选项，并将 :ref:`CONFIG_ULP_COPROC_TYPE` 设置为 ``CONFIG_ULP_COPROC_TYPE_LP_CORE``。:ref:`CONFIG_ULP_COPROC_RESERVE_MEM` 选项为 ULP 保留 RTC 内存，因此必须设置为一个足够大的值，以存储 ULP LP-Core 代码和数据。如果应用程序组件包含多个 ULP 程序，那么 RTC 内存的大小必须足够容纳其中最大的程序。
+1. 在 menuconfig 中启用 :ref:`CONFIG_ULP_COPROC_ENABLED` 和 :ref:`CONFIG_ULP_COPROC_TYPE` 选项，并将 :ref:`CONFIG_ULP_COPROC_TYPE` 设置为 ``CONFIG_ULP_COPROC_TYPE_LP_CORE``。:ref:`CONFIG_ULP_COPROC_RESERVE_MEM` 选项为 ULP 保留 RTC 内存，因此必须设置为一个足够大的值，以存储 ULP LP 内核代码和数据。如果应用程序组件包含多个 ULP 程序，那么 RTC 内存的大小必须足够容纳其中最大的程序。
 
 2. 按照常规步骤构建应用程序（例如 ``idf.py app``）。
 
@@ -113,12 +113,12 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二
 
 .. _ulp-lp-core-access-variables:
 
-访问 ULP LP-Core 程序变量
--------------------------------------------
+访问 ULP LP 内核程序变量
+------------------------
 
-在主程序中可以使用在 ULP LP-Core 程序中定义的全局符号。
+在主程序中可以使用在 ULP LP 内核程序中定义的全局符号。
 
-例如，ULP LP-Core 程序定义了一个变量 ``measurement_count``，用来表示程序从深度睡眠中唤醒芯片前所需的 GPIO 测量次数。
+例如，ULP LP 内核程序定义了一个变量 ``measurement_count``，用来表示程序从深度睡眠中唤醒芯片前所需的 GPIO 测量次数。
 
 .. code-block:: c
 
@@ -132,7 +132,7 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二
         ...do something.
     }
 
-主程序可以访问 ULP LP-Core 程序全局变量，这是因为构建系统生成了 ``${ULP_APP_NAME}.h`` 和 ``${ULP_APP_NAME}.ld`` 文件，文件中定义了 ULP LP-Core 程序中现有的的全局符号。在 ULP LP-Core 程序中定义的每个全局符号都包含在这两个文件中，并具有前缀 ``ulp_``。
+主程序可以访问 ULP LP 内核程序全局变量，这是因为构建系统生成了 ``${ULP_APP_NAME}.h`` 和 ``${ULP_APP_NAME}.ld`` 文件，文件中定义了 ULP LP 内核程序中现有的的全局符号。在 ULP LP 内核程序中定义的每个全局符号都包含在这两个文件中，并具有前缀 ``ulp_``。
 
 头文件中包含符号的声明：
 
@@ -148,7 +148,7 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二
 
     PROVIDE ( ulp_measurement_count = 0x50000060 );
 
-要从主程序访问 ULP LP-Core 程序变量，应使用 ``include`` 语句将生成的头文件包含在主程序中，这样就可以像访问常规变量一样访问 ULP LP-Core 程序变量。
+要从主程序访问 ULP LP 内核程序变量，应使用 ``include`` 语句将生成的头文件包含在主程序中，这样就可以像访问常规变量一样访问 ULP LP 内核程序变量。
 
 .. code-block:: c
 
@@ -160,15 +160,15 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二
 
 .. note::
 
-    LP-Core 程序全局变量存储在二进制文件的 ``.bss`` 或者 ``.data`` 部分。这些部分在加载和执行 LP-Core 二进制文件时被初始化。在首次运行 LP-Core 之前，从 HP-Core 主程序访问这些变量可能会导致未定义行为。
+    LP 内核程序全局变量存储在二进制文件的 ``.bss`` 或者 ``.data`` 部分。这些部分在加载和执行 LP 内核二进制文件时被初始化。在首次运行 LP 内核之前，从 HP-Core 主程序访问这些变量可能会导致未定义行为。
 
 
-启动 ULP LP-Core 程序
---------------------------------
+启动 ULP LP 内核程序
+--------------------
 
-要运行 ULP LP-Core 程序，主应用程序需要先使用 :cpp:func:`ulp_lp_core_load_binary` 函数将 ULP 程序加载到 RTC 内存中，然后使用 :cpp:func:`ulp_lp_core_run` 函数进行启动。
+要运行 ULP LP 内核程序，主应用程序需要先使用 :cpp:func:`ulp_lp_core_load_binary` 函数将 ULP 程序加载到 RTC 内存中，然后使用 :cpp:func:`ulp_lp_core_run` 函数进行启动。
 
-每个 ULP LP-Core 程序以二进制 blob 的形式嵌入到 ESP-IDF 应用程序中。应用程序可以按照如下方式引用和加载该 blob（假设 ULP_APP_NAME 被定义为 ``ulp_app_name``）：
+每个 ULP LP 内核程序以二进制 blob 的形式嵌入到 ESP-IDF 应用程序中。应用程序可以按照如下方式引用和加载该 blob（假设 ULP_APP_NAME 被定义为 ``ulp_app_name``）：
 
 .. code-block:: c
 
@@ -191,10 +191,10 @@ ULP LP-Core 代码会与 ESP-IDF 项目共同编译，生成一个单独的二
 
     ESP_ERROR_CHECK( ulp_lp_core_run(&cfg) );
 
-ULP LP-Core 程序流程
-------------------------
+ULP LP 内核程序流程
+-------------------
 
-ULP LP-Core 协处理器如何启动取决于 :cpp:type:`ulp_lp_core_cfg_t` 中选择的唤醒源。最常见的用例是 ULP 定期唤醒，在进行一些测量后唤醒主 CPU，或者再次进入睡眠状态。
+ULP LP 内核协处理器如何启动取决于 :cpp:type:`ulp_lp_core_cfg_t` 中选择的唤醒源。最常见的用例是 ULP 定期唤醒，在进行一些测量后唤醒主 CPU，或者再次进入睡眠状态。
 
 ULP 有以下唤醒源：
     * :c:macro:`ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU` - LP 内核可以被 HP CPU 唤醒。
@@ -215,10 +215,10 @@ ULP 被唤醒时会经历以下步骤：
     #. 调用 :cpp:func:`ulp_lp_core_halt`
 
 
-ULP LP-Core 支持的外设
-------------------------------
+ULP LP 内核支持的外设
+---------------------
 
-为了增强 ULP LP-Core 协处理器的功能，它可以访问在低功耗电源域运行的外设。ULP LP-Core 协处理器可以在主 CPU 处于睡眠模式时与这些外设进行交互，并在达到唤醒条件时唤醒主 CPU。以下为支持的外设：
+为了增强 ULP LP 内核协处理器的功能，它可以访问在低功耗电源域运行的外设。ULP LP 内核协处理器可以在主 CPU 处于睡眠模式时与这些外设进行交互，并在达到唤醒条件时唤醒主 CPU。以下为支持的外设：
 
 .. list::
 
@@ -229,14 +229,14 @@ ULP LP-Core 支持的外设
 
 .. only:: CONFIG_ESP_ROM_HAS_LP_ROM
 
-    ULP LP-Core ROM
+    ULP LP 内核 ROM
     ---------------
 
-    ULP LP-Core ROM 是位于 LP-ROM 中的一小段预编译代码，用户无法修改。与主 CPU 运行的引导加载程序 ROM 代码类似，ULP LP-Core ROM 也在 ULP LP-Core 协处理器启动时执行。该 ROM 代码会初始化 ULP LP-Core 协处理器，随后跳转到用户程序。如果已初始化 LP UART，该 ROM 代码还会打印启动信息。
+    ULP LP 内核 ROM 是位于 LP-ROM 中的一小段预编译代码，用户无法修改。与主 CPU 运行的引导加载程序 ROM 代码类似，ULP LP 内核 ROM 也在 ULP LP 内核协处理器启动时执行。该 ROM 代码会初始化 ULP LP 内核协处理器，随后跳转到用户程序。如果已初始化 LP UART，该 ROM 代码还会打印启动信息。
 
-    如果已将 :cpp:member:`ulp_lp_core_cfg_t::skip_lp_rom_boot` 设置为真，则不会执行 ULP LP-Core ROM 代码。如需尽快唤醒 ULP，同时避免初始化和信息打印产生额外开销，则可使用这一功能。
+    如果已将 :cpp:member:`ulp_lp_core_cfg_t::skip_lp_rom_boot` 设置为真，则不会执行 ULP LP 内核 ROM 代码。如需尽快唤醒 ULP，同时避免初始化和信息打印产生额外开销，则可使用这一功能。
 
-    除上述启动代码，ULP LP-Core ROM 代码还提供以下功能和接口：
+    除上述启动代码，ULP LP 内核 ROM 代码还提供以下功能和接口：
 
     * :component_file:`ROM.ld 接口 <esp_rom/{IDF_TARGET_PATH_NAME}/ld/{IDF_TARGET_PATH_NAME}lp.rom.ld>`
     * :component_file:`newlib.ld 接口 <esp_rom/{IDF_TARGET_PATH_NAME}/ld/{IDF_TARGET_PATH_NAME}lp.rom.newlib.ld>`
@@ -244,12 +244,12 @@ ULP LP-Core 支持的外设
     在任何情况下，这些函数都存在于 LP-ROM 中，因此在程序中使用这些函数可以减少 ULP 应用程序的 RAM 占用。
 
 
-ULP LP-Core 中断
-----------------
+ULP LP 内核中断
+---------------
 
-配置 LP-Core 协处理器，可以处理各种类型的中断，例如 LP IO 低/高电平中断或是 LP 定时器中断。只需重写 IDF 提供的任何一个弱处理函数，就可以注册一个中断处理程序。所有处理程序可见 :component_file:`ulp_lp_core_interrupts.h <ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h>`。有关特定目标可使用的中断的详细信息，请参阅 **{IDF_TARGET_NAME} 技术参考手册** [`PDF <{IDF_TARGET_TRM_CN_URL}#ulp>`__]。
+配置 LP 内核协处理器，可以处理各种类型的中断，例如 LP IO 低/高电平中断或是 LP 定时器中断。只需重写 IDF 提供的任何一个弱处理函数，就可以注册一个中断处理程序。所有处理程序可见 :component_file:`ulp_lp_core_interrupts.h <ulp/lp_core/lp_core/include/ulp_lp_core_interrupts.h>`。有关特定目标可使用的中断的详细信息，请参阅 **{IDF_TARGET_NAME} 技术参考手册** [`PDF <{IDF_TARGET_TRM_CN_URL}#ulp>`__]。
 
-例如，要重写 LP IO 中断的处理程序，可以在 ULP LP-Core 代码中定义以下函数：
+例如，要重写 LP IO 中断的处理程序，可以在 ULP LP 内核代码中定义以下函数：
 
 .. code-block:: c
 
@@ -260,50 +260,130 @@ ULP LP-Core 中断
 
 :c:macro:`LP_CORE_ISR_ATTR` 宏用于定义中断处理函数，可确保调用中断处理程序时妥善保存并恢复寄存器。
 
-除了为需要处理的中断源配置相关的中断寄存器外，还要调用 :cpp:func:`ulp_lp_core_intr_enable` 函数，在 LP-Core 中断控制器中使能全局中断。
+除了为需要处理的中断源配置相关的中断寄存器外，还要调用 :cpp:func:`ulp_lp_core_intr_enable` 函数，在 LP 内核中断控制器中使能全局中断。
+
+ULP LP 内核时钟配置
+-------------------
 
-调试 ULP LP-Core 应用程序
--------------------------
+{IDF_TARGET_XTAL_FREQ:default="未更新", esp32c5="48 MHz", esp32p4="40 MHz"}
 
-在编程 LP-Core 时，有时很难弄清楚程序未按预期运行的原因。请参考以下策略，调试 LP-Core 程序：
+ULP LP 内核的时钟源来自系统时钟 ``LP_FAST_CLK``，详情请参见 `技术参考手册 <{IDF_TARGET_TRM_CN_URL}>`__ > ``复位和时钟``。
 
-* 使用 LP-UART 打印：LP-Core 可以访问 LP-UART 外设，在主 CPU 处于睡眠状态时独立打印信息。有关使用此驱动程序的示例，请参阅 :example:`system/ulp/lp_core/lp_uart/lp_uart_print`。
+.. only:: SOC_CLK_LP_FAST_SUPPORT_XTAL
 
-* 通过 :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`，将 :cpp:func:`lp_core_printf` 路由到 HP-Core 控制台 UART，可以轻松地将 LP-Core 信息打印到已经连接的 HP-Core 控制台 UART。此方法的缺点是需要主 CPU 处于唤醒状态，并且由于 LP 核与 HP 核未同步，输出可能会交错。
+    在 {IDF_TARGET_NAME} 上，``LP_FAST_CLK`` 支持使用外部 {IDF_TARGET_XTAL_FREQ} 晶振 (XTAL) 作为其时钟源。默认时钟源 ``RTC_FAST_CLOCK`` 的运行频率约为 20 MHz，使用外部晶振时钟后，ULP LP 内核将以更高的频率运行。缺点在于，``LP_FAST_CLK`` 在休眠期间通常会断电以减少功耗，而选择 XTAL 作为时钟源后，休眠期间时钟仍将保持通电，造成功耗增加。因此，如果仅希望在 HP 内核活动时将 LP 内核用作协处理器，则可以使用 XTAL 以提高 LP 内核的性能和频率稳定性。
+
+    要启用此功能，请将 :ref:`CONFIG_RTC_FAST_CLK_SRC` 设置为 ``CONFIG_RTC_FAST_CLK_SRC_XTAL``。
+
+
+调试 ULP LP 内核应用程序
+------------------------
+
+在编程 LP 内核时，有时很难弄清楚程序未按预期运行的原因。请参考以下策略，调试 LP 内核程序：
+
+* 使用 LP-UART 打印：LP 内核可以访问 LP-UART 外设，在主 CPU 处于睡眠状态时独立打印信息。有关使用此驱动程序的示例，请参阅 :example:`system/ulp/lp_core/lp_uart/lp_uart_print`。
+
+* 通过 :ref:`CONFIG_ULP_HP_UART_CONSOLE_PRINT`，将 :cpp:func:`lp_core_printf` 路由到 HP-Core 控制台 UART，可以轻松地将 LP 内核信息打印到已经连接的 HP-Core 控制台 UART。此方法的缺点是需要主 CPU 处于唤醒状态，并且由于 LP 内核与 HP 内未同步，输出可能会交错。
 
 * 通过共享变量共享程序状态：如 :ref:`ulp-lp-core-access-variables` 所述，主 CPU 和 ULP 内核都可以轻松访问 RTC 内存中的全局变量。若想了解 ULP 内核的运行状态，可以将状态信息从 ULP 写入变量中，并通过主 CPU 读取信息。这种方法的缺点在于它需要主 CPU 一直处于唤醒状态，而这通常很难实现。另外，若主 CPU 一直处于唤醒状态，可能会掩盖某些问题，因为部分问题只会在特定电源域断电时发生。
 
-* 紧急处理程序：当检测到异常时，LP-Core 的紧急处理程序会把 LP-Core 寄存器的状态通过 LP-UART 发送出去。将 :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` 选项设置为 ``y``，可以启用紧急处理程序。禁用此选项将减少 LP-Core 应用程序的 LP-RAM 使用量。若想从紧急转储中解析栈回溯，可以使用 esp-idf-monitor_，例如：
+* 紧急处理程序：当检测到异常时，LP 内核的紧急处理程序会把 LP 内核寄存器的状态通过 LP-UART 发送出去。将 :ref:`CONFIG_ULP_PANIC_OUTPUT_ENABLE` 选项设置为 ``y``，可以启用紧急处理程序。禁用此选项将减少 LP 内核应用程序的 LP-RAM 使用量。若想从紧急转储中解析栈回溯，可以使用 esp-idf-monitor_，例如：
 
     .. code-block:: bash
 
         python -m esp_idf_monitor --toolchain-prefix riscv32-esp-elf- --target {IDF_TARGET_NAME} --decode-panic backtrace PATH_TO_ULP_ELF_FILE
 
+调试 ULP LP 内核应用程序：使用 GDB 和 OpenOCD
+----------------------------------------------
 
-应用示例
---------
+与调试 HP 内核类似，也可以用 GDB 和 OpenOCD 来调试 LP 内核上的代码，但要注意其特殊之处和限制条件。
+
+调试会话
+~~~~~~~~
 
-* :example:`system/ulp/lp_core/gpio` 展示了 ULP LP-Core 协处理器在主 CPU 深度睡眠时轮询 GPIO。
+使用支持 LP 内核调试的特殊配置文件来运行 OpenOCD，然后用特殊的 ``gdbinit`` 文件运行 GDB。
+
+.. code-block:: bash
+
+    openocd -f board/{IDF_TARGET_PATH_NAME}-lpcore-builtin.cfg
+    riscv32-esp-elf-gdb -x gdbinit <path to main program ELF>
+
+以下是带有内联注释的 ``gdbinit`` 文件内容，详细信息请参考下一章节。
+
+.. code-block:: bash
+
+    # 连接到目标
+    target extended-remote :3333
+    # 重置芯片
+    mon reset halt
+    maintenance flush register-cache
+    # 添加 ULP 程序的符号和调试信息
+    add-symbol <ULP 程序 ELF 文件路径>
+    # 设置临时硬件断点
+    # 如果需要的断点数量超过硬件支持的数量
+    thb main
+    commands
+    # 在这里设置断点
+    # 此时 ULP 程序已加载到 RAM 中
+    # 若无可用的硬件断点插槽，GDB 将设置软件断点
+    b func1
+    b func2
+    b func3
+    # 恢复执行
+    c
+    end
+    # 重置后启动主程序
+    c
+
+LP 内核调试特性
+~~~~~~~~~~~~~~~
 
-.. only:: esp32c6
+.. list::
 
-    * :example:`system/ulp/lp_core/lp_i2c` 展示了 ULP LP-Core 协处理器在主 CPU 深度睡眠时读取外部 I2C 环境光传感器 (BH1750)，并在达到阈值时唤醒主 CPU。
+    #. 为了方便调试，请在 ULP 应用的 ``CMakeLists.txt`` 文件中添加 ``-O0`` 编译选项。具体操作步骤请参见 :example:`system/ulp/lp_core/debugging/`。
+    :not esp32p4: #. LP 内核支持的硬件异常类型有限，例如，写入地址 `0x0` 不会像在 HP 内核上一样造成系统崩溃。启用 LP 内核应用程序的未定义行为检测器 (`ubsan`) 可以捕捉一些错误，从而在一定程度上弥补这一限制。但请注意，这将显著增加代码量，可能会导致应用程序超出 RTC RAM 的容量限制。要启用 `ubsan`，请在 ``CMakeLists.txt`` 文件中添加 ``-fsanitize=undefined -fno-sanitize=shift-base`` 编译选项。具体操作步骤请参见 :example:`system/ulp/lp_core/debugging/`。
+    #. 为了调试运行在 LP 内核上的程序，需要先将调试信息和符号加载到 GDB 中。这可以通过 GDB 命令行或在 ``gdbinit`` 文件中完成。具体操作步骤请参见上文。
+    #. LP 内核应用程序会在启时会加载到 RAM 中，在此之前设置的所有软件断点都会被覆盖。设置 LP 内核应用断点的最佳时机是在 LP 内核程序运行至 ``main`` 函数之时。
+    #. 使用 IDE 时，可能无法配置上述 ``gdbinit`` 文件中的断点操作或命令。因此，请在调试会话开始前预设并禁用所有断点，只保留 ``main`` 函数处的断点。当程序在 ``main`` 处停止时，手动启用其余断点并恢复执行。
 
-* :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` 展示了低功耗内核上运行的 LP UART 驱动程序如何读取并回显写入串行控制台的数据。
+限制
+~~~~
 
-* :example:`system/ulp/lp_core/lp_uart/lp_uart_print` 展示了如何在低功耗内核上使用串口打印功能。
+#. 调试场景有限制：目前，当 HP 内核或 LP 内核进入睡眠模式时，将无法调适。
+#. 调试 内核时，OpenOCD 不支持 FreeRTOS，因此无法看到系统中正在运行的任务，但会有几个线程代表 HP 和 LP 内核：
 
-* :example:`system/ulp/lp_core/interrupt` 展示了如何在 LP 内核上注册中断处理程序，接收由主 CPU 触发的中断。
+.. code-block:: bash
 
-* :example:`system/ulp/lp_core/gpio_intr_pulse_counter` 展示了如何在主 CPU 处于 Deep-sleep 模式时，使用 GPIO 中断为脉冲计数。
+    (gdb) info thread
+        Id   Target Id                                                          Frame
+        1    Thread 1 "{IDF_TARGET_PATH_NAME}.cpu0" (Name: {IDF_TARGET_PATH_NAME}.cpu0, state: debug-request) 0x40803772 in esp_cpu_wait_for_intr ()
+            at /home/user/projects/esp/esp-idf/components/esp_hw_support/cpu.c:64
+      * 2    Thread 2 "{IDF_TARGET_PATH_NAME}.cpu1" (Name: {IDF_TARGET_PATH_NAME}.cpu1, state: breakpoint)    do_things (max=1000000000)
+            at /home/user/projects/esp/esp-idf/examples/system/ulp/lp_core/debugging/main/lp_core/main.c:21
 
-* :example:`system/ulp/lp_core/build_system/` 演示了如何为 ULP 应用程序添加自定义的 ``CMakeLists.txt`` 文件。
+#. 在 GDB 中设置硬件断点时，这些断点会同时应用到两个内核上，因此可用的硬件断点数量受 LP 内核支持数量（{IDF_TARGET_NAME} 有 {IDF_TARGET_SOC_CPU_BREAKPOINTS_NUM} 个）所限。
+#. OpenOCD 的 flash 支持被禁用。LP 内核应用程序完全在 RAM 中运行，且 GDB 可以为其使用软件断点，因而该限制无关紧要。但若想在 HP 内核运行的代码中调用的 flash 函数（例如 `app_main`）上设置断点，则需要通过 ``hb`` 和 ``thb`` GDB 命令显式请求设置硬件断点。
+#. 由于主程序和 ULP 程序被链接为独立的二进制文件，它们可能会拥有相同名称的全局符号（如函数或变量）。若通过函数名称设置断点，则 GDB 将为所有同名函数设置断点。在调试 LP 内核时，OpenOCD 不支持 flash，因此如果上述函数位于 flash 中，可能会引发问题。此时建议通过源代码行号或函数的内存地址来设置断点。
+
+应用示例
+--------
+
+.. list::
+
+    - :example:`system/ulp/lp_core/gpio` 展示了 ULP LP 内核协处理器在主 CPU 深度睡眠时轮询 GPIO。
+    :esp32c6: - :example:`system/ulp/lp_core/lp_i2c` 展示了 ULP LP 内核协处理器在主 CPU 深度睡眠时读取外部 I2C 环境光传感器 (BH1750)，并在达到阈值时唤醒主 CPU。
+    - :example:`system/ulp/lp_core/lp_uart/lp_uart_echo` 展示了低功耗内核上运行的 LP UART 驱动程序如何读取并回显写入串行控制台的数据。
+    - :example:`system/ulp/lp_core/lp_uart/lp_uart_print` 展示了如何在低功耗内核上使用串口打印功能。
+    - :example:`system/ulp/lp_core/interrupt` 展示了如何在 LP 内核上注册中断处理程序，接收由主 CPU 触发的中断。
+    - :example:`system/ulp/lp_core/gpio_intr_pulse_counter` 展示了如何在主 CPU 处于 Deep-sleep 模式时，使用 GPIO 中断为脉冲计数。
+    - :example:`system/ulp/lp_core/build_system/` 演示了如何为 ULP 应用程序添加自定义的 ``CMakeLists.txt`` 文件。
+    - :example:`system/ulp/lp_core/debugging` 演示了如何使用 GDB 和 OpenOCD 来调试运行在 LP 内核上的代码。
 
 API 参考
--------------
+--------
 
 主 CPU API 参考
-~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~
 
 .. include-build-file:: inc/ulp_lp_core.inc
 .. include-build-file:: inc/lp_core_i2c.inc
@@ -320,7 +400,7 @@ API 参考
 .. include-build-file:: inc/lp_core_types.inc
 
 LP 内核 API 参考
-~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~
 
 .. include-build-file:: inc/ulp_lp_core_utils.inc
 .. include-build-file:: inc/ulp_lp_core_gpio.inc
diff --git a/docs/zh_CN/get-started/index.rst b/docs/zh_CN/get-started/index.rst
index 76fd2d31309..cb6a1ad58fc 100644
--- a/docs/zh_CN/get-started/index.rst
+++ b/docs/zh_CN/get-started/index.rst
@@ -108,19 +108,19 @@
         :maxdepth: 1
 
         ESP32-DevKitC <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32/esp32-devkitc/index.html>
+        ESP32-DevKitM-1 <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32/esp32-devkitm-1/index.html>
         ESP-WROVER-KIT <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32/esp-wrover-kit/index.html>
         ESP32-PICO-KIT <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32/esp32-pico-kit/index.html>
         ESP32-Ethernet-Kit <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32/esp32-ethernet-kit/index.html>
         ESP32-PICO-KIT-1 <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32/esp32-pico-kit-1/index.html>
         ESP32-PICO-DevKitM-2 <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32/esp32-pico-devkitm-2/index.html>
-        ESP32-DevKitM-1 <../hw-reference/esp32/user-guide-devkitm-1>
 
 .. only:: esp32s2
 
     .. toctree::
         :maxdepth: 1
 
-        ESP32-S2-Saola-1 <../hw-reference/esp32s2/user-guide-saola-1-v1.2>
+        ESP32-S2-Saola-1 <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32s2/esp32-s2-saola-1/index.html>
         ESP32-S2-DevKitM-1 <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32s2/esp32-s2-devkitm-1/index.html>
         ESP32-S2-DevKitC-1 <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32s2/esp32-s2-devkitc-1/index.html>
         ESP32-S2-Kaluga-Kit <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32s2/esp32-s2-kaluga-1/index.html>
@@ -139,8 +139,8 @@
     .. toctree::
         :maxdepth: 1
 
-        ESP32-S3-DevKitC-1 <../hw-reference/esp32s3/user-guide-devkitc-1>
-        ESP32-S3-DevKitM-1 <../hw-reference/esp32s3/user-guide-devkitm-1>
+        ESP32-S3-DevKitC-1 <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32s3/esp32-s3-devkitc-1/index.html>
+        ESP32-S3-DevKitM-1 <https://docs.espressif.com/projects/esp-dev-kits/zh_CN/latest/esp32s3/esp32-s3-devkitm-1/index.html>
 
 .. only:: esp32c2
 
diff --git a/docs/zh_CN/get-started/start-project.rst b/docs/zh_CN/get-started/start-project.rst
index ee65b569d6d..ea02c24d357 100644
--- a/docs/zh_CN/get-started/start-project.rst
+++ b/docs/zh_CN/get-started/start-project.rst
@@ -160,7 +160,7 @@
 兼容的 Python 版本
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-ESP-IDF 支持 Python 3.8 及以上版本，建议升级操作系统到最新版本从而更新 Python。也可选择从 `sources <https://www.python.org/downloads/>`_ 安装最新版 Python，或使用 Python 管理系统如 `pyenv <https://github.com/pyenv/pyenv>`_ 对版本进行升级管理。
+ESP-IDF 支持 Python 3.9 及以上版本，建议升级操作系统到最新版本从而更新 Python。也可选择从 `sources <https://www.python.org/downloads/>`_ 安装最新版 Python，或使用 Python 管理系统如 `pyenv <https://github.com/pyenv/pyenv>`_ 对版本进行升级管理。
 
 .. only:: esp32 or esp32s2 or esp32s3
 
diff --git a/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst b/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst
deleted file mode 100644
index f23f4d7c6a5..00000000000
--- a/docs/zh_CN/hw-reference/esp32/user-guide-devkitm-1.rst
+++ /dev/null
@@ -1,335 +0,0 @@
-===================
-ESP32-DevKitM-1
-===================
-
-:link_to_translation:`en: [English]`
-
-本指南将介绍如何使用 ESP32-DevKitM-1，并提供更多关于此开发板的信息。
-
-ESP32-DevKitM-1 是乐鑫推出的一款基于 ESP32-MINI-1/1U 模组的入门级开发板。板上模组大部分管脚均已引出至两侧排针，用户可根据实际需求，通过跳线轻松连接多种外围设备，同时也可将开发板插在面包板上使用。
-
-
-+------------------------+-------------------------+
-| |ESP32-DevKitM-1-正面| | |ESP32-DevKitM-1-侧面|  |
-+------------------------+-------------------------+
-|  ESP32-DevKitM-1-正面  |  ESP32-DevKitM-1-侧面   |
-+------------------------+-------------------------+
-
-.. |ESP32-DevKitM-1-正面| image:: ../../../_static/esp32-DevKitM-1-front.png
-
-.. |ESP32-DevKitM-1-侧面| image:: ../../../_static/esp32-DevKitM-1-isometric.png
-
-
-本指南包括：
-
-- `快速入门`_：提供 ESP32-DevKitM-1 的简要概述及必要的硬件和软件信息。
-- `硬件参考`_：提供 ESP32-DevKitM-1 的详细硬件信息。
-- `相关文档`_：提供相关文档的链接。
-
-
-快速入门
-===========
-
-本节介绍如何开始使用 ESP32-DevKitM-1，主要包括三大部分：首先，介绍一些关于 ESP32-DevKitM-1 的基本信息，然后在 `应用程序开发`_ 章节介绍如何进行硬件初始化，最后介绍如何为 ESP32-DevKitM-1 烧录固件。
-
-
-概述
--------
-
-ESP32-DevKitM-1 开发板是一款小巧实用的开发板，具备以下特色功能：
-
-- 集成了 `ESP32-MINI-1 或 ESP32-MINI-1U <https://www.espressif.com/sites/default/files/documentation/esp32-mini-1_datasheet_cn.pdf>`_ 模组
-- USB 转串口编程接口同时可为开发板供电
-- 设有排针
-- 设有重置按钮和固件下载模式激活按钮
-- 以及其他组件
-
-
-内含组件和包装
----------------
-
-零售订单
-^^^^^^^^^^^
-
-如购买样品，每个 ESP32-DevKitM-1 开发板将以防静电袋或零售商选择的其他方式包装。
-
-零售订单请前往 https://www.espressif.com/zh-hans/company/contact/buy-a-sample。
-
-
-批量订单
-^^^^^^^^^^^
-
-如批量购买，ESP32-DevKitM-1 开发板将以大纸板箱包装。
-
-批量订单请前往 https://www.espressif.com/zh-hans/contact-us/sales-questions。
-
-
-组件介绍
------------
-
-ESP32-DevKitM-1 开发板的主要组件、接口及控制方式见下图。下文以板载 ESP32-MINI-1 的开发板为例进行说明。
-
-
-.. figure:: ../../../_static/esp32-devkitm-1-v1-annotated-photo.png
-    :align: center
-    :alt: ESP32-DevKitM-1 - 正面
-    :figclass: align-center
-
-    ESP32-DevKitM-1 - 正面
-
-
-.. list-table::
-    :widths: 25 75
-    :header-rows: 1
-
-    * - 主要组件
-      - 基本介绍
-    * - 板载模组
-      - ESP32-MINI-1 模组或 ESP32-MINI-1U 模组。ESP32-MINI-1 带有板载 PCB 天线；ESP32-MINI-1U 带有外部天线连接器。两款模组内置的芯片均叠封 4 MB flash。更多详情，请见 `《ESP32-MINI-1 & ESP32-MINI-1U 技术规格书》 <https://www.espressif.com/sites/default/files/documentation/esp32-mini-1_datasheet_cn.pdf>`_
-    * - 5 V 转 3.3 V LDO
-      - 电源转换器，输入 5 V，输出 3.3 V
-    * - Boot 键
-      - 下载按键。按下 **Boot** 键的同时按一下 **Reset** 键进入“固件下载”模式，通过串口下载固件
-    * - Reset 键
-      - 复位按键
-    * - Micro-USB 接口
-      - USB 接口，可用作开发板的供电电源或 PC 和 ESP32 芯片的通信接口
-    * - USB 至 UART 桥接器
-      - 单芯片 USB 至 UART 桥接器，可提供高达 3 Mbps 的传输速率
-    * - 3.3 V 电源指示灯
-      - 开发板连接 USB 电源后，该指示灯亮起。更多信息，请见 `相关文档`_ 中的原理图
-    * - I/O 连接器
-      - 所有可用 GPIO 管脚（除 Flash 的 SPI 总线）均已引出至开发板的排针。用户可对 ESP32 芯片编程，开发多种功能
-
-
-应用程序开发
----------------
-
-ESP32-DevKitM-1 上电前，请首先确认开发板完好无损。
-
-
-硬件准备
-^^^^^^^^^^^^
-
-- ESP32-DevKitM-1 开发板
-- USB A / micro USB B 数据线
-- PC（Windows、Linux 或 macS）
-
-
-软件设置
-^^^^^^^^^^^
-
-现在，请前往 :doc:`../../get-started/index` 中的 :ref:`get-started-step-by-step` 章节，查看如何设置开发环境，并尝试将示例项目烧录至你的开发板。
-
-.. attention::
-
-  对于 2021 年 12 月 2 日之前生产的 ESP32-DevKitM-1，其搭载的模组为单核 MCU 模组。请查看 `PCN-2021-021 <https://www.espressif.com/sites/default/files/pcn_downloads/PCN-2021-021%20ESP32-U4WDH%20%E5%8D%87%E7%BA%A7%E4%B8%BA%E5%8F%8C%E6%A0%B8%E5%A4%84%E7%90%86%E5%99%A8%E4%BA%A7%E5%93%81.pdf>`_ 以确定开发板上搭载的模组是否为单核模组。对于搭载单核模组的开发板，烧录应用程序前，需要在 :ref:`menuconfig <get-started-configure>` 中启用单核模式 (:ref:`CONFIG_FREERTOS_UNICORE`)。
-
-
-硬件参考
-===========
-
-功能框图
-----------
-
-ESP32-DevKitM-1 的主要组件和连接方式如下图所示。
-
-.. figure:: ../../../_static/esp32-DevKitM-1_v1_SystemBlock.png
-    :align: center
-    :alt: ESP32-DevKitM-1
-    :figclass: align-center
-
-    ESP32-DevKitM-1
-
-
-电源选项
-----------
-
-开发板可从以下三种供电方式中任选其一：
-
-* Micro USB 供电（默认）
-* 5V / GND 管脚供电
-* 3V3 / GND 管脚供电
-
-.. warning::
-
-  - 上述供电模式 **不可同时连接**，否则可能会损坏开发板和/或电源。
-  - 建议选择第一种供电方式：Micro USB 端口供电。
-
-
-管脚描述
-----------
-
-开发板两侧 I/O 管脚，其具体名称和功能见下表。外设管脚分配请参考 `《ESP32 技术规格书》`_。
-
-.. list-table::
-   :header-rows: 1
-   :widths: 10 12 12 66
-
-
-   * - 编号
-     - 名称
-     - 类型 [1]_
-     - 功能
-   * - 1
-     - GND
-     - P
-     - 接地
-   * - 2
-     - 3V3
-     - P
-     - 3.3 V 电源
-   * - 3
-     - I36
-     - I
-     - GPIO36, ADC1_CH0, RTC_GPIO0
-   * - 4
-     - I37
-     - I
-     - GPIO37, ADC1_CH1, RTC_GPIO1
-   * - 5
-     - I38
-     - I
-     - GPIO38, ADC1_CH2, RTC_GPIO2
-   * - 6
-     - I39
-     - I
-     - GPIO39, ADC1_CH3, RTC_GPIO3
-   * - 7
-     - RST
-     - I
-     - 复位；高电平：使能；低电平：关闭
-   * - 8
-     - I34
-     - I
-     - GPIO34, ADC1_CH6, RTC_GPIO4
-   * - 9
-     - I35
-     - I
-     - GPIO35, ADC1_CH7, RTC_GPIO5
-   * - 10
-     - IO32
-     - I/O
-     - GPIO32, XTAL_32K_P (32.768 kHz crystal oscillator input), ADC1_CH4, TOUCH9, RTC_GPIO9
-   * - 11
-     - IO33
-     - I/O
-     - GPIO33, XTAL_32K_N (32.768 kHz crystal oscillator output), ADC1_CH5, TOUCH8, RTC_GPIO8
-   * - 12
-     - IO25
-     - I/O
-     - GPIO25, DAC_1, ADC2_CH8, RTC_GPIO6, EMAC_RXD0
-   * - 13
-     - IO26
-     - I/O
-     - GPIO26, DAC_2, ADC2_CH9, RTC_GPIO7, EMAC_RXD1
-   * - 14
-     - IO27
-     - I/O
-     - GPIO27, ADC2_CH7, TOUCH7, RTC_GPIO17, EMAC_RX_DV
-   * - 15
-     - IO14
-     - I/O
-     - GPIO14, ADC2_CH6, TOUCH6, RTC_GPIO16, MTMS, HSPICLK, HS2_CLK, SD_CLK, EMAC_TXD2
-   * - 16
-     - 5V
-     - P
-     - 5 V 电源
-   * - 17
-     - IO12
-     - I/O
-     - GPIO12, ADC2_CH5, TOUCH5, RTC_GPIO15, MTDI [2]_, HSPIQ, HS2_DATA2, SD_DATA2, EMAC_TXD3
-   * - 18
-     - IO13
-     - I/O
-     - GPIO13, ADC2_CH4, TOUCH4, RTC_GPIO14, MTCK, HSPID, HS2_DATA3, SD_DATA3, EMAC_RX_ER
-   * - 19
-     - IO15
-     - I/O
-     - GPIO15, ADC2_CH3, TOUCH3, RTC_GPIO13, MTDO [2]_, HSPICS0, HS2_CMD, SD_CMD, EMAC_RXD3
-   * - 20
-     - IO2
-     - I/O
-     - GPIO2 [2]_, ADC2_CH2, TOUCH2, RTC_GPIO12, HSPIWP, HS2_DATA0, SD_DATA0
-   * - 21
-     - IO0
-     - I/O
-     - GPIO0 [2]_, ADC2_CH1, TOUCH1, RTC_GPIO11, CLK_OUT1, EMAC_TX_CLK
-   * - 22
-     - IO4
-     - I/O
-     - GPIO4, ADC2_CH0, TOUCH0, RTC_GPIO10, HSPIHD, HS2_DATA1, SD_DATA1, EMAC_TX_ER
-   * - 23
-     - IO9
-     - I/O
-     - GPIO9, HS1_DATA2, U1RXD, SD_DATA2
-   * - 24
-     - IO10
-     - I/O
-     - GPIO10, HS1_DATA3, U1TXD, SD_DATA3
-   * - 25
-     - IO5
-     - I/O
-     - GPIO5 [2]_, HS1_DATA6, VSPICS0, EMAC_RX_CLK
-   * - 26
-     - IO18
-     - I/O
-     - GPIO18, HS1_DATA7, VSPICLK
-   * - 27
-     - IO23
-     - I/O
-     - GPIO23, HS1_STROBE, VSPID
-   * - 28
-     - IO19
-     - I/O
-     - GPIO19, VSPIQ, U0CTS, EMAC_TXD0
-   * - 29
-     - IO22
-     - I/O
-     - GPIO22, VSPIWP, U0RTS, EMAC_TXD1
-   * - 30
-     - IO21
-     - I/O
-     - GPIO21, VSPIHD, EMAC_TX_EN
-   * - 31
-     - TXD0
-     - I/O
-     - GPIO1, U0TXD, CLK_OUT3, EMAC_RXD2
-   * - 32
-     - RXD0
-     - I/O
-     - GPIO3, U0RXD, CLK_OUT2
-
-.. [1] P：电源；I：输入；O：输出。
-.. [2] MTDI、GPIO0、GPIO2、MTDO 和 GPIO5 为 Strapping 管脚。在芯片上电和系统复位过程中，Strapping 管脚根据管脚的二进制电压值控制芯片功能。Strapping 管脚的具体描述和应用，请参考 `《ESP32 技术规格书》`_ > 章节 Strapping 管脚。
-
-
-管脚布局
-^^^^^^^^
-
-.. figure:: ../../../_static/ESP32_DevKitM-1_pinlayout.png
-    :align: center
-    :scale: 43%
-    :alt: ESP32-DevKitM-1 （点击放大）
-    :figclass: align-center
-
-    ESP32-DevKitM-1 （点击放大）
-
-
-硬件修订历史
-===============
-
-尚无版本升级历史。
-
-
-相关文档
-============
-
-* `《ESP32-MINI-1 & ESP32-MINI-1U 技术规格书》 <https://www.espressif.com/sites/default/files/documentation/esp32-mini-1_datasheet_cn.pdf>`_ (PDF)
-* `ESP32-DevKitM-1 原理图 <https://dl.espressif.com/dl/schematics/SCH_ESP32-DEVKITM-1_V1_20200910A.pdf>`_ (PDF)
-* `ESP32-DevKitM-1 PCB 布局图 <https://dl.espressif.com/dl/schematics/PCB_ESP32-DevKitM-1_V1_20200910AE.pdf>`_ (PDF)
-* `ESP32-DevKitM-1 布局图 <https://dl.espressif.com/dl/schematics/ESP32-DevKitM-1_V1.dxf>`_ (DXF) - 可使用 `Autodesk Viewer <https://viewer.autodesk.com/>`_ 查看
-* `乐鑫产品选型工具 <https://products.espressif.com/#/product-selector?names=>`_
-* `《ESP32 技术规格书》 <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_cn.pdf>`_ (PDF)
-
-有关本开发板的更多设计文档，请联系我们的商务部门 sales@espressif.com。
diff --git a/docs/zh_CN/hw-reference/esp32s2/user-guide-saola-1-v1.2.rst b/docs/zh_CN/hw-reference/esp32s2/user-guide-saola-1-v1.2.rst
deleted file mode 100644
index fbde889144d..00000000000
--- a/docs/zh_CN/hw-reference/esp32s2/user-guide-saola-1-v1.2.rst
+++ /dev/null
@@ -1,262 +0,0 @@
-================
-ESP32-S2-Saola-1
-================
-
-:link_to_translation:`en: [English]`
-
-本指南介绍了乐鑫一款基于 `ESP32-S2 <https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_cn.pdf>`_ 的小型开发板 ESP32-S2-Saola-1。
-
-.. figure:: ../../../_static/esp32-s2-saola-1-v1.2-isometric.png
-    :align: center
-    :alt: ESP32-S2-Saola-1
-    :figclass: align-center
-
-    ESP32-S2-Saola-1
-
-本指南包括如下内容：
-
-- `入门指南`_：简要介绍了 ESP32-S2-Saola-1 和硬件、软件设置指南。
-- `硬件参考`_：详细介绍了 ESP32-S2-Saola-1 的硬件。
-- `硬件版本`_：介绍硬件历史版本和已知问题，并提供链接至历史版本开发板的入门指南（如有）。
-- `相关文档`_：列出了相关文档的链接。
-
-
-入门指南
-========
-
-本节介绍了如何快速上手 ESP32-S2-Saola-1。开头部分介绍了 ESP32-S2-Saola-1，`开始开发应用`_ 小节介绍了怎样在 ESP32-S2-Saola-1 上安装模组、设置及烧录固件。
-
-
-概述
-----
-
-ESP32-S2-Saola-1 是乐鑫一款基于 ESP32-S2 的小型开发板。板上的绝大部分管脚均已引出，开发人员可根据实际需求，轻松通过跳线连接多种外围器件，或将开发板插在面包板上使用。
-
-为了更好地满足不同用户需求，ESP32-S2-Saola-1 支持以下模组：
-
-- `ESP32-S2-WROVER <https://www.espressif.com/sites/default/files/documentation/esp32-s2-wrover_esp32-s2-wrover-i_datasheet_cn.pdf>`_
-- `ESP32-S2-WROVER-I <https://www.espressif.com/sites/default/files/documentation/esp32-s2-wrover_esp32-s2-wrover-i_datasheet_cn.pdf>`_
-- `ESP32-S2-WROOM <https://www.espressif.com/sites/default/files/documentation/esp32-s2-wroom_esp32-s2-wroom-i_datasheet_cn.pdf>`_
-- `ESP32-S2-WROOM-I <https://www.espressif.com/sites/default/files/documentation/esp32-s2-wroom_esp32-s2-wroom-i_datasheet_cn.pdf>`_
-
-本指南以搭载 ESP32-S2-WROVER 模组的 ESP32-S2-Saola-1 为例。
-
-
-内含组件和包装
---------------
-
-零售订单
-^^^^^^^^
-
-如购买样品，每个 ESP32-S2-Saola-1 开发板将以防静电袋或零售商选择的其他方式包装。
-
-零售订单请前往 https://www.espressif.com/zh-hans/company/contact/buy-a-sample。
-
-
-批量订单
-^^^^^^^^
-
-如批量购买，ESP32-S2-Saola-1 开发板将以大纸板箱包装。
-
-批量订单请前往 https://www.espressif.com/zh-hans/contact-us/sales-questions。
-
-
-组件介绍
---------
-
-.. _user-guide-saola-1-v1.2-board-front:
-
-.. figure:: ../../../_static/esp32-s2-saola-1-v1.2-annotated-photo.png
-    :align: center
-    :alt: ESP32-S2-Saola-1 - 正面
-    :figclass: align-center
-
-    ESP32-S2-Saola-1 - 正面
-
-以下按照顺时针的顺序依次介绍开发板上的主要组件。
-
-.. list-table::
-   :widths: 30 70
-   :header-rows: 1
-
-   * - 主要组件
-     - 介绍
-   * - ESP32-S2-WROVER
-     - ESP32-S2-WROVER 集成 ESP32-S2，是通用型 Wi-Fi MCU 模组，功能强大。该模组采用 PCB 板载天线，配置了 4 MB SPI flash 和 2 MB SPI PSRAM。
-   * - Pin Headers（排针）
-     - 所有可用 GPIO 管脚（除 Flash 和 PSRAM 的 SPI 总线）均已引出至开发板的排针。用户可对 ESP32-S2 芯片编程，使能 SPI、I2S、UART、I2C、触摸传感器、PWM 等多种功能。
-   * - 3.3 V Power On LED（3.3 V 电源指示灯）
-     - 开发板连接 USB 电源后，该指示灯亮起。
-   * - USB-to-UART Bridge（USB 转 UART 桥接器）
-     - 单芯片 USB 至 UART 桥接器，可提供高达 3 Mbps 的传输速率。
-   * - Reset Button（Reset 键）
-     - 复位按键。
-   * - Micro-USB Port（Micro-USB 接口）
-     - USB 接口。可用作开发板的供电电源或 PC 和 ESP32-S2 芯片的通信接口。
-   * - Boot Button（Boot 键）
-     - 下载按键。按住 **Boot** 键的同时按一下 **Reset** 键进入“固件下载”模式，通过串口下载固件。
-   * - RGB LED
-     - 可寻址 RGB 发光二极管 (WS2812)，由 GPIO18 驱动。
-
-
-开始开发应用
-------------
-
-通电前，请确保 ESP32-S2-Saola-1 完好无损。
-
-
-必备硬件
-^^^^^^^^
-
-- ESP32-S2-Saola-1
-- USB 2.0 数据线（标准 A 型转 Micro-B 型）
-- 电脑（Windows、Linux 或 macOS）
-
-.. 注解::
-
-  请确保使用适当的 USB 数据线。部分数据线仅可用于充电，无法用于数据传输和编程。
-
-
-软件设置
-^^^^^^^^
-
-请前往 :doc:`../../get-started/index`，在 :ref:`get-started-step-by-step` 一节查看如何快速设置开发环境，将应用程序烧录至 ESP32-S2-Saola-1。
-
-.. 注解::
-
-    ESP32-S2 系列芯片仅支持 ESP-IDF master 分支或 v4.2 以上版本。
-
-
-硬件参考
-========
-
-功能框图
---------
-
-ESP32-S2-Saola-1 的主要组件和连接方式如下图所示。
-
-.. figure:: ../../../_static/esp32-s2-saola-1-v1.2-block-diags.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S2-Saola-1 （点击放大）
-    :figclass: align-center
-
-    ESP32-S2-Saola-1 （点击放大）
-
-
-电源选项
-^^^^^^^^
-
-以下任一供电方式均可给 ESP32-S2-Saola-1 供电：
-
-- Micro-USB 接口供电（默认）
-- 5V 和 GND 排针供电
-- 3V3 和 GND 排针供电
-
-建议选择第一种供电方式：Micro-USB 接口供电。
-
-
-排针
-----
-
-下表列出了开发板两侧排针（J2 和 J3）的 **名称** 和 **功能**，排针的名称如图 :ref:`user-guide-saola-1-v1.2-board-front` 所示，排针的序号与 `ESP32-S2-Saola-1 原理图`_ (PDF) 一致。
-
-
-J2
-^^^
-
-==== ====  =========   ======================================
-序号 名称  类型 [#]_    功能
-==== ====  =========   ======================================
-1    3V3    P          3.3 V 电源
-2    IO0    I/O        GPIO0, 启动
-3    IO1    I/O        GPIO1, ADC1_CH0, TOUCH_CH1
-4    IO2    I/O        GPIO2, ADC1_CH1, TOUCH_CH2
-5    IO3    I/O        GPIO3, ADC1_CH2, TOUCH_CH3
-6    IO4    I/O        GPIO4, ADC1_CH3, TOUCH_CH4
-7    IO5    I/O        GPIO5, ADC1_CH4, TOUCH_CH5
-8    IO6    I/O        GPIO6, ADC1_CH5, TOUCH_CH6
-9    IO7    I/O        GPIO7, ADC1_CH6, TOUCH_CH7
-10   IO8    I/O        GPIO8, ADC1_CH7, TOUCH_CH8
-11   IO9    I/O        GPIO9, ADC1_CH8, TOUCH_CH9
-12   IO10   I/O        GPIO10, ADC1_CH9, TOUCH_CH10
-13   IO11   I/O        GPIO11, ADC2_CH0, TOUCH_CH11
-14   IO12   I/O        GPIO12, ADC2_CH1, TOUCH_CH12
-15   IO13   I/O        GPIO13, ADC2_CH2, TOUCH_CH13
-16   IO14   I/O        GPIO14, ADC2_CH3, TOUCH_CH14
-17   IO15   I/O        GPIO15, ADC2_CH4, XTAL_32K_P
-18   IO16   I/O        GPIO16, ADC2_CH5, XTAL_32K_N
-19   IO17   I/O        GPIO17, ADC2_CH6, DAC_1
-20   5V0    P          5 V 电源
-21   GND    G          接地
-==== ====  =========   ======================================
-
-
-J3
-^^^
-
-====  ====  =====  ====================================
-序号  名称   类型    功能
-====  ====  =====  ====================================
-1     GND   G      接地
-2     RST   I      CHIP_PU, 复位
-3     IO46  I      GPIO46
-4     IO45  I/O    GPIO45
-5     IO44  I/O    GPIO44, U0RXD
-6     IO43  I/O    GPIO43, U0TXD
-7     IO42  I/O    GPIO42, MTMS
-8     IO41  I/O    GPIO41, MTDI
-9     IO40  I/O    GPIO40, MTDO
-10    IO39  I/O    GPIO39, MTCK
-11    IO38  I/O    GPIO38
-12    IO37  I/O    GPIO37
-13    IO36  I/O    GPIO36
-14    IO35  I/O    GPIO35
-16    IO34  I/O    GPIO34
-17    IO33  I/O    GPIO33
-17    IO26  I/O    GPIO26
-18    IO21  I/O    GPIO21
-19    IO20  I/O    GPIO20, ADC2_CH9, USB_D+
-20    IO19  I/O    GPIO19, ADC2_CH8, USB_D-
-21    IO18  I/O    GPIO18, ADC2_CH7, DAC_2, RGB LED
-====  ====  =====  ====================================
-
-.. [#] P：电源；I：输入；O：输出；T：可设置为高阻。
-
-
-管脚布局
-^^^^^^^^
-
-.. figure:: ../../../_static/esp32-s2_saola1-pinout.jpg
-    :align: center
-    :scale: 45%
-    :alt: ESP32-S2-Saola-1 管脚布局（点击放大）
-    :figclass: align-center
-
-    ESP32-S2-Saola-1 管脚布局（点击放大）
-
-
-硬件版本
-==========
-
-无历史版本。
-
-
-相关文档
-========
-
-* `ESP32-S2-Saola-1 原理图`_ (PDF)
-* `ESP32-S2-Saola-1 尺寸图`_ (PDF)
-* `ESP32-S2 技术规格书`_ (PDF)
-* `ESP32-S2-WROVER & ESP32-S2-WROVER-I 技术规格书`_ (PDF)
-* `ESP32-S2-WROOM & ESP32-S2-WROOM-I 技术规格书`_ (PDF)
-* `乐鑫产品选型工具`_
-
-有关本开发板的更多设计文档，请联系我们的商务部门 `sales@espressif.com <sales@espressif.com>`_。
-
-.. _ESP32-S2-Saola-1 原理图: https://dl.espressif.com/dl/schematics/ESP32-S2-SAOLA-1_V1.1_schematics.pdf
-.. _ESP32-S2-Saola-1 尺寸图: https://dl.espressif.com/dl/schematics/ESP32-S2-Saola-1_V1.2_Dimensions.pdf
-.. _ESP32-S2 技术规格书: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_cn.pdf
-.. _ESP32-S2-WROVER & ESP32-S2-WROVER-I 技术规格书: https://www.espressif.com/sites/default/files/documentation/esp32-s2-wrover_esp32-s2-wrover-i_datasheet_cn.pdf
-.. _ESP32-S2-WROOM & ESP32-S2-WROOM-I 技术规格书: https://www.espressif.com/sites/default/files/documentation/esp32-s2-wroom_esp32-s2-wroom-i_datasheet_cn.pdf
-.. _乐鑫产品选型工具: https://products.espressif.com/#/product-selector?names=
diff --git a/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1-v1.0.rst b/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1-v1.0.rst
deleted file mode 100644
index 4db1d60fb30..00000000000
--- a/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1-v1.0.rst
+++ /dev/null
@@ -1,320 +0,0 @@
-===================
-ESP32-S3-DevKitC-1
-===================
-
-:link_to_translation:`en: [English]`
-
-最新版本：:doc:`user-guide-devkitc-1`
-
-本指南将帮助你快速上手 ESP32-S3-DevKitC-1，并提供该款开发板的详细信息。
-
-ESP32-S3-DevKitC-1 是一款入门级开发板，搭载 Wi-Fi + Bluetooth® LE 模组 ESP32-S3-WROOM-1、ESP32-S3-WROOM-1U 或 ESP32-S3-WROOM-2。
-
-板上模组的大部分管脚均已引出至开发板两侧排针，开发人员可根据实际需求，轻松通过跳线连接多种外围设备，也可将开发板插在面包板上使用。
-
-.. figure:: ../../../_static/esp32-s3-devkitc-1-v1-isometric.png
-    :align: center
-    :alt: ESP32-S3-DevKitC-1（板载 ESP32-S3-WROOM-1 模组）
-
-    ESP32-S3-DevKitC-1（板载 ESP32-S3-WROOM-1 模组）
-
-
-本指南包括如下内容：
-
-- `入门指南`_：简要介绍了开发板和硬件、软件设置指南。
-- `硬件参考`_：详细介绍了开发板的硬件。
-- `硬件版本`_：介绍硬件历史版本和已知问题，并提供链接至历史版本开发板的入门指南（如有）。
-- `相关文档`_：列出了相关文档的链接。
-
-
-入门指南
-========
-
-本小节将简要介绍 ESP32-S3-DevKitC-1，说明如何在 ESP32-S3-DevKitC-1 上烧录固件及相关准备工作。
-
-
-组件介绍
---------
-
-.. _user-guide-s3-devkitc-1-v1-board-front:
-
-.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png
-    :align: center
-    :alt: ESP32-S3-DevKitC-1 - 正面
-
-    ESP32-S3-DevKitC-1 - 正面
-
-以下按照逆时针的顺序依次介绍开发板上的主要组件。
-
-.. list-table::
-   :widths: 30 70
-   :header-rows: 1
-
-   * - 主要组件
-     - 介绍
-   * - ESP32-S3-WROOM-1/1U/2
-     - ESP32-S3-WROOM-1、ESP32-S3-WROOM-1U 和 ESP32-S3-WROOM-2 是通用型 Wi-Fi + 低功耗蓝牙 MCU 模组，具有丰富的外设接口、强大的神经网络运算能力和信号处理能力，专为人工智能和 AIoT 市场打造。ESP32-S3-WROOM-1 和 ESP32-S3-WROOM-2 采用 PCB 板载天线，ESP32-S3-WROOM-1U 采用连接器连接外部天线。
-   * - 5 V to 3.3 V LDO（5 V 转 3.3 V LDO）
-     - 电源转换器，输入 5 V，输出 3.3 V。
-   * - Pin Headers（排针）
-     - 所有可用 GPIO 管脚（除 flash 的 SPI 总线）均已引出至开发板的排针。请查看 :ref:`user-guide-s3-devkitc-1-v1-header-blocks` 获取更多信息。
-   * - USB-to-UART Port（USB 转 UART 接口）
-     - Micro-USB 接口，可用作开发板的供电接口，可烧录固件至芯片，也可作为通信接口，通过板载 USB 转 UART 桥接器与芯片通信。
-   * - Boot Button（Boot 键）
-     - 下载按键。按住 **Boot** 键的同时按一下 **Reset** 键进入“固件下载”模式，通过串口下载固件。
-   * - Reset Button（Reset 键）
-     - 复位按键。
-   * - ESP32-S3 USB Port（ESP32-S3 USB 接口）
-     - ESP32-S3 USB OTG 接口，支持全速 USB 1.1 标准。ESP32-S3 USB 接口可用作开发板的供电接口，可烧录固件至芯片，可通过 USB 协议与芯片通信，也可用于 JTAG 调试。
-   * - USB-to-UART Bridge（USB 转 UART 桥接器）
-     - 单芯片 USB 至 UART 桥接器，可提供高达 3 Mbps 的传输速率。
-   * - RGB LED
-     - 可寻址 RGB 发光二极管，由 GPIO48 驱动。
-   * - 3.3 V Power On LED（3.3 V 电源指示灯）
-     - 开发板连接 USB 电源后，该指示灯亮起。
-
-.. note::
-
-  在板载 ESP32-S3-WROOM-1/1U 模组系列（使用 8 线 SPI flash/PSRAM）的开发板和板载 ESP32-S3-WROOM-2 模组系列的开发板中，管脚 GPIO35、GPIO36 和 GPIO37 已用于内部 ESP32-S3 芯片与 SPI flash/PSRAM 之间的通信，外部不可使用。
-
-
-开始开发应用
--------------
-
-通电前，请确保开发板完好无损。
-
-
-必备硬件
-^^^^^^^^
-
-- ESP32-S3-DevKitC-1
-- USB 2.0 数据线（标准 A 型转 Micro-B 型）
-- 电脑（Windows、Linux 或 macOS）
-
-.. 注解::
-
-  请确保使用适当的 USB 数据线。部分数据线仅可用于充电，无法用于数据传输和编程。
-
-
-硬件设置
-^^^^^^^^
-
-通过 **USB 转 UART 接口** 连接开发板与电脑。软件暂不支持通过 **ESP32-S3 USB 接口** 连接。在后续步骤中，默认使用 **USB 转 UART 接口**。
-
-
-软件设置
-^^^^^^^^
-
-请前往 :doc:`../../get-started/index`，在 :ref:`get-started-step-by-step` 小节查看如何快速设置开发环境，将应用程序烧录至你的开发板。
-
-
-内含组件和包装
----------------
-
-订购信息
-^^^^^^^^^^^^^^
-
-该开发板有多种型号可供选择，详见下表。
-
-.. list-table::
-   :widths: 28 29 19 17 15
-   :header-rows: 1
-
-   * - 订购代码
-     - 搭载模组
-     - Flash
-     - PSRAM
-     - SPI 电压
-   * - ESP32-S3-DevKitC-1-N8
-     - ESP32-S3-WROOM-1-N8
-     - 8 MB QD
-     - —
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N8R2
-     - ESP32-S3-WROOM-1-N8R2
-     - 8 MB QD
-     - 2 MB QD
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N8R8
-     - ESP32-S3-WROOM-1-N8R8
-     - 8 MB QD
-     - 8 MB OT
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N16R8V
-     - ESP32-S3-WROOM-2-N16R8V
-     - 16 MB OT
-     - 8 MB OT
-     - 1.8 V
-   * - ESP32-S3-DevKitC-1-N32R8V
-     - ESP32-S3-WROOM-2-N32R8V
-     - 32 MB OT
-     - 8 MB OT
-     - 1.8 V
-   * - ESP32-S3-DevKitC-1U-N8
-     - ESP32-S3-WROOM-1U-N8
-     - 8 MB QD
-     - —
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1U-N8R2
-     - ESP32-S3-WROOM-1U-N8R2
-     - 8 MB QD
-     - 2 MB QD
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1U-N8R8
-     - ESP32-S3-WROOM-1U-N8R8
-     - 8 MB QD
-     - 8 MB OT
-     - 3.3 V
-
-.. note::
-
-  上表中，QD 指代 Quad SPI，OT 指代 Octal SPI。
-
-
-零售订单
-^^^^^^^^
-
-如购买样品，每个开发板将以防静电袋或零售商选择的其他方式包装。
-
-零售订单请前往 https://www.espressif.com/zh-hans/company/contact/buy-a-sample。
-
-
-批量订单
-^^^^^^^^
-
-如批量购买，开发板将以大纸板箱包装。
-
-批量订单请前往 https://www.espressif.com/zh-hans/contact-us/sales-questions。
-
-
-硬件参考
-========
-
-功能框图
---------
-
-ESP32-S3-DevKitC-1 的主要组件和连接方式如下图所示。
-
-.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S3-DevKitC-1（点击放大）
-
-    ESP32-S3-DevKitC-1（点击放大）
-
-
-电源选项
-^^^^^^^^
-
-以下任一供电方式均可给开发板供电：
-
-- USB 转 UART 接口供电或 ESP32-S3 USB 接口供电（选择其一或同时供电），默认供电方式（推荐）
-- 5V 和 G (GND) 排针供电
-- 3V3 和 G (GND) 排针供电
-
-
-.. _user-guide-s3-devkitc-1-v1-header-blocks:
-
-排针
-----
-
-下表列出了开发板两侧排针（J1 和 J3）的 **名称** 和 **功能**，排针的名称如图 :ref:`user-guide-s3-devkitc-1-v1-board-front` 所示，排针的序号与 `开发板原理图 <https://dl.espressif.com/dl/SCH_ESP32-S3-DEVKITC-1_V1_20210312C.pdf>`_ (PDF) 一致。
-
-
-J1
-^^^
-
-====  ====  ==========  =====================================================================
-序号  名称   类型 [#]_    功能
-====  ====  ==========  =====================================================================
-1     3V3   P            3.3 V 电源
-2     3V3   P            3.3 V 电源
-3     RST   I            EN
-4     4     I/O/T        RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
-5     5     I/O/T        RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
-6     6     I/O/T        RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
-7     7     I/O/T        RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
-8     15    I/O/T        RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
-9     16    I/O/T        RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
-10    17    I/O/T        RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
-11    18    I/O/T        RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3
-12    8     I/O/T        RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
-13    3     I/O/T        RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
-14    46    I/O/T        GPIO46
-15    9     I/O/T        RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD
-16    10    I/O/T        RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS0
-17    11    I/O/T        RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID
-18    12    I/O/T        RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK
-19    13    I/O/T        RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ
-20    14    I/O/T        RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP
-21    5V    P            5 V 电源
-22    G     G            接地
-====  ====  ==========  =====================================================================
-
-
-J3
-^^^
-
-====  ====  ==========  =====================================================================
-序号  名称   类型          功能
-====  ====  ==========  =====================================================================
-1      G     G            接地
-2      TX    I/O/T        U0TXD, GPIO43, CLK_OUT1
-3      RX    I/O/T        U0RXD, GPIO44, CLK_OUT2
-4      1     I/O/T        RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
-5      2     I/O/T        RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
-6      42    I/O/T        MTMS, GPIO42
-7      41    I/O/T        MTDI, GPIO41, CLK_OUT1
-8      40    I/O/T        MTDO, GPIO40, CLK_OUT2
-9      39    I/O/T        MTCK, GPIO39, CLK_OUT3, SUBSPICS1
-10     38    I/O/T        GPIO38, FSPIWP, SUBSPIWP
-11     37    I/O/T        SPIDQS, GPIO37, FSPIQ, SUBSPIQ
-12     36    I/O/T        SPIIO7, GPIO36, FSPICLK, SUBSPICLK
-13     35    I/O/T        SPIIO6, GPIO35, FSPID, SUBSPID
-14     0     I/O/T        RTC_GPIO0, GPIO0
-15     45    I/O/T        GPIO45
-16     48    I/O/T        GPIO48, SPICLK_N, SUBSPICLK_N_DIFF, RGB LED
-17     47    I/O/T        GPIO47, SPICLK_P, SUBSPICLK_P_DIFF
-18     21    I/O/T        RTC_GPIO21, GPIO21
-19     20    I/O/T        RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
-20     19    I/O/T        RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
-21     G     G            接地
-22     G     G            接地
-====  ====  ==========  =====================================================================
-
-
-.. [#] P：电源；I：输入；O：输出；T：可设置为高阻。
-
-
-有关管脚功能名称的解释，请参考 `芯片规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_cn.pdf>`_ (PDF)。
-
-
-管脚布局
-^^^^^^^^^^^
-
-.. figure:: ../../../_static/ESP32-S3_DevKitC-1_pinlayout.jpg
-    :align: center
-    :scale: 50%
-    :alt: ESP32-S3-DevKitC-1（点击放大）
-
-    ESP32-S3-DevKitC-1 管脚布局（点击放大）
-
-
-硬件版本
-============
-
-无历史版本。
-
-
-相关文档
-========
-
-- `ESP32-S3 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_cn.pdf>`_ (PDF)
-- `ESP32-S3-WROOM-1 & ESP32-S3-WROOM-1U 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_cn.pdf>`_ (PDF)
-- `ESP32-S3-WROOM-2 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-2_datasheet_cn.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 原理图 <https://dl.espressif.com/dl/SCH_ESP32-S3-DEVKITC-1_V1_20210312C.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 PCB 布局图 <https://dl.espressif.com/dl/PCB_ESP32-S3-DevKitC-1_V1_20210312CB.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 尺寸图 <https://dl.espressif.com/dl/DXF_ESP32-S3-DevKitC-1_V1_20210312CB.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 尺寸图源文件 <https://dl.espressif.com/dl/DXF_ESP32-S3-DevKitC-1_V1_20210312CB.dxf>`_ (DXF) - 可使用 `Autodesk Viewer <https://viewer.autodesk.com/>`_ 查看
-
-有关本开发板的更多设计文档，请联系我们的商务部门 `sales@espressif.com <sales@espressif.com>`_。
diff --git a/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1.rst b/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1.rst
deleted file mode 100644
index 7038a658d54..00000000000
--- a/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitc-1.rst
+++ /dev/null
@@ -1,329 +0,0 @@
-========================
-ESP32-S3-DevKitC-1 v1.1
-========================
-
-:link_to_translation:`en: [English]`
-
-更早版本：:doc:`user-guide-devkitc-1-v1.0`
-
-本指南将帮助你快速上手 ESP32-S3-DevKitC-1，并提供该款开发板的详细信息。
-
-ESP32-S3-DevKitC-1 是一款入门级开发板，搭载 Wi-Fi + Bluetooth® LE 模组 ESP32-S3-WROOM-1、ESP32-S3-WROOM-1U 或 ESP32-S3-WROOM-2。
-
-板上模组的大部分管脚均已引出至开发板两侧排针，开发人员可根据实际需求，轻松通过跳线连接多种外围设备，也可将开发板插在面包板上使用。
-
-.. figure:: ../../../_static/esp32-s3-devkitc-1-v1.1-isometric.png
-    :align: center
-    :alt: ESP32-S3-DevKitC-1（板载 ESP32-S3-WROOM-1 模组）
-
-    ESP32-S3-DevKitC-1（板载 ESP32-S3-WROOM-1 模组）
-
-
-本指南包括如下内容：
-
-- `入门指南`_：简要介绍了开发板和硬件、软件设置指南。
-- `硬件参考`_：详细介绍了开发板的硬件。
-- `硬件版本`_：介绍硬件历史版本和已知问题，并提供链接至历史版本开发板的入门指南（如有）。
-- `相关文档`_：列出了相关文档的链接。
-
-
-入门指南
-========
-
-本小节将简要介绍 ESP32-S3-DevKitC-1，说明如何在 ESP32-S3-DevKitC-1 上烧录固件及相关准备工作。
-
-
-组件介绍
---------
-
-.. _user-guide-s3-devkitc-1-v1.1-board-front:
-
-.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-annotated-photo.png
-    :align: center
-    :alt: ESP32-S3-DevKitC-1 - 正面
-
-    ESP32-S3-DevKitC-1 - 正面
-
-以下按照逆时针的顺序依次介绍开发板上的主要组件。
-
-.. list-table::
-   :widths: 30 70
-   :header-rows: 1
-
-   * - 主要组件
-     - 介绍
-   * - ESP32-S3-WROOM-1/1U/2
-     - ESP32-S3-WROOM-1、ESP32-S3-WROOM-1U 和 ESP32-S3-WROOM-2 是通用型 Wi-Fi + 低功耗蓝牙 MCU 模组，具有丰富的外设接口、强大的神经网络运算能力和信号处理能力，专为人工智能和 AIoT 市场打造。ESP32-S3-WROOM-1 和 ESP32-S3-WROOM-2 采用 PCB 板载天线，ESP32-S3-WROOM-1U 采用连接器连接外部天线。
-   * - 5 V to 3.3 V LDO（5 V 转 3.3 V LDO）
-     - 电源转换器，输入 5 V，输出 3.3 V。
-   * - Pin Headers（排针）
-     - 所有可用 GPIO 管脚（除 flash 的 SPI 总线）均已引出至开发板的排针。请查看 :ref:`user-guide-s3-devkitc-1-v1.1-header-blocks` 获取更多信息。
-   * - USB-to-UART Port（USB 转 UART 接口）
-     - Micro-USB 接口，可用作开发板的供电接口，可烧录固件至芯片，也可作为通信接口，通过板载 USB 转 UART 桥接器与芯片通信。
-   * - Boot Button（Boot 键）
-     - 下载按键。按住 **Boot** 键的同时按一下 **Reset** 键进入“固件下载”模式，通过串口下载固件。
-   * - Reset Button（Reset 键）
-     - 复位按键。
-   * - USB Port（USB 接口）
-     - ESP32-S3 USB OTG 接口，支持全速 USB 1.1 标准。ESP32-S3 USB 接口可用作开发板的供电接口，可烧录固件至芯片，可通过 USB 协议与芯片通信，也可用于 JTAG 调试。
-   * - USB-to-UART Bridge（USB 转 UART 桥接器）
-     - 单芯片 USB 至 UART 桥接器，可提供高达 3 Mbps 的传输速率。
-   * - RGB LED
-     - 可寻址 RGB 发光二极管，由 GPIO38 驱动。
-   * - 3.3 V Power On LED（3.3 V 电源指示灯）
-     - 开发板连接 USB 电源后，该指示灯亮起。
-
-.. note::
-
-  在板载 ESP32-S3-WROOM-1/1U 模组系列（使用 8 线 SPI flash/PSRAM）的开发板和板载 ESP32-S3-WROOM-2 模组系列的开发板中，管脚 GPIO35、GPIO36 和 GPIO37 已用于内部 ESP32-S3 芯片与 SPI flash/PSRAM 之间的通信，外部不可使用。
-
-
-开始开发应用
--------------
-
-通电前，请确保开发板完好无损。
-
-
-必备硬件
-^^^^^^^^
-
-- ESP32-S3-DevKitC-1
-- USB 2.0 数据线（标准 A 型转 Micro-B 型）
-- 电脑（Windows、Linux 或 macOS）
-
-.. 注解::
-
-  请确保使用适当的 USB 数据线。部分数据线仅可用于充电，无法用于数据传输和编程。
-
-
-硬件设置
-^^^^^^^^
-
-通过 **USB 转 UART 接口** 或 **ESP32-S3 USB 接口** 连接开发板与电脑。在后续步骤中，默认使用 **USB 转 UART 接口**。
-
-
-软件设置
-^^^^^^^^
-
-请前往 :doc:`../../get-started/index`，在 :ref:`get-started-step-by-step` 小节查看如何快速设置开发环境，将应用程序烧录至你的开发板。
-
-
-内含组件和包装
----------------
-
-订购信息
-^^^^^^^^^^^^^^
-
-该开发板有多种型号可供选择，详见下表。
-
-.. list-table::
-   :widths: 28 29 19 17 15
-   :header-rows: 1
-
-   * - 订购代码
-     - 搭载模组
-     - Flash
-     - PSRAM
-     - SPI 电压
-   * - ESP32-S3-DevKitC-1-N8
-     - ESP32-S3-WROOM-1-N8
-     - 8 MB QD
-     - —
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N8R2
-     - ESP32-S3-WROOM-1-N8R2
-     - 8 MB QD
-     - 2 MB QD
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N8R8
-     - ESP32-S3-WROOM-1-N8R8
-     - 8 MB QD
-     - 8 MB OT
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1-N16R8V
-     - ESP32-S3-WROOM-2-N16R8V
-     - 16 MB OT
-     - 8 MB OT
-     - 1.8 V
-   * - ESP32-S3-DevKitC-1-N32R8V
-     - ESP32-S3-WROOM-2-N32R8V
-     - 32 MB OT
-     - 8 MB OT
-     - 1.8 V
-   * - ESP32-S3-DevKitC-1U-N8
-     - ESP32-S3-WROOM-1U-N8
-     - 8 MB QD
-     - —
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1U-N8R2
-     - ESP32-S3-WROOM-1U-N8R2
-     - 8 MB QD
-     - 2 MB QD
-     - 3.3 V
-   * - ESP32-S3-DevKitC-1U-N8R8
-     - ESP32-S3-WROOM-1U-N8R8
-     - 8 MB QD
-     - 8 MB OT
-     - 3.3 V
-
-.. note::
-
-  上表中，QD 指代 Quad SPI，OT 指代 Octal SPI。
-
-
-零售订单
-^^^^^^^^
-
-如购买样品，每个开发板将以防静电袋或零售商选择的其他方式包装。
-
-零售订单请前往 https://www.espressif.com/zh-hans/company/contact/buy-a-sample。
-
-
-批量订单
-^^^^^^^^
-
-如批量购买，开发板将以大纸板箱包装。
-
-批量订单请前往 https://www.espressif.com/zh-hans/contact-us/sales-questions。
-
-
-硬件参考
-========
-
-功能框图
---------
-
-ESP32-S3-DevKitC-1 的主要组件和连接方式如下图所示。
-
-.. figure:: ../../../_static/ESP32-S3-DevKitC-1_v2-SystemBlock.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S3-DevKitC-1（点击放大）
-
-    ESP32-S3-DevKitC-1（点击放大）
-
-
-电源选项
-^^^^^^^^
-
-以下任一供电方式均可给开发板供电：
-
-- USB 转 UART 接口供电或 ESP32-S3 USB 接口供电（选择其一或同时供电），默认供电方式（推荐）
-- 5V 和 G (GND) 排针供电
-- 3V3 和 G (GND) 排针供电
-
-
-.. _user-guide-s3-devkitc-1-v1.1-header-blocks:
-
-排针
-----
-
-下表列出了开发板两侧排针（J1 和 J3）的 **名称** 和 **功能**，排针的名称如图 :ref:`user-guide-s3-devkitc-1-v1.1-board-front` 所示，排针的序号与 `开发板原理图 <https://dl.espressif.com/dl/schematics/SCH_ESP32-S3-DevKitC-1_V1.1_20220413.pdf>`_ (PDF) 一致。
-
-
-J1
-^^^
-
-====  ====  ==========  =====================================================================
-序号  名称   类型 [#]_    功能
-====  ====  ==========  =====================================================================
-1     3V3   P            3.3 V 电源
-2     3V3   P            3.3 V 电源
-3     RST   I            EN
-4     4     I/O/T        RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
-5     5     I/O/T        RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
-6     6     I/O/T        RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
-7     7     I/O/T        RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
-8     15    I/O/T        RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
-9     16    I/O/T        RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
-10    17    I/O/T        RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
-11    18    I/O/T        RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3
-12    8     I/O/T        RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
-13    3     I/O/T        RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
-14    46    I/O/T        GPIO46
-15    9     I/O/T        RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD
-16    10    I/O/T        RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS0
-17    11    I/O/T        RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID
-18    12    I/O/T        RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK
-19    13    I/O/T        RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ
-20    14    I/O/T        RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP
-21    5V    P            5 V 电源
-22    G     G            接地
-====  ====  ==========  =====================================================================
-
-
-J3
-^^^
-
-====  ====  ==========  =====================================================================
-序号  名称   类型          功能
-====  ====  ==========  =====================================================================
-1      G     G            接地
-2      TX    I/O/T        U0TXD, GPIO43, CLK_OUT1
-3      RX    I/O/T        U0RXD, GPIO44, CLK_OUT2
-4      1     I/O/T        RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
-5      2     I/O/T        RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
-6      42    I/O/T        MTMS, GPIO42
-7      41    I/O/T        MTDI, GPIO41, CLK_OUT1
-8      40    I/O/T        MTDO, GPIO40, CLK_OUT2
-9      39    I/O/T        MTCK, GPIO39, CLK_OUT3, SUBSPICS1
-10     38    I/O/T        GPIO38, FSPIWP, SUBSPIWP, RGB LED
-11     37    I/O/T        SPIDQS, GPIO37, FSPIQ, SUBSPIQ
-12     36    I/O/T        SPIIO7, GPIO36, FSPICLK, SUBSPICLK
-13     35    I/O/T        SPIIO6, GPIO35, FSPID, SUBSPID
-14     0     I/O/T        RTC_GPIO0, GPIO0
-15     45    I/O/T        GPIO45
-16     48    I/O/T        GPIO48, SPICLK_N, SUBSPICLK_N_DIFF
-17     47    I/O/T        GPIO47, SPICLK_P, SUBSPICLK_P_DIFF
-18     21    I/O/T        RTC_GPIO21, GPIO21
-19     20    I/O/T        RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
-20     19    I/O/T        RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
-21     G     G            接地
-22     G     G            接地
-====  ====  ==========  =====================================================================
-
-
-.. [#] P：电源；I：输入；O：输出；T：可设置为高阻。
-
-
-有关管脚功能名称的解释，请参考 `ESP32-S3 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_cn.pdf>`_ (PDF)。
-
-
-管脚布局
-^^^^^^^^^^^
-
-.. figure:: ../../../_static/ESP32-S3_DevKitC-1_pinlayout_v1.1.jpg
-    :align: center
-    :scale: 50%
-    :alt: ESP32-S3-DevKitC-1（点击放大）
-
-    ESP32-S3-DevKitC-1 管脚布局（点击放大）
-
-
-硬件版本
-============
-
-:doc:`首次发布 <user-guide-devkitc-1-v1.0>`
-
-.. note::
-
-    目前首次发布和 v1.1 版本的开发板均可订购，两个版本的主要差异在于 RGB LED 所连接的管脚不同。首次发布版本的 RGB LED 连接到 GPIO48，而 v1.1 版本的 RGB LED 连接到 GPIO38。
-
-
-相关文档
-========
-
-- `ESP32-S3 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_cn.pdf>`_ (PDF)
-- `ESP32-S3-WROOM-1 & ESP32-S3-WROOM-1U 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_cn.pdf>`_ (PDF)
-- `ESP32-S3-WROOM-2 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-2_datasheet_cn.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 原理图 <https://dl.espressif.com/dl/schematics/SCH_ESP32-S3-DevKitC-1_V1.1_20221130.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 PCB 布局图 <https://dl.espressif.com/dl/schematics/PCB_ESP32-S3-DevKitC-1_V1.1_20220429.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 尺寸图 <https://dl.espressif.com/dl/schematics/esp_idf/DXF_ESP32-S3-DevKitC-1_V1.1_20220429.pdf>`_ (PDF)
-- `ESP32-S3-DevKitC-1 尺寸图源文件 <https://dl.espressif.com/dl/schematics/esp_idf/DXF_ESP32-S3-DevKitC-1_V1.1_20220429.dxf>`_ (DXF) - 可使用 `Autodesk Viewer <https://viewer.autodesk.com/>`_ 查看
-
-有关本开发板的更多设计文档，请联系我们的商务部门 `sales@espressif.com <sales@espressif.com>`_。
-
-.. toctree::
-    :hidden:
-
-    user-guide-devkitc-1-v1.0
diff --git a/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitm-1.rst b/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitm-1.rst
deleted file mode 100644
index c39d0a54068..00000000000
--- a/docs/zh_CN/hw-reference/esp32s3/user-guide-devkitm-1.rst
+++ /dev/null
@@ -1,258 +0,0 @@
-===================
-ESP32-S3-DevKitM-1
-===================
-
-:link_to_translation:`en: [English]`
-
-本指南将帮助你快速上手 ESP32-S3-DevKitM-1，并提供该款开发板的详细信息。
-
-ESP32-S3-DevKitM-1 是一款入门级开发板，搭载的是 Wi-Fi+蓝牙 LE 模组 ESP32-S3-MINI-1 或 ESP32-S3-MINI-1U，该款模组因小尺寸而得名。
-
-板上模组的大部分管脚均已引出至开发板两侧排针，开发人员可根据实际需求，轻松通过跳线连接多种外围设备，也可将开发板插在面包板上使用。
-
-.. figure:: ../../../_static/esp32-s3-devkitm-1-v1-isometric.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S3-DevKitM-1（板载 ESP32-S3-MINI-1 模组）
-    :figclass: align-center
-
-    ESP32-S3-DevKitM-1（板载 ESP32-S3-MINI-1 模组）
-
-
-本指南包括如下内容：
-
-- `入门指南`_：简要介绍了开发板和硬件、软件设置指南。
-- `硬件参考`_：详细介绍了开发板的硬件。
-- `相关文档`_：列出了相关文档的链接。
-
-
-入门指南
-========
-
-本小节将简要介绍 ESP32-S3-DevKitM-1，说明如何在 ESP32-S3-DevKitM-1 上烧录固件及相关准备工作。
-
-
-组件介绍
---------
-
-.. _user-guide-s3-devkitm-1-v1-board-front:
-
-.. figure:: ../../../_static/ESP32-S3-DevKitM-1_v1-annotated-photo.png
-    :align: center
-    :alt: ESP32-S3-DevKitM-1 - 正面
-    :figclass: align-center
-
-    ESP32-S3-DevKitM-1 - 正面
-
-以下按照逆时针的顺序依次介绍开发板上的主要组件。
-
-.. list-table::
-   :widths: 30 70
-   :header-rows: 1
-
-   * - 主要组件
-     - 介绍
-   * - ESP32-S3-MINI-1/1U
-     - ESP32-S3-MINI-1 和 ESP32-S3-MINI-1U 是通用型 Wi-Fi + 低功耗蓝牙 MCU 模组，具有丰富的外设接口。ESP32-S3-MINI-1 采用 PCB 板载天线，ESP32-S3-MINI-1U 采用连接器连接外部天线。两款模组的核心是 ESP32-S3FN8 芯片。该芯片带有 8 MB flash，由于 flash 直接封装在芯片中，因此 ESP32-S3-MINI-1/1U 模组具有较小的封装尺寸。
-   * - 5 V to 3.3 V LDO（5 V 转 3.3 V LDO）
-     - 电源转换器，输入 5 V，输出 3.3 V。
-   * - Pin Headers（排针）
-     - 所有可用 GPIO 管脚（除 flash 的 SPI 总线）均已引出至开发板的排针。请查看 :ref:`user-guide-s3-DevKitM-1-header-blocks` 获取更多信息。
-   * - USB-to-UART Port（USB 转 UART 接口）
-     - Micro-USB 接口，可用作开发板的供电接口，可烧录固件至芯片，也可作为通信接口，通过板载 USB 转 UART 桥接器与芯片通信。
-   * - Boot Button（Boot 键）
-     - 下载按键。按住 **Boot** 键的同时按一下 **Reset** 键进入“固件下载”模式，通过串口下载固件。
-   * - Reset Button（Reset 键）
-     - 复位按键。
-   * - ESP32-S3 USB Port（ESP32-S3 USB 接口）
-     - ESP32-S3 USB OTG 接口，支持全速 USB 1.1 标准。ESP32-S3 USB 接口可用作开发板的供电接口，可烧录固件至芯片，可通过 USB 协议与芯片通信，也可用于 JTAG 调试。
-   * - USB-to-UART Bridge（USB 转 UART 桥接器）
-     - 单芯片 USB 至 UART 桥接器，可提供高达 3 Mbps 的传输速率。
-   * - RGB LED
-     - 可寻址 RGB 发光二极管，由 GPIO48 驱动。
-   * - 3.3 V Power On LED（3.3 V 电源指示灯）
-     - 开发板连接 USB 电源后，该指示灯亮起。
-
-
-开始开发应用
--------------
-
-通电前，请确保开发板完好无损。
-
-
-必备硬件
-^^^^^^^^
-
-- ESP32-S3-DevKitM-1
-- USB 2.0 数据线（标准 A 型转 Micro-B 型）
-- 电脑（Windows、Linux 或 macOS）
-
-.. 注解::
-
-  请确保使用适当的 USB 数据线。部分数据线仅可用于充电，无法用于数据传输和编程。
-
-
-硬件设置
-^^^^^^^^
-
-通过 **USB 转 UART 接口** 或 **ESP32-S3 USB 接口** 连接开发板与电脑。在后续步骤中，默认使用 **USB 转 UART 接口**。
-
-
-软件设置
-^^^^^^^^
-
-请前往 :doc:`../../get-started/index`，在 :ref:`get-started-step-by-step` 小节查看如何快速设置开发环境，将应用程序烧录至你的开发板。
-
-
-内含组件和包装
----------------
-
-零售订单
-^^^^^^^^
-
-如购买样品，每个开发板将以防静电袋或零售商选择的其他方式包装。
-
-零售订单请前往 https://www.espressif.com/zh-hans/company/contact/buy-a-sample。
-
-
-批量订单
-^^^^^^^^
-
-如批量购买，开发板将以大纸板箱包装。
-
-批量订单请前往 https://www.espressif.com/zh-hans/contact-us/sales-questions。
-
-
-硬件参考
-========
-
-功能框图
---------
-
-ESP32-S3-DevKitM-1 的主要组件和连接方式如下图所示。
-
-.. figure:: ../../../_static/ESP32-S3-DevKitM-1_v1_SystemBlock.png
-    :align: center
-    :scale: 70%
-    :alt: ESP32-S3-DevKitM-1（点击放大）
-    :figclass: align-center
-
-    ESP32-S3-DevKitM-1（点击放大）
-
-
-电源选项
-^^^^^^^^
-
-以下任一供电方式均可给开发板供电：
-
-- USB 转 UART 接口供电或 ESP32-S3 USB 接口供电（选择其一或同时供电），默认供电方式（推荐）
-- 5V 和 G (GND) 排针供电
-- 3V3 和 G (GND) 排针供电
-
-
-.. _user-guide-s3-DevKitM-1-header-blocks:
-
-排针
-----
-
-下表列出了开发板两侧排针（J1 和 J3）的 **名称** 和 **功能**，排针的名称如图 :ref:`user-guide-s3-devkitm-1-v1-board-front` 所示，排针的序号与 `开发板原理图 <https://dl.espressif.com/dl/schematics/SCH_ESP32-S3-DEVKITM-1_V1_20210310A.pdf>`_ (PDF) 一致。
-
-
-J1
-^^^
-
-====  ====  ==========  =====================================================================
-序号  名称   类型 [#]_    功能
-====  ====  ==========  =====================================================================
-1     3V3   P           3.3 V 电源
-2     0     I/O/T       RTC_GPIO0, GPIO0
-3     1     I/O/T       RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0
-4     2     I/O/T       RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1
-5     3     I/O/T       RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2
-6     4     I/O/T       RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3
-7     5     I/O/T       RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4
-8     6     I/O/T       RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5
-9     7     I/O/T       RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6
-10    8     I/O/T       RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7, SUBSPICS1
-11    9     I/O/T       RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD, SUBSPIHD
-12    10    I/O/T       RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4, SUBSPICS0
-13    11    I/O/T       RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5, SUBSPID
-14    12    I/O/T       RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6, SUBSPICLK
-15    13    I/O/T       RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7, SUBSPIQ
-16    14    I/O/T       RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS, SUBSPIWP
-17    15    I/O/T       RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P
-18    16    I/O/T       RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N
-19    17    I/O/T       RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6
-20    18    I/O/T       RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, CLK_OUT3
-21    5V    P           5 V 电源
-22    G     G           接地
-====  ====  ==========  =====================================================================
-
-
-J3
-^^^
-
-====  ====  ==========  =====================================================================
-序号  名称   类型          功能
-====  ====  ==========  =====================================================================
-1     G     G           接地
-2     RST   I           EN
-3     46    I/O/T       GPIO46
-4     45    I/O/T       GPIO45
-5     RX    I/O/T       U0RXD, GPIO44, CLK_OUT2
-6     TX    I/O/T       U0TXD, GPIO43, CLK_OUT1
-7     42    I/O/T       MTMS, GPIO42
-8     41    I/O/T       MTDI, GPIO41, CLK_OUT1
-9     40    I/O/T       MTDO, GPIO40, CLK_OUT2
-10    39    I/O/T       MTCK, GPIO39, CLK_OUT3, SUBSPICS1
-11    38    I/O/T       GPIO38, FSPIWP, SUBSPIWP
-12    37    I/O/T       SPIDQS, GPIO37, FSPIQ, SUBSPIQ
-13    36    I/O/T       SPIIO7, GPIO36, FSPICLK, SUBSPICLK
-14    35    I/O/T       SPIIO6, GPIO35, FSPID, SUBSPID
-15    34    I/O/T       SPIIO5, GPIO34, FSPICS0, SUBSPICS0
-16    33    I/O/T       SPIIO4, GPIO33, FSPIHD, SUBSPIHD
-17    26    I/O/T       SPICS1, GPIO26
-18    21    I/O/T       RTC_GPIO21, GPIO21
-19    20    I/O/T       RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+
-20    19    I/O/T       RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D-
-21    48    I/O/T       SPICLK_N, GPIO48, SUBSPICLK_N_DIFF, RGB LED
-22    47    I/O/T       SPICLK_P, GPIO47, SUBSPICLK_P_DIFF
-====  ====  ==========  =====================================================================
-
-
-.. [#] P：电源；I：输入；O：输出；T：可设置为高阻。
-
-
-
-有关管脚功能名称的解释，请参考 `ESP32-S3 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_cn.pdf>`_ (PDF)。
-
-
-管脚布局
-^^^^^^^^^^^
-
-.. figure:: ../../../_static/ESP32-S3_DevKitM-1_pinlayout.jpg
-    :align: center
-    :scale: 50%
-    :alt: ESP32-S3-DevKitM-1（点击放大）
-    :figclass: align-center
-
-    ESP32-S3-DevKitM-1 管脚布局（点击放大）
-
-
-硬件版本
-============
-
-无历史版本。
-
-
-相关文档
-========
-
-- `ESP32-S3 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_cn.pdf>`_ (PDF)
-- `ESP32-S3-MINI-1 & ESP32-S3-MINI-1U 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_cn.pdf>`_ (PDF)
-- `ESP32-S3-DevKitM-1 原理图 <https://dl.espressif.com/dl/schematics/SCH_ESP32-S3-DEVKITM-1_V1_20210310A.pdf>`_ (PDF)
-- `ESP32-S3-DevKitM-1 PCB 布局图 <https://dl.espressif.com/dl/schematics/PCB_ESP32-S3-DevKitM-1_V1_20210310AC.pdf>`_ (PDF)
-- `ESP32-S3-DevKitM-1 尺寸图 <https://dl.espressif.com/dl/schematics/DXF_ESP32-S3-DevKitM-1_V1_20210310AC.pdf>`_ (PDF)
-- `ESP32-S3-DevKitM-1 尺寸图源文件 <https://dl.espressif.com/dl/schematics/DXF_ESP32-S3-DevKitM-1_V1_20210310AC.dxf>`_ (DXF) - 可使用 `Autodesk Viewer <https://viewer.autodesk.com/>`_ 查看
-
-有关本开发板的更多设计文档，请联系我们的商务部门 `sales@espressif.com <sales@espressif.com>`_。
diff --git a/docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst b/docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst
index b2a818aa1c8..9dc2d0492c4 100644
--- a/docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst
+++ b/docs/zh_CN/libraries-and-frameworks/libs-frameworks.rst
@@ -1,11 +1,11 @@
 其他库和开发框架
-=============================
+================
 :link_to_translation:`en:[English]`
 
 本文展示了一系列乐鑫官方发布的库和框架。
 
 ESP-ADF
--------------------------------------
+-------
 
 ESP-ADF 是一个全方位的音频应用程序框架，该框架支持：
 
@@ -20,14 +20,14 @@ ESP-ADF 是一个全方位的音频应用程序框架，该框架支持：
 该框架对应的 GitHub 仓库为 `ESP-ADF <https://github.com/espressif/esp-adf>`_。
 
 ESP-CSI
-------------------------------------
+-------
 
 ESP-CSI 是一个具有实验性的框架，它利用 Wi-Fi 信道状态信息来检测人体存在。
 
 该框架对应的 GitHub 仓库为 `ESP-CSI <https://github.com/espressif/esp-csi>`_。
 
 ESP-DSP
-------------------------------------
+-------
 
 ESP-DSP 提供了针对数字信号处理应用优化的算法，该库支持：
 
@@ -41,7 +41,7 @@ ESP-DSP 提供了针对数字信号处理应用优化的算法，该库支持：
 该库对应的 GitHub 仓库为 `ESP-DSP 库 <https://github.com/espressif/esp-dsp>`_。
 
 ESP-WIFI-MESH
-------------------------------------------------------
+-------------
 
 ESP-WIFI-MESH 基于 ESP-WIFI-MESH 协议搭建，该框架支持：
 
@@ -54,21 +54,21 @@ ESP-WIFI-MESH 基于 ESP-WIFI-MESH 协议搭建，该框架支持：
 该框架对应的 GitHub 仓库为 `ESP-MDF <https://github.com/espressif/esp-mdf>`_。
 
 ESP-WHO
-------------------------------
+-------
 
 ESP-WHO 框架利用 ESP32 及摄像头实现人脸检测及识别。
 
 该框架对应的 GitHub 仓库为 `ESP-WHO <https://github.com/espressif/esp-who>`_。
 
 ESP RainMaker
----------------------------------------------
+-------------
 
 `ESP RainMaker <https://rainmaker.espressif.com/>`_ 提供了一个快速 AIoT 开发的完整解决方案。使用 ESP RainMaker，用户可以创建多种 AIoT 设备，包括固件 AIoT 以及集成了语音助手、手机应用程序和云后端的 AIoT 等。
 
 该解决方案对应的 GitHub 仓库为 `GitHub 上的 ESP RainMaker <https://github.com/espressif/esp-rainmaker>`_。
 
 ESP-IoT-Solution
---------------------------------------------------
+----------------
 
 `ESP-IoT-Solution <https://docs.espressif.com/projects/espressif-esp-iot-solution/en/latest/>`_ 涵盖了开发 IoT 系统时常用的设备驱动程序及代码框架。在 ESP-IoT-Solution 中，设备驱动程序和代码框架以独立组件存在，可以轻松地集成到 ESP-IDF 项目中。
 
@@ -82,7 +82,7 @@ ESP-IoT-Solution 支持：
 
 
 ESP-Protocols
------------------------------------------
+-------------
 
 `ESP-Protocols <https://github.com/espressif/esp-protocols>`_ 库包含 ESP-IDF 的协议组件集。ESP-Protocols 中的代码以独立组件存在，可以轻松地集成到 ESP-IDF 项目中。此外，每个组件都可以在 `乐鑫组件注册表 <https://components.espressif.com/>`__ 中找到。
 
@@ -96,12 +96,14 @@ ESP-Protocols 组件：
 
 * `asio <https://components.espressif.com/component/espressif/asio>`_ 是一个跨平台的 C++ 库，请参阅 `<https://think-async.com/Asio/>`_。该库基于现代 C++ 提供一致的异步模型，请参阅 `asio 文档 <https://docs.espressif.com/projects/esp-protocols/asio/docs/latest/index.html>`_。
 
+* `esp_wifi_remote <https://components.espressif.com/component/espressif/esp_wifi_remote>`_ 是一个 Wi-Fi 通信库，提供标准的 Wi-Fi API，并且能够借助指定的传输接口，帮助目标设备通过外部 ESP32 芯片实现 Wi-Fi 通信。详情请参阅 :doc:`../api-guides/wifi-expansion`。
+
 ESP-BSP
-----------------------------------------
+-------
 
 `ESP-BSP <https://github.com/espressif/esp-bsp>`_ 库包含了各种乐鑫和第三方开发板的板级支持包 (BSP)，可以帮助快速上手特定的开发板。它们通常包含管脚定义和辅助函数，这些函数可用于初始化特定开发板的外设。此外，BSP 还提供了一些驱动程序，可用于开发版上的外部芯片，如传感器、显示屏、音频编解码器等。
 
 ESP-IDF-CXX
-----------------------------------------------------------
+-----------
 
 `ESP-IDF-CXX <https://github.com/espressif/esp-idf-cxx>`_ 包含了 ESP-IDF 的部分 C++ 封装，重点在实现易用性、安全性、自动资源管理，以及将错误检查转移到编译过程中，以避免运行时失败。它还提供了 ESP 定时器、I2C、SPI、GPIO 等外设或 ESP-IDF 其他功能的 C++ 类。ESP-IDF-CXX 作为组件可以从 `乐鑫组件注册表 <https://components.espressif.com/components/espressif/esp-idf-cxx>`__ 中获取。详情请参阅 `README.md <https://github.com/espressif/esp-idf-cxx/blob/main/README.md>`_。
diff --git a/docs/zh_CN/migration-guides/release-5.x/5.4/index.rst b/docs/zh_CN/migration-guides/release-5.x/5.4/index.rst
index 156a9900b68..e2256533e95 100644
--- a/docs/zh_CN/migration-guides/release-5.x/5.4/index.rst
+++ b/docs/zh_CN/migration-guides/release-5.x/5.4/index.rst
@@ -9,3 +9,5 @@
     gcc
     system
     bluetooth-classic
+    storage
+    wifi
diff --git a/docs/zh_CN/migration-guides/release-5.x/5.4/storage.rst b/docs/zh_CN/migration-guides/release-5.x/5.4/storage.rst
new file mode 100644
index 00000000000..edb535412ac
--- /dev/null
+++ b/docs/zh_CN/migration-guides/release-5.x/5.4/storage.rst
@@ -0,0 +1,7 @@
+存储
+=======
+
+SPI flash 驱动
+^^^^^^^^^^^^^^^^^^^^^^
+
+XMC-C 系列闪存 suspend 功能的支持已被移除。根据闪存制造商的反馈，在某些情况下，XMC-C 闪存需要在 resume 和下一条命令之间间隔 1 毫秒。这对于软件请求来说时间太长。基于上述原因，为了安全使用 suspend 功能，我们决定取消 XMC-C 系列的闪存挂起支持。但是你依旧可以强行通过 `CONFIG_SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND` 的配置使能这个功能。如果您有任何疑问，请联系 espressif 业务支持。
diff --git a/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst b/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst
index dbe6984ddd7..b86411e98f7 100644
--- a/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst
+++ b/docs/zh_CN/migration-guides/release-5.x/5.4/system.rst
@@ -3,11 +3,17 @@
 
 :link_to_translation:`en:[English]`
 
+ESP-Common
+----------
+
+``__VA_NARG__`` 及其相关宏已被重新命名以避免命名冲突，请使用带有 ESP 前缀的新名称，例如 ``ESP_VA_NARG``。
+
 日志
 ------
 
 - `esp_log_buffer_hex` 已弃用，应使用 `ESP_LOG_BUFFER_HEX` 替代。
 - `esp_log_buffer_char` 已弃用，应使用 `ESP_LOG_BUFFER_CHAR` 替代。
+- ``CONFIG_LOG_COLORS`` 的默认值设置为 false。默认情况下，IDF Monitor 在主机端添加颜色。如需在其他控制台监视器的日志输出中启用颜色，请将 ``CONFIG_LOG_COLORS`` 设置为 true。如需在 IDF Monitor 中关闭自动的日志颜色显示，请运行命令： ``idf.py monitor --disable-auto-color``。
 
 ESP ROM
 ---------
diff --git a/docs/zh_CN/migration-guides/release-5.x/5.4/wifi.rst b/docs/zh_CN/migration-guides/release-5.x/5.4/wifi.rst
new file mode 100644
index 00000000000..ed9be5db8df
--- /dev/null
+++ b/docs/zh_CN/migration-guides/release-5.x/5.4/wifi.rst
@@ -0,0 +1,24 @@
+Wi-Fi
+=====
+
+:link_to_translation:`en:[English]`
+
+
+Wi-Fi 扫描和连接
+------------------------
+
+    以下类型已被更改：
+    - :component_file:`esp_wifi/include/esp_wifi_he_types.h`
+
+        - :cpp:struct:`esp_wifi_htc_omc_t` 中:
+
+            - ``uph_id``， ``ul_pw_headroom``， ``min_tx_pw_flag`` 字段被弃用
+
+    - :component_file:`esp_wifi/include/esp_wifi_types_generic.h`
+
+        - :cpp:struct:`wifi_ap_record_t` 中:
+
+            - ``bandwidth`` 的类型从 ``uint8_t`` 更改为 ``wifi_bandwidth_t``
+
+
+
diff --git a/docs/zh_CN/security/flash-encryption.rst b/docs/zh_CN/security/flash-encryption.rst
index da68d9e4b51..34433b3bdf4 100644
--- a/docs/zh_CN/security/flash-encryption.rst
+++ b/docs/zh_CN/security/flash-encryption.rst
@@ -39,7 +39,7 @@ flash 加密功能用于加密与 {IDF_TARGET_NAME} 搭载使用的片外 flash
 
 启用 flash 加密后，会默认加密以下类型的数据：
 
-- :ref:`second-stage-bootloader` （固件引导加载程序）
+- :ref:`second-stage-bootloader`
 - 分区表
 - :ref:`nvs_encr_key_partition`
 - Otadata
@@ -48,7 +48,7 @@ flash 加密功能用于加密与 {IDF_TARGET_NAME} 搭载使用的片外 flash
 其他类型的数据将视情况进行加密：
 
 - 分区表中标有 ``encrypted`` 标志的分区。如需了解详情，请参考 :ref:`encrypted-partition-flag`。
-- 如果启用了安全启动，则会对安全启动引导程序摘要进行加密（见下文）。
+- 如果启用了安全启动，则会对安全启动引导加载程序摘要进行加密（见下文）。
 
 .. _flash-encryption-efuse:
 
@@ -175,39 +175,39 @@ flash 加密操作由 {IDF_TARGET_NAME} 上的多个 eFuse 控制，具体 eFuse
 flash 的加密过程
 ------------------
 
-假设 eFuse 值处于默认状态，且固件的引导加载程序编译为支持 flash 加密，则 flash 加密的具体过程如下：
+假设 eFuse 值处于默认状态，且二级引导加载程序编译为支持 flash 加密，则 flash 加密的具体过程如下：
 
 .. only:: not SOC_FLASH_ENCRYPTION_XTS_AES
 
-  1. 第一次开机复位时，flash 中的所有数据都是未加密的（明文）。ROM 引导加载程序加载固件引导加载程序。
+  1. 第一次开机复位时，flash 中的所有数据都是未加密的（明文）。一级 (ROM) 引导加载程序加载二级引导加载程序。
 
-  2. 固件的引导加载程序将读取 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 值 (``0b0000000``)。因为该值为 0（偶数位），固件的引导加载程序将配置并启用 flash 加密块，同时将 ``FLASH_CRYPT_CONFIG`` eFuse 的值编程为 0xF。关于 flash 加密块的更多信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *eFuse 控制器 (eFuse)* > *flash 加密块* [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]。
+  2. 二级引导加载程序将读取 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 值 (``0b0000000``)。因为该值为 0（偶数位），二级引导加载程序将配置并启用 flash 加密块，同时将 ``FLASH_CRYPT_CONFIG`` eFuse 的值编程为 0xF。关于 flash 加密块的更多信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *eFuse 控制器 (eFuse)* > *flash 加密块* [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]。
 
-  3. 固件引导加载程序首先检查 eFuse 中是否已经存在有效密钥（例如用 espefuse 工具烧写的密钥），如果存在，则会跳过密钥生成，并将该密钥用于 flash 加密过程。否则，固件引导加载程序会使用 RNG（随机数发生器）模块生成一个 AES-256 位密钥，并将其写入 ``flash_encryption`` eFuse 中。由于已设置了 ``flash_encryption`` eFuse 的读保护位和写保护位，因此无法通过软件访问密钥。flash 加密操作完全在硬件中完成，无法通过软件访问密钥。
+  3. 二级引导加载程序首先检查 eFuse 中是否已经存在有效密钥（例如用 espefuse 工具烧写的密钥），如果存在，则会跳过密钥生成，并将该密钥用于 flash 加密过程。否则，二级引导加载程序会使用 RNG（随机数发生器）模块生成一个 AES-256 位密钥，并将其写入 ``flash_encryption`` eFuse 中。由于已设置了 ``flash_encryption`` eFuse 的读保护位和写保护位，因此无法通过软件访问密钥。flash 加密操作完全在硬件中完成，无法通过软件访问密钥。
 
-  4. flash 加密块将加密 flash 的内容（固件的引导加载程序、应用程序、以及标有 ``加密`` 标志的分区）。就地加密可能会耗些时间（对于大分区最多需要一分钟）。
+  4. flash 加密块将加密 flash 的内容（二级引导加载程序、应用程序、以及标有 ``加密`` 标志的分区）。就地加密可能会耗些时间（对于大分区最多需要一分钟）。
 
-  5. 固件引导加载程序将在 ``{IDF_TARGET_CRYPT_CNT}`` (0b0000001) 中设置第一个可用位来对已加密的 flash 内容进行标记。设置奇数个比特位。
+  5. 二级引导加载程序将在 ``{IDF_TARGET_CRYPT_CNT}`` (0b0000001) 中设置第一个可用位来对已加密的 flash 内容进行标记。设置奇数个比特位。
 
-  6. 对于 :ref:`flash-enc-development-mode`，固件引导加载程序仅设置 ``DISABLE_DL_DECRYPT`` 和 ``DISABLE_DL_CACHE`` 的 eFuse 位，以便 UART 引导加载程序重新烧录加密的二进制文件。此外， ``{IDF_TARGET_CRYPT_CNT}`` 的 eFuse 位不受写入保护。
+  6. 对于 :ref:`flash-enc-development-mode`，二级引导加载程序仅设置 ``DISABLE_DL_DECRYPT`` 和 ``DISABLE_DL_CACHE`` 的 eFuse 位，以便 UART 引导加载程序重新烧录加密的二进制文件。此外， ``{IDF_TARGET_CRYPT_CNT}`` 的 eFuse 位不受写入保护。
 
-  7. 对于 :ref:`flash-enc-release-mode`，固件引导加载程序设置 ``DISABLE_DL_ENCRYPT``、``DISABLE_DL_DECRYPT`` 和 ``DISABLE_DL_CACHE`` 的 eFuse 位为 1，以防止 UART 引导加载程序解密 flash 内容。它还写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 位。要修改此行为，请参阅 :ref:`uart-bootloader-encryption`。
+  7. 对于 :ref:`flash-enc-release-mode`，二级引导加载程序设置 ``DISABLE_DL_ENCRYPT``、``DISABLE_DL_DECRYPT`` 和 ``DISABLE_DL_CACHE`` 的 eFuse 位为 1，以防止 UART 引导加载程序解密 flash 内容。它还写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 位。要修改此行为，请参阅 :ref:`uart-bootloader-encryption`。
 
-  8. 重新启动设备以开始执行加密镜像。固件引导加载程序调用 flash 解密块来解密 flash 内容，然后将解密的内容加载到 IRAM 中。
+  8. 重新启动设备以开始执行加密镜像。二级引导加载程序调用 flash 解密块来解密 flash 内容，然后将解密的内容加载到 IRAM 中。
 
 .. only:: SOC_FLASH_ENCRYPTION_XTS_AES_256
 
-  1. 第一次开机复位时，flash 中的所有数据都是未加密的（明文）。ROM 引导加载程序加载固件引导加载程序。
+  1. 第一次开机复位时，flash 中的所有数据都是未加密的（明文）。一级 (ROM) 引导加载程序加载二级引导加载程序。
 
-  2. 固件的引导加载程序将读取 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 值 (``0b000``)。因为该值为 0（偶数位），固件引导加载程序将配置并启用 flash 加密块。关于 flash 加密块的更多信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *eFuse 控制器 (eFuse)* > *自动加密块* [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]。
+  2. 二级引导加载程序将读取 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 值 (``0b000``)。因为该值为 0（偶数位），二级引导加载程序将配置并启用 flash 加密块。关于 flash 加密块的更多信息，请参考 *{IDF_TARGET_NAME} 技术参考手册* > *eFuse 控制器 (eFuse)* > *自动加密块* [`PDF <{IDF_TARGET_TRM_CN_URL}#efuse>`__]。
 
-  3. 固件引导加载程序首先检查 eFuse 中是否已经存在有效密钥（例如用 espefuse 工具烧写的密钥），如果存在，则会跳过密钥生成，并将该密钥用于 flash 加密过程。否则，固件引导加载程序使用 RNG（随机数发生器）模块生成一个 256 位或 512 位的密钥，具体位数取决于 :ref:`生成的 XTS-AES 密钥的大小 <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`，然后将其分别写入一个或两个 `BLOCK_KEYN` eFuse 中。软件也为存储密钥的块更新了 ``KEY_PURPOSE_N``。由于上述一个或两个 ``BLOCK_KEYN`` eFuse 已设置了读保护和写保护位，因此无法通过软件访问密钥。``KEY_PURPOSE_N`` 字段也受写保护。flash 加密操作完全在硬件中完成，无法通过软件访问密钥。
+  3. 二级引导加载程序首先检查 eFuse 中是否已经存在有效密钥（例如用 espefuse 工具烧写的密钥），如果存在，则会跳过密钥生成，并将该密钥用于 flash 加密过程。否则，二级引导加载程序使用 RNG（随机数发生器）模块生成一个 256 位或 512 位的密钥，具体位数取决于 :ref:`生成的 XTS-AES 密钥的大小 <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`，然后将其分别写入一个或两个 `BLOCK_KEYN` eFuse 中。软件也为存储密钥的块更新了 ``KEY_PURPOSE_N``。由于上述一个或两个 ``BLOCK_KEYN`` eFuse 已设置了读保护和写保护位，因此无法通过软件访问密钥。``KEY_PURPOSE_N`` 字段也受写保护。flash 加密操作完全在硬件中完成，无法通过软件访问密钥。
 
-  4. flash 加密块将加密 flash 的内容（固件的引导加载程序、应用程序、以及标有“加密”标志的分区）。就地加密可能会耗些时间（对于大分区最多需要一分钟）。
+  4. flash 加密块将加密 flash 的内容（二级引导加载程序、应用程序、以及标有“加密”标志的分区）。就地加密可能会耗些时间（对于大分区最多需要一分钟）。
 
-  5. 固件引导加载程序将在 ``{IDF_TARGET_CRYPT_CNT}`` (0b001) 中设置第一个可用位来对已加密的 flash 内容进行标记。设置奇数位。
+  5. 二级引导加载程序将在 ``{IDF_TARGET_CRYPT_CNT}`` (0b001) 中设置第一个可用位来对已加密的 flash 内容进行标记。设置奇数位。
 
-  6. 对于 :ref:`flash-enc-development-mode`，固件引导加载程序允许 UART 引导加载程序重新烧录加密后的二进制文件。同时，``{IDF_TARGET_CRYPT_CNT}`` eFuse 位不受写入保护。此外，固件引导加载程序默认置位以下 eFuse 位：
+  6. 对于 :ref:`flash-enc-development-mode`，二级引导加载程序允许 UART 引导加载程序重新烧录加密后的二进制文件。同时，``{IDF_TARGET_CRYPT_CNT}`` eFuse 位不受写入保护。此外，二级引导加载程序默认置位以下 eFuse 位：
 
     .. list::
 
@@ -217,45 +217,45 @@ flash 的加密过程
       - ``HARD_DIS_JTAG``
       - ``DIS_LEGACY_SPI_BOOT``
 
-  7. 对于 :ref:`flash-enc-release-mode`，固件引导加载程序设置所有在开发模式下设置的 eFuse 位。它还写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 位。要修改此行为，请参阅 :ref:`uart-bootloader-encryption`。
+  7. 对于 :ref:`flash-enc-release-mode`，二级引导加载程序设置所有在开发模式下设置的 eFuse 位。它还写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 位。要修改此行为，请参阅 :ref:`uart-bootloader-encryption`。
 
-  8. 重新启动设备以开始执行加密镜像。固件引导加载程序调用 flash 解密块来解密 flash 内容，然后将解密的内容加载到 IRAM 中。
+  8. 重新启动设备以开始执行加密镜像。二级引导加载程序调用 flash 解密块来解密 flash 内容，然后将解密的内容加载到 IRAM 中。
 
 .. only:: SOC_FLASH_ENCRYPTION_XTS_AES_128 and not SOC_FLASH_ENCRYPTION_XTS_AES_256 and not SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
 
-  1. 第一次开机复位时，flash 中的所有数据都是未加密的（明文）。ROM 引导加载程序加载固件引导加载程序。
+  1. 第一次开机复位时，flash 中的所有数据都是未加密的（明文）。一级 (ROM) 引导加载程序加载二级引导加载程序。
 
-  2. 固件的引导加载程序将读取 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 值 (``0b000``)。因为该值为 0（偶数位），固件引导加载程序将配置并启用 flash 加密块。关于 flash 加密块的更多信息，请参考 `{IDF_TARGET_NAME} 技术参考手册 <{IDF_TARGET_TRM_CN_URL}>`_。
+  2. 二级引导加载程序将读取 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 值 (``0b000``)。因为该值为 0（偶数位），二级引导加载程序将配置并启用 flash 加密块。关于 flash 加密块的更多信息，请参考 `{IDF_TARGET_NAME} 技术参考手册 <{IDF_TARGET_TRM_CN_URL}>`_。
 
-  3. 固件的引导加载程序使用 RNG（随机数发生器）模块生成 256 位密钥，然后将其写入 `BLOCK_KEYN` eFuse。软件也为存储密钥的块更新了 ``KEY_PURPOSE_N``。由于 ``BLOCK_KEYN`` eFuse 已设置了读保护和写保护位，因此无法通过软件访问密钥。``KEY_PURPOSE_N`` 字段也受写保护。flash 加密操作完全在硬件中完成，无法通过软件访问密钥。如果 eFuse 中已经存在有效密钥（例如用 espefuse 工具烧写的密钥），则会跳过密钥生成，并将该密钥用于 flash 加密过程。
+  3. 二级引导加载程序使用 RNG（随机数发生器）模块生成 256 位密钥，然后将其写入 `BLOCK_KEYN` eFuse。软件也为存储密钥的块更新了 ``KEY_PURPOSE_N``。由于 ``BLOCK_KEYN`` eFuse 已设置了读保护和写保护位，因此无法通过软件访问密钥。``KEY_PURPOSE_N`` 字段也受写保护。flash 加密操作完全在硬件中完成，无法通过软件访问密钥。如果 eFuse 中已经存在有效密钥（例如用 espefuse 工具烧写的密钥），则会跳过密钥生成，并将该密钥用于 flash 加密过程。
 
-  4. flash 加密块将加密 flash 的内容（固件的引导加载程序、应用程序、以及标有“加密”标志的分区）。就地加密可能会耗些时间（对于大分区最多需要一分钟）。
+  4. flash 加密块将加密 flash 的内容（二级引导加载程序、应用程序、以及标有“加密”标志的分区）。就地加密可能会耗些时间（对于大分区最多需要一分钟）。
 
-  5. 固件引导加载程序将在 ``{IDF_TARGET_CRYPT_CNT}`` (0b001) 中设置第一个可用位来对已加密的 flash 内容进行标记。设置奇数位。
+  5. 二级引导加载程序将在 ``{IDF_TARGET_CRYPT_CNT}`` (0b001) 中设置第一个可用位来对已加密的 flash 内容进行标记。设置奇数位。
 
-  6. 对于 :ref:`flash-enc-development-mode`，固件引导加载程序允许 UART 引导加载程序重新烧录加密后的二进制文件。同时，``{IDF_TARGET_CRYPT_CNT}`` eFuse 位不受写入保护。此外，默认情况下，固件引导加载程序设置 ``DIS_DOWNLOAD_ICACHE``、 ``DIS_PAD_JTAG``、 ``DIS_USB_JTAG`` 和 ``DIS_LEGACY_SPI_BOOT`` eFuse 位。
+  6. 对于 :ref:`flash-enc-development-mode`，二级引导加载程序允许 UART 引导加载程序重新烧录加密后的二进制文件。同时，``{IDF_TARGET_CRYPT_CNT}`` eFuse 位不受写入保护。此外，默认情况下，二级引导加载程序设置 ``DIS_DOWNLOAD_ICACHE``、 ``DIS_PAD_JTAG``、 ``DIS_USB_JTAG`` 和 ``DIS_LEGACY_SPI_BOOT`` eFuse 位。
 
-  7. 对于 :ref:`flash-enc-release-mode`，固件引导加载程序设置所有在开发模式下设置的 eFuse 位以及 ``DIS_DOWNLOAD_MANUAL_ENCRYPT``。它还写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 位。要修改此行为，请参阅 :ref:`uart-bootloader-encryption`。
+  7. 对于 :ref:`flash-enc-release-mode`，二级引导加载程序设置所有在开发模式下设置的 eFuse 位以及 ``DIS_DOWNLOAD_MANUAL_ENCRYPT``。它还写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 位。要修改此行为，请参阅 :ref:`uart-bootloader-encryption`。
 
-  8. 重新启动设备以开始执行加密镜像。固件引导加载程序调用 flash 解密块来解密 flash 内容，然后将解密的内容加载到 IRAM 中。
+  8. 重新启动设备以开始执行加密镜像。二级引导加载程序调用 flash 解密块来解密 flash 内容，然后将解密的内容加载到 IRAM 中。
 
 .. only:: SOC_FLASH_ENCRYPTION_XTS_AES_128 and SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
 
-  1. 第一次开机复位时，flash 中的所有数据都是未加密的（明文）。ROM 引导加载程序加载固件引导加载程序。
+  1. 第一次开机复位时，flash 中的所有数据都是未加密的（明文）。ROM 引导加载程序加载二级引导加载程序。
 
-  2. 固件的引导加载程序将读取 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 值 (``0b000``)。因为该值为 0（偶数位），固件引导加载程序将配置并启用 flash 加密块。关于 flash 加密块的更多信息，请参考 `{IDF_TARGET_NAME} 技术参考手册 <{IDF_TARGET_TRM_CN_URL}>`_。
+  2. 二级引导加载程序将读取 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 值 (``0b000``)。因为该值为 0（偶数位），二级引导加载程序将配置并启用 flash 加密块。关于 flash 加密块的更多信息，请参考 `{IDF_TARGET_NAME} 技术参考手册 <{IDF_TARGET_TRM_CN_URL}>`_。
 
-  3. 固件的引导加载程序使用 RNG（随机数发生器）模块生成 256 位或 128 位密钥（具体位数取决于 :ref:`生成的 XTS-AES 密钥大小 <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`），然后将其写入 `BLOCK_KEY0` eFuse。同时，根据所选选项，软件对 ``XTS_KEY_LENGTH_256`` 进行更新。由于 ``BLOCK_KEY0`` eFuse 已设置写保护和读保护位，故无法通过软件访问密钥。flash 加密操作完全在硬件中完成，无法通过软件访问密钥。若使用 128 位 flash 加密密钥，则整个 eFuse 密钥块都受写保护，但只有低 128 位受读保护，高 128 位是可读的，以满足安全启动的需要。如果 flash 加密密钥是 256 位，那么 ``XTS_KEY_LENGTH_256`` 为 1，否则为 0。为防止意外将 eFuse 从 0 改为 1，为 RELEASE 模式设置了一个写保护位。如果 eFuse 中已经存在有效密钥（例如用 espefuse 工具烧写的密钥），则跳过密钥生成，并将该密钥用于 flash 加密过程。
+  3. 二级引导加载程序使用 RNG（随机数发生器）模块生成 256 位或 128 位密钥（具体位数取决于 :ref:`生成的 XTS-AES 密钥大小 <CONFIG_SECURE_FLASH_ENCRYPTION_KEYSIZE>`），然后将其写入 `BLOCK_KEY0` eFuse。同时，根据所选选项，软件对 ``XTS_KEY_LENGTH_256`` 进行更新。由于 ``BLOCK_KEY0`` eFuse 已设置写保护和读保护位，故无法通过软件访问密钥。flash 加密操作完全在硬件中完成，无法通过软件访问密钥。若使用 128 位 flash 加密密钥，则整个 eFuse 密钥块都受写保护，但只有低 128 位受读保护，高 128 位是可读的，以满足安全启动的需要。如果 flash 加密密钥是 256 位，那么 ``XTS_KEY_LENGTH_256`` 为 1，否则为 0。为防止意外将 eFuse 从 0 改为 1，为 RELEASE 模式设置了一个写保护位。如果 eFuse 中已经存在有效密钥（例如用 espefuse 工具烧写的密钥），则跳过密钥生成，并将该密钥用于 flash 加密过程。
 
-  4. flash 加密块将加密 flash 的内容（固件的引导加载程序、应用程序、以及标有“加密”标志的分区）。就地加密可能会耗些时间（对于大分区最多需要一分钟）。
+  4. flash 加密块将加密 flash 的内容（二级引导加载程序、应用程序、以及标有“加密”标志的分区）。就地加密可能会耗些时间（对于大分区最多需要一分钟）。
 
-  5. 固件引导加载程序将在 ``{IDF_TARGET_CRYPT_CNT}`` (0b001) 中设置第一个可用位来对已加密的 flash 内容进行标记。设置奇数位。
+  5. 二级引导加载程序将在 ``{IDF_TARGET_CRYPT_CNT}`` (0b001) 中设置第一个可用位来对已加密的 flash 内容进行标记。设置奇数位。
 
-  6. 对于 :ref:`flash-enc-development-mode`，固件引导加载程序允许 UART 引导加载程序重新烧录加密后的二进制文件。同时，``{IDF_TARGET_CRYPT_CNT}`` eFuse 位不受写入保护。此外，默认情况下，固件引导加载程序设置 ``DIS_DOWNLOAD_ICACHE``、``DIS_PAD_JTAG`` 和 ``DIS_DIRECT_BOOT`` eFuse 位。
+  6. 对于 :ref:`flash-enc-development-mode`，二级引导加载程序允许 UART 引导加载程序重新烧录加密后的二进制文件。同时，``{IDF_TARGET_CRYPT_CNT}`` eFuse 位不受写入保护。此外，默认情况下，二级引导加载程序设置 ``DIS_DOWNLOAD_ICACHE``、``DIS_PAD_JTAG`` 和 ``DIS_DIRECT_BOOT`` eFuse 位。
 
-  7. 对于 :ref:`flash-enc-release-mode`，固件引导加载程序设置所有在开发模式下设置的 eFuse 位以及 ``DIS_DOWNLOAD_MANUAL_ENCRYPT``。它还写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 位。要修改此行为，请参阅 :ref:`uart-bootloader-encryption`。
+  7. 对于 :ref:`flash-enc-release-mode`，二级引导加载程序设置所有在开发模式下设置的 eFuse 位以及 ``DIS_DOWNLOAD_MANUAL_ENCRYPT``。它还写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse 位。要修改此行为，请参阅 :ref:`uart-bootloader-encryption`。
 
-  8. 重新启动设备以开始执行加密镜像。固件引导加载程序调用 flash 解密块来解密 flash 内容，然后将解密的内容加载到 IRAM 中。
+  8. 重新启动设备以开始执行加密镜像。二级引导加载程序调用 flash 解密块来解密 flash 内容，然后将解密的内容加载到 IRAM 中。
 
 在开发阶段常需编写不同的明文 flash 镜像并测试 flash 的加密过程。这要求固件下载模式能够根据需求不断加载新的明文镜像。但是，在制造和生产过程中，出于安全考虑，固件下载模式不应有权限访问 flash 内容。
 
@@ -316,7 +316,7 @@ flash 加密设置
 
        这个命令不包括任何应该写入 flash 分区的用户文件。请在运行此命令前手动写入这些文件，否则在写入前应单独对这些文件进行加密。
 
-该命令将向 flash 写入未加密的镜像：固件引导加载程序、分区表和应用程序。烧录完成后，{IDF_TARGET_NAME} 将复位。在下一次启动时，固件引导加载程序会加密：固件引导加载程序、应用程序分区和标记为“加密”的分区，然后复位。就地加密可能需要时间，对于大分区最多需要一分钟。之后，应用程序在运行时解密并执行命令。
+该命令将向 flash 写入未加密的镜像：二级引导加载程序、分区表和应用程序。烧录完成后，{IDF_TARGET_NAME} 将复位。在下一次启动时，二级引导加载程序会加密：二级引导加载程序、应用程序分区和标记为“加密”的分区，然后复位。就地加密可能需要时间，对于大分区最多需要一分钟。之后，应用程序在运行时解密并执行命令。
 
 下面是启用 flash 加密后 {IDF_TARGET_NAME} 首次启动时的样例输出：
 
@@ -486,7 +486,7 @@ flash 加密设置
 
       这个命令不包括任何应该被写入 flash 上的分区的用户文件。请在运行此命令前手动写入这些文件，否则在写入前应单独对这些文件进行加密。
 
-  该命令将向 flash 写入未加密的镜像：固件引导加载程序、分区表和应用程序。烧录完成后，{IDF_TARGET_NAME} 将复位。在下一次启动时，固件引导加载程序会加密：固件引导加载程序、应用程序分区和标记为 ``加密`` 的分区，然后复位。就地加密可能需要时间，对于大的分区来说可能耗时一分钟。之后，应用程序在运行时被解密并执行。
+  该命令将向 flash 写入未加密的镜像：二级引导加载程序、分区表和应用程序。烧录完成后，{IDF_TARGET_NAME} 将复位。在下一次启动时，二级引导加载程序会加密：二级引导加载程序、应用程序分区和标记为 ``加密`` 的分区，然后复位。就地加密可能需要时间，对于大的分区来说可能耗时一分钟。之后，应用程序在运行时被解密并执行。
 
 如果使用开发模式，那么更新和重新烧录二进制文件最简单的方法是 :ref:`encrypt-partitions`。
 
@@ -549,7 +549,7 @@ flash 加密设置
 
       这个命令不包括任何应该被写入 flash 分区的用户文件。请在运行此命令前手动写入这些文件，否则在写入前应单独对这些文件进行加密。
 
-  该命令将向 flash 写入未加密的镜像：固件引导加载程序、分区表和应用程序。烧录完成后，{IDF_TARGET_NAME} 将复位。在下一次启动时，固件引导加载程序会加密：固件引导加载程序、应用程序分区和标记为 ``加密`` 的分区，然后复位。就地加密可能需要时间，对于大的分区来说可能耗时一分钟。之后，应用程序在运行时被解密并执行。
+  该命令将向 flash 写入未加密的镜像：二级引导加载程序、分区表和应用程序。烧录完成后，{IDF_TARGET_NAME} 将复位。在下一次启动时，二级引导加载程序会加密：二级引导加载程序、应用程序分区和标记为 ``加密`` 的分区，然后复位。就地加密可能需要时间，对于大的分区来说可能耗时一分钟。之后，应用程序在运行时被解密并执行。
 
 一旦在发布模式下启用 flash 加密，引导加载程序将写保护 ``{IDF_TARGET_CRYPT_CNT}`` eFuse。
 
@@ -576,14 +576,14 @@ flash 加密设置
 外部启用 flash 加密
 ----------------------------------
 
-在上述过程中，对与 flash 加密相关的 eFuse 是通过固件引导加载程序烧写的，或者，也可以借助 ``espefuse`` 工具烧写 eFuse。如需了解详情，请参考 :ref:`enable-flash-encryption-externally`。
+在上述过程中，对与 flash 加密相关的 eFuse 是通过二级引导加载程序烧写的，或者，也可以借助 ``espefuse`` 工具烧写 eFuse。如需了解详情，请参考 :ref:`enable-flash-encryption-externally`。
 
 可能出现的错误
 -----------------
 
 一旦启用 flash 加密，``{IDF_TARGET_CRYPT_CNT}`` 的 eFuse 值将设置为奇数位。这意味着所有标有加密标志的分区都会包含加密的密本。如果 {IDF_TARGET_NAME} 错误地加载了明文数据，则会出现以下三种典型的错误情况：
 
-1. 如果通过 **明文固件引导加载程序镜像** 重新烧录了引导加载程序分区，则 ROM 加载器将无法加载固件引导加载程序，并会显示以下错误类型：
+1. 如果通过 **明文二级引导加载程序镜像** 重新烧录了引导加载程序分区，则 ROM 加载器将无法加载二级引导加载程序，并会显示以下错误类型：
 
 .. only:: esp32
 
@@ -635,7 +635,7 @@ flash 加密设置
 
     如果 flash 内容被擦除或损坏，也会出现这个错误。
 
-2. 如果固件的引导加载程序已加密，但通过 **明文分区表镜像** 重新烧录了分区表，引导加载程序将无法读取分区表，从而出现以下错误：
+2. 如果二级引导加载程序已加密，但通过 **明文分区表镜像** 重新烧录了分区表，引导加载程序将无法读取分区表，从而出现以下错误：
 
   .. code-block:: bash
 
@@ -727,7 +727,7 @@ flash 加密范围
 - flash 中可执行的应用程序代码 (IROM)。
 - 所有存储于 flash 中的只读数据 (DROM)。
 - 通过函数 :cpp:func:`spi_flash_mmap` 访问的任意数据。
-- ROM 引导加载程序读取的固件引导加载程序镜像。
+- ROM 引导加载程序读取的二级引导加载程序镜像。
 
 .. important::
 
@@ -976,7 +976,7 @@ flash 加密的高级功能
 
     ``FLASH_CRYPT_CONFIG`` eFuse 决定 flash 加密密钥中随块偏移“调整”的位数。详情可参考 :ref:`flash-encryption-algorithm`。
 
-    首次启动固件引导加载程序时，该值始终设置为最大值 `0xF`。
+    首次启动二级引导加载程序时，该值始终设置为最大值 `0xF`。
 
     可手动写入这些 eFuse，并在首次启动前对其写保护，以便选择不同的调整值。但不推荐该操作。
 
diff --git a/docs/zh_CN/security/secure-boot-v1.rst b/docs/zh_CN/security/secure-boot-v1.rst
index bff6c2691af..69ee5be89de 100644
--- a/docs/zh_CN/security/secure-boot-v1.rst
+++ b/docs/zh_CN/security/secure-boot-v1.rst
@@ -30,11 +30,11 @@
 
 - 为理解安全启动过程，请熟悉标准 :doc:`../api-guides/startup`。
 
-- 安全启动过程会验证启动过程的两个阶段，包括初始软件引导加载程序和随后的分区与应用加载，形成一条信任链。
+- 安全启动过程会验证启动过程的两个阶段，包括二级引导加载程序的加载和随后的分区与应用加载，形成一条信任链。
 
 
 安全启动过程概述
-----------------------------
+---------------------
 
 以下是对安全启动过程的宏观概述，操作指南请参阅 :ref:`secure-boot-how-to`，进一步的技术细节请参阅 :ref:`secure-boot-technical-details`：
 
@@ -42,18 +42,18 @@
 
 2. 安全启动默认在构建过程中签名镜像和分区表数据。配置项 ``Secure boot private signing key`` 是指向 PEM 格式文件中 ECDSA 公钥/私钥对的文件路径。
 
-3. 启用安全启动支持的 ESP-IDF 负责构建软件引导加载程序镜像，签名验证所需公钥已集成到引导加载程序镜像中。此软件引导加载程序镜像将刷写到 0x1000 偏移地址。
+3. 启用安全启动支持的 ESP-IDF 负责构建二级引导加载程序镜像，签名验证所需公钥已集成到该镜像中。此二级引导加载程序镜像将烧写到 0x1000 偏移地址。
 
-4. 初次启动时，软件引导加载程序按以下方式启用安全启动：
+4. 初次启动时，二级引导加载程序按以下方式启用安全启动：
 
-   - 硬件安全启动支持生成设备安全引导加载程序密钥以及安全摘要。密钥借助硬件随机数生成，随后存储在 eFuse 中，受读写保护。硬件安全启动还支持生成安全摘要，摘要源自密钥、初始向量 (IV) 和引导加载程序镜像内容。
+   - 硬件安全启动支持生成设备安全引导加载程序密钥以及安全摘要。密钥借助硬件随机数生成，随后存储在 eFuse 中，受读写保护。硬件安全启动还支持生成安全摘要，摘要源自密钥、初始向量 (IV) 和该引导加载程序镜像的内容。
    - 安全摘要将刷写到 flash 中的 0x0 偏移地址。
    - 根据安全启动配置，烧录 eFuse 以禁用 JTAG 和 ROM 基本解释器。**强烈建议** 禁用 JTAG 和 ROM 基本解释器。
-   - 烧录 ABS_DONE_0 eFuse 后，引导加载程序将始终启用安全启动，软件引导加载程序也随之受到保护。此后，芯片只有在摘要匹配时才会启动引导加载程序镜像。
+   - 烧录 ABS_DONE_0 eFuse 后，该二级引导加载程序将始终启用安全启动，并随之受到保护。此后，芯片只有在摘要匹配时才会启动引导加载程序镜像。
 
-5. 在后续启动过程中，ROM 引导加载程序检测到安全启动 eFuse 已烧录，读取 0x0 处保存的摘要，然后使用硬件安全启动支持来将其与新计算的摘要进行对比。如果摘要不匹配，启动过程终止。摘要读取和对比完全由硬件完成，软件无法读取计算的摘要。更多技术详情，请参阅 :ref:`secure-boot-hardware-support`。
+5. 在后续启动过程中，一级 (ROM) 引导加载程序检测到安全启动 eFuse 已烧录，读取 0x0 处保存的摘要，然后使用硬件安全启动支持来将其与新计算的摘要进行对比。如果摘要不匹配，启动过程终止。摘要读取和对比完全由硬件完成，软件无法读取计算的摘要。更多技术详情，请参阅 :ref:`secure-boot-hardware-support`。
 
-6. 在安全启动模式下运行时，软件引导加载程序使用安全启动签名密钥，该密钥的公钥已嵌入引导加载程序本身，并作为引导加载程序的一部分进行验证，以在启动前验证附加到所有后续分区表和应用程序镜像的签名。
+6. 在安全启动模式下运行时，二级引导加载程序使用安全启动签名密钥，该密钥的公钥已嵌入该引导加载程序本身，并作为该引导加载程序的一部分进行验证，以在启动前验证附加到所有后续分区表和应用程序镜像的签名。
 
 
 密钥
@@ -61,7 +61,7 @@
 
 安全启动过程中使用以下密钥：
 
-- 安全引导加载程序密钥是一个 256 位 AES 密钥，存储在 eFuse 块 2 中。引导加载程序可以使用内部硬件随机数生成器自行生成该密钥，无需手动提供。也可以选择提供该密钥，请参阅 :ref:`secure-boot-reflashable`。在启用安全启动之前，存储该密钥的 eFuse 受到读取和写入保护，防止软件访问。
+- 安全引导加载程序密钥是一个 256 位 AES 密钥，存储在 eFuse 块 2 中。安全引导加载程序可以使用内部硬件随机数生成器自行生成该密钥，无需手动提供。也可以选择提供该密钥，请参阅 :ref:`secure-boot-reflashable`。在启用安全启动之前，存储该密钥的 eFuse 受到读取和写入保护，防止软件访问。
 
   - eFuse 块 2 默认编码方案为 ``None``，块中存储了一个 256 位密钥。在某些版本的 {IDF_TARGET_NAME} 上，编码方案设置为 ``3/4 Encoding``，CODING_SCHEME eFuse 值为 1，且块中必须存储一个 192 位密钥。
 
@@ -73,9 +73,9 @@
 
 - ``secure boot signing key`` 是标准的 ECDSA 公钥/私钥对，以 PEM 格式存储，请参阅 :ref:`secure-boot-image-signing-algorithm`。
 
-  - 该密钥对的公钥用于验证签名，但不用于创建签名。它编译到软件引导加载程序中，并在启动继续前验证启动过程的第二阶段，包括分区表和应用程序镜像。该公钥可以自由分发，无需保密。
+  - 该密钥对的公钥仅用于验证签名，但不用于创建签名。它编译到二级引导加载程序中，并在启动继续前验证启动过程的第二阶段，包括分区表和应用程序镜像。该公钥可以自由分发，无需保密。
 
-  - 该密钥对的私钥必须严格保密。一旦持有该私钥，即可用它对配置了安全启动和匹配公钥的引导加载程序进行身份验证。
+  - 该密钥对的私钥必须严格保密。一旦持有该私钥，即可用它对任何配置了安全启动和匹配公钥的引导加载程序进行身份验证。
 
 
 引导加载程序大小
@@ -117,7 +117,7 @@
 
   如果启用了安全启动，``idf.py flash`` 不会烧录引导加载程序。
 
-8. 重置 {IDF_TARGET_NAME} 以启动烧录的软件引导加载程序。该软件引导加载程序会在芯片上启用安全启动，验证应用程序镜像签名，并启动应用程序。请查看 {IDF_TARGET_NAME} 的串行控制器输出，确保已启用安全启动，且没有因构建配置发生错误。
+8. 重置 {IDF_TARGET_NAME} 以启动烧录的二级引导加载程序。该二级引导加载程序会在芯片上启用安全启动，验证应用程序镜像签名，并启动应用程序。请查看 {IDF_TARGET_NAME} 的串行控制器输出，确保已启用安全启动，且没有因构建配置发生错误。
 
 .. note::
 
@@ -127,12 +127,12 @@
 
   如果在初次启动过程中重置或关闭了 {IDF_TARGET_NAME}，它会在下次启动时重新开始上述步骤。
 
-9. 在后续启动过程中，安全启动硬件将使用安全引导加载程序密钥验证软件引导加载程序是否更改，随后，软件引导加载程序将使用安全启动签名密钥的公钥部分来验证已签名的分区表和应用程序镜像。
+9. 在后续启动过程中，安全启动硬件将使用安全引导加载程序密钥验证二级引导加载程序是否更改，随后，二级引导加载程序将使用安全启动签名密钥的公钥部分来验证已签名的分区表和应用程序镜像。
 
 
 .. _secure-boot-reflashable:
 
-可重复烧录的软件引导加载程序
+可重复烧录的二级引导加载程序
 -------------------------------
 
 对于生产设备，推荐使用 ``Secure Boot: One-Time Flash`` 配置。该模式下，每个设备都对应拥有始终存储在设备内部的唯一密钥。
@@ -229,7 +229,7 @@
 安全启动硬件支持
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-安全启动验证的第一阶段为检查软件引导加载程序，该检查通过硬件完成。{IDF_TARGET_NAME} 的安全启动支持硬件提供以下三种基本操作：
+安全启动验证的第一阶段为检查二级引导加载程序，该检查通过硬件完成。{IDF_TARGET_NAME} 的安全启动支持硬件提供以下三种基本操作：
 
 1. 通过硬件随机数生成器生成一系列随机字节。
 
diff --git a/docs/zh_CN/security/secure-boot-v2.rst b/docs/zh_CN/security/secure-boot-v2.rst
index 640a32889eb..fbdf0eb89b8 100644
--- a/docs/zh_CN/security/secure-boot-v2.rst
+++ b/docs/zh_CN/security/secure-boot-v2.rst
@@ -1,7 +1,7 @@
 :orphan:
 
 安全启动 (secure boot) v2
-============================
+=========================
 
 :link_to_translation:`en:[English]`
 
@@ -9,7 +9,7 @@
 
 {IDF_TARGET_SBV2_KEY:default="RSA-3072", esp32c2="ECDSA-256 或 ECDSA-192", esp32c6="RSA-3072、ECDSA-256 或 ECDSA-192", esp32h2="RSA-3072、ECDSA-256 或 ECDSA-192", esp32p4="RSA-3072、ECDSA-256 或 ECDSA-192", esp32c5="RSA-3072、ECDSA-256、或 ECDSA-192", esp32c61="ECDSA-256 或 ECDSA-192"}
 
-{IDF_TARGET_SECURE_BOOT_OPTION_TEXT:default="", esp32c6="推荐使用 RSA，其验证时间更短。可以在菜单中选择 RSA 和 ECDSA 方案。", esp32h2="推荐使用 RSA，其验证时间更短。可以在菜单中选择 RSA 和 ECDSA 方案。", esp32p4="推荐使用 RSA，其验证时间更短。可以在菜单中选择 RSA 和 ECDSA 方案。", esp32c5="推荐使用 RSA，其验证时间更短。可以在菜单中选择 RSA 和 ECDSA 方案。"}
+{IDF_TARGET_SECURE_BOOT_OPTION_TEXT:default="", esp32c6="推荐使用 RSA，其验证时间更短。可以在菜单中选择 RSA 和 ECDSA 方案。", esp32h2="推荐使用 RSA，其验证时间更短。可以在菜单中选择 RSA 和 ECDSA 方案。", esp32p4="推荐使用 RSA，其验证时间更短。可以在菜单中选择 RSA 和 ECDSA 方案。"}
 
 {IDF_TARGET_ECO_VERSION:default="", esp32="（v3.0 及以上版本）", esp32c3="（v0.3 及以上版本）"}
 
@@ -29,9 +29,9 @@
 
     .. only:: esp32
 
-        芯片版本低于 v3.0 的 ESP32 安全启动请参阅 :doc:`secure-boot-v1`。如果你的芯片版本支持安全启动 v2，推荐使用此模式，相比安全启动 v1 更安全且灵活。
+        芯片版本低于 v3.0 的 ESP32 安全启动请参阅 :doc:`secure-boot-v1`。如果当前芯片版本支持安全启动 v2，推荐使用此模式，相比安全启动 v1 更安全且灵活。
 
-    安全启动 v2 使用基于 {IDF_TARGET_SBV2_SCHEME} 的应用程序和引导加载程序 (bootloader) :ref:`second-stage-bootloader` 验证。若需要使用 {IDF_TARGET_SBV2_SCHEME} 方案对应用程序签名，且无需对 bootloader 签名，同样可以参考本文档。
+    安全启动 v2 使用基于 {IDF_TARGET_SBV2_SCHEME} 的应用程序和 :ref:`second-stage-bootloader` 验证。若需要使用 {IDF_TARGET_SBV2_SCHEME} 方案对应用程序签名，且无需对引导加载程序 (bootloader) 签名，同样可以参考本文档。
 
 .. only:: esp32
 
@@ -47,9 +47,9 @@
     在本指南中，最常用的命令形式为 ``idf.py secure-<command>``，这是对应 ``espsecure.py <command>`` 的封装。基于 ``idf.py`` 的命令能提供更好的用户体验，但与基于 ``espsecure.py`` 的命令相比，可能会损失一部分高级功能。
 
 背景
-----------
+----
 
-安全启动通过检查每个启动的软件是否已签名来确保设备不会运行任何未经授权（即未签名）的代码。在 {IDF_TARGET_NAME} 上，这些软件包括第二阶段的 bootloader 和每个应用程序的二进制文件。注意，第一阶段的 bootloader 是无法更改的 ROM 代码，因此不需要签名。
+安全启动通过检查每个启动的软件是否已签名来确保设备不会运行任何未经授权（即未签名）的代码。在 {IDF_TARGET_NAME} 上，这些软件包括二级引导加载程序和每个应用程序的二进制文件。注意，一级 (ROM) 引导加载程序是无法更改的 ROM 代码，因此不需要签名。
 
 .. only:: esp32 or (SOC_SECURE_BOOT_V2_RSA and not SOC_SECURE_BOOT_V2_ECC)
 
@@ -65,13 +65,13 @@
 
 {IDF_TARGET_NAME} 的安全启动包括以下步骤：
 
-1. 第一阶段 bootloader (ROM boot) 仍处于 ROM 中，加载第二阶段 bootloader，并验证第二阶段 bootloader 的 {IDF_TARGET_SBV2_SCHEME} 签名。验证通过后方可进入第二阶段。
+1. 一级 (ROM) 引导加载程序加载二级引导加载程序，并验证二级引导加载程序的 {IDF_TARGET_SBV2_SCHEME} 签名。验证通过后，方可运行二级引导加载程序。
 
-2. 第二阶段 bootloader 加载特定应用程序镜像时，会验证应用程序的 {IDF_TARGET_SBV2_SCHEME} 签名。若验证通过，则执行应用程序镜像。
+2. 二级引导加载程序加载特定应用程序镜像，并验证应用程序的 {IDF_TARGET_SBV2_SCHEME} 签名。若验证通过，则执行应用程序镜像。
 
 
 优势
-----------
+----
 
 - {IDF_TARGET_SBV2_SCHEME} 的公钥存储在设备上，而相应的 {IDF_TARGET_SBV2_SCHEME} 私钥存储在私密位置，设备无法访问。
 
@@ -83,60 +83,60 @@
 
     - 芯片在量产时最多能生成并存储三个公钥。
 
-    - {IDF_TARGET_NAME} 支持永久注销个别公钥，对此可以选择保守或激进的配置。
+    - {IDF_TARGET_NAME} 支持永久撤销个别公钥，对此可以选择保守或激进的配置。
 
-      - 保守配置：在此情况下，只有在 bootloader 和应用程序成功迁移到新密钥后才会注销旧密钥。
+      - 保守配置：在此情况下，只有在引导加载程序和应用程序成功迁移到新密钥后才会注销旧密钥。
       - 激进配置：在此情况下，只要使用此密钥验证失败，就会立即注销该密钥。
 
-- 应用程序和软件 bootloader 采用相同的镜像格式和签名验证方法。
+- 应用程序和二级引导加载程序采用相同的镜像格式和签名验证方法。
 
 - 设备不存储任何机密信息，因此可以免受被动侧通道攻击的影响，如时序分析或功耗分析。
 
 
 使用安全启动 v2
-----------------------
+---------------
 
 以下为使用安全启动 v2 流程的概述。有关如何启用安全启动，请参阅 :ref:`secure-boot-v2-howto`。
 
-安全启动 v2 使用专用的 *签名块* 验证 bootloader 镜像和应用程序二进制镜像，每个镜像末尾都附加了一个单独生成的签名块。
+安全启动 v2 使用专用的 *签名块* 验证引导加载程序镜像和应用程序二进制镜像，每个镜像末尾都附加了一个单独生成的签名块。
 
 .. only:: esp32
 
-  在 ESP32 芯片版本 v3.0 中，bootloader 或应用程序镜像只能附加一个签名块。
+  在 ESP32 芯片版本 v3.0 中，引导加载程序或应用程序镜像只能附加一个签名块。
 
 .. only:: esp32c2
 
-  在 {IDF_TARGET_NAME} 中，bootloader 或应用程序镜像只能附加一个签名块。
+  在 {IDF_TARGET_NAME} 中，引导加载程序或应用程序镜像只能附加一个签名块。
 
 .. only:: SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
 
-  在 {IDF_TARGET_NAME} 中，bootloader 或应用程序镜像至多可以附加三个签名块。
+  在 {IDF_TARGET_NAME} 中，引导加载程序或应用程序镜像至多可以附加三个签名块。
 
 每个签名块包含前一个镜像的签名和相应的 {IDF_TARGET_SBV2_KEY} 公钥。有关格式详情，请参阅 :ref:`signature-block-format`。{IDF_TARGET_SBV2_KEY} 公钥的摘要存储在 eFuse 中。
 
-应用程序镜像不仅在每次启动时验证，也会在每次空中升级 (OTA) 时验证。如果当前所选 OTA 应用程序镜像无法验证，bootloader 将回退，并寻找其他正确签名的应用程序镜像。
+应用程序镜像不仅在每次启动时验证，也会在每次空中升级 (OTA) 时验证。如果当前所选 OTA 应用程序镜像无法验证，引导加载程序将回退，并寻找其他正确签名的应用程序镜像。
 
 安全启动 v2 流程遵循以下步骤：
 
 1. 启动时，ROM 代码检查 eFuse 中的安全启动 v2 位。如果禁用了安全启动，则执行普通启动；如果启用了安全启动，将继续以下步骤。
 
-2. ROM 代码验证 bootloader 的签名块，请参阅 :ref:`verify_signature-block`。如果验证失败，启动过程将中止。
+2. ROM 代码验证引导加载程序的签名块，请参阅 :ref:`verify_signature-block`。如果验证失败，启动过程将中止。
 
-3. ROM 代码使用原始镜像数据、相应的签名块以及 eFuse 验证 bootloader 镜像，请参阅 :ref:`verify_image`。如果验证失败，启动过程将中止。
+3. ROM 代码使用原始镜像数据、相应的签名块以及 eFuse 验证引导加载程序镜像，请参阅 :ref:`verify_image`。如果验证失败，启动过程将中止。
 
-4. ROM 代码执行 bootloader 。
+4. ROM 代码执行引导加载程序。
 
-5. bootloader 验证应用程序镜像的签名块，请参阅 :ref:`verify_signature-block`。如果验证失败，启动过程将中止。
+5. 引导加载程序验证应用程序镜像的签名块，请参阅 :ref:`verify_signature-block`。如果验证失败，启动过程将中止。
 
-6. bootloader 使用原始镜像数据、相应的签名块以及 eFuse 验证 bootloader 镜像，请参阅 :ref:`verify_image`。如果验证失败，启动过程将中止。如果验证失败，但发现了其他应用程序镜像， bootloader 将使用步骤 5 到 7 验证另一个镜像。该过程将重复，直至找到有效镜像，或所有镜像验证完毕。
+6. 引导加载程序使用原始镜像数据、相应的签名块以及 eFuse 验证引导加载程序镜像，请参阅 :ref:`verify_image`。如果验证失败，启动过程将中止。如果验证失败，但发现了其他应用程序镜像，引导加载程序将使用步骤 5 到 7 验证另一个镜像。该过程将重复，直至找到有效镜像，或所有镜像验证完毕。
 
-7. bootloader 执行经验证的应用程序镜像。
+7. 引导加载程序执行经验证的应用程序镜像。
 
 
 .. _signature-block-format:
 
 签名块格式
-----------------------
+----------
 
 签名块以 4 KB 的整数倍为起始位置，拥有独立 flash 扇区。签名计算覆盖了镜像中的所有字节，包括填充字节，请参阅 :ref:`secure_padding`。
 
@@ -152,21 +152,21 @@
 
         .. only:: not esp32p4 or not esp32c5
 
-        .. list-table:: 签名验证耗时比较
-            :widths: 10 10 20
-            :header-rows: 1
+            .. list-table:: 签名验证耗时比较
+                :widths: 10 10 20
+                :header-rows: 1
 
-            * - **验证方案**
-              - **耗时**
-              - **CPU 频率**
-            * - RSA-3072
-              - {IDF_TARGET_RSA_TIME}
-              - {IDF_TARGET_CPU_FREQ}
-            * - ECDSA-P256
-              - {IDF_TARGET_ECDSA_TIME}
-              - {IDF_TARGET_CPU_FREQ}
+                * - **验证方案**
+                  - **耗时**
+                  - **CPU 频率**
+                * - RSA-3072
+                  - {IDF_TARGET_RSA_TIME}
+                  - {IDF_TARGET_CPU_FREQ}
+                * - ECDSA-P256
+                  - {IDF_TARGET_ECDSA_TIME}
+                  - {IDF_TARGET_CPU_FREQ}
 
-        上表比较了特定方案中验证签名所需的时间，不代表启动时间。
+            上表比较了特定方案中验证签名所需的时间，不代表启动时间。
 
 各签名块内容如下表所示：
 
@@ -216,7 +216,7 @@
 
     .. note::
 
-      R 和 M' 用于硬件辅助的蒙哥马利乘法 (Montgomery Multiplication)。
+        R 和 M' 用于硬件辅助的蒙哥马利乘法 (Montgomery Multiplication)。
 
 .. only:: SOC_SECURE_BOOT_V2_ECC
 
@@ -264,7 +264,7 @@
 .. _secure_padding:
 
 安全填充
---------------
+--------
 
 在安全启动 v2 方案中，应用程序镜像经过处理，会填充到与 flash MMU 页面大小边界对齐，确保只有经过验证的内容会映射到内部地址空间，这称为安全填充。填充后会进行镜像签名计算，随后将签名块 (4 KB) 附加到镜像上。
 
@@ -301,7 +301,7 @@
 .. _verify_signature-block:
 
 验证签名块
------------------------------
+----------
 
 如果签名块的第一个字节是 ``0xe7``，并且偏移量 1196 处存储了有效的 CRC32，则签名块有效，否则无效。
 
@@ -309,39 +309,39 @@
 .. _verify_image:
 
 验证镜像
------------------------------
+--------
 
 如果存储在某个签名块中的公钥是适用于当前设备的有效公钥，且该签名块中存储的签名与从 flash 中读取的镜像数据计算出的签名匹配，则该镜像通过验证。
 
-1. 将嵌入在 bootloader 签名块中的公钥生成的 SHA-256 哈希摘要与存储在 eFuse 中的摘要进行比较，如果公钥的哈希摘要无法与 eFuse 中的任何哈希摘要匹配，则验证失败。
+1. 将嵌入在引导加载程序签名块中的公钥生成的 SHA-256 哈希摘要与存储在 eFuse 中的摘要进行比较，如果公钥的哈希摘要无法与 eFuse 中的任何哈希摘要匹配，则验证失败。
 
 2. 生成应用程序镜像摘要，将其与签名块中的镜像摘要进行匹配，如果无法匹配，则验证失败。
 
 .. only:: esp32 or (SOC_SECURE_BOOT_V2_RSA and not SOC_SECURE_BOOT_V2_ECC)
 
-    3. 使用公钥，采用 RSA-PSS（RFC8017 的第 8.1.2 节）算法，验证 bootloader 镜像的签名，并与步骤 (2) 中计算的镜像摘要比较。
+    3. 使用公钥，采用 RSA-PSS（RFC8017 的第 8.1.2 节）算法，验证引导加载程序镜像的签名，并与步骤 (2) 中计算的镜像摘要比较。
 
 .. only:: SOC_SECURE_BOOT_V2_ECC and not SOC_SECURE_BOOT_V2_RSA
 
-    3. 使用公钥，采用 ECDSA（RFC6090 的第 5.3.3 节）算法，验证 bootloader 镜像的签名，并与步骤 (2) 中计算的镜像摘要比较。
+    3. 使用公钥，采用 ECDSA（RFC6090 的第 5.3.3 节）算法，验证引导加载程序镜像的签名，并与步骤 (2) 中计算的镜像摘要比较。
 
 .. only:: SOC_SECURE_BOOT_V2_ECC and SOC_SECURE_BOOT_V2_RSA
 
-    1. 使用公钥，采用 RSA-PSS（RFC8017 的第 8.1.2 节）算法或 ECDSA（RFC6090 的第 5.3.3 节）算法，验证 bootloader 镜像的签名，并与步骤 (2) 中计算的镜像摘要比较。
+    3. 使用公钥，采用 RSA-PSS（RFC8017 的第 8.1.2 节）算法或 ECDSA（RFC6090 的第 5.3.3 节）算法，验证引导加载程序镜像的签名，并与步骤 (2) 中计算的镜像摘要比较。
 
 
-bootloader 大小
+引导加载程序的大小
 ------------------
 
-启用安全启动和/或 flash 加密都会增加 bootloader 的大小，因此可能需要更新分区表偏移量，请参阅 :ref:`bootloader-size`。
+启用安全启动和/或 flash 加密都会增加引导加载程序的大小，因此可能需要更新分区表偏移量，请参阅 :ref:`bootloader-size`。
 
-禁用 :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` 时，bootloader 将使用 ``esptool`` 的 ``elf2image`` 命令中的 ``--pad-to-size`` 选项进行扇区填充，每个扇区大小为 4 KB。
+禁用 :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` 时，引导加载程序将使用 ``esptool`` 的 ``elf2image`` 命令中的 ``--pad-to-size`` 选项进行扇区填充，每个扇区大小为 4 KB。
 
 
 .. _efuse-usage:
 
 使用 eFuse
------------
+----------
 
 .. only:: esp32
 
@@ -361,11 +361,11 @@ bootloader 大小
 
     - BLOCK_KEYX - 该块包含其在 KEY_PURPOSE_X 中烧录的功能的对应数据，并存储公钥的 SHA-256 哈希摘要。公钥模数、指数、预先计算的 R 和 M' 值的 SHA-256 哈希摘要都将写入 eFuse 密钥块。这个摘要大小为 776 字节，偏移量从 36 到 812，如 :ref:`signature-block-format` 所示。注意，必须设置写保护位，但切勿设置读保护位。
 
-    - KEY_REVOKEX - 与 3 个密钥块中的每一个相对应的注销标记。例如，设置 KEY_REVOKE2 将注销密钥功能为 SECURE_BOOT_DIGEST2 的密钥块。
+    - KEY_REVOKEX - 与 3 个密钥块中的每一个相对应的撤销标记。例如，设置 KEY_REVOKE2 将撤销密钥功能为 SECURE_BOOT_DIGEST2 的密钥块。
 
-    - SECURE_BOOT_AGGRESSIVE_REVOKE - 启用激进的密钥注销。只要与此密钥的验证失败，密钥就会立即注销。
+    - SECURE_BOOT_AGGRESSIVE_REVOKE - 启用激进的密钥撤销。只要与此密钥的验证失败，密钥就会立即撤销。
 
-    为确保后续不会有攻击者添加受信任的密钥，应使用 KEY_REVOKEX 注销所有未使用的密钥摘要槽。若未启用 :ref:`CONFIG_SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS`，应用程序启动时，将在 :cpp:func:`esp_secure_boot_init_checks` 中检查和修复注销操作。
+    为确保后续不会有攻击者添加受信任的密钥，应使用 KEY_REVOKEX 撤销所有未使用的密钥摘要槽。若未启用 :ref:`CONFIG_SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS`，应用程序启动时，将在 :cpp:func:`esp_secure_boot_init_checks` 中检查和修复撤销操作。
 
 密钥必须为可读密钥，以便软件访问。如果密钥设置了读保护，软件只能读取到全为零的数据，导致签名验证失败，启动中止。
 
@@ -373,7 +373,7 @@ bootloader 大小
 .. _secure-boot-v2-howto:
 
 启用安全启动 v2
-----------------------------
+---------------
 
 1. 打开 :ref:`project-configuration-menu`，在 ``Security features`` 下设置 ``Enable hardware Secure Boot in bootloader`` 以启用安全启动模式。
 
@@ -399,81 +399,90 @@ bootloader 大小
 
 .. important::
 
-   通过此方法生成的签名密钥将使用操作系统和其 Python 安装中提供的最佳随机数源，在 OSX/Linux 上为 `/dev/urandom`，在 Windows 上为 `CryptGenRandom()`。如果此随机数源不足以提供足够的安全性，那么生成的私钥也不足以提供足够的安全性。
+    通过此方法生成的签名密钥将使用操作系统和其 Python 安装中提供的最佳随机数源，在 OSX/Linux 上为 `/dev/urandom`，在 Windows 上为 `CryptGenRandom()`。如果此随机数源不足以提供足够的安全性，那么生成的私钥也不足以提供足够的安全性。
 
 .. important::
 
-   在生产环境下，建议使用 OpenSSL 或其他行业标准的加密程序生成密钥对，详情请参阅 :ref:`secure-boot-v2-generate-key`。
+    在生产环境下，建议使用 OpenSSL 或其他行业标准的加密程序生成密钥对，详情请参阅 :ref:`secure-boot-v2-generate-key`。
 
-7. 运行 ``idf.py bootloader`` 构建启用了安全启动的 bootloader ，构建输出中会包含一个烧录命令的提示，使用 ``esptool.py write_flash`` 烧录。
+7. 运行 ``idf.py bootloader`` 构建启用了安全启动的引导加载程序，构建输出中会包含一个烧录命令的提示，使用 ``esptool.py write_flash`` 烧录。
 
-8. 当你准备好烧录 bootloader 时，请运行指定命令并等待烧录完成。注意，此处的指定命令需要手动输入，构建系统不会执行此过程。
+8. 烧录引导加载程序前，请运行指定命令并等待烧录完成。注意，此处的指定命令需要手动输入，构建系统不会执行此过程。
 
 9. 运行 ``idf.py flash`` 构建并烧录分区表以及刚刚构建的应用程序镜像，该镜像使用步骤 6 中生成的签名密钥进行签名。
 
 .. note::
 
-  如果启用了安全启动，``idf.py flash`` 不会烧录 bootloader 。
+    如果启用了安全启动，``idf.py flash`` 不会烧录引导加载程序。
 
-10.  重置 {IDF_TARGET_NAME}，它将启动你烧录的软件 bootloader 。该软件 bootloader 会在芯片上启用安全启动，然后验证应用程序镜像签名，并启动应用程序。请查看 {IDF_TARGET_NAME} 的串行控制器输出，确保已启用安全启动，且没有因构建配置发生错误。
+10.  重置 {IDF_TARGET_NAME} 将启动烧录的二级引导加载程序。该二级引导加载程序会在芯片上启用安全启动，然后验证应用程序镜像签名，并启动应用程序。请查看 {IDF_TARGET_NAME} 的串行控制器输出，确保已启用安全启动，且没有因构建配置发生错误。
 
 .. note::
 
-  在烧录了有效的分区表和应用程序镜像之前，安全启动不会启用，避免在系统完全配置前发生意外情况。
+    在烧录了有效的分区表和应用程序镜像之前，安全启动不会启用，避免在系统完全配置前发生意外情况。
 
 .. note::
 
-  如果在初次启动过程中重置或关闭了 {IDF_TARGET_NAME}，它会在下次启动时重新开始上述步骤。
+    如果在初次启动过程中重置或关闭了 {IDF_TARGET_NAME}，它会在下次启动时重新开始上述步骤。
 
-11. 在后续启动过程中，安全启动硬件会验证软件 bootloader 是否更改，软件 bootloader 会使用其附加的签名块中经验证的公钥部分，验证已签名的应用程序镜像。
+11. 在后续启动过程中，安全启动硬件会验证二级引导加载程序是否更改，二级引导加载程序会使用其附加的签名块中经验证的公钥部分，验证已签名的应用程序镜像。
 
 
 启用安全启动后的限制
------------------------------------------
+--------------------
 
-- 任何更新过的 bootloader 或应用程序都需要使用与已存储在 eFuse 中的摘要相匹配的密钥来签名。
+- 任何更新过的引导加载程序或应用程序都需要使用与已存储在 eFuse 中的摘要相匹配的密钥来签名。
 
 - 注意，启用安全启动或 flash 加密会禁用 ROM 中的 USB-OTG USB 栈，阻止通过该端口进行串行仿真或设备固件更新 (DFU)。
 
+- 一旦启用安全启动，就无法再对 eFuse 密钥进行读保护，这可以避免攻击者对存储公共密钥摘要的 eFuse 块进行读保护，进而导致系统无法验证和处理签名，系统服务无法正常运行。有关读保护密钥的更多信息，请参阅下方详细说明。
+
 烧录读保护密钥
-~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~
 
-一旦启用安全启动，就无法再对 eFuses 进行读保护，这可以避免攻击者对存储公共密钥摘要的 eFuse 块进行读保护，进而导致系统无法验证和处理签名，系统服务无法正常运行。
+**读保护密钥**：
+以下密钥受到读保护后，相应的硬件将直接访问这些密钥（软件无法读取）：
 
-如果第二阶段 bootloader 启用了 :doc:`/security/flash-encryption`，它会确保在第一次启动时生成的 flash 加密密钥被读保护。
+.. list::
 
-如需在设备启用安全启动后对密钥进行读保护，如：
+    :SOC_FLASH_ENC_SUPPORTED:* flash 加密密钥
 
-.. list::
-  :SOC_FLASH_ENC_SUPPORTED:* flash 加密密钥
+    :SOC_HMAC_SUPPORTED:* HMAC 密钥
 
-  :SOC_HMAC_SUPPORTED:* HMAC 密钥
+    :SOC_ECDSA_SUPPORTED:* ECDSA 密钥
 
-  :SOC_ECDSA_SUPPORTED:* ECDSA 密钥
+    :SOC_KEY_MANAGER_SUPPORTED:* 密钥管理器密钥
+
+**不受读保护的密钥**：
+因软件访问需要（软件可读取），以下密钥不受读保护：
+
+.. list::
 
-  :SOC_KEY_MANAGER_SUPPORTED:* 密钥管理器密钥
+    :SOC_SECURE_BOOT_SUPPORTED:* 安全启动公共密钥摘要
+    * 用户数据
 
-请在启用安全启动的同时启用配置项 :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS`，以防止禁用 eFuses 读保护功能。
+启用安全启动后，默认禁用 eFuses 读保护功能。如后续需在应用程序中对某个 eFuse（例如上述读保护密钥列表中的密钥）进行读保护，请在启用安全启动的同时启用配置项 :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS`。
 
-建议在启用安全启动之前，完成全部密钥的烧录。
+建议在启用安全启动之前，完成全部密钥的烧录。如需启用配置项 :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS`，请在所有读保护 eFuse 密钥烧录后，使用 :cpp:func:`esp_efuse_write_field_bit` 烧录 eFuse {IDF_TARGET_EFUSE_WR_DIS_RD_DIS}。
 
-如需启用配置项 :ref:`CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS`，请在所有读保护 eFuses 密钥烧录后，使用 ``esp_efuse.h`` 的 ``esp_efuse_write_field_bit()`` API 烧录 eFuses {IDF_TARGET_EFUSE_WR_DIS_RD_DIS}。
+.. note::
 
+    如果在启用安全启动时，二级引导加载程序启用了 :doc:`/security/flash-encryption`，则首次启动时生成的 flash 加密密钥已经受到读保护。
 
 .. _secure-boot-v2-generate-key:
 
 生成安全启动签名密钥
-----------------------------------
+--------------------
 
-构建系统会提示你，使用 ``idf.py secure-generate-signing-key`` 命令生成新签名密钥。
+根据构建系统提示，使用 ``idf.py secure-generate-signing-key`` 命令生成新签名密钥。
 
 .. only:: esp32 or SOC_SECURE_BOOT_V2_RSA
 
-   参数 ``--version 2`` 会为安全启动 v2 生成 RSA 3072 私钥。此外，也可以传递 ``--scheme rsa3072`` 生成 RSA 3072 私钥。
+    参数 ``--version 2`` 会为安全启动 v2 生成 RSA 3072 私钥。此外，也可以传递 ``--scheme rsa3072`` 生成 RSA 3072 私钥。
 
 .. only:: SOC_SECURE_BOOT_V2_ECC
 
-   传递 ``--version 2 --scheme ecdsa256`` 或 ``--version 2 --scheme ecdsa192`` 选择 ECDSA 方案，生成相应的 ECDSA 私钥。
+    传递 ``--version 2 --scheme ecdsa256`` 或 ``--version 2 --scheme ecdsa192`` 选择 ECDSA 方案，生成相应的 ECDSA 私钥。
 
 签名密钥的强度取决于 (a) 系统的随机数源和 (b) 所用算法的正确性。对于生产设备，建议从具有高质量熵源的系统生成签名密钥，并使用最佳的可用 {IDF_TARGET_SBV2_SCHEME} 密钥生成工具。
 
@@ -493,13 +502,13 @@ bootloader 大小
 
     .. code-block::
 
-      openssl ecparam -name prime192v1 -genkey -noout -out my_secure_boot_signing_key.pem
+        openssl ecparam -name prime192v1 -genkey -noout -out my_secure_boot_signing_key.pem
 
     生成 ECC NIST256p 曲线密钥
 
     .. code-block::
 
-      openssl ecparam -name prime256v1 -genkey -noout -out my_secure_boot_signing_key.pem
+        openssl ecparam -name prime256v1 -genkey -noout -out my_secure_boot_signing_key.pem
 
 注意，安全启动系统的强度取决于能否保持签名密钥的私密性。
 
@@ -507,10 +516,10 @@ bootloader 大小
 .. _remote-sign-v2-image:
 
 远程镜像签名
-------------------------
+------------
 
 使用 ``idf.py`` 进行签名
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
 对于生产构建，将签名密钥存储在远程签名服务器上，而不是本地构建机器上，是一种比较好的方案，这也是默认的 ESP-IDF 安全启动配置。可以使用命令行工具 ``espsecure.py`` 在远程系统上为应用程序镜像和分区表数据签名，供安全启动使用。
 
@@ -520,33 +529,33 @@ bootloader 大小
 
 .. code-block::
 
-  idf.py secure-sign-data BINARY_FILE --keyfile PRIVATE_SIGNING_KEY
+    idf.py secure-sign-data BINARY_FILE --keyfile PRIVATE_SIGNING_KEY
 
-上述命令将镜像签名附加到现有的二进制文件中，你可以使用 `--output` 参数将签名后的二进制文件写入单独的文件：
+上述命令将镜像签名附加到现有的二进制文件中，可以使用 `--output` 参数将签名后的二进制文件写入单独的文件：
 
 .. code-block::
 
-  idf.py secure-sign-data --keyfile PRIVATE_SIGNING_KEY --output SIGNED_BINARY_FILE BINARY_FILE
+    idf.py secure-sign-data --keyfile PRIVATE_SIGNING_KEY --output SIGNED_BINARY_FILE BINARY_FILE
 
 
 使用预计算的签名进行签名
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
-如果你拥有为镜像生成的有效预计算签名及相应公钥，你可以使用这些签名生成一个签名扇区，并将其附加到镜像中。注意，预计算的签名应计算在镜像中的所有字节，包括安全填充字节。
+如果存在为镜像生成的有效预计算签名及相应公钥，可以使用这些签名生成一个签名扇区，并将其附加到镜像中。注意，预计算的签名应计算在镜像中的所有字节，包括安全填充字节。
 
 在此情况下，应禁用选项 :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` 来构建固件镜像。该镜像将进行安全填充，并使用以下命令，生成带签名的二进制文件：
 
 .. code-block::
 
-  idf.py secure-sign-data --pub-key PUBLIC_SIGNING_KEY --signature SIGNATURE_FILE --output SIGNED_BINARY_FILE BINARY_FILE
+    idf.py secure-sign-data --pub-key PUBLIC_SIGNING_KEY --signature SIGNATURE_FILE --output SIGNED_BINARY_FILE BINARY_FILE
 
 上述命令会验证签名，生成签名块（请参阅 :ref:`signature-block-format`），并将其附加到二进制文件中。
 
 
 使用外部硬件安全模块 (HSM) 进行签名
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-为了提高安全性，你可能会使用外部硬件安全模块 (HSM) 存储私钥，该私钥无法直接访问，但具备一个接口，可以生成二进制文件及其相应公钥的签名。
+为了提高安全性，可能需要使用外部硬件安全模块 (HSM) 存储私钥，该私钥无法直接访问，但具备一个接口，可以生成二进制文件及其相应公钥的签名。
 
 在此情况下，请禁用选项 :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` 并构建固件。随后，可以将已进行安全填充的镜像提供给外部硬件安全模块来生成签名。请参阅 `使用外部 HSM 签名 <https://docs.espressif.com/projects/esptool/en/latest/{IDF_TARGET_PATH_NAME}/espsecure/index.html#remote-signing-using-an-external-hsm>`_ 生成已签名镜像。
 
@@ -554,44 +563,44 @@ bootloader 大小
 
     .. note::
 
-      在上述三种远程签名工作流程中，已签名的二进制文件将写入提供给 ``--output`` 参数的文件名中。选项 ``--append_signatures`` 支持将多个签名（最多 3 个）附加到镜像中。
+        在上述三种远程签名工作流程中，已签名的二进制文件将写入提供给 ``--output`` 参数的文件名中。选项 ``--append_signatures`` 支持将多个签名（最多 3 个）附加到镜像中。
 
 .. only:: not SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
 
     .. note::
 
-      在上述三种远程签名工作流程中，已签名的二进制文件将写入提供给 ``--output`` 参数的文件名中。
+        在上述三种远程签名工作流程中，已签名的二进制文件将写入提供给 ``--output`` 参数的文件名中。
 
 
 使用安全启动的建议
---------------------------
+------------------
 
 * 在具备高质量熵源的系统上生成签名密钥。
 * 时刻对签名密钥保密，泄漏此密钥将危及安全启动系统。
 * 不允许第三方使用 ``idf.py secure-`` 命令来观察密钥生成或签名过程的任何细节，这两个过程都容易受到定时攻击或其他侧信道攻击的威胁。
-* 在安全启动配置中启用所有安全启动选项，包括 flash 加密、禁用 JTAG、禁用 BASIC ROM 解释器和禁用 UART bootloader 的加密 flash 访问。
+* 在安全启动配置中启用所有安全启动选项，包括 flash 加密、禁用 JTAG、禁用 BASIC ROM 解释器和禁用 UART 引导加载程序的加密 flash 访问。
 * 结合 :doc:`flash-encryption` 使用安全启动，防止本地读取 flash 内容。
 
 .. only:: SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
 
     密钥管理
-    --------------
+    --------
 
     * 应独立计算并分别存储 1 到 3 个 {IDF_TARGET_SBV2_KEY} 公钥对（密钥 #0, #1, #2）。
     * 完成烧录后，应设置 KEY_DIGEST eFuse 为写保护位。
     * 未使用的 KEY_DIGEST 槽必须烧录其相应的 KEY_REVOKE eFuse，以永久禁用。请在设备离开工厂前完成此操作。
-    * 烧录 eFuse 可以由软件 bootloader 在首次从 menuconfig 启用 ``Secure Boot v2`` 后进行，也可以使用 ``espefuse.py``，后者与 ROM 中的串行 bootloader 通信。
+    * 烧录 eFuse 可以由二级引导加载程序在首次从 menuconfig 启用 ``Secure Boot v2`` 后进行，也可以使用 ``espefuse.py``，后者与 ROM 中的串行引导加载程序通信。
     * KEY_DIGEST 应从密钥摘要 #0 开始，按顺序编号。如果使用了密钥摘要 #1，则必须使用密钥摘要 #0。如果使用了密钥摘要 #2，则必须使用密钥摘要 #0 和 #1。
-    * 软件 bootloader 不支持 OTA 升级，它将至少由一个私钥签名，也可能使用全部三个私钥，并在工厂内烧录。
+    * 二级引导加载程序不支持 OTA 升级，它将至少由一个私钥签名，也可能使用全部三个私钥，并在工厂内烧录。
     * 应用程序应仅由单个私钥签名，其他私钥应妥善保管。但如果需要注销某些私钥，也可以使用多个签名私钥，请参阅下文的 :ref:`secure-boot-v2-key-revocation`。
 
 
     多个密钥管理
-    -------------
+    ------------
 
-    * 在烧录 bootloader 之前，应使用设备整个生命周期所需的所有私钥对 bootloader 签名。
-    * 构建系统每次只能使用一个私钥签名，如果需要，你必须手动运行命令以附加更多签名。
-    * 你可以使用 ``idf.py secure-sign-data`` 的附加功能，此命令也将在启用安全启动 v2 的 bootloader 编译的末尾显示。
+    * 在烧录引导加载程序之前，应使用设备整个生命周期所需的所有私钥对引导加载程序签名。
+    * 构建系统每次只能使用一个私钥签名，如果需要，必须手动运行命令以附加更多签名。
+    * 可以使用 ``idf.py secure-sign-data`` 的附加功能，此命令也将在启用安全启动 v2 的引导加载程序编译的末尾显示。
 
     .. code-block::
 
@@ -606,21 +615,22 @@ bootloader 大小
 
     .. _secure-boot-v2-key-revocation:
 
-    注销密钥管理
-    --------------
+    撤销密钥管理
+    ------------
 
     * 密钥按线性顺序处理，即密钥 #0、密钥 #1、密钥 #2。
+    * 撤销一个密钥后，其余未被撤销的密钥仍可用于应用程序签名。例如，如密钥 #1 被撤销，仍然可以使用密钥 #0 和密钥 #2 给应用程序签名。
     * 应用程序每次应只使用一个密钥签名，尽量避免暴露未使用的私钥。
-    * bootloader 可以使用来自工厂的多个函数签名。
+    * 引导加载程序可以使用来自工厂的多个函数签名。
 
     .. note::
 
         请注意，启用配置 :ref:`CONFIG_SECURE_BOOT_ALLOW_UNUSED_DIGEST_SLOTS` 只能确保 **应用程序** 不会撤销未使用的摘要槽。
-        若想在设备首次启动时启用安全启动，那么即使启用了上述配置，bootloader 也会在启用安全启动时撤销未使用的摘要槽，因为保留未使用的密钥槽会构成安全隐患。
-        如果在开发流程中需要保留未使用摘要槽，则应从外部启用安全启动 (:ref:`enable-secure-boot-v2-externally`)，而不是在启动设备时启用安全启动，这样 bootloader 就无需启用安全启动，从而避免安全隐患。
+        若想在设备首次启动时启用安全启动，那么即使启用了上述配置，引导加载程序也会在启用安全启动时撤销未使用的摘要槽，因为保留未使用的密钥槽会构成安全隐患。
+        如果在开发流程中需要保留未使用摘要槽，则应从外部启用安全启动 (:ref:`enable-secure-boot-v2-externally`)，而不是在启动设备时启用安全启动，这样引导加载程序就无需启用安全启动，从而避免安全隐患。
 
     保守方法
-    ~~~~~~~~~~~~
+    ~~~~~~~~
 
     假设一个受信任的私钥 (N-1) 受到威胁，需要升级到新的密钥对 (N)。
 
@@ -628,55 +638,131 @@ bootloader 大小
     2. 新的 OTA 更新写入未使用的 OTA 应用程序分区。
     3. 验证新应用程序的签名块。对比公钥与 eFuse 中烧录的摘要，并使用已验证的公钥验证应用程序。
     4. 将活动分区设置为新的 OTA 应用程序分区。
-    5. 设备重置并加载使用密钥 #N-1 验证的 bootloader ，随后启动使用密钥 #N 验证的新应用程序。
-    6. 新应用程序使用密钥 #N 验证 bootloader ，这是最后的检查，然后运行代码注销密钥 #N-1，即设置 KEY_REVOKE eFuse 位。
+    5. 设备重置并加载使用密钥 #N-1 验证的引导加载程序，随后启动使用密钥 #N 验证的新应用程序。
+    6. 新应用程序使用密钥 #N 验证引导加载程序，这是最后的检查，然后运行代码注销密钥 #N-1，即设置 KEY_REVOKE eFuse 位。
     7. 可以使用 API `esp_ota_revoke_secure_boot_public_key()` 注销密钥 #N-1。
 
-    * 类似的方法也可以用于物理重新烧录，以使用新的密钥，还可以同时更改 bootloader 的内容。
+    * 类似的方法也可以用于物理重新烧录，以使用新的密钥，还可以同时更改引导加载程序的内容。
+
+    .. note::
+
+        当前未使用的密钥可以被撤销。例如，如果活动应用程序由密钥 #0 签名，但密钥 #1 已被泄露，请通过上述方法撤销密钥 #1。新的 OTA 更新应继续使用密钥 #0 签名，并且可以使用 API `esp_ota_revoke_secure_boot_public_key (SECURE_BOOT_PUBLIC_KEY_INDEX_[N])` 来撤销密钥 #N（在此例中，N 为 1）。撤销该密钥后，其余密钥以后仍可用于给应用程序签名。
 
 
     .. _secure-boot-v2-aggressive-key-revocation:
 
     激进方法
-    ~~~~~~~~~~~~~~
+    ~~~~~~~~
 
-    ROM 代码具备一项额外功能，即在签名验证失败时可以注销公钥摘要。
+    ROM 代码具备一项额外功能，即在签名验证失败时可以撤销公钥摘要。
 
     请烧录 ``SECURE_BOOT_AGGRESSIVE_REVOKE`` eFuse 或启用 :ref:`CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE` 以启用此功能。
 
-    注销密钥仅适用于成功启用了安全启动的情况。此外，在签名块无效或镜像摘要无效的情况下不会注销密钥，仅在签名验证失败时，即在 :ref:`verify_image` 的第 3 步中验证失败时，才会执行注销操作。
+    撤销密钥仅适用于成功启用了安全启动的情况。此外，在签名块无效或镜像摘要无效的情况下不会撤销密钥，仅在签名验证失败时，即在 :ref:`verify_image` 的第 3 步中验证失败时，才会执行撤销操作。
 
-    一旦注销了密钥，它将无法再用于验证镜像签名。该功能提供了强大的物理攻击防护，但如果由于签名验证失败而注销了所有密钥，可能会导致设备再也无法使用。
+    一旦撤销了密钥，它将无法再用于验证镜像签名。该功能提供了强大的物理攻击防护，但如果由于签名验证失败而撤销了所有密钥，可能会导致设备再也无法使用。
 
 
 .. _secure-boot-v2-technical-details:
 
 技术细节
------------------
-
-以下章节包含安全启动元件的详细参考描述：
+--------
 
+以下章节包含对各安全启动要素的详细参考描述。
 
-手动命令
-~~~~~~~~~~~~~~~
+安全启动已集成到 ESP-IDF 构建系统中，因此 ``idf.py build`` 将进行应用程序镜像签名。启用 :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` 后，``idf.py bootloader`` 将生成一个已签名的引导加载程序。
 
-安全启动已集成到 ESP-IDF 构建系统中，因此 ``idf.py build`` 将进行应用程序镜像签名。启用 :ref:`CONFIG_SECURE_BOOT_BUILD_SIGNED_BINARIES` 后，``idf.py bootloader`` 将生成一个已签名的 bootloader 。
+当然，也可以使用 ``idf.py`` 或 ``openssl`` 工具生成独立的签名并对其进行验证。推荐使用 ``idf.py``，但如果需要在非 ESP-IDF 环境中生成或验证签名，也可以使用 ``openssl`` 命令，安全启动 v2 的签名生成符合标准签名算法。
 
-然而，也可以使用 ``idf.py`` 工具生成独立的签名和摘要。
+使用 ``idf.py`` 生成并验证签名
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-二进制镜像签名：
+1. 二进制镜像签名：
 
 .. code-block::
 
-  idf.py secure-sign-data --keyfile ./my_signing_key.pem --output ./image_signed.bin image-unsigned.bin
+    idf.py secure-sign-data --keyfile ./my_signing_key.pem --output ./image_signed.bin image-unsigned.bin
 
 Keyfile 是包含 {IDF_TARGET_SBV2_KEY} 签名私钥的 PEM 文件。
 
+2. 验证二进制镜像签名：
+
+.. code-block::
+
+    idf.py secure-verify-signature --keyfile ./my_signing_key.pem image_signed.bin
+
+Keyfile 是包含 {IDF_TARGET_SBV2_KEY} 签名公钥/私钥的 PEM 文件。
+
+使用 OpenSSL 生成并验证签名
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+一般推荐使用 ``idf.py`` 工具来生成并验证签名，如果想通过 OpenSSL 生成并验证签名，请参照下列命令：
+
+1. 生成镜像二进制文件的摘要。
+
+    .. code-block:: bash
+
+        openssl dgst -sha256 -binary BINARY_FILE  > DIGEST_BINARY_FILE
+
+2. 使用上述摘要，生成镜像签名。
+
+   .. only:: SOC_SECURE_BOOT_V2_RSA
+
+        生成 RSA-PSS 签名：
+
+            .. code-block:: bash
+
+                openssl pkeyutl -sign \
+                    -in  DIGEST_BINARY_FILE \
+                    -inkey PRIVATE_SIGNING_KEY \
+                    -out SIGNATURE_FILE \
+                    -pkeyopt digest:sha256 \
+                    -pkeyopt rsa_padding_mode:pss \
+                    -pkeyopt rsa_pss_saltlen:32
+
+    .. only:: SOC_SECURE_BOOT_V2_ECC
+
+        生成 ECDSA 签名：
+
+            .. code-block:: bash
+
+                openssl pkeyutl -sign \
+                    -in  DIGEST_BINARY_FILE \
+                    -inkey PRIVATE_SIGNING_KEY \
+                    -out SIGNATURE_FILE
+
+3. 验证生成的签名。
+
+    .. only:: SOC_SECURE_BOOT_V2_RSA
+
+        验证 RSA-PSS 签名：
+
+            .. code-block:: bash
+
+                openssl pkeyutl -verify \
+                    -in DIGEST_BINARY_FILE \
+                    -pubin -inkey PUBLIC_SIGNING_KEY \
+                    -sigfile SIGNATURE_FILE \
+                    -pkeyopt rsa_padding_mode:pss \
+                    -pkeyopt rsa_pss_saltlen:32 \
+                    -pkeyopt digest:sha256
+
+    .. only:: SOC_SECURE_BOOT_V2_ECC
+
+        验证 ECDSA 签名：
+
+            .. code-block:: bash
+
+                openssl pkeyutl -verify \
+                    -in DIGEST_BINARY_FILE \
+                    -pubin -inkey PUBLIC_SIGNING_KEY \
+                    -sigfile SIGNATURE_FILE
+
 
 .. _secure-boot-v2-and-flash-encr:
 
 安全启动 & flash 加密
-------------------------------
+---------------------
 
 如果使用安全启动时没有启用 :doc:`flash-encryption`，可能会发生 ``time-of-check to time-of-use`` 攻击，即在验证并运行镜像后交换 flash 内容。因此，建议同时使用这两个功能。
 
@@ -684,7 +770,7 @@ Keyfile 是包含 {IDF_TARGET_SBV2_KEY} 签名私钥的 PEM 文件。
 
     .. important::
 
-       {IDF_TARGET_NAME} 只有一个 eFuse 密钥块，用于存储两种密钥：安全启动和 flash 加密，但 eFuse 密钥块只能烧录一次，因此建议同时烧录这两种密钥。注意，``Secure Boot`` 和 ``Flash Encryption`` 无法分别启用，否则后续写入 eFuse 密钥块将返回错误。
+        {IDF_TARGET_NAME} 只有一个 eFuse 密钥块，用于存储两种密钥：安全启动和 flash 加密，但 eFuse 密钥块只能烧录一次，因此建议同时烧录这两种密钥。注意，``Secure Boot`` 和 ``Flash Encryption`` 无法分别启用，否则后续写入 eFuse 密钥块将返回错误。
 
 
 .. _signed-app-verify-v2:
@@ -694,7 +780,7 @@ Keyfile 是包含 {IDF_TARGET_SBV2_KEY} 签名私钥的 PEM 文件。
 
 无需启用硬件安全启动选项，即可在 OTA 更新时验证应用程序的安全启动 v2 签名。这种方法采用了与安全启动 v2 相同的应用程序签名方案，但不同于硬件安全启动，软件安全启动无法阻止能够写入 flash 的攻击者绕过签名验证。
 
-如果在启动时无法接受安全启动验证的延迟，和/或威胁模型不包括物理访问或攻击者在 flash 中写入 bootloader 或应用程序分区，则适合使用未启用硬件安全启动的验证。
+如果在启动时无法接受安全启动验证的延迟，和/或威胁模型不包括物理访问或攻击者在 flash 中写入引导加载程序或应用程序分区，则适合使用未启用硬件安全启动的验证。
 
 在此模式下，当前运行的应用程序签名块中的公钥将用于验证新更新的应用程序签名。更新时，不会验证运行中的应用程序签名，而是假定它有效。通过这种方式，系统建立了从当前运行的应用程序到新更新的应用程序之间的信任链。
 
@@ -712,7 +798,7 @@ Keyfile 是包含 {IDF_TARGET_SBV2_KEY} 签名私钥的 PEM 文件。
 .. _signed-app-verify-v2-howto:
 
 启用已签名的应用程序验证
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~
 
 1. 打开 :ref:`project-configuration-menu` > ``Security features``。
 
@@ -726,7 +812,7 @@ Keyfile 是包含 {IDF_TARGET_SBV2_KEY} 签名私钥的 PEM 文件。
 
 .. only:: SOC_SECURE_BOOT_V2_ECC and not SOC_SECURE_BOOT_V2_RSA
 
-    1. 确保 ``App Signing Scheme`` 设置为 ``ECDSA (v2)``。
+    2. 确保 ``App Signing Scheme`` 设置为 ``ECDSA (v2)``。
 
 .. only:: SOC_SECURE_BOOT_V2_RSA and SOC_SECURE_BOOT_V2_ECC
 
@@ -745,11 +831,11 @@ Keyfile 是包含 {IDF_TARGET_SBV2_KEY} 签名私钥的 PEM 文件。
 
 
 进阶功能
------------------
+--------
 
 JTAG 调试
-~~~~~~~~~~~~~~
+~~~~~~~~~
 
-启用安全启动模式时，eFuse 会默认禁用 JTAG。初次启动时，bootloader 即禁用 JTAG 调试功能，并启用安全启动模式。
+启用安全启动模式时，eFuse 会默认禁用 JTAG。初次启动时，引导加载程序禁用 JTAG 调试功能，并启用安全启动模式。
 
 有关在启用安全启动或已签名应用程序验证的情况下使用 JTAG 调试的更多信息，请参阅 :ref:`jtag-debugging-security-features`。
diff --git a/docs/zh_CN/security/security-features-enablement-workflows.rst b/docs/zh_CN/security/security-features-enablement-workflows.rst
index d7f9a8a3ddf..9d63510bc5c 100644
--- a/docs/zh_CN/security/security-features-enablement-workflows.rst
+++ b/docs/zh_CN/security/security-features-enablement-workflows.rst
@@ -18,6 +18,11 @@
 
 这份指南介绍了一系列工作流程，从而在外部主机的协助下启用设备的安全功能。这些工作流程分为多个阶段，每个阶段都会在主机上生成签名/加密密钥，从而在发生电力或其他故障时，提高恢复几率。此外，在主机的协助下，这些流程将加快整体配置过程（例如，在主机上加密固件要比在设备上加密更快）。
 
+.. only:: TARGET_SUPPORT_QEMU
+
+   .. important::
+
+      可以在 :doc:`../api-guides/tools/qemu` 中虚拟测试 {IDF_TARGET_NAME} 目标芯片的安全功能。安全工作流程建立后，便可在真实硬件上继续操作。
 
 目标
 ----
@@ -25,7 +30,7 @@
 #. 用逐步指令简化启用安全功能的传统工作流程。
 #. 设计比基于固件的传统工作流更加灵活的工作流。
 #. 将工作流划分为多个小操作，从而提高可靠性。
-#. 消除对 :ref:`second-stage-bootloader` （固件引导加载程序）的依赖。
+#. 消除对 :ref:`second-stage-bootloader` 的依赖。
 
 准备工作
 --------
@@ -297,7 +302,7 @@
         :esp32: - :ref:`选择 UART ROM 下载模式（永久禁用（推荐））<CONFIG_SECURE_UART_ROM_DL_MODE>` （注意，此选项仅在 :ref:`CONFIG_ESP32_REV_MIN` 设为 3 (ESP32 V3) 时可用）。UART ROM 下载模式在默认设置中自动启用，但建议永久禁用此模式以减少攻击者可用的选项。
         :not esp32: - :ref:`选择发布模式 <CONFIG_SECURE_FLASH_ENCRYPTION_MODE>` （注意，若选择发布模式，则将烧录 ``EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT`` eFuse 位，ROM 下载模式下 flash 加密硬件将被禁用）。
         :not esp32: - :ref:`选择 UART ROM 下载模式（永久切换到安全模式（推荐））<CONFIG_SECURE_UART_ROM_DL_MODE>`。这是推荐的默认选项，如果不需要，也可将其更改为永久禁用 UART ROM 下载模式。
-        - :ref:`选择适当的引导程序日志级别 <CONFIG_BOOTLOADER_LOG_LEVEL>`。
+        - :ref:`选择适当的引导加载程序日志级别 <CONFIG_BOOTLOADER_LOG_LEVEL>`。
         - 保存配置并退出。
 
 7. 构建、加密并烧录二进制文件
@@ -324,7 +329,7 @@
 
         .. only:: esp32
 
-            如果 ESP32 在 eFuse 中使用非默认的 :ref:`FLASH_CRYPT_CONFIG 值 <setting-flash-crypt-config>`，需要将 ``--flash_crypt_conf`` 参数传递给 ``espsecure.py`` 以设置匹配值。如果设备自行配置 flash 加密，则不会发生这种情况，但是如果手动烧录了 eFuses 启用 flash 加密，就有可能发生。
+            如果 ESP32 在 eFuse 中使用非默认的 :ref:`FLASH_CRYPT_CONFIG 值 <setting-flash-crypt-config>`，需要将 ``--flash_crypt_conf`` 参数传递给 ``espsecure.py`` 以设置匹配值。如果通过二级引导加载程序配置 flash 加密，则不会发生这种情况，但是如果手动烧录了 eFuses 启用 flash 加密，就有可能发生。
 
     使用 ``espsecure.py decrypt_flash_data`` 命令时，可以用相同的选项（和不同的输入或输出文件）来解密密文 flash 或之前加密的文件。
 
@@ -518,7 +523,7 @@ flash 加密指南
 
 6. 构建二进制文件
 
-    默认情况下，ROM 引导加载程序只会验证 :ref:`second-stage-bootloader` （固件引导加载程序）。只有在启用 :ref:`CONFIG_SECURE_BOOT` 选项（并将 :ref:`CONFIG_SECURE_BOOT_VERSION` 设置为 ``SECURE_BOOT_V2_ENABLED``）时，固件引导加载程序才会在构建引导加载程序时验证应用程序分区。
+    默认情况下，一级 (ROM) 引导加载程序只会验证 :ref:`second-stage-bootloader`。只有在启用 :ref:`CONFIG_SECURE_BOOT` 选项（并将 :ref:`CONFIG_SECURE_BOOT_VERSION` 设置为 ``SECURE_BOOT_V2_ENABLED``）时，二级引导加载程序才会在构建引导加载程序时验证应用程序分区。
 
     A) 打开 :ref:`project-configuration-menu`，在 ``Security features`` 中设置 ``Enable hardware Secure Boot in bootloader`` 启用 Secure Boot。
 
diff --git a/docs/zh_CN/security/security.rst b/docs/zh_CN/security/security.rst
index 455c79723f7..104c38b7fbc 100644
--- a/docs/zh_CN/security/security.rst
+++ b/docs/zh_CN/security/security.rst
@@ -13,6 +13,12 @@
 
     在本指南中，最常用的命令形式为 ``idf.py secure-<command>``，这是对应 ``espsecure.py <command>`` 的封装。基于 ``idf.py`` 的命令能提供更好的用户体验，但与基于 ``espsecure.py`` 的命令相比，可能会损失一部分高级功能。
 
+.. only:: TARGET_SUPPORT_QEMU
+
+   .. important::
+
+      可以在 :doc:`../api-guides/tools/qemu` 中虚拟测试 {IDF_TARGET_NAME} 目标芯片的安全功能。安全工作流程建立后，便可在真实硬件上继续操作。
+
 目标
 ----
 
diff --git a/docs/zh_CN/versions.rst b/docs/zh_CN/versions.rst
index fca9f997a45..41f12afa55d 100644
--- a/docs/zh_CN/versions.rst
+++ b/docs/zh_CN/versions.rst
@@ -125,7 +125,7 @@ ESP-IDF 的每个主要版本和次要版本（V4.1、V4.2 等）的支持期限
 
     idf.py --version
 
-此外，由于 ESP-IDF 的版本也已编译至固件中，因此你也可以使用宏 ``IDF_VER`` 查看 ESP-IDF 的版本（以字符串的格式）。ESP-IDF 默认引导程序会在设备启动时打印 ESP-IDF 的版本。请注意，在 GitHub 仓库中的代码更新时，代码中的版本信息仅会在源代码重新编译或在清除编译时才会更新，因此打印出来的版本可能并不是最新的。
+此外，由于 ESP-IDF 的版本也已编译至固件中，因此你也可以使用宏 ``IDF_VER`` 查看 ESP-IDF 的版本（以字符串的格式）。ESP-IDF 默认引导加载程序会在设备启动时打印 ESP-IDF 的版本。请注意，在 GitHub 仓库中的代码更新时，代码中的版本信息仅会在源代码重新编译或在清除编译时才会更新，因此打印出来的版本可能并不是最新的。
 
 如果编写的代码需要支持多个 ESP-IDF 版本，可以在编译时使用 :ref:`compile-time macros<idf-version-h>` 检查版本。
 
diff --git a/examples/bluetooth/.build-test-rules.yml b/examples/bluetooth/.build-test-rules.yml
index 2033d2a278a..20f2345ef9b 100644
--- a/examples/bluetooth/.build-test-rules.yml
+++ b/examples/bluetooth/.build-test-rules.yml
@@ -19,7 +19,20 @@ examples/bluetooth/bluedroid/ble:
   <<: *bt_default_depends
   disable:
     - if: SOC_BT_SUPPORTED != 1
-
+  depends_components:
+    - bt
+    - esp_phy
+    - nvs_flash
+    - esp_coex
+    - esp_log
+    - esp_console
+    - mbedtls
+    - vfs
+    - esp_driver_gpio
+    - esp_driver_i2s
+    - esp_driver_uart
+  depends_filepatterns:
+    - examples/bluetooth/bluedroid/ble/pytest_ble_test.py
 
 examples/bluetooth/bluedroid/ble/ble_hid_device_demo:
   disable:
@@ -27,9 +40,43 @@ examples/bluetooth/bluedroid/ble/ble_hid_device_demo:
   depends_components:
     - esp_driver_gpio
 
+examples/bluetooth/bluedroid/ble/ble_throughput:
+  <<: *bt_default_depends
+  disable:
+    - if: SOC_BT_SUPPORTED != 1
+  depends_components:
+    - bt
+    - esp_phy
+    - nvs_flash
+    - esp_coex
+    - esp_log
+    - esp_console
+    - mbedtls
+    - vfs
+    - esp_driver_gpio
+    - esp_driver_i2s
+    - esp_driver_uart
+  depends_filepatterns:
+    - examples/bluetooth/bluedroid/ble_50/pytest_ble_throughput_test.py
+
 examples/bluetooth/bluedroid/ble_50:
+  <<: *bt_default_depends
   disable:
     - if: SOC_BLE_50_SUPPORTED != 1
+  depends_components:
+    - bt
+    - esp_phy
+    - nvs_flash
+    - esp_coex
+    - esp_log
+    - esp_console
+    - mbedtls
+    - vfs
+    - esp_driver_gpio
+    - esp_driver_i2s
+    - esp_driver_uart
+  depends_filepatterns:
+    - examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py
 
 examples/bluetooth/bluedroid/classic_bt:
   disable:
diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_receiver b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_receiver
new file mode 100644
index 00000000000..9c392443402
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_receiver
@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_IBEACON_RECEIVER=y
diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_sender b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_sender
new file mode 100644
index 00000000000..420137b8bac
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.esp32c2_xtal26m_sender
@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_IBEACON_SENDER=y
diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.receiver b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.receiver
new file mode 100644
index 00000000000..b78485c510f
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.receiver
@@ -0,0 +1 @@
+CONFIG_IBEACON_RECEIVER=y
diff --git a/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.sender b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.sender
new file mode 100644
index 00000000000..d463a13eaf4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_ibeacon/sdkconfig.ci.sender
@@ -0,0 +1 @@
+CONFIG_IBEACON_SENDER=y
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py b/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py
new file mode 100644
index 00000000000..f7194312ec8
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/pytest_ble_throughput_test.py
@@ -0,0 +1,162 @@
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import os.path
+import time
+from typing import Tuple
+
+import pytest
+from pytest_embedded_idf.dut import IdfDut
+
+
+# Case 1: gatt write throughput test
+@pytest.mark.esp32
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32c61
+@pytest.mark.esp32c5
+@pytest.mark.esp32h2
+@pytest.mark.esp32s3
+@pytest.mark.wifi_two_dut
+@pytest.mark.parametrize(
+    'count, app_path, config, erase_all', [
+        (2,
+         f'{os.path.join(os.path.dirname(__file__), "throughput_server")}|{os.path.join(os.path.dirname(__file__), "throughput_client")}',
+         'write', 'y'),
+    ],
+    indirect=True,
+)
+def test_gatt_write_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    server = dut[0]
+    client = dut[1]
+    client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+    server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    client.expect_exact('GATT client register, status 0', timeout=30)
+    server.expect_exact('GATT server register, status 0', timeout=30)
+    server.expect_exact('Advertising start successfully', timeout=30)
+    client.expect_exact('Scanning start successfully', timeout=30)
+    client.expect_exact('Device found ', timeout=30)
+    server.expect_exact('Service start, status 0', timeout=30)
+    server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30)
+    client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30)
+    client.expect_exact('MTU exchange, status 0, MTU 517', timeout=30)
+    server.expect_exact('MTU exchange, MTU 517', timeout=30)
+    client.expect_exact('Service search complete', timeout=30)
+    start_time = time.time()
+    while time.time() - start_time < 30:
+        throughput = int(server.expect(r'GATTC write Bit rate = (\d+) Byte/s', timeout=30).group(1).decode('utf8'))
+        assert throughput > 50000 or throughput < 95000
+
+
+# Case 2: gatt write throughput test for ESP32C2 26mhz xtal
+@pytest.mark.esp32c2
+@pytest.mark.wifi_two_dut
+@pytest.mark.xtal_26mhz
+@pytest.mark.parametrize(
+    'count, target, baud, app_path, config, erase_all', [
+        (2, 'esp32c2|esp32c2', '74880',
+         f'{os.path.join(os.path.dirname(__file__), "throughput_server")}|{os.path.join(os.path.dirname(__file__), "throughput_client")}',
+         'esp32c2_xtal26m_write', 'y'),
+    ],
+    indirect=True,
+)
+def test_c2_26mhz_xtal_write_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    server = dut[0]
+    client = dut[1]
+    client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+    server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    client.expect_exact('GATT client register, status 0', timeout=30)
+    server.expect_exact('GATT server register, status 0', timeout=30)
+    server.expect_exact('Advertising start successfully', timeout=30)
+    client.expect_exact('Scanning start successfully', timeout=30)
+    client.expect_exact('Device found ', timeout=30)
+    server.expect_exact('Service start, status 0', timeout=30)
+    server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30)
+    client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30)
+    client.expect_exact('MTU exchange, status 0, MTU 517', timeout=30)
+    server.expect_exact('MTU exchange, MTU 517', timeout=30)
+    client.expect_exact('Service search complete', timeout=30)
+    start_time = time.time()
+    while time.time() - start_time < 30:
+        throughput = int(server.expect(r'GATTC write Bit rate = (\d+) Byte/s', timeout=30).group(1).decode('utf8'))
+        assert throughput > 50000 or throughput < 95000
+
+
+# Case 3: gatt notify throughput test
+@pytest.mark.esp32
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32c61
+@pytest.mark.esp32c5
+@pytest.mark.esp32h2
+@pytest.mark.esp32s3
+@pytest.mark.wifi_two_dut
+@pytest.mark.parametrize(
+    'count, app_path, config, erase_all', [
+        (2,
+         f'{os.path.join(os.path.dirname(__file__), "throughput_server")}|{os.path.join(os.path.dirname(__file__), "throughput_client")}',
+         'notify', 'y'),
+    ],
+    indirect=True,
+)
+def test_gatt_notify_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    server = dut[0]
+    client = dut[1]
+    client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+    server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    client.expect_exact('GATT client register, status 0', timeout=30)
+    server.expect_exact('GATT server register, status 0', timeout=30)
+    server.expect_exact('Advertising start successfully', timeout=30)
+    client.expect_exact('Scanning start successfully', timeout=30)
+    client.expect_exact('Device found ', timeout=30)
+    server.expect_exact('Service start, status 0', timeout=30)
+    server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30)
+    client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30)
+    client.expect_exact('MTU exchange, status 0, MTU 517', timeout=30)
+    server.expect_exact('MTU exchange, MTU 517', timeout=30)
+    client.expect_exact('Service search complete', timeout=30)
+    client.expect_exact('Notification register successfully', timeout=30)
+    server.expect_exact('Notification enable', timeout=30)
+    start_time = time.time()
+    while time.time() - start_time < 30:
+        throughput = int(client.expect(r'Notify Bit rate = (\d+) Byte/s', timeout=30).group(1).decode('utf8'))
+        assert throughput > 50000 or throughput < 95000
+
+
+# Case 4: gatt notify throughput test for ESP32C2 26mhz xtal
+@pytest.mark.esp32c2
+@pytest.mark.wifi_two_dut
+@pytest.mark.xtal_26mhz
+@pytest.mark.parametrize(
+    'count, target, baud, app_path, config, erase_all', [
+        (2, 'esp32c2|esp32c2', '74880',
+         f'{os.path.join(os.path.dirname(__file__), "throughput_server")}|{os.path.join(os.path.dirname(__file__), "throughput_client")}',
+         'esp32c2_xtal26m_notify', 'y'),
+    ],
+    indirect=True,
+)
+def test_c2_26mhz_xtal_notify_throughput(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    server = dut[0]
+    client = dut[1]
+    client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+    server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    client.expect_exact('GATT client register, status 0', timeout=30)
+    server.expect_exact('GATT server register, status 0', timeout=30)
+    server.expect_exact('Advertising start successfully', timeout=30)
+    client.expect_exact('Scanning start successfully', timeout=30)
+    client.expect_exact('Device found ', timeout=30)
+    server.expect_exact('Service start, status 0', timeout=30)
+    server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30)
+    client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30)
+    client.expect_exact('MTU exchange, status 0, MTU 517', timeout=30)
+    server.expect_exact('MTU exchange, MTU 517', timeout=30)
+    client.expect_exact('Service search complete', timeout=30)
+    client.expect_exact('Notification register successfully', timeout=30)
+    server.expect_exact('Notification enable', timeout=30)
+    start_time = time.time()
+    while time.time() - start_time < 30:
+        throughput = int(client.expect(r'Notify Bit rate = (\d+) Byte/s', timeout=30).group(1).decode('utf8'))
+        assert throughput > 50000 or throughput < 95000
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_notify b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_notify
new file mode 100644
index 00000000000..0448a5d2a50
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_notify
@@ -0,0 +1,7 @@
+
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
+CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=y
+CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_write b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_write
new file mode 100644
index 00000000000..5874287ec33
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.esp32c2_xtal26m_write
@@ -0,0 +1,6 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
+CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=y
+CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=n
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.notify b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.notify
new file mode 100644
index 00000000000..db7b616deba
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.notify
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
+CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=y
+CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.write b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.write
new file mode 100644
index 00000000000..a47edbf1826
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_client/sdkconfig.ci.write
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
+CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=y
+CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=n
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_notify b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_notify
new file mode 100644
index 00000000000..0448a5d2a50
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_notify
@@ -0,0 +1,7 @@
+
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
+CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=y
+CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_write b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_write
new file mode 100644
index 00000000000..5874287ec33
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.esp32c2_xtal26m_write
@@ -0,0 +1,6 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
+CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=y
+CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=n
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.notify b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.notify
new file mode 100644
index 00000000000..db7b616deba
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.notify
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
+CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=y
+CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=n
diff --git a/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.write b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.write
new file mode 100644
index 00000000000..a47edbf1826
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/ble_throughput/throughput_server/sdkconfig.ci.write
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
+CONFIG_EXAMPLE_GATTC_WRITE_THROUGHPUT=y
+CONFIG_EXAMPLE_GATTS_NOTIFY_THROUGHPUT=n
diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.esp32c2_xtal26m
new file mode 100644
index 00000000000..e77ed1d26cd
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.esp32c2_xtal26m
@@ -0,0 +1,5 @@
+
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.name
new file mode 100644
index 00000000000..6d9fd6470c4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.ci.name
@@ -0,0 +1,2 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32c2 b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32c2
index 298663d0a39..9759e23400c 100644
--- a/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32c2
+++ b/examples/bluetooth/bluedroid/ble/gatt_client/sdkconfig.defaults.esp32c2
@@ -7,3 +7,7 @@ CONFIG_BT_ENABLED=y
 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
 # CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
 CONFIG_BT_LE_HCI_EVT_BUF_SIZE=257
+
+# XTAL Freq Config
+CONFIG_XTAL_FREQ_26=y
+CONFIG_XTAL_FREQ=26
diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.esp32c2_xtal26m
new file mode 100644
index 00000000000..6ab0a7ab9d4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.esp32c2_xtal26m
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.name
new file mode 100644
index 00000000000..d8e23a54e91
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/gatt_security_client/sdkconfig.ci.name
@@ -0,0 +1,3 @@
+
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.esp32c2_xtal26m
new file mode 100644
index 00000000000..6ab0a7ab9d4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.esp32c2_xtal26m
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.name
new file mode 100644
index 00000000000..d8e23a54e91
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/gatt_security_server/sdkconfig.ci.name
@@ -0,0 +1,3 @@
+
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.esp32c2_xtal26m
new file mode 100644
index 00000000000..6ab0a7ab9d4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.esp32c2_xtal26m
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.name
new file mode 100644
index 00000000000..d8e23a54e91
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.ci.name
@@ -0,0 +1,3 @@
+
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32c2 b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32c2
index 7e477f7373d..f13b703dc9f 100644
--- a/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32c2
+++ b/examples/bluetooth/bluedroid/ble/gatt_server/sdkconfig.defaults.esp32c2
@@ -6,3 +6,6 @@ CONFIG_BT_ENABLED=y
 CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
 # CONFIG_BT_LE_50_FEATURE_SUPPORT is not set
 CONFIG_BT_LE_HCI_EVT_BUF_SIZE=257
+# XTAL Freq Config
+CONFIG_XTAL_FREQ_26=y
+CONFIG_XTAL_FREQ=26
diff --git a/examples/bluetooth/bluedroid/ble/pytest_ble_test.py b/examples/bluetooth/bluedroid/ble/pytest_ble_test.py
new file mode 100644
index 00000000000..9de955b3001
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble/pytest_ble_test.py
@@ -0,0 +1,265 @@
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import os.path
+from typing import Tuple
+
+import pexpect
+import pytest
+from pytest_embedded_idf.dut import IdfDut
+
+
+# Case 1: gatt client and gatt server test
+@pytest.mark.esp32
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32c5
+@pytest.mark.esp32h2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c61
+@pytest.mark.wifi_two_dut
+@pytest.mark.parametrize(
+    'count, app_path, config, erase_all', [
+        (2,
+         f'{os.path.join(os.path.dirname(__file__), "gatt_server")}|{os.path.join(os.path.dirname(__file__), "gatt_client")}',
+         'name', 'y'),
+    ],
+    indirect=True,
+)
+def test_gatt_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    gatt_client = dut[1]
+    gatt_server = dut[0]
+    gatt_client_addr = gatt_client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+    gatt_server_addr = gatt_server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+    gatt_client.expect_exact('GATT client register, status 0', timeout=30)
+    gatt_server.expect_exact('GATT server register, status 0', timeout=30)
+    gatt_server.expect_exact('Advertising start successfully', timeout=30)
+    gatt_client.expect_exact('Scanning start successfully', timeout=30)
+    gatt_client.expect_exact(f'Connected, conn_id 0, remote {gatt_server_addr}', timeout=30)
+    gatt_server.expect_exact(f'Connected, conn_id 0, remote {gatt_client_addr}', timeout=30)
+    gatt_client.expect_exact('Connection params update, status 0', timeout=30)
+    gatt_server.expect_exact('Connection params update, status 0', timeout=30)
+    gatt_client.expect_exact('Service discover complete', timeout=30)
+    gatt_client.expect_exact('Service search complete', timeout=30)
+    gatt_client.expect_exact('MTU exchange, status 0, MTU 500', timeout=30)
+    gatt_server.expect_exact('MTU exchange, MTU 500', timeout=30)
+    gatt_server.expect_exact('Notification enable', timeout=30)
+    gatt_client.expect_exact('Notification received', timeout=30)
+    gatt_client_output = gatt_client.expect(pexpect.TIMEOUT, timeout=10)
+    gatt_server_output = gatt_server.expect(pexpect.TIMEOUT, timeout=10)
+    assert 'rst:' not in str(gatt_client_output) and 'boot:' not in str(gatt_client_output)
+    assert 'rst:' not in str(gatt_server_output) and 'boot:' not in str(gatt_server_output)
+    assert 'Disconnected' not in str(gatt_client_output)
+    assert 'Disconnected' not in str(gatt_server_output)
+
+
+# Case 2: gatt client and gatt server test for ESP32C2 26mhz xtal
+@pytest.mark.esp32c2
+@pytest.mark.wifi_two_dut
+@pytest.mark.xtal_26mhz
+@pytest.mark.parametrize(
+    'count, target, baud, app_path, config, erase_all', [
+        (2, 'esp32c2|esp32c2', '74880',
+         f'{os.path.join(os.path.dirname(__file__), "gatt_server")}|{os.path.join(os.path.dirname(__file__), "gatt_client")}',
+         'esp32c2_xtal26m', 'y'),
+    ],
+    indirect=True,
+)
+def test_c2_26mhz_xtal_gatt_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    gatt_client = dut[1]
+    gatt_server = dut[0]
+    gatt_client_addr = gatt_client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})').group(1).decode('utf8')
+    gatt_server_addr = gatt_server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})').group(1).decode('utf8')
+    gatt_client.expect_exact('GATT client register, status 0', timeout=30)
+    gatt_server.expect_exact('GATT server register, status 0', timeout=30)
+    gatt_server.expect_exact('Advertising start successfully', timeout=30)
+    gatt_client.expect_exact('Scanning start success', timeout=30)
+    gatt_client.expect_exact(f'Connected, conn_id 0, remote {gatt_server_addr}', timeout=30)
+    gatt_server.expect_exact(f'Connected, conn_id 0, remote {gatt_client_addr}', timeout=30)
+    gatt_client.expect_exact('Connection params update, status 0', timeout=30)
+    gatt_server.expect_exact('Connection params update, status 0', timeout=30)
+    gatt_client.expect_exact('Service discover complete', timeout=30)
+    gatt_client.expect_exact('Service search complete', timeout=30)
+    gatt_client.expect_exact('MTU exchange, status 0, MTU 500', timeout=30)
+    gatt_server.expect_exact('MTU exchange, MTU 500', timeout=30)
+    gatt_server.expect_exact('Notification enable', timeout=30)
+    gatt_client.expect_exact('Notification received', timeout=30)
+    gatt_client_output = gatt_client.expect(pexpect.TIMEOUT, timeout=10)
+    gatt_server_output = gatt_server.expect(pexpect.TIMEOUT, timeout=10)
+    assert 'rst:' not in str(gatt_client_output) and 'boot:' not in str(gatt_client_output)
+    assert 'rst:' not in str(gatt_server_output) and 'boot:' not in str(gatt_server_output)
+    assert 'Disconnected' not in str(gatt_client_output)
+    assert 'Disconnected' not in str(gatt_server_output)
+
+
+# Case 3: gatt security server and gatt security client test
+@pytest.mark.esp32
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32c5
+@pytest.mark.esp32h2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c61
+@pytest.mark.wifi_two_dut
+@pytest.mark.parametrize(
+    'count, app_path, config, erase_all', [
+        (2,
+         f'{os.path.join(os.path.dirname(__file__), "gatt_security_server")}|{os.path.join(os.path.dirname(__file__), "gatt_security_client")}',
+         'name', 'y'),
+    ],
+    indirect=True,
+)
+def test_gatt_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut], target: Tuple) -> None:
+    gatt_security_client = dut[1]
+    gatt_security_server = dut[0]
+    gatt_security_client_addr = gatt_security_client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    gatt_security_client.expect_exact('GATT client register, status 0', timeout=30)
+    gatt_security_server.expect_exact('GATT server register, status 0', timeout=30)
+    gatt_security_client.expect_exact('Local privacy config successfully', timeout=30)
+    gatt_security_server.expect_exact('Local privacy config successfully', timeout=30)
+    gatt_security_server.expect_exact('Advertising start successfully', timeout=30)
+    gatt_security_client.expect_exact('Scanning start successfully', timeout=30)
+    gatt_security_client.expect_exact('Device found BE', timeout=30)
+    # can not get rpa_address, so not check server address
+    gatt_security_client.expect_exact(f'Connected, conn_id 0, remote ', timeout=30)
+    if target == ('esp32', 'esp32'):
+        gatt_security_server.expect_exact(f'Connected, conn_id 0, remote', timeout=30)
+    else:
+        gatt_security_server.expect_exact(f'Connected, conn_id 0, remote {gatt_security_client_addr}', timeout=30)
+    gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_PID', timeout=30)
+    gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_LENC', timeout=30)
+    gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_PENC', timeout=30)
+    gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_LID', timeout=30)
+
+    gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_LENC', timeout=30)
+    gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_PENC', timeout=30)
+    gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_LID', timeout=30)
+    gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_PID', timeout=30)
+    if target == ('esp32', 'esp32'):
+        gatt_security_server.expect_exact(f'Authentication complete, addr_type 1, addr ', timeout=30)
+    else:
+        gatt_security_server.expect_exact(f'Authentication complete, addr_type 0, addr {gatt_security_client_addr}', timeout=30)
+    gatt_security_client.expect_exact(f'Authentication complete, addr_type 1, addr ', timeout=30)
+    gatt_security_server.expect_exact('Pairing successfully', timeout=30)
+    gatt_security_server.expect_exact('Bonded devices number 1', timeout=30)
+    gatt_security_client.expect_exact('Pairing successfully', timeout=30)
+    gatt_security_client.expect_exact('Service search complete', timeout=30)
+    gatt_security_client_output = gatt_security_client.expect(pexpect.TIMEOUT, timeout=10)
+    gatt_security_server_output = gatt_security_server.expect(pexpect.TIMEOUT, timeout=10)
+    assert 'rst:' not in str(gatt_security_client_output) and 'boot:' not in str(gatt_security_client_output)
+    assert 'rst:' not in str(gatt_security_server_output) and 'boot:' not in str(gatt_security_server_output)
+    assert 'Disconnected' not in str(gatt_security_client_output)
+    assert 'Disconnected' not in str(gatt_security_server_output)
+
+
+# Case 4: gatt security server and gatt security client test for ESP32C2 26mhz xtal
+@pytest.mark.esp32c2
+@pytest.mark.wifi_two_dut
+@pytest.mark.xtal_26mhz
+@pytest.mark.parametrize(
+    'count, target, baud, app_path, config, erase_all', [
+        (2, 'esp32c2|esp32c2', '74880',
+         f'{os.path.join(os.path.dirname(__file__), "gatt_security_server")}|{os.path.join(os.path.dirname(__file__), "gatt_security_client")}',
+         'esp32c2_xtal26m', 'y'),
+    ],
+    indirect=True,
+)
+def test_c2_26mhz_xtal_gatt_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    gatt_security_client = dut[1]
+    gatt_security_server = dut[0]
+    gatt_security_client_addr = gatt_security_client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    gatt_security_client.expect_exact('GATT client register, status 0', timeout=30)
+    gatt_security_server.expect_exact('GATT server register, status 0', timeout=30)
+    gatt_security_client.expect_exact('Local privacy config successfully', timeout=30)
+    gatt_security_server.expect_exact('Local privacy config successfully', timeout=30)
+    gatt_security_server.expect_exact('Advertising start successfully', timeout=30)
+    gatt_security_client.expect_exact('Scanning start successfully', timeout=30)
+    gatt_security_client.expect_exact('Device found BE', timeout=30)
+    # can not get rpa_address, so not check server address
+    gatt_security_client.expect_exact(f'Connected, conn_id 0, remote ', timeout=30)
+    gatt_security_server.expect_exact(f'Connected, conn_id 0, remote {gatt_security_client_addr}', timeout=30)
+    gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_PID', timeout=30)
+    gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_LENC', timeout=30)
+    gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_PENC', timeout=30)
+    gatt_security_client.expect_exact('Key exchanged, key_type ESP_LE_KEY_LID', timeout=30)
+
+    gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_LENC', timeout=30)
+    gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_PENC', timeout=30)
+    gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_LID', timeout=30)
+    gatt_security_server.expect_exact('Key exchanged, key_type ESP_LE_KEY_PID', timeout=30)
+    gatt_security_server.expect_exact(f'Authentication complete, addr_type 0, addr {gatt_security_client_addr}', timeout=30)
+    gatt_security_client.expect_exact(f'Authentication complete, addr_type 1, addr ', timeout=30)
+    gatt_security_server.expect_exact('Pairing successfully', timeout=30)
+    gatt_security_server.expect_exact('Bonded devices number 1', timeout=30)
+    gatt_security_client.expect_exact('Pairing successfully', timeout=30)
+    gatt_security_client.expect_exact('Service search complete', timeout=30)
+    gatt_security_client_output = gatt_security_client.expect(pexpect.TIMEOUT, timeout=10)
+    gatt_security_server_output = gatt_security_server.expect(pexpect.TIMEOUT, timeout=10)
+    assert 'rst:' not in str(gatt_security_client_output) and 'boot:' not in str(gatt_security_client_output)
+    assert 'rst:' not in str(gatt_security_server_output) and 'boot:' not in str(gatt_security_server_output)
+    assert 'Disconnected' not in str(gatt_security_client_output)
+    assert 'Disconnected' not in str(gatt_security_server_output)
+
+
+# Case 5: ble ibeacon test
+@pytest.mark.esp32
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32c5
+@pytest.mark.esp32h2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c61
+@pytest.mark.wifi_two_dut
+@pytest.mark.parametrize(
+    'count, app_path, config, erase_all', [
+        (2,
+         f'{os.path.join(os.path.dirname(__file__), "ble_ibeacon")}|{os.path.join(os.path.dirname(__file__), "ble_ibeacon")}',
+         'sender|receiver', 'y'),
+    ],
+    indirect=True,
+)
+def test_ble_ibeacon_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    ibeacon_sender = dut[0]
+    ibeacon_receiver = dut[1]
+
+    ibeacon_sender_addr = ibeacon_sender.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    ibeacon_sender.expect_exact('Advertising start successfully', timeout=30)
+    ibeacon_receiver.expect_exact('Scanning start successfully', timeout=30)
+    ibeacon_receiver.expect_exact('iBeacon Found', timeout=30)
+    ibeacon_receiver.expect_exact(f'IBEACON_DEMO: Device address: {ibeacon_sender_addr}', timeout=30)
+    ibeacon_receiver.expect_exact('IBEACON_DEMO: Proximity UUID:', timeout=30)
+    ibeacon_receiver.expect_exact('Major: 0x27b7 (10167)', timeout=30)
+    ibeacon_receiver.expect_exact('Minor: 0xf206 (61958)', timeout=30)
+    ibeacon_receiver.expect_exact('Measured power (RSSI at a 1m distance):', timeout=30)
+    ibeacon_receiver.expect_exact('RSSI of packet: ', timeout=30)
+
+
+# Case 5: ble ibeacon test for ESP32C2 26mhz xtal
+@pytest.mark.esp32c2
+@pytest.mark.wifi_two_dut
+@pytest.mark.xtal_26mhz
+@pytest.mark.parametrize(
+    'count, target, baud, app_path, config, erase_all', [
+        (2, 'esp32c2|esp32c2', '74880',
+         f'{os.path.join(os.path.dirname(__file__), "ble_ibeacon")}|{os.path.join(os.path.dirname(__file__), "ble_ibeacon")}',
+         'esp32c2_xtal26m_sender|esp32c2_xtal26m_receiver', 'y'),
+    ],
+    indirect=True,
+)
+def test_c2_26mhz_ble_ibeacon_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    ibeacon_sender = dut[0]
+    ibeacon_receiver = dut[1]
+
+    ibeacon_sender_addr = ibeacon_sender.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    ibeacon_sender.expect_exact('Advertising start successfully', timeout=30)
+    ibeacon_receiver.expect_exact('Scanning start successfully', timeout=30)
+    ibeacon_receiver.expect_exact('iBeacon Found', timeout=30)
+    ibeacon_receiver.expect_exact(f'IBEACON_DEMO: Device address: {ibeacon_sender_addr}', timeout=30)
+    ibeacon_receiver.expect_exact('IBEACON_DEMO: Proximity UUID:', timeout=30)
+    ibeacon_receiver.expect_exact('Major: 0x27b7 (10167)', timeout=30)
+    ibeacon_receiver.expect_exact('Minor: 0xf206 (61958)', timeout=30)
+    ibeacon_receiver.expect_exact('Measured power (RSSI at a 1m distance):', timeout=30)
+    ibeacon_receiver.expect_exact('RSSI of packet: ', timeout=30)
diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.esp32c2_xtal26m
new file mode 100644
index 00000000000..6ab0a7ab9d4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.esp32c2_xtal26m
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.name
new file mode 100644
index 00000000000..6d9fd6470c4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_client/sdkconfig.ci.name
@@ -0,0 +1,2 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.esp32c2_xtal26m
new file mode 100644
index 00000000000..6ab0a7ab9d4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.esp32c2_xtal26m
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.name
new file mode 100644
index 00000000000..6d9fd6470c4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/ble50_security_server/sdkconfig.ci.name
@@ -0,0 +1,2 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.esp32c2_xtal26m
new file mode 100644
index 00000000000..6ab0a7ab9d4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.esp32c2_xtal26m
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.name
new file mode 100644
index 00000000000..6d9fd6470c4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/periodic_adv/sdkconfig.ci.name
@@ -0,0 +1,2 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.esp32c2_xtal26m b/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.esp32c2_xtal26m
new file mode 100644
index 00000000000..6ab0a7ab9d4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.esp32c2_xtal26m
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_IDF_TARGET="esp32c2"
+CONFIG_XTAL_FREQ_26=y
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.name b/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.name
new file mode 100644
index 00000000000..6d9fd6470c4
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/periodic_sync/sdkconfig.ci.name
@@ -0,0 +1,2 @@
+CONFIG_EXAMPLE_CI_ID=1
+CONFIG_EXAMPLE_CI_PIPELINE_ID=${CI_PIPELINE_ID}
diff --git a/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py b/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py
new file mode 100644
index 00000000000..b5b02e87f80
--- /dev/null
+++ b/examples/bluetooth/bluedroid/ble_50/pytest_ble50_test.py
@@ -0,0 +1,143 @@
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import os.path
+from typing import Tuple
+
+import pytest
+from pytest_embedded_idf.dut import IdfDut
+
+
+# Case 1: ble50 security client and ble50 security server test
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32c5
+@pytest.mark.esp32h2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c61
+@pytest.mark.wifi_two_dut
+@pytest.mark.parametrize(
+    'count, app_path, config, erase_all', [
+        (2,
+         f'{os.path.join(os.path.dirname(__file__), "ble50_security_server")}|{os.path.join(os.path.dirname(__file__), "ble50_security_client")}',
+         'name', 'y'),
+    ],
+    indirect=True,
+)
+def test_ble50_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    server = dut[0]
+    client = dut[1]
+    client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+    server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    server.expect_exact('Extended advertising params set, status 0', timeout=30)
+    server.expect_exact('Extended advertising data set, status 0', timeout=30)
+    server.expect_exact('Extended advertising start, status 0', timeout=30)
+    client.expect_exact('Extended scanning start successfully', timeout=30)
+    client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30)
+    server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30)
+    server.expect_exact('Pairing successfully', timeout=30)
+    client.expect_exact('Pairing successfully', timeout=30)
+    server.expect_exact('Bonded devices number 1', timeout=30)
+    server.expect_exact('Characteristic write', timeout=30)
+    client.expect_exact('Service discover complete', timeout=30)
+    client.expect_exact('Service search complete', timeout=30)
+    client.expect_exact('MTU exchange, status 0', timeout=30)
+    client.expect_exact('Descriptor write successfully', timeout=30)
+
+
+# Case 2: ble50 security client and ble50 security server test for ESP32C2 26mhz xtal
+@pytest.mark.esp32c2
+@pytest.mark.wifi_two_dut
+@pytest.mark.xtal_26mhz
+@pytest.mark.parametrize(
+    'count, target, baud, app_path, config, erase_all', [
+        (2, 'esp32c2|esp32c2', '74880',
+         f'{os.path.join(os.path.dirname(__file__), "ble50_security_server")}|{os.path.join(os.path.dirname(__file__), "ble50_security_client")}',
+         'esp32c2_xtal26m', 'y'),
+    ],
+    indirect=True,
+)
+def test_c2_26mhz_xtal_ble50_security_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    server = dut[0]
+    client = dut[1]
+    client_addr = client.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+    server_addr = server.expect(r'Bluetooth MAC: (([0-9a-fA-F]{2}:){5}[0-9a-fA-F]{2})', timeout=30).group(1).decode('utf8')
+
+    server.expect_exact('Extended advertising params set, status 0', timeout=30)
+    server.expect_exact('Extended advertising data set, status 0', timeout=30)
+    server.expect_exact('Extended advertising start, status 0', timeout=30)
+    client.expect_exact('Extended scanning start successfully', timeout=30)
+    client.expect_exact(f'Connected, conn_id 0, remote {server_addr}', timeout=30)
+    server.expect_exact(f'Connected, conn_id 0, remote {client_addr}', timeout=30)
+    server.expect_exact('Pairing successfully', timeout=30)
+    client.expect_exact('Pairing successfully', timeout=30)
+    server.expect_exact('Bonded devices number 1', timeout=30)
+    server.expect_exact('Characteristic write', timeout=30)
+    client.expect_exact('Service discover complete', timeout=30)
+    client.expect_exact('Service search complete', timeout=30)
+    client.expect_exact('MTU exchange, status 0', timeout=30)
+    client.expect_exact('Descriptor write successfully', timeout=30)
+
+
+# Case 3: period_adv and period_sync test
+@pytest.mark.esp32c3
+@pytest.mark.esp32c6
+@pytest.mark.esp32c5
+@pytest.mark.esp32h2
+@pytest.mark.esp32s3
+@pytest.mark.esp32c61
+@pytest.mark.wifi_two_dut
+@pytest.mark.parametrize(
+    'count, app_path, config, erase_all', [
+        (2,
+         f'{os.path.join(os.path.dirname(__file__), "periodic_adv")}|{os.path.join(os.path.dirname(__file__), "periodic_sync")}',
+         'name', 'y'),
+    ],
+    indirect=True,
+)
+def test_period_adv_sync_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    adv_dut = dut[0]
+    sync_dut = dut[1]
+
+    adv_dut.expect_exact('Extended advertising params set, status 0', timeout=30)
+    adv_dut.expect_exact('Extended advertising random address set, status 0', timeout=30)
+    adv_dut.expect_exact('Extended advertising data set, status 0', timeout=30)
+    adv_dut.expect_exact('Extended advertising start, status 0', timeout=30)
+    adv_dut.expect_exact('Periodic advertising params set, status 0', timeout=30)
+    adv_dut.expect_exact('Periodic advertising data set, status 0', timeout=30)
+    adv_dut.expect_exact('Periodic advertising start, status 0', timeout=30)
+    sync_dut.expect_exact('Extended scanning params set, status 0', timeout=30)
+    sync_dut.expect_exact('Extended scanning start, status 0', timeout=30)
+    sync_dut.expect_exact(f'Create sync with the peer device BE', timeout=30)
+    sync_dut.expect_exact('Periodic advertising sync establish, status 0', timeout=30)
+    sync_dut.expect_exact('Periodic adv report, sync handle ', timeout=30)
+
+
+# Case 4: period_adv and period_sync test for ESP32C2 26mhz xtal
+@pytest.mark.esp32c2
+@pytest.mark.wifi_two_dut
+@pytest.mark.xtal_26mhz
+@pytest.mark.parametrize(
+    'count, target, baud, app_path, config, erase_all', [
+        (2, 'esp32c2|esp32c2', '74880',
+         f'{os.path.join(os.path.dirname(__file__), "periodic_adv")}|{os.path.join(os.path.dirname(__file__), "periodic_sync")}',
+         'esp32c2_xtal26m', 'y'),
+    ],
+    indirect=True,
+)
+def test_c2_26mhz_xtal_period_adv_sync_func(app_path: str, dut: Tuple[IdfDut, IdfDut]) -> None:
+    adv_dut = dut[0]
+    sync_dut = dut[1]
+
+    adv_dut.expect_exact('Extended advertising params set, status 0', timeout=30)
+    adv_dut.expect_exact('Extended advertising random address set, status 0', timeout=30)
+    adv_dut.expect_exact('Extended advertising data set, status 0', timeout=30)
+    adv_dut.expect_exact('Extended advertising start, status 0', timeout=30)
+    adv_dut.expect_exact('Periodic advertising params set, status 0', timeout=30)
+    adv_dut.expect_exact('Periodic advertising data set, status 0', timeout=30)
+    adv_dut.expect_exact('Periodic advertising start, status 0', timeout=30)
+    sync_dut.expect_exact('Extended scanning params set, status 0', timeout=30)
+    sync_dut.expect_exact('Extended scanning start, status 0', timeout=30)
+    sync_dut.expect_exact(f'Create sync with the peer device BE', timeout=30)
+    sync_dut.expect_exact('Periodic advertising sync establish, status 0', timeout=30)
+    sync_dut.expect_exact('Periodic adv report, sync handle ', timeout=30)
diff --git a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c
index 05b75588d46..5c38abda409 100644
--- a/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c
+++ b/examples/bluetooth/bluedroid/classic_bt/hfp_ag/main/bt_app_hf.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -32,7 +32,7 @@ const char *c_hf_evt_str[] = {
     "AUDIO_STATE_EVT",                   /*!< AUDIO CONNECTION STATE CONTROL */
     "VR_STATE_CHANGE_EVT",               /*!< VOICE RECOGNITION CHANGE */
     "VOLUME_CONTROL_EVT",                /*!< AUDIO VOLUME CONTROL */
-    "UNKNOW_AT_CMD",                     /*!< UNKNOW AT COMMAND RECIEVED */
+    "UNKNOW_AT_CMD",                     /*!< UNKNOWN AT COMMAND RECEIVED */
     "IND_UPDATE",                        /*!< INDICATION UPDATE */
     "CIND_RESPONSE_EVT",                 /*!< CALL & DEVICE INDICATION */
     "COPS_RESPONSE_EVT",                 /*!< CURRENT OPERATOR EVENT */
@@ -355,7 +355,7 @@ void bt_app_hf_cb(esp_hf_cb_event_t event, esp_hf_cb_param_t *param)
 
         case ESP_HF_IND_UPDATE_EVT:
         {
-            ESP_LOGI(BT_HF_TAG, "--UPDATE INDCATOR!");
+            ESP_LOGI(BT_HF_TAG, "--UPDATE INDICATOR!");
             esp_hf_call_status_t call_state = 1;
             esp_hf_call_setup_status_t call_setup_state = 2;
             esp_hf_network_state_t ntk_state = 1;
@@ -460,6 +460,7 @@ void bt_app_hf_cb(esp_hf_cb_event_t event, esp_hf_cb_param_t *param)
                 if (param->out_call.type == ESP_HF_DIAL_NUM) {
                     // dia_num
                     ESP_LOGI(BT_HF_TAG, "--Dial number \"%s\".", param->out_call.num_or_loc);
+                    esp_hf_ag_cmee_send(param->out_call.remote_addr, ESP_HF_AT_RESPONSE_CODE_OK, ESP_HF_CME_AG_FAILURE);
                     esp_hf_ag_out_call(param->out_call.remote_addr,1,0,1,0,param->out_call.num_or_loc,0);
                 } else if (param->out_call.type == ESP_HF_DIAL_MEM) {
                     // dia_mem
diff --git a/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md b/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md
index e1be95e4ac3..dbc9e9134c8 100644
--- a/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md
+++ b/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh AliGenie Example
 =============================
diff --git a/examples/bluetooth/esp_ble_mesh/aligenie_demo/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/aligenie_demo/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..19b9555dce5
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/aligenie_demo/sdkconfig.defaults.esp32c61
@@ -0,0 +1,17 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
+
+#
+# light driver config
+#
+CONFIG_LIGHT_GPIO_RED=4
+CONFIG_LIGHT_GPIO_GREEN=5
+CONFIG_LIGHT_GPIO_BLUE=6
+CONFIG_LIGHT_GPIO_COLD=7
+CONFIG_LIGHT_GPIO_WARM=10
+# end of light driver config
diff --git a/examples/bluetooth/esp_ble_mesh/common_components/example_init/ble_mesh_example_init.c b/examples/bluetooth/esp_ble_mesh/common_components/example_init/ble_mesh_example_init.c
index 81600912b47..8a4674a8716 100644
--- a/examples/bluetooth/esp_ble_mesh/common_components/example_init/ble_mesh_example_init.c
+++ b/examples/bluetooth/esp_ble_mesh/common_components/example_init/ble_mesh_example_init.c
@@ -1,6 +1,6 @@
 /*
  * SPDX-FileCopyrightText: 2017 Intel Corporation
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -155,6 +155,22 @@ esp_err_t bluetooth_init(void)
     /* XXX Need to have template for store */
     ble_store_config_init();
 
+#if CONFIG_BLE_MESH_USE_BLE_50
+    /**
+     * On the NimBLE host, once any of the discovery,
+     * advertising, or connection is enabled, it is
+     * no longer possible to register GATT services.
+     *
+     * Once the NimBLE host is started, it will call
+     * the registered sync callback. Since it is
+     * uncertain what the user will do in the sync
+     * callback, GATT services should be registered
+     * before starting the NimBLE.
+     */
+    extern void bt_mesh_gatts_svcs_add(void);
+    bt_mesh_gatts_svcs_add();
+#endif /* CONFIG_BLE_MESH_USE_BLE_50 */
+
     nimble_port_freertos_init(mesh_host_task);
 
     xSemaphoreTake(mesh_sem, portMAX_DELAY);
diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md b/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md
index 8b68cddd7f1..5d5550dd972 100644
--- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md
+++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 # Directed Forwarding
 
diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/main/board.h b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/main/board.h
index 28890cdf2b8..3f7a9b37870 100644
--- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/main/board.h
@@ -35,6 +35,8 @@ extern "C" {
 #define LED_B GPIO_NUM_47
 #elif defined(CONFIG_BLE_MESH_ESP32C6_DEV)
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_client/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/main/board.h b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/main/board.h
index 18d88b2a632..975543b9f9f 100644
--- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/main/board.h
@@ -34,6 +34,8 @@ extern "C" {
 #define LED_B GPIO_NUM_47
 #elif defined(CONFIG_BLE_MESH_ESP32C6_DEV)
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/df_server/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md
index b5e495bb529..373a1bf8249 100644
--- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md
+++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Fast Provisioning Client example
 ========================
diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md
index 6b4b2d8027a..76a918c3c72 100644
--- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md
+++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Fast Provisioning Server example
 ========================
diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/main/board.h b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/main/board.h
index 7bb44d1d9c0..a58820dd613 100644
--- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/main/board.h
@@ -36,6 +36,10 @@ extern "C" {
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
 #define LED_B GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define LED_R GPIO_NUM_8
+#define LED_G GPIO_NUM_8
+#define LED_B GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md
index e3f313d9baf..b5f569475dc 100644
--- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md
+++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Client Model Demo
 ========================
diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/main/board.h b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/main/board.h
index 6d7eb19bf31..ee604c5cf5e 100644
--- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/main/board.h
@@ -37,6 +37,10 @@ extern "C" {
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
 #define LED_B GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define LED_R GPIO_NUM_8
+#define LED_G GPIO_NUM_8
+#define LED_B GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md
index 4e9f4de3892..022003ec161 100644
--- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md
+++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Node demo
 ==========================
diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/main/board.h b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/main/board.h
index 918904c4d17..2be1b508af7 100644
--- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/main/board.h
@@ -36,6 +36,10 @@ extern "C" {
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
 #define LED_B GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define LED_R GPIO_NUM_8
+#define LED_G GPIO_NUM_8
+#define LED_B GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/README.md b/examples/bluetooth/esp_ble_mesh/provisioner/README.md
index 4411669d5f7..a9da37420e4 100644
--- a/examples/bluetooth/esp_ble_mesh/provisioner/README.md
+++ b/examples/bluetooth/esp_ble_mesh/provisioner/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Provisioner demo
 ================================
diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/provisioner/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md b/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md
index 6de56d73ff6..b802d03e39a 100644
--- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 # Remote Provisioning
 
 (See the README.md file in the upper level 'examples' directory for more information about examples.)
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/board.h b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/board.h
index e5466c5dca8..3b04417b5b0 100644
--- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/main/board.h
@@ -30,6 +30,8 @@ extern "C" {
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_47
 #elif defined(CONFIG_BLE_MESH_ESP32C6_DEV)
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32C5_DEV)
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_client/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/main/board.h b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/main/board.h
index e5466c5dca8..3b04417b5b0 100644
--- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/main/board.h
@@ -30,6 +30,8 @@ extern "C" {
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_47
 #elif defined(CONFIG_BLE_MESH_ESP32C6_DEV)
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32C5_DEV)
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/rpr_server/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/main/board.h b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/main/board.h
index e5466c5dca8..3b04417b5b0 100644
--- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/main/board.h
@@ -30,6 +30,8 @@ extern "C" {
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_47
 #elif defined(CONFIG_BLE_MESH_ESP32C6_DEV)
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define BLE_MESH_LED_STRIP_IO GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32C5_DEV)
diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/unprov_dev/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md
index c763b6b43ab..f14a98364ad 100644
--- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md
+++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Sensor Client Example
 ==================================
diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md
index 2088b00e4e8..3257ab5c778 100644
--- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md
+++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Sensor Server Example
 ==================================
diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/main/board.h b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/main/board.h
index 918904c4d17..2be1b508af7 100644
--- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/main/board.h
@@ -36,6 +36,10 @@ extern "C" {
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
 #define LED_B GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define LED_R GPIO_NUM_8
+#define LED_G GPIO_NUM_8
+#define LED_B GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md
index 1a68ab9e5d1..3cc724b88b3 100644
--- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md
+++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Vendor Client Example
 ==================================
diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md
index 9bc9df87a24..7a3849086c6 100644
--- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md
+++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- |
 
 ESP BLE Mesh Vendor Server Example
 ==================================
diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/main/Kconfig.projbuild
index cb2988a8c87..3402e93a56b 100644
--- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/main/Kconfig.projbuild
@@ -38,6 +38,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/main/board.h b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/main/board.h
index 918904c4d17..2be1b508af7 100644
--- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/main/board.h
@@ -36,6 +36,10 @@ extern "C" {
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
 #define LED_B GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define LED_R GPIO_NUM_8
+#define LED_G GPIO_NUM_8
+#define LED_B GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32H2_DEV)
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md b/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md
index e86e1db9547..a08bc1d2876 100644
--- a/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md
+++ b/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- |
 
 ESP-BLE-MESH and Wi-Fi Coexistence Example
 =============================================
diff --git a/examples/bluetooth/esp_ble_mesh/wifi_coexist/main/Kconfig.projbuild b/examples/bluetooth/esp_ble_mesh/wifi_coexist/main/Kconfig.projbuild
index 9344866edb3..c86c9aebb41 100644
--- a/examples/bluetooth/esp_ble_mesh/wifi_coexist/main/Kconfig.projbuild
+++ b/examples/bluetooth/esp_ble_mesh/wifi_coexist/main/Kconfig.projbuild
@@ -33,6 +33,10 @@ menu "Example Configuration"
             bool "ESP32C5-DevKitC"
             depends on IDF_TARGET_ESP32C5
 
+        config BLE_MESH_ESP32C61_DEV
+            bool "ESP32C61-DevKitC"
+            depends on IDF_TARGET_ESP32C61
+
     endchoice
 
 endmenu
diff --git a/examples/bluetooth/esp_ble_mesh/wifi_coexist/main/board.h b/examples/bluetooth/esp_ble_mesh/wifi_coexist/main/board.h
index 1bbda4d6beb..7eca5b0f11f 100644
--- a/examples/bluetooth/esp_ble_mesh/wifi_coexist/main/board.h
+++ b/examples/bluetooth/esp_ble_mesh/wifi_coexist/main/board.h
@@ -32,6 +32,10 @@
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
 #define LED_B GPIO_NUM_8
+#elif defined(CONFIG_BLE_MESH_ESP32C61_DEV)
+#define LED_R GPIO_NUM_8
+#define LED_G GPIO_NUM_8
+#define LED_B GPIO_NUM_8
 #elif defined(CONFIG_BLE_MESH_ESP32C5_DEV)
 #define LED_R GPIO_NUM_8
 #define LED_G GPIO_NUM_8
diff --git a/examples/bluetooth/esp_ble_mesh/wifi_coexist/sdkconfig.defaults.esp32c61 b/examples/bluetooth/esp_ble_mesh/wifi_coexist/sdkconfig.defaults.esp32c61
new file mode 100644
index 00000000000..a96a75c5466
--- /dev/null
+++ b/examples/bluetooth/esp_ble_mesh/wifi_coexist/sdkconfig.defaults.esp32c61
@@ -0,0 +1,7 @@
+# Override some defaults so BT stack is enabled
+# by default in this example
+CONFIG_IDF_TARGET="esp32c61"
+CONFIG_BT_LE_SCAN_DUPL_TYPE_DATA_DEVICE=y
+CONFIG_BT_BLE_42_FEATURES_SUPPORTED=y
+CONFIG_BT_BLE_50_FEATURES_SUPPORTED=n
+CONFIG_BT_LE_50_FEATURE_SUPPORT=n
diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md
index 6c32318b9fe..8f3339a66ec 100644
--- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md
+++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_cent/README.md
@@ -5,6 +5,8 @@
 
 (See the README.md file in the upper level 'examples' directory for more information about examples.)
 
+**This example relies on the BLE controller. Currently, the ESP32/ESP32-C3/ESP32-S3/ESP32-C2 does not support the relevant vendor HCI, so please use the chip modules listed under Supported Targets.**
+
 Please check the [tutorial](tutorial/Ble_Multiple_Connections_Central_Example_Walkthrough.md) for more information about this example.
 
 ## How to Use Example
diff --git a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md
index 8035d1b6419..95d7358bbdd 100644
--- a/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md
+++ b/examples/bluetooth/nimble/ble_multi_conn/ble_multi_conn_prph/README.md
@@ -5,6 +5,8 @@
 
 (See the README.md file in the upper level 'examples' directory for more information about examples.)
 
+**This example relies on the BLE controller. Currently, the ESP32/ESP32-C3/ESP32-S3/ESP32-C2 does not support the relevant vendor HCI, so please use the chip modules listed under Supported Targets.**
+
 Please check the [tutorial](tutorial/Ble_Multiple_Connections_Peripheral_Example_Walkthrough.md) for more information about this example.
 
 ## How to Use Example
diff --git a/examples/common_components/protocol_examples_common/Kconfig.projbuild b/examples/common_components/protocol_examples_common/Kconfig.projbuild
index 800f136a09c..a890bfbe07f 100644
--- a/examples/common_components/protocol_examples_common/Kconfig.projbuild
+++ b/examples/common_components/protocol_examples_common/Kconfig.projbuild
@@ -183,6 +183,15 @@ menu "Example Connection Configuration"
                 help
                     Select the Ethernet PHY device to use in the example.
 
+                config EXAMPLE_ETH_PHY_GENERIC
+                    bool "Generic 802.3 PHY"
+                    help
+                        Any Ethernet PHY chip compliant with IEEE 802.3 can be used. However, while
+                        basic functionality should always work, some specific features might be limited,
+                        even if the PHY meets IEEE 802.3 standard. A typical example is loopback
+                        functionality, where certain PHYs may require setting a specific speed mode to
+                        operate correctly.
+
                 config EXAMPLE_ETH_PHY_IP101
                     bool "IP101"
                     help
diff --git a/examples/common_components/protocol_examples_common/eth_connect.c b/examples/common_components/protocol_examples_common/eth_connect.c
index 8e89dbe28eb..86e856527c2 100644
--- a/examples/common_components/protocol_examples_common/eth_connect.c
+++ b/examples/common_components/protocol_examples_common/eth_connect.c
@@ -103,7 +103,9 @@ static esp_netif_t *eth_start(void)
     esp32_emac_config.smi_gpio.mdc_num = CONFIG_EXAMPLE_ETH_MDC_GPIO;
     esp32_emac_config.smi_gpio.mdio_num = CONFIG_EXAMPLE_ETH_MDIO_GPIO;
     s_mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config);
-#if CONFIG_EXAMPLE_ETH_PHY_IP101
+#if CONFIG_EXAMPLE_ETH_PHY_GENERIC
+    s_phy = esp_eth_phy_new_generic(&phy_config);
+#elif CONFIG_EXAMPLE_ETH_PHY_IP101
     s_phy = esp_eth_phy_new_ip101(&phy_config);
 #elif CONFIG_EXAMPLE_ETH_PHY_RTL8201
     s_phy = esp_eth_phy_new_rtl8201(&phy_config);
diff --git a/examples/common_components/protocol_examples_common/stdin_out.c b/examples/common_components/protocol_examples_common/stdin_out.c
index 9f3a5163f30..57c61fb8f8f 100644
--- a/examples/common_components/protocol_examples_common/stdin_out.c
+++ b/examples/common_components/protocol_examples_common/stdin_out.c
@@ -15,8 +15,7 @@
 
 esp_err_t example_configure_stdin_stdout(void)
 {
-    static bool configured = false;
-    if (configured) {
+    if (uart_is_driver_installed((uart_port_t)CONFIG_ESP_CONSOLE_UART_NUM)) {
       return ESP_OK;
     }
     // Initialize VFS & UART so we can use std::cout/cin
@@ -29,6 +28,5 @@ esp_err_t example_configure_stdin_stdout(void)
     uart_vfs_dev_port_set_rx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CR);
     /* Move the caret to the beginning of the next line on '\n' */
     uart_vfs_dev_port_set_tx_line_endings(CONFIG_ESP_CONSOLE_UART_NUM, ESP_LINE_ENDINGS_CRLF);
-    configured = true;
     return ESP_OK;
 }
diff --git a/examples/custom_bootloader/bootloader_extra_dir/CMakeLists.txt b/examples/custom_bootloader/bootloader_extra_dir/CMakeLists.txt
new file mode 100644
index 00000000000..77e21c4ce6e
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/CMakeLists.txt
@@ -0,0 +1,11 @@
+# For more information about build system see
+# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html
+# The following five lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+idf_build_set_property(BOOTLOADER_EXTRA_COMPONENT_DIRS "${CMAKE_CURRENT_LIST_DIR}/extra_bootloader_components/" APPEND)
+
+project(main)
diff --git a/examples/custom_bootloader/bootloader_extra_dir/README.md b/examples/custom_bootloader/bootloader_extra_dir/README.md
new file mode 100644
index 00000000000..9d0b0021ace
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/README.md
@@ -0,0 +1,56 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+
+# Bootloader extra component
+
+(See the README.md file in the upper level for more information about bootloader examples.)
+
+The purpose of this example is to show how to add a custom directory that contains a component to the bootloader build.
+
+Registering extra components for the bootloader can be done thanks to the IDF property `BOOTLOADER_EXTRA_COMPONENT_DIRS`. It can either refer to a directory that contains several components, either refer to a single component.
+
+## Usage of this example:
+
+Simply compile it:
+```
+idf.py build
+```
+
+Then flash it and open the monitor with the following command:
+```
+idf.py flash monitor
+```
+
+If everything went well, the bootloader should output the following message:
+```
+I (60) EXTRA: This function is called from an extra component
+```
+
+And finally the application will start and show the message:
+```
+User application is loaded and running.
+```
+
+## Organization of this example
+
+This project contains a `main` directory that represents an application. It also has a `bootloader_components` directory that contains a component that will be compiled and linked with the bootloader. This `bootloader_components` can contain several components, each of them would be in a different directory.
+
+The directory `extra_bootloader_components/extra_component/` contains a component that is meant to be included in the bootloader build. To do so, the CMake property `BOOTLOADER_EXTRA_COMPONENT_DIRS` is set from the `CMakeLists.txt` file.
+
+Below is a short explanation of files in the project folder.
+
+```
+├── CMakeLists.txt             Defines the `BOOTLOADER_EXTRA_COMPONENT_DIRS` property
+├── main
+│   ├── CMakeLists.txt
+│   └── main.c                 User application
+├── bootloader_components
+│   └── my_boot_hooks
+│       ├── CMakeLists.txt
+│       └── hooks.c            Implementation of the hooks to execute on boot
+├── extra_bootloader_components
+│   └── extra_component
+│       ├── CMakeLists.txt
+│       └── extra_component.c  Implementation of the extra component
+└── README.md                  This is the file you are currently reading
+```
diff --git a/examples/custom_bootloader/bootloader_extra_dir/bootloader_components/my_boot_hooks/CMakeLists.txt b/examples/custom_bootloader/bootloader_extra_dir/bootloader_components/my_boot_hooks/CMakeLists.txt
new file mode 100644
index 00000000000..6b620571a47
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/bootloader_components/my_boot_hooks/CMakeLists.txt
@@ -0,0 +1,9 @@
+idf_component_register(SRCS "hooks.c"
+                       REQUIRES extra_component)
+
+# We need to force GCC to integrate this static library into the
+# bootloader link. Indeed, by default, as the hooks in the bootloader are weak,
+# the linker would just ignore the symbols in the extra. (i.e. not strictly
+# required)
+# To do so, we need to define the symbol (function) `bootloader_hooks_include`
+# within hooks.c source file.
diff --git a/examples/custom_bootloader/bootloader_extra_dir/bootloader_components/my_boot_hooks/hooks.c b/examples/custom_bootloader/bootloader_extra_dir/bootloader_components/my_boot_hooks/hooks.c
new file mode 100644
index 00000000000..e72e4570a9d
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/bootloader_components/my_boot_hooks/hooks.c
@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+extern void bootloader_extra_dir_function(void);
+
+/* Function used to tell the linker to include this file
+ * with all its symbols.
+ */
+void bootloader_hooks_include(void){
+}
+
+void bootloader_after_init(void) {
+    bootloader_extra_dir_function();
+}
diff --git a/examples/custom_bootloader/bootloader_extra_dir/extra_bootloader_components/extra_component/CMakeLists.txt b/examples/custom_bootloader/bootloader_extra_dir/extra_bootloader_components/extra_component/CMakeLists.txt
new file mode 100644
index 00000000000..ac58fa9c07e
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/extra_bootloader_components/extra_component/CMakeLists.txt
@@ -0,0 +1 @@
+idf_component_register(SRCS "extra_component.c")
diff --git a/examples/custom_bootloader/bootloader_extra_dir/extra_bootloader_components/extra_component/extra_component.c b/examples/custom_bootloader/bootloader_extra_dir/extra_bootloader_components/extra_component/extra_component.c
new file mode 100644
index 00000000000..78b558c5e34
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/extra_bootloader_components/extra_component/extra_component.c
@@ -0,0 +1,11 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include "esp_log.h"
+
+void bootloader_extra_dir_function(void)
+{
+    ESP_LOGI("EXTRA", "This function is called from an extra component");
+}
diff --git a/examples/custom_bootloader/bootloader_extra_dir/main/CMakeLists.txt b/examples/custom_bootloader/bootloader_extra_dir/main/CMakeLists.txt
new file mode 100644
index 00000000000..db0df989711
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "bootloader_hooks_example_main.c"
+                    INCLUDE_DIRS ".")
diff --git a/examples/custom_bootloader/bootloader_extra_dir/main/bootloader_hooks_example_main.c b/examples/custom_bootloader/bootloader_extra_dir/main/bootloader_hooks_example_main.c
new file mode 100644
index 00000000000..293528a6111
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/main/bootloader_hooks_example_main.c
@@ -0,0 +1,11 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include <stdio.h>
+
+void app_main(void)
+{
+    printf("User application is loaded and running.\n");
+}
diff --git a/examples/custom_bootloader/bootloader_extra_dir/pytest_bootloader_extra_dir.py b/examples/custom_bootloader/bootloader_extra_dir/pytest_bootloader_extra_dir.py
new file mode 100644
index 00000000000..217ce76f8e8
--- /dev/null
+++ b/examples/custom_bootloader/bootloader_extra_dir/pytest_bootloader_extra_dir.py
@@ -0,0 +1,10 @@
+# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.supported_targets
+@pytest.mark.generic
+def test_custom_bootloader_extra_component(dut: Dut) -> None:
+    dut.expect_exact('This function is called from an extra component')
diff --git a/examples/ethernet/.build-test-rules.yml b/examples/ethernet/.build-test-rules.yml
index 965eb6b8208..783ab909e17 100644
--- a/examples/ethernet/.build-test-rules.yml
+++ b/examples/ethernet/.build-test-rules.yml
@@ -31,3 +31,9 @@ examples/ethernet/iperf:
     - cmd_system
     - ethernet_init
     - protocol_examples_common
+examples/ethernet/ptp:
+  enable:
+    - if: SOC_EMAC_IEEE1588V2_SUPPORTED == 1
+  depends_components:
+    - esp_eth
+    - esp_netif
diff --git a/examples/ethernet/README.md b/examples/ethernet/README.md
index 1b059a1caf8..abf7b2d176e 100644
--- a/examples/ethernet/README.md
+++ b/examples/ethernet/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
 
 # Ethernet Examples
 
diff --git a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild
index caca0c4211a..325908b5753 100644
--- a/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild
+++ b/examples/ethernet/basic/components/ethernet_init/Kconfig.projbuild
@@ -17,6 +17,15 @@ menu "Example Ethernet Configuration"
             help
                 Select the Ethernet PHY device to use in the example.
 
+            config EXAMPLE_ETH_PHY_GENERIC
+                bool "Generic 802.3 PHY"
+                help
+                    Any Ethernet PHY chip compliant with IEEE 802.3 can be used. However, while
+                    basic functionality should always work, some specific features might be limited,
+                    even if the PHY meets IEEE 802.3 standard. A typical example is loopback
+                    functionality, where certain PHYs may require setting a specific speed mode to
+                    operate correctly.
+
             config EXAMPLE_ETH_PHY_IP101
                 bool "IP101"
                 help
diff --git a/examples/ethernet/basic/components/ethernet_init/ethernet_init.c b/examples/ethernet/basic/components/ethernet_init/ethernet_init.c
index b34304e4a37..831e8cb2079 100644
--- a/examples/ethernet/basic/components/ethernet_init/ethernet_init.c
+++ b/examples/ethernet/basic/components/ethernet_init/ethernet_init.c
@@ -83,7 +83,9 @@ static esp_eth_handle_t eth_init_internal(esp_eth_mac_t **mac_out, esp_eth_phy_t
     // Create new ESP32 Ethernet MAC instance
     esp_eth_mac_t *mac = esp_eth_mac_new_esp32(&esp32_emac_config, &mac_config);
     // Create new PHY instance based on board configuration
-#if CONFIG_EXAMPLE_ETH_PHY_IP101
+#if CONFIG_EXAMPLE_ETH_PHY_GENERIC
+    esp_eth_phy_t *phy = esp_eth_phy_new_generic(&phy_config);
+#elif CONFIG_EXAMPLE_ETH_PHY_IP101
     esp_eth_phy_t *phy = esp_eth_phy_new_ip101(&phy_config);
 #elif CONFIG_EXAMPLE_ETH_PHY_RTL8201
     esp_eth_phy_t *phy = esp_eth_phy_new_rtl8201(&phy_config);
diff --git a/examples/ethernet/basic/pytest_eth_basic.py b/examples/ethernet/basic/pytest_eth_basic.py
index 44ce6db4af2..74c5a2ac63f 100644
--- a/examples/ethernet/basic/pytest_eth_basic.py
+++ b/examples/ethernet/basic/pytest_eth_basic.py
@@ -10,6 +10,7 @@
 @pytest.mark.esp32
 @pytest.mark.parametrize('config', [
     pytest.param('default_ip101', marks=[pytest.mark.ethernet_router]),
+    pytest.param('default_generic', marks=[pytest.mark.ethernet_router]),
     pytest.param('default_dm9051', marks=[pytest.mark.eth_dm9051]),
 ], indirect=True)
 def test_esp_eth_basic(
diff --git a/examples/ethernet/basic/sdkconfig.ci.default_generic b/examples/ethernet/basic/sdkconfig.ci.default_generic
new file mode 100644
index 00000000000..dae839a7c87
--- /dev/null
+++ b/examples/ethernet/basic/sdkconfig.ci.default_generic
@@ -0,0 +1,11 @@
+CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET=y
+CONFIG_EXAMPLE_ETH_PHY_GENERIC=y
+CONFIG_EXAMPLE_ETH_MDC_GPIO=23
+CONFIG_EXAMPLE_ETH_MDIO_GPIO=18
+CONFIG_EXAMPLE_ETH_PHY_RST_GPIO=5
+CONFIG_EXAMPLE_ETH_PHY_ADDR=1
+
+CONFIG_ETH_ENABLED=y
+CONFIG_ETH_USE_ESP32_EMAC=y
+CONFIG_ETH_PHY_INTERFACE_RMII=y
+CONFIG_ETH_RMII_CLK_INPUT=y
diff --git a/examples/ethernet/ptp/CMakeLists.txt b/examples/ethernet/ptp/CMakeLists.txt
new file mode 100644
index 00000000000..532e3753b95
--- /dev/null
+++ b/examples/ethernet/ptp/CMakeLists.txt
@@ -0,0 +1,6 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(ethernet_ptp)
diff --git a/examples/ethernet/ptp/README.md b/examples/ethernet/ptp/README.md
new file mode 100644
index 00000000000..52428895f25
--- /dev/null
+++ b/examples/ethernet/ptp/README.md
@@ -0,0 +1,123 @@
+| Supported Targets | ESP32-P4 |
+| ----------------- | -------- |
+
+# Time Synchronization over PTP
+(See the README.md file in the upper level 'examples' directory for more information about examples.)
+
+## Overview
+
+This example demonstrates the use of Precision Time Protocol (PTP) for time synchronization over Ethernet in ESP-IDF. PTP allows precise time synchronization between different nodes in a network. The example initializes Ethernet, starts a PTP daemon (based on a [Nuttx implementation](https://github.com/apache/nuttx-apps/tree/master/netutils/ptpd) ported to ESP-IDF), and showcases synchronization accuracy by toggling a GPIO pin.
+
+The PTP protocol is transported over **Ethernet at Layer 2 (L2)**, following the guidelines set forth in Annex F of the IEEE 1588-2008 standard (also known as PTPv2). The **timestamps for synchronization are provided by internal Ethernet MAC (EMAC)** and are attached to Ethernet frames at the hardware level. These hardware-generated timestamps are then passed to the software via the **L2 TAP interface**, allowing precise clock synchronization with minimal latency.
+
+The example is designed to run at least with two ESP32P4 boards, where one acts as **the master** and the other as **the slave**. Both devices will begin toggling a GPIO pin once they are synchronized. By measuring alignment of the rising edges of the GPIO pulse on both devices using an oscilloscope, you can observe the synchronization precision. The pulse width and toggle frequency can be configured using ``CONFIG_EXAMPLE_PTP_PULSE_WIDTH_NS``.
+
+## How to use example
+
+### Hardware Required
+
+* It's recommended that you have two official ESP32P4 boards with Ethernet capabilities - [ESP32-P4-Function-EV-Board](https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/user_guide.html).
+
+* Oscilloscope to measure the GPIO pulse alignment between the master and slave devices.
+
+#### Pin Assignment
+
+See common pin assignments for Ethernet examples from [upper level](../README.md#common-pin-assignments).
+
+### Configure the project
+
+Run the:
+
+```
+idf.py menuconfig
+```
+and configure the following parameters:
+
+* **PTP Pulse GPIO Pin**: Set the GPIO pin number for pulse toggling.
+* **Pulse Width (ns)**: Set the pulse width (in nanoseconds).
+* **PTP Daemon Configuration**: Select either Master or Slave and configure all the associated parameters per your application needs. To achieve more precise synchronization, enable ``PTP Client delay requests``.
+* **Ethernet**: See common configurations for Ethernet examples from [upper level](../README.md#common-configurations).
+
+### Build, Flash, and Run
+
+Build the project for both boards and flash it, then run monitor tool to view serial output:
+
+```
+idf.py -p PORT build flash monitor
+```
+
+(Replace PORT with the name of the serial port to use.)
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects.
+
+## Example Output
+
+### PTP Slave
+
+```
+I (10107) ptpd: Got announce packet, seq 3120
+
+I (10107) ptpd: Switching to better PTP time source
+
+I (10107) gpio: GPIO[20]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 
+I (10107) ptpd: Got sync packet, seq 31198
+
+I (10127) ptpd: Waiting for follow-up
+
+I (10127) ptpd: Got follow-up packet, seq 31198
+
+I (10137) ptpd: Local time: 7.633787680, remote time 31996.904013440
+
+I (10137) ptpd: Jumped to timestamp 31996.935345720 s
+
+I (9866) ptp_example: Starting Pulse train
+
+I (9866) ptp_example: curr time: 230.312127120
+
+I (9876) ptp_example: next time: 231.500000000
+
+I (9876) main_task: Returned from app_main()
+I (10836) ptpd: Got sync packet, seq 229
+
+I (10836) ptpd: Waiting for follow-up
+
+I (10836) ptpd: Got follow-up packet, seq 229
+
+I (10846) ptpd: Local time: 231.286076880, remote time 231.286195640
+
+I (10846) ptpd: remote_delta_ns 231286195640, local_delta_ns 231286076880, tick_diff 118760
+
+I (10856) ptpd: offset_ns 118760, adj 130636, drift_acc 11876
+
+...
+
+I (59686) ptpd: Waiting for follow-up
+
+I (59686) ptpd: Got follow-up packet, seq 277
+
+I (59696) ptpd: Local time: 280.136196920, remote time 280.136196120
+
+I (59696) ptpd: remote_delta_ns 1030000440, local_delta_ns 1030000440, tick_diff 0
+
+I (59706) ptpd: offset_ns -186, adj 2, drift_acc 188
+
+I (59716) ptpd: Sent delay req, seq 19
+
+I (59716) ptpd: Got delay-resp, seq 19
+
+I (59726) ptpd: Path delay: 847 ns (avg: 626 ns)
+```
+
+### Synchronization Pulses
+
+The below figure shows synchronization pulses generated by master and slave device measured on oscilloscope.
+
+![sync_puls](./docs/sync_osc.jpg)
+
+## Troubleshooting
+
+See common troubleshooting for Ethernet examples from [upper level](../README.md#common-troubleshooting).
+
+(For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you as soon as possible.)
diff --git a/examples/ethernet/ptp/components/esp_eth_time/CMakeLists.txt b/examples/ethernet/ptp/components/esp_eth_time/CMakeLists.txt
new file mode 100644
index 00000000000..b80be4eafb1
--- /dev/null
+++ b/examples/ethernet/ptp/components/esp_eth_time/CMakeLists.txt
@@ -0,0 +1,3 @@
+idf_component_register(SRCS "esp_eth_time.c"
+                       PRIV_REQUIRES esp_eth
+                       INCLUDE_DIRS ".")
diff --git a/examples/ethernet/ptp/components/esp_eth_time/README.md b/examples/ethernet/ptp/components/esp_eth_time/README.md
new file mode 100644
index 00000000000..b369992b166
--- /dev/null
+++ b/examples/ethernet/ptp/components/esp_eth_time/README.md
@@ -0,0 +1,3 @@
+# ESP Ethernet Time Control Component Example
+
+This example component provides a wrapper around management of the internal Ethernet MAC Time (Time Stamping) system which is normally accessed via `esp_eth_ioctl` commands. The component is offering a more intuitive API mimicking POSIX `clock_settime`, `clock_gettime` group of time functions and so making it easier to integrate with existing systems.
diff --git a/examples/ethernet/ptp/components/esp_eth_time/esp_eth_time.c b/examples/ethernet/ptp/components/esp_eth_time/esp_eth_time.c
new file mode 100644
index 00000000000..b9f99223753
--- /dev/null
+++ b/examples/ethernet/ptp/components/esp_eth_time/esp_eth_time.c
@@ -0,0 +1,142 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include "esp_eth_time.h"
+
+static esp_eth_handle_t s_eth_hndl;
+
+static int esp_eth_clock_esp_err_to_errno(esp_err_t esp_err)
+{
+    switch (esp_err)
+    {
+    case ESP_ERR_INVALID_ARG:
+        return EINVAL;
+    case ESP_ERR_INVALID_STATE:
+        return EBUSY;
+    case ESP_ERR_TIMEOUT:
+        return ETIME;
+    }
+    // default "no err" when error cannot be isolated
+    return 0;
+}
+
+int esp_eth_clock_adjtime(clockid_t clk_id, esp_eth_clock_adj_param_t *adj)
+{
+    switch (clk_id) {
+    case CLOCK_PTP_SYSTEM:
+        if (adj->mode == ETH_CLK_ADJ_FREQ_SCALE) {
+            esp_err_t ret = esp_eth_ioctl(s_eth_hndl, ETH_MAC_ESP_CMD_ADJ_PTP_FREQ, &adj->freq_scale);
+            if (ret != ESP_OK) {
+                errno = esp_eth_clock_esp_err_to_errno(ret);
+                return -1;
+            }
+        } else {
+            errno = EINVAL;
+            return -1;
+        }
+        break;
+    default:
+        errno = EINVAL;
+        return -1;
+    }
+    return 0;
+}
+
+int esp_eth_clock_settime(clockid_t clock_id, const struct timespec *tp)
+{
+    switch (clock_id) {
+    case CLOCK_PTP_SYSTEM: {
+        if (s_eth_hndl) {
+            eth_mac_time_t ptp_time = {
+                .seconds = tp->tv_sec,
+                .nanoseconds = tp->tv_nsec
+            };
+            esp_err_t ret = esp_eth_ioctl(s_eth_hndl, ETH_MAC_ESP_CMD_S_PTP_TIME, &ptp_time);
+            if (ret != ESP_OK) {
+                errno = esp_eth_clock_esp_err_to_errno(ret);
+                return -1;
+            }
+        } else {
+            errno = ENODEV;
+            return -1;
+        }
+        break;
+    }
+    default:
+        errno = EINVAL;
+        return -1;
+    }
+    return 0;
+}
+
+int esp_eth_clock_gettime(clockid_t clock_id, struct timespec *tp)
+{
+    switch (clock_id) {
+    case CLOCK_PTP_SYSTEM: {
+        if (s_eth_hndl) {
+            eth_mac_time_t ptp_time;
+            esp_err_t ret = esp_eth_ioctl(s_eth_hndl, ETH_MAC_ESP_CMD_G_PTP_TIME, &ptp_time);
+            if (ret != ESP_OK) {
+                errno = esp_eth_clock_esp_err_to_errno(ret);
+                return -1;
+            }
+            tp->tv_sec = ptp_time.seconds;
+            tp->tv_nsec = ptp_time.nanoseconds;
+        } else {
+            errno = ENODEV;
+            return -1;
+        }
+        break;
+    }
+    default:
+        errno = EINVAL;
+        return -1;
+    }
+    return 0;
+}
+
+int esp_eth_clock_set_target_time(clockid_t clock_id, struct timespec *tp)
+{
+    eth_mac_time_t mac_target_time = {
+        .seconds = tp->tv_sec,
+        .nanoseconds = tp->tv_nsec
+    };
+    esp_err_t ret = esp_eth_ioctl(s_eth_hndl, ETH_MAC_ESP_CMD_S_TARGET_TIME, &mac_target_time);
+    if (ret != ESP_OK) {
+        errno = esp_eth_clock_esp_err_to_errno(ret);
+        return -1;
+    }
+    return 0;
+}
+
+int esp_eth_clock_register_target_cb(clockid_t clock_id,
+                                     ts_target_exceed_cb_from_isr_t ts_callback)
+{
+    esp_err_t ret = esp_eth_ioctl(s_eth_hndl, ETH_MAC_ESP_CMD_S_TARGET_CB, ts_callback);
+    if (ret != ESP_OK) {
+        errno = esp_eth_clock_esp_err_to_errno(ret);
+        return -1;
+    }
+    return 0;
+}
+
+esp_err_t esp_eth_clock_init(clockid_t clock_id, esp_eth_clock_cfg_t *cfg)
+{
+    switch (clock_id) {
+    case CLOCK_PTP_SYSTEM:
+        // PTP Clock is part of Ethernet system
+        bool ptp_enable = true;
+        if (esp_eth_ioctl(cfg->eth_hndl, ETH_MAC_ESP_CMD_PTP_ENABLE, &ptp_enable) != ESP_OK) {
+            return ESP_FAIL;
+        }
+        s_eth_hndl = cfg->eth_hndl;
+        break;
+    default:
+        return ESP_FAIL;
+    }
+    return ESP_OK;
+}
diff --git a/examples/ethernet/ptp/components/esp_eth_time/esp_eth_time.h b/examples/ethernet/ptp/components/esp_eth_time/esp_eth_time.h
new file mode 100644
index 00000000000..0fa34f078d4
--- /dev/null
+++ b/examples/ethernet/ptp/components/esp_eth_time/esp_eth_time.h
@@ -0,0 +1,131 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <sys/time.h>
+#include <stdint.h>
+#include "esp_err.h"
+#include "esp_eth_driver.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CLOCK_PTP_SYSTEM         ((clockid_t) 19)
+
+/**
+ * @brief Configuration of clock during initialization
+ *
+ */
+typedef struct {
+    esp_eth_handle_t eth_hndl;
+} esp_eth_clock_cfg_t;
+
+/**
+ * @brief The mode of clock adjustment.
+ *
+ */
+typedef enum {
+    ETH_CLK_ADJ_FREQ_SCALE,
+} esp_eth_clock_adj_mode_t;
+
+/**
+ * @brief Structure containing parameters for adjusting the Ethernet clock.
+ *
+ */
+typedef struct {
+    /**
+     * @brief The mode of clock adjustment.
+     *
+     */
+    esp_eth_clock_adj_mode_t mode;
+
+    /**
+     * @brief The frequency scale factor when in ETH_CLK_ADJ_FREQ_SCALE mode.
+     *
+     * This value represents the ratio of the desired frequency to the actual
+     * frequency. A value greater than 1 increases the frequency, while a value
+     * less than 1 decreases the frequency.
+     */
+    double freq_scale;
+} esp_eth_clock_adj_param_t;
+
+/**
+ * @brief Adjust the system clock frequency
+ *
+ * @param clk_id Identifier of the clock to adjust
+ * @param buf Pointer to the adjustment parameters
+ *
+ * @return
+ *     - 0: Success
+ *     - -1: Failure
+ */
+int esp_eth_clock_adjtime(clockid_t clk_id, esp_eth_clock_adj_param_t *adj);
+
+/**
+ * @brief Set the system clock time
+ *
+ * @param clk_id Identifier of the clock to set
+ * @param tp Pointer to the new time
+ *
+ * @return
+ *     - 0: Success
+ *     - -1: Failure
+ */
+int esp_eth_clock_settime(clockid_t clock_id, const struct timespec *tp);
+
+/**
+ * @brief Get the current system clock time
+ *
+ * @param clk_id Identifier of the clock to query
+ * @param tp Pointer to the buffer to store the current time
+ *
+ * @return
+ *     - 0: Success
+ *     - -1: Failure
+ */
+int esp_eth_clock_gettime(clockid_t clock_id, struct timespec *tp);
+
+/**
+ * @brief Set the target time for the system clock.
+ *
+ * @param clk_id Identifier of the clock to set the target time for
+ * @param tp Pointer to the target time
+ *
+ * @return
+ *     - 0: Success
+ *     - -1: Failure
+ */
+int esp_eth_clock_set_target_time(clockid_t clock_id, struct timespec *tp);
+
+/**
+ * @brief Register callback function invoked on Time Stamp target time exceeded interrupt
+ *
+ * @param clock_id Identifier of the clock
+ * @param ts_callback callback function to be registered
+ * @return
+ *     - 0: Success
+ *     - -1: Failure
+ */
+int esp_eth_clock_register_target_cb(clockid_t clock_id,
+                                     ts_target_exceed_cb_from_isr_t ts_callback);
+
+/**
+ * @brief Initialize the Ethernet clock subsystem
+ *
+ * @param clk_id Identifier of the clock to initialize
+ * @param cfg Pointer to the configuration structure
+ *
+ * @return
+ *     - ESP_OK: Success
+ *     - ESP_FAIL: Failure
+ */
+esp_err_t esp_eth_clock_init(clockid_t clock_id, esp_eth_clock_cfg_t *cfg);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/examples/ethernet/ptp/components/ptpd/CMakeLists.txt b/examples/ethernet/ptp/components/ptpd/CMakeLists.txt
new file mode 100644
index 00000000000..bfa611ce8c5
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/CMakeLists.txt
@@ -0,0 +1,6 @@
+idf_component_register(SRCS "ptpd.c"
+                       PRIV_REQUIRES esp_eth esp_netif
+                       INCLUDE_DIRS "." "./include")
+
+target_sources(${COMPONENT_LIB} PRIVATE "ptpd.c")
+target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-unused-function)
diff --git a/examples/ethernet/ptp/components/ptpd/Kconfig.projbuild b/examples/ethernet/ptp/components/ptpd/Kconfig.projbuild
new file mode 100644
index 00000000000..6fbcfbd6851
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/Kconfig.projbuild
@@ -0,0 +1,239 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+menu "PTP Daemon Configuration"
+
+    config NETUTILS_PTPD
+        bool "PTPD client/server"
+        default y
+    #depends on NET_IPv4
+    #depends on NET_IGMP
+    #depends on NET_UDP
+        help
+            Build a minimal implementation of IEEE-1588 precision time protocol.
+            Uses system gettimeofday() and adjtime() calls to synchronize clock
+            with a master clock through network, or to provide a master clock to
+            other systems.
+
+    if NETUTILS_PTPD
+
+        config NETUTILS_PTPD_DEBUG
+            bool "Enable PTP debug messages"
+            default n
+            depends on DEBUG_INFO
+            help
+                Enable PTP debug messages even if CONFIG_DEBUG_NET_INFO is not enabled.
+
+        config NETUTILS_PTPD_CLIENT
+            bool "Enable client support"
+            default y
+            help
+                Act as a PTP client, synchronizing the NuttX clock to a remote master
+                clock.
+
+        config NETUTILS_PTPD_SERVER
+            bool "Enable server support"
+            default n
+            help
+                Act as a PTP server, providing NuttX clock time to other systems.
+
+                Both server and client can be simultaneously enabled. NuttX will then
+                synchronize to a higher priority master clock, or act as a master
+                clock itself if it has the highest priority.
+                Refer to Best Master Clock algorithm in IEEE-1588 for details.
+
+        config NETUTILS_PTPD_STACKSIZE
+            int "PTP daemon stack stack size"
+            default 4096 # DEFAULT_TASK_STACKSIZE
+
+        config NETUTILS_PTPD_SERVERPRIO
+            int "PTP daemon priority"
+            default 100
+
+        config NETUTILS_PTPD_DOMAIN
+            int    "PTP domain selection"
+            default 0
+            range 0 127
+            help
+                Set PTP domain to participate in. Default domain is 0, other domains
+                can be used to isolate reference clocks from each other.
+
+        if NETUTILS_PTPD_SERVER
+
+            config NETUTILS_PTPD_PRIORITY1
+                int "PTP server priority1"
+                default 128
+                range 0 255
+                help
+                    Set clock priority to announce when acting as a PTP server.
+                    Lower value is higher priority.
+                    A higher priority1 clock will be selected without regard to announced
+                    clock quality fields.
+                    Refer to Best Master Clock algorithm in IEEE-1588 for details.
+
+            config NETUTILS_PTPD_PRIORITY2
+                int "PTP server priority2"
+                default 128
+                range 0 255
+                help
+                    Set clock subpriority to announce when acting as a PTP server.
+                    This will distinguish between two clocks that are equivalent in
+                    priority1, class and accuracy values.
+                    Lower value is higher priority.
+
+            config NETUTILS_PTPD_CLASS
+                int "PTP server class"
+                default 248
+                range 0 255
+                help
+                    Set master clock class to announce when acting as a PTP server.
+                    Lower value means higher quality clock source.
+                    248 is the default for unknown class.
+
+            config NETUTILS_PTPD_ACCURACY
+                int "PTP server accuracy"
+                default 254
+                range 0 255
+                help
+                    Set master clock accuracy to announce when acting as a PTP server.
+                    Logarithmic scale is defined in IEEE-1588:
+                    32: +-  25 ns
+                    33: +- 100 ns
+                    34: +- 250 ns
+                    35: +-   1 us
+                    36: +-   2.5 us
+                    37: +-  10 us
+                    38: +-  25 us
+                    39: +- 100 us
+                    40: +- 250 us
+                    41: +-   1 ms
+                    42: +-   2.5 ms
+                    43: +-  10 ms
+                    44: +-  25 ms
+                    45: +- 100 ms
+                    46: +- 250 ms
+                    47: +-   1 s
+                    48: +-  10 s
+                    49: +-  more than 10 s
+                    254: Unknown
+
+            config NETUTILS_PTPD_CLOCKSOURCE
+                int "PTP server clock source type"
+                default 160
+                range 0 255
+                help
+                    Set clock source type to announce when acting as a PTP server.
+                    Common values:
+                    32: GPS
+                    64: PTP
+                    80: NTP
+                    144: Other
+                    160: Internal oscillator
+
+            config NETUTILS_PTPD_SYNC_INTERVAL_MSEC
+                int "PTP server sync transmit interval (ms)"
+                default 1000
+                help
+                    How often to transmit sync packets in server mode.
+
+            config NETUTILS_PTPD_ANNOUNCE_INTERVAL_MSEC
+                int "PTP server announce transmit interval (ms)"
+                default 10000
+                help
+                    How often to transmit announce packets in server mode.
+
+            config NETUTILS_PTPD_TWOSTEP_SYNC
+                bool "PTP server sends two-step synchronization packets"
+                default y
+                help
+                    If enabled, sends a follow-up packet after every sync packet.
+                    This helps compensate for the time taken to initiate the transmission.
+
+            config NETUTILS_PTPD_DELAYRESP_INTERVAL
+                int "PTP server suggested interval of delay requests"
+                range 0 255
+                default 4
+                help
+                    When responding to a delay request, the server can inform the client
+                    how often it should test path delay. This is done using header field
+                    logMessageInterval. The delay will be 2^N seconds.
+
+                    Default value 4 results in 16 second interval.
+
+        endif # NETUTILS_PTPD_SERVER
+
+        if NETUTILS_PTPD_CLIENT
+
+            config NETUTILS_PTPD_TIMEOUT_MS
+                int "PTP client timeout for changing clock source (ms)"
+                default 60000
+                help
+                    If no packets are being received from currently chosen clock source,
+                    fall back to next best clock source after this many seconds.
+
+            config NETUTILS_PTPD_SETTIME_THRESHOLD_MS
+                int "PTP client threshold for changing system time (ms)"
+                default 1000
+                help
+                    If difference between local and remote clock exceeds this threshold,
+                    time is reset with settimeofday() instead of changing the rate with
+                    adjtime().
+
+        # Commented options not used by ESP_PTP
+        #config NETUTILS_PTPD_MULTICAST_TIMEOUT_MS
+        #    int "PTP client timeout to rejoin multicast group (ms)"
+        #    default 30000 #esp32
+        #    default 0
+        #    help
+        #        If no PTP multicast packets are being received, attempt to rejoin the
+        #        multicast group. This can be necessary if network topology changes, or
+        #        depending on hardware, after some error recovery events.
+        #        Set to 0 to disable.
+
+        #config NETUTILS_PTPD_DRIFT_AVERAGE_S
+        #    int "PTP client clock drift rate averaging time (s)"
+        #    default 600
+        #    range 10 86400
+        #    help
+        #        Clock drift rate is averaged over this time pediod. Larger value
+        #        gives more stable estimate but reacts slower to crystal oscillator speed
+        #        changes (such as caused by temperature changes).
+
+            config NETUTILS_PTPD_SEND_DELAYREQ
+                bool "PTP client enable delay requests"
+                default n
+                help
+                    If enabled, sends delay request messages to measure the network delay
+                    to server. If disabled, assumes zero delay.
+
+            if NETUTILS_PTPD_SEND_DELAYREQ
+
+                config NETUTILS_PTPD_MAX_PATH_DELAY_NS
+                    int "PTP client maximum path delay (ns)"
+                    default 100000
+                    range 1 1000000000
+                    help
+                        Measured path delay longer than this is ignored. Delay requests are
+                        also not transmitted until clock synchronization is better than this.
+
+                config NETUTILS_PTPD_DELAYREQ_AVGCOUNT
+                    int "PTP client path delay averaging count"
+                    default 100
+                    help
+                        Measured path delay is averaged over this many samples.
+
+                config NETUTILS_PTPD_PATH_DELAY_STABILITY_NS
+                    int "PTP client send delay request when clock stability (ns)"
+                    default 250
+                    help
+                        Sends path delay request only once the internal clock is stable and skews only
+                        in defined interval.
+
+            endif # NETUTILS_PTPD_SEND_DELAYREQ
+
+        endif # NETUTILS_PTPD_CLIENT
+
+    endif # NETUTILS_PTPD
+
+endmenu # PTP Daemon Configuration
diff --git a/examples/ethernet/ptp/components/ptpd/Make.defs b/examples/ethernet/ptp/components/ptpd/Make.defs
new file mode 100644
index 00000000000..c3f5f60ffb0
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/Make.defs
@@ -0,0 +1,23 @@
+############################################################################
+# apps/netutils/ptpd/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+ifneq ($(CONFIG_NETUTILS_PTPD),)
+CONFIGURED_APPS += $(APPDIR)/netutils/ptpd
+endif
diff --git a/examples/ethernet/ptp/components/ptpd/Makefile b/examples/ethernet/ptp/components/ptpd/Makefile
new file mode 100644
index 00000000000..3f3e98a361b
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/Makefile
@@ -0,0 +1,27 @@
+############################################################################
+# apps/netutils/ptpd/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements.  See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership.  The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License.  You may obtain a copy of the License at
+#
+#   http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(APPDIR)/Make.defs
+
+# PTP server/client implementation
+
+CSRCS = ptpd.c
+
+include $(APPDIR)/Application.mk
diff --git a/examples/ethernet/ptp/components/ptpd/README.md b/examples/ethernet/ptp/components/ptpd/README.md
new file mode 100644
index 00000000000..8f56b771ef6
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/README.md
@@ -0,0 +1,3 @@
+# NuttX PTP Daemon Port Example
+
+This example component presents port of [Nuttx PTP Daemon](https://github.com/apache/nuttx-apps/tree/master/netutils/ptpd) for ESP-IDF.
diff --git a/examples/ethernet/ptp/components/ptpd/idf_component.yml b/examples/ethernet/ptp/components/ptpd/idf_component.yml
new file mode 100644
index 00000000000..97451ea9721
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/idf_component.yml
@@ -0,0 +1,3 @@
+dependencies:
+  esp_eth_time:
+    path: ${IDF_PATH}/examples/ethernet/ptp/components/esp_eth_time
diff --git a/examples/ethernet/ptp/components/ptpd/include/ptpd.h b/examples/ethernet/ptp/components/ptpd/include/ptpd.h
new file mode 100644
index 00000000000..0a65c4885b3
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/include/ptpd.h
@@ -0,0 +1,188 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 The Apache Software Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * SPDX-FileContributor: 2024 Espressif Systems (Shanghai) CO LTD
+ */
+
+/****************************************************************************
+ * apps/include/netutils/ptpd.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __APPS_INCLUDE_NETUTILS_PTPD_H
+#define __APPS_INCLUDE_NETUTILS_PTPD_H
+
+// ESP_PTP
+#include <time.h>
+#ifndef FAR
+#define FAR
+#endif
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* PTPD status information structure */
+
+struct ptpd_status_s
+{
+  /* Is there a valid remote clock source active? */
+
+  bool clock_source_valid;
+
+  /* Information about selected best clock source */
+
+  struct
+  {
+    uint8_t id[8];     /* Clock identity */
+    int utcoffset;     /* Offset between clock time and UTC time (seconds) */
+    int priority1;     /* Main priority field */
+    int clockclass;    /* Clock class (IEEE-1588, lower is better) */
+    int accuracy;      /* Clock accuracy (IEEE-1588, lower is better) */
+    int variance;      /* Clock variance (IEEE-1588, lower is better) */
+    int priority2;     /* Secondary priority field */
+    uint8_t gm_id[8];  /* Grandmaster clock identity */
+    int stepsremoved;  /* How many steps from grandmaster clock */
+    int timesource;    /* Type of time source (IEEE-1588) */
+  } clock_source_info;
+
+  /* When was clock last updated or adjusted (CLOCK_REALTIME).
+   * Matches last_received_sync but in different clock.
+   */
+
+  struct timespec last_clock_update;
+
+  /* Details of clock adjustment made at last_clock_update */
+
+  int64_t last_delta_ns;     /* Latest measured clock error */
+  int64_t last_adjtime_ns;   /* Previously applied adjtime() offset */
+
+  /* Averaged clock drift estimate (parts per billion).
+   * Positive means remote clock runs faster than local clock before
+   * adjustment.
+   */
+
+  long drift_ppb;
+
+  /* Averaged path delay */
+
+  long path_delay_ns;
+
+  /* Timestamps of latest received packets (CLOCK_MONOTONIC) */
+
+  struct timespec last_received_multicast; /* Any multicast packet */
+  struct timespec last_received_announce;  /* Announce from any server */
+  struct timespec last_received_sync;      /* Sync from selected source */
+
+  /* Timestamps of latest transmitted packets (CLOCK_MONOTONIC) */
+
+  struct timespec last_transmitted_sync;
+  struct timespec last_transmitted_announce;
+  struct timespec last_transmitted_delayresp;
+  struct timespec last_transmitted_delayreq;
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ptpd_start
+ *
+ * Description:
+ *   Start the PTP daemon and bind it to specified interface.
+ *
+ * Input Parameters:
+ *   interface - Name of the network interface to bind to, e.g. "eth0"
+ *
+ * Returned Value:
+ *   On success, the non-negative task ID of the PTP daemon is returned;
+ *   On failure, a negated errno value is returned.
+ *
+ ****************************************************************************/
+
+int ptpd_start(FAR const char *interface);
+
+/****************************************************************************
+ * Name: ptpd_status
+ *
+ * Description:
+ *   Query status from a running PTP daemon.
+ *
+ * Input Parameters:
+ *   pid     - Process ID previously returned by ptpd_start()
+ *   status  - Pointer to storage for status information.
+ *
+ * Returned Value:
+ *   On success, returns OK.
+ *   On failure, a negated errno value is returned.
+ *
+ * Assumptions/Limitations:
+ *   Multiple threads with priority less than CONFIG_NETUTILS_PTPD_SERVERPRIO
+ *   can request status simultaneously. If higher priority threads request
+ *   status simultaneously, some of the requests may timeout.
+ *
+ ****************************************************************************/
+
+int ptpd_status(int pid, FAR struct ptpd_status_s *status);
+
+/****************************************************************************
+ * Name: ptpd_stop
+ *
+ * Description:
+ *   Stop PTP daemon
+ *
+ * Input Parameters:
+ *   pid     - Process ID previously returned by ptpd_start()
+ *
+ * Returned Value:
+ *   On success, returns OK.
+ *   On failure, a negated errno value is returned.
+ *
+ ****************************************************************************/
+
+int ptpd_stop(int pid);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APPS_INCLUDE_NETUTILS_PTPD_H */
diff --git a/components/soc/esp32c3/register/soc/.gitkeep b/examples/ethernet/ptp/components/ptpd/port/esp_ptpd.c
similarity index 100%
rename from components/soc/esp32c3/register/soc/.gitkeep
rename to examples/ethernet/ptp/components/ptpd/port/esp_ptpd.c
diff --git a/examples/ethernet/ptp/components/ptpd/ptpd.c b/examples/ethernet/ptp/components/ptpd/ptpd.c
new file mode 100644
index 00000000000..c20657338a5
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/ptpd.c
@@ -0,0 +1,2142 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 The Apache Software Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * SPDX-FileContributor: 2024 Espressif Systems (Shanghai) CO LTD
+ */
+
+/****************************************************************************
+ * apps/netutils/ptpd/ptpd.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#define ESP_PTP 1
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+#ifndef ESP_PTP
+#include <nuttx/config.h>
+#endif
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <sys/socket.h>
+#include <sys/time.h>
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <sched.h>
+#include <assert.h>
+#include <errno.h>
+#ifndef ESP_PTP
+#include <debug.h>
+#endif
+#include <unistd.h>
+#include <fcntl.h>
+
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#ifndef ESP_PTP
+#include <netutils/ipmsfilter.h>
+#endif
+
+#include <net/if.h>
+#include <sys/ioctl.h>
+#include <sys/poll.h>
+#ifndef ESP_PTP
+#include <nuttx/net/netconfig.h>
+#include <netutils/ptpd.h>
+#endif
+
+#include "ptpv2.h"
+
+#ifdef ESP_PTP
+#include "ptpd.h"
+#include "esp_eth_driver.h"
+#include "esp_vfs_l2tap.h"
+#include "semaphore.h"
+#include "esp_log.h"
+#include "esp_err.h"
+#include "lwip/prot/ethernet.h" // Ethernet headers
+
+#include "esp_eth_time.h"
+
+#define ETH_TYPE_PTP 0x88F7
+
+#define ERROR ESP_FAIL
+#define OK ESP_OK
+
+#define UNUSED (void)
+
+#define MSEC_PER_SEC 1000
+#define NSEC_PER_USEC 1000
+#define NSEC_PER_MSEC 1000000ll
+#define NSEC_PER_SEC 1000000000ll
+
+// To able to set either only server or only client
+#ifndef CONFIG_NETUTILS_PTPD_TIMEOUT_MS
+#define CONFIG_NETUTILS_PTPD_TIMEOUT_MS 0
+#endif
+#ifndef CONFIG_NETUTILS_PTPD_SETTIME_THRESHOLD_MS
+#define CONFIG_NETUTILS_PTPD_SETTIME_THRESHOLD_MS 0
+#endif
+#ifndef CONFIG_NETUTILS_PTPD_MAX_PATH_DELAY_NS
+#define CONFIG_NETUTILS_PTPD_MAX_PATH_DELAY_NS 0
+#endif
+#ifndef CONFIG_NETUTILS_PTPD_DELAYREQ_AVGCOUNT
+#define CONFIG_NETUTILS_PTPD_DELAYREQ_AVGCOUNT 0
+#endif
+#ifndef CONFIG_NETUTILS_PTPD_DELAYRESP_INTERVAL
+#define CONFIG_NETUTILS_PTPD_DELAYRESP_INTERVAL 0
+#endif
+#ifndef CONFIG_NETUTILS_PTPD_PATH_DELAY_STABILITY_NS
+#define CONFIG_NETUTILS_PTPD_PATH_DELAY_STABILITY_NS 0
+#endif
+
+#define clock_timespec_subtract(ts1, ts2, ts3) timespecsub(ts1, ts2, ts3)
+#define clock_timespec_add(ts1, ts2, ts3) timespecadd(ts1, ts2, ts3)
+
+#endif // ESP_PTP
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef ESP_PTP
+#define ADJ_FREQ_MAX 512000 // TODO tuneup
+typedef struct
+{
+  int32_t kp;
+  int32_t ki;
+  int32_t drift_acc;
+} pi_cntrl_t;
+#endif // ESP_PTP
+
+/* Carrier structure for querying PTPD status */
+
+struct ptpd_statusreq_s
+{
+  FAR sem_t *done;
+  FAR struct ptpd_status_s *dest;
+};
+
+/* Main PTPD state storage */
+
+struct ptp_state_s
+{
+  /* Request for PTPD task to stop or report status */
+
+  bool stop;
+  struct ptpd_statusreq_s status_req;
+
+#ifdef ESP_PTP
+  uint8_t intf_hw_addr[ETH_ADDR_LEN];
+  int ptp_socket;
+
+  int64_t remote_time_ns_prev;
+  int64_t local_time_ns_prev;
+
+  int64_t last_offset_ns;
+
+  pi_cntrl_t offset_pi;
+#else
+  /* Address of network interface we are operating on */
+
+  struct sockaddr_in interface_addr;
+
+  /* Socket bound to interface for transmission */
+
+  int tx_socket;
+
+  /* Sockets for PTP event and information ports */
+
+  int event_socket;
+
+  int info_socket;
+#endif // ESP_PTP
+
+  /* Our own identity as a clock source */
+
+  struct ptp_announce_s own_identity;
+
+  /* Sequence number counters per message type */
+
+  uint16_t announce_seq;
+  uint16_t sync_seq;
+  uint16_t delay_req_seq;
+
+  /* Previous measurement and estimated clock drift rate */
+
+  struct timespec last_delta_timestamp;
+  int64_t last_delta_ns;
+  int64_t last_adjtime_ns;
+  long drift_avg_total_ms;
+  long drift_ppb;
+
+  /* Identity of currently selected clock source,
+   * from the latest announcement message.
+   *
+   * The timestamps are used for timeout when a source disappears.
+   * They are from the local CLOCK_MONOTONIC.
+   */
+
+  bool selected_source_valid;              /* True if operating as client */
+  struct ptp_announce_s selected_source;   /* Currently selected server */
+  struct timespec last_received_multicast; /* Any multicast packet */
+  struct timespec last_received_announce;  /* Announce from any server */
+  struct timespec last_received_sync;      /* Sync from selected source */
+
+  /* Last transmitted packet timestamps (CLOCK_MONOTONIC)
+   * Used to set transmission interval.
+   */
+
+  struct timespec last_transmitted_sync;
+  struct timespec last_transmitted_announce;
+  struct timespec last_transmitted_delayresp;
+  struct timespec last_transmitted_delayreq;
+
+  /* Timestamps related to path delay calculation (CLOCK_REALTIME) */
+
+  bool can_send_delayreq;
+  struct timespec delayreq_time;
+  int path_delay_avgcount;
+  long path_delay_ns;
+  long delayreq_interval;
+
+  /* Latest received packet and its timestamp (CLOCK_REALTIME) */
+
+  struct timespec rxtime;
+  union
+  {
+    struct ptp_header_s     header;
+    struct ptp_announce_s   announce;
+    struct ptp_sync_s       sync;
+    struct ptp_follow_up_s  follow_up;
+    struct ptp_delay_req_s  delay_req;
+    struct ptp_delay_resp_s delay_resp;
+    uint8_t                 raw[128];
+  } rxbuf;
+
+#ifndef ESP_PTP
+  uint8_t rxcmsg[CMSG_LEN(sizeof(struct timeval))];
+#endif // ESP_PTP
+
+  /* Buffered sync packet for two-step clock setting where server sends
+   * the accurate timestamp in a separate follow-up message.
+   */
+
+  struct ptp_sync_s twostep_packet;
+  struct timespec twostep_rxtime;
+};
+
+#ifdef CONFIG_NETUTILS_PTPD_SERVER
+#  define PTPD_POLL_INTERVAL CONFIG_NETUTILS_PTPD_SYNC_INTERVAL_MSEC
+#else
+#  define PTPD_POLL_INTERVAL CONFIG_NETUTILS_PTPD_TIMEOUT_MS
+#endif
+
+/* PTP debug messages are enabled by either CONFIG_DEBUG_NET_INFO
+ * or separately by CONFIG_NETUTILS_PTPD_DEBUG. This simplifies
+ * debugging without having excessive amount of logging from net.
+ */
+
+#ifdef ESP_PTP
+static const char *TAG = "ptpd";
+#define ptpinfo(format, ...) ESP_LOGI(TAG, format, ##__VA_ARGS__)
+#define ptpwarn(format, ...) ESP_LOGW(TAG, format, ##__VA_ARGS__)
+#define ptperr(format, ...) ESP_LOGE(TAG, format, ##__VA_ARGS__)
+#else
+#ifdef CONFIG_NETUTILS_PTPD_DEBUG
+#  define ptpinfo _info
+#  define ptpwarn _warn
+#  define ptperr  _err
+#else
+#  define ptpinfo ninfo
+#  define ptpwarn nwarn
+#  define ptperr  nerr
+#endif
+#endif // ESP_PTP
+
+#ifdef ESP_PTP
+static struct ptp_state_s *s_state;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+#ifdef ESP_PTP
+static void ptp_create_eth_frame(struct ptp_state_s *state, uint8_t *eth_frame, void *ptp_msg, uint16_t ptp_msg_len)
+{
+  struct eth_hdr eth_hdr = {
+    //.dest.addr = {0x01, 0x80, 0xC2, 0x00, 0x00, 0x0E}, // TODO only for Pdelay_Req, Pdelay_Resp and Pdelay_Resp_Follow_Up
+    .dest.addr = {0x01, 0x1B, 0x19, 0x00, 0x00, 0x00}, // All except peer delay messages, ptp4l sends everything at this addr
+    .type = htons(ETH_TYPE_PTP)
+  };
+  memcpy(&eth_hdr.src.addr, state->intf_hw_addr, ETH_ADDR_LEN);
+
+  memcpy(eth_frame, &eth_hdr, sizeof(eth_hdr));
+  memcpy(eth_frame + sizeof(eth_hdr), ptp_msg, ptp_msg_len);
+}
+
+static int ptp_net_send(FAR struct ptp_state_s *state, void *ptp_msg, uint16_t ptp_msg_len, struct timespec *ts)
+{
+  uint8_t eth_frame[ptp_msg_len + ETH_HEADER_LEN];
+  ptp_create_eth_frame(state, eth_frame, ptp_msg, ptp_msg_len);
+
+  // wrap "Info Records Buffer" into union to ensure proper alignment of data (this is typically needed when
+  // accessing double word variables or structs containing double word variables)
+  union {
+      uint8_t info_recs_buff[L2TAP_IREC_SPACE(sizeof(struct timespec))];
+      l2tap_irec_hdr_t align;
+  } u;
+
+  l2tap_extended_buff_t ptp_msg_ext_buff;
+
+  ptp_msg_ext_buff.info_recs_len = sizeof(u.info_recs_buff);
+  ptp_msg_ext_buff.info_recs_buff = u.info_recs_buff;
+  ptp_msg_ext_buff.buff = eth_frame;
+  ptp_msg_ext_buff.buff_len = sizeof(eth_frame);
+
+  l2tap_irec_hdr_t *ts_info = L2TAP_IREC_FIRST(&ptp_msg_ext_buff);
+  ts_info->len = L2TAP_IREC_LEN(sizeof(struct timespec));
+  ts_info->type = L2TAP_IREC_TIME_STAMP;
+
+  int ret = write(state->ptp_socket, &ptp_msg_ext_buff, 0);
+
+  // check if write was successful, ts exists and ts_info is valid
+  if (ret > 0 && ts && ts_info->type == L2TAP_IREC_TIME_STAMP)
+    {
+      *ts = *(struct timespec *)ts_info->data;
+    }
+
+  return ret;
+}
+
+static int ptp_net_recv(FAR struct ptp_state_s *state, void *ptp_msg, uint16_t ptp_msg_len, struct timespec *ts)
+{
+  uint8_t eth_frame[ptp_msg_len + ETH_HEADER_LEN];
+
+  // wrap "Info Records Buffer" into union to ensure proper alignment of data (this is typically needed when
+  // accessing double word variables or structs containing double word variables)
+  union {
+      uint8_t info_recs_buff[L2TAP_IREC_SPACE(sizeof(struct timespec))];
+      l2tap_irec_hdr_t align;
+  } u;
+  l2tap_extended_buff_t ptp_msg_ext_buff;
+
+  ptp_msg_ext_buff.info_recs_len = sizeof(u.info_recs_buff);
+  ptp_msg_ext_buff.info_recs_buff = u.info_recs_buff;
+  ptp_msg_ext_buff.buff = eth_frame;
+  ptp_msg_ext_buff.buff_len = sizeof(eth_frame);
+
+  l2tap_irec_hdr_t *ts_info = L2TAP_IREC_FIRST(&ptp_msg_ext_buff);
+  ts_info->len = L2TAP_IREC_LEN(sizeof(struct timespec));
+  ts_info->type = L2TAP_IREC_TIME_STAMP;
+
+  int ret = read(state->ptp_socket, &ptp_msg_ext_buff, 0);
+
+  // check if read was successful, ts exists and ts_info is valid
+  if (ret > 0 && ts && ts_info->type == L2TAP_IREC_TIME_STAMP)
+    {
+      *ts = *(struct timespec *)ts_info->data;
+    }
+
+  memcpy(ptp_msg, &eth_frame[ETH_HEADER_LEN], ret);
+
+  return ret;
+}
+
+static int64_t timespec_to_ns(FAR const struct timespec *ts)
+{
+  return ts->tv_sec * NSEC_PER_SEC + (ts->tv_nsec);
+}
+#endif // ESP_PTP
+
+/* Convert from timespec to PTP format */
+
+static void timespec_to_ptp_format(FAR struct timespec *ts,
+                                   FAR uint8_t *timestamp)
+{
+  /* IEEE 1588 uses 48 bits for seconds and 32 bits for nanoseconds,
+   * both fields big-endian.
+   */
+
+#ifdef CONFIG_SYSTEM_TIME64
+  timestamp[0] = (uint8_t)(ts->tv_sec >> 40);
+  timestamp[1] = (uint8_t)(ts->tv_sec >> 32);
+#else
+  timestamp[0] = 0;
+  timestamp[1] = 0;
+#endif
+  timestamp[2] = (uint8_t)(ts->tv_sec >> 24);
+  timestamp[3] = (uint8_t)(ts->tv_sec >> 16);
+  timestamp[4] = (uint8_t)(ts->tv_sec >>  8);
+  timestamp[5] = (uint8_t)(ts->tv_sec >>  0);
+
+  timestamp[6] = (uint8_t)(ts->tv_nsec >>  24);
+  timestamp[7] = (uint8_t)(ts->tv_nsec >>  16);
+  timestamp[8] = (uint8_t)(ts->tv_nsec >>   8);
+  timestamp[9] = (uint8_t)(ts->tv_nsec >>   0);
+}
+
+/* Convert from PTP format to timespec */
+
+static void ptp_format_to_timespec(FAR const uint8_t *timestamp,
+                                   FAR struct timespec *ts)
+{
+  ts->tv_sec =
+      (((int64_t)timestamp[0]) << 40)
+    | (((int64_t)timestamp[1]) << 32)
+    | (((int64_t)timestamp[2]) << 24)
+    | (((int64_t)timestamp[3]) << 16)
+    | (((int64_t)timestamp[4]) <<  8)
+    | (((int64_t)timestamp[5]) <<  0);
+
+  ts->tv_nsec =
+      (((long)timestamp[6]) << 24)
+    | (((long)timestamp[7]) << 16)
+    | (((long)timestamp[8]) <<  8)
+    | (((long)timestamp[9]) <<  0);
+}
+
+/* Returns true if A is a better clock source than B.
+ * Implements Best Master Clock algorithm from IEEE-1588.
+ */
+
+static bool is_better_clock(FAR const struct ptp_announce_s *a,
+                            FAR const struct ptp_announce_s *b)
+{
+  if  (a->gm_priority1 < b->gm_priority1     /* Main priority field */
+    || a->gm_quality[0] < b->gm_quality[0]   /* Clock class */
+    || a->gm_quality[1] < b->gm_quality[1]   /* Clock accuracy */
+    || a->gm_quality[2] < b->gm_quality[2]   /* Clock variance high byte */
+    || a->gm_quality[3] < b->gm_quality[3]   /* Clock variance low byte */
+    || a->gm_priority2 < b->gm_priority2     /* Sub priority field */
+    || memcmp(a->gm_identity, b->gm_identity, sizeof(a->gm_identity)) < 0)
+    {
+      return true;
+    }
+    else
+    {
+      return false;
+    }
+}
+
+static int64_t timespec_to_ms(FAR const struct timespec *ts)
+{
+  return ts->tv_sec * MSEC_PER_SEC + (ts->tv_nsec / NSEC_PER_MSEC);
+}
+
+/* Get positive or negative delta between two timespec values.
+ * If value would exceed int64 limit (292 years), return INT64_MAX/MIN.
+ */
+
+static int64_t timespec_delta_ns(FAR const struct timespec *ts1,
+                                 FAR const struct timespec *ts2)
+{
+  int64_t delta_s;
+
+  delta_s = ts1->tv_sec - ts2->tv_sec;
+
+#ifdef CONFIG_SYSTEM_TIME64
+  /* Conversion to nanoseconds could overflow if the system time is 64-bit */
+
+  if (delta_s >= INT64_MAX / NSEC_PER_SEC)
+    {
+      return INT64_MAX;
+    }
+  else if (delta_s <= INT64_MIN / NSEC_PER_SEC)
+    {
+      return INT64_MIN;
+    }
+#endif
+
+  return delta_s * NSEC_PER_SEC + (ts1->tv_nsec - ts2->tv_nsec);
+}
+
+/* Check if the currently selected source is still valid */
+
+static bool is_selected_source_valid(FAR struct ptp_state_s *state)
+{
+  struct timespec time_now;
+  struct timespec delta;
+
+  if ((state->selected_source.header.messagetype & PTP_MSGTYPE_MASK)
+      != PTP_MSGTYPE_ANNOUNCE)
+    {
+      return false; /* Uninitialized value */
+    }
+
+  /* Note: this uses monotonic clock to track the timeout even when
+   *       system clock is adjusted.
+   */
+
+  clock_gettime(CLOCK_MONOTONIC, &time_now);
+  clock_timespec_subtract(&time_now, &state->last_received_sync, &delta);
+
+  if (timespec_to_ms(&delta) > CONFIG_NETUTILS_PTPD_TIMEOUT_MS)
+    {
+#ifdef ESP_PTP
+      ESP_LOGD(TAG, "Too long time since received packet\n");
+#endif // ESP_PTP
+      return false; /* Too long time since received packet */
+    }
+
+  return true;
+}
+
+/* Increment sequence number for packet type, and copy to header */
+
+static void ptp_increment_sequence(FAR uint16_t *sequence_num,
+                                   FAR struct ptp_header_s *hdr)
+{
+  *sequence_num += 1;
+  hdr->sequenceid[0] = (uint8_t)(*sequence_num >> 8);
+  hdr->sequenceid[1] = (uint8_t)(*sequence_num);
+}
+
+/* Get sequence number from received packet */
+
+static uint16_t ptp_get_sequence(FAR const struct ptp_header_s *hdr)
+{
+  return ((uint16_t)hdr->sequenceid[0] << 8) | hdr->sequenceid[1];
+}
+
+/* Get current system timestamp as a timespec
+ * TODO: Possibly add support for selecting different clock or using
+ *       architecture-specific interface for clock access.
+ */
+
+static int ptp_gettime(FAR struct ptp_state_s *state,
+                       FAR struct timespec *ts)
+{
+  UNUSED(state);
+#ifdef ESP_PTP
+  return esp_eth_clock_gettime(CLOCK_PTP_SYSTEM, ts);
+#else
+  return clock_gettime(CLOCK_REALTIME, ts);
+#endif // ESP_PTP
+}
+
+/* Change current system timestamp by jumping */
+
+static int ptp_settime(FAR struct ptp_state_s *state,
+                       FAR struct timespec *ts)
+{
+  UNUSED(state);
+#ifdef ESP_PTP
+  return esp_eth_clock_settime(CLOCK_PTP_SYSTEM, ts);
+#else
+  return clock_settime(CLOCK_REALTIME, ts);
+#endif // ESP_PTP
+}
+
+#ifndef ESP_PTP
+/* Smoothly adjust timestamp. */
+
+static int ptp_adjtime(FAR struct ptp_state_s *state, int64_t delta_ns)
+{
+  struct timeval delta;
+
+  delta.tv_sec = delta_ns / NSEC_PER_SEC;
+  delta_ns -= (int64_t)delta.tv_sec * NSEC_PER_SEC;
+  delta.tv_usec = delta_ns / NSEC_PER_USEC;
+  return adjtime(&delta, NULL);
+}
+#endif // !ESP_PTP
+
+#ifndef ESP_PTP
+/* Get timestamp of latest received packet */
+
+static int ptp_getrxtime(FAR struct ptp_state_s *state,
+                         FAR struct msghdr *rxhdr,
+                         FAR struct timespec *ts)
+{
+  /* Get hardware or kernel timestamp if available */
+
+#ifdef CONFIG_NET_TIMESTAMP
+  struct cmsghdr *cmsg;
+
+  for_each_cmsghdr(cmsg, rxhdr)
+    {
+      if (cmsg->cmsg_level == SOL_SOCKET &&
+          cmsg->cmsg_type == SO_TIMESTAMP &&
+          cmsg->cmsg_len == CMSG_LEN(sizeof(struct timeval)))
+        {
+          TIMEVAL_TO_TIMESPEC((FAR struct timeval *)CMSG_DATA(cmsg), ts);
+
+          /* Sanity-check the value */
+
+          if (ts->tv_sec > 0 || ts->tv_nsec > 0)
+            {
+              return OK;
+            }
+        }
+    }
+
+  ptpwarn("CONFIG_NET_TIMESTAMP enabled but did not get packet timestamp\n");
+#endif
+
+  /* Fall back to current timestamp */
+
+  return ptp_gettime(state, ts);
+}
+#endif // !ESP_PTP
+
+/* Initialize PTP client/server state and create sockets */
+#ifdef ESP_PTP
+static int ptp_initialize_state(FAR struct ptp_state_s *state,
+                                FAR const char *interface)
+{
+  state->ptp_socket = open("/dev/net/tap", 0);
+  if (state->ptp_socket < 0)
+  {
+      ptperr("Failed to create tx socket: %d\n", errno);
+      return ERROR;
+  }
+
+  // Set Ethernet interface on which to get raw frames
+  if (ioctl(state->ptp_socket, L2TAP_S_INTF_DEVICE, interface) < 0)
+  {
+    ptperr("failed to set network interface at socket: %d\n", errno);
+    return ERROR;
+  }
+
+  // Set the Ethertype filter (frames with this type will be available through the state->tx_socket)
+  uint16_t eth_type_filter = ETH_TYPE_PTP;
+  if (ioctl(state->ptp_socket, L2TAP_S_RCV_FILTER, &eth_type_filter) < 0)
+  {
+    ptperr("failed to set Ethertype filter: %d\n", errno);
+    return ERROR;
+  }
+  // Enable time stamping in driver
+  esp_eth_handle_t eth_handle;
+  if (ioctl(state->ptp_socket, L2TAP_G_DEVICE_DRV_HNDL, &eth_handle) < 0)
+  {
+    ptperr("failed to get socket eth_handle %d\n", errno);
+    return ERROR;
+  }
+  esp_eth_clock_cfg_t clk_cfg = {
+    .eth_hndl = eth_handle,
+  };
+  esp_eth_clock_init(CLOCK_PTP_SYSTEM, &clk_cfg);
+
+  // Enable time stamping in L2TAP
+  if(ioctl(state->ptp_socket, L2TAP_S_TIMESTAMP_EN) < 0)
+  {
+    ptperr("failed to enable time stamping in l2 socket: %d\n", errno);
+    return ERROR;
+  }
+
+  // get HW address
+  esp_eth_ioctl(eth_handle, ETH_CMD_G_MAC_ADDR, &state->intf_hw_addr);
+
+  state->remote_time_ns_prev = 0;
+  state->local_time_ns_prev = 0;
+
+  state->offset_pi.kp = 1;
+  state->offset_pi.ki = 10;
+  state->offset_pi.drift_acc = 0;
+
+  state->own_identity.header.version = 2;
+  state->own_identity.header.domain = CONFIG_NETUTILS_PTPD_DOMAIN;
+  state->own_identity.header.sourceidentity[0] = state->intf_hw_addr[0];
+  state->own_identity.header.sourceidentity[1] = state->intf_hw_addr[1];
+  state->own_identity.header.sourceidentity[2] = state->intf_hw_addr[2];
+  state->own_identity.header.sourceidentity[3] = 0xff;
+  state->own_identity.header.sourceidentity[4] = 0xfe;
+  state->own_identity.header.sourceidentity[5] = state->intf_hw_addr[3];
+  state->own_identity.header.sourceidentity[6] = state->intf_hw_addr[4];
+  state->own_identity.header.sourceidentity[7] = state->intf_hw_addr[5];
+  state->own_identity.header.sourceportindex[0] = 0;
+  state->own_identity.header.sourceportindex[1] = 1;
+#ifdef CONFIG_NETUTILS_PTPD_SERVER
+  state->own_identity.gm_priority1 = CONFIG_NETUTILS_PTPD_PRIORITY1;
+  state->own_identity.gm_quality[0] = CONFIG_NETUTILS_PTPD_CLASS;
+  state->own_identity.gm_quality[1] = CONFIG_NETUTILS_PTPD_ACCURACY;
+  state->own_identity.gm_quality[2] = 0xff; /* No variance estimate */
+  state->own_identity.gm_quality[3] = 0xff;
+  state->own_identity.gm_priority2 = CONFIG_NETUTILS_PTPD_PRIORITY2;
+  memcpy(state->own_identity.gm_identity,
+         state->own_identity.header.sourceidentity,
+         sizeof(state->own_identity.gm_identity));
+  state->own_identity.timesource = CONFIG_NETUTILS_PTPD_CLOCKSOURCE;
+#else
+  state->own_identity.gm_priority1 = 255; // When daemon is statically configured as slave, set the worst
+#endif
+
+  s_state = state;
+  return OK;
+}
+#else
+static int ptp_initialize_state(FAR struct ptp_state_s *state,
+                                FAR const char *interface)
+{
+  int ret;
+  struct ifreq req;
+  struct sockaddr_in bind_addr;
+
+#ifdef CONFIG_NET_TIMESTAMP
+  int arg;
+#endif
+
+  /* Create sockets */
+
+  state->tx_socket = socket(AF_INET, SOCK_DGRAM, 0);
+  if (state->tx_socket < 0)
+    {
+      ptperr("Failed to create tx socket: %d\n", errno);
+      return ERROR;
+    }
+
+  state->event_socket = socket(AF_INET, SOCK_DGRAM, 0);
+  if (state->event_socket < 0)
+    {
+      ptperr("Failed to create event socket: %d\n", errno);
+      return ERROR;
+    }
+
+
+  state->info_socket = socket(AF_INET, SOCK_DGRAM, 0);
+  if (state->info_socket < 0)
+    {
+      ptperr("Failed to create info socket: %d\n", errno);
+      return ERROR;
+    }
+
+  /* Get address information of the specified interface for binding socket
+   * Only supports IPv4 currently.
+   */
+
+  memset(&req, 0, sizeof(req));
+  strncpy(req.ifr_name, interface, sizeof(req.ifr_name));
+
+  if (ioctl(state->event_socket, SIOCGIFADDR, (unsigned long)&req) < 0)
+    {
+      ptperr("Failed to get IP address information for interface %s\n",
+             interface);
+      return ERROR;
+    }
+
+  state->interface_addr = *(struct sockaddr_in *)&req.ifr_ifru.ifru_addr;
+
+  /* Get hardware address to initialize the identity field in header.
+   * Clock identity is EUI-64, which we make from EUI-48.
+   */
+
+  if (ioctl(state->event_socket, SIOCGIFHWADDR, (unsigned long)&req) < 0)
+    {
+      ptperr("Failed to get HW address information for interface %s\n",
+             interface);
+      return ERROR;
+    }
+
+  state->own_identity.header.version = 2;
+  state->own_identity.header.domain = CONFIG_NETUTILS_PTPD_DOMAIN;
+  state->own_identity.header.sourceidentity[0] = req.ifr_hwaddr.sa_data[0];
+  state->own_identity.header.sourceidentity[1] = req.ifr_hwaddr.sa_data[1];
+  state->own_identity.header.sourceidentity[2] = req.ifr_hwaddr.sa_data[2];
+  state->own_identity.header.sourceidentity[3] = 0xff;
+  state->own_identity.header.sourceidentity[4] = 0xfe;
+  state->own_identity.header.sourceidentity[5] = req.ifr_hwaddr.sa_data[3];
+  state->own_identity.header.sourceidentity[6] = req.ifr_hwaddr.sa_data[4];
+  state->own_identity.header.sourceidentity[7] = req.ifr_hwaddr.sa_data[5];
+  state->own_identity.header.sourceportindex[0] = 0;
+  state->own_identity.header.sourceportindex[1] = 1;
+  state->own_identity.gm_priority1 = CONFIG_NETUTILS_PTPD_PRIORITY1;
+  state->own_identity.gm_quality[0] = CONFIG_NETUTILS_PTPD_CLASS;
+  state->own_identity.gm_quality[1] = CONFIG_NETUTILS_PTPD_ACCURACY;
+  state->own_identity.gm_quality[2] = 0xff; /* No variance estimate */
+  state->own_identity.gm_quality[3] = 0xff;
+  state->own_identity.gm_priority2 = CONFIG_NETUTILS_PTPD_PRIORITY2;
+  memcpy(state->own_identity.gm_identity,
+         state->own_identity.header.sourceidentity,
+         sizeof(state->own_identity.gm_identity));
+  state->own_identity.timesource = CONFIG_NETUTILS_PTPD_CLOCKSOURCE;
+
+  /* Subscribe to PTP multicast address */
+
+  bind_addr.sin_family = AF_INET;
+  bind_addr.sin_addr.s_addr = HTONL(PTP_MULTICAST_ADDR);
+
+  clock_gettime(CLOCK_MONOTONIC, &state->last_received_multicast);
+
+  ret = ipmsfilter(&state->interface_addr.sin_addr,
+                   &bind_addr.sin_addr,
+                   MCAST_INCLUDE);
+  if (ret < 0)
+    {
+      ptperr("Failed to bind multicast address: %d\n", errno);
+      return ERROR;
+    }
+
+  /* Bind socket for events */
+
+  bind_addr.sin_port = HTONS(PTP_UDP_PORT_EVENT);
+  ret = bind(state->event_socket, (struct sockaddr *)&bind_addr,
+             sizeof(bind_addr));
+  if (ret < 0)
+    {
+      ptperr("Failed to bind to udp port %d\n", bind_addr.sin_port);
+      return ERROR;
+    }
+
+#ifdef CONFIG_NET_TIMESTAMP
+  arg = 1;
+  ret = setsockopt(state->event_socket, SOL_SOCKET, SO_TIMESTAMP,
+                   &arg, sizeof(arg));
+
+  if (ret < 0)
+    {
+      ptperr("Failed to enable SO_TIMESTAMP: %s\n", strerror(errno));
+
+      /* PTPD can operate without, but with worse accuracy */
+    }
+#endif
+
+  /* Bind socket for announcements */
+
+  bind_addr.sin_port = HTONS(PTP_UDP_PORT_INFO);
+  ret = bind(state->info_socket, (struct sockaddr *)&bind_addr,
+             sizeof(bind_addr));
+  if (ret < 0)
+    {
+      ptperr("Failed to bind to udp port %d\n", bind_addr.sin_port);
+      return ERROR;
+    }
+
+  /* Bind TX socket to interface address (local addr cannot be multicast) */
+
+  bind_addr.sin_addr = state->interface_addr.sin_addr;
+  ret = bind(state->tx_socket, (struct sockaddr *)&bind_addr,
+             sizeof(bind_addr));
+  if (ret < 0)
+    {
+      ptperr("Failed to bind tx to port %d\n", bind_addr.sin_port);
+      return ERROR;
+    }
+
+  return OK;
+}
+#endif // ESP_PTP
+
+/* Unsubscribe multicast and destroy sockets */
+
+static int ptp_destroy_state(FAR struct ptp_state_s *state)
+{
+#ifdef ESP_PTP
+  if (state->ptp_socket > 0)
+  {
+    close(state->ptp_socket);
+    state->ptp_socket = -1;
+  }
+#else
+  struct in_addr mcast_addr;
+
+  mcast_addr.s_addr = HTONL(PTP_MULTICAST_ADDR);
+  ipmsfilter(&state->interface_addr.sin_addr,
+              &mcast_addr,
+              MCAST_EXCLUDE);
+
+  if (state->tx_socket > 0)
+    {
+      close(state->tx_socket);
+      state->tx_socket = -1;
+    }
+
+  if (state->event_socket > 0)
+    {
+      close(state->event_socket);
+      state->event_socket = -1;
+    }
+
+  if (state->info_socket > 0)
+    {
+      close(state->info_socket);
+      state->info_socket = -1;
+    }
+#endif // ESP_PTP
+  return OK;
+}
+
+#ifndef ESP_PTP
+/* Re-subscribe multicast address.
+ * This can become necessary if Ethernet interface gets reset or if external
+ * IGMP-compliant Ethernet switch gets plugged in.
+ */
+
+static int ptp_check_multicast_status(FAR struct ptp_state_s *state)
+{
+#if CONFIG_NETUTILS_PTPD_MULTICAST_TIMEOUT_MS > 0
+  struct in_addr mcast_addr;
+  struct timespec time_now;
+  struct timespec delta;
+
+  clock_gettime(CLOCK_MONOTONIC, &time_now);
+  clock_timespec_subtract(&time_now, &state->last_received_multicast,
+                          &delta);
+
+  if (timespec_to_ms(&delta) > CONFIG_NETUTILS_PTPD_MULTICAST_TIMEOUT_MS)
+    {
+      /* Remove and re-add the multicast group */
+
+      state->last_received_multicast = time_now;
+
+      mcast_addr.s_addr = HTONL(PTP_MULTICAST_ADDR);
+      ipmsfilter(&state->interface_addr.sin_addr,
+                 &mcast_addr,
+                 MCAST_EXCLUDE);
+
+      return ipmsfilter(&state->interface_addr.sin_addr,
+                        &mcast_addr,
+                        MCAST_INCLUDE);
+    }
+
+#else
+  UNUSED(state);
+#endif /* CONFIG_NETUTILS_PTPD_MULTICAST_TIMEOUT_MS */
+
+  return OK;
+}
+#endif // !ESP_PTP
+
+/* Send PTP server announcement packet */
+
+static int ptp_send_announce(FAR struct ptp_state_s *state)
+{
+  struct ptp_announce_s msg;
+#ifndef ESP_PTP
+  struct sockaddr_in addr;
+#endif // !ESP_PTP
+  struct timespec ts;
+  int ret;
+
+#ifndef ESP_PTP
+  addr.sin_family      = AF_INET;
+  addr.sin_addr.s_addr = HTONL(PTP_MULTICAST_ADDR);
+  addr.sin_port        = HTONS(PTP_UDP_PORT_INFO);
+#endif // !ESP_PTP
+
+  memset(&msg, 0, sizeof(msg));
+  msg = state->own_identity;
+  msg.header.messagetype = PTP_MSGTYPE_ANNOUNCE;
+  msg.header.messagelength[1] = sizeof(msg);
+
+  ptp_increment_sequence(&state->announce_seq, &msg.header);
+  ptp_gettime(state, &ts);
+  timespec_to_ptp_format(&ts, msg.origintimestamp);
+
+#ifdef ESP_PTP
+  ret = ptp_net_send(state, &msg, sizeof(msg), NULL);
+#else
+  ret = sendto(state->tx_socket, &msg, sizeof(msg), 0,
+    (struct sockaddr *)&addr, sizeof(addr));
+#endif // ESP_PTP
+
+  if (ret < 0)
+    {
+      ptperr("sendto failed: %d", errno);
+    }
+  else
+    {
+      ptpinfo("Sent announce, seq %ld\n",
+              (long)ptp_get_sequence(&msg.header));
+    }
+
+  return ret;
+}
+
+/* Send PTP server synchronization packet */
+
+static int ptp_send_sync(FAR struct ptp_state_s *state)
+{
+#ifndef ESP_PTP
+  struct msghdr txhdr;
+  struct iovec txiov;
+#endif // !ESP_PTP
+  struct ptp_sync_s msg;
+#ifndef ESP_PTP
+  struct sockaddr_in addr;
+#endif // !ESP_PTP
+  struct timespec ts;
+#ifndef ESP_PTP
+  uint8_t controlbuf[64];
+#endif // !ESP_PTP
+  int ret;
+
+#ifndef ESP_PTP
+  memset(&txhdr, 0, sizeof(txhdr));
+  memset(&txiov, 0, sizeof(txiov));
+
+  addr.sin_family      = AF_INET;
+  addr.sin_addr.s_addr = HTONL(PTP_MULTICAST_ADDR);
+  addr.sin_port        = HTONS(PTP_UDP_PORT_EVENT);
+#endif // !ESP_PTP
+
+  memset(&msg, 0, sizeof(msg));
+  msg.header = state->own_identity.header;
+  msg.header.messagetype = PTP_MSGTYPE_SYNC;
+  msg.header.messagelength[1] = sizeof(msg);
+
+#ifdef CONFIG_NETUTILS_PTPD_TWOSTEP_SYNC
+  msg.header.flags[0] = PTP_FLAGS0_TWOSTEP;
+#endif
+
+#ifndef ESP_PTP
+  txhdr.msg_name = &addr;
+  txhdr.msg_namelen = sizeof(addr);
+  txhdr.msg_iov = &txiov;
+  txhdr.msg_iovlen = 1;
+  txhdr.msg_control = controlbuf;
+  txhdr.msg_controllen = sizeof(controlbuf);
+  txiov.iov_base = &msg;
+  txiov.iov_len = sizeof(msg);
+#endif //!ESP_PTP
+
+  /* Timestamp and send the sync message */
+
+  ptp_increment_sequence(&state->sync_seq, &msg.header);
+  ptp_gettime(state, &ts);
+  timespec_to_ptp_format(&ts, msg.origintimestamp);
+
+#ifdef ESP_PTP
+  ret = ptp_net_send(state, &msg, sizeof(msg), &ts);
+#else
+  ret = sendmsg(state->tx_socket, &txhdr, 0);
+#endif // ESP_PTP
+  if (ret < 0)
+    {
+      ptperr("sendmsg for sync message failed: %d\n", errno);
+      return ret;
+    }
+
+#ifdef CONFIG_NETUTILS_PTPD_TWOSTEP_SYNC
+#ifndef ESP_PTP
+  /* Get timestamp after send completes and send follow-up message
+   *
+   * TODO: Implement SO_TIMESTAMPING and use the actual tx timestamp here.
+   */
+
+  ptp_gettime(state, &ts);
+#endif // !ESP_PTP
+  timespec_to_ptp_format(&ts, msg.origintimestamp);
+  msg.header.messagetype = PTP_MSGTYPE_FOLLOW_UP;
+  msg.header.flags[0] = 0;
+#ifndef ESP_PTP
+  addr.sin_port = HTONS(PTP_UDP_PORT_INFO);
+
+  ret = sendto(state->tx_socket, &msg, sizeof(msg), 0,
+               (struct sockaddr *)&addr, sizeof(addr));
+#else
+  ret = ptp_net_send(state, &msg, sizeof(msg), NULL);
+#endif // !ESP_PTP
+  if (ret < 0)
+    {
+      ptperr("sendto for follow-up message failed: %d\n", errno);
+      return ret;
+    }
+
+  ptpinfo("Sent sync + follow-up, seq %ld\n",
+          (long)ptp_get_sequence(&msg.header));
+#else
+  ptpinfo("Sent sync, seq %ld\n",
+          (long)ptp_get_sequence(&msg.header));
+#endif /* CONFIG_NETUTILS_PTPD_TWOSTEP_SYNC */
+
+  return OK;
+}
+
+/* Send delay request packet to selected source */
+
+static int ptp_send_delay_req(FAR struct ptp_state_s *state)
+{
+  struct ptp_delay_req_s req;
+#ifndef ESP_PTP
+  struct sockaddr_in addr;
+#endif // !ESP_PTP
+  int ret;
+
+#ifndef ESP_PTP
+  addr.sin_family      = AF_INET;
+  addr.sin_addr.s_addr = HTONL(PTP_MULTICAST_ADDR);
+  addr.sin_port        = HTONS(PTP_UDP_PORT_EVENT);
+#endif // !ESP_PTP
+
+  memset(&req, 0, sizeof(req));
+  req.header = state->own_identity.header;
+  req.header.messagetype = PTP_MSGTYPE_DELAY_REQ;
+  req.header.messagelength[1] = sizeof(req);
+  ptp_increment_sequence(&state->delay_req_seq, &req.header);
+
+  ptp_gettime(state, &state->delayreq_time);
+  timespec_to_ptp_format(&state->delayreq_time, req.origintimestamp);
+
+#ifdef ESP_PTP
+  ret = ptp_net_send(state, &req, sizeof(req), &state->delayreq_time);
+#else
+  ret = sendto(state->tx_socket, &req, sizeof(req), 0,
+               (FAR struct sockaddr *)&addr, sizeof(addr));
+#endif // ESP_PTP
+
+#ifndef ESP_PTP
+  /* Get timestamp after send completes.
+   * TODO: Implement SO_TIMESTAMPING and use the actual tx timestamp here.
+   */
+
+  ptp_gettime(state, &state->delayreq_time);
+#endif // !ESP_PTP
+
+  if (ret < 0)
+    {
+      ptperr("sendto failed: %d", errno);
+    }
+  else
+    {
+      clock_gettime(CLOCK_MONOTONIC, &state->last_transmitted_delayreq);
+      ptpinfo("Sent delay req, seq %ld\n",
+              (long)ptp_get_sequence(&req.header));
+    }
+
+  return ret;
+}
+
+/* Check if we need to send packets */
+
+static int ptp_periodic_send(FAR struct ptp_state_s *state)
+{
+#ifdef CONFIG_NETUTILS_PTPD_SERVER
+  /* If there is no better master clock on the network,
+   * act as the reference source and send server packets.
+   */
+
+  if (!state->selected_source_valid)
+    {
+      struct timespec time_now;
+      struct timespec delta;
+
+      clock_gettime(CLOCK_MONOTONIC, &time_now);
+      clock_timespec_subtract(&time_now,
+        &state->last_transmitted_announce, &delta);
+      if (timespec_to_ms(&delta)
+          > CONFIG_NETUTILS_PTPD_ANNOUNCE_INTERVAL_MSEC)
+        {
+          state->last_transmitted_announce = time_now;
+          ptp_send_announce(state);
+        }
+
+      clock_timespec_subtract(&time_now,
+        &state->last_transmitted_sync, &delta);
+      if (timespec_to_ms(&delta) > CONFIG_NETUTILS_PTPD_SYNC_INTERVAL_MSEC)
+        {
+          state->last_transmitted_sync = time_now;
+          ptp_send_sync(state);
+        }
+    }
+#endif /* CONFIG_NETUTILS_PTPD_SERVER */
+
+#ifdef CONFIG_NETUTILS_PTPD_SEND_DELAYREQ
+  if (state->selected_source_valid && state->can_send_delayreq)
+    {
+      struct timespec time_now;
+      struct timespec delta;
+
+      clock_gettime(CLOCK_MONOTONIC, &time_now);
+      clock_timespec_subtract(&time_now,
+                              &state->last_transmitted_delayreq, &delta);
+
+      if (timespec_to_ms(&delta) > state->delayreq_interval * MSEC_PER_SEC)
+        {
+          ptp_send_delay_req(state);
+        }
+    }
+#endif
+
+  return OK;
+}
+
+/* Process received PTP announcement */
+
+static int ptp_process_announce(FAR struct ptp_state_s *state,
+                                FAR struct ptp_announce_s *msg)
+{
+  clock_gettime(CLOCK_MONOTONIC, &state->last_received_announce);
+
+  if (is_better_clock(msg, &state->own_identity))
+    {
+      if (!state->selected_source_valid ||
+          is_better_clock(msg, &state->selected_source))
+        {
+          ptpinfo("Switching to better PTP time source\n");
+
+          state->selected_source = *msg;
+          state->last_received_sync = state->last_received_announce;
+          state->path_delay_avgcount = 0;
+          state->path_delay_ns = 0;
+          state->delayreq_time.tv_sec = 0;
+        }
+    }
+
+  return OK;
+}
+
+#ifdef ESP_PTP
+static void ptp_lock_local_clock_freq(FAR struct ptp_state_s *state,
+                                  FAR struct timespec *remote_timestamp,
+                                  FAR struct timespec *local_timestamp)
+{
+  // Compute how off we are against master
+  int64_t offset_ns = timespec_delta_ns(remote_timestamp, local_timestamp);
+  offset_ns += state->path_delay_ns;
+  // TODO add offset filter
+
+  // Execute PI controller to elimitate the offset
+  // compute I component
+  state->offset_pi.drift_acc += offset_ns / state->offset_pi.ki;
+  // clamp the accumulator to ADJ_FREQ_MAX for sanity
+  if (state->offset_pi.drift_acc > ADJ_FREQ_MAX){
+    state->offset_pi.drift_acc = ADJ_FREQ_MAX;
+  } else if (state->offset_pi.drift_acc < -ADJ_FREQ_MAX) {
+    state->offset_pi.drift_acc = -ADJ_FREQ_MAX;
+  }
+  // compute P component and the whole controller
+  int32_t adj = offset_ns / state->offset_pi.kp + state->offset_pi.drift_acc;
+
+  // Compute difference between number of ticks in slave and master over sync period. This is used to lock the frequency with the master.
+  // However, it never catch-up the offset by itself, hence also add `adj` at the end
+  int64_t remote_time_ns = timespec_to_ns(remote_timestamp);
+  int64_t local_time_ns = timespec_to_ns(local_timestamp);
+  int64_t remote_delta_ns = remote_time_ns - state->remote_time_ns_prev;
+  int64_t local_delta_ns = local_time_ns - state->local_time_ns_prev;
+  // clock tick difference between master and slave
+  int64_t tick_diff = remote_delta_ns - local_delta_ns;
+
+  // compute how to scale the slave frequency to lock with master frequency and also try to catch-up the offset
+  double freq_scale = ((double)(remote_delta_ns /*+ tick_diff*/ + adj)) / (double)local_delta_ns;
+  esp_eth_clock_adj_param_t clk_adj_param = {
+    .mode = ETH_CLK_ADJ_FREQ_SCALE,
+    .freq_scale = freq_scale
+  };
+  esp_eth_clock_adjtime(CLOCK_PTP_SYSTEM, &clk_adj_param);
+
+  state->remote_time_ns_prev = remote_time_ns;
+  state->local_time_ns_prev = local_time_ns;
+
+  ptpinfo("remote_delta_ns %lli, local_delta_ns %lli, tick_diff %lli\n", remote_delta_ns, local_delta_ns, tick_diff);
+  ptpinfo("offset_ns %lli, adj %li, drift_acc %li\n", offset_ns, adj, state->offset_pi.drift_acc);
+
+  // Get the path delay only when clock is stable enough. If we were in process of adjustion (speeding/slowing slave),
+  // we would get incorrect delay
+  int64_t diff = llabs(offset_ns) - llabs(state->last_offset_ns);
+  static int cnt = 0;
+  if (llabs(diff) < CONFIG_NETUTILS_PTPD_PATH_DELAY_STABILITY_NS) {
+    if (cnt <= 3)
+      cnt++;
+  } else {
+    cnt = 0;
+  }
+  if (cnt > 3)
+  {
+    state->can_send_delayreq = true;
+  }
+  state->last_offset_ns = offset_ns;
+}
+
+void ptp_clean_after_step(FAR struct ptp_state_s *state)
+{
+  state->remote_time_ns_prev = 0;
+  state->local_time_ns_prev = 0;
+
+  state->offset_pi.drift_acc = 0;
+  state->last_offset_ns = 0;
+}
+#endif // ESP_PTP
+
+/* Update local clock either by smooth adjustment or by jumping.
+ * Remote time was remote_timestamp at local_timestamp.
+ */
+
+static int ptp_update_local_clock(FAR struct ptp_state_s *state,
+                                  FAR struct timespec *remote_timestamp,
+                                  FAR struct timespec *local_timestamp)
+{
+  int ret = OK;
+  int64_t delta_ns;
+  int64_t absdelta_ns;
+  const int64_t adj_limit_ns = CONFIG_NETUTILS_PTPD_SETTIME_THRESHOLD_MS
+                               * (int64_t)NSEC_PER_MSEC;
+
+  ptpinfo("Local time: %lld.%09ld, remote time %lld.%09ld\n",
+          (long long)local_timestamp->tv_sec,
+          (long)local_timestamp->tv_nsec,
+          (long long)remote_timestamp->tv_sec,
+          (long)remote_timestamp->tv_nsec);
+
+  delta_ns = timespec_delta_ns(remote_timestamp, local_timestamp);
+  delta_ns += state->path_delay_ns;
+  absdelta_ns = (delta_ns < 0) ? -delta_ns : delta_ns;
+
+  if (absdelta_ns > adj_limit_ns)
+    {
+      /* Large difference, move by jumping.
+       * Account for delay since packet was received.
+       */
+
+      struct timespec new_time;
+      ptp_gettime(state, &new_time);
+      clock_timespec_subtract(&new_time, local_timestamp, &new_time);
+      clock_timespec_add(&new_time, remote_timestamp, &new_time);
+      ret = ptp_settime(state, &new_time);
+
+      /* Reinitialize drift adjustment parameters */
+
+      state->last_delta_timestamp = new_time;
+      state->last_delta_ns = 0;
+      state->last_adjtime_ns = 0;
+      state->drift_avg_total_ms = 0;
+      state->drift_ppb = 0;
+
+#ifdef ESP_PTP
+      ptp_clean_after_step(state);
+#endif // ESP_PTP
+
+      if (ret == OK)
+        {
+          ptpinfo("Jumped to timestamp %lld.%09ld s\n",
+                  (long long)new_time.tv_sec, (long)new_time.tv_nsec);
+        }
+      else
+        {
+          ptperr("ptp_settime() failed: %d\n", errno);
+        }
+    }
+  else
+    {
+#ifdef ESP_PTP
+	  ptp_lock_local_clock_freq(state, remote_timestamp, local_timestamp);
+#else
+      /* Track drift rate based on two consecutive measurements and
+       * the adjustment that was made previously.
+       */
+
+      int64_t drift_ppb;
+      struct timespec interval;
+      int interval_ms;
+      int max_avg_period_ms;
+      int64_t adjustment_ns;
+
+      clock_timespec_subtract(local_timestamp,
+                              &state->last_delta_timestamp,
+                              &interval);
+      interval_ms = timespec_to_ms(&interval);
+
+      if (interval_ms > 0 && interval_ms < CONFIG_NETUTILS_PTPD_TIMEOUT_MS)
+        {
+          drift_ppb = (delta_ns - state->last_delta_ns) * MSEC_PER_SEC
+                      / interval_ms;
+        }
+      else
+        {
+          ptpwarn("Measurement interval out of range: %d ms\n", interval_ms);
+          drift_ppb = 0;
+          interval_ms = 1;
+        }
+
+      /* Account for the adjustment previously made */
+
+      drift_ppb += state->last_adjtime_ns * MSEC_PER_SEC
+                  / CONFIG_CLOCK_ADJTIME_PERIOD_MS;
+
+      if (drift_ppb > CONFIG_CLOCK_ADJTIME_SLEWLIMIT_PPM * 1000 ||
+          drift_ppb < -CONFIG_CLOCK_ADJTIME_SLEWLIMIT_PPM * 1000)
+        {
+          ptpwarn("Drift estimate out of range: %lld\n",
+                  (long long)drift_ppb);
+          drift_ppb = state->drift_ppb;
+        }
+
+      /* Take direct average of drift estimate for first measurements,
+       * after that update the exponential sliding average.
+       * Measurements are weighted according to the interval, because
+       * drift estimate is more accurate over longer timespan.
+       */
+
+      state->drift_avg_total_ms += interval_ms;
+      max_avg_period_ms = CONFIG_NETUTILS_PTPD_DRIFT_AVERAGE_S
+                          * MSEC_PER_SEC;
+      if (state->drift_avg_total_ms > max_avg_period_ms)
+        {
+          state->drift_avg_total_ms = max_avg_period_ms;
+        }
+
+      state->drift_ppb += (drift_ppb - state->drift_ppb) * interval_ms
+                        / state->drift_avg_total_ms;
+
+      /* Compute the value we need to give to adjtime() to match the
+       * drift rate.
+       */
+
+      adjustment_ns = state->drift_ppb * CONFIG_CLOCK_ADJTIME_PERIOD_MS
+                      / MSEC_PER_SEC;
+
+      /* Drift estimation ensures local clock runs at same rate as remote.
+       *
+       * Adding the current clock offset to adjustment brings the clocks
+       * to match. To avoid individual outliers from causing jitter, we
+       * take the larger signed value of two previous deltas. This is based
+       * on the logic that packets can get delayed in transit, but do not
+       * travel backwards in time.
+       *
+       * Clock offset is applied over ADJTIME_PERIOD. If there is significant
+       * noise in measurements, increasing ADJTIME_PERIOD will reduce its
+       * effect on the local clock run rate.
+       */
+
+      if (state->last_delta_ns > delta_ns)
+        {
+          adjustment_ns += state->last_delta_ns;
+        }
+      else
+        {
+          adjustment_ns += delta_ns;
+        }
+
+      /* Apply adjustment and store information for next time */
+
+      state->last_delta_ns = delta_ns;
+      state->last_delta_timestamp = *local_timestamp;
+      state->last_adjtime_ns = adjustment_ns;
+
+      ptpinfo("Delta: %+lld ns, adjustment %+lld ns, drift rate %+lld ppb\n",
+              (long long)delta_ns,
+              (long long)state->last_adjtime_ns,
+              (long long)state->drift_ppb);
+
+      ret = ptp_adjtime(state, adjustment_ns);
+
+      if (ret != OK)
+        {
+          ptperr("ptp_adjtime() failed: %d\n", errno);
+        }
+
+      /* Check if clock is stable enough for sending delay requests */
+
+      if (absdelta_ns < CONFIG_NETUTILS_PTPD_MAX_PATH_DELAY_NS)
+        {
+          state->can_send_delayreq = true;
+        }
+#endif // ESP_PTP
+    }
+
+  return ret;
+}
+
+/* Process received PTP sync packet */
+
+static int ptp_process_sync(FAR struct ptp_state_s *state,
+                            FAR struct ptp_sync_s *msg)
+{
+  struct timespec remote_time;
+
+  if (memcmp(msg->header.sourceidentity,
+             state->selected_source.header.sourceidentity,
+             sizeof(msg->header.sourceidentity)) != 0)
+    {
+      /* This packet wasn't from the currently selected source */
+#ifdef ESP_PTP
+      ESP_LOGD(TAG, "This packet wasn't from the currently selected source");
+#endif // ESP_PTP
+      return OK;
+    }
+
+  /* Update timeout tracking */
+
+  clock_gettime(CLOCK_MONOTONIC, &state->last_received_sync);
+
+  if (msg->header.flags[0] & PTP_FLAGS0_TWOSTEP)
+    {
+      /* We need to wait for a follow-up packet before setting the clock. */
+
+      state->twostep_rxtime = state->rxtime;
+      state->twostep_packet = *msg;
+      ptpinfo("Waiting for follow-up\n");
+      return OK;
+    }
+
+  /* Update local clock */
+
+  ptp_format_to_timespec(msg->origintimestamp, &remote_time);
+  return ptp_update_local_clock(state, &remote_time, &state->rxtime);
+}
+
+static int ptp_process_followup(FAR struct ptp_state_s *state,
+                                FAR struct ptp_follow_up_s *msg)
+{
+  struct timespec remote_time;
+
+  if (memcmp(msg->header.sourceidentity,
+             state->twostep_packet.header.sourceidentity,
+             sizeof(msg->header.sourceidentity)) != 0)
+    {
+      return OK; /* This packet wasn't from the currently selected source */
+    }
+
+  if (ptp_get_sequence(&msg->header)
+      != ptp_get_sequence(&state->twostep_packet.header))
+    {
+      ptpwarn("PTP follow-up packet sequence %ld does not match initial "
+              "sync packet sequence %ld, ignoring\n",
+        (long)ptp_get_sequence(&msg->header),
+        (long)ptp_get_sequence(&state->twostep_packet.header));
+      return OK;
+    }
+
+  /* Update local clock based on the remote timestamp we received now
+   * and the local timestamp of when the sync packet was received.
+   */
+
+  ptp_format_to_timespec(msg->origintimestamp, &remote_time);
+  return ptp_update_local_clock(state, &remote_time, &state->twostep_rxtime);
+}
+
+static int ptp_process_delay_req(FAR struct ptp_state_s *state,
+                                 FAR struct ptp_delay_req_s *msg)
+{
+  struct ptp_delay_resp_s resp;
+#ifndef ESP_PTP
+  struct sockaddr_in addr;
+#endif // !ESP_PTP
+  int ret;
+
+  if (state->selected_source_valid)
+    {
+      /* We are operating as a client, ignore delay requests */
+
+      return OK;
+    }
+
+#ifndef ESP_PTP
+  addr.sin_family      = AF_INET;
+  addr.sin_addr.s_addr = HTONL(PTP_MULTICAST_ADDR);
+  addr.sin_port        = HTONS(PTP_UDP_PORT_INFO);
+#endif // !ESP_PTP
+
+  memset(&resp, 0, sizeof(resp));
+  resp.header = state->own_identity.header;
+  resp.header.messagetype = PTP_MSGTYPE_DELAY_RESP;
+  resp.header.messagelength[1] = sizeof(resp);
+  timespec_to_ptp_format(&state->rxtime, resp.receivetimestamp);
+  memcpy(resp.reqidentity, msg->header.sourceidentity,
+         sizeof(resp.reqidentity));
+  memcpy(resp.reqportindex, msg->header.sourceportindex,
+         sizeof(resp.reqportindex));
+  memcpy(resp.header.sequenceid, msg->header.sequenceid,
+         sizeof(resp.header.sequenceid));
+  resp.header.logmessageinterval = CONFIG_NETUTILS_PTPD_DELAYRESP_INTERVAL;
+
+#ifdef ESP_PTP
+  ret = ptp_net_send(state, &resp, sizeof(resp), NULL);
+#else
+  ret = sendto(state->tx_socket, &resp, sizeof(resp), 0,
+               (FAR struct sockaddr *)&addr, sizeof(addr));
+#endif // ESP_PTP
+
+  if (ret < 0)
+    {
+      ptperr("sendto failed: %d", errno);
+    }
+  else
+    {
+      clock_gettime(CLOCK_MONOTONIC, &state->last_transmitted_delayresp);
+      ptpinfo("Sent delay resp, seq %ld\n",
+              (long)ptp_get_sequence(&msg->header));
+    }
+
+  return ret;
+}
+
+static int ptp_process_delay_resp(FAR struct ptp_state_s *state,
+                                  FAR struct ptp_delay_resp_s *msg)
+{
+  int64_t path_delay;
+  int64_t sync_delay;
+  struct timespec remote_rxtime;
+  uint16_t sequence;
+  int interval;
+
+  if (!state->selected_source_valid ||
+      memcmp(msg->header.sourceidentity,
+             state->selected_source.header.sourceidentity,
+             sizeof(msg->header.sourceidentity)) != 0 ||
+      memcmp(msg->reqidentity,
+             state->own_identity.header.sourceidentity,
+             sizeof(msg->reqidentity)) != 0)
+    {
+      return OK; /* This packet wasn't for us */
+    }
+
+  sequence = ptp_get_sequence(&msg->header);
+
+  if (sequence != state->delay_req_seq)
+    {
+      ptpwarn("Ignoring out-of-sequence delay resp (%d vs. expected %d)\n",
+              (int)sequence, (int)state->delay_req_seq);
+      return OK;
+    }
+
+  /* Path delay is calculated as the average between delta for sync
+   * message and delta for delay req message.
+   * (IEEE-1588 section 11.3: Delay request-response mechanism)
+   */
+
+  ptp_format_to_timespec(msg->receivetimestamp, &remote_rxtime);
+  path_delay = timespec_delta_ns(&remote_rxtime, &state->delayreq_time);
+  sync_delay = state->path_delay_ns - state->last_delta_ns;
+  path_delay = (path_delay + sync_delay) / 2;
+
+  if (path_delay >= 0 && path_delay < CONFIG_NETUTILS_PTPD_MAX_PATH_DELAY_NS)
+    {
+      if (state->path_delay_avgcount <
+          CONFIG_NETUTILS_PTPD_DELAYREQ_AVGCOUNT)
+        {
+          state->path_delay_avgcount++;
+        }
+
+      state->path_delay_ns += (path_delay - state->path_delay_ns)
+                              / state->path_delay_avgcount;
+
+      ptpinfo("Path delay: %ld ns (avg: %ld ns)\n",
+        (long)path_delay, (long)state->path_delay_ns);
+    }
+  else
+    {
+      ptpwarn("Path delay out of range: %lld ns\n",
+              (long long)path_delay);
+    }
+
+  /* Calculate interval until next packet */
+
+  if (msg->header.logmessageinterval <= 12)
+    {
+      interval = (1 << msg->header.logmessageinterval);
+    }
+  else
+    {
+      interval = 4096; /* Refuse to obey excessively long intervals */
+    }
+
+  /* Randomize up to 2x nominal delay) */
+
+  state->delayreq_interval = interval + (random() % interval);
+
+  return OK;
+}
+
+/* Determine received packet type and process it */
+
+static int ptp_process_rx_packet(FAR struct ptp_state_s *state,
+                                 ssize_t length)
+{
+  if (length < sizeof(struct ptp_header_s))
+    {
+      ptpwarn("Ignoring invalid PTP packet, length only %d bytes\n",
+              (int)length);
+      return OK;
+    }
+
+  if (state->rxbuf.header.domain != CONFIG_NETUTILS_PTPD_DOMAIN)
+    {
+      /* Part of different clock domain, ignore */
+
+      return OK;
+    }
+
+  clock_gettime(CLOCK_MONOTONIC, &state->last_received_multicast);
+
+  switch (state->rxbuf.header.messagetype & PTP_MSGTYPE_MASK)
+  {
+#ifdef CONFIG_NETUTILS_PTPD_CLIENT
+    case PTP_MSGTYPE_ANNOUNCE:
+      ptpinfo("Got announce packet, seq %ld\n",
+              (long)ptp_get_sequence(&state->rxbuf.header));
+      return ptp_process_announce(state, &state->rxbuf.announce);
+
+    case PTP_MSGTYPE_SYNC:
+      ptpinfo("Got sync packet, seq %ld\n",
+              (long)ptp_get_sequence(&state->rxbuf.header));
+      return ptp_process_sync(state, &state->rxbuf.sync);
+
+    case PTP_MSGTYPE_FOLLOW_UP:
+      ptpinfo("Got follow-up packet, seq %ld\n",
+              (long)ptp_get_sequence(&state->rxbuf.header));
+      return ptp_process_followup(state, &state->rxbuf.follow_up);
+
+    case PTP_MSGTYPE_DELAY_RESP:
+      ptpinfo("Got delay-resp, seq %ld\n",
+              (long)ptp_get_sequence(&state->rxbuf.header));
+      return ptp_process_delay_resp(state, &state->rxbuf.delay_resp);
+#endif
+
+#ifdef CONFIG_NETUTILS_PTPD_SERVER
+    case PTP_MSGTYPE_DELAY_REQ:
+      ptpinfo("Got delay req, seq %ld\n",
+              (long)ptp_get_sequence(&state->rxbuf.header));
+      return ptp_process_delay_req(state, &state->rxbuf.delay_req);
+#endif
+
+    default:
+      ptpinfo("Ignoring unknown PTP packet type: 0x%02x\n",
+              state->rxbuf.header.messagetype);
+      return OK;
+  }
+}
+
+/* Signal handler for status / stop requests */
+#ifndef ESP_PTP
+static void ptp_signal_handler(int signo, FAR siginfo_t *siginfo,
+                               FAR void *context)
+{
+  FAR struct ptp_state_s *state = (FAR struct ptp_state_s *)siginfo->si_user;
+
+  if (signo == SIGHUP)
+    {
+      state->stop = true;
+    }
+  else if (signo == SIGUSR1 && siginfo->si_value.sival_ptr)
+    {
+      state->status_req =
+        *(FAR struct ptpd_statusreq_s *)siginfo->si_value.sival_ptr;
+    }
+}
+
+static void ptp_setup_sighandlers(FAR struct ptp_state_s *state)
+{
+  struct sigaction act;
+
+  act.sa_sigaction = ptp_signal_handler;
+  sigfillset(&act.sa_mask);
+  act.sa_flags = SA_SIGINFO;
+  act.sa_user = state;
+
+  sigaction(SIGHUP, &act, NULL);
+  sigaction(SIGUSR1, &act, NULL);
+}
+#endif // !ESP_PTP
+
+/* Process status information request */
+
+static void ptp_process_statusreq(FAR struct ptp_state_s *state)
+{
+  FAR struct ptpd_status_s *status;
+
+  if (!state->status_req.dest)
+    {
+      return; /* No active request */
+    }
+
+  status = state->status_req.dest;
+  status->clock_source_valid = state->selected_source_valid;
+
+  if (status->clock_source_valid)
+    {
+      /* Copy relevant parts of announce info to status struct */
+
+      FAR struct ptp_announce_s *s = &state->selected_source;
+
+      memcpy(status->clock_source_info.id,
+             s->header.sourceidentity,
+             sizeof(status->clock_source_info.id));
+
+      status->clock_source_info.utcoffset =
+          (int16_t)(((uint16_t)s->utcoffset[0] << 8) | s->utcoffset[1]);
+      status->clock_source_info.priority1 = s->gm_priority1;
+      status->clock_source_info.clockclass = s->gm_quality[0];
+      status->clock_source_info.accuracy = s->gm_quality[1];
+      status->clock_source_info.priority2 = s->gm_priority2;
+      status->clock_source_info.variance =
+          ((uint16_t)s->gm_quality[2] << 8) | s->gm_quality[3];
+
+      memcpy(status->clock_source_info.gm_id,
+             s->gm_identity,
+             sizeof(status->clock_source_info.gm_id));
+
+      status->clock_source_info.stepsremoved =
+          ((uint16_t)s->stepsremoved[0] << 8) | s->stepsremoved[1];
+      status->clock_source_info.timesource = s->timesource;
+    }
+
+  /* Copy latest adjustment info */
+
+  status->last_clock_update = state->last_delta_timestamp;
+  status->last_delta_ns     = state->last_delta_ns;
+  status->last_adjtime_ns   = state->last_adjtime_ns;
+  status->drift_ppb         = state->drift_ppb;
+  status->path_delay_ns     = state->path_delay_ns;
+
+  /* Copy timestamps */
+
+  status->last_received_multicast    = state->last_received_multicast;
+  status->last_received_announce     = state->last_received_announce;
+  status->last_received_sync         = state->last_received_sync;
+  status->last_transmitted_sync      = state->last_transmitted_sync;
+  status->last_transmitted_announce  = state->last_transmitted_announce;
+  status->last_transmitted_delayresp = state->last_transmitted_delayresp;
+  status->last_transmitted_delayreq  = state->last_transmitted_delayreq;
+
+  /* Post semaphore to inform that we are done */
+
+  if (state->status_req.done)
+    {
+      sem_post(state->status_req.done);
+    }
+
+  state->status_req.done = NULL;
+  state->status_req.dest = NULL;
+}
+
+/* Main PTPD task */
+#ifdef ESP_PTP
+static void ptp_daemon(void *task_param)
+#else
+static int ptp_daemon(int argc, FAR char** argv)
+#endif // ESP_PTP
+{
+  FAR const char *interface = "eth0";
+  FAR struct ptp_state_s *state;
+#ifdef ESP_PTP
+  struct pollfd pollfds[1]; // everything is received over one socket at L2
+#else
+  struct pollfd pollfds[2];
+  struct msghdr rxhdr;
+  struct iovec rxiov;
+#endif // ESP_PTP
+  int ret;
+
+#ifndef ESP_PTP
+  memset(&rxhdr, 0, sizeof(rxhdr));
+  memset(&rxiov, 0, sizeof(rxiov));
+#endif // !ESP_PTP
+
+  state = calloc(1, sizeof(struct ptp_state_s));
+
+#ifdef ESP_PTP
+  if (task_param != NULL)
+    {
+      interface = task_param;
+    }
+#else
+  if (argc > 1)
+    {
+      interface = argv[1];
+    }
+#endif // ESP_PTP
+
+  if (ptp_initialize_state(state, interface) != OK)
+    {
+      ptperr("Failed to initialize PTP state, exiting\n");
+
+      ptp_destroy_state(state);
+      free(state);
+
+#ifdef ESP_PTP
+      goto err;
+#else
+      return ERROR;
+#endif // ESP_PTP
+    }
+#ifndef ESP_PTP
+  ptp_setup_sighandlers(state);
+#endif // !ESP_PTP
+
+  pollfds[0].events = POLLIN;
+#ifdef ESP_PTP
+  pollfds[0].fd = state->ptp_socket;
+#else
+  pollfds[0].fd = state->event_socket;
+  pollfds[1].events = POLLIN;
+  pollfds[1].fd = state->info_socket;
+#endif // ESP_PTP
+
+  while (!state->stop)
+    {
+      state->can_send_delayreq = false;
+
+#ifndef ESP_PTP
+      rxhdr.msg_name = NULL;
+      rxhdr.msg_namelen = 0;
+      rxhdr.msg_iov = &rxiov;
+      rxhdr.msg_iovlen = 1;
+      rxhdr.msg_control = &state->rxcmsg;
+      rxhdr.msg_controllen = sizeof(state->rxcmsg);
+      rxhdr.msg_flags = 0;
+      rxiov.iov_base = &state->rxbuf;
+      rxiov.iov_len = sizeof(state->rxbuf);
+#endif // !ESP_PTP
+
+      pollfds[0].revents = 0;
+#ifndef ESP_PTP
+      pollfds[1].revents = 0;
+      ret = poll(pollfds, 2, PTPD_POLL_INTERVAL);
+#else
+	  ret = poll(pollfds, 1, PTPD_POLL_INTERVAL);
+#endif // !ESP_PTP
+
+      if (pollfds[0].revents)
+        {
+          /* Receive time-critical packet, potentially with cmsg
+           * indicating the timestamp.
+           */
+
+#ifdef ESP_PTP
+          ret = ptp_net_recv(state, &state->rxbuf, sizeof(state->rxbuf), &state->rxtime);
+#else
+          ret = recvmsg(state->event_socket, &rxhdr, MSG_DONTWAIT);
+#endif // ESP_PTP
+
+          if (ret > 0)
+            {
+#ifndef ESP_PTP
+              ptp_getrxtime(state, &rxhdr, &state->rxtime);
+#endif
+              ptp_process_rx_packet(state, ret);
+            }
+        }
+
+#ifndef ESP_PTP
+      if (pollfds[1].revents)
+        {
+          /* Receive non-time-critical packet. */
+
+          ret = recv(state->info_socket, &state->rxbuf, sizeof(state->rxbuf),
+                    MSG_DONTWAIT);
+          if (ret > 0)
+            {
+              ptp_process_rx_packet(state, ret);
+            }
+        }
+
+      if (pollfds[0].revents == 0 && pollfds[1].revents == 0)
+        {
+          /* No packets received, check for multicast timeout */
+
+          ptp_check_multicast_status(state);
+        }
+#endif // !ESP_PTP
+      ptp_periodic_send(state);
+
+      state->selected_source_valid = is_selected_source_valid(state);
+      ptp_process_statusreq(state);
+    }
+  ptp_destroy_state(state);
+  free(state);
+
+#ifdef ESP_PTP
+err:
+  s_state = NULL;
+  vTaskDelete(NULL);
+#else
+  return 0;
+#endif // ESP_PTP
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ptpd_start
+ *
+ * Description:
+ *   Start the PTP daemon and bind it to specified interface.
+ *
+ * Input Parameters:
+ *   interface - Name of the network interface to bind to, e.g. "eth0"
+ *
+ * Returned Value:
+ *   On success, the non-negative task ID of the PTP daemon is returned;
+ *   On failure, a negated errno value is returned.
+ *
+ ****************************************************************************/
+
+int ptpd_start(FAR const char *interface)
+{
+#ifdef ESP_PTP
+  if (s_state == NULL) {
+    xTaskCreate(ptp_daemon, "PTPD", CONFIG_NETUTILS_PTPD_STACKSIZE,
+              (void *)interface, tskIDLE_PRIORITY + 2, NULL);
+    return 1;
+  }
+  ESP_LOGE(TAG, "Other instance of PTP is already running");
+  return -1;
+#else
+  int pid;
+  FAR char *task_argv[] = {
+    (FAR char *)interface,
+    NULL
+  };
+
+  pid = task_create("PTPD", CONFIG_NETUTILS_PTPD_SERVERPRIO,
+    CONFIG_NETUTILS_PTPD_STACKSIZE, ptp_daemon, task_argv);
+
+  /* Use kill with signal 0 to check if the process is still alive
+   * after initialization.
+   */
+
+  usleep(USEC_PER_TICK);
+  if (kill(pid, 0) != OK)
+    {
+      return ERROR;
+    }
+  else
+    {
+      return pid;
+    }
+#endif // ESP_PTP
+}
+
+/****************************************************************************
+ * Name: ptpd_status
+ *
+ * Description:
+ *   Query status from a running PTP daemon.
+ *
+ * Input Parameters:
+ *   pid     - Process ID previously returned by ptpd_start()
+ *   status  - Pointer to storage for status information.
+ *
+ * Returned Value:
+ *   On success, returns OK.
+ *   On failure, a negated errno value is returned.
+ *
+ * Assumptions/Limitations:
+ *   Multiple threads with priority less than CONFIG_NETUTILS_PTPD_SERVERPRIO
+ *   can request status simultaneously. If higher priority threads request
+ *   status simultaneously, some of the requests may timeout.
+ *
+ ****************************************************************************/
+
+int ptpd_status(int pid, FAR struct ptpd_status_s *status)
+{
+#ifdef ESP_PTP
+  int ret = 0;
+  sem_t donesem;
+  struct ptpd_statusreq_s req;
+  struct timespec timeout;
+
+  /* Fill in the status request */
+
+  memset(status, 0, sizeof(struct ptpd_status_s));
+  sem_init(&donesem, 0, 0);
+  req.done = &donesem;
+  req.dest = status;
+
+  s_state->status_req = req;
+
+  /* Wait for status request to be handled */
+  clock_gettime(CLOCK_REALTIME, &timeout); // sem_timedwait uses CLOCK_REALTIME
+  timeout.tv_sec += 1;
+
+  if (sem_timedwait(&donesem, &timeout) != 0)
+    {
+      req.done = NULL;
+      req.dest = NULL;
+      s_state->status_req = req;
+      ret = -errno;
+    }
+  sem_destroy(&donesem);
+
+  return ret;
+#endif
+#ifndef CONFIG_BUILD_FLAT
+
+  /* TODO: Use SHM memory to pass the status information if processes
+   * do not share the same memory space.
+   */
+
+  return -ENOTSUP;
+
+#else
+
+  int ret = OK;
+  sem_t donesem;
+  struct ptpd_statusreq_s req;
+  union sigval val;
+  struct timespec timeout;
+
+  /* Fill in the status request */
+
+  memset(status, 0, sizeof(struct ptpd_status_s));
+  sem_init(&donesem, 0, 0);
+  req.done = &donesem;
+  req.dest = status;
+  val.sival_ptr = &req;
+
+  if (sigqueue(pid, SIGUSR1, val) != OK)
+    {
+      return -errno;
+    }
+
+  /* Wait for status request to be handled */
+
+  clock_gettime(CLOCK_MONOTONIC, &timeout);
+  timeout.tv_sec += 1;
+  if (sem_clockwait(&donesem, CLOCK_MONOTONIC, &timeout) != 0)
+    {
+      ret = -errno;
+    }
+
+  return ret;
+
+#endif /* CONFIG_BUILD_FLAT */
+}
+
+/****************************************************************************
+ * Name: ptpd_stop
+ *
+ * Description:
+ *   Stop PTP daemon
+ *
+ * Input Parameters:
+ *   pid     - Process ID previously returned by ptpd_start()
+ *
+ * Returned Value:
+ *   On success, returns OK.
+ *   On failure, a negated errno value is returned.
+ *
+ ****************************************************************************/
+
+int ptpd_stop(int pid)
+{
+#ifdef ESP_PTP
+  s_state->stop = true;
+  return OK;
+#else
+  if (kill(pid, SIGHUP) == OK)
+    {
+      return OK;
+    }
+  else
+    {
+      return -errno;
+    }
+#endif
+}
diff --git a/examples/ethernet/ptp/components/ptpd/ptpv2.h b/examples/ethernet/ptp/components/ptpd/ptpv2.h
new file mode 100644
index 00000000000..30cf527808a
--- /dev/null
+++ b/examples/ethernet/ptp/components/ptpd/ptpv2.h
@@ -0,0 +1,143 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 The Apache Software Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * SPDX-FileContributor: 2024 Espressif Systems (Shanghai) CO LTD
+ */
+
+/****************************************************************************
+ * apps/netutils/ptpd/ptpv2.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __APPS_NETUTILS_PTPD_PTPV2_H
+#define __APPS_NETUTILS_PTPD_PTPV2_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Time-critical messages (id < 8) are sent to port 319,
+ * other messages to port 320.
+ */
+
+#define PTP_UDP_PORT_EVENT 319
+#define PTP_UDP_PORT_INFO  320
+
+/* Multicast address to send to: 224.0.1.129 */
+
+#define PTP_MULTICAST_ADDR ((in_addr_t)0xE0000181)
+
+/* Message types */
+
+#define PTP_MSGTYPE_MASK       0x0F
+#define PTP_MSGTYPE_SYNC          0
+#define PTP_MSGTYPE_DELAY_REQ     1
+#define PTP_MSGTYPE_FOLLOW_UP     8
+#define PTP_MSGTYPE_DELAY_RESP    9
+#define PTP_MSGTYPE_ANNOUNCE     11
+
+/* Message flags */
+
+#define PTP_FLAGS0_TWOSTEP        (1 << 1)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* Defined in IEEE 1588-2008 Precision Time Protocol
+ * All multi-byte fields are big-endian.
+ */
+
+/* Common header for all message types */
+
+struct ptp_header_s
+{
+  uint8_t messagetype;
+  uint8_t version;
+  uint8_t messagelength[2];
+  uint8_t domain;
+  uint8_t reserved1;
+  uint8_t flags[2];
+  uint8_t correction[8];
+  uint8_t reserved2[4];
+  uint8_t sourceidentity[8];
+  uint8_t sourceportindex[2];
+  uint8_t sequenceid[2];
+  uint8_t controlfield;
+  uint8_t logmessageinterval;
+};
+
+/* Announce a master clock */
+
+struct ptp_announce_s
+{
+  struct ptp_header_s header;
+  uint8_t origintimestamp[10];
+  uint8_t utcoffset[2];
+  uint8_t reserved;
+  uint8_t gm_priority1;
+  uint8_t gm_quality[4];
+  uint8_t gm_priority2;
+  uint8_t gm_identity[8];
+  uint8_t stepsremoved[2];
+  uint8_t timesource;
+};
+
+/* Sync: transmit timestamp from master clock */
+
+struct ptp_sync_s
+{
+  struct ptp_header_s header;
+  uint8_t origintimestamp[10];
+};
+
+/* FollowUp: actual timestamp of when sync message was sent */
+
+struct ptp_follow_up_s
+{
+  struct ptp_header_s header;
+  uint8_t origintimestamp[10];
+};
+
+/* DelayReq: request delay measurement */
+
+struct ptp_delay_req_s
+{
+  struct ptp_header_s header;
+  uint8_t origintimestamp[10];
+};
+
+/* DelayResp: response to DelayReq */
+
+struct ptp_delay_resp_s
+{
+  struct ptp_header_s header;
+  uint8_t receivetimestamp[10];
+  uint8_t reqidentity[8];
+  uint8_t reqportindex[2];
+};
+
+#endif /* __APPS_NETUTILS_PTPD_PTPV2_H */
diff --git a/examples/ethernet/ptp/docs/sync_osc.jpg b/examples/ethernet/ptp/docs/sync_osc.jpg
new file mode 100644
index 00000000000..ee50715342a
Binary files /dev/null and b/examples/ethernet/ptp/docs/sync_osc.jpg differ
diff --git a/examples/ethernet/ptp/main/CMakeLists.txt b/examples/ethernet/ptp/main/CMakeLists.txt
new file mode 100644
index 00000000000..12891e07178
--- /dev/null
+++ b/examples/ethernet/ptp/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "ptp_main.c"
+                       INCLUDE_DIRS ".")
diff --git a/examples/ethernet/ptp/main/Kconfig.projbuild b/examples/ethernet/ptp/main/Kconfig.projbuild
new file mode 100644
index 00000000000..1fd46022daa
--- /dev/null
+++ b/examples/ethernet/ptp/main/Kconfig.projbuild
@@ -0,0 +1,22 @@
+menu "Example Configuration"
+
+    orsource "$IDF_PATH/examples/common_components/env_caps/$IDF_TARGET/Kconfig.env_caps"
+
+    config EXAMPLE_PTP_PULSE_GPIO
+        int "PPS GPIO number"
+        range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
+        default 20
+        help
+            Set the GPIO number at which the Pulse signal is outputted.
+
+    config EXAMPLE_PTP_PULSE_WIDTH_NS
+        int "Pulse width (ns)"
+        range 5000 999999999
+        default 500000000
+        help
+            Set pulse width in ns.
+            WARNING: Since the new pulse target time is set programmatically in the callback
+            function, width accuracy may vary or it may be lost completely when you select
+            very short pulse width.
+
+endmenu
diff --git a/examples/ethernet/ptp/main/idf_component.yml b/examples/ethernet/ptp/main/idf_component.yml
new file mode 100644
index 00000000000..cbf926ba807
--- /dev/null
+++ b/examples/ethernet/ptp/main/idf_component.yml
@@ -0,0 +1,7 @@
+dependencies:
+  ethernet_init:
+    path: ${IDF_PATH}/examples/ethernet/basic/components/ethernet_init
+  esp_eth_time:
+    path: ${IDF_PATH}/examples/ethernet/ptp/components/esp_eth_time
+  ptpd:
+    path: ${IDF_PATH}/examples/ethernet/ptp/components/ptpd
diff --git a/examples/ethernet/ptp/main/ptp_main.c b/examples/ethernet/ptp/main/ptp_main.c
new file mode 100644
index 00000000000..7954b17966a
--- /dev/null
+++ b/examples/ethernet/ptp/main/ptp_main.c
@@ -0,0 +1,150 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include <string.h>
+#include "sdkconfig.h"
+#include "esp_log.h"
+#include "esp_event.h"
+#include "esp_eth.h"
+#include "esp_netif.h"
+#include "ethernet_init.h"
+#include "esp_vfs_l2tap.h"
+#include "driver/gpio.h"
+#include "ptpd.h"
+
+#include "esp_eth_time.h"
+
+static const char *TAG = "ptp_example";
+
+static struct timespec s_next_time;
+static bool s_gpio_level;
+
+void init_ethernet_and_netif(void)
+{
+    uint8_t eth_port_cnt;
+    esp_eth_handle_t *eth_handles;
+
+    ESP_ERROR_CHECK(esp_event_loop_create_default());
+
+    ESP_ERROR_CHECK(example_eth_init(&eth_handles, &eth_port_cnt));
+
+    ESP_ERROR_CHECK(esp_netif_init());
+
+    ESP_ERROR_CHECK(esp_vfs_l2tap_intf_register(NULL));
+
+    esp_netif_inherent_config_t esp_netif_base_config = ESP_NETIF_INHERENT_DEFAULT_ETH();
+    esp_netif_config_t esp_netif_config = {
+        .base = &esp_netif_base_config,
+        .stack = ESP_NETIF_NETSTACK_DEFAULT_ETH
+    };
+    char if_key_str[10];
+    char if_desc_str[10];
+    char num_str[3];
+    for (int i = 0; i < eth_port_cnt; i++) {
+        itoa(i, num_str, 10);
+        strcat(strcpy(if_key_str, "ETH_"), num_str);
+        strcat(strcpy(if_desc_str, "eth"), num_str);
+        esp_netif_base_config.if_key = if_key_str;
+        esp_netif_base_config.if_desc = if_desc_str;
+        esp_netif_base_config.route_prio -= i*5;
+        esp_netif_t *eth_netif = esp_netif_new(&esp_netif_config);
+
+        // attach Ethernet driver to TCP/IP stack
+        ESP_ERROR_CHECK(esp_netif_attach(eth_netif, esp_eth_new_netif_glue(eth_handles[i])));
+    }
+
+    for (int i = 0; i < eth_port_cnt; i++) {
+        ESP_ERROR_CHECK(esp_eth_start(eth_handles[i]));
+    }
+}
+
+IRAM_ATTR bool ts_callback(esp_eth_mediator_t *eth, void *user_args)
+{
+    gpio_set_level(CONFIG_EXAMPLE_PTP_PULSE_GPIO, s_gpio_level ^= 1);
+
+    // Set the next target time
+    struct timespec interval = {
+        .tv_sec = 0,
+        .tv_nsec = CONFIG_EXAMPLE_PTP_PULSE_WIDTH_NS
+    };
+    timespecadd(&s_next_time, &interval, &s_next_time);
+
+    struct timespec curr_time;
+    esp_eth_clock_gettime(CLOCK_PTP_SYSTEM, &curr_time);
+    // check the next time is in the future
+    if (timespeccmp(&s_next_time, &curr_time, >)) {
+        esp_eth_clock_set_target_time(CLOCK_PTP_SYSTEM, &s_next_time);
+    }
+
+    return false;
+}
+
+void app_main(void)
+{
+    init_ethernet_and_netif();
+
+    int pid = ptpd_start("ETH_0");
+
+    struct timespec cur_time;
+    // wait for the clock to be available
+    while (esp_eth_clock_gettime(CLOCK_PTP_SYSTEM, &cur_time) == -1) {
+        vTaskDelay(pdMS_TO_TICKS(500));
+    }
+    // register callback function which will toggle output pin
+    esp_eth_clock_register_target_cb(CLOCK_PTP_SYSTEM, ts_callback);
+
+    // initialize output pin
+    gpio_config_t gpio_out_cfg = {
+        .pin_bit_mask = (1ULL << CONFIG_EXAMPLE_PTP_PULSE_GPIO),
+        .mode = GPIO_MODE_OUTPUT,
+        .pull_up_en = GPIO_PULLUP_DISABLE,
+        .pull_down_en = GPIO_PULLDOWN_DISABLE,
+        .intr_type = GPIO_INTR_DISABLE
+    };
+    gpio_config(&gpio_out_cfg);
+    gpio_set_level(CONFIG_EXAMPLE_PTP_PULSE_GPIO, 0);
+
+    bool first_pass = true;
+    bool clock_source_valid = false;
+    bool clock_source_valid_last = false;
+    int32_t clock_source_valid_cnt = 0;
+    while (1) {
+        struct ptpd_status_s ptp_status;
+        // if valid PTP status
+        if (ptpd_status(pid, &ptp_status) == 0) {
+            if (ptp_status.clock_source_valid) {
+                clock_source_valid_cnt++;
+            } else {
+                clock_source_valid_cnt = 0;
+            }
+        } else {
+            clock_source_valid_cnt = 0;
+        }
+        // consider the source valid only after n consequent intervals to be sure clock was synced
+        if (clock_source_valid_cnt > 2) {
+            clock_source_valid = true;
+        } else {
+            clock_source_valid = false;
+        }
+        // source validity changed => resync the pulse for ptp slave OR when the first pass to PTP master
+        // starts generating its pulses
+        if ((clock_source_valid == true && clock_source_valid_last == false) || first_pass) {
+            first_pass = false;
+            // get the most recent (now synced) time
+            esp_eth_clock_gettime(CLOCK_PTP_SYSTEM, &cur_time);
+            // compute the next target time
+            s_next_time.tv_sec = 1;
+            timespecadd(&s_next_time, &cur_time, &s_next_time);
+            s_next_time.tv_nsec = CONFIG_EXAMPLE_PTP_PULSE_WIDTH_NS;
+            ESP_LOGI(TAG, "Starting Pulse train");
+            ESP_LOGI(TAG, "curr time: %llu.%09lu", cur_time.tv_sec, cur_time.tv_nsec);
+            ESP_LOGI(TAG, "next time: %llu.%09lu", s_next_time.tv_sec, s_next_time.tv_nsec);
+            s_gpio_level = 0;
+            gpio_set_level(CONFIG_EXAMPLE_PTP_PULSE_GPIO, s_gpio_level);
+            esp_eth_clock_set_target_time(CLOCK_PTP_SYSTEM, &s_next_time);
+        }
+        clock_source_valid_last = clock_source_valid;
+    }
+}
diff --git a/examples/ethernet/ptp/sdkconfig.defaults b/examples/ethernet/ptp/sdkconfig.defaults
new file mode 100644
index 00000000000..0f922b58242
--- /dev/null
+++ b/examples/ethernet/ptp/sdkconfig.defaults
@@ -0,0 +1,10 @@
+CONFIG_IDF_TARGET="esp32p4"
+
+CONFIG_ESP_NETIF_L2_TAP=y
+
+CONFIG_EXAMPLE_USE_INTERNAL_ETHERNET=y
+CONFIG_EXAMPLE_ETH_PHY_IP101=y
+
+CONFIG_NETUTILS_PTPD=y
+CONFIG_NETUTILS_PTPD_CLIENT=y
+CONFIG_NETUTILS_PTPD_SERVER=y
diff --git a/examples/get-started/blink/sdkconfig.defaults.esp32p4 b/examples/get-started/blink/sdkconfig.defaults.esp32p4
new file mode 100644
index 00000000000..cc80f60a684
--- /dev/null
+++ b/examples/get-started/blink/sdkconfig.defaults.esp32p4
@@ -0,0 +1,2 @@
+CONFIG_BLINK_GPIO=44
+CONFIG_BLINK_LED_STRIP=y
diff --git a/examples/network/sta2eth/README.md b/examples/network/sta2eth/README.md
index 12e812d1f48..2665071dca3 100644
--- a/examples/network/sta2eth/README.md
+++ b/examples/network/sta2eth/README.md
@@ -12,6 +12,8 @@ This example aims to demonstrate 1-1 bridge using WiFi station and one of these
 It also allows for reconfiguring WiFi settings using a virtual network in the Ethernet. The reconfiguration mode is initialized if the WiFi settings are not available, connection fails or manually by long pressing the Boot button (GPIO0).
 It is possible to configure WiFi settings (SSID and password) in a browser on a hostname `"http://wifi.settings"` or using unified provisioning.
 
+Note: This page is intended solely for initial setup and is not recommended for production use, as it lacks any security measures—data is transmitted in plain text over HTTP. For secure, production-grade configuration, we recommend using the default option: unified provisioning.
+
 ## How to use example
 
 This example could be used to *bring* wireless connectivity to devices that support only Ethernet (or USB Ethernet implemented as NCM device).
diff --git a/examples/network/sta2eth/main/Kconfig.projbuild b/examples/network/sta2eth/main/Kconfig.projbuild
index 7b85896e38d..23e90de006b 100644
--- a/examples/network/sta2eth/main/Kconfig.projbuild
+++ b/examples/network/sta2eth/main/Kconfig.projbuild
@@ -4,7 +4,7 @@ menu "Example Configuration"
 
     choice EXAMPLE_WIFI_CONFIGURATION
         prompt "WiFi configuration"
-        default EXAMPLE_WIFI_CONFIGURATION_MANUAL
+        default EXAMPLE_WIFI_CONFIGURATION_PROVISIONING
         help
             Choose how the WiFi settings should be configured.
 
@@ -86,4 +86,26 @@ menu "Example Configuration"
             the reconfiguration mode, i.e. to restart provisioning
             or manual configuration of Wi-Fi settings (ssid, password)
 
+    if EXAMPLE_WIRED_INTERFACE_IS_ETHERNET
+
+        config EXAMPLE_MODIFY_DHCP_MESSAGES
+            bool "Modify DHCP messages"
+            default y
+            help
+                This is needed if the client uses 61 option and the DHCP server applies strict rules
+                on assigning addresses.
+                Set this to 'n' if you don't need DHCP or you're using simplified DHCP workflow
+                without HW address options in DHCP messages.
+
+        config EXAMPLE_ETHERNET_USE_PROMISCUOUS
+            bool "Enable promiscuous mode on Ethernet interface"
+            default n
+            help
+                Enable promiscuous mode on the Ethernet interface.
+                Note: Enabling promiscuous mode results in better throughput as MAC addresses
+                in frames are not rewritten with the Ethernet interface's actual MAC address.
+                Note: Enabling promiscuous mode may cause ARP conflicts if the PC
+                is also connected to the same network with another NIC.
+    endif
+
 endmenu
diff --git a/examples/network/sta2eth/main/ethernet_iface.c b/examples/network/sta2eth/main/ethernet_iface.c
index edc451a0c3f..c856a055376 100644
--- a/examples/network/sta2eth/main/ethernet_iface.c
+++ b/examples/network/sta2eth/main/ethernet_iface.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -20,13 +20,13 @@
  *  - this results in better throughput
  *  - might cause ARP conflicts if the PC is also connected to the same AP with another NIC
  */
-#define ETH_BRIDGE_PROMISCUOUS  0
+#define ETH_BRIDGE_PROMISCUOUS  CONFIG_EXAMPLE_ETHERNET_USE_PROMISCUOUS
 
 /**
  * Set this to 1 to runtime update HW addresses in DHCP messages
  * (this is needed if the client uses 61 option and the DHCP server applies strict rules on assigning addresses)
  */
-#define MODIFY_DHCP_MSGS        0
+#define MODIFY_DHCP_MSGS        CONFIG_EXAMPLE_MODIFY_DHCP_MESSAGES
 
 static const char *TAG = "example_wired_ethernet";
 static esp_eth_handle_t s_eth_handle = NULL;
@@ -49,7 +49,11 @@ void eth_event_handler(void *arg, esp_event_base_t event_base,
     switch (event_id) {
     case ETHERNET_EVENT_CONNECTED:
         ESP_LOGI(TAG, "Ethernet Link Up");
-        esp_netif_dhcps_start(netif);
+        if (netif) {
+            // Start DHCP server only if we "have" the actual netif (provisioning mode)
+            // (if netif==NULL we are only forwarding frames, no lwip involved)
+            esp_netif_dhcps_start(netif);
+        }
         esp_eth_ioctl(eth_handle, ETH_CMD_G_MAC_ADDR, mac_addr);
         ESP_LOGI(TAG, "Ethernet HW Addr %02x:%02x:%02x:%02x:%02x:%02x",
                  mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
@@ -57,7 +61,9 @@ void eth_event_handler(void *arg, esp_event_base_t event_base,
         break;
     case ETHERNET_EVENT_DISCONNECTED:
         ESP_LOGI(TAG, "Ethernet Link Down");
-        esp_netif_dhcps_stop(netif);
+        if (netif) {
+            esp_netif_dhcps_stop(netif);
+        }
         s_ethernet_is_connected = false;
         break;
     case ETHERNET_EVENT_START:
diff --git a/examples/network/sta2eth/main/manual_config.c b/examples/network/sta2eth/main/manual_config.c
index e95d041822a..ded7346c151 100644
--- a/examples/network/sta2eth/main/manual_config.c
+++ b/examples/network/sta2eth/main/manual_config.c
@@ -32,7 +32,8 @@ bool is_provisioned(void)
 
 static esp_err_t http_get_handler(httpd_req_t *req)
 {
-    const char page[] = "<form action=\"/\" method=\"get\"><br><br>\n"
+    const char page[] = "<h3>WARNING: Configuring Wi-Fi credentials on this page is not secure</h3>\n"
+                        "<form action=\"/\" method=\"get\"><br><br>\n"
                         "SSID:  <input type=\"text\" id=\"ssid\" name=\"ssid\"><br><br>\n"
                         "Password:  <input type=\"text\" id=\"password\" name=\"password\"><br><br>\n"
                         "  <input type=\"submit\" value=\"Connect\">"
diff --git a/examples/openthread/.build-test-rules.yml b/examples/openthread/.build-test-rules.yml
index ddd95daa389..9b109179895 100644
--- a/examples/openthread/.build-test-rules.yml
+++ b/examples/openthread/.build-test-rules.yml
@@ -59,3 +59,11 @@ examples/openthread/ot_sleepy_device/light_sleep:
       temporary: true
       reason: Not supported yet, TZ-958
   <<: [*openthread_dependencies, *openthread_sleep_dependencies]
+
+examples/openthread/ot_trel:
+  enable:
+    - if: SOC_WIFI_SUPPORTED == 1
+  disable_test:
+    - if: IDF_TARGET not in ["esp32c6", "esp32s3"]
+      reason: only test on esp32c6 and esp32s3
+  <<: *openthread_dependencies
diff --git a/examples/openthread/ot_ci_function.py b/examples/openthread/ot_ci_function.py
index 3561f4ad1d9..4793b7cb7d9 100644
--- a/examples/openthread/ot_ci_function.py
+++ b/examples/openthread/ot_ci_function.py
@@ -2,7 +2,6 @@
 # SPDX-License-Identifier: Unlicense OR CC0-1.0
 # !/usr/bin/env python3
 # this file defines some functions for testing cli and br under pytest framework
-
 import re
 import socket
 import struct
@@ -145,7 +144,7 @@ def changeDeviceRole(dut:IdfDut, role:str) -> None:
 def getDataset(dut:IdfDut) -> str:
     clean_buffer(dut)
     execute_command(dut, 'dataset active -x')
-    dut_data = dut.expect(r'\n(\w{212})\r', timeout=5)[1].decode()
+    dut_data = dut.expect(r'\n(\w+)\r', timeout=5)[1].decode()
     return str(dut_data)
 
 
diff --git a/examples/openthread/ot_trel/CMakeLists.txt b/examples/openthread/ot_trel/CMakeLists.txt
new file mode 100644
index 00000000000..b12d49bfa30
--- /dev/null
+++ b/examples/openthread/ot_trel/CMakeLists.txt
@@ -0,0 +1,6 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(esp_ot_cli)
diff --git a/examples/openthread/ot_trel/README.md b/examples/openthread/ot_trel/README.md
new file mode 100644
index 00000000000..5cc60dfa2f1
--- /dev/null
+++ b/examples/openthread/ot_trel/README.md
@@ -0,0 +1,133 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
+
+# Thread Radio Encapsulation Link Example
+
+This example demonstrates a Thread Radio Encapsulation Link (TREL) Example.
+
+## How to use example
+
+### Hardware Required
+
+To run this example, a board with Wi-Fi module (for example ESP32-S3) is required.
+
+### Configure the project
+
+```
+idf.py menuconfig
+```
+
+The Wi-Fi ssid and password should be set through the menuconfig:
+```
+Component config → → Example Connection Configuration → → WiFi SSID
+Component config → → Example Connection Configuration → → WiFi Password
+```
+
+The example can run with the default configuration. OpenThread Command Line is enabled with UART as the default interface. Additionally, USB JTAG is also supported and can be activated through the menuconfig:
+
+```
+Component config → ESP System Settings → Channel for console output → USB Serial/JTAG Controller
+```
+
+### Build, Flash, and Run
+
+Build the project and flash it to the board, then run monitor tool to view serial output:
+
+```
+idf.py build
+idf.py -p PORT erase-flash flash monitor
+```
+
+Now you'll get an OpenThread command line shell.
+
+### Example Output
+
+The `help` command will print all of the supported commands.
+```bash
+>  help
+I(7058) OPENTHREAD:[INFO]-CLI-----: execute command: help
+bbr
+bufferinfo
+ccathreshold
+channel
+child
+childip
+childmax
+childsupervision
+childtimeout
+coap
+contextreusedelay
+counters
+dataset
+delaytimermin
+diag
+discover
+dns
+domainname
+eidcache
+eui64
+extaddr
+extpanid
+factoryreset
+...
+```
+
+## Set Up Network
+
+To run this example, at least two ESP32-S3 boards flashed with this ot_trel example are required. And they must connect to the same wifi AP.
+
+On the first device, run the following commands:
+```bash
+> factoryreset
+... # the device will reboot
+
+> dataset init new
+Done
+> dataset commit active
+Done
+> ifconfig up
+Done
+> thread start
+Done
+
+# After some seconds
+
+> state
+leader
+Done
+```
+Now the first device has formed a Thread network as a leader. Get some information which will be used in next steps:
+```bash
+> ipaddr
+fdde:ad00:beef:0:0:ff:fe00:fc00
+fdde:ad00:beef:0:0:ff:fe00:8000
+fdde:ad00:beef:0:a7c6:6311:9c8c:271b
+fe80:0:0:0:5c27:a723:7115:c8f8
+
+# Get the Active Dataset
+> dataset active -x
+0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8
+```
+
+On the second device, set the active dataset from leader, and start Thread interface:
+```bash
+> factoryreset
+... # the device will reboot
+
+> dataset set active 0e080000000000010000000300001835060004001fffe00208fe7bb701f5f1125d0708fd75cbde7c6647bd0510b3914792d44f45b6c7d76eb9306eec94030f4f70656e5468726561642d35383332010258320410e35c581af5029b054fc904a24c2b27700c0402a0fff8
+> ifconfig up
+Done
+> thread start
+Done
+
+# After some seconds
+
+> state
+router  # child is also a valid state
+Done
+```
+The second device has joined the Thread network as a router (or a child).
+
+## Extension commands
+
+You can refer to the [extension command](https://github.com/espressif/esp-thread-br/blob/main/components/esp_ot_cli_extension/README.md) about the extension commands.
diff --git a/examples/openthread/ot_trel/main/CMakeLists.txt b/examples/openthread/ot_trel/main/CMakeLists.txt
new file mode 100644
index 00000000000..cea684e5f9f
--- /dev/null
+++ b/examples/openthread/ot_trel/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "esp_ot_trel.c"
+                       INCLUDE_DIRS ".")
diff --git a/examples/openthread/ot_trel/main/Kconfig.projbuild b/examples/openthread/ot_trel/main/Kconfig.projbuild
new file mode 100644
index 00000000000..7a37072f949
--- /dev/null
+++ b/examples/openthread/ot_trel/main/Kconfig.projbuild
@@ -0,0 +1,9 @@
+menu "OpenThread TREL Example"
+
+    config OPENTHREAD_AUTO_START
+        bool 'Enable the automatic start mode.'
+        default False
+        help
+            If enabled, the Openthread Device will create or connect to thread network with pre-configured
+            network parameters automatically. Otherwise, user need to configure Thread via CLI command manually.
+endmenu
diff --git a/examples/openthread/ot_trel/main/esp_ot_config.h b/examples/openthread/ot_trel/main/esp_ot_config.h
new file mode 100644
index 00000000000..be8eff0e21c
--- /dev/null
+++ b/examples/openthread/ot_trel/main/esp_ot_config.h
@@ -0,0 +1,58 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: CC0-1.0
+ *
+ * OpenThread Command Line Example
+ *
+ * This example code is in the Public Domain (or CC0 licensed, at your option.)
+ *
+ * Unless required by applicable law or agreed to in writing, this
+ * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied.
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+#include "esp_openthread_types.h"
+
+#define ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG()              \
+    {                                                      \
+        .radio_mode = RADIO_MODE_TREL,                     \
+    }
+
+#if CONFIG_OPENTHREAD_CONSOLE_TYPE_UART
+#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG()                    \
+    {                                                           \
+        .host_connection_mode = HOST_CONNECTION_MODE_CLI_UART,  \
+        .host_uart_config = {                                   \
+            .port = 0,                                          \
+            .uart_config =                                      \
+                {                                               \
+                    .baud_rate = 115200,                        \
+                    .data_bits = UART_DATA_8_BITS,              \
+                    .parity = UART_PARITY_DISABLE,              \
+                    .stop_bits = UART_STOP_BITS_1,              \
+                    .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,      \
+                    .rx_flow_ctrl_thresh = 0,                   \
+                    .source_clk = UART_SCLK_DEFAULT,            \
+                },                                              \
+            .rx_pin = UART_PIN_NO_CHANGE,                       \
+            .tx_pin = UART_PIN_NO_CHANGE,                       \
+        },                                                      \
+    }
+#elif CONFIG_OPENTHREAD_CONSOLE_TYPE_USB_SERIAL_JTAG
+#define ESP_OPENTHREAD_DEFAULT_HOST_CONFIG()                        \
+    {                                                               \
+        .host_connection_mode = HOST_CONNECTION_MODE_CLI_USB,       \
+        .host_usb_config = USB_SERIAL_JTAG_DRIVER_CONFIG_DEFAULT(), \
+    }
+#endif
+
+#define ESP_OPENTHREAD_DEFAULT_PORT_CONFIG()    \
+    {                                           \
+        .storage_partition_name = "nvs",        \
+        .netif_queue_size = 10,                 \
+        .task_queue_size = 10,                  \
+    }
diff --git a/examples/openthread/ot_trel/main/esp_ot_trel.c b/examples/openthread/ot_trel/main/esp_ot_trel.c
new file mode 100644
index 00000000000..05b7251da4f
--- /dev/null
+++ b/examples/openthread/ot_trel/main/esp_ot_trel.c
@@ -0,0 +1,139 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: CC0-1.0
+ *
+ * OpenThread Command Line Example
+ *
+ * This example code is in the Public Domain (or CC0 licensed, at your option.)
+ *
+ * Unless required by applicable law or agreed to in writing, this
+ * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied.
+*/
+
+#include <stdio.h>
+#include <unistd.h>
+#include <string.h>
+
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_event.h"
+#include "esp_log.h"
+#include "esp_netif.h"
+#include "esp_netif_types.h"
+#include "esp_openthread.h"
+#include "esp_openthread_cli.h"
+#include "esp_openthread_lock.h"
+#include "esp_openthread_netif_glue.h"
+#include "esp_openthread_types.h"
+#include "esp_ot_config.h"
+#include "esp_vfs_eventfd.h"
+#include "driver/uart.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "hal/uart_types.h"
+#include "nvs_flash.h"
+#include "openthread/cli.h"
+#include "openthread/instance.h"
+#include "openthread/logging.h"
+#include "openthread/tasklet.h"
+#include "protocol_examples_common.h"
+#include "mdns.h"
+
+#if !CONFIG_EXAMPLE_CONNECT_WIFI && !CONFIG_EXAMPLE_CONNECT_ETHERNET
+#error No netif for TREL!
+#endif
+
+#if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE
+#include "ot_led_strip.h"
+#endif
+
+#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION
+#include "esp_ot_cli_extension.h"
+#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION
+
+
+#define TAG "ot_esp_trel"
+
+static esp_netif_t *init_openthread_netif(const esp_openthread_platform_config_t *config)
+{
+    esp_netif_config_t cfg = ESP_NETIF_DEFAULT_OPENTHREAD();
+    esp_netif_t *netif = esp_netif_new(&cfg);
+    assert(netif != NULL);
+    ESP_ERROR_CHECK(esp_netif_attach(netif, esp_openthread_netif_glue_init(config)));
+
+    return netif;
+}
+
+static void ot_task_worker(void *aContext)
+{
+    esp_openthread_platform_config_t config = {
+        .radio_config = ESP_OPENTHREAD_DEFAULT_RADIO_CONFIG(),
+        .host_config = ESP_OPENTHREAD_DEFAULT_HOST_CONFIG(),
+        .port_config = ESP_OPENTHREAD_DEFAULT_PORT_CONFIG(),
+    };
+
+    ESP_ERROR_CHECK(example_connect());
+
+    // Initialize the OpenThread stack
+    ESP_ERROR_CHECK(esp_openthread_init(&config));
+
+#if CONFIG_OPENTHREAD_STATE_INDICATOR_ENABLE
+    ESP_ERROR_CHECK(esp_openthread_state_indicator_init(esp_openthread_get_instance()));
+#endif
+
+#if CONFIG_OPENTHREAD_LOG_LEVEL_DYNAMIC
+    // The OpenThread log level directly matches ESP log level
+    (void)otLoggingSetLevel(CONFIG_LOG_DEFAULT_LEVEL);
+#endif
+    // Initialize the OpenThread cli
+#if CONFIG_OPENTHREAD_CLI
+    esp_openthread_cli_init();
+#endif
+
+    esp_netif_t *openthread_netif;
+    // Initialize the esp_netif bindings
+    openthread_netif = init_openthread_netif(&config);
+    esp_netif_set_default_netif(openthread_netif);
+
+#if CONFIG_OPENTHREAD_CLI_ESP_EXTENSION
+    esp_cli_custom_command_init();
+#endif // CONFIG_OPENTHREAD_CLI_ESP_EXTENSION
+
+    // Run the main loop
+#if CONFIG_OPENTHREAD_CLI
+    esp_openthread_cli_create_task();
+#endif
+#if CONFIG_OPENTHREAD_AUTO_START
+    otOperationalDatasetTlvs dataset;
+    otError error = otDatasetGetActiveTlvs(esp_openthread_get_instance(), &dataset);
+    ESP_ERROR_CHECK(esp_openthread_auto_start((error == OT_ERROR_NONE) ? &dataset : NULL));
+#endif
+    esp_openthread_launch_mainloop();
+
+    // Clean up
+    esp_openthread_netif_glue_deinit();
+    esp_netif_destroy(openthread_netif);
+
+    esp_vfs_eventfd_unregister();
+    vTaskDelete(NULL);
+}
+
+void app_main(void)
+{
+    // Used eventfds:
+    // * netif
+    // * ot task queue
+    esp_vfs_eventfd_config_t eventfd_config = {
+        .max_fds = 2,
+    };
+
+    ESP_ERROR_CHECK(nvs_flash_init());
+    ESP_ERROR_CHECK(esp_event_loop_create_default());
+    ESP_ERROR_CHECK(esp_netif_init());
+    ESP_ERROR_CHECK(esp_vfs_eventfd_register(&eventfd_config));
+    ESP_ERROR_CHECK(mdns_init());
+    ESP_ERROR_CHECK(mdns_hostname_set("esp-ot-trel"));
+    xTaskCreate(ot_task_worker, "ot_trel_main", 8192, xTaskGetCurrentTaskHandle(), 5, NULL);
+}
diff --git a/examples/openthread/ot_trel/main/idf_component.yml b/examples/openthread/ot_trel/main/idf_component.yml
new file mode 100644
index 00000000000..a52a17085f0
--- /dev/null
+++ b/examples/openthread/ot_trel/main/idf_component.yml
@@ -0,0 +1,11 @@
+## IDF Component Manager Manifest File
+dependencies:
+  espressif/esp_ot_cli_extension:
+    version: "~1.2.0"
+  espressif/mdns: "^1.0.3"
+  idf:
+    version: ">=4.1.0"
+  protocol_examples_common:
+    path: ${IDF_PATH}/examples/common_components/protocol_examples_common
+  ot_led:
+    path: ${IDF_PATH}/examples/openthread/ot_common_components/ot_led
diff --git a/examples/openthread/ot_trel/partitions.csv b/examples/openthread/ot_trel/partitions.csv
new file mode 100644
index 00000000000..641bcc9afcc
--- /dev/null
+++ b/examples/openthread/ot_trel/partitions.csv
@@ -0,0 +1,5 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
+nvs,        data, nvs,      0x9000,  0x6000,
+phy_init,   data, phy,      0xf000,  0x1000,
+factory,    app,  factory,  0x10000, 0x170000,
diff --git a/examples/openthread/ot_trel/sdkconfig.ci.trel b/examples/openthread/ot_trel/sdkconfig.ci.trel
new file mode 100644
index 00000000000..994413fa4fc
--- /dev/null
+++ b/examples/openthread/ot_trel/sdkconfig.ci.trel
@@ -0,0 +1,3 @@
+CONFIG_EXAMPLE_CONNECT_WIFI=y
+CONFIG_EXAMPLE_WIFI_SSID="OTCITE"
+CONFIG_EXAMPLE_WIFI_PASSWORD="otcitest888"
diff --git a/examples/openthread/ot_trel/sdkconfig.defaults b/examples/openthread/ot_trel/sdkconfig.defaults
new file mode 100644
index 00000000000..99f65081b92
--- /dev/null
+++ b/examples/openthread/ot_trel/sdkconfig.defaults
@@ -0,0 +1,43 @@
+#
+# Partition Table
+#
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
+CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
+CONFIG_PARTITION_TABLE_OFFSET=0x8000
+CONFIG_PARTITION_TABLE_MD5=y
+# end of Partition Table
+
+#
+# mbedTLS
+#
+CONFIG_MBEDTLS_CMAC_C=y
+CONFIG_MBEDTLS_SSL_PROTO_DTLS=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECJPAKE=y
+CONFIG_MBEDTLS_ECJPAKE_C=y
+# end of mbedTLS
+
+#
+# OpenThread
+#
+CONFIG_OPENTHREAD_ENABLED=y
+CONFIG_OPENTHREAD_BORDER_ROUTER=n
+CONFIG_OPENTHREAD_DNS64_CLIENT=y
+CONFIG_OPENTHREAD_RADIO_154_NONE=y
+CONFIG_OPENTHREAD_RADIO_TREL=y
+# end of OpenThread
+
+#
+# lwIP
+#
+CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=4096
+CONFIG_LWIP_IPV6_NUM_ADDRESSES=8
+CONFIG_LWIP_MULTICAST_PING=y
+CONFIG_LWIP_HOOK_IP6_SELECT_SRC_ADDR_CUSTOM=y
+CONFIG_LWIP_IPV6_AUTOCONFIG=y
+# end of lwIP
+
+#
+# Configurations for optimizing the size of firmware
+#
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
diff --git a/examples/openthread/pytest_otbr.py b/examples/openthread/pytest_otbr.py
index 604862d8d34..2abb6e4cb9c 100644
--- a/examples/openthread/pytest_otbr.py
+++ b/examples/openthread/pytest_otbr.py
@@ -59,6 +59,9 @@
 # Case 14: Curl a website over HTTPS via DNS and NAT64
 #         A border router joins a Wi-Fi network and forms a Thread network, a Thread devices attached to it and curl a https website.
 
+# Case 15: Thread network formation and attaching with TREL
+#         A TREL device forms a Thread network, other TREL devices attach to it, then test ping connection between them.
+
 
 @pytest.fixture(scope='module', name='Init_avahi')
 def fixture_Init_avahi() -> bool:
@@ -792,3 +795,53 @@ def test_https_NAT64_DNS(Init_interface:bool, dut: Tuple[IdfDut, IdfDut, IdfDut]
         ocf.execute_command(br, 'factoryreset')
         ocf.execute_command(cli, 'factoryreset')
         time.sleep(3)
+
+
+# Case 15: Thread network formation and attaching with TREL
+@pytest.mark.supported_targets
+@pytest.mark.esp32c6
+@pytest.mark.openthread_br
+@pytest.mark.flaky(reruns=1, reruns_delay=1)
+@pytest.mark.parametrize(
+    'config, count, app_path, target', [
+        ('trel|trel', 2,
+         f'{os.path.join(os.path.dirname(__file__), "ot_trel")}'
+         f'|{os.path.join(os.path.dirname(__file__), "ot_trel")}',
+         'esp32c6|esp32s3'),
+    ],
+    indirect=True,
+)
+def test_trel_connect(dut: Tuple[IdfDut, IdfDut]) -> None:
+    trel_s3 = dut[1]
+    trel_c6 = dut[0]
+    trel_list = [trel_c6]
+    router_extaddr_list = ['7766554433221101']
+
+    trel_s3.expect('IPv4 address:', timeout=10)
+    trel_c6.expect('IPv4 address:', timeout=10)
+    ocf.init_thread(trel_s3)
+    for trel in trel_list:
+        ocf.init_thread(trel)
+    trel_leader_para = copy.copy(default_br_ot_para)
+    trel_leader_para.bbr = False
+    ocf.joinThreadNetwork(trel_s3, trel_leader_para)
+    trel_para = copy.copy(default_cli_ot_para)
+    trel_para.dataset = ocf.getDataset(trel_s3)
+    try:
+        order = 0
+        for trel in trel_list:
+            trel_para.exaddr = router_extaddr_list[order]
+            order = order + 1
+            ocf.joinThreadNetwork(trel, trel_para)
+        for trel in trel_list:
+            trel_mleid_addr = ocf.get_mleid_addr(trel)
+            trel_s3_mleid_addr = ocf.get_mleid_addr(trel_s3)
+            rx_nums = ocf.ot_ping(trel, trel_s3_mleid_addr, 5)[1]
+            assert rx_nums == 5
+            rx_nums = ocf.ot_ping(trel_s3, trel_mleid_addr, 5)[1]
+            assert rx_nums == 5
+    finally:
+        ocf.execute_command(trel_s3, 'factoryreset')
+        for trel in trel_list:
+            ocf.execute_command(trel, 'factoryreset')
+        time.sleep(3)
diff --git a/examples/peripherals/.build-test-rules.yml b/examples/peripherals/.build-test-rules.yml
index e8ad2c13719..dbf5565c56f 100644
--- a/examples/peripherals/.build-test-rules.yml
+++ b/examples/peripherals/.build-test-rules.yml
@@ -14,6 +14,9 @@ examples/peripherals/adc/continuous_read:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: lack of runners, TODO IDF-9573
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: lack of runner
   <<: *adc_dependencies
 
 examples/peripherals/adc/oneshot_read:
@@ -23,6 +26,9 @@ examples/peripherals/adc/oneshot_read:
     - if: IDF_TARGET == "esp32p4"
       temporary: true
       reason: lack of runner, TODO IDF-9573
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: lack of runner
   <<: *adc_dependencies
 
 examples/peripherals/analog_comparator:
@@ -67,6 +73,12 @@ examples/peripherals/i2c/i2c_eeprom:
   depends_components:
     - esp_driver_i2c
 
+examples/peripherals/i2c/i2c_slave_network_sensor:
+  disable:
+    - if: SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE != 1 or (SOC_WIFI_SUPPORTED != 1 and SOC_EMAC_SUPPORTED != 1)
+  depends_components:
+    - esp_driver_i2c
+
 examples/peripherals/i2c/i2c_tools:
   disable:
     - if: SOC_I2C_SUPPORTED != 1
@@ -102,7 +114,7 @@ examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm:
     - if: SOC_I2S_SUPPORTS_TDM != 1 or (SOC_I2C_SUPPORTED != 1 or SOC_GPSPI_SUPPORTED != 1)
       reason: rely on I2S TDM mode to receive audio, I2C to config es7210 and SPI to save audio to SD card
   disable_test:
-    - if: IDF_TARGET == "esp32p4"
+    - if: IDF_TARGET in ["esp32p4", "esp32c61"]
       temporary: true
       reason: lack of runners
   depends_components:
@@ -420,24 +432,19 @@ examples/peripherals/touch_sensor/touch_element:
     - if: IDF_TARGET in ["esp32s2", "esp32s3"]
       reason: only supports esp32s2 and esp32s3
 
-examples/peripherals/touch_sensor/touch_sensor_v1:
-  disable:
-    - if: SOC_TOUCH_SENSOR_VERSION != 1
-
-examples/peripherals/touch_sensor/touch_sensor_v2:
-  disable:
-    - if: SOC_TOUCH_SENSOR_VERSION != 2
-
-examples/peripherals/touch_sensor/touch_sensor_v3:
+examples/peripherals/touch_sensor/touch_sens_basic:
   disable:
-    - if: SOC_TOUCH_SENSOR_VERSION != 3
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
+    - if: SOC_TOUCH_SENSOR_SUPPORTED != 1
+    - if: SOC_TOUCH_SENSOR_VERSION == 1
       temporary: true
-      reason: the runners do not support the pins for touch sensor
+      reason: not supported yet
   depends_components:
     - esp_driver_touch_sens
 
+examples/peripherals/touch_sensor/touch_sensor_v1:
+  disable:
+    - if: SOC_TOUCH_SENSOR_VERSION != 1
+
 examples/peripherals/twai/twai_alert_and_recovery:
   disable:
     - if: SOC_TWAI_SUPPORTED != 1
diff --git a/examples/peripherals/adc/continuous_read/README.md b/examples/peripherals/adc/continuous_read/README.md
index 614dedffb6a..8e7861d7de4 100644
--- a/examples/peripherals/adc/continuous_read/README.md
+++ b/examples/peripherals/adc/continuous_read/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # ADC DMA Example
 
diff --git a/examples/peripherals/adc/oneshot_read/README.md b/examples/peripherals/adc/oneshot_read/README.md
index 431ae899044..491964fb0bf 100644
--- a/examples/peripherals/adc/oneshot_read/README.md
+++ b/examples/peripherals/adc/oneshot_read/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # ADC Single Read Example
 
diff --git a/examples/peripherals/camera/camera_dsi/components/dsi_init/Kconfig.projbuild b/examples/peripherals/camera/camera_dsi/components/dsi_init/Kconfig.projbuild
index 6e81a71006e..e433698706b 100644
--- a/examples/peripherals/camera/camera_dsi/components/dsi_init/Kconfig.projbuild
+++ b/examples/peripherals/camera/camera_dsi/components/dsi_init/Kconfig.projbuild
@@ -13,7 +13,7 @@ menu "Example DSI Configuration"
     endchoice
 
     choice EXAMPLE_MIPI_DSI_DISP_HRES
-        bool "Set MIPI CSI horizontal resolution"
+        bool "Set MIPI DSI horizontal resolution"
         default EXAMPLE_MIPI_DSI_DISP_HRES_800 if EXAMPLE_LCD_PATTERN_ILI9881C
         default EXAMPLE_MIPI_DSI_DISP_HRES_1024 if EXAMPLE_LCD_PATTERN_EK79007
         default EXAMPLE_MIPI_DSI_DISP_HRES_800
@@ -30,7 +30,7 @@ menu "Example DSI Configuration"
         default 1024 if EXAMPLE_MIPI_DSI_DISP_HRES_1024
 
     choice EXAMPLE_MIPI_DSI_DISP_VRES
-        bool "Set MIPI CSI vertical resolution"
+        bool "Set MIPI DSI vertical resolution"
         default EXAMPLE_MIPI_DSI_DISP_VRES_1280 if EXAMPLE_LCD_PATTERN_ILI9881C
         default EXAMPLE_MIPI_DSI_DISP_VRES_600 if EXAMPLE_LCD_PATTERN_EK79007
         default EXAMPLE_MIPI_DSI_DISP_VRES_1280
diff --git a/examples/peripherals/camera/camera_dsi/components/dsi_init/example_dsi_init.c b/examples/peripherals/camera/camera_dsi/components/dsi_init/example_dsi_init.c
index 9424c27960c..955f45d7942 100644
--- a/examples/peripherals/camera/camera_dsi/components/dsi_init/example_dsi_init.c
+++ b/examples/peripherals/camera/camera_dsi/components/dsi_init/example_dsi_init.c
@@ -36,7 +36,7 @@ void example_dsi_resource_alloc(esp_lcd_dsi_bus_handle_t *mipi_dsi_bus, esp_lcd_
         .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
         .dpi_clock_freq_mhz = EXAMPLE_MIPI_DSI_DPI_CLK_MHZ,
         .virtual_channel = 0,
-        .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB565,
+        .in_color_format = LCD_COLOR_FMT_RGB565,
         .video_timing = {
             .h_size = CONFIG_EXAMPLE_MIPI_DSI_DISP_HRES,
             .v_size = CONFIG_EXAMPLE_MIPI_DSI_DISP_VRES,
diff --git a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c
index 27b22cdaa4d..89b7bbc88a4 100644
--- a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c
+++ b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c
@@ -1,11 +1,9 @@
-/* GPIO Example
-
-   This example code is in the Public Domain (or CC0 licensed, at your option.)
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-   Unless required by applicable law or agreed to in writing, this
-   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-   CONDITIONS OF ANY KIND, either express or implied.
-*/
 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
diff --git a/examples/peripherals/gpio/matrix_keyboard/README.md b/examples/peripherals/gpio/matrix_keyboard/README.md
index 31cd207e55d..76d095e4172 100644
--- a/examples/peripherals/gpio/matrix_keyboard/README.md
+++ b/examples/peripherals/gpio/matrix_keyboard/README.md
@@ -23,7 +23,7 @@ This matrix keyboard driver is interrupt-driven, supports a configurable debounc
 
 This example can run on any target that has the dedicated feature (e.g. ESP32-S2). It's not necessary for your matrix board to have pull-up resisters on row/column lines. The driver has enabled internal pull-up resister by default. A typical matrix board should look as follows:
 
-```
+```text
 row_0   +--------+-------------------+------------------------------+-----------------+
                  |                   |                              |
                  |       +           |       +                      |       +
@@ -51,7 +51,7 @@ row_n   +--------+-------------------+------------------------------+-----------
 
 Build the project and flash it to the board, then run monitor tool to view serial output:
 
-```
+```text
 idf.py -p PORT flash monitor
 ```
 
@@ -63,7 +63,7 @@ See the Getting Started Guide for full steps to configure and use ESP-IDF to bui
 
 ## Example Output
 
-```
+```text
 I (2883) example: press event, key code = 0002
 I (3003) example: release event, key code = 0002
 I (5053) example: press event, key code = 0001
@@ -77,3 +77,7 @@ I (8923) example: release event, key code = 0103
 I (9543) example: press event, key code = 0203
 I (9683) example: release event, key code = 0203
 ```
+
+## Troubleshooting
+
+For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon.
diff --git a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h
index 825ae314693..f4598c74cb9 100644
--- a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h
+++ b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h
@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
diff --git a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c
index daf1b6a3416..48b7a23506e 100644
--- a/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c
+++ b/examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/src/matrix_keyboard.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,24 +7,15 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "freertos/timers.h"
-#include "esp_compiler.h"
 #include "esp_log.h"
+#include "esp_check.h"
 #include "driver/dedic_gpio.h"
 #include "driver/gpio.h"
+#include "esp_private/gpio.h"
 #include "matrix_keyboard.h"
-#include "esp_rom_sys.h"
 
 static const char *TAG = "mkbd";
 
-#define MKBD_CHECK(a, msg, tag, ret, ...)                                         \
-    do {                                                                          \
-        if (unlikely(!(a))) {                                                     \
-            ESP_LOGE(TAG, "%s(%d): " msg, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
-            ret_code = ret;                                                       \
-            goto tag;                                                             \
-        }                                                                         \
-    } while (0)
-
 typedef struct matrix_kbd_t matrix_kbd_t;
 
 struct matrix_kbd_t {
@@ -91,45 +82,36 @@ static void matrix_kbd_debounce_timer_callback(TimerHandle_t xTimer)
 
 esp_err_t matrix_kbd_install(const matrix_kbd_config_t *config, matrix_kbd_handle_t *mkbd_handle)
 {
-    esp_err_t ret_code = ESP_OK;
+    esp_err_t ret = ESP_OK;
     matrix_kbd_t *mkbd = NULL;
-    MKBD_CHECK(config, "matrix keyboard configuration can't be null", err, ESP_ERR_INVALID_ARG);
-    MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG);
+    ESP_RETURN_ON_FALSE(config && mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
 
     mkbd = calloc(1, sizeof(matrix_kbd_t) + (config->nr_row_gpios) * sizeof(uint32_t));
-    MKBD_CHECK(mkbd, "allocate matrix keyboard context failed", err, ESP_ERR_NO_MEM);
+    ESP_RETURN_ON_FALSE(mkbd, ESP_ERR_NO_MEM, TAG, "no mem for matrix keyboard context");
+
+    // Create a ont-shot os timer, used for key debounce
+    mkbd->debounce_timer = xTimerCreate("kb_debounce", pdMS_TO_TICKS(config->debounce_ms), pdFALSE, mkbd, matrix_kbd_debounce_timer_callback);
+    ESP_GOTO_ON_FALSE(mkbd->debounce_timer, ESP_FAIL, err, TAG, "create debounce timer failed");
 
     mkbd->nr_col_gpios = config->nr_col_gpios;
     mkbd->nr_row_gpios = config->nr_row_gpios;
 
-    // GPIO pad configuration
-    // Each GPIO used in matrix key board should be able to input and output
-    // In case the keyboard doesn't design a resister to pull up row/col line
-    // We enable the internal pull up resister, enable Open Drain as well
-    gpio_config_t io_conf = {
-        .mode = GPIO_MODE_INPUT_OUTPUT_OD,
-        .pull_up_en = 1
-    };
-
-    for (int i = 0; i < config->nr_row_gpios; i++) {
-        io_conf.pin_bit_mask = 1ULL << config->row_gpios[i];
-        gpio_config(&io_conf);
-    }
-
     dedic_gpio_bundle_config_t bundle_row_config = {
         .gpio_array = config->row_gpios,
         .array_size = config->nr_row_gpios,
+        // Each GPIO used in matrix key board should be able to input and output
         .flags = {
             .in_en = 1,
             .out_en = 1,
         },
     };
-    MKBD_CHECK(dedic_gpio_new_bundle(&bundle_row_config, &mkbd->row_bundle) == ESP_OK,
-               "create row bundle failed", err, ESP_FAIL);
+    ESP_GOTO_ON_ERROR(dedic_gpio_new_bundle(&bundle_row_config, &mkbd->row_bundle), err, TAG, "create row bundle failed");
 
-    for (int i = 0; i < config->nr_col_gpios; i++) {
-        io_conf.pin_bit_mask = 1ULL << config->col_gpios[i];
-        gpio_config(&io_conf);
+    // In case the keyboard doesn't design a resister to pull up row/col line
+    // We enable the internal pull up resister, enable Open Drain as well
+    for (int i = 0; i < config->nr_row_gpios; i++) {
+        gpio_pullup_en(config->row_gpios[i]);
+        gpio_od_enable(config->row_gpios[i]);
     }
 
     dedic_gpio_bundle_config_t bundle_col_config = {
@@ -140,8 +122,12 @@ esp_err_t matrix_kbd_install(const matrix_kbd_config_t *config, matrix_kbd_handl
             .out_en = 1,
         },
     };
-    MKBD_CHECK(dedic_gpio_new_bundle(&bundle_col_config, &mkbd->col_bundle) == ESP_OK,
-               "create col bundle failed", err, ESP_FAIL);
+    ESP_GOTO_ON_ERROR(dedic_gpio_new_bundle(&bundle_col_config, &mkbd->col_bundle), err, TAG, "create col bundle failed");
+
+    for (int i = 0; i < config->nr_col_gpios; i++) {
+        gpio_pullup_en(config->col_gpios[i]);
+        gpio_od_enable(config->col_gpios[i]);
+    }
 
     // Disable interrupt
     dedic_gpio_bundle_set_interrupt_and_callback(mkbd->row_bundle, (1 << config->nr_row_gpios) - 1,
@@ -149,45 +135,35 @@ esp_err_t matrix_kbd_install(const matrix_kbd_config_t *config, matrix_kbd_handl
     dedic_gpio_bundle_set_interrupt_and_callback(mkbd->col_bundle, (1 << config->nr_col_gpios) - 1,
                                                  DEDIC_GPIO_INTR_NONE, NULL, NULL);
 
-    // Create a ont-shot os timer, used for key debounce
-    mkbd->debounce_timer = xTimerCreate("kb_debounce", pdMS_TO_TICKS(config->debounce_ms), pdFALSE, mkbd, matrix_kbd_debounce_timer_callback);
-    MKBD_CHECK(mkbd->debounce_timer, "create debounce timer failed", err, ESP_FAIL);
-
     * mkbd_handle = mkbd;
     return ESP_OK;
 err:
-    if (mkbd) {
-        if (mkbd->debounce_timer) {
-            xTimerDelete(mkbd->debounce_timer, 0);
-        }
-        if (mkbd->col_bundle) {
-            dedic_gpio_del_bundle(mkbd->col_bundle);
-        }
-        if (mkbd->row_bundle) {
-            dedic_gpio_del_bundle(mkbd->row_bundle);
-        }
-        free(mkbd);
+    if (mkbd->debounce_timer) {
+        xTimerDelete(mkbd->debounce_timer, 0);
     }
-    return ret_code;
+    if (mkbd->col_bundle) {
+        dedic_gpio_del_bundle(mkbd->col_bundle);
+    }
+    if (mkbd->row_bundle) {
+        dedic_gpio_del_bundle(mkbd->row_bundle);
+    }
+    free(mkbd);
+    return ret;
 }
 
 esp_err_t matrix_kbd_uninstall(matrix_kbd_handle_t mkbd_handle)
 {
-    esp_err_t ret_code = ESP_OK;
-    MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG);
+    ESP_RETURN_ON_FALSE(mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     xTimerDelete(mkbd_handle->debounce_timer, 0);
     dedic_gpio_del_bundle(mkbd_handle->col_bundle);
     dedic_gpio_del_bundle(mkbd_handle->row_bundle);
     free(mkbd_handle);
     return ESP_OK;
-err:
-    return ret_code;
 }
 
 esp_err_t matrix_kbd_start(matrix_kbd_handle_t mkbd_handle)
 {
-    esp_err_t ret_code = ESP_OK;
-    MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG);
+    ESP_RETURN_ON_FALSE(mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
 
     // row lines set to high level
     dedic_gpio_bundle_write(mkbd_handle->row_bundle, (1 << mkbd_handle->nr_row_gpios) - 1, (1 << mkbd_handle->nr_row_gpios) - 1);
@@ -203,15 +179,11 @@ esp_err_t matrix_kbd_start(matrix_kbd_handle_t mkbd_handle)
                                                  DEDIC_GPIO_INTR_BOTH_EDGE, matrix_kbd_row_isr_callback, mkbd_handle);
 
     return ESP_OK;
-err:
-    return ret_code;
 }
 
 esp_err_t matrix_kbd_stop(matrix_kbd_handle_t mkbd_handle)
 {
-    esp_err_t ret_code = ESP_OK;
-    MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG);
-
+    ESP_RETURN_ON_FALSE(mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     xTimerStop(mkbd_handle->debounce_timer, 0);
 
     // Disable interrupt
@@ -221,17 +193,12 @@ esp_err_t matrix_kbd_stop(matrix_kbd_handle_t mkbd_handle)
                                                  DEDIC_GPIO_INTR_NONE, NULL, NULL);
 
     return ESP_OK;
-err:
-    return ret_code;
 }
 
 esp_err_t matrix_kbd_register_event_handler(matrix_kbd_handle_t mkbd_handle, matrix_kbd_event_handler handler, void *args)
 {
-    esp_err_t ret_code = ESP_OK;
-    MKBD_CHECK(mkbd_handle, "matrix keyboard handle can't be null", err, ESP_ERR_INVALID_ARG);
+    ESP_RETURN_ON_FALSE(mkbd_handle, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     mkbd_handle->event_handler = handler;
     mkbd_handle->event_handler_args = args;
     return ESP_OK;
-err:
-    return ret_code;
 }
diff --git a/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c b/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c
index fd1008e90ba..657d24136a0 100644
--- a/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c
+++ b/examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c
@@ -1,11 +1,9 @@
-/* Matrix Keyboard (based on dedicated GPIO) example
-
-   This example code is in the Public Domain (or CC0 licensed, at your option.)
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-   Unless required by applicable law or agreed to in writing, this
-   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-   CONDITIONS OF ANY KIND, either express or implied.
-*/
 #include <stdio.h>
 #include "esp_log.h"
 #include "matrix_keyboard.h"
diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/CMakeLists.txt b/examples/peripherals/i2c/i2c_slave_network_sensor/CMakeLists.txt
new file mode 100644
index 00000000000..f4e3329f7e4
--- /dev/null
+++ b/examples/peripherals/i2c/i2c_slave_network_sensor/CMakeLists.txt
@@ -0,0 +1,10 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+
+# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
+idf_build_set_property(MINIMAL_BUILD ON)
+project(i2c_slave_network_sensor)
diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/README.md b/examples/peripherals/i2c/i2c_slave_network_sensor/README.md
new file mode 100644
index 00000000000..91c3ef9314f
--- /dev/null
+++ b/examples/peripherals/i2c/i2c_slave_network_sensor/README.md
@@ -0,0 +1,129 @@
+| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
+
+
+# I2C slave example
+
+This code demonstrates how to use the I2C slave driver to make a "network sensor". For illustration, the "sensor" will fetch some data from Github. You can attach this "sensor" to any I2C bus, then the master should be able to read the network data. This example uses the stretch mechanism to solve the problem of the i2c slave not knowing when it should send or receive data. In this example, we have a task to periodically update esp-idf's data on github. When the i2c master comes to visit, if the i2c slave fifo has data, it will return the data directly, if there is no data, it will set off the stretch interrupt, then there will be a callback to fill in the updated github data into the i2c fifo, release the stretch, and the master will return the data.
+
+## Overview
+
+This example demonstrates the possible usage of I2C slave driver
+
+## How to use example
+
+### Hardware Required
+
+To run this example, you should have one  ESP32-S, ESP32-C based development board. Also this example need wifi signal to access the internet.
+
+#### Pin Assignment:
+
+**Note:** The following pin assignments are used by default, you can change these in the `menuconfig` .
+
+|                                | SDA            | SCL            |
+| ------------------------------ | -------------- | -------------- |
+| ESP I2C Master (this example)  | I2C_MASTER_SDA | I2C_MASTER_SCL |
+| ESP I2C Slave  (this example)  | I2C_SLAVE_SDA  | I2C_SLAVE_SCL  |
+
+For the actual default value of `I2C_SLAVE_SDA` and `I2C_SLAVE_SCL` see `Example Configuration` in `menuconfig`.
+
+**Note:** There's no need to add an external pull-up resistors for SDA/SCL pin, because the driver will enable the internal pull-up resistors.
+
+
+### Command Assignment:
+
+|  Command  |    Content   |
+| --------- | ------------ |
+|   0x10    |     stars    |
+|   0x20    |     forks    |
+|   0x30    |  open_issues |
+|   0x40    |  description |
+
+
+### Build and Flash
+
+Enter `idf.py menuconfig` to config the internet information. In Example Connection Configuration option to config your wifi ssid and password.
+
+Enter `idf.py -p PORT flash monitor` to build, flash and monitor the project.
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects.
+
+## Example Output
+
+```
+I (11200) wifi:dp: 1, bi: 102400, li: 3, scale listen interval from 307200 us to 307200 us
+I (11210) wifi:set rx beacon pti, rx_bcn_pti: 0, bcn_timeout: 25000, mt_pti: 0, mt_time: 10000
+I (11250) wifi:<ba-add>idx:0 (ifx:0, f6:0e:57:fd:ee:8d), tid:0, ssn:1, winSize:64
+I (11610) wifi:dp: 2, bi: 102400, li: 4, scale listen interval from 307200 us to 409600 us
+I (11620) wifi:AP's beacon interval = 102400 us, DTIM period = 2
+I (12460) example_connect: Got IPv6 event: Interface "example_netif_sta" address: fe80:0000:0000:0000:86f7:03ff:fe80:0284, type: ESP_IP6_ADDR_IS_LINK_LOCAL
+I (12720) esp_netif_handlers: example_netif_sta ip: 192.168.70.133, mask: 255.255.255.0, gw: 192.168.70.132
+I (12720) example_connect: Got IPv4 event: Interface "example_netif_sta" address: 192.168.70.133
+I (12730) example_common: Connected to example_netif_sta
+I (12730) example_common: - IPv4 address: 192.168.70.133,
+I (12740) example_common: - IPv6 address: fe80:0000:0000:0000:86f7:03ff:fe80:0284, type: ESP_IP6_ADDR_IS_LINK_LOCAL
+I (12750) gpio: GPIO[5]| InputEn: 1| OutputEn: 1| OpenDrain: 1| Pullup: 0| Pulldown: 0| Intr:0
+I (12760) gpio: GPIO[4]| InputEn: 1| OutputEn: 1| OpenDrain: 1| Pullup: 0| Pulldown: 0| Intr:0
+I (12770) main_task: Returned from app_main()
+I (13470) wifi:<ba-add>idx:1 (ifx:0, f6:0e:57:fd:ee:8d), tid:3, ssn:0, winSize:64
+Star count: 13401
+Forks count: 7248
+issue count: 1767
+the description is: Espressif IoT Development Framework. Official development framework for Espressif SoCs.
+I (16280) HTTP_CLIENT: HTTP GET Status = 200, content_length = 6165
+```
+
+Then you can read the information from an I2C master device.
+
+We can get information via `i2c_tool` example with another esp chip plays in a i2c master role:
+
+```
+I (203) main_task: Calling app_main()
+
+ ==============================================================
+ |             Steps to Use i2c-tools                         |
+ |                                                            |
+ |  1. Try 'help', check all supported commands               |
+ |  2. Try 'i2cconfig' to configure your I2C bus              |
+ |  3. Try 'i2cdetect' to scan devices on the bus             |
+ |  4. Try 'i2cget' to get the content of specific register   |
+ |  5. Try 'i2cset' to set the value of specific register     |
+ |  6. Try 'i2cdump' to dump all the register (Experiment)    |
+ |                                                            |
+ ==============================================================
+
+
+Type 'help' to get the list of commands.
+Use UP/DOWN arrows to navigate through command history.
+Press TAB when typing command name to auto-complete.
+I (303) main_task: Returned from app_main()
+i2c-tools> i2cconfig --port=0 --freq=100000 --sda=5 --scl=4
+i2c-tools> i2cdetect
+     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
+00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+20: -- -- -- -- -- -- -- -- 28 -- -- -- -- -- -- --
+30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+i2c-tools> i2cget -c 0x28 -r 0x10 -l 4
+0x4b 0x35 0x00 0x00
+i2c-tools> i2cget -c 0x28 -r 0x20 -l 4
+0x75 0x1c 0x00 0x00
+i2c-tools> i2cget -c 0x28 -r 0x40 -l 100
+0x45 0x73 0x70 0x72 0x65 0x73 0x73 0x69 0x66 0x20 0x49 0x6f 0x54 0x20 0x44 0x65
+0x76 0x65 0x6c 0x6f 0x70 0x6d 0x65 0x6e 0x74 0x20 0x46 0x72 0x61 0x6d 0x65 0x77
+0x6f 0x72 0x6b 0x2e 0x20 0x4f 0x66 0x66 0x69 0x63 0x69 0x61 0x6c 0x20 0x64 0x65
+0x76 0x65 0x6c 0x6f 0x70 0x6d 0x65 0x6e 0x74 0x20 0x66 0x72 0x61 0x6d 0x65 0x77
+0x6f 0x72 0x6b 0x20 0x66 0x6f 0x72 0x20 0x45 0x73 0x70 0x72 0x65 0x73 0x73 0x69
+0x66 0x20 0x53 0x6f 0x43 0x73 0x2e 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+0x00 0x00 0x00 0x00
+```
+
+## Troubleshooting
+
+(For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you as soon as possible.)
diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/main/CMakeLists.txt b/examples/peripherals/i2c/i2c_slave_network_sensor/main/CMakeLists.txt
new file mode 100644
index 00000000000..e1d351ee8d1
--- /dev/null
+++ b/examples/peripherals/i2c/i2c_slave_network_sensor/main/CMakeLists.txt
@@ -0,0 +1,5 @@
+set(srcs "i2c_slave_main.c")
+
+idf_component_register(SRCS ${srcs}
+                    PRIV_REQUIRES esp_http_client esp_wifi nvs_flash json esp_driver_i2c
+                    INCLUDE_DIRS ".")
diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/main/Kconfig.projbuild b/examples/peripherals/i2c/i2c_slave_network_sensor/main/Kconfig.projbuild
new file mode 100644
index 00000000000..1ae6d281011
--- /dev/null
+++ b/examples/peripherals/i2c/i2c_slave_network_sensor/main/Kconfig.projbuild
@@ -0,0 +1,24 @@
+menu "Example Configuration"
+
+    menu "I2C Slave"
+        config I2C_SLAVE_SCL
+            int "SCL GPIO Num"
+            default 4
+            help
+                GPIO number for I2C Slave clock line.
+
+        config I2C_SLAVE_SDA
+            int "SDA GPIO Num"
+            default 5
+            help
+                GPIO number for I2C Slave data line.
+
+        config I2C_SLAVE_ADDRESS
+            hex "I2C SLAVE ADDRESS"
+            default 0x28
+            help
+                Address of I2C slave
+
+    endmenu
+
+endmenu
diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/main/i2c_slave_main.c b/examples/peripherals/i2c/i2c_slave_network_sensor/main/i2c_slave_main.c
new file mode 100644
index 00000000000..e7c19e5b7a5
--- /dev/null
+++ b/examples/peripherals/i2c/i2c_slave_network_sensor/main/i2c_slave_main.c
@@ -0,0 +1,252 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include "esp_log.h"
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_event.h"
+#include "esp_log.h"
+#include "nvs_flash.h"
+#include "esp_netif.h"
+#include "protocol_examples_common.h"
+#include "esp_http_client.h"
+#include "cJSON.h"
+#include "driver/i2c_slave.h"
+
+static const char *TAG = "example";
+
+#define I2C_SLAVE_SCL_IO CONFIG_I2C_SLAVE_SCL               /*!< gpio number for i2c slave clock */
+#define I2C_SLAVE_SDA_IO CONFIG_I2C_SLAVE_SDA               /*!< gpio number for i2c slave data */
+#define I2C_SLAVE_NUM    0
+#define ESP_SLAVE_ADDR   CONFIG_I2C_SLAVE_ADDRESS           /*!< ESP slave address, you can set any 7bit value */
+
+// Command Lists
+#define STARS_COMMAND          (0x10)
+#define FORKS_COMMAND          (0x20)
+#define OPENISSUES_COMMAND     (0x30)
+#define DESCRIPTIONS_COMMAND   (0x40)
+
+#define GITHUB_API_URL "https://api.github.com/repos/espressif/esp-idf"
+
+typedef struct {
+    char *json_buffer;
+    int json_size;
+    uint8_t tmp_buffer_stars[sizeof(int)];
+    uint8_t tmp_buffer_forks[sizeof(int)];
+    uint8_t tmp_buffer_open_issues[sizeof(int)];
+    uint8_t tmp_buffer_descriptions[100];
+    QueueHandle_t event_queue;
+    uint8_t command_data;
+    i2c_slave_dev_handle_t handle;
+} i2c_slave_github_context_t;
+
+typedef enum {
+    I2C_SLAVE_EVT_RX,
+    I2C_SLAVE_EVT_TX
+} i2c_slave_event_t;
+
+static esp_err_t _http_event_handler(esp_http_client_event_t *evt)
+{
+    i2c_slave_github_context_t *context = (i2c_slave_github_context_t *)evt->user_data;
+    int star_count = 0, forks_count = 0, open_issues_count = 0;
+
+    switch (evt->event_id) {
+    case HTTP_EVENT_ON_DATA:
+        if (evt->data_len > 0) {
+            if (context->json_buffer == NULL) {
+                context->json_buffer = malloc(evt->data_len + 1);
+            } else {
+                context->json_buffer = realloc(context->json_buffer, context->json_size + evt->data_len + 1);
+            }
+            if (context->json_buffer == NULL) {
+                ESP_LOGE("HTTP_CLIENT", "Failed to allocate memory for data json_buffer");
+                return ESP_FAIL;
+            }
+            memcpy(context->json_buffer + context->json_size, evt->data, evt->data_len);
+            context->json_size += evt->data_len;
+            context->json_buffer[context->json_size] = '\0';  // Null-terminate the string
+        }
+        break;
+    case HTTP_EVENT_ON_FINISH:
+        if (context->json_buffer != NULL) {
+            // Process received data
+            cJSON *root = cJSON_Parse(context->json_buffer);
+            cJSON *stars = cJSON_GetObjectItem(root, "stargazers_count");
+
+            if (stars != NULL) {
+                star_count = stars->valueint;
+                printf("Star count: %d\n", star_count);
+                memcpy(context->tmp_buffer_stars, &star_count, sizeof(int));
+            }
+            cJSON *forks = cJSON_GetObjectItem(root, "forks_count");
+            if (forks != NULL) {
+                forks_count = forks->valueint;
+                printf("Forks count: %d\n", forks_count);
+                memcpy(context->tmp_buffer_forks, &forks_count, sizeof(int));
+            }
+            cJSON *open_issues = cJSON_GetObjectItem(root, "open_issues_count");
+            if (open_issues != NULL) {
+                open_issues_count = open_issues->valueint;
+                printf("issue count: %d\n", open_issues_count);
+                memcpy(context->tmp_buffer_open_issues, &open_issues_count, sizeof(int));
+            }
+            cJSON *descriptions = cJSON_GetObjectItem(root, "description");
+            if (descriptions != NULL) {
+                printf("the description is: %s\n", descriptions->valuestring);
+                memcpy(context->tmp_buffer_descriptions, descriptions->valuestring, strlen(descriptions->valuestring));
+            }
+            cJSON_Delete(root);
+            free(context->json_buffer);
+            context->json_buffer = NULL;
+            context->json_size = 0;
+        }
+        break;
+    default:
+        break;
+    }
+
+    return ESP_OK;
+}
+
+void http_get_task(void *pvParameters)
+{
+    i2c_slave_github_context_t *context = (i2c_slave_github_context_t *)pvParameters;
+
+    esp_http_client_config_t config = {
+        .url = GITHUB_API_URL,
+        .event_handler = _http_event_handler,
+        .method = HTTP_METHOD_GET,
+        .buffer_size = 2048,
+        .user_data = context,
+    };
+
+    while (1) {
+        esp_http_client_handle_t client = esp_http_client_init(&config);
+        esp_err_t err = esp_http_client_perform(client);
+        if (err == ESP_OK) {
+            ESP_LOGI("HTTP_CLIENT", "HTTP GET Status = %d, content_length = %lld",
+                     esp_http_client_get_status_code(client),
+                     esp_http_client_get_content_length(client));
+        } else {
+            ESP_LOGE("HTTP_CLIENT", "HTTP GET request failed: %s", esp_err_to_name(err));
+        }
+        esp_http_client_cleanup(client);
+        vTaskDelay(30 * 60 * 1000 / portTICK_PERIOD_MS);
+    }
+    vTaskDelete(NULL);
+}
+
+static bool i2c_slave_request_cb(i2c_slave_dev_handle_t i2c_slave, const i2c_slave_request_event_data_t *evt_data, void *arg)
+{
+    i2c_slave_github_context_t *context = (i2c_slave_github_context_t *)arg;
+    i2c_slave_event_t evt = I2C_SLAVE_EVT_TX;
+    BaseType_t xTaskWoken = 0;
+    xQueueSendFromISR(context->event_queue, &evt, &xTaskWoken);
+    return xTaskWoken;
+}
+
+static bool i2c_slave_receive_cb(i2c_slave_dev_handle_t i2c_slave, const i2c_slave_rx_done_event_data_t *evt_data, void *arg)
+{
+    i2c_slave_github_context_t *context = (i2c_slave_github_context_t *)arg;
+    i2c_slave_event_t evt = I2C_SLAVE_EVT_RX;
+    BaseType_t xTaskWoken = 0;
+    // Command only contains one byte, so just save one bytes here.
+    context->command_data = *evt_data->buffer;
+    xQueueSendFromISR(context->event_queue, &evt, &xTaskWoken);
+    return xTaskWoken;
+}
+
+static void i2c_slave_task(void *arg)
+{
+    i2c_slave_github_context_t *context = (i2c_slave_github_context_t *)arg;
+    i2c_slave_dev_handle_t handle = (i2c_slave_dev_handle_t)context->handle;
+
+    uint8_t zero_buffer[32] = {}; // Use this buffer to clear the fifo.
+    uint32_t write_len, total_written;
+    uint32_t buffer_size = 0;
+
+    while (true) {
+        i2c_slave_event_t evt;
+        if (xQueueReceive(context->event_queue, &evt, 10) == pdTRUE) {
+            if (evt == I2C_SLAVE_EVT_TX) {
+                uint8_t *data_buffer;
+                switch (context->command_data) {
+                case STARS_COMMAND:
+                    data_buffer = context->tmp_buffer_stars;
+                    buffer_size = sizeof(context->tmp_buffer_stars);
+                    break;
+                case FORKS_COMMAND:
+                    data_buffer = context->tmp_buffer_forks;
+                    buffer_size = sizeof(context->tmp_buffer_forks);
+                    break;
+                case OPENISSUES_COMMAND:
+                    data_buffer = context->tmp_buffer_open_issues;
+                    buffer_size = sizeof(context->tmp_buffer_open_issues);
+                    break;
+                case DESCRIPTIONS_COMMAND:
+                    data_buffer = context->tmp_buffer_descriptions;
+                    buffer_size = sizeof(context->tmp_buffer_descriptions);
+                    break;
+                default:
+                    ESP_LOGE(TAG, "Invalid command");
+                    data_buffer = zero_buffer;
+                    buffer_size = sizeof(zero_buffer);
+                    break;
+                }
+
+                total_written = 0;
+                while (total_written < buffer_size) {
+                    ESP_ERROR_CHECK(i2c_slave_write(handle, data_buffer + total_written, buffer_size - total_written, &write_len, 1000));
+                    if (write_len == 0) {
+                        ESP_LOGE(TAG, "Write error or timeout");
+                        break;
+                    }
+                    total_written += write_len;
+                }
+            }
+        }
+    }
+    vTaskDelete(NULL);
+}
+
+void app_main(void)
+{
+    static i2c_slave_github_context_t context = {0};
+
+    ESP_ERROR_CHECK(nvs_flash_init());
+    ESP_ERROR_CHECK(esp_netif_init());
+    ESP_ERROR_CHECK(esp_event_loop_create_default());
+    ESP_ERROR_CHECK(example_connect());
+
+    context.event_queue = xQueueCreate(16, sizeof(i2c_slave_event_t));
+    if (!context.event_queue) {
+        ESP_LOGE(TAG, "Creating queue failed");
+        return;
+    }
+
+    i2c_slave_config_t i2c_slv_config = {
+        .i2c_port = I2C_SLAVE_NUM,
+        .clk_source = I2C_CLK_SRC_DEFAULT,
+        .scl_io_num = I2C_SLAVE_SCL_IO,
+        .sda_io_num = I2C_SLAVE_SDA_IO,
+        .slave_addr = ESP_SLAVE_ADDR,
+        .send_buf_depth = 100,
+        .receive_buf_depth = 100,
+    };
+
+    ESP_ERROR_CHECK(i2c_new_slave_device(&i2c_slv_config, &context.handle));
+    i2c_slave_event_callbacks_t cbs = {
+        .on_receive = i2c_slave_receive_cb,
+        .on_request = i2c_slave_request_cb,
+    };
+    ESP_ERROR_CHECK(i2c_slave_register_event_callbacks(context.handle, &cbs, &context));
+
+    xTaskCreate(http_get_task, "http_get_task", 4096, &context, 20, NULL);
+    xTaskCreate(i2c_slave_task, "i2c_slave_task", 1024 * 4, &context, 10, NULL);
+}
diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/main/idf_component.yml b/examples/peripherals/i2c/i2c_slave_network_sensor/main/idf_component.yml
new file mode 100644
index 00000000000..718194867b7
--- /dev/null
+++ b/examples/peripherals/i2c/i2c_slave_network_sensor/main/idf_component.yml
@@ -0,0 +1,3 @@
+dependencies:
+  protocol_examples_common:
+    path: ${IDF_PATH}/examples/common_components/protocol_examples_common
diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/partitions.csv b/examples/peripherals/i2c/i2c_slave_network_sensor/partitions.csv
new file mode 100644
index 00000000000..326d21693be
--- /dev/null
+++ b/examples/peripherals/i2c/i2c_slave_network_sensor/partitions.csv
@@ -0,0 +1,5 @@
+# Name,   Type, SubType, Offset,   Size, Flags
+# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
+nvs,      data,nvs,0x9000,24K,
+phy_init, data,phy,0xf000,4K,
+factory,  app,factory,0x10000,2M,
diff --git a/examples/peripherals/i2c/i2c_slave_network_sensor/sdkconfig.defaults b/examples/peripherals/i2c/i2c_slave_network_sensor/sdkconfig.defaults
new file mode 100644
index 00000000000..bbb0c22978a
--- /dev/null
+++ b/examples/peripherals/i2c/i2c_slave_network_sensor/sdkconfig.defaults
@@ -0,0 +1,5 @@
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_I2C_ENABLE_SLAVE_DRIVER_VERSION_2=y
+CONFIG_ESP_TLS_INSECURE=y
+CONFIG_ESP_TLS_SKIP_SERVER_CERT_VERIFY=y
diff --git a/examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md b/examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md
index 6b6235f531c..125d839e4ee 100644
--- a/examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md
+++ b/examples/peripherals/i2s/i2s_basic/i2s_pdm/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
 
 # I2S Basic PDM Mode Example
 
diff --git a/examples/peripherals/i2s/i2s_basic/i2s_pdm/pytest_i2s_pdm.py b/examples/peripherals/i2s/i2s_basic/i2s_pdm/pytest_i2s_pdm.py
index 444e1a5f97d..036ae8788fb 100644
--- a/examples/peripherals/i2s/i2s_basic/i2s_pdm/pytest_i2s_pdm.py
+++ b/examples/peripherals/i2s/i2s_basic/i2s_pdm/pytest_i2s_pdm.py
@@ -11,6 +11,7 @@
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
+@pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize(
     'config',
diff --git a/examples/peripherals/i2s/i2s_basic/i2s_std/README.md b/examples/peripherals/i2s/i2s_basic/i2s_std/README.md
index 5fc29993f73..9ab8188df32 100644
--- a/examples/peripherals/i2s/i2s_basic/i2s_std/README.md
+++ b/examples/peripherals/i2s/i2s_basic/i2s_std/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # I2S Basic Standard Mode Example
 
diff --git a/examples/peripherals/i2s/i2s_basic/i2s_std/pytest_i2s_std.py b/examples/peripherals/i2s/i2s_basic/i2s_std/pytest_i2s_std.py
index 81c60e6d4fd..8c4fe8f7b77 100644
--- a/examples/peripherals/i2s/i2s_basic/i2s_std/pytest_i2s_std.py
+++ b/examples/peripherals/i2s/i2s_basic/i2s_std/pytest_i2s_std.py
@@ -12,6 +12,7 @@
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
+@pytest.mark.esp32c61
 @pytest.mark.generic
 def test_i2s_basic_example(dut: Dut) -> None:
 
diff --git a/examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md b/examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md
index f0b30749e4c..1755a1f9514 100644
--- a/examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md
+++ b/examples/peripherals/i2s/i2s_basic/i2s_tdm/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
 
 # I2S Basic TDM Mode Example
 
diff --git a/examples/peripherals/i2s/i2s_basic/i2s_tdm/pytest_i2s_tdm.py b/examples/peripherals/i2s/i2s_basic/i2s_tdm/pytest_i2s_tdm.py
index 80c1bbf321b..3d0005b9098 100644
--- a/examples/peripherals/i2s/i2s_basic/i2s_tdm/pytest_i2s_tdm.py
+++ b/examples/peripherals/i2s/i2s_basic/i2s_tdm/pytest_i2s_tdm.py
@@ -10,6 +10,7 @@
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
+@pytest.mark.esp32c61
 @pytest.mark.generic
 def test_i2s_tdm_example(dut: Dut) -> None:
 
diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md
index b3b26f69ebd..85cc1c9486e 100644
--- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md
+++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
 
 # I2S TDM Example -- ES7210 4-Ch ADC Codec
 
diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c
index 5dceccd4218..79f510e150f 100644
--- a/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c
+++ b/examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/main/i2s_es7210_record_example.c
@@ -168,7 +168,7 @@ sdmmc_card_t * mount_sdcard(void)
 
     ESP_LOGI(TAG, "Card size: %lluMB, speed: %dMHz",
              (((uint64_t)sdmmc_card->csd.capacity) * sdmmc_card->csd.sector_size) >> 20,
-             sdmmc_card->max_freq_khz / 1000);
+             (int)(sdmmc_card->max_freq_khz / 1000));
 
     return sdmmc_card;
 }
@@ -234,7 +234,7 @@ static esp_err_t record_wav(i2s_chan_handle_t i2s_rx_chan)
     ESP_GOTO_ON_ERROR(i2s_channel_enable(i2s_rx_chan), err, TAG, "error while starting i2s rx channel");
     while (wav_written < wav_size) {
         if (wav_written % byte_rate < sizeof(i2s_readraw_buff)) {
-            ESP_LOGI(TAG, "Recording: %"PRIu32"/%ds", wav_written / byte_rate + 1, EXAMPLE_RECORD_TIME_SEC);
+            ESP_LOGI(TAG, "Recording: %"PRIu32"/%ds", wav_written / byte_rate + 1, (int)EXAMPLE_RECORD_TIME_SEC);
         }
         size_t bytes_read = 0;
         /* Read RAW samples from ES7210 */
diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md
index 0ab480ffb28..79aee879b64 100644
--- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md
+++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # I2S ES8311 Example
 
diff --git a/examples/peripherals/i2s/i2s_codec/i2s_es8311/pytest_i2s_es8311.py b/examples/peripherals/i2s/i2s_codec/i2s_es8311/pytest_i2s_es8311.py
index c888db7af6d..54404601b03 100644
--- a/examples/peripherals/i2s/i2s_codec/i2s_es8311/pytest_i2s_es8311.py
+++ b/examples/peripherals/i2s/i2s_codec/i2s_es8311/pytest_i2s_es8311.py
@@ -12,6 +12,7 @@
 @pytest.mark.esp32c6
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
+@pytest.mark.esp32c61
 @pytest.mark.generic
 def test_i2s_es8311_example_generic(dut: Dut) -> None:
     dut.expect('i2s es8311 codec example start')
diff --git a/examples/peripherals/isp/multi_pipelines/README.md b/examples/peripherals/isp/multi_pipelines/README.md
index 71139ba6b41..bfd80fbec16 100644
--- a/examples/peripherals/isp/multi_pipelines/README.md
+++ b/examples/peripherals/isp/multi_pipelines/README.md
@@ -14,6 +14,7 @@ This example demonstrates how to use the ISP (image signal processor) to work wi
 - ISP Demosaic feature
 - ISP GAMMA feature
 - ISP Color feature
+- ISP LSC feature
 
 ## Usage
 
diff --git a/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c b/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
index 15a9289cf6c..3f2db636db8 100644
--- a/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
+++ b/examples/peripherals/isp/multi_pipelines/main/isp_dsi_main.c
@@ -347,6 +347,28 @@ void app_main(void)
     ESP_ERROR_CHECK(esp_isp_color_configure(isp_proc, &color_config));
     ESP_ERROR_CHECK(esp_isp_color_enable(isp_proc));
 
+#if CONFIG_ESP32P4_REV_MIN_FULL >= 100
+    esp_isp_lsc_gain_array_t gain_array = {};
+    esp_isp_lsc_config_t lsc_config = {
+        .gain_array = &gain_array,
+    };
+    size_t gain_size = 0;
+    ESP_ERROR_CHECK(esp_isp_lsc_allocate_gain_array(isp_proc, &gain_array, &gain_size));
+
+    isp_lsc_gain_t gain_val = {
+        .decimal = 204,
+        .integer = 0,
+    };
+    for (int i = 0; i < gain_size; i++) {
+        gain_array.gain_r[i].val = gain_val.val;
+        gain_array.gain_gr[i].val = gain_val.val;
+        gain_array.gain_gb[i].val = gain_val.val;
+        gain_array.gain_b[i].val = gain_val.val;
+    }
+    ESP_ERROR_CHECK(esp_isp_lsc_configure(isp_proc, &lsc_config));
+    ESP_ERROR_CHECK(esp_isp_lsc_enable(isp_proc));
+#endif
+
     typedef struct af_task_param_t {
         isp_proc_handle_t isp_proc;
         esp_sccb_io_handle_t dw9714_io_handle;
diff --git a/examples/peripherals/lcd/i2c_oled/main/i2c_oled_example_main.c b/examples/peripherals/lcd/i2c_oled/main/i2c_oled_example_main.c
index 1276da8aefe..098c62d66ce 100644
--- a/examples/peripherals/lcd/i2c_oled/main/i2c_oled_example_main.c
+++ b/examples/peripherals/lcd/i2c_oled/main/i2c_oled_example_main.c
@@ -5,14 +5,16 @@
  */
 
 #include <stdio.h>
+#include <unistd.h>
+#include <sys/lock.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
+#include "esp_timer.h"
 #include "esp_lcd_panel_io.h"
 #include "esp_lcd_panel_ops.h"
 #include "esp_err.h"
 #include "esp_log.h"
 #include "driver/i2c_master.h"
-#include "esp_lvgl_port.h"
 #include "lvgl.h"
 
 #if CONFIG_EXAMPLE_LCD_CONTROLLER_SH1107
@@ -46,8 +48,81 @@ static const char *TAG = "example";
 #define EXAMPLE_LCD_CMD_BITS           8
 #define EXAMPLE_LCD_PARAM_BITS         8
 
+#define EXAMPLE_LVGL_TICK_PERIOD_MS    5
+#define EXAMPLE_LVGL_TASK_STACK_SIZE   (4 * 1024)
+#define EXAMPLE_LVGL_TASK_PRIORITY     2
+#define EXAMPLE_LVGL_PALETTE_SIZE      8
+
+// To use LV_COLOR_FORMAT_I1, we need an extra buffer to hold the converted data
+static uint8_t oled_buffer[EXAMPLE_LCD_H_RES * EXAMPLE_LCD_V_RES / 8];
+// LVGL library is not thread-safe, this example will call LVGL APIs from different tasks, so use a mutex to protect it
+static _lock_t lvgl_api_lock;
+
 extern void example_lvgl_demo_ui(lv_disp_t *disp);
 
+static bool example_notify_lvgl_flush_ready(esp_lcd_panel_io_handle_t io_panel, esp_lcd_panel_io_event_data_t *edata, void *user_ctx)
+{
+    lv_display_t *disp = (lv_display_t *)user_ctx;
+    lv_display_flush_ready(disp);
+    return false;
+}
+
+static void example_lvgl_flush_cb(lv_display_t *disp, const lv_area_t *area, uint8_t *px_map)
+{
+    esp_lcd_panel_handle_t panel_handle = lv_display_get_user_data(disp);
+
+    // This is necessary because LVGL reserves 2 x 4 bytes in the buffer, as these are assumed to be used as a palette. Skip the palette here
+    // More information about the monochrome, please refer to https://docs.lvgl.io/9.2/porting/display.html#monochrome-displays
+    px_map += EXAMPLE_LVGL_PALETTE_SIZE;
+
+    uint16_t hor_res = lv_display_get_physical_horizontal_resolution(disp);
+    int x1 = area->x1;
+    int x2 = area->x2;
+    int y1 = area->y1;
+    int y2 = area->y2;
+
+    for (int y = y1; y <= y2; y++) {
+        for (int x = x1; x <= x2; x++) {
+            /* The order of bits is MSB first
+                        MSB           LSB
+               bits      7 6 5 4 3 2 1 0
+               pixels    0 1 2 3 4 5 6 7
+                        Left         Right
+            */
+            bool chroma_color = (px_map[(hor_res >> 3) * y  + (x >> 3)] & 1 << (7 - x % 8));
+
+            /* Write to the buffer as required for the display.
+            * It writes only 1-bit for monochrome displays mapped vertically.*/
+            uint8_t *buf = oled_buffer + hor_res * (y >> 3) + (x);
+            if (chroma_color) {
+                (*buf) &= ~(1 << (y % 8));
+            } else {
+                (*buf) |= (1 << (y % 8));
+            }
+        }
+    }
+    // pass the draw buffer to the driver
+    esp_lcd_panel_draw_bitmap(panel_handle, x1, y1, x2 + 1, y2 + 1, oled_buffer);
+}
+
+static void example_increase_lvgl_tick(void *arg)
+{
+    /* Tell LVGL how many milliseconds has elapsed */
+    lv_tick_inc(EXAMPLE_LVGL_TICK_PERIOD_MS);
+}
+
+static void example_lvgl_port_task(void *arg)
+{
+    ESP_LOGI(TAG, "Starting LVGL task");
+    uint32_t time_till_next_ms = 0;
+    while (1) {
+        _lock_acquire(&lvgl_api_lock);
+        time_till_next_ms = lv_timer_handler();
+        _lock_release(&lvgl_api_lock);
+        usleep(1000 * time_till_next_ms);
+    }
+}
+
 void app_main(void)
 {
     ESP_LOGI(TAG, "Initialize I2C bus");
@@ -107,33 +182,48 @@ void app_main(void)
 #endif
 
     ESP_LOGI(TAG, "Initialize LVGL");
-    const lvgl_port_cfg_t lvgl_cfg = ESP_LVGL_PORT_INIT_CONFIG();
-    lvgl_port_init(&lvgl_cfg);
-
-    const lvgl_port_display_cfg_t disp_cfg = {
-        .io_handle = io_handle,
-        .panel_handle = panel_handle,
-        .buffer_size = EXAMPLE_LCD_H_RES * EXAMPLE_LCD_V_RES,
-        .double_buffer = true,
-        .hres = EXAMPLE_LCD_H_RES,
-        .vres = EXAMPLE_LCD_V_RES,
-        .monochrome = true,
-        .rotation = {
-            .swap_xy = false,
-            .mirror_x = false,
-            .mirror_y = false,
-        }
+    lv_init();
+    // create a lvgl display
+    lv_display_t *display = lv_display_create(EXAMPLE_LCD_H_RES, EXAMPLE_LCD_V_RES);
+    // associate the i2c panel handle to the display
+    lv_display_set_user_data(display, panel_handle);
+    // create draw buffer
+    void *buf = NULL;
+    ESP_LOGI(TAG, "Allocate separate LVGL draw buffers");
+    // LVGL reserves 2 x 4 bytes in the buffer, as these are assumed to be used as a palette.
+    size_t draw_buffer_sz = EXAMPLE_LCD_H_RES * EXAMPLE_LCD_V_RES / 8 + EXAMPLE_LVGL_PALETTE_SIZE;
+    buf = heap_caps_calloc(1, draw_buffer_sz, MALLOC_CAP_INTERNAL);
+    assert(buf);
+
+    // LVGL9 suooprt new monochromatic format.
+    lv_display_set_color_format(display, LV_COLOR_FORMAT_I1);
+    // initialize LVGL draw buffers
+    lv_display_set_buffers(display, buf, NULL, draw_buffer_sz, LV_DISPLAY_RENDER_MODE_FULL);
+    // set the callback which can copy the rendered image to an area of the display
+    lv_display_set_flush_cb(display, example_lvgl_flush_cb);
+
+    ESP_LOGI(TAG, "Register io panel event callback for LVGL flush ready notification");
+    const esp_lcd_panel_io_callbacks_t cbs = {
+        .on_color_trans_done = example_notify_lvgl_flush_ready,
     };
-    lv_disp_t *disp = lvgl_port_add_disp(&disp_cfg);
+    /* Register done callback */
+    esp_lcd_panel_io_register_event_callbacks(io_handle, &cbs, display);
 
-    /* Rotation of the screen */
-    lv_disp_set_rotation(disp, LV_DISP_ROT_NONE);
+    ESP_LOGI(TAG, "Use esp_timer as LVGL tick timer");
+    const esp_timer_create_args_t lvgl_tick_timer_args = {
+        .callback = &example_increase_lvgl_tick,
+        .name = "lvgl_tick"
+    };
+    esp_timer_handle_t lvgl_tick_timer = NULL;
+    ESP_ERROR_CHECK(esp_timer_create(&lvgl_tick_timer_args, &lvgl_tick_timer));
+    ESP_ERROR_CHECK(esp_timer_start_periodic(lvgl_tick_timer, EXAMPLE_LVGL_TICK_PERIOD_MS * 1000));
+
+    ESP_LOGI(TAG, "Create LVGL task");
+    xTaskCreate(example_lvgl_port_task, "LVGL", EXAMPLE_LVGL_TASK_STACK_SIZE, NULL, EXAMPLE_LVGL_TASK_PRIORITY, NULL);
 
     ESP_LOGI(TAG, "Display LVGL Scroll Text");
     // Lock the mutex due to the LVGL APIs are not thread-safe
-    if (lvgl_port_lock(0)) {
-        example_lvgl_demo_ui(disp);
-        // Release the mutex
-        lvgl_port_unlock();
-    }
+    _lock_acquire(&lvgl_api_lock);
+    example_lvgl_demo_ui(display);
+    _lock_release(&lvgl_api_lock);
 }
diff --git a/examples/peripherals/lcd/i2c_oled/main/idf_component.yml b/examples/peripherals/lcd/i2c_oled/main/idf_component.yml
index c890e61f8d8..b8408dba26b 100644
--- a/examples/peripherals/lcd/i2c_oled/main/idf_component.yml
+++ b/examples/peripherals/lcd/i2c_oled/main/idf_component.yml
@@ -1,4 +1,3 @@
 dependencies:
-  lvgl/lvgl: "~8.3.0"
+  lvgl/lvgl: "9.2.0"
   esp_lcd_sh1107: "^1"
-  esp_lvgl_port: "^1"
diff --git a/examples/peripherals/lcd/i2c_oled/main/lvgl_demo_ui.c b/examples/peripherals/lcd/i2c_oled/main/lvgl_demo_ui.c
index 251ef5bc977..743711ea527 100644
--- a/examples/peripherals/lcd/i2c_oled/main/lvgl_demo_ui.c
+++ b/examples/peripherals/lcd/i2c_oled/main/lvgl_demo_ui.c
@@ -1,18 +1,18 @@
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: CC0-1.0
  */
 
 #include "lvgl.h"
 
-void example_lvgl_demo_ui(lv_disp_t *disp)
+void example_lvgl_demo_ui(lv_display_t *disp)
 {
-    lv_obj_t *scr = lv_disp_get_scr_act(disp);
+    lv_obj_t *scr = lv_display_get_screen_active(disp);
     lv_obj_t *label = lv_label_create(scr);
     lv_label_set_long_mode(label, LV_LABEL_LONG_SCROLL_CIRCULAR); /* Circular scroll */
     lv_label_set_text(label, "Hello Espressif, Hello LVGL.");
-    /* Size of the screen (if you use rotation 90 or 270, please set disp->driver->ver_res) */
-    lv_obj_set_width(label, disp->driver->hor_res);
+    /* Size of the screen (if you use rotation 90 or 270, please use lv_display_get_vertical_resolution) */
+    lv_obj_set_width(label, lv_display_get_horizontal_resolution(disp));
     lv_obj_align(label, LV_ALIGN_TOP_MID, 0, 0);
 }
diff --git a/examples/peripherals/lcd/i2c_oled/sdkconfig.defaults b/examples/peripherals/lcd/i2c_oled/sdkconfig.defaults
index d92efacc716..dd302d9c638 100644
--- a/examples/peripherals/lcd/i2c_oled/sdkconfig.defaults
+++ b/examples/peripherals/lcd/i2c_oled/sdkconfig.defaults
@@ -1,5 +1,6 @@
 # This file was generated using idf.py save-defconfig. It can be edited manually.
 # Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
 #
-CONFIG_LV_USE_USER_DATA=y
-CONFIG_LV_COLOR_DEPTH_1=y
+CONFIG_LV_CONF_SKIP=y
+CONFIG_LV_USE_OBSERVER=y
+CONFIG_LV_USE_SYSMON=y
diff --git a/examples/peripherals/lcd/i80_controller/main/idf_component.yml b/examples/peripherals/lcd/i80_controller/main/idf_component.yml
index 982d037d375..f57987ae6bf 100644
--- a/examples/peripherals/lcd/i80_controller/main/idf_component.yml
+++ b/examples/peripherals/lcd/i80_controller/main/idf_component.yml
@@ -1,2 +1,2 @@
 dependencies:
-  lvgl/lvgl: "~8.4.0"
+  lvgl/lvgl: "8.4.0"
diff --git a/examples/peripherals/lcd/mipi_dsi/main/idf_component.yml b/examples/peripherals/lcd/mipi_dsi/main/idf_component.yml
index 856f24237a4..b445b5e83e8 100644
--- a/examples/peripherals/lcd/mipi_dsi/main/idf_component.yml
+++ b/examples/peripherals/lcd/mipi_dsi/main/idf_component.yml
@@ -1,4 +1,4 @@
 dependencies:
-  lvgl/lvgl: "~9.2.0"
+  lvgl/lvgl: "9.2.0"
   esp_lcd_ili9881c: "^1.0.0"
   esp_lcd_ek79007: "^1.0.0"
diff --git a/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c b/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c
index 8ae435e7e49..80f8e08f81c 100644
--- a/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c
+++ b/examples/peripherals/lcd/mipi_dsi/main/mipi_dsi_lcd_example_main.c
@@ -216,7 +216,7 @@ void app_main(void)
         .virtual_channel = 0,
         .dpi_clk_src = MIPI_DSI_DPI_CLK_SRC_DEFAULT,
         .dpi_clock_freq_mhz = EXAMPLE_MIPI_DSI_DPI_CLK_MHZ,
-        .pixel_format = LCD_COLOR_PIXEL_FORMAT_RGB888,
+        .in_color_format = LCD_COLOR_FMT_RGB888,
         .video_timing = {
             .h_size = EXAMPLE_MIPI_DSI_LCD_H_RES,
             .v_size = EXAMPLE_MIPI_DSI_LCD_V_RES,
diff --git a/examples/peripherals/lcd/rgb_panel/README.md b/examples/peripherals/lcd/rgb_panel/README.md
index 97b99154613..dcc4b947e2d 100644
--- a/examples/peripherals/lcd/rgb_panel/README.md
+++ b/examples/peripherals/lcd/rgb_panel/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-S3 |
-| ----------------- | -------- |
+| Supported Targets | ESP32-P4 | ESP32-S3 |
+| ----------------- | -------- | -------- |
 
 # RGB LCD Panel Example
 
@@ -19,8 +19,8 @@ This example uses 3 kinds of **buffering mode**:
 
 ### Hardware Required
 
-* An ESP development board, which has RGB LCD peripheral supported and **Octal PSRAM** onboard
-* A general RGB panel, 16 bit-width, with HSYNC, VSYNC and DE signal
+* An ESP development board, which supports the RGB LCD peripheral
+* A general RGB panel, 16/24 bit-width, with HSYNC, VSYNC and DE signal
 * An USB cable for power supply and programming
 
 ### Hardware Connection
@@ -36,7 +36,7 @@ The connection between ESP Board and the LCD is as follows:
 |                       |              |                   |
 |                   PCLK+--------------+PCLK               |
 |                       |              |                   |
-|             DATA[15:0]+--------------+DATA[15:0]         |
+|              DATA[N:0]+--------------+DATA[N:0]          |
 |                       |              |                   |
 |                  HSYNC+--------------+HSYNC              |
 |                       |              |                   |
@@ -55,9 +55,9 @@ The connection between ESP Board and the LCD is as follows:
 
 Run `idf.py menuconfig` and go to `Example Configuration`:
 
-1. Choose whether to `Use double Frame Buffer`
-2. Choose whether to `Avoid tearing effect` (available only when step `1` was chosen to false)
-3. Choose whether to `Use bounce buffer` (available only when step `1` was chosen to false)
+1. `Use single frame buffer`: The RGB LCD driver allocates one frame buffer and mount it to the DMA. The example also allocates one draw buffer for the LVGL library. The draw buffer contents are copied to the frame buffer by the CPU.
+2. `Use double frame buffer`: The RGB LCD driver allocates two frame buffers and mount them to the DMA. The LVGL library draws directly to the offline frame buffer while the online frame buffer is displayed by the RGB LCD controller.
+3. `Use bounce buffer`: The RGB LCD driver allocates one frame buffer and two bounce buffers. The bounce buffers are mounted to the DMA. The frame buffer contents are copied to the bounce buffers by the CPU. The example also allocates one draw buffer for the LVGL library. The draw buffer contents are copied to the frame buffer by the CPU.
 4. Choose the number of LCD data lines in `RGB LCD Data Lines`
 5. Set the GPIOs used by RGB LCD peripheral in `GPIO assignment`, e.g. the synchronization signals (HSYNC, VSYNC, DE) and the data lines
 
@@ -97,16 +97,13 @@ I (1102) main_task: Returned from app_main()
 
 * Why the LCD doesn't light up?
   * Please pay attention to the level used to turn on the LCD backlight, some LCD module needs a low level to turn it on, while others take a high level. You can change the backlight level macro `EXAMPLE_LCD_BK_LIGHT_ON_LEVEL` in [lvgl_example_main.c](main/rgb_lcd_example_main.c).
-* No memory for frame buffer
+* Where to allocate the frame buffer?
   * The frame buffer of RGB panel is located in ESP side (unlike other controller based LCDs, where the frame buffer is located in external chip). As the frame buffer usually consumes much RAM (depends on the LCD resolution and color depth), we recommend to put the frame buffer into PSRAM (like what we do in this example). However, putting frame buffer in PSRAM will limit the maximum PCLK due to the bandwidth of **SPI0**.
-* LCD screen drift
+* Why LCD screen drifts?
   * Slow down the PCLK frequency
   * Adjust other timing parameters like PCLK clock edge (by `pclk_active_neg`), sync porches like VBP (by `vsync_back_porch`) according to your LCD spec
-  * Enable `CONFIG_SPIRAM_FETCH_INSTRUCTIONS` and `CONFIG_SPIRAM_RODATA`, which can saves some bandwidth of SPI0 from being consumed by ICache.
-* LCD screen tear effect
-  * Using double frame buffers
-  * Or adding an extra synchronization mechanism between writing (by Cache) and reading (by EDMA) the frame buffer.
-* Low PCLK frequency
+  * Enable `CONFIG_SPIRAM_XIP_FROM_PSRAM`, which can saves some bandwidth of SPI0 from being consumed by ICache.
+* How to further increase the PCLK frequency?
   * Enable `CONFIG_EXAMPLE_USE_BOUNCE_BUFFER`, which will make the LCD controller fetch data from internal SRAM (instead of the PSRAM), but at the cost of increasing CPU usage.
   * Enable `CONFIG_SPIRAM_XIP_FROM_PSRAM` can also help if the you're not using the bounce buffer mode. These two configurations can save some **SPI0** bandwidth from being consumed by ICache.
 * Why the RGB timing is correct but the LCD doesn't show anything?
diff --git a/examples/peripherals/lcd/rgb_panel/main/Kconfig.projbuild b/examples/peripherals/lcd/rgb_panel/main/Kconfig.projbuild
index 34415bb278c..5dc913d6da3 100644
--- a/examples/peripherals/lcd/rgb_panel/main/Kconfig.projbuild
+++ b/examples/peripherals/lcd/rgb_panel/main/Kconfig.projbuild
@@ -1,23 +1,29 @@
 menu "Example Configuration"
-    config EXAMPLE_DOUBLE_FB
-        bool "Use double Frame Buffer"
-        default "n"
+    choice EXAMPLE_LCD_BUFFER_MODE
+        prompt "RGB LCD Buffer Mode"
+        default EXAMPLE_USE_SINGLE_FB
         help
-            Enable this option, driver will allocate two frame buffers.
+            Select the LCD buffer mode.
 
-    config EXAMPLE_USE_BOUNCE_BUFFER
-        depends on !EXAMPLE_DOUBLE_FB
-        bool "Use bounce buffer"
-        help
-            Enable bounce buffer mode can achieve higher PCLK frequency at the cost of higher CPU consumption.
+        config EXAMPLE_USE_SINGLE_FB
+            bool "Use single frame buffer"
+            help
+                Allocate one frame buffer in the driver.
+                Allocate one draw buffer in LVGL.
 
-    config EXAMPLE_AVOID_TEAR_EFFECT_WITH_SEM
-        depends on !EXAMPLE_DOUBLE_FB
-        bool "Avoid tearing effect"
-        default "y"
-        help
-            Enable this option, the example will use a pair of semaphores to avoid the tearing effect.
-            Note, if the Double Frame Buffer is used, then we can also avoid the tearing effect without the lock.
+        config EXAMPLE_USE_DOUBLE_FB
+            bool "Use double frame buffer"
+            help
+                Allocate two frame buffers in the driver.
+                The frame buffers also work as ping-pong draw buffers in LVGL.
+
+        config EXAMPLE_USE_BOUNCE_BUFFER
+            bool "Use bounce buffer"
+            help
+                Allocate one frame buffer in the driver.
+                Allocate two bounce buffers in the driver.
+                Allocate one draw buffer in LVGL.
+    endchoice
 
     choice EXAMPLE_LCD_DATA_LINES
         prompt "RGB LCD Data Lines"
@@ -27,11 +33,15 @@ menu "Example Configuration"
 
         config EXAMPLE_LCD_DATA_LINES_16
             bool "16 data lines"
+
+        config EXAMPLE_LCD_DATA_LINES_24
+            bool "24 data lines"
     endchoice
 
     config EXAMPLE_LCD_DATA_LINES
         int
         default 16 if EXAMPLE_LCD_DATA_LINES_16
+        default 24 if EXAMPLE_LCD_DATA_LINES_24
 
     menu "GPIO assignment"
         config EXAMPLE_LCD_VSYNC_GPIO
@@ -114,5 +124,45 @@ menu "Example Configuration"
             int "DATA15 GPIO"
             help
                 GPIO pin number for data bus[15].
+        config EXAMPLE_LCD_DATA16_GPIO
+            int "DATA16 GPIO"
+            depends on EXAMPLE_LCD_DATA_LINES > 16
+            help
+                GPIO pin number for data bus[16].
+        config EXAMPLE_LCD_DATA17_GPIO
+            int "DATA17 GPIO"
+            depends on EXAMPLE_LCD_DATA_LINES > 16
+            help
+                GPIO pin number for data bus[17].
+        config EXAMPLE_LCD_DATA18_GPIO
+            int "DATA18 GPIO"
+            depends on EXAMPLE_LCD_DATA_LINES > 16
+            help
+                GPIO pin number for data bus[18].
+        config EXAMPLE_LCD_DATA19_GPIO
+            int "DATA19 GPIO"
+            depends on EXAMPLE_LCD_DATA_LINES > 16
+            help
+                GPIO pin number for data bus[19].
+        config EXAMPLE_LCD_DATA20_GPIO
+            int "DATA20 GPIO"
+            depends on EXAMPLE_LCD_DATA_LINES > 16
+            help
+                GPIO pin number for data bus[20].
+        config EXAMPLE_LCD_DATA21_GPIO
+            int "DATA21 GPIO"
+            depends on EXAMPLE_LCD_DATA_LINES > 16
+            help
+                GPIO pin number for data bus[21].
+        config EXAMPLE_LCD_DATA22_GPIO
+            int "DATA22 GPIO"
+            depends on EXAMPLE_LCD_DATA_LINES > 16
+            help
+                GPIO pin number for data bus[22].
+        config EXAMPLE_LCD_DATA23_GPIO
+            int "DATA23 GPIO"
+            depends on EXAMPLE_LCD_DATA_LINES > 16
+            help
+                GPIO pin number for data bus[23].
     endmenu
 endmenu
diff --git a/examples/peripherals/lcd/rgb_panel/main/idf_component.yml b/examples/peripherals/lcd/rgb_panel/main/idf_component.yml
index f929e7f74a0..4ca86dce7ec 100644
--- a/examples/peripherals/lcd/rgb_panel/main/idf_component.yml
+++ b/examples/peripherals/lcd/rgb_panel/main/idf_component.yml
@@ -1,2 +1,2 @@
 dependencies:
-  lvgl/lvgl: "~9.2.0"
+  lvgl/lvgl: "9.2.0"
diff --git a/examples/peripherals/lcd/rgb_panel/main/rgb_lcd_example_main.c b/examples/peripherals/lcd/rgb_panel/main/rgb_lcd_example_main.c
index 8823c8c01d0..d9b983617d2 100644
--- a/examples/peripherals/lcd/rgb_panel/main/rgb_lcd_example_main.c
+++ b/examples/peripherals/lcd/rgb_panel/main/rgb_lcd_example_main.c
@@ -10,7 +10,6 @@
 #include "sdkconfig.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
-#include "freertos/semphr.h"
 #include "esp_timer.h"
 #include "esp_lcd_panel_ops.h"
 #include "esp_lcd_panel_rgb.h"
@@ -61,17 +60,31 @@ static const char *TAG = "example";
 #define EXAMPLE_PIN_NUM_DATA13         CONFIG_EXAMPLE_LCD_DATA13_GPIO
 #define EXAMPLE_PIN_NUM_DATA14         CONFIG_EXAMPLE_LCD_DATA14_GPIO
 #define EXAMPLE_PIN_NUM_DATA15         CONFIG_EXAMPLE_LCD_DATA15_GPIO
+#if CONFIG_EXAMPLE_LCD_DATA_LINES > 16
+#define EXAMPLE_PIN_NUM_DATA16         CONFIG_EXAMPLE_LCD_DATA16_GPIO
+#define EXAMPLE_PIN_NUM_DATA17         CONFIG_EXAMPLE_LCD_DATA17_GPIO
+#define EXAMPLE_PIN_NUM_DATA18         CONFIG_EXAMPLE_LCD_DATA18_GPIO
+#define EXAMPLE_PIN_NUM_DATA19         CONFIG_EXAMPLE_LCD_DATA19_GPIO
+#define EXAMPLE_PIN_NUM_DATA20         CONFIG_EXAMPLE_LCD_DATA20_GPIO
+#define EXAMPLE_PIN_NUM_DATA21         CONFIG_EXAMPLE_LCD_DATA21_GPIO
+#define EXAMPLE_PIN_NUM_DATA22         CONFIG_EXAMPLE_LCD_DATA22_GPIO
+#define EXAMPLE_PIN_NUM_DATA23         CONFIG_EXAMPLE_LCD_DATA23_GPIO
+#endif
 
-#if CONFIG_EXAMPLE_DOUBLE_FB
+#if CONFIG_EXAMPLE_USE_DOUBLE_FB
 #define EXAMPLE_LCD_NUM_FB             2
 #else
 #define EXAMPLE_LCD_NUM_FB             1
-#endif // CONFIG_EXAMPLE_DOUBLE_FB
+#endif // CONFIG_EXAMPLE_USE_DOUBLE_FB
 
 #if CONFIG_EXAMPLE_LCD_DATA_LINES_16
 #define EXAMPLE_DATA_BUS_WIDTH         16
 #define EXAMPLE_PIXEL_SIZE             2
 #define EXAMPLE_LV_COLOR_FORMAT        LV_COLOR_FORMAT_RGB565
+#elif CONFIG_EXAMPLE_LCD_DATA_LINES_24
+#define EXAMPLE_DATA_BUS_WIDTH         24
+#define EXAMPLE_PIXEL_SIZE             3
+#define EXAMPLE_LV_COLOR_FORMAT        LV_COLOR_FORMAT_RGB888
 #endif
 
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -86,23 +99,13 @@ static const char *TAG = "example";
 // LVGL library is not thread-safe, this example will call LVGL APIs from different tasks, so use a mutex to protect it
 static _lock_t lvgl_api_lock;
 
-// we use two semaphores to sync the VSYNC event and the LVGL task, to avoid potential tearing effect
-#if CONFIG_EXAMPLE_AVOID_TEAR_EFFECT_WITH_SEM
-SemaphoreHandle_t sem_vsync_end;
-SemaphoreHandle_t sem_gui_ready;
-#endif
-
 extern void example_lvgl_demo_ui(lv_display_t *disp);
 
-static bool example_on_vsync_event(esp_lcd_panel_handle_t panel, const esp_lcd_rgb_panel_event_data_t *event_data, void *user_data)
+static bool example_notify_lvgl_flush_ready(esp_lcd_panel_handle_t panel, const esp_lcd_rgb_panel_event_data_t *event_data, void *user_ctx)
 {
-    BaseType_t high_task_awoken = pdFALSE;
-#if CONFIG_EXAMPLE_AVOID_TEAR_EFFECT_WITH_SEM
-    if (xSemaphoreTakeFromISR(sem_gui_ready, &high_task_awoken) == pdTRUE) {
-        xSemaphoreGiveFromISR(sem_vsync_end, &high_task_awoken);
-    }
-#endif
-    return high_task_awoken == pdTRUE;
+    lv_display_t *disp = (lv_display_t *)user_ctx;
+    lv_display_flush_ready(disp);
+    return false;
 }
 
 static void example_lvgl_flush_cb(lv_display_t *disp, const lv_area_t *area, uint8_t *px_map)
@@ -112,13 +115,8 @@ static void example_lvgl_flush_cb(lv_display_t *disp, const lv_area_t *area, uin
     int offsetx2 = area->x2;
     int offsety1 = area->y1;
     int offsety2 = area->y2;
-#if CONFIG_EXAMPLE_AVOID_TEAR_EFFECT_WITH_SEM
-    xSemaphoreGive(sem_gui_ready);
-    xSemaphoreTake(sem_vsync_end, portMAX_DELAY);
-#endif
     // pass the draw buffer to the driver
     esp_lcd_panel_draw_bitmap(panel_handle, offsetx1, offsety1, offsetx2 + 1, offsety2 + 1, px_map);
-    lv_display_flush_ready(disp);
 }
 
 static void example_increase_lvgl_tick(void *arg)
@@ -165,14 +163,6 @@ static void example_bsp_set_lcd_backlight(uint32_t level)
 
 void app_main(void)
 {
-#if CONFIG_EXAMPLE_AVOID_TEAR_EFFECT_WITH_SEM
-    ESP_LOGI(TAG, "Create semaphores");
-    sem_vsync_end = xSemaphoreCreateBinary();
-    assert(sem_vsync_end);
-    sem_gui_ready = xSemaphoreCreateBinary();
-    assert(sem_gui_ready);
-#endif
-
     ESP_LOGI(TAG, "Turn off LCD backlight");
     example_bsp_init_lcd_backlight();
     example_bsp_set_lcd_backlight(EXAMPLE_LCD_BK_LIGHT_OFF_LEVEL);
@@ -209,6 +199,16 @@ void app_main(void)
             EXAMPLE_PIN_NUM_DATA13,
             EXAMPLE_PIN_NUM_DATA14,
             EXAMPLE_PIN_NUM_DATA15,
+#if CONFIG_EXAMPLE_LCD_DATA_LINES > 16
+            EXAMPLE_PIN_NUM_DATA16,
+            EXAMPLE_PIN_NUM_DATA17,
+            EXAMPLE_PIN_NUM_DATA18,
+            EXAMPLE_PIN_NUM_DATA19,
+            EXAMPLE_PIN_NUM_DATA20,
+            EXAMPLE_PIN_NUM_DATA21,
+            EXAMPLE_PIN_NUM_DATA22,
+            EXAMPLE_PIN_NUM_DATA23
+#endif
         },
         .timings = {
             .pclk_hz = EXAMPLE_LCD_PIXEL_CLOCK_HZ,
@@ -246,7 +246,7 @@ void app_main(void)
     // create draw buffers
     void *buf1 = NULL;
     void *buf2 = NULL;
-#if CONFIG_EXAMPLE_DOUBLE_FB
+#if CONFIG_EXAMPLE_USE_DOUBLE_FB
     ESP_LOGI(TAG, "Use frame buffers as LVGL draw buffers");
     ESP_ERROR_CHECK(esp_lcd_rgb_panel_get_frame_buffer(panel_handle, 2, &buf1, &buf2));
     // set LVGL draw buffers and direct mode
@@ -259,14 +259,14 @@ void app_main(void)
     assert(buf1);
     // set LVGL draw buffers and partial mode
     lv_display_set_buffers(display, buf1, buf2, draw_buffer_sz, LV_DISPLAY_RENDER_MODE_PARTIAL);
-#endif // CONFIG_EXAMPLE_DOUBLE_FB
+#endif // CONFIG_EXAMPLE_USE_DOUBLE_FB
 
     // set the callback which can copy the rendered image to an area of the display
     lv_display_set_flush_cb(display, example_lvgl_flush_cb);
 
     ESP_LOGI(TAG, "Register event callbacks");
     esp_lcd_rgb_panel_event_callbacks_t cbs = {
-        .on_vsync = example_on_vsync_event,
+        .on_color_trans_done = example_notify_lvgl_flush_ready,
     };
     ESP_ERROR_CHECK(esp_lcd_rgb_panel_register_event_callbacks(panel_handle, &cbs, display));
 
diff --git a/examples/peripherals/lcd/rgb_panel/pytest_rgb_panel_lvgl.py b/examples/peripherals/lcd/rgb_panel/pytest_rgb_panel_lvgl.py
index 7b0c751ee55..d9af5c60c31 100644
--- a/examples/peripherals/lcd/rgb_panel/pytest_rgb_panel_lvgl.py
+++ b/examples/peripherals/lcd/rgb_panel/pytest_rgb_panel_lvgl.py
@@ -15,7 +15,29 @@
     ],
     indirect=True,
 )
-def test_rgb_lcd_lvgl(dut: Dut) -> None:
+def test_rgb_lcd_lvgl_esp32s3(dut: Dut) -> None:
+    dut.expect_exact('example: Turn off LCD backlight')
+    dut.expect_exact('example: Install RGB LCD panel driver')
+    dut.expect_exact('example: Initialize RGB LCD panel')
+    dut.expect_exact('example: Turn on LCD backlight')
+    dut.expect_exact('example: Initialize LVGL library')
+    dut.expect_exact('example: Install LVGL tick timer')
+    dut.expect_exact('example: Create LVGL task')
+    dut.expect_exact('example: Display LVGL UI')
+
+
+@pytest.mark.esp32p4
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'single_fb_with_bb',
+        'single_fb_no_bb',
+        'double_fb',
+    ],
+    indirect=True,
+)
+def test_rgb_lcd_lvgl_esp32p4(dut: Dut) -> None:
     dut.expect_exact('example: Turn off LCD backlight')
     dut.expect_exact('example: Install RGB LCD panel driver')
     dut.expect_exact('example: Initialize RGB LCD panel')
diff --git a/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.double_fb b/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.double_fb
index 12cbd3b12c5..5f206e08193 100644
--- a/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.double_fb
+++ b/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.double_fb
@@ -1 +1 @@
-CONFIG_EXAMPLE_DOUBLE_FB=y
+CONFIG_EXAMPLE_USE_DOUBLE_FB=y
diff --git a/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.single_fb_no_bb b/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.single_fb_no_bb
index 097e4478f9c..0244809f4cd 100644
--- a/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.single_fb_no_bb
+++ b/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.single_fb_no_bb
@@ -1,2 +1 @@
-CONFIG_EXAMPLE_DOUBLE_FB=n
-CONFIG_EXAMPLE_USE_BOUNCE_BUFFER=n
+CONFIG_EXAMPLE_USE_SINGLE_FB=y
diff --git a/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.single_fb_with_bb b/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.single_fb_with_bb
index 1bd247da1c4..9257f289a3a 100644
--- a/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.single_fb_with_bb
+++ b/examples/peripherals/lcd/rgb_panel/sdkconfig.ci.single_fb_with_bb
@@ -1,2 +1 @@
-CONFIG_EXAMPLE_DOUBLE_FB=n
 CONFIG_EXAMPLE_USE_BOUNCE_BUFFER=y
diff --git a/examples/peripherals/lcd/rgb_panel/sdkconfig.defaults.esp32p4 b/examples/peripherals/lcd/rgb_panel/sdkconfig.defaults.esp32p4
new file mode 100644
index 00000000000..b5b09d8c107
--- /dev/null
+++ b/examples/peripherals/lcd/rgb_panel/sdkconfig.defaults.esp32p4
@@ -0,0 +1,46 @@
+# enable the experimental features for higher PSRAM speed
+CONFIG_IDF_EXPERIMENTAL_FEATURES=y
+
+CONFIG_SPIRAM=y
+CONFIG_SPIRAM_MODE_HEX=y
+CONFIG_SPIRAM_SPEED_200M=y
+
+# LCD_CAM support 24 data lines at most
+CONFIG_EXAMPLE_LCD_DATA_LINES_24=y
+CONFIG_LV_COLOR_DEPTH_24=y
+
+# Default GPIO assignment
+CONFIG_EXAMPLE_LCD_VSYNC_GPIO=41
+CONFIG_EXAMPLE_LCD_HSYNC_GPIO=39
+CONFIG_EXAMPLE_LCD_DE_GPIO=43
+CONFIG_EXAMPLE_LCD_PCLK_GPIO=33
+
+# B0:B7 <=> DATA0:DATA7
+CONFIG_EXAMPLE_LCD_DATA0_GPIO=34
+CONFIG_EXAMPLE_LCD_DATA1_GPIO=12
+CONFIG_EXAMPLE_LCD_DATA2_GPIO=10
+CONFIG_EXAMPLE_LCD_DATA3_GPIO=40
+CONFIG_EXAMPLE_LCD_DATA4_GPIO=42
+CONFIG_EXAMPLE_LCD_DATA5_GPIO=27
+CONFIG_EXAMPLE_LCD_DATA6_GPIO=29
+CONFIG_EXAMPLE_LCD_DATA7_GPIO=31
+
+# G0:G7 <=> DATA8:DATA15
+CONFIG_EXAMPLE_LCD_DATA8_GPIO=16
+CONFIG_EXAMPLE_LCD_DATA9_GPIO=14
+CONFIG_EXAMPLE_LCD_DATA10_GPIO=21
+CONFIG_EXAMPLE_LCD_DATA11_GPIO=23
+CONFIG_EXAMPLE_LCD_DATA12_GPIO=26
+CONFIG_EXAMPLE_LCD_DATA13_GPIO=28
+CONFIG_EXAMPLE_LCD_DATA14_GPIO=30
+CONFIG_EXAMPLE_LCD_DATA15_GPIO=32
+
+# R0:R7 <=> DATA16:DATA23
+CONFIG_EXAMPLE_LCD_DATA16_GPIO=22
+CONFIG_EXAMPLE_LCD_DATA17_GPIO=20
+CONFIG_EXAMPLE_LCD_DATA18_GPIO=18
+CONFIG_EXAMPLE_LCD_DATA19_GPIO=6
+CONFIG_EXAMPLE_LCD_DATA20_GPIO=0
+CONFIG_EXAMPLE_LCD_DATA21_GPIO=15
+CONFIG_EXAMPLE_LCD_DATA22_GPIO=17
+CONFIG_EXAMPLE_LCD_DATA23_GPIO=19
diff --git a/examples/peripherals/lcd/spi_lcd_touch/main/idf_component.yml b/examples/peripherals/lcd/spi_lcd_touch/main/idf_component.yml
index 1ce88fe63e8..9f43889e3d1 100644
--- a/examples/peripherals/lcd/spi_lcd_touch/main/idf_component.yml
+++ b/examples/peripherals/lcd/spi_lcd_touch/main/idf_component.yml
@@ -1,5 +1,5 @@
 dependencies:
-  lvgl/lvgl: "~9.2.0"
+  lvgl/lvgl: "9.2.0"
   esp_lcd_ili9341: "^1.0"
   esp_lcd_gc9a01: "^1.0"
   esp_lcd_touch_stmpe610: "^1.0"
diff --git a/examples/peripherals/mcpwm/mcpwm_sync/main/mcpwm_sync_example_main.c b/examples/peripherals/mcpwm/mcpwm_sync/main/mcpwm_sync_example_main.c
index c05aa0e0000..bb7279d0f75 100644
--- a/examples/peripherals/mcpwm/mcpwm_sync/main/mcpwm_sync_example_main.c
+++ b/examples/peripherals/mcpwm/mcpwm_sync/main/mcpwm_sync_example_main.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -28,6 +28,12 @@ static void example_setup_sync_strategy(mcpwm_timer_handle_t timers[])
     //    |     |      |
     //    v     v      v
     // timer0 timer1 timer2
+    gpio_config_t sync_gpio_conf = {
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = BIT(EXAMPLE_SYNC_GPIO),
+    };
+    ESP_ERROR_CHECK(gpio_config(&sync_gpio_conf));
+
     ESP_LOGI(TAG, "Create GPIO sync source");
     mcpwm_sync_handle_t gpio_sync_source = NULL;
     mcpwm_gpio_sync_src_config_t gpio_sync_config = {
@@ -35,7 +41,6 @@ static void example_setup_sync_strategy(mcpwm_timer_handle_t timers[])
         .gpio_num = EXAMPLE_SYNC_GPIO,
         .flags.pull_down = true,
         .flags.active_neg = false,  // by default, a posedge pulse can trigger a sync event
-        .flags.io_loop_back = true, // then we can trigger a sync event using `gpio_set_level` on the same GPIO
     };
     ESP_ERROR_CHECK(mcpwm_new_gpio_sync_src(&gpio_sync_config, &gpio_sync_source));
 
@@ -50,8 +55,9 @@ static void example_setup_sync_strategy(mcpwm_timer_handle_t timers[])
     }
 
     ESP_LOGI(TAG, "Trigger a pulse on the GPIO as a sync event");
-    gpio_set_level(EXAMPLE_SYNC_GPIO, 0);
-    gpio_set_level(EXAMPLE_SYNC_GPIO, 1);
+    ESP_ERROR_CHECK(gpio_set_level(EXAMPLE_SYNC_GPIO, 0));
+    ESP_ERROR_CHECK(gpio_set_level(EXAMPLE_SYNC_GPIO, 1));
+    ESP_ERROR_CHECK(gpio_reset_pin(EXAMPLE_SYNC_GPIO));
 }
 #endif // CONFIG_EXAMPLE_SYNC_FROM_GPIO
 
diff --git a/examples/peripherals/parlio/parlio_rx/logic_analyzer/components/esp_probe/hw_impl/esp_probe_impl_parlio.c b/examples/peripherals/parlio/parlio_rx/logic_analyzer/components/esp_probe/hw_impl/esp_probe_impl_parlio.c
index 41de582782c..6ad6b4d238c 100644
--- a/examples/peripherals/parlio/parlio_rx/logic_analyzer/components/esp_probe/hw_impl/esp_probe_impl_parlio.c
+++ b/examples/peripherals/parlio/parlio_rx/logic_analyzer/components/esp_probe/hw_impl/esp_probe_impl_parlio.c
@@ -82,8 +82,6 @@ esp_err_t esp_probe_priv_init_hardware(esp_probe_handle_t handle, esp_probe_conf
         .valid_gpio_num = GPIO_NUM_NC,      // Does not need valid gpio, all data gpio are used as sampling channel
         .flags = {
             .clk_gate_en = false,
-            .io_loop_back = true,
-            .io_no_init = true,
         }
     };
     memcpy(parlio_rx_cfg.data_gpio_nums, config->probe_gpio, PARLIO_RX_UNIT_MAX_DATA_WIDTH * sizeof(gpio_num_t));
diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/Kconfig.projbuild b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/Kconfig.projbuild
new file mode 100644
index 00000000000..1529a312acb
--- /dev/null
+++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/Kconfig.projbuild
@@ -0,0 +1,55 @@
+menu "Example Configuration"
+
+    config EXAMPLE_PIN_NUM_R1
+        int "Red Pin 1"
+        default 7
+
+    config EXAMPLE_PIN_NUM_G1
+        int "Green Pin 1"
+        default 4
+
+    config EXAMPLE_PIN_NUM_B1
+        int "Blue Pin 1"
+        default 1
+
+    config EXAMPLE_PIN_NUM_R2
+        int "Red Pin 2"
+        default 6
+
+    config EXAMPLE_PIN_NUM_G2
+        int "Green Pin 2"
+        default 3
+
+    config EXAMPLE_PIN_NUM_B2
+        int "Blue Pin 2"
+        default 0
+
+    config EXAMPLE_PIN_NUM_LATCH
+        int "Latch Pin"
+        default 5
+
+    config EXAMPLE_PIN_NUM_PCLK
+        int "PCLK Pin"
+        default 10
+
+    config EXAMPLE_PIN_NUM_OE
+        int "OE Pin"
+        default 2
+
+    config EXAMPLE_PIN_NUM_A
+        int "A Pin"
+        default 20
+
+    config EXAMPLE_PIN_NUM_B
+        int "B Pin"
+        default 21
+
+    config EXAMPLE_PIN_NUM_C
+        int "C Pin"
+        default 22
+
+    config EXAMPLE_PIN_NUM_D
+        int "D Pin"
+        default 23
+
+endmenu
diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/idf_component.yml b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/idf_component.yml
index fcdb51a8629..c91c519e780 100644
--- a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/idf_component.yml
+++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/idf_component.yml
@@ -1,3 +1,3 @@
 dependencies:
   idf: ">=5.1"
-  lvgl/lvgl: "~8.3.0"
+  lvgl/lvgl: "9.2.2"
diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/lvgl_demo_ui.c b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/lvgl_demo_ui.c
index 0cd90f48bb1..846fcdf7715 100644
--- a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/lvgl_demo_ui.c
+++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/lvgl_demo_ui.c
@@ -1,25 +1,32 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: CC0-1.0
  */
 
 #include "lvgl.h"
 
-void example_lvgl_demo_ui(lv_disp_t *disp)
+void example_lvgl_demo_ui(lv_display_t *disp)
 {
-    lv_obj_t *scr = lv_disp_get_scr_act(disp);
+    lv_obj_t *scr = lv_display_get_screen_active(disp);
+    static lv_style_t up_style;
+    lv_style_init(&up_style);
     lv_obj_t *up_label = lv_label_create(scr);
-    lv_label_set_recolor(up_label, true);
-    lv_label_set_text(up_label, "#FF0000 Hello# #0000FF World#");
+    lv_style_set_text_color(&up_style, lv_palette_main(LV_PALETTE_RED));
+    lv_obj_add_style(up_label, &up_style, 0);
+    lv_label_set_text(up_label, "Hello World");
     lv_label_set_long_mode(up_label, LV_LABEL_LONG_SCROLL_CIRCULAR); /* Circular scroll */
     /* Size of the screen */
-    lv_obj_set_width(up_label, disp->driver->hor_res);
+    lv_obj_set_width(up_label, lv_display_get_horizontal_resolution(disp));
     lv_obj_align_to(up_label, scr, LV_ALIGN_TOP_MID, 0, 0);
 
+    static lv_style_t low_style;
+    lv_style_init(&low_style);
     lv_obj_t *low_label = lv_label_create(scr);
+    lv_style_set_text_color(&low_style, lv_palette_main(LV_PALETTE_GREEN));
+    lv_obj_add_style(low_label, &low_style, 0);
     lv_label_set_text(low_label, LV_SYMBOL_WIFI LV_SYMBOL_GPS LV_SYMBOL_BATTERY_2 LV_SYMBOL_AUDIO);
     /* Size of the screen */
-    lv_obj_set_width(low_label, disp->driver->hor_res);
+    lv_obj_set_width(low_label, lv_display_get_horizontal_resolution(disp));
     lv_obj_align_to(low_label, scr, LV_ALIGN_BOTTOM_MID, 0, 0);
 }
diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c
index 588f4cb96b8..fa248198e3d 100644
--- a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c
+++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/main/rgb_led_matrix_example_main.c
@@ -1,8 +1,9 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
+#include <string.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "esp_attr.h"
@@ -28,20 +29,21 @@ static const char *TAG = "example";
 #define EXAMPLE_HUB75_B1_IDX     1 // B1 bit position
 #define EXAMPLE_HUB75_B2_IDX     0 // B2 bit position
 // GPIO assignment
-#define EXAMPLE_PIN_NUM_R1       7
-#define EXAMPLE_PIN_NUM_G1       4
-#define EXAMPLE_PIN_NUM_B1       1
-#define EXAMPLE_PIN_NUM_R2       6
-#define EXAMPLE_PIN_NUM_G2       3
-#define EXAMPLE_PIN_NUM_B2       0
-#define EXAMPLE_PIN_NUM_LATCH    5
-#define EXAMPLE_PIN_NUM_OE       2
-#define EXAMPLE_PIN_NUM_PCLK     10
+#define EXAMPLE_PIN_NUM_R1       CONFIG_EXAMPLE_PIN_NUM_R1
+#define EXAMPLE_PIN_NUM_G1       CONFIG_EXAMPLE_PIN_NUM_G1
+#define EXAMPLE_PIN_NUM_B1       CONFIG_EXAMPLE_PIN_NUM_B1
+#define EXAMPLE_PIN_NUM_R2       CONFIG_EXAMPLE_PIN_NUM_R2
+#define EXAMPLE_PIN_NUM_G2       CONFIG_EXAMPLE_PIN_NUM_G2
+#define EXAMPLE_PIN_NUM_B2       CONFIG_EXAMPLE_PIN_NUM_B2
+#define EXAMPLE_PIN_NUM_LATCH    CONFIG_EXAMPLE_PIN_NUM_LATCH
+#define EXAMPLE_PIN_NUM_OE       CONFIG_EXAMPLE_PIN_NUM_OE
+#define EXAMPLE_PIN_NUM_PCLK     CONFIG_EXAMPLE_PIN_NUM_PCLK
 // address signals are powered by fast GPIO module
-#define EXAMPLE_PIN_NUM_A       20
-#define EXAMPLE_PIN_NUM_B       21
-#define EXAMPLE_PIN_NUM_C       22
-#define EXAMPLE_PIN_NUM_D       23
+#define EXAMPLE_PIN_NUM_A        CONFIG_EXAMPLE_PIN_NUM_A
+#define EXAMPLE_PIN_NUM_B        CONFIG_EXAMPLE_PIN_NUM_B
+#define EXAMPLE_PIN_NUM_C        CONFIG_EXAMPLE_PIN_NUM_C
+#define EXAMPLE_PIN_NUM_D        CONFIG_EXAMPLE_PIN_NUM_D
+
 // The pixel clock frequency
 #define EXAMPLE_LED_MATRIX_PIXEL_CLOCK_HZ (10 * 1000 * 1000) // 10MHz
 // The pixel number in horizontal and vertical
@@ -52,42 +54,36 @@ static const char *TAG = "example";
 #define EXAMPLE_GPTIMER_RESOLUTION_HZ  (1 * 1000 * 1000) // 1MHz
 #define EXAMPLE_LVGL_TICK_PERIOD_MS    5 // 5ms
 
-// 0x92: we pick the first bit of each RGB element in the order of 3-3-2, that's 0b10010010
-// p1: pixel on the upper half screen
-// p2: pixel on the lower half screen
-// OE=1: disable the output
-#define MERGE_TWO_LVGL_PIXELS(p1, p2)          \
-    do                                         \
-    {                                          \
-        p1->full &= 0x92;                      \
-        p1->full |= (p2->full & 0x92) >> 1;    \
-        p1->full |= 1 << EXAMPLE_HUB75_OE_IDX; \
-    } while (0)
+// LED Matrix frame buffer, we use a dedicated task to flush this frame buffer
+static uint8_t s_frame_buffer[EXAMPLE_LED_MATRIX_H_RES * EXAMPLE_LED_MATRIX_V_RES / 2] = {};
 
-extern void example_lvgl_demo_ui(lv_disp_t *disp);
+// upper_half: pixel on the upper half screen
+// lower_half: pixel on the lower half screen
+static void merge_two_pixels(lv_color16_t *upper_half, lv_color16_t *lower_half, int index)
+{
+    s_frame_buffer[index]  = (upper_half->red >> 4) << EXAMPLE_HUB75_R1_IDX | (upper_half->green >> 5) << EXAMPLE_HUB75_G1_IDX | (upper_half->blue >> 4) << EXAMPLE_HUB75_B1_IDX;
+    s_frame_buffer[index] |= (lower_half->red >> 4) << EXAMPLE_HUB75_R2_IDX | (lower_half->green >> 5) << EXAMPLE_HUB75_G2_IDX | (lower_half->blue >> 4) << EXAMPLE_HUB75_B2_IDX;
+    // OE=1: enable the output
+    s_frame_buffer[index] |= 1 << EXAMPLE_HUB75_OE_IDX;
+}
 
-// LED Matrix frame buffer, we use a dedicated task to flush this frame buffer
-static lv_color_t s_frame_buffer[EXAMPLE_LED_MATRIX_H_RES * EXAMPLE_LED_MATRIX_V_RES / 2];
+extern void example_lvgl_demo_ui(lv_display_t *disp);
 
-static void example_lvgl_flush_cb(lv_disp_drv_t *drv, const lv_area_t *area, lv_color_t *color_map)
+static void example_lvgl_flush_cb(lv_display_t *display, const lv_area_t *area, uint8_t *color_map)
 {
-    lv_color_t *upper_half = color_map;
-    lv_color_t *lower_half = color_map + EXAMPLE_LED_MATRIX_V_RES * EXAMPLE_LED_MATRIX_H_RES / 2;
+    lv_color16_t *upper_half = (lv_color16_t *)color_map;
+    lv_color16_t *lower_half = (lv_color16_t *)color_map + EXAMPLE_LED_MATRIX_V_RES * EXAMPLE_LED_MATRIX_H_RES / 2;
+    int index = 0;
     for (int line = 0; line < EXAMPLE_LED_MATRIX_V_RES / 2; line++) {
         for (int col = 0; col < EXAMPLE_LED_MATRIX_H_RES - 1; col++) {
-            MERGE_TWO_LVGL_PIXELS(upper_half, lower_half);
-            upper_half++;
-            lower_half++;
+            merge_two_pixels(upper_half++, lower_half++, index++);
         }
-        MERGE_TWO_LVGL_PIXELS(upper_half, lower_half);
+        merge_two_pixels(upper_half++, lower_half++, index);
         // need special handling for the last pixel in each line
         // latch up at the end of each line
-        upper_half->full |= (1 << EXAMPLE_HUB75_LATCH_IDX);
-        upper_half++;
-        lower_half++;
+        s_frame_buffer[index++] |= (1 << EXAMPLE_HUB75_LATCH_IDX);
     }
-    memcpy(s_frame_buffer, color_map, sizeof(s_frame_buffer));
-    lv_disp_flush_ready(drv);
+    lv_display_flush_ready(display);
 }
 
 static IRAM_ATTR bool parlio_tx_line_done_cb(parlio_tx_unit_handle_t tx_unit, const parlio_tx_done_event_data_t *edata, void *user_ctx)
@@ -107,9 +103,6 @@ static IRAM_ATTR bool gptimer_alarm_cb_lvgl_tick(gptimer_handle_t timer, const g
 
 void app_main(void)
 {
-    static lv_disp_draw_buf_t disp_buf;
-    static lv_disp_drv_t disp_drv;
-
     ESP_LOGI(TAG, "Install fast GPIO bundle for line address control");
     dedic_gpio_bundle_config_t dedic_gpio_conf = {
         .flags.out_en = true,
@@ -144,7 +137,7 @@ void app_main(void)
         },
         .output_clk_freq_hz = EXAMPLE_LED_MATRIX_PIXEL_CLOCK_HZ,
         .trans_queue_depth = 32,
-        .max_transfer_size = EXAMPLE_LED_MATRIX_H_RES * sizeof(lv_color_t) * 2, // 2 lines as the maximum transfer size
+        .max_transfer_size = EXAMPLE_LED_MATRIX_H_RES * sizeof(uint8_t) * 2, // 2 lines as the maximum transfer size
         .sample_edge = PARLIO_SAMPLE_EDGE_POS,
     };
     ESP_ERROR_CHECK(parlio_new_tx_unit(&config, &tx_unit));
@@ -158,23 +151,21 @@ void app_main(void)
 
     ESP_LOGI(TAG, "Initialize LVGL library");
     lv_init();
+    lv_display_t *display = lv_display_create(EXAMPLE_LED_MATRIX_H_RES, EXAMPLE_LED_MATRIX_V_RES);
+
     // allocate two full-screen draw buffers
-    lv_color_t *buf1 = malloc(EXAMPLE_LED_MATRIX_H_RES * EXAMPLE_LED_MATRIX_V_RES * sizeof(lv_color_t));
+    size_t draw_buffer_sz = EXAMPLE_LED_MATRIX_H_RES * EXAMPLE_LED_MATRIX_V_RES * sizeof(lv_color16_t);
+    void *buf1 = heap_caps_calloc(1, draw_buffer_sz, MALLOC_CAP_INTERNAL);
     assert(buf1);
-    lv_color_t *buf2 = malloc(EXAMPLE_LED_MATRIX_H_RES * EXAMPLE_LED_MATRIX_V_RES * sizeof(lv_color_t));
+    void *buf2 = heap_caps_calloc(1, draw_buffer_sz, MALLOC_CAP_INTERNAL);
     assert(buf2);
+    // Use RGB565 because RGB332 is not supported in LVGL9.2
+    lv_display_set_color_format(display, LV_COLOR_FORMAT_RGB565);
     // initialize LVGL draw buffers
-    lv_disp_draw_buf_init(&disp_buf, buf1, buf2, EXAMPLE_LED_MATRIX_H_RES * EXAMPLE_LED_MATRIX_V_RES);
-
-    ESP_LOGI(TAG, "Register display driver to LVGL");
-    lv_disp_drv_init(&disp_drv);
-    disp_drv.hor_res = EXAMPLE_LED_MATRIX_H_RES;
-    disp_drv.ver_res = EXAMPLE_LED_MATRIX_V_RES;
-    disp_drv.flush_cb = example_lvgl_flush_cb;
-    disp_drv.draw_buf = &disp_buf;
-    disp_drv.user_data = NULL;
-    disp_drv.full_refresh = true; // the full_refresh mode can maintain the synchronization between two adjacent frame buffers
-    lv_disp_t *disp = lv_disp_drv_register(&disp_drv);
+    // Since the rgb matrix needs to be refreshed dynamically, use fullmode
+    lv_display_set_buffers(display, buf1, buf2, draw_buffer_sz, LV_DISPLAY_RENDER_MODE_FULL);
+    // set the callback which can copy the rendered image to an area of the display
+    lv_display_set_flush_cb(display, example_lvgl_flush_cb);
 
     ESP_LOGI(TAG, "Install LVGL tick timer");
     // increase the LVGL tick in the GPTimer alarm callback
@@ -198,7 +189,7 @@ void app_main(void)
     ESP_ERROR_CHECK(gptimer_enable(lvgl_tick_timer));
 
     ESP_LOGI(TAG, "Display LVGL UI");
-    example_lvgl_demo_ui(disp);
+    example_lvgl_demo_ui(display);
 
     ESP_ERROR_CHECK(gptimer_start(lvgl_tick_timer));
 
@@ -210,7 +201,7 @@ void app_main(void)
     while (1) {
         for (int i = 0; i < EXAMPLE_LED_MATRIX_V_RES / 2; i++) {
             ESP_ERROR_CHECK(parlio_tx_unit_transmit(tx_unit, payload + EXAMPLE_LED_MATRIX_H_RES * i,
-                                                    EXAMPLE_LED_MATRIX_H_RES * sizeof(lv_color_t) * 8, &transmit_config));
+                                                    EXAMPLE_LED_MATRIX_H_RES * sizeof(uint8_t) * 8, &transmit_config));
         }
         ESP_ERROR_CHECK(parlio_tx_unit_wait_all_done(tx_unit, -1));
         lv_timer_handler();
diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/pytest_simple_rgb_led_matrix.py b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/pytest_simple_rgb_led_matrix.py
index 940d78c6152..93765565788 100644
--- a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/pytest_simple_rgb_led_matrix.py
+++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/pytest_simple_rgb_led_matrix.py
@@ -1,6 +1,5 @@
-# SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
-
 import pytest
 from pytest_embedded import Dut
 
@@ -11,6 +10,5 @@ def test_simple_rgb_led_matrix_example(dut: Dut) -> None:
     dut.expect_exact('example: Install fast GPIO bundle for line address control')
     dut.expect_exact('example: Install parallel IO TX unit')
     dut.expect_exact('example: Initialize LVGL library')
-    dut.expect_exact('example: Register display driver to LVGL')
     dut.expect_exact('example: Install LVGL tick timer')
     dut.expect_exact('example: Display LVGL UI')
diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults
index 788db185787..3d0db7cbae6 100644
--- a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults
+++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults
@@ -2,5 +2,4 @@
 # Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
 #
 CONFIG_ESP_TASK_WDT_INIT=n
-CONFIG_LV_COLOR_DEPTH_8=y
 CONFIG_LV_THEME_DEFAULT_DARK=y
diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults.esp32c6 b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults.esp32c6
new file mode 100644
index 00000000000..645d154d34c
--- /dev/null
+++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults.esp32c6
@@ -0,0 +1,13 @@
+CONFIG_EXAMPLE_PIN_NUM_R1=7
+CONFIG_EXAMPLE_PIN_NUM_G1=4
+CONFIG_EXAMPLE_PIN_NUM_B1=1
+CONFIG_EXAMPLE_PIN_NUM_R2=6
+CONFIG_EXAMPLE_PIN_NUM_G2=3
+CONFIG_EXAMPLE_PIN_NUM_B2=0
+CONFIG_EXAMPLE_PIN_NUM_LATCH=5
+CONFIG_EXAMPLE_PIN_NUM_OE=2
+CONFIG_EXAMPLE_PIN_NUM_PCLK=10
+CONFIG_EXAMPLE_PIN_NUM_A=20
+CONFIG_EXAMPLE_PIN_NUM_B=21
+CONFIG_EXAMPLE_PIN_NUM_C=22
+CONFIG_EXAMPLE_PIN_NUM_D=23
diff --git a/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults.esp32h2 b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults.esp32h2
new file mode 100644
index 00000000000..6ae3d6cbfed
--- /dev/null
+++ b/examples/peripherals/parlio/parlio_tx/simple_rgb_led_matrix/sdkconfig.defaults.esp32h2
@@ -0,0 +1,13 @@
+CONFIG_EXAMPLE_PIN_NUM_R1=12
+CONFIG_EXAMPLE_PIN_NUM_G1=0
+CONFIG_EXAMPLE_PIN_NUM_B1=22
+CONFIG_EXAMPLE_PIN_NUM_R2=2
+CONFIG_EXAMPLE_PIN_NUM_G2=1
+CONFIG_EXAMPLE_PIN_NUM_B2=3
+CONFIG_EXAMPLE_PIN_NUM_LATCH=11
+CONFIG_EXAMPLE_PIN_NUM_OE=26
+CONFIG_EXAMPLE_PIN_NUM_PCLK=27
+CONFIG_EXAMPLE_PIN_NUM_A=8
+CONFIG_EXAMPLE_PIN_NUM_B=5
+CONFIG_EXAMPLE_PIN_NUM_C=9
+CONFIG_EXAMPLE_PIN_NUM_D=10
diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md
index 26ed2f38b78..4843828bc25 100644
--- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md
+++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 |
-| ----------------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
+| ----------------- | -------- | -------- | --------- | -------- | -------- |
 
 # HC-SR04 Example based on GPTimer Capture and ETM
 
diff --git a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py
index 0c668e45bb1..2756fe0fa29 100644
--- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py
+++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py
@@ -6,6 +6,7 @@
 
 @pytest.mark.esp32c5
 @pytest.mark.esp32c6
+@pytest.mark.esp32c61
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
 @pytest.mark.generic
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v3/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sens_basic/CMakeLists.txt
similarity index 100%
rename from examples/peripherals/touch_sensor/touch_sensor_v3/CMakeLists.txt
rename to examples/peripherals/touch_sensor/touch_sens_basic/CMakeLists.txt
diff --git a/examples/peripherals/touch_sensor/touch_sens_basic/README.md b/examples/peripherals/touch_sensor/touch_sens_basic/README.md
new file mode 100644
index 00000000000..c7381427a82
--- /dev/null
+++ b/examples/peripherals/touch_sensor/touch_sens_basic/README.md
@@ -0,0 +1,125 @@
+| Supported Targets | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- |
+
+# Capacity Touch Sensor Example (for hardware version 3)
+
+(See the README.md file in the upper level 'examples' directory for more information about examples.)
+
+This example is going to demonstrate how to register the touch channels and read the data.
+
+## How to Use Example
+
+### Hardware Required
+
+* A development board with any supported Espressif SOC chip (see `Supported Targets` table above)
+* A USB cable for power supply and programming
+* (Optional) Touch board with touch buttons on it.
+    - If you don't have a touch board, you can connect the touch pins with male jump wires and touch it directly for testing.
+
+### Configure the Project
+
+You can determine the touch channel number by ``EXAMPLE_TOUCH_CHANNEL_NUM`` in the example. And adjust the active threshold by ``s_thresh2bm_ratio``.
+
+### Build and Flash
+
+Build the project and flash it to the board, then run monitor tool to view serial output:
+
+```
+idf.py -p PORT build flash monitor
+```
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
+
+## Example Output
+
+You can see the following output in the monitor if the example runs successfully:
+
+```
+W (461) touch: [sample_cfg_id 0] clock precision loss, expect 4000000 hz, got 4006725 hz
+W (461) touch: [sample_cfg_id 1] clock precision loss, expect 8000000 hz, got 8013450 hz
+W (461) touch: [sample_cfg_id 2] clock precision loss, expect 16000000 hz, got 16026900 hz
+Initial benchmark and new threshold are:
+[CH 0] 0: 4114, 411      1: 2057, 205    2: 1028, 102
+[CH 1] 0: 4643, 464      1: 2322, 232    2: 1160, 116
+[CH 2] 0: 4848, 484      1: 2424, 242    2: 1211, 121
+[CH 3] 0: 4340, 434      1: 2170, 217    2: 1085, 108
+=================================
+benchmark [CH 0]: 4115 2056 1028
+chan_data [CH 0]: 4115 2056 1028
+
+benchmark [CH 1]: 4644 2322 1160
+chan_data [CH 1]: 4644 2322 1160
+
+benchmark [CH 2]: 4848 2423 1211
+chan_data [CH 2]: 4848 2423 1211
+
+benchmark [CH 3]: 4337 2168 1084
+chan_data [CH 3]: 4337 2168 1084
+
+=================================
+benchmark [CH 0]: 4109 2054 1027
+chan_data [CH 0]: 4109 2054 1027
+
+benchmark [CH 1]: 4638 2318 1158
+chan_data [CH 1]: 4638 2318 1158
+
+benchmark [CH 2]: 4843 2421 1210
+chan_data [CH 2]: 4845 2421 1210
+
+benchmark [CH 3]: 4334 2167 1084
+chan_data [CH 3]: 4334 2167 1083
+...
+```
+
+And if you touch and release a button, you will see the following output:
+
+```
+...
+I (1321) touch_callback: [CH 1] active
+=================================
+benchmark [CH 0]: 4111 2055 1027
+chan_data [CH 0]: 4111 2055 1027
+
+benchmark [CH 1]: 4676 2339 1168
+chan_data [CH 1]: 17701 8798 4399
+
+benchmark [CH 2]: 4870 2434 1217
+chan_data [CH 2]: 4867 2433 1217
+
+benchmark [CH 3]: 4333 2165 1082
+chan_data [CH 3]: 4333 2165 1082
+
+=================================
+benchmark [CH 0]: 4109 2053 1027
+chan_data [CH 0]: 4108 2053 1027
+
+benchmark [CH 1]: 4676 2339 1168
+chan_data [CH 1]: 11256 8817 4363
+
+benchmark [CH 2]: 4868 2434 1217
+chan_data [CH 2]: 4862 2429 1214
+
+benchmark [CH 3]: 4332 2165 1082
+chan_data [CH 3]: 4330 2164 1081
+
+I (1931) touch_callback: [CH 1] inactive
+=================================
+benchmark [CH 0]: 4106 2052 1026
+chan_data [CH 0]: 4106 2052 1026
+
+benchmark [CH 1]: 4649 2323 1161
+chan_data [CH 1]: 4650 2323 1161
+
+benchmark [CH 2]: 4847 2422 1211
+chan_data [CH 2]: 4846 2422 1211
+
+benchmark [CH 3]: 4329 2163 1082
+chan_data [CH 3]: 4329 2164 1082
+...
+```
+
+## Troubleshooting
+
+For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon.
diff --git a/examples/peripherals/touch_sensor/touch_sens_basic/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sens_basic/main/CMakeLists.txt
new file mode 100644
index 00000000000..b39f3c6de9c
--- /dev/null
+++ b/examples/peripherals/touch_sensor/touch_sens_basic/main/CMakeLists.txt
@@ -0,0 +1,3 @@
+idf_component_register(SRCS "touch_sens_basic_example_main.c"
+                    REQUIRES esp_driver_touch_sens
+                    INCLUDE_DIRS ".")
diff --git a/examples/peripherals/touch_sensor/touch_sens_basic/main/touch_sens_basic_example_main.c b/examples/peripherals/touch_sensor/touch_sens_basic/main/touch_sens_basic_example_main.c
new file mode 100644
index 00000000000..5973a1d1019
--- /dev/null
+++ b/examples/peripherals/touch_sensor/touch_sens_basic/main/touch_sens_basic_example_main.c
@@ -0,0 +1,153 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: CC0-1.0
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "driver/touch_sens.h"
+#include "esp_check.h"
+#include "touch_sens_example_config.h"
+
+static touch_sensor_handle_t  s_sens_handle = NULL;
+static touch_channel_handle_t s_chan_handle[EXAMPLE_TOUCH_CHANNEL_NUM] = {};
+// Active threshold to benchmark ratio. (i.e., touch will be activated when data >= benchmark * (1 + ratio))
+static float s_thresh2bm_ratio[EXAMPLE_TOUCH_CHANNEL_NUM] = {
+    [0 ... EXAMPLE_TOUCH_CHANNEL_NUM - 1] = 0.015f,  // 1.5%
+};
+// The touch channel IDs that used in this example
+static int s_channel_id[EXAMPLE_TOUCH_CHANNEL_NUM] = {
+    TOUCH_MIN_CHAN_ID,
+    TOUCH_MIN_CHAN_ID + 1,
+    TOUCH_MIN_CHAN_ID + 2,
+    TOUCH_MIN_CHAN_ID + 3,
+};
+
+bool example_touch_on_active_callback(touch_sensor_handle_t sens_handle, const touch_active_event_data_t *event, void *user_ctx)
+{
+    ESP_EARLY_LOGI("touch_callback", "[CH %d] active", (int)event->chan_id);
+    return false;
+}
+
+bool example_touch_on_inactive_callback(touch_sensor_handle_t sens_handle, const touch_inactive_event_data_t *event, void *user_ctx)
+{
+    ESP_EARLY_LOGI("touch_callback", "[CH %d] inactive", (int)event->chan_id);
+    return false;
+}
+
+static void example_touch_do_initial_scanning(void)
+{
+    /* Enable the touch sensor to do the initial scanning, so that to initialize the channel data */
+    ESP_ERROR_CHECK(touch_sensor_enable(s_sens_handle));
+
+    /* Scan the enabled touch channels for several times, to make sure the initial channel data is stable */
+    for (int i = 0; i < EXAMPLE_TOUCH_CHAN_INIT_SCAN_TIMES; i++) {
+        ESP_ERROR_CHECK(touch_sensor_trigger_oneshot_scanning(s_sens_handle, 2000));
+    }
+
+    /* Disable the touch channel to rollback the state */
+    ESP_ERROR_CHECK(touch_sensor_disable(s_sens_handle));
+
+    /* (Optional) Read the initial channel benchmark and reconfig the channel active threshold accordingly */
+    printf("Initial benchmark and new threshold are:\n");
+    for (int i = 0; i < EXAMPLE_TOUCH_CHANNEL_NUM; i++) {
+        /* Read the initial benchmark of the touch channel */
+        uint32_t benchmark[EXAMPLE_TOUCH_SAMPLE_CFG_NUM] = {};
+        ESP_ERROR_CHECK(touch_channel_read_data(s_chan_handle[i], TOUCH_CHAN_DATA_TYPE_BENCHMARK, benchmark));
+        /* Calculate the proper active thresholds regarding the initial benchmark */
+        printf("[CH %d]", i);
+        touch_channel_config_t chan_cfg = EXAMPLE_TOUCH_CHAN_CFG_DEFAULT();
+        for (int j = 0; j < EXAMPLE_TOUCH_SAMPLE_CFG_NUM; j++) {
+            chan_cfg.active_thresh[j] = (uint32_t)(benchmark[j] * s_thresh2bm_ratio[i]);
+            printf(" %d: %"PRIu32", %"PRIu32"\t", j, benchmark[j], chan_cfg.active_thresh[j]);
+        }
+        printf("\n");
+        /* Update the channel configuration */
+        ESP_ERROR_CHECK(touch_sensor_reconfig_channel(s_chan_handle[i], &chan_cfg));
+    }
+}
+
+void app_main(void)
+{
+    /* Use the default sample configurations */
+    touch_sensor_sample_config_t sample_cfg[EXAMPLE_TOUCH_SAMPLE_CFG_NUM] = EXAMPLE_TOUCH_SAMPLE_CFG_DEFAULT();
+    /* Allocate new touch controller handle */
+    touch_sensor_config_t sens_cfg = TOUCH_SENSOR_DEFAULT_BASIC_CONFIG(EXAMPLE_TOUCH_SAMPLE_CFG_NUM, sample_cfg);
+    ESP_ERROR_CHECK(touch_sensor_new_controller(&sens_cfg, &s_sens_handle));
+
+    /* Configure the touch sensor filter */
+    touch_sensor_filter_config_t filter_cfg = TOUCH_SENSOR_DEFAULT_FILTER_CONFIG();
+    ESP_ERROR_CHECK(touch_sensor_config_filter(s_sens_handle, &filter_cfg));
+
+    /** Following is about setting the touch channel active threshold of each sample configuration.
+     *
+     *  @How to Determine:
+     *  As the actual threshold is affected by various factors in real application,
+     *  we need to run the touch app first to get the `benchmark` and the `smooth_data` that being touched.
+     *
+     *  @Formula:
+     *  threshold = benchmark * coeff, (coeff for example, 0.1%~20%)
+     *  Please adjust the coeff to guarantee the threshold < smooth_data - benchmark
+     *
+     *  @Typical Practice:
+     *  Normally, we can't determine a fixed threshold at the beginning,
+     *  but we can give them estimated values first and update them after an initial scanning (like this example),
+     *  Step1: set an estimated value for each sample configuration first. (i.e., here)
+     *  Step2: then reconfig the threshold after the initial scanning.(see `example_touch_do_initial_scanning`)
+     *  Step3: adjust the `s_thresh2bm_ratio` to a proper value to trigger the active callback
+     */
+    touch_channel_config_t chan_cfg = EXAMPLE_TOUCH_CHAN_CFG_DEFAULT();
+    /* Allocate new touch channel on the touch controller */
+    for (int i = 0; i < EXAMPLE_TOUCH_CHANNEL_NUM; i++) {
+        ESP_ERROR_CHECK(touch_sensor_new_channel(s_sens_handle, s_channel_id[i], &chan_cfg, &s_chan_handle[i]));
+    }
+
+    /* Do the initial scanning to initialize the touch channel data
+     * Without this step, the channel data in the first read will be invalid
+     */
+    example_touch_do_initial_scanning();
+
+    /* Register the touch sensor callbacks, here only take `active` and `deactivate` event for example */
+    touch_event_callbacks_t callbacks = {
+        .on_active = example_touch_on_active_callback,
+        .on_inactive = example_touch_on_inactive_callback,
+        .on_measure_done = NULL,
+        .on_scan_done = NULL,
+        .on_timeout = NULL,
+        .on_proximity_meas_done = NULL,
+    };
+    ESP_ERROR_CHECK(touch_sensor_register_callbacks(s_sens_handle, &callbacks, NULL));
+
+    /* Enable the touch sensor */
+    ESP_ERROR_CHECK(touch_sensor_enable(s_sens_handle));
+
+    /* Start continuous scanning, you can also trigger oneshot scanning manually */
+    ESP_ERROR_CHECK(touch_sensor_start_continuous_scanning(s_sens_handle));
+
+    uint32_t benchmark[EXAMPLE_TOUCH_SAMPLE_CFG_NUM] = {};
+    uint32_t chan_data[EXAMPLE_TOUCH_SAMPLE_CFG_NUM] = {};
+    while (1) {
+        printf("=================================\n");
+        for (int i = 0; i < EXAMPLE_TOUCH_CHANNEL_NUM; i++) {
+            /* Read and print the benchmark of each sample configuration */
+            ESP_ERROR_CHECK(touch_channel_read_data(s_chan_handle[i], TOUCH_CHAN_DATA_TYPE_BENCHMARK, benchmark));
+            printf("benchmark [CH %d]:", s_channel_id[i]);
+            for (int j = 0; j < EXAMPLE_TOUCH_SAMPLE_CFG_NUM; j++) {
+                printf(" %"PRIu32, benchmark[j]);
+            }
+            printf("\n");
+            /* Read and print the channel data of each sample configuration */
+            ESP_ERROR_CHECK(touch_channel_read_data(s_chan_handle[i], TOUCH_CHAN_DATA_TYPE_SMOOTH, chan_data));
+            printf("chan_data [CH %d]:", s_channel_id[i]);
+            for (int j = 0; j < EXAMPLE_TOUCH_SAMPLE_CFG_NUM; j++) {
+                printf(" %"PRIu32, chan_data[j]);
+            }
+            printf("\n\n");
+        }
+        /* Read and display the data every 300 ms */
+        vTaskDelay(pdMS_TO_TICKS(300));
+    }
+}
diff --git a/examples/peripherals/touch_sensor/touch_sens_basic/main/touch_sens_example_config.h b/examples/peripherals/touch_sensor/touch_sens_basic/main/touch_sens_example_config.h
new file mode 100644
index 00000000000..856922df767
--- /dev/null
+++ b/examples/peripherals/touch_sensor/touch_sens_basic/main/touch_sens_example_config.h
@@ -0,0 +1,54 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: CC0-1.0
+ */
+
+#pragma once
+
+#include "driver/touch_sens.h"
+#include "esp_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Touch version 3 supports multiple sample configurations
+#define EXAMPLE_TOUCH_SAMPLE_CFG_NUM        TOUCH_SAMPLE_CFG_NUM  // Up to 'TOUCH_SAMPLE_CFG_NUM'
+#define EXAMPLE_TOUCH_CHANNEL_NUM           4
+#define EXAMPLE_TOUCH_CHAN_INIT_SCAN_TIMES  3
+
+ESP_STATIC_ASSERT(EXAMPLE_TOUCH_SAMPLE_CFG_NUM <= TOUCH_SAMPLE_CFG_NUM, "sample configuration number exceed the supported number");
+ESP_STATIC_ASSERT(EXAMPLE_TOUCH_CHANNEL_NUM <= (TOUCH_MAX_CHAN_ID - TOUCH_MIN_CHAN_ID + 1), "touch channel number exceed the max supported number ");
+
+#if SOC_TOUCH_SENSOR_VERSION == 2
+#define EXAMPLE_TOUCH_SAMPLE_CFG_DEFAULT()      {TOUCH_SENSOR_V2_DEFAULT_SAMPLE_CONFIG(500, TOUCH_VOLT_LIM_L_0V5, TOUCH_VOLT_LIM_H_2V2)}
+#define EXAMPLE_TOUCH_CHAN_CFG_DEFAULT()        {  \
+    .active_thresh = {2000},  \
+    .charge_speed = TOUCH_CHARGE_SPEED_7,  \
+    .init_charge_volt = TOUCH_INIT_CHARGE_VOLT_LOW,  \
+}
+#elif SOC_TOUCH_SENSOR_VERSION == 3
+#define EXAMPLE_TOUCH_SAMPLE_CFG(res, cap, coarse_freq_tune, fine_freq_tune) { \
+    .div_num = 8, \
+    .charge_times = 500, \
+    .rc_filter_res = res, \
+    .rc_filter_cap = cap, \
+    .low_drv = fine_freq_tune, \
+    .high_drv = coarse_freq_tune, \
+    .bias_volt = 5, \
+    .bypass_shield_output = false, \
+}
+#define EXAMPLE_TOUCH_SAMPLE_CFG_DEFAULT()      {EXAMPLE_TOUCH_SAMPLE_CFG(3, 29, 8, 3),\
+                                                 EXAMPLE_TOUCH_SAMPLE_CFG(2, 88, 31, 7), \
+                                                 EXAMPLE_TOUCH_SAMPLE_CFG(3, 10, 31, 7)}
+#define EXAMPLE_TOUCH_CHAN_CFG_DEFAULT()        {  \
+    .active_thresh = {1000, 2500, 5000},  \
+}
+#else
+#error "Target not supported"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/examples/peripherals/touch_sensor/touch_sens_basic/pytest_touch_sens_basic.py b/examples/peripherals/touch_sensor/touch_sens_basic/pytest_touch_sens_basic.py
new file mode 100644
index 00000000000..2dbede48e3d
--- /dev/null
+++ b/examples/peripherals/touch_sensor/touch_sens_basic/pytest_touch_sens_basic.py
@@ -0,0 +1,15 @@
+# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32s2
+@pytest.mark.esp32s3
+@pytest.mark.esp32p4
+@pytest.mark.generic
+def test_touch_sens_v3(dut: Dut) -> None:
+    dut.expect_exact('Initial benchmark and new threshold are:')
+    dut.expect(r'\[CH [0-9]+\] 0: [0-9]+, [0-9]+')
+    dut.expect(r'benchmark \[CH [0-9]+\]: [0-9]+')
+    dut.expect(r'chan_data \[CH [0-9]+\]: [0-9]+')
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/CMakeLists.txt
deleted file mode 100644
index c7504c7d03f..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/CMakeLists.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# The following lines of boilerplate have to be in your project's CMakeLists
-# in this exact order for cmake to work correctly
-cmake_minimum_required(VERSION 3.16)
-
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-project(touch_pad_interrupt)
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/README.md b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/README.md
deleted file mode 100644
index d871b21849c..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/README.md
+++ /dev/null
@@ -1,60 +0,0 @@
-| Supported Targets | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- |
-
-# Touch Pad Interrupt Example
-
-(See the README.md file in the upper level 'examples' directory for more information about examples.)
-
-This example demonstrates how to set up ESP32-S2/S3's capacitive touch pad peripheral to trigger interrupt when a pad is touched. It also shows how to detect the touch event by the software for sensor designs when greater touch detection sensitivity is required.
-
-- The hardware interrupt mode occupies less CPU resources, but we can only apply fixed threshold and software algorithms are also impossibile.
-- The polling mode is flexible and supports various software algorithms. However, it comsumes more CPU.
-
-ESP32-S2/S3 supports touch detection by configuring hardware registers. The hardware periodically detects the pulse counts. If the number of pulse counts exceeds the set threshold, a hardware interrupt will be generated to notify the application layer that a certain touch sensor channel may be triggered.
-
-For a simpler example how to configure and read capacitive touch pads, please refer to [touch_pad_read](../touch_pad_read).
-
-## How to use example
-
-### Hardware Required
-
-* A development board with ESP32-S2 or ESP32-S3 chip
-* A touch extension board like [esp32-s2-touch-devkit-1](https://docs.espressif.com/projects/espressif-esp-dev-kits/en/latest/esp32s2/esp32-s2-touch-devkit-1/user_guide.html)
-
-### Build and Flash
-
-Build the project and flash it to the board, then run monitor tool to view serial output:
-
-```
-idf.py -p PORT flash monitor
-```
-
-(Replace PORT with the name of the serial port to use.)
-
-(To exit the serial monitor, type ``Ctrl-]``.)
-
-See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
-
-## Example Output
-
-The application cycles between the interrupt mode and the pooling mode with a filter, to compare performance of the touch sensor system between both scenarios:
-
-```
-I (304) Touch pad: Initializing touch pad
-I (304) Touch pad: Denoise function init
-I (304) Touch pad: touch pad waterproof init
-I (304) Touch pad: touch pad filter init 2
-I (414) Touch pad: test init: touch pad [7] base 7382, thresh 1476
-I (414) Touch pad: test init: touch pad [9] base 7349, thresh 1469
-I (414) Touch pad: test init: touch pad [11] base 8047, thresh 1609
-I (414) Touch pad: test init: touch pad [13] base 8104, thresh 810
-I (5954) Touch pad: TouchSensor [9] be actived, status mask 0x200
-W (6034) Touch pad: TouchSensor [13] be actived, enter guard mode
-W (6034) Touch pad: In guard mode. No response
-W (6174) Touch pad: TouchSensor [13] be actived, exit guard mode
-I (6194) Touch pad: TouchSensor [9] be inactived, status mask 0x0
-```
-
-## Troubleshooting
-
-For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon.
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/CMakeLists.txt
deleted file mode 100644
index 94fac9872e9..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/CMakeLists.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-idf_component_register(SRCS "tp_interrupt_main.c"
-                    INCLUDE_DIRS ".")
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c
deleted file mode 100644
index e8a671ecfcb..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/main/tp_interrupt_main.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: CC0-1.0
- */
-
-#include <stdio.h>
-#include <inttypes.h>
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "freertos/queue.h"
-#include "esp_log.h"
-#include "driver/touch_pad.h"
-
-static const char *TAG = "Touch pad";
-
-static QueueHandle_t que_touch = NULL;
-typedef struct touch_msg {
-    touch_pad_intr_mask_t intr_mask;
-    uint32_t pad_num;
-    uint32_t pad_status;
-    uint32_t pad_val;
-} touch_event_t;
-
-#define TOUCH_BUTTON_NUM    4
-#define TOUCH_BUTTON_WATERPROOF_ENABLE 1
-#define TOUCH_BUTTON_DENOISE_ENABLE    1
-#define TOUCH_CHANGE_CONFIG            0
-
-static const touch_pad_t button[TOUCH_BUTTON_NUM] = {
-    TOUCH_PAD_NUM7,     // 'SELECT' button.
-    TOUCH_PAD_NUM9,     // 'MENU' button.
-    TOUCH_PAD_NUM11,    // 'BACK' button.
-    TOUCH_PAD_NUM13,    // Guard ring for waterproof design.
-    // If this pad be touched, other pads no response.
-};
-
-/*
- * Touch threshold. The threshold determines the sensitivity of the touch.
- * This threshold is derived by testing changes in readings from different touch channels.
- * If (raw_data - benchmark) > benchmark * threshold, the pad be activated.
- * If (raw_data - benchmark) < benchmark * threshold, the pad be inactivated.
- */
-static const float button_threshold[TOUCH_BUTTON_NUM] = {
-    0.2, // 20%.
-    0.2, // 20%.
-    0.2, // 20%.
-    0.1, // 10%.
-};
-
-/*
-  Handle an interrupt triggered when a pad is touched.
-  Recognize what pad has been touched and save it in a table.
- */
-static void touchsensor_interrupt_cb(void *arg)
-{
-    int task_awoken = pdFALSE;
-    touch_event_t evt;
-
-    evt.intr_mask = touch_pad_read_intr_status_mask();
-    evt.pad_status = touch_pad_get_status();
-    evt.pad_num = touch_pad_get_current_meas_channel();
-
-    xQueueSendFromISR(que_touch, &evt, &task_awoken);
-    if (task_awoken == pdTRUE) {
-        portYIELD_FROM_ISR();
-    }
-}
-
-static void tp_example_set_thresholds(void)
-{
-    uint32_t touch_value;
-    for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
-        //read benchmark value
-        touch_pad_read_benchmark(button[i], &touch_value);
-        //set interrupt threshold.
-        touch_pad_set_thresh(button[i], touch_value * button_threshold[i]);
-        ESP_LOGI(TAG, "touch pad [%d] base %"PRIu32", thresh %"PRIu32, \
-                 button[i], touch_value, (uint32_t)(touch_value * button_threshold[i]));
-    }
-}
-
-static void touchsensor_filter_set(touch_filter_mode_t mode)
-{
-    /* Filter function */
-    touch_filter_config_t filter_info = {
-        .mode = mode,           // Test jitter and filter 1/4.
-        .debounce_cnt = 1,      // 1 time count.
-        .noise_thr = 0,         // 50%
-        .jitter_step = 4,       // use for jitter mode.
-        .smh_lvl = TOUCH_PAD_SMOOTH_IIR_2,
-    };
-    touch_pad_filter_set_config(&filter_info);
-    touch_pad_filter_enable();
-    ESP_LOGI(TAG, "touch pad filter init");
-}
-
-static void tp_example_read_task(void *pvParameter)
-{
-    touch_event_t evt = {0};
-    static uint8_t guard_mode_flag = 0;
-    /* Wait touch sensor init done */
-    vTaskDelay(50 / portTICK_PERIOD_MS);
-    tp_example_set_thresholds();
-
-    while (1) {
-        int ret = xQueueReceive(que_touch, &evt, (TickType_t)portMAX_DELAY);
-        if (ret != pdTRUE) {
-            continue;
-        }
-        if (evt.intr_mask & TOUCH_PAD_INTR_MASK_ACTIVE) {
-            /* if guard pad be touched, other pads no response. */
-            if (evt.pad_num == button[3]) {
-                guard_mode_flag = 1;
-                ESP_LOGW(TAG, "TouchSensor [%"PRIu32"] be activated, enter guard mode", evt.pad_num);
-            } else {
-                if (guard_mode_flag == 0) {
-                    ESP_LOGI(TAG, "TouchSensor [%"PRIu32"] be activated, status mask 0x%"PRIu32"", evt.pad_num, evt.pad_status);
-                } else {
-                    ESP_LOGW(TAG, "In guard mode. No response");
-                }
-            }
-        }
-        if (evt.intr_mask & TOUCH_PAD_INTR_MASK_INACTIVE) {
-            /* if guard pad be touched, other pads no response. */
-            if (evt.pad_num == button[3]) {
-                guard_mode_flag = 0;
-                ESP_LOGW(TAG, "TouchSensor [%"PRIu32"] be inactivated, exit guard mode", evt.pad_num);
-            } else {
-                if (guard_mode_flag == 0) {
-                    ESP_LOGI(TAG, "TouchSensor [%"PRIu32"] be inactivated, status mask 0x%"PRIu32, evt.pad_num, evt.pad_status);
-                }
-            }
-        }
-        if (evt.intr_mask & TOUCH_PAD_INTR_MASK_SCAN_DONE) {
-            ESP_LOGI(TAG, "The touch sensor group measurement is done [%"PRIu32"].", evt.pad_num);
-        }
-        if (evt.intr_mask & TOUCH_PAD_INTR_MASK_TIMEOUT) {
-            /* Add your exception handling in here. */
-            ESP_LOGI(TAG, "Touch sensor channel %"PRIu32" measure timeout. Skip this exception channel!!", evt.pad_num);
-            touch_pad_timeout_resume(); // Point on the next channel to measure.
-        }
-    }
-}
-
-void app_main(void)
-{
-    if (que_touch == NULL) {
-        que_touch = xQueueCreate(TOUCH_BUTTON_NUM, sizeof(touch_event_t));
-    }
-    // Initialize touch pad peripheral, it will start a timer to run a filter
-    ESP_LOGI(TAG, "Initializing touch pad");
-    /* Initialize touch pad peripheral. */
-    touch_pad_init();
-    for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
-        touch_pad_config(button[i]);
-    }
-
-#if TOUCH_CHANGE_CONFIG
-    /* If you want change the touch sensor default setting, please write here(after initialize). There are examples: */
-    touch_pad_set_measurement_interval(TOUCH_PAD_SLEEP_CYCLE_DEFAULT);
-    touch_pad_set_charge_discharge_times(TOUCH_PAD_MEASURE_CYCLE_DEFAULT);
-    touch_pad_set_voltage(TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD, TOUCH_PAD_LOW_VOLTAGE_THRESHOLD, TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD);
-    touch_pad_set_idle_channel_connect(TOUCH_PAD_IDLE_CH_CONNECT_DEFAULT);
-    for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
-        touch_pad_set_cnt_mode(button[i], TOUCH_PAD_SLOPE_DEFAULT, TOUCH_PAD_TIE_OPT_DEFAULT);
-    }
-#endif
-
-#if TOUCH_BUTTON_DENOISE_ENABLE
-    /* Denoise setting at TouchSensor 0. */
-    touch_pad_denoise_t denoise = {
-        /* The bits to be cancelled are determined according to the noise level. */
-        .grade = TOUCH_PAD_DENOISE_BIT4,
-        /* By adjusting the parameters, the reading of T0 should be approximated to the reading of the measured channel. */
-        .cap_level = TOUCH_PAD_DENOISE_CAP_L4,
-    };
-    touch_pad_denoise_set_config(&denoise);
-    touch_pad_denoise_enable();
-    ESP_LOGI(TAG, "Denoise function init");
-#endif
-
-#if TOUCH_BUTTON_WATERPROOF_ENABLE
-    /* Waterproof function */
-    touch_pad_waterproof_t waterproof = {
-        .guard_ring_pad = button[3],   // If no ring pad, set 0;
-        /* It depends on the number of the parasitic capacitance of the shield pad.
-           Based on the touch readings of T14 and T0, estimate the size of the parasitic capacitance on T14
-           and set the parameters of the appropriate hardware. */
-        .shield_driver = TOUCH_PAD_SHIELD_DRV_L2,
-    };
-    touch_pad_waterproof_set_config(&waterproof);
-    touch_pad_waterproof_enable();
-    ESP_LOGI(TAG, "touch pad waterproof init");
-#endif
-
-    /* Filter setting */
-    touchsensor_filter_set(TOUCH_PAD_FILTER_IIR_16);
-    touch_pad_timeout_set(true, TOUCH_PAD_THRESHOLD_MAX);
-    /* Register touch interrupt ISR, enable intr type. */
-    touch_pad_isr_register(touchsensor_interrupt_cb, NULL, TOUCH_PAD_INTR_MASK_ALL);
-    /* If you have other touch algorithm, you can get the measured value after the `TOUCH_PAD_INTR_MASK_SCAN_DONE` interrupt is generated. */
-    touch_pad_intr_enable(TOUCH_PAD_INTR_MASK_ACTIVE | TOUCH_PAD_INTR_MASK_INACTIVE | TOUCH_PAD_INTR_MASK_TIMEOUT);
-
-    /* Enable touch sensor clock. Work mode is "timer trigger". */
-    touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER);
-    touch_pad_fsm_start();
-
-    // Start a task to show what pads have been touched
-    xTaskCreate(&tp_example_read_task, "touch_pad_read_task", 4096, NULL, 5, NULL);
-}
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/pytest_touch_pad_interrupt_v2.py b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/pytest_touch_pad_interrupt_v2.py
deleted file mode 100644
index 890b110e91a..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_interrupt/pytest_touch_pad_interrupt_v2.py
+++ /dev/null
@@ -1,15 +0,0 @@
-# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
-# SPDX-License-Identifier: Unlicense OR CC0-1.0
-import pytest
-from pytest_embedded import Dut
-
-
-@pytest.mark.esp32s2
-@pytest.mark.esp32s3
-@pytest.mark.generic
-def test_touch_pad_interrupt_v2(dut: Dut) -> None:
-    dut.expect_exact('Touch pad: Initializing touch pad')
-    dut.expect_exact('Touch pad: Denoise function init')
-    dut.expect_exact('Touch pad: touch pad waterproof init')
-    dut.expect_exact('Touch pad: touch pad filter init')
-    dut.expect(r'touch pad \[\d+\] base \d+, thresh \d+')
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/CMakeLists.txt
deleted file mode 100644
index 9baf66a8bb1..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/CMakeLists.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# The following lines of boilerplate have to be in your project's CMakeLists
-# in this exact order for cmake to work correctly
-cmake_minimum_required(VERSION 3.16)
-
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-project(touch_pad_read)
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/README.md b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/README.md
deleted file mode 100644
index 459e6e6e947..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/README.md
+++ /dev/null
@@ -1,50 +0,0 @@
-| Supported Targets | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- |
-
-# Touch Pad Read Example
-
-(See the README.md file in the upper level 'examples' directory for more information about examples.)
-
-Read and display raw values from capacitive touch pad sensors.
-
-Once configured, ESP32S2/S3 will continuously measure capacitance of touch pad sensors. Measurement is reflected as numeric value inversely related to sensor's capacitance. With a finger touched on a pad, its capacitance will get larger meanwhile the measured value gets smaller, and vice versa.
-
-To detect if a sensor is touched or not, each particular design should be calibrated by obtaining both measurements for each individual sensor. Then a threshold between both values can be established. With specific threshold, API is then able to distinguish whether specific sensor is touched or released. For ESP32-S2/S3, the hardware integrates the edge detection algorithm, which can achieve the purpose of detecting touch actions by configuring appropriate parameters. There is another similar example that demonstrates how to perform simple calibration and trigger an interrupt when a pad is touched - see [touch_pad_interrupt](../touch_pad_interrupt).
-
-## How to use example
-
-### Hardware Required
-
-* A development board with ESP32-S2 or ESP32-S3 chip
-* A touch extension board like [esp32-s2-touch-devkit-1](https://docs.espressif.com/projects/espressif-esp-dev-kits/en/latest/esp32s2/esp32-s2-touch-devkit-1/user_guide.html)
-
-### Build and Flash
-
-Build the project and flash it to the board, then run monitor tool to view serial output:
-
-```
-idf.py -p PORT flash monitor
-```
-
-(Replace PORT with the name of the serial port to use.)
-
-(To exit the serial monitor, type ``Ctrl-]``.)
-
-See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
-
-## Example Output
-
-ESP32-S2/S3 supports up to 14 capacitive touch pads, T1 - T14, which are connected to the specific GPIO pins. For the information of available pins please refer to ESP32-S2/S3 Technical Reference Manual. Note that T0 is an internal channel with no corresponding GPIO, it is mainly used for de-noise. This example will initialize all the 14 touch pads. The raw values of each pad can be monitored in the terminal:
-
-```
-Touch Sensor read, the output format is:
-Touchpad num:[raw data]
-
-T1: [6473] T2: [6507] T3: [6638] T4: [8917] T5: [9053] T6: [7190] T7: [7176] T8: [7416] T9: [7145] T10: [7387] T11: [7973] T12: [7776] T13: [8151] T14: [8190]
-T1: [6463] T2: [6512] T3: [6643] T4: [8920] T5: [9050] T6: [7191] T7: [7176] T8: [7416] T9: [7143] T10: [7387] T11: [7974] T12: [7778] T13: [8152] T14: [8192]
-T1: [6476] T2: [6508] T3: [6641] T4: [8919] T5: [9053] T6: [7190] T7: [7177] T8: [7416] T9: [7143] T10: [7386] T11: [7974] T12: [7776] T13: [8153] T14: [8193]
-```
-
-## Troubleshooting
-
-For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon.
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/CMakeLists.txt
deleted file mode 100644
index 2b9a209ec42..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/CMakeLists.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-idf_component_register(SRCS "tp_read_main.c"
-                    INCLUDE_DIRS ".")
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/tp_read_main.c b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/tp_read_main.c
deleted file mode 100644
index c082d9e6b3d..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/main/tp_read_main.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: CC0-1.0
- */
-
-#include <stdio.h>
-#include <inttypes.h>
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "driver/touch_pad.h"
-#include "esp_log.h"
-
-#define TOUCH_BUTTON_NUM    14
-#define TOUCH_CHANGE_CONFIG 0
-
-static const char *TAG = "touch read";
-static const touch_pad_t button[TOUCH_BUTTON_NUM] = {
-    TOUCH_PAD_NUM1,
-    TOUCH_PAD_NUM2,
-    TOUCH_PAD_NUM3,
-    TOUCH_PAD_NUM4,
-    TOUCH_PAD_NUM5,
-    TOUCH_PAD_NUM6,
-    TOUCH_PAD_NUM7,
-    TOUCH_PAD_NUM8,
-    TOUCH_PAD_NUM9,
-    TOUCH_PAD_NUM10,
-    TOUCH_PAD_NUM11,
-    TOUCH_PAD_NUM12,
-    TOUCH_PAD_NUM13,
-    TOUCH_PAD_NUM14
-};
-
-/*
-  Read values sensed at all available touch pads.
- Print out values in a loop on a serial monitor.
- */
-static void tp_example_read_task(void *pvParameter)
-{
-    uint32_t touch_value;
-
-    /* Wait touch sensor init done */
-    vTaskDelay(100 / portTICK_PERIOD_MS);
-    printf("Touch Sensor read, the output format is: \nTouchpad num:[raw data]\n\n");
-
-    while (1) {
-        for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
-            touch_pad_read_raw_data(button[i], &touch_value);    // read raw data.
-            printf("T%d: [%4"PRIu32"] ", button[i], touch_value);
-        }
-        printf("\n");
-        vTaskDelay(200 / portTICK_PERIOD_MS);
-    }
-}
-
-void app_main(void)
-{
-    /* Initialize touch pad peripheral. */
-    touch_pad_init();
-    for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
-        touch_pad_config(button[i]);
-    }
-#if TOUCH_CHANGE_CONFIG
-    /* If you want change the touch sensor default setting, please write here(after initialize). There are examples: */
-    touch_pad_set_measurement_interval(TOUCH_PAD_SLEEP_CYCLE_DEFAULT);
-    touch_pad_set_charge_discharge_times(TOUCH_PAD_MEASURE_CYCLE_DEFAULT);
-    touch_pad_set_voltage(TOUCH_PAD_HIGH_VOLTAGE_THRESHOLD, TOUCH_PAD_LOW_VOLTAGE_THRESHOLD, TOUCH_PAD_ATTEN_VOLTAGE_THRESHOLD);
-    touch_pad_set_idle_channel_connect(TOUCH_PAD_IDLE_CH_CONNECT_DEFAULT);
-    for (int i = 0; i < TOUCH_BUTTON_NUM; i++) {
-        touch_pad_set_cnt_mode(button[i], TOUCH_PAD_SLOPE_DEFAULT, TOUCH_PAD_TIE_OPT_DEFAULT);
-    }
-#endif
-    /* Denoise setting at TouchSensor 0. */
-    touch_pad_denoise_t denoise = {
-        /* The bits to be cancelled are determined according to the noise level. */
-        .grade = TOUCH_PAD_DENOISE_BIT4,
-        .cap_level = TOUCH_PAD_DENOISE_CAP_L4,
-    };
-    touch_pad_denoise_set_config(&denoise);
-    touch_pad_denoise_enable();
-    ESP_LOGI(TAG, "Denoise function init");
-
-    /* Enable touch sensor clock. Work mode is "timer trigger". */
-    touch_pad_set_fsm_mode(TOUCH_FSM_MODE_TIMER);
-    touch_pad_fsm_start();
-
-    /* Start task to read values by pads. */
-    xTaskCreate(&tp_example_read_task, "touch_pad_read_task", 4096, NULL, 5, NULL);
-}
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/pytest_touch_pad_read_v2.py b/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/pytest_touch_pad_read_v2.py
deleted file mode 100644
index 4c58c674927..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v2/touch_pad_read/pytest_touch_pad_read_v2.py
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
-# SPDX-License-Identifier: Unlicense OR CC0-1.0
-import pytest
-from pytest_embedded import Dut
-
-
-@pytest.mark.esp32s2
-@pytest.mark.esp32s3
-@pytest.mark.generic
-def test_touch_pad_read_v2(dut: Dut) -> None:
-    dut.expect_exact('touch read: Denoise function init')
-    dut.expect(r'T1: \[\d+\] T2: \[\d+\] T3: \[\d+\] T4: \[\d+\] T5: \[\d+\] T6: \[\d+\] T7: \[\d+\] T8: \[\d+\] T9: \[\d+\]'
-               r' T10: \[\d+\] T11: \[\d+\] T12: \[\d+\] T13: \[\d+\] T14: \[\d+\]')
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v3/README.md b/examples/peripherals/touch_sensor/touch_sensor_v3/README.md
deleted file mode 100644
index 650d3a24a66..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v3/README.md
+++ /dev/null
@@ -1,125 +0,0 @@
-| Supported Targets | ESP32-P4 |
-| ----------------- | -------- |
-
-# Capacity Touch Sensor Example (for hardware version 3)
-
-(See the README.md file in the upper level 'examples' directory for more information about examples.)
-
-This example is going to demonstrate how to register the touch channels and read the data.
-
-## How to Use Example
-
-### Hardware Required
-
-* A development board with any supported Espressif SOC chip (see `Supported Targets` table above)
-* A USB cable for power supply and programming
-* (Optional) Touch board with touch buttons on it.
-    - If you don't have a touch board, you can connect the touch pins with male jump wires and touch it directly for testing.
-
-### Configure the Project
-
-You can determine the touch channel number by ``EXAMPLE_TOUCH_CHANNEL_NUM`` in the example. And adjust the active threshold by ``s_thresh2bm_ratio``.
-
-### Build and Flash
-
-Build the project and flash it to the board, then run monitor tool to view serial output:
-
-```
-idf.py -p PORT build flash monitor
-```
-
-(To exit the serial monitor, type ``Ctrl-]``.)
-
-See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
-
-## Example Output
-
-You can see the following output in the monitor if the example runs successfully:
-
-```
-W (461) touch: [sample_cfg_id 0] clock precision loss, expect 4000000 hz, got 4006725 hz
-W (461) touch: [sample_cfg_id 1] clock precision loss, expect 8000000 hz, got 8013450 hz
-W (461) touch: [sample_cfg_id 2] clock precision loss, expect 16000000 hz, got 16026900 hz
-Initial benchmark and new threshold are:
-[CH 0] 0: 4114, 411      1: 2057, 205    2: 1028, 102
-[CH 1] 0: 4643, 464      1: 2322, 232    2: 1160, 116
-[CH 2] 0: 4848, 484      1: 2424, 242    2: 1211, 121
-[CH 3] 0: 4340, 434      1: 2170, 217    2: 1085, 108
-=================================
-benchmark [CH 0]: 4115 2056 1028
-chan_data [CH 0]: 4115 2056 1028
-
-benchmark [CH 1]: 4644 2322 1160
-chan_data [CH 1]: 4644 2322 1160
-
-benchmark [CH 2]: 4848 2423 1211
-chan_data [CH 2]: 4848 2423 1211
-
-benchmark [CH 3]: 4337 2168 1084
-chan_data [CH 3]: 4337 2168 1084
-
-=================================
-benchmark [CH 0]: 4109 2054 1027
-chan_data [CH 0]: 4109 2054 1027
-
-benchmark [CH 1]: 4638 2318 1158
-chan_data [CH 1]: 4638 2318 1158
-
-benchmark [CH 2]: 4843 2421 1210
-chan_data [CH 2]: 4845 2421 1210
-
-benchmark [CH 3]: 4334 2167 1084
-chan_data [CH 3]: 4334 2167 1083
-...
-```
-
-And if you touch and release a button, you will see the following output:
-
-```
-...
-I (1321) touch_callback: [CH 1] active
-=================================
-benchmark [CH 0]: 4111 2055 1027
-chan_data [CH 0]: 4111 2055 1027
-
-benchmark [CH 1]: 4676 2339 1168
-chan_data [CH 1]: 17701 8798 4399
-
-benchmark [CH 2]: 4870 2434 1217
-chan_data [CH 2]: 4867 2433 1217
-
-benchmark [CH 3]: 4333 2165 1082
-chan_data [CH 3]: 4333 2165 1082
-
-=================================
-benchmark [CH 0]: 4109 2053 1027
-chan_data [CH 0]: 4108 2053 1027
-
-benchmark [CH 1]: 4676 2339 1168
-chan_data [CH 1]: 11256 8817 4363
-
-benchmark [CH 2]: 4868 2434 1217
-chan_data [CH 2]: 4862 2429 1214
-
-benchmark [CH 3]: 4332 2165 1082
-chan_data [CH 3]: 4330 2164 1081
-
-I (1931) touch_callback: [CH 1] inactive
-=================================
-benchmark [CH 0]: 4106 2052 1026
-chan_data [CH 0]: 4106 2052 1026
-
-benchmark [CH 1]: 4649 2323 1161
-chan_data [CH 1]: 4650 2323 1161
-
-benchmark [CH 2]: 4847 2422 1211
-chan_data [CH 2]: 4846 2422 1211
-
-benchmark [CH 3]: 4329 2163 1082
-chan_data [CH 3]: 4329 2164 1082
-...
-```
-
-## Troubleshooting
-
-For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon.
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v3/main/CMakeLists.txt b/examples/peripherals/touch_sensor/touch_sensor_v3/main/CMakeLists.txt
deleted file mode 100644
index 8c6b0002d3b..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v3/main/CMakeLists.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-idf_component_register(SRCS "touch_sens_v3_example_main.c"
-                    REQUIRES esp_driver_touch_sens
-                    INCLUDE_DIRS ".")
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v3/main/touch_sens_v3_example_main.c b/examples/peripherals/touch_sensor/touch_sensor_v3/main/touch_sens_v3_example_main.c
deleted file mode 100644
index 77d37045f08..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v3/main/touch_sens_v3_example_main.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: CC0-1.0
- */
-
-#include <stdio.h>
-#include <inttypes.h>
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "driver/touch_sens.h"
-#include "esp_check.h"
-
-// Touch version 3 supports multiple sample configurations
-#define EXAMPLE_TOUCH_SAMPLE_CFG_NUM        1  // Up to 'TOUCH_SAMPLE_CFG_NUM'
-#define EXAMPLE_TOUCH_CHANNEL_NUM           4
-#define EXAMPLE_TOUCH_CHAN_INIT_SCAN_TIMES  3
-
-static touch_sensor_handle_t  s_sens_handle = NULL;
-static touch_channel_handle_t s_chan_handle[EXAMPLE_TOUCH_CHANNEL_NUM] = {};
-// Active threshold to benchmark ratio. (i.e., touch will be activated when data >= benchmark * (1 + ratio))
-static float s_thresh2bm_ratio[EXAMPLE_TOUCH_CHANNEL_NUM] = {
-    [0 ... EXAMPLE_TOUCH_CHANNEL_NUM - 1] = 0.015f,  // 1.5%
-};
-
-bool example_touch_on_active_callback(touch_sensor_handle_t sens_handle, const touch_active_event_data_t *event, void *user_ctx)
-{
-    ESP_EARLY_LOGI("touch_callback", "[CH %d] active", (int)event->chan_id);
-    return false;
-}
-
-bool example_touch_on_inactive_callback(touch_sensor_handle_t sens_handle, const touch_inactive_event_data_t *event, void *user_ctx)
-{
-    ESP_EARLY_LOGI("touch_callback", "[CH %d] inactive", (int)event->chan_id);
-    return false;
-}
-
-static void example_touch_do_initial_scanning(void)
-{
-    /* Enable the touch sensor to do the initial scanning, so that to initialize the channel data */
-    ESP_ERROR_CHECK(touch_sensor_enable(s_sens_handle));
-
-    /* Scan the enabled touch channels for several times, to make sure the initial channel data is stable */
-    for (int i = 0; i < EXAMPLE_TOUCH_CHAN_INIT_SCAN_TIMES; i++) {
-        ESP_ERROR_CHECK(touch_sensor_trigger_oneshot_scanning(s_sens_handle, 2000));
-    }
-
-    /* Disable the touch channel to rollback the state */
-    ESP_ERROR_CHECK(touch_sensor_disable(s_sens_handle));
-
-    /* (Optional) Read the initial channel benchmark and reconfig the channel active threshold accordingly */
-    printf("Initial benchmark and new threshold are:\n");
-    for (int i = 0; i < EXAMPLE_TOUCH_CHANNEL_NUM; i++) {
-        /* Read the initial benchmark of the touch channel */
-        uint32_t benchmark[EXAMPLE_TOUCH_SAMPLE_CFG_NUM] = {};
-        ESP_ERROR_CHECK(touch_channel_read_data(s_chan_handle[i], TOUCH_CHAN_DATA_TYPE_BENCHMARK, benchmark));
-        /* Calculate the proper active thresholds regarding the initial benchmark */
-        printf("[CH %d]", i);
-        touch_channel_config_t chan_cfg = {};
-        for (int j = 0; j < EXAMPLE_TOUCH_SAMPLE_CFG_NUM; j++) {
-            chan_cfg.active_thresh[j] = (uint32_t)(benchmark[j] * s_thresh2bm_ratio[i]);
-            printf(" %d: %"PRIu32", %"PRIu32"\t", j, benchmark[j], chan_cfg.active_thresh[j]);
-        }
-        printf("\n");
-        /* Update the channel configuration */
-        ESP_ERROR_CHECK(touch_sensor_reconfig_channel(s_chan_handle[i], &chan_cfg));
-    }
-}
-
-void app_main(void)
-{
-    /* Use the default sample configurations */
-    touch_sensor_sample_config_t sample_cfg[EXAMPLE_TOUCH_SAMPLE_CFG_NUM] = {
-        TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(1, 1, 1),
-#if EXAMPLE_TOUCH_SAMPLE_CFG_NUM > 1
-        TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(2, 1, 1),
-#endif
-#if EXAMPLE_TOUCH_SAMPLE_CFG_NUM > 2
-        TOUCH_SENSOR_V3_DEFAULT_SAMPLE_CONFIG(4, 1, 1),
-#endif
-    };
-    /* Allocate new touch controller handle */
-    touch_sensor_config_t sens_cfg = TOUCH_SENSOR_DEFAULT_BASIC_CONFIG(EXAMPLE_TOUCH_SAMPLE_CFG_NUM, sample_cfg);
-    ESP_ERROR_CHECK(touch_sensor_new_controller(&sens_cfg, &s_sens_handle));
-
-    /* Configure the touch sensor filter */
-    touch_sensor_filter_config_t filter_cfg = TOUCH_SENSOR_DEFAULT_FILTER_CONFIG();
-    ESP_ERROR_CHECK(touch_sensor_config_filter(s_sens_handle, &filter_cfg));
-
-    /* Allocate new touch channel on the touch controller */
-    touch_channel_config_t chan_cfg = {
-        /** Set the touch channel active threshold of each sample configuration.
-         *
-         *  @How to Determine:
-         *  As the actual threshold is affected by various factors in real application,
-         *  we need to run the touch app first to get the `benchmark` and the `smooth_data` that being touched.
-         *
-         *  @Formula:
-         *  threshold = benchmark * coeff, (coeff for example, 0.1%~20%)
-         *  Please adjust the coeff to guarantee the threshold < smooth_data - benchmark
-         *
-         *  @Typical Practice:
-         *  Normally, we can't determine a fixed threshold at the beginning,
-         *  but we can give them estimated values first and update them after an initial scanning (like this example),
-         *  Step1: set an estimated value for each sample configuration first. (i.e., here)
-         *  Step2: then reconfig the threshold after the initial scanning.(see `example_touch_do_initial_scanning`)
-         *  Step3: adjust the `s_thresh2bm_ratio` to a proper value to trigger the active callback
-         */
-        .active_thresh = {
-            1000,       // estimated active threshold of sample configuration 0
-#if EXAMPLE_TOUCH_SAMPLE_CFG_NUM > 1
-            2500,       // estimated active threshold of sample configuration 1
-#endif
-#if EXAMPLE_TOUCH_SAMPLE_CFG_NUM > 2
-            5000,       // estimated active threshold of sample configuration 2
-#endif
-        },
-    };
-    for (int i = 0; i < EXAMPLE_TOUCH_CHANNEL_NUM; i++) {
-        ESP_ERROR_CHECK(touch_sensor_new_channel(s_sens_handle, i, &chan_cfg, &s_chan_handle[i]));
-    }
-
-    /* Do the initial scanning to initialize the touch channel data
-     * Without this step, the channel data in the first read will be invalid
-     */
-    example_touch_do_initial_scanning();
-
-    /* Register the touch sensor callbacks, here only take `active` and `deactivate` event for example */
-    touch_event_callbacks_t callbacks = {
-        .on_active = example_touch_on_active_callback,
-        .on_inactive = example_touch_on_inactive_callback,
-        .on_measure_done = NULL,
-        .on_scan_done = NULL,
-        .on_timeout = NULL,
-        .on_proximity_meas_done = NULL,
-    };
-    ESP_ERROR_CHECK(touch_sensor_register_callbacks(s_sens_handle, &callbacks, NULL));
-
-    /* Enable the touch sensor */
-    ESP_ERROR_CHECK(touch_sensor_enable(s_sens_handle));
-
-    /* Start continuous scanning, you can also trigger oneshot scanning manually */
-    ESP_ERROR_CHECK(touch_sensor_start_continuous_scanning(s_sens_handle));
-
-    uint32_t benchmark[EXAMPLE_TOUCH_SAMPLE_CFG_NUM] = {};
-    uint32_t chan_data[EXAMPLE_TOUCH_SAMPLE_CFG_NUM] = {};
-    while (1) {
-        printf("=================================\n");
-        for (int i = 0; i < EXAMPLE_TOUCH_CHANNEL_NUM; i++) {
-            /* Read and print the benchmark of each sample configuration */
-            ESP_ERROR_CHECK(touch_channel_read_data(s_chan_handle[i], TOUCH_CHAN_DATA_TYPE_BENCHMARK, benchmark));
-            printf("benchmark [CH %d]:", i);
-            for (int j = 0; j < EXAMPLE_TOUCH_SAMPLE_CFG_NUM; j++) {
-                printf(" %"PRIu32, benchmark[j]);
-            }
-            printf("\n");
-            /* Read and print the channel data of each sample configuration */
-            ESP_ERROR_CHECK(touch_channel_read_data(s_chan_handle[i], TOUCH_CHAN_DATA_TYPE_SMOOTH, chan_data));
-            printf("chan_data [CH %d]:", i);
-            for (int j = 0; j < EXAMPLE_TOUCH_SAMPLE_CFG_NUM; j++) {
-                printf(" %"PRIu32, chan_data[j]);
-            }
-            printf("\n\n");
-        }
-        /* Read and display the data every 300 ms */
-        vTaskDelay(pdMS_TO_TICKS(300));
-    }
-}
diff --git a/examples/peripherals/touch_sensor/touch_sensor_v3/pytest_touch_sens_v3.py b/examples/peripherals/touch_sensor/touch_sensor_v3/pytest_touch_sens_v3.py
deleted file mode 100644
index f03c56c2ffd..00000000000
--- a/examples/peripherals/touch_sensor/touch_sensor_v3/pytest_touch_sens_v3.py
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
-# SPDX-License-Identifier: Unlicense OR CC0-1.0
-import pytest
-from pytest_embedded import Dut
-
-
-@pytest.mark.esp32p4
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 runners do not support touch pins')
-@pytest.mark.generic
-def test_touch_sens_v3(dut: Dut) -> None:
-    dut.expect_exact('Initial benchmark and new threshold are:')
-    dut.expect(r'\[CH [0-9]+\] 0: [0-9]+, [0-9]+')
-    dut.expect(r'benchmark \[CH [0-9]+\]: [0-9]+')
-    dut.expect(r'chan_data \[CH [0-9]+\]: [0-9]+')
diff --git a/examples/peripherals/usb/README.md b/examples/peripherals/usb/README.md
index 2d23a497d73..c25ec63e52a 100644
--- a/examples/peripherals/usb/README.md
+++ b/examples/peripherals/usb/README.md
@@ -1,10 +1,10 @@
 # USB-OTG Examples
 
-See the [README.md](../README.md) file in the upper level [examples](../) directory for more information about examples.
+See the [README.md](../../README.md) file in the upper level [examples](../../) directory for more information about examples.
 
 ## Common Pin Assignments
 
-Pin assignment is only needed for ESP chips that have an USB-OTG peripheral.
+Pin assignment is only needed for ESP chips that have a USB-OTG peripheral.
 If your board doesn't have a USB connector connected to the USB-OTG dedicated GPIOs, you may have to DIY a cable and connect **D+** and **D-** to the pins listed below.
 
 ```
@@ -21,3 +21,6 @@ Refer to `soc/usb_pins.h` to find the real GPIO number of **USBPHY_DP_NUM** and
 |             | USB_DP | USB_DM |
 | ----------- | ------ | ------ |
 | ESP32-S2/S3 | GPIO20 | GPIO19 |
+| ESP32-P4    | pin 51 | pin 50 |
+
+> Note: On the ESP32-P4, the USB 2.0 PHY pins are dedicated to USB-OTG functionality and cannot be used as general-purpose GPIOs.
diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_host/README.md b/examples/peripherals/usb/host/cdc/cdc_acm_host/README.md
index 8f1d6652ff2..504c16e5494 100644
--- a/examples/peripherals/usb/host/cdc/cdc_acm_host/README.md
+++ b/examples/peripherals/usb/host/cdc/cdc_acm_host/README.md
@@ -11,12 +11,11 @@ This example shows how to use the CDC-ACM Host Driver to allow an ESP chip to co
 
 ### Hardware Required
 
-Two ESP boards that have USB-OTG supported. One will act as USB host and the other as USB device.  
-Connect USB_D+, USB_D-, GND and +5V signals of USB host to USB device.
+Two development boards with USB-OTG support. One will act as USB host and the other as USB device.  
 
 #### Pin Assignment
 
-See common pin assignments for USB Device examples from [upper level](../../../README.md#common-pin-assignments).
+Follow instruction in [examples/usb/README.md](../../../README.md) for specific hardware setup.
 
 ### Build and Flash
 
diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/README.md b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/README.md
index 7f3dcd02f1b..2883ef06198 100644
--- a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/README.md
+++ b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/README.md
@@ -5,28 +5,26 @@
 
 (See the README.md file in the upper level 'examples' directory for more information about examples.)
 
-This example shows how to extend CDC-ACM driver for Virtual Communication Port (VCP) devices,
-such as CP210x, FTDI FT23x or CH34x devices.
+This example shows how to extend CDC-ACM driver for Virtual Communication Port (VCP) devices, such as CP210x, FTDI FT23x or CH34x devices.
 
 The drivers are fetched from [ESP Component Registry](https://components.espressif.com/) together with VCP service that automatically loads correct driver for plugged-in device.
 
 ## How to use example
 
-1. Connect your USB<->UART converter to ESP32-S2/S3, the device will be automatically enumerated and correct driver will be loaded
+1. Connect your USB<->UART converter to ESP board, the device will be automatically enumerated and correct driver will be loaded
 2. Change baudrate and other line coding parameters in [cdc_acm_vcp_example_main.cpp](main/cdc_acm_vcp_example_main.cpp) to match your needs
 3. Now you can use the usual CDC-ACM API to control the device and send data. Data are received in `handle_rx` callback
 4. Try disconnecting and then reconnecting of the USB device to experiment with USB hotplugging
 
 ### Hardware Required
 
-* ESP board with USB-OTG supported
+* Development board with USB-OTG support
+* A USB cable for Power supply and programming
 * Silicon Labs CP210x, FTDI FT23x or CP34x USB to UART converter
 
-Connect USB_D+, USB_D-, GND and +5V signals of your ESP chip to matching signals on USB to UART converter.
-
 #### Pin Assignment
 
-See common pin assignments for USB Device examples from [upper level](../../../README.md#common-pin-assignments).
+Follow instruction in [examples/usb/README.md](../../../README.md) for specific hardware setup.
 
 ### Build and Flash
 
diff --git a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/sdkconfig.defaults b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/sdkconfig.defaults
index 990777805d6..a3e635c9d8d 100644
--- a/examples/peripherals/usb/host/cdc/cdc_acm_vcp/sdkconfig.defaults
+++ b/examples/peripherals/usb/host/cdc/cdc_acm_vcp/sdkconfig.defaults
@@ -2,3 +2,4 @@
 # Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
 #
 CONFIG_COMPILER_CXX_EXCEPTIONS=y
+CONFIG_USB_HOST_HUBS_SUPPORTED=y
diff --git a/examples/peripherals/usb/host/hid/README.md b/examples/peripherals/usb/host/hid/README.md
index 281c1805f08..9c52850ee83 100644
--- a/examples/peripherals/usb/host/hid/README.md
+++ b/examples/peripherals/usb/host/hid/README.md
@@ -6,24 +6,13 @@ This example implements a basic USB Host HID Class Driver, and demonstrates how
 
 
 ### Hardware Required
-* Development board with USB capable ESP SoC (ESP32-S2/ESP32-S3)
+* Development board with USB-OTG support
 * A USB cable for Power supply and programming
 * USB OTG Cable
 
 ### Common Pin Assignments
 
-If your board doesn't have a USB A connector connected to the dedicated GPIOs, 
-you may have to DIY a cable and connect **D+** and **D-** to the pins listed below.
-
-```
-ESP BOARD    USB CONNECTOR (type A)
-                   --
-                  | || VCC
-[GPIO19]  ------> | || D-
-[GPIO20]  ------> | || D+
-                  | || GND
-                   --
-```
+Follow instructions in [examples/usb/README.md](../../README.md) for specific hardware setup.
 
 ### Build and Flash
 
diff --git a/examples/peripherals/usb/host/hid/main/hid_host_example.c b/examples/peripherals/usb/host/hid/main/hid_host_example.c
index ca8783f0b25..fde9f95dbd4 100644
--- a/examples/peripherals/usb/host/hid/main/hid_host_example.c
+++ b/examples/peripherals/usb/host/hid/main/hid_host_example.c
@@ -32,7 +32,7 @@ QueueHandle_t app_event_queue = NULL;
 /**
  * @brief APP event group
  *
- * Application logic can be different. There is a one among other ways to distingiush the
+ * Application logic can be different. There is a one among other ways to distinguish the
  * event by application event group.
  * In this example we have two event groups:
  * APP_EVENT            - General event, which is APP_QUIT_PIN press event (Generally, it is IO0).
diff --git a/examples/peripherals/usb/host/hid/sdkconfig.defaults b/examples/peripherals/usb/host/hid/sdkconfig.defaults
new file mode 100644
index 00000000000..bf1b553b238
--- /dev/null
+++ b/examples/peripherals/usb/host/hid/sdkconfig.defaults
@@ -0,0 +1,4 @@
+# This file was generated using idf.py save-defconfig. It can be edited manually.
+# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
+#
+CONFIG_USB_HOST_HUBS_SUPPORTED=y
diff --git a/examples/peripherals/usb/host/msc/README.md b/examples/peripherals/usb/host/msc/README.md
index 94fe45587ac..67504d559ba 100644
--- a/examples/peripherals/usb/host/msc/README.md
+++ b/examples/peripherals/usb/host/msc/README.md
@@ -12,6 +12,7 @@ This example demonstrates usage of the MSC (Mass Storage Class) to access storag
 3. Create `ESP` subdirectory (if not present already), as well as a `text.txt` file
 4. Run read/write benchmarks by transferring 1 MB of data to a `dummy` file
 
+> Note: This example currently supports only FAT-formatted drives. Other file systems, such as exFAT or NTFS, are not compatible with this example. Please ensure that your USB drive is formatted as FAT to avoid compatibility issues.
 
 ### USB Reconnections
 
@@ -20,24 +21,13 @@ The example is run in a loop so that it can demonstrate USB connection and recon
 
 ### Hardware Required
 
-* Development board with USB capable ESP SoC (ESP32-S2/ESP32-S3)
+* Development board with USB-OTG support
 * A USB cable for Power supply and programming
 * A USB flash drive
 
 ### Common Pin Assignments
 
-If your board doesn't have a USB A connector connected to the dedicated GPIOs, 
-you may have to DIY a cable and connect **D+** and **D-** to the pins listed below.
-
-```
-ESP BOARD    USB CONNECTOR (type A)
-                   --
-                  | || VCC
-[GPIO19]  ------> | || D-
-[GPIO20]  ------> | || D+
-                  | || GND
-                   --
-```
+Follow instructions in [examples/usb/README.md](../../README.md) for specific hardware setup.
 
 Additionally, GPIO0 can be shorted to ground in order to deinitialize USB stack. 
 
diff --git a/examples/peripherals/usb/host/msc/main/msc_example_main.c b/examples/peripherals/usb/host/msc/main/msc_example_main.c
index eb934a56810..630c95e6b15 100644
--- a/examples/peripherals/usb/host/msc/main/msc_example_main.c
+++ b/examples/peripherals/usb/host/msc/main/msc_example_main.c
@@ -29,6 +29,11 @@ static const char *TAG = "example";
 #define APP_QUIT_PIN     GPIO_NUM_0 // BOOT button on most boards
 #define BUFFER_SIZE      4096       // The read/write performance can be improved with larger buffer for the cost of RAM, 4kB is enough for most usecases
 
+// IMPORTANT NOTE
+// MSC Class Driver is not fully support connecting devices through external Hub.
+// TODO: Remove this line after MSC Class Driver will support it
+static bool dev_present = false;
+
 /**
  * @brief Application Queue and its messages ID
  */
@@ -78,7 +83,7 @@ static void gpio_cb(void *arg)
 static void msc_event_cb(const msc_host_event_t *event, void *arg)
 {
     if (event->event == MSC_DEVICE_CONNECTED) {
-        ESP_LOGI(TAG, "MSC device connected");
+        ESP_LOGI(TAG, "MSC device connected (usb_addr=%d)", event->device.address);
         app_message_t message = {
             .id = APP_DEVICE_CONNECTED,
             .data.new_dev_address = event->device.address,
@@ -274,47 +279,56 @@ void app_main(void)
         xQueueReceive(app_queue, &msg, portMAX_DELAY);
 
         if (msg.id == APP_DEVICE_CONNECTED) {
-            // 1. MSC flash drive connected. Open it and map it to Virtual File System
-            ESP_ERROR_CHECK(msc_host_install_device(msg.data.new_dev_address, &msc_device));
-            const esp_vfs_fat_mount_config_t mount_config = {
-                .format_if_mount_failed = false,
-                .max_files = 3,
-                .allocation_unit_size = 8192,
-            };
-            ESP_ERROR_CHECK(msc_host_vfs_register(msc_device, MNT_PATH, &mount_config, &vfs_handle));
-
-            // 2. Print information about the connected disk
-            msc_host_device_info_t info;
-            ESP_ERROR_CHECK(msc_host_get_device_info(msc_device, &info));
-            msc_host_print_descriptors(msc_device);
-            print_device_info(&info);
-
-            // 3. List all the files in root directory
-            ESP_LOGI(TAG, "ls command output:");
-            struct dirent *d;
-            DIR *dh = opendir(MNT_PATH);
-            assert(dh);
-            while ((d = readdir(dh)) != NULL) {
-                printf("%s\n", d->d_name);
+            if (dev_present) {
+                ESP_LOGW(TAG, "MSC Example handles only one device at a time");
+            } else {
+                // 0. Change flag
+                dev_present = true;
+                // 1. MSC flash drive connected. Open it and map it to Virtual File System
+                ESP_ERROR_CHECK(msc_host_install_device(msg.data.new_dev_address, &msc_device));
+                const esp_vfs_fat_mount_config_t mount_config = {
+                    .format_if_mount_failed = false,
+                    .max_files = 3,
+                    .allocation_unit_size = 8192,
+                };
+                ESP_ERROR_CHECK(msc_host_vfs_register(msc_device, MNT_PATH, &mount_config, &vfs_handle));
+
+                // 2. Print information about the connected disk
+                msc_host_device_info_t info;
+                ESP_ERROR_CHECK(msc_host_get_device_info(msc_device, &info));
+                msc_host_print_descriptors(msc_device);
+                print_device_info(&info);
+
+                // 3. List all the files in root directory
+                ESP_LOGI(TAG, "ls command output:");
+                struct dirent *d;
+                DIR *dh = opendir(MNT_PATH);
+                assert(dh);
+                while ((d = readdir(dh)) != NULL) {
+                    printf("%s\n", d->d_name);
+                }
+                closedir(dh);
+
+                // 4. The disk is mounted to Virtual File System, perform some basic demo file operation
+                file_operations();
+
+                // 5. Perform speed test
+                speed_test();
+
+                ESP_LOGI(TAG, "Example finished, you can disconnect the USB flash drive");
             }
-            closedir(dh);
-
-            // 4. The disk is mounted to Virtual File System, perform some basic demo file operation
-            file_operations();
-
-            // 5. Perform speed test
-            speed_test();
-
-            ESP_LOGI(TAG, "Example finished, you can disconnect the USB flash drive");
         }
         if ((msg.id == APP_DEVICE_DISCONNECTED) || (msg.id == APP_QUIT)) {
-            if (vfs_handle) {
-                ESP_ERROR_CHECK(msc_host_vfs_unregister(vfs_handle));
-                vfs_handle = NULL;
-            }
-            if (msc_device) {
-                ESP_ERROR_CHECK(msc_host_uninstall_device(msc_device));
-                msc_device = NULL;
+            if (dev_present) {
+                dev_present = false;
+                if (vfs_handle) {
+                    ESP_ERROR_CHECK(msc_host_vfs_unregister(vfs_handle));
+                    vfs_handle = NULL;
+                }
+                if (msc_device) {
+                    ESP_ERROR_CHECK(msc_host_uninstall_device(msc_device));
+                    msc_device = NULL;
+                }
             }
             if (msg.id == APP_QUIT) {
                 // This will cause the usb_task to exit
diff --git a/examples/peripherals/usb/host/msc/sdkconfig.defaults b/examples/peripherals/usb/host/msc/sdkconfig.defaults
new file mode 100644
index 00000000000..bf1b553b238
--- /dev/null
+++ b/examples/peripherals/usb/host/msc/sdkconfig.defaults
@@ -0,0 +1,4 @@
+# This file was generated using idf.py save-defconfig. It can be edited manually.
+# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
+#
+CONFIG_USB_HOST_HUBS_SUPPORTED=y
diff --git a/examples/peripherals/usb/host/usb_host_lib/README.md b/examples/peripherals/usb/host/usb_host_lib/README.md
index a391aedd9bf..e7a2028e181 100644
--- a/examples/peripherals/usb/host/usb_host_lib/README.md
+++ b/examples/peripherals/usb/host/usb_host_lib/README.md
@@ -32,11 +32,8 @@ The example demonstrates the following aspects of the USB Host Library API:
 
 ### Hardware Required
 
-An ESP board that has a push button and supports USB-OTG. The example uses the ESP's internal USB PHY, however the internal USB PHY's pins will need to be connected to a USB port (i.e., a USB breakout board) as follows:
-
-- GND and 5V signals of the ESP board to the GND and 5V lines of the USB port
-- GPIO 19 to D-
-- GPIO 20 to D+
+* Development board with USB-OTG support.
+* Follow instruction in [examples/usb/README.md](../../README.md) for specific hardware setup.
 
 ### Configure the project
 
diff --git a/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c b/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c
index 594488df519..5a89e40dea3 100644
--- a/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c
+++ b/examples/peripherals/usb/host/usb_host_lib/main/class_driver.c
@@ -13,21 +13,40 @@
 #define CLIENT_NUM_EVENT_MSG        5
 
 typedef enum {
-    ACTION_OPEN_DEV = 0x01,
-    ACTION_GET_DEV_INFO = 0x02,
-    ACTION_GET_DEV_DESC = 0x04,
-    ACTION_GET_CONFIG_DESC = 0x08,
-    ACTION_GET_STR_DESC = 0x10,
-    ACTION_CLOSE_DEV = 0x20,
-    ACTION_EXIT = 0x40,
-    ACTION_RECONNECT = 0x80,
+    ACTION_OPEN_DEV         = (1 << 0),
+    ACTION_GET_DEV_INFO     = (1 << 1),
+    ACTION_GET_DEV_DESC     = (1 << 2),
+    ACTION_GET_CONFIG_DESC  = (1 << 3),
+    ACTION_GET_STR_DESC     = (1 << 4),
+    ACTION_CLOSE_DEV        = (1 << 5),
 } action_t;
 
+#define DEV_MAX_COUNT           128
+
 typedef struct {
     usb_host_client_handle_t client_hdl;
     uint8_t dev_addr;
     usb_device_handle_t dev_hdl;
-    uint32_t actions;
+    action_t actions;
+} usb_device_t;
+
+typedef struct {
+    struct {
+        union {
+            struct {
+                uint8_t unhandled_devices: 1;   /**< Device has unhandled devices */
+                uint8_t shutdown: 1;            /**<  */
+                uint8_t reserved6: 6;           /**< Reserved */
+            };
+            uint8_t val;                        /**< Class drivers' flags value */
+        } flags;                                /**< Class drivers' flags */
+        usb_device_t device[DEV_MAX_COUNT];     /**< Class drivers' static array of devices */
+    } mux_protected;                            /**< Mutex protected members. Must be protected by the Class mux_lock when accessed */
+
+    struct {
+        usb_host_client_handle_t client_hdl;
+        SemaphoreHandle_t mux_lock;         /**< Mutex for protected members */
+    } constant;                                 /**< Constant members. Do not change after installation thus do not require a critical section or mutex */
 } class_driver_t;
 
 static const char *TAG = "CLASS";
@@ -38,79 +57,94 @@ static void client_event_cb(const usb_host_client_event_msg_t *event_msg, void *
     class_driver_t *driver_obj = (class_driver_t *)arg;
     switch (event_msg->event) {
     case USB_HOST_CLIENT_EVENT_NEW_DEV:
-        if (driver_obj->dev_addr == 0) {
-            driver_obj->dev_addr = event_msg->new_dev.address;
-            //Open the device next
-            driver_obj->actions |= ACTION_OPEN_DEV;
-        }
+        // Save the device address
+        xSemaphoreTake(driver_obj->constant.mux_lock, portMAX_DELAY);
+        driver_obj->mux_protected.device[event_msg->new_dev.address].dev_addr = event_msg->new_dev.address;
+        driver_obj->mux_protected.device[event_msg->new_dev.address].dev_hdl = NULL;
+        // Open the device next
+        driver_obj->mux_protected.device[event_msg->new_dev.address].actions |= ACTION_OPEN_DEV;
+        // Set flag
+        driver_obj->mux_protected.flags.unhandled_devices = 1;
+        xSemaphoreGive(driver_obj->constant.mux_lock);
         break;
     case USB_HOST_CLIENT_EVENT_DEV_GONE:
-        if (driver_obj->dev_hdl != NULL) {
-            //Cancel any other actions and close the device next
-            driver_obj->actions = ACTION_CLOSE_DEV;
+        // Cancel any other actions and close the device next
+        xSemaphoreTake(driver_obj->constant.mux_lock, portMAX_DELAY);
+        for (uint8_t i = 0; i < DEV_MAX_COUNT; i++) {
+            if (driver_obj->mux_protected.device[i].dev_hdl == event_msg->dev_gone.dev_hdl) {
+                driver_obj->mux_protected.device[i].actions = ACTION_CLOSE_DEV;
+                // Set flag
+                driver_obj->mux_protected.flags.unhandled_devices = 1;
+            }
         }
+        xSemaphoreGive(driver_obj->constant.mux_lock);
         break;
     default:
-        //Should never occur
+        // Should never occur
         abort();
     }
 }
 
-static void action_open_dev(class_driver_t *driver_obj)
+static void action_open_dev(usb_device_t *device_obj)
 {
-    assert(driver_obj->dev_addr != 0);
-    ESP_LOGI(TAG, "Opening device at address %d", driver_obj->dev_addr);
-    ESP_ERROR_CHECK(usb_host_device_open(driver_obj->client_hdl, driver_obj->dev_addr, &driver_obj->dev_hdl));
-    //Get the device's information next
-    driver_obj->actions &= ~ACTION_OPEN_DEV;
-    driver_obj->actions |= ACTION_GET_DEV_INFO;
+    assert(device_obj->dev_addr != 0);
+    ESP_LOGI(TAG, "Opening device at address %d", device_obj->dev_addr);
+    ESP_ERROR_CHECK(usb_host_device_open(device_obj->client_hdl, device_obj->dev_addr, &device_obj->dev_hdl));
+    // Get the device's information next
+    device_obj->actions |= ACTION_GET_DEV_INFO;
 }
 
-static void action_get_info(class_driver_t *driver_obj)
+static void action_get_info(usb_device_t *device_obj)
 {
-    assert(driver_obj->dev_hdl != NULL);
+    assert(device_obj->dev_hdl != NULL);
     ESP_LOGI(TAG, "Getting device information");
     usb_device_info_t dev_info;
-    ESP_ERROR_CHECK(usb_host_device_info(driver_obj->dev_hdl, &dev_info));
+    ESP_ERROR_CHECK(usb_host_device_info(device_obj->dev_hdl, &dev_info));
     ESP_LOGI(TAG, "\t%s speed", (char *[]) {
         "Low", "Full", "High"
     }[dev_info.speed]);
-    ESP_LOGI(TAG, "\tbConfigurationValue %d", dev_info.bConfigurationValue);
+    ESP_LOGI(TAG, "\tParent info:");
+    if (dev_info.parent.dev_hdl) {
+        usb_device_info_t parent_dev_info;
+        ESP_ERROR_CHECK(usb_host_device_info(dev_info.parent.dev_hdl, &parent_dev_info));
+        ESP_LOGI(TAG, "\t\tBus addr: %d", parent_dev_info.dev_addr);
+        ESP_LOGI(TAG, "\t\tPort: %d", dev_info.parent.port_num);
 
-    //Get the device descriptor next
-    driver_obj->actions &= ~ACTION_GET_DEV_INFO;
-    driver_obj->actions |= ACTION_GET_DEV_DESC;
+    } else {
+        ESP_LOGI(TAG, "\t\tPort: ROOT");
+    }
+    ESP_LOGI(TAG, "\tbConfigurationValue %d", dev_info.bConfigurationValue);
+    // Get the device descriptor next
+    device_obj->actions |= ACTION_GET_DEV_DESC;
 }
 
-static void action_get_dev_desc(class_driver_t *driver_obj)
+static void action_get_dev_desc(usb_device_t *device_obj)
 {
-    assert(driver_obj->dev_hdl != NULL);
+    assert(device_obj->dev_hdl != NULL);
     ESP_LOGI(TAG, "Getting device descriptor");
     const usb_device_desc_t *dev_desc;
-    ESP_ERROR_CHECK(usb_host_get_device_descriptor(driver_obj->dev_hdl, &dev_desc));
+    ESP_ERROR_CHECK(usb_host_get_device_descriptor(device_obj->dev_hdl, &dev_desc));
     usb_print_device_descriptor(dev_desc);
-    //Get the device's config descriptor next
-    driver_obj->actions &= ~ACTION_GET_DEV_DESC;
-    driver_obj->actions |= ACTION_GET_CONFIG_DESC;
+    // Get the device's config descriptor next
+    device_obj->actions |= ACTION_GET_CONFIG_DESC;
 }
 
-static void action_get_config_desc(class_driver_t *driver_obj)
+static void action_get_config_desc(usb_device_t *device_obj)
 {
-    assert(driver_obj->dev_hdl != NULL);
+    assert(device_obj->dev_hdl != NULL);
     ESP_LOGI(TAG, "Getting config descriptor");
     const usb_config_desc_t *config_desc;
-    ESP_ERROR_CHECK(usb_host_get_active_config_descriptor(driver_obj->dev_hdl, &config_desc));
+    ESP_ERROR_CHECK(usb_host_get_active_config_descriptor(device_obj->dev_hdl, &config_desc));
     usb_print_config_descriptor(config_desc, NULL);
-    //Get the device's string descriptors next
-    driver_obj->actions &= ~ACTION_GET_CONFIG_DESC;
-    driver_obj->actions |= ACTION_GET_STR_DESC;
+    // Get the device's string descriptors next
+    device_obj->actions |= ACTION_GET_STR_DESC;
 }
 
-static void action_get_str_desc(class_driver_t *driver_obj)
+static void action_get_str_desc(usb_device_t *device_obj)
 {
-    assert(driver_obj->dev_hdl != NULL);
+    assert(device_obj->dev_hdl != NULL);
     usb_device_info_t dev_info;
-    ESP_ERROR_CHECK(usb_host_device_info(driver_obj->dev_hdl, &dev_info));
+    ESP_ERROR_CHECK(usb_host_device_info(device_obj->dev_hdl, &dev_info));
     if (dev_info.str_desc_manufacturer) {
         ESP_LOGI(TAG, "Getting Manufacturer string descriptor");
         usb_print_string_descriptor(dev_info.str_desc_manufacturer);
@@ -123,25 +157,59 @@ static void action_get_str_desc(class_driver_t *driver_obj)
         ESP_LOGI(TAG, "Getting Serial Number string descriptor");
         usb_print_string_descriptor(dev_info.str_desc_serial_num);
     }
-    //Nothing to do until the device disconnects
-    driver_obj->actions &= ~ACTION_GET_STR_DESC;
 }
 
-static void action_close_dev(class_driver_t *driver_obj)
+static void action_close_dev(usb_device_t *device_obj)
 {
-    ESP_ERROR_CHECK(usb_host_device_close(driver_obj->client_hdl, driver_obj->dev_hdl));
-    driver_obj->dev_hdl = NULL;
-    driver_obj->dev_addr = 0;
-    //We need to connect a new device
-    driver_obj->actions &= ~ACTION_CLOSE_DEV;
-    driver_obj->actions |= ACTION_RECONNECT;
+    ESP_ERROR_CHECK(usb_host_device_close(device_obj->client_hdl, device_obj->dev_hdl));
+    device_obj->dev_hdl = NULL;
+    device_obj->dev_addr = 0;
+}
+
+static void class_driver_device_handle(usb_device_t *device_obj)
+{
+    uint8_t actions = device_obj->actions;
+    device_obj->actions = 0;
+
+    while (actions) {
+        if (actions & ACTION_OPEN_DEV) {
+            action_open_dev(device_obj);
+        }
+        if (actions & ACTION_GET_DEV_INFO) {
+            action_get_info(device_obj);
+        }
+        if (actions & ACTION_GET_DEV_DESC) {
+            action_get_dev_desc(device_obj);
+        }
+        if (actions & ACTION_GET_CONFIG_DESC) {
+            action_get_config_desc(device_obj);
+        }
+        if (actions & ACTION_GET_STR_DESC) {
+            action_get_str_desc(device_obj);
+        }
+        if (actions & ACTION_CLOSE_DEV) {
+            action_close_dev(device_obj);
+        }
+
+        actions = device_obj->actions;
+        device_obj->actions = 0;
+    }
 }
 
 void class_driver_task(void *arg)
 {
     class_driver_t driver_obj = {0};
+    usb_host_client_handle_t class_driver_client_hdl = NULL;
 
     ESP_LOGI(TAG, "Registering Client");
+
+    SemaphoreHandle_t mux_lock = xSemaphoreCreateMutex();
+    if (mux_lock == NULL) {
+        ESP_LOGE(TAG, "Unable to create class driver mutex");
+        vTaskSuspend(NULL);
+        return;
+    }
+
     usb_host_client_config_t client_config = {
         .is_synchronous = false,    //Synchronous clients currently not supported. Set this to false
         .max_num_event_msg = CLIENT_NUM_EVENT_MSG,
@@ -150,52 +218,62 @@ void class_driver_task(void *arg)
             .callback_arg = (void *) &driver_obj,
         },
     };
-    ESP_ERROR_CHECK(usb_host_client_register(&client_config, &driver_obj.client_hdl));
+    ESP_ERROR_CHECK(usb_host_client_register(&client_config, &class_driver_client_hdl));
+
+    driver_obj.constant.mux_lock = mux_lock;
+    driver_obj.constant.client_hdl = class_driver_client_hdl;
+
+    for (uint8_t i = 0; i < DEV_MAX_COUNT; i++) {
+        driver_obj.mux_protected.device[i].client_hdl = class_driver_client_hdl;
+    }
+
     s_driver_obj = &driver_obj;
 
     while (1) {
-        if (driver_obj.actions == 0) {
-            usb_host_client_handle_events(driver_obj.client_hdl, portMAX_DELAY);
-        } else {
-            if (driver_obj.actions & ACTION_OPEN_DEV) {
-                action_open_dev(&driver_obj);
+        // Driver has unhandled devices, handle all devices first
+        if (driver_obj.mux_protected.flags.unhandled_devices) {
+            xSemaphoreTake(driver_obj.constant.mux_lock, portMAX_DELAY);
+            for (uint8_t i = 0; i < DEV_MAX_COUNT; i++) {
+                if (driver_obj.mux_protected.device[i].actions) {
+                    class_driver_device_handle(&driver_obj.mux_protected.device[i]);
+                }
             }
-            if (driver_obj.actions & ACTION_GET_DEV_INFO) {
-                action_get_info(&driver_obj);
-            }
-            if (driver_obj.actions & ACTION_GET_DEV_DESC) {
-                action_get_dev_desc(&driver_obj);
-            }
-            if (driver_obj.actions & ACTION_GET_CONFIG_DESC) {
-                action_get_config_desc(&driver_obj);
-            }
-            if (driver_obj.actions & ACTION_GET_STR_DESC) {
-                action_get_str_desc(&driver_obj);
-            }
-            if (driver_obj.actions & ACTION_CLOSE_DEV) {
-                action_close_dev(&driver_obj);
-            }
-            if (driver_obj.actions & ACTION_EXIT) {
+            driver_obj.mux_protected.flags.unhandled_devices = 0;
+            xSemaphoreGive(driver_obj.constant.mux_lock);
+        } else {
+            // Driver is active, handle client events
+            if (driver_obj.mux_protected.flags.shutdown == 0) {
+                usb_host_client_handle_events(class_driver_client_hdl, portMAX_DELAY);
+            } else {
+                // Shutdown the driver
                 break;
             }
-            if (driver_obj.actions & ACTION_RECONNECT) {
-                driver_obj.actions = 0;
-            }
         }
     }
 
-    ESP_LOGI(TAG, "Deregistering Client");
-    ESP_ERROR_CHECK(usb_host_client_deregister(driver_obj.client_hdl));
+    ESP_LOGI(TAG, "Deregistering Class Client");
+    ESP_ERROR_CHECK(usb_host_client_deregister(class_driver_client_hdl));
+    if (mux_lock != NULL) {
+        vSemaphoreDelete(mux_lock);
+    }
     vTaskSuspend(NULL);
 }
 
 void class_driver_client_deregister(void)
 {
-    if (s_driver_obj->dev_hdl != NULL) {
-        s_driver_obj->actions = ACTION_CLOSE_DEV;
+    // Mark all opened devices
+    xSemaphoreTake(s_driver_obj->constant.mux_lock, portMAX_DELAY);
+    for (uint8_t i = 0; i < DEV_MAX_COUNT; i++) {
+        if (s_driver_obj->mux_protected.device[i].dev_hdl != NULL) {
+            // Mark device to close
+            s_driver_obj->mux_protected.device[i].actions |= ACTION_CLOSE_DEV;
+            // Set flag
+            s_driver_obj->mux_protected.flags.unhandled_devices = 1;
+        }
     }
-    s_driver_obj->actions |= ACTION_EXIT;
+    s_driver_obj->mux_protected.flags.shutdown = 1;
+    xSemaphoreGive(s_driver_obj->constant.mux_lock);
 
     // Unblock, exit the loop and proceed to deregister client
-    ESP_ERROR_CHECK(usb_host_client_unblock(s_driver_obj->client_hdl));
+    ESP_ERROR_CHECK(usb_host_client_unblock(s_driver_obj->constant.client_hdl));
 }
diff --git a/examples/peripherals/usb/host/usb_host_lib/main/usb_host_lib_main.c b/examples/peripherals/usb/host/usb_host_lib/main/usb_host_lib_main.c
index e6c2a8df92d..d70c92db72d 100644
--- a/examples/peripherals/usb/host/usb_host_lib/main/usb_host_lib_main.c
+++ b/examples/peripherals/usb/host/usb_host_lib/main/usb_host_lib_main.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -120,26 +120,26 @@ static void usb_host_lib_task(void *arg)
     xTaskNotifyGive(arg);
 
     bool has_clients = true;
-    bool has_devices = true;
-    while (has_clients || has_devices) {
+    bool has_devices = false;
+    while (has_clients) {
         uint32_t event_flags;
         ESP_ERROR_CHECK(usb_host_lib_handle_events(portMAX_DELAY, &event_flags));
         if (event_flags & USB_HOST_LIB_EVENT_FLAGS_NO_CLIENTS) {
-            ESP_LOGI(TAG, "No more clients");
-            has_clients = false;
+            ESP_LOGI(TAG, "Get FLAGS_NO_CLIENTS");
             if (ESP_OK == usb_host_device_free_all()) {
-                ESP_LOGI(TAG, "All devices marked as free");
+                ESP_LOGI(TAG, "All devices marked as free, no need to wait FLAGS_ALL_FREE event");
+                has_clients = false;
             } else {
-                ESP_LOGI(TAG, "Wait for the ALL FREE EVENT");
+                ESP_LOGI(TAG, "Wait for the FLAGS_ALL_FREE");
+                has_devices = true;
             }
         }
-        if (event_flags & USB_HOST_LIB_EVENT_FLAGS_ALL_FREE) {
-            ESP_LOGI(TAG, "No more devices");
-            has_devices = false;
+        if (has_devices && event_flags & USB_HOST_LIB_EVENT_FLAGS_ALL_FREE) {
+            ESP_LOGI(TAG, "Get FLAGS_ALL_FREE");
+            has_clients = false;
         }
-
     }
-    ESP_LOGI(TAG, "No more clients and devices");
+    ESP_LOGI(TAG, "No more clients and devices, uninstall USB Host library");
 
     //Uninstall the USB Host Library
     ESP_ERROR_CHECK(usb_host_uninstall());
@@ -167,7 +167,7 @@ void app_main(void)
 
     TaskHandle_t host_lib_task_hdl, class_driver_task_hdl;
 
-    //Create usb host lib task
+    // Create usb host lib task
     BaseType_t task_created;
     task_created = xTaskCreatePinnedToCore(usb_host_lib_task,
                                            "usb_host",
@@ -178,19 +178,20 @@ void app_main(void)
                                            0);
     assert(task_created == pdTRUE);
 
-    //Wait unit the USB host library is installed
+    // Wait until the USB host library is installed
     ulTaskNotifyTake(false, 1000);
 
-    //Create class driver task
+    // Create class driver task
     task_created = xTaskCreatePinnedToCore(class_driver_task,
                                            "class",
-                                           4096,
+                                           5 * 1024,
                                            NULL,
                                            CLASS_TASK_PRIORITY,
                                            &class_driver_task_hdl,
                                            0);
     assert(task_created == pdTRUE);
-    vTaskDelay(10);     //Add a short delay to let the tasks run
+    // Add a short delay to let the tasks run
+    vTaskDelay(10);
 
     while (1) {
         if (xQueueReceive(app_event_queue, &evt_queue, portMAX_DELAY)) {
@@ -198,22 +199,20 @@ void app_main(void)
                 // User pressed button
                 usb_host_lib_info_t lib_info;
                 ESP_ERROR_CHECK(usb_host_lib_info(&lib_info));
-                if (lib_info.num_devices == 0) {
-                    // End while cycle
-                    break;
-                } else {
-                    ESP_LOGW(TAG, "To shutdown example, remove all USB devices and press button again.");
-                    // Keep polling
+                if (lib_info.num_devices != 0) {
+                    ESP_LOGW(TAG, "Shutdown with attached devices.");
                 }
+                // End while cycle
+                break;
             }
         }
     }
 
-    //Deregister client
+    // Deregister client
     class_driver_client_deregister();
     vTaskDelay(10);
 
-    //Delete the tasks
+    // Delete the tasks
     vTaskDelete(class_driver_task_hdl);
     vTaskDelete(host_lib_task_hdl);
 
diff --git a/examples/peripherals/usb/host/usb_host_lib/sdkconfig.defaults b/examples/peripherals/usb/host/usb_host_lib/sdkconfig.defaults
new file mode 100644
index 00000000000..bf1b553b238
--- /dev/null
+++ b/examples/peripherals/usb/host/usb_host_lib/sdkconfig.defaults
@@ -0,0 +1,4 @@
+# This file was generated using idf.py save-defconfig. It can be edited manually.
+# Espressif IoT Development Framework (ESP-IDF) Project Minimal Configuration
+#
+CONFIG_USB_HOST_HUBS_SUPPORTED=y
diff --git a/examples/peripherals/usb/host/uvc/README.md b/examples/peripherals/usb/host/uvc/README.md
index 3fab9cf6107..eb2e4fee454 100644
--- a/examples/peripherals/usb/host/uvc/README.md
+++ b/examples/peripherals/usb/host/uvc/README.md
@@ -22,12 +22,14 @@ Optionally, the captured video can be visualized on a PC with help of the `playe
 
 ### Hardware Required
 
-* ESP with USB peripheral and external PSRAM
+* Development board with USB-OTG support and external PSRAM
 * Exposed USB host connector
 * USB camera
 
 Running this example on an **ESP module without external PSRAM will fail on initialization**. Please select your PSRAM configuration in menuconfig `Component config->ESP PSRAM`. If you manually disable PSRAM, the required framebuffers might not fit into DRAM (especially on ESP32-S2).
 
+Follow instructions in [examples/usb/README.md](../../README.md) for specific hardware setup.
+
 ### Configure the project
 
 Following configuration is needed for streaming video:
diff --git a/examples/protocols/http_server/file_serving/pytest_http_server_file_serving.py b/examples/protocols/http_server/file_serving/pytest_http_server_file_serving.py
index 66f1faa9db4..ff0c0e8ef55 100644
--- a/examples/protocols/http_server/file_serving/pytest_http_server_file_serving.py
+++ b/examples/protocols/http_server/file_serving/pytest_http_server_file_serving.py
@@ -31,11 +31,12 @@ def test_examples_protocol_http_server_file_serving(dut: Dut) -> None:
     binary_file = os.path.join(dut.app.binary_path, 'file_server.bin')
     bin_size = os.path.getsize(binary_file)
     logging.info('file_server_bin_size : {}KB'.format(bin_size // 1024))
-    logging.info('Erasing the flash on the chip')
+    logging.info('Erasing the storage partition on the chip')
+    dut.serial.erase_partition('storage')
     # Upload binary and start testing
     logging.info('Starting http file serving simple test app')
 
-    dut.expect('Initializing SPIFFS', timeout=30)
+    dut.expect('Initializing SPIFFS', timeout=60)
 
     if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True:
         dut.expect('Please input ssid password:')
diff --git a/examples/protocols/https_server/simple/pytest_https_server_simple.py b/examples/protocols/https_server/simple/pytest_https_server_simple.py
index 86aa6a3f42f..b86fafde337 100644
--- a/examples/protocols/https_server/simple/pytest_https_server_simple.py
+++ b/examples/protocols/https_server/simple/pytest_https_server_simple.py
@@ -1,8 +1,7 @@
 #!/usr/bin/env python
 #
-# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
-
 import http.client
 import logging
 import os
@@ -149,22 +148,22 @@ def test_examples_protocol_https_server_simple(dut: Dut) -> None:
         logging.info('Response obtained does not match with correct response')
         raise RuntimeError('Failed to test SSL connection')
 
-    current_cipher = dut.expect(r'Current Ciphersuite(.*)', timeout=5)[0]
-    logging.info('Current Ciphersuite {}'.format(current_cipher))
-
-    # Close the connection
-    conn.close()
+    if dut.app.sdkconfig.get('CONFIG_EXAMPLE_ENABLE_HTTPS_USER_CALLBACK') is True:
+        current_cipher = dut.expect(r'Current Ciphersuite(.*)', timeout=5)[0]
+        logging.info('Current Ciphersuite {}'.format(current_cipher))
 
-    logging.info('Checking user callback: Obtaining client certificate...')
+        logging.info('Checking user callback: Obtaining client certificate...')
 
-    serial_number = dut.expect(r'serial number\s*:([^\n]*)', timeout=5)[0]
-    issuer_name = dut.expect(r'issuer name\s*:([^\n]*)', timeout=5)[0]
-    expiry = dut.expect(r'expires on ((.*)\d{4}\-(0?[1-9]|1[012])\-(0?[1-9]|[12][0-9]|3[01])*)', timeout=5)[1].decode()
+        serial_number = dut.expect(r'serial number\s*:([^\n]*)', timeout=5)[0]
+        issuer_name = dut.expect(r'issuer name\s*:([^\n]*)', timeout=5)[0]
+        expiry = dut.expect(r'expires on ((.*)\d{4}\-(0?[1-9]|1[012])\-(0?[1-9]|[12][0-9]|3[01])*)', timeout=5)[1].decode()
 
-    logging.info('Serial No. {}'.format(serial_number))
-    logging.info('Issuer Name {}'.format(issuer_name))
-    logging.info('Expires on {}'.format(expiry))
+        logging.info('Serial No. {}'.format(serial_number))
+        logging.info('Issuer Name {}'.format(issuer_name))
+        logging.info('Expires on {}'.format(expiry))
 
+    # Close the connection
+    conn.close()
     logging.info('Correct response obtained')
     logging.info('SSL connection test successful\nClosing the connection')
 
@@ -220,21 +219,21 @@ def test_examples_protocol_https_server_simple_dynamic_buffers(dut: Dut) -> None
         logging.info('Response obtained does not match with correct response')
         raise RuntimeError('Failed to test SSL connection')
 
-    current_cipher = dut.expect(r'Current Ciphersuite(.*)', timeout=5)[0]
-    logging.info('Current Ciphersuite {}'.format(current_cipher))
+    if dut.app.sdkconfig.get('CONFIG_EXAMPLE_ENABLE_HTTPS_USER_CALLBACK') is True:
+        current_cipher = dut.expect(r'Current Ciphersuite(.*)', timeout=5)[0]
+        logging.info('Current Ciphersuite {}'.format(current_cipher))
 
-    # Close the connection
-    conn.close()
-
-    logging.info('Checking user callback: Obtaining client certificate...')
+        logging.info('Checking user callback: Obtaining client certificate...')
 
-    serial_number = dut.expect(r'serial number\s*:([^\n]*)', timeout=5)[0]
-    issuer_name = dut.expect(r'issuer name\s*:([^\n]*)', timeout=5)[0]
-    expiry = dut.expect(r'expires on\s*:((.*)\d{4}\-(0?[1-9]|1[012])\-(0?[1-9]|[12][0-9]|3[01])*)', timeout=5)[1].decode()
+        serial_number = dut.expect(r'serial number\s*:([^\n]*)', timeout=5)[0]
+        issuer_name = dut.expect(r'issuer name\s*:([^\n]*)', timeout=5)[0]
+        expiry = dut.expect(r'expires on\s*:((.*)\d{4}\-(0?[1-9]|1[012])\-(0?[1-9]|[12][0-9]|3[01])*)', timeout=5)[1].decode()
 
-    logging.info('Serial No. : {}'.format(serial_number))
-    logging.info('Issuer Name : {}'.format(issuer_name))
-    logging.info('Expires on : {}'.format(expiry))
+        logging.info('Serial No. : {}'.format(serial_number))
+        logging.info('Issuer Name : {}'.format(issuer_name))
+        logging.info('Expires on : {}'.format(expiry))
 
+    # Close the connection
+    conn.close()
     logging.info('Correct response obtained')
     logging.info('SSL connection test successful\nClosing the connection')
diff --git a/examples/protocols/https_server/simple/sdkconfig.defaults b/examples/protocols/https_server/simple/sdkconfig.defaults
index a9595bf0c1a..02e8335f9ca 100644
--- a/examples/protocols/https_server/simple/sdkconfig.defaults
+++ b/examples/protocols/https_server/simple/sdkconfig.defaults
@@ -1 +1,2 @@
 CONFIG_ESP_HTTPS_SERVER_ENABLE=y
+CONFIG_HTTPD_MAX_REQ_HDR_LEN=1024
diff --git a/examples/protocols/https_server/wss_server/sdkconfig.defaults b/examples/protocols/https_server/wss_server/sdkconfig.defaults
index 0a73bafe0cc..c4c0211210e 100644
--- a/examples/protocols/https_server/wss_server/sdkconfig.defaults
+++ b/examples/protocols/https_server/wss_server/sdkconfig.defaults
@@ -1,2 +1,3 @@
 CONFIG_ESP_HTTPS_SERVER_ENABLE=y
+CONFIG_HTTPD_MAX_REQ_HDR_LEN=1024
 CONFIG_HTTPD_WS_SUPPORT=y
diff --git a/examples/protocols/https_x509_bundle/main/https_x509_bundle_example_main.c b/examples/protocols/https_x509_bundle/main/https_x509_bundle_example_main.c
index 966aa8173e3..33e3040cf90 100644
--- a/examples/protocols/https_x509_bundle/main/https_x509_bundle_example_main.c
+++ b/examples/protocols/https_x509_bundle/main/https_x509_bundle_example_main.c
@@ -43,11 +43,24 @@
 #include "esp_tls.h"
 #include "esp_crt_bundle.h"
 
+#if CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL
+#define MAX_URLS    9
+#else
 #define MAX_URLS    2
+#endif
 
 static const char *web_urls[MAX_URLS] = {
     "https://www.howsmyssl.com/a/check",
     "https://espressif.com",
+#if CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL
+    "https://letsencrypt.org",
+    "https://www.identrust.com",
+    "https://www.globalsign.com",
+    "https://www.sectigo.com",
+    "https://www.digicert.com",
+    "https://www.godaddy.com",
+    "https://rainmaker.espressif.com",  // Amazon
+#endif
 };
 
 static const char *TAG = "example";
diff --git a/examples/protocols/https_x509_bundle/pytest_https_x509_bundle.py b/examples/protocols/https_x509_bundle/pytest_https_x509_bundle.py
index 12ef0d1f1d2..ec3f115bd81 100644
--- a/examples/protocols/https_x509_bundle/pytest_https_x509_bundle.py
+++ b/examples/protocols/https_x509_bundle/pytest_https_x509_bundle.py
@@ -1,10 +1,9 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Unlicense OR CC0-1.0
 import logging
 import os
 
 import pytest
-from common_test_methods import get_env_config_variable
 from pytest_embedded import Dut
 
 
@@ -21,17 +20,11 @@ def test_examples_protocol_https_x509_bundle(dut: Dut) -> None:
     binary_file = os.path.join(dut.app.binary_path, 'https_x509_bundle.bin')
     bin_size = os.path.getsize(binary_file)
     logging.info('https_x509_bundle_bin_size : {}KB'.format(bin_size // 1024))
-    # Connect to AP
-    if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True:
-        dut.expect('Please input ssid password:')
-        env_name = 'wifi_ap'
-        ap_ssid = get_env_config_variable(env_name, 'ap_ssid')
-        ap_password = get_env_config_variable(env_name, 'ap_password')
-        dut.write(f'{ap_ssid} {ap_password}')
     dut.expect(r'IPv4 address: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30)
     # start test
     num_URLS = int(dut.expect(r'Connecting to (\d+) URLs', timeout=30)[1].decode())
-    dut.expect(r'Connection established to ([\s\S]*)', timeout=30)
+    for _ in range(num_URLS):
+        dut.expect(r'Connection established to ([\s\S]*)', timeout=30)
     dut.expect('Completed {} connections'.format(num_URLS), timeout=60)
 
 
@@ -44,15 +37,25 @@ def test_examples_protocol_https_x509_bundle_dynamic_buffer(dut: Dut) -> None:
     binary_file = os.path.join(dut.app.binary_path, 'https_x509_bundle.bin')
     bin_size = os.path.getsize(binary_file)
     logging.info('https_x509_bundle_bin_size : {}KB'.format(bin_size // 1024))
-    # Connect to AP
-    if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True:
-        dut.expect('Please input ssid password:')
-        env_name = 'wifi_ap'
-        ap_ssid = get_env_config_variable(env_name, 'ap_ssid')
-        ap_password = get_env_config_variable(env_name, 'ap_password')
-        dut.write(f'{ap_ssid} {ap_password}')
     dut.expect(r'IPv4 address: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30)
     # start test
     num_URLS = int(dut.expect(r'Connecting to (\d+) URLs', timeout=30)[1].decode())
     dut.expect(r'Connection established to ([\s\S]*)', timeout=30)
     dut.expect('Completed {} connections'.format(num_URLS), timeout=60)
+
+
+@pytest.mark.qemu
+@pytest.mark.esp32
+@pytest.mark.host_test
+@pytest.mark.parametrize('config', ['default_crt_bundle',], indirect=True)
+def test_examples_protocol_https_x509_bundle_default_crt_bundle_stress_test(dut: Dut) -> None:
+    # check and log bin size
+    binary_file = os.path.join(dut.app.binary_path, 'https_x509_bundle.bin')
+    bin_size = os.path.getsize(binary_file)
+    logging.info('https_x509_bundle_bin_size : {}KB'.format(bin_size // 1024))
+    dut.expect(r'IPv4 address: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30)
+    # start test
+    num_URLS = int(dut.expect(r'Connecting to (\d+) URLs', timeout=30)[1].decode())
+    for _ in range(num_URLS):
+        dut.expect(r'Connection established to ([\s\S]*)', timeout=30)
+    dut.expect('Completed {} connections'.format(num_URLS), timeout=60)
diff --git a/examples/protocols/https_x509_bundle/sdkconfig.ci.default_crt_bundle b/examples/protocols/https_x509_bundle/sdkconfig.ci.default_crt_bundle
new file mode 100644
index 00000000000..d0e1451c3e3
--- /dev/null
+++ b/examples/protocols/https_x509_bundle/sdkconfig.ci.default_crt_bundle
@@ -0,0 +1,8 @@
+CONFIG_IDF_TARGET="esp32"
+CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL=y
+
+# QEMU-Related configurations
+CONFIG_EXAMPLE_CONNECT_ETHERNET=y
+CONFIG_EXAMPLE_USE_OPENETH=y
+CONFIG_EXAMPLE_CONNECT_WIFI=n
+CONFIG_ETH_USE_SPI_ETHERNET=n
diff --git a/examples/protocols/icmp_echo/main/echo_example_main.c b/examples/protocols/icmp_echo/main/echo_example_main.c
index a300757479c..67f68093d25 100644
--- a/examples/protocols/icmp_echo/main/echo_example_main.c
+++ b/examples/protocols/icmp_echo/main/echo_example_main.c
@@ -62,11 +62,16 @@ static void cmd_ping_on_ping_end(esp_ping_handle_t hdl, void *args)
     } else {
         loss = 0;
     }
+#ifdef CONFIG_LWIP_IPV4
     if (IP_IS_V4(&target_addr)) {
         printf("\n--- %s ping statistics ---\n", inet_ntoa(*ip_2_ip4(&target_addr)));
-    } else {
+    }
+#endif
+#ifdef CONFIG_LWIP_IPV6
+    if (IP_IS_V6(&target_addr)) {
         printf("\n--- %s ping statistics ---\n", inet6_ntoa(*ip_2_ip6(&target_addr)));
     }
+#endif
     printf("%" PRIu32 " packets transmitted, %" PRIu32 " received, %" PRIu32 "%% packet loss, time %" PRIu32 "ms\n",
            transmitted, received, loss, total_time_ms);
     // delete the ping sessions, so that we clean up all resources and can create a new ping session
@@ -81,6 +86,7 @@ static struct {
     struct arg_int *count;
     struct arg_int *tos;
     struct arg_int *ttl;
+    struct arg_int *interface;
     struct arg_str *host;
     struct arg_end *end;
 } ping_args;
@@ -119,6 +125,10 @@ static int do_ping_cmd(int argc, char **argv)
         config.ttl = (uint32_t)(ping_args.ttl->ival[0]);
     }
 
+    if (ping_args.interface->count > 0) {
+        config.interface = (uint32_t)(ping_args.interface->ival[0]);
+    }
+
     // parse IP address
     struct sockaddr_in6 sock_addr6;
     ip_addr_t target_addr;
@@ -136,13 +146,18 @@ static int do_ping_cmd(int argc, char **argv)
             printf("ping: unknown host %s\n", ping_args.host->sval[0]);
             return 1;
         }
+#ifdef CONFIG_LWIP_IPV4
         if (res->ai_family == AF_INET) {
             struct in_addr addr4 = ((struct sockaddr_in *) (res->ai_addr))->sin_addr;
             inet_addr_to_ip4addr(ip_2_ip4(&target_addr), &addr4);
-        } else {
+        }
+#endif
+#ifdef CONFIG_LWIP_IPV6
+        if (res->ai_family == AF_INET6) {
             struct in6_addr addr6 = ((struct sockaddr_in6 *) (res->ai_addr))->sin6_addr;
             inet6_addr_to_ip6addr(ip_2_ip6(&target_addr), &addr6);
         }
+#endif
         freeaddrinfo(res);
     }
     config.target_addr = target_addr;
@@ -169,6 +184,7 @@ static void register_ping(void)
     ping_args.count = arg_int0("c", "count", "<n>", "Stop after sending count packets");
     ping_args.tos = arg_int0("Q", "tos", "<n>", "Set Type of Service related bits in IP datagrams");
     ping_args.ttl = arg_int0("T", "ttl", "<n>", "Set Time to Live related bits in IP datagrams");
+    ping_args.interface = arg_int0("I", "interface", "<n>", "Set Interface number");
     ping_args.host = arg_str1(NULL, NULL, "<host>", "Host address");
     ping_args.end = arg_end(1);
     const esp_console_cmd_t ping_cmd = {
@@ -232,6 +248,9 @@ void app_main(void)
     /* automatic connection per menuconfig */
     ESP_ERROR_CHECK(example_connect());
 #endif
+    struct ifreq ifr;
+    ESP_ERROR_CHECK(esp_netif_get_netif_impl_name(EXAMPLE_INTERFACE, ifr.ifr_name));
+    printf("Connected on interface: %s (%d)", ifr.ifr_name, esp_netif_get_netif_impl_index(EXAMPLE_INTERFACE));
 
     /* register command `ping` */
     register_ping();
diff --git a/examples/protocols/icmp_echo/pytest_icmp_echo.py b/examples/protocols/icmp_echo/pytest_icmp_echo.py
index d9a73635e13..298e894537d 100644
--- a/examples/protocols/icmp_echo/pytest_icmp_echo.py
+++ b/examples/protocols/icmp_echo/pytest_icmp_echo.py
@@ -1,5 +1,6 @@
-# SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
+import logging
 import os
 
 import pytest
@@ -56,3 +57,33 @@ def test_protocols_icmp_echo(dut: Dut) -> None:
 )
 def test_protocols_icmp_echo_esp32c2_26mhz(dut: Dut) -> None:
     _run_test(dut)
+
+
+@pytest.mark.esp32
+@pytest.mark.wifi_router
+@pytest.mark.parametrize('config', ['ipv6_only',], indirect=True)
+def test_protocols_icmp_echo_ipv6_only(dut: Dut) -> None:
+    # Parse IP address of STA
+    logging.info('Waiting to connect with AP')
+    if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True:
+        dut.expect('Please input ssid password:')
+        env_name = 'wifi_router'
+        ap_ssid = get_env_config_variable(env_name, 'ap_ssid')
+        ap_password = get_env_config_variable(env_name, 'ap_password')
+        dut.write(f'{ap_ssid} {ap_password}')
+    # expect all 8 octets from IPv6 (assumes it's printed in the long form)
+    ipv6_r = r':'.join((r'[0-9a-fA-F]{4}',) * 8)
+    ipv6 = dut.expect(ipv6_r, timeout=30)[0].decode()
+    logging.info(f'Connected AP with IPv6={ipv6}')
+    interface_nr = dut.expect(r'Connected on interface: [a-z]{2}\d \((\d+)\)', timeout=30)[1].decode()
+
+    # ping our own address to simplify things
+    dut.write('ping -I {} {} -c 5'.format(interface_nr, ipv6))
+
+    # expect at least two packets (there could be lost packets)
+    ip = dut.expect(r'64 bytes from ([0-9a-fA-F:]+) icmp_seq=\d ttl=\d+ time=\d+ ms')[1].decode()
+    dut.expect(fr'64 bytes from {ip} icmp_seq=[2-5] ttl=\d+ time=')
+
+    dut.expect(r'5 packets transmitted, [2-5] received, \d{1,3}% packet loss')
+    dut.write('')
+    dut.expect('esp>')
diff --git a/examples/protocols/icmp_echo/sdkconfig.ci.ipv6_only b/examples/protocols/icmp_echo/sdkconfig.ci.ipv6_only
new file mode 100644
index 00000000000..4d475d3f8df
--- /dev/null
+++ b/examples/protocols/icmp_echo/sdkconfig.ci.ipv6_only
@@ -0,0 +1,6 @@
+CONFIG_IDF_TARGET="esp32"
+CONFIG_EXAMPLE_WIFI_SSID_PWD_FROM_STDIN=y
+CONFIG_EXAMPLE_CONNECT_IPV4=n
+CONFIG_EXAMPLE_CONNECT_IPV6=y
+CONFIG_LWIP_IPV4=n
+CONFIG_LWIP_IPV6=y
diff --git a/examples/protocols/mqtt/custom_outbox/sdkconfig.ci.esp32c6 b/examples/protocols/mqtt/custom_outbox/sdkconfig.ci.esp32c6
new file mode 100644
index 00000000000..1686559de40
--- /dev/null
+++ b/examples/protocols/mqtt/custom_outbox/sdkconfig.ci.esp32c6
@@ -0,0 +1 @@
+CONFIG_PARTITION_TABLE_SINGLE_APP_LARGE=y
diff --git a/examples/security/README.md b/examples/security/README.md
new file mode 100644
index 00000000000..2d9f53a4c76
--- /dev/null
+++ b/examples/security/README.md
@@ -0,0 +1,39 @@
+# Security Examples
+
+## Security Features App
+
+This example demonstrates how to enable most of the security features on the ESP32 series SoC with the help of host-based tools such as (idf.py, esptool, espsecure). The example also supports the use of QEMU emulated ESP32-C3 for testing the security features without the need for physical hardware.
+Note: Currently, this example is only supported on the ESP32-C3 SoC.
+The example demonstrates the following security features:
+* Secure Boot V2
+* Flash Encryption
+* HMAC-based NVS Encryption
+* Secure JTAG Return Material Access
+
+## Flash Encryption
+
+The Flash Encryption example for the ESP32 series SoC demonstrates how to enable and use flash encryption in Development and Release modes.
+It includes:
+* Checking the status of flash encryption and relevant eFuses.
+* Writing to and reading from encrypted flash partitions.
+* Initializing FATFS and NVS partitions, both encrypted and non-encrypted.
+* Flashing the example in different modes, with guidance on handling encrypted data.
+
+## NVS Encryption - HMAC
+
+This example demonstrates how to use NVS (Non-Volatile Storage) encryption with an HMAC-based encryption key protection scheme on Espressif SoC chips. The encryption keys are derived from an HMAC key stored in eFuse, ensuring they are not stored in flash memory. This approach eliminates the need for a separate nvs_keys partition and does not require flash encryption to be enabled.
+The steps include:
+* Generating a secure HMAC key using the host tool.
+* Burning the HMAC key into the eFuse.
+* Enabling the HMAC-based NVS encryption scheme.
+* Reading and writing to the encrypted NVS partition.
+
+## HMAC Soft JTAG
+
+The "JTAG Re-enable Example" demonstrates how to use the HMAC peripheral to securely re-enable a software-disabled JTAG interface after authentication on supported ESP32 Series SoCs. This is useful for implementing the Return Material Access (RMA) feature for a device.
+The steps include:
+* Generating a 32-byte HMAC key.
+* Burning the key to an eFuse.
+* Generating token data from the key.
+* Using commands to re-enable JTAG access.
+
diff --git a/examples/security/security_features_app/README.md b/examples/security/security_features_app/README.md
index 9272b81c227..ea48a61b256 100644
--- a/examples/security/security_features_app/README.md
+++ b/examples/security/security_features_app/README.md
@@ -1,25 +1,24 @@
 | Supported Targets | ESP32-C3 |
 | ----------------- | -------- |
 
+# Security Features Application
 
-# All Secure
-
-This example demonstrates how to enable all of the available security features on the esp32c3 target at once.
+This example demonstrates how to enable all of the available security features on the ESP32-C3 target at once.
 This example shall use combination of host based python tools and firmware for enabling all the related security eFuses.
-For simplicity the security features such as Secure Boot V2, Flash Encryption, NVS Encryption shall be enabled through host based python tools (e.g., espefuse).
+For simplicity, the security features such as Secure Boot V2, Flash Encryption, NVS Encryption shall be enabled through host based python tools (e.g., espefuse).
 Some additional security eFuses shall be enabled in the firmware.
 
 **The device that has followed all the steps mentioned below can be used for production use-cases.**
 
 > [!CAUTION]
-> The instructions in the example directly burn eFuses and once done, it cannot be reverted. Please go through the below steps carefully before executing the example. All the steps must be followed without any changes and in the exact sequence, otherwise the device may end up in an unrecoverable state.
+> The instructions in the example directly burn eFuses and once done, it cannot be reverted. Please go through the below steps carefully before executing the example. All the steps must be followed without any changes and in the exact sequence, otherwise the device may end up in an unrecoverable state. Follow the [QEMU workflow](#enable-security-features-with-help-of-qemu) if you want to test the example without the risk of bricking an actual device.
 
 ### Hardware Required
 
-* A development board with ESP32C3 SoC
+* A development board with ESP32-C3 SoC
 * A USB cable for power supply and programming
 
-**Note: The hardware is not required if you plan to run the example with help of QEMU.**
+**Note: The hardware is not required if you plan to run the example with help of [QEMU](#enable-security-features-with-help-of-qemu).**
 
 ## Pre-requisites
 
@@ -32,7 +31,7 @@ export ESPPORT=/* Serial port to which esp is connected */
 
 <details>
     <summary>Setup serial port for QEMU</summary>
-    If you are enabling eFuses on esp32c3 emulated using QEMU then we shall set the serial port as follows:
+    If you are enabling eFuses on ESP32-C3 emulated using QEMU then we shall set the serial port as follows:
 
     export ESPPORT=socket://localhost:5555
 
@@ -40,19 +39,23 @@ export ESPPORT=/* Serial port to which esp is connected */
 
 </details>
 
-**Please make sure to perform this step every time when you open a new terminal to use `esptool/espefuse` commands.**
+**Make sure to perform this step every time when you open a new terminal to use `esptool/espefuse` commands.**
 
 ### 2. Erase flash
 
 We shall erase the flash on the device to ensure a clean state.
 
-```idf.py -p $ESPPORT erase_flash```
+```
+idf.py -p $ESPPORT erase_flash
+```
 
 
 ### 3. Install esptool
 We shall require esptool utility which can be installed as follows:
 
-```pip install esptool```
+```
+pip install esptool
+```
 
 ### 4. Installing qemu (optional)
 
@@ -112,7 +115,8 @@ When the application is built (later in the workflow) the `bootloader` and `appl
 
 	```
 	espsecure.py sign_data --version 2 --keyfile 	/* Signing key placeholder */ --output bootloader-signed.bin build/bootloader/bootloader.bin
-
+	```
+	```
 	espsecure.py sign_data --version 2 --keyfile 	/* Signing key placeholder */ --output my-app-signed.bin build/security_features.bin
 	```
 
@@ -122,7 +126,7 @@ When the application is built (later in the workflow) the `bootloader` and `appl
 Details about the Flash Encryption protocol can be found at the [Flash Encryption documentation](https://docs.espressif.com/projects/esp-idf/en/stable/esp32c3/security/flash-encryption.html)
 The indicates the status of Flash Encryption feature for the chip. The example also demonstrates writing and reading encrypted partitions in flash.
 
-Please follow below steps to enable Flash Encryption:
+Follow below steps to enable Flash Encryption:
 
 1. Generate Flash Encryption keys
 
@@ -163,9 +167,11 @@ It can be done with following commands:
 
 ```
 espsecure.py encrypt_flash_data --aes_xts --keyfile my_flash_encryption_key.bin --address 0x0 --output encrypted_data/bootloader-enc.bin build/bootloader/bootloader.bin
-
+```
+```
 espsecure.py encrypt_flash_data --aes_xts --keyfile my_flash_encryption_key.bin --address 0xD000 --output encrypted_data/partition-table-enc.bin build/partition_table/partition-table.bin
-
+```
+```
 espsecure.py encrypt_flash_data --aes_xts --keyfile my_flash_encryption_key.bin --address 0x20000 --output encrypted_data/security_features-enc.bin build/security_features_app.bin
 ```
 
@@ -200,7 +206,7 @@ We shall use the [nvs_partition_gen.py](../../../components/nvs_flash/nvs_partit
 	Execute following command to generate the encrypted NVS partition.
 
 	```
-	python3 nvs_partition_gen.py encrypt /* CSV placeholder */ nvs_encr_partition.bin /* NVS partition offset */ --inputkey keys/nvs_encr_key.bin
+	python3 $IDF_PATH/components/nvs_flash/nvs_partition_generator/nvs_partition_gen.py encrypt /* CSV placeholder */ nvs_encr_partition.bin /* NVS partition offset */ --inputkey keys/nvs_encr_key.bin
 	```
 	* `CSV placeholder`: CSV file which contains data of the NVS partition. See [CSV file format](https://docs.espressif.com/projects/esp-idf/en/stable/esp32c3/api-reference/storage/nvs_partition_gen.html#csv-file-format) for more details.
 	* `NVS partition offset`: NVS partition offset. Can be found out by executing `idf.py partition-table`
@@ -463,7 +469,7 @@ A hex file containing the eFuse configuration of ESP32C3 v0.3 (ECO3) has been ke
     
     This command shall start a serial connection with QEMU. Keep this running in one terminal and execute espefuse commands in an alternate terminal.
 
-    After espefuse commands are used to update the eFuses of the emulated esp the eFuse file generated in *Step 1* shall get ovwewritten. To revert to the original state, execute the command provided in *Step 1* once again.
+    After espefuse commands are used to update the eFuses of the emulated esp the eFuse file generated in *Step 1* shall get overwritten. To revert to the original state, execute the command provided in *Step 1* once again.
 
 
 3. Execute the commands to enable security features
diff --git a/examples/storage/.build-test-rules.yml b/examples/storage/.build-test-rules.yml
index 4e7e8c66cbe..66a4e3d1c6a 100644
--- a/examples/storage/.build-test-rules.yml
+++ b/examples/storage/.build-test-rules.yml
@@ -19,29 +19,6 @@ examples/storage/emmc:
     - if: IDF_TARGET == "esp32s3"
       reason: only support on esp32s3
 
-examples/storage/ext_flash_fatfs:
-  depends_components:
-    - fatfs
-    - vfs
-    - spi_flash
-    - driver
-  disable:
-    - if: IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"]
-      temporary: true
-      reason: not supported on p4 and c5  # TODO: [ESP32C5] IDF-8715, [ESP32C61] IDF-9314
-  disable_test:
-    - if: IDF_TARGET not in ["esp32"]
-      temporary: true
-      reason: lack of runners
-
-examples/storage/fatfsgen:
-  depends_components:
-    - fatfs
-    - vfs
-  disable_test:
-    - if: IDF_TARGET != "esp32"
-      reason: only one target needed
-
 examples/storage/nvs_rw_blob:
   depends_components:
     - nvs_flash
@@ -110,12 +87,9 @@ examples/storage/perf_benchmark:
     - wear_levelling
     - esp_partition
     - esp_driver_sdmmc
-  disable:
-    - if: IDF_TARGET in ["esp32c5", "esp32c61"]
-      temporary: true
-      reason: not supported yet  # TODO: [ESP32C5] IDF-8704, IDF-10314, [ESP32C61] IDF-9314
   disable_test:
     - if: IDF_TARGET == "esp32p4" and CONFIG_NAME in ["sdmmc_1line", "sdmmc_4line", "sdspi_1line"]
+    - if: IDF_TARGET in ["esp32c61"]
       temporary: true
       reason: lack of runners, build only # TODO: IDF-8970
 
diff --git a/examples/storage/README.md b/examples/storage/README.md
index bb5c821fe89..ebfb75833d5 100644
--- a/examples/storage/README.md
+++ b/examples/storage/README.md
@@ -7,10 +7,11 @@ This directory contains a range of examples ESP-IDF projects. These are intended
 
 The examples are grouped into sub-directories by category. Each category directory contains one or more example projects:
 
+* `fatfs_basic` minimal example of FatFS usage on SPI FLASH
+* `fatfs_advanced` example demonstrates how to use advanced features for working with FatFS such as automatic partition generation
 * `custom_flash_driver` example demonstrates how to implement your own flash chip driver by overriding the default driver.
 * `emmc` example demonstrates how to use an eMMC chip with an ESP device.
 * `ext_flash_fatfs` example demonstrates how to use FATFS partition with external SPI FLASH chip.
-* `fatfsgen` example demonstrates how to use FATFS partition
 * `nvs_rw_blob` example demonstrates how to read and write a single integer value and a blob (binary large object) using NVS to preserve them between ESP module restarts.
 * `nvs_rw_value` example demonstrates how to read and write a single integer value using NVS.
 * `nvs_rw_value_cxx` example demonstrates how to read and write a single integer value using NVS (it uses the C++ NVS handle API).
diff --git a/examples/storage/ext_flash_fatfs/CMakeLists.txt b/examples/storage/ext_flash_fatfs/CMakeLists.txt
deleted file mode 100644
index 93841c0e29c..00000000000
--- a/examples/storage/ext_flash_fatfs/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# The following lines of boilerplate have to be in your project's CMakeLists
-# in this exact order for cmake to work correctly
-cmake_minimum_required(VERSION 3.16)
-
-# external SPI flash driver not currently supported for ESP32-S2
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-project(ext_flash_fatfs)
diff --git a/examples/storage/ext_flash_fatfs/README.md b/examples/storage/ext_flash_fatfs/README.md
deleted file mode 100644
index 0014bd8d314..00000000000
--- a/examples/storage/ext_flash_fatfs/README.md
+++ /dev/null
@@ -1,79 +0,0 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
-
-# FAT FS on External Flash example
-
-(See the README.md file in the upper level 'examples' directory for more information about examples.)
-
-This example is similar to the [wear levelling](../wear_levelling/README.md) example, except that it uses an external SPI Flash chip. This can be useful if you need to add more storage to a module with only 4 MB flash size.
-
-The flow of the example is as follows:
-
-1. Initialize the SPI bus and configure the pins. In this example, VSPI peripheral is used. The pins chosen in this example correspond to IOMUX pins for the VSPI peripheral. If the pin assignment is changed, SPI driver will instead connect the peripheral to the pins using the GPIO Matrix.
-
-2. Initialize the SPI flash chip. This involves creating a run-time object which describes the flash chip (`esp_flash_t`), probing the flash chip, and configuring it for the selected read mode. By default this example uses DIO mode, which only requires 4 pins (MOSI, MISO, SCLK, CS) but we strongly recommend to connect (or pull-up) the WP and HD pins. For modes such as QIO and QOUT, additional pins (WP/DQ2, HD/DQ3) must be connected.
-
-3. Register the entire area of the Flash chip as a *partition* (`esp_partition_t`). This allows other components (FATFS, SPIFFS, NVS, etc) to use the storage provided by the external flash chip.
-
-4. Do some read and write operations using C standard library functions: create a file, write to it, open it for reading, print the contents to the console.
-
-## How to use example
-
-### Hardware required
-
-This example needs an SPI NOR Flash chip connected to the ESP32. The SPI Flash chip must have 3.3V logic levels. The example has been tested with Winbond W25Q32 SPI Flash chip.
-
-Use the following pin assignments:
-
-#### Pin assignments
-
-The GPIO pin numbers used to connect an external SPI flash chip can be customized.
-
-In this example it can be done in source code by changing C defines under `Pin mapping` comment at the top of the file.
-
-The table below shows the default pin assignments.
-
-SPI bus signal | SPI Flash pin | ESP32 pin | ESP32S2 pin | ESP32S3 pin | ESP32C3 pin
----------------|---------------|-----------|-------------|-------------|-------------
-MOSI           | DI            | GPIO23    | GPIO11      | GPIO11      | GPIO7
-MISO           | DO            | GPIO19    | GPIO13      | GPIO13      | GPIO2
-SCLK           | CLK           | GPIO18    | GPIO12      | GPIO12      | GPIO6
-CS             | CMD           | GPIO5     | GPIO10      | GPIO10      | GPIO10
-WP             | WP            | GPIO22    | GPIO14      | GPIO14      | GPIO5
-HD             | HOLD          | GPIO21    | GPIO9       | GPIO9       | GPIO4
-|              | GND           | GND       | GND         | GND         | GND
-|              | VCC           | VCC       | VCC         | VCC         | VCC
-
-### Build and flash
-
-Build the project and flash it to the board, then run monitor tool to view serial output:
-
-```
-idf.py -p PORT flash monitor
-```
-
-(Replace PORT with serial port name.)
-
-(To exit the serial monitor, type ``Ctrl-]``.)
-
-See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
-
-## Example output
-
-Here is a typical example console output.
-
-```
-I (328) example: Initializing external SPI Flash
-I (338) example: Pin assignments:
-I (338) example: MOSI: 23   MISO: 19   SCLK: 18   CS:  5
-I (348) spi_flash: detected chip: generic
-I (348) spi_flash: flash io: dio
-I (348) example: Initialized external Flash, size=4096 KB, ID=0xef4016
-I (358) example: Adding external Flash as a partition, label="storage", size=4096 KB
-I (368) example: Mounting FAT filesystem
-I (378) example: FAT FS: 4024 kB total, 4020 kB free
-I (378) example: Opening file
-I (958) example: File written
-I (958) example: Reading file
-I (958) example: Read from file: 'Written using ESP-IDF v4.0-dev-1301-g0a1160468'
-```
diff --git a/examples/storage/ext_flash_fatfs/main/CMakeLists.txt b/examples/storage/ext_flash_fatfs/main/CMakeLists.txt
deleted file mode 100644
index c8a5c30e46b..00000000000
--- a/examples/storage/ext_flash_fatfs/main/CMakeLists.txt
+++ /dev/null
@@ -1 +0,0 @@
-idf_component_register(SRCS "ext_flash_fatfs_example_main.c")
diff --git a/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c b/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c
deleted file mode 100644
index aa2a2c0990b..00000000000
--- a/examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* Example of FAT filesystem on external Flash.
-   This example code is in the Public Domain (or CC0 licensed, at your option.)
-
-   Unless required by applicable law or agreed to in writing, this
-   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-   CONDITIONS OF ANY KIND, either express or implied.
-
-   This sample shows how to store files inside a FAT filesystem.
-   FAT filesystem is stored in a partition inside SPI flash, using the
-   flash wear levelling library.
-*/
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-
-#include "esp_flash.h"
-#include "esp_flash_spi_init.h"
-#include "esp_partition.h"
-#include "esp_vfs.h"
-#include "esp_vfs_fat.h"
-#include "esp_system.h"
-#include "soc/spi_pins.h"
-
-// h2 and c2 will not support external flash
-#define EXAMPLE_FLASH_FREQ_MHZ      40
-
-static const char *TAG = "example";
-
-// Pin mapping
-// ESP32 (VSPI)
-#ifdef CONFIG_IDF_TARGET_ESP32
-#define HOST_ID  SPI3_HOST
-#define PIN_MOSI SPI3_IOMUX_PIN_NUM_MOSI
-#define PIN_MISO SPI3_IOMUX_PIN_NUM_MISO
-#define PIN_CLK  SPI3_IOMUX_PIN_NUM_CLK
-#define PIN_CS   SPI3_IOMUX_PIN_NUM_CS
-#define PIN_WP   SPI3_IOMUX_PIN_NUM_WP
-#define PIN_HD   SPI3_IOMUX_PIN_NUM_HD
-#define SPI_DMA_CHAN SPI_DMA_CH_AUTO
-#else // Other chips (SPI2/HSPI)
-#define HOST_ID  SPI2_HOST
-#define PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
-#define PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
-#define PIN_CLK  SPI2_IOMUX_PIN_NUM_CLK
-#define PIN_CS   SPI2_IOMUX_PIN_NUM_CS
-#define PIN_WP   SPI2_IOMUX_PIN_NUM_WP
-#define PIN_HD   SPI2_IOMUX_PIN_NUM_HD
-#define SPI_DMA_CHAN SPI_DMA_CH_AUTO
-#endif
-
-// Handle of the wear levelling library instance
-static wl_handle_t s_wl_handle = WL_INVALID_HANDLE;
-
-// Mount path for the partition
-const char *base_path = "/extflash";
-
-static esp_flash_t* example_init_ext_flash(void);
-static const esp_partition_t* example_add_partition(esp_flash_t* ext_flash, const char* partition_label);
-static void example_list_data_partitions(void);
-static bool example_mount_fatfs(const char* partition_label);
-
-void app_main(void)
-{
-    // Set up SPI bus and initialize the external SPI Flash chip
-    esp_flash_t* flash = example_init_ext_flash();
-    if (flash == NULL) {
-        return;
-    }
-
-    // Add the entire external flash chip as a partition
-    const char *partition_label = "storage";
-    example_add_partition(flash, partition_label);
-
-    // List the available partitions
-    example_list_data_partitions();
-
-    // Initialize FAT FS in the partition
-    if (!example_mount_fatfs(partition_label)) {
-        return;
-    }
-
-    // Print FAT FS size information
-    uint64_t bytes_total, bytes_free;
-    esp_vfs_fat_info(base_path, &bytes_total, &bytes_free);
-    ESP_LOGI(TAG, "FAT FS: %" PRIu64 " kB total, %" PRIu64 " kB free", bytes_total / 1024, bytes_free / 1024);
-
-    // Create a file in FAT FS
-    ESP_LOGI(TAG, "Opening file");
-    FILE *f = fopen("/extflash/hello.txt", "wb");
-    if (f == NULL) {
-        ESP_LOGE(TAG, "Failed to open file for writing");
-        return;
-    }
-    fprintf(f, "Written using ESP-IDF %s\n", esp_get_idf_version());
-    fclose(f);
-    ESP_LOGI(TAG, "File written");
-
-    // Open file for reading
-    ESP_LOGI(TAG, "Reading file");
-    f = fopen("/extflash/hello.txt", "rb");
-    if (f == NULL) {
-        ESP_LOGE(TAG, "Failed to open file for reading");
-        return;
-    }
-    char line[128];
-    fgets(line, sizeof(line), f);
-    fclose(f);
-    // strip newline
-    char *pos = strchr(line, '\n');
-    if (pos) {
-        *pos = '\0';
-    }
-    ESP_LOGI(TAG, "Read from file: '%s'", line);
-}
-
-static esp_flash_t* example_init_ext_flash(void)
-{
-    const spi_bus_config_t bus_config = {
-        .mosi_io_num = PIN_MOSI,
-        .miso_io_num = PIN_MISO,
-        .sclk_io_num = PIN_CLK,
-        .quadhd_io_num = PIN_HD,
-        .quadwp_io_num = PIN_WP,
-    };
-
-    const esp_flash_spi_device_config_t device_config = {
-        .host_id = HOST_ID,
-        .cs_id = 0,
-        .cs_io_num = PIN_CS,
-        .io_mode = SPI_FLASH_DIO,
-        .freq_mhz = EXAMPLE_FLASH_FREQ_MHZ,
-    };
-
-    ESP_LOGI(TAG, "Initializing external SPI Flash");
-    ESP_LOGI(TAG, "Pin assignments:");
-    ESP_LOGI(TAG, "MOSI: %2d   MISO: %2d   SCLK: %2d   CS: %2d",
-        bus_config.mosi_io_num, bus_config.miso_io_num,
-        bus_config.sclk_io_num, device_config.cs_io_num
-    );
-
-    // Initialize the SPI bus
-    ESP_LOGI(TAG, "DMA CHANNEL: %d", SPI_DMA_CHAN);
-    ESP_ERROR_CHECK(spi_bus_initialize(HOST_ID, &bus_config, SPI_DMA_CHAN));
-
-    // Add device to the SPI bus
-    esp_flash_t* ext_flash;
-    ESP_ERROR_CHECK(spi_bus_add_flash_device(&ext_flash, &device_config));
-
-    // Probe the Flash chip and initialize it
-    esp_err_t err = esp_flash_init(ext_flash);
-    if (err != ESP_OK) {
-        ESP_LOGE(TAG, "Failed to initialize external Flash: %s (0x%x)", esp_err_to_name(err), err);
-        return NULL;
-    }
-
-    // Print out the ID and size
-    uint32_t id;
-    ESP_ERROR_CHECK(esp_flash_read_id(ext_flash, &id));
-    ESP_LOGI(TAG, "Initialized external Flash, size=%" PRIu32 " KB, ID=0x%" PRIx32, ext_flash->size / 1024, id);
-
-    return ext_flash;
-}
-
-static const esp_partition_t* example_add_partition(esp_flash_t* ext_flash, const char* partition_label)
-{
-    ESP_LOGI(TAG, "Adding external Flash as a partition, label=\"%s\", size=%" PRIu32 " KB", partition_label, ext_flash->size / 1024);
-    const esp_partition_t* fat_partition;
-    const size_t offset = 0;
-    ESP_ERROR_CHECK(esp_partition_register_external(ext_flash, offset, ext_flash->size, partition_label, ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, &fat_partition));
-
-    // Erase space of partition on the external flash chip
-    ESP_LOGI(TAG, "Erasing partition range, offset=%u size=%" PRIu32 " KB", offset, ext_flash->size / 1024);
-    ESP_ERROR_CHECK(esp_partition_erase_range(fat_partition, offset, ext_flash->size));
-    return fat_partition;
-}
-
-static void example_list_data_partitions(void)
-{
-    ESP_LOGI(TAG, "Listing data partitions:");
-    esp_partition_iterator_t it = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, NULL);
-
-    for (; it != NULL; it = esp_partition_next(it)) {
-        const esp_partition_t *part = esp_partition_get(it);
-        ESP_LOGI(TAG, "- partition '%s', subtype %d, offset 0x%" PRIx32 ", size %" PRIu32 " kB",
-        part->label, part->subtype, part->address, part->size / 1024);
-    }
-
-    esp_partition_iterator_release(it);
-}
-
-static bool example_mount_fatfs(const char* partition_label)
-{
-    ESP_LOGI(TAG, "Mounting FAT filesystem");
-    const esp_vfs_fat_mount_config_t mount_config = {
-            .max_files = 4,
-            .format_if_mount_failed = true,
-            .allocation_unit_size = CONFIG_WL_SECTOR_SIZE,
-            .use_one_fat = false,
-    };
-    esp_err_t err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, partition_label, &mount_config, &s_wl_handle);
-    if (err != ESP_OK) {
-        ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err));
-        return false;
-    }
-    return true;
-}
diff --git a/examples/storage/ext_flash_fatfs/pytest_ext_flash_fatfs.py b/examples/storage/ext_flash_fatfs/pytest_ext_flash_fatfs.py
deleted file mode 100644
index afe81763a3a..00000000000
--- a/examples/storage/ext_flash_fatfs/pytest_ext_flash_fatfs.py
+++ /dev/null
@@ -1,19 +0,0 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
-# SPDX-License-Identifier: Unlicense OR CC0-1.0
-
-
-import pytest
-from pytest_embedded import Dut
-
-
-@pytest.mark.esp32
-@pytest.mark.external_flash
-def test_ext_flash_fatfs(dut: Dut) -> None:
-    message_list = ('Initialized external Flash',
-                    'partition \'nvs\'',
-                    'partition \'storage\'',
-                    'File written',
-                    'Read from file: \'Written using ESP-IDF')
-
-    for msg in message_list:
-        dut.expect(msg, timeout=20)
diff --git a/examples/storage/fatfs/.build-test-rules.yml b/examples/storage/fatfs/.build-test-rules.yml
new file mode 100644
index 00000000000..4f3ae3aa16a
--- /dev/null
+++ b/examples/storage/fatfs/.build-test-rules.yml
@@ -0,0 +1,24 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+examples/storage/fatfs:
+  depends_components:
+    - fatfs
+    - vfs
+  disable_test:
+    - if: IDF_TARGET != "esp32"
+      reason: only one target needed
+
+examples/storage/fatfs/ext_flash:
+  depends_components:
+    - fatfs
+    - vfs
+    - spi_flash
+    - driver
+  disable:
+    - if: IDF_TARGET in ["esp32p4", "esp32c5", "esp32c61"]
+      temporary: true
+      reason: not supported on p4 and c5  # TODO: [ESP32C5] IDF-8715, [ESP32C61] IDF-9314
+  disable_test:
+    - if: IDF_TARGET not in ["esp32"]
+      temporary: true
+      reason: lack of runners
diff --git a/examples/storage/fatfs/ext_flash/CMakeLists.txt b/examples/storage/fatfs/ext_flash/CMakeLists.txt
new file mode 100644
index 00000000000..66233663cd7
--- /dev/null
+++ b/examples/storage/fatfs/ext_flash/CMakeLists.txt
@@ -0,0 +1,7 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+# external SPI flash driver not currently supported for ESP32-S2
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(fatfs_ext_flash)
diff --git a/examples/storage/fatfs/ext_flash/README.md b/examples/storage/fatfs/ext_flash/README.md
new file mode 100644
index 00000000000..349fd1ba3ee
--- /dev/null
+++ b/examples/storage/fatfs/ext_flash/README.md
@@ -0,0 +1,79 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
+
+# FAT FS on External Flash example
+
+(See the README.md file in the upper level 'examples' directory for more information about examples.)
+
+This example is similar to the [wear levelling](../../wear_levelling/README.md) example, except that it uses an external SPI Flash chip. This can be useful if you need to add more storage to a module with only 4 MB flash size.
+
+The flow of the example is as follows:
+
+1. Initialize the SPI bus and configure the pins. In this example, VSPI peripheral is used. The pins chosen in this example correspond to IOMUX pins for the VSPI peripheral. If the pin assignment is changed, SPI driver will instead connect the peripheral to the pins using the GPIO Matrix.
+
+2. Initialize the SPI flash chip. This involves creating a run-time object which describes the flash chip (`esp_flash_t`), probing the flash chip, and configuring it for the selected read mode. By default this example uses DIO mode, which only requires 4 pins (MOSI, MISO, SCLK, CS) but we strongly recommend to connect (or pull-up) the WP and HD pins. For modes such as QIO and QOUT, additional pins (WP/DQ2, HD/DQ3) must be connected.
+
+3. Register the entire area of the Flash chip as a *partition* (`esp_partition_t`). This allows other components (FATFS, SPIFFS, NVS, etc) to use the storage provided by the external flash chip.
+
+4. Do some read and write operations using C standard library functions: create a file, write to it, open it for reading, print the contents to the console.
+
+## How to use example
+
+### Hardware required
+
+This example needs an SPI NOR Flash chip connected to the ESP32. The SPI Flash chip must have 3.3V logic levels. The example has been tested with Winbond W25Q32 SPI Flash chip.
+
+Use the following pin assignments:
+
+#### Pin assignments
+
+The GPIO pin numbers used to connect an external SPI flash chip can be customized.
+
+In this example it can be done in source code by changing C defines under `Pin mapping` comment at the top of the file.
+
+The table below shows the default pin assignments.
+
+SPI bus signal | SPI Flash pin | ESP32 pin | ESP32S2 pin | ESP32S3 pin | ESP32C3 pin
+---------------|---------------|-----------|-------------|-------------|-------------
+MOSI           | DI            | GPIO23    | GPIO11      | GPIO11      | GPIO7
+MISO           | DO            | GPIO19    | GPIO13      | GPIO13      | GPIO2
+SCLK           | CLK           | GPIO18    | GPIO12      | GPIO12      | GPIO6
+CS             | CMD           | GPIO5     | GPIO10      | GPIO10      | GPIO10
+WP             | WP            | GPIO22    | GPIO14      | GPIO14      | GPIO5
+HD             | HOLD          | GPIO21    | GPIO9       | GPIO9       | GPIO4
+|              | GND           | GND       | GND         | GND         | GND
+|              | VCC           | VCC       | VCC         | VCC         | VCC
+
+### Build and flash
+
+Build the project and flash it to the board, then run monitor tool to view serial output:
+
+```
+idf.py -p PORT flash monitor
+```
+
+(Replace PORT with serial port name.)
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
+
+## Example output
+
+Here is a typical example console output.
+
+```
+I (328) example: Initializing external SPI Flash
+I (338) example: Pin assignments:
+I (338) example: MOSI: 23   MISO: 19   SCLK: 18   CS:  5
+I (348) spi_flash: detected chip: generic
+I (348) spi_flash: flash io: dio
+I (348) example: Initialized external Flash, size=4096 KB, ID=0xef4016
+I (358) example: Adding external Flash as a partition, label="storage", size=4096 KB
+I (368) example: Mounting FAT filesystem
+I (378) example: FAT FS: 4024 kB total, 4020 kB free
+I (378) example: Opening file
+I (958) example: File written
+I (958) example: Reading file
+I (958) example: Read from file: 'Written using ESP-IDF v4.0-dev-1301-g0a1160468'
+```
diff --git a/examples/storage/fatfs/ext_flash/main/CMakeLists.txt b/examples/storage/fatfs/ext_flash/main/CMakeLists.txt
new file mode 100644
index 00000000000..dea52d1cb4a
--- /dev/null
+++ b/examples/storage/fatfs/ext_flash/main/CMakeLists.txt
@@ -0,0 +1 @@
+idf_component_register(SRCS "fatfs_ext_flash_example_main.c")
diff --git a/examples/storage/fatfs/ext_flash/main/fatfs_ext_flash_example_main.c b/examples/storage/fatfs/ext_flash/main/fatfs_ext_flash_example_main.c
new file mode 100644
index 00000000000..4e10057d10f
--- /dev/null
+++ b/examples/storage/fatfs/ext_flash/main/fatfs_ext_flash_example_main.c
@@ -0,0 +1,212 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+/* Example of FAT filesystem on external Flash.
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+
+   This sample shows how to store files inside a FAT filesystem.
+   FAT filesystem is stored in a partition inside SPI flash, using the
+   flash wear levelling library.
+*/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "esp_flash.h"
+#include "esp_flash_spi_init.h"
+#include "esp_partition.h"
+#include "esp_vfs.h"
+#include "esp_vfs_fat.h"
+#include "esp_system.h"
+#include "soc/spi_pins.h"
+
+// h2 and c2 will not support external flash
+#define EXAMPLE_FLASH_FREQ_MHZ      40
+
+static const char *TAG = "example";
+
+// Pin mapping
+// ESP32 (VSPI)
+#ifdef CONFIG_IDF_TARGET_ESP32
+#define HOST_ID  SPI3_HOST
+#define PIN_MOSI SPI3_IOMUX_PIN_NUM_MOSI
+#define PIN_MISO SPI3_IOMUX_PIN_NUM_MISO
+#define PIN_CLK  SPI3_IOMUX_PIN_NUM_CLK
+#define PIN_CS   SPI3_IOMUX_PIN_NUM_CS
+#define PIN_WP   SPI3_IOMUX_PIN_NUM_WP
+#define PIN_HD   SPI3_IOMUX_PIN_NUM_HD
+#define SPI_DMA_CHAN SPI_DMA_CH_AUTO
+#else // Other chips (SPI2/HSPI)
+#define HOST_ID  SPI2_HOST
+#define PIN_MOSI SPI2_IOMUX_PIN_NUM_MOSI
+#define PIN_MISO SPI2_IOMUX_PIN_NUM_MISO
+#define PIN_CLK  SPI2_IOMUX_PIN_NUM_CLK
+#define PIN_CS   SPI2_IOMUX_PIN_NUM_CS
+#define PIN_WP   SPI2_IOMUX_PIN_NUM_WP
+#define PIN_HD   SPI2_IOMUX_PIN_NUM_HD
+#define SPI_DMA_CHAN SPI_DMA_CH_AUTO
+#endif
+
+// Handle of the wear levelling library instance
+static wl_handle_t s_wl_handle = WL_INVALID_HANDLE;
+
+// Mount path for the partition
+const char *base_path = "/extflash";
+
+static esp_flash_t* example_init_ext_flash(void);
+static const esp_partition_t* example_add_partition(esp_flash_t* ext_flash, const char* partition_label);
+static void example_list_data_partitions(void);
+static bool example_mount_fatfs(const char* partition_label);
+
+void app_main(void)
+{
+    // Set up SPI bus and initialize the external SPI Flash chip
+    esp_flash_t* flash = example_init_ext_flash();
+    if (flash == NULL) {
+        return;
+    }
+
+    // Add the entire external flash chip as a partition
+    const char *partition_label = "storage";
+    example_add_partition(flash, partition_label);
+
+    // List the available partitions
+    example_list_data_partitions();
+
+    // Initialize FAT FS in the partition
+    if (!example_mount_fatfs(partition_label)) {
+        return;
+    }
+
+    // Print FAT FS size information
+    uint64_t bytes_total, bytes_free;
+    esp_vfs_fat_info(base_path, &bytes_total, &bytes_free);
+    ESP_LOGI(TAG, "FAT FS: %" PRIu64 " kB total, %" PRIu64 " kB free", bytes_total / 1024, bytes_free / 1024);
+
+    // Create a file in FAT FS
+    ESP_LOGI(TAG, "Opening file");
+    FILE *f = fopen("/extflash/hello.txt", "wb");
+    if (f == NULL) {
+        ESP_LOGE(TAG, "Failed to open file for writing");
+        return;
+    }
+    fprintf(f, "Written using ESP-IDF %s\n", esp_get_idf_version());
+    fclose(f);
+    ESP_LOGI(TAG, "File written");
+
+    // Open file for reading
+    ESP_LOGI(TAG, "Reading file");
+    f = fopen("/extflash/hello.txt", "rb");
+    if (f == NULL) {
+        ESP_LOGE(TAG, "Failed to open file for reading");
+        return;
+    }
+    char line[128];
+    fgets(line, sizeof(line), f);
+    fclose(f);
+    // strip newline
+    char *pos = strchr(line, '\n');
+    if (pos) {
+        *pos = '\0';
+    }
+    ESP_LOGI(TAG, "Read from file: '%s'", line);
+}
+
+static esp_flash_t* example_init_ext_flash(void)
+{
+    const spi_bus_config_t bus_config = {
+        .mosi_io_num = PIN_MOSI,
+        .miso_io_num = PIN_MISO,
+        .sclk_io_num = PIN_CLK,
+        .quadhd_io_num = PIN_HD,
+        .quadwp_io_num = PIN_WP,
+    };
+
+    const esp_flash_spi_device_config_t device_config = {
+        .host_id = HOST_ID,
+        .cs_id = 0,
+        .cs_io_num = PIN_CS,
+        .io_mode = SPI_FLASH_DIO,
+        .freq_mhz = EXAMPLE_FLASH_FREQ_MHZ,
+    };
+
+    ESP_LOGI(TAG, "Initializing external SPI Flash");
+    ESP_LOGI(TAG, "Pin assignments:");
+    ESP_LOGI(TAG, "MOSI: %2d   MISO: %2d   SCLK: %2d   CS: %2d",
+        bus_config.mosi_io_num, bus_config.miso_io_num,
+        bus_config.sclk_io_num, device_config.cs_io_num
+    );
+
+    // Initialize the SPI bus
+    ESP_LOGI(TAG, "DMA CHANNEL: %d", SPI_DMA_CHAN);
+    ESP_ERROR_CHECK(spi_bus_initialize(HOST_ID, &bus_config, SPI_DMA_CHAN));
+
+    // Add device to the SPI bus
+    esp_flash_t* ext_flash;
+    ESP_ERROR_CHECK(spi_bus_add_flash_device(&ext_flash, &device_config));
+
+    // Probe the Flash chip and initialize it
+    esp_err_t err = esp_flash_init(ext_flash);
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Failed to initialize external Flash: %s (0x%x)", esp_err_to_name(err), err);
+        return NULL;
+    }
+
+    // Print out the ID and size
+    uint32_t id;
+    ESP_ERROR_CHECK(esp_flash_read_id(ext_flash, &id));
+    ESP_LOGI(TAG, "Initialized external Flash, size=%" PRIu32 " KB, ID=0x%" PRIx32, ext_flash->size / 1024, id);
+
+    return ext_flash;
+}
+
+static const esp_partition_t* example_add_partition(esp_flash_t* ext_flash, const char* partition_label)
+{
+    ESP_LOGI(TAG, "Adding external Flash as a partition, label=\"%s\", size=%" PRIu32 " KB", partition_label, ext_flash->size / 1024);
+    const esp_partition_t* fat_partition;
+    const size_t offset = 0;
+    ESP_ERROR_CHECK(esp_partition_register_external(ext_flash, offset, ext_flash->size, partition_label, ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, &fat_partition));
+
+    // Erase space of partition on the external flash chip
+    ESP_LOGI(TAG, "Erasing partition range, offset=%u size=%" PRIu32 " KB", offset, ext_flash->size / 1024);
+    ESP_ERROR_CHECK(esp_partition_erase_range(fat_partition, offset, ext_flash->size));
+    return fat_partition;
+}
+
+static void example_list_data_partitions(void)
+{
+    ESP_LOGI(TAG, "Listing data partitions:");
+    esp_partition_iterator_t it = esp_partition_find(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, NULL);
+
+    for (; it != NULL; it = esp_partition_next(it)) {
+        const esp_partition_t *part = esp_partition_get(it);
+        ESP_LOGI(TAG, "- partition '%s', subtype %d, offset 0x%" PRIx32 ", size %" PRIu32 " kB",
+        part->label, part->subtype, part->address, part->size / 1024);
+    }
+
+    esp_partition_iterator_release(it);
+}
+
+static bool example_mount_fatfs(const char* partition_label)
+{
+    ESP_LOGI(TAG, "Mounting FAT filesystem");
+    const esp_vfs_fat_mount_config_t mount_config = {
+            .max_files = 4,
+            .format_if_mount_failed = true,
+            .allocation_unit_size = CONFIG_WL_SECTOR_SIZE,
+            .use_one_fat = false,
+    };
+    esp_err_t err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, partition_label, &mount_config, &s_wl_handle);
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err));
+        return false;
+    }
+    return true;
+}
diff --git a/examples/storage/fatfs/ext_flash/pytest_fatfs_ext_flash.py b/examples/storage/fatfs/ext_flash/pytest_fatfs_ext_flash.py
new file mode 100644
index 00000000000..56dd334a49a
--- /dev/null
+++ b/examples/storage/fatfs/ext_flash/pytest_fatfs_ext_flash.py
@@ -0,0 +1,17 @@
+# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32
+@pytest.mark.external_flash
+def test_ext_flash_fatfs(dut: Dut) -> None:
+    message_list = ('Initialized external Flash',
+                    'partition \'nvs\'',
+                    'partition \'storage\'',
+                    'File written',
+                    'Read from file: \'Written using ESP-IDF')
+
+    for msg in message_list:
+        dut.expect(msg, timeout=20)
diff --git a/examples/storage/fatfs/fatfsgen/CMakeLists.txt b/examples/storage/fatfs/fatfsgen/CMakeLists.txt
new file mode 100644
index 00000000000..0399bf40c59
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/CMakeLists.txt
@@ -0,0 +1,6 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(fatfs_fatfsgen)
diff --git a/examples/storage/fatfs/fatfsgen/README.md b/examples/storage/fatfs/fatfsgen/README.md
new file mode 100644
index 00000000000..772cf9cd8e8
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/README.md
@@ -0,0 +1,69 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+
+# FATFS partition generation example
+
+(See the README.md file in the upper level 'examples' directory for more information about examples.)
+
+This example demonstrates how to use the FATFS partition
+generation tool [fatfsgen.py](../../../../components/fatfs/fatfsgen.py) to automatically create a FATFS
+filesystem image from the contents of a host folder during build, with an option of
+automatically flashing the created image on invocation of `idf.py -p PORT flash`.
+Beware that the minimal required size of the flash is 4 MB.
+You can specify using menuconfig weather example will use read-only or read-write mode. The default option is read-write mode.
+To change it just use menuconfig:
+
+```shell
+idf.py menuconfig
+```
+
+Then select `Example Configuration` a chose `Mode for generated FATFS image` either `Read-Write Mode` or `Read-Only Mode`.
+`Read-Only` option indicates generating raw fatfs image without wear levelling support.
+On the other hand, for `Read-Write` the generated fatfs image will support wear levelling thus can be mounted in read-write mode.
+
+
+The following gives an overview of the example:
+
+1. There is a directory `fatfs_long_name_image` from which the FATFS filesystem image will be created.
+
+2. Based on the RO/RW configuration either `fatfs_create_rawflash_image` or `fatfs_create_spiflash_image` respectively,
+is used to specify that a FATFS image should be created during build for the `storage` partition.
+For CMake, it is called from [the main component's CMakeLists.txt](./main/CMakeLists.txt).
+`FLASH_IN_PROJECT` specifies that the created image
+should be flashed on invocation of `idf.py -p PORT flash` together with app, bootloader, partition table, etc.
+The image is created on the example's build directory with the output filename `storage.bin`.
+
+3. Upon invocation of `idf.py -p PORT flash monitor`, application loads and
+finds there is already a valid FATFS filesystem in the `storage` partition with files same as those in `fatfs_image` directory. The application is then
+able to read those files.
+
+## How to use example
+
+### Build and flash
+
+To run the example, type the following command:
+
+```CMake
+# CMake
+idf.py -p PORT flash monitor
+```
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
+
+## Example output
+
+Here is the example's console output:
+
+```
+...
+I (322) example: Mounting FAT filesystem
+I (332) example: Reading file
+I (332) example: Read from file: 'this is test'
+I (332) example: Unmounting FAT filesystem
+I (342) example: Done
+```
+
+The logic of the example is contained in a [single source file](./main/fatfsgen_example_main.c),
+and it should be relatively simple to match points in its execution with the log outputs above.
diff --git a/examples/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt b/examples/storage/fatfs/fatfsgen/fatfs_image/hellolongname.txt
similarity index 100%
rename from examples/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt
rename to examples/storage/fatfs/fatfsgen/fatfs_image/hellolongname.txt
diff --git a/examples/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt b/examples/storage/fatfs/fatfsgen/fatfs_image/subdir/testlongfilenames.txt
similarity index 100%
rename from examples/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt
rename to examples/storage/fatfs/fatfsgen/fatfs_image/subdir/testlongfilenames.txt
diff --git a/examples/storage/fatfs/fatfsgen/main/CMakeLists.txt b/examples/storage/fatfs/fatfsgen/main/CMakeLists.txt
new file mode 100644
index 00000000000..1b625a37226
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/main/CMakeLists.txt
@@ -0,0 +1,18 @@
+idf_component_register(SRCS "fatfsgen_example_main.c"
+                    INCLUDE_DIRS ".")
+
+# Create a FATFS image from the contents of the 'fatfs_long_name_image' directory
+# that fits the partition named 'storage'. FLASH_IN_PROJECT indicates that
+# the generated image should be flashed when the entire project is flashed to
+# the target with 'idf.py -p PORT flash'.
+# If read-only mode is set (CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY)
+# the generated image will be raw without wear levelling support.
+# Otherwise it will support wear levelling and thus enable read-write mounting of the image in the device.
+
+set(image ../fatfs_image)
+
+if(CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY)
+    fatfs_create_rawflash_image(storage ${image} FLASH_IN_PROJECT PRESERVE_TIME)
+else()
+    fatfs_create_spiflash_image(storage ${image} FLASH_IN_PROJECT PRESERVE_TIME)
+endif()
diff --git a/examples/storage/fatfs/fatfsgen/main/Kconfig.projbuild b/examples/storage/fatfs/fatfsgen/main/Kconfig.projbuild
new file mode 100644
index 00000000000..ef79d394562
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/main/Kconfig.projbuild
@@ -0,0 +1,10 @@
+menu "Example Configuration"
+
+    config EXAMPLE_FATFS_MODE_READ_ONLY
+        bool "Read only mode for generated FATFS image"
+        default y
+        help
+            If read-only mode is set, the generated fatfs image will be raw (without wear levelling support).
+            Otherwise it will support wear levelling that enables read-write mounting.
+
+endmenu
diff --git a/examples/storage/fatfs/fatfsgen/main/fatfsgen_example_main.c b/examples/storage/fatfs/fatfsgen/main/fatfsgen_example_main.c
new file mode 100644
index 00000000000..abc01a900a8
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/main/fatfsgen_example_main.c
@@ -0,0 +1,92 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "esp_vfs.h"
+#include "esp_vfs_fat.h"
+#include "esp_err.h"
+#include "sdkconfig.h"
+
+static const char *TAG = "example";
+
+// Mount path for the partition
+const char *base_path = "/spiflash";
+
+
+void app_main(void)
+{
+    // To mount device we need name of device partition, define base_path
+    // and allow format partition in case if it is new one and was not formatted before
+    const esp_vfs_fat_mount_config_t mount_config = {
+            .max_files = 4,
+            .format_if_mount_failed = false,
+            .allocation_unit_size = CONFIG_WL_SECTOR_SIZE,
+            .use_one_fat = false,
+    };
+
+#if CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY
+    ESP_LOGI(TAG, "Mounting FAT filesystem in read-only mode");
+    esp_err_t err = esp_vfs_fat_spiflash_mount_ro(base_path, "storage", &mount_config);
+#else
+    ESP_LOGI(TAG, "Mounting FAT filesystem in read/write mode");
+    static wl_handle_t wl_handle = WL_INVALID_HANDLE;
+    esp_err_t err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &wl_handle);
+#endif
+
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err));
+        return;
+    }
+
+    char line[128];
+
+    FILE *f;
+    char *pos;
+    ESP_LOGI(TAG, "Reading file");
+
+    const char *host_filename1 = "/spiflash/subdir/testlongfilenames.txt";
+
+    struct stat info;
+    struct tm timeinfo;
+    char buffer[32];
+
+    if(stat(host_filename1, &info) < 0){
+        ESP_LOGE(TAG, "Failed to read file stats");
+        return;
+    }
+    localtime_r(&info.st_mtime, &timeinfo);
+    strftime(buffer, sizeof(buffer), "%Y-%m-%d", &timeinfo);
+
+    ESP_LOGI(TAG, "The file '%s' was modified at date: %s", host_filename1, buffer);
+
+
+    f = fopen(host_filename1, "rb");
+    if (f == NULL) {
+        ESP_LOGE(TAG, "Failed to open file for reading");
+        return;
+    }
+    fgets(line, sizeof(line), f);
+    fclose(f);
+    // strip newline
+    pos = strchr(line, '\n');
+    if (pos) {
+        *pos = '\0';
+    }
+    ESP_LOGI(TAG, "Read from file: '%s'", line);
+
+    // Unmount FATFS
+    ESP_LOGI(TAG, "Unmounting FAT filesystem");
+
+#if CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY
+    ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_ro(base_path, "storage"));
+#else
+    ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_rw_wl(base_path, wl_handle));
+#endif
+
+    ESP_LOGI(TAG, "Done");
+}
diff --git a/examples/storage/fatfs/fatfsgen/partitions_example.csv b/examples/storage/fatfs/fatfsgen/partitions_example.csv
new file mode 100644
index 00000000000..a3fee302e29
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/partitions_example.csv
@@ -0,0 +1,6 @@
+# Name,   Type, SubType, Offset,  Size,    Flags
+# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
+nvs,      data, nvs,     0x9000,  0x6000,
+phy_init, data, phy,     0xf000,  0x1000,
+factory,  app,  factory, 0x10000, 1M,
+storage,  data, fat,     ,        1M,
diff --git a/examples/storage/fatfs/fatfsgen/pytest_fatfs_fatfsgen_example.py b/examples/storage/fatfs/fatfsgen/pytest_fatfs_fatfsgen_example.py
new file mode 100644
index 00000000000..e0966604ebe
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/pytest_fatfs_fatfsgen_example.py
@@ -0,0 +1,72 @@
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import os
+import re
+from datetime import datetime
+from typing import List
+
+import pytest
+from pytest_embedded import Dut
+
+idf_path = os.environ['IDF_PATH']  # get value of IDF_PATH from environment
+parttool_dir = os.path.join(idf_path, 'components', 'partition_table')
+
+
+@pytest.mark.esp32
+@pytest.mark.generic
+@pytest.mark.parametrize('config', ['test_read_only_partition_gen_ln',
+                                    'test_read_write_partition_gen_ln',
+                                    ], indirect=True)
+def test_examples_fatfs_fatfsgen(config: str, dut: Dut) -> None:
+    # Expects list of strings sequentially
+    def expect_all(msg_list: List[str], to: int) -> None:
+        for msg in msg_list:
+            dut.expect(msg, timeout=to)
+
+    # Expects prefix string followed by date in the format 'yyyy-mm-dd'
+    def expect_date(prefix: str, to: int) -> datetime:
+        expect_str = prefix + '(\\d+)-(\\d+)-(\\d+)'
+        match_ = dut.expect(re.compile(str.encode(expect_str)), timeout=to)
+        year_ = int(match_[1].decode())
+        month_ = int(match_[2].decode())
+        day_ = int(match_[3].decode())
+        return datetime(year_, month_, day_)
+
+    # Calculates absolute difference in days between date_reference and date_actual.
+    # Raises exception if difference exceeds tolerance
+    def evaluate_dates(date_reference: datetime, date_actual: datetime, days_tolerance: int) -> None:
+        td = date_actual - date_reference
+        if abs(td.days) > days_tolerance:
+            raise Exception(f'Too big date difference. Actual: {date_actual}, reference: {date_reference}, tolerance: {days_tolerance} day(s)')
+
+    # Expect timeout
+    timeout = 20
+
+    # We tolerate 30 days difference between actual file creation and date when test was executed.
+    tolerance = 30
+    filename = 'sublongnames/testlongfilenames.txt'
+    date_ref = datetime.today()
+
+    if config in ['test_read_write_partition_gen']:
+        filename_expected = f'/spiflash/{filename}'
+        expect_all(['example: Mounting FAT filesystem',
+                    'example: Opening file',
+                    'example: File written',
+                    'example: Reading file',
+                    'example: Read from file: \'This is written by the device\'',
+                    'example: Reading file'], timeout)
+        date_act = expect_date(f'The file \'{filename_expected}\' was modified at date: ', timeout)
+        evaluate_dates(date_ref, date_act, tolerance)
+        expect_all(['example: Read from file: \'This is generated on the host\'',
+                    'example: Unmounting FAT filesystem',
+                    'example: Done'], timeout)
+
+    elif config in ['test_read_only_partition_gen']:
+        filename_expected = f'/spiflash/{filename}'
+        expect_all(['example: Mounting FAT filesystem',
+                    'example: Reading file'], timeout)
+        date_act = expect_date(f'The file \'{filename_expected}\' was modified at date: ', timeout)
+        evaluate_dates(date_ref, date_act, tolerance)
+        expect_all(['example: Read from file: \'this is test\'',
+                    'example: Unmounting FAT filesystem',
+                    'example: Done'], timeout)
diff --git a/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln b/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln
new file mode 100644
index 00000000000..5122126dcbc
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=y
+CONFIG_FATFS_LFN_HEAP=y
+CONFIG_FATFS_LFN_NONE=n
+CONFIG_FATFS_LFN_STACK=n
diff --git a/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln b/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln
new file mode 100644
index 00000000000..33a0ccfad3d
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln
@@ -0,0 +1,4 @@
+CONFIG_EXAMPLE_FATFS_MODE_READ_ONLY=n
+CONFIG_FATFS_LFN_HEAP=y
+CONFIG_FATFS_LFN_NONE=n
+CONFIG_FATFS_LFN_STACK=n
diff --git a/examples/storage/fatfs/fatfsgen/sdkconfig.defaults b/examples/storage/fatfs/fatfsgen/sdkconfig.defaults
new file mode 100644
index 00000000000..7dd3c63608f
--- /dev/null
+++ b/examples/storage/fatfs/fatfsgen/sdkconfig.defaults
@@ -0,0 +1,4 @@
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_example.csv"
+CONFIG_FATFS_LFN_HEAP=y
diff --git a/examples/storage/fatfs/fs_operations/CMakeLists.txt b/examples/storage/fatfs/fs_operations/CMakeLists.txt
new file mode 100644
index 00000000000..2f478de10dd
--- /dev/null
+++ b/examples/storage/fatfs/fs_operations/CMakeLists.txt
@@ -0,0 +1,6 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(fatfs_fs_operations)
diff --git a/examples/storage/fatfs/fs_operations/README.md b/examples/storage/fatfs/fs_operations/README.md
new file mode 100644
index 00000000000..e11f3077b50
--- /dev/null
+++ b/examples/storage/fatfs/fs_operations/README.md
@@ -0,0 +1,94 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+
+# FATFS Filesystem Operations Example
+
+(See the README.md file in the upper level 'examples' directory for more information about examples.)
+
+This example demonstrates some of the POSIX functions available for working with the FATFS filesystem.
+Including basic read and write operations, as well as creating moving, and deleting files and directories.
+
+## Overview
+
+1. Partition labeled `storage` is mounted (and formatted if necessary) as FATFS filesystem to `/spiflash` mountpoint.
+
+2. All existing files and directories in the root directory are deleted.
+
+3. File `hello.txt` is created and written to.
+
+4. File `hello.txt` is inspected using `fstat` function showing file size and last modification time.
+
+5. File `hello.txt` is written to again, appending to the end of the file.
+
+6. File `hello.txt` is read from and the contents are printed to the console.
+
+7. New directory `new_dir` is created.
+
+8. All files and directories in the root directory are listed.
+
+9. File `hello.txt` is moved and renamed to `new_dir/hello_renamed.txt`.
+
+## How to use example
+
+### Build and flash
+
+To run the example, type the following command:
+
+```CMake
+# CMake
+idf.py -p PORT flash monitor
+```
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
+
+## Example output
+
+Here is the example's console output:
+
+```
+...
+I (323) example: Mounting FAT filesystem
+I (333) example: Deleting everything in /spiflash:
+I (333) example: Deleting everything in /spiflash/new_dir:
+I (673) example: Creating a file
+I (683) example: Writing to the file
+I (733) example: File stats:
+	File size:                13 bytes
+	File modification time:   Thu Jan  1 00:00:00 1970
+
+I (743) example: Wait for 1 seconds
+I (1743) example: Write more to the file
+I (1743) example: File stats:
+	File size:                26 bytes
+	File modification time:   Thu Jan  1 00:00:00 1970
+
+I (1743) example: Go to the beginning of the file
+I (1753) example: Reading from file:
+Hello World!
+Hello World!
+
+I (1753) example: Closing file
+I (1993) example: Listing files in /spiflash:
+/spiflash:
+    file     : hello.txt
+I (1993) example: Creating a new directory
+I (2383) example: Listing files in /spiflash:
+/spiflash:
+    file     : hello.txt
+    directory: new_dir
+I (2383) example: Rename a file
+I (2503) example: Listing files in /spiflash:
+/spiflash:
+    directory: new_dir
+I (2503) example: Listing files in /spiflash/new_dir:
+/spiflash/new_dir:
+    file     : hello_renamed.txt
+I (2513) example: Unmounting FAT filesystem
+I (2643) example: Done
+...
+```
+
+The logic of the example is contained in a [single source file](./main/fatfs_fs_operations_example_main.c),
+and it should be relatively simple to match points in its execution with the log outputs above.
diff --git a/examples/storage/fatfs/fs_operations/main/CMakeLists.txt b/examples/storage/fatfs/fs_operations/main/CMakeLists.txt
new file mode 100644
index 00000000000..a5ae965fc4c
--- /dev/null
+++ b/examples/storage/fatfs/fs_operations/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "fatfs_fs_operations_example_main.c"
+                    INCLUDE_DIRS ".")
diff --git a/examples/storage/fatfs/fs_operations/main/fatfs_fs_operations_example_main.c b/examples/storage/fatfs/fs_operations/main/fatfs_fs_operations_example_main.c
new file mode 100644
index 00000000000..c2dd5bc226a
--- /dev/null
+++ b/examples/storage/fatfs/fs_operations/main/fatfs_fs_operations_example_main.c
@@ -0,0 +1,207 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include <string.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <dirent.h>
+#include <time.h>
+#include <sys/stat.h>
+#include <sys/errno.h>
+#include "esp_vfs.h"
+#include "esp_vfs_fat.h"
+#include "sdkconfig.h"
+
+static const char *TAG = "example";
+
+// Mount path for the partition
+static const char *base_path = "/spiflash";
+
+// File name
+static const char *filename = "/spiflash/hello.txt";
+
+// Function to dump contents of a directory
+static void list_dir(const char *path);
+
+// Best effort recursive function to clean a directory
+static void clean_dir(const char *path);
+
+void app_main(void)
+{
+    ESP_LOGI(TAG, "Mounting FAT filesystem");
+
+    // To mount device we need name of device partition, define base_path
+    // and allow format partition in case if it is new one and was not formatted before
+    const esp_vfs_fat_mount_config_t mount_config = {
+            .max_files = 4,
+            .format_if_mount_failed = true,
+            .allocation_unit_size = CONFIG_WL_SECTOR_SIZE,
+            .use_one_fat = false,
+    };
+
+    wl_handle_t wl_handle = WL_INVALID_HANDLE;
+
+    esp_err_t err = ESP_OK;
+
+    err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &wl_handle);
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err));
+        return;
+    }
+
+    // Ensure the working directory is empty
+    clean_dir(base_path);
+
+    ESP_LOGI(TAG, "Creating a file");
+
+    // Unlike C standard library which uses FILE*, POSIX API uses file descriptors for file operations
+    int fd = open(filename, O_RDWR | O_CREAT | O_TRUNC, 0);
+    if (fd < 0) {
+        ESP_LOGE(TAG, "Failed to open file for writing");
+        return;
+    }
+
+    ESP_LOGI(TAG, "Writing to the file");
+    const char *text = "Hello World!\n";
+    write(fd, text, strlen(text));
+
+    struct stat info;
+    // We have to use `stat` instead of `fstat`, because `fstat` currently isn't fully supported
+    if (stat(filename, &info) < 0) {
+        ESP_LOGE(TAG, "Failed to stat file: %s", strerror(errno));
+        close(fd);
+        return;
+    }
+
+    ESP_LOGI(
+        TAG,
+        "File stats:\n"
+        "\tFile size:                %ld bytes\n"
+        "\tFile modification time:   %s",
+        info.st_size,
+        ctime(&info.st_mtime)
+    );
+
+    ESP_LOGI(TAG, "Wait for 3 seconds");
+    sleep(3);
+
+    ESP_LOGI(TAG, "Write more to the file");
+    write(fd, text, strlen(text));
+
+    ESP_LOGI(TAG, "Force cached data and metadata to the filesystem");
+    fsync(fd);
+
+    if (stat(filename, &info) < 0) {
+        ESP_LOGE(TAG, "Failed to stat file: %s", strerror(errno));
+        close(fd);
+        return;
+    }
+
+    ESP_LOGI(
+        TAG,
+        "File stats:\n"
+        "\tFile size:                %ld bytes\n"
+        "\tFile modification time:   %s",
+        info.st_size,
+        ctime(&info.st_mtime)
+    );
+
+    ESP_LOGI(TAG, "Go to the beginning of the file");
+    lseek(fd, 0, SEEK_SET);
+
+    ESP_LOGI(TAG, "Reading from file:");
+
+    char buf[128] = {0};
+
+    ssize_t len = read(fd, buf, sizeof(buf) - 1);
+    if (len < 0) {
+        ESP_LOGE(TAG, "Failed to read file: %s", strerror(errno));
+        close(fd);
+        return;
+    }
+
+    printf("%.*s\n", len, buf);
+
+    ESP_LOGI(TAG, "Closing file");
+    close(fd);
+
+    // List files in the directory
+    list_dir(base_path);
+
+    ESP_LOGI(TAG, "Creating a new directory");
+    if (mkdir("/spiflash/new_dir", 0777) < 0) {
+        ESP_LOGE(TAG, "Failed to create a new directory: %s", strerror(errno));
+        return;
+    }
+
+    // List files in the directory
+    list_dir(base_path);
+
+    ESP_LOGI(TAG, "Rename a file");
+
+    if (rename(filename, "/spiflash/new_dir/hello_renamed.txt") < 0) {
+        ESP_LOGE(TAG, "Failed to rename file: %s", strerror(errno));
+        return;
+    }
+
+    // List files in the directory
+    list_dir(base_path);
+    list_dir("/spiflash/new_dir");
+
+    ESP_LOGI(TAG, "Unmounting FAT filesystem");
+    ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_rw_wl(base_path, wl_handle));
+
+    ESP_LOGI(TAG, "Done");
+}
+
+void list_dir(const char *path)
+{
+    ESP_LOGI(TAG, "Listing files in %s:", path);
+
+    DIR *dir = opendir(path);
+    if (!dir) {
+        ESP_LOGE(TAG, "Failed to open directory: %s", strerror(errno));
+        return;
+    }
+
+    printf("%s:\n", path);
+    struct dirent *entry;
+    while ((entry = readdir(dir)) != NULL) {
+        printf(
+            "    %s: %s\n",
+            (entry->d_type == DT_DIR)
+                ? "directory"
+                : "file     ",
+            entry->d_name
+        );
+    }
+
+    closedir(dir);
+}
+
+void clean_dir(const char *path)
+{
+    ESP_LOGI(TAG, "Deleting everything in %s:", path);
+
+    DIR *dir = opendir(path);
+    if (!dir) {
+        ESP_LOGE(TAG, "Failed to open directory: %s", strerror(errno));
+        return;
+    }
+
+    struct dirent *entry;
+    while ((entry = readdir(dir)) != NULL) {
+        char full_path[64] = {0};
+        snprintf(full_path, sizeof(full_path), "%.20s/%.40s", path, entry->d_name);
+        if (entry->d_type == DT_DIR)
+            clean_dir(full_path);
+        if (remove(full_path) != 0) {
+            ESP_LOGE(TAG, "Failed to remove %s: %s", full_path, strerror(errno));
+        }
+    }
+
+    closedir(dir);
+}
diff --git a/examples/storage/fatfsgen/partitions_example.csv b/examples/storage/fatfs/fs_operations/partitions_example.csv
similarity index 100%
rename from examples/storage/fatfsgen/partitions_example.csv
rename to examples/storage/fatfs/fs_operations/partitions_example.csv
diff --git a/examples/storage/fatfs/fs_operations/pytest_fatfs_fs_operations_example.py b/examples/storage/fatfs/fs_operations/pytest_fatfs_fs_operations_example.py
new file mode 100644
index 00000000000..4067c80d134
--- /dev/null
+++ b/examples/storage/fatfs/fs_operations/pytest_fatfs_fs_operations_example.py
@@ -0,0 +1,80 @@
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+from datetime import datetime
+from typing import List
+
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32
+@pytest.mark.generic
+def test_examples_fatfs_fs_operations(config: str, dut: Dut) -> None:
+    # Expects list of strings sequentially
+    def expect_all(msg_list: List[str], to: int) -> None:
+        for msg in msg_list:
+            dut.expect(msg, timeout=to)
+
+    def parse_date() -> datetime:
+        months = ['Jan', 'Feb', 'Mar', 'Apr', 'May', 'Jun', 'Jul', 'Aug', 'Sep', 'Oct', 'Nov', 'Dec']
+
+        pattern = r'([A-Z][a-z]{2}) ([A-Z][a-z]{2}) ([ \d]\d) (\d{2}):(\d{2}):(\d{2}) (\d{4})'
+
+        match = dut.expect(pattern)
+        return datetime(
+            month=months.index(match[2].decode('utf-8')) + 1,
+            day=int(match[3]),
+            hour=int(match[4]),
+            minute=int(match[5]),
+            second=int(match[6]),
+            year=int(match[7]),
+        )
+
+    expect_all(
+        [
+            'example: Mounting FAT filesystem',
+            'example: Creating a file',
+            'example: Writing to the file',
+            'example: File stats:',
+            'File size:',
+        ],
+        5
+    )
+
+    original = parse_date()
+
+    expect_all(
+        [
+            'example: Wait for 3 seconds',
+            'example: Write more to the file',
+            'example: Force cached data and metadata to the filesystem',
+            'File size:',
+        ],
+        5
+    )
+
+    updated = parse_date()
+
+    assert updated > original
+
+    expect_all(
+        [
+            'example: Go to the beginning of the file',
+            'example: Reading from file',
+            'Hello World!',
+            'Hello World!',
+            'example: Closing file',
+            'example: Listing files in /spiflash:',
+            'hello.txt',
+            'example: Creating a new directory',
+            'example: Listing files in /spiflash:',
+            'hello.txt',
+            'new_dir',
+            'example: Rename a file',
+            'example: Listing files in /spiflash:',
+            'new_dir',
+            'example: Listing files in /spiflash/new_dir:',
+            'hello_renamed.txt',
+        ],
+        5
+    )
diff --git a/examples/storage/fatfs/fs_operations/sdkconfig.defaults b/examples/storage/fatfs/fs_operations/sdkconfig.defaults
new file mode 100644
index 00000000000..e5ac9375337
--- /dev/null
+++ b/examples/storage/fatfs/fs_operations/sdkconfig.defaults
@@ -0,0 +1,7 @@
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_example.csv"
+CONFIG_PARTITION_TABLE_FILENAME="partitions_example.csv"
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+CONFIG_FATFS_LFN_HEAP=y
+CONFIG_FATFS_LFN_NONE=n
+CONFIG_FATFS_LFN_STACK=n
diff --git a/examples/storage/fatfs/getting_started/CMakeLists.txt b/examples/storage/fatfs/getting_started/CMakeLists.txt
new file mode 100644
index 00000000000..b5959836791
--- /dev/null
+++ b/examples/storage/fatfs/getting_started/CMakeLists.txt
@@ -0,0 +1,6 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(fatfs_getting_started)
diff --git a/examples/storage/fatfs/getting_started/README.md b/examples/storage/fatfs/getting_started/README.md
new file mode 100644
index 00000000000..626f9323cbb
--- /dev/null
+++ b/examples/storage/fatfs/getting_started/README.md
@@ -0,0 +1,44 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+
+# FATFS minimal example
+
+(See the README.md file in the upper level 'examples' directory for more information about examples.)
+
+This example demonstrates the minimal setup required to store persistent data on SPI Flash using the FAT filesystem.
+Beware that the minimal required size of the flash is 4 MB.
+
+## How to use example
+
+### Build and flash
+
+To run the example, type the following command:
+
+```CMake
+# CMake
+idf.py -p PORT flash monitor
+```
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the Getting Started Guide for full steps to configure and use ESP-IDF to build projects.
+
+## Example output
+
+Here is the example's console output:
+
+```
+...
+I (321) example: Mounting FAT filesystem
+I (331) example: Filesystem mounted
+I (331) example: Opening file
+I (731) example: File written
+I (731) example: Reading file
+I (741) example: Read from file: 'Hello World!'
+I (741) example: Unmounting FAT filesystem
+I (851) example: Done
+...
+```
+
+The logic of the example is contained in a [single source file](./main/fatfs_getting_started_main.c),
+and it should be relatively simple to match points in its execution with the log outputs above.
diff --git a/examples/storage/fatfs/getting_started/main/CMakeLists.txt b/examples/storage/fatfs/getting_started/main/CMakeLists.txt
new file mode 100644
index 00000000000..fec5d19cada
--- /dev/null
+++ b/examples/storage/fatfs/getting_started/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "fatfs_getting_started_main.c"
+                    INCLUDE_DIRS ".")
diff --git a/examples/storage/fatfs/getting_started/main/fatfs_getting_started_main.c b/examples/storage/fatfs/getting_started/main/fatfs_getting_started_main.c
new file mode 100644
index 00000000000..ae8529160e0
--- /dev/null
+++ b/examples/storage/fatfs/getting_started/main/fatfs_getting_started_main.c
@@ -0,0 +1,87 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include "esp_vfs.h"
+#include "esp_vfs_fat.h"
+#include "sdkconfig.h"
+
+static const char *TAG = "example";
+
+// Mount path for the partition
+const char *base_path = "/spiflash";
+
+// Handle of the wear levelling library instance
+static wl_handle_t s_wl_handle = WL_INVALID_HANDLE;
+
+void app_main(void)
+{
+    ESP_LOGI(TAG, "Mounting FAT filesystem");
+    // To mount device we need name of device partition, define base_path
+    // and allow format partition in case if it is new one and was not formatted before
+    const esp_vfs_fat_mount_config_t mount_config = {
+            .max_files = 4, // Number of files that can be open at a time
+            .format_if_mount_failed = true, // If true, try to format the partition if mount fails
+            .allocation_unit_size = CONFIG_WL_SECTOR_SIZE, // Size of allocation unit, cluster size.
+            .use_one_fat = false, // Use only one FAT table (reduce memory usage), but decrease reliability of file system in case of power failure.
+    };
+
+    // Mount FATFS filesystem located on "storage" partition in read-write mode
+    esp_err_t err = esp_vfs_fat_spiflash_mount_rw_wl(base_path, "storage", &mount_config, &s_wl_handle);
+    if (err != ESP_OK) {
+        ESP_LOGE(TAG, "Failed to mount FATFS (%s)", esp_err_to_name(err));
+        return;
+    }
+
+    ESP_LOGI(TAG, "Filesystem mounted");
+
+    ESP_LOGI(TAG, "Opening file");
+
+    const char *filename = "/spiflash/example.txt";
+
+    FILE *f = fopen(filename, "wb");
+    if (f == NULL) {
+        perror("fopen"); // Print reason why fopen failed
+        ESP_LOGE(TAG, "Failed to open file for writing");
+        return;
+    }
+
+    fprintf(f, "Hello World!\n");
+    fclose(f);
+
+    ESP_LOGI(TAG, "File written");
+
+    // Open file for reading
+    ESP_LOGI(TAG, "Reading file");
+
+    f = fopen(filename, "r");
+    if (f == NULL) {
+        ESP_LOGE(TAG, "Failed to open file for reading");
+        return;
+    }
+
+    char line[128];
+
+    fgets(line, sizeof(line), f);
+    fclose(f);
+
+    // strip newline
+    char *pos = strchr(line, '\n');
+    if (pos) {
+        *pos = '\0';
+    }
+
+    ESP_LOGI(TAG, "Read from file: '%s'", line);
+
+    // Unmount FATFS
+    ESP_LOGI(TAG, "Unmounting FAT filesystem");
+
+    ESP_ERROR_CHECK(esp_vfs_fat_spiflash_unmount_rw_wl(base_path, s_wl_handle));
+
+    ESP_LOGI(TAG, "Done");
+}
diff --git a/examples/storage/fatfs/getting_started/partitions_example.csv b/examples/storage/fatfs/getting_started/partitions_example.csv
new file mode 100644
index 00000000000..1c79321a107
--- /dev/null
+++ b/examples/storage/fatfs/getting_started/partitions_example.csv
@@ -0,0 +1,6 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
+nvs,      data, nvs,     0x9000,  0x6000,
+phy_init, data, phy,     0xf000,  0x1000,
+factory,  app,  factory, 0x10000, 1M,
+storage,  data, fat,     ,        1M,
diff --git a/examples/storage/fatfs/getting_started/pytest_fatfs_getting_started_example.py b/examples/storage/fatfs/getting_started/pytest_fatfs_getting_started_example.py
new file mode 100644
index 00000000000..e7f9d7d78a7
--- /dev/null
+++ b/examples/storage/fatfs/getting_started/pytest_fatfs_getting_started_example.py
@@ -0,0 +1,17 @@
+# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32
+@pytest.mark.generic
+def test_examples_fatfs_getting_started(dut: Dut) -> None:
+    dut.expect('example: Mounting FAT filesystem', timeout=90)
+    dut.expect('example: Filesystem mounted', timeout=90)
+    dut.expect('example: Opening file', timeout=90)
+    dut.expect('example: File written', timeout=90)
+    dut.expect('example: Reading file', timeout=90)
+    dut.expect('example: Read from file: \'Hello World!\'', timeout=90)
+    dut.expect('example: Unmounting FAT filesystem', timeout=90)
+    dut.expect('example: Done', timeout=90)
diff --git a/examples/storage/fatfsgen/sdkconfig.defaults b/examples/storage/fatfs/getting_started/sdkconfig.defaults
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.defaults
rename to examples/storage/fatfs/getting_started/sdkconfig.defaults
diff --git a/examples/storage/littlefs/main/CMakeLists.txt b/examples/storage/littlefs/main/CMakeLists.txt
index 83567668b9e..14c7cab1011 100644
--- a/examples/storage/littlefs/main/CMakeLists.txt
+++ b/examples/storage/littlefs/main/CMakeLists.txt
@@ -4,8 +4,4 @@ idf_component_register(SRCS "esp_littlefs_example.c"
 
 # Note: you must have a partition named the first argument (here it's "littlefs")
 # in your partition table csv file.
-if(NOT CMAKE_HOST_SYSTEM_NAME STREQUAL "Windows")
-    littlefs_create_partition_image(storage ../flash_data FLASH_IN_PROJECT)
-else()
-    fail_at_build_time(littlefs "Windows does not support LittleFS partition generation")
-endif()
+littlefs_create_partition_image(storage ../flash_data FLASH_IN_PROJECT)
diff --git a/examples/storage/littlefs/main/esp_littlefs_example.c b/examples/storage/littlefs/main/esp_littlefs_example.c
index 53ee5f58e75..eb4b23e65f3 100644
--- a/examples/storage/littlefs/main/esp_littlefs_example.c
+++ b/examples/storage/littlefs/main/esp_littlefs_example.c
@@ -1,6 +1,6 @@
 /*
  * SPDX-FileCopyrightText: 2023 Brian Pugh
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -85,11 +85,11 @@ void app_main(void)
         return;
     }
 
-    char line[128];
+    char line[128] = {0};
     fgets(line, sizeof(line), f);
     fclose(f);
     // strip newline
-    char*pos = strchr(line, '\n');
+    char* pos = strpbrk(line, "\r\n");
     if (pos) {
         *pos = '\0';
     }
@@ -104,7 +104,7 @@ void app_main(void)
     fgets(line, sizeof(line), f);
     fclose(f);
     // strip newline
-    pos = strchr(line, '\n');
+    pos = strpbrk(line, "\r\n");
     if (pos) {
         *pos = '\0';
     }
diff --git a/examples/storage/littlefs/main/idf_component.yml b/examples/storage/littlefs/main/idf_component.yml
index 0056553732a..e4d970c702b 100644
--- a/examples/storage/littlefs/main/idf_component.yml
+++ b/examples/storage/littlefs/main/idf_component.yml
@@ -1,3 +1,3 @@
 ## IDF Component Manager Manifest File
 dependencies:
-  joltwallet/littlefs: "~=1.14.4"
+  joltwallet/littlefs: "~=1.14.8"
diff --git a/examples/storage/perf_benchmark/README.md b/examples/storage/perf_benchmark/README.md
index d3f4f6b5d17..d18c76cbe9c 100644
--- a/examples/storage/perf_benchmark/README.md
+++ b/examples/storage/perf_benchmark/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # Storage performance benchmark example
 
diff --git a/examples/storage/perf_benchmark/main/idf_component.yml b/examples/storage/perf_benchmark/main/idf_component.yml
index c5c86b6035c..e4d970c702b 100644
--- a/examples/storage/perf_benchmark/main/idf_component.yml
+++ b/examples/storage/perf_benchmark/main/idf_component.yml
@@ -1,3 +1,3 @@
 ## IDF Component Manager Manifest File
 dependencies:
-  joltwallet/littlefs: "^1.14.1"
+  joltwallet/littlefs: "~=1.14.8"
diff --git a/examples/storage/perf_benchmark/main/perf_benchmark_example_tests.c b/examples/storage/perf_benchmark/main/perf_benchmark_example_tests.c
index 1e40685f15c..789e6ce305b 100644
--- a/examples/storage/perf_benchmark/main/perf_benchmark_example_tests.c
+++ b/examples/storage/perf_benchmark/main/perf_benchmark_example_tests.c
@@ -50,7 +50,7 @@ static void print_results(const char *name, double time, size_t size, int repeat
 void spiflash_speed_test_raw_run(size_t repeat_count)
 {
     const size_t buf_size = CONFIG_EXAMPLE_TARGET_RW_SIZE;
-    uint32_t* buf = (uint32_t*) calloc(1, buf_size);
+    uint32_t* buf = (uint32_t*) heap_caps_calloc(1, buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_CACHE_ALIGNED | MALLOC_CAP_DMA);
     assert(buf != NULL);
     esp_fill_random(buf, buf_size);
 
@@ -159,7 +159,7 @@ static void run_fs_tests(const char *base_path, const char *type, bool new_file,
     assert(tiny_size < less_than_target_size);
 
     const size_t buf_size = more_than_target_size;
-    uint32_t* buf = (uint32_t*) calloc(1, buf_size);
+    uint32_t* buf = (uint32_t*) heap_caps_calloc(1, buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_CACHE_ALIGNED | MALLOC_CAP_DMA);
     assert(buf != NULL);
     esp_fill_random(buf, buf_size);
 
@@ -219,7 +219,8 @@ void sdcard_speed_test_raw_run(sdmmc_card_t *card, size_t repeat_count)
     size_t sector_count = CONFIG_EXAMPLE_TARGET_RW_SIZE / sector_size;
     size_t subsection_sector_count = sector_count / 4;
 
-    char *buf = (char *) calloc(1, sector_count * sector_size);
+    // Best performance is achieved when the buffer is internal (not PSRAM) and aligned to RAM line size
+    char *buf = (char *) heap_caps_calloc(1, sector_count * sector_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_CACHE_ALIGNED | MALLOC_CAP_DMA);
     assert(buf != NULL);
 
     struct timeval tv_start;
diff --git a/examples/storage/perf_benchmark/pytest_perf_benchmark_example.py b/examples/storage/perf_benchmark/pytest_perf_benchmark_example.py
index 0b7f3b14ffb..defa143f895 100644
--- a/examples/storage/perf_benchmark/pytest_perf_benchmark_example.py
+++ b/examples/storage/perf_benchmark/pytest_perf_benchmark_example.py
@@ -57,6 +57,8 @@ def test_examples_perf_benchmark_sdcard_sdmmc(dut: Dut) -> None:
 @pytest.mark.temp_skip_ci(targets=['esp32'], reason='IDFCI-2059, temporary lack runner')
 @pytest.mark.esp32c3
 @pytest.mark.esp32s2
+@pytest.mark.esp32c5
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C5 C61 GPSPI same, so testing on C5 is enough')
 @pytest.mark.sdcard_spimode
 @pytest.mark.parametrize(
     'config',
diff --git a/examples/storage/sd_card/sdmmc/main/Kconfig.projbuild b/examples/storage/sd_card/sdmmc/main/Kconfig.projbuild
index 70449a8e395..d85180bbbcd 100644
--- a/examples/storage/sd_card/sdmmc/main/Kconfig.projbuild
+++ b/examples/storage/sd_card/sdmmc/main/Kconfig.projbuild
@@ -28,6 +28,22 @@ menu "SD/MMC Example Configuration"
             bool "1 line (D0)"
     endchoice
 
+    choice EXAMPLE_SDMMC_SPEED_MODE
+        prompt "SD/MMC speed mode"
+        default EXAMPLE_SDMMC_SPEED_DS
+
+        config EXAMPLE_SDMMC_SPEED_DS
+            bool "Default Speed"
+        config EXAMPLE_SDMMC_SPEED_HS
+            bool "High Speed"
+        config EXAMPLE_SDMMC_SPEED_UHS_I_SDR50
+            bool "UHS-I SDR50 (100 MHz, 50 MB/s)"
+            depends on SOC_SDMMC_UHS_I_SUPPORTED
+        config EXAMPLE_SDMMC_SPEED_UHS_I_DDR50
+            bool "UHS-I DDR50 (50 MHz, 50 MB/s)"
+            depends on SOC_SDMMC_UHS_I_SUPPORTED
+    endchoice
+
     if SOC_SDMMC_USE_GPIO_MATRIX
 
         config EXAMPLE_PIN_CMD
diff --git a/examples/storage/sd_card/sdmmc/main/sd_card_example_main.c b/examples/storage/sd_card/sdmmc/main/sd_card_example_main.c
index 6821d05fb24..9946e6d9473 100644
--- a/examples/storage/sd_card/sdmmc/main/sd_card_example_main.c
+++ b/examples/storage/sd_card/sdmmc/main/sd_card_example_main.c
@@ -24,6 +24,7 @@
 static const char *TAG = "example";
 
 #define MOUNT_POINT "/sdcard"
+#define EXAMPLE_IS_UHS1    (CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR50 || CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50)
 
 #ifdef CONFIG_EXAMPLE_DEBUG_PIN_CONNECTIONS
 const char* names[] = {"CLK", "CMD", "D0", "D1", "D2", "D3"};
@@ -128,6 +129,16 @@ void app_main(void)
     // For setting a specific frequency, use host.max_freq_khz (range 400kHz - 40MHz for SDMMC)
     // Example: for fixed frequency of 10MHz, use host.max_freq_khz = 10000;
     sdmmc_host_t host = SDMMC_HOST_DEFAULT();
+#if CONFIG_EXAMPLE_SDMMC_SPEED_HS
+    host.max_freq_khz = SDMMC_FREQ_HIGHSPEED;
+#elif CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_SDR50
+    host.slot = SDMMC_HOST_SLOT_0;
+    host.max_freq_khz = SDMMC_FREQ_SDR50;
+    host.flags &= ~SDMMC_HOST_FLAG_DDR;
+#elif CONFIG_EXAMPLE_SDMMC_SPEED_UHS_I_DDR50
+    host.slot = SDMMC_HOST_SLOT_0;
+    host.max_freq_khz = SDMMC_FREQ_DDR50;
+#endif
 
     // For SoCs where the SD power can be supplied both via an internal or external (e.g. on-board LDO) power supply.
     // When using specific IO pins (which can be used for ultra high-speed SDMMC) to connect to the SD card
@@ -149,6 +160,9 @@ void app_main(void)
     // This initializes the slot without card detect (CD) and write protect (WP) signals.
     // Modify slot_config.gpio_cd and slot_config.gpio_wp if your board has these signals.
     sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT();
+#if EXAMPLE_IS_UHS1
+    slot_config.flags |= SDMMC_SLOT_FLAG_UHS1;
+#endif
 
     // Set bus width to use:
 #ifdef CONFIG_EXAMPLE_SDMMC_BUS_WIDTH_4
diff --git a/examples/storage/sd_card/sdspi/CMakeLists.txt b/examples/storage/sd_card/sdspi/CMakeLists.txt
index d41a683007d..e140d486250 100644
--- a/examples/storage/sd_card/sdspi/CMakeLists.txt
+++ b/examples/storage/sd_card/sdspi/CMakeLists.txt
@@ -2,7 +2,6 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-list(APPEND EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/examples/storage/sd_card/sdmmc/components/sd_card")
 set(COMPONENTS main)
 
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
diff --git a/examples/storage/sd_card/sdspi/main/idf_component.yml b/examples/storage/sd_card/sdspi/main/idf_component.yml
new file mode 100644
index 00000000000..b755a62b147
--- /dev/null
+++ b/examples/storage/sd_card/sdspi/main/idf_component.yml
@@ -0,0 +1,3 @@
+dependencies:
+  sd_card:
+    path: ${IDF_PATH}/examples/storage/sd_card/sdmmc/components/sd_card
diff --git a/examples/storage/sd_card/sdspi/pytest_sdspi_card_example.py b/examples/storage/sd_card/sdspi/pytest_sdspi_card_example.py
index 616c5cafdbc..4cfac08bf1a 100644
--- a/examples/storage/sd_card/sdspi/pytest_sdspi_card_example.py
+++ b/examples/storage/sd_card/sdspi/pytest_sdspi_card_example.py
@@ -7,6 +7,7 @@
 from pytest_embedded import Dut
 
 
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C5 C61 GPSPI same, so testing on C5 is enough')
 @pytest.mark.esp32
 @pytest.mark.esp32s3
 @pytest.mark.esp32c3
diff --git a/examples/storage/semihost_vfs/README.md b/examples/storage/semihost_vfs/README.md
index 0cf77e01fa4..0ce5acc0eac 100644
--- a/examples/storage/semihost_vfs/README.md
+++ b/examples/storage/semihost_vfs/README.md
@@ -97,7 +97,7 @@ There are two outputs produced by example:
    ```
    W (274) example: Switch to semihosted stdout
    W (274) example: Switched back to UART stdout
-   I (274) example: Wrote 2798 bytes
+   I (274) example: Wrote 2776 bytes
    ====================== HOST DATA START =========================
    The following are the graphical (non-control) characters defined by
    ISO 8859-1 (1987).  Descriptions in words aren't all that helpful,
@@ -115,4 +115,3 @@ There are two outputs produced by example:
    ====================== HOST DATA END =========================
    I (694) example: Read 6121 bytes
    ```
-
diff --git a/examples/storage/semihost_vfs/pytest_semihost_vfs.py b/examples/storage/semihost_vfs/pytest_semihost_vfs.py
index aff2e51227a..90af90e29e2 100644
--- a/examples/storage/semihost_vfs/pytest_semihost_vfs.py
+++ b/examples/storage/semihost_vfs/pytest_semihost_vfs.py
@@ -1,6 +1,5 @@
-# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Unlicense OR CC0-1.0
-
 import os
 import shutil
 import tempfile
@@ -42,7 +41,10 @@ def prepare() -> t.Generator[None, None, None]:
 def test_semihost_vfs(dut: IdfDut) -> None:
     dut.expect_exact('example: Switch to semihosted stdout')
     dut.expect_exact('example: Switched back to UART stdout')
-    dut.expect_exact('example: Wrote 2798 bytes')
+    if dut.app.sdkconfig.get('LOG_COLORS') is True:
+        dut.expect_exact('example: Wrote 2798 bytes')
+    else:
+        dut.expect_exact('example: Wrote 2776 bytes')
     dut.expect_exact('====================== HOST DATA START =========================')
 
     with open(HOST_FILE_PATH) as f:
diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml
index ddb33070ef0..0dd47d3a677 100644
--- a/examples/system/.build-test-rules.yml
+++ b/examples/system/.build-test-rules.yml
@@ -1,10 +1,10 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
 
 examples/system/app_trace_basic:
-  disable:
+  disable_test:
     - if: IDF_TARGET in ["esp32c6", "esp32h2", "esp32p4", "esp32c5", "esp32c61"]
       temporary: true
-      reason: targets not supported yet, TODO[C61] IDF-9264 IDF-10992
+      reason: usb-serial-jtag tests are not stable yet. TODO[C61] IDF-10992
 
 examples/system/base_mac_address:
   depends_components:
@@ -110,14 +110,14 @@ examples/system/himem:
 
 examples/system/ipc/ipc_isr/riscv:
   enable:
-    - if: IDF_TARGET_ARCH_RISCV == 1 and ESP_IPC_ISR_ENABLE == 1
+    - if: IDF_TARGET in ["esp32p4"]
       reason: The test is intended only for multi-core chips
   depends_components:
     - esp_system
 
 examples/system/ipc/ipc_isr/xtensa:
   enable:
-    - if: IDF_TARGET_ARCH_XTENSA == 1 and ESP_IPC_ISR_ENABLE == 1
+    - if: IDF_TARGET in ["esp32", "esp32s3"]
       reason: The test is intended only for multi-core chips
   depends_components:
     - esp_system
@@ -128,7 +128,7 @@ examples/system/light_sleep:
 
 examples/system/nmi_isr:
   enable:
-    - if: IDF_TARGET_ARCH_XTENSA == 1
+    - if: IDF_TARGET in ["esp32", "esp32s2", "esp32s3"]
       reason: test NMI for Xtensa targets only
 
 examples/system/ota/advanced_https_ota:
@@ -169,14 +169,27 @@ examples/system/ota/native_ota_example:
     - protocol_examples_common
 
 examples/system/ota/otatool:
+  enable:
+    - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["esp32c5", "esp32c61"]
+
+examples/system/ota/partitions_ota:
   disable:
     - if: IDF_TARGET in ["esp32h2"]
       temporary: true
       reason: target esp32h2 is not supported yet
   disable_test:
-    - if: IDF_TARGET in ["esp32c61"]
-      reason: target esp32c61 is not supported yet
-
+    - if: IDF_TARGET not in ["esp32", "esp32c3", "esp32s3"]
+      temporary: true
+      reason: lack of runners
+  depends_components:
+    - app_update
+    - esp_https_ota
+    - esp_http_client
+    # different configs need different components
+    - esp_eth
+    - esp_wifi
+    - esp_phy
+    - mbedtls
 
 examples/system/ota/pre_encrypted_ota:
   disable:
@@ -299,6 +312,12 @@ examples/system/ulp/lp_core/gpio_intr_pulse_counter:
   depends_components:
     - ulp
 
+examples/system/ulp/lp_core/gpio_wakeup:
+  enable:
+    - if: (SOC_LP_CORE_SUPPORTED == 1) and (SOC_RTCIO_PIN_COUNT > 0)
+  depends_components:
+    - ulp
+
 examples/system/ulp/lp_core/inter_cpu_critical_section/:
   enable:
     - if: SOC_LP_CORE_SUPPORTED == 1
@@ -327,6 +346,12 @@ examples/system/ulp/lp_core/lp_i2c:
   depends_components:
     - ulp
 
+examples/system/ulp/lp_core/lp_spi:
+  enable:
+    - if: SOC_LP_SPI_SUPPORTED == 1 and SOC_DEEP_SLEEP_SUPPORTED == 1
+  depends_components:
+    - ulp
+
 examples/system/ulp/lp_core/lp_uart/lp_uart_echo:
   disable:
     - if: (SOC_ULP_LP_UART_SUPPORTED != 1) or (SOC_DEEP_SLEEP_SUPPORTED != 1)
diff --git a/examples/system/app_trace_basic/README.md b/examples/system/app_trace_basic/README.md
index 2da31cd059a..151e992d1a4 100644
--- a/examples/system/app_trace_basic/README.md
+++ b/examples/system/app_trace_basic/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # Application Level Tracing Example (Basic)
 
diff --git a/examples/system/console/advanced/README.md b/examples/system/console/advanced/README.md
index 6a520e850d9..412ba5c0bf9 100644
--- a/examples/system/console/advanced/README.md
+++ b/examples/system/console/advanced/README.md
@@ -160,10 +160,14 @@ Use UP/DOWN arrows to navigate through command history.
 Press TAB when typing command name to auto-complete.
 Your terminal application does not support escape sequences.
 Line editing and history features are disabled.
-On Windows, try using Putty instead.
+On Windows, try using Windows Terminal or Putty instead.
 esp32>
 ```
 
+### Escape Sequences on Windows 10
+
+When using the default command line or PowerShell on Windows 10, you may see a message indicating that the console does not support escape sequences, as shown in the above output. To avoid such issues, it is recommended to run the serial monitor under [Windows Terminal](https://en.wikipedia.org/wiki/Windows_Terminal), which supports all required escape sequences for the app, unlike the default terminal. The main escape sequence of concern is the Device Status Report (`0x1b[5n`), which is used to check terminal capabilities. Any response to this sequence indicates support. This should not be an issue on Windows 11, where Windows Terminal is the default.
+
 ### No USB port appears
 
 On Windows 10, macOS, Linux, USB CDC devices do not require additional drivers to be installed.
diff --git a/examples/system/console/advanced/components/cmd_system/cmd_system_common.c b/examples/system/console/advanced/components/cmd_system/cmd_system_common.c
index 8daa5e5cca6..ca1fb17a728 100644
--- a/examples/system/console/advanced/components/cmd_system/cmd_system_common.c
+++ b/examples/system/console/advanced/components/cmd_system/cmd_system_common.c
@@ -266,7 +266,7 @@ static int log_level(int argc, char **argv)
 static void register_log_level(void)
 {
     log_level_args.tag = arg_str1(NULL, NULL, "<tag|*>", "Log tag to set the level for, or * to set for all tags");
-    log_level_args.level = arg_str1(NULL, NULL, "<none|error|warn|debug|verbose>", "Log level to set. Abbreviated words are accepted.");
+    log_level_args.level = arg_str1(NULL, NULL, "<none|error|warn|info|debug|verbose>", "Log level to set. Abbreviated words are accepted.");
     log_level_args.end = arg_end(2);
 
     const esp_console_cmd_t cmd = {
diff --git a/examples/system/console/advanced/main/console_example_main.c b/examples/system/console/advanced/main/console_example_main.c
index 1ca7aee2e8f..b02fc8fb7b1 100644
--- a/examples/system/console/advanced/main/console_example_main.c
+++ b/examples/system/console/advanced/main/console_example_main.c
@@ -118,7 +118,7 @@ void app_main(void)
         printf("\n"
                "Your terminal application does not support escape sequences.\n"
                "Line editing and history features are disabled.\n"
-               "On Windows, try using Putty instead.\n");
+               "On Windows, try using Windows Terminal or Putty instead.\n");
     }
 
     /* Main loop */
diff --git a/examples/system/console/basic/README.md b/examples/system/console/basic/README.md
index 42387e5c625..cd17e6af15c 100644
--- a/examples/system/console/basic/README.md
+++ b/examples/system/console/basic/README.md
@@ -147,6 +147,10 @@ Use UP/DOWN arrows to navigate through command history.
 Press TAB when typing command name to auto-complete.
 Your terminal application does not support escape sequences.
 Line editing and history features are disabled.
-On Windows, try using Putty instead.
+On Windows, try using Windows Terminal or Putty instead.
 esp32>
 ```
+
+### Escape Sequences on Windows 10
+
+When using the default command line or PowerShell on Windows 10, you may see a message indicating that the console does not support escape sequences, as shown in the above output. To avoid such issues, it is recommended to run the serial monitor under [Windows Terminal](https://en.wikipedia.org/wiki/Windows_Terminal), which supports all required escape sequences for the app, unlike the default terminal. The main escape sequence of concern is the Device Status Report (`0x1b[5n`), which is used to check terminal capabilities. Any response to this sequence indicates support. This should not be an issue on Windows 11, where Windows Terminal is the default.
diff --git a/examples/system/deep_sleep/main/Kconfig.projbuild b/examples/system/deep_sleep/main/Kconfig.projbuild
index 7c2999c8578..5590daf455e 100644
--- a/examples/system/deep_sleep/main/Kconfig.projbuild
+++ b/examples/system/deep_sleep/main/Kconfig.projbuild
@@ -3,7 +3,7 @@ menu "Example Configuration"
     config EXAMPLE_TOUCH_WAKEUP
         bool "Enable touch wake up"
         default y
-        depends on SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
+        depends on SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP && !IDF_TARGET_ESP32P4
         help
             This option enables wake up from deep sleep using touch pads.
             ESP32 - TOUCH8 and TOUCH9, which correspond to GPIO33 and GPIO32.
diff --git a/examples/system/deep_sleep/main/touch_wakeup.c b/examples/system/deep_sleep/main/touch_wakeup.c
index 13d4ff64d4d..97d54e8311b 100644
--- a/examples/system/deep_sleep/main/touch_wakeup.c
+++ b/examples/system/deep_sleep/main/touch_wakeup.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
diff --git a/examples/system/deep_sleep/sdkconfig.defaults b/examples/system/deep_sleep/sdkconfig.defaults
index b508ab21b76..0fc182032c8 100644
--- a/examples/system/deep_sleep/sdkconfig.defaults
+++ b/examples/system/deep_sleep/sdkconfig.defaults
@@ -6,3 +6,4 @@ CONFIG_NEWLIB_TIME_SYSCALL_USE_RTC_HRT=y
 CONFIG_RTC_CLK_SRC_INT_RC=y
 CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y
 CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_TOUCH_SUPPRESS_DEPRECATE_WARN=y
diff --git a/examples/system/efuse/pytest_system_efuse_example.py b/examples/system/efuse/pytest_system_efuse_example.py
index b7e922a6259..6d205104590 100644
--- a/examples/system/efuse/pytest_system_efuse_example.py
+++ b/examples/system/efuse/pytest_system_efuse_example.py
@@ -552,11 +552,9 @@ def test_examples_efuse_with_virt_secure_boot_v2_pre_loaded(dut: Dut) -> None:
 
 @pytest.mark.esp32c3
 @pytest.mark.esp32c2
-# TODO: [ESP32C5] IDF-10043
-# @pytest.mark.esp32c5
-# TODO: [ESP32C61] IDF-10102
-# @pytest.mark.esp32c61
+@pytest.mark.esp32c5
 @pytest.mark.esp32c6
+@pytest.mark.esp32c61
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
 @pytest.mark.esp32s2
@@ -629,11 +627,9 @@ def test_examples_efuse_with_virt_secure_boot_v2_esp32xx(dut: Dut) -> None:
 
 @pytest.mark.esp32c3
 @pytest.mark.esp32c2
-# TODO: [ESP32C5] IDF-10043
-# @pytest.mark.esp32c5
-# TODO: [ESP32C61] IDF-10102
-# @pytest.mark.esp32c61
+@pytest.mark.esp32c5
 @pytest.mark.esp32c6
+@pytest.mark.esp32c61
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
 @pytest.mark.esp32s2
diff --git a/examples/system/efuse/test/partitions_efuse_emul.csv b/examples/system/efuse/test/partitions_efuse_emul.csv
index 4401ccfe748..32c46f969e0 100644
--- a/examples/system/efuse/test/partitions_efuse_emul.csv
+++ b/examples/system/efuse/test/partitions_efuse_emul.csv
@@ -1,7 +1,9 @@
-# Name,   Type, SubType, Offset,   Size,      Flags
-nvs,        data, nvs,      ,       0x4000,
-phy_init,   data, phy,      ,       0x1000,
-storage,    data, 0xff,     ,       0x1000, encrypted
-nvs_key,    data, nvs_keys, ,       0x1000, encrypted,
-emul_efuse, data, efuse,    ,       0x2000,
-factory,    app,  factory,  ,       1M,
+# Name,           Type,            SubType,  Offset, Size,   Flags
+bootloader,       bootloader,      primary,  N/A,    N/A,
+partition_table,  partition_table, primary,  N/A,    N/A,
+nvs,              data,            nvs,      ,       0x4000,
+phy_init,         data,            phy,      ,       0x1000,
+storage,          data,            0xff,     ,       0x1000, encrypted
+nvs_key,          data,            nvs_keys, ,       0x1000, encrypted,
+emul_efuse,       data,            efuse,    ,       0x2000,
+factory,          app,             factory,  ,       1M,
diff --git a/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c b/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c
index 670b13edc12..409e2095b62 100644
--- a/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c
+++ b/examples/system/freertos/basic_freertos_smp_usage/main/lock_example.c
@@ -78,7 +78,7 @@ static void inc_num_atomic_iter(void *arg)
 
 static void inc_num_mutex(void *arg)
 {
-    int task_index = *(int*)arg;
+    int task_index = (int)arg;
     ESP_LOGI(TAG, "mutex task %d created", task_index);
 
     while (!timed_out) {
@@ -159,7 +159,7 @@ int comp_lock_entry_func(int argc, char **argv)
     s_global_num = 0;
     // create 2 tasks to increase a shared number in turn
     for (thread_id = 0; thread_id < SHARE_RES_THREAD_NUM; thread_id++) {
-        xTaskCreatePinnedToCore(inc_num_mutex, NULL, 4096, &thread_id, TASK_PRIO_3, NULL, tskNO_AFFINITY);
+        xTaskCreatePinnedToCore(inc_num_mutex, NULL, 4096, (void *)thread_id, TASK_PRIO_3, NULL, tskNO_AFFINITY);
     }
 
     // time out and stop running after 5 seconds
diff --git a/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py b/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py
index 5019db6a4b4..fa7ac3b547d 100644
--- a/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py
+++ b/examples/system/freertos/basic_freertos_smp_usage/pytest_smp_examples.py
@@ -13,10 +13,13 @@ def test_creating_task(
     dut.expect(r'esp32(?:[a-zA-Z]\d)?>')
     # test creating_task
     dut.write('create_task')
-    dut.expect('create task example: task#0 is running on core#0')
-    dut.expect('create task example: task#1 is running on core#0')
-    dut.expect(r'create task example: task#2 is running on core#\d')
-    dut.expect(r'create task example: task#3 is running on core#\d')
+    expected_patterns = [
+        'create task example: task#0 is running on core#0',
+        'create task example: task#1 is running on core#0',
+        r'create task example: task#2 is running on core#\d',
+        r'create task example: task#3 is running on core#\d',
+    ]
+    dut.expect(expected_patterns, expect_all=True)
 
 
 @pytest.mark.esp32c3
@@ -46,14 +49,14 @@ def test_locks(
     dut.expect(r'esp32(?:[a-zA-Z]\d)?>')
     # test locks
     dut.write('lock')
-    dut.expect(r'lock example: mutex task took \d+ us on core\d')
-    dut.expect(r'lock example: spinlock task took \d+ us on core\d')
-    dut.expect(r'lock example: atomic task took \d+ us on core\d')
-    dut.expect(r'task0 read value = 0 on core #\d')
-    dut.expect('task0 set value = 1')
-    dut.expect(r'task\d read value = 1 on core #\d')
-    dut.expect(r'task\d set value = 2')
-    dut.expect(r'task0 read value = 2 on core #\d')
+    expected_patterns = [
+        r'lock example: mutex task took \d+ us on core\d',
+        r'lock example: spinlock task took \d+ us on core\d',
+        r'lock example: atomic task took \d+ us on core\d',
+        r'task\d read value = \d on core #\d',
+        r'task\d set value = \d',
+    ]
+    dut.expect(expected_patterns, expect_all=True)
 
 
 @pytest.mark.esp32c3
diff --git a/examples/system/nmi_isr/main/nmi_isr_main.c b/examples/system/nmi_isr/main/nmi_isr_main.c
index f2e86d5f425..030577e9215 100644
--- a/examples/system/nmi_isr/main/nmi_isr_main.c
+++ b/examples/system/nmi_isr/main/nmi_isr_main.c
@@ -26,6 +26,7 @@ void app_main(void)
 
     printf("example: Start\n");
 
+    gpio_reset_pin(EXAMPLE_GPIO_IN);
     /* Make sure we have a pull-down on the input GPIO to prevent noise (when disconnected) */
     gpio_pulldown_en(EXAMPLE_GPIO_IN);
     gpio_set_direction(EXAMPLE_GPIO_IN, GPIO_MODE_INPUT_OUTPUT);
diff --git a/examples/system/ota/README.md b/examples/system/ota/README.md
index 09d15d6b83f..ed153c17377 100644
--- a/examples/system/ota/README.md
+++ b/examples/system/ota/README.md
@@ -15,7 +15,15 @@ An application on "ESP-Dev-Board" may be upgraded at runtime by downloading a ne
 - Using the native APIs provided by the [`app_update`](../../../components/app_update) component.
 - Using simplified APIs provided by the [`esp_https_ota`](../../../components/esp_https_ota) component, which provides functionality to upgrade over HTTPS.
 
-Use of the native API is demonstrated in the `native_ota_example` directory while the API provided by the `esp_https_ota` component is demonstrated under `simple_ota_example` and `advanced_https_ota`.
+Use of the native API is demonstrated in the `native_ota_example` directory while the API provided by the `esp_https_ota` component is demonstrated under `simple_ota_example`, `advanced_https_ota`, and `partitions_ota`.
+
+The `partitions_ota` demonstrates the OTA update process for any partition type (other examples support only safe updates for application):
+- Application (safe update).
+- Bootloader (unsafe update).
+- Partition table (unsafe update).
+- other data partitions (unsafe update).
+
+**Note:** **Safe updates** are designed to ensure that the device remains operational even if the update process is interrupted. This means that the device can still boot and function normally, minimizing the risk of failure. On the other hand, **unsafe updates** carry a significant risk. If the update is disrupted while copying to the destination partition, it can lead to critical failures, potentially making the device inoperable and unrecoverable. Since the final copying is performed on the user side, this risk can be minimized by ensuring stable power and error-free conditions during this time.
 
 For information regarding the `esp_https_ota` component, please refer to [ESP HTTPS OTA](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/system/esp_https_ota.html).
 
diff --git a/examples/system/ota/otatool/README.md b/examples/system/ota/otatool/README.md
index 255b2232003..859fb55977c 100644
--- a/examples/system/ota/otatool/README.md
+++ b/examples/system/ota/otatool/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # OTA Tool Example
 
diff --git a/examples/system/ota/otatool/pytest_otatool.py b/examples/system/ota/otatool/pytest_otatool.py
index 8a9d0b21af7..a8fe39976a2 100644
--- a/examples/system/ota/otatool/pytest_otatool.py
+++ b/examples/system/ota/otatool/pytest_otatool.py
@@ -8,7 +8,11 @@
 from pytest_embedded import Dut
 
 
-def _real_test_func(dut: Dut) -> None:
+@pytest.mark.parametrize('config', [
+    pytest.param('default', marks=[pytest.mark.supported_targets, pytest.mark.generic, pytest.mark.temp_skip(targets=['esp32c2'], reason='must have 4MB')]),
+    pytest.param('default', marks=[pytest.mark.esp32c2, pytest.mark.generic, pytest.mark.flash_4mb]),
+], indirect=True)
+def test_otatool_example(dut: Dut) -> None:
     # Verify factory firmware
     dut.expect('OTA Tool Example')
     dut.expect('Example end')
@@ -24,23 +28,3 @@ def _real_test_func(dut: Dut) -> None:
             binary_path = flash_file[1]
             break
     subprocess.check_call([sys.executable, script_path, '--binary', binary_path])
-
-
-@pytest.mark.esp32
-@pytest.mark.esp32s2
-@pytest.mark.esp32c3
-@pytest.mark.esp32s3
-@pytest.mark.esp32c5
-# @pytest.mark.esp32c61 #IDF-11309
-@pytest.mark.esp32c6
-@pytest.mark.esp32p4
-@pytest.mark.generic
-def test_otatool_example(dut: Dut) -> None:
-    _real_test_func(dut)
-
-
-@pytest.mark.esp32c2
-@pytest.mark.generic
-@pytest.mark.flash_4mb
-def test_otatool_example_c2_4mb(dut: Dut) -> None:
-    _real_test_func(dut)
diff --git a/examples/system/ota/partitions_ota/CMakeLists.txt b/examples/system/ota/partitions_ota/CMakeLists.txt
new file mode 100644
index 00000000000..7eea2e02e3b
--- /dev/null
+++ b/examples/system/ota/partitions_ota/CMakeLists.txt
@@ -0,0 +1,15 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(partitions_ota)
+
+# Copy storage.bin from test folder to build directory
+add_custom_target(copy_storage_bin ALL
+    COMMAND ${CMAKE_COMMAND} -E copy
+        ${CMAKE_SOURCE_DIR}/test/storage.bin
+        ${CMAKE_BINARY_DIR}/storage.bin
+    COMMENT "Copying test/storage.bin to build directory"
+    DEPENDS ${CMAKE_SOURCE_DIR}/test/storage.bin
+)
diff --git a/examples/system/ota/partitions_ota/README.md b/examples/system/ota/partitions_ota/README.md
new file mode 100644
index 00000000000..fa93835fe68
--- /dev/null
+++ b/examples/system/ota/partitions_ota/README.md
@@ -0,0 +1,633 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
+
+# Partition OTA Example
+
+This example demonstrates how to perform OTA updates for various partitions using the `esp_https_ota` component's APIs. The following partitions can be updated:
+- Application (app)
+- Bootloader
+- Partition Table
+- Storage
+
+This example can be easily modified to perform OTA updates for any partition type.
+
+> ⚠️ **WARNING**: Updating the bootloader and partition table is not safe. If the final copying to the destination partition is interrupted, the chip may fail to boot. Ensure that the final copy occurs only when power is stable and there is a low risk of errors.
+
+## OTA Update
+Currently, there is no rollback mechanism for non-application partitions. In case of failure, only the application partition can safely rollback.
+
+### Application
+
+Application OTA updates use one active and one passive partition. The new image is downloaded into the passive partition. Once the download is complete and verified, the device switches to the new image. This approach ensures that unexpected reboots during the update do not render the device unusable.
+
+### Bootloader
+
+Bootloader OTA updates are not inherently safe because the ROM bootloader does not support fallback to a recovery bootloader partition. Only the primary bootloader partition can be loaded by the ROM bootloader. Updating the bootloader is rarely necessary, and it is generally not recommended. However, if required, it can be done using the following approaches:
+
+- Register the primary bootloader partition in the partition table, if not already present (see `test/partitions_efuse_emul_2.csv`).
+- Decide where to download the new bootloader image:
+  - Use a passive app partition, if app rollback is not used at the same time.
+  - Use a dedicated OTA bootloader partition (type=bootloader, subtype=ota). You can find unallocated flash space with `partition_utils_find_unallocated()`.
+  - Download directly into the primary bootloader partition (this approach is highly unsafe).
+
+After verification, if `finalize_with_copy` is set to `true`, the tool will automatically copy the new image to the primary bootloader partition. Set `finalize_with_copy` to `false` if you wish to control the final copy step manually.
+
+Limitations for Bootloader OTA updates:
+- Secure Boot V1-enabled devices do not support bootloader updates.
+- There is always a risk of device bricking when updating the bootloader.
+
+### Partition Table
+
+Updating the partition table via OTA is similarly unsafe because the bootloader cannot use a backup partition table in case of failure. If the update fails, the device will be unable to boot. Partition table updates are rarely needed, and caution is strongly advised. The workflow for partition table updates is the same as for the bootloader.
+
+### Storage
+
+Updating storage partitions via OTA is also risky due to the potential for data loss in the partition. There is no fallback mechanism if an error occurs during the update. The workflow for Storage updates is the same as for the bootloader.
+
+## Configuration
+
+Refer to the README.md file in the parent directory for setup instructions.
+
+This example supports binding to a specific network interface ("Ethernet" or "WiFi Station") for firmware updates. You can configure this in `idf.py menuconfig -> Example Configuration -> Support firmware upgrade bind specified interface -> Choose OTA data bind interface`.
+
+The CSV partition table file may include these entries at the beginning (see `test/partitions_efuse_emul_2.csv`):
+```
+PrimaryBTLDR, bootloader, primary, N/A, N/A, encrypted
+PrimaryPrtTable, partition_table, primary, N/A, N/A, encrypted
+```
+
+## Example output
+
+Running the exapmple with sdkconfig.ci.on_update_no_sb_rsa settings:
+
+```
+ESP-ROM:esp32s3-20210327
+Build:Mar 27 2021
+rst:0x1 (POWERON),boot:0x8 (SPI_FAST_FLASH_BOOT)
+SPIWP:0xee
+mode:DIO, clock div:1
+load:0x3fce2820,len:0x15a0
+load:0x403c8700,len:0x4
+load:0x403c8704,len:0xd20
+load:0x403cb700,len:0x2f3c
+entry 0x403c8928
+I (27) boot: ESP-IDF 95a1e4cd 2nd stage bootloader
+I (27) boot: compile time Oct 28 2024 15:26:41
+I (27) boot: Multicore bootloader
+I (27) boot: chip revision: v0.1
+I (30) boot: efuse block revision: v1.2
+I (34) boot.esp32s3: Boot SPI Speed : 80MHz
+I (37) boot.esp32s3: SPI Mode       : DIO
+I (41) boot.esp32s3: SPI Flash Size : 4MB
+I (45) boot: Enabling RNG early entropy source...
+I (49) boot: Partition Table:
+I (52) boot: ## Label            Usage          Type ST Offset   Length
+I (58) boot:  0 nvs              WiFi data        01 02 0000d000 00006000
+I (65) boot:  1 nvs_key          NVS keys         01 04 00013000 00001000
+I (71) boot:  2 storage          Unknown data     01 06 00014000 00001000
+I (78) boot:  3 otadata          OTA data         01 00 00015000 00002000
+I (84) boot:  4 phy_init         RF data          01 01 00017000 00001000
+I (91) boot:  5 emul_efuse       efuse            01 05 00018000 00002000
+I (97) boot:  6 ota_0            OTA app          00 10 00020000 001b0000
+I (104) boot:  7 ota_1            OTA app          00 11 001d0000 001b0000
+I (111) boot: End of partition table
+I (114) boot: No factory image, trying OTA 0
+I (118) esp_image: segment 0: paddr=00020020 vaddr=3c090020 size=24288h (148104) map
+I (152) esp_image: segment 1: paddr=000442b0 vaddr=3fc98900 size=04970h ( 18800) load
+I (156) esp_image: segment 2: paddr=00048c28 vaddr=40374000 size=073f0h ( 29680) load
+I (162) esp_image: segment 3: paddr=00050020 vaddr=42000020 size=8fc00h (588800) map
+I (267) esp_image: segment 4: paddr=000dfc28 vaddr=4037b3f0 size=0d4ach ( 54444) load
+I (279) esp_image: segment 5: paddr=000ed0dc vaddr=600fe100 size=0001ch (    28) load
+I (287) boot: Loaded app from partition at offset 0x20000
+I (429) boot: Set actual ota_seq=1 in otadata[0]
+I (430) boot: Disabling RNG early entropy source...
+I (439) cpu_start: Multicore app
+I (449) cpu_start: Pro cpu start user code
+I (449) cpu_start: cpu freq: 160000000 Hz
+I (449) app_init: Application information:
+I (449) app_init: Project name:     partitions_ota
+I (453) app_init: App version:      95a1e4cd
+I (457) app_init: Compile time:     Oct 28 2024 15:26:38
+I (462) app_init: ELF file SHA256:  0810d7fd3...
+I (467) app_init: ESP-IDF:          95a1e4cd
+I (471) efuse_init: Min chip rev:     v0.0
+I (475) efuse_init: Max chip rev:     v0.99 
+I (479) efuse_init: Chip rev:         v0.1
+I (482) heap_init: Initializing. RAM available for dynamic allocation:
+I (489) heap_init: At 3FCA14A0 len 00048270 (288 KiB): RAM
+I (494) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
+I (499) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
+I (504) heap_init: At 600FE11C len 00001ECC (7 KiB): RTCRAM
+I (511) spi_flash: detected chip: generic
+I (513) spi_flash: flash io: dio
+W (516) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header.
+I (530) sleep_gpio: Configure to isolate all GPIO pins in sleep state
+I (535) sleep_gpio: Enable automatic switching of GPIO sleep configuration
+I (542) main_task: Started on CPU0
+I (562) main_task: Calling app_main()
+I (562) ota_example: OTA example app_main start
+I (572) example_connect: Start example_connect.
+I (572) pp: pp rom version: e7ae62f
+I (572) net80211: net80211 rom version: e7ae62f
+I (592) wifi:wifi driver task: 3fcab44c, prio:23, stack:6656, core=0
+I (592) wifi:wifi firmware version: 2d9c351b0
+I (592) wifi:wifi certification version: v7.0
+I (592) wifi:config NVS flash: enabled
+I (592) wifi:config nano formatting: disabled
+I (602) wifi:Init data frame dynamic rx buffer num: 32
+I (602) wifi:Init static rx mgmt buffer num: 5
+I (612) wifi:Init management short buffer num: 32
+I (612) wifi:Init dynamic tx buffer num: 32
+I (612) wifi:Init static tx FG buffer num: 2
+I (622) wifi:Init static rx buffer size: 1600
+I (622) wifi:Init static rx buffer num: 10
+I (632) wifi:Init dynamic rx buffer num: 32
+I (632) wifi_init: rx ba win: 6
+I (632) wifi_init: accept mbox: 6
+I (642) wifi_init: tcpip mbox: 32
+I (642) wifi_init: udp mbox: 6
+I (642) wifi_init: tcp mbox: 6
+I (642) wifi_init: tcp tx win: 5760
+I (652) wifi_init: tcp rx win: 5760
+I (652) wifi_init: tcp mss: 1440
+I (652) wifi_init: WiFi IRAM OP enabled
+I (662) wifi_init: WiFi RX IRAM OP enabled
+I (662) phy_init: phy_version 680,a6008b2,Jun  4 2024,16:41:10
+W (672) phy_init: failed to load RF calibration data (0x1102), falling back to full calibration
+W (702) phy_init: saving new calibration data because of checksum failure, mode(2)
+I (722) wifi:mode : sta (68:b6:b3:4d:91:08)
+I (722) wifi:enable tsf
+I (722) example_connect: Please input ssid password:
+I (752) example_connect: Connecting to myssid...
+W (752) wifi:Password length matches WPA2 standards, authmode threshold changes from OPEN to WPA2
+I (762) example_connect: Waiting for IP(s)
+I (3592) wifi:new:<2,1>, old:<1,0>, ap:<255,255>, sta:<2,1>, prof:1, snd_ch_cfg:0x0
+I (3592) wifi:state: init -> auth (0xb0)
+I (3592) wifi:state: auth -> assoc (0x0)
+I (3602) wifi:state: assoc -> run (0x10)
+I (3622) wifi:connected with myssid, aid = 3, channel 2, 40U, bssid = 22:d8:d0:45:23:7a
+I (3622) wifi:security: WPA2-PSK, phy: bgn, rssi: -15
+I (3622) wifi:pm start, type: 1
+
+I (3632) wifi:dp: 1, bi: 102400, li: 3, scale listen interval from 307200 us to 307200 us
+I (3632) wifi:set rx beacon pti, rx_bcn_pti: 0, bcn_timeout: 25000, mt_pti: 0, mt_time: 10000
+I (3722) wifi:AP's beacon interval = 102400 us, DTIM period = 1
+I (4722) esp_netif_handlers: example_netif_sta ip: 192.168.3.26, mask: 255.255.255.0, gw: 192.168.3.1
+I (4722) example_connect: Got IPv4 event: Interface "example_netif_sta" address: 192.168.3.26
+I (4732) example_common: Connected to example_netif_sta
+I (4732) example_common: - IPv4 address: 192.168.3.26,
+I (4742) wifi:Set ps type: 0, coexist: 0
+
+I (4742) ota_example: Starting OTA example task
+I (4742) ota_example: Bind interface name is st1
+I (4752) main_task: Returned from app_main()
+I (4762) ota_example: Attempting to download update from https://192.168.3.9:8000/partitions_ota.bin
+I (4782) wifi:<ba-add>idx:0 (ifx:0, 22:d8:d0:45:23:7a), tid:0, ssn:1, winSize:64
+I (4812) esp-x509-crt-bundle: Certificate validated
+I (5142) esp_https_ota: Starting OTA...
+I (5142) esp_https_ota: Writing to <ota_1> partition at offset 0x1d0000
+I (29702) esp_image: segment 0: paddr=001d0020 vaddr=3c090020 size=24288h (148104) map
+I (29722) esp_image: segment 1: paddr=001f42b0 vaddr=3fc98900 size=04970h ( 18800) 
+I (29732) esp_image: segment 2: paddr=001f8c28 vaddr=40374000 size=073f0h ( 29680) 
+I (29732) esp_image: segment 3: paddr=00200020 vaddr=42000020 size=8fc00h (588800) map
+I (29822) esp_image: segment 4: paddr=0028fc28 vaddr=4037b3f0 size=0d4ach ( 54444) 
+I (29832) esp_image: segment 5: paddr=0029d0dc vaddr=600fe100 size=0001ch (    28) 
+I (29832) esp_image: Verifying image signature...
+I (29842) secure_boot_v2: Take trusted digest key(s) from running app
+I (29852) secure_boot_v2: #0 app key digest == #0 trusted key digest
+I (29852) secure_boot_v2: Verifying with RSA-PSS...
+I (29912) secure_boot_v2_rsa: Signature verified successfully!
+I (29912) esp_image: segment 0: paddr=001d0020 vaddr=3c090020 size=24288h (148104) map
+I (29932) esp_image: segment 1: paddr=001f42b0 vaddr=3fc98900 size=04970h ( 18800) 
+I (29942) esp_image: segment 2: paddr=001f8c28 vaddr=40374000 size=073f0h ( 29680) 
+I (29942) esp_image: segment 3: paddr=00200020 vaddr=42000020 size=8fc00h (588800) map
+I (30032) esp_image: segment 4: paddr=0028fc28 vaddr=4037b3f0 size=0d4ach ( 54444) 
+I (30042) esp_image: segment 5: paddr=0029d0dc vaddr=600fe100 size=0001ch (    28) 
+I (30042) esp_image: Verifying image signature...
+I (30042) secure_boot_v2: Take trusted digest key(s) from running app
+I (30062) secure_boot_v2: #0 app key digest == #0 trusted key digest
+I (30062) secure_boot_v2: Verifying with RSA-PSS...
+I (30122) secure_boot_v2_rsa: Signature verified successfully!
+I (30292) ota_example: OTA Succeed, Rebooting...
+I (30292) wifi:state: run -> init (0x0)
+I (30292) wifi:pm stop, total sleep time: 737814 us / 26659208 us
+
+I (30292) wifi:<ba-del>idx:0, tid:0
+I (30302) wifi:new:<2,0>, old:<2,1>, ap:<255,255>, sta:<2,1>, prof:1, snd_ch_cfg:0x0
+I (30352) wifi:flush txq
+I (30352) wifi:stop sw txq
+I (30352) wifi:lmac stop hw txq
+I (30352) wifi:Deinit lldesc rx mblock:10
+
+ESP-ROM:esp32s3-20210327
+Build:Mar 27 2021
+rst:0xc (RTC_SW_CPU_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
+Saved PC:0x40376c31
+SPIWP:0xee
+mode:DIO, clock div:1
+load:0x3fce2820,len:0x15a0
+load:0x403c8700,len:0x4
+load:0x403c8704,len:0xd20
+load:0x403cb700,len:0x2f3c
+entry 0x403c8928
+I (31) boot: ESP-IDF 95a1e4cd 2nd stage bootloader
+I (31) boot: compile time Oct 28 2024 15:26:41
+I (31) boot: Multicore bootloader
+I (32) boot: chip revision: v0.1
+I (34) boot: efuse block revision: v1.2
+I (38) boot.esp32s3: Boot SPI Speed : 80MHz
+I (42) boot.esp32s3: SPI Mode       : DIO
+I (46) boot.esp32s3: SPI Flash Size : 4MB
+I (49) boot: Enabling RNG early entropy source...
+I (54) boot: Partition Table:
+I (56) boot: ## Label            Usage          Type ST Offset   Length
+I (63) boot:  0 nvs              WiFi data        01 02 0000d000 00006000
+I (69) boot:  1 nvs_key          NVS keys         01 04 00013000 00001000
+I (76) boot:  2 storage          Unknown data     01 06 00014000 00001000
+I (82) boot:  3 otadata          OTA data         01 00 00015000 00002000
+I (89) boot:  4 phy_init         RF data          01 01 00017000 00001000
+I (95) boot:  5 emul_efuse       efuse            01 05 00018000 00002000
+I (102) boot:  6 ota_0            OTA app          00 10 00020000 001b0000
+I (108) boot:  7 ota_1            OTA app          00 11 001d0000 001b0000
+I (115) boot: End of partition table
+I (118) esp_image: segment 0: paddr=001d0020 vaddr=3c090020 size=24288h (148104) map
+I (152) esp_image: segment 1: paddr=001f42b0 vaddr=3fc98900 size=04970h ( 18800) load
+I (156) esp_image: segment 2: paddr=001f8c28 vaddr=40374000 size=073f0h ( 29680) load
+I (163) esp_image: segment 3: paddr=00200020 vaddr=42000020 size=8fc00h (588800) map
+I (267) esp_image: segment 4: paddr=0028fc28 vaddr=4037b3f0 size=0d4ach ( 54444) load
+I (279) esp_image: segment 5: paddr=0029d0dc vaddr=600fe100 size=0001ch (    28) load
+I (288) boot: Loaded app from partition at offset 0x1d0000
+I (288) boot: Disabling RNG early entropy source...
+I (298) cpu_start: Multicore app
+I (308) cpu_start: Pro cpu start user code
+I (308) cpu_start: cpu freq: 160000000 Hz
+I (308) app_init: Application information:
+I (308) app_init: Project name:     partitions_ota
+I (312) app_init: App version:      95a1e4cd
+I (316) app_init: Compile time:     Oct 28 2024 15:26:38
+I (321) app_init: ELF file SHA256:  0810d7fd3...
+I (326) app_init: ESP-IDF:          95a1e4cd
+I (330) efuse_init: Min chip rev:     v0.0
+I (334) efuse_init: Max chip rev:     v0.99 
+I (338) efuse_init: Chip rev:         v0.1
+I (341) heap_init: Initializing. RAM available for dynamic allocation:
+I (348) heap_init: At 3FCA14A0 len 00048270 (288 KiB): RAM
+I (353) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
+I (358) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
+I (363) heap_init: At 600FE11C len 00001ECC (7 KiB): RTCRAM
+I (370) spi_flash: detected chip: generic
+I (372) spi_flash: flash io: dio
+W (375) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header.
+I (389) sleep_gpio: Configure to isolate all GPIO pins in sleep state
+I (394) sleep_gpio: Enable automatic switching of GPIO sleep configuration
+I (401) main_task: Started on CPU0
+I (421) main_task: Calling app_main()
+I (421) ota_example: OTA example app_main start
+I (431) example_connect: Start example_connect.
+I (431) pp: pp rom version: e7ae62f
+I (431) net80211: net80211 rom version: e7ae62f
+I (441) wifi:wifi driver task: 3fcab48c, prio:23, stack:6656, core=0
+I (441) wifi:wifi firmware version: 2d9c351b0
+I (441) wifi:wifi certification version: v7.0
+I (451) wifi:config NVS flash: enabled
+I (451) wifi:config nano formatting: disabled
+I (451) wifi:Init data frame dynamic rx buffer num: 32
+I (461) wifi:Init static rx mgmt buffer num: 5
+I (461) wifi:Init management short buffer num: 32
+I (471) wifi:Init dynamic tx buffer num: 32
+I (471) wifi:Init static tx FG buffer num: 2
+I (471) wifi:Init static rx buffer size: 1600
+I (481) wifi:Init static rx buffer num: 10
+I (481) wifi:Init dynamic rx buffer num: 32
+I (491) wifi_init: rx ba win: 6
+I (491) wifi_init: accept mbox: 6
+I (491) wifi_init: tcpip mbox: 32
+I (501) wifi_init: udp mbox: 6
+I (501) wifi_init: tcp mbox: 6
+I (501) wifi_init: tcp tx win: 5760
+I (501) wifi_init: tcp rx win: 5760
+I (511) wifi_init: tcp mss: 1440
+I (511) wifi_init: WiFi IRAM OP enabled
+I (511) wifi_init: WiFi RX IRAM OP enabled
+I (521) phy_init: phy_version 680,a6008b2,Jun  4 2024,16:41:10
+I (561) wifi:mode : sta (68:b6:b3:4d:91:08)
+I (561) wifi:enable tsf
+I (561) example_connect: Please input ssid password:
+I (611) example_connect: Connecting to myssid...
+W (611) wifi:Password length matches WPA2 standards, authmode threshold changes from OPEN to WPA2
+I (611) example_connect: Waiting for IP(s)
+I (3441) wifi:new:<2,1>, old:<1,0>, ap:<255,255>, sta:<2,1>, prof:1, snd_ch_cfg:0x0
+I (3441) wifi:state: init -> auth (0xb0)
+I (3451) wifi:state: auth -> assoc (0x0)
+I (3451) wifi:state: assoc -> run (0x10)
+I (3471) wifi:connected with myssid, aid = 3, channel 2, 40U, bssid = 22:d8:d0:45:23:7a
+I (3471) wifi:security: WPA2-PSK, phy: bgn, rssi: -15
+I (3471) wifi:pm start, type: 1
+
+I (3491) wifi:dp: 1, bi: 102400, li: 3, scale listen interval from 307200 us to 307200 us
+I (3491) wifi:set rx beacon pti, rx_bcn_pti: 0, bcn_timeout: 25000, mt_pti: 0, mt_time: 10000
+I (3571) wifi:AP's beacon interval = 102400 us, DTIM period = 1
+I (4591) esp_netif_handlers: example_netif_sta ip: 192.168.3.26, mask: 255.255.255.0, gw: 192.168.3.1
+I (4591) example_connect: Got IPv4 event: Interface "example_netif_sta" address: 192.168.3.26
+I (4601) example_common: Connected to example_netif_sta
+I (4601) example_common: - IPv4 address: 192.168.3.26,
+I (4611) wifi:Set ps type: 0, coexist: 0
+
+I (4611) ota_example: Starting OTA example task
+I (4611) ota_example: Bind interface name is st1
+I (4621) main_task: Returned from app_main()
+I (4671) ota_example: Attempting to download update from https://192.168.3.9:8000/bootloader/bootloader.bin
+I (4671) ota_example: Use <PrimaryBTLDR> partition (0x00000000)
+I (4701) wifi:<ba-add>idx:0 (ifx:0, 22:d8:d0:45:23:7a), tid:0, ssn:1, winSize:64
+I (4731) esp-x509-crt-bundle: Certificate validated
+I (5061) esp_https_ota: Starting OTA...
+I (5061) esp_https_ota: Writing to <ota_0> partition at offset 0x20000
+I (5061) esp_ota_ops: Staging partition - <ota_0>. Final partition - <PrimaryBTLDR>.
+I (5071) esp_image: Bootloader offsets for PRIMARY: 0x0, Secondary: 0x20000
+I (6121) esp_image: segment 0: paddr=00020020 vaddr=3fce2820 size=015a0h (  5536) 
+I (6121) esp_image: segment 1: paddr=000215c8 vaddr=403c8700 size=00004h (     4) 
+I (6131) esp_image: segment 2: paddr=000215d4 vaddr=403c8704 size=00d20h (  3360) 
+I (6131) esp_image: segment 3: paddr=000222fc vaddr=403cb700 size=02f3ch ( 12092) 
+I (6151) esp_image: Bootloader offsets for PRIMARY: 0x0, Secondary: 0x0
+W (6151) ota_example: Ensure stable power supply! Loss of power at this stage leads to a chip bricking
+I (6151) ota_example: Copy from <ota_0> staging partition to <PrimaryBTLDR>...
+I (7801) ota_example: OTA Succeed, Rebooting...
+I (7801) wifi:state: run -> init (0x0)
+I (7801) wifi:pm stop, total sleep time: 742270 us / 4318054 us
+
+I (7801) wifi:<ba-del>idx:0, tid:0
+I (7821) wifi:new:<2,0>, old:<2,1>, ap:<255,255>, sta:<2,1>, prof:1, snd_ch_cfg:0x0
+I (7831) wifi:flush txq
+I (7831) wifi:stop sw txq
+I (7831) wifi:lmac stop hw txq
+I (7831) wifi:Deinit lldesc rx mblock:10
+
+ESP-ROM:esp32s3-20210327
+Build:Mar 27 2021
+rst:0xc (RTC_SW_CPU_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
+Saved PC:0x40376c31
+SPIWP:0xee
+mode:DIO, clock div:1
+load:0x3fce2820,len:0x15a0
+load:0x403c8700,len:0x4
+load:0x403c8704,len:0xd20
+load:0x403cb700,len:0x2f3c
+entry 0x403c8928
+I (31) boot: ESP-IDF 95a1e4cd 2nd stage bootloader
+I (31) boot: compile time Oct 28 2024 15:26:41
+I (31) boot: Multicore bootloader
+I (32) boot: chip revision: v0.1
+I (34) boot: efuse block revision: v1.2
+I (38) boot.esp32s3: Boot SPI Speed : 80MHz
+I (42) boot.esp32s3: SPI Mode       : DIO
+I (46) boot.esp32s3: SPI Flash Size : 4MB
+I (49) boot: Enabling RNG early entropy source...
+I (54) boot: Partition Table:
+I (56) boot: ## Label            Usage          Type ST Offset   Length
+I (63) boot:  0 nvs              WiFi data        01 02 0000d000 00006000
+I (69) boot:  1 nvs_key          NVS keys         01 04 00013000 00001000
+I (76) boot:  2 storage          Unknown data     01 06 00014000 00001000
+I (82) boot:  3 otadata          OTA data         01 00 00015000 00002000
+I (89) boot:  4 phy_init         RF data          01 01 00017000 00001000
+I (95) boot:  5 emul_efuse       efuse            01 05 00018000 00002000
+I (102) boot:  6 ota_0            OTA app          00 10 00020000 001b0000
+I (108) boot:  7 ota_1            OTA app          00 11 001d0000 001b0000
+I (115) boot: End of partition table
+I (118) esp_image: segment 0: paddr=001d0020 vaddr=3c090020 size=24288h (148104) map
+I (152) esp_image: segment 1: paddr=001f42b0 vaddr=3fc98900 size=04970h ( 18800) load
+I (156) esp_image: segment 2: paddr=001f8c28 vaddr=40374000 size=073f0h ( 29680) load
+I (163) esp_image: segment 3: paddr=00200020 vaddr=42000020 size=8fc00h (588800) map
+I (267) esp_image: segment 4: paddr=0028fc28 vaddr=4037b3f0 size=0d4ach ( 54444) load
+I (279) esp_image: segment 5: paddr=0029d0dc vaddr=600fe100 size=0001ch (    28) load
+I (288) boot: Loaded app from partition at offset 0x1d0000
+I (288) boot: Disabling RNG early entropy source...
+I (298) cpu_start: Multicore app
+I (308) cpu_start: Pro cpu start user code
+I (308) cpu_start: cpu freq: 160000000 Hz
+I (308) app_init: Application information:
+I (308) app_init: Project name:     partitions_ota
+I (312) app_init: App version:      95a1e4cd
+I (316) app_init: Compile time:     Oct 28 2024 15:26:38
+I (321) app_init: ELF file SHA256:  0810d7fd3...
+I (326) app_init: ESP-IDF:          95a1e4cd
+I (330) efuse_init: Min chip rev:     v0.0
+I (334) efuse_init: Max chip rev:     v0.99 
+I (338) efuse_init: Chip rev:         v0.1
+I (341) heap_init: Initializing. RAM available for dynamic allocation:
+I (348) heap_init: At 3FCA14A0 len 00048270 (288 KiB): RAM
+I (353) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
+I (358) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
+I (363) heap_init: At 600FE11C len 00001ECC (7 KiB): RTCRAM
+I (370) spi_flash: detected chip: generic
+I (372) spi_flash: flash io: dio
+W (375) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header.
+I (389) sleep_gpio: Configure to isolate all GPIO pins in sleep state
+I (394) sleep_gpio: Enable automatic switching of GPIO sleep configuration
+I (401) main_task: Started on CPU0
+I (421) main_task: Calling app_main()
+I (421) ota_example: OTA example app_main start
+I (431) example_connect: Start example_connect.
+I (431) pp: pp rom version: e7ae62f
+I (431) net80211: net80211 rom version: e7ae62f
+I (441) wifi:wifi driver task: 3fcab48c, prio:23, stack:6656, core=0
+I (441) wifi:wifi firmware version: 2d9c351b0
+I (441) wifi:wifi certification version: v7.0
+I (451) wifi:config NVS flash: enabled
+I (451) wifi:config nano formatting: disabled
+I (451) wifi:Init data frame dynamic rx buffer num: 32
+I (461) wifi:Init static rx mgmt buffer num: 5
+I (461) wifi:Init management short buffer num: 32
+I (471) wifi:Init dynamic tx buffer num: 32
+I (471) wifi:Init static tx FG buffer num: 2
+I (471) wifi:Init static rx buffer size: 1600
+I (481) wifi:Init static rx buffer num: 10
+I (481) wifi:Init dynamic rx buffer num: 32
+I (491) wifi_init: rx ba win: 6
+I (491) wifi_init: accept mbox: 6
+I (491) wifi_init: tcpip mbox: 32
+I (501) wifi_init: udp mbox: 6
+I (501) wifi_init: tcp mbox: 6
+I (501) wifi_init: tcp tx win: 5760
+I (501) wifi_init: tcp rx win: 5760
+I (511) wifi_init: tcp mss: 1440
+I (511) wifi_init: WiFi IRAM OP enabled
+I (511) wifi_init: WiFi RX IRAM OP enabled
+I (521) phy_init: phy_version 680,a6008b2,Jun  4 2024,16:41:10
+I (561) wifi:mode : sta (68:b6:b3:4d:91:08)
+I (561) wifi:enable tsf
+I (561) example_connect: Please input ssid password:
+I (601) example_connect: Connecting to myssid...
+W (601) wifi:Password length matches WPA2 standards, authmode threshold changes from OPEN to WPA2
+I (601) example_connect: Waiting for IP(s)
+I (3431) wifi:new:<2,1>, old:<1,0>, ap:<255,255>, sta:<2,1>, prof:1, snd_ch_cfg:0x0
+I (3431) wifi:state: init -> auth (0xb0)
+I (3431) wifi:state: auth -> assoc (0x0)
+I (3441) wifi:state: assoc -> run (0x10)
+I (3461) wifi:connected with myssid, aid = 1, channel 2, 40U, bssid = 22:d8:d0:45:23:7a
+I (3461) wifi:security: WPA2-PSK, phy: bgn, rssi: -15
+I (3461) wifi:pm start, type: 1
+
+I (3471) wifi:dp: 1, bi: 102400, li: 3, scale listen interval from 307200 us to 307200 us
+I (3471) wifi:set rx beacon pti, rx_bcn_pti: 0, bcn_timeout: 25000, mt_pti: 0, mt_time: 10000
+I (3511) wifi:AP's beacon interval = 102400 us, DTIM period = 1
+I (4571) esp_netif_handlers: example_netif_sta ip: 192.168.3.26, mask: 255.255.255.0, gw: 192.168.3.1
+I (4571) example_connect: Got IPv4 event: Interface "example_netif_sta" address: 192.168.3.26
+I (4581) example_common: Connected to example_netif_sta
+I (4581) example_common: - IPv4 address: 192.168.3.26,
+I (4591) wifi:Set ps type: 0, coexist: 0
+
+I (4591) ota_example: Starting OTA example task
+I (4591) ota_example: Bind interface name is st1
+I (4601) main_task: Returned from app_main()
+I (4621) ota_example: Attempting to download update from https://192.168.3.9:8000/partition_table/partition-table.bin
+I (4631) ota_example: Use <PrimaryPrtTable> partition (0x0000c000)
+I (4651) wifi:<ba-add>idx:0 (ifx:0, 22:d8:d0:45:23:7a), tid:0, ssn:1, winSize:64
+I (4681) esp-x509-crt-bundle: Certificate validated
+I (5021) esp_https_ota: Starting OTA...
+I (5021) esp_https_ota: Writing to <ota_0> partition at offset 0x20000
+I (5021) esp_ota_ops: Staging partition - <ota_0>. Final partition - <PrimaryPrtTable>.
+W (5181) ota_example: Ensure stable power supply! Loss of power at this stage leads to a chip bricking.
+I (5181) ota_example: Copy from <ota_0> staging partition to <PrimaryPrtTable>...
+I (5261) ota_example: OTA Succeed, Rebooting...
+I (5261) wifi:state: run -> init (0x0)
+I (5261) wifi:pm stop, total sleep time: 715566 us / 1792923 us
+
+I (5261) wifi:<ba-del>idx:0, tid:0
+I (5281) wifi:new:<2,0>, old:<2,1>, ap:<255,255>, sta:<2,1>, prof:1, snd_ch_cfg:0x0
+I (5291) wifi:flush txq
+I (5291) wifi:stop sw txq
+I (5291) wifi:lmac stop hw txq
+I (5291) wifi:Deinit lldesc rx mblock:10
+
+ESP-ROM:esp32s3-20210327
+Build:Mar 27 2021
+rst:0xc (RTC_SW_CPU_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
+Saved PC:0x40376c31
+SPIWP:0xee
+mode:DIO, clock div:1
+load:0x3fce2820,len:0x15a0
+load:0x403c8700,len:0x4
+load:0x403c8704,len:0xd20
+load:0x403cb700,len:0x2f3c
+entry 0x403c8928
+I (31) boot: ESP-IDF 95a1e4cd 2nd stage bootloader
+I (31) boot: compile time Oct 28 2024 15:26:41
+I (31) boot: Multicore bootloader
+I (32) boot: chip revision: v0.1
+I (34) boot: efuse block revision: v1.2
+I (38) boot.esp32s3: Boot SPI Speed : 80MHz
+I (42) boot.esp32s3: SPI Mode       : DIO
+I (46) boot.esp32s3: SPI Flash Size : 4MB
+I (49) boot: Enabling RNG early entropy source...
+I (54) boot: Partition Table:
+I (56) boot: ## Label            Usage          Type ST Offset   Length
+I (63) boot:  0 nvs              WiFi data        01 02 0000d000 00006000
+I (69) boot:  1 nvs_key          NVS keys         01 04 00013000 00001000
+I (76) boot:  2 storage          Unknown data     01 06 00014000 00001000
+I (82) boot:  3 otadata          OTA data         01 00 00015000 00002000
+I (89) boot:  4 phy_init         RF data          01 01 00017000 00001000
+I (95) boot:  5 emul_efuse       efuse            01 05 00018000 00002000
+I (102) boot:  6 ota_0            OTA app          00 10 00020000 001b0000
+I (108) boot:  7 ota_1            OTA app          00 11 001d0000 001b0000
+I (115) boot: End of partition table
+I (118) esp_image: segment 0: paddr=001d0020 vaddr=3c090020 size=24288h (148104) map
+I (152) esp_image: segment 1: paddr=001f42b0 vaddr=3fc98900 size=04970h ( 18800) load
+I (156) esp_image: segment 2: paddr=001f8c28 vaddr=40374000 size=073f0h ( 29680) load
+I (163) esp_image: segment 3: paddr=00200020 vaddr=42000020 size=8fc00h (588800) map
+I (267) esp_image: segment 4: paddr=0028fc28 vaddr=4037b3f0 size=0d4ach ( 54444) load
+I (279) esp_image: segment 5: paddr=0029d0dc vaddr=600fe100 size=0001ch (    28) load
+I (288) boot: Loaded app from partition at offset 0x1d0000
+I (288) boot: Disabling RNG early entropy source...
+I (298) cpu_start: Multicore app
+I (308) cpu_start: Pro cpu start user code
+I (308) cpu_start: cpu freq: 160000000 Hz
+I (308) app_init: Application information:
+I (308) app_init: Project name:     partitions_ota
+I (312) app_init: App version:      95a1e4cd
+I (316) app_init: Compile time:     Oct 28 2024 15:26:38
+I (321) app_init: ELF file SHA256:  0810d7fd3...
+I (326) app_init: ESP-IDF:          95a1e4cd
+I (330) efuse_init: Min chip rev:     v0.0
+I (334) efuse_init: Max chip rev:     v0.99 
+I (338) efuse_init: Chip rev:         v0.1
+I (341) heap_init: Initializing. RAM available for dynamic allocation:
+I (348) heap_init: At 3FCA14A0 len 00048270 (288 KiB): RAM
+I (353) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
+I (358) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
+I (363) heap_init: At 600FE11C len 00001ECC (7 KiB): RTCRAM
+I (370) spi_flash: detected chip: generic
+I (372) spi_flash: flash io: dio
+W (375) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header.
+I (389) sleep_gpio: Configure to isolate all GPIO pins in sleep state
+I (394) sleep_gpio: Enable automatic switching of GPIO sleep configuration
+I (401) main_task: Started on CPU0
+I (421) main_task: Calling app_main()
+I (421) ota_example: OTA example app_main start
+I (431) example_connect: Start example_connect.
+I (431) pp: pp rom version: e7ae62f
+I (431) net80211: net80211 rom version: e7ae62f
+I (441) wifi:wifi driver task: 3fcab48c, prio:23, stack:6656, core=0
+I (441) wifi:wifi firmware version: 2d9c351b0
+I (441) wifi:wifi certification version: v7.0
+I (451) wifi:config NVS flash: enabled
+I (451) wifi:config nano formatting: disabled
+I (451) wifi:Init data frame dynamic rx buffer num: 32
+I (461) wifi:Init static rx mgmt buffer num: 5
+I (461) wifi:Init management short buffer num: 32
+I (471) wifi:Init dynamic tx buffer num: 32
+I (471) wifi:Init static tx FG buffer num: 2
+I (471) wifi:Init static rx buffer size: 1600
+I (481) wifi:Init static rx buffer num: 10
+I (481) wifi:Init dynamic rx buffer num: 32
+I (491) wifi_init: rx ba win: 6
+I (491) wifi_init: accept mbox: 6
+I (491) wifi_init: tcpip mbox: 32
+I (501) wifi_init: udp mbox: 6
+I (501) wifi_init: tcp mbox: 6
+I (501) wifi_init: tcp tx win: 5760
+I (501) wifi_init: tcp rx win: 5760
+I (511) wifi_init: tcp mss: 1440
+I (511) wifi_init: WiFi IRAM OP enabled
+I (511) wifi_init: WiFi RX IRAM OP enabled
+I (521) phy_init: phy_version 680,a6008b2,Jun  4 2024,16:41:10
+I (561) wifi:mode : sta (68:b6:b3:4d:91:08)
+I (561) wifi:enable tsf
+I (561) example_connect: Please input ssid password:
+I (591) example_connect: Connecting to myssid...
+W (591) wifi:Password length matches WPA2 standards, authmode threshold changes from OPEN to WPA2
+I (591) example_connect: Waiting for IP(s)
+I (3421) wifi:new:<2,1>, old:<1,0>, ap:<255,255>, sta:<2,1>, prof:1, snd_ch_cfg:0x0
+I (3421) wifi:state: init -> auth (0xb0)
+I (3431) wifi:state: auth -> assoc (0x0)
+I (3431) wifi:state: assoc -> run (0x10)
+I (3451) wifi:connected with myssid, aid = 1, channel 2, 40U, bssid = 22:d8:d0:45:23:7a
+I (3451) wifi:security: WPA2-PSK, phy: bgn, rssi: -15
+I (3451) wifi:pm start, type: 1
+
+I (3461) wifi:dp: 1, bi: 102400, li: 3, scale listen interval from 307200 us to 307200 us
+I (3461) wifi:set rx beacon pti, rx_bcn_pti: 0, bcn_timeout: 25000, mt_pti: 0, mt_time: 10000
+I (3541) wifi:AP's beacon interval = 102400 us, DTIM period = 1
+I (4551) esp_netif_handlers: example_netif_sta ip: 192.168.3.26, mask: 255.255.255.0, gw: 192.168.3.1
+I (4551) example_connect: Got IPv4 event: Interface "example_netif_sta" address: 192.168.3.26
+I (4561) example_common: Connected to example_netif_sta
+I (4561) example_common: - IPv4 address: 192.168.3.26,
+I (4571) wifi:Set ps type: 0, coexist: 0
+
+I (4571) ota_example: Starting OTA example task
+I (4571) ota_example: Bind interface name is st1
+I (4581) main_task: Returned from app_main()
+I (4601) ota_example: Attempting to download update from https://192.168.3.9:8000/storage.bin
+I (4621) wifi:<ba-add>idx:0 (ifx:0, 22:d8:d0:45:23:7a), tid:0, ssn:1, winSize:64
+I (4641) esp-x509-crt-bundle: Certificate validated
+I (4981) esp_https_ota: Starting OTA...
+I (4981) esp_https_ota: Writing to <ota_0> partition at offset 0x20000
+I (4981) esp_ota_ops: Staging partition - <ota_0>. Final partition - <storage>.
+I (5161) esp_ota_ops: Copy from <ota_0> staging partition to <storage>...
+I (5351) ota_example: 7296406769363431
+I (5351) ota_example: OTA Succeed, Rebooting...
+I (5361) wifi:state: run -> init (0x0)
+I (5361) wifi:pm stop, total sleep time: 772888 us / 1893437 us
+
+I (5371) wifi:<ba-del>idx:0, tid:0
+I (5371) wifi:new:<2,0>, old:<2,1>, ap:<255,255>, sta:<2,1>, prof:1, snd_ch_cfg:0x0
+```
\ No newline at end of file
diff --git a/examples/system/ota/partitions_ota/conftest.py b/examples/system/ota/partitions_ota/conftest.py
new file mode 100644
index 00000000000..f5c1a8860f2
--- /dev/null
+++ b/examples/system/ota/partitions_ota/conftest.py
@@ -0,0 +1,64 @@
+# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Apache-2.0
+import logging
+import os
+
+import pytest
+from _pytest.fixtures import FixtureRequest
+from _pytest.monkeypatch import MonkeyPatch
+from pytest_embedded_idf.app import FlashFile
+from pytest_embedded_idf.serial import IdfSerial
+
+
+# This is a custom IdfSerial class to support custom functionality
+# which is required only for this test
+class EfuseFlashEncSerial(IdfSerial):
+
+    @IdfSerial.use_esptool()
+    def write_flash_no_enc(self) -> None:
+        self.app.flash_settings['encrypt'] = False
+        flash_files = []
+        for file in self.app.flash_files:
+            # Set encrypted flag to false for each file.
+            flash_files.append(file._replace(encrypted=False))
+        # Replace the original tuple with modified tuple with all the files marked as unencrypted.
+        self.app.flash_files = tuple(flash_files)
+        # Now flash the files
+        self.flash()
+
+    def bootloader_flash(self) -> None:
+        """
+        Flash bootloader.
+
+        :return: None
+        """
+        logging.info('Flashing bootloader')
+        bootloader_path = os.path.join(self.app.binary_path, 'bootloader', 'bootloader.bin')
+        offs = int(self.app.sdkconfig.get('BOOTLOADER_OFFSET_IN_FLASH', 0))
+        logging.info('bootloader offset is {0}'.format(hex(offs)))
+        prev_flash_files = self.app.flash_files
+        flash_files = []
+        flash_files.append(
+            FlashFile(
+                offs,
+                bootloader_path,
+                False,
+            )
+        )
+        self.app.flash_files = flash_files
+        self.app.flash_settings['encrypt'] = False
+        self.flash()
+        # Restore self.app.flash files to original value
+        self.app.flash_files = prev_flash_files
+
+
+@pytest.fixture(scope='module')
+def monkeypatch_module(request: FixtureRequest) -> MonkeyPatch:
+    mp = MonkeyPatch()
+    request.addfinalizer(mp.undo)
+    return mp
+
+
+@pytest.fixture(scope='module', autouse=True)
+def replace_dut_class(monkeypatch_module: MonkeyPatch) -> None:
+    monkeypatch_module.setattr('pytest_embedded_idf.IdfSerial', EfuseFlashEncSerial)
diff --git a/examples/system/ota/partitions_ota/main/CMakeLists.txt b/examples/system/ota/partitions_ota/main/CMakeLists.txt
new file mode 100644
index 00000000000..95a0b79929a
--- /dev/null
+++ b/examples/system/ota/partitions_ota/main/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Embed the server root certificate into the final binary
+idf_build_get_property(project_dir PROJECT_DIR)
+idf_component_register(SRC_DIRS "."
+                        INCLUDE_DIRS "."
+                        EMBED_TXTFILES ${project_dir}/server_certs/ca_cert.pem)
diff --git a/examples/system/ota/partitions_ota/main/Kconfig.projbuild b/examples/system/ota/partitions_ota/main/Kconfig.projbuild
new file mode 100644
index 00000000000..77681a9a492
--- /dev/null
+++ b/examples/system/ota/partitions_ota/main/Kconfig.projbuild
@@ -0,0 +1,54 @@
+menu "Example Configuration"
+
+    config EXAMPLE_FIRMWARE_UPGRADE_URL
+        string "firmware upgrade url endpoint"
+        default "https://192.168.0.3:8070/partitions_ota.bin"
+        help
+            URL of server which hosts the firmware
+            image.
+
+    config EXAMPLE_USE_CERT_BUNDLE
+        bool "Enable certificate bundle"
+        default y
+        depends on MBEDTLS_CERTIFICATE_BUNDLE
+        help
+            Enable trusted root certificate bundle. This approach allows to have
+            OTA updates functional with any public server without requirement
+            to explicitly add its server certificate.
+
+    config EXAMPLE_FIRMWARE_UPGRADE_URL_FROM_STDIN
+        bool
+        default y if EXAMPLE_FIRMWARE_UPGRADE_URL = "FROM_STDIN"
+
+    config EXAMPLE_SKIP_COMMON_NAME_CHECK
+        bool "Skip server certificate CN fieldcheck"
+        default n
+        help
+            This allows you to skip the validation of OTA server certificate CN field.
+
+    config EXAMPLE_FIRMWARE_UPGRADE_BIND_IF
+        bool "Support firmware upgrade bind specified interface"
+        default n
+        help
+            This allows you to bind specified interface in OTA example.
+
+    choice EXAMPLE_FIRMWARE_UPGRADE_BIND_IF_TYPE
+        prompt "Choose OTA data bind interface"
+        default EXAMPLE_FIRMWARE_UPGRADE_BIND_IF_STA
+        depends on EXAMPLE_FIRMWARE_UPGRADE_BIND_IF
+        help
+            Select which interface type of OTA data go through.
+
+        config EXAMPLE_FIRMWARE_UPGRADE_BIND_IF_STA
+            bool "Bind wifi station interface"
+            depends on EXAMPLE_CONNECT_WIFI
+            help
+                Select wifi station interface to pass the OTA data.
+
+        config EXAMPLE_FIRMWARE_UPGRADE_BIND_IF_ETH
+            bool "Bind ethernet interface"
+            depends on EXAMPLE_CONNECT_ETHERNET
+            help
+                Select ethernet interface to pass the OTA data.
+    endchoice
+endmenu
diff --git a/examples/system/ota/partitions_ota/main/app_main.c b/examples/system/ota/partitions_ota/main/app_main.c
new file mode 100644
index 00000000000..b77d85b0c0f
--- /dev/null
+++ b/examples/system/ota/partitions_ota/main/app_main.c
@@ -0,0 +1,268 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+/* OTA partitions example
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "esp_system.h"
+#include "esp_event.h"
+#include "esp_log.h"
+#include "esp_ota_ops.h"
+#include "esp_http_client.h"
+#include "esp_https_ota.h"
+#include "protocol_examples_common.h"
+#include "string.h"
+#ifdef CONFIG_EXAMPLE_USE_CERT_BUNDLE
+#include "esp_crt_bundle.h"
+#endif
+#include "esp_flash.h"
+#include "esp_flash_partitions.h"
+#include "esp_partition.h"
+
+#include "nvs.h"
+#include "nvs_flash.h"
+#include "protocol_examples_common.h"
+#include <sys/socket.h>
+#if CONFIG_EXAMPLE_CONNECT_WIFI
+#include "esp_wifi.h"
+#endif
+
+#include "partition_utils.h"
+
+#ifdef CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF
+/* The interface name value can refer to if_desc in esp_netif_defaults.h */
+#if CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF_ETH
+static const char *bind_interface_name = EXAMPLE_NETIF_DESC_ETH;
+#elif CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF_STA
+static const char *bind_interface_name = EXAMPLE_NETIF_DESC_STA;
+#endif
+#endif
+
+static const char *TAG = "ota_example";
+extern const uint8_t server_cert_pem_start[] asm("_binary_ca_cert_pem_start");
+extern const uint8_t server_cert_pem_end[] asm("_binary_ca_cert_pem_end");
+
+#define OTA_URL_SIZE 256
+
+esp_err_t _http_event_handler(esp_http_client_event_t *evt)
+{
+    switch (evt->event_id) {
+    case HTTP_EVENT_ERROR:
+        ESP_LOGD(TAG, "HTTP_EVENT_ERROR");
+        break;
+    case HTTP_EVENT_ON_CONNECTED:
+        ESP_LOGD(TAG, "HTTP_EVENT_ON_CONNECTED");
+        break;
+    case HTTP_EVENT_HEADER_SENT:
+        ESP_LOGD(TAG, "HTTP_EVENT_HEADER_SENT");
+        break;
+    case HTTP_EVENT_ON_HEADER:
+        ESP_LOGD(TAG, "HTTP_EVENT_ON_HEADER, key=%s, value=%s", evt->header_key, evt->header_value);
+        break;
+    case HTTP_EVENT_ON_DATA:
+        ESP_LOGD(TAG, "HTTP_EVENT_ON_DATA, len=%d", evt->data_len);
+        break;
+    case HTTP_EVENT_ON_FINISH:
+        ESP_LOGD(TAG, "HTTP_EVENT_ON_FINISH");
+        break;
+    case HTTP_EVENT_DISCONNECTED:
+        ESP_LOGD(TAG, "HTTP_EVENT_DISCONNECTED");
+        break;
+    case HTTP_EVENT_REDIRECT:
+        ESP_LOGD(TAG, "HTTP_EVENT_REDIRECT");
+        break;
+    }
+    return ESP_OK;
+}
+
+static esp_err_t register_partition(size_t offset, size_t size, const char *label, esp_partition_type_t type, esp_partition_subtype_t subtype, const esp_partition_t **p_partition)
+{
+    // If the partition table contains this partition, then use it, otherwise register it.
+    *p_partition = esp_partition_find_first(type, subtype, NULL);
+    if ((*p_partition) == NULL) {
+        esp_err_t error = esp_partition_register_external(NULL, offset, size, label, type, subtype, p_partition);
+        if (error != ESP_OK) {
+            ESP_LOGE(TAG, "Failed to register %s partition (err=0x%x)", "PrimaryBTLDR", error);
+            return error;
+        }
+    }
+    ESP_LOGI(TAG, "Use <%s> partition (0x%08" PRIx32 ")", (*p_partition)->label, (*p_partition)->address);
+    return ESP_OK;
+}
+
+static esp_err_t ota_update_partitions(esp_https_ota_config_t *ota_config)
+{
+    esp_err_t ret = ESP_ERR_NOT_SUPPORTED;
+    if (strstr(ota_config->http_config->url, "partitions_ota.bin") != NULL) {
+        ret = esp_https_ota(ota_config);
+
+    } else if (strstr(ota_config->http_config->url, "bootloader.bin") != NULL) {
+        const esp_partition_t *primary_bootloader;
+        ESP_ERROR_CHECK(register_partition(ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader));
+        const esp_partition_t *ota_partition = esp_ota_get_next_update_partition(NULL); // free app ota partition will be used for downloading a new image
+#if CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE
+        // Check if the passive OTA app partition is not needed for rollback before using it for other partitions.
+        // The same can be done for partition table and storage updates.
+        esp_ota_img_states_t ota_state;
+        ESP_ERROR_CHECK(esp_ota_get_state_partition(ota_partition, &ota_state));
+        if (ota_state == ESP_OTA_IMG_VALID) {
+            ESP_LOGW(TAG, "Passive OTA app partition <%s> contains a valid app image eligible for rollback.", ota_partition->label);
+            uint32_t ota_bootloader_offset;
+            ESP_ERROR_CHECK(partition_utils_find_unallocated(NULL, ESP_BOOTLOADER_SIZE, ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_SIZE, &ota_bootloader_offset, NULL));
+            ESP_ERROR_CHECK(register_partition(ota_bootloader_offset, ESP_BOOTLOADER_SIZE, "OtaBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_OTA, &ota_partition));
+            ESP_LOGW(TAG, "To avoid overwriting the passive app partition, using the unallocated space on the flash to create a temporary OTA bootloader partition <%s>", ota_partition->label);
+        }
+#endif
+        ota_config->partition.staging = ota_partition;
+        ota_config->partition.final = primary_bootloader;
+        ret = esp_https_ota(ota_config);
+        if (ret == ESP_OK) {
+            ESP_LOGW(TAG, "Ensure stable power supply! Loss of power at this stage leads to a chip bricking");
+            ESP_LOGI(TAG, "Copy from <%s> staging partition to <%s>...", ota_partition->label, primary_bootloader->label);
+            ret = esp_partition_copy(primary_bootloader, 0, ota_partition, 0, primary_bootloader->size);
+            if (ret != ESP_OK) {
+                ESP_LOGE(TAG, "Failed to copy partition to Primary bootloader (err=0x%x). Bootloader likely corrupted. Device will not be able to boot again!", ret);
+            }
+            // If the primary_bootloader already exists in the partition table on flash, it will not be deregistered, and the function will return an error.
+            esp_partition_deregister_external(primary_bootloader);
+        }
+
+    } else if (strstr(ota_config->http_config->url, "partition-table.bin") != NULL) {
+        const esp_partition_t *primary_partition_table;
+        ESP_ERROR_CHECK(register_partition(ESP_PRIMARY_PARTITION_TABLE_OFFSET, ESP_PARTITION_TABLE_SIZE, "PrimaryPrtTable", ESP_PARTITION_TYPE_PARTITION_TABLE, ESP_PARTITION_SUBTYPE_PARTITION_TABLE_PRIMARY, &primary_partition_table));
+        const esp_partition_t *free_app_ota_partition = esp_ota_get_next_update_partition(NULL); // free app ota partition will be used for downloading a new image
+        ota_config->partition.staging = free_app_ota_partition;
+        ota_config->partition.final = primary_partition_table;
+        ota_config->partition.finalize_with_copy = false; // After the download is complete, do not copy the received image to the final partition automatically (it is false by default)
+        ret = esp_https_ota(ota_config);
+        if (ret == ESP_OK) {
+            ESP_LOGW(TAG, "Ensure stable power supply! Loss of power at this stage leads to a chip bricking.");
+            ESP_LOGI(TAG, "Copy from <%s> staging partition to <%s>...", free_app_ota_partition->label, primary_partition_table->label);
+            ret = esp_partition_copy(primary_partition_table, 0, free_app_ota_partition, 0, primary_partition_table->size);
+            if (ret != ESP_OK) {
+                ESP_LOGE(TAG, "Failed to copy partition to Primary partition table (err=0x%x). Partition table likely corrupted. Device will not be able to boot again!", ret);
+            }
+            // If the primary_partition_table already exists in the partition table on flash, it will not be deregistered, and the function will return an error.
+            esp_partition_deregister_external(primary_partition_table);
+        }
+
+    } else if (strstr(ota_config->http_config->url, "storage.bin") != NULL) {
+        ota_config->partition.staging = NULL; // free app ota partition will be selected and used for downloading a new image
+        ota_config->partition.final = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, "storage");
+        assert(ota_config->partition.final != NULL);
+        ota_config->partition.finalize_with_copy = true; // After the download is complete, copy the received image to the final partition automatically
+        ret = esp_https_ota(ota_config);
+        char text[16];
+        ESP_ERROR_CHECK(esp_partition_read(ota_config->partition.final, 0, text, sizeof(text)));
+        ESP_LOG_BUFFER_CHAR(TAG, text, sizeof(text));
+        assert(memcmp("7296406769363431", text, sizeof(text)) == 0);
+
+    } else {
+        ESP_LOGE(TAG, "Unable to load this file (%s). The final partition is unknown.", ota_config->http_config->url);
+    }
+    return ret;
+}
+
+void ota_example_task(void *pvParameter)
+{
+    ESP_LOGI(TAG, "Starting OTA example task");
+#ifdef CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF
+    esp_netif_t *netif = get_example_netif_from_desc(bind_interface_name);
+    if (netif == NULL) {
+        ESP_LOGE(TAG, "Can't find netif from interface description");
+        abort();
+    }
+    struct ifreq ifr;
+    esp_netif_get_netif_impl_name(netif, ifr.ifr_name);
+    ESP_LOGI(TAG, "Bind interface name is %s", ifr.ifr_name);
+#endif
+    esp_http_client_config_t config = {
+        .url = CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL,
+#ifdef CONFIG_EXAMPLE_USE_CERT_BUNDLE
+        .crt_bundle_attach = esp_crt_bundle_attach,
+#else
+        .cert_pem = (char *)server_cert_pem_start,
+#endif /* CONFIG_EXAMPLE_USE_CERT_BUNDLE */
+        .event_handler = _http_event_handler,
+        .keep_alive_enable = true,
+#ifdef CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF
+        .if_name = &ifr,
+#endif
+    };
+
+#ifdef CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL_FROM_STDIN
+    char url_buf[OTA_URL_SIZE];
+    if (strcmp(config.url, "FROM_STDIN") == 0) {
+        example_configure_stdin_stdout();
+        fgets(url_buf, OTA_URL_SIZE, stdin);
+        int len = strlen(url_buf);
+        url_buf[len - 1] = '\0';
+        config.url = url_buf;
+    } else {
+        ESP_LOGE(TAG, "Configuration mismatch: wrong firmware upgrade image url");
+        abort();
+    }
+#endif
+
+#ifdef CONFIG_EXAMPLE_SKIP_COMMON_NAME_CHECK
+    config.skip_cert_common_name_check = true;
+#endif
+
+    esp_https_ota_config_t ota_config = {
+        .http_config = &config,
+    };
+    ESP_LOGI(TAG, "Attempting to download update from %s", config.url);
+    esp_err_t ret = ota_update_partitions(&ota_config);
+    if (ret == ESP_OK) {
+        ESP_LOGI(TAG, "OTA Succeed, Rebooting...");
+        esp_restart();
+    } else {
+        ESP_LOGE(TAG, "Firmware upgrade failed");
+    }
+    while (1) {
+        vTaskDelay(1000 / portTICK_PERIOD_MS);
+    }
+}
+
+void app_main(void)
+{
+    ESP_LOGI(TAG, "OTA example app_main start");
+    // Initialize NVS.
+    esp_err_t err = nvs_flash_init();
+    if (err == ESP_ERR_NVS_NO_FREE_PAGES || err == ESP_ERR_NVS_NEW_VERSION_FOUND) {
+        // 1.OTA app partition table has a smaller NVS partition size than the non-OTA
+        // partition table. This size mismatch may cause NVS initialization to fail.
+        // 2.NVS partition contains data in new format and cannot be recognized by this version of code.
+        // If this happens, we erase NVS partition and initialize NVS again.
+        ESP_ERROR_CHECK(nvs_flash_erase());
+        err = nvs_flash_init();
+    }
+    ESP_ERROR_CHECK(err);
+
+    ESP_ERROR_CHECK(esp_netif_init());
+    ESP_ERROR_CHECK(esp_event_loop_create_default());
+
+    /* This helper function configures Wi-Fi or Ethernet, as selected in menuconfig.
+     * Read "Establishing Wi-Fi or Ethernet Connection" section in
+     * examples/protocols/README.md for more information about this function.
+     */
+    ESP_ERROR_CHECK(example_connect());
+
+#if CONFIG_EXAMPLE_CONNECT_WIFI
+    /* Ensure to disable any WiFi power save mode, this allows best throughput
+     * and hence timings for overall OTA operation.
+     */
+    esp_wifi_set_ps(WIFI_PS_NONE);
+#endif // CONFIG_EXAMPLE_CONNECT_WIFI
+
+    xTaskCreate(&ota_example_task, "ota_example_task", 8192, NULL, 5, NULL);
+}
diff --git a/examples/system/ota/partitions_ota/main/idf_component.yml b/examples/system/ota/partitions_ota/main/idf_component.yml
new file mode 100644
index 00000000000..718194867b7
--- /dev/null
+++ b/examples/system/ota/partitions_ota/main/idf_component.yml
@@ -0,0 +1,3 @@
+dependencies:
+  protocol_examples_common:
+    path: ${IDF_PATH}/examples/common_components/protocol_examples_common
diff --git a/examples/system/ota/partitions_ota/main/partition_utils.c b/examples/system/ota/partitions_ota/main/partition_utils.c
new file mode 100644
index 00000000000..c6dbfe18c94
--- /dev/null
+++ b/examples/system/ota/partitions_ota/main/partition_utils.c
@@ -0,0 +1,118 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <assert.h>
+#include <string.h>
+#include <stdio.h>
+#include <sys/param.h>
+#include "esp_flash_partitions.h"
+#include "esp_flash_internal.h"
+#include "esp_image_format.h"
+#include "esp_flash.h"
+#include "esp_partition.h"
+#include "esp_log.h"
+
+// Returns the number of partitions belonging to the specified flash chip
+static unsigned int count_partitions(esp_flash_t *flash_chip)
+{
+    unsigned int partition_count = 0;
+    esp_partition_iterator_t it = esp_partition_find(ESP_PARTITION_TYPE_ANY, ESP_PARTITION_SUBTYPE_ANY, NULL);
+    assert(it != NULL);
+    for (; it != NULL; it = esp_partition_next(it)) {
+        if (esp_partition_get(it)->flash_chip == flash_chip) {
+            partition_count++;
+        }
+    }
+    esp_partition_iterator_release(it);
+    return partition_count;
+}
+
+// Compare function for qsort to sort partitions by address
+static int compare_partitions(const void *a, const void *b) {
+    const esp_partition_t *part_a = *(const esp_partition_t **)a;
+    const esp_partition_t *part_b = *(const esp_partition_t **)b;
+    return ((int32_t)part_a->address - (int32_t)part_b->address);
+}
+
+static const esp_partition_t **get_sorted_partition_array(esp_flash_t *flash_chip, unsigned int *out_partition_count)
+{
+    // Number of partitions on the flash chip
+    unsigned int partition_count = count_partitions(flash_chip);
+    assert(partition_count != 0);
+    *out_partition_count = partition_count;
+
+    // Allocate an array for copying partitions
+    const esp_partition_t **part_array = (const esp_partition_t **) calloc(partition_count, sizeof(esp_partition_t *));
+    assert(part_array != NULL);
+
+    // Copy partitions to the array
+    unsigned i = 0;
+    esp_partition_iterator_t it = esp_partition_find(ESP_PARTITION_TYPE_ANY, ESP_PARTITION_SUBTYPE_ANY, NULL);
+    assert(it != NULL);
+    for (; it != NULL; it = esp_partition_next(it)) {
+        const esp_partition_t *p = esp_partition_get(it);
+        if (p->flash_chip == flash_chip) {
+            part_array[i++] = p;
+        }
+    }
+    esp_partition_iterator_release(it);
+    assert(i == partition_count);
+
+    // Sort partitions by address using qsort
+    qsort(part_array, partition_count, sizeof(esp_partition_t *), compare_partitions);
+    return part_array;
+}
+
+esp_err_t partition_utils_find_unallocated(esp_flash_t *flash_chip, size_t required_size, uint32_t start_offset, uint32_t *found_offset, size_t *found_size)
+{
+    if (flash_chip == NULL) {
+        flash_chip = esp_flash_default_chip;
+    }
+
+    if (required_size == 0 || found_offset == NULL) {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    // Get a sorted partition array for the given flash chip
+    unsigned int partition_count;
+    const esp_partition_t **sorted_partitions = get_sorted_partition_array(flash_chip, &partition_count);
+    if (sorted_partitions == NULL) {
+        return ESP_ERR_NO_MEM;
+    }
+
+    // Scan for unallocated space between partitions, starting after the start_offset with unused space >= required_size
+    uint32_t last_end_address = start_offset;
+    for (size_t i = 0; i < partition_count; ++i) {
+        if (sorted_partitions[i]->address > start_offset && sorted_partitions[i]->address > last_end_address) {
+            size_t unallocated_size = sorted_partitions[i]->address - last_end_address;
+            if (unallocated_size >= required_size) {
+                *found_offset = last_end_address;
+                if (found_size != NULL) {
+                    *found_size = unallocated_size;
+                }
+                free(sorted_partitions);
+                return ESP_OK;
+            }
+        }
+        last_end_address = sorted_partitions[i]->address + sorted_partitions[i]->size;
+    }
+
+    // Check for unallocated space after the last partition
+    last_end_address = MAX(last_end_address, start_offset);
+    size_t unallocated_size = flash_chip->size - last_end_address;
+    if (unallocated_size >= required_size) {
+        *found_offset = last_end_address;
+        if (found_size != NULL) {
+            *found_size = unallocated_size;
+        }
+        free(sorted_partitions);
+        return ESP_OK;
+    }
+
+    free(sorted_partitions);
+    return ESP_ERR_NOT_FOUND;
+}
diff --git a/examples/system/ota/partitions_ota/main/partition_utils.h b/examples/system/ota/partitions_ota/main/partition_utils.h
new file mode 100644
index 00000000000..6dbfb03201f
--- /dev/null
+++ b/examples/system/ota/partitions_ota/main/partition_utils.h
@@ -0,0 +1,39 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_partition.h"
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Find unallocated space in the partition table.
+ *
+ * This function searches for a contiguous space in the specified flash memory chip
+ * that can accommodate a region of the given size and is not allocated to any partition.
+ * It starts searching from the specifies start_offset and continues until the end of the flash memory.
+ *
+ * @param[in] flash_chip     Pointer to the flash chip structure. If NULL, the default flash chip (internal) is used.
+ * @param[in] required_size  Size of the required unallocated space in bytes.
+ * @param[in] start_offset   Starting offset in the flash memory from where the search should begin.
+ * @param[out] found_offset  Pointer where the offset of the found unallocated space will be stored.
+ * @param[out] found_size    Pointer where the actual size of the found unallocated space will be stored (optional, if it is NULL).
+ *
+ * @return
+ *      - ESP_OK: Unallocated space of the required size was found.
+ *      - ESP_ERR_INVALID_ARG: The found_offset parameter is NULL or the required_size is invalid (e.g., 0).
+ *      - ESP_ERR_NOT_FOUND: No suitable unallocated space was found.
+ */
+esp_err_t partition_utils_find_unallocated(esp_flash_t *flash_chip, size_t required_size, uint32_t start_offset, uint32_t *found_offset, size_t *found_size);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/examples/system/ota/partitions_ota/pytest_partitions_ota.py b/examples/system/ota/partitions_ota/pytest_partitions_ota.py
new file mode 100644
index 00000000000..dae55ff5db1
--- /dev/null
+++ b/examples/system/ota/partitions_ota/pytest_partitions_ota.py
@@ -0,0 +1,186 @@
+# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Unlicense OR CC0-1.0
+import http.server
+import multiprocessing
+import os
+import ssl
+import sys
+from typing import Any
+from typing import Optional
+
+import pexpect
+import pytest
+from pytest_embedded import Dut
+
+try:
+    from common_test_methods import get_env_config_variable, get_host_ip4_by_dest_ip
+except ModuleNotFoundError:
+    idf_path = os.environ['IDF_PATH']
+    sys.path.insert(0, idf_path + '/tools/ci/python_packages')
+    from common_test_methods import get_env_config_variable, get_host_ip4_by_dest_ip
+
+server_cert = '-----BEGIN CERTIFICATE-----\n' \
+              'MIIDWDCCAkACCQCbF4+gVh/MLjANBgkqhkiG9w0BAQsFADBuMQswCQYDVQQGEwJJ\n'\
+              'TjELMAkGA1UECAwCTUgxDDAKBgNVBAcMA1BVTjEMMAoGA1UECgwDRVNQMQwwCgYD\n'\
+              'VQQLDANFU1AxDDAKBgNVBAMMA0VTUDEaMBgGCSqGSIb3DQEJARYLZXNwQGVzcC5j\n'\
+              'b20wHhcNMjEwNzEyMTIzNjI3WhcNNDEwNzA3MTIzNjI3WjBuMQswCQYDVQQGEwJJ\n'\
+              'TjELMAkGA1UECAwCTUgxDDAKBgNVBAcMA1BVTjEMMAoGA1UECgwDRVNQMQwwCgYD\n'\
+              'VQQLDANFU1AxDDAKBgNVBAMMA0VTUDEaMBgGCSqGSIb3DQEJARYLZXNwQGVzcC5j\n'\
+              'b20wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDhxF/y7bygndxPwiWL\n'\
+              'SwS9LY3uBMaJgup0ufNKVhx+FhGQOu44SghuJAaH3KkPUnt6SOM8jC97/yQuc32W\n'\
+              'ukI7eBZoA12kargSnzdv5m5rZZpd+NznSSpoDArOAONKVlzr25A1+aZbix2mKRbQ\n'\
+              'S5w9o1N2BriQuSzd8gL0Y0zEk3VkOWXEL+0yFUT144HnErnD+xnJtHe11yPO2fEz\n'\
+              'YaGiilh0ddL26PXTugXMZN/8fRVHP50P2OG0SvFpC7vghlLp4VFM1/r3UJnvL6Oz\n'\
+              '3ALc6dhxZEKQucqlpj8l1UegszQToopemtIj0qXTHw2+uUnkUyWIPjPC+wdOAoap\n'\
+              'rFTRAgMBAAEwDQYJKoZIhvcNAQELBQADggEBAItw24y565k3C/zENZlxyzto44ud\n'\
+              'IYPQXN8Fa2pBlLe1zlSIyuaA/rWQ+i1daS8nPotkCbWZyf5N8DYaTE4B0OfvoUPk\n'\
+              'B5uGDmbuk6akvlB5BGiYLfQjWHRsK9/4xjtIqN1H58yf3QNROuKsPAeywWS3Fn32\n'\
+              '3//OpbWaClQePx6udRYMqAitKR+QxL7/BKZQsX+UyShuq8hjphvXvk0BW8ONzuw9\n'\
+              'RcoORxM0FzySYjeQvm4LhzC/P3ZBhEq0xs55aL2a76SJhq5hJy7T/Xz6NFByvlrN\n'\
+              'lFJJey33KFrAf5vnV9qcyWFIo7PYy2VsaaEjFeefr7q3sTFSMlJeadexW2Y=\n'\
+              '-----END CERTIFICATE-----\n'
+
+server_key = '-----BEGIN PRIVATE KEY-----\n'\
+             'MIIEvQIBADANBgkqhkiG9w0BAQEFAASCBKcwggSjAgEAAoIBAQDhxF/y7bygndxP\n'\
+             'wiWLSwS9LY3uBMaJgup0ufNKVhx+FhGQOu44SghuJAaH3KkPUnt6SOM8jC97/yQu\n'\
+             'c32WukI7eBZoA12kargSnzdv5m5rZZpd+NznSSpoDArOAONKVlzr25A1+aZbix2m\n'\
+             'KRbQS5w9o1N2BriQuSzd8gL0Y0zEk3VkOWXEL+0yFUT144HnErnD+xnJtHe11yPO\n'\
+             '2fEzYaGiilh0ddL26PXTugXMZN/8fRVHP50P2OG0SvFpC7vghlLp4VFM1/r3UJnv\n'\
+             'L6Oz3ALc6dhxZEKQucqlpj8l1UegszQToopemtIj0qXTHw2+uUnkUyWIPjPC+wdO\n'\
+             'AoaprFTRAgMBAAECggEAE0HCxV/N1Q1h+1OeDDGL5+74yjKSFKyb/vTVcaPCrmaH\n'\
+             'fPvp0ddOvMZJ4FDMAsiQS6/n4gQ7EKKEnYmwTqj4eUYW8yxGUn3f0YbPHbZT+Mkj\n'\
+             'z5woi3nMKi/MxCGDQZX4Ow3xUQlITUqibsfWcFHis8c4mTqdh4qj7xJzehD2PVYF\n'\
+             'gNHZsvVj6MltjBDAVwV1IlGoHjuElm6vuzkfX7phxcA1B4ZqdYY17yCXUnvui46z\n'\
+             'Xn2kUTOOUCEgfgvGa9E+l4OtdXi5IxjaSraU+dlg2KsE4TpCuN2MEVkeR5Ms3Y7Q\n'\
+             'jgJl8vlNFJDQpbFukLcYwG7rO5N5dQ6WWfVia/5XgQKBgQD74at/bXAPrh9NxPmz\n'\
+             'i1oqCHMDoM9sz8xIMZLF9YVu3Jf8ux4xVpRSnNy5RU1gl7ZXbpdgeIQ4v04zy5aw\n'\
+             '8T4tu9K3XnR3UXOy25AK0q+cnnxZg3kFQm+PhtOCKEFjPHrgo2MUfnj+EDddod7N\n'\
+             'JQr9q5rEFbqHupFPpWlqCa3QmQKBgQDldWUGokNaEpmgHDMnHxiibXV5LQhzf8Rq\n'\
+             'gJIQXb7R9EsTSXEvsDyqTBb7PHp2Ko7rZ5YQfyf8OogGGjGElnPoU/a+Jij1gVFv\n'\
+             'kZ064uXAAISBkwHdcuobqc5EbG3ceyH46F+FBFhqM8KcbxJxx08objmh58+83InN\n'\
+             'P9Qr25Xw+QKBgEGXMHuMWgQbSZeM1aFFhoMvlBO7yogBTKb4Ecpu9wI5e3Kan3Al\n'\
+             'pZYltuyf+VhP6XG3IMBEYdoNJyYhu+nzyEdMg8CwXg+8LC7FMis/Ve+o7aS5scgG\n'\
+             '1to/N9DK/swCsdTRdzmc/ZDbVC+TuVsebFBGYZTyO5KgqLpezqaIQrTxAoGALFCU\n'\
+             '10glO9MVyl9H3clap5v+MQ3qcOv/EhaMnw6L2N6WVT481tnxjW4ujgzrFcE4YuxZ\n'\
+             'hgwYu9TOCmeqopGwBvGYWLbj+C4mfSahOAs0FfXDoYazuIIGBpuv03UhbpB1Si4O\n'\
+             'rJDfRnuCnVWyOTkl54gKJ2OusinhjztBjcrV1XkCgYEA3qNi4uBsPdyz9BZGb/3G\n'\
+             'rOMSw0CaT4pEMTLZqURmDP/0hxvTk1polP7O/FYwxVuJnBb6mzDa0xpLFPTpIAnJ\n'\
+             'YXB8xpXU69QVh+EBbemdJWOd+zp5UCfXvb2shAeG3Tn/Dz4cBBMEUutbzP+or0nG\n'\
+             'vSXnRLaxQhooWm+IuX9SuBQ=\n'\
+             '-----END PRIVATE KEY-----\n'
+
+
+@pytest.mark.esp32  # This chip should be >= v3.0
+@pytest.mark.esp32c3
+@pytest.mark.esp32s3
+@pytest.mark.wifi_high_traffic
+@pytest.mark.parametrize('config', [
+    'on_update_no_sb_ecdsa',
+    'on_update_no_sb_rsa',
+    'virt_sb_v2_and_fe',
+    'virt_sb_v2_and_fe_2'
+], indirect=True)
+@pytest.mark.parametrize('skip_autoflash', ['y'], indirect=True)
+@pytest.mark.timeout(2400)
+def test_examples_partitions_ota(dut: Dut) -> None:
+    print(' - Erase flash')
+    dut.serial.erase_flash()
+    print(' - Flash bootloader')
+    dut.serial.bootloader_flash()
+    print(' - Start app (flash partition_table and app)')
+    dut.serial.write_flash_no_enc()
+    update_partitions(dut, 'wifi_high_traffic')
+
+
+@pytest.mark.esp32
+@pytest.mark.esp32c3
+@pytest.mark.flash_encryption_wifi_high_traffic
+@pytest.mark.nightly_run
+@pytest.mark.timeout(2400)
+@pytest.mark.parametrize('config', [
+    'flash_enc_wifi',
+    'flash_enc_wifi_2'
+], indirect=True)
+@pytest.mark.parametrize('skip_autoflash', ['y'], indirect=True)
+def test_examples_partitions_ota_with_flash_encryption_wifi(dut: Dut) -> None:
+    dut.serial.erase_flash()
+    dut.serial.flash()
+    update_partitions(dut, 'flash_encryption_wifi_high_traffic')
+
+
+def update_partitions(dut: Dut, env_name: Optional[str]) -> None:
+    port = 8000
+    thread1 = multiprocessing.Process(target=start_https_server, args=(dut.app.binary_path, '0.0.0.0', port))
+    thread1.daemon = True
+    thread1.start()
+    try:
+        update(dut, port, 'partitions_ota.bin', env_name)
+        update(dut, port, 'bootloader/bootloader.bin', env_name)
+        update(dut, port, 'partition_table/partition-table.bin', env_name)
+        update(dut, port, 'storage.bin', env_name)
+    finally:
+        thread1.terminate()
+
+
+def update(dut: Dut, port: int, path_to_image: str, env_name: Optional[str]) -> None:
+    dut.expect('OTA example app_main start', timeout=90)
+    host_ip = setting_connection(dut, env_name)
+    dut.expect('Starting OTA example task', timeout=30)
+    url = f'https://{host_ip}:{port}/{path_to_image}'
+    print(f'Writing to device: {url}')
+    dut.write(url)
+    dut.expect('OTA Succeed, Rebooting...', timeout=90)
+
+
+def setting_connection(dut: Dut, env_name: Optional[str]) -> Any:
+    if env_name is not None and dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True:
+        dut.expect('Please input ssid password:')
+        ap_ssid = get_env_config_variable(env_name, 'ap_ssid')
+        ap_password = get_env_config_variable(env_name, 'ap_password')
+        dut.write(f'{ap_ssid} {ap_password}')
+    try:
+        ip_address = dut.expect(r'IPv4 address: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30)[1].decode()
+        print(f'Connected to AP/Ethernet with IP: {ip_address}')
+    except pexpect.exceptions.TIMEOUT:
+        raise ValueError('ENV_TEST_FAILURE: Cannot connect to AP/Ethernet')
+    return get_host_ip4_by_dest_ip(ip_address)
+
+
+def start_https_server(ota_image_dir: str, server_ip: str, server_port: int, server_file: Optional[str] = None, key_file: Optional[str] = None) -> None:
+    os.chdir(ota_image_dir)
+
+    if server_file is None:
+        server_file = os.path.join(ota_image_dir, 'server_cert.pem')
+        cert_file_handle = open(server_file, 'w+')
+        cert_file_handle.write(server_cert)
+        cert_file_handle.close()
+
+    if key_file is None:
+        key_file = os.path.join(ota_image_dir, 'server_key.pem')
+        key_file_handle = open('server_key.pem', 'w+')
+        key_file_handle.write(server_key)
+        key_file_handle.close()
+
+    httpd = http.server.HTTPServer((server_ip, server_port), http.server.SimpleHTTPRequestHandler)
+
+    ssl_context = ssl.SSLContext(ssl.PROTOCOL_TLS_SERVER)
+    ssl_context.load_cert_chain(certfile=server_file, keyfile=key_file)
+
+    httpd.socket = ssl_context.wrap_socket(httpd.socket, server_side=True)
+    httpd.serve_forever()
+
+
+if __name__ == '__main__':
+    if sys.argv[2:]:    # if two or more arguments provided:
+        # Usage: pytest_partition_ota.py <image_dir> <server_port> [cert_dir]
+        image_dir = os.path.dirname(os.path.realpath(__file__))
+        bin_dir = os.path.join(image_dir, sys.argv[1])
+        server_port = int(sys.argv[2])
+        server_file = None
+        key_file = None
+        if sys.argv[3:]:  # [cert_dir] - optional argument
+            cert_dir = os.path.join(image_dir, sys.argv[3])
+            server_file = os.path.join(cert_dir, 'ca_cert.pem')
+            key_file = os.path.join(cert_dir, 'ca_key.pem')
+        print(f'Starting HTTPS server at "https://0.0.0.0:{server_port}"')
+        start_https_server(bin_dir, '0.0.0.0', server_port, server_file=server_file, key_file=key_file)
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.flash_enc_wifi b/examples/system/ota/partitions_ota/sdkconfig.ci.flash_enc_wifi
new file mode 100644
index 00000000000..bbbb89bbed6
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.flash_enc_wifi
@@ -0,0 +1,21 @@
+# Common configs
+CONFIG_EXAMPLE_WIFI_SSID_PWD_FROM_STDIN=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL="FROM_STDIN"
+CONFIG_EXAMPLE_SKIP_COMMON_NAME_CHECK=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF=y
+
+CONFIG_MBEDTLS_TLS_CLIENT_ONLY=y
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_EXAMPLE_CONNECT_IPV6=n
+
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
+CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
+CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
+CONFIG_SECURE_BOOT_ALLOW_JTAG=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
+CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
+
+# This is required for nvs encryption (which is enabled by default with flash encryption)
+CONFIG_PARTITION_TABLE_OFFSET=0x9000
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.flash_enc_wifi_2 b/examples/system/ota/partitions_ota/sdkconfig.ci.flash_enc_wifi_2
new file mode 100644
index 00000000000..4fb0b551b06
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.flash_enc_wifi_2
@@ -0,0 +1,24 @@
+# Common configs
+CONFIG_EXAMPLE_WIFI_SSID_PWD_FROM_STDIN=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL="FROM_STDIN"
+CONFIG_EXAMPLE_SKIP_COMMON_NAME_CHECK=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF=y
+
+CONFIG_MBEDTLS_TLS_CLIENT_ONLY=y
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_EXAMPLE_CONNECT_IPV6=n
+
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
+CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
+CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
+CONFIG_SECURE_BOOT_ALLOW_JTAG=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
+CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
+CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
+
+# This is required for nvs encryption (which is enabled by default with flash encryption)
+CONFIG_PARTITION_TABLE_OFFSET=0x9000
+
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul_2.csv"
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_ecdsa b/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_ecdsa
new file mode 100644
index 00000000000..f87e912e9f8
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_ecdsa
@@ -0,0 +1,19 @@
+# Common configs
+CONFIG_EXAMPLE_WIFI_SSID_PWD_FROM_STDIN=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL="FROM_STDIN"
+CONFIG_EXAMPLE_SKIP_COMMON_NAME_CHECK=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF=y
+
+CONFIG_MBEDTLS_TLS_CLIENT_ONLY=y
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_EXAMPLE_CONNECT_IPV6=n
+
+# ECDSA is available only in ESP32
+CONFIG_IDF_TARGET="esp32"
+
+CONFIG_PARTITION_TABLE_OFFSET=0xC000
+
+CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT=y
+CONFIG_SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT=y
+CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME=y
+CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key_ecdsa.pem"
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_rsa b/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_rsa
new file mode 100644
index 00000000000..101049d73a1
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_rsa
@@ -0,0 +1,17 @@
+# Common configs
+CONFIG_EXAMPLE_WIFI_SSID_PWD_FROM_STDIN=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL="FROM_STDIN"
+CONFIG_EXAMPLE_SKIP_COMMON_NAME_CHECK=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF=y
+
+CONFIG_MBEDTLS_TLS_CLIENT_ONLY=y
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_EXAMPLE_CONNECT_IPV6=n
+
+CONFIG_PARTITION_TABLE_OFFSET=0xC000
+
+CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT=y
+CONFIG_SECURE_SIGNED_ON_UPDATE_NO_SECURE_BOOT=y
+CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=y
+CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key.pem"
+CONFIG_SECURE_BOOT_ALLOW_SHORT_APP_PARTITION=y
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_rsa.esp32 b/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_rsa.esp32
new file mode 100644
index 00000000000..df5a4fb8ec9
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.on_update_no_sb_rsa.esp32
@@ -0,0 +1,3 @@
+# ESP32 supports SIGNED_APPS_RSA_SCHEME only in ECO3
+CONFIG_IDF_TARGET="esp32"
+CONFIG_ESP32_REV_MIN_3=y
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe b/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe
new file mode 100644
index 00000000000..b46d7a4f582
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe
@@ -0,0 +1,23 @@
+# Common configs
+CONFIG_EXAMPLE_WIFI_SSID_PWD_FROM_STDIN=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL="FROM_STDIN"
+CONFIG_EXAMPLE_SKIP_COMMON_NAME_CHECK=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF=y
+
+CONFIG_MBEDTLS_TLS_CLIENT_ONLY=y
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_EXAMPLE_CONNECT_IPV6=n
+
+# FLASH_ENCRYPTION & SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH
+# IMPORTANT: ONLY VIRTUAL eFuse MODE!
+CONFIG_EFUSE_VIRTUAL=y
+CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y
+
+CONFIG_PARTITION_TABLE_OFFSET=0xE000
+
+CONFIG_SECURE_BOOT=y
+CONFIG_SECURE_BOOT_V2_ENABLED=y
+CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key.pem"
+CONFIG_SECURE_DISABLE_ROM_DL_MODE=y
+
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe.esp32 b/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe.esp32
new file mode 100644
index 00000000000..413efc1cbdd
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe.esp32
@@ -0,0 +1,3 @@
+# ESP32 supports SECURE_BOOT_V2 only in ECO3
+CONFIG_IDF_TARGET="esp32"
+CONFIG_ESP32_REV_MIN_3=y
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe_2 b/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe_2
new file mode 100644
index 00000000000..40d2f72990c
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe_2
@@ -0,0 +1,26 @@
+# Common configs
+CONFIG_EXAMPLE_WIFI_SSID_PWD_FROM_STDIN=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_URL="FROM_STDIN"
+CONFIG_EXAMPLE_SKIP_COMMON_NAME_CHECK=y
+CONFIG_EXAMPLE_FIRMWARE_UPGRADE_BIND_IF=y
+
+CONFIG_MBEDTLS_TLS_CLIENT_ONLY=y
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y
+CONFIG_EXAMPLE_CONNECT_IPV6=n
+
+# FLASH_ENCRYPTION & SECURE_BOOT_V2 with EFUSE_VIRTUAL_KEEP_IN_FLASH
+# IMPORTANT: ONLY VIRTUAL eFuse MODE!
+CONFIG_EFUSE_VIRTUAL=y
+CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH=y
+
+CONFIG_PARTITION_TABLE_OFFSET=0xE000
+
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul_2.csv"
+
+CONFIG_SECURE_BOOT=y
+CONFIG_SECURE_BOOT_V2_ENABLED=y
+CONFIG_SECURE_BOOT_SIGNING_KEY="test/secure_boot_signing_key.pem"
+CONFIG_SECURE_DISABLE_ROM_DL_MODE=y
+
+CONFIG_SECURE_FLASH_ENC_ENABLED=y
diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe_2.esp32 b/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe_2.esp32
new file mode 100644
index 00000000000..413efc1cbdd
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.ci.virt_sb_v2_and_fe_2.esp32
@@ -0,0 +1,3 @@
+# ESP32 supports SECURE_BOOT_V2 only in ECO3
+CONFIG_IDF_TARGET="esp32"
+CONFIG_ESP32_REV_MIN_3=y
diff --git a/examples/system/ota/partitions_ota/sdkconfig.defaults b/examples/system/ota/partitions_ota/sdkconfig.defaults
new file mode 100644
index 00000000000..70be58b0706
--- /dev/null
+++ b/examples/system/ota/partitions_ota/sdkconfig.defaults
@@ -0,0 +1,11 @@
+# Default sdkconfig parameters to use the OTA
+# partition table layout, with a 4MB flash size
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
+
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul_1.csv"
+
+# Certificate bundle configuration
+CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN=y
+CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE=y
+CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE_PATH="server_certs/ca_cert.pem"
diff --git a/examples/system/ota/partitions_ota/server_certs/ca_cert.pem b/examples/system/ota/partitions_ota/server_certs/ca_cert.pem
new file mode 100644
index 00000000000..b29ba7ab1f5
--- /dev/null
+++ b/examples/system/ota/partitions_ota/server_certs/ca_cert.pem
@@ -0,0 +1,20 @@
+-----BEGIN CERTIFICATE-----
+MIIDWDCCAkACCQCbF4+gVh/MLjANBgkqhkiG9w0BAQsFADBuMQswCQYDVQQGEwJJ
+TjELMAkGA1UECAwCTUgxDDAKBgNVBAcMA1BVTjEMMAoGA1UECgwDRVNQMQwwCgYD
+VQQLDANFU1AxDDAKBgNVBAMMA0VTUDEaMBgGCSqGSIb3DQEJARYLZXNwQGVzcC5j
+b20wHhcNMjEwNzEyMTIzNjI3WhcNNDEwNzA3MTIzNjI3WjBuMQswCQYDVQQGEwJJ
+TjELMAkGA1UECAwCTUgxDDAKBgNVBAcMA1BVTjEMMAoGA1UECgwDRVNQMQwwCgYD
+VQQLDANFU1AxDDAKBgNVBAMMA0VTUDEaMBgGCSqGSIb3DQEJARYLZXNwQGVzcC5j
+b20wggEiMA0GCSqGSIb3DQEBAQUAA4IBDwAwggEKAoIBAQDhxF/y7bygndxPwiWL
+SwS9LY3uBMaJgup0ufNKVhx+FhGQOu44SghuJAaH3KkPUnt6SOM8jC97/yQuc32W
+ukI7eBZoA12kargSnzdv5m5rZZpd+NznSSpoDArOAONKVlzr25A1+aZbix2mKRbQ
+S5w9o1N2BriQuSzd8gL0Y0zEk3VkOWXEL+0yFUT144HnErnD+xnJtHe11yPO2fEz
+YaGiilh0ddL26PXTugXMZN/8fRVHP50P2OG0SvFpC7vghlLp4VFM1/r3UJnvL6Oz
+3ALc6dhxZEKQucqlpj8l1UegszQToopemtIj0qXTHw2+uUnkUyWIPjPC+wdOAoap
+rFTRAgMBAAEwDQYJKoZIhvcNAQELBQADggEBAItw24y565k3C/zENZlxyzto44ud
+IYPQXN8Fa2pBlLe1zlSIyuaA/rWQ+i1daS8nPotkCbWZyf5N8DYaTE4B0OfvoUPk
+B5uGDmbuk6akvlB5BGiYLfQjWHRsK9/4xjtIqN1H58yf3QNROuKsPAeywWS3Fn32
+3//OpbWaClQePx6udRYMqAitKR+QxL7/BKZQsX+UyShuq8hjphvXvk0BW8ONzuw9
+RcoORxM0FzySYjeQvm4LhzC/P3ZBhEq0xs55aL2a76SJhq5hJy7T/Xz6NFByvlrN
+lFJJey33KFrAf5vnV9qcyWFIo7PYy2VsaaEjFeefr7q3sTFSMlJeadexW2Y=
+-----END CERTIFICATE-----
diff --git a/examples/system/ota/partitions_ota/test/partitions_efuse_emul_1.csv b/examples/system/ota/partitions_ota/test/partitions_efuse_emul_1.csv
new file mode 100644
index 00000000000..b028a5ea87b
--- /dev/null
+++ b/examples/system/ota/partitions_ota/test/partitions_efuse_emul_1.csv
@@ -0,0 +1,9 @@
+# Name,           Type,               SubType,   Offset,  Size,      Flags
+nvs,              data,               nvs,       ,        0x6000,
+nvs_key,          data,               nvs_keys,  ,        4K,
+storage,          data,               ,          ,        0x1000,    encrypted
+otadata,          data,               ota,       ,        0x2000,
+phy_init,         data,               phy,       ,        0x1000,
+emul_efuse,       data,               efuse,     ,        0x2000,
+ota_0,            app,                ota_0,     ,        0x1B0000,
+ota_1,            app,                ota_1,     ,        0x1B0000,
diff --git a/examples/system/ota/partitions_ota/test/partitions_efuse_emul_2.csv b/examples/system/ota/partitions_ota/test/partitions_efuse_emul_2.csv
new file mode 100644
index 00000000000..4970ae9470d
--- /dev/null
+++ b/examples/system/ota/partitions_ota/test/partitions_efuse_emul_2.csv
@@ -0,0 +1,11 @@
+# Name,           Type,               SubType,   Offset,  Size,      Flags
+PrimaryBTLDR,     bootloader,         primary,   N/A,     N/A,
+PrimaryPrtTable,  partition_table,    primary,   N/A,     N/A,
+nvs,              data,               nvs,       ,        0x6000,
+nvs_key,          data,               nvs_keys,  ,        4K,
+storage,          data,               ,          ,        0x1000,    encrypted
+otadata,          data,               ota,       ,        0x2000,
+phy_init,         data,               phy,       ,        0x1000,
+emul_efuse,       data,               efuse,     ,        0x2000,
+ota_0,            app,                ota_0,     ,        0x1B0000,
+ota_1,            app,                ota_1,     ,        0x1B0000,
diff --git a/examples/system/ota/partitions_ota/test/secure_boot_signing_key.pem b/examples/system/ota/partitions_ota/test/secure_boot_signing_key.pem
new file mode 100644
index 00000000000..da5fe069c0a
--- /dev/null
+++ b/examples/system/ota/partitions_ota/test/secure_boot_signing_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4wIBAAKCAYEAzJUktQ+7wpPDfDGterxiMRx5w9n7PFaUSK3wnE+05ALsEF8F
+rUOC7/q0GutYYdWopdRM1FUKX2XVaryMViC+DHof42fEbpWYnfrCkYrDn8MLuMyK
+4uGunl8LUTIAZk3I3SZKJZy5FW9eb1XtkwfN1lAd6lEEGQKyoR6Bk/Rkisj0LP7R
+dyV9NKbJhxavZ1ohZXiXU5FW873iGdPIsloZoUK3QGRE1KRIH2woUGHATfXBCf5a
++e41wJzz7YHl5tjyxAbJ9PET52N14G73WoZKHu3QPShALrZVfjsk1oYdFvNdOBDL
+uU0vpyKl7mJHno11gM0UM0s9PrMxk9ffdAqMyS8YeLEk2Xl3AwPv7m9oeGIdSD/P
+okcISYcm4YAl5veqIG3RlkfpWjf5G15UYyLbgmn4GOkgr6ksB/dCFOMi9V1LjPah
+32A7gxqTlapQza+wNs30SYBIXrFde4bNnhFhj4Cbt34ADefWm26KLiZEHFHFN30Z
+IownitXz3rT7rmzBAgMBAAECggGBAK6bBA88dGWnM4rF42gDbFK6GPqdCp3+zuQR
+AHCIXrzT+aInV3L/Ubt730eyYWZusleGEGSQiB/PjAxjC+teWpXPjXPK1o4DQ5Rh
+trn9EuVB1LlOaaMmNqCYQdJ0uH6YGL0WtuXPEvBGcvTXA8MfQACPtFiN+M9XzBlT
+LgiW51DEHhJhEWl9J5VOXGXdaKru893kxFLgkrPI9jZQ2NPPrlxB0qE0csKBy8R1
+zRp9s2FWRAFBg2gYdOwFiPLGkO8rbM+jhXM+IUV1GgVYdxAC6zS9AiIAWuACDEwp
+Pzg3d3/5uyOFK1xTIPl/cG8CZyPQL1v/mUx0MZFaB1R1CVeDuMoFVz2YSbEaAVFv
+QIcJGDN/WlJbt0jwj7/RJKKTx0ipFlUdNbodzdaSl3Yg4N+evzR1nS8DvLJpwl/e
+ybu40IbavwYXWVzirH3wRg+P/NDsHLU5xASAyUwf1minsmObILayEZgfTA6TbrKL
+fZbJCvy2/IuCM6iqKZwSvYy0bJdaAQKBwQDzDVa/M4/sJV0GEbwegeN6Xf+XKkl3
+Gosjd+vQgv/0X1gbdMc0Ej9eYSU5/GYIHxDzDRkYIxtIfwaze1gGeNRHycMCmVkl
+09DMi48jLGE7wzObPu6MtBCSAGHaS9zMTVCYDYtRlykPzG2/1QNrRUDNACnpzneK
+MkWObzFYTIup1zh+JaD56vLIDdL7qM9apmEkq4O6y1BBPnCgRYJy5EU3BDZxz9fP
+47JtCZ47uVguoh/NVYY5uibdvI5iJ4SA/VECgcEA13srpwJppfTTFPRWgD+g7PdU
+Yg+ENBWygiJuwgGv6DyD4k73pxiyshNo7jxsdOLeGFA8hI3dvd/Ei6uUsGnWPy/a
+OwuBcOZrJZjyawNSiC+mrCSP0LGQrC5VjmuE8IU1d2hFWyV/NzkSLaXJ52Zkg3ee
+sSepBHtWEYpwH929u5FTKDKhL0qRH8E1EsULSjmkTa+cVDYgx8+2mb3vHRdJdvt3
+FZU9erKyDb4II5GJhyNQo/cxBosDzj4yIMKM/dxxAoHAE1r1lIZjqLeU/927sGZB
+mkYQC5a3gP+hIvLy2YkFHw3Us2MKVhA58ack0shRy8XFkMVzQSPSkWRkQTjKWsGW
+jhz4JaXWnpeOoite+7sWBy9VVcCeOKBCTY4wPLUb4T0q9ODnPlkeUP7Doqow+oLq
+VSj1LYReqqe0OFKMiG6YFK9p9UnD1wMp0FqheZ8I3DwxsjziYaa9PmTdjTXb3JBn
+Hql8OHYHxqtoUxyX+EObTSNmCvELnl8/pxrT7+cbuzXxAoHAfmNYb1US8qxvQtMu
+CXtIwLUxYXMIcCRp17qqjFDBBM657Hu09uWdqqWH3nTCiKyo6EnntTgg38XoWqQB
+SphJejZvIkLVYYtFPYBAcFQ6jHampEGtuRLtcJCczjRyfUEk4yzdwWB1BccLyop7
+qqZ8PkBjbDV/BYnyKcexjH9bUjEjPWi08jAifyWsI54/yQGWRZrDbwFwqMJEsFif
+b8jA5nEIoDgxH07A8R6NV499wy4LlqDeuJ/BU69XZ6+1UxGBAoHAXfb9t5ivdf9N
+ZbZj61GcrDLyYGDTotucy8HPNMr5P3ZmBR/5UzClpCbWVSaziK3CKzR0zURLw0W7
+rF4CySTjuD9FHOFFWjjlkS4KwOyYiy8fuMMLg1RmsCS8H+0L3Pm25PmRQ9TLjEf4
+0uFWf7fG4GQiciqGcvfaFH3w//d0Q7PSvIMNlM1Gc7JS1Qn4HoDF2Ux6drNb6nJL
+l6tdXNMkUFHBMtaQy0l9D/ex5NZlAniePT3xfMrQf6m0rVAAaAY0
+-----END RSA PRIVATE KEY-----
diff --git a/examples/system/ota/partitions_ota/test/secure_boot_signing_key_ecdsa.pem b/examples/system/ota/partitions_ota/test/secure_boot_signing_key_ecdsa.pem
new file mode 100644
index 00000000000..13a49c4ddc7
--- /dev/null
+++ b/examples/system/ota/partitions_ota/test/secure_boot_signing_key_ecdsa.pem
@@ -0,0 +1,5 @@
+-----BEGIN EC PRIVATE KEY-----
+MHcCAQEEIOvP45grF4dSM2fWbOAp4W8PgFm30HIZqtNEK13O5hVHoAoGCCqGSM49
+AwEHoUQDQgAE1IL73BARrNpkHj1jG50eHoF2LERCwz1BfbshuAeLcsED5aT92Xgu
+gJvq45LN9p6eBi62ZZwr6Z2ZfX3YB3/8KA==
+-----END EC PRIVATE KEY-----
diff --git a/examples/system/ota/partitions_ota/test/storage.bin b/examples/system/ota/partitions_ota/test/storage.bin
new file mode 100644
index 00000000000..547abd18d99
--- /dev/null
+++ b/examples/system/ota/partitions_ota/test/storage.bin
@@ -0,0 +1,68 @@
+729640676936343167405726443197135657269157998
+933232050979719444751452267503063397819023382
+556506319597389776571009503699952437641061732
+002752455079598828837517200348560233202884961
+289477881250470899211041514323644847313434252
+730231884515472435547694444234642911818478157
+604144032495549544339412331088820122187613561
+037928985771855738051392892725939092474036895
+578049014383949960944604448487826864453409450
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+140428241649972439923475366687089049988769325
+628351145210907812434482037266152681719092912
+195052933351010873736343964178221498387487568
+880765493241408400507065714578908626300143903
+883991915607625769735210770743664311477574805
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+364825257659858363550270789813108372635022027
+738652557666400070994836903956811374712435567
+047611244061167695176168226753393440679656386
+185089811485754675632410309589122549282952655
+762982585738215953889178883392751359696199678
+466365406348114092011380838127323464485769393
+308459315194527893288390791240690970366091968
+418737882756335691688926129739468319284933735
+112439699935630133393004802185263769845456882
+716047319575852391012595513490467744266860105
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+760032386987855643579460268598949375417486418
+353173014844750264581499676629717396353130841
+051820655315640727727623322576821500963566535
+812443435910850388330357301683274331804203320
+356920660584480371919309487962624455455544515
diff --git a/examples/system/ota/simple_ota_example/pytest_simple_ota.py b/examples/system/ota/simple_ota_example/pytest_simple_ota.py
index c7c1992f032..bbc7d27be62 100644
--- a/examples/system/ota/simple_ota_example/pytest_simple_ota.py
+++ b/examples/system/ota/simple_ota_example/pytest_simple_ota.py
@@ -225,6 +225,11 @@ def test_examples_protocol_simple_ota_example_with_flash_encryption_wifi(dut: Du
       2. Fetch OTA image over HTTPS
       3. Reboot with the new OTA image
     """
+    # CONFIG_PARTITION_TABLE_TWO_OTA_ENCRYPTED_NVS==y, it includes partitions_two_ota_encr_nvs.csv
+    FACTORY_ADDRESS = '0x20000'
+    OTA_0_ADDRESS = '0x120000'
+    # OTA_1_ADDRESS = '0x220000'
+
     # start test
     # Erase flash
     dut.serial.erase_flash()
@@ -234,7 +239,7 @@ def test_examples_protocol_simple_ota_example_with_flash_encryption_wifi(dut: Du
     thread1.daemon = True
     thread1.start()
     try:
-        dut.expect(f'Loaded app from partition at offset {OTA_0_ADDRESS}', timeout=30)
+        dut.expect(f'Loaded app from partition at offset {FACTORY_ADDRESS}', timeout=30)
         dut.expect('Flash encryption mode is DEVELOPMENT', timeout=10)
         # Parse IP address of STA
         env_name = 'flash_encryption_wifi_high_traffic' if dut.app.sdkconfig.get('EXAMPLE_WIFI_SSID_PWD_FROM_STDIN') is True else None
@@ -245,7 +250,7 @@ def test_examples_protocol_simple_ota_example_with_flash_encryption_wifi(dut: Du
         dut.write(f'https://{host_ip}:8000/simple_ota.bin')
         dut.expect('OTA Succeed, Rebooting...', timeout=60)
         # after reboot
-        dut.expect(f'Loaded app from partition at offset {OTA_1_ADDRESS}', timeout=30)
+        dut.expect(f'Loaded app from partition at offset {OTA_0_ADDRESS}', timeout=30)
         dut.expect('Flash encryption mode is DEVELOPMENT', timeout=10)
         dut.expect('OTA example app_main start', timeout=10)
     finally:
diff --git a/examples/system/ulp/lp_core/gpio_wakeup/CMakeLists.txt b/examples/system/ulp/lp_core/gpio_wakeup/CMakeLists.txt
new file mode 100644
index 00000000000..8c1a422f3f4
--- /dev/null
+++ b/examples/system/ulp/lp_core/gpio_wakeup/CMakeLists.txt
@@ -0,0 +1,6 @@
+# The following lines of boilerplate have to be in your project's CMakeLists
+# in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(ulp_lp_core_gpio_wakeup_example)
diff --git a/examples/system/ulp/lp_core/gpio_wakeup/README.md b/examples/system/ulp/lp_core/gpio_wakeup/README.md
new file mode 100644
index 00000000000..66925750726
--- /dev/null
+++ b/examples/system/ulp/lp_core/gpio_wakeup/README.md
@@ -0,0 +1,26 @@
+| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-P4 |
+| ----------------- | -------- | -------- | -------- |
+# ULP-LP-Core simple example with GPIO Interrupt:
+
+This example demonstrates how to program the LP-Core coprocessor to wake up from a RTC IO interrupt, instead of waking periodically from the ULP timer.
+
+ULP program written in C can be found across `ulp/main.c`. The build system compiles and links this program, converts it into binary format, and embeds it into the .rodata section of the ESP-IDF application.
+
+At runtime, the main code running on the ESP (found in lp_core_gpio_wake_up_example_main.c) loads ULP program into the `RTC_SLOW_MEM` memory region using `ulp_lp_core_load_binary` function. The main code then configures the ULP GPIO wakeup source and starts the coprocessor by using `ulp_lp_core_run` followed by putting the chip into deep sleep mode.
+
+When the wakeup source pin is pulled low the LP-Core coprocessor is woken up, sends a wakeup signal to the main CPU and goes back to sleep again.
+
+In this example the input signal is connected to GPIO2. To change the pin number, check the Chip Pin List document and adjust `WAKEUP_PIN` variable in main.c.
+
+
+## Example output
+
+```
+Not a LP-Core wakeup, initializing it!
+Entering deep sleep
+
+...
+
+LP-Core woke up the main CPU!
+Entering deep sleep
+```
diff --git a/examples/system/ulp/lp_core/gpio_wakeup/main/CMakeLists.txt b/examples/system/ulp/lp_core/gpio_wakeup/main/CMakeLists.txt
new file mode 100644
index 00000000000..9970ae3effb
--- /dev/null
+++ b/examples/system/ulp/lp_core/gpio_wakeup/main/CMakeLists.txt
@@ -0,0 +1,27 @@
+# Set usual component variables
+set(COMPONENT_SRCS "lp_core_gpio_wake_up_example_main.c")
+set(COMPONENT_ADD_INCLUDEDIRS "")
+set(COMPONENT_REQUIRES ulp driver)
+
+register_component()
+
+#
+# ULP support additions to component CMakeLists.txt.
+#
+# 1. The ULP app name must be unique (if multiple components use ULP).
+set(ulp_app_name ulp_${COMPONENT_NAME})
+#
+# 2. Specify all C and Assembly source files.
+#    Files should be placed into a separate directory (in this case, ulp/),
+#    which should not be added to COMPONENT_SRCS.
+set(ulp_riscv_sources "ulp/main.c")
+
+#
+# 3. List all the component source files which include automatically
+#    generated ULP export file, ${ulp_app_name}.h:
+set(ulp_exp_dep_srcs "lp_core_gpio_wake_up_example_main.c")
+
+#
+# 4. Call function to build ULP binary and embed in project using the argument
+#    values above.
+ulp_embed_binary(${ulp_app_name} "${ulp_riscv_sources}" "${ulp_exp_dep_srcs}")
diff --git a/examples/system/ulp/lp_core/gpio_wakeup/main/lp_core_gpio_wake_up_example_main.c b/examples/system/ulp/lp_core/gpio_wakeup/main/lp_core_gpio_wake_up_example_main.c
new file mode 100644
index 00000000000..7de67d59c36
--- /dev/null
+++ b/examples/system/ulp/lp_core/gpio_wakeup/main/lp_core_gpio_wake_up_example_main.c
@@ -0,0 +1,86 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+/* ULP LP-Core GPIO wake-up example
+
+   This example code is in the Public Domain (or CC0 licensed, at your option.)
+
+   Unless required by applicable law or agreed to in writing, this
+   software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+   CONDITIONS OF ANY KIND, either express or implied.
+*/
+
+#include <stdio.h>
+#include "esp_sleep.h"
+#include "driver/rtc_io.h"
+#include "ulp_lp_core.h"
+#include "ulp_main.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+
+#define WAKEUP_PIN 2
+
+extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_main_bin_start");
+extern const uint8_t ulp_main_bin_end[]   asm("_binary_ulp_main_bin_end");
+
+static void init_ulp_program(void);
+
+static void wakeup_gpio_init(void)
+{
+    /* Configure the button GPIO as input, enable wakeup */
+    rtc_gpio_init(WAKEUP_PIN);
+    rtc_gpio_set_direction(WAKEUP_PIN, RTC_GPIO_MODE_INPUT_ONLY);
+    rtc_gpio_pulldown_dis(WAKEUP_PIN);
+    rtc_gpio_pullup_en(WAKEUP_PIN);
+    rtc_gpio_wakeup_enable(WAKEUP_PIN, GPIO_INTR_LOW_LEVEL);
+}
+
+void app_main(void)
+{
+    /* If user is using USB-serial-jtag then idf monitor needs some time to
+    *  re-connect to the USB port. We wait 1 sec here to allow for it to make the reconnection
+    *  before we print anything. Otherwise the chip will go back to sleep again before the user
+    *  has time to monitor any output.
+    */
+    vTaskDelay(pdMS_TO_TICKS(1000));
+
+    wakeup_gpio_init();
+
+    esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
+    /* not a wakeup from ULP, load the firmware */
+    if (cause != ESP_SLEEP_WAKEUP_ULP) {
+        printf("Not a ULP wakeup, initializing it! \n");
+        init_ulp_program();
+    }
+
+    /* ULP read and detected a change in WAKEUP_PIN, prints */
+    if (cause == ESP_SLEEP_WAKEUP_ULP) {
+        printf("ULP woke up the main CPU! \n");
+    }
+
+    /* Go back to sleep, only the ULP will run */
+    printf("Entering deep sleep\n\n");
+
+    /* Small delay to ensure the messages are printed */
+    vTaskDelay(100 / portTICK_PERIOD_MS);
+
+    ESP_ERROR_CHECK( esp_sleep_enable_ulp_wakeup());
+
+    esp_deep_sleep_start();
+}
+
+static void init_ulp_program(void)
+{
+    esp_err_t err = ulp_lp_core_load_binary(ulp_main_bin_start, (ulp_main_bin_end - ulp_main_bin_start));
+    ESP_ERROR_CHECK(err);
+
+    /* Start the program */
+    ulp_lp_core_cfg_t cfg = {
+        .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_LP_IO,
+    };
+
+    err = ulp_lp_core_run(&cfg);
+    ESP_ERROR_CHECK(err);
+}
diff --git a/examples/system/ulp/lp_core/gpio_wakeup/main/ulp/main.c b/examples/system/ulp/lp_core/gpio_wakeup/main/ulp/main.c
new file mode 100644
index 00000000000..0f630ddc0cc
--- /dev/null
+++ b/examples/system/ulp/lp_core/gpio_wakeup/main/ulp/main.c
@@ -0,0 +1,23 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+#include <stdint.h>
+#include <stdbool.h>
+#include "ulp_lp_core.h"
+#include "ulp_lp_core_utils.h"
+#include "ulp_lp_core_gpio.h"
+
+
+int main (void)
+{
+    ulp_lp_core_wakeup_main_processor();
+
+    /* Wakeup interrupt is a level interrupt, wait 1 sec to
+        allow user to release button to avoid waking up the ULP multiple times */
+    ulp_lp_core_delay_us(1000*1000);
+    ulp_lp_core_gpio_clear_intr_status();
+
+    return 0;
+}
diff --git a/examples/system/ulp/lp_core/gpio_wakeup/sdkconfig.defaults b/examples/system/ulp/lp_core/gpio_wakeup/sdkconfig.defaults
new file mode 100644
index 00000000000..456833bc8c3
--- /dev/null
+++ b/examples/system/ulp/lp_core/gpio_wakeup/sdkconfig.defaults
@@ -0,0 +1,9 @@
+# Enable ULP
+CONFIG_ULP_COPROC_ENABLED=y
+CONFIG_ULP_COPROC_TYPE_LP_CORE=y
+CONFIG_ULP_COPROC_RESERVE_MEM=8128
+# Set log level to Warning to produce clean output
+CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
+CONFIG_BOOTLOADER_LOG_LEVEL=2
+CONFIG_LOG_DEFAULT_LEVEL_WARN=y
+CONFIG_LOG_DEFAULT_LEVEL=2
diff --git a/examples/system/ulp/lp_core/lp_spi/CMakeLists.txt b/examples/system/ulp/lp_core/lp_spi/CMakeLists.txt
new file mode 100644
index 00000000000..0eaa5362f3e
--- /dev/null
+++ b/examples/system/ulp/lp_core/lp_spi/CMakeLists.txt
@@ -0,0 +1,6 @@
+# The following five lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+project(lp_spi)
diff --git a/examples/system/ulp/lp_core/lp_spi/README.md b/examples/system/ulp/lp_core/lp_spi/README.md
new file mode 100644
index 00000000000..8823028fe2c
--- /dev/null
+++ b/examples/system/ulp/lp_core/lp_spi/README.md
@@ -0,0 +1,54 @@
+| Supported Targets | ESP32-P4 |
+| ----------------- | -------- |
+
+# LP I2C Example
+
+(See the README.md file in the upper level 'examples' directory for more information about examples.)
+
+## Overview
+
+This example demonstrates the basic usage of the LP SPI driver from the LP core by reading to and writing from a sensor connected over SPI. The ULP will periodically read temperature and humidity measurements from the sensor and wake up the HP CPU if `WAKEUP_HP_CPU_LIMIT_CELSIUS` (30 degrees by default) is exceeded.
+
+## How to use example
+
+### Hardware Required
+
+To run this example, you should have an ESP based development board that supports the LP SPI peripheral on the LP Core as well as a BME280 sensor. BME280 is a combined temperature, humidity and pressure sensor. More information about it can be found in at [BME280](https://www.bosch-sensortec.com/products/environmental-sensors/humidity-sensors-bme280/).
+
+#### Pin Assignment:
+
+**Note:** The following pin assignments are used by default.
+
+|                         | SDI(MISO) | SDO(MOSI) | SCK   | CSB (CS) |
+| ----------------------- | ----------| ----------| ----- | -------- |
+| ESP32-P4 LP SPI Master  | GPIO6     | GPIO7     | GPIO8 | GPIO4    |
+
+### Build and Flash
+
+Enter `idf.py -p PORT flash monitor` to build, flash and monitor the project.
+
+(To exit the serial monitor, type ``Ctrl-]``.)
+
+See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects.
+
+## Example Output
+
+The log output should indicate that the LP core and the LP SPI peripheral have been successfully initialized. The main CPU would then enter deep sleep mode.
+
+```bash
+Not an LP core wakeup. Cause = 0
+Initializing...
+LP SPI initialized successfully
+LP core loaded with firmware successfully
+Entering deep sleep...
+
+(When the BME280 sensor is exposed to a temperature above normal room temperature, defined as 30 degree by default in the ULP code, it will wake up the HP CPU)
+
+LP core woke up the main CPU
+Temperature 31.31 degree celsius, humidity 66.01%RH
+Entering deep sleep...
+```
+
+## Troubleshooting
+
+(For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you as soon as possible.)
diff --git a/examples/system/ulp/lp_core/lp_spi/main/CMakeLists.txt b/examples/system/ulp/lp_core/lp_spi/main/CMakeLists.txt
new file mode 100644
index 00000000000..2e46304acb4
--- /dev/null
+++ b/examples/system/ulp/lp_core/lp_spi/main/CMakeLists.txt
@@ -0,0 +1,25 @@
+# Register the component
+idf_component_register(SRCS "lp_spi_main.c"
+                       INCLUDE_DIRS ""
+                       REQUIRES ulp)
+
+#
+# ULP support additions to component CMakeLists.txt.
+#
+# 1. The LP Core app name must be unique (if multiple components use LP Core).
+set(ulp_app_name lp_core_${COMPONENT_NAME})
+#
+# 2. Specify all C files.
+#    Files should be placed into a separate directory (in this case, lp_core/),
+#    which should not be added to COMPONENT_SRCS.
+set(ulp_lp_core_sources "lp_core/main.c")
+
+#
+# 3. List all the component source files which include automatically
+#    generated LP Core export file, ${ulp_app_name}.h:
+set(ulp_exp_dep_srcs "lp_spi_main.c")
+
+#
+# 4. Call function to build ULP binary and embed in project using the argument
+#    values above.
+ulp_embed_binary(${ulp_app_name} "${ulp_lp_core_sources}" "${ulp_exp_dep_srcs}")
diff --git a/examples/system/ulp/lp_core/lp_spi/main/lp_core/bme280_defs.h b/examples/system/ulp/lp_core/lp_spi/main/lp_core/bme280_defs.h
new file mode 100644
index 00000000000..ae5ae6d0118
--- /dev/null
+++ b/examples/system/ulp/lp_core/lp_spi/main/lp_core/bme280_defs.h
@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+// Contains only the subset of registers used in this example
+
+#define BME280_CHIP_ID_REG              0xD0   // Chip ID Register
+
+#define BME280_RESET_REG                0xE0   // Soft Reset Register
+
+#define BME280_CTRL_HUM_REG             0xF2   // Humidity control
+#define BME280_HUM_OVERSAMPLING_BIT     0      // Bit position for humidity oversampling
+#define BME280_HUM_OVERSAMPLING_1X      0x1    // Value for 1x oversampling
+
+#define BME280_STATUS_REG               0xF3   // Status Register
+#define BME280_MEASURING_BIT            3      // Bit position for measuring in progress status
+
+#define BME280_CTRL_MEAS_REG            0xF4   // Measurement Control Register
+#define BME280_MODE_BIT                 0      // Bit position for mode
+#define BME280_MODE_FORCED              0x1    // Value for setting forced mode
+#define BME280_TEMP_OVERSAMPLING_BIT    5      // Bit position for temperature oversampling
+#define BME280_TEMP_OVERSAMPLING_1X     0x1    // Value for 1x oversampling
+
+#define BME280_CONFIG_REG               0xF5   // Configuration Register
+
+#define BME280_TEMPERATURE_MSB_REG      0xFA   // Temperature data MSB
+#define BME280_TEMPERATURE_LSB_REG      0xFB   // Temperature data LSB
+#define BME280_TEMPERATURE_XLSB_REG     0xFC   // Temperature data XLSB
+#define BME280_HUMIDITY_MSB_REG         0xFD   // Humidity data MSB
+#define BME280_HUMIDITY_LSB_REG         0xFE   // Humidity data LSB
+
+#define BME280_TRIM_PARAM_TEMP_1_REG    0x88    // Trimming Parameter T1
+#define BME280_TRIM_PARAM_HUM_1_REG     0xA1    // Trimming Parameter H1
+#define BME280_TRIM_PARAM_HUM_2_REG     0xE1    // Trimming Parameter H2
+
+#define BME280_RESET_VAL                0xB6   // Write value to trigger a reset
+#define BME280_CHIP_ID_VAL              0x60   // Chip ID
diff --git a/examples/system/ulp/lp_core/lp_spi/main/lp_core/main.c b/examples/system/ulp/lp_core/lp_spi/main/lp_core/main.c
new file mode 100644
index 00000000000..82753c37428
--- /dev/null
+++ b/examples/system/ulp/lp_core/lp_spi/main/lp_core/main.c
@@ -0,0 +1,186 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include "ulp_lp_core_spi.h"
+#include "ulp_lp_core_utils.h"
+#include "ulp_lp_core_print.h"
+#include "bme280_defs.h"
+
+#define LP_SPI_TRANS_WAIT_FOREVER   -1
+#define WAKEUP_HP_CPU_LIMIT_CELSIUS 30
+
+// Uncomment to print debug logs
+// #define DEBUG
+
+#ifdef DEBUG
+#define DEBUG_LOG lp_core_printf
+#else
+#define DEBUG_LOG (void)
+#endif
+
+static bool start_up = true;
+
+// Misc values used to compensate the measurements
+static uint16_t dig_T1;
+static int16_t dig_T2;
+static int16_t dig_T3;
+static int32_t t_fine;
+
+static uint16_t dig_H1;
+static int16_t dig_H2;
+static uint16_t dig_H3;
+static int16_t dig_H4;
+static int16_t dig_H5;
+static int16_t dig_H6;
+
+
+static void bme280_write(uint8_t reg_addr, uint8_t data)
+{
+    lp_spi_transaction_t trans_desc = {
+        .tx_buffer = &data,
+        .tx_length = 1,
+        .address = reg_addr & ~(1 << 7), // Clear MSB of register addr to indicate it is a write
+        .address_bits = 8,
+    };
+
+    esp_err_t err = lp_core_lp_spi_master_transfer(&trans_desc, LP_SPI_TRANS_WAIT_FOREVER);
+    if(err != ESP_OK) {
+        DEBUG_LOG("Failed to write register: 0x%X, with data = 0x%X\n", reg_addr, data);
+        abort();
+    }
+}
+
+static void bme280_read(uint8_t reg_addr, uint8_t* read_data, size_t read_len)
+{
+    lp_spi_transaction_t trans_desc = {
+        .tx_buffer = read_data,
+        .tx_length = read_len,
+        .rx_buffer = read_data,
+        .rx_length = read_len,
+        .address = reg_addr,
+        .address_bits = 8,
+    };
+
+
+    esp_err_t err = lp_core_lp_spi_master_transfer(&trans_desc, LP_SPI_TRANS_WAIT_FOREVER);
+    if(err != ESP_OK) {
+        DEBUG_LOG("Failed to read register: 0x%X, with len = 0x%X\n", reg_addr, read_len);
+        abort();
+    }
+}
+
+
+
+void bme280_read_compensation_params()
+{
+    uint8_t param_buf[6];
+    // Temperature compensation params are all in consecutive registers, read them all in one go
+    bme280_read(BME280_TRIM_PARAM_TEMP_1_REG, param_buf, 6);
+    dig_T1 = (param_buf[1] << 8) | param_buf[0];
+    dig_T2 = (param_buf[3] << 8) | param_buf[2];
+    dig_T3 = (param_buf[5] << 8) | param_buf[4];
+
+    // Humidity compensation params are in two separate regions, read twice
+    bme280_read(BME280_TRIM_PARAM_HUM_1_REG, param_buf, 1);
+    dig_H1 = param_buf[0];
+
+    bme280_read(BME280_TRIM_PARAM_HUM_2_REG, param_buf, 7);
+    dig_H2 = (param_buf[1] << 8) | param_buf[0];
+    dig_H3 = param_buf[2];
+    dig_H4 = (param_buf[3] << 4) | (param_buf[4] & 0xF);
+    dig_H5 = (param_buf[4] >> 4) | (param_buf[5] << 4);
+    dig_H6 = param_buf[6];
+
+}
+
+// Returns temperature in DegC, resolution is 0.01 DegC. Output value of “5123” equals 51.23 DegC.
+// t_fine carries fine temperature as global value
+// Function is taken from BME280 datasheet
+static int32_t convert_temp(int32_t adc_t)
+{
+    int32_t var1, var2, T;
+    var1 = ((((adc_t >> 3) - ((int32_t)dig_T1<<1)))*((int32_t)dig_T2)) >> 11;
+    var2 = (((((adc_t>>4) - ((int32_t)dig_T1)) * ((adc_t>>4) - ((int32_t)dig_T1))) >> 12) * ((int32_t)dig_T3)) >> 14;
+    t_fine = var1 + var2;
+    T = (t_fine * 5 + 128) >> 8;
+    return T;
+}
+
+// Returns humidity in %RH as unsigned 32 bit integer in Q22.10 format (22 integer and 10 fractional bits).
+// Output value of “47445” represents 47445/1024 = 46.333 %RH
+// Function is taken from BME280 datasheet
+static uint32_t convert_humidity(int32_t adc_h)
+{
+    int32_t v_x1_u32r;
+    v_x1_u32r = (t_fine - ((int32_t)76800));
+    v_x1_u32r = (((((adc_h << 14) - (((int32_t)dig_H4) << 20) - (((int32_t)dig_H5) * v_x1_u32r)) + ((int32_t)16384)) >> 15) * (((((((v_x1_u32r * ((int32_t)dig_H6)) >> 10) * (((v_x1_u32r * ((int32_t)dig_H3)) >> 11) + ((int32_t)32768))) >> 10) + ((int32_t)2097152)) * ((int32_t)dig_H2) + 8192) >> 14));
+    v_x1_u32r = (v_x1_u32r - (((((v_x1_u32r >> 15) * (v_x1_u32r >> 15)) >> 7) * ((int32_t)dig_H1)) >> 4));
+    v_x1_u32r = (v_x1_u32r < 0 ? 0 : v_x1_u32r);
+    v_x1_u32r = (v_x1_u32r > 419430400 ? 419430400 : v_x1_u32r);
+    return (uint32_t)(v_x1_u32r>>12);
+}
+
+static void bme280_read_environment_data(int32_t *temperature, uint32_t *humidity)
+{
+    uint8_t ctrl_hum = BME280_HUM_OVERSAMPLING_1X << BME280_HUM_OVERSAMPLING_BIT;
+    bme280_write(BME280_CTRL_HUM_REG, ctrl_hum);
+
+    uint8_t ctrl_meas = (BME280_TEMP_OVERSAMPLING_1X << BME280_TEMP_OVERSAMPLING_BIT) | (BME280_MODE_FORCED << BME280_MODE_BIT);
+    bme280_write(BME280_CTRL_MEAS_REG, ctrl_meas);
+
+    bool measuring = true;
+    while(measuring) {
+        uint8_t status = 0;
+        bme280_read(BME280_STATUS_REG, &status, 1);
+        measuring = status & (1 << BME280_MEASURING_BIT);
+    }
+
+    uint8_t env_data_buf[8] = {};
+    bme280_read(BME280_TEMPERATURE_MSB_REG, env_data_buf, 5);
+    uint32_t adc_temp = (env_data_buf[0] << 12) | (env_data_buf[1] << 4) | (env_data_buf[2] >> 4);
+    uint32_t adc_hum  = (env_data_buf[3] << 8) | (env_data_buf[4]);
+    *temperature = convert_temp(adc_temp);
+    *humidity = convert_humidity(adc_hum);
+}
+
+
+static void init_sensor(void)
+{
+    bme280_write(BME280_RESET_REG, BME280_RESET_VAL);
+    // Give the sensor some time to reset
+    ulp_lp_core_delay_us(2000);
+
+    uint8_t chip_id = 0;
+    bme280_read(BME280_CHIP_ID_REG, &chip_id, sizeof(chip_id));
+    DEBUG_LOG("Read chip id = 0x%X, expected 0x%X\n", chip_id, BME280_CHIP_ID_VAL);
+    if(chip_id != BME280_CHIP_ID_VAL) {
+        abort();
+    }
+}
+
+int32_t temperature;
+uint32_t humidity;
+
+int main (void)
+{
+    if(start_up) {
+        init_sensor();
+        bme280_read_compensation_params();
+        start_up = false;
+    }
+
+    bme280_read_environment_data(&temperature, &humidity);
+    DEBUG_LOG("Temperature: %d.%d degree Celsius, humidity: %d.%d\%%RH\n", temperature / 100, temperature % 100, humidity / 1024, humidity % 1024);
+
+    if(temperature/100 > WAKEUP_HP_CPU_LIMIT_CELSIUS) {
+        ulp_lp_core_wakeup_main_processor();
+    }
+
+    return 0;
+}
diff --git a/examples/system/ulp/lp_core/lp_spi/main/lp_spi_main.c b/examples/system/ulp/lp_core/lp_spi/main/lp_spi_main.c
new file mode 100644
index 00000000000..ba7513f0324
--- /dev/null
+++ b/examples/system/ulp/lp_core/lp_spi/main/lp_spi_main.c
@@ -0,0 +1,102 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include "esp_sleep.h"
+#include "lp_core_main.h"
+#include "ulp_lp_core.h"
+#include "lp_core_spi.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+
+extern const uint8_t lp_core_main_bin_start[] asm("_binary_lp_core_main_bin_start");
+extern const uint8_t lp_core_main_bin_end[]   asm("_binary_lp_core_main_bin_end");
+
+#define LP_SPI_MOSI_PIN 7
+#define LP_SPI_MISO_PIN 6
+#define LP_SPI_SCLK_PIN 8
+#define LP_SPI_CS_PIN   4
+
+#define LP_CORE_WAKEUP_PERIOD_US 1*1000*1000
+
+static void lp_core_init(void)
+{
+    esp_err_t ret = ESP_OK;
+
+    ulp_lp_core_cfg_t cfg = {
+        .wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER,
+        .lp_timer_sleep_duration_us = LP_CORE_WAKEUP_PERIOD_US
+    };
+
+    ret = ulp_lp_core_load_binary(lp_core_main_bin_start, (lp_core_main_bin_end - lp_core_main_bin_start));
+    if (ret != ESP_OK) {
+        printf("LP Core load failed\n");
+        abort();
+    }
+
+    ret = ulp_lp_core_run(&cfg);
+    if (ret != ESP_OK) {
+        printf("LP Core run failed\n");
+        abort();
+    }
+    printf("LP core loaded with firmware successfully\n");
+}
+
+static void lp_spi_init(void)
+{
+    lp_spi_host_t host_id = 0;
+
+    lp_spi_bus_config_t bus_config = {
+        .miso_io_num = LP_SPI_MISO_PIN,
+        .mosi_io_num = LP_SPI_MOSI_PIN,
+        .sclk_io_num = LP_SPI_SCLK_PIN,
+    };
+
+    /* Base LP SPI device settings */
+    lp_spi_device_config_t device = {
+        .cs_io_num = LP_SPI_CS_PIN,
+        .clock_speed_hz = 10 * 1000, // 10 MHz
+        .duty_cycle = 128,  // 50% duty cycle
+    };
+
+    ESP_ERROR_CHECK(lp_core_lp_spi_bus_initialize(host_id, &bus_config));
+
+    /* Add LP SPI device */
+    ESP_ERROR_CHECK(lp_core_lp_spi_bus_add_device(host_id, &device));
+    printf("LP SPI initialized successfully\n");
+}
+
+void app_main(void)
+{
+    /* If user is using USB-serial-jtag then idf monitor needs some time to
+    *  re-connect to the USB port. We wait 1 sec here to allow for it to make the reconnection
+    *  before we print anything. Otherwise the chip will go back to sleep again before the user
+    *  has time to monitor any output.
+    */
+    vTaskDelay(pdMS_TO_TICKS(1000));
+
+    esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
+    if (cause != ESP_SLEEP_WAKEUP_ULP) {
+        printf("Not an LP core wakeup. Cause = %d\n", cause);
+        printf("Initializing...\n");
+
+        /* Initialize LP_SPI from the main processor */
+        lp_spi_init();
+
+        /* Load LP Core binary and start the coprocessor */
+        lp_core_init();
+    } else if (cause == ESP_SLEEP_WAKEUP_ULP) {
+        printf("LP core woke up the main CPU\n");
+        printf("Temperature %.2f degree celsius, humidity %.2f%%RH\n", ulp_temperature / 100.0, ulp_humidity / 1024.0);
+    }
+
+    /* Setup wakeup triggers */
+    ESP_ERROR_CHECK(esp_sleep_enable_ulp_wakeup());
+
+    /* Enter Deep Sleep */
+    printf("Entering deep sleep...\n");
+    esp_deep_sleep_start();
+}
diff --git a/examples/system/ulp/lp_core/lp_spi/sdkconfig.defaults b/examples/system/ulp/lp_core/lp_spi/sdkconfig.defaults
new file mode 100644
index 00000000000..54483bf1d25
--- /dev/null
+++ b/examples/system/ulp/lp_core/lp_spi/sdkconfig.defaults
@@ -0,0 +1,10 @@
+# Enable LP Core
+CONFIG_ULP_COPROC_ENABLED=y
+CONFIG_ULP_COPROC_TYPE_LP_CORE=y
+CONFIG_ULP_COPROC_RESERVE_MEM=8128
+
+# Set log level to Warning to produce clean output
+CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
+CONFIG_BOOTLOADER_LOG_LEVEL=2
+CONFIG_LOG_DEFAULT_LEVEL_WARN=y
+CONFIG_LOG_DEFAULT_LEVEL=2
diff --git a/examples/system/ulp/ulp_riscv/touch/main/ulp_riscv_touch_example_main.c b/examples/system/ulp/ulp_riscv/touch/main/ulp_riscv_touch_example_main.c
index dd5d4a29985..8be53ec9b8e 100644
--- a/examples/system/ulp/ulp_riscv/touch/main/ulp_riscv_touch_example_main.c
+++ b/examples/system/ulp/ulp_riscv/touch/main/ulp_riscv_touch_example_main.c
@@ -10,7 +10,7 @@
 #include "esp_sleep.h"
 #include "ulp_riscv.h"
 #include "ulp_main.h"
-#include "driver/touch_pad.h"
+#include "driver/touch_sensor.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 
diff --git a/examples/system/ulp/ulp_riscv/touch/sdkconfig.defaults b/examples/system/ulp/ulp_riscv/touch/sdkconfig.defaults
index e3745e50576..332fdc55f14 100644
--- a/examples/system/ulp/ulp_riscv/touch/sdkconfig.defaults
+++ b/examples/system/ulp/ulp_riscv/touch/sdkconfig.defaults
@@ -7,3 +7,4 @@ CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
 CONFIG_BOOTLOADER_LOG_LEVEL=2
 CONFIG_LOG_DEFAULT_LEVEL_WARN=y
 CONFIG_LOG_DEFAULT_LEVEL=2
+CONFIG_TOUCH_SUPPRESS_DEPRECATE_WARN=y
diff --git a/examples/wifi/iperf/sdkconfig.defaults.esp32c5 b/examples/wifi/iperf/sdkconfig.defaults.esp32c5
index 7c3a67ad310..338b88f5700 100644
--- a/examples/wifi/iperf/sdkconfig.defaults.esp32c5
+++ b/examples/wifi/iperf/sdkconfig.defaults.esp32c5
@@ -12,7 +12,7 @@ CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
 CONFIG_ESP_WIFI_RX_BA_WIN=22
 CONFIG_ESP_WIFI_NVS_ENABLED=n
 
-CONFIG_LWIP_TCP_SND_BUF_DEFAULT=57600
+CONFIG_LWIP_TCP_SND_BUF_DEFAULT=50400
 CONFIG_LWIP_TCP_WND_DEFAULT=65535
 CONFIG_LWIP_TCP_RECVMBOX_SIZE=48
 CONFIG_LWIP_UDP_RECVMBOX_SIZE=64
diff --git a/examples/wifi/itwt/main/Kconfig.projbuild b/examples/wifi/itwt/main/Kconfig.projbuild
index 9eb0e46e7be..8d8dd52b2e1 100644
--- a/examples/wifi/itwt/main/Kconfig.projbuild
+++ b/examples/wifi/itwt/main/Kconfig.projbuild
@@ -38,6 +38,12 @@ menu "Example Configuration"
         help
             Set static gateway address.
 
+    config EXAMPLE_TWT_ENABLE_KEEP_ALIVE_QOS_NULL
+        bool "enable keep alive qos null"
+        default n
+        help
+            Enable send QOS NULL to keep alive during TWT.
+
     menu "iTWT Configuration"
         config EXAMPLE_ITWT_TRIGGER_ENABLE
             bool "trigger-enabled"
diff --git a/examples/wifi/itwt/main/itwt_main.c b/examples/wifi/itwt/main/itwt_main.c
index e2f4ecc7719..c1e44d8eb2f 100644
--- a/examples/wifi/itwt/main/itwt_main.c
+++ b/examples/wifi/itwt/main/itwt_main.c
@@ -49,6 +49,12 @@ static const char *TAG = "itwt";
 #define DEFAULT_PWD CONFIG_EXAMPLE_WIFI_PASSWORD
 #define ITWT_SETUP_SUCCESS 1
 
+#if CONFIG_EXAMPLE_TWT_ENABLE_KEEP_ALIVE_QOS_NULL
+bool keep_alive_enabled = true;
+#else
+bool keep_alive_enabled = false;
+#endif
+
 #if CONFIG_EXAMPLE_ITWT_TRIGGER_ENABLE
 uint8_t trigger_enabled = 1;
 #else
@@ -264,6 +270,12 @@ static void wifi_itwt(void)
     ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA));
     ESP_ERROR_CHECK(esp_wifi_set_config(WIFI_IF_STA, &wifi_config));
 
+    wifi_twt_config_t wifi_twt_config = {
+        .post_wakeup_event = false,
+        .twt_enable_keep_alive = keep_alive_enabled,
+    };
+    ESP_ERROR_CHECK(esp_wifi_sta_twt_config(&wifi_twt_config));
+
     esp_wifi_set_bandwidth(WIFI_IF_STA, WIFI_BW_HT20);
     esp_wifi_set_protocol(WIFI_IF_STA, WIFI_PROTOCOL_11B | WIFI_PROTOCOL_11G | WIFI_PROTOCOL_11N | WIFI_PROTOCOL_11AX);
     esp_wifi_set_ps(WIFI_PS_MIN_MODEM);
diff --git a/examples/wifi/scan/main/scan.c b/examples/wifi/scan/main/scan.c
index 243b4a7a98f..2dd34ff907a 100644
--- a/examples/wifi/scan/main/scan.c
+++ b/examples/wifi/scan/main/scan.c
@@ -22,7 +22,7 @@
 #define DEFAULT_SCAN_LIST_SIZE CONFIG_EXAMPLE_SCAN_LIST_SIZE
 
 #ifdef CONFIG_EXAMPLE_USE_SCAN_CHANNEL_BITMAP
-#define USE_CHANNEL_BTIMAP 1
+#define USE_CHANNEL_BITMAP 1
 #define CHANNEL_LIST_SIZE 3
 static uint8_t channel_list[CHANNEL_LIST_SIZE] = {1, 6, 11};
 #endif /*CONFIG_EXAMPLE_USE_SCAN_CHANNEL_BITMAP*/
@@ -59,6 +59,12 @@ static void print_auth_mode(int authmode)
     case WIFI_AUTH_WPA2_WPA3_PSK:
         ESP_LOGI(TAG, "Authmode \tWIFI_AUTH_WPA2_WPA3_PSK");
         break;
+    case WIFI_AUTH_WPA3_ENTERPRISE:
+        ESP_LOGI(TAG, "Authmode \tWIFI_AUTH_WPA3_ENTERPRISE");
+        break;
+    case WIFI_AUTH_WPA2_WPA3_ENTERPRISE:
+        ESP_LOGI(TAG, "Authmode \tWIFI_AUTH_WPA2_WPA3_ENTERPRISE");
+        break;
     case WIFI_AUTH_WPA3_ENT_192:
         ESP_LOGI(TAG, "Authmode \tWIFI_AUTH_WPA3_ENT_192");
         break;
@@ -140,7 +146,7 @@ static void print_cipher_type(int pairwise_cipher, int group_cipher)
     }
 }
 
-#ifdef USE_CHANNEL_BTIMAP
+#ifdef USE_CHANNEL_BITMAP
 static void array_2_channel_bitmap(const uint8_t channel_list[], const uint8_t channel_list_size, wifi_scan_config_t *scan_config) {
 
     for(uint8_t i = 0; i < channel_list_size; i++) {
@@ -148,7 +154,7 @@ static void array_2_channel_bitmap(const uint8_t channel_list[], const uint8_t c
         scan_config->channel_bitmap.ghz_2_channels |= (1 << channel);
     }
 }
-#endif /*USE_CHANNEL_BTIMAP*/
+#endif /*USE_CHANNEL_BITMAP*/
 
 
 /* Initialize Wi-Fi as sta and set scan method */
@@ -171,7 +177,7 @@ static void wifi_scan(void)
     ESP_ERROR_CHECK(esp_wifi_set_mode(WIFI_MODE_STA));
     ESP_ERROR_CHECK(esp_wifi_start());
 
-#ifdef USE_CHANNEL_BTIMAP
+#ifdef USE_CHANNEL_BITMAP
     wifi_scan_config_t *scan_config = (wifi_scan_config_t *)calloc(1,sizeof(wifi_scan_config_t));
     if (!scan_config) {
         ESP_LOGE(TAG, "Memory Allocation for scan config failed!");
@@ -183,7 +189,7 @@ static void wifi_scan(void)
 
 #else
     esp_wifi_scan_start(NULL, true);
-#endif /*USE_CHANNEL_BTIMAP*/
+#endif /*USE_CHANNEL_BITMAP*/
 
     ESP_LOGI(TAG, "Max AP number ap_info can hold = %u", number);
     ESP_ERROR_CHECK(esp_wifi_scan_get_ap_num(&ap_count));
diff --git a/examples/zigbee/.build-test-rules.yml b/examples/zigbee/.build-test-rules.yml
index 793bc65b937..eb8c7d7bccd 100644
--- a/examples/zigbee/.build-test-rules.yml
+++ b/examples/zigbee/.build-test-rules.yml
@@ -8,28 +8,15 @@
 
 examples/zigbee/esp_zigbee_gateway:
   enable:
-    - if: SOC_WIFI_SUPPORTED == 1 and IDF_TARGET not in ["esp32c2", "esp32c5", "esp32c61"]
-      reason: not supported esp32c2 and esp32c5 and esp32c61
-  <<: *zigbee_dependencies
-
-examples/zigbee/esp_zigbee_rcp:
-  enable:
-    - if: SOC_IEEE802154_SUPPORTED == 1
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: Not supported yet
+    - if: SOC_WIFI_SUPPORTED == 1 and IDF_TARGET not in ["esp32c2", "esp32c61"]
+      reason: not supported esp32c2 and esp32c61
   <<: *zigbee_dependencies
 
 examples/zigbee/light_sample:
   enable:
     - if: SOC_IEEE802154_SUPPORTED == 1
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: Not supported yet
   disable_test:
-    - if: IDF_TARGET == "esp32c6"
+    - if: IDF_TARGET != "esp32h2"
       temporary: true
       reason: only test on esp32h2
   <<: *zigbee_dependencies
diff --git a/examples/zigbee/common/zcl_utility/include/zcl_utility.h b/examples/zigbee/common/zcl_utility/include/zcl_utility.h
new file mode 100644
index 00000000000..760bf7e10b5
--- /dev/null
+++ b/examples/zigbee/common/zcl_utility/include/zcl_utility.h
@@ -0,0 +1,51 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: LicenseRef-Included
+ *
+ * Zigbee Common
+ *
+ * This example code is in the Public Domain (or CC0 licensed, at your option.)
+ *
+ * Unless required by applicable law or agreed to in writing, this
+ * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied.
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp_err.h"
+#include "esp_check.h"
+#include "esp_zigbee_core.h"
+
+/*! Maximum length of ManufacturerName string field */
+#define ESP_ZB_ZCL_CLUSTER_ID_BASIC_MANUFACTURER_NAME_MAX_LEN 32
+
+/*! Maximum length of ModelIdentifier string field */
+#define ESP_ZB_ZCL_CLUSTER_ID_BASIC_MODEL_IDENTIFIER_MAX_LEN 32
+
+/** optional basic manufacturer information */
+typedef struct zcl_basic_manufacturer_info_s {
+    char *manufacturer_name;
+    char *model_identifier;
+} zcl_basic_manufacturer_info_t;
+
+/**
+ * @brief Adds manufacturer information to the ZCL basic cluster of endpoint
+ *
+ * @param[in] ep_list The pointer to the endpoint list with @p endpoint_id
+ * @param[in] endpoint_id The endpoint identifier indicating where the ZCL basic cluster resides
+ * @param[in] info The pointer to the basic manufacturer information
+ * @return
+ *      - ESP_OK: On success
+ *      - ESP_ERR_INVALID_ARG: Invalid argument
+ */
+esp_err_t esp_zcl_utility_add_ep_basic_manufacturer_info(esp_zb_ep_list_t *ep_list, uint8_t endpoint_id, zcl_basic_manufacturer_info_t *info);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
diff --git a/examples/zigbee/common/zcl_utility/src/zcl_utility.c b/examples/zigbee/common/zcl_utility/src/zcl_utility.c
new file mode 100644
index 00000000000..c88d6cd8bc8
--- /dev/null
+++ b/examples/zigbee/common/zcl_utility/src/zcl_utility.c
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: LicenseRef-Included
+ *
+ * Zigbee Common
+ *
+ * This example code is in the Public Domain (or CC0 licensed, at your option.)
+ *
+ * Unless required by applicable law or agreed to in writing, this
+ * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied.
+ */
+#include "esp_check.h"
+#include "stdio.h"
+#include "string.h"
+#include "zcl_utility.h"
+#include <stdint.h>
+
+static const char *TAG = "ZCL_UTILITY";
+
+esp_err_t esp_zcl_utility_add_ep_basic_manufacturer_info(esp_zb_ep_list_t *ep_list, uint8_t endpoint_id, zcl_basic_manufacturer_info_t *info)
+{
+    esp_err_t ret = ESP_OK;
+    esp_zb_cluster_list_t *cluster_list = NULL;
+    esp_zb_attribute_list_t *basic_cluster = NULL;
+
+    cluster_list = esp_zb_ep_list_get_ep(ep_list, endpoint_id);
+    ESP_RETURN_ON_FALSE(cluster_list, ESP_ERR_INVALID_ARG, TAG, "Failed to find endpoint id: %d in list: %p", endpoint_id, ep_list);
+    basic_cluster = esp_zb_cluster_list_get_cluster(cluster_list, ESP_ZB_ZCL_CLUSTER_ID_BASIC, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+    ESP_RETURN_ON_FALSE(basic_cluster, ESP_ERR_INVALID_ARG, TAG, "Failed to find basic cluster in endpoint: %d", endpoint_id);
+    ESP_RETURN_ON_FALSE((info && info->manufacturer_name), ESP_ERR_INVALID_ARG, TAG, "Invalid manufacturer name");
+    ESP_ERROR_CHECK(esp_zb_basic_cluster_add_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_MANUFACTURER_NAME_ID, info->manufacturer_name));
+    ESP_RETURN_ON_FALSE((info && info->model_identifier), ESP_ERR_INVALID_ARG, TAG, "Invalid model identifier");
+    ESP_ERROR_CHECK(esp_zb_basic_cluster_add_attr(basic_cluster, ESP_ZB_ZCL_ATTR_BASIC_MODEL_IDENTIFIER_ID, info->model_identifier));
+    return ret;
+}
diff --git a/examples/zigbee/esp_zigbee_gateway/README.md b/examples/zigbee/esp_zigbee_gateway/README.md
index 1a6fadfe8f3..e313e611e9c 100644
--- a/examples/zigbee/esp_zigbee_gateway/README.md
+++ b/examples/zigbee/esp_zigbee_gateway/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
 
 # Gateway Example
 
@@ -13,7 +13,7 @@ The ESP Zigbee SDK provides more examples and tools for productization:
 
 By default, two SoCs are required to run this example:
 * An ESP32 series Wi-Fi SoC (ESP32, ESP32-C, ESP32-S, etc) loaded with this esp_zigbee_gateway example.
-* An ESP32-H2 802.15.4 SoC loaded with [esp_zigbee_rcp](../esp_zigbee_rcp) example
+* An ESP32-H2 802.15.4 SoC loaded with [ot_rcp](../../openthread/ot_rcp/) example
 
 Connect the two SoCs via UART, below is an example setup with ESP32-DevKitC and ESP32-H2-DevKitC:
 ![Zigbee_gateway](../../openthread/ot_br/image/thread-border-router-esp32-esp32h2.jpg)
@@ -28,6 +28,10 @@ ESP32 pin     | ESP32-H2 pin
 
 The example could also run on a single SoC which supports both Wi-Fi and Zigbee (e.g., ESP32-C6), but since there is only one RF path in ESP32-C6, which means Wi-Fi and Zigbee can't receive simultaneously, it has a significant impact on performance. Hence the two SoCs solution is recommended.
 
+## Configure the RCP
+
+The `OPENTHREAD_NCP_VENDOR_HOOK` of `ot_rcp` should be selected via menuconfig when the [ot_rcp](../../openthread/ot_rcp/) example is built. Then use `idf.py -p PORT erase-flash` to flash the RCP firmware to ESP32-H2-DevKitC.
+
 ## Configure the project
 
 Before project configuration and build, make sure to set the correct chip target using `idf.py set-target <chip_name>`.
@@ -50,19 +54,80 @@ As you run the example, you will see the following log:
 
 esp_zigbee_gateway:
 ```
-I (660) ESP_ZB_GATEWAY: status: -1
-I (670) ESP_ZB_GATEWAY: Zigbee stack initialized
-I (680) ESP_ZB_GATEWAY: Zigbee rcp device booted
-I (1280) ESP_ZB_GATEWAY: Start network formation
-I (3060) ESP_ZB_GATEWAY: Formed network successfully (Extended PAN ID: f9:54:2d:01:a0:03:f7:84, PAN ID: 0x8651, Channel:13, Short Address: 0x0000)
-I (4060) ESP_ZB_GATEWAY: status: 0
-I (4400) ESP_ZB_GATEWAY: Network steering started
+I (499) main_task: Calling app_main()
+I (519) ESP_RADIO_SPINEL: spinel UART interface initialization completed
+I (519) ESP_RADIO_SPINEL: Spinel UART interface has been successfully enabled
+I (519) ZB_ESP_SPINEL: Spinel UART interface enable successfully
+I (529) main_task: Returned from app_main()
+I(529) OPENTHREAD:[I] P-RadioSpinel-: RCP reset: RESET_POWER_ON
+I(539) OPENTHREAD:[I] P-RadioSpinel-: Software reset RCP successfully
+I (569) ZB_ESP_SPINEL: Radio spinel workflow register successfully
+I (769) ESP_ZB_GATEWAY: Production configuration is ready
+W (769) ESP_ZB_GATEWAY: Production configuration is not present
+I (769) example_connect: Start example_connect.
+I (779) pp: pp rom version: e7ae62f
+I (779) net80211: net80211 rom version: e7ae62f
+I (799) wifi:wifi driver task: 3fca80d8, prio:23, stack:6656, core=0
+I (799) wifi:wifi firmware version: 3ce09e5
+I (799) wifi:wifi certification version: v7.0
+I (799) wifi:config NVS flash: enabled
+I (799) wifi:config nano formatting: disabled
+I (809) wifi:Init data frame dynamic rx buffer num: 32
+I (809) wifi:Init static rx mgmt buffer num: 5
+I (819) wifi:Init management short buffer num: 32
+I (819) wifi:Init dynamic tx buffer num: 32
+I (819) wifi:Init static tx FG buffer num: 2
+I (829) wifi:Init static rx buffer size: 1600
+I (829) wifi:Init static rx buffer num: 10
+I (839) wifi:Init dynamic rx buffer num: 32
+I (839) wifi_init: rx ba win: 6
+I (839) wifi_init: tcpip mbox: 32
+I (849) wifi_init: udp mbox: 6
+I (849) wifi_init: tcp mbox: 6
+I (849) wifi_init: tcp tx win: 5760
+I (859) wifi_init: tcp rx win: 5760
+I (859) wifi_init: tcp mss: 1440
+I (869) wifi_init: WiFi IRAM OP enabled
+I (869) wifi_init: WiFi RX IRAM OP enabled
+I (879) phy_init: phy_version 670,b7bc9b9,Apr 30 2024,10:54:13
+W (879) phy_init: failed to load RF calibration data (0x1102), falling back to full calibration
+I (989) wifi:mode : sta (f4:12:fa:41:a7:f4)
+I (989) wifi:enable tsf
+I (999) example_connect: Connecting to esp-office-2.4G...
+I (999) example_connect: Waiting for IP(s)
+I (3409) wifi:new:<13,0>, old:<1,0>, ap:<255,255>, sta:<13,0>, prof:1
+I (3649) wifi:state: init -> auth (b0)
+I (3719) wifi:state: auth -> assoc (0)
+I (3759) wifi:state: assoc -> run (10)
+I (3769) wifi:connected with esp-office-2.4G, aid = 1, channel 13, BW20, bssid = 9c:3a:9a:04:18:92
+I (3769) wifi:security: WPA2-PSK, phy: bgn, rssi: -42
+I (3769) wifi:pm start, type: 1
+
+I (3779) wifi:dp: 1, bi: 102400, li: 3, scale listen interval from 307200 us to 307200 us
+I (3789) wifi:set rx beacon pti, rx_bcn_pti: 0, bcn_timeout: 25000, mt_pti: 0, mt_time: 10000
+I (3819) wifi:AP's beacon interval = 102400 us, DTIM period = 1
+I (3849) wifi:<ba-add>idx:0 (ifx:0, 9c:3a:9a:04:18:92), tid:0, ssn:0, winSize:64
+I (4799) esp_netif_handlers: example_netif_sta ip: 192.168.200.133, mask: 255.255.252.0, gw: 192.168.200.1
+I (4799) example_connect: Got IPv4 event: Interface "example_netif_sta" address: 192.168.200.133
+I (5509) example_connect: Got IPv6 event: Interface "example_netif_sta" address: fe80:0000:0000:0000:f612:faff:fe41:a7f4, type: ESP_IP6_ADDR_IS_LINK_LOCAL
+I (5509) example_common: Connected to example_netif_sta
+I (5519) example_common: - IPv4 address: 192.168.200.133,
+I (5519) example_common: - IPv6 address: fe80:0000:0000:0000:f612:faff:fe41:a7f4, type: ESP_IP6_ADDR_IS_LINK_LOCAL
+I (5529) wifi:Set ps type: 0, coexist: 0
+
+I (5539) ESP_ZB_GATEWAY: Initialize Zigbee stack
+I (5549) ESP_ZB_GATEWAY: Device started up in  factory-reset mode
+I (5549) ESP_ZB_GATEWAY: Start network formation
+W (5729) ESP_ZB_GATEWAY: Network(0xb8e9) closed, devices joining not allowed.
+I (5729) ESP_ZB_GATEWAY: Formed network successfully (Extended PAN ID: 60:55:f9:ff:fe:f7:73:e8, PAN ID: 0xb8e9, Channel:13, Short Address: 0x0000)
+I (6339) ESP_ZB_GATEWAY: Network(0xb8e9) is open for 180 seconds
+I (6339) ESP_ZB_GATEWAY: Network steering started
 ```
 
 ## Gateway Functions
 
- * After Zigbee gateway starts up, it will read MAC ieee address and Zigbee stack version number from the Zigbee rcp and start working together with Zigbee rcp via UART communication to form a Zigbee network
- * More Gateway functionalities supporting Wi-Fi interaction will come later
+ * When the device starts up, it will attempt to connect to a Wi-Fi network and then interface with the OT-RCP via UART to form a Zigbee network.
+ * For more Gateway functionalities, please refer to [matter zigbee bridge](https://github.com/espressif/esp-matter/tree/main/examples/bridge_apps/zigbee_bridge/) and [Rainmaker Zigbee Gateway](https://github.com/espressif/esp-rainmaker/tree/master/examples/zigbee_gateway) examples.
 
 ## Troubleshooting
 
diff --git a/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c b/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c
index b5fedf4587a..a0eb05f9500 100644
--- a/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c
+++ b/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.c
@@ -1,7 +1,7 @@
 /*
  * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: CC0-1.0
+ * SPDX-License-Identifier: LicenseRef-Included
  *
  * Zigbee Gateway Example
  *
@@ -17,20 +17,17 @@
 #include "freertos/task.h"
 #include "driver/usb_serial_jtag.h"
 #include "esp_coexist.h"
+#include "esp_check.h"
 #include "esp_log.h"
 #include "esp_netif.h"
+#include "esp_vfs_dev.h"
+#include "esp_vfs_usb_serial_jtag.h"
 #include "esp_vfs_eventfd.h"
 #include "esp_wifi.h"
 #include "nvs_flash.h"
 #include "protocol_examples_common.h"
 #include "esp_zigbee_gateway.h"
-
-#include "driver/uart_vfs.h"
-#include "driver/usb_serial_jtag_vfs.h"
-
-#if (!defined ZB_MACSPLIT_HOST && defined ZB_MACSPLIT_DEVICE)
-#error Only Zigbee gateway host device should be defined
-#endif
+#include "zb_config_platform.h"
 
 static const char *TAG = "ESP_ZB_GATEWAY";
 
@@ -61,7 +58,7 @@ esp_err_t esp_zb_gateway_console_init(void)
 
 static void bdb_start_top_level_commissioning_cb(uint8_t mode_mask)
 {
-    ESP_ERROR_CHECK(esp_zb_bdb_start_top_level_commissioning(mode_mask));
+    ESP_RETURN_ON_FALSE(esp_zb_bdb_start_top_level_commissioning(mode_mask) == ESP_OK, , TAG, "Failed to start Zigbee bdb commissioning");
 }
 
 void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct)
@@ -70,18 +67,19 @@ void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct)
     esp_err_t err_status = signal_struct->esp_err_status;
     esp_zb_app_signal_type_t sig_type = *p_sg_p;
     esp_zb_zdo_signal_device_annce_params_t *dev_annce_params = NULL;
-    esp_zb_zdo_signal_macsplit_dev_boot_params_t *rcp_version = NULL;
 
     switch (sig_type) {
     case ESP_ZB_ZDO_SIGNAL_SKIP_STARTUP:
-        ESP_LOGI(TAG, "Zigbee stack initialized");
+#if CONFIG_EXAMPLE_CONNECT_WIFI
+#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE
+        esp_coex_wifi_i154_enable();
+#endif /* CONFIG_ESP_COEX_SW_COEXIST_ENABLE */
+        ESP_RETURN_ON_FALSE(example_connect() == ESP_OK, , TAG, "Failed to connect to Wi-Fi");
+        ESP_RETURN_ON_FALSE(esp_wifi_set_ps(WIFI_PS_MIN_MODEM) == ESP_OK, , TAG, "Failed to set Wi-Fi minimum modem power save type");
+#endif /* CONFIG_EXAMPLE_CONNECT_WIFI */
+        ESP_LOGI(TAG, "Initialize Zigbee stack");
         esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_INITIALIZATION);
         break;
-    case ESP_ZB_MACSPLIT_DEVICE_BOOT:
-        ESP_LOGI(TAG, "Zigbee rcp device booted");
-        rcp_version = (esp_zb_zdo_signal_macsplit_dev_boot_params_t *)esp_zb_app_signal_get_params(p_sg_p);
-        ESP_LOGI(TAG, "Running RCP Version: %s", rcp_version->version_str);
-        break;
     case ESP_ZB_BDB_SIGNAL_DEVICE_FIRST_START:
     case ESP_ZB_BDB_SIGNAL_DEVICE_REBOOT:
         if (err_status == ESP_OK) {
@@ -90,6 +88,7 @@ void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct)
                 ESP_LOGI(TAG, "Start network formation");
                 esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_NETWORK_FORMATION);
             } else {
+                esp_zb_bdb_open_network(180);
                 ESP_LOGI(TAG, "Device rebooted");
             }
         } else {
@@ -128,6 +127,10 @@ void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct)
             }
         }
         break;
+    case ESP_ZB_ZDO_SIGNAL_PRODUCTION_CONFIG_READY:
+        ESP_LOGI(TAG, "Production configuration is %s", err_status == ESP_OK ? "ready" : "not present");
+        esp_zb_set_node_descriptor_manufacturer_code(ESP_MANUFACTURER_CODE);
+        break;
     default:
         ESP_LOGI(TAG, "ZDO signal: %s (0x%x), status: %s", esp_zb_zdo_signal_to_string(sig_type), sig_type,
                  esp_err_to_name(err_status));
@@ -141,8 +144,25 @@ static void esp_zb_task(void *pvParameters)
     esp_zb_cfg_t zb_nwk_cfg = ESP_ZB_ZC_CONFIG();
     esp_zb_init(&zb_nwk_cfg);
     esp_zb_set_primary_network_channel_set(ESP_ZB_PRIMARY_CHANNEL_MASK);
+    esp_zb_ep_list_t *ep_list = esp_zb_ep_list_create();
+    esp_zb_cluster_list_t *cluster_list = esp_zb_zcl_cluster_list_create();
+    esp_zb_endpoint_config_t endpoint_config = {
+        .endpoint = ESP_ZB_GATEWAY_ENDPOINT,
+        .app_profile_id = ESP_ZB_AF_HA_PROFILE_ID,
+        .app_device_id = ESP_ZB_HA_REMOTE_CONTROL_DEVICE_ID,
+        .app_device_version = 0,
+    };
+
+    esp_zb_attribute_list_t *basic_cluser = esp_zb_basic_cluster_create(NULL);
+    esp_zb_basic_cluster_add_attr(basic_cluser, ESP_ZB_ZCL_ATTR_BASIC_MANUFACTURER_NAME_ID, ESP_MANUFACTURER_NAME);
+    esp_zb_basic_cluster_add_attr(basic_cluser, ESP_ZB_ZCL_ATTR_BASIC_MODEL_IDENTIFIER_ID, ESP_MODEL_IDENTIFIER);
+    esp_zb_cluster_list_add_basic_cluster(cluster_list, basic_cluser, ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+    esp_zb_cluster_list_add_identify_cluster(cluster_list, esp_zb_identify_cluster_create(NULL), ESP_ZB_ZCL_CLUSTER_SERVER_ROLE);
+    esp_zb_ep_list_add_gateway_ep(ep_list, cluster_list, endpoint_config);
+    esp_zb_device_register(ep_list);
     ESP_ERROR_CHECK(esp_zb_start(false));
-    esp_zb_main_loop_iteration();
+    esp_zb_stack_main_loop();
+    vTaskDelete(NULL);
 }
 
 void app_main(void)
@@ -159,14 +179,5 @@ void app_main(void)
 #if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG
     ESP_ERROR_CHECK(esp_zb_gateway_console_init());
 #endif
-#if CONFIG_EXAMPLE_CONNECT_WIFI
-    ESP_ERROR_CHECK(example_connect());
-#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE
-    ESP_ERROR_CHECK(esp_wifi_set_ps(WIFI_PS_MIN_MODEM));
-    esp_coex_wifi_i154_enable();
-#else
-    ESP_ERROR_CHECK(esp_wifi_set_ps(WIFI_PS_NONE));
-#endif
-#endif
-    xTaskCreate(esp_zb_task, "Zigbee_main", 4096, NULL, 5, NULL);
+    xTaskCreate(esp_zb_task, "Zigbee_main", 8192, NULL, 5, NULL);
 }
diff --git a/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.h b/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.h
index 2bc61f0e2bd..03a880bb59c 100644
--- a/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.h
+++ b/examples/zigbee/esp_zigbee_gateway/main/esp_zigbee_gateway.h
@@ -1,7 +1,7 @@
 /*
  * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: CC0-1.0
+ * SPDX-License-Identifier: LicenseRef-Included
  *
  * Zigbee Gateway Example
  *
@@ -19,6 +19,17 @@
 #define MAX_CHILDREN                    10          /* the max amount of connected devices */
 #define INSTALLCODE_POLICY_ENABLE       false       /* enable the install code policy for security */
 #define ESP_ZB_PRIMARY_CHANNEL_MASK     (1l << 13)  /* Zigbee primary channel mask use in the example */
+#define ESP_ZB_GATEWAY_ENDPOINT         1           /* Gateway endpoint identifier */
+#define APP_PROD_CFG_CURRENT_VERSION    0x0001      /* Production configuration version */
+
+/* Basic manufacturer information */
+#define ESP_MANUFACTURER_CODE 0x131B                 /* Customized manufacturer code */
+#define ESP_MANUFACTURER_NAME "\x09""ESPRESSIF"      /* Customized manufacturer name */
+#define ESP_MODEL_IDENTIFIER "\x07"CONFIG_IDF_TARGET /* Customized model identifier */
+
+/* RCP connection pins */
+#define HOST_RX_PIN_TO_RCP_TX 4
+#define HOST_TX_PIN_TO_RCP_RX 5
 
 #define ESP_ZB_ZC_CONFIG()                                                              \
     {                                                                                   \
@@ -32,17 +43,17 @@
 #if CONFIG_ZB_RADIO_NATIVE
 #define ESP_ZB_DEFAULT_RADIO_CONFIG()                           \
     {                                                           \
-        .radio_mode = RADIO_MODE_NATIVE,                        \
+        .radio_mode = ZB_RADIO_MODE_NATIVE,                     \
     }
 #else
 #define ESP_ZB_DEFAULT_RADIO_CONFIG()                           \
     {                                                           \
-        .radio_mode = RADIO_MODE_UART_RCP,                      \
+        .radio_mode = ZB_RADIO_MODE_UART_RCP,                   \
             .radio_uart_config = {                              \
             .port = 1,                                          \
             .uart_config =                                      \
                 {                                               \
-                    .baud_rate = 115200,                        \
+                    .baud_rate = 460800,                        \
                     .data_bits = UART_DATA_8_BITS,              \
                     .parity = UART_PARITY_DISABLE,              \
                     .stop_bits = UART_STOP_BITS_1,              \
@@ -50,13 +61,13 @@
                     .rx_flow_ctrl_thresh = 0,                   \
                     .source_clk = UART_SCLK_DEFAULT,            \
                 },                                              \
-            .rx_pin = 4,                                        \
-            .tx_pin = 5,                                        \
+            .rx_pin = HOST_RX_PIN_TO_RCP_TX,                    \
+            .tx_pin = HOST_TX_PIN_TO_RCP_RX,                    \
         },                                                      \
     }
 #endif
 
 #define ESP_ZB_DEFAULT_HOST_CONFIG()                            \
     {                                                           \
-        .host_connection_mode = HOST_CONNECTION_MODE_NONE,      \
+        .host_connection_mode = ZB_HOST_CONNECTION_MODE_NONE,   \
     }
diff --git a/examples/zigbee/esp_zigbee_gateway/main/idf_component.yml b/examples/zigbee/esp_zigbee_gateway/main/idf_component.yml
index 5346a089ab5..d3a34266983 100644
--- a/examples/zigbee/esp_zigbee_gateway/main/idf_component.yml
+++ b/examples/zigbee/esp_zigbee_gateway/main/idf_component.yml
@@ -1,7 +1,7 @@
 ## IDF Component Manager Manifest File
 dependencies:
-  espressif/esp-zboss-lib: "1.0.9"
-  espressif/esp-zigbee-lib: "1.0.9"
+  espressif/esp-zboss-lib: "~1.6.0"
+  espressif/esp-zigbee-lib: "~1.6.0"
   ## Required IDF version
   idf:
     version: ">=5.0.0"
diff --git a/examples/zigbee/esp_zigbee_rcp/CMakeLists.txt b/examples/zigbee/esp_zigbee_rcp/CMakeLists.txt
deleted file mode 100644
index 6cf79c44b31..00000000000
--- a/examples/zigbee/esp_zigbee_rcp/CMakeLists.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# For more information about build system see
-# https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/build-system.html
-# The following five lines of boilerplate have to be in your project's
-# CMakeLists in this exact order for cmake to work correctly
-cmake_minimum_required(VERSION 3.16)
-include($ENV{IDF_PATH}/tools/cmake/project.cmake)
-project(esp_zigbee_rcp)
diff --git a/examples/zigbee/esp_zigbee_rcp/README.md b/examples/zigbee/esp_zigbee_rcp/README.md
deleted file mode 100644
index a930b7fc814..00000000000
--- a/examples/zigbee/esp_zigbee_rcp/README.md
+++ /dev/null
@@ -1,34 +0,0 @@
-| Supported Targets | ESP32-C6 | ESP32-H2 |
-| ----------------- | -------- | -------- |
-
-# Rcp Example
-
-This test code shows how to configure Zigbee rcp (radio co-processor) device. Rcp doesn't function alone, it needs to work together with Zigbee gateway (see [esp_zigbee_gateway example](../esp_zigbee_gateway))
-
-## Hardware Required
-
-* One development board with ESP32-H2 SoC acting as Zigbee rcp (loaded with esp_zigbee_rcp example)
-* A USB cable for power supply and programming
-* Choose ESP32 or ESP32-S3 as Zigbee gateway. The connection and setup refer to the Zigbee gateway example for setup details (see [esp_zigbee_gateway example](../esp_zigbee_gateway))
-* TX, RX pin can be also configured by user in esp_zigbee_rcp.h
-
-## Configure the project
-
-Before project configuration and build, make sure to set the correct chip target using `idf.py --preview set-target TARGET` command.
-
-## Erase the NVRAM
-
-Before flash it to the board, it is recommended to erase NVRAM if user doesn't want to keep the previous examples or other projects stored info using `idf.py -p PORT erase-flash`
-
-## Build and Flash
-
-Build the project, flash it to the board by running `idf.py -p <PORT> build flash`
-
-## Rcp Functions
-
- * After rcp starts up, it will send its own MAC ieee address and Zigbee stack version number to the Zigbee gateway and start working together with Zigbee gateway via UART communication
- * For more log info please see Zigbee gateway side
-
-## Troubleshooting
-
-For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon
diff --git a/examples/zigbee/esp_zigbee_rcp/main/CMakeLists.txt b/examples/zigbee/esp_zigbee_rcp/main/CMakeLists.txt
deleted file mode 100644
index fe9c25c12f1..00000000000
--- a/examples/zigbee/esp_zigbee_rcp/main/CMakeLists.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-idf_component_register(SRCS "esp_zigbee_rcp.c"
-                    INCLUDE_DIRS ".")
diff --git a/examples/zigbee/esp_zigbee_rcp/main/esp_zigbee_rcp.c b/examples/zigbee/esp_zigbee_rcp/main/esp_zigbee_rcp.c
deleted file mode 100644
index 2c419ab68db..00000000000
--- a/examples/zigbee/esp_zigbee_rcp/main/esp_zigbee_rcp.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: CC0-1.0
- *
- * Zigbee RCP Example
- *
- * This example code is in the Public Domain (or CC0 licensed, at your option.)
- *
- * Unless required by applicable law or agreed to in writing, this
- * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
- * CONDITIONS OF ANY KIND, either express or implied.
- */
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/task.h"
-#include "esp_log.h"
-#include "nvs_flash.h"
-#include "zb_scheduler.h"
-#include "esp_zigbee_rcp.h"
-
-#if (defined ZB_MACSPLIT_HOST && !defined ZB_MACSPLIT_DEVICE)
-#error Only Zigbee rcp device should be defined
-#endif
-static const char *TAG = "ESP_ZB_RCP";
-
-void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct)
-{
-    uint32_t *p_sg_p       = signal_struct->p_app_signal;
-    esp_err_t err_status = signal_struct->esp_err_status;
-    esp_zb_app_signal_type_t sig_type = *p_sg_p;
-    if (err_status == ESP_OK) {
-    } else if (sig_type == ESP_ZB_ZDO_SIGNAL_PRODUCTION_CONFIG_READY) {
-        ESP_LOGI(TAG, "Production config is not present or invalid");
-    } else {
-        ESP_LOGI(TAG, "Device started FAILED status %d", err_status);
-    }
-}
-
-static void esp_zb_task(void *pvParameters)
-{
-    esp_zb_rcp_init();
-    esp_zb_rcp_main_loop_iteration();
-}
-
-void app_main(void)
-{
-    esp_zb_platform_config_t config = {
-        .radio_config = ESP_ZB_DEFAULT_RADIO_CONFIG(),
-        .host_config = ESP_ZB_DEFAULT_HOST_CONFIG(),
-    };
-    ESP_ERROR_CHECK(nvs_flash_init());
-    /* load Zigbee rcp platform config to initialization */
-    esp_zb_macsplit_set_version(RCP_COMPILE_DEFINE);
-    ESP_ERROR_CHECK(esp_zb_platform_config(&config));
-    xTaskCreate(esp_zb_task, "Zigbee_main", 4096, NULL, 5, NULL);
-}
diff --git a/examples/zigbee/esp_zigbee_rcp/main/esp_zigbee_rcp.h b/examples/zigbee/esp_zigbee_rcp/main/esp_zigbee_rcp.h
deleted file mode 100644
index c8f59a51a31..00000000000
--- a/examples/zigbee/esp_zigbee_rcp/main/esp_zigbee_rcp.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: CC0-1.0
- *
- * Zigbee RCP Example
- *
- * This example code is in the Public Domain (or CC0 licensed, at your option.)
- *
- * Unless required by applicable law or agreed to in writing, this
- * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
- * CONDITIONS OF ANY KIND, either express or implied.
- */
-#include "esp_zigbee_core.h"
-
-#define ESP_ZB_DEFAULT_RADIO_CONFIG()                           \
-    {                                                           \
-        .radio_mode = RADIO_MODE_NATIVE,                        \
-    }
-
-#define ESP_ZB_DEFAULT_HOST_CONFIG()                            \
-    {                                                           \
-        .host_connection_mode = HOST_CONNECTION_MODE_RCP_UART,  \
-        .host_uart_config = {                                   \
-            .port = 0,                                          \
-            .uart_config =                                      \
-                {                                               \
-                    .baud_rate = 115200,                        \
-                    .data_bits = UART_DATA_8_BITS,              \
-                    .parity = UART_PARITY_DISABLE,              \
-                    .stop_bits = UART_STOP_BITS_1,              \
-                    .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,      \
-                    .rx_flow_ctrl_thresh = 0,                   \
-                    .source_clk = UART_SCLK_DEFAULT,            \
-                },                                              \
-            .rx_pin = UART_PIN_NO_CHANGE,                       \
-            .tx_pin = UART_PIN_NO_CHANGE,                       \
-        },                                                      \
-    }
diff --git a/examples/zigbee/esp_zigbee_rcp/main/idf_component.yml b/examples/zigbee/esp_zigbee_rcp/main/idf_component.yml
deleted file mode 100644
index c186c3c8cad..00000000000
--- a/examples/zigbee/esp_zigbee_rcp/main/idf_component.yml
+++ /dev/null
@@ -1,7 +0,0 @@
-## IDF Component Manager Manifest File
-dependencies:
-  espressif/esp-zboss-lib: "1.0.9"
-  espressif/esp-zigbee-lib: "1.0.9"
-  ## Required IDF version
-  idf:
-    version: ">=5.0.0"
diff --git a/examples/zigbee/esp_zigbee_rcp/partitions.csv b/examples/zigbee/esp_zigbee_rcp/partitions.csv
deleted file mode 100644
index e72a9f10a23..00000000000
--- a/examples/zigbee/esp_zigbee_rcp/partitions.csv
+++ /dev/null
@@ -1,6 +0,0 @@
-# Name,   Type, SubType, Offset,  Size, Flags
-# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
-nvs,        data, nvs,      0x9000,  0x6000,
-phy_init,   data, phy,      0xf000,  0x1000,
-factory,    app,  factory,  0x10000, 548K,
-zb_storage, data, fat,      0x9a000, 16K,
diff --git a/examples/zigbee/esp_zigbee_rcp/sdkconfig.defaults b/examples/zigbee/esp_zigbee_rcp/sdkconfig.defaults
deleted file mode 100644
index b337975d5c9..00000000000
--- a/examples/zigbee/esp_zigbee_rcp/sdkconfig.defaults
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Partition Table
-#
-CONFIG_PARTITION_TABLE_CUSTOM=y
-CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
-CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
-CONFIG_PARTITION_TABLE_OFFSET=0x8000
-CONFIG_PARTITION_TABLE_MD5=y
-# end of Partition Table
-
-#
-# ZBOSS Source
-#
-CONFIG_ZB_ENABLED=y
-CONFIG_ZB_RCP=y
-# end of ZBOSS Source
-# end of Component config
diff --git a/examples/zigbee/light_sample/HA_on_off_light/README.md b/examples/zigbee/light_sample/HA_on_off_light/README.md
index a22052d6086..1078416c3ba 100644
--- a/examples/zigbee/light_sample/HA_on_off_light/README.md
+++ b/examples/zigbee/light_sample/HA_on_off_light/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C6 | ESP32-H2 |
-| ----------------- | -------- | -------- |
+| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- | -------- |
 
 # Light Bulb Example
 
@@ -34,24 +34,28 @@ Build the project, flash it to the board, and start the monitor tool to view the
 As you run the example, you will see the following log:
 
 ```
-I (394) main_task: Calling app_main()
-I (404) gpio: GPIO[8]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0
-I (404) phy_init: phy_version 220,2dbbbe7,Sep 25 2023,20:39:25
-I (464) phy: libbtbb version: 90c587c, Sep 25 2023, 20:39:57
-I (474) ESP_ZB_COLOR_DIMM_LIGHT: ZDO signal: ZDO Config Ready (0x17), status: ESP_FAIL
-I (474) ESP_ZB_COLOR_DIMM_LIGHT: Zigbee stack initialized
-I (484) ESP_ZB_COLOR_DIMM_LIGHT: Start network steering
-I (484) main_task: Returned from app_main()
-I (9614) ESP_ZB_COLOR_DIMM_LIGHT: ZDO signal: NWK Permit Join (0x36), status: ESP_OK
-I (9834) ESP_ZB_COLOR_DIMM_LIGHT: ZDO signal: NWK Permit Join (0x36), status: ESP_OK
-I (9834) ESP_ZB_COLOR_DIMM_LIGHT: Joined network successfully (Extended PAN ID: 60:55:f9:00:00:f6:07:b4, PAN ID: 0x2a74, Channel:13)
-I (32944) ESP_ZB_COLOR_DIMM_LIGHT: Received message: endpoint(10), cluster(0x6), attribute(0x0), data size(1)
-I (32944) ESP_ZB_COLOR_DIMM_LIGHT: Light sets to On
-I (33984) ESP_ZB_COLOR_DIMM_LIGHT: Received message: endpoint(10), cluster(0x6), attribute(0x0), data size(1)
-I (33984) ESP_ZB_COLOR_DIMM_LIGHT: Light sets to Off
-I (35304) ESP_ZB_COLOR_DIMM_LIGHT: ZDO signal: NLME Status Indication (0x32), status: ESP_OK
-I (35534) ESP_ZB_COLOR_DIMM_LIGHT: Received message: endpoint(10), cluster(0x6), attribute(0x0), data size(1)
-I (35534) ESP_ZB_COLOR_DIMM_LIGHT: Light sets to On
+I (403) app_start: Starting scheduler on CPU0
+I (408) main_task: Started on CPU0
+I (408) main_task: Calling app_main()
+I (428) phy: phy_version: 230,2, 9aae6ea, Jan 15 2024, 11:17:12
+I (428) phy: libbtbb version: 944f18e, Jan 15 2024, 11:17:25
+I (438) main_task: Returned from app_main()
+I (548) ESP_ZB_ON_OFF_LIGHT: ZDO signal: ZDO Config Ready (0x17), status: ESP_FAIL
+I (548) ESP_ZB_ON_OFF_LIGHT: Initialize Zigbee stack
+W (548) rmt: channel resolution loss, real=10666666
+I (558) gpio: GPIO[8]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0 
+I (548) ESP_ZB_ON_OFF_LIGHT: Deferred driver initialization successful
+I (568) ESP_ZB_ON_OFF_LIGHT: Device started up in  factory-reset mode
+I (578) ESP_ZB_ON_OFF_LIGHT: Start network steering
+I (3558) ESP_ZB_ON_OFF_LIGHT: Joined network successfully (Extended PAN ID: 74:4d:bd:ff:fe:63:f7:30, PAN ID: 0x13af, Channel:13, Short Address: 0x7c16)
+I (10238) ESP_ZB_ON_OFF_LIGHT: Received message: endpoint(10), cluster(0x6), attribute(0x0), data size(1)
+I (10238) ESP_ZB_ON_OFF_LIGHT: Light sets to On
+I (10798) ESP_ZB_ON_OFF_LIGHT: Received message: endpoint(10), cluster(0x6), attribute(0x0), data size(1)
+I (10798) ESP_ZB_ON_OFF_LIGHT: Light sets to Off
+I (11228) ESP_ZB_ON_OFF_LIGHT: Received message: endpoint(10), cluster(0x6), attribute(0x0), data size(1)
+I (11228) ESP_ZB_ON_OFF_LIGHT: Light sets to On
+I (11618) ESP_ZB_ON_OFF_LIGHT: Received message: endpoint(10), cluster(0x6), attribute(0x0), data size(1)
+I (11618) ESP_ZB_ON_OFF_LIGHT: Light sets to Off
 ```
 
 ## Light Control Functions
diff --git a/examples/zigbee/light_sample/HA_on_off_light/main/CMakeLists.txt b/examples/zigbee/light_sample/HA_on_off_light/main/CMakeLists.txt
index 61bef7bbbef..15343efb83c 100644
--- a/examples/zigbee/light_sample/HA_on_off_light/main/CMakeLists.txt
+++ b/examples/zigbee/light_sample/HA_on_off_light/main/CMakeLists.txt
@@ -1,6 +1,4 @@
 idf_component_register(
-    SRCS
-    "esp_zb_light.c"
-    "light_driver.c"
-    INCLUDE_DIRS "."
+    SRC_DIRS  "." "../../../common/zcl_utility/src"
+    INCLUDE_DIRS "." "../../../common/zcl_utility/include"
 )
diff --git a/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.c b/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.c
index a77ac5dc94f..4f3256c5578 100644
--- a/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.c
+++ b/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.c
@@ -1,7 +1,7 @@
 /*
  * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: CC0-1.0
+ * SPDX-License-Identifier:  LicenseRef-Included
  *
  * Zigbee HA_on_off_light Example
  *
@@ -11,7 +11,6 @@
  * software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  * CONDITIONS OF ANY KIND, either express or implied.
  */
-
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "esp_check.h"
@@ -26,9 +25,15 @@
 
 static const char *TAG = "ESP_ZB_ON_OFF_LIGHT";
 /********************* Define functions **************************/
+static esp_err_t deferred_driver_init(void)
+{
+    light_driver_init(LIGHT_DEFAULT_OFF);
+    return ESP_OK;
+}
+
 static void bdb_start_top_level_commissioning_cb(uint8_t mode_mask)
 {
-    ESP_ERROR_CHECK(esp_zb_bdb_start_top_level_commissioning(mode_mask));
+    ESP_RETURN_ON_FALSE(esp_zb_bdb_start_top_level_commissioning(mode_mask) == ESP_OK, , TAG, "Failed to start Zigbee commissioning");
 }
 
 void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct)
@@ -38,12 +43,13 @@ void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct)
     esp_zb_app_signal_type_t sig_type = *p_sg_p;
     switch (sig_type) {
     case ESP_ZB_ZDO_SIGNAL_SKIP_STARTUP:
-        ESP_LOGI(TAG, "Zigbee stack initialized");
+        ESP_LOGI(TAG, "Initialize Zigbee stack");
         esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_INITIALIZATION);
         break;
     case ESP_ZB_BDB_SIGNAL_DEVICE_FIRST_START:
     case ESP_ZB_BDB_SIGNAL_DEVICE_REBOOT:
         if (err_status == ESP_OK) {
+            ESP_LOGI(TAG, "Deferred driver initialization %s", deferred_driver_init() ? "failed" : "successful");
             ESP_LOGI(TAG, "Device started up in %s factory-reset mode", esp_zb_bdb_is_factory_new() ? "" : "non");
             if (esp_zb_bdb_is_factory_new()) {
                 ESP_LOGI(TAG, "Start network steering");
@@ -119,11 +125,17 @@ static void esp_zb_task(void *pvParameters)
     esp_zb_init(&zb_nwk_cfg);
     esp_zb_on_off_light_cfg_t light_cfg = ESP_ZB_DEFAULT_ON_OFF_LIGHT_CONFIG();
     esp_zb_ep_list_t *esp_zb_on_off_light_ep = esp_zb_on_off_light_ep_create(HA_ESP_LIGHT_ENDPOINT, &light_cfg);
+    zcl_basic_manufacturer_info_t info = {
+        .manufacturer_name = ESP_MANUFACTURER_NAME,
+        .model_identifier = ESP_MODEL_IDENTIFIER,
+    };
+
+    esp_zcl_utility_add_ep_basic_manufacturer_info(esp_zb_on_off_light_ep, HA_ESP_LIGHT_ENDPOINT, &info);
     esp_zb_device_register(esp_zb_on_off_light_ep);
     esp_zb_core_action_handler_register(zb_action_handler);
     esp_zb_set_primary_network_channel_set(ESP_ZB_PRIMARY_CHANNEL_MASK);
     ESP_ERROR_CHECK(esp_zb_start(false));
-    esp_zb_main_loop_iteration();
+    esp_zb_stack_main_loop();
 }
 
 void app_main(void)
@@ -134,6 +146,5 @@ void app_main(void)
     };
     ESP_ERROR_CHECK(nvs_flash_init());
     ESP_ERROR_CHECK(esp_zb_platform_config(&config));
-    light_driver_init(LIGHT_DEFAULT_OFF);
     xTaskCreate(esp_zb_task, "Zigbee_main", 4096, NULL, 5, NULL);
 }
diff --git a/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.h b/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.h
index 5def811a87f..3f4a751c672 100644
--- a/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.h
+++ b/examples/zigbee/light_sample/HA_on_off_light/main/esp_zb_light.h
@@ -1,7 +1,7 @@
 /*
  * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: CC0-1.0
+ * SPDX-License-Identifier:  LicenseRef-Included
  *
  * Zigbee HA_on_off_light Example
  *
@@ -14,13 +14,18 @@
 
 #include "esp_zigbee_core.h"
 #include "light_driver.h"
+#include "zcl_utility.h"
 
 /* Zigbee configuration */
-#define INSTALLCODE_POLICY_ENABLE       false   /* enable the install code policy for security */
-#define ED_AGING_TIMEOUT                ESP_ZB_ED_AGING_TIMEOUT_64MIN
-#define ED_KEEP_ALIVE                   3000    /* 3000 millisecond */
-#define HA_ESP_LIGHT_ENDPOINT           10      /* esp light bulb device endpoint, used to process light controlling commands */
-#define ESP_ZB_PRIMARY_CHANNEL_MASK     ESP_ZB_TRANSCEIVER_ALL_CHANNELS_MASK  /* Zigbee primary channel mask use in the example */
+#define INSTALLCODE_POLICY_ENABLE       false                                /* enable the install code policy for security */
+#define ED_AGING_TIMEOUT                ESP_ZB_ED_AGING_TIMEOUT_64MIN        /* aging timeout of device */
+#define ED_KEEP_ALIVE                   3000                                 /* 3000 millisecond */
+#define HA_ESP_LIGHT_ENDPOINT           10                                   /* esp light bulb device endpoint, used to process light controlling commands */
+#define ESP_ZB_PRIMARY_CHANNEL_MASK     ESP_ZB_TRANSCEIVER_ALL_CHANNELS_MASK /* Zigbee primary channel mask use in the example */
+
+/* Basic manufacturer information */
+#define ESP_MANUFACTURER_NAME "\x09""ESPRESSIF"      /* Customized manufacturer name */
+#define ESP_MODEL_IDENTIFIER "\x07"CONFIG_IDF_TARGET /* Customized model identifier */
 
 #define ESP_ZB_ZED_CONFIG()                                         \
     {                                                               \
@@ -34,10 +39,10 @@
 
 #define ESP_ZB_DEFAULT_RADIO_CONFIG()                           \
     {                                                           \
-        .radio_mode = RADIO_MODE_NATIVE,                        \
+        .radio_mode = ZB_RADIO_MODE_NATIVE,                     \
     }
 
 #define ESP_ZB_DEFAULT_HOST_CONFIG()                            \
     {                                                           \
-        .host_connection_mode = HOST_CONNECTION_MODE_NONE,      \
+        .host_connection_mode = ZB_HOST_CONNECTION_MODE_NONE,   \
     }
diff --git a/examples/zigbee/light_sample/HA_on_off_light/main/idf_component.yml b/examples/zigbee/light_sample/HA_on_off_light/main/idf_component.yml
index 8578e73e678..198da019c3d 100644
--- a/examples/zigbee/light_sample/HA_on_off_light/main/idf_component.yml
+++ b/examples/zigbee/light_sample/HA_on_off_light/main/idf_component.yml
@@ -1,7 +1,7 @@
 ## IDF Component Manager Manifest File
 dependencies:
-  espressif/esp-zboss-lib: "1.0.9"
-  espressif/esp-zigbee-lib: "1.0.9"
+  espressif/esp-zboss-lib: "~1.6.0"
+  espressif/esp-zigbee-lib: "~1.6.0"
   espressif/led_strip: "~2.0.0"
   ## Required IDF version
   idf:
diff --git a/examples/zigbee/light_sample/HA_on_off_switch/README.md b/examples/zigbee/light_sample/HA_on_off_switch/README.md
index b02dc682ece..61f4128bf1a 100644
--- a/examples/zigbee/light_sample/HA_on_off_switch/README.md
+++ b/examples/zigbee/light_sample/HA_on_off_switch/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C6 | ESP32-H2 |
-| ----------------- | -------- | -------- |
+| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- | -------- |
 
 # Light Switch Example
 
@@ -34,31 +34,34 @@ Build the project, flash it to the board, and start the monitor tool to view the
 As you run the example, you will see the following log:
 
 ```
-I (388) main_task: Calling app_main()
-I (398) gpio: GPIO[9]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:2
-I (398) phy_init: phy_version 220,2dbbbe7,Sep 25 2023,20:39:25
-I (478) phy: libbtbb version: 90c587c, Sep 25 2023, 20:39:57
-I (488) ESP_ZB_ON_OFF_SWITCH: ZDO signal: ZDO Config Ready (0x17), status: ESP_FAIL
-I (488) ESP_ZB_ON_OFF_SWITCH: Zigbee stack initialized
-I (488) ESP_ZB_ON_OFF_SWITCH: Start network formation
-I (498) main_task: Returned from app_main()
-I (998) ESP_ZB_ON_OFF_SWITCH: ZDO signal: NWK Permit Join (0x36), status: ESP_OK
-I (998) ESP_ZB_ON_OFF_SWITCH: Formed network successfully (Extended PAN ID: 60:55:f9:00:00:f6:07:b4, PAN ID: 0x2a74, Channel:13)
-I (1468) ESP_ZB_ON_OFF_SWITCH: ZDO signal: NWK Permit Join (0x36), status: ESP_OK
-I (1468) ESP_ZB_ON_OFF_SWITCH: Network steering started
-I (14228) ESP_ZB_ON_OFF_SWITCH: ZDO signal: NWK Device Associated (0x12), status: ESP_OK
-I (14728) ESP_ZB_ON_OFF_SWITCH: ZDO signal: ZDO Device Update (0x30), status: ESP_OK
-I (14788) ESP_ZB_ON_OFF_SWITCH: New device commissioned or rejoined (short: 0xe399)
-I (14858) ESP_ZB_ON_OFF_SWITCH: Found light
-I (14858) ESP_ZB_ON_OFF_SWITCH: Try to bind On/Off
-I (14858) ESP_ZB_ON_OFF_SWITCH: Bound successfully!
-I (14858) ESP_ZB_ON_OFF_SWITCH: The light originating from address(0xe399) on endpoint(10)
-I (15338) ESP_ZB_ON_OFF_SWITCH: ZDO signal: ZDO Device Authorized (0x2f), status: ESP_OK
-I (15408) ESP_ZB_ON_OFF_SWITCH: ZDO signal: NWK Permit Join (0x36), status: ESP_OK
-I (35838) ESP_ZB_ON_OFF_SWITCH: ZDO signal: NLME Status Indication (0x32), status: ESP_OK
-I (38548) ESP_ZB_ON_OFF_SWITCH: Send 'on_off toggle' command
-I (39598) ESP_ZB_ON_OFF_SWITCH: Send 'on_off toggle' command
-I (41148) ESP_ZB_ON_OFF_SWITCH: Send 'on_off toggle' command
+I (441) main_task: Started on CPU0                                                                                                                                                                                                                                                        
+I (441) main_task: Calling app_main()                                                                                                        
+I (461) phy: phy_version: 230,2, 9aae6ea, Jan 15 2024, 11:17:12       
+I (461) phy: libbtbb version: 944f18e, Jan 15 2024, 11:17:25                                                                                 
+I (471) main_task: Returned from app_main()                                                                                                  
+I (601) ESP_ZB_ON_OFF_SWITCH: ZDO signal: ZDO Config Ready (0x17), status: ESP_FAIL                                                          
+I (601) ESP_ZB_ON_OFF_SWITCH: Initialize Zigbee stack                                                                                        
+I (611) gpio: GPIO[9]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:2                                                 
+I (611) ESP_ZB_ON_OFF_SWITCH: Deferred driver initialization successful                                                                      
+I (621) ESP_ZB_ON_OFF_SWITCH: Device started up in  factory-reset mode                                                                       
+I (621) ESP_ZB_ON_OFF_SWITCH: Start network formation                                                                                        
+W (781) ESP_ZB_ON_OFF_SWITCH: Network(0x13af) closed, devices joining not allowed.                                                           
+I (781) ESP_ZB_ON_OFF_SWITCH: Formed network successfully (Extended PAN ID: 74:4d:bd:ff:fe:63:f7:30, PAN ID: 0x13af, Channel:13, Short Address: 0x0000)
+I (1391) ESP_ZB_ON_OFF_SWITCH: Network(0x13af) is open for 180 seconds                                                                       
+I (1391) ESP_ZB_ON_OFF_SWITCH: Network steering started                                                                                      
+I (9561) ESP_ZB_ON_OFF_SWITCH: ZDO signal: NWK Device Associated (0x12), status: ESP_OK                                                      
+I (9561) ESP_ZB_ON_OFF_SWITCH: ZDO signal: ZDO Device Update (0x30), status: ESP_OK                                                          
+I (9601) ESP_ZB_ON_OFF_SWITCH: New device commissioned or rejoined (short: 0x7c16)                                                           
+I (9671) ESP_ZB_ON_OFF_SWITCH: Found light                            
+I (9671) ESP_ZB_ON_OFF_SWITCH: Try to bind On/Off                                                                                            
+I (9681) ESP_ZB_ON_OFF_SWITCH: Bound successfully!                                                                                           
+I (9681) ESP_ZB_ON_OFF_SWITCH: The light originating from address(0x7c16) on endpoint(10)                                                    
+I (9751) ESP_ZB_ON_OFF_SWITCH: ZDO signal: ZDO Device Authorized (0x2f), status: ESP_OK                                                      
+I (9781) ESP_ZB_ON_OFF_SWITCH: Network(0x13af) is open for 180 seconds                                                                       
+I (16451) ESP_ZB_ON_OFF_SWITCH: Send 'on_off toggle' command                                                                                 
+I (17011) ESP_ZB_ON_OFF_SWITCH: Send 'on_off toggle' command                                                                                 
+I (17441) ESP_ZB_ON_OFF_SWITCH: Send 'on_off toggle' command                                                                                 
+I (17831) ESP_ZB_ON_OFF_SWITCH: Send 'on_off toggle' command
 ```
 
 ## Light Control Functions
diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/CMakeLists.txt b/examples/zigbee/light_sample/HA_on_off_switch/main/CMakeLists.txt
index b996c0f78a5..15343efb83c 100644
--- a/examples/zigbee/light_sample/HA_on_off_switch/main/CMakeLists.txt
+++ b/examples/zigbee/light_sample/HA_on_off_switch/main/CMakeLists.txt
@@ -1,6 +1,4 @@
 idf_component_register(
-    SRCS
-    "esp_zb_switch.c"
-    "switch_driver.c"
-    INCLUDE_DIRS "."
+    SRC_DIRS  "." "../../../common/zcl_utility/src"
+    INCLUDE_DIRS "." "../../../common/zcl_utility/include"
 )
diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.c b/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.c
index 2750377202b..64459f04b31 100644
--- a/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.c
+++ b/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.c
@@ -1,7 +1,7 @@
 /*
  * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: CC0-1.0
+ * SPDX-License-Identifier:  LicenseRef-Included
  *
  * Zigbee HA_on_off_switch Example
  *
@@ -15,6 +15,8 @@
 #include "string.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
+#include "esp_err.h"
+#include "esp_check.h"
 #include "esp_log.h"
 #include "nvs_flash.h"
 #include "ha/esp_zigbee_ha_standard.h"
@@ -35,7 +37,7 @@ static switch_func_pair_t button_func_pair[] = {
 
 static const char *TAG = "ESP_ZB_ON_OFF_SWITCH";
 
-static void esp_zb_buttons_handler(switch_func_pair_t *button_func_pair)
+static void zb_buttons_handler(switch_func_pair_t *button_func_pair)
 {
     if (button_func_pair->func == SWITCH_ONOFF_TOGGLE_CONTROL) {
         /* implemented light switch toggle functionality */
@@ -43,14 +45,23 @@ static void esp_zb_buttons_handler(switch_func_pair_t *button_func_pair)
         cmd_req.zcl_basic_cmd.src_endpoint = HA_ONOFF_SWITCH_ENDPOINT;
         cmd_req.address_mode = ESP_ZB_APS_ADDR_MODE_DST_ADDR_ENDP_NOT_PRESENT;
         cmd_req.on_off_cmd_id = ESP_ZB_ZCL_CMD_ON_OFF_TOGGLE_ID;
-        ESP_EARLY_LOGI(TAG, "Send 'on_off toggle' command");
+        esp_zb_lock_acquire(portMAX_DELAY);
         esp_zb_zcl_on_off_cmd_req(&cmd_req);
+        esp_zb_lock_release();
+        ESP_EARLY_LOGI(TAG, "Send 'on_off toggle' command");
     }
 }
 
+static esp_err_t deferred_driver_init(void)
+{
+    ESP_RETURN_ON_FALSE(switch_driver_init(button_func_pair, PAIR_SIZE(button_func_pair), zb_buttons_handler), ESP_FAIL, TAG,
+                        "Failed to initialize switch driver");
+    return ESP_OK;
+}
+
 static void bdb_start_top_level_commissioning_cb(uint8_t mode_mask)
 {
-    ESP_ERROR_CHECK(esp_zb_bdb_start_top_level_commissioning(mode_mask));
+    ESP_RETURN_ON_FALSE(esp_zb_bdb_start_top_level_commissioning(mode_mask) == ESP_OK, , TAG, "Failed to start Zigbee bdb commissioning");
 }
 
 static void bind_cb(esp_zb_zdp_status_t zdo_status, void *user_ctx)
@@ -94,17 +105,19 @@ void esp_zb_app_signal_handler(esp_zb_app_signal_t *signal_struct)
     esp_zb_zdo_signal_device_annce_params_t *dev_annce_params = NULL;
     switch (sig_type) {
     case ESP_ZB_ZDO_SIGNAL_SKIP_STARTUP:
-        ESP_LOGI(TAG, "Zigbee stack initialized");
+        ESP_LOGI(TAG, "Initialize Zigbee stack");
         esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_INITIALIZATION);
         break;
     case ESP_ZB_BDB_SIGNAL_DEVICE_FIRST_START:
     case ESP_ZB_BDB_SIGNAL_DEVICE_REBOOT:
         if (err_status == ESP_OK) {
+            ESP_LOGI(TAG, "Deferred driver initialization %s", deferred_driver_init() ? "failed" : "successful");
             ESP_LOGI(TAG, "Device started up in %s factory-reset mode", esp_zb_bdb_is_factory_new() ? "" : "non");
             if (esp_zb_bdb_is_factory_new()) {
                 ESP_LOGI(TAG, "Start network formation");
                 esp_zb_bdb_start_top_level_commissioning(ESP_ZB_BDB_MODE_NETWORK_FORMATION);
             } else {
+                esp_zb_bdb_open_network(180);
                 ESP_LOGI(TAG, "Device rebooted");
             }
         } else {
@@ -161,10 +174,16 @@ static void esp_zb_task(void *pvParameters)
     esp_zb_init(&zb_nwk_cfg);
     esp_zb_on_off_switch_cfg_t switch_cfg = ESP_ZB_DEFAULT_ON_OFF_SWITCH_CONFIG();
     esp_zb_ep_list_t *esp_zb_on_off_switch_ep = esp_zb_on_off_switch_ep_create(HA_ONOFF_SWITCH_ENDPOINT, &switch_cfg);
+    zcl_basic_manufacturer_info_t info = {
+        .manufacturer_name = ESP_MANUFACTURER_NAME,
+        .model_identifier = ESP_MODEL_IDENTIFIER,
+    };
+
+    esp_zcl_utility_add_ep_basic_manufacturer_info(esp_zb_on_off_switch_ep, HA_ONOFF_SWITCH_ENDPOINT, &info);
     esp_zb_device_register(esp_zb_on_off_switch_ep);
     esp_zb_set_primary_network_channel_set(ESP_ZB_PRIMARY_CHANNEL_MASK);
     ESP_ERROR_CHECK(esp_zb_start(false));
-    esp_zb_main_loop_iteration();
+    esp_zb_stack_main_loop();
 }
 
 void app_main(void)
@@ -175,6 +194,6 @@ void app_main(void)
     };
     ESP_ERROR_CHECK(nvs_flash_init());
     ESP_ERROR_CHECK(esp_zb_platform_config(&config));
-    switch_driver_init(button_func_pair, PAIR_SIZE(button_func_pair), esp_zb_buttons_handler);
+
     xTaskCreate(esp_zb_task, "Zigbee_main", 4096, NULL, 5, NULL);
 }
diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.h b/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.h
index d4d95a0a0e4..32a6dc9edf0 100644
--- a/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.h
+++ b/examples/zigbee/light_sample/HA_on_off_switch/main/esp_zb_switch.h
@@ -1,7 +1,7 @@
 /*
  * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: CC0-1.0
+ * SPDX-License-Identifier:  LicenseRef-Included
  *
  * Zigbee HA_on_off_switch Example
  *
@@ -13,12 +13,17 @@
  */
 #include "esp_zigbee_core.h"
 #include "switch_driver.h"
+#include "zcl_utility.h"
 
 /* Zigbee configuration */
-#define MAX_CHILDREN                    10          /* the max amount of connected devices */
-#define INSTALLCODE_POLICY_ENABLE       false       /* enable the install code policy for security */
-#define HA_ONOFF_SWITCH_ENDPOINT        1           /* esp light switch device endpoint */
-#define ESP_ZB_PRIMARY_CHANNEL_MASK     (1l << 13)  /* Zigbee primary channel mask use in the example */
+#define MAX_CHILDREN                    10         /* the max amount of connected devices */
+#define INSTALLCODE_POLICY_ENABLE       false      /* enable the install code policy for security */
+#define HA_ONOFF_SWITCH_ENDPOINT        1          /* esp light switch device endpoint */
+#define ESP_ZB_PRIMARY_CHANNEL_MASK     (1l << 13) /* Zigbee primary channel mask use in the example */
+
+/* Basic manufacturer information */
+#define ESP_MANUFACTURER_NAME "\x09""ESPRESSIF"      /* Customized manufacturer name */
+#define ESP_MODEL_IDENTIFIER "\x07"CONFIG_IDF_TARGET /* Customized model identifier */
 
 #define ESP_ZB_ZC_CONFIG()                                                              \
     {                                                                                   \
@@ -31,10 +36,10 @@
 
 #define ESP_ZB_DEFAULT_RADIO_CONFIG()                           \
     {                                                           \
-        .radio_mode = RADIO_MODE_NATIVE,                        \
+        .radio_mode = ZB_RADIO_MODE_NATIVE,                     \
     }
 
 #define ESP_ZB_DEFAULT_HOST_CONFIG()                            \
     {                                                           \
-        .host_connection_mode = HOST_CONNECTION_MODE_NONE,      \
+        .host_connection_mode = ZB_HOST_CONNECTION_MODE_NONE,   \
     }
diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/idf_component.yml b/examples/zigbee/light_sample/HA_on_off_switch/main/idf_component.yml
index c186c3c8cad..ad32c63b48e 100644
--- a/examples/zigbee/light_sample/HA_on_off_switch/main/idf_component.yml
+++ b/examples/zigbee/light_sample/HA_on_off_switch/main/idf_component.yml
@@ -1,7 +1,7 @@
 ## IDF Component Manager Manifest File
 dependencies:
-  espressif/esp-zboss-lib: "1.0.9"
-  espressif/esp-zigbee-lib: "1.0.9"
+  espressif/esp-zboss-lib: "~1.6.0"
+  espressif/esp-zigbee-lib: "~1.6.0"
   ## Required IDF version
   idf:
     version: ">=5.0.0"
diff --git a/examples/zigbee/light_sample/HA_on_off_switch/main/switch_driver.c b/examples/zigbee/light_sample/HA_on_off_switch/main/switch_driver.c
index 2acf388944e..8c03708cc85 100644
--- a/examples/zigbee/light_sample/HA_on_off_switch/main/switch_driver.c
+++ b/examples/zigbee/light_sample/HA_on_off_switch/main/switch_driver.c
@@ -67,7 +67,7 @@ static void IRAM_ATTR gpio_isr_handler(void *arg)
 }
 
 /**
- * @brief Enable GPIO (switchs refer to) isr
+ * @brief Enable GPIO (switches refer to) isr
  *
  * @param enabled      enable isr if true.
  */
@@ -159,7 +159,7 @@ static bool switch_driver_gpio_init(switch_func_pair_t *button_func_pair, uint8_
         return false;
     }
     /* start gpio task */
-    xTaskCreate(switch_driver_button_detected, "button_detected", 2048, NULL, 10, NULL);
+    xTaskCreate(switch_driver_button_detected, "button_detected", 4096, NULL, 10, NULL);
     /* install gpio isr service */
     gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT);
     for (int i = 0; i < button_num; ++i) {
diff --git a/tools/activate.py b/tools/activate.py
index 8c0c021a5da..d1f88e34adf 100755
--- a/tools/activate.py
+++ b/tools/activate.py
@@ -14,7 +14,7 @@
 
 
 def die(msg: str) -> None:
-    sys.exit(f'error: {msg}')
+    sys.exit(f'\nERROR: {msg}')
 
 
 idf_tools_path = os.path.realpath(os.path.dirname(__file__))
@@ -37,7 +37,11 @@ def die(msg: str) -> None:
 os.environ['IDF_PYTHON_ENV_PATH'] = idf_python_env_path
 os.environ['ESP_IDF_VERSION'] = idf_version
 
+if not os.path.exists(virtualenv_python):
+    die(f'ESP-IDF Python virtual environment not found. Please run the install script to set it up before proceeding.')
+
 try:
     run([virtualenv_python, os.path.join(idf_path, 'tools', 'export_utils', 'activate_venv.py')] + sys.argv[1:], check=True)
 except (OSError, SubprocessError):
-    die(f'Activation script failed')
+    die('\n'.join(['Activation script failed',
+                   'To view detailed debug information, set ESP_IDF_EXPORT_DEBUG=1 and run the export script again.']))
diff --git a/tools/ci/artifacts_handler.py b/tools/ci/artifacts_handler.py
index 6147f61bdd7..06752b02830 100644
--- a/tools/ci/artifacts_handler.py
+++ b/tools/ci/artifacts_handler.py
@@ -152,11 +152,8 @@ def _upload_files(
     try:
         if has_file:
             obj_name = f'{pipeline_id}/{artifact_type.value}/{sanitize_job_name(job_name)}/{job_id}.zip'
-            print(f'Created archive file: {job_id}.zip, uploading as {obj_name}')
-
             client.fput_object(getenv('IDF_S3_BUCKET'), obj_name, f'{job_id}.zip')
-            url = client.get_presigned_url('GET', getenv('IDF_S3_BUCKET'), obj_name)
-            print(f'Please download the archive file which includes {artifact_type.value} from {url}')
+            print(f'Created archive file: {job_id}.zip, uploaded as {obj_name}')
     finally:
         os.remove(f'{job_id}.zip')
 
diff --git a/tools/ci/astyle-rules.yml b/tools/ci/astyle-rules.yml
index e74f913eb54..12da05ef74e 100644
--- a/tools/ci/astyle-rules.yml
+++ b/tools/ci/astyle-rules.yml
@@ -161,6 +161,10 @@ components_not_formatted_permanent:
     - "/examples/peripherals/dac/dac_continuous/dac_audio/main/audio_example_file.h"
     # Coredump (generated)
     - /components/espcoredump/include_core_dump/elf.h
+    # OpenOCD stub binaries (generated)
+    - /components/esp_system/openocd_stub_bins/*.inc
+    - /components/esp_system/openocd_stub_bins/esp32c6/*.inc
+    - /components/esp_system/openocd_stub_bins/esp32h2/*.inc
 
 docs:
   # Docs directory contains some .inc files, which are not C include files
diff --git a/tools/ci/build_template_app.sh b/tools/ci/build_template_app.sh
index c77c85026a1..59457ad0cb7 100755
--- a/tools/ci/build_template_app.sh
+++ b/tools/ci/build_template_app.sh
@@ -54,7 +54,7 @@ build_stage2() {
     # Override EXTRA_CFLAGS and EXTRA_CXXFLAGS in the environment
     export EXTRA_CFLAGS=${PEDANTIC_CFLAGS/-Werror=unused-variable -Werror=unused-but-set-variable -Werror=unused-function/}
     export EXTRA_CXXFLAGS=${PEDANTIC_CXXFLAGS/-Werror=unused-variable -Werror=unused-but-set-variable -Werror=unused-function/}
-    python -m idf_build_apps build -vv \
+    python -m idf_build_apps build -v \
         -p ${TEMPLATE_APP_PATH} \
         -t all \
         ${CONFIG_STR} \
@@ -69,7 +69,7 @@ build_stage2() {
 
 build_stage1() {
     CONFIG_STR=$(get_config_str sdkconfig.ci2.*=)
-    python -m idf_build_apps build -vv \
+    python -m idf_build_apps build -v \
         -p ${TEMPLATE_APP_PATH} \
         -t all \
         ${CONFIG_STR} \
diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt
index f605b7cd054..712e7b5791f 100644
--- a/tools/ci/check_copyright_ignore.txt
+++ b/tools/ci/check_copyright_ignore.txt
@@ -503,8 +503,8 @@ components/protocomm/include/transports/protocomm_console.h
 components/protocomm/include/transports/protocomm_httpd.h
 components/riscv/include/riscv/csr.h
 components/riscv/include/riscv/encoding.h
+components/sdmmc/include/esp_private/sdmmc_common.h
 components/sdmmc/sdmmc_common.c
-components/sdmmc/sdmmc_common.h
 components/sdmmc/sdmmc_init.c
 components/sdmmc/sdmmc_io.c
 components/sdmmc/sdmmc_mmc.c
@@ -524,33 +524,6 @@ components/soc/esp32/include/soc/touch_sensor_channel.h
 components/soc/esp32/include/soc/uart_pins.h
 components/soc/esp32/include/soc/wdev_reg.h
 components/soc/esp32/ledc_periph.c
-components/soc/esp32c3/include/soc/apb_saradc_reg.h
-components/soc/esp32c3/include/soc/assist_debug_reg.h
-components/soc/esp32c3/include/soc/bb_reg.h
-components/soc/esp32c3/include/soc/boot_mode.h
-components/soc/esp32c3/include/soc/extmem_reg.h
-components/soc/esp32c3/include/soc/fe_reg.h
-components/soc/esp32c3/include/soc/gpio_reg.h
-components/soc/esp32c3/include/soc/gpio_struct.h
-components/soc/esp32c3/include/soc/i2c_reg.h
-components/soc/esp32c3/include/soc/interrupt_core0_reg.h
-components/soc/esp32c3/include/soc/ledc_reg.h
-components/soc/esp32c3/include/soc/nrx_reg.h
-components/soc/esp32c3/include/soc/reset_reasons.h
-components/soc/esp32c3/include/soc/rtc_i2c_reg.h
-components/soc/esp32c3/include/soc/sensitive_reg.h
-components/soc/esp32c3/include/soc/sensitive_struct.h
-components/soc/esp32c3/include/soc/soc_pins.h
-components/soc/esp32c3/include/soc/spi_mem_reg.h
-components/soc/esp32c3/include/soc/systimer_reg.h
-components/soc/esp32c3/include/soc/systimer_struct.h
-components/soc/esp32c3/include/soc/uart_pins.h
-components/soc/esp32c3/include/soc/uart_reg.h
-components/soc/esp32c3/include/soc/uhci_reg.h
-components/soc/esp32c3/include/soc/usb_serial_jtag_reg.h
-components/soc/esp32c3/include/soc/usb_serial_jtag_struct.h
-components/soc/esp32c3/include/soc/wdev_reg.h
-components/soc/esp32c3/interrupts.c
 components/soc/esp32c3/ledc_periph.c
 components/soc/esp32s2/adc_periph.c
 components/soc/esp32s2/include/soc/bb_reg.h
@@ -565,63 +538,9 @@ components/soc/esp32s2/include/soc/touch_sensor_pins.h
 components/soc/esp32s2/include/soc/uart_pins.h
 components/soc/esp32s2/include/soc/wdev_reg.h
 components/soc/esp32s2/ledc_periph.c
-components/soc/esp32s3/include/soc/apb_saradc_reg.h
-components/soc/esp32s3/include/soc/assist_debug_reg.h
-components/soc/esp32s3/include/soc/assist_debug_struct.h
-components/soc/esp32s3/include/soc/bb_reg.h
-components/soc/esp32s3/include/soc/boot_mode.h
-components/soc/esp32s3/include/soc/extmem_reg.h
-components/soc/esp32s3/include/soc/extmem_struct.h
-components/soc/esp32s3/include/soc/fe_reg.h
-components/soc/esp32s3/include/soc/gpio_reg.h
-components/soc/esp32s3/include/soc/hinf_reg.h
-components/soc/esp32s3/include/soc/hinf_struct.h
-components/soc/esp32s3/include/soc/host_reg.h
-components/soc/esp32s3/include/soc/host_struct.h
-components/soc/esp32s3/include/soc/i2c_reg.h
-components/soc/esp32s3/include/soc/i2c_struct.h
-components/soc/esp32s3/include/soc/interrupt_core0_reg.h
-components/soc/esp32s3/include/soc/interrupt_core0_struct.h
-components/soc/esp32s3/include/soc/interrupt_core1_reg.h
-components/soc/esp32s3/include/soc/interrupt_core1_struct.h
-components/soc/esp32s3/include/soc/interrupt_struct.h
-components/soc/esp32s3/include/soc/ledc_reg.h
-components/soc/esp32s3/include/soc/ledc_struct.h
 components/soc/esp32s3/include/soc/mpu_caps.h
-components/soc/esp32s3/include/soc/nrx_reg.h
-components/soc/esp32s3/include/soc/peri_backup_reg.h
-components/soc/esp32s3/include/soc/peri_backup_struct.h
-components/soc/esp32s3/include/soc/reset_reasons.h
-components/soc/esp32s3/include/soc/rtc_i2c_reg.h
-components/soc/esp32s3/include/soc/rtc_i2c_struct.h
-components/soc/esp32s3/include/soc/rtc_io_reg.h
-components/soc/esp32s3/include/soc/rtc_io_struct.h
-components/soc/esp32s3/include/soc/sdmmc_pins.h
-components/soc/esp32s3/include/soc/sdmmc_reg.h
-components/soc/esp32s3/include/soc/sensitive_reg.h
-components/soc/esp32s3/include/soc/sensitive_struct.h
-components/soc/esp32s3/include/soc/soc_ulp.h
-components/soc/esp32s3/include/soc/spi_mem_reg.h
-components/soc/esp32s3/include/soc/spi_mem_struct.h
-components/soc/esp32s3/include/soc/spi_reg.h
-components/soc/esp32s3/include/soc/spi_struct.h
-components/soc/esp32s3/include/soc/syscon_struct.h
-components/soc/esp32s3/include/soc/system_reg.h
-components/soc/esp32s3/include/soc/system_struct.h
-components/soc/esp32s3/include/soc/systimer_reg.h
-components/soc/esp32s3/include/soc/systimer_struct.h
-components/soc/esp32s3/include/soc/touch_channel.h
-components/soc/esp32s3/include/soc/uart_pins.h
-components/soc/esp32s3/include/soc/uart_reg.h
-components/soc/esp32s3/include/soc/uart_struct.h
-components/soc/esp32s3/include/soc/uhci_reg.h
-components/soc/esp32s3/include/soc/usb_serial_jtag_struct.h
-components/soc/esp32s3/include/soc/usb_wrap_reg.h
-components/soc/esp32s3/include/soc/usb_wrap_struct.h
-components/soc/esp32s3/include/soc/wdev_reg.h
 components/soc/esp32s3/ledc_periph.c
 components/soc/include/soc/gpio_periph.h
-components/soc/include/soc/ledc_periph.h
 components/soc/lldesc.c
 components/spi_flash/include/spi_flash_chip_boya.h
 components/spi_flash/include/spi_flash_chip_gd.h
@@ -955,9 +874,6 @@ examples/mesh/manual_networking/main/mesh_main.c
 examples/network/simple_sniffer/main/cmd_sniffer.c
 examples/network/simple_sniffer/main/cmd_sniffer.h
 examples/network/simple_sniffer/main/simple_sniffer_example_main.c
-examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c
-examples/peripherals/gpio/matrix_keyboard/components/matrix_keyboard/include/matrix_keyboard.h
-examples/peripherals/gpio/matrix_keyboard/main/matrix_keyboard_example_main.c
 examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c
 examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c
 examples/peripherals/sdio/host/main/app_main.c
@@ -1023,7 +939,6 @@ examples/security/flash_encryption/main/flash_encrypt_main.c
 examples/storage/custom_flash_driver/components/custom_chip_driver/chip_drivers.c
 examples/storage/custom_flash_driver/components/custom_chip_driver/spi_flash_chip_eon.c
 examples/storage/custom_flash_driver/main/main.c
-examples/storage/ext_flash_fatfs/main/ext_flash_fatfs_example_main.c
 examples/storage/nvs_rw_blob/main/nvs_blob_example_main.c
 examples/storage/nvs_rw_value/main/nvs_value_example_main.c
 examples/storage/nvs_rw_value_cxx/main/nvs_value_example_main.cpp
diff --git a/tools/ci/check_examples_extra_component_dirs.sh b/tools/ci/check_examples_extra_component_dirs.sh
index 207efff7f4d..dd2e311342e 100755
--- a/tools/ci/check_examples_extra_component_dirs.sh
+++ b/tools/ci/check_examples_extra_component_dirs.sh
@@ -5,7 +5,8 @@ set -uo pipefail
 # Examples shouldn't use EXTRA_COMPONENT_DIRS, instead the dependencies should be specified in idf_component.yml files
 
 output=$(find ${IDF_PATH}/examples -name "CMakeLists.txt" -not -path "**/managed_components/**" -not -path "**/build/**")
-files=$(egrep "set\(EXTRA_COMPONENT_DIRS" ${output} | cut -d ":" -f 1)
+# Make sure the regex doesn't match the text `BOOTLOADER_EXTRA_COMPONENT_DIRS`
+files=$(egrep "[^A-Za-Z0-9_]EXTRA_COMPONENT_DIRS" ${output} | cut -d ":" -f 1)
 found_issues=0
 for file in ${files}
 do
diff --git a/tools/ci/dynamic_pipelines/report.py b/tools/ci/dynamic_pipelines/report.py
index bbfb6b6df0d..ca41156462e 100644
--- a/tools/ci/dynamic_pipelines/report.py
+++ b/tools/ci/dynamic_pipelines/report.py
@@ -11,6 +11,7 @@
 
 import yaml
 from artifacts_handler import ArtifactType
+from gitlab import GitlabUpdateError
 from gitlab_api import Gitlab
 from idf_build_apps import App
 from idf_build_apps.constants import BuildStatus
@@ -254,6 +255,10 @@ def _update_mr_comment(self, comment: str, print_retry_jobs_message: bool) -> No
         )
         del_retry_job_pic_pattern = re.escape(RETRY_JOB_TITLE) + r'.*?' + re.escape(f'{RETRY_JOB_PICTURE_PATH})')
 
+        new_comment = f'{COMMENT_START_MARKER}\n\n{comment}'
+        if print_retry_jobs_message:
+            new_comment += retry_job_picture_comment
+
         for note in self.mr.notes.list(iterator=True):
             if note.body.startswith(COMMENT_START_MARKER):
                 updated_str = self._get_updated_comment(note.body, comment)
@@ -264,14 +269,13 @@ def _update_mr_comment(self, comment: str, print_retry_jobs_message: bool) -> No
                     updated_str += retry_job_picture_comment
 
                 note.body = updated_str
-                note.save()
+                try:
+                    note.save()
+                except GitlabUpdateError:
+                    print('Failed to update MR comment, Creating a new comment')
+                    self.mr.notes.create({'body': new_comment})
                 break
         else:
-            # Create a new comment if no existing comment is found
-            new_comment = f'{COMMENT_START_MARKER}\n\n{comment}'
-            if print_retry_jobs_message:
-                new_comment += retry_job_picture_comment
-
             self.mr.notes.create({'body': new_comment})
 
     def _get_updated_comment(self, existing_comment: str, new_comment: str) -> str:
diff --git a/tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py b/tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py
index bea461414b4..019bc789a61 100644
--- a/tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py
+++ b/tools/ci/dynamic_pipelines/scripts/generate_target_test_child_pipeline.py
@@ -8,7 +8,6 @@
 """
 import argparse
 import glob
-import logging
 import os
 import typing as t
 from collections import Counter
@@ -21,16 +20,15 @@
 from dynamic_pipelines.constants import DEFAULT_TARGET_TEST_CHILD_PIPELINE_FILEPATH
 from dynamic_pipelines.constants import DEFAULT_TARGET_TEST_CHILD_PIPELINE_NAME
 from dynamic_pipelines.constants import DEFAULT_TEST_PATHS
-from dynamic_pipelines.constants import KNOWN_GENERATE_TEST_CHILD_PIPELINE_WARNINGS_FILEPATH
+from dynamic_pipelines.constants import (
+    KNOWN_GENERATE_TEST_CHILD_PIPELINE_WARNINGS_FILEPATH,
+)
 from dynamic_pipelines.models import EmptyJob
 from dynamic_pipelines.models import Job
 from dynamic_pipelines.models import TargetTestJob
 from dynamic_pipelines.utils import dump_jobs_to_yaml
-from gitlab.v4.objects import Project
-from gitlab_api import Gitlab
 from idf_build_apps import App
 from idf_ci.app import import_apps_from_txt
-from idf_ci_utils import IDF_PATH
 from idf_pytest.script import get_pytest_cases
 
 
@@ -50,22 +48,17 @@ def get_tags_with_amount(s: str) -> t.List[str]:
 
 
 def get_target_test_jobs(
-    project: Project, paths: str, apps: t.List[App]
-) -> t.Tuple[t.List[Job], t.List[str], t.Dict[str, t.List[str]]]:
+    paths: str, apps: t.List[App], exclude_runner_tags: t.Set[str]
+) -> t.Tuple[t.List[Job], t.List[str], t.List[str]]:
     """
     Return the target test jobs and the extra yaml files to include
     """
-    issues: t.Dict[str, t.List[str]] = {
-        'no_env_marker_test_cases': [],
-        'no_runner_tags': [],
-    }
-
     if mr_labels := os.getenv('CI_MERGE_REQUEST_LABELS'):
         print(f'MR labels: {mr_labels}')
 
         if BUILD_ONLY_LABEL in mr_labels.split(','):
             print('MR has build only label, skip generating target test child pipeline')
-            return [EmptyJob()], [], issues
+            return [EmptyJob()], [], []
 
     pytest_cases = get_pytest_cases(
         paths,
@@ -73,10 +66,11 @@ def get_target_test_jobs(
         marker_expr='not host_test',  # since it's generating target-test child pipeline
     )
 
+    no_env_marker_test_cases: t.List[str] = []
     res = defaultdict(list)
     for case in pytest_cases:
         if not case.env_markers:
-            issues['no_env_marker_test_cases'].append(case.item.nodeid)
+            no_env_marker_test_cases.append(case.item.nodeid)
             continue
 
         res[(case.target_selector, tuple(sorted(case.env_markers)))].append(case)
@@ -84,13 +78,8 @@ def get_target_test_jobs(
     target_test_jobs: t.List[Job] = []
     for (target_selector, env_markers), cases in res.items():
         runner_tags = get_tags_with_amount(target_selector) + list(env_markers)
-        # we don't need to get all runner, as long as we get one runner, it's fine
-        runner_list = project.runners.list(status='online', tag_list=','.join(runner_tags), get_all=False)
-        if not runner_list:
-            issues['no_runner_tags'].append(','.join(runner_tags))
-            logging.warning(f'No runner found for {",".join(runner_tags)}, required by cases:')
-            for case in cases:
-                logging.warning(f'  - {case.item.nodeid}')
+        if ','.join(runner_tags) in exclude_runner_tags:
+            print('WARNING: excluding test cases with runner tags:', runner_tags)
             continue
 
         target_test_job = TargetTestJob(
@@ -115,63 +104,54 @@ def get_target_test_jobs(
     if fast_pipeline_flag:
         extra_include_yml = ['tools/ci/dynamic_pipelines/templates/fast_pipeline.yml']
 
-    issues['no_env_marker_test_cases'] = sorted(issues['no_env_marker_test_cases'])
-    issues['no_runner_tags'] = sorted(issues['no_runner_tags'])
-
-    return target_test_jobs, extra_include_yml, issues
+    no_env_marker_test_cases.sort()
+    return target_test_jobs, extra_include_yml, no_env_marker_test_cases
 
 
 def generate_target_test_child_pipeline(
-    project: Project,
     paths: str,
     apps: t.List[App],
     output_filepath: str,
 ) -> None:
-    target_test_jobs, extra_include_yml, issues = get_target_test_jobs(project, paths, apps)
-
     with open(KNOWN_GENERATE_TEST_CHILD_PIPELINE_WARNINGS_FILEPATH) as fr:
         known_warnings_dict = yaml.safe_load(fr) or dict()
 
+    exclude_runner_tags_set = set(known_warnings_dict.get('no_runner_tags', []))
+    # EXCLUDE_RUNNER_TAGS is a string separated by ';'
+    # like 'esp32,generic;esp32c3,wifi'
+    if exclude_runner_tags := os.getenv('EXCLUDE_RUNNER_TAGS'):
+        exclude_runner_tags_set.update(exclude_runner_tags.split(';'))
+
+    target_test_jobs, extra_include_yml, no_env_marker_test_cases = get_target_test_jobs(
+        paths=paths,
+        apps=apps,
+        exclude_runner_tags=exclude_runner_tags_set,
+    )
+
     known_no_env_marker_test_cases = set(known_warnings_dict.get('no_env_marker_test_cases', []))
-    no_env_marker_test_cases = set(issues['no_env_marker_test_cases'])
+    no_env_marker_test_cases_set = set(no_env_marker_test_cases)
 
     no_env_marker_test_cases_fail = False
-    if no_env_marker_test_cases - known_no_env_marker_test_cases:
+    if no_env_marker_test_cases_set - known_no_env_marker_test_cases:
         print('ERROR: NEW "no_env_marker_test_cases" detected:')
-        for case in no_env_marker_test_cases - known_no_env_marker_test_cases:
+        for case in no_env_marker_test_cases_set - known_no_env_marker_test_cases:
             print(f'  - {case}')
         no_env_marker_test_cases_fail = True
 
-        print('Please add at least one environment markers to the test cases listed above. '
-              'You may check all the env markers here: tools/ci/idf_pytest/constants.py')
-
-    known_no_runner_tags = set(known_warnings_dict.get('no_runner_tags', []))
-    no_runner_tags = set(issues['no_runner_tags'])
-
-    no_runner_tags_fail = False
-    if no_runner_tags - known_no_runner_tags:
-        print('ERROR: NEW "no_runner_tags" detected:')
-        for tag in no_runner_tags - known_no_runner_tags:
-            print(f'  - {tag}')
-        no_runner_tags_fail = True
-
         print(
-            '- If you\'re the owner of the missing runners, '
-            'please make sure the runners are online and have the required tags.\n'
-            '- If you\'re the owner of the test cases that require the missing tags, '
-            'please add at least one runner with the required tags.\n'
-            '- For other users, please contact the runner owner first, '
-            'or report this issue in our internal CI channel.\n'
-            'If the issue cannot be solved in a short time, '
-            'please add the missing tags to the "no_runner_tags" section '
-            'under the file inside ESP-IDF repo: '
-            f'{os.path.relpath(KNOWN_GENERATE_TEST_CHILD_PIPELINE_WARNINGS_FILEPATH, IDF_PATH)}.'
+            'Please add at least one environment markers to the test cases listed above. '
+            'You may check all the env markers here: tools/ci/idf_pytest/constants.py'
         )
 
-    if no_env_marker_test_cases_fail or no_runner_tags_fail:
+    if no_env_marker_test_cases_fail:
         raise SystemExit('Failed to generate target test child pipeline.')
 
-    dump_jobs_to_yaml(target_test_jobs, output_filepath, DEFAULT_TARGET_TEST_CHILD_PIPELINE_NAME, extra_include_yml)
+    dump_jobs_to_yaml(
+        target_test_jobs,
+        output_filepath,
+        DEFAULT_TARGET_TEST_CHILD_PIPELINE_NAME,
+        extra_include_yml,
+    )
     print(f'Generate child pipeline yaml file {output_filepath} with {sum(j.parallel for j in target_test_jobs)} jobs')
 
 
@@ -187,18 +167,6 @@ def generate_target_test_child_pipeline(
         default=DEFAULT_TEST_PATHS,
         help='Paths to the apps to build.',
     )
-    parser.add_argument(
-        '--project-id',
-        type=int,
-        default=os.getenv('CI_PROJECT_ID'),
-        help='Project ID',
-    )
-    parser.add_argument(
-        '--pipeline-id',
-        type=int,
-        default=os.getenv('PARENT_PIPELINE_ID'),
-        help='Pipeline ID',
-    )
     parser.add_argument(
         '-o',
         '--output',
@@ -215,15 +183,12 @@ def generate_target_test_child_pipeline(
 
     args = parser.parse_args()
 
-    gl_project = Gitlab(args.project_id).project
-
     apps = []
     for f in glob.glob(args.app_info_filepattern):
         apps.extend(import_apps_from_txt(f))
 
     generate_target_test_child_pipeline(
-        gl_project,
-        args.paths,
-        apps,
-        args.output,
+        paths=args.paths,
+        apps=apps,
+        output_filepath=args.output,
     )
diff --git a/tools/ci/dynamic_pipelines/templates/.dynamic_jobs.yml b/tools/ci/dynamic_pipelines/templates/.dynamic_jobs.yml
index 3eff163539f..4d78137e602 100644
--- a/tools/ci/dynamic_pipelines/templates/.dynamic_jobs.yml
+++ b/tools/ci/dynamic_pipelines/templates/.dynamic_jobs.yml
@@ -7,12 +7,16 @@
 .dynamic_build_template:
   extends:
     - .before_script:build
-    - .after_script:build:ccache:upload-when-fail
+    - .after_script:build:ccache-show-stats:upload-failed-job-logs
   image: $ESP_ENV_IMAGE
   stage: build
+  timeout: 1 hour
   variables:
     # Enable ccache for all build jobs. See configure_ci_environment.sh for more ccache related settings.
     IDF_CCACHE_ENABLE: "1"
+    # Since the version 3.21 CMake passes source files and include dirs to ninja using absolute paths.
+    # Needed for pytest junit reports.
+    INSTALL_EXTRA_TOOLS: cmake
   needs:
     - pipeline: $PARENT_PIPELINE_ID
       job: generate_build_child_pipeline
@@ -51,6 +55,7 @@
     PYTEST_NODES: ""
     TARGET_SELECTOR: ""
     ENV_MARKERS: ""
+    INSTALL_EXTRA_TOOLS: "xtensa-esp-elf-gdb riscv32-esp-elf-gdb openocd-esp32 esp-rom-elfs"
     PYTEST_EXTRA_FLAGS: "--dev-passwd ${ETHERNET_TEST_PASSWORD} --dev-user ${ETHERNET_TEST_USER} --capture=fd --verbosity=0"
   cache:
     # Usually do not need submodule-cache in target_test
@@ -64,16 +69,16 @@
       - pytest-embedded/
 # Child pipeline reports won't be collected in the main one
 # https://gitlab.com/groups/gitlab-org/-/epics/8205
-#    reports:
-#      junit: XUNIT_RESULT.xml
+#   reports:
+#     junit: XUNIT_RESULT.xml
     when: always
     expire_in: 1 week
   script:
     # get known failure cases
-    - python tools/ci/get_known_failure_cases_file.py
+    - run_cmd python tools/ci/get_known_failure_cases_file.py
     # get runner env config file
     - retry_failed git clone $TEST_ENV_CONFIG_REPO
-    - python $CHECKOUT_REF_SCRIPT ci-test-runner-configs ci-test-runner-configs
+    - run_cmd python $CHECKOUT_REF_SCRIPT ci-test-runner-configs ci-test-runner-configs
     # CI specific options start from "--known-failure-cases-file xxx". could ignore when running locally
     - run_cmd pytest ${PYTEST_NODES}
       --target ${TARGET_SELECTOR}
@@ -85,4 +90,7 @@
       --parallel-index ${CI_NODE_INDEX:-1}
       ${PYTEST_EXTRA_FLAGS}
   after_script:
-    - python tools/ci/artifacts_handler.py upload --type logs junit_reports
+    - source tools/ci/utils.sh
+    - section_start "upload_junit_reports"
+    - run_cmd python tools/ci/artifacts_handler.py upload --type logs junit_reports
+    - section_end "upload_junit_reports"
diff --git a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml
index 3feff2eb180..e0e3f61f174 100644
--- a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml
+++ b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml
@@ -1,3 +1,6 @@
+# This is the file that contains the known warnings for the generate_test_child_pipeline.py script.
+# no_env_marker_test_cases: List of test cases that do not have environment markers.
+#   each item shall be the test node id, you may check the error message to get the node id.
 no_env_marker_test_cases:
   - components/nvs_flash/test_apps/pytest_nvs_flash.py::test_nvs_flash[default]
   - components/vfs/test_apps/pytest_vfs.py::test_vfs_ccomp[ccomp]
@@ -7,12 +10,24 @@ no_env_marker_test_cases:
   - examples/storage/nvs_rw_value/pytest_nvs_rw_value.py::test_examples_nvs_rw_value
   - examples/storage/nvs_rw_value_cxx/pytest_nvs_rw_value_cxx.py::test_examples_nvs_rw_value_cxx
   - examples/storage/wear_levelling/pytest_wear_levelling_example.py::test_wear_levelling_example
+
+# no_runner_tags: List of runner tags that has no test runner set.
+#   each item shall be a comma separated list of runner tags.
+# NOTE:
+#   1. for multi dut tests, the runner tag shall be <target>_<count>, e.g. esp32_2 instead of esp32,esp32
+#   2. don't have spaces in the comma separated list.
 no_runner_tags:
   - esp32,ip101
   - esp32c2,jtag,xtal_40mhz
   - esp32c3,flash_multi
   - esp32c3,sdcard_sdmode
+  - esp32c5,adc
+  - esp32c5,generic
   - esp32c5,jtag
+  - esp32c5,wifi_ap
+  - esp32c5,wifi_router
+  - esp32c5_2,generic_multi_device
+  - esp32c5_2,wifi_two_dut
   - esp32c6,jtag
   - esp32c61,jtag
   - esp32h2,jtag
diff --git a/tools/ci/python_packages/common_test_methods.py b/tools/ci/python_packages/common_test_methods.py
index 80392fbc27e..fe5db2a9e73 100644
--- a/tools/ci/python_packages/common_test_methods.py
+++ b/tools/ci/python_packages/common_test_methods.py
@@ -1,12 +1,19 @@
-# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
-
 import logging
 import os
 import socket
-from typing import Any, List
+from typing import Any
+from typing import List
+
+try:
+    import netifaces
+except ImportError:
+    from unittest.mock import MagicMock
+
+    netifaces = MagicMock()
+    logging.warning('netifaces is not installed. Please install it to get network interface information.')
 
-import netifaces
 import yaml
 
 ENV_CONFIG_FILE_SEARCH = [
diff --git a/tools/ci/utils.sh b/tools/ci/utils.sh
index f860fef110d..17951e2173a 100644
--- a/tools/ci/utils.sh
+++ b/tools/ci/utils.sh
@@ -35,7 +35,9 @@ function add_doc_server_ssh_keys() {
 }
 
 function fetch_submodules() {
+  section_start "fetch_submodules" "Fetching submodules..."
   python "${SUBMODULE_FETCH_TOOL}" -s "${SUBMODULES_TO_FETCH}"
+  section_end "fetch_submodules"
 }
 
 function get_all_submodules() {
@@ -49,6 +51,19 @@ function set_component_ut_vars() {
   echo "exported variables COMPONENT_UT_DIRS, COMPONENT_UT_EXCLUDES"
 }
 
+# https://docs.gitlab.com/ee/ci/yaml/script.html#use-a-script-to-improve-display-of-collapsible-sections
+function section_start() {
+  local section_title="${1}"
+  local section_description="${2:-$section_title}"
+
+  echo -e "section_start:`date +%s`:${section_title}[collapsed=true]\r\e[0K${section_description}"
+}
+function section_end() {
+  local section_title="${1}"
+
+  echo -e "section_end:`date +%s`:${section_title}\r\e[0K"
+}
+
 function error() {
   printf "\033[0;31m%s\n\033[0m" "${1}" >&2
 }
diff --git a/tools/cmake/build.cmake b/tools/cmake/build.cmake
index c9414c437d4..b3d72516e5a 100644
--- a/tools/cmake/build.cmake
+++ b/tools/cmake/build.cmake
@@ -524,6 +524,7 @@ macro(idf_build_process target)
     cmake_parse_arguments(_ "${options}" "${single_value}" "${multi_value}" ${ARGN})
 
     idf_build_set_property(BOOTLOADER_BUILD "${BOOTLOADER_BUILD}")
+    idf_build_set_property(NON_OS_BUILD "${NON_OS_BUILD}")
 
     idf_build_set_property(IDF_TOOLCHAIN "${IDF_TOOLCHAIN}")
 
diff --git a/tools/cmake/component.cmake b/tools/cmake/component.cmake
index 1ad0ed05ede..1651a659028 100644
--- a/tools/cmake/component.cmake
+++ b/tools/cmake/component.cmake
@@ -122,6 +122,7 @@ endfunction()
 # keeps a list of all its properties.
 #
 function(__component_write_properties output_file)
+    set(component_properties_text "")
     idf_build_get_property(component_targets __COMPONENT_TARGETS)
     foreach(component_target ${component_targets})
         __component_get_property(component_properties ${component_target} __COMPONENT_PROPERTIES)
@@ -130,8 +131,8 @@ function(__component_write_properties output_file)
             set(component_properties_text
                 "${component_properties_text}\nset(__component_${component_target}_${property} \"${val}\")")
         endforeach()
-        file(WRITE ${output_file} "${component_properties_text}")
     endforeach()
+    file(WRITE ${output_file} "${component_properties_text}")
 endfunction()
 
 #
diff --git a/tools/cmake/run_size_tool.cmake b/tools/cmake/run_size_tool.cmake
index 1e237d5bdb8..76164d5e24e 100644
--- a/tools/cmake/run_size_tool.cmake
+++ b/tools/cmake/run_size_tool.cmake
@@ -36,6 +36,10 @@ if(DEFINED ENV{SIZE_DIFF_FILE})
     list(APPEND IDF_SIZE_CMD "--diff=$ENV{SIZE_DIFF_FILE}")
 endif()
 
+if(DEFINED ENV{ESP_IDF_SIZE_NG})
+    list(APPEND IDF_SIZE_CMD "--unify")
+endif()
+
 list(APPEND IDF_SIZE_CMD ${MAP_FILE})
 
 execute_process(COMMAND ${IDF_SIZE_CMD}
diff --git a/tools/cmake/version.cmake b/tools/cmake/version.cmake
index 6293abcca1f..d2ea49e4b8e 100644
--- a/tools/cmake/version.cmake
+++ b/tools/cmake/version.cmake
@@ -1,5 +1,5 @@
 set(IDF_VERSION_MAJOR 5)
-set(IDF_VERSION_MINOR 4)
+set(IDF_VERSION_MINOR 5)
 set(IDF_VERSION_PATCH 0)
 
 set(ENV{IDF_VERSION} "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}")
diff --git a/tools/detect_python.fish b/tools/detect_python.fish
index e8988e3922f..5b53fb9ab50 100644
--- a/tools/detect_python.fish
+++ b/tools/detect_python.fish
@@ -3,11 +3,11 @@
 # This is a port of detect_python.sh. More information are provided there.
 
 set OLDEST_PYTHON_SUPPORTED_MAJOR 3
-set OLDEST_PYTHON_SUPPORTED_MINOR 8
+set OLDEST_PYTHON_SUPPORTED_MINOR 9
 
 set -x ESP_PYTHON python
 
-for p_cmd in python3 python python3.8 python3.9 python3.10 python3.11 python3.12;
+for p_cmd in python3 python python3.9 python3.10 python3.11 python3.12 python3.13;
     $p_cmd --version >/dev/null 2>&1; or continue
     echo "Checking \"$p_cmd\" ..."
 
diff --git a/tools/detect_python.sh b/tools/detect_python.sh
index bc3e65c59ac..eb3b759f922 100644
--- a/tools/detect_python.sh
+++ b/tools/detect_python.sh
@@ -8,11 +8,11 @@
 # 3. If required version of python is not found, script will fail
 
 OLDEST_PYTHON_SUPPORTED_MAJOR=3
-OLDEST_PYTHON_SUPPORTED_MINOR=8
+OLDEST_PYTHON_SUPPORTED_MINOR=9
 
 ESP_PYTHON=python
 
-for p_cmd in python3 python python3.8 python3.9 python3.10 python3.11 python3.12; do
+for p_cmd in python3 python python3.9 python3.10 python3.11 python3.12 python3.13; do
     $p_cmd --version >/dev/null 2>&1 || continue
     echo "Checking \"$p_cmd\" ..."
 
diff --git a/tools/esp_prov/transport/transport_http.py b/tools/esp_prov/transport/transport_http.py
index f17cfc8f6de..1474e4627f3 100644
--- a/tools/esp_prov/transport/transport_http.py
+++ b/tools/esp_prov/transport/transport_http.py
@@ -1,8 +1,9 @@
-# SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 #
 import socket
-from http.client import HTTPConnection, HTTPSConnection
+from http.client import HTTPConnection
+from http.client import HTTPSConnection
 
 from utils import str_to_bytes
 
@@ -12,7 +13,7 @@
 class Transport_HTTP(Transport):
     def __init__(self, hostname, ssl_context=None):
         try:
-            socket.gethostbyname(hostname.split(':')[0])
+            socket.getaddrinfo(hostname.split(':')[0], None)
         except socket.gaierror:
             raise RuntimeError(f'Unable to resolve hostname: {hostname}')
 
@@ -35,7 +36,7 @@ def _send_post_request(self, path, data):
             # While establishing a session, the device sends the Set-Cookie header
             # with value 'session=cookie_session_id' in its first response of the session to the tool.
             # To maintain the same session, successive requests from the tool should include
-            # an additional 'Cookie' header with the above recieved value.
+            # an additional 'Cookie' header with the above received value.
             for hdr_key, hdr_val in response.getheaders():
                 if hdr_key == 'Set-Cookie':
                     self.headers['Cookie'] = hdr_val
diff --git a/tools/export_utils/activate_venv.py b/tools/export_utils/activate_venv.py
index fa3ed051453..d409d50eadf 100644
--- a/tools/export_utils/activate_venv.py
+++ b/tools/export_utils/activate_venv.py
@@ -87,9 +87,16 @@ def get_idf_env() -> Dict[str,str]:
         'IDF_PYTHON_ENV_PATH': os.environ['IDF_PYTHON_ENV_PATH'],
     }
 
-    for line in stdout.splitlines():
-        var, val = line.split('=')
-        idf_env[var] = val
+    try:
+        for line in stdout.splitlines():
+            var, val = line.split('=')
+            idf_env[var] = val
+    except ValueError as e:
+        debug('\n'.join(['Output from `./tools/idf_tools.py export --format key-value`:',
+                         f'{stdout}']))
+        raise ValueError('\n'.join(['Please ensure your ESP-IDF installation is clean, especially file `./tools/idf_tools.py`.',
+                                    'The command `./tools/idf_tools.py export` appears to be returning unexpected values.',
+                                    f'Details: {e}']))
 
     if 'PATH' in idf_env:
         idf_env['PATH'] = os.pathsep.join([extra_paths, idf_env['PATH']])
diff --git a/tools/export_utils/shell_types.py b/tools/export_utils/shell_types.py
index bb0d0c5ff54..d2e34606723 100644
--- a/tools/export_utils/shell_types.py
+++ b/tools/export_utils/shell_types.py
@@ -1,10 +1,13 @@
 # SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
+import getpass
 import os
 import re
 import shutil
 import sys
 import textwrap
+from datetime import datetime
+from datetime import timedelta
 from pathlib import Path
 from subprocess import run
 from tempfile import gettempdir
@@ -18,6 +21,7 @@
 import click
 from console_output import debug
 from console_output import status_message
+from console_output import warn
 from utils import conf
 from utils import run_cmd
 
@@ -27,10 +31,26 @@ def __init__(self, shell: str, deactivate_cmd: str, new_esp_idf_env: Dict[str,st
         self.shell = shell
         self.deactivate_cmd = deactivate_cmd
         self.new_esp_idf_env = new_esp_idf_env
-        self.tmp_dir_path = Path(gettempdir()) / 'esp_idf_activate'
+
+        try:
+            self.tmp_dir_path = Path(gettempdir()) / ('esp_idf_activate_' + getpass.getuser())
+        except Exception as e:
+            self.tmp_dir_path = Path(gettempdir()) / 'esp_idf_activate'
+            warn(f'Failed to get username with error: {e}. Using default temporary directory {self.tmp_dir_path}.')
+
         if not conf.ARGS.debug and os.path.exists(self.tmp_dir_path):
             # Do not cleanup temporary directory when debugging
-            shutil.rmtree(self.tmp_dir_path)
+            for item in self.tmp_dir_path.iterdir():
+                try:
+                    if item.is_file():
+                        current_time = datetime.now()
+                        file_creation_time = datetime.fromtimestamp(os.path.getctime(item))
+                        # delete files older than 1 hour to avoid datarace when using activation in parallel
+                        if current_time - file_creation_time > timedelta(hours=1):
+                            item.unlink()
+                except Exception as e:
+                    warn(f'Failed to clean temp activation directory with file {item}: {e}')
+
         self.tmp_dir_path.mkdir(parents=True, exist_ok=True)
 
     def export(self) -> None:
diff --git a/tools/idf.py b/tools/idf.py
index 8059c42cca3..61eaf2bddd2 100755
--- a/tools/idf.py
+++ b/tools/idf.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 #
-# SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -8,7 +8,6 @@
 #
 # You don't have to use idf.py, you can use cmake directly
 # (or use cmake in an IDE)
-
 # WARNING: we don't check for Python build-time dependencies until
 # check_environment() function below. If possible, avoid importing
 # any external libraries here - put in external script, or import in
@@ -16,15 +15,21 @@
 import codecs
 import json
 import locale
-import os
 import os.path
 import shlex
 import subprocess
 import sys
-from collections import Counter, OrderedDict, _OrderedDictKeysView
+from collections import Counter
+from collections import OrderedDict
+from collections.abc import KeysView
 from importlib import import_module
 from pkgutil import iter_modules
-from typing import Any, Callable, Dict, List, Optional, Union
+from typing import Any
+from typing import Callable
+from typing import Dict
+from typing import List
+from typing import Optional
+from typing import Union
 
 # pyc files remain in the filesystem when switching between branches which might raise errors for incompatible
 # idf.py extensions. Therefore, pyc file generation is turned off:
@@ -39,13 +44,19 @@
     if os.getenv('IDF_COMPONENT_MANAGER') != '0':
         from idf_component_manager import idf_extensions
 except ImportError as e:
-    # For example, importing click could cause this.
-    print((f'Cannot import module "{e.name}". This usually means that "idf.py" was not '
+    print((f'{e}\n'
+           f'This usually means that "idf.py" was not '
            f'spawned within an ESP-IDF shell environment or the python virtual '
            f'environment used by "idf.py" is corrupted.\n'
            f'Please use idf.py only in an ESP-IDF shell environment. If problem persists, '
            f'please try to install ESP-IDF tools again as described in the Get Started guide.'),
           file=sys.stderr)
+    if e.name is None:
+        # The ImportError or ModuleNotFoundError might be raised without
+        # specifying a module name. In this not so common situation, re-raise
+        # the exception to print all the information that could assist in
+        # identifying the problem.
+        raise
 
     sys.exit(1)
 
@@ -128,7 +139,7 @@ def _safe_relpath(path: str, start: Optional[str]=None) -> str:
         return os.path.abspath(path)
 
 
-def init_cli(verbose_output: List=None) -> Any:
+def init_cli(verbose_output: Optional[List]=None) -> Any:
     # Click is imported here to run it after check_environment()
     import click
 
@@ -194,7 +205,7 @@ def __init__(self, callback: Callable, name: str, aliases: List, dependencies: O
             self.action_args = action_args
             self.aliases = aliases
 
-        def __call__(self, context: click.core.Context, global_args: PropertyDict, action_args: Dict=None) -> None:
+        def __call__(self, context: click.core.Context, global_args: PropertyDict, action_args: Optional[Dict]=None) -> None:
             if action_args is None:
                 action_args = self.action_args
 
@@ -295,7 +306,7 @@ class Scope(object):
 
         SCOPES = ('default', 'global', 'shared')
 
-        def __init__(self, scope: Union['Scope', str]=None) -> None:  # noqa: F821
+        def __init__(self, scope: Optional[Union['Scope', str]]=None) -> None:  # noqa: F821
             if scope is None:
                 self._scope = 'default'
             elif isinstance(scope, str) and scope in self.SCOPES:
@@ -318,7 +329,7 @@ def __str__(self) -> str:
 
     class Option(click.Option):
         """Option that knows whether it should be global"""
-        def __init__(self, scope: Union[Scope, str]=None, deprecated: Union[Dict, str, bool]=False, hidden: bool=False, **kwargs: str) -> None:
+        def __init__(self, scope: Optional[Union[Scope, str]]=None, deprecated: Union[Dict, str, bool]=False, hidden: bool=False, **kwargs: str) -> None:
             """
             Keyword arguments additional to Click's Option class:
 
@@ -356,7 +367,7 @@ def get_help_record(self, ctx: click.core.Context) -> Any:
 
     class CLI(click.MultiCommand):
         """Action list contains all actions with options available for CLI"""
-        def __init__(self, all_actions: Dict=None, verbose_output: List=None, help: str=None) -> None:
+        def __init__(self, all_actions: Optional[Dict]=None, verbose_output: Optional[List]=None, help: Optional[str]=None) -> None:
             super(CLI, self).__init__(
                 chain=True,
                 invoke_without_command=True,
@@ -440,7 +451,7 @@ def get_command(self, ctx: click.core.Context, name: str) -> Optional[Action]:
                     return Action(name=name, callback=callback.unwrapped_callback)
                 return None
 
-        def _print_closing_message(self, args: PropertyDict, actions: _OrderedDictKeysView) -> None:
+        def _print_closing_message(self, args: PropertyDict, actions: KeysView) -> None:
             # print a closing message of some kind,
             # except if any of the following actions were requested
             if any(t in str(actions) for t in ('flash', 'dfu', 'uf2', 'uf2-app', 'qemu')):
@@ -578,7 +589,7 @@ def execute_tasks(self, tasks: List, **kwargs: str) -> OrderedDict:
 
                 dependecies_processed = True
 
-                # If task have some dependecies they have to be executed before the task.
+                # If task have some dependencies they have to be executed before the task.
                 for dep in task.dependencies:
                     if dep not in tasks_to_run.keys():
                         # If dependent task is in the list of unprocessed tasks move to the front of the list
@@ -711,11 +722,11 @@ def parse_project_dir(project_dir: str) -> Any:
     return CLI(help=cli_help, verbose_output=verbose_output, all_actions=all_actions)
 
 
-def main(argv: List[Any] = None) -> None:
+def main(argv: Optional[List[Any]] = None) -> None:
     # Check the environment only when idf.py is invoked regularly from command line.
     checks_output = None if SHELL_COMPLETE_RUN else check_environment()
 
-    # Check existance of the current working directory to prevent exceptions from click cli.
+    # Check existence of the current working directory to prevent exceptions from click cli.
     try:
         os.getcwd()
     except FileNotFoundError as e:
diff --git a/tools/idf_py_actions/debug_ext.py b/tools/idf_py_actions/debug_ext.py
index eb05437e925..02d4f4f9567 100644
--- a/tools/idf_py_actions/debug_ext.py
+++ b/tools/idf_py_actions/debug_ext.py
@@ -408,14 +408,23 @@ def get_gdb_args(project_desc: Dict[str, Any]) -> List:
         return args
 
     def _get_gdbgui_version(ctx: Context) -> Tuple[int, ...]:
-        completed_process = subprocess.run(['gdbgui', '--version'], stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
-        captured_output = completed_process.stdout.decode('utf-8', 'ignore')
-
-        if completed_process.returncode != 0:
+        try:
+            completed_process = subprocess.run(['gdbgui', '--version'], stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
+            subprocess_success = True
+            captured_output = completed_process.stdout.decode('utf-8', 'ignore')
+        except FileNotFoundError:
+            # This is happening at least with Python 3.12 when gdbgui is not installed
+            subprocess_success = False
+
+        if not subprocess_success or completed_process.returncode != 0:
             if sys.version_info[:2] >= (3, 11) and sys.platform == 'win32':
                 raise SystemExit('Unfortunately, gdbgui is supported only with Python 3.10 or older. '
                                  'See: https://github.com/espressif/esp-idf/issues/10116. '
                                  'Please use "idf.py gdb" or debug in Eclipse/Vscode instead.')
+            if sys.version_info[:2] >= (3, 13) and sys.platform != 'win32':
+                raise SystemExit('Unfortunately, gdbgui is supported only with Python 3.12 or older. '
+                                 'See: https://github.com/cs01/gdbgui/issues/494. '
+                                 'Please use "idf.py gdb" or debug in Eclipse/Vscode instead.')
             raise FatalError('Error starting gdbgui. Please make sure gdbgui has been installed with '
                              '"install.{sh,bat,ps1,fish} --enable-gdbgui" and can be started. '
                              f'Error: {captured_output}', ctx)
diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml
index f17f3fa2874..67c57f3a7c6 100644
--- a/tools/idf_py_actions/hints.yml
+++ b/tools/idf_py_actions/hints.yml
@@ -443,3 +443,11 @@
 -
     re: "discarded output section: .*\\.got"
     hint: "Some objects being linked were compiled with the \"-fpic\"/\"-fpie\" options. These options may be suitable for \"linux\" builds, but must not be applied for esp32XX targets."
+
+-
+    re: "(error: Total discarded sections size is \\d+ bytes)|(region [`'.\\w]+ overflowed by \\d+ bytes)"
+    hint: "The binary size has exceeded the limit. To resolve the issue consider reducing the binary size.\nYou can explore size optimization techniques in the documentation by running 'idf.py docs -sp api-guides/performance/size.html#reducing-overall-size'.\nNote that the linker performed the dead code elimination."
+
+-
+    re: "implicit declaration of function '__VA_NARG__'"
+    hint: "__VA_NARG_ has been renamed. Please use ESP_VA_NARG instead"
diff --git a/tools/idf_py_actions/qemu_ext.py b/tools/idf_py_actions/qemu_ext.py
index 685e9c8363e..ad46a07ddee 100644
--- a/tools/idf_py_actions/qemu_ext.py
+++ b/tools/idf_py_actions/qemu_ext.py
@@ -213,7 +213,7 @@ def _get_project_desc(args: PropertyDict, ctx: Context) -> Any:
             project_desc = json.load(f)
         return project_desc
 
-    def qemu(action: str, ctx: Context, args: PropertyDict, qemu_extra_args: str, gdb: bool, graphics: bool, efuse_file: str) -> None:
+    def qemu(action: str, ctx: Context, args: PropertyDict, qemu_extra_args: str, gdb: bool, graphics: bool, efuse_file: str, flash_file: str) -> None:
         project_desc = _get_project_desc(args, ctx)
 
         # Determine the target and check if we have the necessary QEMU binary
@@ -230,11 +230,21 @@ def qemu(action: str, ctx: Context, args: PropertyDict, qemu_extra_args: str, gd
 
         # Generate flash image and efuse image
         flash_size = get_sdkconfig_value(project_desc['config_file'], 'CONFIG_ESPTOOLPY_FLASHSIZE')
-        bin_path = os.path.join(args.build_dir, 'qemu_flash.bin')
-        yellow_print(f'Generating flash image: {bin_path}')
-        subprocess.check_call([
-            sys.executable, '-m', 'esptool', f'--chip={target}', 'merge_bin', f'--output={bin_path}',
-            f'--fill-flash-size={flash_size}', '@flash_args'], cwd=args.build_dir)
+
+        if flash_file:
+            bin_path = flash_file
+            try:
+                open(bin_path, 'rb').close()
+                yellow_print(f'Using provided flash image: {bin_path}')
+            except FileNotFoundError:
+                red_print(f'The provided flash image file \"{bin_path}\" could not be found')
+                raise SystemExit(1)
+        else:
+            bin_path = os.path.join(args.build_dir, 'qemu_flash.bin')
+            yellow_print(f'Generating flash image: {bin_path}')
+            subprocess.check_call([
+                sys.executable, '-m', 'esptool', f'--chip={target}', 'merge_bin', f'--output={bin_path}',
+                f'--fill-flash-size={flash_size}', '@flash_args'], cwd=args.build_dir)
 
         if efuse_file:
             efuse_bin_path = efuse_file
@@ -251,12 +261,18 @@ def qemu(action: str, ctx: Context, args: PropertyDict, qemu_extra_args: str, gd
         # Prepare QEMU launch arguments
         qemu_args = [qemu_target_info.qemu_prog]
         qemu_args += qemu_target_info.qemu_args.split(' ')
+        # When boot mode is specified, the flash image is not required.
+        if not options.boot_mode:
+            qemu_args += [
+                '-drive', f'file={bin_path},if=mtd,format=raw',
+            ]
+
         qemu_args += [
-            '-drive', f'file={bin_path},if=mtd,format=raw',
             '-drive', f'file={efuse_bin_path},if=none,format=raw,id=efuse',
             '-global', f'driver={qemu_target_info.efuse_device},property=drive,value=efuse',
             '-global', f'driver=timer.{target}.timg,property=wdt_disable,value=true',
         ]
+
         if '-nic' not in qemu_extra_args:
             qemu_args += ['-nic', 'user,model=open_eth']
 
@@ -339,6 +355,13 @@ def cleanup_qemu() -> None:
                                  'in build directory is used.'),
                         'is_flag': False,
                         'default': '',
+                    },
+                    {
+                        'names': ['--flash-file'],
+                        'help': ('File used as the qemu flash image. If not specified, qemu_flash.bin file '
+                                 'in build directory is used.'),
+                        'is_flag': False,
+                        'default': '',
                     }
                 ]
             }
diff --git a/tools/idf_py_actions/roms.json b/tools/idf_py_actions/roms.json
index 40a4ff930a0..01524dc9cf1 100644
--- a/tools/idf_py_actions/roms.json
+++ b/tools/idf_py_actions/roms.json
@@ -44,6 +44,13 @@
       "build_date_str": "Feb  7 2021"
     }
   ],
+  "esp32c5": [
+    {
+      "rev": 0,
+      "build_date_str_addr": "0x4004b3c4",
+      "build_date_str": "Mar 29 2024"
+    }
+  ],
   "esp32c6": [
     {
       "rev": 0,
diff --git a/tools/idf_py_actions/serial_ext.py b/tools/idf_py_actions/serial_ext.py
index 9d8c1b3a3a7..502ca5ecec0 100644
--- a/tools/idf_py_actions/serial_ext.py
+++ b/tools/idf_py_actions/serial_ext.py
@@ -105,6 +105,7 @@ def monitor(
         timestamps: bool,
         timestamp_format: str,
         force_color: bool,
+        disable_auto_color: bool,
     ) -> None:
         """
         Run esp_idf_monitor to watch build output
@@ -187,6 +188,9 @@ def monitor(
         if force_color or os.name == 'nt':
             monitor_args += ['--force-color']
 
+        if disable_auto_color:
+            monitor_args += ['--disable-auto-color']
+
         idf_py = [PYTHON] + _get_commandline_options(ctx)  # commands to re-run idf.py
         monitor_args += ['-m', ' '.join("'%s'" % a for a in idf_py)]
         hints = not args.no_hints
@@ -1011,6 +1015,11 @@ def efuse_write_protect(action: str, ctx: click.core.Context, args: PropertyDict
                         'is_flag': True,
                         'help': 'Always print ANSI for colors',
                     },
+                    {
+                        'names': ['--disable-auto-color'],
+                        'is_flag': True,
+                        'help': 'Disable auto coloring logs',
+                    },
                 ],
                 'order_dependencies': [
                     'flash',
diff --git a/tools/idf_tools.py b/tools/idf_tools.py
index a928c046567..5ae9f4cae21 100755
--- a/tools/idf_tools.py
+++ b/tools/idf_tools.py
@@ -2122,8 +2122,12 @@ def process_tool(
 
     if not tool.versions_installed:
         if tool.get_install_type() == IDFTool.INSTALL_ALWAYS:
-            handle_missing_versions(tool, tool_name, install_cmd, prefer_system_hint)
-            tool_found = False
+            if os.getenv('IDF_SKIP_TOOLS_CHECK', '0') == '1':
+                warn(f'Tool {tool_name} is not installed and IDF_SKIP_TOOLS_CHECK is set. '
+                     'This may cause build failures.')
+            else:
+                handle_missing_versions(tool, tool_name, install_cmd, prefer_system_hint)
+                tool_found = False
         # If a tool found, but it is optional and does not have versions installed, use whatever is in PATH.
         return tool_export_paths, tool_export_vars, tool_found
 
@@ -2574,7 +2578,10 @@ def action_install_python_env(args):  # type: ignore
     reinstall = args.reinstall
     idf_python_env_path, _, virtualenv_python, idf_version = get_python_env_path()
 
-    is_virtualenv = hasattr(sys, 'real_prefix') or (hasattr(sys, 'base_prefix') and sys.base_prefix != sys.prefix)
+    nix_store = os.environ.get('NIX_STORE')
+    is_nix = nix_store is not None and sys.base_prefix.startswith(nix_store) and sys.prefix.startswith(nix_store)
+
+    is_virtualenv = not is_nix and (hasattr(sys, 'real_prefix') or (hasattr(sys, 'base_prefix') and sys.base_prefix != sys.prefix))
     if is_virtualenv and (not os.path.exists(idf_python_env_path) or reinstall):
         fatal('This script was called from a virtual environment, can not create a virtual environment again')
         raise SystemExit(1)
diff --git a/tools/ldgen/ldgen/fragments.py b/tools/ldgen/ldgen/fragments.py
index 0acd81f605d..80cc167e207 100644
--- a/tools/ldgen/ldgen/fragments.py
+++ b/tools/ldgen/ldgen/fragments.py
@@ -1,13 +1,34 @@
 #
-# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 #
-
-from typing import Any, Dict, List, Optional, Set, Tuple, Union
-
-from pyparsing import (Combine, Forward, Group, IndentedBlock, Keyword, LineEnd, Literal, OneOrMore, Opt,
-                       ParseFatalException, SkipTo, Suppress, Word, ZeroOrMore, alphanums, alphas, delimited_list,
-                       nums, rest_of_line)
+from typing import Any
+from typing import Dict
+from typing import List
+from typing import Optional
+from typing import Set
+from typing import Tuple
+from typing import Union
+
+from pyparsing import alphanums
+from pyparsing import alphas
+from pyparsing import Combine
+from pyparsing import delimited_list
+from pyparsing import Forward
+from pyparsing import Group
+from pyparsing import IndentedBlock
+from pyparsing import Keyword
+from pyparsing import LineEnd
+from pyparsing import Literal
+from pyparsing import nums
+from pyparsing import OneOrMore
+from pyparsing import Opt
+from pyparsing import ParseFatalException
+from pyparsing import rest_of_line
+from pyparsing import SkipTo
+from pyparsing import Suppress
+from pyparsing import Word
+from pyparsing import ZeroOrMore
 
 
 class Empty:
@@ -227,11 +248,11 @@ class Sort(EntryFlag):
     _keywords = Keyword('name') | Keyword('alignment') | Keyword('init_priority')
     SORT = (Keyword('SORT').suppress()
             + Suppress('(')
-            + _keywords.set_results_name('first')
-            + Opt(Suppress(',') + _keywords.set_results_name('second'))
+            + Opt(_keywords.set_results_name('first')
+            + Opt(Suppress(',') + _keywords.set_results_name('second')))
             + Suppress(')'))
 
-    def __init__(self, first: str, second: Optional[str] = None):
+    def __init__(self, first: Optional[str] = None, second: Optional[str] = None):
         self.first = first
         self.second = second
 
@@ -244,7 +265,7 @@ def __eq__(self, other):
 
     @staticmethod
     def parse(toks):
-        return Sort(toks.first, toks.second or None)
+        return Sort(toks.first or None, toks.second or None)
 
 
 class Flag:
diff --git a/tools/ldgen/test/test_fragments.py b/tools/ldgen/test/test_fragments.py
index 9cc3899e989..c7e72892eef 100755
--- a/tools/ldgen/test/test_fragments.py
+++ b/tools/ldgen/test/test_fragments.py
@@ -705,6 +705,7 @@ def test_sort_flag(self):
 archive: libmain.a
 entries:
     obj1 (default);
+        text->flash_text SORT(),
         text->flash_text SORT(name),
         rodata->flash_rodata SORT(alignment),
         data->dram0_data SORT(init_priority),
@@ -717,7 +718,8 @@ def test_sort_flag(self):
         fragment_file = parse_fragment_file(test_fragment, self.sdkconfig)
         fragment = fragment_file.fragments[0]
 
-        expected = [Flag('text', 'flash_text', [Sort('name')]),
+        expected = [Flag('text', 'flash_text', [Sort()]),
+                    Flag('text', 'flash_text', [Sort('name')]),
                     Flag('rodata', 'flash_rodata', [Sort('alignment')]),
                     Flag('data', 'dram0_data', [Sort('init_priority')]),
                     Flag('bss', 'dram0_bss', [Sort('name', 'alignment')]),
diff --git a/tools/mass_mfg/docs/README.rst b/tools/mass_mfg/docs/README.rst
index 537d8008e3b..42b3a91280b 100644
--- a/tools/mass_mfg/docs/README.rst
+++ b/tools/mass_mfg/docs/README.rst
@@ -157,7 +157,7 @@ Running the utility
 
 **Usage**::
 
-    python mfg_gen.py generate [-h] [--fileid FILEID] [--version {1,2}] [--keygen]
+    python mfg_gen.py generate [-h] [--prefix_num start length] [--fileid FILEID] [--version {1,2}] [--keygen]
                                     [--inputkey INPUTKEY] [--outdir OUTDIR]
                                     [--key_protect_hmac] [--kp_hmac_keygen]
                                     [--kp_hmac_keyfile KP_HMAC_KEYFILE] [--kp_hmac_inputkey KP_HMAC_INPUTKEY]
@@ -184,6 +184,10 @@ Running the utility
     +=============================================+===============================================================================+
     | ``-h`` / ``--help``                         | Show the help message and exit                                                |
     +---------------------------------------------+-------------------------------------------------------------------------------+
+    | ``--prefix_num start length``               | Prefix number start and length (in digits) to be added for each output        |
+    |                                             | filename. The number is used as monotonic counter, thus different for each    |
+    |                                             | file.                                                                         |
+    +---------------------------------------------+-------------------------------------------------------------------------------+
     | ``--fileid FILEID``                         | Unique file identifier (any key in values file)                               |
     |                                             | for each filename suffix (Default: numeric value(1,2,3...))                   |
     +---------------------------------------------+-------------------------------------------------------------------------------+
diff --git a/tools/mass_mfg/mfg_gen.py b/tools/mass_mfg/mfg_gen.py
index 7348ef2a748..00260b46c34 100644
--- a/tools/mass_mfg/mfg_gen.py
+++ b/tools/mass_mfg/mfg_gen.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 #
-# SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
 #
 import argparse
@@ -262,11 +262,14 @@ def create_intermediate_csv(args, keys_in_values_file, keys_repeat, is_encr=Fals
             values_file_reader = csv.reader(csv_values_file, delimiter=',')
             next(values_file_reader)
 
-            # Create new directory(if doesn't exist) to store csv file generated
+            # Create new directory (if doesn't exist) to store csv file generated
             output_csv_target_dir = create_dir('csv', args.outdir)
-            # Create new directory(if doesn't exist) to store bin file generated
+            # Create new directory (if doesn't exist) to store bin file generated
             output_bin_target_dir = create_dir('bin', args.outdir)
 
+            if args.prefix_num:
+                prefix_num_start, prefix_num_digits = args.prefix_num
+
             for values_data_line in values_file_reader:
                 key_value_data = list(zip_longest(keys_in_values_file, values_data_line))
 
@@ -275,9 +278,18 @@ def create_intermediate_csv(args, keys_in_values_file, keys_repeat, is_encr=Fals
 
                 key_value_pair = key_value_data[:]
 
-                # Verify if output csv file does not exist
-                csv_filename = args.prefix + '-' + file_identifier_value + '.' + 'csv'
+                if args.prefix_num:
+                    # Create file name prefix based on user supplied start and length
+                    prefix_number = f'{prefix_num_start:0{prefix_num_digits}}'
+                    csv_filename = args.prefix + '-' + prefix_number + '-' + file_identifier_value + '.' + 'csv'
+                    bin_filename = args.prefix + '-' + prefix_number + '-' + file_identifier_value + '.' + 'bin'
+                    prefix_num_start += 1
+                else:
+                    csv_filename = args.prefix + '-' + file_identifier_value + '.' + 'csv'
+                    bin_filename = args.prefix + '-' + file_identifier_value + '.' + 'bin'
+
                 output_csv_file = output_csv_target_dir + csv_filename
+                # Verify if output csv file does not exist
                 if os.path.isfile(output_csv_file):
                     raise SystemExit('Target csv file: %s already exists.`' % output_csv_file)
 
@@ -285,9 +297,8 @@ def create_intermediate_csv(args, keys_in_values_file, keys_repeat, is_encr=Fals
                 add_data_to_file(config_data_to_write, key_value_pair, output_csv_file)
                 print('\nCreated CSV file: ===>', output_csv_file)
 
-                # Verify if output bin file does not exist
-                bin_filename = args.prefix + '-' + file_identifier_value + '.' + 'bin'
                 output_bin_file = output_bin_target_dir + bin_filename
+                # Verify if output bin file does not exist
                 if os.path.isfile(output_bin_file):
                     raise SystemExit('Target binary file: %s already exists.`' % output_bin_file)
 
@@ -398,6 +409,11 @@ def main():
                                 default=None,
                                 help='Size of NVS partition in bytes\
                                     \n(must be multiple of 4096)')
+        parser_gen.add_argument('--prefix_num',
+                                type=int,
+                                nargs=2,
+                                metavar=('start', 'length'),
+                                help='Prefix number (counter) start and length (in digits) to be added for each output filename')
         parser_gen.add_argument('--fileid',
                                 default=None,
                                 help='''Unique file identifier(any key in values file) \
diff --git a/tools/mocks/freertos/CMakeLists.txt b/tools/mocks/freertos/CMakeLists.txt
index ce6111260ab..9286bd3d2ce 100644
--- a/tools/mocks/freertos/CMakeLists.txt
+++ b/tools/mocks/freertos/CMakeLists.txt
@@ -25,7 +25,8 @@ idf_component_mock(INCLUDE_DIRS ${include_dirs}
     ${original_freertos_dir}/esp_additions/include/freertos/idf_additions.h
     ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/task.h
     ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/event_groups.h
-    ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/queue.h)
+    ${original_freertos_dir}/FreeRTOS-Kernel/include/freertos/queue.h
+    ${original_freertos_dir}/FreeRTOS-Kernel/portable/linux/include/freertos/portmacro.h)
 
 idf_component_get_property(freertos_lib freertos COMPONENT_LIB)
 target_compile_definitions(${freertos_lib} PUBLIC "projCOVERAGE_TEST=0")
diff --git a/tools/python_version_checker.py b/tools/python_version_checker.py
index 0ae6d8e7d41..aadaa29df41 100755
--- a/tools/python_version_checker.py
+++ b/tools/python_version_checker.py
@@ -1,6 +1,6 @@
 #!/usr/bin/env python
 #
-# SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -8,9 +8,8 @@
 #
 # There are related tools/detect_python.{sh,fish} scripts which are called earlier when the paths are not properly
 # set-up and they only intend to prefer the use of Python 3 over Python 2. Why not more? All possible executables
-# (python3.8, python3.9, ...) cannot be hardcoded there and at the end, the user is responsible to set-up a system
+# (python3.9, python3.10, ...) cannot be hardcoded there and at the end, the user is responsible to set-up a system
 # where "python" or "python3" of compatible version is available.
-
 import sys
 
 try:
@@ -20,7 +19,7 @@
 except ImportError:
     pass
 
-OLDEST_PYTHON_SUPPORTED = (3, 8)  # keep it as tuple for comparison with sys.version_info
+OLDEST_PYTHON_SUPPORTED = (3, 9)  # keep it as tuple for comparison with sys.version_info
 
 
 def _ver_to_str(it):  # type: (Iterable) -> str
diff --git a/tools/requirements/requirements.ci.txt b/tools/requirements/requirements.ci.txt
index fa1ac259d40..dfec5b20fc3 100644
--- a/tools/requirements/requirements.ci.txt
+++ b/tools/requirements/requirements.ci.txt
@@ -15,3 +15,4 @@ pyyaml
 SimpleWebSocketServer
 pylint-gitlab
 minio
+prettytable
diff --git a/tools/requirements/requirements.gdbgui.txt b/tools/requirements/requirements.gdbgui.txt
index 2d7f1cd434f..60cbf384a70 100644
--- a/tools/requirements/requirements.gdbgui.txt
+++ b/tools/requirements/requirements.gdbgui.txt
@@ -7,5 +7,6 @@
 
 # gdbgui Python 3.11 issue https://github.com/cs01/gdbgui/issues/447 was fixed in 0.15.2.0. Windows users need an
 # older Python to use since new gdbgui versions don't support Windows anymore.
-gdbgui; sys_platform != 'win32'
+# Python 3.13 is not supported: https://github.com/cs01/gdbgui/issues/494
+gdbgui; sys_platform != 'win32' and python_version < "3.13"
 gdbgui; sys_platform == 'win32' and python_version < "3.11"
diff --git a/tools/test_apps/build_system/bootloader/sdkconfig.ci.verbose_logging b/tools/test_apps/build_system/bootloader/sdkconfig.ci.verbose_logging
index 2ce67a363ce..06028d51aba 100644
--- a/tools/test_apps/build_system/bootloader/sdkconfig.ci.verbose_logging
+++ b/tools/test_apps/build_system/bootloader/sdkconfig.ci.verbose_logging
@@ -2,3 +2,4 @@
 # Turn verbose log on for bootloader
 #
 CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE=y
+CONFIG_PARTITION_TABLE_OFFSET=0xF000
diff --git a/tools/test_apps/security/secure_boot/pytest_secure_boot.py b/tools/test_apps/security/secure_boot/pytest_secure_boot.py
index c570e8de430..6bd5ae69cd1 100644
--- a/tools/test_apps/security/secure_boot/pytest_secure_boot.py
+++ b/tools/test_apps/security/secure_boot/pytest_secure_boot.py
@@ -80,10 +80,8 @@ def dut_start_secure_app(dut: Dut) -> None:
 # Test secure boot flow.
 # Correctly signed bootloader + correctly signed app should work
 @pytest.mark.esp32c3
-# TODO: [ESP32C5] IDF-10043
-# @pytest.mark.esp32c5
-# TODO: [ESP32C5] IDF-10102
-# @pytest.mark.esp32c61
+@pytest.mark.esp32c5
+@pytest.mark.esp32c61
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
 def test_examples_security_secure_boot(dut: Dut) -> None:
@@ -96,10 +94,8 @@ def test_examples_security_secure_boot(dut: Dut) -> None:
 # Test efuse key index and key block combination.
 # Any key index can be written to any key block and should work
 @pytest.mark.esp32c3
-# TODO: [ESP32C5] IDF-10043
-# @pytest.mark.esp32c5
-# TODO: [ESP32C5] IDF-10102
-# @pytest.mark.esp32c61
+@pytest.mark.esp32c5
+@pytest.mark.esp32c61
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
 # Increasing the test timeout to 1200s as the test runs for 18 iterations
@@ -122,10 +118,8 @@ def test_examples_security_secure_boot_key_combo(dut: Dut) -> None:
 # Test secure boot key revoke.
 # If a key is revoked, bootloader signed with that key should fail verification
 @pytest.mark.esp32c3
-# TODO: [ESP32C5] IDF-10043
-# @pytest.mark.esp32c5
-# TODO: [ESP32C5] IDF-10102
-# @pytest.mark.esp32c61
+@pytest.mark.esp32c5
+@pytest.mark.esp32c61
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
 def test_examples_security_secure_boot_key_revoke(dut: Dut) -> None:
@@ -145,10 +139,8 @@ def test_examples_security_secure_boot_key_revoke(dut: Dut) -> None:
 # Test bootloader signature corruption.
 # Corrupt one byte at a time of bootloader signature and test that the verification fails
 @pytest.mark.esp32c3
-# TODO: [ESP32C5] IDF-10043
-# @pytest.mark.esp32c5
-# TODO: [ESP32C5] IDF-10102
-# @pytest.mark.esp32c61
+@pytest.mark.esp32c5
+@pytest.mark.esp32c61
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
 @pytest.mark.timeout(18000)
@@ -186,10 +178,8 @@ def test_examples_security_secure_boot_corrupt_bl_sig(dut: Dut) -> None:
 # Test app signature corruption.
 # Corrupt app signature, one byte at a time, and test that the verification fails
 @pytest.mark.esp32c3
-# TODO: [ESP32C5] IDF-10043
-# @pytest.mark.esp32c5
-# TODO: [ESP32C5] IDF-10102
-# @pytest.mark.esp32c61
+@pytest.mark.esp32c5
+@pytest.mark.esp32c61
 @pytest.mark.esp32s3
 @pytest.mark.esp32p4
 @pytest.mark.timeout(18000)
diff --git a/tools/test_apps/storage/.build-test-rules.yml b/tools/test_apps/storage/.build-test-rules.yml
index d27c0ab8933..f0ab55097ce 100644
--- a/tools/test_apps/storage/.build-test-rules.yml
+++ b/tools/test_apps/storage/.build-test-rules.yml
@@ -1,5 +1,13 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
 
+tools/test_apps/storage/fatfsgen:
+  depends_components:
+    - fatfs
+    - vfs
+  disable_test:
+    - if: IDF_TARGET != "esp32"
+      reason: only one target needed
+
 tools/test_apps/storage/partition_table_readonly:
   disable_test:
     - if: IDF_TARGET not in ["esp32", "esp32c3"]
diff --git a/examples/storage/fatfsgen/CMakeLists.txt b/tools/test_apps/storage/fatfsgen/CMakeLists.txt
similarity index 100%
rename from examples/storage/fatfsgen/CMakeLists.txt
rename to tools/test_apps/storage/fatfsgen/CMakeLists.txt
diff --git a/examples/storage/fatfsgen/README.md b/tools/test_apps/storage/fatfsgen/README.md
similarity index 100%
rename from examples/storage/fatfsgen/README.md
rename to tools/test_apps/storage/fatfsgen/README.md
diff --git a/examples/storage/fatfsgen/fatfs_image/hello.txt b/tools/test_apps/storage/fatfsgen/fatfs_image/hello.txt
similarity index 100%
rename from examples/storage/fatfsgen/fatfs_image/hello.txt
rename to tools/test_apps/storage/fatfsgen/fatfs_image/hello.txt
diff --git a/examples/storage/fatfsgen/fatfs_image/sub/test.txt b/tools/test_apps/storage/fatfsgen/fatfs_image/sub/test.txt
similarity index 100%
rename from examples/storage/fatfsgen/fatfs_image/sub/test.txt
rename to tools/test_apps/storage/fatfsgen/fatfs_image/sub/test.txt
diff --git a/tools/test_apps/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt b/tools/test_apps/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt
new file mode 100644
index 00000000000..45caad27256
--- /dev/null
+++ b/tools/test_apps/storage/fatfsgen/fatfs_long_name_image/hellolongname.txt
@@ -0,0 +1 @@
+This is generated on the host; long name it has
diff --git a/tools/test_apps/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt b/tools/test_apps/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt
new file mode 100644
index 00000000000..e8c8c6d51ff
--- /dev/null
+++ b/tools/test_apps/storage/fatfsgen/fatfs_long_name_image/sublongnames/testlongfilenames.txt
@@ -0,0 +1 @@
+this is test; long name it has
diff --git a/examples/storage/fatfsgen/main/CMakeLists.txt b/tools/test_apps/storage/fatfsgen/main/CMakeLists.txt
similarity index 100%
rename from examples/storage/fatfsgen/main/CMakeLists.txt
rename to tools/test_apps/storage/fatfsgen/main/CMakeLists.txt
diff --git a/examples/storage/fatfsgen/main/Kconfig.projbuild b/tools/test_apps/storage/fatfsgen/main/Kconfig.projbuild
similarity index 100%
rename from examples/storage/fatfsgen/main/Kconfig.projbuild
rename to tools/test_apps/storage/fatfsgen/main/Kconfig.projbuild
diff --git a/examples/storage/fatfsgen/main/fatfsgen_example_main.c b/tools/test_apps/storage/fatfsgen/main/fatfsgen_example_main.c
similarity index 100%
rename from examples/storage/fatfsgen/main/fatfsgen_example_main.c
rename to tools/test_apps/storage/fatfsgen/main/fatfsgen_example_main.c
diff --git a/tools/test_apps/storage/fatfsgen/partitions_example.csv b/tools/test_apps/storage/fatfsgen/partitions_example.csv
new file mode 100644
index 00000000000..1c79321a107
--- /dev/null
+++ b/tools/test_apps/storage/fatfsgen/partitions_example.csv
@@ -0,0 +1,6 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
+nvs,      data, nvs,     0x9000,  0x6000,
+phy_init, data, phy,     0xf000,  0x1000,
+factory,  app,  factory, 0x10000, 1M,
+storage,  data, fat,     ,        1M,
diff --git a/examples/storage/fatfsgen/pytest_fatfsgen_example.py b/tools/test_apps/storage/fatfsgen/pytest_fatfsgen_example.py
similarity index 100%
rename from examples/storage/fatfsgen/pytest_fatfsgen_example.py
rename to tools/test_apps/storage/fatfsgen/pytest_fatfsgen_example.py
diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen
rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen
diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt
rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_default_dt
diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln
rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln
diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt
rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_only_partition_gen_ln_default_dt
diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen
rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen
diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt
rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_default_dt
diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln
rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln
diff --git a/examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt b/tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt
similarity index 100%
rename from examples/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt
rename to tools/test_apps/storage/fatfsgen/sdkconfig.ci.test_read_write_partition_gen_ln_default_dt
diff --git a/tools/test_apps/storage/fatfsgen/sdkconfig.defaults b/tools/test_apps/storage/fatfsgen/sdkconfig.defaults
new file mode 100644
index 00000000000..47363c32d51
--- /dev/null
+++ b/tools/test_apps/storage/fatfsgen/sdkconfig.defaults
@@ -0,0 +1,4 @@
+CONFIG_PARTITION_TABLE_CUSTOM=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_example.csv"
+CONFIG_PARTITION_TABLE_FILENAME="partitions_example.csv"
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
diff --git a/tools/test_apps/system/.build-test-rules.yml b/tools/test_apps/system/.build-test-rules.yml
index 209d0e98662..c98392018b3 100644
--- a/tools/test_apps/system/.build-test-rules.yml
+++ b/tools/test_apps/system/.build-test-rules.yml
@@ -62,6 +62,15 @@ tools/test_apps/system/memprot:
       temporary: true
       reason: the other targets are not tested yet
 
+tools/test_apps/system/mmu_page_size:
+  enable:
+    - if: IDF_TARGET in ["esp32c6", "esp32h2"]
+      reason: Coverage for two targets with configurable MMU page size is sufficient
+  depends_components:
+    - esp_app_format
+    - bootloader_support
+    - esp_mm
+
 tools/test_apps/system/no_embedded_paths:
   enable:
     - if: IDF_TARGET in ["esp32", "esp32c3", "esp32s2"]
diff --git a/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp b/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp
index cb058d62c06..716e6d4eb0e 100644
--- a/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp
+++ b/tools/test_apps/system/cxx_build_test/main/test_i2c_lcd.cpp
@@ -52,6 +52,7 @@ void test_i2c_lcd_apis(void)
         .trans_queue_depth = 4,
         .flags = {
             .enable_internal_pullup = true,
+            .allow_pd = false,
         }
     };
 
diff --git a/tools/test_apps/system/mmu_page_size/CMakeLists.txt b/tools/test_apps/system/mmu_page_size/CMakeLists.txt
new file mode 100644
index 00000000000..9a2312cf5b7
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/CMakeLists.txt
@@ -0,0 +1,7 @@
+# The following lines of boilerplate have to be in your project's
+# CMakeLists in this exact order for cmake to work correctly
+cmake_minimum_required(VERSION 3.16)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+set(COMPONENTS main)
+project(test_mmu_page_size)
diff --git a/tools/test_apps/system/mmu_page_size/README.md b/tools/test_apps/system/mmu_page_size/README.md
new file mode 100644
index 00000000000..0163e2dec50
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/README.md
@@ -0,0 +1,5 @@
+| Supported Targets | ESP32-C6 | ESP32-H2 |
+| ----------------- | -------- | -------- |
+
+This test app ensures that bootloader can support configurable MMU page size as per the application binary header.
+This test tries to boot the application with different MMU page sizes and checks if the application is able to boot successfully.
diff --git a/tools/test_apps/system/mmu_page_size/conftest.py b/tools/test_apps/system/mmu_page_size/conftest.py
new file mode 100644
index 00000000000..21d1a1145e1
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/conftest.py
@@ -0,0 +1,51 @@
+# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: Apache-2.0
+import logging
+import os
+
+import pytest
+from _pytest.fixtures import FixtureRequest
+from _pytest.monkeypatch import MonkeyPatch
+from pytest_embedded_idf.app import FlashFile
+from pytest_embedded_idf.serial import IdfSerial
+
+
+# This is a custom IdfSerial class to support custom functionality
+# which is required only for this test
+class FlashBootloader(IdfSerial):
+    def bootloader_flash(self, binary_path: str) -> None:
+        """
+        Flash bootloader.
+
+        :return: None
+        """
+        logging.info('Flashing bootloader')
+        bootloader_path = os.path.join(binary_path, 'bootloader', 'bootloader.bin')
+        logging.info(bootloader_path)
+        offs = int(self.app.sdkconfig.get('BOOTLOADER_OFFSET_IN_FLASH', 0))
+        logging.info('bootloader offset is {0}'.format(hex(offs)))
+        prev_flash_files = self.app.flash_files
+        flash_files = []
+        flash_files.append(
+            FlashFile(
+                offs,
+                bootloader_path,
+                False,
+            )
+        )
+        self.app.flash_files = flash_files
+        self.flash()
+        # Restore self.app.flash files to original value
+        self.app.flash_files = prev_flash_files
+
+
+@pytest.fixture(scope='module')
+def monkeypatch_module(request: FixtureRequest) -> MonkeyPatch:
+    mp = MonkeyPatch()
+    request.addfinalizer(mp.undo)
+    return mp
+
+
+@pytest.fixture(scope='module', autouse=True)
+def replace_dut_class(monkeypatch_module: MonkeyPatch) -> None:
+    monkeypatch_module.setattr('pytest_embedded_idf.IdfSerial', FlashBootloader)
diff --git a/tools/test_apps/system/mmu_page_size/main/CMakeLists.txt b/tools/test_apps/system/mmu_page_size/main/CMakeLists.txt
new file mode 100644
index 00000000000..06087b89d56
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/main/CMakeLists.txt
@@ -0,0 +1,2 @@
+idf_component_register(SRCS "main.c"
+                        PRIV_REQUIRES unity esp_partition)
diff --git a/tools/test_apps/system/mmu_page_size/main/main.c b/tools/test_apps/system/mmu_page_size/main/main.c
new file mode 100644
index 00000000000..a820c55c540
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/main/main.c
@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <inttypes.h>
+
+#include "unity.h"
+#include "esp_partition.h"
+
+#define SZ 4096
+
+void app_main(void)
+{
+    printf("App is running\n");
+
+    // Perform some partition and memory map related operations
+    char src_p_1[32] = "Test data pattern 123456789";
+    char buf[32];
+
+    // Find storage partition
+    const esp_partition_t* partition = esp_partition_find_first(
+            ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_FAT, NULL);
+    TEST_ASSERT_NOT_NULL(partition);
+
+    esp_partition_mmap_handle_t handle1;
+    const void *ptr1;
+    TEST_ESP_OK(esp_partition_mmap(partition, 0, SZ, ESP_PARTITION_MMAP_DATA, &ptr1, &handle1));
+    TEST_ESP_OK(esp_partition_erase_range(partition, 0, SZ));
+    TEST_ESP_OK(esp_partition_write(partition, 0, src_p_1, sizeof(src_p_1)));
+    memcpy(buf, ptr1, sizeof(buf));
+
+    TEST_ASSERT_EQUAL(0, memcmp(buf, src_p_1, sizeof(buf)));
+    esp_partition_munmap(handle1);
+
+    printf("Partition test done\n");
+}
diff --git a/tools/test_apps/system/mmu_page_size/partitions.csv b/tools/test_apps/system/mmu_page_size/partitions.csv
new file mode 100644
index 00000000000..5f1296d92dd
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/partitions.csv
@@ -0,0 +1,6 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
+nvs,      data, nvs,     ,        0x6000,
+phy_init, data, phy,     ,        0x1000,
+factory,  app,  factory, ,        1M,
+storage,  data, fat,     ,        64K,
diff --git a/tools/test_apps/system/mmu_page_size/pytest_mmu_page_size.py b/tools/test_apps/system/mmu_page_size/pytest_mmu_page_size.py
new file mode 100644
index 00000000000..cd9eb47db27
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/pytest_mmu_page_size.py
@@ -0,0 +1,52 @@
+# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import os
+
+import pytest
+from artifacts_handler import ArtifactType
+from idf_ci_utils import IDF_PATH
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.generic
+@pytest.mark.parametrize('config', ['32K'], indirect=True)
+def test_app_mmu_page_size_32k_and_bootloader_mmu_page_size_64k(dut: Dut, app_downloader, config) -> None:  # type: ignore
+    dut.expect('App is running')
+
+    assert '32K' in config
+    app_config = config.replace('32K', '64K')
+
+    path_to_mmu_page_size_64k_build = os.path.join(dut.app.app_path, f'build_{dut.target}_{app_config}')
+    if app_downloader:
+        app_downloader.download_app(
+            os.path.relpath(path_to_mmu_page_size_64k_build, IDF_PATH), ArtifactType.BUILD_DIR_WITHOUT_MAP_AND_ELF_FILES
+        )
+
+    dut.serial.bootloader_flash(path_to_mmu_page_size_64k_build)
+    dut.expect('MMU page size mismatch')
+    dut.expect('App is running')
+    dut.expect('Partition test done\n')
+
+
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.generic
+@pytest.mark.parametrize('config', ['64K'], indirect=True)
+def test_app_mmu_page_size_64k_and_bootloader_mmu_page_size_32k(dut: Dut, app_downloader, config) -> None:  # type: ignore
+    dut.expect('App is running')
+
+    assert '64K' in config
+    app_config = config.replace('64K', '32K')
+
+    path_to_mmu_page_size_32k_build = os.path.join(dut.app.app_path, f'build_{dut.target}_{app_config}')
+    if app_downloader:
+        app_downloader.download_app(
+            os.path.relpath(path_to_mmu_page_size_32k_build, IDF_PATH), ArtifactType.BUILD_DIR_WITHOUT_MAP_AND_ELF_FILES
+        )
+
+    dut.serial.bootloader_flash(path_to_mmu_page_size_32k_build)
+    dut.expect('MMU page size mismatch')
+    dut.expect('App is running')
+    dut.expect('Partition test done\n')
diff --git a/tools/test_apps/system/mmu_page_size/sdkconfig.ci.32K b/tools/test_apps/system/mmu_page_size/sdkconfig.ci.32K
new file mode 100644
index 00000000000..d2d45ce8e24
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/sdkconfig.ci.32K
@@ -0,0 +1,2 @@
+# This config option internally select 32KB MMU page size
+CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
diff --git a/tools/test_apps/system/mmu_page_size/sdkconfig.ci.64K b/tools/test_apps/system/mmu_page_size/sdkconfig.ci.64K
new file mode 100644
index 00000000000..f57de8fda29
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/sdkconfig.ci.64K
@@ -0,0 +1,2 @@
+# This config option internally select 64KB MMU page size
+CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
diff --git a/tools/test_apps/system/mmu_page_size/sdkconfig.defaults b/tools/test_apps/system/mmu_page_size/sdkconfig.defaults
new file mode 100644
index 00000000000..4b0421e1aba
--- /dev/null
+++ b/tools/test_apps/system/mmu_page_size/sdkconfig.defaults
@@ -0,0 +1 @@
+CONFIG_PARTITION_TABLE_CUSTOM=y
diff --git a/tools/test_apps/system/panic/CMakeLists.txt b/tools/test_apps/system/panic/CMakeLists.txt
index 3305b7b4f6f..e9db4327f57 100644
--- a/tools/test_apps/system/panic/CMakeLists.txt
+++ b/tools/test_apps/system/panic/CMakeLists.txt
@@ -17,7 +17,7 @@ if(CONFIG_TEST_MEMPROT)
     endif()
 endif()
 
-if(NOT CONFIG_TEST_MEMPROT AND NOT CONFIG_ESP_COREDUMP_CAPTURE_DRAM AND NOT CONFIG_SPIRAM)
+if(NOT CONFIG_TEST_MEMPROT AND NOT CONFIG_ESP_COREDUMP_CAPTURE_DRAM)
     # Enable UBSAN checks
     #
     # shift-base sanitizer is disabled due to the following pattern found in register header files:
diff --git a/tools/test_apps/system/panic/main/include/test_panic.h b/tools/test_apps/system/panic/main/include/test_panic.h
index 71733add77e..32d05126554 100644
--- a/tools/test_apps/system/panic/main/include/test_panic.h
+++ b/tools/test_apps/system/panic/main/include/test_panic.h
@@ -31,7 +31,7 @@ void test_hw_stack_guard_cpu1(void);
 #endif // CONFIG_FREERTOS_UNICORE
 #endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD
 
-#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
 void test_panic_extram_stack_heap(void);
 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
 void test_panic_extram_stack_bss(void);
diff --git a/tools/test_apps/system/panic/main/test_app_main.c b/tools/test_apps/system/panic/main/test_app_main.c
index b55f7de7652..a824e25e5bd 100644
--- a/tools/test_apps/system/panic/main/test_app_main.c
+++ b/tools/test_apps/system/panic/main/test_app_main.c
@@ -95,7 +95,7 @@ void app_main(void)
     HANDLE_TEST(test_name, test_hw_stack_guard_cpu1);
 #endif // CONFIG_FREERTOS_UNICORE
 #endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD
-#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
     HANDLE_TEST(test_name, test_panic_extram_stack_heap);
 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
     HANDLE_TEST(test_name, test_panic_extram_stack_bss);
diff --git a/tools/test_apps/system/panic/main/test_panic.c b/tools/test_apps/system/panic/main/test_panic.c
index 6f58469d826..eafc9daddfe 100644
--- a/tools/test_apps/system/panic/main/test_panic.c
+++ b/tools/test_apps/system/panic/main/test_panic.c
@@ -96,7 +96,7 @@ void test_hw_stack_guard_cpu1(void)
 #endif // CONFIG_FREERTOS_UNICORE
 #endif // CONFIG_ESP_SYSTEM_HW_STACK_GUARD
 
-#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
 
 static void stack_in_extram(void* arg) {
     (void) arg;
@@ -130,7 +130,7 @@ void test_panic_extram_stack_bss(void)
     vTaskDelay(1000);
 }
 #endif
-#endif // ESP_COREDUMP_ENABLE_TO_FLASH && SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+#endif // ESP_COREDUMP_ENABLE_TO_FLASH && FREERTOS_TASK_CREATE_ALLOW_EXT_MEM
 
 
 #if !CONFIG_FREERTOS_UNICORE
diff --git a/tools/test_apps/system/panic/pytest_panic.py b/tools/test_apps/system/panic/pytest_panic.py
index d75f71224fb..4f522488e08 100644
--- a/tools/test_apps/system/panic/pytest_panic.py
+++ b/tools/test_apps/system/panic/pytest_panic.py
@@ -29,6 +29,7 @@
     pytest.mark.esp32c5,
     pytest.mark.esp32c6,
     pytest.mark.esp32h2,
+    pytest.mark.esp32c61,
 ]
 
 TARGETS_RISCV_DUAL_CORE = [
@@ -54,9 +55,8 @@
     pytest.param('coredump_uart_bin_crc', marks=TARGETS_ALL),
     pytest.param('coredump_uart_elf_crc', marks=TARGETS_ALL),
     pytest.param('coredump_flash_custom_stack', marks=TARGETS_RISCV),
-    # TODO: Move esp32c61 to TARGETS_RISCV once Core Dump is supported (IDF-9268)
-    pytest.param('gdbstub', marks=TARGETS_ALL + [pytest.mark.esp32c61]),
-    pytest.param('panic', marks=TARGETS_ALL + [pytest.mark.esp32c61]),
+    pytest.param('gdbstub', marks=TARGETS_ALL),
+    pytest.param('panic', marks=TARGETS_ALL),
 ]
 
 CONFIGS_DUAL_CORE = [
@@ -85,7 +85,6 @@
     pytest.param('coredump_flash_bin_crc', marks=TARGETS_RISCV),
     pytest.param('coredump_uart_bin_crc', marks=TARGETS_RISCV),
     pytest.param('coredump_uart_elf_crc', marks=TARGETS_RISCV),
-    # TODO: Add stack guard support to the ESP32-C61: IDF-9269
     pytest.param('gdbstub', marks=TARGETS_RISCV),
     pytest.param('panic', marks=TARGETS_RISCV),
 ]
@@ -310,7 +309,8 @@ def test_cache_error(dut: PanicTestDut, config: str, test_func_name: str) -> Non
         # Cache error interrupt is not enabled, IDF-1558
         dut.expect_gme('IllegalInstruction')
     elif dut.target in ['esp32', 'esp32s3']:
-        dut.expect_gme('Cache disabled but cached memory region accessed')
+        dut.expect_gme('Cache error')
+        dut.expect_exact('Cache disabled but cached memory region accessed')
     else:
         dut.expect_gme('Cache error')
         dut.expect_exact('Cache access error')
@@ -573,7 +573,7 @@ def test_assert_cache_disabled(
 def cache_error_log_check(dut: PanicTestDut) -> None:
     if dut.is_xtensa:
         if dut.target == 'esp32s3':
-            dut.expect_exact("Guru Meditation Error: Core  / panic'ed (Cache disabled but cached memory region accessed)")
+            dut.expect_exact("Guru Meditation Error: Core  / panic'ed (Cache error)")
             dut.expect_exact('Write back error occurred while dcache tries to write back to flash')
             dut.expect_exact('The following backtrace may not indicate the code that caused Cache invalid access')
         else:
@@ -981,7 +981,7 @@ def test_hw_stack_guard_cpu(dut: PanicTestDut, cpu: int) -> None:
     assert end_addr > start_addr
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='TODO: IDF-8662')
+@pytest.mark.temp_skip_ci(targets=['esp32c5', 'esp32c61'], reason='TODO: IDF-8662 and IDF-9269')
 @pytest.mark.parametrize('config', CONFIGS_HW_STACK_GUARD, indirect=True)
 @pytest.mark.generic
 def test_hw_stack_guard_cpu0(dut: PanicTestDut, config: str, test_func_name: str) -> None:
@@ -990,7 +990,6 @@ def test_hw_stack_guard_cpu0(dut: PanicTestDut, config: str, test_func_name: str
     common_test(dut, config)
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32c5'], reason='TODO: IDF-8662')
 @pytest.mark.parametrize('config', CONFIGS_HW_STACK_GUARD_DUAL_CORE, indirect=True)
 @pytest.mark.generic
 def test_hw_stack_guard_cpu1(dut: PanicTestDut, config: str, test_func_name: str) -> None:
@@ -1037,7 +1036,7 @@ def test_capture_dram(dut: PanicTestDut, config: str, test_func_name: str) -> No
     assert int(dut.gdb_data_eval_expr('g_cd_iram')) == 0x4243
     assert int(dut.gdb_data_eval_expr('g_cd_dram')) == 0x4344
 
-    if dut.target != 'esp32c2':
+    if dut.target not in ['esp32c61', 'esp32c2']:
         assert int(dut.gdb_data_eval_expr('g_rtc_data_var')) == 0x55AA
         assert int(dut.gdb_data_eval_expr('g_rtc_fast_var')) == 0xAABBCCDD
 
diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32
index 26769c3c598..065b49d68b2 100644
--- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32
+++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32
@@ -5,7 +5,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y
 # We need to have the coredump info log
 CONFIG_LOG_DEFAULT_LEVEL_INFO=y
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
 CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y
 CONFIG_ESP_COREDUMP_CAPTURE_DRAM=y
diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s2 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s2
index ad1a91fa811..7c372f58f2c 100644
--- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s2
+++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s2
@@ -5,7 +5,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y
 # We need to have the coredump info log
 CONFIG_LOG_DEFAULT_LEVEL_INFO=y
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
 CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y
 CONFIG_ESP_COREDUMP_CAPTURE_DRAM=y
diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s3 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s3
index 46903a02235..a1533240cb6 100644
--- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s3
+++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_bss_esp32s3
@@ -5,7 +5,7 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y
 # We need to have the coredump info log
 CONFIG_LOG_DEFAULT_LEVEL_INFO=y
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y
 CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y
 CONFIG_ESP_COREDUMP_CAPTURE_DRAM=y
diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32
index 18391318a37..a98716641a9 100644
--- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32
+++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32
@@ -5,5 +5,5 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y
 # We need to have the coredump info log
 CONFIG_LOG_DEFAULT_LEVEL_INFO=y
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y
diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s2 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s2
index 981803c0be2..dddebf12c09 100644
--- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s2
+++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s2
@@ -5,5 +5,5 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y
 # We need to have the coredump info log
 CONFIG_LOG_DEFAULT_LEVEL_INFO=y
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y
diff --git a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s3 b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s3
index ff952817bde..55202118942 100644
--- a/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s3
+++ b/tools/test_apps/system/panic/sdkconfig.ci.coredump_flash_extram_stack_heap_esp32s3
@@ -5,5 +5,5 @@ CONFIG_ESP_COREDUMP_CHECKSUM_SHA256=y
 # We need to have the coredump info log
 CONFIG_LOG_DEFAULT_LEVEL_INFO=y
 CONFIG_SPIRAM=y
-CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
+CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=y
 CONFIG_ESP_COREDUMP_USE_STACK_SIZE=y
diff --git a/tools/test_apps/system/panic/test_panic_util/panic_dut.py b/tools/test_apps/system/panic/test_panic_util/panic_dut.py
index b19b32d5393..ba104f4af80 100644
--- a/tools/test_apps/system/panic/test_panic_util/panic_dut.py
+++ b/tools/test_apps/system/panic/test_panic_util/panic_dut.py
@@ -147,9 +147,15 @@ def _call_espcoredump(
         logging.info('espcoredump output is written to %s', self.coredump_output.name)
 
         self.serial.close()
-        subprocess.check_call(espcoredump_args, stdout=self.coredump_output)
-        self.coredump_output.flush()
-        self.coredump_output.seek(0)
+        try:
+            subprocess.check_call(espcoredump_args, stdout=self.coredump_output, stderr=self.coredump_output)
+        except subprocess.CalledProcessError:
+            self.coredump_output.flush()
+            with open(output_file_name, 'r') as file:
+                logging.error('espcoredump failed with output: %s', file.read())
+            raise
+        finally:
+            self.coredump_output.seek(0)
 
     def process_coredump_uart(
         self, expected: Optional[List[Union[str, re.Pattern]]] = None, wait_reboot: bool = True
diff --git a/tools/test_idf_tools/test_idf_tools.py b/tools/test_idf_tools/test_idf_tools.py
index 1275430ef09..87eab1dee0c 100755
--- a/tools/test_idf_tools/test_idf_tools.py
+++ b/tools/test_idf_tools/test_idf_tools.py
@@ -312,6 +312,19 @@ def test_export_prefer_system_cmake(self):
 
         self.assertNotIn(tool_to_test, output)
 
+    def test_export_with_required_tools_check_skipped(self):
+        self.run_idf_tools_with_error(['export'], assertError=True)
+
+        new_os_environ = os.environ.copy()
+        new_os_environ['IDF_SKIP_TOOLS_CHECK'] = '1'
+        with patch('os.environ', new_os_environ):
+            self.run_idf_tools_with_action(['export'])
+
+            self.run_idf_tools_with_action(['install', OPENOCD])
+            output = self.run_idf_tools_with_action(['export'])
+            self.assertIn('%s/tools/openocd-esp32/%s/openocd-esp32/bin' %
+                          (self.temp_tools_dir, OPENOCD_VERSION), output)
+
 
 # TestUsageUnix tests installed tools on UNIX platforms
 @unittest.skipIf(sys.platform == 'win32', reason='Tools for UNIX differ')
diff --git a/tools/tools.json b/tools/tools.json
index 54b3037af73..7fab2a8ec49 100644
--- a/tools/tools.json
+++ b/tools/tools.json
@@ -605,46 +605,46 @@
       "versions": [
         {
           "linux-amd64": {
-            "sha256": "f8c68541fa38307bc0c0763b7e1e3fe4e943d5d45da07d817a73b492e103b652",
-            "size": 2373094,
-            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20240821/openocd-esp32-linux-amd64-0.12.0-esp32-20240821.tar.gz"
+            "sha256": "e82b0f036dc99244bead5f09a86e91bb2365cbcd1122ac68261e5647942485df",
+            "size": 2398717,
+            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-linux-amd64-0.12.0-esp32-20241016.tar.gz"
           },
           "linux-arm64": {
-            "sha256": "4d6e263d84e447354dc685848557d6c284dda7fe007ee451f729a7edfa7baad7",
-            "size": 2251272,
-            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20240821/openocd-esp32-linux-arm64-0.12.0-esp32-20240821.tar.gz"
+            "sha256": "8f8daf5bd22ec5d2fa9257b0862ec33da18ee677e023fb9a9eb17f74ce208c76",
+            "size": 2271584,
+            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-linux-arm64-0.12.0-esp32-20241016.tar.gz"
           },
           "linux-armel": {
-            "sha256": "9d45679f2c4cf450d5e2350047cf57bb76dde2487d30cebce0a72c9173b5c45b",
-            "size": 2390074,
-            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20240821/openocd-esp32-linux-armel-0.12.0-esp32-20240821.tar.gz"
+            "sha256": "bc9c020ecf20e2000f76cffa44305fd5bc44d2e688ea78cce423399d33f19767",
+            "size": 2414206,
+            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-linux-armel-0.12.0-esp32-20241016.tar.gz"
           },
           "linux-armhf": {
-            "sha256": "7f56d6a0c73e3988891a0781adee4973e6b9ea4bb4584cacb88384cb3db59050",
-            "size": 2232548,
-            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20240821/openocd-esp32-linux-armhf-0.12.0-esp32-20240821.tar.gz"
+            "sha256": "2cd6436465333e998000b1c311d301b295d8ebaa3fb1c9aa9d4393539dc16ec6",
+            "size": 2258623,
+            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-linux-armhf-0.12.0-esp32-20241016.tar.gz"
           },
           "macos": {
-            "sha256": "565c8fabc5f19a6e7a0864a294d74b307eec30b9291d16d3fc90e273f0330cb4",
-            "size": 2485320,
-            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20240821/openocd-esp32-macos-0.12.0-esp32-20240821.tar.gz"
+            "sha256": "02a2dffe801a2d005fa9e614d80ff8173395b2cb0b5d3118d0229d094a9946a7",
+            "size": 2508089,
+            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-macos-0.12.0-esp32-20241016.tar.gz"
           },
           "macos-arm64": {
-            "sha256": "68c5c7cf3d15b9810939a5edabc6ff2c9f4fc32262de91fc292a180bc5cc0637",
-            "size": 2530336,
-            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20240821/openocd-esp32-macos-arm64-0.12.0-esp32-20240821.tar.gz"
+            "sha256": "c382f9e884d6565cb6089bff5f200f4810994667d885f062c3d3c5625a0fa9d6",
+            "size": 2552569,
+            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-macos-arm64-0.12.0-esp32-20241016.tar.gz"
           },
-          "name": "v0.12.0-esp32-20240821",
+          "name": "v0.12.0-esp32-20241016",
           "status": "recommended",
           "win32": {
-            "sha256": "463fc2903ddaf03f86ff50836c5c63cc696550b0446140159eddfd2e85570c5d",
-            "size": 2916409,
-            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20240821/openocd-esp32-win32-0.12.0-esp32-20240821.zip"
+            "sha256": "3b5d615e0a72cc771a45dd469031312d5881c01d7b6bc9edb29b8b6bda8c2e90",
+            "size": 2946244,
+            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-win32-0.12.0-esp32-20241016.zip"
           },
           "win64": {
-            "sha256": "550f57369f1f1f6cc600b5dffa3378fd6164d8ea8db7c567cf41091771f090cb",
-            "size": 2916408,
-            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20240821/openocd-esp32-win64-0.12.0-esp32-20240821.zip"
+            "sha256": "5e7b2fd1947d3a8625f6a11db7a2340cf2f41ff4c61284c022c7d7c32b18780a",
+            "size": 2946244,
+            "url": "https://github.com/espressif/openocd-esp32/releases/download/v0.12.0-esp32-20241016/openocd-esp32-win64-0.12.0-esp32-20241016.zip"
           }
         }
       ]
@@ -863,11 +863,11 @@
       "versions": [
         {
           "any": {
-            "sha256": "a26609b415710f0163d785850c769752717004059c129c472e9a0cbd54e0422c",
-            "size": 3258247,
-            "url": "https://github.com/espressif/esp-rom-elfs/releases/download/20240305/esp-rom-elfs-20240305.tar.gz"
+            "sha256": "921f000164a421c7628fbfee55b173384aafaa51883adc65cd27bf9b0af9e9a9",
+            "size": 3540038,
+            "url": "https://github.com/espressif/esp-rom-elfs/releases/download/20241011/esp-rom-elfs-20241011.tar.gz"
           },
-          "name": "20240305",
+          "name": "20241011",
           "status": "recommended"
         }
       ]